commit 9edf1899bdaccafc60f4b638a68c4fa8669dd154 Author: Jinghao Shi Date: Mon Apr 3 12:52:03 2017 -0400 verilog init diff --git a/verilog/Makefile b/verilog/Makefile new file mode 100644 index 0000000..0dfd6ff --- /dev/null +++ b/verilog/Makefile @@ -0,0 +1,45 @@ +############################################################################### +# +# ICARUS VERILOG & GTKWAVE MAKEFILE +# MADE BY WILLIAM GIBB FOR HACDC +# williamgibb@gmail.com +# +# USE THE FOLLOWING COMMANDS WITH THIS MAKEFILE +# "make check" - compiles your verilog design - good for checking code +# "make simulate" - compiles your design+TB & simulates your design +# "make display" - compiles, simulates and displays waveforms +# +############################################################################### + +#TOOL INPUT +SRC = $(wildcard *.v) $(wildcard *.mif) $(wildcard *.coe) +MODULE_LIST = dot11_modules.list + +TESTBENCH = dot11_tb.v +COMPILER_OUT = dot11.out #COMPILER OUTPUT +SIM_OUT = dot11.vcd + +############################################################################### +# BE CAREFUL WHEN CHANGING ITEMS BELOW THIS LINE +############################################################################### +#TOOLS +COMPILER = iverilog +SIMULATOR = vvp +VIEWER = gtkwave + +#TOOL OPTIONS +COMPILER_FLAGS = -v -c $(MODULE_LIST) -o $(COMPILER_OUT) -DDEBUG_PRINT +SIMULATOR_FLAGS = -v -n +############################################################################### + +#MAKE DIRECTIVES +compile: $(TESTBENCH) $(SRC) + $(COMPILER) $(COMPILER_FLAGS) $(TESTBENCH) + +simulate: compile + $(SIMULATOR) $(SIMULATOR_FLAGS) $(COMPILER_OUT) + +clean: + rm -rfv $(COMPILER_OUT) $(SIM_OUT) + +.PHONY: clean diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/ASYNC_FIFO_V5_1.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/ASYNC_FIFO_V5_1.v new file mode 100644 index 0000000..f6825e9 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/ASYNC_FIFO_V5_1.v @@ -0,0 +1,764 @@ +/****************************************************************************** + * + * $RCSfile: ASYNC_FIFO_V5_1.v,v $ $Revision: 1.15 $ $Date: 2008/09/08 20:05:11 $ + * + ****************************************************************************** + * + * Asynchronous FIFO V5_1 - Verilog Behavioral Model + * + ****************************************************************************** + * + * Filename: ASYNC_FIFO_V5_1.v + * + * Description: + * The behavioral model for the asynchronous fifo. + * + ******************************************************************************/ + +// Copyright(C) 2003 by Xilinx, Inc. All rights reserved. +// This text/file contains proprietary, confidential +// information of Xilinx, Inc., is distributed under license +// from Xilinx, Inc., and may be used, copied and/or +// disclosed only pursuant to the terms of a valid license +// agreement with Xilinx, Inc. Xilinx hereby grants you +// a license to use this text/file solely for design, simulation, +// implementation and creation of design files limited +// to Xilinx devices or technologies. Use with non-Xilinx +// devices or technologies is expressly prohibited and +// immediately terminates your license unless covered by +// a separate agreement. +// +// Xilinx is providing this design, code, or information +// "as is" solely for use in developing programs and +// solutions for Xilinx devices. By providing this design, +// code, or information as one possible implementation of +// this feature, application or standard, Xilinx is making no +// representation that this implementation is free from any +// claims of infringement. You are responsible for +// obtaining any rights you may require for your implementation. +// Xilinx expressly disclaims any warranty whatsoever with +// respect to the adequacy of the implementation, including +// but not limited to any warranties or representations that this +// implementation is free from claims of infringement, implied +// warranties of merchantability or fitness for a particular +// purpose. +// +// Xilinx products are not intended for use in life support +// appliances, devices, or systems. Use in such applications are +// expressly prohibited. +// +// This copyright and support notice must be retained as part +// of this text at all times. (c) Copyright 1995-2003 Xilinx, Inc. +// All rights reserved. + + +`timescale 1ns/10ps + + +/****************************************************************************** + * Declare top-level module + ******************************************************************************/ +module ASYNC_FIFO_V5_1 (DIN, WR_EN, WR_CLK, RD_EN, RD_CLK, AINIT, DOUT, + FULL, EMPTY, ALMOST_FULL, ALMOST_EMPTY, + WR_COUNT, RD_COUNT, RD_ACK, RD_ERR, WR_ACK, WR_ERR); + + +/************************************************************************* + * Definition of Ports + * DIN : Input data bus for the fifo. + * DOUT : Output data bus for the fifo. + * AINIT : Asynchronous Reset for the fifo. + * WR_EN : Write enable signal. + * WR_CLK : Write Clock. + * FULL : Indicates a full condition in the FIFO. Full is asserted + * when no more words can be written into the FIFO. + * ALMOST_FULL : Indicates that the FIFO only has room for one additional + * word to be written before it is full. + * WR_ACK : Acknowledgement of a successful write on the + * previous clock edge + * WR_ERR : The write operation on the previous clock edge was + * unsuccessful due to an overflow condition + * WR_COUNT : Number of data words in fifo(synchronous to WR_CLK) + * This is only the MSBs of the count value. + * RD_EN : Read enable signal. + * RD_CLK : Read Clock. + * EMPTY : Indicates an empty condition in the FIFO. Empty is + * asserted when no more words can be read from the FIFO. + * ALMOST_EMPTY: Indicates that the FIFO only has one word remaining + * in the FIFO. One additional read will cause an + * EMPTY condition. + * RD_ACK : Acknowledgement of a successful read on the + * previous clock edge + * RD_ERR : The read operation on the previous clock edge was + * unsuccessful due to an underflow condition + * RD_COUNT : Number of data words in fifo(synchronous to RD_CLK) + * This is only the MSBs of the count value. + *************************************************************************/ + + +//Declare user parameters and their defaults +parameter C_DATA_WIDTH = 8; +parameter C_ENABLE_RLOCS = 0; +parameter C_FIFO_DEPTH = 511; +parameter C_HAS_ALMOST_EMPTY = 1; +parameter C_HAS_ALMOST_FULL = 1; +parameter C_HAS_RD_ACK = 1; +parameter C_HAS_RD_COUNT = 1; +parameter C_HAS_RD_ERR = 1; +parameter C_HAS_WR_ACK = 1; +parameter C_HAS_WR_COUNT = 1; +parameter C_HAS_WR_ERR = 1; +parameter C_RD_ACK_LOW = 0; +parameter C_RD_COUNT_WIDTH = 2; +parameter C_RD_ERR_LOW = 0; +parameter C_USE_BLOCKMEM = 1; +parameter C_WR_ACK_LOW = 0; +parameter C_WR_COUNT_WIDTH = 2; +parameter C_WR_ERR_LOW = 0; + +//Declare input and output ports +input [C_DATA_WIDTH-1 : 0] DIN; +input WR_EN; +input WR_CLK; +input RD_EN; +input RD_CLK; +input AINIT; +output [C_DATA_WIDTH-1 : 0] DOUT; +output FULL; +output EMPTY; +output ALMOST_FULL; +output ALMOST_EMPTY; +output [C_WR_COUNT_WIDTH-1 : 0] WR_COUNT; +output [C_RD_COUNT_WIDTH-1 : 0] RD_COUNT; +output RD_ACK; +output RD_ERR; +output WR_ACK; +output WR_ERR; + +/************************************************************************* + * Parameters used as constants + *************************************************************************/ +//length of the linked list which will simulate a FIFO +parameter listlength = C_FIFO_DEPTH*(C_DATA_WIDTH+1); + +/************************************************************************* + * Internal regs (for always blocks) and wires (for assign statements) + *************************************************************************/ + +//Linked list to be used as an ideal FIFO +reg [listlength:0] list; + + +//pulse asserted at posedge of WR_CLK +reg wr_pulse; + +//pulse asserted at posedge of RD_CLK +reg rd_pulse; + + +//pulse asserted at conclusion of write operation +reg wr_pulse_ack; + +//pulse asserted at conclusion of read operation +reg rd_pulse_ack; + + +//Special ideal FIFO signals +reg [C_DATA_WIDTH-1:0] ideal_dout; +reg ideal_wr_ack; +reg ideal_rd_ack; +reg ideal_wr_err; +reg ideal_rd_err; +reg ideal_full; +reg ideal_empty; +reg ideal_almost_full; +reg ideal_almost_empty; + + +//Integer value for the number of words in the FIFO +reg [31 : 0] ideal_wr_count_tmp; +reg [31 : 0] ideal_rd_count_tmp; + +//Integer value representing the MSBs of the counts +reg [31 : 0] ideal_wr_count_int; +reg [31 : 0] ideal_rd_count_int; + +//MSBs of the counts +reg [C_WR_COUNT_WIDTH-1 : 0] ideal_wr_count; +reg [C_RD_COUNT_WIDTH-1 : 0] ideal_rd_count; + + +/************************************************************************* + * binary : + * Calculates how many bits are needed to represent the input number + *************************************************************************/ + function [31:0] binary; + input [31:0] inval; + integer power; + integer bits; + begin + power = 1; + bits = 0; + while (power <= inval) + begin + power = power * 2; + bits = bits + 1; + end //while + binary = bits; + end + endfunction //binary + +/************************************************************************ + * listsize: + * Returns number of entries in the linked list + *************************************************************************/ + function [31:0] listsize; + input [((C_DATA_WIDTH+1)*C_FIFO_DEPTH):0] inarray; + reg condition; + integer i; + integer j; + begin + condition = 1'b0; + i = 0; + j = 0; + while (condition == 1'b0) + begin + j = (C_DATA_WIDTH+1)*i; + if(inarray[j] == 1'b0) + condition = 1'b1; + i = i + 1; + end //while + listsize = (i-1); + end + endfunction //listsize + +/************************************************************************ + * addlist : + * Add an entry to the end of the linked list + *************************************************************************/ + function [((C_DATA_WIDTH+1)*C_FIFO_DEPTH):0] addlist; + input [((C_DATA_WIDTH+1)*C_FIFO_DEPTH):0] inarray; + input [C_DATA_WIDTH-1:0] inword; + reg [((C_DATA_WIDTH+1)*C_FIFO_DEPTH):0] temp; + integer i; + integer j; + begin + temp = 1'b0; + i = listsize(inarray); + j = (i*(C_DATA_WIDTH+1)); + temp[C_DATA_WIDTH:0] = {inword, 1'b1}; + temp = temp << j; + addlist = temp | inarray; + end + endfunction //addlist + +/************************************************************************ + * readlist : + * Non-destructive read from the head of the linked list + *************************************************************************/ + function [C_DATA_WIDTH-1:0] readlist; + input [((C_DATA_WIDTH+1)*C_FIFO_DEPTH):0] inarray; + begin + readlist = inarray[C_DATA_WIDTH:1]; + end + endfunction //readlist + +/************************************************************************ + * removelist : + * Remove/Delete entry from head of the linked list + *************************************************************************/ + function [((C_DATA_WIDTH+1)*C_FIFO_DEPTH):0] removelist; + input [((C_DATA_WIDTH+1)*C_FIFO_DEPTH):0] inarray; + begin + removelist = inarray >> (C_DATA_WIDTH+1); + end + endfunction //removelist + + +/************************************************************************* + * Initialize Signals + *************************************************************************/ + initial + begin + list = 0; + wr_pulse = 1'b0; + rd_pulse = 1'b0; + wr_pulse_ack = 1'b0; + rd_pulse_ack = 1'b0; + + ideal_dout = 0; + ideal_wr_ack = 1'b0; + ideal_rd_ack = 1'b0; + ideal_wr_err = 1'b0; + ideal_rd_err = 1'b0; + ideal_full = 1'b1; + ideal_empty = 1'b1; + ideal_almost_full = 1'b1; + ideal_almost_empty = 1'b1; + ideal_wr_count = 0; + ideal_rd_count = 0; + end + + +/************************************************************************* + * Assign Internal ideal signals to output ports + *************************************************************************/ +assign DOUT = ideal_dout; +assign FULL = ideal_full; +assign EMPTY = ideal_empty; +assign ALMOST_FULL = ideal_almost_full; +assign ALMOST_EMPTY = ideal_almost_empty; +assign WR_COUNT = ideal_wr_count; +assign RD_COUNT = ideal_rd_count; + +//Handshaking signals can be active low, depending on _LOW parameters +assign WR_ACK = ideal_wr_ack ? !C_WR_ACK_LOW : C_WR_ACK_LOW; +assign WR_ERR = ideal_wr_err ? !C_WR_ERR_LOW : C_WR_ERR_LOW; +assign RD_ACK = ideal_rd_ack ? !C_RD_ACK_LOW : C_RD_ACK_LOW; +assign RD_ERR = ideal_rd_err ? !C_RD_ERR_LOW : C_RD_ERR_LOW; + + +/************************************************************************* + * Generate read and write pulse signals + * + * These pulses are instantaneous pulses which occur only in delta-time, + * and are never active for any amount of simulation time. + * + * The pulses handshake with each other and the wr_pulse_ack and rd_pulse_ack + * signals to guarantee that they can never occur at the same time, and + * to guarantee that a write or read operation completes before the other + * can begin. + *************************************************************************/ + +/********wr_pulse generator*************/ + always @(posedge WR_CLK) + begin : gen_wr_pulse + //Wait until rd_pulse is 0 before setting the wr_pulse + // to make sure that they can't BOTH be active simultaneously. + wait (!rd_pulse && !rd_pulse_ack) + wr_pulse = 1'b1; + + //Wait until read/write always block replies before clearing wr_pulse + wait (wr_pulse_ack) + wr_pulse = 1'b0; + + end // wr_pulse generator + + +/********rd_pulse generator*************/ + always @(posedge RD_CLK) + begin : gen_rd_pulse + //Wait until wr_pulse is 0 before setting the rd_pulse + // to make sure that they can't BOTH be active simultaneously. + wait (!wr_pulse && !wr_pulse_ack) + rd_pulse = 1'b1; + + //Wait until read/write always block replies before clearing rd_pulse + wait (rd_pulse_ack) + rd_pulse = 1'b0; + + end // rd_pulse generator + + + +/************************************************************************* + * Read and Write from FIFO (FIFO is implemented by a linked list) + * + * The following are the possible scenarios for the FIFO: + * + * 1) AINIT=1, in which case a reset condition occurs, all outputs and + * internal states are cleared, and the triggering pulse is cleared. + * + * 2) This process was triggered with ONLY a wr_pulse, rd_pulse is 0. + * This is a normal case. Only a write operation is performed. + * + * 3) This process was triggered with ONLY a rd_pulse, wr_pulse is 0. + * This is a normal case. Only a read operation is performed. + * + * 4) This process was triggered with ONLY a wr_pulse, but rd_pulse is also 1. + * The pulse generator processes (above) require that one pulse be cleared + * before the other can be activated. This should prevent this case from + * occurring. + * + * 5) This process was triggered with ONLY a rd_pulse, but wr_pulse is also 1. + * The pulse generator processes (above) require that one pulse be cleared + * before the other can be activated. This should prevent this case from + * occurring. + * + * 6) This process was triggered with BOTH a wr_pulse and a rd_pulse + * simultaneously, and was only triggerred once. It was found through + * experimentation that this case is actually possible. + * This case is handled explicitly below as an error. + * Handshaking between pulse generation processes, and the requirement + * that a rd_pulse_ack or wr_pulse_ack must be asserted before continuing + * should prevent this from occuring. + *************************************************************************/ + + always @(posedge wr_pulse or posedge rd_pulse or posedge AINIT) + begin : gen_fifo + + /****** Reset fifo (case 1)***************************************/ + if (AINIT == 1'b1) + begin + list <= 0; + ideal_dout <= 0; + ideal_wr_ack <= 1'b0; + ideal_rd_ack <= 1'b0; + ideal_wr_err <= 1'b0; + ideal_rd_err <= 1'b0; + ideal_full <= 1'b1; + ideal_almost_full <= 1'b1; + ideal_empty <= 1'b1; + ideal_almost_empty <= 1'b1; + ideal_wr_count <= 0; + ideal_rd_count <= 0; + + //If either pulse is set, acknowledge and clear it + if ((wr_pulse == 1'b1) && (rd_pulse == 1'b1)) + $display ("ERROR: Illegal operation internal to async_fifo_v5_1 Verilog model."); + + if (wr_pulse == 1'b1) + begin + wr_pulse_ack = 1'b1; + wait (!wr_pulse) + wr_pulse_ack = 1'b0; + end + + if (rd_pulse == 1'b1) + begin + rd_pulse_ack = 1'b1; + wait (!rd_pulse) + rd_pulse_ack = 1'b0; + end + + + end // if (AINIT == 1'b1) + + + else //AINIT == 1'b0 + + begin + + /*********** Error: read AND write to the fifo (case 5) ********/ + if ((wr_pulse == 1'b1) && (rd_pulse == 1'b1)) + $display ("ERROR: Illegal operation internal to async_fifo_v5_1 Verilog model."); + + /****** Write operation (case 2) *******************************/ + if (wr_pulse == 1'b1) + begin + //If this is a write, handle the write by adding the value + // to the linked list, and updating all outputs appropriately + if (WR_EN == 1'b1) + begin + + //If the FIFO is completely empty, but we are + // successfully writing to it + if (listsize(list) == 0) + begin + //Add value on DIN port to linked list + list = addlist(list,DIN); + //Write successful, so issue acknowledge + // and no error + ideal_wr_ack = 1'b1; + ideal_wr_err = 1'b0; + //Not even close to full. + ideal_full = 1'b0; + ideal_almost_full = 1'b0; + //Writing, so not empty. + ideal_empty = 1'b0; + // Will still be almost empty after 1 write + ideal_almost_empty = 1'b1; + + ideal_wr_count_tmp = listsize(list); + ideal_wr_count_int = (listsize(list) << C_WR_COUNT_WIDTH) / (C_FIFO_DEPTH + 1); + ideal_wr_count = ideal_wr_count_int[C_WR_COUNT_WIDTH-1:0]; + end //(listsize(list) == 0) + + //If the FIFO is not close to being full, and not empty + else if ((listsize(list) < C_FIFO_DEPTH-2) && (listsize(list)>=1)) + begin + //Add value on DIN port to linked list + list = addlist(list,DIN); + //Write successful, so issue acknowledge + // and no error + ideal_wr_ack = 1'b1; + ideal_wr_err = 1'b0; + //Not even close to full. + ideal_full = 1'b0; + ideal_almost_full = 1'b0; + //not close to empty + ideal_empty = 1'b0; + //Was not empty, so this write will make FIFO + // no longer almost_empty + ideal_almost_empty = 1'b0; + + ideal_wr_count_tmp = listsize(list); + ideal_wr_count_int = (listsize(list) << C_WR_COUNT_WIDTH) / (C_FIFO_DEPTH + 1); + ideal_wr_count = ideal_wr_count_int[C_WR_COUNT_WIDTH-1:0]; + end // if + + //If the FIFO is 2 from full + else if (listsize(list) == C_FIFO_DEPTH-2) + begin + //Add value on DIN port to linked list + list = addlist(list,DIN); + //Write successful, so issue acknowledge + // and no error + ideal_wr_ack = 1'b1; + ideal_wr_err = 1'b0; + //Still 2 from full + ideal_full = 1'b0; + //2 from full, and writing, so set almost_full + ideal_almost_full = 1'b1; + //not even close to empty + ideal_empty = 1'b0; + ideal_almost_empty = 1'b0; + + ideal_wr_count_tmp = listsize(list); + ideal_wr_count_int = (listsize(list) << C_WR_COUNT_WIDTH) / (C_FIFO_DEPTH + 1); + ideal_wr_count = ideal_wr_count_int[C_WR_COUNT_WIDTH-1:0]; + end // if (listsize(list) == C_FIFO_DEPTH-2) + + //If the FIFO is one from full + else if (listsize(list) == C_FIFO_DEPTH-1) + begin + //Add value on DIN port to linked list + list = addlist(list,DIN); + //Write successful, so issue acknowledge + // and no error + ideal_wr_ack = 1'b1; + ideal_wr_err = 1'b0; + //This write is CAUSING the FIFO to go full + ideal_full = 1'b1; + ideal_almost_full = 1'b1; + //Not even close to empty + ideal_empty = 1'b0; + ideal_almost_empty = 1'b0; + + ideal_wr_count_tmp = listsize(list); + ideal_wr_count_int = (listsize(list) << C_WR_COUNT_WIDTH) / (C_FIFO_DEPTH + 1); + ideal_wr_count = ideal_wr_count_int[C_WR_COUNT_WIDTH-1:0]; + end // if (listsize(list) == C_FIFO_DEPTH-1) + + //If the FIFO is full, do NOT perform the write, + // update flags accordingly + else if (listsize(list) >= C_FIFO_DEPTH) + begin + //write unsuccessful - do not change contents + list = list; + //Do not acknowledge the write + ideal_wr_ack = 1'b0; + //throw an overflow error + ideal_wr_err = 1'b1; + //Reminder that FIFO is still full + ideal_full = 1'b1; + ideal_almost_full = 1'b1; + //Not even close to empty + ideal_empty = 1'b0; + ideal_almost_empty = 1'b0; + + ideal_wr_count_tmp = listsize(list); + ideal_wr_count_int = (listsize(list) << C_WR_COUNT_WIDTH) / (C_FIFO_DEPTH + 1); + ideal_wr_count = ideal_wr_count_int[C_WR_COUNT_WIDTH-1:0]; + end + end //(WR_EN == 1'b1) + + else //if (WR_EN == 1'b0) + begin + //If user did not attempt a write, then do not + // give ack or err + ideal_wr_ack = 1'b0; + ideal_wr_err = 1'b0; + + //Implied statements: + //ideal_empty = ideal_empty; + //ideal_almost_empty = ideal_almost_empty; + + //Check for full + if (listsize(list) > C_FIFO_DEPTH-1) + ideal_full = 1'b1; + else + ideal_full = 1'b0; + + //Check for almost_full + if (listsize(list) > C_FIFO_DEPTH-2) + ideal_almost_full = 1'b1; + else + ideal_almost_full = 1'b0; + + + ideal_wr_count_tmp = listsize(list); + ideal_wr_count_int = (listsize(list) << C_WR_COUNT_WIDTH) / (C_FIFO_DEPTH + 1); + ideal_wr_count = ideal_wr_count_int[C_WR_COUNT_WIDTH-1:0]; + end + + + //Whether it was a write or not, clear the pulse + wr_pulse_ack = 1'b1; + wait (!wr_pulse) + wr_pulse_ack = 1'b0; + end + + + /****** Read operation (case 3) **********************************/ + if (rd_pulse == 1'b1) + begin + //If this is a read, handle the read by popping the value off the linked list + if (RD_EN == 1'b1) + begin + + //If the FIFO is completely empty + if (listsize(list) <= 0) + begin + //Do not change the contents of the FIFO + list = list; + //Read nothing (0) from the empty FIFO + ideal_dout = 0; + //Do not acknowledge the read from empty FIFO + ideal_rd_ack = 1'b0; + //Throw an underflow error + ideal_rd_err = 1'b1; + //Not even close to full + ideal_full = 1'b0; + ideal_almost_full = 1'b0; + //Reminder that FIFO is still empty + ideal_empty = 1'b1; + ideal_almost_empty = 1'b1; + + ideal_rd_count_tmp = listsize(list); + ideal_rd_count_int = (listsize(list) << C_RD_COUNT_WIDTH) / (C_FIFO_DEPTH + 1); + ideal_rd_count = ideal_rd_count_int[C_RD_COUNT_WIDTH-1:0]; + end // if (listsize(list) <= 0) + + //If the FIFO is one from empty + else if (listsize(list) == 1) + begin + //Read top value from the FIFO + ideal_dout = readlist(list); + //Pop single value off of linked list + list = removelist(list); + //Acknowledge the read from the FIFO, no error + ideal_rd_ack = 1'b1; + ideal_rd_err = 1'b0; + //Not even close to full + ideal_full = 1'b0; + ideal_almost_full = 1'b0; + //Note that FIFO is GOING empty + ideal_empty = 1'b1; + ideal_almost_empty = 1'b1; + + ideal_rd_count_tmp = listsize(list); + ideal_rd_count_int = (listsize(list) << C_RD_COUNT_WIDTH) / (C_FIFO_DEPTH + 1); + ideal_rd_count = ideal_rd_count_int[C_RD_COUNT_WIDTH-1:0]; + end // if (listsize(list) == 1) + + //If the FIFO is two from empty + else if (listsize(list) == 2) + begin + //Read top value from the FIFO + ideal_dout = readlist(list); + //Pop single value off of linked list + list = removelist(list); + //Acknowledge the read from the FIFO, no error + ideal_rd_ack = 1'b1; + ideal_rd_err = 1'b0; + //Not even close to full + ideal_full = 1'b0; + ideal_almost_full = 1'b0; + //Fifo is not yet empty + ideal_empty = 1'b0; + //2 from empty and reading, so going almost_empty + ideal_almost_empty = 1'b1; + + ideal_rd_count_tmp = listsize(list); + ideal_rd_count_int = (listsize(list) << C_RD_COUNT_WIDTH) / (C_FIFO_DEPTH + 1); + ideal_rd_count = ideal_rd_count_int[C_RD_COUNT_WIDTH-1:0]; + end // if (listsize(list) == 2) + + //If the FIFO is not close to being empty + else if ((listsize(list) > 2) && (listsize(list)<=C_FIFO_DEPTH-1)) + begin + //Read top value from the FIFO + ideal_dout = readlist(list); + //Pop single value off of linked list + list = removelist(list); + //Acknowledge the read from the FIFO, no error + ideal_rd_ack = 1'b1; + ideal_rd_err = 1'b0; + //Reading, so not FULL + ideal_full = 1'b0; + //At least one from full AND reading, so no longer almost_full + ideal_almost_full = 1'b0; + //Not close to empty + ideal_empty = 1'b0; + ideal_almost_empty = 1'b0; + + ideal_rd_count_tmp = listsize(list); + ideal_rd_count_int = (listsize(list) << C_RD_COUNT_WIDTH) / (C_FIFO_DEPTH + 1); + ideal_rd_count = ideal_rd_count_int[C_RD_COUNT_WIDTH-1:0]; + end // if ((listsize(list) > 2) && (listsize(list)<=C_FIFO_DEPTH-1)) + + //If the FIFO is completely full, and we are successfully reading from it + else if (listsize(list) == C_FIFO_DEPTH) + begin + //Read top value from the FIFO + ideal_dout = readlist(list); + //Pop single value off of linked list + list = removelist(list); + //Acknowledge the read from the FIFO, no error + ideal_rd_ack = 1'b1; + ideal_rd_err = 1'b0; + //Reading, so not FULL + ideal_full = 1'b0; + //Was just full, and this is only the first read + ideal_almost_full = 1'b1; + //Not close to empty + ideal_empty = 1'b0; + ideal_almost_empty = 1'b0; + + ideal_rd_count_tmp = listsize(list); + ideal_rd_count_int = (listsize(list) << C_RD_COUNT_WIDTH) / (C_FIFO_DEPTH + 1); + ideal_rd_count = ideal_rd_count_int[C_RD_COUNT_WIDTH-1:0]; + end // if (listsize(list) == C_FIFO_DEPTH) + + end //(RD_EN == 1'b1) + + else //if (RD_EN == 1'b0) + begin + //If user did not attempt a read, do not give an ack or err + ideal_rd_ack = 1'b0; + ideal_rd_err = 1'b0; + + //Check for empty + if (listsize(list) < 1) + ideal_empty = 1'b1; + else + ideal_empty = 1'b0; + + //Check for almost_empty + if (listsize(list) < 2) + ideal_almost_empty = 1'b1; + else + ideal_almost_empty = 1'b0; + + //Implied statements: + //ideal_full = ideal_full; + //ideal_almost_full =ideal_almost_full; + + + ideal_rd_count_tmp = listsize(list); + ideal_rd_count_int = (listsize(list) << C_RD_COUNT_WIDTH) / (C_FIFO_DEPTH + 1); + ideal_rd_count = ideal_rd_count_int[C_RD_COUNT_WIDTH-1:0]; + end // else: !if(RD_EN == 1'b1) + + + //Whether it was a read or not, clear the pulse + rd_pulse_ack = 1'b1; + wait (!rd_pulse) + rd_pulse_ack = 1'b0; + end // if (rd_pulse == 1'b1) + + end // else: !if(AINIT == 1'b1) + end // block: gen_fifo + +endmodule // ASYNC_FIFO_V5_1 diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/BLKMEMDP_V4_0.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/BLKMEMDP_V4_0.v new file mode 100644 index 0000000..37b3aaa --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/BLKMEMDP_V4_0.v @@ -0,0 +1,1179 @@ +/************************************************************************** + * $Id: BLKMEMDP_V4_0.v,v 1.17 2008/09/08 20:06:20 akennedy Exp $ + ************************************************************************** + * Dual Port Block Memory - Verilog Behavioral Model + * ************************************************************************ + * + * + * This File is owned and controlled by Xilinx and must be used solely + * for design, simulation, implementation and creation of design files + * limited to Xilinx devices or technologies. Use with non-Xilinx + * devices or technologies is expressly prohibited and immediately + * terminates your license. + * + * Xilinx products are not intended for use in life support + * appliances, devices, or systems. Use in such applications is + * expressly prohibited. + * + * **************************** + * ** Copyright Xilinx, Inc. ** + * ** All rights reserved. ** + * **************************** + * + * + ************************************************************************* + * Filename: BLKMEMDP_V4_0.v + * + * Description: The Verilog behavioral model for the Dual Port Block Memory + * + * *********************************************************************** + */ + +`timescale 1ns/10ps +`celldefine + + +`define c_dp_rom 4 +`define c_dp_ram 2 +`define c_write_first 0 +`define c_read_first 1 +`define c_no_change 2 + +module BLKMEMDP_V4_0(DOUTA, DOUTB, ADDRA, CLKA, DINA, ENA, SINITA, WEA, NDA, RFDA, RDYA, ADDRB, CLKB, DINB, ENB, SINITB, WEB,NDB, RFDB, RDYB); + + + + parameter c_addra_width = 11 ; + parameter c_addrb_width = 9 ; + parameter c_default_data = "0"; // indicates string of hex characters used to initialize memory + parameter c_depth_a = 2048 ; + parameter c_depth_b = 512 ; + parameter c_enable_rlocs = 0 ; // core includes placement constraints + parameter c_has_default_data = 1; + parameter c_has_dina = 1 ; // indicate port A has data input pins + parameter c_has_dinb = 1 ; // indicate port B has data input pins + parameter c_has_douta = 1 ; // indicates port A has output + parameter c_has_doutb = 1 ; // indicates port B has output + parameter c_has_ena = 1 ; // indicates port A has a ENA pin + parameter c_has_enb = 1 ; // indicates port B has a ENB pin + parameter c_has_limit_data_pitch = 1 ; + parameter c_has_nda = 0 ; // Port A has a new data pin + parameter c_has_ndb = 0 ; // Port B has a new data pin + parameter c_has_rdya = 0 ; // Port A has result ready pin + parameter c_has_rdyb = 0 ; // Port B has result ready pin + parameter c_has_rfda = 0 ; // Port A has ready for data pin + parameter c_has_rfdb = 0 ; // Port B has ready for data pin + parameter c_has_sinita = 1 ; // indicates port A has a SINITA pin + parameter c_has_sinitb = 1 ; // indicates port B has a SINITB pin + parameter c_has_wea = 1 ; // indicates port A has a WEA pin + parameter c_has_web = 1 ; // indicates port B has a WEB pin + parameter c_limit_data_pitch = 16 ; + parameter c_mem_init_file = "null.mif"; // controls which .mif file used to initialize memory + parameter c_pipe_stages_a = 0 ; // indicates the number of pipe stages needed in port A + parameter c_pipe_stages_b = 0 ; // indicates the number of pipe stages needed in port B + parameter c_reg_inputsa = 0 ; // indicates we, addr, and din of port A are registered + parameter c_reg_inputsb = 0 ; // indicates we, addr, and din of port B are registered + parameter c_sinita_value = "0000"; // indicates string of hex used to initialize A output registers + parameter c_sinitb_value = "0000"; // indicates string of hex used to initialize B output resisters + parameter c_width_a = 8 ; + parameter c_width_b = 32 ; + parameter c_write_modea = 2; // controls which write modes shall be used + parameter c_write_modeb = 2; // controls which write modes shall be used + + // New Generics for Primitive Selection and Pin Polarity + parameter c_ybottom_addr = "1024"; + parameter c_yclka_is_rising = 1; // controls the active edge of the CLKA Pin + parameter c_yclkb_is_rising = 1; // controls the active edge of the CLKB Pin + parameter c_yena_is_high = 1; // controls the polarity of the ENA Pin + parameter c_yenb_is_high = 1; // controls the polarity of the ENB Pin + parameter c_yhierarchy = "hierarchy1"; + parameter c_ymake_bmm = 0; + parameter c_yprimitive_type = "4kx4"; // Indicates which primitive should be used to build the + // memory if c_yuse_single_primitive=1 + parameter c_ysinita_is_high = 1; // controls the polarity of the SINITA Pin + parameter c_ysinitb_is_high = 1; // controls the polarity of the SINITB Pin + parameter c_ytop_addr = "0"; + parameter c_yuse_single_primitive = 0; // controls whether the Memory is build out of a + // user selected primitive or is built from multiple + // primitives with the "optimize for area" algorithm used + parameter c_ywea_is_high = 1; // controls the polarity of the WEA Pin + parameter c_yweb_is_high = 1; // controls the polarity of the WEB Pin + + +// IO ports + + + + output [c_width_a-1:0] DOUTA; + + input [c_addra_width-1:0] ADDRA; + input [c_width_a-1:0] DINA; + input ENA, CLKA, WEA, SINITA, NDA; + output RFDA, RDYA; + + output [c_width_b-1:0] DOUTB; + + input [c_addrb_width-1:0] ADDRB; + input [c_width_b-1:0] DINB; + input ENB, CLKB, WEB, SINITB, NDB; + output RFDB, RDYB; + + +// internal signals + + reg [c_width_a-1:0] douta_mux_out ; // output of multiplexer -- + wire [c_width_a-1:0] DOUTA = douta_mux_out; + reg RFDA, RDYA ; + + reg [c_width_b-1:0] doutb_mux_out ; // output of multiplexer -- + wire [c_width_b-1:0] DOUTB = doutb_mux_out; + reg RFDB, RDYB; + + + reg [c_width_a-1:0] douta_out_q; // registered output of douta_out + reg [c_width_a-1:0] doa_out; // output of Port A RAM + reg [c_width_a-1:0] douta_out; // output of pipeline mux for port A + + reg [c_width_b-1:0] doutb_out_q ; // registered output for doutb_out + reg [c_width_b-1:0] dob_out; // output of Port B RAM + reg [c_width_b-1:0] doutb_out ; // output of pipeline mux for port B + + reg [c_depth_a*c_width_a-1 : 0] mem; + reg [24:0] count ; + reg [1:0] wr_mode_a, wr_mode_b; + + reg [(c_width_a-1) : 0] pipelinea [0 : c_pipe_stages_a]; + reg [(c_width_b-1) : 0] pipelineb [0 : c_pipe_stages_b]; + reg sub_rdy_a[0 : c_pipe_stages_a]; + reg sub_rdy_b[0 : c_pipe_stages_b]; + + reg [10:0] ci, cj; + reg [10:0] dmi, dmj, dni, dnj, doi, doj, dai, daj, dbi, dbj, dci, dcj, ddi, ddj; + reg [10:0] pmi, pmj, pni, pnj, poi, poj, pai, paj, pbi, pbj, pci, pcj, pdi, pdj; + integer ai, aj, ak, al, am, an, ap ; + integer bi, bj, bk, bl, bm, bn, bp ; + integer i, j, k, l, m, n, p; + + wire [c_addra_width-1:0] addra_i = ADDRA; + reg [c_width_a-1:0] dia_int ; + reg [c_width_a-1:0] dia_q ; + wire [c_width_a-1:0] dia_i ; + wire ena_int ; + reg ena_q ; + wire clka_int ; + reg wea_int ; + wire wea_i ; + reg wea_q ; + wire ssra_int ; + wire nda_int ; + wire nda_i ; + reg rfda_int ; + reg rdya_int ; + reg nda_q ; + reg new_data_a ; + reg new_data_a_q ; + reg [c_addra_width-1:0] addra_q; + reg [c_addra_width-1:0] addra_int; + reg [c_width_a-1:0] sinita_value ; // initialization value for output registers of Port A + + wire [c_addrb_width-1:0] addrb_i = ADDRB; + reg [c_width_b-1:0] dib_int ; + reg [c_width_b-1:0] dib_q ; + wire [c_width_b-1:0] dib_i ; + wire enb_int ; + reg enb_q ; + wire clkb_int ; + reg web_int ; + wire web_i ; + reg web_q ; + wire ssrb_int ; + wire ndb_int ; + wire ndb_i ; + reg rfdb_int ; + reg rdyb_int ; + reg ndb_q ; + reg new_data_b ; + reg new_data_b_q ; + reg [c_addrb_width-1:0] addrb_q ; + reg [c_addrb_width-1:0] addrb_int ; + reg [c_width_b-1:0] sinitb_value ; // initialization value for output registers of Port B + +// variables used to initialize memory contents to default values. + + reg [c_width_a-1:0] bitval ; + reg [c_width_a-1:0] ram_temp [0:c_depth_a-1] ; + reg [c_width_a-1:0] default_data ; + +// variables used to detect address collision on dual port Rams + + reg recovery_a, recovery_b; + reg address_collision; + + wire clka_enable_pp = ena_int && wea_int && enb_int && address_collision + && c_yclka_is_rising && c_yclkb_is_rising; + wire clkb_enable_pp = enb_int && web_int && ena_int && address_collision + && c_yclka_is_rising && c_yclkb_is_rising; + wire collision_posa_posb = clka_enable_pp || clkb_enable_pp; + + // For posedge clka and negedge clkb + + wire clka_enable_pn = ena_int && wea_int && enb_int && address_collision + && c_yclka_is_rising && (!c_yclkb_is_rising); + wire clkb_enable_pn = enb_int && web_int && ena_int && address_collision + && c_yclka_is_rising && (!c_yclkb_is_rising); + wire collision_posa_negb = clka_enable_pn || clkb_enable_pn; + + // For negedge clka and posedge clkb + + wire clka_enable_np = ena_int && wea_int && enb_int && address_collision + && (!c_yclka_is_rising) && c_yclkb_is_rising; + wire clkb_enable_np = enb_int && web_int && ena_int && address_collision + && (!c_yclka_is_rising) && c_yclkb_is_rising; + wire collision_nega_posb = clka_enable_np || clkb_enable_np; + + // For negedge clka and clkb + + wire clka_enable_nn = ena_int && wea_int && enb_int && address_collision + && (!c_yclka_is_rising) && (!c_yclkb_is_rising); + wire clkb_enable_nn = enb_int && web_int && ena_int && address_collision + && (!c_yclka_is_rising) && (!c_yclkb_is_rising); + wire collision_nega_negb = clka_enable_nn || clkb_enable_nn; + + +// tri0 GSR = glbl.GSR; + + assign dia_i = (c_has_dina === 1)?DINA:'b0; + assign ena_int = defval(ENA, c_has_ena, 1, c_yena_is_high); + assign ssra_int = defval(SINITA, c_has_sinita, 0, c_ysinita_is_high); + assign nda_i = defval(NDA, c_has_nda, 1, 1); + assign clka_int = defval(CLKA, 1, 1, c_yclka_is_rising); + + assign dib_i = (c_has_dinb === 1)?DINB:'b0; + assign enb_int = defval(ENB, c_has_enb, 1, c_yenb_is_high); + assign ssrb_int = defval(SINITB, c_has_sinitb, 0, c_ysinitb_is_high); + assign ndb_i = defval(NDB, c_has_ndb, 1, 1); + assign clkb_int = defval(CLKB, 1, 1, c_yclkb_is_rising); + +// RAM/ROM functionality + + assign wea_i = defval(WEA, c_has_wea, 0, c_ywea_is_high); + assign web_i = defval(WEB, c_has_web, 0, c_yweb_is_high); + + + function defval; + input i; + input hassig; + input val; + input active_high; + begin + if(hassig == 1) + begin + if (active_high == 1) + defval = i; + else + defval = ~i; + end + else + defval = val; + end + endfunction + + function max; + input a; + input b; + begin + max = (a > b) ? a : b; + end + endfunction + + function a_is_X; + input [c_width_a-1 : 0] i; + integer j ; + begin + a_is_X = 1'b0; + for(j = 0; j < c_width_a; j = j + 1) + begin + if(i[j] === 1'bx) + a_is_X = 1'b1; + end // loop + end + endfunction + + function b_is_X; + input [c_width_b-1 : 0] i; + integer j ; + begin + b_is_X = 1'b0; + for(j = 0; j < c_width_b; j = j + 1) + begin + if(i[j] === 1'bx) + b_is_X = 1'b1; + end // loop + end + endfunction + + function [c_width_a-1:0] hexstr_conv; + input [(c_width_a*8)-1:0] def_data; + + integer index,i,j; + reg [3:0] bin; + + begin + index = 0; + hexstr_conv = 'b0; + for( i=c_width_a-1; i>=0; i=i-1 ) + begin + case (def_data[7:0]) + 8'b00000000 : + begin + bin = 4'b0000; + i = -1; + end + 8'b00110000 : bin = 4'b0000; + 8'b00110001 : bin = 4'b0001; + 8'b00110010 : bin = 4'b0010; + 8'b00110011 : bin = 4'b0011; + 8'b00110100 : bin = 4'b0100; + 8'b00110101 : bin = 4'b0101; + 8'b00110110 : bin = 4'b0110; + 8'b00110111 : bin = 4'b0111; + 8'b00111000 : bin = 4'b1000; + 8'b00111001 : bin = 4'b1001; + 8'b01000001 : bin = 4'b1010; + 8'b01000010 : bin = 4'b1011; + 8'b01000011 : bin = 4'b1100; + 8'b01000100 : bin = 4'b1101; + 8'b01000101 : bin = 4'b1110; + 8'b01000110 : bin = 4'b1111; + 8'b01100001 : bin = 4'b1010; + 8'b01100010 : bin = 4'b1011; + 8'b01100011 : bin = 4'b1100; + 8'b01100100 : bin = 4'b1101; + 8'b01100101 : bin = 4'b1110; + 8'b01100110 : bin = 4'b1111; + default : + begin + $display("ERROR in %m at time %t: NOT A HEX CHARACTER",$time); + bin = 4'bx; + end + endcase + for( j=0; j<4; j=j+1) + begin + if ((index*4)+j < c_width_a) + begin + hexstr_conv[(index*4)+j] = bin[j]; + end + end + index = index + 1; + def_data = def_data >> 8; + end + end + endfunction + + function [c_width_b-1:0] hexstr_conv_b; + input [(c_width_b*8)-1:0] def_data; + + integer index,i,j; + reg [3:0] bin; + + begin + index = 0; + hexstr_conv_b = 'b0; + for( i=c_width_b-1; i>=0; i=i-1 ) + begin + case (def_data[7:0]) + 8'b00000000 : + begin + bin = 4'b0000; + i = -1; + end + 8'b00110000 : bin = 4'b0000; + 8'b00110001 : bin = 4'b0001; + 8'b00110010 : bin = 4'b0010; + 8'b00110011 : bin = 4'b0011; + 8'b00110100 : bin = 4'b0100; + 8'b00110101 : bin = 4'b0101; + 8'b00110110 : bin = 4'b0110; + 8'b00110111 : bin = 4'b0111; + 8'b00111000 : bin = 4'b1000; + 8'b00111001 : bin = 4'b1001; + 8'b01000001 : bin = 4'b1010; + 8'b01000010 : bin = 4'b1011; + 8'b01000011 : bin = 4'b1100; + 8'b01000100 : bin = 4'b1101; + 8'b01000101 : bin = 4'b1110; + 8'b01000110 : bin = 4'b1111; + 8'b01100001 : bin = 4'b1010; + 8'b01100010 : bin = 4'b1011; + 8'b01100011 : bin = 4'b1100; + 8'b01100100 : bin = 4'b1101; + 8'b01100101 : bin = 4'b1110; + 8'b01100110 : bin = 4'b1111; + default : + begin + $display("ERROR in %m at time %t: NOT A HEX CHARACTER",$time); + bin = 4'bx; + end + endcase + for( j=0; j<4; j=j+1) + begin + if ((index*4)+j < c_width_b) + begin + hexstr_conv_b[(index*4)+j] = bin[j]; + end + end + index = index + 1; + def_data = def_data >> 8; + end + end + endfunction + + + + + +// Initialize memory contents to 0 for now . + + initial begin + + sinita_value = 'b0 ; + sinitb_value = 'b0 ; + + default_data = hexstr_conv(c_default_data); + if (c_has_sinita == 1 ) + sinita_value = hexstr_conv(c_sinita_value); + if (c_has_sinitb == 1 ) + sinitb_value = hexstr_conv_b(c_sinitb_value); + for(i = 0; i < c_depth_a; i = i + 1) + ram_temp[i] = default_data; + if (c_has_default_data == 0) + $readmemb(c_mem_init_file, ram_temp) ; + + for(i = 0; i < c_depth_a; i = i + 1) + for(j = 0; j < c_width_a; j = j + 1) + begin + bitval = (1'b1 << j); + mem[(i*c_width_a) + j] = (ram_temp[i] & bitval) >> j; + end + recovery_a = 0; + recovery_b = 0; + for (k = 0; k <= c_pipe_stages_a; k = k + 1) + pipelinea[k] = sinita_value ; + for (l = 0; l <= c_pipe_stages_b; l = l + 1) + pipelineb[l] = sinitb_value ; + for (m = 0; m <= c_pipe_stages_a; m = m + 1) + sub_rdy_a[m] = 0 ; + for (n = 0; n <= c_pipe_stages_b; n = n + 1) + sub_rdy_b[n] = 0 ; + doa_out = sinita_value ; + dob_out = sinitb_value ; + nda_q = 0; + ndb_q = 0; + new_data_a_q = 0 ; + new_data_b_q = 0 ; + dia_q = 0; + dib_q = 0; + addra_q = 0; + addrb_q = 0; + wea_q = 0; + web_q = 0; + end + + + always @(addra_int or addrb_int) begin // check address collision + address_collision <= 1'b0; + for (ci = 0; ci < c_width_a; ci = ci + 1) begin // absolute address A + for (cj = 0; cj < c_width_b; cj = cj + 1) begin // absolute address B + if ((addra_int * c_width_a + ci) == (addrb_int * c_width_b + cj)) begin + address_collision <= 1'b1; + end + end + end + end +/*********************************************************************************************************** +* The following 3 always blocks handle memory inputs for the case of an address collision on ADDRA and ADDRB +***********************************************************************************************************/ + always @(posedge recovery_a or posedge recovery_b) begin + if (((wr_mode_a == 2'b01) && (wr_mode_b == 2'b01)) || + ((wr_mode_a != 2'b01) && (wr_mode_b != 2'b01))) begin + if (wea_int == 1 && web_int == 1) begin + if (addra_int < c_depth_a) + for (dmi = 0; dmi < c_width_a; dmi = dmi + 1) begin + for (dmj = 0; dmj < c_width_b; dmj = dmj + 1) begin + if ((addra_int * c_width_a + dmi) == (addrb_int * c_width_b + dmj)) begin + mem[addra_int * c_width_a + dmi] <= 1'bX; + end + end + end + else + //Warning Condition: + //Write Mode PortA is "Read First" and Write Mode PortB is "Read First" and WEA = 1 and WEB = 1 and ADDRA out of the valid range + //or + //Write Mode PortA is not "Read First" and Write Mode PortB is not "Read First" and WEA = 1 and WEB = 1 and ADDRA out of the valid range + $display("Invalid Address Warning #1: Warning in %m at time %t: Port A address %d (%b) of block memory invalid. Valid depth configured as 0 to %d",$time,addra_int,addra_int,c_depth_a-1); + end + end + recovery_a <= 0; + recovery_b <= 0; + end + + always @(posedge recovery_a or posedge recovery_b) begin + if ((wr_mode_a == 2'b01) && (wr_mode_b != 2'b01)) begin + if (wea_int == 1 && web_int == 1) begin + if (addra_int < c_depth_a) + for (dni = 0; dni < c_width_a; dni = dni + 1) begin + for (dnj = 0; dnj < c_width_b; dnj = dnj + 1) begin + if ((addra_int * c_width_a + dni) == (addrb_int * c_width_b + dnj)) begin + mem[addra_int * c_width_a + dni] <= dia_int[dni]; + end + end + end + else + //Warning Condition: + //Write Mode PortA is "Read First" and Write Mode PortB is not "Read First" and WEA = 1 and WEB = 1 and ADDRA out of the valid range + $display("Invalid Address Warning #2: Warning in %m at time %t: Port A address %d (%b) of block memory invalid. Valid depth configured as 0 to %d",$time,addra_int,addra_int,c_depth_a-1); + end + end + end + + always @(posedge recovery_a or posedge recovery_b) begin + if ((wr_mode_a != 2'b01) && (wr_mode_b == 2'b01)) begin + if (wea_int == 1 && web_int == 1) begin + if (addrb_int < c_depth_b) + for (doi = 0; doi < c_width_a; doi = doi + 1) begin + for (doj = 0; doj < c_width_b; doj = doj + 1) begin + if ((addra_int * c_width_a + doi) == (addrb_int * c_width_b + doj)) begin + mem[addrb_int * c_width_b + doj] <= dib_int[doj]; + end + end + end + else + //Warning Condition: + //Write Mode PortA is not "Read First" and Write Mode PortB is "Read First" and WEA = 1 and WEB = 1 and ADDRB out of the valid range + $display("Invalid Address Warning #3: Warning in %m at time %t: Port B address %d (%b) of block memory invalid. Valid depth configured as 0 to %d",$time,addrb_int,addrb_int,c_depth_b-1); + end + end + end +/*********************************************************************************************************** +*The following 4 always blocks handle memory outputs for the case of an address collision on ADDRA and ADDRB +***********************************************************************************************************/ + always @(posedge recovery_a or posedge recovery_b) begin + if ((wr_mode_b == 2'b00) || (wr_mode_b == 2'b10)) begin + if ((wea_int == 0) && (web_int == 1) && (ssra_int == 0)) begin + if (addra_int < c_depth_a) + for (dai = 0; dai < c_width_a; dai = dai + 1) begin + for (daj = 0; daj < c_width_b; daj = daj + 1) begin + if ((addra_int * c_width_a + dai) == (addrb_int * c_width_b + daj)) begin + doa_out[dai] <= 1'bX; + end + end + end + else + //Warning Condition: + //Write Mode PortB is "Write First" and WEA = 0 and WEB = 1 and SINITA = 0 and ADDRA out of the valid range + //or + //Write Mode PortB is "No Change" and WEA = 0 and WEB = 1 and SINITA = 0 and ADDRA out of the valid range + $display("Invalid Address Warning #4: Warning in %m at time %t: Port A address %d (%b) of block memory invalid. Valid depth configured as 0 to %d",$time,addra_int,addra_int,c_depth_a-1); + end + end + end + + always @(posedge recovery_a or posedge recovery_b) begin + if ((wr_mode_a == 2'b00) || (wr_mode_a == 2'b10)) begin + if ((wea_int == 1) && (web_int == 0) && (ssrb_int == 0)) begin + if (addrb_int < c_depth_b) + for (dbi = 0; dbi < c_width_a; dbi = dbi + 1) begin + for (dbj = 0; dbj < c_width_b; dbj = dbj + 1) begin + if ((addra_int * c_width_a + dbi) == (addrb_int * c_width_b + dbj)) begin + dob_out[dbj] <= 1'bX; + end + end + end + else + //Warning Condition: + //Write Mode PortA is "Write First" and WEA = 1 and WEB = 0 and SINITB = 0 and ADDRB out of the valid range + //or + //Write Mode PortA is "No Change" and WEA = 1 and WEB = 0 and SINITB = 0 and ADDRB out of the valid range + $display("Invalid Address Warning #5: Warning in %m at time %t: Port B address %d (%b) of block memory invalid. Valid depth configured as 0 to %d",$time,addrb_int,addrb_int,c_depth_b-1); + end + end + end + + always @(posedge recovery_a or posedge recovery_b) begin + if (((wr_mode_a == 2'b00) && (wr_mode_b == 2'b00)) || + ((wr_mode_a != 2'b10) && (wr_mode_b == 2'b10)) || + ((wr_mode_a == 2'b01) && (wr_mode_b == 2'b00))) begin + if ((wea_int == 1) && (web_int == 1) && (ssra_int == 0)) begin + if (addra_int < c_depth_a) + for (dci = 0; dci < c_width_a; dci = dci + 1) begin + for (dcj = 0; dcj < c_width_b; dcj = dcj + 1) begin + if ((addra_int * c_width_a + dci) == (addrb_int * c_width_b + dcj)) begin + doa_out[dci] <= 1'bX; + end + end + end + else + //Warning Condition: + //Write Mode PortA is "Write First" and Write Mode PortB is "Write First" and WEA = 1 and WEB = 1 and SINITA = 0 and ADDRA out of the valid range + //or + //Write Mode PortA is not "No Change" and Write Mode PortB is "No Change" and WEA = 1 and WEB = 1 and SINITA = 0 and ADDRA out of the valid range + //or + //Write Mode PortA is "Read First" and Write Mode PortB is "Write First" and WEA = 1 and WEB = 1 and SINITA = 0 and ADDRA out of the valid range + $display("Invalid Address Warning #6: Warning in %m at time %t: Port A address %d (%b) of block memory invalid. Valid depth configured as 0 to %d",$time,addra_int,addra_int,c_depth_a-1); + end + end + end + + always @(posedge recovery_a or posedge recovery_b) begin + if (((wr_mode_a == 2'b00) && (wr_mode_b == 2'b00)) || + ((wr_mode_a == 2'b10) && (wr_mode_b != 2'b10)) || + ((wr_mode_a == 2'b00) && (wr_mode_b == 2'b01))) begin + if ((wea_int == 1) && (web_int == 1) && (ssrb_int == 0)) begin + if (addrb_int < c_depth_b) + for (ddi = 0; ddi < c_width_a; ddi = ddi + 1) begin + for (ddj = 0; ddj < c_width_b; ddj = ddj + 1) begin + if ((addra_int * c_width_a + ddi) == (addrb_int * c_width_b + ddj)) begin + dob_out[ddj] <= 1'bX; + end + end + end + else + //Warning Condition: + //Write Mode PortA is "Write First" and Write Mode PortB is "Write First" and WEA = 1 and WEB = 1 and SINITB = 0 and ADDRB out of the valid range + //or + //Write Mode PortA is "No Change" and Write Mode PortB is not "No Change" and WEA = 1 and WEB = 1 and SINITB = 0 and ADDRB out of the valid range + //or + //Write Mode PortA is "Write First" and Write Mode PortB is "Read First" and WEA = 1 and WEB = 1 and SINITB = 0 and ADDRB out of the valid range + $display("Invalid Address Warning #7: Warning in %m at time %t: Port B address %d (%b) of block memory invalid. Valid depth configured as 0 to %d",$time,addrb_int,addrb_int,c_depth_b-1); + end + end + end + + // Parity Section is deleted + + initial begin + case (c_write_modea) + `c_write_first : wr_mode_a <= 2'b00; + `c_read_first : wr_mode_a <= 2'b01; + `c_no_change : wr_mode_a <= 2'b10; + default : begin + $display("Error in %m at time %t: c_write_modea = %s is not WRITE_FIRST, READ_FIRST or NO_CHANGE.",$time, c_write_modea); + $finish; + end + endcase + end + + initial begin + case (c_write_modeb) + `c_write_first : wr_mode_b <= 2'b00; + `c_read_first : wr_mode_b <= 2'b01; + `c_no_change : wr_mode_b <= 2'b10; + default : begin + $display("Error in %m at time %t: c_write_modeb = %s is not WRITE_FIRST, READ_FIRST or NO_CHANGE.",$time, c_write_modeb); + $finish; + end + endcase + end + +// Port A + + +// Generate ouput control signals for Port A: RFDA and RDYA + + always @ (rfda_int or rdya_int) + begin + if (c_has_rfda == 1) + RFDA = rfda_int ; + else + RFDA = 1'b0 ; + + if ((c_has_rdya == 1) && (c_has_nda == 1) && (c_has_rfda == 1) ) + RDYA = rdya_int; + else + RDYA = 1'b0 ; + end + + always @ (ena_int ) + begin + if (ena_int == 1'b1) + rfda_int <= 1'b1 ; + else + rfda_int <= 1'b0 ; + end + +// Gate nd signal with en + + assign nda_int = ena_int && nda_i ; + +// Register hanshaking signals for port A + + always @ (posedge clka_int) + begin + if (ena_int == 1'b1) + begin + if (ssra_int == 1'b1) + nda_q <= 1'b0 ; + else + nda_q <= nda_int ; + end + else + nda_q <= nda_q ; + end + +// Register data/ address / we inputs for port A + + always @ (posedge clka_int) + begin + if (ena_int == 1'b1) + begin + dia_q <= dia_i ; + addra_q <= addra_i ; + wea_q <= wea_i ; + end + end + + +// Select registered or non-registered write enable for Port A + + always @ ( wea_i or wea_q ) + begin + if (c_reg_inputsa == 1) + wea_int = wea_q ; + else + wea_int = wea_i ; + end + +// Select registered or non-registered data/address/nd inputs for Port A + + always @ ( dia_i or dia_q ) + begin + if ( c_reg_inputsa == 1) + dia_int = dia_q; + else + dia_int = dia_i; + end + + always @ ( addra_i or addra_q or nda_q or nda_int ) + begin + if ( c_reg_inputsa == 1) + begin + addra_int = addra_q ; + new_data_a = nda_q ; + end + else + begin + addra_int = addra_i; + new_data_a = nda_int ; + end + end + +// Register the new_data signal for Port A to track the synchronous RAM output + + always @(posedge clka_int) + begin + if (ena_int == 1'b1) + begin + if (ssra_int == 1'b1) + new_data_a_q <= 1'b0 ; + else + new_data_a_q <= new_data_a ; + end + end + +// Generate data outputs for Port A + + + /*************************************************************** + *The following always block assigns the value for the DOUTA bus + ***************************************************************/ + always @(posedge clka_int) begin + if (ena_int == 1'b1) begin + if (ssra_int == 1'b1) begin + for ( ai = 0; ai < c_width_a; ai = ai + 1) + doa_out[ai] <= sinita_value[ai]; + end + else begin + //The following IF block assigns the output for a write operation + if (wea_int == 1'b1) begin + if (wr_mode_a == 2'b00) begin + if (addra_int < c_depth_a) + for ( aj = 0; aj < c_width_a; aj = aj + 1) + doa_out[aj] <= dia_int[aj] ; + else + //Warning Condition (Error occurs on rising edge of CLKA): + //Write Mode PortA is "Write First" and ENA = 1 and SINITA = 0 and WEA = 1 and ADDRA out of the valid range + $display("Invalid Address Warning #8: Warning in %m at time %t: Port A address %d (%b) of block memory invalid. Valid depth configured as 0 to %d",$time,addra_int,addra_int,c_depth_a-1); + end + else if (wr_mode_a == 2'b01) begin + if (addra_int < c_depth_a) + for ( ak = 0; ak < c_width_a; ak = ak + 1) + doa_out[ak] <= mem[(addra_int*c_width_a) + ak]; + else + //Warning Condition (Error occurs on rising edge of CLKA): + //Write Mode PortA is "Read First" and ENA = 1 and SINITA = 0 and WEA = 1 and ADDRA out of the valid range + $display("Invalid Address Warning #9: Warning in %m at time %t: Port A address %d (%b) of block memory invalid. Valid depth configured as 0 to %d",$time,addra_int,addra_int,c_depth_a-1); + end + else begin + if (addra_int < c_depth_a) + doa_out <= doa_out; + else + //Warning Condition (Error occurs on rising edge of CLKA): + //Write Mode PortA is "No Change" and ENA = 1 and SINITA = 0 and WEA = 1 and ADDRA out of the valid range + $display("Invalid Address Warning #10: Warning in %m at time %t: Port A address %d (%b) of block memory invalid. Valid depth configured as 0 to %d",$time,addra_int,addra_int,c_depth_a-1); + end + end + //The following ELSE block assigns the output for a read operation + else begin + if (addra_int < c_depth_a) + for ( al = 0; al < c_width_a; al = al + 1) + doa_out[al] <= mem[(addra_int*c_width_a) + al]; + else begin + if (c_has_douta == 1)//New IF statement to remove read errors when port is write only + begin + //Warning Condition (Error occurs on rising edge of CLKA): + //ENA = 1 and SINITA = 0 and WEA = 0 and ADDRA out of the valid range + $display("Invalid Address Warning #11: Warning in %m at time %t: Port A address %d (%b) of block memory invalid. Valid depth configured as 0 to %d",$time,addra_int,addra_int,c_depth_a-1); + end + end + end + end + end + end + /*************************************************************************************** + *The following always block assigns the DINA bus to the memory during a write operation + ***************************************************************************************/ + always @(posedge clka_int) begin + if (ena_int == 1'b1 && wea_int == 1'b1) begin + if (addra_int < c_depth_a) + for ( am = 0; am < c_width_a; am = am + 1) + mem[(addra_int*c_width_a) + am] <= dia_int[am]; + else + //Warning Condition (Error occurs on rising edge of CLKA): + //ENA = 1 and WEA = 1 and ADDRA out of the valid range + $display("Invalid Address Warning #12: Warning in %m at time %t: Port A address %d (%b) of block memory invalid. Valid depth configured as 0 to %d",$time,addra_int,addra_int,c_depth_a-1); + end + end + + // output pipelines for Port A + + always @(posedge clka_int) begin + if (ena_int == 1'b1 && c_pipe_stages_a > 0) + begin + for (i = c_pipe_stages_a; i >= 1; i = i -1 ) + begin + if (ssra_int == 1'b1 && ena_int == 1'b1 ) + begin + pipelinea[i] <= sinita_value ; + sub_rdy_a[i] <= 0 ; + end + else + begin + if (i==1) + begin + pipelinea[i] <= doa_out ; + sub_rdy_a[i] <= new_data_a_q ; + end + else + + begin + pipelinea[i] <= pipelinea[i-1] ; + sub_rdy_a[i] <= sub_rdy_a[i-1] ; + end + end + end + end + end + +// Select pipeline output if c_pipe_stages_a > 0 + + always @( pipelinea[c_pipe_stages_a] or sub_rdy_a[c_pipe_stages_a] or new_data_a_q or doa_out ) begin + if (c_pipe_stages_a == 0 ) + begin + douta_out = doa_out ; + rdya_int = new_data_a_q; + end + else + begin + douta_out = pipelinea[c_pipe_stages_a]; + rdya_int = sub_rdy_a[c_pipe_stages_a]; + end + end + + + // Select Port A data outputs based on c_has_douta parameter + + always @( douta_out ) begin + if ( c_has_douta == 1) + douta_mux_out = douta_out ; + else + douta_mux_out = 0 ; + end + + + +// Port B + + + +// Generate output control signals for Port B: RFDB and RDYB + + always @ (rfdb_int or rdyb_int) + begin + if (c_has_rfdb == 1) + RFDB = rfdb_int ; + else + RFDB = 1'b0 ; + + if ((c_has_rdyb == 1) && (c_has_ndb == 1) && (c_has_rfdb == 1) ) + RDYB = rdyb_int; + else + RDYB = 1'b0 ; + end + + always @ (enb_int ) + begin + if ( enb_int == 1'b1 ) + rfdb_int = 1'b1 ; + else + rfdb_int = 1'b0 ; + end + +// Gate nd signal with en + + assign ndb_int = enb_int && ndb_i ; + +// Register hanshaking signals for port B + + always @ (posedge clkb_int) + begin + if (enb_int == 1'b1) + begin + if (ssrb_int == 1'b1) + ndb_q <= 1'b0 ; + else + ndb_q <= ndb_int ; + end + else + ndb_q <= ndb_q; + end + +// Register data / address / we inputs for port B + + always @ (posedge clkb_int) + begin + if (enb_int == 1'b1) + begin + dib_q <= dib_i ; + addrb_q <= addrb_i ; + web_q <= web_i ; + end + end + +// Select registered or non-registered write enable for port B + + always @ (web_i or web_q ) + begin + if (c_reg_inputsb == 1) + web_int = web_q ; + else + web_int = web_i ; + end + + + +// Select registered or non-registered data/address/nd inputs for Port B + + always @ ( dib_i or dib_q ) + begin + if ( c_reg_inputsb == 1) + dib_int = dib_q; + else + dib_int = dib_i; + end + + always @ ( addrb_i or addrb_q or ndb_q or ndb_int) + begin + if ( c_reg_inputsb == 1) + begin + addrb_int = addrb_q ; + new_data_b = ndb_q ; + end + else + begin + addrb_int = addrb_i; + new_data_b = ndb_int ; + end + end + +// Register the new_data signal for Port B to track the synchronous RAM output + + always @(posedge clkb_int) + begin + if (enb_int == 1'b1 ) + begin + if (ssrb_int == 1'b1) + new_data_b_q <= 1'b0 ; + else + new_data_b_q <= new_data_b ; + end + end + + + + + +// Generate data outputs for Port B + + + /*************************************************************** + *The following always block assigns the value for the DOUTB bus + ***************************************************************/ + always @(posedge clkb_int) begin + if (enb_int == 1'b1) begin + if (ssrb_int == 1'b1) begin + for (bi = 0; bi < c_width_b; bi = bi + 1) + dob_out[bi] <= sinitb_value[bi]; + end + else begin + //The following IF block assigns the output for a write operation + if (web_int == 1'b1) begin + if (wr_mode_b == 2'b00) begin + if (addrb_int < c_depth_b) + for (bj = 0; bj < c_width_b; bj = bj + 1) + dob_out[bj] <= dib_int[bj]; + else + //Warning Condition (Error occurs on rising edge of CLKB): + //Write Mode PortB is "Write First" and ENB = 1 and SINITB = 0 and WEB = 1 and ADDRB out of the valid range + $display("Invalid Address Warning #13: Warning in %m at time %t: Port B address %d (%b) of block memory invalid. Valid depth configured as 0 to %d",$time,addrb_int,addrb_int,c_depth_b-1); + end + else if (wr_mode_b == 2'b01) begin + if (addrb_int < c_depth_b) + for (bk = 0; bk < c_width_b; bk = bk + 1) + dob_out[bk] <= mem[(addrb_int*c_width_b) + bk]; + else + //Warning Condition (Error occurs on rising edge of CLKB): + //Write Mode PortB is "Read First" and ENB = 1 and SINITB = 0 and WEB = 1 and ADDRB out of the valid range + $display("Invalid Address Warning #14: Warning in %m at time %t: Port B address %d (%b) of block memory invalid. Valid depth configured as 0 to %d",$time,addrb_int,addrb_int,c_depth_b-1); + end + else begin + if (addrb_int < c_depth_b) + dob_out <= dob_out ; + else + //Warning Condition (Error occurs on rising edge of CLKB): + //Write Mode PortB is "No Change" and ENB = 1 and SINITB = 0 and WEB = 1 and ADDRB out of the valid range + $display("Invalid Address Warning #15: Warning in %m at time %t: Port B address %d (%b) of block memory invalid. Valid depth configured as 0 to %d",$time,addrb_int,addrb_int,c_depth_b-1); + end + end + //The following ELSE block assigns the output for a read operation + else begin + if (addrb_int < c_depth_b) + for (bl = 0; bl < c_width_b; bl = bl + 1) + dob_out[bl] <= mem[(addrb_int*c_width_b) + bl]; + else begin + if (c_has_doutb == 1)//New IF statement to remove read errors when port is write only + begin + //Warning Condition (Error occurs on rising edge of CLKB): + //ENB = 1 and SINITB = 0 and WEB = 0 and ADDRB out of the valid range + $display("Invalid Address Warning #16: Warning in %m at time %t: Port B address %d (%b) of block memory invalid. Valid depth configured as 0 to %d",$time,addrb_int,addrb_int,c_depth_b-1); + end + end + end + end + end + end + /*************************************************************************************** + *The following always block assigns the DINA bus to the memory during a write operation + ***************************************************************************************/ + always @(posedge clkb_int) begin + if (enb_int == 1'b1 && web_int == 1'b1) begin + if (addrb_int < c_depth_b) + for (bm = 0; bm < c_width_b; bm = bm + 1) + mem[(addrb_int*c_width_b) + bm] <= dib_int[bm]; + else + //Warning Condition (Error occurs on rising edge of CLKB): + //ENB = 1 and WEB = 1 and ADDRB out of the valid range + $display("Invalid Address Warning #17: Warning in %m at time %t: Port B address %d (%b) of block memory invalid. Valid depth configured as 0 to %d",$time,addrb_int,addrb_int,c_depth_b-1); + end + end + + // output pipelines for Port B + + always @(posedge clkb_int) begin + if (enb_int == 1'b1 && c_pipe_stages_b > 0) + begin + for (j = c_pipe_stages_b; j >= 1; j = j -1 ) + begin + if (ssrb_int == 1'b1 && enb_int == 1'b1 ) + begin + pipelineb[j] <= sinitb_value ; + sub_rdy_b[j] <= 0 ; + end + else + begin + if (j==1) + begin + pipelineb[j] <= dob_out ; + sub_rdy_b[j] <= new_data_b_q ; + end + else + begin + pipelineb[j] <= pipelineb[j-1] ; + sub_rdy_b[j] <= sub_rdy_b[j-1] ; + end + end + end + end + end + +// Select pipeline for B if c_pipe_stages_b > 0 + + always @(pipelineb[c_pipe_stages_b] or sub_rdy_b[c_pipe_stages_b] or new_data_b_q or dob_out) begin + if ( c_pipe_stages_b == 0 ) + begin + doutb_out = dob_out ; + rdyb_int = new_data_b_q; + end + else + begin + rdyb_int = sub_rdy_b[c_pipe_stages_b]; + doutb_out = pipelineb[c_pipe_stages_b]; + end + end + + +// Select Port B data outputs based on c_has_doutb parameter + + always @( doutb_out) begin + if ( c_has_doutb == 1) + doutb_mux_out = doutb_out ; + else + doutb_mux_out = 0 ; + end + + + + + + specify + + // when both CLKA and CLKB are active on the positive edge + $recovery (posedge CLKB, posedge CLKA &&& collision_posa_posb, 1, recovery_b); + $recovery (posedge CLKA, posedge CLKB &&& collision_posa_posb, 1, recovery_a); + + // when both CLKA active on positive edge and CLKB are active on the negative edge + $recovery (negedge CLKB, posedge CLKA &&& collision_posa_negb, 1, recovery_b); + $recovery (posedge CLKA, negedge CLKB &&& collision_posa_negb, 1, recovery_a); + + // when both CLKA active on negative edge and CLKB are active on the positive edge + $recovery (posedge CLKB, negedge CLKA &&& collision_nega_posb, 1, recovery_b); + $recovery (negedge CLKA, posedge CLKB &&& collision_nega_posb, 1, recovery_a); + + // when both CLKA and CLKB are active on the negative edge + $recovery (negedge CLKB, negedge CLKA &&& collision_nega_negb, 1, recovery_b); + $recovery (negedge CLKA, negedge CLKB &&& collision_nega_negb, 1, recovery_a); + + endspecify + +endmodule + +`endcelldefine diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/BLKMEMDP_V5_0.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/BLKMEMDP_V5_0.v new file mode 100644 index 0000000..13976ea --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/BLKMEMDP_V5_0.v @@ -0,0 +1,1181 @@ +/************************************************************************** + * $RCSfile: BLKMEMDP_V5_0.v,v $ $Revision: 1.15 $ $Date: 2008/09/08 20:06:23 $ + ************************************************************************** + * Dual Port Block Memory - Verilog Behavioral Model + * ************************************************************************ + * + * Copyright(C) 2002 by Xilinx, Inc. All rights reserved. + * This text contains proprietary, confidential + * information of Xilinx, Inc., is distributed + * under license from Xilinx, Inc., and may be used, + * copied and/or disclosed only pursuant to the terms + * of a valid license agreement with Xilinx, Inc. This copyright + * notice must be retained as part of this text at all times. + * + ************************************************************************* + * Filename: BLKMEMDP_V5_0.v + * + * Description: The Verilog behavioral model for the Dual Port Block Memory + * + * *********************************************************************** + */ + +`timescale 1ns/10ps +`celldefine + + +`define c_dp_rom 4 +`define c_dp_ram 2 +`define c_write_first 0 +`define c_read_first 1 +`define c_no_change 2 + +module BLKMEMDP_V5_0(DOUTA, DOUTB, ADDRA, CLKA, DINA, ENA, SINITA, WEA, NDA, RFDA, RDYA, ADDRB, CLKB, DINB, ENB, SINITB, WEB,NDB, RFDB, RDYB); + + + + parameter c_addra_width = 11 ; + parameter c_addrb_width = 9 ; + parameter c_default_data = "0"; // indicates string of hex characters used to initialize memory + parameter c_depth_a = 2048 ; + parameter c_depth_b = 512 ; + parameter c_enable_rlocs = 0 ; // core includes placement constraints + parameter c_has_default_data = 1; + parameter c_has_dina = 1 ; // indicate port A has data input pins + parameter c_has_dinb = 1 ; // indicate port B has data input pins + parameter c_has_douta = 1 ; // indicates port A has output + parameter c_has_doutb = 1 ; // indicates port B has output + parameter c_has_ena = 1 ; // indicates port A has a ENA pin + parameter c_has_enb = 1 ; // indicates port B has a ENB pin + parameter c_has_limit_data_pitch = 1 ; + parameter c_has_nda = 0 ; // Port A has a new data pin + parameter c_has_ndb = 0 ; // Port B has a new data pin + parameter c_has_rdya = 0 ; // Port A has result ready pin + parameter c_has_rdyb = 0 ; // Port B has result ready pin + parameter c_has_rfda = 0 ; // Port A has ready for data pin + parameter c_has_rfdb = 0 ; // Port B has ready for data pin + parameter c_has_sinita = 1 ; // indicates port A has a SINITA pin + parameter c_has_sinitb = 1 ; // indicates port B has a SINITB pin + parameter c_has_wea = 1 ; // indicates port A has a WEA pin + parameter c_has_web = 1 ; // indicates port B has a WEB pin + parameter c_limit_data_pitch = 16 ; + parameter c_mem_init_file = "null.mif"; // controls which .mif file used to initialize memory + parameter c_pipe_stages_a = 0 ; // indicates the number of pipe stages needed in port A + parameter c_pipe_stages_b = 0 ; // indicates the number of pipe stages needed in port B + parameter c_reg_inputsa = 0 ; // indicates we, addr, and din of port A are registered + parameter c_reg_inputsb = 0 ; // indicates we, addr, and din of port B are registered + parameter c_sinita_value = "0000"; // indicates string of hex used to initialize A output registers + parameter c_sinitb_value = "0000"; // indicates string of hex used to initialize B output resisters + parameter c_width_a = 8 ; + parameter c_width_b = 32 ; + parameter c_write_modea = 2; // controls which write modes shall be used + parameter c_write_modeb = 2; // controls which write modes shall be used + + // New Generics for Primitive Selection and Pin Polarity + parameter c_ybottom_addr = "1024"; + parameter c_yclka_is_rising = 1; // controls the active edge of the CLKA Pin + parameter c_yclkb_is_rising = 1; // controls the active edge of the CLKB Pin + parameter c_yena_is_high = 1; // controls the polarity of the ENA Pin + parameter c_yenb_is_high = 1; // controls the polarity of the ENB Pin + parameter c_yhierarchy = "hierarchy1"; + parameter c_ymake_bmm = 0; + parameter c_yprimitive_type = "4kx4"; // Indicates which primitive should be used to build the + // memory if c_yuse_single_primitive=1 + parameter c_ysinita_is_high = 1; // controls the polarity of the SINITA Pin + parameter c_ysinitb_is_high = 1; // controls the polarity of the SINITB Pin + parameter c_ytop_addr = "0"; + parameter c_yuse_single_primitive = 0; // controls whether the Memory is build out of a + // user selected primitive or is built from multiple + // primitives with the "optimize for area" algorithm used + parameter c_ywea_is_high = 1; // controls the polarity of the WEA Pin + parameter c_yweb_is_high = 1; // controls the polarity of the WEB Pin + + +// IO ports + + + + output [c_width_a-1:0] DOUTA; + + input [c_addra_width-1:0] ADDRA; + input [c_width_a-1:0] DINA; + input ENA, CLKA, WEA, SINITA, NDA; + output RFDA, RDYA; + + output [c_width_b-1:0] DOUTB; + + input [c_addrb_width-1:0] ADDRB; + input [c_width_b-1:0] DINB; + input ENB, CLKB, WEB, SINITB, NDB; + output RFDB, RDYB; + + +// internal signals + + reg [c_width_a-1:0] douta_mux_out ; // output of multiplexer -- + wire [c_width_a-1:0] DOUTA = douta_mux_out; + reg RFDA, RDYA ; + + reg [c_width_b-1:0] doutb_mux_out ; // output of multiplexer -- + wire [c_width_b-1:0] DOUTB = doutb_mux_out; + reg RFDB, RDYB; + + + reg [c_width_a-1:0] douta_out_q; // registered output of douta_out + reg [c_width_a-1:0] doa_out; // output of Port A RAM + reg [c_width_a-1:0] douta_out; // output of pipeline mux for port A + + reg [c_width_b-1:0] doutb_out_q ; // registered output for doutb_out + reg [c_width_b-1:0] dob_out; // output of Port B RAM + reg [c_width_b-1:0] doutb_out ; // output of pipeline mux for port B + + reg [c_depth_a*c_width_a-1 : 0] mem; + reg [24:0] count ; + reg [1:0] wr_mode_a, wr_mode_b; + + reg [(c_width_a-1) : 0] pipelinea [0 : c_pipe_stages_a]; + reg [(c_width_b-1) : 0] pipelineb [0 : c_pipe_stages_b]; + reg sub_rdy_a[0 : c_pipe_stages_a]; + reg sub_rdy_b[0 : c_pipe_stages_b]; + + reg [10:0] ci, cj; + reg [10:0] dmi, dmj, dni, dnj, doi, doj, dai, daj, dbi, dbj, dci, dcj, ddi, ddj; + reg [10:0] pmi, pmj, pni, pnj, poi, poj, pai, paj, pbi, pbj, pci, pcj, pdi, pdj; + integer ai, aj, ak, al, am, an, ap ; + integer bi, bj, bk, bl, bm, bn, bp ; + integer i, j, k, l, m, n, p; + + wire [c_addra_width-1:0] addra_i = ADDRA; + reg [c_width_a-1:0] dia_int ; + reg [c_width_a-1:0] dia_q ; + wire [c_width_a-1:0] dia_i ; + wire ena_int ; + reg ena_q ; + wire clka_int ; + reg wea_int ; + wire wea_i ; + reg wea_q ; + wire ssra_int ; + wire nda_int ; + wire nda_i ; + reg rfda_int ; + reg rdya_int ; + reg nda_q ; + reg new_data_a ; + reg new_data_a_q ; + reg [c_addra_width-1:0] addra_q; + reg [c_addra_width-1:0] addra_int; + reg [c_width_a-1:0] sinita_value ; // initialization value for output registers of Port A + + wire [c_addrb_width-1:0] addrb_i = ADDRB; + reg [c_width_b-1:0] dib_int ; + reg [c_width_b-1:0] dib_q ; + wire [c_width_b-1:0] dib_i ; + wire enb_int ; + reg enb_q ; + wire clkb_int ; + reg web_int ; + wire web_i ; + reg web_q ; + wire ssrb_int ; + wire ndb_int ; + wire ndb_i ; + reg rfdb_int ; + reg rdyb_int ; + reg ndb_q ; + reg new_data_b ; + reg new_data_b_q ; + reg [c_addrb_width-1:0] addrb_q ; + reg [c_addrb_width-1:0] addrb_int ; + reg [c_width_b-1:0] sinitb_value ; // initialization value for output registers of Port B + +// variables used to initialize memory contents to default values. + + reg [c_width_a-1:0] bitval ; + reg [c_width_a-1:0] ram_temp [0:c_depth_a-1] ; + reg [c_width_a-1:0] default_data ; + +// variables used to detect address collision on dual port Rams + + reg recovery_a, recovery_b; + reg address_collision; + + wire clka_enable_pp = ena_int && wea_int && enb_int && address_collision + && c_yclka_is_rising && c_yclkb_is_rising; + wire clkb_enable_pp = enb_int && web_int && ena_int && address_collision + && c_yclka_is_rising && c_yclkb_is_rising; + wire collision_posa_posb = clka_enable_pp || clkb_enable_pp; + + // For posedge clka and negedge clkb + + wire clka_enable_pn = ena_int && wea_int && enb_int && address_collision + && c_yclka_is_rising && (!c_yclkb_is_rising); + wire clkb_enable_pn = enb_int && web_int && ena_int && address_collision + && c_yclka_is_rising && (!c_yclkb_is_rising); + wire collision_posa_negb = clka_enable_pn || clkb_enable_pn; + + // For negedge clka and posedge clkb + + wire clka_enable_np = ena_int && wea_int && enb_int && address_collision + && (!c_yclka_is_rising) && c_yclkb_is_rising; + wire clkb_enable_np = enb_int && web_int && ena_int && address_collision + && (!c_yclka_is_rising) && c_yclkb_is_rising; + wire collision_nega_posb = clka_enable_np || clkb_enable_np; + + // For negedge clka and clkb + + wire clka_enable_nn = ena_int && wea_int && enb_int && address_collision + && (!c_yclka_is_rising) && (!c_yclkb_is_rising); + wire clkb_enable_nn = enb_int && web_int && ena_int && address_collision + && (!c_yclka_is_rising) && (!c_yclkb_is_rising); + wire collision_nega_negb = clka_enable_nn || clkb_enable_nn; + + +// tri0 GSR = glbl.GSR; + + assign dia_i = (c_has_dina === 1)?DINA:'b0; + assign ena_int = defval(ENA, c_has_ena, 1, c_yena_is_high); + assign ssra_int = defval(SINITA, c_has_sinita, 0, c_ysinita_is_high); + assign nda_i = defval(NDA, c_has_nda, 1, 1); + assign clka_int = defval(CLKA, 1, 1, c_yclka_is_rising); + + assign dib_i = (c_has_dinb === 1)?DINB:'b0; + assign enb_int = defval(ENB, c_has_enb, 1, c_yenb_is_high); + assign ssrb_int = defval(SINITB, c_has_sinitb, 0, c_ysinitb_is_high); + assign ndb_i = defval(NDB, c_has_ndb, 1, 1); + assign clkb_int = defval(CLKB, 1, 1, c_yclkb_is_rising); + +// RAM/ROM functionality + + assign wea_i = defval(WEA, c_has_wea, 0, c_ywea_is_high); + assign web_i = defval(WEB, c_has_web, 0, c_yweb_is_high); + + + function defval; + input i; + input hassig; + input val; + input active_high; + begin + if(hassig == 1) + begin + if (active_high == 1) + defval = i; + else + defval = ~i; + end + else + defval = val; + end + endfunction + + function max; + input a; + input b; + begin + max = (a > b) ? a : b; + end + endfunction + + function a_is_X; + input [c_width_a-1 : 0] i; + integer j ; + begin + a_is_X = 1'b0; + for(j = 0; j < c_width_a; j = j + 1) + begin + if(i[j] === 1'bx) + a_is_X = 1'b1; + end // loop + end + endfunction + + function b_is_X; + input [c_width_b-1 : 0] i; + integer j ; + begin + b_is_X = 1'b0; + for(j = 0; j < c_width_b; j = j + 1) + begin + if(i[j] === 1'bx) + b_is_X = 1'b1; + end // loop + end + endfunction + + function [c_width_a-1:0] hexstr_conv; + input [(c_width_a*8)-1:0] def_data; + + integer index,i,j; + reg [3:0] bin; + + begin + index = 0; + hexstr_conv = 'b0; + for( i=c_width_a-1; i>=0; i=i-1 ) + begin + case (def_data[7:0]) + 8'b00000000 : + begin + bin = 4'b0000; + i = -1; + end + 8'b00110000 : bin = 4'b0000; + 8'b00110001 : bin = 4'b0001; + 8'b00110010 : bin = 4'b0010; + 8'b00110011 : bin = 4'b0011; + 8'b00110100 : bin = 4'b0100; + 8'b00110101 : bin = 4'b0101; + 8'b00110110 : bin = 4'b0110; + 8'b00110111 : bin = 4'b0111; + 8'b00111000 : bin = 4'b1000; + 8'b00111001 : bin = 4'b1001; + 8'b01000001 : bin = 4'b1010; + 8'b01000010 : bin = 4'b1011; + 8'b01000011 : bin = 4'b1100; + 8'b01000100 : bin = 4'b1101; + 8'b01000101 : bin = 4'b1110; + 8'b01000110 : bin = 4'b1111; + 8'b01100001 : bin = 4'b1010; + 8'b01100010 : bin = 4'b1011; + 8'b01100011 : bin = 4'b1100; + 8'b01100100 : bin = 4'b1101; + 8'b01100101 : bin = 4'b1110; + 8'b01100110 : bin = 4'b1111; + default : + begin + $display("ERROR in %m at time %t: NOT A HEX CHARACTER",$time); + bin = 4'bx; + end + endcase + for( j=0; j<4; j=j+1) + begin + if ((index*4)+j < c_width_a) + begin + hexstr_conv[(index*4)+j] = bin[j]; + end + end + index = index + 1; + def_data = def_data >> 8; + end + end + endfunction + + function [c_width_b-1:0] hexstr_conv_b; + input [(c_width_b*8)-1:0] def_data; + + integer index,i,j; + reg [3:0] bin; + + begin + index = 0; + hexstr_conv_b = 'b0; + for( i=c_width_b-1; i>=0; i=i-1 ) + begin + case (def_data[7:0]) + 8'b00000000 : + begin + bin = 4'b0000; + i = -1; + end + 8'b00110000 : bin = 4'b0000; + 8'b00110001 : bin = 4'b0001; + 8'b00110010 : bin = 4'b0010; + 8'b00110011 : bin = 4'b0011; + 8'b00110100 : bin = 4'b0100; + 8'b00110101 : bin = 4'b0101; + 8'b00110110 : bin = 4'b0110; + 8'b00110111 : bin = 4'b0111; + 8'b00111000 : bin = 4'b1000; + 8'b00111001 : bin = 4'b1001; + 8'b01000001 : bin = 4'b1010; + 8'b01000010 : bin = 4'b1011; + 8'b01000011 : bin = 4'b1100; + 8'b01000100 : bin = 4'b1101; + 8'b01000101 : bin = 4'b1110; + 8'b01000110 : bin = 4'b1111; + 8'b01100001 : bin = 4'b1010; + 8'b01100010 : bin = 4'b1011; + 8'b01100011 : bin = 4'b1100; + 8'b01100100 : bin = 4'b1101; + 8'b01100101 : bin = 4'b1110; + 8'b01100110 : bin = 4'b1111; + default : + begin + $display("ERROR in %m at time %t: NOT A HEX CHARACTER",$time); + bin = 4'bx; + end + endcase + for( j=0; j<4; j=j+1) + begin + if ((index*4)+j < c_width_b) + begin + hexstr_conv_b[(index*4)+j] = bin[j]; + end + end + index = index + 1; + def_data = def_data >> 8; + end + end + endfunction + + + + + +// Initialize memory contents to 0 for now . + + initial begin + sinita_value = 'b0 ; + sinitb_value = 'b0 ; + + default_data = hexstr_conv(c_default_data); + if (c_has_sinita == 1 ) + sinita_value = hexstr_conv(c_sinita_value); + if (c_has_sinitb == 1 ) + sinitb_value = hexstr_conv_b(c_sinitb_value); + for(i = 0; i < c_depth_a; i = i + 1) + ram_temp[i] = default_data; + if (c_has_default_data == 0) + $readmemb(c_mem_init_file, ram_temp) ; + + for(i = 0; i < c_depth_a; i = i + 1) + for(j = 0; j < c_width_a; j = j + 1) + begin + bitval = (1'b1 << j); + mem[(i*c_width_a) + j] = (ram_temp[i] & bitval) >> j; + end + recovery_a = 0; + recovery_b = 0; + for (k = 0; k <= c_pipe_stages_a; k = k + 1) + pipelinea[k] = sinita_value ; + for (l = 0; l <= c_pipe_stages_b; l = l + 1) + pipelineb[l] = sinitb_value ; + for (m = 0; m <= c_pipe_stages_a; m = m + 1) + sub_rdy_a[m] = 0 ; + for (n = 0; n <= c_pipe_stages_b; n = n + 1) + sub_rdy_b[n] = 0 ; + doa_out = sinita_value ; + dob_out = sinitb_value ; + nda_q = 0; + ndb_q = 0; + new_data_a_q = 0 ; + new_data_b_q = 0 ; + dia_q = 0; + dib_q = 0; + addra_q = 0; + addrb_q = 0; + wea_q = 0; + web_q = 0; + #1 douta_out = sinita_value; + #1 doutb_out = sinitb_value; + #1 rdya_int = 0; + #1 rdyb_int = 0; + end + + + always @(addra_int or addrb_int) begin // check address collision + address_collision <= 1'b0; + for (ci = 0; ci < c_width_a; ci = ci + 1) begin // absolute address A + for (cj = 0; cj < c_width_b; cj = cj + 1) begin // absolute address B + if ((addra_int * c_width_a + ci) == (addrb_int * c_width_b + cj)) begin + address_collision <= 1'b1; + end + end + end + end +/*********************************************************************************************************** +* The following 3 always blocks handle memory inputs for the case of an address collision on ADDRA and ADDRB +***********************************************************************************************************/ + always @(posedge recovery_a or posedge recovery_b) begin + if (((wr_mode_a == 2'b01) && (wr_mode_b == 2'b01)) || + ((wr_mode_a != 2'b01) && (wr_mode_b != 2'b01))) begin + if (wea_int == 1 && web_int == 1) begin + if (addra_int < c_depth_a) + for (dmi = 0; dmi < c_width_a; dmi = dmi + 1) begin + for (dmj = 0; dmj < c_width_b; dmj = dmj + 1) begin + if ((addra_int * c_width_a + dmi) == (addrb_int * c_width_b + dmj)) begin + mem[addra_int * c_width_a + dmi] <= 1'bX; + end + end + end + else + //Warning Condition: + //Write Mode PortA is "Read First" and Write Mode PortB is "Read First" and WEA = 1 and WEB = 1 and ADDRA out of the valid range + //or + //Write Mode PortA is not "Read First" and Write Mode PortB is not "Read First" and WEA = 1 and WEB = 1 and ADDRA out of the valid range + $display("Invalid Address Warning #1: Warning in %m at time %t: Port A address %d (%b) of block memory invalid. Valid depth configured as 0 to %d",$time,addra_int,addra_int,c_depth_a-1); + end + end + recovery_a <= 0; + recovery_b <= 0; + end + + always @(posedge recovery_a or posedge recovery_b) begin + if ((wr_mode_a == 2'b01) && (wr_mode_b != 2'b01)) begin + if (wea_int == 1 && web_int == 1) begin + if (addra_int < c_depth_a) + for (dni = 0; dni < c_width_a; dni = dni + 1) begin + for (dnj = 0; dnj < c_width_b; dnj = dnj + 1) begin + if ((addra_int * c_width_a + dni) == (addrb_int * c_width_b + dnj)) begin + mem[addra_int * c_width_a + dni] <= dia_int[dni]; + end + end + end + else + //Warning Condition: + //Write Mode PortA is "Read First" and Write Mode PortB is not "Read First" and WEA = 1 and WEB = 1 and ADDRA out of the valid range + $display("Invalid Address Warning #2: Warning in %m at time %t: Port A address %d (%b) of block memory invalid. Valid depth configured as 0 to %d",$time,addra_int,addra_int,c_depth_a-1); + end + end + end + + always @(posedge recovery_a or posedge recovery_b) begin + if ((wr_mode_a != 2'b01) && (wr_mode_b == 2'b01)) begin + if (wea_int == 1 && web_int == 1) begin + if (addrb_int < c_depth_b) + for (doi = 0; doi < c_width_a; doi = doi + 1) begin + for (doj = 0; doj < c_width_b; doj = doj + 1) begin + if ((addra_int * c_width_a + doi) == (addrb_int * c_width_b + doj)) begin + mem[addrb_int * c_width_b + doj] <= dib_int[doj]; + end + end + end + else + //Warning Condition: + //Write Mode PortA is not "Read First" and Write Mode PortB is "Read First" and WEA = 1 and WEB = 1 and ADDRB out of the valid range + $display("Invalid Address Warning #3: Warning in %m at time %t: Port B address %d (%b) of block memory invalid. Valid depth configured as 0 to %d",$time,addrb_int,addrb_int,c_depth_b-1); + end + end + end +/*********************************************************************************************************** +*The following 4 always blocks handle memory outputs for the case of an address collision on ADDRA and ADDRB +***********************************************************************************************************/ + always @(posedge recovery_a or posedge recovery_b) begin + if ((wr_mode_b == 2'b00) || (wr_mode_b == 2'b10)) begin + if ((wea_int == 0) && (web_int == 1) && (ssra_int == 0)) begin + if (addra_int < c_depth_a) + for (dai = 0; dai < c_width_a; dai = dai + 1) begin + for (daj = 0; daj < c_width_b; daj = daj + 1) begin + if ((addra_int * c_width_a + dai) == (addrb_int * c_width_b + daj)) begin + doa_out[dai] <= 1'bX; + end + end + end + else + //Warning Condition: + //Write Mode PortB is "Write First" and WEA = 0 and WEB = 1 and SINITA = 0 and ADDRA out of the valid range + //or + //Write Mode PortB is "No Change" and WEA = 0 and WEB = 1 and SINITA = 0 and ADDRA out of the valid range + $display("Invalid Address Warning #4: Warning in %m at time %t: Port A address %d (%b) of block memory invalid. Valid depth configured as 0 to %d",$time,addra_int,addra_int,c_depth_a-1); + end + end + end + + always @(posedge recovery_a or posedge recovery_b) begin + if ((wr_mode_a == 2'b00) || (wr_mode_a == 2'b10)) begin + if ((wea_int == 1) && (web_int == 0) && (ssrb_int == 0)) begin + if (addrb_int < c_depth_b) + for (dbi = 0; dbi < c_width_a; dbi = dbi + 1) begin + for (dbj = 0; dbj < c_width_b; dbj = dbj + 1) begin + if ((addra_int * c_width_a + dbi) == (addrb_int * c_width_b + dbj)) begin + dob_out[dbj] <= 1'bX; + end + end + end + else + //Warning Condition: + //Write Mode PortA is "Write First" and WEA = 1 and WEB = 0 and SINITB = 0 and ADDRB out of the valid range + //or + //Write Mode PortA is "No Change" and WEA = 1 and WEB = 0 and SINITB = 0 and ADDRB out of the valid range + $display("Invalid Address Warning #5: Warning in %m at time %t: Port B address %d (%b) of block memory invalid. Valid depth configured as 0 to %d",$time,addrb_int,addrb_int,c_depth_b-1); + end + end + end + + always @(posedge recovery_a or posedge recovery_b) begin + if (((wr_mode_a == 2'b00) && (wr_mode_b == 2'b00)) || + ((wr_mode_a != 2'b10) && (wr_mode_b == 2'b10)) || + ((wr_mode_a == 2'b01) && (wr_mode_b == 2'b00))) begin + if ((wea_int == 1) && (web_int == 1) && (ssra_int == 0)) begin + if (addra_int < c_depth_a) + for (dci = 0; dci < c_width_a; dci = dci + 1) begin + for (dcj = 0; dcj < c_width_b; dcj = dcj + 1) begin + if ((addra_int * c_width_a + dci) == (addrb_int * c_width_b + dcj)) begin + doa_out[dci] <= 1'bX; + end + end + end + else + //Warning Condition: + //Write Mode PortA is "Write First" and Write Mode PortB is "Write First" and WEA = 1 and WEB = 1 and SINITA = 0 and ADDRA out of the valid range + //or + //Write Mode PortA is not "No Change" and Write Mode PortB is "No Change" and WEA = 1 and WEB = 1 and SINITA = 0 and ADDRA out of the valid range + //or + //Write Mode PortA is "Read First" and Write Mode PortB is "Write First" and WEA = 1 and WEB = 1 and SINITA = 0 and ADDRA out of the valid range + $display("Invalid Address Warning #6: Warning in %m at time %t: Port A address %d (%b) of block memory invalid. Valid depth configured as 0 to %d",$time,addra_int,addra_int,c_depth_a-1); + end + end + end + + always @(posedge recovery_a or posedge recovery_b) begin + if (((wr_mode_a == 2'b00) && (wr_mode_b == 2'b00)) || + ((wr_mode_a == 2'b10) && (wr_mode_b != 2'b10)) || + ((wr_mode_a == 2'b00) && (wr_mode_b == 2'b01))) begin + if ((wea_int == 1) && (web_int == 1) && (ssrb_int == 0)) begin + if (addrb_int < c_depth_b) + for (ddi = 0; ddi < c_width_a; ddi = ddi + 1) begin + for (ddj = 0; ddj < c_width_b; ddj = ddj + 1) begin + if ((addra_int * c_width_a + ddi) == (addrb_int * c_width_b + ddj)) begin + dob_out[ddj] <= 1'bX; + end + end + end + else + //Warning Condition: + //Write Mode PortA is "Write First" and Write Mode PortB is "Write First" and WEA = 1 and WEB = 1 and SINITB = 0 and ADDRB out of the valid range + //or + //Write Mode PortA is "No Change" and Write Mode PortB is not "No Change" and WEA = 1 and WEB = 1 and SINITB = 0 and ADDRB out of the valid range + //or + //Write Mode PortA is "Write First" and Write Mode PortB is "Read First" and WEA = 1 and WEB = 1 and SINITB = 0 and ADDRB out of the valid range + $display("Invalid Address Warning #7: Warning in %m at time %t: Port B address %d (%b) of block memory invalid. Valid depth configured as 0 to %d",$time,addrb_int,addrb_int,c_depth_b-1); + end + end + end + + // Parity Section is deleted + + initial begin + case (c_write_modea) + `c_write_first : wr_mode_a <= 2'b00; + `c_read_first : wr_mode_a <= 2'b01; + `c_no_change : wr_mode_a <= 2'b10; + default : begin + $display("Error in %m at time %t: c_write_modea = %s is not WRITE_FIRST, READ_FIRST or NO_CHANGE.",$time, c_write_modea); + $finish; + end + endcase + end + + initial begin + case (c_write_modeb) + `c_write_first : wr_mode_b <= 2'b00; + `c_read_first : wr_mode_b <= 2'b01; + `c_no_change : wr_mode_b <= 2'b10; + default : begin + $display("Error in %m at time %t: c_write_modeb = %s is not WRITE_FIRST, READ_FIRST or NO_CHANGE.",$time, c_write_modeb); + $finish; + end + endcase + end + +// Port A + + +// Generate ouput control signals for Port A: RFDA and RDYA + + always @ (rfda_int or rdya_int) + begin + if (c_has_rfda == 1) + RFDA = rfda_int ; + else + RFDA = 1'b0 ; + + if ((c_has_rdya == 1) && (c_has_nda == 1) && (c_has_rfda == 1) ) + RDYA = rdya_int; + else + RDYA = 1'b0 ; + end + + always @ (ena_int ) + begin + if (ena_int == 1'b1) + rfda_int <= 1'b1 ; + else + rfda_int <= 1'b0 ; + end + +// Gate nd signal with en + + assign nda_int = ena_int && nda_i ; + +// Register hanshaking signals for port A + + always @ (posedge clka_int) + begin + if (ena_int == 1'b1) + begin + if (ssra_int == 1'b1) + nda_q <= 1'b0 ; + else + nda_q <= nda_int ; + end + else + nda_q <= nda_q ; + end + +// Register data/ address / we inputs for port A + + always @ (posedge clka_int) + begin + if (ena_int == 1'b1) + begin + dia_q <= dia_i ; + addra_q <= addra_i ; + wea_q <= wea_i ; + end + end + + +// Select registered or non-registered write enable for Port A + + always @ ( wea_i or wea_q ) + begin + if (c_reg_inputsa == 1) + wea_int = wea_q ; + else + wea_int = wea_i ; + end + +// Select registered or non-registered data/address/nd inputs for Port A + + always @ ( dia_i or dia_q ) + begin + if ( c_reg_inputsa == 1) + dia_int = dia_q; + else + dia_int = dia_i; + end + + always @ ( addra_i or addra_q or nda_q or nda_int ) + begin + if ( c_reg_inputsa == 1) + begin + addra_int = addra_q ; + new_data_a = nda_q ; + end + else + begin + addra_int = addra_i; + new_data_a = nda_int ; + end + end + +// Register the new_data signal for Port A to track the synchronous RAM output + + always @(posedge clka_int) + begin + if (ena_int == 1'b1) + begin + if (ssra_int == 1'b1) + new_data_a_q <= 1'b0 ; + else + new_data_a_q <= new_data_a ; + end + end + +// Generate data outputs for Port A + + + /*************************************************************** + *The following always block assigns the value for the DOUTA bus + ***************************************************************/ + always @(posedge clka_int) begin + if (ena_int == 1'b1) begin + if (ssra_int == 1'b1) begin + // for ( ai = 0; ai < c_width_a; ai = ai + 1) + // doa_out[ai] <= sinita_value[ai]; + doa_out <= sinita_value; + end + else begin + //The following IF block assigns the output for a write operation + if (wea_int == 1'b1) begin + if (wr_mode_a == 2'b00) begin + if (addra_int < c_depth_a) + // for ( aj = 0; aj < c_width_a; aj = aj + 1) + // doa_out[aj] <= dia_int[aj] ; + doa_out <= dia_int ; + else + //Warning Condition (Error occurs on rising edge of CLKA): + //Write Mode PortA is "Write First" and ENA = 1 and SINITA = 0 and WEA = 1 and ADDRA out of the valid range + $display("Invalid Address Warning #8: Warning in %m at time %t: Port A address %d (%b) of block memory invalid. Valid depth configured as 0 to %d",$time,addra_int,addra_int,c_depth_a-1); + end + else if (wr_mode_a == 2'b01) begin + if (addra_int < c_depth_a) + // for ( ak = 0; ak < c_width_a; ak = ak + 1) + // doa_out[ak] <= mem[(addra_int*c_width_a) + ak]; + doa_out <= mem >> (addra_int*c_width_a); + else + //Warning Condition (Error occurs on rising edge of CLKA): + //Write Mode PortA is "Read First" and ENA = 1 and SINITA = 0 and WEA = 1 and ADDRA out of the valid range + $display("Invalid Address Warning #9: Warning in %m at time %t: Port A address %d (%b) of block memory invalid. Valid depth configured as 0 to %d",$time,addra_int,addra_int,c_depth_a-1); + end + else begin + if (addra_int < c_depth_a) + doa_out <= doa_out; + else + //Warning Condition (Error occurs on rising edge of CLKA): + //Write Mode PortA is "No Change" and ENA = 1 and SINITA = 0 and WEA = 1 and ADDRA out of the valid range + $display("Invalid Address Warning #10: Warning in %m at time %t: Port A address %d (%b) of block memory invalid. Valid depth configured as 0 to %d",$time,addra_int,addra_int,c_depth_a-1); + end + end + //The following ELSE block assigns the output for a read operation + else begin + if (addra_int < c_depth_a) + // for ( al = 0; al < c_width_a; al = al + 1) + // doa_out[al] <= mem[(addra_int*c_width_a) + al]; + doa_out <= mem >> (addra_int*c_width_a); + else begin + if (c_has_douta == 1)//New IF statement to remove read errors when port is write only + begin + //Warning Condition (Error occurs on rising edge of CLKA): + //ENA = 1 and SINITA = 0 and WEA = 0 and ADDRA out of the valid range + $display("Invalid Address Warning #11: Warning in %m at time %t: Port A address %d (%b) of block memory invalid. Valid depth configured as 0 to %d",$time,addra_int,addra_int,c_depth_a-1); + end + end + end + end + end + end + /*************************************************************************************** + *The following always block assigns the DINA bus to the memory during a write operation + ***************************************************************************************/ + always @(posedge clka_int) begin + if (ena_int == 1'b1 && wea_int == 1'b1) begin + if (addra_int < c_depth_a) + for ( am = 0; am < c_width_a; am = am + 1) + mem[(addra_int*c_width_a) + am] <= dia_int[am]; + else + //Warning Condition (Error occurs on rising edge of CLKA): + //ENA = 1 and WEA = 1 and ADDRA out of the valid range + $display("Invalid Address Warning #12: Warning in %m at time %t: Port A address %d (%b) of block memory invalid. Valid depth configured as 0 to %d",$time,addra_int,addra_int,c_depth_a-1); + end + end + + // output pipelines for Port A + + always @(posedge clka_int) begin + if (ena_int == 1'b1 && c_pipe_stages_a > 0) + begin + for (i = c_pipe_stages_a; i >= 1; i = i -1 ) + begin + if (ssra_int == 1'b1 && ena_int == 1'b1 ) + begin + pipelinea[i] <= sinita_value ; + sub_rdy_a[i] <= 0 ; + end + else + begin + if (i==1) + begin + pipelinea[i] <= doa_out ; + sub_rdy_a[i] <= new_data_a_q ; + end + else + + begin + pipelinea[i] <= pipelinea[i-1] ; + sub_rdy_a[i] <= sub_rdy_a[i-1] ; + end + end + end + end + end + +// Select pipeline output if c_pipe_stages_a > 0 + + always @( pipelinea[c_pipe_stages_a] or sub_rdy_a[c_pipe_stages_a] or new_data_a_q or doa_out ) begin + if (c_pipe_stages_a == 0 ) + begin + douta_out = doa_out ; + rdya_int = new_data_a_q; + end + else + begin + douta_out = pipelinea[c_pipe_stages_a]; + rdya_int = sub_rdy_a[c_pipe_stages_a]; + end + end + + + // Select Port A data outputs based on c_has_douta parameter + + always @( douta_out ) begin + if ( c_has_douta == 1) + douta_mux_out = douta_out ; + else + douta_mux_out = 0 ; + end + + + +// Port B + + + +// Generate output control signals for Port B: RFDB and RDYB + + always @ (rfdb_int or rdyb_int) + begin + if (c_has_rfdb == 1) + RFDB = rfdb_int ; + else + RFDB = 1'b0 ; + + if ((c_has_rdyb == 1) && (c_has_ndb == 1) && (c_has_rfdb == 1) ) + RDYB = rdyb_int; + else + RDYB = 1'b0 ; + end + + always @ (enb_int ) + begin + if ( enb_int == 1'b1 ) + rfdb_int = 1'b1 ; + else + rfdb_int = 1'b0 ; + end + +// Gate nd signal with en + + assign ndb_int = enb_int && ndb_i ; + +// Register hanshaking signals for port B + + always @ (posedge clkb_int) + begin + if (enb_int == 1'b1) + begin + if (ssrb_int == 1'b1) + ndb_q <= 1'b0 ; + else + ndb_q <= ndb_int ; + end + else + ndb_q <= ndb_q; + end + +// Register data / address / we inputs for port B + + always @ (posedge clkb_int) + begin + if (enb_int == 1'b1) + begin + dib_q <= dib_i ; + addrb_q <= addrb_i ; + web_q <= web_i ; + end + end + +// Select registered or non-registered write enable for port B + + always @ (web_i or web_q ) + begin + if (c_reg_inputsb == 1) + web_int = web_q ; + else + web_int = web_i ; + end + + + +// Select registered or non-registered data/address/nd inputs for Port B + + always @ ( dib_i or dib_q ) + begin + if ( c_reg_inputsb == 1) + dib_int = dib_q; + else + dib_int = dib_i; + end + + always @ ( addrb_i or addrb_q or ndb_q or ndb_int) + begin + if ( c_reg_inputsb == 1) + begin + addrb_int = addrb_q ; + new_data_b = ndb_q ; + end + else + begin + addrb_int = addrb_i; + new_data_b = ndb_int ; + end + end + +// Register the new_data signal for Port B to track the synchronous RAM output + + always @(posedge clkb_int) + begin + if (enb_int == 1'b1 ) + begin + if (ssrb_int == 1'b1) + new_data_b_q <= 1'b0 ; + else + new_data_b_q <= new_data_b ; + end + end + + + + + +// Generate data outputs for Port B + + + /*************************************************************** + *The following always block assigns the value for the DOUTB bus + ***************************************************************/ + always @(posedge clkb_int) begin + if (enb_int == 1'b1) begin + if (ssrb_int == 1'b1) begin + // for (bi = 0; bi < c_width_b; bi = bi + 1) + // dob_out[bi] <= sinitb_value[bi]; + dob_out <= sinitb_value; + end + else begin + //The following IF block assigns the output for a write operation + if (web_int == 1'b1) begin + if (wr_mode_b == 2'b00) begin + if (addrb_int < c_depth_b) + // for (bj = 0; bj < c_width_b; bj = bj + 1) + // dob_out[bj] <= dib_int[bj]; + dob_out <= dib_int; + else + //Warning Condition (Error occurs on rising edge of CLKB): + //Write Mode PortB is "Write First" and ENB = 1 and SINITB = 0 and WEB = 1 and ADDRB out of the valid range + $display("Invalid Address Warning #13: Warning in %m at time %t: Port B address %d (%b) of block memory invalid. Valid depth configured as 0 to %d",$time,addrb_int,addrb_int,c_depth_b-1); + end + else if (wr_mode_b == 2'b01) begin + if (addrb_int < c_depth_b) + // for (bk = 0; bk < c_width_b; bk = bk + 1) + // dob_out[bk] <= mem[(addrb_int*c_width_b) + bk]; + dob_out <= mem >> (addrb_int*c_width_b); + else + //Warning Condition (Error occurs on rising edge of CLKB): + //Write Mode PortB is "Read First" and ENB = 1 and SINITB = 0 and WEB = 1 and ADDRB out of the valid range + $display("Invalid Address Warning #14: Warning in %m at time %t: Port B address %d (%b) of block memory invalid. Valid depth configured as 0 to %d",$time,addrb_int,addrb_int,c_depth_b-1); + end + else begin + if (addrb_int < c_depth_b) + dob_out <= dob_out ; + else + //Warning Condition (Error occurs on rising edge of CLKB): + //Write Mode PortB is "No Change" and ENB = 1 and SINITB = 0 and WEB = 1 and ADDRB out of the valid range + $display("Invalid Address Warning #15: Warning in %m at time %t: Port B address %d (%b) of block memory invalid. Valid depth configured as 0 to %d",$time,addrb_int,addrb_int,c_depth_b-1); + end + end + //The following ELSE block assigns the output for a read operation + else begin + if (addrb_int < c_depth_b) + // for (bl = 0; bl < c_width_b; bl = bl + 1) + // dob_out[bl] <= mem[(addrb_int*c_width_b) + bl]; + dob_out <= mem >> (addrb_int*c_width_b); + else begin + if (c_has_doutb == 1)//New IF statement to remove read errors when port is write only + begin + //Warning Condition (Error occurs on rising edge of CLKB): + //ENB = 1 and SINITB = 0 and WEB = 0 and ADDRB out of the valid range + $display("Invalid Address Warning #16: Warning in %m at time %t: Port B address %d (%b) of block memory invalid. Valid depth configured as 0 to %d",$time,addrb_int,addrb_int,c_depth_b-1); + end + end + end + end + end + end + /*************************************************************************************** + *The following always block assigns the DINA bus to the memory during a write operation + ***************************************************************************************/ + always @(posedge clkb_int) begin + if (enb_int == 1'b1 && web_int == 1'b1) begin + if (addrb_int < c_depth_b) + for (bm = 0; bm < c_width_b; bm = bm + 1) + mem[(addrb_int*c_width_b) + bm] <= dib_int[bm]; + else + //Warning Condition (Error occurs on rising edge of CLKB): + //ENB = 1 and WEB = 1 and ADDRB out of the valid range + $display("Invalid Address Warning #17: Warning in %m at time %t: Port B address %d (%b) of block memory invalid. Valid depth configured as 0 to %d",$time,addrb_int,addrb_int,c_depth_b-1); + end + end + + // output pipelines for Port B + + always @(posedge clkb_int) begin + if (enb_int == 1'b1 && c_pipe_stages_b > 0) + begin + for (j = c_pipe_stages_b; j >= 1; j = j -1 ) + begin + if (ssrb_int == 1'b1 && enb_int == 1'b1 ) + begin + pipelineb[j] <= sinitb_value ; + sub_rdy_b[j] <= 0 ; + end + else + begin + if (j==1) + begin + pipelineb[j] <= dob_out ; + sub_rdy_b[j] <= new_data_b_q ; + end + else + begin + pipelineb[j] <= pipelineb[j-1] ; + sub_rdy_b[j] <= sub_rdy_b[j-1] ; + end + end + end + end + end + +// Select pipeline for B if c_pipe_stages_b > 0 + + always @(pipelineb[c_pipe_stages_b] or sub_rdy_b[c_pipe_stages_b] or new_data_b_q or dob_out) begin + if ( c_pipe_stages_b == 0 ) + begin + doutb_out = dob_out ; + rdyb_int = new_data_b_q; + end + else + begin + rdyb_int = sub_rdy_b[c_pipe_stages_b]; + doutb_out = pipelineb[c_pipe_stages_b]; + end + end + + +// Select Port B data outputs based on c_has_doutb parameter + + always @( doutb_out) begin + if ( c_has_doutb == 1) + doutb_mux_out = doutb_out ; + else + doutb_mux_out = 0 ; + end + + + + + + specify + + // when both CLKA and CLKB are active on the positive edge + $recovery (posedge CLKB, posedge CLKA &&& collision_posa_posb, 1, recovery_b); + $recovery (posedge CLKA, posedge CLKB &&& collision_posa_posb, 1, recovery_a); + + // when both CLKA active on positive edge and CLKB are active on the negative edge + $recovery (negedge CLKB, posedge CLKA &&& collision_posa_negb, 1, recovery_b); + $recovery (posedge CLKA, negedge CLKB &&& collision_posa_negb, 1, recovery_a); + + // when both CLKA active on negative edge and CLKB are active on the positive edge + $recovery (posedge CLKB, negedge CLKA &&& collision_nega_posb, 1, recovery_b); + $recovery (negedge CLKA, posedge CLKB &&& collision_nega_posb, 1, recovery_a); + + // when both CLKA and CLKB are active on the negative edge + $recovery (negedge CLKB, negedge CLKA &&& collision_nega_negb, 1, recovery_b); + $recovery (negedge CLKA, negedge CLKB &&& collision_nega_negb, 1, recovery_a); + + endspecify + +endmodule + +`endcelldefine diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/BLKMEMDP_V6_0.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/BLKMEMDP_V6_0.v new file mode 100644 index 0000000..520fb5a --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/BLKMEMDP_V6_0.v @@ -0,0 +1,1315 @@ +// Copyright(C) 2003 by Xilinx, Inc. All rights reserved. +// This text/file contains proprietary, confidential +// information of Xilinx, Inc., is distributed under license +// from Xilinx, Inc., and may be used, copied and/or +// disclosed only pursuant to the terms of a valid license +// agreement with Xilinx, Inc. Xilinx hereby grants you +// a license to use this text/file solely for design, simulation, +// implementation and creation of design files limited +// to Xilinx devices or technologies. Use with non-Xilinx +// devices or technologies is expressly prohibited and +// immediately terminates your license unless covered by +// a separate agreement. +// +// Xilinx is providing this design, code, or information +// "as is" solely for use in developing programs and +// solutions for Xilinx devices. By providing this design, +// code, or information as one possible implementation of +// this feature, application or standard, Xilinx is making no +// representation that this implementation is free from any +// claims of infringement. You are responsible for +// obtaining any rights you may require for your implementation. +// Xilinx expressly disclaims any warranty whatsoever with +// respect to the adequacy of the implementation, including +// but not limited to any warranties or representations that this +// implementation is free from claims of infringement, implied +// warranties of merchantability or fitness for a particular +// purpose. +// +// Xilinx products are not intended for use in life support +// appliances, devices, or systems. Use in such applications are +// expressly prohibited. +// +// This copyright and support notice must be retained as part +// of this text at all times. (c) Copyright 1995-2003 Xilinx, Inc. +// All rights reserved. + +/************************************************************************** + * $RCSfile: BLKMEMDP_V6_0.v,v $ $Revision: 1.13 $ $Date: 2008/09/08 20:06:26 $ + ************************************************************************** + * Dual Port Block Memory - Verilog Behavioral Model + * ************************************************************************ + * + * + ************************************************************************* + * Filename: BLKMEMDP_V6_0.v + * + * Description: The Verilog behavioral model for the Dual Port Block Memory + * + * *********************************************************************** + */ + +`timescale 1ns/10ps +`celldefine + + +`define c_dp_rom 4 +`define c_dp_ram 2 +`define c_write_first 0 +`define c_read_first 1 +`define c_no_change 2 + +module BLKMEMDP_V6_0(DOUTA, DOUTB, ADDRA, CLKA, DINA, ENA, SINITA, WEA, NDA, RFDA, RDYA, ADDRB, CLKB, DINB, ENB, SINITB, WEB,NDB, RFDB, RDYB); + + + + parameter c_addra_width = 11 ; + parameter c_addrb_width = 9 ; + parameter c_default_data = "0"; // indicates string of hex characters used to initialize memory + parameter c_depth_a = 2048 ; + parameter c_depth_b = 512 ; + parameter c_enable_rlocs = 0 ; // core includes placement constraints + parameter c_has_default_data = 1; + parameter c_has_dina = 1 ; // indicate port A has data input pins + parameter c_has_dinb = 1 ; // indicate port B has data input pins + parameter c_has_douta = 1 ; // indicates port A has output + parameter c_has_doutb = 1 ; // indicates port B has output + parameter c_has_ena = 1 ; // indicates port A has a ENA pin + parameter c_has_enb = 1 ; // indicates port B has a ENB pin + parameter c_has_limit_data_pitch = 1 ; + parameter c_has_nda = 0 ; // Port A has a new data pin + parameter c_has_ndb = 0 ; // Port B has a new data pin + parameter c_has_rdya = 0 ; // Port A has result ready pin + parameter c_has_rdyb = 0 ; // Port B has result ready pin + parameter c_has_rfda = 0 ; // Port A has ready for data pin + parameter c_has_rfdb = 0 ; // Port B has ready for data pin + parameter c_has_sinita = 1 ; // indicates port A has a SINITA pin + parameter c_has_sinitb = 1 ; // indicates port B has a SINITB pin + parameter c_has_wea = 1 ; // indicates port A has a WEA pin + parameter c_has_web = 1 ; // indicates port B has a WEB pin + parameter c_limit_data_pitch = 16 ; + parameter c_mem_init_file = "null.mif"; // controls which .mif file used to initialize memory + parameter c_pipe_stages_a = 0 ; // indicates the number of pipe stages needed in port A + parameter c_pipe_stages_b = 0 ; // indicates the number of pipe stages needed in port B + parameter c_reg_inputsa = 0 ; // indicates we, addr, and din of port A are registered + parameter c_reg_inputsb = 0 ; // indicates we, addr, and din of port B are registered + parameter c_sinita_value = "0000"; // indicates string of hex used to initialize A output registers + parameter c_sinitb_value = "0000"; // indicates string of hex used to initialize B output resisters + parameter c_width_a = 8 ; + parameter c_width_b = 32 ; + parameter c_write_modea = 2; // controls which write modes shall be used + parameter c_write_modeb = 2; // controls which write modes shall be used + + // New Generics for Primitive Selection and Pin Polarity + parameter c_ybottom_addr = "1024"; + parameter c_yclka_is_rising = 1; // controls the active edge of the CLKA Pin + parameter c_yclkb_is_rising = 1; // controls the active edge of the CLKB Pin + parameter c_yena_is_high = 1; // controls the polarity of the ENA Pin + parameter c_yenb_is_high = 1; // controls the polarity of the ENB Pin + parameter c_yhierarchy = "hierarchy1"; + parameter c_ymake_bmm = 0; + parameter c_yprimitive_type = "4kx4"; // Indicates which primitive should be used to build the + // memory if c_yuse_single_primitive=1 + parameter c_ysinita_is_high = 1; // controls the polarity of the SINITA Pin + parameter c_ysinitb_is_high = 1; // controls the polarity of the SINITB Pin + parameter c_ytop_addr = "0"; + parameter c_yuse_single_primitive = 0; // controls whether the Memory is build out of a + // user selected primitive or is built from multiple + // primitives with the "optimize for area" algorithm used + parameter c_ywea_is_high = 1; // controls the polarity of the WEA Pin + parameter c_yweb_is_high = 1; // controls the polarity of the WEB Pin + + parameter c_yydisable_warnings = 1; //1=no warnings, 0=print warnings + + +// IO ports + + + + output [c_width_a-1:0] DOUTA; + + input [c_addra_width-1:0] ADDRA; + input [c_width_a-1:0] DINA; + input ENA, CLKA, WEA, SINITA, NDA; + output RFDA, RDYA; + + output [c_width_b-1:0] DOUTB; + + input [c_addrb_width-1:0] ADDRB; + input [c_width_b-1:0] DINB; + input ENB, CLKB, WEB, SINITB, NDB; + output RFDB, RDYB; + + +// internal signals + + reg [c_width_a-1:0] douta_mux_out ; // output of multiplexer -- + wire [c_width_a-1:0] DOUTA = douta_mux_out; + reg RFDA, RDYA ; + + reg [c_width_b-1:0] doutb_mux_out ; // output of multiplexer -- + wire [c_width_b-1:0] DOUTB = doutb_mux_out; + reg RFDB, RDYB; + + + reg [c_width_a-1:0] douta_out_q; // registered output of douta_out + reg [c_width_a-1:0] doa_out; // output of Port A RAM + reg [c_width_a-1:0] douta_out; // output of pipeline mux for port A + + reg [c_width_b-1:0] doutb_out_q ; // registered output for doutb_out + reg [c_width_b-1:0] dob_out; // output of Port B RAM + reg [c_width_b-1:0] doutb_out ; // output of pipeline mux for port B + + reg [c_depth_a*c_width_a-1 : 0] mem; + reg [24:0] count ; + reg [1:0] wr_mode_a, wr_mode_b; + + reg [(c_width_a-1) : 0] pipelinea [0 : c_pipe_stages_a]; + reg [(c_width_b-1) : 0] pipelineb [0 : c_pipe_stages_b]; + reg sub_rdy_a[0 : c_pipe_stages_a]; + reg sub_rdy_b[0 : c_pipe_stages_b]; + + reg [10:0] ci, cj; + reg [10:0] dmi, dmj, dni, dnj, doi, doj, dai, daj, dbi, dbj, dci, dcj, ddi, ddj; + reg [10:0] pmi, pmj, pni, pnj, poi, poj, pai, paj, pbi, pbj, pci, pcj, pdi, pdj; + integer ai, aj, ak, al, am, an, ap ; + integer bi, bj, bk, bl, bm, bn, bp ; + integer i, j, k, l, m, n, p; + + wire [c_addra_width-1:0] addra_i = ADDRA; + reg [c_width_a-1:0] dia_int ; + reg [c_width_a-1:0] dia_q ; + wire [c_width_a-1:0] dia_i ; + wire ena_int ; + reg ena_q ; + wire clka_int ; + reg wea_int ; + wire wea_i ; + reg wea_q ; + wire ssra_int ; + wire nda_int ; + wire nda_i ; + reg rfda_int ; + reg rdya_int ; + reg nda_q ; + reg new_data_a ; + reg new_data_a_q ; + reg [c_addra_width-1:0] addra_q; + reg [c_addra_width-1:0] addra_int; + reg [c_width_a-1:0] sinita_value ; // initialization value for output registers of Port A + + wire [c_addrb_width-1:0] addrb_i = ADDRB; + reg [c_width_b-1:0] dib_int ; + reg [c_width_b-1:0] dib_q ; + wire [c_width_b-1:0] dib_i ; + wire enb_int ; + reg enb_q ; + wire clkb_int ; + reg web_int ; + wire web_i ; + reg web_q ; + wire ssrb_int ; + wire ndb_int ; + wire ndb_i ; + reg rfdb_int ; + reg rdyb_int ; + reg ndb_q ; + reg new_data_b ; + reg new_data_b_q ; + reg [c_addrb_width-1:0] addrb_q ; + reg [c_addrb_width-1:0] addrb_int ; + reg [c_width_b-1:0] sinitb_value ; // initialization value for output registers of Port B + +// variables used to initialize memory contents to default values. + + reg [c_width_a-1:0] bitval ; + reg [c_width_a-1:0] ram_temp [0:c_depth_a-1] ; + reg [c_width_a-1:0] default_data ; + +// variables used to detect address collision on dual port Rams + + reg recovery_a, recovery_b; + reg address_collision; + + wire clka_enable_pp = ena_int && wea_int && enb_int && address_collision + && c_yclka_is_rising && c_yclkb_is_rising; + wire clkb_enable_pp = enb_int && web_int && ena_int && address_collision + && c_yclka_is_rising && c_yclkb_is_rising; + wire collision_posa_posb = clka_enable_pp || clkb_enable_pp; + + // For posedge clka and negedge clkb + + wire clka_enable_pn = ena_int && wea_int && enb_int && address_collision + && c_yclka_is_rising && (!c_yclkb_is_rising); + wire clkb_enable_pn = enb_int && web_int && ena_int && address_collision + && c_yclka_is_rising && (!c_yclkb_is_rising); + wire collision_posa_negb = clka_enable_pn || clkb_enable_pn; + + // For negedge clka and posedge clkb + + wire clka_enable_np = ena_int && wea_int && enb_int && address_collision + && (!c_yclka_is_rising) && c_yclkb_is_rising; + wire clkb_enable_np = enb_int && web_int && ena_int && address_collision + && (!c_yclka_is_rising) && c_yclkb_is_rising; + wire collision_nega_posb = clka_enable_np || clkb_enable_np; + + // For negedge clka and clkb + + wire clka_enable_nn = ena_int && wea_int && enb_int && address_collision + && (!c_yclka_is_rising) && (!c_yclkb_is_rising); + wire clkb_enable_nn = enb_int && web_int && ena_int && address_collision + && (!c_yclka_is_rising) && (!c_yclkb_is_rising); + wire collision_nega_negb = clka_enable_nn || clkb_enable_nn; + + +// tri0 GSR = glbl.GSR; + + assign dia_i = (c_has_dina === 1)?DINA:'b0; + assign ena_int = defval(ENA, c_has_ena, 1, c_yena_is_high); + assign ssra_int = defval(SINITA, c_has_sinita, 0, c_ysinita_is_high); + assign nda_i = defval(NDA, c_has_nda, 1, 1); + assign clka_int = defval(CLKA, 1, 1, c_yclka_is_rising); + + assign dib_i = (c_has_dinb === 1)?DINB:'b0; + assign enb_int = defval(ENB, c_has_enb, 1, c_yenb_is_high); + assign ssrb_int = defval(SINITB, c_has_sinitb, 0, c_ysinitb_is_high); + assign ndb_i = defval(NDB, c_has_ndb, 1, 1); + assign clkb_int = defval(CLKB, 1, 1, c_yclkb_is_rising); + +// RAM/ROM functionality + + assign wea_i = defval(WEA, c_has_wea, 0, c_ywea_is_high); + assign web_i = defval(WEB, c_has_web, 0, c_yweb_is_high); + + + function defval; + input i; + input hassig; + input val; + input active_high; + begin + if(hassig == 1) + begin + if (active_high == 1) + defval = i; + else + defval = ~i; + end + else + defval = val; + end + endfunction + + function max; + input a; + input b; + begin + max = (a > b) ? a : b; + end + endfunction + + function a_is_X; + input [c_width_a-1 : 0] i; + integer j ; + begin + a_is_X = 1'b0; + for(j = 0; j < c_width_a; j = j + 1) + begin + if(i[j] === 1'bx) + a_is_X = 1'b1; + end // loop + end + endfunction + + function b_is_X; + input [c_width_b-1 : 0] i; + integer j ; + begin + b_is_X = 1'b0; + for(j = 0; j < c_width_b; j = j + 1) + begin + if(i[j] === 1'bx) + b_is_X = 1'b1; + end // loop + end + endfunction + + function [c_width_a-1:0] hexstr_conv; + input [(c_width_a*8)-1:0] def_data; + + integer index,i,j; + reg [3:0] bin; + + begin + index = 0; + hexstr_conv = 'b0; + for( i=c_width_a-1; i>=0; i=i-1 ) + begin + case (def_data[7:0]) + 8'b00000000 : + begin + bin = 4'b0000; + i = -1; + end + 8'b00110000 : bin = 4'b0000; + 8'b00110001 : bin = 4'b0001; + 8'b00110010 : bin = 4'b0010; + 8'b00110011 : bin = 4'b0011; + 8'b00110100 : bin = 4'b0100; + 8'b00110101 : bin = 4'b0101; + 8'b00110110 : bin = 4'b0110; + 8'b00110111 : bin = 4'b0111; + 8'b00111000 : bin = 4'b1000; + 8'b00111001 : bin = 4'b1001; + 8'b01000001 : bin = 4'b1010; + 8'b01000010 : bin = 4'b1011; + 8'b01000011 : bin = 4'b1100; + 8'b01000100 : bin = 4'b1101; + 8'b01000101 : bin = 4'b1110; + 8'b01000110 : bin = 4'b1111; + 8'b01100001 : bin = 4'b1010; + 8'b01100010 : bin = 4'b1011; + 8'b01100011 : bin = 4'b1100; + 8'b01100100 : bin = 4'b1101; + 8'b01100101 : bin = 4'b1110; + 8'b01100110 : bin = 4'b1111; + default : + begin + if (c_yydisable_warnings == 0) begin + $display("ERROR in %m at time %t: NOT A HEX CHARACTER",$time); + end + bin = 4'bx; + end + endcase + for( j=0; j<4; j=j+1) + begin + if ((index*4)+j < c_width_a) + begin + hexstr_conv[(index*4)+j] = bin[j]; + end + end + index = index + 1; + def_data = def_data >> 8; + end + end + endfunction + + function [c_width_b-1:0] hexstr_conv_b; + input [(c_width_b*8)-1:0] def_data; + + integer index,i,j; + reg [3:0] bin; + + begin + index = 0; + hexstr_conv_b = 'b0; + for( i=c_width_b-1; i>=0; i=i-1 ) + begin + case (def_data[7:0]) + 8'b00000000 : + begin + bin = 4'b0000; + i = -1; + end + 8'b00110000 : bin = 4'b0000; + 8'b00110001 : bin = 4'b0001; + 8'b00110010 : bin = 4'b0010; + 8'b00110011 : bin = 4'b0011; + 8'b00110100 : bin = 4'b0100; + 8'b00110101 : bin = 4'b0101; + 8'b00110110 : bin = 4'b0110; + 8'b00110111 : bin = 4'b0111; + 8'b00111000 : bin = 4'b1000; + 8'b00111001 : bin = 4'b1001; + 8'b01000001 : bin = 4'b1010; + 8'b01000010 : bin = 4'b1011; + 8'b01000011 : bin = 4'b1100; + 8'b01000100 : bin = 4'b1101; + 8'b01000101 : bin = 4'b1110; + 8'b01000110 : bin = 4'b1111; + 8'b01100001 : bin = 4'b1010; + 8'b01100010 : bin = 4'b1011; + 8'b01100011 : bin = 4'b1100; + 8'b01100100 : bin = 4'b1101; + 8'b01100101 : bin = 4'b1110; + 8'b01100110 : bin = 4'b1111; + default : + begin + if (c_yydisable_warnings == 0) begin + $display("ERROR in %m at time %t: NOT A HEX CHARACTER",$time); + end + bin = 4'bx; + end + endcase + for( j=0; j<4; j=j+1) + begin + if ((index*4)+j < c_width_b) + begin + hexstr_conv_b[(index*4)+j] = bin[j]; + end + end + index = index + 1; + def_data = def_data >> 8; + end + end + endfunction + + + + + +// Initialize memory contents to 0 for now . + + initial begin + sinita_value = 'b0 ; + sinitb_value = 'b0 ; + + default_data = hexstr_conv(c_default_data); + if (c_has_sinita == 1 ) + sinita_value = hexstr_conv(c_sinita_value); + if (c_has_sinitb == 1 ) + sinitb_value = hexstr_conv_b(c_sinitb_value); + for(i = 0; i < c_depth_a; i = i + 1) + ram_temp[i] = default_data; + if (c_has_default_data == 0) + $readmemb(c_mem_init_file, ram_temp) ; + + for(i = 0; i < c_depth_a; i = i + 1) + for(j = 0; j < c_width_a; j = j + 1) + begin + bitval = (1'b1 << j); + mem[(i*c_width_a) + j] = (ram_temp[i] & bitval) >> j; + end + recovery_a = 0; + recovery_b = 0; + for (k = 0; k <= c_pipe_stages_a; k = k + 1) + pipelinea[k] = sinita_value ; + for (l = 0; l <= c_pipe_stages_b; l = l + 1) + pipelineb[l] = sinitb_value ; + for (m = 0; m <= c_pipe_stages_a; m = m + 1) + sub_rdy_a[m] = 0 ; + for (n = 0; n <= c_pipe_stages_b; n = n + 1) + sub_rdy_b[n] = 0 ; + doa_out = sinita_value ; + dob_out = sinitb_value ; + nda_q = 0; + ndb_q = 0; + new_data_a_q = 0 ; + new_data_b_q = 0 ; + dia_q = 0; + dib_q = 0; + addra_q = 0; + addrb_q = 0; + wea_q = 0; + web_q = 0; + #1 douta_out = sinita_value; + #1 doutb_out = sinitb_value; + #1 rdya_int = 0; + #1 rdyb_int = 0; + end + + + always @(addra_int or addrb_int) begin // check address collision + address_collision <= 1'b0; + for (ci = 0; ci < c_width_a; ci = ci + 1) begin // absolute address A + for (cj = 0; cj < c_width_b; cj = cj + 1) begin // absolute address B + if ((addra_int * c_width_a + ci) == (addrb_int * c_width_b + cj)) begin + address_collision <= 1'b1; + end + end + end + end +/*********************************************************************************************************** +* The following 3 always blocks handle memory inputs for the case of an address collision on ADDRA and ADDRB +***********************************************************************************************************/ + always @(posedge recovery_a or posedge recovery_b) begin + if (((wr_mode_a == 2'b01) && (wr_mode_b == 2'b01)) || + ((wr_mode_a != 2'b01) && (wr_mode_b != 2'b01))) begin + if (wea_int == 1 && web_int == 1) begin + if (addra_int < c_depth_a) + for (dmi = 0; dmi < c_width_a; dmi = dmi + 1) begin + for (dmj = 0; dmj < c_width_b; dmj = dmj + 1) begin + if ((addra_int * c_width_a + dmi) == (addrb_int * c_width_b + dmj)) begin +//Fixed read-first collision +// mem[addra_int * c_width_a + dmi] <= 1'bX; + if ((wr_mode_a == 2'b01) && (wr_mode_b == 2'b01)) + begin + doa_out[dmi] <= 1'bX; + dob_out[dmj] <= 1'bX; + end + else + mem[addra_int * c_width_a + dmi] <= 1'bX; + end + end + end + else begin + //Warning Condition: + //Write Mode PortA is "Read First" and Write Mode PortB is "Read First" and WEA = 1 and WEB = 1 and ADDRA out of the valid range + //or + //Write Mode PortA is not "Read First" and Write Mode PortB is not "Read First" and WEA = 1 and WEB = 1 and ADDRA out of the valid range + if (c_yydisable_warnings == 0) begin + $display("Invalid Address Warning #1: Warning in %m at time %t: Port A address %d (%b) of block memory invalid. Valid depth configured as 0 to %d",$time,addra_int,addra_int,c_depth_a-1); + end + doa_out <= {c_width_a{1'bX}}; // assign data bus to X + end + end + end + recovery_a <= 0; + recovery_b <= 0; + end + + always @(posedge recovery_a or posedge recovery_b) begin + if ((wr_mode_a == 2'b01) && (wr_mode_b != 2'b01)) begin + if (wea_int == 1 && web_int == 1) begin + if (addra_int < c_depth_a) + for (dni = 0; dni < c_width_a; dni = dni + 1) begin + for (dnj = 0; dnj < c_width_b; dnj = dnj + 1) begin + if ((addra_int * c_width_a + dni) == (addrb_int * c_width_b + dnj)) begin + mem[addra_int * c_width_a + dni] <= dia_int[dni]; + end + end + end + else begin + //Warning Condition: + //Write Mode PortA is "Read First" and Write Mode PortB is not "Read First" and WEA = 1 and WEB = 1 and ADDRA out of the valid range + if (c_yydisable_warnings == 0) begin + $display("Invalid Address Warning #2: Warning in %m at time %t: Port A address %d (%b) of block memory invalid. Valid depth configured as 0 to %d",$time,addra_int,addra_int,c_depth_a-1); + end + doa_out <= {c_width_a{1'bX}}; // assign data bus to X + end + end + end + end + + always @(posedge recovery_a or posedge recovery_b) begin + if ((wr_mode_a != 2'b01) && (wr_mode_b == 2'b01)) begin + if (wea_int == 1 && web_int == 1) begin + if (addrb_int < c_depth_b) + for (doi = 0; doi < c_width_a; doi = doi + 1) begin + for (doj = 0; doj < c_width_b; doj = doj + 1) begin + if ((addra_int * c_width_a + doi) == (addrb_int * c_width_b + doj)) begin + mem[addrb_int * c_width_b + doj] <= dib_int[doj]; + end + end + end + else begin + //Warning Condition: + //Write Mode PortA is not "Read First" and Write Mode PortB is "Read First" and WEA = 1 and WEB = 1 and ADDRB out of the valid range + if (c_yydisable_warnings == 0) begin + $display("Invalid Address Warning #3: Warning in %m at time %t: Port B address %d (%b) of block memory invalid. Valid depth configured as 0 to %d",$time,addrb_int,addrb_int,c_depth_b-1); + end + dob_out <= {c_width_b{1'bX}}; // assign data bus to X + end + end + end + end +/*********************************************************************************************************** +*The following 4 always blocks handle memory outputs for the case of an address collision on ADDRA and ADDRB +***********************************************************************************************************/ + always @(posedge recovery_a or posedge recovery_b) begin + if ((wr_mode_b == 2'b00) || (wr_mode_b == 2'b10)) begin + if ((wea_int == 0) && (web_int == 1) && (ssra_int == 0)) begin + if (addra_int < c_depth_a) + for (dai = 0; dai < c_width_a; dai = dai + 1) begin + for (daj = 0; daj < c_width_b; daj = daj + 1) begin + if ((addra_int * c_width_a + dai) == (addrb_int * c_width_b + daj)) begin + doa_out[dai] <= 1'bX; + end + end + end + else begin + //Warning Condition: + //Write Mode PortB is "Write First" and WEA = 0 and WEB = 1 and SINITA = 0 and ADDRA out of the valid range + //or + //Write Mode PortB is "No Change" and WEA = 0 and WEB = 1 and SINITA = 0 and ADDRA out of the valid range + if (c_yydisable_warnings == 0) begin + $display("Invalid Address Warning #4: Warning in %m at time %t: Port A address %d (%b) of block memory invalid. Valid depth configured as 0 to %d",$time,addra_int,addra_int,c_depth_a-1); + end + doa_out <= {c_width_a{1'bX}}; // assign data bus to X + end + end + end + end + + always @(posedge recovery_a or posedge recovery_b) begin + if ((wr_mode_a == 2'b00) || (wr_mode_a == 2'b10)) begin + if ((wea_int == 1) && (web_int == 0) && (ssrb_int == 0)) begin + if (addrb_int < c_depth_b) + for (dbi = 0; dbi < c_width_a; dbi = dbi + 1) begin + for (dbj = 0; dbj < c_width_b; dbj = dbj + 1) begin + if ((addra_int * c_width_a + dbi) == (addrb_int * c_width_b + dbj)) begin + dob_out[dbj] <= 1'bX; + end + end + end + else begin + //Warning Condition: + //Write Mode PortA is "Write First" and WEA = 1 and WEB = 0 and SINITB = 0 and ADDRB out of the valid range + //or + //Write Mode PortA is "No Change" and WEA = 1 and WEB = 0 and SINITB = 0 and ADDRB out of the valid range + if (c_yydisable_warnings == 0) begin + $display("Invalid Address Warning #5: Warning in %m at time %t: Port B address %d (%b) of block memory invalid. Valid depth configured as 0 to %d",$time,addrb_int,addrb_int,c_depth_b-1); + end + dob_out <= {c_width_b{1'bX}}; // assign data bus to X + end + end + end + end + + always @(posedge recovery_a or posedge recovery_b) begin + if (((wr_mode_a == 2'b00) && (wr_mode_b == 2'b00)) || + ((wr_mode_a != 2'b10) && (wr_mode_b == 2'b10)) || + ((wr_mode_a == 2'b01) && (wr_mode_b == 2'b00))) begin + if ((wea_int == 1) && (web_int == 1) && (ssra_int == 0)) begin + if (addra_int < c_depth_a) + for (dci = 0; dci < c_width_a; dci = dci + 1) begin + for (dcj = 0; dcj < c_width_b; dcj = dcj + 1) begin + if ((addra_int * c_width_a + dci) == (addrb_int * c_width_b + dcj)) begin + doa_out[dci] <= 1'bX; + end + end + end + else begin + //Warning Condition: + //Write Mode PortA is "Write First" and Write Mode PortB is "Write First" and WEA = 1 and WEB = 1 and SINITA = 0 and ADDRA out of the valid range + //or + //Write Mode PortA is not "No Change" and Write Mode PortB is "No Change" and WEA = 1 and WEB = 1 and SINITA = 0 and ADDRA out of the valid range + //or + //Write Mode PortA is "Read First" and Write Mode PortB is "Write First" and WEA = 1 and WEB = 1 and SINITA = 0 and ADDRA out of the valid range + if (c_yydisable_warnings == 0) begin + $display("Invalid Address Warning #6: Warning in %m at time %t: Port A address %d (%b) of block memory invalid. Valid depth configured as 0 to %d",$time,addra_int,addra_int,c_depth_a-1); + end + doa_out <= {c_width_a{1'bX}}; // assign data bus to X + end + end + end + end + + always @(posedge recovery_a or posedge recovery_b) begin + if (((wr_mode_a == 2'b00) && (wr_mode_b == 2'b00)) || + ((wr_mode_a == 2'b10) && (wr_mode_b != 2'b10)) || + ((wr_mode_a == 2'b00) && (wr_mode_b == 2'b01))) begin + if ((wea_int == 1) && (web_int == 1) && (ssrb_int == 0)) begin + if (addrb_int < c_depth_b) + for (ddi = 0; ddi < c_width_a; ddi = ddi + 1) begin + for (ddj = 0; ddj < c_width_b; ddj = ddj + 1) begin + if ((addra_int * c_width_a + ddi) == (addrb_int * c_width_b + ddj)) begin + dob_out[ddj] <= 1'bX; + end + end + end + else begin + //Warning Condition: + //Write Mode PortA is "Write First" and Write Mode PortB is "Write First" and WEA = 1 and WEB = 1 and SINITB = 0 and ADDRB out of the valid range + //or + //Write Mode PortA is "No Change" and Write Mode PortB is not "No Change" and WEA = 1 and WEB = 1 and SINITB = 0 and ADDRB out of the valid range + //or + //Write Mode PortA is "Write First" and Write Mode PortB is "Read First" and WEA = 1 and WEB = 1 and SINITB = 0 and ADDRB out of the valid range + if (c_yydisable_warnings == 0) begin + $display("Invalid Address Warning #7: Warning in %m at time %t: Port B address %d (%b) of block memory invalid. Valid depth configured as 0 to %d",$time,addrb_int,addrb_int,c_depth_b-1); + end + dob_out <= {c_width_b{1'bX}}; // assign data bus to X + end + end + end + end + + // Parity Section is deleted + + initial begin + case (c_write_modea) + `c_write_first : wr_mode_a <= 2'b00; + `c_read_first : wr_mode_a <= 2'b01; + `c_no_change : wr_mode_a <= 2'b10; + default : begin + if (c_yydisable_warnings == 0) begin + $display("Error in %m at time %t: c_write_modea = %s is not WRITE_FIRST, READ_FIRST or NO_CHANGE.",$time, c_write_modea); + end + $finish; + end + endcase + end + + initial begin + case (c_write_modeb) + `c_write_first : wr_mode_b <= 2'b00; + `c_read_first : wr_mode_b <= 2'b01; + `c_no_change : wr_mode_b <= 2'b10; + default : begin + if (c_yydisable_warnings == 0) begin + $display("Error in %m at time %t: c_write_modeb = %s is not WRITE_FIRST, READ_FIRST or NO_CHANGE.",$time, c_write_modeb); + end + $finish; + end + endcase + end + +// Port A + + +// Generate ouput control signals for Port A: RFDA and RDYA + + always @ (rfda_int or rdya_int) + begin + if (c_has_rfda == 1) + RFDA = rfda_int ; + else + RFDA = 1'b0 ; + + if ((c_has_rdya == 1) && (c_has_nda == 1) && (c_has_rfda == 1) ) + RDYA = rdya_int; + else + RDYA = 1'b0 ; + end + + always @ (ena_int ) + begin + if (ena_int == 1'b1) + rfda_int <= 1'b1 ; + else + rfda_int <= 1'b0 ; + end + +// Gate nd signal with en + + assign nda_int = ena_int && nda_i ; + +// Register hanshaking signals for port A + + always @ (posedge clka_int) + begin + if (ena_int == 1'b1) + begin + if (ssra_int == 1'b1) + nda_q <= 1'b0 ; + else + nda_q <= nda_int ; + end + else + nda_q <= nda_q ; + end + +// Register data/ address / we inputs for port A + + always @ (posedge clka_int) + begin + if (ena_int == 1'b1) + begin + dia_q <= dia_i ; + addra_q <= addra_i ; + wea_q <= wea_i ; + end + end + + +// Select registered or non-registered write enable for Port A + + always @ ( wea_i or wea_q ) + begin + if (c_reg_inputsa == 1) + wea_int = wea_q ; + else + wea_int = wea_i ; + end + +// Select registered or non-registered data/address/nd inputs for Port A + + always @ ( dia_i or dia_q ) + begin + if ( c_reg_inputsa == 1) + dia_int = dia_q; + else + dia_int = dia_i; + end + + always @ ( addra_i or addra_q or nda_q or nda_int ) + begin + if ( c_reg_inputsa == 1) + begin + addra_int = addra_q ; + if ((wea_q == 1'b1) && (c_write_modea == 2)) + new_data_a = 1'b0 ; + else + new_data_a = nda_q ; + end + else + begin + addra_int = addra_i; + if ((wea_i == 1'b1) && (c_write_modea == 2)) + new_data_a = 1'b0 ; + else + new_data_a = nda_int ; + end + end + +// Register the new_data signal for Port A to track the synchronous RAM output + + always @(posedge clka_int) + begin + if (ena_int == 1'b1) + begin + if (ssra_int == 1'b1) + new_data_a_q <= 1'b0 ; + else + // Do not update RDYA if write mode is no_change and wea=1 + //if (!(c_write_modea == 2 && wea_int == 1)) begin + // rii1 : 10/20 Make dual port behavior the same as single port + new_data_a_q <= new_data_a ; + //end + end + end + +// Generate data outputs for Port A + + + /*************************************************************** + *The following always block assigns the value for the DOUTA bus + ***************************************************************/ + always @(posedge clka_int) begin + if (ena_int == 1'b1) begin + if (ssra_int == 1'b1) begin + // for ( ai = 0; ai < c_width_a; ai = ai + 1) + // doa_out[ai] <= sinita_value[ai]; + doa_out <= sinita_value; + end + else begin + //The following IF block assigns the output for a write operation + if (wea_int == 1'b1) begin + if (wr_mode_a == 2'b00) begin + if (addra_int < c_depth_a) + // for ( aj = 0; aj < c_width_a; aj = aj + 1) + // doa_out[aj] <= dia_int[aj] ; + doa_out <= dia_int ; + else begin + //Warning Condition (Error occurs on rising edge of CLKA): + //Write Mode PortA is "Write First" and ENA = 1 and SINITA = 0 and WEA = 1 and ADDRA out of the valid range + if (c_yydisable_warnings == 0) begin + $display("Invalid Address Warning #8: Warning in %m at time %t: Port A address %d (%b) of block memory invalid. Valid depth configured as 0 to %d",$time,addra_int,addra_int,c_depth_a-1); + end + doa_out <= {c_width_a{1'bX}}; // assign data bus to X + end + end + else if (wr_mode_a == 2'b01) begin + if (addra_int < c_depth_a) + // for ( ak = 0; ak < c_width_a; ak = ak + 1) + // doa_out[ak] <= mem[(addra_int*c_width_a) + ak]; + doa_out <= mem >> (addra_int*c_width_a); + else begin + //Warning Condition (Error occurs on rising edge of CLKA): + //Write Mode PortA is "Read First" and ENA = 1 and SINITA = 0 and WEA = 1 and ADDRA out of the valid range + if (c_yydisable_warnings == 0) begin + $display("Invalid Address Warning #9: Warning in %m at time %t: Port A address %d (%b) of block memory invalid. Valid depth configured as 0 to %d",$time,addra_int,addra_int,c_depth_a-1); + end + doa_out <= {c_width_a{1'bX}}; //assign data bus to X + end + end + else begin + if (addra_int < c_depth_a) + doa_out <= doa_out; + else begin + //Warning Condition (Error occurs on rising edge of CLKA): + //Write Mode PortA is "No Change" and ENA = 1 and SINITA = 0 and WEA = 1 and ADDRA out of the valid range + if (c_yydisable_warnings == 0) begin + $display("Invalid Address Warning #10: Warning in %m at time %t: Port A address %d (%b) of block memory invalid. Valid depth configured as 0 to %d",$time,addra_int,addra_int,c_depth_a-1); + end + doa_out <= {c_width_a{1'bX}}; //assign data bus to X + end + end + end + //The following ELSE block assigns the output for a read operation + else begin + if (addra_int < c_depth_a) + // for ( al = 0; al < c_width_a; al = al + 1) + // doa_out[al] <= mem[(addra_int*c_width_a) + al]; + doa_out <= mem >> (addra_int*c_width_a); + else begin + if (c_has_douta == 1)//New IF statement to remove read errors when port is write only + begin + //Warning Condition (Error occurs on rising edge of CLKA): + //ENA = 1 and SINITA = 0 and WEA = 0 and ADDRA out of the valid range + if (c_yydisable_warnings == 0) begin + $display("Invalid Address Warning #11: Warning in %m at time %t: Port A address %d (%b) of block memory invalid. Valid depth configured as 0 to %d",$time,addra_int,addra_int,c_depth_a-1); + end + doa_out <= {c_width_a{1'bX}}; //assign data bus to X + end + end + end + end + end + end + /*************************************************************************************** + *The following always block assigns the DINA bus to the memory during a write operation + ***************************************************************************************/ + always @(posedge clka_int) begin + if (ena_int == 1'b1 && wea_int == 1'b1) begin + if (addra_int < c_depth_a) + for ( am = 0; am < c_width_a; am = am + 1) + mem[(addra_int*c_width_a) + am] <= dia_int[am]; + else begin + //Warning Condition (Error occurs on rising edge of CLKA): + //ENA = 1 and WEA = 1 and ADDRA out of the valid range + if (c_yydisable_warnings == 0) begin + $display("Invalid Address Warning #12: Warning in %m at time %t: Port A address %d (%b) of block memory invalid. Valid depth configured as 0 to %d",$time,addra_int,addra_int,c_depth_a-1); + end + doa_out <= {c_width_a{1'bX}}; //assign data bus to X + end + end + end + + // output pipelines for Port A + + always @(posedge clka_int) begin + if (ena_int == 1'b1 && c_pipe_stages_a > 0) + begin + for (i = c_pipe_stages_a; i >= 1; i = i -1 ) + begin + if (ssra_int == 1'b1 && ena_int == 1'b1 ) + begin + pipelinea[i] <= sinita_value ; + sub_rdy_a[i] <= 0 ; + end + else + begin + // Do not change output when no_change and web=1 + if (!(c_write_modea == 2 && wea_int == 1)) begin + if (i==1) + pipelinea[i] <= doa_out ; + else + pipelinea[i] <= pipelinea[i-1] ; + end // if (!(c_write_modea == 2 && wea_int == 1)) + if (i==1) + sub_rdy_a[i] <= new_data_a_q ; + else + sub_rdy_a[i] <= sub_rdy_a[i-1] ; + end + end + end + end + +// Select pipeline output if c_pipe_stages_a > 0 + + always @( pipelinea[c_pipe_stages_a] or sub_rdy_a[c_pipe_stages_a] or new_data_a_q or doa_out ) begin + if (c_pipe_stages_a == 0 ) + begin + douta_out = doa_out ; + rdya_int = new_data_a_q; + end + else + begin + douta_out = pipelinea[c_pipe_stages_a]; + rdya_int = sub_rdy_a[c_pipe_stages_a]; + end + end + + + // Select Port A data outputs based on c_has_douta parameter + + always @( douta_out ) begin + if ( c_has_douta == 1) + douta_mux_out = douta_out ; + else + douta_mux_out = 0 ; + end + + + +// Port B + + + +// Generate output control signals for Port B: RFDB and RDYB + + always @ (rfdb_int or rdyb_int) + begin + if (c_has_rfdb == 1) + RFDB = rfdb_int ; + else + RFDB = 1'b0 ; + + if ((c_has_rdyb == 1) && (c_has_ndb == 1) && (c_has_rfdb == 1) ) + RDYB = rdyb_int; + else + RDYB = 1'b0 ; + end + + always @ (enb_int ) + begin + if ( enb_int == 1'b1 ) + rfdb_int = 1'b1 ; + else + rfdb_int = 1'b0 ; + end + +// Gate nd signal with en + + assign ndb_int = enb_int && ndb_i ; + +// Register hanshaking signals for port B + + always @ (posedge clkb_int) + begin + if (enb_int == 1'b1) + begin + if (ssrb_int == 1'b1) + ndb_q <= 1'b0 ; + else + ndb_q <= ndb_int ; + end + else + ndb_q <= ndb_q; + end + +// Register data / address / we inputs for port B + + always @ (posedge clkb_int) + begin + if (enb_int == 1'b1) + begin + dib_q <= dib_i ; + addrb_q <= addrb_i ; + web_q <= web_i ; + end + end + +// Select registered or non-registered write enable for port B + + always @ (web_i or web_q ) + begin + if (c_reg_inputsb == 1) + web_int = web_q ; + else + web_int = web_i ; + end + + + +// Select registered or non-registered data/address/nd inputs for Port B + + always @ ( dib_i or dib_q ) + begin + if ( c_reg_inputsb == 1) + dib_int = dib_q; + else + dib_int = dib_i; + end + + always @ ( addrb_i or addrb_q or ndb_q or ndb_int or web_q or web_i) + begin + if ( c_reg_inputsb == 1) + begin + addrb_int = addrb_q ; + if ((web_q == 1'b1) && (c_write_modeb == 2)) + new_data_b = 1'b0 ; + else + new_data_b = ndb_q ; + end + else + begin + addrb_int = addrb_i; + if ((web_i == 1'b1) && (c_write_modeb == 2)) + new_data_b = 1'b0 ; + else + new_data_b = ndb_int ; + end + end + +// Register the new_data signal for Port B to track the synchronous RAM output + + always @(posedge clkb_int) + begin + if (enb_int == 1'b1 ) + begin + if (ssrb_int == 1'b1) + new_data_b_q <= 1'b0 ; + else + // Do not update RDYB if write mode is no_change and web=1 + //if (!(c_write_modeb == 2 && web_int == 1)) begin + // rii1 : 10/20 Make dual port behavior the same as single port + new_data_b_q <= new_data_b ; + //end + end + end + + + + + +// Generate data outputs for Port B + + + /*************************************************************** + *The following always block assigns the value for the DOUTB bus + ***************************************************************/ + always @(posedge clkb_int) begin + if (enb_int == 1'b1) begin + if (ssrb_int == 1'b1) begin + // for (bi = 0; bi < c_width_b; bi = bi + 1) + // dob_out[bi] <= sinitb_value[bi]; + dob_out <= sinitb_value; + end + else begin + //The following IF block assigns the output for a write operation + if (web_int == 1'b1) begin + if (wr_mode_b == 2'b00) begin + if (addrb_int < c_depth_b) + // for (bj = 0; bj < c_width_b; bj = bj + 1) + // dob_out[bj] <= dib_int[bj]; + dob_out <= dib_int; + else begin + //Warning Condition (Error occurs on rising edge of CLKB): + //Write Mode PortB is "Write First" and ENB = 1 and SINITB = 0 and WEB = 1 and ADDRB out of the valid range + if (c_yydisable_warnings == 0) begin + $display("Invalid Address Warning #13: Warning in %m at time %t: Port B address %d (%b) of block memory invalid. Valid depth configured as 0 to %d",$time,addrb_int,addrb_int,c_depth_b-1); + end + dob_out <= {c_width_b{1'bX}}; //assign data bus to X + end + end + else if (wr_mode_b == 2'b01) begin + if (addrb_int < c_depth_b) + // for (bk = 0; bk < c_width_b; bk = bk + 1) + // dob_out[bk] <= mem[(addrb_int*c_width_b) + bk]; + dob_out <= mem >> (addrb_int*c_width_b); + else begin + //Warning Condition (Error occurs on rising edge of CLKB): + //Write Mode PortB is "Read First" and ENB = 1 and SINITB = 0 and WEB = 1 and ADDRB out of the valid range + if (c_yydisable_warnings == 0) begin + $display("Invalid Address Warning #14: Warning in %m at time %t: Port B address %d (%b) of block memory invalid. Valid depth configured as 0 to %d",$time,addrb_int,addrb_int,c_depth_b-1); + end + dob_out <= {c_width_b{1'bX}}; //assign data bus to X + end + end + else begin + if (addrb_int < c_depth_b) + dob_out <= dob_out ; + else begin + //Warning Condition (Error occurs on rising edge of CLKB): + //Write Mode PortB is "No Change" and ENB = 1 and SINITB = 0 and WEB = 1 and ADDRB out of the valid range + if (c_yydisable_warnings == 0) begin + $display("Invalid Address Warning #15: Warning in %m at time %t: Port B address %d (%b) of block memory invalid. Valid depth configured as 0 to %d",$time,addrb_int,addrb_int,c_depth_b-1); + end + dob_out <= {c_width_b{1'bX}}; //assign data bus to X + end + end + end + //The following ELSE block assigns the output for a read operation + else begin + if (addrb_int < c_depth_b) + // for (bl = 0; bl < c_width_b; bl = bl + 1) + // dob_out[bl] <= mem[(addrb_int*c_width_b) + bl]; + dob_out <= mem >> (addrb_int*c_width_b); + else begin + if (c_has_doutb == 1)//New IF statement to remove read errors when port is write only + begin + //Warning Condition (Error occurs on rising edge of CLKB): + //ENB = 1 and SINITB = 0 and WEB = 0 and ADDRB out of the valid range + if (c_yydisable_warnings == 0) begin + $display("Invalid Address Warning #16: Warning in %m at time %t: Port B address %d (%b) of block memory invalid. Valid depth configured as 0 to %d",$time,addrb_int,addrb_int,c_depth_b-1); + end + dob_out <= {c_width_b{1'bX}}; //assign data bus to X + end + end + end + end + end + end + /*************************************************************************************** + *The following always block assigns the DINA bus to the memory during a write operation + ***************************************************************************************/ + always @(posedge clkb_int) begin + if (enb_int == 1'b1 && web_int == 1'b1) begin + if (addrb_int < c_depth_b) + for (bm = 0; bm < c_width_b; bm = bm + 1) + mem[(addrb_int*c_width_b) + bm] <= dib_int[bm]; + else begin + //Warning Condition (Error occurs on rising edge of CLKB): + //ENB = 1 and WEB = 1 and ADDRB out of the valid range + if (c_yydisable_warnings == 0) begin + $display("Invalid Address Warning #17: Warning in %m at time %t: Port B address %d (%b) of block memory invalid. Valid depth configured as 0 to %d",$time,addrb_int,addrb_int,c_depth_b-1); + end + dob_out <= {c_width_b{1'bX}}; // assign data bus to X + end + end + end + + // output pipelines for Port B + + always @(posedge clkb_int) begin + if (enb_int == 1'b1 && c_pipe_stages_b > 0) + begin + for (j = c_pipe_stages_b; j >= 1; j = j -1 ) + begin + if (ssrb_int == 1'b1 && enb_int == 1'b1 ) + begin + pipelineb[j] <= sinitb_value ; + sub_rdy_b[j] <= 0 ; + end + else + begin + // Do not change output when no_change and web=1 + if (!(c_write_modeb == 2 && web_int == 1)) begin + if (j==1) + pipelineb[j] <= dob_out ; + else + pipelineb[j] <= pipelineb[j-1] ; + end + if (j==1) + sub_rdy_b[j] <= new_data_b_q ; + else + sub_rdy_b[j] <= sub_rdy_b[j-1] ; + end + end + end + end + +// Select pipeline for B if c_pipe_stages_b > 0 + + always @(pipelineb[c_pipe_stages_b] or sub_rdy_b[c_pipe_stages_b] or new_data_b_q or dob_out) begin + if ( c_pipe_stages_b == 0 ) + begin + doutb_out = dob_out ; + rdyb_int = new_data_b_q; + end + else + begin + rdyb_int = sub_rdy_b[c_pipe_stages_b]; + doutb_out = pipelineb[c_pipe_stages_b]; + end + end + + +// Select Port B data outputs based on c_has_doutb parameter + + always @( doutb_out) begin + if ( c_has_doutb == 1) + doutb_mux_out = doutb_out ; + else + doutb_mux_out = 0 ; + end + + + + + + specify + + // when both CLKA and CLKB are active on the positive edge + $recovery (posedge CLKB, posedge CLKA &&& collision_posa_posb, 1, recovery_b); + $recovery (posedge CLKA, posedge CLKB &&& collision_posa_posb, 1, recovery_a); + + // when both CLKA active on positive edge and CLKB are active on the negative edge + $recovery (negedge CLKB, posedge CLKA &&& collision_posa_negb, 1, recovery_b); + $recovery (posedge CLKA, negedge CLKB &&& collision_posa_negb, 1, recovery_a); + + // when both CLKA active on negative edge and CLKB are active on the positive edge + $recovery (posedge CLKB, negedge CLKA &&& collision_nega_posb, 1, recovery_b); + $recovery (negedge CLKA, posedge CLKB &&& collision_nega_posb, 1, recovery_a); + + // when both CLKA and CLKB are active on the negative edge + $recovery (negedge CLKB, negedge CLKA &&& collision_nega_negb, 1, recovery_b); + $recovery (negedge CLKA, negedge CLKB &&& collision_nega_negb, 1, recovery_a); + + endspecify + +endmodule + +`endcelldefine diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/BLKMEMDP_V6_1.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/BLKMEMDP_V6_1.v new file mode 100644 index 0000000..fe3f643 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/BLKMEMDP_V6_1.v @@ -0,0 +1,1315 @@ +// Copyright(C) 2004 by Xilinx, Inc. All rights reserved. +// This text/file contains proprietary, confidential +// information of Xilinx, Inc., is distributed under license +// from Xilinx, Inc., and may be used, copied and/or +// disclosed only pursuant to the terms of a valid license +// agreement with Xilinx, Inc. Xilinx hereby grants you +// a license to use this text/file solely for design, simulation, +// implementation and creation of design files limited +// to Xilinx devices or technologies. Use with non-Xilinx +// devices or technologies is expressly prohibited and +// immediately terminates your license unless covered by +// a separate agreement. +// +// Xilinx is providing this design, code, or information +// "as is" solely for use in developing programs and +// solutions for Xilinx devices. By providing this design, +// code, or information as one possible implementation of +// this feature, application or standard, Xilinx is making no +// representation that this implementation is free from any +// claims of infringement. You are responsible for +// obtaining any rights you may require for your implementation. +// Xilinx expressly disclaims any warranty whatsoever with +// respect to the adequacy of the implementation, including +// but not limited to any warranties or representations that this +// implementation is free from claims of infringement, implied +// warranties of merchantability or fitness for a particular +// purpose. +// +// Xilinx products are not intended for use in life support +// appliances, devices, or systems. Use in such applications are +// expressly prohibited. +// +// This copyright and support notice must be retained as part +// of this text at all times. (c) Copyright 1995-2004 Xilinx, Inc. +// All rights reserved. + +/************************************************************************** + * $RCSfile: BLKMEMDP_V6_1.v,v $ $Revision: 1.12 $ $Date: 2008/09/08 20:06:29 $ + ************************************************************************** + * Dual Port Block Memory - Verilog Behavioral Model + * ************************************************************************ + * + * + ************************************************************************* + * Filename: BLKMEMDP_V6_1.v + * + * Description: The Verilog behavioral model for the Dual Port Block Memory + * + * *********************************************************************** + */ + +`timescale 1ns/10ps +`celldefine + + +`define c_dp_rom 4 +`define c_dp_ram 2 +`define c_write_first 0 +`define c_read_first 1 +`define c_no_change 2 + +module BLKMEMDP_V6_1(DOUTA, DOUTB, ADDRA, CLKA, DINA, ENA, SINITA, WEA, NDA, RFDA, RDYA, ADDRB, CLKB, DINB, ENB, SINITB, WEB,NDB, RFDB, RDYB); + + + + parameter c_addra_width = 11 ; + parameter c_addrb_width = 9 ; + parameter c_default_data = "0"; // indicates string of hex characters used to initialize memory + parameter c_depth_a = 2048 ; + parameter c_depth_b = 512 ; + parameter c_enable_rlocs = 0 ; // core includes placement constraints + parameter c_has_default_data = 1; + parameter c_has_dina = 1 ; // indicate port A has data input pins + parameter c_has_dinb = 1 ; // indicate port B has data input pins + parameter c_has_douta = 1 ; // indicates port A has output + parameter c_has_doutb = 1 ; // indicates port B has output + parameter c_has_ena = 1 ; // indicates port A has a ENA pin + parameter c_has_enb = 1 ; // indicates port B has a ENB pin + parameter c_has_limit_data_pitch = 1 ; + parameter c_has_nda = 0 ; // Port A has a new data pin + parameter c_has_ndb = 0 ; // Port B has a new data pin + parameter c_has_rdya = 0 ; // Port A has result ready pin + parameter c_has_rdyb = 0 ; // Port B has result ready pin + parameter c_has_rfda = 0 ; // Port A has ready for data pin + parameter c_has_rfdb = 0 ; // Port B has ready for data pin + parameter c_has_sinita = 1 ; // indicates port A has a SINITA pin + parameter c_has_sinitb = 1 ; // indicates port B has a SINITB pin + parameter c_has_wea = 1 ; // indicates port A has a WEA pin + parameter c_has_web = 1 ; // indicates port B has a WEB pin + parameter c_limit_data_pitch = 16 ; + parameter c_mem_init_file = "null.mif"; // controls which .mif file used to initialize memory + parameter c_pipe_stages_a = 0 ; // indicates the number of pipe stages needed in port A + parameter c_pipe_stages_b = 0 ; // indicates the number of pipe stages needed in port B + parameter c_reg_inputsa = 0 ; // indicates we, addr, and din of port A are registered + parameter c_reg_inputsb = 0 ; // indicates we, addr, and din of port B are registered + parameter c_sinita_value = "0000"; // indicates string of hex used to initialize A output registers + parameter c_sinitb_value = "0000"; // indicates string of hex used to initialize B output resisters + parameter c_width_a = 8 ; + parameter c_width_b = 32 ; + parameter c_write_modea = 2; // controls which write modes shall be used + parameter c_write_modeb = 2; // controls which write modes shall be used + + // New Generics for Primitive Selection and Pin Polarity + parameter c_ybottom_addr = "1024"; + parameter c_yclka_is_rising = 1; // controls the active edge of the CLKA Pin + parameter c_yclkb_is_rising = 1; // controls the active edge of the CLKB Pin + parameter c_yena_is_high = 1; // controls the polarity of the ENA Pin + parameter c_yenb_is_high = 1; // controls the polarity of the ENB Pin + parameter c_yhierarchy = "hierarchy1"; + parameter c_ymake_bmm = 0; + parameter c_yprimitive_type = "4kx4"; // Indicates which primitive should be used to build the + // memory if c_yuse_single_primitive=1 + parameter c_ysinita_is_high = 1; // controls the polarity of the SINITA Pin + parameter c_ysinitb_is_high = 1; // controls the polarity of the SINITB Pin + parameter c_ytop_addr = "0"; + parameter c_yuse_single_primitive = 0; // controls whether the Memory is build out of a + // user selected primitive or is built from multiple + // primitives with the "optimize for area" algorithm used + parameter c_ywea_is_high = 1; // controls the polarity of the WEA Pin + parameter c_yweb_is_high = 1; // controls the polarity of the WEB Pin + + parameter c_yydisable_warnings = 1; //1=no warnings, 0=print warnings + + +// IO ports + + + + output [c_width_a-1:0] DOUTA; + + input [c_addra_width-1:0] ADDRA; + input [c_width_a-1:0] DINA; + input ENA, CLKA, WEA, SINITA, NDA; + output RFDA, RDYA; + + output [c_width_b-1:0] DOUTB; + + input [c_addrb_width-1:0] ADDRB; + input [c_width_b-1:0] DINB; + input ENB, CLKB, WEB, SINITB, NDB; + output RFDB, RDYB; + + +// internal signals + + reg [c_width_a-1:0] douta_mux_out ; // output of multiplexer -- + wire [c_width_a-1:0] DOUTA = douta_mux_out; + reg RFDA, RDYA ; + + reg [c_width_b-1:0] doutb_mux_out ; // output of multiplexer -- + wire [c_width_b-1:0] DOUTB = doutb_mux_out; + reg RFDB, RDYB; + + + reg [c_width_a-1:0] douta_out_q; // registered output of douta_out + reg [c_width_a-1:0] doa_out; // output of Port A RAM + reg [c_width_a-1:0] douta_out; // output of pipeline mux for port A + + reg [c_width_b-1:0] doutb_out_q ; // registered output for doutb_out + reg [c_width_b-1:0] dob_out; // output of Port B RAM + reg [c_width_b-1:0] doutb_out ; // output of pipeline mux for port B + + reg [c_depth_a*c_width_a-1 : 0] mem; + reg [24:0] count ; + reg [1:0] wr_mode_a, wr_mode_b; + + reg [(c_width_a-1) : 0] pipelinea [0 : c_pipe_stages_a]; + reg [(c_width_b-1) : 0] pipelineb [0 : c_pipe_stages_b]; + reg sub_rdy_a[0 : c_pipe_stages_a]; + reg sub_rdy_b[0 : c_pipe_stages_b]; + + reg [10:0] ci, cj; + reg [10:0] dmi, dmj, dni, dnj, doi, doj, dai, daj, dbi, dbj, dci, dcj, ddi, ddj; + reg [10:0] pmi, pmj, pni, pnj, poi, poj, pai, paj, pbi, pbj, pci, pcj, pdi, pdj; + integer ai, aj, ak, al, am, an, ap ; + integer bi, bj, bk, bl, bm, bn, bp ; + integer i, j, k, l, m, n, p; + + wire [c_addra_width-1:0] addra_i = ADDRA; + reg [c_width_a-1:0] dia_int ; + reg [c_width_a-1:0] dia_q ; + wire [c_width_a-1:0] dia_i ; + wire ena_int ; + reg ena_q ; + wire clka_int ; + reg wea_int ; + wire wea_i ; + reg wea_q ; + wire ssra_int ; + wire nda_int ; + wire nda_i ; + reg rfda_int ; + reg rdya_int ; + reg nda_q ; + reg new_data_a ; + reg new_data_a_q ; + reg [c_addra_width-1:0] addra_q; + reg [c_addra_width-1:0] addra_int; + reg [c_width_a-1:0] sinita_value ; // initialization value for output registers of Port A + + wire [c_addrb_width-1:0] addrb_i = ADDRB; + reg [c_width_b-1:0] dib_int ; + reg [c_width_b-1:0] dib_q ; + wire [c_width_b-1:0] dib_i ; + wire enb_int ; + reg enb_q ; + wire clkb_int ; + reg web_int ; + wire web_i ; + reg web_q ; + wire ssrb_int ; + wire ndb_int ; + wire ndb_i ; + reg rfdb_int ; + reg rdyb_int ; + reg ndb_q ; + reg new_data_b ; + reg new_data_b_q ; + reg [c_addrb_width-1:0] addrb_q ; + reg [c_addrb_width-1:0] addrb_int ; + reg [c_width_b-1:0] sinitb_value ; // initialization value for output registers of Port B + +// variables used to initialize memory contents to default values. + + reg [c_width_a-1:0] bitval ; + reg [c_width_a-1:0] ram_temp [0:c_depth_a-1] ; + reg [c_width_a-1:0] default_data ; + +// variables used to detect address collision on dual port Rams + + reg recovery_a, recovery_b; + reg address_collision; + + wire clka_enable_pp = ena_int && wea_int && enb_int && address_collision + && c_yclka_is_rising && c_yclkb_is_rising; + wire clkb_enable_pp = enb_int && web_int && ena_int && address_collision + && c_yclka_is_rising && c_yclkb_is_rising; + wire collision_posa_posb = clka_enable_pp || clkb_enable_pp; + + // For posedge clka and negedge clkb + + wire clka_enable_pn = ena_int && wea_int && enb_int && address_collision + && c_yclka_is_rising && (!c_yclkb_is_rising); + wire clkb_enable_pn = enb_int && web_int && ena_int && address_collision + && c_yclka_is_rising && (!c_yclkb_is_rising); + wire collision_posa_negb = clka_enable_pn || clkb_enable_pn; + + // For negedge clka and posedge clkb + + wire clka_enable_np = ena_int && wea_int && enb_int && address_collision + && (!c_yclka_is_rising) && c_yclkb_is_rising; + wire clkb_enable_np = enb_int && web_int && ena_int && address_collision + && (!c_yclka_is_rising) && c_yclkb_is_rising; + wire collision_nega_posb = clka_enable_np || clkb_enable_np; + + // For negedge clka and clkb + + wire clka_enable_nn = ena_int && wea_int && enb_int && address_collision + && (!c_yclka_is_rising) && (!c_yclkb_is_rising); + wire clkb_enable_nn = enb_int && web_int && ena_int && address_collision + && (!c_yclka_is_rising) && (!c_yclkb_is_rising); + wire collision_nega_negb = clka_enable_nn || clkb_enable_nn; + + +// tri0 GSR = glbl.GSR; + + assign dia_i = (c_has_dina === 1)?DINA:'b0; + assign ena_int = defval(ENA, c_has_ena, 1, c_yena_is_high); + assign ssra_int = defval(SINITA, c_has_sinita, 0, c_ysinita_is_high); + assign nda_i = defval(NDA, c_has_nda, 1, 1); + assign clka_int = defval(CLKA, 1, 1, c_yclka_is_rising); + + assign dib_i = (c_has_dinb === 1)?DINB:'b0; + assign enb_int = defval(ENB, c_has_enb, 1, c_yenb_is_high); + assign ssrb_int = defval(SINITB, c_has_sinitb, 0, c_ysinitb_is_high); + assign ndb_i = defval(NDB, c_has_ndb, 1, 1); + assign clkb_int = defval(CLKB, 1, 1, c_yclkb_is_rising); + +// RAM/ROM functionality + + assign wea_i = defval(WEA, c_has_wea, 0, c_ywea_is_high); + assign web_i = defval(WEB, c_has_web, 0, c_yweb_is_high); + + + function defval; + input i; + input hassig; + input val; + input active_high; + begin + if(hassig == 1) + begin + if (active_high == 1) + defval = i; + else + defval = ~i; + end + else + defval = val; + end + endfunction + + function max; + input a; + input b; + begin + max = (a > b) ? a : b; + end + endfunction + + function a_is_X; + input [c_width_a-1 : 0] i; + integer j ; + begin + a_is_X = 1'b0; + for(j = 0; j < c_width_a; j = j + 1) + begin + if(i[j] === 1'bx) + a_is_X = 1'b1; + end // loop + end + endfunction + + function b_is_X; + input [c_width_b-1 : 0] i; + integer j ; + begin + b_is_X = 1'b0; + for(j = 0; j < c_width_b; j = j + 1) + begin + if(i[j] === 1'bx) + b_is_X = 1'b1; + end // loop + end + endfunction + + function [c_width_a-1:0] hexstr_conv; + input [(c_width_a*8)-1:0] def_data; + + integer index,i,j; + reg [3:0] bin; + + begin + index = 0; + hexstr_conv = 'b0; + for( i=c_width_a-1; i>=0; i=i-1 ) + begin + case (def_data[7:0]) + 8'b00000000 : + begin + bin = 4'b0000; + i = -1; + end + 8'b00110000 : bin = 4'b0000; + 8'b00110001 : bin = 4'b0001; + 8'b00110010 : bin = 4'b0010; + 8'b00110011 : bin = 4'b0011; + 8'b00110100 : bin = 4'b0100; + 8'b00110101 : bin = 4'b0101; + 8'b00110110 : bin = 4'b0110; + 8'b00110111 : bin = 4'b0111; + 8'b00111000 : bin = 4'b1000; + 8'b00111001 : bin = 4'b1001; + 8'b01000001 : bin = 4'b1010; + 8'b01000010 : bin = 4'b1011; + 8'b01000011 : bin = 4'b1100; + 8'b01000100 : bin = 4'b1101; + 8'b01000101 : bin = 4'b1110; + 8'b01000110 : bin = 4'b1111; + 8'b01100001 : bin = 4'b1010; + 8'b01100010 : bin = 4'b1011; + 8'b01100011 : bin = 4'b1100; + 8'b01100100 : bin = 4'b1101; + 8'b01100101 : bin = 4'b1110; + 8'b01100110 : bin = 4'b1111; + default : + begin + if (c_yydisable_warnings == 0) begin + $display("ERROR in %m at time %t: NOT A HEX CHARACTER",$time); + end + bin = 4'bx; + end + endcase + for( j=0; j<4; j=j+1) + begin + if ((index*4)+j < c_width_a) + begin + hexstr_conv[(index*4)+j] = bin[j]; + end + end + index = index + 1; + def_data = def_data >> 8; + end + end + endfunction + + function [c_width_b-1:0] hexstr_conv_b; + input [(c_width_b*8)-1:0] def_data; + + integer index,i,j; + reg [3:0] bin; + + begin + index = 0; + hexstr_conv_b = 'b0; + for( i=c_width_b-1; i>=0; i=i-1 ) + begin + case (def_data[7:0]) + 8'b00000000 : + begin + bin = 4'b0000; + i = -1; + end + 8'b00110000 : bin = 4'b0000; + 8'b00110001 : bin = 4'b0001; + 8'b00110010 : bin = 4'b0010; + 8'b00110011 : bin = 4'b0011; + 8'b00110100 : bin = 4'b0100; + 8'b00110101 : bin = 4'b0101; + 8'b00110110 : bin = 4'b0110; + 8'b00110111 : bin = 4'b0111; + 8'b00111000 : bin = 4'b1000; + 8'b00111001 : bin = 4'b1001; + 8'b01000001 : bin = 4'b1010; + 8'b01000010 : bin = 4'b1011; + 8'b01000011 : bin = 4'b1100; + 8'b01000100 : bin = 4'b1101; + 8'b01000101 : bin = 4'b1110; + 8'b01000110 : bin = 4'b1111; + 8'b01100001 : bin = 4'b1010; + 8'b01100010 : bin = 4'b1011; + 8'b01100011 : bin = 4'b1100; + 8'b01100100 : bin = 4'b1101; + 8'b01100101 : bin = 4'b1110; + 8'b01100110 : bin = 4'b1111; + default : + begin + if (c_yydisable_warnings == 0) begin + $display("ERROR in %m at time %t: NOT A HEX CHARACTER",$time); + end + bin = 4'bx; + end + endcase + for( j=0; j<4; j=j+1) + begin + if ((index*4)+j < c_width_b) + begin + hexstr_conv_b[(index*4)+j] = bin[j]; + end + end + index = index + 1; + def_data = def_data >> 8; + end + end + endfunction + + + + + +// Initialize memory contents to 0 for now . + + initial begin + sinita_value = 'b0 ; + sinitb_value = 'b0 ; + + default_data = hexstr_conv(c_default_data); + if (c_has_sinita == 1 ) + sinita_value = hexstr_conv(c_sinita_value); + if (c_has_sinitb == 1 ) + sinitb_value = hexstr_conv_b(c_sinitb_value); + for(i = 0; i < c_depth_a; i = i + 1) + ram_temp[i] = default_data; + if (c_has_default_data == 0) + $readmemb(c_mem_init_file, ram_temp) ; + + for(i = 0; i < c_depth_a; i = i + 1) + for(j = 0; j < c_width_a; j = j + 1) + begin + bitval = (1'b1 << j); + mem[(i*c_width_a) + j] = (ram_temp[i] & bitval) >> j; + end + recovery_a = 0; + recovery_b = 0; + for (k = 0; k <= c_pipe_stages_a; k = k + 1) + pipelinea[k] = sinita_value ; + for (l = 0; l <= c_pipe_stages_b; l = l + 1) + pipelineb[l] = sinitb_value ; + for (m = 0; m <= c_pipe_stages_a; m = m + 1) + sub_rdy_a[m] = 0 ; + for (n = 0; n <= c_pipe_stages_b; n = n + 1) + sub_rdy_b[n] = 0 ; + doa_out = sinita_value ; + dob_out = sinitb_value ; + nda_q = 0; + ndb_q = 0; + new_data_a_q = 0 ; + new_data_b_q = 0 ; + dia_q = 0; + dib_q = 0; + addra_q = 0; + addrb_q = 0; + wea_q = 0; + web_q = 0; + #1 douta_out = sinita_value; + #1 doutb_out = sinitb_value; + #1 rdya_int = 0; + #1 rdyb_int = 0; + end + + + always @(addra_int or addrb_int) begin // check address collision + address_collision <= 1'b0; + for (ci = 0; ci < c_width_a; ci = ci + 1) begin // absolute address A + for (cj = 0; cj < c_width_b; cj = cj + 1) begin // absolute address B + if ((addra_int * c_width_a + ci) == (addrb_int * c_width_b + cj)) begin + address_collision <= 1'b1; + end + end + end + end +/*********************************************************************************************************** +* The following 3 always blocks handle memory inputs for the case of an address collision on ADDRA and ADDRB +***********************************************************************************************************/ + always @(posedge recovery_a or posedge recovery_b) begin + if (((wr_mode_a == 2'b01) && (wr_mode_b == 2'b01)) || + ((wr_mode_a != 2'b01) && (wr_mode_b != 2'b01))) begin + if (wea_int == 1 && web_int == 1) begin + if (addra_int < c_depth_a) + for (dmi = 0; dmi < c_width_a; dmi = dmi + 1) begin + for (dmj = 0; dmj < c_width_b; dmj = dmj + 1) begin + if ((addra_int * c_width_a + dmi) == (addrb_int * c_width_b + dmj)) begin +//Fixed read-first collision +// mem[addra_int * c_width_a + dmi] <= 1'bX; + if ((wr_mode_a == 2'b01) && (wr_mode_b == 2'b01)) + begin + doa_out[dmi] <= 1'bX; + dob_out[dmj] <= 1'bX; + end + else + mem[addra_int * c_width_a + dmi] <= 1'bX; + end + end + end + else begin + //Warning Condition: + //Write Mode PortA is "Read First" and Write Mode PortB is "Read First" and WEA = 1 and WEB = 1 and ADDRA out of the valid range + //or + //Write Mode PortA is not "Read First" and Write Mode PortB is not "Read First" and WEA = 1 and WEB = 1 and ADDRA out of the valid range + if (c_yydisable_warnings == 0) begin + $display("Invalid Address Warning #1: Warning in %m at time %t: Port A address %d (%b) of block memory invalid. Valid depth configured as 0 to %d",$time,addra_int,addra_int,c_depth_a-1); + end + doa_out <= {c_width_a{1'bX}}; // assign data bus to X + end + end + end + recovery_a <= 0; + recovery_b <= 0; + end + + always @(posedge recovery_a or posedge recovery_b) begin + if ((wr_mode_a == 2'b01) && (wr_mode_b != 2'b01)) begin + if (wea_int == 1 && web_int == 1) begin + if (addra_int < c_depth_a) + for (dni = 0; dni < c_width_a; dni = dni + 1) begin + for (dnj = 0; dnj < c_width_b; dnj = dnj + 1) begin + if ((addra_int * c_width_a + dni) == (addrb_int * c_width_b + dnj)) begin + mem[addra_int * c_width_a + dni] <= dia_int[dni]; + end + end + end + else begin + //Warning Condition: + //Write Mode PortA is "Read First" and Write Mode PortB is not "Read First" and WEA = 1 and WEB = 1 and ADDRA out of the valid range + if (c_yydisable_warnings == 0) begin + $display("Invalid Address Warning #2: Warning in %m at time %t: Port A address %d (%b) of block memory invalid. Valid depth configured as 0 to %d",$time,addra_int,addra_int,c_depth_a-1); + end + doa_out <= {c_width_a{1'bX}}; // assign data bus to X + end + end + end + end + + always @(posedge recovery_a or posedge recovery_b) begin + if ((wr_mode_a != 2'b01) && (wr_mode_b == 2'b01)) begin + if (wea_int == 1 && web_int == 1) begin + if (addrb_int < c_depth_b) + for (doi = 0; doi < c_width_a; doi = doi + 1) begin + for (doj = 0; doj < c_width_b; doj = doj + 1) begin + if ((addra_int * c_width_a + doi) == (addrb_int * c_width_b + doj)) begin + mem[addrb_int * c_width_b + doj] <= dib_int[doj]; + end + end + end + else begin + //Warning Condition: + //Write Mode PortA is not "Read First" and Write Mode PortB is "Read First" and WEA = 1 and WEB = 1 and ADDRB out of the valid range + if (c_yydisable_warnings == 0) begin + $display("Invalid Address Warning #3: Warning in %m at time %t: Port B address %d (%b) of block memory invalid. Valid depth configured as 0 to %d",$time,addrb_int,addrb_int,c_depth_b-1); + end + dob_out <= {c_width_b{1'bX}}; // assign data bus to X + end + end + end + end +/*********************************************************************************************************** +*The following 4 always blocks handle memory outputs for the case of an address collision on ADDRA and ADDRB +***********************************************************************************************************/ + always @(posedge recovery_a or posedge recovery_b) begin + if ((wr_mode_b == 2'b00) || (wr_mode_b == 2'b10)) begin + if ((wea_int == 0) && (web_int == 1) && (ssra_int == 0)) begin + if (addra_int < c_depth_a) + for (dai = 0; dai < c_width_a; dai = dai + 1) begin + for (daj = 0; daj < c_width_b; daj = daj + 1) begin + if ((addra_int * c_width_a + dai) == (addrb_int * c_width_b + daj)) begin + doa_out[dai] <= 1'bX; + end + end + end + else begin + //Warning Condition: + //Write Mode PortB is "Write First" and WEA = 0 and WEB = 1 and SINITA = 0 and ADDRA out of the valid range + //or + //Write Mode PortB is "No Change" and WEA = 0 and WEB = 1 and SINITA = 0 and ADDRA out of the valid range + if (c_yydisable_warnings == 0) begin + $display("Invalid Address Warning #4: Warning in %m at time %t: Port A address %d (%b) of block memory invalid. Valid depth configured as 0 to %d",$time,addra_int,addra_int,c_depth_a-1); + end + doa_out <= {c_width_a{1'bX}}; // assign data bus to X + end + end + end + end + + always @(posedge recovery_a or posedge recovery_b) begin + if ((wr_mode_a == 2'b00) || (wr_mode_a == 2'b10)) begin + if ((wea_int == 1) && (web_int == 0) && (ssrb_int == 0)) begin + if (addrb_int < c_depth_b) + for (dbi = 0; dbi < c_width_a; dbi = dbi + 1) begin + for (dbj = 0; dbj < c_width_b; dbj = dbj + 1) begin + if ((addra_int * c_width_a + dbi) == (addrb_int * c_width_b + dbj)) begin + dob_out[dbj] <= 1'bX; + end + end + end + else begin + //Warning Condition: + //Write Mode PortA is "Write First" and WEA = 1 and WEB = 0 and SINITB = 0 and ADDRB out of the valid range + //or + //Write Mode PortA is "No Change" and WEA = 1 and WEB = 0 and SINITB = 0 and ADDRB out of the valid range + if (c_yydisable_warnings == 0) begin + $display("Invalid Address Warning #5: Warning in %m at time %t: Port B address %d (%b) of block memory invalid. Valid depth configured as 0 to %d",$time,addrb_int,addrb_int,c_depth_b-1); + end + dob_out <= {c_width_b{1'bX}}; // assign data bus to X + end + end + end + end + + always @(posedge recovery_a or posedge recovery_b) begin + if (((wr_mode_a == 2'b00) && (wr_mode_b == 2'b00)) || + ((wr_mode_a != 2'b10) && (wr_mode_b == 2'b10)) || + ((wr_mode_a == 2'b01) && (wr_mode_b == 2'b00))) begin + if ((wea_int == 1) && (web_int == 1) && (ssra_int == 0)) begin + if (addra_int < c_depth_a) + for (dci = 0; dci < c_width_a; dci = dci + 1) begin + for (dcj = 0; dcj < c_width_b; dcj = dcj + 1) begin + if ((addra_int * c_width_a + dci) == (addrb_int * c_width_b + dcj)) begin + doa_out[dci] <= 1'bX; + end + end + end + else begin + //Warning Condition: + //Write Mode PortA is "Write First" and Write Mode PortB is "Write First" and WEA = 1 and WEB = 1 and SINITA = 0 and ADDRA out of the valid range + //or + //Write Mode PortA is not "No Change" and Write Mode PortB is "No Change" and WEA = 1 and WEB = 1 and SINITA = 0 and ADDRA out of the valid range + //or + //Write Mode PortA is "Read First" and Write Mode PortB is "Write First" and WEA = 1 and WEB = 1 and SINITA = 0 and ADDRA out of the valid range + if (c_yydisable_warnings == 0) begin + $display("Invalid Address Warning #6: Warning in %m at time %t: Port A address %d (%b) of block memory invalid. Valid depth configured as 0 to %d",$time,addra_int,addra_int,c_depth_a-1); + end + doa_out <= {c_width_a{1'bX}}; // assign data bus to X + end + end + end + end + + always @(posedge recovery_a or posedge recovery_b) begin + if (((wr_mode_a == 2'b00) && (wr_mode_b == 2'b00)) || + ((wr_mode_a == 2'b10) && (wr_mode_b != 2'b10)) || + ((wr_mode_a == 2'b00) && (wr_mode_b == 2'b01))) begin + if ((wea_int == 1) && (web_int == 1) && (ssrb_int == 0)) begin + if (addrb_int < c_depth_b) + for (ddi = 0; ddi < c_width_a; ddi = ddi + 1) begin + for (ddj = 0; ddj < c_width_b; ddj = ddj + 1) begin + if ((addra_int * c_width_a + ddi) == (addrb_int * c_width_b + ddj)) begin + dob_out[ddj] <= 1'bX; + end + end + end + else begin + //Warning Condition: + //Write Mode PortA is "Write First" and Write Mode PortB is "Write First" and WEA = 1 and WEB = 1 and SINITB = 0 and ADDRB out of the valid range + //or + //Write Mode PortA is "No Change" and Write Mode PortB is not "No Change" and WEA = 1 and WEB = 1 and SINITB = 0 and ADDRB out of the valid range + //or + //Write Mode PortA is "Write First" and Write Mode PortB is "Read First" and WEA = 1 and WEB = 1 and SINITB = 0 and ADDRB out of the valid range + if (c_yydisable_warnings == 0) begin + $display("Invalid Address Warning #7: Warning in %m at time %t: Port B address %d (%b) of block memory invalid. Valid depth configured as 0 to %d",$time,addrb_int,addrb_int,c_depth_b-1); + end + dob_out <= {c_width_b{1'bX}}; // assign data bus to X + end + end + end + end + + // Parity Section is deleted + + initial begin + case (c_write_modea) + `c_write_first : wr_mode_a <= 2'b00; + `c_read_first : wr_mode_a <= 2'b01; + `c_no_change : wr_mode_a <= 2'b10; + default : begin + if (c_yydisable_warnings == 0) begin + $display("Error in %m at time %t: c_write_modea = %s is not WRITE_FIRST, READ_FIRST or NO_CHANGE.",$time, c_write_modea); + end + $finish; + end + endcase + end + + initial begin + case (c_write_modeb) + `c_write_first : wr_mode_b <= 2'b00; + `c_read_first : wr_mode_b <= 2'b01; + `c_no_change : wr_mode_b <= 2'b10; + default : begin + if (c_yydisable_warnings == 0) begin + $display("Error in %m at time %t: c_write_modeb = %s is not WRITE_FIRST, READ_FIRST or NO_CHANGE.",$time, c_write_modeb); + end + $finish; + end + endcase + end + +// Port A + + +// Generate ouput control signals for Port A: RFDA and RDYA + + always @ (rfda_int or rdya_int) + begin + if (c_has_rfda == 1) + RFDA = rfda_int ; + else + RFDA = 1'b0 ; + + if ((c_has_rdya == 1) && (c_has_nda == 1) && (c_has_rfda == 1) ) + RDYA = rdya_int; + else + RDYA = 1'b0 ; + end + + always @ (ena_int ) + begin + if (ena_int == 1'b1) + rfda_int <= 1'b1 ; + else + rfda_int <= 1'b0 ; + end + +// Gate nd signal with en + + assign nda_int = ena_int && nda_i ; + +// Register hanshaking signals for port A + + always @ (posedge clka_int) + begin + if (ena_int == 1'b1) + begin + if (ssra_int == 1'b1) + nda_q <= 1'b0 ; + else + nda_q <= nda_int ; + end + else + nda_q <= nda_q ; + end + +// Register data/ address / we inputs for port A + + always @ (posedge clka_int) + begin + if (ena_int == 1'b1) + begin + dia_q <= dia_i ; + addra_q <= addra_i ; + wea_q <= wea_i ; + end + end + + +// Select registered or non-registered write enable for Port A + + always @ ( wea_i or wea_q ) + begin + if (c_reg_inputsa == 1) + wea_int = wea_q ; + else + wea_int = wea_i ; + end + +// Select registered or non-registered data/address/nd inputs for Port A + + always @ ( dia_i or dia_q ) + begin + if ( c_reg_inputsa == 1) + dia_int = dia_q; + else + dia_int = dia_i; + end + + always @ ( addra_i or addra_q or nda_q or nda_int ) + begin + if ( c_reg_inputsa == 1) + begin + addra_int = addra_q ; + if ((wea_q == 1'b1) && (c_write_modea == 2)) + new_data_a = 1'b0 ; + else + new_data_a = nda_q ; + end + else + begin + addra_int = addra_i; + if ((wea_i == 1'b1) && (c_write_modea == 2)) + new_data_a = 1'b0 ; + else + new_data_a = nda_int ; + end + end + +// Register the new_data signal for Port A to track the synchronous RAM output + + always @(posedge clka_int) + begin + if (ena_int == 1'b1) + begin + if (ssra_int == 1'b1) + new_data_a_q <= 1'b0 ; + else + // Do not update RDYA if write mode is no_change and wea=1 + //if (!(c_write_modea == 2 && wea_int == 1)) begin + // rii1 : 10/20 Make dual port behavior the same as single port + new_data_a_q <= new_data_a ; + //end + end + end + +// Generate data outputs for Port A + + + /*************************************************************** + *The following always block assigns the value for the DOUTA bus + ***************************************************************/ + always @(posedge clka_int) begin + if (ena_int == 1'b1) begin + if (ssra_int == 1'b1) begin + // for ( ai = 0; ai < c_width_a; ai = ai + 1) + // doa_out[ai] <= sinita_value[ai]; + doa_out <= sinita_value; + end + else begin + //The following IF block assigns the output for a write operation + if (wea_int == 1'b1) begin + if (wr_mode_a == 2'b00) begin + if (addra_int < c_depth_a) + // for ( aj = 0; aj < c_width_a; aj = aj + 1) + // doa_out[aj] <= dia_int[aj] ; + doa_out <= dia_int ; + else begin + //Warning Condition (Error occurs on rising edge of CLKA): + //Write Mode PortA is "Write First" and ENA = 1 and SINITA = 0 and WEA = 1 and ADDRA out of the valid range + if (c_yydisable_warnings == 0) begin + $display("Invalid Address Warning #8: Warning in %m at time %t: Port A address %d (%b) of block memory invalid. Valid depth configured as 0 to %d",$time,addra_int,addra_int,c_depth_a-1); + end + doa_out <= {c_width_a{1'bX}}; // assign data bus to X + end + end + else if (wr_mode_a == 2'b01) begin + if (addra_int < c_depth_a) + // for ( ak = 0; ak < c_width_a; ak = ak + 1) + // doa_out[ak] <= mem[(addra_int*c_width_a) + ak]; + doa_out <= mem >> (addra_int*c_width_a); + else begin + //Warning Condition (Error occurs on rising edge of CLKA): + //Write Mode PortA is "Read First" and ENA = 1 and SINITA = 0 and WEA = 1 and ADDRA out of the valid range + if (c_yydisable_warnings == 0) begin + $display("Invalid Address Warning #9: Warning in %m at time %t: Port A address %d (%b) of block memory invalid. Valid depth configured as 0 to %d",$time,addra_int,addra_int,c_depth_a-1); + end + doa_out <= {c_width_a{1'bX}}; //assign data bus to X + end + end + else begin + if (addra_int < c_depth_a) + doa_out <= doa_out; + else begin + //Warning Condition (Error occurs on rising edge of CLKA): + //Write Mode PortA is "No Change" and ENA = 1 and SINITA = 0 and WEA = 1 and ADDRA out of the valid range + if (c_yydisable_warnings == 0) begin + $display("Invalid Address Warning #10: Warning in %m at time %t: Port A address %d (%b) of block memory invalid. Valid depth configured as 0 to %d",$time,addra_int,addra_int,c_depth_a-1); + end + doa_out <= {c_width_a{1'bX}}; //assign data bus to X + end + end + end + //The following ELSE block assigns the output for a read operation + else begin + if (addra_int < c_depth_a) + // for ( al = 0; al < c_width_a; al = al + 1) + // doa_out[al] <= mem[(addra_int*c_width_a) + al]; + doa_out <= mem >> (addra_int*c_width_a); + else begin + if (c_has_douta == 1)//New IF statement to remove read errors when port is write only + begin + //Warning Condition (Error occurs on rising edge of CLKA): + //ENA = 1 and SINITA = 0 and WEA = 0 and ADDRA out of the valid range + if (c_yydisable_warnings == 0) begin + $display("Invalid Address Warning #11: Warning in %m at time %t: Port A address %d (%b) of block memory invalid. Valid depth configured as 0 to %d",$time,addra_int,addra_int,c_depth_a-1); + end + doa_out <= {c_width_a{1'bX}}; //assign data bus to X + end + end + end + end + end + end + /*************************************************************************************** + *The following always block assigns the DINA bus to the memory during a write operation + ***************************************************************************************/ + always @(posedge clka_int) begin + if (ena_int == 1'b1 && wea_int == 1'b1) begin + if (addra_int < c_depth_a) + for ( am = 0; am < c_width_a; am = am + 1) + mem[(addra_int*c_width_a) + am] <= dia_int[am]; + else begin + //Warning Condition (Error occurs on rising edge of CLKA): + //ENA = 1 and WEA = 1 and ADDRA out of the valid range + if (c_yydisable_warnings == 0) begin + $display("Invalid Address Warning #12: Warning in %m at time %t: Port A address %d (%b) of block memory invalid. Valid depth configured as 0 to %d",$time,addra_int,addra_int,c_depth_a-1); + end + doa_out <= {c_width_a{1'bX}}; //assign data bus to X + end + end + end + + // output pipelines for Port A + + always @(posedge clka_int) begin + if (ena_int == 1'b1 && c_pipe_stages_a > 0) + begin + for (i = c_pipe_stages_a; i >= 1; i = i -1 ) + begin + if (ssra_int == 1'b1 && ena_int == 1'b1 ) + begin + pipelinea[i] <= sinita_value ; + sub_rdy_a[i] <= 0 ; + end + else + begin + // Do not change output when no_change and web=1 +// if (!(c_write_modea == 2 && wea_int == 1)) begin + if (i==1) + pipelinea[i] <= doa_out ; + else + pipelinea[i] <= pipelinea[i-1] ; +// end // if (!(c_write_modea == 2 && wea_int == 1)) + if (i==1) + sub_rdy_a[i] <= new_data_a_q ; + else + sub_rdy_a[i] <= sub_rdy_a[i-1] ; + end + end + end + end + +// Select pipeline output if c_pipe_stages_a > 0 + + always @( pipelinea[c_pipe_stages_a] or sub_rdy_a[c_pipe_stages_a] or new_data_a_q or doa_out ) begin + if (c_pipe_stages_a == 0 ) + begin + douta_out = doa_out ; + rdya_int = new_data_a_q; + end + else + begin + douta_out = pipelinea[c_pipe_stages_a]; + rdya_int = sub_rdy_a[c_pipe_stages_a]; + end + end + + + // Select Port A data outputs based on c_has_douta parameter + + always @( douta_out ) begin + if ( c_has_douta == 1) + douta_mux_out = douta_out ; + else + douta_mux_out = 0 ; + end + + + +// Port B + + + +// Generate output control signals for Port B: RFDB and RDYB + + always @ (rfdb_int or rdyb_int) + begin + if (c_has_rfdb == 1) + RFDB = rfdb_int ; + else + RFDB = 1'b0 ; + + if ((c_has_rdyb == 1) && (c_has_ndb == 1) && (c_has_rfdb == 1) ) + RDYB = rdyb_int; + else + RDYB = 1'b0 ; + end + + always @ (enb_int ) + begin + if ( enb_int == 1'b1 ) + rfdb_int = 1'b1 ; + else + rfdb_int = 1'b0 ; + end + +// Gate nd signal with en + + assign ndb_int = enb_int && ndb_i ; + +// Register hanshaking signals for port B + + always @ (posedge clkb_int) + begin + if (enb_int == 1'b1) + begin + if (ssrb_int == 1'b1) + ndb_q <= 1'b0 ; + else + ndb_q <= ndb_int ; + end + else + ndb_q <= ndb_q; + end + +// Register data / address / we inputs for port B + + always @ (posedge clkb_int) + begin + if (enb_int == 1'b1) + begin + dib_q <= dib_i ; + addrb_q <= addrb_i ; + web_q <= web_i ; + end + end + +// Select registered or non-registered write enable for port B + + always @ (web_i or web_q ) + begin + if (c_reg_inputsb == 1) + web_int = web_q ; + else + web_int = web_i ; + end + + + +// Select registered or non-registered data/address/nd inputs for Port B + + always @ ( dib_i or dib_q ) + begin + if ( c_reg_inputsb == 1) + dib_int = dib_q; + else + dib_int = dib_i; + end + + always @ ( addrb_i or addrb_q or ndb_q or ndb_int or web_q or web_i) + begin + if ( c_reg_inputsb == 1) + begin + addrb_int = addrb_q ; + if ((web_q == 1'b1) && (c_write_modeb == 2)) + new_data_b = 1'b0 ; + else + new_data_b = ndb_q ; + end + else + begin + addrb_int = addrb_i; + if ((web_i == 1'b1) && (c_write_modeb == 2)) + new_data_b = 1'b0 ; + else + new_data_b = ndb_int ; + end + end + +// Register the new_data signal for Port B to track the synchronous RAM output + + always @(posedge clkb_int) + begin + if (enb_int == 1'b1 ) + begin + if (ssrb_int == 1'b1) + new_data_b_q <= 1'b0 ; + else + // Do not update RDYB if write mode is no_change and web=1 + //if (!(c_write_modeb == 2 && web_int == 1)) begin + // rii1 : 10/20 Make dual port behavior the same as single port + new_data_b_q <= new_data_b ; + //end + end + end + + + + + +// Generate data outputs for Port B + + + /*************************************************************** + *The following always block assigns the value for the DOUTB bus + ***************************************************************/ + always @(posedge clkb_int) begin + if (enb_int == 1'b1) begin + if (ssrb_int == 1'b1) begin + // for (bi = 0; bi < c_width_b; bi = bi + 1) + // dob_out[bi] <= sinitb_value[bi]; + dob_out <= sinitb_value; + end + else begin + //The following IF block assigns the output for a write operation + if (web_int == 1'b1) begin + if (wr_mode_b == 2'b00) begin + if (addrb_int < c_depth_b) + // for (bj = 0; bj < c_width_b; bj = bj + 1) + // dob_out[bj] <= dib_int[bj]; + dob_out <= dib_int; + else begin + //Warning Condition (Error occurs on rising edge of CLKB): + //Write Mode PortB is "Write First" and ENB = 1 and SINITB = 0 and WEB = 1 and ADDRB out of the valid range + if (c_yydisable_warnings == 0) begin + $display("Invalid Address Warning #13: Warning in %m at time %t: Port B address %d (%b) of block memory invalid. Valid depth configured as 0 to %d",$time,addrb_int,addrb_int,c_depth_b-1); + end + dob_out <= {c_width_b{1'bX}}; //assign data bus to X + end + end + else if (wr_mode_b == 2'b01) begin + if (addrb_int < c_depth_b) + // for (bk = 0; bk < c_width_b; bk = bk + 1) + // dob_out[bk] <= mem[(addrb_int*c_width_b) + bk]; + dob_out <= mem >> (addrb_int*c_width_b); + else begin + //Warning Condition (Error occurs on rising edge of CLKB): + //Write Mode PortB is "Read First" and ENB = 1 and SINITB = 0 and WEB = 1 and ADDRB out of the valid range + if (c_yydisable_warnings == 0) begin + $display("Invalid Address Warning #14: Warning in %m at time %t: Port B address %d (%b) of block memory invalid. Valid depth configured as 0 to %d",$time,addrb_int,addrb_int,c_depth_b-1); + end + dob_out <= {c_width_b{1'bX}}; //assign data bus to X + end + end + else begin + if (addrb_int < c_depth_b) + dob_out <= dob_out ; + else begin + //Warning Condition (Error occurs on rising edge of CLKB): + //Write Mode PortB is "No Change" and ENB = 1 and SINITB = 0 and WEB = 1 and ADDRB out of the valid range + if (c_yydisable_warnings == 0) begin + $display("Invalid Address Warning #15: Warning in %m at time %t: Port B address %d (%b) of block memory invalid. Valid depth configured as 0 to %d",$time,addrb_int,addrb_int,c_depth_b-1); + end + dob_out <= {c_width_b{1'bX}}; //assign data bus to X + end + end + end + //The following ELSE block assigns the output for a read operation + else begin + if (addrb_int < c_depth_b) + // for (bl = 0; bl < c_width_b; bl = bl + 1) + // dob_out[bl] <= mem[(addrb_int*c_width_b) + bl]; + dob_out <= mem >> (addrb_int*c_width_b); + else begin + if (c_has_doutb == 1)//New IF statement to remove read errors when port is write only + begin + //Warning Condition (Error occurs on rising edge of CLKB): + //ENB = 1 and SINITB = 0 and WEB = 0 and ADDRB out of the valid range + if (c_yydisable_warnings == 0) begin + $display("Invalid Address Warning #16: Warning in %m at time %t: Port B address %d (%b) of block memory invalid. Valid depth configured as 0 to %d",$time,addrb_int,addrb_int,c_depth_b-1); + end + dob_out <= {c_width_b{1'bX}}; //assign data bus to X + end + end + end + end + end + end + /*************************************************************************************** + *The following always block assigns the DINA bus to the memory during a write operation + ***************************************************************************************/ + always @(posedge clkb_int) begin + if (enb_int == 1'b1 && web_int == 1'b1) begin + if (addrb_int < c_depth_b) + for (bm = 0; bm < c_width_b; bm = bm + 1) + mem[(addrb_int*c_width_b) + bm] <= dib_int[bm]; + else begin + //Warning Condition (Error occurs on rising edge of CLKB): + //ENB = 1 and WEB = 1 and ADDRB out of the valid range + if (c_yydisable_warnings == 0) begin + $display("Invalid Address Warning #17: Warning in %m at time %t: Port B address %d (%b) of block memory invalid. Valid depth configured as 0 to %d",$time,addrb_int,addrb_int,c_depth_b-1); + end + dob_out <= {c_width_b{1'bX}}; // assign data bus to X + end + end + end + + // output pipelines for Port B + + always @(posedge clkb_int) begin + if (enb_int == 1'b1 && c_pipe_stages_b > 0) + begin + for (j = c_pipe_stages_b; j >= 1; j = j -1 ) + begin + if (ssrb_int == 1'b1 && enb_int == 1'b1 ) + begin + pipelineb[j] <= sinitb_value ; + sub_rdy_b[j] <= 0 ; + end + else + begin + // Do not change output when no_change and web=1 +// if (!(c_write_modeb == 2 && web_int == 1)) begin + if (j==1) + pipelineb[j] <= dob_out ; + else + pipelineb[j] <= pipelineb[j-1] ; +// end + if (j==1) + sub_rdy_b[j] <= new_data_b_q ; + else + sub_rdy_b[j] <= sub_rdy_b[j-1] ; + end + end + end + end + +// Select pipeline for B if c_pipe_stages_b > 0 + + always @(pipelineb[c_pipe_stages_b] or sub_rdy_b[c_pipe_stages_b] or new_data_b_q or dob_out) begin + if ( c_pipe_stages_b == 0 ) + begin + doutb_out = dob_out ; + rdyb_int = new_data_b_q; + end + else + begin + rdyb_int = sub_rdy_b[c_pipe_stages_b]; + doutb_out = pipelineb[c_pipe_stages_b]; + end + end + + +// Select Port B data outputs based on c_has_doutb parameter + + always @( doutb_out) begin + if ( c_has_doutb == 1) + doutb_mux_out = doutb_out ; + else + doutb_mux_out = 0 ; + end + + + + + + specify + + // when both CLKA and CLKB are active on the positive edge + $recovery (posedge CLKB, posedge CLKA &&& collision_posa_posb, 1, recovery_b); + $recovery (posedge CLKA, posedge CLKB &&& collision_posa_posb, 1, recovery_a); + + // when both CLKA active on positive edge and CLKB are active on the negative edge + $recovery (negedge CLKB, posedge CLKA &&& collision_posa_negb, 1, recovery_b); + $recovery (posedge CLKA, negedge CLKB &&& collision_posa_negb, 1, recovery_a); + + // when both CLKA active on negative edge and CLKB are active on the positive edge + $recovery (posedge CLKB, negedge CLKA &&& collision_nega_posb, 1, recovery_b); + $recovery (negedge CLKA, posedge CLKB &&& collision_nega_posb, 1, recovery_a); + + // when both CLKA and CLKB are active on the negative edge + $recovery (negedge CLKB, negedge CLKA &&& collision_nega_negb, 1, recovery_b); + $recovery (negedge CLKA, negedge CLKB &&& collision_nega_negb, 1, recovery_a); + + endspecify + +endmodule + +`endcelldefine diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/BLKMEMDP_V6_2.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/BLKMEMDP_V6_2.v new file mode 100644 index 0000000..b25a514 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/BLKMEMDP_V6_2.v @@ -0,0 +1,1317 @@ +// Copyright(C) 2004 by Xilinx, Inc. All rights reserved. +// This text/file contains proprietary, confidential +// information of Xilinx, Inc., is distributed under license +// from Xilinx, Inc., and may be used, copied and/or +// disclosed only pursuant to the terms of a valid license +// agreement with Xilinx, Inc. Xilinx hereby grants you +// a license to use this text/file solely for design, simulation, +// implementation and creation of design files limited +// to Xilinx devices or technologies. Use with non-Xilinx +// devices or technologies is expressly prohibited and +// immediately terminates your license unless covered by +// a separate agreement. +// +// Xilinx is providing this design, code, or information +// "as is" solely for use in developing programs and +// solutions for Xilinx devices. By providing this design, +// code, or information as one possible implementation of +// this feature, application or standard, Xilinx is making no +// representation that this implementation is free from any +// claims of infringement. You are responsible for +// obtaining any rights you may require for your implementation. +// Xilinx expressly disclaims any warranty whatsoever with +// respect to the adequacy of the implementation, including +// but not limited to any warranties or representations that this +// implementation is free from claims of infringement, implied +// warranties of merchantability or fitness for a particular +// purpose. +// +// Xilinx products are not intended for use in life support +// appliances, devices, or systems. Use in such applications are +// expressly prohibited. +// +// This copyright and support notice must be retained as part +// of this text at all times. (c) Copyright 1995-2004 Xilinx, Inc. +// All rights reserved. + +/************************************************************************** + * $RCSfile: BLKMEMDP_V6_2.v,v $ $Revision: 1.10 $ $Date: 2008/09/08 16:50:43 $ + ************************************************************************** + * Dual Port Block Memory - Verilog Behavioral Model + * ************************************************************************ + * + * + ************************************************************************* + * Filename: BLKMEMDP_V6_2.v + * + * Description: The Verilog behavioral model for the Dual Port Block Memory + * + * *********************************************************************** + */ + +`timescale 1ns/10ps +`celldefine + + +`define c_dp_rom 4 +`define c_dp_ram 2 +`define c_write_first 0 +`define c_read_first 1 +`define c_no_change 2 + +module BLKMEMDP_V6_2(DOUTA, DOUTB, ADDRA, CLKA, DINA, ENA, SINITA, WEA, NDA, RFDA, RDYA, ADDRB, CLKB, DINB, ENB, SINITB, WEB,NDB, RFDB, RDYB); + + + + parameter c_addra_width = 11 ; + parameter c_addrb_width = 9 ; + parameter c_default_data = "0"; // indicates string of hex characters used to initialize memory + parameter c_depth_a = 2048 ; + parameter c_depth_b = 512 ; + parameter c_enable_rlocs = 0 ; // core includes placement constraints + parameter c_has_default_data = 1; + parameter c_has_dina = 1 ; // indicate port A has data input pins + parameter c_has_dinb = 1 ; // indicate port B has data input pins + parameter c_has_douta = 1 ; // indicates port A has output + parameter c_has_doutb = 1 ; // indicates port B has output + parameter c_has_ena = 1 ; // indicates port A has a ENA pin + parameter c_has_enb = 1 ; // indicates port B has a ENB pin + parameter c_has_limit_data_pitch = 1 ; + parameter c_has_nda = 0 ; // Port A has a new data pin + parameter c_has_ndb = 0 ; // Port B has a new data pin + parameter c_has_rdya = 0 ; // Port A has result ready pin + parameter c_has_rdyb = 0 ; // Port B has result ready pin + parameter c_has_rfda = 0 ; // Port A has ready for data pin + parameter c_has_rfdb = 0 ; // Port B has ready for data pin + parameter c_has_sinita = 1 ; // indicates port A has a SINITA pin + parameter c_has_sinitb = 1 ; // indicates port B has a SINITB pin + parameter c_has_wea = 1 ; // indicates port A has a WEA pin + parameter c_has_web = 1 ; // indicates port B has a WEB pin + parameter c_limit_data_pitch = 16 ; + parameter c_mem_init_file = "null.mif"; // controls which .mif file used to initialize memory + parameter c_pipe_stages_a = 0 ; // indicates the number of pipe stages needed in port A + parameter c_pipe_stages_b = 0 ; // indicates the number of pipe stages needed in port B + parameter c_reg_inputsa = 0 ; // indicates we, addr, and din of port A are registered + parameter c_reg_inputsb = 0 ; // indicates we, addr, and din of port B are registered + parameter c_sim_collision_check = "NONE"; + parameter c_sinita_value = "0000"; // indicates string of hex used to initialize A output registers + parameter c_sinitb_value = "0000"; // indicates string of hex used to initialize B output resisters + parameter c_width_a = 8 ; + parameter c_width_b = 32 ; + parameter c_write_modea = 2; // controls which write modes shall be used + parameter c_write_modeb = 2; // controls which write modes shall be used + + // New Generics for Primitive Selection and Pin Polarity + parameter c_ybottom_addr = "1024"; + parameter c_yclka_is_rising = 1; // controls the active edge of the CLKA Pin + parameter c_yclkb_is_rising = 1; // controls the active edge of the CLKB Pin + parameter c_yena_is_high = 1; // controls the polarity of the ENA Pin + parameter c_yenb_is_high = 1; // controls the polarity of the ENB Pin + parameter c_yhierarchy = "hierarchy1"; + parameter c_ymake_bmm = 0; + parameter c_yprimitive_type = "4kx4"; // Indicates which primitive should be used to build the + // memory if c_yuse_single_primitive=1 + parameter c_ysinita_is_high = 1; // controls the polarity of the SINITA Pin + parameter c_ysinitb_is_high = 1; // controls the polarity of the SINITB Pin + parameter c_ytop_addr = "0"; + parameter c_yuse_single_primitive = 0; // controls whether the Memory is build out of a + // user selected primitive or is built from multiple + // primitives with the "optimize for area" algorithm used + parameter c_ywea_is_high = 1; // controls the polarity of the WEA Pin + parameter c_yweb_is_high = 1; // controls the polarity of the WEB Pin + + parameter c_yydisable_warnings = 1; //1=no warnings, 0=print warnings + + + +// IO ports + + + + output [c_width_a-1:0] DOUTA; + + input [c_addra_width-1:0] ADDRA; + input [c_width_a-1:0] DINA; + input ENA, CLKA, WEA, SINITA, NDA; + output RFDA, RDYA; + + output [c_width_b-1:0] DOUTB; + + input [c_addrb_width-1:0] ADDRB; + input [c_width_b-1:0] DINB; + input ENB, CLKB, WEB, SINITB, NDB; + output RFDB, RDYB; + + +// internal signals + + reg [c_width_a-1:0] douta_mux_out ; // output of multiplexer -- + wire [c_width_a-1:0] DOUTA = douta_mux_out; + reg RFDA, RDYA ; + + reg [c_width_b-1:0] doutb_mux_out ; // output of multiplexer -- + wire [c_width_b-1:0] DOUTB = doutb_mux_out; + reg RFDB, RDYB; + + + reg [c_width_a-1:0] douta_out_q; // registered output of douta_out + reg [c_width_a-1:0] doa_out; // output of Port A RAM + reg [c_width_a-1:0] douta_out; // output of pipeline mux for port A + + reg [c_width_b-1:0] doutb_out_q ; // registered output for doutb_out + reg [c_width_b-1:0] dob_out; // output of Port B RAM + reg [c_width_b-1:0] doutb_out ; // output of pipeline mux for port B + + reg [c_depth_a*c_width_a-1 : 0] mem; + reg [24:0] count ; + reg [1:0] wr_mode_a, wr_mode_b; + + reg [(c_width_a-1) : 0] pipelinea [0 : c_pipe_stages_a]; + reg [(c_width_b-1) : 0] pipelineb [0 : c_pipe_stages_b]; + reg sub_rdy_a[0 : c_pipe_stages_a]; + reg sub_rdy_b[0 : c_pipe_stages_b]; + + reg [10:0] ci, cj; + reg [10:0] dmi, dmj, dni, dnj, doi, doj, dai, daj, dbi, dbj, dci, dcj, ddi, ddj; + reg [10:0] pmi, pmj, pni, pnj, poi, poj, pai, paj, pbi, pbj, pci, pcj, pdi, pdj; + integer ai, aj, ak, al, am, an, ap ; + integer bi, bj, bk, bl, bm, bn, bp ; + integer i, j, k, l, m, n, p; + + wire [c_addra_width-1:0] addra_i = ADDRA; + reg [c_width_a-1:0] dia_int ; + reg [c_width_a-1:0] dia_q ; + wire [c_width_a-1:0] dia_i ; + wire ena_int ; + reg ena_q ; + wire clka_int ; + reg wea_int ; + wire wea_i ; + reg wea_q ; + wire ssra_int ; + wire nda_int ; + wire nda_i ; + reg rfda_int ; + reg rdya_int ; + reg nda_q ; + reg new_data_a ; + reg new_data_a_q ; + reg [c_addra_width-1:0] addra_q; + reg [c_addra_width-1:0] addra_int; + reg [c_width_a-1:0] sinita_value ; // initialization value for output registers of Port A + + wire [c_addrb_width-1:0] addrb_i = ADDRB; + reg [c_width_b-1:0] dib_int ; + reg [c_width_b-1:0] dib_q ; + wire [c_width_b-1:0] dib_i ; + wire enb_int ; + reg enb_q ; + wire clkb_int ; + reg web_int ; + wire web_i ; + reg web_q ; + wire ssrb_int ; + wire ndb_int ; + wire ndb_i ; + reg rfdb_int ; + reg rdyb_int ; + reg ndb_q ; + reg new_data_b ; + reg new_data_b_q ; + reg [c_addrb_width-1:0] addrb_q ; + reg [c_addrb_width-1:0] addrb_int ; + reg [c_width_b-1:0] sinitb_value ; // initialization value for output registers of Port B + +// variables used to initialize memory contents to default values. + + reg [c_width_a-1:0] bitval ; + reg [c_width_a-1:0] ram_temp [0:c_depth_a-1] ; + reg [c_width_a-1:0] default_data ; + +// variables used to detect address collision on dual port Rams + + reg recovery_a, recovery_b; + reg address_collision; + + wire clka_enable_pp = ena_int && wea_int && enb_int && address_collision + && c_yclka_is_rising && c_yclkb_is_rising; + wire clkb_enable_pp = enb_int && web_int && ena_int && address_collision + && c_yclka_is_rising && c_yclkb_is_rising; + wire collision_posa_posb = clka_enable_pp || clkb_enable_pp; + + // For posedge clka and negedge clkb + + wire clka_enable_pn = ena_int && wea_int && enb_int && address_collision + && c_yclka_is_rising && (!c_yclkb_is_rising); + wire clkb_enable_pn = enb_int && web_int && ena_int && address_collision + && c_yclka_is_rising && (!c_yclkb_is_rising); + wire collision_posa_negb = clka_enable_pn || clkb_enable_pn; + + // For negedge clka and posedge clkb + + wire clka_enable_np = ena_int && wea_int && enb_int && address_collision + && (!c_yclka_is_rising) && c_yclkb_is_rising; + wire clkb_enable_np = enb_int && web_int && ena_int && address_collision + && (!c_yclka_is_rising) && c_yclkb_is_rising; + wire collision_nega_posb = clka_enable_np || clkb_enable_np; + + // For negedge clka and clkb + + wire clka_enable_nn = ena_int && wea_int && enb_int && address_collision + && (!c_yclka_is_rising) && (!c_yclkb_is_rising); + wire clkb_enable_nn = enb_int && web_int && ena_int && address_collision + && (!c_yclka_is_rising) && (!c_yclkb_is_rising); + wire collision_nega_negb = clka_enable_nn || clkb_enable_nn; + + +// tri0 GSR = glbl.GSR; + + assign dia_i = (c_has_dina === 1)?DINA:'b0; + assign ena_int = defval(ENA, c_has_ena, 1, c_yena_is_high); + assign ssra_int = defval(SINITA, c_has_sinita, 0, c_ysinita_is_high); + assign nda_i = defval(NDA, c_has_nda, 1, 1); + assign clka_int = defval(CLKA, 1, 1, c_yclka_is_rising); + + assign dib_i = (c_has_dinb === 1)?DINB:'b0; + assign enb_int = defval(ENB, c_has_enb, 1, c_yenb_is_high); + assign ssrb_int = defval(SINITB, c_has_sinitb, 0, c_ysinitb_is_high); + assign ndb_i = defval(NDB, c_has_ndb, 1, 1); + assign clkb_int = defval(CLKB, 1, 1, c_yclkb_is_rising); + +// RAM/ROM functionality + + assign wea_i = defval(WEA, c_has_wea, 0, c_ywea_is_high); + assign web_i = defval(WEB, c_has_web, 0, c_yweb_is_high); + + + function defval; + input i; + input hassig; + input val; + input active_high; + begin + if(hassig == 1) + begin + if (active_high == 1) + defval = i; + else + defval = ~i; + end + else + defval = val; + end + endfunction + + function max; + input a; + input b; + begin + max = (a > b) ? a : b; + end + endfunction + + function a_is_X; + input [c_width_a-1 : 0] i; + integer j ; + begin + a_is_X = 1'b0; + for(j = 0; j < c_width_a; j = j + 1) + begin + if(i[j] === 1'bx) + a_is_X = 1'b1; + end // loop + end + endfunction + + function b_is_X; + input [c_width_b-1 : 0] i; + integer j ; + begin + b_is_X = 1'b0; + for(j = 0; j < c_width_b; j = j + 1) + begin + if(i[j] === 1'bx) + b_is_X = 1'b1; + end // loop + end + endfunction + + function [c_width_a-1:0] hexstr_conv; + input [(c_width_a*8)-1:0] def_data; + + integer index,i,j; + reg [3:0] bin; + + begin + index = 0; + hexstr_conv = 'b0; + for( i=c_width_a-1; i>=0; i=i-1 ) + begin + case (def_data[7:0]) + 8'b00000000 : + begin + bin = 4'b0000; + i = -1; + end + 8'b00110000 : bin = 4'b0000; + 8'b00110001 : bin = 4'b0001; + 8'b00110010 : bin = 4'b0010; + 8'b00110011 : bin = 4'b0011; + 8'b00110100 : bin = 4'b0100; + 8'b00110101 : bin = 4'b0101; + 8'b00110110 : bin = 4'b0110; + 8'b00110111 : bin = 4'b0111; + 8'b00111000 : bin = 4'b1000; + 8'b00111001 : bin = 4'b1001; + 8'b01000001 : bin = 4'b1010; + 8'b01000010 : bin = 4'b1011; + 8'b01000011 : bin = 4'b1100; + 8'b01000100 : bin = 4'b1101; + 8'b01000101 : bin = 4'b1110; + 8'b01000110 : bin = 4'b1111; + 8'b01100001 : bin = 4'b1010; + 8'b01100010 : bin = 4'b1011; + 8'b01100011 : bin = 4'b1100; + 8'b01100100 : bin = 4'b1101; + 8'b01100101 : bin = 4'b1110; + 8'b01100110 : bin = 4'b1111; + default : + begin + if (c_yydisable_warnings == 0) begin + $display("ERROR in %m at time %t: NOT A HEX CHARACTER",$time); + end + bin = 4'bx; + end + endcase + for( j=0; j<4; j=j+1) + begin + if ((index*4)+j < c_width_a) + begin + hexstr_conv[(index*4)+j] = bin[j]; + end + end + index = index + 1; + def_data = def_data >> 8; + end + end + endfunction + + function [c_width_b-1:0] hexstr_conv_b; + input [(c_width_b*8)-1:0] def_data; + + integer index,i,j; + reg [3:0] bin; + + begin + index = 0; + hexstr_conv_b = 'b0; + for( i=c_width_b-1; i>=0; i=i-1 ) + begin + case (def_data[7:0]) + 8'b00000000 : + begin + bin = 4'b0000; + i = -1; + end + 8'b00110000 : bin = 4'b0000; + 8'b00110001 : bin = 4'b0001; + 8'b00110010 : bin = 4'b0010; + 8'b00110011 : bin = 4'b0011; + 8'b00110100 : bin = 4'b0100; + 8'b00110101 : bin = 4'b0101; + 8'b00110110 : bin = 4'b0110; + 8'b00110111 : bin = 4'b0111; + 8'b00111000 : bin = 4'b1000; + 8'b00111001 : bin = 4'b1001; + 8'b01000001 : bin = 4'b1010; + 8'b01000010 : bin = 4'b1011; + 8'b01000011 : bin = 4'b1100; + 8'b01000100 : bin = 4'b1101; + 8'b01000101 : bin = 4'b1110; + 8'b01000110 : bin = 4'b1111; + 8'b01100001 : bin = 4'b1010; + 8'b01100010 : bin = 4'b1011; + 8'b01100011 : bin = 4'b1100; + 8'b01100100 : bin = 4'b1101; + 8'b01100101 : bin = 4'b1110; + 8'b01100110 : bin = 4'b1111; + default : + begin + if (c_yydisable_warnings == 0) begin + $display("ERROR in %m at time %t: NOT A HEX CHARACTER",$time); + end + bin = 4'bx; + end + endcase + for( j=0; j<4; j=j+1) + begin + if ((index*4)+j < c_width_b) + begin + hexstr_conv_b[(index*4)+j] = bin[j]; + end + end + index = index + 1; + def_data = def_data >> 8; + end + end + endfunction + + + + + +// Initialize memory contents to 0 for now . + + initial begin + sinita_value = 'b0 ; + sinitb_value = 'b0 ; + + default_data = hexstr_conv(c_default_data); + if (c_has_sinita == 1 ) + sinita_value = hexstr_conv(c_sinita_value); + if (c_has_sinitb == 1 ) + sinitb_value = hexstr_conv_b(c_sinitb_value); + for(i = 0; i < c_depth_a; i = i + 1) + ram_temp[i] = default_data; + if (c_has_default_data == 0) + $readmemb(c_mem_init_file, ram_temp) ; + + for(i = 0; i < c_depth_a; i = i + 1) + for(j = 0; j < c_width_a; j = j + 1) + begin + bitval = (1'b1 << j); + mem[(i*c_width_a) + j] = (ram_temp[i] & bitval) >> j; + end + recovery_a = 0; + recovery_b = 0; + for (k = 0; k <= c_pipe_stages_a; k = k + 1) + pipelinea[k] = sinita_value ; + for (l = 0; l <= c_pipe_stages_b; l = l + 1) + pipelineb[l] = sinitb_value ; + for (m = 0; m <= c_pipe_stages_a; m = m + 1) + sub_rdy_a[m] = 0 ; + for (n = 0; n <= c_pipe_stages_b; n = n + 1) + sub_rdy_b[n] = 0 ; + doa_out = sinita_value ; + dob_out = sinitb_value ; + nda_q = 0; + ndb_q = 0; + new_data_a_q = 0 ; + new_data_b_q = 0 ; + dia_q = 0; + dib_q = 0; + addra_q = 0; + addrb_q = 0; + wea_q = 0; + web_q = 0; + #1 douta_out = sinita_value; + #1 doutb_out = sinitb_value; + #1 rdya_int = 0; + #1 rdyb_int = 0; + end + + + always @(addra_int or addrb_int) begin // check address collision + address_collision <= 1'b0; + for (ci = 0; ci < c_width_a; ci = ci + 1) begin // absolute address A + for (cj = 0; cj < c_width_b; cj = cj + 1) begin // absolute address B + if ((addra_int * c_width_a + ci) == (addrb_int * c_width_b + cj)) begin + address_collision <= 1'b1; + end + end + end + end +/*********************************************************************************************************** +* The following 3 always blocks handle memory inputs for the case of an address collision on ADDRA and ADDRB +***********************************************************************************************************/ + always @(posedge recovery_a or posedge recovery_b) begin + if (((wr_mode_a == 2'b01) && (wr_mode_b == 2'b01)) || + ((wr_mode_a != 2'b01) && (wr_mode_b != 2'b01))) begin + if (wea_int == 1 && web_int == 1) begin + if (addra_int < c_depth_a) + for (dmi = 0; dmi < c_width_a; dmi = dmi + 1) begin + for (dmj = 0; dmj < c_width_b; dmj = dmj + 1) begin + if ((addra_int * c_width_a + dmi) == (addrb_int * c_width_b + dmj)) begin +//Fixed read-first collision +// mem[addra_int * c_width_a + dmi] <= 1'bX; + if ((wr_mode_a == 2'b01) && (wr_mode_b == 2'b01)) + begin + doa_out[dmi] <= 1'bX; + dob_out[dmj] <= 1'bX; + end + else + mem[addra_int * c_width_a + dmi] <= 1'bX; + end + end + end + else begin + //Warning Condition: + //Write Mode PortA is "Read First" and Write Mode PortB is "Read First" and WEA = 1 and WEB = 1 and ADDRA out of the valid range + //or + //Write Mode PortA is not "Read First" and Write Mode PortB is not "Read First" and WEA = 1 and WEB = 1 and ADDRA out of the valid range + if (c_yydisable_warnings == 0) begin + $display("Invalid Address Warning #1: Warning in %m at time %t: Port A address %d (%b) of block memory invalid. Valid depth configured as 0 to %d",$time,addra_int,addra_int,c_depth_a-1); + end + doa_out <= {c_width_a{1'bX}}; // assign data bus to X + end + end + end + recovery_a <= 0; + recovery_b <= 0; + end + + always @(posedge recovery_a or posedge recovery_b) begin + if ((wr_mode_a == 2'b01) && (wr_mode_b != 2'b01)) begin + if (wea_int == 1 && web_int == 1) begin + if (addra_int < c_depth_a) + for (dni = 0; dni < c_width_a; dni = dni + 1) begin + for (dnj = 0; dnj < c_width_b; dnj = dnj + 1) begin + if ((addra_int * c_width_a + dni) == (addrb_int * c_width_b + dnj)) begin + mem[addra_int * c_width_a + dni] <= dia_int[dni]; + end + end + end + else begin + //Warning Condition: + //Write Mode PortA is "Read First" and Write Mode PortB is not "Read First" and WEA = 1 and WEB = 1 and ADDRA out of the valid range + if (c_yydisable_warnings == 0) begin + $display("Invalid Address Warning #2: Warning in %m at time %t: Port A address %d (%b) of block memory invalid. Valid depth configured as 0 to %d",$time,addra_int,addra_int,c_depth_a-1); + end + doa_out <= {c_width_a{1'bX}}; // assign data bus to X + end + end + end + end + + always @(posedge recovery_a or posedge recovery_b) begin + if ((wr_mode_a != 2'b01) && (wr_mode_b == 2'b01)) begin + if (wea_int == 1 && web_int == 1) begin + if (addrb_int < c_depth_b) + for (doi = 0; doi < c_width_a; doi = doi + 1) begin + for (doj = 0; doj < c_width_b; doj = doj + 1) begin + if ((addra_int * c_width_a + doi) == (addrb_int * c_width_b + doj)) begin + mem[addrb_int * c_width_b + doj] <= dib_int[doj]; + end + end + end + else begin + //Warning Condition: + //Write Mode PortA is not "Read First" and Write Mode PortB is "Read First" and WEA = 1 and WEB = 1 and ADDRB out of the valid range + if (c_yydisable_warnings == 0) begin + $display("Invalid Address Warning #3: Warning in %m at time %t: Port B address %d (%b) of block memory invalid. Valid depth configured as 0 to %d",$time,addrb_int,addrb_int,c_depth_b-1); + end + dob_out <= {c_width_b{1'bX}}; // assign data bus to X + end + end + end + end +/*********************************************************************************************************** +*The following 4 always blocks handle memory outputs for the case of an address collision on ADDRA and ADDRB +***********************************************************************************************************/ + always @(posedge recovery_a or posedge recovery_b) begin + if ((wr_mode_b == 2'b00) || (wr_mode_b == 2'b10)) begin + if ((wea_int == 0) && (web_int == 1) && (ssra_int == 0)) begin + if (addra_int < c_depth_a) + for (dai = 0; dai < c_width_a; dai = dai + 1) begin + for (daj = 0; daj < c_width_b; daj = daj + 1) begin + if ((addra_int * c_width_a + dai) == (addrb_int * c_width_b + daj)) begin + doa_out[dai] <= 1'bX; + end + end + end + else begin + //Warning Condition: + //Write Mode PortB is "Write First" and WEA = 0 and WEB = 1 and SINITA = 0 and ADDRA out of the valid range + //or + //Write Mode PortB is "No Change" and WEA = 0 and WEB = 1 and SINITA = 0 and ADDRA out of the valid range + if (c_yydisable_warnings == 0) begin + $display("Invalid Address Warning #4: Warning in %m at time %t: Port A address %d (%b) of block memory invalid. Valid depth configured as 0 to %d",$time,addra_int,addra_int,c_depth_a-1); + end + doa_out <= {c_width_a{1'bX}}; // assign data bus to X + end + end + end + end + + always @(posedge recovery_a or posedge recovery_b) begin + if ((wr_mode_a == 2'b00) || (wr_mode_a == 2'b10)) begin + if ((wea_int == 1) && (web_int == 0) && (ssrb_int == 0)) begin + if (addrb_int < c_depth_b) + for (dbi = 0; dbi < c_width_a; dbi = dbi + 1) begin + for (dbj = 0; dbj < c_width_b; dbj = dbj + 1) begin + if ((addra_int * c_width_a + dbi) == (addrb_int * c_width_b + dbj)) begin + dob_out[dbj] <= 1'bX; + end + end + end + else begin + //Warning Condition: + //Write Mode PortA is "Write First" and WEA = 1 and WEB = 0 and SINITB = 0 and ADDRB out of the valid range + //or + //Write Mode PortA is "No Change" and WEA = 1 and WEB = 0 and SINITB = 0 and ADDRB out of the valid range + if (c_yydisable_warnings == 0) begin + $display("Invalid Address Warning #5: Warning in %m at time %t: Port B address %d (%b) of block memory invalid. Valid depth configured as 0 to %d",$time,addrb_int,addrb_int,c_depth_b-1); + end + dob_out <= {c_width_b{1'bX}}; // assign data bus to X + end + end + end + end + + always @(posedge recovery_a or posedge recovery_b) begin + if (((wr_mode_a == 2'b00) && (wr_mode_b == 2'b00)) || + ((wr_mode_a != 2'b10) && (wr_mode_b == 2'b10)) || + ((wr_mode_a == 2'b01) && (wr_mode_b == 2'b00))) begin + if ((wea_int == 1) && (web_int == 1) && (ssra_int == 0)) begin + if (addra_int < c_depth_a) + for (dci = 0; dci < c_width_a; dci = dci + 1) begin + for (dcj = 0; dcj < c_width_b; dcj = dcj + 1) begin + if ((addra_int * c_width_a + dci) == (addrb_int * c_width_b + dcj)) begin + doa_out[dci] <= 1'bX; + end + end + end + else begin + //Warning Condition: + //Write Mode PortA is "Write First" and Write Mode PortB is "Write First" and WEA = 1 and WEB = 1 and SINITA = 0 and ADDRA out of the valid range + //or + //Write Mode PortA is not "No Change" and Write Mode PortB is "No Change" and WEA = 1 and WEB = 1 and SINITA = 0 and ADDRA out of the valid range + //or + //Write Mode PortA is "Read First" and Write Mode PortB is "Write First" and WEA = 1 and WEB = 1 and SINITA = 0 and ADDRA out of the valid range + if (c_yydisable_warnings == 0) begin + $display("Invalid Address Warning #6: Warning in %m at time %t: Port A address %d (%b) of block memory invalid. Valid depth configured as 0 to %d",$time,addra_int,addra_int,c_depth_a-1); + end + doa_out <= {c_width_a{1'bX}}; // assign data bus to X + end + end + end + end + + always @(posedge recovery_a or posedge recovery_b) begin + if (((wr_mode_a == 2'b00) && (wr_mode_b == 2'b00)) || + ((wr_mode_a == 2'b10) && (wr_mode_b != 2'b10)) || + ((wr_mode_a == 2'b00) && (wr_mode_b == 2'b01))) begin + if ((wea_int == 1) && (web_int == 1) && (ssrb_int == 0)) begin + if (addrb_int < c_depth_b) + for (ddi = 0; ddi < c_width_a; ddi = ddi + 1) begin + for (ddj = 0; ddj < c_width_b; ddj = ddj + 1) begin + if ((addra_int * c_width_a + ddi) == (addrb_int * c_width_b + ddj)) begin + dob_out[ddj] <= 1'bX; + end + end + end + else begin + //Warning Condition: + //Write Mode PortA is "Write First" and Write Mode PortB is "Write First" and WEA = 1 and WEB = 1 and SINITB = 0 and ADDRB out of the valid range + //or + //Write Mode PortA is "No Change" and Write Mode PortB is not "No Change" and WEA = 1 and WEB = 1 and SINITB = 0 and ADDRB out of the valid range + //or + //Write Mode PortA is "Write First" and Write Mode PortB is "Read First" and WEA = 1 and WEB = 1 and SINITB = 0 and ADDRB out of the valid range + if (c_yydisable_warnings == 0) begin + $display("Invalid Address Warning #7: Warning in %m at time %t: Port B address %d (%b) of block memory invalid. Valid depth configured as 0 to %d",$time,addrb_int,addrb_int,c_depth_b-1); + end + dob_out <= {c_width_b{1'bX}}; // assign data bus to X + end + end + end + end + + // Parity Section is deleted + + initial begin + case (c_write_modea) + `c_write_first : wr_mode_a <= 2'b00; + `c_read_first : wr_mode_a <= 2'b01; + `c_no_change : wr_mode_a <= 2'b10; + default : begin + if (c_yydisable_warnings == 0) begin + $display("Error in %m at time %t: c_write_modea = %s is not WRITE_FIRST, READ_FIRST or NO_CHANGE.",$time, c_write_modea); + end + $finish; + end + endcase + end + + initial begin + case (c_write_modeb) + `c_write_first : wr_mode_b <= 2'b00; + `c_read_first : wr_mode_b <= 2'b01; + `c_no_change : wr_mode_b <= 2'b10; + default : begin + if (c_yydisable_warnings == 0) begin + $display("Error in %m at time %t: c_write_modeb = %s is not WRITE_FIRST, READ_FIRST or NO_CHANGE.",$time, c_write_modeb); + end + $finish; + end + endcase + end + +// Port A + + +// Generate ouput control signals for Port A: RFDA and RDYA + + always @ (rfda_int or rdya_int) + begin + if (c_has_rfda == 1) + RFDA = rfda_int ; + else + RFDA = 1'b0 ; + + if ((c_has_rdya == 1) && (c_has_nda == 1) && (c_has_rfda == 1) ) + RDYA = rdya_int; + else + RDYA = 1'b0 ; + end + + always @ (ena_int ) + begin + if (ena_int == 1'b1) + rfda_int <= 1'b1 ; + else + rfda_int <= 1'b0 ; + end + +// Gate nd signal with en + + assign nda_int = ena_int && nda_i ; + +// Register hanshaking signals for port A + + always @ (posedge clka_int) + begin + if (ena_int == 1'b1) + begin + if (ssra_int == 1'b1) + nda_q <= 1'b0 ; + else + nda_q <= nda_int ; + end + else + nda_q <= nda_q ; + end + +// Register data/ address / we inputs for port A + + always @ (posedge clka_int) + begin + if (ena_int == 1'b1) + begin + dia_q <= dia_i ; + addra_q <= addra_i ; + wea_q <= wea_i ; + end + end + + +// Select registered or non-registered write enable for Port A + + always @ ( wea_i or wea_q ) + begin + if (c_reg_inputsa == 1) + wea_int = wea_q ; + else + wea_int = wea_i ; + end + +// Select registered or non-registered data/address/nd inputs for Port A + + always @ ( dia_i or dia_q ) + begin + if ( c_reg_inputsa == 1) + dia_int = dia_q; + else + dia_int = dia_i; + end + + always @ ( addra_i or addra_q or nda_q or nda_int ) + begin + if ( c_reg_inputsa == 1) + begin + addra_int = addra_q ; + if ((wea_q == 1'b1) && (c_write_modea == 2)) + new_data_a = 1'b0 ; + else + new_data_a = nda_q ; + end + else + begin + addra_int = addra_i; + if ((wea_i == 1'b1) && (c_write_modea == 2)) + new_data_a = 1'b0 ; + else + new_data_a = nda_int ; + end + end + +// Register the new_data signal for Port A to track the synchronous RAM output + + always @(posedge clka_int) + begin + if (ena_int == 1'b1) + begin + if (ssra_int == 1'b1) + new_data_a_q <= 1'b0 ; + else + // Do not update RDYA if write mode is no_change and wea=1 + //if (!(c_write_modea == 2 && wea_int == 1)) begin + // rii1 : 10/20 Make dual port behavior the same as single port + new_data_a_q <= new_data_a ; + //end + end + end + +// Generate data outputs for Port A + + + /*************************************************************** + *The following always block assigns the value for the DOUTA bus + ***************************************************************/ + always @(posedge clka_int) begin + if (ena_int == 1'b1) begin + if (ssra_int == 1'b1) begin + // for ( ai = 0; ai < c_width_a; ai = ai + 1) + // doa_out[ai] <= sinita_value[ai]; + doa_out <= sinita_value; + end + else begin + //The following IF block assigns the output for a write operation + if (wea_int == 1'b1) begin + if (wr_mode_a == 2'b00) begin + if (addra_int < c_depth_a) + // for ( aj = 0; aj < c_width_a; aj = aj + 1) + // doa_out[aj] <= dia_int[aj] ; + doa_out <= dia_int ; + else begin + //Warning Condition (Error occurs on rising edge of CLKA): + //Write Mode PortA is "Write First" and ENA = 1 and SINITA = 0 and WEA = 1 and ADDRA out of the valid range + if (c_yydisable_warnings == 0) begin + $display("Invalid Address Warning #8: Warning in %m at time %t: Port A address %d (%b) of block memory invalid. Valid depth configured as 0 to %d",$time,addra_int,addra_int,c_depth_a-1); + end + doa_out <= {c_width_a{1'bX}}; // assign data bus to X + end + end + else if (wr_mode_a == 2'b01) begin + if (addra_int < c_depth_a) + // for ( ak = 0; ak < c_width_a; ak = ak + 1) + // doa_out[ak] <= mem[(addra_int*c_width_a) + ak]; + doa_out <= mem >> (addra_int*c_width_a); + else begin + //Warning Condition (Error occurs on rising edge of CLKA): + //Write Mode PortA is "Read First" and ENA = 1 and SINITA = 0 and WEA = 1 and ADDRA out of the valid range + if (c_yydisable_warnings == 0) begin + $display("Invalid Address Warning #9: Warning in %m at time %t: Port A address %d (%b) of block memory invalid. Valid depth configured as 0 to %d",$time,addra_int,addra_int,c_depth_a-1); + end + doa_out <= {c_width_a{1'bX}}; //assign data bus to X + end + end + else begin + if (addra_int < c_depth_a) + doa_out <= doa_out; + else begin + //Warning Condition (Error occurs on rising edge of CLKA): + //Write Mode PortA is "No Change" and ENA = 1 and SINITA = 0 and WEA = 1 and ADDRA out of the valid range + if (c_yydisable_warnings == 0) begin + $display("Invalid Address Warning #10: Warning in %m at time %t: Port A address %d (%b) of block memory invalid. Valid depth configured as 0 to %d",$time,addra_int,addra_int,c_depth_a-1); + end + doa_out <= {c_width_a{1'bX}}; //assign data bus to X + end + end + end + //The following ELSE block assigns the output for a read operation + else begin + if (addra_int < c_depth_a) + // for ( al = 0; al < c_width_a; al = al + 1) + // doa_out[al] <= mem[(addra_int*c_width_a) + al]; + doa_out <= mem >> (addra_int*c_width_a); + else begin + if (c_has_douta == 1)//New IF statement to remove read errors when port is write only + begin + //Warning Condition (Error occurs on rising edge of CLKA): + //ENA = 1 and SINITA = 0 and WEA = 0 and ADDRA out of the valid range + if (c_yydisable_warnings == 0) begin + $display("Invalid Address Warning #11: Warning in %m at time %t: Port A address %d (%b) of block memory invalid. Valid depth configured as 0 to %d",$time,addra_int,addra_int,c_depth_a-1); + end + doa_out <= {c_width_a{1'bX}}; //assign data bus to X + end + end + end + end + end + end + /*************************************************************************************** + *The following always block assigns the DINA bus to the memory during a write operation + ***************************************************************************************/ + always @(posedge clka_int) begin + if (ena_int == 1'b1 && wea_int == 1'b1) begin + if (addra_int < c_depth_a) + for ( am = 0; am < c_width_a; am = am + 1) + mem[(addra_int*c_width_a) + am] <= dia_int[am]; + else begin + //Warning Condition (Error occurs on rising edge of CLKA): + //ENA = 1 and WEA = 1 and ADDRA out of the valid range + if (c_yydisable_warnings == 0) begin + $display("Invalid Address Warning #12: Warning in %m at time %t: Port A address %d (%b) of block memory invalid. Valid depth configured as 0 to %d",$time,addra_int,addra_int,c_depth_a-1); + end + doa_out <= {c_width_a{1'bX}}; //assign data bus to X + end + end + end + + // output pipelines for Port A + + always @(posedge clka_int) begin + if (ena_int == 1'b1 && c_pipe_stages_a > 0) + begin + for (i = c_pipe_stages_a; i >= 1; i = i -1 ) + begin + if (ssra_int == 1'b1 && ena_int == 1'b1 ) + begin + pipelinea[i] <= sinita_value ; + sub_rdy_a[i] <= 0 ; + end + else + begin + // Do not change output when no_change and web=1 +// if (!(c_write_modea == 2 && wea_int == 1)) begin + if (i==1) + pipelinea[i] <= doa_out ; + else + pipelinea[i] <= pipelinea[i-1] ; +// end // if (!(c_write_modea == 2 && wea_int == 1)) + if (i==1) + sub_rdy_a[i] <= new_data_a_q ; + else + sub_rdy_a[i] <= sub_rdy_a[i-1] ; + end + end + end + end + +// Select pipeline output if c_pipe_stages_a > 0 + + always @( pipelinea[c_pipe_stages_a] or sub_rdy_a[c_pipe_stages_a] or new_data_a_q or doa_out ) begin + if (c_pipe_stages_a == 0 ) + begin + douta_out = doa_out ; + rdya_int = new_data_a_q; + end + else + begin + douta_out = pipelinea[c_pipe_stages_a]; + rdya_int = sub_rdy_a[c_pipe_stages_a]; + end + end + + + // Select Port A data outputs based on c_has_douta parameter + + always @( douta_out ) begin + if ( c_has_douta == 1) + douta_mux_out = douta_out ; + else + douta_mux_out = 0 ; + end + + + +// Port B + + + +// Generate output control signals for Port B: RFDB and RDYB + + always @ (rfdb_int or rdyb_int) + begin + if (c_has_rfdb == 1) + RFDB = rfdb_int ; + else + RFDB = 1'b0 ; + + if ((c_has_rdyb == 1) && (c_has_ndb == 1) && (c_has_rfdb == 1) ) + RDYB = rdyb_int; + else + RDYB = 1'b0 ; + end + + always @ (enb_int ) + begin + if ( enb_int == 1'b1 ) + rfdb_int = 1'b1 ; + else + rfdb_int = 1'b0 ; + end + +// Gate nd signal with en + + assign ndb_int = enb_int && ndb_i ; + +// Register hanshaking signals for port B + + always @ (posedge clkb_int) + begin + if (enb_int == 1'b1) + begin + if (ssrb_int == 1'b1) + ndb_q <= 1'b0 ; + else + ndb_q <= ndb_int ; + end + else + ndb_q <= ndb_q; + end + +// Register data / address / we inputs for port B + + always @ (posedge clkb_int) + begin + if (enb_int == 1'b1) + begin + dib_q <= dib_i ; + addrb_q <= addrb_i ; + web_q <= web_i ; + end + end + +// Select registered or non-registered write enable for port B + + always @ (web_i or web_q ) + begin + if (c_reg_inputsb == 1) + web_int = web_q ; + else + web_int = web_i ; + end + + + +// Select registered or non-registered data/address/nd inputs for Port B + + always @ ( dib_i or dib_q ) + begin + if ( c_reg_inputsb == 1) + dib_int = dib_q; + else + dib_int = dib_i; + end + + always @ ( addrb_i or addrb_q or ndb_q or ndb_int or web_q or web_i) + begin + if ( c_reg_inputsb == 1) + begin + addrb_int = addrb_q ; + if ((web_q == 1'b1) && (c_write_modeb == 2)) + new_data_b = 1'b0 ; + else + new_data_b = ndb_q ; + end + else + begin + addrb_int = addrb_i; + if ((web_i == 1'b1) && (c_write_modeb == 2)) + new_data_b = 1'b0 ; + else + new_data_b = ndb_int ; + end + end + +// Register the new_data signal for Port B to track the synchronous RAM output + + always @(posedge clkb_int) + begin + if (enb_int == 1'b1 ) + begin + if (ssrb_int == 1'b1) + new_data_b_q <= 1'b0 ; + else + // Do not update RDYB if write mode is no_change and web=1 + //if (!(c_write_modeb == 2 && web_int == 1)) begin + // rii1 : 10/20 Make dual port behavior the same as single port + new_data_b_q <= new_data_b ; + //end + end + end + + + + + +// Generate data outputs for Port B + + + /*************************************************************** + *The following always block assigns the value for the DOUTB bus + ***************************************************************/ + always @(posedge clkb_int) begin + if (enb_int == 1'b1) begin + if (ssrb_int == 1'b1) begin + // for (bi = 0; bi < c_width_b; bi = bi + 1) + // dob_out[bi] <= sinitb_value[bi]; + dob_out <= sinitb_value; + end + else begin + //The following IF block assigns the output for a write operation + if (web_int == 1'b1) begin + if (wr_mode_b == 2'b00) begin + if (addrb_int < c_depth_b) + // for (bj = 0; bj < c_width_b; bj = bj + 1) + // dob_out[bj] <= dib_int[bj]; + dob_out <= dib_int; + else begin + //Warning Condition (Error occurs on rising edge of CLKB): + //Write Mode PortB is "Write First" and ENB = 1 and SINITB = 0 and WEB = 1 and ADDRB out of the valid range + if (c_yydisable_warnings == 0) begin + $display("Invalid Address Warning #13: Warning in %m at time %t: Port B address %d (%b) of block memory invalid. Valid depth configured as 0 to %d",$time,addrb_int,addrb_int,c_depth_b-1); + end + dob_out <= {c_width_b{1'bX}}; //assign data bus to X + end + end + else if (wr_mode_b == 2'b01) begin + if (addrb_int < c_depth_b) + // for (bk = 0; bk < c_width_b; bk = bk + 1) + // dob_out[bk] <= mem[(addrb_int*c_width_b) + bk]; + dob_out <= mem >> (addrb_int*c_width_b); + else begin + //Warning Condition (Error occurs on rising edge of CLKB): + //Write Mode PortB is "Read First" and ENB = 1 and SINITB = 0 and WEB = 1 and ADDRB out of the valid range + if (c_yydisable_warnings == 0) begin + $display("Invalid Address Warning #14: Warning in %m at time %t: Port B address %d (%b) of block memory invalid. Valid depth configured as 0 to %d",$time,addrb_int,addrb_int,c_depth_b-1); + end + dob_out <= {c_width_b{1'bX}}; //assign data bus to X + end + end + else begin + if (addrb_int < c_depth_b) + dob_out <= dob_out ; + else begin + //Warning Condition (Error occurs on rising edge of CLKB): + //Write Mode PortB is "No Change" and ENB = 1 and SINITB = 0 and WEB = 1 and ADDRB out of the valid range + if (c_yydisable_warnings == 0) begin + $display("Invalid Address Warning #15: Warning in %m at time %t: Port B address %d (%b) of block memory invalid. Valid depth configured as 0 to %d",$time,addrb_int,addrb_int,c_depth_b-1); + end + dob_out <= {c_width_b{1'bX}}; //assign data bus to X + end + end + end + //The following ELSE block assigns the output for a read operation + else begin + if (addrb_int < c_depth_b) + // for (bl = 0; bl < c_width_b; bl = bl + 1) + // dob_out[bl] <= mem[(addrb_int*c_width_b) + bl]; + dob_out <= mem >> (addrb_int*c_width_b); + else begin + if (c_has_doutb == 1)//New IF statement to remove read errors when port is write only + begin + //Warning Condition (Error occurs on rising edge of CLKB): + //ENB = 1 and SINITB = 0 and WEB = 0 and ADDRB out of the valid range + if (c_yydisable_warnings == 0) begin + $display("Invalid Address Warning #16: Warning in %m at time %t: Port B address %d (%b) of block memory invalid. Valid depth configured as 0 to %d",$time,addrb_int,addrb_int,c_depth_b-1); + end + dob_out <= {c_width_b{1'bX}}; //assign data bus to X + end + end + end + end + end + end + /*************************************************************************************** + *The following always block assigns the DINA bus to the memory during a write operation + ***************************************************************************************/ + always @(posedge clkb_int) begin + if (enb_int == 1'b1 && web_int == 1'b1) begin + if (addrb_int < c_depth_b) + for (bm = 0; bm < c_width_b; bm = bm + 1) + mem[(addrb_int*c_width_b) + bm] <= dib_int[bm]; + else begin + //Warning Condition (Error occurs on rising edge of CLKB): + //ENB = 1 and WEB = 1 and ADDRB out of the valid range + if (c_yydisable_warnings == 0) begin + $display("Invalid Address Warning #17: Warning in %m at time %t: Port B address %d (%b) of block memory invalid. Valid depth configured as 0 to %d",$time,addrb_int,addrb_int,c_depth_b-1); + end + dob_out <= {c_width_b{1'bX}}; // assign data bus to X + end + end + end + + // output pipelines for Port B + + always @(posedge clkb_int) begin + if (enb_int == 1'b1 && c_pipe_stages_b > 0) + begin + for (j = c_pipe_stages_b; j >= 1; j = j -1 ) + begin + if (ssrb_int == 1'b1 && enb_int == 1'b1 ) + begin + pipelineb[j] <= sinitb_value ; + sub_rdy_b[j] <= 0 ; + end + else + begin + // Do not change output when no_change and web=1 +// if (!(c_write_modeb == 2 && web_int == 1)) begin + if (j==1) + pipelineb[j] <= dob_out ; + else + pipelineb[j] <= pipelineb[j-1] ; +// end + if (j==1) + sub_rdy_b[j] <= new_data_b_q ; + else + sub_rdy_b[j] <= sub_rdy_b[j-1] ; + end + end + end + end + +// Select pipeline for B if c_pipe_stages_b > 0 + + always @(pipelineb[c_pipe_stages_b] or sub_rdy_b[c_pipe_stages_b] or new_data_b_q or dob_out) begin + if ( c_pipe_stages_b == 0 ) + begin + doutb_out = dob_out ; + rdyb_int = new_data_b_q; + end + else + begin + rdyb_int = sub_rdy_b[c_pipe_stages_b]; + doutb_out = pipelineb[c_pipe_stages_b]; + end + end + + +// Select Port B data outputs based on c_has_doutb parameter + + always @( doutb_out) begin + if ( c_has_doutb == 1) + doutb_mux_out = doutb_out ; + else + doutb_mux_out = 0 ; + end + + + + + + specify + + // when both CLKA and CLKB are active on the positive edge + $recovery (posedge CLKB, posedge CLKA &&& collision_posa_posb, 1, recovery_b); + $recovery (posedge CLKA, posedge CLKB &&& collision_posa_posb, 1, recovery_a); + + // when both CLKA active on positive edge and CLKB are active on the negative edge + $recovery (negedge CLKB, posedge CLKA &&& collision_posa_negb, 1, recovery_b); + $recovery (posedge CLKA, negedge CLKB &&& collision_posa_negb, 1, recovery_a); + + // when both CLKA active on negative edge and CLKB are active on the positive edge + $recovery (posedge CLKB, negedge CLKA &&& collision_nega_posb, 1, recovery_b); + $recovery (negedge CLKA, posedge CLKB &&& collision_nega_posb, 1, recovery_a); + + // when both CLKA and CLKB are active on the negative edge + $recovery (negedge CLKB, negedge CLKA &&& collision_nega_negb, 1, recovery_b); + $recovery (negedge CLKA, negedge CLKB &&& collision_nega_negb, 1, recovery_a); + + endspecify + +endmodule + +`endcelldefine diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/BLKMEMDP_V6_3.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/BLKMEMDP_V6_3.v new file mode 100644 index 0000000..45fa79f --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/BLKMEMDP_V6_3.v @@ -0,0 +1,1317 @@ +// Copyright(C) 2004 by Xilinx, Inc. All rights reserved. +// This text/file contains proprietary, confidential +// information of Xilinx, Inc., is distributed under license +// from Xilinx, Inc., and may be used, copied and/or +// disclosed only pursuant to the terms of a valid license +// agreement with Xilinx, Inc. Xilinx hereby grants you +// a license to use this text/file solely for design, simulation, +// implementation and creation of design files limited +// to Xilinx devices or technologies. Use with non-Xilinx +// devices or technologies is expressly prohibited and +// immediately terminates your license unless covered by +// a separate agreement. +// +// Xilinx is providing this design, code, or information +// "as is" solely for use in developing programs and +// solutions for Xilinx devices. By providing this design, +// code, or information as one possible implementation of +// this feature, application or standard, Xilinx is making no +// representation that this implementation is free from any +// claims of infringement. You are responsible for +// obtaining any rights you may require for your implementation. +// Xilinx expressly disclaims any warranty whatsoever with +// respect to the adequacy of the implementation, including +// but not limited to any warranties or representations that this +// implementation is free from claims of infringement, implied +// warranties of merchantability or fitness for a particular +// purpose. +// +// Xilinx products are not intended for use in life support +// appliances, devices, or systems. Use in such applications are +// expressly prohibited. +// +// This copyright and support notice must be retained as part +// of this text at all times. (c) Copyright 1995-2004 Xilinx, Inc. +// All rights reserved. + +/************************************************************************** + * $RCSfile: BLKMEMDP_V6_3.v,v $ $Revision: 1.8 $ $Date: 2008/09/08 16:50:46 $ + ************************************************************************** + * Dual Port Block Memory - Verilog Behavioral Model + * ************************************************************************ + * + * + ************************************************************************* + * Filename: BLKMEMDP_V6_3.v + * + * Description: The Verilog behavioral model for the Dual Port Block Memory + * + * *********************************************************************** + */ + +`timescale 1ns/10ps +`celldefine + + +`define c_dp_rom 4 +`define c_dp_ram 2 +`define c_write_first 0 +`define c_read_first 1 +`define c_no_change 2 + +module BLKMEMDP_V6_3(DOUTA, DOUTB, ADDRA, CLKA, DINA, ENA, SINITA, WEA, NDA, RFDA, RDYA, ADDRB, CLKB, DINB, ENB, SINITB, WEB,NDB, RFDB, RDYB); + + + + parameter c_addra_width = 11 ; + parameter c_addrb_width = 9 ; + parameter c_default_data = "0"; // indicates string of hex characters used to initialize memory + parameter c_depth_a = 2048 ; + parameter c_depth_b = 512 ; + parameter c_enable_rlocs = 0 ; // core includes placement constraints + parameter c_has_default_data = 1; + parameter c_has_dina = 1 ; // indicate port A has data input pins + parameter c_has_dinb = 1 ; // indicate port B has data input pins + parameter c_has_douta = 1 ; // indicates port A has output + parameter c_has_doutb = 1 ; // indicates port B has output + parameter c_has_ena = 1 ; // indicates port A has a ENA pin + parameter c_has_enb = 1 ; // indicates port B has a ENB pin + parameter c_has_limit_data_pitch = 1 ; + parameter c_has_nda = 0 ; // Port A has a new data pin + parameter c_has_ndb = 0 ; // Port B has a new data pin + parameter c_has_rdya = 0 ; // Port A has result ready pin + parameter c_has_rdyb = 0 ; // Port B has result ready pin + parameter c_has_rfda = 0 ; // Port A has ready for data pin + parameter c_has_rfdb = 0 ; // Port B has ready for data pin + parameter c_has_sinita = 1 ; // indicates port A has a SINITA pin + parameter c_has_sinitb = 1 ; // indicates port B has a SINITB pin + parameter c_has_wea = 1 ; // indicates port A has a WEA pin + parameter c_has_web = 1 ; // indicates port B has a WEB pin + parameter c_limit_data_pitch = 16 ; + parameter c_mem_init_file = "null.mif"; // controls which .mif file used to initialize memory + parameter c_pipe_stages_a = 0 ; // indicates the number of pipe stages needed in port A + parameter c_pipe_stages_b = 0 ; // indicates the number of pipe stages needed in port B + parameter c_reg_inputsa = 0 ; // indicates we, addr, and din of port A are registered + parameter c_reg_inputsb = 0 ; // indicates we, addr, and din of port B are registered + parameter c_sim_collision_check = "NONE"; + parameter c_sinita_value = "0000"; // indicates string of hex used to initialize A output registers + parameter c_sinitb_value = "0000"; // indicates string of hex used to initialize B output resisters + parameter c_width_a = 8 ; + parameter c_width_b = 32 ; + parameter c_write_modea = 2; // controls which write modes shall be used + parameter c_write_modeb = 2; // controls which write modes shall be used + + // New Generics for Primitive Selection and Pin Polarity + parameter c_ybottom_addr = "1024"; + parameter c_yclka_is_rising = 1; // controls the active edge of the CLKA Pin + parameter c_yclkb_is_rising = 1; // controls the active edge of the CLKB Pin + parameter c_yena_is_high = 1; // controls the polarity of the ENA Pin + parameter c_yenb_is_high = 1; // controls the polarity of the ENB Pin + parameter c_yhierarchy = "hierarchy1"; + parameter c_ymake_bmm = 0; + parameter c_yprimitive_type = "4kx4"; // Indicates which primitive should be used to build the + // memory if c_yuse_single_primitive=1 + parameter c_ysinita_is_high = 1; // controls the polarity of the SINITA Pin + parameter c_ysinitb_is_high = 1; // controls the polarity of the SINITB Pin + parameter c_ytop_addr = "0"; + parameter c_yuse_single_primitive = 0; // controls whether the Memory is build out of a + // user selected primitive or is built from multiple + // primitives with the "optimize for area" algorithm used + parameter c_ywea_is_high = 1; // controls the polarity of the WEA Pin + parameter c_yweb_is_high = 1; // controls the polarity of the WEB Pin + + parameter c_yydisable_warnings = 1; //1=no warnings, 0=print warnings + + + +// IO ports + + + + output [c_width_a-1:0] DOUTA; + + input [c_addra_width-1:0] ADDRA; + input [c_width_a-1:0] DINA; + input ENA, CLKA, WEA, SINITA, NDA; + output RFDA, RDYA; + + output [c_width_b-1:0] DOUTB; + + input [c_addrb_width-1:0] ADDRB; + input [c_width_b-1:0] DINB; + input ENB, CLKB, WEB, SINITB, NDB; + output RFDB, RDYB; + + +// internal signals + + reg [c_width_a-1:0] douta_mux_out ; // output of multiplexer -- + wire [c_width_a-1:0] DOUTA = douta_mux_out; + reg RFDA, RDYA ; + + reg [c_width_b-1:0] doutb_mux_out ; // output of multiplexer -- + wire [c_width_b-1:0] DOUTB = doutb_mux_out; + reg RFDB, RDYB; + + + reg [c_width_a-1:0] douta_out_q; // registered output of douta_out + reg [c_width_a-1:0] doa_out; // output of Port A RAM + reg [c_width_a-1:0] douta_out; // output of pipeline mux for port A + + reg [c_width_b-1:0] doutb_out_q ; // registered output for doutb_out + reg [c_width_b-1:0] dob_out; // output of Port B RAM + reg [c_width_b-1:0] doutb_out ; // output of pipeline mux for port B + + reg [c_depth_a*c_width_a-1 : 0] mem; + reg [24:0] count ; + reg [1:0] wr_mode_a, wr_mode_b; + + reg [(c_width_a-1) : 0] pipelinea [0 : c_pipe_stages_a]; + reg [(c_width_b-1) : 0] pipelineb [0 : c_pipe_stages_b]; + reg sub_rdy_a[0 : c_pipe_stages_a]; + reg sub_rdy_b[0 : c_pipe_stages_b]; + + reg [10:0] ci, cj; + reg [10:0] dmi, dmj, dni, dnj, doi, doj, dai, daj, dbi, dbj, dci, dcj, ddi, ddj; + reg [10:0] pmi, pmj, pni, pnj, poi, poj, pai, paj, pbi, pbj, pci, pcj, pdi, pdj; + integer ai, aj, ak, al, am, an, ap ; + integer bi, bj, bk, bl, bm, bn, bp ; + integer i, j, k, l, m, n, p; + + wire [c_addra_width-1:0] addra_i = ADDRA; + reg [c_width_a-1:0] dia_int ; + reg [c_width_a-1:0] dia_q ; + wire [c_width_a-1:0] dia_i ; + wire ena_int ; + reg ena_q ; + wire clka_int ; + reg wea_int ; + wire wea_i ; + reg wea_q ; + wire ssra_int ; + wire nda_int ; + wire nda_i ; + reg rfda_int ; + reg rdya_int ; + reg nda_q ; + reg new_data_a ; + reg new_data_a_q ; + reg [c_addra_width-1:0] addra_q; + reg [c_addra_width-1:0] addra_int; + reg [c_width_a-1:0] sinita_value ; // initialization value for output registers of Port A + + wire [c_addrb_width-1:0] addrb_i = ADDRB; + reg [c_width_b-1:0] dib_int ; + reg [c_width_b-1:0] dib_q ; + wire [c_width_b-1:0] dib_i ; + wire enb_int ; + reg enb_q ; + wire clkb_int ; + reg web_int ; + wire web_i ; + reg web_q ; + wire ssrb_int ; + wire ndb_int ; + wire ndb_i ; + reg rfdb_int ; + reg rdyb_int ; + reg ndb_q ; + reg new_data_b ; + reg new_data_b_q ; + reg [c_addrb_width-1:0] addrb_q ; + reg [c_addrb_width-1:0] addrb_int ; + reg [c_width_b-1:0] sinitb_value ; // initialization value for output registers of Port B + +// variables used to initialize memory contents to default values. + + reg [c_width_a-1:0] bitval ; + reg [c_width_a-1:0] ram_temp [0:c_depth_a-1] ; + reg [c_width_a-1:0] default_data ; + +// variables used to detect address collision on dual port Rams + + reg recovery_a, recovery_b; + reg address_collision; + + wire clka_enable_pp = ena_int && wea_int && enb_int && address_collision + && c_yclka_is_rising && c_yclkb_is_rising; + wire clkb_enable_pp = enb_int && web_int && ena_int && address_collision + && c_yclka_is_rising && c_yclkb_is_rising; + wire collision_posa_posb = clka_enable_pp || clkb_enable_pp; + + // For posedge clka and negedge clkb + + wire clka_enable_pn = ena_int && wea_int && enb_int && address_collision + && c_yclka_is_rising && (!c_yclkb_is_rising); + wire clkb_enable_pn = enb_int && web_int && ena_int && address_collision + && c_yclka_is_rising && (!c_yclkb_is_rising); + wire collision_posa_negb = clka_enable_pn || clkb_enable_pn; + + // For negedge clka and posedge clkb + + wire clka_enable_np = ena_int && wea_int && enb_int && address_collision + && (!c_yclka_is_rising) && c_yclkb_is_rising; + wire clkb_enable_np = enb_int && web_int && ena_int && address_collision + && (!c_yclka_is_rising) && c_yclkb_is_rising; + wire collision_nega_posb = clka_enable_np || clkb_enable_np; + + // For negedge clka and clkb + + wire clka_enable_nn = ena_int && wea_int && enb_int && address_collision + && (!c_yclka_is_rising) && (!c_yclkb_is_rising); + wire clkb_enable_nn = enb_int && web_int && ena_int && address_collision + && (!c_yclka_is_rising) && (!c_yclkb_is_rising); + wire collision_nega_negb = clka_enable_nn || clkb_enable_nn; + + +// tri0 GSR = glbl.GSR; + + assign dia_i = (c_has_dina === 1)?DINA:'b0; + assign ena_int = defval(ENA, c_has_ena, 1, c_yena_is_high); + assign ssra_int = defval(SINITA, c_has_sinita, 0, c_ysinita_is_high); + assign nda_i = defval(NDA, c_has_nda, 1, 1); + assign clka_int = defval(CLKA, 1, 1, c_yclka_is_rising); + + assign dib_i = (c_has_dinb === 1)?DINB:'b0; + assign enb_int = defval(ENB, c_has_enb, 1, c_yenb_is_high); + assign ssrb_int = defval(SINITB, c_has_sinitb, 0, c_ysinitb_is_high); + assign ndb_i = defval(NDB, c_has_ndb, 1, 1); + assign clkb_int = defval(CLKB, 1, 1, c_yclkb_is_rising); + +// RAM/ROM functionality + + assign wea_i = defval(WEA, c_has_wea, 0, c_ywea_is_high); + assign web_i = defval(WEB, c_has_web, 0, c_yweb_is_high); + + + function defval; + input i; + input hassig; + input val; + input active_high; + begin + if(hassig == 1) + begin + if (active_high == 1) + defval = i; + else + defval = ~i; + end + else + defval = val; + end + endfunction + + function max; + input a; + input b; + begin + max = (a > b) ? a : b; + end + endfunction + + function a_is_X; + input [c_width_a-1 : 0] i; + integer j ; + begin + a_is_X = 1'b0; + for(j = 0; j < c_width_a; j = j + 1) + begin + if(i[j] === 1'bx) + a_is_X = 1'b1; + end // loop + end + endfunction + + function b_is_X; + input [c_width_b-1 : 0] i; + integer j ; + begin + b_is_X = 1'b0; + for(j = 0; j < c_width_b; j = j + 1) + begin + if(i[j] === 1'bx) + b_is_X = 1'b1; + end // loop + end + endfunction + + function [c_width_a-1:0] hexstr_conv; + input [(c_width_a*8)-1:0] def_data; + + integer index,i,j; + reg [3:0] bin; + + begin + index = 0; + hexstr_conv = 'b0; + for( i=c_width_a-1; i>=0; i=i-1 ) + begin + case (def_data[7:0]) + 8'b00000000 : + begin + bin = 4'b0000; + i = -1; + end + 8'b00110000 : bin = 4'b0000; + 8'b00110001 : bin = 4'b0001; + 8'b00110010 : bin = 4'b0010; + 8'b00110011 : bin = 4'b0011; + 8'b00110100 : bin = 4'b0100; + 8'b00110101 : bin = 4'b0101; + 8'b00110110 : bin = 4'b0110; + 8'b00110111 : bin = 4'b0111; + 8'b00111000 : bin = 4'b1000; + 8'b00111001 : bin = 4'b1001; + 8'b01000001 : bin = 4'b1010; + 8'b01000010 : bin = 4'b1011; + 8'b01000011 : bin = 4'b1100; + 8'b01000100 : bin = 4'b1101; + 8'b01000101 : bin = 4'b1110; + 8'b01000110 : bin = 4'b1111; + 8'b01100001 : bin = 4'b1010; + 8'b01100010 : bin = 4'b1011; + 8'b01100011 : bin = 4'b1100; + 8'b01100100 : bin = 4'b1101; + 8'b01100101 : bin = 4'b1110; + 8'b01100110 : bin = 4'b1111; + default : + begin + if (c_yydisable_warnings == 0) begin + $display("ERROR in %m at time %t: NOT A HEX CHARACTER",$time); + end + bin = 4'bx; + end + endcase + for( j=0; j<4; j=j+1) + begin + if ((index*4)+j < c_width_a) + begin + hexstr_conv[(index*4)+j] = bin[j]; + end + end + index = index + 1; + def_data = def_data >> 8; + end + end + endfunction + + function [c_width_b-1:0] hexstr_conv_b; + input [(c_width_b*8)-1:0] def_data; + + integer index,i,j; + reg [3:0] bin; + + begin + index = 0; + hexstr_conv_b = 'b0; + for( i=c_width_b-1; i>=0; i=i-1 ) + begin + case (def_data[7:0]) + 8'b00000000 : + begin + bin = 4'b0000; + i = -1; + end + 8'b00110000 : bin = 4'b0000; + 8'b00110001 : bin = 4'b0001; + 8'b00110010 : bin = 4'b0010; + 8'b00110011 : bin = 4'b0011; + 8'b00110100 : bin = 4'b0100; + 8'b00110101 : bin = 4'b0101; + 8'b00110110 : bin = 4'b0110; + 8'b00110111 : bin = 4'b0111; + 8'b00111000 : bin = 4'b1000; + 8'b00111001 : bin = 4'b1001; + 8'b01000001 : bin = 4'b1010; + 8'b01000010 : bin = 4'b1011; + 8'b01000011 : bin = 4'b1100; + 8'b01000100 : bin = 4'b1101; + 8'b01000101 : bin = 4'b1110; + 8'b01000110 : bin = 4'b1111; + 8'b01100001 : bin = 4'b1010; + 8'b01100010 : bin = 4'b1011; + 8'b01100011 : bin = 4'b1100; + 8'b01100100 : bin = 4'b1101; + 8'b01100101 : bin = 4'b1110; + 8'b01100110 : bin = 4'b1111; + default : + begin + if (c_yydisable_warnings == 0) begin + $display("ERROR in %m at time %t: NOT A HEX CHARACTER",$time); + end + bin = 4'bx; + end + endcase + for( j=0; j<4; j=j+1) + begin + if ((index*4)+j < c_width_b) + begin + hexstr_conv_b[(index*4)+j] = bin[j]; + end + end + index = index + 1; + def_data = def_data >> 8; + end + end + endfunction + + + + + +// Initialize memory contents to 0 for now . + + initial begin + sinita_value = 'b0 ; + sinitb_value = 'b0 ; + + default_data = hexstr_conv(c_default_data); + if (c_has_sinita == 1 ) + sinita_value = hexstr_conv(c_sinita_value); + if (c_has_sinitb == 1 ) + sinitb_value = hexstr_conv_b(c_sinitb_value); + for(i = 0; i < c_depth_a; i = i + 1) + ram_temp[i] = default_data; + if (c_has_default_data == 0) + $readmemb(c_mem_init_file, ram_temp) ; + + for(i = 0; i < c_depth_a; i = i + 1) + for(j = 0; j < c_width_a; j = j + 1) + begin + bitval = (1'b1 << j); + mem[(i*c_width_a) + j] = (ram_temp[i] & bitval) >> j; + end + recovery_a = 0; + recovery_b = 0; + for (k = 0; k <= c_pipe_stages_a; k = k + 1) + pipelinea[k] = sinita_value ; + for (l = 0; l <= c_pipe_stages_b; l = l + 1) + pipelineb[l] = sinitb_value ; + for (m = 0; m <= c_pipe_stages_a; m = m + 1) + sub_rdy_a[m] = 0 ; + for (n = 0; n <= c_pipe_stages_b; n = n + 1) + sub_rdy_b[n] = 0 ; + doa_out = sinita_value ; + dob_out = sinitb_value ; + nda_q = 0; + ndb_q = 0; + new_data_a_q = 0 ; + new_data_b_q = 0 ; + dia_q = 0; + dib_q = 0; + addra_q = 0; + addrb_q = 0; + wea_q = 0; + web_q = 0; + #1 douta_out = sinita_value; + #1 doutb_out = sinitb_value; + #1 rdya_int = 0; + #1 rdyb_int = 0; + end + + + always @(addra_int or addrb_int) begin // check address collision + address_collision <= 1'b0; + for (ci = 0; ci < c_width_a; ci = ci + 1) begin // absolute address A + for (cj = 0; cj < c_width_b; cj = cj + 1) begin // absolute address B + if ((addra_int * c_width_a + ci) == (addrb_int * c_width_b + cj)) begin + address_collision <= 1'b1; + end + end + end + end +/*********************************************************************************************************** +* The following 3 always blocks handle memory inputs for the case of an address collision on ADDRA and ADDRB +***********************************************************************************************************/ + always @(posedge recovery_a or posedge recovery_b) begin + if (((wr_mode_a == 2'b01) && (wr_mode_b == 2'b01)) || + ((wr_mode_a != 2'b01) && (wr_mode_b != 2'b01))) begin + if (wea_int == 1 && web_int == 1) begin + if (addra_int < c_depth_a) + for (dmi = 0; dmi < c_width_a; dmi = dmi + 1) begin + for (dmj = 0; dmj < c_width_b; dmj = dmj + 1) begin + if ((addra_int * c_width_a + dmi) == (addrb_int * c_width_b + dmj)) begin +//Fixed read-first collision +// mem[addra_int * c_width_a + dmi] <= 1'bX; + if ((wr_mode_a == 2'b01) && (wr_mode_b == 2'b01)) + begin + doa_out[dmi] <= 1'bX; + dob_out[dmj] <= 1'bX; + end + else + mem[addra_int * c_width_a + dmi] <= 1'bX; + end + end + end + else begin + //Warning Condition: + //Write Mode PortA is "Read First" and Write Mode PortB is "Read First" and WEA = 1 and WEB = 1 and ADDRA out of the valid range + //or + //Write Mode PortA is not "Read First" and Write Mode PortB is not "Read First" and WEA = 1 and WEB = 1 and ADDRA out of the valid range + if (c_yydisable_warnings == 0) begin + $display("Invalid Address Warning #1: Warning in %m at time %t: Port A address %d (%b) of block memory invalid. Valid depth configured as 0 to %d",$time,addra_int,addra_int,c_depth_a-1); + end + doa_out <= {c_width_a{1'bX}}; // assign data bus to X + end + end + end + recovery_a <= 0; + recovery_b <= 0; + end + + always @(posedge recovery_a or posedge recovery_b) begin + if ((wr_mode_a == 2'b01) && (wr_mode_b != 2'b01)) begin + if (wea_int == 1 && web_int == 1) begin + if (addra_int < c_depth_a) + for (dni = 0; dni < c_width_a; dni = dni + 1) begin + for (dnj = 0; dnj < c_width_b; dnj = dnj + 1) begin + if ((addra_int * c_width_a + dni) == (addrb_int * c_width_b + dnj)) begin + mem[addra_int * c_width_a + dni] <= dia_int[dni]; + end + end + end + else begin + //Warning Condition: + //Write Mode PortA is "Read First" and Write Mode PortB is not "Read First" and WEA = 1 and WEB = 1 and ADDRA out of the valid range + if (c_yydisable_warnings == 0) begin + $display("Invalid Address Warning #2: Warning in %m at time %t: Port A address %d (%b) of block memory invalid. Valid depth configured as 0 to %d",$time,addra_int,addra_int,c_depth_a-1); + end + doa_out <= {c_width_a{1'bX}}; // assign data bus to X + end + end + end + end + + always @(posedge recovery_a or posedge recovery_b) begin + if ((wr_mode_a != 2'b01) && (wr_mode_b == 2'b01)) begin + if (wea_int == 1 && web_int == 1) begin + if (addrb_int < c_depth_b) + for (doi = 0; doi < c_width_a; doi = doi + 1) begin + for (doj = 0; doj < c_width_b; doj = doj + 1) begin + if ((addra_int * c_width_a + doi) == (addrb_int * c_width_b + doj)) begin + mem[addrb_int * c_width_b + doj] <= dib_int[doj]; + end + end + end + else begin + //Warning Condition: + //Write Mode PortA is not "Read First" and Write Mode PortB is "Read First" and WEA = 1 and WEB = 1 and ADDRB out of the valid range + if (c_yydisable_warnings == 0) begin + $display("Invalid Address Warning #3: Warning in %m at time %t: Port B address %d (%b) of block memory invalid. Valid depth configured as 0 to %d",$time,addrb_int,addrb_int,c_depth_b-1); + end + dob_out <= {c_width_b{1'bX}}; // assign data bus to X + end + end + end + end +/*********************************************************************************************************** +*The following 4 always blocks handle memory outputs for the case of an address collision on ADDRA and ADDRB +***********************************************************************************************************/ + always @(posedge recovery_a or posedge recovery_b) begin + if ((wr_mode_b == 2'b00) || (wr_mode_b == 2'b10)) begin + if ((wea_int == 0) && (web_int == 1) && (ssra_int == 0)) begin + if (addra_int < c_depth_a) + for (dai = 0; dai < c_width_a; dai = dai + 1) begin + for (daj = 0; daj < c_width_b; daj = daj + 1) begin + if ((addra_int * c_width_a + dai) == (addrb_int * c_width_b + daj)) begin + doa_out[dai] <= 1'bX; + end + end + end + else begin + //Warning Condition: + //Write Mode PortB is "Write First" and WEA = 0 and WEB = 1 and SINITA = 0 and ADDRA out of the valid range + //or + //Write Mode PortB is "No Change" and WEA = 0 and WEB = 1 and SINITA = 0 and ADDRA out of the valid range + if (c_yydisable_warnings == 0) begin + $display("Invalid Address Warning #4: Warning in %m at time %t: Port A address %d (%b) of block memory invalid. Valid depth configured as 0 to %d",$time,addra_int,addra_int,c_depth_a-1); + end + doa_out <= {c_width_a{1'bX}}; // assign data bus to X + end + end + end + end + + always @(posedge recovery_a or posedge recovery_b) begin + if ((wr_mode_a == 2'b00) || (wr_mode_a == 2'b10)) begin + if ((wea_int == 1) && (web_int == 0) && (ssrb_int == 0)) begin + if (addrb_int < c_depth_b) + for (dbi = 0; dbi < c_width_a; dbi = dbi + 1) begin + for (dbj = 0; dbj < c_width_b; dbj = dbj + 1) begin + if ((addra_int * c_width_a + dbi) == (addrb_int * c_width_b + dbj)) begin + dob_out[dbj] <= 1'bX; + end + end + end + else begin + //Warning Condition: + //Write Mode PortA is "Write First" and WEA = 1 and WEB = 0 and SINITB = 0 and ADDRB out of the valid range + //or + //Write Mode PortA is "No Change" and WEA = 1 and WEB = 0 and SINITB = 0 and ADDRB out of the valid range + if (c_yydisable_warnings == 0) begin + $display("Invalid Address Warning #5: Warning in %m at time %t: Port B address %d (%b) of block memory invalid. Valid depth configured as 0 to %d",$time,addrb_int,addrb_int,c_depth_b-1); + end + dob_out <= {c_width_b{1'bX}}; // assign data bus to X + end + end + end + end + + always @(posedge recovery_a or posedge recovery_b) begin + if (((wr_mode_a == 2'b00) && (wr_mode_b == 2'b00)) || + ((wr_mode_a != 2'b10) && (wr_mode_b == 2'b10)) || + ((wr_mode_a == 2'b01) && (wr_mode_b == 2'b00))) begin + if ((wea_int == 1) && (web_int == 1) && (ssra_int == 0)) begin + if (addra_int < c_depth_a) + for (dci = 0; dci < c_width_a; dci = dci + 1) begin + for (dcj = 0; dcj < c_width_b; dcj = dcj + 1) begin + if ((addra_int * c_width_a + dci) == (addrb_int * c_width_b + dcj)) begin + doa_out[dci] <= 1'bX; + end + end + end + else begin + //Warning Condition: + //Write Mode PortA is "Write First" and Write Mode PortB is "Write First" and WEA = 1 and WEB = 1 and SINITA = 0 and ADDRA out of the valid range + //or + //Write Mode PortA is not "No Change" and Write Mode PortB is "No Change" and WEA = 1 and WEB = 1 and SINITA = 0 and ADDRA out of the valid range + //or + //Write Mode PortA is "Read First" and Write Mode PortB is "Write First" and WEA = 1 and WEB = 1 and SINITA = 0 and ADDRA out of the valid range + if (c_yydisable_warnings == 0) begin + $display("Invalid Address Warning #6: Warning in %m at time %t: Port A address %d (%b) of block memory invalid. Valid depth configured as 0 to %d",$time,addra_int,addra_int,c_depth_a-1); + end + doa_out <= {c_width_a{1'bX}}; // assign data bus to X + end + end + end + end + + always @(posedge recovery_a or posedge recovery_b) begin + if (((wr_mode_a == 2'b00) && (wr_mode_b == 2'b00)) || + ((wr_mode_a == 2'b10) && (wr_mode_b != 2'b10)) || + ((wr_mode_a == 2'b00) && (wr_mode_b == 2'b01))) begin + if ((wea_int == 1) && (web_int == 1) && (ssrb_int == 0)) begin + if (addrb_int < c_depth_b) + for (ddi = 0; ddi < c_width_a; ddi = ddi + 1) begin + for (ddj = 0; ddj < c_width_b; ddj = ddj + 1) begin + if ((addra_int * c_width_a + ddi) == (addrb_int * c_width_b + ddj)) begin + dob_out[ddj] <= 1'bX; + end + end + end + else begin + //Warning Condition: + //Write Mode PortA is "Write First" and Write Mode PortB is "Write First" and WEA = 1 and WEB = 1 and SINITB = 0 and ADDRB out of the valid range + //or + //Write Mode PortA is "No Change" and Write Mode PortB is not "No Change" and WEA = 1 and WEB = 1 and SINITB = 0 and ADDRB out of the valid range + //or + //Write Mode PortA is "Write First" and Write Mode PortB is "Read First" and WEA = 1 and WEB = 1 and SINITB = 0 and ADDRB out of the valid range + if (c_yydisable_warnings == 0) begin + $display("Invalid Address Warning #7: Warning in %m at time %t: Port B address %d (%b) of block memory invalid. Valid depth configured as 0 to %d",$time,addrb_int,addrb_int,c_depth_b-1); + end + dob_out <= {c_width_b{1'bX}}; // assign data bus to X + end + end + end + end + + // Parity Section is deleted + + initial begin + case (c_write_modea) + `c_write_first : wr_mode_a <= 2'b00; + `c_read_first : wr_mode_a <= 2'b01; + `c_no_change : wr_mode_a <= 2'b10; + default : begin + if (c_yydisable_warnings == 0) begin + $display("Error in %m at time %t: c_write_modea = %s is not WRITE_FIRST, READ_FIRST or NO_CHANGE.",$time, c_write_modea); + end + $finish; + end + endcase + end + + initial begin + case (c_write_modeb) + `c_write_first : wr_mode_b <= 2'b00; + `c_read_first : wr_mode_b <= 2'b01; + `c_no_change : wr_mode_b <= 2'b10; + default : begin + if (c_yydisable_warnings == 0) begin + $display("Error in %m at time %t: c_write_modeb = %s is not WRITE_FIRST, READ_FIRST or NO_CHANGE.",$time, c_write_modeb); + end + $finish; + end + endcase + end + +// Port A + + +// Generate ouput control signals for Port A: RFDA and RDYA + + always @ (rfda_int or rdya_int) + begin + if (c_has_rfda == 1) + RFDA = rfda_int ; + else + RFDA = 1'b0 ; + + if ((c_has_rdya == 1) && (c_has_nda == 1) && (c_has_rfda == 1) ) + RDYA = rdya_int; + else + RDYA = 1'b0 ; + end + + always @ (ena_int ) + begin + if (ena_int == 1'b1) + rfda_int <= 1'b1 ; + else + rfda_int <= 1'b0 ; + end + +// Gate nd signal with en + + assign nda_int = ena_int && nda_i ; + +// Register hanshaking signals for port A + + always @ (posedge clka_int) + begin + if (ena_int == 1'b1) + begin + if (ssra_int == 1'b1) + nda_q <= 1'b0 ; + else + nda_q <= nda_int ; + end + else + nda_q <= nda_q ; + end + +// Register data/ address / we inputs for port A + + always @ (posedge clka_int) + begin + if (ena_int == 1'b1) + begin + dia_q <= dia_i ; + addra_q <= addra_i ; + wea_q <= wea_i ; + end + end + + +// Select registered or non-registered write enable for Port A + + always @ ( wea_i or wea_q ) + begin + if (c_reg_inputsa == 1) + wea_int = wea_q ; + else + wea_int = wea_i ; + end + +// Select registered or non-registered data/address/nd inputs for Port A + + always @ ( dia_i or dia_q ) + begin + if ( c_reg_inputsa == 1) + dia_int = dia_q; + else + dia_int = dia_i; + end + + always @ ( addra_i or addra_q or nda_q or nda_int ) + begin + if ( c_reg_inputsa == 1) + begin + addra_int = addra_q ; + if ((wea_q == 1'b1) && (c_write_modea == 2)) + new_data_a = 1'b0 ; + else + new_data_a = nda_q ; + end + else + begin + addra_int = addra_i; + if ((wea_i == 1'b1) && (c_write_modea == 2)) + new_data_a = 1'b0 ; + else + new_data_a = nda_int ; + end + end + +// Register the new_data signal for Port A to track the synchronous RAM output + + always @(posedge clka_int) + begin + if (ena_int == 1'b1) + begin + if (ssra_int == 1'b1) + new_data_a_q <= 1'b0 ; + else + // Do not update RDYA if write mode is no_change and wea=1 + //if (!(c_write_modea == 2 && wea_int == 1)) begin + // rii1 : 10/20 Make dual port behavior the same as single port + new_data_a_q <= new_data_a ; + //end + end + end + +// Generate data outputs for Port A + + + /*************************************************************** + *The following always block assigns the value for the DOUTA bus + ***************************************************************/ + always @(posedge clka_int) begin + if (ena_int == 1'b1) begin + if (ssra_int == 1'b1) begin + // for ( ai = 0; ai < c_width_a; ai = ai + 1) + // doa_out[ai] <= sinita_value[ai]; + doa_out <= sinita_value; + end + else begin + //The following IF block assigns the output for a write operation + if (wea_int == 1'b1) begin + if (wr_mode_a == 2'b00) begin + if (addra_int < c_depth_a) + // for ( aj = 0; aj < c_width_a; aj = aj + 1) + // doa_out[aj] <= dia_int[aj] ; + doa_out <= dia_int ; + else begin + //Warning Condition (Error occurs on rising edge of CLKA): + //Write Mode PortA is "Write First" and ENA = 1 and SINITA = 0 and WEA = 1 and ADDRA out of the valid range + if (c_yydisable_warnings == 0) begin + $display("Invalid Address Warning #8: Warning in %m at time %t: Port A address %d (%b) of block memory invalid. Valid depth configured as 0 to %d",$time,addra_int,addra_int,c_depth_a-1); + end + doa_out <= {c_width_a{1'bX}}; // assign data bus to X + end + end + else if (wr_mode_a == 2'b01) begin + if (addra_int < c_depth_a) + // for ( ak = 0; ak < c_width_a; ak = ak + 1) + // doa_out[ak] <= mem[(addra_int*c_width_a) + ak]; + doa_out <= mem >> (addra_int*c_width_a); + else begin + //Warning Condition (Error occurs on rising edge of CLKA): + //Write Mode PortA is "Read First" and ENA = 1 and SINITA = 0 and WEA = 1 and ADDRA out of the valid range + if (c_yydisable_warnings == 0) begin + $display("Invalid Address Warning #9: Warning in %m at time %t: Port A address %d (%b) of block memory invalid. Valid depth configured as 0 to %d",$time,addra_int,addra_int,c_depth_a-1); + end + doa_out <= {c_width_a{1'bX}}; //assign data bus to X + end + end + else begin + if (addra_int < c_depth_a) + doa_out <= doa_out; + else begin + //Warning Condition (Error occurs on rising edge of CLKA): + //Write Mode PortA is "No Change" and ENA = 1 and SINITA = 0 and WEA = 1 and ADDRA out of the valid range + if (c_yydisable_warnings == 0) begin + $display("Invalid Address Warning #10: Warning in %m at time %t: Port A address %d (%b) of block memory invalid. Valid depth configured as 0 to %d",$time,addra_int,addra_int,c_depth_a-1); + end + doa_out <= {c_width_a{1'bX}}; //assign data bus to X + end + end + end + //The following ELSE block assigns the output for a read operation + else begin + if (addra_int < c_depth_a) + // for ( al = 0; al < c_width_a; al = al + 1) + // doa_out[al] <= mem[(addra_int*c_width_a) + al]; + doa_out <= mem >> (addra_int*c_width_a); + else begin + if (c_has_douta == 1)//New IF statement to remove read errors when port is write only + begin + //Warning Condition (Error occurs on rising edge of CLKA): + //ENA = 1 and SINITA = 0 and WEA = 0 and ADDRA out of the valid range + if (c_yydisable_warnings == 0) begin + $display("Invalid Address Warning #11: Warning in %m at time %t: Port A address %d (%b) of block memory invalid. Valid depth configured as 0 to %d",$time,addra_int,addra_int,c_depth_a-1); + end + doa_out <= {c_width_a{1'bX}}; //assign data bus to X + end + end + end + end + end + end + /*************************************************************************************** + *The following always block assigns the DINA bus to the memory during a write operation + ***************************************************************************************/ + always @(posedge clka_int) begin + if (ena_int == 1'b1 && wea_int == 1'b1) begin + if (addra_int < c_depth_a) + for ( am = 0; am < c_width_a; am = am + 1) + mem[(addra_int*c_width_a) + am] <= dia_int[am]; + else begin + //Warning Condition (Error occurs on rising edge of CLKA): + //ENA = 1 and WEA = 1 and ADDRA out of the valid range + if (c_yydisable_warnings == 0) begin + $display("Invalid Address Warning #12: Warning in %m at time %t: Port A address %d (%b) of block memory invalid. Valid depth configured as 0 to %d",$time,addra_int,addra_int,c_depth_a-1); + end + doa_out <= {c_width_a{1'bX}}; //assign data bus to X + end + end + end + + // output pipelines for Port A + + always @(posedge clka_int) begin + if (ena_int == 1'b1 && c_pipe_stages_a > 0) + begin + for (i = c_pipe_stages_a; i >= 1; i = i -1 ) + begin + if (ssra_int == 1'b1 && ena_int == 1'b1 ) + begin + pipelinea[i] <= sinita_value ; + sub_rdy_a[i] <= 0 ; + end + else + begin + // Do not change output when no_change and web=1 +// if (!(c_write_modea == 2 && wea_int == 1)) begin + if (i==1) + pipelinea[i] <= doa_out ; + else + pipelinea[i] <= pipelinea[i-1] ; +// end // if (!(c_write_modea == 2 && wea_int == 1)) + if (i==1) + sub_rdy_a[i] <= new_data_a_q ; + else + sub_rdy_a[i] <= sub_rdy_a[i-1] ; + end + end + end + end + +// Select pipeline output if c_pipe_stages_a > 0 + + always @( pipelinea[c_pipe_stages_a] or sub_rdy_a[c_pipe_stages_a] or new_data_a_q or doa_out ) begin + if (c_pipe_stages_a == 0 ) + begin + douta_out = doa_out ; + rdya_int = new_data_a_q; + end + else + begin + douta_out = pipelinea[c_pipe_stages_a]; + rdya_int = sub_rdy_a[c_pipe_stages_a]; + end + end + + + // Select Port A data outputs based on c_has_douta parameter + + always @( douta_out ) begin + if ( c_has_douta == 1) + douta_mux_out = douta_out ; + else + douta_mux_out = 0 ; + end + + + +// Port B + + + +// Generate output control signals for Port B: RFDB and RDYB + + always @ (rfdb_int or rdyb_int) + begin + if (c_has_rfdb == 1) + RFDB = rfdb_int ; + else + RFDB = 1'b0 ; + + if ((c_has_rdyb == 1) && (c_has_ndb == 1) && (c_has_rfdb == 1) ) + RDYB = rdyb_int; + else + RDYB = 1'b0 ; + end + + always @ (enb_int ) + begin + if ( enb_int == 1'b1 ) + rfdb_int = 1'b1 ; + else + rfdb_int = 1'b0 ; + end + +// Gate nd signal with en + + assign ndb_int = enb_int && ndb_i ; + +// Register hanshaking signals for port B + + always @ (posedge clkb_int) + begin + if (enb_int == 1'b1) + begin + if (ssrb_int == 1'b1) + ndb_q <= 1'b0 ; + else + ndb_q <= ndb_int ; + end + else + ndb_q <= ndb_q; + end + +// Register data / address / we inputs for port B + + always @ (posedge clkb_int) + begin + if (enb_int == 1'b1) + begin + dib_q <= dib_i ; + addrb_q <= addrb_i ; + web_q <= web_i ; + end + end + +// Select registered or non-registered write enable for port B + + always @ (web_i or web_q ) + begin + if (c_reg_inputsb == 1) + web_int = web_q ; + else + web_int = web_i ; + end + + + +// Select registered or non-registered data/address/nd inputs for Port B + + always @ ( dib_i or dib_q ) + begin + if ( c_reg_inputsb == 1) + dib_int = dib_q; + else + dib_int = dib_i; + end + + always @ ( addrb_i or addrb_q or ndb_q or ndb_int or web_q or web_i) + begin + if ( c_reg_inputsb == 1) + begin + addrb_int = addrb_q ; + if ((web_q == 1'b1) && (c_write_modeb == 2)) + new_data_b = 1'b0 ; + else + new_data_b = ndb_q ; + end + else + begin + addrb_int = addrb_i; + if ((web_i == 1'b1) && (c_write_modeb == 2)) + new_data_b = 1'b0 ; + else + new_data_b = ndb_int ; + end + end + +// Register the new_data signal for Port B to track the synchronous RAM output + + always @(posedge clkb_int) + begin + if (enb_int == 1'b1 ) + begin + if (ssrb_int == 1'b1) + new_data_b_q <= 1'b0 ; + else + // Do not update RDYB if write mode is no_change and web=1 + //if (!(c_write_modeb == 2 && web_int == 1)) begin + // rii1 : 10/20 Make dual port behavior the same as single port + new_data_b_q <= new_data_b ; + //end + end + end + + + + + +// Generate data outputs for Port B + + + /*************************************************************** + *The following always block assigns the value for the DOUTB bus + ***************************************************************/ + always @(posedge clkb_int) begin + if (enb_int == 1'b1) begin + if (ssrb_int == 1'b1) begin + // for (bi = 0; bi < c_width_b; bi = bi + 1) + // dob_out[bi] <= sinitb_value[bi]; + dob_out <= sinitb_value; + end + else begin + //The following IF block assigns the output for a write operation + if (web_int == 1'b1) begin + if (wr_mode_b == 2'b00) begin + if (addrb_int < c_depth_b) + // for (bj = 0; bj < c_width_b; bj = bj + 1) + // dob_out[bj] <= dib_int[bj]; + dob_out <= dib_int; + else begin + //Warning Condition (Error occurs on rising edge of CLKB): + //Write Mode PortB is "Write First" and ENB = 1 and SINITB = 0 and WEB = 1 and ADDRB out of the valid range + if (c_yydisable_warnings == 0) begin + $display("Invalid Address Warning #13: Warning in %m at time %t: Port B address %d (%b) of block memory invalid. Valid depth configured as 0 to %d",$time,addrb_int,addrb_int,c_depth_b-1); + end + dob_out <= {c_width_b{1'bX}}; //assign data bus to X + end + end + else if (wr_mode_b == 2'b01) begin + if (addrb_int < c_depth_b) + // for (bk = 0; bk < c_width_b; bk = bk + 1) + // dob_out[bk] <= mem[(addrb_int*c_width_b) + bk]; + dob_out <= mem >> (addrb_int*c_width_b); + else begin + //Warning Condition (Error occurs on rising edge of CLKB): + //Write Mode PortB is "Read First" and ENB = 1 and SINITB = 0 and WEB = 1 and ADDRB out of the valid range + if (c_yydisable_warnings == 0) begin + $display("Invalid Address Warning #14: Warning in %m at time %t: Port B address %d (%b) of block memory invalid. Valid depth configured as 0 to %d",$time,addrb_int,addrb_int,c_depth_b-1); + end + dob_out <= {c_width_b{1'bX}}; //assign data bus to X + end + end + else begin + if (addrb_int < c_depth_b) + dob_out <= dob_out ; + else begin + //Warning Condition (Error occurs on rising edge of CLKB): + //Write Mode PortB is "No Change" and ENB = 1 and SINITB = 0 and WEB = 1 and ADDRB out of the valid range + if (c_yydisable_warnings == 0) begin + $display("Invalid Address Warning #15: Warning in %m at time %t: Port B address %d (%b) of block memory invalid. Valid depth configured as 0 to %d",$time,addrb_int,addrb_int,c_depth_b-1); + end + dob_out <= {c_width_b{1'bX}}; //assign data bus to X + end + end + end + //The following ELSE block assigns the output for a read operation + else begin + if (addrb_int < c_depth_b) + // for (bl = 0; bl < c_width_b; bl = bl + 1) + // dob_out[bl] <= mem[(addrb_int*c_width_b) + bl]; + dob_out <= mem >> (addrb_int*c_width_b); + else begin + if (c_has_doutb == 1)//New IF statement to remove read errors when port is write only + begin + //Warning Condition (Error occurs on rising edge of CLKB): + //ENB = 1 and SINITB = 0 and WEB = 0 and ADDRB out of the valid range + if (c_yydisable_warnings == 0) begin + $display("Invalid Address Warning #16: Warning in %m at time %t: Port B address %d (%b) of block memory invalid. Valid depth configured as 0 to %d",$time,addrb_int,addrb_int,c_depth_b-1); + end + dob_out <= {c_width_b{1'bX}}; //assign data bus to X + end + end + end + end + end + end + /*************************************************************************************** + *The following always block assigns the DINA bus to the memory during a write operation + ***************************************************************************************/ + always @(posedge clkb_int) begin + if (enb_int == 1'b1 && web_int == 1'b1) begin + if (addrb_int < c_depth_b) + for (bm = 0; bm < c_width_b; bm = bm + 1) + mem[(addrb_int*c_width_b) + bm] <= dib_int[bm]; + else begin + //Warning Condition (Error occurs on rising edge of CLKB): + //ENB = 1 and WEB = 1 and ADDRB out of the valid range + if (c_yydisable_warnings == 0) begin + $display("Invalid Address Warning #17: Warning in %m at time %t: Port B address %d (%b) of block memory invalid. Valid depth configured as 0 to %d",$time,addrb_int,addrb_int,c_depth_b-1); + end + dob_out <= {c_width_b{1'bX}}; // assign data bus to X + end + end + end + + // output pipelines for Port B + + always @(posedge clkb_int) begin + if (enb_int == 1'b1 && c_pipe_stages_b > 0) + begin + for (j = c_pipe_stages_b; j >= 1; j = j -1 ) + begin + if (ssrb_int == 1'b1 && enb_int == 1'b1 ) + begin + pipelineb[j] <= sinitb_value ; + sub_rdy_b[j] <= 0 ; + end + else + begin + // Do not change output when no_change and web=1 +// if (!(c_write_modeb == 2 && web_int == 1)) begin + if (j==1) + pipelineb[j] <= dob_out ; + else + pipelineb[j] <= pipelineb[j-1] ; +// end + if (j==1) + sub_rdy_b[j] <= new_data_b_q ; + else + sub_rdy_b[j] <= sub_rdy_b[j-1] ; + end + end + end + end + +// Select pipeline for B if c_pipe_stages_b > 0 + + always @(pipelineb[c_pipe_stages_b] or sub_rdy_b[c_pipe_stages_b] or new_data_b_q or dob_out) begin + if ( c_pipe_stages_b == 0 ) + begin + doutb_out = dob_out ; + rdyb_int = new_data_b_q; + end + else + begin + rdyb_int = sub_rdy_b[c_pipe_stages_b]; + doutb_out = pipelineb[c_pipe_stages_b]; + end + end + + +// Select Port B data outputs based on c_has_doutb parameter + + always @( doutb_out) begin + if ( c_has_doutb == 1) + doutb_mux_out = doutb_out ; + else + doutb_mux_out = 0 ; + end + + + + + + specify + + // when both CLKA and CLKB are active on the positive edge + $recovery (posedge CLKB, posedge CLKA &&& collision_posa_posb, 1, recovery_b); + $recovery (posedge CLKA, posedge CLKB &&& collision_posa_posb, 1, recovery_a); + + // when both CLKA active on positive edge and CLKB are active on the negative edge + $recovery (negedge CLKB, posedge CLKA &&& collision_posa_negb, 1, recovery_b); + $recovery (posedge CLKA, negedge CLKB &&& collision_posa_negb, 1, recovery_a); + + // when both CLKA active on negative edge and CLKB are active on the positive edge + $recovery (posedge CLKB, negedge CLKA &&& collision_nega_posb, 1, recovery_b); + $recovery (negedge CLKA, posedge CLKB &&& collision_nega_posb, 1, recovery_a); + + // when both CLKA and CLKB are active on the negative edge + $recovery (negedge CLKB, negedge CLKA &&& collision_nega_negb, 1, recovery_b); + $recovery (negedge CLKA, negedge CLKB &&& collision_nega_negb, 1, recovery_a); + + endspecify + +endmodule + +`endcelldefine diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/BLKMEMSP_V4_0.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/BLKMEMSP_V4_0.v new file mode 100644 index 0000000..e9adcf5 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/BLKMEMSP_V4_0.v @@ -0,0 +1,534 @@ +/***************************************************************************** + * $Id: BLKMEMSP_V4_0.v,v 1.17 2008/09/08 20:06:34 akennedy Exp $ + ***************************************************************************** + * Block Memory Compiler - Verilog Behavioral Model + ***************************************************************************** + * + * This File is owned and controlled by Xilinx and must be used solely + * for design, simulation, implementation and creation of design files + * limited to Xilinx devices or technologies. Use with non-Xilinx + * devices or technologies is expressly prohibited and immediately + * terminates your license. + * + * Xilinx products are not intended for use in life support + * appliances, devices, or systems. Use in such applications is + * expressly prohibited. + * + * **************************** + * ** Copyright Xilinx, Inc. ** + * ** All rights reserved. ** + * **************************** + * + ************************************************************************* + * Filename: blkmemsp_v4_0 + * + * Decsription: Single Port V2 BRAM behavioral model. Extendable depth/width. + * The behavior for EN = `X`, WE = `X`, and for CLK transitions to + * or from `X` is not considered. + * + **************************************************************************/ +`timescale 1ns/10ps + +`celldefine + + +`define c_sp_rom 0 +`define c_sp_ram 1 +`define c_write_first 0 +`define c_read_first 1 +`define c_no_change 2 + +module BLKMEMSP_V4_0(DOUT, ADDR, DIN, EN, CLK, WE, SINIT, ND, RFD, RDY); + + parameter c_addr_width = 9 ; // controls address width of memory + parameter c_default_data = "0"; // indicates string of hex characters used to initialize memory + parameter c_depth = 512 ; // controls depth of memory + parameter c_enable_rlocs = 0 ; // core includes placement constraints + parameter c_has_default_data = 1; // initializes contents of memory to c_default_data + parameter c_has_din = 1 ; // indicates memory has data input pins + parameter c_has_en = 1 ; // indicates memory has a EN pin + parameter c_has_limit_data_pitch = 0 ; // + parameter c_has_nd = 0 ; // Memory has a new data pin + parameter c_has_rdy = 0 ; // Memory has result ready pin + parameter c_has_rfd = 0 ; // Memory has ready for data pin + parameter c_has_sinit = 1 ; // indicates memory has a SINIT pin + parameter c_has_we = 1 ; // indicates memory has a WE pin + parameter c_limit_data_pitch = 18; + parameter c_mem_init_file = "null.mif"; // controls which .mif file used to initialize memory + parameter c_pipe_stages = 1 ; // indicates the number of pipe stages needed in port A + parameter c_reg_inputs = 0 ; // indicates WE, ADDR, and DIN are registered + parameter c_sinit_value = "0000"; // indicates string of hex used to initialize output registers + parameter c_width = 32 ; // controls data width of memory + parameter c_write_mode = 2; // controls which write modes shall be used + + parameter c_ybottom_addr = "1024"; + parameter c_yclk_is_rising = 1; + parameter c_yen_is_high = 1; + parameter c_yhierarchy = "hierarchy1"; + parameter c_ymake_bmm = 1; + parameter c_yprimitive_type = "4kx4"; + parameter c_ysinit_is_high = 1; + parameter c_ytop_addr = "0"; + parameter c_yuse_single_primitive = 0; + parameter c_ywe_is_high = 1; + +// IO ports + + + output [c_width-1:0] DOUT; + input [c_addr_width-1:0] ADDR; + input [c_width-1:0] DIN; + input EN, CLK, WE, SINIT, ND; + output RFD, RDY; + + reg RFD ; + reg RDY ; + + reg [c_width-1:0] dout_int; // output of RAM + reg [c_width-1:0] pipe_out ; // output of pipeline stage + wire [c_width-1:0] DOUT = pipe_out ; + reg [c_depth*c_width-1:0] mem; + reg [24:0] count; + reg [1:0] wr_mode; + + wire [c_addr_width-1:0] addr_i = ADDR; + reg [c_addr_width-1:0] addr_int ; + reg [c_width-1:0] di_int ; + wire [c_width-1:0] di_i ; + wire clk_int ; + wire en_int ; + reg we_int ; + wire we_i ; + reg we_q ; + wire ssr_int ; + wire nd_int ; + wire nd_i ; + reg rfd_int ; + reg rdy_int ; + reg nd_q ; + reg [c_width-1:0] di_q ; + reg [c_addr_width-1:0] addr_q; + reg new_data ; + reg new_data_q ; // to track the synchronous PORT RAM output + + reg [c_width-1:0] default_data ; + reg [c_width-1:0] ram_temp [0:c_depth-1]; + reg [c_width-1:0] bitval; + reg [c_width-1:0] sinit_value; + + reg [(c_width-1) : 0] pipeline [0 : c_pipe_stages]; + reg sub_rdy[0 : c_pipe_stages]; + reg [10:0] ci, cj ; + reg [10:0] dmi, dmj, dni, dnj, doi, doj ; + integer i, j, k, l, m; + integer ai, aj, ak, al, am, an, ap ; + + +// Generate input control signals +// Combinational + +// Take care of ROM/RAM functionality + + assign clk_int = defval(CLK, 1, 1, c_yclk_is_rising); + assign we_i = defval(WE, c_has_we, 0, c_ywe_is_high); + assign di_i = (c_has_din == 1)?DIN:'b0; + assign en_int = defval(EN, c_has_en, 1, c_yen_is_high); + assign ssr_int = defval(SINIT , c_has_sinit , 0, c_ysinit_is_high); + assign nd_i = defval (ND, c_has_nd, 1, 1); + + +// tri0 GSR = glbl.GSR; + + function defval; + input i; + input hassig; + input val; + input active_high; + begin + if(hassig == 1) + begin + if (active_high == 1) + defval = i; + else + defval = ~i; + end + else + defval = val; + end + endfunction + + function max; + input a; + input b; + begin + max = (a > b) ? a : b; + end + endfunction + + function a_is_X; + input [c_width-1 : 0] i; + integer j ; + begin + a_is_X = 1'b0; + for(j = 0; j < c_width; j = j + 1) + begin + if(i[j] === 1'bx) + a_is_X = 1'b1; + end // loop + end + endfunction + + + function [c_width-1:0] hexstr_conv; + input [(c_width*8)-1:0] def_data; + + integer index,i,j; + reg [3:0] bin; + + begin + index = 0; + hexstr_conv = 'b0; + for( i=c_width-1; i>=0; i=i-1 ) + begin + case (def_data[7:0]) + 8'b00000000 : + begin + bin = 4'b0000; + i = -1; + end + 8'b00110000 : bin = 4'b0000; + 8'b00110001 : bin = 4'b0001; + 8'b00110010 : bin = 4'b0010; + 8'b00110011 : bin = 4'b0011; + 8'b00110100 : bin = 4'b0100; + 8'b00110101 : bin = 4'b0101; + 8'b00110110 : bin = 4'b0110; + 8'b00110111 : bin = 4'b0111; + 8'b00111000 : bin = 4'b1000; + 8'b00111001 : bin = 4'b1001; + 8'b01000001 : bin = 4'b1010; + 8'b01000010 : bin = 4'b1011; + 8'b01000011 : bin = 4'b1100; + 8'b01000100 : bin = 4'b1101; + 8'b01000101 : bin = 4'b1110; + 8'b01000110 : bin = 4'b1111; + 8'b01100001 : bin = 4'b1010; + 8'b01100010 : bin = 4'b1011; + 8'b01100011 : bin = 4'b1100; + 8'b01100100 : bin = 4'b1101; + 8'b01100101 : bin = 4'b1110; + 8'b01100110 : bin = 4'b1111; + default : + begin + $display("ERROR in %m at time %t : NOT A HEX CHARACTER",$time); + bin = 4'bx; + end + endcase + for( j=0; j<4; j=j+1) + begin + if ((index*4)+j < c_width) + begin + hexstr_conv[(index*4)+j] = bin[j]; + end + end + index = index + 1; + def_data = def_data >> 8; + end + end + endfunction + + +// Initialize memory contents to default_data for now . In future, read from .mif file and initialize the content properly + + initial begin + sinit_value = 'b0 ; + default_data = hexstr_conv(c_default_data); + if (c_has_sinit == 1 ) + sinit_value = hexstr_conv(c_sinit_value); + for(i = 0; i < c_depth; i = i + 1) + ram_temp[i] = default_data; + if (c_has_default_data == 0) + $readmemb(c_mem_init_file, ram_temp); + for(i = 0; i < c_depth; i = i + 1) + for(j = 0; j < c_width; j = j + 1) + begin + bitval = (1'b1 << j); + mem[(i*c_width) + j] = (ram_temp[i] & bitval) >> j; + end + for (k = 0; k <= c_pipe_stages; k = k + 1) + pipeline[k] = sinit_value ; + for (m = 0; m <= c_pipe_stages; m = m + 1) + sub_rdy[m] = 0 ; + pipe_out = sinit_value ; + dout_int = sinit_value ; + nd_q = 0 ; + new_data_q = 0 ; + di_q = 0 ; + addr_q = 0 ; + we_q = 0 ; + end + +// Generate output control signals RFD and RDY +// Combinational + + always @ ( rfd_int) + begin + if (c_has_rfd == 1) + RFD = rfd_int ; + else + RFD = 1'b0 ; + end + + always @ (en_int ) + begin + if (en_int == 1'b1) + rfd_int = 1'b1 ; + else + rfd_int = 1'b0 ; + end + + always @ ( rdy_int ) + begin + if ((c_has_rdy == 1) && (c_has_nd == 1) && (c_has_rfd == 1) ) + RDY = rdy_int ; + else + RDY = 1'b0 ; + end + + assign nd_int = en_int && nd_i ; // only pass nd through if en is 1 + +// Register hanshaking inputs + + always @(posedge clk_int ) + begin + if (en_int == 1'b1) + begin + if (ssr_int == 1'b1) + nd_q <= 1'b0 ; + else + nd_q <= nd_int; + end + else + nd_q <= nd_q ; + end +// Register data / address / data inputs + + always @(posedge clk_int ) + begin + if (en_int == 1'b1) + begin + di_q <= di_i ; + addr_q <= addr_i ; + we_q <= we_i ; + end + end + +// Register en input + +// always @(posedge clk_int ) +// begin +// en_q <= en_i ; +// end + +// Select registered or non-registered en signal + +// always @( en_i or en_q) +// begin +// if (c_reg_en == 1) +// en_int = en_q ; +// else +// en_int = en_i ; +// end + +// select registered or non-registered write enable + + always @( we_i or we_q) + begin + if (c_reg_inputs == 1 ) + we_int = we_q ; + else + we_int = we_i ; + end + +// select registered data/address/nd inputs + + always @( di_i or di_q) + begin + if ( c_reg_inputs == 1) + di_int = di_q ; + else + di_int = di_i ; + end + + always @( addr_i or addr_q or nd_q or nd_int ) + begin + if (c_reg_inputs == 1) + begin + addr_int = addr_q; + new_data = nd_q ; + end + else + begin + addr_int = addr_i ; + new_data = nd_int ; + end + end + +// Register the new_data signal to track the synchronous RAM output + + always @(posedge clk_int) + begin + if ( en_int == 1'b1 ) + begin + if (ssr_int == 1'b1) + new_data_q <= 0 ; + else + new_data_q <= new_data ; + end + end + +// Ininitialize A and B outputs for INIT_A and INIT_B when GSR asserted . + +// always @(GSR) +// if (GSR) begin +// assign dout_int = INIT[c_width-1:0]; +// end +// else begin +// deassign dout_int; +// end + + initial begin + case (c_write_mode) + `c_write_first : wr_mode <= 2'b00; + `c_read_first : wr_mode <= 2'b01; + `c_no_change : wr_mode <= 2'b10; + default : begin + $display("Error in %m at time %t: c_write_mode = %s is not WRITE_FIRST, READ_FIRST or NO_CHANGE.",$time , c_write_mode); + $finish; + end + endcase + end + + + /*************************************************************** + *The following always block assigns the value for the DOUT bus + ***************************************************************/ + always @(posedge clk_int) begin + if (en_int == 1'b1) begin + if (ssr_int == 1'b1) begin + for ( ai = 0; ai < c_width; ai = ai + 1) + dout_int[ai] <= sinit_value[ai]; + end + else begin + //The following IF block assigns the output for a write operation + if (we_int == 1'b1) begin + if (wr_mode == 2'b00) begin + if (addr_int < c_depth) + for (aj = 0; aj < c_width; aj = aj + 1) + dout_int[aj] <= di_int[aj]; + else + //Warning Condition (Error occurs on rising edge of CLK): + //Write Mode Port is "Write First" and EN = 1 and SINIT = 0 and WE = 1 and ADDR out of the valid range + $display("Invalid Address Warning #1: Warning in %m at time %t: Block memory address %d (%b) invalid. Valid depth configured as 0 to %d",$time,addr_int,addr_int,c_depth-1); + end + else if (wr_mode == 2'b01) begin + if (addr_int < c_depth) + for (ak = 0; ak < c_width; ak = ak + 1 ) + dout_int[ak] <= mem[(addr_int*c_width) + ak]; + else + //Warning Condition (Error occurs on rising edge of CLK): + //Write Mode Port is "Read First" and EN = 1 and SINIT = 0 and WE = 1 and ADDR out of the valid range + $display("Invalid Address Warning #2: Warning in %m at time %t: Block memory address %d (%b) invalid. Valid depth configured as 0 to %d",$time,addr_int,addr_int,c_depth-1); + end + else begin + if (addr_int < c_depth) + dout_int <= dout_int ; + else + //Warning Condition (Error occurs on rising edge of CLK): + //Write Mode Port is "No Change" and EN = 1 and SINIT = 0 and WE = 1 and ADDR out of the valid range + $display("Invalid Address Warning #3: Warning in %m at time %t: Block memory address %d (%b) invalid. Valid depth configured as 0 to %d",$time,addr_int,addr_int,c_depth-1); + end + end + //The following ELSE block assigns the output for a read operation + else begin + if (addr_int < c_depth) + for ( al = 0; al < c_width; al = al + 1) + dout_int[al] <= mem[(addr_int*c_width) + al]; + else + //Warning Condition (Error occurs on rising edge of CLK): + //EN = 1 and SINIT = 0 and WE = 0 and ADDRA out of the valid range + $display("Invalid Address Warning #4: Warning in %m at time %t: Block memory address %d (%b) invalid. Valid depth configured as 0 to %d",$time,addr_int,addr_int,c_depth-1); + end + end + end + end + + +// Write to memory contents + /*************************************************************************************** + *The following always block assigns the DIN bus to the memory during a write operation + ***************************************************************************************/ + always @(posedge clk_int) begin + if (en_int == 1'b1 && we_int == 1'b1) begin + if (addr_int < c_depth) + for (am = 0; am < c_width; am = am + 1 ) + mem [(addr_int*c_width) + am] <= di_int[am] ; + else + //Warning Condition (Error occurs on rising edge of CLK): + //EN = 1 and WE = 1 and ADDR out of the valid range + $display("Invalid Address Warning #5: Warning in %m at time %t: Block memory address %d (%b) invalid. Valid depth configured as 0 to %d",$time,addr_int,addr_int,c_depth-1); + end + end + +// output pipelines + + always @(posedge clk_int) begin + if (en_int == 1'b1 && c_pipe_stages > 0) + begin + for (i = c_pipe_stages; i >= 1; i = i -1 ) + begin + if (ssr_int == 1'b1 && en_int == 1'b1) + begin + pipeline[i] <= sinit_value ; + sub_rdy[i] <= 0 ; + end + else + begin + if (i==1) + begin + pipeline[1] <= dout_int; + sub_rdy[1] <= new_data_q; + end + else + begin + pipeline[i] <= pipeline[i-1] ; + sub_rdy[i] <= sub_rdy[i-1] ; + end + end + end + end + end + +// Select pipelined data output or no-pipelined data output + + always @( pipeline[c_pipe_stages] or dout_int or new_data_q or sub_rdy[c_pipe_stages]) begin + if (c_pipe_stages == 0 ) + begin + pipe_out = dout_int ; + rdy_int = new_data_q ; + end + else + begin + pipe_out = pipeline[c_pipe_stages]; + rdy_int = sub_rdy[c_pipe_stages]; + end + end + + + // specify +// (CLK *> DOUT) = (1, 1); +// endspecify + +endmodule + +`endcelldefine diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/BLKMEMSP_V5_0.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/BLKMEMSP_V5_0.v new file mode 100644 index 0000000..d93159a --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/BLKMEMSP_V5_0.v @@ -0,0 +1,488 @@ +/***************************************************************************** + * $RCSfile: BLKMEMSP_V5_0.v,v $$Date: 2008/09/08 20:06:36 $ + ***************************************************************************** + * Block Memory Compiler - Verilog Behavioral Model + ***************************************************************************** + * + * This File is owned and controlled by Xilinx and must be used solely + * for design, simulation, implementation and creation of design files + * limited to Xilinx devices or technologies. Use with non-Xilinx + * devices or technologies is expressly prohibited and immediately + * terminates your license. + * + * Xilinx products are not intended for use in life support + * appliances, devices, or systems. Use in such applications is + * expressly prohibited. + * + * **************************** + * ** Copyright Xilinx, Inc. ** + * ** All rights reserved. ** + * **************************** + * + ************************************************************************* + * Filename: BLKMEMSP_V5_0.v + * + * Decsription: Single Port V2 BRAM behavioral model. Extendable depth/width. + * The behavior for EN = `X`, WE = `X`, and for CLK transitions to + * or from `X` is not considered. + * + **************************************************************************/ +`timescale 1ns/10ps + +`celldefine + + +`define c_sp_rom 0 +`define c_sp_ram 1 +`define c_write_first 0 +`define c_read_first 1 +`define c_no_change 2 + +module BLKMEMSP_V5_0(DOUT, ADDR, DIN, EN, CLK, WE, SINIT, ND, RFD, RDY); + + parameter c_addr_width = 9 ; // controls address width of memory + parameter c_default_data = "0"; // indicates string of hex characters used to initialize memory + parameter c_depth = 512 ; // controls depth of memory + parameter c_enable_rlocs = 0 ; // core includes placement constraints + parameter c_has_default_data = 1; // initializes contents of memory to c_default_data + parameter c_has_din = 1 ; // indicates memory has data input pins + parameter c_has_en = 1 ; // indicates memory has a EN pin + parameter c_has_limit_data_pitch = 0 ; // + parameter c_has_nd = 0 ; // Memory has a new data pin + parameter c_has_rdy = 0 ; // Memory has result ready pin + parameter c_has_rfd = 0 ; // Memory has ready for data pin + parameter c_has_sinit = 1 ; // indicates memory has a SINIT pin + parameter c_has_we = 1 ; // indicates memory has a WE pin + parameter c_limit_data_pitch = 18; + parameter c_mem_init_file = "null.mif"; // controls which .mif file used to initialize memory + parameter c_pipe_stages = 1 ; // indicates the number of pipe stages needed in port A + parameter c_reg_inputs = 0 ; // indicates WE, ADDR, and DIN are registered + parameter c_sinit_value = "0000"; // indicates string of hex used to initialize output registers + parameter c_width = 32 ; // controls data width of memory + parameter c_write_mode = 2; // controls which write modes shall be used + + parameter c_ybottom_addr = "1024"; + parameter c_yclk_is_rising = 1; + parameter c_yen_is_high = 1; + parameter c_yhierarchy = "hierarchy1"; + parameter c_ymake_bmm = 1; + parameter c_yprimitive_type = "4kx4"; + parameter c_ysinit_is_high = 1; + parameter c_ytop_addr = "0"; + parameter c_yuse_single_primitive = 0; + parameter c_ywe_is_high = 1; + +// IO ports + + + output [c_width-1:0] DOUT; + input [c_addr_width-1:0] ADDR; + input [c_width-1:0] DIN; + input EN, CLK, WE, SINIT, ND; + output RFD, RDY; + + reg RFD ; + reg RDY ; + + reg [c_width-1:0] dout_int; // output of RAM + reg [c_width-1:0] pipe_out ; // output of pipeline stage + wire [c_width-1:0] DOUT = pipe_out ; + reg [c_width-1:0] mem [0:c_depth-1]; + reg [24:0] count; + reg [1:0] wr_mode; + + wire [c_addr_width-1:0] addr_i = ADDR; + reg [c_addr_width-1:0] addr_int ; + reg [c_width-1:0] di_int ; + wire [c_width-1:0] di_i ; + wire clk_int ; + wire en_int ; + reg we_int ; + wire we_i ; + reg we_q ; + wire ssr_int ; + wire nd_int ; + wire nd_i ; + reg rfd_int ; + reg rdy_int ; + reg nd_q ; + reg [c_width-1:0] di_q ; + reg [c_addr_width-1:0] addr_q; + reg new_data ; + reg new_data_q ; // to track the synchronous PORT RAM output + + reg [c_width-1:0] default_data ; + reg [c_width-1:0] ram_temp [0:c_depth-1]; + reg [c_width-1:0] bitval; + reg [c_width-1:0] sinit_value; + + reg [(c_width-1) : 0] pipeline [0 : c_pipe_stages]; + reg sub_rdy[0 : c_pipe_stages]; + reg [10:0] ci, cj ; + reg [10:0] dmi, dmj, dni, dnj, doi, doj ; + integer i, j, k, l, m; + integer ai, aj, ak, al, am, an, ap ; + + +// Generate input control signals +// Combinational + +// Take care of ROM/RAM functionality + + assign clk_int = defval(CLK, 1, 1, c_yclk_is_rising); + assign we_i = defval(WE, c_has_we, 0, c_ywe_is_high); + assign di_i = (c_has_din == 1)?DIN:'b0; + assign en_int = defval(EN, c_has_en, 1, c_yen_is_high); + assign ssr_int = defval(SINIT , c_has_sinit , 0, c_ysinit_is_high); + assign nd_i = defval (ND, c_has_nd, 1, 1); + + +// tri0 GSR = glbl.GSR; + + function defval; + input i; + input hassig; + input val; + input active_high; + begin + if(hassig == 1) + begin + if (active_high == 1) + defval = i; + else + defval = ~i; + end + else + defval = val; + end + endfunction + + function max; + input a; + input b; + begin + max = (a > b) ? a : b; + end + endfunction + + function a_is_X; + input [c_width-1 : 0] i; + integer j ; + begin + a_is_X = 1'b0; + for(j = 0; j < c_width; j = j + 1) + begin + if(i[j] === 1'bx) + a_is_X = 1'b1; + end // loop + end + endfunction + + + function [c_width-1:0] hexstr_conv; + input [(c_width*8)-1:0] def_data; + + integer index,i,j; + reg [3:0] bin; + + begin + index = 0; + hexstr_conv = 'b0; + for( i=c_width-1; i>=0; i=i-1 ) + begin + case (def_data[7:0]) + 8'b00000000 : + begin + bin = 4'b0000; + i = -1; + end + 8'b00110000 : bin = 4'b0000; + 8'b00110001 : bin = 4'b0001; + 8'b00110010 : bin = 4'b0010; + 8'b00110011 : bin = 4'b0011; + 8'b00110100 : bin = 4'b0100; + 8'b00110101 : bin = 4'b0101; + 8'b00110110 : bin = 4'b0110; + 8'b00110111 : bin = 4'b0111; + 8'b00111000 : bin = 4'b1000; + 8'b00111001 : bin = 4'b1001; + 8'b01000001 : bin = 4'b1010; + 8'b01000010 : bin = 4'b1011; + 8'b01000011 : bin = 4'b1100; + 8'b01000100 : bin = 4'b1101; + 8'b01000101 : bin = 4'b1110; + 8'b01000110 : bin = 4'b1111; + 8'b01100001 : bin = 4'b1010; + 8'b01100010 : bin = 4'b1011; + 8'b01100011 : bin = 4'b1100; + 8'b01100100 : bin = 4'b1101; + 8'b01100101 : bin = 4'b1110; + 8'b01100110 : bin = 4'b1111; + default : + begin + $display("ERROR in %m at time %t : NOT A HEX CHARACTER",$time); + bin = 4'bx; + end + endcase + for( j=0; j<4; j=j+1) + begin + if ((index*4)+j < c_width) + begin + hexstr_conv[(index*4)+j] = bin[j]; + end + end + index = index + 1; + def_data = def_data >> 8; + end + end + endfunction + + initial begin + sinit_value = 'b0 ; + default_data = hexstr_conv(c_default_data); + if (c_has_sinit == 1 ) + sinit_value = hexstr_conv(c_sinit_value); + for(i = 0; i < c_depth; i = i + 1) + mem[i] = default_data; + if (c_has_default_data == 0) + $readmemb(c_mem_init_file, mem); + for (k = 0; k <= c_pipe_stages; k = k + 1) + pipeline[k] = sinit_value ; + for (m = 0; m <= c_pipe_stages; m = m + 1) + sub_rdy[m] = 0 ; + dout_int = sinit_value ; + nd_q = 0 ; + new_data_q = 0 ; + di_q = 0 ; + addr_q = 0 ; + we_q = 0 ; + #1 pipe_out = sinit_value; + end + +// Generate output control signals RFD and RDY +// Combinational + + always @ ( rfd_int) + begin + if (c_has_rfd == 1) + RFD = rfd_int ; + else + RFD = 1'b0 ; + end + + always @ (en_int ) + begin + if (en_int == 1'b1) + rfd_int = 1'b1 ; + else + rfd_int = 1'b0 ; + end + + always @ ( rdy_int ) + begin + if ((c_has_rdy == 1) && (c_has_nd == 1) && (c_has_rfd == 1) ) + RDY = rdy_int ; + else + RDY = 1'b0 ; + end + + assign nd_int = en_int && nd_i ; // only pass nd through if en is 1 + +// Register hanshaking inputs + + always @(posedge clk_int ) + begin + if (en_int == 1'b1) + begin + if (ssr_int == 1'b1) + nd_q <= 1'b0 ; + else + nd_q <= nd_int; + end + else + nd_q <= nd_q ; + end +// Register data / address / data inputs + + always @(posedge clk_int ) + begin + if (en_int == 1'b1) + begin + di_q <= di_i ; + addr_q <= addr_i ; + we_q <= we_i ; + end + end + +// select registered or non-registered write enable + + always @( we_i or we_q) + begin + if (c_reg_inputs == 1 ) + we_int = we_q ; + else + we_int = we_i ; + end + +// select registered data/address/nd inputs + + always @( di_i or di_q) + begin + if ( c_reg_inputs == 1) + di_int = di_q ; + else + di_int = di_i ; + end + + always @( addr_i or addr_q or nd_q or nd_int ) + begin + if (c_reg_inputs == 1) + begin + addr_int = addr_q; + new_data = nd_q ; + end + else + begin + addr_int = addr_i ; + new_data = nd_int ; + end + end + +// Register the new_data signal to track the synchronous RAM output + + always @(posedge clk_int) + begin + if ( en_int == 1'b1 ) + begin + if (ssr_int == 1'b1) + new_data_q <= 0 ; + else + new_data_q <= new_data ; + end + end + + initial begin + case (c_write_mode) + `c_write_first : wr_mode <= 2'b00; + `c_read_first : wr_mode <= 2'b01; + `c_no_change : wr_mode <= 2'b10; + default : begin + $display("Error in %m at time %t: c_write_mode = %s is not WRITE_FIRST, READ_FIRST or NO_CHANGE.",$time , c_write_mode); + $finish; + end + endcase + end + + + /*************************************************************** + *The following always block assigns the value for the DOUT bus + ***************************************************************/ + always @(posedge clk_int) begin + if (en_int == 1'b1) begin + if (ssr_int == 1'b1) begin + dout_int <= sinit_value; + end + else begin + //The following IF block assigns the output for a write operation + if (we_int == 1'b1) begin + if (wr_mode == 2'b00) begin + if (addr_int < c_depth) + dout_int <= di_int; + else + //Warning Condition (Error occurs on rising edge of CLK): + //Write Mode Port is "Write First" and EN = 1 and SINIT = 0 and WE = 1 and ADDR out of the valid range + $display("Invalid Address Warning #1: Warning in %m at time %t: Block memory address %d (%b) invalid. Valid depth configured as 0 to %d",$time,addr_int,addr_int,c_depth-1); + end + else if (wr_mode == 2'b01) begin + if (addr_int < c_depth) + dout_int <= mem[addr_int]; + else + //Warning Condition (Error occurs on rising edge of CLK): + //Write Mode Port is "Read First" and EN = 1 and SINIT = 0 and WE = 1 and ADDR out of the valid range + $display("Invalid Address Warning #2: Warning in %m at time %t: Block memory address %d (%b) invalid. Valid depth configured as 0 to %d",$time,addr_int,addr_int,c_depth-1); + end + else begin + if (addr_int < c_depth) + dout_int <= dout_int ; + else + //Warning Condition (Error occurs on rising edge of CLK): + //Write Mode Port is "No Change" and EN = 1 and SINIT = 0 and WE = 1 and ADDR out of the valid range + $display("Invalid Address Warning #3: Warning in %m at time %t: Block memory address %d (%b) invalid. Valid depth configured as 0 to %d",$time,addr_int,addr_int,c_depth-1); + end + end + //The following ELSE block assigns the output for a read operation + else begin + if (addr_int < c_depth) + dout_int <= mem[addr_int]; + else + //Warning Condition (Error occurs on rising edge of CLK): + //EN = 1 and SINIT = 0 and WE = 0 and ADDRA out of the valid range + $display("Invalid Address Warning #4: Warning in %m at time %t: Block memory address %d (%b) invalid. Valid depth configured as 0 to %d",$time,addr_int,addr_int,c_depth-1); + end + end + end + end + + +// Write to memory contents + /*************************************************************************************** + *The following always block assigns the DIN bus to the memory during a write operation + ***************************************************************************************/ + always @(posedge clk_int) begin + if (en_int == 1'b1 && we_int == 1'b1) begin + if (addr_int < c_depth) + mem [addr_int] <= di_int ; + else + //Warning Condition (Error occurs on rising edge of CLK): + //EN = 1 and WE = 1 and ADDR out of the valid range + $display("Invalid Address Warning #5: Warning in %m at time %t: Block memory address %d (%b) invalid. Valid depth configured as 0 to %d",$time,addr_int,addr_int,c_depth-1); + end + end + +// output pipelines + + always @(posedge clk_int) begin + if (en_int == 1'b1 && c_pipe_stages > 0) + begin + for (i = c_pipe_stages; i >= 1; i = i -1 ) + begin + if (ssr_int == 1'b1 && en_int == 1'b1) + begin + pipeline[i] <= sinit_value ; + sub_rdy[i] <= 0 ; + end + else + begin + if (i==1) + begin + pipeline[i] <= dout_int; + sub_rdy[i] <= new_data_q; + end + else + begin + pipeline[i] <= pipeline[i-1] ; + sub_rdy[i] <= sub_rdy[i-1] ; + end + end + end + end + end + +// Select pipelined data output or no-pipelined data output + + always @( pipeline[c_pipe_stages] or sub_rdy[c_pipe_stages] or new_data_q or dout_int) begin + if (c_pipe_stages == 0 ) + begin + pipe_out = dout_int ; + rdy_int = new_data_q ; + end + else + begin + rdy_int = sub_rdy[c_pipe_stages]; + pipe_out = pipeline[c_pipe_stages]; + end + end + +endmodule + +`endcelldefine diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/BLKMEMSP_V6_0.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/BLKMEMSP_V6_0.v new file mode 100644 index 0000000..b72bb53 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/BLKMEMSP_V6_0.v @@ -0,0 +1,542 @@ +// Copyright(C) 2003 by Xilinx, Inc. All rights reserved. +// This text/file contains proprietary, confidential +// information of Xilinx, Inc., is distributed under license +// from Xilinx, Inc., and may be used, copied and/or +// disclosed only pursuant to the terms of a valid license +// agreement with Xilinx, Inc. Xilinx hereby grants you +// a license to use this text/file solely for design, simulation, +// implementation and creation of design files limited +// to Xilinx devices or technologies. Use with non-Xilinx +// devices or technologies is expressly prohibited and +// immediately terminates your license unless covered by +// a separate agreement. +// +// Xilinx is providing this design, code, or information +// "as is" solely for use in developing programs and +// solutions for Xilinx devices. By providing this design, +// code, or information as one possible implementation of +// this feature, application or standard, Xilinx is making no +// representation that this implementation is free from any +// claims of infringement. You are responsible for +// obtaining any rights you may require for your implementation. +// Xilinx expressly disclaims any warranty whatsoever with +// respect to the adequacy of the implementation, including +// but not limited to any warranties or representations that this +// implementation is free from claims of infringement, implied +// warranties of merchantability or fitness for a particular +// purpose. +// +// Xilinx products are not intended for use in life support +// appliances, devices, or systems. Use in such applications are +// expressly prohibited. +// +// This copyright and support notice must be retained as part +// of this text at all times. (c) Copyright 1995-2003 Xilinx, Inc. +// All rights reserved. + +/***************************************************************************** + * $RCSfile: BLKMEMSP_V6_0.v,v $$Date: 2008/09/08 20:06:40 $ + ***************************************************************************** + * Block Memory Compiler - Verilog Behavioral Model + ***************************************************************************** + * + * + ************************************************************************* + * Filename: BLKMEMSP_V6_0.v + * + * Decsription: Single Port V2 BRAM behavioral model. Extendable depth/width. + * The behavior for EN = `X`, WE = `X`, and for CLK transitions to + * or from `X` is not considered. + * + **************************************************************************/ +`timescale 1ns/10ps + +`celldefine + + +`define c_sp_rom 0 +`define c_sp_ram 1 +`define c_write_first 0 +`define c_read_first 1 +`define c_no_change 2 + +module BLKMEMSP_V6_0(DOUT, ADDR, DIN, EN, CLK, WE, SINIT, ND, RFD, RDY); + + parameter c_addr_width = 9 ; // controls address width of memory + parameter c_default_data = "0"; // indicates string of hex characters used to initialize memory + parameter c_depth = 512 ; // controls depth of memory + parameter c_enable_rlocs = 0 ; // core includes placement constraints + parameter c_has_default_data = 1; // initializes contents of memory to c_default_data + parameter c_has_din = 1 ; // indicates memory has data input pins + parameter c_has_en = 1 ; // indicates memory has a EN pin + parameter c_has_limit_data_pitch = 0 ; // + parameter c_has_nd = 0 ; // Memory has a new data pin + parameter c_has_rdy = 0 ; // Memory has result ready pin + parameter c_has_rfd = 0 ; // Memory has ready for data pin + parameter c_has_sinit = 1 ; // indicates memory has a SINIT pin + parameter c_has_we = 1 ; // indicates memory has a WE pin + parameter c_limit_data_pitch = 18; + parameter c_mem_init_file = "null.mif"; // controls which .mif file used to initialize memory + parameter c_pipe_stages = 1 ; // indicates the number of pipe stages needed in port A + parameter c_reg_inputs = 0 ; // indicates WE, ADDR, and DIN are registered + parameter c_sinit_value = "0000"; // indicates string of hex used to initialize output registers + parameter c_width = 32 ; // controls data width of memory + parameter c_write_mode = 2; // controls which write modes shall be used + + parameter c_ybottom_addr = "1024"; + parameter c_yclk_is_rising = 1; + parameter c_yen_is_high = 1; + parameter c_yhierarchy = "hierarchy1"; + parameter c_ymake_bmm = 1; + parameter c_yprimitive_type = "4kx4"; + parameter c_ysinit_is_high = 1; + parameter c_ytop_addr = "0"; + parameter c_yuse_single_primitive = 0; + parameter c_ywe_is_high = 1; + parameter c_yydisable_warnings = 0; + + +// IO ports + + + output [c_width-1:0] DOUT; + input [c_addr_width-1:0] ADDR; + input [c_width-1:0] DIN; + input EN, CLK, WE, SINIT, ND; + output RFD, RDY; + + reg RFD ; + reg RDY ; + + reg [c_width-1:0] dout_int; // output of RAM + reg [c_width-1:0] pipe_out ; // output of pipeline stage + wire [c_width-1:0] DOUT = pipe_out ; + reg [c_width-1:0] mem [0:c_depth-1]; + reg [24:0] count; + reg [1:0] wr_mode; + + wire [c_addr_width-1:0] addr_i = ADDR; + reg [c_addr_width-1:0] addr_int ; + reg [c_width-1:0] di_int ; + wire [c_width-1:0] di_i ; + wire clk_int ; + wire en_int ; + reg we_int ; + wire we_i ; + reg we_q ; + wire ssr_int ; + wire nd_int ; + wire nd_i ; + reg rfd_int ; + reg rdy_int ; + reg nd_q ; + reg [c_width-1:0] di_q ; + reg [c_addr_width-1:0] addr_q; + reg new_data ; + reg new_data_q ; // to track the synchronous PORT RAM output + + reg [c_width-1:0] default_data ; + reg [c_width-1:0] ram_temp [0:c_depth-1]; + reg [c_width-1:0] bitval; + reg [c_width-1:0] sinit_value; + + reg [(c_width-1) : 0] pipeline [0 : c_pipe_stages]; + reg sub_rdy[0 : c_pipe_stages]; + reg [10:0] ci, cj ; + reg [10:0] dmi, dmj, dni, dnj, doi, doj ; + integer i, j, k, l, m; + integer ai, aj, ak, al, am, an, ap ; + + +// Generate input control signals +// Combinational + +// Take care of ROM/RAM functionality + + assign clk_int = defval(CLK, 1, 1, c_yclk_is_rising); + assign we_i = defval(WE, c_has_we, 0, c_ywe_is_high); + assign di_i = (c_has_din == 1)?DIN:'b0; + assign en_int = defval(EN, c_has_en, 1, c_yen_is_high); + assign ssr_int = defval(SINIT , c_has_sinit , 0, c_ysinit_is_high); + assign nd_i = defval (ND, c_has_nd, 1, 1); + + +// tri0 GSR = glbl.GSR; + + function defval; + input i; + input hassig; + input val; + input active_high; + begin + if(hassig == 1) + begin + if (active_high == 1) + defval = i; + else + defval = ~i; + end + else + defval = val; + end + endfunction + + function max; + input a; + input b; + begin + max = (a > b) ? a : b; + end + endfunction + + function a_is_X; + input [c_width-1 : 0] i; + integer j ; + begin + a_is_X = 1'b0; + for(j = 0; j < c_width; j = j + 1) + begin + if(i[j] === 1'bx) + a_is_X = 1'b1; + end // loop + end + endfunction + + + function [c_width-1:0] hexstr_conv; + input [(c_width*8)-1:0] def_data; + + integer index,i,j; + reg [3:0] bin; + + begin + index = 0; + hexstr_conv = 'b0; + for( i=c_width-1; i>=0; i=i-1 ) + begin + case (def_data[7:0]) + 8'b00000000 : + begin + bin = 4'b0000; + i = -1; + end + 8'b00110000 : bin = 4'b0000; + 8'b00110001 : bin = 4'b0001; + 8'b00110010 : bin = 4'b0010; + 8'b00110011 : bin = 4'b0011; + 8'b00110100 : bin = 4'b0100; + 8'b00110101 : bin = 4'b0101; + 8'b00110110 : bin = 4'b0110; + 8'b00110111 : bin = 4'b0111; + 8'b00111000 : bin = 4'b1000; + 8'b00111001 : bin = 4'b1001; + 8'b01000001 : bin = 4'b1010; + 8'b01000010 : bin = 4'b1011; + 8'b01000011 : bin = 4'b1100; + 8'b01000100 : bin = 4'b1101; + 8'b01000101 : bin = 4'b1110; + 8'b01000110 : bin = 4'b1111; + 8'b01100001 : bin = 4'b1010; + 8'b01100010 : bin = 4'b1011; + 8'b01100011 : bin = 4'b1100; + 8'b01100100 : bin = 4'b1101; + 8'b01100101 : bin = 4'b1110; + 8'b01100110 : bin = 4'b1111; + default : + begin + if (c_yydisable_warnings == 0) begin + $display("ERROR in %m at time %t : NOT A HEX CHARACTER",$time); + end + bin = 4'bx; + end + endcase + for( j=0; j<4; j=j+1) + begin + if ((index*4)+j < c_width) + begin + hexstr_conv[(index*4)+j] = bin[j]; + end + end + index = index + 1; + def_data = def_data >> 8; + end + end + endfunction + + initial begin + sinit_value = 'b0 ; + default_data = hexstr_conv(c_default_data); + if (c_has_sinit == 1 ) + sinit_value = hexstr_conv(c_sinit_value); + for(i = 0; i < c_depth; i = i + 1) + mem[i] = default_data; + if (c_has_default_data == 0) + $readmemb(c_mem_init_file, mem); + for (k = 0; k <= c_pipe_stages; k = k + 1) + pipeline[k] = sinit_value ; + for (m = 0; m <= c_pipe_stages; m = m + 1) + sub_rdy[m] = 0 ; + dout_int = sinit_value ; + nd_q = 0 ; + new_data_q = 0 ; + di_q = 0 ; + addr_q = 0 ; + we_q = 0 ; + #1 pipe_out = sinit_value; + end + +// Generate output control signals RFD and RDY +// Combinational + + always @ ( rfd_int) + begin + if (c_has_rfd == 1) + RFD = rfd_int ; + else + RFD = 1'b0 ; + end + + always @ (en_int ) + begin + if (en_int == 1'b1) + rfd_int = 1'b1 ; + else + rfd_int = 1'b0 ; + end + + always @ ( rdy_int ) + begin + if ((c_has_rdy == 1) && (c_has_nd == 1) && (c_has_rfd == 1) ) + RDY = rdy_int ; + else + RDY = 1'b0 ; + end + + assign nd_int = en_int && nd_i ; // only pass nd through if en is 1 + +// Register hanshaking inputs + + always @(posedge clk_int ) + begin + if (en_int == 1'b1) + begin + if (ssr_int == 1'b1) + nd_q <= 1'b0 ; + else + nd_q <= nd_int; + end + else + nd_q <= nd_q ; + end +// Register data / address / data inputs + + always @(posedge clk_int ) + begin + if (en_int == 1'b1) + begin + di_q <= di_i ; + addr_q <= addr_i ; + we_q <= we_i ; + end + end + +// select registered or non-registered write enable + + always @( we_i or we_q) + begin + if (c_reg_inputs == 1 ) + we_int = we_q ; + else + we_int = we_i ; + end + +// select registered data/address/nd inputs + + always @( di_i or di_q) + begin + if ( c_reg_inputs == 1) + di_int = di_q ; + else + di_int = di_i ; + end + + always @( addr_i or addr_q or nd_q or nd_int or we_q or we_i) + begin + if (c_reg_inputs == 1) + begin + addr_int = addr_q; + if ((we_q == 1'b1) && (c_write_mode == 2)) + new_data = 1'b0 ; + else + new_data = nd_q ; + end + else + begin + addr_int = addr_i ; + if ((we_i == 1'b1) && (c_write_mode == 2)) + new_data = 1'b0 ; + else + new_data = nd_int ; + end + end + +// Register the new_data signal to track the synchronous RAM output + + always @(posedge clk_int) + begin + if ( en_int == 1'b1 ) + begin + if (ssr_int == 1'b1) + new_data_q <= 0 ; + else + new_data_q <= new_data ; + end + end + + initial begin + case (c_write_mode) + `c_write_first : wr_mode <= 2'b00; + `c_read_first : wr_mode <= 2'b01; + `c_no_change : wr_mode <= 2'b10; + default : begin + if (c_yydisable_warnings == 0) begin + $display("Error in %m at time %t: c_write_mode = %s is not WRITE_FIRST, READ_FIRST or NO_CHANGE.",$time , c_write_mode); + end + $finish; + end + endcase + end + + + /*************************************************************** + *The following always block assigns the value for the DOUT bus + ***************************************************************/ + always @(posedge clk_int) begin + if (en_int == 1'b1) begin + if (ssr_int == 1'b1) begin + dout_int <= sinit_value; + end + else begin + //The following IF block assigns the output for a write operation + if (we_int == 1'b1) begin + if (wr_mode == 2'b00) begin + if (addr_int < c_depth) + dout_int <= di_int; + else + //Warning Condition (Error occurs on rising edge of CLK): + //Write Mode Port is "Write First" and EN = 1 and SINIT = 0 and WE = 1 and ADDR out of the valid range + if (c_yydisable_warnings == 0) begin + $display("Invalid Address Warning #1: Warning in %m at time %t: Block memory address %d (%b) invalid. Valid depth configured as 0 to %d",$time,addr_int,addr_int,c_depth-1); + end + end + else if (wr_mode == 2'b01) begin + if (addr_int < c_depth) + dout_int <= mem[addr_int]; + else + //Warning Condition (Error occurs on rising edge of CLK): + //Write Mode Port is "Read First" and EN = 1 and SINIT = 0 and WE = 1 and ADDR out of the valid range + if (c_yydisable_warnings == 0) begin + $display("Invalid Address Warning #2: Warning in %m at time %t: Block memory address %d (%b) invalid. Valid depth configured as 0 to %d",$time,addr_int,addr_int,c_depth-1); + end + end + else begin + if (addr_int < c_depth) + dout_int <= dout_int ; + else + //Warning Condition (Error occurs on rising edge of CLK): + //Write Mode Port is "No Change" and EN = 1 and SINIT = 0 and WE = 1 and ADDR out of the valid range + if (c_yydisable_warnings == 0) begin + $display("Invalid Address Warning #3: Warning in %m at time %t: Block memory address %d (%b) invalid. Valid depth configured as 0 to %d",$time,addr_int,addr_int,c_depth-1); + end + end + end + //The following ELSE block assigns the output for a read operation + else begin + if (addr_int < c_depth) + dout_int <= mem[addr_int]; + else + //Warning Condition (Error occurs on rising edge of CLK): + //EN = 1 and SINIT = 0 and WE = 0 and ADDRA out of the valid range + if (c_yydisable_warnings == 0) begin + $display("Invalid Address Warning #4: Warning in %m at time %t: Block memory address %d (%b) invalid. Valid depth configured as 0 to %d",$time,addr_int,addr_int,c_depth-1); + end + end + end + end + end + + +// Write to memory contents + /*************************************************************************************** + *The following always block assigns the DIN bus to the memory during a write operation + ***************************************************************************************/ + always @(posedge clk_int) begin + if (en_int == 1'b1 && we_int == 1'b1) begin + if (addr_int < c_depth) + mem [addr_int] <= di_int ; + else + //Warning Condition (Error occurs on rising edge of CLK): + //EN = 1 and WE = 1 and ADDR out of the valid range + if (c_yydisable_warnings == 0) begin + $display("Invalid Address Warning #5: Warning in %m at time %t: Block memory address %d (%b) invalid. Valid depth configured as 0 to %d",$time,addr_int,addr_int,c_depth-1); + end + end + end + +// output pipelines + + always @(posedge clk_int) begin + if (en_int == 1'b1 && c_pipe_stages > 0) + begin + for (i = c_pipe_stages; i >= 1; i = i -1 ) + begin + if (ssr_int == 1'b1 && en_int == 1'b1) + begin + pipeline[i] <= sinit_value ; + sub_rdy[i] <= 0 ; + end + else + begin + // Do not update output register if no_change on write and + // WE = 1 + if (!(c_write_mode == 2 && we_int == 1)) begin + if (i==1) + begin + pipeline[i] <= dout_int; + end + else + begin + pipeline[i] <= pipeline[i-1] ; + end + end // if (!(c_write_mode == 2 && we_int == 1)) + if (i==1) + begin + sub_rdy[i] <= new_data_q; + end + else + begin + sub_rdy[i] <= sub_rdy[i-1] ; + end + end + end + end + end + +// Select pipelined data output or no-pipelined data output + + always @( pipeline[c_pipe_stages] or sub_rdy[c_pipe_stages] or new_data_q or dout_int) begin + if (c_pipe_stages == 0 ) + begin + pipe_out = dout_int ; + rdy_int = new_data_q ; + end + else + begin + rdy_int = sub_rdy[c_pipe_stages]; + pipe_out = pipeline[c_pipe_stages]; + end + end + +endmodule + +`endcelldefine diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/BLKMEMSP_V6_2.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/BLKMEMSP_V6_2.v new file mode 100644 index 0000000..532e8e3 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/BLKMEMSP_V6_2.v @@ -0,0 +1,542 @@ +// Copyright(C) 2004 by Xilinx, Inc. All rights reserved. +// This text/file contains proprietary, confidential +// information of Xilinx, Inc., is distributed under license +// from Xilinx, Inc., and may be used, copied and/or +// disclosed only pursuant to the terms of a valid license +// agreement with Xilinx, Inc. Xilinx hereby grants you +// a license to use this text/file solely for design, simulation, +// implementation and creation of design files limited +// to Xilinx devices or technologies. Use with non-Xilinx +// devices or technologies is expressly prohibited and +// immediately terminates your license unless covered by +// a separate agreement. +// +// Xilinx is providing this design, code, or information +// "as is" solely for use in developing programs and +// solutions for Xilinx devices. By providing this design, +// code, or information as one possible implementation of +// this feature, application or standard, Xilinx is making no +// representation that this implementation is free from any +// claims of infringement. You are responsible for +// obtaining any rights you may require for your implementation. +// Xilinx expressly disclaims any warranty whatsoever with +// respect to the adequacy of the implementation, including +// but not limited to any warranties or representations that this +// implementation is free from claims of infringement, implied +// warranties of merchantability or fitness for a particular +// purpose. +// +// Xilinx products are not intended for use in life support +// appliances, devices, or systems. Use in such applications are +// expressly prohibited. +// +// This copyright and support notice must be retained as part +// of this text at all times. (c) Copyright 1995-2004 Xilinx, Inc. +// All rights reserved. + +/***************************************************************************** + * $RCSfile: BLKMEMSP_V6_2.v,v $ + ***************************************************************************** + * Block Memory Compiler - Verilog Behavioral Model + ***************************************************************************** + * + * + ************************************************************************* + * Filename: BLKMEMSP_V6_2.v + * + * Decsription: Single Port V2 BRAM behavioral model. Extendable depth/width. + * The behavior for EN = `X`, WE = `X`, and for CLK transitions to + * or from `X` is not considered. + * + **************************************************************************/ +`timescale 1ns/10ps + +`celldefine + + +`define c_sp_rom 0 +`define c_sp_ram 1 +`define c_write_first 0 +`define c_read_first 1 +`define c_no_change 2 + +module BLKMEMSP_V6_2(DOUT, ADDR, DIN, EN, CLK, WE, SINIT, ND, RFD, RDY); + + parameter c_addr_width = 9 ; // controls address width of memory + parameter c_default_data = "0"; // indicates string of hex characters used to initialize memory + parameter c_depth = 512 ; // controls depth of memory + parameter c_enable_rlocs = 0 ; // core includes placement constraints + parameter c_has_default_data = 1; // initializes contents of memory to c_default_data + parameter c_has_din = 1 ; // indicates memory has data input pins + parameter c_has_en = 1 ; // indicates memory has a EN pin + parameter c_has_limit_data_pitch = 0 ; // + parameter c_has_nd = 0 ; // Memory has a new data pin + parameter c_has_rdy = 0 ; // Memory has result ready pin + parameter c_has_rfd = 0 ; // Memory has ready for data pin + parameter c_has_sinit = 1 ; // indicates memory has a SINIT pin + parameter c_has_we = 1 ; // indicates memory has a WE pin + parameter c_limit_data_pitch = 18; + parameter c_mem_init_file = "null.mif"; // controls which .mif file used to initialize memory + parameter c_pipe_stages = 1 ; // indicates the number of pipe stages needed in port A + parameter c_reg_inputs = 0 ; // indicates WE, ADDR, and DIN are registered + parameter c_sinit_value = "0000"; // indicates string of hex used to initialize output registers + parameter c_width = 32 ; // controls data width of memory + parameter c_write_mode = 2; // controls which write modes shall be used + + parameter c_ybottom_addr = "1024"; + parameter c_yclk_is_rising = 1; + parameter c_yen_is_high = 1; + parameter c_yhierarchy = "hierarchy1"; + parameter c_ymake_bmm = 1; + parameter c_yprimitive_type = "4kx4"; + parameter c_ysinit_is_high = 1; + parameter c_ytop_addr = "0"; + parameter c_yuse_single_primitive = 0; + parameter c_ywe_is_high = 1; + parameter c_yydisable_warnings = 0; + + +// IO ports + + + output [c_width-1:0] DOUT; + input [c_addr_width-1:0] ADDR; + input [c_width-1:0] DIN; + input EN, CLK, WE, SINIT, ND; + output RFD, RDY; + + reg RFD ; + reg RDY ; + + reg [c_width-1:0] dout_int; // output of RAM + reg [c_width-1:0] pipe_out ; // output of pipeline stage + wire [c_width-1:0] DOUT = pipe_out ; + reg [c_width-1:0] mem [0:c_depth-1]; + reg [24:0] count; + reg [1:0] wr_mode; + + wire [c_addr_width-1:0] addr_i = ADDR; + reg [c_addr_width-1:0] addr_int ; + reg [c_width-1:0] di_int ; + wire [c_width-1:0] di_i ; + wire clk_int ; + wire en_int ; + reg we_int ; + wire we_i ; + reg we_q ; + wire ssr_int ; + wire nd_int ; + wire nd_i ; + reg rfd_int ; + reg rdy_int ; + reg nd_q ; + reg [c_width-1:0] di_q ; + reg [c_addr_width-1:0] addr_q; + reg new_data ; + reg new_data_q ; // to track the synchronous PORT RAM output + + reg [c_width-1:0] default_data ; + reg [c_width-1:0] ram_temp [0:c_depth-1]; + reg [c_width-1:0] bitval; + reg [c_width-1:0] sinit_value; + + reg [(c_width-1) : 0] pipeline [0 : c_pipe_stages]; + reg sub_rdy[0 : c_pipe_stages]; + reg [10:0] ci, cj ; + reg [10:0] dmi, dmj, dni, dnj, doi, doj ; + integer i, j, k, l, m; + integer ai, aj, ak, al, am, an, ap ; + + +// Generate input control signals +// Combinational + +// Take care of ROM/RAM functionality + + assign clk_int = defval(CLK, 1, 1, c_yclk_is_rising); + assign we_i = defval(WE, c_has_we, 0, c_ywe_is_high); + assign di_i = (c_has_din == 1)?DIN:'b0; + assign en_int = defval(EN, c_has_en, 1, c_yen_is_high); + assign ssr_int = defval(SINIT , c_has_sinit , 0, c_ysinit_is_high); + assign nd_i = defval (ND, c_has_nd, 1, 1); + + +// tri0 GSR = glbl.GSR; + + function defval; + input i; + input hassig; + input val; + input active_high; + begin + if(hassig == 1) + begin + if (active_high == 1) + defval = i; + else + defval = ~i; + end + else + defval = val; + end + endfunction + + function max; + input a; + input b; + begin + max = (a > b) ? a : b; + end + endfunction + + function a_is_X; + input [c_width-1 : 0] i; + integer j ; + begin + a_is_X = 1'b0; + for(j = 0; j < c_width; j = j + 1) + begin + if(i[j] === 1'bx) + a_is_X = 1'b1; + end // loop + end + endfunction + + + function [c_width-1:0] hexstr_conv; + input [(c_width*8)-1:0] def_data; + + integer index,i,j; + reg [3:0] bin; + + begin + index = 0; + hexstr_conv = 'b0; + for( i=c_width-1; i>=0; i=i-1 ) + begin + case (def_data[7:0]) + 8'b00000000 : + begin + bin = 4'b0000; + i = -1; + end + 8'b00110000 : bin = 4'b0000; + 8'b00110001 : bin = 4'b0001; + 8'b00110010 : bin = 4'b0010; + 8'b00110011 : bin = 4'b0011; + 8'b00110100 : bin = 4'b0100; + 8'b00110101 : bin = 4'b0101; + 8'b00110110 : bin = 4'b0110; + 8'b00110111 : bin = 4'b0111; + 8'b00111000 : bin = 4'b1000; + 8'b00111001 : bin = 4'b1001; + 8'b01000001 : bin = 4'b1010; + 8'b01000010 : bin = 4'b1011; + 8'b01000011 : bin = 4'b1100; + 8'b01000100 : bin = 4'b1101; + 8'b01000101 : bin = 4'b1110; + 8'b01000110 : bin = 4'b1111; + 8'b01100001 : bin = 4'b1010; + 8'b01100010 : bin = 4'b1011; + 8'b01100011 : bin = 4'b1100; + 8'b01100100 : bin = 4'b1101; + 8'b01100101 : bin = 4'b1110; + 8'b01100110 : bin = 4'b1111; + default : + begin + if (c_yydisable_warnings == 0) begin + $display("ERROR in %m at time %t : NOT A HEX CHARACTER",$time); + end + bin = 4'bx; + end + endcase + for( j=0; j<4; j=j+1) + begin + if ((index*4)+j < c_width) + begin + hexstr_conv[(index*4)+j] = bin[j]; + end + end + index = index + 1; + def_data = def_data >> 8; + end + end + endfunction + + initial begin + sinit_value = 'b0 ; + default_data = hexstr_conv(c_default_data); + if (c_has_sinit == 1 ) + sinit_value = hexstr_conv(c_sinit_value); + for(i = 0; i < c_depth; i = i + 1) + mem[i] = default_data; + if (c_has_default_data == 0) + $readmemb(c_mem_init_file, mem); + for (k = 0; k <= c_pipe_stages; k = k + 1) + pipeline[k] = sinit_value ; + for (m = 0; m <= c_pipe_stages; m = m + 1) + sub_rdy[m] = 0 ; + dout_int = sinit_value ; + nd_q = 0 ; + new_data_q = 0 ; + di_q = 0 ; + addr_q = 0 ; + we_q = 0 ; + #1 pipe_out = sinit_value; + end + +// Generate output control signals RFD and RDY +// Combinational + + always @ ( rfd_int) + begin + if (c_has_rfd == 1) + RFD = rfd_int ; + else + RFD = 1'b0 ; + end + + always @ (en_int ) + begin + if (en_int == 1'b1) + rfd_int = 1'b1 ; + else + rfd_int = 1'b0 ; + end + + always @ ( rdy_int ) + begin + if ((c_has_rdy == 1) && (c_has_nd == 1) && (c_has_rfd == 1) ) + RDY = rdy_int ; + else + RDY = 1'b0 ; + end + + assign nd_int = en_int && nd_i ; // only pass nd through if en is 1 + +// Register hanshaking inputs + + always @(posedge clk_int ) + begin + if (en_int == 1'b1) + begin + if (ssr_int == 1'b1) + nd_q <= 1'b0 ; + else + nd_q <= nd_int; + end + else + nd_q <= nd_q ; + end +// Register data / address / data inputs + + always @(posedge clk_int ) + begin + if (en_int == 1'b1) + begin + di_q <= di_i ; + addr_q <= addr_i ; + we_q <= we_i ; + end + end + +// select registered or non-registered write enable + + always @( we_i or we_q) + begin + if (c_reg_inputs == 1 ) + we_int = we_q ; + else + we_int = we_i ; + end + +// select registered data/address/nd inputs + + always @( di_i or di_q) + begin + if ( c_reg_inputs == 1) + di_int = di_q ; + else + di_int = di_i ; + end + + always @( addr_i or addr_q or nd_q or nd_int or we_q or we_i) + begin + if (c_reg_inputs == 1) + begin + addr_int = addr_q; + if ((we_q == 1'b1) && (c_write_mode == 2)) + new_data = 1'b0 ; + else + new_data = nd_q ; + end + else + begin + addr_int = addr_i ; + if ((we_i == 1'b1) && (c_write_mode == 2)) + new_data = 1'b0 ; + else + new_data = nd_int ; + end + end + +// Register the new_data signal to track the synchronous RAM output + + always @(posedge clk_int) + begin + if ( en_int == 1'b1 ) + begin + if (ssr_int == 1'b1) + new_data_q <= 0 ; + else + new_data_q <= new_data ; + end + end + + initial begin + case (c_write_mode) + `c_write_first : wr_mode <= 2'b00; + `c_read_first : wr_mode <= 2'b01; + `c_no_change : wr_mode <= 2'b10; + default : begin + if (c_yydisable_warnings == 0) begin + $display("Error in %m at time %t: c_write_mode = %s is not WRITE_FIRST, READ_FIRST or NO_CHANGE.",$time , c_write_mode); + end + $finish; + end + endcase + end + + + /*************************************************************** + *The following always block assigns the value for the DOUT bus + ***************************************************************/ + always @(posedge clk_int) begin + if (en_int == 1'b1) begin + if (ssr_int == 1'b1) begin + dout_int <= sinit_value; + end + else begin + //The following IF block assigns the output for a write operation + if (we_int == 1'b1) begin + if (wr_mode == 2'b00) begin + if (addr_int < c_depth) + dout_int <= di_int; + else + //Warning Condition (Error occurs on rising edge of CLK): + //Write Mode Port is "Write First" and EN = 1 and SINIT = 0 and WE = 1 and ADDR out of the valid range + if (c_yydisable_warnings == 0) begin + $display("Invalid Address Warning #1: Warning in %m at time %t: Block memory address %d (%b) invalid. Valid depth configured as 0 to %d",$time,addr_int,addr_int,c_depth-1); + end + end + else if (wr_mode == 2'b01) begin + if (addr_int < c_depth) + dout_int <= mem[addr_int]; + else + //Warning Condition (Error occurs on rising edge of CLK): + //Write Mode Port is "Read First" and EN = 1 and SINIT = 0 and WE = 1 and ADDR out of the valid range + if (c_yydisable_warnings == 0) begin + $display("Invalid Address Warning #2: Warning in %m at time %t: Block memory address %d (%b) invalid. Valid depth configured as 0 to %d",$time,addr_int,addr_int,c_depth-1); + end + end + else begin + if (addr_int < c_depth) + dout_int <= dout_int ; + else + //Warning Condition (Error occurs on rising edge of CLK): + //Write Mode Port is "No Change" and EN = 1 and SINIT = 0 and WE = 1 and ADDR out of the valid range + if (c_yydisable_warnings == 0) begin + $display("Invalid Address Warning #3: Warning in %m at time %t: Block memory address %d (%b) invalid. Valid depth configured as 0 to %d",$time,addr_int,addr_int,c_depth-1); + end + end + end + //The following ELSE block assigns the output for a read operation + else begin + if (addr_int < c_depth) + dout_int <= mem[addr_int]; + else + //Warning Condition (Error occurs on rising edge of CLK): + //EN = 1 and SINIT = 0 and WE = 0 and ADDRA out of the valid range + if (c_yydisable_warnings == 0) begin + $display("Invalid Address Warning #4: Warning in %m at time %t: Block memory address %d (%b) invalid. Valid depth configured as 0 to %d",$time,addr_int,addr_int,c_depth-1); + end + end + end + end + end + + +// Write to memory contents + /*************************************************************************************** + *The following always block assigns the DIN bus to the memory during a write operation + ***************************************************************************************/ + always @(posedge clk_int) begin + if (en_int == 1'b1 && we_int == 1'b1) begin + if (addr_int < c_depth) + mem [addr_int] <= di_int ; + else + //Warning Condition (Error occurs on rising edge of CLK): + //EN = 1 and WE = 1 and ADDR out of the valid range + if (c_yydisable_warnings == 0) begin + $display("Invalid Address Warning #5: Warning in %m at time %t: Block memory address %d (%b) invalid. Valid depth configured as 0 to %d",$time,addr_int,addr_int,c_depth-1); + end + end + end + +// output pipelines + + always @(posedge clk_int) begin + if (en_int == 1'b1 && c_pipe_stages > 0) + begin + for (i = c_pipe_stages; i >= 1; i = i -1 ) + begin + if (ssr_int == 1'b1 && en_int == 1'b1) + begin + pipeline[i] <= sinit_value ; + sub_rdy[i] <= 0 ; + end + else + begin + // Do not update output register if no_change on write and + // WE = 1 +// if (!(c_write_mode == 2 && we_int == 1)) begin + if (i==1) + begin + pipeline[i] <= dout_int; + end + else + begin + pipeline[i] <= pipeline[i-1] ; + end +// end // if (!(c_write_mode == 2 && we_int == 1)) + if (i==1) + begin + sub_rdy[i] <= new_data_q; + end + else + begin + sub_rdy[i] <= sub_rdy[i-1] ; + end + end + end + end + end + +// Select pipelined data output or no-pipelined data output + + always @( pipeline[c_pipe_stages] or sub_rdy[c_pipe_stages] or new_data_q or dout_int) begin + if (c_pipe_stages == 0 ) + begin + pipe_out = dout_int ; + rdy_int = new_data_q ; + end + else + begin + rdy_int = sub_rdy[c_pipe_stages]; + pipe_out = pipeline[c_pipe_stages]; + end + end + +endmodule + +`endcelldefine diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/BLK_MEM_GEN_V2_1.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/BLK_MEM_GEN_V2_1.v new file mode 100644 index 0000000..a5a388e --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/BLK_MEM_GEN_V2_1.v @@ -0,0 +1,911 @@ +/****************************************************************************** + * + * Block Memory Generator Core - Block Memory Behavioral Model + * + * Copyright(C) 2005 by Xilinx, Inc. All rights reserved. + * This text/file contains proprietary, confidential + * information of Xilinx, Inc., is distributed under + * license from Xilinx, Inc., and may be used, copied + * and/or disclosed only pursuant to the terms of a valid + * license agreement with Xilinx, Inc. Xilinx hereby + * grants you a license to use this text/file solely for + * design, simulation, implementation and creation of + * design files limited to Xilinx devices or technologies. + * Use with non-Xilinx devices or technologies is expressly + * prohibited and immediately terminates your license unless + * covered by a separate agreement. + * + * Xilinx is providing this design, code, or information + * "as-is" solely for use in developing programs and + * solutions for Xilinx devices, with no obligation on the + * part of Xilinx to provide support. By providing this design, + * code, or information as one possible implementation of + * this feature, application or standard, Xilinx is making no + * representation that this implementation is free from any + * claims of infringement. You are responsible for obtaining + * any rights you may require for your implementation. + * Xilinx expressly disclaims any warranty whatsoever with + * respect to the adequacy of the implementation, including + * but not limited to any warranties or representations that this + * implementation is free from claims of infringement, implied + * warranties of merchantability or fitness for a particular + * purpose. + * + * Xilinx products are not intended for use in life support + * appliances, devices, or systems. Use in such applications is + * expressly prohibited. + * + * Any modifications that are made to the Source Code are + * done at the user's sole risk and will be unsupported. + * The Xilinx Support Hotline does not have access to source + * code and therefore cannot answer specific questions related + * to source HDL. The Xilinx Hotline support of original source + * code IP shall only address issues and questions related + * to the standard Netlist version of the core (and thus + * indirectly, the original core source). + * + * This copyright and support notice must be retained as part + * of this text at all times. (c) Copyright 1995-2005 Xilinx, Inc. + * All rights reserved. + * + ***************************************************************************** + * + * Filename: BLK_MEM_GEN_V2_1.v + * + * Description: + * This file is the Verilog behvarial model for the + * Block Memory Generator Core. + * + ***************************************************************************** + * Author: Xilinx + * + * History: January 11, 2006 Initial revision + *****************************************************************************/ +`timescale 1ps/1ps + +module BLK_MEM_GEN_V2_1_output_stage + #(parameter C_DATA_WIDTH = 32, + parameter C_HAS_SSR = 1, + parameter C_SINIT_VAL = "0", + parameter C_HAS_REGCE = 1, + parameter C_HAS_EN = 1, + parameter C_FAMILY = "virtex5", + parameter num_stages = 1, + parameter flop_delay = 100) + (input CLK, + input SSR, + input REGCE, + input EN, + input [C_DATA_WIDTH-1:0] DIN, + output reg [C_DATA_WIDTH-1:0] DOUT); + + localparam reg_stages = (num_stages == 0) ? 0 : num_stages-1; + reg [C_DATA_WIDTH*reg_stages-1:0] out_regs; + reg [C_DATA_WIDTH*8-1:0] sinit_str = C_SINIT_VAL; + reg [C_DATA_WIDTH-1:0] sinit_val; + + // Wire off optional inputs based on parameters + //--------------------------------------------- + wire en_i; + wire regce_i; + wire ssr_i; + assign en_i = (C_HAS_EN==0 || EN); + assign regce_i = ((C_HAS_REGCE==1) && REGCE) || + ((C_HAS_REGCE==0) && (C_HAS_EN==0 || EN)); + assign ssr_i = (C_HAS_SSR==1) && SSR; + + initial begin + // Power on: load up the output registers and latches + if (!($sscanf(sinit_str, "%h", sinit_val))) begin + sinit_val = 0; + end + DOUT = sinit_val; + // This will be one wider than need, but 0 is an error + out_regs = {(reg_stages+1){sinit_val}}; + end + + generate if (num_stages == 0) begin : zero_stages + always @* begin + DOUT = DIN; + end + end + endgenerate + + generate if (num_stages == 1) begin : one_stages + always @(posedge CLK) begin + if (regce_i && ssr_i) begin + DOUT <= #flop_delay sinit_val; + end else if (regce_i) begin + DOUT <= #flop_delay DIN; + end + end + end + endgenerate + + generate if (num_stages > 1) begin : multi_stage + always @(posedge CLK) begin + if (regce_i && ssr_i) begin + DOUT <= #flop_delay sinit_val; + end else if (regce_i) begin + DOUT <= #flop_delay + out_regs[C_DATA_WIDTH*(num_stages-2)+:C_DATA_WIDTH]; + end + + if (en_i) begin + out_regs <= #flop_delay + (out_regs << C_DATA_WIDTH) | DIN; + end + end + end + endgenerate +endmodule + +module BLK_MEM_GEN_V2_1 + #(parameter C_ADDRA_WIDTH = 5, + parameter C_ADDRB_WIDTH = 5, + parameter C_ALGORITHM = 2, + parameter C_BYTE_SIZE = 8, + parameter C_COMMON_CLK = 1, + parameter C_DEFAULT_DATA = "0", + parameter C_DISABLE_WARN_BHV_COLL = 0, + parameter C_DISABLE_WARN_BHV_RANGE = 0, + parameter C_FAMILY = "virtex4", + parameter C_HAS_ENA = 1, + parameter C_HAS_ENB = 1, + parameter C_HAS_MEM_OUTPUT_REGS = 0, + parameter C_HAS_MUX_OUTPUT_REGS = 0, + parameter C_HAS_REGCEA = 0, + parameter C_HAS_REGCEB = 0, + parameter C_HAS_SSRA = 0, + parameter C_HAS_SSRB = 0, + parameter C_INIT_FILE_NAME = "", + parameter C_LOAD_INIT_FILE = 0, + parameter C_MEM_TYPE = 2, + parameter C_PRIM_TYPE = 3, + parameter C_READ_DEPTH_A = 64, + parameter C_READ_DEPTH_B = 64, + parameter C_READ_WIDTH_A = 32, + parameter C_READ_WIDTH_B = 32, + parameter C_SIM_COLLISION_CHECK = "NONE", + parameter C_SINITA_VAL = "0", + parameter C_SINITB_VAL = "0", + parameter C_USE_BYTE_WEA = 0, + parameter C_USE_BYTE_WEB = 0, + parameter C_USE_DEFAULT_DATA = 0, + parameter C_WEA_WIDTH = 1, + parameter C_WEB_WIDTH = 1, + parameter C_WRITE_DEPTH_A = 64, + parameter C_WRITE_DEPTH_B = 64, + parameter C_WRITE_MODE_A = "WRITE_FIRST", + parameter C_WRITE_MODE_B = "WRITE_FIRST", + parameter C_WRITE_WIDTH_A = 32, + parameter C_WRITE_WIDTH_B = 32, + parameter C_CORENAME = "blk_mem_gen_v2_1") + (input CLKA, + input [C_WRITE_WIDTH_A-1:0] DINA, + input [C_ADDRA_WIDTH-1:0] ADDRA, + input ENA, + input REGCEA, + input [C_WEA_WIDTH-1:0] WEA, + input SSRA, + output [C_READ_WIDTH_A-1:0] DOUTA, + input CLKB, + input [C_WRITE_WIDTH_B-1:0] DINB, + input [C_ADDRB_WIDTH-1:0] ADDRB, + input ENB, + input REGCEB, + input [C_WEB_WIDTH-1:0] WEB, + input SSRB, + output [C_READ_WIDTH_B-1:0] DOUTB); + + // constants for the core behavior + //================================ + // file handles for logging + //------------------------------------------------------ + localparam addrfile = 32'h8000_0001; // stdout for addr out of range + localparam collfile = 32'h8000_0001; // stdout for coll detection + localparam errfile = 32'h8000_0001; // stdout for file I/O errors + + // other constants + //------------------------------------------------------ + localparam coll_delay = 2000; // 2 ns + + // locally derived parameters to determine memory shape + //----------------------------------------------------- + localparam min_width_a = (C_WRITE_WIDTH_A < C_READ_WIDTH_A) ? + C_WRITE_WIDTH_A : C_READ_WIDTH_A; + localparam min_width_b = (C_WRITE_WIDTH_B < C_READ_WIDTH_B) ? + C_WRITE_WIDTH_B : C_READ_WIDTH_B; + localparam min_width = (min_width_a < min_width_b) ? + min_width_a : min_width_b; + + localparam max_width_a = (C_WRITE_WIDTH_A > C_READ_WIDTH_A) ? + C_WRITE_WIDTH_A : C_READ_WIDTH_A; + localparam max_width_b = (C_WRITE_WIDTH_B > C_READ_WIDTH_B) ? + C_WRITE_WIDTH_B : C_READ_WIDTH_B; + localparam max_width = (max_width_a > max_width_b) ? + max_width_a : max_width_b; + + localparam max_depth_a = (C_WRITE_DEPTH_A > C_READ_DEPTH_A) ? + C_WRITE_DEPTH_A : C_READ_DEPTH_A; + localparam max_depth_b = (C_WRITE_DEPTH_B > C_READ_DEPTH_B) ? + C_WRITE_DEPTH_B : C_READ_DEPTH_B; + localparam max_depth = (max_depth_a > max_depth_b) ? + max_depth_a : max_depth_b; + + // locally derived parameters to assist memory access + //---------------------------------------------------- + localparam write_width_ratio_a = C_WRITE_WIDTH_A/min_width; + localparam read_width_ratio_a = C_READ_WIDTH_A/min_width; + localparam write_width_ratio_b = C_WRITE_WIDTH_B/min_width; + localparam read_width_ratio_b = C_READ_WIDTH_B/min_width; + + // To modify the LSBs of the 'wider' data to the actual + // address value + //---------------------------------------------------- + localparam write_addr_a_div = C_WRITE_WIDTH_A/min_width_a; + localparam read_addr_a_div = C_READ_WIDTH_A/min_width_a; + localparam write_addr_b_div = C_WRITE_WIDTH_B/min_width_b; + localparam read_addr_b_div = C_READ_WIDTH_B/min_width_b; + + // If byte writes aren't being used, make sure byte_size is not + // wider than the memory elements to avoid compilation warnings + localparam byte_size = (C_BYTE_SIZE < min_width) ? C_BYTE_SIZE : min_width; + + // the memory + reg [min_width-1:0] memory [0:max_depth-1]; + // memory output 'latches' + reg [C_READ_WIDTH_A-1:0] memory_out_a; + reg [C_READ_WIDTH_B-1:0] memory_out_b; + // reset values + reg [C_READ_WIDTH_A-1:0] sinita_val; + reg [C_READ_WIDTH_B-1:0] sinitb_val; + + // collision detect + reg is_collision; + reg is_collision_a, is_collision_delay_a; + reg is_collision_b, is_collision_delay_b; + + // temporary variables for initialization + //--------------------------------------- + integer status; + reg [639:0] err_str; + integer initfile; + // data input buffer + reg [C_WRITE_WIDTH_A-1:0] mif_data; + // string values in hex + reg [C_READ_WIDTH_A*8-1:0] sinita_str = C_SINITA_VAL; + reg [C_READ_WIDTH_B*8-1:0] sinitb_str = C_SINITB_VAL; + reg [C_WRITE_WIDTH_A*8-1:0] default_data_str = C_DEFAULT_DATA; + // initialization filename + reg [1023*8-1:0] init_file_str = C_INIT_FILE_NAME; + + // internal configuration parameters + //--------------------------------------------- + localparam flop_delay = 100; // 100 ps + localparam single_port = (C_MEM_TYPE==0 || C_MEM_TYPE==3); + localparam is_rom = (C_MEM_TYPE==3 || C_MEM_TYPE==4); + localparam has_a_write = (!is_rom); + localparam has_b_write = (C_MEM_TYPE==2); + localparam has_a_read = (C_MEM_TYPE!=1); + localparam has_b_read = (!single_port); + localparam has_b_port = (has_b_read || has_b_write); + localparam num_output_stages = C_HAS_MEM_OUTPUT_REGS + + C_HAS_MUX_OUTPUT_REGS; + + wire ena_i; + wire enb_i; + wire reseta_i; + wire resetb_i; + wire [C_WEA_WIDTH-1:0] wea_i; + wire [C_WEB_WIDTH-1:0] web_i; + wire rea_i; + wire reb_i; + assign ena_i = (C_HAS_ENA==0) || ENA; + assign enb_i = ((C_HAS_ENB==0) || ENB) && has_b_port; + assign reseta_i = (C_HAS_SSRA==1) && SSRA && ena_i && + (num_output_stages==0); + assign resetb_i = (C_HAS_SSRB==1) && SSRB && enb_i && + (num_output_stages==0); + assign wea_i = (has_a_write && ena_i) ? WEA : 'b0; + assign web_i = (has_b_write && enb_i) ? WEB : 'b0; + assign rea_i = (has_a_read) ? ena_i : 'b0; + assign reb_i = (has_b_read) ? enb_i : 'b0; + + // tasks to access the memory + //--------------------------- + task write_a + (input reg [C_ADDRA_WIDTH-1:0] addr, + input reg [C_WEA_WIDTH-1:0] byte_en, + input reg [C_WRITE_WIDTH_A-1:0] data); + reg [C_WRITE_WIDTH_A-1:0] current_contents; + reg [C_ADDRA_WIDTH-1:0] address; + integer i; + begin + // Shift the address by the ratio + address = (addr/write_addr_a_div); + if (address >= C_WRITE_DEPTH_A) begin + if (!C_DISABLE_WARN_BHV_RANGE) begin + $fdisplay(addrfile, + "%0s WARNING: Address %0h is outside range for A Write", + C_CORENAME, addr); + end + + // valid address + end else begin + + // Combine w/ byte writes + if (C_USE_BYTE_WEA) begin + + // Get the current memory contents + if (write_width_ratio_a == 1) begin + // Workaround for IUS 5.5 part-select issue + current_contents = memory[address]; + end else begin + for (i = 0; i < write_width_ratio_a; i = i + 1) begin + current_contents[min_width*i+:min_width] + = memory[address*write_width_ratio_a + i]; + end + end + + // Apply incoming bytes + if (C_WEA_WIDTH == 1) begin + // Workaround for IUS 5.5 part-select issue + if (byte_en[0]) begin + current_contents = data; + end + end else begin + for (i = 0; i < C_WEA_WIDTH; i = i + 1) begin + if (byte_en[i]) begin + current_contents[byte_size*i+:byte_size] + = data[byte_size*i+:byte_size]; + end + end + end + + // No byte-writes, overwrite the whole word + end else begin + current_contents = data; + end + + // Write data to memory + if (write_width_ratio_a == 1) begin + // Workaround for IUS 5.5 part-select issue + memory[address*write_width_ratio_a] = current_contents; + end else begin + for (i = 0; i < write_width_ratio_a; i = i + 1) begin + memory[address*write_width_ratio_a + i] + = current_contents[min_width*i+:min_width]; + end + end + + end + end + endtask + + task write_b + (input reg [C_ADDRB_WIDTH-1:0] addr, + input reg [C_WEB_WIDTH-1:0] byte_en, + input reg [C_WRITE_WIDTH_B-1:0] data); + reg [C_WRITE_WIDTH_B-1:0] current_contents; + reg [C_ADDRB_WIDTH-1:0] address; + integer i; + begin + // Shift the address by the ratio + address = (addr/write_addr_b_div); + if (address >= C_WRITE_DEPTH_B) begin + if (!C_DISABLE_WARN_BHV_RANGE) begin + $fdisplay(addrfile, + "%0s WARNING: Address %0h is outside range for B Write", + C_CORENAME, addr); + end + + // valid address + end else begin + + // Combine w/ byte writes + if (C_USE_BYTE_WEB) begin + + // Get the current memory contents + if (write_width_ratio_b == 1) begin + // Workaround for IUS 5.5 part-select issue + current_contents = memory[address]; + end else begin + for (i = 0; i < write_width_ratio_b; i = i + 1) begin + current_contents[min_width*i+:min_width] + = memory[address*write_width_ratio_b + i]; + end + end + + // Apply incoming bytes + if (C_WEB_WIDTH == 1) begin + // Workaround for IUS 5.5 part-select issue + if (byte_en[0]) begin + current_contents = data; + end + end else begin + for (i = 0; i < C_WEB_WIDTH; i = i + 1) begin + if (byte_en[i]) begin + current_contents[byte_size*i+:byte_size] + = data[byte_size*i+:byte_size]; + end + end + end + + // No byte-writes, overwrite the whole word + end else begin + current_contents = data; + end + + // Write data to memory + if (write_width_ratio_b == 1) begin + // Workaround for IUS 5.5 part-select issue + memory[address*write_width_ratio_b] = current_contents; + end else begin + for (i = 0; i < write_width_ratio_b; i = i + 1) begin + memory[address*write_width_ratio_b + i] + = current_contents[min_width*i+:min_width]; + end + end + end + end + endtask + + task read_a + (input reg [C_ADDRA_WIDTH-1:0] addr, + input reg reset); + reg [C_ADDRA_WIDTH-1:0] address; + integer i; + begin + + if (reset) begin + memory_out_a <= #flop_delay sinita_val; + end else begin + // Shift the address by the ratio + address = (addr/read_addr_a_div); + if (address >= C_READ_DEPTH_A) begin + if (!C_DISABLE_WARN_BHV_RANGE) begin + $fdisplay(addrfile, + "%0s WARNING: Address %0h is outside range for A Read", + C_CORENAME, addr); + end + + // valid address + end else begin + + if (read_width_ratio_a==1) begin + memory_out_a <= #flop_delay memory[address*read_width_ratio_a]; + end else begin + // Increment through the 'partial' words in the memory + for (i = 0; i < read_width_ratio_a; i = i + 1) begin + memory_out_a[min_width*i+:min_width] + <= #flop_delay memory[address*read_width_ratio_a + i]; + end + end + + end + end + end + endtask + + task read_b + (input reg [C_ADDRB_WIDTH-1:0] addr, + input reg reset); + reg [C_ADDRB_WIDTH-1:0] address; + integer i; + begin + + if (reset) begin + memory_out_b <= #flop_delay sinitb_val; + end else begin + // Shift the address + address = (addr/read_addr_b_div); + if (address >= C_READ_DEPTH_B) begin + if (!C_DISABLE_WARN_BHV_RANGE) begin + $fdisplay(addrfile, + "%0s WARNING: Address %0h is outside range for B Read", + C_CORENAME, addr); + end + + // valid address + end else begin + + if (read_width_ratio_b==1) begin + memory_out_b <= #flop_delay memory[address*read_width_ratio_b]; + end else begin + // Increment through the 'partial' words in the memory + for (i = 0; i < read_width_ratio_b; i = i + 1) begin + memory_out_b[min_width*i+:min_width] + <= #flop_delay memory[address*read_width_ratio_b + i]; + end + end + + end + end + end + endtask + + task init_memory; + integer i, addr_step; + integer status; + reg [C_WRITE_WIDTH_A-1:0] default_data; + begin + default_data = 0; + + // Convert the default to hex + if (C_USE_DEFAULT_DATA) begin + if (default_data_str == "") begin + $fdisplay(errfile, "%0s ERROR: C_DEFAULT_DATA is empty!", C_CORENAME); + $finish; + end else begin + status = $sscanf(default_data_str, "%h", default_data); + if (status == 0) begin + $fdisplay(errfile, {"%0s ERROR: Unsuccessful hexadecimal read", + "from C_DEFAULT_DATA: %0s"}, + C_CORENAME, C_DEFAULT_DATA); + $finish; + end + end + end + + // Step by write_addr_a_div through the memory via the + // Port A write interface to hit every location once + addr_step = write_addr_a_div; + + // 'write' to every location with default (or 0) + for (i = 0; i < C_WRITE_DEPTH_A*addr_step; i = i + addr_step) begin + write_a(i, {C_WEA_WIDTH{1'b1}}, default_data); + end + + // Get specialized data from the MIF file + if (C_LOAD_INIT_FILE) begin + if (init_file_str == "") begin + $fdisplay(errfile, "%0s ERROR: C_INIT_FILE_NAME is empty!", + C_CORENAME); + $finish; + end else begin + initfile = $fopen(init_file_str, "r"); + if (initfile == 0) begin + $fdisplay(errfile, {"%0s, ERROR: Problem opening", + "C_INIT_FILE_NAME: %0s!"}, + C_CORENAME, init_file_str); + $finish; + end else begin + // loop through the mif file, loading in the data + for (i = 0; i < C_WRITE_DEPTH_A*addr_step; i = i + addr_step) begin + status = $fscanf(initfile, "%b", mif_data); + if (status > 0) begin + write_a(i, {C_WEA_WIDTH{1'b1}}, mif_data); + end + end + $fclose(initfile); + end + end + end + end + endtask + + function integer collision_check (input reg [C_ADDRA_WIDTH-1:0] addr_a, + input integer iswrite_a, + input reg [C_ADDRB_WIDTH-1:0] addr_b, + input integer iswrite_b); + reg [C_ADDRA_WIDTH-1:0] base_addr_a; + reg [C_ADDRB_WIDTH-1:0] base_addr_b; + integer ratio_a, ratio_b; + integer lo_addr_wider, hi_addr_wider; + integer lo_addr_narrow, hi_addr_narrow; + begin + // Convert the input addresses in base and offsets for our + // memory array. Ignore LSBs for asymmetric ports + if (iswrite_a) begin + base_addr_a = (addr_a/write_addr_a_div) * write_addr_a_div; + ratio_a = write_width_ratio_a; + end else begin + base_addr_a = (addr_a/read_addr_a_div) * read_addr_a_div; + ratio_a = read_width_ratio_a; + end + if (iswrite_b) begin + base_addr_b = (addr_b/write_addr_b_div) * write_addr_b_div; + ratio_b = write_width_ratio_b; + end else begin + base_addr_b = (addr_b/read_addr_b_div) * read_addr_b_div; + ratio_b = read_width_ratio_b; + end + + // Determine the wider port, and normalized ranges + if (ratio_a >= ratio_b) begin + lo_addr_wider = base_addr_a * ratio_a; + hi_addr_wider = lo_addr_wider + ratio_a; + lo_addr_narrow = base_addr_b * ratio_b; + hi_addr_narrow = lo_addr_narrow + ratio_b; + end else begin + lo_addr_wider = base_addr_b * ratio_b; + hi_addr_wider = lo_addr_wider + ratio_b; + lo_addr_narrow = base_addr_a * ratio_a; + hi_addr_narrow = lo_addr_narrow + ratio_a; + end + + // compare the two ranges of address (narrow inside wider) + if ((lo_addr_narrow >= lo_addr_wider) && + (hi_addr_narrow <= hi_addr_wider)) begin + collision_check = 1; + end else begin + collision_check = 0; + end + + end + endfunction + + // power on values + //----------------------------- + initial begin + // Load up the memory + init_memory; + // Load up the output registers and latches + if ($sscanf(sinita_str, "%h", sinita_val)) begin + memory_out_a = sinita_val; + end else begin + memory_out_a = 0; + end + if ($sscanf(sinitb_str, "%h", sinitb_val)) begin + memory_out_b = sinitb_val; + end else begin + memory_out_b = 0; + end + + $display("Block Memory Generator CORE Generator module %m is using a behavioral model for simulation which will not precisely model memory collision behavior."); + + end + + //------------------------------------------------------------------------- + // These are the main blocks which schedule read and write operations + //------------------------------------------------------------------------- + + generate if (C_COMMON_CLK) begin : common_clk_scheduling + // Synchronous clocks: schedule port operations with respect to + // both write operating modes + always @(posedge CLKA) begin + case ({C_WRITE_MODE_A, C_WRITE_MODE_B}) + {"WRITE_FIRST","WRITE_FIRST"}: begin + if (wea_i) write_a(ADDRA, wea_i, DINA); + if (web_i) write_b(ADDRB, web_i, DINB); + if (rea_i) read_a(ADDRA, reseta_i); + if (reb_i) read_b(ADDRB, resetb_i); + end + {"READ_FIRST", "WRITE_FIRST"}: begin + if (web_i) write_b(ADDRB, web_i, DINB); + if (reb_i) read_b(ADDRB, resetb_i); + if (rea_i) read_a(ADDRA, reseta_i); + if (wea_i) write_a(ADDRA, wea_i, DINA); + end + {"WRITE_FIRST","READ_FIRST"}: begin + if (wea_i) write_a(ADDRA, wea_i, DINA); + if (rea_i) read_a(ADDRA, reseta_i); + if (reb_i) read_b(ADDRB, resetb_i); + if (web_i) write_b(ADDRB, web_i, DINB); + end + {"READ_FIRST", "READ_FIRST"}: begin + if (rea_i) read_a(ADDRA, reseta_i); + if (reb_i) read_b(ADDRB, resetb_i); + if (wea_i) write_a(ADDRA, wea_i, DINA); + if (web_i) write_b(ADDRB, web_i, DINB); + end + {"WRITE_FIRST","NO_CHANGE"}: begin + if (wea_i) write_a(ADDRA, wea_i, DINA); + if (rea_i) read_a(ADDRA, reseta_i); + if ((reb_i && !web_i) || resetb_i) read_b(ADDRB, resetb_i); + if (web_i) write_b(ADDRB, web_i, DINB); + end + {"READ_FIRST", "NO_CHANGE"}: begin + if (rea_i) read_a(ADDRA, reseta_i); + if ((reb_i && !web_i) || resetb_i) read_b(ADDRB, resetb_i); + if (wea_i) write_a(ADDRA, wea_i, DINA); + if (web_i) write_b(ADDRB, web_i, DINB); + end + {"NO_CHANGE", "WRITE_FIRST"}: begin + if (wea_i) write_a(ADDRA, wea_i, DINA); + if (web_i) write_b(ADDRB, web_i, DINB); + if ((rea_i && !wea_i) || reseta_i) read_a(ADDRA, reseta_i); + if (reb_i) read_b(ADDRB, resetb_i); + end + {"NO_CHANGE", "READ_FIRST"}: begin + if (reb_i) read_b(ADDRB, resetb_i); + if ((rea_i && !wea_i) || reseta_i) read_a(ADDRA, reseta_i); + if (wea_i) write_a(ADDRA, wea_i, DINA); + if (web_i) write_b(ADDRB, web_i, DINB); + end + {"NO_CHANGE", "NO_CHANGE"}: begin + if (wea_i) write_a(ADDRA, wea_i, DINA); + if (web_i) write_b(ADDRB, web_i, DINB); + if ((rea_i && !wea_i) || reseta_i) read_a(ADDRA, reseta_i); + if ((reb_i && !web_i) || resetb_i) read_b(ADDRB, resetb_i); + end + default: begin + if (wea_i) write_a(ADDRA, wea_i, DINA); + if (web_i) write_b(ADDRB, web_i, DINB); + if (rea_i) read_a(ADDRA, reseta_i); + if (reb_i) read_b(ADDRB, resetb_i); + end + endcase + end + + end else begin : asynch_clk_scheduling + // Asynchronous clocks: port operation is independent + always @(posedge CLKA) begin + case (C_WRITE_MODE_A) + "WRITE_FIRST": begin + if (wea_i) write_a(ADDRA, wea_i, DINA); + if (rea_i) read_a(ADDRA, reseta_i); + end + "READ_FIRST": begin + if (rea_i) read_a(ADDRA, reseta_i); + if (wea_i) write_a(ADDRA, wea_i, DINA); + end + "NO_CHANGE": begin + if (wea_i) write_a(ADDRA, wea_i, DINA); + if ((rea_i && !wea_i) || reseta_i) read_a(ADDRA, reseta_i); + end + endcase + end + + always @(posedge CLKB) begin + case (C_WRITE_MODE_B) + "WRITE_FIRST": begin + if (web_i) write_b(ADDRB, web_i, DINB); + if (reb_i) read_b(ADDRB, resetb_i); + end + "READ_FIRST": begin + if (reb_i) read_b(ADDRB, resetb_i); + if (web_i) write_b(ADDRB, web_i, DINB); + end + "NO_CHANGE": begin + if (web_i) write_b(ADDRB, web_i, DINB); + if ((reb_i && !web_i) || resetb_i) read_b(ADDRB, resetb_i); + end + endcase + end + end + endgenerate + + // Variable depth output stage + BLK_MEM_GEN_V2_1_output_stage + #(.C_DATA_WIDTH (C_READ_WIDTH_A), + .C_HAS_SSR (C_HAS_SSRA), + .C_SINIT_VAL (C_SINITA_VAL), + .C_HAS_REGCE (C_HAS_REGCEA), + .C_HAS_EN (C_HAS_ENA), + .C_FAMILY (C_FAMILY), + .num_stages (num_output_stages), + .flop_delay (flop_delay)) + reg_a + (.CLK (CLKA), + .SSR (SSRA), + .REGCE (REGCEA), + .EN (ENA), + .DIN (memory_out_a), + .DOUT (DOUTA)); + + BLK_MEM_GEN_V2_1_output_stage + #(.C_DATA_WIDTH (C_READ_WIDTH_B), + .C_HAS_SSR (C_HAS_SSRB), + .C_SINIT_VAL (C_SINITB_VAL), + .C_HAS_REGCE (C_HAS_REGCEB), + .C_HAS_EN (C_HAS_ENB), + .C_FAMILY (C_FAMILY), + .num_stages (num_output_stages), + .flop_delay (flop_delay)) + reg_b + (.CLK (CLKB), + .SSR (SSRB), + .REGCE (REGCEB), + .EN (ENB), + .DIN (memory_out_b), + .DOUT (DOUTB)); + + // Synchronous collision checks + generate if (!C_DISABLE_WARN_BHV_COLL && C_COMMON_CLK) begin : sync_coll + always @(posedge CLKA) begin + // Possible collision if both are enabled and the addresses match + if (ena_i && enb_i) begin + is_collision = collision_check(ADDRA, wea_i, ADDRB, web_i); + end else begin + is_collision = 0; + end + + // If the write port is in READ_FIRST mode, there is no collision + if (C_WRITE_MODE_A=="READ_FIRST" && wea_i && !web_i) begin + is_collision = 0; + end + if (C_WRITE_MODE_B=="READ_FIRST" && web_i && !wea_i) begin + is_collision = 0; + end + + // Only flag if one of the accesses is a write + if (is_collision && (wea_i || web_i)) begin + $fwrite(collfile, "%0s collision detected at time: %0d, ", + C_CORENAME, $time); + $fwrite(collfile, "A %0s address: %0h, B %0s address: %0h\n", + wea_i ? "write" : "read", ADDRA, + web_i ? "write" : "read", ADDRB); + end + end + + // Asynchronous collision checks + end else if (!C_DISABLE_WARN_BHV_COLL && !C_COMMON_CLK) begin : async_coll + + // Delay A and B addresses in order to mimic setup/hold times + wire [C_ADDRA_WIDTH-1:0] #coll_delay addra_delay = ADDRA; + wire [0:0] #coll_delay wea_delay = wea_i; + wire #coll_delay ena_delay = ena_i; + wire [C_ADDRB_WIDTH-1:0] #coll_delay addrb_delay = ADDRB; + wire [0:0] #coll_delay web_delay = web_i; + wire #coll_delay enb_delay = enb_i; + + // Do the checks w/rt A + always @(posedge CLKA) begin + // Possible collision if both are enabled and the addresses match + if (ena_i && enb_i) begin + is_collision_a = collision_check(ADDRA, wea_i, ADDRB, web_i); + end else begin + is_collision_a = 0; + end + if (ena_i && enb_delay) begin + is_collision_delay_a = collision_check(ADDRA, wea_i, + addrb_delay, web_delay); + end else begin + is_collision_delay_a = 0; + end + + + // Only flag if B access is a write + if (is_collision_a && web_i) begin + $fwrite(collfile, "%0s collision detected at time: %0d, ", + C_CORENAME, $time); + $fwrite(collfile, "A %0s address: %0h, B write address: %0h\n", + wea_i ? "write" : "read", ADDRA, ADDRB); + + end else if (is_collision_delay_a && web_delay) begin + $fwrite(collfile, "%0s collision detected at time: %0d, ", + C_CORENAME, $time); + $fwrite(collfile, "A %0s address: %0h, B write address: %0h\n", + wea_i ? "write" : "read", ADDRA, addrb_delay); + end + + end + + // Do the checks w/rt B + always @(posedge CLKB) begin + + // Possible collision if both are enabled and the addresses match + if (ena_i && enb_i) begin + is_collision_b = collision_check(ADDRA, wea_i, ADDRB, web_i); + end else begin + is_collision_b = 0; + end + if (ena_delay && enb_i) begin + is_collision_delay_b = collision_check(addra_delay, wea_delay, + ADDRB, web_i); + end else begin + is_collision_delay_b = 0; + end + + + // Only flag if A access is a write + if (is_collision_b && wea_i) begin + $fwrite(collfile, "%0s collision detected at time: %0d, ", + C_CORENAME, $time); + $fwrite(collfile, "A write address: %0h, B %s address: %0h\n", + ADDRA, web_i ? "write" : "read", ADDRB); + + end else if (is_collision_delay_b && wea_delay) begin + $fwrite(collfile, "%0s collision detected at time: %0d, ", + C_CORENAME, $time); + $fwrite(collfile, "A write address: %0h, B %s address: %0h\n", + addra_delay, web_i ? "write" : "read", ADDRB); + end + + end + end + endgenerate + +endmodule diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/BLK_MEM_GEN_V2_1_xst.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/BLK_MEM_GEN_V2_1_xst.v new file mode 100644 index 0000000..27fc591 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/BLK_MEM_GEN_V2_1_xst.v @@ -0,0 +1,183 @@ +/****************************************************************************** + * + * Block Memory Generator Core - Block Memory Behavioral Model + * + * Copyright(C) 2005 by Xilinx, Inc. All rights reserved. + * This text/file contains proprietary, confidential + * information of Xilinx, Inc., is distributed under + * license from Xilinx, Inc., and may be used, copied + * and/or disclosed only pursuant to the terms of a valid + * license agreement with Xilinx, Inc. Xilinx hereby + * grants you a license to use this text/file solely for + * design, simulation, implementation and creation of + * design files limited to Xilinx devices or technologies. + * Use with non-Xilinx devices or technologies is expressly + * prohibited and immediately terminates your license unless + * covered by a separate agreement. + * + * Xilinx is providing this design, code, or information + * "as-is" solely for use in developing programs and + * solutions for Xilinx devices, with no obligation on the + * part of Xilinx to provide support. By providing this design, + * code, or information as one possible implementation of + * this feature, application or standard, Xilinx is making no + * representation that this implementation is free from any + * claims of infringement. You are responsible for obtaining + * any rights you may require for your implementation. + * Xilinx expressly disclaims any warranty whatsoever with + * respect to the adequacy of the implementation, including + * but not limited to any warranties or representations that this + * implementation is free from claims of infringement, implied + * warranties of merchantability or fitness for a particular + * purpose. + * + * Xilinx products are not intended for use in life support + * appliances, devices, or systems. Use in such applications is + * expressly prohibited. + * + * Any modifications that are made to the Source Code are + * done at the user's sole risk and will be unsupported. + * The Xilinx Support Hotline does not have access to source + * code and therefore cannot answer specific questions related + * to source HDL. The Xilinx Hotline support of original source + * code IP shall only address issues and questions related + * to the standard Netlist version of the core (and thus + * indirectly, the original core source). + * + * This copyright and support notice must be retained as part + * of this text at all times. (c) Copyright 1995-2005 Xilinx, Inc. + * All rights reserved. + * + ***************************************************************************** + * + * Filename: BLK_MEM_GEN_V2_1.v + * + * Description: + * This file is the Verilog behvarial model for the + * Block Memory Generator Core. + * + ***************************************************************************** + * Author: Xilinx + * + * History: September 6, 2005 Initial revision + *****************************************************************************/ +`timescale 1ps/1ps + +module BLK_MEM_GEN_V2_1_xst + #(parameter C_ADDRA_WIDTH = 5, + parameter C_ADDRB_WIDTH = 5, + parameter C_ALGORITHM = 1, + parameter C_BYTE_SIZE = 9, + parameter C_COMMON_CLK = 1, + parameter C_DEFAULT_DATA = "0", + parameter C_DISABLE_WARN_BHV_COLL = 0, + parameter C_DISABLE_WARN_BHV_RANGE = 0, + parameter C_FAMILY = "virtex5", + parameter C_HAS_ENA = 1, + parameter C_HAS_ENB = 1, + parameter C_HAS_MEM_OUTPUT_REGS = 0, + parameter C_HAS_MUX_OUTPUT_REGS = 0, + parameter C_HAS_REGCEA = 0, + parameter C_HAS_REGCEB = 0, + parameter C_HAS_SSRA = 0, + parameter C_HAS_SSRB = 0, + parameter C_INIT_FILE_NAME = "", + parameter C_LOAD_INIT_FILE = 0, + parameter C_MEM_TYPE = 2, + parameter C_PRIM_TYPE = 3, + parameter C_READ_DEPTH_A = 64, + parameter C_READ_DEPTH_B = 64, + parameter C_READ_WIDTH_A = 32, + parameter C_READ_WIDTH_B = 32, + parameter C_SIM_COLLISION_CHECK = "NONE", + parameter C_SINITA_VAL = "0", + parameter C_SINITB_VAL = "0", + parameter C_USE_BYTE_WEA = 0, + parameter C_USE_BYTE_WEB = 0, + parameter C_USE_DEFAULT_DATA = 0, + parameter C_WEA_WIDTH = 1, + parameter C_WEB_WIDTH = 1, + parameter C_WRITE_DEPTH_A = 64, + parameter C_WRITE_DEPTH_B = 64, + parameter C_WRITE_MODE_A = "WRITE_FIRST", + parameter C_WRITE_MODE_B = "WRITE_FIRST", + parameter C_WRITE_WIDTH_A = 32, + parameter C_WRITE_WIDTH_B = 32) + (input CLKA, + input [C_WRITE_WIDTH_A-1:0] DINA, + input [C_ADDRA_WIDTH-1:0] ADDRA, + input ENA, + input REGCEA, + input [C_WEA_WIDTH-1:0] WEA, + input SSRA, + output [C_READ_WIDTH_A-1:0] DOUTA, + input CLKB, + input [C_WRITE_WIDTH_B-1:0] DINB, + input [C_ADDRB_WIDTH-1:0] ADDRB, + input ENB, + input REGCEB, + input [C_WEB_WIDTH-1:0] WEB, + input SSRB, + output [C_READ_WIDTH_B-1:0] DOUTB); + + BLK_MEM_GEN_V2_1 + #(.C_FAMILY (C_FAMILY), + .C_MEM_TYPE (C_MEM_TYPE), + .C_ALGORITHM (C_ALGORITHM), + .C_PRIM_TYPE (C_PRIM_TYPE), + .C_BYTE_SIZE (C_BYTE_SIZE), + .C_COMMON_CLK (C_COMMON_CLK), + .C_SIM_COLLISION_CHECK (C_SIM_COLLISION_CHECK), + .C_DISABLE_WARN_BHV_COLL (C_DISABLE_WARN_BHV_COLL), + .C_DISABLE_WARN_BHV_RANGE (C_DISABLE_WARN_BHV_RANGE), + .C_LOAD_INIT_FILE (C_LOAD_INIT_FILE), + .C_INIT_FILE_NAME (C_INIT_FILE_NAME), + .C_USE_DEFAULT_DATA (C_USE_DEFAULT_DATA), + .C_DEFAULT_DATA (C_DEFAULT_DATA), + .C_HAS_MEM_OUTPUT_REGS (C_HAS_MEM_OUTPUT_REGS), + .C_HAS_MUX_OUTPUT_REGS (C_HAS_MUX_OUTPUT_REGS), + .C_WRITE_WIDTH_A (C_WRITE_WIDTH_A), + .C_READ_WIDTH_A (C_READ_WIDTH_A), + .C_WRITE_DEPTH_A (C_WRITE_DEPTH_A), + .C_READ_DEPTH_A (C_READ_DEPTH_A), + .C_ADDRA_WIDTH (C_ADDRA_WIDTH), + .C_WRITE_MODE_A (C_WRITE_MODE_A), + .C_HAS_ENA (C_HAS_ENA), + .C_HAS_REGCEA (C_HAS_REGCEA), + .C_HAS_SSRA (C_HAS_SSRA), + .C_SINITA_VAL (C_SINITA_VAL), + .C_USE_BYTE_WEA (C_USE_BYTE_WEA), + .C_WEA_WIDTH (C_WEA_WIDTH), + .C_WRITE_WIDTH_B (C_WRITE_WIDTH_B), + .C_READ_WIDTH_B (C_READ_WIDTH_B), + .C_WRITE_DEPTH_B (C_WRITE_DEPTH_B), + .C_READ_DEPTH_B (C_READ_DEPTH_B), + .C_ADDRB_WIDTH (C_ADDRB_WIDTH), + .C_WRITE_MODE_B (C_WRITE_MODE_B), + .C_HAS_ENB (C_HAS_ENB), + .C_HAS_REGCEB (C_HAS_REGCEB), + .C_HAS_SSRB (C_HAS_SSRB), + .C_SINITB_VAL (C_SINITB_VAL), + .C_USE_BYTE_WEB (C_USE_BYTE_WEB), + .C_WEB_WIDTH (C_WEB_WIDTH) + ) blk_mem_gen_v2_1_dut ( + .DINA (DINA), + .DINB (DINB), + .ADDRA (ADDRA), + .ADDRB (ADDRB), + .ENA (ENA), + .ENB (ENB), + .REGCEA (REGCEA), + .REGCEB (REGCEB), + .WEA (WEA), + .WEB (WEB), + .SSRA (SSRA), + .SSRB (SSRB), + .CLKA (CLKA), + .CLKB (CLKB), + .DOUTA (DOUTA), + .DOUTB (DOUTB) +); + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/BLK_MEM_GEN_V2_2.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/BLK_MEM_GEN_V2_2.v new file mode 100644 index 0000000..def1f47 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/BLK_MEM_GEN_V2_2.v @@ -0,0 +1,1054 @@ +/****************************************************************************** + * + * Block Memory Generator Core - Block Memory Behavioral Model + * + * Copyright(C) 2005 by Xilinx, Inc. All rights reserved. + * This text/file contains proprietary, confidential + * information of Xilinx, Inc., is distributed under + * license from Xilinx, Inc., and may be used, copied + * and/or disclosed only pursuant to the terms of a valid + * license agreement with Xilinx, Inc. Xilinx hereby + * grants you a license to use this text/file solely for + * design, simulation, implementation and creation of + * design files limited to Xilinx devices or technologies. + * Use with non-Xilinx devices or technologies is expressly + * prohibited and immediately terminates your license unless + * covered by a separate agreement. + * + * Xilinx is providing this design, code, or information + * "as-is" solely for use in developing programs and + * solutions for Xilinx devices, with no obligation on the + * part of Xilinx to provide support. By providing this design, + * code, or information as one possible implementation of + * this feature, application or standard, Xilinx is making no + * representation that this implementation is free from any + * claims of infringement. You are responsible for obtaining + * any rights you may require for your implementation. + * Xilinx expressly disclaims any warranty whatsoever with + * respect to the adequacy of the implementation, including + * but not limited to any warranties or representations that this + * implementation is free from claims of infringement, implied + * warranties of merchantability or fitness for a particular + * purpose. + * + * Xilinx products are not intended for use in life support + * appliances, devices, or systems. Use in such applications is + * expressly prohibited. + * + * Any modifications that are made to the Source Code are + * done at the user's sole risk and will be unsupported. + * The Xilinx Support Hotline does not have access to source + * code and therefore cannot answer specific questions related + * to source HDL. The Xilinx Hotline support of original source + * code IP shall only address issues and questions related + * to the standard Netlist version of the core (and thus + * indirectly, the original core source). + * + * This copyright and support notice must be retained as part + * of this text at all times. (c) Copyright 1995-2005 Xilinx, Inc. + * All rights reserved. + * + ***************************************************************************** + * + * Filename: BLK_MEM_GEN_V2_2.v + * + * Description: + * This file is the Verilog behvarial model for the + * Block Memory Generator Core. + * + ***************************************************************************** + * Author: Xilinx + * + * History: January 11, 2006 Initial revision + *****************************************************************************/ +`timescale 1ps/1ps + +module BLK_MEM_GEN_V2_2_output_stage + #(parameter C_DATA_WIDTH = 32, + parameter C_HAS_SSR = 1, + parameter C_SINIT_VAL = "0", + parameter C_HAS_REGCE = 1, + parameter C_HAS_EN = 1, + parameter C_FAMILY = "virtex5", + parameter num_stages = 1, + parameter flop_delay = 100) + (input CLK, + input SSR, + input REGCE, + input EN, + input [C_DATA_WIDTH-1:0] DIN, + output reg [C_DATA_WIDTH-1:0] DOUT); + + localparam reg_stages = (num_stages == 0) ? 0 : num_stages-1; + reg [C_DATA_WIDTH*reg_stages-1:0] out_regs; + reg [C_DATA_WIDTH*8-1:0] sinit_str = C_SINIT_VAL; + reg [C_DATA_WIDTH-1:0] sinit_val; + + // Wire off optional inputs based on parameters + //--------------------------------------------- + wire en_i; + wire regce_i; + wire ssr_i; + assign en_i = (C_HAS_EN==0 || EN); + assign regce_i = ((C_HAS_REGCE==1) && REGCE) || + ((C_HAS_REGCE==0) && (C_HAS_EN==0 || EN)); + assign ssr_i = (C_HAS_SSR==1) && SSR; + + initial begin + // Power on: load up the output registers and latches + if (!($sscanf(sinit_str, "%h", sinit_val))) begin + sinit_val = 0; + end + DOUT = sinit_val; + // This will be one wider than need, but 0 is an error + out_regs = {(reg_stages+1){sinit_val}}; + end + + generate if (num_stages == 0) begin : zero_stages + always @* begin + DOUT = DIN; + end + end + endgenerate + + generate if (num_stages == 1) begin : one_stages + always @(posedge CLK) begin + if (regce_i && ssr_i) begin + DOUT <= #flop_delay sinit_val; + end else if (regce_i) begin + DOUT <= #flop_delay DIN; + end + end + end + endgenerate + + generate if (num_stages > 1) begin : multi_stage + always @(posedge CLK) begin + if (regce_i && ssr_i) begin + DOUT <= #flop_delay sinit_val; + end else if (regce_i) begin + DOUT <= #flop_delay + out_regs[C_DATA_WIDTH*(num_stages-2)+:C_DATA_WIDTH]; + end + + if (en_i) begin + out_regs <= #flop_delay + (out_regs << C_DATA_WIDTH) | DIN; + end + end + end + endgenerate +endmodule + +module BLK_MEM_GEN_V2_2 + #(parameter C_ADDRA_WIDTH = 5, + parameter C_ADDRB_WIDTH = 5, + parameter C_ALGORITHM = 2, + parameter C_BYTE_SIZE = 8, + parameter C_COMMON_CLK = 1, + parameter C_DEFAULT_DATA = "0", + parameter C_DISABLE_WARN_BHV_COLL = 0, + parameter C_DISABLE_WARN_BHV_RANGE = 0, + parameter C_FAMILY = "virtex4", + parameter C_HAS_ENA = 1, + parameter C_HAS_ENB = 1, + parameter C_HAS_MEM_OUTPUT_REGS = 0, + parameter C_HAS_MUX_OUTPUT_REGS = 0, + parameter C_HAS_REGCEA = 0, + parameter C_HAS_REGCEB = 0, + parameter C_HAS_SSRA = 0, + parameter C_HAS_SSRB = 0, + parameter C_INIT_FILE_NAME = "", + parameter C_LOAD_INIT_FILE = 0, + parameter C_MEM_TYPE = 2, + parameter C_PRIM_TYPE = 3, + parameter C_READ_DEPTH_A = 64, + parameter C_READ_DEPTH_B = 64, + parameter C_READ_WIDTH_A = 32, + parameter C_READ_WIDTH_B = 32, + parameter C_SIM_COLLISION_CHECK = "NONE", + parameter C_SINITA_VAL = "0", + parameter C_SINITB_VAL = "0", + parameter C_USE_BYTE_WEA = 0, + parameter C_USE_BYTE_WEB = 0, + parameter C_USE_DEFAULT_DATA = 0, + parameter C_USE_ECC = 0, + parameter C_WEA_WIDTH = 1, + parameter C_WEB_WIDTH = 1, + parameter C_WRITE_DEPTH_A = 64, + parameter C_WRITE_DEPTH_B = 64, + parameter C_WRITE_MODE_A = "WRITE_FIRST", + parameter C_WRITE_MODE_B = "WRITE_FIRST", + parameter C_WRITE_WIDTH_A = 32, + parameter C_WRITE_WIDTH_B = 32, + parameter C_CORENAME = "blk_mem_gen_v2_2") + (input CLKA, + input [C_WRITE_WIDTH_A-1:0] DINA, + input [C_ADDRA_WIDTH-1:0] ADDRA, + input ENA, + input REGCEA, + input [C_WEA_WIDTH-1:0] WEA, + input SSRA, + output [C_READ_WIDTH_A-1:0] DOUTA, + input CLKB, + input [C_WRITE_WIDTH_B-1:0] DINB, + input [C_ADDRB_WIDTH-1:0] ADDRB, + input ENB, + input REGCEB, + input [C_WEB_WIDTH-1:0] WEB, + input SSRB, + output [C_READ_WIDTH_B-1:0] DOUTB, + output DBITERR, + output SBITERR + ); + + // constants for the core behavior + //================================ + // file handles for logging + //------------------------------------------------------ + localparam addrfile = 32'h8000_0001; // stdout for addr out of range + localparam collfile = 32'h8000_0001; // stdout for coll detection + localparam errfile = 32'h8000_0001; // stdout for file I/O errors + + // other constants + //------------------------------------------------------ + localparam coll_delay = 2000; // 2 ns + + // locally derived parameters to determine memory shape + //----------------------------------------------------- + localparam min_width_a = (C_WRITE_WIDTH_A < C_READ_WIDTH_A) ? + C_WRITE_WIDTH_A : C_READ_WIDTH_A; + localparam min_width_b = (C_WRITE_WIDTH_B < C_READ_WIDTH_B) ? + C_WRITE_WIDTH_B : C_READ_WIDTH_B; + localparam min_width = (min_width_a < min_width_b) ? + min_width_a : min_width_b; + + localparam max_width_a = (C_WRITE_WIDTH_A > C_READ_WIDTH_A) ? + C_WRITE_WIDTH_A : C_READ_WIDTH_A; + localparam max_width_b = (C_WRITE_WIDTH_B > C_READ_WIDTH_B) ? + C_WRITE_WIDTH_B : C_READ_WIDTH_B; + localparam max_width = (max_width_a > max_width_b) ? + max_width_a : max_width_b; + + localparam max_depth_a = (C_WRITE_DEPTH_A > C_READ_DEPTH_A) ? + C_WRITE_DEPTH_A : C_READ_DEPTH_A; + localparam max_depth_b = (C_WRITE_DEPTH_B > C_READ_DEPTH_B) ? + C_WRITE_DEPTH_B : C_READ_DEPTH_B; + localparam max_depth = (max_depth_a > max_depth_b) ? + max_depth_a : max_depth_b; + + + // locally derived parameters to assist memory access + //---------------------------------------------------- + localparam write_width_ratio_a = C_WRITE_WIDTH_A/min_width; + localparam read_width_ratio_a = C_READ_WIDTH_A/min_width; + localparam write_width_ratio_b = C_WRITE_WIDTH_B/min_width; + localparam read_width_ratio_b = C_READ_WIDTH_B/min_width; + + // To modify the LSBs of the 'wider' data to the actual + // address value + //---------------------------------------------------- + localparam write_addr_a_div = C_WRITE_WIDTH_A/min_width_a; + localparam read_addr_a_div = C_READ_WIDTH_A/min_width_a; + localparam write_addr_b_div = C_WRITE_WIDTH_B/min_width_b; + localparam read_addr_b_div = C_READ_WIDTH_B/min_width_b; + + // If byte writes aren't being used, make sure byte_size is not + // wider than the memory elements to avoid compilation warnings + localparam byte_size = (C_BYTE_SIZE < min_width) ? C_BYTE_SIZE : min_width; + + // the memory + reg [min_width-1:0] memory [0:max_depth-1]; + // memory output 'latches' + reg [C_READ_WIDTH_A-1:0] memory_out_a; + reg [C_READ_WIDTH_B-1:0] memory_out_b; + // reset values + reg [C_READ_WIDTH_A-1:0] sinita_val; + reg [C_READ_WIDTH_B-1:0] sinitb_val; + + // collision detect + reg is_collision; + reg is_collision_a, is_collision_delay_a; + reg is_collision_b, is_collision_delay_b; + + // temporary variables for initialization + //--------------------------------------- + integer status; + reg [639:0] err_str; + integer initfile; + // data input buffer + reg [C_WRITE_WIDTH_A-1:0] mif_data; + // string values in hex + reg [C_READ_WIDTH_A*8-1:0] sinita_str = C_SINITA_VAL; + reg [C_READ_WIDTH_B*8-1:0] sinitb_str = C_SINITB_VAL; + reg [C_WRITE_WIDTH_A*8-1:0] default_data_str = C_DEFAULT_DATA; + // initialization filename + reg [1023*8-1:0] init_file_str = C_INIT_FILE_NAME; + + // internal configuration parameters + //--------------------------------------------- + localparam flop_delay = 100; // 100 ps + localparam single_port = (C_MEM_TYPE==0 || C_MEM_TYPE==3); + localparam is_rom = (C_MEM_TYPE==3 || C_MEM_TYPE==4); + localparam has_a_write = (!is_rom); + localparam has_b_write = (C_MEM_TYPE==2); + localparam has_a_read = (C_MEM_TYPE!=1); + localparam has_b_read = (!single_port); + localparam has_b_port = (has_b_read || has_b_write); + localparam num_output_stages = C_HAS_MEM_OUTPUT_REGS + + C_HAS_MUX_OUTPUT_REGS; + + wire ena_i; + wire enb_i; + wire reseta_i; + wire resetb_i; + wire [C_WEA_WIDTH-1:0] wea_i; + wire [C_WEB_WIDTH-1:0] web_i; + wire rea_i; + wire reb_i; + assign ena_i = (C_HAS_ENA==0) || ENA; + assign enb_i = ((C_HAS_ENB==0) || ENB) && has_b_port; + assign reseta_i = (C_HAS_SSRA==1) && SSRA && ena_i && + (num_output_stages==0); + assign resetb_i = (C_HAS_SSRB==1) && SSRB && enb_i && + (num_output_stages==0); + assign wea_i = (has_a_write && ena_i) ? WEA : 'b0; + assign web_i = (has_b_write && enb_i) ? WEB : 'b0; + assign rea_i = (has_a_read) ? ena_i : 'b0; + assign reb_i = (has_b_read) ? enb_i : 'b0; + + // tasks to access the memory + //--------------------------- + task write_a + (input reg [C_ADDRA_WIDTH-1:0] addr, + input reg [C_WEA_WIDTH-1:0] byte_en, + input reg [C_WRITE_WIDTH_A-1:0] data); + reg [C_WRITE_WIDTH_A-1:0] current_contents; + reg [C_ADDRA_WIDTH-1:0] address; + integer i; + begin + // Shift the address by the ratio + address = (addr/write_addr_a_div); + if (address >= C_WRITE_DEPTH_A) begin + if (!C_DISABLE_WARN_BHV_RANGE) begin + $fdisplay(addrfile, + "%0s WARNING: Address %0h is outside range for A Write", + C_CORENAME, addr); + end + + // valid address + end else begin + + // Combine w/ byte writes + if (C_USE_BYTE_WEA) begin + + // Get the current memory contents + if (write_width_ratio_a == 1) begin + // Workaround for IUS 5.5 part-select issue + current_contents = memory[address]; + end else begin + for (i = 0; i < write_width_ratio_a; i = i + 1) begin + current_contents[min_width*i+:min_width] + = memory[address*write_width_ratio_a + i]; + end + end + + // Apply incoming bytes + if (C_WEA_WIDTH == 1) begin + // Workaround for IUS 5.5 part-select issue + if (byte_en[0]) begin + current_contents = data; + end + end else begin + for (i = 0; i < C_WEA_WIDTH; i = i + 1) begin + if (byte_en[i]) begin + current_contents[byte_size*i+:byte_size] + = data[byte_size*i+:byte_size]; + end + end + end + + // No byte-writes, overwrite the whole word + end else begin + current_contents = data; + end + + // Write data to memory + if (write_width_ratio_a == 1) begin + // Workaround for IUS 5.5 part-select issue + memory[address*write_width_ratio_a] = current_contents; + end else begin + for (i = 0; i < write_width_ratio_a; i = i + 1) begin + memory[address*write_width_ratio_a + i] + = current_contents[min_width*i+:min_width]; + end + end + + end + end + endtask + + task write_b + (input reg [C_ADDRB_WIDTH-1:0] addr, + input reg [C_WEB_WIDTH-1:0] byte_en, + input reg [C_WRITE_WIDTH_B-1:0] data); + reg [C_WRITE_WIDTH_B-1:0] current_contents; + reg [C_ADDRB_WIDTH-1:0] address; + integer i; + begin + // Shift the address by the ratio + address = (addr/write_addr_b_div); + if (address >= C_WRITE_DEPTH_B) begin + if (!C_DISABLE_WARN_BHV_RANGE) begin + $fdisplay(addrfile, + "%0s WARNING: Address %0h is outside range for B Write", + C_CORENAME, addr); + end + + // valid address + end else begin + + // Combine w/ byte writes + if (C_USE_BYTE_WEB) begin + + // Get the current memory contents + if (write_width_ratio_b == 1) begin + // Workaround for IUS 5.5 part-select issue + current_contents = memory[address]; + end else begin + for (i = 0; i < write_width_ratio_b; i = i + 1) begin + current_contents[min_width*i+:min_width] + = memory[address*write_width_ratio_b + i]; + end + end + + // Apply incoming bytes + if (C_WEB_WIDTH == 1) begin + // Workaround for IUS 5.5 part-select issue + if (byte_en[0]) begin + current_contents = data; + end + end else begin + for (i = 0; i < C_WEB_WIDTH; i = i + 1) begin + if (byte_en[i]) begin + current_contents[byte_size*i+:byte_size] + = data[byte_size*i+:byte_size]; + end + end + end + + // No byte-writes, overwrite the whole word + end else begin + current_contents = data; + end + + // Write data to memory + if (write_width_ratio_b == 1) begin + // Workaround for IUS 5.5 part-select issue + memory[address*write_width_ratio_b] = current_contents; + end else begin + for (i = 0; i < write_width_ratio_b; i = i + 1) begin + memory[address*write_width_ratio_b + i] + = current_contents[min_width*i+:min_width]; + end + end + end + end + endtask + + task read_a + (input reg [C_ADDRA_WIDTH-1:0] addr, + input reg reset); + reg [C_ADDRA_WIDTH-1:0] address; + integer i; + begin + + if (reset) begin + memory_out_a <= #flop_delay sinita_val; + end else begin + // Shift the address by the ratio + address = (addr/read_addr_a_div); + if (address >= C_READ_DEPTH_A) begin + if (!C_DISABLE_WARN_BHV_RANGE) begin + $fdisplay(addrfile, + "%0s WARNING: Address %0h is outside range for A Read", + C_CORENAME, addr); + end + + // valid address + end else begin + + if (read_width_ratio_a==1) begin + memory_out_a <= #flop_delay memory[address*read_width_ratio_a]; + end else begin + // Increment through the 'partial' words in the memory + for (i = 0; i < read_width_ratio_a; i = i + 1) begin + memory_out_a[min_width*i+:min_width] + <= #flop_delay memory[address*read_width_ratio_a + i]; + end + end + + end + end + end + endtask + + task read_b + (input reg [C_ADDRB_WIDTH-1:0] addr, + input reg reset); + reg [C_ADDRB_WIDTH-1:0] address; + integer i; + begin + + if (reset) begin + memory_out_b <= #flop_delay sinitb_val; + end else begin + // Shift the address + address = (addr/read_addr_b_div); + if (address >= C_READ_DEPTH_B) begin + if (!C_DISABLE_WARN_BHV_RANGE) begin + $fdisplay(addrfile, + "%0s WARNING: Address %0h is outside range for B Read", + C_CORENAME, addr); + end + + // valid address + end else begin + + if (read_width_ratio_b==1) begin + memory_out_b <= #flop_delay memory[address*read_width_ratio_b]; + end else begin + // Increment through the 'partial' words in the memory + for (i = 0; i < read_width_ratio_b; i = i + 1) begin + memory_out_b[min_width*i+:min_width] + <= #flop_delay memory[address*read_width_ratio_b + i]; + end + end + + end + end + end + endtask + + task init_memory; + integer i, addr_step; + integer status; + reg [C_WRITE_WIDTH_A-1:0] default_data; + begin + default_data = 0; + + // Convert the default to hex + if (C_USE_DEFAULT_DATA) begin + if (default_data_str == "") begin + $fdisplay(errfile, "%0s ERROR: C_DEFAULT_DATA is empty!", C_CORENAME); + $finish; + end else begin + status = $sscanf(default_data_str, "%h", default_data); + if (status == 0) begin + $fdisplay(errfile, {"%0s ERROR: Unsuccessful hexadecimal read", + "from C_DEFAULT_DATA: %0s"}, + C_CORENAME, C_DEFAULT_DATA); + $finish; + end + end + end + + // Step by write_addr_a_div through the memory via the + // Port A write interface to hit every location once + addr_step = write_addr_a_div; + + // 'write' to every location with default (or 0) + for (i = 0; i < C_WRITE_DEPTH_A*addr_step; i = i + addr_step) begin + write_a(i, {C_WEA_WIDTH{1'b1}}, default_data); + end + + // Get specialized data from the MIF file + if (C_LOAD_INIT_FILE) begin + if (init_file_str == "") begin + $fdisplay(errfile, "%0s ERROR: C_INIT_FILE_NAME is empty!", + C_CORENAME); + $finish; + end else begin + initfile = $fopen(init_file_str, "r"); + if (initfile == 0) begin + $fdisplay(errfile, {"%0s, ERROR: Problem opening", + "C_INIT_FILE_NAME: %0s!"}, + C_CORENAME, init_file_str); + $finish; + end else begin + // loop through the mif file, loading in the data + for (i = 0; i < C_WRITE_DEPTH_A*addr_step; i = i + addr_step) begin + status = $fscanf(initfile, "%b", mif_data); + if (status > 0) begin + write_a(i, {C_WEA_WIDTH{1'b1}}, mif_data); + end + end + $fclose(initfile); + end + end + end + end + endtask + + function integer log2roundup (input integer data_value); + integer width; + integer cnt; + begin + width = 0; + + if (data_value > 1) begin + for(cnt=1 ; cnt < data_value ; cnt = cnt * 2) begin + width = width + 1; + end //loop + end //if + + log2roundup = width; + + end //log2roundup + endfunction + + + + function integer collision_check (input reg [C_ADDRA_WIDTH-1:0] addr_a, + input integer iswrite_a, + input reg [C_ADDRB_WIDTH-1:0] addr_b, + input integer iswrite_b); + reg [C_ADDRA_WIDTH-1:0] base_addr_a; + reg [C_ADDRB_WIDTH-1:0] base_addr_b; + integer ratio_a, ratio_b; + integer lo_addr_wider, hi_addr_wider; + integer lo_addr_narrow, hi_addr_narrow; + reg c_aw_bw, c_aw_br, c_ar_bw; + integer write_addr_a_width, read_addr_a_width; + integer write_addr_b_width, read_addr_b_width; + + begin + + c_aw_bw = 0; + c_aw_br = 0; + c_ar_bw = 0; + + // Determine the effective address widths for each of the 4 ports + write_addr_a_width = C_ADDRA_WIDTH-log2roundup(write_addr_a_div); + read_addr_a_width = C_ADDRA_WIDTH-log2roundup(read_addr_a_div); + write_addr_b_width = C_ADDRB_WIDTH-log2roundup(write_addr_b_div); + read_addr_b_width = C_ADDRB_WIDTH-log2roundup(read_addr_b_div); + + + //Look for a write-write collision. In order for a write-write + //collision to exist, both ports must have a write transaction. + if (iswrite_a && iswrite_b) begin + if (write_addr_a_width > write_addr_b_width) begin + //write_addr_b_width is smaller, so scale both addresses to that + // width for comparing write_addr_a and write_addr_b + //addr_a starts as C_ADDRA_WIDTH, + // scale it down to write_addr_b_width + //addr_b starts as C_ADDRB_WIDTH, + // scale it down to write_addr_b_width + //Once both are scaled to write_addr_b_width, compare. + if (((addr_a)/2**(C_ADDRA_WIDTH-write_addr_b_width)) == ((addr_b)/2**(C_ADDRB_WIDTH-write_addr_b_width))) begin + c_aw_bw = 1; + end else begin + c_aw_bw = 0; + end + end else begin + //write_addr_a_width is smaller, so scale both addresses to that + // width for comparing write_addr_a and write_addr_b + //addr_a starts as C_ADDRA_WIDTH, + // scale it down to write_addr_a_width + //addr_b starts as C_ADDRB_WIDTH, + // scale it down to write_addr_a_width + //Once both are scaled to write_addr_a_width, compare. + if (((addr_b)/2**(C_ADDRB_WIDTH-write_addr_a_width)) == ((addr_a)/2**(C_ADDRA_WIDTH-write_addr_a_width))) begin + c_aw_bw = 1; + end else begin + c_aw_bw = 0; + end + end //width + end //iswrite_a and iswrite_b + + //If the B port is reading (which means it is enabled - so could be + // a TX_WRITE or TX_READ), then check for a write-read collision). + //This could happen whether or not a write-write collision exists due + // to asymmetric write/read ports. + if (iswrite_a) begin + if (write_addr_a_width > read_addr_b_width) begin + //read_addr_b_width is smaller, so scale both addresses to that + // width for comparing write_addr_a and read_addr_b + //addr_a starts as C_ADDRA_WIDTH, + // scale it down to read_addr_b_width + //addr_b starts as C_ADDRB_WIDTH, + // scale it down to read_addr_b_width + //Once both are scaled to read_addr_b_width, compare. + if (((addr_a)/2**(C_ADDRA_WIDTH-read_addr_b_width)) == ((addr_b)/2**(C_ADDRB_WIDTH-read_addr_b_width))) begin + c_aw_br = 1; + end else begin + c_aw_br = 0; + end + end else begin + //write_addr_a_width is smaller, so scale both addresses to that + // width for comparing write_addr_a and read_addr_b + //addr_a starts as C_ADDRA_WIDTH, + // scale it down to write_addr_a_width + //addr_b starts as C_ADDRB_WIDTH, + // scale it down to write_addr_a_width + //Once both are scaled to write_addr_a_width, compare. + if (((addr_b)/2**(C_ADDRB_WIDTH-write_addr_a_width)) == ((addr_a)/2**(C_ADDRA_WIDTH-write_addr_a_width))) begin + c_aw_br = 1; + end else begin + c_aw_br = 0; + end + end //width + end //iswrite_a + + //If the A port is reading (which means it is enabled - so could be + // a TX_WRITE or TX_READ), then check for a write-read collision). + //This could happen whether or not a write-write collision exists due + // to asymmetric write/read ports. + if (iswrite_b) begin + if (read_addr_a_width > write_addr_b_width) begin + //write_addr_b_width is smaller, so scale both addresses to that + // width for comparing read_addr_a and write_addr_b + //addr_a starts as C_ADDRA_WIDTH, + // scale it down to write_addr_b_width + //addr_b starts as C_ADDRB_WIDTH, + // scale it down to write_addr_b_width + //Once both are scaled to write_addr_b_width, compare. + if (((addr_a)/2**(C_ADDRA_WIDTH-write_addr_b_width)) == ((addr_b)/2**(C_ADDRB_WIDTH-write_addr_b_width))) begin + c_ar_bw = 1; + end else begin + c_ar_bw = 0; + end + end else begin + //read_addr_a_width is smaller, so scale both addresses to that + // width for comparing read_addr_a and write_addr_b + //addr_a starts as C_ADDRA_WIDTH, + // scale it down to read_addr_a_width + //addr_b starts as C_ADDRB_WIDTH, + // scale it down to read_addr_a_width + //Once both are scaled to read_addr_a_width, compare. + if (((addr_b)/2**(C_ADDRB_WIDTH-read_addr_a_width)) == ((addr_a)/2**(C_ADDRA_WIDTH-read_addr_a_width))) begin + c_ar_bw = 1; + end else begin + c_ar_bw = 0; + end + end //width + end //iswrite_b + + + // Convert the input addresses in base and offsets for our + // memory array. Ignore LSBs for asymmetric ports + if (iswrite_a) begin + base_addr_a = (addr_a/write_addr_a_div) * write_addr_a_div; + ratio_a = write_width_ratio_a; + end else begin + base_addr_a = (addr_a/read_addr_a_div) * read_addr_a_div; + ratio_a = read_width_ratio_a; + end + if (iswrite_b) begin + base_addr_b = (addr_b/write_addr_b_div) * write_addr_b_div; + ratio_b = write_width_ratio_b; + end else begin + base_addr_b = (addr_b/read_addr_b_div) * read_addr_b_div; + ratio_b = read_width_ratio_b; + end + + // Determine the wider port, and normalized ranges + if (ratio_a >= ratio_b) begin + lo_addr_wider = base_addr_a * ratio_a; + hi_addr_wider = lo_addr_wider + ratio_a; + lo_addr_narrow = base_addr_b * ratio_b; + hi_addr_narrow = lo_addr_narrow + ratio_b; + end else begin + lo_addr_wider = base_addr_b * ratio_b; + hi_addr_wider = lo_addr_wider + ratio_b; + lo_addr_narrow = base_addr_a * ratio_a; + hi_addr_narrow = lo_addr_narrow + ratio_a; + end + + // compare the two ranges of address (narrow inside wider) + //if ((lo_addr_narrow >= lo_addr_wider) && + // (hi_addr_narrow <= hi_addr_wider)) begin + // collision_check = 1; + //end else begin + // collision_check = 0; + //end + + collision_check = c_aw_bw | c_aw_br | c_ar_bw; + + end + endfunction + + // power on values + //----------------------------- + initial begin + // Load up the memory + init_memory; + // Load up the output registers and latches + if ($sscanf(sinita_str, "%h", sinita_val)) begin + memory_out_a = sinita_val; + end else begin + memory_out_a = 0; + end + if ($sscanf(sinitb_str, "%h", sinitb_val)) begin + memory_out_b = sinitb_val; + end else begin + memory_out_b = 0; + end + + $display("Block Memory Generator CORE Generator module %m is using a behavioral model for simulation which will not precisely model memory collision behavior."); + + end + + //------------------------------------------------------------------------- + // These are the main blocks which schedule read and write operations + //------------------------------------------------------------------------- + + generate if (C_COMMON_CLK) begin : common_clk_scheduling + // Synchronous clocks: schedule port operations with respect to + // both write operating modes + always @(posedge CLKA) begin + case ({C_WRITE_MODE_A, C_WRITE_MODE_B}) + {"WRITE_FIRST","WRITE_FIRST"}: begin + if (wea_i) write_a(ADDRA, wea_i, DINA); + if (web_i) write_b(ADDRB, web_i, DINB); + if (rea_i) read_a(ADDRA, reseta_i); + if (reb_i) read_b(ADDRB, resetb_i); + end + {"READ_FIRST", "WRITE_FIRST"}: begin + if (web_i) write_b(ADDRB, web_i, DINB); + if (reb_i) read_b(ADDRB, resetb_i); + if (rea_i) read_a(ADDRA, reseta_i); + if (wea_i) write_a(ADDRA, wea_i, DINA); + end + {"WRITE_FIRST","READ_FIRST"}: begin + if (wea_i) write_a(ADDRA, wea_i, DINA); + if (rea_i) read_a(ADDRA, reseta_i); + if (reb_i) read_b(ADDRB, resetb_i); + if (web_i) write_b(ADDRB, web_i, DINB); + end + {"READ_FIRST", "READ_FIRST"}: begin + if (rea_i) read_a(ADDRA, reseta_i); + if (reb_i) read_b(ADDRB, resetb_i); + if (wea_i) write_a(ADDRA, wea_i, DINA); + if (web_i) write_b(ADDRB, web_i, DINB); + end + {"WRITE_FIRST","NO_CHANGE"}: begin + if (wea_i) write_a(ADDRA, wea_i, DINA); + if (rea_i) read_a(ADDRA, reseta_i); + if ((reb_i && !web_i) || resetb_i) read_b(ADDRB, resetb_i); + if (web_i) write_b(ADDRB, web_i, DINB); + end + {"READ_FIRST", "NO_CHANGE"}: begin + if (rea_i) read_a(ADDRA, reseta_i); + if ((reb_i && !web_i) || resetb_i) read_b(ADDRB, resetb_i); + if (wea_i) write_a(ADDRA, wea_i, DINA); + if (web_i) write_b(ADDRB, web_i, DINB); + end + {"NO_CHANGE", "WRITE_FIRST"}: begin + if (wea_i) write_a(ADDRA, wea_i, DINA); + if (web_i) write_b(ADDRB, web_i, DINB); + if ((rea_i && !wea_i) || reseta_i) read_a(ADDRA, reseta_i); + if (reb_i) read_b(ADDRB, resetb_i); + end + {"NO_CHANGE", "READ_FIRST"}: begin + if (reb_i) read_b(ADDRB, resetb_i); + if ((rea_i && !wea_i) || reseta_i) read_a(ADDRA, reseta_i); + if (wea_i) write_a(ADDRA, wea_i, DINA); + if (web_i) write_b(ADDRB, web_i, DINB); + end + {"NO_CHANGE", "NO_CHANGE"}: begin + if (wea_i) write_a(ADDRA, wea_i, DINA); + if (web_i) write_b(ADDRB, web_i, DINB); + if ((rea_i && !wea_i) || reseta_i) read_a(ADDRA, reseta_i); + if ((reb_i && !web_i) || resetb_i) read_b(ADDRB, resetb_i); + end + default: begin + if (wea_i) write_a(ADDRA, wea_i, DINA); + if (web_i) write_b(ADDRB, web_i, DINB); + if (rea_i) read_a(ADDRA, reseta_i); + if (reb_i) read_b(ADDRB, resetb_i); + end + endcase + end + + end else begin : asynch_clk_scheduling + // Asynchronous clocks: port operation is independent + always @(posedge CLKA) begin + case (C_WRITE_MODE_A) + "WRITE_FIRST": begin + if (wea_i) write_a(ADDRA, wea_i, DINA); + if (rea_i) read_a(ADDRA, reseta_i); + end + "READ_FIRST": begin + if (rea_i) read_a(ADDRA, reseta_i); + if (wea_i) write_a(ADDRA, wea_i, DINA); + end + "NO_CHANGE": begin + if (wea_i) write_a(ADDRA, wea_i, DINA); + if ((rea_i && !wea_i) || reseta_i) read_a(ADDRA, reseta_i); + end + endcase + end + + always @(posedge CLKB) begin + case (C_WRITE_MODE_B) + "WRITE_FIRST": begin + if (web_i) write_b(ADDRB, web_i, DINB); + if (reb_i) read_b(ADDRB, resetb_i); + end + "READ_FIRST": begin + if (reb_i) read_b(ADDRB, resetb_i); + if (web_i) write_b(ADDRB, web_i, DINB); + end + "NO_CHANGE": begin + if (web_i) write_b(ADDRB, web_i, DINB); + if ((reb_i && !web_i) || resetb_i) read_b(ADDRB, resetb_i); + end + endcase + end + end + endgenerate + + // Variable depth output stage + BLK_MEM_GEN_V2_2_output_stage + #(.C_DATA_WIDTH (C_READ_WIDTH_A), + .C_HAS_SSR (C_HAS_SSRA), + .C_SINIT_VAL (C_SINITA_VAL), + .C_HAS_REGCE (C_HAS_REGCEA), + .C_HAS_EN (C_HAS_ENA), + .C_FAMILY (C_FAMILY), + .num_stages (num_output_stages), + .flop_delay (flop_delay)) + reg_a + (.CLK (CLKA), + .SSR (SSRA), + .REGCE (REGCEA), + .EN (ENA), + .DIN (memory_out_a), + .DOUT (DOUTA)); + + BLK_MEM_GEN_V2_2_output_stage + #(.C_DATA_WIDTH (C_READ_WIDTH_B), + .C_HAS_SSR (C_HAS_SSRB), + .C_SINIT_VAL (C_SINITB_VAL), + .C_HAS_REGCE (C_HAS_REGCEB), + .C_HAS_EN (C_HAS_ENB), + .C_FAMILY (C_FAMILY), + .num_stages (num_output_stages), + .flop_delay (flop_delay)) + reg_b + (.CLK (CLKB), + .SSR (SSRB), + .REGCE (REGCEB), + .EN (ENB), + .DIN (memory_out_b), + .DOUT (DOUTB)); + + // Synchronous collision checks + generate if (!C_DISABLE_WARN_BHV_COLL && C_COMMON_CLK) begin : sync_coll + always @(posedge CLKA) begin + // Possible collision if both are enabled and the addresses match + if (ena_i && enb_i) begin + is_collision = collision_check(ADDRA, wea_i, ADDRB, web_i); + end else begin + is_collision = 0; + end + + // If the write port is in READ_FIRST mode, there is no collision + if (C_WRITE_MODE_A=="READ_FIRST" && wea_i && !web_i) begin + is_collision = 0; + end + if (C_WRITE_MODE_B=="READ_FIRST" && web_i && !wea_i) begin + is_collision = 0; + end + + // Only flag if one of the accesses is a write + if (is_collision && (wea_i || web_i)) begin + $fwrite(collfile, "%0s collision detected at time: %0d, ", + C_CORENAME, $time); + $fwrite(collfile, "A %0s address: %0h, B %0s address: %0h\n", + wea_i ? "write" : "read", ADDRA, + web_i ? "write" : "read", ADDRB); + end + end + + // Asynchronous collision checks + end else if (!C_DISABLE_WARN_BHV_COLL && !C_COMMON_CLK) begin : async_coll + + // Delay A and B addresses in order to mimic setup/hold times + wire [C_ADDRA_WIDTH-1:0] #coll_delay addra_delay = ADDRA; + wire [0:0] #coll_delay wea_delay = wea_i; + wire #coll_delay ena_delay = ena_i; + wire [C_ADDRB_WIDTH-1:0] #coll_delay addrb_delay = ADDRB; + wire [0:0] #coll_delay web_delay = web_i; + wire #coll_delay enb_delay = enb_i; + + // Do the checks w/rt A + always @(posedge CLKA) begin + // Possible collision if both are enabled and the addresses match + if (ena_i && enb_i) begin + is_collision_a = collision_check(ADDRA, wea_i, ADDRB, web_i); + end else begin + is_collision_a = 0; + end + if (ena_i && enb_delay) begin + is_collision_delay_a = collision_check(ADDRA, wea_i, + addrb_delay, web_delay); + end else begin + is_collision_delay_a = 0; + end + + + // Only flag if B access is a write + if (is_collision_a && web_i) begin + $fwrite(collfile, "%0s collision detected at time: %0d, ", + C_CORENAME, $time); + $fwrite(collfile, "A %0s address: %0h, B write address: %0h\n", + wea_i ? "write" : "read", ADDRA, ADDRB); + + end else if (is_collision_delay_a && web_delay) begin + $fwrite(collfile, "%0s collision detected at time: %0d, ", + C_CORENAME, $time); + $fwrite(collfile, "A %0s address: %0h, B write address: %0h\n", + wea_i ? "write" : "read", ADDRA, addrb_delay); + end + + end + + // Do the checks w/rt B + always @(posedge CLKB) begin + + // Possible collision if both are enabled and the addresses match + if (ena_i && enb_i) begin + is_collision_b = collision_check(ADDRA, wea_i, ADDRB, web_i); + end else begin + is_collision_b = 0; + end + if (ena_delay && enb_i) begin + is_collision_delay_b = collision_check(addra_delay, wea_delay, + ADDRB, web_i); + end else begin + is_collision_delay_b = 0; + end + + + // Only flag if A access is a write + if (is_collision_b && wea_i) begin + $fwrite(collfile, "%0s collision detected at time: %0d, ", + C_CORENAME, $time); + $fwrite(collfile, "A write address: %0h, B %s address: %0h\n", + ADDRA, web_i ? "write" : "read", ADDRB); + + end else if (is_collision_delay_b && wea_delay) begin + $fwrite(collfile, "%0s collision detected at time: %0d, ", + C_CORENAME, $time); + $fwrite(collfile, "A write address: %0h, B %s address: %0h\n", + addra_delay, web_i ? "write" : "read", ADDRB); + end + + end + end + endgenerate + +endmodule diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/BLK_MEM_GEN_V2_2_xst.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/BLK_MEM_GEN_V2_2_xst.v new file mode 100644 index 0000000..3afa49b --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/BLK_MEM_GEN_V2_2_xst.v @@ -0,0 +1,189 @@ +/****************************************************************************** + * + * Block Memory Generator Core - Block Memory Behavioral Model + * + * Copyright(C) 2005 by Xilinx, Inc. All rights reserved. + * This text/file contains proprietary, confidential + * information of Xilinx, Inc., is distributed under + * license from Xilinx, Inc., and may be used, copied + * and/or disclosed only pursuant to the terms of a valid + * license agreement with Xilinx, Inc. Xilinx hereby + * grants you a license to use this text/file solely for + * design, simulation, implementation and creation of + * design files limited to Xilinx devices or technologies. + * Use with non-Xilinx devices or technologies is expressly + * prohibited and immediately terminates your license unless + * covered by a separate agreement. + * + * Xilinx is providing this design, code, or information + * "as-is" solely for use in developing programs and + * solutions for Xilinx devices, with no obligation on the + * part of Xilinx to provide support. By providing this design, + * code, or information as one possible implementation of + * this feature, application or standard, Xilinx is making no + * representation that this implementation is free from any + * claims of infringement. You are responsible for obtaining + * any rights you may require for your implementation. + * Xilinx expressly disclaims any warranty whatsoever with + * respect to the adequacy of the implementation, including + * but not limited to any warranties or representations that this + * implementation is free from claims of infringement, implied + * warranties of merchantability or fitness for a particular + * purpose. + * + * Xilinx products are not intended for use in life support + * appliances, devices, or systems. Use in such applications is + * expressly prohibited. + * + * Any modifications that are made to the Source Code are + * done at the user's sole risk and will be unsupported. + * The Xilinx Support Hotline does not have access to source + * code and therefore cannot answer specific questions related + * to source HDL. The Xilinx Hotline support of original source + * code IP shall only address issues and questions related + * to the standard Netlist version of the core (and thus + * indirectly, the original core source). + * + * This copyright and support notice must be retained as part + * of this text at all times. (c) Copyright 1995-2005 Xilinx, Inc. + * All rights reserved. + * + ***************************************************************************** + * + * Filename: BLK_MEM_GEN_V2_2.v + * + * Description: + * This file is the Verilog behvarial model for the + * Block Memory Generator Core. + * + ***************************************************************************** + * Author: Xilinx + * + * History: September 6, 2005 Initial revision + *****************************************************************************/ +`timescale 1ps/1ps + +module BLK_MEM_GEN_V2_2_xst + #(parameter C_ADDRA_WIDTH = 5, + parameter C_ADDRB_WIDTH = 5, + parameter C_ALGORITHM = 1, + parameter C_BYTE_SIZE = 9, + parameter C_COMMON_CLK = 1, + parameter C_DEFAULT_DATA = "0", + parameter C_DISABLE_WARN_BHV_COLL = 0, + parameter C_DISABLE_WARN_BHV_RANGE = 0, + parameter C_FAMILY = "virtex5", + parameter C_HAS_ENA = 1, + parameter C_HAS_ENB = 1, + parameter C_HAS_MEM_OUTPUT_REGS = 0, + parameter C_HAS_MUX_OUTPUT_REGS = 0, + parameter C_HAS_REGCEA = 0, + parameter C_HAS_REGCEB = 0, + parameter C_HAS_SSRA = 0, + parameter C_HAS_SSRB = 0, + parameter C_INIT_FILE_NAME = "", + parameter C_LOAD_INIT_FILE = 0, + parameter C_MEM_TYPE = 2, + parameter C_PRIM_TYPE = 3, + parameter C_READ_DEPTH_A = 64, + parameter C_READ_DEPTH_B = 64, + parameter C_READ_WIDTH_A = 32, + parameter C_READ_WIDTH_B = 32, + parameter C_SIM_COLLISION_CHECK = "NONE", + parameter C_SINITA_VAL = "0", + parameter C_SINITB_VAL = "0", + parameter C_USE_BYTE_WEA = 0, + parameter C_USE_BYTE_WEB = 0, + parameter C_USE_DEFAULT_DATA = 0, + parameter C_USE_ECC = 0, + parameter C_WEA_WIDTH = 1, + parameter C_WEB_WIDTH = 1, + parameter C_WRITE_DEPTH_A = 64, + parameter C_WRITE_DEPTH_B = 64, + parameter C_WRITE_MODE_A = "WRITE_FIRST", + parameter C_WRITE_MODE_B = "WRITE_FIRST", + parameter C_WRITE_WIDTH_A = 32, + parameter C_WRITE_WIDTH_B = 32) + (input CLKA, + input [C_WRITE_WIDTH_A-1:0] DINA, + input [C_ADDRA_WIDTH-1:0] ADDRA, + input ENA, + input REGCEA, + input [C_WEA_WIDTH-1:0] WEA, + input SSRA, + output [C_READ_WIDTH_A-1:0] DOUTA, + input CLKB, + input [C_WRITE_WIDTH_B-1:0] DINB, + input [C_ADDRB_WIDTH-1:0] ADDRB, + input ENB, + input REGCEB, + input [C_WEB_WIDTH-1:0] WEB, + input SSRB, + output [C_READ_WIDTH_B-1:0] DOUTB, + output DBITERR, + output SBITERR); + + BLK_MEM_GEN_V2_2 + #(.C_FAMILY (C_FAMILY), + .C_MEM_TYPE (C_MEM_TYPE), + .C_ALGORITHM (C_ALGORITHM), + .C_USE_ECC (C_USE_ECC), + .C_PRIM_TYPE (C_PRIM_TYPE), + .C_BYTE_SIZE (C_BYTE_SIZE), + .C_COMMON_CLK (C_COMMON_CLK), + .C_SIM_COLLISION_CHECK (C_SIM_COLLISION_CHECK), + .C_DISABLE_WARN_BHV_COLL (C_DISABLE_WARN_BHV_COLL), + .C_DISABLE_WARN_BHV_RANGE (C_DISABLE_WARN_BHV_RANGE), + .C_LOAD_INIT_FILE (C_LOAD_INIT_FILE), + .C_INIT_FILE_NAME (C_INIT_FILE_NAME), + .C_USE_DEFAULT_DATA (C_USE_DEFAULT_DATA), + .C_DEFAULT_DATA (C_DEFAULT_DATA), + .C_HAS_MEM_OUTPUT_REGS (C_HAS_MEM_OUTPUT_REGS), + .C_HAS_MUX_OUTPUT_REGS (C_HAS_MUX_OUTPUT_REGS), + .C_WRITE_WIDTH_A (C_WRITE_WIDTH_A), + .C_READ_WIDTH_A (C_READ_WIDTH_A), + .C_WRITE_DEPTH_A (C_WRITE_DEPTH_A), + .C_READ_DEPTH_A (C_READ_DEPTH_A), + .C_ADDRA_WIDTH (C_ADDRA_WIDTH), + .C_WRITE_MODE_A (C_WRITE_MODE_A), + .C_HAS_ENA (C_HAS_ENA), + .C_HAS_REGCEA (C_HAS_REGCEA), + .C_HAS_SSRA (C_HAS_SSRA), + .C_SINITA_VAL (C_SINITA_VAL), + .C_USE_BYTE_WEA (C_USE_BYTE_WEA), + .C_WEA_WIDTH (C_WEA_WIDTH), + .C_WRITE_WIDTH_B (C_WRITE_WIDTH_B), + .C_READ_WIDTH_B (C_READ_WIDTH_B), + .C_WRITE_DEPTH_B (C_WRITE_DEPTH_B), + .C_READ_DEPTH_B (C_READ_DEPTH_B), + .C_ADDRB_WIDTH (C_ADDRB_WIDTH), + .C_WRITE_MODE_B (C_WRITE_MODE_B), + .C_HAS_ENB (C_HAS_ENB), + .C_HAS_REGCEB (C_HAS_REGCEB), + .C_HAS_SSRB (C_HAS_SSRB), + .C_SINITB_VAL (C_SINITB_VAL), + .C_USE_BYTE_WEB (C_USE_BYTE_WEB), + .C_WEB_WIDTH (C_WEB_WIDTH) + ) blk_mem_gen_v2_2_dut ( + .DINA (DINA), + .DINB (DINB), + .ADDRA (ADDRA), + .ADDRB (ADDRB), + .ENA (ENA), + .ENB (ENB), + .REGCEA (REGCEA), + .REGCEB (REGCEB), + .WEA (WEA), + .WEB (WEB), + .SSRA (SSRA), + .SSRB (SSRB), + .CLKA (CLKA), + .CLKB (CLKB), + .DOUTA (DOUTA), + .DOUTB (DOUTB), + .DBITERR (DBITERR), + .SBITERR (SBITERR) +); + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/BLK_MEM_GEN_V2_4.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/BLK_MEM_GEN_V2_4.v new file mode 100644 index 0000000..3164d39 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/BLK_MEM_GEN_V2_4.v @@ -0,0 +1,1108 @@ +/****************************************************************************** + * + * Block Memory Generator Core - Block Memory Behavioral Model + * + * Copyright(C) 2005 by Xilinx, Inc. All rights reserved. + * This text/file contains proprietary, confidential + * information of Xilinx, Inc., is distributed under + * license from Xilinx, Inc., and may be used, copied + * and/or disclosed only pursuant to the terms of a valid + * license agreement with Xilinx, Inc. Xilinx hereby + * grants you a license to use this text/file solely for + * design, simulation, implementation and creation of + * design files limited to Xilinx devices or technologies. + * Use with non-Xilinx devices or technologies is expressly + * prohibited and immediately terminates your license unless + * covered by a separate agreement. + * + * Xilinx is providing this design, code, or information + * "as-is" solely for use in developing programs and + * solutions for Xilinx devices, with no obligation on the + * part of Xilinx to provide support. By providing this design, + * code, or information as one possible implementation of + * this feature, application or standard, Xilinx is making no + * representation that this implementation is free from any + * claims of infringement. You are responsible for obtaining + * any rights you may require for your implementation. + * Xilinx expressly disclaims any warranty whatsoever with + * respect to the adequacy of the implementation, including + * but not limited to any warranties or representations that this + * implementation is free from claims of infringement, implied + * warranties of merchantability or fitness for a particular + * purpose. + * + * Xilinx products are not intended for use in life support + * appliances, devices, or systems. Use in such applications is + * expressly prohibited. + * + * Any modifications that are made to the Source Code are + * done at the user's sole risk and will be unsupported. + * The Xilinx Support Hotline does not have access to source + * code and therefore cannot answer specific questions related + * to source HDL. The Xilinx Hotline support of original source + * code IP shall only address issues and questions related + * to the standard Netlist version of the core (and thus + * indirectly, the original core source). + * + * This copyright and support notice must be retained as part + * of this text at all times. (c) Copyright 1995-2005 Xilinx, Inc. + * All rights reserved. + * + ***************************************************************************** + * + * Filename: BLK_MEM_GEN_V2_4.v + * + * Description: + * This file is the Verilog behvarial model for the + * Block Memory Generator Core. + * + ***************************************************************************** + * Author: Xilinx + * + * History: January 11, 2006 Initial revision + *****************************************************************************/ +`timescale 1ps/1ps + +module BLK_MEM_GEN_V2_4_output_stage + #(parameter C_DATA_WIDTH = 32, + parameter C_HAS_SSR = 0, + parameter C_SINIT_VAL = "0", + parameter C_HAS_REGCE = 0, + parameter C_HAS_EN = 0, + parameter C_USE_ECC = 0, + parameter C_FAMILY = "virtex5", + parameter C_XDEVICEFAMILY = "virtex5", + parameter C_USE_RAMB16BWER_RST_BHV = 0, + parameter num_stages = 1, + parameter flop_delay = 100) + (input CLK, + input SSR, + input REGCE, + input EN, + input [C_DATA_WIDTH-1:0] DIN, + output reg [C_DATA_WIDTH-1:0] DOUT); + + localparam reg_stages = (num_stages == 0) ? 0 : num_stages-1; + reg [C_DATA_WIDTH*reg_stages-1:0] out_regs; + reg [C_DATA_WIDTH*8-1:0] sinit_str = C_SINIT_VAL; + reg [C_DATA_WIDTH-1:0] sinit_val; + + // Wire off optional inputs based on parameters + //--------------------------------------------- + wire en_i; + wire regce_i; + wire ssr_i; + //Internal enable for output registers is tied to user EN or '1' depending + // on parameters + // For V4 ECC, EN is always 1 + // Virtex-4 ECC Not Yet Supported + assign en_i = (C_HAS_EN==0 || EN) + || (C_USE_ECC && C_FAMILY=="virtex4"); + //Internal enable is tied to user REGCE, EN or '1' depending on parameters + // For V4 ECC, REGCE is always 1 + // Virtex-4 ECC Not Yet Supported + assign regce_i = ((C_HAS_REGCE==1) && REGCE) || + ((C_HAS_REGCE==0) && (C_HAS_EN==0 || EN)) + || (C_USE_ECC && C_FAMILY=="virtex4"); + //Internal SRR is tied to user SSR or '0' depending on parameters + assign ssr_i = (C_HAS_SSR==1) && SSR; + + initial begin + // Power on: load up the output registers and latches + if (!($sscanf(sinit_str, "%h", sinit_val))) begin + sinit_val = 0; + end + DOUT = sinit_val; + // This will be one wider than need, but 0 is an error + out_regs = {(reg_stages+1){sinit_val}}; + end + + generate if (num_stages == 0) begin : zero_stages + always @* begin + DOUT = DIN; + end + end + endgenerate + + generate if (num_stages == 1 && C_USE_RAMB16BWER_RST_BHV==0) begin : one_stages_norm + always @(posedge CLK) begin + if (regce_i && ssr_i) begin + DOUT <= #flop_delay sinit_val; + end else if (regce_i) begin + DOUT <= #flop_delay DIN; + end + end + end + endgenerate + + generate if (num_stages == 1 && C_USE_RAMB16BWER_RST_BHV==1) begin : one_stages_s3ax + always @(posedge CLK) begin + if (en_i && ssr_i) begin + DOUT <= #flop_delay sinit_val; + end else if (regce_i) begin + DOUT <= #flop_delay DIN; + end + end + end + endgenerate + + generate if (num_stages > 1) begin : multi_stage + always @(posedge CLK) begin + if (regce_i && ssr_i) begin + DOUT <= #flop_delay sinit_val; + end else if (regce_i) begin + DOUT <= #flop_delay + out_regs[C_DATA_WIDTH*(num_stages-2)+:C_DATA_WIDTH]; + end + + if (en_i) begin + out_regs <= #flop_delay + (out_regs << C_DATA_WIDTH) | DIN; + end + end + end + endgenerate +endmodule + +module BLK_MEM_GEN_V2_4 + #(parameter C_ADDRA_WIDTH = 5, + parameter C_ADDRB_WIDTH = 5, + parameter C_ALGORITHM = 2, + parameter C_BYTE_SIZE = 8, + parameter C_COMMON_CLK = 1, + parameter C_CORENAME = "blk_mem_gen_v2_4", + parameter C_DEFAULT_DATA = "0", + parameter C_DISABLE_WARN_BHV_COLL = 0, + parameter C_DISABLE_WARN_BHV_RANGE = 0, + parameter C_FAMILY = "virtex4", + parameter C_HAS_ENA = 1, + parameter C_HAS_ENB = 1, + parameter C_HAS_MEM_OUTPUT_REGS = 0, + parameter C_HAS_MUX_OUTPUT_REGS = 0, + parameter C_HAS_REGCEA = 0, + parameter C_HAS_REGCEB = 0, + parameter C_HAS_SSRA = 0, + parameter C_HAS_SSRB = 0, + parameter C_INIT_FILE_NAME = "", + parameter C_LOAD_INIT_FILE = 0, + parameter C_MEM_TYPE = 2, + parameter C_PRIM_TYPE = 3, + parameter C_READ_DEPTH_A = 64, + parameter C_READ_DEPTH_B = 64, + parameter C_READ_WIDTH_A = 32, + parameter C_READ_WIDTH_B = 32, + parameter C_SIM_COLLISION_CHECK = "NONE", + parameter C_SINITA_VAL = "0", + parameter C_SINITB_VAL = "0", + parameter C_USE_BYTE_WEA = 0, + parameter C_USE_BYTE_WEB = 0, + parameter C_USE_DEFAULT_DATA = 0, + parameter C_USE_ECC = 0, + parameter C_USE_RAMB16BWER_RST_BHV = 0, + parameter C_WEA_WIDTH = 1, + parameter C_WEB_WIDTH = 1, + parameter C_WRITE_DEPTH_A = 64, + parameter C_WRITE_DEPTH_B = 64, + parameter C_WRITE_MODE_A = "WRITE_FIRST", + parameter C_WRITE_MODE_B = "WRITE_FIRST", + parameter C_WRITE_WIDTH_A = 32, + parameter C_WRITE_WIDTH_B = 32, + parameter C_XDEVICEFAMILY = "virtex4" +) + (input CLKA, + input [C_WRITE_WIDTH_A-1:0] DINA, + input [C_ADDRA_WIDTH-1:0] ADDRA, + input ENA, + input REGCEA, + input [C_WEA_WIDTH-1:0] WEA, + input SSRA, + output [C_READ_WIDTH_A-1:0] DOUTA, + input CLKB, + input [C_WRITE_WIDTH_B-1:0] DINB, + input [C_ADDRB_WIDTH-1:0] ADDRB, + input ENB, + input REGCEB, + input [C_WEB_WIDTH-1:0] WEB, + input SSRB, + output [C_READ_WIDTH_B-1:0] DOUTB, + output DBITERR, + output SBITERR + ); + + // constants for the core behavior + //================================ + // file handles for logging + //------------------------------------------------------ + localparam addrfile = 32'h8000_0001; // stdout for addr out of range + localparam collfile = 32'h8000_0001; // stdout for coll detection + localparam errfile = 32'h8000_0001; // stdout for file I/O errors + + // other constants + //------------------------------------------------------ + localparam coll_delay = 2000; // 2 ns + + // locally derived parameters to determine memory shape + //----------------------------------------------------- + localparam min_width_a = (C_WRITE_WIDTH_A < C_READ_WIDTH_A) ? + C_WRITE_WIDTH_A : C_READ_WIDTH_A; + localparam min_width_b = (C_WRITE_WIDTH_B < C_READ_WIDTH_B) ? + C_WRITE_WIDTH_B : C_READ_WIDTH_B; + localparam min_width = (min_width_a < min_width_b) ? + min_width_a : min_width_b; + + localparam max_width_a = (C_WRITE_WIDTH_A > C_READ_WIDTH_A) ? + C_WRITE_WIDTH_A : C_READ_WIDTH_A; + localparam max_width_b = (C_WRITE_WIDTH_B > C_READ_WIDTH_B) ? + C_WRITE_WIDTH_B : C_READ_WIDTH_B; + localparam max_width = (max_width_a > max_width_b) ? + max_width_a : max_width_b; + + localparam max_depth_a = (C_WRITE_DEPTH_A > C_READ_DEPTH_A) ? + C_WRITE_DEPTH_A : C_READ_DEPTH_A; + localparam max_depth_b = (C_WRITE_DEPTH_B > C_READ_DEPTH_B) ? + C_WRITE_DEPTH_B : C_READ_DEPTH_B; + localparam max_depth = (max_depth_a > max_depth_b) ? + max_depth_a : max_depth_b; + + + // locally derived parameters to assist memory access + //---------------------------------------------------- + localparam write_width_ratio_a = C_WRITE_WIDTH_A/min_width; + localparam read_width_ratio_a = C_READ_WIDTH_A/min_width; + localparam write_width_ratio_b = C_WRITE_WIDTH_B/min_width; + localparam read_width_ratio_b = C_READ_WIDTH_B/min_width; + + // To modify the LSBs of the 'wider' data to the actual + // address value + //---------------------------------------------------- + localparam write_addr_a_div = C_WRITE_WIDTH_A/min_width_a; + localparam read_addr_a_div = C_READ_WIDTH_A/min_width_a; + localparam write_addr_b_div = C_WRITE_WIDTH_B/min_width_b; + localparam read_addr_b_div = C_READ_WIDTH_B/min_width_b; + + // If byte writes aren't being used, make sure byte_size is not + // wider than the memory elements to avoid compilation warnings + localparam byte_size = (C_BYTE_SIZE < min_width) ? C_BYTE_SIZE : min_width; + + // the memory + reg [min_width-1:0] memory [0:max_depth-1]; + // memory output 'latches' + reg [C_READ_WIDTH_A-1:0] memory_out_a; + reg [C_READ_WIDTH_B-1:0] memory_out_b; + // reset values + reg [C_READ_WIDTH_A-1:0] sinita_val; + reg [C_READ_WIDTH_B-1:0] sinitb_val; + + // collision detect + reg is_collision; + reg is_collision_a, is_collision_delay_a; + reg is_collision_b, is_collision_delay_b; + + // temporary variables for initialization + //--------------------------------------- + integer status; + reg [639:0] err_str; + integer initfile; + // data input buffer + reg [C_WRITE_WIDTH_A-1:0] mif_data; + // string values in hex + reg [C_READ_WIDTH_A*8-1:0] sinita_str = C_SINITA_VAL; + reg [C_READ_WIDTH_B*8-1:0] sinitb_str = C_SINITB_VAL; + reg [C_WRITE_WIDTH_A*8-1:0] default_data_str = C_DEFAULT_DATA; + // initialization filename + reg [1023*8-1:0] init_file_str = C_INIT_FILE_NAME; + + // internal configuration parameters + //--------------------------------------------- + localparam flop_delay = 100; // 100 ps + localparam single_port = (C_MEM_TYPE==0 || C_MEM_TYPE==3); + localparam is_rom = (C_MEM_TYPE==3 || C_MEM_TYPE==4); + localparam has_a_write = (!is_rom); + localparam has_b_write = (C_MEM_TYPE==2); + localparam has_a_read = (C_MEM_TYPE!=1); + localparam has_b_read = (!single_port); + localparam has_b_port = (has_b_read || has_b_write); + // Virtex-4 ECC Not Yet Supported + localparam num_output_stages = (C_FAMILY=="virtex4" && C_USE_ECC==1) ? + (C_HAS_MEM_OUTPUT_REGS + C_HAS_MUX_OUTPUT_REGS + 1) : + (C_HAS_MEM_OUTPUT_REGS + C_HAS_MUX_OUTPUT_REGS); + + wire ena_i; + wire enb_i; + wire reseta_i; + wire resetb_i; + wire [C_WEA_WIDTH-1:0] wea_i; + wire [C_WEB_WIDTH-1:0] web_i; + wire rea_i; + wire reb_i; + + // ECC SBITERR/DBITERR Outputs + // The ECC Behavior is not modeled by the behavioral models, therefore + // the SBITERR and DBITERR outputs are explicitly tied to 0. + assign SBITERR = 0; + assign DBITERR = 0; + + + // This effectively wires off optional inputs + assign ena_i = (C_HAS_ENA==0) || ENA; + assign enb_i = ((C_HAS_ENB==0) || ENB) && has_b_port; + assign wea_i = (has_a_write && ena_i) ? WEA : 'b0; + assign web_i = (has_b_write && enb_i) ? WEB : 'b0; + assign rea_i = (has_a_read) ? ena_i : 'b0; + assign reb_i = (has_b_read) ? enb_i : 'b0; + + // these signals reset the memory latches + assign reseta_i = ((C_HAS_SSRA==1 && SSRA && ena_i && num_output_stages==0) || + (C_HAS_SSRA==1 && SSRA && ena_i && C_USE_RAMB16BWER_RST_BHV==1)); + assign resetb_i = ((C_HAS_SSRB==1 && SSRB && enb_i && num_output_stages==0) || + (C_HAS_SSRB==1 && SSRB && enb_i && C_USE_RAMB16BWER_RST_BHV==1)); + + // tasks to access the memory + //--------------------------- + task write_a + (input reg [C_ADDRA_WIDTH-1:0] addr, + input reg [C_WEA_WIDTH-1:0] byte_en, + input reg [C_WRITE_WIDTH_A-1:0] data); + reg [C_WRITE_WIDTH_A-1:0] current_contents; + reg [C_ADDRA_WIDTH-1:0] address; + integer i; + begin + // Shift the address by the ratio + address = (addr/write_addr_a_div); + if (address >= C_WRITE_DEPTH_A) begin + if (!C_DISABLE_WARN_BHV_RANGE) begin + $fdisplay(addrfile, + "%0s WARNING: Address %0h is outside range for A Write", + C_CORENAME, addr); + end + + // valid address + end else begin + + // Combine w/ byte writes + if (C_USE_BYTE_WEA) begin + + // Get the current memory contents + if (write_width_ratio_a == 1) begin + // Workaround for IUS 5.5 part-select issue + current_contents = memory[address]; + end else begin + for (i = 0; i < write_width_ratio_a; i = i + 1) begin + current_contents[min_width*i+:min_width] + = memory[address*write_width_ratio_a + i]; + end + end + + // Apply incoming bytes + if (C_WEA_WIDTH == 1) begin + // Workaround for IUS 5.5 part-select issue + if (byte_en[0]) begin + current_contents = data; + end + end else begin + for (i = 0; i < C_WEA_WIDTH; i = i + 1) begin + if (byte_en[i]) begin + current_contents[byte_size*i+:byte_size] + = data[byte_size*i+:byte_size]; + end + end + end + + // No byte-writes, overwrite the whole word + end else begin + current_contents = data; + end + + // Write data to memory + if (write_width_ratio_a == 1) begin + // Workaround for IUS 5.5 part-select issue + memory[address*write_width_ratio_a] = current_contents; + end else begin + for (i = 0; i < write_width_ratio_a; i = i + 1) begin + memory[address*write_width_ratio_a + i] + = current_contents[min_width*i+:min_width]; + end + end + + end + end + endtask + + task write_b + (input reg [C_ADDRB_WIDTH-1:0] addr, + input reg [C_WEB_WIDTH-1:0] byte_en, + input reg [C_WRITE_WIDTH_B-1:0] data); + reg [C_WRITE_WIDTH_B-1:0] current_contents; + reg [C_ADDRB_WIDTH-1:0] address; + integer i; + begin + // Shift the address by the ratio + address = (addr/write_addr_b_div); + if (address >= C_WRITE_DEPTH_B) begin + if (!C_DISABLE_WARN_BHV_RANGE) begin + $fdisplay(addrfile, + "%0s WARNING: Address %0h is outside range for B Write", + C_CORENAME, addr); + end + + // valid address + end else begin + + // Combine w/ byte writes + if (C_USE_BYTE_WEB) begin + + // Get the current memory contents + if (write_width_ratio_b == 1) begin + // Workaround for IUS 5.5 part-select issue + current_contents = memory[address]; + end else begin + for (i = 0; i < write_width_ratio_b; i = i + 1) begin + current_contents[min_width*i+:min_width] + = memory[address*write_width_ratio_b + i]; + end + end + + // Apply incoming bytes + if (C_WEB_WIDTH == 1) begin + // Workaround for IUS 5.5 part-select issue + if (byte_en[0]) begin + current_contents = data; + end + end else begin + for (i = 0; i < C_WEB_WIDTH; i = i + 1) begin + if (byte_en[i]) begin + current_contents[byte_size*i+:byte_size] + = data[byte_size*i+:byte_size]; + end + end + end + + // No byte-writes, overwrite the whole word + end else begin + current_contents = data; + end + + // Write data to memory + if (write_width_ratio_b == 1) begin + // Workaround for IUS 5.5 part-select issue + memory[address*write_width_ratio_b] = current_contents; + end else begin + for (i = 0; i < write_width_ratio_b; i = i + 1) begin + memory[address*write_width_ratio_b + i] + = current_contents[min_width*i+:min_width]; + end + end + end + end + endtask + + task read_a + (input reg [C_ADDRA_WIDTH-1:0] addr, + input reg reset); + reg [C_ADDRA_WIDTH-1:0] address; + integer i; + begin + + if (reset) begin + memory_out_a <= #flop_delay sinita_val; + end else begin + // Shift the address by the ratio + address = (addr/read_addr_a_div); + if (address >= C_READ_DEPTH_A) begin + if (!C_DISABLE_WARN_BHV_RANGE) begin + $fdisplay(addrfile, + "%0s WARNING: Address %0h is outside range for A Read", + C_CORENAME, addr); + end + + // valid address + end else begin + + if (read_width_ratio_a==1) begin + memory_out_a <= #flop_delay memory[address*read_width_ratio_a]; + end else begin + // Increment through the 'partial' words in the memory + for (i = 0; i < read_width_ratio_a; i = i + 1) begin + memory_out_a[min_width*i+:min_width] + <= #flop_delay memory[address*read_width_ratio_a + i]; + end + end + + end + end + end + endtask + + task read_b + (input reg [C_ADDRB_WIDTH-1:0] addr, + input reg reset); + reg [C_ADDRB_WIDTH-1:0] address; + integer i; + begin + + if (reset) begin + memory_out_b <= #flop_delay sinitb_val; + end else begin + // Shift the address + address = (addr/read_addr_b_div); + if (address >= C_READ_DEPTH_B) begin + if (!C_DISABLE_WARN_BHV_RANGE) begin + $fdisplay(addrfile, + "%0s WARNING: Address %0h is outside range for B Read", + C_CORENAME, addr); + end + + // valid address + end else begin + + if (read_width_ratio_b==1) begin + memory_out_b <= #flop_delay memory[address*read_width_ratio_b]; + end else begin + // Increment through the 'partial' words in the memory + for (i = 0; i < read_width_ratio_b; i = i + 1) begin + memory_out_b[min_width*i+:min_width] + <= #flop_delay memory[address*read_width_ratio_b + i]; + end + end + + end + end + end + endtask + + task init_memory; + integer i, addr_step; + integer status; + reg [C_WRITE_WIDTH_A-1:0] default_data; + begin + default_data = 0; + + //Display output message indicating that the behavioral model is being initialized + if (C_USE_DEFAULT_DATA || C_LOAD_INIT_FILE) $display(" Block Memory Generator CORE Generator module loading initial data..."); + + // Convert the default to hex + if (C_USE_DEFAULT_DATA) begin + if (default_data_str == "") begin + $fdisplay(errfile, "%0s ERROR: C_DEFAULT_DATA is empty!", C_CORENAME); + $finish; + end else begin + status = $sscanf(default_data_str, "%h", default_data); + if (status == 0) begin + $fdisplay(errfile, {"%0s ERROR: Unsuccessful hexadecimal read", + "from C_DEFAULT_DATA: %0s"}, + C_CORENAME, C_DEFAULT_DATA); + $finish; + end + end + end + + // Step by write_addr_a_div through the memory via the + // Port A write interface to hit every location once + addr_step = write_addr_a_div; + + // 'write' to every location with default (or 0) + for (i = 0; i < C_WRITE_DEPTH_A*addr_step; i = i + addr_step) begin + write_a(i, {C_WEA_WIDTH{1'b1}}, default_data); + end + + // Get specialized data from the MIF file + if (C_LOAD_INIT_FILE) begin + if (init_file_str == "") begin + $fdisplay(errfile, "%0s ERROR: C_INIT_FILE_NAME is empty!", + C_CORENAME); + $finish; + end else begin + initfile = $fopen(init_file_str, "r"); + if (initfile == 0) begin + $fdisplay(errfile, {"%0s, ERROR: Problem opening", + "C_INIT_FILE_NAME: %0s!"}, + C_CORENAME, init_file_str); + $finish; + end else begin + // loop through the mif file, loading in the data + for (i = 0; i < C_WRITE_DEPTH_A*addr_step; i = i + addr_step) begin + status = $fscanf(initfile, "%b", mif_data); + if (status > 0) begin + write_a(i, {C_WEA_WIDTH{1'b1}}, mif_data); + end + end + $fclose(initfile); + end //initfile + end //init_file_str + end //C_LOAD_INIT_FILE + + //Display output message indicating that the behavioral model is done initializing + if (C_USE_DEFAULT_DATA || C_LOAD_INIT_FILE) $display(" Block Memory Generator data initialization complete."); + + + end + endtask + + function integer log2roundup (input integer data_value); + integer width; + integer cnt; + begin + width = 0; + + if (data_value > 1) begin + for(cnt=1 ; cnt < data_value ; cnt = cnt * 2) begin + width = width + 1; + end //loop + end //if + + log2roundup = width; + + end //log2roundup + endfunction + + + + function integer collision_check (input reg [C_ADDRA_WIDTH-1:0] addr_a, + input integer iswrite_a, + input reg [C_ADDRB_WIDTH-1:0] addr_b, + input integer iswrite_b); + reg [C_ADDRA_WIDTH-1:0] base_addr_a; + reg [C_ADDRB_WIDTH-1:0] base_addr_b; + integer ratio_a, ratio_b; + integer lo_addr_wider, hi_addr_wider; + integer lo_addr_narrow, hi_addr_narrow; + reg c_aw_bw, c_aw_br, c_ar_bw; + integer write_addr_a_width, read_addr_a_width; + integer write_addr_b_width, read_addr_b_width; + + begin + + c_aw_bw = 0; + c_aw_br = 0; + c_ar_bw = 0; + + // Determine the effective address widths for each of the 4 ports + write_addr_a_width = C_ADDRA_WIDTH-log2roundup(write_addr_a_div); + read_addr_a_width = C_ADDRA_WIDTH-log2roundup(read_addr_a_div); + write_addr_b_width = C_ADDRB_WIDTH-log2roundup(write_addr_b_div); + read_addr_b_width = C_ADDRB_WIDTH-log2roundup(read_addr_b_div); + + + //Look for a write-write collision. In order for a write-write + //collision to exist, both ports must have a write transaction. + if (iswrite_a && iswrite_b) begin + if (write_addr_a_width > write_addr_b_width) begin + //write_addr_b_width is smaller, so scale both addresses to that + // width for comparing write_addr_a and write_addr_b + //addr_a starts as C_ADDRA_WIDTH, + // scale it down to write_addr_b_width + //addr_b starts as C_ADDRB_WIDTH, + // scale it down to write_addr_b_width + //Once both are scaled to write_addr_b_width, compare. + if (((addr_a)/2**(C_ADDRA_WIDTH-write_addr_b_width)) == ((addr_b)/2**(C_ADDRB_WIDTH-write_addr_b_width))) begin + c_aw_bw = 1; + end else begin + c_aw_bw = 0; + end + end else begin + //write_addr_a_width is smaller, so scale both addresses to that + // width for comparing write_addr_a and write_addr_b + //addr_a starts as C_ADDRA_WIDTH, + // scale it down to write_addr_a_width + //addr_b starts as C_ADDRB_WIDTH, + // scale it down to write_addr_a_width + //Once both are scaled to write_addr_a_width, compare. + if (((addr_b)/2**(C_ADDRB_WIDTH-write_addr_a_width)) == ((addr_a)/2**(C_ADDRA_WIDTH-write_addr_a_width))) begin + c_aw_bw = 1; + end else begin + c_aw_bw = 0; + end + end //width + end //iswrite_a and iswrite_b + + //If the B port is reading (which means it is enabled - so could be + // a TX_WRITE or TX_READ), then check for a write-read collision). + //This could happen whether or not a write-write collision exists due + // to asymmetric write/read ports. + if (iswrite_a) begin + if (write_addr_a_width > read_addr_b_width) begin + //read_addr_b_width is smaller, so scale both addresses to that + // width for comparing write_addr_a and read_addr_b + //addr_a starts as C_ADDRA_WIDTH, + // scale it down to read_addr_b_width + //addr_b starts as C_ADDRB_WIDTH, + // scale it down to read_addr_b_width + //Once both are scaled to read_addr_b_width, compare. + if (((addr_a)/2**(C_ADDRA_WIDTH-read_addr_b_width)) == ((addr_b)/2**(C_ADDRB_WIDTH-read_addr_b_width))) begin + c_aw_br = 1; + end else begin + c_aw_br = 0; + end + end else begin + //write_addr_a_width is smaller, so scale both addresses to that + // width for comparing write_addr_a and read_addr_b + //addr_a starts as C_ADDRA_WIDTH, + // scale it down to write_addr_a_width + //addr_b starts as C_ADDRB_WIDTH, + // scale it down to write_addr_a_width + //Once both are scaled to write_addr_a_width, compare. + if (((addr_b)/2**(C_ADDRB_WIDTH-write_addr_a_width)) == ((addr_a)/2**(C_ADDRA_WIDTH-write_addr_a_width))) begin + c_aw_br = 1; + end else begin + c_aw_br = 0; + end + end //width + end //iswrite_a + + //If the A port is reading (which means it is enabled - so could be + // a TX_WRITE or TX_READ), then check for a write-read collision). + //This could happen whether or not a write-write collision exists due + // to asymmetric write/read ports. + if (iswrite_b) begin + if (read_addr_a_width > write_addr_b_width) begin + //write_addr_b_width is smaller, so scale both addresses to that + // width for comparing read_addr_a and write_addr_b + //addr_a starts as C_ADDRA_WIDTH, + // scale it down to write_addr_b_width + //addr_b starts as C_ADDRB_WIDTH, + // scale it down to write_addr_b_width + //Once both are scaled to write_addr_b_width, compare. + if (((addr_a)/2**(C_ADDRA_WIDTH-write_addr_b_width)) == ((addr_b)/2**(C_ADDRB_WIDTH-write_addr_b_width))) begin + c_ar_bw = 1; + end else begin + c_ar_bw = 0; + end + end else begin + //read_addr_a_width is smaller, so scale both addresses to that + // width for comparing read_addr_a and write_addr_b + //addr_a starts as C_ADDRA_WIDTH, + // scale it down to read_addr_a_width + //addr_b starts as C_ADDRB_WIDTH, + // scale it down to read_addr_a_width + //Once both are scaled to read_addr_a_width, compare. + if (((addr_b)/2**(C_ADDRB_WIDTH-read_addr_a_width)) == ((addr_a)/2**(C_ADDRA_WIDTH-read_addr_a_width))) begin + c_ar_bw = 1; + end else begin + c_ar_bw = 0; + end + end //width + end //iswrite_b + + + // Convert the input addresses in base and offsets for our + // memory array. Ignore LSBs for asymmetric ports + if (iswrite_a) begin + base_addr_a = (addr_a/write_addr_a_div) * write_addr_a_div; + ratio_a = write_width_ratio_a; + end else begin + base_addr_a = (addr_a/read_addr_a_div) * read_addr_a_div; + ratio_a = read_width_ratio_a; + end + if (iswrite_b) begin + base_addr_b = (addr_b/write_addr_b_div) * write_addr_b_div; + ratio_b = write_width_ratio_b; + end else begin + base_addr_b = (addr_b/read_addr_b_div) * read_addr_b_div; + ratio_b = read_width_ratio_b; + end + + // Determine the wider port, and normalized ranges + if (ratio_a >= ratio_b) begin + lo_addr_wider = base_addr_a * ratio_a; + hi_addr_wider = lo_addr_wider + ratio_a; + lo_addr_narrow = base_addr_b * ratio_b; + hi_addr_narrow = lo_addr_narrow + ratio_b; + end else begin + lo_addr_wider = base_addr_b * ratio_b; + hi_addr_wider = lo_addr_wider + ratio_b; + lo_addr_narrow = base_addr_a * ratio_a; + hi_addr_narrow = lo_addr_narrow + ratio_a; + end + + // compare the two ranges of address (narrow inside wider) + //if ((lo_addr_narrow >= lo_addr_wider) && + // (hi_addr_narrow <= hi_addr_wider)) begin + // collision_check = 1; + //end else begin + // collision_check = 0; + //end + + collision_check = c_aw_bw | c_aw_br | c_ar_bw; + + end + endfunction + + // power on values + //----------------------------- + initial begin + // Load up the memory + init_memory; + // Load up the output registers and latches + if ($sscanf(sinita_str, "%h", sinita_val)) begin + memory_out_a = sinita_val; + end else begin + memory_out_a = 0; + end + if ($sscanf(sinitb_str, "%h", sinitb_val)) begin + memory_out_b = sinitb_val; + end else begin + memory_out_b = 0; + end + + $display("Block Memory Generator CORE Generator module %m is using a behavioral model for simulation which will not precisely model memory collision behavior."); + + end + + //------------------------------------------------------------------------- + // These are the main blocks which schedule read and write operations + //------------------------------------------------------------------------- + + generate if (C_COMMON_CLK) begin : common_clk_scheduling + // Synchronous clocks: schedule port operations with respect to + // both write operating modes + always @(posedge CLKA) begin + case ({C_WRITE_MODE_A, C_WRITE_MODE_B}) + {"WRITE_FIRST","WRITE_FIRST"}: begin + if (wea_i) write_a(ADDRA, wea_i, DINA); + if (web_i) write_b(ADDRB, web_i, DINB); + if (rea_i) read_a(ADDRA, reseta_i); + if (reb_i) read_b(ADDRB, resetb_i); + end + {"READ_FIRST", "WRITE_FIRST"}: begin + if (web_i) write_b(ADDRB, web_i, DINB); + if (reb_i) read_b(ADDRB, resetb_i); + if (rea_i) read_a(ADDRA, reseta_i); + if (wea_i) write_a(ADDRA, wea_i, DINA); + end + {"WRITE_FIRST","READ_FIRST"}: begin + if (wea_i) write_a(ADDRA, wea_i, DINA); + if (rea_i) read_a(ADDRA, reseta_i); + if (reb_i) read_b(ADDRB, resetb_i); + if (web_i) write_b(ADDRB, web_i, DINB); + end + {"READ_FIRST", "READ_FIRST"}: begin + if (rea_i) read_a(ADDRA, reseta_i); + if (reb_i) read_b(ADDRB, resetb_i); + if (wea_i) write_a(ADDRA, wea_i, DINA); + if (web_i) write_b(ADDRB, web_i, DINB); + end + {"WRITE_FIRST","NO_CHANGE"}: begin + if (wea_i) write_a(ADDRA, wea_i, DINA); + if (rea_i) read_a(ADDRA, reseta_i); + if ((reb_i && !web_i) || resetb_i) read_b(ADDRB, resetb_i); + if (web_i) write_b(ADDRB, web_i, DINB); + end + {"READ_FIRST", "NO_CHANGE"}: begin + if (rea_i) read_a(ADDRA, reseta_i); + if ((reb_i && !web_i) || resetb_i) read_b(ADDRB, resetb_i); + if (wea_i) write_a(ADDRA, wea_i, DINA); + if (web_i) write_b(ADDRB, web_i, DINB); + end + {"NO_CHANGE", "WRITE_FIRST"}: begin + if (wea_i) write_a(ADDRA, wea_i, DINA); + if (web_i) write_b(ADDRB, web_i, DINB); + if ((rea_i && !wea_i) || reseta_i) read_a(ADDRA, reseta_i); + if (reb_i) read_b(ADDRB, resetb_i); + end + {"NO_CHANGE", "READ_FIRST"}: begin + if (reb_i) read_b(ADDRB, resetb_i); + if ((rea_i && !wea_i) || reseta_i) read_a(ADDRA, reseta_i); + if (wea_i) write_a(ADDRA, wea_i, DINA); + if (web_i) write_b(ADDRB, web_i, DINB); + end + {"NO_CHANGE", "NO_CHANGE"}: begin + if (wea_i) write_a(ADDRA, wea_i, DINA); + if (web_i) write_b(ADDRB, web_i, DINB); + if ((rea_i && !wea_i) || reseta_i) read_a(ADDRA, reseta_i); + if ((reb_i && !web_i) || resetb_i) read_b(ADDRB, resetb_i); + end + default: begin + if (wea_i) write_a(ADDRA, wea_i, DINA); + if (web_i) write_b(ADDRB, web_i, DINB); + if (rea_i) read_a(ADDRA, reseta_i); + if (reb_i) read_b(ADDRB, resetb_i); + end + endcase + end + + end else begin : asynch_clk_scheduling + // Asynchronous clocks: port operation is independent + always @(posedge CLKA) begin + case (C_WRITE_MODE_A) + "WRITE_FIRST": begin + if (wea_i) write_a(ADDRA, wea_i, DINA); + if (rea_i) read_a(ADDRA, reseta_i); + end + "READ_FIRST": begin + if (rea_i) read_a(ADDRA, reseta_i); + if (wea_i) write_a(ADDRA, wea_i, DINA); + end + "NO_CHANGE": begin + if (wea_i) write_a(ADDRA, wea_i, DINA); + if ((rea_i && !wea_i) || reseta_i) read_a(ADDRA, reseta_i); + end + endcase + end + + always @(posedge CLKB) begin + case (C_WRITE_MODE_B) + "WRITE_FIRST": begin + if (web_i) write_b(ADDRB, web_i, DINB); + if (reb_i) read_b(ADDRB, resetb_i); + end + "READ_FIRST": begin + if (reb_i) read_b(ADDRB, resetb_i); + if (web_i) write_b(ADDRB, web_i, DINB); + end + "NO_CHANGE": begin + if (web_i) write_b(ADDRB, web_i, DINB); + if ((reb_i && !web_i) || resetb_i) read_b(ADDRB, resetb_i); + end + endcase + end + end + endgenerate + + // Variable depth output stage + BLK_MEM_GEN_V2_4_output_stage + #(.C_DATA_WIDTH (C_READ_WIDTH_A), + .C_HAS_SSR (C_HAS_SSRA), + .C_SINIT_VAL (C_SINITA_VAL), + .C_HAS_REGCE (C_HAS_REGCEA), + .C_HAS_EN (C_HAS_ENA), + .C_USE_ECC (C_USE_ECC), + .C_FAMILY (C_FAMILY), + .C_XDEVICEFAMILY (C_XDEVICEFAMILY), + .C_USE_RAMB16BWER_RST_BHV (C_USE_RAMB16BWER_RST_BHV), + .num_stages (num_output_stages), + .flop_delay (flop_delay)) + reg_a + (.CLK (CLKA), + .SSR (SSRA), + .REGCE (REGCEA), + .EN (ENA), + .DIN (memory_out_a), + .DOUT (DOUTA)); + + BLK_MEM_GEN_V2_4_output_stage + #(.C_DATA_WIDTH (C_READ_WIDTH_B), + .C_HAS_SSR (C_HAS_SSRB), + .C_SINIT_VAL (C_SINITB_VAL), + .C_HAS_REGCE (C_HAS_REGCEB), + .C_HAS_EN (C_HAS_ENB), + .C_USE_ECC (C_USE_ECC), + .C_FAMILY (C_FAMILY), + .C_XDEVICEFAMILY (C_XDEVICEFAMILY), + .C_USE_RAMB16BWER_RST_BHV (C_USE_RAMB16BWER_RST_BHV), + .num_stages (num_output_stages), + .flop_delay (flop_delay)) + reg_b + (.CLK (CLKB), + .SSR (SSRB), + .REGCE (REGCEB), + .EN (ENB), + .DIN (memory_out_b), + .DOUT (DOUTB)); + + // Synchronous collision checks + generate if (!C_DISABLE_WARN_BHV_COLL && C_COMMON_CLK) begin : sync_coll + always @(posedge CLKA) begin + // Possible collision if both are enabled and the addresses match + if (ena_i && enb_i) begin + is_collision = collision_check(ADDRA, wea_i, ADDRB, web_i); + end else begin + is_collision = 0; + end + + // If the write port is in READ_FIRST mode, there is no collision + if (C_WRITE_MODE_A=="READ_FIRST" && wea_i && !web_i) begin + is_collision = 0; + end + if (C_WRITE_MODE_B=="READ_FIRST" && web_i && !wea_i) begin + is_collision = 0; + end + + // Only flag if one of the accesses is a write + if (is_collision && (wea_i || web_i)) begin + $fwrite(collfile, "%0s collision detected at time: %0d, ", + C_CORENAME, $time); + $fwrite(collfile, "A %0s address: %0h, B %0s address: %0h\n", + wea_i ? "write" : "read", ADDRA, + web_i ? "write" : "read", ADDRB); + end + end + + // Asynchronous collision checks + end else if (!C_DISABLE_WARN_BHV_COLL && !C_COMMON_CLK) begin : async_coll + + // Delay A and B addresses in order to mimic setup/hold times + wire [C_ADDRA_WIDTH-1:0] #coll_delay addra_delay = ADDRA; + wire [0:0] #coll_delay wea_delay = wea_i; + wire #coll_delay ena_delay = ena_i; + wire [C_ADDRB_WIDTH-1:0] #coll_delay addrb_delay = ADDRB; + wire [0:0] #coll_delay web_delay = web_i; + wire #coll_delay enb_delay = enb_i; + + // Do the checks w/rt A + always @(posedge CLKA) begin + // Possible collision if both are enabled and the addresses match + if (ena_i && enb_i) begin + is_collision_a = collision_check(ADDRA, wea_i, ADDRB, web_i); + end else begin + is_collision_a = 0; + end + if (ena_i && enb_delay) begin + is_collision_delay_a = collision_check(ADDRA, wea_i, + addrb_delay, web_delay); + end else begin + is_collision_delay_a = 0; + end + + + // Only flag if B access is a write + if (is_collision_a && web_i) begin + $fwrite(collfile, "%0s collision detected at time: %0d, ", + C_CORENAME, $time); + $fwrite(collfile, "A %0s address: %0h, B write address: %0h\n", + wea_i ? "write" : "read", ADDRA, ADDRB); + + end else if (is_collision_delay_a && web_delay) begin + $fwrite(collfile, "%0s collision detected at time: %0d, ", + C_CORENAME, $time); + $fwrite(collfile, "A %0s address: %0h, B write address: %0h\n", + wea_i ? "write" : "read", ADDRA, addrb_delay); + end + + end + + // Do the checks w/rt B + always @(posedge CLKB) begin + + // Possible collision if both are enabled and the addresses match + if (ena_i && enb_i) begin + is_collision_b = collision_check(ADDRA, wea_i, ADDRB, web_i); + end else begin + is_collision_b = 0; + end + if (ena_delay && enb_i) begin + is_collision_delay_b = collision_check(addra_delay, wea_delay, + ADDRB, web_i); + end else begin + is_collision_delay_b = 0; + end + + + // Only flag if A access is a write + if (is_collision_b && wea_i) begin + $fwrite(collfile, "%0s collision detected at time: %0d, ", + C_CORENAME, $time); + $fwrite(collfile, "A write address: %0h, B %s address: %0h\n", + ADDRA, web_i ? "write" : "read", ADDRB); + + end else if (is_collision_delay_b && wea_delay) begin + $fwrite(collfile, "%0s collision detected at time: %0d, ", + C_CORENAME, $time); + $fwrite(collfile, "A write address: %0h, B %s address: %0h\n", + addra_delay, web_i ? "write" : "read", ADDRB); + end + + end + end + endgenerate + +endmodule diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/BLK_MEM_GEN_V2_4_xst.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/BLK_MEM_GEN_V2_4_xst.v new file mode 100644 index 0000000..0b7f21f --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/BLK_MEM_GEN_V2_4_xst.v @@ -0,0 +1,195 @@ +/****************************************************************************** + * + * Block Memory Generator Core - Block Memory Behavioral Model + * + * Copyright(C) 2005 by Xilinx, Inc. All rights reserved. + * This text/file contains proprietary, confidential + * information of Xilinx, Inc., is distributed under + * license from Xilinx, Inc., and may be used, copied + * and/or disclosed only pursuant to the terms of a valid + * license agreement with Xilinx, Inc. Xilinx hereby + * grants you a license to use this text/file solely for + * design, simulation, implementation and creation of + * design files limited to Xilinx devices or technologies. + * Use with non-Xilinx devices or technologies is expressly + * prohibited and immediately terminates your license unless + * covered by a separate agreement. + * + * Xilinx is providing this design, code, or information + * "as-is" solely for use in developing programs and + * solutions for Xilinx devices, with no obligation on the + * part of Xilinx to provide support. By providing this design, + * code, or information as one possible implementation of + * this feature, application or standard, Xilinx is making no + * representation that this implementation is free from any + * claims of infringement. You are responsible for obtaining + * any rights you may require for your implementation. + * Xilinx expressly disclaims any warranty whatsoever with + * respect to the adequacy of the implementation, including + * but not limited to any warranties or representations that this + * implementation is free from claims of infringement, implied + * warranties of merchantability or fitness for a particular + * purpose. + * + * Xilinx products are not intended for use in life support + * appliances, devices, or systems. Use in such applications is + * expressly prohibited. + * + * Any modifications that are made to the Source Code are + * done at the user's sole risk and will be unsupported. + * The Xilinx Support Hotline does not have access to source + * code and therefore cannot answer specific questions related + * to source HDL. The Xilinx Hotline support of original source + * code IP shall only address issues and questions related + * to the standard Netlist version of the core (and thus + * indirectly, the original core source). + * + * This copyright and support notice must be retained as part + * of this text at all times. (c) Copyright 1995-2005 Xilinx, Inc. + * All rights reserved. + * + ***************************************************************************** + * + * Filename: BLK_MEM_GEN_V2_4.v + * + * Description: + * This file is the Verilog behvarial model for the + * Block Memory Generator Core. + * + ***************************************************************************** + * Author: Xilinx + * + * History: September 6, 2005 Initial revision + *****************************************************************************/ +`timescale 1ps/1ps + +module BLK_MEM_GEN_V2_4_xst + #(parameter C_ADDRA_WIDTH = 5, + parameter C_ADDRB_WIDTH = 5, + parameter C_ALGORITHM = 1, + parameter C_BYTE_SIZE = 9, + parameter C_COMMON_CLK = 1, + parameter C_DEFAULT_DATA = "0", + parameter C_DISABLE_WARN_BHV_COLL = 0, + parameter C_DISABLE_WARN_BHV_RANGE = 0, + parameter C_FAMILY = "virtex5", + parameter C_HAS_ENA = 1, + parameter C_HAS_ENB = 1, + parameter C_HAS_MEM_OUTPUT_REGS = 0, + parameter C_HAS_MUX_OUTPUT_REGS = 0, + parameter C_HAS_REGCEA = 0, + parameter C_HAS_REGCEB = 0, + parameter C_HAS_SSRA = 0, + parameter C_HAS_SSRB = 0, + parameter C_INIT_FILE_NAME = "", + parameter C_LOAD_INIT_FILE = 0, + parameter C_MEM_TYPE = 2, + parameter C_PRIM_TYPE = 3, + parameter C_READ_DEPTH_A = 64, + parameter C_READ_DEPTH_B = 64, + parameter C_READ_WIDTH_A = 32, + parameter C_READ_WIDTH_B = 32, + parameter C_SIM_COLLISION_CHECK = "NONE", + parameter C_SINITA_VAL = "0", + parameter C_SINITB_VAL = "0", + parameter C_USE_BYTE_WEA = 0, + parameter C_USE_BYTE_WEB = 0, + parameter C_USE_DEFAULT_DATA = 0, + parameter C_USE_ECC = 0, + parameter C_USE_RAMB16BWER_RST_BHV = 0, + parameter C_WEA_WIDTH = 1, + parameter C_WEB_WIDTH = 1, + parameter C_WRITE_DEPTH_A = 64, + parameter C_WRITE_DEPTH_B = 64, + parameter C_WRITE_MODE_A = "WRITE_FIRST", + parameter C_WRITE_MODE_B = "WRITE_FIRST", + parameter C_WRITE_WIDTH_A = 32, + parameter C_WRITE_WIDTH_B = 32, + parameter C_XDEVICEFAMILY = "virtex5" +) + (input CLKA, + input [C_WRITE_WIDTH_A-1:0] DINA, + input [C_ADDRA_WIDTH-1:0] ADDRA, + input ENA, + input REGCEA, + input [C_WEA_WIDTH-1:0] WEA, + input SSRA, + output [C_READ_WIDTH_A-1:0] DOUTA, + input CLKB, + input [C_WRITE_WIDTH_B-1:0] DINB, + input [C_ADDRB_WIDTH-1:0] ADDRB, + input ENB, + input REGCEB, + input [C_WEB_WIDTH-1:0] WEB, + input SSRB, + output [C_READ_WIDTH_B-1:0] DOUTB, + output DBITERR, + output SBITERR); + + BLK_MEM_GEN_V2_4 + #( + .C_ADDRA_WIDTH (C_ADDRA_WIDTH), + .C_ADDRB_WIDTH (C_ADDRB_WIDTH), + .C_ALGORITHM (C_ALGORITHM), + .C_BYTE_SIZE (C_BYTE_SIZE), + .C_COMMON_CLK (C_COMMON_CLK), + .C_DEFAULT_DATA (C_DEFAULT_DATA), + .C_DISABLE_WARN_BHV_COLL (C_DISABLE_WARN_BHV_COLL), + .C_DISABLE_WARN_BHV_RANGE (C_DISABLE_WARN_BHV_RANGE), + .C_FAMILY (C_FAMILY), + .C_HAS_ENA (C_HAS_ENA), + .C_HAS_ENB (C_HAS_ENB), + .C_HAS_MEM_OUTPUT_REGS (C_HAS_MEM_OUTPUT_REGS), + .C_HAS_MUX_OUTPUT_REGS (C_HAS_MUX_OUTPUT_REGS), + .C_HAS_REGCEA (C_HAS_REGCEA), + .C_HAS_REGCEB (C_HAS_REGCEB), + .C_HAS_SSRA (C_HAS_SSRA), + .C_HAS_SSRB (C_HAS_SSRB), + .C_INIT_FILE_NAME (C_INIT_FILE_NAME), + .C_LOAD_INIT_FILE (C_LOAD_INIT_FILE), + .C_MEM_TYPE (C_MEM_TYPE), + .C_PRIM_TYPE (C_PRIM_TYPE), + .C_READ_DEPTH_A (C_READ_DEPTH_A), + .C_READ_DEPTH_B (C_READ_DEPTH_B), + .C_READ_WIDTH_A (C_READ_WIDTH_A), + .C_READ_WIDTH_B (C_READ_WIDTH_B), + .C_SIM_COLLISION_CHECK (C_SIM_COLLISION_CHECK), + .C_SINITA_VAL (C_SINITA_VAL), + .C_SINITB_VAL (C_SINITB_VAL), + .C_USE_BYTE_WEA (C_USE_BYTE_WEA), + .C_USE_BYTE_WEB (C_USE_BYTE_WEB), + .C_USE_DEFAULT_DATA (C_USE_DEFAULT_DATA), + .C_USE_ECC (C_USE_ECC), + .C_USE_RAMB16BWER_RST_BHV (C_USE_RAMB16BWER_RST_BHV), + .C_WEA_WIDTH (C_WEA_WIDTH), + .C_WEB_WIDTH (C_WEB_WIDTH), + .C_WRITE_DEPTH_A (C_WRITE_DEPTH_A), + .C_WRITE_DEPTH_B (C_WRITE_DEPTH_B), + .C_WRITE_MODE_A (C_WRITE_MODE_A), + .C_WRITE_MODE_B (C_WRITE_MODE_B), + .C_WRITE_WIDTH_A (C_WRITE_WIDTH_A), + .C_WRITE_WIDTH_B (C_WRITE_WIDTH_B), + .C_XDEVICEFAMILY (C_XDEVICEFAMILY) + ) blk_mem_gen_v2_4_dut ( + .DINA (DINA), + .DINB (DINB), + .ADDRA (ADDRA), + .ADDRB (ADDRB), + .ENA (ENA), + .ENB (ENB), + .REGCEA (REGCEA), + .REGCEB (REGCEB), + .WEA (WEA), + .WEB (WEB), + .SSRA (SSRA), + .SSRB (SSRB), + .CLKA (CLKA), + .CLKB (CLKB), + .DOUTA (DOUTA), + .DOUTB (DOUTB), + .DBITERR (DBITERR), + .SBITERR (SBITERR) +); + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/BLK_MEM_GEN_V2_5.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/BLK_MEM_GEN_V2_5.v new file mode 100644 index 0000000..ef0dbca --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/BLK_MEM_GEN_V2_5.v @@ -0,0 +1,1158 @@ +/****************************************************************************** + * + * Block Memory Generator Core - Block Memory Behavioral Model + * + * Copyright(C) 2005 by Xilinx, Inc. All rights reserved. + * This text/file contains proprietary, confidential + * information of Xilinx, Inc., is distributed under + * license from Xilinx, Inc., and may be used, copied + * and/or disclosed only pursuant to the terms of a valid + * license agreement with Xilinx, Inc. Xilinx hereby + * grants you a license to use this text/file solely for + * design, simulation, implementation and creation of + * design files limited to Xilinx devices or technologies. + * Use with non-Xilinx devices or technologies is expressly + * prohibited and immediately terminates your license unless + * covered by a separate agreement. + * + * Xilinx is providing this design, code, or information + * "as-is" solely for use in developing programs and + * solutions for Xilinx devices, with no obligation on the + * part of Xilinx to provide support. By providing this design, + * code, or information as one possible implementation of + * this feature, application or standard, Xilinx is making no + * representation that this implementation is free from any + * claims of infringement. You are responsible for obtaining + * any rights you may require for your implementation. + * Xilinx expressly disclaims any warranty whatsoever with + * respect to the adequacy of the implementation, including + * but not limited to any warranties or representations that this + * implementation is free from claims of infringement, implied + * warranties of merchantability or fitness for a particular + * purpose. + * + * Xilinx products are not intended for use in life support + * appliances, devices, or systems. Use in such applications is + * expressly prohibited. + * + * Any modifications that are made to the Source Code are + * done at the user's sole risk and will be unsupported. + * The Xilinx Support Hotline does not have access to source + * code and therefore cannot answer specific questions related + * to source HDL. The Xilinx Hotline support of original source + * code IP shall only address issues and questions related + * to the standard Netlist version of the core (and thus + * indirectly, the original core source). + * + * This copyright and support notice must be retained as part + * of this text at all times. (c) Copyright 1995-2005 Xilinx, Inc. + * All rights reserved. + * + ***************************************************************************** + * + * Filename: BLK_MEM_GEN_V2_5.v + * + * Description: + * This file is the Verilog behvarial model for the + * Block Memory Generator Core. + * + ***************************************************************************** + * Author: Xilinx + * + * History: January 11, 2006 Initial revision + *****************************************************************************/ +`timescale 1ps/1ps + +module BLK_MEM_GEN_V2_5_output_stage + #(parameter C_DATA_WIDTH = 32, + parameter C_HAS_SSR = 0, + parameter C_SINIT_VAL = "0", + parameter C_HAS_REGCE = 0, + parameter C_HAS_EN = 0, + parameter C_USE_ECC = 0, + parameter C_FAMILY = "virtex5", + parameter C_XDEVICEFAMILY = "virtex5", + parameter C_USE_RAMB16BWER_RST_BHV = 0, + parameter C_HAS_MEM_OUTPUT_REGS = 0, + parameter num_stages = 1, + parameter flop_delay = 100) + (input CLK, + input SSR, + input REGCE, + input EN, + input [C_DATA_WIDTH-1:0] DIN, + output reg [C_DATA_WIDTH-1:0] DOUT); + + localparam reg_stages = (num_stages == 0) ? 0 : num_stages-1; + reg [C_DATA_WIDTH*reg_stages-1:0] out_regs; + reg [C_DATA_WIDTH*8-1:0] sinit_str = C_SINIT_VAL; + reg [C_DATA_WIDTH-1:0] sinit_val; + + // Wire off optional inputs based on parameters + //--------------------------------------------- + wire en_i; + wire regce_i; + wire ssr_i; + //Internal enable for output registers is tied to user EN or '1' depending + // on parameters + // For V4 ECC, EN is always 1 + // Virtex-4 ECC Not Yet Supported + assign en_i = (C_HAS_EN==0 || EN) + || (C_USE_ECC && C_FAMILY=="virtex4"); + //Internal enable is tied to user REGCE, EN or '1' depending on parameters + // For V4 ECC, REGCE is always 1 + // Virtex-4 ECC Not Yet Supported + assign regce_i = ((C_HAS_REGCE==1) && REGCE) || + ((C_HAS_REGCE==0) && (C_HAS_EN==0 || EN)) + || (C_USE_ECC && C_FAMILY=="virtex4"); + //Internal SRR is tied to user SSR or '0' depending on parameters + assign ssr_i = (C_HAS_SSR==1) && SSR; + + initial begin + // Power on: load up the output registers and latches + if (!($sscanf(sinit_str, "%h", sinit_val))) begin + sinit_val = 0; + end + DOUT = sinit_val; + // This will be one wider than need, but 0 is an error + out_regs = {(reg_stages+1){sinit_val}}; + end + + generate if (num_stages == 0) begin : zero_stages + always @* begin + DOUT = DIN; + end + end + endgenerate + + // Because c_use_ramb16bwer_rst_bhv is common for both Port A and Port B, + // the corresponding C_HAS_MEM_OUTPUT_REGS_* has to be checked to determine + // the DOUT reset behavior for each port. + + // Possible valid combinations: (assuming C_HAS_MUX_OUTPUT_REGS_[A/B]=0) + // Note: C_HAS_MUX_OUTPUT_REGS_*=0 when (C_HAS_MEM_OUTPUT_REGS_*=1 AND + // C_USE_RAMB16BWER_RST_BHV=1 AND + // C_HAS_SSR*=1) + + // +-----------------------------+------------+------------------------+ + // |C_USE_RAMB16BWER|C_HAS_MEM |C_HAS_MEM | Reset Behavior | + // | _RST_BHV |_OUTPUT_REGS|_OUTPUT_REGS| | + // | | _A | _B | | + // +----------------+------------+------------+------------------------+ + // | 0 | x | x | A/B=Normal | + // +----------------+------------+------------+------------------------+ + // | 1 | 1 | 0 |A=Special if HAS_SSRA=1 | + // | | | |B=Normal | + // +----------------+------------+------------+------------------------+ + // | 1 | 0 | 1 |A=Normal | + // | | | |B=Special if HAS_SSRB=1 | + // +----------------+------------+------------+------------------------+ + // | 1 | 1 | 1 |A=Special if HAS_SSRA=1 | + // | | | |B=Special if HAS_SSRB=1 | + // +----------------+------------+------------+------------------------+ + // + // x = anything + // Normal = Normal V5 like behavior + // Special = Special RAMB16BWER primitive behavior for Spartan-3adsp + + generate if (num_stages == 1 && + (C_USE_RAMB16BWER_RST_BHV==0 || + C_HAS_MEM_OUTPUT_REGS==0 || + C_HAS_SSR==0)) begin : one_stages_norm + + always @(posedge CLK) begin + if (regce_i && ssr_i) begin + DOUT <= #flop_delay sinit_val; + end else if (regce_i) begin + DOUT <= #flop_delay DIN; + end + end + end + endgenerate + + generate if (num_stages == 1 && + C_USE_RAMB16BWER_RST_BHV==1 && + C_HAS_MEM_OUTPUT_REGS==1 && + C_HAS_SSR==1 ) begin : one_stages_s3adsp + + always @(posedge CLK) begin + if (en_i && ssr_i) begin + DOUT <= #flop_delay sinit_val; + end else if (regce_i) begin + DOUT <= #flop_delay DIN; + end + end + end + endgenerate + + generate if (num_stages > 1) begin : multi_stage + always @(posedge CLK) begin + if (regce_i && ssr_i) begin + DOUT <= #flop_delay sinit_val; + end else if (regce_i) begin + DOUT <= #flop_delay + out_regs[C_DATA_WIDTH*(num_stages-2)+:C_DATA_WIDTH]; + end + + if (en_i) begin + out_regs <= #flop_delay + (out_regs << C_DATA_WIDTH) | DIN; + end + end + end + endgenerate +endmodule + +module BLK_MEM_GEN_V2_5 + #(parameter C_ADDRA_WIDTH = 5, + parameter C_ADDRB_WIDTH = 5, + parameter C_ALGORITHM = 2, + parameter C_BYTE_SIZE = 8, + parameter C_COMMON_CLK = 1, + parameter C_CORENAME = "blk_mem_gen_v2_5", + parameter C_DEFAULT_DATA = "0", + parameter C_DISABLE_WARN_BHV_COLL = 0, + parameter C_DISABLE_WARN_BHV_RANGE = 0, + parameter C_FAMILY = "virtex4", + parameter C_HAS_ENA = 1, + parameter C_HAS_ENB = 1, + parameter C_HAS_MEM_OUTPUT_REGS_A = 0, + parameter C_HAS_MEM_OUTPUT_REGS_B = 0, + parameter C_HAS_MUX_OUTPUT_REGS_A = 0, + parameter C_HAS_MUX_OUTPUT_REGS_B = 0, + parameter C_HAS_REGCEA = 0, + parameter C_HAS_REGCEB = 0, + parameter C_HAS_SSRA = 0, + parameter C_HAS_SSRB = 0, + parameter C_INIT_FILE_NAME = "", + parameter C_LOAD_INIT_FILE = 0, + parameter C_MEM_TYPE = 2, + parameter C_PRIM_TYPE = 3, + parameter C_READ_DEPTH_A = 64, + parameter C_READ_DEPTH_B = 64, + parameter C_READ_WIDTH_A = 32, + parameter C_READ_WIDTH_B = 32, + parameter C_SIM_COLLISION_CHECK = "NONE", + parameter C_SINITA_VAL = "0", + parameter C_SINITB_VAL = "0", + parameter C_USE_BYTE_WEA = 0, + parameter C_USE_BYTE_WEB = 0, + parameter C_USE_DEFAULT_DATA = 0, + parameter C_USE_ECC = 0, + parameter C_USE_RAMB16BWER_RST_BHV = 0, + parameter C_WEA_WIDTH = 1, + parameter C_WEB_WIDTH = 1, + parameter C_WRITE_DEPTH_A = 64, + parameter C_WRITE_DEPTH_B = 64, + parameter C_WRITE_MODE_A = "WRITE_FIRST", + parameter C_WRITE_MODE_B = "WRITE_FIRST", + parameter C_WRITE_WIDTH_A = 32, + parameter C_WRITE_WIDTH_B = 32, + parameter C_XDEVICEFAMILY = "virtex4" +) + (input CLKA, + input [C_WRITE_WIDTH_A-1:0] DINA, + input [C_ADDRA_WIDTH-1:0] ADDRA, + input ENA, + input REGCEA, + input [C_WEA_WIDTH-1:0] WEA, + input SSRA, + output [C_READ_WIDTH_A-1:0] DOUTA, + input CLKB, + input [C_WRITE_WIDTH_B-1:0] DINB, + input [C_ADDRB_WIDTH-1:0] ADDRB, + input ENB, + input REGCEB, + input [C_WEB_WIDTH-1:0] WEB, + input SSRB, + output [C_READ_WIDTH_B-1:0] DOUTB, + output DBITERR, + output SBITERR + ); + + // constants for the core behavior + //================================ + // file handles for logging + //------------------------------------------------------ + localparam addrfile = 32'h8000_0001; // stdout for addr out of range + localparam collfile = 32'h8000_0001; // stdout for coll detection + localparam errfile = 32'h8000_0001; // stdout for file I/O errors + + // other constants + //------------------------------------------------------ + localparam coll_delay = 2000; // 2 ns + + // locally derived parameters to determine memory shape + //----------------------------------------------------- + localparam min_width_a = (C_WRITE_WIDTH_A < C_READ_WIDTH_A) ? + C_WRITE_WIDTH_A : C_READ_WIDTH_A; + localparam min_width_b = (C_WRITE_WIDTH_B < C_READ_WIDTH_B) ? + C_WRITE_WIDTH_B : C_READ_WIDTH_B; + localparam min_width = (min_width_a < min_width_b) ? + min_width_a : min_width_b; + + localparam max_width_a = (C_WRITE_WIDTH_A > C_READ_WIDTH_A) ? + C_WRITE_WIDTH_A : C_READ_WIDTH_A; + localparam max_width_b = (C_WRITE_WIDTH_B > C_READ_WIDTH_B) ? + C_WRITE_WIDTH_B : C_READ_WIDTH_B; + localparam max_width = (max_width_a > max_width_b) ? + max_width_a : max_width_b; + + localparam max_depth_a = (C_WRITE_DEPTH_A > C_READ_DEPTH_A) ? + C_WRITE_DEPTH_A : C_READ_DEPTH_A; + localparam max_depth_b = (C_WRITE_DEPTH_B > C_READ_DEPTH_B) ? + C_WRITE_DEPTH_B : C_READ_DEPTH_B; + localparam max_depth = (max_depth_a > max_depth_b) ? + max_depth_a : max_depth_b; + + + // locally derived parameters to assist memory access + //---------------------------------------------------- + localparam write_width_ratio_a = C_WRITE_WIDTH_A/min_width; + localparam read_width_ratio_a = C_READ_WIDTH_A/min_width; + localparam write_width_ratio_b = C_WRITE_WIDTH_B/min_width; + localparam read_width_ratio_b = C_READ_WIDTH_B/min_width; + + // To modify the LSBs of the 'wider' data to the actual + // address value + //---------------------------------------------------- + localparam write_addr_a_div = C_WRITE_WIDTH_A/min_width_a; + localparam read_addr_a_div = C_READ_WIDTH_A/min_width_a; + localparam write_addr_b_div = C_WRITE_WIDTH_B/min_width_b; + localparam read_addr_b_div = C_READ_WIDTH_B/min_width_b; + + // If byte writes aren't being used, make sure byte_size is not + // wider than the memory elements to avoid compilation warnings + localparam byte_size = (C_BYTE_SIZE < min_width) ? C_BYTE_SIZE : min_width; + + // the memory + reg [min_width-1:0] memory [0:max_depth-1]; + // memory output 'latches' + reg [C_READ_WIDTH_A-1:0] memory_out_a; + reg [C_READ_WIDTH_B-1:0] memory_out_b; + // reset values + reg [C_READ_WIDTH_A-1:0] sinita_val; + reg [C_READ_WIDTH_B-1:0] sinitb_val; + + // collision detect + reg is_collision; + reg is_collision_a, is_collision_delay_a; + reg is_collision_b, is_collision_delay_b; + + // temporary variables for initialization + //--------------------------------------- + integer status; + reg [639:0] err_str; + integer initfile; + // data input buffer + reg [C_WRITE_WIDTH_A-1:0] mif_data; + // string values in hex + reg [C_READ_WIDTH_A*8-1:0] sinita_str = C_SINITA_VAL; + reg [C_READ_WIDTH_B*8-1:0] sinitb_str = C_SINITB_VAL; + reg [C_WRITE_WIDTH_A*8-1:0] default_data_str = C_DEFAULT_DATA; + // initialization filename + reg [1023*8-1:0] init_file_str = C_INIT_FILE_NAME; + + // internal configuration parameters + //--------------------------------------------- + localparam flop_delay = 100; // 100 ps + localparam single_port = (C_MEM_TYPE==0 || C_MEM_TYPE==3); + localparam is_rom = (C_MEM_TYPE==3 || C_MEM_TYPE==4); + localparam has_a_write = (!is_rom); + localparam has_b_write = (C_MEM_TYPE==2); + localparam has_a_read = (C_MEM_TYPE!=1); + localparam has_b_read = (!single_port); + localparam has_b_port = (has_b_read || has_b_write); + // Virtex-4 ECC Not Yet Supported + localparam num_output_stages_a = (C_FAMILY=="virtex4" && C_USE_ECC==1) ? + (C_HAS_MEM_OUTPUT_REGS_A + C_HAS_MUX_OUTPUT_REGS_A + 1) : + (C_HAS_MEM_OUTPUT_REGS_A + C_HAS_MUX_OUTPUT_REGS_A); + + localparam num_output_stages_b = (C_FAMILY=="virtex4" && C_USE_ECC==1) ? + (C_HAS_MEM_OUTPUT_REGS_B + C_HAS_MUX_OUTPUT_REGS_B + 1) : + (C_HAS_MEM_OUTPUT_REGS_B + C_HAS_MUX_OUTPUT_REGS_B); + wire ena_i; + wire enb_i; + wire reseta_i; + wire resetb_i; + wire [C_WEA_WIDTH-1:0] wea_i; + wire [C_WEB_WIDTH-1:0] web_i; + wire rea_i; + wire reb_i; + + // ECC SBITERR/DBITERR Outputs + // The ECC Behavior is not modeled by the behavioral models, therefore + // the SBITERR and DBITERR outputs are explicitly tied to 0. + assign SBITERR = 0; + assign DBITERR = 0; + + + // This effectively wires off optional inputs + assign ena_i = (C_HAS_ENA==0) || ENA; + assign enb_i = ((C_HAS_ENB==0) || ENB) && has_b_port; + assign wea_i = (has_a_write && ena_i) ? WEA : 'b0; + assign web_i = (has_b_write && enb_i) ? WEB : 'b0; + assign rea_i = (has_a_read) ? ena_i : 'b0; + assign reb_i = (has_b_read) ? enb_i : 'b0; + + // these signals reset the memory latches + // Because c_use_ramb16bwer_rst_bhv is common for both Port A and Port B, + // the corresponding C_HAS_MEM_OUTPUT_REG_* has to be checked as well to determine + // the reset behavior for each port. + + assign reseta_i = ((C_HAS_SSRA==1 && SSRA && ena_i && num_output_stages_a==0) || + (C_HAS_SSRA==1 && SSRA && ena_i && C_USE_RAMB16BWER_RST_BHV==1 && C_HAS_MEM_OUTPUT_REGS_A==1 && C_HAS_MUX_OUTPUT_REGS_A==0)); + assign resetb_i = ((C_HAS_SSRB==1 && SSRB && enb_i && num_output_stages_b==0) || + (C_HAS_SSRB==1 && SSRB && enb_i && C_USE_RAMB16BWER_RST_BHV==1 && C_HAS_MEM_OUTPUT_REGS_B==1 && C_HAS_MUX_OUTPUT_REGS_B==0)); + + // tasks to access the memory + //--------------------------- + task write_a + (input reg [C_ADDRA_WIDTH-1:0] addr, + input reg [C_WEA_WIDTH-1:0] byte_en, + input reg [C_WRITE_WIDTH_A-1:0] data); + reg [C_WRITE_WIDTH_A-1:0] current_contents; + reg [C_ADDRA_WIDTH-1:0] address; + integer i; + begin + // Shift the address by the ratio + address = (addr/write_addr_a_div); + if (address >= C_WRITE_DEPTH_A) begin + if (!C_DISABLE_WARN_BHV_RANGE) begin + $fdisplay(addrfile, + "%0s WARNING: Address %0h is outside range for A Write", + C_CORENAME, addr); + end + + // valid address + end else begin + + // Combine w/ byte writes + if (C_USE_BYTE_WEA) begin + + // Get the current memory contents + if (write_width_ratio_a == 1) begin + // Workaround for IUS 5.5 part-select issue + current_contents = memory[address]; + end else begin + for (i = 0; i < write_width_ratio_a; i = i + 1) begin + current_contents[min_width*i+:min_width] + = memory[address*write_width_ratio_a + i]; + end + end + + // Apply incoming bytes + if (C_WEA_WIDTH == 1) begin + // Workaround for IUS 5.5 part-select issue + if (byte_en[0]) begin + current_contents = data; + end + end else begin + for (i = 0; i < C_WEA_WIDTH; i = i + 1) begin + if (byte_en[i]) begin + current_contents[byte_size*i+:byte_size] + = data[byte_size*i+:byte_size]; + end + end + end + + // No byte-writes, overwrite the whole word + end else begin + current_contents = data; + end + + // Write data to memory + if (write_width_ratio_a == 1) begin + // Workaround for IUS 5.5 part-select issue + memory[address*write_width_ratio_a] = current_contents; + end else begin + for (i = 0; i < write_width_ratio_a; i = i + 1) begin + memory[address*write_width_ratio_a + i] + = current_contents[min_width*i+:min_width]; + end + end + + end + end + endtask + + task write_b + (input reg [C_ADDRB_WIDTH-1:0] addr, + input reg [C_WEB_WIDTH-1:0] byte_en, + input reg [C_WRITE_WIDTH_B-1:0] data); + reg [C_WRITE_WIDTH_B-1:0] current_contents; + reg [C_ADDRB_WIDTH-1:0] address; + integer i; + begin + // Shift the address by the ratio + address = (addr/write_addr_b_div); + if (address >= C_WRITE_DEPTH_B) begin + if (!C_DISABLE_WARN_BHV_RANGE) begin + $fdisplay(addrfile, + "%0s WARNING: Address %0h is outside range for B Write", + C_CORENAME, addr); + end + + // valid address + end else begin + + // Combine w/ byte writes + if (C_USE_BYTE_WEB) begin + + // Get the current memory contents + if (write_width_ratio_b == 1) begin + // Workaround for IUS 5.5 part-select issue + current_contents = memory[address]; + end else begin + for (i = 0; i < write_width_ratio_b; i = i + 1) begin + current_contents[min_width*i+:min_width] + = memory[address*write_width_ratio_b + i]; + end + end + + // Apply incoming bytes + if (C_WEB_WIDTH == 1) begin + // Workaround for IUS 5.5 part-select issue + if (byte_en[0]) begin + current_contents = data; + end + end else begin + for (i = 0; i < C_WEB_WIDTH; i = i + 1) begin + if (byte_en[i]) begin + current_contents[byte_size*i+:byte_size] + = data[byte_size*i+:byte_size]; + end + end + end + + // No byte-writes, overwrite the whole word + end else begin + current_contents = data; + end + + // Write data to memory + if (write_width_ratio_b == 1) begin + // Workaround for IUS 5.5 part-select issue + memory[address*write_width_ratio_b] = current_contents; + end else begin + for (i = 0; i < write_width_ratio_b; i = i + 1) begin + memory[address*write_width_ratio_b + i] + = current_contents[min_width*i+:min_width]; + end + end + end + end + endtask + + task read_a + (input reg [C_ADDRA_WIDTH-1:0] addr, + input reg reset); + reg [C_ADDRA_WIDTH-1:0] address; + integer i; + begin + + if (reset) begin + memory_out_a <= #flop_delay sinita_val; + end else begin + // Shift the address by the ratio + address = (addr/read_addr_a_div); + if (address >= C_READ_DEPTH_A) begin + if (!C_DISABLE_WARN_BHV_RANGE) begin + $fdisplay(addrfile, + "%0s WARNING: Address %0h is outside range for A Read", + C_CORENAME, addr); + end + + // valid address + end else begin + + if (read_width_ratio_a==1) begin + memory_out_a <= #flop_delay memory[address*read_width_ratio_a]; + end else begin + // Increment through the 'partial' words in the memory + for (i = 0; i < read_width_ratio_a; i = i + 1) begin + memory_out_a[min_width*i+:min_width] + <= #flop_delay memory[address*read_width_ratio_a + i]; + end + end + + end + end + end + endtask + + task read_b + (input reg [C_ADDRB_WIDTH-1:0] addr, + input reg reset); + reg [C_ADDRB_WIDTH-1:0] address; + integer i; + begin + + if (reset) begin + memory_out_b <= #flop_delay sinitb_val; + end else begin + // Shift the address + address = (addr/read_addr_b_div); + if (address >= C_READ_DEPTH_B) begin + if (!C_DISABLE_WARN_BHV_RANGE) begin + $fdisplay(addrfile, + "%0s WARNING: Address %0h is outside range for B Read", + C_CORENAME, addr); + end + + // valid address + end else begin + + if (read_width_ratio_b==1) begin + memory_out_b <= #flop_delay memory[address*read_width_ratio_b]; + end else begin + // Increment through the 'partial' words in the memory + for (i = 0; i < read_width_ratio_b; i = i + 1) begin + memory_out_b[min_width*i+:min_width] + <= #flop_delay memory[address*read_width_ratio_b + i]; + end + end + + end + end + end + endtask + + task init_memory; + integer i, addr_step; + integer status; + reg [C_WRITE_WIDTH_A-1:0] default_data; + begin + default_data = 0; + + //Display output message indicating that the behavioral model is being initialized + if (C_USE_DEFAULT_DATA || C_LOAD_INIT_FILE) $display(" Block Memory Generator CORE Generator module loading initial data..."); + + // Convert the default to hex + if (C_USE_DEFAULT_DATA) begin + if (default_data_str == "") begin + $fdisplay(errfile, "%0s ERROR: C_DEFAULT_DATA is empty!", C_CORENAME); + $finish; + end else begin + status = $sscanf(default_data_str, "%h", default_data); + if (status == 0) begin + $fdisplay(errfile, {"%0s ERROR: Unsuccessful hexadecimal read", + "from C_DEFAULT_DATA: %0s"}, + C_CORENAME, C_DEFAULT_DATA); + $finish; + end + end + end + + // Step by write_addr_a_div through the memory via the + // Port A write interface to hit every location once + addr_step = write_addr_a_div; + + // 'write' to every location with default (or 0) + for (i = 0; i < C_WRITE_DEPTH_A*addr_step; i = i + addr_step) begin + write_a(i, {C_WEA_WIDTH{1'b1}}, default_data); + end + + // Get specialized data from the MIF file + if (C_LOAD_INIT_FILE) begin + if (init_file_str == "") begin + $fdisplay(errfile, "%0s ERROR: C_INIT_FILE_NAME is empty!", + C_CORENAME); + $finish; + end else begin + initfile = $fopen(init_file_str, "r"); + if (initfile == 0) begin + $fdisplay(errfile, {"%0s, ERROR: Problem opening", + "C_INIT_FILE_NAME: %0s!"}, + C_CORENAME, init_file_str); + $finish; + end else begin + // loop through the mif file, loading in the data + for (i = 0; i < C_WRITE_DEPTH_A*addr_step; i = i + addr_step) begin + status = $fscanf(initfile, "%b", mif_data); + if (status > 0) begin + write_a(i, {C_WEA_WIDTH{1'b1}}, mif_data); + end + end + $fclose(initfile); + end //initfile + end //init_file_str + end //C_LOAD_INIT_FILE + + //Display output message indicating that the behavioral model is done initializing + if (C_USE_DEFAULT_DATA || C_LOAD_INIT_FILE) $display(" Block Memory Generator data initialization complete."); + + + end + endtask + + function integer log2roundup (input integer data_value); + integer width; + integer cnt; + begin + width = 0; + + if (data_value > 1) begin + for(cnt=1 ; cnt < data_value ; cnt = cnt * 2) begin + width = width + 1; + end //loop + end //if + + log2roundup = width; + + end //log2roundup + endfunction + + + + function integer collision_check (input reg [C_ADDRA_WIDTH-1:0] addr_a, + input integer iswrite_a, + input reg [C_ADDRB_WIDTH-1:0] addr_b, + input integer iswrite_b); + reg [C_ADDRA_WIDTH-1:0] base_addr_a; + reg [C_ADDRB_WIDTH-1:0] base_addr_b; + integer ratio_a, ratio_b; + integer lo_addr_wider, hi_addr_wider; + integer lo_addr_narrow, hi_addr_narrow; + reg c_aw_bw, c_aw_br, c_ar_bw; + integer write_addr_a_width, read_addr_a_width; + integer write_addr_b_width, read_addr_b_width; + + begin + + c_aw_bw = 0; + c_aw_br = 0; + c_ar_bw = 0; + + // Determine the effective address widths for each of the 4 ports + write_addr_a_width = C_ADDRA_WIDTH-log2roundup(write_addr_a_div); + read_addr_a_width = C_ADDRA_WIDTH-log2roundup(read_addr_a_div); + write_addr_b_width = C_ADDRB_WIDTH-log2roundup(write_addr_b_div); + read_addr_b_width = C_ADDRB_WIDTH-log2roundup(read_addr_b_div); + + + //Look for a write-write collision. In order for a write-write + //collision to exist, both ports must have a write transaction. + if (iswrite_a && iswrite_b) begin + if (write_addr_a_width > write_addr_b_width) begin + //write_addr_b_width is smaller, so scale both addresses to that + // width for comparing write_addr_a and write_addr_b + //addr_a starts as C_ADDRA_WIDTH, + // scale it down to write_addr_b_width + //addr_b starts as C_ADDRB_WIDTH, + // scale it down to write_addr_b_width + //Once both are scaled to write_addr_b_width, compare. + if (((addr_a)/2**(C_ADDRA_WIDTH-write_addr_b_width)) == ((addr_b)/2**(C_ADDRB_WIDTH-write_addr_b_width))) begin + c_aw_bw = 1; + end else begin + c_aw_bw = 0; + end + end else begin + //write_addr_a_width is smaller, so scale both addresses to that + // width for comparing write_addr_a and write_addr_b + //addr_a starts as C_ADDRA_WIDTH, + // scale it down to write_addr_a_width + //addr_b starts as C_ADDRB_WIDTH, + // scale it down to write_addr_a_width + //Once both are scaled to write_addr_a_width, compare. + if (((addr_b)/2**(C_ADDRB_WIDTH-write_addr_a_width)) == ((addr_a)/2**(C_ADDRA_WIDTH-write_addr_a_width))) begin + c_aw_bw = 1; + end else begin + c_aw_bw = 0; + end + end //width + end //iswrite_a and iswrite_b + + //If the B port is reading (which means it is enabled - so could be + // a TX_WRITE or TX_READ), then check for a write-read collision). + //This could happen whether or not a write-write collision exists due + // to asymmetric write/read ports. + if (iswrite_a) begin + if (write_addr_a_width > read_addr_b_width) begin + //read_addr_b_width is smaller, so scale both addresses to that + // width for comparing write_addr_a and read_addr_b + //addr_a starts as C_ADDRA_WIDTH, + // scale it down to read_addr_b_width + //addr_b starts as C_ADDRB_WIDTH, + // scale it down to read_addr_b_width + //Once both are scaled to read_addr_b_width, compare. + if (((addr_a)/2**(C_ADDRA_WIDTH-read_addr_b_width)) == ((addr_b)/2**(C_ADDRB_WIDTH-read_addr_b_width))) begin + c_aw_br = 1; + end else begin + c_aw_br = 0; + end + end else begin + //write_addr_a_width is smaller, so scale both addresses to that + // width for comparing write_addr_a and read_addr_b + //addr_a starts as C_ADDRA_WIDTH, + // scale it down to write_addr_a_width + //addr_b starts as C_ADDRB_WIDTH, + // scale it down to write_addr_a_width + //Once both are scaled to write_addr_a_width, compare. + if (((addr_b)/2**(C_ADDRB_WIDTH-write_addr_a_width)) == ((addr_a)/2**(C_ADDRA_WIDTH-write_addr_a_width))) begin + c_aw_br = 1; + end else begin + c_aw_br = 0; + end + end //width + end //iswrite_a + + //If the A port is reading (which means it is enabled - so could be + // a TX_WRITE or TX_READ), then check for a write-read collision). + //This could happen whether or not a write-write collision exists due + // to asymmetric write/read ports. + if (iswrite_b) begin + if (read_addr_a_width > write_addr_b_width) begin + //write_addr_b_width is smaller, so scale both addresses to that + // width for comparing read_addr_a and write_addr_b + //addr_a starts as C_ADDRA_WIDTH, + // scale it down to write_addr_b_width + //addr_b starts as C_ADDRB_WIDTH, + // scale it down to write_addr_b_width + //Once both are scaled to write_addr_b_width, compare. + if (((addr_a)/2**(C_ADDRA_WIDTH-write_addr_b_width)) == ((addr_b)/2**(C_ADDRB_WIDTH-write_addr_b_width))) begin + c_ar_bw = 1; + end else begin + c_ar_bw = 0; + end + end else begin + //read_addr_a_width is smaller, so scale both addresses to that + // width for comparing read_addr_a and write_addr_b + //addr_a starts as C_ADDRA_WIDTH, + // scale it down to read_addr_a_width + //addr_b starts as C_ADDRB_WIDTH, + // scale it down to read_addr_a_width + //Once both are scaled to read_addr_a_width, compare. + if (((addr_b)/2**(C_ADDRB_WIDTH-read_addr_a_width)) == ((addr_a)/2**(C_ADDRA_WIDTH-read_addr_a_width))) begin + c_ar_bw = 1; + end else begin + c_ar_bw = 0; + end + end //width + end //iswrite_b + + + // Convert the input addresses in base and offsets for our + // memory array. Ignore LSBs for asymmetric ports + if (iswrite_a) begin + base_addr_a = (addr_a/write_addr_a_div) * write_addr_a_div; + ratio_a = write_width_ratio_a; + end else begin + base_addr_a = (addr_a/read_addr_a_div) * read_addr_a_div; + ratio_a = read_width_ratio_a; + end + if (iswrite_b) begin + base_addr_b = (addr_b/write_addr_b_div) * write_addr_b_div; + ratio_b = write_width_ratio_b; + end else begin + base_addr_b = (addr_b/read_addr_b_div) * read_addr_b_div; + ratio_b = read_width_ratio_b; + end + + // Determine the wider port, and normalized ranges + if (ratio_a >= ratio_b) begin + lo_addr_wider = base_addr_a * ratio_a; + hi_addr_wider = lo_addr_wider + ratio_a; + lo_addr_narrow = base_addr_b * ratio_b; + hi_addr_narrow = lo_addr_narrow + ratio_b; + end else begin + lo_addr_wider = base_addr_b * ratio_b; + hi_addr_wider = lo_addr_wider + ratio_b; + lo_addr_narrow = base_addr_a * ratio_a; + hi_addr_narrow = lo_addr_narrow + ratio_a; + end + + // compare the two ranges of address (narrow inside wider) + //if ((lo_addr_narrow >= lo_addr_wider) && + // (hi_addr_narrow <= hi_addr_wider)) begin + // collision_check = 1; + //end else begin + // collision_check = 0; + //end + + collision_check = c_aw_bw | c_aw_br | c_ar_bw; + + end + endfunction + + // power on values + //----------------------------- + initial begin + // Load up the memory + init_memory; + // Load up the output registers and latches + if ($sscanf(sinita_str, "%h", sinita_val)) begin + memory_out_a = sinita_val; + end else begin + memory_out_a = 0; + end + if ($sscanf(sinitb_str, "%h", sinitb_val)) begin + memory_out_b = sinitb_val; + end else begin + memory_out_b = 0; + end + + $display("Block Memory Generator CORE Generator module %m is using a behavioral model for simulation which will not precisely model memory collision behavior."); + + end + + //------------------------------------------------------------------------- + // These are the main blocks which schedule read and write operations + //------------------------------------------------------------------------- + + generate if (C_COMMON_CLK) begin : common_clk_scheduling + // Synchronous clocks: schedule port operations with respect to + // both write operating modes + always @(posedge CLKA) begin + case ({C_WRITE_MODE_A, C_WRITE_MODE_B}) + {"WRITE_FIRST","WRITE_FIRST"}: begin + if (wea_i) write_a(ADDRA, wea_i, DINA); + if (web_i) write_b(ADDRB, web_i, DINB); + if (rea_i) read_a(ADDRA, reseta_i); + if (reb_i) read_b(ADDRB, resetb_i); + end + {"READ_FIRST", "WRITE_FIRST"}: begin + if (web_i) write_b(ADDRB, web_i, DINB); + if (reb_i) read_b(ADDRB, resetb_i); + if (rea_i) read_a(ADDRA, reseta_i); + if (wea_i) write_a(ADDRA, wea_i, DINA); + end + {"WRITE_FIRST","READ_FIRST"}: begin + if (wea_i) write_a(ADDRA, wea_i, DINA); + if (rea_i) read_a(ADDRA, reseta_i); + if (reb_i) read_b(ADDRB, resetb_i); + if (web_i) write_b(ADDRB, web_i, DINB); + end + {"READ_FIRST", "READ_FIRST"}: begin + if (rea_i) read_a(ADDRA, reseta_i); + if (reb_i) read_b(ADDRB, resetb_i); + if (wea_i) write_a(ADDRA, wea_i, DINA); + if (web_i) write_b(ADDRB, web_i, DINB); + end + {"WRITE_FIRST","NO_CHANGE"}: begin + if (wea_i) write_a(ADDRA, wea_i, DINA); + if (rea_i) read_a(ADDRA, reseta_i); + if ((reb_i && !web_i) || resetb_i) read_b(ADDRB, resetb_i); + if (web_i) write_b(ADDRB, web_i, DINB); + end + {"READ_FIRST", "NO_CHANGE"}: begin + if (rea_i) read_a(ADDRA, reseta_i); + if ((reb_i && !web_i) || resetb_i) read_b(ADDRB, resetb_i); + if (wea_i) write_a(ADDRA, wea_i, DINA); + if (web_i) write_b(ADDRB, web_i, DINB); + end + {"NO_CHANGE", "WRITE_FIRST"}: begin + if (wea_i) write_a(ADDRA, wea_i, DINA); + if (web_i) write_b(ADDRB, web_i, DINB); + if ((rea_i && !wea_i) || reseta_i) read_a(ADDRA, reseta_i); + if (reb_i) read_b(ADDRB, resetb_i); + end + {"NO_CHANGE", "READ_FIRST"}: begin + if (reb_i) read_b(ADDRB, resetb_i); + if ((rea_i && !wea_i) || reseta_i) read_a(ADDRA, reseta_i); + if (wea_i) write_a(ADDRA, wea_i, DINA); + if (web_i) write_b(ADDRB, web_i, DINB); + end + {"NO_CHANGE", "NO_CHANGE"}: begin + if (wea_i) write_a(ADDRA, wea_i, DINA); + if (web_i) write_b(ADDRB, web_i, DINB); + if ((rea_i && !wea_i) || reseta_i) read_a(ADDRA, reseta_i); + if ((reb_i && !web_i) || resetb_i) read_b(ADDRB, resetb_i); + end + default: begin + if (wea_i) write_a(ADDRA, wea_i, DINA); + if (web_i) write_b(ADDRB, web_i, DINB); + if (rea_i) read_a(ADDRA, reseta_i); + if (reb_i) read_b(ADDRB, resetb_i); + end + endcase + end + + end else begin : asynch_clk_scheduling + // Asynchronous clocks: port operation is independent + always @(posedge CLKA) begin + case (C_WRITE_MODE_A) + "WRITE_FIRST": begin + if (wea_i) write_a(ADDRA, wea_i, DINA); + if (rea_i) read_a(ADDRA, reseta_i); + end + "READ_FIRST": begin + if (rea_i) read_a(ADDRA, reseta_i); + if (wea_i) write_a(ADDRA, wea_i, DINA); + end + "NO_CHANGE": begin + if (wea_i) write_a(ADDRA, wea_i, DINA); + if ((rea_i && !wea_i) || reseta_i) read_a(ADDRA, reseta_i); + end + endcase + end + + always @(posedge CLKB) begin + case (C_WRITE_MODE_B) + "WRITE_FIRST": begin + if (web_i) write_b(ADDRB, web_i, DINB); + if (reb_i) read_b(ADDRB, resetb_i); + end + "READ_FIRST": begin + if (reb_i) read_b(ADDRB, resetb_i); + if (web_i) write_b(ADDRB, web_i, DINB); + end + "NO_CHANGE": begin + if (web_i) write_b(ADDRB, web_i, DINB); + if ((reb_i && !web_i) || resetb_i) read_b(ADDRB, resetb_i); + end + endcase + end + end + endgenerate + + // Variable depth output stage + BLK_MEM_GEN_V2_5_output_stage + #(.C_DATA_WIDTH (C_READ_WIDTH_A), + .C_HAS_SSR (C_HAS_SSRA), + .C_SINIT_VAL (C_SINITA_VAL), + .C_HAS_REGCE (C_HAS_REGCEA), + .C_HAS_EN (C_HAS_ENA), + .C_USE_ECC (C_USE_ECC), + .C_FAMILY (C_FAMILY), + .C_XDEVICEFAMILY (C_XDEVICEFAMILY), + .C_USE_RAMB16BWER_RST_BHV (C_USE_RAMB16BWER_RST_BHV), + .C_HAS_MEM_OUTPUT_REGS (C_HAS_MEM_OUTPUT_REGS_A), + .num_stages (num_output_stages_a), + .flop_delay (flop_delay)) + reg_a + (.CLK (CLKA), + .SSR (SSRA), + .REGCE (REGCEA), + .EN (ENA), + .DIN (memory_out_a), + .DOUT (DOUTA)); + + BLK_MEM_GEN_V2_5_output_stage + #(.C_DATA_WIDTH (C_READ_WIDTH_B), + .C_HAS_SSR (C_HAS_SSRB), + .C_SINIT_VAL (C_SINITB_VAL), + .C_HAS_REGCE (C_HAS_REGCEB), + .C_HAS_EN (C_HAS_ENB), + .C_USE_ECC (C_USE_ECC), + .C_FAMILY (C_FAMILY), + .C_XDEVICEFAMILY (C_XDEVICEFAMILY), + .C_USE_RAMB16BWER_RST_BHV (C_USE_RAMB16BWER_RST_BHV), + .C_HAS_MEM_OUTPUT_REGS (C_HAS_MEM_OUTPUT_REGS_B), + .num_stages (num_output_stages_b), + .flop_delay (flop_delay)) + reg_b + (.CLK (CLKB), + .SSR (SSRB), + .REGCE (REGCEB), + .EN (ENB), + .DIN (memory_out_b), + .DOUT (DOUTB)); + + // Synchronous collision checks + generate if (!C_DISABLE_WARN_BHV_COLL && C_COMMON_CLK) begin : sync_coll + always @(posedge CLKA) begin + // Possible collision if both are enabled and the addresses match + if (ena_i && enb_i) begin + is_collision = collision_check(ADDRA, wea_i, ADDRB, web_i); + end else begin + is_collision = 0; + end + + // If the write port is in READ_FIRST mode, there is no collision + if (C_WRITE_MODE_A=="READ_FIRST" && wea_i && !web_i) begin + is_collision = 0; + end + if (C_WRITE_MODE_B=="READ_FIRST" && web_i && !wea_i) begin + is_collision = 0; + end + + // Only flag if one of the accesses is a write + if (is_collision && (wea_i || web_i)) begin + $fwrite(collfile, "%0s collision detected at time: %0d, ", + C_CORENAME, $time); + $fwrite(collfile, "A %0s address: %0h, B %0s address: %0h\n", + wea_i ? "write" : "read", ADDRA, + web_i ? "write" : "read", ADDRB); + end + end + + // Asynchronous collision checks + end else if (!C_DISABLE_WARN_BHV_COLL && !C_COMMON_CLK) begin : async_coll + + // Delay A and B addresses in order to mimic setup/hold times + wire [C_ADDRA_WIDTH-1:0] #coll_delay addra_delay = ADDRA; + wire [0:0] #coll_delay wea_delay = wea_i; + wire #coll_delay ena_delay = ena_i; + wire [C_ADDRB_WIDTH-1:0] #coll_delay addrb_delay = ADDRB; + wire [0:0] #coll_delay web_delay = web_i; + wire #coll_delay enb_delay = enb_i; + + // Do the checks w/rt A + always @(posedge CLKA) begin + // Possible collision if both are enabled and the addresses match + if (ena_i && enb_i) begin + is_collision_a = collision_check(ADDRA, wea_i, ADDRB, web_i); + end else begin + is_collision_a = 0; + end + if (ena_i && enb_delay) begin + is_collision_delay_a = collision_check(ADDRA, wea_i, + addrb_delay, web_delay); + end else begin + is_collision_delay_a = 0; + end + + + // Only flag if B access is a write + if (is_collision_a && web_i) begin + $fwrite(collfile, "%0s collision detected at time: %0d, ", + C_CORENAME, $time); + $fwrite(collfile, "A %0s address: %0h, B write address: %0h\n", + wea_i ? "write" : "read", ADDRA, ADDRB); + + end else if (is_collision_delay_a && web_delay) begin + $fwrite(collfile, "%0s collision detected at time: %0d, ", + C_CORENAME, $time); + $fwrite(collfile, "A %0s address: %0h, B write address: %0h\n", + wea_i ? "write" : "read", ADDRA, addrb_delay); + end + + end + + // Do the checks w/rt B + always @(posedge CLKB) begin + + // Possible collision if both are enabled and the addresses match + if (ena_i && enb_i) begin + is_collision_b = collision_check(ADDRA, wea_i, ADDRB, web_i); + end else begin + is_collision_b = 0; + end + if (ena_delay && enb_i) begin + is_collision_delay_b = collision_check(addra_delay, wea_delay, + ADDRB, web_i); + end else begin + is_collision_delay_b = 0; + end + + + // Only flag if A access is a write + if (is_collision_b && wea_i) begin + $fwrite(collfile, "%0s collision detected at time: %0d, ", + C_CORENAME, $time); + $fwrite(collfile, "A write address: %0h, B %s address: %0h\n", + ADDRA, web_i ? "write" : "read", ADDRB); + + end else if (is_collision_delay_b && wea_delay) begin + $fwrite(collfile, "%0s collision detected at time: %0d, ", + C_CORENAME, $time); + $fwrite(collfile, "A write address: %0h, B %s address: %0h\n", + addra_delay, web_i ? "write" : "read", ADDRB); + end + + end + end + endgenerate + +endmodule diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/BLK_MEM_GEN_V2_5_xst.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/BLK_MEM_GEN_V2_5_xst.v new file mode 100644 index 0000000..5890db9 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/BLK_MEM_GEN_V2_5_xst.v @@ -0,0 +1,199 @@ +/****************************************************************************** + * + * Block Memory Generator Core - Block Memory Behavioral Model + * + * Copyright(C) 2005 by Xilinx, Inc. All rights reserved. + * This text/file contains proprietary, confidential + * information of Xilinx, Inc., is distributed under + * license from Xilinx, Inc., and may be used, copied + * and/or disclosed only pursuant to the terms of a valid + * license agreement with Xilinx, Inc. Xilinx hereby + * grants you a license to use this text/file solely for + * design, simulation, implementation and creation of + * design files limited to Xilinx devices or technologies. + * Use with non-Xilinx devices or technologies is expressly + * prohibited and immediately terminates your license unless + * covered by a separate agreement. + * + * Xilinx is providing this design, code, or information + * "as-is" solely for use in developing programs and + * solutions for Xilinx devices, with no obligation on the + * part of Xilinx to provide support. By providing this design, + * code, or information as one possible implementation of + * this feature, application or standard, Xilinx is making no + * representation that this implementation is free from any + * claims of infringement. You are responsible for obtaining + * any rights you may require for your implementation. + * Xilinx expressly disclaims any warranty whatsoever with + * respect to the adequacy of the implementation, including + * but not limited to any warranties or representations that this + * implementation is free from claims of infringement, implied + * warranties of merchantability or fitness for a particular + * purpose. + * + * Xilinx products are not intended for use in life support + * appliances, devices, or systems. Use in such applications is + * expressly prohibited. + * + * Any modifications that are made to the Source Code are + * done at the user's sole risk and will be unsupported. + * The Xilinx Support Hotline does not have access to source + * code and therefore cannot answer specific questions related + * to source HDL. The Xilinx Hotline support of original source + * code IP shall only address issues and questions related + * to the standard Netlist version of the core (and thus + * indirectly, the original core source). + * + * This copyright and support notice must be retained as part + * of this text at all times. (c) Copyright 1995-2005 Xilinx, Inc. + * All rights reserved. + * + ***************************************************************************** + * + * Filename: BLK_MEM_GEN_V2_5.v + * + * Description: + * This file is the Verilog behvarial model for the + * Block Memory Generator Core. + * + ***************************************************************************** + * Author: Xilinx + * + * History: September 6, 2005 Initial revision + *****************************************************************************/ +`timescale 1ps/1ps + +module BLK_MEM_GEN_V2_5_xst + #(parameter C_ADDRA_WIDTH = 5, + parameter C_ADDRB_WIDTH = 5, + parameter C_ALGORITHM = 1, + parameter C_BYTE_SIZE = 9, + parameter C_COMMON_CLK = 1, + parameter C_DEFAULT_DATA = "0", + parameter C_DISABLE_WARN_BHV_COLL = 0, + parameter C_DISABLE_WARN_BHV_RANGE = 0, + parameter C_FAMILY = "virtex5", + parameter C_HAS_ENA = 1, + parameter C_HAS_ENB = 1, + parameter C_HAS_MEM_OUTPUT_REGS_A = 0, + parameter C_HAS_MEM_OUTPUT_REGS_B = 0, + parameter C_HAS_MUX_OUTPUT_REGS_A = 0, + parameter C_HAS_MUX_OUTPUT_REGS_B = 0, + parameter C_HAS_REGCEA = 0, + parameter C_HAS_REGCEB = 0, + parameter C_HAS_SSRA = 0, + parameter C_HAS_SSRB = 0, + parameter C_INIT_FILE_NAME = "", + parameter C_LOAD_INIT_FILE = 0, + parameter C_MEM_TYPE = 2, + parameter C_PRIM_TYPE = 3, + parameter C_READ_DEPTH_A = 64, + parameter C_READ_DEPTH_B = 64, + parameter C_READ_WIDTH_A = 32, + parameter C_READ_WIDTH_B = 32, + parameter C_SIM_COLLISION_CHECK = "NONE", + parameter C_SINITA_VAL = "0", + parameter C_SINITB_VAL = "0", + parameter C_USE_BYTE_WEA = 0, + parameter C_USE_BYTE_WEB = 0, + parameter C_USE_DEFAULT_DATA = 0, + parameter C_USE_ECC = 0, + parameter C_USE_RAMB16BWER_RST_BHV = 0, + parameter C_WEA_WIDTH = 1, + parameter C_WEB_WIDTH = 1, + parameter C_WRITE_DEPTH_A = 64, + parameter C_WRITE_DEPTH_B = 64, + parameter C_WRITE_MODE_A = "WRITE_FIRST", + parameter C_WRITE_MODE_B = "WRITE_FIRST", + parameter C_WRITE_WIDTH_A = 32, + parameter C_WRITE_WIDTH_B = 32, + parameter C_XDEVICEFAMILY = "virtex5" +) + (input CLKA, + input [C_WRITE_WIDTH_A-1:0] DINA, + input [C_ADDRA_WIDTH-1:0] ADDRA, + input ENA, + input REGCEA, + input [C_WEA_WIDTH-1:0] WEA, + input SSRA, + output [C_READ_WIDTH_A-1:0] DOUTA, + input CLKB, + input [C_WRITE_WIDTH_B-1:0] DINB, + input [C_ADDRB_WIDTH-1:0] ADDRB, + input ENB, + input REGCEB, + input [C_WEB_WIDTH-1:0] WEB, + input SSRB, + output [C_READ_WIDTH_B-1:0] DOUTB, + output DBITERR, + output SBITERR); + + BLK_MEM_GEN_V2_5 + #( + .C_ADDRA_WIDTH (C_ADDRA_WIDTH), + .C_ADDRB_WIDTH (C_ADDRB_WIDTH), + .C_ALGORITHM (C_ALGORITHM), + .C_BYTE_SIZE (C_BYTE_SIZE), + .C_COMMON_CLK (C_COMMON_CLK), + .C_DEFAULT_DATA (C_DEFAULT_DATA), + .C_DISABLE_WARN_BHV_COLL (C_DISABLE_WARN_BHV_COLL), + .C_DISABLE_WARN_BHV_RANGE (C_DISABLE_WARN_BHV_RANGE), + .C_FAMILY (C_FAMILY), + .C_HAS_ENA (C_HAS_ENA), + .C_HAS_ENB (C_HAS_ENB), + .C_HAS_MEM_OUTPUT_REGS_A (C_HAS_MEM_OUTPUT_REGS_A), + .C_HAS_MEM_OUTPUT_REGS_B (C_HAS_MEM_OUTPUT_REGS_B), + .C_HAS_MUX_OUTPUT_REGS_A (C_HAS_MUX_OUTPUT_REGS_A), + .C_HAS_MUX_OUTPUT_REGS_B (C_HAS_MUX_OUTPUT_REGS_B), + .C_HAS_REGCEA (C_HAS_REGCEA), + .C_HAS_REGCEB (C_HAS_REGCEB), + .C_HAS_SSRA (C_HAS_SSRA), + .C_HAS_SSRB (C_HAS_SSRB), + .C_INIT_FILE_NAME (C_INIT_FILE_NAME), + .C_LOAD_INIT_FILE (C_LOAD_INIT_FILE), + .C_MEM_TYPE (C_MEM_TYPE), + .C_PRIM_TYPE (C_PRIM_TYPE), + .C_READ_DEPTH_A (C_READ_DEPTH_A), + .C_READ_DEPTH_B (C_READ_DEPTH_B), + .C_READ_WIDTH_A (C_READ_WIDTH_A), + .C_READ_WIDTH_B (C_READ_WIDTH_B), + .C_SIM_COLLISION_CHECK (C_SIM_COLLISION_CHECK), + .C_SINITA_VAL (C_SINITA_VAL), + .C_SINITB_VAL (C_SINITB_VAL), + .C_USE_BYTE_WEA (C_USE_BYTE_WEA), + .C_USE_BYTE_WEB (C_USE_BYTE_WEB), + .C_USE_DEFAULT_DATA (C_USE_DEFAULT_DATA), + .C_USE_ECC (C_USE_ECC), + .C_USE_RAMB16BWER_RST_BHV (C_USE_RAMB16BWER_RST_BHV), + .C_WEA_WIDTH (C_WEA_WIDTH), + .C_WEB_WIDTH (C_WEB_WIDTH), + .C_WRITE_DEPTH_A (C_WRITE_DEPTH_A), + .C_WRITE_DEPTH_B (C_WRITE_DEPTH_B), + .C_WRITE_MODE_A (C_WRITE_MODE_A), + .C_WRITE_MODE_B (C_WRITE_MODE_B), + .C_WRITE_WIDTH_A (C_WRITE_WIDTH_A), + .C_WRITE_WIDTH_B (C_WRITE_WIDTH_B), + .C_XDEVICEFAMILY (C_XDEVICEFAMILY) + ) blk_mem_gen_v2_5_dut ( + .DINA (DINA), + .DINB (DINB), + .ADDRA (ADDRA), + .ADDRB (ADDRB), + .ENA (ENA), + .ENB (ENB), + .REGCEA (REGCEA), + .REGCEB (REGCEB), + .WEA (WEA), + .WEB (WEB), + .SSRA (SSRA), + .SSRB (SSRB), + .CLKA (CLKA), + .CLKB (CLKB), + .DOUTA (DOUTA), + .DOUTB (DOUTB), + .DBITERR (DBITERR), + .SBITERR (SBITERR) +); + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/BLK_MEM_GEN_V2_6.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/BLK_MEM_GEN_V2_6.v new file mode 100644 index 0000000..534c493 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/BLK_MEM_GEN_V2_6.v @@ -0,0 +1,1179 @@ +/****************************************************************************** + * + * Block Memory Generator Core - Block Memory Behavioral Model + * + * Copyright(C) 2005 by Xilinx, Inc. All rights reserved. + * This text/file contains proprietary, confidential + * information of Xilinx, Inc., is distributed under + * license from Xilinx, Inc., and may be used, copied + * and/or disclosed only pursuant to the terms of a valid + * license agreement with Xilinx, Inc. Xilinx hereby + * grants you a license to use this text/file solely for + * design, simulation, implementation and creation of + * design files limited to Xilinx devices or technologies. + * Use with non-Xilinx devices or technologies is expressly + * prohibited and immediately terminates your license unless + * covered by a separate agreement. + * + * Xilinx is providing this design, code, or information + * "as-is" solely for use in developing programs and + * solutions for Xilinx devices, with no obligation on the + * part of Xilinx to provide support. By providing this design, + * code, or information as one possible implementation of + * this feature, application or standard, Xilinx is making no + * representation that this implementation is free from any + * claims of infringement. You are responsible for obtaining + * any rights you may require for your implementation. + * Xilinx expressly disclaims any warranty whatsoever with + * respect to the adequacy of the implementation, including + * but not limited to any warranties or representations that this + * implementation is free from claims of infringement, implied + * warranties of merchantability or fitness for a particular + * purpose. + * + * Xilinx products are not intended for use in life support + * appliances, devices, or systems. Use in such applications is + * expressly prohibited. + * + * Any modifications that are made to the Source Code are + * done at the user's sole risk and will be unsupported. + * The Xilinx Support Hotline does not have access to source + * code and therefore cannot answer specific questions related + * to source HDL. The Xilinx Hotline support of original source + * code IP shall only address issues and questions related + * to the standard Netlist version of the core (and thus + * indirectly, the original core source). + * + * This copyright and support notice must be retained as part + * of this text at all times. (c) Copyright 1995-2005 Xilinx, Inc. + * All rights reserved. + * + ***************************************************************************** + * + * Filename: BLK_MEM_GEN_V2_6.v + * + * Description: + * This file is the Verilog behvarial model for the + * Block Memory Generator Core. + * + ***************************************************************************** + * Author: Xilinx + * + * History: January 11, 2006 Initial revision + *****************************************************************************/ +`timescale 1ps/1ps + +module BLK_MEM_GEN_V2_6_output_stage + #(parameter C_DATA_WIDTH = 32, + parameter C_HAS_SSR = 0, + parameter C_SINIT_VAL = "0", + parameter C_HAS_REGCE = 0, + parameter C_HAS_EN = 0, + parameter C_USE_ECC = 0, + parameter C_FAMILY = "virtex5", + parameter C_XDEVICEFAMILY = "virtex5", + parameter C_USE_RAMB16BWER_RST_BHV = 0, + parameter C_HAS_MEM_OUTPUT_REGS = 0, + parameter num_stages = 1, + parameter flop_delay = 100) + (input CLK, + input SSR, + input REGCE, + input EN, + input [C_DATA_WIDTH-1:0] DIN, + output reg [C_DATA_WIDTH-1:0] DOUT); + + localparam reg_stages = (num_stages == 0) ? 0 : num_stages-1; + reg [C_DATA_WIDTH*reg_stages-1:0] out_regs; + reg [C_DATA_WIDTH*8-1:0] sinit_str = C_SINIT_VAL; + reg [C_DATA_WIDTH-1:0] sinit_val; + + // Wire off optional inputs based on parameters + //--------------------------------------------- + wire en_i; + wire regce_i; + wire ssr_i; + //Internal enable for output registers is tied to user EN or '1' depending + // on parameters + // For V4 ECC, EN is always 1 + // Virtex-4 ECC Not Yet Supported + assign en_i = (C_HAS_EN==0 || EN) + || (C_USE_ECC && C_FAMILY=="virtex4"); + //Internal enable is tied to user REGCE, EN or '1' depending on parameters + // For V4 ECC, REGCE is always 1 + // Virtex-4 ECC Not Yet Supported + assign regce_i = ((C_HAS_REGCE==1) && REGCE) || + ((C_HAS_REGCE==0) && (C_HAS_EN==0 || EN)) + || (C_USE_ECC && C_FAMILY=="virtex4"); + //Internal SRR is tied to user SSR or '0' depending on parameters + assign ssr_i = (C_HAS_SSR==1) && SSR; + + initial begin + // Power on: load up the output registers and latches + if (!($sscanf(sinit_str, "%h", sinit_val))) begin + sinit_val = 0; + end + DOUT = sinit_val; + // This will be one wider than need, but 0 is an error + out_regs = {(reg_stages+1){sinit_val}}; + end + + //*********************************************** + // num_stages = 0 (No output registers. RAM only) + //*********************************************** + generate if (num_stages == 0) begin : zero_stages + always @* begin + DOUT = DIN; + end + end + endgenerate + + //*********************************************** + // num_stages = 1 + // (Mem Output Reg only or Mux Output Reg only) + //*********************************************** + // Because c_use_ramb16bwer_rst_bhv is common for both Port A and Port B, + // the corresponding C_HAS_MEM_OUTPUT_REGS_* has to be checked to determine + // the DOUT reset behavior for each port. + + // Possible valid combinations: (assuming C_HAS_MUX_OUTPUT_REGS_[A/B]=0) + // Note: C_HAS_MUX_OUTPUT_REGS_*=0 when (C_HAS_MEM_OUTPUT_REGS_*=1 AND + // C_USE_RAMB16BWER_RST_BHV=1 AND + // C_HAS_SSR*=1) + + // +-----------------------------+------------+------------------------+ + // |C_USE_RAMB16BWER|C_HAS_MEM |C_HAS_MEM | Reset Behavior | + // | _RST_BHV |_OUTPUT_REGS|_OUTPUT_REGS| | + // | | _A | _B | | + // +----------------+------------+------------+------------------------+ + // | 0 | x | x | A/B=Normal | + // +----------------+------------+------------+------------------------+ + // | 1 | 1 | 0 |A=Special if HAS_SSRA=1 | + // | | | |B=Normal | + // +----------------+------------+------------+------------------------+ + // | 1 | 0 | 1 |A=Normal | + // | | | |B=Special if HAS_SSRB=1 | + // +----------------+------------+------------+------------------------+ + // | 1 | 1 | 1 |A=Special if HAS_SSRA=1 | + // | | | |B=Special if HAS_SSRB=1 | + // +----------------+------------+------------+------------------------+ + // + // x = anything + // Normal = Normal V5 like behavior + // Special = Special RAMB16BWER primitive behavior for Spartan-3adsp + + generate if (num_stages == 1 && + (C_USE_RAMB16BWER_RST_BHV==0 || + C_HAS_MEM_OUTPUT_REGS==0 || + C_HAS_SSR==0)) begin : one_stages_norm + + always @(posedge CLK) begin + if (regce_i && ssr_i) begin + DOUT <= #flop_delay sinit_val; + end else if (regce_i) begin + DOUT <= #flop_delay DIN; + end + end + end + endgenerate + + generate if (num_stages == 1 && + C_USE_RAMB16BWER_RST_BHV==1 && + C_HAS_MEM_OUTPUT_REGS==1 && + C_HAS_SSR==1 ) begin : one_stages_s3adsp + + always @(posedge CLK) begin + if (en_i && ssr_i) begin + DOUT <= #flop_delay sinit_val; + end else if (regce_i) begin + DOUT <= #flop_delay DIN; + end + end + end + endgenerate + + //********************************************************* + // num_stages > 1 + // Mem Output Reg + Mux Output Reg + // or + // Mem Output Reg + Mux Pipeline Stages (>0) + Mux Output Reg + // or + // Mux Pipeline Stages (>0) + Mux Output Reg + //********************************************************* + generate if (num_stages > 1) begin : multi_stage + always @(posedge CLK) begin + if (regce_i && ssr_i) begin + DOUT <= #flop_delay sinit_val; + end else if (regce_i) begin + DOUT <= #flop_delay + out_regs[C_DATA_WIDTH*(num_stages-2)+:C_DATA_WIDTH]; + end + + if (en_i) begin + out_regs <= #flop_delay + (out_regs << C_DATA_WIDTH) | DIN; + end + end + end + endgenerate +endmodule + +module BLK_MEM_GEN_V2_6 + #(parameter C_ADDRA_WIDTH = 5, + parameter C_ADDRB_WIDTH = 5, + parameter C_ALGORITHM = 2, + parameter C_BYTE_SIZE = 8, + parameter C_COMMON_CLK = 1, + parameter C_CORENAME = "blk_mem_gen_v2_6", + parameter C_DEFAULT_DATA = "0", + parameter C_DISABLE_WARN_BHV_COLL = 0, + parameter C_DISABLE_WARN_BHV_RANGE = 0, + parameter C_FAMILY = "virtex4", + parameter C_HAS_ENA = 1, + parameter C_HAS_ENB = 1, + parameter C_HAS_MEM_OUTPUT_REGS_A = 0, + parameter C_HAS_MEM_OUTPUT_REGS_B = 0, + parameter C_HAS_MUX_OUTPUT_REGS_A = 0, + parameter C_HAS_MUX_OUTPUT_REGS_B = 0, + parameter C_MUX_PIPELINE_STAGES = 0, + parameter C_HAS_REGCEA = 0, + parameter C_HAS_REGCEB = 0, + parameter C_HAS_SSRA = 0, + parameter C_HAS_SSRB = 0, + parameter C_INIT_FILE_NAME = "", + parameter C_LOAD_INIT_FILE = 0, + parameter C_MEM_TYPE = 2, + parameter C_PRIM_TYPE = 3, + parameter C_READ_DEPTH_A = 64, + parameter C_READ_DEPTH_B = 64, + parameter C_READ_WIDTH_A = 32, + parameter C_READ_WIDTH_B = 32, + parameter C_SIM_COLLISION_CHECK = "NONE", + parameter C_SINITA_VAL = "0", + parameter C_SINITB_VAL = "0", + parameter C_USE_BYTE_WEA = 0, + parameter C_USE_BYTE_WEB = 0, + parameter C_USE_DEFAULT_DATA = 0, + parameter C_USE_ECC = 0, + parameter C_USE_RAMB16BWER_RST_BHV = 0, + parameter C_WEA_WIDTH = 1, + parameter C_WEB_WIDTH = 1, + parameter C_WRITE_DEPTH_A = 64, + parameter C_WRITE_DEPTH_B = 64, + parameter C_WRITE_MODE_A = "WRITE_FIRST", + parameter C_WRITE_MODE_B = "WRITE_FIRST", + parameter C_WRITE_WIDTH_A = 32, + parameter C_WRITE_WIDTH_B = 32, + parameter C_XDEVICEFAMILY = "virtex4" +) + (input CLKA, + input [C_WRITE_WIDTH_A-1:0] DINA, + input [C_ADDRA_WIDTH-1:0] ADDRA, + input ENA, + input REGCEA, + input [C_WEA_WIDTH-1:0] WEA, + input SSRA, + output [C_READ_WIDTH_A-1:0] DOUTA, + input CLKB, + input [C_WRITE_WIDTH_B-1:0] DINB, + input [C_ADDRB_WIDTH-1:0] ADDRB, + input ENB, + input REGCEB, + input [C_WEB_WIDTH-1:0] WEB, + input SSRB, + output [C_READ_WIDTH_B-1:0] DOUTB, + output DBITERR, + output SBITERR + ); + + // constants for the core behavior + //================================ + // file handles for logging + //------------------------------------------------------ + localparam addrfile = 32'h8000_0001; // stdout for addr out of range + localparam collfile = 32'h8000_0001; // stdout for coll detection + localparam errfile = 32'h8000_0001; // stdout for file I/O errors + + // other constants + //------------------------------------------------------ + localparam coll_delay = 2000; // 2 ns + + // locally derived parameters to determine memory shape + //----------------------------------------------------- + localparam min_width_a = (C_WRITE_WIDTH_A < C_READ_WIDTH_A) ? + C_WRITE_WIDTH_A : C_READ_WIDTH_A; + localparam min_width_b = (C_WRITE_WIDTH_B < C_READ_WIDTH_B) ? + C_WRITE_WIDTH_B : C_READ_WIDTH_B; + localparam min_width = (min_width_a < min_width_b) ? + min_width_a : min_width_b; + + localparam max_width_a = (C_WRITE_WIDTH_A > C_READ_WIDTH_A) ? + C_WRITE_WIDTH_A : C_READ_WIDTH_A; + localparam max_width_b = (C_WRITE_WIDTH_B > C_READ_WIDTH_B) ? + C_WRITE_WIDTH_B : C_READ_WIDTH_B; + localparam max_width = (max_width_a > max_width_b) ? + max_width_a : max_width_b; + + localparam max_depth_a = (C_WRITE_DEPTH_A > C_READ_DEPTH_A) ? + C_WRITE_DEPTH_A : C_READ_DEPTH_A; + localparam max_depth_b = (C_WRITE_DEPTH_B > C_READ_DEPTH_B) ? + C_WRITE_DEPTH_B : C_READ_DEPTH_B; + localparam max_depth = (max_depth_a > max_depth_b) ? + max_depth_a : max_depth_b; + + + // locally derived parameters to assist memory access + //---------------------------------------------------- + localparam write_width_ratio_a = C_WRITE_WIDTH_A/min_width; + localparam read_width_ratio_a = C_READ_WIDTH_A/min_width; + localparam write_width_ratio_b = C_WRITE_WIDTH_B/min_width; + localparam read_width_ratio_b = C_READ_WIDTH_B/min_width; + + // To modify the LSBs of the 'wider' data to the actual + // address value + //---------------------------------------------------- + localparam write_addr_a_div = C_WRITE_WIDTH_A/min_width_a; + localparam read_addr_a_div = C_READ_WIDTH_A/min_width_a; + localparam write_addr_b_div = C_WRITE_WIDTH_B/min_width_b; + localparam read_addr_b_div = C_READ_WIDTH_B/min_width_b; + + // If byte writes aren't being used, make sure byte_size is not + // wider than the memory elements to avoid compilation warnings + localparam byte_size = (C_BYTE_SIZE < min_width) ? C_BYTE_SIZE : min_width; + + // the memory + reg [min_width-1:0] memory [0:max_depth-1]; + // memory output 'latches' + reg [C_READ_WIDTH_A-1:0] memory_out_a; + reg [C_READ_WIDTH_B-1:0] memory_out_b; + // reset values + reg [C_READ_WIDTH_A-1:0] sinita_val; + reg [C_READ_WIDTH_B-1:0] sinitb_val; + + // collision detect + reg is_collision; + reg is_collision_a, is_collision_delay_a; + reg is_collision_b, is_collision_delay_b; + + // temporary variables for initialization + //--------------------------------------- + integer status; + reg [639:0] err_str; + integer initfile; + // data input buffer + reg [C_WRITE_WIDTH_A-1:0] mif_data; + // string values in hex + reg [C_READ_WIDTH_A*8-1:0] sinita_str = C_SINITA_VAL; + reg [C_READ_WIDTH_B*8-1:0] sinitb_str = C_SINITB_VAL; + reg [C_WRITE_WIDTH_A*8-1:0] default_data_str = C_DEFAULT_DATA; + // initialization filename + reg [1023*8-1:0] init_file_str = C_INIT_FILE_NAME; + + // internal configuration parameters + //--------------------------------------------- + localparam flop_delay = 100; // 100 ps + localparam single_port = (C_MEM_TYPE==0 || C_MEM_TYPE==3); + localparam is_rom = (C_MEM_TYPE==3 || C_MEM_TYPE==4); + localparam has_a_write = (!is_rom); + localparam has_b_write = (C_MEM_TYPE==2); + localparam has_a_read = (C_MEM_TYPE!=1); + localparam has_b_read = (!single_port); + localparam has_b_port = (has_b_read || has_b_write); + + //Calculate the pipeline register stages for Port A and Port B + localparam mux_pipeline_stages_a = (C_HAS_MUX_OUTPUT_REGS_A) ? C_MUX_PIPELINE_STAGES : 0; + localparam mux_pipeline_stages_b = (C_HAS_MUX_OUTPUT_REGS_B) ? C_MUX_PIPELINE_STAGES : 0; + + // Virtex-4 ECC Not Yet Supported + localparam num_output_stages_a = (C_FAMILY=="virtex4" && C_USE_ECC==1) ? + (C_HAS_MEM_OUTPUT_REGS_A + mux_pipeline_stages_a + C_HAS_MUX_OUTPUT_REGS_A + 1) : + (C_HAS_MEM_OUTPUT_REGS_A + mux_pipeline_stages_a + C_HAS_MUX_OUTPUT_REGS_A); + + localparam num_output_stages_b = (C_FAMILY=="virtex4" && C_USE_ECC==1) ? + (C_HAS_MEM_OUTPUT_REGS_B + mux_pipeline_stages_b + C_HAS_MUX_OUTPUT_REGS_B + 1) : + (C_HAS_MEM_OUTPUT_REGS_B + mux_pipeline_stages_b + C_HAS_MUX_OUTPUT_REGS_B); + wire ena_i; + wire enb_i; + wire reseta_i; + wire resetb_i; + wire [C_WEA_WIDTH-1:0] wea_i; + wire [C_WEB_WIDTH-1:0] web_i; + wire rea_i; + wire reb_i; + + // ECC SBITERR/DBITERR Outputs + // The ECC Behavior is not modeled by the behavioral models, therefore + // the SBITERR and DBITERR outputs are explicitly tied to 0. + assign SBITERR = 0; + assign DBITERR = 0; + + + // This effectively wires off optional inputs + assign ena_i = (C_HAS_ENA==0) || ENA; + assign enb_i = ((C_HAS_ENB==0) || ENB) && has_b_port; + assign wea_i = (has_a_write && ena_i) ? WEA : 'b0; + assign web_i = (has_b_write && enb_i) ? WEB : 'b0; + assign rea_i = (has_a_read) ? ena_i : 'b0; + assign reb_i = (has_b_read) ? enb_i : 'b0; + + // these signals reset the memory latches + // Because c_use_ramb16bwer_rst_bhv is common for both Port A and Port B, + // the corresponding C_HAS_MEM_OUTPUT_REG_* has to be checked as well to determine + // the reset behavior for each port. + + assign reseta_i = ((C_HAS_SSRA==1 && SSRA && ena_i && num_output_stages_a==0) || + (C_HAS_SSRA==1 && SSRA && ena_i && C_USE_RAMB16BWER_RST_BHV==1 && C_HAS_MEM_OUTPUT_REGS_A==1 && C_HAS_MUX_OUTPUT_REGS_A==0)); + assign resetb_i = ((C_HAS_SSRB==1 && SSRB && enb_i && num_output_stages_b==0) || + (C_HAS_SSRB==1 && SSRB && enb_i && C_USE_RAMB16BWER_RST_BHV==1 && C_HAS_MEM_OUTPUT_REGS_B==1 && C_HAS_MUX_OUTPUT_REGS_B==0)); + + // tasks to access the memory + //--------------------------- + task write_a + (input reg [C_ADDRA_WIDTH-1:0] addr, + input reg [C_WEA_WIDTH-1:0] byte_en, + input reg [C_WRITE_WIDTH_A-1:0] data); + reg [C_WRITE_WIDTH_A-1:0] current_contents; + reg [C_ADDRA_WIDTH-1:0] address; + integer i; + begin + // Shift the address by the ratio + address = (addr/write_addr_a_div); + if (address >= C_WRITE_DEPTH_A) begin + if (!C_DISABLE_WARN_BHV_RANGE) begin + $fdisplay(addrfile, + "%0s WARNING: Address %0h is outside range for A Write", + C_CORENAME, addr); + end + + // valid address + end else begin + + // Combine w/ byte writes + if (C_USE_BYTE_WEA) begin + + // Get the current memory contents + if (write_width_ratio_a == 1) begin + // Workaround for IUS 5.5 part-select issue + current_contents = memory[address]; + end else begin + for (i = 0; i < write_width_ratio_a; i = i + 1) begin + current_contents[min_width*i+:min_width] + = memory[address*write_width_ratio_a + i]; + end + end + + // Apply incoming bytes + if (C_WEA_WIDTH == 1) begin + // Workaround for IUS 5.5 part-select issue + if (byte_en[0]) begin + current_contents = data; + end + end else begin + for (i = 0; i < C_WEA_WIDTH; i = i + 1) begin + if (byte_en[i]) begin + current_contents[byte_size*i+:byte_size] + = data[byte_size*i+:byte_size]; + end + end + end + + // No byte-writes, overwrite the whole word + end else begin + current_contents = data; + end + + // Write data to memory + if (write_width_ratio_a == 1) begin + // Workaround for IUS 5.5 part-select issue + memory[address*write_width_ratio_a] = current_contents; + end else begin + for (i = 0; i < write_width_ratio_a; i = i + 1) begin + memory[address*write_width_ratio_a + i] + = current_contents[min_width*i+:min_width]; + end + end + + end + end + endtask + + task write_b + (input reg [C_ADDRB_WIDTH-1:0] addr, + input reg [C_WEB_WIDTH-1:0] byte_en, + input reg [C_WRITE_WIDTH_B-1:0] data); + reg [C_WRITE_WIDTH_B-1:0] current_contents; + reg [C_ADDRB_WIDTH-1:0] address; + integer i; + begin + // Shift the address by the ratio + address = (addr/write_addr_b_div); + if (address >= C_WRITE_DEPTH_B) begin + if (!C_DISABLE_WARN_BHV_RANGE) begin + $fdisplay(addrfile, + "%0s WARNING: Address %0h is outside range for B Write", + C_CORENAME, addr); + end + + // valid address + end else begin + + // Combine w/ byte writes + if (C_USE_BYTE_WEB) begin + + // Get the current memory contents + if (write_width_ratio_b == 1) begin + // Workaround for IUS 5.5 part-select issue + current_contents = memory[address]; + end else begin + for (i = 0; i < write_width_ratio_b; i = i + 1) begin + current_contents[min_width*i+:min_width] + = memory[address*write_width_ratio_b + i]; + end + end + + // Apply incoming bytes + if (C_WEB_WIDTH == 1) begin + // Workaround for IUS 5.5 part-select issue + if (byte_en[0]) begin + current_contents = data; + end + end else begin + for (i = 0; i < C_WEB_WIDTH; i = i + 1) begin + if (byte_en[i]) begin + current_contents[byte_size*i+:byte_size] + = data[byte_size*i+:byte_size]; + end + end + end + + // No byte-writes, overwrite the whole word + end else begin + current_contents = data; + end + + // Write data to memory + if (write_width_ratio_b == 1) begin + // Workaround for IUS 5.5 part-select issue + memory[address*write_width_ratio_b] = current_contents; + end else begin + for (i = 0; i < write_width_ratio_b; i = i + 1) begin + memory[address*write_width_ratio_b + i] + = current_contents[min_width*i+:min_width]; + end + end + end + end + endtask + + task read_a + (input reg [C_ADDRA_WIDTH-1:0] addr, + input reg reset); + reg [C_ADDRA_WIDTH-1:0] address; + integer i; + begin + + if (reset) begin + memory_out_a <= #flop_delay sinita_val; + end else begin + // Shift the address by the ratio + address = (addr/read_addr_a_div); + if (address >= C_READ_DEPTH_A) begin + if (!C_DISABLE_WARN_BHV_RANGE) begin + $fdisplay(addrfile, + "%0s WARNING: Address %0h is outside range for A Read", + C_CORENAME, addr); + end + + // valid address + end else begin + + if (read_width_ratio_a==1) begin + memory_out_a <= #flop_delay memory[address*read_width_ratio_a]; + end else begin + // Increment through the 'partial' words in the memory + for (i = 0; i < read_width_ratio_a; i = i + 1) begin + memory_out_a[min_width*i+:min_width] + <= #flop_delay memory[address*read_width_ratio_a + i]; + end + end + + end + end + end + endtask + + task read_b + (input reg [C_ADDRB_WIDTH-1:0] addr, + input reg reset); + reg [C_ADDRB_WIDTH-1:0] address; + integer i; + begin + + if (reset) begin + memory_out_b <= #flop_delay sinitb_val; + end else begin + // Shift the address + address = (addr/read_addr_b_div); + if (address >= C_READ_DEPTH_B) begin + if (!C_DISABLE_WARN_BHV_RANGE) begin + $fdisplay(addrfile, + "%0s WARNING: Address %0h is outside range for B Read", + C_CORENAME, addr); + end + + // valid address + end else begin + + if (read_width_ratio_b==1) begin + memory_out_b <= #flop_delay memory[address*read_width_ratio_b]; + end else begin + // Increment through the 'partial' words in the memory + for (i = 0; i < read_width_ratio_b; i = i + 1) begin + memory_out_b[min_width*i+:min_width] + <= #flop_delay memory[address*read_width_ratio_b + i]; + end + end + + end + end + end + endtask + + task init_memory; + integer i, addr_step; + integer status; + reg [C_WRITE_WIDTH_A-1:0] default_data; + begin + default_data = 0; + + //Display output message indicating that the behavioral model is being initialized + if (C_USE_DEFAULT_DATA || C_LOAD_INIT_FILE) $display(" Block Memory Generator CORE Generator module loading initial data..."); + + // Convert the default to hex + if (C_USE_DEFAULT_DATA) begin + if (default_data_str == "") begin + $fdisplay(errfile, "%0s ERROR: C_DEFAULT_DATA is empty!", C_CORENAME); + $finish; + end else begin + status = $sscanf(default_data_str, "%h", default_data); + if (status == 0) begin + $fdisplay(errfile, {"%0s ERROR: Unsuccessful hexadecimal read", + "from C_DEFAULT_DATA: %0s"}, + C_CORENAME, C_DEFAULT_DATA); + $finish; + end + end + end + + // Step by write_addr_a_div through the memory via the + // Port A write interface to hit every location once + addr_step = write_addr_a_div; + + // 'write' to every location with default (or 0) + for (i = 0; i < C_WRITE_DEPTH_A*addr_step; i = i + addr_step) begin + write_a(i, {C_WEA_WIDTH{1'b1}}, default_data); + end + + // Get specialized data from the MIF file + if (C_LOAD_INIT_FILE) begin + if (init_file_str == "") begin + $fdisplay(errfile, "%0s ERROR: C_INIT_FILE_NAME is empty!", + C_CORENAME); + $finish; + end else begin + initfile = $fopen(init_file_str, "r"); + if (initfile == 0) begin + $fdisplay(errfile, {"%0s, ERROR: Problem opening", + "C_INIT_FILE_NAME: %0s!"}, + C_CORENAME, init_file_str); + $finish; + end else begin + // loop through the mif file, loading in the data + for (i = 0; i < C_WRITE_DEPTH_A*addr_step; i = i + addr_step) begin + status = $fscanf(initfile, "%b", mif_data); + if (status > 0) begin + write_a(i, {C_WEA_WIDTH{1'b1}}, mif_data); + end + end + $fclose(initfile); + end //initfile + end //init_file_str + end //C_LOAD_INIT_FILE + + //Display output message indicating that the behavioral model is done initializing + if (C_USE_DEFAULT_DATA || C_LOAD_INIT_FILE) $display(" Block Memory Generator data initialization complete."); + + + end + endtask + + function integer log2roundup (input integer data_value); + integer width; + integer cnt; + begin + width = 0; + + if (data_value > 1) begin + for(cnt=1 ; cnt < data_value ; cnt = cnt * 2) begin + width = width + 1; + end //loop + end //if + + log2roundup = width; + + end //log2roundup + endfunction + + + + function integer collision_check (input reg [C_ADDRA_WIDTH-1:0] addr_a, + input integer iswrite_a, + input reg [C_ADDRB_WIDTH-1:0] addr_b, + input integer iswrite_b); + reg [C_ADDRA_WIDTH-1:0] base_addr_a; + reg [C_ADDRB_WIDTH-1:0] base_addr_b; + integer ratio_a, ratio_b; + integer lo_addr_wider, hi_addr_wider; + integer lo_addr_narrow, hi_addr_narrow; + reg c_aw_bw, c_aw_br, c_ar_bw; + integer write_addr_a_width, read_addr_a_width; + integer write_addr_b_width, read_addr_b_width; + + begin + + c_aw_bw = 0; + c_aw_br = 0; + c_ar_bw = 0; + + // Determine the effective address widths for each of the 4 ports + write_addr_a_width = C_ADDRA_WIDTH-log2roundup(write_addr_a_div); + read_addr_a_width = C_ADDRA_WIDTH-log2roundup(read_addr_a_div); + write_addr_b_width = C_ADDRB_WIDTH-log2roundup(write_addr_b_div); + read_addr_b_width = C_ADDRB_WIDTH-log2roundup(read_addr_b_div); + + + //Look for a write-write collision. In order for a write-write + //collision to exist, both ports must have a write transaction. + if (iswrite_a && iswrite_b) begin + if (write_addr_a_width > write_addr_b_width) begin + //write_addr_b_width is smaller, so scale both addresses to that + // width for comparing write_addr_a and write_addr_b + //addr_a starts as C_ADDRA_WIDTH, + // scale it down to write_addr_b_width + //addr_b starts as C_ADDRB_WIDTH, + // scale it down to write_addr_b_width + //Once both are scaled to write_addr_b_width, compare. + if (((addr_a)/2**(C_ADDRA_WIDTH-write_addr_b_width)) == ((addr_b)/2**(C_ADDRB_WIDTH-write_addr_b_width))) begin + c_aw_bw = 1; + end else begin + c_aw_bw = 0; + end + end else begin + //write_addr_a_width is smaller, so scale both addresses to that + // width for comparing write_addr_a and write_addr_b + //addr_a starts as C_ADDRA_WIDTH, + // scale it down to write_addr_a_width + //addr_b starts as C_ADDRB_WIDTH, + // scale it down to write_addr_a_width + //Once both are scaled to write_addr_a_width, compare. + if (((addr_b)/2**(C_ADDRB_WIDTH-write_addr_a_width)) == ((addr_a)/2**(C_ADDRA_WIDTH-write_addr_a_width))) begin + c_aw_bw = 1; + end else begin + c_aw_bw = 0; + end + end //width + end //iswrite_a and iswrite_b + + //If the B port is reading (which means it is enabled - so could be + // a TX_WRITE or TX_READ), then check for a write-read collision). + //This could happen whether or not a write-write collision exists due + // to asymmetric write/read ports. + if (iswrite_a) begin + if (write_addr_a_width > read_addr_b_width) begin + //read_addr_b_width is smaller, so scale both addresses to that + // width for comparing write_addr_a and read_addr_b + //addr_a starts as C_ADDRA_WIDTH, + // scale it down to read_addr_b_width + //addr_b starts as C_ADDRB_WIDTH, + // scale it down to read_addr_b_width + //Once both are scaled to read_addr_b_width, compare. + if (((addr_a)/2**(C_ADDRA_WIDTH-read_addr_b_width)) == ((addr_b)/2**(C_ADDRB_WIDTH-read_addr_b_width))) begin + c_aw_br = 1; + end else begin + c_aw_br = 0; + end + end else begin + //write_addr_a_width is smaller, so scale both addresses to that + // width for comparing write_addr_a and read_addr_b + //addr_a starts as C_ADDRA_WIDTH, + // scale it down to write_addr_a_width + //addr_b starts as C_ADDRB_WIDTH, + // scale it down to write_addr_a_width + //Once both are scaled to write_addr_a_width, compare. + if (((addr_b)/2**(C_ADDRB_WIDTH-write_addr_a_width)) == ((addr_a)/2**(C_ADDRA_WIDTH-write_addr_a_width))) begin + c_aw_br = 1; + end else begin + c_aw_br = 0; + end + end //width + end //iswrite_a + + //If the A port is reading (which means it is enabled - so could be + // a TX_WRITE or TX_READ), then check for a write-read collision). + //This could happen whether or not a write-write collision exists due + // to asymmetric write/read ports. + if (iswrite_b) begin + if (read_addr_a_width > write_addr_b_width) begin + //write_addr_b_width is smaller, so scale both addresses to that + // width for comparing read_addr_a and write_addr_b + //addr_a starts as C_ADDRA_WIDTH, + // scale it down to write_addr_b_width + //addr_b starts as C_ADDRB_WIDTH, + // scale it down to write_addr_b_width + //Once both are scaled to write_addr_b_width, compare. + if (((addr_a)/2**(C_ADDRA_WIDTH-write_addr_b_width)) == ((addr_b)/2**(C_ADDRB_WIDTH-write_addr_b_width))) begin + c_ar_bw = 1; + end else begin + c_ar_bw = 0; + end + end else begin + //read_addr_a_width is smaller, so scale both addresses to that + // width for comparing read_addr_a and write_addr_b + //addr_a starts as C_ADDRA_WIDTH, + // scale it down to read_addr_a_width + //addr_b starts as C_ADDRB_WIDTH, + // scale it down to read_addr_a_width + //Once both are scaled to read_addr_a_width, compare. + if (((addr_b)/2**(C_ADDRB_WIDTH-read_addr_a_width)) == ((addr_a)/2**(C_ADDRA_WIDTH-read_addr_a_width))) begin + c_ar_bw = 1; + end else begin + c_ar_bw = 0; + end + end //width + end //iswrite_b + + + // Convert the input addresses in base and offsets for our + // memory array. Ignore LSBs for asymmetric ports + if (iswrite_a) begin + base_addr_a = (addr_a/write_addr_a_div) * write_addr_a_div; + ratio_a = write_width_ratio_a; + end else begin + base_addr_a = (addr_a/read_addr_a_div) * read_addr_a_div; + ratio_a = read_width_ratio_a; + end + if (iswrite_b) begin + base_addr_b = (addr_b/write_addr_b_div) * write_addr_b_div; + ratio_b = write_width_ratio_b; + end else begin + base_addr_b = (addr_b/read_addr_b_div) * read_addr_b_div; + ratio_b = read_width_ratio_b; + end + + // Determine the wider port, and normalized ranges + if (ratio_a >= ratio_b) begin + lo_addr_wider = base_addr_a * ratio_a; + hi_addr_wider = lo_addr_wider + ratio_a; + lo_addr_narrow = base_addr_b * ratio_b; + hi_addr_narrow = lo_addr_narrow + ratio_b; + end else begin + lo_addr_wider = base_addr_b * ratio_b; + hi_addr_wider = lo_addr_wider + ratio_b; + lo_addr_narrow = base_addr_a * ratio_a; + hi_addr_narrow = lo_addr_narrow + ratio_a; + end + + // compare the two ranges of address (narrow inside wider) + //if ((lo_addr_narrow >= lo_addr_wider) && + // (hi_addr_narrow <= hi_addr_wider)) begin + // collision_check = 1; + //end else begin + // collision_check = 0; + //end + + collision_check = c_aw_bw | c_aw_br | c_ar_bw; + + end + endfunction + + // power on values + //----------------------------- + initial begin + // Load up the memory + init_memory; + // Load up the output registers and latches + if ($sscanf(sinita_str, "%h", sinita_val)) begin + memory_out_a = sinita_val; + end else begin + memory_out_a = 0; + end + if ($sscanf(sinitb_str, "%h", sinitb_val)) begin + memory_out_b = sinitb_val; + end else begin + memory_out_b = 0; + end + + $display("Block Memory Generator CORE Generator module %m is using a behavioral model for simulation which will not precisely model memory collision behavior."); + + end + + //------------------------------------------------------------------------- + // These are the main blocks which schedule read and write operations + //------------------------------------------------------------------------- + + generate if (C_COMMON_CLK) begin : common_clk_scheduling + // Synchronous clocks: schedule port operations with respect to + // both write operating modes + always @(posedge CLKA) begin + case ({C_WRITE_MODE_A, C_WRITE_MODE_B}) + {"WRITE_FIRST","WRITE_FIRST"}: begin + if (wea_i) write_a(ADDRA, wea_i, DINA); + if (web_i) write_b(ADDRB, web_i, DINB); + if (rea_i) read_a(ADDRA, reseta_i); + if (reb_i) read_b(ADDRB, resetb_i); + end + {"READ_FIRST", "WRITE_FIRST"}: begin + if (web_i) write_b(ADDRB, web_i, DINB); + if (reb_i) read_b(ADDRB, resetb_i); + if (rea_i) read_a(ADDRA, reseta_i); + if (wea_i) write_a(ADDRA, wea_i, DINA); + end + {"WRITE_FIRST","READ_FIRST"}: begin + if (wea_i) write_a(ADDRA, wea_i, DINA); + if (rea_i) read_a(ADDRA, reseta_i); + if (reb_i) read_b(ADDRB, resetb_i); + if (web_i) write_b(ADDRB, web_i, DINB); + end + {"READ_FIRST", "READ_FIRST"}: begin + if (rea_i) read_a(ADDRA, reseta_i); + if (reb_i) read_b(ADDRB, resetb_i); + if (wea_i) write_a(ADDRA, wea_i, DINA); + if (web_i) write_b(ADDRB, web_i, DINB); + end + {"WRITE_FIRST","NO_CHANGE"}: begin + if (wea_i) write_a(ADDRA, wea_i, DINA); + if (rea_i) read_a(ADDRA, reseta_i); + if ((reb_i && !web_i) || resetb_i) read_b(ADDRB, resetb_i); + if (web_i) write_b(ADDRB, web_i, DINB); + end + {"READ_FIRST", "NO_CHANGE"}: begin + if (rea_i) read_a(ADDRA, reseta_i); + if ((reb_i && !web_i) || resetb_i) read_b(ADDRB, resetb_i); + if (wea_i) write_a(ADDRA, wea_i, DINA); + if (web_i) write_b(ADDRB, web_i, DINB); + end + {"NO_CHANGE", "WRITE_FIRST"}: begin + if (wea_i) write_a(ADDRA, wea_i, DINA); + if (web_i) write_b(ADDRB, web_i, DINB); + if ((rea_i && !wea_i) || reseta_i) read_a(ADDRA, reseta_i); + if (reb_i) read_b(ADDRB, resetb_i); + end + {"NO_CHANGE", "READ_FIRST"}: begin + if (reb_i) read_b(ADDRB, resetb_i); + if ((rea_i && !wea_i) || reseta_i) read_a(ADDRA, reseta_i); + if (wea_i) write_a(ADDRA, wea_i, DINA); + if (web_i) write_b(ADDRB, web_i, DINB); + end + {"NO_CHANGE", "NO_CHANGE"}: begin + if (wea_i) write_a(ADDRA, wea_i, DINA); + if (web_i) write_b(ADDRB, web_i, DINB); + if ((rea_i && !wea_i) || reseta_i) read_a(ADDRA, reseta_i); + if ((reb_i && !web_i) || resetb_i) read_b(ADDRB, resetb_i); + end + default: begin + if (wea_i) write_a(ADDRA, wea_i, DINA); + if (web_i) write_b(ADDRB, web_i, DINB); + if (rea_i) read_a(ADDRA, reseta_i); + if (reb_i) read_b(ADDRB, resetb_i); + end + endcase + end + + end else begin : asynch_clk_scheduling + // Asynchronous clocks: port operation is independent + always @(posedge CLKA) begin + case (C_WRITE_MODE_A) + "WRITE_FIRST": begin + if (wea_i) write_a(ADDRA, wea_i, DINA); + if (rea_i) read_a(ADDRA, reseta_i); + end + "READ_FIRST": begin + if (rea_i) read_a(ADDRA, reseta_i); + if (wea_i) write_a(ADDRA, wea_i, DINA); + end + "NO_CHANGE": begin + if (wea_i) write_a(ADDRA, wea_i, DINA); + if ((rea_i && !wea_i) || reseta_i) read_a(ADDRA, reseta_i); + end + endcase + end + + always @(posedge CLKB) begin + case (C_WRITE_MODE_B) + "WRITE_FIRST": begin + if (web_i) write_b(ADDRB, web_i, DINB); + if (reb_i) read_b(ADDRB, resetb_i); + end + "READ_FIRST": begin + if (reb_i) read_b(ADDRB, resetb_i); + if (web_i) write_b(ADDRB, web_i, DINB); + end + "NO_CHANGE": begin + if (web_i) write_b(ADDRB, web_i, DINB); + if ((reb_i && !web_i) || resetb_i) read_b(ADDRB, resetb_i); + end + endcase + end + end + endgenerate + + // Variable depth output stage + BLK_MEM_GEN_V2_6_output_stage + #(.C_DATA_WIDTH (C_READ_WIDTH_A), + .C_HAS_SSR (C_HAS_SSRA), + .C_SINIT_VAL (C_SINITA_VAL), + .C_HAS_REGCE (C_HAS_REGCEA), + .C_HAS_EN (C_HAS_ENA), + .C_USE_ECC (C_USE_ECC), + .C_FAMILY (C_FAMILY), + .C_XDEVICEFAMILY (C_XDEVICEFAMILY), + .C_USE_RAMB16BWER_RST_BHV (C_USE_RAMB16BWER_RST_BHV), + .C_HAS_MEM_OUTPUT_REGS (C_HAS_MEM_OUTPUT_REGS_A), + .num_stages (num_output_stages_a), + .flop_delay (flop_delay)) + reg_a + (.CLK (CLKA), + .SSR (SSRA), + .REGCE (REGCEA), + .EN (ENA), + .DIN (memory_out_a), + .DOUT (DOUTA)); + + BLK_MEM_GEN_V2_6_output_stage + #(.C_DATA_WIDTH (C_READ_WIDTH_B), + .C_HAS_SSR (C_HAS_SSRB), + .C_SINIT_VAL (C_SINITB_VAL), + .C_HAS_REGCE (C_HAS_REGCEB), + .C_HAS_EN (C_HAS_ENB), + .C_USE_ECC (C_USE_ECC), + .C_FAMILY (C_FAMILY), + .C_XDEVICEFAMILY (C_XDEVICEFAMILY), + .C_USE_RAMB16BWER_RST_BHV (C_USE_RAMB16BWER_RST_BHV), + .C_HAS_MEM_OUTPUT_REGS (C_HAS_MEM_OUTPUT_REGS_B), + .num_stages (num_output_stages_b), + .flop_delay (flop_delay)) + reg_b + (.CLK (CLKB), + .SSR (SSRB), + .REGCE (REGCEB), + .EN (ENB), + .DIN (memory_out_b), + .DOUT (DOUTB)); + + // Synchronous collision checks + generate if (!C_DISABLE_WARN_BHV_COLL && C_COMMON_CLK) begin : sync_coll + always @(posedge CLKA) begin + // Possible collision if both are enabled and the addresses match + if (ena_i && enb_i) begin + is_collision = collision_check(ADDRA, wea_i, ADDRB, web_i); + end else begin + is_collision = 0; + end + + // If the write port is in READ_FIRST mode, there is no collision + if (C_WRITE_MODE_A=="READ_FIRST" && wea_i && !web_i) begin + is_collision = 0; + end + if (C_WRITE_MODE_B=="READ_FIRST" && web_i && !wea_i) begin + is_collision = 0; + end + + // Only flag if one of the accesses is a write + if (is_collision && (wea_i || web_i)) begin + $fwrite(collfile, "%0s collision detected at time: %0d, ", + C_CORENAME, $time); + $fwrite(collfile, "A %0s address: %0h, B %0s address: %0h\n", + wea_i ? "write" : "read", ADDRA, + web_i ? "write" : "read", ADDRB); + end + end + + // Asynchronous collision checks + end else if (!C_DISABLE_WARN_BHV_COLL && !C_COMMON_CLK) begin : async_coll + + // Delay A and B addresses in order to mimic setup/hold times + wire [C_ADDRA_WIDTH-1:0] #coll_delay addra_delay = ADDRA; + wire [0:0] #coll_delay wea_delay = wea_i; + wire #coll_delay ena_delay = ena_i; + wire [C_ADDRB_WIDTH-1:0] #coll_delay addrb_delay = ADDRB; + wire [0:0] #coll_delay web_delay = web_i; + wire #coll_delay enb_delay = enb_i; + + // Do the checks w/rt A + always @(posedge CLKA) begin + // Possible collision if both are enabled and the addresses match + if (ena_i && enb_i) begin + is_collision_a = collision_check(ADDRA, wea_i, ADDRB, web_i); + end else begin + is_collision_a = 0; + end + if (ena_i && enb_delay) begin + is_collision_delay_a = collision_check(ADDRA, wea_i, + addrb_delay, web_delay); + end else begin + is_collision_delay_a = 0; + end + + + // Only flag if B access is a write + if (is_collision_a && web_i) begin + $fwrite(collfile, "%0s collision detected at time: %0d, ", + C_CORENAME, $time); + $fwrite(collfile, "A %0s address: %0h, B write address: %0h\n", + wea_i ? "write" : "read", ADDRA, ADDRB); + + end else if (is_collision_delay_a && web_delay) begin + $fwrite(collfile, "%0s collision detected at time: %0d, ", + C_CORENAME, $time); + $fwrite(collfile, "A %0s address: %0h, B write address: %0h\n", + wea_i ? "write" : "read", ADDRA, addrb_delay); + end + + end + + // Do the checks w/rt B + always @(posedge CLKB) begin + + // Possible collision if both are enabled and the addresses match + if (ena_i && enb_i) begin + is_collision_b = collision_check(ADDRA, wea_i, ADDRB, web_i); + end else begin + is_collision_b = 0; + end + if (ena_delay && enb_i) begin + is_collision_delay_b = collision_check(addra_delay, wea_delay, + ADDRB, web_i); + end else begin + is_collision_delay_b = 0; + end + + + // Only flag if A access is a write + if (is_collision_b && wea_i) begin + $fwrite(collfile, "%0s collision detected at time: %0d, ", + C_CORENAME, $time); + $fwrite(collfile, "A write address: %0h, B %s address: %0h\n", + ADDRA, web_i ? "write" : "read", ADDRB); + + end else if (is_collision_delay_b && wea_delay) begin + $fwrite(collfile, "%0s collision detected at time: %0d, ", + C_CORENAME, $time); + $fwrite(collfile, "A write address: %0h, B %s address: %0h\n", + addra_delay, web_i ? "write" : "read", ADDRB); + end + + end + end + endgenerate + +endmodule diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/BLK_MEM_GEN_V2_6_xst.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/BLK_MEM_GEN_V2_6_xst.v new file mode 100644 index 0000000..8766c46 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/BLK_MEM_GEN_V2_6_xst.v @@ -0,0 +1,201 @@ +/****************************************************************************** + * + * Block Memory Generator Core - Block Memory Behavioral Model + * + * Copyright(C) 2005 by Xilinx, Inc. All rights reserved. + * This text/file contains proprietary, confidential + * information of Xilinx, Inc., is distributed under + * license from Xilinx, Inc., and may be used, copied + * and/or disclosed only pursuant to the terms of a valid + * license agreement with Xilinx, Inc. Xilinx hereby + * grants you a license to use this text/file solely for + * design, simulation, implementation and creation of + * design files limited to Xilinx devices or technologies. + * Use with non-Xilinx devices or technologies is expressly + * prohibited and immediately terminates your license unless + * covered by a separate agreement. + * + * Xilinx is providing this design, code, or information + * "as-is" solely for use in developing programs and + * solutions for Xilinx devices, with no obligation on the + * part of Xilinx to provide support. By providing this design, + * code, or information as one possible implementation of + * this feature, application or standard, Xilinx is making no + * representation that this implementation is free from any + * claims of infringement. You are responsible for obtaining + * any rights you may require for your implementation. + * Xilinx expressly disclaims any warranty whatsoever with + * respect to the adequacy of the implementation, including + * but not limited to any warranties or representations that this + * implementation is free from claims of infringement, implied + * warranties of merchantability or fitness for a particular + * purpose. + * + * Xilinx products are not intended for use in life support + * appliances, devices, or systems. Use in such applications is + * expressly prohibited. + * + * Any modifications that are made to the Source Code are + * done at the user's sole risk and will be unsupported. + * The Xilinx Support Hotline does not have access to source + * code and therefore cannot answer specific questions related + * to source HDL. The Xilinx Hotline support of original source + * code IP shall only address issues and questions related + * to the standard Netlist version of the core (and thus + * indirectly, the original core source). + * + * This copyright and support notice must be retained as part + * of this text at all times. (c) Copyright 1995-2005 Xilinx, Inc. + * All rights reserved. + * + ***************************************************************************** + * + * Filename: BLK_MEM_GEN_V2_6.v + * + * Description: + * This file is the Verilog behvarial model for the + * Block Memory Generator Core. + * + ***************************************************************************** + * Author: Xilinx + * + * History: September 6, 2005 Initial revision + *****************************************************************************/ +`timescale 1ps/1ps + +module BLK_MEM_GEN_V2_6_xst + #(parameter C_ADDRA_WIDTH = 5, + parameter C_ADDRB_WIDTH = 5, + parameter C_ALGORITHM = 1, + parameter C_BYTE_SIZE = 9, + parameter C_COMMON_CLK = 1, + parameter C_DEFAULT_DATA = "0", + parameter C_DISABLE_WARN_BHV_COLL = 0, + parameter C_DISABLE_WARN_BHV_RANGE = 0, + parameter C_FAMILY = "virtex5", + parameter C_HAS_ENA = 1, + parameter C_HAS_ENB = 1, + parameter C_HAS_MEM_OUTPUT_REGS_A = 0, + parameter C_HAS_MEM_OUTPUT_REGS_B = 0, + parameter C_HAS_MUX_OUTPUT_REGS_A = 0, + parameter C_HAS_MUX_OUTPUT_REGS_B = 0, + parameter C_MUX_PIPELINE_STAGES = 0, + parameter C_HAS_REGCEA = 0, + parameter C_HAS_REGCEB = 0, + parameter C_HAS_SSRA = 0, + parameter C_HAS_SSRB = 0, + parameter C_INIT_FILE_NAME = "", + parameter C_LOAD_INIT_FILE = 0, + parameter C_MEM_TYPE = 2, + parameter C_PRIM_TYPE = 3, + parameter C_READ_DEPTH_A = 64, + parameter C_READ_DEPTH_B = 64, + parameter C_READ_WIDTH_A = 32, + parameter C_READ_WIDTH_B = 32, + parameter C_SIM_COLLISION_CHECK = "NONE", + parameter C_SINITA_VAL = "0", + parameter C_SINITB_VAL = "0", + parameter C_USE_BYTE_WEA = 0, + parameter C_USE_BYTE_WEB = 0, + parameter C_USE_DEFAULT_DATA = 0, + parameter C_USE_ECC = 0, + parameter C_USE_RAMB16BWER_RST_BHV = 0, + parameter C_WEA_WIDTH = 1, + parameter C_WEB_WIDTH = 1, + parameter C_WRITE_DEPTH_A = 64, + parameter C_WRITE_DEPTH_B = 64, + parameter C_WRITE_MODE_A = "WRITE_FIRST", + parameter C_WRITE_MODE_B = "WRITE_FIRST", + parameter C_WRITE_WIDTH_A = 32, + parameter C_WRITE_WIDTH_B = 32, + parameter C_XDEVICEFAMILY = "virtex5" +) + (input CLKA, + input [C_WRITE_WIDTH_A-1:0] DINA, + input [C_ADDRA_WIDTH-1:0] ADDRA, + input ENA, + input REGCEA, + input [C_WEA_WIDTH-1:0] WEA, + input SSRA, + output [C_READ_WIDTH_A-1:0] DOUTA, + input CLKB, + input [C_WRITE_WIDTH_B-1:0] DINB, + input [C_ADDRB_WIDTH-1:0] ADDRB, + input ENB, + input REGCEB, + input [C_WEB_WIDTH-1:0] WEB, + input SSRB, + output [C_READ_WIDTH_B-1:0] DOUTB, + output DBITERR, + output SBITERR); + + BLK_MEM_GEN_V2_6 + #( + .C_ADDRA_WIDTH (C_ADDRA_WIDTH), + .C_ADDRB_WIDTH (C_ADDRB_WIDTH), + .C_ALGORITHM (C_ALGORITHM), + .C_BYTE_SIZE (C_BYTE_SIZE), + .C_COMMON_CLK (C_COMMON_CLK), + .C_DEFAULT_DATA (C_DEFAULT_DATA), + .C_DISABLE_WARN_BHV_COLL (C_DISABLE_WARN_BHV_COLL), + .C_DISABLE_WARN_BHV_RANGE (C_DISABLE_WARN_BHV_RANGE), + .C_FAMILY (C_FAMILY), + .C_HAS_ENA (C_HAS_ENA), + .C_HAS_ENB (C_HAS_ENB), + .C_HAS_MEM_OUTPUT_REGS_A (C_HAS_MEM_OUTPUT_REGS_A), + .C_HAS_MEM_OUTPUT_REGS_B (C_HAS_MEM_OUTPUT_REGS_B), + .C_HAS_MUX_OUTPUT_REGS_A (C_HAS_MUX_OUTPUT_REGS_A), + .C_HAS_MUX_OUTPUT_REGS_B (C_HAS_MUX_OUTPUT_REGS_B), + .C_MUX_PIPELINE_STAGES (C_MUX_PIPELINE_STAGES), + .C_HAS_REGCEA (C_HAS_REGCEA), + .C_HAS_REGCEB (C_HAS_REGCEB), + .C_HAS_SSRA (C_HAS_SSRA), + .C_HAS_SSRB (C_HAS_SSRB), + .C_INIT_FILE_NAME (C_INIT_FILE_NAME), + .C_LOAD_INIT_FILE (C_LOAD_INIT_FILE), + .C_MEM_TYPE (C_MEM_TYPE), + .C_PRIM_TYPE (C_PRIM_TYPE), + .C_READ_DEPTH_A (C_READ_DEPTH_A), + .C_READ_DEPTH_B (C_READ_DEPTH_B), + .C_READ_WIDTH_A (C_READ_WIDTH_A), + .C_READ_WIDTH_B (C_READ_WIDTH_B), + .C_SIM_COLLISION_CHECK (C_SIM_COLLISION_CHECK), + .C_SINITA_VAL (C_SINITA_VAL), + .C_SINITB_VAL (C_SINITB_VAL), + .C_USE_BYTE_WEA (C_USE_BYTE_WEA), + .C_USE_BYTE_WEB (C_USE_BYTE_WEB), + .C_USE_DEFAULT_DATA (C_USE_DEFAULT_DATA), + .C_USE_ECC (C_USE_ECC), + .C_USE_RAMB16BWER_RST_BHV (C_USE_RAMB16BWER_RST_BHV), + .C_WEA_WIDTH (C_WEA_WIDTH), + .C_WEB_WIDTH (C_WEB_WIDTH), + .C_WRITE_DEPTH_A (C_WRITE_DEPTH_A), + .C_WRITE_DEPTH_B (C_WRITE_DEPTH_B), + .C_WRITE_MODE_A (C_WRITE_MODE_A), + .C_WRITE_MODE_B (C_WRITE_MODE_B), + .C_WRITE_WIDTH_A (C_WRITE_WIDTH_A), + .C_WRITE_WIDTH_B (C_WRITE_WIDTH_B), + .C_XDEVICEFAMILY (C_XDEVICEFAMILY) + ) blk_mem_gen_v2_6_dut ( + .DINA (DINA), + .DINB (DINB), + .ADDRA (ADDRA), + .ADDRB (ADDRB), + .ENA (ENA), + .ENB (ENB), + .REGCEA (REGCEA), + .REGCEB (REGCEB), + .WEA (WEA), + .WEB (WEB), + .SSRA (SSRA), + .SSRB (SSRB), + .CLKA (CLKA), + .CLKB (CLKB), + .DOUTA (DOUTA), + .DOUTB (DOUTB), + .DBITERR (DBITERR), + .SBITERR (SBITERR) +); + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/BLK_MEM_GEN_V2_7.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/BLK_MEM_GEN_V2_7.v new file mode 100644 index 0000000..e630ad6 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/BLK_MEM_GEN_V2_7.v @@ -0,0 +1,1257 @@ +/****************************************************************************** + * + * Block Memory Generator Core - Block Memory Behavioral Model + * + * Copyright(C) 2005 by Xilinx, Inc. All rights reserved. + * This text/file contains proprietary, confidential + * information of Xilinx, Inc., is distributed under + * license from Xilinx, Inc., and may be used, copied + * and/or disclosed only pursuant to the terms of a valid + * license agreement with Xilinx, Inc. Xilinx hereby + * grants you a license to use this text/file solely for + * design, simulation, implementation and creation of + * design files limited to Xilinx devices or technologies. + * Use with non-Xilinx devices or technologies is expressly + * prohibited and immediately terminates your license unless + * covered by a separate agreement. + * + * Xilinx is providing this design, code, or information + * "as-is" solely for use in developing programs and + * solutions for Xilinx devices, with no obligation on the + * part of Xilinx to provide support. By providing this design, + * code, or information as one possible implementation of + * this feature, application or standard, Xilinx is making no + * representation that this implementation is free from any + * claims of infringement. You are responsible for obtaining + * any rights you may require for your implementation. + * Xilinx expressly disclaims any warranty whatsoever with + * respect to the adequacy of the implementation, including + * but not limited to any warranties or representations that this + * implementation is free from claims of infringement, implied + * warranties of merchantability or fitness for a particular + * purpose. + * + * Xilinx products are not intended for use in life support + * appliances, devices, or systems. Use in such applications is + * expressly prohibited. + * + * Any modifications that are made to the Source Code are + * done at the user's sole risk and will be unsupported. + * The Xilinx Support Hotline does not have access to source + * code and therefore cannot answer specific questions related + * to source HDL. The Xilinx Hotline support of original source + * code IP shall only address issues and questions related + * to the standard Netlist version of the core (and thus + * indirectly, the original core source). + * + * This copyright and support notice must be retained as part + * of this text at all times. (c) Copyright 1995-2005 Xilinx, Inc. + * All rights reserved. + * + ***************************************************************************** + * + * Filename: BLK_MEM_GEN_V2_7.v + * + * Description: + * This file is the Verilog behvarial model for the + * Block Memory Generator Core. + * + ***************************************************************************** + * Author: Xilinx + * + * History: January 11, 2006 Initial revision + * June 11, 2007 Added independent register stages for + * Port A and Port B (IP1_Jm/v2.5) + * August 28, 2007 Added mux pipeline stages feature (IP2_Jm/v2.6) + *****************************************************************************/ +`timescale 1ps/1ps + +//****************************************************************************** +// Output Register Stage module +// +// This module builds the output register stages of the memory. This module is +// instantiated in the main memory module (BLK_MEM_GEN_V2_7) which is +// declared/implemented further down in this file. +//****************************************************************************** + +module BLK_MEM_GEN_V2_7_output_stage + #(parameter C_DATA_WIDTH = 32, + parameter C_HAS_SSR = 0, + parameter C_SINIT_VAL = "0", + parameter C_HAS_REGCE = 0, + parameter C_HAS_EN = 0, + parameter C_USE_ECC = 0, + parameter C_FAMILY = "virtex5", + parameter C_XDEVICEFAMILY = "virtex5", + parameter C_USE_RAMB16BWER_RST_BHV = 0, + parameter C_HAS_MEM_OUTPUT_REGS = 0, + parameter num_stages = 1, + parameter flop_delay = 100) + + (input CLK, + input SSR, + input REGCE, + input EN, + input [C_DATA_WIDTH-1:0] DIN, + output reg [C_DATA_WIDTH-1:0] DOUT); + + localparam reg_stages = (num_stages == 0) ? 0 : num_stages-1; + // Declare the pipeline registers + // (includes mem output reg, mux pipeline stages, and mux output reg) + reg [C_DATA_WIDTH*reg_stages-1:0] out_regs; + + reg [C_DATA_WIDTH*8-1:0] sinit_str = C_SINIT_VAL; + reg [C_DATA_WIDTH-1:0] sinit_val; + + //********************************************* + // Wire off optional inputs based on parameters + //********************************************* + wire en_i; + wire regce_i; + wire ssr_i; + + // Internal enable for output registers is tied to user EN or '1' depending + // on parameters + // For V4 ECC, EN is always 1 + // Virtex-4 ECC Not Yet Supported + assign en_i = (C_HAS_EN==0 || EN) + || (C_USE_ECC && C_FAMILY=="virtex4"); + + // Internal register enable for output registers is tied to user REGCE, EN or + // '1' depending on parameters + // For V4 ECC, REGCE is always 1 + // Virtex-4 ECC Not Yet Supported + assign regce_i = ((C_HAS_REGCE==1) && REGCE) || + ((C_HAS_REGCE==0) && (C_HAS_EN==0 || EN)) + || (C_USE_ECC && C_FAMILY=="virtex4"); + + //Internal SRR is tied to user SSR or '0' depending on parameters + assign ssr_i = (C_HAS_SSR==1) && SSR; + + //**************************************************** + // Power on: load up the output registers and latches + //**************************************************** + initial begin + if (!($sscanf(sinit_str, "%h", sinit_val))) begin + sinit_val = 0; + end + DOUT = sinit_val; + // This will be one wider than need, but 0 is an error + out_regs = {(reg_stages+1){sinit_val}}; + end + + //*********************************************** + // num_stages = 0 (No output registers. RAM only) + //*********************************************** + generate if (num_stages == 0) begin : zero_stages + always @* begin + DOUT = DIN; + end + end + endgenerate + + //*********************************************** + // num_stages = 1 + // (Mem Output Reg only or Mux Output Reg only) + //*********************************************** + // Because c_use_ramb16bwer_rst_bhv is common for both Port A and Port B, + // the corresponding C_HAS_MEM_OUTPUT_REGS_* has to be checked to determine + // the DOUT reset behavior for each port. + + // Possible valid combinations: (assuming C_HAS_MUX_OUTPUT_REGS_[A/B]=0) + // Note: C_HAS_MUX_OUTPUT_REGS_*=0 when (C_HAS_MEM_OUTPUT_REGS_*=1 AND + // C_USE_RAMB16BWER_RST_BHV=1 AND + // C_HAS_SSR*=1) + + // +-----------------------------+------------+------------------------+ + // |C_USE_RAMB16BWER|C_HAS_MEM |C_HAS_MEM | Reset Behavior | + // | _RST_BHV |_OUTPUT_REGS|_OUTPUT_REGS| | + // | | _A | _B | | + // +----------------+------------+------------+------------------------+ + // | 0 | x | x | A/B=Normal | + // +----------------+------------+------------+------------------------+ + // | 1 | 1 | 0 |A=Special if HAS_SSRA=1 | + // | | | |B=Normal | + // +----------------+------------+------------+------------------------+ + // | 1 | 0 | 1 |A=Normal | + // | | | |B=Special if HAS_SSRB=1 | + // +----------------+------------+------------+------------------------+ + // | 1 | 1 | 1 |A=Special if HAS_SSRA=1 | + // | | | |B=Special if HAS_SSRB=1 | + // +----------------+------------+------------+------------------------+ + // + // x = anything + // Normal = Normal V5 like behavior + // Special = Special RAMB16BWER primitive behavior for Spartan-3adsp + + // Normal V5 like behavior + generate if (num_stages == 1 && + (C_USE_RAMB16BWER_RST_BHV==0 || + C_HAS_MEM_OUTPUT_REGS==0 || + C_HAS_SSR==0)) begin : one_stages_norm + + always @(posedge CLK) begin + if (regce_i && ssr_i) begin + DOUT <= #flop_delay sinit_val; + end else if (regce_i) begin + DOUT <= #flop_delay DIN; + end + end + end + endgenerate + + // Special RAMB16BWER primitive behavior for Spartan-3adsp + generate if (num_stages == 1 && + C_USE_RAMB16BWER_RST_BHV==1 && + C_HAS_MEM_OUTPUT_REGS==1 && + C_HAS_SSR==1 ) begin : one_stages_s3adsp + + always @(posedge CLK) begin + if (en_i && ssr_i) begin + DOUT <= #flop_delay sinit_val; + end else if (regce_i) begin + DOUT <= #flop_delay DIN; + end + end + end + endgenerate + + //************************************************************ + // num_stages > 1 + // Mem Output Reg + Mux Output Reg + // or + // Mem Output Reg + Mux Pipeline Stages (>0) + Mux Output Reg + // or + // Mux Pipeline Stages (>0) + Mux Output Reg + //************************************************************* + generate if (num_stages > 1) begin : multi_stage + always @(posedge CLK) begin + if (regce_i && ssr_i) begin + DOUT <= #flop_delay sinit_val; + end else if (regce_i) begin + DOUT <= #flop_delay + out_regs[C_DATA_WIDTH*(num_stages-2)+:C_DATA_WIDTH]; + end + + // Shift the data through the output stages + if (en_i) begin + out_regs <= #flop_delay + (out_regs << C_DATA_WIDTH) | DIN; + end + end + end + endgenerate +endmodule + + +//****************************************************************************** +// Main Memory module +// +// This module is the top-level behavioral model and this implements the RAM +//****************************************************************************** +module BLK_MEM_GEN_V2_7 + #(parameter C_ADDRA_WIDTH = 5, + parameter C_ADDRB_WIDTH = 5, + parameter C_ALGORITHM = 2, + parameter C_BYTE_SIZE = 8, + parameter C_COMMON_CLK = 1, + parameter C_CORENAME = "blk_mem_gen_v2_7", + parameter C_DEFAULT_DATA = "0", + parameter C_DISABLE_WARN_BHV_COLL = 0, + parameter C_DISABLE_WARN_BHV_RANGE = 0, + parameter C_FAMILY = "virtex4", + parameter C_HAS_ENA = 1, + parameter C_HAS_ENB = 1, + parameter C_HAS_MEM_OUTPUT_REGS_A = 0, + parameter C_HAS_MEM_OUTPUT_REGS_B = 0, + parameter C_HAS_MUX_OUTPUT_REGS_A = 0, + parameter C_HAS_MUX_OUTPUT_REGS_B = 0, + parameter C_MUX_PIPELINE_STAGES = 0, + parameter C_HAS_REGCEA = 0, + parameter C_HAS_REGCEB = 0, + parameter C_HAS_SSRA = 0, + parameter C_HAS_SSRB = 0, + parameter C_INIT_FILE_NAME = "", + parameter C_LOAD_INIT_FILE = 0, + parameter C_MEM_TYPE = 2, + parameter C_PRIM_TYPE = 3, + parameter C_READ_DEPTH_A = 64, + parameter C_READ_DEPTH_B = 64, + parameter C_READ_WIDTH_A = 32, + parameter C_READ_WIDTH_B = 32, + parameter C_SIM_COLLISION_CHECK = "NONE", + parameter C_SINITA_VAL = "0", + parameter C_SINITB_VAL = "0", + parameter C_USE_BYTE_WEA = 0, + parameter C_USE_BYTE_WEB = 0, + parameter C_USE_DEFAULT_DATA = 0, + parameter C_USE_ECC = 0, + parameter C_USE_RAMB16BWER_RST_BHV = 0, + parameter C_WEA_WIDTH = 1, + parameter C_WEB_WIDTH = 1, + parameter C_WRITE_DEPTH_A = 64, + parameter C_WRITE_DEPTH_B = 64, + parameter C_WRITE_MODE_A = "WRITE_FIRST", + parameter C_WRITE_MODE_B = "WRITE_FIRST", + parameter C_WRITE_WIDTH_A = 32, + parameter C_WRITE_WIDTH_B = 32, + parameter C_XDEVICEFAMILY = "virtex4" +) + + (input CLKA, + input [C_WRITE_WIDTH_A-1:0] DINA, + input [C_ADDRA_WIDTH-1:0] ADDRA, + input ENA, + input REGCEA, + input [C_WEA_WIDTH-1:0] WEA, + input SSRA, + output [C_READ_WIDTH_A-1:0] DOUTA, + input CLKB, + input [C_WRITE_WIDTH_B-1:0] DINB, + input [C_ADDRB_WIDTH-1:0] ADDRB, + input ENB, + input REGCEB, + input [C_WEB_WIDTH-1:0] WEB, + input SSRB, + output [C_READ_WIDTH_B-1:0] DOUTB, + output DBITERR, + output SBITERR + ); + +// Note: C_CORENAME parameter is hard-coded to "blk_mem_gen_v2_7" and it is +// only used by this module to print warning messages. It is neither passed +// down from blk_mem_gen_v2_7_xst.v nor present in the instantiation template +// coregen generates + + //*************************************************************************** + // constants for the core behavior + //*************************************************************************** + // file handles for logging + //-------------------------------------------------- + localparam addrfile = 32'h8000_0001; // stdout for addr out of range + localparam collfile = 32'h8000_0001; // stdout for coll detection + localparam errfile = 32'h8000_0001; // stdout for file I/O errors + + // other constants + //-------------------------------------------------- + localparam coll_delay = 2000; // 2 ns + + // locally derived parameters to determine memory shape + //----------------------------------------------------- + localparam min_width_a = (C_WRITE_WIDTH_A < C_READ_WIDTH_A) ? + C_WRITE_WIDTH_A : C_READ_WIDTH_A; + localparam min_width_b = (C_WRITE_WIDTH_B < C_READ_WIDTH_B) ? + C_WRITE_WIDTH_B : C_READ_WIDTH_B; + localparam min_width = (min_width_a < min_width_b) ? + min_width_a : min_width_b; + + localparam max_width_a = (C_WRITE_WIDTH_A > C_READ_WIDTH_A) ? + C_WRITE_WIDTH_A : C_READ_WIDTH_A; + localparam max_width_b = (C_WRITE_WIDTH_B > C_READ_WIDTH_B) ? + C_WRITE_WIDTH_B : C_READ_WIDTH_B; + localparam max_width = (max_width_a > max_width_b) ? + max_width_a : max_width_b; + + localparam max_depth_a = (C_WRITE_DEPTH_A > C_READ_DEPTH_A) ? + C_WRITE_DEPTH_A : C_READ_DEPTH_A; + localparam max_depth_b = (C_WRITE_DEPTH_B > C_READ_DEPTH_B) ? + C_WRITE_DEPTH_B : C_READ_DEPTH_B; + localparam max_depth = (max_depth_a > max_depth_b) ? + max_depth_a : max_depth_b; + + + // locally derived parameters to assist memory access + //---------------------------------------------------- + // Calculate the width ratios of each port with respect to the narrowest + // port + localparam write_width_ratio_a = C_WRITE_WIDTH_A/min_width; + localparam read_width_ratio_a = C_READ_WIDTH_A/min_width; + localparam write_width_ratio_b = C_WRITE_WIDTH_B/min_width; + localparam read_width_ratio_b = C_READ_WIDTH_B/min_width; + + // To modify the LSBs of the 'wider' data to the actual + // address value + //---------------------------------------------------- + localparam write_addr_a_div = C_WRITE_WIDTH_A/min_width_a; + localparam read_addr_a_div = C_READ_WIDTH_A/min_width_a; + localparam write_addr_b_div = C_WRITE_WIDTH_B/min_width_b; + localparam read_addr_b_div = C_READ_WIDTH_B/min_width_b; + + // If byte writes aren't being used, make sure byte_size is not + // wider than the memory elements to avoid compilation warnings + localparam byte_size = (C_BYTE_SIZE < min_width) ? C_BYTE_SIZE : min_width; + + // The memory + reg [min_width-1:0] memory [0:max_depth-1]; + // Memory output 'latches' + reg [C_READ_WIDTH_A-1:0] memory_out_a; + reg [C_READ_WIDTH_B-1:0] memory_out_b; + // Reset values + reg [C_READ_WIDTH_A-1:0] sinita_val; + reg [C_READ_WIDTH_B-1:0] sinitb_val; + + // Collision detect + reg is_collision; + reg is_collision_a, is_collision_delay_a; + reg is_collision_b, is_collision_delay_b; + + // Temporary variables for initialization + //--------------------------------------- + integer status; + reg [639:0] err_str; + integer initfile; + // data input buffer + reg [C_WRITE_WIDTH_A-1:0] mif_data; + // string values in hex + reg [C_READ_WIDTH_A*8-1:0] sinita_str = C_SINITA_VAL; + reg [C_READ_WIDTH_B*8-1:0] sinitb_str = C_SINITB_VAL; + reg [C_WRITE_WIDTH_A*8-1:0] default_data_str = C_DEFAULT_DATA; + // initialization filename + reg [1023*8-1:0] init_file_str = C_INIT_FILE_NAME; + + // Internal configuration parameters + //--------------------------------------------- + localparam flop_delay = 100; // 100 ps + localparam single_port = (C_MEM_TYPE==0 || C_MEM_TYPE==3); + localparam is_rom = (C_MEM_TYPE==3 || C_MEM_TYPE==4); + localparam has_a_write = (!is_rom); + localparam has_b_write = (C_MEM_TYPE==2); + localparam has_a_read = (C_MEM_TYPE!=1); + localparam has_b_read = (!single_port); + localparam has_b_port = (has_b_read || has_b_write); + + // Calculate the mux pipeline register stages for Port A and Port B + //------------------------------------------------------------------ + localparam mux_pipeline_stages_a = (C_HAS_MUX_OUTPUT_REGS_A) ? C_MUX_PIPELINE_STAGES : 0; + localparam mux_pipeline_stages_b = (C_HAS_MUX_OUTPUT_REGS_B) ? C_MUX_PIPELINE_STAGES : 0; + + // Calculate total number of register stages in the core + // ----------------------------------------------------- + // Note: Virtex-4 ECC Not Yet Supported + localparam num_output_stages_a = + (C_FAMILY=="virtex4" && C_USE_ECC==1) ? + (C_HAS_MEM_OUTPUT_REGS_A+mux_pipeline_stages_a+C_HAS_MUX_OUTPUT_REGS_A+1): + (C_HAS_MEM_OUTPUT_REGS_A+mux_pipeline_stages_a+C_HAS_MUX_OUTPUT_REGS_A); + + localparam num_output_stages_b = + (C_FAMILY=="virtex4" && C_USE_ECC==1) ? + (C_HAS_MEM_OUTPUT_REGS_B+mux_pipeline_stages_b+C_HAS_MUX_OUTPUT_REGS_B+1): + (C_HAS_MEM_OUTPUT_REGS_B+mux_pipeline_stages_b+C_HAS_MUX_OUTPUT_REGS_B); + + wire ena_i; + wire enb_i; + wire reseta_i; + wire resetb_i; + wire [C_WEA_WIDTH-1:0] wea_i; + wire [C_WEB_WIDTH-1:0] web_i; + wire rea_i; + wire reb_i; + + // ECC SBITERR/DBITERR Outputs + // The ECC Behavior is not modeled by the behavioral models, therefore + // the SBITERR and DBITERR outputs are explicitly tied to 0. + assign SBITERR = 0; + assign DBITERR = 0; + + + // This effectively wires off optional inputs + assign ena_i = (C_HAS_ENA==0) || ENA; + assign enb_i = ((C_HAS_ENB==0) || ENB) && has_b_port; + assign wea_i = (has_a_write && ena_i) ? WEA : 'b0; + assign web_i = (has_b_write && enb_i) ? WEB : 'b0; + assign rea_i = (has_a_read) ? ena_i : 'b0; + assign reb_i = (has_b_read) ? enb_i : 'b0; + + // These signals reset the memory latches + // Because c_use_ramb16bwer_rst_bhv is common for both Port A and Port B, + // the corresponding C_HAS_MEM_OUTPUT_REG_* has to be checked as well to + // determine the reset behavior for each port. + + assign reseta_i = + ((C_HAS_SSRA==1 && SSRA && ena_i && num_output_stages_a==0) || + (C_HAS_SSRA==1 && SSRA && ena_i && C_USE_RAMB16BWER_RST_BHV==1 && + C_HAS_MEM_OUTPUT_REGS_A==1 && C_HAS_MUX_OUTPUT_REGS_A==0)); + + assign resetb_i = + ((C_HAS_SSRB==1 && SSRB && enb_i && num_output_stages_b==0) || + (C_HAS_SSRB==1 && SSRB && enb_i && C_USE_RAMB16BWER_RST_BHV==1 && + C_HAS_MEM_OUTPUT_REGS_B==1 && C_HAS_MUX_OUTPUT_REGS_B==0)); + + // Tasks to access the memory + //--------------------------- + //************** + // write_a + //************** + task write_a + (input reg [C_ADDRA_WIDTH-1:0] addr, + input reg [C_WEA_WIDTH-1:0] byte_en, + input reg [C_WRITE_WIDTH_A-1:0] data); + reg [C_WRITE_WIDTH_A-1:0] current_contents; + reg [C_ADDRA_WIDTH-1:0] address; + integer i; + begin + // Shift the address by the ratio + address = (addr/write_addr_a_div); + if (address >= C_WRITE_DEPTH_A) begin + if (!C_DISABLE_WARN_BHV_RANGE) begin + $fdisplay(addrfile, + "%0s WARNING: Address %0h is outside range for A Write", + C_CORENAME, addr); + end + + // valid address + end else begin + + // Combine w/ byte writes + if (C_USE_BYTE_WEA) begin + + // Get the current memory contents + if (write_width_ratio_a == 1) begin + // Workaround for IUS 5.5 part-select issue + current_contents = memory[address]; + end else begin + for (i = 0; i < write_width_ratio_a; i = i + 1) begin + current_contents[min_width*i+:min_width] + = memory[address*write_width_ratio_a + i]; + end + end + + // Apply incoming bytes + if (C_WEA_WIDTH == 1) begin + // Workaround for IUS 5.5 part-select issue + if (byte_en[0]) begin + current_contents = data; + end + end else begin + for (i = 0; i < C_WEA_WIDTH; i = i + 1) begin + if (byte_en[i]) begin + current_contents[byte_size*i+:byte_size] + = data[byte_size*i+:byte_size]; + end + end + end + + // No byte-writes, overwrite the whole word + end else begin + current_contents = data; + end + + // Write data to memory + if (write_width_ratio_a == 1) begin + // Workaround for IUS 5.5 part-select issue + memory[address*write_width_ratio_a] = current_contents; + end else begin + for (i = 0; i < write_width_ratio_a; i = i + 1) begin + memory[address*write_width_ratio_a + i] + = current_contents[min_width*i+:min_width]; + end + end + + end + end + endtask + + //************** + // write_b + //************** + task write_b + (input reg [C_ADDRB_WIDTH-1:0] addr, + input reg [C_WEB_WIDTH-1:0] byte_en, + input reg [C_WRITE_WIDTH_B-1:0] data); + reg [C_WRITE_WIDTH_B-1:0] current_contents; + reg [C_ADDRB_WIDTH-1:0] address; + integer i; + begin + // Shift the address by the ratio + address = (addr/write_addr_b_div); + if (address >= C_WRITE_DEPTH_B) begin + if (!C_DISABLE_WARN_BHV_RANGE) begin + $fdisplay(addrfile, + "%0s WARNING: Address %0h is outside range for B Write", + C_CORENAME, addr); + end + + // valid address + end else begin + + // Combine w/ byte writes + if (C_USE_BYTE_WEB) begin + + // Get the current memory contents + if (write_width_ratio_b == 1) begin + // Workaround for IUS 5.5 part-select issue + current_contents = memory[address]; + end else begin + for (i = 0; i < write_width_ratio_b; i = i + 1) begin + current_contents[min_width*i+:min_width] + = memory[address*write_width_ratio_b + i]; + end + end + + // Apply incoming bytes + if (C_WEB_WIDTH == 1) begin + // Workaround for IUS 5.5 part-select issue + if (byte_en[0]) begin + current_contents = data; + end + end else begin + for (i = 0; i < C_WEB_WIDTH; i = i + 1) begin + if (byte_en[i]) begin + current_contents[byte_size*i+:byte_size] + = data[byte_size*i+:byte_size]; + end + end + end + + // No byte-writes, overwrite the whole word + end else begin + current_contents = data; + end + + // Write data to memory + if (write_width_ratio_b == 1) begin + // Workaround for IUS 5.5 part-select issue + memory[address*write_width_ratio_b] = current_contents; + end else begin + for (i = 0; i < write_width_ratio_b; i = i + 1) begin + memory[address*write_width_ratio_b + i] + = current_contents[min_width*i+:min_width]; + end + end + end + end + endtask + + //************** + // read_a + //************** + task read_a + (input reg [C_ADDRA_WIDTH-1:0] addr, + input reg reset); + reg [C_ADDRA_WIDTH-1:0] address; + integer i; + begin + + if (reset) begin + memory_out_a <= #flop_delay sinita_val; + end else begin + // Shift the address by the ratio + address = (addr/read_addr_a_div); + if (address >= C_READ_DEPTH_A) begin + if (!C_DISABLE_WARN_BHV_RANGE) begin + $fdisplay(addrfile, + "%0s WARNING: Address %0h is outside range for A Read", + C_CORENAME, addr); + end + + // valid address + end else begin + + if (read_width_ratio_a==1) begin + memory_out_a <= #flop_delay memory[address*read_width_ratio_a]; + end else begin + // Increment through the 'partial' words in the memory + for (i = 0; i < read_width_ratio_a; i = i + 1) begin + memory_out_a[min_width*i+:min_width] + <= #flop_delay memory[address*read_width_ratio_a + i]; + end + end + + end + end + end + endtask + + //************** + // read_b + //************** + task read_b + (input reg [C_ADDRB_WIDTH-1:0] addr, + input reg reset); + reg [C_ADDRB_WIDTH-1:0] address; + integer i; + begin + + if (reset) begin + memory_out_b <= #flop_delay sinitb_val; + end else begin + // Shift the address + address = (addr/read_addr_b_div); + if (address >= C_READ_DEPTH_B) begin + if (!C_DISABLE_WARN_BHV_RANGE) begin + $fdisplay(addrfile, + "%0s WARNING: Address %0h is outside range for B Read", + C_CORENAME, addr); + end + + // valid address + end else begin + + if (read_width_ratio_b==1) begin + memory_out_b <= #flop_delay memory[address*read_width_ratio_b]; + end else begin + // Increment through the 'partial' words in the memory + for (i = 0; i < read_width_ratio_b; i = i + 1) begin + memory_out_b[min_width*i+:min_width] + <= #flop_delay memory[address*read_width_ratio_b + i]; + end + end + + end + end + end + endtask + + //************** + // init_memory + //************** + task init_memory; + integer i, addr_step; + integer status; + reg [C_WRITE_WIDTH_A-1:0] default_data; + begin + default_data = 0; + + //Display output message indicating that the behavioral model is being initialized + if (C_USE_DEFAULT_DATA || C_LOAD_INIT_FILE) $display(" Block Memory Generator CORE Generator module loading initial data..."); + + // Convert the default to hex + if (C_USE_DEFAULT_DATA) begin + if (default_data_str == "") begin + $fdisplay(errfile, "%0s ERROR: C_DEFAULT_DATA is empty!", C_CORENAME); + $finish; + end else begin + status = $sscanf(default_data_str, "%h", default_data); + if (status == 0) begin + $fdisplay(errfile, {"%0s ERROR: Unsuccessful hexadecimal read", + "from C_DEFAULT_DATA: %0s"}, + C_CORENAME, C_DEFAULT_DATA); + $finish; + end + end + end + + // Step by write_addr_a_div through the memory via the + // Port A write interface to hit every location once + addr_step = write_addr_a_div; + + // 'write' to every location with default (or 0) + for (i = 0; i < C_WRITE_DEPTH_A*addr_step; i = i + addr_step) begin + write_a(i, {C_WEA_WIDTH{1'b1}}, default_data); + end + + // Get specialized data from the MIF file + if (C_LOAD_INIT_FILE) begin + if (init_file_str == "") begin + $fdisplay(errfile, "%0s ERROR: C_INIT_FILE_NAME is empty!", + C_CORENAME); + $finish; + end else begin + initfile = $fopen(init_file_str, "r"); + if (initfile == 0) begin + $fdisplay(errfile, {"%0s, ERROR: Problem opening", + "C_INIT_FILE_NAME: %0s!"}, + C_CORENAME, init_file_str); + $finish; + end else begin + // loop through the mif file, loading in the data + for (i = 0; i < C_WRITE_DEPTH_A*addr_step; i = i + addr_step) begin + status = $fscanf(initfile, "%b", mif_data); + if (status > 0) begin + write_a(i, {C_WEA_WIDTH{1'b1}}, mif_data); + end + end + $fclose(initfile); + end //initfile + end //init_file_str + end //C_LOAD_INIT_FILE + + //Display output message indicating that the behavioral model is done initializing + if (C_USE_DEFAULT_DATA || C_LOAD_INIT_FILE) + $display(" Block Memory Generator data initialization complete."); + end + endtask + + //************** + // log2roundup + //************** + function integer log2roundup (input integer data_value); + integer width; + integer cnt; + begin + width = 0; + + if (data_value > 1) begin + for(cnt=1 ; cnt < data_value ; cnt = cnt * 2) begin + width = width + 1; + end //loop + end //if + + log2roundup = width; + + end //log2roundup + endfunction + + //******************* + // collision_check + //******************* + function integer collision_check (input reg [C_ADDRA_WIDTH-1:0] addr_a, + input integer iswrite_a, + input reg [C_ADDRB_WIDTH-1:0] addr_b, + input integer iswrite_b); + reg [C_ADDRA_WIDTH-1:0] base_addr_a; + reg [C_ADDRB_WIDTH-1:0] base_addr_b; + integer ratio_a, ratio_b; + integer lo_addr_wider, hi_addr_wider; + integer lo_addr_narrow, hi_addr_narrow; + reg c_aw_bw, c_aw_br, c_ar_bw; + integer write_addr_a_width, read_addr_a_width; + integer write_addr_b_width, read_addr_b_width; + + begin + + c_aw_bw = 0; + c_aw_br = 0; + c_ar_bw = 0; + + // Determine the effective address widths for each of the 4 ports + write_addr_a_width = C_ADDRA_WIDTH-log2roundup(write_addr_a_div); + read_addr_a_width = C_ADDRA_WIDTH-log2roundup(read_addr_a_div); + write_addr_b_width = C_ADDRB_WIDTH-log2roundup(write_addr_b_div); + read_addr_b_width = C_ADDRB_WIDTH-log2roundup(read_addr_b_div); + + + //Look for a write-write collision. In order for a write-write + //collision to exist, both ports must have a write transaction. + if (iswrite_a && iswrite_b) begin + if (write_addr_a_width > write_addr_b_width) begin + //write_addr_b_width is smaller, so scale both addresses to that + // width for comparing write_addr_a and write_addr_b + //addr_a starts as C_ADDRA_WIDTH, + // scale it down to write_addr_b_width + //addr_b starts as C_ADDRB_WIDTH, + // scale it down to write_addr_b_width + //Once both are scaled to write_addr_b_width, compare. + if (((addr_a)/2**(C_ADDRA_WIDTH-write_addr_b_width)) == ((addr_b)/2**(C_ADDRB_WIDTH-write_addr_b_width))) begin + c_aw_bw = 1; + end else begin + c_aw_bw = 0; + end + end else begin + //write_addr_a_width is smaller, so scale both addresses to that + // width for comparing write_addr_a and write_addr_b + //addr_a starts as C_ADDRA_WIDTH, + // scale it down to write_addr_a_width + //addr_b starts as C_ADDRB_WIDTH, + // scale it down to write_addr_a_width + //Once both are scaled to write_addr_a_width, compare. + if (((addr_b)/2**(C_ADDRB_WIDTH-write_addr_a_width)) == ((addr_a)/2**(C_ADDRA_WIDTH-write_addr_a_width))) begin + c_aw_bw = 1; + end else begin + c_aw_bw = 0; + end + end //width + end //iswrite_a and iswrite_b + + //If the B port is reading (which means it is enabled - so could be + // a TX_WRITE or TX_READ), then check for a write-read collision). + //This could happen whether or not a write-write collision exists due + // to asymmetric write/read ports. + if (iswrite_a) begin + if (write_addr_a_width > read_addr_b_width) begin + //read_addr_b_width is smaller, so scale both addresses to that + // width for comparing write_addr_a and read_addr_b + //addr_a starts as C_ADDRA_WIDTH, + // scale it down to read_addr_b_width + //addr_b starts as C_ADDRB_WIDTH, + // scale it down to read_addr_b_width + //Once both are scaled to read_addr_b_width, compare. + if (((addr_a)/2**(C_ADDRA_WIDTH-read_addr_b_width)) == ((addr_b)/2**(C_ADDRB_WIDTH-read_addr_b_width))) begin + c_aw_br = 1; + end else begin + c_aw_br = 0; + end + end else begin + //write_addr_a_width is smaller, so scale both addresses to that + // width for comparing write_addr_a and read_addr_b + //addr_a starts as C_ADDRA_WIDTH, + // scale it down to write_addr_a_width + //addr_b starts as C_ADDRB_WIDTH, + // scale it down to write_addr_a_width + //Once both are scaled to write_addr_a_width, compare. + if (((addr_b)/2**(C_ADDRB_WIDTH-write_addr_a_width)) == ((addr_a)/2**(C_ADDRA_WIDTH-write_addr_a_width))) begin + c_aw_br = 1; + end else begin + c_aw_br = 0; + end + end //width + end //iswrite_a + + //If the A port is reading (which means it is enabled - so could be + // a TX_WRITE or TX_READ), then check for a write-read collision). + //This could happen whether or not a write-write collision exists due + // to asymmetric write/read ports. + if (iswrite_b) begin + if (read_addr_a_width > write_addr_b_width) begin + //write_addr_b_width is smaller, so scale both addresses to that + // width for comparing read_addr_a and write_addr_b + //addr_a starts as C_ADDRA_WIDTH, + // scale it down to write_addr_b_width + //addr_b starts as C_ADDRB_WIDTH, + // scale it down to write_addr_b_width + //Once both are scaled to write_addr_b_width, compare. + if (((addr_a)/2**(C_ADDRA_WIDTH-write_addr_b_width)) == ((addr_b)/2**(C_ADDRB_WIDTH-write_addr_b_width))) begin + c_ar_bw = 1; + end else begin + c_ar_bw = 0; + end + end else begin + //read_addr_a_width is smaller, so scale both addresses to that + // width for comparing read_addr_a and write_addr_b + //addr_a starts as C_ADDRA_WIDTH, + // scale it down to read_addr_a_width + //addr_b starts as C_ADDRB_WIDTH, + // scale it down to read_addr_a_width + //Once both are scaled to read_addr_a_width, compare. + if (((addr_b)/2**(C_ADDRB_WIDTH-read_addr_a_width)) == ((addr_a)/2**(C_ADDRA_WIDTH-read_addr_a_width))) begin + c_ar_bw = 1; + end else begin + c_ar_bw = 0; + end + end //width + end //iswrite_b + + + // Convert the input addresses in base and offsets for our + // memory array. Ignore LSBs for asymmetric ports + if (iswrite_a) begin + base_addr_a = (addr_a/write_addr_a_div) * write_addr_a_div; + ratio_a = write_width_ratio_a; + end else begin + base_addr_a = (addr_a/read_addr_a_div) * read_addr_a_div; + ratio_a = read_width_ratio_a; + end + if (iswrite_b) begin + base_addr_b = (addr_b/write_addr_b_div) * write_addr_b_div; + ratio_b = write_width_ratio_b; + end else begin + base_addr_b = (addr_b/read_addr_b_div) * read_addr_b_div; + ratio_b = read_width_ratio_b; + end + + // Determine the wider port, and normalized ranges + if (ratio_a >= ratio_b) begin + lo_addr_wider = base_addr_a * ratio_a; + hi_addr_wider = lo_addr_wider + ratio_a; + lo_addr_narrow = base_addr_b * ratio_b; + hi_addr_narrow = lo_addr_narrow + ratio_b; + end else begin + lo_addr_wider = base_addr_b * ratio_b; + hi_addr_wider = lo_addr_wider + ratio_b; + lo_addr_narrow = base_addr_a * ratio_a; + hi_addr_narrow = lo_addr_narrow + ratio_a; + end + + // compare the two ranges of address (narrow inside wider) + //if ((lo_addr_narrow >= lo_addr_wider) && + // (hi_addr_narrow <= hi_addr_wider)) begin + // collision_check = 1; + //end else begin + // collision_check = 0; + //end + + collision_check = c_aw_bw | c_aw_br | c_ar_bw; + + end + endfunction + + //******************************* + // power on values + //******************************* + initial begin + // Load up the memory + init_memory; + // Load up the output registers and latches + if ($sscanf(sinita_str, "%h", sinita_val)) begin + memory_out_a = sinita_val; + end else begin + memory_out_a = 0; + end + if ($sscanf(sinitb_str, "%h", sinitb_val)) begin + memory_out_b = sinitb_val; + end else begin + memory_out_b = 0; + end + + $display("Block Memory Generator CORE Generator module %m is using a behavioral model for simulation which will not precisely model memory collision behavior."); + + end + + //************************************************************************* + // These are the main blocks which schedule read and write operations + //************************************************************************* + + generate if (C_COMMON_CLK) begin : common_clk_scheduling + // Synchronous clocks: schedule port operations with respect to + // both write operating modes + always @(posedge CLKA) begin + case ({C_WRITE_MODE_A, C_WRITE_MODE_B}) + {"WRITE_FIRST","WRITE_FIRST"}: begin + if (wea_i) write_a(ADDRA, wea_i, DINA); + if (web_i) write_b(ADDRB, web_i, DINB); + if (rea_i) read_a(ADDRA, reseta_i); + if (reb_i) read_b(ADDRB, resetb_i); + end + {"READ_FIRST", "WRITE_FIRST"}: begin + if (web_i) write_b(ADDRB, web_i, DINB); + if (reb_i) read_b(ADDRB, resetb_i); + if (rea_i) read_a(ADDRA, reseta_i); + if (wea_i) write_a(ADDRA, wea_i, DINA); + end + {"WRITE_FIRST","READ_FIRST"}: begin + if (wea_i) write_a(ADDRA, wea_i, DINA); + if (rea_i) read_a(ADDRA, reseta_i); + if (reb_i) read_b(ADDRB, resetb_i); + if (web_i) write_b(ADDRB, web_i, DINB); + end + {"READ_FIRST", "READ_FIRST"}: begin + if (rea_i) read_a(ADDRA, reseta_i); + if (reb_i) read_b(ADDRB, resetb_i); + if (wea_i) write_a(ADDRA, wea_i, DINA); + if (web_i) write_b(ADDRB, web_i, DINB); + end + {"WRITE_FIRST","NO_CHANGE"}: begin + if (wea_i) write_a(ADDRA, wea_i, DINA); + if (rea_i) read_a(ADDRA, reseta_i); + if ((reb_i && !web_i) || resetb_i) read_b(ADDRB, resetb_i); + if (web_i) write_b(ADDRB, web_i, DINB); + end + {"READ_FIRST", "NO_CHANGE"}: begin + if (rea_i) read_a(ADDRA, reseta_i); + if ((reb_i && !web_i) || resetb_i) read_b(ADDRB, resetb_i); + if (wea_i) write_a(ADDRA, wea_i, DINA); + if (web_i) write_b(ADDRB, web_i, DINB); + end + {"NO_CHANGE", "WRITE_FIRST"}: begin + if (wea_i) write_a(ADDRA, wea_i, DINA); + if (web_i) write_b(ADDRB, web_i, DINB); + if ((rea_i && !wea_i) || reseta_i) read_a(ADDRA, reseta_i); + if (reb_i) read_b(ADDRB, resetb_i); + end + {"NO_CHANGE", "READ_FIRST"}: begin + if (reb_i) read_b(ADDRB, resetb_i); + if ((rea_i && !wea_i) || reseta_i) read_a(ADDRA, reseta_i); + if (wea_i) write_a(ADDRA, wea_i, DINA); + if (web_i) write_b(ADDRB, web_i, DINB); + end + {"NO_CHANGE", "NO_CHANGE"}: begin + if (wea_i) write_a(ADDRA, wea_i, DINA); + if (web_i) write_b(ADDRB, web_i, DINB); + if ((rea_i && !wea_i) || reseta_i) read_a(ADDRA, reseta_i); + if ((reb_i && !web_i) || resetb_i) read_b(ADDRB, resetb_i); + end + default: begin + if (wea_i) write_a(ADDRA, wea_i, DINA); + if (web_i) write_b(ADDRB, web_i, DINB); + if (rea_i) read_a(ADDRA, reseta_i); + if (reb_i) read_b(ADDRB, resetb_i); + end + endcase + end + + end else begin : asynch_clk_scheduling + // Asynchronous clocks: port operation is independent + always @(posedge CLKA) begin + case (C_WRITE_MODE_A) + "WRITE_FIRST": begin + if (wea_i) write_a(ADDRA, wea_i, DINA); + if (rea_i) read_a(ADDRA, reseta_i); + end + "READ_FIRST": begin + if (rea_i) read_a(ADDRA, reseta_i); + if (wea_i) write_a(ADDRA, wea_i, DINA); + end + "NO_CHANGE": begin + if (wea_i) write_a(ADDRA, wea_i, DINA); + if ((rea_i && !wea_i) || reseta_i) read_a(ADDRA, reseta_i); + end + endcase + end + + always @(posedge CLKB) begin + case (C_WRITE_MODE_B) + "WRITE_FIRST": begin + if (web_i) write_b(ADDRB, web_i, DINB); + if (reb_i) read_b(ADDRB, resetb_i); + end + "READ_FIRST": begin + if (reb_i) read_b(ADDRB, resetb_i); + if (web_i) write_b(ADDRB, web_i, DINB); + end + "NO_CHANGE": begin + if (web_i) write_b(ADDRB, web_i, DINB); + if ((reb_i && !web_i) || resetb_i) read_b(ADDRB, resetb_i); + end + endcase + end + end + endgenerate + + //*************************************************************** + // Instantiate the variable depth output register stage module + //*************************************************************** + // Port A + BLK_MEM_GEN_V2_7_output_stage + #(.C_DATA_WIDTH (C_READ_WIDTH_A), + .C_HAS_SSR (C_HAS_SSRA), + .C_SINIT_VAL (C_SINITA_VAL), + .C_HAS_REGCE (C_HAS_REGCEA), + .C_HAS_EN (C_HAS_ENA), + .C_USE_ECC (C_USE_ECC), + .C_FAMILY (C_FAMILY), + .C_XDEVICEFAMILY (C_XDEVICEFAMILY), + .C_USE_RAMB16BWER_RST_BHV (C_USE_RAMB16BWER_RST_BHV), + .C_HAS_MEM_OUTPUT_REGS (C_HAS_MEM_OUTPUT_REGS_A), + .num_stages (num_output_stages_a), + .flop_delay (flop_delay)) + reg_a + (.CLK (CLKA), + .SSR (SSRA), + .REGCE (REGCEA), + .EN (ENA), + .DIN (memory_out_a), + .DOUT (DOUTA)); + + // Port B + BLK_MEM_GEN_V2_7_output_stage + #(.C_DATA_WIDTH (C_READ_WIDTH_B), + .C_HAS_SSR (C_HAS_SSRB), + .C_SINIT_VAL (C_SINITB_VAL), + .C_HAS_REGCE (C_HAS_REGCEB), + .C_HAS_EN (C_HAS_ENB), + .C_USE_ECC (C_USE_ECC), + .C_FAMILY (C_FAMILY), + .C_XDEVICEFAMILY (C_XDEVICEFAMILY), + .C_USE_RAMB16BWER_RST_BHV (C_USE_RAMB16BWER_RST_BHV), + .C_HAS_MEM_OUTPUT_REGS (C_HAS_MEM_OUTPUT_REGS_B), + .num_stages (num_output_stages_b), + .flop_delay (flop_delay)) + reg_b + (.CLK (CLKB), + .SSR (SSRB), + .REGCE (REGCEB), + .EN (ENB), + .DIN (memory_out_b), + .DOUT (DOUTB)); + + //**************************************************** + // Synchronous collision checks + //**************************************************** + generate if (!C_DISABLE_WARN_BHV_COLL && C_COMMON_CLK) begin : sync_coll + always @(posedge CLKA) begin + // Possible collision if both are enabled and the addresses match + if (ena_i && enb_i) begin + is_collision = collision_check(ADDRA, wea_i, ADDRB, web_i); + end else begin + is_collision = 0; + end + + // If the write port is in READ_FIRST mode, there is no collision + if (C_WRITE_MODE_A=="READ_FIRST" && wea_i && !web_i) begin + is_collision = 0; + end + if (C_WRITE_MODE_B=="READ_FIRST" && web_i && !wea_i) begin + is_collision = 0; + end + + // Only flag if one of the accesses is a write + if (is_collision && (wea_i || web_i)) begin + $fwrite(collfile, "%0s collision detected at time: %0d, ", + C_CORENAME, $time); + $fwrite(collfile, "A %0s address: %0h, B %0s address: %0h\n", + wea_i ? "write" : "read", ADDRA, + web_i ? "write" : "read", ADDRB); + end + end + + //**************************************************** + // Asynchronous collision checks + //**************************************************** + end else if (!C_DISABLE_WARN_BHV_COLL && !C_COMMON_CLK) begin : async_coll + + // Delay A and B addresses in order to mimic setup/hold times + wire [C_ADDRA_WIDTH-1:0] #coll_delay addra_delay = ADDRA; + wire [0:0] #coll_delay wea_delay = wea_i; + wire #coll_delay ena_delay = ena_i; + wire [C_ADDRB_WIDTH-1:0] #coll_delay addrb_delay = ADDRB; + wire [0:0] #coll_delay web_delay = web_i; + wire #coll_delay enb_delay = enb_i; + + // Do the checks w/rt A + always @(posedge CLKA) begin + // Possible collision if both are enabled and the addresses match + if (ena_i && enb_i) begin + is_collision_a = collision_check(ADDRA, wea_i, ADDRB, web_i); + end else begin + is_collision_a = 0; + end + if (ena_i && enb_delay) begin + is_collision_delay_a = collision_check(ADDRA, wea_i, + addrb_delay, web_delay); + end else begin + is_collision_delay_a = 0; + end + + + // Only flag if B access is a write + if (is_collision_a && web_i) begin + $fwrite(collfile, "%0s collision detected at time: %0d, ", + C_CORENAME, $time); + $fwrite(collfile, "A %0s address: %0h, B write address: %0h\n", + wea_i ? "write" : "read", ADDRA, ADDRB); + + end else if (is_collision_delay_a && web_delay) begin + $fwrite(collfile, "%0s collision detected at time: %0d, ", + C_CORENAME, $time); + $fwrite(collfile, "A %0s address: %0h, B write address: %0h\n", + wea_i ? "write" : "read", ADDRA, addrb_delay); + end + + end + + // Do the checks w/rt B + always @(posedge CLKB) begin + + // Possible collision if both are enabled and the addresses match + if (ena_i && enb_i) begin + is_collision_b = collision_check(ADDRA, wea_i, ADDRB, web_i); + end else begin + is_collision_b = 0; + end + if (ena_delay && enb_i) begin + is_collision_delay_b = collision_check(addra_delay, wea_delay, + ADDRB, web_i); + end else begin + is_collision_delay_b = 0; + end + + + // Only flag if A access is a write + if (is_collision_b && wea_i) begin + $fwrite(collfile, "%0s collision detected at time: %0d, ", + C_CORENAME, $time); + $fwrite(collfile, "A write address: %0h, B %s address: %0h\n", + ADDRA, web_i ? "write" : "read", ADDRB); + + end else if (is_collision_delay_b && wea_delay) begin + $fwrite(collfile, "%0s collision detected at time: %0d, ", + C_CORENAME, $time); + $fwrite(collfile, "A write address: %0h, B %s address: %0h\n", + addra_delay, web_i ? "write" : "read", ADDRB); + end + + end + end + endgenerate + +endmodule diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/BLK_MEM_GEN_V2_7_xst.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/BLK_MEM_GEN_V2_7_xst.v new file mode 100644 index 0000000..c7797eb --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/BLK_MEM_GEN_V2_7_xst.v @@ -0,0 +1,209 @@ +/****************************************************************************** + * + * Block Memory Generator Core - Block Memory Behavioral Model + * + * Copyright(C) 2005 by Xilinx, Inc. All rights reserved. + * This text/file contains proprietary, confidential + * information of Xilinx, Inc., is distributed under + * license from Xilinx, Inc., and may be used, copied + * and/or disclosed only pursuant to the terms of a valid + * license agreement with Xilinx, Inc. Xilinx hereby + * grants you a license to use this text/file solely for + * design, simulation, implementation and creation of + * design files limited to Xilinx devices or technologies. + * Use with non-Xilinx devices or technologies is expressly + * prohibited and immediately terminates your license unless + * covered by a separate agreement. + * + * Xilinx is providing this design, code, or information + * "as-is" solely for use in developing programs and + * solutions for Xilinx devices, with no obligation on the + * part of Xilinx to provide support. By providing this design, + * code, or information as one possible implementation of + * this feature, application or standard, Xilinx is making no + * representation that this implementation is free from any + * claims of infringement. You are responsible for obtaining + * any rights you may require for your implementation. + * Xilinx expressly disclaims any warranty whatsoever with + * respect to the adequacy of the implementation, including + * but not limited to any warranties or representations that this + * implementation is free from claims of infringement, implied + * warranties of merchantability or fitness for a particular + * purpose. + * + * Xilinx products are not intended for use in life support + * appliances, devices, or systems. Use in such applications is + * expressly prohibited. + * + * Any modifications that are made to the Source Code are + * done at the user's sole risk and will be unsupported. + * The Xilinx Support Hotline does not have access to source + * code and therefore cannot answer specific questions related + * to source HDL. The Xilinx Hotline support of original source + * code IP shall only address issues and questions related + * to the standard Netlist version of the core (and thus + * indirectly, the original core source). + * + * This copyright and support notice must be retained as part + * of this text at all times. (c) Copyright 1995-2005 Xilinx, Inc. + * All rights reserved. + * + ***************************************************************************** + * + * Filename: BLK_MEM_GEN_V2_7.v + * + * Description: + * This file is the Verilog behvarial model for the + * Block Memory Generator Core. + * + ***************************************************************************** + * Author: Xilinx + * + * History: September 6, 2005 Initial revision + *****************************************************************************/ +`timescale 1ps/1ps + +module BLK_MEM_GEN_V2_7_xst + #(parameter C_ADDRA_WIDTH = 5, + parameter C_ADDRB_WIDTH = 5, + parameter C_ALGORITHM = 1, + parameter C_BYTE_SIZE = 9, + parameter C_COMMON_CLK = 1, + parameter C_DEFAULT_DATA = "0", + parameter C_DISABLE_WARN_BHV_COLL = 0, + parameter C_DISABLE_WARN_BHV_RANGE = 0, + parameter C_FAMILY = "virtex5", + parameter C_HAS_ENA = 1, + parameter C_HAS_ENB = 1, + parameter C_HAS_MEM_OUTPUT_REGS_A = 0, + parameter C_HAS_MEM_OUTPUT_REGS_B = 0, + parameter C_HAS_MUX_OUTPUT_REGS_A = 0, + parameter C_HAS_MUX_OUTPUT_REGS_B = 0, + parameter C_MUX_PIPELINE_STAGES = 0, + parameter C_HAS_REGCEA = 0, + parameter C_HAS_REGCEB = 0, + parameter C_HAS_SSRA = 0, + parameter C_HAS_SSRB = 0, + parameter C_INIT_FILE_NAME = "", + parameter C_LOAD_INIT_FILE = 0, + parameter C_MEM_TYPE = 2, + parameter C_PRIM_TYPE = 3, + parameter C_READ_DEPTH_A = 64, + parameter C_READ_DEPTH_B = 64, + parameter C_READ_WIDTH_A = 32, + parameter C_READ_WIDTH_B = 32, + parameter C_SIM_COLLISION_CHECK = "NONE", + parameter C_SINITA_VAL = "0", + parameter C_SINITB_VAL = "0", + parameter C_USE_BYTE_WEA = 0, + parameter C_USE_BYTE_WEB = 0, + parameter C_USE_DEFAULT_DATA = 0, + parameter C_USE_ECC = 0, + parameter C_USE_RAMB16BWER_RST_BHV = 0, + parameter C_WEA_WIDTH = 1, + parameter C_WEB_WIDTH = 1, + parameter C_WRITE_DEPTH_A = 64, + parameter C_WRITE_DEPTH_B = 64, + parameter C_WRITE_MODE_A = "WRITE_FIRST", + parameter C_WRITE_MODE_B = "WRITE_FIRST", + parameter C_WRITE_WIDTH_A = 32, + parameter C_WRITE_WIDTH_B = 32, + parameter C_XDEVICEFAMILY = "virtex5", + parameter C_ELABORATION_DIR = "" +) + (input CLKA, + input [C_WRITE_WIDTH_A-1:0] DINA, + input [C_ADDRA_WIDTH-1:0] ADDRA, + input ENA, + input REGCEA, + input [C_WEA_WIDTH-1:0] WEA, + input SSRA, + output [C_READ_WIDTH_A-1:0] DOUTA, + input CLKB, + input [C_WRITE_WIDTH_B-1:0] DINB, + input [C_ADDRB_WIDTH-1:0] ADDRB, + input ENB, + input REGCEB, + input [C_WEB_WIDTH-1:0] WEB, + input SSRB, + output [C_READ_WIDTH_B-1:0] DOUTB, + output DBITERR, + output SBITERR); + + +// Note: C_ELABORATION_DIR parameter is only used in synthesis +// (and doesn't get mentioned in the instantiation template Coregen generates). +// This wrapper file has to work both in simulation and synthesis. So, this +// parameter exists. It is not used by the behavioral model +// (BLK_MEM_GEN_V2_7.vhd) + + BLK_MEM_GEN_V2_7 + #( + .C_ADDRA_WIDTH (C_ADDRA_WIDTH), + .C_ADDRB_WIDTH (C_ADDRB_WIDTH), + .C_ALGORITHM (C_ALGORITHM), + .C_BYTE_SIZE (C_BYTE_SIZE), + .C_COMMON_CLK (C_COMMON_CLK), + .C_DEFAULT_DATA (C_DEFAULT_DATA), + .C_DISABLE_WARN_BHV_COLL (C_DISABLE_WARN_BHV_COLL), + .C_DISABLE_WARN_BHV_RANGE (C_DISABLE_WARN_BHV_RANGE), + .C_FAMILY (C_FAMILY), + .C_HAS_ENA (C_HAS_ENA), + .C_HAS_ENB (C_HAS_ENB), + .C_HAS_MEM_OUTPUT_REGS_A (C_HAS_MEM_OUTPUT_REGS_A), + .C_HAS_MEM_OUTPUT_REGS_B (C_HAS_MEM_OUTPUT_REGS_B), + .C_HAS_MUX_OUTPUT_REGS_A (C_HAS_MUX_OUTPUT_REGS_A), + .C_HAS_MUX_OUTPUT_REGS_B (C_HAS_MUX_OUTPUT_REGS_B), + .C_MUX_PIPELINE_STAGES (C_MUX_PIPELINE_STAGES), + .C_HAS_REGCEA (C_HAS_REGCEA), + .C_HAS_REGCEB (C_HAS_REGCEB), + .C_HAS_SSRA (C_HAS_SSRA), + .C_HAS_SSRB (C_HAS_SSRB), + .C_INIT_FILE_NAME (C_INIT_FILE_NAME), + .C_LOAD_INIT_FILE (C_LOAD_INIT_FILE), + .C_MEM_TYPE (C_MEM_TYPE), + .C_PRIM_TYPE (C_PRIM_TYPE), + .C_READ_DEPTH_A (C_READ_DEPTH_A), + .C_READ_DEPTH_B (C_READ_DEPTH_B), + .C_READ_WIDTH_A (C_READ_WIDTH_A), + .C_READ_WIDTH_B (C_READ_WIDTH_B), + .C_SIM_COLLISION_CHECK (C_SIM_COLLISION_CHECK), + .C_SINITA_VAL (C_SINITA_VAL), + .C_SINITB_VAL (C_SINITB_VAL), + .C_USE_BYTE_WEA (C_USE_BYTE_WEA), + .C_USE_BYTE_WEB (C_USE_BYTE_WEB), + .C_USE_DEFAULT_DATA (C_USE_DEFAULT_DATA), + .C_USE_ECC (C_USE_ECC), + .C_USE_RAMB16BWER_RST_BHV (C_USE_RAMB16BWER_RST_BHV), + .C_WEA_WIDTH (C_WEA_WIDTH), + .C_WEB_WIDTH (C_WEB_WIDTH), + .C_WRITE_DEPTH_A (C_WRITE_DEPTH_A), + .C_WRITE_DEPTH_B (C_WRITE_DEPTH_B), + .C_WRITE_MODE_A (C_WRITE_MODE_A), + .C_WRITE_MODE_B (C_WRITE_MODE_B), + .C_WRITE_WIDTH_A (C_WRITE_WIDTH_A), + .C_WRITE_WIDTH_B (C_WRITE_WIDTH_B), + .C_XDEVICEFAMILY (C_XDEVICEFAMILY) + ) blk_mem_gen_v2_7_dut ( + .DINA (DINA), + .DINB (DINB), + .ADDRA (ADDRA), + .ADDRB (ADDRB), + .ENA (ENA), + .ENB (ENB), + .REGCEA (REGCEA), + .REGCEB (REGCEB), + .WEA (WEA), + .WEB (WEB), + .SSRA (SSRA), + .SSRB (SSRB), + .CLKA (CLKA), + .CLKB (CLKB), + .DOUTA (DOUTA), + .DOUTB (DOUTB), + .DBITERR (DBITERR), + .SBITERR (SBITERR) +); + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/BLK_MEM_GEN_V3_1.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/BLK_MEM_GEN_V3_1.v new file mode 100644 index 0000000..9fe8b7f --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/BLK_MEM_GEN_V3_1.v @@ -0,0 +1,1741 @@ +/****************************************************************************** +-- (c) Copyright 2006 - 2009 Xilinx, Inc. All rights reserved. +-- +-- This file contains confidential and proprietary information +-- of Xilinx, Inc. and is protected under U.S. and +-- international copyright and other intellectual property +-- laws. +-- +-- DISCLAIMER +-- This disclaimer is not a license and does not grant any +-- rights to the materials distributed herewith. Except as +-- otherwise provided in a valid license issued to you by +-- Xilinx, and to the maximum extent permitted by applicable +-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +-- (2) Xilinx shall not be liable (whether in contract or tort, +-- including negligence, or under any other theory of +-- liability) for any loss or damage of any kind or nature +-- related to, arising under or in connection with these +-- materials, including for any direct, or any indirect, +-- special, incidental, or consequential loss or damage +-- (including loss of data, profits, goodwill, or any type of +-- loss or damage suffered as a result of any action brought +-- by a third party) even if such damage or loss was +-- reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail- +-- safe, or for use in any application requiring fail-safe +-- performance, such as life-support or safety devices or +-- systems, Class III medical devices, nuclear facilities, +-- applications related to the deployment of airbags, or any +-- other applications that could lead to death, personal +-- injury, or severe property or environmental damage +-- (individually and collectively, "Critical +-- Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical +-- Applications, subject only to applicable laws and +-- regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +-- PART OF THIS FILE AT ALL TIMES. +-- + ***************************************************************************** + * + * Filename: BLK_MEM_GEN_V3_1.v + * + * Description: + * This file is the Verilog behvarial model for the + * Block Memory Generator Core. + * + ***************************************************************************** + * Author: Xilinx + * + * History: Jan 11, 2006 Initial revision + * Jun 11, 2007 Added independent register stages for + * Port A and Port B (IP1_Jm/v2.5) + * Aug 28, 2007 Added mux pipeline stages feature (IP2_Jm/v2.6) + * Mar 13, 2008 Behavioral model optimizations + * April 07, 2009 : Added support for Spartan-6 and Virtex-6 + * features, including the following: + * (i) error injection, detection and/or correction + * (ii) reset priority + * (iii) special reset behavior + * + *****************************************************************************/ +`timescale 1ps/1ps + +//***************************************************************************** +// Output Register Stage module +// +// This module builds the output register stages of the memory. This module is +// instantiated in the main memory module (BLK_MEM_GEN_V3_1) which is +// declared/implemented further down in this file. +//***************************************************************************** + +module BLK_MEM_GEN_V3_1_output_stage + #(parameter C_FAMILY = "virtex5", + parameter C_XDEVICEFAMILY = "virtex5", + parameter C_RST_TYPE = "SYNC", + parameter C_HAS_RST = 0, + parameter C_RSTRAM = 0, + parameter C_RST_PRIORITY = "CE", + parameter C_INIT_VAL = "0", + parameter C_HAS_EN = 0, + parameter C_HAS_REGCE = 0, + parameter C_DATA_WIDTH = 32, + parameter C_ADDRB_WIDTH = 10, + parameter C_HAS_MEM_OUTPUT_REGS = 0, + parameter C_USE_ECC = 0, + parameter num_stages = 1, + parameter flop_delay = 100 + ) + ( + input CLK, + input RST, + input EN, + input REGCE, + input [C_DATA_WIDTH-1:0] DIN, + output reg [C_DATA_WIDTH-1:0] DOUT, + input SBITERR_IN, + input DBITERR_IN, + output reg SBITERR, + output reg DBITERR, + input [C_ADDRB_WIDTH-1:0] RDADDRECC_IN, + output reg [C_ADDRB_WIDTH-1:0] RDADDRECC +); + + localparam reg_stages = (num_stages == 0) ? 0 : num_stages-1; + // Declare the pipeline registers + // (includes mem output reg, mux pipeline stages, and mux output reg) + reg [C_DATA_WIDTH*reg_stages-1:0] out_regs; + reg [C_ADDRB_WIDTH*reg_stages-1:0] rdaddrecc_regs; + reg [reg_stages-1:0] sbiterr_regs; + reg [reg_stages-1:0] dbiterr_regs; + + reg [C_DATA_WIDTH*8-1:0] init_str = C_INIT_VAL; + reg [C_DATA_WIDTH-1:0] init_val; + + //********************************************* + // Wire off optional inputs based on parameters + //********************************************* + wire en_i; + wire regce_i; + wire rst_i; + + // Internal enable for output registers is tied to user EN or '1' depending + // on parameters + assign en_i = (C_HAS_EN==0 || EN); + + // Internal register enable for output registers is tied to user REGCE, EN or + // '1' depending on parameters + // For V4 ECC, REGCE is always 1 + // Virtex-4 ECC Not Yet Supported + assign regce_i = ((C_HAS_REGCE==1) && REGCE) || + ((C_HAS_REGCE==0) && (C_HAS_EN==0 || EN)); + + //Internal SRR is tied to user RST or '0' depending on parameters + assign rst_i = (C_HAS_RST==1) && RST; + + //**************************************************** + // Power on: load up the output registers and latches + //**************************************************** + initial begin + if (!($sscanf(init_str, "%h", init_val))) begin + init_val = 0; + end + DOUT = init_val; + RDADDRECC = 0; + SBITERR = 1'b0; + DBITERR = 1'b0; + // This will be one wider than need, but 0 is an error + out_regs = {(reg_stages+1){init_val}}; + rdaddrecc_regs = 0; + sbiterr_regs = {(reg_stages+1){1'b0}}; + dbiterr_regs = {(reg_stages+1){1'b0}}; + end + + //*********************************************** + // num_stages = 0 (No output registers. RAM only) + //*********************************************** + generate if (num_stages == 0) begin : zero_stages + always @* begin + DOUT = DIN; + RDADDRECC = RDADDRECC_IN; + SBITERR = SBITERR_IN; + DBITERR = DBITERR_IN; + end + end + endgenerate + + //*********************************************** + // num_stages = 1 + // (Mem Output Reg only or Mux Output Reg only) + //*********************************************** + + // Possible valid combinations: + // Note: C_HAS_MUX_OUTPUT_REGS_*=0 when (C_RSTRAM_*=1) + // +-----------------------------------------+ + // | C_RSTRAM_* | Reset Behavior | + // +----------------+------------------------+ + // | 0 | Normal Behavior | + // +----------------+------------------------+ + // | 1 | Special Behavior | + // +----------------+------------------------+ + // + // Normal = REGCE gates reset, as in the case of all families except S3ADSP. + // Special = EN gates reset, as in the case of S3ADSP. + + generate if (num_stages == 1 && + (C_RSTRAM == 0 || (C_RSTRAM == 1 && C_XDEVICEFAMILY != "spartan3adsp") || + C_HAS_MEM_OUTPUT_REGS == 0 || C_HAS_RST == 0)) + begin : one_stages_norm + //Asynchronous Reset + if (C_FAMILY == "spartan6" && C_RST_TYPE == "ASYNC") begin + if(C_RST_PRIORITY == "CE") begin //REGCE has priority + always @ (*) begin + if (rst_i && regce_i) DOUT <= #flop_delay init_val; + end + always @ (posedge CLK) begin + if (!rst_i && regce_i) DOUT <= #flop_delay DIN; + end //CLK + end else begin //RST has priority + always @ (*) begin + if (rst_i) DOUT <= #flop_delay init_val; + end + always @ (posedge CLK) begin + if (!rst_i && regce_i) DOUT <= #flop_delay DIN; + end //CLK + end //end Priority conditions + //Synchronous Reset + end else begin + always @(posedge CLK) begin + if (C_RST_PRIORITY == "CE") begin //REGCE has priority + if (regce_i && rst_i) begin + DOUT <= #flop_delay init_val; + RDADDRECC <= #flop_delay 0; + SBITERR <= #flop_delay 1'b0; + DBITERR <= #flop_delay 1'b0; + end else if (regce_i) begin + DOUT <= #flop_delay DIN; + RDADDRECC <= #flop_delay RDADDRECC_IN; + SBITERR <= #flop_delay SBITERR_IN; + DBITERR <= #flop_delay DBITERR_IN; + end //Output signal assignments + end else begin //RST has priority + if (rst_i) begin + DOUT <= #flop_delay init_val; + RDADDRECC <= #flop_delay RDADDRECC_IN; + SBITERR <= #flop_delay 1'b0; + DBITERR <= #flop_delay 1'b0; + end else if (regce_i) begin + DOUT <= #flop_delay DIN; + RDADDRECC <= #flop_delay RDADDRECC_IN; + SBITERR <= #flop_delay SBITERR_IN; + DBITERR <= #flop_delay DBITERR_IN; + end //Output signal assignments + end //end Priority conditions + end //CLK + end //end RST Type conditions + end //end one_stages_norm generate statement + endgenerate + + // Special Reset Behavior for S3ADSP + generate if (num_stages == 1 && C_RSTRAM == 1 && C_XDEVICEFAMILY =="spartan3adsp") + begin : one_stage_splbhv + always @(posedge CLK) begin + if (en_i && rst_i) begin + DOUT <= #flop_delay init_val; + end else if (regce_i && !rst_i) begin + DOUT <= #flop_delay DIN; + end //Output signal assignments + end //end CLK + end //end one_stage_splbhv generate statement + endgenerate + + //************************************************************ + // num_stages > 1 + // Mem Output Reg + Mux Output Reg + // or + // Mem Output Reg + Mux Pipeline Stages (>0) + Mux Output Reg + // or + // Mux Pipeline Stages (>0) + Mux Output Reg + //************************************************************* + generate if (num_stages > 1) begin : multi_stage + //Asynchronous Reset + if (C_FAMILY == "spartan6" && C_RST_TYPE == "ASYNC") begin + if(C_RST_PRIORITY == "CE") begin //REGCE has priority + always @ (*) begin + if (rst_i && regce_i) DOUT <= #flop_delay init_val; + end + always @ (posedge CLK) begin + if (!rst_i && regce_i) + DOUT <= #flop_delay out_regs[C_DATA_WIDTH*(num_stages-2)+:C_DATA_WIDTH]; + end //CLK + end else begin //RST has priority + always @ (*) begin + if (rst_i) DOUT <= #flop_delay init_val; + end + always @ (posedge CLK) begin + if (!rst_i && regce_i) + DOUT <= #flop_delay out_regs[C_DATA_WIDTH*(num_stages-2)+:C_DATA_WIDTH]; + end //CLK + end //end Priority conditions + always @ (posedge CLK) begin + if (en_i) begin + out_regs <= #flop_delay (out_regs << C_DATA_WIDTH) | DIN; + end + end + //Synchronous Reset + end else begin + always @(posedge CLK) begin + if (C_RST_PRIORITY == "CE") begin //REGCE has priority + if (regce_i && rst_i) begin + DOUT <= #flop_delay init_val; + RDADDRECC <= #flop_delay 0; + SBITERR <= #flop_delay 1'b0; + DBITERR <= #flop_delay 1'b0; + end else if (regce_i) begin + DOUT <= #flop_delay + out_regs[C_DATA_WIDTH*(num_stages-2)+:C_DATA_WIDTH]; + RDADDRECC <= #flop_delay rdaddrecc_regs[C_ADDRB_WIDTH*(num_stages-2)+:C_ADDRB_WIDTH]; + SBITERR <= #flop_delay sbiterr_regs[num_stages-2]; + DBITERR <= #flop_delay dbiterr_regs[num_stages-2]; + end //Output signal assignments + end else begin //RST has priority + if (rst_i) begin + DOUT <= #flop_delay init_val; + RDADDRECC <= #flop_delay 0; + SBITERR <= #flop_delay 1'b0; + DBITERR <= #flop_delay 1'b0; + end else if (regce_i) begin + DOUT <= #flop_delay + out_regs[C_DATA_WIDTH*(num_stages-2)+:C_DATA_WIDTH]; + RDADDRECC <= #flop_delay rdaddrecc_regs[C_ADDRB_WIDTH*(num_stages-2)+:C_ADDRB_WIDTH]; + SBITERR <= #flop_delay sbiterr_regs[num_stages-2]; + DBITERR <= #flop_delay dbiterr_regs[num_stages-2]; + end //Output signal assignments + end //end Priority conditions + // Shift the data through the output stages + if (en_i) begin + out_regs <= #flop_delay (out_regs << C_DATA_WIDTH) | DIN; + rdaddrecc_regs <= #flop_delay (rdaddrecc_regs << C_ADDRB_WIDTH) | RDADDRECC_IN; + sbiterr_regs <= #flop_delay (sbiterr_regs << 1) | SBITERR_IN; + dbiterr_regs <= #flop_delay (dbiterr_regs << 1) | DBITERR_IN; + end + end //end CLK + end //end RST Type conditions + end //end multi_stage generate statement + endgenerate +endmodule + + +//***************************************************************************** +// Main Memory module +// +// This module is the top-level behavioral model and this implements the RAM +//***************************************************************************** +module BLK_MEM_GEN_V3_1 + #(parameter C_CORENAME = "blk_mem_gen_v3_1", + parameter C_FAMILY = "virtex6", + parameter C_XDEVICEFAMILY = "virtex6", + parameter C_MEM_TYPE = 2, + parameter C_BYTE_SIZE = 9, + parameter C_ALGORITHM = 1, + parameter C_PRIM_TYPE = 3, + parameter C_LOAD_INIT_FILE = 0, + parameter C_INIT_FILE_NAME = "", + parameter C_USE_DEFAULT_DATA = 0, + parameter C_DEFAULT_DATA = "0", + parameter C_RST_TYPE = "SYNC", + parameter C_HAS_RSTA = 0, + parameter C_RST_PRIORITY_A = "CE", + parameter C_RSTRAM_A = 0, + parameter C_INITA_VAL = "0", + parameter C_HAS_ENA = 1, + parameter C_HAS_REGCEA = 0, + parameter C_USE_BYTE_WEA = 0, + parameter C_WEA_WIDTH = 1, + parameter C_WRITE_MODE_A = "WRITE_FIRST", + parameter C_WRITE_WIDTH_A = 32, + parameter C_READ_WIDTH_A = 32, + parameter C_WRITE_DEPTH_A = 64, + parameter C_READ_DEPTH_A = 64, + parameter C_ADDRA_WIDTH = 5, + parameter C_HAS_RSTB = 0, + parameter C_RST_PRIORITY_B = "CE", + parameter C_RSTRAM_B = 0, + parameter C_INITB_VAL = "0", + parameter C_HAS_ENB = 1, + parameter C_HAS_REGCEB = 0, + parameter C_USE_BYTE_WEB = 0, + parameter C_WEB_WIDTH = 1, + parameter C_WRITE_MODE_B = "WRITE_FIRST", + parameter C_WRITE_WIDTH_B = 32, + parameter C_READ_WIDTH_B = 32, + parameter C_WRITE_DEPTH_B = 64, + parameter C_READ_DEPTH_B = 64, + parameter C_ADDRB_WIDTH = 5, + parameter C_HAS_MEM_OUTPUT_REGS_A = 0, + parameter C_HAS_MEM_OUTPUT_REGS_B = 0, + parameter C_HAS_MUX_OUTPUT_REGS_A = 0, + parameter C_HAS_MUX_OUTPUT_REGS_B = 0, + parameter C_MUX_PIPELINE_STAGES = 0, + parameter C_USE_ECC = 0, + parameter C_HAS_INJECTERR = 0, + parameter C_SIM_COLLISION_CHECK = "NONE", + parameter C_COMMON_CLK = 1, + parameter C_DISABLE_WARN_BHV_COLL = 0, + parameter C_DISABLE_WARN_BHV_RANGE = 0 + ) + (input CLKA, + input RSTA, + input ENA, + input REGCEA, + input [C_WEA_WIDTH-1:0] WEA, + input [C_ADDRA_WIDTH-1:0] ADDRA, + input [C_WRITE_WIDTH_A-1:0] DINA, + output [C_READ_WIDTH_A-1:0] DOUTA, + input CLKB, + input RSTB, + input ENB, + input REGCEB, + input [C_WEB_WIDTH-1:0] WEB, + input [C_ADDRB_WIDTH-1:0] ADDRB, + input [C_WRITE_WIDTH_B-1:0] DINB, + output [C_READ_WIDTH_B-1:0] DOUTB, + input INJECTSBITERR, + input INJECTDBITERR, + output SBITERR, + output DBITERR, + output [C_ADDRB_WIDTH-1:0] RDADDRECC + ); + +// Note: C_CORENAME parameter is hard-coded to "blk_mem_gen_v3_1" and it is +// only used by this module to print warning messages. It is neither passed +// down from blk_mem_gen_v3_1_xst.v nor present in the instantiation template +// coregen generates + + //*************************************************************************** + // constants for the core behavior + //*************************************************************************** + // file handles for logging + //-------------------------------------------------- + localparam addrfile = 32'h8000_0001; //stdout for addr out of range + localparam collfile = 32'h8000_0001; //stdout for coll detection + localparam errfile = 32'h8000_0001; //stdout for file I/O errors + + // other constants + //-------------------------------------------------- + localparam coll_delay = 2000; // 2 ns + + // locally derived parameters to determine memory shape + //----------------------------------------------------- + localparam min_width_a = (C_WRITE_WIDTH_A < C_READ_WIDTH_A) ? + C_WRITE_WIDTH_A : C_READ_WIDTH_A; + localparam min_width_b = (C_WRITE_WIDTH_B < C_READ_WIDTH_B) ? + C_WRITE_WIDTH_B : C_READ_WIDTH_B; + localparam min_width = (min_width_a < min_width_b) ? + min_width_a : min_width_b; + + localparam max_width_a = (C_WRITE_WIDTH_A > C_READ_WIDTH_A) ? + C_WRITE_WIDTH_A : C_READ_WIDTH_A; + localparam max_width_b = (C_WRITE_WIDTH_B > C_READ_WIDTH_B) ? + C_WRITE_WIDTH_B : C_READ_WIDTH_B; + localparam max_width = (max_width_a > max_width_b) ? + max_width_a : max_width_b; + + localparam max_depth_a = (C_WRITE_DEPTH_A > C_READ_DEPTH_A) ? + C_WRITE_DEPTH_A : C_READ_DEPTH_A; + localparam max_depth_b = (C_WRITE_DEPTH_B > C_READ_DEPTH_B) ? + C_WRITE_DEPTH_B : C_READ_DEPTH_B; + localparam max_depth = (max_depth_a > max_depth_b) ? + max_depth_a : max_depth_b; + + + // locally derived parameters to assist memory access + //---------------------------------------------------- + // Calculate the width ratios of each port with respect to the narrowest + // port + localparam write_width_ratio_a = C_WRITE_WIDTH_A/min_width; + localparam read_width_ratio_a = C_READ_WIDTH_A/min_width; + localparam write_width_ratio_b = C_WRITE_WIDTH_B/min_width; + localparam read_width_ratio_b = C_READ_WIDTH_B/min_width; + + // To modify the LSBs of the 'wider' data to the actual + // address value + //---------------------------------------------------- + localparam write_addr_a_div = C_WRITE_WIDTH_A/min_width_a; + localparam read_addr_a_div = C_READ_WIDTH_A/min_width_a; + localparam write_addr_b_div = C_WRITE_WIDTH_B/min_width_b; + localparam read_addr_b_div = C_READ_WIDTH_B/min_width_b; + + // If byte writes aren't being used, make sure byte_size is not + // wider than the memory elements to avoid compilation warnings + localparam byte_size = (C_BYTE_SIZE < min_width) ? C_BYTE_SIZE : min_width; + + // The memory + reg [min_width-1:0] memory [0:max_depth-1]; + // ECC error arrays + reg sbiterr_arr [0:max_depth-1]; + reg dbiterr_arr [0:max_depth-1]; + + // Memory output 'latches' + reg [C_READ_WIDTH_A-1:0] memory_out_a; + reg [C_READ_WIDTH_B-1:0] memory_out_b; + + // ECC error inputs and outputs from output_stage module: + reg sbiterr_in; + wire sbiterr_sp; + wire sbiterr_sdp; + reg dbiterr_in; + wire dbiterr_sp; + wire dbiterr_sdp; + + reg [C_ADDRB_WIDTH-1:0] rdaddrecc_in; + wire [C_ADDRB_WIDTH-1:0] rdaddrecc_sp; + wire [C_ADDRB_WIDTH-1:0] rdaddrecc_sdp; + + // Reset values + reg [C_READ_WIDTH_A-1:0] inita_val; + reg [C_READ_WIDTH_B-1:0] initb_val; + + // Collision detect + reg is_collision; + reg is_collision_a, is_collision_delay_a; + reg is_collision_b, is_collision_delay_b; + + // Temporary variables for initialization + //--------------------------------------- + integer status; + reg [639:0] err_str; + integer initfile; + // data input buffer + reg [C_WRITE_WIDTH_A-1:0] mif_data; + // string values in hex + reg [C_READ_WIDTH_A*8-1:0] inita_str = C_INITA_VAL; + reg [C_READ_WIDTH_B*8-1:0] initb_str = C_INITB_VAL; + reg [C_WRITE_WIDTH_A*8-1:0] default_data_str = C_DEFAULT_DATA; + // initialization filename + reg [1023*8-1:0] init_file_str = C_INIT_FILE_NAME; + + + //Constants used to calculate the effective address widths for each of the + //four ports. + //width_waa =log2(write_addr_a_div); width_raa=log2(read_addr_a_div) + //width_wab =log2(write_addr_b_div); width_rab=log2(read_addr_b_div) + integer cnt = 1; + integer width_waa = 0; + integer width_raa = 0; + integer width_wab = 0; + integer width_rab = 0; + integer write_addr_a_width, read_addr_a_width; + integer write_addr_b_width, read_addr_b_width; + + + // Internal configuration parameters + //--------------------------------------------- + localparam flop_delay = 100; // 100 ps + localparam single_port = (C_MEM_TYPE==0 || C_MEM_TYPE==3); + localparam is_rom = (C_MEM_TYPE==3 || C_MEM_TYPE==4); + localparam has_a_write = (!is_rom); + localparam has_b_write = (C_MEM_TYPE==2); + localparam has_a_read = (C_MEM_TYPE!=1); + localparam has_b_read = (!single_port); + localparam has_b_port = (has_b_read || has_b_write); + + // Calculate the mux pipeline register stages for Port A and Port B + //------------------------------------------------------------------ + localparam mux_pipeline_stages_a = (C_HAS_MUX_OUTPUT_REGS_A) ? + C_MUX_PIPELINE_STAGES : 0; + localparam mux_pipeline_stages_b = (C_HAS_MUX_OUTPUT_REGS_B) ? + C_MUX_PIPELINE_STAGES : 0; + + // Calculate total number of register stages in the core + // ----------------------------------------------------- + localparam num_output_stages_a = (C_HAS_MEM_OUTPUT_REGS_A+mux_pipeline_stages_a+C_HAS_MUX_OUTPUT_REGS_A); + + localparam num_output_stages_b = (C_HAS_MEM_OUTPUT_REGS_B+mux_pipeline_stages_b+C_HAS_MUX_OUTPUT_REGS_B); + + wire ena_i; + wire enb_i; + wire reseta_i; + wire resetb_i; + wire [C_WEA_WIDTH-1:0] wea_i; + wire [C_WEB_WIDTH-1:0] web_i; + wire rea_i; + wire reb_i; + + // ECC SBITERR/DBITERR Outputs + // The ECC Behavior is modeled by the behavioral models only for Virtex-6. + // For Virtex-5, these outputs will be tied to 0. + assign SBITERR = (C_MEM_TYPE == 0 && C_USE_ECC == 1)?sbiterr_sp:((C_MEM_TYPE == 1 && C_USE_ECC == 1)?sbiterr_sdp:0); + assign DBITERR = (C_MEM_TYPE == 0 && C_USE_ECC == 1)?dbiterr_sp:((C_MEM_TYPE == 1 && C_USE_ECC == 1)?dbiterr_sdp:0); + assign RDADDRECC = (C_FAMILY == "virtex6")? + ((C_MEM_TYPE == 0 && C_USE_ECC == 1)?rdaddrecc_sp: + ((C_MEM_TYPE == 1 && C_USE_ECC == 1)?rdaddrecc_sdp:0)) : 0; + + + // This effectively wires off optional inputs + assign ena_i = (C_HAS_ENA==0) || ENA; + assign enb_i = ((C_HAS_ENB==0) || ENB) && has_b_port; + assign wea_i = (has_a_write && ena_i) ? WEA : 'b0; + assign web_i = (has_b_write && enb_i) ? WEB : 'b0; + assign rea_i = (has_a_read) ? ena_i : 'b0; + assign reb_i = (has_b_read) ? enb_i : 'b0; + + // These signals reset the memory latches + +// IR-495658: OLD Implementation, before v3.1 when reset priority did not exist +// assign reseta_i = +// ((C_HAS_RSTA==1 && RSTA && ena_i && num_output_stages_a==0) || +// (C_HAS_RSTA==1 && RSTA && ena_i && C_RSTRAM_A==1)); +// +// assign resetb_i = +// ((C_HAS_RSTB==1 && RSTB && enb_i && num_output_stages_b==0) || +// (C_HAS_RSTB==1 && RSTB && enb_i && C_RSTRAM_B==1)); + + assign reseta_i = + ((C_HAS_RSTA==1 && RSTA && num_output_stages_a==0) || + (C_HAS_RSTA==1 && RSTA && C_RSTRAM_A==1)); + + assign resetb_i = + ((C_HAS_RSTB==1 && RSTB && num_output_stages_b==0) || + (C_HAS_RSTB==1 && RSTB && C_RSTRAM_B==1)); + + // Tasks to access the memory + //--------------------------- + //************** + // write_a + //************** + task write_a + (input reg [C_ADDRA_WIDTH-1:0] addr, + input reg [C_WEA_WIDTH-1:0] byte_en, + input reg [C_WRITE_WIDTH_A-1:0] data, + input inj_sbiterr, + input inj_dbiterr); + reg [C_WRITE_WIDTH_A-1:0] current_contents; + reg [C_ADDRA_WIDTH-1:0] address; + integer i; + begin + // Shift the address by the ratio + address = (addr/write_addr_a_div); + if (address >= C_WRITE_DEPTH_A) begin + if (!C_DISABLE_WARN_BHV_RANGE) begin + $fdisplay(addrfile, + "%0s WARNING: Address %0h is outside range for A Write", + C_CORENAME, addr); + end + + // valid address + end else begin + + // Combine w/ byte writes + if (C_USE_BYTE_WEA) begin + + // Get the current memory contents + if (write_width_ratio_a == 1) begin + // Workaround for IUS 5.5 part-select issue + current_contents = memory[address]; + end else begin + for (i = 0; i < write_width_ratio_a; i = i + 1) begin + current_contents[min_width*i+:min_width] + = memory[address*write_width_ratio_a + i]; + end + end + + // Apply incoming bytes + if (C_WEA_WIDTH == 1) begin + // Workaround for IUS 5.5 part-select issue + if (byte_en[0]) begin + current_contents = data; + end + end else begin + for (i = 0; i < C_WEA_WIDTH; i = i + 1) begin + if (byte_en[i]) begin + current_contents[byte_size*i+:byte_size] + = data[byte_size*i+:byte_size]; + end + end + end + + // No byte-writes, overwrite the whole word + end else begin + current_contents = data; + end + + // Insert double bit errors: + if (C_USE_ECC == 1) begin + if ((C_HAS_INJECTERR == 2 || C_HAS_INJECTERR == 3) && inj_dbiterr == 1'b1) begin + current_contents[0] = !(current_contents[0]); + current_contents[1] = !(current_contents[1]); + end + end + + // Write data to memory + if (write_width_ratio_a == 1) begin + // Workaround for IUS 5.5 part-select issue + memory[address*write_width_ratio_a] = current_contents; + end else begin + for (i = 0; i < write_width_ratio_a; i = i + 1) begin + memory[address*write_width_ratio_a + i] + = current_contents[min_width*i+:min_width]; + end + end + + // Store the address at which error is injected: + if (C_FAMILY == "virtex6" && C_USE_ECC == 1) begin + if ((C_HAS_INJECTERR == 1 && inj_sbiterr == 1'b1) || + (C_HAS_INJECTERR == 3 && inj_sbiterr == 1'b1 && inj_dbiterr != 1'b1)) + begin + sbiterr_arr[addr] = 1; + end else begin + sbiterr_arr[addr] = 0; + end + + if ((C_HAS_INJECTERR == 2 || C_HAS_INJECTERR == 3) && inj_dbiterr == 1'b1) begin + dbiterr_arr[addr] = 1; + end else begin + dbiterr_arr[addr] = 0; + end + end + + end + end + endtask + + //************** + // write_b + //************** + task write_b + (input reg [C_ADDRB_WIDTH-1:0] addr, + input reg [C_WEB_WIDTH-1:0] byte_en, + input reg [C_WRITE_WIDTH_B-1:0] data); + reg [C_WRITE_WIDTH_B-1:0] current_contents; + reg [C_ADDRB_WIDTH-1:0] address; + integer i; + begin + // Shift the address by the ratio + address = (addr/write_addr_b_div); + if (address >= C_WRITE_DEPTH_B) begin + if (!C_DISABLE_WARN_BHV_RANGE) begin + $fdisplay(addrfile, + "%0s WARNING: Address %0h is outside range for B Write", + C_CORENAME, addr); + end + + // valid address + end else begin + + // Combine w/ byte writes + if (C_USE_BYTE_WEB) begin + + // Get the current memory contents + if (write_width_ratio_b == 1) begin + // Workaround for IUS 5.5 part-select issue + current_contents = memory[address]; + end else begin + for (i = 0; i < write_width_ratio_b; i = i + 1) begin + current_contents[min_width*i+:min_width] + = memory[address*write_width_ratio_b + i]; + end + end + + // Apply incoming bytes + if (C_WEB_WIDTH == 1) begin + // Workaround for IUS 5.5 part-select issue + if (byte_en[0]) begin + current_contents = data; + end + end else begin + for (i = 0; i < C_WEB_WIDTH; i = i + 1) begin + if (byte_en[i]) begin + current_contents[byte_size*i+:byte_size] + = data[byte_size*i+:byte_size]; + end + end + end + + // No byte-writes, overwrite the whole word + end else begin + current_contents = data; + end + + // Write data to memory + if (write_width_ratio_b == 1) begin + // Workaround for IUS 5.5 part-select issue + memory[address*write_width_ratio_b] = current_contents; + end else begin + for (i = 0; i < write_width_ratio_b; i = i + 1) begin + memory[address*write_width_ratio_b + i] + = current_contents[min_width*i+:min_width]; + end + end + end + end + endtask + + //************** + // read_a + //************** + task read_a + (input reg [C_ADDRA_WIDTH-1:0] addr, + input reg reset); + reg [C_ADDRA_WIDTH-1:0] address; + integer i; + begin + + if (reset) begin + memory_out_a <= #flop_delay inita_val; + sbiterr_in <= #flop_delay 1'b0; + dbiterr_in <= #flop_delay 1'b0; + rdaddrecc_in <= #flop_delay 0; + end else begin + // Shift the address by the ratio + address = (addr/read_addr_a_div); + if (address >= C_READ_DEPTH_A) begin + if (!C_DISABLE_WARN_BHV_RANGE) begin + $fdisplay(addrfile, + "%0s WARNING: Address %0h is outside range for A Read", + C_CORENAME, addr); + end + memory_out_a <= #flop_delay 'bX; + sbiterr_in <= 1'bX; + dbiterr_in <= 1'bX; + rdaddrecc_in <= #flop_delay 'bX; + // valid address + end else begin + if (read_width_ratio_a==1) begin + memory_out_a <= #flop_delay memory[address*read_width_ratio_a]; + end else begin + // Increment through the 'partial' words in the memory + for (i = 0; i < read_width_ratio_a; i = i + 1) begin + memory_out_a[min_width*i+:min_width] + <= #flop_delay memory[address*read_width_ratio_a + i]; + end + end //end read_width_ratio_a==1 loop + + if (C_FAMILY == "virtex6" && C_USE_ECC == 1) begin + rdaddrecc_in <= addr; + + if (sbiterr_arr[addr] == 1) begin + sbiterr_in <= 1'b1; + end else begin + sbiterr_in <= 1'b0; + end + + if (dbiterr_arr[addr] == 1) begin + dbiterr_in <= 1'b1; + end else begin + dbiterr_in <= 1'b0; + end + + end //end ECC loop + end //end valid address loop + end //end reset-data assignment loops + end + endtask + + //************** + // read_b + //************** + task read_b + (input reg [C_ADDRB_WIDTH-1:0] addr, + input reg reset); + reg [C_ADDRB_WIDTH-1:0] address; + integer i; + begin + + if (reset) begin + memory_out_b <= #flop_delay initb_val; + sbiterr_in <= #flop_delay 1'b0; + dbiterr_in <= #flop_delay 1'b0; + rdaddrecc_in <= #flop_delay 0; + end else begin + // Shift the address + address = (addr/read_addr_b_div); + if (address >= C_READ_DEPTH_B) begin + if (!C_DISABLE_WARN_BHV_RANGE) begin + $fdisplay(addrfile, + "%0s WARNING: Address %0h is outside range for B Read", + C_CORENAME, addr); + end + memory_out_b <= #flop_delay 'bX; + sbiterr_in <= 1'bX; + dbiterr_in <= 1'bX; + rdaddrecc_in <= #flop_delay 'bX; + // valid address + end else begin + if (read_width_ratio_b==1) begin + memory_out_b <= #flop_delay memory[address*read_width_ratio_b]; + end else begin + // Increment through the 'partial' words in the memory + for (i = 0; i < read_width_ratio_b; i = i + 1) begin + memory_out_b[min_width*i+:min_width] + <= #flop_delay memory[address*read_width_ratio_b + i]; + end + end + + if (C_FAMILY == "virtex6" && C_USE_ECC == 1) begin + rdaddrecc_in <= addr; + if (sbiterr_arr[addr] == 1) begin + sbiterr_in <= 1'b1; + end else begin + sbiterr_in <= 1'b0; + end + + if (dbiterr_arr[addr] == 1) begin + dbiterr_in <= 1'b1; + end else begin + dbiterr_in <= 1'b0; + end + end else begin + rdaddrecc_in <= 0; + dbiterr_in <= 1'b0; + sbiterr_in <= 1'b0; + end //end ECC Loop + + end //end Valid address loop + end //end reset-data assignment loops + end + endtask + + //************** + // reset_a + //************** + task reset_a (input reg reset); + begin + if (reset) memory_out_a <= #flop_delay inita_val; + end + endtask + + //************** + // reset_b + //************** + task reset_b (input reg reset); + begin + if (reset) memory_out_b <= #flop_delay initb_val; + end + endtask + + //************** + // init_memory + //************** + task init_memory; + integer i, addr_step; + integer status; + reg [C_WRITE_WIDTH_A-1:0] default_data; + begin + default_data = 0; + + //Display output message indicating that the behavioral model is being + //initialized + if (C_USE_DEFAULT_DATA || C_LOAD_INIT_FILE) $display(" Block Memory Generator CORE Generator module loading initial data..."); + + // Convert the default to hex + if (C_USE_DEFAULT_DATA) begin + if (default_data_str == "") begin + $fdisplay(errfile, "%0s ERROR: C_DEFAULT_DATA is empty!", C_CORENAME); + $finish; + end else begin + status = $sscanf(default_data_str, "%h", default_data); + if (status == 0) begin + $fdisplay(errfile, {"%0s ERROR: Unsuccessful hexadecimal read", + "from C_DEFAULT_DATA: %0s"}, + C_CORENAME, C_DEFAULT_DATA); + $finish; + end + end + end + + // Step by write_addr_a_div through the memory via the + // Port A write interface to hit every location once + addr_step = write_addr_a_div; + + // 'write' to every location with default (or 0) + for (i = 0; i < C_WRITE_DEPTH_A*addr_step; i = i + addr_step) begin + write_a(i, {C_WEA_WIDTH{1'b1}}, default_data, 1'b0, 1'b0); + end + + // Get specialized data from the MIF file + if (C_LOAD_INIT_FILE) begin + if (init_file_str == "") begin + $fdisplay(errfile, "%0s ERROR: C_INIT_FILE_NAME is empty!", + C_CORENAME); + $finish; + end else begin + initfile = $fopen(init_file_str, "r"); + if (initfile == 0) begin + $fdisplay(errfile, {"%0s, ERROR: Problem opening", + "C_INIT_FILE_NAME: %0s!"}, + C_CORENAME, init_file_str); + $finish; + end else begin + // loop through the mif file, loading in the data + for (i = 0; i < C_WRITE_DEPTH_A*addr_step; i = i + addr_step) begin + status = $fscanf(initfile, "%b", mif_data); + if (status > 0) begin + write_a(i, {C_WEA_WIDTH{1'b1}}, mif_data, 1'b0, 1'b0); + end + end + $fclose(initfile); + end //initfile + end //init_file_str + end //C_LOAD_INIT_FILE + + //Display output message indicating that the behavioral model is done + //initializing + if (C_USE_DEFAULT_DATA || C_LOAD_INIT_FILE) + $display(" Block Memory Generator data initialization complete."); + end + endtask + + //************** + // log2roundup + //************** + function integer log2roundup (input integer data_value); + integer width; + integer cnt; + begin + width = 0; + + if (data_value > 1) begin + for(cnt=1 ; cnt < data_value ; cnt = cnt * 2) begin + width = width + 1; + end //loop + end //if + + log2roundup = width; + + end //log2roundup + endfunction + + + //******************* + // collision_check + //******************* + function integer collision_check (input reg [C_ADDRA_WIDTH-1:0] addr_a, + input integer iswrite_a, + input reg [C_ADDRB_WIDTH-1:0] addr_b, + input integer iswrite_b); + reg c_aw_bw, c_aw_br, c_ar_bw; + integer scaled_addra_to_waddrb_width; + integer scaled_addrb_to_waddrb_width; + integer scaled_addra_to_waddra_width; + integer scaled_addrb_to_waddra_width; + integer scaled_addra_to_raddrb_width; + integer scaled_addrb_to_raddrb_width; + integer scaled_addra_to_raddra_width; + integer scaled_addrb_to_raddra_width; + + + + begin + + c_aw_bw = 0; + c_aw_br = 0; + c_ar_bw = 0; + + //If write_addr_b_width is smaller, scale both addresses to that width for + //comparing write_addr_a and write_addr_b; addr_a starts as C_ADDRA_WIDTH, + //scale it down to write_addr_b_width. addr_b starts as C_ADDRB_WIDTH, + //scale it down to write_addr_b_width. Once both are scaled to + //write_addr_b_width, compare. + scaled_addra_to_waddrb_width = ((addr_a)/ + 2**(C_ADDRA_WIDTH-write_addr_b_width)); + scaled_addrb_to_waddrb_width = ((addr_b)/ + 2**(C_ADDRB_WIDTH-write_addr_b_width)); + + //If write_addr_a_width is smaller, scale both addresses to that width for + //comparing write_addr_a and write_addr_b; addr_a starts as C_ADDRA_WIDTH, + //scale it down to write_addr_a_width. addr_b starts as C_ADDRB_WIDTH, + //scale it down to write_addr_a_width. Once both are scaled to + //write_addr_a_width, compare. + scaled_addra_to_waddra_width = ((addr_a)/ + 2**(C_ADDRA_WIDTH-write_addr_a_width)); + scaled_addrb_to_waddra_width = ((addr_b)/ + 2**(C_ADDRB_WIDTH-write_addr_a_width)); + + //If read_addr_b_width is smaller, scale both addresses to that width for + //comparing write_addr_a and read_addr_b; addr_a starts as C_ADDRA_WIDTH, + //scale it down to read_addr_b_width. addr_b starts as C_ADDRB_WIDTH, + //scale it down to read_addr_b_width. Once both are scaled to + //read_addr_b_width, compare. + scaled_addra_to_raddrb_width = ((addr_a)/ + 2**(C_ADDRA_WIDTH-read_addr_b_width)); + scaled_addrb_to_raddrb_width = ((addr_b)/ + 2**(C_ADDRB_WIDTH-read_addr_b_width)); + + //If read_addr_a_width is smaller, scale both addresses to that width for + //comparing read_addr_a and write_addr_b; addr_a starts as C_ADDRA_WIDTH, + //scale it down to read_addr_a_width. addr_b starts as C_ADDRB_WIDTH, + //scale it down to read_addr_a_width. Once both are scaled to + //read_addr_a_width, compare. + scaled_addra_to_raddra_width = ((addr_a)/ + 2**(C_ADDRA_WIDTH-read_addr_a_width)); + scaled_addrb_to_raddra_width = ((addr_b)/ + 2**(C_ADDRB_WIDTH-read_addr_a_width)); + + //Look for a write-write collision. In order for a write-write + //collision to exist, both ports must have a write transaction. + if (iswrite_a && iswrite_b) begin + if (write_addr_a_width > write_addr_b_width) begin + if (scaled_addra_to_waddrb_width == scaled_addrb_to_waddrb_width) begin + c_aw_bw = 1; + end else begin + c_aw_bw = 0; + end + end else begin + if (scaled_addrb_to_waddra_width == scaled_addra_to_waddra_width) begin + c_aw_bw = 1; + end else begin + c_aw_bw = 0; + end + end //width + end //iswrite_a and iswrite_b + + //If the B port is reading (which means it is enabled - so could be + //a TX_WRITE or TX_READ), then check for a write-read collision). + //This could happen whether or not a write-write collision exists due + //to asymmetric write/read ports. + if (iswrite_a) begin + if (write_addr_a_width > read_addr_b_width) begin + if (scaled_addra_to_raddrb_width == scaled_addrb_to_raddrb_width) begin + c_aw_br = 1; + end else begin + c_aw_br = 0; + end + end else begin + if (scaled_addrb_to_waddra_width == scaled_addra_to_waddra_width) begin + c_aw_br = 1; + end else begin + c_aw_br = 0; + end + end //width + end //iswrite_a + + //If the A port is reading (which means it is enabled - so could be + // a TX_WRITE or TX_READ), then check for a write-read collision). + //This could happen whether or not a write-write collision exists due + // to asymmetric write/read ports. + if (iswrite_b) begin + if (read_addr_a_width > write_addr_b_width) begin + if (scaled_addra_to_waddrb_width == scaled_addrb_to_waddrb_width) begin + c_ar_bw = 1; + end else begin + c_ar_bw = 0; + end + end else begin + if (scaled_addrb_to_raddra_width == scaled_addra_to_raddra_width) begin + c_ar_bw = 1; + end else begin + c_ar_bw = 0; + end + end //width + end //iswrite_b + + + + collision_check = c_aw_bw | c_aw_br | c_ar_bw; + + end + endfunction + + //******************************* + // power on values + //******************************* + initial begin + // Load up the memory + init_memory; + // Load up the output registers and latches + if ($sscanf(inita_str, "%h", inita_val)) begin + memory_out_a = inita_val; + end else begin + memory_out_a = 0; + end + if ($sscanf(initb_str, "%h", initb_val)) begin + memory_out_b = initb_val; + end else begin + memory_out_b = 0; + end + + sbiterr_in <= 1'b0; + dbiterr_in <= 1'b0; + rdaddrecc_in <= 0; + + // Determine the effective address widths for each of the 4 ports + write_addr_a_width = C_ADDRA_WIDTH - log2roundup(write_addr_a_div); + read_addr_a_width = C_ADDRA_WIDTH - log2roundup(read_addr_a_div); + write_addr_b_width = C_ADDRB_WIDTH - log2roundup(write_addr_b_div); + read_addr_b_width = C_ADDRB_WIDTH - log2roundup(read_addr_b_div); + + $display("Block Memory Generator CORE Generator module %m is using a behavioral model for simulation which will not precisely model memory collision behavior."); + + end + + //************************************************************************* + // Asynchronous reset of Port A and Port B are performed here + // Note that the asynchronous reset feature is only supported in Spartan6 + // devices + //************************************************************************* + generate if(C_FAMILY=="spartan6" && C_RST_TYPE=="ASYNC") begin : async_rst + if (C_RST_PRIORITY_A=="CE") begin + always @ (*) begin + if (rea_i) reset_a(reseta_i); + end + end + else begin + always @ (*) begin + reset_a(reseta_i); + end + end + + if (C_RST_PRIORITY_B=="CE") begin + always @ (*) begin + if (reb_i) reset_b(resetb_i); + end + end + else begin + always @ (*) begin + reset_b(resetb_i); + end + end + + end + endgenerate + + //*************************************************************************** + // These are the main blocks which schedule read and write operations + // Note that the reset priority feature at the latch stage is only supported + // for Spartan-6. For other families, the default priority at the latch stage + // is "CE" + //*************************************************************************** + // Synchronous clocks: schedule port operations with respect to + // both write operating modes + generate + if(C_COMMON_CLK && (C_WRITE_MODE_A == "WRITE_FIRST") && (C_WRITE_MODE_B == + "WRITE_FIRST")) begin : com_clk_sched_wf_wf + always @(posedge CLKA) begin + //Write A + if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR); + //Write B + if (web_i) write_b(ADDRB, web_i, DINB); + //Read A + if (C_FAMILY=="spartan6" && C_RST_PRIORITY_A=="SR") begin + if (reseta_i) reset_a(reseta_i); + else if (rea_i) read_a(ADDRA, reseta_i); + end else begin + if (rea_i) read_a(ADDRA, reseta_i); + end + //Read B + if (C_FAMILY=="spartan6" && C_RST_PRIORITY_B=="SR") begin + if (resetb_i) reset_b(resetb_i); + else if (reb_i) read_b(ADDRB, resetb_i); + end else begin + if (reb_i) read_b(ADDRB, resetb_i); + end + end + end + else + if(C_COMMON_CLK && (C_WRITE_MODE_A == "READ_FIRST") && (C_WRITE_MODE_B == + "WRITE_FIRST")) begin : com_clk_sched_rf_wf + always @(posedge CLKA) begin + //Write B + if (web_i) write_b(ADDRB, web_i, DINB); + //Read B + if (C_FAMILY=="spartan6" && C_RST_PRIORITY_B=="SR") begin + if (resetb_i) reset_b(resetb_i); + else if (reb_i) read_b(ADDRB, resetb_i); + end else begin + if (reb_i) read_b(ADDRB, resetb_i); + end + //Read A + if (C_FAMILY=="spartan6" && C_RST_PRIORITY_A=="SR") begin + if (reseta_i) reset_a(reseta_i); + else if (rea_i) read_a(ADDRA, reseta_i); + end else begin + if (rea_i) read_a(ADDRA, reseta_i); + end + //Write A + if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR); + end + end + else + if(C_COMMON_CLK && (C_WRITE_MODE_A == "WRITE_FIRST") && (C_WRITE_MODE_B == + "READ_FIRST")) begin : com_clk_sched_wf_rf + always @(posedge CLKA) begin + //Write A + if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR); + //Read A + if (C_FAMILY=="spartan6" && C_RST_PRIORITY_A=="SR") begin + if (reseta_i) reset_a(reseta_i); + else if (rea_i) read_a(ADDRA, reseta_i); + end else begin + if (rea_i) read_a(ADDRA, reseta_i); + end + //Read B + if (C_FAMILY=="spartan6" && C_RST_PRIORITY_B=="SR") begin + if (resetb_i) reset_b(resetb_i); + else if (reb_i) read_b(ADDRB, resetb_i); + end else begin + if (reb_i) read_b(ADDRB, resetb_i); + end + //Write B + if (web_i) write_b(ADDRB, web_i, DINB); + end + end + else + if(C_COMMON_CLK && (C_WRITE_MODE_A == "READ_FIRST") && (C_WRITE_MODE_B == + "READ_FIRST")) begin : com_clk_sched_rf_rf + always @(posedge CLKA) begin + //Read A + if (C_FAMILY=="spartan6" && C_RST_PRIORITY_A=="SR") begin + if (reseta_i) reset_a(reseta_i); + else if (rea_i) read_a(ADDRA, reseta_i); + end else begin + if (rea_i) read_a(ADDRA, reseta_i); + end + //Read B + if (C_FAMILY=="spartan6" && C_RST_PRIORITY_B=="SR") begin + if (resetb_i) reset_b(resetb_i); + else if (reb_i) read_b(ADDRB, resetb_i); + end else begin + if (reb_i) read_b(ADDRB, resetb_i); + end + //Write A + if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR); + //Write B + if (web_i) write_b(ADDRB, web_i, DINB); + end + end + else if(C_COMMON_CLK && (C_WRITE_MODE_A =="WRITE_FIRST") && (C_WRITE_MODE_B == + "NO_CHANGE")) begin : com_clk_sched_wf_nc + always @(posedge CLKA) begin + //Write A + if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR); + //Read A + if (C_FAMILY=="spartan6" && C_RST_PRIORITY_A=="SR") begin + if (reseta_i) reset_a(reseta_i); + else if (rea_i) read_a(ADDRA, reseta_i); + end else begin + if (rea_i) read_a(ADDRA, reseta_i); + end + //Read B + if (C_FAMILY=="spartan6" && C_RST_PRIORITY_B=="SR") begin + if (resetb_i) reset_b(resetb_i); + else if (reb_i && !web_i) read_b(ADDRB, resetb_i); + end else begin + if (reb_i && (!web_i || resetb_i)) read_b(ADDRB, resetb_i); + end + //Write B + if (web_i) write_b(ADDRB, web_i, DINB); + end + end + else if(C_COMMON_CLK && (C_WRITE_MODE_A =="READ_FIRST") && (C_WRITE_MODE_B == + "NO_CHANGE")) begin : com_clk_sched_rf_nc + always @(posedge CLKA) begin + //Read A + if (C_FAMILY=="spartan6" && C_RST_PRIORITY_A=="SR") begin + if (reseta_i) reset_a(reseta_i); + else if (rea_i) read_a(ADDRA, reseta_i); + end else begin + if (rea_i) read_a(ADDRA, reseta_i); + end + //Read B + if (C_FAMILY=="spartan6" && C_RST_PRIORITY_B=="SR") begin + if (resetb_i) reset_b(resetb_i); + else if (reb_i && !web_i) read_b(ADDRB, resetb_i); + end else begin + if (reb_i && (!web_i || resetb_i)) read_b(ADDRB, resetb_i); + end + //Write A + if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR); + //Write B + if (web_i) write_b(ADDRB, web_i, DINB); + end + end + else if(C_COMMON_CLK && (C_WRITE_MODE_A =="NO_CHANGE") && (C_WRITE_MODE_B == + "WRITE_FIRST")) begin : com_clk_sched_nc_wf + always @(posedge CLKA) begin + //Write A + if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR); + //Write B + if (web_i) write_b(ADDRB, web_i, DINB); + //Read A + if (C_FAMILY=="spartan6" && C_RST_PRIORITY_A=="SR") begin + if (reseta_i) reset_a(reseta_i); + else if (rea_i && !wea_i) read_a(ADDRA, reseta_i); + end else begin + if (rea_i && (!wea_i || reseta_i)) read_a(ADDRA, reseta_i); + end + //Read B + if (C_FAMILY=="spartan6" && C_RST_PRIORITY_B=="SR") begin + if (resetb_i) reset_b(resetb_i); + else if (reb_i) read_b(ADDRB, resetb_i); + end else begin + if (reb_i) read_b(ADDRB, resetb_i); + end + end + end + else if(C_COMMON_CLK && (C_WRITE_MODE_A =="NO_CHANGE") && (C_WRITE_MODE_B == + "READ_FIRST")) begin : com_clk_sched_nc_rf + always @(posedge CLKA) begin + //Read B + if (C_FAMILY=="spartan6" && C_RST_PRIORITY_B=="SR") begin + if (resetb_i) reset_b(resetb_i); + else if (reb_i) read_b(ADDRB, resetb_i); + end else begin + if (reb_i) read_b(ADDRB, resetb_i); + end + //Read A + if (C_FAMILY=="spartan6" && C_RST_PRIORITY_A=="SR") begin + if (reseta_i) reset_a(reseta_i); + else if (rea_i && !wea_i) read_a(ADDRA, reseta_i); + end else begin + if (rea_i && (!wea_i || reseta_i)) read_a(ADDRA, reseta_i); + end + //Write A + if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR); + //Write B + if (web_i) write_b(ADDRB, web_i, DINB); + end + end + else if(C_COMMON_CLK && (C_WRITE_MODE_A =="NO_CHANGE") && (C_WRITE_MODE_B == + "NO_CHANGE")) begin : com_clk_sched_nc_nc + always @(posedge CLKA) begin + //Write A + if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR); + //Write B + if (web_i) write_b(ADDRB, web_i, DINB); + //Read A + if (C_FAMILY=="spartan6" && C_RST_PRIORITY_A=="SR") begin + if (reseta_i) reset_a(reseta_i); + else if (rea_i && !wea_i) read_a(ADDRA, reseta_i); + end else begin + if (rea_i && (!wea_i || reseta_i)) read_a(ADDRA, reseta_i); + end + //Read B + if (C_FAMILY=="spartan6" && C_RST_PRIORITY_B=="SR") begin + if (resetb_i) reset_b(resetb_i); + else if (reb_i && !web_i) read_b(ADDRB, resetb_i); + end else begin + if (reb_i && (!web_i || resetb_i)) read_b(ADDRB, resetb_i); + end + end + end + else if(C_COMMON_CLK) begin: com_clk_sched_default + always @(posedge CLKA) begin + //Write A + if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR); + //Write B + if (web_i) write_b(ADDRB, web_i, DINB); + //Read A + if (C_FAMILY=="spartan6" && C_RST_PRIORITY_A=="SR") begin + if (reseta_i) reset_a(reseta_i); + else if (rea_i) read_a(ADDRA, reseta_i); + end else begin + if (rea_i) read_a(ADDRA, reseta_i); + end + //Read B + if (C_FAMILY=="spartan6" && C_RST_PRIORITY_B=="SR") begin + if (resetb_i) reset_b(resetb_i); + else if (reb_i) read_b(ADDRB, resetb_i); + end else begin + if (reb_i) read_b(ADDRB, resetb_i); + end + end + end + endgenerate + + // Asynchronous clocks: port operation is independent + + generate + if((!C_COMMON_CLK) && (C_WRITE_MODE_A == "WRITE_FIRST")) begin : async_clk_sched_clka_wf + always @(posedge CLKA) begin + //Write A + if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR); + //Read A + if (C_FAMILY=="spartan6" && C_RST_PRIORITY_A=="SR") begin + if (reseta_i) reset_a(reseta_i); + else if (rea_i) read_a(ADDRA, reseta_i); + end else begin + if (rea_i) read_a(ADDRA, reseta_i); + end + end + end + else if((!C_COMMON_CLK) && (C_WRITE_MODE_A == "READ_FIRST")) begin : async_clk_sched_clka_rf + always @(posedge CLKA) begin + //Read A + if (C_FAMILY=="spartan6" && C_RST_PRIORITY_A=="SR") begin + if (reseta_i) reset_a(reseta_i); + else if (rea_i) read_a(ADDRA, reseta_i); + end else begin + if (rea_i) read_a(ADDRA, reseta_i); + end + //Write A + if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR); + end + end + else if((!C_COMMON_CLK) && (C_WRITE_MODE_A == "NO_CHANGE")) begin : async_clk_sched_clka_nc + always @(posedge CLKA) begin + //Write A + if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR); + //Read A + if (C_FAMILY=="spartan6" && C_RST_PRIORITY_A=="SR") begin + if (reseta_i) reset_a(reseta_i); + else if (rea_i && !wea_i) read_a(ADDRA, reseta_i); + end else begin + if (rea_i && (!wea_i || reseta_i)) read_a(ADDRA, reseta_i); + end + end + end + endgenerate + + generate + if ((!C_COMMON_CLK) && (C_WRITE_MODE_B == "WRITE_FIRST")) begin: async_clk_sched_clkb_wf + always @(posedge CLKB) begin + //Write B + if (web_i) write_b(ADDRB, web_i, DINB); + //Read B + if (C_FAMILY=="spartan6" && C_RST_PRIORITY_B=="SR") begin + if (resetb_i) reset_b(resetb_i); + else if (reb_i) read_b(ADDRB, resetb_i); + end else begin + if (reb_i) read_b(ADDRB, resetb_i); + end + end + end + else if ((!C_COMMON_CLK) && (C_WRITE_MODE_B == "READ_FIRST")) begin: async_clk_sched_clkb_rf + always @(posedge CLKB) begin + //Read B + if (C_FAMILY=="spartan6" && C_RST_PRIORITY_B=="SR") begin + if (resetb_i) reset_b(resetb_i); + else if (reb_i) read_b(ADDRB, resetb_i); + end else begin + if (reb_i) read_b(ADDRB, resetb_i); + end + //Write B + if (web_i) write_b(ADDRB, web_i, DINB); + end + end + else if ((!C_COMMON_CLK) && (C_WRITE_MODE_B == "NO_CHANGE")) begin: async_clk_sched_clkb_nc + always @(posedge CLKB) begin + //Write B + if (web_i) write_b(ADDRB, web_i, DINB); + //Read B + if (C_FAMILY=="spartan6" && C_RST_PRIORITY_B=="SR") begin + if (resetb_i) reset_b(resetb_i); + else if (reb_i && !web_i) read_b(ADDRB, resetb_i); + end else begin + if (reb_i && (!web_i || resetb_i)) read_b(ADDRB, resetb_i); + end + end + end + endgenerate + + + //*************************************************************** + // Instantiate the variable depth output register stage module + //*************************************************************** + // Port A + BLK_MEM_GEN_V3_1_output_stage + #(.C_FAMILY (C_FAMILY), + .C_XDEVICEFAMILY (C_XDEVICEFAMILY), + .C_RST_TYPE (C_RST_TYPE), + .C_HAS_RST (C_HAS_RSTA), + .C_RSTRAM (C_RSTRAM_A), + .C_RST_PRIORITY (C_RST_PRIORITY_A), + .C_INIT_VAL (C_INITA_VAL), + .C_HAS_EN (C_HAS_ENA), + .C_HAS_REGCE (C_HAS_REGCEA), + .C_DATA_WIDTH (C_READ_WIDTH_A), + .C_ADDRB_WIDTH (C_ADDRB_WIDTH), + .C_HAS_MEM_OUTPUT_REGS (C_HAS_MEM_OUTPUT_REGS_A), + .C_USE_ECC (C_USE_ECC), + .num_stages (num_output_stages_a), + .flop_delay (flop_delay)) + reg_a + (.CLK (CLKA), + .RST (RSTA), + .EN (ENA), + .REGCE (REGCEA), + .DIN (memory_out_a), + .DOUT (DOUTA), + .SBITERR_IN (sbiterr_in), + .DBITERR_IN (dbiterr_in), + .SBITERR (sbiterr_sp), + .DBITERR (dbiterr_sp), + .RDADDRECC_IN (rdaddrecc_in), + .RDADDRECC (rdaddrecc_sp) + ); + + // Port B + BLK_MEM_GEN_V3_1_output_stage + #(.C_FAMILY (C_FAMILY), + .C_XDEVICEFAMILY (C_XDEVICEFAMILY), + .C_RST_TYPE (C_RST_TYPE), + .C_HAS_RST (C_HAS_RSTB), + .C_RSTRAM (C_RSTRAM_B), + .C_RST_PRIORITY (C_RST_PRIORITY_B), + .C_INIT_VAL (C_INITB_VAL), + .C_HAS_EN (C_HAS_ENB), + .C_HAS_REGCE (C_HAS_REGCEB), + .C_DATA_WIDTH (C_READ_WIDTH_B), + .C_ADDRB_WIDTH (C_ADDRB_WIDTH), + .C_HAS_MEM_OUTPUT_REGS (C_HAS_MEM_OUTPUT_REGS_B), + .C_USE_ECC (C_USE_ECC), + .num_stages (num_output_stages_b), + .flop_delay (flop_delay)) + reg_b + (.CLK (CLKB), + .RST (RSTB), + .EN (ENB), + .REGCE (REGCEB), + .DIN (memory_out_b), + .DOUT (DOUTB), + .SBITERR_IN (sbiterr_in), + .DBITERR_IN (dbiterr_in), + .SBITERR (sbiterr_sdp), + .DBITERR (dbiterr_sdp), + .RDADDRECC_IN (rdaddrecc_in), + .RDADDRECC (rdaddrecc_sdp) + ); + + //**************************************************** + // Synchronous collision checks + //**************************************************** + generate if (!C_DISABLE_WARN_BHV_COLL && C_COMMON_CLK) begin : sync_coll + always @(posedge CLKA) begin + // Possible collision if both are enabled and the addresses match + if (ena_i && enb_i) begin + if (wea_i || web_i) begin + is_collision = collision_check(ADDRA, wea_i, ADDRB, web_i); + end else begin + is_collision = 0; + end + end else begin + is_collision = 0; + end + + // If the write port is in READ_FIRST mode, there is no collision + if (C_WRITE_MODE_A=="READ_FIRST" && wea_i && !web_i) begin + is_collision = 0; + end + if (C_WRITE_MODE_B=="READ_FIRST" && web_i && !wea_i) begin + is_collision = 0; + end + + // Only flag if one of the accesses is a write + if (is_collision && (wea_i || web_i)) begin + $fwrite(collfile, "%0s collision detected at time: %0d, ", + C_CORENAME, $time); + $fwrite(collfile, "A %0s address: %0h, B %0s address: %0h\n", + wea_i ? "write" : "read", ADDRA, + web_i ? "write" : "read", ADDRB); + end + end + + //**************************************************** + // Asynchronous collision checks + //**************************************************** + end else if (!C_DISABLE_WARN_BHV_COLL && !C_COMMON_CLK) begin : async_coll + + // Delay A and B addresses in order to mimic setup/hold times + wire [C_ADDRA_WIDTH-1:0] #coll_delay addra_delay = ADDRA; + wire [0:0] #coll_delay wea_delay = wea_i; + wire #coll_delay ena_delay = ena_i; + wire [C_ADDRB_WIDTH-1:0] #coll_delay addrb_delay = ADDRB; + wire [0:0] #coll_delay web_delay = web_i; + wire #coll_delay enb_delay = enb_i; + + // Do the checks w/rt A + always @(posedge CLKA) begin + // Possible collision if both are enabled and the addresses match + if (ena_i && enb_i) begin + if (wea_i || web_i) begin + is_collision_a = collision_check(ADDRA, wea_i, ADDRB, web_i); + end else begin + is_collision_a = 0; + end + end else begin + is_collision_a = 0; + end + + if (ena_i && enb_delay) begin + if(wea_i || web_delay) begin + is_collision_delay_a = collision_check(ADDRA, wea_i, addrb_delay, + web_delay); + end else begin + is_collision_delay_a = 0; + end + end else begin + is_collision_delay_a = 0; + end + + + // Only flag if B access is a write + if (is_collision_a && web_i) begin + $fwrite(collfile, "%0s collision detected at time: %0d, ", + C_CORENAME, $time); + $fwrite(collfile, "A %0s address: %0h, B write address: %0h\n", + wea_i ? "write" : "read", ADDRA, ADDRB); + + end else if (is_collision_delay_a && web_delay) begin + $fwrite(collfile, "%0s collision detected at time: %0d, ", + C_CORENAME, $time); + $fwrite(collfile, "A %0s address: %0h, B write address: %0h\n", + wea_i ? "write" : "read", ADDRA, addrb_delay); + end + + end + + // Do the checks w/rt B + always @(posedge CLKB) begin + + // Possible collision if both are enabled and the addresses match + if (ena_i && enb_i) begin + if (wea_i || web_i) begin + is_collision_b = collision_check(ADDRA, wea_i, ADDRB, web_i); + end else begin + is_collision_b = 0; + end + end else begin + is_collision_b = 0; + end + + if (ena_delay && enb_i) begin + if (wea_delay || web_i) begin + is_collision_delay_b = collision_check(addra_delay, wea_delay, ADDRB, + web_i); + end else begin + is_collision_delay_b = 0; + end + end else begin + is_collision_delay_b = 0; + end + + + // Only flag if A access is a write + if (is_collision_b && wea_i) begin + $fwrite(collfile, "%0s collision detected at time: %0d, ", + C_CORENAME, $time); + $fwrite(collfile, "A write address: %0h, B %s address: %0h\n", + ADDRA, web_i ? "write" : "read", ADDRB); + + end else if (is_collision_delay_b && wea_delay) begin + $fwrite(collfile, "%0s collision detected at time: %0d, ", + C_CORENAME, $time); + $fwrite(collfile, "A write address: %0h, B %s address: %0h\n", + addra_delay, web_i ? "write" : "read", ADDRB); + end + + end + end + endgenerate + +endmodule diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/BLK_MEM_GEN_V3_1_xst.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/BLK_MEM_GEN_V3_1_xst.v new file mode 100644 index 0000000..91e093a --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/BLK_MEM_GEN_V3_1_xst.v @@ -0,0 +1,224 @@ +/****************************************************************************** +-- (c) Copyright 2006 - 2009 Xilinx, Inc. All rights reserved. +-- +-- This file contains confidential and proprietary information +-- of Xilinx, Inc. and is protected under U.S. and +-- international copyright and other intellectual property +-- laws. +-- +-- DISCLAIMER +-- This disclaimer is not a license and does not grant any +-- rights to the materials distributed herewith. Except as +-- otherwise provided in a valid license issued to you by +-- Xilinx, and to the maximum extent permitted by applicable +-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +-- (2) Xilinx shall not be liable (whether in contract or tort, +-- including negligence, or under any other theory of +-- liability) for any loss or damage of any kind or nature +-- related to, arising under or in connection with these +-- materials, including for any direct, or any indirect, +-- special, incidental, or consequential loss or damage +-- (including loss of data, profits, goodwill, or any type of +-- loss or damage suffered as a result of any action brought +-- by a third party) even if such damage or loss was +-- reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail- +-- safe, or for use in any application requiring fail-safe +-- performance, such as life-support or safety devices or +-- systems, Class III medical devices, nuclear facilities, +-- applications related to the deployment of airbags, or any +-- other applications that could lead to death, personal +-- injury, or severe property or environmental damage +-- (individually and collectively, "Critical +-- Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical +-- Applications, subject only to applicable laws and +-- regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +-- PART OF THIS FILE AT ALL TIMES. +-- + ***************************************************************************** + * + * Filename: BLK_MEM_GEN_V3_1.v + * + * Description: + * This file is the Verilog behvarial model for the + * Block Memory Generator Core. + * + ***************************************************************************** + * Author: Xilinx + * + * History: September 6, 2005 Initial revision + *****************************************************************************/ +`timescale 1ps/1ps + +module BLK_MEM_GEN_V3_1_xst + #(parameter C_FAMILY = "virtex5", + parameter C_XDEVICEFAMILY = "virtex5", + parameter C_ELABORATION_DIR = "", + parameter C_MEM_TYPE = 2, + parameter C_BYTE_SIZE = 9, + parameter C_ALGORITHM = 1, + parameter C_PRIM_TYPE = 3, + parameter C_LOAD_INIT_FILE = 0, + parameter C_INIT_FILE_NAME = "", + parameter C_USE_DEFAULT_DATA = 0, + parameter C_DEFAULT_DATA = "0", + parameter C_RST_TYPE = "SYNC", + parameter C_HAS_RSTA = 0, + parameter C_RST_PRIORITY_A = "CE", + parameter C_RSTRAM_A = 0, + parameter C_INITA_VAL = "0", + parameter C_HAS_ENA = 1, + parameter C_HAS_REGCEA = 0, + parameter C_USE_BYTE_WEA = 0, + parameter C_WEA_WIDTH = 1, + parameter C_WRITE_MODE_A = "WRITE_FIRST", + parameter C_WRITE_WIDTH_A = 32, + parameter C_READ_WIDTH_A = 32, + parameter C_WRITE_DEPTH_A = 64, + parameter C_READ_DEPTH_A = 64, + parameter C_ADDRA_WIDTH = 5, + parameter C_HAS_RSTB = 0, + parameter C_RST_PRIORITY_B = "CE", + parameter C_RSTRAM_B = 0, + parameter C_INITB_VAL = "0", + parameter C_HAS_ENB = 1, + parameter C_HAS_REGCEB = 0, + parameter C_USE_BYTE_WEB = 0, + parameter C_WEB_WIDTH = 1, + parameter C_WRITE_MODE_B = "WRITE_FIRST", + parameter C_WRITE_WIDTH_B = 32, + parameter C_READ_WIDTH_B = 32, + parameter C_WRITE_DEPTH_B = 64, + parameter C_READ_DEPTH_B = 64, + parameter C_ADDRB_WIDTH = 5, + parameter C_HAS_MEM_OUTPUT_REGS_A = 0, + parameter C_HAS_MEM_OUTPUT_REGS_B = 0, + parameter C_HAS_MUX_OUTPUT_REGS_A = 0, + parameter C_HAS_MUX_OUTPUT_REGS_B = 0, + parameter C_MUX_PIPELINE_STAGES = 0, + parameter C_USE_ECC = 0, + parameter C_HAS_INJECTERR = 0, + parameter C_SIM_COLLISION_CHECK = "NONE", + parameter C_COMMON_CLK = 1, + parameter C_DISABLE_WARN_BHV_COLL = 0, + parameter C_DISABLE_WARN_BHV_RANGE = 0 +) + (input CLKA, + input RSTA, + input ENA, + input REGCEA, + input [C_WEA_WIDTH-1:0] WEA, + input [C_ADDRA_WIDTH-1:0] ADDRA, + input [C_WRITE_WIDTH_A-1:0] DINA, + output [C_READ_WIDTH_A-1:0] DOUTA, + input CLKB, + input RSTB, + input ENB, + input REGCEB, + input [C_WEB_WIDTH-1:0] WEB, + input [C_ADDRB_WIDTH-1:0] ADDRB, + input [C_WRITE_WIDTH_B-1:0] DINB, + output [C_READ_WIDTH_B-1:0] DOUTB, + input INJECTSBITERR, + input INJECTDBITERR, + output SBITERR, + output DBITERR, + output [C_ADDRB_WIDTH-1:0] RDADDRECC +); + + +// Note: C_ELABORATION_DIR parameter is only used in synthesis +// (and doesn't get mentioned in the instantiation template Coregen generates). +// This wrapper file has to work both in simulation and synthesis. So, this +// parameter exists. It is not used by the behavioral model +// (BLK_MEM_GEN_V3_1.vhd) + + BLK_MEM_GEN_V3_1 + #( + .C_CORENAME ("blk_mem_gen_v3_1"), + .C_FAMILY (C_FAMILY), + .C_XDEVICEFAMILY (C_XDEVICEFAMILY), + .C_MEM_TYPE (C_MEM_TYPE), + .C_BYTE_SIZE (C_BYTE_SIZE), + .C_ALGORITHM (C_ALGORITHM), + .C_PRIM_TYPE (C_PRIM_TYPE), + .C_LOAD_INIT_FILE (C_LOAD_INIT_FILE), + .C_INIT_FILE_NAME (C_INIT_FILE_NAME), + .C_USE_DEFAULT_DATA (C_USE_DEFAULT_DATA), + .C_DEFAULT_DATA (C_DEFAULT_DATA), + .C_RST_TYPE (C_RST_TYPE), + .C_HAS_RSTA (C_HAS_RSTA), + .C_RST_PRIORITY_A (C_RST_PRIORITY_A), + .C_RSTRAM_A (C_RSTRAM_A), + .C_INITA_VAL (C_INITA_VAL), + .C_HAS_ENA (C_HAS_ENA), + .C_HAS_REGCEA (C_HAS_REGCEA), + .C_USE_BYTE_WEA (C_USE_BYTE_WEA), + .C_WEA_WIDTH (C_WEA_WIDTH), + .C_WRITE_MODE_A (C_WRITE_MODE_A), + .C_WRITE_WIDTH_A (C_WRITE_WIDTH_A), + .C_READ_WIDTH_A (C_READ_WIDTH_A), + .C_WRITE_DEPTH_A (C_WRITE_DEPTH_A), + .C_READ_DEPTH_A (C_READ_DEPTH_A), + .C_ADDRA_WIDTH (C_ADDRA_WIDTH), + .C_HAS_RSTB (C_HAS_RSTB), + .C_RST_PRIORITY_B (C_RST_PRIORITY_B), + .C_RSTRAM_B (C_RSTRAM_B), + .C_INITB_VAL (C_INITB_VAL), + .C_HAS_ENB (C_HAS_ENB), + .C_HAS_REGCEB (C_HAS_REGCEB), + .C_USE_BYTE_WEB (C_USE_BYTE_WEB), + .C_WEB_WIDTH (C_WEB_WIDTH), + .C_WRITE_MODE_B (C_WRITE_MODE_B), + .C_WRITE_WIDTH_B (C_WRITE_WIDTH_B), + .C_READ_WIDTH_B (C_READ_WIDTH_B), + .C_WRITE_DEPTH_B (C_WRITE_DEPTH_B), + .C_READ_DEPTH_B (C_READ_DEPTH_B), + .C_ADDRB_WIDTH (C_ADDRB_WIDTH), + .C_HAS_MEM_OUTPUT_REGS_A (C_HAS_MEM_OUTPUT_REGS_A), + .C_HAS_MEM_OUTPUT_REGS_B (C_HAS_MEM_OUTPUT_REGS_B), + .C_HAS_MUX_OUTPUT_REGS_A (C_HAS_MUX_OUTPUT_REGS_A), + .C_HAS_MUX_OUTPUT_REGS_B (C_HAS_MUX_OUTPUT_REGS_B), + .C_MUX_PIPELINE_STAGES (C_MUX_PIPELINE_STAGES), + .C_USE_ECC (C_USE_ECC), + .C_HAS_INJECTERR (C_HAS_INJECTERR), + .C_SIM_COLLISION_CHECK (C_SIM_COLLISION_CHECK), + .C_COMMON_CLK (C_COMMON_CLK), + .C_DISABLE_WARN_BHV_COLL (C_DISABLE_WARN_BHV_COLL), + .C_DISABLE_WARN_BHV_RANGE (C_DISABLE_WARN_BHV_RANGE) + ) blk_mem_gen_v3_1_dut ( + .CLKA (CLKA), + .RSTA (RSTA), + .ENA (ENA), + .REGCEA (REGCEA), + .WEA (WEA), + .ADDRA (ADDRA), + .DINA (DINA), + .DOUTA (DOUTA), + .CLKB (CLKB), + .RSTB (RSTB), + .ENB (ENB), + .REGCEB (REGCEB), + .WEB (WEB), + .ADDRB (ADDRB), + .DINB (DINB), + .DOUTB (DOUTB), + .INJECTSBITERR (INJECTSBITERR), + .INJECTDBITERR (INJECTDBITERR), + .SBITERR (SBITERR), + .DBITERR (DBITERR), + .RDADDRECC (RDADDRECC) +); + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/BLK_MEM_GEN_V3_2.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/BLK_MEM_GEN_V3_2.v new file mode 100644 index 0000000..2c8cee1 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/BLK_MEM_GEN_V3_2.v @@ -0,0 +1,1866 @@ +/****************************************************************************** +-- (c) Copyright 2006 - 2009 Xilinx, Inc. All rights reserved. +-- +-- This file contains confidential and proprietary information +-- of Xilinx, Inc. and is protected under U.S. and +-- international copyright and other intellectual property +-- laws. +-- +-- DISCLAIMER +-- This disclaimer is not a license and does not grant any +-- rights to the materials distributed herewith. Except as +-- otherwise provided in a valid license issued to you by +-- Xilinx, and to the maximum extent permitted by applicable +-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +-- (2) Xilinx shall not be liable (whether in contract or tort, +-- including negligence, or under any other theory of +-- liability) for any loss or damage of any kind or nature +-- related to, arising under or in connection with these +-- materials, including for any direct, or any indirect, +-- special, incidental, or consequential loss or damage +-- (including loss of data, profits, goodwill, or any type of +-- loss or damage suffered as a result of any action brought +-- by a third party) even if such damage or loss was +-- reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail- +-- safe, or for use in any application requiring fail-safe +-- performance, such as life-support or safety devices or +-- systems, Class III medical devices, nuclear facilities, +-- applications related to the deployment of airbags, or any +-- other applications that could lead to death, personal +-- injury, or severe property or environmental damage +-- (individually and collectively, "Critical +-- Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical +-- Applications, subject only to applicable laws and +-- regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +-- PART OF THIS FILE AT ALL TIMES. +-- + ***************************************************************************** + * + * Filename: BLK_MEM_GEN_V3_2.v + * + * Description: + * This file is the Verilog behvarial model for the + * Block Memory Generator Core. + * + ***************************************************************************** + * Author: Xilinx + * + * History: Jan 11, 2006 Initial revision + * Jun 11, 2007 Added independent register stages for + * Port A and Port B (IP1_Jm/v2.5) + * Aug 28, 2007 Added mux pipeline stages feature (IP2_Jm/v2.6) + * Mar 13, 2008 Behavioral model optimizations + * April 07, 2009 : Added support for Spartan-6 and Virtex-6 + * features, including the following: + * (i) error injection, detection and/or correction + * (ii) reset priority + * (iii) special reset behavior + * + *****************************************************************************/ +`timescale 1ps/1ps + +//***************************************************************************** +// Output Register Stage module +// +// This module builds the output register stages of the memory. This module is +// instantiated in the main memory module (BLK_MEM_GEN_V3_2) which is +// declared/implemented further down in this file. +//***************************************************************************** + +module BLK_MEM_GEN_V3_2_output_stage + #(parameter C_FAMILY = "virtex5", + parameter C_XDEVICEFAMILY = "virtex5", + parameter C_RST_TYPE = "SYNC", + parameter C_HAS_RST = 0, + parameter C_RSTRAM = 0, + parameter C_RST_PRIORITY = "CE", + parameter C_INIT_VAL = "0", + parameter C_HAS_EN = 0, + parameter C_HAS_REGCE = 0, + parameter C_DATA_WIDTH = 32, + parameter C_ADDRB_WIDTH = 10, + parameter C_HAS_MEM_OUTPUT_REGS = 0, + parameter C_USE_ECC = 0, + parameter NUM_STAGES = 1, + parameter FLOP_DELAY = 100 + ) + ( + input CLK, + input RST, + input EN, + input REGCE, + input [C_DATA_WIDTH-1:0] DIN, + output reg [C_DATA_WIDTH-1:0] DOUT, + input SBITERR_IN, + input DBITERR_IN, + output reg SBITERR, + output reg DBITERR, + input [C_ADDRB_WIDTH-1:0] RDADDRECC_IN, + output reg [C_ADDRB_WIDTH-1:0] RDADDRECC +); + +//****************************** +// Port and Generic Definitions +//****************************** + //------------------------------------------------------------------------- + // Generic Definitions + //------------------------------------------------------------------------- + // C_FAMILY,C_XDEVICEFAMILY: Designates architecture targeted. The following + // options are available - "spartan3", "spartan6", + // "virtex4", "virtex5" and "virtex6". + // C_RST_TYPE : Type of reset - Synchronous or Asynchronous + // C_HAS_RST : Determines the presence of the RST port + // C_RSTRAM : Determines if special reset behavior is used + // C_RST_PRIORITY : Determines the priority between CE and SR + // C_INIT_VAL : Initialization value + // C_HAS_EN : Determines the presence of the EN port + // C_HAS_REGCE : Determines the presence of the REGCE port + // C_DATA_WIDTH : Memory write/read width + // C_ADDRB_WIDTH : Width of the ADDRB input port + // C_HAS_MEM_OUTPUT_REGS : Designates the use of a register at the output + // of the RAM primitive + // C_USE_ECC : Determines if the ECC feature is used or + // not. Only applicable for V5 and V6 + // NUM_STAGES : Determines the number of output stages + // FLOP_DELAY : Constant delay for register assignments + //------------------------------------------------------------------------- + // Port Definitions + //------------------------------------------------------------------------- + // CLK : Clock to synchronize all read and write operations + // RST : Reset input to reset memory outputs to a user-defined + // reset state + // EN : Enable all read and write operations + // REGCE : Register Clock Enable to control each pipeline output + // register stages + // DIN : Data input to the Output stage. + // DOUT : Final Data output + // SBITERR_IN : SBITERR input signal to the Output stage. + // SBITERR : Final SBITERR Output signal. + // DBITERR_IN : DBITERR input signal to the Output stage. + // DBITERR : Final DBITERR Output signal. + // RDADDRECC_IN : RDADDRECC input signal to the Output stage. + // RDADDRECC : Final RDADDRECC Output signal. + //------------------------------------------------------------------------- + +// Fix for CR-509792 +// localparam REG_STAGES = (NUM_STAGES == 0) ? 0 : NUM_STAGES-1; + localparam REG_STAGES = (NUM_STAGES < 2) ? 1 : NUM_STAGES-1; + + // Declare the pipeline registers + // (includes mem output reg, mux pipeline stages, and mux output reg) + reg [C_DATA_WIDTH*REG_STAGES-1:0] out_regs; + reg [C_ADDRB_WIDTH*REG_STAGES-1:0] rdaddrecc_regs; + reg [REG_STAGES-1:0] sbiterr_regs; + reg [REG_STAGES-1:0] dbiterr_regs; + + reg [C_DATA_WIDTH*8-1:0] init_str = C_INIT_VAL; + reg [C_DATA_WIDTH-1:0] init_val; + + //********************************************* + // Wire off optional inputs based on parameters + //********************************************* + wire en_i; + wire regce_i; + wire rst_i; + + // Internal enable for output registers is tied to user EN or '1' depending + // on parameters + assign en_i = (C_HAS_EN==0 || EN); + + // Internal register enable for output registers is tied to user REGCE, EN or + // '1' depending on parameters + // For V4 ECC, REGCE is always 1 + // Virtex-4 ECC Not Yet Supported + assign regce_i = ((C_HAS_REGCE==1) && REGCE) || + ((C_HAS_REGCE==0) && (C_HAS_EN==0 || EN)); + + //Internal SRR is tied to user RST or '0' depending on parameters + assign rst_i = (C_HAS_RST==1) && RST; + + //**************************************************** + // Power on: load up the output registers and latches + //**************************************************** + initial begin + if (!($sscanf(init_str, "%h", init_val))) begin + init_val = 0; + end + DOUT = init_val; + RDADDRECC = 0; + SBITERR = 1'b0; + DBITERR = 1'b0; + // This will be one wider than need, but 0 is an error + out_regs = {(REG_STAGES+1){init_val}}; + rdaddrecc_regs = 0; + sbiterr_regs = {(REG_STAGES+1){1'b0}}; + dbiterr_regs = {(REG_STAGES+1){1'b0}}; + end + + //*********************************************** + // NUM_STAGES = 0 (No output registers. RAM only) + //*********************************************** + generate if (NUM_STAGES == 0) begin : zero_stages + always @* begin + DOUT = DIN; + RDADDRECC = RDADDRECC_IN; + SBITERR = SBITERR_IN; + DBITERR = DBITERR_IN; + end + end + endgenerate + + //*********************************************** + // NUM_STAGES = 1 + // (Mem Output Reg only or Mux Output Reg only) + //*********************************************** + + // Possible valid combinations: + // Note: C_HAS_MUX_OUTPUT_REGS_*=0 when (C_RSTRAM_*=1) + // +-----------------------------------------+ + // | C_RSTRAM_* | Reset Behavior | + // +----------------+------------------------+ + // | 0 | Normal Behavior | + // +----------------+------------------------+ + // | 1 | Special Behavior | + // +----------------+------------------------+ + // + // Normal = REGCE gates reset, as in the case of all families except S3ADSP. + // Special = EN gates reset, as in the case of S3ADSP. + + generate if (NUM_STAGES == 1 && + (C_RSTRAM == 0 || (C_RSTRAM == 1 && C_XDEVICEFAMILY != "spartan3adsp") || + C_HAS_MEM_OUTPUT_REGS == 0 || C_HAS_RST == 0)) + begin : one_stages_norm + //Asynchronous Reset + if (C_FAMILY == "spartan6" && C_RST_TYPE == "ASYNC") begin + if(C_RST_PRIORITY == "CE") begin //REGCE has priority + always @ (*) begin + if (rst_i && regce_i) DOUT = init_val; + end + always @ (posedge CLK) begin + if (!rst_i && regce_i) DOUT <= #FLOP_DELAY DIN; + end //CLK + end else begin //RST has priority + always @ (*) begin + if (rst_i) DOUT = init_val; + end + always @ (posedge CLK) begin + if (!rst_i && regce_i) DOUT <= #FLOP_DELAY DIN; + end //CLK + end //end Priority conditions + //Synchronous Reset + end else begin + always @(posedge CLK) begin + if (C_RST_PRIORITY == "CE") begin //REGCE has priority + if (regce_i && rst_i) begin + DOUT <= #FLOP_DELAY init_val; + RDADDRECC <= #FLOP_DELAY 0; + SBITERR <= #FLOP_DELAY 1'b0; + DBITERR <= #FLOP_DELAY 1'b0; + end else if (regce_i) begin + DOUT <= #FLOP_DELAY DIN; + RDADDRECC <= #FLOP_DELAY RDADDRECC_IN; + SBITERR <= #FLOP_DELAY SBITERR_IN; + DBITERR <= #FLOP_DELAY DBITERR_IN; + end //Output signal assignments + end else begin //RST has priority + if (rst_i) begin + DOUT <= #FLOP_DELAY init_val; + RDADDRECC <= #FLOP_DELAY RDADDRECC_IN; + SBITERR <= #FLOP_DELAY 1'b0; + DBITERR <= #FLOP_DELAY 1'b0; + end else if (regce_i) begin + DOUT <= #FLOP_DELAY DIN; + RDADDRECC <= #FLOP_DELAY RDADDRECC_IN; + SBITERR <= #FLOP_DELAY SBITERR_IN; + DBITERR <= #FLOP_DELAY DBITERR_IN; + end //Output signal assignments + end //end Priority conditions + end //CLK + end //end RST Type conditions + end //end one_stages_norm generate statement + endgenerate + + // Special Reset Behavior for S3ADSP + generate if (NUM_STAGES == 1 && C_RSTRAM == 1 && C_XDEVICEFAMILY =="spartan3adsp") + begin : one_stage_splbhv + always @(posedge CLK) begin + if (en_i && rst_i) begin + DOUT <= #FLOP_DELAY init_val; + end else if (regce_i && !rst_i) begin + DOUT <= #FLOP_DELAY DIN; + end //Output signal assignments + end //end CLK + end //end one_stage_splbhv generate statement + endgenerate + + //************************************************************ + // NUM_STAGES > 1 + // Mem Output Reg + Mux Output Reg + // or + // Mem Output Reg + Mux Pipeline Stages (>0) + Mux Output Reg + // or + // Mux Pipeline Stages (>0) + Mux Output Reg + //************************************************************* + generate if (NUM_STAGES > 1) begin : multi_stage + //Asynchronous Reset + if (C_FAMILY == "spartan6" && C_RST_TYPE == "ASYNC") begin + if(C_RST_PRIORITY == "CE") begin //REGCE has priority + always @ (*) begin + if (rst_i && regce_i) DOUT = init_val; + end + always @ (posedge CLK) begin + if (!rst_i && regce_i) + DOUT <= #FLOP_DELAY out_regs[C_DATA_WIDTH*(NUM_STAGES-2)+:C_DATA_WIDTH]; + end //CLK + end else begin //RST has priority + always @ (*) begin + if (rst_i) DOUT = init_val; + end + always @ (posedge CLK) begin + if (!rst_i && regce_i) + DOUT <= #FLOP_DELAY out_regs[C_DATA_WIDTH*(NUM_STAGES-2)+:C_DATA_WIDTH]; + end //CLK + end //end Priority conditions + always @ (posedge CLK) begin + if (en_i) begin + out_regs <= (out_regs << C_DATA_WIDTH) | DIN; + end + end + //Synchronous Reset + end else begin + always @(posedge CLK) begin + if (C_RST_PRIORITY == "CE") begin //REGCE has priority + if (regce_i && rst_i) begin + DOUT <= #FLOP_DELAY init_val; + RDADDRECC <= #FLOP_DELAY 0; + SBITERR <= #FLOP_DELAY 1'b0; + DBITERR <= #FLOP_DELAY 1'b0; + end else if (regce_i) begin + DOUT <= #FLOP_DELAY + out_regs[C_DATA_WIDTH*(NUM_STAGES-2)+:C_DATA_WIDTH]; + RDADDRECC <= #FLOP_DELAY rdaddrecc_regs[C_ADDRB_WIDTH*(NUM_STAGES-2)+:C_ADDRB_WIDTH]; + SBITERR <= #FLOP_DELAY sbiterr_regs[NUM_STAGES-2]; + DBITERR <= #FLOP_DELAY dbiterr_regs[NUM_STAGES-2]; + end //Output signal assignments + end else begin //RST has priority + if (rst_i) begin + DOUT <= #FLOP_DELAY init_val; + RDADDRECC <= #FLOP_DELAY 0; + SBITERR <= #FLOP_DELAY 1'b0; + DBITERR <= #FLOP_DELAY 1'b0; + end else if (regce_i) begin + DOUT <= #FLOP_DELAY + out_regs[C_DATA_WIDTH*(NUM_STAGES-2)+:C_DATA_WIDTH]; + RDADDRECC <= #FLOP_DELAY rdaddrecc_regs[C_ADDRB_WIDTH*(NUM_STAGES-2)+:C_ADDRB_WIDTH]; + SBITERR <= #FLOP_DELAY sbiterr_regs[NUM_STAGES-2]; + DBITERR <= #FLOP_DELAY dbiterr_regs[NUM_STAGES-2]; + end //Output signal assignments + end //end Priority conditions + // Shift the data through the output stages + if (en_i) begin + out_regs <= #FLOP_DELAY (out_regs << C_DATA_WIDTH) | DIN; + rdaddrecc_regs <= #FLOP_DELAY (rdaddrecc_regs << C_ADDRB_WIDTH) | RDADDRECC_IN; + sbiterr_regs <= #FLOP_DELAY (sbiterr_regs << 1) | SBITERR_IN; + dbiterr_regs <= #FLOP_DELAY (dbiterr_regs << 1) | DBITERR_IN; + end + end //end CLK + end //end RST Type conditions + end //end multi_stage generate statement + endgenerate +endmodule + + +//***************************************************************************** +// Main Memory module +// +// This module is the top-level behavioral model and this implements the RAM +//***************************************************************************** +module BLK_MEM_GEN_V3_2 + #(parameter C_CORENAME = "blk_mem_gen_v3_2", + parameter C_FAMILY = "virtex6", + parameter C_XDEVICEFAMILY = "virtex6", + parameter C_MEM_TYPE = 2, + parameter C_BYTE_SIZE = 9, + parameter C_ALGORITHM = 1, + parameter C_PRIM_TYPE = 3, + parameter C_LOAD_INIT_FILE = 0, + parameter C_INIT_FILE_NAME = "", + parameter C_USE_DEFAULT_DATA = 0, + parameter C_DEFAULT_DATA = "0", + parameter C_RST_TYPE = "SYNC", + parameter C_HAS_RSTA = 0, + parameter C_RST_PRIORITY_A = "CE", + parameter C_RSTRAM_A = 0, + parameter C_INITA_VAL = "0", + parameter C_HAS_ENA = 1, + parameter C_HAS_REGCEA = 0, + parameter C_USE_BYTE_WEA = 0, + parameter C_WEA_WIDTH = 1, + parameter C_WRITE_MODE_A = "WRITE_FIRST", + parameter C_WRITE_WIDTH_A = 32, + parameter C_READ_WIDTH_A = 32, + parameter C_WRITE_DEPTH_A = 64, + parameter C_READ_DEPTH_A = 64, + parameter C_ADDRA_WIDTH = 5, + parameter C_HAS_RSTB = 0, + parameter C_RST_PRIORITY_B = "CE", + parameter C_RSTRAM_B = 0, + parameter C_INITB_VAL = "0", + parameter C_HAS_ENB = 1, + parameter C_HAS_REGCEB = 0, + parameter C_USE_BYTE_WEB = 0, + parameter C_WEB_WIDTH = 1, + parameter C_WRITE_MODE_B = "WRITE_FIRST", + parameter C_WRITE_WIDTH_B = 32, + parameter C_READ_WIDTH_B = 32, + parameter C_WRITE_DEPTH_B = 64, + parameter C_READ_DEPTH_B = 64, + parameter C_ADDRB_WIDTH = 5, + parameter C_HAS_MEM_OUTPUT_REGS_A = 0, + parameter C_HAS_MEM_OUTPUT_REGS_B = 0, + parameter C_HAS_MUX_OUTPUT_REGS_A = 0, + parameter C_HAS_MUX_OUTPUT_REGS_B = 0, + parameter C_MUX_PIPELINE_STAGES = 0, + parameter C_USE_ECC = 0, + parameter C_HAS_INJECTERR = 0, + parameter C_SIM_COLLISION_CHECK = "NONE", + parameter C_COMMON_CLK = 1, + parameter C_DISABLE_WARN_BHV_COLL = 0, + parameter C_DISABLE_WARN_BHV_RANGE = 0 + ) + (input CLKA, + input RSTA, + input ENA, + input REGCEA, + input [C_WEA_WIDTH-1:0] WEA, + input [C_ADDRA_WIDTH-1:0] ADDRA, + input [C_WRITE_WIDTH_A-1:0] DINA, + output [C_READ_WIDTH_A-1:0] DOUTA, + input CLKB, + input RSTB, + input ENB, + input REGCEB, + input [C_WEB_WIDTH-1:0] WEB, + input [C_ADDRB_WIDTH-1:0] ADDRB, + input [C_WRITE_WIDTH_B-1:0] DINB, + output [C_READ_WIDTH_B-1:0] DOUTB, + input INJECTSBITERR, + input INJECTDBITERR, + output SBITERR, + output DBITERR, + output [C_ADDRB_WIDTH-1:0] RDADDRECC + ); +//****************************** +// Port and Generic Definitions +//****************************** + //------------------------------------------------------------------------- + // Generic Definitions + //------------------------------------------------------------------------- + // C_CORENAME : Instance name of the Block Memory Generator core + // C_FAMILY,C_XDEVICEFAMILY: Designates architecture targeted. The following + // options are available - "spartan3", "spartan6", + // "virtex4", "virtex5" and "virtex6". + // C_MEM_TYPE : Designates memory type. + // It can be + // 0 - Single Port Memory + // 1 - Simple Dual Port Memory + // 2 - True Dual Port Memory + // 3 - Single Port Read Only Memory + // 4 - Dual Port Read Only Memory + // C_BYTE_SIZE : Size of a byte (8 or 9 bits) + // C_ALGORITHM : Designates the algorithm method used + // for constructing the memory. + // It can be Fixed_Primitives, Minimum_Area or + // Low_Power + // C_PRIM_TYPE : Designates the user selected primitive used to + // construct the memory. + // + // C_LOAD_INIT_FILE : Designates the use of an initialization file to + // initialize memory contents. + // C_INIT_FILE_NAME : Memory initialization file name. + // C_USE_DEFAULT_DATA : Designates whether to fill remaining + // initialization space with default data + // C_DEFAULT_DATA : Default value of all memory locations + // not initialized by the memory + // initialization file. + // C_RST_TYPE : Type of reset - Synchronous or Asynchronous + // C_HAS_RSTA : Determines the presence of the RSTA port + // C_RST_PRIORITY_A : Determines the priority between CE and SR for + // Port A. + // C_RSTRAM_A : Determines if special reset behavior is used for + // Port A + // C_INITA_VAL : The initialization value for Port A + // C_HAS_ENA : Determines the presence of the ENA port + // C_HAS_REGCEA : Determines the presence of the REGCEA port + // C_USE_BYTE_WEA : Determines if the Byte Write is used or not. + // C_WEA_WIDTH : The width of the WEA port + // C_WRITE_MODE_A : Configurable write mode for Port A. It can be + // WRITE_FIRST, READ_FIRST or NO_CHANGE. + // C_WRITE_WIDTH_A : Memory write width for Port A. + // C_READ_WIDTH_A : Memory read width for Port A. + // C_WRITE_DEPTH_A : Memory write depth for Port A. + // C_READ_DEPTH_A : Memory read depth for Port A. + // C_ADDRA_WIDTH : Width of the ADDRA input port + // C_HAS_RSTB : Determines the presence of the RSTB port + // C_RST_PRIORITY_B : Determines the priority between CE and SR for + // Port B. + // C_RSTRAM_B : Determines if special reset behavior is used for + // Port B + // C_INITB_VAL : The initialization value for Port B + // C_HAS_ENB : Determines the presence of the ENB port + // C_HAS_REGCEB : Determines the presence of the REGCEB port + // C_USE_BYTE_WEB : Determines if the Byte Write is used or not. + // C_WEB_WIDTH : The width of the WEB port + // C_WRITE_MODE_B : Configurable write mode for Port B. It can be + // WRITE_FIRST, READ_FIRST or NO_CHANGE. + // C_WRITE_WIDTH_B : Memory write width for Port B. + // C_READ_WIDTH_B : Memory read width for Port B. + // C_WRITE_DEPTH_B : Memory write depth for Port B. + // C_READ_DEPTH_B : Memory read depth for Port B. + // C_ADDRB_WIDTH : Width of the ADDRB input port + // C_HAS_MEM_OUTPUT_REGS_A : Designates the use of a register at the output + // of the RAM primitive for Port A. + // C_HAS_MEM_OUTPUT_REGS_B : Designates the use of a register at the output + // of the RAM primitive for Port B. + // C_HAS_MUX_OUTPUT_REGS_A : Designates the use of a register at the output + // of the MUX for Port A. + // C_HAS_MUX_OUTPUT_REGS_B : Designates the use of a register at the output + // of the MUX for Port B. + // C_MUX_PIPELINE_STAGES : Designates the number of pipeline stages in + // between the muxes. + // C_USE_ECC : Determines if the ECC feature is used or + // not. Only applicable for V5 and V6 + // C_HAS_INJECTERR : Determines if the error injection pins + // are present or not. If the ECC feature + // is not used, this value is defaulted to + // 0, else the following are the allowed + // values: + // 0 : No INJECTSBITERR or INJECTDBITERR pins + // 1 : Only INJECTSBITERR pin exists + // 2 : Only INJECTDBITERR pin exists + // 3 : Both INJECTSBITERR and INJECTDBITERR pins exist + // C_SIM_COLLISION_CHECK : Controls the disabling of Unisim model collision + // warnings. It can be "ALL", "NONE", + // "Warnings_Only" or "Generate_X_Only". + // C_COMMON_CLK : Determins if the core has a single CLK input. + // C_DISABLE_WARN_BHV_COLL : Controls the Behavioral Model Collision warnings + // C_DISABLE_WARN_BHV_RANGE: Controls the Behavioral Model Out of Range + // warnings + //------------------------------------------------------------------------- + // Port Definitions + //------------------------------------------------------------------------- + // CLKA : Clock to synchronize all read and write operations of Port A. + // RSTA : Reset input to reset memory outputs to a user-defined + // reset state for Port A. + // ENA : Enable all read and write operations of Port A. + // REGCEA : Register Clock Enable to control each pipeline output + // register stages for Port A. + // WEA : Write Enable to enable all write operations of Port A. + // ADDRA : Address of Port A. + // DINA : Data input of Port A. + // DOUTA : Data output of Port A. + // CLKB : Clock to synchronize all read and write operations of Port B. + // RSTB : Reset input to reset memory outputs to a user-defined + // reset state for Port B. + // ENB : Enable all read and write operations of Port B. + // REGCEB : Register Clock Enable to control each pipeline output + // register stages for Port B. + // WEB : Write Enable to enable all write operations of Port B. + // ADDRB : Address of Port B. + // DINB : Data input of Port B. + // DOUTB : Data output of Port B. + // INJECTSBITERR : Single Bit ECC Error Injection Pin. + // INJECTDBITERR : Double Bit ECC Error Injection Pin. + // SBITERR : Output signal indicating that a Single Bit ECC Error has been + // detected and corrected. + // DBITERR : Output signal indicating that a Double Bit ECC Error has been + // detected. + // RDADDRECC : Read Address Output signal indicating address at which an + // ECC error has occurred. + //------------------------------------------------------------------------- + + +// Note: C_CORENAME parameter is hard-coded to "blk_mem_gen_v3_2" and it is +// only used by this module to print warning messages. It is neither passed +// down from blk_mem_gen_v3_2_xst.v nor present in the instantiation template +// coregen generates + + //*************************************************************************** + // constants for the core behavior + //*************************************************************************** + // file handles for logging + //-------------------------------------------------- + localparam ADDRFILE = 32'h8000_0001; //stdout for addr out of range + localparam COLLFILE = 32'h8000_0001; //stdout for coll detection + localparam ERRFILE = 32'h8000_0001; //stdout for file I/O errors + + // other constants + //-------------------------------------------------- + localparam COLL_DELAY = 2000; // 2 ns + + // locally derived parameters to determine memory shape + //----------------------------------------------------- + localparam MIN_WIDTH_A = (C_WRITE_WIDTH_A < C_READ_WIDTH_A) ? + C_WRITE_WIDTH_A : C_READ_WIDTH_A; + localparam MIN_WIDTH_B = (C_WRITE_WIDTH_B < C_READ_WIDTH_B) ? + C_WRITE_WIDTH_B : C_READ_WIDTH_B; + localparam MIN_WIDTH = (MIN_WIDTH_A < MIN_WIDTH_B) ? + MIN_WIDTH_A : MIN_WIDTH_B; + + localparam MAX_DEPTH_A = (C_WRITE_DEPTH_A > C_READ_DEPTH_A) ? + C_WRITE_DEPTH_A : C_READ_DEPTH_A; + localparam MAX_DEPTH_B = (C_WRITE_DEPTH_B > C_READ_DEPTH_B) ? + C_WRITE_DEPTH_B : C_READ_DEPTH_B; + localparam MAX_DEPTH = (MAX_DEPTH_A > MAX_DEPTH_B) ? + MAX_DEPTH_A : MAX_DEPTH_B; + + + // locally derived parameters to assist memory access + //---------------------------------------------------- + // Calculate the width ratios of each port with respect to the narrowest + // port + localparam WRITE_WIDTH_RATIO_A = C_WRITE_WIDTH_A/MIN_WIDTH; + localparam READ_WIDTH_RATIO_A = C_READ_WIDTH_A/MIN_WIDTH; + localparam WRITE_WIDTH_RATIO_B = C_WRITE_WIDTH_B/MIN_WIDTH; + localparam READ_WIDTH_RATIO_B = C_READ_WIDTH_B/MIN_WIDTH; + + // To modify the LSBs of the 'wider' data to the actual + // address value + //---------------------------------------------------- + localparam WRITE_ADDR_A_DIV = C_WRITE_WIDTH_A/MIN_WIDTH_A; + localparam READ_ADDR_A_DIV = C_READ_WIDTH_A/MIN_WIDTH_A; + localparam WRITE_ADDR_B_DIV = C_WRITE_WIDTH_B/MIN_WIDTH_B; + localparam READ_ADDR_B_DIV = C_READ_WIDTH_B/MIN_WIDTH_B; + + // If byte writes aren't being used, make sure BYTE_SIZE is not + // wider than the memory elements to avoid compilation warnings + localparam BYTE_SIZE = (C_BYTE_SIZE < MIN_WIDTH) ? C_BYTE_SIZE : MIN_WIDTH; + + // The memory + reg [MIN_WIDTH-1:0] memory [0:MAX_DEPTH-1]; + // ECC error arrays + reg sbiterr_arr [0:MAX_DEPTH-1]; + reg dbiterr_arr [0:MAX_DEPTH-1]; + + // Memory output 'latches' + reg [C_READ_WIDTH_A-1:0] memory_out_a; + reg [C_READ_WIDTH_B-1:0] memory_out_b; + + // ECC error inputs and outputs from output_stage module: + reg sbiterr_in; + wire sbiterr_sdp; + reg dbiterr_in; + wire dbiterr_sdp; + + reg [C_ADDRB_WIDTH-1:0] rdaddrecc_in; + wire [C_ADDRB_WIDTH-1:0] rdaddrecc_sdp; + + // Reset values + reg [C_READ_WIDTH_A-1:0] inita_val; + reg [C_READ_WIDTH_B-1:0] initb_val; + + // Collision detect + reg is_collision; + reg is_collision_a, is_collision_delay_a; + reg is_collision_b, is_collision_delay_b; + + // Temporary variables for initialization + //--------------------------------------- + integer status; + integer initfile; + // data input buffer + reg [C_WRITE_WIDTH_A-1:0] mif_data; + // string values in hex + reg [C_READ_WIDTH_A*8-1:0] inita_str = C_INITA_VAL; + reg [C_READ_WIDTH_B*8-1:0] initb_str = C_INITB_VAL; + reg [C_WRITE_WIDTH_A*8-1:0] default_data_str = C_DEFAULT_DATA; + // initialization filename + reg [1023*8-1:0] init_file_str = C_INIT_FILE_NAME; + + + //Constants used to calculate the effective address widths for each of the + //four ports. + integer cnt = 1; + integer write_addr_a_width, read_addr_a_width; + integer write_addr_b_width, read_addr_b_width; + + + // Internal configuration parameters + //--------------------------------------------- + localparam FLOP_DELAY = 100; // 100 ps + localparam SINGLE_PORT = (C_MEM_TYPE==0 || C_MEM_TYPE==3); + localparam IS_ROM = (C_MEM_TYPE==3 || C_MEM_TYPE==4); + localparam HAS_A_WRITE = (!IS_ROM); + localparam HAS_B_WRITE = (C_MEM_TYPE==2); + localparam HAS_A_READ = (C_MEM_TYPE!=1); + localparam HAS_B_READ = (!SINGLE_PORT); + localparam HAS_B_PORT = (HAS_B_READ || HAS_B_WRITE); + + // Calculate the mux pipeline register stages for Port A and Port B + //------------------------------------------------------------------ + localparam MUX_PIPELINE_STAGES_A = (C_HAS_MUX_OUTPUT_REGS_A) ? + C_MUX_PIPELINE_STAGES : 0; + localparam MUX_PIPELINE_STAGES_B = (C_HAS_MUX_OUTPUT_REGS_B) ? + C_MUX_PIPELINE_STAGES : 0; + + // Calculate total number of register stages in the core + // ----------------------------------------------------- + localparam NUM_OUTPUT_STAGES_A = (C_HAS_MEM_OUTPUT_REGS_A+MUX_PIPELINE_STAGES_A+C_HAS_MUX_OUTPUT_REGS_A); + + localparam NUM_OUTPUT_STAGES_B = (C_HAS_MEM_OUTPUT_REGS_B+MUX_PIPELINE_STAGES_B+C_HAS_MUX_OUTPUT_REGS_B); + + wire ena_i; + wire enb_i; + wire reseta_i; + wire resetb_i; + wire [C_WEA_WIDTH-1:0] wea_i; + wire [C_WEB_WIDTH-1:0] web_i; + wire rea_i; + wire reb_i; + + // ECC SBITERR/DBITERR Outputs + // The ECC Behavior is modeled by the behavioral models only for Virtex-6. + // For Virtex-5, these outputs will be tied to 0. + assign SBITERR = (C_MEM_TYPE == 1 && C_USE_ECC == 1)?sbiterr_sdp:0; + assign DBITERR = (C_MEM_TYPE == 1 && C_USE_ECC == 1)?dbiterr_sdp:0; + assign RDADDRECC = (C_FAMILY == "virtex6" && C_MEM_TYPE == 1 && C_USE_ECC == 1)?rdaddrecc_sdp:0; + + + // This effectively wires off optional inputs + assign ena_i = (C_HAS_ENA==0) || ENA; + assign enb_i = ((C_HAS_ENB==0) || ENB) && HAS_B_PORT; + assign wea_i = (HAS_A_WRITE && ena_i) ? WEA : 'b0; + assign web_i = (HAS_B_WRITE && enb_i) ? WEB : 'b0; + assign rea_i = (HAS_A_READ) ? ena_i : 'b0; + assign reb_i = (HAS_B_READ) ? enb_i : 'b0; + + // These signals reset the memory latches + + assign reseta_i = + ((C_HAS_RSTA==1 && RSTA && NUM_OUTPUT_STAGES_A==0) || + (C_HAS_RSTA==1 && RSTA && C_RSTRAM_A==1)); + + assign resetb_i = + ((C_HAS_RSTB==1 && RSTB && NUM_OUTPUT_STAGES_B==0) || + (C_HAS_RSTB==1 && RSTB && C_RSTRAM_B==1)); + + // Tasks to access the memory + //--------------------------- + //************** + // write_a + //************** + task write_a + (input reg [C_ADDRA_WIDTH-1:0] addr, + input reg [C_WEA_WIDTH-1:0] byte_en, + input reg [C_WRITE_WIDTH_A-1:0] data, + input inj_sbiterr, + input inj_dbiterr); + reg [C_WRITE_WIDTH_A-1:0] current_contents; + reg [C_ADDRA_WIDTH-1:0] address; + integer i; + begin + // Shift the address by the ratio + address = (addr/WRITE_ADDR_A_DIV); + if (address >= C_WRITE_DEPTH_A) begin + if (!C_DISABLE_WARN_BHV_RANGE) begin + $fdisplay(ADDRFILE, + "%0s WARNING: Address %0h is outside range for A Write", + C_CORENAME, addr); + end + + // valid address + end else begin + + // Combine w/ byte writes + if (C_USE_BYTE_WEA) begin + + // Get the current memory contents + if (WRITE_WIDTH_RATIO_A == 1) begin + // Workaround for IUS 5.5 part-select issue + current_contents = memory[address]; + end else begin + for (i = 0; i < WRITE_WIDTH_RATIO_A; i = i + 1) begin + current_contents[MIN_WIDTH*i+:MIN_WIDTH] + = memory[address*WRITE_WIDTH_RATIO_A + i]; + end + end + + // Apply incoming bytes + if (C_WEA_WIDTH == 1) begin + // Workaround for IUS 5.5 part-select issue + if (byte_en[0]) begin + current_contents = data; + end + end else begin + for (i = 0; i < C_WEA_WIDTH; i = i + 1) begin + if (byte_en[i]) begin + current_contents[BYTE_SIZE*i+:BYTE_SIZE] + = data[BYTE_SIZE*i+:BYTE_SIZE]; + end + end + end + + // No byte-writes, overwrite the whole word + end else begin + current_contents = data; + end + + // Insert double bit errors: + if (C_USE_ECC == 1) begin + if ((C_HAS_INJECTERR == 2 || C_HAS_INJECTERR == 3) && inj_dbiterr == 1'b1) begin + current_contents[0] = !(current_contents[0]); + current_contents[1] = !(current_contents[1]); + end + end + + // Write data to memory + if (WRITE_WIDTH_RATIO_A == 1) begin + // Workaround for IUS 5.5 part-select issue + memory[address*WRITE_WIDTH_RATIO_A] = current_contents; + end else begin + for (i = 0; i < WRITE_WIDTH_RATIO_A; i = i + 1) begin + memory[address*WRITE_WIDTH_RATIO_A + i] + = current_contents[MIN_WIDTH*i+:MIN_WIDTH]; + end + end + + // Store the address at which error is injected: + if (C_FAMILY == "virtex6" && C_USE_ECC == 1) begin + if ((C_HAS_INJECTERR == 1 && inj_sbiterr == 1'b1) || + (C_HAS_INJECTERR == 3 && inj_sbiterr == 1'b1 && inj_dbiterr != 1'b1)) + begin + sbiterr_arr[addr] = 1; + end else begin + sbiterr_arr[addr] = 0; + end + + if ((C_HAS_INJECTERR == 2 || C_HAS_INJECTERR == 3) && inj_dbiterr == 1'b1) begin + dbiterr_arr[addr] = 1; + end else begin + dbiterr_arr[addr] = 0; + end + end + + end + end + endtask + + //************** + // write_b + //************** + task write_b + (input reg [C_ADDRB_WIDTH-1:0] addr, + input reg [C_WEB_WIDTH-1:0] byte_en, + input reg [C_WRITE_WIDTH_B-1:0] data); + reg [C_WRITE_WIDTH_B-1:0] current_contents; + reg [C_ADDRB_WIDTH-1:0] address; + integer i; + begin + // Shift the address by the ratio + address = (addr/WRITE_ADDR_B_DIV); + if (address >= C_WRITE_DEPTH_B) begin + if (!C_DISABLE_WARN_BHV_RANGE) begin + $fdisplay(ADDRFILE, + "%0s WARNING: Address %0h is outside range for B Write", + C_CORENAME, addr); + end + + // valid address + end else begin + + // Combine w/ byte writes + if (C_USE_BYTE_WEB) begin + + // Get the current memory contents + if (WRITE_WIDTH_RATIO_B == 1) begin + // Workaround for IUS 5.5 part-select issue + current_contents = memory[address]; + end else begin + for (i = 0; i < WRITE_WIDTH_RATIO_B; i = i + 1) begin + current_contents[MIN_WIDTH*i+:MIN_WIDTH] + = memory[address*WRITE_WIDTH_RATIO_B + i]; + end + end + + // Apply incoming bytes + if (C_WEB_WIDTH == 1) begin + // Workaround for IUS 5.5 part-select issue + if (byte_en[0]) begin + current_contents = data; + end + end else begin + for (i = 0; i < C_WEB_WIDTH; i = i + 1) begin + if (byte_en[i]) begin + current_contents[BYTE_SIZE*i+:BYTE_SIZE] + = data[BYTE_SIZE*i+:BYTE_SIZE]; + end + end + end + + // No byte-writes, overwrite the whole word + end else begin + current_contents = data; + end + + // Write data to memory + if (WRITE_WIDTH_RATIO_B == 1) begin + // Workaround for IUS 5.5 part-select issue + memory[address*WRITE_WIDTH_RATIO_B] = current_contents; + end else begin + for (i = 0; i < WRITE_WIDTH_RATIO_B; i = i + 1) begin + memory[address*WRITE_WIDTH_RATIO_B + i] + = current_contents[MIN_WIDTH*i+:MIN_WIDTH]; + end + end + end + end + endtask + + //************** + // read_a + //************** + task read_a + (input reg [C_ADDRA_WIDTH-1:0] addr, + input reg reset); + reg [C_ADDRA_WIDTH-1:0] address; + integer i; + begin + + if (reset) begin + memory_out_a <= #FLOP_DELAY inita_val; + end else begin + // Shift the address by the ratio + address = (addr/READ_ADDR_A_DIV); + if (address >= C_READ_DEPTH_A) begin + if (!C_DISABLE_WARN_BHV_RANGE) begin + $fdisplay(ADDRFILE, + "%0s WARNING: Address %0h is outside range for A Read", + C_CORENAME, addr); + end + memory_out_a <= #FLOP_DELAY 'bX; + // valid address + end else begin + if (READ_WIDTH_RATIO_A==1) begin + memory_out_a <= #FLOP_DELAY memory[address*READ_WIDTH_RATIO_A]; + end else begin + // Increment through the 'partial' words in the memory + for (i = 0; i < READ_WIDTH_RATIO_A; i = i + 1) begin + memory_out_a[MIN_WIDTH*i+:MIN_WIDTH] + <= #FLOP_DELAY memory[address*READ_WIDTH_RATIO_A + i]; + end + end //end READ_WIDTH_RATIO_A==1 loop + + end //end valid address loop + end //end reset-data assignment loops + end + endtask + + //************** + // read_b + //************** + task read_b + (input reg [C_ADDRB_WIDTH-1:0] addr, + input reg reset); + reg [C_ADDRB_WIDTH-1:0] address; + integer i; + begin + + if (reset) begin + memory_out_b <= #FLOP_DELAY initb_val; + sbiterr_in <= #FLOP_DELAY 1'b0; + dbiterr_in <= #FLOP_DELAY 1'b0; + rdaddrecc_in <= #FLOP_DELAY 0; + end else begin + // Shift the address + address = (addr/READ_ADDR_B_DIV); + if (address >= C_READ_DEPTH_B) begin + if (!C_DISABLE_WARN_BHV_RANGE) begin + $fdisplay(ADDRFILE, + "%0s WARNING: Address %0h is outside range for B Read", + C_CORENAME, addr); + end + memory_out_b <= #FLOP_DELAY 'bX; + sbiterr_in <= #FLOP_DELAY 1'bX; + dbiterr_in <= #FLOP_DELAY 1'bX; + rdaddrecc_in <= #FLOP_DELAY 'bX; + // valid address + end else begin + if (READ_WIDTH_RATIO_B==1) begin + memory_out_b <= #FLOP_DELAY memory[address*READ_WIDTH_RATIO_B]; + end else begin + // Increment through the 'partial' words in the memory + for (i = 0; i < READ_WIDTH_RATIO_B; i = i + 1) begin + memory_out_b[MIN_WIDTH*i+:MIN_WIDTH] + <= #FLOP_DELAY memory[address*READ_WIDTH_RATIO_B + i]; + end + end + + if (C_FAMILY == "virtex6" && C_USE_ECC == 1) begin + rdaddrecc_in <= addr; + if (sbiterr_arr[addr] == 1) begin + sbiterr_in <= #FLOP_DELAY 1'b1; + end else begin + sbiterr_in <= #FLOP_DELAY 1'b0; + end + + if (dbiterr_arr[addr] == 1) begin + dbiterr_in <= #FLOP_DELAY 1'b1; + end else begin + dbiterr_in <= #FLOP_DELAY 1'b0; + end + end else begin + rdaddrecc_in <= #FLOP_DELAY 0; + dbiterr_in <= #FLOP_DELAY 1'b0; + sbiterr_in <= #FLOP_DELAY 1'b0; + end //end ECC Loop + + end //end Valid address loop + end //end reset-data assignment loops + end + endtask + + //************** + // reset_a + //************** + task reset_a (input reg reset); + begin + if (reset) memory_out_a <= #FLOP_DELAY inita_val; + end + endtask + + //************** + // reset_b + //************** + task reset_b (input reg reset); + begin + if (reset) memory_out_b <= #FLOP_DELAY initb_val; + end + endtask + + //************** + // init_memory + //************** + task init_memory; + integer i, addr_step; + integer status; + reg [C_WRITE_WIDTH_A-1:0] default_data; + begin + default_data = 0; + + //Display output message indicating that the behavioral model is being + //initialized + if (C_USE_DEFAULT_DATA || C_LOAD_INIT_FILE) $display(" Block Memory Generator CORE Generator module loading initial data..."); + + // Convert the default to hex + if (C_USE_DEFAULT_DATA) begin + if (default_data_str == "") begin + $fdisplay(ERRFILE, "%0s ERROR: C_DEFAULT_DATA is empty!", C_CORENAME); + $finish; + end else begin + status = $sscanf(default_data_str, "%h", default_data); + if (status == 0) begin + $fdisplay(ERRFILE, {"%0s ERROR: Unsuccessful hexadecimal read", + "from C_DEFAULT_DATA: %0s"}, + C_CORENAME, C_DEFAULT_DATA); + $finish; + end + end + end + + // Step by WRITE_ADDR_A_DIV through the memory via the + // Port A write interface to hit every location once + addr_step = WRITE_ADDR_A_DIV; + + // 'write' to every location with default (or 0) + for (i = 0; i < C_WRITE_DEPTH_A*addr_step; i = i + addr_step) begin + write_a(i, {C_WEA_WIDTH{1'b1}}, default_data, 1'b0, 1'b0); + end + + // Get specialized data from the MIF file + if (C_LOAD_INIT_FILE) begin + if (init_file_str == "") begin + $fdisplay(ERRFILE, "%0s ERROR: C_INIT_FILE_NAME is empty!", + C_CORENAME); + $finish; + end else begin + initfile = $fopen(init_file_str, "r"); + if (initfile == 0) begin + $fdisplay(ERRFILE, {"%0s, ERROR: Problem opening", + "C_INIT_FILE_NAME: %0s!"}, + C_CORENAME, init_file_str); + $finish; + end else begin + // loop through the mif file, loading in the data + for (i = 0; i < C_WRITE_DEPTH_A*addr_step; i = i + addr_step) begin + status = $fscanf(initfile, "%b", mif_data); + if (status > 0) begin + write_a(i, {C_WEA_WIDTH{1'b1}}, mif_data, 1'b0, 1'b0); + end + end + $fclose(initfile); + end //initfile + end //init_file_str + end //C_LOAD_INIT_FILE + + //Display output message indicating that the behavioral model is done + //initializing + if (C_USE_DEFAULT_DATA || C_LOAD_INIT_FILE) + $display(" Block Memory Generator data initialization complete."); + end + endtask + + //************** + // log2roundup + //************** + function integer log2roundup (input integer data_value); + integer width; + integer cnt; + begin + width = 0; + + if (data_value > 1) begin + for(cnt=1 ; cnt < data_value ; cnt = cnt * 2) begin + width = width + 1; + end //loop + end //if + + log2roundup = width; + + end //log2roundup + endfunction + + + //******************* + // collision_check + //******************* + function integer collision_check (input reg [C_ADDRA_WIDTH-1:0] addr_a, + input integer iswrite_a, + input reg [C_ADDRB_WIDTH-1:0] addr_b, + input integer iswrite_b); + reg c_aw_bw, c_aw_br, c_ar_bw; + integer scaled_addra_to_waddrb_width; + integer scaled_addrb_to_waddrb_width; + integer scaled_addra_to_waddra_width; + integer scaled_addrb_to_waddra_width; + integer scaled_addra_to_raddrb_width; + integer scaled_addrb_to_raddrb_width; + integer scaled_addra_to_raddra_width; + integer scaled_addrb_to_raddra_width; + + + + begin + + c_aw_bw = 0; + c_aw_br = 0; + c_ar_bw = 0; + + //If write_addr_b_width is smaller, scale both addresses to that width for + //comparing write_addr_a and write_addr_b; addr_a starts as C_ADDRA_WIDTH, + //scale it down to write_addr_b_width. addr_b starts as C_ADDRB_WIDTH, + //scale it down to write_addr_b_width. Once both are scaled to + //write_addr_b_width, compare. + scaled_addra_to_waddrb_width = ((addr_a)/ + 2**(C_ADDRA_WIDTH-write_addr_b_width)); + scaled_addrb_to_waddrb_width = ((addr_b)/ + 2**(C_ADDRB_WIDTH-write_addr_b_width)); + + //If write_addr_a_width is smaller, scale both addresses to that width for + //comparing write_addr_a and write_addr_b; addr_a starts as C_ADDRA_WIDTH, + //scale it down to write_addr_a_width. addr_b starts as C_ADDRB_WIDTH, + //scale it down to write_addr_a_width. Once both are scaled to + //write_addr_a_width, compare. + scaled_addra_to_waddra_width = ((addr_a)/ + 2**(C_ADDRA_WIDTH-write_addr_a_width)); + scaled_addrb_to_waddra_width = ((addr_b)/ + 2**(C_ADDRB_WIDTH-write_addr_a_width)); + + //If read_addr_b_width is smaller, scale both addresses to that width for + //comparing write_addr_a and read_addr_b; addr_a starts as C_ADDRA_WIDTH, + //scale it down to read_addr_b_width. addr_b starts as C_ADDRB_WIDTH, + //scale it down to read_addr_b_width. Once both are scaled to + //read_addr_b_width, compare. + scaled_addra_to_raddrb_width = ((addr_a)/ + 2**(C_ADDRA_WIDTH-read_addr_b_width)); + scaled_addrb_to_raddrb_width = ((addr_b)/ + 2**(C_ADDRB_WIDTH-read_addr_b_width)); + + //If read_addr_a_width is smaller, scale both addresses to that width for + //comparing read_addr_a and write_addr_b; addr_a starts as C_ADDRA_WIDTH, + //scale it down to read_addr_a_width. addr_b starts as C_ADDRB_WIDTH, + //scale it down to read_addr_a_width. Once both are scaled to + //read_addr_a_width, compare. + scaled_addra_to_raddra_width = ((addr_a)/ + 2**(C_ADDRA_WIDTH-read_addr_a_width)); + scaled_addrb_to_raddra_width = ((addr_b)/ + 2**(C_ADDRB_WIDTH-read_addr_a_width)); + + //Look for a write-write collision. In order for a write-write + //collision to exist, both ports must have a write transaction. + if (iswrite_a && iswrite_b) begin + if (write_addr_a_width > write_addr_b_width) begin + if (scaled_addra_to_waddrb_width == scaled_addrb_to_waddrb_width) begin + c_aw_bw = 1; + end else begin + c_aw_bw = 0; + end + end else begin + if (scaled_addrb_to_waddra_width == scaled_addra_to_waddra_width) begin + c_aw_bw = 1; + end else begin + c_aw_bw = 0; + end + end //width + end //iswrite_a and iswrite_b + + //If the B port is reading (which means it is enabled - so could be + //a TX_WRITE or TX_READ), then check for a write-read collision). + //This could happen whether or not a write-write collision exists due + //to asymmetric write/read ports. + if (iswrite_a) begin + if (write_addr_a_width > read_addr_b_width) begin + if (scaled_addra_to_raddrb_width == scaled_addrb_to_raddrb_width) begin + c_aw_br = 1; + end else begin + c_aw_br = 0; + end + end else begin + if (scaled_addrb_to_waddra_width == scaled_addra_to_waddra_width) begin + c_aw_br = 1; + end else begin + c_aw_br = 0; + end + end //width + end //iswrite_a + + //If the A port is reading (which means it is enabled - so could be + // a TX_WRITE or TX_READ), then check for a write-read collision). + //This could happen whether or not a write-write collision exists due + // to asymmetric write/read ports. + if (iswrite_b) begin + if (read_addr_a_width > write_addr_b_width) begin + if (scaled_addra_to_waddrb_width == scaled_addrb_to_waddrb_width) begin + c_ar_bw = 1; + end else begin + c_ar_bw = 0; + end + end else begin + if (scaled_addrb_to_raddra_width == scaled_addra_to_raddra_width) begin + c_ar_bw = 1; + end else begin + c_ar_bw = 0; + end + end //width + end //iswrite_b + + + + collision_check = c_aw_bw | c_aw_br | c_ar_bw; + + end + endfunction + + //******************************* + // power on values + //******************************* + initial begin + // Load up the memory + init_memory; + // Load up the output registers and latches + if ($sscanf(inita_str, "%h", inita_val)) begin + memory_out_a = inita_val; + end else begin + memory_out_a = 0; + end + if ($sscanf(initb_str, "%h", initb_val)) begin + memory_out_b = initb_val; + end else begin + memory_out_b = 0; + end + + sbiterr_in = 1'b0; + dbiterr_in = 1'b0; + rdaddrecc_in = 0; + + // Determine the effective address widths for each of the 4 ports + write_addr_a_width = C_ADDRA_WIDTH - log2roundup(WRITE_ADDR_A_DIV); + read_addr_a_width = C_ADDRA_WIDTH - log2roundup(READ_ADDR_A_DIV); + write_addr_b_width = C_ADDRB_WIDTH - log2roundup(WRITE_ADDR_B_DIV); + read_addr_b_width = C_ADDRB_WIDTH - log2roundup(READ_ADDR_B_DIV); + + $display("Block Memory Generator CORE Generator module %m is using a behavioral model for simulation which will not precisely model memory collision behavior."); + + end + + //************************************************************************* + // Asynchronous reset of Port A and Port B are performed here + // Note that the asynchronous reset feature is only supported in Spartan6 + // devices + //************************************************************************* + generate if(C_FAMILY=="spartan6" && C_RST_TYPE=="ASYNC") begin : async_rst + if (C_RST_PRIORITY_A=="CE") begin + always @ (*) begin + if (rea_i) reset_a(reseta_i); + end + end + else begin + always @ (*) begin + reset_a(reseta_i); + end + end + + if (C_RST_PRIORITY_B=="CE") begin + always @ (*) begin + if (reb_i) reset_b(resetb_i); + end + end + else begin + always @ (*) begin + reset_b(resetb_i); + end + end + + end + endgenerate + + //*************************************************************************** + // These are the main blocks which schedule read and write operations + // Note that the reset priority feature at the latch stage is only supported + // for Spartan-6. For other families, the default priority at the latch stage + // is "CE" + //*************************************************************************** + // Synchronous clocks: schedule port operations with respect to + // both write operating modes + generate + if(C_COMMON_CLK && (C_WRITE_MODE_A == "WRITE_FIRST") && (C_WRITE_MODE_B == + "WRITE_FIRST")) begin : com_clk_sched_wf_wf + always @(posedge CLKA) begin + //Write A + if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR); + //Write B + if (web_i) write_b(ADDRB, web_i, DINB); + //Read A + if (C_FAMILY=="spartan6" && C_RST_PRIORITY_A=="SR") begin + if (reseta_i) reset_a(reseta_i); + else if (rea_i) read_a(ADDRA, reseta_i); + end else begin + if (rea_i) read_a(ADDRA, reseta_i); + end + //Read B + if (C_FAMILY=="spartan6" && C_RST_PRIORITY_B=="SR") begin + if (resetb_i) reset_b(resetb_i); + else if (reb_i) read_b(ADDRB, resetb_i); + end else begin + if (reb_i) read_b(ADDRB, resetb_i); + end + end + end + else + if(C_COMMON_CLK && (C_WRITE_MODE_A == "READ_FIRST") && (C_WRITE_MODE_B == + "WRITE_FIRST")) begin : com_clk_sched_rf_wf + always @(posedge CLKA) begin + //Write B + if (web_i) write_b(ADDRB, web_i, DINB); + //Read B + if (C_FAMILY=="spartan6" && C_RST_PRIORITY_B=="SR") begin + if (resetb_i) reset_b(resetb_i); + else if (reb_i) read_b(ADDRB, resetb_i); + end else begin + if (reb_i) read_b(ADDRB, resetb_i); + end + //Read A + if (C_FAMILY=="spartan6" && C_RST_PRIORITY_A=="SR") begin + if (reseta_i) reset_a(reseta_i); + else if (rea_i) read_a(ADDRA, reseta_i); + end else begin + if (rea_i) read_a(ADDRA, reseta_i); + end + //Write A + if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR); + end + end + else + if(C_COMMON_CLK && (C_WRITE_MODE_A == "WRITE_FIRST") && (C_WRITE_MODE_B == + "READ_FIRST")) begin : com_clk_sched_wf_rf + always @(posedge CLKA) begin + //Write A + if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR); + //Read A + if (C_FAMILY=="spartan6" && C_RST_PRIORITY_A=="SR") begin + if (reseta_i) reset_a(reseta_i); + else if (rea_i) read_a(ADDRA, reseta_i); + end else begin + if (rea_i) read_a(ADDRA, reseta_i); + end + //Read B + if (C_FAMILY=="spartan6" && C_RST_PRIORITY_B=="SR") begin + if (resetb_i) reset_b(resetb_i); + else if (reb_i) read_b(ADDRB, resetb_i); + end else begin + if (reb_i) read_b(ADDRB, resetb_i); + end + //Write B + if (web_i) write_b(ADDRB, web_i, DINB); + end + end + else + if(C_COMMON_CLK && (C_WRITE_MODE_A == "READ_FIRST") && (C_WRITE_MODE_B == + "READ_FIRST")) begin : com_clk_sched_rf_rf + always @(posedge CLKA) begin + //Read A + if (C_FAMILY=="spartan6" && C_RST_PRIORITY_A=="SR") begin + if (reseta_i) reset_a(reseta_i); + else if (rea_i) read_a(ADDRA, reseta_i); + end else begin + if (rea_i) read_a(ADDRA, reseta_i); + end + //Read B + if (C_FAMILY=="spartan6" && C_RST_PRIORITY_B=="SR") begin + if (resetb_i) reset_b(resetb_i); + else if (reb_i) read_b(ADDRB, resetb_i); + end else begin + if (reb_i) read_b(ADDRB, resetb_i); + end + //Write A + if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR); + //Write B + if (web_i) write_b(ADDRB, web_i, DINB); + end + end + else if(C_COMMON_CLK && (C_WRITE_MODE_A =="WRITE_FIRST") && (C_WRITE_MODE_B == + "NO_CHANGE")) begin : com_clk_sched_wf_nc + always @(posedge CLKA) begin + //Write A + if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR); + //Read A + if (C_FAMILY=="spartan6" && C_RST_PRIORITY_A=="SR") begin + if (reseta_i) reset_a(reseta_i); + else if (rea_i) read_a(ADDRA, reseta_i); + end else begin + if (rea_i) read_a(ADDRA, reseta_i); + end + //Read B + if (C_FAMILY=="spartan6" && C_RST_PRIORITY_B=="SR") begin + if (resetb_i) reset_b(resetb_i); + else if (reb_i && !web_i) read_b(ADDRB, resetb_i); + end else begin + if (reb_i && (!web_i || resetb_i)) read_b(ADDRB, resetb_i); + end + //Write B + if (web_i) write_b(ADDRB, web_i, DINB); + end + end + else if(C_COMMON_CLK && (C_WRITE_MODE_A =="READ_FIRST") && (C_WRITE_MODE_B == + "NO_CHANGE")) begin : com_clk_sched_rf_nc + always @(posedge CLKA) begin + //Read A + if (C_FAMILY=="spartan6" && C_RST_PRIORITY_A=="SR") begin + if (reseta_i) reset_a(reseta_i); + else if (rea_i) read_a(ADDRA, reseta_i); + end else begin + if (rea_i) read_a(ADDRA, reseta_i); + end + //Read B + if (C_FAMILY=="spartan6" && C_RST_PRIORITY_B=="SR") begin + if (resetb_i) reset_b(resetb_i); + else if (reb_i && !web_i) read_b(ADDRB, resetb_i); + end else begin + if (reb_i && (!web_i || resetb_i)) read_b(ADDRB, resetb_i); + end + //Write A + if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR); + //Write B + if (web_i) write_b(ADDRB, web_i, DINB); + end + end + else if(C_COMMON_CLK && (C_WRITE_MODE_A =="NO_CHANGE") && (C_WRITE_MODE_B == + "WRITE_FIRST")) begin : com_clk_sched_nc_wf + always @(posedge CLKA) begin + //Write A + if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR); + //Write B + if (web_i) write_b(ADDRB, web_i, DINB); + //Read A + if (C_FAMILY=="spartan6" && C_RST_PRIORITY_A=="SR") begin + if (reseta_i) reset_a(reseta_i); + else if (rea_i && !wea_i) read_a(ADDRA, reseta_i); + end else begin + if (rea_i && (!wea_i || reseta_i)) read_a(ADDRA, reseta_i); + end + //Read B + if (C_FAMILY=="spartan6" && C_RST_PRIORITY_B=="SR") begin + if (resetb_i) reset_b(resetb_i); + else if (reb_i) read_b(ADDRB, resetb_i); + end else begin + if (reb_i) read_b(ADDRB, resetb_i); + end + end + end + else if(C_COMMON_CLK && (C_WRITE_MODE_A =="NO_CHANGE") && (C_WRITE_MODE_B == + "READ_FIRST")) begin : com_clk_sched_nc_rf + always @(posedge CLKA) begin + //Read B + if (C_FAMILY=="spartan6" && C_RST_PRIORITY_B=="SR") begin + if (resetb_i) reset_b(resetb_i); + else if (reb_i) read_b(ADDRB, resetb_i); + end else begin + if (reb_i) read_b(ADDRB, resetb_i); + end + //Read A + if (C_FAMILY=="spartan6" && C_RST_PRIORITY_A=="SR") begin + if (reseta_i) reset_a(reseta_i); + else if (rea_i && !wea_i) read_a(ADDRA, reseta_i); + end else begin + if (rea_i && (!wea_i || reseta_i)) read_a(ADDRA, reseta_i); + end + //Write A + if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR); + //Write B + if (web_i) write_b(ADDRB, web_i, DINB); + end + end + else if(C_COMMON_CLK && (C_WRITE_MODE_A =="NO_CHANGE") && (C_WRITE_MODE_B == + "NO_CHANGE")) begin : com_clk_sched_nc_nc + always @(posedge CLKA) begin + //Write A + if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR); + //Write B + if (web_i) write_b(ADDRB, web_i, DINB); + //Read A + if (C_FAMILY=="spartan6" && C_RST_PRIORITY_A=="SR") begin + if (reseta_i) reset_a(reseta_i); + else if (rea_i && !wea_i) read_a(ADDRA, reseta_i); + end else begin + if (rea_i && (!wea_i || reseta_i)) read_a(ADDRA, reseta_i); + end + //Read B + if (C_FAMILY=="spartan6" && C_RST_PRIORITY_B=="SR") begin + if (resetb_i) reset_b(resetb_i); + else if (reb_i && !web_i) read_b(ADDRB, resetb_i); + end else begin + if (reb_i && (!web_i || resetb_i)) read_b(ADDRB, resetb_i); + end + end + end + else if(C_COMMON_CLK) begin: com_clk_sched_default + always @(posedge CLKA) begin + //Write A + if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR); + //Write B + if (web_i) write_b(ADDRB, web_i, DINB); + //Read A + if (C_FAMILY=="spartan6" && C_RST_PRIORITY_A=="SR") begin + if (reseta_i) reset_a(reseta_i); + else if (rea_i) read_a(ADDRA, reseta_i); + end else begin + if (rea_i) read_a(ADDRA, reseta_i); + end + //Read B + if (C_FAMILY=="spartan6" && C_RST_PRIORITY_B=="SR") begin + if (resetb_i) reset_b(resetb_i); + else if (reb_i) read_b(ADDRB, resetb_i); + end else begin + if (reb_i) read_b(ADDRB, resetb_i); + end + end + end + endgenerate + + // Asynchronous clocks: port operation is independent + + generate + if((!C_COMMON_CLK) && (C_WRITE_MODE_A == "WRITE_FIRST")) begin : async_clk_sched_clka_wf + always @(posedge CLKA) begin + //Write A + if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR); + //Read A + if (C_FAMILY=="spartan6" && C_RST_PRIORITY_A=="SR") begin + if (reseta_i) reset_a(reseta_i); + else if (rea_i) read_a(ADDRA, reseta_i); + end else begin + if (rea_i) read_a(ADDRA, reseta_i); + end + end + end + else if((!C_COMMON_CLK) && (C_WRITE_MODE_A == "READ_FIRST")) begin : async_clk_sched_clka_rf + always @(posedge CLKA) begin + //Read A + if (C_FAMILY=="spartan6" && C_RST_PRIORITY_A=="SR") begin + if (reseta_i) reset_a(reseta_i); + else if (rea_i) read_a(ADDRA, reseta_i); + end else begin + if (rea_i) read_a(ADDRA, reseta_i); + end + //Write A + if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR); + end + end + else if((!C_COMMON_CLK) && (C_WRITE_MODE_A == "NO_CHANGE")) begin : async_clk_sched_clka_nc + always @(posedge CLKA) begin + //Write A + if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR); + //Read A + if (C_FAMILY=="spartan6" && C_RST_PRIORITY_A=="SR") begin + if (reseta_i) reset_a(reseta_i); + else if (rea_i && !wea_i) read_a(ADDRA, reseta_i); + end else begin + if (rea_i && (!wea_i || reseta_i)) read_a(ADDRA, reseta_i); + end + end + end + endgenerate + + generate + if ((!C_COMMON_CLK) && (C_WRITE_MODE_B == "WRITE_FIRST")) begin: async_clk_sched_clkb_wf + always @(posedge CLKB) begin + //Write B + if (web_i) write_b(ADDRB, web_i, DINB); + //Read B + if (C_FAMILY=="spartan6" && C_RST_PRIORITY_B=="SR") begin + if (resetb_i) reset_b(resetb_i); + else if (reb_i) read_b(ADDRB, resetb_i); + end else begin + if (reb_i) read_b(ADDRB, resetb_i); + end + end + end + else if ((!C_COMMON_CLK) && (C_WRITE_MODE_B == "READ_FIRST")) begin: async_clk_sched_clkb_rf + always @(posedge CLKB) begin + //Read B + if (C_FAMILY=="spartan6" && C_RST_PRIORITY_B=="SR") begin + if (resetb_i) reset_b(resetb_i); + else if (reb_i) read_b(ADDRB, resetb_i); + end else begin + if (reb_i) read_b(ADDRB, resetb_i); + end + //Write B + if (web_i) write_b(ADDRB, web_i, DINB); + end + end + else if ((!C_COMMON_CLK) && (C_WRITE_MODE_B == "NO_CHANGE")) begin: async_clk_sched_clkb_nc + always @(posedge CLKB) begin + //Write B + if (web_i) write_b(ADDRB, web_i, DINB); + //Read B + if (C_FAMILY=="spartan6" && C_RST_PRIORITY_B=="SR") begin + if (resetb_i) reset_b(resetb_i); + else if (reb_i && !web_i) read_b(ADDRB, resetb_i); + end else begin + if (reb_i && (!web_i || resetb_i)) read_b(ADDRB, resetb_i); + end + end + end + endgenerate + + + //*************************************************************** + // Instantiate the variable depth output register stage module + //*************************************************************** + // Port A + BLK_MEM_GEN_V3_2_output_stage + #(.C_FAMILY (C_FAMILY), + .C_XDEVICEFAMILY (C_XDEVICEFAMILY), + .C_RST_TYPE (C_RST_TYPE), + .C_HAS_RST (C_HAS_RSTA), + .C_RSTRAM (C_RSTRAM_A), + .C_RST_PRIORITY (C_RST_PRIORITY_A), + .C_INIT_VAL (C_INITA_VAL), + .C_HAS_EN (C_HAS_ENA), + .C_HAS_REGCE (C_HAS_REGCEA), + .C_DATA_WIDTH (C_READ_WIDTH_A), + .C_ADDRB_WIDTH (C_ADDRB_WIDTH), + .C_HAS_MEM_OUTPUT_REGS (C_HAS_MEM_OUTPUT_REGS_A), + .C_USE_ECC (C_USE_ECC), + .NUM_STAGES (NUM_OUTPUT_STAGES_A), + .FLOP_DELAY (FLOP_DELAY)) + reg_a + (.CLK (CLKA), + .RST (RSTA), + .EN (ENA), + .REGCE (REGCEA), + .DIN (memory_out_a), + .DOUT (DOUTA), + .SBITERR_IN (1'b0), + .DBITERR_IN (1'b0), + .SBITERR (), + .DBITERR (), + .RDADDRECC_IN ({C_ADDRB_WIDTH{1'b0}}), + .RDADDRECC () + ); + + // Port B + BLK_MEM_GEN_V3_2_output_stage + #(.C_FAMILY (C_FAMILY), + .C_XDEVICEFAMILY (C_XDEVICEFAMILY), + .C_RST_TYPE (C_RST_TYPE), + .C_HAS_RST (C_HAS_RSTB), + .C_RSTRAM (C_RSTRAM_B), + .C_RST_PRIORITY (C_RST_PRIORITY_B), + .C_INIT_VAL (C_INITB_VAL), + .C_HAS_EN (C_HAS_ENB), + .C_HAS_REGCE (C_HAS_REGCEB), + .C_DATA_WIDTH (C_READ_WIDTH_B), + .C_ADDRB_WIDTH (C_ADDRB_WIDTH), + .C_HAS_MEM_OUTPUT_REGS (C_HAS_MEM_OUTPUT_REGS_B), + .C_USE_ECC (C_USE_ECC), + .NUM_STAGES (NUM_OUTPUT_STAGES_B), + .FLOP_DELAY (FLOP_DELAY)) + reg_b + (.CLK (CLKB), + .RST (RSTB), + .EN (ENB), + .REGCE (REGCEB), + .DIN (memory_out_b), + .DOUT (DOUTB), + .SBITERR_IN (sbiterr_in), + .DBITERR_IN (dbiterr_in), + .SBITERR (sbiterr_sdp), + .DBITERR (dbiterr_sdp), + .RDADDRECC_IN (rdaddrecc_in), + .RDADDRECC (rdaddrecc_sdp) + ); + + //**************************************************** + // Synchronous collision checks + //**************************************************** + generate if (!C_DISABLE_WARN_BHV_COLL && C_COMMON_CLK) begin : sync_coll + always @(posedge CLKA) begin + // Possible collision if both are enabled and the addresses match + if (ena_i && enb_i) begin + if (wea_i || web_i) begin + is_collision <= collision_check(ADDRA, wea_i, ADDRB, web_i); + end else begin + is_collision <= 0; + end + end else begin + is_collision <= 0; + end + + // If the write port is in READ_FIRST mode, there is no collision + if (C_WRITE_MODE_A=="READ_FIRST" && wea_i && !web_i) begin + is_collision <= 0; + end + if (C_WRITE_MODE_B=="READ_FIRST" && web_i && !wea_i) begin + is_collision <= 0; + end + + // Only flag if one of the accesses is a write + if (is_collision && (wea_i || web_i)) begin + $fwrite(COLLFILE, "%0s collision detected at time: %0d, ", + C_CORENAME, $time); + $fwrite(COLLFILE, "A %0s address: %0h, B %0s address: %0h\n", + wea_i ? "write" : "read", ADDRA, + web_i ? "write" : "read", ADDRB); + end + end + + //**************************************************** + // Asynchronous collision checks + //**************************************************** + end else if (!C_DISABLE_WARN_BHV_COLL && !C_COMMON_CLK) begin : async_coll + + // Delay A and B addresses in order to mimic setup/hold times + wire [C_ADDRA_WIDTH-1:0] #COLL_DELAY addra_delay = ADDRA; + wire [0:0] #COLL_DELAY wea_delay = wea_i; + wire #COLL_DELAY ena_delay = ena_i; + wire [C_ADDRB_WIDTH-1:0] #COLL_DELAY addrb_delay = ADDRB; + wire [0:0] #COLL_DELAY web_delay = web_i; + wire #COLL_DELAY enb_delay = enb_i; + + // Do the checks w/rt A + always @(posedge CLKA) begin + // Possible collision if both are enabled and the addresses match + if (ena_i && enb_i) begin + if (wea_i || web_i) begin + is_collision_a <= collision_check(ADDRA, wea_i, ADDRB, web_i); + end else begin + is_collision_a <= 0; + end + end else begin + is_collision_a <= 0; + end + + if (ena_i && enb_delay) begin + if(wea_i || web_delay) begin + is_collision_delay_a <= collision_check(ADDRA, wea_i, addrb_delay, + web_delay); + end else begin + is_collision_delay_a <= 0; + end + end else begin + is_collision_delay_a <= 0; + end + + + // Only flag if B access is a write + if (is_collision_a && web_i) begin + $fwrite(COLLFILE, "%0s collision detected at time: %0d, ", + C_CORENAME, $time); + $fwrite(COLLFILE, "A %0s address: %0h, B write address: %0h\n", + wea_i ? "write" : "read", ADDRA, ADDRB); + + end else if (is_collision_delay_a && web_delay) begin + $fwrite(COLLFILE, "%0s collision detected at time: %0d, ", + C_CORENAME, $time); + $fwrite(COLLFILE, "A %0s address: %0h, B write address: %0h\n", + wea_i ? "write" : "read", ADDRA, addrb_delay); + end + + end + + // Do the checks w/rt B + always @(posedge CLKB) begin + + // Possible collision if both are enabled and the addresses match + if (ena_i && enb_i) begin + if (wea_i || web_i) begin + is_collision_b <= collision_check(ADDRA, wea_i, ADDRB, web_i); + end else begin + is_collision_b <= 0; + end + end else begin + is_collision_b <= 0; + end + + if (ena_delay && enb_i) begin + if (wea_delay || web_i) begin + is_collision_delay_b <= collision_check(addra_delay, wea_delay, ADDRB, + web_i); + end else begin + is_collision_delay_b <= 0; + end + end else begin + is_collision_delay_b <= 0; + end + + + // Only flag if A access is a write + if (is_collision_b && wea_i) begin + $fwrite(COLLFILE, "%0s collision detected at time: %0d, ", + C_CORENAME, $time); + $fwrite(COLLFILE, "A write address: %0h, B %s address: %0h\n", + ADDRA, web_i ? "write" : "read", ADDRB); + + end else if (is_collision_delay_b && wea_delay) begin + $fwrite(COLLFILE, "%0s collision detected at time: %0d, ", + C_CORENAME, $time); + $fwrite(COLLFILE, "A write address: %0h, B %s address: %0h\n", + addra_delay, web_i ? "write" : "read", ADDRB); + end + + end + end + endgenerate + +endmodule diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/BLK_MEM_GEN_V3_2_xst.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/BLK_MEM_GEN_V3_2_xst.v new file mode 100644 index 0000000..ad7835c --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/BLK_MEM_GEN_V3_2_xst.v @@ -0,0 +1,224 @@ +/****************************************************************************** +-- (c) Copyright 2006 - 2009 Xilinx, Inc. All rights reserved. +-- +-- This file contains confidential and proprietary information +-- of Xilinx, Inc. and is protected under U.S. and +-- international copyright and other intellectual property +-- laws. +-- +-- DISCLAIMER +-- This disclaimer is not a license and does not grant any +-- rights to the materials distributed herewith. Except as +-- otherwise provided in a valid license issued to you by +-- Xilinx, and to the maximum extent permitted by applicable +-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +-- (2) Xilinx shall not be liable (whether in contract or tort, +-- including negligence, or under any other theory of +-- liability) for any loss or damage of any kind or nature +-- related to, arising under or in connection with these +-- materials, including for any direct, or any indirect, +-- special, incidental, or consequential loss or damage +-- (including loss of data, profits, goodwill, or any type of +-- loss or damage suffered as a result of any action brought +-- by a third party) even if such damage or loss was +-- reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail- +-- safe, or for use in any application requiring fail-safe +-- performance, such as life-support or safety devices or +-- systems, Class III medical devices, nuclear facilities, +-- applications related to the deployment of airbags, or any +-- other applications that could lead to death, personal +-- injury, or severe property or environmental damage +-- (individually and collectively, "Critical +-- Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical +-- Applications, subject only to applicable laws and +-- regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +-- PART OF THIS FILE AT ALL TIMES. +-- + ***************************************************************************** + * + * Filename: BLK_MEM_GEN_V3_2.v + * + * Description: + * This file is the Verilog behvarial model for the + * Block Memory Generator Core. + * + ***************************************************************************** + * Author: Xilinx + * + * History: September 6, 2005 Initial revision + *****************************************************************************/ +`timescale 1ps/1ps + +module BLK_MEM_GEN_V3_2_xst + #(parameter C_FAMILY = "virtex5", + parameter C_XDEVICEFAMILY = "virtex5", + parameter C_ELABORATION_DIR = "", + parameter C_MEM_TYPE = 2, + parameter C_BYTE_SIZE = 9, + parameter C_ALGORITHM = 1, + parameter C_PRIM_TYPE = 3, + parameter C_LOAD_INIT_FILE = 0, + parameter C_INIT_FILE_NAME = "", + parameter C_USE_DEFAULT_DATA = 0, + parameter C_DEFAULT_DATA = "0", + parameter C_RST_TYPE = "SYNC", + parameter C_HAS_RSTA = 0, + parameter C_RST_PRIORITY_A = "CE", + parameter C_RSTRAM_A = 0, + parameter C_INITA_VAL = "0", + parameter C_HAS_ENA = 1, + parameter C_HAS_REGCEA = 0, + parameter C_USE_BYTE_WEA = 0, + parameter C_WEA_WIDTH = 1, + parameter C_WRITE_MODE_A = "WRITE_FIRST", + parameter C_WRITE_WIDTH_A = 32, + parameter C_READ_WIDTH_A = 32, + parameter C_WRITE_DEPTH_A = 64, + parameter C_READ_DEPTH_A = 64, + parameter C_ADDRA_WIDTH = 5, + parameter C_HAS_RSTB = 0, + parameter C_RST_PRIORITY_B = "CE", + parameter C_RSTRAM_B = 0, + parameter C_INITB_VAL = "0", + parameter C_HAS_ENB = 1, + parameter C_HAS_REGCEB = 0, + parameter C_USE_BYTE_WEB = 0, + parameter C_WEB_WIDTH = 1, + parameter C_WRITE_MODE_B = "WRITE_FIRST", + parameter C_WRITE_WIDTH_B = 32, + parameter C_READ_WIDTH_B = 32, + parameter C_WRITE_DEPTH_B = 64, + parameter C_READ_DEPTH_B = 64, + parameter C_ADDRB_WIDTH = 5, + parameter C_HAS_MEM_OUTPUT_REGS_A = 0, + parameter C_HAS_MEM_OUTPUT_REGS_B = 0, + parameter C_HAS_MUX_OUTPUT_REGS_A = 0, + parameter C_HAS_MUX_OUTPUT_REGS_B = 0, + parameter C_MUX_PIPELINE_STAGES = 0, + parameter C_USE_ECC = 0, + parameter C_HAS_INJECTERR = 0, + parameter C_SIM_COLLISION_CHECK = "NONE", + parameter C_COMMON_CLK = 1, + parameter C_DISABLE_WARN_BHV_COLL = 0, + parameter C_DISABLE_WARN_BHV_RANGE = 0 +) + (input CLKA, + input RSTA, + input ENA, + input REGCEA, + input [C_WEA_WIDTH-1:0] WEA, + input [C_ADDRA_WIDTH-1:0] ADDRA, + input [C_WRITE_WIDTH_A-1:0] DINA, + output [C_READ_WIDTH_A-1:0] DOUTA, + input CLKB, + input RSTB, + input ENB, + input REGCEB, + input [C_WEB_WIDTH-1:0] WEB, + input [C_ADDRB_WIDTH-1:0] ADDRB, + input [C_WRITE_WIDTH_B-1:0] DINB, + output [C_READ_WIDTH_B-1:0] DOUTB, + input INJECTSBITERR, + input INJECTDBITERR, + output SBITERR, + output DBITERR, + output [C_ADDRB_WIDTH-1:0] RDADDRECC +); + + +// Note: C_ELABORATION_DIR parameter is only used in synthesis +// (and doesn't get mentioned in the instantiation template Coregen generates). +// This wrapper file has to work both in simulation and synthesis. So, this +// parameter exists. It is not used by the behavioral model +// (BLK_MEM_GEN_V3_2.vhd) + + BLK_MEM_GEN_V3_2 + #( + .C_CORENAME ("blk_mem_gen_v3_2"), + .C_FAMILY (C_FAMILY), + .C_XDEVICEFAMILY (C_XDEVICEFAMILY), + .C_MEM_TYPE (C_MEM_TYPE), + .C_BYTE_SIZE (C_BYTE_SIZE), + .C_ALGORITHM (C_ALGORITHM), + .C_PRIM_TYPE (C_PRIM_TYPE), + .C_LOAD_INIT_FILE (C_LOAD_INIT_FILE), + .C_INIT_FILE_NAME (C_INIT_FILE_NAME), + .C_USE_DEFAULT_DATA (C_USE_DEFAULT_DATA), + .C_DEFAULT_DATA (C_DEFAULT_DATA), + .C_RST_TYPE (C_RST_TYPE), + .C_HAS_RSTA (C_HAS_RSTA), + .C_RST_PRIORITY_A (C_RST_PRIORITY_A), + .C_RSTRAM_A (C_RSTRAM_A), + .C_INITA_VAL (C_INITA_VAL), + .C_HAS_ENA (C_HAS_ENA), + .C_HAS_REGCEA (C_HAS_REGCEA), + .C_USE_BYTE_WEA (C_USE_BYTE_WEA), + .C_WEA_WIDTH (C_WEA_WIDTH), + .C_WRITE_MODE_A (C_WRITE_MODE_A), + .C_WRITE_WIDTH_A (C_WRITE_WIDTH_A), + .C_READ_WIDTH_A (C_READ_WIDTH_A), + .C_WRITE_DEPTH_A (C_WRITE_DEPTH_A), + .C_READ_DEPTH_A (C_READ_DEPTH_A), + .C_ADDRA_WIDTH (C_ADDRA_WIDTH), + .C_HAS_RSTB (C_HAS_RSTB), + .C_RST_PRIORITY_B (C_RST_PRIORITY_B), + .C_RSTRAM_B (C_RSTRAM_B), + .C_INITB_VAL (C_INITB_VAL), + .C_HAS_ENB (C_HAS_ENB), + .C_HAS_REGCEB (C_HAS_REGCEB), + .C_USE_BYTE_WEB (C_USE_BYTE_WEB), + .C_WEB_WIDTH (C_WEB_WIDTH), + .C_WRITE_MODE_B (C_WRITE_MODE_B), + .C_WRITE_WIDTH_B (C_WRITE_WIDTH_B), + .C_READ_WIDTH_B (C_READ_WIDTH_B), + .C_WRITE_DEPTH_B (C_WRITE_DEPTH_B), + .C_READ_DEPTH_B (C_READ_DEPTH_B), + .C_ADDRB_WIDTH (C_ADDRB_WIDTH), + .C_HAS_MEM_OUTPUT_REGS_A (C_HAS_MEM_OUTPUT_REGS_A), + .C_HAS_MEM_OUTPUT_REGS_B (C_HAS_MEM_OUTPUT_REGS_B), + .C_HAS_MUX_OUTPUT_REGS_A (C_HAS_MUX_OUTPUT_REGS_A), + .C_HAS_MUX_OUTPUT_REGS_B (C_HAS_MUX_OUTPUT_REGS_B), + .C_MUX_PIPELINE_STAGES (C_MUX_PIPELINE_STAGES), + .C_USE_ECC (C_USE_ECC), + .C_HAS_INJECTERR (C_HAS_INJECTERR), + .C_SIM_COLLISION_CHECK (C_SIM_COLLISION_CHECK), + .C_COMMON_CLK (C_COMMON_CLK), + .C_DISABLE_WARN_BHV_COLL (C_DISABLE_WARN_BHV_COLL), + .C_DISABLE_WARN_BHV_RANGE (C_DISABLE_WARN_BHV_RANGE) + ) blk_mem_gen_v3_2_dut ( + .CLKA (CLKA), + .RSTA (RSTA), + .ENA (ENA), + .REGCEA (REGCEA), + .WEA (WEA), + .ADDRA (ADDRA), + .DINA (DINA), + .DOUTA (DOUTA), + .CLKB (CLKB), + .RSTB (RSTB), + .ENB (ENB), + .REGCEB (REGCEB), + .WEB (WEB), + .ADDRB (ADDRB), + .DINB (DINB), + .DOUTB (DOUTB), + .INJECTSBITERR (INJECTSBITERR), + .INJECTDBITERR (INJECTDBITERR), + .SBITERR (SBITERR), + .DBITERR (DBITERR), + .RDADDRECC (RDADDRECC) +); + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/BLK_MEM_GEN_V3_3.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/BLK_MEM_GEN_V3_3.v new file mode 100644 index 0000000..851f703 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/BLK_MEM_GEN_V3_3.v @@ -0,0 +1,1866 @@ +/****************************************************************************** +-- (c) Copyright 2006 - 2009 Xilinx, Inc. All rights reserved. +-- +-- This file contains confidential and proprietary information +-- of Xilinx, Inc. and is protected under U.S. and +-- international copyright and other intellectual property +-- laws. +-- +-- DISCLAIMER +-- This disclaimer is not a license and does not grant any +-- rights to the materials distributed herewith. Except as +-- otherwise provided in a valid license issued to you by +-- Xilinx, and to the maximum extent permitted by applicable +-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +-- (2) Xilinx shall not be liable (whether in contract or tort, +-- including negligence, or under any other theory of +-- liability) for any loss or damage of any kind or nature +-- related to, arising under or in connection with these +-- materials, including for any direct, or any indirect, +-- special, incidental, or consequential loss or damage +-- (including loss of data, profits, goodwill, or any type of +-- loss or damage suffered as a result of any action brought +-- by a third party) even if such damage or loss was +-- reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail- +-- safe, or for use in any application requiring fail-safe +-- performance, such as life-support or safety devices or +-- systems, Class III medical devices, nuclear facilities, +-- applications related to the deployment of airbags, or any +-- other applications that could lead to death, personal +-- injury, or severe property or environmental damage +-- (individually and collectively, "Critical +-- Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical +-- Applications, subject only to applicable laws and +-- regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +-- PART OF THIS FILE AT ALL TIMES. +-- + ***************************************************************************** + * + * Filename: BLK_MEM_GEN_V3_3.v + * + * Description: + * This file is the Verilog behvarial model for the + * Block Memory Generator Core. + * + ***************************************************************************** + * Author: Xilinx + * + * History: Jan 11, 2006 Initial revision + * Jun 11, 2007 Added independent register stages for + * Port A and Port B (IP1_Jm/v2.5) + * Aug 28, 2007 Added mux pipeline stages feature (IP2_Jm/v2.6) + * Mar 13, 2008 Behavioral model optimizations + * April 07, 2009 : Added support for Spartan-6 and Virtex-6 + * features, including the following: + * (i) error injection, detection and/or correction + * (ii) reset priority + * (iii) special reset behavior + * + *****************************************************************************/ +`timescale 1ps/1ps + +//***************************************************************************** +// Output Register Stage module +// +// This module builds the output register stages of the memory. This module is +// instantiated in the main memory module (BLK_MEM_GEN_V3_3) which is +// declared/implemented further down in this file. +//***************************************************************************** + +module BLK_MEM_GEN_V3_3_output_stage + #(parameter C_FAMILY = "virtex5", + parameter C_XDEVICEFAMILY = "virtex5", + parameter C_RST_TYPE = "SYNC", + parameter C_HAS_RST = 0, + parameter C_RSTRAM = 0, + parameter C_RST_PRIORITY = "CE", + parameter C_INIT_VAL = "0", + parameter C_HAS_EN = 0, + parameter C_HAS_REGCE = 0, + parameter C_DATA_WIDTH = 32, + parameter C_ADDRB_WIDTH = 10, + parameter C_HAS_MEM_OUTPUT_REGS = 0, + parameter C_USE_ECC = 0, + parameter NUM_STAGES = 1, + parameter FLOP_DELAY = 100 + ) + ( + input CLK, + input RST, + input EN, + input REGCE, + input [C_DATA_WIDTH-1:0] DIN, + output reg [C_DATA_WIDTH-1:0] DOUT, + input SBITERR_IN, + input DBITERR_IN, + output reg SBITERR, + output reg DBITERR, + input [C_ADDRB_WIDTH-1:0] RDADDRECC_IN, + output reg [C_ADDRB_WIDTH-1:0] RDADDRECC +); + +//****************************** +// Port and Generic Definitions +//****************************** + //------------------------------------------------------------------------- + // Generic Definitions + //------------------------------------------------------------------------- + // C_FAMILY,C_XDEVICEFAMILY: Designates architecture targeted. The following + // options are available - "spartan3", "spartan6", + // "virtex4", "virtex5", "virtex6" and "virtex6l". + // C_RST_TYPE : Type of reset - Synchronous or Asynchronous + // C_HAS_RST : Determines the presence of the RST port + // C_RSTRAM : Determines if special reset behavior is used + // C_RST_PRIORITY : Determines the priority between CE and SR + // C_INIT_VAL : Initialization value + // C_HAS_EN : Determines the presence of the EN port + // C_HAS_REGCE : Determines the presence of the REGCE port + // C_DATA_WIDTH : Memory write/read width + // C_ADDRB_WIDTH : Width of the ADDRB input port + // C_HAS_MEM_OUTPUT_REGS : Designates the use of a register at the output + // of the RAM primitive + // C_USE_ECC : Determines if the ECC feature is used or + // not. Only applicable for V5 and V6 + // NUM_STAGES : Determines the number of output stages + // FLOP_DELAY : Constant delay for register assignments + //------------------------------------------------------------------------- + // Port Definitions + //------------------------------------------------------------------------- + // CLK : Clock to synchronize all read and write operations + // RST : Reset input to reset memory outputs to a user-defined + // reset state + // EN : Enable all read and write operations + // REGCE : Register Clock Enable to control each pipeline output + // register stages + // DIN : Data input to the Output stage. + // DOUT : Final Data output + // SBITERR_IN : SBITERR input signal to the Output stage. + // SBITERR : Final SBITERR Output signal. + // DBITERR_IN : DBITERR input signal to the Output stage. + // DBITERR : Final DBITERR Output signal. + // RDADDRECC_IN : RDADDRECC input signal to the Output stage. + // RDADDRECC : Final RDADDRECC Output signal. + //------------------------------------------------------------------------- + +// Fix for CR-509792 +// localparam REG_STAGES = (NUM_STAGES == 0) ? 0 : NUM_STAGES-1; + localparam REG_STAGES = (NUM_STAGES < 2) ? 1 : NUM_STAGES-1; + + // Declare the pipeline registers + // (includes mem output reg, mux pipeline stages, and mux output reg) + reg [C_DATA_WIDTH*REG_STAGES-1:0] out_regs; + reg [C_ADDRB_WIDTH*REG_STAGES-1:0] rdaddrecc_regs; + reg [REG_STAGES-1:0] sbiterr_regs; + reg [REG_STAGES-1:0] dbiterr_regs; + + reg [C_DATA_WIDTH*8-1:0] init_str = C_INIT_VAL; + reg [C_DATA_WIDTH-1:0] init_val; + + //********************************************* + // Wire off optional inputs based on parameters + //********************************************* + wire en_i; + wire regce_i; + wire rst_i; + + // Internal enable for output registers is tied to user EN or '1' depending + // on parameters + assign en_i = (C_HAS_EN==0 || EN); + + // Internal register enable for output registers is tied to user REGCE, EN or + // '1' depending on parameters + // For V4 ECC, REGCE is always 1 + // Virtex-4 ECC Not Yet Supported + assign regce_i = ((C_HAS_REGCE==1) && REGCE) || + ((C_HAS_REGCE==0) && (C_HAS_EN==0 || EN)); + + //Internal SRR is tied to user RST or '0' depending on parameters + assign rst_i = (C_HAS_RST==1) && RST; + + //**************************************************** + // Power on: load up the output registers and latches + //**************************************************** + initial begin + if (!($sscanf(init_str, "%h", init_val))) begin + init_val = 0; + end + DOUT = init_val; + RDADDRECC = 0; + SBITERR = 1'b0; + DBITERR = 1'b0; + // This will be one wider than need, but 0 is an error + out_regs = {(REG_STAGES+1){init_val}}; + rdaddrecc_regs = 0; + sbiterr_regs = {(REG_STAGES+1){1'b0}}; + dbiterr_regs = {(REG_STAGES+1){1'b0}}; + end + + //*********************************************** + // NUM_STAGES = 0 (No output registers. RAM only) + //*********************************************** + generate if (NUM_STAGES == 0) begin : zero_stages + always @* begin + DOUT = DIN; + RDADDRECC = RDADDRECC_IN; + SBITERR = SBITERR_IN; + DBITERR = DBITERR_IN; + end + end + endgenerate + + //*********************************************** + // NUM_STAGES = 1 + // (Mem Output Reg only or Mux Output Reg only) + //*********************************************** + + // Possible valid combinations: + // Note: C_HAS_MUX_OUTPUT_REGS_*=0 when (C_RSTRAM_*=1) + // +-----------------------------------------+ + // | C_RSTRAM_* | Reset Behavior | + // +----------------+------------------------+ + // | 0 | Normal Behavior | + // +----------------+------------------------+ + // | 1 | Special Behavior | + // +----------------+------------------------+ + // + // Normal = REGCE gates reset, as in the case of all families except S3ADSP. + // Special = EN gates reset, as in the case of S3ADSP. + + generate if (NUM_STAGES == 1 && + (C_RSTRAM == 0 || (C_RSTRAM == 1 && (C_XDEVICEFAMILY != "spartan3adsp" && C_XDEVICEFAMILY != "aspartan3adsp" )) || + C_HAS_MEM_OUTPUT_REGS == 0 || C_HAS_RST == 0)) + begin : one_stages_norm + //Asynchronous Reset + if ((C_FAMILY == "spartan6" || C_FAMILY == "spartan6l" || C_FAMILY == "aspartan6") && C_RST_TYPE == "ASYNC") begin + if(C_RST_PRIORITY == "CE") begin //REGCE has priority + always @ (*) begin + if (rst_i && regce_i) DOUT = init_val; + end + always @ (posedge CLK) begin + if (!rst_i && regce_i) DOUT <= #FLOP_DELAY DIN; + end //CLK + end else begin //RST has priority + always @ (*) begin + if (rst_i) DOUT = init_val; + end + always @ (posedge CLK) begin + if (!rst_i && regce_i) DOUT <= #FLOP_DELAY DIN; + end //CLK + end //end Priority conditions + //Synchronous Reset + end else begin + always @(posedge CLK) begin + if (C_RST_PRIORITY == "CE") begin //REGCE has priority + if (regce_i && rst_i) begin + DOUT <= #FLOP_DELAY init_val; + RDADDRECC <= #FLOP_DELAY 0; + SBITERR <= #FLOP_DELAY 1'b0; + DBITERR <= #FLOP_DELAY 1'b0; + end else if (regce_i) begin + DOUT <= #FLOP_DELAY DIN; + RDADDRECC <= #FLOP_DELAY RDADDRECC_IN; + SBITERR <= #FLOP_DELAY SBITERR_IN; + DBITERR <= #FLOP_DELAY DBITERR_IN; + end //Output signal assignments + end else begin //RST has priority + if (rst_i) begin + DOUT <= #FLOP_DELAY init_val; + RDADDRECC <= #FLOP_DELAY RDADDRECC_IN; + SBITERR <= #FLOP_DELAY 1'b0; + DBITERR <= #FLOP_DELAY 1'b0; + end else if (regce_i) begin + DOUT <= #FLOP_DELAY DIN; + RDADDRECC <= #FLOP_DELAY RDADDRECC_IN; + SBITERR <= #FLOP_DELAY SBITERR_IN; + DBITERR <= #FLOP_DELAY DBITERR_IN; + end //Output signal assignments + end //end Priority conditions + end //CLK + end //end RST Type conditions + end //end one_stages_norm generate statement + endgenerate + + // Special Reset Behavior for S3ADSP + generate if (NUM_STAGES == 1 && C_RSTRAM == 1 && (C_XDEVICEFAMILY =="spartan3adsp" || C_XDEVICEFAMILY =="aspartan3adsp")) + begin : one_stage_splbhv + always @(posedge CLK) begin + if (en_i && rst_i) begin + DOUT <= #FLOP_DELAY init_val; + end else if (regce_i && !rst_i) begin + DOUT <= #FLOP_DELAY DIN; + end //Output signal assignments + end //end CLK + end //end one_stage_splbhv generate statement + endgenerate + + //************************************************************ + // NUM_STAGES > 1 + // Mem Output Reg + Mux Output Reg + // or + // Mem Output Reg + Mux Pipeline Stages (>0) + Mux Output Reg + // or + // Mux Pipeline Stages (>0) + Mux Output Reg + //************************************************************* + generate if (NUM_STAGES > 1) begin : multi_stage + //Asynchronous Reset + if ((C_FAMILY == "spartan6" || C_FAMILY == "spartan6l" || C_FAMILY == "aspartan6") && C_RST_TYPE == "ASYNC") begin + if(C_RST_PRIORITY == "CE") begin //REGCE has priority + always @ (*) begin + if (rst_i && regce_i) DOUT = init_val; + end + always @ (posedge CLK) begin + if (!rst_i && regce_i) + DOUT <= #FLOP_DELAY out_regs[C_DATA_WIDTH*(NUM_STAGES-2)+:C_DATA_WIDTH]; + end //CLK + end else begin //RST has priority + always @ (*) begin + if (rst_i) DOUT = init_val; + end + always @ (posedge CLK) begin + if (!rst_i && regce_i) + DOUT <= #FLOP_DELAY out_regs[C_DATA_WIDTH*(NUM_STAGES-2)+:C_DATA_WIDTH]; + end //CLK + end //end Priority conditions + always @ (posedge CLK) begin + if (en_i) begin + out_regs <= (out_regs << C_DATA_WIDTH) | DIN; + end + end + //Synchronous Reset + end else begin + always @(posedge CLK) begin + if (C_RST_PRIORITY == "CE") begin //REGCE has priority + if (regce_i && rst_i) begin + DOUT <= #FLOP_DELAY init_val; + RDADDRECC <= #FLOP_DELAY 0; + SBITERR <= #FLOP_DELAY 1'b0; + DBITERR <= #FLOP_DELAY 1'b0; + end else if (regce_i) begin + DOUT <= #FLOP_DELAY + out_regs[C_DATA_WIDTH*(NUM_STAGES-2)+:C_DATA_WIDTH]; + RDADDRECC <= #FLOP_DELAY rdaddrecc_regs[C_ADDRB_WIDTH*(NUM_STAGES-2)+:C_ADDRB_WIDTH]; + SBITERR <= #FLOP_DELAY sbiterr_regs[NUM_STAGES-2]; + DBITERR <= #FLOP_DELAY dbiterr_regs[NUM_STAGES-2]; + end //Output signal assignments + end else begin //RST has priority + if (rst_i) begin + DOUT <= #FLOP_DELAY init_val; + RDADDRECC <= #FLOP_DELAY 0; + SBITERR <= #FLOP_DELAY 1'b0; + DBITERR <= #FLOP_DELAY 1'b0; + end else if (regce_i) begin + DOUT <= #FLOP_DELAY + out_regs[C_DATA_WIDTH*(NUM_STAGES-2)+:C_DATA_WIDTH]; + RDADDRECC <= #FLOP_DELAY rdaddrecc_regs[C_ADDRB_WIDTH*(NUM_STAGES-2)+:C_ADDRB_WIDTH]; + SBITERR <= #FLOP_DELAY sbiterr_regs[NUM_STAGES-2]; + DBITERR <= #FLOP_DELAY dbiterr_regs[NUM_STAGES-2]; + end //Output signal assignments + end //end Priority conditions + // Shift the data through the output stages + if (en_i) begin + out_regs <= #FLOP_DELAY (out_regs << C_DATA_WIDTH) | DIN; + rdaddrecc_regs <= #FLOP_DELAY (rdaddrecc_regs << C_ADDRB_WIDTH) | RDADDRECC_IN; + sbiterr_regs <= #FLOP_DELAY (sbiterr_regs << 1) | SBITERR_IN; + dbiterr_regs <= #FLOP_DELAY (dbiterr_regs << 1) | DBITERR_IN; + end + end //end CLK + end //end RST Type conditions + end //end multi_stage generate statement + endgenerate +endmodule + + +//***************************************************************************** +// Main Memory module +// +// This module is the top-level behavioral model and this implements the RAM +//***************************************************************************** +module BLK_MEM_GEN_V3_3 + #(parameter C_CORENAME = "blk_mem_gen_v3_3", + parameter C_FAMILY = "virtex6", + parameter C_XDEVICEFAMILY = "virtex6", + parameter C_MEM_TYPE = 2, + parameter C_BYTE_SIZE = 9, + parameter C_ALGORITHM = 1, + parameter C_PRIM_TYPE = 3, + parameter C_LOAD_INIT_FILE = 0, + parameter C_INIT_FILE_NAME = "", + parameter C_USE_DEFAULT_DATA = 0, + parameter C_DEFAULT_DATA = "0", + parameter C_RST_TYPE = "SYNC", + parameter C_HAS_RSTA = 0, + parameter C_RST_PRIORITY_A = "CE", + parameter C_RSTRAM_A = 0, + parameter C_INITA_VAL = "0", + parameter C_HAS_ENA = 1, + parameter C_HAS_REGCEA = 0, + parameter C_USE_BYTE_WEA = 0, + parameter C_WEA_WIDTH = 1, + parameter C_WRITE_MODE_A = "WRITE_FIRST", + parameter C_WRITE_WIDTH_A = 32, + parameter C_READ_WIDTH_A = 32, + parameter C_WRITE_DEPTH_A = 64, + parameter C_READ_DEPTH_A = 64, + parameter C_ADDRA_WIDTH = 5, + parameter C_HAS_RSTB = 0, + parameter C_RST_PRIORITY_B = "CE", + parameter C_RSTRAM_B = 0, + parameter C_INITB_VAL = "0", + parameter C_HAS_ENB = 1, + parameter C_HAS_REGCEB = 0, + parameter C_USE_BYTE_WEB = 0, + parameter C_WEB_WIDTH = 1, + parameter C_WRITE_MODE_B = "WRITE_FIRST", + parameter C_WRITE_WIDTH_B = 32, + parameter C_READ_WIDTH_B = 32, + parameter C_WRITE_DEPTH_B = 64, + parameter C_READ_DEPTH_B = 64, + parameter C_ADDRB_WIDTH = 5, + parameter C_HAS_MEM_OUTPUT_REGS_A = 0, + parameter C_HAS_MEM_OUTPUT_REGS_B = 0, + parameter C_HAS_MUX_OUTPUT_REGS_A = 0, + parameter C_HAS_MUX_OUTPUT_REGS_B = 0, + parameter C_MUX_PIPELINE_STAGES = 0, + parameter C_USE_ECC = 0, + parameter C_HAS_INJECTERR = 0, + parameter C_SIM_COLLISION_CHECK = "NONE", + parameter C_COMMON_CLK = 1, + parameter C_DISABLE_WARN_BHV_COLL = 0, + parameter C_DISABLE_WARN_BHV_RANGE = 0 + ) + (input CLKA, + input RSTA, + input ENA, + input REGCEA, + input [C_WEA_WIDTH-1:0] WEA, + input [C_ADDRA_WIDTH-1:0] ADDRA, + input [C_WRITE_WIDTH_A-1:0] DINA, + output [C_READ_WIDTH_A-1:0] DOUTA, + input CLKB, + input RSTB, + input ENB, + input REGCEB, + input [C_WEB_WIDTH-1:0] WEB, + input [C_ADDRB_WIDTH-1:0] ADDRB, + input [C_WRITE_WIDTH_B-1:0] DINB, + output [C_READ_WIDTH_B-1:0] DOUTB, + input INJECTSBITERR, + input INJECTDBITERR, + output SBITERR, + output DBITERR, + output [C_ADDRB_WIDTH-1:0] RDADDRECC + ); +//****************************** +// Port and Generic Definitions +//****************************** + //------------------------------------------------------------------------- + // Generic Definitions + //------------------------------------------------------------------------- + // C_CORENAME : Instance name of the Block Memory Generator core + // C_FAMILY,C_XDEVICEFAMILY: Designates architecture targeted. The following + // options are available - "spartan3", "spartan6", + // "virtex4", "virtex5", "virtex6" and "virtex6l". + // C_MEM_TYPE : Designates memory type. + // It can be + // 0 - Single Port Memory + // 1 - Simple Dual Port Memory + // 2 - True Dual Port Memory + // 3 - Single Port Read Only Memory + // 4 - Dual Port Read Only Memory + // C_BYTE_SIZE : Size of a byte (8 or 9 bits) + // C_ALGORITHM : Designates the algorithm method used + // for constructing the memory. + // It can be Fixed_Primitives, Minimum_Area or + // Low_Power + // C_PRIM_TYPE : Designates the user selected primitive used to + // construct the memory. + // + // C_LOAD_INIT_FILE : Designates the use of an initialization file to + // initialize memory contents. + // C_INIT_FILE_NAME : Memory initialization file name. + // C_USE_DEFAULT_DATA : Designates whether to fill remaining + // initialization space with default data + // C_DEFAULT_DATA : Default value of all memory locations + // not initialized by the memory + // initialization file. + // C_RST_TYPE : Type of reset - Synchronous or Asynchronous + // C_HAS_RSTA : Determines the presence of the RSTA port + // C_RST_PRIORITY_A : Determines the priority between CE and SR for + // Port A. + // C_RSTRAM_A : Determines if special reset behavior is used for + // Port A + // C_INITA_VAL : The initialization value for Port A + // C_HAS_ENA : Determines the presence of the ENA port + // C_HAS_REGCEA : Determines the presence of the REGCEA port + // C_USE_BYTE_WEA : Determines if the Byte Write is used or not. + // C_WEA_WIDTH : The width of the WEA port + // C_WRITE_MODE_A : Configurable write mode for Port A. It can be + // WRITE_FIRST, READ_FIRST or NO_CHANGE. + // C_WRITE_WIDTH_A : Memory write width for Port A. + // C_READ_WIDTH_A : Memory read width for Port A. + // C_WRITE_DEPTH_A : Memory write depth for Port A. + // C_READ_DEPTH_A : Memory read depth for Port A. + // C_ADDRA_WIDTH : Width of the ADDRA input port + // C_HAS_RSTB : Determines the presence of the RSTB port + // C_RST_PRIORITY_B : Determines the priority between CE and SR for + // Port B. + // C_RSTRAM_B : Determines if special reset behavior is used for + // Port B + // C_INITB_VAL : The initialization value for Port B + // C_HAS_ENB : Determines the presence of the ENB port + // C_HAS_REGCEB : Determines the presence of the REGCEB port + // C_USE_BYTE_WEB : Determines if the Byte Write is used or not. + // C_WEB_WIDTH : The width of the WEB port + // C_WRITE_MODE_B : Configurable write mode for Port B. It can be + // WRITE_FIRST, READ_FIRST or NO_CHANGE. + // C_WRITE_WIDTH_B : Memory write width for Port B. + // C_READ_WIDTH_B : Memory read width for Port B. + // C_WRITE_DEPTH_B : Memory write depth for Port B. + // C_READ_DEPTH_B : Memory read depth for Port B. + // C_ADDRB_WIDTH : Width of the ADDRB input port + // C_HAS_MEM_OUTPUT_REGS_A : Designates the use of a register at the output + // of the RAM primitive for Port A. + // C_HAS_MEM_OUTPUT_REGS_B : Designates the use of a register at the output + // of the RAM primitive for Port B. + // C_HAS_MUX_OUTPUT_REGS_A : Designates the use of a register at the output + // of the MUX for Port A. + // C_HAS_MUX_OUTPUT_REGS_B : Designates the use of a register at the output + // of the MUX for Port B. + // C_MUX_PIPELINE_STAGES : Designates the number of pipeline stages in + // between the muxes. + // C_USE_ECC : Determines if the ECC feature is used or + // not. Only applicable for V5 and V6 + // C_HAS_INJECTERR : Determines if the error injection pins + // are present or not. If the ECC feature + // is not used, this value is defaulted to + // 0, else the following are the allowed + // values: + // 0 : No INJECTSBITERR or INJECTDBITERR pins + // 1 : Only INJECTSBITERR pin exists + // 2 : Only INJECTDBITERR pin exists + // 3 : Both INJECTSBITERR and INJECTDBITERR pins exist + // C_SIM_COLLISION_CHECK : Controls the disabling of Unisim model collision + // warnings. It can be "ALL", "NONE", + // "Warnings_Only" or "Generate_X_Only". + // C_COMMON_CLK : Determins if the core has a single CLK input. + // C_DISABLE_WARN_BHV_COLL : Controls the Behavioral Model Collision warnings + // C_DISABLE_WARN_BHV_RANGE: Controls the Behavioral Model Out of Range + // warnings + //------------------------------------------------------------------------- + // Port Definitions + //------------------------------------------------------------------------- + // CLKA : Clock to synchronize all read and write operations of Port A. + // RSTA : Reset input to reset memory outputs to a user-defined + // reset state for Port A. + // ENA : Enable all read and write operations of Port A. + // REGCEA : Register Clock Enable to control each pipeline output + // register stages for Port A. + // WEA : Write Enable to enable all write operations of Port A. + // ADDRA : Address of Port A. + // DINA : Data input of Port A. + // DOUTA : Data output of Port A. + // CLKB : Clock to synchronize all read and write operations of Port B. + // RSTB : Reset input to reset memory outputs to a user-defined + // reset state for Port B. + // ENB : Enable all read and write operations of Port B. + // REGCEB : Register Clock Enable to control each pipeline output + // register stages for Port B. + // WEB : Write Enable to enable all write operations of Port B. + // ADDRB : Address of Port B. + // DINB : Data input of Port B. + // DOUTB : Data output of Port B. + // INJECTSBITERR : Single Bit ECC Error Injection Pin. + // INJECTDBITERR : Double Bit ECC Error Injection Pin. + // SBITERR : Output signal indicating that a Single Bit ECC Error has been + // detected and corrected. + // DBITERR : Output signal indicating that a Double Bit ECC Error has been + // detected. + // RDADDRECC : Read Address Output signal indicating address at which an + // ECC error has occurred. + //------------------------------------------------------------------------- + + +// Note: C_CORENAME parameter is hard-coded to "blk_mem_gen_v3_3" and it is +// only used by this module to print warning messages. It is neither passed +// down from blk_mem_gen_v3_3_xst.v nor present in the instantiation template +// coregen generates + + //*************************************************************************** + // constants for the core behavior + //*************************************************************************** + // file handles for logging + //-------------------------------------------------- + localparam ADDRFILE = 32'h8000_0001; //stdout for addr out of range + localparam COLLFILE = 32'h8000_0001; //stdout for coll detection + localparam ERRFILE = 32'h8000_0001; //stdout for file I/O errors + + // other constants + //-------------------------------------------------- + localparam COLL_DELAY = 2000; // 2 ns + + // locally derived parameters to determine memory shape + //----------------------------------------------------- + localparam MIN_WIDTH_A = (C_WRITE_WIDTH_A < C_READ_WIDTH_A) ? + C_WRITE_WIDTH_A : C_READ_WIDTH_A; + localparam MIN_WIDTH_B = (C_WRITE_WIDTH_B < C_READ_WIDTH_B) ? + C_WRITE_WIDTH_B : C_READ_WIDTH_B; + localparam MIN_WIDTH = (MIN_WIDTH_A < MIN_WIDTH_B) ? + MIN_WIDTH_A : MIN_WIDTH_B; + + localparam MAX_DEPTH_A = (C_WRITE_DEPTH_A > C_READ_DEPTH_A) ? + C_WRITE_DEPTH_A : C_READ_DEPTH_A; + localparam MAX_DEPTH_B = (C_WRITE_DEPTH_B > C_READ_DEPTH_B) ? + C_WRITE_DEPTH_B : C_READ_DEPTH_B; + localparam MAX_DEPTH = (MAX_DEPTH_A > MAX_DEPTH_B) ? + MAX_DEPTH_A : MAX_DEPTH_B; + + + // locally derived parameters to assist memory access + //---------------------------------------------------- + // Calculate the width ratios of each port with respect to the narrowest + // port + localparam WRITE_WIDTH_RATIO_A = C_WRITE_WIDTH_A/MIN_WIDTH; + localparam READ_WIDTH_RATIO_A = C_READ_WIDTH_A/MIN_WIDTH; + localparam WRITE_WIDTH_RATIO_B = C_WRITE_WIDTH_B/MIN_WIDTH; + localparam READ_WIDTH_RATIO_B = C_READ_WIDTH_B/MIN_WIDTH; + + // To modify the LSBs of the 'wider' data to the actual + // address value + //---------------------------------------------------- + localparam WRITE_ADDR_A_DIV = C_WRITE_WIDTH_A/MIN_WIDTH_A; + localparam READ_ADDR_A_DIV = C_READ_WIDTH_A/MIN_WIDTH_A; + localparam WRITE_ADDR_B_DIV = C_WRITE_WIDTH_B/MIN_WIDTH_B; + localparam READ_ADDR_B_DIV = C_READ_WIDTH_B/MIN_WIDTH_B; + + // If byte writes aren't being used, make sure BYTE_SIZE is not + // wider than the memory elements to avoid compilation warnings + localparam BYTE_SIZE = (C_BYTE_SIZE < MIN_WIDTH) ? C_BYTE_SIZE : MIN_WIDTH; + + // The memory + reg [MIN_WIDTH-1:0] memory [0:MAX_DEPTH-1]; + // ECC error arrays + reg sbiterr_arr [0:MAX_DEPTH-1]; + reg dbiterr_arr [0:MAX_DEPTH-1]; + + // Memory output 'latches' + reg [C_READ_WIDTH_A-1:0] memory_out_a; + reg [C_READ_WIDTH_B-1:0] memory_out_b; + + // ECC error inputs and outputs from output_stage module: + reg sbiterr_in; + wire sbiterr_sdp; + reg dbiterr_in; + wire dbiterr_sdp; + + reg [C_ADDRB_WIDTH-1:0] rdaddrecc_in; + wire [C_ADDRB_WIDTH-1:0] rdaddrecc_sdp; + + // Reset values + reg [C_READ_WIDTH_A-1:0] inita_val; + reg [C_READ_WIDTH_B-1:0] initb_val; + + // Collision detect + reg is_collision; + reg is_collision_a, is_collision_delay_a; + reg is_collision_b, is_collision_delay_b; + + // Temporary variables for initialization + //--------------------------------------- + integer status; + integer initfile; + // data input buffer + reg [C_WRITE_WIDTH_A-1:0] mif_data; + // string values in hex + reg [C_READ_WIDTH_A*8-1:0] inita_str = C_INITA_VAL; + reg [C_READ_WIDTH_B*8-1:0] initb_str = C_INITB_VAL; + reg [C_WRITE_WIDTH_A*8-1:0] default_data_str = C_DEFAULT_DATA; + // initialization filename + reg [1023*8-1:0] init_file_str = C_INIT_FILE_NAME; + + + //Constants used to calculate the effective address widths for each of the + //four ports. + integer cnt = 1; + integer write_addr_a_width, read_addr_a_width; + integer write_addr_b_width, read_addr_b_width; + + + // Internal configuration parameters + //--------------------------------------------- + localparam FLOP_DELAY = 100; // 100 ps + localparam SINGLE_PORT = (C_MEM_TYPE==0 || C_MEM_TYPE==3); + localparam IS_ROM = (C_MEM_TYPE==3 || C_MEM_TYPE==4); + localparam HAS_A_WRITE = (!IS_ROM); + localparam HAS_B_WRITE = (C_MEM_TYPE==2); + localparam HAS_A_READ = (C_MEM_TYPE!=1); + localparam HAS_B_READ = (!SINGLE_PORT); + localparam HAS_B_PORT = (HAS_B_READ || HAS_B_WRITE); + + // Calculate the mux pipeline register stages for Port A and Port B + //------------------------------------------------------------------ + localparam MUX_PIPELINE_STAGES_A = (C_HAS_MUX_OUTPUT_REGS_A) ? + C_MUX_PIPELINE_STAGES : 0; + localparam MUX_PIPELINE_STAGES_B = (C_HAS_MUX_OUTPUT_REGS_B) ? + C_MUX_PIPELINE_STAGES : 0; + + // Calculate total number of register stages in the core + // ----------------------------------------------------- + localparam NUM_OUTPUT_STAGES_A = (C_HAS_MEM_OUTPUT_REGS_A+MUX_PIPELINE_STAGES_A+C_HAS_MUX_OUTPUT_REGS_A); + + localparam NUM_OUTPUT_STAGES_B = (C_HAS_MEM_OUTPUT_REGS_B+MUX_PIPELINE_STAGES_B+C_HAS_MUX_OUTPUT_REGS_B); + + wire ena_i; + wire enb_i; + wire reseta_i; + wire resetb_i; + wire [C_WEA_WIDTH-1:0] wea_i; + wire [C_WEB_WIDTH-1:0] web_i; + wire rea_i; + wire reb_i; + + // ECC SBITERR/DBITERR Outputs + // The ECC Behavior is modeled by the behavioral models only for Virtex-6. + // For Virtex-5, these outputs will be tied to 0. + assign SBITERR = (C_MEM_TYPE == 1 && C_USE_ECC == 1)?sbiterr_sdp:0; + assign DBITERR = (C_MEM_TYPE == 1 && C_USE_ECC == 1)?dbiterr_sdp:0; + assign RDADDRECC = ((C_FAMILY == "virtex6" || C_FAMILY == "virtex6l") && C_MEM_TYPE == 1 && C_USE_ECC == 1)?rdaddrecc_sdp:0; + + + // This effectively wires off optional inputs + assign ena_i = (C_HAS_ENA==0) || ENA; + assign enb_i = ((C_HAS_ENB==0) || ENB) && HAS_B_PORT; + assign wea_i = (HAS_A_WRITE && ena_i) ? WEA : 'b0; + assign web_i = (HAS_B_WRITE && enb_i) ? WEB : 'b0; + assign rea_i = (HAS_A_READ) ? ena_i : 'b0; + assign reb_i = (HAS_B_READ) ? enb_i : 'b0; + + // These signals reset the memory latches + + assign reseta_i = + ((C_HAS_RSTA==1 && RSTA && NUM_OUTPUT_STAGES_A==0) || + (C_HAS_RSTA==1 && RSTA && C_RSTRAM_A==1)); + + assign resetb_i = + ((C_HAS_RSTB==1 && RSTB && NUM_OUTPUT_STAGES_B==0) || + (C_HAS_RSTB==1 && RSTB && C_RSTRAM_B==1)); + + // Tasks to access the memory + //--------------------------- + //************** + // write_a + //************** + task write_a + (input reg [C_ADDRA_WIDTH-1:0] addr, + input reg [C_WEA_WIDTH-1:0] byte_en, + input reg [C_WRITE_WIDTH_A-1:0] data, + input inj_sbiterr, + input inj_dbiterr); + reg [C_WRITE_WIDTH_A-1:0] current_contents; + reg [C_ADDRA_WIDTH-1:0] address; + integer i; + begin + // Shift the address by the ratio + address = (addr/WRITE_ADDR_A_DIV); + if (address >= C_WRITE_DEPTH_A) begin + if (!C_DISABLE_WARN_BHV_RANGE) begin + $fdisplay(ADDRFILE, + "%0s WARNING: Address %0h is outside range for A Write", + C_CORENAME, addr); + end + + // valid address + end else begin + + // Combine w/ byte writes + if (C_USE_BYTE_WEA) begin + + // Get the current memory contents + if (WRITE_WIDTH_RATIO_A == 1) begin + // Workaround for IUS 5.5 part-select issue + current_contents = memory[address]; + end else begin + for (i = 0; i < WRITE_WIDTH_RATIO_A; i = i + 1) begin + current_contents[MIN_WIDTH*i+:MIN_WIDTH] + = memory[address*WRITE_WIDTH_RATIO_A + i]; + end + end + + // Apply incoming bytes + if (C_WEA_WIDTH == 1) begin + // Workaround for IUS 5.5 part-select issue + if (byte_en[0]) begin + current_contents = data; + end + end else begin + for (i = 0; i < C_WEA_WIDTH; i = i + 1) begin + if (byte_en[i]) begin + current_contents[BYTE_SIZE*i+:BYTE_SIZE] + = data[BYTE_SIZE*i+:BYTE_SIZE]; + end + end + end + + // No byte-writes, overwrite the whole word + end else begin + current_contents = data; + end + + // Insert double bit errors: + if (C_USE_ECC == 1) begin + if ((C_HAS_INJECTERR == 2 || C_HAS_INJECTERR == 3) && inj_dbiterr == 1'b1) begin + current_contents[0] = !(current_contents[0]); + current_contents[1] = !(current_contents[1]); + end + end + + // Write data to memory + if (WRITE_WIDTH_RATIO_A == 1) begin + // Workaround for IUS 5.5 part-select issue + memory[address*WRITE_WIDTH_RATIO_A] = current_contents; + end else begin + for (i = 0; i < WRITE_WIDTH_RATIO_A; i = i + 1) begin + memory[address*WRITE_WIDTH_RATIO_A + i] + = current_contents[MIN_WIDTH*i+:MIN_WIDTH]; + end + end + + // Store the address at which error is injected: + if ((C_FAMILY == "virtex6" || C_FAMILY == "virtex6l") && C_USE_ECC == 1) begin + if ((C_HAS_INJECTERR == 1 && inj_sbiterr == 1'b1) || + (C_HAS_INJECTERR == 3 && inj_sbiterr == 1'b1 && inj_dbiterr != 1'b1)) + begin + sbiterr_arr[addr] = 1; + end else begin + sbiterr_arr[addr] = 0; + end + + if ((C_HAS_INJECTERR == 2 || C_HAS_INJECTERR == 3) && inj_dbiterr == 1'b1) begin + dbiterr_arr[addr] = 1; + end else begin + dbiterr_arr[addr] = 0; + end + end + + end + end + endtask + + //************** + // write_b + //************** + task write_b + (input reg [C_ADDRB_WIDTH-1:0] addr, + input reg [C_WEB_WIDTH-1:0] byte_en, + input reg [C_WRITE_WIDTH_B-1:0] data); + reg [C_WRITE_WIDTH_B-1:0] current_contents; + reg [C_ADDRB_WIDTH-1:0] address; + integer i; + begin + // Shift the address by the ratio + address = (addr/WRITE_ADDR_B_DIV); + if (address >= C_WRITE_DEPTH_B) begin + if (!C_DISABLE_WARN_BHV_RANGE) begin + $fdisplay(ADDRFILE, + "%0s WARNING: Address %0h is outside range for B Write", + C_CORENAME, addr); + end + + // valid address + end else begin + + // Combine w/ byte writes + if (C_USE_BYTE_WEB) begin + + // Get the current memory contents + if (WRITE_WIDTH_RATIO_B == 1) begin + // Workaround for IUS 5.5 part-select issue + current_contents = memory[address]; + end else begin + for (i = 0; i < WRITE_WIDTH_RATIO_B; i = i + 1) begin + current_contents[MIN_WIDTH*i+:MIN_WIDTH] + = memory[address*WRITE_WIDTH_RATIO_B + i]; + end + end + + // Apply incoming bytes + if (C_WEB_WIDTH == 1) begin + // Workaround for IUS 5.5 part-select issue + if (byte_en[0]) begin + current_contents = data; + end + end else begin + for (i = 0; i < C_WEB_WIDTH; i = i + 1) begin + if (byte_en[i]) begin + current_contents[BYTE_SIZE*i+:BYTE_SIZE] + = data[BYTE_SIZE*i+:BYTE_SIZE]; + end + end + end + + // No byte-writes, overwrite the whole word + end else begin + current_contents = data; + end + + // Write data to memory + if (WRITE_WIDTH_RATIO_B == 1) begin + // Workaround for IUS 5.5 part-select issue + memory[address*WRITE_WIDTH_RATIO_B] = current_contents; + end else begin + for (i = 0; i < WRITE_WIDTH_RATIO_B; i = i + 1) begin + memory[address*WRITE_WIDTH_RATIO_B + i] + = current_contents[MIN_WIDTH*i+:MIN_WIDTH]; + end + end + end + end + endtask + + //************** + // read_a + //************** + task read_a + (input reg [C_ADDRA_WIDTH-1:0] addr, + input reg reset); + reg [C_ADDRA_WIDTH-1:0] address; + integer i; + begin + + if (reset) begin + memory_out_a <= #FLOP_DELAY inita_val; + end else begin + // Shift the address by the ratio + address = (addr/READ_ADDR_A_DIV); + if (address >= C_READ_DEPTH_A) begin + if (!C_DISABLE_WARN_BHV_RANGE) begin + $fdisplay(ADDRFILE, + "%0s WARNING: Address %0h is outside range for A Read", + C_CORENAME, addr); + end + memory_out_a <= #FLOP_DELAY 'bX; + // valid address + end else begin + if (READ_WIDTH_RATIO_A==1) begin + memory_out_a <= #FLOP_DELAY memory[address*READ_WIDTH_RATIO_A]; + end else begin + // Increment through the 'partial' words in the memory + for (i = 0; i < READ_WIDTH_RATIO_A; i = i + 1) begin + memory_out_a[MIN_WIDTH*i+:MIN_WIDTH] + <= #FLOP_DELAY memory[address*READ_WIDTH_RATIO_A + i]; + end + end //end READ_WIDTH_RATIO_A==1 loop + + end //end valid address loop + end //end reset-data assignment loops + end + endtask + + //************** + // read_b + //************** + task read_b + (input reg [C_ADDRB_WIDTH-1:0] addr, + input reg reset); + reg [C_ADDRB_WIDTH-1:0] address; + integer i; + begin + + if (reset) begin + memory_out_b <= #FLOP_DELAY initb_val; + sbiterr_in <= #FLOP_DELAY 1'b0; + dbiterr_in <= #FLOP_DELAY 1'b0; + rdaddrecc_in <= #FLOP_DELAY 0; + end else begin + // Shift the address + address = (addr/READ_ADDR_B_DIV); + if (address >= C_READ_DEPTH_B) begin + if (!C_DISABLE_WARN_BHV_RANGE) begin + $fdisplay(ADDRFILE, + "%0s WARNING: Address %0h is outside range for B Read", + C_CORENAME, addr); + end + memory_out_b <= #FLOP_DELAY 'bX; + sbiterr_in <= #FLOP_DELAY 1'bX; + dbiterr_in <= #FLOP_DELAY 1'bX; + rdaddrecc_in <= #FLOP_DELAY 'bX; + // valid address + end else begin + if (READ_WIDTH_RATIO_B==1) begin + memory_out_b <= #FLOP_DELAY memory[address*READ_WIDTH_RATIO_B]; + end else begin + // Increment through the 'partial' words in the memory + for (i = 0; i < READ_WIDTH_RATIO_B; i = i + 1) begin + memory_out_b[MIN_WIDTH*i+:MIN_WIDTH] + <= #FLOP_DELAY memory[address*READ_WIDTH_RATIO_B + i]; + end + end + + if ((C_FAMILY == "virtex6" || C_FAMILY == "virtex6l") && C_USE_ECC == 1) begin + rdaddrecc_in <= addr; + if (sbiterr_arr[addr] == 1) begin + sbiterr_in <= #FLOP_DELAY 1'b1; + end else begin + sbiterr_in <= #FLOP_DELAY 1'b0; + end + + if (dbiterr_arr[addr] == 1) begin + dbiterr_in <= #FLOP_DELAY 1'b1; + end else begin + dbiterr_in <= #FLOP_DELAY 1'b0; + end + end else begin + rdaddrecc_in <= #FLOP_DELAY 0; + dbiterr_in <= #FLOP_DELAY 1'b0; + sbiterr_in <= #FLOP_DELAY 1'b0; + end //end ECC Loop + + end //end Valid address loop + end //end reset-data assignment loops + end + endtask + + //************** + // reset_a + //************** + task reset_a (input reg reset); + begin + if (reset) memory_out_a <= #FLOP_DELAY inita_val; + end + endtask + + //************** + // reset_b + //************** + task reset_b (input reg reset); + begin + if (reset) memory_out_b <= #FLOP_DELAY initb_val; + end + endtask + + //************** + // init_memory + //************** + task init_memory; + integer i, addr_step; + integer status; + reg [C_WRITE_WIDTH_A-1:0] default_data; + begin + default_data = 0; + + //Display output message indicating that the behavioral model is being + //initialized + if (C_USE_DEFAULT_DATA || C_LOAD_INIT_FILE) $display(" Block Memory Generator CORE Generator module loading initial data..."); + + // Convert the default to hex + if (C_USE_DEFAULT_DATA) begin + if (default_data_str == "") begin + $fdisplay(ERRFILE, "%0s ERROR: C_DEFAULT_DATA is empty!", C_CORENAME); + $finish; + end else begin + status = $sscanf(default_data_str, "%h", default_data); + if (status == 0) begin + $fdisplay(ERRFILE, {"%0s ERROR: Unsuccessful hexadecimal read", + "from C_DEFAULT_DATA: %0s"}, + C_CORENAME, C_DEFAULT_DATA); + $finish; + end + end + end + + // Step by WRITE_ADDR_A_DIV through the memory via the + // Port A write interface to hit every location once + addr_step = WRITE_ADDR_A_DIV; + + // 'write' to every location with default (or 0) + for (i = 0; i < C_WRITE_DEPTH_A*addr_step; i = i + addr_step) begin + write_a(i, {C_WEA_WIDTH{1'b1}}, default_data, 1'b0, 1'b0); + end + + // Get specialized data from the MIF file + if (C_LOAD_INIT_FILE) begin + if (init_file_str == "") begin + $fdisplay(ERRFILE, "%0s ERROR: C_INIT_FILE_NAME is empty!", + C_CORENAME); + $finish; + end else begin + initfile = $fopen(init_file_str, "r"); + if (initfile == 0) begin + $fdisplay(ERRFILE, {"%0s, ERROR: Problem opening", + "C_INIT_FILE_NAME: %0s!"}, + C_CORENAME, init_file_str); + $finish; + end else begin + // loop through the mif file, loading in the data + for (i = 0; i < C_WRITE_DEPTH_A*addr_step; i = i + addr_step) begin + status = $fscanf(initfile, "%b", mif_data); + if (status > 0) begin + write_a(i, {C_WEA_WIDTH{1'b1}}, mif_data, 1'b0, 1'b0); + end + end + $fclose(initfile); + end //initfile + end //init_file_str + end //C_LOAD_INIT_FILE + + //Display output message indicating that the behavioral model is done + //initializing + if (C_USE_DEFAULT_DATA || C_LOAD_INIT_FILE) + $display(" Block Memory Generator data initialization complete."); + end + endtask + + //************** + // log2roundup + //************** + function integer log2roundup (input integer data_value); + integer width; + integer cnt; + begin + width = 0; + + if (data_value > 1) begin + for(cnt=1 ; cnt < data_value ; cnt = cnt * 2) begin + width = width + 1; + end //loop + end //if + + log2roundup = width; + + end //log2roundup + endfunction + + + //******************* + // collision_check + //******************* + function integer collision_check (input reg [C_ADDRA_WIDTH-1:0] addr_a, + input integer iswrite_a, + input reg [C_ADDRB_WIDTH-1:0] addr_b, + input integer iswrite_b); + reg c_aw_bw, c_aw_br, c_ar_bw; + integer scaled_addra_to_waddrb_width; + integer scaled_addrb_to_waddrb_width; + integer scaled_addra_to_waddra_width; + integer scaled_addrb_to_waddra_width; + integer scaled_addra_to_raddrb_width; + integer scaled_addrb_to_raddrb_width; + integer scaled_addra_to_raddra_width; + integer scaled_addrb_to_raddra_width; + + + + begin + + c_aw_bw = 0; + c_aw_br = 0; + c_ar_bw = 0; + + //If write_addr_b_width is smaller, scale both addresses to that width for + //comparing write_addr_a and write_addr_b; addr_a starts as C_ADDRA_WIDTH, + //scale it down to write_addr_b_width. addr_b starts as C_ADDRB_WIDTH, + //scale it down to write_addr_b_width. Once both are scaled to + //write_addr_b_width, compare. + scaled_addra_to_waddrb_width = ((addr_a)/ + 2**(C_ADDRA_WIDTH-write_addr_b_width)); + scaled_addrb_to_waddrb_width = ((addr_b)/ + 2**(C_ADDRB_WIDTH-write_addr_b_width)); + + //If write_addr_a_width is smaller, scale both addresses to that width for + //comparing write_addr_a and write_addr_b; addr_a starts as C_ADDRA_WIDTH, + //scale it down to write_addr_a_width. addr_b starts as C_ADDRB_WIDTH, + //scale it down to write_addr_a_width. Once both are scaled to + //write_addr_a_width, compare. + scaled_addra_to_waddra_width = ((addr_a)/ + 2**(C_ADDRA_WIDTH-write_addr_a_width)); + scaled_addrb_to_waddra_width = ((addr_b)/ + 2**(C_ADDRB_WIDTH-write_addr_a_width)); + + //If read_addr_b_width is smaller, scale both addresses to that width for + //comparing write_addr_a and read_addr_b; addr_a starts as C_ADDRA_WIDTH, + //scale it down to read_addr_b_width. addr_b starts as C_ADDRB_WIDTH, + //scale it down to read_addr_b_width. Once both are scaled to + //read_addr_b_width, compare. + scaled_addra_to_raddrb_width = ((addr_a)/ + 2**(C_ADDRA_WIDTH-read_addr_b_width)); + scaled_addrb_to_raddrb_width = ((addr_b)/ + 2**(C_ADDRB_WIDTH-read_addr_b_width)); + + //If read_addr_a_width is smaller, scale both addresses to that width for + //comparing read_addr_a and write_addr_b; addr_a starts as C_ADDRA_WIDTH, + //scale it down to read_addr_a_width. addr_b starts as C_ADDRB_WIDTH, + //scale it down to read_addr_a_width. Once both are scaled to + //read_addr_a_width, compare. + scaled_addra_to_raddra_width = ((addr_a)/ + 2**(C_ADDRA_WIDTH-read_addr_a_width)); + scaled_addrb_to_raddra_width = ((addr_b)/ + 2**(C_ADDRB_WIDTH-read_addr_a_width)); + + //Look for a write-write collision. In order for a write-write + //collision to exist, both ports must have a write transaction. + if (iswrite_a && iswrite_b) begin + if (write_addr_a_width > write_addr_b_width) begin + if (scaled_addra_to_waddrb_width == scaled_addrb_to_waddrb_width) begin + c_aw_bw = 1; + end else begin + c_aw_bw = 0; + end + end else begin + if (scaled_addrb_to_waddra_width == scaled_addra_to_waddra_width) begin + c_aw_bw = 1; + end else begin + c_aw_bw = 0; + end + end //width + end //iswrite_a and iswrite_b + + //If the B port is reading (which means it is enabled - so could be + //a TX_WRITE or TX_READ), then check for a write-read collision). + //This could happen whether or not a write-write collision exists due + //to asymmetric write/read ports. + if (iswrite_a) begin + if (write_addr_a_width > read_addr_b_width) begin + if (scaled_addra_to_raddrb_width == scaled_addrb_to_raddrb_width) begin + c_aw_br = 1; + end else begin + c_aw_br = 0; + end + end else begin + if (scaled_addrb_to_waddra_width == scaled_addra_to_waddra_width) begin + c_aw_br = 1; + end else begin + c_aw_br = 0; + end + end //width + end //iswrite_a + + //If the A port is reading (which means it is enabled - so could be + // a TX_WRITE or TX_READ), then check for a write-read collision). + //This could happen whether or not a write-write collision exists due + // to asymmetric write/read ports. + if (iswrite_b) begin + if (read_addr_a_width > write_addr_b_width) begin + if (scaled_addra_to_waddrb_width == scaled_addrb_to_waddrb_width) begin + c_ar_bw = 1; + end else begin + c_ar_bw = 0; + end + end else begin + if (scaled_addrb_to_raddra_width == scaled_addra_to_raddra_width) begin + c_ar_bw = 1; + end else begin + c_ar_bw = 0; + end + end //width + end //iswrite_b + + + + collision_check = c_aw_bw | c_aw_br | c_ar_bw; + + end + endfunction + + //******************************* + // power on values + //******************************* + initial begin + // Load up the memory + init_memory; + // Load up the output registers and latches + if ($sscanf(inita_str, "%h", inita_val)) begin + memory_out_a = inita_val; + end else begin + memory_out_a = 0; + end + if ($sscanf(initb_str, "%h", initb_val)) begin + memory_out_b = initb_val; + end else begin + memory_out_b = 0; + end + + sbiterr_in = 1'b0; + dbiterr_in = 1'b0; + rdaddrecc_in = 0; + + // Determine the effective address widths for each of the 4 ports + write_addr_a_width = C_ADDRA_WIDTH - log2roundup(WRITE_ADDR_A_DIV); + read_addr_a_width = C_ADDRA_WIDTH - log2roundup(READ_ADDR_A_DIV); + write_addr_b_width = C_ADDRB_WIDTH - log2roundup(WRITE_ADDR_B_DIV); + read_addr_b_width = C_ADDRB_WIDTH - log2roundup(READ_ADDR_B_DIV); + + $display("Block Memory Generator CORE Generator module %m is using a behavioral model for simulation which will not precisely model memory collision behavior."); + + end + + //************************************************************************* + // Asynchronous reset of Port A and Port B are performed here + // Note that the asynchronous reset feature is only supported in Spartan6 + // devices + //************************************************************************* + generate if((C_FAMILY == "spartan6" || C_FAMILY == "spartan6l" || C_FAMILY == "aspartan6") && C_RST_TYPE=="ASYNC") begin : async_rst + if (C_RST_PRIORITY_A=="CE") begin + always @ (*) begin + if (rea_i) reset_a(reseta_i); + end + end + else begin + always @ (*) begin + reset_a(reseta_i); + end + end + + if (C_RST_PRIORITY_B=="CE") begin + always @ (*) begin + if (reb_i) reset_b(resetb_i); + end + end + else begin + always @ (*) begin + reset_b(resetb_i); + end + end + + end + endgenerate + + //*************************************************************************** + // These are the main blocks which schedule read and write operations + // Note that the reset priority feature at the latch stage is only supported + // for Spartan-6. For other families, the default priority at the latch stage + // is "CE" + //*************************************************************************** + // Synchronous clocks: schedule port operations with respect to + // both write operating modes + generate + if(C_COMMON_CLK && (C_WRITE_MODE_A == "WRITE_FIRST") && (C_WRITE_MODE_B == + "WRITE_FIRST")) begin : com_clk_sched_wf_wf + always @(posedge CLKA) begin + //Write A + if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR); + //Write B + if (web_i) write_b(ADDRB, web_i, DINB); + //Read A + if ((C_FAMILY == "spartan6" || C_FAMILY == "spartan6l" || C_FAMILY == "aspartan6") && C_RST_PRIORITY_A=="SR") begin + if (reseta_i) reset_a(reseta_i); + else if (rea_i) read_a(ADDRA, reseta_i); + end else begin + if (rea_i) read_a(ADDRA, reseta_i); + end + //Read B + if ((C_FAMILY == "spartan6" || C_FAMILY == "spartan6l" || C_FAMILY == "aspartan6") && C_RST_PRIORITY_B=="SR") begin + if (resetb_i) reset_b(resetb_i); + else if (reb_i) read_b(ADDRB, resetb_i); + end else begin + if (reb_i) read_b(ADDRB, resetb_i); + end + end + end + else + if(C_COMMON_CLK && (C_WRITE_MODE_A == "READ_FIRST") && (C_WRITE_MODE_B == + "WRITE_FIRST")) begin : com_clk_sched_rf_wf + always @(posedge CLKA) begin + //Write B + if (web_i) write_b(ADDRB, web_i, DINB); + //Read B + if ((C_FAMILY == "spartan6" || C_FAMILY == "spartan6l" || C_FAMILY == "aspartan6") && C_RST_PRIORITY_B=="SR") begin + if (resetb_i) reset_b(resetb_i); + else if (reb_i) read_b(ADDRB, resetb_i); + end else begin + if (reb_i) read_b(ADDRB, resetb_i); + end + //Read A + if ((C_FAMILY == "spartan6" || C_FAMILY == "spartan6l" || C_FAMILY == "aspartan6") && C_RST_PRIORITY_A=="SR") begin + if (reseta_i) reset_a(reseta_i); + else if (rea_i) read_a(ADDRA, reseta_i); + end else begin + if (rea_i) read_a(ADDRA, reseta_i); + end + //Write A + if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR); + end + end + else + if(C_COMMON_CLK && (C_WRITE_MODE_A == "WRITE_FIRST") && (C_WRITE_MODE_B == + "READ_FIRST")) begin : com_clk_sched_wf_rf + always @(posedge CLKA) begin + //Write A + if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR); + //Read A + if ((C_FAMILY == "spartan6" || C_FAMILY == "spartan6l" || C_FAMILY == "aspartan6") && C_RST_PRIORITY_A=="SR") begin + if (reseta_i) reset_a(reseta_i); + else if (rea_i) read_a(ADDRA, reseta_i); + end else begin + if (rea_i) read_a(ADDRA, reseta_i); + end + //Read B + if ((C_FAMILY == "spartan6" || C_FAMILY == "spartan6l"|| C_FAMILY == "aspartan6") && C_RST_PRIORITY_B=="SR") begin + if (resetb_i) reset_b(resetb_i); + else if (reb_i) read_b(ADDRB, resetb_i); + end else begin + if (reb_i) read_b(ADDRB, resetb_i); + end + //Write B + if (web_i) write_b(ADDRB, web_i, DINB); + end + end + else + if(C_COMMON_CLK && (C_WRITE_MODE_A == "READ_FIRST") && (C_WRITE_MODE_B == + "READ_FIRST")) begin : com_clk_sched_rf_rf + always @(posedge CLKA) begin + //Read A + if ((C_FAMILY == "spartan6" || C_FAMILY == "spartan6l"|| C_FAMILY == "aspartan6") && C_RST_PRIORITY_A=="SR") begin + if (reseta_i) reset_a(reseta_i); + else if (rea_i) read_a(ADDRA, reseta_i); + end else begin + if (rea_i) read_a(ADDRA, reseta_i); + end + //Read B + if ((C_FAMILY == "spartan6" || C_FAMILY == "spartan6l"|| C_FAMILY == "aspartan6") && C_RST_PRIORITY_B=="SR") begin + if (resetb_i) reset_b(resetb_i); + else if (reb_i) read_b(ADDRB, resetb_i); + end else begin + if (reb_i) read_b(ADDRB, resetb_i); + end + //Write A + if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR); + //Write B + if (web_i) write_b(ADDRB, web_i, DINB); + end + end + else if(C_COMMON_CLK && (C_WRITE_MODE_A =="WRITE_FIRST") && (C_WRITE_MODE_B == + "NO_CHANGE")) begin : com_clk_sched_wf_nc + always @(posedge CLKA) begin + //Write A + if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR); + //Read A + if ((C_FAMILY == "spartan6" || C_FAMILY == "spartan6l"|| C_FAMILY == "aspartan6") && C_RST_PRIORITY_A=="SR") begin + if (reseta_i) reset_a(reseta_i); + else if (rea_i) read_a(ADDRA, reseta_i); + end else begin + if (rea_i) read_a(ADDRA, reseta_i); + end + //Read B + if ((C_FAMILY == "spartan6" || C_FAMILY == "spartan6l"|| C_FAMILY == "aspartan6") && C_RST_PRIORITY_B=="SR") begin + if (resetb_i) reset_b(resetb_i); + else if (reb_i && !web_i) read_b(ADDRB, resetb_i); + end else begin + if (reb_i && (!web_i || resetb_i)) read_b(ADDRB, resetb_i); + end + //Write B + if (web_i) write_b(ADDRB, web_i, DINB); + end + end + else if(C_COMMON_CLK && (C_WRITE_MODE_A =="READ_FIRST") && (C_WRITE_MODE_B == + "NO_CHANGE")) begin : com_clk_sched_rf_nc + always @(posedge CLKA) begin + //Read A + if ((C_FAMILY == "spartan6" || C_FAMILY == "spartan6l"|| C_FAMILY == "aspartan6") && C_RST_PRIORITY_A=="SR") begin + if (reseta_i) reset_a(reseta_i); + else if (rea_i) read_a(ADDRA, reseta_i); + end else begin + if (rea_i) read_a(ADDRA, reseta_i); + end + //Read B + if ((C_FAMILY == "spartan6" || C_FAMILY == "spartan6l"|| C_FAMILY == "aspartan6") && C_RST_PRIORITY_B=="SR") begin + if (resetb_i) reset_b(resetb_i); + else if (reb_i && !web_i) read_b(ADDRB, resetb_i); + end else begin + if (reb_i && (!web_i || resetb_i)) read_b(ADDRB, resetb_i); + end + //Write A + if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR); + //Write B + if (web_i) write_b(ADDRB, web_i, DINB); + end + end + else if(C_COMMON_CLK && (C_WRITE_MODE_A =="NO_CHANGE") && (C_WRITE_MODE_B == + "WRITE_FIRST")) begin : com_clk_sched_nc_wf + always @(posedge CLKA) begin + //Write A + if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR); + //Write B + if (web_i) write_b(ADDRB, web_i, DINB); + //Read A + if ((C_FAMILY == "spartan6" || C_FAMILY == "spartan6l"|| C_FAMILY == "aspartan6") && C_RST_PRIORITY_A=="SR") begin + if (reseta_i) reset_a(reseta_i); + else if (rea_i && !wea_i) read_a(ADDRA, reseta_i); + end else begin + if (rea_i && (!wea_i || reseta_i)) read_a(ADDRA, reseta_i); + end + //Read B + if ((C_FAMILY == "spartan6" || C_FAMILY == "spartan6l"|| C_FAMILY == "aspartan6") && C_RST_PRIORITY_B=="SR") begin + if (resetb_i) reset_b(resetb_i); + else if (reb_i) read_b(ADDRB, resetb_i); + end else begin + if (reb_i) read_b(ADDRB, resetb_i); + end + end + end + else if(C_COMMON_CLK && (C_WRITE_MODE_A =="NO_CHANGE") && (C_WRITE_MODE_B == + "READ_FIRST")) begin : com_clk_sched_nc_rf + always @(posedge CLKA) begin + //Read B + if ((C_FAMILY == "spartan6" || C_FAMILY == "spartan6l"|| C_FAMILY == "aspartan6") && C_RST_PRIORITY_B=="SR") begin + if (resetb_i) reset_b(resetb_i); + else if (reb_i) read_b(ADDRB, resetb_i); + end else begin + if (reb_i) read_b(ADDRB, resetb_i); + end + //Read A + if ((C_FAMILY == "spartan6" || C_FAMILY == "spartan6l"|| C_FAMILY == "aspartan6") && C_RST_PRIORITY_A=="SR") begin + if (reseta_i) reset_a(reseta_i); + else if (rea_i && !wea_i) read_a(ADDRA, reseta_i); + end else begin + if (rea_i && (!wea_i || reseta_i)) read_a(ADDRA, reseta_i); + end + //Write A + if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR); + //Write B + if (web_i) write_b(ADDRB, web_i, DINB); + end + end + else if(C_COMMON_CLK && (C_WRITE_MODE_A =="NO_CHANGE") && (C_WRITE_MODE_B == + "NO_CHANGE")) begin : com_clk_sched_nc_nc + always @(posedge CLKA) begin + //Write A + if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR); + //Write B + if (web_i) write_b(ADDRB, web_i, DINB); + //Read A + if ((C_FAMILY == "spartan6" || C_FAMILY == "spartan6l"|| C_FAMILY == "aspartan6") && C_RST_PRIORITY_A=="SR") begin + if (reseta_i) reset_a(reseta_i); + else if (rea_i && !wea_i) read_a(ADDRA, reseta_i); + end else begin + if (rea_i && (!wea_i || reseta_i)) read_a(ADDRA, reseta_i); + end + //Read B + if ((C_FAMILY == "spartan6" || C_FAMILY == "spartan6l"|| C_FAMILY == "aspartan6") && C_RST_PRIORITY_B=="SR") begin + if (resetb_i) reset_b(resetb_i); + else if (reb_i && !web_i) read_b(ADDRB, resetb_i); + end else begin + if (reb_i && (!web_i || resetb_i)) read_b(ADDRB, resetb_i); + end + end + end + else if(C_COMMON_CLK) begin: com_clk_sched_default + always @(posedge CLKA) begin + //Write A + if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR); + //Write B + if (web_i) write_b(ADDRB, web_i, DINB); + //Read A + if ((C_FAMILY == "spartan6" || C_FAMILY == "spartan6l"|| C_FAMILY == "aspartan6") && C_RST_PRIORITY_A=="SR") begin + if (reseta_i) reset_a(reseta_i); + else if (rea_i) read_a(ADDRA, reseta_i); + end else begin + if (rea_i) read_a(ADDRA, reseta_i); + end + //Read B + if ((C_FAMILY == "spartan6" || C_FAMILY == "spartan6l"|| C_FAMILY == "aspartan6") && C_RST_PRIORITY_B=="SR") begin + if (resetb_i) reset_b(resetb_i); + else if (reb_i) read_b(ADDRB, resetb_i); + end else begin + if (reb_i) read_b(ADDRB, resetb_i); + end + end + end + endgenerate + + // Asynchronous clocks: port operation is independent + + generate + if((!C_COMMON_CLK) && (C_WRITE_MODE_A == "WRITE_FIRST")) begin : async_clk_sched_clka_wf + always @(posedge CLKA) begin + //Write A + if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR); + //Read A + if ((C_FAMILY == "spartan6" || C_FAMILY == "spartan6l"|| C_FAMILY == "aspartan6") && C_RST_PRIORITY_A=="SR") begin + if (reseta_i) reset_a(reseta_i); + else if (rea_i) read_a(ADDRA, reseta_i); + end else begin + if (rea_i) read_a(ADDRA, reseta_i); + end + end + end + else if((!C_COMMON_CLK) && (C_WRITE_MODE_A == "READ_FIRST")) begin : async_clk_sched_clka_rf + always @(posedge CLKA) begin + //Read A + if ((C_FAMILY == "spartan6" || C_FAMILY == "spartan6l"|| C_FAMILY == "aspartan6") && C_RST_PRIORITY_A=="SR") begin + if (reseta_i) reset_a(reseta_i); + else if (rea_i) read_a(ADDRA, reseta_i); + end else begin + if (rea_i) read_a(ADDRA, reseta_i); + end + //Write A + if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR); + end + end + else if((!C_COMMON_CLK) && (C_WRITE_MODE_A == "NO_CHANGE")) begin : async_clk_sched_clka_nc + always @(posedge CLKA) begin + //Write A + if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR); + //Read A + if ((C_FAMILY == "spartan6" || C_FAMILY == "spartan6l"|| C_FAMILY == "aspartan6") && C_RST_PRIORITY_A=="SR") begin + if (reseta_i) reset_a(reseta_i); + else if (rea_i && !wea_i) read_a(ADDRA, reseta_i); + end else begin + if (rea_i && (!wea_i || reseta_i)) read_a(ADDRA, reseta_i); + end + end + end + endgenerate + + generate + if ((!C_COMMON_CLK) && (C_WRITE_MODE_B == "WRITE_FIRST")) begin: async_clk_sched_clkb_wf + always @(posedge CLKB) begin + //Write B + if (web_i) write_b(ADDRB, web_i, DINB); + //Read B + if ((C_FAMILY == "spartan6" || C_FAMILY == "spartan6l"|| C_FAMILY == "aspartan6") && C_RST_PRIORITY_B=="SR") begin + if (resetb_i) reset_b(resetb_i); + else if (reb_i) read_b(ADDRB, resetb_i); + end else begin + if (reb_i) read_b(ADDRB, resetb_i); + end + end + end + else if ((!C_COMMON_CLK) && (C_WRITE_MODE_B == "READ_FIRST")) begin: async_clk_sched_clkb_rf + always @(posedge CLKB) begin + //Read B + if ((C_FAMILY == "spartan6" || C_FAMILY == "spartan6l"|| C_FAMILY == "aspartan6") && C_RST_PRIORITY_B=="SR") begin + if (resetb_i) reset_b(resetb_i); + else if (reb_i) read_b(ADDRB, resetb_i); + end else begin + if (reb_i) read_b(ADDRB, resetb_i); + end + //Write B + if (web_i) write_b(ADDRB, web_i, DINB); + end + end + else if ((!C_COMMON_CLK) && (C_WRITE_MODE_B == "NO_CHANGE")) begin: async_clk_sched_clkb_nc + always @(posedge CLKB) begin + //Write B + if (web_i) write_b(ADDRB, web_i, DINB); + //Read B + if ((C_FAMILY == "spartan6" || C_FAMILY == "spartan6l"|| C_FAMILY == "aspartan6") && C_RST_PRIORITY_B=="SR") begin + if (resetb_i) reset_b(resetb_i); + else if (reb_i && !web_i) read_b(ADDRB, resetb_i); + end else begin + if (reb_i && (!web_i || resetb_i)) read_b(ADDRB, resetb_i); + end + end + end + endgenerate + + + //*************************************************************** + // Instantiate the variable depth output register stage module + //*************************************************************** + // Port A + BLK_MEM_GEN_V3_3_output_stage + #(.C_FAMILY (C_FAMILY), + .C_XDEVICEFAMILY (C_XDEVICEFAMILY), + .C_RST_TYPE (C_RST_TYPE), + .C_HAS_RST (C_HAS_RSTA), + .C_RSTRAM (C_RSTRAM_A), + .C_RST_PRIORITY (C_RST_PRIORITY_A), + .C_INIT_VAL (C_INITA_VAL), + .C_HAS_EN (C_HAS_ENA), + .C_HAS_REGCE (C_HAS_REGCEA), + .C_DATA_WIDTH (C_READ_WIDTH_A), + .C_ADDRB_WIDTH (C_ADDRB_WIDTH), + .C_HAS_MEM_OUTPUT_REGS (C_HAS_MEM_OUTPUT_REGS_A), + .C_USE_ECC (C_USE_ECC), + .NUM_STAGES (NUM_OUTPUT_STAGES_A), + .FLOP_DELAY (FLOP_DELAY)) + reg_a + (.CLK (CLKA), + .RST (RSTA), + .EN (ENA), + .REGCE (REGCEA), + .DIN (memory_out_a), + .DOUT (DOUTA), + .SBITERR_IN (1'b0), + .DBITERR_IN (1'b0), + .SBITERR (), + .DBITERR (), + .RDADDRECC_IN ({C_ADDRB_WIDTH{1'b0}}), + .RDADDRECC () + ); + + // Port B + BLK_MEM_GEN_V3_3_output_stage + #(.C_FAMILY (C_FAMILY), + .C_XDEVICEFAMILY (C_XDEVICEFAMILY), + .C_RST_TYPE (C_RST_TYPE), + .C_HAS_RST (C_HAS_RSTB), + .C_RSTRAM (C_RSTRAM_B), + .C_RST_PRIORITY (C_RST_PRIORITY_B), + .C_INIT_VAL (C_INITB_VAL), + .C_HAS_EN (C_HAS_ENB), + .C_HAS_REGCE (C_HAS_REGCEB), + .C_DATA_WIDTH (C_READ_WIDTH_B), + .C_ADDRB_WIDTH (C_ADDRB_WIDTH), + .C_HAS_MEM_OUTPUT_REGS (C_HAS_MEM_OUTPUT_REGS_B), + .C_USE_ECC (C_USE_ECC), + .NUM_STAGES (NUM_OUTPUT_STAGES_B), + .FLOP_DELAY (FLOP_DELAY)) + reg_b + (.CLK (CLKB), + .RST (RSTB), + .EN (ENB), + .REGCE (REGCEB), + .DIN (memory_out_b), + .DOUT (DOUTB), + .SBITERR_IN (sbiterr_in), + .DBITERR_IN (dbiterr_in), + .SBITERR (sbiterr_sdp), + .DBITERR (dbiterr_sdp), + .RDADDRECC_IN (rdaddrecc_in), + .RDADDRECC (rdaddrecc_sdp) + ); + + //**************************************************** + // Synchronous collision checks + //**************************************************** + generate if (!C_DISABLE_WARN_BHV_COLL && C_COMMON_CLK) begin : sync_coll + always @(posedge CLKA) begin + // Possible collision if both are enabled and the addresses match + if (ena_i && enb_i) begin + if (wea_i || web_i) begin + is_collision <= collision_check(ADDRA, wea_i, ADDRB, web_i); + end else begin + is_collision <= 0; + end + end else begin + is_collision <= 0; + end + + // If the write port is in READ_FIRST mode, there is no collision + if (C_WRITE_MODE_A=="READ_FIRST" && wea_i && !web_i) begin + is_collision <= 0; + end + if (C_WRITE_MODE_B=="READ_FIRST" && web_i && !wea_i) begin + is_collision <= 0; + end + + // Only flag if one of the accesses is a write + if (is_collision && (wea_i || web_i)) begin + $fwrite(COLLFILE, "%0s collision detected at time: %0d, ", + C_CORENAME, $time); + $fwrite(COLLFILE, "A %0s address: %0h, B %0s address: %0h\n", + wea_i ? "write" : "read", ADDRA, + web_i ? "write" : "read", ADDRB); + end + end + + //**************************************************** + // Asynchronous collision checks + //**************************************************** + end else if (!C_DISABLE_WARN_BHV_COLL && !C_COMMON_CLK) begin : async_coll + + // Delay A and B addresses in order to mimic setup/hold times + wire [C_ADDRA_WIDTH-1:0] #COLL_DELAY addra_delay = ADDRA; + wire [0:0] #COLL_DELAY wea_delay = wea_i; + wire #COLL_DELAY ena_delay = ena_i; + wire [C_ADDRB_WIDTH-1:0] #COLL_DELAY addrb_delay = ADDRB; + wire [0:0] #COLL_DELAY web_delay = web_i; + wire #COLL_DELAY enb_delay = enb_i; + + // Do the checks w/rt A + always @(posedge CLKA) begin + // Possible collision if both are enabled and the addresses match + if (ena_i && enb_i) begin + if (wea_i || web_i) begin + is_collision_a <= collision_check(ADDRA, wea_i, ADDRB, web_i); + end else begin + is_collision_a <= 0; + end + end else begin + is_collision_a <= 0; + end + + if (ena_i && enb_delay) begin + if(wea_i || web_delay) begin + is_collision_delay_a <= collision_check(ADDRA, wea_i, addrb_delay, + web_delay); + end else begin + is_collision_delay_a <= 0; + end + end else begin + is_collision_delay_a <= 0; + end + + + // Only flag if B access is a write + if (is_collision_a && web_i) begin + $fwrite(COLLFILE, "%0s collision detected at time: %0d, ", + C_CORENAME, $time); + $fwrite(COLLFILE, "A %0s address: %0h, B write address: %0h\n", + wea_i ? "write" : "read", ADDRA, ADDRB); + + end else if (is_collision_delay_a && web_delay) begin + $fwrite(COLLFILE, "%0s collision detected at time: %0d, ", + C_CORENAME, $time); + $fwrite(COLLFILE, "A %0s address: %0h, B write address: %0h\n", + wea_i ? "write" : "read", ADDRA, addrb_delay); + end + + end + + // Do the checks w/rt B + always @(posedge CLKB) begin + + // Possible collision if both are enabled and the addresses match + if (ena_i && enb_i) begin + if (wea_i || web_i) begin + is_collision_b <= collision_check(ADDRA, wea_i, ADDRB, web_i); + end else begin + is_collision_b <= 0; + end + end else begin + is_collision_b <= 0; + end + + if (ena_delay && enb_i) begin + if (wea_delay || web_i) begin + is_collision_delay_b <= collision_check(addra_delay, wea_delay, ADDRB, + web_i); + end else begin + is_collision_delay_b <= 0; + end + end else begin + is_collision_delay_b <= 0; + end + + + // Only flag if A access is a write + if (is_collision_b && wea_i) begin + $fwrite(COLLFILE, "%0s collision detected at time: %0d, ", + C_CORENAME, $time); + $fwrite(COLLFILE, "A write address: %0h, B %s address: %0h\n", + ADDRA, web_i ? "write" : "read", ADDRB); + + end else if (is_collision_delay_b && wea_delay) begin + $fwrite(COLLFILE, "%0s collision detected at time: %0d, ", + C_CORENAME, $time); + $fwrite(COLLFILE, "A write address: %0h, B %s address: %0h\n", + addra_delay, web_i ? "write" : "read", ADDRB); + end + + end + end + endgenerate + +endmodule diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/BLK_MEM_GEN_V3_3_xst.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/BLK_MEM_GEN_V3_3_xst.v new file mode 100644 index 0000000..3d28117 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/BLK_MEM_GEN_V3_3_xst.v @@ -0,0 +1,224 @@ +/****************************************************************************** +-- (c) Copyright 2006 - 2009 Xilinx, Inc. All rights reserved. +-- +-- This file contains confidential and proprietary information +-- of Xilinx, Inc. and is protected under U.S. and +-- international copyright and other intellectual property +-- laws. +-- +-- DISCLAIMER +-- This disclaimer is not a license and does not grant any +-- rights to the materials distributed herewith. Except as +-- otherwise provided in a valid license issued to you by +-- Xilinx, and to the maximum extent permitted by applicable +-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +-- (2) Xilinx shall not be liable (whether in contract or tort, +-- including negligence, or under any other theory of +-- liability) for any loss or damage of any kind or nature +-- related to, arising under or in connection with these +-- materials, including for any direct, or any indirect, +-- special, incidental, or consequential loss or damage +-- (including loss of data, profits, goodwill, or any type of +-- loss or damage suffered as a result of any action brought +-- by a third party) even if such damage or loss was +-- reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail- +-- safe, or for use in any application requiring fail-safe +-- performance, such as life-support or safety devices or +-- systems, Class III medical devices, nuclear facilities, +-- applications related to the deployment of airbags, or any +-- other applications that could lead to death, personal +-- injury, or severe property or environmental damage +-- (individually and collectively, "Critical +-- Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical +-- Applications, subject only to applicable laws and +-- regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +-- PART OF THIS FILE AT ALL TIMES. +-- + ***************************************************************************** + * + * Filename: BLK_MEM_GEN_V3_3.v + * + * Description: + * This file is the Verilog behvarial model for the + * Block Memory Generator Core. + * + ***************************************************************************** + * Author: Xilinx + * + * History: September 6, 2005 Initial revision + *****************************************************************************/ +`timescale 1ps/1ps + +module BLK_MEM_GEN_V3_3_xst + #(parameter C_FAMILY = "virtex5", + parameter C_XDEVICEFAMILY = "virtex5", + parameter C_ELABORATION_DIR = "", + parameter C_MEM_TYPE = 2, + parameter C_BYTE_SIZE = 9, + parameter C_ALGORITHM = 1, + parameter C_PRIM_TYPE = 3, + parameter C_LOAD_INIT_FILE = 0, + parameter C_INIT_FILE_NAME = "", + parameter C_USE_DEFAULT_DATA = 0, + parameter C_DEFAULT_DATA = "0", + parameter C_RST_TYPE = "SYNC", + parameter C_HAS_RSTA = 0, + parameter C_RST_PRIORITY_A = "CE", + parameter C_RSTRAM_A = 0, + parameter C_INITA_VAL = "0", + parameter C_HAS_ENA = 1, + parameter C_HAS_REGCEA = 0, + parameter C_USE_BYTE_WEA = 0, + parameter C_WEA_WIDTH = 1, + parameter C_WRITE_MODE_A = "WRITE_FIRST", + parameter C_WRITE_WIDTH_A = 32, + parameter C_READ_WIDTH_A = 32, + parameter C_WRITE_DEPTH_A = 64, + parameter C_READ_DEPTH_A = 64, + parameter C_ADDRA_WIDTH = 5, + parameter C_HAS_RSTB = 0, + parameter C_RST_PRIORITY_B = "CE", + parameter C_RSTRAM_B = 0, + parameter C_INITB_VAL = "0", + parameter C_HAS_ENB = 1, + parameter C_HAS_REGCEB = 0, + parameter C_USE_BYTE_WEB = 0, + parameter C_WEB_WIDTH = 1, + parameter C_WRITE_MODE_B = "WRITE_FIRST", + parameter C_WRITE_WIDTH_B = 32, + parameter C_READ_WIDTH_B = 32, + parameter C_WRITE_DEPTH_B = 64, + parameter C_READ_DEPTH_B = 64, + parameter C_ADDRB_WIDTH = 5, + parameter C_HAS_MEM_OUTPUT_REGS_A = 0, + parameter C_HAS_MEM_OUTPUT_REGS_B = 0, + parameter C_HAS_MUX_OUTPUT_REGS_A = 0, + parameter C_HAS_MUX_OUTPUT_REGS_B = 0, + parameter C_MUX_PIPELINE_STAGES = 0, + parameter C_USE_ECC = 0, + parameter C_HAS_INJECTERR = 0, + parameter C_SIM_COLLISION_CHECK = "NONE", + parameter C_COMMON_CLK = 1, + parameter C_DISABLE_WARN_BHV_COLL = 0, + parameter C_DISABLE_WARN_BHV_RANGE = 0 +) + (input CLKA, + input RSTA, + input ENA, + input REGCEA, + input [C_WEA_WIDTH-1:0] WEA, + input [C_ADDRA_WIDTH-1:0] ADDRA, + input [C_WRITE_WIDTH_A-1:0] DINA, + output [C_READ_WIDTH_A-1:0] DOUTA, + input CLKB, + input RSTB, + input ENB, + input REGCEB, + input [C_WEB_WIDTH-1:0] WEB, + input [C_ADDRB_WIDTH-1:0] ADDRB, + input [C_WRITE_WIDTH_B-1:0] DINB, + output [C_READ_WIDTH_B-1:0] DOUTB, + input INJECTSBITERR, + input INJECTDBITERR, + output SBITERR, + output DBITERR, + output [C_ADDRB_WIDTH-1:0] RDADDRECC +); + + +// Note: C_ELABORATION_DIR parameter is only used in synthesis +// (and doesn't get mentioned in the instantiation template Coregen generates). +// This wrapper file has to work both in simulation and synthesis. So, this +// parameter exists. It is not used by the behavioral model +// (BLK_MEM_GEN_V3_3.vhd) + + BLK_MEM_GEN_V3_3 + #( + .C_CORENAME ("blk_mem_gen_v3_3"), + .C_FAMILY (C_FAMILY), + .C_XDEVICEFAMILY (C_XDEVICEFAMILY), + .C_MEM_TYPE (C_MEM_TYPE), + .C_BYTE_SIZE (C_BYTE_SIZE), + .C_ALGORITHM (C_ALGORITHM), + .C_PRIM_TYPE (C_PRIM_TYPE), + .C_LOAD_INIT_FILE (C_LOAD_INIT_FILE), + .C_INIT_FILE_NAME (C_INIT_FILE_NAME), + .C_USE_DEFAULT_DATA (C_USE_DEFAULT_DATA), + .C_DEFAULT_DATA (C_DEFAULT_DATA), + .C_RST_TYPE (C_RST_TYPE), + .C_HAS_RSTA (C_HAS_RSTA), + .C_RST_PRIORITY_A (C_RST_PRIORITY_A), + .C_RSTRAM_A (C_RSTRAM_A), + .C_INITA_VAL (C_INITA_VAL), + .C_HAS_ENA (C_HAS_ENA), + .C_HAS_REGCEA (C_HAS_REGCEA), + .C_USE_BYTE_WEA (C_USE_BYTE_WEA), + .C_WEA_WIDTH (C_WEA_WIDTH), + .C_WRITE_MODE_A (C_WRITE_MODE_A), + .C_WRITE_WIDTH_A (C_WRITE_WIDTH_A), + .C_READ_WIDTH_A (C_READ_WIDTH_A), + .C_WRITE_DEPTH_A (C_WRITE_DEPTH_A), + .C_READ_DEPTH_A (C_READ_DEPTH_A), + .C_ADDRA_WIDTH (C_ADDRA_WIDTH), + .C_HAS_RSTB (C_HAS_RSTB), + .C_RST_PRIORITY_B (C_RST_PRIORITY_B), + .C_RSTRAM_B (C_RSTRAM_B), + .C_INITB_VAL (C_INITB_VAL), + .C_HAS_ENB (C_HAS_ENB), + .C_HAS_REGCEB (C_HAS_REGCEB), + .C_USE_BYTE_WEB (C_USE_BYTE_WEB), + .C_WEB_WIDTH (C_WEB_WIDTH), + .C_WRITE_MODE_B (C_WRITE_MODE_B), + .C_WRITE_WIDTH_B (C_WRITE_WIDTH_B), + .C_READ_WIDTH_B (C_READ_WIDTH_B), + .C_WRITE_DEPTH_B (C_WRITE_DEPTH_B), + .C_READ_DEPTH_B (C_READ_DEPTH_B), + .C_ADDRB_WIDTH (C_ADDRB_WIDTH), + .C_HAS_MEM_OUTPUT_REGS_A (C_HAS_MEM_OUTPUT_REGS_A), + .C_HAS_MEM_OUTPUT_REGS_B (C_HAS_MEM_OUTPUT_REGS_B), + .C_HAS_MUX_OUTPUT_REGS_A (C_HAS_MUX_OUTPUT_REGS_A), + .C_HAS_MUX_OUTPUT_REGS_B (C_HAS_MUX_OUTPUT_REGS_B), + .C_MUX_PIPELINE_STAGES (C_MUX_PIPELINE_STAGES), + .C_USE_ECC (C_USE_ECC), + .C_HAS_INJECTERR (C_HAS_INJECTERR), + .C_SIM_COLLISION_CHECK (C_SIM_COLLISION_CHECK), + .C_COMMON_CLK (C_COMMON_CLK), + .C_DISABLE_WARN_BHV_COLL (C_DISABLE_WARN_BHV_COLL), + .C_DISABLE_WARN_BHV_RANGE (C_DISABLE_WARN_BHV_RANGE) + ) blk_mem_gen_v3_3_dut ( + .CLKA (CLKA), + .RSTA (RSTA), + .ENA (ENA), + .REGCEA (REGCEA), + .WEA (WEA), + .ADDRA (ADDRA), + .DINA (DINA), + .DOUTA (DOUTA), + .CLKB (CLKB), + .RSTB (RSTB), + .ENB (ENB), + .REGCEB (REGCEB), + .WEB (WEB), + .ADDRB (ADDRB), + .DINB (DINB), + .DOUTB (DOUTB), + .INJECTSBITERR (INJECTSBITERR), + .INJECTDBITERR (INJECTDBITERR), + .SBITERR (SBITERR), + .DBITERR (DBITERR), + .RDADDRECC (RDADDRECC) +); + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/BLK_MEM_GEN_V4_1.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/BLK_MEM_GEN_V4_1.v new file mode 100644 index 0000000..54cd7a8 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/BLK_MEM_GEN_V4_1.v @@ -0,0 +1,2388 @@ +/****************************************************************************** +-- (c) Copyright 2006 - 2009 Xilinx, Inc. All rights reserved. +-- +-- This file contains confidential and proprietary information +-- of Xilinx, Inc. and is protected under U.S. and +-- international copyright and other intellectual property +-- laws. +-- +-- DISCLAIMER +-- This disclaimer is not a license and does not grant any +-- rights to the materials distributed herewith. Except as +-- otherwise provided in a valid license issued to you by +-- Xilinx, and to the maximum extent permitted by applicable +-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +-- (2) Xilinx shall not be liable (whether in contract or tort, +-- including negligence, or under any other theory of +-- liability) for any loss or damage of any kind or nature +-- related to, arising under or in connection with these +-- materials, including for any direct, or any indirect, +-- special, incidental, or consequential loss or damage +-- (including loss of data, profits, goodwill, or any type of +-- loss or damage suffered as a result of any action brought +-- by a third party) even if such damage or loss was +-- reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail- +-- safe, or for use in any application requiring fail-safe +-- performance, such as life-support or safety devices or +-- systems, Class III medical devices, nuclear facilities, +-- applications related to the deployment of airbags, or any +-- other applications that could lead to death, personal +-- injury, or severe property or environmental damage +-- (individually and collectively, "Critical +-- Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical +-- Applications, subject only to applicable laws and +-- regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +-- PART OF THIS FILE AT ALL TIMES. +-- + ***************************************************************************** + * + * Filename: BLK_MEM_GEN_V4_1.v + * + * Description: + * This file is the Verilog behvarial model for the + * Block Memory Generator Core. + * + ***************************************************************************** + * Author: Xilinx + * + * History: Jan 11, 2006 Initial revision + * Jun 11, 2007 Added independent register stages for + * Port A and Port B (IP1_Jm/v2.5) + * Aug 28, 2007 Added mux pipeline stages feature (IP2_Jm/v2.6) + * Mar 13, 2008 Behavioral model optimizations + * April 07, 2009 : Added support for Spartan-6 and Virtex-6 + * features, including the following: + * (i) error injection, detection and/or correction + * (ii) reset priority + * (iii) special reset behavior + * + *****************************************************************************/ +`timescale 1ps/1ps + +//***************************************************************************** +// Output Register Stage module +// +// This module builds the output register stages of the memory. This module is +// instantiated in the main memory module (BLK_MEM_GEN_V4_1) which is +// declared/implemented further down in this file. +//***************************************************************************** + +module BLK_MEM_GEN_V4_1_output_stage + #(parameter C_FAMILY = "virtex5", + parameter C_XDEVICEFAMILY = "virtex5", + parameter C_RST_TYPE = "SYNC", + parameter C_HAS_RST = 0, + parameter C_RSTRAM = 0, + parameter C_RST_PRIORITY = "CE", + parameter C_INIT_VAL = "0", + parameter C_HAS_EN = 0, + parameter C_HAS_REGCE = 0, + parameter C_DATA_WIDTH = 32, + parameter C_ADDRB_WIDTH = 10, + parameter C_HAS_MEM_OUTPUT_REGS = 0, + parameter C_USE_SOFTECC = 0, + parameter C_USE_ECC = 0, + parameter NUM_STAGES = 1, + parameter FLOP_DELAY = 100 + ) + ( + input CLK, + input RST, + input EN, + input REGCE, + input [C_DATA_WIDTH-1:0] DIN, + output reg [C_DATA_WIDTH-1:0] DOUT, + input SBITERR_IN, + input DBITERR_IN, + output reg SBITERR, + output reg DBITERR, + input [C_ADDRB_WIDTH-1:0] RDADDRECC_IN, + output reg [C_ADDRB_WIDTH-1:0] RDADDRECC +); + +//****************************** +// Port and Generic Definitions +//****************************** + //------------------------------------------------------------------------- + // Generic Definitions + //------------------------------------------------------------------------- + // C_FAMILY,C_XDEVICEFAMILY: Designates architecture targeted. The following + // options are available - "spartan3", "spartan6", + // "virtex4", "virtex5", "virtex6" and "virtex6l". + // C_RST_TYPE : Type of reset - Synchronous or Asynchronous + // C_HAS_RST : Determines the presence of the RST port + // C_RSTRAM : Determines if special reset behavior is used + // C_RST_PRIORITY : Determines the priority between CE and SR + // C_INIT_VAL : Initialization value + // C_HAS_EN : Determines the presence of the EN port + // C_HAS_REGCE : Determines the presence of the REGCE port + // C_DATA_WIDTH : Memory write/read width + // C_ADDRB_WIDTH : Width of the ADDRB input port + // C_HAS_MEM_OUTPUT_REGS : Designates the use of a register at the output + // of the RAM primitive + // C_USE_SOFTECC : Determines if the Soft ECC feature is used or + // not. Only applicable Spartan-6 + // C_USE_ECC : Determines if the ECC feature is used or + // not. Only applicable for V5 and V6 + // NUM_STAGES : Determines the number of output stages + // FLOP_DELAY : Constant delay for register assignments + //------------------------------------------------------------------------- + // Port Definitions + //------------------------------------------------------------------------- + // CLK : Clock to synchronize all read and write operations + // RST : Reset input to reset memory outputs to a user-defined + // reset state + // EN : Enable all read and write operations + // REGCE : Register Clock Enable to control each pipeline output + // register stages + // DIN : Data input to the Output stage. + // DOUT : Final Data output + // SBITERR_IN : SBITERR input signal to the Output stage. + // SBITERR : Final SBITERR Output signal. + // DBITERR_IN : DBITERR input signal to the Output stage. + // DBITERR : Final DBITERR Output signal. + // RDADDRECC_IN : RDADDRECC input signal to the Output stage. + // RDADDRECC : Final RDADDRECC Output signal. + //------------------------------------------------------------------------- + +// Fix for CR-509792 +// localparam REG_STAGES = (NUM_STAGES == 0) ? 0 : NUM_STAGES-1; + localparam REG_STAGES = (NUM_STAGES < 2) ? 1 : NUM_STAGES-1; + + // Declare the pipeline registers + // (includes mem output reg, mux pipeline stages, and mux output reg) + reg [C_DATA_WIDTH*REG_STAGES-1:0] out_regs; + reg [C_ADDRB_WIDTH*REG_STAGES-1:0] rdaddrecc_regs; + reg [REG_STAGES-1:0] sbiterr_regs; + reg [REG_STAGES-1:0] dbiterr_regs; + + reg [C_DATA_WIDTH*8-1:0] init_str = C_INIT_VAL; + reg [C_DATA_WIDTH-1:0] init_val; + + //********************************************* + // Wire off optional inputs based on parameters + //********************************************* + wire en_i; + wire regce_i; + wire rst_i; + + // Internal enable for output registers is tied to user EN or '1' depending + // on parameters + assign en_i = (C_HAS_EN==0 || EN); + + // Internal register enable for output registers is tied to user REGCE, EN or + // '1' depending on parameters + // For V4 ECC, REGCE is always 1 + // Virtex-4 ECC Not Yet Supported + assign regce_i = ((C_HAS_REGCE==1) && REGCE) || + ((C_HAS_REGCE==0) && (C_HAS_EN==0 || EN)); + + //Internal SRR is tied to user RST or '0' depending on parameters + assign rst_i = (C_HAS_RST==1) && RST; + + //**************************************************** + // Power on: load up the output registers and latches + //**************************************************** + initial begin + if (!($sscanf(init_str, "%h", init_val))) begin + init_val = 0; + end + DOUT = init_val; + RDADDRECC = 0; + SBITERR = 1'b0; + DBITERR = 1'b0; + // This will be one wider than need, but 0 is an error + out_regs = {(REG_STAGES+1){init_val}}; + rdaddrecc_regs = 0; + sbiterr_regs = {(REG_STAGES+1){1'b0}}; + dbiterr_regs = {(REG_STAGES+1){1'b0}}; + end + + //*********************************************** + // NUM_STAGES = 0 (No output registers. RAM only) + //*********************************************** + generate if (NUM_STAGES == 0) begin : zero_stages + always @* begin + DOUT = DIN; + RDADDRECC = RDADDRECC_IN; + SBITERR = SBITERR_IN; + DBITERR = DBITERR_IN; + end + end + endgenerate + + //*********************************************** + // NUM_STAGES = 1 + // (Mem Output Reg only or Mux Output Reg only) + //*********************************************** + + // Possible valid combinations: + // Note: C_HAS_MUX_OUTPUT_REGS_*=0 when (C_RSTRAM_*=1) + // +-----------------------------------------+ + // | C_RSTRAM_* | Reset Behavior | + // +----------------+------------------------+ + // | 0 | Normal Behavior | + // +----------------+------------------------+ + // | 1 | Special Behavior | + // +----------------+------------------------+ + // + // Normal = REGCE gates reset, as in the case of all families except S3ADSP. + // Special = EN gates reset, as in the case of S3ADSP. + + generate if (NUM_STAGES == 1 && + (C_RSTRAM == 0 || (C_RSTRAM == 1 && (C_XDEVICEFAMILY != "spartan3adsp" && C_XDEVICEFAMILY != "aspartan3adsp" )) || + C_HAS_MEM_OUTPUT_REGS == 0 || C_HAS_RST == 0)) + begin : one_stages_norm + //Asynchronous Reset + if ((C_FAMILY == "spartan6") && C_RST_TYPE == "ASYNC") begin + if(C_RST_PRIORITY == "CE") begin //REGCE has priority + always @ (*) begin + if (rst_i && regce_i) DOUT = init_val; + end + always @ (posedge CLK) begin + if (!rst_i && regce_i) DOUT <= #FLOP_DELAY DIN; + end //CLK + end else begin //RST has priority + always @ (*) begin + if (rst_i) DOUT = init_val; + end + always @ (posedge CLK) begin + if (!rst_i && regce_i) DOUT <= #FLOP_DELAY DIN; + end //CLK + end //end Priority conditions + //Synchronous Reset + end else begin + always @(posedge CLK) begin + if (C_RST_PRIORITY == "CE") begin //REGCE has priority + if (regce_i && rst_i) begin + DOUT <= #FLOP_DELAY init_val; + RDADDRECC <= #FLOP_DELAY 0; + SBITERR <= #FLOP_DELAY 1'b0; + DBITERR <= #FLOP_DELAY 1'b0; + end else if (regce_i) begin + DOUT <= #FLOP_DELAY DIN; + RDADDRECC <= #FLOP_DELAY RDADDRECC_IN; + SBITERR <= #FLOP_DELAY SBITERR_IN; + DBITERR <= #FLOP_DELAY DBITERR_IN; + end //Output signal assignments + end else begin //RST has priority + if (rst_i) begin + DOUT <= #FLOP_DELAY init_val; + RDADDRECC <= #FLOP_DELAY RDADDRECC_IN; + SBITERR <= #FLOP_DELAY 1'b0; + DBITERR <= #FLOP_DELAY 1'b0; + end else if (regce_i) begin + DOUT <= #FLOP_DELAY DIN; + RDADDRECC <= #FLOP_DELAY RDADDRECC_IN; + SBITERR <= #FLOP_DELAY SBITERR_IN; + DBITERR <= #FLOP_DELAY DBITERR_IN; + end //Output signal assignments + end //end Priority conditions + end //CLK + end //end RST Type conditions + end //end one_stages_norm generate statement + endgenerate + + // Special Reset Behavior for S3ADSP + generate if (NUM_STAGES == 1 && C_RSTRAM == 1 && (C_XDEVICEFAMILY =="spartan3adsp" || C_XDEVICEFAMILY =="aspartan3adsp")) + begin : one_stage_splbhv + always @(posedge CLK) begin + if (en_i && rst_i) begin + DOUT <= #FLOP_DELAY init_val; + end else if (regce_i && !rst_i) begin + DOUT <= #FLOP_DELAY DIN; + end //Output signal assignments + end //end CLK + end //end one_stage_splbhv generate statement + endgenerate + + //************************************************************ + // NUM_STAGES > 1 + // Mem Output Reg + Mux Output Reg + // or + // Mem Output Reg + Mux Pipeline Stages (>0) + Mux Output Reg + // or + // Mux Pipeline Stages (>0) + Mux Output Reg + //************************************************************* + generate if (NUM_STAGES > 1) begin : multi_stage + //Asynchronous Reset + if ((C_FAMILY == "spartan6") && C_RST_TYPE == "ASYNC") begin + if(C_RST_PRIORITY == "CE") begin //REGCE has priority + always @ (*) begin + if (rst_i && regce_i) DOUT = init_val; + end + always @ (posedge CLK) begin + if (!rst_i && regce_i) + DOUT <= #FLOP_DELAY out_regs[C_DATA_WIDTH*(NUM_STAGES-2)+:C_DATA_WIDTH]; + end //CLK + end else begin //RST has priority + always @ (*) begin + if (rst_i) DOUT = init_val; + end + always @ (posedge CLK) begin + if (!rst_i && regce_i) + DOUT <= #FLOP_DELAY out_regs[C_DATA_WIDTH*(NUM_STAGES-2)+:C_DATA_WIDTH]; + end //CLK + end //end Priority conditions + always @ (posedge CLK) begin + if (en_i) begin + out_regs <= (out_regs << C_DATA_WIDTH) | DIN; + end + end + //Synchronous Reset + end else begin + always @(posedge CLK) begin + if (C_RST_PRIORITY == "CE") begin //REGCE has priority + if (regce_i && rst_i) begin + DOUT <= #FLOP_DELAY init_val; + RDADDRECC <= #FLOP_DELAY 0; + SBITERR <= #FLOP_DELAY 1'b0; + DBITERR <= #FLOP_DELAY 1'b0; + end else if (regce_i) begin + DOUT <= #FLOP_DELAY + out_regs[C_DATA_WIDTH*(NUM_STAGES-2)+:C_DATA_WIDTH]; + RDADDRECC <= #FLOP_DELAY rdaddrecc_regs[C_ADDRB_WIDTH*(NUM_STAGES-2)+:C_ADDRB_WIDTH]; + SBITERR <= #FLOP_DELAY sbiterr_regs[NUM_STAGES-2]; + DBITERR <= #FLOP_DELAY dbiterr_regs[NUM_STAGES-2]; + end //Output signal assignments + end else begin //RST has priority + if (rst_i) begin + DOUT <= #FLOP_DELAY init_val; + RDADDRECC <= #FLOP_DELAY 0; + SBITERR <= #FLOP_DELAY 1'b0; + DBITERR <= #FLOP_DELAY 1'b0; + end else if (regce_i) begin + DOUT <= #FLOP_DELAY + out_regs[C_DATA_WIDTH*(NUM_STAGES-2)+:C_DATA_WIDTH]; + RDADDRECC <= #FLOP_DELAY rdaddrecc_regs[C_ADDRB_WIDTH*(NUM_STAGES-2)+:C_ADDRB_WIDTH]; + SBITERR <= #FLOP_DELAY sbiterr_regs[NUM_STAGES-2]; + DBITERR <= #FLOP_DELAY dbiterr_regs[NUM_STAGES-2]; + end //Output signal assignments + end //end Priority conditions + // Shift the data through the output stages + if (en_i) begin + out_regs <= #FLOP_DELAY (out_regs << C_DATA_WIDTH) | DIN; + rdaddrecc_regs <= #FLOP_DELAY (rdaddrecc_regs << C_ADDRB_WIDTH) | RDADDRECC_IN; + sbiterr_regs <= #FLOP_DELAY (sbiterr_regs << 1) | SBITERR_IN; + dbiterr_regs <= #FLOP_DELAY (dbiterr_regs << 1) | DBITERR_IN; + end + end //end CLK + end //end RST Type conditions + end //end multi_stage generate statement + endgenerate +endmodule + +module BLK_MEM_GEN_V4_1_softecc_output_reg_stage + #(parameter C_DATA_WIDTH = 32, + parameter C_ADDRB_WIDTH = 10, + parameter C_HAS_SOFTECC_OUTPUT_REGS_A= 0, + parameter C_HAS_SOFTECC_OUTPUT_REGS_B= 0, + parameter C_USE_SOFTECC = 0, + parameter FLOP_DELAY = 100 + ) + ( + input CLK, + input [C_DATA_WIDTH-1:0] DIN, + output reg [C_DATA_WIDTH-1:0] DOUT, + input SBITERR_IN, + input DBITERR_IN, + output reg SBITERR, + output reg DBITERR, + input [C_ADDRB_WIDTH-1:0] RDADDRECC_IN, + output reg [C_ADDRB_WIDTH-1:0] RDADDRECC +); + +//****************************** +// Port and Generic Definitions +//****************************** + //------------------------------------------------------------------------- + // Generic Definitions + //------------------------------------------------------------------------- + // C_DATA_WIDTH : Memory write/read width + // C_ADDRB_WIDTH : Width of the ADDRB input port + // C_HAS_SOFTECC_OUTPUT_REGS_B : Designates the use of a register at the output + // of the RAM primitive + // C_USE_SOFTECC : Determines if the Soft ECC feature is used or + // not. Only applicable Spartan-6 + // FLOP_DELAY : Constant delay for register assignments + //------------------------------------------------------------------------- + // Port Definitions + //------------------------------------------------------------------------- + // CLK : Clock to synchronize all read and write operations + // DIN : Data input to the Output stage. + // DOUT : Final Data output + // SBITERR_IN : SBITERR input signal to the Output stage. + // SBITERR : Final SBITERR Output signal. + // DBITERR_IN : DBITERR input signal to the Output stage. + // DBITERR : Final DBITERR Output signal. + // RDADDRECC_IN : RDADDRECC input signal to the Output stage. + // RDADDRECC : Final RDADDRECC Output signal. + //------------------------------------------------------------------------- + + reg [C_DATA_WIDTH-1:0] dout_i = 0; + reg sbiterr_i = 0; + reg dbiterr_i = 0; + reg [C_ADDRB_WIDTH-1:0] rdaddrecc_i = 0; + + //*********************************************** + // NO OUTPUT REGISTERS. + //*********************************************** + generate if (C_HAS_SOFTECC_OUTPUT_REGS_B==0) begin : no_output_stage + always @* begin + DOUT = DIN; + RDADDRECC = RDADDRECC_IN; + SBITERR = SBITERR_IN; + DBITERR = DBITERR_IN; + end + end + endgenerate + + //*********************************************** + // WITH OUTPUT REGISTERS. + //*********************************************** + generate if (C_HAS_SOFTECC_OUTPUT_REGS_B==1) begin : has_output_stage + always @(posedge CLK) begin + dout_i <= #FLOP_DELAY DIN; + rdaddrecc_i <= #FLOP_DELAY RDADDRECC_IN; + sbiterr_i <= #FLOP_DELAY SBITERR_IN; + dbiterr_i <= #FLOP_DELAY DBITERR_IN; + end //end CLK + + always @* begin + DOUT = dout_i; + RDADDRECC = rdaddrecc_i; + SBITERR = sbiterr_i; + DBITERR = dbiterr_i; + end //end always + end //end in_or_out_stage generate statement + endgenerate + +endmodule + + +//***************************************************************************** +// Main Memory module +// +// This module is the top-level behavioral model and this implements the RAM +//***************************************************************************** +module BLK_MEM_GEN_V4_1_mem_module + #(parameter C_CORENAME = "blk_mem_gen_v4_1", + parameter C_FAMILY = "virtex6", + parameter C_XDEVICEFAMILY = "virtex6", + parameter C_MEM_TYPE = 2, + parameter C_BYTE_SIZE = 9, + parameter C_ALGORITHM = 1, + parameter C_PRIM_TYPE = 3, + parameter C_LOAD_INIT_FILE = 0, + parameter C_INIT_FILE_NAME = "", + parameter C_USE_DEFAULT_DATA = 0, + parameter C_DEFAULT_DATA = "0", + parameter C_RST_TYPE = "SYNC", + parameter C_HAS_RSTA = 0, + parameter C_RST_PRIORITY_A = "CE", + parameter C_RSTRAM_A = 0, + parameter C_INITA_VAL = "0", + parameter C_HAS_ENA = 1, + parameter C_HAS_REGCEA = 0, + parameter C_USE_BYTE_WEA = 0, + parameter C_WEA_WIDTH = 1, + parameter C_WRITE_MODE_A = "WRITE_FIRST", + parameter C_WRITE_WIDTH_A = 32, + parameter C_READ_WIDTH_A = 32, + parameter C_WRITE_DEPTH_A = 64, + parameter C_READ_DEPTH_A = 64, + parameter C_ADDRA_WIDTH = 5, + parameter C_HAS_RSTB = 0, + parameter C_RST_PRIORITY_B = "CE", + parameter C_RSTRAM_B = 0, + parameter C_INITB_VAL = "0", + parameter C_HAS_ENB = 1, + parameter C_HAS_REGCEB = 0, + parameter C_USE_BYTE_WEB = 0, + parameter C_WEB_WIDTH = 1, + parameter C_WRITE_MODE_B = "WRITE_FIRST", + parameter C_WRITE_WIDTH_B = 32, + parameter C_READ_WIDTH_B = 32, + parameter C_WRITE_DEPTH_B = 64, + parameter C_READ_DEPTH_B = 64, + parameter C_ADDRB_WIDTH = 5, + parameter C_HAS_MEM_OUTPUT_REGS_A = 0, + parameter C_HAS_MEM_OUTPUT_REGS_B = 0, + parameter C_HAS_MUX_OUTPUT_REGS_A = 0, + parameter C_HAS_MUX_OUTPUT_REGS_B = 0, + parameter C_HAS_SOFTECC_INPUT_REGS_A = 0, + parameter C_HAS_SOFTECC_INPUT_REGS_B = 0, + parameter C_HAS_SOFTECC_OUTPUT_REGS_A= 0, + parameter C_HAS_SOFTECC_OUTPUT_REGS_B= 0, + parameter C_MUX_PIPELINE_STAGES = 0, + parameter C_USE_SOFTECC = 0, + parameter C_USE_ECC = 0, + parameter C_HAS_INJECTERR = 0, + parameter C_SIM_COLLISION_CHECK = "NONE", + parameter C_COMMON_CLK = 1, + parameter FLOP_DELAY = 100, + parameter C_DISABLE_WARN_BHV_COLL = 0, + parameter C_DISABLE_WARN_BHV_RANGE = 0 + ) + (input CLKA, + input RSTA, + input ENA, + input REGCEA, + input [C_WEA_WIDTH-1:0] WEA, + input [C_ADDRA_WIDTH-1:0] ADDRA, + input [C_WRITE_WIDTH_A-1:0] DINA, + output [C_READ_WIDTH_A-1:0] DOUTA, + input CLKB, + input RSTB, + input ENB, + input REGCEB, + input [C_WEB_WIDTH-1:0] WEB, + input [C_ADDRB_WIDTH-1:0] ADDRB, + input [C_WRITE_WIDTH_B-1:0] DINB, + output [C_READ_WIDTH_B-1:0] DOUTB, + input INJECTSBITERR, + input INJECTDBITERR, + output SBITERR, + output DBITERR, + output [C_ADDRB_WIDTH-1:0] RDADDRECC + ); +//****************************** +// Port and Generic Definitions +//****************************** + //------------------------------------------------------------------------- + // Generic Definitions + //------------------------------------------------------------------------- + // C_CORENAME : Instance name of the Block Memory Generator core + // C_FAMILY,C_XDEVICEFAMILY: Designates architecture targeted. The following + // options are available - "spartan3", "spartan6", + // "virtex4", "virtex5", "virtex6" and "virtex6l". + // C_MEM_TYPE : Designates memory type. + // It can be + // 0 - Single Port Memory + // 1 - Simple Dual Port Memory + // 2 - True Dual Port Memory + // 3 - Single Port Read Only Memory + // 4 - Dual Port Read Only Memory + // C_BYTE_SIZE : Size of a byte (8 or 9 bits) + // C_ALGORITHM : Designates the algorithm method used + // for constructing the memory. + // It can be Fixed_Primitives, Minimum_Area or + // Low_Power + // C_PRIM_TYPE : Designates the user selected primitive used to + // construct the memory. + // + // C_LOAD_INIT_FILE : Designates the use of an initialization file to + // initialize memory contents. + // C_INIT_FILE_NAME : Memory initialization file name. + // C_USE_DEFAULT_DATA : Designates whether to fill remaining + // initialization space with default data + // C_DEFAULT_DATA : Default value of all memory locations + // not initialized by the memory + // initialization file. + // C_RST_TYPE : Type of reset - Synchronous or Asynchronous + // C_HAS_RSTA : Determines the presence of the RSTA port + // C_RST_PRIORITY_A : Determines the priority between CE and SR for + // Port A. + // C_RSTRAM_A : Determines if special reset behavior is used for + // Port A + // C_INITA_VAL : The initialization value for Port A + // C_HAS_ENA : Determines the presence of the ENA port + // C_HAS_REGCEA : Determines the presence of the REGCEA port + // C_USE_BYTE_WEA : Determines if the Byte Write is used or not. + // C_WEA_WIDTH : The width of the WEA port + // C_WRITE_MODE_A : Configurable write mode for Port A. It can be + // WRITE_FIRST, READ_FIRST or NO_CHANGE. + // C_WRITE_WIDTH_A : Memory write width for Port A. + // C_READ_WIDTH_A : Memory read width for Port A. + // C_WRITE_DEPTH_A : Memory write depth for Port A. + // C_READ_DEPTH_A : Memory read depth for Port A. + // C_ADDRA_WIDTH : Width of the ADDRA input port + // C_HAS_RSTB : Determines the presence of the RSTB port + // C_RST_PRIORITY_B : Determines the priority between CE and SR for + // Port B. + // C_RSTRAM_B : Determines if special reset behavior is used for + // Port B + // C_INITB_VAL : The initialization value for Port B + // C_HAS_ENB : Determines the presence of the ENB port + // C_HAS_REGCEB : Determines the presence of the REGCEB port + // C_USE_BYTE_WEB : Determines if the Byte Write is used or not. + // C_WEB_WIDTH : The width of the WEB port + // C_WRITE_MODE_B : Configurable write mode for Port B. It can be + // WRITE_FIRST, READ_FIRST or NO_CHANGE. + // C_WRITE_WIDTH_B : Memory write width for Port B. + // C_READ_WIDTH_B : Memory read width for Port B. + // C_WRITE_DEPTH_B : Memory write depth for Port B. + // C_READ_DEPTH_B : Memory read depth for Port B. + // C_ADDRB_WIDTH : Width of the ADDRB input port + // C_HAS_MEM_OUTPUT_REGS_A : Designates the use of a register at the output + // of the RAM primitive for Port A. + // C_HAS_MEM_OUTPUT_REGS_B : Designates the use of a register at the output + // of the RAM primitive for Port B. + // C_HAS_MUX_OUTPUT_REGS_A : Designates the use of a register at the output + // of the MUX for Port A. + // C_HAS_MUX_OUTPUT_REGS_B : Designates the use of a register at the output + // of the MUX for Port B. + // C_MUX_PIPELINE_STAGES : Designates the number of pipeline stages in + // between the muxes. + // C_USE_SOFTECC : Determines if the Soft ECC feature is used or + // not. Only applicable Spartan-6 + // C_USE_ECC : Determines if the ECC feature is used or + // not. Only applicable for V5 and V6 + // C_HAS_INJECTERR : Determines if the error injection pins + // are present or not. If the ECC feature + // is not used, this value is defaulted to + // 0, else the following are the allowed + // values: + // 0 : No INJECTSBITERR or INJECTDBITERR pins + // 1 : Only INJECTSBITERR pin exists + // 2 : Only INJECTDBITERR pin exists + // 3 : Both INJECTSBITERR and INJECTDBITERR pins exist + // C_SIM_COLLISION_CHECK : Controls the disabling of Unisim model collision + // warnings. It can be "ALL", "NONE", + // "Warnings_Only" or "Generate_X_Only". + // C_COMMON_CLK : Determins if the core has a single CLK input. + // C_DISABLE_WARN_BHV_COLL : Controls the Behavioral Model Collision warnings + // C_DISABLE_WARN_BHV_RANGE: Controls the Behavioral Model Out of Range + // warnings + //------------------------------------------------------------------------- + // Port Definitions + //------------------------------------------------------------------------- + // CLKA : Clock to synchronize all read and write operations of Port A. + // RSTA : Reset input to reset memory outputs to a user-defined + // reset state for Port A. + // ENA : Enable all read and write operations of Port A. + // REGCEA : Register Clock Enable to control each pipeline output + // register stages for Port A. + // WEA : Write Enable to enable all write operations of Port A. + // ADDRA : Address of Port A. + // DINA : Data input of Port A. + // DOUTA : Data output of Port A. + // CLKB : Clock to synchronize all read and write operations of Port B. + // RSTB : Reset input to reset memory outputs to a user-defined + // reset state for Port B. + // ENB : Enable all read and write operations of Port B. + // REGCEB : Register Clock Enable to control each pipeline output + // register stages for Port B. + // WEB : Write Enable to enable all write operations of Port B. + // ADDRB : Address of Port B. + // DINB : Data input of Port B. + // DOUTB : Data output of Port B. + // INJECTSBITERR : Single Bit ECC Error Injection Pin. + // INJECTDBITERR : Double Bit ECC Error Injection Pin. + // SBITERR : Output signal indicating that a Single Bit ECC Error has been + // detected and corrected. + // DBITERR : Output signal indicating that a Double Bit ECC Error has been + // detected. + // RDADDRECC : Read Address Output signal indicating address at which an + // ECC error has occurred. + //------------------------------------------------------------------------- + + +// Note: C_CORENAME parameter is hard-coded to "blk_mem_gen_v4_1" and it is +// only used by this module to print warning messages. It is neither passed +// down from blk_mem_gen_v4_1_xst.v nor present in the instantiation template +// coregen generates + + //*************************************************************************** + // constants for the core behavior + //*************************************************************************** + // file handles for logging + //-------------------------------------------------- + localparam ADDRFILE = 32'h8000_0001; //stdout for addr out of range + localparam COLLFILE = 32'h8000_0001; //stdout for coll detection + localparam ERRFILE = 32'h8000_0001; //stdout for file I/O errors + + // other constants + //-------------------------------------------------- + localparam COLL_DELAY = 2000; // 2 ns + + // locally derived parameters to determine memory shape + //----------------------------------------------------- + + localparam CHKBIT_WIDTH = (C_WRITE_WIDTH_A>57 ? 8 : (C_WRITE_WIDTH_A>26 ? 7 : (C_WRITE_WIDTH_A>11 ? 6 : (C_WRITE_WIDTH_A>4 ? 5 : (C_WRITE_WIDTH_A<5 ? 4 :0))))); + + localparam MIN_WIDTH_A = (C_WRITE_WIDTH_A < C_READ_WIDTH_A) ? + C_WRITE_WIDTH_A : C_READ_WIDTH_A; + localparam MIN_WIDTH_B = (C_WRITE_WIDTH_B < C_READ_WIDTH_B) ? + C_WRITE_WIDTH_B : C_READ_WIDTH_B; + localparam MIN_WIDTH = (MIN_WIDTH_A < MIN_WIDTH_B) ? + MIN_WIDTH_A : MIN_WIDTH_B; + + localparam MAX_DEPTH_A = (C_WRITE_DEPTH_A > C_READ_DEPTH_A) ? + C_WRITE_DEPTH_A : C_READ_DEPTH_A; + localparam MAX_DEPTH_B = (C_WRITE_DEPTH_B > C_READ_DEPTH_B) ? + C_WRITE_DEPTH_B : C_READ_DEPTH_B; + localparam MAX_DEPTH = (MAX_DEPTH_A > MAX_DEPTH_B) ? + MAX_DEPTH_A : MAX_DEPTH_B; + + + // locally derived parameters to assist memory access + //---------------------------------------------------- + // Calculate the width ratios of each port with respect to the narrowest + // port + localparam WRITE_WIDTH_RATIO_A = C_WRITE_WIDTH_A/MIN_WIDTH; + localparam READ_WIDTH_RATIO_A = C_READ_WIDTH_A/MIN_WIDTH; + localparam WRITE_WIDTH_RATIO_B = C_WRITE_WIDTH_B/MIN_WIDTH; + localparam READ_WIDTH_RATIO_B = C_READ_WIDTH_B/MIN_WIDTH; + + // To modify the LSBs of the 'wider' data to the actual + // address value + //---------------------------------------------------- + localparam WRITE_ADDR_A_DIV = C_WRITE_WIDTH_A/MIN_WIDTH_A; + localparam READ_ADDR_A_DIV = C_READ_WIDTH_A/MIN_WIDTH_A; + localparam WRITE_ADDR_B_DIV = C_WRITE_WIDTH_B/MIN_WIDTH_B; + localparam READ_ADDR_B_DIV = C_READ_WIDTH_B/MIN_WIDTH_B; + + // If byte writes aren't being used, make sure BYTE_SIZE is not + // wider than the memory elements to avoid compilation warnings + localparam BYTE_SIZE = (C_BYTE_SIZE < MIN_WIDTH) ? C_BYTE_SIZE : MIN_WIDTH; + + // The memory + reg [MIN_WIDTH-1:0] memory [0:MAX_DEPTH-1]; + reg [C_WRITE_WIDTH_A+CHKBIT_WIDTH-1:0] doublebit_error = 3; + // ECC error arrays + reg sbiterr_arr [0:MAX_DEPTH-1]; + reg dbiterr_arr [0:MAX_DEPTH-1]; + + reg softecc_sbiterr_arr [0:MAX_DEPTH-1]; + reg softecc_dbiterr_arr [0:MAX_DEPTH-1]; + // Memory output 'latches' + reg [C_READ_WIDTH_A-1:0] memory_out_a; + reg [C_READ_WIDTH_B-1:0] memory_out_b; + + // ECC error inputs and outputs from output_stage module: + reg sbiterr_in; + wire sbiterr_sdp; + reg dbiterr_in; + wire dbiterr_sdp; + + wire [C_READ_WIDTH_B-1:0] dout_i; + wire dbiterr_i; + wire sbiterr_i; + wire [C_ADDRB_WIDTH-1:0] rdaddrecc_i; + + reg [C_ADDRB_WIDTH-1:0] rdaddrecc_in; + wire [C_ADDRB_WIDTH-1:0] rdaddrecc_sdp; + + // Reset values + reg [C_READ_WIDTH_A-1:0] inita_val; + reg [C_READ_WIDTH_B-1:0] initb_val; + + // Collision detect + reg is_collision; + reg is_collision_a, is_collision_delay_a; + reg is_collision_b, is_collision_delay_b; + + // Temporary variables for initialization + //--------------------------------------- + integer status; + integer initfile; + // data input buffer + reg [C_WRITE_WIDTH_A-1:0] mif_data; + // string values in hex + reg [C_READ_WIDTH_A*8-1:0] inita_str = C_INITA_VAL; + reg [C_READ_WIDTH_B*8-1:0] initb_str = C_INITB_VAL; + reg [C_WRITE_WIDTH_A*8-1:0] default_data_str = C_DEFAULT_DATA; + // initialization filename + reg [1023*8-1:0] init_file_str = C_INIT_FILE_NAME; + + + //Constants used to calculate the effective address widths for each of the + //four ports. + integer cnt = 1; + integer write_addr_a_width, read_addr_a_width; + integer write_addr_b_width, read_addr_b_width; + + + // Internal configuration parameters + //--------------------------------------------- + localparam SINGLE_PORT = (C_MEM_TYPE==0 || C_MEM_TYPE==3); + localparam IS_ROM = (C_MEM_TYPE==3 || C_MEM_TYPE==4); + localparam HAS_A_WRITE = (!IS_ROM); + localparam HAS_B_WRITE = (C_MEM_TYPE==2); + localparam HAS_A_READ = (C_MEM_TYPE!=1); + localparam HAS_B_READ = (!SINGLE_PORT); + localparam HAS_B_PORT = (HAS_B_READ || HAS_B_WRITE); + + // Calculate the mux pipeline register stages for Port A and Port B + //------------------------------------------------------------------ + localparam MUX_PIPELINE_STAGES_A = (C_HAS_MUX_OUTPUT_REGS_A) ? + C_MUX_PIPELINE_STAGES : 0; + localparam MUX_PIPELINE_STAGES_B = (C_HAS_MUX_OUTPUT_REGS_B) ? + C_MUX_PIPELINE_STAGES : 0; + + // Calculate total number of register stages in the core + // ----------------------------------------------------- + localparam NUM_OUTPUT_STAGES_A = (C_HAS_MEM_OUTPUT_REGS_A+MUX_PIPELINE_STAGES_A+C_HAS_MUX_OUTPUT_REGS_A); + + localparam NUM_OUTPUT_STAGES_B = (C_HAS_MEM_OUTPUT_REGS_B+MUX_PIPELINE_STAGES_B+C_HAS_MUX_OUTPUT_REGS_B); + + wire ena_i; + wire enb_i; + wire reseta_i; + wire resetb_i; + wire [C_WEA_WIDTH-1:0] wea_i; + wire [C_WEB_WIDTH-1:0] web_i; + wire rea_i; + wire reb_i; + + // ECC SBITERR/DBITERR Outputs + // The ECC Behavior is modeled by the behavioral models only for Virtex-6. + // For Virtex-5, these outputs will be tied to 0. + assign SBITERR = ((C_MEM_TYPE == 1 && C_USE_ECC == 1) || C_USE_SOFTECC == 1)?sbiterr_sdp:0; + assign DBITERR = ((C_MEM_TYPE == 1 && C_USE_ECC == 1) || C_USE_SOFTECC == 1)?dbiterr_sdp:0; + assign RDADDRECC = (((C_FAMILY == "virtex6") && C_MEM_TYPE == 1 && C_USE_ECC == 1) || C_USE_SOFTECC == 1)?rdaddrecc_sdp:0; + + + // This effectively wires off optional inputs + assign ena_i = (C_HAS_ENA==0) || ENA; + assign enb_i = ((C_HAS_ENB==0) || ENB) && HAS_B_PORT; + assign wea_i = (HAS_A_WRITE && ena_i) ? WEA : 'b0; + assign web_i = (HAS_B_WRITE && enb_i) ? WEB : 'b0; + assign rea_i = (HAS_A_READ) ? ena_i : 'b0; + assign reb_i = (HAS_B_READ) ? enb_i : 'b0; + + // These signals reset the memory latches + + assign reseta_i = + ((C_HAS_RSTA==1 && RSTA && NUM_OUTPUT_STAGES_A==0) || + (C_HAS_RSTA==1 && RSTA && C_RSTRAM_A==1)); + + assign resetb_i = + ((C_HAS_RSTB==1 && RSTB && NUM_OUTPUT_STAGES_B==0) || + (C_HAS_RSTB==1 && RSTB && C_RSTRAM_B==1)); + + // Tasks to access the memory + //--------------------------- + //************** + // write_a + //************** + task write_a + (input reg [C_ADDRA_WIDTH-1:0] addr, + input reg [C_WEA_WIDTH-1:0] byte_en, + input reg [C_WRITE_WIDTH_A-1:0] data, + input inj_sbiterr, + input inj_dbiterr); + reg [C_WRITE_WIDTH_A-1:0] current_contents; + reg [C_ADDRA_WIDTH-1:0] address; + integer i; + begin + // Shift the address by the ratio + address = (addr/WRITE_ADDR_A_DIV); + if (address >= C_WRITE_DEPTH_A) begin + if (!C_DISABLE_WARN_BHV_RANGE) begin + $fdisplay(ADDRFILE, + "%0s WARNING: Address %0h is outside range for A Write", + C_CORENAME, addr); + end + + // valid address + end else begin + + // Combine w/ byte writes + if (C_USE_BYTE_WEA) begin + + // Get the current memory contents + if (WRITE_WIDTH_RATIO_A == 1) begin + // Workaround for IUS 5.5 part-select issue + current_contents = memory[address]; + end else begin + for (i = 0; i < WRITE_WIDTH_RATIO_A; i = i + 1) begin + current_contents[MIN_WIDTH*i+:MIN_WIDTH] + = memory[address*WRITE_WIDTH_RATIO_A + i]; + end + end + + // Apply incoming bytes + if (C_WEA_WIDTH == 1) begin + // Workaround for IUS 5.5 part-select issue + if (byte_en[0]) begin + current_contents = data; + end + end else begin + for (i = 0; i < C_WEA_WIDTH; i = i + 1) begin + if (byte_en[i]) begin + current_contents[BYTE_SIZE*i+:BYTE_SIZE] + = data[BYTE_SIZE*i+:BYTE_SIZE]; + end + end + end + + // No byte-writes, overwrite the whole word + end else begin + current_contents = data; + end + + // Insert double bit errors: + if (C_USE_ECC == 1) begin + if ((C_HAS_INJECTERR == 2 || C_HAS_INJECTERR == 3) && inj_dbiterr == 1'b1) begin + current_contents[0] = !(current_contents[0]); + current_contents[1] = !(current_contents[1]); + end + end + + // Insert softecc double bit errors: + if (C_USE_SOFTECC == 1) begin + if ((C_HAS_INJECTERR == 2 || C_HAS_INJECTERR == 3) && inj_dbiterr == 1'b1) begin + doublebit_error[C_WRITE_WIDTH_A+CHKBIT_WIDTH-1:2] = doublebit_error[C_WRITE_WIDTH_A+CHKBIT_WIDTH-3:0]; + doublebit_error[0] = doublebit_error[C_WRITE_WIDTH_A+CHKBIT_WIDTH-1]; + doublebit_error[1] = doublebit_error[C_WRITE_WIDTH_A+CHKBIT_WIDTH-2]; + current_contents = current_contents ^ doublebit_error[C_WRITE_WIDTH_A-1:0]; + end + end + + // Write data to memory + if (WRITE_WIDTH_RATIO_A == 1) begin + // Workaround for IUS 5.5 part-select issue + memory[address*WRITE_WIDTH_RATIO_A] = current_contents; + end else begin + for (i = 0; i < WRITE_WIDTH_RATIO_A; i = i + 1) begin + memory[address*WRITE_WIDTH_RATIO_A + i] + = current_contents[MIN_WIDTH*i+:MIN_WIDTH]; + end + end + + // Store the address at which error is injected: + if ((C_FAMILY == "virtex6") && C_USE_ECC == 1) begin + if ((C_HAS_INJECTERR == 1 && inj_sbiterr == 1'b1) || + (C_HAS_INJECTERR == 3 && inj_sbiterr == 1'b1 && inj_dbiterr != 1'b1)) + begin + sbiterr_arr[addr] = 1; + end else begin + sbiterr_arr[addr] = 0; + end + + if ((C_HAS_INJECTERR == 2 || C_HAS_INJECTERR == 3) && inj_dbiterr == 1'b1) begin + dbiterr_arr[addr] = 1; + end else begin + dbiterr_arr[addr] = 0; + end + end + + // Store the address at which softecc error is injected: + if (C_USE_SOFTECC == 1) begin + if ((C_HAS_INJECTERR == 1 && inj_sbiterr == 1'b1) || + (C_HAS_INJECTERR == 3 && inj_sbiterr == 1'b1 && inj_dbiterr != 1'b1)) + begin + softecc_sbiterr_arr[addr] = 1; + end else begin + softecc_sbiterr_arr[addr] = 0; + end + + if ((C_HAS_INJECTERR == 2 || C_HAS_INJECTERR == 3) && inj_dbiterr == 1'b1) begin + softecc_dbiterr_arr[addr] = 1; + end else begin + softecc_dbiterr_arr[addr] = 0; + end + end + + end + end + endtask + + //************** + // write_b + //************** + task write_b + (input reg [C_ADDRB_WIDTH-1:0] addr, + input reg [C_WEB_WIDTH-1:0] byte_en, + input reg [C_WRITE_WIDTH_B-1:0] data); + reg [C_WRITE_WIDTH_B-1:0] current_contents; + reg [C_ADDRB_WIDTH-1:0] address; + integer i; + begin + // Shift the address by the ratio + address = (addr/WRITE_ADDR_B_DIV); + if (address >= C_WRITE_DEPTH_B) begin + if (!C_DISABLE_WARN_BHV_RANGE) begin + $fdisplay(ADDRFILE, + "%0s WARNING: Address %0h is outside range for B Write", + C_CORENAME, addr); + end + + // valid address + end else begin + + // Combine w/ byte writes + if (C_USE_BYTE_WEB) begin + + // Get the current memory contents + if (WRITE_WIDTH_RATIO_B == 1) begin + // Workaround for IUS 5.5 part-select issue + current_contents = memory[address]; + end else begin + for (i = 0; i < WRITE_WIDTH_RATIO_B; i = i + 1) begin + current_contents[MIN_WIDTH*i+:MIN_WIDTH] + = memory[address*WRITE_WIDTH_RATIO_B + i]; + end + end + + // Apply incoming bytes + if (C_WEB_WIDTH == 1) begin + // Workaround for IUS 5.5 part-select issue + if (byte_en[0]) begin + current_contents = data; + end + end else begin + for (i = 0; i < C_WEB_WIDTH; i = i + 1) begin + if (byte_en[i]) begin + current_contents[BYTE_SIZE*i+:BYTE_SIZE] + = data[BYTE_SIZE*i+:BYTE_SIZE]; + end + end + end + + // No byte-writes, overwrite the whole word + end else begin + current_contents = data; + end + + // Write data to memory + if (WRITE_WIDTH_RATIO_B == 1) begin + // Workaround for IUS 5.5 part-select issue + memory[address*WRITE_WIDTH_RATIO_B] = current_contents; + end else begin + for (i = 0; i < WRITE_WIDTH_RATIO_B; i = i + 1) begin + memory[address*WRITE_WIDTH_RATIO_B + i] + = current_contents[MIN_WIDTH*i+:MIN_WIDTH]; + end + end + end + end + endtask + + //************** + // read_a + //************** + task read_a + (input reg [C_ADDRA_WIDTH-1:0] addr, + input reg reset); + reg [C_ADDRA_WIDTH-1:0] address; + integer i; + begin + + if (reset) begin + memory_out_a <= #FLOP_DELAY inita_val; + end else begin + // Shift the address by the ratio + address = (addr/READ_ADDR_A_DIV); + if (address >= C_READ_DEPTH_A) begin + if (!C_DISABLE_WARN_BHV_RANGE) begin + $fdisplay(ADDRFILE, + "%0s WARNING: Address %0h is outside range for A Read", + C_CORENAME, addr); + end + memory_out_a <= #FLOP_DELAY 'bX; + // valid address + end else begin + if (READ_WIDTH_RATIO_A==1) begin + memory_out_a <= #FLOP_DELAY memory[address*READ_WIDTH_RATIO_A]; + end else begin + // Increment through the 'partial' words in the memory + for (i = 0; i < READ_WIDTH_RATIO_A; i = i + 1) begin + memory_out_a[MIN_WIDTH*i+:MIN_WIDTH] + <= #FLOP_DELAY memory[address*READ_WIDTH_RATIO_A + i]; + end + end //end READ_WIDTH_RATIO_A==1 loop + + end //end valid address loop + end //end reset-data assignment loops + end + endtask + + //************** + // read_b + //************** + task read_b + (input reg [C_ADDRB_WIDTH-1:0] addr, + input reg reset); + reg [C_ADDRB_WIDTH-1:0] address; + integer i; + begin + + if (reset) begin + memory_out_b <= #FLOP_DELAY initb_val; + sbiterr_in <= #FLOP_DELAY 1'b0; + dbiterr_in <= #FLOP_DELAY 1'b0; + rdaddrecc_in <= #FLOP_DELAY 0; + end else begin + // Shift the address + address = (addr/READ_ADDR_B_DIV); + if (address >= C_READ_DEPTH_B) begin + if (!C_DISABLE_WARN_BHV_RANGE) begin + $fdisplay(ADDRFILE, + "%0s WARNING: Address %0h is outside range for B Read", + C_CORENAME, addr); + end + memory_out_b <= #FLOP_DELAY 'bX; + sbiterr_in <= #FLOP_DELAY 1'bX; + dbiterr_in <= #FLOP_DELAY 1'bX; + rdaddrecc_in <= #FLOP_DELAY 'bX; + // valid address + end else begin + if (READ_WIDTH_RATIO_B==1) begin + memory_out_b <= #FLOP_DELAY memory[address*READ_WIDTH_RATIO_B]; + end else begin + // Increment through the 'partial' words in the memory + for (i = 0; i < READ_WIDTH_RATIO_B; i = i + 1) begin + memory_out_b[MIN_WIDTH*i+:MIN_WIDTH] + <= #FLOP_DELAY memory[address*READ_WIDTH_RATIO_B + i]; + end + end + + if ((C_FAMILY == "virtex6") && C_USE_ECC == 1) begin + rdaddrecc_in <= #FLOP_DELAY addr; + if (sbiterr_arr[addr] == 1) begin + sbiterr_in <= #FLOP_DELAY 1'b1; + end else begin + sbiterr_in <= #FLOP_DELAY 1'b0; + end + + if (dbiterr_arr[addr] == 1) begin + dbiterr_in <= #FLOP_DELAY 1'b1; + end else begin + dbiterr_in <= #FLOP_DELAY 1'b0; + end +///// end else begin +///// rdaddrecc_in <= #FLOP_DELAY 0; +///// dbiterr_in <= #FLOP_DELAY 1'b0; +///// sbiterr_in <= #FLOP_DELAY 1'b0; +///// end //end ECC Loop + + end else if (C_USE_SOFTECC == 1) begin + rdaddrecc_in <= #FLOP_DELAY addr; + if (softecc_sbiterr_arr[addr] == 1) begin + sbiterr_in <= #FLOP_DELAY 1'b1; + end else begin + sbiterr_in <= #FLOP_DELAY 1'b0; + end + + if (softecc_dbiterr_arr[addr] == 1) begin + dbiterr_in <= #FLOP_DELAY 1'b1; + end else begin + dbiterr_in <= #FLOP_DELAY 1'b0; + end + end else begin + rdaddrecc_in <= #FLOP_DELAY 0; + dbiterr_in <= #FLOP_DELAY 1'b0; + sbiterr_in <= #FLOP_DELAY 1'b0; + end //end SOFTECC Loop + + end //end Valid address loop + end //end reset-data assignment loops + end + endtask + + //************** + // reset_a + //************** + task reset_a (input reg reset); + begin + if (reset) memory_out_a <= #FLOP_DELAY inita_val; + end + endtask + + //************** + // reset_b + //************** + task reset_b (input reg reset); + begin + if (reset) memory_out_b <= #FLOP_DELAY initb_val; + end + endtask + + //************** + // init_memory + //************** + task init_memory; + integer i, addr_step; + integer status; + reg [C_WRITE_WIDTH_A-1:0] default_data; + begin + default_data = 0; + + //Display output message indicating that the behavioral model is being + //initialized + if (C_USE_DEFAULT_DATA || C_LOAD_INIT_FILE) $display(" Block Memory Generator CORE Generator module loading initial data..."); + + // Convert the default to hex + if (C_USE_DEFAULT_DATA) begin + if (default_data_str == "") begin + $fdisplay(ERRFILE, "%0s ERROR: C_DEFAULT_DATA is empty!", C_CORENAME); + $finish; + end else begin + status = $sscanf(default_data_str, "%h", default_data); + if (status == 0) begin + $fdisplay(ERRFILE, {"%0s ERROR: Unsuccessful hexadecimal read", + "from C_DEFAULT_DATA: %0s"}, + C_CORENAME, C_DEFAULT_DATA); + $finish; + end + end + end + + // Step by WRITE_ADDR_A_DIV through the memory via the + // Port A write interface to hit every location once + addr_step = WRITE_ADDR_A_DIV; + + // 'write' to every location with default (or 0) + for (i = 0; i < C_WRITE_DEPTH_A*addr_step; i = i + addr_step) begin + write_a(i, {C_WEA_WIDTH{1'b1}}, default_data, 1'b0, 1'b0); + end + + // Get specialized data from the MIF file + if (C_LOAD_INIT_FILE) begin + if (init_file_str == "") begin + $fdisplay(ERRFILE, "%0s ERROR: C_INIT_FILE_NAME is empty!", + C_CORENAME); + $finish; + end else begin + initfile = $fopen(init_file_str, "r"); + if (initfile == 0) begin + $fdisplay(ERRFILE, {"%0s, ERROR: Problem opening", + "C_INIT_FILE_NAME: %0s!"}, + C_CORENAME, init_file_str); + $finish; + end else begin + // loop through the mif file, loading in the data + for (i = 0; i < C_WRITE_DEPTH_A*addr_step; i = i + addr_step) begin + status = $fscanf(initfile, "%b", mif_data); + if (status > 0) begin + write_a(i, {C_WEA_WIDTH{1'b1}}, mif_data, 1'b0, 1'b0); + end + end + $fclose(initfile); + end //initfile + end //init_file_str + end //C_LOAD_INIT_FILE + + //Display output message indicating that the behavioral model is done + //initializing + if (C_USE_DEFAULT_DATA || C_LOAD_INIT_FILE) + $display(" Block Memory Generator data initialization complete."); + end + endtask + + //************** + // log2roundup + //************** + function integer log2roundup (input integer data_value); + integer width; + integer cnt; + begin + width = 0; + + if (data_value > 1) begin + for(cnt=1 ; cnt < data_value ; cnt = cnt * 2) begin + width = width + 1; + end //loop + end //if + + log2roundup = width; + + end //log2roundup + endfunction + + + //******************* + // collision_check + //******************* + function integer collision_check (input reg [C_ADDRA_WIDTH-1:0] addr_a, + input integer iswrite_a, + input reg [C_ADDRB_WIDTH-1:0] addr_b, + input integer iswrite_b); + reg c_aw_bw, c_aw_br, c_ar_bw; + integer scaled_addra_to_waddrb_width; + integer scaled_addrb_to_waddrb_width; + integer scaled_addra_to_waddra_width; + integer scaled_addrb_to_waddra_width; + integer scaled_addra_to_raddrb_width; + integer scaled_addrb_to_raddrb_width; + integer scaled_addra_to_raddra_width; + integer scaled_addrb_to_raddra_width; + + + + begin + + c_aw_bw = 0; + c_aw_br = 0; + c_ar_bw = 0; + + //If write_addr_b_width is smaller, scale both addresses to that width for + //comparing write_addr_a and write_addr_b; addr_a starts as C_ADDRA_WIDTH, + //scale it down to write_addr_b_width. addr_b starts as C_ADDRB_WIDTH, + //scale it down to write_addr_b_width. Once both are scaled to + //write_addr_b_width, compare. + scaled_addra_to_waddrb_width = ((addr_a)/ + 2**(C_ADDRA_WIDTH-write_addr_b_width)); + scaled_addrb_to_waddrb_width = ((addr_b)/ + 2**(C_ADDRB_WIDTH-write_addr_b_width)); + + //If write_addr_a_width is smaller, scale both addresses to that width for + //comparing write_addr_a and write_addr_b; addr_a starts as C_ADDRA_WIDTH, + //scale it down to write_addr_a_width. addr_b starts as C_ADDRB_WIDTH, + //scale it down to write_addr_a_width. Once both are scaled to + //write_addr_a_width, compare. + scaled_addra_to_waddra_width = ((addr_a)/ + 2**(C_ADDRA_WIDTH-write_addr_a_width)); + scaled_addrb_to_waddra_width = ((addr_b)/ + 2**(C_ADDRB_WIDTH-write_addr_a_width)); + + //If read_addr_b_width is smaller, scale both addresses to that width for + //comparing write_addr_a and read_addr_b; addr_a starts as C_ADDRA_WIDTH, + //scale it down to read_addr_b_width. addr_b starts as C_ADDRB_WIDTH, + //scale it down to read_addr_b_width. Once both are scaled to + //read_addr_b_width, compare. + scaled_addra_to_raddrb_width = ((addr_a)/ + 2**(C_ADDRA_WIDTH-read_addr_b_width)); + scaled_addrb_to_raddrb_width = ((addr_b)/ + 2**(C_ADDRB_WIDTH-read_addr_b_width)); + + //If read_addr_a_width is smaller, scale both addresses to that width for + //comparing read_addr_a and write_addr_b; addr_a starts as C_ADDRA_WIDTH, + //scale it down to read_addr_a_width. addr_b starts as C_ADDRB_WIDTH, + //scale it down to read_addr_a_width. Once both are scaled to + //read_addr_a_width, compare. + scaled_addra_to_raddra_width = ((addr_a)/ + 2**(C_ADDRA_WIDTH-read_addr_a_width)); + scaled_addrb_to_raddra_width = ((addr_b)/ + 2**(C_ADDRB_WIDTH-read_addr_a_width)); + + //Look for a write-write collision. In order for a write-write + //collision to exist, both ports must have a write transaction. + if (iswrite_a && iswrite_b) begin + if (write_addr_a_width > write_addr_b_width) begin + if (scaled_addra_to_waddrb_width == scaled_addrb_to_waddrb_width) begin + c_aw_bw = 1; + end else begin + c_aw_bw = 0; + end + end else begin + if (scaled_addrb_to_waddra_width == scaled_addra_to_waddra_width) begin + c_aw_bw = 1; + end else begin + c_aw_bw = 0; + end + end //width + end //iswrite_a and iswrite_b + + //If the B port is reading (which means it is enabled - so could be + //a TX_WRITE or TX_READ), then check for a write-read collision). + //This could happen whether or not a write-write collision exists due + //to asymmetric write/read ports. + if (iswrite_a) begin + if (write_addr_a_width > read_addr_b_width) begin + if (scaled_addra_to_raddrb_width == scaled_addrb_to_raddrb_width) begin + c_aw_br = 1; + end else begin + c_aw_br = 0; + end + end else begin + if (scaled_addrb_to_waddra_width == scaled_addra_to_waddra_width) begin + c_aw_br = 1; + end else begin + c_aw_br = 0; + end + end //width + end //iswrite_a + + //If the A port is reading (which means it is enabled - so could be + // a TX_WRITE or TX_READ), then check for a write-read collision). + //This could happen whether or not a write-write collision exists due + // to asymmetric write/read ports. + if (iswrite_b) begin + if (read_addr_a_width > write_addr_b_width) begin + if (scaled_addra_to_waddrb_width == scaled_addrb_to_waddrb_width) begin + c_ar_bw = 1; + end else begin + c_ar_bw = 0; + end + end else begin + if (scaled_addrb_to_raddra_width == scaled_addra_to_raddra_width) begin + c_ar_bw = 1; + end else begin + c_ar_bw = 0; + end + end //width + end //iswrite_b + + + + collision_check = c_aw_bw | c_aw_br | c_ar_bw; + + end + endfunction + + //******************************* + // power on values + //******************************* + initial begin + // Load up the memory + init_memory; + // Load up the output registers and latches + if ($sscanf(inita_str, "%h", inita_val)) begin + memory_out_a = inita_val; + end else begin + memory_out_a = 0; + end + if ($sscanf(initb_str, "%h", initb_val)) begin + memory_out_b = initb_val; + end else begin + memory_out_b = 0; + end + + sbiterr_in = 1'b0; + dbiterr_in = 1'b0; + rdaddrecc_in = 0; + + // Determine the effective address widths for each of the 4 ports + write_addr_a_width = C_ADDRA_WIDTH - log2roundup(WRITE_ADDR_A_DIV); + read_addr_a_width = C_ADDRA_WIDTH - log2roundup(READ_ADDR_A_DIV); + write_addr_b_width = C_ADDRB_WIDTH - log2roundup(WRITE_ADDR_B_DIV); + read_addr_b_width = C_ADDRB_WIDTH - log2roundup(READ_ADDR_B_DIV); + + $display("Block Memory Generator CORE Generator module %m is using a behavioral model for simulation which will not precisely model memory collision behavior."); + + end + + //************************************************************************* + // Asynchronous reset of Port A and Port B are performed here + // Note that the asynchronous reset feature is only supported in Spartan6 + // devices + //************************************************************************* + generate if((C_FAMILY == "spartan6") && C_RST_TYPE=="ASYNC") begin : async_rst + if (C_RST_PRIORITY_A=="CE") begin + always @ (*) begin + if (rea_i) reset_a(reseta_i); + end + end + else begin + always @ (*) begin + reset_a(reseta_i); + end + end + + if (C_RST_PRIORITY_B=="CE") begin + always @ (*) begin + if (reb_i) reset_b(resetb_i); + end + end + else begin + always @ (*) begin + reset_b(resetb_i); + end + end + + end + endgenerate + + //*************************************************************************** + // These are the main blocks which schedule read and write operations + // Note that the reset priority feature at the latch stage is only supported + // for Spartan-6. For other families, the default priority at the latch stage + // is "CE" + //*************************************************************************** + // Synchronous clocks: schedule port operations with respect to + // both write operating modes + generate + if(C_COMMON_CLK && (C_WRITE_MODE_A == "WRITE_FIRST") && (C_WRITE_MODE_B == + "WRITE_FIRST")) begin : com_clk_sched_wf_wf + always @(posedge CLKA) begin + //Write A + if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR); + //Write B + if (web_i) write_b(ADDRB, web_i, DINB); + //Read A + if ((C_FAMILY == "spartan6") && C_RST_PRIORITY_A=="SR") begin + if (reseta_i) reset_a(reseta_i); + else if (rea_i) read_a(ADDRA, reseta_i); + end else begin + if (rea_i) read_a(ADDRA, reseta_i); + end + //Read B + if ((C_FAMILY == "spartan6") && C_RST_PRIORITY_B=="SR") begin + if (resetb_i) reset_b(resetb_i); + else if (reb_i) read_b(ADDRB, resetb_i); + end else begin + if (reb_i) read_b(ADDRB, resetb_i); + end + end + end + else + if(C_COMMON_CLK && (C_WRITE_MODE_A == "READ_FIRST") && (C_WRITE_MODE_B == + "WRITE_FIRST")) begin : com_clk_sched_rf_wf + always @(posedge CLKA) begin + //Write B + if (web_i) write_b(ADDRB, web_i, DINB); + //Read B + if ((C_FAMILY == "spartan6") && C_RST_PRIORITY_B=="SR") begin + if (resetb_i) reset_b(resetb_i); + else if (reb_i) read_b(ADDRB, resetb_i); + end else begin + if (reb_i) read_b(ADDRB, resetb_i); + end + //Read A + if ((C_FAMILY == "spartan6") && C_RST_PRIORITY_A=="SR") begin + if (reseta_i) reset_a(reseta_i); + else if (rea_i) read_a(ADDRA, reseta_i); + end else begin + if (rea_i) read_a(ADDRA, reseta_i); + end + //Write A + if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR); + end + end + else + if(C_COMMON_CLK && (C_WRITE_MODE_A == "WRITE_FIRST") && (C_WRITE_MODE_B == + "READ_FIRST")) begin : com_clk_sched_wf_rf + always @(posedge CLKA) begin + //Write A + if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR); + //Read A + if ((C_FAMILY == "spartan6") && C_RST_PRIORITY_A=="SR") begin + if (reseta_i) reset_a(reseta_i); + else if (rea_i) read_a(ADDRA, reseta_i); + end else begin + if (rea_i) read_a(ADDRA, reseta_i); + end + //Read B + if ((C_FAMILY == "spartan6") && C_RST_PRIORITY_B=="SR") begin + if (resetb_i) reset_b(resetb_i); + else if (reb_i) read_b(ADDRB, resetb_i); + end else begin + if (reb_i) read_b(ADDRB, resetb_i); + end + //Write B + if (web_i) write_b(ADDRB, web_i, DINB); + end + end + else + if(C_COMMON_CLK && (C_WRITE_MODE_A == "READ_FIRST") && (C_WRITE_MODE_B == + "READ_FIRST")) begin : com_clk_sched_rf_rf + always @(posedge CLKA) begin + //Read A + if ((C_FAMILY == "spartan6") && C_RST_PRIORITY_A=="SR") begin + if (reseta_i) reset_a(reseta_i); + else if (rea_i) read_a(ADDRA, reseta_i); + end else begin + if (rea_i) read_a(ADDRA, reseta_i); + end + //Read B + if ((C_FAMILY == "spartan6") && C_RST_PRIORITY_B=="SR") begin + if (resetb_i) reset_b(resetb_i); + else if (reb_i) read_b(ADDRB, resetb_i); + end else begin + if (reb_i) read_b(ADDRB, resetb_i); + end + //Write A + if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR); + //Write B + if (web_i) write_b(ADDRB, web_i, DINB); + end + end + else if(C_COMMON_CLK && (C_WRITE_MODE_A =="WRITE_FIRST") && (C_WRITE_MODE_B == + "NO_CHANGE")) begin : com_clk_sched_wf_nc + always @(posedge CLKA) begin + //Write A + if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR); + //Read A + if ((C_FAMILY == "spartan6") && C_RST_PRIORITY_A=="SR") begin + if (reseta_i) reset_a(reseta_i); + else if (rea_i) read_a(ADDRA, reseta_i); + end else begin + if (rea_i) read_a(ADDRA, reseta_i); + end + //Read B + if ((C_FAMILY == "spartan6") && C_RST_PRIORITY_B=="SR") begin + if (resetb_i) reset_b(resetb_i); + else if (reb_i && !web_i) read_b(ADDRB, resetb_i); + end else begin + if (reb_i && (!web_i || resetb_i)) read_b(ADDRB, resetb_i); + end + //Write B + if (web_i) write_b(ADDRB, web_i, DINB); + end + end + else if(C_COMMON_CLK && (C_WRITE_MODE_A =="READ_FIRST") && (C_WRITE_MODE_B == + "NO_CHANGE")) begin : com_clk_sched_rf_nc + always @(posedge CLKA) begin + //Read A + if ((C_FAMILY == "spartan6") && C_RST_PRIORITY_A=="SR") begin + if (reseta_i) reset_a(reseta_i); + else if (rea_i) read_a(ADDRA, reseta_i); + end else begin + if (rea_i) read_a(ADDRA, reseta_i); + end + //Read B + if ((C_FAMILY == "spartan6") && C_RST_PRIORITY_B=="SR") begin + if (resetb_i) reset_b(resetb_i); + else if (reb_i && !web_i) read_b(ADDRB, resetb_i); + end else begin + if (reb_i && (!web_i || resetb_i)) read_b(ADDRB, resetb_i); + end + //Write A + if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR); + //Write B + if (web_i) write_b(ADDRB, web_i, DINB); + end + end + else if(C_COMMON_CLK && (C_WRITE_MODE_A =="NO_CHANGE") && (C_WRITE_MODE_B == + "WRITE_FIRST")) begin : com_clk_sched_nc_wf + always @(posedge CLKA) begin + //Write A + if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR); + //Write B + if (web_i) write_b(ADDRB, web_i, DINB); + //Read A + if ((C_FAMILY == "spartan6") && C_RST_PRIORITY_A=="SR") begin + if (reseta_i) reset_a(reseta_i); + else if (rea_i && !wea_i) read_a(ADDRA, reseta_i); + end else begin + if (rea_i && (!wea_i || reseta_i)) read_a(ADDRA, reseta_i); + end + //Read B + if ((C_FAMILY == "spartan6") && C_RST_PRIORITY_B=="SR") begin + if (resetb_i) reset_b(resetb_i); + else if (reb_i) read_b(ADDRB, resetb_i); + end else begin + if (reb_i) read_b(ADDRB, resetb_i); + end + end + end + else if(C_COMMON_CLK && (C_WRITE_MODE_A =="NO_CHANGE") && (C_WRITE_MODE_B == + "READ_FIRST")) begin : com_clk_sched_nc_rf + always @(posedge CLKA) begin + //Read B + if ((C_FAMILY == "spartan6") && C_RST_PRIORITY_B=="SR") begin + if (resetb_i) reset_b(resetb_i); + else if (reb_i) read_b(ADDRB, resetb_i); + end else begin + if (reb_i) read_b(ADDRB, resetb_i); + end + //Read A + if ((C_FAMILY == "spartan6") && C_RST_PRIORITY_A=="SR") begin + if (reseta_i) reset_a(reseta_i); + else if (rea_i && !wea_i) read_a(ADDRA, reseta_i); + end else begin + if (rea_i && (!wea_i || reseta_i)) read_a(ADDRA, reseta_i); + end + //Write A + if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR); + //Write B + if (web_i) write_b(ADDRB, web_i, DINB); + end + end + else if(C_COMMON_CLK && (C_WRITE_MODE_A =="NO_CHANGE") && (C_WRITE_MODE_B == + "NO_CHANGE")) begin : com_clk_sched_nc_nc + always @(posedge CLKA) begin + //Write A + if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR); + //Write B + if (web_i) write_b(ADDRB, web_i, DINB); + //Read A + if ((C_FAMILY == "spartan6") && C_RST_PRIORITY_A=="SR") begin + if (reseta_i) reset_a(reseta_i); + else if (rea_i && !wea_i) read_a(ADDRA, reseta_i); + end else begin + if (rea_i && (!wea_i || reseta_i)) read_a(ADDRA, reseta_i); + end + //Read B + if ((C_FAMILY == "spartan6") && C_RST_PRIORITY_B=="SR") begin + if (resetb_i) reset_b(resetb_i); + else if (reb_i && !web_i) read_b(ADDRB, resetb_i); + end else begin + if (reb_i && (!web_i || resetb_i)) read_b(ADDRB, resetb_i); + end + end + end + else if(C_COMMON_CLK) begin: com_clk_sched_default + always @(posedge CLKA) begin + //Write A + if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR); + //Write B + if (web_i) write_b(ADDRB, web_i, DINB); + //Read A + if ((C_FAMILY == "spartan6") && C_RST_PRIORITY_A=="SR") begin + if (reseta_i) reset_a(reseta_i); + else if (rea_i) read_a(ADDRA, reseta_i); + end else begin + if (rea_i) read_a(ADDRA, reseta_i); + end + //Read B + if ((C_FAMILY == "spartan6") && C_RST_PRIORITY_B=="SR") begin + if (resetb_i) reset_b(resetb_i); + else if (reb_i) read_b(ADDRB, resetb_i); + end else begin + if (reb_i) read_b(ADDRB, resetb_i); + end + end + end + endgenerate + + // Asynchronous clocks: port operation is independent + + generate + if((!C_COMMON_CLK) && (C_WRITE_MODE_A == "WRITE_FIRST")) begin : async_clk_sched_clka_wf + always @(posedge CLKA) begin + //Write A + if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR); + //Read A + if ((C_FAMILY == "spartan6") && C_RST_PRIORITY_A=="SR") begin + if (reseta_i) reset_a(reseta_i); + else if (rea_i) read_a(ADDRA, reseta_i); + end else begin + if (rea_i) read_a(ADDRA, reseta_i); + end + end + end + else if((!C_COMMON_CLK) && (C_WRITE_MODE_A == "READ_FIRST")) begin : async_clk_sched_clka_rf + always @(posedge CLKA) begin + //Read A + if ((C_FAMILY == "spartan6") && C_RST_PRIORITY_A=="SR") begin + if (reseta_i) reset_a(reseta_i); + else if (rea_i) read_a(ADDRA, reseta_i); + end else begin + if (rea_i) read_a(ADDRA, reseta_i); + end + //Write A + if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR); + end + end + else if((!C_COMMON_CLK) && (C_WRITE_MODE_A == "NO_CHANGE")) begin : async_clk_sched_clka_nc + always @(posedge CLKA) begin + //Write A + if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR); + //Read A + if ((C_FAMILY == "spartan6") && C_RST_PRIORITY_A=="SR") begin + if (reseta_i) reset_a(reseta_i); + else if (rea_i && !wea_i) read_a(ADDRA, reseta_i); + end else begin + if (rea_i && (!wea_i || reseta_i)) read_a(ADDRA, reseta_i); + end + end + end + endgenerate + + generate + if ((!C_COMMON_CLK) && (C_WRITE_MODE_B == "WRITE_FIRST")) begin: async_clk_sched_clkb_wf + always @(posedge CLKB) begin + //Write B + if (web_i) write_b(ADDRB, web_i, DINB); + //Read B + if ((C_FAMILY == "spartan6") && C_RST_PRIORITY_B=="SR") begin + if (resetb_i) reset_b(resetb_i); + else if (reb_i) read_b(ADDRB, resetb_i); + end else begin + if (reb_i) read_b(ADDRB, resetb_i); + end + end + end + else if ((!C_COMMON_CLK) && (C_WRITE_MODE_B == "READ_FIRST")) begin: async_clk_sched_clkb_rf + always @(posedge CLKB) begin + //Read B + if ((C_FAMILY == "spartan6") && C_RST_PRIORITY_B=="SR") begin + if (resetb_i) reset_b(resetb_i); + else if (reb_i) read_b(ADDRB, resetb_i); + end else begin + if (reb_i) read_b(ADDRB, resetb_i); + end + //Write B + if (web_i) write_b(ADDRB, web_i, DINB); + end + end + else if ((!C_COMMON_CLK) && (C_WRITE_MODE_B == "NO_CHANGE")) begin: async_clk_sched_clkb_nc + always @(posedge CLKB) begin + //Write B + if (web_i) write_b(ADDRB, web_i, DINB); + //Read B + if ((C_FAMILY == "spartan6") && C_RST_PRIORITY_B=="SR") begin + if (resetb_i) reset_b(resetb_i); + else if (reb_i && !web_i) read_b(ADDRB, resetb_i); + end else begin + if (reb_i && (!web_i || resetb_i)) read_b(ADDRB, resetb_i); + end + end + end + endgenerate + + + //*************************************************************** + // Instantiate the variable depth output register stage module + //*************************************************************** + // Port A + BLK_MEM_GEN_V4_1_output_stage + #(.C_FAMILY (C_FAMILY), + .C_XDEVICEFAMILY (C_XDEVICEFAMILY), + .C_RST_TYPE (C_RST_TYPE), + .C_HAS_RST (C_HAS_RSTA), + .C_RSTRAM (C_RSTRAM_A), + .C_RST_PRIORITY (C_RST_PRIORITY_A), + .C_INIT_VAL (C_INITA_VAL), + .C_HAS_EN (C_HAS_ENA), + .C_HAS_REGCE (C_HAS_REGCEA), + .C_DATA_WIDTH (C_READ_WIDTH_A), + .C_ADDRB_WIDTH (C_ADDRB_WIDTH), + .C_HAS_MEM_OUTPUT_REGS (C_HAS_MEM_OUTPUT_REGS_A), + .C_USE_SOFTECC (C_USE_SOFTECC), + .C_USE_ECC (C_USE_ECC), + .NUM_STAGES (NUM_OUTPUT_STAGES_A), + .FLOP_DELAY (FLOP_DELAY)) + reg_a + (.CLK (CLKA), + .RST (RSTA), + .EN (ENA), + .REGCE (REGCEA), + .DIN (memory_out_a), + .DOUT (DOUTA), + .SBITERR_IN (1'b0), + .DBITERR_IN (1'b0), + .SBITERR (), + .DBITERR (), + .RDADDRECC_IN ({C_ADDRB_WIDTH{1'b0}}), + .RDADDRECC () + ); + + // Port B + BLK_MEM_GEN_V4_1_output_stage + #(.C_FAMILY (C_FAMILY), + .C_XDEVICEFAMILY (C_XDEVICEFAMILY), + .C_RST_TYPE (C_RST_TYPE), + .C_HAS_RST (C_HAS_RSTB), + .C_RSTRAM (C_RSTRAM_B), + .C_RST_PRIORITY (C_RST_PRIORITY_B), + .C_INIT_VAL (C_INITB_VAL), + .C_HAS_EN (C_HAS_ENB), + .C_HAS_REGCE (C_HAS_REGCEB), + .C_DATA_WIDTH (C_READ_WIDTH_B), + .C_ADDRB_WIDTH (C_ADDRB_WIDTH), + .C_HAS_MEM_OUTPUT_REGS (C_HAS_MEM_OUTPUT_REGS_B), + .C_USE_SOFTECC (C_USE_SOFTECC), + .C_USE_ECC (C_USE_ECC), + .NUM_STAGES (NUM_OUTPUT_STAGES_B), + .FLOP_DELAY (FLOP_DELAY)) + reg_b + (.CLK (CLKB), + .RST (RSTB), + .EN (ENB), + .REGCE (REGCEB), + .DIN (memory_out_b), + .DOUT (dout_i), + .SBITERR_IN (sbiterr_in), + .DBITERR_IN (dbiterr_in), + .SBITERR (sbiterr_i), + .DBITERR (dbiterr_i), + .RDADDRECC_IN (rdaddrecc_in), + .RDADDRECC (rdaddrecc_i) + ); + + //*************************************************************** + // Instantiate the Input and Output register stages + //*************************************************************** +BLK_MEM_GEN_V4_1_softecc_output_reg_stage + #(.C_DATA_WIDTH (C_READ_WIDTH_B), + .C_ADDRB_WIDTH (C_ADDRB_WIDTH), + .C_HAS_SOFTECC_OUTPUT_REGS_A (C_HAS_SOFTECC_OUTPUT_REGS_A), + .C_HAS_SOFTECC_OUTPUT_REGS_B (C_HAS_SOFTECC_OUTPUT_REGS_B), + .C_USE_SOFTECC (C_USE_SOFTECC), + .FLOP_DELAY (FLOP_DELAY)) + has_softecc_output_reg_stage + (.CLK (CLKB), + .DIN (dout_i), + .DOUT (DOUTB), + .SBITERR_IN (sbiterr_i), + .DBITERR_IN (dbiterr_i), + .SBITERR (sbiterr_sdp), + .DBITERR (dbiterr_sdp), + .RDADDRECC_IN (rdaddrecc_i), + .RDADDRECC (rdaddrecc_sdp) +); + + //**************************************************** + // Synchronous collision checks + //**************************************************** + generate if (!C_DISABLE_WARN_BHV_COLL && C_COMMON_CLK) begin : sync_coll + always @(posedge CLKA) begin + // Possible collision if both are enabled and the addresses match + if (ena_i && enb_i) begin + if (wea_i || web_i) begin + is_collision <= collision_check(ADDRA, wea_i, ADDRB, web_i); + end else begin + is_collision <= 0; + end + end else begin + is_collision <= 0; + end + + // If the write port is in READ_FIRST mode, there is no collision + if (C_WRITE_MODE_A=="READ_FIRST" && wea_i && !web_i) begin + is_collision <= 0; + end + if (C_WRITE_MODE_B=="READ_FIRST" && web_i && !wea_i) begin + is_collision <= 0; + end + + // Only flag if one of the accesses is a write + if (is_collision && (wea_i || web_i)) begin + $fwrite(COLLFILE, "%0s collision detected at time: %0d, ", + C_CORENAME, $time); + $fwrite(COLLFILE, "A %0s address: %0h, B %0s address: %0h\n", + wea_i ? "write" : "read", ADDRA, + web_i ? "write" : "read", ADDRB); + end + end + + //**************************************************** + // Asynchronous collision checks + //**************************************************** + end else if (!C_DISABLE_WARN_BHV_COLL && !C_COMMON_CLK) begin : async_coll + + // Delay A and B addresses in order to mimic setup/hold times + wire [C_ADDRA_WIDTH-1:0] #COLL_DELAY addra_delay = ADDRA; + wire [0:0] #COLL_DELAY wea_delay = wea_i; + wire #COLL_DELAY ena_delay = ena_i; + wire [C_ADDRB_WIDTH-1:0] #COLL_DELAY addrb_delay = ADDRB; + wire [0:0] #COLL_DELAY web_delay = web_i; + wire #COLL_DELAY enb_delay = enb_i; + + // Do the checks w/rt A + always @(posedge CLKA) begin + // Possible collision if both are enabled and the addresses match + if (ena_i && enb_i) begin + if (wea_i || web_i) begin + is_collision_a <= collision_check(ADDRA, wea_i, ADDRB, web_i); + end else begin + is_collision_a <= 0; + end + end else begin + is_collision_a <= 0; + end + + if (ena_i && enb_delay) begin + if(wea_i || web_delay) begin + is_collision_delay_a <= collision_check(ADDRA, wea_i, addrb_delay, + web_delay); + end else begin + is_collision_delay_a <= 0; + end + end else begin + is_collision_delay_a <= 0; + end + + + // Only flag if B access is a write + if (is_collision_a && web_i) begin + $fwrite(COLLFILE, "%0s collision detected at time: %0d, ", + C_CORENAME, $time); + $fwrite(COLLFILE, "A %0s address: %0h, B write address: %0h\n", + wea_i ? "write" : "read", ADDRA, ADDRB); + + end else if (is_collision_delay_a && web_delay) begin + $fwrite(COLLFILE, "%0s collision detected at time: %0d, ", + C_CORENAME, $time); + $fwrite(COLLFILE, "A %0s address: %0h, B write address: %0h\n", + wea_i ? "write" : "read", ADDRA, addrb_delay); + end + + end + + // Do the checks w/rt B + always @(posedge CLKB) begin + + // Possible collision if both are enabled and the addresses match + if (ena_i && enb_i) begin + if (wea_i || web_i) begin + is_collision_b <= collision_check(ADDRA, wea_i, ADDRB, web_i); + end else begin + is_collision_b <= 0; + end + end else begin + is_collision_b <= 0; + end + + if (ena_delay && enb_i) begin + if (wea_delay || web_i) begin + is_collision_delay_b <= collision_check(addra_delay, wea_delay, ADDRB, + web_i); + end else begin + is_collision_delay_b <= 0; + end + end else begin + is_collision_delay_b <= 0; + end + + + // Only flag if A access is a write + if (is_collision_b && wea_i) begin + $fwrite(COLLFILE, "%0s collision detected at time: %0d, ", + C_CORENAME, $time); + $fwrite(COLLFILE, "A write address: %0h, B %s address: %0h\n", + ADDRA, web_i ? "write" : "read", ADDRB); + + end else if (is_collision_delay_b && wea_delay) begin + $fwrite(COLLFILE, "%0s collision detected at time: %0d, ", + C_CORENAME, $time); + $fwrite(COLLFILE, "A write address: %0h, B %s address: %0h\n", + addra_delay, web_i ? "write" : "read", ADDRB); + end + + end + end + endgenerate + +endmodule +//***************************************************************************** +// Top module wraps Input register and Memory module +// +// This module is the top-level behavioral model and this implements the memory +// module and the input registers +//***************************************************************************** +module BLK_MEM_GEN_V4_1 + #(parameter C_CORENAME = "blk_mem_gen_v4_1", + parameter C_FAMILY = "virtex6", + parameter C_XDEVICEFAMILY = "virtex6", + parameter C_MEM_TYPE = 2, + parameter C_BYTE_SIZE = 9, + parameter C_ALGORITHM = 1, + parameter C_PRIM_TYPE = 3, + parameter C_LOAD_INIT_FILE = 0, + parameter C_INIT_FILE_NAME = "", + parameter C_USE_DEFAULT_DATA = 0, + parameter C_DEFAULT_DATA = "0", + parameter C_RST_TYPE = "SYNC", + parameter C_HAS_RSTA = 0, + parameter C_RST_PRIORITY_A = "CE", + parameter C_RSTRAM_A = 0, + parameter C_INITA_VAL = "0", + parameter C_HAS_ENA = 1, + parameter C_HAS_REGCEA = 0, + parameter C_USE_BYTE_WEA = 0, + parameter C_WEA_WIDTH = 1, + parameter C_WRITE_MODE_A = "WRITE_FIRST", + parameter C_WRITE_WIDTH_A = 32, + parameter C_READ_WIDTH_A = 32, + parameter C_WRITE_DEPTH_A = 64, + parameter C_READ_DEPTH_A = 64, + parameter C_ADDRA_WIDTH = 5, + parameter C_HAS_RSTB = 0, + parameter C_RST_PRIORITY_B = "CE", + parameter C_RSTRAM_B = 0, + parameter C_INITB_VAL = "0", + parameter C_HAS_ENB = 1, + parameter C_HAS_REGCEB = 0, + parameter C_USE_BYTE_WEB = 0, + parameter C_WEB_WIDTH = 1, + parameter C_WRITE_MODE_B = "WRITE_FIRST", + parameter C_WRITE_WIDTH_B = 32, + parameter C_READ_WIDTH_B = 32, + parameter C_WRITE_DEPTH_B = 64, + parameter C_READ_DEPTH_B = 64, + parameter C_ADDRB_WIDTH = 5, + parameter C_HAS_MEM_OUTPUT_REGS_A = 0, + parameter C_HAS_MEM_OUTPUT_REGS_B = 0, + parameter C_HAS_MUX_OUTPUT_REGS_A = 0, + parameter C_HAS_MUX_OUTPUT_REGS_B = 0, + parameter C_HAS_SOFTECC_INPUT_REGS_A = 0, + parameter C_HAS_SOFTECC_INPUT_REGS_B = 0, + parameter C_HAS_SOFTECC_OUTPUT_REGS_A= 0, + parameter C_HAS_SOFTECC_OUTPUT_REGS_B= 0, + parameter C_MUX_PIPELINE_STAGES = 0, + parameter C_USE_SOFTECC = 0, + parameter C_USE_ECC = 0, + parameter C_HAS_INJECTERR = 0, + parameter C_SIM_COLLISION_CHECK = "NONE", + parameter C_COMMON_CLK = 1, + parameter C_DISABLE_WARN_BHV_COLL = 0, + parameter C_DISABLE_WARN_BHV_RANGE = 0 + ) + (input CLKA, + input RSTA, + input ENA, + input REGCEA, + input [C_WEA_WIDTH-1:0] WEA, + input [C_ADDRA_WIDTH-1:0] ADDRA, + input [C_WRITE_WIDTH_A-1:0] DINA, + output [C_READ_WIDTH_A-1:0] DOUTA, + input CLKB, + input RSTB, + input ENB, + input REGCEB, + input [C_WEB_WIDTH-1:0] WEB, + input [C_ADDRB_WIDTH-1:0] ADDRB, + input [C_WRITE_WIDTH_B-1:0] DINB, + output [C_READ_WIDTH_B-1:0] DOUTB, + input INJECTSBITERR, + input INJECTDBITERR, + output SBITERR, + output DBITERR, + output [C_ADDRB_WIDTH-1:0] RDADDRECC + ); +//****************************** +// Port and Generic Definitions +//****************************** + //------------------------------------------------------------------------- + // Generic Definitions + //------------------------------------------------------------------------- + // C_CORENAME : Instance name of the Block Memory Generator core + // C_FAMILY,C_XDEVICEFAMILY: Designates architecture targeted. The following + // options are available - "spartan3", "spartan6", + // "virtex4", "virtex5", "virtex6" and "virtex6l". + // C_MEM_TYPE : Designates memory type. + // It can be + // 0 - Single Port Memory + // 1 - Simple Dual Port Memory + // 2 - True Dual Port Memory + // 3 - Single Port Read Only Memory + // 4 - Dual Port Read Only Memory + // C_BYTE_SIZE : Size of a byte (8 or 9 bits) + // C_ALGORITHM : Designates the algorithm method used + // for constructing the memory. + // It can be Fixed_Primitives, Minimum_Area or + // Low_Power + // C_PRIM_TYPE : Designates the user selected primitive used to + // construct the memory. + // + // C_LOAD_INIT_FILE : Designates the use of an initialization file to + // initialize memory contents. + // C_INIT_FILE_NAME : Memory initialization file name. + // C_USE_DEFAULT_DATA : Designates whether to fill remaining + // initialization space with default data + // C_DEFAULT_DATA : Default value of all memory locations + // not initialized by the memory + // initialization file. + // C_RST_TYPE : Type of reset - Synchronous or Asynchronous + // C_HAS_RSTA : Determines the presence of the RSTA port + // C_RST_PRIORITY_A : Determines the priority between CE and SR for + // Port A. + // C_RSTRAM_A : Determines if special reset behavior is used for + // Port A + // C_INITA_VAL : The initialization value for Port A + // C_HAS_ENA : Determines the presence of the ENA port + // C_HAS_REGCEA : Determines the presence of the REGCEA port + // C_USE_BYTE_WEA : Determines if the Byte Write is used or not. + // C_WEA_WIDTH : The width of the WEA port + // C_WRITE_MODE_A : Configurable write mode for Port A. It can be + // WRITE_FIRST, READ_FIRST or NO_CHANGE. + // C_WRITE_WIDTH_A : Memory write width for Port A. + // C_READ_WIDTH_A : Memory read width for Port A. + // C_WRITE_DEPTH_A : Memory write depth for Port A. + // C_READ_DEPTH_A : Memory read depth for Port A. + // C_ADDRA_WIDTH : Width of the ADDRA input port + // C_HAS_RSTB : Determines the presence of the RSTB port + // C_RST_PRIORITY_B : Determines the priority between CE and SR for + // Port B. + // C_RSTRAM_B : Determines if special reset behavior is used for + // Port B + // C_INITB_VAL : The initialization value for Port B + // C_HAS_ENB : Determines the presence of the ENB port + // C_HAS_REGCEB : Determines the presence of the REGCEB port + // C_USE_BYTE_WEB : Determines if the Byte Write is used or not. + // C_WEB_WIDTH : The width of the WEB port + // C_WRITE_MODE_B : Configurable write mode for Port B. It can be + // WRITE_FIRST, READ_FIRST or NO_CHANGE. + // C_WRITE_WIDTH_B : Memory write width for Port B. + // C_READ_WIDTH_B : Memory read width for Port B. + // C_WRITE_DEPTH_B : Memory write depth for Port B. + // C_READ_DEPTH_B : Memory read depth for Port B. + // C_ADDRB_WIDTH : Width of the ADDRB input port + // C_HAS_MEM_OUTPUT_REGS_A : Designates the use of a register at the output + // of the RAM primitive for Port A. + // C_HAS_MEM_OUTPUT_REGS_B : Designates the use of a register at the output + // of the RAM primitive for Port B. + // C_HAS_MUX_OUTPUT_REGS_A : Designates the use of a register at the output + // of the MUX for Port A. + // C_HAS_MUX_OUTPUT_REGS_B : Designates the use of a register at the output + // of the MUX for Port B. + // C_HAS_SOFTECC_INPUT_REGS_A : + // C_HAS_SOFTECC_INPUT_REGS_B : + // C_HAS_SOFTECC_OUTPUT_REGS_A : + // C_HAS_SOFTECC_OUTPUT_REGS_B : + // C_MUX_PIPELINE_STAGES : Designates the number of pipeline stages in + // between the muxes. + // C_USE_SOFTECC : Determines if the Soft ECC feature is used or + // not. Only applicable Spartan-6 + // C_USE_ECC : Determines if the ECC feature is used or + // not. Only applicable for V5 and V6 + // C_HAS_INJECTERR : Determines if the error injection pins + // are present or not. If the ECC feature + // is not used, this value is defaulted to + // 0, else the following are the allowed + // values: + // 0 : No INJECTSBITERR or INJECTDBITERR pins + // 1 : Only INJECTSBITERR pin exists + // 2 : Only INJECTDBITERR pin exists + // 3 : Both INJECTSBITERR and INJECTDBITERR pins exist + // C_SIM_COLLISION_CHECK : Controls the disabling of Unisim model collision + // warnings. It can be "ALL", "NONE", + // "Warnings_Only" or "Generate_X_Only". + // C_COMMON_CLK : Determins if the core has a single CLK input. + // C_DISABLE_WARN_BHV_COLL : Controls the Behavioral Model Collision warnings + // C_DISABLE_WARN_BHV_RANGE: Controls the Behavioral Model Out of Range + // warnings + //------------------------------------------------------------------------- + // Port Definitions + //------------------------------------------------------------------------- + // CLKA : Clock to synchronize all read and write operations of Port A. + // RSTA : Reset input to reset memory outputs to a user-defined + // reset state for Port A. + // ENA : Enable all read and write operations of Port A. + // REGCEA : Register Clock Enable to control each pipeline output + // register stages for Port A. + // WEA : Write Enable to enable all write operations of Port A. + // ADDRA : Address of Port A. + // DINA : Data input of Port A. + // DOUTA : Data output of Port A. + // CLKB : Clock to synchronize all read and write operations of Port B. + // RSTB : Reset input to reset memory outputs to a user-defined + // reset state for Port B. + // ENB : Enable all read and write operations of Port B. + // REGCEB : Register Clock Enable to control each pipeline output + // register stages for Port B. + // WEB : Write Enable to enable all write operations of Port B. + // ADDRB : Address of Port B. + // DINB : Data input of Port B. + // DOUTB : Data output of Port B. + // INJECTSBITERR : Single Bit ECC Error Injection Pin. + // INJECTDBITERR : Double Bit ECC Error Injection Pin. + // SBITERR : Output signal indicating that a Single Bit ECC Error has been + // detected and corrected. + // DBITERR : Output signal indicating that a Double Bit ECC Error has been + // detected. + // RDADDRECC : Read Address Output signal indicating address at which an + // ECC error has occurred. + //------------------------------------------------------------------------- + + localparam FLOP_DELAY = 100; // 100 ps + + reg injectsbiterr_in; + reg injectdbiterr_in; + reg rsta_in; + reg ena_in; + reg regcea_in; + reg [C_WEA_WIDTH-1:0] wea_in; + reg [C_ADDRA_WIDTH-1:0] addra_in; + reg [C_WRITE_WIDTH_A-1:0] dina_in; + //*********************************************** + // INPUT REGISTERS. + //*********************************************** + generate if (C_HAS_SOFTECC_INPUT_REGS_A==0) begin : no_softecc_input_reg_stage + always @* begin + injectsbiterr_in = INJECTSBITERR; + injectdbiterr_in = INJECTDBITERR; + rsta_in = RSTA; + ena_in = ENA; + regcea_in = REGCEA; + wea_in = WEA; + addra_in = ADDRA; + dina_in = DINA; + end //end always + end //end no_softecc_input_reg_stage + endgenerate + + generate if (C_HAS_SOFTECC_INPUT_REGS_A==1) begin : has_softecc_input_reg_stage + always @(posedge CLKA) begin + injectsbiterr_in <= #FLOP_DELAY INJECTSBITERR; + injectdbiterr_in <= #FLOP_DELAY INJECTDBITERR; + rsta_in <= #FLOP_DELAY RSTA; + ena_in <= #FLOP_DELAY ENA; + regcea_in <= #FLOP_DELAY REGCEA; + wea_in <= #FLOP_DELAY WEA; + addra_in <= #FLOP_DELAY ADDRA; + dina_in <= #FLOP_DELAY DINA; + end //end always + end //end input_reg_stages generate statement + endgenerate + +BLK_MEM_GEN_V4_1_mem_module + #(.C_CORENAME (C_CORENAME), + .C_FAMILY (C_FAMILY), + .C_XDEVICEFAMILY (C_XDEVICEFAMILY), + .C_MEM_TYPE (C_MEM_TYPE), + .C_BYTE_SIZE (C_BYTE_SIZE), + .C_ALGORITHM (C_ALGORITHM), + .C_PRIM_TYPE (C_PRIM_TYPE), + .C_LOAD_INIT_FILE (C_LOAD_INIT_FILE), + .C_INIT_FILE_NAME (C_INIT_FILE_NAME), + .C_USE_DEFAULT_DATA (C_USE_DEFAULT_DATA), + .C_DEFAULT_DATA (C_DEFAULT_DATA), + .C_RST_TYPE (C_RST_TYPE), + .C_HAS_RSTA (C_HAS_RSTA), + .C_RST_PRIORITY_A (C_RST_PRIORITY_A), + .C_RSTRAM_A (C_RSTRAM_A), + .C_INITA_VAL (C_INITA_VAL), + .C_HAS_ENA (C_HAS_ENA), + .C_HAS_REGCEA (C_HAS_REGCEA), + .C_USE_BYTE_WEA (C_USE_BYTE_WEA), + .C_WEA_WIDTH (C_WEA_WIDTH), + .C_WRITE_MODE_A (C_WRITE_MODE_A), + .C_WRITE_WIDTH_A (C_WRITE_WIDTH_A), + .C_READ_WIDTH_A (C_READ_WIDTH_A), + .C_WRITE_DEPTH_A (C_WRITE_DEPTH_A), + .C_READ_DEPTH_A (C_READ_DEPTH_A), + .C_ADDRA_WIDTH (C_ADDRA_WIDTH), + .C_HAS_RSTB (C_HAS_RSTB), + .C_RST_PRIORITY_B (C_RST_PRIORITY_B), + .C_RSTRAM_B (C_RSTRAM_B), + .C_INITB_VAL (C_INITB_VAL), + .C_HAS_ENB (C_HAS_ENB), + .C_HAS_REGCEB (C_HAS_REGCEB), + .C_USE_BYTE_WEB (C_USE_BYTE_WEB), + .C_WEB_WIDTH (C_WEB_WIDTH), + .C_WRITE_MODE_B (C_WRITE_MODE_B), + .C_WRITE_WIDTH_B (C_WRITE_WIDTH_B), + .C_READ_WIDTH_B (C_READ_WIDTH_B), + .C_WRITE_DEPTH_B (C_WRITE_DEPTH_B), + .C_READ_DEPTH_B (C_READ_DEPTH_B), + .C_ADDRB_WIDTH (C_ADDRB_WIDTH), + .C_HAS_MEM_OUTPUT_REGS_A (C_HAS_MEM_OUTPUT_REGS_A), + .C_HAS_MEM_OUTPUT_REGS_B (C_HAS_MEM_OUTPUT_REGS_B), + .C_HAS_MUX_OUTPUT_REGS_A (C_HAS_MUX_OUTPUT_REGS_A), + .C_HAS_MUX_OUTPUT_REGS_B (C_HAS_MUX_OUTPUT_REGS_B), + .C_HAS_SOFTECC_INPUT_REGS_A (C_HAS_SOFTECC_INPUT_REGS_A), + .C_HAS_SOFTECC_INPUT_REGS_B (C_HAS_SOFTECC_INPUT_REGS_B), + .C_HAS_SOFTECC_OUTPUT_REGS_A (C_HAS_SOFTECC_OUTPUT_REGS_A), + .C_HAS_SOFTECC_OUTPUT_REGS_B (C_HAS_SOFTECC_OUTPUT_REGS_B), + .C_MUX_PIPELINE_STAGES (C_MUX_PIPELINE_STAGES), + .C_USE_SOFTECC (C_USE_SOFTECC), + .C_USE_ECC (C_USE_ECC), + .C_HAS_INJECTERR (C_HAS_INJECTERR), + .C_SIM_COLLISION_CHECK (C_SIM_COLLISION_CHECK), + .C_COMMON_CLK (C_COMMON_CLK), + .FLOP_DELAY (FLOP_DELAY), + .C_DISABLE_WARN_BHV_COLL (C_DISABLE_WARN_BHV_COLL), + .C_DISABLE_WARN_BHV_RANGE (C_DISABLE_WARN_BHV_RANGE)) + blk_mem_gen_v4_1_inst + (.CLKA (CLKA), + .RSTA (rsta_in), + .ENA (ena_in), + .REGCEA (regcea_in), + .WEA (wea_in), + .ADDRA (addra_in), + .DINA (dina_in), + .DOUTA (DOUTA), + .CLKB (CLKB), + .RSTB (RSTB), + .ENB (ENB), + .REGCEB (REGCEB), + .WEB (WEB), + .ADDRB (ADDRB), + .DINB (DINB), + .DOUTB (DOUTB), + .INJECTSBITERR (injectsbiterr_in), + .INJECTDBITERR (injectdbiterr_in), + .SBITERR (SBITERR), + .DBITERR (DBITERR), + .RDADDRECC (RDADDRECC) + ); +endmodule diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/BLK_MEM_GEN_V4_1_xst.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/BLK_MEM_GEN_V4_1_xst.v new file mode 100644 index 0000000..5236677 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/BLK_MEM_GEN_V4_1_xst.v @@ -0,0 +1,238 @@ +/****************************************************************************** +-- (c) Copyright 2006 - 2009 Xilinx, Inc. All rights reserved. +-- +-- This file contains confidential and proprietary information +-- of Xilinx, Inc. and is protected under U.S. and +-- international copyright and other intellectual property +-- laws. +-- +-- DISCLAIMER +-- This disclaimer is not a license and does not grant any +-- rights to the materials distributed herewith. Except as +-- otherwise provided in a valid license issued to you by +-- Xilinx, and to the maximum extent permitted by applicable +-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +-- (2) Xilinx shall not be liable (whether in contract or tort, +-- including negligence, or under any other theory of +-- liability) for any loss or damage of any kind or nature +-- related to, arising under or in connection with these +-- materials, including for any direct, or any indirect, +-- special, incidental, or consequential loss or damage +-- (including loss of data, profits, goodwill, or any type of +-- loss or damage suffered as a result of any action brought +-- by a third party) even if such damage or loss was +-- reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail- +-- safe, or for use in any application requiring fail-safe +-- performance, such as life-support or safety devices or +-- systems, Class III medical devices, nuclear facilities, +-- applications related to the deployment of airbags, or any +-- other applications that could lead to death, personal +-- injury, or severe property or environmental damage +-- (individually and collectively, "Critical +-- Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical +-- Applications, subject only to applicable laws and +-- regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +-- PART OF THIS FILE AT ALL TIMES. +-- + ***************************************************************************** + * + * Filename: BLK_MEM_GEN_V4_1.v + * + * Description: + * This file is the Verilog behvarial model for the + * Block Memory Generator Core. + * + ***************************************************************************** + * Author: Xilinx + * + * History: September 6, 2005 Initial revision + *****************************************************************************/ +`timescale 1ps/1ps + +module BLK_MEM_GEN_V4_1_xst + #(parameter C_FAMILY = "virtex5", + parameter C_XDEVICEFAMILY = "virtex5", + parameter C_ELABORATION_DIR = "", + parameter C_MEM_TYPE = 2, + parameter C_BYTE_SIZE = 9, + parameter C_ALGORITHM = 1, + parameter C_PRIM_TYPE = 3, + parameter C_LOAD_INIT_FILE = 0, + parameter C_INIT_FILE_NAME = "", + parameter C_USE_DEFAULT_DATA = 0, + parameter C_DEFAULT_DATA = "0", + parameter C_RST_TYPE = "SYNC", + parameter C_HAS_RSTA = 0, + parameter C_RST_PRIORITY_A = "CE", + parameter C_RSTRAM_A = 0, + parameter C_INITA_VAL = "0", + parameter C_HAS_ENA = 1, + parameter C_HAS_REGCEA = 0, + parameter C_USE_BYTE_WEA = 0, + parameter C_WEA_WIDTH = 1, + parameter C_WRITE_MODE_A = "WRITE_FIRST", + parameter C_WRITE_WIDTH_A = 32, + parameter C_READ_WIDTH_A = 32, + parameter C_WRITE_DEPTH_A = 64, + parameter C_READ_DEPTH_A = 64, + parameter C_ADDRA_WIDTH = 5, + parameter C_HAS_RSTB = 0, + parameter C_RST_PRIORITY_B = "CE", + parameter C_RSTRAM_B = 0, + parameter C_INITB_VAL = "0", + parameter C_HAS_ENB = 1, + parameter C_HAS_REGCEB = 0, + parameter C_USE_BYTE_WEB = 0, + parameter C_WEB_WIDTH = 1, + parameter C_WRITE_MODE_B = "WRITE_FIRST", + parameter C_WRITE_WIDTH_B = 32, + parameter C_READ_WIDTH_B = 32, + parameter C_WRITE_DEPTH_B = 64, + parameter C_READ_DEPTH_B = 64, + parameter C_ADDRB_WIDTH = 5, + parameter C_HAS_MEM_OUTPUT_REGS_A = 0, + parameter C_HAS_MEM_OUTPUT_REGS_B = 0, + parameter C_HAS_MUX_OUTPUT_REGS_A = 0, + parameter C_HAS_MUX_OUTPUT_REGS_B = 0, + parameter C_HAS_SOFTECC_INPUT_REGS_A = 0, + parameter C_HAS_SOFTECC_INPUT_REGS_B = 0, + parameter C_HAS_SOFTECC_OUTPUT_REGS_A= 0, + parameter C_HAS_SOFTECC_OUTPUT_REGS_B= 0, + parameter C_MUX_PIPELINE_STAGES = 0, + parameter C_USE_SOFTECC = 0, + parameter C_USE_ECC = 0, + parameter C_HAS_INJECTERR = 0, + parameter C_SIM_COLLISION_CHECK = "NONE", + parameter C_COMMON_CLK = 1, + parameter C_DISABLE_WARN_BHV_COLL = 0, + parameter C_DISABLE_WARN_BHV_RANGE = 0 +) + (input CLKA, + input RSTA, + input ENA, + input REGCEA, + input [C_WEA_WIDTH-1:0] WEA, + input [C_ADDRA_WIDTH-1:0] ADDRA, + input [C_WRITE_WIDTH_A-1:0] DINA, + output [C_READ_WIDTH_A-1:0] DOUTA, + input CLKB, + input RSTB, + input ENB, + input REGCEB, + input [C_WEB_WIDTH-1:0] WEB, + input [C_ADDRB_WIDTH-1:0] ADDRB, + input [C_WRITE_WIDTH_B-1:0] DINB, + output [C_READ_WIDTH_B-1:0] DOUTB, + input INJECTSBITERR, + input INJECTDBITERR, + output SBITERR, + output DBITERR, + output [C_ADDRB_WIDTH-1:0] RDADDRECC +); + + +// Note: C_ELABORATION_DIR parameter is only used in synthesis +// (and doesn't get mentioned in the instantiation template Coregen generates). +// This wrapper file has to work both in simulation and synthesis. So, this +// parameter exists. It is not used by the behavioral model +// (BLK_MEM_GEN_V4_1.vhd) + + localparam C_FAMILY_LOCALPARAM = (C_FAMILY=="virtex6l" ? "virtex6" : (C_FAMILY=="spartan6l" ? "spartan6" : (C_FAMILY=="aspartan6" ? "spartan6" : C_FAMILY))); + + BLK_MEM_GEN_V4_1 + #( + .C_CORENAME ("blk_mem_gen_v4_1"), +// .C_FAMILY (C_FAMILY), +// .C_FAMILY (C_FAMILY=="virtex6l" ? virtex6 : (C_FAMILY=="spartan6l" ? spartan6 : (C_FAMILY=="aspartan6" ? spartan6 : C_FAMILY))), + .C_FAMILY (C_FAMILY_LOCALPARAM), + .C_XDEVICEFAMILY (C_XDEVICEFAMILY), + .C_MEM_TYPE (C_MEM_TYPE), + .C_BYTE_SIZE (C_BYTE_SIZE), + .C_ALGORITHM (C_ALGORITHM), + .C_PRIM_TYPE (C_PRIM_TYPE), + .C_LOAD_INIT_FILE (C_LOAD_INIT_FILE), + .C_INIT_FILE_NAME (C_INIT_FILE_NAME), + .C_USE_DEFAULT_DATA (C_USE_DEFAULT_DATA), + .C_DEFAULT_DATA (C_DEFAULT_DATA), + .C_RST_TYPE (C_RST_TYPE), + .C_HAS_RSTA (C_HAS_RSTA), + .C_RST_PRIORITY_A (C_RST_PRIORITY_A), + .C_RSTRAM_A (C_RSTRAM_A), + .C_INITA_VAL (C_INITA_VAL), + .C_HAS_ENA (C_HAS_ENA), + .C_HAS_REGCEA (C_HAS_REGCEA), + .C_USE_BYTE_WEA (C_USE_BYTE_WEA), + .C_WEA_WIDTH (C_WEA_WIDTH), + .C_WRITE_MODE_A (C_WRITE_MODE_A), + .C_WRITE_WIDTH_A (C_WRITE_WIDTH_A), + .C_READ_WIDTH_A (C_READ_WIDTH_A), + .C_WRITE_DEPTH_A (C_WRITE_DEPTH_A), + .C_READ_DEPTH_A (C_READ_DEPTH_A), + .C_ADDRA_WIDTH (C_ADDRA_WIDTH), + .C_HAS_RSTB (C_HAS_RSTB), + .C_RST_PRIORITY_B (C_RST_PRIORITY_B), + .C_RSTRAM_B (C_RSTRAM_B), + .C_INITB_VAL (C_INITB_VAL), + .C_HAS_ENB (C_HAS_ENB), + .C_HAS_REGCEB (C_HAS_REGCEB), + .C_USE_BYTE_WEB (C_USE_BYTE_WEB), + .C_WEB_WIDTH (C_WEB_WIDTH), + .C_WRITE_MODE_B (C_WRITE_MODE_B), + .C_WRITE_WIDTH_B (C_WRITE_WIDTH_B), + .C_READ_WIDTH_B (C_READ_WIDTH_B), + .C_WRITE_DEPTH_B (C_WRITE_DEPTH_B), + .C_READ_DEPTH_B (C_READ_DEPTH_B), + .C_ADDRB_WIDTH (C_ADDRB_WIDTH), + .C_HAS_MEM_OUTPUT_REGS_A (C_HAS_MEM_OUTPUT_REGS_A), + .C_HAS_MEM_OUTPUT_REGS_B (C_HAS_MEM_OUTPUT_REGS_B), + .C_HAS_MUX_OUTPUT_REGS_A (C_HAS_MUX_OUTPUT_REGS_A), + .C_HAS_MUX_OUTPUT_REGS_B (C_HAS_MUX_OUTPUT_REGS_B), + .C_HAS_SOFTECC_INPUT_REGS_A (C_HAS_SOFTECC_INPUT_REGS_A), + .C_HAS_SOFTECC_INPUT_REGS_B (C_HAS_SOFTECC_INPUT_REGS_B), + .C_HAS_SOFTECC_OUTPUT_REGS_A (C_HAS_SOFTECC_OUTPUT_REGS_A), + .C_HAS_SOFTECC_OUTPUT_REGS_B (C_HAS_SOFTECC_OUTPUT_REGS_B), + .C_MUX_PIPELINE_STAGES (C_MUX_PIPELINE_STAGES), + .C_USE_SOFTECC (C_USE_SOFTECC), + .C_USE_ECC (C_USE_ECC), + .C_HAS_INJECTERR (C_HAS_INJECTERR), + .C_SIM_COLLISION_CHECK (C_SIM_COLLISION_CHECK), + .C_COMMON_CLK (C_COMMON_CLK), + .C_DISABLE_WARN_BHV_COLL (C_DISABLE_WARN_BHV_COLL), + .C_DISABLE_WARN_BHV_RANGE (C_DISABLE_WARN_BHV_RANGE) + ) blk_mem_gen_v4_1_dut ( + .CLKA (CLKA), + .RSTA (RSTA), + .ENA (ENA), + .REGCEA (REGCEA), + .WEA (WEA), + .ADDRA (ADDRA), + .DINA (DINA), + .DOUTA (DOUTA), + .CLKB (CLKB), + .RSTB (RSTB), + .ENB (ENB), + .REGCEB (REGCEB), + .WEB (WEB), + .ADDRB (ADDRB), + .DINB (DINB), + .DOUTB (DOUTB), + .INJECTSBITERR (INJECTSBITERR), + .INJECTDBITERR (INJECTDBITERR), + .SBITERR (SBITERR), + .DBITERR (DBITERR), + .RDADDRECC (RDADDRECC) +); + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/BLK_MEM_GEN_V4_2.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/BLK_MEM_GEN_V4_2.v new file mode 100644 index 0000000..d9db8f0 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/BLK_MEM_GEN_V4_2.v @@ -0,0 +1,2378 @@ +/****************************************************************************** +-- (c) Copyright 2006 - 2009 Xilinx, Inc. All rights reserved. +-- +-- This file contains confidential and proprietary information +-- of Xilinx, Inc. and is protected under U.S. and +-- international copyright and other intellectual property +-- laws. +-- +-- DISCLAIMER +-- This disclaimer is not a license and does not grant any +-- rights to the materials distributed herewith. Except as +-- otherwise provided in a valid license issued to you by +-- Xilinx, and to the maximum extent permitted by applicable +-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +-- (2) Xilinx shall not be liable (whether in contract or tort, +-- including negligence, or under any other theory of +-- liability) for any loss or damage of any kind or nature +-- related to, arising under or in connection with these +-- materials, including for any direct, or any indirect, +-- special, incidental, or consequential loss or damage +-- (including loss of data, profits, goodwill, or any type of +-- loss or damage suffered as a result of any action brought +-- by a third party) even if such damage or loss was +-- reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail- +-- safe, or for use in any application requiring fail-safe +-- performance, such as life-support or safety devices or +-- systems, Class III medical devices, nuclear facilities, +-- applications related to the deployment of airbags, or any +-- other applications that could lead to death, personal +-- injury, or severe property or environmental damage +-- (individually and collectively, "Critical +-- Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical +-- Applications, subject only to applicable laws and +-- regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +-- PART OF THIS FILE AT ALL TIMES. +-- + ***************************************************************************** + * + * Filename: BLK_MEM_GEN_V4_2.v + * + * Description: + * This file is the Verilog behvarial model for the + * Block Memory Generator Core. + * + ***************************************************************************** + * Author: Xilinx + * + * History: Jan 11, 2006 Initial revision + * Jun 11, 2007 Added independent register stages for + * Port A and Port B (IP1_Jm/v2.5) + * Aug 28, 2007 Added mux pipeline stages feature (IP2_Jm/v2.6) + * Mar 13, 2008 Behavioral model optimizations + * April 07, 2009 : Added support for Spartan-6 and Virtex-6 + * features, including the following: + * (i) error injection, detection and/or correction + * (ii) reset priority + * (iii) special reset behavior + * + *****************************************************************************/ +`timescale 1ps/1ps + +//***************************************************************************** +// Output Register Stage module +// +// This module builds the output register stages of the memory. This module is +// instantiated in the main memory module (BLK_MEM_GEN_V4_2) which is +// declared/implemented further down in this file. +//***************************************************************************** + +module BLK_MEM_GEN_V4_2_output_stage + #(parameter C_FAMILY = "virtex5", + parameter C_XDEVICEFAMILY = "virtex5", + parameter C_RST_TYPE = "SYNC", + parameter C_HAS_RST = 0, + parameter C_RSTRAM = 0, + parameter C_RST_PRIORITY = "CE", + parameter C_INIT_VAL = "0", + parameter C_HAS_EN = 0, + parameter C_HAS_REGCE = 0, + parameter C_DATA_WIDTH = 32, + parameter C_ADDRB_WIDTH = 10, + parameter C_HAS_MEM_OUTPUT_REGS = 0, + parameter C_USE_SOFTECC = 0, + parameter C_USE_ECC = 0, + parameter NUM_STAGES = 1, + parameter FLOP_DELAY = 100 + ) + ( + input CLK, + input RST, + input EN, + input REGCE, + input [C_DATA_WIDTH-1:0] DIN, + output reg [C_DATA_WIDTH-1:0] DOUT, + input SBITERR_IN, + input DBITERR_IN, + output reg SBITERR, + output reg DBITERR, + input [C_ADDRB_WIDTH-1:0] RDADDRECC_IN, + output reg [C_ADDRB_WIDTH-1:0] RDADDRECC +); + +//****************************** +// Port and Generic Definitions +//****************************** + //------------------------------------------------------------------------- + // Generic Definitions + //------------------------------------------------------------------------- + // C_FAMILY,C_XDEVICEFAMILY: Designates architecture targeted. The following + // options are available - "spartan3", "spartan6", + // "virtex4", "virtex5", "virtex6" and "virtex6l". + // C_RST_TYPE : Type of reset - Synchronous or Asynchronous + // C_HAS_RST : Determines the presence of the RST port + // C_RSTRAM : Determines if special reset behavior is used + // C_RST_PRIORITY : Determines the priority between CE and SR + // C_INIT_VAL : Initialization value + // C_HAS_EN : Determines the presence of the EN port + // C_HAS_REGCE : Determines the presence of the REGCE port + // C_DATA_WIDTH : Memory write/read width + // C_ADDRB_WIDTH : Width of the ADDRB input port + // C_HAS_MEM_OUTPUT_REGS : Designates the use of a register at the output + // of the RAM primitive + // C_USE_SOFTECC : Determines if the Soft ECC feature is used or + // not. Only applicable Spartan-6 + // C_USE_ECC : Determines if the ECC feature is used or + // not. Only applicable for V5 and V6 + // NUM_STAGES : Determines the number of output stages + // FLOP_DELAY : Constant delay for register assignments + //------------------------------------------------------------------------- + // Port Definitions + //------------------------------------------------------------------------- + // CLK : Clock to synchronize all read and write operations + // RST : Reset input to reset memory outputs to a user-defined + // reset state + // EN : Enable all read and write operations + // REGCE : Register Clock Enable to control each pipeline output + // register stages + // DIN : Data input to the Output stage. + // DOUT : Final Data output + // SBITERR_IN : SBITERR input signal to the Output stage. + // SBITERR : Final SBITERR Output signal. + // DBITERR_IN : DBITERR input signal to the Output stage. + // DBITERR : Final DBITERR Output signal. + // RDADDRECC_IN : RDADDRECC input signal to the Output stage. + // RDADDRECC : Final RDADDRECC Output signal. + //------------------------------------------------------------------------- + +// Fix for CR-509792 +// localparam REG_STAGES = (NUM_STAGES == 0) ? 0 : NUM_STAGES-1; + localparam REG_STAGES = (NUM_STAGES < 2) ? 1 : NUM_STAGES-1; + + // Declare the pipeline registers + // (includes mem output reg, mux pipeline stages, and mux output reg) + reg [C_DATA_WIDTH*REG_STAGES-1:0] out_regs; + reg [C_ADDRB_WIDTH*REG_STAGES-1:0] rdaddrecc_regs; + reg [REG_STAGES-1:0] sbiterr_regs; + reg [REG_STAGES-1:0] dbiterr_regs; + + reg [C_DATA_WIDTH*8-1:0] init_str = C_INIT_VAL; + reg [C_DATA_WIDTH-1:0] init_val; + + //********************************************* + // Wire off optional inputs based on parameters + //********************************************* + wire en_i; + wire regce_i; + wire rst_i; + + // Internal enable for output registers is tied to user EN or '1' depending + // on parameters + assign en_i = (C_HAS_EN==0 || EN); + + // Internal register enable for output registers is tied to user REGCE, EN or + // '1' depending on parameters + // For V4 ECC, REGCE is always 1 + // Virtex-4 ECC Not Yet Supported + assign regce_i = ((C_HAS_REGCE==1) && REGCE) || + ((C_HAS_REGCE==0) && (C_HAS_EN==0 || EN)); + + //Internal SRR is tied to user RST or '0' depending on parameters + assign rst_i = (C_HAS_RST==1) && RST; + + //**************************************************** + // Power on: load up the output registers and latches + //**************************************************** + initial begin + if (!($sscanf(init_str, "%h", init_val))) begin + init_val = 0; + end + DOUT = init_val; + RDADDRECC = 0; + SBITERR = 1'b0; + DBITERR = 1'b0; + // This will be one wider than need, but 0 is an error + out_regs = {(REG_STAGES+1){init_val}}; + rdaddrecc_regs = 0; + sbiterr_regs = {(REG_STAGES+1){1'b0}}; + dbiterr_regs = {(REG_STAGES+1){1'b0}}; + end + + //*********************************************** + // NUM_STAGES = 0 (No output registers. RAM only) + //*********************************************** + generate if (NUM_STAGES == 0) begin : zero_stages + always @* begin + DOUT = DIN; + RDADDRECC = RDADDRECC_IN; + SBITERR = SBITERR_IN; + DBITERR = DBITERR_IN; + end + end + endgenerate + + //*********************************************** + // NUM_STAGES = 1 + // (Mem Output Reg only or Mux Output Reg only) + //*********************************************** + + // Possible valid combinations: + // Note: C_HAS_MUX_OUTPUT_REGS_*=0 when (C_RSTRAM_*=1) + // +-----------------------------------------+ + // | C_RSTRAM_* | Reset Behavior | + // +----------------+------------------------+ + // | 0 | Normal Behavior | + // +----------------+------------------------+ + // | 1 | Special Behavior | + // +----------------+------------------------+ + // + // Normal = REGCE gates reset, as in the case of all families except S3ADSP. + // Special = EN gates reset, as in the case of S3ADSP. + + generate if (NUM_STAGES == 1 && + (C_RSTRAM == 0 || (C_RSTRAM == 1 && (C_XDEVICEFAMILY != "spartan3adsp" && C_XDEVICEFAMILY != "aspartan3adsp" )) || + C_HAS_MEM_OUTPUT_REGS == 0 || C_HAS_RST == 0)) + begin : one_stages_norm + //Asynchronous Reset + if ((C_FAMILY == "spartan6") && C_RST_TYPE == "ASYNC") begin + if(C_RST_PRIORITY == "CE") begin //REGCE has priority + always @ (*) begin + if (rst_i && regce_i) DOUT = init_val; + end + always @ (posedge CLK) begin + if (!rst_i && regce_i) DOUT <= #FLOP_DELAY DIN; + end //CLK + end else begin //RST has priority + always @ (*) begin + if (rst_i) DOUT = init_val; + end + always @ (posedge CLK) begin + if (!rst_i && regce_i) DOUT <= #FLOP_DELAY DIN; + end //CLK + end //end Priority conditions + //Synchronous Reset + end else begin + always @(posedge CLK) begin + if (C_RST_PRIORITY == "CE") begin //REGCE has priority + if (regce_i && rst_i) begin + DOUT <= #FLOP_DELAY init_val; + RDADDRECC <= #FLOP_DELAY 0; + SBITERR <= #FLOP_DELAY 1'b0; + DBITERR <= #FLOP_DELAY 1'b0; + end else if (regce_i) begin + DOUT <= #FLOP_DELAY DIN; + RDADDRECC <= #FLOP_DELAY RDADDRECC_IN; + SBITERR <= #FLOP_DELAY SBITERR_IN; + DBITERR <= #FLOP_DELAY DBITERR_IN; + end //Output signal assignments + end else begin //RST has priority + if (rst_i) begin + DOUT <= #FLOP_DELAY init_val; + RDADDRECC <= #FLOP_DELAY RDADDRECC_IN; + SBITERR <= #FLOP_DELAY 1'b0; + DBITERR <= #FLOP_DELAY 1'b0; + end else if (regce_i) begin + DOUT <= #FLOP_DELAY DIN; + RDADDRECC <= #FLOP_DELAY RDADDRECC_IN; + SBITERR <= #FLOP_DELAY SBITERR_IN; + DBITERR <= #FLOP_DELAY DBITERR_IN; + end //Output signal assignments + end //end Priority conditions + end //CLK + end //end RST Type conditions + end //end one_stages_norm generate statement + endgenerate + + // Special Reset Behavior for S3ADSP + generate if (NUM_STAGES == 1 && C_RSTRAM == 1 && (C_XDEVICEFAMILY =="spartan3adsp" || C_XDEVICEFAMILY =="aspartan3adsp")) + begin : one_stage_splbhv + always @(posedge CLK) begin + if (en_i && rst_i) begin + DOUT <= #FLOP_DELAY init_val; + end else if (regce_i && !rst_i) begin + DOUT <= #FLOP_DELAY DIN; + end //Output signal assignments + end //end CLK + end //end one_stage_splbhv generate statement + endgenerate + + //************************************************************ + // NUM_STAGES > 1 + // Mem Output Reg + Mux Output Reg + // or + // Mem Output Reg + Mux Pipeline Stages (>0) + Mux Output Reg + // or + // Mux Pipeline Stages (>0) + Mux Output Reg + //************************************************************* + generate if (NUM_STAGES > 1) begin : multi_stage + //Asynchronous Reset + if ((C_FAMILY == "spartan6") && C_RST_TYPE == "ASYNC") begin + if(C_RST_PRIORITY == "CE") begin //REGCE has priority + always @ (*) begin + if (rst_i && regce_i) DOUT = init_val; + end + always @ (posedge CLK) begin + if (!rst_i && regce_i) + DOUT <= #FLOP_DELAY out_regs[C_DATA_WIDTH*(NUM_STAGES-2)+:C_DATA_WIDTH]; + end //CLK + end else begin //RST has priority + always @ (*) begin + if (rst_i) DOUT = init_val; + end + always @ (posedge CLK) begin + if (!rst_i && regce_i) + DOUT <= #FLOP_DELAY out_regs[C_DATA_WIDTH*(NUM_STAGES-2)+:C_DATA_WIDTH]; + end //CLK + end //end Priority conditions + always @ (posedge CLK) begin + if (en_i) begin + out_regs <= (out_regs << C_DATA_WIDTH) | DIN; + end + end + //Synchronous Reset + end else begin + always @(posedge CLK) begin + if (C_RST_PRIORITY == "CE") begin //REGCE has priority + if (regce_i && rst_i) begin + DOUT <= #FLOP_DELAY init_val; + RDADDRECC <= #FLOP_DELAY 0; + SBITERR <= #FLOP_DELAY 1'b0; + DBITERR <= #FLOP_DELAY 1'b0; + end else if (regce_i) begin + DOUT <= #FLOP_DELAY + out_regs[C_DATA_WIDTH*(NUM_STAGES-2)+:C_DATA_WIDTH]; + RDADDRECC <= #FLOP_DELAY rdaddrecc_regs[C_ADDRB_WIDTH*(NUM_STAGES-2)+:C_ADDRB_WIDTH]; + SBITERR <= #FLOP_DELAY sbiterr_regs[NUM_STAGES-2]; + DBITERR <= #FLOP_DELAY dbiterr_regs[NUM_STAGES-2]; + end //Output signal assignments + end else begin //RST has priority + if (rst_i) begin + DOUT <= #FLOP_DELAY init_val; + RDADDRECC <= #FLOP_DELAY 0; + SBITERR <= #FLOP_DELAY 1'b0; + DBITERR <= #FLOP_DELAY 1'b0; + end else if (regce_i) begin + DOUT <= #FLOP_DELAY + out_regs[C_DATA_WIDTH*(NUM_STAGES-2)+:C_DATA_WIDTH]; + RDADDRECC <= #FLOP_DELAY rdaddrecc_regs[C_ADDRB_WIDTH*(NUM_STAGES-2)+:C_ADDRB_WIDTH]; + SBITERR <= #FLOP_DELAY sbiterr_regs[NUM_STAGES-2]; + DBITERR <= #FLOP_DELAY dbiterr_regs[NUM_STAGES-2]; + end //Output signal assignments + end //end Priority conditions + // Shift the data through the output stages + if (en_i) begin + out_regs <= #FLOP_DELAY (out_regs << C_DATA_WIDTH) | DIN; + rdaddrecc_regs <= #FLOP_DELAY (rdaddrecc_regs << C_ADDRB_WIDTH) | RDADDRECC_IN; + sbiterr_regs <= #FLOP_DELAY (sbiterr_regs << 1) | SBITERR_IN; + dbiterr_regs <= #FLOP_DELAY (dbiterr_regs << 1) | DBITERR_IN; + end + end //end CLK + end //end RST Type conditions + end //end multi_stage generate statement + endgenerate +endmodule + +module BLK_MEM_GEN_V4_2_softecc_output_reg_stage + #(parameter C_DATA_WIDTH = 32, + parameter C_ADDRB_WIDTH = 10, + parameter C_HAS_SOFTECC_OUTPUT_REGS_B= 0, + parameter C_USE_SOFTECC = 0, + parameter FLOP_DELAY = 100 + ) + ( + input CLK, + input [C_DATA_WIDTH-1:0] DIN, + output reg [C_DATA_WIDTH-1:0] DOUT, + input SBITERR_IN, + input DBITERR_IN, + output reg SBITERR, + output reg DBITERR, + input [C_ADDRB_WIDTH-1:0] RDADDRECC_IN, + output reg [C_ADDRB_WIDTH-1:0] RDADDRECC +); + +//****************************** +// Port and Generic Definitions +//****************************** + //------------------------------------------------------------------------- + // Generic Definitions + //------------------------------------------------------------------------- + // C_DATA_WIDTH : Memory write/read width + // C_ADDRB_WIDTH : Width of the ADDRB input port + // C_HAS_SOFTECC_OUTPUT_REGS_B : Designates the use of a register at the output + // of the RAM primitive + // C_USE_SOFTECC : Determines if the Soft ECC feature is used or + // not. Only applicable Spartan-6 + // FLOP_DELAY : Constant delay for register assignments + //------------------------------------------------------------------------- + // Port Definitions + //------------------------------------------------------------------------- + // CLK : Clock to synchronize all read and write operations + // DIN : Data input to the Output stage. + // DOUT : Final Data output + // SBITERR_IN : SBITERR input signal to the Output stage. + // SBITERR : Final SBITERR Output signal. + // DBITERR_IN : DBITERR input signal to the Output stage. + // DBITERR : Final DBITERR Output signal. + // RDADDRECC_IN : RDADDRECC input signal to the Output stage. + // RDADDRECC : Final RDADDRECC Output signal. + //------------------------------------------------------------------------- + + reg [C_DATA_WIDTH-1:0] dout_i = 0; + reg sbiterr_i = 0; + reg dbiterr_i = 0; + reg [C_ADDRB_WIDTH-1:0] rdaddrecc_i = 0; + + //*********************************************** + // NO OUTPUT REGISTERS. + //*********************************************** + generate if (C_HAS_SOFTECC_OUTPUT_REGS_B==0) begin : no_output_stage + always @* begin + DOUT = DIN; + RDADDRECC = RDADDRECC_IN; + SBITERR = SBITERR_IN; + DBITERR = DBITERR_IN; + end + end + endgenerate + + //*********************************************** + // WITH OUTPUT REGISTERS. + //*********************************************** + generate if (C_HAS_SOFTECC_OUTPUT_REGS_B==1) begin : has_output_stage + always @(posedge CLK) begin + dout_i <= #FLOP_DELAY DIN; + rdaddrecc_i <= #FLOP_DELAY RDADDRECC_IN; + sbiterr_i <= #FLOP_DELAY SBITERR_IN; + dbiterr_i <= #FLOP_DELAY DBITERR_IN; + end //end CLK + + always @* begin + DOUT = dout_i; + RDADDRECC = rdaddrecc_i; + SBITERR = sbiterr_i; + DBITERR = dbiterr_i; + end //end always + end //end in_or_out_stage generate statement + endgenerate + +endmodule + + +//***************************************************************************** +// Main Memory module +// +// This module is the top-level behavioral model and this implements the RAM +//***************************************************************************** +module BLK_MEM_GEN_V4_2_mem_module + #(parameter C_CORENAME = "blk_mem_gen_v4_2", + parameter C_FAMILY = "virtex6", + parameter C_XDEVICEFAMILY = "virtex6", + parameter C_MEM_TYPE = 2, + parameter C_BYTE_SIZE = 9, + parameter C_ALGORITHM = 1, + parameter C_PRIM_TYPE = 3, + parameter C_LOAD_INIT_FILE = 0, + parameter C_INIT_FILE_NAME = "", + parameter C_USE_DEFAULT_DATA = 0, + parameter C_DEFAULT_DATA = "0", + parameter C_RST_TYPE = "SYNC", + parameter C_HAS_RSTA = 0, + parameter C_RST_PRIORITY_A = "CE", + parameter C_RSTRAM_A = 0, + parameter C_INITA_VAL = "0", + parameter C_HAS_ENA = 1, + parameter C_HAS_REGCEA = 0, + parameter C_USE_BYTE_WEA = 0, + parameter C_WEA_WIDTH = 1, + parameter C_WRITE_MODE_A = "WRITE_FIRST", + parameter C_WRITE_WIDTH_A = 32, + parameter C_READ_WIDTH_A = 32, + parameter C_WRITE_DEPTH_A = 64, + parameter C_READ_DEPTH_A = 64, + parameter C_ADDRA_WIDTH = 5, + parameter C_HAS_RSTB = 0, + parameter C_RST_PRIORITY_B = "CE", + parameter C_RSTRAM_B = 0, + parameter C_INITB_VAL = "0", + parameter C_HAS_ENB = 1, + parameter C_HAS_REGCEB = 0, + parameter C_USE_BYTE_WEB = 0, + parameter C_WEB_WIDTH = 1, + parameter C_WRITE_MODE_B = "WRITE_FIRST", + parameter C_WRITE_WIDTH_B = 32, + parameter C_READ_WIDTH_B = 32, + parameter C_WRITE_DEPTH_B = 64, + parameter C_READ_DEPTH_B = 64, + parameter C_ADDRB_WIDTH = 5, + parameter C_HAS_MEM_OUTPUT_REGS_A = 0, + parameter C_HAS_MEM_OUTPUT_REGS_B = 0, + parameter C_HAS_MUX_OUTPUT_REGS_A = 0, + parameter C_HAS_MUX_OUTPUT_REGS_B = 0, + parameter C_HAS_SOFTECC_INPUT_REGS_A = 0, + parameter C_HAS_SOFTECC_OUTPUT_REGS_B= 0, + parameter C_MUX_PIPELINE_STAGES = 0, + parameter C_USE_SOFTECC = 0, + parameter C_USE_ECC = 0, + parameter C_HAS_INJECTERR = 0, + parameter C_SIM_COLLISION_CHECK = "NONE", + parameter C_COMMON_CLK = 1, + parameter FLOP_DELAY = 100, + parameter C_DISABLE_WARN_BHV_COLL = 0, + parameter C_DISABLE_WARN_BHV_RANGE = 0 + ) + (input CLKA, + input RSTA, + input ENA, + input REGCEA, + input [C_WEA_WIDTH-1:0] WEA, + input [C_ADDRA_WIDTH-1:0] ADDRA, + input [C_WRITE_WIDTH_A-1:0] DINA, + output [C_READ_WIDTH_A-1:0] DOUTA, + input CLKB, + input RSTB, + input ENB, + input REGCEB, + input [C_WEB_WIDTH-1:0] WEB, + input [C_ADDRB_WIDTH-1:0] ADDRB, + input [C_WRITE_WIDTH_B-1:0] DINB, + output [C_READ_WIDTH_B-1:0] DOUTB, + input INJECTSBITERR, + input INJECTDBITERR, + output SBITERR, + output DBITERR, + output [C_ADDRB_WIDTH-1:0] RDADDRECC + ); +//****************************** +// Port and Generic Definitions +//****************************** + //------------------------------------------------------------------------- + // Generic Definitions + //------------------------------------------------------------------------- + // C_CORENAME : Instance name of the Block Memory Generator core + // C_FAMILY,C_XDEVICEFAMILY: Designates architecture targeted. The following + // options are available - "spartan3", "spartan6", + // "virtex4", "virtex5", "virtex6" and "virtex6l". + // C_MEM_TYPE : Designates memory type. + // It can be + // 0 - Single Port Memory + // 1 - Simple Dual Port Memory + // 2 - True Dual Port Memory + // 3 - Single Port Read Only Memory + // 4 - Dual Port Read Only Memory + // C_BYTE_SIZE : Size of a byte (8 or 9 bits) + // C_ALGORITHM : Designates the algorithm method used + // for constructing the memory. + // It can be Fixed_Primitives, Minimum_Area or + // Low_Power + // C_PRIM_TYPE : Designates the user selected primitive used to + // construct the memory. + // + // C_LOAD_INIT_FILE : Designates the use of an initialization file to + // initialize memory contents. + // C_INIT_FILE_NAME : Memory initialization file name. + // C_USE_DEFAULT_DATA : Designates whether to fill remaining + // initialization space with default data + // C_DEFAULT_DATA : Default value of all memory locations + // not initialized by the memory + // initialization file. + // C_RST_TYPE : Type of reset - Synchronous or Asynchronous + // C_HAS_RSTA : Determines the presence of the RSTA port + // C_RST_PRIORITY_A : Determines the priority between CE and SR for + // Port A. + // C_RSTRAM_A : Determines if special reset behavior is used for + // Port A + // C_INITA_VAL : The initialization value for Port A + // C_HAS_ENA : Determines the presence of the ENA port + // C_HAS_REGCEA : Determines the presence of the REGCEA port + // C_USE_BYTE_WEA : Determines if the Byte Write is used or not. + // C_WEA_WIDTH : The width of the WEA port + // C_WRITE_MODE_A : Configurable write mode for Port A. It can be + // WRITE_FIRST, READ_FIRST or NO_CHANGE. + // C_WRITE_WIDTH_A : Memory write width for Port A. + // C_READ_WIDTH_A : Memory read width for Port A. + // C_WRITE_DEPTH_A : Memory write depth for Port A. + // C_READ_DEPTH_A : Memory read depth for Port A. + // C_ADDRA_WIDTH : Width of the ADDRA input port + // C_HAS_RSTB : Determines the presence of the RSTB port + // C_RST_PRIORITY_B : Determines the priority between CE and SR for + // Port B. + // C_RSTRAM_B : Determines if special reset behavior is used for + // Port B + // C_INITB_VAL : The initialization value for Port B + // C_HAS_ENB : Determines the presence of the ENB port + // C_HAS_REGCEB : Determines the presence of the REGCEB port + // C_USE_BYTE_WEB : Determines if the Byte Write is used or not. + // C_WEB_WIDTH : The width of the WEB port + // C_WRITE_MODE_B : Configurable write mode for Port B. It can be + // WRITE_FIRST, READ_FIRST or NO_CHANGE. + // C_WRITE_WIDTH_B : Memory write width for Port B. + // C_READ_WIDTH_B : Memory read width for Port B. + // C_WRITE_DEPTH_B : Memory write depth for Port B. + // C_READ_DEPTH_B : Memory read depth for Port B. + // C_ADDRB_WIDTH : Width of the ADDRB input port + // C_HAS_MEM_OUTPUT_REGS_A : Designates the use of a register at the output + // of the RAM primitive for Port A. + // C_HAS_MEM_OUTPUT_REGS_B : Designates the use of a register at the output + // of the RAM primitive for Port B. + // C_HAS_MUX_OUTPUT_REGS_A : Designates the use of a register at the output + // of the MUX for Port A. + // C_HAS_MUX_OUTPUT_REGS_B : Designates the use of a register at the output + // of the MUX for Port B. + // C_MUX_PIPELINE_STAGES : Designates the number of pipeline stages in + // between the muxes. + // C_USE_SOFTECC : Determines if the Soft ECC feature is used or + // not. Only applicable Spartan-6 + // C_USE_ECC : Determines if the ECC feature is used or + // not. Only applicable for V5 and V6 + // C_HAS_INJECTERR : Determines if the error injection pins + // are present or not. If the ECC feature + // is not used, this value is defaulted to + // 0, else the following are the allowed + // values: + // 0 : No INJECTSBITERR or INJECTDBITERR pins + // 1 : Only INJECTSBITERR pin exists + // 2 : Only INJECTDBITERR pin exists + // 3 : Both INJECTSBITERR and INJECTDBITERR pins exist + // C_SIM_COLLISION_CHECK : Controls the disabling of Unisim model collision + // warnings. It can be "ALL", "NONE", + // "Warnings_Only" or "Generate_X_Only". + // C_COMMON_CLK : Determins if the core has a single CLK input. + // C_DISABLE_WARN_BHV_COLL : Controls the Behavioral Model Collision warnings + // C_DISABLE_WARN_BHV_RANGE: Controls the Behavioral Model Out of Range + // warnings + //------------------------------------------------------------------------- + // Port Definitions + //------------------------------------------------------------------------- + // CLKA : Clock to synchronize all read and write operations of Port A. + // RSTA : Reset input to reset memory outputs to a user-defined + // reset state for Port A. + // ENA : Enable all read and write operations of Port A. + // REGCEA : Register Clock Enable to control each pipeline output + // register stages for Port A. + // WEA : Write Enable to enable all write operations of Port A. + // ADDRA : Address of Port A. + // DINA : Data input of Port A. + // DOUTA : Data output of Port A. + // CLKB : Clock to synchronize all read and write operations of Port B. + // RSTB : Reset input to reset memory outputs to a user-defined + // reset state for Port B. + // ENB : Enable all read and write operations of Port B. + // REGCEB : Register Clock Enable to control each pipeline output + // register stages for Port B. + // WEB : Write Enable to enable all write operations of Port B. + // ADDRB : Address of Port B. + // DINB : Data input of Port B. + // DOUTB : Data output of Port B. + // INJECTSBITERR : Single Bit ECC Error Injection Pin. + // INJECTDBITERR : Double Bit ECC Error Injection Pin. + // SBITERR : Output signal indicating that a Single Bit ECC Error has been + // detected and corrected. + // DBITERR : Output signal indicating that a Double Bit ECC Error has been + // detected. + // RDADDRECC : Read Address Output signal indicating address at which an + // ECC error has occurred. + //------------------------------------------------------------------------- + + +// Note: C_CORENAME parameter is hard-coded to "blk_mem_gen_v4_2" and it is +// only used by this module to print warning messages. It is neither passed +// down from blk_mem_gen_v4_2_xst.v nor present in the instantiation template +// coregen generates + + //*************************************************************************** + // constants for the core behavior + //*************************************************************************** + // file handles for logging + //-------------------------------------------------- + localparam ADDRFILE = 32'h8000_0001; //stdout for addr out of range + localparam COLLFILE = 32'h8000_0001; //stdout for coll detection + localparam ERRFILE = 32'h8000_0001; //stdout for file I/O errors + + // other constants + //-------------------------------------------------- + localparam COLL_DELAY = 2000; // 2 ns + + // locally derived parameters to determine memory shape + //----------------------------------------------------- + + localparam CHKBIT_WIDTH = (C_WRITE_WIDTH_A>57 ? 8 : (C_WRITE_WIDTH_A>26 ? 7 : (C_WRITE_WIDTH_A>11 ? 6 : (C_WRITE_WIDTH_A>4 ? 5 : (C_WRITE_WIDTH_A<5 ? 4 :0))))); + + localparam MIN_WIDTH_A = (C_WRITE_WIDTH_A < C_READ_WIDTH_A) ? + C_WRITE_WIDTH_A : C_READ_WIDTH_A; + localparam MIN_WIDTH_B = (C_WRITE_WIDTH_B < C_READ_WIDTH_B) ? + C_WRITE_WIDTH_B : C_READ_WIDTH_B; + localparam MIN_WIDTH = (MIN_WIDTH_A < MIN_WIDTH_B) ? + MIN_WIDTH_A : MIN_WIDTH_B; + + localparam MAX_DEPTH_A = (C_WRITE_DEPTH_A > C_READ_DEPTH_A) ? + C_WRITE_DEPTH_A : C_READ_DEPTH_A; + localparam MAX_DEPTH_B = (C_WRITE_DEPTH_B > C_READ_DEPTH_B) ? + C_WRITE_DEPTH_B : C_READ_DEPTH_B; + localparam MAX_DEPTH = (MAX_DEPTH_A > MAX_DEPTH_B) ? + MAX_DEPTH_A : MAX_DEPTH_B; + + + // locally derived parameters to assist memory access + //---------------------------------------------------- + // Calculate the width ratios of each port with respect to the narrowest + // port + localparam WRITE_WIDTH_RATIO_A = C_WRITE_WIDTH_A/MIN_WIDTH; + localparam READ_WIDTH_RATIO_A = C_READ_WIDTH_A/MIN_WIDTH; + localparam WRITE_WIDTH_RATIO_B = C_WRITE_WIDTH_B/MIN_WIDTH; + localparam READ_WIDTH_RATIO_B = C_READ_WIDTH_B/MIN_WIDTH; + + // To modify the LSBs of the 'wider' data to the actual + // address value + //---------------------------------------------------- + localparam WRITE_ADDR_A_DIV = C_WRITE_WIDTH_A/MIN_WIDTH_A; + localparam READ_ADDR_A_DIV = C_READ_WIDTH_A/MIN_WIDTH_A; + localparam WRITE_ADDR_B_DIV = C_WRITE_WIDTH_B/MIN_WIDTH_B; + localparam READ_ADDR_B_DIV = C_READ_WIDTH_B/MIN_WIDTH_B; + + // If byte writes aren't being used, make sure BYTE_SIZE is not + // wider than the memory elements to avoid compilation warnings + localparam BYTE_SIZE = (C_BYTE_SIZE < MIN_WIDTH) ? C_BYTE_SIZE : MIN_WIDTH; + + // The memory + reg [MIN_WIDTH-1:0] memory [0:MAX_DEPTH-1]; + reg [C_WRITE_WIDTH_A+CHKBIT_WIDTH-1:0] doublebit_error = 3; + // ECC error arrays + reg sbiterr_arr [0:MAX_DEPTH-1]; + reg dbiterr_arr [0:MAX_DEPTH-1]; + + reg softecc_sbiterr_arr [0:MAX_DEPTH-1]; + reg softecc_dbiterr_arr [0:MAX_DEPTH-1]; + // Memory output 'latches' + reg [C_READ_WIDTH_A-1:0] memory_out_a; + reg [C_READ_WIDTH_B-1:0] memory_out_b; + + // ECC error inputs and outputs from output_stage module: + reg sbiterr_in; + wire sbiterr_sdp; + reg dbiterr_in; + wire dbiterr_sdp; + + wire [C_READ_WIDTH_B-1:0] dout_i; + wire dbiterr_i; + wire sbiterr_i; + wire [C_ADDRB_WIDTH-1:0] rdaddrecc_i; + + reg [C_ADDRB_WIDTH-1:0] rdaddrecc_in; + wire [C_ADDRB_WIDTH-1:0] rdaddrecc_sdp; + + // Reset values + reg [C_READ_WIDTH_A-1:0] inita_val; + reg [C_READ_WIDTH_B-1:0] initb_val; + + // Collision detect + reg is_collision; + reg is_collision_a, is_collision_delay_a; + reg is_collision_b, is_collision_delay_b; + + // Temporary variables for initialization + //--------------------------------------- + integer status; + integer initfile; + // data input buffer + reg [C_WRITE_WIDTH_A-1:0] mif_data; + // string values in hex + reg [C_READ_WIDTH_A*8-1:0] inita_str = C_INITA_VAL; + reg [C_READ_WIDTH_B*8-1:0] initb_str = C_INITB_VAL; + reg [C_WRITE_WIDTH_A*8-1:0] default_data_str = C_DEFAULT_DATA; + // initialization filename + reg [1023*8-1:0] init_file_str = C_INIT_FILE_NAME; + + + //Constants used to calculate the effective address widths for each of the + //four ports. + integer cnt = 1; + integer write_addr_a_width, read_addr_a_width; + integer write_addr_b_width, read_addr_b_width; + + + // Internal configuration parameters + //--------------------------------------------- + localparam SINGLE_PORT = (C_MEM_TYPE==0 || C_MEM_TYPE==3); + localparam IS_ROM = (C_MEM_TYPE==3 || C_MEM_TYPE==4); + localparam HAS_A_WRITE = (!IS_ROM); + localparam HAS_B_WRITE = (C_MEM_TYPE==2); + localparam HAS_A_READ = (C_MEM_TYPE!=1); + localparam HAS_B_READ = (!SINGLE_PORT); + localparam HAS_B_PORT = (HAS_B_READ || HAS_B_WRITE); + + // Calculate the mux pipeline register stages for Port A and Port B + //------------------------------------------------------------------ + localparam MUX_PIPELINE_STAGES_A = (C_HAS_MUX_OUTPUT_REGS_A) ? + C_MUX_PIPELINE_STAGES : 0; + localparam MUX_PIPELINE_STAGES_B = (C_HAS_MUX_OUTPUT_REGS_B) ? + C_MUX_PIPELINE_STAGES : 0; + + // Calculate total number of register stages in the core + // ----------------------------------------------------- + localparam NUM_OUTPUT_STAGES_A = (C_HAS_MEM_OUTPUT_REGS_A+MUX_PIPELINE_STAGES_A+C_HAS_MUX_OUTPUT_REGS_A); + + localparam NUM_OUTPUT_STAGES_B = (C_HAS_MEM_OUTPUT_REGS_B+MUX_PIPELINE_STAGES_B+C_HAS_MUX_OUTPUT_REGS_B); + + wire ena_i; + wire enb_i; + wire reseta_i; + wire resetb_i; + wire [C_WEA_WIDTH-1:0] wea_i; + wire [C_WEB_WIDTH-1:0] web_i; + wire rea_i; + wire reb_i; + + // ECC SBITERR/DBITERR Outputs + // The ECC Behavior is modeled by the behavioral models only for Virtex-6. + // For Virtex-5, these outputs will be tied to 0. + assign SBITERR = ((C_MEM_TYPE == 1 && C_USE_ECC == 1) || C_USE_SOFTECC == 1)?sbiterr_sdp:0; + assign DBITERR = ((C_MEM_TYPE == 1 && C_USE_ECC == 1) || C_USE_SOFTECC == 1)?dbiterr_sdp:0; + assign RDADDRECC = (((C_FAMILY == "virtex6") && C_MEM_TYPE == 1 && C_USE_ECC == 1) || C_USE_SOFTECC == 1)?rdaddrecc_sdp:0; + + + // This effectively wires off optional inputs + assign ena_i = (C_HAS_ENA==0) || ENA; + assign enb_i = ((C_HAS_ENB==0) || ENB) && HAS_B_PORT; + assign wea_i = (HAS_A_WRITE && ena_i) ? WEA : 'b0; + assign web_i = (HAS_B_WRITE && enb_i) ? WEB : 'b0; + assign rea_i = (HAS_A_READ) ? ena_i : 'b0; + assign reb_i = (HAS_B_READ) ? enb_i : 'b0; + + // These signals reset the memory latches + + assign reseta_i = + ((C_HAS_RSTA==1 && RSTA && NUM_OUTPUT_STAGES_A==0) || + (C_HAS_RSTA==1 && RSTA && C_RSTRAM_A==1)); + + assign resetb_i = + ((C_HAS_RSTB==1 && RSTB && NUM_OUTPUT_STAGES_B==0) || + (C_HAS_RSTB==1 && RSTB && C_RSTRAM_B==1)); + + // Tasks to access the memory + //--------------------------- + //************** + // write_a + //************** + task write_a + (input reg [C_ADDRA_WIDTH-1:0] addr, + input reg [C_WEA_WIDTH-1:0] byte_en, + input reg [C_WRITE_WIDTH_A-1:0] data, + input inj_sbiterr, + input inj_dbiterr); + reg [C_WRITE_WIDTH_A-1:0] current_contents; + reg [C_ADDRA_WIDTH-1:0] address; + integer i; + begin + // Shift the address by the ratio + address = (addr/WRITE_ADDR_A_DIV); + if (address >= C_WRITE_DEPTH_A) begin + if (!C_DISABLE_WARN_BHV_RANGE) begin + $fdisplay(ADDRFILE, + "%0s WARNING: Address %0h is outside range for A Write", + C_CORENAME, addr); + end + + // valid address + end else begin + + // Combine w/ byte writes + if (C_USE_BYTE_WEA) begin + + // Get the current memory contents + if (WRITE_WIDTH_RATIO_A == 1) begin + // Workaround for IUS 5.5 part-select issue + current_contents = memory[address]; + end else begin + for (i = 0; i < WRITE_WIDTH_RATIO_A; i = i + 1) begin + current_contents[MIN_WIDTH*i+:MIN_WIDTH] + = memory[address*WRITE_WIDTH_RATIO_A + i]; + end + end + + // Apply incoming bytes + if (C_WEA_WIDTH == 1) begin + // Workaround for IUS 5.5 part-select issue + if (byte_en[0]) begin + current_contents = data; + end + end else begin + for (i = 0; i < C_WEA_WIDTH; i = i + 1) begin + if (byte_en[i]) begin + current_contents[BYTE_SIZE*i+:BYTE_SIZE] + = data[BYTE_SIZE*i+:BYTE_SIZE]; + end + end + end + + // No byte-writes, overwrite the whole word + end else begin + current_contents = data; + end + + // Insert double bit errors: + if (C_USE_ECC == 1) begin + if ((C_HAS_INJECTERR == 2 || C_HAS_INJECTERR == 3) && inj_dbiterr == 1'b1) begin + current_contents[0] = !(current_contents[0]); + current_contents[1] = !(current_contents[1]); + end + end + + // Insert softecc double bit errors: + if (C_USE_SOFTECC == 1) begin + if ((C_HAS_INJECTERR == 2 || C_HAS_INJECTERR == 3) && inj_dbiterr == 1'b1) begin + doublebit_error[C_WRITE_WIDTH_A+CHKBIT_WIDTH-1:2] = doublebit_error[C_WRITE_WIDTH_A+CHKBIT_WIDTH-3:0]; + doublebit_error[0] = doublebit_error[C_WRITE_WIDTH_A+CHKBIT_WIDTH-1]; + doublebit_error[1] = doublebit_error[C_WRITE_WIDTH_A+CHKBIT_WIDTH-2]; + current_contents = current_contents ^ doublebit_error[C_WRITE_WIDTH_A-1:0]; + end + end + + // Write data to memory + if (WRITE_WIDTH_RATIO_A == 1) begin + // Workaround for IUS 5.5 part-select issue + memory[address*WRITE_WIDTH_RATIO_A] = current_contents; + end else begin + for (i = 0; i < WRITE_WIDTH_RATIO_A; i = i + 1) begin + memory[address*WRITE_WIDTH_RATIO_A + i] + = current_contents[MIN_WIDTH*i+:MIN_WIDTH]; + end + end + + // Store the address at which error is injected: + if ((C_FAMILY == "virtex6") && C_USE_ECC == 1) begin + if ((C_HAS_INJECTERR == 1 && inj_sbiterr == 1'b1) || + (C_HAS_INJECTERR == 3 && inj_sbiterr == 1'b1 && inj_dbiterr != 1'b1)) + begin + sbiterr_arr[addr] = 1; + end else begin + sbiterr_arr[addr] = 0; + end + + if ((C_HAS_INJECTERR == 2 || C_HAS_INJECTERR == 3) && inj_dbiterr == 1'b1) begin + dbiterr_arr[addr] = 1; + end else begin + dbiterr_arr[addr] = 0; + end + end + + // Store the address at which softecc error is injected: + if (C_USE_SOFTECC == 1) begin + if ((C_HAS_INJECTERR == 1 && inj_sbiterr == 1'b1) || + (C_HAS_INJECTERR == 3 && inj_sbiterr == 1'b1 && inj_dbiterr != 1'b1)) + begin + softecc_sbiterr_arr[addr] = 1; + end else begin + softecc_sbiterr_arr[addr] = 0; + end + + if ((C_HAS_INJECTERR == 2 || C_HAS_INJECTERR == 3) && inj_dbiterr == 1'b1) begin + softecc_dbiterr_arr[addr] = 1; + end else begin + softecc_dbiterr_arr[addr] = 0; + end + end + + end + end + endtask + + //************** + // write_b + //************** + task write_b + (input reg [C_ADDRB_WIDTH-1:0] addr, + input reg [C_WEB_WIDTH-1:0] byte_en, + input reg [C_WRITE_WIDTH_B-1:0] data); + reg [C_WRITE_WIDTH_B-1:0] current_contents; + reg [C_ADDRB_WIDTH-1:0] address; + integer i; + begin + // Shift the address by the ratio + address = (addr/WRITE_ADDR_B_DIV); + if (address >= C_WRITE_DEPTH_B) begin + if (!C_DISABLE_WARN_BHV_RANGE) begin + $fdisplay(ADDRFILE, + "%0s WARNING: Address %0h is outside range for B Write", + C_CORENAME, addr); + end + + // valid address + end else begin + + // Combine w/ byte writes + if (C_USE_BYTE_WEB) begin + + // Get the current memory contents + if (WRITE_WIDTH_RATIO_B == 1) begin + // Workaround for IUS 5.5 part-select issue + current_contents = memory[address]; + end else begin + for (i = 0; i < WRITE_WIDTH_RATIO_B; i = i + 1) begin + current_contents[MIN_WIDTH*i+:MIN_WIDTH] + = memory[address*WRITE_WIDTH_RATIO_B + i]; + end + end + + // Apply incoming bytes + if (C_WEB_WIDTH == 1) begin + // Workaround for IUS 5.5 part-select issue + if (byte_en[0]) begin + current_contents = data; + end + end else begin + for (i = 0; i < C_WEB_WIDTH; i = i + 1) begin + if (byte_en[i]) begin + current_contents[BYTE_SIZE*i+:BYTE_SIZE] + = data[BYTE_SIZE*i+:BYTE_SIZE]; + end + end + end + + // No byte-writes, overwrite the whole word + end else begin + current_contents = data; + end + + // Write data to memory + if (WRITE_WIDTH_RATIO_B == 1) begin + // Workaround for IUS 5.5 part-select issue + memory[address*WRITE_WIDTH_RATIO_B] = current_contents; + end else begin + for (i = 0; i < WRITE_WIDTH_RATIO_B; i = i + 1) begin + memory[address*WRITE_WIDTH_RATIO_B + i] + = current_contents[MIN_WIDTH*i+:MIN_WIDTH]; + end + end + end + end + endtask + + //************** + // read_a + //************** + task read_a + (input reg [C_ADDRA_WIDTH-1:0] addr, + input reg reset); + reg [C_ADDRA_WIDTH-1:0] address; + integer i; + begin + + if (reset) begin + memory_out_a <= #FLOP_DELAY inita_val; + end else begin + // Shift the address by the ratio + address = (addr/READ_ADDR_A_DIV); + if (address >= C_READ_DEPTH_A) begin + if (!C_DISABLE_WARN_BHV_RANGE) begin + $fdisplay(ADDRFILE, + "%0s WARNING: Address %0h is outside range for A Read", + C_CORENAME, addr); + end + memory_out_a <= #FLOP_DELAY 'bX; + // valid address + end else begin + if (READ_WIDTH_RATIO_A==1) begin + memory_out_a <= #FLOP_DELAY memory[address*READ_WIDTH_RATIO_A]; + end else begin + // Increment through the 'partial' words in the memory + for (i = 0; i < READ_WIDTH_RATIO_A; i = i + 1) begin + memory_out_a[MIN_WIDTH*i+:MIN_WIDTH] + <= #FLOP_DELAY memory[address*READ_WIDTH_RATIO_A + i]; + end + end //end READ_WIDTH_RATIO_A==1 loop + + end //end valid address loop + end //end reset-data assignment loops + end + endtask + + //************** + // read_b + //************** + task read_b + (input reg [C_ADDRB_WIDTH-1:0] addr, + input reg reset); + reg [C_ADDRB_WIDTH-1:0] address; + integer i; + begin + + if (reset) begin + memory_out_b <= #FLOP_DELAY initb_val; + sbiterr_in <= #FLOP_DELAY 1'b0; + dbiterr_in <= #FLOP_DELAY 1'b0; + rdaddrecc_in <= #FLOP_DELAY 0; + end else begin + // Shift the address + address = (addr/READ_ADDR_B_DIV); + if (address >= C_READ_DEPTH_B) begin + if (!C_DISABLE_WARN_BHV_RANGE) begin + $fdisplay(ADDRFILE, + "%0s WARNING: Address %0h is outside range for B Read", + C_CORENAME, addr); + end + memory_out_b <= #FLOP_DELAY 'bX; + sbiterr_in <= #FLOP_DELAY 1'bX; + dbiterr_in <= #FLOP_DELAY 1'bX; + rdaddrecc_in <= #FLOP_DELAY 'bX; + // valid address + end else begin + if (READ_WIDTH_RATIO_B==1) begin + memory_out_b <= #FLOP_DELAY memory[address*READ_WIDTH_RATIO_B]; + end else begin + // Increment through the 'partial' words in the memory + for (i = 0; i < READ_WIDTH_RATIO_B; i = i + 1) begin + memory_out_b[MIN_WIDTH*i+:MIN_WIDTH] + <= #FLOP_DELAY memory[address*READ_WIDTH_RATIO_B + i]; + end + end + + if ((C_FAMILY == "virtex6") && C_USE_ECC == 1) begin + rdaddrecc_in <= #FLOP_DELAY addr; + if (sbiterr_arr[addr] == 1) begin + sbiterr_in <= #FLOP_DELAY 1'b1; + end else begin + sbiterr_in <= #FLOP_DELAY 1'b0; + end + + if (dbiterr_arr[addr] == 1) begin + dbiterr_in <= #FLOP_DELAY 1'b1; + end else begin + dbiterr_in <= #FLOP_DELAY 1'b0; + end +///// end else begin +///// rdaddrecc_in <= #FLOP_DELAY 0; +///// dbiterr_in <= #FLOP_DELAY 1'b0; +///// sbiterr_in <= #FLOP_DELAY 1'b0; +///// end //end ECC Loop + + end else if (C_USE_SOFTECC == 1) begin + rdaddrecc_in <= #FLOP_DELAY addr; + if (softecc_sbiterr_arr[addr] == 1) begin + sbiterr_in <= #FLOP_DELAY 1'b1; + end else begin + sbiterr_in <= #FLOP_DELAY 1'b0; + end + + if (softecc_dbiterr_arr[addr] == 1) begin + dbiterr_in <= #FLOP_DELAY 1'b1; + end else begin + dbiterr_in <= #FLOP_DELAY 1'b0; + end + end else begin + rdaddrecc_in <= #FLOP_DELAY 0; + dbiterr_in <= #FLOP_DELAY 1'b0; + sbiterr_in <= #FLOP_DELAY 1'b0; + end //end SOFTECC Loop + + end //end Valid address loop + end //end reset-data assignment loops + end + endtask + + //************** + // reset_a + //************** + task reset_a (input reg reset); + begin + if (reset) memory_out_a <= #FLOP_DELAY inita_val; + end + endtask + + //************** + // reset_b + //************** + task reset_b (input reg reset); + begin + if (reset) memory_out_b <= #FLOP_DELAY initb_val; + end + endtask + + //************** + // init_memory + //************** + task init_memory; + integer i, addr_step; + integer status; + reg [C_WRITE_WIDTH_A-1:0] default_data; + begin + default_data = 0; + + //Display output message indicating that the behavioral model is being + //initialized + if (C_USE_DEFAULT_DATA || C_LOAD_INIT_FILE) $display(" Block Memory Generator CORE Generator module loading initial data..."); + + // Convert the default to hex + if (C_USE_DEFAULT_DATA) begin + if (default_data_str == "") begin + $fdisplay(ERRFILE, "%0s ERROR: C_DEFAULT_DATA is empty!", C_CORENAME); + $finish; + end else begin + status = $sscanf(default_data_str, "%h", default_data); + if (status == 0) begin + $fdisplay(ERRFILE, {"%0s ERROR: Unsuccessful hexadecimal read", + "from C_DEFAULT_DATA: %0s"}, + C_CORENAME, C_DEFAULT_DATA); + $finish; + end + end + end + + // Step by WRITE_ADDR_A_DIV through the memory via the + // Port A write interface to hit every location once + addr_step = WRITE_ADDR_A_DIV; + + // 'write' to every location with default (or 0) + for (i = 0; i < C_WRITE_DEPTH_A*addr_step; i = i + addr_step) begin + write_a(i, {C_WEA_WIDTH{1'b1}}, default_data, 1'b0, 1'b0); + end + + // Get specialized data from the MIF file + if (C_LOAD_INIT_FILE) begin + if (init_file_str == "") begin + $fdisplay(ERRFILE, "%0s ERROR: C_INIT_FILE_NAME is empty!", + C_CORENAME); + $finish; + end else begin + initfile = $fopen(init_file_str, "r"); + if (initfile == 0) begin + $fdisplay(ERRFILE, {"%0s, ERROR: Problem opening", + "C_INIT_FILE_NAME: %0s!"}, + C_CORENAME, init_file_str); + $finish; + end else begin + // loop through the mif file, loading in the data + for (i = 0; i < C_WRITE_DEPTH_A*addr_step; i = i + addr_step) begin + status = $fscanf(initfile, "%b", mif_data); + if (status > 0) begin + write_a(i, {C_WEA_WIDTH{1'b1}}, mif_data, 1'b0, 1'b0); + end + end + $fclose(initfile); + end //initfile + end //init_file_str + end //C_LOAD_INIT_FILE + + //Display output message indicating that the behavioral model is done + //initializing + if (C_USE_DEFAULT_DATA || C_LOAD_INIT_FILE) + $display(" Block Memory Generator data initialization complete."); + end + endtask + + //************** + // log2roundup + //************** + function integer log2roundup (input integer data_value); + integer width; + integer cnt; + begin + width = 0; + + if (data_value > 1) begin + for(cnt=1 ; cnt < data_value ; cnt = cnt * 2) begin + width = width + 1; + end //loop + end //if + + log2roundup = width; + + end //log2roundup + endfunction + + + //******************* + // collision_check + //******************* + function integer collision_check (input reg [C_ADDRA_WIDTH-1:0] addr_a, + input integer iswrite_a, + input reg [C_ADDRB_WIDTH-1:0] addr_b, + input integer iswrite_b); + reg c_aw_bw, c_aw_br, c_ar_bw; + integer scaled_addra_to_waddrb_width; + integer scaled_addrb_to_waddrb_width; + integer scaled_addra_to_waddra_width; + integer scaled_addrb_to_waddra_width; + integer scaled_addra_to_raddrb_width; + integer scaled_addrb_to_raddrb_width; + integer scaled_addra_to_raddra_width; + integer scaled_addrb_to_raddra_width; + + + + begin + + c_aw_bw = 0; + c_aw_br = 0; + c_ar_bw = 0; + + //If write_addr_b_width is smaller, scale both addresses to that width for + //comparing write_addr_a and write_addr_b; addr_a starts as C_ADDRA_WIDTH, + //scale it down to write_addr_b_width. addr_b starts as C_ADDRB_WIDTH, + //scale it down to write_addr_b_width. Once both are scaled to + //write_addr_b_width, compare. + scaled_addra_to_waddrb_width = ((addr_a)/ + 2**(C_ADDRA_WIDTH-write_addr_b_width)); + scaled_addrb_to_waddrb_width = ((addr_b)/ + 2**(C_ADDRB_WIDTH-write_addr_b_width)); + + //If write_addr_a_width is smaller, scale both addresses to that width for + //comparing write_addr_a and write_addr_b; addr_a starts as C_ADDRA_WIDTH, + //scale it down to write_addr_a_width. addr_b starts as C_ADDRB_WIDTH, + //scale it down to write_addr_a_width. Once both are scaled to + //write_addr_a_width, compare. + scaled_addra_to_waddra_width = ((addr_a)/ + 2**(C_ADDRA_WIDTH-write_addr_a_width)); + scaled_addrb_to_waddra_width = ((addr_b)/ + 2**(C_ADDRB_WIDTH-write_addr_a_width)); + + //If read_addr_b_width is smaller, scale both addresses to that width for + //comparing write_addr_a and read_addr_b; addr_a starts as C_ADDRA_WIDTH, + //scale it down to read_addr_b_width. addr_b starts as C_ADDRB_WIDTH, + //scale it down to read_addr_b_width. Once both are scaled to + //read_addr_b_width, compare. + scaled_addra_to_raddrb_width = ((addr_a)/ + 2**(C_ADDRA_WIDTH-read_addr_b_width)); + scaled_addrb_to_raddrb_width = ((addr_b)/ + 2**(C_ADDRB_WIDTH-read_addr_b_width)); + + //If read_addr_a_width is smaller, scale both addresses to that width for + //comparing read_addr_a and write_addr_b; addr_a starts as C_ADDRA_WIDTH, + //scale it down to read_addr_a_width. addr_b starts as C_ADDRB_WIDTH, + //scale it down to read_addr_a_width. Once both are scaled to + //read_addr_a_width, compare. + scaled_addra_to_raddra_width = ((addr_a)/ + 2**(C_ADDRA_WIDTH-read_addr_a_width)); + scaled_addrb_to_raddra_width = ((addr_b)/ + 2**(C_ADDRB_WIDTH-read_addr_a_width)); + + //Look for a write-write collision. In order for a write-write + //collision to exist, both ports must have a write transaction. + if (iswrite_a && iswrite_b) begin + if (write_addr_a_width > write_addr_b_width) begin + if (scaled_addra_to_waddrb_width == scaled_addrb_to_waddrb_width) begin + c_aw_bw = 1; + end else begin + c_aw_bw = 0; + end + end else begin + if (scaled_addrb_to_waddra_width == scaled_addra_to_waddra_width) begin + c_aw_bw = 1; + end else begin + c_aw_bw = 0; + end + end //width + end //iswrite_a and iswrite_b + + //If the B port is reading (which means it is enabled - so could be + //a TX_WRITE or TX_READ), then check for a write-read collision). + //This could happen whether or not a write-write collision exists due + //to asymmetric write/read ports. + if (iswrite_a) begin + if (write_addr_a_width > read_addr_b_width) begin + if (scaled_addra_to_raddrb_width == scaled_addrb_to_raddrb_width) begin + c_aw_br = 1; + end else begin + c_aw_br = 0; + end + end else begin + if (scaled_addrb_to_waddra_width == scaled_addra_to_waddra_width) begin + c_aw_br = 1; + end else begin + c_aw_br = 0; + end + end //width + end //iswrite_a + + //If the A port is reading (which means it is enabled - so could be + // a TX_WRITE or TX_READ), then check for a write-read collision). + //This could happen whether or not a write-write collision exists due + // to asymmetric write/read ports. + if (iswrite_b) begin + if (read_addr_a_width > write_addr_b_width) begin + if (scaled_addra_to_waddrb_width == scaled_addrb_to_waddrb_width) begin + c_ar_bw = 1; + end else begin + c_ar_bw = 0; + end + end else begin + if (scaled_addrb_to_raddra_width == scaled_addra_to_raddra_width) begin + c_ar_bw = 1; + end else begin + c_ar_bw = 0; + end + end //width + end //iswrite_b + + + + collision_check = c_aw_bw | c_aw_br | c_ar_bw; + + end + endfunction + + //******************************* + // power on values + //******************************* + initial begin + // Load up the memory + init_memory; + // Load up the output registers and latches + if ($sscanf(inita_str, "%h", inita_val)) begin + memory_out_a = inita_val; + end else begin + memory_out_a = 0; + end + if ($sscanf(initb_str, "%h", initb_val)) begin + memory_out_b = initb_val; + end else begin + memory_out_b = 0; + end + + sbiterr_in = 1'b0; + dbiterr_in = 1'b0; + rdaddrecc_in = 0; + + // Determine the effective address widths for each of the 4 ports + write_addr_a_width = C_ADDRA_WIDTH - log2roundup(WRITE_ADDR_A_DIV); + read_addr_a_width = C_ADDRA_WIDTH - log2roundup(READ_ADDR_A_DIV); + write_addr_b_width = C_ADDRB_WIDTH - log2roundup(WRITE_ADDR_B_DIV); + read_addr_b_width = C_ADDRB_WIDTH - log2roundup(READ_ADDR_B_DIV); + + $display("Block Memory Generator CORE Generator module %m is using a behavioral model for simulation which will not precisely model memory collision behavior."); + + end + + //************************************************************************* + // Asynchronous reset of Port A and Port B are performed here + // Note that the asynchronous reset feature is only supported in Spartan6 + // devices + //************************************************************************* + generate if((C_FAMILY == "spartan6") && C_RST_TYPE=="ASYNC") begin : async_rst + if (C_RST_PRIORITY_A=="CE") begin + always @ (*) begin + if (rea_i) reset_a(reseta_i); + end + end + else begin + always @ (*) begin + reset_a(reseta_i); + end + end + + if (C_RST_PRIORITY_B=="CE") begin + always @ (*) begin + if (reb_i) reset_b(resetb_i); + end + end + else begin + always @ (*) begin + reset_b(resetb_i); + end + end + + end + endgenerate + + //*************************************************************************** + // These are the main blocks which schedule read and write operations + // Note that the reset priority feature at the latch stage is only supported + // for Spartan-6. For other families, the default priority at the latch stage + // is "CE" + //*************************************************************************** + // Synchronous clocks: schedule port operations with respect to + // both write operating modes + generate + if(C_COMMON_CLK && (C_WRITE_MODE_A == "WRITE_FIRST") && (C_WRITE_MODE_B == + "WRITE_FIRST")) begin : com_clk_sched_wf_wf + always @(posedge CLKA) begin + //Write A + if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR); + //Write B + if (web_i) write_b(ADDRB, web_i, DINB); + //Read A + if ((C_FAMILY == "spartan6") && C_RST_PRIORITY_A=="SR") begin + if (reseta_i) reset_a(reseta_i); + else if (rea_i) read_a(ADDRA, reseta_i); + end else begin + if (rea_i) read_a(ADDRA, reseta_i); + end + //Read B + if ((C_FAMILY == "spartan6") && C_RST_PRIORITY_B=="SR") begin + if (resetb_i) reset_b(resetb_i); + else if (reb_i) read_b(ADDRB, resetb_i); + end else begin + if (reb_i) read_b(ADDRB, resetb_i); + end + end + end + else + if(C_COMMON_CLK && (C_WRITE_MODE_A == "READ_FIRST") && (C_WRITE_MODE_B == + "WRITE_FIRST")) begin : com_clk_sched_rf_wf + always @(posedge CLKA) begin + //Write B + if (web_i) write_b(ADDRB, web_i, DINB); + //Read B + if ((C_FAMILY == "spartan6") && C_RST_PRIORITY_B=="SR") begin + if (resetb_i) reset_b(resetb_i); + else if (reb_i) read_b(ADDRB, resetb_i); + end else begin + if (reb_i) read_b(ADDRB, resetb_i); + end + //Read A + if ((C_FAMILY == "spartan6") && C_RST_PRIORITY_A=="SR") begin + if (reseta_i) reset_a(reseta_i); + else if (rea_i) read_a(ADDRA, reseta_i); + end else begin + if (rea_i) read_a(ADDRA, reseta_i); + end + //Write A + if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR); + end + end + else + if(C_COMMON_CLK && (C_WRITE_MODE_A == "WRITE_FIRST") && (C_WRITE_MODE_B == + "READ_FIRST")) begin : com_clk_sched_wf_rf + always @(posedge CLKA) begin + //Write A + if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR); + //Read A + if ((C_FAMILY == "spartan6") && C_RST_PRIORITY_A=="SR") begin + if (reseta_i) reset_a(reseta_i); + else if (rea_i) read_a(ADDRA, reseta_i); + end else begin + if (rea_i) read_a(ADDRA, reseta_i); + end + //Read B + if ((C_FAMILY == "spartan6") && C_RST_PRIORITY_B=="SR") begin + if (resetb_i) reset_b(resetb_i); + else if (reb_i) read_b(ADDRB, resetb_i); + end else begin + if (reb_i) read_b(ADDRB, resetb_i); + end + //Write B + if (web_i) write_b(ADDRB, web_i, DINB); + end + end + else + if(C_COMMON_CLK && (C_WRITE_MODE_A == "READ_FIRST") && (C_WRITE_MODE_B == + "READ_FIRST")) begin : com_clk_sched_rf_rf + always @(posedge CLKA) begin + //Read A + if ((C_FAMILY == "spartan6") && C_RST_PRIORITY_A=="SR") begin + if (reseta_i) reset_a(reseta_i); + else if (rea_i) read_a(ADDRA, reseta_i); + end else begin + if (rea_i) read_a(ADDRA, reseta_i); + end + //Read B + if ((C_FAMILY == "spartan6") && C_RST_PRIORITY_B=="SR") begin + if (resetb_i) reset_b(resetb_i); + else if (reb_i) read_b(ADDRB, resetb_i); + end else begin + if (reb_i) read_b(ADDRB, resetb_i); + end + //Write A + if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR); + //Write B + if (web_i) write_b(ADDRB, web_i, DINB); + end + end + else if(C_COMMON_CLK && (C_WRITE_MODE_A =="WRITE_FIRST") && (C_WRITE_MODE_B == + "NO_CHANGE")) begin : com_clk_sched_wf_nc + always @(posedge CLKA) begin + //Write A + if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR); + //Read A + if ((C_FAMILY == "spartan6") && C_RST_PRIORITY_A=="SR") begin + if (reseta_i) reset_a(reseta_i); + else if (rea_i) read_a(ADDRA, reseta_i); + end else begin + if (rea_i) read_a(ADDRA, reseta_i); + end + //Read B + if ((C_FAMILY == "spartan6") && C_RST_PRIORITY_B=="SR") begin + if (resetb_i) reset_b(resetb_i); + else if (reb_i && !web_i) read_b(ADDRB, resetb_i); + end else begin + if (reb_i && (!web_i || resetb_i)) read_b(ADDRB, resetb_i); + end + //Write B + if (web_i) write_b(ADDRB, web_i, DINB); + end + end + else if(C_COMMON_CLK && (C_WRITE_MODE_A =="READ_FIRST") && (C_WRITE_MODE_B == + "NO_CHANGE")) begin : com_clk_sched_rf_nc + always @(posedge CLKA) begin + //Read A + if ((C_FAMILY == "spartan6") && C_RST_PRIORITY_A=="SR") begin + if (reseta_i) reset_a(reseta_i); + else if (rea_i) read_a(ADDRA, reseta_i); + end else begin + if (rea_i) read_a(ADDRA, reseta_i); + end + //Read B + if ((C_FAMILY == "spartan6") && C_RST_PRIORITY_B=="SR") begin + if (resetb_i) reset_b(resetb_i); + else if (reb_i && !web_i) read_b(ADDRB, resetb_i); + end else begin + if (reb_i && (!web_i || resetb_i)) read_b(ADDRB, resetb_i); + end + //Write A + if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR); + //Write B + if (web_i) write_b(ADDRB, web_i, DINB); + end + end + else if(C_COMMON_CLK && (C_WRITE_MODE_A =="NO_CHANGE") && (C_WRITE_MODE_B == + "WRITE_FIRST")) begin : com_clk_sched_nc_wf + always @(posedge CLKA) begin + //Write A + if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR); + //Write B + if (web_i) write_b(ADDRB, web_i, DINB); + //Read A + if ((C_FAMILY == "spartan6") && C_RST_PRIORITY_A=="SR") begin + if (reseta_i) reset_a(reseta_i); + else if (rea_i && !wea_i) read_a(ADDRA, reseta_i); + end else begin + if (rea_i && (!wea_i || reseta_i)) read_a(ADDRA, reseta_i); + end + //Read B + if ((C_FAMILY == "spartan6") && C_RST_PRIORITY_B=="SR") begin + if (resetb_i) reset_b(resetb_i); + else if (reb_i) read_b(ADDRB, resetb_i); + end else begin + if (reb_i) read_b(ADDRB, resetb_i); + end + end + end + else if(C_COMMON_CLK && (C_WRITE_MODE_A =="NO_CHANGE") && (C_WRITE_MODE_B == + "READ_FIRST")) begin : com_clk_sched_nc_rf + always @(posedge CLKA) begin + //Read B + if ((C_FAMILY == "spartan6") && C_RST_PRIORITY_B=="SR") begin + if (resetb_i) reset_b(resetb_i); + else if (reb_i) read_b(ADDRB, resetb_i); + end else begin + if (reb_i) read_b(ADDRB, resetb_i); + end + //Read A + if ((C_FAMILY == "spartan6") && C_RST_PRIORITY_A=="SR") begin + if (reseta_i) reset_a(reseta_i); + else if (rea_i && !wea_i) read_a(ADDRA, reseta_i); + end else begin + if (rea_i && (!wea_i || reseta_i)) read_a(ADDRA, reseta_i); + end + //Write A + if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR); + //Write B + if (web_i) write_b(ADDRB, web_i, DINB); + end + end + else if(C_COMMON_CLK && (C_WRITE_MODE_A =="NO_CHANGE") && (C_WRITE_MODE_B == + "NO_CHANGE")) begin : com_clk_sched_nc_nc + always @(posedge CLKA) begin + //Write A + if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR); + //Write B + if (web_i) write_b(ADDRB, web_i, DINB); + //Read A + if ((C_FAMILY == "spartan6") && C_RST_PRIORITY_A=="SR") begin + if (reseta_i) reset_a(reseta_i); + else if (rea_i && !wea_i) read_a(ADDRA, reseta_i); + end else begin + if (rea_i && (!wea_i || reseta_i)) read_a(ADDRA, reseta_i); + end + //Read B + if ((C_FAMILY == "spartan6") && C_RST_PRIORITY_B=="SR") begin + if (resetb_i) reset_b(resetb_i); + else if (reb_i && !web_i) read_b(ADDRB, resetb_i); + end else begin + if (reb_i && (!web_i || resetb_i)) read_b(ADDRB, resetb_i); + end + end + end + else if(C_COMMON_CLK) begin: com_clk_sched_default + always @(posedge CLKA) begin + //Write A + if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR); + //Write B + if (web_i) write_b(ADDRB, web_i, DINB); + //Read A + if ((C_FAMILY == "spartan6") && C_RST_PRIORITY_A=="SR") begin + if (reseta_i) reset_a(reseta_i); + else if (rea_i) read_a(ADDRA, reseta_i); + end else begin + if (rea_i) read_a(ADDRA, reseta_i); + end + //Read B + if ((C_FAMILY == "spartan6") && C_RST_PRIORITY_B=="SR") begin + if (resetb_i) reset_b(resetb_i); + else if (reb_i) read_b(ADDRB, resetb_i); + end else begin + if (reb_i) read_b(ADDRB, resetb_i); + end + end + end + endgenerate + + // Asynchronous clocks: port operation is independent + + generate + if((!C_COMMON_CLK) && (C_WRITE_MODE_A == "WRITE_FIRST")) begin : async_clk_sched_clka_wf + always @(posedge CLKA) begin + //Write A + if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR); + //Read A + if ((C_FAMILY == "spartan6") && C_RST_PRIORITY_A=="SR") begin + if (reseta_i) reset_a(reseta_i); + else if (rea_i) read_a(ADDRA, reseta_i); + end else begin + if (rea_i) read_a(ADDRA, reseta_i); + end + end + end + else if((!C_COMMON_CLK) && (C_WRITE_MODE_A == "READ_FIRST")) begin : async_clk_sched_clka_rf + always @(posedge CLKA) begin + //Read A + if ((C_FAMILY == "spartan6") && C_RST_PRIORITY_A=="SR") begin + if (reseta_i) reset_a(reseta_i); + else if (rea_i) read_a(ADDRA, reseta_i); + end else begin + if (rea_i) read_a(ADDRA, reseta_i); + end + //Write A + if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR); + end + end + else if((!C_COMMON_CLK) && (C_WRITE_MODE_A == "NO_CHANGE")) begin : async_clk_sched_clka_nc + always @(posedge CLKA) begin + //Write A + if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR); + //Read A + if ((C_FAMILY == "spartan6") && C_RST_PRIORITY_A=="SR") begin + if (reseta_i) reset_a(reseta_i); + else if (rea_i && !wea_i) read_a(ADDRA, reseta_i); + end else begin + if (rea_i && (!wea_i || reseta_i)) read_a(ADDRA, reseta_i); + end + end + end + endgenerate + + generate + if ((!C_COMMON_CLK) && (C_WRITE_MODE_B == "WRITE_FIRST")) begin: async_clk_sched_clkb_wf + always @(posedge CLKB) begin + //Write B + if (web_i) write_b(ADDRB, web_i, DINB); + //Read B + if ((C_FAMILY == "spartan6") && C_RST_PRIORITY_B=="SR") begin + if (resetb_i) reset_b(resetb_i); + else if (reb_i) read_b(ADDRB, resetb_i); + end else begin + if (reb_i) read_b(ADDRB, resetb_i); + end + end + end + else if ((!C_COMMON_CLK) && (C_WRITE_MODE_B == "READ_FIRST")) begin: async_clk_sched_clkb_rf + always @(posedge CLKB) begin + //Read B + if ((C_FAMILY == "spartan6") && C_RST_PRIORITY_B=="SR") begin + if (resetb_i) reset_b(resetb_i); + else if (reb_i) read_b(ADDRB, resetb_i); + end else begin + if (reb_i) read_b(ADDRB, resetb_i); + end + //Write B + if (web_i) write_b(ADDRB, web_i, DINB); + end + end + else if ((!C_COMMON_CLK) && (C_WRITE_MODE_B == "NO_CHANGE")) begin: async_clk_sched_clkb_nc + always @(posedge CLKB) begin + //Write B + if (web_i) write_b(ADDRB, web_i, DINB); + //Read B + if ((C_FAMILY == "spartan6") && C_RST_PRIORITY_B=="SR") begin + if (resetb_i) reset_b(resetb_i); + else if (reb_i && !web_i) read_b(ADDRB, resetb_i); + end else begin + if (reb_i && (!web_i || resetb_i)) read_b(ADDRB, resetb_i); + end + end + end + endgenerate + + + //*************************************************************** + // Instantiate the variable depth output register stage module + //*************************************************************** + // Port A + BLK_MEM_GEN_V4_2_output_stage + #(.C_FAMILY (C_FAMILY), + .C_XDEVICEFAMILY (C_XDEVICEFAMILY), + .C_RST_TYPE (C_RST_TYPE), + .C_HAS_RST (C_HAS_RSTA), + .C_RSTRAM (C_RSTRAM_A), + .C_RST_PRIORITY (C_RST_PRIORITY_A), + .C_INIT_VAL (C_INITA_VAL), + .C_HAS_EN (C_HAS_ENA), + .C_HAS_REGCE (C_HAS_REGCEA), + .C_DATA_WIDTH (C_READ_WIDTH_A), + .C_ADDRB_WIDTH (C_ADDRB_WIDTH), + .C_HAS_MEM_OUTPUT_REGS (C_HAS_MEM_OUTPUT_REGS_A), + .C_USE_SOFTECC (C_USE_SOFTECC), + .C_USE_ECC (C_USE_ECC), + .NUM_STAGES (NUM_OUTPUT_STAGES_A), + .FLOP_DELAY (FLOP_DELAY)) + reg_a + (.CLK (CLKA), + .RST (RSTA), + .EN (ENA), + .REGCE (REGCEA), + .DIN (memory_out_a), + .DOUT (DOUTA), + .SBITERR_IN (1'b0), + .DBITERR_IN (1'b0), + .SBITERR (), + .DBITERR (), + .RDADDRECC_IN ({C_ADDRB_WIDTH{1'b0}}), + .RDADDRECC () + ); + + // Port B + BLK_MEM_GEN_V4_2_output_stage + #(.C_FAMILY (C_FAMILY), + .C_XDEVICEFAMILY (C_XDEVICEFAMILY), + .C_RST_TYPE (C_RST_TYPE), + .C_HAS_RST (C_HAS_RSTB), + .C_RSTRAM (C_RSTRAM_B), + .C_RST_PRIORITY (C_RST_PRIORITY_B), + .C_INIT_VAL (C_INITB_VAL), + .C_HAS_EN (C_HAS_ENB), + .C_HAS_REGCE (C_HAS_REGCEB), + .C_DATA_WIDTH (C_READ_WIDTH_B), + .C_ADDRB_WIDTH (C_ADDRB_WIDTH), + .C_HAS_MEM_OUTPUT_REGS (C_HAS_MEM_OUTPUT_REGS_B), + .C_USE_SOFTECC (C_USE_SOFTECC), + .C_USE_ECC (C_USE_ECC), + .NUM_STAGES (NUM_OUTPUT_STAGES_B), + .FLOP_DELAY (FLOP_DELAY)) + reg_b + (.CLK (CLKB), + .RST (RSTB), + .EN (ENB), + .REGCE (REGCEB), + .DIN (memory_out_b), + .DOUT (dout_i), + .SBITERR_IN (sbiterr_in), + .DBITERR_IN (dbiterr_in), + .SBITERR (sbiterr_i), + .DBITERR (dbiterr_i), + .RDADDRECC_IN (rdaddrecc_in), + .RDADDRECC (rdaddrecc_i) + ); + + //*************************************************************** + // Instantiate the Input and Output register stages + //*************************************************************** +BLK_MEM_GEN_V4_2_softecc_output_reg_stage + #(.C_DATA_WIDTH (C_READ_WIDTH_B), + .C_ADDRB_WIDTH (C_ADDRB_WIDTH), + .C_HAS_SOFTECC_OUTPUT_REGS_B (C_HAS_SOFTECC_OUTPUT_REGS_B), + .C_USE_SOFTECC (C_USE_SOFTECC), + .FLOP_DELAY (FLOP_DELAY)) + has_softecc_output_reg_stage + (.CLK (CLKB), + .DIN (dout_i), + .DOUT (DOUTB), + .SBITERR_IN (sbiterr_i), + .DBITERR_IN (dbiterr_i), + .SBITERR (sbiterr_sdp), + .DBITERR (dbiterr_sdp), + .RDADDRECC_IN (rdaddrecc_i), + .RDADDRECC (rdaddrecc_sdp) +); + + //**************************************************** + // Synchronous collision checks + //**************************************************** + generate if (!C_DISABLE_WARN_BHV_COLL && C_COMMON_CLK) begin : sync_coll + always @(posedge CLKA) begin + // Possible collision if both are enabled and the addresses match + if (ena_i && enb_i) begin + if (wea_i || web_i) begin + is_collision <= collision_check(ADDRA, wea_i, ADDRB, web_i); + end else begin + is_collision <= 0; + end + end else begin + is_collision <= 0; + end + + // If the write port is in READ_FIRST mode, there is no collision + if (C_WRITE_MODE_A=="READ_FIRST" && wea_i && !web_i) begin + is_collision <= 0; + end + if (C_WRITE_MODE_B=="READ_FIRST" && web_i && !wea_i) begin + is_collision <= 0; + end + + // Only flag if one of the accesses is a write + if (is_collision && (wea_i || web_i)) begin + $fwrite(COLLFILE, "%0s collision detected at time: %0d, ", + C_CORENAME, $time); + $fwrite(COLLFILE, "A %0s address: %0h, B %0s address: %0h\n", + wea_i ? "write" : "read", ADDRA, + web_i ? "write" : "read", ADDRB); + end + end + + //**************************************************** + // Asynchronous collision checks + //**************************************************** + end else if (!C_DISABLE_WARN_BHV_COLL && !C_COMMON_CLK) begin : async_coll + + // Delay A and B addresses in order to mimic setup/hold times + wire [C_ADDRA_WIDTH-1:0] #COLL_DELAY addra_delay = ADDRA; + wire [0:0] #COLL_DELAY wea_delay = wea_i; + wire #COLL_DELAY ena_delay = ena_i; + wire [C_ADDRB_WIDTH-1:0] #COLL_DELAY addrb_delay = ADDRB; + wire [0:0] #COLL_DELAY web_delay = web_i; + wire #COLL_DELAY enb_delay = enb_i; + + // Do the checks w/rt A + always @(posedge CLKA) begin + // Possible collision if both are enabled and the addresses match + if (ena_i && enb_i) begin + if (wea_i || web_i) begin + is_collision_a <= collision_check(ADDRA, wea_i, ADDRB, web_i); + end else begin + is_collision_a <= 0; + end + end else begin + is_collision_a <= 0; + end + + if (ena_i && enb_delay) begin + if(wea_i || web_delay) begin + is_collision_delay_a <= collision_check(ADDRA, wea_i, addrb_delay, + web_delay); + end else begin + is_collision_delay_a <= 0; + end + end else begin + is_collision_delay_a <= 0; + end + + + // Only flag if B access is a write + if (is_collision_a && web_i) begin + $fwrite(COLLFILE, "%0s collision detected at time: %0d, ", + C_CORENAME, $time); + $fwrite(COLLFILE, "A %0s address: %0h, B write address: %0h\n", + wea_i ? "write" : "read", ADDRA, ADDRB); + + end else if (is_collision_delay_a && web_delay) begin + $fwrite(COLLFILE, "%0s collision detected at time: %0d, ", + C_CORENAME, $time); + $fwrite(COLLFILE, "A %0s address: %0h, B write address: %0h\n", + wea_i ? "write" : "read", ADDRA, addrb_delay); + end + + end + + // Do the checks w/rt B + always @(posedge CLKB) begin + + // Possible collision if both are enabled and the addresses match + if (ena_i && enb_i) begin + if (wea_i || web_i) begin + is_collision_b <= collision_check(ADDRA, wea_i, ADDRB, web_i); + end else begin + is_collision_b <= 0; + end + end else begin + is_collision_b <= 0; + end + + if (ena_delay && enb_i) begin + if (wea_delay || web_i) begin + is_collision_delay_b <= collision_check(addra_delay, wea_delay, ADDRB, + web_i); + end else begin + is_collision_delay_b <= 0; + end + end else begin + is_collision_delay_b <= 0; + end + + + // Only flag if A access is a write + if (is_collision_b && wea_i) begin + $fwrite(COLLFILE, "%0s collision detected at time: %0d, ", + C_CORENAME, $time); + $fwrite(COLLFILE, "A write address: %0h, B %s address: %0h\n", + ADDRA, web_i ? "write" : "read", ADDRB); + + end else if (is_collision_delay_b && wea_delay) begin + $fwrite(COLLFILE, "%0s collision detected at time: %0d, ", + C_CORENAME, $time); + $fwrite(COLLFILE, "A write address: %0h, B %s address: %0h\n", + addra_delay, web_i ? "write" : "read", ADDRB); + end + + end + end + endgenerate + +endmodule +//***************************************************************************** +// Top module wraps Input register and Memory module +// +// This module is the top-level behavioral model and this implements the memory +// module and the input registers +//***************************************************************************** +module BLK_MEM_GEN_V4_2 + #(parameter C_CORENAME = "blk_mem_gen_v4_2", + parameter C_FAMILY = "virtex6", + parameter C_XDEVICEFAMILY = "virtex6", + parameter C_MEM_TYPE = 2, + parameter C_BYTE_SIZE = 9, + parameter C_ALGORITHM = 1, + parameter C_PRIM_TYPE = 3, + parameter C_LOAD_INIT_FILE = 0, + parameter C_INIT_FILE_NAME = "", + parameter C_USE_DEFAULT_DATA = 0, + parameter C_DEFAULT_DATA = "0", + parameter C_RST_TYPE = "SYNC", + parameter C_HAS_RSTA = 0, + parameter C_RST_PRIORITY_A = "CE", + parameter C_RSTRAM_A = 0, + parameter C_INITA_VAL = "0", + parameter C_HAS_ENA = 1, + parameter C_HAS_REGCEA = 0, + parameter C_USE_BYTE_WEA = 0, + parameter C_WEA_WIDTH = 1, + parameter C_WRITE_MODE_A = "WRITE_FIRST", + parameter C_WRITE_WIDTH_A = 32, + parameter C_READ_WIDTH_A = 32, + parameter C_WRITE_DEPTH_A = 64, + parameter C_READ_DEPTH_A = 64, + parameter C_ADDRA_WIDTH = 5, + parameter C_HAS_RSTB = 0, + parameter C_RST_PRIORITY_B = "CE", + parameter C_RSTRAM_B = 0, + parameter C_INITB_VAL = "0", + parameter C_HAS_ENB = 1, + parameter C_HAS_REGCEB = 0, + parameter C_USE_BYTE_WEB = 0, + parameter C_WEB_WIDTH = 1, + parameter C_WRITE_MODE_B = "WRITE_FIRST", + parameter C_WRITE_WIDTH_B = 32, + parameter C_READ_WIDTH_B = 32, + parameter C_WRITE_DEPTH_B = 64, + parameter C_READ_DEPTH_B = 64, + parameter C_ADDRB_WIDTH = 5, + parameter C_HAS_MEM_OUTPUT_REGS_A = 0, + parameter C_HAS_MEM_OUTPUT_REGS_B = 0, + parameter C_HAS_MUX_OUTPUT_REGS_A = 0, + parameter C_HAS_MUX_OUTPUT_REGS_B = 0, + parameter C_HAS_SOFTECC_INPUT_REGS_A = 0, + parameter C_HAS_SOFTECC_OUTPUT_REGS_B= 0, + parameter C_MUX_PIPELINE_STAGES = 0, + parameter C_USE_SOFTECC = 0, + parameter C_USE_ECC = 0, + parameter C_HAS_INJECTERR = 0, + parameter C_SIM_COLLISION_CHECK = "NONE", + parameter C_COMMON_CLK = 1, + parameter C_DISABLE_WARN_BHV_COLL = 0, + parameter C_DISABLE_WARN_BHV_RANGE = 0 + ) + (input CLKA, + input RSTA, + input ENA, + input REGCEA, + input [C_WEA_WIDTH-1:0] WEA, + input [C_ADDRA_WIDTH-1:0] ADDRA, + input [C_WRITE_WIDTH_A-1:0] DINA, + output [C_READ_WIDTH_A-1:0] DOUTA, + input CLKB, + input RSTB, + input ENB, + input REGCEB, + input [C_WEB_WIDTH-1:0] WEB, + input [C_ADDRB_WIDTH-1:0] ADDRB, + input [C_WRITE_WIDTH_B-1:0] DINB, + output [C_READ_WIDTH_B-1:0] DOUTB, + input INJECTSBITERR, + input INJECTDBITERR, + output SBITERR, + output DBITERR, + output [C_ADDRB_WIDTH-1:0] RDADDRECC + ); +//****************************** +// Port and Generic Definitions +//****************************** + //------------------------------------------------------------------------- + // Generic Definitions + //------------------------------------------------------------------------- + // C_CORENAME : Instance name of the Block Memory Generator core + // C_FAMILY,C_XDEVICEFAMILY: Designates architecture targeted. The following + // options are available - "spartan3", "spartan6", + // "virtex4", "virtex5", "virtex6" and "virtex6l". + // C_MEM_TYPE : Designates memory type. + // It can be + // 0 - Single Port Memory + // 1 - Simple Dual Port Memory + // 2 - True Dual Port Memory + // 3 - Single Port Read Only Memory + // 4 - Dual Port Read Only Memory + // C_BYTE_SIZE : Size of a byte (8 or 9 bits) + // C_ALGORITHM : Designates the algorithm method used + // for constructing the memory. + // It can be Fixed_Primitives, Minimum_Area or + // Low_Power + // C_PRIM_TYPE : Designates the user selected primitive used to + // construct the memory. + // + // C_LOAD_INIT_FILE : Designates the use of an initialization file to + // initialize memory contents. + // C_INIT_FILE_NAME : Memory initialization file name. + // C_USE_DEFAULT_DATA : Designates whether to fill remaining + // initialization space with default data + // C_DEFAULT_DATA : Default value of all memory locations + // not initialized by the memory + // initialization file. + // C_RST_TYPE : Type of reset - Synchronous or Asynchronous + // C_HAS_RSTA : Determines the presence of the RSTA port + // C_RST_PRIORITY_A : Determines the priority between CE and SR for + // Port A. + // C_RSTRAM_A : Determines if special reset behavior is used for + // Port A + // C_INITA_VAL : The initialization value for Port A + // C_HAS_ENA : Determines the presence of the ENA port + // C_HAS_REGCEA : Determines the presence of the REGCEA port + // C_USE_BYTE_WEA : Determines if the Byte Write is used or not. + // C_WEA_WIDTH : The width of the WEA port + // C_WRITE_MODE_A : Configurable write mode for Port A. It can be + // WRITE_FIRST, READ_FIRST or NO_CHANGE. + // C_WRITE_WIDTH_A : Memory write width for Port A. + // C_READ_WIDTH_A : Memory read width for Port A. + // C_WRITE_DEPTH_A : Memory write depth for Port A. + // C_READ_DEPTH_A : Memory read depth for Port A. + // C_ADDRA_WIDTH : Width of the ADDRA input port + // C_HAS_RSTB : Determines the presence of the RSTB port + // C_RST_PRIORITY_B : Determines the priority between CE and SR for + // Port B. + // C_RSTRAM_B : Determines if special reset behavior is used for + // Port B + // C_INITB_VAL : The initialization value for Port B + // C_HAS_ENB : Determines the presence of the ENB port + // C_HAS_REGCEB : Determines the presence of the REGCEB port + // C_USE_BYTE_WEB : Determines if the Byte Write is used or not. + // C_WEB_WIDTH : The width of the WEB port + // C_WRITE_MODE_B : Configurable write mode for Port B. It can be + // WRITE_FIRST, READ_FIRST or NO_CHANGE. + // C_WRITE_WIDTH_B : Memory write width for Port B. + // C_READ_WIDTH_B : Memory read width for Port B. + // C_WRITE_DEPTH_B : Memory write depth for Port B. + // C_READ_DEPTH_B : Memory read depth for Port B. + // C_ADDRB_WIDTH : Width of the ADDRB input port + // C_HAS_MEM_OUTPUT_REGS_A : Designates the use of a register at the output + // of the RAM primitive for Port A. + // C_HAS_MEM_OUTPUT_REGS_B : Designates the use of a register at the output + // of the RAM primitive for Port B. + // C_HAS_MUX_OUTPUT_REGS_A : Designates the use of a register at the output + // of the MUX for Port A. + // C_HAS_MUX_OUTPUT_REGS_B : Designates the use of a register at the output + // of the MUX for Port B. + // C_HAS_SOFTECC_INPUT_REGS_A : + // C_HAS_SOFTECC_OUTPUT_REGS_B : + // C_MUX_PIPELINE_STAGES : Designates the number of pipeline stages in + // between the muxes. + // C_USE_SOFTECC : Determines if the Soft ECC feature is used or + // not. Only applicable Spartan-6 + // C_USE_ECC : Determines if the ECC feature is used or + // not. Only applicable for V5 and V6 + // C_HAS_INJECTERR : Determines if the error injection pins + // are present or not. If the ECC feature + // is not used, this value is defaulted to + // 0, else the following are the allowed + // values: + // 0 : No INJECTSBITERR or INJECTDBITERR pins + // 1 : Only INJECTSBITERR pin exists + // 2 : Only INJECTDBITERR pin exists + // 3 : Both INJECTSBITERR and INJECTDBITERR pins exist + // C_SIM_COLLISION_CHECK : Controls the disabling of Unisim model collision + // warnings. It can be "ALL", "NONE", + // "Warnings_Only" or "Generate_X_Only". + // C_COMMON_CLK : Determins if the core has a single CLK input. + // C_DISABLE_WARN_BHV_COLL : Controls the Behavioral Model Collision warnings + // C_DISABLE_WARN_BHV_RANGE: Controls the Behavioral Model Out of Range + // warnings + //------------------------------------------------------------------------- + // Port Definitions + //------------------------------------------------------------------------- + // CLKA : Clock to synchronize all read and write operations of Port A. + // RSTA : Reset input to reset memory outputs to a user-defined + // reset state for Port A. + // ENA : Enable all read and write operations of Port A. + // REGCEA : Register Clock Enable to control each pipeline output + // register stages for Port A. + // WEA : Write Enable to enable all write operations of Port A. + // ADDRA : Address of Port A. + // DINA : Data input of Port A. + // DOUTA : Data output of Port A. + // CLKB : Clock to synchronize all read and write operations of Port B. + // RSTB : Reset input to reset memory outputs to a user-defined + // reset state for Port B. + // ENB : Enable all read and write operations of Port B. + // REGCEB : Register Clock Enable to control each pipeline output + // register stages for Port B. + // WEB : Write Enable to enable all write operations of Port B. + // ADDRB : Address of Port B. + // DINB : Data input of Port B. + // DOUTB : Data output of Port B. + // INJECTSBITERR : Single Bit ECC Error Injection Pin. + // INJECTDBITERR : Double Bit ECC Error Injection Pin. + // SBITERR : Output signal indicating that a Single Bit ECC Error has been + // detected and corrected. + // DBITERR : Output signal indicating that a Double Bit ECC Error has been + // detected. + // RDADDRECC : Read Address Output signal indicating address at which an + // ECC error has occurred. + //------------------------------------------------------------------------- + + localparam FLOP_DELAY = 100; // 100 ps + + reg injectsbiterr_in; + reg injectdbiterr_in; + reg rsta_in; + reg ena_in; + reg regcea_in; + reg [C_WEA_WIDTH-1:0] wea_in; + reg [C_ADDRA_WIDTH-1:0] addra_in; + reg [C_WRITE_WIDTH_A-1:0] dina_in; + //*********************************************** + // INPUT REGISTERS. + //*********************************************** + generate if (C_HAS_SOFTECC_INPUT_REGS_A==0) begin : no_softecc_input_reg_stage + always @* begin + injectsbiterr_in = INJECTSBITERR; + injectdbiterr_in = INJECTDBITERR; + rsta_in = RSTA; + ena_in = ENA; + regcea_in = REGCEA; + wea_in = WEA; + addra_in = ADDRA; + dina_in = DINA; + end //end always + end //end no_softecc_input_reg_stage + endgenerate + + generate if (C_HAS_SOFTECC_INPUT_REGS_A==1) begin : has_softecc_input_reg_stage + always @(posedge CLKA) begin + injectsbiterr_in <= #FLOP_DELAY INJECTSBITERR; + injectdbiterr_in <= #FLOP_DELAY INJECTDBITERR; + rsta_in <= #FLOP_DELAY RSTA; + ena_in <= #FLOP_DELAY ENA; + regcea_in <= #FLOP_DELAY REGCEA; + wea_in <= #FLOP_DELAY WEA; + addra_in <= #FLOP_DELAY ADDRA; + dina_in <= #FLOP_DELAY DINA; + end //end always + end //end input_reg_stages generate statement + endgenerate + +BLK_MEM_GEN_V4_2_mem_module + #(.C_CORENAME (C_CORENAME), + .C_FAMILY (C_FAMILY), + .C_XDEVICEFAMILY (C_XDEVICEFAMILY), + .C_MEM_TYPE (C_MEM_TYPE), + .C_BYTE_SIZE (C_BYTE_SIZE), + .C_ALGORITHM (C_ALGORITHM), + .C_PRIM_TYPE (C_PRIM_TYPE), + .C_LOAD_INIT_FILE (C_LOAD_INIT_FILE), + .C_INIT_FILE_NAME (C_INIT_FILE_NAME), + .C_USE_DEFAULT_DATA (C_USE_DEFAULT_DATA), + .C_DEFAULT_DATA (C_DEFAULT_DATA), + .C_RST_TYPE (C_RST_TYPE), + .C_HAS_RSTA (C_HAS_RSTA), + .C_RST_PRIORITY_A (C_RST_PRIORITY_A), + .C_RSTRAM_A (C_RSTRAM_A), + .C_INITA_VAL (C_INITA_VAL), + .C_HAS_ENA (C_HAS_ENA), + .C_HAS_REGCEA (C_HAS_REGCEA), + .C_USE_BYTE_WEA (C_USE_BYTE_WEA), + .C_WEA_WIDTH (C_WEA_WIDTH), + .C_WRITE_MODE_A (C_WRITE_MODE_A), + .C_WRITE_WIDTH_A (C_WRITE_WIDTH_A), + .C_READ_WIDTH_A (C_READ_WIDTH_A), + .C_WRITE_DEPTH_A (C_WRITE_DEPTH_A), + .C_READ_DEPTH_A (C_READ_DEPTH_A), + .C_ADDRA_WIDTH (C_ADDRA_WIDTH), + .C_HAS_RSTB (C_HAS_RSTB), + .C_RST_PRIORITY_B (C_RST_PRIORITY_B), + .C_RSTRAM_B (C_RSTRAM_B), + .C_INITB_VAL (C_INITB_VAL), + .C_HAS_ENB (C_HAS_ENB), + .C_HAS_REGCEB (C_HAS_REGCEB), + .C_USE_BYTE_WEB (C_USE_BYTE_WEB), + .C_WEB_WIDTH (C_WEB_WIDTH), + .C_WRITE_MODE_B (C_WRITE_MODE_B), + .C_WRITE_WIDTH_B (C_WRITE_WIDTH_B), + .C_READ_WIDTH_B (C_READ_WIDTH_B), + .C_WRITE_DEPTH_B (C_WRITE_DEPTH_B), + .C_READ_DEPTH_B (C_READ_DEPTH_B), + .C_ADDRB_WIDTH (C_ADDRB_WIDTH), + .C_HAS_MEM_OUTPUT_REGS_A (C_HAS_MEM_OUTPUT_REGS_A), + .C_HAS_MEM_OUTPUT_REGS_B (C_HAS_MEM_OUTPUT_REGS_B), + .C_HAS_MUX_OUTPUT_REGS_A (C_HAS_MUX_OUTPUT_REGS_A), + .C_HAS_MUX_OUTPUT_REGS_B (C_HAS_MUX_OUTPUT_REGS_B), + .C_HAS_SOFTECC_INPUT_REGS_A (C_HAS_SOFTECC_INPUT_REGS_A), + .C_HAS_SOFTECC_OUTPUT_REGS_B (C_HAS_SOFTECC_OUTPUT_REGS_B), + .C_MUX_PIPELINE_STAGES (C_MUX_PIPELINE_STAGES), + .C_USE_SOFTECC (C_USE_SOFTECC), + .C_USE_ECC (C_USE_ECC), + .C_HAS_INJECTERR (C_HAS_INJECTERR), + .C_SIM_COLLISION_CHECK (C_SIM_COLLISION_CHECK), + .C_COMMON_CLK (C_COMMON_CLK), + .FLOP_DELAY (FLOP_DELAY), + .C_DISABLE_WARN_BHV_COLL (C_DISABLE_WARN_BHV_COLL), + .C_DISABLE_WARN_BHV_RANGE (C_DISABLE_WARN_BHV_RANGE)) + blk_mem_gen_v4_2_inst + (.CLKA (CLKA), + .RSTA (rsta_in), + .ENA (ena_in), + .REGCEA (regcea_in), + .WEA (wea_in), + .ADDRA (addra_in), + .DINA (dina_in), + .DOUTA (DOUTA), + .CLKB (CLKB), + .RSTB (RSTB), + .ENB (ENB), + .REGCEB (REGCEB), + .WEB (WEB), + .ADDRB (ADDRB), + .DINB (DINB), + .DOUTB (DOUTB), + .INJECTSBITERR (injectsbiterr_in), + .INJECTDBITERR (injectdbiterr_in), + .SBITERR (SBITERR), + .DBITERR (DBITERR), + .RDADDRECC (RDADDRECC) + ); +endmodule diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/BLK_MEM_GEN_V4_2_xst.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/BLK_MEM_GEN_V4_2_xst.v new file mode 100644 index 0000000..a5842ed --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/BLK_MEM_GEN_V4_2_xst.v @@ -0,0 +1,234 @@ +/****************************************************************************** +-- (c) Copyright 2006 - 2009 Xilinx, Inc. All rights reserved. +-- +-- This file contains confidential and proprietary information +-- of Xilinx, Inc. and is protected under U.S. and +-- international copyright and other intellectual property +-- laws. +-- +-- DISCLAIMER +-- This disclaimer is not a license and does not grant any +-- rights to the materials distributed herewith. Except as +-- otherwise provided in a valid license issued to you by +-- Xilinx, and to the maximum extent permitted by applicable +-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +-- (2) Xilinx shall not be liable (whether in contract or tort, +-- including negligence, or under any other theory of +-- liability) for any loss or damage of any kind or nature +-- related to, arising under or in connection with these +-- materials, including for any direct, or any indirect, +-- special, incidental, or consequential loss or damage +-- (including loss of data, profits, goodwill, or any type of +-- loss or damage suffered as a result of any action brought +-- by a third party) even if such damage or loss was +-- reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail- +-- safe, or for use in any application requiring fail-safe +-- performance, such as life-support or safety devices or +-- systems, Class III medical devices, nuclear facilities, +-- applications related to the deployment of airbags, or any +-- other applications that could lead to death, personal +-- injury, or severe property or environmental damage +-- (individually and collectively, "Critical +-- Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical +-- Applications, subject only to applicable laws and +-- regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +-- PART OF THIS FILE AT ALL TIMES. +-- + ***************************************************************************** + * + * Filename: BLK_MEM_GEN_V4_2.v + * + * Description: + * This file is the Verilog behvarial model for the + * Block Memory Generator Core. + * + ***************************************************************************** + * Author: Xilinx + * + * History: September 6, 2005 Initial revision + *****************************************************************************/ +`timescale 1ps/1ps + +module BLK_MEM_GEN_V4_2_xst + #(parameter C_FAMILY = "virtex5", + parameter C_XDEVICEFAMILY = "virtex5", + parameter C_ELABORATION_DIR = "", + parameter C_MEM_TYPE = 2, + parameter C_BYTE_SIZE = 9, + parameter C_ALGORITHM = 1, + parameter C_PRIM_TYPE = 3, + parameter C_LOAD_INIT_FILE = 0, + parameter C_INIT_FILE_NAME = "", + parameter C_USE_DEFAULT_DATA = 0, + parameter C_DEFAULT_DATA = "0", + parameter C_RST_TYPE = "SYNC", + parameter C_HAS_RSTA = 0, + parameter C_RST_PRIORITY_A = "CE", + parameter C_RSTRAM_A = 0, + parameter C_INITA_VAL = "0", + parameter C_HAS_ENA = 1, + parameter C_HAS_REGCEA = 0, + parameter C_USE_BYTE_WEA = 0, + parameter C_WEA_WIDTH = 1, + parameter C_WRITE_MODE_A = "WRITE_FIRST", + parameter C_WRITE_WIDTH_A = 32, + parameter C_READ_WIDTH_A = 32, + parameter C_WRITE_DEPTH_A = 64, + parameter C_READ_DEPTH_A = 64, + parameter C_ADDRA_WIDTH = 5, + parameter C_HAS_RSTB = 0, + parameter C_RST_PRIORITY_B = "CE", + parameter C_RSTRAM_B = 0, + parameter C_INITB_VAL = "0", + parameter C_HAS_ENB = 1, + parameter C_HAS_REGCEB = 0, + parameter C_USE_BYTE_WEB = 0, + parameter C_WEB_WIDTH = 1, + parameter C_WRITE_MODE_B = "WRITE_FIRST", + parameter C_WRITE_WIDTH_B = 32, + parameter C_READ_WIDTH_B = 32, + parameter C_WRITE_DEPTH_B = 64, + parameter C_READ_DEPTH_B = 64, + parameter C_ADDRB_WIDTH = 5, + parameter C_HAS_MEM_OUTPUT_REGS_A = 0, + parameter C_HAS_MEM_OUTPUT_REGS_B = 0, + parameter C_HAS_MUX_OUTPUT_REGS_A = 0, + parameter C_HAS_MUX_OUTPUT_REGS_B = 0, + parameter C_HAS_SOFTECC_INPUT_REGS_A = 0, + parameter C_HAS_SOFTECC_OUTPUT_REGS_B= 0, + parameter C_MUX_PIPELINE_STAGES = 0, + parameter C_USE_SOFTECC = 0, + parameter C_USE_ECC = 0, + parameter C_HAS_INJECTERR = 0, + parameter C_SIM_COLLISION_CHECK = "NONE", + parameter C_COMMON_CLK = 1, + parameter C_DISABLE_WARN_BHV_COLL = 0, + parameter C_DISABLE_WARN_BHV_RANGE = 0 +) + (input CLKA, + input RSTA, + input ENA, + input REGCEA, + input [C_WEA_WIDTH-1:0] WEA, + input [C_ADDRA_WIDTH-1:0] ADDRA, + input [C_WRITE_WIDTH_A-1:0] DINA, + output [C_READ_WIDTH_A-1:0] DOUTA, + input CLKB, + input RSTB, + input ENB, + input REGCEB, + input [C_WEB_WIDTH-1:0] WEB, + input [C_ADDRB_WIDTH-1:0] ADDRB, + input [C_WRITE_WIDTH_B-1:0] DINB, + output [C_READ_WIDTH_B-1:0] DOUTB, + input INJECTSBITERR, + input INJECTDBITERR, + output SBITERR, + output DBITERR, + output [C_ADDRB_WIDTH-1:0] RDADDRECC +); + + +// Note: C_ELABORATION_DIR parameter is only used in synthesis +// (and doesn't get mentioned in the instantiation template Coregen generates). +// This wrapper file has to work both in simulation and synthesis. So, this +// parameter exists. It is not used by the behavioral model +// (BLK_MEM_GEN_V4_2.vhd) + + localparam C_FAMILY_LOCALPARAM = (C_FAMILY=="virtex6l" ? "virtex6" : (C_FAMILY=="spartan6l" ? "spartan6" : (C_FAMILY=="aspartan6" ? "spartan6" : C_FAMILY))); + + BLK_MEM_GEN_V4_2 + #( + .C_CORENAME ("blk_mem_gen_v4_2"), +// .C_FAMILY (C_FAMILY), +// .C_FAMILY (C_FAMILY=="virtex6l" ? virtex6 : (C_FAMILY=="spartan6l" ? spartan6 : (C_FAMILY=="aspartan6" ? spartan6 : C_FAMILY))), + .C_FAMILY (C_FAMILY_LOCALPARAM), + .C_XDEVICEFAMILY (C_XDEVICEFAMILY), + .C_MEM_TYPE (C_MEM_TYPE), + .C_BYTE_SIZE (C_BYTE_SIZE), + .C_ALGORITHM (C_ALGORITHM), + .C_PRIM_TYPE (C_PRIM_TYPE), + .C_LOAD_INIT_FILE (C_LOAD_INIT_FILE), + .C_INIT_FILE_NAME (C_INIT_FILE_NAME), + .C_USE_DEFAULT_DATA (C_USE_DEFAULT_DATA), + .C_DEFAULT_DATA (C_DEFAULT_DATA), + .C_RST_TYPE (C_RST_TYPE), + .C_HAS_RSTA (C_HAS_RSTA), + .C_RST_PRIORITY_A (C_RST_PRIORITY_A), + .C_RSTRAM_A (C_RSTRAM_A), + .C_INITA_VAL (C_INITA_VAL), + .C_HAS_ENA (C_HAS_ENA), + .C_HAS_REGCEA (C_HAS_REGCEA), + .C_USE_BYTE_WEA (C_USE_BYTE_WEA), + .C_WEA_WIDTH (C_WEA_WIDTH), + .C_WRITE_MODE_A (C_WRITE_MODE_A), + .C_WRITE_WIDTH_A (C_WRITE_WIDTH_A), + .C_READ_WIDTH_A (C_READ_WIDTH_A), + .C_WRITE_DEPTH_A (C_WRITE_DEPTH_A), + .C_READ_DEPTH_A (C_READ_DEPTH_A), + .C_ADDRA_WIDTH (C_ADDRA_WIDTH), + .C_HAS_RSTB (C_HAS_RSTB), + .C_RST_PRIORITY_B (C_RST_PRIORITY_B), + .C_RSTRAM_B (C_RSTRAM_B), + .C_INITB_VAL (C_INITB_VAL), + .C_HAS_ENB (C_HAS_ENB), + .C_HAS_REGCEB (C_HAS_REGCEB), + .C_USE_BYTE_WEB (C_USE_BYTE_WEB), + .C_WEB_WIDTH (C_WEB_WIDTH), + .C_WRITE_MODE_B (C_WRITE_MODE_B), + .C_WRITE_WIDTH_B (C_WRITE_WIDTH_B), + .C_READ_WIDTH_B (C_READ_WIDTH_B), + .C_WRITE_DEPTH_B (C_WRITE_DEPTH_B), + .C_READ_DEPTH_B (C_READ_DEPTH_B), + .C_ADDRB_WIDTH (C_ADDRB_WIDTH), + .C_HAS_MEM_OUTPUT_REGS_A (C_HAS_MEM_OUTPUT_REGS_A), + .C_HAS_MEM_OUTPUT_REGS_B (C_HAS_MEM_OUTPUT_REGS_B), + .C_HAS_MUX_OUTPUT_REGS_A (C_HAS_MUX_OUTPUT_REGS_A), + .C_HAS_MUX_OUTPUT_REGS_B (C_HAS_MUX_OUTPUT_REGS_B), + .C_HAS_SOFTECC_INPUT_REGS_A (C_HAS_SOFTECC_INPUT_REGS_A), + .C_HAS_SOFTECC_OUTPUT_REGS_B (C_HAS_SOFTECC_OUTPUT_REGS_B), + .C_MUX_PIPELINE_STAGES (C_MUX_PIPELINE_STAGES), + .C_USE_SOFTECC (C_USE_SOFTECC), + .C_USE_ECC (C_USE_ECC), + .C_HAS_INJECTERR (C_HAS_INJECTERR), + .C_SIM_COLLISION_CHECK (C_SIM_COLLISION_CHECK), + .C_COMMON_CLK (C_COMMON_CLK), + .C_DISABLE_WARN_BHV_COLL (C_DISABLE_WARN_BHV_COLL), + .C_DISABLE_WARN_BHV_RANGE (C_DISABLE_WARN_BHV_RANGE) + ) blk_mem_gen_v4_2_dut ( + .CLKA (CLKA), + .RSTA (RSTA), + .ENA (ENA), + .REGCEA (REGCEA), + .WEA (WEA), + .ADDRA (ADDRA), + .DINA (DINA), + .DOUTA (DOUTA), + .CLKB (CLKB), + .RSTB (RSTB), + .ENB (ENB), + .REGCEB (REGCEB), + .WEB (WEB), + .ADDRB (ADDRB), + .DINB (DINB), + .DOUTB (DOUTB), + .INJECTSBITERR (INJECTSBITERR), + .INJECTDBITERR (INJECTDBITERR), + .SBITERR (SBITERR), + .DBITERR (DBITERR), + .RDADDRECC (RDADDRECC) +); + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/CAM_V5_0.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/CAM_V5_0.v new file mode 100644 index 0000000..f4e2b8c --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/CAM_V5_0.v @@ -0,0 +1,1221 @@ +/**************************************************************************** + * $RCSfile: CAM_V5_0.v,v $ $Revision: 1.12 $ $Date: 2008/09/08 20:07:00 $ + * ************************************************************************** + * + * Content Addressable Memory - Verilog Behavioral Model + * + * Filename: CAM_V5_0.v + * + * Description: + * The behavioral model for the Content Addressable Memory core + * + * *************************************************************************/ + +// Copyright(C) 2004 by Xilinx, Inc. All rights reserved. +// This text/file contains proprietary, confidential +// information of Xilinx, Inc., is distributed under license +// from Xilinx, Inc., and may be used, copied and/or +// disclosed only pursuant to the terms of a valid license +// agreement with Xilinx, Inc. Xilinx hereby grants you +// a license to use this text/file solely for design, simulation, +// implementation and creation of design files limited +// to Xilinx devices or technologies. Use with non-Xilinx +// devices or technologies is expressly prohibited and +// immediately terminates your license unless covered by +// a separate agreement. +// +// Xilinx is providing this design, code, or information +// "as is" solely for use in developing programs and +// solutions for Xilinx devices. By providing this design, +// code, or information as one possible implementation of +// this feature, application or standard, Xilinx is making no +// representation that this implementation is free from any +// claims of infringement. You are responsible for +// obtaining any rights you may require for your implementation. +// Xilinx expressly disclaims any warranty whatsoever with +// respect to the adequacy of the implementation, including +// but not limited to any warranties or representations that this +// implementation is free from claims of infringement, implied +// warranties of merchantability or fitness for a particular +// purpose. +// +// Xilinx products are not intended for use in life support +// appliances, devices, or systems. Use in such applications are +// expressly prohibited. +// +// This copyright and support notice must be retained as part +// of this text at all times. (c) Copyright 1995-2004 Xilinx, Inc. +// All rights reserved. + + + /************************************************************************* + * Set the timescale value for this core + *************************************************************************/ +`timescale 1ns/10ps + + + /************************************************************************* + * Declare top-level module + *************************************************************************/ +module CAM_V5_0 + ( + CLK, + CMP_DATA_MASK, + CMP_DIN, + DATA_MASK, + DIN, + EN, + WE, + WR_ADDR, + BUSY, + MATCH, + MATCH_ADDR, + MULTIPLE_MATCH, + READ_WARNING, + SINGLE_MATCH + ); + + +/************************************************************************* + * Parameter Declarations (external) + *************************************************************************/ +parameter c_addr_type = 2; +parameter c_cmp_data_mask_width = 4; +parameter c_cmp_din_width = 4; +parameter c_data_mask_width = 4; +parameter c_depth = 16; +parameter c_din_width = 4; +parameter c_enable_rlocs = 0; +//parameter c_family = ""; +parameter c_has_cmp_data_mask = 0; +parameter c_has_cmp_din = 0; +parameter c_has_data_mask = 0; +parameter c_has_en = 0; +parameter c_has_multiple_match = 0; +parameter c_has_read_warning = 0; +parameter c_has_single_match = 0; +parameter c_has_we = 1; +parameter c_has_wr_addr = 1; +parameter c_match_addr_width = 16; +parameter c_match_resolution_type = 0; +parameter c_mem_init = 0; +parameter c_mem_init_file = ""; +parameter c_mem_type = 0; +parameter c_read_cycles = 1; +parameter c_reg_outputs = 0; +parameter c_ternary_mode = 0; +parameter c_width = 1; +parameter c_wr_addr_width = 4; + + +/**************************************************************************** + * Definition of Generics: + **************************************************************************** + * c_addr_type : Determines format of MATCH_ADDR output + * 0 = Binary Encoded + * 1 = Single Match Unencoded (one*hot) + * 2 = Multi*match unencoded (shows all matches) + * c_cmp_data_mask_width : Width of the cmp_data_mask port + * (should be the same as c_width) + * c_cmp_din_width : Width of the cmp_din port + * (should be the same as c_width) + * c_data_mask_width : Width of the data_mask port + * (should be the same as c_width) + * c_depth : Depth of the CAM + * (Must be > 2) + * c_din_width : Width of the din port + * (should be the same as c_width) + * c_enable_rlocs : Enable placement directives? + * 0 = Placement disabled + * 1 = Placement enabled + * c_family : Architecture (not used in behavioral model) + * c_has_cmp_data_mask : 1 if cmp_data_mask input port present + * c_has_cmp_din : 1 if cmp_din input port present + * c_has_data_mask : 1 if data_mask input port present + * c_has_en : 1 if en input port present + * c_has_multiple_match : 1 if multiple_match output port present + * c_has_read_warning : 1 if read_warning output port present + * c_has_single_match : 1 if single_match output port present + * c_has_we : 1 if we input port present + * c_has_wr_addr : 1 if wr_addr input port present + * c_match_addr_width : Width of the match_addr port + * log2roundup(c_depth) if c_addr_type=0 + * c_depth if c_addr_type = 1 or 2 + * c_match_resolution_type : When c_addr_type=0 or 1, only one match can + * be output. + * 0 = Output lowest matching address + * 1 = Output highest matching address + * c_mem_init : 0 = Do not initialize CAM + * 1 = Initialize CAM + * c_mem_init_file : Filename of .mif file for initializing CAM + * c_mem_type : 0 = SRL16E implementation + * 1 = Block Memory implementation + * c_read_cycles : Always fixed as 1 in CAM version 3.0 + * c_reg_outputs : For use with Block Memory ONLY. + * 0 = Do not add extra output registers. + * 1 = Add output registers + * c_ternary_mode : 0 = Binary CAM + * 1 = Ternary CAM (can store X's) + * c_width : Data Width of the CAM + * c_wr_addr_width : Width of wr_addr port = log2roundup(c_depth) + ***************************************************************************/ + + + +/************************************************************************* + * Input and Output Declarations + *************************************************************************/ +input CLK; +input [c_cmp_data_mask_width-1:0] CMP_DATA_MASK; +input [c_cmp_din_width-1:0] CMP_DIN; +input [c_data_mask_width-1:0] DATA_MASK; +input [c_din_width-1:0] DIN; +input EN; +input WE; +input [c_wr_addr_width-1:0] WR_ADDR; +output BUSY; +output MATCH; +output [c_match_addr_width-1:0] MATCH_ADDR; +output MULTIPLE_MATCH; +output READ_WARNING; +output SINGLE_MATCH; + +reg MATCH; +reg [c_match_addr_width-1:0] MATCH_ADDR; +reg MULTIPLE_MATCH; +reg READ_WARNING; +reg SINGLE_MATCH; + +/**************************************************************************** + * Definition of Ports + **************************************************************************** + * CLK : IN : Clock + * CMP_DATA_MASK : IN : Data mask for CMP_DIN port + * CMP_DIN : IN : Compare port - Data input (CAM read/search operation) + * DATA_MASK : IN : Data mask for DIN port + * DIN : IN : Data input (CAM Write operation, and CAM read/search) + * EN : IN : CAM enable (active high) + * WE : IN : CAM write enable (active high) + * WR_ADDR : IN : CAM write address + * BUSY : OUT : High state indicates that user can not start a new + * write operation + * MATCH : OUT : High state indicates one or more matches found + * MATCH_ADDR : OUT : Address (or addresses) of matches found (if any) + * MULTIPLE_MATCH : OUT : High state indicates MORE than one match found + * READ_WARNING : OUT : High state indicates that the match operation may + * have returned misleading results because the data + * was being modified by a simultanous write operation + * SINGLE_MATCH : OUT : High state indicates ONLY one match found + ***************************************************************************/ + + + +/************************************************************************* + * Internal wires and regs for each port + *************************************************************************/ +wire [c_width-1:0] rd_din; +wire [c_width-1:0] rd_data_mask; +wire [c_width-1:0] data_mask_i; +wire [c_width-1:0] din_i; +wire en_i; +wire we_i; +wire [c_wr_addr_width-1:0] wr_addr_i; +reg busy_i; + + +/************************************************************************* + * registered copies of inputs + *************************************************************************/ +reg [c_width-1:0] data_mask_q; +reg [c_width-1:0] din_q; +reg [c_wr_addr_width-1:0] wr_addr_q; +//[c_width-1:0] wr_data_mask_q; +//[c_width-1:0] wr_din_q; + + +/************************************************************************* + * non-registered versions of output ports + *************************************************************************/ +reg match_i; +reg [c_match_addr_width-1:0] match_addr_i; +reg multiple_match_i; +reg read_warning_i; +reg single_match_i; + + +/************************************************************************* + * registered versions of output ports + *************************************************************************/ +reg match_q; +reg [c_match_addr_width-1:0] match_addr_q; +reg multiple_match_q; +reg read_warning_q; +reg single_match_q; + + +/************************************************************************* + * internal signals, not connected to ports + *************************************************************************/ +reg [c_wr_addr_width-1:0] wr_addr_int; +reg [c_width-1:0] wr_din; +reg [c_width-1:0] wr_data_mask; + +integer write_counter; +wire wren; + +reg RESET; + + +/************************************************************************* + * internal signals used in the match always block + *************************************************************************/ +reg [c_depth-1:0] m_match_addr_i; +integer m_matches; +integer i, j, initcntw, initcntd; +reg [c_depth-1:0] tmp_m_match_addr_i; + + +/************************************************************************* + * Data type for internal cam data storage + *************************************************************************/ +reg [c_width-1:0] cam_data[0:c_depth-1]; + +/************************************************************************* + * Data type for internal cam mask storage + *************************************************************************/ +reg [c_width-1:0] cam_mask[0:c_depth-1]; + +/************************************************************************* + * Data type for internal cam initialization + *************************************************************************/ +reg [c_width-1:0] cam_init[0:c_depth-1]; + +/************************************************************************* + * Initialzation value for cam_data and cam_mask elements + *************************************************************************/ +reg [c_width-1:0] init_word; +reg [c_width-1:0] data_word; +reg [c_width-1:0] mask_word; +reg [c_width-1:0] zees; +reg [c_width-1:0] zeros; + +/************************************************************************* + * Internal Constants + *************************************************************************/ + +parameter const_srl_mem = 0; //Constant for c_mem_type= SRL16 +parameter const_block_mem = 1; //Constant for c_mem_type= Block Memory +parameter const_dist_mem = 2; //Constant for c_mem_type= Distributed Memory + +parameter const_bin_encoded = 0; //Constant for c_addr_type= Binary Encoded +parameter const_sm_unencoded = 1; //Constant for c_addr_type= Single-Match Unencoded +parameter const_mm_unencoded = 2; //Constant for c_addr_type= Multiple-Match Unencoded + +parameter const_lowest_match = 0; //Constant for c_resolution_type= Lowest Match +parameter const_highest_match = 1; //Constant for c_resolution_type= Highest Match + +parameter const_ternary_off = 0; //Constant for c_ternary_mode = None +parameter const_ternary_std = 1; //Constant for c_ternary_mode = Standard +parameter const_ternary_enh = 2; //Constant for c_ternary_mode = XY + + +/************States for the CAM's internal state machine ****************/ +parameter READ_MODE = 1; +parameter START_WRITE_MODE = 2; +parameter END_BLK_WR_MODE = 3; +parameter BUSY_SRL_WR_MODE = 4; +parameter NEAR_SRL_END_WR_MODE = 5; +parameter END_SRL_WR_MODE = 6; + +integer CAM_MODE; + + + + +/************************************************************************* + * CAM Functions + *************************************************************************/ + + + + +/************************************************************************* + * FUNCTION: binary_match_encoder + * + * DESCRIPTION: + * This is the binary encoder which converts a one-hot match value into + * the binary match value + * + * An input of all-zeros produces a zero output + * + * INPUT: + * vector = one-hot encoded vector + * + * OUTPUT: + * binary encoded equivalent of the one-hot input + *************************************************************************/ + function [c_match_addr_width-1:0] binary_match_encoder; + + input [c_depth-1:0] vector; + integer i; + begin + binary_match_encoder=0; + for (i=0; i<=c_depth; i=i+1) + if (vector[i]==1'b1) + binary_match_encoder=i; + end + endfunction + + + +/************************************************************************* + * FUNCTION: one_hot + * + * DESCRIPTION: + * This function converts a binary value into a one-hot encoded + * value of width one_hot_size. + * + * INPUT: + * matchlocation = binary vector + * + * OUTPUT: + * one-hot encoded equivalent of binary value + *************************************************************************/ + function [c_depth-1:0] one_hot_match; + input [c_wr_addr_width-1:0] matchlocation; + integer i; + begin + for (i=0;i<=c_depth-1;i=i+1) + if (i==matchlocation) + one_hot_match[i] = 1'b1; + else + one_hot_match[i] = 1'b0; + end + endfunction + + +/************************************************************************* + * FUNCTION: set_bit + * + * DESCRIPTION: + * This function sets the bit bit_to_set of the input binary value. It + * returns the modified std_logic_vector of that binary value. + * + * INPUT: + * bit_to_set = value indicating which bit to set + * initialvalue = bit vector + * + * OUTPUT: + * initialvalue, with the bit_to_set bit set to '1' + *************************************************************************/ + function [c_depth-1:0] set_bit; + input [c_wr_addr_width-1:0] bit_to_set; + input [c_depth-1:0] initialvalue; + begin + set_bit = initialvalue; + set_bit[bit_to_set] = 1'b1; + end + endfunction + + +/************************************************************************* + * FUNCTION: ternary_value + * + * WARNING: THIS FUNCTION DOES NOT WORK FOR VERILOG + * + * DESCRIPTION: + * This function converts a mask and data vector into a single + * std_logic_vector using 1's 0's and X's. + * + * INPUT: + * mask : mask for data, if bit is '1', bit is considered an 'X' + * data : data + * + * OUTPUT: + * the data and mask combined into a single std_logic_vector, where + * any bit masked out is assigned the value 'X'. + *************************************************************************/ +// function [c_width-1:0] ternary_value; +// input [c_width-1:0] mask; +// input [c_width-1:0] data; +// integer i; +// begin +// for (i=0; i<=c_width-1; i=i+1) +// if (mask[i]==1'b1) +// ternary_value[i] = 1'bx; +// else +// ternary_value[i] = data[i]; +// end +// endfunction + + +/************************************************************************* + * FUNCTION: ternary_compare + * + * DESCRIPTION: + * This function compares two ternary values which are described using + * a combination of mask and data. When the mask bit = '1', the bit + * is considered an X, and will match either a 0 or a 1 bit. + * INPUTS: + * maska = mask for dataa, a bit of '1' indicates an 'X' value + * dataa = first data input + * maskb = mask for datab, a bit of '1' indicates an 'X' value + * datab = second data input + * + * OUTPUT: + * 1 if A matches B. X's (mask 1's) are considered "don't cares". + * 0 otherwise. + *************************************************************************/ + function ternary_compare; + input [c_width-1:0] maska; + input [c_width-1:0] dataa; + input [c_width-1:0] maskb; + input [c_width-1:0] datab; + integer i; + integer equal; + begin + equal = 1; + for (i=0; i<=c_width-1; i=i+1) + begin + if (dataa[i]===1'bz || datab[i]===1'bz) + equal = 0; + if (maska[i]==1'b0 && maskb[i]==1'b0) + begin + if (dataa[i]===1'b1 && datab[i]===1'b0) + equal = 0; + if (dataa[i]===1'b0 && datab[i]===1'b1) + equal = 0; + end + end + + ternary_compare = equal; + + end + endfunction + + function ternary_compare_xy; + input [c_width-1:0] maska; + input [c_width-1:0] dataa; + input [c_width-1:0] maskb; + input [c_width-1:0] datab; + integer i; + integer equal; + begin + equal = 1; + for (i=0; i<=c_width-1; i=i+1) + begin + if (dataa[i]===1'bz || datab[i]===1'bz) + equal = 0; + if (maska[i]==1'b1 || maskb[i]==1'b1) + begin + if (dataa[i]===1'b1 || datab[i]===1'b1) + equal = 0; + end + end + + ternary_compare_xy = equal; + + end + endfunction + + +/************************************************************************* + * FUNCTION: ternary_compareX + * + * WARNING: THIS FUNCTION DOES NOT WORK FOR VERILOG + * + * DESCRIPTION: + * This function compares two std_logic_vectors which can include X's. + * Here, an X is considered to match both 1 and 0. + * A U matches nothing. + * + * INPUTS: + * dataa = first data input (can include X's) + * datab = second data input (can include X's) + * + * OUTPUT: + * 1 if A matches B. X's are considered "don't cares". + * 0 otherwise. + *************************************************************************/ +// function ternary_compareX; +// input [c_width-1:0] dataa; +// input [c_width-1:0] datab; +// integer i; +// integer equal; +// begin +// equal = 1; +// for (i=0; i<=c_width-1; i=i+1) +// begin +// if (dataa[i]==1'bz || datab[i]==1'bz) +// equal = 0; +// if (dataa[i]==1'b1 && datab[i]==1'b0) +// equal = 0; +// if (dataa[i]==1'b0 && datab[i]==1'b1) +// equal = 0; +// end +// ternary_compareX = equal; +// end +// endfunction + + +/************************************************************************* + * FUNCTION: binary_compare + * + * DESCRIPTION: + * This function compares two std_logic_vectors (dataa and datab). + * It returns true if they are identical, false otherwise. + * If any bit is 'Z', the vectors are considered to not match. + * + * INPUTS: + * dataa = first data input (binary format) + * datab = second data input (binary format) + * + * OUTPUT: + * 1 if the binary values match exactly, + * 0 otherwise + *************************************************************************/ + function binary_compare; + input [c_width-1:0] dataa; + input [c_width-1:0] datab; + integer i; + integer equal; + begin + equal = 1; + for (i=0; i<=c_width-1; i=i+1) + begin + if (dataa[i]===1'bz || datab[i]===1'bz) + equal = 0; + if (dataa[i]===1'b1 && datab[i]===1'b0) + equal = 0; + if (dataa[i]===1'b0 && datab[i]===1'b1) + equal = 0; + end + + binary_compare = equal; + + end +endfunction + + + + +/************************************************************************* + * Establish initial values + *************************************************************************/ +initial + begin + //Initialize internal signals to 0 + RESET = 1'b0; + + busy_i = 1'b0; + read_warning_i = 1'b0; + + match_i = 1'b0; + multiple_match_i = 1'b0; + single_match_i = 1'b0; + + m_match_addr_i = 0; + + //Initialize registered outputs to 0 + // (they won't be updated until 2nd clock cycle) + data_mask_q = 0; + din_q = 0; + wr_addr_q = 0; + match_q = 1'b0; + match_addr_q = 0; + multiple_match_q = 1'b0; + read_warning_q = 1'b0; + single_match_q = 1'b0; + + //Initialize outputs to 0 + // (they won't be set until match transitions) + MATCH = 0; + if (c_addr_type == const_bin_encoded && + c_match_resolution_type == const_lowest_match) + MATCH_ADDR = c_depth; + else + MATCH_ADDR = 0; + if (c_has_multiple_match) + MULTIPLE_MATCH = multiple_match_q; + if (c_has_read_warning) + READ_WARNING = read_warning_q; + if (c_has_single_match) + SINGLE_MATCH = single_match_q; + + //Initialize internal write signals to 0 + // (since they are registered and don't get updated immediately) + wr_addr_int = 0; + wr_din = 0; + wr_data_mask = 0; + + write_counter = 0; + + CAM_MODE = READ_MODE; + + //Initializing the CAM + + // Set up temporary values for storing z's and 0's + for (initcntw=0; initcntw<=c_width-1; initcntw = initcntw+1) + begin + zees[initcntw]=1'bz; + zeros[initcntw]=1'b0; + end + + //Initialize the cam_init array so that each element is all-Zs + for (initcntd=0; initcntd<=c_depth-1; initcntd = initcntd+1) + cam_init[initcntd]=zees; + + //When initialization option is not selected, + // initialize data to Zs, and mask to 0s. + if (c_mem_init == 0) + for (initcntd=0; initcntd<=c_depth-1; initcntd = initcntd+1) + begin + cam_data[initcntd]=zees; + cam_mask[initcntd]=zeros; + end + + //if Initialization option is selected + else + begin + //Read cam_init array from the .mif file + $readmemb(c_mem_init_file, cam_init); + + //Set data and mask arrays based on .mif data + for (initcntd=0; initcntd<=c_depth-1; initcntd = initcntd+1) + begin + init_word = cam_init[initcntd]; + for (initcntw=0; initcntw<=c_width-1; initcntw = initcntw+1) + begin + if (init_word[initcntw] == 1'b0) + begin + data_word[initcntw] = 1'b0; + mask_word[initcntw] = 1'b0; + end + else if (init_word[initcntw] == 1'b1) + begin + data_word[initcntw] = 1'b1; + mask_word[initcntw] = 1'b0; + end + else + begin + data_word[initcntw] = 1'b0; + mask_word[initcntw] = 1'b1; + end + end + cam_data[initcntd] = data_word; + cam_mask[initcntd] = mask_word; + end + end + + end // initial begin + + + + + +/************************************************************************* + * Connect ports to internal signals + *************************************************************************/ + + //Data input bus (write data) + assign din_i = DIN; + + //Write Enable + assign we_i = c_has_we ? WE : 1'b0; + + //Write Address + assign wr_addr_i = c_has_wr_addr ? WR_ADDR : 0; + + //Busy flag + assign BUSY = busy_i; + + //Match flags, Match Address, Read Warning flag + always @(match_i or match_q or match_addr_i or match_addr_q or multiple_match_i or multiple_match_q or read_warning_i or read_warning_q or single_match_i or single_match_q) + begin + if (c_reg_outputs==1) + begin + MATCH = match_q; + MATCH_ADDR = match_addr_q; + if (c_has_multiple_match) + MULTIPLE_MATCH = multiple_match_q; + if (c_has_read_warning) + READ_WARNING = read_warning_q; + if (c_has_single_match) + SINGLE_MATCH = single_match_q; + end + else + begin + MATCH = match_i; + MATCH_ADDR = match_addr_i; + if (c_has_multiple_match) + MULTIPLE_MATCH = multiple_match_i; + if (c_has_read_warning) + READ_WARNING = read_warning_i; + if (c_has_single_match) + SINGLE_MATCH = single_match_i; + end + end // always @ (match_i, match_q, match_addr_i, match_addr_q) + + //Data mask for din port (write data) + assign data_mask_i = c_has_data_mask ? DATA_MASK : 0; + + //Read data input + assign rd_din = c_has_cmp_din ? CMP_DIN : DIN; + + //Data mask for read data input + //assign rd_data_mask = c_has_cmp_data_mask ? (c_has_cmp_din ? CMP_DATA_MASK : (c_has_data_mask ? DATA_MASK : 0)) : 0; + assign rd_data_mask = c_has_cmp_data_mask ? CMP_DATA_MASK : ((c_has_data_mask ? DATA_MASK : 0)); + + + //Internal enable signal + assign en_i = c_has_en ? EN : 1; + + +/************************************************************************* + * Registered Outputs + *************************************************************************/ +always @(posedge CLK or posedge RESET) + begin + if (c_reg_outputs==1) + begin + if (RESET) + begin + match_q <= 0; + match_addr_q <= 0; + multiple_match_q <= 0; + read_warning_q <= 0; + single_match_q <= 0; + end + else + if (en_i) + begin + match_q <= match_i; + match_addr_q <= match_addr_i; + multiple_match_q <= multiple_match_i; + read_warning_q <= read_warning_i; + single_match_q <= single_match_i; + end // if en_i + end // if ((c_reg_outputs==1) || (c_addr_type==const_bin_encoded)) + end // always @ (posedge CLK, posedge RESET) + + + + /************************************************************************* + * PROCESS: mode_proc + * + * DESCRIPTION: + * This always block determines the current state of the CAM. + * It implements a state machine. On the rising edge of the clock, this + * process determines the next state based on the current state and any + * relevant inputs (we_i, write_counter, or c_mem_type). + *************************************************************************/ + + always @(posedge CLK) + if (en_i) + case (CAM_MODE) + + READ_MODE: + if (we_i) + CAM_MODE <= START_WRITE_MODE; + else //we_i=1 + CAM_MODE <= READ_MODE; + + START_WRITE_MODE: + if (c_mem_type==const_block_mem) + CAM_MODE <= END_BLK_WR_MODE; + else //c_mem_type=srl16 + CAM_MODE <= BUSY_SRL_WR_MODE; + + END_BLK_WR_MODE: + if (we_i) + CAM_MODE <= START_WRITE_MODE; + else //we_i=1 + CAM_MODE <= READ_MODE; + + BUSY_SRL_WR_MODE: + if (write_counter < 14) + CAM_MODE <= BUSY_SRL_WR_MODE; + else //write_counter >= 14 + CAM_MODE <= NEAR_SRL_END_WR_MODE; + + NEAR_SRL_END_WR_MODE: + CAM_MODE <= END_SRL_WR_MODE; + + END_SRL_WR_MODE: + if (we_i) + CAM_MODE <= START_WRITE_MODE; + else //we_i=1 + CAM_MODE <= READ_MODE; + + default: + CAM_MODE <= READ_MODE; + + endcase // case(CAM_MODE) + + + + + +/************************************************************************* + * PROCESS: match_proc + * + * DESCRIPTION: + * This process provides the logic used to determine if there is a match, + * how many matches are present, and the ideal state of the various output + * signals associated with the match logic. + * (Note: these outputs might be overridden under certain conditions) + ************************************************************************* + * On the rising clock edge, the m_ (match_) internal signals are calculated. + * These m_ signals are later connected to the appropriate outputs. + *************************************************************************/ + always @(posedge CLK) + if (en_i) + begin + //set defaults + tmp_m_match_addr_i = 0; + single_match_i <= 1'b0; + multiple_match_i <= 1'b0; + match_i <= 1'b0; + m_matches = 0; + + for (i=0; i<=c_depth-1; i=i+1) + begin + if (c_match_resolution_type==const_highest_match) + //loop the other way if resolution_type changes + j = c_depth-1-i; + else + j = i; + + //determine if a match for the data is found in location i + // (either direct match, or a ternary match) + if ((c_ternary_mode == const_ternary_off && binary_compare(rd_din, cam_data[j])) + || (c_ternary_mode == const_ternary_std + && ternary_compare(rd_data_mask, rd_din, cam_mask[j], cam_data[j])) + || (c_ternary_mode == const_ternary_enh + && ternary_compare_xy(rd_data_mask, rd_din, cam_mask[j], cam_data[j]))) + + //If during a write, we are reading and writing to the same address + if (j == wr_addr_int && wren == 1) + ; //Then do nothing (don't count this match) + else + begin + //Otherwise, count the match + + + /******************************************************** + * Calculate once for Read + *******************************************************/ + //if one or more matches have already been found, + // update signals to reflect multiple matches + if (m_matches > 0) + begin + single_match_i <= 1'b0; + multiple_match_i <= 1'b1; + match_i <= 1'b1; + if (c_addr_type == const_mm_unencoded) + tmp_m_match_addr_i = set_bit(j, tmp_m_match_addr_i); + end + + + //if no matches have been found yet, then update signals + // to reflect a single match + if (m_matches == 0) + begin + single_match_i <= 1'b1; + multiple_match_i <= 1'b0; + match_i <= 1'b1; + tmp_m_match_addr_i = one_hot_match(j); + m_matches = m_matches + 1; + end + + end + end + + m_match_addr_i <= tmp_m_match_addr_i; + + end + + + +/************************************************************************* + * Match Address Output (optional binary encoding) + *************************************************************************/ + always @(m_match_addr_i) + if (c_addr_type==const_bin_encoded) + match_addr_i = binary_match_encoder(m_match_addr_i); + else + match_addr_i = m_match_addr_i; + + + +/************************************************************************* + * The internal write values (wr_data_mask and wr_din) are set asynchronously + * when din_i and data_mask_i changes, but once a write operation starts, + * they are connected to their registered values, to hold the data valid + * until the write operation is complete. + *************************************************************************/ + +always @(din_i or din_q or data_mask_i or data_mask_q or wr_addr_i or wr_addr_q or we_i or busy_i) + if (we_i==1 && busy_i==0) + begin + wr_data_mask <= data_mask_i; + wr_din <= din_i; + wr_addr_int <= wr_addr_i; + end + else + begin + wr_data_mask <= data_mask_q; + wr_din <= din_q; + wr_addr_int <= wr_addr_q; + end // else: !if(we_i==1 && busy_i==0) + + +assign wren = we_i | busy_i; + + +/************************************************************************* + * PROCESS: proc_inputs + * + * DESCRIPTION: + * Register the input values to hold them during processing. + *************************************************************************/ +always @(posedge CLK) + begin + if (en_i==1 && we_i==1 && busy_i==0) + begin + data_mask_q <= data_mask_i; + din_q <= din_i; + wr_addr_q <= wr_addr_i; + end + end + + + + +/************************************************************************* + * PROCESS: main + * + * DESCRIPTION: + * This process, on the rising edge of the clock, uses a case statement + * to identify the current state. + * In these blocks, the outputs for that CAM state are calculated. + * This implements a MEALY machine, where the outputs are set on each state + * transition according to the current state and the inputs. + *************************************************************************/ + +always @(posedge CLK) + begin + if (en_i) + case (CAM_MODE) + + /**************************************************************** + * READ MODE - CAM's normal state, searching for matches + ***************************************************************/ + READ_MODE: + if (we_i == 0) + // IF continuing to read + begin + busy_i <= 1'b0; + read_warning_i <= 1'b0; + write_counter <= 0; + end + else + // ELSE starting a write + begin + if ((c_ternary_mode == const_ternary_off && binary_compare(wr_din, rd_din)) + || (c_ternary_mode == const_ternary_std + && ternary_compare(wr_data_mask, wr_din, rd_data_mask, rd_din)) + || (c_ternary_mode == const_ternary_enh + && ternary_compare_xy(wr_data_mask, wr_din, rd_data_mask, rd_din))) + + //IF read and write data match, flag a read warning + read_warning_i <= 1'b1; + else + read_warning_i <= 1'b0; + + busy_i <= 1'b1; //Set busy while writing + write_counter <= write_counter+1; //Start counting the clock + //cycles for the write + end + + + + + //************************************************************* + // START WRITE MODE - A write operation has been initiated + //************************************************************* + START_WRITE_MODE: + if (c_mem_type == const_block_mem) + + // IF block memory implementation + begin + busy_i <= 0; + write_counter <= write_counter+1; + if ((c_ternary_mode == const_ternary_off && binary_compare(wr_din, rd_din)) + || (c_ternary_mode == const_ternary_std + && ternary_compare(wr_data_mask, wr_din, rd_data_mask, rd_din)) + || (c_ternary_mode == const_ternary_enh + && ternary_compare_xy(wr_data_mask, wr_din, rd_data_mask, rd_din))) + //IF read and write data match, flag a read warning + read_warning_i <= 1; + else + read_warning_i <= 0; + + // Update the contents of the CAM with the value being written + if (c_ternary_mode) + begin + cam_data[wr_addr_int] <= wr_din; + cam_mask[wr_addr_int] <= wr_data_mask; + end + else + cam_data[wr_addr_int] <= wr_din; + end + + else //c_mem_type=const_srl16 + + // ELSE srl16 implementation + begin + if ((c_ternary_mode == const_ternary_off && binary_compare(wr_din, rd_din)) + || (c_ternary_mode == const_ternary_std + && ternary_compare(wr_data_mask, wr_din, rd_data_mask, rd_din)) + || (c_ternary_mode == const_ternary_enh + && ternary_compare_xy(wr_data_mask, wr_din, rd_data_mask, rd_din))) + //IF read and write data match, flag a read warning + read_warning_i <= 1; + else + read_warning_i <= 0; + + busy_i <= 1;//Set busy while writing + write_counter <= write_counter+1;// Count clock cyles for the + // write + end + + + //************************************************************* + // END BLK WR MODE - Last cycle of a block-memory write operation + //************************************************************* + END_BLK_WR_MODE: + if (we_i == 0) + // IF ending the write operation and going into read_mode + begin + busy_i <= 0; + read_warning_i <= 0; + write_counter <= 0; + end + else + // ELSE starting another write operation immediately + begin + if ((c_ternary_mode == const_ternary_off && binary_compare(wr_din, rd_din)) + || (c_ternary_mode == const_ternary_std + && ternary_compare(wr_data_mask, wr_din, rd_data_mask, rd_din)) + || (c_ternary_mode == const_ternary_enh + && ternary_compare_xy(wr_data_mask, wr_din, rd_data_mask, rd_din))) + + //IF read and write data match, flag a read warning + read_warning_i <= 1; + else + read_warning_i <= 0; + + busy_i <= 1;//Set busy while writing + write_counter <= 1; + end // else: !ifwe_i + + + + + + //************************************************************* + // BUSY_SRL_WR_MODE - Middle of a SRL16 write operation + //************************************************************* + BUSY_SRL_WR_MODE: + begin + if ((c_ternary_mode == const_ternary_off && binary_compare(wr_din, rd_din)) + || (c_ternary_mode == const_ternary_std + && ternary_compare(wr_data_mask, wr_din, rd_data_mask, rd_din)) + || (c_ternary_mode == const_ternary_enh + && ternary_compare_xy(wr_data_mask, wr_din, rd_data_mask, rd_din))) + //IF read and write data match, flag a read warning + read_warning_i <= 1; + else + read_warning_i <= 0; + + busy_i <= 1;//Set busy while writing + write_counter <= write_counter+1;// Count clock cyles for the + // write + end // case: BUSY_SRL_WR_MODE + + + + + //************************************************************* + // NEAR_SRL_END_WR_MODE - Next-to-last clock cycle for an SRL16 write + //************************************************************* + NEAR_SRL_END_WR_MODE: + begin + if ((c_ternary_mode == const_ternary_off && binary_compare(wr_din, rd_din)) + || (c_ternary_mode == const_ternary_std + && ternary_compare(wr_data_mask, wr_din, rd_data_mask, rd_din)) + || (c_ternary_mode == const_ternary_enh + && ternary_compare_xy(wr_data_mask, wr_din, rd_data_mask, rd_din))) + //IF read and write data match, flag a read warning + read_warning_i <= 1; + else + read_warning_i <= 0; + + busy_i <= 0; + write_counter <= write_counter+1; + + // Update the contents of the CAM with the value being written + if (c_ternary_mode != const_ternary_off) + begin + cam_data[wr_addr_int] <= wr_din; + cam_mask[wr_addr_int] <= wr_data_mask; + end + else + cam_data[wr_addr_int] <= wr_din; + + end + + + + //************************************************************* + // END_SRL_WR_MODE - Last cycle of a SRL16 write operation + //************************************************************* + END_SRL_WR_MODE: + if (we_i == 0) + // IF ending the write operation and going into read_mode + begin + busy_i <= 0; + read_warning_i <= 0; + write_counter <= 0; + end + else + // ELSE starting another write operation immediately + begin + if ((c_ternary_mode == const_ternary_off && binary_compare(wr_din, rd_din)) + || (c_ternary_mode == const_ternary_std + && ternary_compare(wr_data_mask, wr_din, rd_data_mask, rd_din)) + || (c_ternary_mode == const_ternary_enh + && ternary_compare_xy(wr_data_mask, wr_din, rd_data_mask, rd_din))) + //IF read and write data match, flag a read warning + read_warning_i <= 1; + else + read_warning_i <= 0; + + busy_i <= 1;//Set busy while writing + write_counter <= 1; + end + + + endcase // case(CAM_MODE) + + end // always @ (posedge CLK) + + + + + + +endmodule // CAM_V5_0 + + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/CAM_V5_1.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/CAM_V5_1.v new file mode 100644 index 0000000..fc0f6f2 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/CAM_V5_1.v @@ -0,0 +1,1221 @@ +/**************************************************************************** + * $RCSfile: CAM_V5_1.v,v $ $Revision: 1.11 $ $Date: 2008/09/08 20:07:04 $ + * ************************************************************************** + * + * Content Addressable Memory - Verilog Behavioral Model + * + * Filename: CAM_V5_1.v + * + * Description: + * The behavioral model for the Content Addressable Memory core + * + * *************************************************************************/ + +// Copyright(C) 2004 by Xilinx, Inc. All rights reserved. +// This text/file contains proprietary, confidential +// information of Xilinx, Inc., is distributed under license +// from Xilinx, Inc., and may be used, copied and/or +// disclosed only pursuant to the terms of a valid license +// agreement with Xilinx, Inc. Xilinx hereby grants you +// a license to use this text/file solely for design, simulation, +// implementation and creation of design files limited +// to Xilinx devices or technologies. Use with non-Xilinx +// devices or technologies is expressly prohibited and +// immediately terminates your license unless covered by +// a separate agreement. +// +// Xilinx is providing this design, code, or information +// "as is" solely for use in developing programs and +// solutions for Xilinx devices. By providing this design, +// code, or information as one possible implementation of +// this feature, application or standard, Xilinx is making no +// representation that this implementation is free from any +// claims of infringement. You are responsible for +// obtaining any rights you may require for your implementation. +// Xilinx expressly disclaims any warranty whatsoever with +// respect to the adequacy of the implementation, including +// but not limited to any warranties or representations that this +// implementation is free from claims of infringement, implied +// warranties of merchantability or fitness for a particular +// purpose. +// +// Xilinx products are not intended for use in life support +// appliances, devices, or systems. Use in such applications are +// expressly prohibited. +// +// This copyright and support notice must be retained as part +// of this text at all times. (c) Copyright 1995-2004 Xilinx, Inc. +// All rights reserved. + + + /************************************************************************* + * Set the timescale value for this core + *************************************************************************/ +`timescale 1ns/10ps + + + /************************************************************************* + * Declare top-level module + *************************************************************************/ +module CAM_V5_1 + ( + CLK, + CMP_DATA_MASK, + CMP_DIN, + DATA_MASK, + DIN, + EN, + WE, + WR_ADDR, + BUSY, + MATCH, + MATCH_ADDR, + MULTIPLE_MATCH, + READ_WARNING, + SINGLE_MATCH + ); + + +/************************************************************************* + * Parameter Declarations (external) + *************************************************************************/ +parameter c_addr_type = 2; +parameter c_cmp_data_mask_width = 4; +parameter c_cmp_din_width = 4; +parameter c_data_mask_width = 4; +parameter c_depth = 16; +parameter c_din_width = 4; +parameter c_enable_rlocs = 0; +//parameter c_family = ""; +parameter c_has_cmp_data_mask = 0; +parameter c_has_cmp_din = 0; +parameter c_has_data_mask = 0; +parameter c_has_en = 0; +parameter c_has_multiple_match = 0; +parameter c_has_read_warning = 0; +parameter c_has_single_match = 0; +parameter c_has_we = 1; +parameter c_has_wr_addr = 1; +parameter c_match_addr_width = 16; +parameter c_match_resolution_type = 0; +parameter c_mem_init = 0; +parameter c_mem_init_file = ""; +parameter c_mem_type = 0; +parameter c_read_cycles = 1; +parameter c_reg_outputs = 0; +parameter c_ternary_mode = 0; +parameter c_width = 1; +parameter c_wr_addr_width = 4; + + +/**************************************************************************** + * Definition of Generics: + **************************************************************************** + * c_addr_type : Determines format of MATCH_ADDR output + * 0 = Binary Encoded + * 1 = Single Match Unencoded (one*hot) + * 2 = Multi*match unencoded (shows all matches) + * c_cmp_data_mask_width : Width of the cmp_data_mask port + * (should be the same as c_width) + * c_cmp_din_width : Width of the cmp_din port + * (should be the same as c_width) + * c_data_mask_width : Width of the data_mask port + * (should be the same as c_width) + * c_depth : Depth of the CAM + * (Must be > 2) + * c_din_width : Width of the din port + * (should be the same as c_width) + * c_enable_rlocs : Enable placement directives? + * 0 = Placement disabled + * 1 = Placement enabled + * c_family : Architecture (not used in behavioral model) + * c_has_cmp_data_mask : 1 if cmp_data_mask input port present + * c_has_cmp_din : 1 if cmp_din input port present + * c_has_data_mask : 1 if data_mask input port present + * c_has_en : 1 if en input port present + * c_has_multiple_match : 1 if multiple_match output port present + * c_has_read_warning : 1 if read_warning output port present + * c_has_single_match : 1 if single_match output port present + * c_has_we : 1 if we input port present + * c_has_wr_addr : 1 if wr_addr input port present + * c_match_addr_width : Width of the match_addr port + * log2roundup(c_depth) if c_addr_type=0 + * c_depth if c_addr_type = 1 or 2 + * c_match_resolution_type : When c_addr_type=0 or 1, only one match can + * be output. + * 0 = Output lowest matching address + * 1 = Output highest matching address + * c_mem_init : 0 = Do not initialize CAM + * 1 = Initialize CAM + * c_mem_init_file : Filename of .mif file for initializing CAM + * c_mem_type : 0 = SRL16E implementation + * 1 = Block Memory implementation + * c_read_cycles : Always fixed as 1 in CAM version 3.0 + * c_reg_outputs : For use with Block Memory ONLY. + * 0 = Do not add extra output registers. + * 1 = Add output registers + * c_ternary_mode : 0 = Binary CAM + * 1 = Ternary CAM (can store X's) + * c_width : Data Width of the CAM + * c_wr_addr_width : Width of wr_addr port = log2roundup(c_depth) + ***************************************************************************/ + + + +/************************************************************************* + * Input and Output Declarations + *************************************************************************/ +input CLK; +input [c_cmp_data_mask_width-1:0] CMP_DATA_MASK; +input [c_cmp_din_width-1:0] CMP_DIN; +input [c_data_mask_width-1:0] DATA_MASK; +input [c_din_width-1:0] DIN; +input EN; +input WE; +input [c_wr_addr_width-1:0] WR_ADDR; +output BUSY; +output MATCH; +output [c_match_addr_width-1:0] MATCH_ADDR; +output MULTIPLE_MATCH; +output READ_WARNING; +output SINGLE_MATCH; + +reg MATCH; +reg [c_match_addr_width-1:0] MATCH_ADDR; +reg MULTIPLE_MATCH; +reg READ_WARNING; +reg SINGLE_MATCH; + +/**************************************************************************** + * Definition of Ports + **************************************************************************** + * CLK : IN : Clock + * CMP_DATA_MASK : IN : Data mask for CMP_DIN port + * CMP_DIN : IN : Compare port - Data input (CAM read/search operation) + * DATA_MASK : IN : Data mask for DIN port + * DIN : IN : Data input (CAM Write operation, and CAM read/search) + * EN : IN : CAM enable (active high) + * WE : IN : CAM write enable (active high) + * WR_ADDR : IN : CAM write address + * BUSY : OUT : High state indicates that user can not start a new + * write operation + * MATCH : OUT : High state indicates one or more matches found + * MATCH_ADDR : OUT : Address (or addresses) of matches found (if any) + * MULTIPLE_MATCH : OUT : High state indicates MORE than one match found + * READ_WARNING : OUT : High state indicates that the match operation may + * have returned misleading results because the data + * was being modified by a simultanous write operation + * SINGLE_MATCH : OUT : High state indicates ONLY one match found + ***************************************************************************/ + + + +/************************************************************************* + * Internal wires and regs for each port + *************************************************************************/ +wire [c_width-1:0] rd_din; +wire [c_width-1:0] rd_data_mask; +wire [c_width-1:0] data_mask_i; +wire [c_width-1:0] din_i; +wire en_i; +wire we_i; +wire [c_wr_addr_width-1:0] wr_addr_i; +reg busy_i; + + +/************************************************************************* + * registered copies of inputs + *************************************************************************/ +reg [c_width-1:0] data_mask_q; +reg [c_width-1:0] din_q; +reg [c_wr_addr_width-1:0] wr_addr_q; +//[c_width-1:0] wr_data_mask_q; +//[c_width-1:0] wr_din_q; + + +/************************************************************************* + * non-registered versions of output ports + *************************************************************************/ +reg match_i; +reg [c_match_addr_width-1:0] match_addr_i; +reg multiple_match_i; +reg read_warning_i; +reg single_match_i; + + +/************************************************************************* + * registered versions of output ports + *************************************************************************/ +reg match_q; +reg [c_match_addr_width-1:0] match_addr_q; +reg multiple_match_q; +reg read_warning_q; +reg single_match_q; + + +/************************************************************************* + * internal signals, not connected to ports + *************************************************************************/ +reg [c_wr_addr_width-1:0] wr_addr_int; +reg [c_width-1:0] wr_din; +reg [c_width-1:0] wr_data_mask; + +integer write_counter; +wire wren; + +reg RESET; + + +/************************************************************************* + * internal signals used in the match always block + *************************************************************************/ +reg [c_depth-1:0] m_match_addr_i; +integer m_matches; +integer i, j, initcntw, initcntd; +reg [c_depth-1:0] tmp_m_match_addr_i; + + +/************************************************************************* + * Data type for internal cam data storage + *************************************************************************/ +reg [c_width-1:0] cam_data[0:c_depth-1]; + +/************************************************************************* + * Data type for internal cam mask storage + *************************************************************************/ +reg [c_width-1:0] cam_mask[0:c_depth-1]; + +/************************************************************************* + * Data type for internal cam initialization + *************************************************************************/ +reg [c_width-1:0] cam_init[0:c_depth-1]; + +/************************************************************************* + * Initialzation value for cam_data and cam_mask elements + *************************************************************************/ +reg [c_width-1:0] init_word; +reg [c_width-1:0] data_word; +reg [c_width-1:0] mask_word; +reg [c_width-1:0] zees; +reg [c_width-1:0] zeros; + +/************************************************************************* + * Internal Constants + *************************************************************************/ + +parameter const_srl_mem = 0; //Constant for c_mem_type= SRL16 +parameter const_block_mem = 1; //Constant for c_mem_type= Block Memory +parameter const_dist_mem = 2; //Constant for c_mem_type= Distributed Memory + +parameter const_bin_encoded = 0; //Constant for c_addr_type= Binary Encoded +parameter const_sm_unencoded = 1; //Constant for c_addr_type= Single-Match Unencoded +parameter const_mm_unencoded = 2; //Constant for c_addr_type= Multiple-Match Unencoded + +parameter const_lowest_match = 0; //Constant for c_resolution_type= Lowest Match +parameter const_highest_match = 1; //Constant for c_resolution_type= Highest Match + +parameter const_ternary_off = 0; //Constant for c_ternary_mode = None +parameter const_ternary_std = 1; //Constant for c_ternary_mode = Standard +parameter const_ternary_enh = 2; //Constant for c_ternary_mode = XY + + +/************States for the CAM's internal state machine ****************/ +parameter READ_MODE = 1; +parameter START_WRITE_MODE = 2; +parameter END_BLK_WR_MODE = 3; +parameter BUSY_SRL_WR_MODE = 4; +parameter NEAR_SRL_END_WR_MODE = 5; +parameter END_SRL_WR_MODE = 6; + +integer CAM_MODE; + + + + +/************************************************************************* + * CAM Functions + *************************************************************************/ + + + + +/************************************************************************* + * FUNCTION: binary_match_encoder + * + * DESCRIPTION: + * This is the binary encoder which converts a one-hot match value into + * the binary match value + * + * An input of all-zeros produces a zero output + * + * INPUT: + * vector = one-hot encoded vector + * + * OUTPUT: + * binary encoded equivalent of the one-hot input + *************************************************************************/ + function [c_match_addr_width-1:0] binary_match_encoder; + + input [c_depth-1:0] vector; + integer i; + begin + binary_match_encoder=0; + for (i=0; i<=c_depth; i=i+1) + if (vector[i]==1'b1) + binary_match_encoder=i; + end + endfunction + + + +/************************************************************************* + * FUNCTION: one_hot + * + * DESCRIPTION: + * This function converts a binary value into a one-hot encoded + * value of width one_hot_size. + * + * INPUT: + * matchlocation = binary vector + * + * OUTPUT: + * one-hot encoded equivalent of binary value + *************************************************************************/ + function [c_depth-1:0] one_hot_match; + input [c_wr_addr_width-1:0] matchlocation; + integer i; + begin + for (i=0;i<=c_depth-1;i=i+1) + if (i==matchlocation) + one_hot_match[i] = 1'b1; + else + one_hot_match[i] = 1'b0; + end + endfunction + + +/************************************************************************* + * FUNCTION: set_bit + * + * DESCRIPTION: + * This function sets the bit bit_to_set of the input binary value. It + * returns the modified std_logic_vector of that binary value. + * + * INPUT: + * bit_to_set = value indicating which bit to set + * initialvalue = bit vector + * + * OUTPUT: + * initialvalue, with the bit_to_set bit set to '1' + *************************************************************************/ + function [c_depth-1:0] set_bit; + input [c_wr_addr_width-1:0] bit_to_set; + input [c_depth-1:0] initialvalue; + begin + set_bit = initialvalue; + set_bit[bit_to_set] = 1'b1; + end + endfunction + + +/************************************************************************* + * FUNCTION: ternary_value + * + * WARNING: THIS FUNCTION DOES NOT WORK FOR VERILOG + * + * DESCRIPTION: + * This function converts a mask and data vector into a single + * std_logic_vector using 1's 0's and X's. + * + * INPUT: + * mask : mask for data, if bit is '1', bit is considered an 'X' + * data : data + * + * OUTPUT: + * the data and mask combined into a single std_logic_vector, where + * any bit masked out is assigned the value 'X'. + *************************************************************************/ +// function [c_width-1:0] ternary_value; +// input [c_width-1:0] mask; +// input [c_width-1:0] data; +// integer i; +// begin +// for (i=0; i<=c_width-1; i=i+1) +// if (mask[i]==1'b1) +// ternary_value[i] = 1'bx; +// else +// ternary_value[i] = data[i]; +// end +// endfunction + + +/************************************************************************* + * FUNCTION: ternary_compare + * + * DESCRIPTION: + * This function compares two ternary values which are described using + * a combination of mask and data. When the mask bit = '1', the bit + * is considered an X, and will match either a 0 or a 1 bit. + * INPUTS: + * maska = mask for dataa, a bit of '1' indicates an 'X' value + * dataa = first data input + * maskb = mask for datab, a bit of '1' indicates an 'X' value + * datab = second data input + * + * OUTPUT: + * 1 if A matches B. X's (mask 1's) are considered "don't cares". + * 0 otherwise. + *************************************************************************/ + function ternary_compare; + input [c_width-1:0] maska; + input [c_width-1:0] dataa; + input [c_width-1:0] maskb; + input [c_width-1:0] datab; + integer i; + integer equal; + begin + equal = 1; + for (i=0; i<=c_width-1; i=i+1) + begin + if (dataa[i]===1'bz || datab[i]===1'bz) + equal = 0; + if (maska[i]==1'b0 && maskb[i]==1'b0) + begin + if (dataa[i]===1'b1 && datab[i]===1'b0) + equal = 0; + if (dataa[i]===1'b0 && datab[i]===1'b1) + equal = 0; + end + end + + ternary_compare = equal; + + end + endfunction + + function ternary_compare_xy; + input [c_width-1:0] maska; + input [c_width-1:0] dataa; + input [c_width-1:0] maskb; + input [c_width-1:0] datab; + integer i; + integer equal; + begin + equal = 1; + for (i=0; i<=c_width-1; i=i+1) + begin + if (dataa[i]===1'bz || datab[i]===1'bz) + equal = 0; + if (maska[i]==1'b1 || maskb[i]==1'b1) + begin + if (dataa[i]===1'b1 || datab[i]===1'b1) + equal = 0; + end + end + + ternary_compare_xy = equal; + + end + endfunction + + +/************************************************************************* + * FUNCTION: ternary_compareX + * + * WARNING: THIS FUNCTION DOES NOT WORK FOR VERILOG + * + * DESCRIPTION: + * This function compares two std_logic_vectors which can include X's. + * Here, an X is considered to match both 1 and 0. + * A U matches nothing. + * + * INPUTS: + * dataa = first data input (can include X's) + * datab = second data input (can include X's) + * + * OUTPUT: + * 1 if A matches B. X's are considered "don't cares". + * 0 otherwise. + *************************************************************************/ +// function ternary_compareX; +// input [c_width-1:0] dataa; +// input [c_width-1:0] datab; +// integer i; +// integer equal; +// begin +// equal = 1; +// for (i=0; i<=c_width-1; i=i+1) +// begin +// if (dataa[i]==1'bz || datab[i]==1'bz) +// equal = 0; +// if (dataa[i]==1'b1 && datab[i]==1'b0) +// equal = 0; +// if (dataa[i]==1'b0 && datab[i]==1'b1) +// equal = 0; +// end +// ternary_compareX = equal; +// end +// endfunction + + +/************************************************************************* + * FUNCTION: binary_compare + * + * DESCRIPTION: + * This function compares two std_logic_vectors (dataa and datab). + * It returns true if they are identical, false otherwise. + * If any bit is 'Z', the vectors are considered to not match. + * + * INPUTS: + * dataa = first data input (binary format) + * datab = second data input (binary format) + * + * OUTPUT: + * 1 if the binary values match exactly, + * 0 otherwise + *************************************************************************/ + function binary_compare; + input [c_width-1:0] dataa; + input [c_width-1:0] datab; + integer i; + integer equal; + begin + equal = 1; + for (i=0; i<=c_width-1; i=i+1) + begin + if (dataa[i]===1'bz || datab[i]===1'bz) + equal = 0; + if (dataa[i]===1'b1 && datab[i]===1'b0) + equal = 0; + if (dataa[i]===1'b0 && datab[i]===1'b1) + equal = 0; + end + + binary_compare = equal; + + end +endfunction + + + + +/************************************************************************* + * Establish initial values + *************************************************************************/ +initial + begin + //Initialize internal signals to 0 + RESET = 1'b0; + + busy_i = 1'b0; + read_warning_i = 1'b0; + + match_i = 1'b0; + multiple_match_i = 1'b0; + single_match_i = 1'b0; + + m_match_addr_i = 0; + + //Initialize registered outputs to 0 + // (they won't be updated until 2nd clock cycle) + data_mask_q = 0; + din_q = 0; + wr_addr_q = 0; + match_q = 1'b0; + match_addr_q = 0; + multiple_match_q = 1'b0; + read_warning_q = 1'b0; + single_match_q = 1'b0; + + //Initialize outputs to 0 + // (they won't be set until match transitions) + MATCH = 0; + if (c_addr_type == const_bin_encoded && + c_match_resolution_type == const_lowest_match) + MATCH_ADDR = c_depth; + else + MATCH_ADDR = 0; + if (c_has_multiple_match) + MULTIPLE_MATCH = multiple_match_q; + if (c_has_read_warning) + READ_WARNING = read_warning_q; + if (c_has_single_match) + SINGLE_MATCH = single_match_q; + + //Initialize internal write signals to 0 + // (since they are registered and don't get updated immediately) + wr_addr_int = 0; + wr_din = 0; + wr_data_mask = 0; + + write_counter = 0; + + CAM_MODE = READ_MODE; + + //Initializing the CAM + + // Set up temporary values for storing z's and 0's + for (initcntw=0; initcntw<=c_width-1; initcntw = initcntw+1) + begin + zees[initcntw]=1'bz; + zeros[initcntw]=1'b0; + end + + //Initialize the cam_init array so that each element is all-Zs + for (initcntd=0; initcntd<=c_depth-1; initcntd = initcntd+1) + cam_init[initcntd]=zees; + + //When initialization option is not selected, + // initialize data to Zs, and mask to 0s. + if (c_mem_init == 0) + for (initcntd=0; initcntd<=c_depth-1; initcntd = initcntd+1) + begin + cam_data[initcntd]=zees; + cam_mask[initcntd]=zeros; + end + + //if Initialization option is selected + else + begin + //Read cam_init array from the .mif file + $readmemb(c_mem_init_file, cam_init); + + //Set data and mask arrays based on .mif data + for (initcntd=0; initcntd<=c_depth-1; initcntd = initcntd+1) + begin + init_word = cam_init[initcntd]; + for (initcntw=0; initcntw<=c_width-1; initcntw = initcntw+1) + begin + if (init_word[initcntw] == 1'b0) + begin + data_word[initcntw] = 1'b0; + mask_word[initcntw] = 1'b0; + end + else if (init_word[initcntw] == 1'b1) + begin + data_word[initcntw] = 1'b1; + mask_word[initcntw] = 1'b0; + end + else + begin + data_word[initcntw] = 1'b0; + mask_word[initcntw] = 1'b1; + end + end + cam_data[initcntd] = data_word; + cam_mask[initcntd] = mask_word; + end + end + + end // initial begin + + + + + +/************************************************************************* + * Connect ports to internal signals + *************************************************************************/ + + //Data input bus (write data) + assign din_i = DIN; + + //Write Enable + assign we_i = c_has_we ? WE : 1'b0; + + //Write Address + assign wr_addr_i = c_has_wr_addr ? WR_ADDR : 0; + + //Busy flag + assign BUSY = busy_i; + + //Match flags, Match Address, Read Warning flag + always @(match_i or match_q or match_addr_i or match_addr_q or multiple_match_i or multiple_match_q or read_warning_i or read_warning_q or single_match_i or single_match_q) + begin + if (c_reg_outputs==1) + begin + MATCH = match_q; + MATCH_ADDR = match_addr_q; + if (c_has_multiple_match) + MULTIPLE_MATCH = multiple_match_q; + if (c_has_read_warning) + READ_WARNING = read_warning_q; + if (c_has_single_match) + SINGLE_MATCH = single_match_q; + end + else + begin + MATCH = match_i; + MATCH_ADDR = match_addr_i; + if (c_has_multiple_match) + MULTIPLE_MATCH = multiple_match_i; + if (c_has_read_warning) + READ_WARNING = read_warning_i; + if (c_has_single_match) + SINGLE_MATCH = single_match_i; + end + end // always @ (match_i, match_q, match_addr_i, match_addr_q) + + //Data mask for din port (write data) + assign data_mask_i = c_has_data_mask ? DATA_MASK : 0; + + //Read data input + assign rd_din = c_has_cmp_din ? CMP_DIN : DIN; + + //Data mask for read data input + //assign rd_data_mask = c_has_cmp_data_mask ? (c_has_cmp_din ? CMP_DATA_MASK : (c_has_data_mask ? DATA_MASK : 0)) : 0; + assign rd_data_mask = c_has_cmp_data_mask ? CMP_DATA_MASK : ((c_has_data_mask ? DATA_MASK : 0)); + + + //Internal enable signal + assign en_i = c_has_en ? EN : 1; + + +/************************************************************************* + * Registered Outputs + *************************************************************************/ +always @(posedge CLK or posedge RESET) + begin + if (c_reg_outputs==1) + begin + if (RESET) + begin + match_q <= 0; + match_addr_q <= 0; + multiple_match_q <= 0; + read_warning_q <= 0; + single_match_q <= 0; + end + else + if (en_i) + begin + match_q <= match_i; + match_addr_q <= match_addr_i; + multiple_match_q <= multiple_match_i; + read_warning_q <= read_warning_i; + single_match_q <= single_match_i; + end // if en_i + end // if ((c_reg_outputs==1) || (c_addr_type==const_bin_encoded)) + end // always @ (posedge CLK, posedge RESET) + + + + /************************************************************************* + * PROCESS: mode_proc + * + * DESCRIPTION: + * This always block determines the current state of the CAM. + * It implements a state machine. On the rising edge of the clock, this + * process determines the next state based on the current state and any + * relevant inputs (we_i, write_counter, or c_mem_type). + *************************************************************************/ + + always @(posedge CLK) + if (en_i) + case (CAM_MODE) + + READ_MODE: + if (we_i) + CAM_MODE <= START_WRITE_MODE; + else //we_i=1 + CAM_MODE <= READ_MODE; + + START_WRITE_MODE: + if (c_mem_type==const_block_mem) + CAM_MODE <= END_BLK_WR_MODE; + else //c_mem_type=srl16 + CAM_MODE <= BUSY_SRL_WR_MODE; + + END_BLK_WR_MODE: + if (we_i) + CAM_MODE <= START_WRITE_MODE; + else //we_i=1 + CAM_MODE <= READ_MODE; + + BUSY_SRL_WR_MODE: + if (write_counter < 14) + CAM_MODE <= BUSY_SRL_WR_MODE; + else //write_counter >= 14 + CAM_MODE <= NEAR_SRL_END_WR_MODE; + + NEAR_SRL_END_WR_MODE: + CAM_MODE <= END_SRL_WR_MODE; + + END_SRL_WR_MODE: + if (we_i) + CAM_MODE <= START_WRITE_MODE; + else //we_i=1 + CAM_MODE <= READ_MODE; + + default: + CAM_MODE <= READ_MODE; + + endcase // case(CAM_MODE) + + + + + +/************************************************************************* + * PROCESS: match_proc + * + * DESCRIPTION: + * This process provides the logic used to determine if there is a match, + * how many matches are present, and the ideal state of the various output + * signals associated with the match logic. + * (Note: these outputs might be overridden under certain conditions) + ************************************************************************* + * On the rising clock edge, the m_ (match_) internal signals are calculated. + * These m_ signals are later connected to the appropriate outputs. + *************************************************************************/ + always @(posedge CLK) + if (en_i) + begin + //set defaults + tmp_m_match_addr_i = 0; + single_match_i <= 1'b0; + multiple_match_i <= 1'b0; + match_i <= 1'b0; + m_matches = 0; + + for (i=0; i<=c_depth-1; i=i+1) + begin + if (c_match_resolution_type==const_highest_match) + //loop the other way if resolution_type changes + j = c_depth-1-i; + else + j = i; + + //determine if a match for the data is found in location i + // (either direct match, or a ternary match) + if ((c_ternary_mode == const_ternary_off && binary_compare(rd_din, cam_data[j])) + || (c_ternary_mode == const_ternary_std + && ternary_compare(rd_data_mask, rd_din, cam_mask[j], cam_data[j])) + || (c_ternary_mode == const_ternary_enh + && ternary_compare_xy(rd_data_mask, rd_din, cam_mask[j], cam_data[j]))) + + //If during a write, we are reading and writing to the same address + if (j == wr_addr_int && wren == 1) + ; //Then do nothing (don't count this match) + else + begin + //Otherwise, count the match + + + /******************************************************** + * Calculate once for Read + *******************************************************/ + //if one or more matches have already been found, + // update signals to reflect multiple matches + if (m_matches > 0) + begin + single_match_i <= 1'b0; + multiple_match_i <= 1'b1; + match_i <= 1'b1; + if (c_addr_type == const_mm_unencoded) + tmp_m_match_addr_i = set_bit(j, tmp_m_match_addr_i); + end + + + //if no matches have been found yet, then update signals + // to reflect a single match + if (m_matches == 0) + begin + single_match_i <= 1'b1; + multiple_match_i <= 1'b0; + match_i <= 1'b1; + tmp_m_match_addr_i = one_hot_match(j); + m_matches = m_matches + 1; + end + + end + end + + m_match_addr_i <= tmp_m_match_addr_i; + + end + + + +/************************************************************************* + * Match Address Output (optional binary encoding) + *************************************************************************/ + always @(m_match_addr_i) + if (c_addr_type==const_bin_encoded) + match_addr_i = binary_match_encoder(m_match_addr_i); + else + match_addr_i = m_match_addr_i; + + + +/************************************************************************* + * The internal write values (wr_data_mask and wr_din) are set asynchronously + * when din_i and data_mask_i changes, but once a write operation starts, + * they are connected to their registered values, to hold the data valid + * until the write operation is complete. + *************************************************************************/ + +always @(din_i or din_q or data_mask_i or data_mask_q or wr_addr_i or wr_addr_q or we_i or busy_i) + if (we_i==1 && busy_i==0) + begin + wr_data_mask <= data_mask_i; + wr_din <= din_i; + wr_addr_int <= wr_addr_i; + end + else + begin + wr_data_mask <= data_mask_q; + wr_din <= din_q; + wr_addr_int <= wr_addr_q; + end // else: !if(we_i==1 && busy_i==0) + + +assign wren = we_i | busy_i; + + +/************************************************************************* + * PROCESS: proc_inputs + * + * DESCRIPTION: + * Register the input values to hold them during processing. + *************************************************************************/ +always @(posedge CLK) + begin + if (en_i==1 && we_i==1 && busy_i==0) + begin + data_mask_q <= data_mask_i; + din_q <= din_i; + wr_addr_q <= wr_addr_i; + end + end + + + + +/************************************************************************* + * PROCESS: main + * + * DESCRIPTION: + * This process, on the rising edge of the clock, uses a case statement + * to identify the current state. + * In these blocks, the outputs for that CAM state are calculated. + * This implements a MEALY machine, where the outputs are set on each state + * transition according to the current state and the inputs. + *************************************************************************/ + +always @(posedge CLK) + begin + if (en_i) + case (CAM_MODE) + + /**************************************************************** + * READ MODE - CAM's normal state, searching for matches + ***************************************************************/ + READ_MODE: + if (we_i == 0) + // IF continuing to read + begin + busy_i <= 1'b0; + read_warning_i <= 1'b0; + write_counter <= 0; + end + else + // ELSE starting a write + begin + if ((c_ternary_mode == const_ternary_off && binary_compare(wr_din, rd_din)) + || (c_ternary_mode == const_ternary_std + && ternary_compare(wr_data_mask, wr_din, rd_data_mask, rd_din)) + || (c_ternary_mode == const_ternary_enh + && ternary_compare_xy(wr_data_mask, wr_din, rd_data_mask, rd_din))) + + //IF read and write data match, flag a read warning + read_warning_i <= 1'b1; + else + read_warning_i <= 1'b0; + + busy_i <= 1'b1; //Set busy while writing + write_counter <= write_counter+1; //Start counting the clock + //cycles for the write + end + + + + + //************************************************************* + // START WRITE MODE - A write operation has been initiated + //************************************************************* + START_WRITE_MODE: + if (c_mem_type == const_block_mem) + + // IF block memory implementation + begin + busy_i <= 0; + write_counter <= write_counter+1; + if ((c_ternary_mode == const_ternary_off && binary_compare(wr_din, rd_din)) + || (c_ternary_mode == const_ternary_std + && ternary_compare(wr_data_mask, wr_din, rd_data_mask, rd_din)) + || (c_ternary_mode == const_ternary_enh + && ternary_compare_xy(wr_data_mask, wr_din, rd_data_mask, rd_din))) + //IF read and write data match, flag a read warning + read_warning_i <= 1; + else + read_warning_i <= 0; + + // Update the contents of the CAM with the value being written + if (c_ternary_mode) + begin + cam_data[wr_addr_int] <= wr_din; + cam_mask[wr_addr_int] <= wr_data_mask; + end + else + cam_data[wr_addr_int] <= wr_din; + end + + else //c_mem_type=const_srl16 + + // ELSE srl16 implementation + begin + if ((c_ternary_mode == const_ternary_off && binary_compare(wr_din, rd_din)) + || (c_ternary_mode == const_ternary_std + && ternary_compare(wr_data_mask, wr_din, rd_data_mask, rd_din)) + || (c_ternary_mode == const_ternary_enh + && ternary_compare_xy(wr_data_mask, wr_din, rd_data_mask, rd_din))) + //IF read and write data match, flag a read warning + read_warning_i <= 1; + else + read_warning_i <= 0; + + busy_i <= 1;//Set busy while writing + write_counter <= write_counter+1;// Count clock cyles for the + // write + end + + + //************************************************************* + // END BLK WR MODE - Last cycle of a block-memory write operation + //************************************************************* + END_BLK_WR_MODE: + if (we_i == 0) + // IF ending the write operation and going into read_mode + begin + busy_i <= 0; + read_warning_i <= 0; + write_counter <= 0; + end + else + // ELSE starting another write operation immediately + begin + if ((c_ternary_mode == const_ternary_off && binary_compare(wr_din, rd_din)) + || (c_ternary_mode == const_ternary_std + && ternary_compare(wr_data_mask, wr_din, rd_data_mask, rd_din)) + || (c_ternary_mode == const_ternary_enh + && ternary_compare_xy(wr_data_mask, wr_din, rd_data_mask, rd_din))) + + //IF read and write data match, flag a read warning + read_warning_i <= 1; + else + read_warning_i <= 0; + + busy_i <= 1;//Set busy while writing + write_counter <= 1; + end // else: !ifwe_i + + + + + + //************************************************************* + // BUSY_SRL_WR_MODE - Middle of a SRL16 write operation + //************************************************************* + BUSY_SRL_WR_MODE: + begin + if ((c_ternary_mode == const_ternary_off && binary_compare(wr_din, rd_din)) + || (c_ternary_mode == const_ternary_std + && ternary_compare(wr_data_mask, wr_din, rd_data_mask, rd_din)) + || (c_ternary_mode == const_ternary_enh + && ternary_compare_xy(wr_data_mask, wr_din, rd_data_mask, rd_din))) + //IF read and write data match, flag a read warning + read_warning_i <= 1; + else + read_warning_i <= 0; + + busy_i <= 1;//Set busy while writing + write_counter <= write_counter+1;// Count clock cyles for the + // write + end // case: BUSY_SRL_WR_MODE + + + + + //************************************************************* + // NEAR_SRL_END_WR_MODE - Next-to-last clock cycle for an SRL16 write + //************************************************************* + NEAR_SRL_END_WR_MODE: + begin + if ((c_ternary_mode == const_ternary_off && binary_compare(wr_din, rd_din)) + || (c_ternary_mode == const_ternary_std + && ternary_compare(wr_data_mask, wr_din, rd_data_mask, rd_din)) + || (c_ternary_mode == const_ternary_enh + && ternary_compare_xy(wr_data_mask, wr_din, rd_data_mask, rd_din))) + //IF read and write data match, flag a read warning + read_warning_i <= 1; + else + read_warning_i <= 0; + + busy_i <= 0; + write_counter <= write_counter+1; + + // Update the contents of the CAM with the value being written + if (c_ternary_mode != const_ternary_off) + begin + cam_data[wr_addr_int] <= wr_din; + cam_mask[wr_addr_int] <= wr_data_mask; + end + else + cam_data[wr_addr_int] <= wr_din; + + end + + + + //************************************************************* + // END_SRL_WR_MODE - Last cycle of a SRL16 write operation + //************************************************************* + END_SRL_WR_MODE: + if (we_i == 0) + // IF ending the write operation and going into read_mode + begin + busy_i <= 0; + read_warning_i <= 0; + write_counter <= 0; + end + else + // ELSE starting another write operation immediately + begin + if ((c_ternary_mode == const_ternary_off && binary_compare(wr_din, rd_din)) + || (c_ternary_mode == const_ternary_std + && ternary_compare(wr_data_mask, wr_din, rd_data_mask, rd_din)) + || (c_ternary_mode == const_ternary_enh + && ternary_compare_xy(wr_data_mask, wr_din, rd_data_mask, rd_din))) + //IF read and write data match, flag a read warning + read_warning_i <= 1; + else + read_warning_i <= 0; + + busy_i <= 1;//Set busy while writing + write_counter <= 1; + end + + + endcase // case(CAM_MODE) + + end // always @ (posedge CLK) + + + + + + +endmodule // CAM_V5_1 + + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/CAM_V6_1.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/CAM_V6_1.v new file mode 100644 index 0000000..2d2dd98 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/CAM_V6_1.v @@ -0,0 +1,1225 @@ +/**************************************************************************** + * $RCSfile: CAM_V6_1.v,v $ $Revision: 1.2 $ $Date: 2008/09/09 20:23:02 $ + * ************************************************************************** + * + * Content Addressable Memory - Verilog Behavioral Model + * + * Filename: CAM_V6_1.v + * + * Description: + * The behavioral model for the Content Addressable Memory core + * + * *************************************************************************/ + +// Copyright(C) 2004 by Xilinx, Inc. All rights reserved. +// This text/file contains proprietary, confidential +// information of Xilinx, Inc., is distributed under license +// from Xilinx, Inc., and may be used, copied and/or +// disclosed only pursuant to the terms of a valid license +// agreement with Xilinx, Inc. Xilinx hereby grants you +// a license to use this text/file solely for design, simulation, +// implementation and creation of design files limited +// to Xilinx devices or technologies. Use with non-Xilinx +// devices or technologies is expressly prohibited and +// immediately terminates your license unless covered by +// a separate agreement. +// +// Xilinx is providing this design, code, or information +// "as is" solely for use in developing programs and +// solutions for Xilinx devices. By providing this design, +// code, or information as one possible implementation of +// this feature, application or standard, Xilinx is making no +// representation that this implementation is free from any +// claims of infringement. You are responsible for +// obtaining any rights you may require for your implementation. +// Xilinx expressly disclaims any warranty whatsoever with +// respect to the adequacy of the implementation, including +// but not limited to any warranties or representations that this +// implementation is free from claims of infringement, implied +// warranties of merchantability or fitness for a particular +// purpose. +// +// Xilinx products are not intended for use in life support +// appliances, devices, or systems. Use in such applications are +// expressly prohibited. +// +// This copyright and support notice must be retained as part +// of this text at all times. (c) Copyright 1995-2004 Xilinx, Inc. +// All rights reserved. + + + /************************************************************************* + * Set the timescale value for this core + *************************************************************************/ +`timescale 1ns/10ps + + + /************************************************************************* + * Declare top-level module + *************************************************************************/ +module CAM_V6_1 + ( + CLK, + CMP_DATA_MASK, + CMP_DIN, + DATA_MASK, + DIN, + EN, + WE, + WR_ADDR, + BUSY, + MATCH, + MATCH_ADDR, + MULTIPLE_MATCH, + READ_WARNING, + SINGLE_MATCH + ); + + +/************************************************************************* + * Parameter Declarations (external) + *************************************************************************/ +parameter c_addr_type = 2; +parameter c_cmp_data_mask_width = 4; +parameter c_cmp_din_width = 4; +parameter c_data_mask_width = 4; +parameter c_depth = 16; +parameter c_din_width = 4; +parameter c_family = ""; +parameter c_has_cmp_data_mask = 0; +parameter c_has_cmp_din = 0; +parameter c_has_data_mask = 0; +parameter c_has_en = 0; +parameter c_has_multiple_match = 0; +parameter c_has_read_warning = 0; +parameter c_has_single_match = 0; +parameter c_has_we = 1; +parameter c_has_wr_addr = 1; +parameter c_match_addr_width = 16; +parameter c_match_resolution_type = 0; +parameter c_mem_init = 0; +parameter c_mem_init_file = ""; +parameter c_mem_type = 0; +parameter c_read_cycles = 1; +parameter c_reg_outputs = 0; +parameter c_ternary_mode = 0; +parameter c_width = 1; +parameter c_wr_addr_width = 4; + + +/**************************************************************************** + * Definition of Generics: + **************************************************************************** + * c_addr_type : Determines format of MATCH_ADDR output + * 0 = Binary Encoded + * 1 = Single Match Unencoded (one*hot) + * 2 = Multi*match unencoded (shows all matches) + * c_cmp_data_mask_width : Width of the cmp_data_mask port + * (should be the same as c_width) + * c_cmp_din_width : Width of the cmp_din port + * (should be the same as c_width) + * c_data_mask_width : Width of the data_mask port + * (should be the same as c_width) + * c_depth : Depth of the CAM + * (Must be > 2) + * c_din_width : Width of the din port + * (should be the same as c_width) + * c_family : Architecture (not used in behavioral model) + * c_has_cmp_data_mask : 1 if cmp_data_mask input port present + * c_has_cmp_din : 1 if cmp_din input port present + * c_has_data_mask : 1 if data_mask input port present + * c_has_en : 1 if en input port present + * c_has_multiple_match : 1 if multiple_match output port present + * c_has_read_warning : 1 if read_warning output port present + * c_has_single_match : 1 if single_match output port present + * c_has_we : 1 if we input port present + * c_has_wr_addr : 1 if wr_addr input port present + * c_match_addr_width : Width of the match_addr port + * log2roundup(c_depth) if c_addr_type=0 + * c_depth if c_addr_type = 1 or 2 + * c_match_resolution_type : When c_addr_type=0 or 1, only one match can + * be output. + * 0 = Output lowest matching address + * 1 = Output highest matching address + * c_mem_init : 0 = Do not initialize CAM + * 1 = Initialize CAM + * c_mem_init_file : Filename of .mif file for initializing CAM + * c_mem_type : 0 = SRL16E implementation + * 1 = Block Memory implementation + * c_read_cycles : Always fixed as 1 in CAM version 3.0 + * c_reg_outputs : For use with Block Memory ONLY. + * 0 = Do not add extra output registers. + * 1 = Add output registers + * c_ternary_mode : 0 = Binary CAM + * 1 = Ternary CAM (can store X's) + * c_width : Data Width of the CAM + * c_wr_addr_width : Width of wr_addr port = log2roundup(c_depth) + ***************************************************************************/ + + + +/************************************************************************* + * Input and Output Declarations + *************************************************************************/ +input CLK; +input [c_cmp_data_mask_width-1:0] CMP_DATA_MASK; +input [c_cmp_din_width-1:0] CMP_DIN; +input [c_data_mask_width-1:0] DATA_MASK; +input [c_din_width-1:0] DIN; +input EN; +input WE; +input [c_wr_addr_width-1:0] WR_ADDR; +output BUSY; +output MATCH; +output [c_match_addr_width-1:0] MATCH_ADDR; +output MULTIPLE_MATCH; +output READ_WARNING; +output SINGLE_MATCH; + +reg MATCH; +reg [c_match_addr_width-1:0] MATCH_ADDR; +reg MULTIPLE_MATCH; +reg READ_WARNING; +reg SINGLE_MATCH; + +/**************************************************************************** + * Definition of Ports + **************************************************************************** + * CLK : IN : Clock + * CMP_DATA_MASK : IN : Data mask for CMP_DIN port + * CMP_DIN : IN : Compare port - Data input (CAM read/search operation) + * DATA_MASK : IN : Data mask for DIN port + * DIN : IN : Data input (CAM Write operation, and CAM read/search) + * EN : IN : CAM enable (active high) + * WE : IN : CAM write enable (active high) + * WR_ADDR : IN : CAM write address + * BUSY : OUT : High state indicates that user can not start a new + * write operation + * MATCH : OUT : High state indicates one or more matches found + * MATCH_ADDR : OUT : Address (or addresses) of matches found (if any) + * MULTIPLE_MATCH : OUT : High state indicates MORE than one match found + * READ_WARNING : OUT : High state indicates that the match operation may + * have returned misleading results because the data + * was being modified by a simultanous write operation + * SINGLE_MATCH : OUT : High state indicates ONLY one match found + ***************************************************************************/ + + + +/************************************************************************* + * Internal wires and regs for each port + *************************************************************************/ +wire [c_width-1:0] rd_din; +wire [c_width-1:0] rd_data_mask; +wire [c_width-1:0] data_mask_i; +wire [c_width-1:0] din_i; +wire en_i; +wire we_i; +wire [c_wr_addr_width-1:0] wr_addr_i; +reg busy_i; + + +/************************************************************************* + * registered copies of inputs + *************************************************************************/ +reg [c_width-1:0] data_mask_q; +reg [c_width-1:0] din_q; +reg [c_wr_addr_width-1:0] wr_addr_q; +//[c_width-1:0] wr_data_mask_q; +//[c_width-1:0] wr_din_q; + + +/************************************************************************* + * non-registered versions of output ports + *************************************************************************/ +reg match_i; +reg [c_match_addr_width-1:0] match_addr_i; +reg multiple_match_i; +reg read_warning_i; +reg single_match_i; + + +/************************************************************************* + * registered versions of output ports + *************************************************************************/ +reg match_q; +reg [c_match_addr_width-1:0] match_addr_q; +reg multiple_match_q; +reg read_warning_q; +reg single_match_q; + + +/************************************************************************* + * internal signals, not connected to ports + *************************************************************************/ +reg [c_wr_addr_width-1:0] wr_addr_int; +reg [c_width-1:0] wr_din; +reg [c_width-1:0] wr_data_mask; + +integer write_counter; +wire wren; + +reg RESET; + + +/************************************************************************* + * internal signals used in the match always block + *************************************************************************/ +reg [c_depth-1:0] m_match_addr_i; +integer m_matches; +integer i, j, initcntw, initcntd; +reg [c_depth-1:0] tmp_m_match_addr_i; + + +/************************************************************************* + * Data type for internal cam data storage + *************************************************************************/ +reg [c_width-1:0] cam_data[0:c_depth-1]; + +/************************************************************************* + * Data type for internal cam mask storage + *************************************************************************/ +reg [c_width-1:0] cam_mask[0:c_depth-1]; + +/************************************************************************* + * Data type for internal cam initialization + *************************************************************************/ +reg [c_width-1:0] cam_init[0:c_depth-1]; + +/************************************************************************* + * Initialzation value for cam_data and cam_mask elements + *************************************************************************/ +reg [c_width-1:0] init_word; +reg [c_width-1:0] data_word; +reg [c_width-1:0] mask_word; +reg [c_width-1:0] zees; +reg [c_width-1:0] zeros; + +/************************************************************************* + * Internal Constants + *************************************************************************/ + +parameter const_srl_mem = 0; //Constant for c_mem_type= SRL16 +parameter const_block_mem = 1; //Constant for c_mem_type= Block Memory +parameter const_dist_mem = 2; //Constant for c_mem_type= Distributed Memory + +parameter const_bin_encoded = 0; //Constant for c_addr_type= Binary Encoded +parameter const_sm_unencoded = 1; //Constant for c_addr_type= Single-Match Unencoded +parameter const_mm_unencoded = 2; //Constant for c_addr_type= Multiple-Match Unencoded + +parameter const_lowest_match = 0; //Constant for c_resolution_type= Lowest Match +parameter const_highest_match = 1; //Constant for c_resolution_type= Highest Match + +parameter const_ternary_off = 0; //Constant for c_ternary_mode = None +parameter const_ternary_std = 1; //Constant for c_ternary_mode = Standard +parameter const_ternary_enh = 2; //Constant for c_ternary_mode = XY + + +/************States for the CAM's internal state machine ****************/ +parameter READ_MODE = 1; +parameter START_WRITE_MODE = 2; +parameter END_BLK_WR_MODE = 3; +parameter BUSY_SRL_WR_MODE = 4; +parameter NEAR_SRL_END_WR_MODE = 5; +parameter END_SRL_WR_MODE = 6; + +integer CAM_MODE; + + + + +/************************************************************************* + * CAM Functions + *************************************************************************/ + + + + +/************************************************************************* + * FUNCTION: binary_match_encoder + * + * DESCRIPTION: + * This is the binary encoder which converts a one-hot match value into + * the binary match value + * + * An input of all-zeros produces a zero output + * + * INPUT: + * vector = one-hot encoded vector + * + * OUTPUT: + * binary encoded equivalent of the one-hot input + *************************************************************************/ + function [c_match_addr_width-1:0] binary_match_encoder; + + input [c_depth-1:0] vector; + integer i; + begin + binary_match_encoder=0; + for (i=0; i<=c_depth; i=i+1) + if (vector[i]==1'b1) + binary_match_encoder=i; + end + endfunction + + + +/************************************************************************* + * FUNCTION: one_hot + * + * DESCRIPTION: + * This function converts a binary value into a one-hot encoded + * value of width one_hot_size. + * + * INPUT: + * matchlocation = binary vector + * + * OUTPUT: + * one-hot encoded equivalent of binary value + *************************************************************************/ + function [c_depth-1:0] one_hot_match; + input [c_wr_addr_width-1:0] matchlocation; + integer i; + begin + for (i=0;i<=c_depth-1;i=i+1) + if (i==matchlocation) + one_hot_match[i] = 1'b1; + else + one_hot_match[i] = 1'b0; + end + endfunction + + +/************************************************************************* + * FUNCTION: set_bit + * + * DESCRIPTION: + * This function sets the bit bit_to_set of the input binary value. It + * returns the modified std_logic_vector of that binary value. + * + * INPUT: + * bit_to_set = value indicating which bit to set + * initialvalue = bit vector + * + * OUTPUT: + * initialvalue, with the bit_to_set bit set to '1' + *************************************************************************/ + function [c_depth-1:0] set_bit; + input [c_wr_addr_width-1:0] bit_to_set; + input [c_depth-1:0] initialvalue; + begin + set_bit = initialvalue; + set_bit[bit_to_set] = 1'b1; + end + endfunction + + +/************************************************************************* + * FUNCTION: ternary_value + * + * WARNING: THIS FUNCTION DOES NOT WORK FOR VERILOG + * + * DESCRIPTION: + * This function converts a mask and data vector into a single + * std_logic_vector using 1's 0's and X's. + * + * INPUT: + * mask : mask for data, if bit is '1', bit is considered an 'X' + * data : data + * + * OUTPUT: + * the data and mask combined into a single std_logic_vector, where + * any bit masked out is assigned the value 'X'. + *************************************************************************/ +// function [c_width-1:0] ternary_value; +// input [c_width-1:0] mask; +// input [c_width-1:0] data; +// integer i; +// begin +// for (i=0; i<=c_width-1; i=i+1) +// if (mask[i]==1'b1) +// ternary_value[i] = 1'bx; +// else +// ternary_value[i] = data[i]; +// end +// endfunction + + +/************************************************************************* + * FUNCTION: ternary_compare + * + * DESCRIPTION: + * This function compares two ternary values which are described using + * a combination of mask and data. When the mask bit = '1', the bit + * is considered an X, and will match either a 0 or a 1 bit. + * INPUTS: + * maska = mask for dataa, a bit of '1' indicates an 'X' value + * dataa = first data input + * maskb = mask for datab, a bit of '1' indicates an 'X' value + * datab = second data input + * + * OUTPUT: + * 1 if A matches B. X's (mask 1's) are considered "don't cares". + * 0 otherwise. + *************************************************************************/ + function ternary_compare; + input [c_width-1:0] maska; + input [c_width-1:0] dataa; + input [c_width-1:0] maskb; + input [c_width-1:0] datab; + integer i; + integer equal; + begin + equal = 1; + for (i=0; i<=c_width-1; i=i+1) + begin + if (dataa[i]===1'bz || datab[i]===1'bz) + equal = 0; + if (maska[i]==1'b0 && maskb[i]==1'b0) + begin + if (dataa[i]===1'b1 && datab[i]===1'b0) + equal = 0; + if (dataa[i]===1'b0 && datab[i]===1'b1) + equal = 0; + end + end + + ternary_compare = equal; + + end + endfunction + + function ternary_compare_xy; + input [c_width-1:0] maska; + input [c_width-1:0] dataa; + input [c_width-1:0] maskb; + input [c_width-1:0] datab; + integer i; + integer equal; + begin + equal = 1; + for (i=0; i<=c_width-1; i=i+1) + begin + if (dataa[i]===1'bz || datab[i]===1'bz) + equal = 0; + if (maska[i]==1'b1 || maskb[i]==1'b1) + begin + if (dataa[i]===1'b1 || datab[i]===1'b1) + equal = 0; + end + end + + ternary_compare_xy = equal; + + end + endfunction + + +/************************************************************************* + * FUNCTION: ternary_compareX + * + * WARNING: THIS FUNCTION DOES NOT WORK FOR VERILOG + * + * DESCRIPTION: + * This function compares two std_logic_vectors which can include X's. + * Here, an X is considered to match both 1 and 0. + * A U matches nothing. + * + * INPUTS: + * dataa = first data input (can include X's) + * datab = second data input (can include X's) + * + * OUTPUT: + * 1 if A matches B. X's are considered "don't cares". + * 0 otherwise. + *************************************************************************/ +// function ternary_compareX; +// input [c_width-1:0] dataa; +// input [c_width-1:0] datab; +// integer i; +// integer equal; +// begin +// equal = 1; +// for (i=0; i<=c_width-1; i=i+1) +// begin +// if (dataa[i]==1'bz || datab[i]==1'bz) +// equal = 0; +// if (dataa[i]==1'b1 && datab[i]==1'b0) +// equal = 0; +// if (dataa[i]==1'b0 && datab[i]==1'b1) +// equal = 0; +// end +// ternary_compareX = equal; +// end +// endfunction + + +/************************************************************************* + * FUNCTION: binary_compare + * + * DESCRIPTION: + * This function compares two std_logic_vectors (dataa and datab). + * It returns true if they are identical, false otherwise. + * If any bit is 'Z', the vectors are considered to not match. + * + * INPUTS: + * dataa = first data input (binary format) + * datab = second data input (binary format) + * + * OUTPUT: + * 1 if the binary values match exactly, + * 0 otherwise + *************************************************************************/ + function binary_compare; + input [c_width-1:0] dataa; + input [c_width-1:0] datab; + integer i; + integer equal; + begin + equal = 1; + for (i=0; i<=c_width-1; i=i+1) + begin + if (dataa[i]===1'bz || datab[i]===1'bz) + equal = 0; + if (dataa[i]===1'b1 && datab[i]===1'b0) + equal = 0; + if (dataa[i]===1'b0 && datab[i]===1'b1) + equal = 0; + end + + binary_compare = equal; + + end +endfunction + + + + +/************************************************************************* + * Establish initial values + *************************************************************************/ +initial + begin + //Initialize internal signals to 0 + RESET = 1'b0; + + busy_i = 1'b0; + read_warning_i = 1'b0; + + match_i = 1'b0; + multiple_match_i = 1'b0; + single_match_i = 1'b0; + + m_match_addr_i = 0; + + //Initialize registered outputs to 0 + // (they won't be updated until 2nd clock cycle) + data_mask_q = 0; + din_q = 0; + wr_addr_q = 0; + match_q = 1'b0; + match_addr_q = 0; + multiple_match_q = 1'b0; + read_warning_q = 1'b0; + single_match_q = 1'b0; + + //Initialize outputs to 0 + // (they won't be set until match transitions) + MATCH = 0; + if (c_addr_type == const_bin_encoded && + c_match_resolution_type == const_lowest_match) + MATCH_ADDR = c_depth; + else + MATCH_ADDR = 0; + if (c_has_multiple_match) + MULTIPLE_MATCH = multiple_match_q; + if (c_has_read_warning) + READ_WARNING = read_warning_q; + if (c_has_single_match) + SINGLE_MATCH = single_match_q; + + //Initialize internal write signals to 0 + // (since they are registered and don't get updated immediately) + wr_addr_int = 0; + wr_din = 0; + wr_data_mask = 0; + + write_counter = 0; + + CAM_MODE = READ_MODE; + + //Initializing the CAM + + // Set up temporary values for storing z's and 0's + for (initcntw=0; initcntw<=c_width-1; initcntw = initcntw+1) + begin + zees[initcntw]=1'bz; + zeros[initcntw]=1'b0; + end + + //Initialize the cam_init array so that each element is all-Zs + for (initcntd=0; initcntd<=c_depth-1; initcntd = initcntd+1) + cam_init[initcntd]=zees; + + //When initialization option is not selected, + // initialize data to Zs, and mask to 0s. + if (c_mem_init == 0) + for (initcntd=0; initcntd<=c_depth-1; initcntd = initcntd+1) + begin + cam_data[initcntd]=zees; + cam_mask[initcntd]=zeros; + end + + //if Initialization option is selected + else + begin + //Read cam_init array from the .mif file + $readmemb(c_mem_init_file, cam_init); + + //Set data and mask arrays based on .mif data + for (initcntd=0; initcntd<=c_depth-1; initcntd = initcntd+1) + begin + init_word = cam_init[initcntd]; + for (initcntw=0; initcntw<=c_width-1; initcntw = initcntw+1) + begin + if (init_word[initcntw] == 1'b0) + begin + data_word[initcntw] = 1'b0; + mask_word[initcntw] = 1'b0; + end + else if (init_word[initcntw] == 1'b1) + begin + data_word[initcntw] = 1'b1; + mask_word[initcntw] = 1'b0; + end + //Standard Ternary Mode (init_word=x) + else if (init_word[initcntw] === 1'bx) + begin + data_word[initcntw] = 1'b0; + mask_word[initcntw] = 1'b1; + end + //Uninitialized case (cam_init array was initialized to z earlier + //in this code. + else + begin + data_word[initcntw] = 1'bz; + mask_word[initcntw] = 1'b0; + end + end + cam_data[initcntd] = data_word; + cam_mask[initcntd] = mask_word; + end + end + + end // initial begin + + + + + +/************************************************************************* + * Connect ports to internal signals + *************************************************************************/ + + //Data input bus (write data) + assign din_i = DIN; + + //Write Enable + assign we_i = c_has_we ? WE : 1'b0; + + //Write Address + assign wr_addr_i = c_has_wr_addr ? WR_ADDR : 0; + + //Busy flag + assign BUSY = busy_i; + + //Match flags, Match Address, Read Warning flag + always @(match_i or match_q or match_addr_i or match_addr_q or multiple_match_i or multiple_match_q or read_warning_i or read_warning_q or single_match_i or single_match_q) + begin + if (c_reg_outputs==1) + begin + MATCH = match_q; + MATCH_ADDR = match_addr_q; + if (c_has_multiple_match) + MULTIPLE_MATCH = multiple_match_q; + if (c_has_read_warning) + READ_WARNING = read_warning_q; + if (c_has_single_match) + SINGLE_MATCH = single_match_q; + end + else + begin + MATCH = match_i; + MATCH_ADDR = match_addr_i; + if (c_has_multiple_match) + MULTIPLE_MATCH = multiple_match_i; + if (c_has_read_warning) + READ_WARNING = read_warning_i; + if (c_has_single_match) + SINGLE_MATCH = single_match_i; + end + end // always @ (match_i, match_q, match_addr_i, match_addr_q) + + //Data mask for din port (write data) + assign data_mask_i = c_has_data_mask ? DATA_MASK : 0; + + //Read data input + assign rd_din = c_has_cmp_din ? CMP_DIN : DIN; + + //Data mask for read data input + //assign rd_data_mask = c_has_cmp_data_mask ? (c_has_cmp_din ? CMP_DATA_MASK : (c_has_data_mask ? DATA_MASK : 0)) : 0; + assign rd_data_mask = c_has_cmp_data_mask ? CMP_DATA_MASK : ((c_has_data_mask ? DATA_MASK : 0)); + + + //Internal enable signal + assign en_i = c_has_en ? EN : 1; + + +/************************************************************************* + * Registered Outputs + *************************************************************************/ +always @(posedge CLK or posedge RESET) + begin + if (c_reg_outputs==1) + begin + if (RESET) + begin + match_q <= 0; + match_addr_q <= 0; + multiple_match_q <= 0; + read_warning_q <= 0; + single_match_q <= 0; + end + else + if (en_i) + begin + match_q <= match_i; + match_addr_q <= match_addr_i; + multiple_match_q <= multiple_match_i; + read_warning_q <= read_warning_i; + single_match_q <= single_match_i; + end // if en_i + end // if ((c_reg_outputs==1) || (c_addr_type==const_bin_encoded)) + end // always @ (posedge CLK, posedge RESET) + + + + /************************************************************************* + * PROCESS: mode_proc + * + * DESCRIPTION: + * This always block determines the current state of the CAM. + * It implements a state machine. On the rising edge of the clock, this + * process determines the next state based on the current state and any + * relevant inputs (we_i, write_counter, or c_mem_type). + *************************************************************************/ + + always @(posedge CLK) + if (en_i) + case (CAM_MODE) + + READ_MODE: + if (we_i) + CAM_MODE <= START_WRITE_MODE; + else //we_i=1 + CAM_MODE <= READ_MODE; + + START_WRITE_MODE: + if (c_mem_type==const_block_mem) + CAM_MODE <= END_BLK_WR_MODE; + else //c_mem_type=srl16 + CAM_MODE <= BUSY_SRL_WR_MODE; + + END_BLK_WR_MODE: + if (we_i) + CAM_MODE <= START_WRITE_MODE; + else //we_i=1 + CAM_MODE <= READ_MODE; + + BUSY_SRL_WR_MODE: + if (write_counter < 14) + CAM_MODE <= BUSY_SRL_WR_MODE; + else //write_counter >= 14 + CAM_MODE <= NEAR_SRL_END_WR_MODE; + + NEAR_SRL_END_WR_MODE: + CAM_MODE <= END_SRL_WR_MODE; + + END_SRL_WR_MODE: + if (we_i) + CAM_MODE <= START_WRITE_MODE; + else //we_i=1 + CAM_MODE <= READ_MODE; + + default: + CAM_MODE <= READ_MODE; + + endcase // case(CAM_MODE) + + + + + +/************************************************************************* + * PROCESS: match_proc + * + * DESCRIPTION: + * This process provides the logic used to determine if there is a match, + * how many matches are present, and the ideal state of the various output + * signals associated with the match logic. + * (Note: these outputs might be overridden under certain conditions) + ************************************************************************* + * On the rising clock edge, the m_ (match_) internal signals are calculated. + * These m_ signals are later connected to the appropriate outputs. + *************************************************************************/ + always @(posedge CLK) + if (en_i) + begin + //set defaults + tmp_m_match_addr_i = 0; + single_match_i <= 1'b0; + multiple_match_i <= 1'b0; + match_i <= 1'b0; + m_matches = 0; + + for (i=0; i<=c_depth-1; i=i+1) + begin + if (c_match_resolution_type==const_highest_match) + //loop the other way if resolution_type changes + j = c_depth-1-i; + else + j = i; + + //determine if a match for the data is found in location i + // (either direct match, or a ternary match) + if ((c_ternary_mode == const_ternary_off && binary_compare(rd_din, cam_data[j])) + || (c_ternary_mode == const_ternary_std + && ternary_compare(rd_data_mask, rd_din, cam_mask[j], cam_data[j])) + || (c_ternary_mode == const_ternary_enh + && ternary_compare_xy(rd_data_mask, rd_din, cam_mask[j], cam_data[j]))) + + //If during a write, we are reading and writing to the same address + if (j == wr_addr_int && wren == 1) + ; //Then do nothing (don't count this match) + else + begin + //Otherwise, count the match + + + /******************************************************** + * Calculate once for Read + *******************************************************/ + //if one or more matches have already been found, + // update signals to reflect multiple matches + if (m_matches > 0) + begin + single_match_i <= 1'b0; + multiple_match_i <= 1'b1; + match_i <= 1'b1; + if (c_addr_type == const_mm_unencoded) + tmp_m_match_addr_i = set_bit(j, tmp_m_match_addr_i); + end + + + //if no matches have been found yet, then update signals + // to reflect a single match + if (m_matches == 0) + begin + single_match_i <= 1'b1; + multiple_match_i <= 1'b0; + match_i <= 1'b1; + tmp_m_match_addr_i = one_hot_match(j); + m_matches = m_matches + 1; + end + + end + end + + m_match_addr_i <= tmp_m_match_addr_i; + + end + + + +/************************************************************************* + * Match Address Output (optional binary encoding) + *************************************************************************/ + always @(m_match_addr_i) + if (c_addr_type==const_bin_encoded) + match_addr_i = binary_match_encoder(m_match_addr_i); + else + match_addr_i = m_match_addr_i; + + + +/************************************************************************* + * The internal write values (wr_data_mask and wr_din) are set asynchronously + * when din_i and data_mask_i changes, but once a write operation starts, + * they are connected to their registered values, to hold the data valid + * until the write operation is complete. + *************************************************************************/ + +always @(din_i or din_q or data_mask_i or data_mask_q or wr_addr_i or wr_addr_q or we_i or busy_i) + if (we_i==1 && busy_i==0) + begin + wr_data_mask <= data_mask_i; + wr_din <= din_i; + wr_addr_int <= wr_addr_i; + end + else + begin + wr_data_mask <= data_mask_q; + wr_din <= din_q; + wr_addr_int <= wr_addr_q; + end // else: !if(we_i==1 && busy_i==0) + + +assign wren = we_i | busy_i; + + +/************************************************************************* + * PROCESS: proc_inputs + * + * DESCRIPTION: + * Register the input values to hold them during processing. + *************************************************************************/ +always @(posedge CLK) + begin + if (en_i==1 && we_i==1 && busy_i==0) + begin + data_mask_q <= data_mask_i; + din_q <= din_i; + wr_addr_q <= wr_addr_i; + end + end + + + + +/************************************************************************* + * PROCESS: main + * + * DESCRIPTION: + * This process, on the rising edge of the clock, uses a case statement + * to identify the current state. + * In these blocks, the outputs for that CAM state are calculated. + * This implements a MEALY machine, where the outputs are set on each state + * transition according to the current state and the inputs. + *************************************************************************/ + +always @(posedge CLK) + begin + if (en_i) + case (CAM_MODE) + + /**************************************************************** + * READ MODE - CAM's normal state, searching for matches + ***************************************************************/ + READ_MODE: + if (we_i == 0) + // IF continuing to read + begin + busy_i <= 1'b0; + read_warning_i <= 1'b0; + write_counter <= 0; + end + else + // ELSE starting a write + begin + if ((c_ternary_mode == const_ternary_off && binary_compare(wr_din, rd_din)) + || (c_ternary_mode == const_ternary_std + && ternary_compare(wr_data_mask, wr_din, rd_data_mask, rd_din)) + || (c_ternary_mode == const_ternary_enh + && ternary_compare_xy(wr_data_mask, wr_din, rd_data_mask, rd_din))) + + //IF read and write data match, flag a read warning + read_warning_i <= 1'b1; + else + read_warning_i <= 1'b0; + + busy_i <= 1'b1; //Set busy while writing + write_counter <= write_counter+1; //Start counting the clock + //cycles for the write + end + + + + + //************************************************************* + // START WRITE MODE - A write operation has been initiated + //************************************************************* + START_WRITE_MODE: + if (c_mem_type == const_block_mem) + + // IF block memory implementation + begin + busy_i <= 0; + write_counter <= write_counter+1; + if ((c_ternary_mode == const_ternary_off && binary_compare(wr_din, rd_din)) + || (c_ternary_mode == const_ternary_std + && ternary_compare(wr_data_mask, wr_din, rd_data_mask, rd_din)) + || (c_ternary_mode == const_ternary_enh + && ternary_compare_xy(wr_data_mask, wr_din, rd_data_mask, rd_din))) + //IF read and write data match, flag a read warning + read_warning_i <= 1; + else + read_warning_i <= 0; + + // Update the contents of the CAM with the value being written + if (c_ternary_mode) + begin + cam_data[wr_addr_int] <= wr_din; + cam_mask[wr_addr_int] <= wr_data_mask; + end + else + cam_data[wr_addr_int] <= wr_din; + end + + else //c_mem_type=const_srl16 + + // ELSE srl16 implementation + begin + if ((c_ternary_mode == const_ternary_off && binary_compare(wr_din, rd_din)) + || (c_ternary_mode == const_ternary_std + && ternary_compare(wr_data_mask, wr_din, rd_data_mask, rd_din)) + || (c_ternary_mode == const_ternary_enh + && ternary_compare_xy(wr_data_mask, wr_din, rd_data_mask, rd_din))) + //IF read and write data match, flag a read warning + read_warning_i <= 1; + else + read_warning_i <= 0; + + busy_i <= 1;//Set busy while writing + write_counter <= write_counter+1;// Count clock cyles for the + // write + end + + + //************************************************************* + // END BLK WR MODE - Last cycle of a block-memory write operation + //************************************************************* + END_BLK_WR_MODE: + if (we_i == 0) + // IF ending the write operation and going into read_mode + begin + busy_i <= 0; + read_warning_i <= 0; + write_counter <= 0; + end + else + // ELSE starting another write operation immediately + begin + if ((c_ternary_mode == const_ternary_off && binary_compare(wr_din, rd_din)) + || (c_ternary_mode == const_ternary_std + && ternary_compare(wr_data_mask, wr_din, rd_data_mask, rd_din)) + || (c_ternary_mode == const_ternary_enh + && ternary_compare_xy(wr_data_mask, wr_din, rd_data_mask, rd_din))) + + //IF read and write data match, flag a read warning + read_warning_i <= 1; + else + read_warning_i <= 0; + + busy_i <= 1;//Set busy while writing + write_counter <= 1; + end // else: !ifwe_i + + + + + + //************************************************************* + // BUSY_SRL_WR_MODE - Middle of a SRL16 write operation + //************************************************************* + BUSY_SRL_WR_MODE: + begin + if ((c_ternary_mode == const_ternary_off && binary_compare(wr_din, rd_din)) + || (c_ternary_mode == const_ternary_std + && ternary_compare(wr_data_mask, wr_din, rd_data_mask, rd_din)) + || (c_ternary_mode == const_ternary_enh + && ternary_compare_xy(wr_data_mask, wr_din, rd_data_mask, rd_din))) + //IF read and write data match, flag a read warning + read_warning_i <= 1; + else + read_warning_i <= 0; + + busy_i <= 1;//Set busy while writing + write_counter <= write_counter+1;// Count clock cyles for the + // write + end // case: BUSY_SRL_WR_MODE + + + + + //************************************************************* + // NEAR_SRL_END_WR_MODE - Next-to-last clock cycle for an SRL16 write + //************************************************************* + NEAR_SRL_END_WR_MODE: + begin + if ((c_ternary_mode == const_ternary_off && binary_compare(wr_din, rd_din)) + || (c_ternary_mode == const_ternary_std + && ternary_compare(wr_data_mask, wr_din, rd_data_mask, rd_din)) + || (c_ternary_mode == const_ternary_enh + && ternary_compare_xy(wr_data_mask, wr_din, rd_data_mask, rd_din))) + //IF read and write data match, flag a read warning + read_warning_i <= 1; + else + read_warning_i <= 0; + + busy_i <= 0; + write_counter <= write_counter+1; + + // Update the contents of the CAM with the value being written + if (c_ternary_mode != const_ternary_off) + begin + cam_data[wr_addr_int] <= wr_din; + cam_mask[wr_addr_int] <= wr_data_mask; + end + else + cam_data[wr_addr_int] <= wr_din; + + end + + + + //************************************************************* + // END_SRL_WR_MODE - Last cycle of a SRL16 write operation + //************************************************************* + END_SRL_WR_MODE: + if (we_i == 0) + // IF ending the write operation and going into read_mode + begin + busy_i <= 0; + read_warning_i <= 0; + write_counter <= 0; + end + else + // ELSE starting another write operation immediately + begin + if ((c_ternary_mode == const_ternary_off && binary_compare(wr_din, rd_din)) + || (c_ternary_mode == const_ternary_std + && ternary_compare(wr_data_mask, wr_din, rd_data_mask, rd_din)) + || (c_ternary_mode == const_ternary_enh + && ternary_compare_xy(wr_data_mask, wr_din, rd_data_mask, rd_din))) + //IF read and write data match, flag a read warning + read_warning_i <= 1; + else + read_warning_i <= 0; + + busy_i <= 1;//Set busy while writing + write_counter <= 1; + end + + + endcase // case(CAM_MODE) + + end // always @ (posedge CLK) + + + + + + +endmodule // CAM_V6_1 + + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/C_ACCUM_V4_0.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/C_ACCUM_V4_0.v new file mode 100644 index 0000000..48c9eb3 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/C_ACCUM_V4_0.v @@ -0,0 +1,629 @@ +/* $Id: C_ACCUM_V4_0.v,v 1.11 2008/09/08 20:05:45 akennedy Exp $ +-- +-- Filename - C_ACCUM_V4_0.v +-- Author - Xilinx +-- Creation - 15 July 1999 +-- +-- Description - This file contains the Verilog behavior for the Baseblocks C_ACCUM_V4_0 module +*/ + + + + +`define c_set 0 +`define c_clear 1 +`define c_override 0 +`define c_no_override 1 +`define c_add 0 +`define c_sub 1 +`define c_add_sub 2 +`define c_signed 0 +`define c_unsigned 1 +`define c_pin 2 +`define allUKs {(C_HIGH_BIT-C_LOW_BIT)+1{1'bx}} + +module C_ACCUM_V4_0 (B, CLK, ADD, C_IN, B_IN, CE, BYPASS, ACLR, ASET, AINIT, + SCLR, SSET, SINIT, B_SIGNED, OVFL, C_OUT, B_OUT, + Q_OVFL, Q_C_OUT, Q_B_OUT, S, Q); + + parameter C_ADD_MODE = `c_add; + parameter C_AINIT_VAL = ""; + parameter C_BYPASS_ENABLE = `c_override; + parameter C_BYPASS_LOW = 0; + parameter C_B_CONSTANT = 0; + parameter C_B_TYPE = `c_unsigned; + parameter C_B_VALUE = ""; + parameter C_B_WIDTH = 16; + parameter C_ENABLE_RLOCS = 1; + parameter C_HAS_ACLR = 0; + parameter C_HAS_ADD = 0; + parameter C_HAS_AINIT = 0; + parameter C_HAS_ASET = 0; + parameter C_HAS_BYPASS = 0; + parameter C_HAS_B_IN = 1; + parameter C_HAS_B_OUT = 0; + parameter C_HAS_B_SIGNED = 0; + parameter C_HAS_CE = 0; + parameter C_HAS_C_IN = 1; + parameter C_HAS_C_OUT = 0; + parameter C_HAS_OVFL = 0; + parameter C_HAS_Q_B_OUT = 0; + parameter C_HAS_Q_C_OUT = 0; + parameter C_HAS_Q_OVFL = 0; + parameter C_HAS_S = 0; + parameter C_HAS_SCLR = 0; + parameter C_HAS_SINIT = 0; + parameter C_HAS_SSET = 0; + parameter C_HIGH_BIT = 15; + parameter C_LOW_BIT = 0; + parameter C_OUT_WIDTH = 16; + parameter C_PIPE_STAGES = 1; + parameter C_SATURATE = 0; + parameter C_SCALE = 0; + parameter C_SINIT_VAL = ""; + parameter C_SYNC_ENABLE = `c_override; + parameter C_SYNC_PRIORITY = `c_clear; + + // Only for internal consumption (prob with MTI otherwise) + parameter outwidth_min_one = C_OUT_WIDTH-1; + parameter bwidth_min_one = C_B_WIDTH-1; + + input [C_B_WIDTH-1 : 0] B; + input CLK; + input ADD; + input C_IN; + input B_IN; + input CE; + input BYPASS; + input ACLR; + input ASET; + input AINIT; + input SCLR; + input SSET; + input SINIT; + input B_SIGNED; + output OVFL; + output C_OUT; + output B_OUT; + output Q_OVFL; + output Q_C_OUT; + output Q_B_OUT; + output [C_HIGH_BIT : C_LOW_BIT] S; + output [C_HIGH_BIT : C_LOW_BIT] Q; + + + // Internal values to drive signals when input is missing + wire [C_OUT_WIDTH-1 : 0] intS; + wire [C_OUT_WIDTH-1 : 0] intS_sat0; + wire [C_OUT_WIDTH-1 : 0] intS_unsat1; + wire [C_OUT_WIDTH-1 : 0] intS_sinsat1; + wire [C_OUT_WIDTH-1 : 0] intFB; + wire [C_OUT_WIDTH-1 : 0] intFBq; + wire [C_OUT_WIDTH-1 : 0] intFBq_sat0; + wire [C_OUT_WIDTH-1 : 0] intFBq_unsat1; + wire [C_OUT_WIDTH-1 : 0] intFBq_sinsat1; + wire intSCLR; + wire intSSET; + wire intSCLR_TO_ADDER; + wire intSSET_TO_ADDER; + wire intSCLR_TO_MSB; + wire intSSET_TO_MSB; + wire intSCLR_TO_REST; + wire intSSET_TO_REST; + wire intB_SIGNED; + wire intBYPASSbar; + wire intC_OUT; + wire intB_OUT; + wire Q_C_OUT; + wire Q_B_OUT; + wire OVFL; + wire Q_OVFL; + wire intC_OUT_sat0; + wire intB_OUT_sat0; + wire Q_C_OUT_sat0; + wire Q_B_OUT_sat0; + wire OVFL_sat0; + wire Q_OVFL_sat0; + wire intC_OUT_unsat1; + wire intB_OUT_unsat1; + wire Q_C_OUT_unsat1; + wire Q_B_OUT_unsat1; + wire OVFL_unsat1; + wire Q_OVFL_unsat1; + wire intC_OUT_sinsat1; + wire intB_OUT_sinsat1; + wire Q_C_OUT_sinsat1; + wire Q_B_OUT_sinsat1; + wire OVFL_sinsat1; + wire Q_OVFL_sinsat1; + + wire tmpsetsatlogic_un00; + wire tmpsetsatlogic_un01; + wire tmpsetsatlogic_un10; + wire tmpsetsatlogic_un11c; + wire tmpsetsatlogic_un11s; + + wire tmpclrsatlogic_un00; + wire tmpclrsatlogic_un01; + wire tmpclrsatlogic_un10; + wire tmpclrsatlogic_un11c; + wire tmpclrsatlogic_un11s; + + wire tmpsetsatlogicmsb_sg00; + wire tmpsetsatlogicmsb_sg01; + wire tmpsetsatlogicmsb_sg10; + wire tmpsetsatlogicmsb_sg11c; + wire tmpsetsatlogicmsb_sg11s; + + wire tmpsetsatlogicrest_sg00; + wire tmpsetsatlogicrest_sg01; + wire tmpsetsatlogicrest_sg10; + wire tmpsetsatlogicrest_sg11c; + wire tmpsetsatlogicrest_sg11s; + + wire tmpclrsatlogicmsb_sg00; + wire tmpclrsatlogicmsb_sg01; + wire tmpclrsatlogicmsb_sg10; + wire tmpclrsatlogicmsb_sg11c; + wire tmpclrsatlogicmsb_sg11s; + + wire tmpclrsatlogicrest_sg00; + wire tmpclrsatlogicrest_sg01; + wire tmpclrsatlogicrest_sg10; + wire tmpclrsatlogicrest_sg11c; + wire tmpclrsatlogicrest_sg11s; + + wire addsetBaseSig ; + wire subsetBaseSig ; + wire addsubsetBaseSig ; + wire addclrBaseSig ; + wire subclrBaseSig ; + wire addsubclrBaseSig ; + + wire addsetBasePin ; + wire subsetBasePin ; + wire addsubsetBasePin ; + wire addclrBasePin ; + wire subclrBasePin ; + wire addsubclrBasePin ; + + wire addsetBase ; + wire subsetBase ; + wire addsubsetBase ; + wire addclrBase ; + wire subclrBase ; + wire addsubclrBase ; + + wire intCE ; + wire intB ; + + wire [C_HIGH_BIT : C_LOW_BIT] Q = intFBq; + wire [C_HIGH_BIT : C_LOW_BIT] S = (C_HAS_S == 1 ? intS : `allUKs); + wire C_OUT = (C_HAS_C_OUT == 1 ? intC_OUT : 1'bx); + wire B_OUT = (C_HAS_B_OUT == 1 ? intB_OUT : 1'bx); + + + // Sort out default values for missing ports + + assign intB_SIGNED = defval(B_SIGNED, C_HAS_B_SIGNED, 0); + assign intBYPASSbar = (C_BYPASS_LOW == 1 ? BYPASS : ~BYPASS); + assign intSCLR = defval(SCLR, C_HAS_SCLR, 0); + assign intSSET = defval(SSET, C_HAS_SSET, 0); + + // Now make up the design from other baseblox + // An addsub for when no saturation logic is required... + C_ADDSUB_V4_0 #(C_ADD_MODE, + C_AINIT_VAL, + (C_B_TYPE == `c_pin )? `c_signed : C_B_TYPE, + C_OUT_WIDTH, + C_BYPASS_ENABLE, + C_BYPASS_LOW, + C_B_CONSTANT, + C_B_TYPE, + C_B_VALUE, + C_B_WIDTH, + C_ENABLE_RLOCS, + C_HAS_ACLR, + C_HAS_ADD, + C_HAS_AINIT, + C_HAS_ASET, + C_HAS_B_SIGNED, + C_HAS_BYPASS, + C_HAS_B_IN, + C_HAS_B_OUT, + C_HAS_B_SIGNED, + C_HAS_CE, + C_HAS_C_IN, + C_HAS_C_OUT, + C_HAS_OVFL, + 1, + C_HAS_Q_B_OUT, + C_HAS_Q_C_OUT, + C_HAS_Q_OVFL, + C_HAS_S, + C_HAS_SCLR, + C_HAS_SINIT, + C_HAS_SSET, + outwidth_min_one, + 1, + 0, + C_OUT_WIDTH, + C_PIPE_STAGES, + C_SINIT_VAL, + C_SYNC_ENABLE, + C_SYNC_PRIORITY) + sat0_addsub(.A(intFB), .B(B), .CLK(CLK), .ADD(ADD), + .C_IN(C_IN), .B_IN(B_IN), .CE(CE), .BYPASS(BYPASS), + .ACLR(ACLR), .ASET(ASET), .AINIT(AINIT), + .SCLR(SCLR), .SSET(SSET), .SINIT(SINIT), + .A_SIGNED(B_SIGNED), .B_SIGNED(B_SIGNED), + .OVFL(OVFL_sat0), .C_OUT(intC_OUT_sat0), + .B_OUT(intB_OUT_sat0), .Q_OVFL(Q_OVFL_sat0), + .Q_C_OUT(Q_C_OUT_sat0), .Q_B_OUT(Q_B_OUT_sat0), + .S(intS_sat0), .Q(intFBq_sat0)); + + + // Another addsub for when saturation logic IS required, but only for unsigned data + C_ADDSUB_V4_0 #(C_ADD_MODE, + C_AINIT_VAL, + C_B_TYPE, + C_OUT_WIDTH, + C_BYPASS_ENABLE, + C_BYPASS_LOW, + C_B_CONSTANT, + C_B_TYPE, + C_B_VALUE, + C_B_WIDTH, + C_ENABLE_RLOCS, + 0, + C_HAS_ADD, + 0, + 0, + C_HAS_B_SIGNED, + C_HAS_BYPASS, + C_HAS_B_IN, + 1, + C_HAS_B_SIGNED, + C_HAS_CE, + C_HAS_C_IN, + 1, + C_HAS_OVFL, + 1, + C_HAS_Q_B_OUT, + C_HAS_Q_C_OUT, + C_HAS_Q_OVFL, + C_HAS_S, + 1, + 0, + 1, + outwidth_min_one, + 1, + 0, + C_OUT_WIDTH, + C_PIPE_STAGES, + C_SINIT_VAL, + C_SYNC_ENABLE, + C_SYNC_PRIORITY) + unsat1_addsub(.A(intFB), .B(B), .CLK(CLK), .ADD(ADD), + .C_IN(C_IN), .B_IN(B_IN), .CE(CE), .BYPASS(BYPASS), + .ACLR(ACLR), .ASET(ASET), .AINIT(AINIT), + .SCLR(intSCLR_TO_ADDER), .SSET(intSSET_TO_ADDER), .SINIT(SINIT), + .A_SIGNED(B_SIGNED), .B_SIGNED(B_SIGNED), + .OVFL(OVFL_unsat1), .C_OUT(intC_OUT_unsat1), + .B_OUT(intB_OUT_unsat1), .Q_OVFL(Q_OVFL_unsat1), + .Q_C_OUT(Q_C_OUT_unsat1), .Q_B_OUT(Q_B_OUT_unsat1), + .S(intS_unsat1), .Q(intFBq_unsat1)); + + // Another addsub for when saturation logic IS required, but for signed data + C_ADDSUB_V4_0 #(C_ADD_MODE, + C_AINIT_VAL, + C_B_TYPE, + C_OUT_WIDTH, + C_BYPASS_ENABLE, + C_BYPASS_LOW, + C_B_CONSTANT, + C_B_TYPE, + C_B_VALUE, + C_B_WIDTH, + C_ENABLE_RLOCS, + C_HAS_ACLR, + C_HAS_ADD, + C_HAS_AINIT, + C_HAS_ASET, + C_HAS_B_SIGNED, + C_HAS_BYPASS, + C_HAS_B_IN, + 1, + C_HAS_B_SIGNED, + C_HAS_CE, + C_HAS_C_IN, + 1, + C_HAS_OVFL, + 0, + C_HAS_Q_B_OUT, + C_HAS_Q_C_OUT, + C_HAS_Q_OVFL, + 1, + C_HAS_SCLR, + C_HAS_SINIT, + C_HAS_SSET, + outwidth_min_one, + 1, + 0, + C_OUT_WIDTH, + C_PIPE_STAGES, + C_SINIT_VAL, + C_SYNC_ENABLE, + C_SYNC_PRIORITY) + sinsat1_addsub(.A(intFB), .B(B), .CLK(CLK), .ADD(ADD), + .C_IN(C_IN), .B_IN(B_IN), .CE(CE), .BYPASS(BYPASS), + .ACLR(ACLR), .ASET(ASET), .AINIT(AINIT), + .SCLR(SCLR), .SSET(SSET), .SINIT(SINIT), + .A_SIGNED(B_SIGNED), .B_SIGNED(B_SIGNED), + .OVFL(OVFL_sinsat1), .C_OUT(intC_OUT_sinsat1), + .B_OUT(intB_OUT_sinsat1), .Q_OVFL(Q_OVFL_sinsat1), + .Q_C_OUT(Q_C_OUT_sinsat1), .Q_B_OUT(Q_B_OUT_sinsat1), + .S(intS_sinsat1)); + + // Registers for output of the last addsub + C_REG_FD_V4_0 #(C_AINIT_VAL[(C_OUT_WIDTH*8)-1 : (C_OUT_WIDTH-1)*8], + C_ENABLE_RLOCS, + 0, + 0, + 0, + C_HAS_CE, + 1, + 0, + 1, + C_SINIT_VAL[(C_OUT_WIDTH*8)-1 : (C_OUT_WIDTH-1)*8], + C_SYNC_ENABLE, + C_SYNC_PRIORITY, + 1) + msb_reg(.D(intS_sinsat1[outwidth_min_one]), .CLK(CLK), + .CE(intCE), .ACLR(ACLR), .ASET(ASET), .AINIT(AINIT), + .SCLR(intSCLR_TO_MSB), .SSET(intSSET_TO_MSB), + .SINIT(SINIT), .Q(intFBq_sinsat1[outwidth_min_one])); + + // Need the ?: on the value of C_B_WIDTH in case it == 1 + C_REG_FD_V4_0 #(C_AINIT_VAL[(((C_OUT_WIDTH == 1 ? 2 : C_OUT_WIDTH)-1)*8)-1 : 0], + C_ENABLE_RLOCS, + 0, + 0, + 0, + C_HAS_CE, + 1, + 0, + 1, + C_SINIT_VAL[(((C_OUT_WIDTH == 1 ? 2 : C_OUT_WIDTH)-1)*8)-1 : 0], + C_SYNC_ENABLE, + C_SYNC_PRIORITY, + (C_OUT_WIDTH == 1 ? 2 : C_OUT_WIDTH)-1) + rest_reg(.D(intS_sinsat1[(C_OUT_WIDTH == 1 ? 2 : C_OUT_WIDTH)-2 : 0]), .CLK(CLK), + .CE(intCE), .ACLR(ACLR), .ASET(ASET), .AINIT(AINIT), + .SCLR((C_B_WIDTH == 1 ? intSCLR_TO_MSB : intSCLR_TO_REST)), .SSET((C_B_WIDTH == 1 ? intSSET_TO_MSB : intSSET_TO_REST)), + .SINIT(SINIT), .Q(intFBq_sinsat1[(C_OUT_WIDTH == 1 ? 2 : C_OUT_WIDTH)-2 : 0])); + + + // Sort out the choices from all these output signals... + assign intCE = (C_SATURATE == 0 ? CE : (((C_HAS_BYPASS == 1)&&(C_BYPASS_LOW == 1)) ? ((C_BYPASS_ENABLE == `c_no_override) ? (~BYPASS | CE) : CE) : (((C_HAS_BYPASS == 1)&&(C_BYPASS_LOW == 0)) ? ((C_BYPASS_ENABLE == `c_no_override) ? (BYPASS | CE) : CE) : CE))) ; + assign intC_OUT = (C_SATURATE == 0 ? intC_OUT_sat0 : (C_B_TYPE == `c_unsigned ? intC_OUT_unsat1 : intC_OUT_sinsat1)); + assign intB_OUT = (C_SATURATE == 0 ? intB_OUT_sat0 : (C_B_TYPE == `c_unsigned ? intB_OUT_unsat1 : intB_OUT_sinsat1)); + assign OVFL = (C_SATURATE == 0 ? OVFL_sat0 : (C_B_TYPE == `c_unsigned ? OVFL_unsat1 : OVFL_sinsat1)); + assign Q_C_OUT = (C_SATURATE == 0 ? Q_C_OUT_sat0 : (C_B_TYPE == `c_unsigned ? Q_C_OUT_unsat1 : Q_C_OUT_sinsat1)); + assign Q_B_OUT = (C_SATURATE == 0 ? Q_B_OUT_sat0 : (C_B_TYPE == `c_unsigned ? Q_B_OUT_unsat1 : Q_B_OUT_sinsat1)); + assign Q_OVFL = (C_SATURATE == 0 ? Q_OVFL_sat0 : (C_B_TYPE == `c_unsigned ? Q_OVFL_unsat1 : Q_OVFL_sinsat1)); + assign intS = (C_SATURATE == 0 ? intS_sat0 : (C_B_TYPE == `c_unsigned ? intS_unsat1 : intS_sinsat1)); + assign intFBq = (C_SATURATE == 0 ? intFBq_sat0 : (C_B_TYPE == `c_unsigned ? intFBq_unsat1 : intFBq_sinsat1)); + + + // COMPLEX decisions on what to feed to the local control sigs... + // The signal name suffices denote: un = unsigned, sg = signed, 00 = has neither sset nor sclr, 01 = has sclr only etc + // 11c = has bot sset and sclr and sclr dominates, 11s = sset dominates, etc + + // Unsigned version first + assign tmpsetsatlogic_un00 = (C_ADD_MODE == `c_add ? intC_OUT : (C_ADD_MODE == `c_sub ? intSSET : (intC_OUT & ADD))); + assign tmpsetsatlogic_un01 = (C_ADD_MODE == `c_add ? (intC_OUT & ~intSCLR) : (C_ADD_MODE == `c_sub ? intSSET : (intC_OUT & ~intSCLR & ADD))); + assign tmpsetsatlogic_un10 = (C_ADD_MODE == `c_add ? (intC_OUT | intSSET) : (C_ADD_MODE == `c_sub ? intSSET : ((intC_OUT & ADD) | intSSET))); + assign tmpsetsatlogic_un11c = (C_ADD_MODE == `c_add ? (~intSCLR & (intC_OUT | intSSET)) : (C_ADD_MODE == `c_sub ? (~intSCLR & intSSET) : ((~intSCLR & intC_OUT & ADD) | (intSSET & ~intSCLR)))); + assign tmpsetsatlogic_un11s = (C_ADD_MODE == `c_add ? (intC_OUT | intSSET) : (C_ADD_MODE == `c_sub ? intSSET : ((~intSCLR & intC_OUT & ADD) | intSSET))); + + assign tmpclrsatlogic_un00 = (C_ADD_MODE == `c_add ? intSCLR : (C_ADD_MODE == `c_sub ? ~intB_OUT : (~intC_OUT & ~ADD))); + assign tmpclrsatlogic_un01 = (C_ADD_MODE == `c_add ? intSCLR : (C_ADD_MODE == `c_sub ? (~intB_OUT | intSCLR) : (intSCLR | (~intC_OUT & ~ADD)))); + assign tmpclrsatlogic_un10 = (C_ADD_MODE == `c_add ? intSCLR : (C_ADD_MODE == `c_sub ? (~intB_OUT & ~intSSET) : (~intSSET & ~intC_OUT & ~ADD))); + assign tmpclrsatlogic_un11c = (C_ADD_MODE == `c_add ? intSCLR : (C_ADD_MODE == `c_sub ? (intSCLR | (~intB_OUT & ~intSSET)) : (intSCLR | (~intSSET & ~intC_OUT & ~ADD)))); + assign tmpclrsatlogic_un11s = (C_ADD_MODE == `c_add ? (intSCLR & ~intSSET) : (C_ADD_MODE == `c_sub ? (~intSSET & (intSCLR | ~intB_OUT)) : ((intSCLR & ~intSSET) | (~intSSET & ~intC_OUT & ~ADD)))); + + assign intSSET_TO_ADDER = (C_HAS_SSET == 0 ? (C_HAS_SCLR == 0 ? tmpsetsatlogic_un00 : tmpsetsatlogic_un01) : + (C_HAS_SCLR == 0 ? tmpsetsatlogic_un10 : + (C_SYNC_PRIORITY == `c_clear ? tmpsetsatlogic_un11c : tmpsetsatlogic_un11s))); + + assign intSCLR_TO_ADDER = (C_HAS_SSET == 0 ? (C_HAS_SCLR == 0 ? tmpclrsatlogic_un00 : tmpclrsatlogic_un01) : + (C_HAS_SCLR == 0 ? tmpclrsatlogic_un10 : + (C_SYNC_PRIORITY == `c_clear ? tmpclrsatlogic_un11c : tmpclrsatlogic_un11s))); + + // Now all the signals for the signed version + assign intB = (C_B_CONSTANT == 1 ? (C_B_VALUE[(C_B_WIDTH*8)-1 : (C_B_WIDTH-1)*8] == "0" ? 1'b0 : 1'b1) : B[C_B_WIDTH-1]) ; + assign addclrBaseSig = (intS[C_HIGH_BIT] & ~(intFBq[C_HIGH_BIT]) & ~(intB)) ; + assign addsetBaseSig = (~(intS[C_HIGH_BIT]) & intFBq[C_HIGH_BIT] & intB) ; + assign subclrBaseSig = (intS[C_HIGH_BIT] & ~(intFBq[C_HIGH_BIT]) & intB) ; + assign subsetBaseSig = (~(intS[C_HIGH_BIT]) & intFBq[C_HIGH_BIT] & ~(intB)) ; + assign addsubclrBaseSig = ((~ADD & (intS[C_HIGH_BIT] & ~(intFBq[C_HIGH_BIT]) & intB)) | (ADD & (intS[C_HIGH_BIT] & ~(intFBq[C_HIGH_BIT]) & ~(intB)))) ; + assign addsubsetBaseSig = ((~ADD & (~(intS[C_HIGH_BIT]) & intFBq[C_HIGH_BIT] & ~(intB))) | (ADD & (~(intS[C_HIGH_BIT]) & intFBq[C_HIGH_BIT] & intB))) ; + + assign addclrBasePin = (~(intB_SIGNED) & ~(intFBq[C_HIGH_BIT]) & intS[C_HIGH_BIT]) | (intB_SIGNED & ~(intFBq[C_HIGH_BIT]) & intS[C_HIGH_BIT] & ~(intB)); + assign addsetBasePin = (intB_SIGNED & intFBq[C_HIGH_BIT] & ~(intS[C_HIGH_BIT]) & intB) ; + assign subclrBasePin = (intB_SIGNED & ~(intFBq[C_HIGH_BIT]) & intS[C_HIGH_BIT] & intB); + assign subsetBasePin = (~(intB_SIGNED) & intFBq[C_HIGH_BIT] & ~(intS[C_HIGH_BIT])) | (intB_SIGNED & intFBq[C_HIGH_BIT] & ~(intS[C_HIGH_BIT]) & ~(intB)); + assign addsubclrBasePin = (~(ADD) & (intB_SIGNED & ~(intFBq[C_HIGH_BIT]) & intS[C_HIGH_BIT] & intB)) | (ADD & ((~(intB_SIGNED) & ~(intFBq[C_HIGH_BIT]) & intS[C_HIGH_BIT]) | (intB_SIGNED & ~(intFBq[C_HIGH_BIT]) & intS[C_HIGH_BIT] & ~(intB)))) ; + assign addsubsetBasePin = (~(ADD) & ((~intB_SIGNED & intFBq[C_HIGH_BIT] & ~(intS[C_HIGH_BIT])) | (intB_SIGNED & intFBq[C_HIGH_BIT] & ~intS[C_HIGH_BIT] & ~intB))) | (ADD & intB_SIGNED & intFBq[C_HIGH_BIT] & ~intS[C_HIGH_BIT] & intB) ; + + assign addclrBase = (C_HAS_B_SIGNED == 0 ? addclrBaseSig : addclrBasePin); + assign addsetBase = (C_HAS_B_SIGNED == 0 ? addsetBaseSig : addsetBasePin); + assign subclrBase = (C_HAS_B_SIGNED == 0 ? subclrBaseSig : subclrBasePin); + assign subsetBase = (C_HAS_B_SIGNED == 0 ? subsetBaseSig : subsetBasePin); + assign addsubclrBase = (C_HAS_B_SIGNED == 0 ? addsubclrBaseSig : addsubclrBasePin); + assign addsubsetBase = (C_HAS_B_SIGNED == 0 ? addsubsetBaseSig : addsubsetBasePin); + + assign tmpsetsatlogicmsb_sg00 = (C_ADD_MODE == `c_add ? (C_HAS_BYPASS == 1 ? addsetBase & intBYPASSbar : addsetBase) : (C_ADD_MODE == `c_sub ? (C_HAS_BYPASS == 1 ? subsetBase & intBYPASSbar : subsetBase) : (C_HAS_BYPASS == 1 ? addsubsetBase & intBYPASSbar : addsubsetBase) )); + assign tmpsetsatlogicmsb_sg01 = tmpsetsatlogicmsb_sg00 & ~intSCLR ; + assign tmpsetsatlogicmsb_sg10 = tmpsetsatlogicmsb_sg00 | intSSET ; + assign tmpsetsatlogicmsb_sg11c = (tmpsetsatlogicmsb_sg00 | intSSET) & ~intSCLR ; + assign tmpsetsatlogicmsb_sg11s = tmpsetsatlogicmsb_sg00 | intSSET ; + + assign tmpsetsatlogicrest_sg00 = (C_ADD_MODE == `c_add ? (C_HAS_BYPASS == 1 ? addclrBase & intBYPASSbar : addclrBase) : (C_ADD_MODE == `c_sub ? (C_HAS_BYPASS == 1 ? subclrBase & intBYPASSbar : subclrBase) : (C_HAS_BYPASS == 1 ? addsubclrBase & intBYPASSbar : addsubclrBase) )); + assign tmpsetsatlogicrest_sg01 = tmpsetsatlogicrest_sg00 & ~intSCLR ; + assign tmpsetsatlogicrest_sg10 = tmpsetsatlogicrest_sg00 | intSSET ; + assign tmpsetsatlogicrest_sg11c = (tmpsetsatlogicrest_sg00 | intSSET) & ~intSCLR ; + assign tmpsetsatlogicrest_sg11s = tmpsetsatlogicrest_sg00 | intSSET ; + + assign tmpclrsatlogicmsb_sg00 = tmpsetsatlogicrest_sg00 ; + assign tmpclrsatlogicmsb_sg01 = tmpsetsatlogicrest_sg00 | intSCLR ; + assign tmpclrsatlogicmsb_sg10 = tmpsetsatlogicrest_sg00 & ~intSSET ; + assign tmpclrsatlogicmsb_sg11c = tmpsetsatlogicrest_sg00 | intSCLR ; + assign tmpclrsatlogicmsb_sg11s = (tmpsetsatlogicrest_sg00 | intSCLR) & ~intSSET ; + + assign tmpclrsatlogicrest_sg00 = tmpsetsatlogicmsb_sg00 ; + assign tmpclrsatlogicrest_sg01 = tmpsetsatlogicmsb_sg00 | intSCLR ; + assign tmpclrsatlogicrest_sg10 = tmpsetsatlogicmsb_sg00 & ~intSSET ; + assign tmpclrsatlogicrest_sg11c = tmpsetsatlogicmsb_sg00 | intSCLR ; + assign tmpclrsatlogicrest_sg11s = (tmpsetsatlogicmsb_sg00 | intSCLR) & ~intSSET ; + + assign intSSET_TO_MSB = (C_HAS_SSET == 0 ? (C_HAS_SCLR == 0 ? tmpsetsatlogicmsb_sg00 : tmpsetsatlogicmsb_sg01) : + (C_HAS_SCLR == 0 ? tmpsetsatlogicmsb_sg10 : + (C_SYNC_PRIORITY == `c_clear ? tmpsetsatlogicmsb_sg11c : tmpsetsatlogicmsb_sg11s))); + + assign intSCLR_TO_MSB = (C_HAS_SSET == 0 ? (C_HAS_SCLR == 0 ? tmpclrsatlogicmsb_sg00 : tmpclrsatlogicmsb_sg01) : + (C_HAS_SCLR == 0 ? tmpclrsatlogicmsb_sg10 : + (C_SYNC_PRIORITY == `c_clear ? tmpclrsatlogicmsb_sg11c : tmpclrsatlogicmsb_sg11s))); + + assign intSSET_TO_REST = (C_HAS_SSET == 0 ? (C_HAS_SCLR == 0 ? tmpsetsatlogicrest_sg00 : tmpsetsatlogicrest_sg01) : + (C_HAS_SCLR == 0 ? tmpsetsatlogicrest_sg10 : + (C_SYNC_PRIORITY == `c_clear ? tmpsetsatlogicrest_sg11c : tmpsetsatlogicrest_sg11s))); + + assign intSCLR_TO_REST = (C_HAS_SSET == 0 ? (C_HAS_SCLR == 0 ? tmpclrsatlogicrest_sg00 : tmpclrsatlogicrest_sg01) : + (C_HAS_SCLR == 0 ? tmpclrsatlogicrest_sg10 : + (C_SYNC_PRIORITY == `c_clear ? tmpclrsatlogicrest_sg11c : tmpclrsatlogicrest_sg11s))); + + // Finally we are ready to scale the feedback signal... + // If the scaling factor results in NO bits being fed back to the input then we need to handle this! + // This is the case if C_SCALE >= C_OUT_WIDTH + assign intFB[C_OUT_WIDTH-1-(C_SCALE >= C_OUT_WIDTH ? 0 : C_SCALE) : 0] = (C_SCALE >= C_OUT_WIDTH ? {C_OUT_WIDTH{1'b0}} : intFBq[C_OUT_WIDTH-1 : (C_SCALE >= C_OUT_WIDTH ? 0 : C_SCALE)]); + //assign intFB[C_OUT_WIDTH-1 : C_OUT_WIDTH-(C_SCALE == 0 ? 1 : C_SCALE)] = (C_SCALE == 0 ? intFBq[C_OUT_WIDTH-1] : (C_SCALE < C_OUT_WIDTH && (C_B_TYPE == `c_signed || (C_B_TYPE == `c_pin && intB_SIGNED === 1'b1)) ? + // {C_SCALE{intFBq[C_OUT_WIDTH-1]}} : {C_SCALE{1'b0}})); + assign intFB[C_OUT_WIDTH-1 : C_OUT_WIDTH-(C_SCALE == 0 ? 1 : C_SCALE)] = (C_SCALE == 0 ? intFBq[C_OUT_WIDTH-1] : (C_SCALE < C_OUT_WIDTH && (C_B_TYPE == `c_signed || C_B_TYPE == `c_pin) ? + {C_SCALE{intFBq[C_OUT_WIDTH-1]}} : {C_SCALE{1'b0}})); + + + + + initial + begin + #1; + end + + +/* helper functions */ + + function defval; + input i; + input hassig; + input val; + begin + if(hassig == 1) + defval = i; + else + defval = val; + end + endfunction + + function [C_B_WIDTH - 1 : 0] to_bitsB; + input [C_B_WIDTH*8 : 1] instring; + integer i; + integer non_null_string; + begin + non_null_string = 0; + for(i = C_B_WIDTH; i > 0; i = i - 1) + begin // Is the string empty? + if(instring[(i*8)] == 0 && + instring[(i*8)-1] == 0 && + instring[(i*8)-2] == 0 && + instring[(i*8)-3] == 0 && + instring[(i*8)-4] == 0 && + instring[(i*8)-5] == 0 && + instring[(i*8)-6] == 0 && + instring[(i*8)-7] == 0 && + non_null_string == 0) + non_null_string = 0; // Use the return value to flag a non-empty string + else + non_null_string = 1; // Non-null character! + end + if(non_null_string == 0) // String IS empty! Just return the value to be all '0's + begin + for(i = C_B_WIDTH; i > 0; i = i - 1) + to_bitsB[i-1] = 0; + end + else + begin + for(i = C_B_WIDTH; i > 0; i = i - 1) + begin // Is this character a '0'? (ASCII = 48 = 00110000) + if(instring[(i*8)] == 0 && + instring[(i*8)-1] == 0 && + instring[(i*8)-2] == 1 && + instring[(i*8)-3] == 1 && + instring[(i*8)-4] == 0 && + instring[(i*8)-5] == 0 && + instring[(i*8)-6] == 0 && + instring[(i*8)-7] == 0) + to_bitsB[i-1] = 0; + // Or is it a '1'? + else if(instring[(i*8)] == 0 && + instring[(i*8)-1] == 0 && + instring[(i*8)-2] == 1 && + instring[(i*8)-3] == 1 && + instring[(i*8)-4] == 0 && + instring[(i*8)-5] == 0 && + instring[(i*8)-6] == 0 && + instring[(i*8)-7] == 1) + to_bitsB[i-1] = 1; + // Or is it a ' '? (a null char - in which case insert a '0') + else if(instring[(i*8)] == 0 && + instring[(i*8)-1] == 0 && + instring[(i*8)-2] == 0 && + instring[(i*8)-3] == 0 && + instring[(i*8)-4] == 0 && + instring[(i*8)-5] == 0 && + instring[(i*8)-6] == 0 && + instring[(i*8)-7] == 0) + to_bitsB[i-1] = 0; + else + begin + $display("Error: non-binary digit in string \"%s\"\nExiting simulation...", instring); + $finish; + end + end + end + end + endfunction + + function max; + input a; + input b; + begin + max = (a > b) ? a : b; + end + endfunction + +endmodule + +`undef c_set +`undef c_clear +`undef c_override +`undef c_no_override +`undef c_add +`undef c_sub +`undef c_add_sub +`undef c_signed +`undef c_unsigned +`undef c_pin +`undef allUKs + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/C_ACCUM_V5_0.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/C_ACCUM_V5_0.v new file mode 100644 index 0000000..29745b6 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/C_ACCUM_V5_0.v @@ -0,0 +1,654 @@ +/* $Id: C_ACCUM_V5_0.v,v 1.17 2008/09/08 20:05:55 akennedy Exp $ +-- +-- Filename - C_ACCUM_V5_0.v +-- Author - Xilinx +-- Creation - 15 July 1999 +-- +-- Description - This file contains the Verilog behavior for the Baseblocks C_ACCUM_V5_0 module +*/ + +`timescale 1 ns/10 ps + +`define c_set 0 +`define c_clear 1 +`define c_override 0 +`define c_no_override 1 +`define c_add 0 +`define c_sub 1 +`define c_add_sub 2 +`define c_signed 0 +`define c_unsigned 1 +`define c_pin 2 +`define allUKs {(C_HIGH_BIT-C_LOW_BIT)+1{1'bx}} + +module C_ACCUM_V5_0 (B, CLK, ADD, C_IN, B_IN, CE, BYPASS, ACLR, ASET, AINIT, + SCLR, SSET, SINIT, B_SIGNED, OVFL, C_OUT, B_OUT, + Q_OVFL, Q_C_OUT, Q_B_OUT, S, Q); + + parameter C_ADD_MODE = `c_add; + parameter C_AINIT_VAL = "0000000000000000"; + parameter C_BYPASS_ENABLE = `c_override; + parameter C_BYPASS_LOW = 0; + parameter C_B_CONSTANT = 0; + parameter C_B_TYPE = `c_unsigned; + parameter C_B_VALUE = "0000000000000000"; + parameter C_B_WIDTH = 16; + parameter C_ENABLE_RLOCS = 1; + parameter C_HAS_ACLR = 1; + parameter C_HAS_ADD = 0; + parameter C_HAS_AINIT = 0; + parameter C_HAS_ASET = 0; + parameter C_HAS_BYPASS = 0; + parameter C_HAS_BYPASS_WITH_CIN = 0; + parameter C_HAS_B_IN = 1; + parameter C_HAS_B_OUT = 0; + parameter C_HAS_B_SIGNED = 0; + parameter C_HAS_CE = 1; + parameter C_HAS_C_IN = 1; + parameter C_HAS_C_OUT = 0; + parameter C_HAS_OVFL = 0; + parameter C_HAS_Q_B_OUT = 0; + parameter C_HAS_Q_C_OUT = 0; + parameter C_HAS_Q_OVFL = 0; + parameter C_HAS_S = 1; + parameter C_HAS_SCLR = 1; + parameter C_HAS_SINIT = 0; + parameter C_HAS_SSET = 0; + parameter C_HIGH_BIT = 15; + parameter C_LOW_BIT = 0; + parameter C_OUT_WIDTH = 16; + parameter C_PIPE_STAGES = 1; + parameter C_SATURATE = 0; + parameter C_SCALE = 1; + parameter C_SINIT_VAL = "0000000000000000"; + parameter C_SYNC_ENABLE = `c_override; + parameter C_SYNC_PRIORITY = `c_clear; + + // Only for internal consumption (prob with MTI otherwise) + parameter outwidth_min_one = C_OUT_WIDTH-1; + parameter bwidth_min_one = C_B_WIDTH-1; + + parameter tempSyncEnable = ((C_SYNC_ENABLE == 0 && C_HAS_CE == 1 && (C_HAS_SSET == 1 || C_HAS_SCLR == 1) && C_SATURATE == 1) ? 1 : C_SYNC_ENABLE); + + input [C_B_WIDTH-1 : 0] B; + input CLK; + input ADD; + input C_IN; + input B_IN; + input CE; + input BYPASS; + input ACLR; + input ASET; + input AINIT; + input SCLR; + input SSET; + input SINIT; + input B_SIGNED; + output OVFL; + output C_OUT; + output B_OUT; + output Q_OVFL; + output Q_C_OUT; + output Q_B_OUT; + output [C_HIGH_BIT : C_LOW_BIT] S; + output [C_HIGH_BIT : C_LOW_BIT] Q; + + + // Internal values to drive signals when input is missing + wire [C_OUT_WIDTH-1 : 0] intS; + wire [C_OUT_WIDTH-1 : 0] intS_sat0; + wire [C_OUT_WIDTH-1 : 0] intS_unsat1; + wire [C_OUT_WIDTH-1 : 0] intS_sinsat1; + wire [C_OUT_WIDTH-1 : 0] intFB; + wire [C_OUT_WIDTH-1 : 0] intFBq; + wire [C_OUT_WIDTH-1 : 0] intFBq_sat0; + wire [C_OUT_WIDTH-1 : 0] intFBq_unsat1; + wire [C_OUT_WIDTH-1 : 0] intFBq_sinsat1; + wire intSCLR; + wire intSSET; + wire intSCLR_TO_ADDER; + wire intSSET_TO_ADDER; + wire intSCLR_TO_MSB; + wire intSSET_TO_MSB; + wire intSCLR_TO_REST; + wire intSSET_TO_REST; + wire intB_SIGNED; + wire intBYPASSbar; + wire intC_OUT; + wire intB_OUT; + wire Q_C_OUT; + wire Q_B_OUT; + wire OVFL; + wire Q_OVFL; + wire intC_OUT_sat0; + wire intB_OUT_sat0; + wire Q_C_OUT_sat0; + wire Q_B_OUT_sat0; + wire OVFL_sat0; + wire Q_OVFL_sat0; + wire intC_OUT_unsat1; + wire intB_OUT_unsat1; + wire Q_C_OUT_unsat1; + wire Q_B_OUT_unsat1; + wire OVFL_unsat1; + wire Q_OVFL_unsat1; + wire intC_OUT_sinsat1; + wire intB_OUT_sinsat1; + wire Q_C_OUT_sinsat1; + wire Q_B_OUT_sinsat1; + wire OVFL_sinsat1; + wire Q_OVFL_sinsat1; + wire intBYPASS_WITH_CIN; // New signal for bypass with Cin mode + wire tempCE; + + + wire tmpsetsatlogic_un00; + wire tmpsetsatlogic_un01; + wire tmpsetsatlogic_un10; + wire tmpsetsatlogic_un11c; + wire tmpsetsatlogic_un11s; + + wire tmpclrsatlogic_un00; + wire tmpclrsatlogic_un01; + wire tmpclrsatlogic_un10; + wire tmpclrsatlogic_un11c; + wire tmpclrsatlogic_un11s; + + wire tmpsetsatlogicmsb_sg00; + wire tmpsetsatlogicmsb_sg01; + wire tmpsetsatlogicmsb_sg10; + wire tmpsetsatlogicmsb_sg11c; + wire tmpsetsatlogicmsb_sg11s; + + wire tmpsetsatlogicrest_sg00; + wire tmpsetsatlogicrest_sg01; + wire tmpsetsatlogicrest_sg10; + wire tmpsetsatlogicrest_sg11c; + wire tmpsetsatlogicrest_sg11s; + + wire tmpclrsatlogicmsb_sg00; + wire tmpclrsatlogicmsb_sg01; + wire tmpclrsatlogicmsb_sg10; + wire tmpclrsatlogicmsb_sg11c; + wire tmpclrsatlogicmsb_sg11s; + + wire tmpclrsatlogicrest_sg00; + wire tmpclrsatlogicrest_sg01; + wire tmpclrsatlogicrest_sg10; + wire tmpclrsatlogicrest_sg11c; + wire tmpclrsatlogicrest_sg11s; + + wire addsetBaseSig ; + wire subsetBaseSig ; + wire addsubsetBaseSig ; + wire addclrBaseSig ; + wire subclrBaseSig ; + wire addsubclrBaseSig ; + + wire addsetBasePin ; + wire subsetBasePin ; + wire addsubsetBasePin ; + wire addclrBasePin ; + wire subclrBasePin ; + wire addsubclrBasePin ; + + wire addsetBase ; + wire subsetBase ; + wire addsubsetBase ; + wire addclrBase ; + wire subclrBase ; + wire addsubclrBase ; + + wire intCE ; + wire intB ; + wire [C_B_WIDTH : 0] intBconst; + + wire [C_HIGH_BIT : C_LOW_BIT] Q = intFBq; + wire [C_HIGH_BIT : C_LOW_BIT] S = (C_HAS_S == 1 ? intS : `allUKs); + wire C_OUT = (C_HAS_C_OUT == 1 ? intC_OUT : 1'bx); + wire B_OUT = (C_HAS_B_OUT == 1 ? intB_OUT : 1'bx); + + + // Sort out default values for missing ports + + assign intB_SIGNED = defval(B_SIGNED, C_HAS_B_SIGNED, 0); + assign intBYPASSbar = (C_BYPASS_LOW == 1 ? BYPASS : ~BYPASS); + assign intSCLR = defval(SCLR, C_HAS_SCLR, 0); + assign intSSET = defval(SSET, C_HAS_SSET, 0); + assign intBYPASS_WITH_CIN = C_HAS_BYPASS_WITH_CIN; //assign new c_has_bypass_with_cin parameter to internal wire + assign intBconst = (C_B_CONSTANT === 1) ? to_bitsB(C_B_VALUE) : B; + + // Now make up the design from other baseblox + // An addsub for when no saturation logic is required... + C_ADDSUB_V5_0 #(C_ADD_MODE, + C_AINIT_VAL, + (C_B_TYPE == `c_pin )? `c_signed : C_B_TYPE, + C_OUT_WIDTH, + C_BYPASS_ENABLE, + C_BYPASS_LOW, + C_B_CONSTANT, + C_B_TYPE, + C_B_VALUE, + C_B_WIDTH, + C_ENABLE_RLOCS, + C_HAS_ACLR, + C_HAS_ADD, + C_HAS_AINIT, + C_HAS_ASET, + C_HAS_B_SIGNED, + C_HAS_BYPASS, + C_HAS_BYPASS_WITH_CIN, + C_HAS_B_IN, + C_HAS_B_OUT, + C_HAS_B_SIGNED, + C_HAS_CE, + C_HAS_C_IN, + C_HAS_C_OUT, + C_HAS_OVFL, + 1, + C_HAS_Q_B_OUT, + C_HAS_Q_C_OUT, + C_HAS_Q_OVFL, + C_HAS_S, + C_HAS_SCLR, + C_HAS_SINIT, + C_HAS_SSET, + outwidth_min_one, + 1, + 0, + C_OUT_WIDTH, + C_PIPE_STAGES, + C_SINIT_VAL, + C_SYNC_ENABLE, + C_SYNC_PRIORITY) + sat0_addsub(.A(intFB), .B(B), .CLK(CLK), .ADD(ADD), + .C_IN(C_IN), .B_IN(B_IN), .CE(CE), .BYPASS(BYPASS), + .ACLR(ACLR), .ASET(ASET), .AINIT(AINIT), + .SCLR(SCLR), .SSET(SSET), .SINIT(SINIT), + .A_SIGNED(B_SIGNED), .B_SIGNED(B_SIGNED), + .OVFL(OVFL_sat0), .C_OUT(intC_OUT_sat0), + .B_OUT(intB_OUT_sat0), .Q_OVFL(Q_OVFL_sat0), + .Q_C_OUT(Q_C_OUT_sat0), .Q_B_OUT(Q_B_OUT_sat0), + .S(intS_sat0), .Q(intFBq_sat0)); + + + // Another addsub for when saturation logic IS required, but only for unsigned data + C_ADDSUB_V5_0 #(C_ADD_MODE, + C_AINIT_VAL, + C_B_TYPE, + C_OUT_WIDTH, + C_BYPASS_ENABLE, + C_BYPASS_LOW, + C_B_CONSTANT, + C_B_TYPE, + C_B_VALUE, + C_B_WIDTH, + C_ENABLE_RLOCS, + 0, + C_HAS_ADD, + 0, + 0, + C_HAS_B_SIGNED, + C_HAS_BYPASS, + C_HAS_BYPASS_WITH_CIN, + C_HAS_B_IN, + 1, + C_HAS_B_SIGNED, + C_HAS_CE, + C_HAS_C_IN, + 1, + C_HAS_OVFL, + 1, + C_HAS_Q_B_OUT, + C_HAS_Q_C_OUT, + C_HAS_Q_OVFL, + C_HAS_S, + 1, + 0, + 1, + outwidth_min_one, + 1, + 0, + C_OUT_WIDTH, + C_PIPE_STAGES, + C_SINIT_VAL, + tempSyncEnable, + C_SYNC_PRIORITY) + unsat1_addsub(.A(intFB), .B(B), .CLK(CLK), .ADD(ADD), + .C_IN(C_IN), .B_IN(B_IN), .CE(intCE), .BYPASS(BYPASS), + .ACLR(ACLR), .ASET(ASET), .AINIT(AINIT), + .SCLR(intSCLR_TO_ADDER), .SSET(intSSET_TO_ADDER), .SINIT(SINIT), + .A_SIGNED(B_SIGNED), .B_SIGNED(B_SIGNED), + .OVFL(OVFL_unsat1), .C_OUT(intC_OUT_unsat1), + .B_OUT(intB_OUT_unsat1), .Q_OVFL(Q_OVFL_unsat1), + .Q_C_OUT(Q_C_OUT_unsat1), .Q_B_OUT(Q_B_OUT_unsat1), + .S(intS_unsat1), .Q(intFBq_unsat1)); + + // Another addsub for when saturation logic IS required, but for signed data + C_ADDSUB_V5_0 #(C_ADD_MODE, + C_AINIT_VAL, + C_B_TYPE, + C_OUT_WIDTH, + C_BYPASS_ENABLE, + C_BYPASS_LOW, + C_B_CONSTANT, + C_B_TYPE, + C_B_VALUE, + C_B_WIDTH, + C_ENABLE_RLOCS, + C_HAS_ACLR, + C_HAS_ADD, + C_HAS_AINIT, + C_HAS_ASET, + C_HAS_B_SIGNED, + C_HAS_BYPASS, + C_HAS_BYPASS_WITH_CIN, + C_HAS_B_IN, + 1, + C_HAS_B_SIGNED, + C_HAS_CE, + C_HAS_C_IN, + 1, + C_HAS_OVFL, + 0, + C_HAS_Q_B_OUT, + C_HAS_Q_C_OUT, + C_HAS_Q_OVFL, + 1, + C_HAS_SCLR, + C_HAS_SINIT, + C_HAS_SSET, + outwidth_min_one, + 1, + 0, + C_OUT_WIDTH, + C_PIPE_STAGES, + C_SINIT_VAL, + tempSyncEnable, // wasC_SYNC_ENABLE, + C_SYNC_PRIORITY) + sinsat1_addsub(.A(intFB), .B(B), .CLK(CLK), .ADD(ADD), + .C_IN(C_IN), .B_IN(B_IN), .CE(intCE), .BYPASS(BYPASS), + .ACLR(ACLR), .ASET(ASET), .AINIT(AINIT), + .SCLR(SCLR), .SSET(SSET), .SINIT(SINIT), + .A_SIGNED(B_SIGNED), .B_SIGNED(B_SIGNED), + .OVFL(OVFL_sinsat1), .C_OUT(intC_OUT_sinsat1), + .B_OUT(intB_OUT_sinsat1), .Q_OVFL(Q_OVFL_sinsat1), + .Q_C_OUT(Q_C_OUT_sinsat1), .Q_B_OUT(Q_B_OUT_sinsat1), + .S(intS_sinsat1), .Q()); + + // Registers for output of the last addsub + C_REG_FD_V5_0 #(C_AINIT_VAL[(C_OUT_WIDTH*8)-1 : (C_OUT_WIDTH-1)*8], + C_ENABLE_RLOCS, + 0, + 0, + 0, + C_HAS_CE, + 1, + 0, + 1, + C_SINIT_VAL[(C_OUT_WIDTH*8)-1 : (C_OUT_WIDTH-1)*8], + C_SYNC_ENABLE, + C_SYNC_PRIORITY, + 1) + msb_reg(.D(intS_sinsat1[outwidth_min_one]), .CLK(CLK), + .CE(intCE), .ACLR(ACLR), .ASET(ASET), .AINIT(AINIT), + .SCLR(intSCLR_TO_MSB), .SSET(intSSET_TO_MSB), + .SINIT(SINIT), .Q(intFBq_sinsat1[outwidth_min_one])); + + // Need the ?: on the value of C_B_WIDTH in case it == 1 + C_REG_FD_V5_0 #(C_AINIT_VAL[(((C_OUT_WIDTH == 1 ? 2 : C_OUT_WIDTH)-1)*8)-1 : 0], + C_ENABLE_RLOCS, + 0, + 0, + 0, + C_HAS_CE, + 1, + 0, + 1, + C_SINIT_VAL[(((C_OUT_WIDTH == 1 ? 2 : C_OUT_WIDTH)-1)*8)-1 : 0], + C_SYNC_ENABLE, + C_SYNC_PRIORITY, + (C_OUT_WIDTH == 1 ? 2 : C_OUT_WIDTH)-1) + rest_reg(.D(intS_sinsat1[(C_OUT_WIDTH == 1 ? 2 : C_OUT_WIDTH)-2 : 0]), .CLK(CLK), + .CE(intCE), .ACLR(ACLR), .ASET(ASET), .AINIT(AINIT), + .SCLR((C_B_WIDTH == 1 ? intSCLR_TO_MSB : intSCLR_TO_REST)), .SSET((C_B_WIDTH == 1 ? intSSET_TO_MSB : intSSET_TO_REST)), + .SINIT(SINIT), .Q(intFBq_sinsat1[(C_OUT_WIDTH == 1 ? 2 : C_OUT_WIDTH)-2 : 0])); + + + // Sort out the choices from all these output signals... + assign tempCE = ((C_SYNC_ENABLE == 0 && C_HAS_CE == 1 && (C_HAS_SSET == 1 || C_HAS_SCLR == 1) && C_SATURATE == 1) ? (CE | intSSET | intSCLR) : CE); + assign intCE = (C_SATURATE == 0 ? CE : (((C_HAS_BYPASS == 1)&&(C_BYPASS_LOW == 1)) ? ((C_BYPASS_ENABLE == `c_override) ? (~BYPASS | tempCE) : tempCE) : (((C_HAS_BYPASS == 1)&&(C_BYPASS_LOW == 0)) ? ((C_BYPASS_ENABLE == `c_override) ? (BYPASS | tempCE) : tempCE) : tempCE))) ; + + assign intC_OUT = (C_SATURATE == 0 ? intC_OUT_sat0 : (C_B_TYPE == `c_unsigned ? intC_OUT_unsat1 : intC_OUT_sinsat1)); + assign intB_OUT = (C_SATURATE == 0 ? intB_OUT_sat0 : (C_B_TYPE == `c_unsigned ? intB_OUT_unsat1 : intB_OUT_sinsat1)); + assign OVFL = (C_SATURATE == 0 ? OVFL_sat0 : (C_B_TYPE == `c_unsigned ? OVFL_unsat1 : OVFL_sinsat1)); + assign Q_C_OUT = (C_SATURATE == 0 ? Q_C_OUT_sat0 : (C_B_TYPE == `c_unsigned ? Q_C_OUT_unsat1 : Q_C_OUT_sinsat1)); + assign Q_B_OUT = (C_SATURATE == 0 ? Q_B_OUT_sat0 : (C_B_TYPE == `c_unsigned ? Q_B_OUT_unsat1 : Q_B_OUT_sinsat1)); + assign Q_OVFL = (C_SATURATE == 0 ? Q_OVFL_sat0 : (C_B_TYPE == `c_unsigned ? Q_OVFL_unsat1 : Q_OVFL_sinsat1)); + assign intS = (C_SATURATE == 0 ? intS_sat0 : (C_B_TYPE == `c_unsigned ? intS_unsat1 : intS_sinsat1)); + assign intFBq = (C_SATURATE == 0 ? intFBq_sat0 : (C_B_TYPE == `c_unsigned ? intFBq_unsat1 : intFBq_sinsat1)); + + + // COMPLEX decisions on what to feed to the local control sigs... + // The signal name suffices denote: un = unsigned, sg = signed, 00 = has neither sset nor sclr, 01 = has sclr only etc + // 11c = has bot sset and sclr and sclr dominates, 11s = sset dominates, etc + + // Unsigned version first + assign tmpsetsatlogic_un00 = (C_ADD_MODE == `c_add ? intC_OUT : (C_ADD_MODE == `c_sub ? intSSET : (intC_OUT & ADD))); + assign tmpsetsatlogic_un01 = (C_ADD_MODE == `c_add ? (intC_OUT & ~intSCLR) : (C_ADD_MODE == `c_sub ? intSSET : (intC_OUT & ~intSCLR & ADD))); + assign tmpsetsatlogic_un10 = (C_ADD_MODE == `c_add ? (intC_OUT | intSSET) : (C_ADD_MODE == `c_sub ? intSSET : ((intC_OUT & ADD) | intSSET))); + assign tmpsetsatlogic_un11c = (C_ADD_MODE == `c_add ? (~intSCLR & (intC_OUT | intSSET)) : (C_ADD_MODE == `c_sub ? (~intSCLR & intSSET) : ((~intSCLR & intC_OUT & ADD) | (intSSET & ~intSCLR)))); + assign tmpsetsatlogic_un11s = (C_ADD_MODE == `c_add ? ((~intSCLR && intC_OUT) | intSSET) : (C_ADD_MODE == `c_sub ? intSSET : ((~intSCLR & intC_OUT & ADD) | intSSET))); + +// assign tmpclrsatlogic_un00 = (C_ADD_MODE == `c_add ? intSCLR : (C_ADD_MODE == `c_sub ? ~intB_OUT : (~intC_OUT & ~ADD))); + assign tmpclrsatlogic_un00 = (C_ADD_MODE == `c_add ? intSCLR : (C_ADD_MODE == `c_sub ? (C_HAS_BYPASS == 1 ? (C_BYPASS_LOW == 1 ? (~intB_OUT & BYPASS) : (~intB_OUT & ~BYPASS)): ~intB_OUT) : (C_HAS_BYPASS == 1 ? (C_BYPASS_LOW ==1 ? ((~intC_OUT & ~ADD) & BYPASS) : ((~intC_OUT & ~ADD) & ~BYPASS)) : (~intC_OUT & ~ADD)))); +// assign tmpclrsatlogic_un01 = (C_ADD_MODE == `c_add ? intSCLR : (C_ADD_MODE == `c_sub ? (~intB_OUT | intSCLR) : (intSCLR | (~intC_OUT & ~ADD)))); + assign tmpclrsatlogic_un01 = (C_ADD_MODE == `c_add ? intSCLR : (C_ADD_MODE == `c_sub ? (C_HAS_BYPASS == 1 ? (C_BYPASS_LOW == 1 ? ((~intB_OUT & BYPASS) | intSCLR) : ((~intB_OUT & ~BYPASS) | intSCLR)) : (~intB_OUT | intSCLR)) : (C_HAS_BYPASS == 1 ? (C_BYPASS_LOW ==1 ? (intSCLR | ((~intC_OUT & ~ADD) & BYPASS)) : (intSCLR | ((~intC_OUT & ~ADD) & ~BYPASS))) : (intSCLR | (~intC_OUT & ~ADD))))); +// assign tmpclrsatlogic_un10 = (C_ADD_MODE == `c_add ? intSCLR : (C_ADD_MODE == `c_sub ? (~intB_OUT & ~intSSET) : (~intSSET & ~intC_OUT & ~ADD))); + assign tmpclrsatlogic_un10 = (C_ADD_MODE == `c_add ? intSCLR : (C_ADD_MODE == `c_sub ? (C_HAS_BYPASS == 1 ? (C_BYPASS_LOW == 1 ? ((~intB_OUT & BYPASS) & ~intSSET) : ((~intB_OUT & ~BYPASS) & ~intSSET)): (~intB_OUT & ~intSSET)) : ((C_HAS_BYPASS == 1 ? (C_BYPASS_LOW ==1 ? (~intSSET & (~intC_OUT & ~ADD) & BYPASS) : (~intSSET & ((~intC_OUT & ~ADD) & ~BYPASS))) : (~intSSET & ~intC_OUT & ~ADD))))); +// assign tmpclrsatlogic_un11c = (C_ADD_MODE == `c_add ? intSCLR : (C_ADD_MODE == `c_sub ? (intSCLR | (~intB_OUT & ~intSSET)) : (intSCLR | (~intSSET & ~intC_OUT & ~ADD)))); + assign tmpclrsatlogic_un11c = (C_ADD_MODE == `c_add ? intSCLR : (C_ADD_MODE == `c_sub ? (C_HAS_BYPASS == 1 ? (C_BYPASS_LOW == 1 ? (intSCLR | ((~intB_OUT & BYPASS) & ~intSSET)) : (intSCLR | ((~intB_OUT & ~BYPASS) & ~intSSET))) : (intSCLR | (~intB_OUT & ~intSSET))) : ((C_HAS_BYPASS == 1 ? (C_BYPASS_LOW ==1 ? (intSCLR | ((~intSSET & ~intC_OUT & ~ADD) & BYPASS)) : (intSCLR | ((~intSSET & ~intC_OUT & ~ADD) & ~BYPASS))) : (intSCLR | (~intSSET & ~intC_OUT & ~ADD)))))); +// assign tmpclrsatlogic_un11s = (C_ADD_MODE == `c_add ? (intSCLR & ~intSSET) : (C_ADD_MODE == `c_sub ? (~intSSET & (intSCLR | ~intB_OUT)) : ((intSCLR & ~intSSET) | (~intSSET & ~intC_OUT & ~ADD)))); + assign tmpclrsatlogic_un11s = (C_ADD_MODE == `c_add ? (intSCLR & ~intSSET) : (C_ADD_MODE == `c_sub ? (C_HAS_BYPASS == 1 ? (C_BYPASS_LOW == 1 ? (~intSSET & (intSCLR | (~intB_OUT & BYPASS))) : (~intSSET & (intSCLR | (~intB_OUT & ~BYPASS)))) : (~intSSET & (intSCLR | ~intB_OUT))) : (C_HAS_BYPASS == 1 ? (C_BYPASS_LOW ==1 ? ((intSCLR & ~intSSET) | (~intSSET & ((~intC_OUT & ~ADD) & BYPASS))): ((intSCLR & ~intSSET) | (~intSSET & ((~intC_OUT & ~ADD) & ~BYPASS)))) : ((intSCLR & ~intSSET) | (~intSSET & ~intC_OUT & ~ADD))))); + + assign intSSET_TO_ADDER = (C_HAS_SSET == 0 ? (C_HAS_SCLR == 0 ? tmpsetsatlogic_un00 : tmpsetsatlogic_un01) : + (C_HAS_SCLR == 0 ? tmpsetsatlogic_un10 : + (C_SYNC_PRIORITY == `c_clear ? tmpsetsatlogic_un11c : tmpsetsatlogic_un11s))); + + assign intSCLR_TO_ADDER = (C_HAS_SSET == 0 ? (C_HAS_SCLR == 0 ? tmpclrsatlogic_un00 : tmpclrsatlogic_un01) : + (C_HAS_SCLR == 0 ? tmpclrsatlogic_un10 : + (C_SYNC_PRIORITY == `c_clear ? tmpclrsatlogic_un11c : tmpclrsatlogic_un11s))); + + // Now all the signals for the signed version + assign intB = intBconst[C_B_WIDTH-1]; + //assign intB = (C_B_CONSTANT == 1 ? (C_B_VALUE[(C_B_WIDTH*8)-1 : (C_B_WIDTH-1)*8] == "0" ? 1'b0 : 1'b1) : B[C_B_WIDTH-1]) ; + + assign addclrBaseSig = (intS[C_HIGH_BIT] & ~(intFBq[C_HIGH_BIT]) & ~(intB)) ; + assign addsetBaseSig = (~(intS[C_HIGH_BIT]) & intFBq[C_HIGH_BIT] & intB) ; + assign subclrBaseSig = (intS[C_HIGH_BIT] & ~(intFBq[C_HIGH_BIT]) & intB) ; + assign subsetBaseSig = (~(intS[C_HIGH_BIT]) & intFBq[C_HIGH_BIT] & ~(intB)) ; + assign addsubclrBaseSig = ((~ADD & (intS[C_HIGH_BIT] & ~(intFBq[C_HIGH_BIT]) & intB)) | (ADD & (intS[C_HIGH_BIT] & ~(intFBq[C_HIGH_BIT]) & ~(intB)))) ; + assign addsubsetBaseSig = ((~ADD & (~(intS[C_HIGH_BIT]) & intFBq[C_HIGH_BIT] & ~(intB))) | (ADD & (~(intS[C_HIGH_BIT]) & intFBq[C_HIGH_BIT] & intB))) ; + + assign addclrBasePin = (~(intB_SIGNED) & ~(intFBq[C_HIGH_BIT]) & intS[C_HIGH_BIT]) | (intB_SIGNED & ~(intFBq[C_HIGH_BIT]) & intS[C_HIGH_BIT] & ~(intB)); + assign addsetBasePin = (intB_SIGNED & intFBq[C_HIGH_BIT] & ~(intS[C_HIGH_BIT]) & intB) ; + assign subclrBasePin = (intB_SIGNED & ~(intFBq[C_HIGH_BIT]) & intS[C_HIGH_BIT] & intB); + assign subsetBasePin = (~(intB_SIGNED) & intFBq[C_HIGH_BIT] & ~(intS[C_HIGH_BIT])) | (intB_SIGNED & intFBq[C_HIGH_BIT] & ~(intS[C_HIGH_BIT]) & ~(intB)); + assign addsubclrBasePin = (~(ADD) & (intB_SIGNED & ~(intFBq[C_HIGH_BIT]) & intS[C_HIGH_BIT] & intB)) | (ADD & ((~(intB_SIGNED) & ~(intFBq[C_HIGH_BIT]) & intS[C_HIGH_BIT]) | (intB_SIGNED & ~(intFBq[C_HIGH_BIT]) & intS[C_HIGH_BIT] & ~(intB)))) ; + assign addsubsetBasePin = (~(ADD) & ((~intB_SIGNED & intFBq[C_HIGH_BIT] & ~(intS[C_HIGH_BIT])) | (intB_SIGNED & intFBq[C_HIGH_BIT] & ~intS[C_HIGH_BIT] & ~intB))) | (ADD & intB_SIGNED & intFBq[C_HIGH_BIT] & ~intS[C_HIGH_BIT] & intB) ; + + assign addclrBase = (C_HAS_B_SIGNED == 0 ? addclrBaseSig : addclrBasePin); + assign addsetBase = (C_HAS_B_SIGNED == 0 ? addsetBaseSig : addsetBasePin); + assign subclrBase = (C_HAS_B_SIGNED == 0 ? subclrBaseSig : subclrBasePin); + assign subsetBase = (C_HAS_B_SIGNED == 0 ? subsetBaseSig : subsetBasePin); + assign addsubclrBase = (C_HAS_B_SIGNED == 0 ? addsubclrBaseSig : addsubclrBasePin); + assign addsubsetBase = (C_HAS_B_SIGNED == 0 ? addsubsetBaseSig : addsubsetBasePin); + + assign tmpsetsatlogicmsb_sg00 = (C_ADD_MODE == `c_add ? (C_HAS_BYPASS == 1 ? addsetBase & intBYPASSbar : addsetBase) : (C_ADD_MODE == `c_sub ? (C_HAS_BYPASS == 1 ? subsetBase & intBYPASSbar : subsetBase) : (C_HAS_BYPASS == 1 ? addsubsetBase & intBYPASSbar : addsubsetBase) )); + assign tmpsetsatlogicmsb_sg01 = tmpsetsatlogicmsb_sg00 & ~intSCLR ; + assign tmpsetsatlogicmsb_sg10 = tmpsetsatlogicmsb_sg00 | intSSET ; + assign tmpsetsatlogicmsb_sg11c = (tmpsetsatlogicmsb_sg00 | intSSET) & ~intSCLR ; + assign tmpsetsatlogicmsb_sg11s = tmpsetsatlogicmsb_sg00 | intSSET ; + + assign tmpsetsatlogicrest_sg00 = (C_ADD_MODE == `c_add ? (C_HAS_BYPASS == 1 ? addclrBase & intBYPASSbar : addclrBase) : (C_ADD_MODE == `c_sub ? (C_HAS_BYPASS == 1 ? subclrBase & intBYPASSbar : subclrBase) : (C_HAS_BYPASS == 1 ? addsubclrBase & intBYPASSbar : addsubclrBase) )); + assign tmpsetsatlogicrest_sg01 = tmpsetsatlogicrest_sg00 & ~intSCLR ; + assign tmpsetsatlogicrest_sg10 = tmpsetsatlogicrest_sg00 | intSSET ; + assign tmpsetsatlogicrest_sg11c = (tmpsetsatlogicrest_sg00 | intSSET) & ~intSCLR ; + assign tmpsetsatlogicrest_sg11s = tmpsetsatlogicrest_sg00 | intSSET ; + + assign tmpclrsatlogicmsb_sg00 = tmpsetsatlogicrest_sg00 ; + assign tmpclrsatlogicmsb_sg01 = tmpsetsatlogicrest_sg00 | intSCLR ; + assign tmpclrsatlogicmsb_sg10 = tmpsetsatlogicrest_sg00 & ~intSSET ; + assign tmpclrsatlogicmsb_sg11c = tmpsetsatlogicrest_sg00 | intSCLR ; + assign tmpclrsatlogicmsb_sg11s = (tmpsetsatlogicrest_sg00 | intSCLR) & ~intSSET ; + + assign tmpclrsatlogicrest_sg00 = tmpsetsatlogicmsb_sg00 ; + assign tmpclrsatlogicrest_sg01 = tmpsetsatlogicmsb_sg00 | intSCLR ; + assign tmpclrsatlogicrest_sg10 = tmpsetsatlogicmsb_sg00 & ~intSSET ; + assign tmpclrsatlogicrest_sg11c = tmpsetsatlogicmsb_sg00 | intSCLR ; + assign tmpclrsatlogicrest_sg11s = (tmpsetsatlogicmsb_sg00 | intSCLR) & ~intSSET ; + + assign intSSET_TO_MSB = (C_HAS_SSET == 0 ? (C_HAS_SCLR == 0 ? tmpsetsatlogicmsb_sg00 : tmpsetsatlogicmsb_sg01) : + (C_HAS_SCLR == 0 ? tmpsetsatlogicmsb_sg10 : + (C_SYNC_PRIORITY == `c_clear ? tmpsetsatlogicmsb_sg11c : tmpsetsatlogicmsb_sg11s))); + + assign intSCLR_TO_MSB = (C_HAS_SSET == 0 ? (C_HAS_SCLR == 0 ? tmpclrsatlogicmsb_sg00 : tmpclrsatlogicmsb_sg01) : + (C_HAS_SCLR == 0 ? tmpclrsatlogicmsb_sg10 : + (C_SYNC_PRIORITY == `c_clear ? tmpclrsatlogicmsb_sg11c : tmpclrsatlogicmsb_sg11s))); + + assign intSSET_TO_REST = (C_HAS_SSET == 0 ? (C_HAS_SCLR == 0 ? tmpsetsatlogicrest_sg00 : tmpsetsatlogicrest_sg01) : + (C_HAS_SCLR == 0 ? tmpsetsatlogicrest_sg10 : + (C_SYNC_PRIORITY == `c_clear ? tmpsetsatlogicrest_sg11c : tmpsetsatlogicrest_sg11s))); + + assign intSCLR_TO_REST = (C_HAS_SSET == 0 ? (C_HAS_SCLR == 0 ? tmpclrsatlogicrest_sg00 : tmpclrsatlogicrest_sg01) : + (C_HAS_SCLR == 0 ? tmpclrsatlogicrest_sg10 : + (C_SYNC_PRIORITY == `c_clear ? tmpclrsatlogicrest_sg11c : tmpclrsatlogicrest_sg11s))); + + // Finally we are ready to scale the feedback signal... + // If the scaling factor results in NO bits being fed back to the input then we need to handle this! + // This is the case if C_SCALE >= C_OUT_WIDTH + assign intFB[C_OUT_WIDTH-1-(C_SCALE >= C_OUT_WIDTH ? 0 : C_SCALE) : 0] = (C_SCALE >= C_OUT_WIDTH ? {C_OUT_WIDTH{1'b0}} : intFBq[C_OUT_WIDTH-1 : (C_SCALE >= C_OUT_WIDTH ? 0 : C_SCALE)]); + //assign intFB[C_OUT_WIDTH-1 : C_OUT_WIDTH-(C_SCALE == 0 ? 1 : C_SCALE)] = (C_SCALE == 0 ? intFBq[C_OUT_WIDTH-1] : (C_SCALE < C_OUT_WIDTH && (C_B_TYPE == `c_signed || (C_B_TYPE == `c_pin && intB_SIGNED === 1'b1)) ? + // {C_SCALE{intFBq[C_OUT_WIDTH-1]}} : {C_SCALE{1'b0}})); + assign intFB[C_OUT_WIDTH-1 : C_OUT_WIDTH-(C_SCALE == 0 ? 1 : C_SCALE)] = (C_SCALE == 0 ? intFBq[C_OUT_WIDTH-1] : (C_SCALE < C_OUT_WIDTH && (C_B_TYPE == `c_signed || C_B_TYPE == `c_pin) ? + {C_SCALE{intFBq[C_OUT_WIDTH-1]}} : {C_SCALE{1'b0}})); + + + + + initial + begin + #1; + end + +/* helper functions */ + + function defval; + input i; + input hassig; + input val; + begin + if(hassig == 1) + defval = i; + else + defval = val; + end + endfunction + + function [C_B_WIDTH - 1 : 0] to_bitsB; + input [C_B_WIDTH*8 : 1] instring; + integer i; + integer non_null_string; + begin + non_null_string = 0; + for(i = C_B_WIDTH; i > 0; i = i - 1) + begin // Is the string empty? + if(instring[(i*8)] == 0 && + instring[(i*8)-1] == 0 && + instring[(i*8)-2] == 0 && + instring[(i*8)-3] == 0 && + instring[(i*8)-4] == 0 && + instring[(i*8)-5] == 0 && + instring[(i*8)-6] == 0 && + instring[(i*8)-7] == 0 && + non_null_string == 0) + non_null_string = 0; // Use the return value to flag a non-empty string + else + non_null_string = 1; // Non-null character! + end + if(non_null_string == 0) // String IS empty! Just return the value to be all '0's + begin + for(i = C_B_WIDTH; i > 0; i = i - 1) + to_bitsB[i-1] = 0; + end + else + begin + for(i = C_B_WIDTH; i > 0; i = i - 1) + begin // Is this character a '0'? (ASCII = 48 = 00110000) + if(instring[(i*8)] == 0 && + instring[(i*8)-1] == 0 && + instring[(i*8)-2] == 1 && + instring[(i*8)-3] == 1 && + instring[(i*8)-4] == 0 && + instring[(i*8)-5] == 0 && + instring[(i*8)-6] == 0 && + instring[(i*8)-7] == 0) + to_bitsB[i-1] = 0; + // Or is it a '1'? + else if(instring[(i*8)] == 0 && + instring[(i*8)-1] == 0 && + instring[(i*8)-2] == 1 && + instring[(i*8)-3] == 1 && + instring[(i*8)-4] == 0 && + instring[(i*8)-5] == 0 && + instring[(i*8)-6] == 0 && + instring[(i*8)-7] == 1) + to_bitsB[i-1] = 1; + // Or is it a ' '? (a null char - in which case insert a '0') + else if(instring[(i*8)] == 0 && + instring[(i*8)-1] == 0 && + instring[(i*8)-2] == 0 && + instring[(i*8)-3] == 0 && + instring[(i*8)-4] == 0 && + instring[(i*8)-5] == 0 && + instring[(i*8)-6] == 0 && + instring[(i*8)-7] == 0) + to_bitsB[i-1] = 0; + else + begin + $display("Error in %m at time %d ns: non-binary digit in string \"%s\"\nExiting simulation...",$time, instring); + $finish; + end + end + end + end + endfunction + + function max; + input a; + input b; + begin + max = (a > b) ? a : b; + end + endfunction + +endmodule + +`undef c_set +`undef c_clear +`undef c_override +`undef c_no_override +`undef c_add +`undef c_sub +`undef c_add_sub +`undef c_signed +`undef c_unsigned +`undef c_pin +`undef allUKs + + + + + + + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/C_ACCUM_V5_1.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/C_ACCUM_V5_1.v new file mode 100644 index 0000000..b82214b --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/C_ACCUM_V5_1.v @@ -0,0 +1,655 @@ +/* $Id: C_ACCUM_V5_1.v,v 1.15 2008/09/08 20:05:55 akennedy Exp $ +-- +-- Filename - C_ACCUM_V5_1.v +-- Author - Xilinx +-- Creation - 15 July 1999 +-- +-- Description - This file contains the Verilog behavior for the Baseblocks C_ACCUM_V5_1 module +*/ + +`timescale 1 ns/10 ps + +`define c_set 0 +`define c_clear 1 +`define c_override 0 +`define c_no_override 1 +`define c_add 0 +`define c_sub 1 +`define c_add_sub 2 +`define c_signed 0 +`define c_unsigned 1 +`define c_pin 2 +`define allUKs {(C_HIGH_BIT-C_LOW_BIT)+1{1'bx}} + +module C_ACCUM_V5_1 (B, CLK, ADD, C_IN, B_IN, CE, BYPASS, ACLR, ASET, AINIT, + SCLR, SSET, SINIT, B_SIGNED, OVFL, C_OUT, B_OUT, + Q_OVFL, Q_C_OUT, Q_B_OUT, S, Q); + + parameter C_ADD_MODE = `c_add; + parameter C_AINIT_VAL = "0000000000000000"; + parameter C_BYPASS_ENABLE = `c_override; + parameter C_BYPASS_LOW = 0; + parameter C_B_CONSTANT = 0; + parameter C_B_TYPE = `c_unsigned; + parameter C_B_VALUE = "0000000000000000"; + parameter C_B_WIDTH = 16; + parameter C_ENABLE_RLOCS = 1; + parameter C_HAS_ACLR = 1; + parameter C_HAS_ADD = 0; + parameter C_HAS_AINIT = 0; + parameter C_HAS_ASET = 0; + parameter C_HAS_BYPASS = 0; + parameter C_HAS_BYPASS_WITH_CIN = 0; + parameter C_HAS_B_IN = 1; + parameter C_HAS_B_OUT = 0; + parameter C_HAS_B_SIGNED = 0; + parameter C_HAS_CE = 1; + parameter C_HAS_C_IN = 1; + parameter C_HAS_C_OUT = 0; + parameter C_HAS_OVFL = 0; + parameter C_HAS_Q_B_OUT = 0; + parameter C_HAS_Q_C_OUT = 0; + parameter C_HAS_Q_OVFL = 0; + parameter C_HAS_S = 1; + parameter C_HAS_SCLR = 1; + parameter C_HAS_SINIT = 0; + parameter C_HAS_SSET = 0; + parameter C_HIGH_BIT = 15; + parameter C_LOW_BIT = 0; + parameter C_OUT_WIDTH = 16; + parameter C_PIPE_STAGES = 1; + parameter C_SATURATE = 0; + parameter C_SCALE = 1; + parameter C_SINIT_VAL = "0000000000000000"; + parameter C_SYNC_ENABLE = `c_override; + parameter C_SYNC_PRIORITY = `c_clear; + + // Only for internal consumption (prob with MTI otherwise) + parameter outwidth_min_one = C_OUT_WIDTH-1; + parameter bwidth_min_one = C_B_WIDTH-1; + + parameter tempSyncEnable = ((C_SYNC_ENABLE == 0 && C_HAS_CE == 1 && (C_HAS_SSET == 1 || C_HAS_SCLR == 1) && C_SATURATE == 1) ? 1 : C_SYNC_ENABLE); + + input [C_B_WIDTH-1 : 0] B; + input CLK; + input ADD; + input C_IN; + input B_IN; + input CE; + input BYPASS; + input ACLR; + input ASET; + input AINIT; + input SCLR; + input SSET; + input SINIT; + input B_SIGNED; + output OVFL; + output C_OUT; + output B_OUT; + output Q_OVFL; + output Q_C_OUT; + output Q_B_OUT; + output [C_HIGH_BIT : C_LOW_BIT] S; + output [C_HIGH_BIT : C_LOW_BIT] Q; + + + // Internal values to drive signals when input is missing + wire [C_OUT_WIDTH-1 : 0] intS; + wire [C_OUT_WIDTH-1 : 0] intS_sat0; + wire [C_OUT_WIDTH-1 : 0] intS_unsat1; + wire [C_OUT_WIDTH-1 : 0] intS_sinsat1; + wire [C_OUT_WIDTH-1 : 0] intFB; + wire [C_OUT_WIDTH-1 : 0] intFBq; + wire [C_OUT_WIDTH-1 : 0] intFBq_sat0; + wire [C_OUT_WIDTH-1 : 0] intFBq_unsat1; + wire [C_OUT_WIDTH-1 : 0] intFBq_sinsat1; + wire intSCLR; + wire intSSET; + wire intSCLR_TO_ADDER; + wire intSSET_TO_ADDER; + wire intSCLR_TO_MSB; + wire intSSET_TO_MSB; + wire intSCLR_TO_REST; + wire intSSET_TO_REST; + wire intB_SIGNED; + wire intBYPASSbar; + wire intC_OUT; + wire intB_OUT; + wire Q_C_OUT; + wire Q_B_OUT; + wire OVFL; + wire Q_OVFL; + wire intC_OUT_sat0; + wire intB_OUT_sat0; + wire Q_C_OUT_sat0; + wire Q_B_OUT_sat0; + wire OVFL_sat0; + wire Q_OVFL_sat0; + wire intC_OUT_unsat1; + wire intB_OUT_unsat1; + wire Q_C_OUT_unsat1; + wire Q_B_OUT_unsat1; + wire OVFL_unsat1; + wire Q_OVFL_unsat1; + wire intC_OUT_sinsat1; + wire intB_OUT_sinsat1; + wire Q_C_OUT_sinsat1; + wire Q_B_OUT_sinsat1; + wire OVFL_sinsat1; + wire Q_OVFL_sinsat1; + wire intBYPASS_WITH_CIN; // New signal for bypass with Cin mode + wire tempCE; + + + wire tmpsetsatlogic_un00; + wire tmpsetsatlogic_un01; + wire tmpsetsatlogic_un10; + wire tmpsetsatlogic_un11c; + wire tmpsetsatlogic_un11s; + + wire tmpclrsatlogic_un00; + wire tmpclrsatlogic_un01; + wire tmpclrsatlogic_un10; + wire tmpclrsatlogic_un11c; + wire tmpclrsatlogic_un11s; + + wire tmpsetsatlogicmsb_sg00; + wire tmpsetsatlogicmsb_sg01; + wire tmpsetsatlogicmsb_sg10; + wire tmpsetsatlogicmsb_sg11c; + wire tmpsetsatlogicmsb_sg11s; + + wire tmpsetsatlogicrest_sg00; + wire tmpsetsatlogicrest_sg01; + wire tmpsetsatlogicrest_sg10; + wire tmpsetsatlogicrest_sg11c; + wire tmpsetsatlogicrest_sg11s; + + wire tmpclrsatlogicmsb_sg00; + wire tmpclrsatlogicmsb_sg01; + wire tmpclrsatlogicmsb_sg10; + wire tmpclrsatlogicmsb_sg11c; + wire tmpclrsatlogicmsb_sg11s; + + wire tmpclrsatlogicrest_sg00; + wire tmpclrsatlogicrest_sg01; + wire tmpclrsatlogicrest_sg10; + wire tmpclrsatlogicrest_sg11c; + wire tmpclrsatlogicrest_sg11s; + + wire addsetBaseSig ; + wire subsetBaseSig ; + wire addsubsetBaseSig ; + wire addclrBaseSig ; + wire subclrBaseSig ; + wire addsubclrBaseSig ; + + wire addsetBasePin ; + wire subsetBasePin ; + wire addsubsetBasePin ; + wire addclrBasePin ; + wire subclrBasePin ; + wire addsubclrBasePin ; + + wire addsetBase ; + wire subsetBase ; + wire addsubsetBase ; + wire addclrBase ; + wire subclrBase ; + wire addsubclrBase ; + + wire intCE ; + wire intB ; + wire [C_B_WIDTH : 0] intBconst; + + wire [C_HIGH_BIT : C_LOW_BIT] Q = intFBq; + wire [C_HIGH_BIT : C_LOW_BIT] S = (C_HAS_S == 1 ? intS : `allUKs); + wire C_OUT = (C_HAS_C_OUT == 1 ? intC_OUT : 1'bx); + wire B_OUT = (C_HAS_B_OUT == 1 ? intB_OUT : 1'bx); + + + // Sort out default values for missing ports + + assign intB_SIGNED = defval(B_SIGNED, C_HAS_B_SIGNED, 0); + assign intBYPASSbar = (C_BYPASS_LOW == 1 ? BYPASS : ~BYPASS); + assign intSCLR = defval(SCLR, C_HAS_SCLR, 0); + assign intSSET = defval(SSET, C_HAS_SSET, 0); + assign intBYPASS_WITH_CIN = C_HAS_BYPASS_WITH_CIN; //assign new c_has_bypass_with_cin parameter to internal wire + assign intBconst = (C_B_CONSTANT === 1) ? to_bitsB(C_B_VALUE) : B; + + // Now make up the design from other baseblox + // An addsub for when no saturation logic is required... + C_ADDSUB_V5_0 #(C_ADD_MODE, + C_AINIT_VAL, + (C_B_TYPE == `c_pin )? `c_signed : C_B_TYPE, + C_OUT_WIDTH, + C_BYPASS_ENABLE, + C_BYPASS_LOW, + C_B_CONSTANT, + C_B_TYPE, + C_B_VALUE, + C_B_WIDTH, + C_ENABLE_RLOCS, + C_HAS_ACLR, + C_HAS_ADD, + C_HAS_AINIT, + C_HAS_ASET, + C_HAS_B_SIGNED, + C_HAS_BYPASS, + C_HAS_BYPASS_WITH_CIN, + C_HAS_B_IN, + C_HAS_B_OUT, + C_HAS_B_SIGNED, + C_HAS_CE, + C_HAS_C_IN, + C_HAS_C_OUT, + C_HAS_OVFL, + 1, + C_HAS_Q_B_OUT, + C_HAS_Q_C_OUT, + C_HAS_Q_OVFL, + C_HAS_S, + C_HAS_SCLR, + C_HAS_SINIT, + C_HAS_SSET, + outwidth_min_one, + 1, + 0, + C_OUT_WIDTH, + C_PIPE_STAGES, + C_SINIT_VAL, + C_SYNC_ENABLE, + C_SYNC_PRIORITY) + sat0_addsub(.A(intFB), .B(B), .CLK(CLK), .ADD(ADD), + .C_IN(C_IN), .B_IN(B_IN), .CE(CE), .BYPASS(BYPASS), + .ACLR(ACLR), .ASET(ASET), .AINIT(AINIT), + .SCLR(SCLR), .SSET(SSET), .SINIT(SINIT), + .A_SIGNED(B_SIGNED), .B_SIGNED(B_SIGNED), + .OVFL(OVFL_sat0), .C_OUT(intC_OUT_sat0), + .B_OUT(intB_OUT_sat0), .Q_OVFL(Q_OVFL_sat0), + .Q_C_OUT(Q_C_OUT_sat0), .Q_B_OUT(Q_B_OUT_sat0), + .S(intS_sat0), .Q(intFBq_sat0)); + + + // Another addsub for when saturation logic IS required, but only for unsigned data + C_ADDSUB_V5_0 #(C_ADD_MODE, + C_AINIT_VAL, + C_B_TYPE, + C_OUT_WIDTH, + C_BYPASS_ENABLE, + C_BYPASS_LOW, + C_B_CONSTANT, + C_B_TYPE, + C_B_VALUE, + C_B_WIDTH, + C_ENABLE_RLOCS, + 0, + C_HAS_ADD, + 0, + 0, + C_HAS_B_SIGNED, + C_HAS_BYPASS, + C_HAS_BYPASS_WITH_CIN, + C_HAS_B_IN, + 1, + C_HAS_B_SIGNED, + C_HAS_CE, + C_HAS_C_IN, + 1, + C_HAS_OVFL, + 1, + C_HAS_Q_B_OUT, + C_HAS_Q_C_OUT, + C_HAS_Q_OVFL, + C_HAS_S, + 1, + 0, + 1, + outwidth_min_one, + 1, + 0, + C_OUT_WIDTH, + C_PIPE_STAGES, + C_SINIT_VAL, + tempSyncEnable, + C_SYNC_PRIORITY) + unsat1_addsub(.A(intFB), .B(B), .CLK(CLK), .ADD(ADD), + .C_IN(C_IN), .B_IN(B_IN), .CE(intCE), .BYPASS(BYPASS), + .ACLR(ACLR), .ASET(ASET), .AINIT(AINIT), + .SCLR(intSCLR_TO_ADDER), .SSET(intSSET_TO_ADDER), .SINIT(SINIT), + .A_SIGNED(B_SIGNED), .B_SIGNED(B_SIGNED), + .OVFL(OVFL_unsat1), .C_OUT(intC_OUT_unsat1), + .B_OUT(intB_OUT_unsat1), .Q_OVFL(Q_OVFL_unsat1), + .Q_C_OUT(Q_C_OUT_unsat1), .Q_B_OUT(Q_B_OUT_unsat1), + .S(intS_unsat1), .Q(intFBq_unsat1)); + + // Another addsub for when saturation logic IS required, but for signed data + C_ADDSUB_V5_0 #(C_ADD_MODE, + C_AINIT_VAL, + C_B_TYPE, + C_OUT_WIDTH, + C_BYPASS_ENABLE, + C_BYPASS_LOW, + C_B_CONSTANT, + C_B_TYPE, + C_B_VALUE, + C_B_WIDTH, + C_ENABLE_RLOCS, + C_HAS_ACLR, + C_HAS_ADD, + C_HAS_AINIT, + C_HAS_ASET, + C_HAS_B_SIGNED, + C_HAS_BYPASS, + C_HAS_BYPASS_WITH_CIN, + C_HAS_B_IN, + 1, + C_HAS_B_SIGNED, + C_HAS_CE, + C_HAS_C_IN, + 1, + C_HAS_OVFL, + 0, + C_HAS_Q_B_OUT, + C_HAS_Q_C_OUT, + C_HAS_Q_OVFL, + 1, + C_HAS_SCLR, + C_HAS_SINIT, + C_HAS_SSET, + outwidth_min_one, + 1, + 0, + C_OUT_WIDTH, + C_PIPE_STAGES, + C_SINIT_VAL, + tempSyncEnable, // wasC_SYNC_ENABLE, + C_SYNC_PRIORITY) + sinsat1_addsub(.A(intFB), .B(B), .CLK(CLK), .ADD(ADD), + .C_IN(C_IN), .B_IN(B_IN), .CE(intCE), .BYPASS(BYPASS), + .ACLR(ACLR), .ASET(ASET), .AINIT(AINIT), + .SCLR(SCLR), .SSET(SSET), .SINIT(SINIT), + .A_SIGNED(B_SIGNED), .B_SIGNED(B_SIGNED), + .OVFL(OVFL_sinsat1), .C_OUT(intC_OUT_sinsat1), + .B_OUT(intB_OUT_sinsat1), .Q_OVFL(Q_OVFL_sinsat1), + .Q_C_OUT(Q_C_OUT_sinsat1), .Q_B_OUT(Q_B_OUT_sinsat1), + .S(intS_sinsat1), .Q()); + + // Registers for output of the last addsub + C_REG_FD_V5_0 #(C_AINIT_VAL[(C_OUT_WIDTH*8)-1 : (C_OUT_WIDTH-1)*8], + C_ENABLE_RLOCS, + 0, + 0, + 0, + C_HAS_CE, + 1, + 0, + 1, + C_SINIT_VAL[(C_OUT_WIDTH*8)-1 : (C_OUT_WIDTH-1)*8], + tempSyncEnable, //C_SYNC_ENABLE, + C_SYNC_PRIORITY, + 1) + msb_reg(.D(intS_sinsat1[outwidth_min_one]), .CLK(CLK), + .CE(intCE), .ACLR(ACLR), .ASET(ASET), .AINIT(AINIT), + .SCLR(intSCLR_TO_MSB), .SSET(intSSET_TO_MSB), + .SINIT(SINIT), .Q(intFBq_sinsat1[outwidth_min_one])); + + // Need the ?: on the value of C_B_WIDTH in case it == 1 + C_REG_FD_V5_0 #(C_AINIT_VAL[(((C_OUT_WIDTH == 1 ? 2 : C_OUT_WIDTH)-1)*8)-1 : 0], + C_ENABLE_RLOCS, + 0, + 0, + 0, + C_HAS_CE, + 1, + 0, + 1, + C_SINIT_VAL[(((C_OUT_WIDTH == 1 ? 2 : C_OUT_WIDTH)-1)*8)-1 : 0], + tempSyncEnable, //C_SYNC_ENABLE, + C_SYNC_PRIORITY, + (C_OUT_WIDTH == 1 ? 2 : C_OUT_WIDTH)-1) + rest_reg(.D(intS_sinsat1[(C_OUT_WIDTH == 1 ? 2 : C_OUT_WIDTH)-2 : 0]), .CLK(CLK), + .CE(intCE), .ACLR(ACLR), .ASET(ASET), .AINIT(AINIT), + .SCLR((C_B_WIDTH == 1 ? intSCLR_TO_MSB : intSCLR_TO_REST)), .SSET((C_B_WIDTH == 1 ? intSSET_TO_MSB : intSSET_TO_REST)), + .SINIT(SINIT), .Q(intFBq_sinsat1[(C_OUT_WIDTH == 1 ? 2 : C_OUT_WIDTH)-2 : 0])); + + + // Sort out the choices from all these output signals... + assign tempCE = ((C_SYNC_ENABLE == 0 && C_HAS_CE == 1 && (C_HAS_SSET == 1 || C_HAS_SCLR == 1) && C_SATURATE == 1) ? (CE | intSSET | intSCLR) : CE); + assign intCE = (C_SATURATE == 0 ? CE : (((C_HAS_BYPASS == 1)&&(C_BYPASS_LOW == 1)) ? ((C_BYPASS_ENABLE == `c_override) ? (~BYPASS | tempCE) : tempCE) : (((C_HAS_BYPASS == 1)&&(C_BYPASS_LOW == 0)) ? ((C_BYPASS_ENABLE == `c_override) ? (BYPASS | tempCE) : tempCE) : tempCE))) ; + + assign intC_OUT = (C_SATURATE == 0 ? intC_OUT_sat0 : (C_B_TYPE == `c_unsigned ? intC_OUT_unsat1 : intC_OUT_sinsat1)); + assign intB_OUT = (C_SATURATE == 0 ? intB_OUT_sat0 : (C_B_TYPE == `c_unsigned ? intB_OUT_unsat1 : intB_OUT_sinsat1)); + assign OVFL = (C_SATURATE == 0 ? OVFL_sat0 : (C_B_TYPE == `c_unsigned ? OVFL_unsat1 : OVFL_sinsat1)); + assign Q_C_OUT = (C_SATURATE == 0 ? Q_C_OUT_sat0 : (C_B_TYPE == `c_unsigned ? Q_C_OUT_unsat1 : Q_C_OUT_sinsat1)); + assign Q_B_OUT = (C_SATURATE == 0 ? Q_B_OUT_sat0 : (C_B_TYPE == `c_unsigned ? Q_B_OUT_unsat1 : Q_B_OUT_sinsat1)); + assign Q_OVFL = (C_SATURATE == 0 ? Q_OVFL_sat0 : (C_B_TYPE == `c_unsigned ? Q_OVFL_unsat1 : Q_OVFL_sinsat1)); + assign intS = (C_SATURATE == 0 ? intS_sat0 : (C_B_TYPE == `c_unsigned ? intS_unsat1 : intS_sinsat1)); + assign intFBq = (C_SATURATE == 0 ? intFBq_sat0 : (C_B_TYPE == `c_unsigned ? intFBq_unsat1 : intFBq_sinsat1)); + + + // COMPLEX decisions on what to feed to the local control sigs... + // The signal name suffices denote: un = unsigned, sg = signed, 00 = has neither sset nor sclr, 01 = has sclr only etc + // 11c = has bot sset and sclr and sclr dominates, 11s = sset dominates, etc + + // Unsigned version first + assign tmpsetsatlogic_un00 = (C_ADD_MODE == `c_add ? intC_OUT : (C_ADD_MODE == `c_sub ? intSSET : (intC_OUT & ADD))); + assign tmpsetsatlogic_un01 = (C_ADD_MODE == `c_add ? (intC_OUT & ~intSCLR) : (C_ADD_MODE == `c_sub ? intSSET : (intC_OUT & ~intSCLR & ADD))); + assign tmpsetsatlogic_un10 = (C_ADD_MODE == `c_add ? (intC_OUT | intSSET) : (C_ADD_MODE == `c_sub ? intSSET : ((intC_OUT & ADD) | intSSET))); + assign tmpsetsatlogic_un11c = (C_ADD_MODE == `c_add ? (~intSCLR & (intC_OUT | intSSET)) : (C_ADD_MODE == `c_sub ? (~intSCLR & intSSET) : ((~intSCLR & intC_OUT & ADD) | (intSSET & ~intSCLR)))); + assign tmpsetsatlogic_un11s = (C_ADD_MODE == `c_add ? ((~intSCLR && intC_OUT) | intSSET) : (C_ADD_MODE == `c_sub ? intSSET : ((~intSCLR & intC_OUT & ADD) | intSSET))); + +// assign tmpclrsatlogic_un00 = (C_ADD_MODE == `c_add ? intSCLR : (C_ADD_MODE == `c_sub ? ~intB_OUT : (~intC_OUT & ~ADD))); + assign tmpclrsatlogic_un00 = (C_ADD_MODE == `c_add ? intSCLR : (C_ADD_MODE == `c_sub ? (C_HAS_BYPASS == 1 ? (C_BYPASS_LOW == 1 ? (~intB_OUT & BYPASS) : (~intB_OUT & ~BYPASS)): ~intB_OUT) : (C_HAS_BYPASS == 1 ? (C_BYPASS_LOW ==1 ? ((~intC_OUT & ~ADD) & BYPASS) : ((~intC_OUT & ~ADD) & ~BYPASS)) : (~intC_OUT & ~ADD)))); +// assign tmpclrsatlogic_un01 = (C_ADD_MODE == `c_add ? intSCLR : (C_ADD_MODE == `c_sub ? (~intB_OUT | intSCLR) : (intSCLR | (~intC_OUT & ~ADD)))); + assign tmpclrsatlogic_un01 = (C_ADD_MODE == `c_add ? intSCLR : (C_ADD_MODE == `c_sub ? (C_HAS_BYPASS == 1 ? (C_BYPASS_LOW == 1 ? ((~intB_OUT & BYPASS) | intSCLR) : ((~intB_OUT & ~BYPASS) | intSCLR)) : (~intB_OUT | intSCLR)) : (C_HAS_BYPASS == 1 ? (C_BYPASS_LOW ==1 ? (intSCLR | ((~intC_OUT & ~ADD) & BYPASS)) : (intSCLR | ((~intC_OUT & ~ADD) & ~BYPASS))) : (intSCLR | (~intC_OUT & ~ADD))))); +// assign tmpclrsatlogic_un10 = (C_ADD_MODE == `c_add ? intSCLR : (C_ADD_MODE == `c_sub ? (~intB_OUT & ~intSSET) : (~intSSET & ~intC_OUT & ~ADD))); + assign tmpclrsatlogic_un10 = (C_ADD_MODE == `c_add ? intSCLR : (C_ADD_MODE == `c_sub ? (C_HAS_BYPASS == 1 ? (C_BYPASS_LOW == 1 ? ((~intB_OUT & BYPASS) & ~intSSET) : ((~intB_OUT & ~BYPASS) & ~intSSET)): (~intB_OUT & ~intSSET)) : ((C_HAS_BYPASS == 1 ? (C_BYPASS_LOW ==1 ? (~intSSET & (~intC_OUT & ~ADD) & BYPASS) : (~intSSET & ((~intC_OUT & ~ADD) & ~BYPASS))) : (~intSSET & ~intC_OUT & ~ADD))))); +// assign tmpclrsatlogic_un11c = (C_ADD_MODE == `c_add ? intSCLR : (C_ADD_MODE == `c_sub ? (intSCLR | (~intB_OUT & ~intSSET)) : (intSCLR | (~intSSET & ~intC_OUT & ~ADD)))); + assign tmpclrsatlogic_un11c = (C_ADD_MODE == `c_add ? intSCLR : (C_ADD_MODE == `c_sub ? (C_HAS_BYPASS == 1 ? (C_BYPASS_LOW == 1 ? (intSCLR | ((~intB_OUT & BYPASS) & ~intSSET)) : (intSCLR | ((~intB_OUT & ~BYPASS) & ~intSSET))) : (intSCLR | (~intB_OUT & ~intSSET))) : ((C_HAS_BYPASS == 1 ? (C_BYPASS_LOW ==1 ? (intSCLR | ((~intSSET & ~intC_OUT & ~ADD) & BYPASS)) : (intSCLR | ((~intSSET & ~intC_OUT & ~ADD) & ~BYPASS))) : (intSCLR | (~intSSET & ~intC_OUT & ~ADD)))))); +// assign tmpclrsatlogic_un11s = (C_ADD_MODE == `c_add ? (intSCLR & ~intSSET) : (C_ADD_MODE == `c_sub ? (~intSSET & (intSCLR | ~intB_OUT)) : ((intSCLR & ~intSSET) | (~intSSET & ~intC_OUT & ~ADD)))); + assign tmpclrsatlogic_un11s = (C_ADD_MODE == `c_add ? (intSCLR & ~intSSET) : (C_ADD_MODE == `c_sub ? (C_HAS_BYPASS == 1 ? (C_BYPASS_LOW == 1 ? (~intSSET & (intSCLR | (~intB_OUT & BYPASS))) : (~intSSET & (intSCLR | (~intB_OUT & ~BYPASS)))) : (~intSSET & (intSCLR | ~intB_OUT))) : (C_HAS_BYPASS == 1 ? (C_BYPASS_LOW ==1 ? ((intSCLR & ~intSSET) | (~intSSET & ((~intC_OUT & ~ADD) & BYPASS))): ((intSCLR & ~intSSET) | (~intSSET & ((~intC_OUT & ~ADD) & ~BYPASS)))) : ((intSCLR & ~intSSET) | (~intSSET & ~intC_OUT & ~ADD))))); + + assign intSSET_TO_ADDER = (C_HAS_SSET == 0 ? (C_HAS_SCLR == 0 ? tmpsetsatlogic_un00 : tmpsetsatlogic_un01) : + (C_HAS_SCLR == 0 ? tmpsetsatlogic_un10 : + (C_SYNC_PRIORITY == `c_clear ? tmpsetsatlogic_un11c : tmpsetsatlogic_un11s))); + + assign intSCLR_TO_ADDER = (C_HAS_SSET == 0 ? (C_HAS_SCLR == 0 ? tmpclrsatlogic_un00 : tmpclrsatlogic_un01) : + (C_HAS_SCLR == 0 ? tmpclrsatlogic_un10 : + (C_SYNC_PRIORITY == `c_clear ? tmpclrsatlogic_un11c : tmpclrsatlogic_un11s))); + + // Now all the signals for the signed version + assign intB = intBconst[C_B_WIDTH-1]; + //assign intB = (C_B_CONSTANT == 1 ? (C_B_VALUE[(C_B_WIDTH*8)-1 : (C_B_WIDTH-1)*8] == "0" ? 1'b0 : 1'b1) : B[C_B_WIDTH-1]) ; + + assign addclrBaseSig = (intS[C_HIGH_BIT] & ~(intFBq[C_HIGH_BIT]) & ~(intB)) ; + assign addsetBaseSig = (~(intS[C_HIGH_BIT]) & intFBq[C_HIGH_BIT] & intB) ; + assign subclrBaseSig = (intS[C_HIGH_BIT] & ~(intFBq[C_HIGH_BIT]) & intB) ; + assign subsetBaseSig = (~(intS[C_HIGH_BIT]) & intFBq[C_HIGH_BIT] & ~(intB)) ; + assign addsubclrBaseSig = ((~ADD & (intS[C_HIGH_BIT] & ~(intFBq[C_HIGH_BIT]) & intB)) | (ADD & (intS[C_HIGH_BIT] & ~(intFBq[C_HIGH_BIT]) & ~(intB)))) ; + assign addsubsetBaseSig = ((~ADD & (~(intS[C_HIGH_BIT]) & intFBq[C_HIGH_BIT] & ~(intB))) | (ADD & (~(intS[C_HIGH_BIT]) & intFBq[C_HIGH_BIT] & intB))) ; + + assign addclrBasePin = (~(intB_SIGNED) & ~(intFBq[C_HIGH_BIT]) & intS[C_HIGH_BIT]) | (intB_SIGNED & ~(intFBq[C_HIGH_BIT]) & intS[C_HIGH_BIT] & ~(intB)); + assign addsetBasePin = (intB_SIGNED & intFBq[C_HIGH_BIT] & ~(intS[C_HIGH_BIT]) & intB) ; + assign subclrBasePin = (intB_SIGNED & ~(intFBq[C_HIGH_BIT]) & intS[C_HIGH_BIT] & intB); + assign subsetBasePin = (~(intB_SIGNED) & intFBq[C_HIGH_BIT] & ~(intS[C_HIGH_BIT])) | (intB_SIGNED & intFBq[C_HIGH_BIT] & ~(intS[C_HIGH_BIT]) & ~(intB)); + assign addsubclrBasePin = (~(ADD) & (intB_SIGNED & ~(intFBq[C_HIGH_BIT]) & intS[C_HIGH_BIT] & intB)) | (ADD & ((~(intB_SIGNED) & ~(intFBq[C_HIGH_BIT]) & intS[C_HIGH_BIT]) | (intB_SIGNED & ~(intFBq[C_HIGH_BIT]) & intS[C_HIGH_BIT] & ~(intB)))) ; + assign addsubsetBasePin = (~(ADD) & ((~intB_SIGNED & intFBq[C_HIGH_BIT] & ~(intS[C_HIGH_BIT])) | (intB_SIGNED & intFBq[C_HIGH_BIT] & ~intS[C_HIGH_BIT] & ~intB))) | (ADD & intB_SIGNED & intFBq[C_HIGH_BIT] & ~intS[C_HIGH_BIT] & intB) ; + + assign addclrBase = (C_HAS_B_SIGNED == 0 ? addclrBaseSig : addclrBasePin); + assign addsetBase = (C_HAS_B_SIGNED == 0 ? addsetBaseSig : addsetBasePin); + assign subclrBase = (C_HAS_B_SIGNED == 0 ? subclrBaseSig : subclrBasePin); + assign subsetBase = (C_HAS_B_SIGNED == 0 ? subsetBaseSig : subsetBasePin); + assign addsubclrBase = (C_HAS_B_SIGNED == 0 ? addsubclrBaseSig : addsubclrBasePin); + assign addsubsetBase = (C_HAS_B_SIGNED == 0 ? addsubsetBaseSig : addsubsetBasePin); + + assign tmpsetsatlogicmsb_sg00 = (C_ADD_MODE == `c_add ? (C_HAS_BYPASS == 1 ? addsetBase & intBYPASSbar : addsetBase) : (C_ADD_MODE == `c_sub ? (C_HAS_BYPASS == 1 ? subsetBase & intBYPASSbar : subsetBase) : (C_HAS_BYPASS == 1 ? addsubsetBase & intBYPASSbar : addsubsetBase) )); + assign tmpsetsatlogicmsb_sg01 = tmpsetsatlogicmsb_sg00 & ~intSCLR ; + assign tmpsetsatlogicmsb_sg10 = tmpsetsatlogicmsb_sg00 | intSSET ; + assign tmpsetsatlogicmsb_sg11c = (tmpsetsatlogicmsb_sg00 | intSSET) & ~intSCLR ; + assign tmpsetsatlogicmsb_sg11s = tmpsetsatlogicmsb_sg00 | intSSET ; + + assign tmpsetsatlogicrest_sg00 = (C_ADD_MODE == `c_add ? (C_HAS_BYPASS == 1 ? addclrBase & intBYPASSbar : addclrBase) : (C_ADD_MODE == `c_sub ? (C_HAS_BYPASS == 1 ? subclrBase & intBYPASSbar : subclrBase) : (C_HAS_BYPASS == 1 ? addsubclrBase & intBYPASSbar : addsubclrBase) )); + assign tmpsetsatlogicrest_sg01 = tmpsetsatlogicrest_sg00 & ~intSCLR ; + assign tmpsetsatlogicrest_sg10 = tmpsetsatlogicrest_sg00 | intSSET ; + assign tmpsetsatlogicrest_sg11c = (tmpsetsatlogicrest_sg00 | intSSET) & ~intSCLR ; + assign tmpsetsatlogicrest_sg11s = tmpsetsatlogicrest_sg00 | intSSET ; + + assign tmpclrsatlogicmsb_sg00 = tmpsetsatlogicrest_sg00 ; + assign tmpclrsatlogicmsb_sg01 = tmpsetsatlogicrest_sg00 | intSCLR ; + assign tmpclrsatlogicmsb_sg10 = tmpsetsatlogicrest_sg00 & ~intSSET ; + assign tmpclrsatlogicmsb_sg11c = tmpsetsatlogicrest_sg00 | intSCLR ; + assign tmpclrsatlogicmsb_sg11s = (tmpsetsatlogicrest_sg00 | intSCLR) & ~intSSET ; + + assign tmpclrsatlogicrest_sg00 = tmpsetsatlogicmsb_sg00 ; + assign tmpclrsatlogicrest_sg01 = tmpsetsatlogicmsb_sg00 | intSCLR ; + assign tmpclrsatlogicrest_sg10 = tmpsetsatlogicmsb_sg00 & ~intSSET ; + assign tmpclrsatlogicrest_sg11c = tmpsetsatlogicmsb_sg00 | intSCLR ; + assign tmpclrsatlogicrest_sg11s = (tmpsetsatlogicmsb_sg00 | intSCLR) & ~intSSET ; + + assign intSSET_TO_MSB = (C_HAS_SSET == 0 ? (C_HAS_SCLR == 0 ? tmpsetsatlogicmsb_sg00 : tmpsetsatlogicmsb_sg01) : + (C_HAS_SCLR == 0 ? tmpsetsatlogicmsb_sg10 : + (C_SYNC_PRIORITY == `c_clear ? tmpsetsatlogicmsb_sg11c : tmpsetsatlogicmsb_sg11s))); + + assign intSCLR_TO_MSB = (C_HAS_SSET == 0 ? (C_HAS_SCLR == 0 ? tmpclrsatlogicmsb_sg00 : tmpclrsatlogicmsb_sg01) : + (C_HAS_SCLR == 0 ? tmpclrsatlogicmsb_sg10 : + (C_SYNC_PRIORITY == `c_clear ? tmpclrsatlogicmsb_sg11c : tmpclrsatlogicmsb_sg11s))); + + assign intSSET_TO_REST = (C_HAS_SSET == 0 ? (C_HAS_SCLR == 0 ? tmpsetsatlogicrest_sg00 : tmpsetsatlogicrest_sg01) : + (C_HAS_SCLR == 0 ? tmpsetsatlogicrest_sg10 : + (C_SYNC_PRIORITY == `c_clear ? tmpsetsatlogicrest_sg11c : tmpsetsatlogicrest_sg11s))); + + assign intSCLR_TO_REST = (C_HAS_SSET == 0 ? (C_HAS_SCLR == 0 ? tmpclrsatlogicrest_sg00 : tmpclrsatlogicrest_sg01) : + (C_HAS_SCLR == 0 ? tmpclrsatlogicrest_sg10 : + (C_SYNC_PRIORITY == `c_clear ? tmpclrsatlogicrest_sg11c : tmpclrsatlogicrest_sg11s))); + + // Finally we are ready to scale the feedback signal... + // If the scaling factor results in NO bits being fed back to the input then we need to handle this! + // This is the case if C_SCALE >= C_OUT_WIDTH + assign intFB[C_OUT_WIDTH-1-(C_SCALE >= C_OUT_WIDTH ? 0 : C_SCALE) : 0] = (C_SCALE >= C_OUT_WIDTH ? {C_OUT_WIDTH{1'b0}} : intFBq[C_OUT_WIDTH-1 : (C_SCALE >= C_OUT_WIDTH ? 0 : C_SCALE)]); + //assign intFB[C_OUT_WIDTH-1 : C_OUT_WIDTH-(C_SCALE == 0 ? 1 : C_SCALE)] = (C_SCALE == 0 ? intFBq[C_OUT_WIDTH-1] : (C_SCALE < C_OUT_WIDTH && (C_B_TYPE == `c_signed || (C_B_TYPE == `c_pin && intB_SIGNED === 1'b1)) ? + // {C_SCALE{intFBq[C_OUT_WIDTH-1]}} : {C_SCALE{1'b0}})); + assign intFB[C_OUT_WIDTH-1 : C_OUT_WIDTH-(C_SCALE == 0 ? 1 : C_SCALE)] = (C_SCALE == 0 ? intFBq[C_OUT_WIDTH-1] : (C_SCALE < C_OUT_WIDTH && (C_B_TYPE == `c_signed || C_B_TYPE == `c_pin) ? + {C_SCALE{intFBq[C_OUT_WIDTH-1]}} : {C_SCALE{1'b0}})); + + + + + initial + begin + #1; + end + +/* helper functions */ + + function defval; + input i; + input hassig; + input val; + begin + if(hassig == 1) + defval = i; + else + defval = val; + end + endfunction + + function [C_B_WIDTH - 1 : 0] to_bitsB; + input [C_B_WIDTH*8 : 1] instring; + integer i; + integer non_null_string; + begin + non_null_string = 0; + for(i = C_B_WIDTH; i > 0; i = i - 1) + begin // Is the string empty? + if(instring[(i*8)] == 0 && + instring[(i*8)-1] == 0 && + instring[(i*8)-2] == 0 && + instring[(i*8)-3] == 0 && + instring[(i*8)-4] == 0 && + instring[(i*8)-5] == 0 && + instring[(i*8)-6] == 0 && + instring[(i*8)-7] == 0 && + non_null_string == 0) + non_null_string = 0; // Use the return value to flag a non-empty string + else + non_null_string = 1; // Non-null character! + end + if(non_null_string == 0) // String IS empty! Just return the value to be all '0's + begin + for(i = C_B_WIDTH; i > 0; i = i - 1) + to_bitsB[i-1] = 0; + end + else + begin + for(i = C_B_WIDTH; i > 0; i = i - 1) + begin // Is this character a '0'? (ASCII = 48 = 00110000) + if(instring[(i*8)] == 0 && + instring[(i*8)-1] == 0 && + instring[(i*8)-2] == 1 && + instring[(i*8)-3] == 1 && + instring[(i*8)-4] == 0 && + instring[(i*8)-5] == 0 && + instring[(i*8)-6] == 0 && + instring[(i*8)-7] == 0) + to_bitsB[i-1] = 0; + // Or is it a '1'? + else if(instring[(i*8)] == 0 && + instring[(i*8)-1] == 0 && + instring[(i*8)-2] == 1 && + instring[(i*8)-3] == 1 && + instring[(i*8)-4] == 0 && + instring[(i*8)-5] == 0 && + instring[(i*8)-6] == 0 && + instring[(i*8)-7] == 1) + to_bitsB[i-1] = 1; + // Or is it a ' '? (a null char - in which case insert a '0') + else if(instring[(i*8)] == 0 && + instring[(i*8)-1] == 0 && + instring[(i*8)-2] == 0 && + instring[(i*8)-3] == 0 && + instring[(i*8)-4] == 0 && + instring[(i*8)-5] == 0 && + instring[(i*8)-6] == 0 && + instring[(i*8)-7] == 0) + to_bitsB[i-1] = 0; + else + begin + $display("Error in %m at time %d ns: non-binary digit in string \"%s\"\nExiting simulation...",$time, instring); + $finish; + end + end + end + end + endfunction + + function max; + input a; + input b; + begin + max = (a > b) ? a : b; + end + endfunction + +endmodule + +`undef c_set +`undef c_clear +`undef c_override +`undef c_no_override +`undef c_add +`undef c_sub +`undef c_add_sub +`undef c_signed +`undef c_unsigned +`undef c_pin +`undef allUKs + + + + + + + + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/C_ACCUM_V6_0.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/C_ACCUM_V6_0.v new file mode 100644 index 0000000..b761f84 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/C_ACCUM_V6_0.v @@ -0,0 +1,663 @@ +// Copyright(C) 2002 by Xilinx, Inc. All rights reserved. +// This text contains proprietary, confidential +// information of Xilinx, Inc., is distributed +// under license from Xilinx, Inc., and may be used, +// copied and/or disclosed only pursuant to the terms +// of a valid license agreement with Xilinx, Inc. This copyright +// notice must be retained as part of this text at all times. + + +/* $Id: C_ACCUM_V6_0.v,v 1.16 2008/09/08 20:06:04 akennedy Exp $ +-- +-- Filename - C_ACCUM_V6_0.v +-- Author - Xilinx +-- Creation - 15 July 1999 +-- +-- Description - This file contains the Verilog behavior for the Baseblocks C_ACCUM_V6_0 module +*/ + +`timescale 1 ns/10 ps + +`define c_set 0 +`define c_clear 1 +`define c_override 0 +`define c_no_override 1 +`define c_add 0 +`define c_sub 1 +`define c_add_sub 2 +`define c_signed 0 +`define c_unsigned 1 +`define c_pin 2 +`define allUKs {(C_HIGH_BIT-C_LOW_BIT)+1{1'bx}} + +module C_ACCUM_V6_0 (B, CLK, ADD, C_IN, B_IN, CE, BYPASS, ACLR, ASET, AINIT, + SCLR, SSET, SINIT, B_SIGNED, OVFL, C_OUT, B_OUT, + Q_OVFL, Q_C_OUT, Q_B_OUT, S, Q); + + parameter C_ADD_MODE = `c_add; + parameter C_AINIT_VAL = "0000000000000000"; + parameter C_BYPASS_ENABLE = `c_no_override; + parameter C_BYPASS_LOW = 0; + parameter C_B_CONSTANT = 0; + parameter C_B_TYPE = `c_unsigned; + parameter C_B_VALUE = "0000000000000000"; + parameter C_B_WIDTH = 16; + parameter C_ENABLE_RLOCS = 1; + parameter C_HAS_ACLR = 0; + parameter C_HAS_ADD = 0; + parameter C_HAS_AINIT = 0; + parameter C_HAS_ASET = 0; + parameter C_HAS_BYPASS = 0; + parameter C_HAS_BYPASS_WITH_CIN = 0; + parameter C_HAS_B_IN = 0; + parameter C_HAS_B_OUT = 0; + parameter C_HAS_B_SIGNED = 0; + parameter C_HAS_CE = 0; + parameter C_HAS_C_IN = 1; + parameter C_HAS_C_OUT = 0; + parameter C_HAS_OVFL = 0; + parameter C_HAS_Q_B_OUT = 0; + parameter C_HAS_Q_C_OUT = 0; + parameter C_HAS_Q_OVFL = 0; + parameter C_HAS_S = 0; + parameter C_HAS_SCLR = 0; + parameter C_HAS_SINIT = 0; + parameter C_HAS_SSET = 0; + parameter C_HIGH_BIT = 15; + parameter C_LOW_BIT = 0; + parameter C_OUT_WIDTH = 16; + parameter C_PIPE_STAGES = 0; + parameter C_SATURATE = 0; + parameter C_SCALE = 0; + parameter C_SINIT_VAL = "0000000000000000"; + parameter C_SYNC_ENABLE = `c_override; + parameter C_SYNC_PRIORITY = `c_clear; + + // Only for internal consumption (prob with MTI otherwise) + parameter outwidth_min_one = C_OUT_WIDTH-1; + parameter bwidth_min_one = C_B_WIDTH-1; + + parameter tempSyncEnable = ((C_SYNC_ENABLE == 0 && C_HAS_CE == 1 && (C_HAS_SSET == 1 || C_HAS_SCLR == 1) && C_SATURATE == 1) ? 1 : C_SYNC_ENABLE); + + input [C_B_WIDTH-1 : 0] B; + input CLK; + input ADD; + input C_IN; + input B_IN; + input CE; + input BYPASS; + input ACLR; + input ASET; + input AINIT; + input SCLR; + input SSET; + input SINIT; + input B_SIGNED; + output OVFL; + output C_OUT; + output B_OUT; + output Q_OVFL; + output Q_C_OUT; + output Q_B_OUT; + output [C_HIGH_BIT : C_LOW_BIT] S; + output [C_HIGH_BIT : C_LOW_BIT] Q; + + + // Internal values to drive signals when input is missing + wire [C_OUT_WIDTH-1 : 0] intS; + wire [C_OUT_WIDTH-1 : 0] intS_sat0; + wire [C_OUT_WIDTH-1 : 0] intS_unsat1; + wire [C_OUT_WIDTH-1 : 0] intS_sinsat1; + wire [C_OUT_WIDTH-1 : 0] intFB; + wire [C_OUT_WIDTH-1 : 0] intFBq; + wire [C_OUT_WIDTH-1 : 0] intFBq_sat0; + wire [C_OUT_WIDTH-1 : 0] intFBq_unsat1; + wire [C_OUT_WIDTH-1 : 0] intFBq_sinsat1; + wire intSCLR; + wire intSSET; + wire intSCLR_TO_ADDER; + wire intSSET_TO_ADDER; + wire intSCLR_TO_MSB; + wire intSSET_TO_MSB; + wire intSCLR_TO_REST; + wire intSSET_TO_REST; + wire intB_SIGNED; + wire intBYPASSbar; + wire intC_OUT; + wire intB_OUT; + wire Q_C_OUT; + wire Q_B_OUT; + wire OVFL; + wire Q_OVFL; + wire intC_OUT_sat0; + wire intB_OUT_sat0; + wire Q_C_OUT_sat0; + wire Q_B_OUT_sat0; + wire OVFL_sat0; + wire Q_OVFL_sat0; + wire intC_OUT_unsat1; + wire intB_OUT_unsat1; + wire Q_C_OUT_unsat1; + wire Q_B_OUT_unsat1; + wire OVFL_unsat1; + wire Q_OVFL_unsat1; + wire intC_OUT_sinsat1; + wire intB_OUT_sinsat1; + wire Q_C_OUT_sinsat1; + wire Q_B_OUT_sinsat1; + wire OVFL_sinsat1; + wire Q_OVFL_sinsat1; + wire intBYPASS_WITH_CIN; // New signal for bypass with Cin mode + wire tempCE; + + + wire tmpsetsatlogic_un00; + wire tmpsetsatlogic_un01; + wire tmpsetsatlogic_un10; + wire tmpsetsatlogic_un11c; + wire tmpsetsatlogic_un11s; + + wire tmpclrsatlogic_un00; + wire tmpclrsatlogic_un01; + wire tmpclrsatlogic_un10; + wire tmpclrsatlogic_un11c; + wire tmpclrsatlogic_un11s; + + wire tmpsetsatlogicmsb_sg00; + wire tmpsetsatlogicmsb_sg01; + wire tmpsetsatlogicmsb_sg10; + wire tmpsetsatlogicmsb_sg11c; + wire tmpsetsatlogicmsb_sg11s; + + wire tmpsetsatlogicrest_sg00; + wire tmpsetsatlogicrest_sg01; + wire tmpsetsatlogicrest_sg10; + wire tmpsetsatlogicrest_sg11c; + wire tmpsetsatlogicrest_sg11s; + + wire tmpclrsatlogicmsb_sg00; + wire tmpclrsatlogicmsb_sg01; + wire tmpclrsatlogicmsb_sg10; + wire tmpclrsatlogicmsb_sg11c; + wire tmpclrsatlogicmsb_sg11s; + + wire tmpclrsatlogicrest_sg00; + wire tmpclrsatlogicrest_sg01; + wire tmpclrsatlogicrest_sg10; + wire tmpclrsatlogicrest_sg11c; + wire tmpclrsatlogicrest_sg11s; + + wire addsetBaseSig ; + wire subsetBaseSig ; + wire addsubsetBaseSig ; + wire addclrBaseSig ; + wire subclrBaseSig ; + wire addsubclrBaseSig ; + + wire addsetBasePin ; + wire subsetBasePin ; + wire addsubsetBasePin ; + wire addclrBasePin ; + wire subclrBasePin ; + wire addsubclrBasePin ; + + wire addsetBase ; + wire subsetBase ; + wire addsubsetBase ; + wire addclrBase ; + wire subclrBase ; + wire addsubclrBase ; + + wire intCE ; + wire intB ; + wire [C_B_WIDTH : 0] intBconst; + + wire [C_HIGH_BIT : C_LOW_BIT] Q = intFBq; + wire [C_HIGH_BIT : C_LOW_BIT] S = (C_HAS_S == 1 ? intS : `allUKs); + wire C_OUT = (C_HAS_C_OUT == 1 ? intC_OUT : 1'bx); + wire B_OUT = (C_HAS_B_OUT == 1 ? intB_OUT : 1'bx); + parameter temp_C_SCALE = (C_SCALE == 0 ? 1'b1 : C_SCALE); + + + // Sort out default values for missing ports + + assign intB_SIGNED = defval(B_SIGNED, C_HAS_B_SIGNED, 0); + assign intBYPASSbar = (C_BYPASS_LOW == 1 ? BYPASS : ~BYPASS); + assign intSCLR = defval(SCLR, C_HAS_SCLR, 0); + assign intSSET = defval(SSET, C_HAS_SSET, 0); + assign intBYPASS_WITH_CIN = C_HAS_BYPASS_WITH_CIN; //assign new c_has_bypass_with_cin parameter to internal wire + assign intBconst = (C_B_CONSTANT === 1) ? to_bitsB(C_B_VALUE) : B; + + // Now make up the design from other baseblox + // An addsub for when no saturation logic is required... + C_ADDSUB_V6_0 #(C_ADD_MODE, + C_AINIT_VAL, + (C_B_TYPE == `c_pin )? `c_signed : C_B_TYPE, + C_OUT_WIDTH, + C_BYPASS_ENABLE, + C_BYPASS_LOW, + C_B_CONSTANT, + C_B_TYPE, + C_B_VALUE, + C_B_WIDTH, + C_ENABLE_RLOCS, + C_HAS_ACLR, + C_HAS_ADD, + C_HAS_AINIT, + C_HAS_ASET, + C_HAS_B_SIGNED, + C_HAS_BYPASS, + C_HAS_BYPASS_WITH_CIN, + C_HAS_B_IN, + C_HAS_B_OUT, + C_HAS_B_SIGNED, + C_HAS_CE, + C_HAS_C_IN, + C_HAS_C_OUT, + C_HAS_OVFL, + 1, + C_HAS_Q_B_OUT, + C_HAS_Q_C_OUT, + C_HAS_Q_OVFL, + C_HAS_S, + C_HAS_SCLR, + C_HAS_SINIT, + C_HAS_SSET, + outwidth_min_one, + 1, + 0, + C_OUT_WIDTH, + C_PIPE_STAGES, + C_SINIT_VAL, + C_SYNC_ENABLE, + C_SYNC_PRIORITY) + sat0_addsub(.A(intFB), .B(B), .CLK(CLK), .ADD(ADD), + .C_IN(C_IN), .B_IN(B_IN), .CE(CE), .BYPASS(BYPASS), + .ACLR(ACLR), .ASET(ASET), .AINIT(AINIT), + .SCLR(SCLR), .SSET(SSET), .SINIT(SINIT), + .A_SIGNED(B_SIGNED), .B_SIGNED(B_SIGNED), + .OVFL(OVFL_sat0), .C_OUT(intC_OUT_sat0), + .B_OUT(intB_OUT_sat0), .Q_OVFL(Q_OVFL_sat0), + .Q_C_OUT(Q_C_OUT_sat0), .Q_B_OUT(Q_B_OUT_sat0), + .S(intS_sat0), .Q(intFBq_sat0)); + + + // Another addsub for when saturation logic IS required, but only for unsigned data + C_ADDSUB_V6_0 #(C_ADD_MODE, + C_AINIT_VAL, + C_B_TYPE, + C_OUT_WIDTH, + C_BYPASS_ENABLE, + C_BYPASS_LOW, + C_B_CONSTANT, + C_B_TYPE, + C_B_VALUE, + C_B_WIDTH, + C_ENABLE_RLOCS, + 0, + C_HAS_ADD, + 0, + 0, + C_HAS_B_SIGNED, + C_HAS_BYPASS, + C_HAS_BYPASS_WITH_CIN, + C_HAS_B_IN, + 1, + C_HAS_B_SIGNED, + C_HAS_CE, + C_HAS_C_IN, + 1, + C_HAS_OVFL, + 1, + C_HAS_Q_B_OUT, + C_HAS_Q_C_OUT, + C_HAS_Q_OVFL, + C_HAS_S, + 1, + 0, + 1, + outwidth_min_one, + 1, + 0, + C_OUT_WIDTH, + C_PIPE_STAGES, + C_SINIT_VAL, + tempSyncEnable, + C_SYNC_PRIORITY) + unsat1_addsub(.A(intFB), .B(B), .CLK(CLK), .ADD(ADD), + .C_IN(C_IN), .B_IN(B_IN), .CE(intCE), .BYPASS(BYPASS), + .ACLR(ACLR), .ASET(ASET), .AINIT(AINIT), + .SCLR(intSCLR_TO_ADDER), .SSET(intSSET_TO_ADDER), .SINIT(SINIT), + .A_SIGNED(B_SIGNED), .B_SIGNED(B_SIGNED), + .OVFL(OVFL_unsat1), .C_OUT(intC_OUT_unsat1), + .B_OUT(intB_OUT_unsat1), .Q_OVFL(Q_OVFL_unsat1), + .Q_C_OUT(Q_C_OUT_unsat1), .Q_B_OUT(Q_B_OUT_unsat1), + .S(intS_unsat1), .Q(intFBq_unsat1)); + + // Another addsub for when saturation logic IS required, but for signed data + C_ADDSUB_V6_0 #(C_ADD_MODE, + C_AINIT_VAL, + C_B_TYPE, + C_OUT_WIDTH, + C_BYPASS_ENABLE, + C_BYPASS_LOW, + C_B_CONSTANT, + C_B_TYPE, + C_B_VALUE, + C_B_WIDTH, + C_ENABLE_RLOCS, + C_HAS_ACLR, + C_HAS_ADD, + C_HAS_AINIT, + C_HAS_ASET, + C_HAS_B_SIGNED, + C_HAS_BYPASS, + C_HAS_BYPASS_WITH_CIN, + C_HAS_B_IN, + 1, + C_HAS_B_SIGNED, + C_HAS_CE, + C_HAS_C_IN, + 1, + C_HAS_OVFL, + 0, + C_HAS_Q_B_OUT, + C_HAS_Q_C_OUT, + C_HAS_Q_OVFL, + 1, + C_HAS_SCLR, + C_HAS_SINIT, + C_HAS_SSET, + outwidth_min_one, + 1, + 0, + C_OUT_WIDTH, + C_PIPE_STAGES, + C_SINIT_VAL, + tempSyncEnable, // wasC_SYNC_ENABLE, + C_SYNC_PRIORITY) + sinsat1_addsub(.A(intFB), .B(B), .CLK(CLK), .ADD(ADD), + .C_IN(C_IN), .B_IN(B_IN), .CE(intCE), .BYPASS(BYPASS), + .ACLR(ACLR), .ASET(ASET), .AINIT(AINIT), + .SCLR(SCLR), .SSET(SSET), .SINIT(SINIT), + .A_SIGNED(B_SIGNED), .B_SIGNED(B_SIGNED), + .OVFL(OVFL_sinsat1), .C_OUT(intC_OUT_sinsat1), + .B_OUT(intB_OUT_sinsat1), .Q_OVFL(Q_OVFL_sinsat1), + .Q_C_OUT(Q_C_OUT_sinsat1), .Q_B_OUT(Q_B_OUT_sinsat1), + .S(intS_sinsat1), .Q()); + + // Registers for output of the last addsub + C_REG_FD_V6_0 #(00000000, //C_AINIT_VAL[(C_OUT_WIDTH*8)-1 : (C_OUT_WIDTH-1)*8], + C_ENABLE_RLOCS, + 0, + 0, + 0, + C_HAS_CE, + 1, + 0, + 1, + 00000000,//C_SINIT_VAL[(C_OUT_WIDTH*8)-1 : (C_OUT_WIDTH-1)*8], + tempSyncEnable, //C_SYNC_ENABLE, + C_SYNC_PRIORITY, + 1) + msb_reg(.D(intS_sinsat1[outwidth_min_one]), .CLK(CLK), + .CE(intCE), .ACLR(ACLR), .ASET(ASET), .AINIT(AINIT), + .SCLR(intSCLR_TO_MSB), .SSET(intSSET_TO_MSB), + .SINIT(SINIT), .Q(intFBq_sinsat1[outwidth_min_one])); + + // Need the ?: on the value of C_B_WIDTH in case it == 1 + C_REG_FD_V6_0 #(00000000, // C_AINIT_VAL[(((C_OUT_WIDTH == 1 ? 2 : C_OUT_WIDTH)-1)*8)-1 : 0], + C_ENABLE_RLOCS, + 0, + 0, + 0, + C_HAS_CE, + 1, + 0, + 1, + 00000000, //C_SINIT_VAL[(((C_OUT_WIDTH == 1 ? 2 : C_OUT_WIDTH)-1)*8)-1 : 0], + tempSyncEnable, //C_SYNC_ENABLE, + C_SYNC_PRIORITY, + (C_OUT_WIDTH == 1 ? 2 : C_OUT_WIDTH)-1) + rest_reg(.D(intS_sinsat1[(C_OUT_WIDTH == 1 ? 2 : C_OUT_WIDTH)-2 : 0]), .CLK(CLK), + .CE(intCE), .ACLR(ACLR), .ASET(ASET), .AINIT(AINIT), + .SCLR((C_B_WIDTH == 1 ? intSCLR_TO_MSB : intSCLR_TO_REST)), .SSET((C_B_WIDTH == 1 ? intSSET_TO_MSB : intSSET_TO_REST)), + .SINIT(SINIT), .Q(intFBq_sinsat1[(C_OUT_WIDTH == 1 ? 2 : C_OUT_WIDTH)-2 : 0])); + + + // Sort out the choices from all these output signals... + assign tempCE = ((C_SYNC_ENABLE == 0 && C_HAS_CE == 1 && (C_HAS_SSET == 1 || C_HAS_SCLR == 1) && C_SATURATE == 1) ? (CE | intSSET | intSCLR) : CE); + assign intCE = (C_SATURATE == 0 ? CE : (((C_HAS_BYPASS == 1)&&(C_BYPASS_LOW == 1)) ? ((C_BYPASS_ENABLE == `c_override) ? (~BYPASS | tempCE) : tempCE) : (((C_HAS_BYPASS == 1)&&(C_BYPASS_LOW == 0)) ? ((C_BYPASS_ENABLE == `c_override) ? (BYPASS | tempCE) : tempCE) : tempCE))) ; + + assign intC_OUT = (C_SATURATE == 0 ? intC_OUT_sat0 : (C_B_TYPE == `c_unsigned ? intC_OUT_unsat1 : intC_OUT_sinsat1)); + assign intB_OUT = (C_SATURATE == 0 ? intB_OUT_sat0 : (C_B_TYPE == `c_unsigned ? intB_OUT_unsat1 : intB_OUT_sinsat1)); + assign OVFL = (C_SATURATE == 0 ? OVFL_sat0 : (C_B_TYPE == `c_unsigned ? OVFL_unsat1 : OVFL_sinsat1)); + assign Q_C_OUT = (C_SATURATE == 0 ? Q_C_OUT_sat0 : (C_B_TYPE == `c_unsigned ? Q_C_OUT_unsat1 : Q_C_OUT_sinsat1)); + assign Q_B_OUT = (C_SATURATE == 0 ? Q_B_OUT_sat0 : (C_B_TYPE == `c_unsigned ? Q_B_OUT_unsat1 : Q_B_OUT_sinsat1)); + assign Q_OVFL = (C_SATURATE == 0 ? Q_OVFL_sat0 : (C_B_TYPE == `c_unsigned ? Q_OVFL_unsat1 : Q_OVFL_sinsat1)); + assign intS = (C_SATURATE == 0 ? intS_sat0 : (C_B_TYPE == `c_unsigned ? intS_unsat1 : intS_sinsat1)); + assign intFBq = (C_SATURATE == 0 ? intFBq_sat0 : (C_B_TYPE == `c_unsigned ? intFBq_unsat1 : intFBq_sinsat1)); + + + // COMPLEX decisions on what to feed to the local control sigs... + // The signal name suffices denote: un = unsigned, sg = signed, 00 = has neither sset nor sclr, 01 = has sclr only etc + // 11c = has bot sset and sclr and sclr dominates, 11s = sset dominates, etc + + // Unsigned version first + assign tmpsetsatlogic_un00 = (C_ADD_MODE == `c_add ? intC_OUT : (C_ADD_MODE == `c_sub ? intSSET : (intC_OUT & ADD))); + assign tmpsetsatlogic_un01 = (C_ADD_MODE == `c_add ? (intC_OUT & ~intSCLR) : (C_ADD_MODE == `c_sub ? intSSET : (intC_OUT & ~intSCLR & ADD))); + assign tmpsetsatlogic_un10 = (C_ADD_MODE == `c_add ? (intC_OUT | intSSET) : (C_ADD_MODE == `c_sub ? intSSET : ((intC_OUT & ADD) | intSSET))); + assign tmpsetsatlogic_un11c = (C_ADD_MODE == `c_add ? (~intSCLR & (intC_OUT | intSSET)) : (C_ADD_MODE == `c_sub ? (~intSCLR & intSSET) : ((~intSCLR & intC_OUT & ADD) | (intSSET & ~intSCLR)))); + assign tmpsetsatlogic_un11s = (C_ADD_MODE == `c_add ? ((~intSCLR && intC_OUT) | intSSET) : (C_ADD_MODE == `c_sub ? intSSET : ((~intSCLR & intC_OUT & ADD) | intSSET))); + +// assign tmpclrsatlogic_un00 = (C_ADD_MODE == `c_add ? intSCLR : (C_ADD_MODE == `c_sub ? ~intB_OUT : (~intC_OUT & ~ADD))); + assign tmpclrsatlogic_un00 = (C_ADD_MODE == `c_add ? intSCLR : (C_ADD_MODE == `c_sub ? (C_HAS_BYPASS == 1 ? (C_BYPASS_LOW == 1 ? (~intB_OUT & BYPASS) : (~intB_OUT & ~BYPASS)): ~intB_OUT) : (C_HAS_BYPASS == 1 ? (C_BYPASS_LOW ==1 ? ((~intC_OUT & ~ADD) & BYPASS) : ((~intC_OUT & ~ADD) & ~BYPASS)) : (~intC_OUT & ~ADD)))); +// assign tmpclrsatlogic_un01 = (C_ADD_MODE == `c_add ? intSCLR : (C_ADD_MODE == `c_sub ? (~intB_OUT | intSCLR) : (intSCLR | (~intC_OUT & ~ADD)))); + assign tmpclrsatlogic_un01 = (C_ADD_MODE == `c_add ? intSCLR : (C_ADD_MODE == `c_sub ? (C_HAS_BYPASS == 1 ? (C_BYPASS_LOW == 1 ? ((~intB_OUT & BYPASS) | intSCLR) : ((~intB_OUT & ~BYPASS) | intSCLR)) : (~intB_OUT | intSCLR)) : (C_HAS_BYPASS == 1 ? (C_BYPASS_LOW ==1 ? (intSCLR | ((~intC_OUT & ~ADD) & BYPASS)) : (intSCLR | ((~intC_OUT & ~ADD) & ~BYPASS))) : (intSCLR | (~intC_OUT & ~ADD))))); +// assign tmpclrsatlogic_un10 = (C_ADD_MODE == `c_add ? intSCLR : (C_ADD_MODE == `c_sub ? (~intB_OUT & ~intSSET) : (~intSSET & ~intC_OUT & ~ADD))); + assign tmpclrsatlogic_un10 = (C_ADD_MODE == `c_add ? intSCLR : (C_ADD_MODE == `c_sub ? (C_HAS_BYPASS == 1 ? (C_BYPASS_LOW == 1 ? ((~intB_OUT & BYPASS) & ~intSSET) : ((~intB_OUT & ~BYPASS) & ~intSSET)): (~intB_OUT & ~intSSET)) : ((C_HAS_BYPASS == 1 ? (C_BYPASS_LOW ==1 ? (~intSSET & (~intC_OUT & ~ADD) & BYPASS) : (~intSSET & ((~intC_OUT & ~ADD) & ~BYPASS))) : (~intSSET & ~intC_OUT & ~ADD))))); +// assign tmpclrsatlogic_un11c = (C_ADD_MODE == `c_add ? intSCLR : (C_ADD_MODE == `c_sub ? (intSCLR | (~intB_OUT & ~intSSET)) : (intSCLR | (~intSSET & ~intC_OUT & ~ADD)))); + assign tmpclrsatlogic_un11c = (C_ADD_MODE == `c_add ? intSCLR : (C_ADD_MODE == `c_sub ? (C_HAS_BYPASS == 1 ? (C_BYPASS_LOW == 1 ? (intSCLR | ((~intB_OUT & BYPASS) & ~intSSET)) : (intSCLR | ((~intB_OUT & ~BYPASS) & ~intSSET))) : (intSCLR | (~intB_OUT & ~intSSET))) : ((C_HAS_BYPASS == 1 ? (C_BYPASS_LOW ==1 ? (intSCLR | ((~intSSET & ~intC_OUT & ~ADD) & BYPASS)) : (intSCLR | ((~intSSET & ~intC_OUT & ~ADD) & ~BYPASS))) : (intSCLR | (~intSSET & ~intC_OUT & ~ADD))))));// assign tmpclrsatlogic_un11s = (C_ADD_MODE == `c_add ? (intSCLR & ~intSSET) : (C_ADD_MODE == `c_sub ? (~intSSET & (intSCLR | ~intB_OUT)) : ((intSCLR & ~intSSET) | (~intSSET & ~intC_OUT & ~ADD)))); + assign tmpclrsatlogic_un11s = (C_ADD_MODE == `c_add ? (intSCLR & ~intSSET) : (C_ADD_MODE == `c_sub ? (C_HAS_BYPASS == 1 ? (C_BYPASS_LOW == 1 ? (~intSSET & (intSCLR | (~intB_OUT & BYPASS))) : (~intSSET & (intSCLR | (~intB_OUT & ~BYPASS)))) : (~intSSET & (intSCLR | ~intB_OUT))) : (C_HAS_BYPASS == 1 ? (C_BYPASS_LOW ==1 ? ((intSCLR & ~intSSET) | (~intSSET & ((~intC_OUT & ~ADD) & BYPASS))): ((intSCLR & ~intSSET) | (~intSSET & ((~intC_OUT & ~ADD) & ~BYPASS)))) : ((intSCLR & ~intSSET) | (~intSSET & ~intC_OUT & ~ADD))))); + + assign intSSET_TO_ADDER = (C_HAS_SSET == 0 ? (C_HAS_SCLR == 0 ? tmpsetsatlogic_un00 : tmpsetsatlogic_un01) : + (C_HAS_SCLR == 0 ? tmpsetsatlogic_un10 : + (C_SYNC_PRIORITY == `c_clear ? tmpsetsatlogic_un11c : tmpsetsatlogic_un11s))); + + assign intSCLR_TO_ADDER = (C_HAS_SSET == 0 ? (C_HAS_SCLR == 0 ? tmpclrsatlogic_un00 : tmpclrsatlogic_un01) : + (C_HAS_SCLR == 0 ? tmpclrsatlogic_un10 : + (C_SYNC_PRIORITY == `c_clear ? tmpclrsatlogic_un11c : tmpclrsatlogic_un11s))); + + // Now all the signals for the signed version + assign intB = intBconst[C_B_WIDTH-1]; + //assign intB = (C_B_CONSTANT == 1 ? (C_B_VALUE[(C_B_WIDTH*8)-1 : (C_B_WIDTH-1)*8] == "0" ? 1'b0 : 1'b1) : B[C_B_WIDTH-1]) ; + + assign addclrBaseSig = (intS[C_HIGH_BIT] & ~(intFBq[C_HIGH_BIT]) & ~(intB)) ; + assign addsetBaseSig = (~(intS[C_HIGH_BIT]) & intFBq[C_HIGH_BIT] & intB) ; + assign subclrBaseSig = (intS[C_HIGH_BIT] & ~(intFBq[C_HIGH_BIT]) & intB) ; + assign subsetBaseSig = (~(intS[C_HIGH_BIT]) & intFBq[C_HIGH_BIT] & ~(intB)) ; + assign addsubclrBaseSig = ((~ADD & (intS[C_HIGH_BIT] & ~(intFBq[C_HIGH_BIT]) & intB)) | (ADD & (intS[C_HIGH_BIT] & ~(intFBq[C_HIGH_BIT]) & ~(intB)))) ; + assign addsubsetBaseSig = ((~ADD & (~(intS[C_HIGH_BIT]) & intFBq[C_HIGH_BIT] & ~(intB))) | (ADD & (~(intS[C_HIGH_BIT]) & intFBq[C_HIGH_BIT] & intB))) ; + + assign addclrBasePin = (~(intB_SIGNED) & ~(intFBq[C_HIGH_BIT]) & intS[C_HIGH_BIT]) | (intB_SIGNED & ~(intFBq[C_HIGH_BIT]) & intS[C_HIGH_BIT] & ~(intB)); + assign addsetBasePin = (intB_SIGNED & intFBq[C_HIGH_BIT] & ~(intS[C_HIGH_BIT]) & intB) ; + assign subclrBasePin = (intB_SIGNED & ~(intFBq[C_HIGH_BIT]) & intS[C_HIGH_BIT] & intB); + assign subsetBasePin = (~(intB_SIGNED) & intFBq[C_HIGH_BIT] & ~(intS[C_HIGH_BIT])) | (intB_SIGNED & intFBq[C_HIGH_BIT] & ~(intS[C_HIGH_BIT]) & ~(intB)); + assign addsubclrBasePin = (~(ADD) & (intB_SIGNED & ~(intFBq[C_HIGH_BIT]) & intS[C_HIGH_BIT] & intB)) | (ADD & ((~(intB_SIGNED) & ~(intFBq[C_HIGH_BIT]) & intS[C_HIGH_BIT]) | (intB_SIGNED & ~(intFBq[C_HIGH_BIT]) & intS[C_HIGH_BIT] & ~(intB)))) ; + assign addsubsetBasePin = (~(ADD) & ((~intB_SIGNED & intFBq[C_HIGH_BIT] & ~(intS[C_HIGH_BIT])) | (intB_SIGNED & intFBq[C_HIGH_BIT] & ~intS[C_HIGH_BIT] & ~intB))) | (ADD & intB_SIGNED & intFBq[C_HIGH_BIT] & ~intS[C_HIGH_BIT] & intB) ; + + assign addclrBase = (C_HAS_B_SIGNED == 0 ? addclrBaseSig : addclrBasePin); + assign addsetBase = (C_HAS_B_SIGNED == 0 ? addsetBaseSig : addsetBasePin); + assign subclrBase = (C_HAS_B_SIGNED == 0 ? subclrBaseSig : subclrBasePin); + assign subsetBase = (C_HAS_B_SIGNED == 0 ? subsetBaseSig : subsetBasePin); + assign addsubclrBase = (C_HAS_B_SIGNED == 0 ? addsubclrBaseSig : addsubclrBasePin); + assign addsubsetBase = (C_HAS_B_SIGNED == 0 ? addsubsetBaseSig : addsubsetBasePin); + + assign tmpsetsatlogicmsb_sg00 = (C_ADD_MODE == `c_add ? (C_HAS_BYPASS == 1 ? addsetBase & intBYPASSbar : addsetBase) : (C_ADD_MODE == `c_sub ? (C_HAS_BYPASS == 1 ? subsetBase & intBYPASSbar : subsetBase) : (C_HAS_BYPASS == 1 ? addsubsetBase & intBYPASSbar : addsubsetBase) )); + assign tmpsetsatlogicmsb_sg01 = tmpsetsatlogicmsb_sg00 & ~intSCLR ; + assign tmpsetsatlogicmsb_sg10 = tmpsetsatlogicmsb_sg00 | intSSET ; + assign tmpsetsatlogicmsb_sg11c = (tmpsetsatlogicmsb_sg00 | intSSET) & ~intSCLR ; + assign tmpsetsatlogicmsb_sg11s = (tmpsetsatlogicmsb_sg00 & ~intSCLR) | intSSET ; //new code!! + + assign tmpsetsatlogicrest_sg00 = (C_ADD_MODE == `c_add ? (C_HAS_BYPASS == 1 ? addclrBase & intBYPASSbar : addclrBase) : (C_ADD_MODE == `c_sub ? (C_HAS_BYPASS == 1 ? subclrBase & intBYPASSbar : subclrBase) : (C_HAS_BYPASS == 1 ? addsubclrBase & intBYPASSbar : addsubclrBase) )); + assign tmpsetsatlogicrest_sg01 = tmpsetsatlogicrest_sg00 & ~intSCLR ; + assign tmpsetsatlogicrest_sg10 = tmpsetsatlogicrest_sg00 | intSSET ; + assign tmpsetsatlogicrest_sg11c = (tmpsetsatlogicrest_sg00 | intSSET) & ~intSCLR ; + assign tmpsetsatlogicrest_sg11s = (tmpsetsatlogicrest_sg00 & (~intSCLR)) | intSSET ; + + assign tmpclrsatlogicmsb_sg00 = tmpsetsatlogicrest_sg00 ; + assign tmpclrsatlogicmsb_sg01 = tmpsetsatlogicrest_sg00 | intSCLR ; + assign tmpclrsatlogicmsb_sg10 = tmpsetsatlogicrest_sg00 & ~intSSET ; + assign tmpclrsatlogicmsb_sg11c = (tmpsetsatlogicrest_sg00 & ~intSSET) | intSCLR ; // not sure about the intSSET in this one! + assign tmpclrsatlogicmsb_sg11s = (tmpsetsatlogicrest_sg00 | intSCLR) & ~intSSET ; + + assign tmpclrsatlogicrest_sg00 = tmpsetsatlogicmsb_sg00 ; + assign tmpclrsatlogicrest_sg01 = tmpsetsatlogicmsb_sg00 | intSCLR ; + assign tmpclrsatlogicrest_sg10 = tmpsetsatlogicmsb_sg00 & ~intSSET ; + assign tmpclrsatlogicrest_sg11c = (tmpsetsatlogicmsb_sg00 & ~intSSET) | intSCLR ; // added to fix reg override sync bug + assign tmpclrsatlogicrest_sg11s = (tmpsetsatlogicmsb_sg00 | intSCLR) & ~intSSET ; + + assign intSSET_TO_MSB = (C_HAS_SSET == 0 ? (C_HAS_SCLR == 0 ? tmpsetsatlogicmsb_sg00 : tmpsetsatlogicmsb_sg01) : + (C_HAS_SCLR == 0 ? tmpsetsatlogicmsb_sg10 : + (C_SYNC_PRIORITY == `c_clear ? tmpsetsatlogicmsb_sg11c : tmpsetsatlogicmsb_sg11s))); + + assign intSCLR_TO_MSB = (C_HAS_SSET == 0 ? (C_HAS_SCLR == 0 ? tmpclrsatlogicmsb_sg00 : tmpclrsatlogicmsb_sg01) : + (C_HAS_SCLR == 0 ? tmpclrsatlogicmsb_sg10 : + (C_SYNC_PRIORITY == `c_clear ? tmpclrsatlogicmsb_sg11c : tmpclrsatlogicmsb_sg11s))); + + assign intSSET_TO_REST = (C_HAS_SSET == 0 ? (C_HAS_SCLR == 0 ? tmpsetsatlogicrest_sg00 : tmpsetsatlogicrest_sg01) : + (C_HAS_SCLR == 0 ? tmpsetsatlogicrest_sg10 : + (C_SYNC_PRIORITY == `c_clear ? tmpsetsatlogicrest_sg11c : tmpsetsatlogicrest_sg11s))); + + assign intSCLR_TO_REST = (C_HAS_SSET == 0 ? (C_HAS_SCLR == 0 ? tmpclrsatlogicrest_sg00 : tmpclrsatlogicrest_sg01) : + (C_HAS_SCLR == 0 ? tmpclrsatlogicrest_sg10 : + (C_SYNC_PRIORITY == `c_clear ? tmpclrsatlogicrest_sg11c : tmpclrsatlogicrest_sg11s))); + + // Finally we are ready to scale the feedback signal... + // If the scaling factor results in NO bits being fed back to the input then we need to handle this! + // This is the case if C_SCALE >= C_OUT_WIDTH + assign intFB[C_OUT_WIDTH-1-(C_SCALE >= C_OUT_WIDTH ? 0 : C_SCALE) : 0] = (C_SCALE >= C_OUT_WIDTH ? {C_OUT_WIDTH{1'b0}} : intFBq[C_OUT_WIDTH-1 : (C_SCALE >= C_OUT_WIDTH ? 0 : C_SCALE)]); + //assign intFB[C_OUT_WIDTH-1 : C_OUT_WIDTH-(C_SCALE == 0 ? 1 : C_SCALE)] = (C_SCALE == 0 ? intFBq[C_OUT_WIDTH-1] : (C_SCALE < C_OUT_WIDTH && (C_B_TYPE == `c_signed || (C_B_TYPE == `c_pin && intB_SIGNED === 1'b1)) ? + // {C_SCALE{intFBq[C_OUT_WIDTH-1]}} : {C_SCALE{1'b0}})); + assign intFB[C_OUT_WIDTH-1 : C_OUT_WIDTH-(C_SCALE == 0 ? 1 : C_SCALE)] = (C_SCALE == 0 ? intFBq[C_OUT_WIDTH-1] : (C_SCALE < C_OUT_WIDTH && (C_B_TYPE == `c_signed || C_B_TYPE == `c_pin) ? + {temp_C_SCALE{intFBq[C_OUT_WIDTH-1]}} : {temp_C_SCALE{1'b0}})); + + + + + initial + begin + #1; + end + +/* helper functions */ + + function defval; + input i; + input hassig; + input val; + begin + if(hassig == 1) + defval = i; + else + defval = val; + end + endfunction + + function [C_B_WIDTH - 1 : 0] to_bitsB; + input [C_B_WIDTH*8 : 1] instring; + integer i; + integer non_null_string; + begin + non_null_string = 0; + for(i = C_B_WIDTH; i > 0; i = i - 1) + begin // Is the string empty? + if(instring[(i*8)] == 0 && + instring[(i*8)-1] == 0 && + instring[(i*8)-2] == 0 && + instring[(i*8)-3] == 0 && + instring[(i*8)-4] == 0 && + instring[(i*8)-5] == 0 && + instring[(i*8)-6] == 0 && + instring[(i*8)-7] == 0 && + non_null_string == 0) + non_null_string = 0; // Use the return value to flag a non-empty string + else + non_null_string = 1; // Non-null character! + end + if(non_null_string == 0) // String IS empty! Just return the value to be all '0's + begin + for(i = C_B_WIDTH; i > 0; i = i - 1) + to_bitsB[i-1] = 0; + end + else + begin + for(i = C_B_WIDTH; i > 0; i = i - 1) + begin // Is this character a '0'? (ASCII = 48 = 00110000) + if(instring[(i*8)] == 0 && + instring[(i*8)-1] == 0 && + instring[(i*8)-2] == 1 && + instring[(i*8)-3] == 1 && + instring[(i*8)-4] == 0 && + instring[(i*8)-5] == 0 && + instring[(i*8)-6] == 0 && + instring[(i*8)-7] == 0) + to_bitsB[i-1] = 0; + // Or is it a '1'? + else if(instring[(i*8)] == 0 && + instring[(i*8)-1] == 0 && + instring[(i*8)-2] == 1 && + instring[(i*8)-3] == 1 && + instring[(i*8)-4] == 0 && + instring[(i*8)-5] == 0 && + instring[(i*8)-6] == 0 && + instring[(i*8)-7] == 1) + to_bitsB[i-1] = 1; + // Or is it a ' '? (a null char - in which case insert a '0') + else if(instring[(i*8)] == 0 && + instring[(i*8)-1] == 0 && + instring[(i*8)-2] == 0 && + instring[(i*8)-3] == 0 && + instring[(i*8)-4] == 0 && + instring[(i*8)-5] == 0 && + instring[(i*8)-6] == 0 && + instring[(i*8)-7] == 0) + to_bitsB[i-1] = 0; + else + begin + $display("Error in %m at time %d ns: non-binary digit in string \"%s\"\nExiting simulation...",$time, instring); + $finish; + end + end + end + end + endfunction + + function max; + input a; + input b; + begin + max = (a > b) ? a : b; + end + endfunction + +endmodule + +`undef c_set +`undef c_clear +`undef c_override +`undef c_no_override +`undef c_add +`undef c_sub +`undef c_add_sub +`undef c_signed +`undef c_unsigned +`undef c_pin +`undef allUKs + + + + + + + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/C_ACCUM_V7_0.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/C_ACCUM_V7_0.v new file mode 100644 index 0000000..deef433 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/C_ACCUM_V7_0.v @@ -0,0 +1,692 @@ +// Copyright(C) 2003 by Xilinx, Inc. All rights reserved. +// This text/file contains proprietary, confidential +// information of Xilinx, Inc., is distributed under license +// from Xilinx, Inc., and may be used, copied and/or +// disclosed only pursuant to the terms of a valid license +// agreement with Xilinx, Inc. Xilinx hereby grants you +// a license to use this text/file solely for design, simulation, +// implementation and creation of design files limited +// to Xilinx devices or technologies. Use with non-Xilinx +// devices or technologies is expressly prohibited and +// immediately terminates your license unless covered by +// a separate agreement. +// +// Xilinx is providing this design, code, or information +// "as is" solely for use in developing programs and +// solutions for Xilinx devices. By providing this design, +// code, or information as one possible implementation of +// this feature, application or standard, Xilinx is making no +// representation that this implementation is free from any +// claims of infringement. You are responsible for +// obtaining any rights you may require for your implementation. +// Xilinx expressly disclaims any warranty whatsoever with +// respect to the adequacy of the implementation, including +// but not limited to any warranties or representations that this +// implementation is free from claims of infringement, implied +// warranties of merchantability or fitness for a particular +// purpose. +// +// Xilinx products are not intended for use in life support +// appliances, devices, or systems. Use in such applications are +// expressly prohibited. +// +// This copyright and support notice must be retained as part +// of this text at all times. (c) Copyright 1995-2003 Xilinx, Inc. +// All rights reserved. + + + +/* $Id: C_ACCUM_V7_0.v,v 1.13 2008/09/08 20:06:13 akennedy Exp $ +-- +-- Filename - C_ACCUM_V7_0.v +-- Author - Xilinx +-- Creation - 15 July 1999 +-- +-- Description - This file contains the Verilog behavior for the Baseblocks C_ACCUM_V7_0 module +*/ + +`timescale 1 ns/10 ps + +`define c_set 0 +`define c_clear 1 +`define c_override 0 +`define c_no_override 1 +`define c_add 0 +`define c_sub 1 +`define c_add_sub 2 +`define c_signed 0 +`define c_unsigned 1 +`define c_pin 2 +`define allUKs {(C_HIGH_BIT-C_LOW_BIT)+1{1'bx}} + +module C_ACCUM_V7_0 (B, CLK, ADD, C_IN, B_IN, CE, BYPASS, ACLR, ASET, AINIT, + SCLR, SSET, SINIT, B_SIGNED, OVFL, C_OUT, B_OUT, + Q_OVFL, Q_C_OUT, Q_B_OUT, S, Q); + + parameter C_ADD_MODE = `c_add; + parameter C_AINIT_VAL = "0000000000000000"; + parameter C_BYPASS_ENABLE = `c_no_override; + parameter C_BYPASS_LOW = 0; + parameter C_B_CONSTANT = 0; + parameter C_B_TYPE = `c_unsigned; + parameter C_B_VALUE = "0000000000000000"; + parameter C_B_WIDTH = 16; + parameter C_ENABLE_RLOCS = 1; + parameter C_HAS_ACLR = 0; + parameter C_HAS_ADD = 0; + parameter C_HAS_AINIT = 0; + parameter C_HAS_ASET = 0; + parameter C_HAS_BYPASS = 0; + parameter C_HAS_BYPASS_WITH_CIN = 0; + parameter C_HAS_B_IN = 0; + parameter C_HAS_B_OUT = 0; + parameter C_HAS_B_SIGNED = 0; + parameter C_HAS_CE = 0; + parameter C_HAS_C_IN = 1; + parameter C_HAS_C_OUT = 0; + parameter C_HAS_OVFL = 0; + parameter C_HAS_Q_B_OUT = 0; + parameter C_HAS_Q_C_OUT = 0; + parameter C_HAS_Q_OVFL = 0; + parameter C_HAS_S = 0; + parameter C_HAS_SCLR = 0; + parameter C_HAS_SINIT = 0; + parameter C_HAS_SSET = 0; + parameter C_HIGH_BIT = 15; + parameter C_LOW_BIT = 0; + parameter C_OUT_WIDTH = 16; + parameter C_PIPE_STAGES = 0; + parameter C_SATURATE = 0; + parameter C_SCALE = 0; + parameter C_SINIT_VAL = "0000000000000000"; + parameter C_SYNC_ENABLE = `c_override; + parameter C_SYNC_PRIORITY = `c_clear; + + // Only for internal consumption (prob with MTI otherwise) + parameter outwidth_min_one = C_OUT_WIDTH-1; + parameter bwidth_min_one = C_B_WIDTH-1; + + parameter tempSyncEnable = ((C_SYNC_ENABLE == 0 && C_HAS_CE == 1 && (C_HAS_SSET == 1 || C_HAS_SCLR == 1) && C_SATURATE == 1) ? 1 : C_SYNC_ENABLE); + + input [C_B_WIDTH-1 : 0] B; + input CLK; + input ADD; + input C_IN; + input B_IN; + input CE; + input BYPASS; + input ACLR; + input ASET; + input AINIT; + input SCLR; + input SSET; + input SINIT; + input B_SIGNED; + output OVFL; + output C_OUT; + output B_OUT; + output Q_OVFL; + output Q_C_OUT; + output Q_B_OUT; + output [C_HIGH_BIT : C_LOW_BIT] S; + output [C_HIGH_BIT : C_LOW_BIT] Q; + + + // Internal values to drive signals when input is missing + wire [C_OUT_WIDTH-1 : 0] intS; + wire [C_OUT_WIDTH-1 : 0] intS_sat0; + wire [C_OUT_WIDTH-1 : 0] intS_unsat1; + wire [C_OUT_WIDTH-1 : 0] intS_sinsat1; + wire [C_OUT_WIDTH-1 : 0] intFB; + wire [C_OUT_WIDTH-1 : 0] intFBq; + wire [C_OUT_WIDTH-1 : 0] intFBq_sat0; + wire [C_OUT_WIDTH-1 : 0] intFBq_unsat1; + wire [C_OUT_WIDTH-1 : 0] intFBq_sinsat1; + wire intSCLR; + wire intSSET; + wire intSCLR_TO_ADDER; + wire intSSET_TO_ADDER; + wire intSCLR_TO_MSB; + wire intSSET_TO_MSB; + wire intSCLR_TO_REST; + wire intSSET_TO_REST; + wire intB_SIGNED; + wire intBYPASSbar; + wire intC_OUT; + wire intB_OUT; + wire Q_C_OUT; + wire Q_B_OUT; + wire OVFL; + wire Q_OVFL; + wire intC_OUT_sat0; + wire intB_OUT_sat0; + wire Q_C_OUT_sat0; + wire Q_B_OUT_sat0; + wire OVFL_sat0; + wire Q_OVFL_sat0; + wire intC_OUT_unsat1; + wire intB_OUT_unsat1; + wire Q_C_OUT_unsat1; + wire Q_B_OUT_unsat1; + wire OVFL_unsat1; + wire Q_OVFL_unsat1; + wire intC_OUT_sinsat1; + wire intB_OUT_sinsat1; + wire Q_C_OUT_sinsat1; + wire Q_B_OUT_sinsat1; + wire OVFL_sinsat1; + wire Q_OVFL_sinsat1; + wire intBYPASS_WITH_CIN; // New signal for bypass with Cin mode + wire tempCE; + + + wire tmpsetsatlogic_un00; + wire tmpsetsatlogic_un01; + wire tmpsetsatlogic_un10; + wire tmpsetsatlogic_un11c; + wire tmpsetsatlogic_un11s; + + wire tmpclrsatlogic_un00; + wire tmpclrsatlogic_un01; + wire tmpclrsatlogic_un10; + wire tmpclrsatlogic_un11c; + wire tmpclrsatlogic_un11s; + + wire tmpsetsatlogicmsb_sg00; + wire tmpsetsatlogicmsb_sg01; + wire tmpsetsatlogicmsb_sg10; + wire tmpsetsatlogicmsb_sg11c; + wire tmpsetsatlogicmsb_sg11s; + + wire tmpsetsatlogicrest_sg00; + wire tmpsetsatlogicrest_sg01; + wire tmpsetsatlogicrest_sg10; + wire tmpsetsatlogicrest_sg11c; + wire tmpsetsatlogicrest_sg11s; + + wire tmpclrsatlogicmsb_sg00; + wire tmpclrsatlogicmsb_sg01; + wire tmpclrsatlogicmsb_sg10; + wire tmpclrsatlogicmsb_sg11c; + wire tmpclrsatlogicmsb_sg11s; + + wire tmpclrsatlogicrest_sg00; + wire tmpclrsatlogicrest_sg01; + wire tmpclrsatlogicrest_sg10; + wire tmpclrsatlogicrest_sg11c; + wire tmpclrsatlogicrest_sg11s; + + wire addsetBaseSig ; + wire subsetBaseSig ; + wire addsubsetBaseSig ; + wire addclrBaseSig ; + wire subclrBaseSig ; + wire addsubclrBaseSig ; + + wire addsetBasePin ; + wire subsetBasePin ; + wire addsubsetBasePin ; + wire addclrBasePin ; + wire subclrBasePin ; + wire addsubclrBasePin ; + + wire addsetBase ; + wire subsetBase ; + wire addsubsetBase ; + wire addclrBase ; + wire subclrBase ; + wire addsubclrBase ; + + wire intCE ; + wire intB ; + wire [C_B_WIDTH : 0] intBconst; + + wire [C_HIGH_BIT : C_LOW_BIT] Q = intFBq; + wire [C_HIGH_BIT : C_LOW_BIT] S = (C_HAS_S == 1 ? intS : `allUKs); + wire C_OUT = (C_HAS_C_OUT == 1 ? intC_OUT : 1'bx); + wire B_OUT = (C_HAS_B_OUT == 1 ? intB_OUT : 1'bx); + parameter temp_C_SCALE = (C_SCALE == 0 ? 1'b1 : C_SCALE); + + + // Sort out default values for missing ports + + assign intB_SIGNED = defval(B_SIGNED, C_HAS_B_SIGNED, 0); + assign intBYPASSbar = (C_BYPASS_LOW == 1 ? BYPASS : ~BYPASS); + assign intSCLR = defval(SCLR, C_HAS_SCLR, 0); + assign intSSET = defval(SSET, C_HAS_SSET, 0); + assign intBYPASS_WITH_CIN = C_HAS_BYPASS_WITH_CIN; //assign new c_has_bypass_with_cin parameter to internal wire + assign intBconst = (C_B_CONSTANT === 1) ? to_bitsB(C_B_VALUE) : B; + + // Now make up the design from other baseblox + // An addsub for when no saturation logic is required... + C_ADDSUB_V7_0 #(C_ADD_MODE, + C_AINIT_VAL, + (C_B_TYPE == `c_pin )? `c_signed : C_B_TYPE, + C_OUT_WIDTH, + C_BYPASS_ENABLE, + C_BYPASS_LOW, + C_B_CONSTANT, + C_B_TYPE, + C_B_VALUE, + C_B_WIDTH, + C_ENABLE_RLOCS, + C_HAS_ACLR, + C_HAS_ADD, + C_HAS_AINIT, + C_HAS_ASET, + C_HAS_B_SIGNED, + C_HAS_BYPASS, + C_HAS_BYPASS_WITH_CIN, + C_HAS_B_IN, + C_HAS_B_OUT, + C_HAS_B_SIGNED, + C_HAS_CE, + C_HAS_C_IN, + C_HAS_C_OUT, + C_HAS_OVFL, + 1, + C_HAS_Q_B_OUT, + C_HAS_Q_C_OUT, + C_HAS_Q_OVFL, + C_HAS_S, + C_HAS_SCLR, + C_HAS_SINIT, + C_HAS_SSET, + outwidth_min_one, + 1, + 0, + C_OUT_WIDTH, + C_PIPE_STAGES, + C_SINIT_VAL, + C_SYNC_ENABLE, + C_SYNC_PRIORITY) + sat0_addsub(.A(intFB), .B(B), .CLK(CLK), .ADD(ADD), + .C_IN(C_IN), .B_IN(B_IN), .CE(CE), .BYPASS(BYPASS), + .ACLR(ACLR), .ASET(ASET), .AINIT(AINIT), + .SCLR(SCLR), .SSET(SSET), .SINIT(SINIT), + .A_SIGNED(B_SIGNED), .B_SIGNED(B_SIGNED), + .OVFL(OVFL_sat0), .C_OUT(intC_OUT_sat0), + .B_OUT(intB_OUT_sat0), .Q_OVFL(Q_OVFL_sat0), + .Q_C_OUT(Q_C_OUT_sat0), .Q_B_OUT(Q_B_OUT_sat0), + .S(intS_sat0), .Q(intFBq_sat0)); + + + // Another addsub for when saturation logic IS required, but only for unsigned data + C_ADDSUB_V7_0 #(C_ADD_MODE, + C_AINIT_VAL, + C_B_TYPE, + C_OUT_WIDTH, + C_BYPASS_ENABLE, + C_BYPASS_LOW, + C_B_CONSTANT, + C_B_TYPE, + C_B_VALUE, + C_B_WIDTH, + C_ENABLE_RLOCS, + 0, + C_HAS_ADD, + 0, + 0, + C_HAS_B_SIGNED, + C_HAS_BYPASS, + C_HAS_BYPASS_WITH_CIN, + C_HAS_B_IN, + 1, + C_HAS_B_SIGNED, + C_HAS_CE, + C_HAS_C_IN, + 1, + C_HAS_OVFL, + 1, + C_HAS_Q_B_OUT, + C_HAS_Q_C_OUT, + C_HAS_Q_OVFL, + C_HAS_S, + 1, + 0, + 1, + outwidth_min_one, + 1, + 0, + C_OUT_WIDTH, + C_PIPE_STAGES, + C_SINIT_VAL, + tempSyncEnable, + C_SYNC_PRIORITY) + unsat1_addsub(.A(intFB), .B(B), .CLK(CLK), .ADD(ADD), + .C_IN(C_IN), .B_IN(B_IN), .CE(intCE), .BYPASS(BYPASS), + .ACLR(ACLR), .ASET(ASET), .AINIT(AINIT), + .SCLR(intSCLR_TO_ADDER), .SSET(intSSET_TO_ADDER), .SINIT(SINIT), + .A_SIGNED(B_SIGNED), .B_SIGNED(B_SIGNED), + .OVFL(OVFL_unsat1), .C_OUT(intC_OUT_unsat1), + .B_OUT(intB_OUT_unsat1), .Q_OVFL(Q_OVFL_unsat1), + .Q_C_OUT(Q_C_OUT_unsat1), .Q_B_OUT(Q_B_OUT_unsat1), + .S(intS_unsat1), .Q(intFBq_unsat1)); + + // Another addsub for when saturation logic IS required, but for signed data + C_ADDSUB_V7_0 #(C_ADD_MODE, + C_AINIT_VAL, + C_B_TYPE, + C_OUT_WIDTH, + C_BYPASS_ENABLE, + C_BYPASS_LOW, + C_B_CONSTANT, + C_B_TYPE, + C_B_VALUE, + C_B_WIDTH, + C_ENABLE_RLOCS, + C_HAS_ACLR, + C_HAS_ADD, + C_HAS_AINIT, + C_HAS_ASET, + C_HAS_B_SIGNED, + C_HAS_BYPASS, + C_HAS_BYPASS_WITH_CIN, + C_HAS_B_IN, + 1, + C_HAS_B_SIGNED, + C_HAS_CE, + C_HAS_C_IN, + 1, + C_HAS_OVFL, + 0, + C_HAS_Q_B_OUT, + C_HAS_Q_C_OUT, + C_HAS_Q_OVFL, + 1, + C_HAS_SCLR, + C_HAS_SINIT, + C_HAS_SSET, + outwidth_min_one, + 1, + 0, + C_OUT_WIDTH, + C_PIPE_STAGES, + C_SINIT_VAL, + tempSyncEnable, // wasC_SYNC_ENABLE, + C_SYNC_PRIORITY) + sinsat1_addsub(.A(intFB), .B(B), .CLK(CLK), .ADD(ADD), + .C_IN(C_IN), .B_IN(B_IN), .CE(intCE), .BYPASS(BYPASS), + .ACLR(ACLR), .ASET(ASET), .AINIT(AINIT), + .SCLR(SCLR), .SSET(SSET), .SINIT(SINIT), + .A_SIGNED(B_SIGNED), .B_SIGNED(B_SIGNED), + .OVFL(OVFL_sinsat1), .C_OUT(intC_OUT_sinsat1), + .B_OUT(intB_OUT_sinsat1), .Q_OVFL(Q_OVFL_sinsat1), + .Q_C_OUT(Q_C_OUT_sinsat1), .Q_B_OUT(Q_B_OUT_sinsat1), + .S(intS_sinsat1), .Q()); + + // Registers for output of the last addsub + C_REG_FD_V7_0 #(00000000, //C_AINIT_VAL[(C_OUT_WIDTH*8)-1 : (C_OUT_WIDTH-1)*8], + C_ENABLE_RLOCS, + 0, + 0, + 0, + C_HAS_CE, + 1, + 0, + 1, + 00000000,//C_SINIT_VAL[(C_OUT_WIDTH*8)-1 : (C_OUT_WIDTH-1)*8], + tempSyncEnable, //C_SYNC_ENABLE, + C_SYNC_PRIORITY, + 1) + msb_reg(.D(intS_sinsat1[outwidth_min_one]), .CLK(CLK), + .CE(intCE), .ACLR(ACLR), .ASET(ASET), .AINIT(AINIT), + .SCLR(intSCLR_TO_MSB), .SSET(intSSET_TO_MSB), + .SINIT(SINIT), .Q(intFBq_sinsat1[outwidth_min_one])); + + // Need the ?: on the value of C_B_WIDTH in case it == 1 + C_REG_FD_V7_0 #(00000000, // C_AINIT_VAL[(((C_OUT_WIDTH == 1 ? 2 : C_OUT_WIDTH)-1)*8)-1 : 0], + C_ENABLE_RLOCS, + 0, + 0, + 0, + C_HAS_CE, + 1, + 0, + 1, + 00000000, //C_SINIT_VAL[(((C_OUT_WIDTH == 1 ? 2 : C_OUT_WIDTH)-1)*8)-1 : 0], + tempSyncEnable, //C_SYNC_ENABLE, + C_SYNC_PRIORITY, + (C_OUT_WIDTH == 1 ? 2 : C_OUT_WIDTH)-1) + rest_reg(.D(intS_sinsat1[(C_OUT_WIDTH == 1 ? 2 : C_OUT_WIDTH)-2 : 0]), .CLK(CLK), + .CE(intCE), .ACLR(ACLR), .ASET(ASET), .AINIT(AINIT), + .SCLR((C_B_WIDTH == 1 ? intSCLR_TO_MSB : intSCLR_TO_REST)), .SSET((C_B_WIDTH == 1 ? intSSET_TO_MSB : intSSET_TO_REST)), + .SINIT(SINIT), .Q(intFBq_sinsat1[(C_OUT_WIDTH == 1 ? 2 : C_OUT_WIDTH)-2 : 0])); + + + // Sort out the choices from all these output signals... + assign tempCE = ((C_SYNC_ENABLE == 0 && C_HAS_CE == 1 && (C_HAS_SSET == 1 || C_HAS_SCLR == 1) && C_SATURATE == 1) ? (CE | intSSET | intSCLR) : CE); + assign intCE = (C_SATURATE == 0 ? CE : (((C_HAS_BYPASS == 1)&&(C_BYPASS_LOW == 1)) ? ((C_BYPASS_ENABLE == `c_override) ? (~BYPASS | tempCE) : tempCE) : (((C_HAS_BYPASS == 1)&&(C_BYPASS_LOW == 0)) ? ((C_BYPASS_ENABLE == `c_override) ? (BYPASS | tempCE) : tempCE) : tempCE))) ; + + assign intC_OUT = (C_SATURATE == 0 ? intC_OUT_sat0 : (C_B_TYPE == `c_unsigned ? intC_OUT_unsat1 : intC_OUT_sinsat1)); + assign intB_OUT = (C_SATURATE == 0 ? intB_OUT_sat0 : (C_B_TYPE == `c_unsigned ? intB_OUT_unsat1 : intB_OUT_sinsat1)); + assign OVFL = (C_SATURATE == 0 ? OVFL_sat0 : (C_B_TYPE == `c_unsigned ? OVFL_unsat1 : OVFL_sinsat1)); + assign Q_C_OUT = (C_SATURATE == 0 ? Q_C_OUT_sat0 : (C_B_TYPE == `c_unsigned ? Q_C_OUT_unsat1 : Q_C_OUT_sinsat1)); + assign Q_B_OUT = (C_SATURATE == 0 ? Q_B_OUT_sat0 : (C_B_TYPE == `c_unsigned ? Q_B_OUT_unsat1 : Q_B_OUT_sinsat1)); + assign Q_OVFL = (C_SATURATE == 0 ? Q_OVFL_sat0 : (C_B_TYPE == `c_unsigned ? Q_OVFL_unsat1 : Q_OVFL_sinsat1)); + assign intS = (C_SATURATE == 0 ? intS_sat0 : (C_B_TYPE == `c_unsigned ? intS_unsat1 : intS_sinsat1)); + assign intFBq = (C_SATURATE == 0 ? intFBq_sat0 : (C_B_TYPE == `c_unsigned ? intFBq_unsat1 : intFBq_sinsat1)); + + + // COMPLEX decisions on what to feed to the local control sigs... + // The signal name suffices denote: un = unsigned, sg = signed, 00 = has neither sset nor sclr, 01 = has sclr only etc + // 11c = has bot sset and sclr and sclr dominates, 11s = sset dominates, etc + + // Unsigned version first + assign tmpsetsatlogic_un00 = (C_ADD_MODE == `c_add ? intC_OUT : (C_ADD_MODE == `c_sub ? intSSET : (intC_OUT & ADD))); + assign tmpsetsatlogic_un01 = (C_ADD_MODE == `c_add ? (intC_OUT & ~intSCLR) : (C_ADD_MODE == `c_sub ? intSSET : (intC_OUT & ~intSCLR & ADD))); + assign tmpsetsatlogic_un10 = (C_ADD_MODE == `c_add ? (intC_OUT | intSSET) : (C_ADD_MODE == `c_sub ? intSSET : ((intC_OUT & ADD) | intSSET))); + assign tmpsetsatlogic_un11c = (C_ADD_MODE == `c_add ? (~intSCLR & (intC_OUT | intSSET)) : (C_ADD_MODE == `c_sub ? (~intSCLR & intSSET) : ((~intSCLR & intC_OUT & ADD) | (intSSET & ~intSCLR)))); + assign tmpsetsatlogic_un11s = (C_ADD_MODE == `c_add ? ((~intSCLR && intC_OUT) | intSSET) : (C_ADD_MODE == `c_sub ? intSSET : ((~intSCLR & intC_OUT & ADD) | intSSET))); + +// assign tmpclrsatlogic_un00 = (C_ADD_MODE == `c_add ? intSCLR : (C_ADD_MODE == `c_sub ? ~intB_OUT : (~intC_OUT & ~ADD))); + assign tmpclrsatlogic_un00 = (C_ADD_MODE == `c_add ? intSCLR : (C_ADD_MODE == `c_sub ? (C_HAS_BYPASS == 1 ? (C_BYPASS_LOW == 1 ? (~intB_OUT & BYPASS) : (~intB_OUT & ~BYPASS)): ~intB_OUT) : (C_HAS_BYPASS == 1 ? (C_BYPASS_LOW ==1 ? ((~intC_OUT & ~ADD) & BYPASS) : ((~intC_OUT & ~ADD) & ~BYPASS)) : (~intC_OUT & ~ADD)))); +// assign tmpclrsatlogic_un01 = (C_ADD_MODE == `c_add ? intSCLR : (C_ADD_MODE == `c_sub ? (~intB_OUT | intSCLR) : (intSCLR | (~intC_OUT & ~ADD)))); + assign tmpclrsatlogic_un01 = (C_ADD_MODE == `c_add ? intSCLR : (C_ADD_MODE == `c_sub ? (C_HAS_BYPASS == 1 ? (C_BYPASS_LOW == 1 ? ((~intB_OUT & BYPASS) | intSCLR) : ((~intB_OUT & ~BYPASS) | intSCLR)) : (~intB_OUT | intSCLR)) : (C_HAS_BYPASS == 1 ? (C_BYPASS_LOW ==1 ? (intSCLR | ((~intC_OUT & ~ADD) & BYPASS)) : (intSCLR | ((~intC_OUT & ~ADD) & ~BYPASS))) : (intSCLR | (~intC_OUT & ~ADD))))); +// assign tmpclrsatlogic_un10 = (C_ADD_MODE == `c_add ? intSCLR : (C_ADD_MODE == `c_sub ? (~intB_OUT & ~intSSET) : (~intSSET & ~intC_OUT & ~ADD))); + assign tmpclrsatlogic_un10 = (C_ADD_MODE == `c_add ? intSCLR : (C_ADD_MODE == `c_sub ? (C_HAS_BYPASS == 1 ? (C_BYPASS_LOW == 1 ? ((~intB_OUT & BYPASS) & ~intSSET) : ((~intB_OUT & ~BYPASS) & ~intSSET)): (~intB_OUT & ~intSSET)) : ((C_HAS_BYPASS == 1 ? (C_BYPASS_LOW ==1 ? (~intSSET & (~intC_OUT & ~ADD) & BYPASS) : (~intSSET & ((~intC_OUT & ~ADD) & ~BYPASS))) : (~intSSET & ~intC_OUT & ~ADD))))); +// assign tmpclrsatlogic_un11c = (C_ADD_MODE == `c_add ? intSCLR : (C_ADD_MODE == `c_sub ? (intSCLR | (~intB_OUT & ~intSSET)) : (intSCLR | (~intSSET & ~intC_OUT & ~ADD)))); + assign tmpclrsatlogic_un11c = (C_ADD_MODE == `c_add ? intSCLR : (C_ADD_MODE == `c_sub ? (C_HAS_BYPASS == 1 ? (C_BYPASS_LOW == 1 ? (intSCLR | ((~intB_OUT & BYPASS) & ~intSSET)) : (intSCLR | ((~intB_OUT & ~BYPASS) & ~intSSET))) : (intSCLR | (~intB_OUT & ~intSSET))) : ((C_HAS_BYPASS == 1 ? (C_BYPASS_LOW ==1 ? (intSCLR | ((~intSSET & ~intC_OUT & ~ADD) & BYPASS)) : (intSCLR | ((~intSSET & ~intC_OUT & ~ADD) & ~BYPASS))) : (intSCLR | (~intSSET & ~intC_OUT & ~ADD))))));// assign tmpclrsatlogic_un11s = (C_ADD_MODE == `c_add ? (intSCLR & ~intSSET) : (C_ADD_MODE == `c_sub ? (~intSSET & (intSCLR | ~intB_OUT)) : ((intSCLR & ~intSSET) | (~intSSET & ~intC_OUT & ~ADD)))); + assign tmpclrsatlogic_un11s = (C_ADD_MODE == `c_add ? (intSCLR & ~intSSET) : (C_ADD_MODE == `c_sub ? (C_HAS_BYPASS == 1 ? (C_BYPASS_LOW == 1 ? (~intSSET & (intSCLR | (~intB_OUT & BYPASS))) : (~intSSET & (intSCLR | (~intB_OUT & ~BYPASS)))) : (~intSSET & (intSCLR | ~intB_OUT))) : (C_HAS_BYPASS == 1 ? (C_BYPASS_LOW ==1 ? ((intSCLR & ~intSSET) | (~intSSET & ((~intC_OUT & ~ADD) & BYPASS))): ((intSCLR & ~intSSET) | (~intSSET & ((~intC_OUT & ~ADD) & ~BYPASS)))) : ((intSCLR & ~intSSET) | (~intSSET & ~intC_OUT & ~ADD))))); + + assign intSSET_TO_ADDER = (C_HAS_SSET == 0 ? (C_HAS_SCLR == 0 ? tmpsetsatlogic_un00 : tmpsetsatlogic_un01) : + (C_HAS_SCLR == 0 ? tmpsetsatlogic_un10 : + (C_SYNC_PRIORITY == `c_clear ? tmpsetsatlogic_un11c : tmpsetsatlogic_un11s))); + + assign intSCLR_TO_ADDER = (C_HAS_SSET == 0 ? (C_HAS_SCLR == 0 ? tmpclrsatlogic_un00 : tmpclrsatlogic_un01) : + (C_HAS_SCLR == 0 ? tmpclrsatlogic_un10 : + (C_SYNC_PRIORITY == `c_clear ? tmpclrsatlogic_un11c : tmpclrsatlogic_un11s))); + + // Now all the signals for the signed version + assign intB = intBconst[C_B_WIDTH-1]; + //assign intB = (C_B_CONSTANT == 1 ? (C_B_VALUE[(C_B_WIDTH*8)-1 : (C_B_WIDTH-1)*8] == "0" ? 1'b0 : 1'b1) : B[C_B_WIDTH-1]) ; + + assign addclrBaseSig = (intS[C_HIGH_BIT] & ~(intFBq[C_HIGH_BIT]) & ~(intB)) ; + assign addsetBaseSig = (~(intS[C_HIGH_BIT]) & intFBq[C_HIGH_BIT] & intB) ; + assign subclrBaseSig = (intS[C_HIGH_BIT] & ~(intFBq[C_HIGH_BIT]) & intB) ; + assign subsetBaseSig = (~(intS[C_HIGH_BIT]) & intFBq[C_HIGH_BIT] & ~(intB)) ; + assign addsubclrBaseSig = ((~ADD & (intS[C_HIGH_BIT] & ~(intFBq[C_HIGH_BIT]) & intB)) | (ADD & (intS[C_HIGH_BIT] & ~(intFBq[C_HIGH_BIT]) & ~(intB)))) ; + assign addsubsetBaseSig = ((~ADD & (~(intS[C_HIGH_BIT]) & intFBq[C_HIGH_BIT] & ~(intB))) | (ADD & (~(intS[C_HIGH_BIT]) & intFBq[C_HIGH_BIT] & intB))) ; + + assign addclrBasePin = (~(intB_SIGNED) & ~(intFBq[C_HIGH_BIT]) & intS[C_HIGH_BIT]) | (intB_SIGNED & ~(intFBq[C_HIGH_BIT]) & intS[C_HIGH_BIT] & ~(intB)); + assign addsetBasePin = (intB_SIGNED & intFBq[C_HIGH_BIT] & ~(intS[C_HIGH_BIT]) & intB) ; + assign subclrBasePin = (intB_SIGNED & ~(intFBq[C_HIGH_BIT]) & intS[C_HIGH_BIT] & intB); + assign subsetBasePin = (~(intB_SIGNED) & intFBq[C_HIGH_BIT] & ~(intS[C_HIGH_BIT])) | (intB_SIGNED & intFBq[C_HIGH_BIT] & ~(intS[C_HIGH_BIT]) & ~(intB)); + assign addsubclrBasePin = (~(ADD) & (intB_SIGNED & ~(intFBq[C_HIGH_BIT]) & intS[C_HIGH_BIT] & intB)) | (ADD & ((~(intB_SIGNED) & ~(intFBq[C_HIGH_BIT]) & intS[C_HIGH_BIT]) | (intB_SIGNED & ~(intFBq[C_HIGH_BIT]) & intS[C_HIGH_BIT] & ~(intB)))) ; + assign addsubsetBasePin = (~(ADD) & ((~intB_SIGNED & intFBq[C_HIGH_BIT] & ~(intS[C_HIGH_BIT])) | (intB_SIGNED & intFBq[C_HIGH_BIT] & ~intS[C_HIGH_BIT] & ~intB))) | (ADD & intB_SIGNED & intFBq[C_HIGH_BIT] & ~intS[C_HIGH_BIT] & intB) ; + + assign addclrBase = (C_HAS_B_SIGNED == 0 ? addclrBaseSig : addclrBasePin); + assign addsetBase = (C_HAS_B_SIGNED == 0 ? addsetBaseSig : addsetBasePin); + assign subclrBase = (C_HAS_B_SIGNED == 0 ? subclrBaseSig : subclrBasePin); + assign subsetBase = (C_HAS_B_SIGNED == 0 ? subsetBaseSig : subsetBasePin); + assign addsubclrBase = (C_HAS_B_SIGNED == 0 ? addsubclrBaseSig : addsubclrBasePin); + assign addsubsetBase = (C_HAS_B_SIGNED == 0 ? addsubsetBaseSig : addsubsetBasePin); + + assign tmpsetsatlogicmsb_sg00 = (C_ADD_MODE == `c_add ? (C_HAS_BYPASS == 1 ? addsetBase & intBYPASSbar : addsetBase) : (C_ADD_MODE == `c_sub ? (C_HAS_BYPASS == 1 ? subsetBase & intBYPASSbar : subsetBase) : (C_HAS_BYPASS == 1 ? addsubsetBase & intBYPASSbar : addsubsetBase) )); + assign tmpsetsatlogicmsb_sg01 = tmpsetsatlogicmsb_sg00 & ~intSCLR ; + assign tmpsetsatlogicmsb_sg10 = tmpsetsatlogicmsb_sg00 | intSSET ; + assign tmpsetsatlogicmsb_sg11c = (tmpsetsatlogicmsb_sg00 | intSSET) & ~intSCLR ; + assign tmpsetsatlogicmsb_sg11s = (tmpsetsatlogicmsb_sg00 & ~intSCLR) | intSSET ; //new code!! + + assign tmpsetsatlogicrest_sg00 = (C_ADD_MODE == `c_add ? (C_HAS_BYPASS == 1 ? addclrBase & intBYPASSbar : addclrBase) : (C_ADD_MODE == `c_sub ? (C_HAS_BYPASS == 1 ? subclrBase & intBYPASSbar : subclrBase) : (C_HAS_BYPASS == 1 ? addsubclrBase & intBYPASSbar : addsubclrBase) )); + assign tmpsetsatlogicrest_sg01 = tmpsetsatlogicrest_sg00 & ~intSCLR ; + assign tmpsetsatlogicrest_sg10 = tmpsetsatlogicrest_sg00 | intSSET ; + assign tmpsetsatlogicrest_sg11c = (tmpsetsatlogicrest_sg00 | intSSET) & ~intSCLR ; + assign tmpsetsatlogicrest_sg11s = (tmpsetsatlogicrest_sg00 & (~intSCLR)) | intSSET ; + + assign tmpclrsatlogicmsb_sg00 = tmpsetsatlogicrest_sg00 ; + assign tmpclrsatlogicmsb_sg01 = tmpsetsatlogicrest_sg00 | intSCLR ; + assign tmpclrsatlogicmsb_sg10 = tmpsetsatlogicrest_sg00 & ~intSSET ; + assign tmpclrsatlogicmsb_sg11c = (tmpsetsatlogicrest_sg00 & ~intSSET) | intSCLR ; // not sure about the intSSET in this one! + assign tmpclrsatlogicmsb_sg11s = (tmpsetsatlogicrest_sg00 | intSCLR) & ~intSSET ; + + assign tmpclrsatlogicrest_sg00 = tmpsetsatlogicmsb_sg00 ; + assign tmpclrsatlogicrest_sg01 = tmpsetsatlogicmsb_sg00 | intSCLR ; + assign tmpclrsatlogicrest_sg10 = tmpsetsatlogicmsb_sg00 & ~intSSET ; + assign tmpclrsatlogicrest_sg11c = (tmpsetsatlogicmsb_sg00 & ~intSSET) | intSCLR ; // added to fix reg override sync bug + assign tmpclrsatlogicrest_sg11s = (tmpsetsatlogicmsb_sg00 | intSCLR) & ~intSSET ; + + assign intSSET_TO_MSB = (C_HAS_SSET == 0 ? (C_HAS_SCLR == 0 ? tmpsetsatlogicmsb_sg00 : tmpsetsatlogicmsb_sg01) : + (C_HAS_SCLR == 0 ? tmpsetsatlogicmsb_sg10 : + (C_SYNC_PRIORITY == `c_clear ? tmpsetsatlogicmsb_sg11c : tmpsetsatlogicmsb_sg11s))); + + assign intSCLR_TO_MSB = (C_HAS_SSET == 0 ? (C_HAS_SCLR == 0 ? tmpclrsatlogicmsb_sg00 : tmpclrsatlogicmsb_sg01) : + (C_HAS_SCLR == 0 ? tmpclrsatlogicmsb_sg10 : + (C_SYNC_PRIORITY == `c_clear ? tmpclrsatlogicmsb_sg11c : tmpclrsatlogicmsb_sg11s))); + + assign intSSET_TO_REST = (C_HAS_SSET == 0 ? (C_HAS_SCLR == 0 ? tmpsetsatlogicrest_sg00 : tmpsetsatlogicrest_sg01) : + (C_HAS_SCLR == 0 ? tmpsetsatlogicrest_sg10 : + (C_SYNC_PRIORITY == `c_clear ? tmpsetsatlogicrest_sg11c : tmpsetsatlogicrest_sg11s))); + + assign intSCLR_TO_REST = (C_HAS_SSET == 0 ? (C_HAS_SCLR == 0 ? tmpclrsatlogicrest_sg00 : tmpclrsatlogicrest_sg01) : + (C_HAS_SCLR == 0 ? tmpclrsatlogicrest_sg10 : + (C_SYNC_PRIORITY == `c_clear ? tmpclrsatlogicrest_sg11c : tmpclrsatlogicrest_sg11s))); + + // Finally we are ready to scale the feedback signal... + // If the scaling factor results in NO bits being fed back to the input then we need to handle this! + // This is the case if C_SCALE >= C_OUT_WIDTH + assign intFB[C_OUT_WIDTH-1-(C_SCALE >= C_OUT_WIDTH ? 0 : C_SCALE) : 0] = (C_SCALE >= C_OUT_WIDTH ? {C_OUT_WIDTH{1'b0}} : intFBq[C_OUT_WIDTH-1 : (C_SCALE >= C_OUT_WIDTH ? 0 : C_SCALE)]); + //assign intFB[C_OUT_WIDTH-1 : C_OUT_WIDTH-(C_SCALE == 0 ? 1 : C_SCALE)] = (C_SCALE == 0 ? intFBq[C_OUT_WIDTH-1] : (C_SCALE < C_OUT_WIDTH && (C_B_TYPE == `c_signed || (C_B_TYPE == `c_pin && intB_SIGNED === 1'b1)) ? + // {C_SCALE{intFBq[C_OUT_WIDTH-1]}} : {C_SCALE{1'b0}})); + assign intFB[C_OUT_WIDTH-1 : C_OUT_WIDTH-(C_SCALE == 0 ? 1 : C_SCALE)] = (C_SCALE == 0 ? intFBq[C_OUT_WIDTH-1] : (C_SCALE < C_OUT_WIDTH && (C_B_TYPE == `c_signed || C_B_TYPE == `c_pin) ? + {temp_C_SCALE{intFBq[C_OUT_WIDTH-1]}} : {temp_C_SCALE{1'b0}})); + + + + + initial + begin + #1; + end + +/* helper functions */ + + function defval; + input i; + input hassig; + input val; + begin + if(hassig == 1) + defval = i; + else + defval = val; + end + endfunction + + function [C_B_WIDTH - 1 : 0] to_bitsB; + input [C_B_WIDTH*8 : 1] instring; + integer i; + integer non_null_string; + begin + non_null_string = 0; + for(i = C_B_WIDTH; i > 0; i = i - 1) + begin // Is the string empty? + if(instring[(i*8)] == 0 && + instring[(i*8)-1] == 0 && + instring[(i*8)-2] == 0 && + instring[(i*8)-3] == 0 && + instring[(i*8)-4] == 0 && + instring[(i*8)-5] == 0 && + instring[(i*8)-6] == 0 && + instring[(i*8)-7] == 0 && + non_null_string == 0) + non_null_string = 0; // Use the return value to flag a non-empty string + else + non_null_string = 1; // Non-null character! + end + if(non_null_string == 0) // String IS empty! Just return the value to be all '0's + begin + for(i = C_B_WIDTH; i > 0; i = i - 1) + to_bitsB[i-1] = 0; + end + else + begin + for(i = C_B_WIDTH; i > 0; i = i - 1) + begin // Is this character a '0'? (ASCII = 48 = 00110000) + if(instring[(i*8)] == 0 && + instring[(i*8)-1] == 0 && + instring[(i*8)-2] == 1 && + instring[(i*8)-3] == 1 && + instring[(i*8)-4] == 0 && + instring[(i*8)-5] == 0 && + instring[(i*8)-6] == 0 && + instring[(i*8)-7] == 0) + to_bitsB[i-1] = 0; + // Or is it a '1'? + else if(instring[(i*8)] == 0 && + instring[(i*8)-1] == 0 && + instring[(i*8)-2] == 1 && + instring[(i*8)-3] == 1 && + instring[(i*8)-4] == 0 && + instring[(i*8)-5] == 0 && + instring[(i*8)-6] == 0 && + instring[(i*8)-7] == 1) + to_bitsB[i-1] = 1; + // Or is it a ' '? (a null char - in which case insert a '0') + else if(instring[(i*8)] == 0 && + instring[(i*8)-1] == 0 && + instring[(i*8)-2] == 0 && + instring[(i*8)-3] == 0 && + instring[(i*8)-4] == 0 && + instring[(i*8)-5] == 0 && + instring[(i*8)-6] == 0 && + instring[(i*8)-7] == 0) + to_bitsB[i-1] = 0; + else + begin + $display("Error in %m at time %d ns: non-binary digit in string \"%s\"\nExiting simulation...",$time, instring); + $finish; + end + end + end + end + endfunction + + function max; + input a; + input b; + begin + max = (a > b) ? a : b; + end + endfunction + +endmodule + +`undef c_set +`undef c_clear +`undef c_override +`undef c_no_override +`undef c_add +`undef c_sub +`undef c_add_sub +`undef c_signed +`undef c_unsigned +`undef c_pin +`undef allUKs + + + + + + + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/C_ADDSUB_V4_0.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/C_ADDSUB_V4_0.v new file mode 100644 index 0000000..fc35870 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/C_ADDSUB_V4_0.v @@ -0,0 +1,656 @@ +/* $Id: C_ADDSUB_V4_0.v,v 1.12 2008/09/08 20:05:45 akennedy Exp $ +-- +-- Filename - C_ADDSUB_V4_0.v +-- Author - Xilinx +-- Creation - 22 Mar 1999 +-- +-- Description - This file contains the Verilog behavior for the Baseblocks C_ADDSUB_V4_0 module +*/ + + + +`define c_set 0 +`define c_clear 1 +`define c_override 0 +`define c_no_override 1 +`define c_add 0 +`define c_sub 1 +`define c_add_sub 2 +`define c_signed 0 +`define c_unsigned 1 +`define c_pin 2 +`define allUKs {(C_HIGH_BIT-C_LOW_BIT)+1{1'bx}} + +module C_ADDSUB_V4_0 (A, B, CLK, ADD, C_IN, B_IN, CE, BYPASS, ACLR, ASET, AINIT, + SCLR, SSET, SINIT, A_SIGNED, B_SIGNED, OVFL, C_OUT, B_OUT, + Q_OVFL, Q_C_OUT, Q_B_OUT, S, Q); + + parameter C_ADD_MODE = `c_add; + parameter C_AINIT_VAL = ""; + parameter C_A_TYPE = `c_unsigned; + parameter C_A_WIDTH = 16; + parameter C_BYPASS_ENABLE = `c_override; + parameter C_BYPASS_LOW = 0; + parameter C_B_CONSTANT = 0; + parameter C_B_TYPE = `c_unsigned; + parameter C_B_VALUE = ""; + parameter C_B_WIDTH = 16; + parameter C_ENABLE_RLOCS = 1; + parameter C_HAS_ACLR = 0; + parameter C_HAS_ADD = 0; + parameter C_HAS_AINIT = 0; + parameter C_HAS_ASET = 0; + parameter C_HAS_A_SIGNED = 0; + parameter C_HAS_BYPASS = 0; + parameter C_HAS_B_IN = 1; + parameter C_HAS_B_OUT = 0; + parameter C_HAS_B_SIGNED = 0; + parameter C_HAS_CE = 0; + parameter C_HAS_C_IN = 1; + parameter C_HAS_C_OUT = 0; + parameter C_HAS_OVFL = 0; + parameter C_HAS_Q = 1; + parameter C_HAS_Q_B_OUT = 0; + parameter C_HAS_Q_C_OUT = 0; + parameter C_HAS_Q_OVFL = 0; + parameter C_HAS_S = 0; + parameter C_HAS_SCLR = 0; + parameter C_HAS_SINIT = 0; + parameter C_HAS_SSET = 0; + parameter C_HIGH_BIT = 15; + parameter C_LATENCY = 1; + parameter C_LOW_BIT = 0; + parameter C_OUT_WIDTH = 16; + parameter C_PIPE_STAGES = 1; + parameter C_SINIT_VAL = ""; + parameter C_SYNC_ENABLE = `c_override; + parameter C_SYNC_PRIORITY = `c_clear; + + // internal parameters (not to be set from instanciation) + parameter tmpWidth = (C_A_WIDTH > C_B_WIDTH) ? C_A_WIDTH + 2 : C_B_WIDTH + 2; + parameter output_reg_width = C_HIGH_BIT-C_LOW_BIT+1; + + input [C_A_WIDTH-1 : 0] A; + input [C_B_WIDTH-1 : 0] B; + input CLK; + input ADD; + input C_IN; + input B_IN; + input CE; + input BYPASS; + input ACLR; + input ASET; + input AINIT; + input SCLR; + input SSET; + input SINIT; + input A_SIGNED; + input B_SIGNED; + output OVFL; + output C_OUT; + output B_OUT; + output Q_OVFL; + output Q_C_OUT; + output Q_B_OUT; + output [C_HIGH_BIT : C_LOW_BIT] S; + output [C_HIGH_BIT : C_LOW_BIT] Q; + + + // Internal values to drive signals when input is missing + wire [C_B_WIDTH-1 : 0] intBconst; + wire [C_B_WIDTH-1 : 0] intB; + wire intADD; + wire intBYPASS; + wire intC_IN; + wire intB_IN; + wire intCE; + wire intQCE; + wire intA_SIGNED; + wire intB_SIGNED; + reg intC_OUT; + reg intB_OUT; + reg intOVFL; + wire intQ_C_OUT; + wire intQ_B_OUT; + wire intQ_OVFL; + reg [C_HIGH_BIT : C_LOW_BIT ] intS; + wire [C_HIGH_BIT : C_LOW_BIT ] intQ; + wire intACLR; + wire intASET; + wire intAINIT; + wire intSCLR; + wire intSSET; + wire intSINIT; + wire intACLR_INIT; + wire intSCLR_INIT; + reg lastCLK; + reg lastADD; + + reg [C_HIGH_BIT : C_LOW_BIT] intQpipe [C_LATENCY+2 : 0]; + reg [C_LATENCY+2 : 0] intQ_C_OUTpipe; + reg [C_LATENCY+2 : 0] intQ_B_OUTpipe; + reg [C_LATENCY : 0] intQ_OVFLpipe; + + reg [C_HIGH_BIT : C_LOW_BIT] intQpipeend; + reg intQ_C_OUTpipeend; + reg intQ_B_OUTpipeend; + reg intQ_OVFLpipeend; + reg [C_HIGH_BIT : C_LOW_BIT] tmp_pipe1; + reg [C_HIGH_BIT : C_LOW_BIT] tmp_pipe2; + + + wire [C_HIGH_BIT : C_LOW_BIT] Q = (C_HAS_Q == 1 ? intQ : `allUKs); + wire Q_C_OUT = (C_HAS_Q_C_OUT == 1 ? intQ_C_OUT : 1'bx); + wire Q_B_OUT = (C_HAS_Q_B_OUT == 1 ? intQ_B_OUT : 1'bx); + wire Q_OVFL = (C_HAS_Q_OVFL == 1 ? intQ_OVFL : 1'bx); + wire [C_HIGH_BIT : C_LOW_BIT] S = (C_HAS_S == 1 ? intS : `allUKs); + wire C_OUT = (C_HAS_C_OUT == 1 ? intC_OUT : 1'bx); + wire B_OUT = (C_HAS_B_OUT == 1 ? intB_OUT : 1'bx); + wire OVFL = (C_HAS_OVFL == 1 ? intOVFL : 1'bx); + + // Sort out default values for missing ports + + assign intCE = defval(CE, C_HAS_CE, 1); + assign intACLR = defval(ACLR, C_HAS_ACLR, 0); + assign intASET = defval(ASET, C_HAS_ASET, 0); + assign intAINIT = defval(AINIT, C_HAS_AINIT, 0); + assign intSCLR = defval(SCLR, C_HAS_SCLR, 0); + assign intSSET = defval(SSET, C_HAS_SSET, 0); + assign intSINIT = defval(SINIT, C_HAS_SINIT, 0); + assign intACLR_INIT = (intACLR || intAINIT); + assign intSCLR_INIT = (intSCLR || intSINIT); + + assign intBconst = (C_B_CONSTANT === 1) ? to_bitsB(C_B_VALUE) : B; + assign intADD = (C_HAS_ADD === 1) ? ADD : ((C_ADD_MODE === `c_add) ? 1 : ((C_ADD_MODE === `c_sub) ? 0 : 3)); // 3 is an illegal value since this is an illegal option! + assign intBYPASS = (C_HAS_BYPASS === 1) ? ((C_BYPASS_LOW === 1) ? !BYPASS : BYPASS) : 0; + assign intC_IN = ((C_HAS_C_IN === 1) ? C_IN : ((C_HAS_ADD === 1) ? ~intADD : 0)); + assign intB_IN = defval(B_IN, C_HAS_B_IN, 1); + assign intA_SIGNED = defval(A_SIGNED, C_HAS_A_SIGNED, 0); + //assign intB_SIGNED = defval(B_SIGNED, C_HAS_B_SIGNED, 0); + assign intB_SIGNED = ((C_HAS_B_SIGNED === 0) ? 0 : (((C_HAS_B_SIGNED === 1) && ~((C_B_CONSTANT === 1) && (C_HAS_BYPASS === 0) && (C_B_VALUE[((C_B_WIDTH*8)-1):((C_B_WIDTH-1)*8)] === "0")) ? B_SIGNED : 0))) ; + assign intB = (intBYPASS === 0 ? intBconst : B); + assign intQCE = (C_HAS_CE === 1 ? (C_HAS_BYPASS === 1 ? (C_BYPASS_ENABLE === `c_override ? CE || intBYPASS : CE) : CE) : 1'b1); + + integer j, k; + integer pipe, pipe1; + integer i; + + reg [tmpWidth-1 : 0] tmpA; + reg [tmpWidth-1 : 0] tmpB; + reg [tmpWidth-1 : 0] tmpC; + reg [tmpWidth-1 : 0] tmpBC; + reg [tmpWidth-1 : 0] tmpABC; + reg [tmpWidth-2 : 0] tmpD; + reg [tmpWidth-2 : 0] tmpE; + reg [tmpWidth-2 : 0] tmpF; + + // Registers on outputs by default + C_REG_FD_V4_0 #(C_AINIT_VAL, C_ENABLE_RLOCS, C_HAS_ACLR, C_HAS_AINIT, C_HAS_ASET, + C_HAS_CE, C_HAS_SCLR, C_HAS_SINIT, C_HAS_SSET, + C_SINIT_VAL, C_SYNC_ENABLE, C_SYNC_PRIORITY, output_reg_width) + regq (.D(intQpipeend), .CLK(CLK), .CE(intQCE), .ACLR(ACLR), .ASET(ASET), + .AINIT(AINIT), .SCLR(SCLR), .SSET(SSET), .SINIT(SINIT), + .Q(intQ)); + + C_REG_FD_V4_0 #("0", C_ENABLE_RLOCS, C_HAS_ACLR, C_HAS_AINIT, C_HAS_ASET, + C_HAS_CE, C_HAS_SCLR, C_HAS_SINIT, C_HAS_SSET, + "0", C_SYNC_ENABLE, C_SYNC_PRIORITY, 1) + regcout (.D(intQ_C_OUTpipeend), .CLK(CLK), .CE(intQCE), .ACLR(intACLR_INIT), + .AINIT(AINIT), .ASET(ASET), .SCLR(intSCLR_INIT), .SINIT(SINIT), .SSET(SSET), + .Q(intQ_C_OUT)); + + C_REG_FD_V4_0 #("0", C_ENABLE_RLOCS, C_HAS_ACLR, C_HAS_AINIT, C_HAS_ASET, + C_HAS_CE, C_HAS_SCLR, C_HAS_SINIT, C_HAS_SSET, + "0", C_SYNC_ENABLE, C_SYNC_PRIORITY, 1) + regbout (.D(intQ_B_OUTpipeend), .CLK(CLK), .CE(intQCE), .ACLR(intACLR_INIT), + .AINIT(AINIT), .ASET(ASET), .SCLR(intSCLR_INIT), .SINIT(SINIT), .SSET(SSET), + .Q(intQ_B_OUT)); + + C_REG_FD_V4_0 #("0", C_ENABLE_RLOCS, C_HAS_ACLR, C_HAS_AINIT, C_HAS_ASET, + C_HAS_CE, C_HAS_SCLR, C_HAS_SINIT, C_HAS_SSET, + "0", C_SYNC_ENABLE, C_SYNC_PRIORITY, 1) + regovfl (.D(intQ_OVFLpipeend), .CLK(CLK), .CE(intQCE), .ACLR(intACLR_INIT), + .AINIT(AINIT), .ASET(ASET), .SCLR(intSCLR_INIT), .SINIT(SINIT), .SSET(SSET), + .Q(intQ_OVFL)); + + initial + begin + #1; + for(i = 0; i <= C_LATENCY+2; i = i + 1) + begin + intQpipe[i] = 'bx; + intQ_C_OUTpipe[i] = 1'bx; + intQ_B_OUTpipe[i] = 1'bx; + intQ_OVFLpipe[i] = 1'bx; + end + intQpipeend = `allUKs; + intQ_C_OUTpipeend = 0; + intQ_B_OUTpipeend = 0; + intQ_OVFLpipeend = 0; + intS = `allUKs; + intC_OUT = 0; + intB_OUT = 0; + intOVFL = 0; + end + + always@(A or intB or intADD or intBYPASS or intC_IN or intB_IN or intA_SIGNED or intB_SIGNED) + begin + tmpC = 0; + if(intC_IN !== 1'b0) + begin + if((C_ADD_MODE == `c_add_sub && intADD == 1) || C_ADD_MODE == `c_add) + begin + tmpC = intC_IN; + end + end + else if(intC_IN !== 1'b1 && C_ADD_MODE == `c_add_sub && intADD === 1'b0) + begin + tmpC[0] = ~intC_IN; + end + else if(intB_IN !== 1'b1 && C_ADD_MODE == `c_sub) + begin + tmpC[0] = ~intB_IN; + end + + if(C_A_TYPE == `c_signed || (C_A_TYPE == `c_pin && intA_SIGNED === 1)) + begin + for(j = tmpWidth-1; j >= C_A_WIDTH; j = j - 1) + begin + tmpA[j] = A[C_A_WIDTH-1]; + end + end + else if(C_A_TYPE == `c_unsigned || (C_A_TYPE == `c_pin && intA_SIGNED === 0)) + begin + for(j = tmpWidth-1; j >= C_A_WIDTH; j = j - 1) + begin + tmpA[j] = 0; + end + end + + tmpA[C_A_WIDTH-1 : 0] = A; + + if(C_B_TYPE == `c_signed || (C_B_TYPE == `c_pin && intB_SIGNED === 1)) + begin + for(j = tmpWidth-1; j >= C_B_WIDTH; j = j - 1) + begin + tmpB[j] = intB[C_B_WIDTH-1]; + end + end + else if(C_B_TYPE == `c_unsigned || (C_B_TYPE == `c_pin && intB_SIGNED === 0)) + begin + for(j = tmpWidth-1; j >= C_B_WIDTH; j = j - 1) + begin + tmpB[j] = 0; + end + end + + tmpB[C_B_WIDTH-1 : 0] = intB; + + if(intBYPASS == 1) + begin + intS <= #1 tmpB[C_HIGH_BIT : C_LOW_BIT]; + if (is_X(tmpB) && C_LATENCY >1) + begin + intC_OUT <= #1 1'bx; + intB_OUT <= #1 1'bx; + intOVFL <= #1 1'bx; + end + else + begin + intC_OUT <= #1 1'b0; + intB_OUT <= #1 1'b0; + intOVFL <= #1 1'b0; + end + end + else if(is_X(tmpA) || is_X(tmpB) || is_X(tmpC) || intBYPASS === 1'bx || intADD === 1'bx) + begin + intS <= #1 {C_HIGH_BIT-C_LOW_BIT+1{1'bx}}; + intC_OUT <= #1 1'bx; + intB_OUT <= #1 1'bx; + intOVFL <= #1 1'bx; + end + else + begin + if((C_ADD_MODE == `c_add_sub && intADD == 1) || C_ADD_MODE == `c_add) + begin + tmpBC = add(tmpB, tmpC); + end + else if((C_ADD_MODE == `c_add_sub && intADD == 0) || C_ADD_MODE == `c_sub) + begin + tmpBC = add(tmpB, tmpC); + end + + if((C_ADD_MODE == `c_add_sub && intADD == 1) || C_ADD_MODE == `c_add) + begin + tmpABC = add(tmpA, tmpBC); + end + else if((C_ADD_MODE == `c_add_sub && intADD == 0) || C_ADD_MODE == `c_sub) + begin + tmpABC = sub(tmpA, tmpBC); + end + + intS <= #1 tmpABC[C_HIGH_BIT : C_LOW_BIT]; + + if(C_HAS_C_OUT == 1 || C_HAS_Q_C_OUT == 1) + begin + if((C_ADD_MODE == `c_add_sub && intADD === 1'b1) || C_ADD_MODE == `c_add) + intC_OUT <= #1 tmpABC[tmpWidth-2]; + else if(C_ADD_MODE == `c_add_sub && intADD === 1'b0) + intC_OUT <= #1 ~tmpABC[tmpWidth-2]; + end + + if(C_HAS_B_OUT == 1 || C_HAS_Q_B_OUT == 1) + begin + intB_OUT <= #1 !tmpABC[tmpWidth-2]; + end + + if(C_HAS_OVFL == 1 || C_HAS_Q_OVFL == 1) + begin + tmpD[tmpWidth-3 : 0] = tmpA[tmpWidth-3 : 0]; + if(C_A_TYPE == `c_signed || (C_A_TYPE == `c_pin && intA_SIGNED == 1)) + tmpD[tmpWidth-2] = tmpA[tmpWidth-1]; + else + tmpD[tmpWidth-2] = 1'b0; + tmpE[tmpWidth-3 : 0] = tmpBC[tmpWidth-3 : 0]; + if(C_B_TYPE == `c_signed || (C_B_TYPE == `c_pin && intB_SIGNED == 1)) + tmpE[tmpWidth-2] = tmpBC[tmpWidth-1]; + else + tmpE[tmpWidth-2] = 1'b0; + if((C_ADD_MODE == `c_add_sub && intADD == 1) || C_ADD_MODE == `c_add) + begin + tmpF = sm_add(tmpD, tmpE); + end + else if((C_ADD_MODE == `c_add_sub && intADD == 0) || C_ADD_MODE == `c_sub) + begin + tmpF = sm_sub(tmpD, tmpE); + end + + intOVFL <= #1 tmpF[tmpWidth-3] ^ tmpABC[tmpWidth-2]; + end + end + end + + always@(posedge CLK) + lastADD <= intADD; + + always@(posedge CLK) + begin + if(CLK === 1'b1 && lastCLK === 1'b0 && intCE === 1'b1) // OK! Update pipelines! + begin + if (lastADD === intADD) // is pipeline data valid? + begin + for(pipe = 2; pipe <= C_LATENCY-1; pipe = pipe + 1) + begin + intQpipe[pipe] <= intQpipe[pipe+1]; + intQ_C_OUTpipe[pipe] <= intQ_C_OUTpipe[pipe+1]; + intQ_B_OUTpipe[pipe] <= intQ_B_OUTpipe[pipe+1]; + intQ_OVFLpipe[pipe] <= intQ_OVFLpipe[pipe+1]; + end + end + else + begin + for(pipe = 2; pipe <= C_LATENCY-1; pipe = pipe + 1) + begin + intQpipe[pipe] <= 'bx; + intQ_C_OUTpipe[pipe] <= 1'bx; + intQ_B_OUTpipe[pipe] <= 1'bx; + intQ_OVFLpipe[pipe] <= 1'bx; + end + end + intQpipe[C_LATENCY] <= intS; + intQ_C_OUTpipe[C_LATENCY] <= intC_OUT; + intQ_B_OUTpipe[C_LATENCY] <= intB_OUT; + intQ_OVFLpipe[C_LATENCY] <= intOVFL; + end + else if((CLK === 1'bx && lastCLK === 1'b0) || (CLK === 1'b1 && lastCLK === 1'bx) || intCE === 1'bx) // POSSIBLY Update pipelines! + begin + for(pipe = 2; pipe <= C_LATENCY-1; pipe = pipe + 1) + begin + if(intQ_C_OUTpipe[pipe] !== intQ_C_OUTpipe[pipe+1]) + intQ_C_OUTpipe[pipe] <= 1'bx; + if(intQ_B_OUTpipe[pipe] !== intQ_B_OUTpipe[pipe+1]) + intQ_B_OUTpipe[pipe] <= 1'bx; + if(intQ_OVFLpipe[pipe] !== intQ_OVFLpipe[pipe+1]) + intQ_OVFLpipe[pipe] <= 1'bx; + tmp_pipe1 = intQpipe[pipe]; + tmp_pipe2 = intQpipe[pipe+1]; + for(pipe1 = C_LOW_BIT; pipe1 < C_HIGH_BIT+1; pipe1 = pipe1 + 1) + begin + if(tmp_pipe1[pipe1] !== tmp_pipe2[pipe1]) + tmp_pipe1[pipe1] = 1'bx; + end + intQpipe[pipe] <= tmp_pipe1; + end + if(intQ_C_OUTpipe[C_LATENCY] !== intC_OUT) + intQ_C_OUTpipe[C_LATENCY] <= 1'bx; + if(intQ_B_OUTpipe[C_LATENCY] !== intB_OUT) + intQ_B_OUTpipe[C_LATENCY] <= 1'bx; + if(intQ_OVFLpipe[C_LATENCY] !== intOVFL) + intQ_OVFLpipe[C_LATENCY] <= 1'bx; + for(pipe1 = C_LOW_BIT; pipe1 < C_HIGH_BIT+1; pipe1 = pipe1 + 1) + begin + if(tmp_pipe1[pipe1] !== intS[pipe1]) + tmp_pipe1[pipe1] = 1'bx; + end + intQpipe[C_LATENCY] <= tmp_pipe1; + end + end + + always@(intS or intQpipe[2] or intADD or lastADD) + begin + if(C_LATENCY < 2) // No pipeline + intQpipeend <= intS; + else if (lastADD === intADD) + // Pipeline stages required + intQpipeend <= intQpipe[2]; + else + // pipeline data invalid + intQpipeend <= 'bx; + end + + always@(intC_OUT or intQ_C_OUTpipe[2] or intADD or lastADD) + begin + if(C_LATENCY < 2) // No pipeline + intQ_C_OUTpipeend <= intC_OUT; + else if (lastADD === intADD) + // Pipeline stages required + intQ_C_OUTpipeend <= intQ_C_OUTpipe[2]; + else + // Pipeline data invalid + intQ_C_OUTpipeend <= 1'bx; + end + + always@(intB_OUT or intQ_B_OUTpipe[2] or intADD or lastADD) + begin + if(C_LATENCY < 2) // No pipeline + intQ_B_OUTpipeend <= intB_OUT; + else if (lastADD === intADD) + // Pipeline stages required + intQ_B_OUTpipeend <= intQ_B_OUTpipe[2]; + else + intQ_B_OUTpipeend <= 1'bx; + end + + always@(intOVFL or intQ_OVFLpipe[2] or intADD or lastADD) + begin + if(C_LATENCY < 2) // No pipeline + intQ_OVFLpipeend <= intOVFL; + else if (lastADD === intADD) + // Pipeline stages required + intQ_OVFLpipeend <= intQ_OVFLpipe[2]; + else + intQ_OVFLpipeend <= 1'bx; + end + + always@(CLK) + lastCLK <= CLK; + +/* helper functions */ + + function defval; + input i; + input hassig; + input val; + begin + if(hassig == 1) + defval = i; + else + defval = val; + end + endfunction + + function [C_B_WIDTH - 1 : 0] to_bitsB; + input [C_B_WIDTH*8 : 1] instring; + integer i; + integer non_null_string; + begin + non_null_string = 0; + for(i = C_B_WIDTH; i > 0; i = i - 1) + begin // Is the string empty? + if(instring[(i*8)] == 0 && + instring[(i*8)-1] == 0 && + instring[(i*8)-2] == 0 && + instring[(i*8)-3] == 0 && + instring[(i*8)-4] == 0 && + instring[(i*8)-5] == 0 && + instring[(i*8)-6] == 0 && + instring[(i*8)-7] == 0 && + non_null_string == 0) + non_null_string = 0; // Use the return value to flag a non-empty string + else + non_null_string = 1; // Non-null character! + end + if(non_null_string == 0) // String IS empty! Just return the value to be all '0's + begin + for(i = C_B_WIDTH; i > 0; i = i - 1) + to_bitsB[i-1] = 0; + end + else + begin + for(i = C_B_WIDTH; i > 0; i = i - 1) + begin // Is this character a '0'? (ASCII = 48 = 00110000) + if(instring[(i*8)] == 0 && + instring[(i*8)-1] == 0 && + instring[(i*8)-2] == 1 && + instring[(i*8)-3] == 1 && + instring[(i*8)-4] == 0 && + instring[(i*8)-5] == 0 && + instring[(i*8)-6] == 0 && + instring[(i*8)-7] == 0) + to_bitsB[i-1] = 0; + // Or is it a '1'? + else if(instring[(i*8)] == 0 && + instring[(i*8)-1] == 0 && + instring[(i*8)-2] == 1 && + instring[(i*8)-3] == 1 && + instring[(i*8)-4] == 0 && + instring[(i*8)-5] == 0 && + instring[(i*8)-6] == 0 && + instring[(i*8)-7] == 1) + to_bitsB[i-1] = 1; + // Or is it a ' '? (a null char - in which case insert a '0') + else if(instring[(i*8)] == 0 && + instring[(i*8)-1] == 0 && + instring[(i*8)-2] == 0 && + instring[(i*8)-3] == 0 && + instring[(i*8)-4] == 0 && + instring[(i*8)-5] == 0 && + instring[(i*8)-6] == 0 && + instring[(i*8)-7] == 0) + to_bitsB[i-1] = 0; + else + begin + $display("Error: non-binary digit in string \"%s\"\nExiting simulation...", instring); + $finish; + end + end + end + end + endfunction + + function max; + input a; + input b; + begin + max = (a > b) ? a : b; + end + endfunction + + function is_X; + input [tmpWidth-1 : 0] i; + begin + is_X = 1'b0; + for(j = 0; j < tmpWidth; j = j + 1) + begin + if(i[j] === 1'bx) + is_X = 1'b1; + end // loop + end + endfunction + + function [tmpWidth-1 : 0] add; + input [tmpWidth-1 : 0] i1; + input [tmpWidth-1 : 0] i2; + integer bit_index; + integer carryin, carryout; + begin + carryin = 0; + carryout = 0; + for(bit_index=0; bit_index < tmpWidth; bit_index = bit_index + 1) + begin + add[bit_index] = i1[bit_index] ^ i2[bit_index] ^ carryin; + carryout = (i1[bit_index] && i2[bit_index]) || (carryin && (i1[bit_index] || i2[bit_index])); + carryin = carryout; + end + end + endfunction + + function [tmpWidth-1 : 0] sub; + input [tmpWidth-1 : 0] i1; + input [tmpWidth-1 : 0] i2; + begin + i2 = add(~i2, 1); + sub = add(i1, i2); + end + endfunction + + function [tmpWidth-2 : 0] sm_add; + input [tmpWidth-2 : 0] i1; + input [tmpWidth-2 : 0] i2; + integer bit_index; + integer carryin, carryout; + begin + carryin = 0; + carryout = 0; + for(bit_index=0; bit_index < tmpWidth-1; bit_index = bit_index + 1) + begin + sm_add[bit_index] = i1[bit_index] ^ i2[bit_index] ^ carryin; + carryout = (i1[bit_index] && i2[bit_index]) || (carryin && (i1[bit_index] || i2[bit_index])); + carryin = carryout; + end + end + endfunction + + function [tmpWidth-2 : 0] sm_sub; + input [tmpWidth-2 : 0] i1; + input [tmpWidth-2 : 0] i2; + begin + i2 = sm_add(~i2, 1); + sm_sub = sm_add(i1, i2); + end + endfunction + +endmodule + +`undef c_set +`undef c_clear +`undef c_override +`undef c_no_override +`undef c_add +`undef c_sub +`undef c_add_sub +`undef c_signed +`undef c_unsigned +`undef c_pin +`undef allUKs + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/C_ADDSUB_V5_0.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/C_ADDSUB_V5_0.v new file mode 100644 index 0000000..a735cb2 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/C_ADDSUB_V5_0.v @@ -0,0 +1,684 @@ +/* $Id: C_ADDSUB_V5_0.v,v 1.17 2008/09/08 20:05:55 akennedy Exp $ +-- +-- Filename - C_ADDSUB_V5_0.v +-- Author - Xilinx +-- Creation - 22 Mar 1999 +-- +-- Description - This file contains the Verilog behavior for the Baseblocks C_ADDSUB_V5_0 module +*/ + +`timescale 1ns/10ps + +`define c_set 0 +`define c_clear 1 +`define c_override 0 +`define c_no_override 1 +`define c_add 0 +`define c_sub 1 +`define c_add_sub 2 +`define c_signed 0 +`define c_unsigned 1 +`define c_pin 2 +`define allUKs {(C_HIGH_BIT-C_LOW_BIT)+1{1'bx}} + +module C_ADDSUB_V5_0 (A, B, CLK, ADD, C_IN, B_IN, CE, BYPASS, ACLR, ASET, AINIT, + SCLR, SSET, SINIT, A_SIGNED, B_SIGNED, OVFL, C_OUT, B_OUT, + Q_OVFL, Q_C_OUT, Q_B_OUT, S, Q); + + parameter C_ADD_MODE = `c_add; + parameter C_AINIT_VAL = "0"; + parameter C_A_TYPE = `c_unsigned; + parameter C_A_WIDTH = 16; + parameter C_BYPASS_ENABLE = `c_override; + parameter C_BYPASS_LOW = 0; + parameter C_B_CONSTANT = 0; + parameter C_B_TYPE = `c_unsigned; + parameter C_B_VALUE = "0000000000000000"; + parameter C_B_WIDTH = 16; + parameter C_ENABLE_RLOCS = 1; + parameter C_HAS_ACLR = 0; + parameter C_HAS_ADD = 0; + parameter C_HAS_AINIT = 0; + parameter C_HAS_ASET = 0; + parameter C_HAS_A_SIGNED = 0; + parameter C_HAS_BYPASS = 0; + parameter C_HAS_BYPASS_WITH_CIN = 0; + parameter C_HAS_B_IN = 1; + parameter C_HAS_B_OUT = 0; + parameter C_HAS_B_SIGNED = 0; + parameter C_HAS_CE = 0; + parameter C_HAS_C_IN = 1; + parameter C_HAS_C_OUT = 0; + parameter C_HAS_OVFL = 0; + parameter C_HAS_Q = 1; + parameter C_HAS_Q_B_OUT = 0; + parameter C_HAS_Q_C_OUT = 0; + parameter C_HAS_Q_OVFL = 0; + parameter C_HAS_S = 0; + parameter C_HAS_SCLR = 0; + parameter C_HAS_SINIT = 0; + parameter C_HAS_SSET = 0; + parameter C_HIGH_BIT = 15; + parameter C_LATENCY = 1; + parameter C_LOW_BIT = 0; + parameter C_OUT_WIDTH = 16; + parameter C_PIPE_STAGES = 1; + parameter C_SINIT_VAL = "0"; + parameter C_SYNC_ENABLE = `c_override; + parameter C_SYNC_PRIORITY = `c_clear; + + + // internal parameters (not to be set from instanciation) + parameter tmpWidth = (C_A_WIDTH > C_B_WIDTH) ? C_A_WIDTH + 2 : C_B_WIDTH + 2; + parameter output_reg_width = C_HIGH_BIT-C_LOW_BIT+1; + + input [C_A_WIDTH-1 : 0] A; + input [C_B_WIDTH-1 : 0] B; + input CLK; + input ADD; + input C_IN; + input B_IN; + input CE; + input BYPASS; + input ACLR; + input ASET; + input AINIT; + input SCLR; + input SSET; + input SINIT; + input A_SIGNED; + input B_SIGNED; + output OVFL; + output C_OUT; + output B_OUT; + output Q_OVFL; + output Q_C_OUT; + output Q_B_OUT; + output [C_HIGH_BIT : C_LOW_BIT] S; + output [C_HIGH_BIT : C_LOW_BIT] Q; + + + + // Internal values to drive signals when input is missing + wire [C_B_WIDTH-1 : 0] intBconst; + wire [C_B_WIDTH-1 : 0] intB; + wire intADD; + wire intBYPASS; + wire intC_IN; + wire intB_IN; + wire intCE; + wire intQCE; + wire intA_SIGNED; + wire intB_SIGNED; + reg intC_OUT; + reg intB_OUT; + reg intOVFL; + wire intQ_C_OUT; + wire intQ_B_OUT; + wire intQ_OVFL; + reg [C_HIGH_BIT : C_LOW_BIT ] intS; + wire [C_HIGH_BIT : C_LOW_BIT ] intQ; + wire intACLR; + wire intASET; + wire intAINIT; + wire intSCLR; + wire intSSET; + wire intSINIT; + wire intACLR_INIT; + wire intSCLR_INIT; + wire intBYPASS_WITH_CIN; // New signal for bypass with Cin mode + reg lastCLK; + reg lastADD; + + reg [C_HIGH_BIT : C_LOW_BIT] intQpipe [C_LATENCY+2 : 0]; + reg [C_LATENCY+2 : 0] intQ_C_OUTpipe; + reg [C_LATENCY+2 : 0] intQ_B_OUTpipe; + reg [C_LATENCY+2 : 0] intQ_OVFLpipe; + + reg [C_HIGH_BIT : C_LOW_BIT] intQpipeend; + reg intQ_C_OUTpipeend; + reg intQ_B_OUTpipeend; + reg intQ_OVFLpipeend; + reg [C_HIGH_BIT : C_LOW_BIT] tmp_pipe1; + reg [C_HIGH_BIT : C_LOW_BIT] tmp_pipe2; + + + wire [C_HIGH_BIT : C_LOW_BIT] Q = (C_HAS_Q == 1 ? intQ : `allUKs); + wire Q_C_OUT = (C_HAS_Q_C_OUT == 1 ? intQ_C_OUT : 1'bx); + wire Q_B_OUT = (C_HAS_Q_B_OUT == 1 ? intQ_B_OUT : 1'bx); + wire Q_OVFL = (C_HAS_Q_OVFL == 1 ? intQ_OVFL : 1'bx); + wire [C_HIGH_BIT : C_LOW_BIT] S = (C_HAS_S == 1 ? intS : `allUKs); + wire C_OUT = (C_HAS_C_OUT == 1 ? intC_OUT : 1'bx); + wire B_OUT = (C_HAS_B_OUT == 1 ? intB_OUT : 1'bx); + wire OVFL = (C_HAS_OVFL == 1 ? intOVFL : 1'bx); + + // Sort out default values for missing ports + + assign intCE = defval(CE, C_HAS_CE, 1); + assign intACLR = defval(ACLR, C_HAS_ACLR, 0); + assign intASET = defval(ASET, C_HAS_ASET, 0); + assign intAINIT = defval(AINIT, C_HAS_AINIT, 0); + assign intSCLR = defval(SCLR, C_HAS_SCLR, 0); + assign intSSET = defval(SSET, C_HAS_SSET, 0); + assign intSINIT = defval(SINIT, C_HAS_SINIT, 0); + assign intACLR_INIT = (intACLR || intAINIT); + assign intSCLR_INIT = (intSCLR || intSINIT); + + assign intBconst = (C_B_CONSTANT === 1) ? to_bitsB(C_B_VALUE) : B; + assign intADD = (C_HAS_ADD === 1) ? ADD : ((C_ADD_MODE === `c_add) ? 1 : ((C_ADD_MODE === `c_sub) ? 0 : 3)); // 3 is an illegal value since this is an illegal option! + assign intBYPASS = (C_HAS_BYPASS === 1) ? ((C_BYPASS_LOW === 1) ? !BYPASS : BYPASS) : 0; + assign intBYPASS_WITH_CIN = C_HAS_BYPASS_WITH_CIN; // new parameter to allow the bypass mode to take account of the c_in + assign intC_IN = ((C_HAS_C_IN === 1) ? C_IN : ((C_HAS_ADD === 1) ? ~intADD : 0)); + assign intB_IN = defval(B_IN, C_HAS_B_IN, 1); + assign intA_SIGNED = defval(A_SIGNED, C_HAS_A_SIGNED, 0); + //assign intB_SIGNED = defval(B_SIGNED, C_HAS_B_SIGNED, 0); + assign intB_SIGNED = ((C_HAS_B_SIGNED === 0) ? 0 : (((C_HAS_B_SIGNED === 1) && ~((C_B_CONSTANT === 1) && (C_HAS_BYPASS === 0) && (C_B_VALUE[((C_B_WIDTH*8)-1):((C_B_WIDTH-1)*8)] === "0")) ? B_SIGNED : 0))) ; + assign intB = (intBYPASS === 0 ? intBconst : B); + assign intQCE = (C_HAS_CE === 1 ? (C_HAS_BYPASS === 1 ? (C_BYPASS_ENABLE === `c_override ? CE || intBYPASS : CE) : CE) : 1'b1); + + integer j, k; + integer pipe, pipe1; + integer i; + + reg [tmpWidth-1 : 0] tmpA; + reg [tmpWidth-1 : 0] tmpB; + reg [tmpWidth-1 : 0] tmpC; + reg [tmpWidth-1 : 0] tmpBC; + reg [tmpWidth-1 : 0] tmpABC; + reg [tmpWidth-2 : 0] tmpD; + reg [tmpWidth-2 : 0] tmpE; + reg [tmpWidth-2 : 0] tmpF; + + // Registers on outputs by default + C_REG_FD_V5_0 #(C_AINIT_VAL, C_ENABLE_RLOCS, C_HAS_ACLR, C_HAS_AINIT, C_HAS_ASET, + C_HAS_CE, C_HAS_SCLR, C_HAS_SINIT, C_HAS_SSET, + C_SINIT_VAL, C_SYNC_ENABLE, C_SYNC_PRIORITY, output_reg_width) + regq (.D(intQpipeend), .CLK(CLK), .CE(intQCE), .ACLR(ACLR), .ASET(ASET), + .AINIT(AINIT), .SCLR(SCLR), .SSET(SSET), .SINIT(SINIT), + .Q(intQ)); + + C_REG_FD_V5_0 #("0", C_ENABLE_RLOCS, C_HAS_ACLR, C_HAS_AINIT, C_HAS_ASET, + C_HAS_CE, C_HAS_SCLR, C_HAS_SINIT, C_HAS_SSET, + "0", C_SYNC_ENABLE, C_SYNC_PRIORITY, 1) + regcout (.D(intQ_C_OUTpipeend), .CLK(CLK), .CE(intQCE), .ACLR(intACLR_INIT), + .AINIT(AINIT), .ASET(ASET), .SCLR(intSCLR_INIT), .SINIT(SINIT), .SSET(SSET), + .Q(intQ_C_OUT)); + + C_REG_FD_V5_0 #("0", C_ENABLE_RLOCS, C_HAS_ACLR, C_HAS_AINIT, C_HAS_ASET, + C_HAS_CE, C_HAS_SCLR, C_HAS_SINIT, C_HAS_SSET, + "0", C_SYNC_ENABLE, C_SYNC_PRIORITY, 1) + regbout (.D(intQ_B_OUTpipeend), .CLK(CLK), .CE(intQCE), .ACLR(intACLR_INIT), + .AINIT(AINIT), .ASET(ASET), .SCLR(intSCLR_INIT), .SINIT(SINIT), .SSET(SSET), + .Q(intQ_B_OUT)); + + C_REG_FD_V5_0 #("0", C_ENABLE_RLOCS, C_HAS_ACLR, C_HAS_AINIT, C_HAS_ASET, + C_HAS_CE, C_HAS_SCLR, C_HAS_SINIT, C_HAS_SSET, + "0", C_SYNC_ENABLE, C_SYNC_PRIORITY, 1) + regovfl (.D(intQ_OVFLpipeend), .CLK(CLK), .CE(intQCE), .ACLR(intACLR_INIT), + .AINIT(AINIT), .ASET(ASET), .SCLR(intSCLR_INIT), .SINIT(SINIT), .SSET(SSET), + .Q(intQ_OVFL)); + + initial + begin + #1; + for(i = 0; i <= C_LATENCY+2; i = i + 1) + begin + intQpipe[i] = 'bx; + intQ_C_OUTpipe[i] = 1'bx; + intQ_B_OUTpipe[i] = 1'bx; + intQ_OVFLpipe[i] = 1'bx; + end + intQpipeend = `allUKs; + intQ_C_OUTpipeend = 0; + intQ_B_OUTpipeend = 0; + intQ_OVFLpipeend = 0; + intS = `allUKs; + intC_OUT = 0; + intB_OUT = 0; + intOVFL = 0; + end + + always@(A or intB or intADD or intBYPASS or intC_IN or intB_IN or intA_SIGNED or intB_SIGNED) + begin + tmpC = 0; + if(intC_IN !== 1'b0) + begin + if((C_ADD_MODE == `c_add_sub && intADD == 1) || C_ADD_MODE == `c_add) + begin + tmpC = intC_IN; + end + end + else if(intC_IN !== 1'b1 && C_ADD_MODE == `c_add_sub && intADD === 1'b0) + begin + tmpC[0] = ~intC_IN; + end + else if(intB_IN !== 1'b1 && C_ADD_MODE == `c_sub) + begin + tmpC[0] = ~intB_IN; + end + + if(C_A_TYPE == `c_signed || (C_A_TYPE == `c_pin && intA_SIGNED === 1)) + begin + for(j = tmpWidth-1; j >= C_A_WIDTH; j = j - 1) + begin + tmpA[j] = A[C_A_WIDTH-1]; + end + end + else if(C_A_TYPE == `c_unsigned || (C_A_TYPE == `c_pin && intA_SIGNED === 0)) + begin + for(j = tmpWidth-1; j >= C_A_WIDTH; j = j - 1) + begin + tmpA[j] = 0; + end + end + + tmpA[C_A_WIDTH-1 : 0] = A; + + if(C_B_TYPE == `c_signed || (C_B_TYPE == `c_pin && intB_SIGNED === 1)) + begin + for(j = tmpWidth-1; j >= C_B_WIDTH; j = j - 1) + begin + tmpB[j] = intB[C_B_WIDTH-1]; + end + end + else if(C_B_TYPE == `c_unsigned || (C_B_TYPE == `c_pin && intB_SIGNED === 0)) + begin + for(j = tmpWidth-1; j >= C_B_WIDTH; j = j - 1) + begin + tmpB[j] = 0; + end + end + + tmpB[C_B_WIDTH-1 : 0] = intB; + + if(intBYPASS == 1 && intBYPASS_WITH_CIN == 0) + begin + intS <= #1 tmpB[C_HIGH_BIT : C_LOW_BIT]; + if (is_X(tmpB) && C_LATENCY >1) + begin + intC_OUT <= #1 1'bx; + intB_OUT <= #1 1'bx; + intOVFL <= #1 1'bx; + end + else + begin + intC_OUT <= #1 1'b0; + intB_OUT <= #1 1'b0; + intOVFL <= #1 1'b0; + end + end + else if(is_X(tmpA) || is_X(tmpB) || is_X(tmpC) || intBYPASS === 1'bx || intADD === 1'bx) + begin + intS <= #1 {C_HIGH_BIT-C_LOW_BIT+1{1'bx}}; + intC_OUT <= #1 1'bx; + intB_OUT <= #1 1'bx; + intOVFL <= #1 1'bx; + end + else if (intBYPASS == 1 && intBYPASS_WITH_CIN == 1) // new section to model the behaviour of the new + begin // c_has_bypass_with_cin mode. This mode is only available + tmpBC = add(tmpB, tmpC); // for Adder variations. + + intS <= #1 tmpBC[C_HIGH_BIT : C_LOW_BIT]; + + if(C_HAS_C_OUT == 1 || C_HAS_Q_C_OUT == 1) + begin + intC_OUT <= #1 tmpBC[tmpWidth-2]; + end + + if(C_HAS_OVFL == 1 || C_HAS_Q_OVFL == 1) + begin + + if(C_HAS_OVFL == 1 || C_HAS_Q_OVFL == 1) + begin + tmpD[tmpWidth-2 : 0] = {tmpWidth - 1{1'b0}}; + tmpE[tmpWidth-3 : 0] = tmpBC[tmpWidth-3 : 0]; + tmpE[tmpWidth-2] = tmpBC[tmpWidth-1]; + tmpF = sm_add(tmpD, tmpE); + intOVFL <= #1 tmpF[tmpWidth-3] ^ tmpBC[tmpWidth-2]; + end + end + end + else + begin + if((C_ADD_MODE == `c_add_sub && intADD == 1) || C_ADD_MODE == `c_add) + begin + tmpBC = add(tmpB, tmpC); + end + else if((C_ADD_MODE == `c_add_sub && intADD == 0) || C_ADD_MODE == `c_sub) + begin + tmpBC = add(tmpB, tmpC); + end + + if((C_ADD_MODE == `c_add_sub && intADD == 1) || C_ADD_MODE == `c_add) + begin + tmpABC = add(tmpA, tmpBC); + end + else if((C_ADD_MODE == `c_add_sub && intADD == 0) || C_ADD_MODE == `c_sub) + begin + tmpABC = sub(tmpA, tmpBC); + end + + intS <= #1 tmpABC[C_HIGH_BIT : C_LOW_BIT]; + + if(C_HAS_C_OUT == 1 || C_HAS_Q_C_OUT == 1) + begin + if((C_ADD_MODE == `c_add_sub && intADD === 1'b1) || C_ADD_MODE == `c_add) + intC_OUT <= #1 tmpABC[tmpWidth-2]; + else if(C_ADD_MODE == `c_add_sub && intADD === 1'b0) + intC_OUT <= #1 ~tmpABC[tmpWidth-2]; + end + + if(C_HAS_B_OUT == 1 || C_HAS_Q_B_OUT == 1) + begin + intB_OUT <= #1 !tmpABC[tmpWidth-2]; + end + + if(C_HAS_OVFL == 1 || C_HAS_Q_OVFL == 1) + begin + tmpD[tmpWidth-3 : 0] = tmpA[tmpWidth-3 : 0]; + if(C_A_TYPE == `c_signed || (C_A_TYPE == `c_pin && intA_SIGNED == 1)) + tmpD[tmpWidth-2] = tmpA[tmpWidth-1]; + else + tmpD[tmpWidth-2] = 1'b0; + tmpE[tmpWidth-3 : 0] = tmpBC[tmpWidth-3 : 0]; + if(C_B_TYPE == `c_signed || (C_B_TYPE == `c_pin && intB_SIGNED == 1)) + tmpE[tmpWidth-2] = tmpBC[tmpWidth-1]; + else + tmpE[tmpWidth-2] = 1'b0; + if((C_ADD_MODE == `c_add_sub && intADD == 1) || C_ADD_MODE == `c_add) + begin + tmpF = sm_add(tmpD, tmpE); + end + else if((C_ADD_MODE == `c_add_sub && intADD == 0) || C_ADD_MODE == `c_sub) + begin + tmpF = sm_sub(tmpD, tmpE); + end + + intOVFL <= #1 tmpF[tmpWidth-3] ^ tmpABC[tmpWidth-2]; + end + end + end + + always@(posedge CLK) + lastADD <= intADD; + + always@(posedge CLK) + begin + if(CLK === 1'b1 && lastCLK === 1'b0 && intCE === 1'b1) // OK! Update pipelines! + begin + if (lastADD === intADD) // is pipeline data valid? + begin + for(pipe = 2; pipe <= C_LATENCY-1; pipe = pipe + 1) + begin + intQpipe[pipe] <= intQpipe[pipe+1]; + intQ_C_OUTpipe[pipe] <= intQ_C_OUTpipe[pipe+1]; + intQ_B_OUTpipe[pipe] <= intQ_B_OUTpipe[pipe+1]; + intQ_OVFLpipe[pipe] <= intQ_OVFLpipe[pipe+1]; + end + end + else + begin + for(pipe = 2; pipe <= C_LATENCY-1; pipe = pipe + 1) + begin + intQpipe[pipe] <= 'bx; + intQ_C_OUTpipe[pipe] <= 1'bx; + intQ_B_OUTpipe[pipe] <= 1'bx; + intQ_OVFLpipe[pipe] <= 1'bx; + end + end + intQpipe[C_LATENCY] <= intS; + intQ_C_OUTpipe[C_LATENCY] <= intC_OUT; + intQ_B_OUTpipe[C_LATENCY] <= intB_OUT; + intQ_OVFLpipe[C_LATENCY] <= intOVFL; + end + else if((CLK === 1'bx && lastCLK === 1'b0) || (CLK === 1'b1 && lastCLK === 1'bx) || intCE === 1'bx) // POSSIBLY Update pipelines! + begin + for(pipe = 2; pipe <= C_LATENCY-1; pipe = pipe + 1) + begin + if(intQ_C_OUTpipe[pipe] !== intQ_C_OUTpipe[pipe+1]) + intQ_C_OUTpipe[pipe] <= 1'bx; + if(intQ_B_OUTpipe[pipe] !== intQ_B_OUTpipe[pipe+1]) + intQ_B_OUTpipe[pipe] <= 1'bx; + if(intQ_OVFLpipe[pipe] !== intQ_OVFLpipe[pipe+1]) + intQ_OVFLpipe[pipe] <= 1'bx; + tmp_pipe1 = intQpipe[pipe]; + tmp_pipe2 = intQpipe[pipe+1]; + for(pipe1 = C_LOW_BIT; pipe1 < C_HIGH_BIT+1; pipe1 = pipe1 + 1) + begin + if(tmp_pipe1[pipe1] !== tmp_pipe2[pipe1]) + tmp_pipe1[pipe1] = 1'bx; + end + intQpipe[pipe] <= tmp_pipe1; + end + if(intQ_C_OUTpipe[C_LATENCY] !== intC_OUT) + intQ_C_OUTpipe[C_LATENCY] <= 1'bx; + if(intQ_B_OUTpipe[C_LATENCY] !== intB_OUT) + intQ_B_OUTpipe[C_LATENCY] <= 1'bx; + if(intQ_OVFLpipe[C_LATENCY] !== intOVFL) + intQ_OVFLpipe[C_LATENCY] <= 1'bx; + for(pipe1 = C_LOW_BIT; pipe1 < C_HIGH_BIT+1; pipe1 = pipe1 + 1) + begin + if(tmp_pipe1[pipe1] !== intS[pipe1]) + tmp_pipe1[pipe1] = 1'bx; + end + intQpipe[C_LATENCY] <= tmp_pipe1; + end + end + + always@(intS or intQpipe[2] or intADD or lastADD) + begin + if(C_LATENCY < 2) // No pipeline + intQpipeend <= intS; + else if (lastADD === intADD) + // Pipeline stages required + intQpipeend <= intQpipe[2]; + else + // pipeline data invalid + intQpipeend <= 'bx; + end + + always@(intC_OUT or intQ_C_OUTpipe[2] or intADD or lastADD) + begin + if(C_LATENCY < 2) // No pipeline + intQ_C_OUTpipeend <= intC_OUT; + else if (lastADD === intADD) + // Pipeline stages required + intQ_C_OUTpipeend <= intQ_C_OUTpipe[2]; + else + // Pipeline data invalid + intQ_C_OUTpipeend <= 1'bx; + end + + always@(intB_OUT or intQ_B_OUTpipe[2] or intADD or lastADD) + begin + if(C_LATENCY < 2) // No pipeline + intQ_B_OUTpipeend <= intB_OUT; + else if (lastADD === intADD) + // Pipeline stages required + intQ_B_OUTpipeend <= intQ_B_OUTpipe[2]; + else + intQ_B_OUTpipeend <= 1'bx; + end + + always@(intOVFL or intQ_OVFLpipe[2] or intADD or lastADD) + begin + if(C_LATENCY < 2) // No pipeline + intQ_OVFLpipeend <= intOVFL; + else if (lastADD === intADD) + // Pipeline stages required + intQ_OVFLpipeend <= intQ_OVFLpipe[2]; + else + intQ_OVFLpipeend <= 1'bx; + end + + always@(CLK) + lastCLK <= CLK; + +/* helper functions */ + + function defval; + input i; + input hassig; + input val; + begin + if(hassig == 1) + defval = i; + else + defval = val; + end + endfunction + + function [C_B_WIDTH - 1 : 0] to_bitsB; + input [C_B_WIDTH*8 : 1] instring; + integer i; + integer non_null_string; + begin + non_null_string = 0; + for(i = C_B_WIDTH; i > 0; i = i - 1) + begin // Is the string empty? + if(instring[(i*8)] == 0 && + instring[(i*8)-1] == 0 && + instring[(i*8)-2] == 0 && + instring[(i*8)-3] == 0 && + instring[(i*8)-4] == 0 && + instring[(i*8)-5] == 0 && + instring[(i*8)-6] == 0 && + instring[(i*8)-7] == 0 && + non_null_string == 0) + non_null_string = 0; // Use the return value to flag a non-empty string + else + non_null_string = 1; // Non-null character! + end + if(non_null_string == 0) // String IS empty! Just return the value to be all '0's + begin + for(i = C_B_WIDTH; i > 0; i = i - 1) + to_bitsB[i-1] = 0; + end + else + begin + for(i = C_B_WIDTH; i > 0; i = i - 1) + begin // Is this character a '0'? (ASCII = 48 = 00110000) + if(instring[(i*8)] == 0 && + instring[(i*8)-1] == 0 && + instring[(i*8)-2] == 1 && + instring[(i*8)-3] == 1 && + instring[(i*8)-4] == 0 && + instring[(i*8)-5] == 0 && + instring[(i*8)-6] == 0 && + instring[(i*8)-7] == 0) + to_bitsB[i-1] = 0; + // Or is it a '1'? + else if(instring[(i*8)] == 0 && + instring[(i*8)-1] == 0 && + instring[(i*8)-2] == 1 && + instring[(i*8)-3] == 1 && + instring[(i*8)-4] == 0 && + instring[(i*8)-5] == 0 && + instring[(i*8)-6] == 0 && + instring[(i*8)-7] == 1) + to_bitsB[i-1] = 1; + // Or is it a ' '? (a null char - in which case insert a '0') + else if(instring[(i*8)] == 0 && + instring[(i*8)-1] == 0 && + instring[(i*8)-2] == 0 && + instring[(i*8)-3] == 0 && + instring[(i*8)-4] == 0 && + instring[(i*8)-5] == 0 && + instring[(i*8)-6] == 0 && + instring[(i*8)-7] == 0) + to_bitsB[i-1] = 0; + else + begin + $display("Error in %m at time %d ns: non-binary digit in string \"%s\"\nExiting simulation...",$time, instring); + $finish; + end + end + end + end + endfunction + + function max; + input a; + input b; + begin + max = (a > b) ? a : b; + end + endfunction + + function is_X; + input [tmpWidth-1 : 0] i; + begin + is_X = 1'b0; + for(j = 0; j < tmpWidth; j = j + 1) + begin + if(i[j] === 1'bx) + is_X = 1'b1; + end // loop + end + endfunction + + function [tmpWidth-1 : 0] add; + input [tmpWidth-1 : 0] i1; + input [tmpWidth-1 : 0] i2; + integer bit_index; + integer carryin, carryout; + begin + carryin = 0; + carryout = 0; + for(bit_index=0; bit_index < tmpWidth; bit_index = bit_index + 1) + begin + add[bit_index] = i1[bit_index] ^ i2[bit_index] ^ carryin; + carryout = (i1[bit_index] && i2[bit_index]) || (carryin && (i1[bit_index] || i2[bit_index])); + carryin = carryout; + end + end + endfunction + + function [tmpWidth-1 : 0] sub; + input [tmpWidth-1 : 0] i1; + input [tmpWidth-1 : 0] i2; + begin + i2 = add(~i2, 1); + sub = add(i1, i2); + end + endfunction + + function [tmpWidth-2 : 0] sm_add; + input [tmpWidth-2 : 0] i1; + input [tmpWidth-2 : 0] i2; + integer bit_index; + integer carryin, carryout; + begin + carryin = 0; + carryout = 0; + for(bit_index=0; bit_index < tmpWidth-1; bit_index = bit_index + 1) + begin + sm_add[bit_index] = i1[bit_index] ^ i2[bit_index] ^ carryin; + carryout = (i1[bit_index] && i2[bit_index]) || (carryin && (i1[bit_index] || i2[bit_index])); + carryin = carryout; + end + end + endfunction + + function [tmpWidth-2 : 0] sm_sub; + input [tmpWidth-2 : 0] i1; + input [tmpWidth-2 : 0] i2; + begin + i2 = sm_add(~i2, 1); + sm_sub = sm_add(i1, i2); + end + endfunction + +endmodule + +`undef c_set +`undef c_clear +`undef c_override +`undef c_no_override +`undef c_add +`undef c_sub +`undef c_add_sub +`undef c_signed +`undef c_unsigned +`undef c_pin +`undef allUKs diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/C_ADDSUB_V6_0.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/C_ADDSUB_V6_0.v new file mode 100644 index 0000000..0e41550 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/C_ADDSUB_V6_0.v @@ -0,0 +1,742 @@ +// Copyright(C) 2002 by Xilinx, Inc. All rights reserved. +// This text contains proprietary, confidential +// information of Xilinx, Inc., is distributed +// under license from Xilinx, Inc., and may be used, +// copied and/or disclosed only pursuant to the terms +// of a valid license agreement with Xilinx, Inc. This copyright +// notice must be retained as part of this text at all times. + + +/* $Id: C_ADDSUB_V6_0.v,v 1.16 2008/09/08 20:06:04 akennedy Exp $ +-- +-- Filename - C_ADDSUB_V6_0.v +-- Author - Xilinx +-- Creation - 22 Mar 1999 +-- +-- Description - This file contains the Verilog behavior for the Baseblocks C_ADDSUB_V6_0 module +*/ + +`timescale 1ns/10ps + +`define c_set 0 +`define c_clear 1 +`define c_override 0 +`define c_no_override 1 +`define c_add 0 +`define c_sub 1 +`define c_add_sub 2 +`define c_signed 0 +`define c_unsigned 1 +`define c_pin 2 +`define allUKs {(C_HIGH_BIT-C_LOW_BIT)+1{1'bx}} + +module C_ADDSUB_V6_0 (A, B, CLK, ADD, C_IN, B_IN, CE, BYPASS, ACLR, ASET, AINIT, + SCLR, SSET, SINIT, A_SIGNED, B_SIGNED, OVFL, C_OUT, B_OUT, + Q_OVFL, Q_C_OUT, Q_B_OUT, S, Q); + + parameter C_ADD_MODE = `c_add; + parameter C_AINIT_VAL = "0"; + parameter C_A_TYPE = `c_unsigned; + parameter C_A_WIDTH = 16; + parameter C_BYPASS_ENABLE = `c_override; + parameter C_BYPASS_LOW = 0; + parameter C_B_CONSTANT = 0; + parameter C_B_TYPE = `c_unsigned; + parameter C_B_VALUE = "0000000000000000"; + parameter C_B_WIDTH = 16; + parameter C_ENABLE_RLOCS = 1; + parameter C_HAS_ACLR = 0; + parameter C_HAS_ADD = 0; + parameter C_HAS_AINIT = 0; + parameter C_HAS_ASET = 0; + parameter C_HAS_A_SIGNED = 0; + parameter C_HAS_BYPASS = 0; + parameter C_HAS_BYPASS_WITH_CIN = 0; + parameter C_HAS_B_IN = 1; + parameter C_HAS_B_OUT = 0; + parameter C_HAS_B_SIGNED = 0; + parameter C_HAS_CE = 0; + parameter C_HAS_C_IN = 1; + parameter C_HAS_C_OUT = 0; + parameter C_HAS_OVFL = 0; + parameter C_HAS_Q = 1; + parameter C_HAS_Q_B_OUT = 0; + parameter C_HAS_Q_C_OUT = 0; + parameter C_HAS_Q_OVFL = 0; + parameter C_HAS_S = 0; + parameter C_HAS_SCLR = 0; + parameter C_HAS_SINIT = 0; + parameter C_HAS_SSET = 0; + parameter C_HIGH_BIT = 15; + parameter C_LATENCY = 1; + parameter C_LOW_BIT = 0; + parameter C_OUT_WIDTH = 16; + parameter C_PIPE_STAGES = 1; + parameter C_SINIT_VAL = "0"; + parameter C_SYNC_ENABLE = `c_override; + parameter C_SYNC_PRIORITY = `c_clear; + + + // internal parameters (not to be set from instanciation) + parameter tmpWidth = (C_A_WIDTH > C_B_WIDTH) ? C_A_WIDTH + 2 : C_B_WIDTH + 2; + parameter output_reg_width = C_HIGH_BIT-C_LOW_BIT+1; + + input [C_A_WIDTH-1 : 0] A; + input [C_B_WIDTH-1 : 0] B; + input CLK; + input ADD; + input C_IN; + input B_IN; + input CE; + input BYPASS; + input ACLR; + input ASET; + input AINIT; + input SCLR; + input SSET; + input SINIT; + input A_SIGNED; + input B_SIGNED; + output OVFL; + output C_OUT; + output B_OUT; + output Q_OVFL; + output Q_C_OUT; + output Q_B_OUT; + output [C_HIGH_BIT : C_LOW_BIT] S; + output [C_HIGH_BIT : C_LOW_BIT] Q; + + + + // Internal values to drive signals when input is missing + wire [C_B_WIDTH-1 : 0] intBconst; + wire [C_B_WIDTH-1 : 0] intB; + wire intADD; + wire intBYPASS; + wire intC_IN; + wire intB_IN; + wire intCE; + wire intQCE; + wire intA_SIGNED; + wire intB_SIGNED; + reg intC_OUT; + reg intB_OUT; + reg intOVFL; + wire intQ_C_OUT; + wire intQ_B_OUT; + wire intQ_OVFL; + reg [C_HIGH_BIT : C_LOW_BIT ] intS; + wire [C_HIGH_BIT : C_LOW_BIT ] intQ; + wire intACLR; + wire intASET; + wire intAINIT; + wire intSCLR; + wire intSSET; + wire intSINIT; + wire intACLR_INIT; + wire intSCLR_INIT; + wire intBYPASS_WITH_CIN; // New signal for bypass with Cin mode + reg lastCLK; + reg lastADD; + wire [8 : 1] b_max; + reg [C_HIGH_BIT : C_LOW_BIT] intQpipe [C_LATENCY+2 : 0]; + reg [C_LATENCY+2 : 0] intQ_C_OUTpipe; + reg [C_LATENCY+2 : 0] intQ_B_OUTpipe; + reg [C_LATENCY+2 : 0] intQ_OVFLpipe; + reg [C_LATENCY-1 : 0] intADDpipe; + + reg [C_HIGH_BIT : C_LOW_BIT] intQpipeend; + reg intQ_C_OUTpipeend; + reg intQ_B_OUTpipeend; + reg intQ_OVFLpipeend; + reg [C_HIGH_BIT : C_LOW_BIT] tmp_pipe1; + reg [C_HIGH_BIT : C_LOW_BIT] tmp_pipe2; + + + wire [C_HIGH_BIT : C_LOW_BIT] Q = (C_HAS_Q == 1 ? intQ : `allUKs); + wire Q_C_OUT = (C_HAS_Q_C_OUT == 1 ? intQ_C_OUT : 1'bx); + wire Q_B_OUT = (C_HAS_Q_B_OUT == 1 ? intQ_B_OUT : 1'bx); + wire Q_OVFL = (C_HAS_Q_OVFL == 1 ? intQ_OVFL : 1'bx); + wire [C_HIGH_BIT : C_LOW_BIT] S = (C_HAS_S == 1 ? intS : `allUKs); + wire C_OUT = (C_HAS_C_OUT == 1 ? intC_OUT : 1'bx); + wire B_OUT = (C_HAS_B_OUT == 1 ? intB_OUT : 1'bx); + wire OVFL = (C_HAS_OVFL == 1 ? intOVFL : 1'bx); + + // Sort out default values for missing ports + + assign b_max = max_bval(C_B_VALUE); + assign intCE = defval(CE, C_HAS_CE, 1); + assign intACLR = defval(ACLR, C_HAS_ACLR, 0); + assign intASET = defval(ASET, C_HAS_ASET, 0); + assign intAINIT = defval(AINIT, C_HAS_AINIT, 0); + assign intSCLR = defval(SCLR, C_HAS_SCLR, 0); + assign intSSET = defval(SSET, C_HAS_SSET, 0); + assign intSINIT = defval(SINIT, C_HAS_SINIT, 0); + assign intACLR_INIT = (intACLR || intAINIT); + assign intSCLR_INIT = (intSCLR || intSINIT); + + assign intBconst = (C_B_CONSTANT === 1) ? to_bitsB(C_B_VALUE) : B; +// assign intADD = (C_HAS_ADD === 1) ? ((C_LATENCY < 2) ? ADD : intADDpipe[C_LATENCY-1]) : ((C_ADD_MODE === `c_add) ? 1 : ((C_ADD_MODE === `c_sub) ? 0 : 3)); // 3 is an illegal value since this is an illegal option! + assign intADD = (C_HAS_ADD === 1) ? ADD : (C_ADD_MODE === `c_add) ? 1 : ((C_ADD_MODE === `c_sub) ? 0 : 3); // 3 is an illegal value since this is an illegal option! + assign intBYPASS = (C_HAS_BYPASS === 1) ? ((C_BYPASS_LOW === 1) ? !BYPASS : BYPASS) : 0; + assign intBYPASS_WITH_CIN = C_HAS_BYPASS_WITH_CIN; // new parameter to allow the bypass mode to take account of the c_in + assign intC_IN = ((C_HAS_C_IN === 1) ? C_IN : ((C_HAS_ADD === 1) ? ~intADD : 0)); + assign intB_IN = defval(B_IN, C_HAS_B_IN, 1); + assign intA_SIGNED = defval(A_SIGNED, C_HAS_A_SIGNED, 0); + //assign intB_SIGNED = defval(B_SIGNED, C_HAS_B_SIGNED, 0); + assign intB_SIGNED = ((C_HAS_B_SIGNED === 0) ? 0 : (((C_HAS_B_SIGNED === 1) && ~((C_B_CONSTANT === 1) && (C_HAS_BYPASS === 0) && (b_max === 0)) ? B_SIGNED : 0))) ; + assign intB = (intBYPASS === 0 ? intBconst : B); + assign intQCE = (C_HAS_CE === 1 ? (C_HAS_BYPASS === 1 ? (C_BYPASS_ENABLE === `c_override ? CE || intBYPASS : CE) : CE) : 1'b1); + + integer j, k; + integer pipe, pipe1; + integer i; + + reg [tmpWidth-1 : 0] tmpA; + reg [tmpWidth-1 : 0] tmpB; + reg [tmpWidth-1 : 0] tmpC; + reg [tmpWidth-1 : 0] tmpBC; + reg [tmpWidth-1 : 0] tmpABC; + reg [tmpWidth-2 : 0] tmpD; + reg [tmpWidth-2 : 0] tmpE; + reg [tmpWidth-2 : 0] tmpF; + + // Registers on outputs by default + C_REG_FD_V6_0 #(C_AINIT_VAL, C_ENABLE_RLOCS, C_HAS_ACLR, C_HAS_AINIT, C_HAS_ASET, + C_HAS_CE, C_HAS_SCLR, C_HAS_SINIT, C_HAS_SSET, + C_SINIT_VAL, C_SYNC_ENABLE, C_SYNC_PRIORITY, output_reg_width) + regq (.D(intQpipeend), .CLK(CLK), .CE(intQCE), .ACLR(ACLR), .ASET(ASET), + .AINIT(AINIT), .SCLR(SCLR), .SSET(SSET), .SINIT(SINIT), + .Q(intQ)); + + C_REG_FD_V6_0 #("0", C_ENABLE_RLOCS, C_HAS_ACLR, C_HAS_AINIT, C_HAS_ASET, + C_HAS_CE, C_HAS_SCLR, C_HAS_SINIT, C_HAS_SSET, + "0", C_SYNC_ENABLE, C_SYNC_PRIORITY, 1) + regcout (.D(intQ_C_OUTpipeend), .CLK(CLK), .CE(intQCE), .ACLR(intACLR_INIT), + .AINIT(AINIT), .ASET(ASET), .SCLR(intSCLR_INIT), .SINIT(SINIT), .SSET(SSET), + .Q(intQ_C_OUT)); + + C_REG_FD_V6_0 #("0", C_ENABLE_RLOCS, C_HAS_ACLR, C_HAS_AINIT, C_HAS_ASET, + C_HAS_CE, C_HAS_SCLR, C_HAS_SINIT, C_HAS_SSET, + "0", C_SYNC_ENABLE, C_SYNC_PRIORITY, 1) + regbout (.D(intQ_B_OUTpipeend), .CLK(CLK), .CE(intQCE), .ACLR(intACLR_INIT), + .AINIT(AINIT), .ASET(ASET), .SCLR(intSCLR_INIT), .SINIT(SINIT), .SSET(SSET), + .Q(intQ_B_OUT)); + + C_REG_FD_V6_0 #("0", C_ENABLE_RLOCS, C_HAS_ACLR, C_HAS_AINIT, C_HAS_ASET, + C_HAS_CE, C_HAS_SCLR, C_HAS_SINIT, C_HAS_SSET, + "0", C_SYNC_ENABLE, C_SYNC_PRIORITY, 1) + regovfl (.D(intQ_OVFLpipeend), .CLK(CLK), .CE(intQCE), .ACLR(intACLR_INIT), + .AINIT(AINIT), .ASET(ASET), .SCLR(intSCLR_INIT), .SINIT(SINIT), .SSET(SSET), + .Q(intQ_OVFL)); + + initial + begin + #1; + for(i = 0; i <= C_LATENCY+2; i = i + 1) + begin + intQpipe[i] = 'bx; + intQ_C_OUTpipe[i] = 1'bx; + intQ_B_OUTpipe[i] = 1'bx; + intQ_OVFLpipe[i] = 1'bx; + end + intQpipeend = `allUKs; + intQ_C_OUTpipeend = 1'bx; + intQ_B_OUTpipeend = 1'bx; + intQ_OVFLpipeend = 1'bx; + intS = `allUKs; + intC_OUT = 1'bx; + intB_OUT = 1'bx; + intOVFL = 1'bx; + end + + always@(A or intB or intADD or intBYPASS or intC_IN or intB_IN or intA_SIGNED or intB_SIGNED) + begin + tmpC = 0; + if(intC_IN !== 1'b0) + begin + if((C_ADD_MODE == `c_add_sub && intADD == 1) || C_ADD_MODE == `c_add) + begin + tmpC = intC_IN; + end + end + else if(intC_IN !== 1'b1 && C_ADD_MODE == `c_add_sub && intADD === 1'b0) + begin + tmpC[0] = ~intC_IN; + end + else if(intB_IN !== 1'b1 && C_ADD_MODE == `c_sub) + begin + tmpC[0] = ~intB_IN; + end + + if(C_A_TYPE == `c_signed || (C_A_TYPE == `c_pin && intA_SIGNED === 1)) + begin + for(j = tmpWidth-1; j >= C_A_WIDTH; j = j - 1) + begin + tmpA[j] = A[C_A_WIDTH-1]; + end + end + else if(C_A_TYPE == `c_unsigned || (C_A_TYPE == `c_pin && intA_SIGNED === 0)) + begin + for(j = tmpWidth-1; j >= C_A_WIDTH; j = j - 1) + begin + tmpA[j] = 0; + end + end + + tmpA[C_A_WIDTH-1 : 0] = A; + + if(C_B_TYPE == `c_signed || (C_B_TYPE == `c_pin && intB_SIGNED === 1)) + begin + for(j = tmpWidth-1; j >= C_B_WIDTH; j = j - 1) + begin + tmpB[j] = intB[C_B_WIDTH-1]; + end + end + else if(C_B_TYPE == `c_unsigned || (C_B_TYPE == `c_pin && intB_SIGNED === 0)) + begin + for(j = tmpWidth-1; j >= C_B_WIDTH; j = j - 1) + begin + tmpB[j] = 0; + end + end + + tmpB[C_B_WIDTH-1 : 0] = intB; + + if(intBYPASS == 1 && intBYPASS_WITH_CIN == 0) + begin + intS <= #1 tmpB[C_HIGH_BIT : C_LOW_BIT]; + if (is_X(tmpB)) + begin + intC_OUT <= #1 1'bx; + intB_OUT <= #1 1'bx; + intOVFL <= #1 1'bx; + end + else + begin + intC_OUT <= #1 1'b0; + intB_OUT <= #1 1'b0; + intOVFL <= #1 1'b0; + end + end + else if(is_X(tmpA) || is_X(tmpB) || is_X(tmpC) || intBYPASS === 1'bx || intADD === 1'bx) + begin + intS <= #1 {C_HIGH_BIT-C_LOW_BIT+1{1'bx}}; + intC_OUT <= #1 1'bx; + intB_OUT <= #1 1'bx; + intOVFL <= #1 1'bx; + end + else if (intBYPASS == 1 && intBYPASS_WITH_CIN == 1) // new section to model the behaviour of the new + begin // c_has_bypass_with_cin mode. This mode is only available + tmpBC = add(tmpB, tmpC); // for Adder variations. + + intS <= #1 tmpBC[C_HIGH_BIT : C_LOW_BIT]; + + if(C_HAS_C_OUT == 1 || C_HAS_Q_C_OUT == 1) + begin + intC_OUT <= #1 tmpBC[tmpWidth-2]; + end + + if(C_HAS_OVFL == 1 || C_HAS_Q_OVFL == 1) + begin + + if(C_HAS_OVFL == 1 || C_HAS_Q_OVFL == 1) + begin + tmpD[tmpWidth-2 : 0] = {tmpWidth - 1{1'b0}}; + tmpE[tmpWidth-3 : 0] = tmpBC[tmpWidth-3 : 0]; + tmpE[tmpWidth-2] = tmpBC[tmpWidth-1]; + tmpF = sm_add(tmpD, tmpE); + intOVFL <= #1 tmpF[tmpWidth-3] ^ tmpBC[tmpWidth-2]; + end + end + end + else + begin + if((C_ADD_MODE == `c_add_sub && intADD == 1) || C_ADD_MODE == `c_add) + begin + tmpBC = add(tmpB, tmpC); + end + else if((C_ADD_MODE == `c_add_sub && intADD == 0) || C_ADD_MODE == `c_sub) + begin + tmpBC = add(tmpB, tmpC); + end + + if((C_ADD_MODE == `c_add_sub && intADD == 1) || C_ADD_MODE == `c_add) + begin + tmpABC = add(tmpA, tmpBC); + end + else if((C_ADD_MODE == `c_add_sub && intADD == 0) || C_ADD_MODE == `c_sub) + begin + tmpABC = sub(tmpA, tmpBC); + end + + intS <= #1 tmpABC[C_HIGH_BIT : C_LOW_BIT]; + + if(C_HAS_C_OUT == 1 || C_HAS_Q_C_OUT == 1) + begin + if((C_ADD_MODE == `c_add_sub && intADD === 1'b1) || C_ADD_MODE == `c_add) + intC_OUT <= #1 tmpABC[tmpWidth-2]; + else if(C_ADD_MODE == `c_add_sub && intADD === 1'b0) + intC_OUT <= #1 ~tmpABC[tmpWidth-2]; + end + + if(C_HAS_B_OUT == 1 || C_HAS_Q_B_OUT == 1) + begin + intB_OUT <= #1 !tmpABC[tmpWidth-2]; + end + + if(C_HAS_OVFL == 1 || C_HAS_Q_OVFL == 1) + begin + tmpD[tmpWidth-3 : 0] = tmpA[tmpWidth-3 : 0]; + if(C_A_TYPE == `c_signed || (C_A_TYPE == `c_pin && intA_SIGNED == 1)) + tmpD[tmpWidth-2] = tmpA[tmpWidth-1]; + else + tmpD[tmpWidth-2] = 1'b0; + tmpE[tmpWidth-3 : 0] = tmpBC[tmpWidth-3 : 0]; + if(C_B_TYPE == `c_signed || (C_B_TYPE == `c_pin && intB_SIGNED == 1)) + tmpE[tmpWidth-2] = tmpBC[tmpWidth-1]; + else + tmpE[tmpWidth-2] = 1'b0; + if((C_ADD_MODE == `c_add_sub && intADD == 1) || C_ADD_MODE == `c_add) + begin + tmpF = sm_add(tmpD, tmpE); + end + else if((C_ADD_MODE == `c_add_sub && intADD == 0) || C_ADD_MODE == `c_sub) + begin + tmpF = sm_sub(tmpD, tmpE); + end + + intOVFL <= #1 tmpF[tmpWidth-3] ^ tmpABC[tmpWidth-2]; + end + end + end + + always@(posedge CLK) + lastADD <= intADD; + + always@(posedge CLK ) + begin + if ((intACLR === 1'b1 || intSCLR === 1'b1) && C_ADD_MODE === `c_add) + begin + for (pipe = 2; pipe <= C_LATENCY+2; pipe = pipe + 1) + begin + intQpipe[pipe] <= 1'b0; + intQ_C_OUTpipe[pipe] <= 1'b0; + intQ_B_OUTpipe[pipe] <= 1'b0; + intQ_OVFLpipe[pipe] <= 1'b0; + end + end + else if(CLK === 1'b1 && lastCLK === 1'b0 && intQCE === 1'b1) // OK! Update pipelines! + begin + for(pipe = 2; pipe <= C_LATENCY-1; pipe = pipe + 1) + begin + intQpipe[pipe] <= intQpipe[pipe+1]; + intQ_C_OUTpipe[pipe] <= intQ_C_OUTpipe[pipe+1]; + intQ_B_OUTpipe[pipe] <= intQ_B_OUTpipe[pipe+1]; + intQ_OVFLpipe[pipe] <= intQ_OVFLpipe[pipe+1]; + end + + intQpipe[C_LATENCY] <= intS; + intQ_C_OUTpipe[C_LATENCY] <= intC_OUT; + intQ_B_OUTpipe[C_LATENCY] <= intB_OUT; + intQ_OVFLpipe[C_LATENCY] <= intOVFL; + end + else if((CLK === 1'bx && lastCLK === 1'b0) || (CLK === 1'b1 && lastCLK === 1'bx) || intQCE === 1'bx) // POSSIBLY Update pipelines! + begin + for(pipe = 2; pipe <= C_LATENCY-1; pipe = pipe + 1) + begin + if(intQ_C_OUTpipe[pipe] !== intQ_C_OUTpipe[pipe+1]) + intQ_C_OUTpipe[pipe] <= 1'bx; + if(intQ_B_OUTpipe[pipe] !== intQ_B_OUTpipe[pipe+1]) + intQ_B_OUTpipe[pipe] <= 1'bx; + if(intQ_OVFLpipe[pipe] !== intQ_OVFLpipe[pipe+1]) + intQ_OVFLpipe[pipe] <= 1'bx; + tmp_pipe1 = intQpipe[pipe]; + tmp_pipe2 = intQpipe[pipe+1]; + for(pipe1 = C_LOW_BIT; pipe1 < C_HIGH_BIT+1; pipe1 = pipe1 + 1) + begin + if(tmp_pipe1[pipe1] !== tmp_pipe2[pipe1]) + tmp_pipe1[pipe1] = 1'bx; + end + intQpipe[pipe] <= tmp_pipe1; + end + if(intQ_C_OUTpipe[C_LATENCY] !== intC_OUT) + intQ_C_OUTpipe[C_LATENCY] <= 1'bx; + if(intQ_B_OUTpipe[C_LATENCY] !== intB_OUT) + intQ_B_OUTpipe[C_LATENCY] <= 1'bx; + if(intQ_OVFLpipe[C_LATENCY] !== intOVFL) + intQ_OVFLpipe[C_LATENCY] <= 1'bx; + for(pipe1 = C_LOW_BIT; pipe1 < C_HIGH_BIT+1; pipe1 = pipe1 + 1) + begin + if(tmp_pipe1[pipe1] !== intS[pipe1]) + tmp_pipe1[pipe1] = 1'bx; + end + intQpipe[C_LATENCY] <= tmp_pipe1; + end + end + + always@(intS or intQpipe[2] or intADD or lastADD) + begin + if(C_LATENCY < 2) // No pipeline + intQpipeend <= intS; + else if (lastADD === intADD) + // Pipeline stages required + intQpipeend <= intQpipe[2]; + end + + always@(intC_OUT or intQ_C_OUTpipe[2] or intADD or lastADD) + begin + if(C_LATENCY < 2) // No pipeline + intQ_C_OUTpipeend <= intC_OUT; + else if (lastADD === intADD) + // Pipeline stages required + intQ_C_OUTpipeend <= intQ_C_OUTpipe[2]; + end + + always@(intB_OUT or intQ_B_OUTpipe[2] or intADD or lastADD) + begin + if(C_LATENCY < 2) // No pipeline + intQ_B_OUTpipeend <= intB_OUT; + else if (lastADD === intADD) + // Pipeline stages required + intQ_B_OUTpipeend <= intQ_B_OUTpipe[2]; + end + + always@(intOVFL or intQ_OVFLpipe[2] or intADD or lastADD) + begin + if(C_LATENCY < 2) // No pipeline + intQ_OVFLpipeend <= intOVFL; + else if (lastADD === intADD) + // Pipeline stages required + intQ_OVFLpipeend <= intQ_OVFLpipe[2]; + end + + + always@(CLK) + lastCLK <= CLK; + + + +/* helper functions */ + + function defval; + input i; + input hassig; + input val; + begin + if(hassig == 1) + defval = i; + else + defval = val; + end + endfunction + + function [C_B_WIDTH - 1 : 0] to_bitsB; + input [C_B_WIDTH*8 : 1] instring; + integer i; + integer non_null_string; + begin + non_null_string = 0; + for(i = C_B_WIDTH; i > 0; i = i - 1) + begin // Is the string empty? + if(instring[(i*8)] == 0 && + instring[(i*8)-1] == 0 && + instring[(i*8)-2] == 0 && + instring[(i*8)-3] == 0 && + instring[(i*8)-4] == 0 && + instring[(i*8)-5] == 0 && + instring[(i*8)-6] == 0 && + instring[(i*8)-7] == 0 && + non_null_string == 0) + non_null_string = 0; // Use the return value to flag a non-empty string + else + non_null_string = 1; // Non-null character! + end + if(non_null_string == 0) // String IS empty! Just return the value to be all '0's + begin + for(i = C_B_WIDTH; i > 0; i = i - 1) + to_bitsB[i-1] = 0; + end + else + begin + for(i = C_B_WIDTH; i > 0; i = i - 1) + begin // Is this character a '0'? (ASCII = 48 = 00110000) + if(instring[(i*8)] == 0 && + instring[(i*8)-1] == 0 && + instring[(i*8)-2] == 1 && + instring[(i*8)-3] == 1 && + instring[(i*8)-4] == 0 && + instring[(i*8)-5] == 0 && + instring[(i*8)-6] == 0 && + instring[(i*8)-7] == 0) + to_bitsB[i-1] = 0; + // Or is it a '1'? + else if(instring[(i*8)] == 0 && + instring[(i*8)-1] == 0 && + instring[(i*8)-2] == 1 && + instring[(i*8)-3] == 1 && + instring[(i*8)-4] == 0 && + instring[(i*8)-5] == 0 && + instring[(i*8)-6] == 0 && + instring[(i*8)-7] == 1) + to_bitsB[i-1] = 1; + // Or is it a ' '? (a null char - in which case insert a '0') + else if(instring[(i*8)] == 0 && + instring[(i*8)-1] == 0 && + instring[(i*8)-2] == 0 && + instring[(i*8)-3] == 0 && + instring[(i*8)-4] == 0 && + instring[(i*8)-5] == 0 && + instring[(i*8)-6] == 0 && + instring[(i*8)-7] == 0) + to_bitsB[i-1] = 0; + else + begin + $display("Error in %m at time %d ns: non-binary digit in string \"%s\"\nExiting simulation...",$time, instring); + $finish; + end + end + end + end + endfunction + + function max_bval; + input [C_B_WIDTH*8 : 1] instring; + integer i; + integer last_val; + integer non_null_string; + begin + non_null_string = 1; + for(i = 0; i < C_B_WIDTH; i = i + 1) + begin // Is the string empty? + + // if(instring[(i*8)] == 0 && + // instring[(i*8)-1] == 0 && + // instring[(i*8)-2] == 0 && + // instring[(i*8)-3] == 0 && + // instring[(i*8)-4] == 0 && + // instring[(i*8)-5] == 0 && + // instring[(i*8)-6] == 0 && + // instring[(i*8)-7] == 0 && + // non_null_string == 1) + // non_null_string = 0; + + // is string a '0' + // else if(instring[(i*8)] == 0 && + if(instring[(i*8)] == 0 && + instring[(i*8)-1] == 0 && + instring[(i*8)-2] == 1 && + instring[(i*8)-3] == 1 && + instring[(i*8)-4] == 0 && + instring[(i*8)-5] == 0 && + instring[(i*8)-6] == 0 && + instring[(i*8)-7] == 0 && + non_null_string == 1) +// non_null_string = 1; + last_val = 0; + // Or is it a '1'? + else if(instring[(i*8)] == 0 && + instring[(i*8)-1] == 0 && + instring[(i*8)-2] == 1 && + instring[(i*8)-3] == 1 && + instring[(i*8)-4] == 0 && + instring[(i*8)-5] == 0 && + instring[(i*8)-6] == 0 && + instring[(i*8)-7] == 1 && + non_null_string == 1) + + // non_null_string = 1; + last_val = 1; + else + non_null_string = 0; + end + + max_bval = last_val; + end + endfunction + + function max; + input a; + input b; + begin + max = (a > b) ? a : b; + end + endfunction + + function is_X; + input [tmpWidth-1 : 0] i; + begin + is_X = 1'b0; + for(j = 0; j < tmpWidth; j = j + 1) + begin + if(i[j] === 1'bx) + is_X = 1'b1; + end // loop + end + endfunction + + function [tmpWidth-1 : 0] add; + input [tmpWidth-1 : 0] i1; + input [tmpWidth-1 : 0] i2; + integer bit_index; + integer carryin, carryout; + begin + carryin = 0; + carryout = 0; + for(bit_index=0; bit_index < tmpWidth; bit_index = bit_index + 1) + begin + add[bit_index] = i1[bit_index] ^ i2[bit_index] ^ carryin; + carryout = (i1[bit_index] && i2[bit_index]) || (carryin && (i1[bit_index] || i2[bit_index])); + carryin = carryout; + end + end + endfunction + + function [tmpWidth-1 : 0] sub; + input [tmpWidth-1 : 0] i1; + input [tmpWidth-1 : 0] i2; + begin + i2 = add(~i2, 1); + sub = add(i1, i2); + end + endfunction + + function [tmpWidth-2 : 0] sm_add; + input [tmpWidth-2 : 0] i1; + input [tmpWidth-2 : 0] i2; + integer bit_index; + integer carryin, carryout; + begin + carryin = 0; + carryout = 0; + for(bit_index=0; bit_index < tmpWidth-1; bit_index = bit_index + 1) + begin + sm_add[bit_index] = i1[bit_index] ^ i2[bit_index] ^ carryin; + carryout = (i1[bit_index] && i2[bit_index]) || (carryin && (i1[bit_index] || i2[bit_index])); + carryin = carryout; + end + end + endfunction + + function [tmpWidth-2 : 0] sm_sub; + input [tmpWidth-2 : 0] i1; + input [tmpWidth-2 : 0] i2; + begin + i2 = sm_add(~i2, 1); + sm_sub = sm_add(i1, i2); + end + endfunction + +endmodule + +`undef c_set +`undef c_clear +`undef c_override +`undef c_no_override +`undef c_add +`undef c_sub +`undef c_add_sub +`undef c_signed +`undef c_unsigned +`undef c_pin +`undef allUKs diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/C_ADDSUB_V7_0.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/C_ADDSUB_V7_0.v new file mode 100644 index 0000000..1b14911 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/C_ADDSUB_V7_0.v @@ -0,0 +1,772 @@ +// Copyright(C) 2003 by Xilinx, Inc. All rights reserved. +// This text/file contains proprietary, confidential +// information of Xilinx, Inc., is distributed under license +// from Xilinx, Inc., and may be used, copied and/or +// disclosed only pursuant to the terms of a valid license +// agreement with Xilinx, Inc. Xilinx hereby grants you +// a license to use this text/file solely for design, simulation, +// implementation and creation of design files limited +// to Xilinx devices or technologies. Use with non-Xilinx +// devices or technologies is expressly prohibited and +// immediately terminates your license unless covered by +// a separate agreement. +// +// Xilinx is providing this design, code, or information +// "as is" solely for use in developing programs and +// solutions for Xilinx devices. By providing this design, +// code, or information as one possible implementation of +// this feature, application or standard, Xilinx is making no +// representation that this implementation is free from any +// claims of infringement. You are responsible for +// obtaining any rights you may require for your implementation. +// Xilinx expressly disclaims any warranty whatsoever with +// respect to the adequacy of the implementation, including +// but not limited to any warranties or representations that this +// implementation is free from claims of infringement, implied +// warranties of merchantability or fitness for a particular +// purpose. +// +// Xilinx products are not intended for use in life support +// appliances, devices, or systems. Use in such applications are +// expressly prohibited. +// +// This copyright and support notice must be retained as part +// of this text at all times. (c) Copyright 1995-2003 Xilinx, Inc. +// All rights reserved. + + + + +/* $Id: C_ADDSUB_V7_0.v,v 1.13 2008/09/08 20:06:13 akennedy Exp $ +-- +-- Filename - C_ADDSUB_V7_0.v +-- Author - Xilinx +-- Creation - 22 Mar 1999 +-- +-- Description - This file contains the Verilog behavior for the Baseblocks C_ADDSUB_V7_0 module +*/ + +`timescale 1ns/10ps + +`define c_set 0 +`define c_clear 1 +`define c_override 0 +`define c_no_override 1 +`define c_add 0 +`define c_sub 1 +`define c_add_sub 2 +`define c_signed 0 +`define c_unsigned 1 +`define c_pin 2 +`define allUKs {(C_HIGH_BIT-C_LOW_BIT)+1{1'bx}} + +module C_ADDSUB_V7_0 (A, B, CLK, ADD, C_IN, B_IN, CE, BYPASS, ACLR, ASET, AINIT, + SCLR, SSET, SINIT, A_SIGNED, B_SIGNED, OVFL, C_OUT, B_OUT, + Q_OVFL, Q_C_OUT, Q_B_OUT, S, Q); + + parameter C_ADD_MODE = `c_add; + parameter C_AINIT_VAL = "0"; + parameter C_A_TYPE = `c_unsigned; + parameter C_A_WIDTH = 16; + parameter C_BYPASS_ENABLE = `c_override; + parameter C_BYPASS_LOW = 0; + parameter C_B_CONSTANT = 0; + parameter C_B_TYPE = `c_unsigned; + parameter C_B_VALUE = "0000000000000000"; + parameter C_B_WIDTH = 16; + parameter C_ENABLE_RLOCS = 1; + parameter C_HAS_ACLR = 0; + parameter C_HAS_ADD = 0; + parameter C_HAS_AINIT = 0; + parameter C_HAS_ASET = 0; + parameter C_HAS_A_SIGNED = 0; + parameter C_HAS_BYPASS = 0; + parameter C_HAS_BYPASS_WITH_CIN = 0; + parameter C_HAS_B_IN = 1; + parameter C_HAS_B_OUT = 0; + parameter C_HAS_B_SIGNED = 0; + parameter C_HAS_CE = 0; + parameter C_HAS_C_IN = 1; + parameter C_HAS_C_OUT = 0; + parameter C_HAS_OVFL = 0; + parameter C_HAS_Q = 1; + parameter C_HAS_Q_B_OUT = 0; + parameter C_HAS_Q_C_OUT = 0; + parameter C_HAS_Q_OVFL = 0; + parameter C_HAS_S = 0; + parameter C_HAS_SCLR = 0; + parameter C_HAS_SINIT = 0; + parameter C_HAS_SSET = 0; + parameter C_HIGH_BIT = 15; + parameter C_LATENCY = 1; + parameter C_LOW_BIT = 0; + parameter C_OUT_WIDTH = 16; + parameter C_PIPE_STAGES = 1; + parameter C_SINIT_VAL = "0"; + parameter C_SYNC_ENABLE = `c_override; + parameter C_SYNC_PRIORITY = `c_clear; + + + // internal parameters (not to be set from instanciation) + parameter tmpWidth = (C_A_WIDTH > C_B_WIDTH) ? C_A_WIDTH + 2 : C_B_WIDTH + 2; + parameter output_reg_width = C_HIGH_BIT-C_LOW_BIT+1; + + input [C_A_WIDTH-1 : 0] A; + input [C_B_WIDTH-1 : 0] B; + input CLK; + input ADD; + input C_IN; + input B_IN; + input CE; + input BYPASS; + input ACLR; + input ASET; + input AINIT; + input SCLR; + input SSET; + input SINIT; + input A_SIGNED; + input B_SIGNED; + output OVFL; + output C_OUT; + output B_OUT; + output Q_OVFL; + output Q_C_OUT; + output Q_B_OUT; + output [C_HIGH_BIT : C_LOW_BIT] S; + output [C_HIGH_BIT : C_LOW_BIT] Q; + + + + // Internal values to drive signals when input is missing + wire [C_B_WIDTH-1 : 0] intBconst; + wire [C_B_WIDTH-1 : 0] intB; + wire intADD; + wire intBYPASS; + wire intC_IN; + wire intB_IN; + wire intCE; + wire intQCE; + wire intA_SIGNED; + wire intB_SIGNED; + reg intC_OUT; + reg intB_OUT; + reg intOVFL; + wire intQ_C_OUT; + wire intQ_B_OUT; + wire intQ_OVFL; + reg [C_HIGH_BIT : C_LOW_BIT ] intS; + wire [C_HIGH_BIT : C_LOW_BIT ] intQ; + wire intACLR; + wire intASET; + wire intAINIT; + wire intSCLR; + wire intSSET; + wire intSINIT; + wire intACLR_INIT; + wire intSCLR_INIT; + wire intBYPASS_WITH_CIN; // New signal for bypass with Cin mode + reg lastCLK; + reg lastADD; + wire [8 : 1] b_max; + reg [C_HIGH_BIT : C_LOW_BIT] intQpipe [C_LATENCY+2 : 0]; + reg [C_LATENCY+2 : 0] intQ_C_OUTpipe; + reg [C_LATENCY+2 : 0] intQ_B_OUTpipe; + reg [C_LATENCY+2 : 0] intQ_OVFLpipe; + reg [C_LATENCY-1 : 0] intADDpipe; + + reg [C_HIGH_BIT : C_LOW_BIT] intQpipeend; + reg intQ_C_OUTpipeend; + reg intQ_B_OUTpipeend; + reg intQ_OVFLpipeend; + reg [C_HIGH_BIT : C_LOW_BIT] tmp_pipe1; + reg [C_HIGH_BIT : C_LOW_BIT] tmp_pipe2; + + + wire [C_HIGH_BIT : C_LOW_BIT] Q = (C_HAS_Q == 1 ? intQ : `allUKs); + wire Q_C_OUT = (C_HAS_Q_C_OUT == 1 ? intQ_C_OUT : 1'bx); + wire Q_B_OUT = (C_HAS_Q_B_OUT == 1 ? intQ_B_OUT : 1'bx); + wire Q_OVFL = (C_HAS_Q_OVFL == 1 ? intQ_OVFL : 1'bx); + wire [C_HIGH_BIT : C_LOW_BIT] S = (C_HAS_S == 1 ? intS : `allUKs); + wire C_OUT = (C_HAS_C_OUT == 1 ? intC_OUT : 1'bx); + wire B_OUT = (C_HAS_B_OUT == 1 ? intB_OUT : 1'bx); + wire OVFL = (C_HAS_OVFL == 1 ? intOVFL : 1'bx); + + // Sort out default values for missing ports + + assign b_max = max_bval(C_B_VALUE); + assign intCE = defval(CE, C_HAS_CE, 1); + assign intACLR = defval(ACLR, C_HAS_ACLR, 0); + assign intASET = defval(ASET, C_HAS_ASET, 0); + assign intAINIT = defval(AINIT, C_HAS_AINIT, 0); + assign intSCLR = defval(SCLR, C_HAS_SCLR, 0); + assign intSSET = defval(SSET, C_HAS_SSET, 0); + assign intSINIT = defval(SINIT, C_HAS_SINIT, 0); + assign intACLR_INIT = (intACLR || intAINIT); + assign intSCLR_INIT = (intSCLR || intSINIT); + + assign intBconst = (C_B_CONSTANT === 1) ? to_bitsB(C_B_VALUE) : B; +// assign intADD = (C_HAS_ADD === 1) ? ((C_LATENCY < 2) ? ADD : intADDpipe[C_LATENCY-1]) : ((C_ADD_MODE === `c_add) ? 1 : ((C_ADD_MODE === `c_sub) ? 0 : 3)); // 3 is an illegal value since this is an illegal option! + assign intADD = (C_HAS_ADD === 1) ? ADD : (C_ADD_MODE === `c_add) ? 1 : ((C_ADD_MODE === `c_sub) ? 0 : 3); // 3 is an illegal value since this is an illegal option! + assign intBYPASS = (C_HAS_BYPASS === 1) ? ((C_BYPASS_LOW === 1) ? !BYPASS : BYPASS) : 0; + assign intBYPASS_WITH_CIN = C_HAS_BYPASS_WITH_CIN; // new parameter to allow the bypass mode to take account of the c_in + assign intC_IN = ((C_HAS_C_IN === 1) ? C_IN : ((C_HAS_ADD === 1) ? ~intADD : 0)); + assign intB_IN = defval(B_IN, C_HAS_B_IN, 1); + assign intA_SIGNED = defval(A_SIGNED, C_HAS_A_SIGNED, 0); + //assign intB_SIGNED = defval(B_SIGNED, C_HAS_B_SIGNED, 0); + assign intB_SIGNED = ((C_HAS_B_SIGNED === 0) ? 0 : (((C_HAS_B_SIGNED === 1) && ~((C_B_CONSTANT === 1) && (C_HAS_BYPASS === 0) && (b_max === 0)) ? B_SIGNED : 0))) ; + assign intB = (intBYPASS === 0 ? intBconst : B); + assign intQCE = (C_HAS_CE === 1 ? (C_HAS_BYPASS === 1 ? (C_BYPASS_ENABLE === `c_override ? CE || intBYPASS : CE) : CE) : 1'b1); + + integer j, k; + integer pipe, pipe1; + integer i; + + reg [tmpWidth-1 : 0] tmpA; + reg [tmpWidth-1 : 0] tmpB; + reg [tmpWidth-1 : 0] tmpC; + reg [tmpWidth-1 : 0] tmpBC; + reg [tmpWidth-1 : 0] tmpABC; + reg [tmpWidth-2 : 0] tmpD; + reg [tmpWidth-2 : 0] tmpE; + reg [tmpWidth-2 : 0] tmpF; + + // Registers on outputs by default + C_REG_FD_V7_0 #(C_AINIT_VAL, C_ENABLE_RLOCS, C_HAS_ACLR, C_HAS_AINIT, C_HAS_ASET, + C_HAS_CE, C_HAS_SCLR, C_HAS_SINIT, C_HAS_SSET, + C_SINIT_VAL, C_SYNC_ENABLE, C_SYNC_PRIORITY, output_reg_width) + regq (.D(intQpipeend), .CLK(CLK), .CE(intQCE), .ACLR(ACLR), .ASET(ASET), + .AINIT(AINIT), .SCLR(SCLR), .SSET(SSET), .SINIT(SINIT), + .Q(intQ)); + + C_REG_FD_V7_0 #("0", C_ENABLE_RLOCS, C_HAS_ACLR, C_HAS_AINIT, C_HAS_ASET, + C_HAS_CE, C_HAS_SCLR, C_HAS_SINIT, C_HAS_SSET, + "0", C_SYNC_ENABLE, C_SYNC_PRIORITY, 1) + regcout (.D(intQ_C_OUTpipeend), .CLK(CLK), .CE(intQCE), .ACLR(intACLR_INIT), + .AINIT(AINIT), .ASET(ASET), .SCLR(intSCLR_INIT), .SINIT(SINIT), .SSET(SSET), + .Q(intQ_C_OUT)); + + C_REG_FD_V7_0 #("0", C_ENABLE_RLOCS, C_HAS_ACLR, C_HAS_AINIT, C_HAS_ASET, + C_HAS_CE, C_HAS_SCLR, C_HAS_SINIT, C_HAS_SSET, + "0", C_SYNC_ENABLE, C_SYNC_PRIORITY, 1) + regbout (.D(intQ_B_OUTpipeend), .CLK(CLK), .CE(intQCE), .ACLR(intACLR_INIT), + .AINIT(AINIT), .ASET(ASET), .SCLR(intSCLR_INIT), .SINIT(SINIT), .SSET(SSET), + .Q(intQ_B_OUT)); + + C_REG_FD_V7_0 #("0", C_ENABLE_RLOCS, C_HAS_ACLR, C_HAS_AINIT, C_HAS_ASET, + C_HAS_CE, C_HAS_SCLR, C_HAS_SINIT, C_HAS_SSET, + "0", C_SYNC_ENABLE, C_SYNC_PRIORITY, 1) + regovfl (.D(intQ_OVFLpipeend), .CLK(CLK), .CE(intQCE), .ACLR(intACLR_INIT), + .AINIT(AINIT), .ASET(ASET), .SCLR(intSCLR_INIT), .SINIT(SINIT), .SSET(SSET), + .Q(intQ_OVFL)); + + initial + begin + #1; + for(i = 0; i <= C_LATENCY+2; i = i + 1) + begin + intQpipe[i] = 'bx; + intQ_C_OUTpipe[i] = 1'bx; + intQ_B_OUTpipe[i] = 1'bx; + intQ_OVFLpipe[i] = 1'bx; + end + intQpipeend = `allUKs; + intQ_C_OUTpipeend = 1'bx; + intQ_B_OUTpipeend = 1'bx; + intQ_OVFLpipeend = 1'bx; + intS = `allUKs; + intC_OUT = 1'bx; + intB_OUT = 1'bx; + intOVFL = 1'bx; + end + + always@(A or intB or intADD or intBYPASS or intC_IN or intB_IN or intA_SIGNED or intB_SIGNED) + begin + tmpC = 0; + if(intC_IN !== 1'b0) + begin + if((C_ADD_MODE == `c_add_sub && intADD == 1) || C_ADD_MODE == `c_add) + begin + tmpC = intC_IN; + end + end + else if(intC_IN !== 1'b1 && C_ADD_MODE == `c_add_sub && intADD === 1'b0) + begin + tmpC[0] = ~intC_IN; + end + else if(intB_IN !== 1'b1 && C_ADD_MODE == `c_sub) + begin + tmpC[0] = ~intB_IN; + end + + if(C_A_TYPE == `c_signed || (C_A_TYPE == `c_pin && intA_SIGNED === 1)) + begin + for(j = tmpWidth-1; j >= C_A_WIDTH; j = j - 1) + begin + tmpA[j] = A[C_A_WIDTH-1]; + end + end + else if(C_A_TYPE == `c_unsigned || (C_A_TYPE == `c_pin && intA_SIGNED === 0)) + begin + for(j = tmpWidth-1; j >= C_A_WIDTH; j = j - 1) + begin + tmpA[j] = 0; + end + end + + tmpA[C_A_WIDTH-1 : 0] = A; + + if(C_B_TYPE == `c_signed || (C_B_TYPE == `c_pin && intB_SIGNED === 1)) + begin + for(j = tmpWidth-1; j >= C_B_WIDTH; j = j - 1) + begin + tmpB[j] = intB[C_B_WIDTH-1]; + end + end + else if(C_B_TYPE == `c_unsigned || (C_B_TYPE == `c_pin && intB_SIGNED === 0)) + begin + for(j = tmpWidth-1; j >= C_B_WIDTH; j = j - 1) + begin + tmpB[j] = 0; + end + end + + tmpB[C_B_WIDTH-1 : 0] = intB; + + if(intBYPASS == 1 && intBYPASS_WITH_CIN == 0) + begin + intS <= #1 tmpB[C_HIGH_BIT : C_LOW_BIT]; + if (is_X(tmpB)) + begin + intC_OUT <= #1 1'bx; + intB_OUT <= #1 1'bx; + intOVFL <= #1 1'bx; + end + else + begin + intC_OUT <= #1 1'b0; + intB_OUT <= #1 1'b0; + intOVFL <= #1 1'b0; + end + end + else if(is_X(tmpA) || is_X(tmpB) || is_X(tmpC) || intBYPASS === 1'bx || intADD === 1'bx) + begin + intS <= #1 {C_HIGH_BIT-C_LOW_BIT+1{1'bx}}; + intC_OUT <= #1 1'bx; + intB_OUT <= #1 1'bx; + intOVFL <= #1 1'bx; + end + else if (intBYPASS == 1 && intBYPASS_WITH_CIN == 1) // new section to model the behaviour of the new + begin // c_has_bypass_with_cin mode. This mode is only available + tmpBC = add(tmpB, tmpC); // for Adder variations. + + intS <= #1 tmpBC[C_HIGH_BIT : C_LOW_BIT]; + + if(C_HAS_C_OUT == 1 || C_HAS_Q_C_OUT == 1) + begin + intC_OUT <= #1 tmpBC[tmpWidth-2]; + end + + if(C_HAS_OVFL == 1 || C_HAS_Q_OVFL == 1) + begin + + if(C_HAS_OVFL == 1 || C_HAS_Q_OVFL == 1) + begin + tmpD[tmpWidth-2 : 0] = {tmpWidth - 1{1'b0}}; + tmpE[tmpWidth-3 : 0] = tmpBC[tmpWidth-3 : 0]; + tmpE[tmpWidth-2] = tmpBC[tmpWidth-1]; + tmpF = sm_add(tmpD, tmpE); + intOVFL <= #1 tmpF[tmpWidth-3] ^ tmpBC[tmpWidth-2]; + end + end + end + else + begin + if((C_ADD_MODE == `c_add_sub && intADD == 1) || C_ADD_MODE == `c_add) + begin + tmpBC = add(tmpB, tmpC); + end + else if((C_ADD_MODE == `c_add_sub && intADD == 0) || C_ADD_MODE == `c_sub) + begin + tmpBC = add(tmpB, tmpC); + end + + if((C_ADD_MODE == `c_add_sub && intADD == 1) || C_ADD_MODE == `c_add) + begin + tmpABC = add(tmpA, tmpBC); + end + else if((C_ADD_MODE == `c_add_sub && intADD == 0) || C_ADD_MODE == `c_sub) + begin + tmpABC = sub(tmpA, tmpBC); + end + + intS <= #1 tmpABC[C_HIGH_BIT : C_LOW_BIT]; + + if(C_HAS_C_OUT == 1 || C_HAS_Q_C_OUT == 1) + begin + if((C_ADD_MODE == `c_add_sub && intADD === 1'b1) || C_ADD_MODE == `c_add) + intC_OUT <= #1 tmpABC[tmpWidth-2]; + else if(C_ADD_MODE == `c_add_sub && intADD === 1'b0) + intC_OUT <= #1 ~tmpABC[tmpWidth-2]; + end + + if(C_HAS_B_OUT == 1 || C_HAS_Q_B_OUT == 1) + begin + intB_OUT <= #1 !tmpABC[tmpWidth-2]; + end + + if(C_HAS_OVFL == 1 || C_HAS_Q_OVFL == 1) + begin + tmpD[tmpWidth-3 : 0] = tmpA[tmpWidth-3 : 0]; + if(C_A_TYPE == `c_signed || (C_A_TYPE == `c_pin && intA_SIGNED == 1)) + tmpD[tmpWidth-2] = tmpA[tmpWidth-1]; + else + tmpD[tmpWidth-2] = 1'b0; + tmpE[tmpWidth-3 : 0] = tmpBC[tmpWidth-3 : 0]; + if(C_B_TYPE == `c_signed || (C_B_TYPE == `c_pin && intB_SIGNED == 1)) + tmpE[tmpWidth-2] = tmpBC[tmpWidth-1]; + else + tmpE[tmpWidth-2] = 1'b0; + if((C_ADD_MODE == `c_add_sub && intADD == 1) || C_ADD_MODE == `c_add) + begin + tmpF = sm_add(tmpD, tmpE); + end + else if((C_ADD_MODE == `c_add_sub && intADD == 0) || C_ADD_MODE == `c_sub) + begin + tmpF = sm_sub(tmpD, tmpE); + end + + intOVFL <= #1 tmpF[tmpWidth-3] ^ tmpABC[tmpWidth-2]; + end + end + end + + always@(posedge CLK) + lastADD <= intADD; + + always@(posedge CLK ) + begin + if ((intACLR === 1'b1 || intSCLR === 1'b1) && C_ADD_MODE === `c_add) + begin + for (pipe = 2; pipe <= C_LATENCY+2; pipe = pipe + 1) + begin + intQpipe[pipe] <= 1'b0; + intQ_C_OUTpipe[pipe] <= 1'b0; + intQ_B_OUTpipe[pipe] <= 1'b0; + intQ_OVFLpipe[pipe] <= 1'b0; + end + end + else if(CLK === 1'b1 && lastCLK === 1'b0 && intQCE === 1'b1) // OK! Update pipelines! + begin + for(pipe = 2; pipe <= C_LATENCY-1; pipe = pipe + 1) + begin + intQpipe[pipe] <= intQpipe[pipe+1]; + intQ_C_OUTpipe[pipe] <= intQ_C_OUTpipe[pipe+1]; + intQ_B_OUTpipe[pipe] <= intQ_B_OUTpipe[pipe+1]; + intQ_OVFLpipe[pipe] <= intQ_OVFLpipe[pipe+1]; + end + + intQpipe[C_LATENCY] <= intS; + intQ_C_OUTpipe[C_LATENCY] <= intC_OUT; + intQ_B_OUTpipe[C_LATENCY] <= intB_OUT; + intQ_OVFLpipe[C_LATENCY] <= intOVFL; + end + else if((CLK === 1'bx && lastCLK === 1'b0) || (CLK === 1'b1 && lastCLK === 1'bx) || intQCE === 1'bx) // POSSIBLY Update pipelines! + begin + for(pipe = 2; pipe <= C_LATENCY-1; pipe = pipe + 1) + begin + if(intQ_C_OUTpipe[pipe] !== intQ_C_OUTpipe[pipe+1]) + intQ_C_OUTpipe[pipe] <= 1'bx; + if(intQ_B_OUTpipe[pipe] !== intQ_B_OUTpipe[pipe+1]) + intQ_B_OUTpipe[pipe] <= 1'bx; + if(intQ_OVFLpipe[pipe] !== intQ_OVFLpipe[pipe+1]) + intQ_OVFLpipe[pipe] <= 1'bx; + tmp_pipe1 = intQpipe[pipe]; + tmp_pipe2 = intQpipe[pipe+1]; + for(pipe1 = C_LOW_BIT; pipe1 < C_HIGH_BIT+1; pipe1 = pipe1 + 1) + begin + if(tmp_pipe1[pipe1] !== tmp_pipe2[pipe1]) + tmp_pipe1[pipe1] = 1'bx; + end + intQpipe[pipe] <= tmp_pipe1; + end + if(intQ_C_OUTpipe[C_LATENCY] !== intC_OUT) + intQ_C_OUTpipe[C_LATENCY] <= 1'bx; + if(intQ_B_OUTpipe[C_LATENCY] !== intB_OUT) + intQ_B_OUTpipe[C_LATENCY] <= 1'bx; + if(intQ_OVFLpipe[C_LATENCY] !== intOVFL) + intQ_OVFLpipe[C_LATENCY] <= 1'bx; + for(pipe1 = C_LOW_BIT; pipe1 < C_HIGH_BIT+1; pipe1 = pipe1 + 1) + begin + if(tmp_pipe1[pipe1] !== intS[pipe1]) + tmp_pipe1[pipe1] = 1'bx; + end + intQpipe[C_LATENCY] <= tmp_pipe1; + end + end + + always@(intS or intQpipe[2] or intADD or lastADD) + begin + if(C_LATENCY < 2) // No pipeline + intQpipeend <= intS; + else if (lastADD === intADD) + // Pipeline stages required + intQpipeend <= intQpipe[2]; + end + + always@(intC_OUT or intQ_C_OUTpipe[2] or intADD or lastADD) + begin + if(C_LATENCY < 2) // No pipeline + intQ_C_OUTpipeend <= intC_OUT; + else if (lastADD === intADD) + // Pipeline stages required + intQ_C_OUTpipeend <= intQ_C_OUTpipe[2]; + end + + always@(intB_OUT or intQ_B_OUTpipe[2] or intADD or lastADD) + begin + if(C_LATENCY < 2) // No pipeline + intQ_B_OUTpipeend <= intB_OUT; + else if (lastADD === intADD) + // Pipeline stages required + intQ_B_OUTpipeend <= intQ_B_OUTpipe[2]; + end + + always@(intOVFL or intQ_OVFLpipe[2] or intADD or lastADD) + begin + if(C_LATENCY < 2) // No pipeline + intQ_OVFLpipeend <= intOVFL; + else if (lastADD === intADD) + // Pipeline stages required + intQ_OVFLpipeend <= intQ_OVFLpipe[2]; + end + + + always@(CLK) + lastCLK <= CLK; + + + +/* helper functions */ + + function defval; + input i; + input hassig; + input val; + begin + if(hassig == 1) + defval = i; + else + defval = val; + end + endfunction + + function [C_B_WIDTH - 1 : 0] to_bitsB; + input [C_B_WIDTH*8 : 1] instring; + integer i; + integer non_null_string; + begin + non_null_string = 0; + for(i = C_B_WIDTH; i > 0; i = i - 1) + begin // Is the string empty? + if(instring[(i*8)] == 0 && + instring[(i*8)-1] == 0 && + instring[(i*8)-2] == 0 && + instring[(i*8)-3] == 0 && + instring[(i*8)-4] == 0 && + instring[(i*8)-5] == 0 && + instring[(i*8)-6] == 0 && + instring[(i*8)-7] == 0 && + non_null_string == 0) + non_null_string = 0; // Use the return value to flag a non-empty string + else + non_null_string = 1; // Non-null character! + end + if(non_null_string == 0) // String IS empty! Just return the value to be all '0's + begin + for(i = C_B_WIDTH; i > 0; i = i - 1) + to_bitsB[i-1] = 0; + end + else + begin + for(i = C_B_WIDTH; i > 0; i = i - 1) + begin // Is this character a '0'? (ASCII = 48 = 00110000) + if(instring[(i*8)] == 0 && + instring[(i*8)-1] == 0 && + instring[(i*8)-2] == 1 && + instring[(i*8)-3] == 1 && + instring[(i*8)-4] == 0 && + instring[(i*8)-5] == 0 && + instring[(i*8)-6] == 0 && + instring[(i*8)-7] == 0) + to_bitsB[i-1] = 0; + // Or is it a '1'? + else if(instring[(i*8)] == 0 && + instring[(i*8)-1] == 0 && + instring[(i*8)-2] == 1 && + instring[(i*8)-3] == 1 && + instring[(i*8)-4] == 0 && + instring[(i*8)-5] == 0 && + instring[(i*8)-6] == 0 && + instring[(i*8)-7] == 1) + to_bitsB[i-1] = 1; + // Or is it a ' '? (a null char - in which case insert a '0') + else if(instring[(i*8)] == 0 && + instring[(i*8)-1] == 0 && + instring[(i*8)-2] == 0 && + instring[(i*8)-3] == 0 && + instring[(i*8)-4] == 0 && + instring[(i*8)-5] == 0 && + instring[(i*8)-6] == 0 && + instring[(i*8)-7] == 0) + to_bitsB[i-1] = 0; + else + begin + $display("Error in %m at time %d ns: non-binary digit in string \"%s\"\nExiting simulation...",$time, instring); + $finish; + end + end + end + end + endfunction + + function max_bval; + input [C_B_WIDTH*8 : 1] instring; + integer i; + integer last_val; + integer non_null_string; + begin + non_null_string = 1; + for(i = 0; i < C_B_WIDTH; i = i + 1) + begin // Is the string empty? + + // if(instring[(i*8)] == 0 && + // instring[(i*8)-1] == 0 && + // instring[(i*8)-2] == 0 && + // instring[(i*8)-3] == 0 && + // instring[(i*8)-4] == 0 && + // instring[(i*8)-5] == 0 && + // instring[(i*8)-6] == 0 && + // instring[(i*8)-7] == 0 && + // non_null_string == 1) + // non_null_string = 0; + + // is string a '0' + // else if(instring[(i*8)] == 0 && + if(instring[(i*8)] == 0 && + instring[(i*8)-1] == 0 && + instring[(i*8)-2] == 1 && + instring[(i*8)-3] == 1 && + instring[(i*8)-4] == 0 && + instring[(i*8)-5] == 0 && + instring[(i*8)-6] == 0 && + instring[(i*8)-7] == 0 && + non_null_string == 1) +// non_null_string = 1; + last_val = 0; + // Or is it a '1'? + else if(instring[(i*8)] == 0 && + instring[(i*8)-1] == 0 && + instring[(i*8)-2] == 1 && + instring[(i*8)-3] == 1 && + instring[(i*8)-4] == 0 && + instring[(i*8)-5] == 0 && + instring[(i*8)-6] == 0 && + instring[(i*8)-7] == 1 && + non_null_string == 1) + + // non_null_string = 1; + last_val = 1; + else + non_null_string = 0; + end + + max_bval = last_val; + end + endfunction + + function max; + input a; + input b; + begin + max = (a > b) ? a : b; + end + endfunction + + function is_X; + input [tmpWidth-1 : 0] i; + begin + is_X = 1'b0; + for(j = 0; j < tmpWidth; j = j + 1) + begin + if(i[j] === 1'bx) + is_X = 1'b1; + end // loop + end + endfunction + + function [tmpWidth-1 : 0] add; + input [tmpWidth-1 : 0] i1; + input [tmpWidth-1 : 0] i2; + integer bit_index; + integer carryin, carryout; + begin + carryin = 0; + carryout = 0; + for(bit_index=0; bit_index < tmpWidth; bit_index = bit_index + 1) + begin + add[bit_index] = i1[bit_index] ^ i2[bit_index] ^ carryin; + carryout = (i1[bit_index] && i2[bit_index]) || (carryin && (i1[bit_index] || i2[bit_index])); + carryin = carryout; + end + end + endfunction + + function [tmpWidth-1 : 0] sub; + input [tmpWidth-1 : 0] i1; + input [tmpWidth-1 : 0] i2; + begin + i2 = add(~i2, 1); + sub = add(i1, i2); + end + endfunction + + function [tmpWidth-2 : 0] sm_add; + input [tmpWidth-2 : 0] i1; + input [tmpWidth-2 : 0] i2; + integer bit_index; + integer carryin, carryout; + begin + carryin = 0; + carryout = 0; + for(bit_index=0; bit_index < tmpWidth-1; bit_index = bit_index + 1) + begin + sm_add[bit_index] = i1[bit_index] ^ i2[bit_index] ^ carryin; + carryout = (i1[bit_index] && i2[bit_index]) || (carryin && (i1[bit_index] || i2[bit_index])); + carryin = carryout; + end + end + endfunction + + function [tmpWidth-2 : 0] sm_sub; + input [tmpWidth-2 : 0] i1; + input [tmpWidth-2 : 0] i2; + begin + i2 = sm_add(~i2, 1); + sm_sub = sm_add(i1, i2); + end + endfunction + +endmodule + +`undef c_set +`undef c_clear +`undef c_override +`undef c_no_override +`undef c_add +`undef c_sub +`undef c_add_sub +`undef c_signed +`undef c_unsigned +`undef c_pin +`undef allUKs diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/C_BIT_CORRELATOR_V3_0.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/C_BIT_CORRELATOR_V3_0.v new file mode 100644 index 0000000..f24b6b9 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/C_BIT_CORRELATOR_V3_0.v @@ -0,0 +1,438 @@ +//-- $ID:$ +// ************************************************************************ +// $Id: C_BIT_CORRELATOR_V3_0.V +// ************************************************************************ +// Copyright 2000 - Xilinx Inc. +// All rights reserved. +// ************************************************************************ +// Filename: C_BIT_CORRELATOR_V3_0.V +// Creation : Nov. 1th, 2000 +// Description: Verilog Behavioral Model for bit_correlator Model +// +// Algorithm : Compares the bits of a sequence, with a pattern +// which may/maynot have some bits masked. The sequence +// can be from upto 8 possible channels, sequencing every +// clock cycle. (currently supported for serial input) +// ************************************************************************ +// ************************************************************************ +// Last Change : +// +// ************************************************************************ + +`timescale 1ns/10ps + +// some definitions + +`define true 1'b1 +`define false 1'b0 + +`define c_enable_rlocs 0 + +`define c_serial 0 +`define c_parallel_2_serial 1 +`define c_parallel 2 + +`define c_no_reload 0 +`define c_reload 1 + +module C_BIT_CORRELATOR_V3_0 + (CLK, // clock + DIN, // Data INput + LD_DIN, LD_WE, COEF_LD, // unsupported reload ports for version 3.0 + ND, // qualifying signal for DIN, new data + DOUT, // Data OUTput + RDY, RFD, //DOUT qualifier ReaDY, ND qualifier Ready_For_Data + SEL_I, SEL_O); // Input and Output channel indicator + + parameter C_CHANNELS = 1; + parameter C_DATA_WIDTH = 1; + // unsupported placement option for version 3.0 + parameter C_ENABLE_RLOCS = `false; + parameter C_HAS_MASK = `false; + parameter C_HAS_SEL_INDICATOR = `false; + parameter C_INPUT_TYPE = `c_serial; + parameter C_LATENCY = 2; //latency in correlating, + //doesn't include latency + //due to reading data + parameter C_MEM_INIT_FILE = "bit_corr_16.mif"; + + // unsupported reload options for version 3.0 + parameter C_RELOAD = `c_no_reload; + parameter C_RELOAD_DELAY = 0; + parameter C_RELOAD_MEM_TYPE = 0; + + // unsupported placement option for version 3.0 + parameter C_SHAPE = 0; + + // number of taps of the bit correlator + parameter C_TAPS = 16; + + /******* number of bits needed to represent #channels ********/ + parameter channel_width = ((C_CHANNELS <=2) ? 1: + ((C_CHANNELS <=4) ? 2: + ((C_CHANNELS <=8) ? 3:4))); + + /************************************************************* + using word 'score' to mean the #bits matching and score_width + is the bit_width required to represent this number. + *************************************************************/ + parameter score_width = ((C_TAPS < 2) ? 1: + ((C_TAPS < 4) ? 2: + ((C_TAPS < 8) ? 3: + ((C_TAPS < 16) ? 4: + ((C_TAPS < 32) ? 5: + ((C_TAPS < 64) ? 6: + ((C_TAPS < 128) ? 7: + ((C_TAPS < 256) ? 8: + ((C_TAPS < 512) ? 9: + ((C_TAPS < 1024) ? 10: + ((C_TAPS < 2048) ? 11: + ((C_TAPS < 4096) ? 12:13)))))))))))); + parameter rfd_delay = ((C_INPUT_TYPE == `c_parallel_2_serial) ? + C_DATA_WIDTH : 1); + parameter rdy_counter_max = rfd_delay; + + parameter rdy_latency = C_LATENCY; + + parameter actual_input_width = ((C_INPUT_TYPE == `c_serial) ? 1: + ((C_INPUT_TYPE == `c_parallel) ? C_TAPS : + C_DATA_WIDTH)); + input CLK; + input [actual_input_width - 1 : 0] DIN; + input LD_DIN; // not supported in version 3.0 + input LD_WE; // not supported in version 3.0 + input COEF_LD; // not supported in version 3.0 + input ND; + + output [score_width - 1 : 0] DOUT; + output RDY; + output RFD; + output [channel_width - 1 : 0] SEL_I; + output [channel_width - 1 : 0] SEL_O; + + reg [score_width - 1 : 0] DOUT; + reg RDY; + reg RFD; + reg [channel_width - 1 : 0] SEL_I; + reg [channel_width - 1 : 0] SEL_O; + + reg local_rdy; + + // registers for input storage + reg [C_TAPS - 1 : 0] reg_din[C_CHANNELS - 1:0]; + reg [C_TAPS - 1 : 0] tmp_din; + reg [C_TAPS - 1 : 0] tmp_reg_din; + // registers for pattern and mask + reg [C_TAPS - 1 : 0] pattern; + reg [C_TAPS - 1 : 0] mask; + + reg [channel_width - 1 : 0] in_channel; + reg [score_width - 1 : 0] count; + //reg [C_DATA_WIDTH - 1 : 0] psc_din; + reg [actual_input_width - 1 : 0] psc_din; //hp, 30jul, trying to correct + //the VSS/VCS error messages for psc_bin(C_DATA_WIDTH-1:1) usage. + reg [score_width : 0] dout_array[ C_LATENCY - 1 :0]; + reg [score_width : 0] sel_o_array[ C_LATENCY - 1:0]; + reg rdy_array[ rdy_latency : 0]; + + reg input_buffer_empty; + + integer count_rfd, delay, count_rdy; + integer i, bits; + integer start_correlator; //integer value to start off the process + + integer load_counter; + + /************** shift new data into corresponding channel ***********/ + task shift_data; + + begin + if (C_INPUT_TYPE == `c_parallel) + begin + if ((ND == 1'b1) && (RFD == 1'b1)) + reg_din[0] = DIN; + end + else if(C_INPUT_TYPE == `c_serial) + begin + if((ND == 1'b1) && (RFD == 1'b1)) + begin + tmp_din = reg_din[in_channel]; + if(C_TAPS > 1) + tmp_din = {tmp_din[(C_TAPS - 2) : 0], DIN}; + else + tmp_din = DIN; + reg_din[in_channel] = tmp_din; + end + end + else if(C_INPUT_TYPE == `c_parallel_2_serial) + begin + if((ND == 1'b1) && (RFD == 1'b1)) + begin + psc_din = DIN; + load_counter = 0; + end + + else if ((load_counter < (actual_input_width-1)) && (actual_input_width> 1)) + begin + for (i = 0; i <= actual_input_width - 1;i=i + 1) + begin + if(i== (actual_input_width - 1) ) + psc_din[actual_input_width - 1] = 1'b0; + else + psc_din[i] = psc_din[i+1]; + end + //psc_din = {1'b0, psc_din[(actual_input_width - 1): 1]}; + load_counter = load_counter + 1; + end + + if((ND == 1'b0) && (RFD == 1'b1)) + input_buffer_empty = 1'b1; + else + input_buffer_empty = 1'b0; + + + tmp_din = reg_din[in_channel]; + if (input_buffer_empty == 1'b0) + begin + if(C_TAPS > 1) + tmp_din = {tmp_din[(C_TAPS -2) : 0], psc_din[0]}; + else + tmp_din = psc_din[0]; + end + reg_din[in_channel] = tmp_din; + end + end + endtask + + /************** read the file for pattern and mask bits ***********/ + task read_pattern_mask; + + reg[3:0] data_from_file[(C_TAPS -1) : 0]; + reg [3:0] tmp; + + begin + // Reading the MIF file and assigning the bits to + // pattern and mask variable + + $readmemh(C_MEM_INIT_FILE, data_from_file); + + for(i=0;i= C_CHANNELS -1 ) ? 0: in_channel + 1; + + start_correlator = 1; //basically waiting for 1st ND + + end // ND high + + shift_data; + +/******************* Counting the matched bits ************/ + if (start_correlator == 0) + count = 0; + else + begin + count = 0; + tmp_reg_din = reg_din[in_channel]; + for(bits=0; bits <= (C_TAPS - 1) ; bits = bits + 1) + begin + if(mask[bits] == 1'b1) + begin + if(tmp_reg_din[bits] == pattern[bits]) + begin + count = count + 1; + end + end + end + end + + // generate RFD + //if((C_INPUT_TYPE == `c_parallel_2_serial) && (C_DATA_WIDTH > 1)) + + //hp,30jul, trying to correct + //the VSS/VCS error messages for psc_bin(C_DATA_WIDTH-1:1) usage. + if((C_INPUT_TYPE == `c_parallel_2_serial) && (actual_input_width > 1)) + begin + if((ND == 1) && (RFD == 1)) // also checking RFD to allow for ND + // ND to remain high all time when + // user has the input ready always + begin + count_rfd = rfd_delay - 2; + RFD <= 1'b0; + end + else if(start_correlator == 1) + begin + if (count_rfd == 0) // RFD is pulled high 1 clk cycle earlier + begin // so that we donot waste one clock. + RFD <= 1'b1; + end + else if (count_rfd > 0) + begin + RFD <= 1'b0; + count_rfd = (count_rfd - 1); + end + else + $display( "%m,%dns Error: count_rfd < 0", $time); + end + end + else + RFD <= 1'b1; + + // local_rdy generation dependent on ND and C_DATA_WIDTH + + if (ND == 1) + begin + local_rdy = 1; + count_rdy = rdy_counter_max - 1; + end + else + begin + if(count_rdy == 0) + begin + local_rdy = 0; + end + else + begin + count_rdy = count_rdy - 1; + local_rdy = 1; + end + end + + // RDY generation + if(rdy_latency == 1) + RDY <= local_rdy; + else + begin + RDY <= rdy_array[rdy_latency - 2]; + for (delay = rdy_latency -3 ;delay >= 0;delay = delay -1) + rdy_array[delay +1] <= rdy_array[delay]; + rdy_array[0] <= local_rdy; + end + + if (C_LATENCY == 1) + DOUT <= count; + else if (C_LATENCY >= 2) + begin + DOUT <= dout_array[C_LATENCY - 2]; + for ( delay = C_LATENCY - 3; delay >= 0; delay = delay - 1) + dout_array[delay + 1] <= dout_array[delay]; + dout_array[0] <= count; + end + + //generate SEL_O + if((C_HAS_SEL_INDICATOR) && (C_INPUT_TYPE == `c_serial)) + begin + if (C_LATENCY >= 1) + begin + SEL_O <= sel_o_array[C_LATENCY - 1]; + for (delay = C_LATENCY - 2;delay >= 0; delay = delay - 1) + sel_o_array[delay + 1] <= sel_o_array[delay]; + sel_o_array[0] <= in_channel; + end + + //generating SEL_O + SEL_I = in_channel; + end + + end //always + +endmodule + +`undef true +`undef false + +`undef c_enable_rlocs + +`undef c_serial +`undef c_parallel_2_serial +`undef c_parallel + +`undef c_no_reload +`undef c_reload diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/C_COMPARE_V4_0.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/C_COMPARE_V4_0.v new file mode 100644 index 0000000..a4f4df9 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/C_COMPARE_V4_0.v @@ -0,0 +1,1219 @@ +/* $Id: C_COMPARE_V4_0.v,v 1.11 2008/09/08 20:05:45 akennedy Exp $ +-- +-- Filename - C_COMPARE_V4_0.v +-- Author - Xilinx +-- Creation - 28 Jan 1999 +-- +-- Description - This file contains the Verilog behavior for the Baseblocks C_COMPARE_V4_0 module +*/ + + + +`define c_set 0 +`define c_clear 1 +`define c_override 0 +`define c_no_override 1 +`define c_signed 0 +`define c_unsigned 1 + +module C_COMPARE_V4_0 (A, B, CLK, CE, ACLR, ASET, SCLR, SSET, + A_EQ_B, A_NE_B, A_LT_B, A_GT_B, A_LE_B, A_GE_B, + QA_EQ_B, QA_NE_B, QA_LT_B, QA_GT_B, QA_LE_B, QA_GE_B); + + parameter C_AINIT_VAL = ""; + parameter C_B_CONSTANT = 0; + parameter C_B_VALUE = ""; + parameter C_DATA_TYPE = `c_unsigned; + parameter C_ENABLE_RLOCS = 1; + parameter C_HAS_ACLR = 0; + parameter C_HAS_ASET = 0; + parameter C_HAS_A_EQ_B = 1; + parameter C_HAS_A_GE_B = 0; + parameter C_HAS_A_GT_B = 0; + parameter C_HAS_A_LE_B = 0; + parameter C_HAS_A_LT_B = 0; + parameter C_HAS_A_NE_B = 0; + parameter C_HAS_CE = 0; + parameter C_HAS_QA_EQ_B = 0; + parameter C_HAS_QA_GE_B = 0; + parameter C_HAS_QA_GT_B = 0; + parameter C_HAS_QA_LE_B = 0; + parameter C_HAS_QA_LT_B = 0; + parameter C_HAS_QA_NE_B = 0; + parameter C_HAS_SCLR = 0; + parameter C_HAS_SSET = 0; + parameter C_PIPE_STAGES = 1; + parameter C_SYNC_ENABLE = `c_override; + parameter C_SYNC_PRIORITY = `c_clear; + parameter C_WIDTH = 16; + + + input [C_WIDTH-1 : 0] A; + input [C_WIDTH-1 : 0] B; + input CLK; + input CE; + input ACLR; + input ASET; + input SCLR; + input SSET; + output A_EQ_B; + output A_NE_B; + output A_LT_B; + output A_GT_B; + output A_LE_B; + output A_GE_B; + output QA_EQ_B; + output QA_NE_B; + output QA_LT_B; + output QA_GT_B; + output QA_LE_B; + output QA_GE_B; + + // Internal values to drive signals when input is missing + reg [C_WIDTH-1 : 0] intB; + reg intCE; + reg intACLR; + reg intASET; + reg intSCLR; + reg intSSET; + reg intA_EQ_B; + reg intA_NE_B; + reg intA_LT_B; + reg intA_GT_B; + reg intA_LE_B; + reg intA_GE_B; + wire intQA_EQ_B; + wire intQA_NE_B; + wire intQA_LT_B; + wire intQA_GT_B; + wire intQA_LE_B; + wire intQA_GE_B; + reg lastCLK; + + reg [C_PIPE_STAGES+2 : 0] intQA_EQ_Bpipe; + reg intQA_EQ_Bpipeend; + reg [C_PIPE_STAGES+2 : 0] intQA_NE_Bpipe; + reg intQA_NE_Bpipeend; + reg [C_PIPE_STAGES+2 : 0] intQA_LT_Bpipe; + reg intQA_LT_Bpipeend; + reg [C_PIPE_STAGES+2 : 0] intQA_GT_Bpipe; + reg intQA_GT_Bpipeend; + reg [C_PIPE_STAGES+2 : 0] intQA_LE_Bpipe; + reg intQA_LE_Bpipeend; + reg [C_PIPE_STAGES+2 : 0] intQA_GE_Bpipe; + reg intQA_GE_Bpipeend; + + wire AINIT; + wire SINIT; + + wire A_EQ_B = (C_HAS_A_EQ_B == 1 ? intA_EQ_B : 1'bx); + wire A_NE_B = (C_HAS_A_NE_B == 1 ? intA_NE_B : 1'bx); + wire A_LT_B = (C_HAS_A_LT_B == 1 ? intA_LT_B : 1'bx); + wire A_GT_B = (C_HAS_A_GT_B == 1 ? intA_GT_B : 1'bx); + wire A_LE_B = (C_HAS_A_LE_B == 1 ? intA_LE_B : 1'bx); + wire A_GE_B = (C_HAS_A_GE_B == 1 ? intA_GE_B : 1'bx); + wire QA_EQ_B = (C_HAS_QA_EQ_B == 1 ? intQA_EQ_B : 1'bx); + wire QA_NE_B = (C_HAS_QA_NE_B == 1 ? intQA_NE_B : 1'bx); + wire QA_LT_B = (C_HAS_QA_LT_B == 1 ? intQA_LT_B : 1'bx); + wire QA_GT_B = (C_HAS_QA_GT_B == 1 ? intQA_GT_B : 1'bx); + wire QA_LE_B = (C_HAS_QA_LE_B == 1 ? intQA_LE_B : 1'bx); + wire QA_GE_B = (C_HAS_QA_GE_B == 1 ? intQA_GE_B : 1'bx); + + integer pipe, notdone, i; + + reg aeqb, aneb, altb, agtb, aleb, ageb; + reg [C_WIDTH-1:0] a_low; + reg [C_WIDTH-1:0] a_high; + reg [C_WIDTH-1:0] b_low; + reg [C_WIDTH-1:0] b_high; + + // Instance the required output regs + C_REG_FD_V4_0 #(C_AINIT_VAL, C_ENABLE_RLOCS, C_HAS_ACLR, 0, C_HAS_ASET, + C_HAS_CE, C_HAS_SCLR, 0, C_HAS_SSET, + "0", C_SYNC_ENABLE, C_SYNC_PRIORITY, 1) + regaeqb (.D(intQA_EQ_Bpipeend), .CLK(CLK), .CE(CE), .ACLR(ACLR), .ASET(ASET), + .AINIT(AINIT), .SCLR(SCLR), .SSET(SSET), .SINIT(SINIT), + .Q(intQA_EQ_B)); + + C_REG_FD_V4_0 #(C_AINIT_VAL, C_ENABLE_RLOCS, C_HAS_ACLR, 0, C_HAS_ASET, + C_HAS_CE, C_HAS_SCLR, 0, C_HAS_SSET, + "0", C_SYNC_ENABLE, C_SYNC_PRIORITY, 1) + reganeb (.D(intQA_NE_Bpipeend), .CLK(CLK), .CE(CE), .ACLR(ACLR), .ASET(ASET), + .AINIT(AINIT), .SCLR(SCLR), .SSET(SSET), .SINIT(SINIT), + .Q(intQA_NE_B)); + + C_REG_FD_V4_0 #(C_AINIT_VAL, C_ENABLE_RLOCS, C_HAS_ACLR, 0, C_HAS_ASET, + C_HAS_CE, C_HAS_SCLR, 0, C_HAS_SSET, + "0", C_SYNC_ENABLE, C_SYNC_PRIORITY, 1) + regaltb (.D(intQA_LT_Bpipeend), .CLK(CLK), .CE(CE), .ACLR(ACLR), .ASET(ASET), + .AINIT(AINIT), .SCLR(SCLR), .SSET(SSET), .SINIT(SINIT), + .Q(intQA_LT_B)); + + C_REG_FD_V4_0 #(C_AINIT_VAL, C_ENABLE_RLOCS, C_HAS_ACLR, 0, C_HAS_ASET, + C_HAS_CE, C_HAS_SCLR, 0, C_HAS_SSET, + "0", C_SYNC_ENABLE, C_SYNC_PRIORITY, 1) + regagtb (.D(intQA_GT_Bpipeend), .CLK(CLK), .CE(CE), .ACLR(ACLR), .ASET(ASET), + .AINIT(AINIT), .SCLR(SCLR), .SSET(SSET), .SINIT(SINIT), + .Q(intQA_GT_B)); + + C_REG_FD_V4_0 #(C_AINIT_VAL, C_ENABLE_RLOCS, C_HAS_ACLR, 0, C_HAS_ASET, + C_HAS_CE, C_HAS_SCLR, 0, C_HAS_SSET, + "0", C_SYNC_ENABLE, C_SYNC_PRIORITY, 1) + regaleb (.D(intQA_LE_Bpipeend), .CLK(CLK), .CE(CE), .ACLR(ACLR), .ASET(ASET), + .AINIT(AINIT), .SCLR(SCLR), .SSET(SSET), .SINIT(SINIT), + .Q(intQA_LE_B)); + + C_REG_FD_V4_0 #(C_AINIT_VAL, C_ENABLE_RLOCS, C_HAS_ACLR, 0, C_HAS_ASET, + C_HAS_CE, C_HAS_SCLR, 0, C_HAS_SSET, + "0", C_SYNC_ENABLE, C_SYNC_PRIORITY, 1) + regageb (.D(intQA_GE_Bpipeend), .CLK(CLK), .CE(CE), .ACLR(ACLR), .ASET(ASET), + .AINIT(AINIT), .SCLR(SCLR), .SSET(SSET), .SINIT(SINIT), + .Q(intQA_GE_B)); + + initial + begin + #1; + intCE = defval(CE, C_HAS_CE, 1); + intB = defvecval(B, (C_B_CONSTANT == 1) ? 0 : 1, to_bits(C_B_VALUE)); + + intQA_EQ_Bpipe = 'b0; + intQA_NE_Bpipe = 'b0; + intQA_LT_Bpipe = 'b0; + intQA_GT_Bpipe = 'b0; + intQA_LE_Bpipe = 'b0; + intQA_GE_Bpipe = 'b0; + + if(is_X(A) == 1 || is_X(intB) == 1) + begin + notdone = 1; + if((is_X(A) && A === {C_WIDTH{1'bx}}) && (is_X(intB) && intB === {C_WIDTH{1'bx}})) + begin + aeqb <= 1'bx; + aneb <= 1'bx; + altb <= 1'bx; + agtb <= 1'bx; + aleb <= 1'bx; + ageb <= 1'bx; + notdone = 0; + end + else if(C_DATA_TYPE == `c_signed) + begin +/* if(A[C_WIDTH-1] === 1'bx && intB[C_WIDTH-1] === 1'bx) + // Don't know the sign of EITHER data => ALL X's + begin + aeqb <= 1'bx; + aneb <= 1'bx; + altb <= 1'bx; + agtb <= 1'bx; + aleb <= 1'bx; + ageb <= 1'bx; + notdone = 0; + end + else if (A[C_WIDTH-1] !== 1'bx && intB[C_WIDTH-1] !== 1'bx) +*/ if (A[C_WIDTH-1] !== 1'bx && intB[C_WIDTH-1] !== 1'bx) + begin + // The sign bits are both known + if (A[C_WIDTH-1] !== intB[C_WIDTH-1]) + begin + // different signs! + if (A[C_WIDTH-1] === 1'b1) + begin + // A is negative and B is positive + aeqb <= 0; + aneb <= 1; + altb <= 1; + agtb <= 0; + aleb <= 1; + ageb <= 0; + notdone = 0; + end + else // A is +ve and B is -ve + begin + aeqb <= 0; + aneb <= 1; + altb <= 0; + agtb <= 1; + aleb <= 0; + ageb <= 1; + notdone = 0; + end + end + end + end + if (notdone == 1) // check further + begin + // Make copies of A and B with all X's substituted with 0's and 1's + a_low = A; + a_high = A; + b_low = intB; + b_high = intB; + for (i=C_WIDTH-2; i >= 0; i = i - 1) + begin + if (a_low[i] === 1'bx) + begin + a_low[i] = 0; + a_high[i] = 1; + end + if (b_low[i] === 1'bx) + begin + b_low[i] = 0; + b_high[i] = 1; + end + end + // we now (almost - need to check possible sign bits) have worst-case values which must agree on the comparison result + // if that result is not to be unknown... + if (C_DATA_TYPE == `c_signed) + begin + // Set the sign bits of the range values to 0 since + // the sign of the values will be treated separately + a_low[C_WIDTH-1] = 0; + a_high[C_WIDTH-1] = 0; + b_low[C_WIDTH-1] = 0; + b_high[C_WIDTH-1] = 0; + + if((A[C_WIDTH-1] === 1'b1 && intB[C_WIDTH-1] === 1'bx) + || (intB[C_WIDTH-1] === 1'b0 && A[C_WIDTH-1] === 1'bx)) + begin // Sign of A is -ve and sign of B is unknown OR + // sign of B is +ve and sign of A is unknown + // Is A always < B? + if (a_high < b_low) + begin + // A is definitely < than B + aeqb <= 0; + aneb <= 1; + altb <= 1; + agtb <= 0; + aleb <= 1; + ageb <= 0; + end + else if (a_high == b_low) + begin + // A is <= than B + aeqb <= 1'bx; + aneb <= 1'bx; + altb <= 1'bx; + agtb <= 0; + aleb <= 1; + ageb <= 1'bx; + end + else if (a_low != b_low && a_low !== b_high && a_high !== b_low && a_high !== b_high && !(intB === {C_WIDTH{1'bx}} || A === {C_WIDTH{1'bx}})) + begin // Definitely not equal! + aeqb <= 1'b0; + aneb <= 1'b1; + altb <= 1'bx; + agtb <= 1'bx; + aleb <= 1'bx; + ageb <= 1'bx; + end + else // There is > 1 overlap between the ranges so all X's + begin + aeqb <= 1'bx; + aneb <= 1'bx; + altb <= 1'bx; + agtb <= 1'bx; + aleb <= 1'bx; + ageb <= 1'bx; + end + end + else if((A[C_WIDTH-1] === 1'b0 && intB[C_WIDTH-1] === 1'bx) + || (intB[C_WIDTH-1] === 1'b1 && A[C_WIDTH-1] === 1'bx)) + begin // Sign of A is +ve and sign of B is unknown OR + // sign of B is -ve and sign of A is unknown + // Is B always < A? + if (b_high < a_low) + begin + // B is definitely < than A + aeqb <= 0; + aneb <= 1; + altb <= 0; + agtb <= 1; + aleb <= 0; + ageb <= 1; + end + else if (b_high == a_low) + begin + // B is <= than A + aeqb <= 1'bx; + aneb <= 1'bx; + altb <= 0; + agtb <= 1'bx; + aleb <= 1'bx; + ageb <= 1; + end + else if (a_low != b_low && a_low !== b_high && a_high !== b_low && a_high !== b_high && !(intB === {C_WIDTH{1'bx}} || A === {C_WIDTH{1'bx}})) + begin // Definitely not equal! + aeqb <= 1'b0; + aneb <= 1'b1; + altb <= 1'bx; + agtb <= 1'bx; + aleb <= 1'bx; + ageb <= 1'bx; + end + else // There is > 1 overlap between the ranges so all X's + begin + aeqb <= 1'bx; + aneb <= 1'bx; + altb <= 1'bx; + agtb <= 1'bx; + aleb <= 1'bx; + ageb <= 1'bx; + end + end + else // Sign bits on A and B are identical and both are known + begin + if (a_high < b_low) + begin + // A is definitely < than B + aeqb <= 0; + aneb <= 1; + altb <= 1; + agtb <= 0; + aleb <= 1; + ageb <= 0; + end + else if (a_low > b_high) + begin + // A is definitely > than B + aeqb <= 0; + aneb <= 1; + altb <= 0; + agtb <= 1; + aleb <= 0; + ageb <= 1; + end + else if (a_high == b_low) + begin + // A is <= than B + aeqb <= 1'bx; + aneb <= 1'bx; + altb <= 1'bx; + agtb <= 0; + aleb <= 1; + ageb <= 1'bx; + end + else if (a_low == b_high) + begin + // A is >= than B + aeqb <= 1'bx; + aneb <= 1'bx; + altb <= 0; + agtb <= 1'bx; + aleb <= 1'bx; + ageb <= 1; + end + else if (a_low != b_low && a_low !== b_high && a_high !== b_low && a_high !== b_high && !(intB === {C_WIDTH{1'bx}} || A === {C_WIDTH{1'bx}})) + begin // Definitely not equal! + aeqb <= 1'b0; + aneb <= 1'b1; + altb <= 1'bx; + agtb <= 1'bx; + aleb <= 1'bx; + ageb <= 1'bx; + end + else // There is > 1 overlap between the ranges so all X's + begin + aeqb <= 1'bx; + aneb <= 1'bx; + altb <= 1'bx; + agtb <= 1'bx; + aleb <= 1'bx; + ageb <= 1'bx; + end + end + end + else // unsigned data + begin + if (a_low[C_WIDTH-1] === 1'bx) + begin + a_low[C_WIDTH-1] = 0; + a_high[C_WIDTH-1] = 1; + end + if (b_low[C_WIDTH-1] === 1'bx) + begin + b_low[C_WIDTH-1] = 0; + b_high[C_WIDTH-1] = 1; + end + if (a_high < b_low) + begin + // A is definitely < than B + aeqb <= 0; + aneb <= 1; + altb <= 1; + agtb <= 0; + aleb <= 1; + ageb <= 0; + end + else if (a_low > b_high) + begin + // A is definitely > than B + aeqb <= 0; + aneb <= 1; + altb <= 0; + agtb <= 1; + aleb <= 0; + ageb <= 1; + end + else if (a_high == b_low) + begin + // A is <= B + aeqb <= 1'bx; + aneb <= 1'bx; + altb <= 1'bx; + agtb <= 0; + aleb <= 1; + ageb <= 1'bx; + end + else if (a_low == b_high) + begin + // A is >= B + aeqb <= 1'bx; + aneb <= 1'bx; + altb <= 0; + agtb <= 1'bx; + aleb <= 1'bx; + ageb <= 1; + end + else if (a_low != b_low && a_low !== b_high && a_high !== b_low && a_high !== b_high && !(intB === {C_WIDTH{1'bx}} || A === {C_WIDTH{1'bx}})) + begin // Definitely not equal! + aeqb <= 1'b0; + aneb <= 1'b1; + altb <= 1'bx; + agtb <= 1'bx; + aleb <= 1'bx; + ageb <= 1'bx; + end + else // There is > 1 overlap between the ranges so all X's + begin + aeqb <= 1'bx; + aneb <= 1'bx; + altb <= 1'bx; + agtb <= 1'bx; + aleb <= 1'bx; + ageb <= 1'bx; + end + end + end + end + else if (C_DATA_TYPE == `c_signed) + begin + // Signed data so examine MSB and rest separately in some cases + if(A == intB) + begin + aeqb <= 1; + aneb <= 0; + altb <= 0; + agtb <= 0; + end + else if(A[C_WIDTH-1] == intB[C_WIDTH-1]) // Both numbers are -ve or both are +ve + begin + if(A < intB) + begin + aeqb <= 0; + aneb <= 1; + altb <= 1; + agtb <= 0; + end + if(A > intB) + begin + aeqb <= 0; + aneb <= 1; + altb <= 0; + agtb <= 1; + end + end + else if(A[C_WIDTH-1] == 1 && intB[C_WIDTH-1] == 0) // A is -ve, B is +ve + begin + aeqb <= 0; + aneb <= 1; + altb <= 1; + agtb <= 0; + end + else if(A[C_WIDTH-1] == 0 && intB[C_WIDTH-1] == 1) // A is +ve, B is -ve + begin + aeqb <= 0; + aneb <= 1; + altb <= 0; + agtb <= 1; + end + if(aeqb == 1 || altb == 1) + aleb <= 1; + else + aleb <= 0; + if(aeqb == 1 || agtb == 1) + ageb <= 1; + else + ageb <= 0; + end + else // Data is unsigned + begin + if(A == intB) + begin + aeqb <= 1; + aneb <= 0; + altb <= 0; + agtb <= 0; + end + if(A < intB) + begin + aeqb <= 0; + aneb <= 1; + altb <= 1; + agtb <= 0; + end + if(A > intB) + begin + aeqb <= 0; + aneb <= 1; + altb <= 0; + agtb <= 1; + end + if(aeqb == 1 || altb == 1) + aleb <= 1; + else + aleb <= 0; + if(aeqb == 1 || agtb == 1) + ageb <= 1; + else + ageb <= 0; + end + + intA_EQ_B <= #1 aeqb; + intA_NE_B <= #1 aneb; + intA_LT_B <= #1 altb; + intA_GT_B <= #1 agtb; + intA_LE_B <= #1 aleb; + intA_GE_B <= #1 ageb; + + end + + always @(CLK) + lastCLK <= CLK; + + always @(A or B or CE or ACLR or ASET or SCLR or SSET) + begin + intCE = defval(CE, C_HAS_CE, 1); + intB = defvecval(B, (C_B_CONSTANT == 1) ? 0 : 1, to_bits(C_B_VALUE)); + + if(is_X(A) == 1 || is_X(intB) == 1) + begin + notdone = 1; + if((is_X(A) && A === {C_WIDTH{1'bx}}) && (is_X(intB) && intB === {C_WIDTH{1'bx}})) + begin + aeqb = 1'bx; + aneb = 1'bx; + altb = 1'bx; + agtb = 1'bx; + aleb = 1'bx; + ageb = 1'bx; + notdone = 0; + end + else if(C_DATA_TYPE == `c_signed) + begin +/* if(A[C_WIDTH-1] === 1'bx && intB[C_WIDTH-1] === 1'bx) + // Don't know the sign of EITHER data => ALL X's + begin + aeqb = 1'bx; + aneb = 1'bx; + altb = 1'bx; + agtb = 1'bx; + aleb = 1'bx; + ageb = 1'bx; + notdone = 0; + end + else if (A[C_WIDTH-1] !== 1'bx && intB[C_WIDTH-1] !== 1'bx) +*/ if (A[C_WIDTH-1] !== 1'bx && intB[C_WIDTH-1] !== 1'bx) + begin + // The sign bits are both known + if (A[C_WIDTH-1] !== intB[C_WIDTH-1]) + begin + // different signs! + if (A[C_WIDTH-1] === 1'b1) + begin + // A is negative and B is positive + aeqb = 0; + aneb = 1; + altb = 1; + agtb = 0; + aleb = 1; + ageb = 0; + notdone = 0; + end + else // A is +ve and B is -ve + begin + aeqb = 0; + aneb = 1; + altb = 0; + agtb = 1; + aleb = 0; + ageb = 1; + notdone = 0; + end + end + end + end + if (notdone == 1) // check further + begin + // Make copies of A and B with all X's substituted with 0's and 1's + a_low = A; + a_high = A; + b_low = intB; + b_high = intB; + for (i=C_WIDTH-2; i >= 0; i = i - 1) + begin + if (a_low[i] === 1'bx) + begin + a_low[i] = 0; + a_high[i] = 1; + end + if (b_low[i] === 1'bx) + begin + b_low[i] = 0; + b_high[i] = 1; + end + end + // we now (almost - need to check possible sign bits) have worst-case values which must agree on the comparison result + // if that result is not to be unknown... + if (C_DATA_TYPE == `c_signed) + begin + // Set the sign bits of the range values to 0 since + // the sign of the values will be treated separately + a_low[C_WIDTH-1] = 0; + a_high[C_WIDTH-1] = 0; + b_low[C_WIDTH-1] = 0; + b_high[C_WIDTH-1] = 0; + + if((A[C_WIDTH-1] === 1'b1 && intB[C_WIDTH-1] === 1'bx) + || (intB[C_WIDTH-1] === 1'b0 && A[C_WIDTH-1] === 1'bx)) + begin // Sign of A is -ve and sign of B is unknown OR + // sign of B is +ve and sign of A is unknown + // Is A always < B? + if (a_high < b_low) + begin + // A is definitely < than B + aeqb = 0; + aneb = 1; + altb = 1; + agtb = 0; + aleb = 1; + ageb = 0; + end + else if (a_high == b_low) + begin + // A is <= than B + aeqb = 1'bx; + aneb = 1'bx; + altb = 1'bx; + agtb = 0; + aleb = 1; + ageb = 1'bx; + end + else if (a_low != b_low && a_low !== b_high && a_high !== b_low && a_high !== b_high && !(intB === {C_WIDTH{1'bx}} || A === {C_WIDTH{1'bx}})) + begin // Definitely not equal! + aeqb = 1'b0; + aneb = 1'b1; + altb = 1'bx; + agtb = 1'bx; + aleb = 1'bx; + ageb = 1'bx; + end + else // There is > 1 overlap between the ranges so all X's + begin + aeqb = 1'bx; + aneb = 1'bx; + altb = 1'bx; + agtb = 1'bx; + aleb = 1'bx; + ageb = 1'bx; + end + end + else if((A[C_WIDTH-1] === 1'b0 && intB[C_WIDTH-1] === 1'bx) + || (intB[C_WIDTH-1] === 1'b1 && A[C_WIDTH-1] === 1'bx)) + begin // Sign of A is +ve and sign of B is unknown OR + // sign of B is -ve and sign of A is unknown + // Is B always < A? + if (b_high < a_low) + begin + // B is definitely < than A + aeqb = 0; + aneb = 1; + altb = 0; + agtb = 1; + aleb = 0; + ageb = 1; + end + else if (b_high == a_low) + begin + // B is <= than A + aeqb = 1'bx; + aneb = 1'bx; + altb = 0; + agtb = 1'bx; + aleb = 1'bx; + ageb = 1; + end + else if (a_low != b_low && a_low !== b_high && a_high !== b_low && a_high !== b_high && !(intB === {C_WIDTH{1'bx}} || A === {C_WIDTH{1'bx}})) + begin // Definitely not equal! + aeqb = 1'b0; + aneb = 1'b1; + altb = 1'bx; + agtb = 1'bx; + aleb = 1'bx; + ageb = 1'bx; + end + else // There is > 1 overlap between the ranges so all X's + begin + aeqb = 1'bx; + aneb = 1'bx; + altb = 1'bx; + agtb = 1'bx; + aleb = 1'bx; + ageb = 1'bx; + end + end + else // Sign bits on A and B are identical and both are known + begin + if (a_high < b_low) + begin + // A is definitely < than B + aeqb = 0; + aneb = 1; + altb = 1; + agtb = 0; + aleb = 1; + ageb = 0; + end + else if (a_low > b_high) + begin + // A is definitely > than B + aeqb = 0; + aneb = 1; + altb = 0; + agtb = 1; + aleb = 0; + ageb = 1; + end + else if (a_high == b_low) + begin + // A is <= than B + aeqb = 1'bx; + aneb = 1'bx; + altb = 1'bx; + agtb = 0; + aleb = 1; + ageb = 1'bx; + end + else if (a_low == b_high) + begin + // A is >= than B + aeqb = 1'bx; + aneb = 1'bx; + altb = 0; + agtb = 1'bx; + aleb = 1'bx; + ageb = 1; + end + else if (a_low != b_low && a_low !== b_high && a_high !== b_low && a_high !== b_high && !(intB === {C_WIDTH{1'bx}} || A === {C_WIDTH{1'bx}})) + begin // Definitely not equal! + aeqb = 1'b0; + aneb = 1'b1; + altb = 1'bx; + agtb = 1'bx; + aleb = 1'bx; + ageb = 1'bx; + end + else // There is > 1 overlap between the ranges so all X's + begin + aeqb = 1'bx; + aneb = 1'bx; + altb = 1'bx; + agtb = 1'bx; + aleb = 1'bx; + ageb = 1'bx; + end + end + end + else // unsigned data + begin + if (a_low[C_WIDTH-1] === 1'bx) + begin + a_low[C_WIDTH-1] = 0; + a_high[C_WIDTH-1] = 1; + end + if (b_low[C_WIDTH-1] === 1'bx) + begin + b_low[C_WIDTH-1] = 0; + b_high[C_WIDTH-1] = 1; + end + if (a_high < b_low) + begin + // A is definitely < than B + aeqb = 0; + aneb = 1; + altb = 1; + agtb = 0; + aleb = 1; + ageb = 0; + end + else if (a_low > b_high) + begin + // A is definitely > than B + aeqb = 0; + aneb = 1; + altb = 0; + agtb = 1; + aleb = 0; + ageb = 1; + end + else if (a_high == b_low) + begin + // A is <= B + aeqb = 1'bx; + aneb = 1'bx; + altb = 1'bx; + agtb = 0; + aleb = 1; + ageb = 1'bx; + end + else if (a_low == b_high) + begin + // A is >= B + aeqb = 1'bx; + aneb = 1'bx; + altb = 0; + agtb = 1'bx; + aleb = 1'bx; + ageb = 1; + end + else if (a_low != b_low && a_low !== b_high && a_high !== b_low && a_high !== b_high && !(intB === {C_WIDTH{1'bx}} || A === {C_WIDTH{1'bx}})) + begin // Definitely not equal! + aeqb = 1'b0; + aneb = 1'b1; + altb = 1'bx; + agtb = 1'bx; + aleb = 1'bx; + ageb = 1'bx; + end + else // There is > 1 overlap between the ranges so all X's + begin + aeqb = 1'bx; + aneb = 1'bx; + altb = 1'bx; + agtb = 1'bx; + aleb = 1'bx; + ageb = 1'bx; + end + end + end + end + else if (C_DATA_TYPE == `c_signed) + begin + // Signed data so examine MSB and rest separately in some cases + if(A == intB) + begin + aeqb = 1; + aneb = 0; + altb = 0; + agtb = 0; + end + else if(A[C_WIDTH-1] == intB[C_WIDTH-1]) // Both numbers are -ve or both are +ve + begin + if(A < intB) + begin + aeqb = 0; + aneb = 1; + altb = 1; + agtb = 0; + end + if(A > intB) + begin + aeqb = 0; + aneb = 1; + altb = 0; + agtb = 1; + end + end + else if(A[C_WIDTH-1] == 1 && intB[C_WIDTH-1] == 0) // A is -ve, B is +ve + begin + aeqb = 0; + aneb = 1; + altb = 1; + agtb = 0; + end + else if(A[C_WIDTH-1] == 0 && intB[C_WIDTH-1] == 1) // A is +ve, B is -ve + begin + aeqb = 0; + aneb = 1; + altb = 0; + agtb = 1; + end + if(aeqb == 1 || altb == 1) + aleb = 1; + else + aleb = 0; + if(aeqb == 1 || agtb == 1) + ageb = 1; + else + ageb = 0; + end + else // Data is unsigned + begin + if(A == intB) + begin + aeqb = 1; + aneb = 0; + altb = 0; + agtb = 0; + end + if(A < intB) + begin + aeqb = 0; + aneb = 1; + altb = 1; + agtb = 0; + end + if(A > intB) + begin + aeqb = 0; + aneb = 1; + altb = 0; + agtb = 1; + end + if(aeqb == 1 || altb == 1) + aleb = 1; + else + aleb = 0; + if(aeqb == 1 || agtb == 1) + ageb = 1; + else + ageb = 0; + end + + intA_EQ_B <= #1 aeqb; + intA_NE_B <= #1 aneb; + intA_LT_B <= #1 altb; + intA_GT_B <= #1 agtb; + intA_LE_B <= #1 aleb; + intA_GE_B <= #1 ageb; + end + + always@(posedge CLK) + begin + if(CLK === 1'b1 && lastCLK === 1'b0 && intCE === 1'b1) // OK! Update pipelines! + begin + for(pipe = 2; pipe <= C_PIPE_STAGES-1; pipe = pipe + 1) + begin + intQA_EQ_Bpipe[pipe] <= intQA_EQ_Bpipe[pipe+1]; + intQA_NE_Bpipe[pipe] <= intQA_NE_Bpipe[pipe+1]; + intQA_LT_Bpipe[pipe] <= intQA_LT_Bpipe[pipe+1]; + intQA_GT_Bpipe[pipe] <= intQA_GT_Bpipe[pipe+1]; + intQA_LE_Bpipe[pipe] <= intQA_LE_Bpipe[pipe+1]; + intQA_GE_Bpipe[pipe] <= intQA_GE_Bpipe[pipe+1]; + end + intQA_EQ_Bpipe[C_PIPE_STAGES] <= intA_EQ_B; + intQA_NE_Bpipe[C_PIPE_STAGES] <= intA_NE_B; + intQA_LT_Bpipe[C_PIPE_STAGES] <= intA_LT_B; + intQA_GT_Bpipe[C_PIPE_STAGES] <= intA_GT_B; + intQA_LE_Bpipe[C_PIPE_STAGES] <= intA_LE_B; + intQA_GE_Bpipe[C_PIPE_STAGES] <= intA_GE_B; + end + else if((CLK === 1'bx && lastCLK === 1'b0) || (CLK === 1'b1 && lastCLK === 1'bx) || intCE === 1'bx) // POSSIBLY Update pipelines! + begin + for(pipe = 2; pipe <= C_PIPE_STAGES-1; pipe = pipe + 1) + begin + if(intQA_EQ_Bpipe[pipe] !== intQA_EQ_Bpipe[pipe+1]) + intQA_EQ_Bpipe[pipe] <= 1'bx; + if(intQA_NE_Bpipe[pipe] !== intQA_NE_Bpipe[pipe+1]) + intQA_NE_Bpipe[pipe] <= 1'bx; + if(intQA_LT_Bpipe[pipe] !== intQA_LT_Bpipe[pipe+1]) + intQA_LT_Bpipe[pipe] <= 1'bx; + if(intQA_GT_Bpipe[pipe] !== intQA_GT_Bpipe[pipe+1]) + intQA_GT_Bpipe[pipe] <= 1'bx; + if(intQA_LE_Bpipe[pipe] !== intQA_LE_Bpipe[pipe+1]) + intQA_LE_Bpipe[pipe] <= 1'bx; + if(intQA_GE_Bpipe[pipe] !== intQA_GE_Bpipe[pipe+1]) + intQA_GE_Bpipe[pipe] <= 1'bx; + end + if(intQA_EQ_Bpipe[C_PIPE_STAGES] !== intA_EQ_B) + intQA_EQ_Bpipe[C_PIPE_STAGES] <= 1'bx; + if(intQA_NE_Bpipe[C_PIPE_STAGES] !== intA_NE_B) + intQA_NE_Bpipe[C_PIPE_STAGES] <= 1'bx; + if(intQA_LT_Bpipe[C_PIPE_STAGES] !== intA_LT_B) + intQA_LT_Bpipe[C_PIPE_STAGES] <= 1'bx; + if(intQA_GT_Bpipe[C_PIPE_STAGES] !== intA_GT_B) + intQA_GT_Bpipe[C_PIPE_STAGES] <= 1'bx; + if(intQA_LE_Bpipe[C_PIPE_STAGES] !== intA_LE_B) + intQA_LE_Bpipe[C_PIPE_STAGES] <= 1'bx; + if(intQA_GE_Bpipe[C_PIPE_STAGES] !== intA_GE_B) + intQA_GE_Bpipe[C_PIPE_STAGES] <= 1'bx; + end + end + + always@(intA_EQ_B or intQA_EQ_Bpipe[2]) + begin + if(C_PIPE_STAGES < 2) // No pipeline + intQA_EQ_Bpipeend <= intA_EQ_B; + else // Pipeline stages required + begin + intQA_EQ_Bpipeend <= intQA_EQ_Bpipe[2]; + end + end + always@(intA_NE_B or intQA_NE_Bpipe[2]) + begin + if(C_PIPE_STAGES < 2) // No pipeline + intQA_NE_Bpipeend <= intA_NE_B; + else // Pipeline stages required + begin + intQA_NE_Bpipeend <= intQA_NE_Bpipe[2]; + end + end + always@(intA_LT_B or intQA_LT_Bpipe[2]) + begin + if(C_PIPE_STAGES < 2) // No pipeline + intQA_LT_Bpipeend <= intA_LT_B; + else // Pipeline stages required + begin + intQA_LT_Bpipeend <= intQA_LT_Bpipe[2]; + end + end + always@(intA_GT_B or intQA_GT_Bpipe[2]) + begin + if(C_PIPE_STAGES < 2) // No pipeline + intQA_GT_Bpipeend <= intA_GT_B; + else // Pipeline stages required + begin + intQA_GT_Bpipeend <= intQA_GT_Bpipe[2]; + end + end + always@(intA_LE_B or intQA_LE_Bpipe[2]) + begin + if(C_PIPE_STAGES < 2) // No pipeline + intQA_LE_Bpipeend <= intA_LE_B; + else // Pipeline stages required + begin + intQA_LE_Bpipeend <= intQA_LE_Bpipe[2]; + end + end + always@(intA_GE_B or intQA_GE_Bpipe[2]) + begin + if(C_PIPE_STAGES < 2) // No pipeline + intQA_GE_Bpipeend <= intA_GE_B; + else // Pipeline stages required + begin + intQA_GE_Bpipeend <= intQA_GE_Bpipe[2]; + end + end + + function is_X; + input [C_WIDTH-1 : 0] i; + integer j; + begin + is_X = 0; + for(j = 0; j < C_WIDTH; j = j + 1) + if(i[j] === 1'bx) + is_X = 1; + end + endfunction + + function defval; + input i; + input hassig; + input val; + begin + if(hassig == 1) + defval = i; + else + defval = val; + end + endfunction + + function [C_WIDTH - 1 : 0] defvecval; + input [C_WIDTH-1 : 0] i; + input hassig; + input [C_WIDTH-1 : 0] val; + begin + if(hassig == 1) + defvecval = i; + else + defvecval = val; + end + endfunction + + function [C_WIDTH - 1 : 0] to_bits; + input [C_WIDTH*8 : 1] instring; + integer i; + integer non_null_string; + begin + non_null_string = 0; + for(i = C_WIDTH; i > 0; i = i - 1) + begin // Is the string empty? + if(instring[(i*8)] == 0 && + instring[(i*8)-1] == 0 && + instring[(i*8)-2] == 0 && + instring[(i*8)-3] == 0 && + instring[(i*8)-4] == 0 && + instring[(i*8)-5] == 0 && + instring[(i*8)-6] == 0 && + instring[(i*8)-7] == 0 && + non_null_string == 0) + non_null_string = 0; // Use the return value to flag a non-empty string + else + non_null_string = 1; // Non-null character! + end + if(non_null_string == 0) // String IS empty! Just return the value to be all '0's + begin + for(i = C_WIDTH; i > 0; i = i - 1) + to_bits[i-1] = 0; + end + else + begin + for(i = C_WIDTH; i > 0; i = i - 1) + begin // Is this character a '0'? (ASCII = 48 = 00110000) + if(instring[(i*8)] == 0 && + instring[(i*8)-1] == 0 && + instring[(i*8)-2] == 1 && + instring[(i*8)-3] == 1 && + instring[(i*8)-4] == 0 && + instring[(i*8)-5] == 0 && + instring[(i*8)-6] == 0 && + instring[(i*8)-7] == 0) + to_bits[i-1] = 0; + // Or is it a '1'? + else if(instring[(i*8)] == 0 && + instring[(i*8)-1] == 0 && + instring[(i*8)-2] == 1 && + instring[(i*8)-3] == 1 && + instring[(i*8)-4] == 0 && + instring[(i*8)-5] == 0 && + instring[(i*8)-6] == 0 && + instring[(i*8)-7] == 1) + to_bits[i-1] = 1; + // Or is it a ' '? (a null char - in which case insert a '0') + else if(instring[(i*8)] == 0 && + instring[(i*8)-1] == 0 && + instring[(i*8)-2] == 0 && + instring[(i*8)-3] == 0 && + instring[(i*8)-4] == 0 && + instring[(i*8)-5] == 0 && + instring[(i*8)-6] == 0 && + instring[(i*8)-7] == 0) + to_bits[i-1] = 0; + else + begin + $display("Error: non-binary digit in string \"%s\"\nExiting simulation...", instring); + $finish; + end + end + end + end + endfunction + +endmodule + +`undef c_set +`undef c_clear +`undef c_override +`undef c_no_override +`undef c_signed +`undef c_unsigned + + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/C_COMPARE_V5_0.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/C_COMPARE_V5_0.v new file mode 100644 index 0000000..364fc1d --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/C_COMPARE_V5_0.v @@ -0,0 +1,1218 @@ +/* $Id: C_COMPARE_V5_0.v,v 1.17 2008/09/08 20:05:55 akennedy Exp $ +-- +-- Filename - C_COMPARE_V5_0.v +-- Author - Xilinx +-- Creation - 28 Jan 1999 +-- +-- Description - This file contains the Verilog behavior for the Baseblocks C_COMPARE_V5_0 module +*/ + +`timescale 1ns/10ps + +`define c_set 0 +`define c_clear 1 +`define c_override 0 +`define c_no_override 1 +`define c_signed 0 +`define c_unsigned 1 + +module C_COMPARE_V5_0 (A, B, CLK, CE, ACLR, ASET, SCLR, SSET, + A_EQ_B, A_NE_B, A_LT_B, A_GT_B, A_LE_B, A_GE_B, + QA_EQ_B, QA_NE_B, QA_LT_B, QA_GT_B, QA_LE_B, QA_GE_B); + + parameter C_AINIT_VAL = ""; + parameter C_B_CONSTANT = 0; + parameter C_B_VALUE = ""; + parameter C_DATA_TYPE = `c_unsigned; + parameter C_ENABLE_RLOCS = 1; + parameter C_HAS_ACLR = 0; + parameter C_HAS_ASET = 0; + parameter C_HAS_A_EQ_B = 1; + parameter C_HAS_A_GE_B = 0; + parameter C_HAS_A_GT_B = 0; + parameter C_HAS_A_LE_B = 0; + parameter C_HAS_A_LT_B = 0; + parameter C_HAS_A_NE_B = 0; + parameter C_HAS_CE = 0; + parameter C_HAS_QA_EQ_B = 0; + parameter C_HAS_QA_GE_B = 0; + parameter C_HAS_QA_GT_B = 0; + parameter C_HAS_QA_LE_B = 0; + parameter C_HAS_QA_LT_B = 0; + parameter C_HAS_QA_NE_B = 0; + parameter C_HAS_SCLR = 0; + parameter C_HAS_SSET = 0; + parameter C_PIPE_STAGES = 1; + parameter C_SYNC_ENABLE = `c_override; + parameter C_SYNC_PRIORITY = `c_clear; + parameter C_WIDTH = 16; + + + input [C_WIDTH-1 : 0] A; + input [C_WIDTH-1 : 0] B; + input CLK; + input CE; + input ACLR; + input ASET; + input SCLR; + input SSET; + output A_EQ_B; + output A_NE_B; + output A_LT_B; + output A_GT_B; + output A_LE_B; + output A_GE_B; + output QA_EQ_B; + output QA_NE_B; + output QA_LT_B; + output QA_GT_B; + output QA_LE_B; + output QA_GE_B; + + // Internal values to drive signals when input is missing + reg [C_WIDTH-1 : 0] intB; + reg intCE; + reg intACLR; + reg intASET; + reg intSCLR; + reg intSSET; + reg intA_EQ_B; + reg intA_NE_B; + reg intA_LT_B; + reg intA_GT_B; + reg intA_LE_B; + reg intA_GE_B; + wire intQA_EQ_B; + wire intQA_NE_B; + wire intQA_LT_B; + wire intQA_GT_B; + wire intQA_LE_B; + wire intQA_GE_B; + reg lastCLK; + + reg [C_PIPE_STAGES+2 : 0] intQA_EQ_Bpipe; + reg intQA_EQ_Bpipeend; + reg [C_PIPE_STAGES+2 : 0] intQA_NE_Bpipe; + reg intQA_NE_Bpipeend; + reg [C_PIPE_STAGES+2 : 0] intQA_LT_Bpipe; + reg intQA_LT_Bpipeend; + reg [C_PIPE_STAGES+2 : 0] intQA_GT_Bpipe; + reg intQA_GT_Bpipeend; + reg [C_PIPE_STAGES+2 : 0] intQA_LE_Bpipe; + reg intQA_LE_Bpipeend; + reg [C_PIPE_STAGES+2 : 0] intQA_GE_Bpipe; + reg intQA_GE_Bpipeend; + + wire AINIT; + wire SINIT; + + wire A_EQ_B = (C_HAS_A_EQ_B == 1 ? intA_EQ_B : 1'bx); + wire A_NE_B = (C_HAS_A_NE_B == 1 ? intA_NE_B : 1'bx); + wire A_LT_B = (C_HAS_A_LT_B == 1 ? intA_LT_B : 1'bx); + wire A_GT_B = (C_HAS_A_GT_B == 1 ? intA_GT_B : 1'bx); + wire A_LE_B = (C_HAS_A_LE_B == 1 ? intA_LE_B : 1'bx); + wire A_GE_B = (C_HAS_A_GE_B == 1 ? intA_GE_B : 1'bx); + wire QA_EQ_B = (C_HAS_QA_EQ_B == 1 ? intQA_EQ_B : 1'bx); + wire QA_NE_B = (C_HAS_QA_NE_B == 1 ? intQA_NE_B : 1'bx); + wire QA_LT_B = (C_HAS_QA_LT_B == 1 ? intQA_LT_B : 1'bx); + wire QA_GT_B = (C_HAS_QA_GT_B == 1 ? intQA_GT_B : 1'bx); + wire QA_LE_B = (C_HAS_QA_LE_B == 1 ? intQA_LE_B : 1'bx); + wire QA_GE_B = (C_HAS_QA_GE_B == 1 ? intQA_GE_B : 1'bx); + + integer pipe, notdone, i; + + reg aeqb, aneb, altb, agtb, aleb, ageb; + reg [C_WIDTH-1:0] a_low; + reg [C_WIDTH-1:0] a_high; + reg [C_WIDTH-1:0] b_low; + reg [C_WIDTH-1:0] b_high; + + // Instance the required output regs + C_REG_FD_V5_0 #(C_AINIT_VAL, C_ENABLE_RLOCS, C_HAS_ACLR, 0, C_HAS_ASET, + C_HAS_CE, C_HAS_SCLR, 0, C_HAS_SSET, + "0", C_SYNC_ENABLE, C_SYNC_PRIORITY, 1) + regaeqb (.D(intQA_EQ_Bpipeend), .CLK(CLK), .CE(CE), .ACLR(ACLR), .ASET(ASET), + .AINIT(AINIT), .SCLR(SCLR), .SSET(SSET), .SINIT(SINIT), + .Q(intQA_EQ_B)); + + C_REG_FD_V5_0 #(C_AINIT_VAL, C_ENABLE_RLOCS, C_HAS_ACLR, 0, C_HAS_ASET, + C_HAS_CE, C_HAS_SCLR, 0, C_HAS_SSET, + "0", C_SYNC_ENABLE, C_SYNC_PRIORITY, 1) + reganeb (.D(intQA_NE_Bpipeend), .CLK(CLK), .CE(CE), .ACLR(ACLR), .ASET(ASET), + .AINIT(AINIT), .SCLR(SCLR), .SSET(SSET), .SINIT(SINIT), + .Q(intQA_NE_B)); + + C_REG_FD_V5_0 #(C_AINIT_VAL, C_ENABLE_RLOCS, C_HAS_ACLR, 0, C_HAS_ASET, + C_HAS_CE, C_HAS_SCLR, 0, C_HAS_SSET, + "0", C_SYNC_ENABLE, C_SYNC_PRIORITY, 1) + regaltb (.D(intQA_LT_Bpipeend), .CLK(CLK), .CE(CE), .ACLR(ACLR), .ASET(ASET), + .AINIT(AINIT), .SCLR(SCLR), .SSET(SSET), .SINIT(SINIT), + .Q(intQA_LT_B)); + + C_REG_FD_V5_0 #(C_AINIT_VAL, C_ENABLE_RLOCS, C_HAS_ACLR, 0, C_HAS_ASET, + C_HAS_CE, C_HAS_SCLR, 0, C_HAS_SSET, + "0", C_SYNC_ENABLE, C_SYNC_PRIORITY, 1) + regagtb (.D(intQA_GT_Bpipeend), .CLK(CLK), .CE(CE), .ACLR(ACLR), .ASET(ASET), + .AINIT(AINIT), .SCLR(SCLR), .SSET(SSET), .SINIT(SINIT), + .Q(intQA_GT_B)); + + C_REG_FD_V5_0 #(C_AINIT_VAL, C_ENABLE_RLOCS, C_HAS_ACLR, 0, C_HAS_ASET, + C_HAS_CE, C_HAS_SCLR, 0, C_HAS_SSET, + "0", C_SYNC_ENABLE, C_SYNC_PRIORITY, 1) + regaleb (.D(intQA_LE_Bpipeend), .CLK(CLK), .CE(CE), .ACLR(ACLR), .ASET(ASET), + .AINIT(AINIT), .SCLR(SCLR), .SSET(SSET), .SINIT(SINIT), + .Q(intQA_LE_B)); + + C_REG_FD_V5_0 #(C_AINIT_VAL, C_ENABLE_RLOCS, C_HAS_ACLR, 0, C_HAS_ASET, + C_HAS_CE, C_HAS_SCLR, 0, C_HAS_SSET, + "0", C_SYNC_ENABLE, C_SYNC_PRIORITY, 1) + regageb (.D(intQA_GE_Bpipeend), .CLK(CLK), .CE(CE), .ACLR(ACLR), .ASET(ASET), + .AINIT(AINIT), .SCLR(SCLR), .SSET(SSET), .SINIT(SINIT), + .Q(intQA_GE_B)); + + initial + begin + #1; + intCE = defval(CE, C_HAS_CE, 1); + intB = defvecval(B, (C_B_CONSTANT == 1) ? 0 : 1, to_bits(C_B_VALUE)); + + intQA_EQ_Bpipe = 'b0; + intQA_NE_Bpipe = 'b0; + intQA_LT_Bpipe = 'b0; + intQA_GT_Bpipe = 'b0; + intQA_LE_Bpipe = 'b0; + intQA_GE_Bpipe = 'b0; + + if(is_X(A) == 1 || is_X(intB) == 1) + begin + notdone = 1; + if((is_X(A) && A === {C_WIDTH{1'bx}}) && (is_X(intB) && intB === {C_WIDTH{1'bx}})) + begin + aeqb <= 1'bx; + aneb <= 1'bx; + altb <= 1'bx; + agtb <= 1'bx; + aleb <= 1'bx; + ageb <= 1'bx; + notdone = 0; + end + else if(C_DATA_TYPE == `c_signed) + begin +/* if(A[C_WIDTH-1] === 1'bx && intB[C_WIDTH-1] === 1'bx) + // Don't know the sign of EITHER data => ALL X's + begin + aeqb <= 1'bx; + aneb <= 1'bx; + altb <= 1'bx; + agtb <= 1'bx; + aleb <= 1'bx; + ageb <= 1'bx; + notdone = 0; + end + else if (A[C_WIDTH-1] !== 1'bx && intB[C_WIDTH-1] !== 1'bx) +*/ if (A[C_WIDTH-1] !== 1'bx && intB[C_WIDTH-1] !== 1'bx) + begin + // The sign bits are both known + if (A[C_WIDTH-1] !== intB[C_WIDTH-1]) + begin + // different signs! + if (A[C_WIDTH-1] === 1'b1) + begin + // A is negative and B is positive + aeqb <= 0; + aneb <= 1; + altb <= 1; + agtb <= 0; + aleb <= 1; + ageb <= 0; + notdone = 0; + end + else // A is +ve and B is -ve + begin + aeqb <= 0; + aneb <= 1; + altb <= 0; + agtb <= 1; + aleb <= 0; + ageb <= 1; + notdone = 0; + end + end + end + end + if (notdone == 1) // check further + begin + // Make copies of A and B with all X's substituted with 0's and 1's + a_low = A; + a_high = A; + b_low = intB; + b_high = intB; + for (i=C_WIDTH-2; i >= 0; i = i - 1) + begin + if (a_low[i] === 1'bx) + begin + a_low[i] = 0; + a_high[i] = 1; + end + if (b_low[i] === 1'bx) + begin + b_low[i] = 0; + b_high[i] = 1; + end + end + // we now (almost - need to check possible sign bits) have worst-case values which must agree on the comparison result + // if that result is not to be unknown... + if (C_DATA_TYPE == `c_signed) + begin + // Set the sign bits of the range values to 0 since + // the sign of the values will be treated separately + a_low[C_WIDTH-1] = 0; + a_high[C_WIDTH-1] = 0; + b_low[C_WIDTH-1] = 0; + b_high[C_WIDTH-1] = 0; + + if((A[C_WIDTH-1] === 1'b1 && intB[C_WIDTH-1] === 1'bx) + || (intB[C_WIDTH-1] === 1'b0 && A[C_WIDTH-1] === 1'bx)) + begin // Sign of A is -ve and sign of B is unknown OR + // sign of B is +ve and sign of A is unknown + // Is A always < B? + if (a_high < b_low) + begin + // A is definitely < than B + aeqb <= 0; + aneb <= 1; + altb <= 1; + agtb <= 0; + aleb <= 1; + ageb <= 0; + end + else if (a_high == b_low) + begin + // A is <= than B + aeqb <= 1'bx; + aneb <= 1'bx; + altb <= 1'bx; + agtb <= 0; + aleb <= 1; + ageb <= 1'bx; + end + else if (a_low != b_low && a_low !== b_high && a_high !== b_low && a_high !== b_high && !(intB === {C_WIDTH{1'bx}} || A === {C_WIDTH{1'bx}})) + begin // Definitely not equal! + aeqb <= 1'b0; + aneb <= 1'b1; + altb <= 1'bx; + agtb <= 1'bx; + aleb <= 1'bx; + ageb <= 1'bx; + end + else // There is > 1 overlap between the ranges so all X's + begin + aeqb <= 1'bx; + aneb <= 1'bx; + altb <= 1'bx; + agtb <= 1'bx; + aleb <= 1'bx; + ageb <= 1'bx; + end + end + else if((A[C_WIDTH-1] === 1'b0 && intB[C_WIDTH-1] === 1'bx) + || (intB[C_WIDTH-1] === 1'b1 && A[C_WIDTH-1] === 1'bx)) + begin // Sign of A is +ve and sign of B is unknown OR + // sign of B is -ve and sign of A is unknown + // Is B always < A? + if (b_high < a_low) + begin + // B is definitely < than A + aeqb <= 0; + aneb <= 1; + altb <= 0; + agtb <= 1; + aleb <= 0; + ageb <= 1; + end + else if (b_high == a_low) + begin + // B is <= than A + aeqb <= 1'bx; + aneb <= 1'bx; + altb <= 0; + agtb <= 1'bx; + aleb <= 1'bx; + ageb <= 1; + end + else if (a_low != b_low && a_low !== b_high && a_high !== b_low && a_high !== b_high && !(intB === {C_WIDTH{1'bx}} || A === {C_WIDTH{1'bx}})) + begin // Definitely not equal! + aeqb <= 1'b0; + aneb <= 1'b1; + altb <= 1'bx; + agtb <= 1'bx; + aleb <= 1'bx; + ageb <= 1'bx; + end + else // There is > 1 overlap between the ranges so all X's + begin + aeqb <= 1'bx; + aneb <= 1'bx; + altb <= 1'bx; + agtb <= 1'bx; + aleb <= 1'bx; + ageb <= 1'bx; + end + end + else // Sign bits on A and B are identical and both are known + begin + if (a_high < b_low) + begin + // A is definitely < than B + aeqb <= 0; + aneb <= 1; + altb <= 1; + agtb <= 0; + aleb <= 1; + ageb <= 0; + end + else if (a_low > b_high) + begin + // A is definitely > than B + aeqb <= 0; + aneb <= 1; + altb <= 0; + agtb <= 1; + aleb <= 0; + ageb <= 1; + end + else if (a_high == b_low) + begin + // A is <= than B + aeqb <= 1'bx; + aneb <= 1'bx; + altb <= 1'bx; + agtb <= 0; + aleb <= 1; + ageb <= 1'bx; + end + else if (a_low == b_high) + begin + // A is >= than B + aeqb <= 1'bx; + aneb <= 1'bx; + altb <= 0; + agtb <= 1'bx; + aleb <= 1'bx; + ageb <= 1; + end + else if (a_low != b_low && a_low !== b_high && a_high !== b_low && a_high !== b_high && !(intB === {C_WIDTH{1'bx}} || A === {C_WIDTH{1'bx}})) + begin // Definitely not equal! + aeqb <= 1'b0; + aneb <= 1'b1; + altb <= 1'bx; + agtb <= 1'bx; + aleb <= 1'bx; + ageb <= 1'bx; + end + else // There is > 1 overlap between the ranges so all X's + begin + aeqb <= 1'bx; + aneb <= 1'bx; + altb <= 1'bx; + agtb <= 1'bx; + aleb <= 1'bx; + ageb <= 1'bx; + end + end + end + else // unsigned data + begin + if (a_low[C_WIDTH-1] === 1'bx) + begin + a_low[C_WIDTH-1] = 0; + a_high[C_WIDTH-1] = 1; + end + if (b_low[C_WIDTH-1] === 1'bx) + begin + b_low[C_WIDTH-1] = 0; + b_high[C_WIDTH-1] = 1; + end + if (a_high < b_low) + begin + // A is definitely < than B + aeqb <= 0; + aneb <= 1; + altb <= 1; + agtb <= 0; + aleb <= 1; + ageb <= 0; + end + else if (a_low > b_high) + begin + // A is definitely > than B + aeqb <= 0; + aneb <= 1; + altb <= 0; + agtb <= 1; + aleb <= 0; + ageb <= 1; + end + else if (a_high == b_low) + begin + // A is <= B + aeqb <= 1'bx; + aneb <= 1'bx; + altb <= 1'bx; + agtb <= 0; + aleb <= 1; + ageb <= 1'bx; + end + else if (a_low == b_high) + begin + // A is >= B + aeqb <= 1'bx; + aneb <= 1'bx; + altb <= 0; + agtb <= 1'bx; + aleb <= 1'bx; + ageb <= 1; + end + else if (a_low != b_low && a_low !== b_high && a_high !== b_low && a_high !== b_high && !(intB === {C_WIDTH{1'bx}} || A === {C_WIDTH{1'bx}})) + begin // Definitely not equal! + aeqb <= 1'b0; + aneb <= 1'b1; + altb <= 1'bx; + agtb <= 1'bx; + aleb <= 1'bx; + ageb <= 1'bx; + end + else // There is > 1 overlap between the ranges so all X's + begin + aeqb <= 1'bx; + aneb <= 1'bx; + altb <= 1'bx; + agtb <= 1'bx; + aleb <= 1'bx; + ageb <= 1'bx; + end + end + end + end + else if (C_DATA_TYPE == `c_signed) + begin + // Signed data so examine MSB and rest separately in some cases + if(A == intB) + begin + aeqb <= 1; + aneb <= 0; + altb <= 0; + agtb <= 0; + end + else if(A[C_WIDTH-1] == intB[C_WIDTH-1]) // Both numbers are -ve or both are +ve + begin + if(A < intB) + begin + aeqb <= 0; + aneb <= 1; + altb <= 1; + agtb <= 0; + end + if(A > intB) + begin + aeqb <= 0; + aneb <= 1; + altb <= 0; + agtb <= 1; + end + end + else if(A[C_WIDTH-1] == 1 && intB[C_WIDTH-1] == 0) // A is -ve, B is +ve + begin + aeqb <= 0; + aneb <= 1; + altb <= 1; + agtb <= 0; + end + else if(A[C_WIDTH-1] == 0 && intB[C_WIDTH-1] == 1) // A is +ve, B is -ve + begin + aeqb <= 0; + aneb <= 1; + altb <= 0; + agtb <= 1; + end + if(aeqb == 1 || altb == 1) + aleb <= 1; + else + aleb <= 0; + if(aeqb == 1 || agtb == 1) + ageb <= 1; + else + ageb <= 0; + end + else // Data is unsigned + begin + if(A == intB) + begin + aeqb <= 1; + aneb <= 0; + altb <= 0; + agtb <= 0; + end + if(A < intB) + begin + aeqb <= 0; + aneb <= 1; + altb <= 1; + agtb <= 0; + end + if(A > intB) + begin + aeqb <= 0; + aneb <= 1; + altb <= 0; + agtb <= 1; + end + if(aeqb == 1 || altb == 1) + aleb <= 1; + else + aleb <= 0; + if(aeqb == 1 || agtb == 1) + ageb <= 1; + else + ageb <= 0; + end + + intA_EQ_B <= #1 aeqb; + intA_NE_B <= #1 aneb; + intA_LT_B <= #1 altb; + intA_GT_B <= #1 agtb; + intA_LE_B <= #1 aleb; + intA_GE_B <= #1 ageb; + + end + + always @(CLK) + lastCLK <= CLK; + + always @(A or B or CE or ACLR or ASET or SCLR or SSET) + begin + intCE = defval(CE, C_HAS_CE, 1); + intB = defvecval(B, (C_B_CONSTANT == 1) ? 0 : 1, to_bits(C_B_VALUE)); + + if(is_X(A) == 1 || is_X(intB) == 1) + begin + notdone = 1; + if((is_X(A) && A === {C_WIDTH{1'bx}}) && (is_X(intB) && intB === {C_WIDTH{1'bx}})) + begin + aeqb = 1'bx; + aneb = 1'bx; + altb = 1'bx; + agtb = 1'bx; + aleb = 1'bx; + ageb = 1'bx; + notdone = 0; + end + else if(C_DATA_TYPE == `c_signed) + begin +/* if(A[C_WIDTH-1] === 1'bx && intB[C_WIDTH-1] === 1'bx) + // Don't know the sign of EITHER data => ALL X's + begin + aeqb = 1'bx; + aneb = 1'bx; + altb = 1'bx; + agtb = 1'bx; + aleb = 1'bx; + ageb = 1'bx; + notdone = 0; + end + else if (A[C_WIDTH-1] !== 1'bx && intB[C_WIDTH-1] !== 1'bx) +*/ if (A[C_WIDTH-1] !== 1'bx && intB[C_WIDTH-1] !== 1'bx) + begin + // The sign bits are both known + if (A[C_WIDTH-1] !== intB[C_WIDTH-1]) + begin + // different signs! + if (A[C_WIDTH-1] === 1'b1) + begin + // A is negative and B is positive + aeqb = 0; + aneb = 1; + altb = 1; + agtb = 0; + aleb = 1; + ageb = 0; + notdone = 0; + end + else // A is +ve and B is -ve + begin + aeqb = 0; + aneb = 1; + altb = 0; + agtb = 1; + aleb = 0; + ageb = 1; + notdone = 0; + end + end + end + end + if (notdone == 1) // check further + begin + // Make copies of A and B with all X's substituted with 0's and 1's + a_low = A; + a_high = A; + b_low = intB; + b_high = intB; + for (i=C_WIDTH-2; i >= 0; i = i - 1) + begin + if (a_low[i] === 1'bx) + begin + a_low[i] = 0; + a_high[i] = 1; + end + if (b_low[i] === 1'bx) + begin + b_low[i] = 0; + b_high[i] = 1; + end + end + // we now (almost - need to check possible sign bits) have worst-case values which must agree on the comparison result + // if that result is not to be unknown... + if (C_DATA_TYPE == `c_signed) + begin + // Set the sign bits of the range values to 0 since + // the sign of the values will be treated separately + a_low[C_WIDTH-1] = 0; + a_high[C_WIDTH-1] = 0; + b_low[C_WIDTH-1] = 0; + b_high[C_WIDTH-1] = 0; + + if((A[C_WIDTH-1] === 1'b1 && intB[C_WIDTH-1] === 1'bx) + || (intB[C_WIDTH-1] === 1'b0 && A[C_WIDTH-1] === 1'bx)) + begin // Sign of A is -ve and sign of B is unknown OR + // sign of B is +ve and sign of A is unknown + // Is A always < B? + if (a_high < b_low) + begin + // A is definitely < than B + aeqb = 0; + aneb = 1; + altb = 1; + agtb = 0; + aleb = 1; + ageb = 0; + end + else if (a_high == b_low) + begin + // A is <= than B + aeqb = 1'bx; + aneb = 1'bx; + altb = 1'bx; + agtb = 0; + aleb = 1; + ageb = 1'bx; + end + else if (a_low != b_low && a_low !== b_high && a_high !== b_low && a_high !== b_high && !(intB === {C_WIDTH{1'bx}} || A === {C_WIDTH{1'bx}})) + begin // Definitely not equal! + aeqb = 1'b0; + aneb = 1'b1; + altb = 1'bx; + agtb = 1'bx; + aleb = 1'bx; + ageb = 1'bx; + end + else // There is > 1 overlap between the ranges so all X's + begin + aeqb = 1'bx; + aneb = 1'bx; + altb = 1'bx; + agtb = 1'bx; + aleb = 1'bx; + ageb = 1'bx; + end + end + else if((A[C_WIDTH-1] === 1'b0 && intB[C_WIDTH-1] === 1'bx) + || (intB[C_WIDTH-1] === 1'b1 && A[C_WIDTH-1] === 1'bx)) + begin // Sign of A is +ve and sign of B is unknown OR + // sign of B is -ve and sign of A is unknown + // Is B always < A? + if (b_high < a_low) + begin + // B is definitely < than A + aeqb = 0; + aneb = 1; + altb = 0; + agtb = 1; + aleb = 0; + ageb = 1; + end + else if (b_high == a_low) + begin + // B is <= than A + aeqb = 1'bx; + aneb = 1'bx; + altb = 0; + agtb = 1'bx; + aleb = 1'bx; + ageb = 1; + end + else if (a_low != b_low && a_low !== b_high && a_high !== b_low && a_high !== b_high && !(intB === {C_WIDTH{1'bx}} || A === {C_WIDTH{1'bx}})) + begin // Definitely not equal! + aeqb = 1'b0; + aneb = 1'b1; + altb = 1'bx; + agtb = 1'bx; + aleb = 1'bx; + ageb = 1'bx; + end + else // There is > 1 overlap between the ranges so all X's + begin + aeqb = 1'bx; + aneb = 1'bx; + altb = 1'bx; + agtb = 1'bx; + aleb = 1'bx; + ageb = 1'bx; + end + end + else // Sign bits on A and B are identical and both are known + begin + if (a_high < b_low) + begin + // A is definitely < than B + aeqb = 0; + aneb = 1; + altb = 1; + agtb = 0; + aleb = 1; + ageb = 0; + end + else if (a_low > b_high) + begin + // A is definitely > than B + aeqb = 0; + aneb = 1; + altb = 0; + agtb = 1; + aleb = 0; + ageb = 1; + end + else if (a_high == b_low) + begin + // A is <= than B + aeqb = 1'bx; + aneb = 1'bx; + altb = 1'bx; + agtb = 0; + aleb = 1; + ageb = 1'bx; + end + else if (a_low == b_high) + begin + // A is >= than B + aeqb = 1'bx; + aneb = 1'bx; + altb = 0; + agtb = 1'bx; + aleb = 1'bx; + ageb = 1; + end + else if (a_low != b_low && a_low !== b_high && a_high !== b_low && a_high !== b_high && !(intB === {C_WIDTH{1'bx}} || A === {C_WIDTH{1'bx}})) + begin // Definitely not equal! + aeqb = 1'b0; + aneb = 1'b1; + altb = 1'bx; + agtb = 1'bx; + aleb = 1'bx; + ageb = 1'bx; + end + else // There is > 1 overlap between the ranges so all X's + begin + aeqb = 1'bx; + aneb = 1'bx; + altb = 1'bx; + agtb = 1'bx; + aleb = 1'bx; + ageb = 1'bx; + end + end + end + else // unsigned data + begin + if (a_low[C_WIDTH-1] === 1'bx) + begin + a_low[C_WIDTH-1] = 0; + a_high[C_WIDTH-1] = 1; + end + if (b_low[C_WIDTH-1] === 1'bx) + begin + b_low[C_WIDTH-1] = 0; + b_high[C_WIDTH-1] = 1; + end + if (a_high < b_low) + begin + // A is definitely < than B + aeqb = 0; + aneb = 1; + altb = 1; + agtb = 0; + aleb = 1; + ageb = 0; + end + else if (a_low > b_high) + begin + // A is definitely > than B + aeqb = 0; + aneb = 1; + altb = 0; + agtb = 1; + aleb = 0; + ageb = 1; + end + else if (a_high == b_low) + begin + // A is <= B + aeqb = 1'bx; + aneb = 1'bx; + altb = 1'bx; + agtb = 0; + aleb = 1; + ageb = 1'bx; + end + else if (a_low == b_high) + begin + // A is >= B + aeqb = 1'bx; + aneb = 1'bx; + altb = 0; + agtb = 1'bx; + aleb = 1'bx; + ageb = 1; + end + else if (a_low != b_low && a_low !== b_high && a_high !== b_low && a_high !== b_high && !(intB === {C_WIDTH{1'bx}} || A === {C_WIDTH{1'bx}})) + begin // Definitely not equal! + aeqb = 1'b0; + aneb = 1'b1; + altb = 1'bx; + agtb = 1'bx; + aleb = 1'bx; + ageb = 1'bx; + end + else // There is > 1 overlap between the ranges so all X's + begin + aeqb = 1'bx; + aneb = 1'bx; + altb = 1'bx; + agtb = 1'bx; + aleb = 1'bx; + ageb = 1'bx; + end + end + end + end + else if (C_DATA_TYPE == `c_signed) + begin + // Signed data so examine MSB and rest separately in some cases + if(A == intB) + begin + aeqb = 1; + aneb = 0; + altb = 0; + agtb = 0; + end + else if(A[C_WIDTH-1] == intB[C_WIDTH-1]) // Both numbers are -ve or both are +ve + begin + if(A < intB) + begin + aeqb = 0; + aneb = 1; + altb = 1; + agtb = 0; + end + if(A > intB) + begin + aeqb = 0; + aneb = 1; + altb = 0; + agtb = 1; + end + end + else if(A[C_WIDTH-1] == 1 && intB[C_WIDTH-1] == 0) // A is -ve, B is +ve + begin + aeqb = 0; + aneb = 1; + altb = 1; + agtb = 0; + end + else if(A[C_WIDTH-1] == 0 && intB[C_WIDTH-1] == 1) // A is +ve, B is -ve + begin + aeqb = 0; + aneb = 1; + altb = 0; + agtb = 1; + end + if(aeqb == 1 || altb == 1) + aleb = 1; + else + aleb = 0; + if(aeqb == 1 || agtb == 1) + ageb = 1; + else + ageb = 0; + end + else // Data is unsigned + begin + if(A == intB) + begin + aeqb = 1; + aneb = 0; + altb = 0; + agtb = 0; + end + if(A < intB) + begin + aeqb = 0; + aneb = 1; + altb = 1; + agtb = 0; + end + if(A > intB) + begin + aeqb = 0; + aneb = 1; + altb = 0; + agtb = 1; + end + if(aeqb == 1 || altb == 1) + aleb = 1; + else + aleb = 0; + if(aeqb == 1 || agtb == 1) + ageb = 1; + else + ageb = 0; + end + + intA_EQ_B <= #1 aeqb; + intA_NE_B <= #1 aneb; + intA_LT_B <= #1 altb; + intA_GT_B <= #1 agtb; + intA_LE_B <= #1 aleb; + intA_GE_B <= #1 ageb; + end + + always@(posedge CLK) + begin + if(CLK === 1'b1 && lastCLK === 1'b0 && intCE === 1'b1) // OK! Update pipelines! + begin + for(pipe = 2; pipe <= C_PIPE_STAGES-1; pipe = pipe + 1) + begin + intQA_EQ_Bpipe[pipe] <= intQA_EQ_Bpipe[pipe+1]; + intQA_NE_Bpipe[pipe] <= intQA_NE_Bpipe[pipe+1]; + intQA_LT_Bpipe[pipe] <= intQA_LT_Bpipe[pipe+1]; + intQA_GT_Bpipe[pipe] <= intQA_GT_Bpipe[pipe+1]; + intQA_LE_Bpipe[pipe] <= intQA_LE_Bpipe[pipe+1]; + intQA_GE_Bpipe[pipe] <= intQA_GE_Bpipe[pipe+1]; + end + intQA_EQ_Bpipe[C_PIPE_STAGES] <= intA_EQ_B; + intQA_NE_Bpipe[C_PIPE_STAGES] <= intA_NE_B; + intQA_LT_Bpipe[C_PIPE_STAGES] <= intA_LT_B; + intQA_GT_Bpipe[C_PIPE_STAGES] <= intA_GT_B; + intQA_LE_Bpipe[C_PIPE_STAGES] <= intA_LE_B; + intQA_GE_Bpipe[C_PIPE_STAGES] <= intA_GE_B; + end + else if((CLK === 1'bx && lastCLK === 1'b0) || (CLK === 1'b1 && lastCLK === 1'bx) || intCE === 1'bx) // POSSIBLY Update pipelines! + begin + for(pipe = 2; pipe <= C_PIPE_STAGES-1; pipe = pipe + 1) + begin + if(intQA_EQ_Bpipe[pipe] !== intQA_EQ_Bpipe[pipe+1]) + intQA_EQ_Bpipe[pipe] <= 1'bx; + if(intQA_NE_Bpipe[pipe] !== intQA_NE_Bpipe[pipe+1]) + intQA_NE_Bpipe[pipe] <= 1'bx; + if(intQA_LT_Bpipe[pipe] !== intQA_LT_Bpipe[pipe+1]) + intQA_LT_Bpipe[pipe] <= 1'bx; + if(intQA_GT_Bpipe[pipe] !== intQA_GT_Bpipe[pipe+1]) + intQA_GT_Bpipe[pipe] <= 1'bx; + if(intQA_LE_Bpipe[pipe] !== intQA_LE_Bpipe[pipe+1]) + intQA_LE_Bpipe[pipe] <= 1'bx; + if(intQA_GE_Bpipe[pipe] !== intQA_GE_Bpipe[pipe+1]) + intQA_GE_Bpipe[pipe] <= 1'bx; + end + if(intQA_EQ_Bpipe[C_PIPE_STAGES] !== intA_EQ_B) + intQA_EQ_Bpipe[C_PIPE_STAGES] <= 1'bx; + if(intQA_NE_Bpipe[C_PIPE_STAGES] !== intA_NE_B) + intQA_NE_Bpipe[C_PIPE_STAGES] <= 1'bx; + if(intQA_LT_Bpipe[C_PIPE_STAGES] !== intA_LT_B) + intQA_LT_Bpipe[C_PIPE_STAGES] <= 1'bx; + if(intQA_GT_Bpipe[C_PIPE_STAGES] !== intA_GT_B) + intQA_GT_Bpipe[C_PIPE_STAGES] <= 1'bx; + if(intQA_LE_Bpipe[C_PIPE_STAGES] !== intA_LE_B) + intQA_LE_Bpipe[C_PIPE_STAGES] <= 1'bx; + if(intQA_GE_Bpipe[C_PIPE_STAGES] !== intA_GE_B) + intQA_GE_Bpipe[C_PIPE_STAGES] <= 1'bx; + end + end + + always@(intA_EQ_B or intQA_EQ_Bpipe[2]) + begin + if(C_PIPE_STAGES < 2) // No pipeline + intQA_EQ_Bpipeend <= intA_EQ_B; + else // Pipeline stages required + begin + intQA_EQ_Bpipeend <= intQA_EQ_Bpipe[2]; + end + end + always@(intA_NE_B or intQA_NE_Bpipe[2]) + begin + if(C_PIPE_STAGES < 2) // No pipeline + intQA_NE_Bpipeend <= intA_NE_B; + else // Pipeline stages required + begin + intQA_NE_Bpipeend <= intQA_NE_Bpipe[2]; + end + end + always@(intA_LT_B or intQA_LT_Bpipe[2]) + begin + if(C_PIPE_STAGES < 2) // No pipeline + intQA_LT_Bpipeend <= intA_LT_B; + else // Pipeline stages required + begin + intQA_LT_Bpipeend <= intQA_LT_Bpipe[2]; + end + end + always@(intA_GT_B or intQA_GT_Bpipe[2]) + begin + if(C_PIPE_STAGES < 2) // No pipeline + intQA_GT_Bpipeend <= intA_GT_B; + else // Pipeline stages required + begin + intQA_GT_Bpipeend <= intQA_GT_Bpipe[2]; + end + end + always@(intA_LE_B or intQA_LE_Bpipe[2]) + begin + if(C_PIPE_STAGES < 2) // No pipeline + intQA_LE_Bpipeend <= intA_LE_B; + else // Pipeline stages required + begin + intQA_LE_Bpipeend <= intQA_LE_Bpipe[2]; + end + end + always@(intA_GE_B or intQA_GE_Bpipe[2]) + begin + if(C_PIPE_STAGES < 2) // No pipeline + intQA_GE_Bpipeend <= intA_GE_B; + else // Pipeline stages required + begin + intQA_GE_Bpipeend <= intQA_GE_Bpipe[2]; + end + end + + function is_X; + input [C_WIDTH-1 : 0] i; + integer j; + begin + is_X = 0; + for(j = 0; j < C_WIDTH; j = j + 1) + if(i[j] === 1'bx) + is_X = 1; + end + endfunction + + function defval; + input i; + input hassig; + input val; + begin + if(hassig == 1) + defval = i; + else + defval = val; + end + endfunction + + function [C_WIDTH - 1 : 0] defvecval; + input [C_WIDTH-1 : 0] i; + input hassig; + input [C_WIDTH-1 : 0] val; + begin + if(hassig == 1) + defvecval = i; + else + defvecval = val; + end + endfunction + + function [C_WIDTH - 1 : 0] to_bits; + input [C_WIDTH*8 : 1] instring; + integer i; + integer non_null_string; + begin + non_null_string = 0; + for(i = C_WIDTH; i > 0; i = i - 1) + begin // Is the string empty? + if(instring[(i*8)] == 0 && + instring[(i*8)-1] == 0 && + instring[(i*8)-2] == 0 && + instring[(i*8)-3] == 0 && + instring[(i*8)-4] == 0 && + instring[(i*8)-5] == 0 && + instring[(i*8)-6] == 0 && + instring[(i*8)-7] == 0 && + non_null_string == 0) + non_null_string = 0; // Use the return value to flag a non-empty string + else + non_null_string = 1; // Non-null character! + end + if(non_null_string == 0) // String IS empty! Just return the value to be all '0's + begin + for(i = C_WIDTH; i > 0; i = i - 1) + to_bits[i-1] = 0; + end + else + begin + for(i = C_WIDTH; i > 0; i = i - 1) + begin // Is this character a '0'? (ASCII = 48 = 00110000) + if(instring[(i*8)] == 0 && + instring[(i*8)-1] == 0 && + instring[(i*8)-2] == 1 && + instring[(i*8)-3] == 1 && + instring[(i*8)-4] == 0 && + instring[(i*8)-5] == 0 && + instring[(i*8)-6] == 0 && + instring[(i*8)-7] == 0) + to_bits[i-1] = 0; + // Or is it a '1'? + else if(instring[(i*8)] == 0 && + instring[(i*8)-1] == 0 && + instring[(i*8)-2] == 1 && + instring[(i*8)-3] == 1 && + instring[(i*8)-4] == 0 && + instring[(i*8)-5] == 0 && + instring[(i*8)-6] == 0 && + instring[(i*8)-7] == 1) + to_bits[i-1] = 1; + // Or is it a ' '? (a null char - in which case insert a '0') + else if(instring[(i*8)] == 0 && + instring[(i*8)-1] == 0 && + instring[(i*8)-2] == 0 && + instring[(i*8)-3] == 0 && + instring[(i*8)-4] == 0 && + instring[(i*8)-5] == 0 && + instring[(i*8)-6] == 0 && + instring[(i*8)-7] == 0) + to_bits[i-1] = 0; + else + begin + $display("Error in %m at time %d ns: non-binary digit in string \"%s\"\nExiting simulation...", $time, instring); + $finish; + end + end + end + end + endfunction + +endmodule + +`undef c_set +`undef c_clear +`undef c_override +`undef c_no_override +`undef c_signed +`undef c_unsigned + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/C_COMPARE_V6_0.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/C_COMPARE_V6_0.v new file mode 100644 index 0000000..f5dcd34 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/C_COMPARE_V6_0.v @@ -0,0 +1,1227 @@ +// Copyright(C) 2002 by Xilinx, Inc. All rights reserved. +// This text contains proprietary, confidential +// information of Xilinx, Inc., is distributed +// under license from Xilinx, Inc., and may be used, +// copied and/or disclosed only pursuant to the terms +// of a valid license agreement with Xilinx, Inc. This copyright +// notice must be retained as part of this text at all times. + + +/* $Id: C_COMPARE_V6_0.v,v 1.16 2008/09/08 20:06:04 akennedy Exp $ +-- +-- Filename - C_COMPARE_V6_0.v +-- Author - Xilinx +-- Creation - 28 Jan 1999 +-- +-- Description - This file contains the Verilog behavior for the Baseblocks C_COMPARE_V6_0 module +*/ + +`timescale 1ns/10ps + +`define c_set 0 +`define c_clear 1 +`define c_override 0 +`define c_no_override 1 +`define c_signed 0 +`define c_unsigned 1 + +module C_COMPARE_V6_0 (A, B, CLK, CE, ACLR, ASET, SCLR, SSET, + A_EQ_B, A_NE_B, A_LT_B, A_GT_B, A_LE_B, A_GE_B, + QA_EQ_B, QA_NE_B, QA_LT_B, QA_GT_B, QA_LE_B, QA_GE_B); + + parameter C_AINIT_VAL = ""; + parameter C_B_CONSTANT = 0; + parameter C_B_VALUE = ""; + parameter C_DATA_TYPE = `c_unsigned; + parameter C_ENABLE_RLOCS = 1; + parameter C_HAS_ACLR = 0; + parameter C_HAS_ASET = 0; + parameter C_HAS_A_EQ_B = 1; + parameter C_HAS_A_GE_B = 0; + parameter C_HAS_A_GT_B = 0; + parameter C_HAS_A_LE_B = 0; + parameter C_HAS_A_LT_B = 0; + parameter C_HAS_A_NE_B = 0; + parameter C_HAS_CE = 0; + parameter C_HAS_QA_EQ_B = 0; + parameter C_HAS_QA_GE_B = 0; + parameter C_HAS_QA_GT_B = 0; + parameter C_HAS_QA_LE_B = 0; + parameter C_HAS_QA_LT_B = 0; + parameter C_HAS_QA_NE_B = 0; + parameter C_HAS_SCLR = 0; + parameter C_HAS_SSET = 0; + parameter C_PIPE_STAGES = 1; + parameter C_SYNC_ENABLE = `c_override; + parameter C_SYNC_PRIORITY = `c_clear; + parameter C_WIDTH = 16; + + + input [C_WIDTH-1 : 0] A; + input [C_WIDTH-1 : 0] B; + input CLK; + input CE; + input ACLR; + input ASET; + input SCLR; + input SSET; + output A_EQ_B; + output A_NE_B; + output A_LT_B; + output A_GT_B; + output A_LE_B; + output A_GE_B; + output QA_EQ_B; + output QA_NE_B; + output QA_LT_B; + output QA_GT_B; + output QA_LE_B; + output QA_GE_B; + + // Internal values to drive signals when input is missing + reg [C_WIDTH-1 : 0] intB; + reg intCE; + reg intACLR; + reg intASET; + reg intSCLR; + reg intSSET; + reg intA_EQ_B; + reg intA_NE_B; + reg intA_LT_B; + reg intA_GT_B; + reg intA_LE_B; + reg intA_GE_B; + wire intQA_EQ_B; + wire intQA_NE_B; + wire intQA_LT_B; + wire intQA_GT_B; + wire intQA_LE_B; + wire intQA_GE_B; + reg lastCLK; + + reg [C_PIPE_STAGES+2 : 0] intQA_EQ_Bpipe; + reg intQA_EQ_Bpipeend; + reg [C_PIPE_STAGES+2 : 0] intQA_NE_Bpipe; + reg intQA_NE_Bpipeend; + reg [C_PIPE_STAGES+2 : 0] intQA_LT_Bpipe; + reg intQA_LT_Bpipeend; + reg [C_PIPE_STAGES+2 : 0] intQA_GT_Bpipe; + reg intQA_GT_Bpipeend; + reg [C_PIPE_STAGES+2 : 0] intQA_LE_Bpipe; + reg intQA_LE_Bpipeend; + reg [C_PIPE_STAGES+2 : 0] intQA_GE_Bpipe; + reg intQA_GE_Bpipeend; + + wire AINIT; + wire SINIT; + + wire A_EQ_B = (C_HAS_A_EQ_B == 1 ? intA_EQ_B : 1'bx); + wire A_NE_B = (C_HAS_A_NE_B == 1 ? intA_NE_B : 1'bx); + wire A_LT_B = (C_HAS_A_LT_B == 1 ? intA_LT_B : 1'bx); + wire A_GT_B = (C_HAS_A_GT_B == 1 ? intA_GT_B : 1'bx); + wire A_LE_B = (C_HAS_A_LE_B == 1 ? intA_LE_B : 1'bx); + wire A_GE_B = (C_HAS_A_GE_B == 1 ? intA_GE_B : 1'bx); + wire QA_EQ_B = (C_HAS_QA_EQ_B == 1 ? intQA_EQ_B : 1'bx); + wire QA_NE_B = (C_HAS_QA_NE_B == 1 ? intQA_NE_B : 1'bx); + wire QA_LT_B = (C_HAS_QA_LT_B == 1 ? intQA_LT_B : 1'bx); + wire QA_GT_B = (C_HAS_QA_GT_B == 1 ? intQA_GT_B : 1'bx); + wire QA_LE_B = (C_HAS_QA_LE_B == 1 ? intQA_LE_B : 1'bx); + wire QA_GE_B = (C_HAS_QA_GE_B == 1 ? intQA_GE_B : 1'bx); + + integer pipe, notdone, i; + + reg aeqb, aneb, altb, agtb, aleb, ageb; + reg [C_WIDTH-1:0] a_low; + reg [C_WIDTH-1:0] a_high; + reg [C_WIDTH-1:0] b_low; + reg [C_WIDTH-1:0] b_high; + + // Instance the required output regs + C_REG_FD_V6_0 #(C_AINIT_VAL, C_ENABLE_RLOCS, C_HAS_ACLR, 0, C_HAS_ASET, + C_HAS_CE, C_HAS_SCLR, 0, C_HAS_SSET, + "0", C_SYNC_ENABLE, C_SYNC_PRIORITY, 1) + regaeqb (.D(intQA_EQ_Bpipeend), .CLK(CLK), .CE(CE), .ACLR(ACLR), .ASET(ASET), + .AINIT(AINIT), .SCLR(SCLR), .SSET(SSET), .SINIT(SINIT), + .Q(intQA_EQ_B)); + + C_REG_FD_V6_0 #(C_AINIT_VAL, C_ENABLE_RLOCS, C_HAS_ACLR, 0, C_HAS_ASET, + C_HAS_CE, C_HAS_SCLR, 0, C_HAS_SSET, + "0", C_SYNC_ENABLE, C_SYNC_PRIORITY, 1) + reganeb (.D(intQA_NE_Bpipeend), .CLK(CLK), .CE(CE), .ACLR(ACLR), .ASET(ASET), + .AINIT(AINIT), .SCLR(SCLR), .SSET(SSET), .SINIT(SINIT), + .Q(intQA_NE_B)); + + C_REG_FD_V6_0 #(C_AINIT_VAL, C_ENABLE_RLOCS, C_HAS_ACLR, 0, C_HAS_ASET, + C_HAS_CE, C_HAS_SCLR, 0, C_HAS_SSET, + "0", C_SYNC_ENABLE, C_SYNC_PRIORITY, 1) + regaltb (.D(intQA_LT_Bpipeend), .CLK(CLK), .CE(CE), .ACLR(ACLR), .ASET(ASET), + .AINIT(AINIT), .SCLR(SCLR), .SSET(SSET), .SINIT(SINIT), + .Q(intQA_LT_B)); + + C_REG_FD_V6_0 #(C_AINIT_VAL, C_ENABLE_RLOCS, C_HAS_ACLR, 0, C_HAS_ASET, + C_HAS_CE, C_HAS_SCLR, 0, C_HAS_SSET, + "0", C_SYNC_ENABLE, C_SYNC_PRIORITY, 1) + regagtb (.D(intQA_GT_Bpipeend), .CLK(CLK), .CE(CE), .ACLR(ACLR), .ASET(ASET), + .AINIT(AINIT), .SCLR(SCLR), .SSET(SSET), .SINIT(SINIT), + .Q(intQA_GT_B)); + + C_REG_FD_V6_0 #(C_AINIT_VAL, C_ENABLE_RLOCS, C_HAS_ACLR, 0, C_HAS_ASET, + C_HAS_CE, C_HAS_SCLR, 0, C_HAS_SSET, + "0", C_SYNC_ENABLE, C_SYNC_PRIORITY, 1) + regaleb (.D(intQA_LE_Bpipeend), .CLK(CLK), .CE(CE), .ACLR(ACLR), .ASET(ASET), + .AINIT(AINIT), .SCLR(SCLR), .SSET(SSET), .SINIT(SINIT), + .Q(intQA_LE_B)); + + C_REG_FD_V6_0 #(C_AINIT_VAL, C_ENABLE_RLOCS, C_HAS_ACLR, 0, C_HAS_ASET, + C_HAS_CE, C_HAS_SCLR, 0, C_HAS_SSET, + "0", C_SYNC_ENABLE, C_SYNC_PRIORITY, 1) + regageb (.D(intQA_GE_Bpipeend), .CLK(CLK), .CE(CE), .ACLR(ACLR), .ASET(ASET), + .AINIT(AINIT), .SCLR(SCLR), .SSET(SSET), .SINIT(SINIT), + .Q(intQA_GE_B)); + + initial + begin + #1; + intCE = defval(CE, C_HAS_CE, 1); + intB = defvecval(B, (C_B_CONSTANT == 1) ? 0 : 1, to_bits(C_B_VALUE)); + + intQA_EQ_Bpipe = 'b0; + intQA_NE_Bpipe = 'b0; + intQA_LT_Bpipe = 'b0; + intQA_GT_Bpipe = 'b0; + intQA_LE_Bpipe = 'b0; + intQA_GE_Bpipe = 'b0; + + if(is_X(A) == 1 || is_X(intB) == 1) + begin + notdone = 1; + if((is_X(A) && A === {C_WIDTH{1'bx}}) && (is_X(intB) && intB === {C_WIDTH{1'bx}})) + begin + aeqb <= 1'bx; + aneb <= 1'bx; + altb <= 1'bx; + agtb <= 1'bx; + aleb <= 1'bx; + ageb <= 1'bx; + notdone = 0; + end + else if(C_DATA_TYPE == `c_signed) + begin +/* if(A[C_WIDTH-1] === 1'bx && intB[C_WIDTH-1] === 1'bx) + // Don't know the sign of EITHER data => ALL X's + begin + aeqb <= 1'bx; + aneb <= 1'bx; + altb <= 1'bx; + agtb <= 1'bx; + aleb <= 1'bx; + ageb <= 1'bx; + notdone = 0; + end + else if (A[C_WIDTH-1] !== 1'bx && intB[C_WIDTH-1] !== 1'bx) +*/ if (A[C_WIDTH-1] !== 1'bx && intB[C_WIDTH-1] !== 1'bx) + begin + // The sign bits are both known + if (A[C_WIDTH-1] !== intB[C_WIDTH-1]) + begin + // different signs! + if (A[C_WIDTH-1] === 1'b1) + begin + // A is negative and B is positive + aeqb <= 0; + aneb <= 1; + altb <= 1; + agtb <= 0; + aleb <= 1; + ageb <= 0; + notdone = 0; + end + else // A is +ve and B is -ve + begin + aeqb <= 0; + aneb <= 1; + altb <= 0; + agtb <= 1; + aleb <= 0; + ageb <= 1; + notdone = 0; + end + end + end + end + if (notdone == 1) // check further + begin + // Make copies of A and B with all X's substituted with 0's and 1's + a_low = A; + a_high = A; + b_low = intB; + b_high = intB; + for (i=C_WIDTH-2; i >= 0; i = i - 1) + begin + if (a_low[i] === 1'bx) + begin + a_low[i] = 0; + a_high[i] = 1; + end + if (b_low[i] === 1'bx) + begin + b_low[i] = 0; + b_high[i] = 1; + end + end + // we now (almost - need to check possible sign bits) have worst-case values which must agree on the comparison result + // if that result is not to be unknown... + if (C_DATA_TYPE == `c_signed) + begin + // Set the sign bits of the range values to 0 since + // the sign of the values will be treated separately + a_low[C_WIDTH-1] = 0; + a_high[C_WIDTH-1] = 0; + b_low[C_WIDTH-1] = 0; + b_high[C_WIDTH-1] = 0; + + if((A[C_WIDTH-1] === 1'b1 && intB[C_WIDTH-1] === 1'bx) + || (intB[C_WIDTH-1] === 1'b0 && A[C_WIDTH-1] === 1'bx)) + begin // Sign of A is -ve and sign of B is unknown OR + // sign of B is +ve and sign of A is unknown + // Is A always < B? + if (a_high < b_low) + begin + // A is definitely < than B + aeqb <= 0; + aneb <= 1; + altb <= 1; + agtb <= 0; + aleb <= 1; + ageb <= 0; + end + else if (a_high == b_low) + begin + // A is <= than B + aeqb <= 1'bx; + aneb <= 1'bx; + altb <= 1'bx; + agtb <= 0; + aleb <= 1; + ageb <= 1'bx; + end + else if (a_low != b_low && a_low !== b_high && a_high !== b_low && a_high !== b_high && !(intB === {C_WIDTH{1'bx}} || A === {C_WIDTH{1'bx}})) + begin // Definitely not equal! + aeqb <= 1'b0; + aneb <= 1'b1; + altb <= 1'bx; + agtb <= 1'bx; + aleb <= 1'bx; + ageb <= 1'bx; + end + else // There is > 1 overlap between the ranges so all X's + begin + aeqb <= 1'bx; + aneb <= 1'bx; + altb <= 1'bx; + agtb <= 1'bx; + aleb <= 1'bx; + ageb <= 1'bx; + end + end + else if((A[C_WIDTH-1] === 1'b0 && intB[C_WIDTH-1] === 1'bx) + || (intB[C_WIDTH-1] === 1'b1 && A[C_WIDTH-1] === 1'bx)) + begin // Sign of A is +ve and sign of B is unknown OR + // sign of B is -ve and sign of A is unknown + // Is B always < A? + if (b_high < a_low) + begin + // B is definitely < than A + aeqb <= 0; + aneb <= 1; + altb <= 0; + agtb <= 1; + aleb <= 0; + ageb <= 1; + end + else if (b_high == a_low) + begin + // B is <= than A + aeqb <= 1'bx; + aneb <= 1'bx; + altb <= 0; + agtb <= 1'bx; + aleb <= 1'bx; + ageb <= 1; + end + else if (a_low != b_low && a_low !== b_high && a_high !== b_low && a_high !== b_high && !(intB === {C_WIDTH{1'bx}} || A === {C_WIDTH{1'bx}})) + begin // Definitely not equal! + aeqb <= 1'b0; + aneb <= 1'b1; + altb <= 1'bx; + agtb <= 1'bx; + aleb <= 1'bx; + ageb <= 1'bx; + end + else // There is > 1 overlap between the ranges so all X's + begin + aeqb <= 1'bx; + aneb <= 1'bx; + altb <= 1'bx; + agtb <= 1'bx; + aleb <= 1'bx; + ageb <= 1'bx; + end + end + else // Sign bits on A and B are identical and both are known + begin + if (a_high < b_low) + begin + // A is definitely < than B + aeqb <= 0; + aneb <= 1; + altb <= 1; + agtb <= 0; + aleb <= 1; + ageb <= 0; + end + else if (a_low > b_high) + begin + // A is definitely > than B + aeqb <= 0; + aneb <= 1; + altb <= 0; + agtb <= 1; + aleb <= 0; + ageb <= 1; + end + else if (a_high == b_low) + begin + // A is <= than B + aeqb <= 1'bx; + aneb <= 1'bx; + altb <= 1'bx; + agtb <= 0; + aleb <= 1; + ageb <= 1'bx; + end + else if (a_low == b_high) + begin + // A is >= than B + aeqb <= 1'bx; + aneb <= 1'bx; + altb <= 0; + agtb <= 1'bx; + aleb <= 1'bx; + ageb <= 1; + end + else if (a_low != b_low && a_low !== b_high && a_high !== b_low && a_high !== b_high && !(intB === {C_WIDTH{1'bx}} || A === {C_WIDTH{1'bx}})) + begin // Definitely not equal! + aeqb <= 1'b0; + aneb <= 1'b1; + altb <= 1'bx; + agtb <= 1'bx; + aleb <= 1'bx; + ageb <= 1'bx; + end + else // There is > 1 overlap between the ranges so all X's + begin + aeqb <= 1'bx; + aneb <= 1'bx; + altb <= 1'bx; + agtb <= 1'bx; + aleb <= 1'bx; + ageb <= 1'bx; + end + end + end + else // unsigned data + begin + if (a_low[C_WIDTH-1] === 1'bx) + begin + a_low[C_WIDTH-1] = 0; + a_high[C_WIDTH-1] = 1; + end + if (b_low[C_WIDTH-1] === 1'bx) + begin + b_low[C_WIDTH-1] = 0; + b_high[C_WIDTH-1] = 1; + end + if (a_high < b_low) + begin + // A is definitely < than B + aeqb <= 0; + aneb <= 1; + altb <= 1; + agtb <= 0; + aleb <= 1; + ageb <= 0; + end + else if (a_low > b_high) + begin + // A is definitely > than B + aeqb <= 0; + aneb <= 1; + altb <= 0; + agtb <= 1; + aleb <= 0; + ageb <= 1; + end + else if (a_high == b_low) + begin + // A is <= B + aeqb <= 1'bx; + aneb <= 1'bx; + altb <= 1'bx; + agtb <= 0; + aleb <= 1; + ageb <= 1'bx; + end + else if (a_low == b_high) + begin + // A is >= B + aeqb <= 1'bx; + aneb <= 1'bx; + altb <= 0; + agtb <= 1'bx; + aleb <= 1'bx; + ageb <= 1; + end + else if (a_low != b_low && a_low !== b_high && a_high !== b_low && a_high !== b_high && !(intB === {C_WIDTH{1'bx}} || A === {C_WIDTH{1'bx}})) + begin // Definitely not equal! + aeqb <= 1'b0; + aneb <= 1'b1; + altb <= 1'bx; + agtb <= 1'bx; + aleb <= 1'bx; + ageb <= 1'bx; + end + else // There is > 1 overlap between the ranges so all X's + begin + aeqb <= 1'bx; + aneb <= 1'bx; + altb <= 1'bx; + agtb <= 1'bx; + aleb <= 1'bx; + ageb <= 1'bx; + end + end + end + end + else if (C_DATA_TYPE == `c_signed) + begin + // Signed data so examine MSB and rest separately in some cases + if(A == intB) + begin + aeqb <= 1; + aneb <= 0; + altb <= 0; + agtb <= 0; + end + else if(A[C_WIDTH-1] == intB[C_WIDTH-1]) // Both numbers are -ve or both are +ve + begin + if(A < intB) + begin + aeqb <= 0; + aneb <= 1; + altb <= 1; + agtb <= 0; + end + if(A > intB) + begin + aeqb <= 0; + aneb <= 1; + altb <= 0; + agtb <= 1; + end + end + else if(A[C_WIDTH-1] == 1 && intB[C_WIDTH-1] == 0) // A is -ve, B is +ve + begin + aeqb <= 0; + aneb <= 1; + altb <= 1; + agtb <= 0; + end + else if(A[C_WIDTH-1] == 0 && intB[C_WIDTH-1] == 1) // A is +ve, B is -ve + begin + aeqb <= 0; + aneb <= 1; + altb <= 0; + agtb <= 1; + end + if(aeqb == 1 || altb == 1) + aleb <= 1; + else + aleb <= 0; + if(aeqb == 1 || agtb == 1) + ageb <= 1; + else + ageb <= 0; + end + else // Data is unsigned + begin + if(A == intB) + begin + aeqb <= 1; + aneb <= 0; + altb <= 0; + agtb <= 0; + end + if(A < intB) + begin + aeqb <= 0; + aneb <= 1; + altb <= 1; + agtb <= 0; + end + if(A > intB) + begin + aeqb <= 0; + aneb <= 1; + altb <= 0; + agtb <= 1; + end + if(aeqb == 1 || altb == 1) + aleb <= 1; + else + aleb <= 0; + if(aeqb == 1 || agtb == 1) + ageb <= 1; + else + ageb <= 0; + end + + intA_EQ_B <= #1 aeqb; + intA_NE_B <= #1 aneb; + intA_LT_B <= #1 altb; + intA_GT_B <= #1 agtb; + intA_LE_B <= #1 aleb; + intA_GE_B <= #1 ageb; + + end + + always @(CLK) + lastCLK <= CLK; + + always @(A or B or CE or ACLR or ASET or SCLR or SSET) + begin + intCE = defval(CE, C_HAS_CE, 1); + intB = defvecval(B, (C_B_CONSTANT == 1) ? 0 : 1, to_bits(C_B_VALUE)); + + if(is_X(A) == 1 || is_X(intB) == 1) + begin + notdone = 1; + if((is_X(A) && A === {C_WIDTH{1'bx}}) && (is_X(intB) && intB === {C_WIDTH{1'bx}})) + begin + aeqb = 1'bx; + aneb = 1'bx; + altb = 1'bx; + agtb = 1'bx; + aleb = 1'bx; + ageb = 1'bx; + notdone = 0; + end + else if(C_DATA_TYPE == `c_signed) + begin +/* if(A[C_WIDTH-1] === 1'bx && intB[C_WIDTH-1] === 1'bx) + // Don't know the sign of EITHER data => ALL X's + begin + aeqb = 1'bx; + aneb = 1'bx; + altb = 1'bx; + agtb = 1'bx; + aleb = 1'bx; + ageb = 1'bx; + notdone = 0; + end + else if (A[C_WIDTH-1] !== 1'bx && intB[C_WIDTH-1] !== 1'bx) +*/ if (A[C_WIDTH-1] !== 1'bx && intB[C_WIDTH-1] !== 1'bx) + begin + // The sign bits are both known + if (A[C_WIDTH-1] !== intB[C_WIDTH-1]) + begin + // different signs! + if (A[C_WIDTH-1] === 1'b1) + begin + // A is negative and B is positive + aeqb = 0; + aneb = 1; + altb = 1; + agtb = 0; + aleb = 1; + ageb = 0; + notdone = 0; + end + else // A is +ve and B is -ve + begin + aeqb = 0; + aneb = 1; + altb = 0; + agtb = 1; + aleb = 0; + ageb = 1; + notdone = 0; + end + end + end + end + if (notdone == 1) // check further + begin + // Make copies of A and B with all X's substituted with 0's and 1's + a_low = A; + a_high = A; + b_low = intB; + b_high = intB; + for (i=C_WIDTH-2; i >= 0; i = i - 1) + begin + if (a_low[i] === 1'bx) + begin + a_low[i] = 0; + a_high[i] = 1; + end + if (b_low[i] === 1'bx) + begin + b_low[i] = 0; + b_high[i] = 1; + end + end + // we now (almost - need to check possible sign bits) have worst-case values which must agree on the comparison result + // if that result is not to be unknown... + if (C_DATA_TYPE == `c_signed) + begin + // Set the sign bits of the range values to 0 since + // the sign of the values will be treated separately + a_low[C_WIDTH-1] = 0; + a_high[C_WIDTH-1] = 0; + b_low[C_WIDTH-1] = 0; + b_high[C_WIDTH-1] = 0; + + if((A[C_WIDTH-1] === 1'b1 && intB[C_WIDTH-1] === 1'bx) + || (intB[C_WIDTH-1] === 1'b0 && A[C_WIDTH-1] === 1'bx)) + begin // Sign of A is -ve and sign of B is unknown OR + // sign of B is +ve and sign of A is unknown + // Is A always < B? + if (a_high < b_low) + begin + // A is definitely < than B + aeqb = 0; + aneb = 1; + altb = 1; + agtb = 0; + aleb = 1; + ageb = 0; + end + else if (a_high == b_low) + begin + // A is <= than B + aeqb = 1'bx; + aneb = 1'bx; + altb = 1'bx; + agtb = 0; + aleb = 1; + ageb = 1'bx; + end + else if (a_low != b_low && a_low !== b_high && a_high !== b_low && a_high !== b_high && !(intB === {C_WIDTH{1'bx}} || A === {C_WIDTH{1'bx}})) + begin // Definitely not equal! + aeqb = 1'b0; + aneb = 1'b1; + altb = 1'bx; + agtb = 1'bx; + aleb = 1'bx; + ageb = 1'bx; + end + else // There is > 1 overlap between the ranges so all X's + begin + aeqb = 1'bx; + aneb = 1'bx; + altb = 1'bx; + agtb = 1'bx; + aleb = 1'bx; + ageb = 1'bx; + end + end + else if((A[C_WIDTH-1] === 1'b0 && intB[C_WIDTH-1] === 1'bx) + || (intB[C_WIDTH-1] === 1'b1 && A[C_WIDTH-1] === 1'bx)) + begin // Sign of A is +ve and sign of B is unknown OR + // sign of B is -ve and sign of A is unknown + // Is B always < A? + if (b_high < a_low) + begin + // B is definitely < than A + aeqb = 0; + aneb = 1; + altb = 0; + agtb = 1; + aleb = 0; + ageb = 1; + end + else if (b_high == a_low) + begin + // B is <= than A + aeqb = 1'bx; + aneb = 1'bx; + altb = 0; + agtb = 1'bx; + aleb = 1'bx; + ageb = 1; + end + else if (a_low != b_low && a_low !== b_high && a_high !== b_low && a_high !== b_high && !(intB === {C_WIDTH{1'bx}} || A === {C_WIDTH{1'bx}})) + begin // Definitely not equal! + aeqb = 1'b0; + aneb = 1'b1; + altb = 1'bx; + agtb = 1'bx; + aleb = 1'bx; + ageb = 1'bx; + end + else // There is > 1 overlap between the ranges so all X's + begin + aeqb = 1'bx; + aneb = 1'bx; + altb = 1'bx; + agtb = 1'bx; + aleb = 1'bx; + ageb = 1'bx; + end + end + else // Sign bits on A and B are identical and both are known + begin + if (a_high < b_low) + begin + // A is definitely < than B + aeqb = 0; + aneb = 1; + altb = 1; + agtb = 0; + aleb = 1; + ageb = 0; + end + else if (a_low > b_high) + begin + // A is definitely > than B + aeqb = 0; + aneb = 1; + altb = 0; + agtb = 1; + aleb = 0; + ageb = 1; + end + else if (a_high == b_low) + begin + // A is <= than B + aeqb = 1'bx; + aneb = 1'bx; + altb = 1'bx; + agtb = 0; + aleb = 1; + ageb = 1'bx; + end + else if (a_low == b_high) + begin + // A is >= than B + aeqb = 1'bx; + aneb = 1'bx; + altb = 0; + agtb = 1'bx; + aleb = 1'bx; + ageb = 1; + end + else if (a_low != b_low && a_low !== b_high && a_high !== b_low && a_high !== b_high && !(intB === {C_WIDTH{1'bx}} || A === {C_WIDTH{1'bx}})) + begin // Definitely not equal! + aeqb = 1'b0; + aneb = 1'b1; + altb = 1'bx; + agtb = 1'bx; + aleb = 1'bx; + ageb = 1'bx; + end + else // There is > 1 overlap between the ranges so all X's + begin + aeqb = 1'bx; + aneb = 1'bx; + altb = 1'bx; + agtb = 1'bx; + aleb = 1'bx; + ageb = 1'bx; + end + end + end + else // unsigned data + begin + if (a_low[C_WIDTH-1] === 1'bx) + begin + a_low[C_WIDTH-1] = 0; + a_high[C_WIDTH-1] = 1; + end + if (b_low[C_WIDTH-1] === 1'bx) + begin + b_low[C_WIDTH-1] = 0; + b_high[C_WIDTH-1] = 1; + end + if (a_high < b_low) + begin + // A is definitely < than B + aeqb = 0; + aneb = 1; + altb = 1; + agtb = 0; + aleb = 1; + ageb = 0; + end + else if (a_low > b_high) + begin + // A is definitely > than B + aeqb = 0; + aneb = 1; + altb = 0; + agtb = 1; + aleb = 0; + ageb = 1; + end + else if (a_high == b_low) + begin + // A is <= B + aeqb = 1'bx; + aneb = 1'bx; + altb = 1'bx; + agtb = 0; + aleb = 1; + ageb = 1'bx; + end + else if (a_low == b_high) + begin + // A is >= B + aeqb = 1'bx; + aneb = 1'bx; + altb = 0; + agtb = 1'bx; + aleb = 1'bx; + ageb = 1; + end + else if (a_low != b_low && a_low !== b_high && a_high !== b_low && a_high !== b_high && !(intB === {C_WIDTH{1'bx}} || A === {C_WIDTH{1'bx}})) + begin // Definitely not equal! + aeqb = 1'b0; + aneb = 1'b1; + altb = 1'bx; + agtb = 1'bx; + aleb = 1'bx; + ageb = 1'bx; + end + else // There is > 1 overlap between the ranges so all X's + begin + aeqb = 1'bx; + aneb = 1'bx; + altb = 1'bx; + agtb = 1'bx; + aleb = 1'bx; + ageb = 1'bx; + end + end + end + end + else if (C_DATA_TYPE == `c_signed) + begin + // Signed data so examine MSB and rest separately in some cases + if(A == intB) + begin + aeqb = 1; + aneb = 0; + altb = 0; + agtb = 0; + end + else if(A[C_WIDTH-1] == intB[C_WIDTH-1]) // Both numbers are -ve or both are +ve + begin + if(A < intB) + begin + aeqb = 0; + aneb = 1; + altb = 1; + agtb = 0; + end + if(A > intB) + begin + aeqb = 0; + aneb = 1; + altb = 0; + agtb = 1; + end + end + else if(A[C_WIDTH-1] == 1 && intB[C_WIDTH-1] == 0) // A is -ve, B is +ve + begin + aeqb = 0; + aneb = 1; + altb = 1; + agtb = 0; + end + else if(A[C_WIDTH-1] == 0 && intB[C_WIDTH-1] == 1) // A is +ve, B is -ve + begin + aeqb = 0; + aneb = 1; + altb = 0; + agtb = 1; + end + if(aeqb == 1 || altb == 1) + aleb = 1; + else + aleb = 0; + if(aeqb == 1 || agtb == 1) + ageb = 1; + else + ageb = 0; + end + else // Data is unsigned + begin + if(A == intB) + begin + aeqb = 1; + aneb = 0; + altb = 0; + agtb = 0; + end + if(A < intB) + begin + aeqb = 0; + aneb = 1; + altb = 1; + agtb = 0; + end + if(A > intB) + begin + aeqb = 0; + aneb = 1; + altb = 0; + agtb = 1; + end + if(aeqb == 1 || altb == 1) + aleb = 1; + else + aleb = 0; + if(aeqb == 1 || agtb == 1) + ageb = 1; + else + ageb = 0; + end + + intA_EQ_B <= #1 aeqb; + intA_NE_B <= #1 aneb; + intA_LT_B <= #1 altb; + intA_GT_B <= #1 agtb; + intA_LE_B <= #1 aleb; + intA_GE_B <= #1 ageb; + end + + always@(posedge CLK) + begin + if(CLK === 1'b1 && lastCLK === 1'b0 && intCE === 1'b1) // OK! Update pipelines! + begin + for(pipe = 2; pipe <= C_PIPE_STAGES-1; pipe = pipe + 1) + begin + intQA_EQ_Bpipe[pipe] <= intQA_EQ_Bpipe[pipe+1]; + intQA_NE_Bpipe[pipe] <= intQA_NE_Bpipe[pipe+1]; + intQA_LT_Bpipe[pipe] <= intQA_LT_Bpipe[pipe+1]; + intQA_GT_Bpipe[pipe] <= intQA_GT_Bpipe[pipe+1]; + intQA_LE_Bpipe[pipe] <= intQA_LE_Bpipe[pipe+1]; + intQA_GE_Bpipe[pipe] <= intQA_GE_Bpipe[pipe+1]; + end + intQA_EQ_Bpipe[C_PIPE_STAGES] <= intA_EQ_B; + intQA_NE_Bpipe[C_PIPE_STAGES] <= intA_NE_B; + intQA_LT_Bpipe[C_PIPE_STAGES] <= intA_LT_B; + intQA_GT_Bpipe[C_PIPE_STAGES] <= intA_GT_B; + intQA_LE_Bpipe[C_PIPE_STAGES] <= intA_LE_B; + intQA_GE_Bpipe[C_PIPE_STAGES] <= intA_GE_B; + end + else if((CLK === 1'bx && lastCLK === 1'b0) || (CLK === 1'b1 && lastCLK === 1'bx) || intCE === 1'bx) // POSSIBLY Update pipelines! + begin + for(pipe = 2; pipe <= C_PIPE_STAGES-1; pipe = pipe + 1) + begin + if(intQA_EQ_Bpipe[pipe] !== intQA_EQ_Bpipe[pipe+1]) + intQA_EQ_Bpipe[pipe] <= 1'bx; + if(intQA_NE_Bpipe[pipe] !== intQA_NE_Bpipe[pipe+1]) + intQA_NE_Bpipe[pipe] <= 1'bx; + if(intQA_LT_Bpipe[pipe] !== intQA_LT_Bpipe[pipe+1]) + intQA_LT_Bpipe[pipe] <= 1'bx; + if(intQA_GT_Bpipe[pipe] !== intQA_GT_Bpipe[pipe+1]) + intQA_GT_Bpipe[pipe] <= 1'bx; + if(intQA_LE_Bpipe[pipe] !== intQA_LE_Bpipe[pipe+1]) + intQA_LE_Bpipe[pipe] <= 1'bx; + if(intQA_GE_Bpipe[pipe] !== intQA_GE_Bpipe[pipe+1]) + intQA_GE_Bpipe[pipe] <= 1'bx; + end + if(intQA_EQ_Bpipe[C_PIPE_STAGES] !== intA_EQ_B) + intQA_EQ_Bpipe[C_PIPE_STAGES] <= 1'bx; + if(intQA_NE_Bpipe[C_PIPE_STAGES] !== intA_NE_B) + intQA_NE_Bpipe[C_PIPE_STAGES] <= 1'bx; + if(intQA_LT_Bpipe[C_PIPE_STAGES] !== intA_LT_B) + intQA_LT_Bpipe[C_PIPE_STAGES] <= 1'bx; + if(intQA_GT_Bpipe[C_PIPE_STAGES] !== intA_GT_B) + intQA_GT_Bpipe[C_PIPE_STAGES] <= 1'bx; + if(intQA_LE_Bpipe[C_PIPE_STAGES] !== intA_LE_B) + intQA_LE_Bpipe[C_PIPE_STAGES] <= 1'bx; + if(intQA_GE_Bpipe[C_PIPE_STAGES] !== intA_GE_B) + intQA_GE_Bpipe[C_PIPE_STAGES] <= 1'bx; + end + end + + always@(intA_EQ_B or intQA_EQ_Bpipe[2]) + begin + if(C_PIPE_STAGES < 2) // No pipeline + intQA_EQ_Bpipeend <= intA_EQ_B; + else // Pipeline stages required + begin + intQA_EQ_Bpipeend <= intQA_EQ_Bpipe[2]; + end + end + always@(intA_NE_B or intQA_NE_Bpipe[2]) + begin + if(C_PIPE_STAGES < 2) // No pipeline + intQA_NE_Bpipeend <= intA_NE_B; + else // Pipeline stages required + begin + intQA_NE_Bpipeend <= intQA_NE_Bpipe[2]; + end + end + always@(intA_LT_B or intQA_LT_Bpipe[2]) + begin + if(C_PIPE_STAGES < 2) // No pipeline + intQA_LT_Bpipeend <= intA_LT_B; + else // Pipeline stages required + begin + intQA_LT_Bpipeend <= intQA_LT_Bpipe[2]; + end + end + always@(intA_GT_B or intQA_GT_Bpipe[2]) + begin + if(C_PIPE_STAGES < 2) // No pipeline + intQA_GT_Bpipeend <= intA_GT_B; + else // Pipeline stages required + begin + intQA_GT_Bpipeend <= intQA_GT_Bpipe[2]; + end + end + always@(intA_LE_B or intQA_LE_Bpipe[2]) + begin + if(C_PIPE_STAGES < 2) // No pipeline + intQA_LE_Bpipeend <= intA_LE_B; + else // Pipeline stages required + begin + intQA_LE_Bpipeend <= intQA_LE_Bpipe[2]; + end + end + always@(intA_GE_B or intQA_GE_Bpipe[2]) + begin + if(C_PIPE_STAGES < 2) // No pipeline + intQA_GE_Bpipeend <= intA_GE_B; + else // Pipeline stages required + begin + intQA_GE_Bpipeend <= intQA_GE_Bpipe[2]; + end + end + + function is_X; + input [C_WIDTH-1 : 0] i; + integer j; + begin + is_X = 0; + for(j = 0; j < C_WIDTH; j = j + 1) + if(i[j] === 1'bx) + is_X = 1; + end + endfunction + + function defval; + input i; + input hassig; + input val; + begin + if(hassig == 1) + defval = i; + else + defval = val; + end + endfunction + + function [C_WIDTH - 1 : 0] defvecval; + input [C_WIDTH-1 : 0] i; + input hassig; + input [C_WIDTH-1 : 0] val; + begin + if(hassig == 1) + defvecval = i; + else + defvecval = val; + end + endfunction + + function [C_WIDTH - 1 : 0] to_bits; + input [C_WIDTH*8 : 1] instring; + integer i; + integer non_null_string; + begin + non_null_string = 0; + for(i = C_WIDTH; i > 0; i = i - 1) + begin // Is the string empty? + if(instring[(i*8)] == 0 && + instring[(i*8)-1] == 0 && + instring[(i*8)-2] == 0 && + instring[(i*8)-3] == 0 && + instring[(i*8)-4] == 0 && + instring[(i*8)-5] == 0 && + instring[(i*8)-6] == 0 && + instring[(i*8)-7] == 0 && + non_null_string == 0) + non_null_string = 0; // Use the return value to flag a non-empty string + else + non_null_string = 1; // Non-null character! + end + if(non_null_string == 0) // String IS empty! Just return the value to be all '0's + begin + for(i = C_WIDTH; i > 0; i = i - 1) + to_bits[i-1] = 0; + end + else + begin + for(i = C_WIDTH; i > 0; i = i - 1) + begin // Is this character a '0'? (ASCII = 48 = 00110000) + if(instring[(i*8)] == 0 && + instring[(i*8)-1] == 0 && + instring[(i*8)-2] == 1 && + instring[(i*8)-3] == 1 && + instring[(i*8)-4] == 0 && + instring[(i*8)-5] == 0 && + instring[(i*8)-6] == 0 && + instring[(i*8)-7] == 0) + to_bits[i-1] = 0; + // Or is it a '1'? + else if(instring[(i*8)] == 0 && + instring[(i*8)-1] == 0 && + instring[(i*8)-2] == 1 && + instring[(i*8)-3] == 1 && + instring[(i*8)-4] == 0 && + instring[(i*8)-5] == 0 && + instring[(i*8)-6] == 0 && + instring[(i*8)-7] == 1) + to_bits[i-1] = 1; + // Or is it a ' '? (a null char - in which case insert a '0') + else if(instring[(i*8)] == 0 && + instring[(i*8)-1] == 0 && + instring[(i*8)-2] == 0 && + instring[(i*8)-3] == 0 && + instring[(i*8)-4] == 0 && + instring[(i*8)-5] == 0 && + instring[(i*8)-6] == 0 && + instring[(i*8)-7] == 0) + to_bits[i-1] = 0; + else + begin + $display("Error in %m at time %d ns: non-binary digit in string \"%s\"\nExiting simulation...", $time, instring); + $finish; + end + end + end + end + endfunction + +endmodule + +`undef c_set +`undef c_clear +`undef c_override +`undef c_no_override +`undef c_signed +`undef c_unsigned + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/C_COMPARE_V7_0.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/C_COMPARE_V7_0.v new file mode 100644 index 0000000..2eb6015 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/C_COMPARE_V7_0.v @@ -0,0 +1,1256 @@ +// Copyright(C) 2003 by Xilinx, Inc. All rights reserved. +// This text/file contains proprietary, confidential +// information of Xilinx, Inc., is distributed under license +// from Xilinx, Inc., and may be used, copied and/or +// disclosed only pursuant to the terms of a valid license +// agreement with Xilinx, Inc. Xilinx hereby grants you +// a license to use this text/file solely for design, simulation, +// implementation and creation of design files limited +// to Xilinx devices or technologies. Use with non-Xilinx +// devices or technologies is expressly prohibited and +// immediately terminates your license unless covered by +// a separate agreement. +// +// Xilinx is providing this design, code, or information +// "as is" solely for use in developing programs and +// solutions for Xilinx devices. By providing this design, +// code, or information as one possible implementation of +// this feature, application or standard, Xilinx is making no +// representation that this implementation is free from any +// claims of infringement. You are responsible for +// obtaining any rights you may require for your implementation. +// Xilinx expressly disclaims any warranty whatsoever with +// respect to the adequacy of the implementation, including +// but not limited to any warranties or representations that this +// implementation is free from claims of infringement, implied +// warranties of merchantability or fitness for a particular +// purpose. +// +// Xilinx products are not intended for use in life support +// appliances, devices, or systems. Use in such applications are +// expressly prohibited. +// +// This copyright and support notice must be retained as part +// of this text at all times. (c) Copyright 1995-2003 Xilinx, Inc. +// All rights reserved. + + + +/* $Id: C_COMPARE_V7_0.v,v 1.13 2008/09/08 20:06:13 akennedy Exp $ +-- +-- Filename - C_COMPARE_V7_0.v +-- Author - Xilinx +-- Creation - 28 Jan 1999 +-- +-- Description - This file contains the Verilog behavior for the Baseblocks C_COMPARE_V7_0 module +*/ + +`timescale 1ns/10ps + +`define c_set 0 +`define c_clear 1 +`define c_override 0 +`define c_no_override 1 +`define c_signed 0 +`define c_unsigned 1 + +module C_COMPARE_V7_0 (A, B, CLK, CE, ACLR, ASET, SCLR, SSET, + A_EQ_B, A_NE_B, A_LT_B, A_GT_B, A_LE_B, A_GE_B, + QA_EQ_B, QA_NE_B, QA_LT_B, QA_GT_B, QA_LE_B, QA_GE_B); + + parameter C_AINIT_VAL = ""; + parameter C_B_CONSTANT = 0; + parameter C_B_VALUE = ""; + parameter C_DATA_TYPE = `c_unsigned; + parameter C_ENABLE_RLOCS = 1; + parameter C_HAS_ACLR = 0; + parameter C_HAS_ASET = 0; + parameter C_HAS_A_EQ_B = 1; + parameter C_HAS_A_GE_B = 0; + parameter C_HAS_A_GT_B = 0; + parameter C_HAS_A_LE_B = 0; + parameter C_HAS_A_LT_B = 0; + parameter C_HAS_A_NE_B = 0; + parameter C_HAS_CE = 0; + parameter C_HAS_QA_EQ_B = 0; + parameter C_HAS_QA_GE_B = 0; + parameter C_HAS_QA_GT_B = 0; + parameter C_HAS_QA_LE_B = 0; + parameter C_HAS_QA_LT_B = 0; + parameter C_HAS_QA_NE_B = 0; + parameter C_HAS_SCLR = 0; + parameter C_HAS_SSET = 0; + parameter C_PIPE_STAGES = 1; + parameter C_SYNC_ENABLE = `c_override; + parameter C_SYNC_PRIORITY = `c_clear; + parameter C_WIDTH = 16; + + + input [C_WIDTH-1 : 0] A; + input [C_WIDTH-1 : 0] B; + input CLK; + input CE; + input ACLR; + input ASET; + input SCLR; + input SSET; + output A_EQ_B; + output A_NE_B; + output A_LT_B; + output A_GT_B; + output A_LE_B; + output A_GE_B; + output QA_EQ_B; + output QA_NE_B; + output QA_LT_B; + output QA_GT_B; + output QA_LE_B; + output QA_GE_B; + + // Internal values to drive signals when input is missing + reg [C_WIDTH-1 : 0] intB; + reg intCE; + reg intACLR; + reg intASET; + reg intSCLR; + reg intSSET; + reg intA_EQ_B; + reg intA_NE_B; + reg intA_LT_B; + reg intA_GT_B; + reg intA_LE_B; + reg intA_GE_B; + wire intQA_EQ_B; + wire intQA_NE_B; + wire intQA_LT_B; + wire intQA_GT_B; + wire intQA_LE_B; + wire intQA_GE_B; + reg lastCLK; + + reg [C_PIPE_STAGES+2 : 0] intQA_EQ_Bpipe; + reg intQA_EQ_Bpipeend; + reg [C_PIPE_STAGES+2 : 0] intQA_NE_Bpipe; + reg intQA_NE_Bpipeend; + reg [C_PIPE_STAGES+2 : 0] intQA_LT_Bpipe; + reg intQA_LT_Bpipeend; + reg [C_PIPE_STAGES+2 : 0] intQA_GT_Bpipe; + reg intQA_GT_Bpipeend; + reg [C_PIPE_STAGES+2 : 0] intQA_LE_Bpipe; + reg intQA_LE_Bpipeend; + reg [C_PIPE_STAGES+2 : 0] intQA_GE_Bpipe; + reg intQA_GE_Bpipeend; + + wire AINIT; + wire SINIT; + + wire A_EQ_B = (C_HAS_A_EQ_B == 1 ? intA_EQ_B : 1'bx); + wire A_NE_B = (C_HAS_A_NE_B == 1 ? intA_NE_B : 1'bx); + wire A_LT_B = (C_HAS_A_LT_B == 1 ? intA_LT_B : 1'bx); + wire A_GT_B = (C_HAS_A_GT_B == 1 ? intA_GT_B : 1'bx); + wire A_LE_B = (C_HAS_A_LE_B == 1 ? intA_LE_B : 1'bx); + wire A_GE_B = (C_HAS_A_GE_B == 1 ? intA_GE_B : 1'bx); + wire QA_EQ_B = (C_HAS_QA_EQ_B == 1 ? intQA_EQ_B : 1'bx); + wire QA_NE_B = (C_HAS_QA_NE_B == 1 ? intQA_NE_B : 1'bx); + wire QA_LT_B = (C_HAS_QA_LT_B == 1 ? intQA_LT_B : 1'bx); + wire QA_GT_B = (C_HAS_QA_GT_B == 1 ? intQA_GT_B : 1'bx); + wire QA_LE_B = (C_HAS_QA_LE_B == 1 ? intQA_LE_B : 1'bx); + wire QA_GE_B = (C_HAS_QA_GE_B == 1 ? intQA_GE_B : 1'bx); + + integer pipe, notdone, i; + + reg aeqb, aneb, altb, agtb, aleb, ageb; + reg [C_WIDTH-1:0] a_low; + reg [C_WIDTH-1:0] a_high; + reg [C_WIDTH-1:0] b_low; + reg [C_WIDTH-1:0] b_high; + + // Instance the required output regs + C_REG_FD_V7_0 #(C_AINIT_VAL, C_ENABLE_RLOCS, C_HAS_ACLR, 0, C_HAS_ASET, + C_HAS_CE, C_HAS_SCLR, 0, C_HAS_SSET, + "0", C_SYNC_ENABLE, C_SYNC_PRIORITY, 1) + regaeqb (.D(intQA_EQ_Bpipeend), .CLK(CLK), .CE(CE), .ACLR(ACLR), .ASET(ASET), + .AINIT(AINIT), .SCLR(SCLR), .SSET(SSET), .SINIT(SINIT), + .Q(intQA_EQ_B)); + + C_REG_FD_V7_0 #(C_AINIT_VAL, C_ENABLE_RLOCS, C_HAS_ACLR, 0, C_HAS_ASET, + C_HAS_CE, C_HAS_SCLR, 0, C_HAS_SSET, + "0", C_SYNC_ENABLE, C_SYNC_PRIORITY, 1) + reganeb (.D(intQA_NE_Bpipeend), .CLK(CLK), .CE(CE), .ACLR(ACLR), .ASET(ASET), + .AINIT(AINIT), .SCLR(SCLR), .SSET(SSET), .SINIT(SINIT), + .Q(intQA_NE_B)); + + C_REG_FD_V7_0 #(C_AINIT_VAL, C_ENABLE_RLOCS, C_HAS_ACLR, 0, C_HAS_ASET, + C_HAS_CE, C_HAS_SCLR, 0, C_HAS_SSET, + "0", C_SYNC_ENABLE, C_SYNC_PRIORITY, 1) + regaltb (.D(intQA_LT_Bpipeend), .CLK(CLK), .CE(CE), .ACLR(ACLR), .ASET(ASET), + .AINIT(AINIT), .SCLR(SCLR), .SSET(SSET), .SINIT(SINIT), + .Q(intQA_LT_B)); + + C_REG_FD_V7_0 #(C_AINIT_VAL, C_ENABLE_RLOCS, C_HAS_ACLR, 0, C_HAS_ASET, + C_HAS_CE, C_HAS_SCLR, 0, C_HAS_SSET, + "0", C_SYNC_ENABLE, C_SYNC_PRIORITY, 1) + regagtb (.D(intQA_GT_Bpipeend), .CLK(CLK), .CE(CE), .ACLR(ACLR), .ASET(ASET), + .AINIT(AINIT), .SCLR(SCLR), .SSET(SSET), .SINIT(SINIT), + .Q(intQA_GT_B)); + + C_REG_FD_V7_0 #(C_AINIT_VAL, C_ENABLE_RLOCS, C_HAS_ACLR, 0, C_HAS_ASET, + C_HAS_CE, C_HAS_SCLR, 0, C_HAS_SSET, + "0", C_SYNC_ENABLE, C_SYNC_PRIORITY, 1) + regaleb (.D(intQA_LE_Bpipeend), .CLK(CLK), .CE(CE), .ACLR(ACLR), .ASET(ASET), + .AINIT(AINIT), .SCLR(SCLR), .SSET(SSET), .SINIT(SINIT), + .Q(intQA_LE_B)); + + C_REG_FD_V7_0 #(C_AINIT_VAL, C_ENABLE_RLOCS, C_HAS_ACLR, 0, C_HAS_ASET, + C_HAS_CE, C_HAS_SCLR, 0, C_HAS_SSET, + "0", C_SYNC_ENABLE, C_SYNC_PRIORITY, 1) + regageb (.D(intQA_GE_Bpipeend), .CLK(CLK), .CE(CE), .ACLR(ACLR), .ASET(ASET), + .AINIT(AINIT), .SCLR(SCLR), .SSET(SSET), .SINIT(SINIT), + .Q(intQA_GE_B)); + + initial + begin + #1; + intCE = defval(CE, C_HAS_CE, 1); + intB = defvecval(B, (C_B_CONSTANT == 1) ? 0 : 1, to_bits(C_B_VALUE)); + + intQA_EQ_Bpipe = 'b0; + intQA_NE_Bpipe = 'b0; + intQA_LT_Bpipe = 'b0; + intQA_GT_Bpipe = 'b0; + intQA_LE_Bpipe = 'b0; + intQA_GE_Bpipe = 'b0; + + if(is_X(A) == 1 || is_X(intB) == 1) + begin + notdone = 1; + if((is_X(A) && A === {C_WIDTH{1'bx}}) && (is_X(intB) && intB === {C_WIDTH{1'bx}})) + begin + aeqb <= 1'bx; + aneb <= 1'bx; + altb <= 1'bx; + agtb <= 1'bx; + aleb <= 1'bx; + ageb <= 1'bx; + notdone = 0; + end + else if(C_DATA_TYPE == `c_signed) + begin +/* if(A[C_WIDTH-1] === 1'bx && intB[C_WIDTH-1] === 1'bx) + // Don't know the sign of EITHER data => ALL X's + begin + aeqb <= 1'bx; + aneb <= 1'bx; + altb <= 1'bx; + agtb <= 1'bx; + aleb <= 1'bx; + ageb <= 1'bx; + notdone = 0; + end + else if (A[C_WIDTH-1] !== 1'bx && intB[C_WIDTH-1] !== 1'bx) +*/ if (A[C_WIDTH-1] !== 1'bx && intB[C_WIDTH-1] !== 1'bx) + begin + // The sign bits are both known + if (A[C_WIDTH-1] !== intB[C_WIDTH-1]) + begin + // different signs! + if (A[C_WIDTH-1] === 1'b1) + begin + // A is negative and B is positive + aeqb <= 0; + aneb <= 1; + altb <= 1; + agtb <= 0; + aleb <= 1; + ageb <= 0; + notdone = 0; + end + else // A is +ve and B is -ve + begin + aeqb <= 0; + aneb <= 1; + altb <= 0; + agtb <= 1; + aleb <= 0; + ageb <= 1; + notdone = 0; + end + end + end + end + if (notdone == 1) // check further + begin + // Make copies of A and B with all X's substituted with 0's and 1's + a_low = A; + a_high = A; + b_low = intB; + b_high = intB; + for (i=C_WIDTH-2; i >= 0; i = i - 1) + begin + if (a_low[i] === 1'bx) + begin + a_low[i] = 0; + a_high[i] = 1; + end + if (b_low[i] === 1'bx) + begin + b_low[i] = 0; + b_high[i] = 1; + end + end + // we now (almost - need to check possible sign bits) have worst-case values which must agree on the comparison result + // if that result is not to be unknown... + if (C_DATA_TYPE == `c_signed) + begin + // Set the sign bits of the range values to 0 since + // the sign of the values will be treated separately + a_low[C_WIDTH-1] = 0; + a_high[C_WIDTH-1] = 0; + b_low[C_WIDTH-1] = 0; + b_high[C_WIDTH-1] = 0; + + if((A[C_WIDTH-1] === 1'b1 && intB[C_WIDTH-1] === 1'bx) + || (intB[C_WIDTH-1] === 1'b0 && A[C_WIDTH-1] === 1'bx)) + begin // Sign of A is -ve and sign of B is unknown OR + // sign of B is +ve and sign of A is unknown + // Is A always < B? + if (a_high < b_low) + begin + // A is definitely < than B + aeqb <= 0; + aneb <= 1; + altb <= 1; + agtb <= 0; + aleb <= 1; + ageb <= 0; + end + else if (a_high == b_low) + begin + // A is <= than B + aeqb <= 1'bx; + aneb <= 1'bx; + altb <= 1'bx; + agtb <= 0; + aleb <= 1; + ageb <= 1'bx; + end + else if (a_low != b_low && a_low !== b_high && a_high !== b_low && a_high !== b_high && !(intB === {C_WIDTH{1'bx}} || A === {C_WIDTH{1'bx}})) + begin // Definitely not equal! + aeqb <= 1'b0; + aneb <= 1'b1; + altb <= 1'bx; + agtb <= 1'bx; + aleb <= 1'bx; + ageb <= 1'bx; + end + else // There is > 1 overlap between the ranges so all X's + begin + aeqb <= 1'bx; + aneb <= 1'bx; + altb <= 1'bx; + agtb <= 1'bx; + aleb <= 1'bx; + ageb <= 1'bx; + end + end + else if((A[C_WIDTH-1] === 1'b0 && intB[C_WIDTH-1] === 1'bx) + || (intB[C_WIDTH-1] === 1'b1 && A[C_WIDTH-1] === 1'bx)) + begin // Sign of A is +ve and sign of B is unknown OR + // sign of B is -ve and sign of A is unknown + // Is B always < A? + if (b_high < a_low) + begin + // B is definitely < than A + aeqb <= 0; + aneb <= 1; + altb <= 0; + agtb <= 1; + aleb <= 0; + ageb <= 1; + end + else if (b_high == a_low) + begin + // B is <= than A + aeqb <= 1'bx; + aneb <= 1'bx; + altb <= 0; + agtb <= 1'bx; + aleb <= 1'bx; + ageb <= 1; + end + else if (a_low != b_low && a_low !== b_high && a_high !== b_low && a_high !== b_high && !(intB === {C_WIDTH{1'bx}} || A === {C_WIDTH{1'bx}})) + begin // Definitely not equal! + aeqb <= 1'b0; + aneb <= 1'b1; + altb <= 1'bx; + agtb <= 1'bx; + aleb <= 1'bx; + ageb <= 1'bx; + end + else // There is > 1 overlap between the ranges so all X's + begin + aeqb <= 1'bx; + aneb <= 1'bx; + altb <= 1'bx; + agtb <= 1'bx; + aleb <= 1'bx; + ageb <= 1'bx; + end + end + else // Sign bits on A and B are identical and both are known + begin + if (a_high < b_low) + begin + // A is definitely < than B + aeqb <= 0; + aneb <= 1; + altb <= 1; + agtb <= 0; + aleb <= 1; + ageb <= 0; + end + else if (a_low > b_high) + begin + // A is definitely > than B + aeqb <= 0; + aneb <= 1; + altb <= 0; + agtb <= 1; + aleb <= 0; + ageb <= 1; + end + else if (a_high == b_low) + begin + // A is <= than B + aeqb <= 1'bx; + aneb <= 1'bx; + altb <= 1'bx; + agtb <= 0; + aleb <= 1; + ageb <= 1'bx; + end + else if (a_low == b_high) + begin + // A is >= than B + aeqb <= 1'bx; + aneb <= 1'bx; + altb <= 0; + agtb <= 1'bx; + aleb <= 1'bx; + ageb <= 1; + end + else if (a_low != b_low && a_low !== b_high && a_high !== b_low && a_high !== b_high && !(intB === {C_WIDTH{1'bx}} || A === {C_WIDTH{1'bx}})) + begin // Definitely not equal! + aeqb <= 1'b0; + aneb <= 1'b1; + altb <= 1'bx; + agtb <= 1'bx; + aleb <= 1'bx; + ageb <= 1'bx; + end + else // There is > 1 overlap between the ranges so all X's + begin + aeqb <= 1'bx; + aneb <= 1'bx; + altb <= 1'bx; + agtb <= 1'bx; + aleb <= 1'bx; + ageb <= 1'bx; + end + end + end + else // unsigned data + begin + if (a_low[C_WIDTH-1] === 1'bx) + begin + a_low[C_WIDTH-1] = 0; + a_high[C_WIDTH-1] = 1; + end + if (b_low[C_WIDTH-1] === 1'bx) + begin + b_low[C_WIDTH-1] = 0; + b_high[C_WIDTH-1] = 1; + end + if (a_high < b_low) + begin + // A is definitely < than B + aeqb <= 0; + aneb <= 1; + altb <= 1; + agtb <= 0; + aleb <= 1; + ageb <= 0; + end + else if (a_low > b_high) + begin + // A is definitely > than B + aeqb <= 0; + aneb <= 1; + altb <= 0; + agtb <= 1; + aleb <= 0; + ageb <= 1; + end + else if (a_high == b_low) + begin + // A is <= B + aeqb <= 1'bx; + aneb <= 1'bx; + altb <= 1'bx; + agtb <= 0; + aleb <= 1; + ageb <= 1'bx; + end + else if (a_low == b_high) + begin + // A is >= B + aeqb <= 1'bx; + aneb <= 1'bx; + altb <= 0; + agtb <= 1'bx; + aleb <= 1'bx; + ageb <= 1; + end + else if (a_low != b_low && a_low !== b_high && a_high !== b_low && a_high !== b_high && !(intB === {C_WIDTH{1'bx}} || A === {C_WIDTH{1'bx}})) + begin // Definitely not equal! + aeqb <= 1'b0; + aneb <= 1'b1; + altb <= 1'bx; + agtb <= 1'bx; + aleb <= 1'bx; + ageb <= 1'bx; + end + else // There is > 1 overlap between the ranges so all X's + begin + aeqb <= 1'bx; + aneb <= 1'bx; + altb <= 1'bx; + agtb <= 1'bx; + aleb <= 1'bx; + ageb <= 1'bx; + end + end + end + end + else if (C_DATA_TYPE == `c_signed) + begin + // Signed data so examine MSB and rest separately in some cases + if(A == intB) + begin + aeqb <= 1; + aneb <= 0; + altb <= 0; + agtb <= 0; + end + else if(A[C_WIDTH-1] == intB[C_WIDTH-1]) // Both numbers are -ve or both are +ve + begin + if(A < intB) + begin + aeqb <= 0; + aneb <= 1; + altb <= 1; + agtb <= 0; + end + if(A > intB) + begin + aeqb <= 0; + aneb <= 1; + altb <= 0; + agtb <= 1; + end + end + else if(A[C_WIDTH-1] == 1 && intB[C_WIDTH-1] == 0) // A is -ve, B is +ve + begin + aeqb <= 0; + aneb <= 1; + altb <= 1; + agtb <= 0; + end + else if(A[C_WIDTH-1] == 0 && intB[C_WIDTH-1] == 1) // A is +ve, B is -ve + begin + aeqb <= 0; + aneb <= 1; + altb <= 0; + agtb <= 1; + end + if(aeqb == 1 || altb == 1) + aleb <= 1; + else + aleb <= 0; + if(aeqb == 1 || agtb == 1) + ageb <= 1; + else + ageb <= 0; + end + else // Data is unsigned + begin + if(A == intB) + begin + aeqb <= 1; + aneb <= 0; + altb <= 0; + agtb <= 0; + end + if(A < intB) + begin + aeqb <= 0; + aneb <= 1; + altb <= 1; + agtb <= 0; + end + if(A > intB) + begin + aeqb <= 0; + aneb <= 1; + altb <= 0; + agtb <= 1; + end + if(aeqb == 1 || altb == 1) + aleb <= 1; + else + aleb <= 0; + if(aeqb == 1 || agtb == 1) + ageb <= 1; + else + ageb <= 0; + end + + intA_EQ_B <= #1 aeqb; + intA_NE_B <= #1 aneb; + intA_LT_B <= #1 altb; + intA_GT_B <= #1 agtb; + intA_LE_B <= #1 aleb; + intA_GE_B <= #1 ageb; + + end + + always @(CLK) + lastCLK <= CLK; + + always @(A or B or CE or ACLR or ASET or SCLR or SSET) + begin + intCE = defval(CE, C_HAS_CE, 1); + intB = defvecval(B, (C_B_CONSTANT == 1) ? 0 : 1, to_bits(C_B_VALUE)); + + if(is_X(A) == 1 || is_X(intB) == 1) + begin + notdone = 1; + if((is_X(A) && A === {C_WIDTH{1'bx}}) && (is_X(intB) && intB === {C_WIDTH{1'bx}})) + begin + aeqb = 1'bx; + aneb = 1'bx; + altb = 1'bx; + agtb = 1'bx; + aleb = 1'bx; + ageb = 1'bx; + notdone = 0; + end + else if(C_DATA_TYPE == `c_signed) + begin +/* if(A[C_WIDTH-1] === 1'bx && intB[C_WIDTH-1] === 1'bx) + // Don't know the sign of EITHER data => ALL X's + begin + aeqb = 1'bx; + aneb = 1'bx; + altb = 1'bx; + agtb = 1'bx; + aleb = 1'bx; + ageb = 1'bx; + notdone = 0; + end + else if (A[C_WIDTH-1] !== 1'bx && intB[C_WIDTH-1] !== 1'bx) +*/ if (A[C_WIDTH-1] !== 1'bx && intB[C_WIDTH-1] !== 1'bx) + begin + // The sign bits are both known + if (A[C_WIDTH-1] !== intB[C_WIDTH-1]) + begin + // different signs! + if (A[C_WIDTH-1] === 1'b1) + begin + // A is negative and B is positive + aeqb = 0; + aneb = 1; + altb = 1; + agtb = 0; + aleb = 1; + ageb = 0; + notdone = 0; + end + else // A is +ve and B is -ve + begin + aeqb = 0; + aneb = 1; + altb = 0; + agtb = 1; + aleb = 0; + ageb = 1; + notdone = 0; + end + end + end + end + if (notdone == 1) // check further + begin + // Make copies of A and B with all X's substituted with 0's and 1's + a_low = A; + a_high = A; + b_low = intB; + b_high = intB; + for (i=C_WIDTH-2; i >= 0; i = i - 1) + begin + if (a_low[i] === 1'bx) + begin + a_low[i] = 0; + a_high[i] = 1; + end + if (b_low[i] === 1'bx) + begin + b_low[i] = 0; + b_high[i] = 1; + end + end + // we now (almost - need to check possible sign bits) have worst-case values which must agree on the comparison result + // if that result is not to be unknown... + if (C_DATA_TYPE == `c_signed) + begin + // Set the sign bits of the range values to 0 since + // the sign of the values will be treated separately + a_low[C_WIDTH-1] = 0; + a_high[C_WIDTH-1] = 0; + b_low[C_WIDTH-1] = 0; + b_high[C_WIDTH-1] = 0; + + if((A[C_WIDTH-1] === 1'b1 && intB[C_WIDTH-1] === 1'bx) + || (intB[C_WIDTH-1] === 1'b0 && A[C_WIDTH-1] === 1'bx)) + begin // Sign of A is -ve and sign of B is unknown OR + // sign of B is +ve and sign of A is unknown + // Is A always < B? + if (a_high < b_low) + begin + // A is definitely < than B + aeqb = 0; + aneb = 1; + altb = 1; + agtb = 0; + aleb = 1; + ageb = 0; + end + else if (a_high == b_low) + begin + // A is <= than B + aeqb = 1'bx; + aneb = 1'bx; + altb = 1'bx; + agtb = 0; + aleb = 1; + ageb = 1'bx; + end + else if (a_low != b_low && a_low !== b_high && a_high !== b_low && a_high !== b_high && !(intB === {C_WIDTH{1'bx}} || A === {C_WIDTH{1'bx}})) + begin // Definitely not equal! + aeqb = 1'b0; + aneb = 1'b1; + altb = 1'bx; + agtb = 1'bx; + aleb = 1'bx; + ageb = 1'bx; + end + else // There is > 1 overlap between the ranges so all X's + begin + aeqb = 1'bx; + aneb = 1'bx; + altb = 1'bx; + agtb = 1'bx; + aleb = 1'bx; + ageb = 1'bx; + end + end + else if((A[C_WIDTH-1] === 1'b0 && intB[C_WIDTH-1] === 1'bx) + || (intB[C_WIDTH-1] === 1'b1 && A[C_WIDTH-1] === 1'bx)) + begin // Sign of A is +ve and sign of B is unknown OR + // sign of B is -ve and sign of A is unknown + // Is B always < A? + if (b_high < a_low) + begin + // B is definitely < than A + aeqb = 0; + aneb = 1; + altb = 0; + agtb = 1; + aleb = 0; + ageb = 1; + end + else if (b_high == a_low) + begin + // B is <= than A + aeqb = 1'bx; + aneb = 1'bx; + altb = 0; + agtb = 1'bx; + aleb = 1'bx; + ageb = 1; + end + else if (a_low != b_low && a_low !== b_high && a_high !== b_low && a_high !== b_high && !(intB === {C_WIDTH{1'bx}} || A === {C_WIDTH{1'bx}})) + begin // Definitely not equal! + aeqb = 1'b0; + aneb = 1'b1; + altb = 1'bx; + agtb = 1'bx; + aleb = 1'bx; + ageb = 1'bx; + end + else // There is > 1 overlap between the ranges so all X's + begin + aeqb = 1'bx; + aneb = 1'bx; + altb = 1'bx; + agtb = 1'bx; + aleb = 1'bx; + ageb = 1'bx; + end + end + else // Sign bits on A and B are identical and both are known + begin + if (a_high < b_low) + begin + // A is definitely < than B + aeqb = 0; + aneb = 1; + altb = 1; + agtb = 0; + aleb = 1; + ageb = 0; + end + else if (a_low > b_high) + begin + // A is definitely > than B + aeqb = 0; + aneb = 1; + altb = 0; + agtb = 1; + aleb = 0; + ageb = 1; + end + else if (a_high == b_low) + begin + // A is <= than B + aeqb = 1'bx; + aneb = 1'bx; + altb = 1'bx; + agtb = 0; + aleb = 1; + ageb = 1'bx; + end + else if (a_low == b_high) + begin + // A is >= than B + aeqb = 1'bx; + aneb = 1'bx; + altb = 0; + agtb = 1'bx; + aleb = 1'bx; + ageb = 1; + end + else if (a_low != b_low && a_low !== b_high && a_high !== b_low && a_high !== b_high && !(intB === {C_WIDTH{1'bx}} || A === {C_WIDTH{1'bx}})) + begin // Definitely not equal! + aeqb = 1'b0; + aneb = 1'b1; + altb = 1'bx; + agtb = 1'bx; + aleb = 1'bx; + ageb = 1'bx; + end + else // There is > 1 overlap between the ranges so all X's + begin + aeqb = 1'bx; + aneb = 1'bx; + altb = 1'bx; + agtb = 1'bx; + aleb = 1'bx; + ageb = 1'bx; + end + end + end + else // unsigned data + begin + if (a_low[C_WIDTH-1] === 1'bx) + begin + a_low[C_WIDTH-1] = 0; + a_high[C_WIDTH-1] = 1; + end + if (b_low[C_WIDTH-1] === 1'bx) + begin + b_low[C_WIDTH-1] = 0; + b_high[C_WIDTH-1] = 1; + end + if (a_high < b_low) + begin + // A is definitely < than B + aeqb = 0; + aneb = 1; + altb = 1; + agtb = 0; + aleb = 1; + ageb = 0; + end + else if (a_low > b_high) + begin + // A is definitely > than B + aeqb = 0; + aneb = 1; + altb = 0; + agtb = 1; + aleb = 0; + ageb = 1; + end + else if (a_high == b_low) + begin + // A is <= B + aeqb = 1'bx; + aneb = 1'bx; + altb = 1'bx; + agtb = 0; + aleb = 1; + ageb = 1'bx; + end + else if (a_low == b_high) + begin + // A is >= B + aeqb = 1'bx; + aneb = 1'bx; + altb = 0; + agtb = 1'bx; + aleb = 1'bx; + ageb = 1; + end + else if (a_low != b_low && a_low !== b_high && a_high !== b_low && a_high !== b_high && !(intB === {C_WIDTH{1'bx}} || A === {C_WIDTH{1'bx}})) + begin // Definitely not equal! + aeqb = 1'b0; + aneb = 1'b1; + altb = 1'bx; + agtb = 1'bx; + aleb = 1'bx; + ageb = 1'bx; + end + else // There is > 1 overlap between the ranges so all X's + begin + aeqb = 1'bx; + aneb = 1'bx; + altb = 1'bx; + agtb = 1'bx; + aleb = 1'bx; + ageb = 1'bx; + end + end + end + end + else if (C_DATA_TYPE == `c_signed) + begin + // Signed data so examine MSB and rest separately in some cases + if(A == intB) + begin + aeqb = 1; + aneb = 0; + altb = 0; + agtb = 0; + end + else if(A[C_WIDTH-1] == intB[C_WIDTH-1]) // Both numbers are -ve or both are +ve + begin + if(A < intB) + begin + aeqb = 0; + aneb = 1; + altb = 1; + agtb = 0; + end + if(A > intB) + begin + aeqb = 0; + aneb = 1; + altb = 0; + agtb = 1; + end + end + else if(A[C_WIDTH-1] == 1 && intB[C_WIDTH-1] == 0) // A is -ve, B is +ve + begin + aeqb = 0; + aneb = 1; + altb = 1; + agtb = 0; + end + else if(A[C_WIDTH-1] == 0 && intB[C_WIDTH-1] == 1) // A is +ve, B is -ve + begin + aeqb = 0; + aneb = 1; + altb = 0; + agtb = 1; + end + if(aeqb == 1 || altb == 1) + aleb = 1; + else + aleb = 0; + if(aeqb == 1 || agtb == 1) + ageb = 1; + else + ageb = 0; + end + else // Data is unsigned + begin + if(A == intB) + begin + aeqb = 1; + aneb = 0; + altb = 0; + agtb = 0; + end + if(A < intB) + begin + aeqb = 0; + aneb = 1; + altb = 1; + agtb = 0; + end + if(A > intB) + begin + aeqb = 0; + aneb = 1; + altb = 0; + agtb = 1; + end + if(aeqb == 1 || altb == 1) + aleb = 1; + else + aleb = 0; + if(aeqb == 1 || agtb == 1) + ageb = 1; + else + ageb = 0; + end + + intA_EQ_B <= #1 aeqb; + intA_NE_B <= #1 aneb; + intA_LT_B <= #1 altb; + intA_GT_B <= #1 agtb; + intA_LE_B <= #1 aleb; + intA_GE_B <= #1 ageb; + end + + always@(posedge CLK) + begin + if(CLK === 1'b1 && lastCLK === 1'b0 && intCE === 1'b1) // OK! Update pipelines! + begin + for(pipe = 2; pipe <= C_PIPE_STAGES-1; pipe = pipe + 1) + begin + intQA_EQ_Bpipe[pipe] <= intQA_EQ_Bpipe[pipe+1]; + intQA_NE_Bpipe[pipe] <= intQA_NE_Bpipe[pipe+1]; + intQA_LT_Bpipe[pipe] <= intQA_LT_Bpipe[pipe+1]; + intQA_GT_Bpipe[pipe] <= intQA_GT_Bpipe[pipe+1]; + intQA_LE_Bpipe[pipe] <= intQA_LE_Bpipe[pipe+1]; + intQA_GE_Bpipe[pipe] <= intQA_GE_Bpipe[pipe+1]; + end + intQA_EQ_Bpipe[C_PIPE_STAGES] <= intA_EQ_B; + intQA_NE_Bpipe[C_PIPE_STAGES] <= intA_NE_B; + intQA_LT_Bpipe[C_PIPE_STAGES] <= intA_LT_B; + intQA_GT_Bpipe[C_PIPE_STAGES] <= intA_GT_B; + intQA_LE_Bpipe[C_PIPE_STAGES] <= intA_LE_B; + intQA_GE_Bpipe[C_PIPE_STAGES] <= intA_GE_B; + end + else if((CLK === 1'bx && lastCLK === 1'b0) || (CLK === 1'b1 && lastCLK === 1'bx) || intCE === 1'bx) // POSSIBLY Update pipelines! + begin + for(pipe = 2; pipe <= C_PIPE_STAGES-1; pipe = pipe + 1) + begin + if(intQA_EQ_Bpipe[pipe] !== intQA_EQ_Bpipe[pipe+1]) + intQA_EQ_Bpipe[pipe] <= 1'bx; + if(intQA_NE_Bpipe[pipe] !== intQA_NE_Bpipe[pipe+1]) + intQA_NE_Bpipe[pipe] <= 1'bx; + if(intQA_LT_Bpipe[pipe] !== intQA_LT_Bpipe[pipe+1]) + intQA_LT_Bpipe[pipe] <= 1'bx; + if(intQA_GT_Bpipe[pipe] !== intQA_GT_Bpipe[pipe+1]) + intQA_GT_Bpipe[pipe] <= 1'bx; + if(intQA_LE_Bpipe[pipe] !== intQA_LE_Bpipe[pipe+1]) + intQA_LE_Bpipe[pipe] <= 1'bx; + if(intQA_GE_Bpipe[pipe] !== intQA_GE_Bpipe[pipe+1]) + intQA_GE_Bpipe[pipe] <= 1'bx; + end + if(intQA_EQ_Bpipe[C_PIPE_STAGES] !== intA_EQ_B) + intQA_EQ_Bpipe[C_PIPE_STAGES] <= 1'bx; + if(intQA_NE_Bpipe[C_PIPE_STAGES] !== intA_NE_B) + intQA_NE_Bpipe[C_PIPE_STAGES] <= 1'bx; + if(intQA_LT_Bpipe[C_PIPE_STAGES] !== intA_LT_B) + intQA_LT_Bpipe[C_PIPE_STAGES] <= 1'bx; + if(intQA_GT_Bpipe[C_PIPE_STAGES] !== intA_GT_B) + intQA_GT_Bpipe[C_PIPE_STAGES] <= 1'bx; + if(intQA_LE_Bpipe[C_PIPE_STAGES] !== intA_LE_B) + intQA_LE_Bpipe[C_PIPE_STAGES] <= 1'bx; + if(intQA_GE_Bpipe[C_PIPE_STAGES] !== intA_GE_B) + intQA_GE_Bpipe[C_PIPE_STAGES] <= 1'bx; + end + end + + always@(intA_EQ_B or intQA_EQ_Bpipe[2]) + begin + if(C_PIPE_STAGES < 2) // No pipeline + intQA_EQ_Bpipeend <= intA_EQ_B; + else // Pipeline stages required + begin + intQA_EQ_Bpipeend <= intQA_EQ_Bpipe[2]; + end + end + always@(intA_NE_B or intQA_NE_Bpipe[2]) + begin + if(C_PIPE_STAGES < 2) // No pipeline + intQA_NE_Bpipeend <= intA_NE_B; + else // Pipeline stages required + begin + intQA_NE_Bpipeend <= intQA_NE_Bpipe[2]; + end + end + always@(intA_LT_B or intQA_LT_Bpipe[2]) + begin + if(C_PIPE_STAGES < 2) // No pipeline + intQA_LT_Bpipeend <= intA_LT_B; + else // Pipeline stages required + begin + intQA_LT_Bpipeend <= intQA_LT_Bpipe[2]; + end + end + always@(intA_GT_B or intQA_GT_Bpipe[2]) + begin + if(C_PIPE_STAGES < 2) // No pipeline + intQA_GT_Bpipeend <= intA_GT_B; + else // Pipeline stages required + begin + intQA_GT_Bpipeend <= intQA_GT_Bpipe[2]; + end + end + always@(intA_LE_B or intQA_LE_Bpipe[2]) + begin + if(C_PIPE_STAGES < 2) // No pipeline + intQA_LE_Bpipeend <= intA_LE_B; + else // Pipeline stages required + begin + intQA_LE_Bpipeend <= intQA_LE_Bpipe[2]; + end + end + always@(intA_GE_B or intQA_GE_Bpipe[2]) + begin + if(C_PIPE_STAGES < 2) // No pipeline + intQA_GE_Bpipeend <= intA_GE_B; + else // Pipeline stages required + begin + intQA_GE_Bpipeend <= intQA_GE_Bpipe[2]; + end + end + + function is_X; + input [C_WIDTH-1 : 0] i; + integer j; + begin + is_X = 0; + for(j = 0; j < C_WIDTH; j = j + 1) + if(i[j] === 1'bx) + is_X = 1; + end + endfunction + + function defval; + input i; + input hassig; + input val; + begin + if(hassig == 1) + defval = i; + else + defval = val; + end + endfunction + + function [C_WIDTH - 1 : 0] defvecval; + input [C_WIDTH-1 : 0] i; + input hassig; + input [C_WIDTH-1 : 0] val; + begin + if(hassig == 1) + defvecval = i; + else + defvecval = val; + end + endfunction + + function [C_WIDTH - 1 : 0] to_bits; + input [C_WIDTH*8 : 1] instring; + integer i; + integer non_null_string; + begin + non_null_string = 0; + for(i = C_WIDTH; i > 0; i = i - 1) + begin // Is the string empty? + if(instring[(i*8)] == 0 && + instring[(i*8)-1] == 0 && + instring[(i*8)-2] == 0 && + instring[(i*8)-3] == 0 && + instring[(i*8)-4] == 0 && + instring[(i*8)-5] == 0 && + instring[(i*8)-6] == 0 && + instring[(i*8)-7] == 0 && + non_null_string == 0) + non_null_string = 0; // Use the return value to flag a non-empty string + else + non_null_string = 1; // Non-null character! + end + if(non_null_string == 0) // String IS empty! Just return the value to be all '0's + begin + for(i = C_WIDTH; i > 0; i = i - 1) + to_bits[i-1] = 0; + end + else + begin + for(i = C_WIDTH; i > 0; i = i - 1) + begin // Is this character a '0'? (ASCII = 48 = 00110000) + if(instring[(i*8)] == 0 && + instring[(i*8)-1] == 0 && + instring[(i*8)-2] == 1 && + instring[(i*8)-3] == 1 && + instring[(i*8)-4] == 0 && + instring[(i*8)-5] == 0 && + instring[(i*8)-6] == 0 && + instring[(i*8)-7] == 0) + to_bits[i-1] = 0; + // Or is it a '1'? + else if(instring[(i*8)] == 0 && + instring[(i*8)-1] == 0 && + instring[(i*8)-2] == 1 && + instring[(i*8)-3] == 1 && + instring[(i*8)-4] == 0 && + instring[(i*8)-5] == 0 && + instring[(i*8)-6] == 0 && + instring[(i*8)-7] == 1) + to_bits[i-1] = 1; + // Or is it a ' '? (a null char - in which case insert a '0') + else if(instring[(i*8)] == 0 && + instring[(i*8)-1] == 0 && + instring[(i*8)-2] == 0 && + instring[(i*8)-3] == 0 && + instring[(i*8)-4] == 0 && + instring[(i*8)-5] == 0 && + instring[(i*8)-6] == 0 && + instring[(i*8)-7] == 0) + to_bits[i-1] = 0; + else + begin + $display("Error in %m at time %d ns: non-binary digit in string \"%s\"\nExiting simulation...", $time, instring); + $finish; + end + end + end + end + endfunction + +endmodule + +`undef c_set +`undef c_clear +`undef c_override +`undef c_no_override +`undef c_signed +`undef c_unsigned + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/C_COUNTER_BINARY_V4_0.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/C_COUNTER_BINARY_V4_0.v new file mode 100644 index 0000000..b005fe2 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/C_COUNTER_BINARY_V4_0.v @@ -0,0 +1,409 @@ +/* $Id: C_COUNTER_BINARY_V4_0.v,v 1.11 2008/09/08 20:05:46 akennedy Exp $ +-- +-- Filename - C_COUNTER_BINARY_V4_0.v +-- Author - Xilinx +-- Creation -14 July 1999 +-- +-- Description - This file contains the Verilog behavior for the Baseblocks C_COUNTER_BINARY_V4_0 module +*/ + + + + + +`define c_set 0 +`define c_clear 1 +`define c_override 0 +`define c_no_override 1 +`define c_signed 0 +`define c_unsigned 1 +`define c_pin 2 +`define c_up 0 +`define c_down 1 +`define c_updown 2 +`define allXs {C_WIDTH{1'bx}} + +module C_COUNTER_BINARY_V4_0 (CLK, UP, CE, LOAD, L, IV, ACLR, ASET, AINIT, SCLR, SSET, SINIT, THRESH0, Q_THRESH0, THRESH1, Q_THRESH1, Q); + + parameter C_AINIT_VAL = "0"; + parameter C_COUNT_BY = ""; + parameter C_COUNT_MODE = `c_up; + parameter C_COUNT_TO = "1111111111111111"; + parameter C_ENABLE_RLOCS = 1; + parameter C_HAS_ACLR = 0; + parameter C_HAS_AINIT = 0; + parameter C_HAS_ASET = 0; + parameter C_HAS_CE = 0; + parameter C_HAS_IV = 0; + parameter C_HAS_L = 0; + parameter C_HAS_LOAD = 0; + parameter C_HAS_Q_THRESH0 = 0; + parameter C_HAS_Q_THRESH1 = 0; + parameter C_HAS_SCLR = 0; + parameter C_HAS_SINIT = 0; + parameter C_HAS_SSET = 0; + parameter C_HAS_THRESH0 = 0; + parameter C_HAS_THRESH1 = 0; + parameter C_HAS_UP = 0; + parameter C_LOAD_ENABLE = `c_no_override; + parameter C_LOAD_LOW = 0; + parameter C_PIPE_STAGES = 0; + parameter C_RESTRICT_COUNT = 0; + parameter C_SINIT_VAL = "0"; + parameter C_SYNC_ENABLE = `c_override; + parameter C_SYNC_PRIORITY = `c_clear; + parameter C_THRESH0_VALUE = "1111111111111111"; + parameter C_THRESH1_VALUE = "1111111111111111"; + parameter C_THRESH_EARLY = 1; + parameter C_WIDTH = 16; + + parameter C_OUT_TYPE = `c_signed; + parameter adder_HAS_SCLR = ((C_RESTRICT_COUNT == 1) || (C_HAS_SCLR == 1) ? 1 : 0); + + parameter iaxero = {62{"0"}}; + parameter iextendC_THRESH0_VALUE = {iaxero,C_THRESH0_VALUE}; + parameter iextendC_THRESH1_VALUE = {iaxero,C_THRESH1_VALUE}; + parameter iazero = {64{"0"}}; + parameter intC_HAS_SCLR0 = (iextendC_THRESH0_VALUE[0] == "0" ? (iextendC_THRESH0_VALUE[1] == "0" ? + (iextendC_THRESH0_VALUE[2] == "0" ? (iextendC_THRESH0_VALUE[3] == "0" ? + (iextendC_THRESH0_VALUE[4] == "0" ? (iextendC_THRESH0_VALUE[5] == "0" ? + (iextendC_THRESH0_VALUE[6] == "0" ? (iextendC_THRESH0_VALUE[7] == "0" ? + (iextendC_THRESH0_VALUE[8] == "0" ? (iextendC_THRESH0_VALUE[9] == "0" ? + (iextendC_THRESH0_VALUE[10] == "0" ? (iextendC_THRESH0_VALUE[11] == "0" ? + (iextendC_THRESH0_VALUE[12] == "0" ? (iextendC_THRESH0_VALUE[13] == "0" ? + (iextendC_THRESH0_VALUE[14] == "0" ? (iextendC_THRESH0_VALUE[15] == "0" ? + (iextendC_THRESH0_VALUE[16] == "0" ? (iextendC_THRESH0_VALUE[17] == "0" ? + (iextendC_THRESH0_VALUE[18] == "0" ? (iextendC_THRESH0_VALUE[19] == "0" ? + (iextendC_THRESH0_VALUE[20] == "0" ? (iextendC_THRESH0_VALUE[21] == "0" ? + (iextendC_THRESH0_VALUE[22] == "0" ? (iextendC_THRESH0_VALUE[23] == "0" ? + (iextendC_THRESH0_VALUE[24] == "0" ? (iextendC_THRESH0_VALUE[25] == "0" ? + (iextendC_THRESH0_VALUE[26] == "0" ? (iextendC_THRESH0_VALUE[27] == "0" ? + (iextendC_THRESH0_VALUE[28] == "0" ? (iextendC_THRESH0_VALUE[29] == "0" ? + (iextendC_THRESH0_VALUE[30] == "0" ? (iextendC_THRESH0_VALUE[31] == "0" ? + (iextendC_THRESH0_VALUE[32] == "0" ? (iextendC_THRESH0_VALUE[33] == "0" ? + (iextendC_THRESH0_VALUE[34] == "0" ? (iextendC_THRESH0_VALUE[35] == "0" ? + (iextendC_THRESH0_VALUE[36] == "0" ? (iextendC_THRESH0_VALUE[37] == "0" ? + (iextendC_THRESH0_VALUE[38] == "0" ? (iextendC_THRESH0_VALUE[39] == "0" ? + (iextendC_THRESH0_VALUE[40] == "0" ? (iextendC_THRESH0_VALUE[41] == "0" ? + (iextendC_THRESH0_VALUE[42] == "0" ? (iextendC_THRESH0_VALUE[43] == "0" ? + (iextendC_THRESH0_VALUE[44] == "0" ? (iextendC_THRESH0_VALUE[45] == "0" ? + (iextendC_THRESH0_VALUE[46] == "0" ? (iextendC_THRESH0_VALUE[47] == "0" ? + (iextendC_THRESH0_VALUE[48] == "0" ? (iextendC_THRESH0_VALUE[49] == "0" ? + (iextendC_THRESH0_VALUE[50] == "0" ? (iextendC_THRESH0_VALUE[51] == "0" ? + (iextendC_THRESH0_VALUE[52] == "0" ? (iextendC_THRESH0_VALUE[53] == "0" ? + (iextendC_THRESH0_VALUE[54] == "0" ? (iextendC_THRESH0_VALUE[55] == "0" ? + (iextendC_THRESH0_VALUE[56] == "0" ? (iextendC_THRESH0_VALUE[57] == "0" ? + (iextendC_THRESH0_VALUE[58] == "0" ? (iextendC_THRESH0_VALUE[59] == "0" ? + (iextendC_THRESH0_VALUE[60] == "0" ? (iextendC_THRESH0_VALUE[61] == "0" ? + (iextendC_THRESH0_VALUE[62] == "0" ? (iextendC_THRESH0_VALUE[63] == "0" ? 0 + : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) + : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) + : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) + : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) + : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) + : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) + : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) + : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) + : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) + : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) + : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) + : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) + : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) + : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) + : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) + : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) + : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) + : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) + : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) + : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) + : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) + : (C_HAS_SCLR == 1 ? 1 : 0)); + parameter intC_HAS_SCLR1 = (iextendC_THRESH1_VALUE[0] == "0" ? (iextendC_THRESH1_VALUE[1] == "0" ? + (iextendC_THRESH1_VALUE[2] == "0" ? (iextendC_THRESH1_VALUE[3] == "0" ? + (iextendC_THRESH1_VALUE[4] == "0" ? (iextendC_THRESH1_VALUE[5] == "0" ? + (iextendC_THRESH1_VALUE[6] == "0" ? (iextendC_THRESH1_VALUE[7] == "0" ? + (iextendC_THRESH1_VALUE[8] == "0" ? (iextendC_THRESH1_VALUE[9] == "0" ? + (iextendC_THRESH1_VALUE[10] == "0" ? (iextendC_THRESH1_VALUE[11] == "0" ? + (iextendC_THRESH1_VALUE[12] == "0" ? (iextendC_THRESH1_VALUE[13] == "0" ? + (iextendC_THRESH1_VALUE[14] == "0" ? (iextendC_THRESH1_VALUE[15] == "0" ? + (iextendC_THRESH1_VALUE[16] == "0" ? (iextendC_THRESH1_VALUE[17] == "0" ? + (iextendC_THRESH1_VALUE[18] == "0" ? (iextendC_THRESH1_VALUE[19] == "0" ? + (iextendC_THRESH1_VALUE[20] == "0" ? (iextendC_THRESH1_VALUE[21] == "0" ? + (iextendC_THRESH1_VALUE[22] == "0" ? (iextendC_THRESH1_VALUE[23] == "0" ? + (iextendC_THRESH1_VALUE[24] == "0" ? (iextendC_THRESH1_VALUE[25] == "0" ? + (iextendC_THRESH1_VALUE[26] == "0" ? (iextendC_THRESH1_VALUE[27] == "0" ? + (iextendC_THRESH1_VALUE[28] == "0" ? (iextendC_THRESH1_VALUE[29] == "0" ? + (iextendC_THRESH1_VALUE[30] == "0" ? (iextendC_THRESH1_VALUE[31] == "0" ? + (iextendC_THRESH1_VALUE[32] == "0" ? (iextendC_THRESH1_VALUE[33] == "0" ? + (iextendC_THRESH1_VALUE[34] == "0" ? (iextendC_THRESH1_VALUE[35] == "0" ? + (iextendC_THRESH1_VALUE[36] == "0" ? (iextendC_THRESH1_VALUE[37] == "0" ? + (iextendC_THRESH1_VALUE[38] == "0" ? (iextendC_THRESH1_VALUE[39] == "0" ? + (iextendC_THRESH1_VALUE[40] == "0" ? (iextendC_THRESH1_VALUE[41] == "0" ? + (iextendC_THRESH1_VALUE[42] == "0" ? (iextendC_THRESH1_VALUE[43] == "0" ? + (iextendC_THRESH1_VALUE[44] == "0" ? (iextendC_THRESH1_VALUE[45] == "0" ? + (iextendC_THRESH1_VALUE[46] == "0" ? (iextendC_THRESH1_VALUE[47] == "0" ? + (iextendC_THRESH1_VALUE[48] == "0" ? (iextendC_THRESH1_VALUE[49] == "0" ? + (iextendC_THRESH1_VALUE[50] == "0" ? (iextendC_THRESH1_VALUE[51] == "0" ? + (iextendC_THRESH1_VALUE[52] == "0" ? (iextendC_THRESH1_VALUE[53] == "0" ? + (iextendC_THRESH1_VALUE[54] == "0" ? (iextendC_THRESH1_VALUE[55] == "0" ? + (iextendC_THRESH1_VALUE[56] == "0" ? (iextendC_THRESH1_VALUE[57] == "0" ? + (iextendC_THRESH1_VALUE[58] == "0" ? (iextendC_THRESH1_VALUE[59] == "0" ? + (iextendC_THRESH1_VALUE[60] == "0" ? (iextendC_THRESH1_VALUE[61] == "0" ? + (iextendC_THRESH1_VALUE[62] == "0" ? (iextendC_THRESH1_VALUE[63] == "0" ? 0 + : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) + : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) + : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) + : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) + : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) + : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) + : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) + : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) + : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) + : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) + : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) + : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) + : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) + : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) + : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) + : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) + : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) + : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) + : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) + : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) + : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) + : (C_HAS_SCLR == 1 ? 1 : 0)); + + + + + + input CLK; + input UP; + input CE; + input LOAD; + input [C_WIDTH-1 : 0] L; + input [C_WIDTH-1 : 0] IV; + input ACLR; + input ASET; + input AINIT; + input SCLR; + input SSET; + input SINIT; + output THRESH0; + output Q_THRESH0; + output THRESH1; + output Q_THRESH1; + output [C_WIDTH-1 : 0] Q; + + // Internal values to drive signals when input is missing + wire intUP; + wire intUPbar = ~intUP; + wire intCE; + wire intLOAD; + wire [C_WIDTH-1 : 0] intL; + wire [C_WIDTH-1 : 0] intB; + wire [C_WIDTH-1 : 0] all_zeros = {C_WIDTH{1'b0}}; + wire intSCLR; + wire intCount_to_reached; + reg intTHRESH0; + reg intTHRESH1; + wire intQ_THRESH0; + wire intQ_THRESH1; + wire [C_WIDTH-1 : 0] intFBq; + wire [C_WIDTH-1 : 0] intFBs; + wire [C_WIDTH-1 : 0] intQ = intFBq; + wire [C_WIDTH-1 : 0] intFBq_or_zero; + wire [C_WIDTH-1 : 0] intFBs_or_q; + wire [C_WIDTH-1 : 0] intCount_by = to_bits(C_COUNT_BY); + wire [C_WIDTH-1 : 0] intB_or_load; + wire [C_WIDTH-1 : 0] tmpintB_or_load; + + wire Q_THRESH0 = (C_HAS_Q_THRESH0 == 1 ? intQ_THRESH0 : 1'bx); + wire Q_THRESH1 = (C_HAS_Q_THRESH1 == 1 ? intQ_THRESH1 : 1'bx); + wire [C_WIDTH-1 : 0] Q = intQ; + + wire [C_WIDTH-1 : 0] intXLOADMUX; + wire [C_WIDTH-1 : 0] intSINITVAL = to_bits(C_SINIT_VAL); + wire [C_WIDTH-1 : 0] intXL; + wire intXLOAD; + wire intXXLOAD; + wire #5 intSCLR_RESET = (intSCLR || (intCount_to_reached && intCE && C_RESTRICT_COUNT == 1)) && ~intXXLOAD; + + // Sort out default values for missing ports + + assign intUP = (C_HAS_UP == 1 ? UP : (C_COUNT_MODE == `c_up ? 1'b1 : 1'b0)); + assign intCE = defval(CE, C_HAS_CE, 1); + assign intL = (C_HAS_L == 1 ? L : {C_WIDTH{1'b0}}); + assign intB = (C_HAS_IV == 1 ? IV : intCount_by); + assign intXL = (C_RESTRICT_COUNT == 1 ? (C_HAS_SINIT == 1 ? (C_HAS_LOAD == 1 ? intXLOADMUX : intSINITVAL) : intL) : intL); + assign intLOAD = (C_LOAD_LOW == 1 ? ~LOAD : LOAD ); + assign intXLOAD = (C_RESTRICT_COUNT == 1 ? (C_HAS_SINIT == 1 ? (C_HAS_LOAD == 1 ? (C_HAS_CE == 1 ? (C_SYNC_ENABLE != C_LOAD_ENABLE ? (C_SYNC_ENABLE == 0 ? (C_LOAD_LOW == 1 ? (((~SINIT) && (~CE)) || ((~SINIT) && LOAD && CE)) : (SINIT || (LOAD && CE))) : (C_LOAD_LOW == 1 ? ((LOAD && (~CE)) || ((~SINIT) && LOAD && CE)) : (LOAD || (SINIT && CE)))) : (C_LOAD_LOW == 1 ? LOAD && ~SINIT : LOAD || SINIT)) : (C_LOAD_LOW == 1 ? LOAD && ~SINIT : LOAD || SINIT)) : (C_LOAD_LOW ? ~SINIT : SINIT)) : (C_HAS_LOAD == 1 ? LOAD : 1'b0)) : (C_HAS_LOAD == 1 ? LOAD : 1'b0)); + assign intXXLOAD = (C_RESTRICT_COUNT == 1 ? (C_HAS_SINIT == 1 ? (C_HAS_LOAD == 1 ? (C_LOAD_LOW == 1 ? ~intXLOAD : intXLOAD) : (C_LOAD_LOW == 1 ? ~intXLOAD : intXLOAD)) : (C_HAS_LOAD == 1 ? intLOAD : 1'b0)) : (C_HAS_LOAD == 1 ? intLOAD : 1'b0)); + assign intSCLR = defval(SCLR, C_HAS_SCLR, 0); + assign intB_or_load = (C_HAS_LOAD == 1 ? tmpintB_or_load : (C_RESTRICT_COUNT == 1 ? (C_HAS_SINIT == 1 ? tmpintB_or_load : intB) : intB)); + assign intFBs_or_q = (C_THRESH_EARLY == 1 ? intFBs : intFBq); + + + // The addsub on which this is based... + + C_ADDSUB_V4_0 #(C_COUNT_MODE, + C_AINIT_VAL, + C_OUT_TYPE, + C_WIDTH, + (((~(C_HAS_LOAD===1)) || C_LOAD_ENABLE) && (C_SYNC_ENABLE || ~(C_RESTRICT_COUNT && C_HAS_SINIT))), + C_LOAD_LOW, // DLUNN CHANGED FROM 0, + 0, + C_OUT_TYPE, + "", + C_WIDTH, + C_ENABLE_RLOCS, + C_HAS_ACLR, + C_HAS_UP, + C_HAS_AINIT, + C_HAS_ASET, + 0, + C_HAS_LOAD || (C_RESTRICT_COUNT == 1 && C_HAS_SINIT == 1), // DLUNN CHANGED FROM 1, + 0, + 0, + 0, + C_HAS_CE, + 1, + 0, + 0, + 1, + 0, + 0, + 0, + 1, + adder_HAS_SCLR, + C_HAS_SINIT && ~(C_RESTRICT_COUNT === 1), + C_HAS_SSET, + C_WIDTH-1, + 1, + 0, + C_WIDTH, + C_PIPE_STAGES, + C_SINIT_VAL, + C_SYNC_ENABLE, + C_SYNC_PRIORITY) + the_addsub (.A(intFBq_or_zero), .B(intB_or_load), .CLK(CLK), .ADD(intUP), + .CE(CE), .C_IN(intUPbar), .ACLR(ACLR), .ASET(ASET), + .AINIT(AINIT), .SCLR(intSCLR_RESET), .SSET(SSET), + .SINIT(SINIT), .BYPASS(intXLOAD), .S(intFBs), .Q(intFBq)); + + // The Restrict Count/Sinit LOAD mux + + C_MUX_BUS_V4_0 #("", C_ENABLE_RLOCS, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 2, + 0, 0, 1, "", 0, 0, C_WIDTH) + mxRCSL(.MA(intSINITVAL), .MB(intL), .S(intLOAD), .O(intXLOADMUX)); + + // The feedback mux + + C_MUX_BUS_V4_0 #("", C_ENABLE_RLOCS, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 2, + 0, 0, 1, "", 0, 0, C_WIDTH) + mxfb(.MA(intFBq), .MB(all_zeros), .S(intXXLOAD), .O(intFBq_or_zero)); + + // The LOAD mux + + C_MUX_BUS_V4_0 #("", C_ENABLE_RLOCS, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 2, + 0, 0, 1, "", 0, 0, C_WIDTH) + mx1(.MA(intB), .MB(intXL), .S(intXXLOAD), .O(tmpintB_or_load)); + + // The Threshhold comparators + + C_COMPARE_V4_0 #("0", 1, C_THRESH0_VALUE, C_OUT_TYPE, C_ENABLE_RLOCS, C_HAS_ACLR, 0, + C_HAS_THRESH0, 0, 0, 0, 0, 0, C_HAS_CE, C_HAS_Q_THRESH0, + 0, 0, 0, 0, 0, intC_HAS_SCLR0, 0, 0, 0, 0, C_WIDTH) + th0(.A(intFBs_or_q), .CLK(CLK), .CE(CE), .ACLR(ACLR), .SCLR(intSCLR_RESET), .A_EQ_B(THRESH0), .QA_EQ_B(Q_THRESH0)); + + C_COMPARE_V4_0 #("0", 1, C_THRESH1_VALUE, C_OUT_TYPE, C_ENABLE_RLOCS, C_HAS_ACLR, 0, + C_HAS_THRESH1, 0, 0, 0, 0, 0, C_HAS_CE, C_HAS_Q_THRESH1, + 0, 0, 0, 0, 0, intC_HAS_SCLR1, 0, 0, 0, 0, C_WIDTH) + th1(.A(intFBs_or_q), .CLK(CLK), .CE(CE), .ACLR(ACLR), .SCLR(intSCLR_RESET), .A_EQ_B(THRESH1), .QA_EQ_B(Q_THRESH1)); + + C_COMPARE_V4_0 #("0", 1, C_COUNT_TO, C_OUT_TYPE, C_ENABLE_RLOCS, C_HAS_ACLR, 0, + 0, 0, 0, 0, 0, 0, C_HAS_CE, 1, + 0, 0, 0, 0, 0, C_HAS_SCLR, 0, 0, 0, 0, C_WIDTH) + th_to(.A(intFBs), .CLK(CLK), .CE(CE), .ACLR(ACLR), .SCLR(SCLR), .QA_EQ_B(intCount_to_reached)); + + initial + begin + + #1; + + + end + + function defval; + input i; + input hassig; + input val; + begin + if(hassig == 1) + defval = i; + else + defval = val; + end + endfunction + + function [C_WIDTH - 1 : 0] to_bits; + input [C_WIDTH*8 : 1] instring; + integer i; + begin + for(i = C_WIDTH; i > 0; i = i - 1) + begin // Is this character a '0'? (ASCII = 48 = 00110000) + if(instring[(i*8)] == 0 && + instring[(i*8)-1] == 0 && + instring[(i*8)-2] == 1 && + instring[(i*8)-3] == 1 && + instring[(i*8)-4] == 0 && + instring[(i*8)-5] == 0 && + instring[(i*8)-6] == 0 && + instring[(i*8)-7] == 0) + to_bits[i-1] = 0; + // Or is it a '1'? + else if(instring[(i*8)] == 0 && + instring[(i*8)-1] == 0 && + instring[(i*8)-2] == 1 && + instring[(i*8)-3] == 1 && + instring[(i*8)-4] == 0 && + instring[(i*8)-5] == 0 && + instring[(i*8)-6] == 0 && + instring[(i*8)-7] == 1) + + to_bits[i-1] = 1; + // Or is it a ' '? (a null char - in which case insert a '0') + else if(instring[(i*8)] == 0 && + instring[(i*8)-1] == 0 && + instring[(i*8)-2] == 0 && + instring[(i*8)-3] == 0 && + instring[(i*8)-4] == 0 && + instring[(i*8)-5] == 0 && + instring[(i*8)-6] == 0 && + instring[(i*8)-7] == 0) + to_bits[i-1] = 0; + else + begin + $display("Error: non-binary digit in string \"%s\"\nExiting simulation...", instring); + $finish; + end + end + end + endfunction + + + +endmodule + +`undef c_set +`undef c_clear +`undef c_override +`undef c_no_override +`undef c_signed +`undef c_unsigned +`undef c_pin +`undef c_up +`undef c_down +`undef c_updown +`undef allXs + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/C_COUNTER_BINARY_V5_0.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/C_COUNTER_BINARY_V5_0.v new file mode 100644 index 0000000..bb10672 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/C_COUNTER_BINARY_V5_0.v @@ -0,0 +1,440 @@ +/* $Id: C_COUNTER_BINARY_V5_0.v,v 1.17 2008/09/08 20:05:55 akennedy Exp $ +-- +-- Filename - C_COUNTER_BINARY_V5_0.v +-- Author - Xilinx +-- Creation -14 July 1999 +-- +-- Description - This file contains the Verilog behavior for the Baseblocks C_COUNTER_BINARY_V5_0 module +*/ + +`timescale 1ns/10ps + +`define c_set 0 +`define c_clear 1 +`define c_override 0 +`define c_no_override 1 +`define c_signed 0 +`define c_unsigned 1 +`define c_pin 2 +`define c_up 0 +`define c_down 1 +`define c_updown 2 +`define allXs {C_WIDTH{1'bx}} + +module C_COUNTER_BINARY_V5_0 (CLK, UP, CE, LOAD, L, IV, ACLR, ASET, AINIT, SCLR, SSET, SINIT, THRESH0, Q_THRESH0, THRESH1, Q_THRESH1, Q); + + parameter C_AINIT_VAL = "0"; + parameter C_COUNT_BY = ""; + parameter C_COUNT_MODE = `c_up; + parameter C_COUNT_TO = "1111111111111111"; + parameter C_ENABLE_RLOCS = 1; + parameter C_HAS_ACLR = 0; + parameter C_HAS_AINIT = 0; + parameter C_HAS_ASET = 0; + parameter C_HAS_CE = 0; + parameter C_HAS_IV = 0; + parameter C_HAS_L = 0; + parameter C_HAS_LOAD = 0; + parameter C_HAS_Q_THRESH0 = 0; + parameter C_HAS_Q_THRESH1 = 0; + parameter C_HAS_SCLR = 0; + parameter C_HAS_SINIT = 0; + parameter C_HAS_SSET = 0; + parameter C_HAS_THRESH0 = 0; + parameter C_HAS_THRESH1 = 0; + parameter C_HAS_UP = 0; + parameter C_LOAD_ENABLE = `c_no_override; + parameter C_LOAD_LOW = 0; + parameter C_PIPE_STAGES = 0; + parameter C_RESTRICT_COUNT = 0; + parameter C_SINIT_VAL = "0"; + parameter C_SYNC_ENABLE = `c_override; + parameter C_SYNC_PRIORITY = `c_clear; + parameter C_THRESH0_VALUE = "1111111111111111"; + parameter C_THRESH1_VALUE = "1111111111111111"; + parameter C_THRESH_EARLY = 1; + parameter C_WIDTH = 16; + + parameter C_OUT_TYPE = `c_signed; + parameter adder_HAS_SCLR = ((C_RESTRICT_COUNT == 1) || (C_HAS_SCLR == 1) ? 1 : 0); + + parameter iaxero = {62{"0"}}; + parameter iextendC_THRESH0_VALUE = {iaxero,C_THRESH0_VALUE}; + parameter iextendC_THRESH1_VALUE = {iaxero,C_THRESH1_VALUE}; + parameter iazero = {64{"0"}}; + parameter intC_HAS_SCLR0 = (iextendC_THRESH0_VALUE[0] == "0" ? (iextendC_THRESH0_VALUE[1] == "0" ? + (iextendC_THRESH0_VALUE[2] == "0" ? (iextendC_THRESH0_VALUE[3] == "0" ? + (iextendC_THRESH0_VALUE[4] == "0" ? (iextendC_THRESH0_VALUE[5] == "0" ? + (iextendC_THRESH0_VALUE[6] == "0" ? (iextendC_THRESH0_VALUE[7] == "0" ? + (iextendC_THRESH0_VALUE[8] == "0" ? (iextendC_THRESH0_VALUE[9] == "0" ? + (iextendC_THRESH0_VALUE[10] == "0" ? (iextendC_THRESH0_VALUE[11] == "0" ? + (iextendC_THRESH0_VALUE[12] == "0" ? (iextendC_THRESH0_VALUE[13] == "0" ? + (iextendC_THRESH0_VALUE[14] == "0" ? (iextendC_THRESH0_VALUE[15] == "0" ? + (iextendC_THRESH0_VALUE[16] == "0" ? (iextendC_THRESH0_VALUE[17] == "0" ? + (iextendC_THRESH0_VALUE[18] == "0" ? (iextendC_THRESH0_VALUE[19] == "0" ? + (iextendC_THRESH0_VALUE[20] == "0" ? (iextendC_THRESH0_VALUE[21] == "0" ? + (iextendC_THRESH0_VALUE[22] == "0" ? (iextendC_THRESH0_VALUE[23] == "0" ? + (iextendC_THRESH0_VALUE[24] == "0" ? (iextendC_THRESH0_VALUE[25] == "0" ? + (iextendC_THRESH0_VALUE[26] == "0" ? (iextendC_THRESH0_VALUE[27] == "0" ? + (iextendC_THRESH0_VALUE[28] == "0" ? (iextendC_THRESH0_VALUE[29] == "0" ? + (iextendC_THRESH0_VALUE[30] == "0" ? (iextendC_THRESH0_VALUE[31] == "0" ? + (iextendC_THRESH0_VALUE[32] == "0" ? (iextendC_THRESH0_VALUE[33] == "0" ? + (iextendC_THRESH0_VALUE[34] == "0" ? (iextendC_THRESH0_VALUE[35] == "0" ? + (iextendC_THRESH0_VALUE[36] == "0" ? (iextendC_THRESH0_VALUE[37] == "0" ? + (iextendC_THRESH0_VALUE[38] == "0" ? (iextendC_THRESH0_VALUE[39] == "0" ? + (iextendC_THRESH0_VALUE[40] == "0" ? (iextendC_THRESH0_VALUE[41] == "0" ? + (iextendC_THRESH0_VALUE[42] == "0" ? (iextendC_THRESH0_VALUE[43] == "0" ? + (iextendC_THRESH0_VALUE[44] == "0" ? (iextendC_THRESH0_VALUE[45] == "0" ? + (iextendC_THRESH0_VALUE[46] == "0" ? (iextendC_THRESH0_VALUE[47] == "0" ? + (iextendC_THRESH0_VALUE[48] == "0" ? (iextendC_THRESH0_VALUE[49] == "0" ? + (iextendC_THRESH0_VALUE[50] == "0" ? (iextendC_THRESH0_VALUE[51] == "0" ? + (iextendC_THRESH0_VALUE[52] == "0" ? (iextendC_THRESH0_VALUE[53] == "0" ? + (iextendC_THRESH0_VALUE[54] == "0" ? (iextendC_THRESH0_VALUE[55] == "0" ? + (iextendC_THRESH0_VALUE[56] == "0" ? (iextendC_THRESH0_VALUE[57] == "0" ? + (iextendC_THRESH0_VALUE[58] == "0" ? (iextendC_THRESH0_VALUE[59] == "0" ? + (iextendC_THRESH0_VALUE[60] == "0" ? (iextendC_THRESH0_VALUE[61] == "0" ? + (iextendC_THRESH0_VALUE[62] == "0" ? (iextendC_THRESH0_VALUE[63] == "0" ? 0 + : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) + : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) + : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) + : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) + : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) + : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) + : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) + : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) + : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) + : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) + : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) + : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) + : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) + : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) + : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) + : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) + : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) + : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) + : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) + : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) + : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) + : (C_HAS_SCLR == 1 ? 1 : 0)); + parameter intC_HAS_SCLR1 = (iextendC_THRESH1_VALUE[0] == "0" ? (iextendC_THRESH1_VALUE[1] == "0" ? + (iextendC_THRESH1_VALUE[2] == "0" ? (iextendC_THRESH1_VALUE[3] == "0" ? + (iextendC_THRESH1_VALUE[4] == "0" ? (iextendC_THRESH1_VALUE[5] == "0" ? + (iextendC_THRESH1_VALUE[6] == "0" ? (iextendC_THRESH1_VALUE[7] == "0" ? + (iextendC_THRESH1_VALUE[8] == "0" ? (iextendC_THRESH1_VALUE[9] == "0" ? + (iextendC_THRESH1_VALUE[10] == "0" ? (iextendC_THRESH1_VALUE[11] == "0" ? + (iextendC_THRESH1_VALUE[12] == "0" ? (iextendC_THRESH1_VALUE[13] == "0" ? + (iextendC_THRESH1_VALUE[14] == "0" ? (iextendC_THRESH1_VALUE[15] == "0" ? + (iextendC_THRESH1_VALUE[16] == "0" ? (iextendC_THRESH1_VALUE[17] == "0" ? + (iextendC_THRESH1_VALUE[18] == "0" ? (iextendC_THRESH1_VALUE[19] == "0" ? + (iextendC_THRESH1_VALUE[20] == "0" ? (iextendC_THRESH1_VALUE[21] == "0" ? + (iextendC_THRESH1_VALUE[22] == "0" ? (iextendC_THRESH1_VALUE[23] == "0" ? + (iextendC_THRESH1_VALUE[24] == "0" ? (iextendC_THRESH1_VALUE[25] == "0" ? + (iextendC_THRESH1_VALUE[26] == "0" ? (iextendC_THRESH1_VALUE[27] == "0" ? + (iextendC_THRESH1_VALUE[28] == "0" ? (iextendC_THRESH1_VALUE[29] == "0" ? + (iextendC_THRESH1_VALUE[30] == "0" ? (iextendC_THRESH1_VALUE[31] == "0" ? + (iextendC_THRESH1_VALUE[32] == "0" ? (iextendC_THRESH1_VALUE[33] == "0" ? + (iextendC_THRESH1_VALUE[34] == "0" ? (iextendC_THRESH1_VALUE[35] == "0" ? + (iextendC_THRESH1_VALUE[36] == "0" ? (iextendC_THRESH1_VALUE[37] == "0" ? + (iextendC_THRESH1_VALUE[38] == "0" ? (iextendC_THRESH1_VALUE[39] == "0" ? + (iextendC_THRESH1_VALUE[40] == "0" ? (iextendC_THRESH1_VALUE[41] == "0" ? + (iextendC_THRESH1_VALUE[42] == "0" ? (iextendC_THRESH1_VALUE[43] == "0" ? + (iextendC_THRESH1_VALUE[44] == "0" ? (iextendC_THRESH1_VALUE[45] == "0" ? + (iextendC_THRESH1_VALUE[46] == "0" ? (iextendC_THRESH1_VALUE[47] == "0" ? + (iextendC_THRESH1_VALUE[48] == "0" ? (iextendC_THRESH1_VALUE[49] == "0" ? + (iextendC_THRESH1_VALUE[50] == "0" ? (iextendC_THRESH1_VALUE[51] == "0" ? + (iextendC_THRESH1_VALUE[52] == "0" ? (iextendC_THRESH1_VALUE[53] == "0" ? + (iextendC_THRESH1_VALUE[54] == "0" ? (iextendC_THRESH1_VALUE[55] == "0" ? + (iextendC_THRESH1_VALUE[56] == "0" ? (iextendC_THRESH1_VALUE[57] == "0" ? + (iextendC_THRESH1_VALUE[58] == "0" ? (iextendC_THRESH1_VALUE[59] == "0" ? + (iextendC_THRESH1_VALUE[60] == "0" ? (iextendC_THRESH1_VALUE[61] == "0" ? + (iextendC_THRESH1_VALUE[62] == "0" ? (iextendC_THRESH1_VALUE[63] == "0" ? 0 + : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) + : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) + : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) + : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) + : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) + : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) + : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) + : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) + : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) + : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) + : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) + : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) + : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) + : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) + : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) + : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) + : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) + : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) + : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) + : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) + : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) + : (C_HAS_SCLR == 1 ? 1 : 0)); + + + + + + input CLK; + input UP; + input CE; + input LOAD; + input [C_WIDTH-1 : 0] L; + input [C_WIDTH-1 : 0] IV; + input ACLR; + input ASET; + input AINIT; + input SCLR; + input SSET; + input SINIT; + output THRESH0; + output Q_THRESH0; + output THRESH1; + output Q_THRESH1; + output [C_WIDTH-1 : 0] Q; + + // Internal values to drive signals when input is missing + wire intUP; + wire intUPbar = ~intUP; + wire intCE; + wire intLOAD; + wire [C_WIDTH-1 : 0] intL; + wire [C_WIDTH-1 : 0] intB; + wire [C_WIDTH-1 : 0] all_zeros = {C_WIDTH{1'b0}}; + wire intSCLR; + wire intCount_to_reached; + reg intTHRESH0; + reg intTHRESH1; + wire intQ_THRESH0; + wire intQ_THRESH1; + wire [C_WIDTH-1 : 0] intFBq; + wire [C_WIDTH-1 : 0] intFBs; + wire [C_WIDTH-1 : 0] intQ = intFBq; + wire [C_WIDTH-1 : 0] intFBq_or_zero; + wire [C_WIDTH-1 : 0] intFBs_or_q; + wire [C_WIDTH-1 : 0] intCount_by = to_bits(C_COUNT_BY); + wire [C_WIDTH-1 : 0] intB_or_load; + wire [C_WIDTH-1 : 0] tmpintB_or_load; + + wire Q_THRESH0 = (C_HAS_Q_THRESH0 == 1 ? intQ_THRESH0 : 1'bx); + wire Q_THRESH1 = (C_HAS_Q_THRESH1 == 1 ? intQ_THRESH1 : 1'bx); + wire [C_WIDTH-1 : 0] Q = intQ; + + wire [C_WIDTH-1 : 0] intXLOADMUX; + wire [C_WIDTH-1 : 0] intSINITVAL = to_bits(C_SINIT_VAL); + wire [C_WIDTH-1 : 0] intXL; + wire intXLOAD; + wire intXXLOAD; + wire #5 intSCLR_RESET = (intSCLR || (intCount_to_reached && intCE && C_RESTRICT_COUNT == 1)) && ~intXXLOAD; + + // Sort out default values for missing ports + + assign intUP = (C_HAS_UP == 1 ? UP : (C_COUNT_MODE == `c_up ? 1'b1 : 1'b0)); + assign intCE = defval(CE, C_HAS_CE, 1); + assign intL = (C_HAS_L == 1 ? L : {C_WIDTH{1'b0}}); + assign intB = (C_HAS_IV == 1 ? IV : intCount_by); + assign intXL = (C_RESTRICT_COUNT == 1 ? (C_HAS_SINIT == 1 ? (C_HAS_LOAD == 1 ? intXLOADMUX : intSINITVAL) : intL) : intL); + assign intLOAD = (C_LOAD_LOW == 1 ? ~LOAD : LOAD ); + assign intXLOAD = (C_RESTRICT_COUNT == 1 ? (C_HAS_SINIT == 1 ? (C_HAS_LOAD == 1 ? (C_HAS_CE == 1 ? (C_SYNC_ENABLE != C_LOAD_ENABLE ? (C_SYNC_ENABLE == 0 ? (C_LOAD_LOW == 1 ? (((~SINIT) && (~CE)) || ((~SINIT) && LOAD && CE)) : (SINIT || (LOAD && CE))) : (C_LOAD_LOW == 1 ? ((LOAD && (~CE)) || ((~SINIT) && LOAD && CE)) : (LOAD || (SINIT && CE)))) : (C_LOAD_LOW == 1 ? LOAD && ~SINIT : LOAD || SINIT)) : (C_LOAD_LOW == 1 ? LOAD && ~SINIT : LOAD || SINIT)) : (C_LOAD_LOW ? ~SINIT : SINIT)) : (C_HAS_LOAD == 1 ? LOAD : 1'b0)) : (C_HAS_LOAD == 1 ? LOAD : 1'b0)); + assign intXXLOAD = (C_RESTRICT_COUNT == 1 ? (C_HAS_SINIT == 1 ? (C_HAS_LOAD == 1 ? (C_LOAD_LOW == 1 ? ~intXLOAD : intXLOAD) : (C_LOAD_LOW == 1 ? ~intXLOAD : intXLOAD)) : (C_HAS_LOAD == 1 ? intLOAD : 1'b0)) : (C_HAS_LOAD == 1 ? intLOAD : 1'b0)); + assign intSCLR = defval(SCLR, C_HAS_SCLR, 0); + assign intB_or_load = (C_HAS_LOAD == 1 ? tmpintB_or_load : (C_RESTRICT_COUNT == 1 ? (C_HAS_SINIT == 1 ? tmpintB_or_load : intB) : intB)); + assign intFBs_or_q = (C_THRESH_EARLY == 1 ? intFBs : intFBq); + + + // The addsub on which this is based... + + C_ADDSUB_V5_0 #(C_COUNT_MODE, + C_AINIT_VAL, + C_OUT_TYPE, + C_WIDTH, + (((~(C_HAS_LOAD===1)) || C_LOAD_ENABLE) && (C_SYNC_ENABLE || ~(C_RESTRICT_COUNT && C_HAS_SINIT))), + C_LOAD_LOW, // DLUNN CHANGED FROM 0, + 0, + C_OUT_TYPE, + "0000000000000000", + C_WIDTH, + C_ENABLE_RLOCS, + C_HAS_ACLR, + C_HAS_UP, + C_HAS_AINIT, + C_HAS_ASET, + 0, + C_HAS_LOAD || (C_RESTRICT_COUNT == 1 && C_HAS_SINIT == 1), // DLUNN CHANGED FROM 1, + 0, + 0, + 0, + 0, + C_HAS_CE, + 1, + 0, + 0, + 1, + 0, + 0, + 0, + 1, + adder_HAS_SCLR, + C_HAS_SINIT && ~(C_RESTRICT_COUNT === 1), + C_HAS_SSET, + C_WIDTH-1, + 1, + 0, + C_WIDTH, + C_PIPE_STAGES, + C_SINIT_VAL, + C_SYNC_ENABLE, + C_SYNC_PRIORITY) + the_addsub (.A(intFBq_or_zero), .B(intB_or_load), .CLK(CLK), .ADD(intUP), + .C_IN(intUPbar), .B_IN(), .CE(CE), .BYPASS(intXLOAD), + .ACLR(ACLR), .ASET(ASET), .AINIT(AINIT), + .SCLR(intSCLR_RESET), .SSET(SSET), .SINIT(SINIT), + .A_SIGNED(), .B_SIGNED(), .OVFL(), .C_OUT(), .B_OUT(), + .Q_OVFL(), .Q_C_OUT(), .Q_B_OUT(), + .S(intFBs), .Q(intFBq)); + + // The Restrict Count/Sinit LOAD mux + + C_MUX_BUS_V5_0 #("", C_ENABLE_RLOCS, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 2, + 0, 0, 1, "", 0, 0, C_WIDTH) + mxRCSL(.MA(intSINITVAL), .MB(intL), .MC(), .MD(), .ME(), .MF(), .MG(), .MH(), + .MAA(), .MAB(), .MAC(), .MAD(), .MAE(), .MAF(), .MAG(), .MAH(), + .MBA(), .MBB(), .MBC(), .MBD(), .MBE(), .MBF(), .MBG(), .MBH(), + .MCA(), .MCB(), .MCC(), .MCD(), .MCE(), .MCF(), .MCG(), .MCH(), + .S(intLOAD), .CLK(), .CE(), .EN(), .ACLR(), .ASET(), .AINIT(), + .SCLR(), .SSET(), .SINIT(), + .O(intXLOADMUX), .Q()); + + // The feedback mux + + C_MUX_BUS_V5_0 #("", C_ENABLE_RLOCS, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 2, + 0, 0, 1, "", 0, 0, C_WIDTH) + mxfb(.MA(intFBq), .MB(all_zeros), .MC(), .MD(), .ME(), .MF(), .MG(), .MH(), + .MAA(), .MAB(), .MAC(), .MAD(), .MAE(), .MAF(), .MAG(), .MAH(), + .MBA(), .MBB(), .MBC(), .MBD(), .MBE(), .MBF(), .MBG(), .MBH(), + .MCA(), .MCB(), .MCC(), .MCD(), .MCE(), .MCF(), .MCG(), .MCH(), + .S(intXXLOAD), .CLK(), .CE(), .EN(), .ACLR(), .ASET(), .AINIT(), + .SCLR(), .SSET(), .SINIT(), + .O(intFBq_or_zero), .Q()); + + // The LOAD mux + + C_MUX_BUS_V5_0 #("", C_ENABLE_RLOCS, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 2, + 0, 0, 1, "", 0, 0, C_WIDTH) + mx1(.MA(intB), .MB(intXL), .MC(), .MD(), .ME(), .MF(), .MG(), .MH(), + .MAA(), .MAB(), .MAC(), .MAD(), .MAE(), .MAF(), .MAG(), .MAH(), + .MBA(), .MBB(), .MBC(), .MBD(), .MBE(), .MBF(), .MBG(), .MBH(), + .MCA(), .MCB(), .MCC(), .MCD(), .MCE(), .MCF(), .MCG(), .MCH(), + .S(intXXLOAD), .CLK(), .CE(), .EN(), .ACLR(), .ASET(), .AINIT(), + .SCLR(), .SSET(), .SINIT(), + .O(tmpintB_or_load), .Q()); + + // The Threshhold comparators + + C_COMPARE_V5_0 #("0", 1, C_THRESH0_VALUE, C_OUT_TYPE, C_ENABLE_RLOCS, C_HAS_ACLR, 0, + C_HAS_THRESH0, 0, 0, 0, 0, 0, C_HAS_CE, C_HAS_Q_THRESH0, + 0, 0, 0, 0, 0, intC_HAS_SCLR0, 0, 0, 0, 0, C_WIDTH) + th0(.A(intFBs_or_q), .B(), .CLK(CLK), .CE(CE), + .ACLR(ACLR), .ASET(), + .SCLR(intSCLR_RESET), .SSET(), + .A_EQ_B(THRESH0), .A_NE_B(), .A_LT_B(), .A_GT_B(), .A_LE_B(), .A_GE_B(), + .QA_EQ_B(Q_THRESH0), .QA_NE_B(), .QA_LT_B(), .QA_GT_B(), .QA_LE_B(), .QA_GE_B()); + + C_COMPARE_V5_0 #("0", 1, C_THRESH1_VALUE, C_OUT_TYPE, C_ENABLE_RLOCS, C_HAS_ACLR, 0, + C_HAS_THRESH1, 0, 0, 0, 0, 0, C_HAS_CE, C_HAS_Q_THRESH1, + 0, 0, 0, 0, 0, intC_HAS_SCLR1, 0, 0, 0, 0, C_WIDTH) + th1(.A(intFBs_or_q), .B(), .CLK(CLK), .CE(CE), + .ACLR(ACLR), .ASET(), + .SCLR(intSCLR_RESET), .SSET(), + .A_EQ_B(THRESH1), .A_NE_B(), .A_LT_B(), .A_GT_B(), .A_LE_B(), .A_GE_B(), + .QA_EQ_B(Q_THRESH1), .QA_NE_B(), .QA_LT_B(), .QA_GT_B(), .QA_LE_B(), .QA_GE_B()); + + C_COMPARE_V5_0 #("0", 1, C_COUNT_TO, C_OUT_TYPE, C_ENABLE_RLOCS, C_HAS_ACLR, 0, + 0, 0, 0, 0, 0, 0, C_HAS_CE, 1, + 0, 0, 0, 0, 0, C_HAS_SCLR, 0, 0, 0, 0, C_WIDTH) + th_to(.A(intFBs), .B(), .CLK(CLK), .CE(CE), + .ACLR(ACLR), .ASET(), + .SCLR(SCLR), .SSET(), + .A_EQ_B(), .A_NE_B(), .A_LT_B(), .A_GT_B(), .A_LE_B(), .A_GE_B(), + .QA_EQ_B(intCount_to_reached), .QA_NE_B(), .QA_LT_B(), .QA_GT_B(), .QA_LE_B(), .QA_GE_B()); + + initial + begin + + #1; + + + end + + function defval; + input i; + input hassig; + input val; + begin + if(hassig == 1) + defval = i; + else + defval = val; + end + endfunction + + function [C_WIDTH - 1 : 0] to_bits; + input [C_WIDTH*8 : 1] instring; + integer i; + begin + for(i = C_WIDTH; i > 0; i = i - 1) + begin // Is this character a '0'? (ASCII = 48 = 00110000) + if(instring[(i*8)] == 0 && + instring[(i*8)-1] == 0 && + instring[(i*8)-2] == 1 && + instring[(i*8)-3] == 1 && + instring[(i*8)-4] == 0 && + instring[(i*8)-5] == 0 && + instring[(i*8)-6] == 0 && + instring[(i*8)-7] == 0) + to_bits[i-1] = 0; + // Or is it a '1'? + else if(instring[(i*8)] == 0 && + instring[(i*8)-1] == 0 && + instring[(i*8)-2] == 1 && + instring[(i*8)-3] == 1 && + instring[(i*8)-4] == 0 && + instring[(i*8)-5] == 0 && + instring[(i*8)-6] == 0 && + instring[(i*8)-7] == 1) + + to_bits[i-1] = 1; + // Or is it a ' '? (a null char - in which case insert a '0') + else if(instring[(i*8)] == 0 && + instring[(i*8)-1] == 0 && + instring[(i*8)-2] == 0 && + instring[(i*8)-3] == 0 && + instring[(i*8)-4] == 0 && + instring[(i*8)-5] == 0 && + instring[(i*8)-6] == 0 && + instring[(i*8)-7] == 0) + to_bits[i-1] = 0; + else + begin + $display("Error in %m at time %d ns : non-binary digit in string \"%s\"\nExiting simulation...", $time, instring); + $finish; + end + end + end + endfunction + + + +endmodule + +`undef c_set +`undef c_clear +`undef c_override +`undef c_no_override +`undef c_signed +`undef c_unsigned +`undef c_pin +`undef c_up +`undef c_down +`undef c_updown +`undef allXs diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/C_COUNTER_BINARY_V6_0.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/C_COUNTER_BINARY_V6_0.v new file mode 100644 index 0000000..aba75ca --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/C_COUNTER_BINARY_V6_0.v @@ -0,0 +1,470 @@ +// Copyright(C) 2002 by Xilinx, Inc. All rights reserved. +// This text contains proprietary, confidential +// information of Xilinx, Inc., is distributed +// under license from Xilinx, Inc., and may be used, +// copied and/or disclosed only pursuant to the terms +// of a valid license agreement with Xilinx, Inc. This copyright +// notice must be retained as part of this text at all times. + + +/* $Id: C_COUNTER_BINARY_V6_0.v,v 1.16 2008/09/08 20:06:04 akennedy Exp $ +-- +-- Filename - C_COUNTER_BINARY_V6_0.v +-- Author - Xilinx +-- Creation -14 July 1999 +-- +-- Description - This file contains the Verilog behavior for the Baseblocks C_COUNTER_BINARY_V6_0 module +*/ + +`timescale 1ns/10ps + +`define c_set 0 +`define c_clear 1 +`define c_override 0 +`define c_no_override 1 +`define c_signed 0 +`define c_unsigned 1 +`define c_pin 2 +`define c_up 0 +`define c_down 1 +`define c_updown 2 +`define allXs {C_WIDTH{1'bx}} + +module C_COUNTER_BINARY_V6_0 (CLK, UP, CE, LOAD, L, IV, ACLR, ASET, AINIT, SCLR, SSET, SINIT, THRESH0, Q_THRESH0, THRESH1, Q_THRESH1, Q); + + parameter C_AINIT_VAL = "0"; + parameter C_COUNT_BY = ""; + parameter C_COUNT_MODE = `c_up; + parameter C_COUNT_TO = "1111111111111111"; + parameter C_ENABLE_RLOCS = 1; + parameter C_HAS_ACLR = 0; + parameter C_HAS_AINIT = 0; + parameter C_HAS_ASET = 0; + parameter C_HAS_CE = 0; + parameter C_HAS_IV = 0; + parameter C_HAS_L = 0; + parameter C_HAS_LOAD = 0; + parameter C_HAS_Q_THRESH0 = 0; + parameter C_HAS_Q_THRESH1 = 0; + parameter C_HAS_SCLR = 0; + parameter C_HAS_SINIT = 0; + parameter C_HAS_SSET = 0; + parameter C_HAS_THRESH0 = 0; + parameter C_HAS_THRESH1 = 0; + parameter C_HAS_UP = 0; + parameter C_LOAD_ENABLE = `c_no_override; + parameter C_LOAD_LOW = 0; + parameter C_PIPE_STAGES = 0; + parameter C_RESTRICT_COUNT = 0; + parameter C_SINIT_VAL = "0"; + parameter C_SYNC_ENABLE = `c_override; + parameter C_SYNC_PRIORITY = `c_clear; + parameter C_THRESH0_VALUE = "1111111111111111"; + parameter C_THRESH1_VALUE = "1111111111111111"; + parameter C_THRESH_EARLY = 1; + parameter C_WIDTH = 16; + + parameter C_OUT_TYPE = `c_signed; + parameter adder_HAS_SCLR = ((C_RESTRICT_COUNT == 1) || (C_HAS_SCLR == 1) ? 1 : 0); + + parameter iaxero = {62{"0"}}; + parameter iextendC_THRESH0_VALUE = {iaxero,C_THRESH0_VALUE}; + parameter iextendC_THRESH1_VALUE = {iaxero,C_THRESH1_VALUE}; + parameter iazero = {64{"0"}}; + parameter TH_TO_HAS_SCLR = ((C_HAS_SCLR == 1 || C_HAS_SSET == 1) ? 1 : 0); + parameter TH_TO_HAS_ASET = ((C_HAS_AINIT && (C_AINIT_VAL == C_COUNT_TO)) ? 1 : 0); + parameter TH_TO_HAS_ACLR = ((C_HAS_ACLR || (C_HAS_AINIT && (C_AINIT_VAL != C_COUNT_TO))) ? 1 : 0); + parameter intC_HAS_SCLR0 = (iextendC_THRESH0_VALUE[0] == "0" ? (iextendC_THRESH0_VALUE[1] == "0" ? + (iextendC_THRESH0_VALUE[2] == "0" ? (iextendC_THRESH0_VALUE[3] == "0" ? + (iextendC_THRESH0_VALUE[4] == "0" ? (iextendC_THRESH0_VALUE[5] == "0" ? + (iextendC_THRESH0_VALUE[6] == "0" ? (iextendC_THRESH0_VALUE[7] == "0" ? + (iextendC_THRESH0_VALUE[8] == "0" ? (iextendC_THRESH0_VALUE[9] == "0" ? + (iextendC_THRESH0_VALUE[10] == "0" ? (iextendC_THRESH0_VALUE[11] == "0" ? + (iextendC_THRESH0_VALUE[12] == "0" ? (iextendC_THRESH0_VALUE[13] == "0" ? + (iextendC_THRESH0_VALUE[14] == "0" ? (iextendC_THRESH0_VALUE[15] == "0" ? + (iextendC_THRESH0_VALUE[16] == "0" ? (iextendC_THRESH0_VALUE[17] == "0" ? + (iextendC_THRESH0_VALUE[18] == "0" ? (iextendC_THRESH0_VALUE[19] == "0" ? + (iextendC_THRESH0_VALUE[20] == "0" ? (iextendC_THRESH0_VALUE[21] == "0" ? + (iextendC_THRESH0_VALUE[22] == "0" ? (iextendC_THRESH0_VALUE[23] == "0" ? + (iextendC_THRESH0_VALUE[24] == "0" ? (iextendC_THRESH0_VALUE[25] == "0" ? + (iextendC_THRESH0_VALUE[26] == "0" ? (iextendC_THRESH0_VALUE[27] == "0" ? + (iextendC_THRESH0_VALUE[28] == "0" ? (iextendC_THRESH0_VALUE[29] == "0" ? + (iextendC_THRESH0_VALUE[30] == "0" ? (iextendC_THRESH0_VALUE[31] == "0" ? + (iextendC_THRESH0_VALUE[32] == "0" ? (iextendC_THRESH0_VALUE[33] == "0" ? + (iextendC_THRESH0_VALUE[34] == "0" ? (iextendC_THRESH0_VALUE[35] == "0" ? + (iextendC_THRESH0_VALUE[36] == "0" ? (iextendC_THRESH0_VALUE[37] == "0" ? + (iextendC_THRESH0_VALUE[38] == "0" ? (iextendC_THRESH0_VALUE[39] == "0" ? + (iextendC_THRESH0_VALUE[40] == "0" ? (iextendC_THRESH0_VALUE[41] == "0" ? + (iextendC_THRESH0_VALUE[42] == "0" ? (iextendC_THRESH0_VALUE[43] == "0" ? + (iextendC_THRESH0_VALUE[44] == "0" ? (iextendC_THRESH0_VALUE[45] == "0" ? + (iextendC_THRESH0_VALUE[46] == "0" ? (iextendC_THRESH0_VALUE[47] == "0" ? + (iextendC_THRESH0_VALUE[48] == "0" ? (iextendC_THRESH0_VALUE[49] == "0" ? + (iextendC_THRESH0_VALUE[50] == "0" ? (iextendC_THRESH0_VALUE[51] == "0" ? + (iextendC_THRESH0_VALUE[52] == "0" ? (iextendC_THRESH0_VALUE[53] == "0" ? + (iextendC_THRESH0_VALUE[54] == "0" ? (iextendC_THRESH0_VALUE[55] == "0" ? + (iextendC_THRESH0_VALUE[56] == "0" ? (iextendC_THRESH0_VALUE[57] == "0" ? + (iextendC_THRESH0_VALUE[58] == "0" ? (iextendC_THRESH0_VALUE[59] == "0" ? + (iextendC_THRESH0_VALUE[60] == "0" ? (iextendC_THRESH0_VALUE[61] == "0" ? + (iextendC_THRESH0_VALUE[62] == "0" ? (iextendC_THRESH0_VALUE[63] == "0" ? 0 + : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) + : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) + : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) + : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) + : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) + : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) + : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) + : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) + : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) + : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) + : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) + : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) + : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) + : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) + : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) + : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) + : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) + : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) + : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) + : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) + : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) + : (C_HAS_SCLR == 1 ? 1 : 0)); + parameter intC_HAS_SCLR1 = (iextendC_THRESH1_VALUE[0] == "0" ? (iextendC_THRESH1_VALUE[1] == "0" ? + (iextendC_THRESH1_VALUE[2] == "0" ? (iextendC_THRESH1_VALUE[3] == "0" ? + (iextendC_THRESH1_VALUE[4] == "0" ? (iextendC_THRESH1_VALUE[5] == "0" ? + (iextendC_THRESH1_VALUE[6] == "0" ? (iextendC_THRESH1_VALUE[7] == "0" ? + (iextendC_THRESH1_VALUE[8] == "0" ? (iextendC_THRESH1_VALUE[9] == "0" ? + (iextendC_THRESH1_VALUE[10] == "0" ? (iextendC_THRESH1_VALUE[11] == "0" ? + (iextendC_THRESH1_VALUE[12] == "0" ? (iextendC_THRESH1_VALUE[13] == "0" ? + (iextendC_THRESH1_VALUE[14] == "0" ? (iextendC_THRESH1_VALUE[15] == "0" ? + (iextendC_THRESH1_VALUE[16] == "0" ? (iextendC_THRESH1_VALUE[17] == "0" ? + (iextendC_THRESH1_VALUE[18] == "0" ? (iextendC_THRESH1_VALUE[19] == "0" ? + (iextendC_THRESH1_VALUE[20] == "0" ? (iextendC_THRESH1_VALUE[21] == "0" ? + (iextendC_THRESH1_VALUE[22] == "0" ? (iextendC_THRESH1_VALUE[23] == "0" ? + (iextendC_THRESH1_VALUE[24] == "0" ? (iextendC_THRESH1_VALUE[25] == "0" ? + (iextendC_THRESH1_VALUE[26] == "0" ? (iextendC_THRESH1_VALUE[27] == "0" ? + (iextendC_THRESH1_VALUE[28] == "0" ? (iextendC_THRESH1_VALUE[29] == "0" ? + (iextendC_THRESH1_VALUE[30] == "0" ? (iextendC_THRESH1_VALUE[31] == "0" ? + (iextendC_THRESH1_VALUE[32] == "0" ? (iextendC_THRESH1_VALUE[33] == "0" ? + (iextendC_THRESH1_VALUE[34] == "0" ? (iextendC_THRESH1_VALUE[35] == "0" ? + (iextendC_THRESH1_VALUE[36] == "0" ? (iextendC_THRESH1_VALUE[37] == "0" ? + (iextendC_THRESH1_VALUE[38] == "0" ? (iextendC_THRESH1_VALUE[39] == "0" ? + (iextendC_THRESH1_VALUE[40] == "0" ? (iextendC_THRESH1_VALUE[41] == "0" ? + (iextendC_THRESH1_VALUE[42] == "0" ? (iextendC_THRESH1_VALUE[43] == "0" ? + (iextendC_THRESH1_VALUE[44] == "0" ? (iextendC_THRESH1_VALUE[45] == "0" ? + (iextendC_THRESH1_VALUE[46] == "0" ? (iextendC_THRESH1_VALUE[47] == "0" ? + (iextendC_THRESH1_VALUE[48] == "0" ? (iextendC_THRESH1_VALUE[49] == "0" ? + (iextendC_THRESH1_VALUE[50] == "0" ? (iextendC_THRESH1_VALUE[51] == "0" ? + (iextendC_THRESH1_VALUE[52] == "0" ? (iextendC_THRESH1_VALUE[53] == "0" ? + (iextendC_THRESH1_VALUE[54] == "0" ? (iextendC_THRESH1_VALUE[55] == "0" ? + (iextendC_THRESH1_VALUE[56] == "0" ? (iextendC_THRESH1_VALUE[57] == "0" ? + (iextendC_THRESH1_VALUE[58] == "0" ? (iextendC_THRESH1_VALUE[59] == "0" ? + (iextendC_THRESH1_VALUE[60] == "0" ? (iextendC_THRESH1_VALUE[61] == "0" ? + (iextendC_THRESH1_VALUE[62] == "0" ? (iextendC_THRESH1_VALUE[63] == "0" ? 0 + : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) + : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) + : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) + : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) + : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) + : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) + : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) + : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) + : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) + : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) + : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) + : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) + : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) + : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) + : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) + : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) + : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) + : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) + : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) + : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) + : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) + : (C_HAS_SCLR == 1 ? 1 : 0)); + + + + + + input CLK; + input UP; + input CE; + input LOAD; + input [C_WIDTH-1 : 0] L; + input [C_WIDTH-1 : 0] IV; + input ACLR; + input ASET; + input AINIT; + input SCLR; + input SSET; + input SINIT; + output THRESH0; + output Q_THRESH0; + output THRESH1; + output Q_THRESH1; + output [C_WIDTH-1 : 0] Q; + + // Internal values to drive signals when input is missing + wire intUP; + wire intUPbar = ~intUP; + wire intCE; + wire intLOAD; + wire [C_WIDTH-1 : 0] intL; + wire [C_WIDTH-1 : 0] intB; + wire [C_WIDTH-1 : 0] all_zeros = {C_WIDTH{1'b0}}; + wire intSCLR; + wire intCount_to_reached; + reg intTHRESH0; + reg intTHRESH1; + wire intQ_THRESH0; + wire intQ_THRESH1; + wire [C_WIDTH-1 : 0] intFBq; + wire [C_WIDTH-1 : 0] intFBs; + wire [C_WIDTH-1 : 0] intQ = intFBq; + wire [C_WIDTH-1 : 0] intFBq_or_zero; + wire [C_WIDTH-1 : 0] intFBs_or_q; + wire [C_WIDTH-1 : 0] intCount_by = to_bits(C_COUNT_BY); + wire [C_WIDTH-1 : 0] intB_or_load; + wire [C_WIDTH-1 : 0] tmpintB_or_load; + + wire Q_THRESH0 = (C_HAS_Q_THRESH0 == 1 ? intQ_THRESH0 : 1'bx); + wire Q_THRESH1 = (C_HAS_Q_THRESH1 == 1 ? intQ_THRESH1 : 1'bx); + wire [C_WIDTH-1 : 0] Q = intQ; + + wire [C_WIDTH-1 : 0] intXLOADMUX; + wire [C_WIDTH-1 : 0] intSINITVAL = to_bits(C_SINIT_VAL); + wire [C_WIDTH-1 : 0] intXL; + wire intXLOAD; + wire intXXLOAD; + wire #5 intSCLR_RESET = (intSCLR || (intCount_to_reached && intCE && C_RESTRICT_COUNT == 1)) && ~intXXLOAD; + wire #5 intSCLR_RESET_for_thresh = intSCLR; //((intSCLR && intCE) || (intCount_to_reached && intCE && C_RESTRICT_COUNT == 1)) && ~intXXLOAD; + + wire intSCLR_for_th_to; + wire ACLR_for_th_to; + wire ASET_for_th_to; + + // Sort out default values for missing ports + + assign intUP = (C_HAS_UP == 1 ? UP : (C_COUNT_MODE == `c_up ? 1'b1 : 1'b0)); + assign intCE = defval(CE, C_HAS_CE, 1); + assign intL = (C_HAS_L == 1 ? L : {C_WIDTH{1'b0}}); + assign intB = (C_HAS_IV == 1 ? IV : intCount_by); + assign intXL = (C_RESTRICT_COUNT == 1 ? (C_HAS_SINIT == 1 ? (C_HAS_LOAD == 1 ? intXLOADMUX : intSINITVAL) : intL) : intL); + assign intLOAD = (C_LOAD_LOW == 1 ? ~LOAD : LOAD ); + assign intXLOAD = (C_RESTRICT_COUNT == 1 ? (C_HAS_SINIT == 1 ? (C_HAS_LOAD == 1 ? (C_HAS_CE == 1 ? (C_SYNC_ENABLE != C_LOAD_ENABLE ? (C_SYNC_ENABLE == 0 ? (C_LOAD_LOW == 1 ? (((~SINIT) && (~CE)) || ((~SINIT) && LOAD && CE)) : (SINIT || (LOAD && CE))) : (C_LOAD_LOW == 1 ? ((LOAD && (~CE)) || ((~SINIT) && LOAD && CE)) : (LOAD || (SINIT && CE)))) : (C_LOAD_LOW == 1 ? LOAD && ~SINIT : LOAD || SINIT)) : (C_LOAD_LOW == 1 ? LOAD && ~SINIT : LOAD || SINIT)) : (C_LOAD_LOW ? ~SINIT : SINIT)) : (C_HAS_LOAD == 1 ? LOAD : 1'b0)) : (C_HAS_LOAD == 1 ? LOAD : 1'b0)); + assign intXXLOAD = (C_RESTRICT_COUNT == 1 ? (C_HAS_SINIT == 1 ? (C_HAS_LOAD == 1 ? (C_LOAD_LOW == 1 ? ~intXLOAD : intXLOAD) : (C_LOAD_LOW == 1 ? ~intXLOAD : intXLOAD)) : (C_HAS_LOAD == 1 ? intLOAD : 1'b0)) : (C_HAS_LOAD == 1 ? intLOAD : 1'b0)); + assign intSCLR = defval(SCLR, C_HAS_SCLR, 0); + assign intB_or_load = (C_HAS_LOAD == 1 ? tmpintB_or_load : (C_RESTRICT_COUNT == 1 ? (C_HAS_SINIT == 1 ? tmpintB_or_load : intB) : intB)); + assign intFBs_or_q = (C_THRESH_EARLY == 1 ? intFBs : intFBq); + + assign intSCLR_for_th_to = ((C_HAS_SCLR == 1 && C_HAS_SSET == 1) ? (SCLR | SSET) : + (C_HAS_SCLR == 1 && C_HAS_SSET == 0) ? SCLR : + (C_HAS_SCLR == 0 && C_HAS_SSET == 1) ? SSET : + 0); + assign ACLR_for_th_to = ((C_HAS_ACLR == 1 && (C_HAS_AINIT == 1 && C_COUNT_TO != C_AINIT_VAL)) + ? (ACLR | AINIT) + : ((C_HAS_AINIT == 1 && C_COUNT_TO != C_AINIT_VAL) + ? AINIT + : (C_HAS_ACLR == 1 ? ACLR : 0))); + assign ASET_for_th_to = ((C_HAS_AINIT == 1 && C_COUNT_TO == C_AINIT_VAL) + ? AINIT + : 0); + + + // The addsub on which this is based... + + C_ADDSUB_V6_0 #(C_COUNT_MODE, + C_AINIT_VAL, + C_OUT_TYPE, + C_WIDTH, + (((~(C_HAS_LOAD===1)) || C_LOAD_ENABLE) && (C_SYNC_ENABLE || ~(C_RESTRICT_COUNT && C_HAS_SINIT))), + C_LOAD_LOW, // DLUNN CHANGED FROM 0, + 0, + C_OUT_TYPE, + "0000000000000000", + C_WIDTH, + C_ENABLE_RLOCS, + C_HAS_ACLR, + C_HAS_UP, + C_HAS_AINIT, + C_HAS_ASET, + 0, + C_HAS_LOAD || (C_RESTRICT_COUNT == 1 && C_HAS_SINIT == 1), // DLUNN CHANGED FROM 1, + 0, + 0, + 0, + 0, + C_HAS_CE, + 1, + 0, + 0, + 1, + 0, + 0, + 0, + 1, + adder_HAS_SCLR, + C_HAS_SINIT && ~(C_RESTRICT_COUNT === 1), + C_HAS_SSET, + C_WIDTH-1, + 1, + 0, + C_WIDTH, + C_PIPE_STAGES, + C_SINIT_VAL, + C_SYNC_ENABLE, + C_SYNC_PRIORITY) + the_addsub (.A(intFBq_or_zero), .B(intB_or_load), .CLK(CLK), .ADD(intUP), + .C_IN(intUPbar), .B_IN(), .CE(CE), .BYPASS(intXLOAD), + .ACLR(ACLR), .ASET(ASET), .AINIT(AINIT), + .SCLR(intSCLR_RESET), .SSET(SSET), .SINIT(SINIT), + .A_SIGNED(), .B_SIGNED(), .OVFL(), .C_OUT(), .B_OUT(), + .Q_OVFL(), .Q_C_OUT(), .Q_B_OUT(), + .S(intFBs), .Q(intFBq)); + + // The Restrict Count/Sinit LOAD mux + + C_MUX_BUS_V6_0 #("", C_ENABLE_RLOCS, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 2, + 0, 0, 1, "", 0, 0, C_WIDTH) + mxRCSL(.MA(intSINITVAL), .MB(intL), .MC(), .MD(), .ME(), .MF(), .MG(), .MH(), + .MAA(), .MAB(), .MAC(), .MAD(), .MAE(), .MAF(), .MAG(), .MAH(), + .MBA(), .MBB(), .MBC(), .MBD(), .MBE(), .MBF(), .MBG(), .MBH(), + .MCA(), .MCB(), .MCC(), .MCD(), .MCE(), .MCF(), .MCG(), .MCH(), + .S(intLOAD), .CLK(), .CE(), .EN(), .ACLR(), .ASET(), .AINIT(), + .SCLR(), .SSET(), .SINIT(), + .O(intXLOADMUX), .Q()); + + // The feedback mux + + C_MUX_BUS_V6_0 #("", C_ENABLE_RLOCS, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 2, + 0, 0, 1, "", 0, 0, C_WIDTH) + mxfb(.MA(intFBq), .MB(all_zeros), .MC(), .MD(), .ME(), .MF(), .MG(), .MH(), + .MAA(), .MAB(), .MAC(), .MAD(), .MAE(), .MAF(), .MAG(), .MAH(), + .MBA(), .MBB(), .MBC(), .MBD(), .MBE(), .MBF(), .MBG(), .MBH(), + .MCA(), .MCB(), .MCC(), .MCD(), .MCE(), .MCF(), .MCG(), .MCH(), + .S(intXXLOAD), .CLK(), .CE(), .EN(), .ACLR(), .ASET(), .AINIT(), + .SCLR(), .SSET(), .SINIT(), + .O(intFBq_or_zero), .Q()); + + // The LOAD mux + + C_MUX_BUS_V6_0 #("", C_ENABLE_RLOCS, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 2, + 0, 0, 1, "", 0, 0, C_WIDTH) + mx1(.MA(intB), .MB(intXL), .MC(), .MD(), .ME(), .MF(), .MG(), .MH(), + .MAA(), .MAB(), .MAC(), .MAD(), .MAE(), .MAF(), .MAG(), .MAH(), + .MBA(), .MBB(), .MBC(), .MBD(), .MBE(), .MBF(), .MBG(), .MBH(), + .MCA(), .MCB(), .MCC(), .MCD(), .MCE(), .MCF(), .MCG(), .MCH(), + .S(intXXLOAD), .CLK(), .CE(), .EN(), .ACLR(), .ASET(), .AINIT(), + .SCLR(), .SSET(), .SINIT(), + .O(tmpintB_or_load), .Q()); + + // The Threshhold comparators + + C_COMPARE_V6_0 #("0", 1, C_THRESH0_VALUE, C_OUT_TYPE, C_ENABLE_RLOCS, C_HAS_ACLR, 0, + C_HAS_THRESH0, 0, 0, 0, 0, 0, C_HAS_CE, C_HAS_Q_THRESH0, + 0, 0, 0, 0, 0, intC_HAS_SCLR0, 0, 0, 1, 0, C_WIDTH) + th0(.A(intFBs_or_q), .B(), .CLK(CLK), .CE(CE), + .ACLR(ACLR), .ASET(), + .SCLR(intSCLR_RESET_for_thresh), .SSET(), + .A_EQ_B(THRESH0), .A_NE_B(), .A_LT_B(), .A_GT_B(), .A_LE_B(), .A_GE_B(), + .QA_EQ_B(Q_THRESH0), .QA_NE_B(), .QA_LT_B(), .QA_GT_B(), .QA_LE_B(), .QA_GE_B()); + + C_COMPARE_V6_0 #("0", 1, C_THRESH1_VALUE, C_OUT_TYPE, C_ENABLE_RLOCS, C_HAS_ACLR, 0, + C_HAS_THRESH1, 0, 0, 0, 0, 0, C_HAS_CE, C_HAS_Q_THRESH1, + 0, 0, 0, 0, 0, intC_HAS_SCLR1, 0, 0, 1, 0, C_WIDTH) + th1(.A(intFBs_or_q), .B(), .CLK(CLK), .CE(CE), + .ACLR(ACLR), .ASET(), + .SCLR(intSCLR_RESET_for_thresh), .SSET(), + .A_EQ_B(THRESH1), .A_NE_B(), .A_LT_B(), .A_GT_B(), .A_LE_B(), .A_GE_B(), + .QA_EQ_B(Q_THRESH1), .QA_NE_B(), .QA_LT_B(), .QA_GT_B(), .QA_LE_B(), .QA_GE_B()); + + C_COMPARE_V6_0 #("0", 1, C_COUNT_TO, C_OUT_TYPE, C_ENABLE_RLOCS, TH_TO_HAS_ACLR, TH_TO_HAS_ASET, + 0, 0, 0, 0, 0, 0, C_HAS_CE, 1, + 0, 0, 0, 0, 0, TH_TO_HAS_SCLR, 0, 0, C_SYNC_ENABLE, 0, C_WIDTH) + th_to(.A(intFBs), .B(), .CLK(CLK), .CE(CE), + .ACLR(ACLR_for_th_to), .ASET(ASET_for_th_to), + .SCLR(intSCLR_for_th_to), .SSET(), + .A_EQ_B(), .A_NE_B(), .A_LT_B(), .A_GT_B(), .A_LE_B(), .A_GE_B(), + .QA_EQ_B(intCount_to_reached), .QA_NE_B(), .QA_LT_B(), .QA_GT_B(), .QA_LE_B(), .QA_GE_B()); + + initial + begin + + #1; + + + end + + function defval; + input i; + input hassig; + input val; + begin + if(hassig == 1) + defval = i; + else + defval = val; + end + endfunction + + function [C_WIDTH - 1 : 0] to_bits; + input [C_WIDTH*8 : 1] instring; + integer i; + begin + for(i = C_WIDTH; i > 0; i = i - 1) + begin // Is this character a '0'? (ASCII = 48 = 00110000) + if(instring[(i*8)] == 0 && + instring[(i*8)-1] == 0 && + instring[(i*8)-2] == 1 && + instring[(i*8)-3] == 1 && + instring[(i*8)-4] == 0 && + instring[(i*8)-5] == 0 && + instring[(i*8)-6] == 0 && + instring[(i*8)-7] == 0) + to_bits[i-1] = 0; + // Or is it a '1'? + else if(instring[(i*8)] == 0 && + instring[(i*8)-1] == 0 && + instring[(i*8)-2] == 1 && + instring[(i*8)-3] == 1 && + instring[(i*8)-4] == 0 && + instring[(i*8)-5] == 0 && + instring[(i*8)-6] == 0 && + instring[(i*8)-7] == 1) + + to_bits[i-1] = 1; + // Or is it a ' '? (a null char - in which case insert a '0') + else if(instring[(i*8)] == 0 && + instring[(i*8)-1] == 0 && + instring[(i*8)-2] == 0 && + instring[(i*8)-3] == 0 && + instring[(i*8)-4] == 0 && + instring[(i*8)-5] == 0 && + instring[(i*8)-6] == 0 && + instring[(i*8)-7] == 0) + to_bits[i-1] = 0; + else + begin + $display("Error in %m at time %d ns : non-binary digit in string \"%s\"\nExiting simulation...", $time, instring); + $finish; + end + end + end + endfunction + + + +endmodule + +`undef c_set +`undef c_clear +`undef c_override +`undef c_no_override +`undef c_signed +`undef c_unsigned +`undef c_pin +`undef c_up +`undef c_down +`undef c_updown +`undef allXs diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/C_COUNTER_BINARY_V7_0.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/C_COUNTER_BINARY_V7_0.v new file mode 100644 index 0000000..35d50aa --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/C_COUNTER_BINARY_V7_0.v @@ -0,0 +1,501 @@ +// Copyright(C) 2003 by Xilinx, Inc. All rights reserved. +// This text/file contains proprietary, confidential +// information of Xilinx, Inc., is distributed under license +// from Xilinx, Inc., and may be used, copied and/or +// disclosed only pursuant to the terms of a valid license +// agreement with Xilinx, Inc. Xilinx hereby grants you +// a license to use this text/file solely for design, simulation, +// implementation and creation of design files limited +// to Xilinx devices or technologies. Use with non-Xilinx +// devices or technologies is expressly prohibited and +// immediately terminates your license unless covered by +// a separate agreement. +// +// Xilinx is providing this design, code, or information +// "as is" solely for use in developing programs and +// solutions for Xilinx devices. By providing this design, +// code, or information as one possible implementation of +// this feature, application or standard, Xilinx is making no +// representation that this implementation is free from any +// claims of infringement. You are responsible for +// obtaining any rights you may require for your implementation. +// Xilinx expressly disclaims any warranty whatsoever with +// respect to the adequacy of the implementation, including +// but not limited to any warranties or representations that this +// implementation is free from claims of infringement, implied +// warranties of merchantability or fitness for a particular +// purpose. +// +// Xilinx products are not intended for use in life support +// appliances, devices, or systems. Use in such applications are +// expressly prohibited. +// +// This copyright and support notice must be retained as part +// of this text at all times. (c) Copyright 1995-2003 Xilinx, Inc. +// All rights reserved. + + + +/* $Id: C_COUNTER_BINARY_V7_0.v,v 1.13 2008/09/08 20:06:13 akennedy Exp $ +-- +-- Filename - C_COUNTER_BINARY_V7_0.v +-- Author - Xilinx +-- Creation -14 July 1999 +-- +-- Description - This file contains the Verilog behavior for the Baseblocks C_COUNTER_BINARY_V7_0 module +*/ + +`timescale 1ns/10ps + +`define c_set 0 +`define c_clear 1 +`define c_override 0 +`define c_no_override 1 +`define c_signed 0 +`define c_unsigned 1 +`define c_pin 2 +`define c_up 0 +`define c_down 1 +`define c_updown 2 +`define allXs {C_WIDTH{1'bx}} + +module C_COUNTER_BINARY_V7_0 (CLK, UP, CE, LOAD, L, IV, ACLR, ASET, AINIT, SCLR, SSET, SINIT, THRESH0, Q_THRESH0, THRESH1, Q_THRESH1, Q); + + parameter C_AINIT_VAL = "0"; + parameter C_COUNT_BY = ""; + parameter C_COUNT_MODE = `c_up; + parameter C_COUNT_TO = "1111111111111111"; + parameter C_ENABLE_RLOCS = 1; + parameter C_HAS_ACLR = 0; + parameter C_HAS_AINIT = 0; + parameter C_HAS_ASET = 0; + parameter C_HAS_CE = 0; + parameter C_HAS_IV = 0; + parameter C_HAS_L = 0; + parameter C_HAS_LOAD = 0; + parameter C_HAS_Q_THRESH0 = 0; + parameter C_HAS_Q_THRESH1 = 0; + parameter C_HAS_SCLR = 0; + parameter C_HAS_SINIT = 0; + parameter C_HAS_SSET = 0; + parameter C_HAS_THRESH0 = 0; + parameter C_HAS_THRESH1 = 0; + parameter C_HAS_UP = 0; + parameter C_LOAD_ENABLE = `c_no_override; + parameter C_LOAD_LOW = 0; + parameter C_PIPE_STAGES = 0; + parameter C_RESTRICT_COUNT = 0; + parameter C_SINIT_VAL = "0"; + parameter C_SYNC_ENABLE = `c_override; + parameter C_SYNC_PRIORITY = `c_clear; + parameter C_THRESH0_VALUE = "1111111111111111"; + parameter C_THRESH1_VALUE = "1111111111111111"; + parameter C_THRESH_EARLY = 1; + parameter C_WIDTH = 16; + + + + parameter adder_HAS_SCLR = ((C_RESTRICT_COUNT == 1) || (C_HAS_SCLR == 1) ? 1 : 0); + + parameter iaxero = {62{"0"}}; + parameter iextendC_THRESH0_VALUE = {iaxero,C_THRESH0_VALUE}; + parameter iextendC_THRESH1_VALUE = {iaxero,C_THRESH1_VALUE}; + parameter iazero = {64{"0"}}; + parameter TH_TO_HAS_SCLR = ((C_HAS_SCLR == 1 || C_HAS_SSET == 1) ? 1 : 0); + parameter TH_TO_HAS_ASET = ((C_HAS_AINIT && (C_AINIT_VAL == C_COUNT_TO)) ? 1 : 0); + parameter TH_TO_HAS_ACLR = ((C_HAS_ACLR || (C_HAS_AINIT && (C_AINIT_VAL != C_COUNT_TO))) ? 1 : 0); + parameter intC_HAS_SCLR0 = (iextendC_THRESH0_VALUE[0] == 0 ? (iextendC_THRESH0_VALUE[1] == 0 ? + (iextendC_THRESH0_VALUE[2] == 0 ? (iextendC_THRESH0_VALUE[3] == 0 ? + (iextendC_THRESH0_VALUE[4] == 0 ? (iextendC_THRESH0_VALUE[5] == 0 ? + (iextendC_THRESH0_VALUE[6] == 0 ? (iextendC_THRESH0_VALUE[7] == 0 ? + (iextendC_THRESH0_VALUE[8] == 0 ? (iextendC_THRESH0_VALUE[9] == 0 ? + (iextendC_THRESH0_VALUE[10] == 0 ? (iextendC_THRESH0_VALUE[11] == 0 ? + (iextendC_THRESH0_VALUE[12] == 0 ? (iextendC_THRESH0_VALUE[13] == 0 ? + (iextendC_THRESH0_VALUE[14] == 0 ? (iextendC_THRESH0_VALUE[15] == 0 ? + (iextendC_THRESH0_VALUE[16] == 0 ? (iextendC_THRESH0_VALUE[17] == 0 ? + (iextendC_THRESH0_VALUE[18] == 0 ? (iextendC_THRESH0_VALUE[19] == 0 ? + (iextendC_THRESH0_VALUE[20] == 0 ? (iextendC_THRESH0_VALUE[21] == 0 ? + (iextendC_THRESH0_VALUE[22] == 0 ? (iextendC_THRESH0_VALUE[23] == 0 ? + (iextendC_THRESH0_VALUE[24] == 0 ? (iextendC_THRESH0_VALUE[25] == 0 ? + (iextendC_THRESH0_VALUE[26] == 0 ? (iextendC_THRESH0_VALUE[27] == 0 ? + (iextendC_THRESH0_VALUE[28] == 0 ? (iextendC_THRESH0_VALUE[29] == 0 ? + (iextendC_THRESH0_VALUE[30] == 0 ? (iextendC_THRESH0_VALUE[31] == 0 ? + (iextendC_THRESH0_VALUE[32] == 0 ? (iextendC_THRESH0_VALUE[33] == 0 ? + (iextendC_THRESH0_VALUE[34] == 0 ? (iextendC_THRESH0_VALUE[35] == 0 ? + (iextendC_THRESH0_VALUE[36] == 0 ? (iextendC_THRESH0_VALUE[37] == 0 ? + (iextendC_THRESH0_VALUE[38] == 0 ? (iextendC_THRESH0_VALUE[39] == 0 ? + (iextendC_THRESH0_VALUE[40] == 0 ? (iextendC_THRESH0_VALUE[41] == 0 ? + (iextendC_THRESH0_VALUE[42] == 0 ? (iextendC_THRESH0_VALUE[43] == 0 ? + (iextendC_THRESH0_VALUE[44] == 0 ? (iextendC_THRESH0_VALUE[45] == 0 ? + (iextendC_THRESH0_VALUE[46] == 0 ? (iextendC_THRESH0_VALUE[47] == 0 ? + (iextendC_THRESH0_VALUE[48] == 0 ? (iextendC_THRESH0_VALUE[49] == 0 ? + (iextendC_THRESH0_VALUE[50] == 0 ? (iextendC_THRESH0_VALUE[51] == 0 ? + (iextendC_THRESH0_VALUE[52] == 0 ? (iextendC_THRESH0_VALUE[53] == 0 ? + (iextendC_THRESH0_VALUE[54] == 0 ? (iextendC_THRESH0_VALUE[55] == 0 ? + (iextendC_THRESH0_VALUE[56] == 0 ? (iextendC_THRESH0_VALUE[57] == 0 ? + (iextendC_THRESH0_VALUE[58] == 0 ? (iextendC_THRESH0_VALUE[59] == 0 ? + (iextendC_THRESH0_VALUE[60] == 0 ? (iextendC_THRESH0_VALUE[61] == 0 ? + (iextendC_THRESH0_VALUE[62] == 0 ? (iextendC_THRESH0_VALUE[63] == 0 ? 0 + : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) + : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) + : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) + : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) + : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) + : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) + : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) + : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) + : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) + : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) + : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) + : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) + : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) + : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) + : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) + : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) + : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) + : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) + : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) + : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) + : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) + : (C_HAS_SCLR == 1 ? 1 : 0)); + parameter intC_HAS_SCLR1 = (iextendC_THRESH1_VALUE[0] == 0 ? (iextendC_THRESH1_VALUE[1] == 0 ? + (iextendC_THRESH1_VALUE[2] == 0 ? (iextendC_THRESH1_VALUE[3] == 0 ? + (iextendC_THRESH1_VALUE[4] == 0 ? (iextendC_THRESH1_VALUE[5] == 0 ? + (iextendC_THRESH1_VALUE[6] == 0 ? (iextendC_THRESH1_VALUE[7] == 0 ? + (iextendC_THRESH1_VALUE[8] == 0 ? (iextendC_THRESH1_VALUE[9] == 0 ? + (iextendC_THRESH1_VALUE[10] == 0 ? (iextendC_THRESH1_VALUE[11] == 0 ? + (iextendC_THRESH1_VALUE[12] == 0 ? (iextendC_THRESH1_VALUE[13] == 0 ? + (iextendC_THRESH1_VALUE[14] == 0 ? (iextendC_THRESH1_VALUE[15] == 0 ? + (iextendC_THRESH1_VALUE[16] == 0 ? (iextendC_THRESH1_VALUE[17] == 0 ? + (iextendC_THRESH1_VALUE[18] == 0 ? (iextendC_THRESH1_VALUE[19] == 0 ? + (iextendC_THRESH1_VALUE[20] == 0 ? (iextendC_THRESH1_VALUE[21] == 0 ? + (iextendC_THRESH1_VALUE[22] == 0 ? (iextendC_THRESH1_VALUE[23] == 0 ? + (iextendC_THRESH1_VALUE[24] == 0 ? (iextendC_THRESH1_VALUE[25] == 0 ? + (iextendC_THRESH1_VALUE[26] == 0 ? (iextendC_THRESH1_VALUE[27] == 0 ? + (iextendC_THRESH1_VALUE[28] == 0 ? (iextendC_THRESH1_VALUE[29] == 0 ? + (iextendC_THRESH1_VALUE[30] == 0 ? (iextendC_THRESH1_VALUE[31] == 0 ? + (iextendC_THRESH1_VALUE[32] == 0 ? (iextendC_THRESH1_VALUE[33] == 0 ? + (iextendC_THRESH1_VALUE[34] == 0 ? (iextendC_THRESH1_VALUE[35] == 0 ? + (iextendC_THRESH1_VALUE[36] == 0 ? (iextendC_THRESH1_VALUE[37] == 0 ? + (iextendC_THRESH1_VALUE[38] == 0 ? (iextendC_THRESH1_VALUE[39] == 0 ? + (iextendC_THRESH1_VALUE[40] == 0 ? (iextendC_THRESH1_VALUE[41] == 0 ? + (iextendC_THRESH1_VALUE[42] == 0 ? (iextendC_THRESH1_VALUE[43] == 0 ? + (iextendC_THRESH1_VALUE[44] == 0 ? (iextendC_THRESH1_VALUE[45] == 0 ? + (iextendC_THRESH1_VALUE[46] == 0 ? (iextendC_THRESH1_VALUE[47] == 0 ? + (iextendC_THRESH1_VALUE[48] == 0 ? (iextendC_THRESH1_VALUE[49] == 0 ? + (iextendC_THRESH1_VALUE[50] == 0 ? (iextendC_THRESH1_VALUE[51] == 0 ? + (iextendC_THRESH1_VALUE[52] == 0 ? (iextendC_THRESH1_VALUE[53] == 0 ? + (iextendC_THRESH1_VALUE[54] == 0 ? (iextendC_THRESH1_VALUE[55] == 0 ? + (iextendC_THRESH1_VALUE[56] == 0 ? (iextendC_THRESH1_VALUE[57] == 0 ? + (iextendC_THRESH1_VALUE[58] == 0 ? (iextendC_THRESH1_VALUE[59] == 0 ? + (iextendC_THRESH1_VALUE[60] == 0 ? (iextendC_THRESH1_VALUE[61] == 0 ? + (iextendC_THRESH1_VALUE[62] == 0 ? (iextendC_THRESH1_VALUE[63] == 0 ? 0 + : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) + : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) + : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) + : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) + : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) + : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) + : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) + : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) + : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) + : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) + : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) + : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) + : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) + : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) + : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) + : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) + : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) + : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) + : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) + : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) + : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) : (C_HAS_SCLR == 1 ? 1 : 0)) + : (C_HAS_SCLR == 1 ? 1 : 0)); + parameter C_OUT_TYPE = `c_signed; + + + + + + input CLK; + input UP; + input CE; + input LOAD; + input [C_WIDTH-1 : 0] L; + input [C_WIDTH-1 : 0] IV; + input ACLR; + input ASET; + input AINIT; + input SCLR; + input SSET; + input SINIT; + output THRESH0; + output Q_THRESH0; + output THRESH1; + output Q_THRESH1; + output [C_WIDTH-1 : 0] Q; + + // Internal values to drive signals when input is missing + wire intUP; + wire intUPbar = ~intUP; + wire intCE; + wire intLOAD; + wire [C_WIDTH-1 : 0] intL; + wire [C_WIDTH-1 : 0] intB; + wire [C_WIDTH-1 : 0] all_zeros = {C_WIDTH{1'b0}}; + wire intSCLR; + wire intCount_to_reached; + reg intTHRESH0; + reg intTHRESH1; + wire intQ_THRESH0; + wire intQ_THRESH1; + wire [C_WIDTH-1 : 0] intFBq; + wire [C_WIDTH-1 : 0] intFBs; + wire [C_WIDTH-1 : 0] intQ = intFBq; + wire [C_WIDTH-1 : 0] intFBq_or_zero; + wire [C_WIDTH-1 : 0] intFBs_or_q; + wire [C_WIDTH-1 : 0] intCount_by = to_bits(C_COUNT_BY); + wire [C_WIDTH-1 : 0] intB_or_load; + wire [C_WIDTH-1 : 0] tmpintB_or_load; + + wire Q_THRESH0 = (C_HAS_Q_THRESH0 == 1 ? intQ_THRESH0 : 1'bx); + wire Q_THRESH1 = (C_HAS_Q_THRESH1 == 1 ? intQ_THRESH1 : 1'bx); + wire [C_WIDTH-1 : 0] Q = intQ; + + wire [C_WIDTH-1 : 0] intXLOADMUX; + wire [C_WIDTH-1 : 0] intSINITVAL = to_bits(C_SINIT_VAL); + wire [C_WIDTH-1 : 0] intXL; + wire intXLOAD; + wire intXXLOAD; + wire #5 intSCLR_RESET = (intSCLR || (intCount_to_reached && intCE && C_RESTRICT_COUNT == 1)) && ~intXXLOAD; + wire #5 intSCLR_RESET_for_thresh = intSCLR; //((intSCLR && intCE) || (intCount_to_reached && intCE && C_RESTRICT_COUNT == 1)) && ~intXXLOAD; + + wire intSCLR_for_th_to; + wire ACLR_for_th_to; + wire ASET_for_th_to; + + // Sort out default values for missing ports + + assign intUP = (C_HAS_UP == 1 ? UP : (C_COUNT_MODE == `c_up ? 1'b1 : 1'b0)); + assign intCE = defval(CE, C_HAS_CE, 1); + assign intL = (C_HAS_L == 1 ? L : {C_WIDTH{1'b0}}); + assign intB = (C_HAS_IV == 1 ? IV : intCount_by); + assign intXL = (C_RESTRICT_COUNT == 1 ? (C_HAS_SINIT == 1 ? (C_HAS_LOAD == 1 ? intXLOADMUX : intSINITVAL) : intL) : intL); + assign intLOAD = (C_LOAD_LOW == 1 ? ~LOAD : LOAD ); + assign intXLOAD = (C_RESTRICT_COUNT == 1 ? (C_HAS_SINIT == 1 ? (C_HAS_LOAD == 1 ? (C_HAS_CE == 1 ? (C_SYNC_ENABLE != C_LOAD_ENABLE ? (C_SYNC_ENABLE == 0 ? (C_LOAD_LOW == 1 ? (((~SINIT) && (~CE)) || ((~SINIT) && LOAD && CE)) : (SINIT || (LOAD && CE))) : (C_LOAD_LOW == 1 ? ((LOAD && (~CE)) || ((~SINIT) && LOAD && CE)) : (LOAD || (SINIT && CE)))) : (C_LOAD_LOW == 1 ? LOAD && ~SINIT : LOAD || SINIT)) : (C_LOAD_LOW == 1 ? LOAD && ~SINIT : LOAD || SINIT)) : (C_LOAD_LOW ? ~SINIT : SINIT)) : (C_HAS_LOAD == 1 ? LOAD : 1'b0)) : (C_HAS_LOAD == 1 ? LOAD : 1'b0)); + assign intXXLOAD = (C_RESTRICT_COUNT == 1 ? (C_HAS_SINIT == 1 ? (C_HAS_LOAD == 1 ? (C_LOAD_LOW == 1 ? ~intXLOAD : intXLOAD) : (C_LOAD_LOW == 1 ? ~intXLOAD : intXLOAD)) : (C_HAS_LOAD == 1 ? intLOAD : 1'b0)) : (C_HAS_LOAD == 1 ? intLOAD : 1'b0)); + assign intSCLR = defval(SCLR, C_HAS_SCLR, 0); + assign intB_or_load = (C_HAS_LOAD == 1 ? tmpintB_or_load : (C_RESTRICT_COUNT == 1 ? (C_HAS_SINIT == 1 ? tmpintB_or_load : intB) : intB)); + assign intFBs_or_q = (C_THRESH_EARLY == 1 ? intFBs : intFBq); + + assign intSCLR_for_th_to = ((C_HAS_SCLR == 1 && C_HAS_SSET == 1) ? (SCLR | SSET) : + (C_HAS_SCLR == 1 && C_HAS_SSET == 0) ? SCLR : + (C_HAS_SCLR == 0 && C_HAS_SSET == 1) ? SSET : + 0); + assign ACLR_for_th_to = ((C_HAS_ACLR == 1 && (C_HAS_AINIT == 1 && C_COUNT_TO != C_AINIT_VAL)) + ? (ACLR | AINIT) + : ((C_HAS_AINIT == 1 && C_COUNT_TO != C_AINIT_VAL) + ? AINIT + : (C_HAS_ACLR == 1 ? ACLR : 0))); + assign ASET_for_th_to = ((C_HAS_AINIT == 1 && C_COUNT_TO == C_AINIT_VAL) + ? AINIT + : 0); + + + // The addsub on which this is based... + + C_ADDSUB_V7_0 #(C_COUNT_MODE, + C_AINIT_VAL, + C_OUT_TYPE, + C_WIDTH, + (((~(C_HAS_LOAD===1)) || C_LOAD_ENABLE) && (C_SYNC_ENABLE || ~(C_RESTRICT_COUNT && C_HAS_SINIT))), + C_LOAD_LOW, // DLUNN CHANGED FROM 0, + 0, + C_OUT_TYPE, + "0000000000000000", + C_WIDTH, + C_ENABLE_RLOCS, + C_HAS_ACLR, + C_HAS_UP, + C_HAS_AINIT, + C_HAS_ASET, + 0, + C_HAS_LOAD || (C_RESTRICT_COUNT == 1 && C_HAS_SINIT == 1), // DLUNN CHANGED FROM 1, + 0, + 0, + 0, + 0, + C_HAS_CE, + 1, + 0, + 0, + 1, + 0, + 0, + 0, + 1, + adder_HAS_SCLR, + C_HAS_SINIT && ~(C_RESTRICT_COUNT === 1), + C_HAS_SSET, + C_WIDTH-1, + 1, + 0, + C_WIDTH, + C_PIPE_STAGES, + C_SINIT_VAL, + C_SYNC_ENABLE, + C_SYNC_PRIORITY) + the_addsub (.A(intFBq_or_zero), .B(intB_or_load), .CLK(CLK), .ADD(intUP), + .C_IN(intUPbar), .B_IN(), .CE(CE), .BYPASS(intXLOAD), + .ACLR(ACLR), .ASET(ASET), .AINIT(AINIT), + .SCLR(intSCLR_RESET), .SSET(SSET), .SINIT(SINIT), + .A_SIGNED(), .B_SIGNED(), .OVFL(), .C_OUT(), .B_OUT(), + .Q_OVFL(), .Q_C_OUT(), .Q_B_OUT(), + .S(intFBs), .Q(intFBq)); + + // The Restrict Count/Sinit LOAD mux + + C_MUX_BUS_V7_0 #("", C_ENABLE_RLOCS, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 2, + 0, 0, 1, "", 0, 0, C_WIDTH) + mxRCSL(.MA(intSINITVAL), .MB(intL), .MC(), .MD(), .ME(), .MF(), .MG(), .MH(), + .MAA(), .MAB(), .MAC(), .MAD(), .MAE(), .MAF(), .MAG(), .MAH(), + .MBA(), .MBB(), .MBC(), .MBD(), .MBE(), .MBF(), .MBG(), .MBH(), + .MCA(), .MCB(), .MCC(), .MCD(), .MCE(), .MCF(), .MCG(), .MCH(), + .S(intLOAD), .CLK(), .CE(), .EN(), .ACLR(), .ASET(), .AINIT(), + .SCLR(), .SSET(), .SINIT(), + .O(intXLOADMUX), .Q()); + + // The feedback mux + + C_MUX_BUS_V7_0 #("", C_ENABLE_RLOCS, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 2, + 0, 0, 1, "", 0, 0, C_WIDTH) + mxfb(.MA(intFBq), .MB(all_zeros), .MC(), .MD(), .ME(), .MF(), .MG(), .MH(), + .MAA(), .MAB(), .MAC(), .MAD(), .MAE(), .MAF(), .MAG(), .MAH(), + .MBA(), .MBB(), .MBC(), .MBD(), .MBE(), .MBF(), .MBG(), .MBH(), + .MCA(), .MCB(), .MCC(), .MCD(), .MCE(), .MCF(), .MCG(), .MCH(), + .S(intXXLOAD), .CLK(), .CE(), .EN(), .ACLR(), .ASET(), .AINIT(), + .SCLR(), .SSET(), .SINIT(), + .O(intFBq_or_zero), .Q()); + + // The LOAD mux + + C_MUX_BUS_V7_0 #("", C_ENABLE_RLOCS, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 2, + 0, 0, 1, "", 0, 0, C_WIDTH) + mx1(.MA(intB), .MB(intXL), .MC(), .MD(), .ME(), .MF(), .MG(), .MH(), + .MAA(), .MAB(), .MAC(), .MAD(), .MAE(), .MAF(), .MAG(), .MAH(), + .MBA(), .MBB(), .MBC(), .MBD(), .MBE(), .MBF(), .MBG(), .MBH(), + .MCA(), .MCB(), .MCC(), .MCD(), .MCE(), .MCF(), .MCG(), .MCH(), + .S(intXXLOAD), .CLK(), .CE(), .EN(), .ACLR(), .ASET(), .AINIT(), + .SCLR(), .SSET(), .SINIT(), + .O(tmpintB_or_load), .Q()); + + // The Threshhold comparators + + C_COMPARE_V7_0 #("0", 1, C_THRESH0_VALUE, C_OUT_TYPE, C_ENABLE_RLOCS, C_HAS_ACLR, 0, + C_HAS_THRESH0, 0, 0, 0, 0, 0, C_HAS_CE, C_HAS_Q_THRESH0, + 0, 0, 0, 0, 0, intC_HAS_SCLR0, 0, 0, 1, 0, C_WIDTH) + th0(.A(intFBs_or_q), .B(), .CLK(CLK), .CE(CE), + .ACLR(ACLR), .ASET(), + .SCLR(intSCLR_RESET_for_thresh), .SSET(), + .A_EQ_B(THRESH0), .A_NE_B(), .A_LT_B(), .A_GT_B(), .A_LE_B(), .A_GE_B(), + .QA_EQ_B(Q_THRESH0), .QA_NE_B(), .QA_LT_B(), .QA_GT_B(), .QA_LE_B(), .QA_GE_B()); + + C_COMPARE_V7_0 #("0", 1, C_THRESH1_VALUE, C_OUT_TYPE, C_ENABLE_RLOCS, C_HAS_ACLR, 0, + C_HAS_THRESH1, 0, 0, 0, 0, 0, C_HAS_CE, C_HAS_Q_THRESH1, + 0, 0, 0, 0, 0, intC_HAS_SCLR1, 0, 0, 1, 0, C_WIDTH) + th1(.A(intFBs_or_q), .B(), .CLK(CLK), .CE(CE), + .ACLR(ACLR), .ASET(), + .SCLR(intSCLR_RESET_for_thresh), .SSET(), + .A_EQ_B(THRESH1), .A_NE_B(), .A_LT_B(), .A_GT_B(), .A_LE_B(), .A_GE_B(), + .QA_EQ_B(Q_THRESH1), .QA_NE_B(), .QA_LT_B(), .QA_GT_B(), .QA_LE_B(), .QA_GE_B()); + + C_COMPARE_V7_0 #("0", 1, C_COUNT_TO, C_OUT_TYPE, C_ENABLE_RLOCS, TH_TO_HAS_ACLR, TH_TO_HAS_ASET, + 0, 0, 0, 0, 0, 0, C_HAS_CE, 1, + 0, 0, 0, 0, 0, TH_TO_HAS_SCLR, 0, 0, C_SYNC_ENABLE, 0, C_WIDTH) + th_to(.A(intFBs), .B(), .CLK(CLK), .CE(CE), + .ACLR(ACLR_for_th_to), .ASET(ASET_for_th_to), + .SCLR(intSCLR_for_th_to), .SSET(), + .A_EQ_B(), .A_NE_B(), .A_LT_B(), .A_GT_B(), .A_LE_B(), .A_GE_B(), + .QA_EQ_B(intCount_to_reached), .QA_NE_B(), .QA_LT_B(), .QA_GT_B(), .QA_LE_B(), .QA_GE_B()); + + initial + begin + + #1; + + + end + + function defval; + input i; + input hassig; + input val; + begin + if(hassig == 1) + defval = i; + else + defval = val; + end + endfunction + + function [C_WIDTH - 1 : 0] to_bits; + input [C_WIDTH*8 : 1] instring; + integer i; + begin + for(i = C_WIDTH; i > 0; i = i - 1) + begin // Is this character a '0'? (ASCII = 48 = 00110000) + if(instring[(i*8)] == 0 && + instring[(i*8)-1] == 0 && + instring[(i*8)-2] == 1 && + instring[(i*8)-3] == 1 && + instring[(i*8)-4] == 0 && + instring[(i*8)-5] == 0 && + instring[(i*8)-6] == 0 && + instring[(i*8)-7] == 0) + to_bits[i-1] = 0; + // Or is it a '1'? + else if(instring[(i*8)] == 0 && + instring[(i*8)-1] == 0 && + instring[(i*8)-2] == 1 && + instring[(i*8)-3] == 1 && + instring[(i*8)-4] == 0 && + instring[(i*8)-5] == 0 && + instring[(i*8)-6] == 0 && + instring[(i*8)-7] == 1) + + to_bits[i-1] = 1; + // Or is it a ' '? (a null char - in which case insert a '0') + else if(instring[(i*8)] == 0 && + instring[(i*8)-1] == 0 && + instring[(i*8)-2] == 0 && + instring[(i*8)-3] == 0 && + instring[(i*8)-4] == 0 && + instring[(i*8)-5] == 0 && + instring[(i*8)-6] == 0 && + instring[(i*8)-7] == 0) + to_bits[i-1] = 0; + else + begin + $display("Error in %m at time %d ns : non-binary digit in string \"%s\"\nExiting simulation...", $time, instring); + $finish; + end + end + end + endfunction + + + +endmodule + +`undef c_set +`undef c_clear +`undef c_override +`undef c_no_override +`undef c_signed +`undef c_unsigned +`undef c_pin +`undef c_up +`undef c_down +`undef c_updown +`undef allXs diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/C_DA_FIR_V7_0.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/C_DA_FIR_V7_0.v new file mode 100644 index 0000000..7f5ee8c --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/C_DA_FIR_V7_0.v @@ -0,0 +1,1177 @@ +/* +-- $Revision: 1.15 $ $Date: 2008/09/08 20:07:41 $ +---------------------------------------------------------------------- +-- This file is owned and controlled by Xilinx and must be used -- +-- solely for design, simulation, implementation and creation of -- +-- design files limited to Xilinx devices or technologies. Use -- +-- with non-Xilinx devices or technologies is expressly prohibited -- +-- and immediately terminates your license. -- +-- -- +-- Xilinx products are not intended for use in life support -- +-- appliances, devices, or systems. Use in such applications are -- +-- expressly prohibited. -- +-- -- +-- Copyright (C) 2001, Xilinx, Inc. All Rights Reserved. -- +---------------------------------------------------------------------- +-- +-- Description: +-- DA FIR filter behavioral model +-- +*/ + +`timescale 1 ns/10 ps + +// !!! undef at the end if we add to this + +`define true 1'b1 +`define false 1'b0 +`define TRUE 1'b1 +`define FALSE 1'b0 + +`define c_signed 0 +`define c_unsigned 1 +`define c_nrz 2 + +`define c_symmetric 0 +`define c_non_symmetric 1 +`define c_neg_symmetric 2 + +`define c_single_rate_fir 0 +`define c_polyphase_interpolating 1 +`define c_polyphase_decimating 2 +`define c_hilbert_transform 3 +`define c_interpolated_fir 4 +`define c_half_band 5 +`define c_decimating_half_band 6 +`define c_interpolating_half_band 7 + +`define c_no_reload 0 +`define c_stop_during_reload 1 + + +//********************************************************** +// This line is used in the ActiveHDL testbench +// module Verilog_Model + +// This line is used in the SVG testbench +module C_DA_FIR_V7_0 +//********************************************************** + + ( + DIN, ND, + CLK, + RST, + COEF_LD, + LD_DIN, + LD_WE, + DOUT, + DOUT_I, DOUT_Q, + RDY, RFD, + SEL_I, SEL_O, + CAS_F_IN, CAS_R_IN, CAS_F_OUT, CAS_R_OUT + ); + + + // NOTE: These parameters MUST be in ALPHABETICAL order + //**** Parameters modified to match CONSTANT declarations in testbench file ***** + parameter C_BAAT = 16; + parameter C_CHANNELS = 1; + parameter C_COEFF_TYPE = `c_signed; + parameter C_COEFF_WIDTH = 16; + parameter C_DATA_TYPE = `c_signed; + parameter C_DATA_WIDTH = 16; + parameter C_ENABLE_RLOCS = 0; + parameter C_FILTER_TYPE = `c_single_rate_fir; + parameter C_HAS_RESET = 0; + parameter C_HAS_SEL_I = 0; + parameter C_HAS_SEL_O = 0; + parameter C_HAS_SIN_F = 0; + parameter C_HAS_SIN_R = 0; + parameter C_HAS_SOUT_F = 0; + parameter C_HAS_SOUT_R = 0; + parameter C_LATENCY = 9; + parameter C_MEM_INIT_FILE = "std_12_coef.mif"; + parameter C_OPTIMIZE = 0; + parameter C_POLYPHASE_FACTOR = 1; + parameter C_REG_OUTPUT = 1; + parameter C_RELOAD = `c_no_reload; + parameter C_RELOAD_DELAY = 0; + parameter C_RELOAD_MEM_TYPE = 0; // ignored + parameter C_RESPONSE = `c_non_symmetric; + parameter C_RESULT_WIDTH = 36; + parameter C_SATURATE = 0; // not supported + parameter C_SHAPE = 0; + parameter C_TAPS = 12; + parameter C_USE_MODEL_FUNC = 0; // if 1 then use latency function otherwise use C_LATENCY + parameter C_ZPF = 1; + + // bits need to represent channel + parameter channel_width = ((C_CHANNELS <=2) ? 1: + ((C_CHANNELS <=4) ? 2: + ((C_CHANNELS <=8) ? 3:4))); + + + // Interpolated filter: number of taps including zero packing factor + parameter zpf_taps = C_TAPS*C_ZPF; + + // input ports + input [C_DATA_WIDTH - 1 :0] DIN; + input ND; + input RST; + input [C_BAAT - 1:0] CAS_R_IN; + input [C_BAAT - 1:0] CAS_F_IN; + input CLK; + input COEF_LD; + input [C_COEFF_WIDTH - 1 : 0] LD_DIN; + input LD_WE; + + // output ports + output [C_RESULT_WIDTH - 1 :0] DOUT; + output [C_DATA_WIDTH - 1 :0] DOUT_I; + output [C_RESULT_WIDTH - 1 :0] DOUT_Q; + output RDY; + output RFD; + output [channel_width - 1 :0] SEL_I; + output [channel_width - 1 :0] SEL_O; + output [C_BAAT - 1:0] CAS_R_OUT; + output [C_BAAT - 1:0] CAS_F_OUT; + +// coefficients intialized from memory file +// or coefficient input +reg [C_COEFF_WIDTH - 1 : 0] c_data [0 : C_TAPS - 1]; +reg [C_COEFF_WIDTH - 1 : 0] tmp_c_data; +reg [C_COEFF_WIDTH - 1 : 0] c_int_data [0 : C_TAPS - 1]; // absolute value of coefficients +reg c_data_sign [0 : C_TAPS - 1]; // coefficient sign + +// temp variable for incoming data +reg [C_DATA_WIDTH - 1 : 0] tmp_x_data; +// integer array of filter data +reg [C_DATA_WIDTH - 1 : 0] x_int_data [0 : C_CHANNELS*C_TAPS - 1]; // absolute value of sample data +reg [C_DATA_WIDTH - 1 : 0] x_zpf_data [0 : C_CHANNELS*zpf_taps - 1]; // absolute value of interpolated filter data (with zeros inserted) +reg x_data_sign [0 : C_CHANNELS*C_TAPS - 1]; // sample data sign +reg x_zpf_data_sign [0 : C_CHANNELS*zpf_taps - 1]; // sample data sign for interpolated filters + +// maxm number of results PER CHANNEL that may need to be saved until they can be output on DOUT +parameter back_data_per_channel = (C_USE_MODEL_FUNC == 1) ? 50 : + (C_POLYPHASE_FACTOR < 1) ? 2 * (C_LATENCY+1) : + 2 * (C_LATENCY+1)*C_POLYPHASE_FACTOR; + +// maxm number of results that may need to be saved until they can be output on DOUT +parameter back_data = (C_USE_MODEL_FUNC == 1) ? 50 : + (C_POLYPHASE_FACTOR < 1) ? 2 * (C_LATENCY+1) : + 2 * (C_LATENCY+1)*C_POLYPHASE_FACTOR*C_CHANNELS; +reg [C_RESULT_WIDTH - 1 :0] tmpDOUT [0 : back_data - 1]; +// variable to hold the I component of the Hilbert output +reg [C_DATA_WIDTH - 1 : 0] x_hilbert[0 : back_data - 1]; +// number of cycles before each saved result can be output, and RDY asserted +integer count_rdy[0 : back_data - 1]; + +// output regs +reg [C_RESULT_WIDTH - 1 :0] DOUT; +reg [C_DATA_WIDTH - 1 :0] DOUT_I; +reg [C_RESULT_WIDTH - 1 :0] DOUT_Q; +reg RFD; +reg RDY; +reg prevRDY; + +reg [channel_width - 1 : 0]SEL_I; +reg [channel_width - 1 : 0]SEL_O; + +reg [C_BAAT - 1:0] CAS_F_OUT; +reg [C_BAAT - 1:0] CAS_R_OUT; +reg [C_DATA_WIDTH - 1:0] cascade_data_f; +reg [C_DATA_WIDTH - 1:0] cascade_data_r; +reg delay1ND; +reg delay2ND; + + +`define all1s {C_RESULT_WIDTH{1'b1}} +`define all0s {C_RESULT_WIDTH{1'b0}} +`define allXs {C_RESULT_WIDTH{1'bx}} +`define MAX_NUMBER_SAMPLES 9 // Maximum number of samples that can be stored in the last input FIFO + +// number of coefs that must be provided during reloading +parameter num_reload_coefs = (C_RESPONSE == `c_non_symmetric) ? (C_TAPS) : (C_TAPS+1)/2; +// cascade data defaults +parameter cascade_num_cycles = (C_DATA_WIDTH != C_BAAT && C_RESPONSE != `c_non_symmetric) ? + (C_DATA_WIDTH + 1 + C_BAAT - 1)/C_BAAT : + (C_DATA_WIDTH + C_BAAT - 1)/C_BAAT; +parameter extwidth = cascade_num_cycles * C_BAAT; + +reg [extwidth - 1:0] save_casc_f, save_casc_r; + +integer i,j; +integer c_taps_2; +integer sel_i,sel_o; +integer prev_sel_i; +integer load_counter; +integer count_rfd_non_decimating; // replicates functionality of 'count_rfd' in original model (SJZ 2/1B) +integer new_data[0 : C_CHANNELS - 1]; // made integer an array +integer count_rfd[0 : C_CHANNELS - 1]; // made integer an array +integer rdy_counter; // tracks clocks between when RDY can go active +integer data_output_rdy; // indicates that one channel has data available to be output +integer data_output_channel; // indicates the channel that has data available +integer next_data_output_channel; // tracks which channel will be next to have data available +integer subfilter_number; // tracks which subfilter the input data is being written to +integer subfilter_number_delayed; +integer subfilter_num_samples_buffer[0 : C_POLYPHASE_FACTOR - 1]; // number of samples stored in each subfilter's input buffer +integer compute_channel_select; // tracks which channel is performing a computation +integer read_buffer_to_rfd_counter; // counts clocks between RDY going active and RFD being asserted +integer delay_first_read_flag; // Holds up read of data out input buffers until one clock after last subfilters buffer has first data sample written into it +integer c_pipe_stages; +integer cascade_out_cycle_number, cascade_in_cycle_number; +integer do_compute_result; +integer rfd_latency; // number of cycles after ND that RFD can be asserted again +integer reloading; // true if the filter is in the process of reloading +integer reloading_one_cycle; // true if it is one cycle since COEF_LD was asserted + +integer prev_reset; // to track if there was a reset in the previous clock + // cycle, and has been removed now. +//--------------------------------------------------------- +// initialise +//--------------------------------------------------------- + + initial + begin + if(C_USE_MODEL_FUNC == 1) + begin + $display("%m,%dns ERROR: This model has not been set up to compute latency. Please call Xilinx Support.", $time); + $stop; + end + else + c_pipe_stages = C_LATENCY - 1; // Subtract one since the model doesn't count the first rising edge + rfd_latency = compute_rfd_latency(C_FILTER_TYPE); + if (C_HAS_SIN_F || C_HAS_SOUT_F) // cascaded + c_pipe_stages = c_pipe_stages - 1; // We Wait for a cycle before storing it + + // coefficient checks + if(C_FILTER_TYPE == `c_half_band) + if(C_TAPS % 2 == 0) + begin + $display("%m,%dns ERROR: for halfband filters the number of taps must be odd", $time); + $display("%m,%dns -- No of taps is set to %d \n Exiting simulation...", $time, C_TAPS); + $stop; + end + + // read coefficients from the MIF file + $readmemh(C_MEM_INIT_FILE, c_data); + c_taps_2 = C_TAPS/2; + + // Allocate to absolute value array and set the sign of each coefficient + // Convert NRZ coefficients to signed + for (i=0;i < C_TAPS; i= i+1) + begin + tmp_c_data = c_data[i]; + if( C_COEFF_TYPE == `c_signed && tmp_c_data[C_COEFF_WIDTH - 1] === 1'b1) + begin + c_int_data[i] = ~tmp_c_data +1; + c_data_sign[i] = 1; + end + else if (C_COEFF_TYPE == `c_nrz) + begin + if (tmp_c_data[0] === 1'b0) + c_data_sign[i] = 0; + else + c_data_sign[i] = 1; + c_int_data[i] = 1'b1; + end + else + begin + c_int_data[i] = tmp_c_data; + c_data_sign[i] = 0; + end + end + + RFD = 1; + reloading = `false; + reloading_one_cycle = `false; + + sel_i = 0; + if(C_HAS_SEL_I) + SEL_I <= 1'b0; + + sel_o = 0; + if(C_HAS_SEL_O) + SEL_O <= 1'b0; + + // do all initialization common to startup and to reloading + do_initialize; + + prev_reset = 0; + + end //initial + + +//--------------------------------------------------------- +// always on posedge of clock +//--------------------------------------------------------- + + always@ (posedge CLK) + begin + // Reset DOUT if RST input is active + if (C_HAS_RESET && RST === 1'b1) + begin + //DOUT <= `all0s; + do_initialize; + RFD <= 1'b0; + prev_reset = 1; + + sel_i = 0; + if(C_HAS_SEL_I) + SEL_I <= 1'b0; + + if(C_HAS_SEL_O) + begin + sel_o = 0; + SEL_O <= 1'b0; + end + if (C_RELOAD != `c_no_reload) + begin + reloading = `false; + reloading_one_cycle = `false; + end + + if(reloading == `true) + begin + $display("%m,%dns WARNING: Coefficient reloading was already in progress when RST occured. So stopping the reload process midway. Start the reloading again to get valid results at the output.", $time); + end + end + else + begin + if(prev_reset == 1) + begin + RFD <= 1'b1; + prev_reset = 0; + end + + // handle the load coefficients + if (C_RELOAD == `c_stop_during_reload && COEF_LD === 1'b1 ) + begin + if (reloading == `true) + begin + $display("%m,%dns ERROR: Reloading is already in progress. Please assert COEF_LD only after the current reload has been completed", $time); + $stop; + end + + reloading = `true; + + sel_i = 0; + if(C_HAS_SEL_I) + SEL_I <= 1'b0; + + if(C_HAS_SEL_O) + begin + sel_o = 0; + SEL_O <= 1'b0; + end + + /* if(RDY === 1'b1) + begin + if(C_HAS_SEL_O == 1) + begin + sel_o = (sel_o >= C_CHANNELS - 1)? 0: sel_o+1; + SEL_O <= sel_o; + end + end + */ + + // do all initialization common to startup and to reloading + do_initialize; + + if (LD_WE === 1'b1) + begin + $display("%m,%dns ERROR: LD_WE must only be asserted the cycle after COEF_LD is asserted.", $time); + $stop; + end + RFD = 0; + end // Stop during reload AND COEF_LD = 1 + + if (C_RELOAD == `c_stop_during_reload && LD_WE === 1'b1 ) + begin + if (reloading == `false) + begin + $display("%m,%dns Warning: LD_WE must only be asserted when the filter is in the process of reloading. Please assert COEF_LD to start the reload process.", $time); + end + if (load_counter >= num_reload_coefs) + begin + $display("%m,%dns Warning: The required number of coefficients have already been provided. LD_WE and LD_DIN will be ignored.", $time); + end + + tmp_c_data = LD_DIN; + // Save the absolute value of the coefficient as well as its sign + if( C_COEFF_TYPE == `c_signed && tmp_c_data[C_COEFF_WIDTH - 1] === 1'b1) + begin + c_int_data[load_counter] = ~tmp_c_data +1; + c_data_sign[load_counter] = 1; + end + + // Convert NRZ coefficients to signed + else if (C_COEFF_TYPE == `c_nrz) + begin + if (tmp_c_data[0] === 1'b0) + c_data_sign[load_counter] = 0; + else + c_data_sign[load_counter] = 1; + c_int_data[load_counter] = 1'b1; + end + else + begin + c_int_data[load_counter] = tmp_c_data; + c_data_sign[load_counter] = 0; + end + + // For symmetric or negative symmetric coefficients, update the coefficient + // mirror posn, and update the sign accordingly + if (C_RESPONSE == `c_symmetric) + begin + c_int_data[C_TAPS-load_counter - 1] = c_int_data[load_counter]; + c_data_sign[C_TAPS-load_counter - 1] = c_data_sign[load_counter]; + end + else if (C_RESPONSE == `c_neg_symmetric && (C_TAPS % 2 == 0 || load_counter < (C_TAPS - 1)/2)) + begin + c_int_data[C_TAPS-load_counter - 1] = c_int_data[load_counter]; + c_data_sign[C_TAPS-load_counter - 1] = (c_data_sign[load_counter]+1)%2; + end + + load_counter = load_counter + 1; + // All coefficients have been supplied. RFD will be asserted in C_RELOAD_DELAY cycles + if ((load_counter) >= num_reload_coefs ) + count_rfd_non_decimating = C_RELOAD_DELAY; + + end // Stop during reload AND LD_WE = 1 + + if (reloading == `true) + begin + if (count_rfd_non_decimating > 0) + begin + count_rfd_non_decimating = count_rfd_non_decimating - 1; + + // Filter reloading has completed, and the filter is ready to assert RFD + if (count_rfd_non_decimating == 0) + begin + reloading = `false; + reloading_one_cycle = `false; + end + end + end + + // Filter is NOT in the process of reloading the coefficients + else + begin + // For all results waiting to be output, decrement the number of cycles before RDY should be asserted + for(j = 0; j 0) // A previous computation has not yet completed + do_compute_result = `false; + else + begin + do_compute_result = `true; + count_rfd[0] = rfd_latency; + end + end + + if (do_compute_result) + if (subfilter_num_samples_buffer[C_POLYPHASE_FACTOR - 1] > 0) + // Each subfilter has one sample read out from the input buffer for each computation + for (i = 0; i < C_POLYPHASE_FACTOR; i = i + 1) + subfilter_num_samples_buffer[i] = subfilter_num_samples_buffer[i] - 1; + + + // Determine if RFD should be enabled by checking if the last register has data + if (subfilter_num_samples_buffer[C_POLYPHASE_FACTOR - 1] == 0) + RFD <= 1; + else if (subfilter_num_samples_buffer[C_POLYPHASE_FACTOR - 1] == 1) + if (do_compute_result) // A computation will be started and a sample will be read from each subfilter + RFD <= 1; + else + if (count_rfd[0] == 0) // No computation is busy being performed + RFD <= 1; + else // The input buffer cannot except any more samples even though samples will be read out of the buffer + RFD <= 0; + // Cannot accept any more samples because the register is full and a new computation is not ready to begin + else + RFD <= 0; + + end // Single channel Decimating filters + + //----------------------------------------------------------------------------------------- + // Multi-channel Decimating filters + //----------------------------------------------------------------------------------------- + else + begin + // Compute a result every time "C_POLYPHASE_FACTOR" samples have been received and there is no + // prior computation being performed. + if (subfilter_num_samples_buffer[C_POLYPHASE_FACTOR - 1] >= 1) + begin + // A previous computation has not yet completed + if ( (subfilter_number_delayed == C_POLYPHASE_FACTOR - 1) && (ND == 1'b1) && (RFD === 1'b1) ) + begin + do_compute_result = `true; + count_rfd[compute_channel_select] = rfd_latency; + end + else + do_compute_result = `false; + end + + // Update number of samples left in the each subfilter buffer after data has been read out of the buffer + if (subfilter_num_samples_buffer[C_POLYPHASE_FACTOR - 1] > 0) + begin + if (delay_first_read_flag) + begin + if (read_buffer_to_rfd_counter == 0) + begin + read_buffer_to_rfd_counter = rfd_latency; + + // Each subfilter has one sample read out from the input buffer for each computation + for (i = 0; i < C_POLYPHASE_FACTOR; i = i + 1) + subfilter_num_samples_buffer[i] = subfilter_num_samples_buffer[i] - 1; + end + end + + // Set flag indicating that the first data sample has been written into the last subfilter + // input buffer. This is needed so that the "read_buffer_to_rfd_counter" does NOT start + // until one clock after the first sample has been written to the last subfilter buffer. + delay_first_read_flag = 1; + + end + // The last subfilter's input buffer is empty + else + delay_first_read_flag = 0; + + // Input FIFOs are created for multi-channel filters. Once the last FIFO has been filled with + // "MAX_NUMBER_SAMPLES" samples, no more inputs will be accepted. + // Determine if RFD should be enabled by looking at input FIFO of the LAST channel only. + if (subfilter_num_samples_buffer[C_POLYPHASE_FACTOR - 1] < `MAX_NUMBER_SAMPLES) + if (RFD === 1'b1) + RFD <= 1; + // Allow new data to be received after data has been output and data has been read from the input buffers + else if ( read_buffer_to_rfd_counter == rfd_latency ) + RFD <= 1; + else + RFD <= 0; + // The last subfilter's input buffer is full + else + RFD <= 0; + + end // Multiple channel implementation + end // Decimating filter + + // NOT a decimating filter + else if (count_rfd_non_decimating > 0) + RFD <= 0; + else + RFD <= 1; + + //----------------------------------------------------------------------------------------- + // Update the SEL_I port and other signals (for Non-Decimating filters) + //----------------------------------------------------------------------------------------- + if (ND === 1'b1 && RFD === 1'b1) + begin + // NOT a Decimating filter + if (C_FILTER_TYPE != `c_polyphase_decimating && C_FILTER_TYPE != `c_decimating_half_band) + begin + count_rfd_non_decimating = rfd_latency; + if (count_rfd_non_decimating > 0) + RFD <= 0; + + do_compute_result = `true; + end + + if (!C_HAS_SIN_F && !C_HAS_SOUT_F) // Not cascaded + begin + prev_sel_i = sel_i; + sel_i = (sel_i >= C_CHANNELS - 1) ? 0 : sel_i+1; + if(C_HAS_SEL_I) + SEL_I <= sel_i; + end // Not cascaded + end // ND high and RFD high + + else + // NOT a Decimating filter + if (C_FILTER_TYPE != `c_polyphase_decimating && C_FILTER_TYPE != `c_decimating_half_band) + do_compute_result = `false; + + //----------------------------------------------------------------------------------------- + // Compute a new result + //----------------------------------------------------------------------------------------- + if (do_compute_result) + begin + compute_result(c_pipe_stages); + + // for interpolating filters, stuff zeros into data memory, and compute the new results + if (C_FILTER_TYPE == `c_polyphase_interpolating || C_FILTER_TYPE == `c_interpolating_half_band) + begin + for (i=1; i 0) ) + begin + new_data[next_data_output_channel] = new_data[next_data_output_channel] - 1; + for(j = 0; j < new_data[next_data_output_channel]; j=j+1) + count_rdy[(next_data_output_channel * back_data_per_channel + j)] = count_rdy[(next_data_output_channel * back_data_per_channel + j+1)]; + + data_output_channel = next_data_output_channel; + next_data_output_channel = (next_data_output_channel == (C_CHANNELS - 1)) ? 0 : next_data_output_channel + 1; + data_output_rdy = 1; // Set signal that indicates that a channel has data available + end + + prevRDY = RDY; + if (data_output_rdy == 1) + begin + if (C_FILTER_TYPE == `c_polyphase_interpolating || C_FILTER_TYPE == `c_interpolating_half_band) + rdy_counter = 0; + else + rdy_counter = rfd_latency; + + RDY <= 1; + + // place output on DOUT + if(C_FILTER_TYPE != `c_hilbert_transform) + DOUT <= tmpDOUT[(data_output_channel*back_data_per_channel + new_data[data_output_channel])]; + else + begin + DOUT_I <= x_hilbert[(data_output_channel*back_data_per_channel + new_data[data_output_channel])]; + DOUT_Q <= tmpDOUT[(data_output_channel*back_data_per_channel + new_data[data_output_channel])]; + end + end + else // No data is available to be output + begin + prevRDY = RDY; + RDY <= 0; + // If outputs are not registered, and RDY is low, set DOUT (or DOUT_I and DOUT_Q) to Xs + if(C_REG_OUTPUT == 0) + begin + if(C_FILTER_TYPE != `c_hilbert_transform) + DOUT <= `allXs; + else + begin + DOUT_I <= {C_DATA_WIDTH{1'bx}}; + DOUT_Q <= `allXs; + end + end + end + + // Update SEL_O the cycle after RDY is asserted + if (prevRDY === 1'b1) + begin + if (C_HAS_SEL_O == 1) + begin + sel_o = (sel_o >= C_CHANNELS - 1)? 0: sel_o+1; + SEL_O <= sel_o; + end + end + end // reloading + end //reset else block + end //always + + // cascade init. Cascading has not been updated for reloading or NRZ + initial + begin + cascade_in_cycle_number = cascade_num_cycles+1; + cascade_out_cycle_number = cascade_num_cycles+1; + delay1ND = 1'b0; + delay2ND = 1'b0; + save_casc_f = {extwidth{1'b0}}; + save_casc_r = {extwidth{1'b0}}; + end // initial + + // Handle cascading. Cascading has not been updated for reloading or NRZ + task handle_cascading; + reg [C_DATA_WIDTH - 1:0] saved_din, new_f_data, new_r_data, saved_int_data; + reg [extwidth - 1:0] save_casc_f_out, save_casc_r_out; + begin + + if (ND === 1'b1 && RFD === 1'b1) + begin + if (!C_HAS_SIN_F) + saved_din <= DIN; + end + else if (delay2ND === 1'b1) + begin + save_casc_f = {extwidth{1'b0}}; + save_casc_r = {extwidth{1'b0}}; + cascade_in_cycle_number = 1; + end + + // if we are reading in data, finish doing so + if (cascade_in_cycle_number <= cascade_num_cycles && C_DATA_WIDTH != C_BAAT) + begin + if (C_HAS_SIN_F) + save_casc_f = save_casc_f | (CAS_F_IN << ((cascade_in_cycle_number - 1)*C_BAAT)); + if (C_HAS_SIN_R) + save_casc_r = save_casc_r | (CAS_R_IN << ((cascade_in_cycle_number - 1)*C_BAAT)); + cascade_in_cycle_number = cascade_in_cycle_number + 1; + end + + if (delay1ND === 1'b1) + begin + if (!C_HAS_SIN_F) + new_f_data = saved_din; + else if (C_BAAT == C_DATA_WIDTH) // pda + new_f_data = CAS_F_IN; + else + new_f_data = save_casc_f[C_DATA_WIDTH - 1:0]; + + if (C_HAS_SIN_R) + if (C_BAAT == C_DATA_WIDTH) // pda + new_r_data = CAS_R_IN; + else + new_r_data = save_casc_r[C_DATA_WIDTH - 1:0]; + + shift_cascaded_data(new_f_data, new_r_data); // shift in the new data + compute_result(c_pipe_stages); + + if (C_HAS_SOUT_F || C_HAS_SOUT_R) + begin + saved_int_data = x_int_data[sel_i*C_TAPS]; + if (C_DATA_TYPE == `c_signed && saved_int_data[C_DATA_WIDTH - 1] === 1'b1) + save_casc_r_out = {{extwidth-C_DATA_WIDTH{1'b1}}, saved_int_data}; // sign extend + else + save_casc_r_out = saved_int_data; + if (C_RESPONSE == `c_non_symmetric) + save_casc_f_out = save_casc_r_out; + else + begin + saved_int_data = x_int_data[sel_i*C_TAPS + C_TAPS/2]; + if (C_DATA_TYPE == `c_signed && saved_int_data[C_DATA_WIDTH - 1] === 1'b1) + save_casc_f_out = {{extwidth-C_DATA_WIDTH{1'b1}}, saved_int_data}; // sign extend + else + save_casc_f_out = saved_int_data; + end + cascade_out_cycle_number = 1; + end + end // delay1ND === 1'b1 + // if we were writing out data, finish doing so + if (cascade_out_cycle_number <= cascade_num_cycles) + begin + if (C_HAS_SOUT_F) + begin + CAS_F_OUT <= #1 save_casc_f_out[C_BAAT - 1:0]; + save_casc_f_out = save_casc_f_out >> C_BAAT; + end + if (C_HAS_SOUT_R) + begin + CAS_R_OUT <= #1 save_casc_r_out[C_BAAT - 1:0]; + save_casc_r_out = save_casc_r_out >> C_BAAT; + end + cascade_out_cycle_number = cascade_out_cycle_number + 1; + end + else if (cascade_out_cycle_number == cascade_num_cycles+1 && C_BAAT != C_DATA_WIDTH) + begin + if (C_HAS_SOUT_F) + if (C_RESPONSE == `c_non_symmetric) + if (C_TAPS == 1) + CAS_F_OUT <= #1 save_casc_f[C_BAAT - 1:0]; + else + CAS_F_OUT <= #1 x_int_data[sel_i*C_TAPS+1]; + else + if (C_TAPS == 2) + CAS_F_OUT <= #1 save_casc_f[C_BAAT - 1:0]; + else + CAS_F_OUT <= #1 x_int_data[sel_i*C_TAPS + 1 + C_TAPS/2]; + if (C_HAS_SOUT_R) + if (C_TAPS == 2 || (C_HAS_SIN_F && C_HAS_SOUT_F && C_TAPS == 3)) + CAS_R_OUT <= #1 save_casc_r[C_BAAT - 1:0]; + else + CAS_R_OUT <= #1 x_int_data[sel_i*C_TAPS + 1]; + cascade_out_cycle_number = cascade_out_cycle_number + 1; + end + + delay2ND = delay1ND; + delay1ND = ND; +end +endtask + + // shift in the new input data + task shift_data; + input [C_DATA_WIDTH - 1:0] datain; + begin + // Increment the count of the number of samples stored in the input buffer (for decimating filters). Each + // subfilter holds multiple samples for every channel. For multi-channel operation, each new sample + // is the data for the next sequential channel. Once every channel has gotten a sample, the subsequent + // N samples (N = number of channels) are written to the next subfilter. A new computation is started + // once a channel has at least one sample in every subfilter. + if (C_FILTER_TYPE == `c_polyphase_decimating || C_FILTER_TYPE == `c_decimating_half_band) + begin + subfilter_num_samples_buffer[subfilter_number] = subfilter_num_samples_buffer[subfilter_number] + 1; + + // This variable is used to control when a new computation can is started. + subfilter_number_delayed = subfilter_number; + + // After each channel has received a sample, subsequent data will be written to the next subfilter + if (sel_i == C_CHANNELS - 1) + subfilter_number = (subfilter_number == C_POLYPHASE_FACTOR - 1) ? 0 : subfilter_number + 1; + end + + // All filters except Interpolated FIRs + if ( C_FILTER_TYPE == `c_single_rate_fir + || C_FILTER_TYPE == `c_half_band + || C_FILTER_TYPE == `c_polyphase_decimating + || C_FILTER_TYPE == `c_polyphase_interpolating + || C_FILTER_TYPE == `c_interpolating_half_band + || C_FILTER_TYPE == `c_decimating_half_band + || C_FILTER_TYPE == `c_hilbert_transform) + begin + // move data through only for the current sel_i channel + for ( j = C_TAPS - 1 ; j > 0; j = j - 1) + begin + x_int_data[sel_i*C_TAPS + j] = x_int_data[sel_i*C_TAPS + j - 1]; + x_data_sign[sel_i*C_TAPS + j] = x_data_sign[sel_i*C_TAPS + j - 1]; + end + + // For signed data that is negative, take the 2's complement of the data and set the sign bit high + if ( C_DATA_TYPE == `c_signed && datain[C_DATA_WIDTH - 1] === 1'b1) + begin + x_int_data[sel_i*C_TAPS] = ~datain +1; + x_data_sign[sel_i*C_TAPS] = 1; + end + else if (C_DATA_TYPE == `c_nrz) + begin + if (datain == 1'b0) + x_data_sign[sel_i*C_TAPS] = 0; + else + x_data_sign[sel_i*C_TAPS] = 1; + + x_int_data[sel_i*C_TAPS] = 1'b1; + end + // For unsigned data or positive, signed data, move the new data into memory + else + begin + x_int_data[sel_i*C_TAPS] = datain; + x_data_sign[sel_i*C_TAPS] = 0; + end + end + + else if (C_FILTER_TYPE == `c_interpolated_fir) + begin + // move data through only for current sel_i channel + for ( j = zpf_taps - 1 ; j > 0; j = j - 1) + begin + x_zpf_data[sel_i*zpf_taps+j] = x_zpf_data[sel_i*zpf_taps+j - 1]; + x_zpf_data_sign[sel_i*zpf_taps+j] = x_zpf_data_sign[sel_i*zpf_taps+j - 1]; + end + + // Save the new data as an absolute value and a sign + if( C_DATA_TYPE == `c_signed && datain[C_DATA_WIDTH - 1] === 1'b1) + begin + x_zpf_data[sel_i*zpf_taps] = ~datain +1; + x_zpf_data_sign[sel_i*zpf_taps] = 1; + end + else if (C_DATA_TYPE == `c_nrz) + begin + if (datain == 1'b0) + x_zpf_data_sign[sel_i*zpf_taps] = 0; + else + x_zpf_data_sign[sel_i*zpf_taps] = 1; + x_zpf_data[sel_i*zpf_taps] = 1'b1; + end + else + begin + x_zpf_data[sel_i*zpf_taps] = datain; + x_zpf_data_sign[sel_i*zpf_taps] = 0; + end + end + end + endtask // shift_data + +// cascading has not been updated for nrz or for reloading +// Note that new data is now shifted into position 0 - this task must be changed + task shift_cascaded_data; + input [C_DATA_WIDTH - 1:0] dataf, datar; + integer midpoint; + begin + midpoint = C_TAPS/2; + + if (C_HAS_SIN_R) + begin + for (j=0; j0; j= j - 1) + begin + tmpDOUT[(compute_channel_select*back_data_per_channel + j)] = tmpDOUT[(compute_channel_select*back_data_per_channel + j - 1)]; + x_hilbert[(compute_channel_select*back_data_per_channel + j)] = x_hilbert[(compute_channel_select*back_data_per_channel + j - 1)]; + end + + tmpDOUT[(compute_channel_select*back_data_per_channel)] = new_result; + + // This is only used by hilbert transform FIRs + tmp_x_data = x_int_data[compute_channel_select*C_TAPS - 1 + (C_TAPS+1)/2]; + x_is_signed = x_data_sign[compute_channel_select*C_TAPS - 1 + (C_TAPS+1)/2]; + if (x_is_signed == 1) + x_hilbert[(compute_channel_select*back_data_per_channel)] = ~tmp_x_data + 1; + else + x_hilbert[(compute_channel_select*back_data_per_channel)] = tmp_x_data; + + // Save the number of cycles before the result is placed on the output + count_rdy[(compute_channel_select*back_data_per_channel + (new_data[compute_channel_select]))] = pipeline_length; + new_data[compute_channel_select] = new_data[compute_channel_select] + 1; + + // Update channel number that will begin the next computation + if (compute_channel_select < C_CHANNELS - 1) + compute_channel_select = compute_channel_select + 1; + else + compute_channel_select = 0; + + end + endtask // compute_result + + // All initialization required at startup, and at reloading + task do_initialize; + begin + // set the data array to zero + for (i=0; i<= C_CHANNELS*C_TAPS - 1; i= i+1) + begin + if (C_DATA_TYPE === `c_nrz) + x_int_data[i] = 1'b1; + else + x_int_data[i] = 0; + x_data_sign[i] = 0; + end + for (i=0; i<= C_CHANNELS*zpf_taps - 1; i= i+1) + begin + if (C_DATA_TYPE === `c_nrz) + x_zpf_data[i] = 1'b1; + else + x_zpf_data[i] = 0; + x_zpf_data_sign[i] = 0; + end + + if (C_FILTER_TYPE != `c_hilbert_transform) + begin + if (C_REG_OUTPUT == 0) + DOUT <= `allXs; + else + DOUT <= `all0s; + end + else + begin + if (C_REG_OUTPUT == 0) + begin + DOUT_I <= {C_DATA_WIDTH{1'bx}}; + DOUT_Q <= `allXs; + end + else + begin + DOUT_I <= {C_DATA_WIDTH{1'b0}}; + DOUT_Q <= `all0s; + end + end + + for (i=0;i= C_CHANNELS - 1)? 0: sel_o+1; + SEL_O <= sel_o; + end + end + */ + + // do all initialization common to startup and to reloading + do_initialize; + + if (LD_WE === 1'b1) + begin + $display("%m,%dns ERROR: LD_WE must only be asserted the cycle after COEF_LD is asserted.", $time); + $stop; + end + RFD = 0; + end // Stop during reload AND COEF_LD = 1 + + if (C_RELOAD == `c_stop_during_reload && LD_WE === 1'b1 ) + begin + if (reloading == `false) + begin + $display("%m,%dns Warning: LD_WE must only be asserted when the filter is in the process of reloading. Please assert COEF_LD to start the reload process.", $time); + end + if (load_counter >= num_reload_coefs) + begin + $display("%m,%dns Warning: The required number of coefficients have already been provided. LD_WE and LD_DIN will be ignored.", $time); + end + + tmp_c_data = LD_DIN; + // Save the absolute value of the coefficient as well as its sign + if( C_COEFF_TYPE == `c_signed && tmp_c_data[C_COEFF_WIDTH - 1] === 1'b1) + begin + c_int_data[load_counter] = ~tmp_c_data +1; + c_data_sign[load_counter] = 1; + end + + // Convert NRZ coefficients to signed + else if (C_COEFF_TYPE == `c_nrz) + begin + if (tmp_c_data[0] === 1'b0) + c_data_sign[load_counter] = 0; + else + c_data_sign[load_counter] = 1; + c_int_data[load_counter] = 1'b1; + end + else + begin + c_int_data[load_counter] = tmp_c_data; + c_data_sign[load_counter] = 0; + end + + // For symmetric or negative symmetric coefficients, update the coefficient + // mirror posn, and update the sign accordingly + if (C_RESPONSE == `c_symmetric) + begin + c_int_data[C_TAPS-load_counter - 1] = c_int_data[load_counter]; + c_data_sign[C_TAPS-load_counter - 1] = c_data_sign[load_counter]; + end + else if (C_RESPONSE == `c_neg_symmetric && (C_TAPS % 2 == 0 || load_counter < (C_TAPS - 1)/2)) + begin + c_int_data[C_TAPS-load_counter - 1] = c_int_data[load_counter]; + c_data_sign[C_TAPS-load_counter - 1] = (c_data_sign[load_counter]+1)%2; + end + + load_counter = load_counter + 1; + // All coefficients have been supplied. RFD will be asserted in C_RELOAD_DELAY cycles + if ((load_counter) >= num_reload_coefs ) + count_rfd_non_decimating = C_RELOAD_DELAY; + + end // Stop during reload AND LD_WE = 1 + + if (reloading == `true) + begin + if (count_rfd_non_decimating > 0) + begin + count_rfd_non_decimating = count_rfd_non_decimating - 1; + + // Filter reloading has completed, and the filter is ready to assert RFD + if (count_rfd_non_decimating == 0) + begin + reloading = `false; + reloading_one_cycle = `false; + end + end + end + + // Filter is NOT in the process of reloading the coefficients + else + begin + // For all results waiting to be output, decrement the number of cycles before RDY should be asserted + for(j = 0; j 0) // A previous computation has not yet completed + do_compute_result = `false; + else + begin + do_compute_result = `true; + count_rfd[0] = rfd_latency; + end + end + + if (do_compute_result) + if (subfilter_num_samples_buffer[C_POLYPHASE_FACTOR - 1] > 0) + // Each subfilter has one sample read out from the input buffer for each computation + for (i = 0; i < C_POLYPHASE_FACTOR; i = i + 1) + subfilter_num_samples_buffer[i] = subfilter_num_samples_buffer[i] - 1; + + + // Determine if RFD should be enabled by checking if the last register has data + if (subfilter_num_samples_buffer[C_POLYPHASE_FACTOR - 1] == 0) + RFD <= 1; + else if (subfilter_num_samples_buffer[C_POLYPHASE_FACTOR - 1] == 1) + if (do_compute_result) // A computation will be started and a sample will be read from each subfilter + RFD <= 1; + else + if (count_rfd[0] == 0) // No computation is busy being performed + RFD <= 1; + else // The input buffer cannot except any more samples even though samples will be read out of the buffer + RFD <= 0; + // Cannot accept any more samples because the register is full and a new computation is not ready to begin + else + RFD <= 0; + + end // Single channel Decimating filters + + //----------------------------------------------------------------------------------------- + // Multi-channel Decimating filters + //----------------------------------------------------------------------------------------- + else + begin + // Compute a result every time "C_POLYPHASE_FACTOR" samples have been received and there is no + // prior computation being performed. + if (subfilter_num_samples_buffer[C_POLYPHASE_FACTOR - 1] >= 1) + begin + // A previous computation has not yet completed + if ( (subfilter_number_delayed == C_POLYPHASE_FACTOR - 1) && (ND == 1'b1) && (RFD === 1'b1) ) + begin + do_compute_result = `true; + count_rfd[compute_channel_select] = rfd_latency; + end + else + do_compute_result = `false; + end + + // Update number of samples left in the each subfilter buffer after data has been read out of the buffer + if (subfilter_num_samples_buffer[C_POLYPHASE_FACTOR - 1] > 0) + begin + if (delay_first_read_flag) + begin + if (read_buffer_to_rfd_counter == 0) + begin + read_buffer_to_rfd_counter = rfd_latency; + + // Each subfilter has one sample read out from the input buffer for each computation + for (i = 0; i < C_POLYPHASE_FACTOR; i = i + 1) + subfilter_num_samples_buffer[i] = subfilter_num_samples_buffer[i] - 1; + end + end + + // Set flag indicating that the first data sample has been written into the last subfilter + // input buffer. This is needed so that the "read_buffer_to_rfd_counter" does NOT start + // until one clock after the first sample has been written to the last subfilter buffer. + delay_first_read_flag = 1; + + end + // The last subfilter's input buffer is empty + else + delay_first_read_flag = 0; + + // Input FIFOs are created for multi-channel filters. Once the last FIFO has been filled with + // "MAX_NUMBER_SAMPLES" samples, no more inputs will be accepted. + // Determine if RFD should be enabled by looking at input FIFO of the LAST channel only. + if (subfilter_num_samples_buffer[C_POLYPHASE_FACTOR - 1] < `MAX_NUMBER_SAMPLES) + if (RFD === 1'b1) + RFD <= 1; + // Allow new data to be received after data has been output and data has been read from the input buffers + else if ( read_buffer_to_rfd_counter == rfd_latency ) + RFD <= 1; + else + RFD <= 0; + // The last subfilter's input buffer is full + else + RFD <= 0; + + end // Multiple channel implementation + end // Decimating filter + + // NOT a decimating filter + else if (count_rfd_non_decimating > 0) + RFD <= 0; + else + RFD <= 1; + + //----------------------------------------------------------------------------------------- + // Update the SEL_I port and other signals (for Non-Decimating filters) + //----------------------------------------------------------------------------------------- + if (ND === 1'b1 && RFD === 1'b1) + begin + // NOT a Decimating filter + if (C_FILTER_TYPE != `c_polyphase_decimating && C_FILTER_TYPE != `c_decimating_half_band) + begin + count_rfd_non_decimating = rfd_latency; + if (count_rfd_non_decimating > 0) + RFD <= 0; + + do_compute_result = `true; + end + + if (!C_HAS_SIN_F && !C_HAS_SOUT_F) // Not cascaded + begin + prev_sel_i = sel_i; + sel_i = (sel_i >= C_CHANNELS - 1) ? 0 : sel_i+1; + if(C_HAS_SEL_I) + SEL_I <= sel_i; + end // Not cascaded + end // ND high and RFD high + + else + // NOT a Decimating filter + if (C_FILTER_TYPE != `c_polyphase_decimating && C_FILTER_TYPE != `c_decimating_half_band) + do_compute_result = `false; + + //----------------------------------------------------------------------------------------- + // Compute a new result + //----------------------------------------------------------------------------------------- + if (do_compute_result) + begin + compute_result(c_pipe_stages); + + // for interpolating filters, stuff zeros into data memory, and compute the new results + if (C_FILTER_TYPE == `c_polyphase_interpolating || C_FILTER_TYPE == `c_interpolating_half_band) + begin + for (i=1; i 0) ) + begin + new_data[next_data_output_channel] = new_data[next_data_output_channel] - 1; + for(j = 0; j < new_data[next_data_output_channel]; j=j+1) + count_rdy[(next_data_output_channel * back_data_per_channel + j)] = count_rdy[(next_data_output_channel * back_data_per_channel + j+1)]; + + data_output_channel = next_data_output_channel; + next_data_output_channel = (next_data_output_channel == (C_CHANNELS - 1)) ? 0 : next_data_output_channel + 1; + data_output_rdy = 1; // Set signal that indicates that a channel has data available + end + + prevRDY = RDY; + if (data_output_rdy == 1) + begin + if (C_FILTER_TYPE == `c_polyphase_interpolating || C_FILTER_TYPE == `c_interpolating_half_band) + rdy_counter = 0; + else + rdy_counter = rfd_latency; + + RDY <= 1; + + // place output on DOUT + if(C_FILTER_TYPE != `c_hilbert_transform) + DOUT <= tmpDOUT[(data_output_channel*back_data_per_channel + new_data[data_output_channel])]; + else + begin + DOUT_I <= x_hilbert[(data_output_channel*back_data_per_channel + new_data[data_output_channel])]; + DOUT_Q <= tmpDOUT[(data_output_channel*back_data_per_channel + new_data[data_output_channel])]; + end + end + else // No data is available to be output + begin + prevRDY = RDY; + RDY <= 0; + // If outputs are not registered, and RDY is low, set DOUT (or DOUT_I and DOUT_Q) to Xs + if(C_REG_OUTPUT == 0) + begin + if(C_FILTER_TYPE != `c_hilbert_transform) + DOUT <= `allXs; + else + begin + DOUT_I <= {C_DATA_WIDTH{1'bx}}; + DOUT_Q <= `allXs; + end + end + end + + // Update SEL_O the cycle after RDY is asserted + if (prevRDY === 1'b1) + begin + if (C_HAS_SEL_O == 1) + begin + sel_o = (sel_o >= C_CHANNELS - 1)? 0: sel_o+1; + SEL_O <= sel_o; + end + end + end // reloading + end //reset else block + end //always + + // cascade init. Cascading has not been updated for reloading or NRZ + initial + begin + cascade_in_cycle_number = cascade_num_cycles+1; + cascade_out_cycle_number = cascade_num_cycles+1; + delay1ND = 1'b0; + delay2ND = 1'b0; + save_casc_f = {extwidth{1'b0}}; + save_casc_r = {extwidth{1'b0}}; + end // initial + + // Handle cascading. Cascading has not been updated for reloading or NRZ + task handle_cascading; + reg [C_DATA_WIDTH - 1:0] saved_din, new_f_data, new_r_data, saved_int_data; + reg [extwidth - 1:0] save_casc_f_out, save_casc_r_out; + begin + + if (ND === 1'b1 && RFD === 1'b1) + begin + if (!C_HAS_SIN_F) + saved_din <= DIN; + end + else if (delay2ND === 1'b1) + begin + save_casc_f = {extwidth{1'b0}}; + save_casc_r = {extwidth{1'b0}}; + cascade_in_cycle_number = 1; + end + + // if we are reading in data, finish doing so + if (cascade_in_cycle_number <= cascade_num_cycles && C_DATA_WIDTH != C_BAAT) + begin + if (C_HAS_SIN_F) + save_casc_f = save_casc_f | (CAS_F_IN << ((cascade_in_cycle_number - 1)*C_BAAT)); + if (C_HAS_SIN_R) + save_casc_r = save_casc_r | (CAS_R_IN << ((cascade_in_cycle_number - 1)*C_BAAT)); + cascade_in_cycle_number = cascade_in_cycle_number + 1; + end + + if (delay1ND === 1'b1) + begin + if (!C_HAS_SIN_F) + new_f_data = saved_din; + else if (C_BAAT == C_DATA_WIDTH) // pda + new_f_data = CAS_F_IN; + else + new_f_data = save_casc_f[C_DATA_WIDTH - 1:0]; + + if (C_HAS_SIN_R) + if (C_BAAT == C_DATA_WIDTH) // pda + new_r_data = CAS_R_IN; + else + new_r_data = save_casc_r[C_DATA_WIDTH - 1:0]; + + shift_cascaded_data(new_f_data, new_r_data); // shift in the new data + compute_result(c_pipe_stages); + + if (C_HAS_SOUT_F || C_HAS_SOUT_R) + begin + saved_int_data = x_int_data[sel_i*C_TAPS]; + if (C_DATA_TYPE == `c_signed && saved_int_data[C_DATA_WIDTH - 1] === 1'b1) + save_casc_r_out = {{extwidth-C_DATA_WIDTH{1'b1}}, saved_int_data}; // sign extend + else + save_casc_r_out = saved_int_data; + if (C_RESPONSE == `c_non_symmetric) + save_casc_f_out = save_casc_r_out; + else + begin + saved_int_data = x_int_data[sel_i*C_TAPS + C_TAPS/2]; + if (C_DATA_TYPE == `c_signed && saved_int_data[C_DATA_WIDTH - 1] === 1'b1) + save_casc_f_out = {{extwidth-C_DATA_WIDTH{1'b1}}, saved_int_data}; // sign extend + else + save_casc_f_out = saved_int_data; + end + cascade_out_cycle_number = 1; + end + end // delay1ND === 1'b1 + // if we were writing out data, finish doing so + if (cascade_out_cycle_number <= cascade_num_cycles) + begin + if (C_HAS_SOUT_F) + begin + CAS_F_OUT <= #1 save_casc_f_out[C_BAAT - 1:0]; + save_casc_f_out = save_casc_f_out >> C_BAAT; + end + if (C_HAS_SOUT_R) + begin + CAS_R_OUT <= #1 save_casc_r_out[C_BAAT - 1:0]; + save_casc_r_out = save_casc_r_out >> C_BAAT; + end + cascade_out_cycle_number = cascade_out_cycle_number + 1; + end + else if (cascade_out_cycle_number == cascade_num_cycles+1 && C_BAAT != C_DATA_WIDTH) + begin + if (C_HAS_SOUT_F) + if (C_RESPONSE == `c_non_symmetric) + if (C_TAPS == 1) + CAS_F_OUT <= #1 save_casc_f[C_BAAT - 1:0]; + else + CAS_F_OUT <= #1 x_int_data[sel_i*C_TAPS+1]; + else + if (C_TAPS == 2) + CAS_F_OUT <= #1 save_casc_f[C_BAAT - 1:0]; + else + CAS_F_OUT <= #1 x_int_data[sel_i*C_TAPS + 1 + C_TAPS/2]; + if (C_HAS_SOUT_R) + if (C_TAPS == 2 || (C_HAS_SIN_F && C_HAS_SOUT_F && C_TAPS == 3)) + CAS_R_OUT <= #1 save_casc_r[C_BAAT - 1:0]; + else + CAS_R_OUT <= #1 x_int_data[sel_i*C_TAPS + 1]; + cascade_out_cycle_number = cascade_out_cycle_number + 1; + end + + delay2ND = delay1ND; + delay1ND = ND; +end +endtask + + // shift in the new input data + task shift_data; + input [C_DATA_WIDTH - 1:0] datain; + begin + // Increment the count of the number of samples stored in the input buffer (for decimating filters). Each + // subfilter holds multiple samples for every channel. For multi-channel operation, each new sample + // is the data for the next sequential channel. Once every channel has gotten a sample, the subsequent + // N samples (N = number of channels) are written to the next subfilter. A new computation is started + // once a channel has at least one sample in every subfilter. + if (C_FILTER_TYPE == `c_polyphase_decimating || C_FILTER_TYPE == `c_decimating_half_band) + begin + subfilter_num_samples_buffer[subfilter_number] = subfilter_num_samples_buffer[subfilter_number] + 1; + + // This variable is used to control when a new computation can is started. + subfilter_number_delayed = subfilter_number; + + // After each channel has received a sample, subsequent data will be written to the next subfilter + if (sel_i == C_CHANNELS - 1) + subfilter_number = (subfilter_number == C_POLYPHASE_FACTOR - 1) ? 0 : subfilter_number + 1; + end + + // All filters except Interpolated FIRs + if ( C_FILTER_TYPE == `c_single_rate_fir + || C_FILTER_TYPE == `c_half_band + || C_FILTER_TYPE == `c_polyphase_decimating + || C_FILTER_TYPE == `c_polyphase_interpolating + || C_FILTER_TYPE == `c_interpolating_half_band + || C_FILTER_TYPE == `c_decimating_half_band + || C_FILTER_TYPE == `c_hilbert_transform) + begin + // move data through only for the current sel_i channel + for ( j = C_TAPS - 1 ; j > 0; j = j - 1) + begin + x_int_data[sel_i*C_TAPS + j] = x_int_data[sel_i*C_TAPS + j - 1]; + x_data_sign[sel_i*C_TAPS + j] = x_data_sign[sel_i*C_TAPS + j - 1]; + end + + // For signed data that is negative, take the 2's complement of the data and set the sign bit high + if ( C_DATA_TYPE == `c_signed && datain[C_DATA_WIDTH - 1] === 1'b1) + begin + x_int_data[sel_i*C_TAPS] = ~datain +1; + x_data_sign[sel_i*C_TAPS] = 1; + end + else if (C_DATA_TYPE == `c_nrz) + begin + if (datain == 1'b0) + x_data_sign[sel_i*C_TAPS] = 0; + else + x_data_sign[sel_i*C_TAPS] = 1; + + x_int_data[sel_i*C_TAPS] = 1'b1; + end + // For unsigned data or positive, signed data, move the new data into memory + else + begin + x_int_data[sel_i*C_TAPS] = datain; + x_data_sign[sel_i*C_TAPS] = 0; + end + end + + else if (C_FILTER_TYPE == `c_interpolated_fir) + begin + // move data through only for current sel_i channel + for ( j = zpf_taps - 1 ; j > 0; j = j - 1) + begin + x_zpf_data[sel_i*zpf_taps+j] = x_zpf_data[sel_i*zpf_taps+j - 1]; + x_zpf_data_sign[sel_i*zpf_taps+j] = x_zpf_data_sign[sel_i*zpf_taps+j - 1]; + end + + // Save the new data as an absolute value and a sign + if( C_DATA_TYPE == `c_signed && datain[C_DATA_WIDTH - 1] === 1'b1) + begin + x_zpf_data[sel_i*zpf_taps] = ~datain +1; + x_zpf_data_sign[sel_i*zpf_taps] = 1; + end + else if (C_DATA_TYPE == `c_nrz) + begin + if (datain == 1'b0) + x_zpf_data_sign[sel_i*zpf_taps] = 0; + else + x_zpf_data_sign[sel_i*zpf_taps] = 1; + x_zpf_data[sel_i*zpf_taps] = 1'b1; + end + else + begin + x_zpf_data[sel_i*zpf_taps] = datain; + x_zpf_data_sign[sel_i*zpf_taps] = 0; + end + end + end + endtask // shift_data + +// cascading has not been updated for nrz or for reloading +// Note that new data is now shifted into position 0 - this task must be changed + task shift_cascaded_data; + input [C_DATA_WIDTH - 1:0] dataf, datar; + integer midpoint; + begin + midpoint = C_TAPS/2; + + if (C_HAS_SIN_R) + begin + for (j=0; j0; j= j - 1) + begin + tmpDOUT[(compute_channel_select*back_data_per_channel + j)] = tmpDOUT[(compute_channel_select*back_data_per_channel + j - 1)]; + x_hilbert[(compute_channel_select*back_data_per_channel + j)] = x_hilbert[(compute_channel_select*back_data_per_channel + j - 1)]; + end + + tmpDOUT[(compute_channel_select*back_data_per_channel)] = new_result; + + // This is only used by hilbert transform FIRs + tmp_x_data = x_int_data[compute_channel_select*C_TAPS - 1 + (C_TAPS+1)/2]; + x_is_signed = x_data_sign[compute_channel_select*C_TAPS - 1 + (C_TAPS+1)/2]; + if (x_is_signed == 1) + x_hilbert[(compute_channel_select*back_data_per_channel)] = ~tmp_x_data + 1; + else + x_hilbert[(compute_channel_select*back_data_per_channel)] = tmp_x_data; + + // Save the number of cycles before the result is placed on the output + count_rdy[(compute_channel_select*back_data_per_channel + (new_data[compute_channel_select]))] = pipeline_length; + new_data[compute_channel_select] = new_data[compute_channel_select] + 1; + + // Update channel number that will begin the next computation + if (compute_channel_select < C_CHANNELS - 1) + compute_channel_select = compute_channel_select + 1; + else + compute_channel_select = 0; + + end + endtask // compute_result + + // All initialization required at startup, and at reloading + task do_initialize; + begin + // set the data array to zero + for (i=0; i<= C_CHANNELS*C_TAPS - 1; i= i+1) + begin + if (C_DATA_TYPE === `c_nrz) + x_int_data[i] = 1'b1; + else + x_int_data[i] = 0; + x_data_sign[i] = 0; + end + for (i=0; i<= C_CHANNELS*zpf_taps - 1; i= i+1) + begin + if (C_DATA_TYPE === `c_nrz) + x_zpf_data[i] = 1'b1; + else + x_zpf_data[i] = 0; + x_zpf_data_sign[i] = 0; + end + + if (C_FILTER_TYPE != `c_hilbert_transform) + begin + if (C_REG_OUTPUT == 0) + DOUT <= `allXs; + else + DOUT <= `all0s; + end + else + begin + if (C_REG_OUTPUT == 0) + begin + DOUT_I <= {C_DATA_WIDTH{1'bx}}; + DOUT_Q <= `allXs; + end + else + begin + DOUT_I <= {C_DATA_WIDTH{1'b0}}; + DOUT_Q <= `all0s; + end + end + + for (i=0;i4?(4*C_HAS_SPRA):0) : 0] A; + input [C_WIDTH-1 : 0] D; + input [C_ADDR_WIDTH-1 : 0] DPRA; + input [C_ADDR_WIDTH-1 : 0] SPRA; + input CLK; + input WE; + input I_CE; + input RD_EN; + input QSPO_CE; + input QDPO_CE; + input QDPO_CLK; + input QSPO_RST; + input QDPO_RST; + input QSPO_SRST; + input QDPO_SRST; + output [C_WIDTH-1 : 0] SPO; + output [C_WIDTH-1 : 0] QSPO; + output [C_WIDTH-1 : 0] DPO; + output [C_WIDTH-1 : 0] QDPO; + + // Address signal connected to memory + wire [C_ADDR_WIDTH - 1 : 0] a_int; + // Read Address signal connected to srl16-based memory + wire [C_ADDR_WIDTH - 1 : 0] spra_int; + // Registered Address signal connected to memory + wire [C_ADDR_WIDTH - 1 : 0] a_int1; + // Registered Read Address signal connected to srl16-based memory + wire [C_ADDR_WIDTH - 1 : 0] spra_int1; + // DP port address signal connected to memory + wire [C_ADDR_WIDTH - 1 : 0] dpra_int; + // DP port address signal connected to memory + wire [C_ADDR_WIDTH - 1 : 0] dpra_int1; + // Input data signal connected to memory + wire [C_WIDTH - 1 : 0] d_int; + // Registered Input data signal connected to memory + wire [C_WIDTH - 1 : 0] d_int1; + // DP output register clock + wire doclk; + // Input data/address/WE register Clock Enable + wire ice; + // Special address register Clock Enable for ROMs + wire a_reg_ice; + // DP read address port register clock enable +// wire dpra_ce; + // WE wire connected to memory + wire we_int; + // Registered WE wire connected to memory + wire we_int1; + // Clock enable for the WE register + wire wece; + // Read Enable wire connected to BUFT-type output mux + wire re_int; + // Registered Read Enable wire connected to BUFT-type output mux + wire re_int1; + // unregistered version of qspo_ce + wire qspo_ce_int; + // possibly registered version of qspo_ce + wire qspo_ce_reg; + // registered version of qspo_ce + wire qspo_ce_reg1; + // unregistered version of qdpo_ce + wire qdpo_ce_int; + // possibly registered version of qdpo_ce + wire qdpo_ce_reg; + // registered version of qdpo_ce + wire qdpo_ce_reg1; + // possibly single port registered output reset + wire qspo_rst_int; + // possibly dual port registered output reset + wire qdpo_rst_int; + // possibly single port registered output sync reset + wire qspo_srst_int; + // possibly dual port registered output sync reset + wire qdpo_srst_int; + // Direct SP output from memory + reg [C_WIDTH - 1 : 0] spo_async; + // Direct DP output from memory + reg [C_WIDTH - 1 : 0] dpo_async; + // Possibly pipelined and/or registered SP output from memory + wire [C_WIDTH - 1 : 0] intQSPO; + // Possibly pipelined and/or registered DP output from memory + wire [C_WIDTH - 1 : 0] intQDPO; + // Pipeline signals + reg [C_WIDTH - 1 : 0] spo_pipe [pipe_stages+2 : 0]; + reg [C_WIDTH - 1 : 0] dpo_pipe [dpo_pipe_stages+2 : 0]; + // Possibly pipelined SP output from memory + reg [C_WIDTH - 1 : 0] spo_pipeend; + // Possibly pipelined DP output from memory + reg [C_WIDTH - 1 : 0] dpo_pipeend; + // BUFT outputs + wire [C_WIDTH - 1 : 0] spo_reg; + wire [C_WIDTH - 1 : 0] dpo_reg; + wire [C_WIDTH - 1 : 0] spo_reg_tmp; + wire [C_WIDTH - 1 : 0] dpo_reg_tmp; + + integer pipe, pipe1, pipe2, pipe3, pipe4, i, j, srl_start, srl_end; + + // Array to hold ram data + reg [C_WIDTH-1 : 0] ram_data [C_DEPTH-1 : 0]; + reg [C_WIDTH-1 : 0] tmp_data1; + reg [C_WIDTH-1 : 0] tmp_data2; + + reg [C_WIDTH-1 : 0] default_data; + reg [C_WIDTH-1 : 0] spo_tmp; + reg [C_WIDTH-1 : 0] dpo_tmp; + reg [C_WIDTH-1 : 0] tmp_pipe1; + reg [C_WIDTH-1 : 0] tmp_pipe2; + reg [C_WIDTH-1 : 0] tmp_pipe3; + reg lastCLK; + reg lastdoclk; + + function integer ADDR_IS_X; + input [C_ADDR_WIDTH-1 : 0] value; + integer i; + begin + ADDR_IS_X = 0; + for(i = 0; i < C_ADDR_WIDTH; i = i + 1) + if(value[i] === 1'bx) + ADDR_IS_X = 1; + end + endfunction + + // Deal with the optional output signals... + wire [C_WIDTH - 1 : 0] SPO = (C_HAS_SPO ? (C_MUX_TYPE == `c_lut_based ? spo_async : spo_reg) : `allXs); + wire [C_WIDTH - 1 : 0] DPO = (C_HAS_DPO && C_MEM_TYPE == `c_dp_ram ? (C_MUX_TYPE == `c_lut_based ? dpo_async : dpo_reg) : `allXs); + wire [C_WIDTH - 1 : 0] QSPO = (C_HAS_QSPO ? intQSPO : `allXs); + wire [C_WIDTH - 1 : 0] QDPO = (C_HAS_QDPO ? intQDPO : `allXs); + + // Deal with the optional input signals... + + assign ice = (C_HAS_I_CE == 1 ? I_CE : 1'b1); + assign a_reg_ice = (C_MEM_TYPE == `c_rom ? qspo_ce_int : ice); + assign wece = (C_HAS_WE == 1 && C_REG_A_D_INPUTS == 1 && C_QUALIFY_WE == 1 ? ice : 1'b1); +// assign dpra_ce = (C_HAS_QDPO_CE == 1 ? QDPO_CE : 1'b1); + assign doclk = (C_HAS_QDPO_CLK == 1 ? QDPO_CLK : CLK); + assign qspo_ce_int = (C_HAS_QSPO_CE == 1 ? QSPO_CE : 1'b1); + assign qdpo_ce_int = (C_QCE_JOINED == 1 ? qspo_ce_int : (C_HAS_QDPO_CE == 1 ? QDPO_CE : ((C_HAS_QSPO == 1 && C_MEM_TYPE == `c_srl16) ? qspo_ce_int : 1'b1))); + assign qspo_rst_int = (C_HAS_QSPO_RST && C_HAS_QSPO ? QSPO_RST : 1'b0); + assign qdpo_rst_int = (C_HAS_QDPO_RST && C_HAS_QDPO ? QDPO_RST : 1'b0); + assign qspo_srst_int = (C_HAS_QSPO_SRST && C_HAS_QSPO ? QSPO_SRST : 1'b0); + assign qdpo_srst_int = (C_HAS_QDPO_SRST && C_HAS_QDPO ? QDPO_SRST : 1'b0); + + // (Optional) registers on SP address and on optional data/we/qspo_ce signals + C_REG_FD_V4_0 #("0", C_ENABLE_RLOCS, 0, 0, 0, + 0, 0, 0, 0, + "0", 0, 0, 1) + qspo1_reg (.D(qspo_ce_int), .CLK(CLK), .CE(1'b0), .ACLR(1'b0), .ASET(1'b0), + .AINIT(1'b0), .SCLR(1'b0), .SSET(1'b0), .SINIT(1'b0), + .Q(qspo_ce_reg1)); + + C_REG_FD_V4_0 #("0", C_ENABLE_RLOCS, 0, 0, 0, + 1, 0, 0, 0, + "0", 0, 0, (C_ADDR_WIDTH-(C_ADDR_WIDTH>4?(C_HAS_SPRA*4):0))) + a_rega (.D(A[C_ADDR_WIDTH - 1-(C_ADDR_WIDTH>4?(4*C_HAS_SPRA):0) : 0]), .CLK(CLK), .CE(a_reg_ice), .ACLR(1'b0), .ASET(1'b0), + .AINIT(1'b0), .SCLR(1'b0), .SSET(1'b0), .SINIT(1'b0), + .Q(a_int1[C_ADDR_WIDTH - 1-(C_ADDR_WIDTH>4?(4*C_HAS_SPRA):0) : 0])); + + C_REG_FD_V4_0 #("0", C_ENABLE_RLOCS, 0, 0, 0, + 1, 0, 0, 0, + "0", 0, 0, C_ADDR_WIDTH) + spra_reg (.D(SPRA), .CLK(CLK), .CE(qspo_ce_int), .ACLR(1'b0), .ASET(1'b0), + .AINIT(1'b0), .SCLR(1'b0), .SSET(1'b0), .SINIT(1'b0), + .Q(spra_int1)); + + C_REG_FD_V4_0 #("0", C_ENABLE_RLOCS, 0, 0, 0, + 1, 0, 0, 0, + "0", 0, 0, 1) + we_reg (.D(WE), .CLK(CLK), .CE(wece), .ACLR(1'b0), .ASET(1'b0), + .AINIT(1'b0), .SCLR(1'b0), .SSET(1'b0), .SINIT(1'b0), + .Q(we_int1)); + + C_REG_FD_V4_0 #("0", C_ENABLE_RLOCS, 0, 0, 0, + 0, 0, 0, 0, + "0", 0, 0, 1) + re_reg (.D(RD_EN), .CLK(CLK),// .CE(qspo_ce_int), + .CE(1'b0), .ACLR(1'b0), .ASET(1'b0), + .AINIT(1'b0), .SCLR(1'b0), .SSET(1'b0), .SINIT(1'b0), + .Q(re_int1)); + + C_REG_FD_V4_0 #("0", C_ENABLE_RLOCS, 0, 0, 0, + 1, 0, 0, 0, + "0", 0, 0, C_WIDTH) + d_reg (.D(D), .CLK(CLK), .CE(ice), .ACLR(1'b0), .ASET(1'b0), + .AINIT(1'b0), .SCLR(1'b0), .SSET(1'b0), .SINIT(1'b0), + .Q(d_int1)); + + C_REG_FD_V4_0 #("0", C_ENABLE_RLOCS, 0, 0, 0, + 0, 0, 0, 0, + "0", 0, 0, C_WIDTH) + spo_reg1 (.D(spo_async), .CLK(CLK), .CE(1'b0), .ACLR(1'b0), .ASET(1'b0), + .AINIT(1'b0), .SCLR(1'b0), .SSET(1'b0), .SINIT(1'b0), + .Q(spo_reg_tmp)); + + C_REG_FD_V4_0 #("0", C_ENABLE_RLOCS, 0, 0, 0, + 0, 0, 0, 0, + "0", 0, 0, C_WIDTH) + dpo_reg1 (.D(dpo_async), .CLK(doclk), .CE(1'b0), .ACLR(1'b0), .ASET(1'b0), + .AINIT(1'b0), .SCLR(1'b0), .SSET(1'b0), .SINIT(1'b0), + .Q(dpo_reg_tmp)); + + // Deal with these optional registers + assign qspo_ce_reg = (C_REG_A_D_INPUTS == 0 ? (C_HAS_QSPO_CE == 1 ? qspo_ce_int : 1'b1) : (C_HAS_QSPO_CE == 1 ? qspo_ce_reg1 : 1'b1)); + assign a_int = (C_REG_A_D_INPUTS == 0 ? (C_MEM_TYPE != `c_srl16 ? A : (C_ADDR_WIDTH>4 ? A[C_ADDR_WIDTH - 1 -(C_ADDR_WIDTH>4?(4*C_HAS_SPRA):0) : 0]<<4 : 0)) : + (C_MEM_TYPE != `c_srl16 ? a_int1 : (C_ADDR_WIDTH>4 ? a_int1[C_ADDR_WIDTH - 1 -(C_ADDR_WIDTH>4?(4*C_HAS_SPRA):0) : 0]<<4 : 0))); + assign spra_int = (C_REG_A_D_INPUTS == 0 ? (C_MEM_TYPE != `c_srl16 ? A : SPRA) : + (C_MEM_TYPE != `c_srl16 ? a_int1 : spra_int1)); + assign we_int = (C_REG_A_D_INPUTS == 0 ? (C_HAS_WE == 1 ? WE : 1'b1) : (C_HAS_WE == 1 ? we_int1 : 1'b1)); + assign re_int = (C_REG_A_D_INPUTS == 0 ? (C_HAS_RD_EN == 1 ? RD_EN : 1'b1) : (C_HAS_RD_EN == 1 ? re_int1 : 1'b1)); + assign d_int = (C_REG_A_D_INPUTS == 0 ? (C_HAS_D == 1 ? D : `allXs) : (C_HAS_D == 1 ? d_int1 : `allXs)); + assign spo_reg = (pipe_stages == 1 ? spo_reg_tmp : spo_async); + assign dpo_reg = (pipe_stages == 1 ? dpo_reg_tmp : dpo_async); + + // (Optional) DP Read Address and QDPO_CE registers + + C_REG_FD_V4_0 #("0", C_ENABLE_RLOCS, 0, 0, 0, + 1, 0, 0, 0, + "0", 0, 0, C_ADDR_WIDTH) + dpra_reg (.D(DPRA), .CLK(doclk), .CE(qdpo_ce_int), .ACLR(1'b0), .ASET(1'b0), + .AINIT(1'b0), .SCLR(1'b0), .SSET(1'b0), .SINIT(1'b0), + .Q(dpra_int1)); + + C_REG_FD_V4_0 #("0", C_ENABLE_RLOCS, 0, 0, 0, + 0, 0, 0, 0, + "0", 0, 0, 1) + qdpo1_reg (.D(qdpo_ce_int), .CLK(doclk), .CE(1'b0), .ACLR(1'b0), .ASET(1'b0), + .AINIT(1'b0), .SCLR(1'b0), .SSET(1'b0), .SINIT(1'b0), + .Q(qdpo_ce_reg1)); + + // Deal with these optional registers + assign qdpo_ce_reg = (C_REG_DPRA_INPUT == 0 ? (C_HAS_QDPO_CE == 1 ? qdpo_ce_int : (C_QCE_JOINED == 1 ? qdpo_ce_int : 1'b1)) : + (C_HAS_QDPO_CE == 1 ? qdpo_ce_reg1 : (C_QCE_JOINED == 1 || C_MEM_TYPE == `c_srl16 ? qdpo_ce_reg1 : 1'b1))); + assign dpra_int = (C_REG_DPRA_INPUT == 0 ? (C_HAS_DPRA == 1 ? DPRA : `allXs) : (C_HAS_DPRA == 1 ? dpra_int1 : `allXs)); + + // (Optional) pipeline registers + + always@(posedge CLK) + begin + if(CLK === 1'b1 && lastCLK === 1'b0 && qspo_ce_reg === 1'b1) // OK! Update pipelines! + begin + for(pipe = 2; pipe <= pipe_stages-1; pipe = pipe + 1) + begin + spo_pipe[pipe] <= spo_pipe[pipe+1]; + end + spo_pipe[pipe_stages] <= spo_async; + end + else if((CLK === 1'bx && lastCLK === 1'b0) || (CLK === 1'b1 && lastCLK === 1'bx) || qspo_ce_reg === 1'bx) // POSSIBLY Update pipelines! + begin + for(pipe = 2; pipe <= pipe_stages-1; pipe = pipe + 1) + begin + tmp_pipe1 = spo_pipe[pipe]; + tmp_pipe2 = spo_pipe[pipe+1]; + for(pipe1 = 0; pipe1 < C_WIDTH; pipe1 = pipe1 + 1) + begin + if(tmp_pipe1[pipe1] !== tmp_pipe2[pipe1]) + tmp_pipe1[pipe1] = 1'bx; + end + spo_pipe[pipe] <= tmp_pipe1; + end + tmp_pipe1 = spo_pipe[pipe_stages]; + for(pipe1 = 0; pipe1 < C_WIDTH; pipe1 = pipe1 + 1) + begin + if(tmp_pipe1[pipe1] !== spo_async[pipe1]) + tmp_pipe1[pipe1] = 1'bx; + end + spo_pipe[pipe_stages] <= tmp_pipe1; + end + end + + always@(spo_async or spo_pipe[2]) + begin + if(pipe_stages < 2) // No pipeline + spo_pipeend <= spo_async; + else // Pipeline stages required + begin + spo_pipeend <= spo_pipe[2]; + end + end + + always@(posedge doclk) + begin + if(doclk === 1'b1 && lastdoclk === 1'b0 && qdpo_ce_reg === 1'b1) // OK! Update pipelines! + begin + for(pipe3 = 2; pipe3 <= dpo_pipe_stages-1; pipe3 = pipe3 + 1) + begin + dpo_pipe[pipe3] <= dpo_pipe[pipe3+1]; + end + dpo_pipe[dpo_pipe_stages] <= dpo_async; + end + else if((doclk === 1'bx && lastdoclk === 1'b0) || (doclk === 1'b1 && lastdoclk === 1'bx) || qdpo_ce_reg === 1'bx) // POSSIBLY Update pipelines! + begin + for(pipe4 = 2; pipe4 <= dpo_pipe_stages-1; pipe4 = pipe4 + 1) + begin + tmp_pipe3 = dpo_pipe[pipe4]; + tmp_pipe2 = dpo_pipe[pipe4+1]; + for(pipe1 = 0; pipe1 < C_WIDTH; pipe1 = pipe1 + 1) + begin + if(tmp_pipe3[pipe1] !== tmp_pipe2[pipe1]) + tmp_pipe3[pipe1] = 1'bx; + end + dpo_pipe[pipe4] <= tmp_pipe3; + end + tmp_pipe3 = dpo_pipe[dpo_pipe_stages]; + for(pipe2 = 0; pipe2 < C_WIDTH; pipe2 = pipe2 + 1) + begin + if(tmp_pipe3[pipe2] !== dpo_async[pipe2]) + tmp_pipe3[pipe2] = 1'bx; + end + dpo_pipe[dpo_pipe_stages] <= tmp_pipe3; + end + end + + always@(dpo_async or dpo_pipe[2]) + begin + if(dpo_pipe_stages < 2) // No pipeline + dpo_pipeend <= dpo_async; + else // Pipeline stages required + begin + dpo_pipeend <= dpo_pipe[2]; + end + end + + // (Optional) output registers at end of optional pipelines + + C_REG_FD_V4_0 #("0", C_ENABLE_RLOCS, C_HAS_QSPO_RST, 0, 0, + 1, C_HAS_QSPO_SRST, 0, 0, + "0", C_SYNC_ENABLE, 0, C_WIDTH) + qspo_reg (.D(spo_pipeend), .CLK(CLK), .CE(qspo_ce_reg), .ASET(1'b0), + .AINIT(1'b0), .SSET(1'b0), .SINIT(1'b0), + .ACLR(qspo_rst_int), .SCLR(qspo_srst_int), .Q(intQSPO)); + + C_REG_FD_V4_0 #("0", C_ENABLE_RLOCS, C_HAS_QDPO_RST, 0, 0, + 1, C_HAS_QDPO_SRST, 0, 0, + "0", C_SYNC_ENABLE, 0, C_WIDTH) + qdpo_reg (.D(dpo_pipeend), .CLK(doclk), .CE(qdpo_ce_reg), .ASET(1'b0), + .AINIT(1'b0), .SSET(1'b0), .SINIT(1'b0), + .ACLR(qdpo_rst_int), .SCLR(qdpo_srst_int), .Q(intQDPO)); + + + + // Startup behaviour + initial + begin + default_data = 'b0; + case (radix) + 3 : default_data = decstr_conv(C_DEFAULT_DATA); + 2 : default_data = binstr_conv(C_DEFAULT_DATA); + 1 : default_data = hexstr_conv(C_DEFAULT_DATA); + default : $display("ERROR in %m at %d ns: BAD DATA RADIX - valid range 1 to 3", $time); + endcase + + for(i = 0; i < C_DEPTH; i = i + 1) + ram_data[i] = default_data; + + if(C_READ_MIF == 1) + begin + $readmemb(C_MEM_INIT_FILE, ram_data); + end + if (C_GENERATE_MIF == 1) + write_meminit_file; + + spo_tmp = 'b0; + dpo_tmp = 'b0; + lastCLK = 1'b0; + lastdoclk = 1'b0; + + for(i = 0; i < pipe_stages+3; i = i + 1) + begin + spo_pipe[i] = `all0s; + end + for(i = 0; i < dpo_pipe_stages+3; i = i + 1) + begin + dpo_pipe[i] = `all0s; + end + if(pipe_stages < 2) // No pipeline + begin + spo_pipeend = spo_async; + end + else + begin + spo_pipeend = spo_pipe[2]; + end + if(dpo_pipe_stages < 2) // No pipeline + begin + dpo_pipeend = dpo_async; + end + else + begin + dpo_pipeend = dpo_pipe[2]; + end + end + + always @(CLK) + lastCLK <= CLK; + + always @(doclk) + lastdoclk <= doclk; + + always @(posedge CLK or a_int or we_int or spra_int or dpra_int or d_int or re_int) + begin + if(((CLK === 1'b1 && lastCLK === 1'b0) || C_HAS_CLK == 0) && C_MEM_TYPE != `c_rom) + begin + if(ADDR_IS_X(a_int) || a_int < C_DEPTH) + begin + if(we_int === 1'bx) + begin + if(ADDR_IS_X(a_int)) + begin + for(i = 0; i < C_DEPTH; i = i + 1) + ram_data[i] = `allXs; + end + else + begin + if(C_MEM_TYPE == `c_srl16) + begin + srl_start = (a_int/16)*16; // Ignore lower 4 bits of a_int + srl_end = srl_start+16; + if(srl_end > C_DEPTH) + srl_end = C_DEPTH; + for(i = srl_end-1; i > srl_start; i = i - 1) + begin // Shift data through the SRL16s + tmp_data1 = ram_data[i]; + tmp_data2 = ram_data[i-1]; + for(j = 0; j < C_WIDTH; j = j + 1) + begin + if(tmp_data1[j] !== tmp_data2[j]) + tmp_data1[j] = 1'bx; + end + ram_data[i] = tmp_data1; + end + tmp_data1 = ram_data[srl_start]; + for(j = 0; j < C_WIDTH; j = j + 1) + begin + if(tmp_data1[j] !== d_int[j]) + tmp_data1[j] = 1'bx; + end + ram_data[srl_start] = tmp_data1; + end + else + begin + tmp_data1 = ram_data[a_int]; + for(j = 0; j < C_WIDTH; j = j + 1) + begin + if(tmp_data1[j] !== d_int[j]) + tmp_data1[j] = 1'bx; + end + ram_data[a_int] = tmp_data1; + end + end + end + else if(we_int === 1'b1) + begin + if(ADDR_IS_X(a_int)) + begin + for(i = 0; i < C_DEPTH; i = i + 1) + ram_data[i] = `allXs; + end + else + begin + if(C_MEM_TYPE == `c_srl16) + begin + srl_start = (a_int/16)*16; // Ignore lower 4 bits of a_int + srl_end = srl_start+16; + if(srl_end > C_DEPTH) + srl_end = C_DEPTH; + for(i = srl_end-1; i > srl_start; i = i - 1) + begin // Shift data through the SRL16s + ram_data[i] = ram_data[i-1]; + end + ram_data[srl_start] = d_int; + end + else + begin + //if (C_MEM_TYPE == `c_dp_ram && a_int == dpra_int && we_int == 1 && qspo_ce_int == 1) + //begin + // $display("WARNING in %m at time %d ns: Memory Hazard: Reading and Writing to same dual port address!", $time); + //end + ram_data[a_int] = d_int; + end + end + end + end + else if(a_int >= C_DEPTH) + $display("WARNING in %m at time %d ns: Writing to out-of-range address!! - max address is %d", $time, C_DEPTH); + end + else if((C_HAS_CLK == 0 || ((CLK === 1'bx && lastCLK === 1'b0) || CLK === 1'b1 && lastCLK === 1'bx)) && C_MEM_TYPE != `c_rom) + begin + if(ADDR_IS_X(a_int) || a_int < C_DEPTH) + begin + if(we_int === 1'bx) + begin + if(ADDR_IS_X(a_int)) + begin + for(i = 0; i < C_DEPTH; i = i + 1) + ram_data[i] = `allXs; + end + else + begin + if(C_MEM_TYPE == `c_srl16) + begin + srl_start = (a_int/16)*16; // Ignore lower 4 bits of a_int + srl_end = srl_start+16; + if(srl_end > C_DEPTH) + srl_end = C_DEPTH; + for(i = srl_end-1; i > srl_start; i = i - 1) + begin // Shift data through the SRL16s + tmp_data1 = ram_data[i]; + tmp_data2 = ram_data[i-1]; + for(j = 0; j < C_WIDTH; j = j + 1) + begin + if(tmp_data1[j] !== tmp_data2[j]) + tmp_data1[j] = 1'bx; + end + ram_data[i] = tmp_data1; + end + tmp_data1 = ram_data[srl_start]; + for(j = 0; j < C_WIDTH; j = j + 1) + begin + if(tmp_data1[j] !== d_int[j]) + tmp_data1[j] = 1'bx; + end + ram_data[srl_start] = tmp_data1; + end + else + begin + tmp_data1 = ram_data[a_int]; + for(j = 0; j < C_WIDTH; j = j + 1) + begin + if(tmp_data1[j] !== d_int[j]) + tmp_data1[j] = 1'bx; + end + ram_data[a_int] = tmp_data1; + end + end + end + else if(we_int === 1'b1) + begin + if(ADDR_IS_X(a_int)) + begin + for(i = 0; i < C_DEPTH; i = i + 1) + ram_data[i] = `allXs; + end + else + begin + if(C_MEM_TYPE == `c_srl16) + begin + srl_start = (a_int/16)*16; // Ignore lower 4 bits of a_int + srl_end = srl_start+16; + if(srl_end > C_DEPTH) + srl_end = C_DEPTH; + for(i = srl_end-1; i > srl_start; i = i - 1) + begin // Shift data through the SRL16s + tmp_data1 = ram_data[i]; + tmp_data2 = ram_data[i-1]; + for(j = 0; j < C_WIDTH; j = j + 1) + begin + if(tmp_data1[j] !== tmp_data2[j]) + tmp_data1[j] = 1'bx; + end + ram_data[i] = tmp_data1; + end + tmp_data1 = ram_data[srl_start]; + for(j = 0; j < C_WIDTH; j = j + 1) + begin + if(tmp_data1[j] !== d_int[j]) + tmp_data1[j] = 1'bx; + end + ram_data[srl_start] = tmp_data1; + end + else + begin + //if (C_MEM_TYPE == `c_dp_ram && a_int == dpra_int && we_int == 1 && qspo_ce_int == 1) + //begin + // $display("WARNING in %m at time %d ns: Memory Hazard: Reading and Writing to same dual port address!", $time); + //end + tmp_data1 = ram_data[a_int]; + for(j = 0; j < C_WIDTH; j = j + 1) + begin + if(tmp_data1[j] !== d_int[j]) + tmp_data1[j] = 1'bx; + end + ram_data[a_int] = tmp_data1; + end + end + end + end + else if(a_int >= C_DEPTH) + $display("WARNING in %m at time %d ns: Writing to out-of-range address!! - max address is %d", $time, C_DEPTH); + end + + // Read behaviour + + if(re_int === 1'bx) + begin + spo_tmp = `allXs; + dpo_tmp = `allXs; + end + else if(re_int === 1'b1) + begin + if(ADDR_IS_X(spra_int)) + spo_tmp = `allXs; + else + begin + if(spra_int < C_DEPTH) + spo_tmp = ram_data[spra_int]; + else if(C_MUX_TYPE == `c_buft_based) + begin + $display("WARNING in %m at time %d ns: Reading from out-of-range address!! - max address is %d", $time, C_DEPTH); + spo_tmp = `allZs; + end + else + begin + $display("WARNING in %m at time %d ns: Reading from out-of-range address!! - max address is %d", $time, C_DEPTH); + spo_tmp = `all0s; + end + end + + if(ADDR_IS_X(dpra_int)) + dpo_tmp = `allXs; + else + begin + if(dpra_int < C_DEPTH) + dpo_tmp = ram_data[dpra_int]; + else if(C_MUX_TYPE == `c_buft_based) + begin + $display("WARNING in %m at time %d ns: Reading from out-of-range address!! - max address is %d", $time, C_DEPTH); + dpo_tmp = `allZs; + end + else + begin + $display("WARNING in %m at time %d ns: Reading from out-of-range address!! - max address is %d", $time, C_DEPTH); + dpo_tmp = `all0s; + end + end + end + else // re_int == 0 + begin + spo_tmp = `allZs; + dpo_tmp = `allZs; + end + + spo_async <= spo_tmp; + dpo_async <= dpo_tmp; + + end + + + function [C_WIDTH-1:0] binstr_conv; + input [(C_WIDTH*8)-1:0] def_data; + + integer index,i; + + begin + index = 0; + binstr_conv = 'b0; + + for( i=C_WIDTH-1; i>=0; i=i-1 ) + begin + case (def_data[7:0]) + 8'b00000000 : i = -1; + 8'b00110000 : binstr_conv[index] = 1'b0; + 8'b00110001 : binstr_conv[index] = 1'b1; + default : + begin + $display("ERROR in %m at time %d ns: NOT A BINARY CHARACTER", $time); + binstr_conv[index] = 1'bx; + end + endcase + index = index + 1; + def_data = def_data >> 8; + end + end + endfunction + + function [C_WIDTH-1:0] hexstr_conv; + input [(C_WIDTH*8)-1:0] def_data; + + integer index,i,j; + reg [3:0] bin; + + begin + index = 0; + hexstr_conv = 'b0; + for( i=C_WIDTH-1; i>=0; i=i-1 ) + begin + case (def_data[7:0]) + 8'b00000000 : + begin + bin = 4'b0000; + i = -1; + end + 8'b00110000 : bin = 4'b0000; + 8'b00110001 : bin = 4'b0001; + 8'b00110010 : bin = 4'b0010; + 8'b00110011 : bin = 4'b0011; + 8'b00110100 : bin = 4'b0100; + 8'b00110101 : bin = 4'b0101; + 8'b00110110 : bin = 4'b0110; + 8'b00110111 : bin = 4'b0111; + 8'b00111000 : bin = 4'b1000; + 8'b00111001 : bin = 4'b1001; + 8'b01000001 : bin = 4'b1010; + 8'b01000010 : bin = 4'b1011; + 8'b01000011 : bin = 4'b1100; + 8'b01000100 : bin = 4'b1101; + 8'b01000101 : bin = 4'b1110; + 8'b01000110 : bin = 4'b1111; + 8'b01100001 : bin = 4'b1010; + 8'b01100010 : bin = 4'b1011; + 8'b01100011 : bin = 4'b1100; + 8'b01100100 : bin = 4'b1101; + 8'b01100101 : bin = 4'b1110; + 8'b01100110 : bin = 4'b1111; + default : + begin + $display("ERROR in %m at time %d ns: NOT A HEX CHARACTER", $time); + bin = 4'bx; + end + endcase + for( j=0; j<4; j=j+1) + begin + if ((index*4)+j < C_WIDTH) + begin + hexstr_conv[(index*4)+j] = bin[j]; + end + end + index = index + 1; + def_data = def_data >> 8; + end + end + endfunction + + function [C_WIDTH-1:0] decstr_conv; + input [(C_WIDTH*8)-1:0] def_data; + + integer index,i,j; + reg [3:0] bin; + + begin + index = 0; + decstr_conv = 'b0; + for( i=C_WIDTH-1; i>=0; i=i-1 ) + begin + case (def_data[7:0]) + 8'b00000000 : + begin + bin = 4'b0000; + i = -1; + end + 8'b00110000 : bin = 4'b0000; + 8'b00110001 : bin = 4'b0001; + 8'b00110010 : bin = 4'b0010; + 8'b00110011 : bin = 4'b0011; + 8'b00110100 : bin = 4'b0100; + 8'b00110101 : bin = 4'b0101; + 8'b00110110 : bin = 4'b0110; + 8'b00110111 : bin = 4'b0111; + 8'b00111000 : bin = 4'b1000; + 8'b00111001 : bin = 4'b1001; + 8'b01000001 : bin = 4'b1010; + 8'b01000010 : bin = 4'b1011; + 8'b01000011 : bin = 4'b1100; + 8'b01000100 : bin = 4'b1101; + 8'b01000101 : bin = 4'b1110; + 8'b01000110 : bin = 4'b1111; + default : + begin + $display("ERROR in %m at time %d ns: NOT A DECIMAL CHARACTER", $time); + bin = 4'bx; + end + endcase + for( j=0; j<4; j=j+1) + begin + if ((index*4)+j < C_WIDTH) + begin + decstr_conv[(index*4)+j] = bin[j]; + end + end + index = index + 1; + def_data = def_data >> 8; + end + end + endfunction + + task write_meminit_file; + + integer addrs, outfile, bit_index; + + reg [C_WIDTH-1 : 0] conts; + reg anyX; + + begin + outfile = $fopen(C_MEM_INIT_FILE); + for( addrs = 0; addrs < C_DEPTH; addrs=addrs+1) + begin + anyX = 1'b0; + conts = ram_data[addrs]; + for(bit_index = 0; bit_index < C_WIDTH; bit_index=bit_index+1) + if(conts[bit_index] === 1'bx) anyX = 1'b1; + if(anyX == 1'b1) + $display("ERROR in %m at time %d ns: MEMORY CONTAINS UNKNOWNS", $time); + $fdisplay(outfile,"%b",ram_data[addrs]); + end + $fclose(outfile); + end + endtask + +endmodule + +`undef all0s +`undef all1s +`undef allXs +`undef allZs +`undef addrallXs + +`undef c_rom +`undef c_sp_ram +`undef c_dp_ram +`undef c_srl16 + +`undef c_lut_based +`undef c_buft_based + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/C_DIST_MEM_V6_0.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/C_DIST_MEM_V6_0.v new file mode 100644 index 0000000..52140e9 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/C_DIST_MEM_V6_0.v @@ -0,0 +1,903 @@ +// Copyright(C) 2002 by Xilinx, Inc. All rights reserved. +// This text contains proprietary, confidential +// information of Xilinx, Inc., is distributed +// under license from Xilinx, Inc., and may be used, +// copied and/or disclosed only pursuant to the terms +// of a valid license agreement with Xilinx, Inc. This copyright +// notice must be retained as part of this text at all times. + + +/* $Id: C_DIST_MEM_V6_0.v,v 1.17 2008/09/08 20:06:51 akennedy Exp $ +-- +-- Filename - C_DIST_MEM_V6_0.v +-- Author - Xilinx +-- Creation - 24 Mar 1999 +-- +-- Description +-- Distributed RAM Simulation Model +*/ + + +`timescale 1ns/10ps +`define all0s 'b0 +`define all1s {C_WIDTH{1'b1}} +`define allXs {C_WIDTH{1'bx}} +`define allZs {C_WIDTH{1'bz}} +`define addrallXs {C_ADDR_WIDTH{1'bx}} + +`define c_rom 0 +`define c_sp_ram 1 +`define c_dp_ram 2 +`define c_srl16 3 + +`define c_lut_based 0 +`define c_buft_based 1 + +module C_DIST_MEM_V6_0 (A, D, DPRA, SPRA, CLK, WE, I_CE, RD_EN, QSPO_CE, QDPO_CE, QDPO_CLK, QSPO_RST, QDPO_RST, QSPO_SRST, QDPO_SRST, SPO, DPO, QSPO, QDPO); + + parameter C_ADDR_WIDTH = 6; + parameter C_DEFAULT_DATA = "0"; + parameter C_DEFAULT_DATA_RADIX = 1; + parameter C_DEPTH = 64; + parameter C_ENABLE_RLOCS = 1; + parameter C_GENERATE_MIF = 0; + parameter C_HAS_CLK = 1; + parameter C_HAS_D = 1; + parameter C_HAS_DPO = 0; + parameter C_HAS_DPRA = 0; + parameter C_HAS_I_CE = 0; + parameter C_HAS_QDPO = 0; + parameter C_HAS_QDPO_CE = 0; + parameter C_HAS_QDPO_CLK = 0; + parameter C_HAS_QDPO_RST = 0; // RSTB + parameter C_HAS_QDPO_SRST = 0; + parameter C_HAS_QSPO = 0; + parameter C_HAS_QSPO_CE = 0; + parameter C_HAS_QSPO_RST = 0; // RSTA + parameter C_HAS_QSPO_SRST = 0; + parameter C_HAS_RD_EN = 0; + parameter C_HAS_SPO = 1; + parameter C_HAS_SPRA = 0; + parameter C_HAS_WE = 1; + parameter C_LATENCY = 0; + parameter C_MEM_INIT_FILE = "null.mif"; + parameter C_MEM_TYPE = 1; // c_sp_ram + parameter C_MUX_TYPE = 0; // c_lut_based + parameter C_QCE_JOINED = 0; + parameter C_QUALIFY_WE = 0; + parameter C_READ_MIF = 0; + parameter C_REG_A_D_INPUTS = 0; + parameter C_REG_DPRA_INPUT = 0; + parameter C_SYNC_ENABLE = 0; + parameter C_WIDTH = 16; + parameter radix = C_DEFAULT_DATA_RADIX; + parameter pipe_stages = C_LATENCY-C_REG_A_D_INPUTS; + parameter dpo_pipe_stages = pipe_stages+C_HAS_QDPO-C_HAS_QSPO; + parameter C_RAM32_FIX = 0; // should not be passed in to simulation model + + parameter NCELAB_DPO_PIPE_CONSTANT = (dpo_pipe_stages < 2 ? 0 : 2); + parameter NCELAB_SPO_PIPE_CONSTANT = (pipe_stages < 2 ? 0 : 2); + + input [C_ADDR_WIDTH-1 - (C_ADDR_WIDTH>4?(4*C_HAS_SPRA):0) : 0] A; + input [C_WIDTH-1 : 0] D; + input [C_ADDR_WIDTH-1 : 0] DPRA; + input [C_ADDR_WIDTH-1 : 0] SPRA; + input CLK; + input WE; + input I_CE; + input RD_EN; + input QSPO_CE; + input QDPO_CE; + input QDPO_CLK; + input QSPO_RST; + input QDPO_RST; + input QSPO_SRST; + input QDPO_SRST; + output [C_WIDTH-1 : 0] SPO; + output [C_WIDTH-1 : 0] QSPO; + output [C_WIDTH-1 : 0] DPO; + output [C_WIDTH-1 : 0] QDPO; + + // Address signal connected to memory + wire [C_ADDR_WIDTH - 1 : 0] a_int; + // Read Address signal connected to srl16-based memory + wire [C_ADDR_WIDTH - 1 : 0] spra_int; + // Registered Address signal connected to memory + wire [C_ADDR_WIDTH - 1 : 0] a_int1; + // Registered Read Address signal connected to srl16-based memory + wire [C_ADDR_WIDTH - 1 : 0] spra_int1; + // DP port address signal connected to memory + wire [C_ADDR_WIDTH - 1 : 0] dpra_int; + // DP port address signal connected to memory + wire [C_ADDR_WIDTH - 1 : 0] dpra_int1; + // Input data signal connected to memory + wire [C_WIDTH - 1 : 0] d_int; + // Registered Input data signal connected to memory + wire [C_WIDTH - 1 : 0] d_int1; + // DP output register clock + wire doclk; + // Input data/address/WE register Clock Enable + wire ice; + // Special address register Clock Enable for ROMs + wire a_reg_ice; + // DP read address port register clock enable +// wire dpra_ce; + // WE wire connected to memory + wire we_int; + // Registered WE wire connected to memory + wire we_int1; + // Clock enable for the WE register + wire wece; + // Read Enable wire connected to BUFT-type output mux + wire re_int; + // Registered Read Enable wire connected to BUFT-type output mux + wire re_int1; + // unregistered version of qspo_ce + wire qspo_ce_int; + // possibly registered version of qspo_ce + wire qspo_ce_reg; + // registered version of qspo_ce + wire qspo_ce_reg1; + // unregistered version of qdpo_ce + wire qdpo_ce_int; + // possibly registered version of qdpo_ce + wire qdpo_ce_reg; + // registered version of qdpo_ce + wire qdpo_ce_reg1; + // possibly single port registered output reset + wire qspo_rst_int; + // possibly dual port registered output reset + wire qdpo_rst_int; + // possibly single port registered output sync reset + wire qspo_srst_int; + // possibly dual port registered output sync reset + wire qdpo_srst_int; + // Direct SP output from memory + reg [C_WIDTH - 1 : 0] spo_async; + // Direct DP output from memory + reg [C_WIDTH - 1 : 0] dpo_async; + // Possibly pipelined and/or registered SP output from memory + wire [C_WIDTH - 1 : 0] intQSPO; + // Possibly pipelined and/or registered DP output from memory + wire [C_WIDTH - 1 : 0] intQDPO; + // Pipeline signals + reg [C_WIDTH - 1 : 0] spo_pipe [pipe_stages+2 : 0]; + reg [C_WIDTH - 1 : 0] dpo_pipe [dpo_pipe_stages+2 : 0]; + // Possibly pipelined SP output from memory + reg [C_WIDTH - 1 : 0] spo_pipeend; + // Possibly pipelined DP output from memory + reg [C_WIDTH - 1 : 0] dpo_pipeend; + // BUFT outputs + wire [C_WIDTH - 1 : 0] spo_reg; + wire [C_WIDTH - 1 : 0] dpo_reg; + wire [C_WIDTH - 1 : 0] spo_reg_tmp; + wire [C_WIDTH - 1 : 0] dpo_reg_tmp; + + integer pipe, pipe1, pipe2, pipe3, pipe4, i, j, srl_start, srl_end; + + // Array to hold ram data + reg [C_WIDTH-1 : 0] ram_data [C_DEPTH-1 : 0]; + reg [C_WIDTH-1 : 0] tmp_data1; + reg [C_WIDTH-1 : 0] tmp_data2; + + reg [C_WIDTH-1 : 0] default_data; + reg [C_WIDTH-1 : 0] spo_tmp; + reg [C_WIDTH-1 : 0] dpo_tmp; + reg [C_WIDTH-1 : 0] tmp_pipe1; + reg [C_WIDTH-1 : 0] tmp_pipe2; + reg [C_WIDTH-1 : 0] tmp_pipe3; + reg lastCLK; + reg lastdoclk; + + function integer ADDR_IS_X; + input [C_ADDR_WIDTH-1 : 0] value; + integer i; + begin + ADDR_IS_X = 0; + for(i = 0; i < C_ADDR_WIDTH; i = i + 1) + if(value[i] === 1'bx) + ADDR_IS_X = 1; + end + endfunction + + // Deal with the optional output signals... + wire [C_WIDTH - 1 : 0] SPO = (C_HAS_SPO ? (C_MUX_TYPE == `c_lut_based ? spo_async : spo_reg) : `allXs); + wire [C_WIDTH - 1 : 0] DPO = (C_HAS_DPO && C_MEM_TYPE == `c_dp_ram ? (C_MUX_TYPE == `c_lut_based ? dpo_async : dpo_reg) : `allXs); + wire [C_WIDTH - 1 : 0] QSPO = (C_HAS_QSPO ? intQSPO : `allXs); + wire [C_WIDTH - 1 : 0] QDPO = (C_HAS_QDPO ? intQDPO : `allXs); + + // Deal with the optional input signals... + + assign ice = (C_HAS_I_CE == 1 ? I_CE : 1'b1); + assign a_reg_ice = (C_MEM_TYPE == `c_rom ? qspo_ce_int : ice); + assign wece = (C_HAS_WE == 1 && C_REG_A_D_INPUTS == 1 && C_QUALIFY_WE == 1 ? ice : 1'b1); +// assign dpra_ce = (C_HAS_QDPO_CE == 1 ? QDPO_CE : 1'b1); + assign doclk = (C_HAS_QDPO_CLK == 1 ? QDPO_CLK : CLK); + assign qspo_ce_int = (C_HAS_QSPO_CE == 1 ? QSPO_CE : 1'b1); + assign qdpo_ce_int = (C_QCE_JOINED == 1 ? qspo_ce_int : (C_HAS_QDPO_CE == 1 ? QDPO_CE : ((C_HAS_QSPO == 1 && C_MEM_TYPE == `c_srl16) ? qspo_ce_int : 1'b1))); + assign qspo_rst_int = (C_HAS_QSPO_RST && C_HAS_QSPO ? QSPO_RST : 1'b0); + assign qdpo_rst_int = (C_HAS_QDPO_RST && C_HAS_QDPO ? QDPO_RST : 1'b0); + assign qspo_srst_int = (C_HAS_QSPO_SRST && C_HAS_QSPO ? QSPO_SRST : 1'b0); + assign qdpo_srst_int = (C_HAS_QDPO_SRST && C_HAS_QDPO ? QDPO_SRST : 1'b0); + + // (Optional) registers on SP address and on optional data/we/qspo_ce signals + C_REG_FD_V6_0 #("0", C_ENABLE_RLOCS, 0, 0, 0, + 0, 0, 0, 0, + "0", 0, 0, 1) + qspo1_reg (.D(qspo_ce_int), .CLK(CLK), .CE(1'b0), .ACLR(1'b0), .ASET(1'b0), + .AINIT(1'b0), .SCLR(1'b0), .SSET(1'b0), .SINIT(1'b0), + .Q(qspo_ce_reg1)); + + C_REG_FD_V6_0 #("0", C_ENABLE_RLOCS, 0, 0, 0, + 1, 0, 0, 0, + "0", 0, 0, (C_ADDR_WIDTH-(C_ADDR_WIDTH>4?(C_HAS_SPRA*4):0))) + a_rega (.D(A[C_ADDR_WIDTH - 1-(C_ADDR_WIDTH>4?(4*C_HAS_SPRA):0) : 0]), .CLK(CLK), .CE(a_reg_ice), .ACLR(1'b0), .ASET(1'b0), + .AINIT(1'b0), .SCLR(1'b0), .SSET(1'b0), .SINIT(1'b0), + .Q(a_int1[C_ADDR_WIDTH - 1-(C_ADDR_WIDTH>4?(4*C_HAS_SPRA):0) : 0])); + + C_REG_FD_V6_0 #("0", C_ENABLE_RLOCS, 0, 0, 0, + 1, 0, 0, 0, + "0", 0, 0, C_ADDR_WIDTH) + spra_reg (.D(SPRA), .CLK(CLK), .CE(qspo_ce_int), .ACLR(1'b0), .ASET(1'b0), + .AINIT(1'b0), .SCLR(1'b0), .SSET(1'b0), .SINIT(1'b0), + .Q(spra_int1)); + + C_REG_FD_V6_0 #("0", C_ENABLE_RLOCS, 0, 0, 0, + 1, 0, 0, 0, + "0", 0, 0, 1) + we_reg (.D(WE), .CLK(CLK), .CE(wece), .ACLR(1'b0), .ASET(1'b0), + .AINIT(1'b0), .SCLR(1'b0), .SSET(1'b0), .SINIT(1'b0), + .Q(we_int1)); + + C_REG_FD_V6_0 #("0", C_ENABLE_RLOCS, 0, 0, 0, + 0, 0, 0, 0, + "0", 0, 0, 1) + re_reg (.D(RD_EN), .CLK(CLK),// .CE(qspo_ce_int), + .CE(1'b0), .ACLR(1'b0), .ASET(1'b0), + .AINIT(1'b0), .SCLR(1'b0), .SSET(1'b0), .SINIT(1'b0), + .Q(re_int1)); + + C_REG_FD_V6_0 #("0", C_ENABLE_RLOCS, 0, 0, 0, + 1, 0, 0, 0, + "0", 0, 0, C_WIDTH) + d_reg (.D(D), .CLK(CLK), .CE(ice), .ACLR(1'b0), .ASET(1'b0), + .AINIT(1'b0), .SCLR(1'b0), .SSET(1'b0), .SINIT(1'b0), + .Q(d_int1)); + + C_REG_FD_V6_0 #("0", C_ENABLE_RLOCS, 0, 0, 0, + 0, 0, 0, 0, + "0", 0, 0, C_WIDTH) + spo_reg1 (.D(spo_async), .CLK(CLK), .CE(1'b0), .ACLR(1'b0), .ASET(1'b0), + .AINIT(1'b0), .SCLR(1'b0), .SSET(1'b0), .SINIT(1'b0), + .Q(spo_reg_tmp)); + + C_REG_FD_V6_0 #("0", C_ENABLE_RLOCS, 0, 0, 0, + 0, 0, 0, 0, + "0", 0, 0, C_WIDTH) + dpo_reg1 (.D(dpo_async), .CLK(doclk), .CE(1'b0), .ACLR(1'b0), .ASET(1'b0), + .AINIT(1'b0), .SCLR(1'b0), .SSET(1'b0), .SINIT(1'b0), + .Q(dpo_reg_tmp)); + + // Deal with these optional registers + assign qspo_ce_reg = (C_REG_A_D_INPUTS == 0 ? (C_HAS_QSPO_CE == 1 ? qspo_ce_int : 1'b1) : (C_HAS_QSPO_CE == 1 ? qspo_ce_reg1 : 1'b1)); + assign a_int = (C_REG_A_D_INPUTS == 0 ? (C_MEM_TYPE != `c_srl16 ? A : (C_ADDR_WIDTH>4 ? A[C_ADDR_WIDTH - 1 -(C_ADDR_WIDTH>4?(4*C_HAS_SPRA):0) : 0]<<4 : 0)) : + (C_MEM_TYPE != `c_srl16 ? a_int1 : (C_ADDR_WIDTH>4 ? a_int1[C_ADDR_WIDTH - 1 -(C_ADDR_WIDTH>4?(4*C_HAS_SPRA):0) : 0]<<4 : 0))); + assign spra_int = (C_REG_A_D_INPUTS == 0 ? (C_MEM_TYPE != `c_srl16 ? A : SPRA) : + (C_MEM_TYPE != `c_srl16 ? a_int1 : spra_int1)); + assign we_int = (C_REG_A_D_INPUTS == 0 ? (C_HAS_WE == 1 ? WE : 1'b1) : (C_HAS_WE == 1 ? we_int1 : 1'b1)); + assign re_int = (C_REG_A_D_INPUTS == 0 ? (C_HAS_RD_EN == 1 ? RD_EN : 1'b1) : (C_HAS_RD_EN == 1 ? re_int1 : 1'b1)); + assign d_int = (C_REG_A_D_INPUTS == 0 ? (C_HAS_D == 1 ? D : `allXs) : (C_HAS_D == 1 ? d_int1 : `allXs)); + assign spo_reg = (pipe_stages == 1 ? spo_reg_tmp : spo_async); + assign dpo_reg = (pipe_stages == 1 ? dpo_reg_tmp : dpo_async); + + // (Optional) DP Read Address and QDPO_CE registers + + C_REG_FD_V6_0 #("0", C_ENABLE_RLOCS, 0, 0, 0, + 1, 0, 0, 0, + "0", 0, 0, C_ADDR_WIDTH) + dpra_reg (.D(DPRA), .CLK(doclk), .CE(qdpo_ce_int), .ACLR(1'b0), .ASET(1'b0), + .AINIT(1'b0), .SCLR(1'b0), .SSET(1'b0), .SINIT(1'b0), + .Q(dpra_int1)); + + C_REG_FD_V6_0 #("0", C_ENABLE_RLOCS, 0, 0, 0, + 0, 0, 0, 0, + "0", 0, 0, 1) + qdpo1_reg (.D(qdpo_ce_int), .CLK(doclk), .CE(1'b0), .ACLR(1'b0), .ASET(1'b0), + .AINIT(1'b0), .SCLR(1'b0), .SSET(1'b0), .SINIT(1'b0), + .Q(qdpo_ce_reg1)); + + // Deal with these optional registers + assign qdpo_ce_reg = (C_REG_DPRA_INPUT == 0 ? (C_HAS_QDPO_CE == 1 ? qdpo_ce_int : (C_QCE_JOINED == 1 ? qdpo_ce_int : 1'b1)) : + (C_HAS_QDPO_CE == 1 ? qdpo_ce_reg1 : (C_QCE_JOINED == 1 || C_MEM_TYPE == `c_srl16 ? qdpo_ce_reg1 : 1'b1))); + assign dpra_int = (C_REG_DPRA_INPUT == 0 ? (C_HAS_DPRA == 1 ? DPRA : `allXs) : (C_HAS_DPRA == 1 ? dpra_int1 : `allXs)); + + // (Optional) pipeline registers + + always@(posedge CLK) + begin + if(CLK === 1'b1 && lastCLK === 1'b0 && qspo_ce_reg === 1'b1) // OK! Update pipelines! + begin + for(pipe = 2; pipe <= pipe_stages-1; pipe = pipe + 1) + begin + spo_pipe[pipe] <= spo_pipe[pipe+1]; + end + spo_pipe[pipe_stages] <= spo_async; + end + else if((CLK === 1'bx && lastCLK === 1'b0) || (CLK === 1'b1 && lastCLK === 1'bx) || qspo_ce_reg === 1'bx) // POSSIBLY Update pipelines! + begin + for(pipe = 2; pipe <= pipe_stages-1; pipe = pipe + 1) + begin + tmp_pipe1 = spo_pipe[pipe]; + tmp_pipe2 = spo_pipe[pipe+1]; + for(pipe1 = 0; pipe1 < C_WIDTH; pipe1 = pipe1 + 1) + begin + if(tmp_pipe1[pipe1] !== tmp_pipe2[pipe1]) + tmp_pipe1[pipe1] = 1'bx; + end + spo_pipe[pipe] <= tmp_pipe1; + end + tmp_pipe1 = spo_pipe[pipe_stages]; + for(pipe1 = 0; pipe1 < C_WIDTH; pipe1 = pipe1 + 1) + begin + if(tmp_pipe1[pipe1] !== spo_async[pipe1]) + tmp_pipe1[pipe1] = 1'bx; + end + spo_pipe[pipe_stages] <= tmp_pipe1; + end + end + + always@(spo_async or spo_pipe[NCELAB_SPO_PIPE_CONSTANT]) //2 + begin + if(pipe_stages < 2) // No pipeline + spo_pipeend <= spo_async; + else // Pipeline stages required + begin + spo_pipeend <= spo_pipe[NCELAB_SPO_PIPE_CONSTANT]; //2 + end + end + + always@(posedge doclk) + begin + if(doclk === 1'b1 && lastdoclk === 1'b0 && qdpo_ce_reg === 1'b1) // OK! Update pipelines! + begin + for(pipe3 = 2; pipe3 <= dpo_pipe_stages-1; pipe3 = pipe3 + 1) + begin + dpo_pipe[pipe3] <= dpo_pipe[pipe3+1]; + end + dpo_pipe[dpo_pipe_stages] <= dpo_async; + end + else if((doclk === 1'bx && lastdoclk === 1'b0) || (doclk === 1'b1 && lastdoclk === 1'bx) || qdpo_ce_reg === 1'bx) // POSSIBLY Update pipelines! + begin + for(pipe4 = 2; pipe4 <= dpo_pipe_stages-1; pipe4 = pipe4 + 1) + begin + tmp_pipe3 = dpo_pipe[pipe4]; + tmp_pipe2 = dpo_pipe[pipe4+1]; + for(pipe1 = 0; pipe1 < C_WIDTH; pipe1 = pipe1 + 1) + begin + if(tmp_pipe3[pipe1] !== tmp_pipe2[pipe1]) + tmp_pipe3[pipe1] = 1'bx; + end + dpo_pipe[pipe4] <= tmp_pipe3; + end + tmp_pipe3 = dpo_pipe[dpo_pipe_stages]; + for(pipe2 = 0; pipe2 < C_WIDTH; pipe2 = pipe2 + 1) + begin + if(tmp_pipe3[pipe2] !== dpo_async[pipe2]) + tmp_pipe3[pipe2] = 1'bx; + end + dpo_pipe[dpo_pipe_stages] <= tmp_pipe3; + end + end + + always@(dpo_async or dpo_pipe[NCELAB_DPO_PIPE_CONSTANT]) //2 + begin + if(dpo_pipe_stages < 2) // No pipeline + dpo_pipeend <= dpo_async; + else // Pipeline stages required + begin + dpo_pipeend <= dpo_pipe[NCELAB_DPO_PIPE_CONSTANT]; //2 + end + end + + // (Optional) output registers at end of optional pipelines + + C_REG_FD_V6_0 #("0", C_ENABLE_RLOCS, C_HAS_QSPO_RST, 0, 0, + 1, C_HAS_QSPO_SRST, 0, 0, + "0", C_SYNC_ENABLE, 0, C_WIDTH) + qspo_reg (.D(spo_pipeend), .CLK(CLK), .CE(qspo_ce_reg), .ASET(1'b0), + .AINIT(1'b0), .SSET(1'b0), .SINIT(1'b0), + .ACLR(qspo_rst_int), .SCLR(qspo_srst_int), .Q(intQSPO)); + + C_REG_FD_V6_0 #("0", C_ENABLE_RLOCS, C_HAS_QDPO_RST, 0, 0, + 1, C_HAS_QDPO_SRST, 0, 0, + "0", C_SYNC_ENABLE, 0, C_WIDTH) + qdpo_reg (.D(dpo_pipeend), .CLK(doclk), .CE(qdpo_ce_reg), .ASET(1'b0), + .AINIT(1'b0), .SSET(1'b0), .SINIT(1'b0), + .ACLR(qdpo_rst_int), .SCLR(qdpo_srst_int), .Q(intQDPO)); + + + + // Startup behaviour + initial + begin + default_data = 'b0; + case (radix) + 3 : default_data = decstr_conv(C_DEFAULT_DATA); + 2 : default_data = binstr_conv(C_DEFAULT_DATA); + 1 : default_data = hexstr_conv(C_DEFAULT_DATA); + default : $display("ERROR in %m at %d ns: BAD DATA RADIX - valid range 1 to 3", $time); + endcase + + for(i = 0; i < C_DEPTH; i = i + 1) + ram_data[i] = default_data; + + if(C_READ_MIF == 1) + begin + $readmemb(C_MEM_INIT_FILE, ram_data, 0 , C_DEPTH-1); + end + if (C_GENERATE_MIF == 1) + write_meminit_file; + + spo_tmp = 'b0; + dpo_tmp = 'b0; + lastCLK = 1'b0; + lastdoclk = 1'b0; + + for(i = 0; i < pipe_stages+3; i = i + 1) + begin + spo_pipe[i] = `all0s; + end + for(i = 0; i < dpo_pipe_stages+3; i = i + 1) + begin + dpo_pipe[i] = `all0s; + end + if(pipe_stages < 2) // No pipeline + begin + spo_pipeend = spo_async; + end + else + begin + spo_pipeend = spo_pipe[NCELAB_SPO_PIPE_CONSTANT]; //2 + end + if(dpo_pipe_stages < 2) // No pipeline + begin + dpo_pipeend = dpo_async; + end + else + begin + dpo_pipeend = dpo_pipe[NCELAB_DPO_PIPE_CONSTANT]; //2 + end + end + + always @(CLK) + lastCLK <= CLK; + + always @(doclk) + lastdoclk <= doclk; + + always @(posedge CLK or a_int or we_int or spra_int or dpra_int or d_int or re_int) + begin + if(((CLK === 1'b1 && lastCLK === 1'b0) || C_HAS_CLK == 0) && C_MEM_TYPE != `c_rom) + begin + if(ADDR_IS_X(a_int) || a_int < C_DEPTH) + begin + if(we_int === 1'bx) + begin + if(ADDR_IS_X(a_int)) + begin + for(i = 0; i < C_DEPTH; i = i + 1) + ram_data[i] = `allXs; + end + else + begin + if(C_MEM_TYPE == `c_srl16) + begin + srl_start = (a_int/16)*16; // Ignore lower 4 bits of a_int + srl_end = srl_start+16; + if(srl_end > C_DEPTH) + srl_end = C_DEPTH; + for(i = srl_end-1; i > srl_start; i = i - 1) + begin // Shift data through the SRL16s + tmp_data1 = ram_data[i]; + tmp_data2 = ram_data[i-1]; + for(j = 0; j < C_WIDTH; j = j + 1) + begin + if(tmp_data1[j] !== tmp_data2[j]) + tmp_data1[j] = 1'bx; + end + ram_data[i] = tmp_data1; + end + tmp_data1 = ram_data[srl_start]; + for(j = 0; j < C_WIDTH; j = j + 1) + begin + if(tmp_data1[j] !== d_int[j]) + tmp_data1[j] = 1'bx; + end + ram_data[srl_start] = tmp_data1; + end + else + begin + tmp_data1 = ram_data[a_int]; + for(j = 0; j < C_WIDTH; j = j + 1) + begin + if(tmp_data1[j] !== d_int[j]) + tmp_data1[j] = 1'bx; + end + ram_data[a_int] = tmp_data1; + end + end + end + else if(we_int === 1'b1) + begin + if(ADDR_IS_X(a_int)) + begin + for(i = 0; i < C_DEPTH; i = i + 1) + ram_data[i] = `allXs; + end + else + begin + if(C_MEM_TYPE == `c_srl16) + begin + srl_start = (a_int/16)*16; // Ignore lower 4 bits of a_int + srl_end = srl_start+16; + if(srl_end > C_DEPTH) + srl_end = C_DEPTH; + for(i = srl_end-1; i > srl_start; i = i - 1) + begin // Shift data through the SRL16s + ram_data[i] = ram_data[i-1]; + end + ram_data[srl_start] = d_int; + end + else + begin + //if (C_MEM_TYPE == `c_dp_ram && a_int == dpra_int && we_int == 1 && qspo_ce_int == 1) + //begin + // $display("WARNING in %m at time %d ns: Memory Hazard: Reading and Writing to same dual port address!", $time); + //end + ram_data[a_int] = d_int; + end + end + end + end + else if(a_int >= C_DEPTH) + $display("WARNING in %m at time %d ns: Writing to out-of-range address!! - max address is %d", $time, C_DEPTH); + end + else if((C_HAS_CLK == 0 || ((CLK === 1'bx && lastCLK === 1'b0) || CLK === 1'b1 && lastCLK === 1'bx)) && C_MEM_TYPE != `c_rom) + begin + if(ADDR_IS_X(a_int) || a_int < C_DEPTH) + begin + if(we_int === 1'bx) + begin + if(ADDR_IS_X(a_int)) + begin + for(i = 0; i < C_DEPTH; i = i + 1) + ram_data[i] = `allXs; + end + else + begin + if(C_MEM_TYPE == `c_srl16) + begin + srl_start = (a_int/16)*16; // Ignore lower 4 bits of a_int + srl_end = srl_start+16; + if(srl_end > C_DEPTH) + srl_end = C_DEPTH; + for(i = srl_end-1; i > srl_start; i = i - 1) + begin // Shift data through the SRL16s + tmp_data1 = ram_data[i]; + tmp_data2 = ram_data[i-1]; + for(j = 0; j < C_WIDTH; j = j + 1) + begin + if(tmp_data1[j] !== tmp_data2[j]) + tmp_data1[j] = 1'bx; + end + ram_data[i] = tmp_data1; + end + tmp_data1 = ram_data[srl_start]; + for(j = 0; j < C_WIDTH; j = j + 1) + begin + if(tmp_data1[j] !== d_int[j]) + tmp_data1[j] = 1'bx; + end + ram_data[srl_start] = tmp_data1; + end + else + begin + tmp_data1 = ram_data[a_int]; + for(j = 0; j < C_WIDTH; j = j + 1) + begin + if(tmp_data1[j] !== d_int[j]) + tmp_data1[j] = 1'bx; + end + ram_data[a_int] = tmp_data1; + end + end + end + else if(we_int === 1'b1) + begin + if(ADDR_IS_X(a_int)) + begin + for(i = 0; i < C_DEPTH; i = i + 1) + ram_data[i] = `allXs; + end + else + begin + if(C_MEM_TYPE == `c_srl16) + begin + srl_start = (a_int/16)*16; // Ignore lower 4 bits of a_int + srl_end = srl_start+16; + if(srl_end > C_DEPTH) + srl_end = C_DEPTH; + for(i = srl_end-1; i > srl_start; i = i - 1) + begin // Shift data through the SRL16s + tmp_data1 = ram_data[i]; + tmp_data2 = ram_data[i-1]; + for(j = 0; j < C_WIDTH; j = j + 1) + begin + if(tmp_data1[j] !== tmp_data2[j]) + tmp_data1[j] = 1'bx; + end + ram_data[i] = tmp_data1; + end + tmp_data1 = ram_data[srl_start]; + for(j = 0; j < C_WIDTH; j = j + 1) + begin + if(tmp_data1[j] !== d_int[j]) + tmp_data1[j] = 1'bx; + end + ram_data[srl_start] = tmp_data1; + end + else + begin + //if (C_MEM_TYPE == `c_dp_ram && a_int == dpra_int && we_int == 1 && qspo_ce_int == 1) + //begin + // $display("WARNING in %m at time %d ns: Memory Hazard: Reading and Writing to same dual port address!", $time); + //end + tmp_data1 = ram_data[a_int]; + for(j = 0; j < C_WIDTH; j = j + 1) + begin + if(tmp_data1[j] !== d_int[j]) + tmp_data1[j] = 1'bx; + end + ram_data[a_int] = tmp_data1; + end + end + end + end + else if(a_int >= C_DEPTH) + $display("WARNING in %m at time %d ns: Writing to out-of-range address!! - max address is %d", $time, C_DEPTH); + end + + // Read behaviour + + if(re_int === 1'bx) + begin + spo_tmp = `allXs; + dpo_tmp = `allXs; + end + else if(re_int === 1'b1) + begin + if(ADDR_IS_X(spra_int)) + spo_tmp = `allXs; + else + begin + if(spra_int < C_DEPTH) + spo_tmp = ram_data[spra_int]; + else if(C_MUX_TYPE == `c_buft_based) + begin + $display("WARNING in %m at time %d ns: Reading from out-of-range address!! - max address is %d", $time, C_DEPTH); + spo_tmp = `allZs; + end + else + begin + $display("WARNING in %m at time %d ns: Reading from out-of-range address!! - max address is %d", $time, C_DEPTH); + spo_tmp = `all0s; + end + end + + if(ADDR_IS_X(dpra_int)) + dpo_tmp = `allXs; + else + begin + if(dpra_int < C_DEPTH) + dpo_tmp = ram_data[dpra_int]; + else if(C_MUX_TYPE == `c_buft_based) + begin + $display("WARNING in %m at time %d ns: Reading from out-of-range address!! - max address is %d", $time, C_DEPTH); + dpo_tmp = `allZs; + end + else + begin + $display("WARNING in %m at time %d ns: Reading from out-of-range address!! - max address is %d", $time, C_DEPTH); + dpo_tmp = `all0s; + end + end + end + else // re_int == 0 + begin + spo_tmp = `allZs; + dpo_tmp = `allZs; + end + + spo_async <= spo_tmp; + dpo_async <= dpo_tmp; + + end + + + function [C_WIDTH-1:0] binstr_conv; + input [(C_WIDTH*8)-1:0] def_data; + + integer index,i; + + begin + index = 0; + binstr_conv = 'b0; + + for( i=C_WIDTH-1; i>=0; i=i-1 ) + begin + case (def_data[7:0]) + 8'b00000000 : i = -1; + 8'b00110000 : binstr_conv[index] = 1'b0; + 8'b00110001 : binstr_conv[index] = 1'b1; + default : + begin + $display("ERROR in %m at time %d ns: NOT A BINARY CHARACTER", $time); + binstr_conv[index] = 1'bx; + end + endcase + index = index + 1; + def_data = def_data >> 8; + end + end + endfunction + + function [C_WIDTH-1:0] hexstr_conv; + input [(C_WIDTH*8)-1:0] def_data; + + integer index,i,j; + reg [3:0] bin; + + begin + index = 0; + hexstr_conv = 'b0; + for( i=C_WIDTH-1; i>=0; i=i-1 ) + begin + case (def_data[7:0]) + 8'b00000000 : + begin + bin = 4'b0000; + i = -1; + end + 8'b00110000 : bin = 4'b0000; + 8'b00110001 : bin = 4'b0001; + 8'b00110010 : bin = 4'b0010; + 8'b00110011 : bin = 4'b0011; + 8'b00110100 : bin = 4'b0100; + 8'b00110101 : bin = 4'b0101; + 8'b00110110 : bin = 4'b0110; + 8'b00110111 : bin = 4'b0111; + 8'b00111000 : bin = 4'b1000; + 8'b00111001 : bin = 4'b1001; + 8'b01000001 : bin = 4'b1010; + 8'b01000010 : bin = 4'b1011; + 8'b01000011 : bin = 4'b1100; + 8'b01000100 : bin = 4'b1101; + 8'b01000101 : bin = 4'b1110; + 8'b01000110 : bin = 4'b1111; + 8'b01100001 : bin = 4'b1010; + 8'b01100010 : bin = 4'b1011; + 8'b01100011 : bin = 4'b1100; + 8'b01100100 : bin = 4'b1101; + 8'b01100101 : bin = 4'b1110; + 8'b01100110 : bin = 4'b1111; + default : + begin + $display("ERROR in %m at time %d ns: NOT A HEX CHARACTER", $time); + bin = 4'bx; + end + endcase + for( j=0; j<4; j=j+1) + begin + if ((index*4)+j < C_WIDTH) + begin + hexstr_conv[(index*4)+j] = bin[j]; + end + end + index = index + 1; + def_data = def_data >> 8; + end + end + endfunction + + function [C_WIDTH-1:0] decstr_conv; + input [(C_WIDTH*8)-1:0] def_data; + + integer index,i,j,ten; + reg [3:0] bin; + reg [C_WIDTH-1:0] temp, result; + + begin + index = 0; + decstr_conv = 'b0; + result = 'b0; + for( i=0; i> 8; + end + end + endfunction + + task write_meminit_file; + + integer addrs, outfile, bit_index; + + reg [C_WIDTH-1 : 0] conts; + reg anyX; + + begin + outfile = $fopen(C_MEM_INIT_FILE); + for( addrs = 0; addrs < C_DEPTH; addrs=addrs+1) + begin + anyX = 1'b0; + conts = ram_data[addrs]; + for(bit_index = 0; bit_index < C_WIDTH; bit_index=bit_index+1) + if(conts[bit_index] === 1'bx) anyX = 1'b1; + if(anyX == 1'b1) + $display("ERROR in %m at time %d ns: MEMORY CONTAINS UNKNOWNS", $time); + $fdisplay(outfile,"%b",ram_data[addrs]); + end + $fclose(outfile); + end + endtask + +endmodule + +`undef all0s +`undef all1s +`undef allXs +`undef allZs +`undef addrallXs + +`undef c_rom +`undef c_sp_ram +`undef c_dp_ram +`undef c_srl16 + +`undef c_lut_based +`undef c_buft_based + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/C_DIST_MEM_V7_0.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/C_DIST_MEM_V7_0.v new file mode 100644 index 0000000..4052470 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/C_DIST_MEM_V7_0.v @@ -0,0 +1,944 @@ +// Copyright(C) 2003 by Xilinx, Inc. All rights reserved. +// This text/file contains proprietary, confidential +// information of Xilinx, Inc., is distributed under license +// from Xilinx, Inc., and may be used, copied and/or +// disclosed only pursuant to the terms of a valid license +// agreement with Xilinx, Inc. Xilinx hereby grants you +// a license to use this text/file solely for design, simulation, +// implementation and creation of design files limited +// to Xilinx devices or technologies. Use with non-Xilinx +// devices or technologies is expressly prohibited and +// immediately terminates your license unless covered by +// a separate agreement. +// +// Xilinx is providing this design, code, or information +// "as is" solely for use in developing programs and +// solutions for Xilinx devices. By providing this design, +// code, or information as one possible implementation of +// this feature, application or standard, Xilinx is making no +// representation that this implementation is free from any +// claims of infringement. You are responsible for +// obtaining any rights you may require for your implementation. +// Xilinx expressly disclaims any warranty whatsoever with +// respect to the adequacy of the implementation, including +// but not limited to any warranties or representations that this +// implementation is free from claims of infringement, implied +// warranties of merchantability or fitness for a particular +// purpose. +// +// Xilinx products are not intended for use in life support +// appliances, devices, or systems. Use in such applications are +// expressly prohibited. +// +// This copyright and support notice must be retained as part +// of this text at all times. (c) Copyright 1995-2003 Xilinx, Inc. +// All rights reserved. + + + +/* $Revision: 1.13 $ $Date: 2008/09/08 20:06:53 $ +-- +-- Filename - C_DIST_MEM_V7_0.v +-- Author - Xilinx +-- Creation - 24 Mar 1999 +-- +-- Description +-- Distributed RAM Simulation Model +*/ + + +`timescale 1ns/10ps +`define all0s 'b0 +`define all1s {C_WIDTH{1'b1}} +`define allXs {C_WIDTH{1'bx}} +`define allZs {C_WIDTH{1'bz}} +`define addrallXs {C_ADDR_WIDTH{1'bx}} + +`define c_rom 0 +`define c_sp_ram 1 +`define c_dp_ram 2 +`define c_srl16 3 + +`define c_lut_based 0 +`define c_buft_based 1 + +module C_DIST_MEM_V7_0 (A, D, DPRA, SPRA, CLK, WE, I_CE, RD_EN, QSPO_CE, QDPO_CE, QDPO_CLK, QSPO_RST, QDPO_RST, QSPO_SRST, QDPO_SRST, SPO, DPO, QSPO, QDPO); + + parameter C_ADDR_WIDTH = 6; + parameter C_DEFAULT_DATA = "0"; + parameter C_DEFAULT_DATA_RADIX = 1; + parameter C_DEPTH = 64; + parameter C_ENABLE_RLOCS = 1; + parameter C_GENERATE_MIF = 0; + parameter C_HAS_CLK = 1; + parameter C_HAS_D = 1; + parameter C_HAS_DPO = 0; + parameter C_HAS_DPRA = 0; + parameter C_HAS_I_CE = 0; + parameter C_HAS_QDPO = 0; + parameter C_HAS_QDPO_CE = 0; + parameter C_HAS_QDPO_CLK = 0; + parameter C_HAS_QDPO_RST = 0; // RSTB + parameter C_HAS_QDPO_SRST = 0; + parameter C_HAS_QSPO = 0; + parameter C_HAS_QSPO_CE = 0; + parameter C_HAS_QSPO_RST = 0; // RSTA + parameter C_HAS_QSPO_SRST = 0; + parameter C_HAS_RD_EN = 0; + parameter C_HAS_SPO = 1; + parameter C_HAS_SPRA = 0; + parameter C_HAS_WE = 1; + parameter C_LATENCY = 0; + parameter C_MEM_INIT_FILE = "null.mif"; + parameter C_MEM_TYPE = 1; // c_sp_ram + parameter C_MUX_TYPE = 0; // c_lut_based + parameter C_QCE_JOINED = 0; + parameter C_QUALIFY_WE = 0; + parameter C_READ_MIF = 0; + parameter C_REG_A_D_INPUTS = 0; + parameter C_REG_DPRA_INPUT = 0; + parameter C_SYNC_ENABLE = 0; + parameter C_WIDTH = 16; + parameter radix = C_DEFAULT_DATA_RADIX; + parameter pipe_stages = C_LATENCY-C_REG_A_D_INPUTS; + parameter dpo_pipe_stages = pipe_stages+1-C_HAS_QSPO; // replaced C_HAS_QDPO for 1 as this parameter is only valid when C_HAS_QDPO anyway + parameter C_RAM32_FIX = 0; // should not be passed in to simulation model + + parameter NCELAB_DPO_PIPE_CONSTANT = (dpo_pipe_stages < 2 ? 0 : 2); + parameter NCELAB_SPO_PIPE_CONSTANT = (pipe_stages < 2 ? 0 : 2); + + input [C_ADDR_WIDTH-1 - (C_ADDR_WIDTH>4?(4*C_HAS_SPRA):0) : 0] A; + input [C_WIDTH-1 : 0] D; + input [C_ADDR_WIDTH-1 : 0] DPRA; + input [C_ADDR_WIDTH-1 : 0] SPRA; + input CLK; + input WE; + input I_CE; + input RD_EN; + input QSPO_CE; + input QDPO_CE; + input QDPO_CLK; + input QSPO_RST; + input QDPO_RST; + input QSPO_SRST; + input QDPO_SRST; + output [C_WIDTH-1 : 0] SPO; + output [C_WIDTH-1 : 0] QSPO; + output [C_WIDTH-1 : 0] DPO; + output [C_WIDTH-1 : 0] QDPO; + + // Address signal connected to memory + wire [C_ADDR_WIDTH - 1 : 0] a_int; + // Read Address signal connected to srl16-based memory + wire [C_ADDR_WIDTH - 1 : 0] spra_int; + // Registered Address signal connected to memory + wire [C_ADDR_WIDTH - 1 : 0] a_int1; + // Registered Read Address signal connected to srl16-based memory + wire [C_ADDR_WIDTH - 1 : 0] spra_int1; + // DP port address signal connected to memory + wire [C_ADDR_WIDTH - 1 : 0] dpra_int; + // DP port address signal connected to memory + wire [C_ADDR_WIDTH - 1 : 0] dpra_int1; + // Input data signal connected to memory + wire [C_WIDTH - 1 : 0] d_int; + // Registered Input data signal connected to memory + wire [C_WIDTH - 1 : 0] d_int1; + // DP output register clock + wire doclk; + // Input data/address/WE register Clock Enable + wire ice; + // Special address register Clock Enable for ROMs + wire a_reg_ice; + // DP read address port register clock enable +// wire dpra_ce; + // WE wire connected to memory + wire we_int; + // Registered WE wire connected to memory + wire we_int1; + // Clock enable for the WE register + wire wece; + // Read Enable wire connected to BUFT-type output mux + wire re_int; + // Registered Read Enable wire connected to BUFT-type output mux + wire re_int1; + // unregistered version of qspo_ce + wire qspo_ce_int; + // possibly registered version of qspo_ce + wire qspo_ce_reg; + // registered version of qspo_ce + wire qspo_ce_reg1; + // unregistered version of qdpo_ce + wire qdpo_ce_int; + // possibly registered version of qdpo_ce + wire qdpo_ce_reg; + // registered version of qdpo_ce + wire qdpo_ce_reg1; + // possibly single port registered output reset + wire qspo_rst_int; + // possibly dual port registered output reset + wire qdpo_rst_int; + // possibly single port registered output sync reset + wire qspo_srst_int; + // possibly dual port registered output sync reset + wire qdpo_srst_int; + // Direct SP output from memory + reg [C_WIDTH - 1 : 0] spo_async; + // Direct DP output from memory + reg [C_WIDTH - 1 : 0] dpo_async; + // Possibly pipelined and/or registered SP output from memory + wire [C_WIDTH - 1 : 0] intQSPO; + // Possibly pipelined and/or registered DP output from memory + wire [C_WIDTH - 1 : 0] intQDPO; + // Pipeline signals + reg [C_WIDTH - 1 : 0] spo_pipe [pipe_stages+2 : 0]; + reg [C_WIDTH - 1 : 0] dpo_pipe [dpo_pipe_stages+2 : 0]; + // Possibly pipelined SP output from memory + reg [C_WIDTH - 1 : 0] spo_pipeend; + // Possibly pipelined DP output from memory + reg [C_WIDTH - 1 : 0] dpo_pipeend; + // BUFT outputs + wire [C_WIDTH - 1 : 0] spo_reg; + wire [C_WIDTH - 1 : 0] dpo_reg; + wire [C_WIDTH - 1 : 0] spo_reg_tmp; + wire [C_WIDTH - 1 : 0] dpo_reg_tmp; + + integer pipe, pipe1, pipe2, pipe3, pipe4, i, j, srl_start, srl_end; + + // Array to hold ram data + reg [C_WIDTH-1 : 0] ram_data [C_DEPTH-1 : 0]; + reg [C_WIDTH-1 : 0] tmp_data1; + reg [C_WIDTH-1 : 0] tmp_data2; + + reg [C_WIDTH-1 : 0] default_data; + reg [C_WIDTH-1 : 0] spo_tmp; + reg [C_WIDTH-1 : 0] dpo_tmp; + reg [C_WIDTH-1 : 0] tmp_pipe1; + reg [C_WIDTH-1 : 0] tmp_pipe2; + reg [C_WIDTH-1 : 0] tmp_pipe3; + reg lastCLK; + reg lastdoclk; + + reg start; + + function integer ADDR_IS_X; + input [C_ADDR_WIDTH-1 : 0] value; + integer i; + begin + ADDR_IS_X = 0; + for(i = 0; i < C_ADDR_WIDTH; i = i + 1) + if(value[i] === 1'bx) + ADDR_IS_X = 1; + end + endfunction + + // Deal with the optional output signals... + wire [C_WIDTH - 1 : 0] SPO = (C_HAS_SPO ? (C_MUX_TYPE == `c_lut_based ? spo_async : spo_reg) : `allXs); + wire [C_WIDTH - 1 : 0] DPO = (C_HAS_DPO && C_MEM_TYPE == `c_dp_ram ? (C_MUX_TYPE == `c_lut_based ? dpo_async : dpo_reg) : `allXs); + wire [C_WIDTH - 1 : 0] QSPO = (C_HAS_QSPO ? intQSPO : `allXs); + wire [C_WIDTH - 1 : 0] QDPO = (C_HAS_QDPO ? intQDPO : `allXs); + + // Deal with the optional input signals... + + assign ice = (C_HAS_I_CE == 1 ? I_CE : 1'b1); + assign a_reg_ice = (C_MEM_TYPE == `c_rom ? qspo_ce_int : ice); + assign wece = (C_HAS_WE == 1 && C_REG_A_D_INPUTS == 1 && C_QUALIFY_WE == 1 ? ice : 1'b1); +// assign dpra_ce = (C_HAS_QDPO_CE == 1 ? QDPO_CE : 1'b1); + assign doclk = (C_HAS_QDPO_CLK == 1 ? QDPO_CLK : CLK); + assign qspo_ce_int = (C_HAS_QSPO_CE == 1 ? QSPO_CE : 1'b1); + assign qdpo_ce_int = (C_QCE_JOINED == 1 ? qspo_ce_int : (C_HAS_QDPO_CE == 1 ? QDPO_CE : ((C_HAS_QSPO == 1 && C_MEM_TYPE == `c_srl16) ? qspo_ce_int : 1'b1))); + assign qspo_rst_int = (C_HAS_QSPO_RST && C_HAS_QSPO ? QSPO_RST : 1'b0); + assign qdpo_rst_int = (C_HAS_QDPO_RST && C_HAS_QDPO ? QDPO_RST : 1'b0); + assign qspo_srst_int = (C_HAS_QSPO_SRST && C_HAS_QSPO ? QSPO_SRST : 1'b0); + assign qdpo_srst_int = (C_HAS_QDPO_SRST && C_HAS_QDPO ? QDPO_SRST : 1'b0); + + // (Optional) registers on SP address and on optional data/we/qspo_ce signals + C_REG_FD_V7_0 #("0", C_ENABLE_RLOCS, 0, 0, 0, + 0, 0, 0, 0, + "0", 0, 0, 1) + qspo1_reg (.D(qspo_ce_int), .CLK(CLK), .CE(1'b0), .ACLR(1'b0), .ASET(1'b0), + .AINIT(1'b0), .SCLR(1'b0), .SSET(1'b0), .SINIT(1'b0), + .Q(qspo_ce_reg1)); + + C_REG_FD_V7_0 #("0", C_ENABLE_RLOCS, 0, 0, 0, + 1, 0, 0, 0, + "0", 0, 0, (C_ADDR_WIDTH-(C_ADDR_WIDTH>4?(C_HAS_SPRA*4):0))) + a_rega (.D(A[C_ADDR_WIDTH - 1-(C_ADDR_WIDTH>4?(4*C_HAS_SPRA):0) : 0]), .CLK(CLK), .CE(a_reg_ice), .ACLR(1'b0), .ASET(1'b0), + .AINIT(1'b0), .SCLR(1'b0), .SSET(1'b0), .SINIT(1'b0), + .Q(a_int1[C_ADDR_WIDTH - 1-(C_ADDR_WIDTH>4?(4*C_HAS_SPRA):0) : 0])); + + C_REG_FD_V7_0 #("0", C_ENABLE_RLOCS, 0, 0, 0, + 1, 0, 0, 0, + "0", 0, 0, C_ADDR_WIDTH) + spra_reg (.D(SPRA), .CLK(CLK), .CE(qspo_ce_int), .ACLR(1'b0), .ASET(1'b0), + .AINIT(1'b0), .SCLR(1'b0), .SSET(1'b0), .SINIT(1'b0), + .Q(spra_int1)); + + C_REG_FD_V7_0 #("0", C_ENABLE_RLOCS, 0, 0, 0, + 1, 0, 0, 0, + "0", 0, 0, 1) + we_reg (.D(WE), .CLK(CLK), .CE(wece), .ACLR(1'b0), .ASET(1'b0), + .AINIT(1'b0), .SCLR(1'b0), .SSET(1'b0), .SINIT(1'b0), + .Q(we_int1)); + + C_REG_FD_V7_0 #("0", C_ENABLE_RLOCS, 0, 0, 0, + 0, 0, 0, 0, + "0", 0, 0, 1) + re_reg (.D(RD_EN), .CLK(CLK),// .CE(qspo_ce_int), + .CE(1'b0), .ACLR(1'b0), .ASET(1'b0), + .AINIT(1'b0), .SCLR(1'b0), .SSET(1'b0), .SINIT(1'b0), + .Q(re_int1)); + + C_REG_FD_V7_0 #("0", C_ENABLE_RLOCS, 0, 0, 0, + 1, 0, 0, 0, + "0", 0, 0, C_WIDTH) + d_reg (.D(D), .CLK(CLK), .CE(ice), .ACLR(1'b0), .ASET(1'b0), + .AINIT(1'b0), .SCLR(1'b0), .SSET(1'b0), .SINIT(1'b0), + .Q(d_int1)); + + C_REG_FD_V7_0 #("0", C_ENABLE_RLOCS, 0, 0, 0, + 0, 0, 0, 0, + "0", 0, 0, C_WIDTH) + spo_reg1 (.D(spo_async), .CLK(CLK), .CE(1'b0), .ACLR(1'b0), .ASET(1'b0), + .AINIT(1'b0), .SCLR(1'b0), .SSET(1'b0), .SINIT(1'b0), + .Q(spo_reg_tmp)); + + C_REG_FD_V7_0 #("0", C_ENABLE_RLOCS, 0, 0, 0, + 0, 0, 0, 0, + "0", 0, 0, C_WIDTH) + dpo_reg1 (.D(dpo_async), .CLK(doclk), .CE(1'b0), .ACLR(1'b0), .ASET(1'b0), + .AINIT(1'b0), .SCLR(1'b0), .SSET(1'b0), .SINIT(1'b0), + .Q(dpo_reg_tmp)); + + // Deal with these optional registers + assign qspo_ce_reg = (C_REG_A_D_INPUTS == 0 ? (C_HAS_QSPO_CE == 1 ? qspo_ce_int : 1'b1) : (C_HAS_QSPO_CE == 1 ? qspo_ce_reg1 : 1'b1)); + assign a_int = (C_REG_A_D_INPUTS == 0 ? (C_MEM_TYPE != `c_srl16 ? A : (C_ADDR_WIDTH>4 ? A[C_ADDR_WIDTH - 1 -(C_ADDR_WIDTH>4?(4*C_HAS_SPRA):0) : 0]<<4 : 0)) : + (C_MEM_TYPE != `c_srl16 ? a_int1 : (C_ADDR_WIDTH>4 ? a_int1[C_ADDR_WIDTH - 1 -(C_ADDR_WIDTH>4?(4*C_HAS_SPRA):0) : 0]<<4 : 0))); + assign spra_int = (C_REG_A_D_INPUTS == 0 ? (C_MEM_TYPE != `c_srl16 ? A : SPRA) : + (C_MEM_TYPE != `c_srl16 ? a_int1 : spra_int1)); + assign we_int = (C_REG_A_D_INPUTS == 0 ? (C_HAS_WE == 1 ? WE : 1'b1) : (C_HAS_WE == 1 ? we_int1 : 1'b1)); + assign re_int = (C_REG_A_D_INPUTS == 0 ? (C_HAS_RD_EN == 1 ? RD_EN : 1'b1) : (C_HAS_RD_EN == 1 ? re_int1 : 1'b1)); + assign d_int = (C_REG_A_D_INPUTS == 0 ? (C_HAS_D == 1 ? D : `allXs) : (C_HAS_D == 1 ? d_int1 : `allXs)); + assign spo_reg = (pipe_stages == 1 ? spo_reg_tmp : spo_async); + assign dpo_reg = (pipe_stages == 1 ? dpo_reg_tmp : dpo_async); + + // (Optional) DP Read Address and QDPO_CE registers + + C_REG_FD_V7_0 #("0", C_ENABLE_RLOCS, 0, 0, 0, + 1, 0, 0, 0, + "0", 0, 0, C_ADDR_WIDTH) + dpra_reg (.D(DPRA), .CLK(doclk), .CE(qdpo_ce_int), .ACLR(1'b0), .ASET(1'b0), + .AINIT(1'b0), .SCLR(1'b0), .SSET(1'b0), .SINIT(1'b0), + .Q(dpra_int1)); + + C_REG_FD_V7_0 #("0", C_ENABLE_RLOCS, 0, 0, 0, + 0, 0, 0, 0, + "0", 0, 0, 1) + qdpo1_reg (.D(qdpo_ce_int), .CLK(doclk), .CE(1'b0), .ACLR(1'b0), .ASET(1'b0), + .AINIT(1'b0), .SCLR(1'b0), .SSET(1'b0), .SINIT(1'b0), + .Q(qdpo_ce_reg1)); + + // Deal with these optional registers + assign qdpo_ce_reg = (C_REG_DPRA_INPUT == 0 ? (C_HAS_QDPO_CE == 1 ? qdpo_ce_int : (C_QCE_JOINED == 1 ? qdpo_ce_int : 1'b1)) : + (C_HAS_QDPO_CE == 1 ? qdpo_ce_reg1 : (C_QCE_JOINED == 1 || C_MEM_TYPE == `c_srl16 ? qdpo_ce_reg1 : 1'b1))); + assign dpra_int = (C_REG_DPRA_INPUT == 0 ? (C_HAS_DPRA == 1 ? DPRA : `allXs) : (C_HAS_DPRA == 1 ? dpra_int1 : `allXs)); + + // (Optional) pipeline registers + + always@(posedge CLK) + begin + if(CLK === 1'b1 && lastCLK === 1'b0 && qspo_ce_reg === 1'b1) // OK! Update pipelines! + begin + for(pipe = 2; pipe <= pipe_stages-1; pipe = pipe + 1) + begin + spo_pipe[pipe] <= spo_pipe[pipe+1]; + end + spo_pipe[pipe_stages] <= spo_async; + end + else if((CLK === 1'bx && lastCLK === 1'b0) || (CLK === 1'b1 && lastCLK === 1'bx) || qspo_ce_reg === 1'bx) // POSSIBLY Update pipelines! + begin + for(pipe = 2; pipe <= pipe_stages-1; pipe = pipe + 1) + begin + tmp_pipe1 = spo_pipe[pipe]; + tmp_pipe2 = spo_pipe[pipe+1]; + for(pipe1 = 0; pipe1 < C_WIDTH; pipe1 = pipe1 + 1) + begin + if(tmp_pipe1[pipe1] !== tmp_pipe2[pipe1]) + tmp_pipe1[pipe1] = 1'bx; + end + spo_pipe[pipe] <= tmp_pipe1; + end + tmp_pipe1 = spo_pipe[pipe_stages]; + for(pipe1 = 0; pipe1 < C_WIDTH; pipe1 = pipe1 + 1) + begin + if(tmp_pipe1[pipe1] !== spo_async[pipe1]) + tmp_pipe1[pipe1] = 1'bx; + end + spo_pipe[pipe_stages] <= tmp_pipe1; + end + end + + always@(spo_async or spo_pipe[NCELAB_SPO_PIPE_CONSTANT]) //2 + begin + if(pipe_stages < 2) // No pipeline + spo_pipeend <= spo_async; + else // Pipeline stages required + begin + spo_pipeend <= spo_pipe[NCELAB_SPO_PIPE_CONSTANT]; //2 + end + end + + always@(posedge doclk) + begin + if(doclk === 1'b1 && lastdoclk === 1'b0 && qdpo_ce_reg === 1'b1) // OK! Update pipelines! + begin + for(pipe3 = 2; pipe3 <= dpo_pipe_stages-1; pipe3 = pipe3 + 1) + begin + dpo_pipe[pipe3] <= dpo_pipe[pipe3+1]; + end + dpo_pipe[dpo_pipe_stages] <= dpo_async; + end + else if((doclk === 1'bx && lastdoclk === 1'b0) || (doclk === 1'b1 && lastdoclk === 1'bx) || qdpo_ce_reg === 1'bx) // POSSIBLY Update pipelines! + begin + for(pipe4 = 2; pipe4 <= dpo_pipe_stages-1; pipe4 = pipe4 + 1) + begin + tmp_pipe3 = dpo_pipe[pipe4]; + tmp_pipe2 = dpo_pipe[pipe4+1]; + for(pipe1 = 0; pipe1 < C_WIDTH; pipe1 = pipe1 + 1) + begin + if(tmp_pipe3[pipe1] !== tmp_pipe2[pipe1]) + tmp_pipe3[pipe1] = 1'bx; + end + dpo_pipe[pipe4] <= tmp_pipe3; + end + tmp_pipe3 = dpo_pipe[dpo_pipe_stages]; + for(pipe2 = 0; pipe2 < C_WIDTH; pipe2 = pipe2 + 1) + begin + if(tmp_pipe3[pipe2] !== dpo_async[pipe2]) + tmp_pipe3[pipe2] = 1'bx; + end + dpo_pipe[dpo_pipe_stages] <= tmp_pipe3; + end + end + + always@(dpo_async or dpo_pipe[NCELAB_DPO_PIPE_CONSTANT]) //2 + begin + if(dpo_pipe_stages < 2) // No pipeline + dpo_pipeend <= dpo_async; + else // Pipeline stages required + begin + dpo_pipeend <= dpo_pipe[NCELAB_DPO_PIPE_CONSTANT]; //2 + end + end + + // (Optional) output registers at end of optional pipelines + + C_REG_FD_V7_0 #("0", C_ENABLE_RLOCS, C_HAS_QSPO_RST, 0, 0, + 1, C_HAS_QSPO_SRST, 0, 0, + "0", C_SYNC_ENABLE, 0, C_WIDTH) + qspo_reg (.D(spo_pipeend), .CLK(CLK), .CE(qspo_ce_reg), .ASET(1'b0), + .AINIT(1'b0), .SSET(1'b0), .SINIT(1'b0), + .ACLR(qspo_rst_int), .SCLR(qspo_srst_int), .Q(intQSPO)); + + C_REG_FD_V7_0 #("0", C_ENABLE_RLOCS, C_HAS_QDPO_RST, 0, 0, + 1, C_HAS_QDPO_SRST, 0, 0, + "0", C_SYNC_ENABLE, 0, C_WIDTH) + qdpo_reg (.D(dpo_pipeend), .CLK(doclk), .CE(qdpo_ce_reg), .ASET(1'b0), + .AINIT(1'b0), .SSET(1'b0), .SINIT(1'b0), + .ACLR(qdpo_rst_int), .SCLR(qdpo_srst_int), .Q(intQDPO)); + + + + // Startup behaviour + initial + begin + default_data = 'b0; + case (radix) + 3 : default_data = decstr_conv(C_DEFAULT_DATA); + 2 : default_data = binstr_conv(C_DEFAULT_DATA); + 1 : default_data = hexstr_conv(C_DEFAULT_DATA); + default : $display("ERROR in %m at %d ns: BAD DATA RADIX - valid range 1 to 3", $time); + endcase + + for(i = 0; i < C_DEPTH; i = i + 1) + ram_data[i] = default_data; + + if(C_READ_MIF == 1) + begin + $readmemb(C_MEM_INIT_FILE, ram_data, 0 , C_DEPTH-1); + end + if (C_GENERATE_MIF == 1) + write_meminit_file; + + spo_tmp = 'b0; + dpo_tmp = 'b0; + lastCLK = 1'b0; + lastdoclk = 1'b0; + + spo_async = spo_tmp; + dpo_async = dpo_tmp; + + for(i = 0; i < pipe_stages+3; i = i + 1) + begin + spo_pipe[i] = `all0s; + end + for(i = 0; i < dpo_pipe_stages+3; i = i + 1) + begin + dpo_pipe[i] = `all0s; + end + if(pipe_stages < 2) // No pipeline + begin + spo_pipeend = spo_async; + end + else + begin + spo_pipeend = spo_pipe[NCELAB_SPO_PIPE_CONSTANT]; //2 + end + if(dpo_pipe_stages < 2) // No pipeline + begin + dpo_pipeend = dpo_async; + end + else + begin + dpo_pipeend = dpo_pipe[NCELAB_DPO_PIPE_CONSTANT]; //2 + end + + start <= 0; + end + + always @(CLK) + lastCLK <= CLK; + + always @(doclk) + lastdoclk <= doclk; + + always @(posedge CLK or a_int or we_int or spra_int or dpra_int or d_int or re_int or spo_async or dpo_async or start) + begin + if ($realtime != 0 || start == 0) // gets around race condition at startup (CR 171445) + // added start to ensure that this process is still run at startup + // but after all the intials have completed to fix CR 175826 + begin + if(((CLK === 1'b1 && lastCLK === 1'b0) || C_HAS_CLK == 0) && C_MEM_TYPE != `c_rom) + begin + if(ADDR_IS_X(a_int) || a_int < C_DEPTH) + begin + if(we_int === 1'bx) + begin + if(ADDR_IS_X(a_int)) + begin + for(i = 0; i < C_DEPTH; i = i + 1) + ram_data[i] = `allXs; + end + else + begin + if(C_MEM_TYPE == `c_srl16) + begin + srl_start = (a_int/16)*16; // Ignore lower 4 bits of a_int + srl_end = srl_start+16; + if(srl_end > C_DEPTH) + srl_end = C_DEPTH; + for(i = srl_end-1; i > srl_start; i = i - 1) + begin // Shift data through the SRL16s + tmp_data1 = ram_data[i]; + tmp_data2 = ram_data[i-1]; + for(j = 0; j < C_WIDTH; j = j + 1) + begin + if(tmp_data1[j] !== tmp_data2[j]) + tmp_data1[j] = 1'bx; + end + ram_data[i] = tmp_data1; + end + tmp_data1 = ram_data[srl_start]; + for(j = 0; j < C_WIDTH; j = j + 1) + begin + if(tmp_data1[j] !== d_int[j]) + tmp_data1[j] = 1'bx; + end + ram_data[srl_start] = tmp_data1; + end + else + begin + tmp_data1 = ram_data[a_int]; + for(j = 0; j < C_WIDTH; j = j + 1) + begin + if(tmp_data1[j] !== d_int[j]) + tmp_data1[j] = 1'bx; + end + ram_data[a_int] = tmp_data1; + end + end + end + else if(we_int === 1'b1) + begin + if(ADDR_IS_X(a_int)) + begin + for(i = 0; i < C_DEPTH; i = i + 1) + ram_data[i] = `allXs; + end + else + begin + if(C_MEM_TYPE == `c_srl16) + begin + srl_start = (a_int/16)*16; // Ignore lower 4 bits of a_int + srl_end = srl_start+16; + if(srl_end > C_DEPTH) + srl_end = C_DEPTH; + for(i = srl_end-1; i > srl_start; i = i - 1) + begin // Shift data through the SRL16s + ram_data[i] = ram_data[i-1]; + end + ram_data[srl_start] = d_int; + end + else + begin + //if (C_MEM_TYPE == `c_dp_ram && a_int == dpra_int && we_int == 1 && qspo_ce_int == 1) + //begin + // $display("WARNING in %m at time %d ns: Memory Hazard: Reading and Writing to same dual port address!", $time); + //end + ram_data[a_int] = d_int; + end + end + end + end + else if(a_int >= C_DEPTH) + $display("WARNING in %m at time %d ns: Writing to out-of-range address!! - max address is %d", $time, C_DEPTH); + end + else if((C_HAS_CLK == 0 || ((CLK === 1'bx && lastCLK === 1'b0) || CLK === 1'b1 && lastCLK === 1'bx)) && C_MEM_TYPE != `c_rom) + begin + if(ADDR_IS_X(a_int) || a_int < C_DEPTH) + begin + if(we_int === 1'bx) + begin + if(ADDR_IS_X(a_int)) + begin + for(i = 0; i < C_DEPTH; i = i + 1) + ram_data[i] = `allXs; + end + else + begin + if(C_MEM_TYPE == `c_srl16) + begin + srl_start = (a_int/16)*16; // Ignore lower 4 bits of a_int + srl_end = srl_start+16; + if(srl_end > C_DEPTH) + srl_end = C_DEPTH; + for(i = srl_end-1; i > srl_start; i = i - 1) + begin // Shift data through the SRL16s + tmp_data1 = ram_data[i]; + tmp_data2 = ram_data[i-1]; + for(j = 0; j < C_WIDTH; j = j + 1) + begin + if(tmp_data1[j] !== tmp_data2[j]) + tmp_data1[j] = 1'bx; + end + ram_data[i] = tmp_data1; + end + tmp_data1 = ram_data[srl_start]; + for(j = 0; j < C_WIDTH; j = j + 1) + begin + if(tmp_data1[j] !== d_int[j]) + tmp_data1[j] = 1'bx; + end + ram_data[srl_start] = tmp_data1; + end + else + begin + tmp_data1 = ram_data[a_int]; + for(j = 0; j < C_WIDTH; j = j + 1) + begin + if(tmp_data1[j] !== d_int[j]) + tmp_data1[j] = 1'bx; + end + ram_data[a_int] = tmp_data1; + end + end + end + else if(we_int === 1'b1) + begin + if(ADDR_IS_X(a_int)) + begin + for(i = 0; i < C_DEPTH; i = i + 1) + ram_data[i] = `allXs; + end + else + begin + if(C_MEM_TYPE == `c_srl16) + begin + srl_start = (a_int/16)*16; // Ignore lower 4 bits of a_int + srl_end = srl_start+16; + if(srl_end > C_DEPTH) + srl_end = C_DEPTH; + for(i = srl_end-1; i > srl_start; i = i - 1) + begin // Shift data through the SRL16s + tmp_data1 = ram_data[i]; + tmp_data2 = ram_data[i-1]; + for(j = 0; j < C_WIDTH; j = j + 1) + begin + if(tmp_data1[j] !== tmp_data2[j]) + tmp_data1[j] = 1'bx; + end + ram_data[i] = tmp_data1; + end + tmp_data1 = ram_data[srl_start]; + for(j = 0; j < C_WIDTH; j = j + 1) + begin + if(tmp_data1[j] !== d_int[j]) + tmp_data1[j] = 1'bx; + end + ram_data[srl_start] = tmp_data1; + end + else + begin + //if (C_MEM_TYPE == `c_dp_ram && a_int == dpra_int && we_int == 1 && qspo_ce_int == 1) + //begin + // $display("WARNING in %m at time %d ns: Memory Hazard: Reading and Writing to same dual port address!", $time); + //end + tmp_data1 = ram_data[a_int]; + for(j = 0; j < C_WIDTH; j = j + 1) + begin + if(tmp_data1[j] !== d_int[j]) + tmp_data1[j] = 1'bx; + end + ram_data[a_int] = tmp_data1; + end + end + end + end + else if(a_int >= C_DEPTH) + $display("WARNING in %m at time %d ns: Writing to out-of-range address!! - max address is %d", $time, C_DEPTH); + end + + // Read behaviour + + if(re_int === 1'bx) + begin + spo_tmp = `allXs; + dpo_tmp = `allXs; + end + else if(re_int === 1'b1) + begin + if(ADDR_IS_X(spra_int)) + spo_tmp = `allXs; + else + begin + if(spra_int < C_DEPTH) + spo_tmp = ram_data[spra_int]; + else if(C_MUX_TYPE == `c_buft_based) + begin + $display("WARNING in %m at time %d ns: Reading from out-of-range address!! - max address is %d", $time, C_DEPTH); + spo_tmp = `allZs; + end + else + begin + $display("WARNING in %m at time %d ns: Reading from out-of-range address!! - max address is %d", $time, C_DEPTH); + spo_tmp = `all0s; + end + end + + if(ADDR_IS_X(dpra_int)) + dpo_tmp = `allXs; + else + begin + if(dpra_int < C_DEPTH) + dpo_tmp = ram_data[dpra_int]; + else if(C_MUX_TYPE == `c_buft_based) + begin + $display("WARNING in %m at time %d ns: Reading from out-of-range address!! - max address is %d", $time, C_DEPTH); + dpo_tmp = `allZs; + end + else + begin + $display("WARNING in %m at time %d ns: Reading from out-of-range address!! - max address is %d", $time, C_DEPTH); + dpo_tmp = `all0s; + end + end + end + else // re_int == 0 + begin + spo_tmp = `all1s; + dpo_tmp = `all1s; + end + + spo_async <= spo_tmp; + dpo_async <= dpo_tmp; + end + + end + + + function [C_WIDTH-1:0] binstr_conv; + input [(C_WIDTH*8)-1:0] def_data; + + integer index,i; + + begin + index = 0; + binstr_conv = 'b0; + + for( i=C_WIDTH-1; i>=0; i=i-1 ) + begin + case (def_data[7:0]) + 8'b00000000 : i = -1; + 8'b00110000 : binstr_conv[index] = 1'b0; + 8'b00110001 : binstr_conv[index] = 1'b1; + default : + begin + $display("ERROR in %m at time %d ns: NOT A BINARY CHARACTER", $time); + binstr_conv[index] = 1'bx; + end + endcase + index = index + 1; + def_data = def_data >> 8; + end + end + endfunction + + function [C_WIDTH-1:0] hexstr_conv; + input [(C_WIDTH*8)-1:0] def_data; + + integer index,i,j; + reg [3:0] bin; + + begin + index = 0; + hexstr_conv = 'b0; + for( i=C_WIDTH-1; i>=0; i=i-1 ) + begin + case (def_data[7:0]) + 8'b00000000 : + begin + bin = 4'b0000; + i = -1; + end + 8'b00110000 : bin = 4'b0000; + 8'b00110001 : bin = 4'b0001; + 8'b00110010 : bin = 4'b0010; + 8'b00110011 : bin = 4'b0011; + 8'b00110100 : bin = 4'b0100; + 8'b00110101 : bin = 4'b0101; + 8'b00110110 : bin = 4'b0110; + 8'b00110111 : bin = 4'b0111; + 8'b00111000 : bin = 4'b1000; + 8'b00111001 : bin = 4'b1001; + 8'b01000001 : bin = 4'b1010; + 8'b01000010 : bin = 4'b1011; + 8'b01000011 : bin = 4'b1100; + 8'b01000100 : bin = 4'b1101; + 8'b01000101 : bin = 4'b1110; + 8'b01000110 : bin = 4'b1111; + 8'b01100001 : bin = 4'b1010; + 8'b01100010 : bin = 4'b1011; + 8'b01100011 : bin = 4'b1100; + 8'b01100100 : bin = 4'b1101; + 8'b01100101 : bin = 4'b1110; + 8'b01100110 : bin = 4'b1111; + default : + begin + $display("ERROR in %m at time %d ns: NOT A HEX CHARACTER", $time); + bin = 4'bx; + end + endcase + for( j=0; j<4; j=j+1) + begin + if ((index*4)+j < C_WIDTH) + begin + hexstr_conv[(index*4)+j] = bin[j]; + end + end + index = index + 1; + def_data = def_data >> 8; + end + end + endfunction + + function [C_WIDTH-1:0] decstr_conv; + input [(C_WIDTH*8)-1:0] def_data; + + integer index,i,j,ten; + reg [3:0] bin; + reg [C_WIDTH-1:0] temp, result; + + begin + index = 0; + decstr_conv = 'b0; + result = 'b0; + for( i=0; i> 8; + end + end + endfunction + + task write_meminit_file; + + integer addrs, outfile, bit_index; + + reg [C_WIDTH-1 : 0] conts; + reg anyX; + + begin + outfile = $fopen(C_MEM_INIT_FILE); + for( addrs = 0; addrs < C_DEPTH; addrs=addrs+1) + begin + anyX = 1'b0; + conts = ram_data[addrs]; + for(bit_index = 0; bit_index < C_WIDTH; bit_index=bit_index+1) + if(conts[bit_index] === 1'bx) anyX = 1'b1; + if(anyX == 1'b1) + $display("ERROR in %m at time %d ns: MEMORY CONTAINS UNKNOWNS", $time); + $fdisplay(outfile,"%b",ram_data[addrs]); + end + $fclose(outfile); + end + endtask + +endmodule + +`undef all0s +`undef all1s +`undef allXs +`undef allZs +`undef addrallXs + +`undef c_rom +`undef c_sp_ram +`undef c_dp_ram +`undef c_srl16 + +`undef c_lut_based +`undef c_buft_based + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/C_DIST_MEM_V7_1.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/C_DIST_MEM_V7_1.v new file mode 100644 index 0000000..2467c26 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/C_DIST_MEM_V7_1.v @@ -0,0 +1,944 @@ +// Copyright(C) 2004 by Xilinx, Inc. All rights reserved. +// This text/file contains proprietary, confidential +// information of Xilinx, Inc., is distributed under license +// from Xilinx, Inc., and may be used, copied and/or +// disclosed only pursuant to the terms of a valid license +// agreement with Xilinx, Inc. Xilinx hereby grants you +// a license to use this text/file solely for design, simulation, +// implementation and creation of design files limited +// to Xilinx devices or technologies. Use with non-Xilinx +// devices or technologies is expressly prohibited and +// immediately terminates your license unless covered by +// a separate agreement. +// +// Xilinx is providing this design, code, or information +// "as is" solely for use in developing programs and +// solutions for Xilinx devices. By providing this design, +// code, or information as one possible implementation of +// this feature, application or standard, Xilinx is making no +// representation that this implementation is free from any +// claims of infringement. You are responsible for +// obtaining any rights you may require for your implementation. +// Xilinx expressly disclaims any warranty whatsoever with +// respect to the adequacy of the implementation, including +// but not limited to any warranties or representations that this +// implementation is free from claims of infringement, implied +// warranties of merchantability or fitness for a particular +// purpose. +// +// Xilinx products are not intended for use in life support +// appliances, devices, or systems. Use in such applications are +// expressly prohibited. +// +// This copyright and support notice must be retained as part +// of this text at all times. (c) Copyright 1995-2004 Xilinx, Inc. +// All rights reserved. + + + +/* $Revision: 1.12 $ $Date: 2008/09/08 20:06:54 $ +-- +-- Filename - C_DIST_MEM_V7_1.v +-- Author - Xilinx +-- Creation - 24 Mar 1999 +-- +-- Description +-- Distributed RAM Simulation Model +*/ + + +`timescale 1ns/10ps +`define all0s 'b0 +`define all1s {C_WIDTH{1'b1}} +`define allXs {C_WIDTH{1'bx}} +`define allZs {C_WIDTH{1'bz}} +`define addrallXs {C_ADDR_WIDTH{1'bx}} + +`define c_rom 0 +`define c_sp_ram 1 +`define c_dp_ram 2 +`define c_srl16 3 + +`define c_lut_based 0 +`define c_buft_based 1 + +module C_DIST_MEM_V7_1 (A, D, DPRA, SPRA, CLK, WE, I_CE, RD_EN, QSPO_CE, QDPO_CE, QDPO_CLK, QSPO_RST, QDPO_RST, QSPO_SRST, QDPO_SRST, SPO, DPO, QSPO, QDPO); + + parameter C_ADDR_WIDTH = 6; + parameter C_DEFAULT_DATA = "0"; + parameter C_DEFAULT_DATA_RADIX = 1; + parameter C_DEPTH = 64; + parameter C_ENABLE_RLOCS = 1; + parameter C_GENERATE_MIF = 0; + parameter C_HAS_CLK = 1; + parameter C_HAS_D = 1; + parameter C_HAS_DPO = 0; + parameter C_HAS_DPRA = 0; + parameter C_HAS_I_CE = 0; + parameter C_HAS_QDPO = 0; + parameter C_HAS_QDPO_CE = 0; + parameter C_HAS_QDPO_CLK = 0; + parameter C_HAS_QDPO_RST = 0; // RSTB + parameter C_HAS_QDPO_SRST = 0; + parameter C_HAS_QSPO = 0; + parameter C_HAS_QSPO_CE = 0; + parameter C_HAS_QSPO_RST = 0; // RSTA + parameter C_HAS_QSPO_SRST = 0; + parameter C_HAS_RD_EN = 0; + parameter C_HAS_SPO = 1; + parameter C_HAS_SPRA = 0; + parameter C_HAS_WE = 1; + parameter C_LATENCY = 0; + parameter C_MEM_INIT_FILE = "null.mif"; + parameter C_MEM_TYPE = 1; // c_sp_ram + parameter C_MUX_TYPE = 0; // c_lut_based + parameter C_QCE_JOINED = 0; + parameter C_QUALIFY_WE = 0; + parameter C_READ_MIF = 0; + parameter C_REG_A_D_INPUTS = 0; + parameter C_REG_DPRA_INPUT = 0; + parameter C_SYNC_ENABLE = 0; + parameter C_WIDTH = 16; + parameter radix = C_DEFAULT_DATA_RADIX; + parameter pipe_stages = C_LATENCY-C_REG_A_D_INPUTS; + parameter dpo_pipe_stages = pipe_stages+1-C_HAS_QSPO; // replaced C_HAS_QDPO for 1 as this parameter is only valid when C_HAS_QDPO anyway + parameter C_RAM32_FIX = 0; // should not be passed in to simulation model + + parameter NCELAB_DPO_PIPE_CONSTANT = (dpo_pipe_stages < 2 ? 0 : 2); + parameter NCELAB_SPO_PIPE_CONSTANT = (pipe_stages < 2 ? 0 : 2); + + input [C_ADDR_WIDTH-1 - (C_ADDR_WIDTH>4?(4*C_HAS_SPRA):0) : 0] A; + input [C_WIDTH-1 : 0] D; + input [C_ADDR_WIDTH-1 : 0] DPRA; + input [C_ADDR_WIDTH-1 : 0] SPRA; + input CLK; + input WE; + input I_CE; + input RD_EN; + input QSPO_CE; + input QDPO_CE; + input QDPO_CLK; + input QSPO_RST; + input QDPO_RST; + input QSPO_SRST; + input QDPO_SRST; + output [C_WIDTH-1 : 0] SPO; + output [C_WIDTH-1 : 0] QSPO; + output [C_WIDTH-1 : 0] DPO; + output [C_WIDTH-1 : 0] QDPO; + + // Address signal connected to memory + wire [C_ADDR_WIDTH - 1 : 0] a_int; + // Read Address signal connected to srl16-based memory + wire [C_ADDR_WIDTH - 1 : 0] spra_int; + // Registered Address signal connected to memory + wire [C_ADDR_WIDTH - 1 : 0] a_int1; + // Registered Read Address signal connected to srl16-based memory + wire [C_ADDR_WIDTH - 1 : 0] spra_int1; + // DP port address signal connected to memory + wire [C_ADDR_WIDTH - 1 : 0] dpra_int; + // DP port address signal connected to memory + wire [C_ADDR_WIDTH - 1 : 0] dpra_int1; + // Input data signal connected to memory + wire [C_WIDTH - 1 : 0] d_int; + // Registered Input data signal connected to memory + wire [C_WIDTH - 1 : 0] d_int1; + // DP output register clock + wire doclk; + // Input data/address/WE register Clock Enable + wire ice; + // Special address register Clock Enable for ROMs + wire a_reg_ice; + // DP read address port register clock enable +// wire dpra_ce; + // WE wire connected to memory + wire we_int; + // Registered WE wire connected to memory + wire we_int1; + // Clock enable for the WE register + wire wece; + // Read Enable wire connected to BUFT-type output mux + wire re_int; + // Registered Read Enable wire connected to BUFT-type output mux + wire re_int1; + // unregistered version of qspo_ce + wire qspo_ce_int; + // possibly registered version of qspo_ce + wire qspo_ce_reg; + // registered version of qspo_ce + wire qspo_ce_reg1; + // unregistered version of qdpo_ce + wire qdpo_ce_int; + // possibly registered version of qdpo_ce + wire qdpo_ce_reg; + // registered version of qdpo_ce + wire qdpo_ce_reg1; + // possibly single port registered output reset + wire qspo_rst_int; + // possibly dual port registered output reset + wire qdpo_rst_int; + // possibly single port registered output sync reset + wire qspo_srst_int; + // possibly dual port registered output sync reset + wire qdpo_srst_int; + // Direct SP output from memory + reg [C_WIDTH - 1 : 0] spo_async; + // Direct DP output from memory + reg [C_WIDTH - 1 : 0] dpo_async; + // Possibly pipelined and/or registered SP output from memory + wire [C_WIDTH - 1 : 0] intQSPO; + // Possibly pipelined and/or registered DP output from memory + wire [C_WIDTH - 1 : 0] intQDPO; + // Pipeline signals + reg [C_WIDTH - 1 : 0] spo_pipe [pipe_stages+2 : 0]; + reg [C_WIDTH - 1 : 0] dpo_pipe [dpo_pipe_stages+2 : 0]; + // Possibly pipelined SP output from memory + reg [C_WIDTH - 1 : 0] spo_pipeend; + // Possibly pipelined DP output from memory + reg [C_WIDTH - 1 : 0] dpo_pipeend; + // BUFT outputs + wire [C_WIDTH - 1 : 0] spo_reg; + wire [C_WIDTH - 1 : 0] dpo_reg; + wire [C_WIDTH - 1 : 0] spo_reg_tmp; + wire [C_WIDTH - 1 : 0] dpo_reg_tmp; + + integer pipe, pipe1, pipe2, pipe3, pipe4, i, j, srl_start, srl_end; + + // Array to hold ram data + reg [C_WIDTH-1 : 0] ram_data [C_DEPTH-1 : 0]; + reg [C_WIDTH-1 : 0] tmp_data1; + reg [C_WIDTH-1 : 0] tmp_data2; + + reg [C_WIDTH-1 : 0] default_data; + reg [C_WIDTH-1 : 0] spo_tmp; + reg [C_WIDTH-1 : 0] dpo_tmp; + reg [C_WIDTH-1 : 0] tmp_pipe1; + reg [C_WIDTH-1 : 0] tmp_pipe2; + reg [C_WIDTH-1 : 0] tmp_pipe3; + reg lastCLK; + reg lastdoclk; + + reg start; + + function integer ADDR_IS_X; + input [C_ADDR_WIDTH-1 : 0] value; + integer i; + begin + ADDR_IS_X = 0; + for(i = 0; i < C_ADDR_WIDTH; i = i + 1) + if(value[i] === 1'bx) + ADDR_IS_X = 1; + end + endfunction + + // Deal with the optional output signals... + wire [C_WIDTH - 1 : 0] SPO = (C_HAS_SPO ? (C_MUX_TYPE == `c_lut_based ? spo_async : spo_reg) : `allXs); + wire [C_WIDTH - 1 : 0] DPO = (C_HAS_DPO && C_MEM_TYPE == `c_dp_ram ? (C_MUX_TYPE == `c_lut_based ? dpo_async : dpo_reg) : `allXs); + wire [C_WIDTH - 1 : 0] QSPO = (C_HAS_QSPO ? intQSPO : `allXs); + wire [C_WIDTH - 1 : 0] QDPO = (C_HAS_QDPO ? intQDPO : `allXs); + + // Deal with the optional input signals... + + assign ice = (C_HAS_I_CE == 1 ? I_CE : 1'b1); + assign a_reg_ice = (C_MEM_TYPE == `c_rom ? qspo_ce_int : ice); + assign wece = (C_HAS_WE == 1 && C_REG_A_D_INPUTS == 1 && C_QUALIFY_WE == 1 ? ice : 1'b1); +// assign dpra_ce = (C_HAS_QDPO_CE == 1 ? QDPO_CE : 1'b1); + assign doclk = (C_HAS_QDPO_CLK == 1 ? QDPO_CLK : CLK); + assign qspo_ce_int = (C_HAS_QSPO_CE == 1 ? QSPO_CE : 1'b1); + assign qdpo_ce_int = (C_QCE_JOINED == 1 ? qspo_ce_int : (C_HAS_QDPO_CE == 1 ? QDPO_CE : ((C_HAS_QSPO == 1 && C_MEM_TYPE == `c_srl16) ? qspo_ce_int : 1'b1))); + assign qspo_rst_int = (C_HAS_QSPO_RST && C_HAS_QSPO ? QSPO_RST : 1'b0); + assign qdpo_rst_int = (C_HAS_QDPO_RST && C_HAS_QDPO ? QDPO_RST : 1'b0); + assign qspo_srst_int = (C_HAS_QSPO_SRST && C_HAS_QSPO ? QSPO_SRST : 1'b0); + assign qdpo_srst_int = (C_HAS_QDPO_SRST && C_HAS_QDPO ? QDPO_SRST : 1'b0); + + // (Optional) registers on SP address and on optional data/we/qspo_ce signals + C_REG_FD_V7_0 #("0", C_ENABLE_RLOCS, 0, 0, 0, + 0, 0, 0, 0, + "0", 0, 0, 1) + qspo1_reg (.D(qspo_ce_int), .CLK(CLK), .CE(1'b0), .ACLR(1'b0), .ASET(1'b0), + .AINIT(1'b0), .SCLR(1'b0), .SSET(1'b0), .SINIT(1'b0), + .Q(qspo_ce_reg1)); + + C_REG_FD_V7_0 #("0", C_ENABLE_RLOCS, 0, 0, 0, + 1, 0, 0, 0, + "0", 0, 0, (C_ADDR_WIDTH-(C_ADDR_WIDTH>4?(C_HAS_SPRA*4):0))) + a_rega (.D(A[C_ADDR_WIDTH - 1-(C_ADDR_WIDTH>4?(4*C_HAS_SPRA):0) : 0]), .CLK(CLK), .CE(a_reg_ice), .ACLR(1'b0), .ASET(1'b0), + .AINIT(1'b0), .SCLR(1'b0), .SSET(1'b0), .SINIT(1'b0), + .Q(a_int1[C_ADDR_WIDTH - 1-(C_ADDR_WIDTH>4?(4*C_HAS_SPRA):0) : 0])); + + C_REG_FD_V7_0 #("0", C_ENABLE_RLOCS, 0, 0, 0, + 1, 0, 0, 0, + "0", 0, 0, C_ADDR_WIDTH) + spra_reg (.D(SPRA), .CLK(CLK), .CE(qspo_ce_int), .ACLR(1'b0), .ASET(1'b0), + .AINIT(1'b0), .SCLR(1'b0), .SSET(1'b0), .SINIT(1'b0), + .Q(spra_int1)); + + C_REG_FD_V7_0 #("0", C_ENABLE_RLOCS, 0, 0, 0, + 1, 0, 0, 0, + "0", 0, 0, 1) + we_reg (.D(WE), .CLK(CLK), .CE(wece), .ACLR(1'b0), .ASET(1'b0), + .AINIT(1'b0), .SCLR(1'b0), .SSET(1'b0), .SINIT(1'b0), + .Q(we_int1)); + + C_REG_FD_V7_0 #("0", C_ENABLE_RLOCS, 0, 0, 0, + 0, 0, 0, 0, + "0", 0, 0, 1) + re_reg (.D(RD_EN), .CLK(CLK),// .CE(qspo_ce_int), + .CE(1'b0), .ACLR(1'b0), .ASET(1'b0), + .AINIT(1'b0), .SCLR(1'b0), .SSET(1'b0), .SINIT(1'b0), + .Q(re_int1)); + + C_REG_FD_V7_0 #("0", C_ENABLE_RLOCS, 0, 0, 0, + 1, 0, 0, 0, + "0", 0, 0, C_WIDTH) + d_reg (.D(D), .CLK(CLK), .CE(ice), .ACLR(1'b0), .ASET(1'b0), + .AINIT(1'b0), .SCLR(1'b0), .SSET(1'b0), .SINIT(1'b0), + .Q(d_int1)); + + C_REG_FD_V7_0 #("0", C_ENABLE_RLOCS, 0, 0, 0, + 0, 0, 0, 0, + "0", 0, 0, C_WIDTH) + spo_reg1 (.D(spo_async), .CLK(CLK), .CE(1'b0), .ACLR(1'b0), .ASET(1'b0), + .AINIT(1'b0), .SCLR(1'b0), .SSET(1'b0), .SINIT(1'b0), + .Q(spo_reg_tmp)); + + C_REG_FD_V7_0 #("0", C_ENABLE_RLOCS, 0, 0, 0, + 0, 0, 0, 0, + "0", 0, 0, C_WIDTH) + dpo_reg1 (.D(dpo_async), .CLK(doclk), .CE(1'b0), .ACLR(1'b0), .ASET(1'b0), + .AINIT(1'b0), .SCLR(1'b0), .SSET(1'b0), .SINIT(1'b0), + .Q(dpo_reg_tmp)); + + // Deal with these optional registers + assign qspo_ce_reg = (C_REG_A_D_INPUTS == 0 ? (C_HAS_QSPO_CE == 1 ? qspo_ce_int : 1'b1) : (C_HAS_QSPO_CE == 1 ? qspo_ce_reg1 : 1'b1)); + assign a_int = (C_REG_A_D_INPUTS == 0 ? (C_MEM_TYPE != `c_srl16 ? A : (C_ADDR_WIDTH>4 ? A[C_ADDR_WIDTH - 1 -(C_ADDR_WIDTH>4?(4*C_HAS_SPRA):0) : 0]<<4 : 0)) : + (C_MEM_TYPE != `c_srl16 ? a_int1 : (C_ADDR_WIDTH>4 ? a_int1[C_ADDR_WIDTH - 1 -(C_ADDR_WIDTH>4?(4*C_HAS_SPRA):0) : 0]<<4 : 0))); + assign spra_int = (C_REG_A_D_INPUTS == 0 ? (C_MEM_TYPE != `c_srl16 ? A : SPRA) : + (C_MEM_TYPE != `c_srl16 ? a_int1 : spra_int1)); + assign we_int = (C_REG_A_D_INPUTS == 0 ? (C_HAS_WE == 1 ? WE : 1'b1) : (C_HAS_WE == 1 ? we_int1 : 1'b1)); + assign re_int = (C_REG_A_D_INPUTS == 0 ? (C_HAS_RD_EN == 1 ? RD_EN : 1'b1) : (C_HAS_RD_EN == 1 ? re_int1 : 1'b1)); + assign d_int = (C_REG_A_D_INPUTS == 0 ? (C_HAS_D == 1 ? D : `allXs) : (C_HAS_D == 1 ? d_int1 : `allXs)); + assign spo_reg = (pipe_stages == 1 ? spo_reg_tmp : spo_async); + assign dpo_reg = (pipe_stages == 1 ? dpo_reg_tmp : dpo_async); + + // (Optional) DP Read Address and QDPO_CE registers + + C_REG_FD_V7_0 #("0", C_ENABLE_RLOCS, 0, 0, 0, + 1, 0, 0, 0, + "0", 0, 0, C_ADDR_WIDTH) + dpra_reg (.D(DPRA), .CLK(doclk), .CE(qdpo_ce_int), .ACLR(1'b0), .ASET(1'b0), + .AINIT(1'b0), .SCLR(1'b0), .SSET(1'b0), .SINIT(1'b0), + .Q(dpra_int1)); + + C_REG_FD_V7_0 #("0", C_ENABLE_RLOCS, 0, 0, 0, + 0, 0, 0, 0, + "0", 0, 0, 1) + qdpo1_reg (.D(qdpo_ce_int), .CLK(doclk), .CE(1'b0), .ACLR(1'b0), .ASET(1'b0), + .AINIT(1'b0), .SCLR(1'b0), .SSET(1'b0), .SINIT(1'b0), + .Q(qdpo_ce_reg1)); + + // Deal with these optional registers + assign qdpo_ce_reg = (C_REG_DPRA_INPUT == 0 ? (C_HAS_QDPO_CE == 1 ? qdpo_ce_int : (C_QCE_JOINED == 1 ? qdpo_ce_int : 1'b1)) : + (C_HAS_QDPO_CE == 1 ? qdpo_ce_reg1 : (C_QCE_JOINED == 1 || C_MEM_TYPE == `c_srl16 ? qdpo_ce_reg1 : 1'b1))); + assign dpra_int = (C_REG_DPRA_INPUT == 0 ? (C_HAS_DPRA == 1 ? DPRA : `allXs) : (C_HAS_DPRA == 1 ? dpra_int1 : `allXs)); + + // (Optional) pipeline registers + + always@(posedge CLK) + begin + if(CLK === 1'b1 && lastCLK === 1'b0 && qspo_ce_reg === 1'b1) // OK! Update pipelines! + begin + for(pipe = 2; pipe <= pipe_stages-1; pipe = pipe + 1) + begin + spo_pipe[pipe] <= spo_pipe[pipe+1]; + end + spo_pipe[pipe_stages] <= spo_async; + end + else if((CLK === 1'bx && lastCLK === 1'b0) || (CLK === 1'b1 && lastCLK === 1'bx) || qspo_ce_reg === 1'bx) // POSSIBLY Update pipelines! + begin + for(pipe = 2; pipe <= pipe_stages-1; pipe = pipe + 1) + begin + tmp_pipe1 = spo_pipe[pipe]; + tmp_pipe2 = spo_pipe[pipe+1]; + for(pipe1 = 0; pipe1 < C_WIDTH; pipe1 = pipe1 + 1) + begin + if(tmp_pipe1[pipe1] !== tmp_pipe2[pipe1]) + tmp_pipe1[pipe1] = 1'bx; + end + spo_pipe[pipe] <= tmp_pipe1; + end + tmp_pipe1 = spo_pipe[pipe_stages]; + for(pipe1 = 0; pipe1 < C_WIDTH; pipe1 = pipe1 + 1) + begin + if(tmp_pipe1[pipe1] !== spo_async[pipe1]) + tmp_pipe1[pipe1] = 1'bx; + end + spo_pipe[pipe_stages] <= tmp_pipe1; + end + end + + always@(spo_async or spo_pipe[NCELAB_SPO_PIPE_CONSTANT]) //2 + begin + if(pipe_stages < 2) // No pipeline + spo_pipeend <= spo_async; + else // Pipeline stages required + begin + spo_pipeend <= spo_pipe[NCELAB_SPO_PIPE_CONSTANT]; //2 + end + end + + always@(posedge doclk) + begin + if(doclk === 1'b1 && lastdoclk === 1'b0 && qdpo_ce_reg === 1'b1) // OK! Update pipelines! + begin + for(pipe3 = 2; pipe3 <= dpo_pipe_stages-1; pipe3 = pipe3 + 1) + begin + dpo_pipe[pipe3] <= dpo_pipe[pipe3+1]; + end + dpo_pipe[dpo_pipe_stages] <= dpo_async; + end + else if((doclk === 1'bx && lastdoclk === 1'b0) || (doclk === 1'b1 && lastdoclk === 1'bx) || qdpo_ce_reg === 1'bx) // POSSIBLY Update pipelines! + begin + for(pipe4 = 2; pipe4 <= dpo_pipe_stages-1; pipe4 = pipe4 + 1) + begin + tmp_pipe3 = dpo_pipe[pipe4]; + tmp_pipe2 = dpo_pipe[pipe4+1]; + for(pipe1 = 0; pipe1 < C_WIDTH; pipe1 = pipe1 + 1) + begin + if(tmp_pipe3[pipe1] !== tmp_pipe2[pipe1]) + tmp_pipe3[pipe1] = 1'bx; + end + dpo_pipe[pipe4] <= tmp_pipe3; + end + tmp_pipe3 = dpo_pipe[dpo_pipe_stages]; + for(pipe2 = 0; pipe2 < C_WIDTH; pipe2 = pipe2 + 1) + begin + if(tmp_pipe3[pipe2] !== dpo_async[pipe2]) + tmp_pipe3[pipe2] = 1'bx; + end + dpo_pipe[dpo_pipe_stages] <= tmp_pipe3; + end + end + + always@(dpo_async or dpo_pipe[NCELAB_DPO_PIPE_CONSTANT]) //2 + begin + if(dpo_pipe_stages < 2) // No pipeline + dpo_pipeend <= dpo_async; + else // Pipeline stages required + begin + dpo_pipeend <= dpo_pipe[NCELAB_DPO_PIPE_CONSTANT]; //2 + end + end + + // (Optional) output registers at end of optional pipelines + + C_REG_FD_V7_0 #("0", C_ENABLE_RLOCS, C_HAS_QSPO_RST, 0, 0, + 1, C_HAS_QSPO_SRST, 0, 0, + "0", C_SYNC_ENABLE, 0, C_WIDTH) + qspo_reg (.D(spo_pipeend), .CLK(CLK), .CE(qspo_ce_reg), .ASET(1'b0), + .AINIT(1'b0), .SSET(1'b0), .SINIT(1'b0), + .ACLR(qspo_rst_int), .SCLR(qspo_srst_int), .Q(intQSPO)); + + C_REG_FD_V7_0 #("0", C_ENABLE_RLOCS, C_HAS_QDPO_RST, 0, 0, + 1, C_HAS_QDPO_SRST, 0, 0, + "0", C_SYNC_ENABLE, 0, C_WIDTH) + qdpo_reg (.D(dpo_pipeend), .CLK(doclk), .CE(qdpo_ce_reg), .ASET(1'b0), + .AINIT(1'b0), .SSET(1'b0), .SINIT(1'b0), + .ACLR(qdpo_rst_int), .SCLR(qdpo_srst_int), .Q(intQDPO)); + + + + // Startup behaviour + initial + begin + default_data = 'b0; + case (radix) + 3 : default_data = decstr_conv(C_DEFAULT_DATA); + 2 : default_data = binstr_conv(C_DEFAULT_DATA); + 1 : default_data = hexstr_conv(C_DEFAULT_DATA); + default : $display("ERROR in %m at %d ns: BAD DATA RADIX - valid range 1 to 3", $time); + endcase + + for(i = 0; i < C_DEPTH; i = i + 1) + ram_data[i] = default_data; + + if(C_READ_MIF == 1) + begin + $readmemb(C_MEM_INIT_FILE, ram_data, 0 , C_DEPTH-1); + end + if (C_GENERATE_MIF == 1) + write_meminit_file; + + spo_tmp = 'b0; + dpo_tmp = 'b0; + lastCLK = 1'b0; + lastdoclk = 1'b0; + + spo_async = spo_tmp; + dpo_async = dpo_tmp; + + for(i = 0; i < pipe_stages+3; i = i + 1) + begin + spo_pipe[i] = `all0s; + end + for(i = 0; i < dpo_pipe_stages+3; i = i + 1) + begin + dpo_pipe[i] = `all0s; + end + if(pipe_stages < 2) // No pipeline + begin + spo_pipeend = spo_async; + end + else + begin + spo_pipeend = spo_pipe[NCELAB_SPO_PIPE_CONSTANT]; //2 + end + if(dpo_pipe_stages < 2) // No pipeline + begin + dpo_pipeend = dpo_async; + end + else + begin + dpo_pipeend = dpo_pipe[NCELAB_DPO_PIPE_CONSTANT]; //2 + end + + start <= 0; + end + + always @(CLK) + lastCLK <= CLK; + + always @(doclk) + lastdoclk <= doclk; + + always @(posedge CLK or a_int or we_int or spra_int or dpra_int or d_int or re_int or spo_async or dpo_async or start) + begin + if ($realtime != 0 || start == 0) // gets around race condition at startup (CR 171445) + // added start to ensure that this process is still run at startup + // but after all the intials have completed to fix CR 175826 + begin + if(((CLK === 1'b1 && lastCLK === 1'b0) || C_HAS_CLK == 0) && C_MEM_TYPE != `c_rom) + begin + if(ADDR_IS_X(a_int) || a_int < C_DEPTH) + begin + if(we_int === 1'bx) + begin + if(ADDR_IS_X(a_int)) + begin + for(i = 0; i < C_DEPTH; i = i + 1) + ram_data[i] = `allXs; + end + else + begin + if(C_MEM_TYPE == `c_srl16) + begin + srl_start = (a_int/16)*16; // Ignore lower 4 bits of a_int + srl_end = srl_start+16; + if(srl_end > C_DEPTH) + srl_end = C_DEPTH; + for(i = srl_end-1; i > srl_start; i = i - 1) + begin // Shift data through the SRL16s + tmp_data1 = ram_data[i]; + tmp_data2 = ram_data[i-1]; + for(j = 0; j < C_WIDTH; j = j + 1) + begin + if(tmp_data1[j] !== tmp_data2[j]) + tmp_data1[j] = 1'bx; + end + ram_data[i] = tmp_data1; + end + tmp_data1 = ram_data[srl_start]; + for(j = 0; j < C_WIDTH; j = j + 1) + begin + if(tmp_data1[j] !== d_int[j]) + tmp_data1[j] = 1'bx; + end + ram_data[srl_start] = tmp_data1; + end + else + begin + tmp_data1 = ram_data[a_int]; + for(j = 0; j < C_WIDTH; j = j + 1) + begin + if(tmp_data1[j] !== d_int[j]) + tmp_data1[j] = 1'bx; + end + ram_data[a_int] = tmp_data1; + end + end + end + else if(we_int === 1'b1) + begin + if(ADDR_IS_X(a_int)) + begin + for(i = 0; i < C_DEPTH; i = i + 1) + ram_data[i] = `allXs; + end + else + begin + if(C_MEM_TYPE == `c_srl16) + begin + srl_start = (a_int/16)*16; // Ignore lower 4 bits of a_int + srl_end = srl_start+16; + if(srl_end > C_DEPTH) + srl_end = C_DEPTH; + for(i = srl_end-1; i > srl_start; i = i - 1) + begin // Shift data through the SRL16s + ram_data[i] = ram_data[i-1]; + end + ram_data[srl_start] = d_int; + end + else + begin + //if (C_MEM_TYPE == `c_dp_ram && a_int == dpra_int && we_int == 1 && qspo_ce_int == 1) + //begin + // $display("WARNING in %m at time %d ns: Memory Hazard: Reading and Writing to same dual port address!", $time); + //end + ram_data[a_int] = d_int; + end + end + end + end + else if(a_int >= C_DEPTH) + $display("WARNING in %m at time %d ns: Writing to out-of-range address!! - max address is %d", $time, C_DEPTH); + end + else if((C_HAS_CLK == 0 || ((CLK === 1'bx && lastCLK === 1'b0) || CLK === 1'b1 && lastCLK === 1'bx)) && C_MEM_TYPE != `c_rom) + begin + if(ADDR_IS_X(a_int) || a_int < C_DEPTH) + begin + if(we_int === 1'bx) + begin + if(ADDR_IS_X(a_int)) + begin + for(i = 0; i < C_DEPTH; i = i + 1) + ram_data[i] = `allXs; + end + else + begin + if(C_MEM_TYPE == `c_srl16) + begin + srl_start = (a_int/16)*16; // Ignore lower 4 bits of a_int + srl_end = srl_start+16; + if(srl_end > C_DEPTH) + srl_end = C_DEPTH; + for(i = srl_end-1; i > srl_start; i = i - 1) + begin // Shift data through the SRL16s + tmp_data1 = ram_data[i]; + tmp_data2 = ram_data[i-1]; + for(j = 0; j < C_WIDTH; j = j + 1) + begin + if(tmp_data1[j] !== tmp_data2[j]) + tmp_data1[j] = 1'bx; + end + ram_data[i] = tmp_data1; + end + tmp_data1 = ram_data[srl_start]; + for(j = 0; j < C_WIDTH; j = j + 1) + begin + if(tmp_data1[j] !== d_int[j]) + tmp_data1[j] = 1'bx; + end + ram_data[srl_start] = tmp_data1; + end + else + begin + tmp_data1 = ram_data[a_int]; + for(j = 0; j < C_WIDTH; j = j + 1) + begin + if(tmp_data1[j] !== d_int[j]) + tmp_data1[j] = 1'bx; + end + ram_data[a_int] = tmp_data1; + end + end + end + else if(we_int === 1'b1) + begin + if(ADDR_IS_X(a_int)) + begin + for(i = 0; i < C_DEPTH; i = i + 1) + ram_data[i] = `allXs; + end + else + begin + if(C_MEM_TYPE == `c_srl16) + begin + srl_start = (a_int/16)*16; // Ignore lower 4 bits of a_int + srl_end = srl_start+16; + if(srl_end > C_DEPTH) + srl_end = C_DEPTH; + for(i = srl_end-1; i > srl_start; i = i - 1) + begin // Shift data through the SRL16s + tmp_data1 = ram_data[i]; + tmp_data2 = ram_data[i-1]; + for(j = 0; j < C_WIDTH; j = j + 1) + begin + if(tmp_data1[j] !== tmp_data2[j]) + tmp_data1[j] = 1'bx; + end + ram_data[i] = tmp_data1; + end + tmp_data1 = ram_data[srl_start]; + for(j = 0; j < C_WIDTH; j = j + 1) + begin + if(tmp_data1[j] !== d_int[j]) + tmp_data1[j] = 1'bx; + end + ram_data[srl_start] = tmp_data1; + end + else + begin + //if (C_MEM_TYPE == `c_dp_ram && a_int == dpra_int && we_int == 1 && qspo_ce_int == 1) + //begin + // $display("WARNING in %m at time %d ns: Memory Hazard: Reading and Writing to same dual port address!", $time); + //end + tmp_data1 = ram_data[a_int]; + for(j = 0; j < C_WIDTH; j = j + 1) + begin + if(tmp_data1[j] !== d_int[j]) + tmp_data1[j] = 1'bx; + end + ram_data[a_int] = tmp_data1; + end + end + end + end + else if(a_int >= C_DEPTH) + $display("WARNING in %m at time %d ns: Writing to out-of-range address!! - max address is %d", $time, C_DEPTH); + end + + // Read behaviour + + if(re_int === 1'bx) + begin + spo_tmp = `allXs; + dpo_tmp = `allXs; + end + else if(re_int === 1'b1) + begin + if(ADDR_IS_X(spra_int)) + spo_tmp = `allXs; + else + begin + if(spra_int < C_DEPTH) + spo_tmp = ram_data[spra_int]; + else if(C_MUX_TYPE == `c_buft_based) + begin + $display("WARNING in %m at time %d ns: Reading from out-of-range address!! - max address is %d", $time, C_DEPTH); + spo_tmp = `allZs; + end + else + begin + $display("WARNING in %m at time %d ns: Reading from out-of-range address!! - max address is %d", $time, C_DEPTH); + spo_tmp = `all0s; + end + end + + if(ADDR_IS_X(dpra_int)) + dpo_tmp = `allXs; + else + begin + if(dpra_int < C_DEPTH) + dpo_tmp = ram_data[dpra_int]; + else if(C_MUX_TYPE == `c_buft_based) + begin + $display("WARNING in %m at time %d ns: Reading from out-of-range address!! - max address is %d", $time, C_DEPTH); + dpo_tmp = `allZs; + end + else + begin + $display("WARNING in %m at time %d ns: Reading from out-of-range address!! - max address is %d", $time, C_DEPTH); + dpo_tmp = `all0s; + end + end + end + else // re_int == 0 + begin + spo_tmp = `all1s; + dpo_tmp = `all1s; + end + + spo_async <= spo_tmp; + dpo_async <= dpo_tmp; + end + + end + + + function [C_WIDTH-1:0] binstr_conv; + input [(C_WIDTH*8)-1:0] def_data; + + integer index,i; + + begin + index = 0; + binstr_conv = 'b0; + + for( i=C_WIDTH-1; i>=0; i=i-1 ) + begin + case (def_data[7:0]) + 8'b00000000 : i = -1; + 8'b00110000 : binstr_conv[index] = 1'b0; + 8'b00110001 : binstr_conv[index] = 1'b1; + default : + begin + $display("ERROR in %m at time %d ns: NOT A BINARY CHARACTER", $time); + binstr_conv[index] = 1'bx; + end + endcase + index = index + 1; + def_data = def_data >> 8; + end + end + endfunction + + function [C_WIDTH-1:0] hexstr_conv; + input [(C_WIDTH*8)-1:0] def_data; + + integer index,i,j; + reg [3:0] bin; + + begin + index = 0; + hexstr_conv = 'b0; + for( i=C_WIDTH-1; i>=0; i=i-1 ) + begin + case (def_data[7:0]) + 8'b00000000 : + begin + bin = 4'b0000; + i = -1; + end + 8'b00110000 : bin = 4'b0000; + 8'b00110001 : bin = 4'b0001; + 8'b00110010 : bin = 4'b0010; + 8'b00110011 : bin = 4'b0011; + 8'b00110100 : bin = 4'b0100; + 8'b00110101 : bin = 4'b0101; + 8'b00110110 : bin = 4'b0110; + 8'b00110111 : bin = 4'b0111; + 8'b00111000 : bin = 4'b1000; + 8'b00111001 : bin = 4'b1001; + 8'b01000001 : bin = 4'b1010; + 8'b01000010 : bin = 4'b1011; + 8'b01000011 : bin = 4'b1100; + 8'b01000100 : bin = 4'b1101; + 8'b01000101 : bin = 4'b1110; + 8'b01000110 : bin = 4'b1111; + 8'b01100001 : bin = 4'b1010; + 8'b01100010 : bin = 4'b1011; + 8'b01100011 : bin = 4'b1100; + 8'b01100100 : bin = 4'b1101; + 8'b01100101 : bin = 4'b1110; + 8'b01100110 : bin = 4'b1111; + default : + begin + $display("ERROR in %m at time %d ns: NOT A HEX CHARACTER", $time); + bin = 4'bx; + end + endcase + for( j=0; j<4; j=j+1) + begin + if ((index*4)+j < C_WIDTH) + begin + hexstr_conv[(index*4)+j] = bin[j]; + end + end + index = index + 1; + def_data = def_data >> 8; + end + end + endfunction + + function [C_WIDTH-1:0] decstr_conv; + input [(C_WIDTH*8)-1:0] def_data; + + integer index,i,j,ten; + reg [3:0] bin; + reg [C_WIDTH-1:0] temp, result; + + begin + index = 0; + decstr_conv = 'b0; + result = 'b0; + for( i=0; i> 8; + end + end + endfunction + + task write_meminit_file; + + integer addrs, outfile, bit_index; + + reg [C_WIDTH-1 : 0] conts; + reg anyX; + + begin + outfile = $fopen(C_MEM_INIT_FILE); + for( addrs = 0; addrs < C_DEPTH; addrs=addrs+1) + begin + anyX = 1'b0; + conts = ram_data[addrs]; + for(bit_index = 0; bit_index < C_WIDTH; bit_index=bit_index+1) + if(conts[bit_index] === 1'bx) anyX = 1'b1; + if(anyX == 1'b1) + $display("ERROR in %m at time %d ns: MEMORY CONTAINS UNKNOWNS", $time); + $fdisplay(outfile,"%b",ram_data[addrs]); + end + $fclose(outfile); + end + endtask + +endmodule + +`undef all0s +`undef all1s +`undef allXs +`undef allZs +`undef addrallXs + +`undef c_rom +`undef c_sp_ram +`undef c_dp_ram +`undef c_srl16 + +`undef c_lut_based +`undef c_buft_based + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/C_GATE_BIT_BUS_V4_0.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/C_GATE_BIT_BUS_V4_0.v new file mode 100644 index 0000000..abdae98 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/C_GATE_BIT_BUS_V4_0.v @@ -0,0 +1,538 @@ +/* $Id: C_GATE_BIT_BUS_V4_0.v,v 1.11 2008/09/08 20:05:46 akennedy Exp $ +-- +-- Filename - C_GATE_BIT_BUS_V4_0.v +-- Author - Xilinx +-- Creation - 25 Jan 1999 +-- +-- Description - This file contains the Verilog behavior for the Baseblocks C_GATE_BIT_BUS_V4_0 module +*/ + + + +`define c_set 0 +`define c_clear 1 +`define c_override 0 +`define c_no_override 1 +`define c_and 0 +`define c_nand 1 +`define c_or 2 +`define c_nor 3 +`define c_xor 4 +`define c_xnor 5 + +module C_GATE_BIT_BUS_V4_0 (I, CTRL, CLK, CE, ACLR, ASET, AINIT, SCLR, SSET, SINIT, O, Q); + + parameter C_AINIT_VAL = ""; + parameter C_ENABLE_RLOCS = 1; + parameter C_GATE_TYPE = `c_and; + parameter C_HAS_ACLR = 0; + parameter C_HAS_AINIT = 0; + parameter C_HAS_ASET = 0; + parameter C_HAS_CE = 0; + parameter C_HAS_O = 0; + parameter C_HAS_Q = 1; + parameter C_HAS_SCLR = 0; + parameter C_HAS_SINIT = 0; + parameter C_HAS_SSET = 0; + parameter C_INPUT_INV_MASK = ""; + parameter C_SINIT_VAL = ""; + parameter C_SYNC_ENABLE = `c_override; + parameter C_SYNC_PRIORITY = `c_clear; + parameter C_WIDTH = 16; + + + input [C_WIDTH-1 : 0] I; + input CTRL; + input CLK; + input CE; + input ACLR; + input ASET; + input AINIT; + input SCLR; + input SSET; + input SINIT; + output [C_WIDTH-1 : 0] O; + output [C_WIDTH-1 : 0] Q; + + reg [C_WIDTH-1 : 0] intO; + wire [C_WIDTH-1 : 0] intQ; + + wire [C_WIDTH-1 : 0] Q = (C_HAS_Q == 1 ? intQ : {C_WIDTH{1'bx}}); + wire [C_WIDTH-1 : 0] O = (C_HAS_O == 1 ? intO : {C_WIDTH{1'bx}}); + + + integer j; + + reg [C_WIDTH-1 : 0] tmpsig; + reg [C_WIDTH-1 : 0] tmpres; + + // Output register + C_REG_FD_V4_0 #(C_AINIT_VAL, C_ENABLE_RLOCS, C_HAS_ACLR, C_HAS_AINIT, C_HAS_ASET, + C_HAS_CE, C_HAS_SCLR, C_HAS_SINIT, C_HAS_SSET, + C_SINIT_VAL, C_SYNC_ENABLE, C_SYNC_PRIORITY, C_WIDTH) + reg1 (.D(intO), .CLK(CLK), .CE(CE), .ACLR(ACLR), .ASET(ASET), + .AINIT(AINIT), .SCLR(SCLR), .SSET(SSET), .SINIT(SINIT), + .Q(intQ)); + + initial + begin + #1; + + tmpsig = to_bits(C_INPUT_INV_MASK); + if(CTRL === 1'bx) + begin + for(j = 0; j < C_WIDTH; j = j + 1) + begin + if(tmpsig[j] == 1) // Inversion of input bit + begin + if(C_GATE_TYPE == 0) // AND gate + begin + if(I[j] === 1'b1) + tmpres[j] = 1'b0; + else + tmpres[j] = 1'bx; + end + else if(C_GATE_TYPE == 1) // NAND gate + begin + if(I[j] === 1'b1) + tmpres[j] = 1'b1; + else + tmpres[j] = 1'bx; + end + else if(C_GATE_TYPE == 2) // OR gate + begin + if(I[j] === 1'b0) + tmpres[j] = 1'b1; + else + tmpres[j] = 1'bx; + end + else if(C_GATE_TYPE == 3) // NOR gate + begin + if(I[j] === 1'b0) + tmpres[j] = 1'b0; + else + tmpres[j] = 1'bx; + end + else if(C_GATE_TYPE == 4) // XOR gate + tmpres[j] = 1'bx; + else if(C_GATE_TYPE == 5) // XNOR gate + tmpres[j] = 1'bx; + end + else // No input inversion on bit j of input + begin + if(C_GATE_TYPE == 0) // AND gate + begin + if(I[j] === 1'b0) + tmpres[j] = 1'b0; + else + tmpres[j] = 1'bx; + end + else if(C_GATE_TYPE == 1) // NAND gate + begin + if(I[j] === 1'b0) + tmpres[j] = 1'b1; + else + tmpres[j] = 1'bx; + end + else if(C_GATE_TYPE == 2) // OR gate + begin + if(I[j] === 1'b1) + tmpres[j] = 1'b1; + else + tmpres[j] = 1'bx; + end + else if(C_GATE_TYPE == 3) // NOR gate + begin + if(I[j] === 1'b1) + tmpres[j] = 1'b0; + else + tmpres[j] = 1'bx; + end + else if(C_GATE_TYPE == 4) // XOR gate + tmpres[j] = 1'bx; + else if(C_GATE_TYPE == 5) // XNOR gate + tmpres[j] = 1'bx; + end + end + end + else // CTRL is not unknown + begin + for(j = 0; j < C_WIDTH; j = j + 1) + begin + if(tmpsig[j] == 1) + begin + if(C_GATE_TYPE == 0) // AND gate + begin + if(I[j] !== 1'bx) + tmpres[j] = CTRL & ~I[j]; + else if(CTRL === 1'b0) + tmpres[j] = 1'b0; + else + tmpres[j] = 1'bx; + end + else if(C_GATE_TYPE == 1) // NAND gate + begin + if(I[j] !== 1'bx) + tmpres[j] = ~(CTRL & ~I[j]); + else if(CTRL === 1'b0) + tmpres[j] = 1'b1; + else + tmpres[j] = 1'bx; + end + else if(C_GATE_TYPE == 2) // OR gate + begin + if(I[j] !== 1'bx) + tmpres[j] = CTRL | ~I[j]; + else if(CTRL === 1'b1) + tmpres[j] = 1'b1; + else + tmpres[j] = 1'bx; + end + else if(C_GATE_TYPE == 3) // NOR gate + begin + if(I[j] !== 1'bx) + tmpres[j] = ~(CTRL | ~I[j]); + else if(CTRL === 1'b1) + tmpres[j] = 1'b0; + else + tmpres[j] = 1'bx; + end + else if(C_GATE_TYPE == 4) // XOR gate + begin + if(I[j] !== 1'bx) + tmpres[j] = CTRL ^ ~I[j]; + else + tmpres[j] = 1'bx; + end + else if(C_GATE_TYPE == 5) // XNOR gate + begin + if(I[j] !== 1'bx) + tmpres[j] = ~(CTRL ^ ~I[j]); + else + tmpres[j] = 1'bx; + end + end + else // No input inversion on bit j of input + begin + if(C_GATE_TYPE == 0) // AND gate + begin + if(I[j] !== 1'bx) + tmpres[j] = CTRL & I[j]; + else if(CTRL === 1'b0) + tmpres[j] = 1'b0; + else + tmpres[j] = 1'bx; + end + else if(C_GATE_TYPE == 1) // NAND gate + begin + if(I[j] !== 1'bx) + tmpres[j] = ~(CTRL & I[j]); + else if(CTRL === 1'b0) + tmpres[j] = 1'b0; + else + tmpres[j] = 1'bx; + end + else if(C_GATE_TYPE == 2) // OR gate + begin + if(I[j] !== 1'bx) + tmpres[j] = CTRL | I[j]; + else if(CTRL === 1'b1) + tmpres[j] = 1'b1; + else + tmpres[j] = 1'bx; + end + else if(C_GATE_TYPE == 3) // NOR gate + begin + if(I[j] !== 1'bx) + tmpres[j] = ~(CTRL | I[j]); + else if(CTRL === 1'b1) + tmpres[j] = 1'b1; + else + tmpres[j] = 1'bx; + end + else if(C_GATE_TYPE == 4) // XOR gate + begin + if(I[j] !== 1'bx) + tmpres[j] = CTRL ^ I[j]; + else + tmpres[j] = 1'bx; + end + else if(C_GATE_TYPE == 5) // XNOR gate + begin + if(I[j] !== 1'bx) + tmpres[j] = ~(CTRL ^ I[j]); + else + tmpres[j] = 1'bx; + end + end + end + end + + intO <= tmpres; + end + + always@(I or CTRL) + begin + + if(CTRL === 1'bx) + begin + for(j = 0; j < C_WIDTH; j = j + 1) + begin + if(tmpsig[j] == 1) // Inversion of input bit + begin + if(C_GATE_TYPE == 0) // AND gate + begin + if(I[j] === 1'b1) + tmpres[j] = 1'b0; + else + tmpres[j] = 1'bx; + end + else if(C_GATE_TYPE == 1) // NAND gate + begin + if(I[j] === 1'b1) + tmpres[j] = 1'b1; + else + tmpres[j] = 1'bx; + end + else if(C_GATE_TYPE == 2) // OR gate + begin + if(I[j] === 1'b0) + tmpres[j] = 1'b1; + else + tmpres[j] = 1'bx; + end + else if(C_GATE_TYPE == 3) // NOR gate + begin + if(I[j] === 1'b0) + tmpres[j] = 1'b0; + else + tmpres[j] = 1'bx; + end + else if(C_GATE_TYPE == 4) // XOR gate + tmpres[j] = 1'bx; + else if(C_GATE_TYPE == 5) // XNOR gate + tmpres[j] = 1'bx; + end + else // No input inversion on bit j of input + begin + if(C_GATE_TYPE == 0) // AND gate + begin + if(I[j] === 1'b0) + tmpres[j] = 1'b0; + else + tmpres[j] = 1'bx; + end + else if(C_GATE_TYPE == 1) // NAND gate + begin + if(I[j] === 1'b0) + tmpres[j] = 1'b1; + else + tmpres[j] = 1'bx; + end + else if(C_GATE_TYPE == 2) // OR gate + begin + if(I[j] === 1'b1) + tmpres[j] = 1'b1; + else + tmpres[j] = 1'bx; + end + else if(C_GATE_TYPE == 3) // NOR gate + begin + if(I[j] === 1'b1) + tmpres[j] = 1'b0; + else + tmpres[j] = 1'bx; + end + else if(C_GATE_TYPE == 4) // XOR gate + tmpres[j] = 1'bx; + else if(C_GATE_TYPE == 5) // XNOR gate + tmpres[j] = 1'bx; + end + end + end + else // CTRL is not unknown + begin + for(j = 0; j < C_WIDTH; j = j + 1) + begin + if(tmpsig[j] == 1) + begin + if(C_GATE_TYPE == 0) // AND gate + begin + if(I[j] !== 1'bx) + tmpres[j] = CTRL & ~I[j]; + else if(CTRL === 1'b0) + tmpres[j] = 1'b0; + else + tmpres[j] = 1'bx; + end + else if(C_GATE_TYPE == 1) // NAND gate + begin + if(I[j] !== 1'bx) + tmpres[j] = ~(CTRL & ~I[j]); + else if(CTRL === 1'b0) + tmpres[j] = 1'b1; + else + tmpres[j] = 1'bx; + end + else if(C_GATE_TYPE == 2) // OR gate + begin + if(I[j] !== 1'bx) + tmpres[j] = CTRL | ~I[j]; + else if(CTRL === 1'b1) + tmpres[j] = 1'b1; + else + tmpres[j] = 1'bx; + end + else if(C_GATE_TYPE == 3) // NOR gate + begin + if(I[j] !== 1'bx) + tmpres[j] = ~(CTRL | ~I[j]); + else if(CTRL === 1'b1) + tmpres[j] = 1'b0; + else + tmpres[j] = 1'bx; + end + else if(C_GATE_TYPE == 4) // XOR gate + begin + if(I[j] !== 1'bx) + tmpres[j] = CTRL ^ ~I[j]; + else + tmpres[j] = 1'bx; + end + else if(C_GATE_TYPE == 5) // XNOR gate + begin + if(I[j] !== 1'bx) + tmpres[j] = ~(CTRL ^ ~I[j]); + else + tmpres[j] = 1'bx; + end + end + else // No input inversion on bit j of input + begin + if(C_GATE_TYPE == 0) // AND gate + begin + if(I[j] !== 1'bx) + tmpres[j] = CTRL & I[j]; + else if(CTRL === 1'b0) + tmpres[j] = 1'b0; + else + tmpres[j] = 1'bx; + end + else if(C_GATE_TYPE == 1) // NAND gate + begin + if(I[j] !== 1'bx) + tmpres[j] = ~(CTRL & I[j]); + else if(CTRL === 1'b0) + tmpres[j] = 1'b0; + else + tmpres[j] = 1'bx; + end + else if(C_GATE_TYPE == 2) // OR gate + begin + if(I[j] !== 1'bx) + tmpres[j] = CTRL | I[j]; + else if(CTRL === 1'b1) + tmpres[j] = 1'b1; + else + tmpres[j] = 1'bx; + end + else if(C_GATE_TYPE == 3) // NOR gate + begin + if(I[j] !== 1'bx) + tmpres[j] = ~(CTRL | I[j]); + else if(CTRL === 1'b1) + tmpres[j] = 1'b1; + else + tmpres[j] = 1'bx; + end + else if(C_GATE_TYPE == 4) // XOR gate + begin + if(I[j] !== 1'bx) + tmpres[j] = CTRL ^ I[j]; + else + tmpres[j] = 1'bx; + end + else if(C_GATE_TYPE == 5) // XNOR gate + begin + if(I[j] !== 1'bx) + tmpres[j] = ~(CTRL ^ I[j]); + else + tmpres[j] = 1'bx; + end + end + end + end + + intO <= #1 tmpres; + end + + function defval; + input i; + input hassig; + input val; + begin + if(hassig == 1) + defval = i; + else + defval = val; + end + endfunction + + function [C_WIDTH - 1 : 0] to_bits; + input [C_WIDTH*8 : 1] instring; + integer i; + begin + for(i = C_WIDTH; i > 0; i = i - 1) + begin // Is this character a '0'? (ASCII = 48 = 00110000) + if(instring[(i*8)] == 0 && + instring[(i*8)-1] == 0 && + instring[(i*8)-2] == 1 && + instring[(i*8)-3] == 1 && + instring[(i*8)-4] == 0 && + instring[(i*8)-5] == 0 && + instring[(i*8)-6] == 0 && + instring[(i*8)-7] == 0) + to_bits[i-1] = 0; + // Or is it a '1'? + else if(instring[(i*8)] == 0 && + instring[(i*8)-1] == 0 && + instring[(i*8)-2] == 1 && + instring[(i*8)-3] == 1 && + instring[(i*8)-4] == 0 && + instring[(i*8)-5] == 0 && + instring[(i*8)-6] == 0 && + instring[(i*8)-7] == 1) + + to_bits[i-1] = 1; + // Or is it a ' '? (a null char - in which case insert a '0') + else if(instring[(i*8)] == 0 && + instring[(i*8)-1] == 0 && + instring[(i*8)-2] == 0 && + instring[(i*8)-3] == 0 && + instring[(i*8)-4] == 0 && + instring[(i*8)-5] == 0 && + instring[(i*8)-6] == 0 && + instring[(i*8)-7] == 0) + to_bits[i-1] = 0; + else + begin + $display("Error: non-binary digit in string \"%s\"\nExiting simulation...", instring); + $finish; + end + end + end + endfunction + +endmodule + +`undef c_set +`undef c_clear +`undef c_override +`undef c_no_override +`undef c_and +`undef c_nand +`undef c_or +`undef c_nor +`undef c_xor +`undef c_xnor + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/C_GATE_BIT_BUS_V5_0.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/C_GATE_BIT_BUS_V5_0.v new file mode 100644 index 0000000..f44a3a9 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/C_GATE_BIT_BUS_V5_0.v @@ -0,0 +1,539 @@ +/* $Id: C_GATE_BIT_BUS_V5_0.v,v 1.17 2008/09/08 20:05:55 akennedy Exp $ +-- +-- Filename - C_GATE_BIT_BUS_V5_0.v +-- Author - Xilinx +-- Creation - 25 Jan 1999 +-- +-- Description - This file contains the Verilog behavior for the Baseblocks C_GATE_BIT_BUS_V5_0 module +*/ + +`timescale 1ns/10ps + +`define c_set 0 +`define c_clear 1 +`define c_override 0 +`define c_no_override 1 +`define c_and 0 +`define c_nand 1 +`define c_or 2 +`define c_nor 3 +`define c_xor 4 +`define c_xnor 5 + +module C_GATE_BIT_BUS_V5_0 (I, CTRL, CLK, CE, ACLR, ASET, AINIT, SCLR, SSET, SINIT, O, Q); + + parameter C_AINIT_VAL = ""; + parameter C_ENABLE_RLOCS = 1; + parameter C_GATE_TYPE = `c_and; + parameter C_HAS_ACLR = 0; + parameter C_HAS_AINIT = 0; + parameter C_HAS_ASET = 0; + parameter C_HAS_CE = 0; + parameter C_HAS_O = 0; + parameter C_HAS_Q = 1; + parameter C_HAS_SCLR = 0; + parameter C_HAS_SINIT = 0; + parameter C_HAS_SSET = 0; + parameter C_INPUT_INV_MASK = ""; + parameter C_SINIT_VAL = ""; + parameter C_SYNC_ENABLE = `c_override; + parameter C_SYNC_PRIORITY = `c_clear; + parameter C_WIDTH = 16; + + + input [C_WIDTH-1 : 0] I; + input CTRL; + input CLK; + input CE; + input ACLR; + input ASET; + input AINIT; + input SCLR; + input SSET; + input SINIT; + output [C_WIDTH-1 : 0] O; + output [C_WIDTH-1 : 0] Q; + + reg [C_WIDTH-1 : 0] intO; + wire [C_WIDTH-1 : 0] intQ; + + wire [C_WIDTH-1 : 0] Q = (C_HAS_Q == 1 ? intQ : {C_WIDTH{1'bx}}); + wire [C_WIDTH-1 : 0] O = (C_HAS_O == 1 ? intO : {C_WIDTH{1'bx}}); + + + integer j; + + reg [C_WIDTH-1 : 0] tmpsig; + reg [C_WIDTH-1 : 0] tmpres; + + // Output register + C_REG_FD_V5_0 #(C_AINIT_VAL, C_ENABLE_RLOCS, C_HAS_ACLR, C_HAS_AINIT, C_HAS_ASET, + C_HAS_CE, C_HAS_SCLR, C_HAS_SINIT, C_HAS_SSET, + C_SINIT_VAL, C_SYNC_ENABLE, C_SYNC_PRIORITY, C_WIDTH) + reg1 (.D(intO), .CLK(CLK), .CE(CE), .ACLR(ACLR), .ASET(ASET), + .AINIT(AINIT), .SCLR(SCLR), .SSET(SSET), .SINIT(SINIT), + .Q(intQ)); + + initial + begin + #1; + + tmpsig = to_bits(C_INPUT_INV_MASK); + if(CTRL === 1'bx) + begin + for(j = 0; j < C_WIDTH; j = j + 1) + begin + if(tmpsig[j] == 1) // Inversion of input bit + begin + if(C_GATE_TYPE == 0) // AND gate + begin + if(I[j] === 1'b1) + tmpres[j] = 1'b0; + else + tmpres[j] = 1'bx; + end + else if(C_GATE_TYPE == 1) // NAND gate + begin + if(I[j] === 1'b1) + tmpres[j] = 1'b1; + else + tmpres[j] = 1'bx; + end + else if(C_GATE_TYPE == 2) // OR gate + begin + if(I[j] === 1'b0) + tmpres[j] = 1'b1; + else + tmpres[j] = 1'bx; + end + else if(C_GATE_TYPE == 3) // NOR gate + begin + if(I[j] === 1'b0) + tmpres[j] = 1'b0; + else + tmpres[j] = 1'bx; + end + else if(C_GATE_TYPE == 4) // XOR gate + tmpres[j] = 1'bx; + else if(C_GATE_TYPE == 5) // XNOR gate + tmpres[j] = 1'bx; + end + else // No input inversion on bit j of input + begin + if(C_GATE_TYPE == 0) // AND gate + begin + if(I[j] === 1'b0) + tmpres[j] = 1'b0; + else + tmpres[j] = 1'bx; + end + else if(C_GATE_TYPE == 1) // NAND gate + begin + if(I[j] === 1'b0) + tmpres[j] = 1'b1; + else + tmpres[j] = 1'bx; + end + else if(C_GATE_TYPE == 2) // OR gate + begin + if(I[j] === 1'b1) + tmpres[j] = 1'b1; + else + tmpres[j] = 1'bx; + end + else if(C_GATE_TYPE == 3) // NOR gate + begin + if(I[j] === 1'b1) + tmpres[j] = 1'b0; + else + tmpres[j] = 1'bx; + end + else if(C_GATE_TYPE == 4) // XOR gate + tmpres[j] = 1'bx; + else if(C_GATE_TYPE == 5) // XNOR gate + tmpres[j] = 1'bx; + end + end + end + else // CTRL is not unknown + begin + for(j = 0; j < C_WIDTH; j = j + 1) + begin + if(tmpsig[j] == 1) + begin + if(C_GATE_TYPE == 0) // AND gate + begin + if(I[j] !== 1'bx) + tmpres[j] = CTRL & ~I[j]; + else if(CTRL === 1'b0) + tmpres[j] = 1'b0; + else + tmpres[j] = 1'bx; + end + else if(C_GATE_TYPE == 1) // NAND gate + begin + if(I[j] !== 1'bx) + tmpres[j] = ~(CTRL & ~I[j]); + else if(CTRL === 1'b0) + tmpres[j] = 1'b1; + else + tmpres[j] = 1'bx; + end + else if(C_GATE_TYPE == 2) // OR gate + begin + if(I[j] !== 1'bx) + tmpres[j] = CTRL | ~I[j]; + else if(CTRL === 1'b1) + tmpres[j] = 1'b1; + else + tmpres[j] = 1'bx; + end + else if(C_GATE_TYPE == 3) // NOR gate + begin + if(I[j] !== 1'bx) + tmpres[j] = ~(CTRL | ~I[j]); + else if(CTRL === 1'b1) + tmpres[j] = 1'b0; + else + tmpres[j] = 1'bx; + end + else if(C_GATE_TYPE == 4) // XOR gate + begin + if(I[j] !== 1'bx) + tmpres[j] = CTRL ^ ~I[j]; + else + tmpres[j] = 1'bx; + end + else if(C_GATE_TYPE == 5) // XNOR gate + begin + if(I[j] !== 1'bx) + tmpres[j] = ~(CTRL ^ ~I[j]); + else + tmpres[j] = 1'bx; + end + end + else // No input inversion on bit j of input + begin + if(C_GATE_TYPE == 0) // AND gate + begin + if(I[j] !== 1'bx) + tmpres[j] = CTRL & I[j]; + else if(CTRL === 1'b0) + tmpres[j] = 1'b0; + else + tmpres[j] = 1'bx; + end + else if(C_GATE_TYPE == 1) // NAND gate + begin + if(I[j] !== 1'bx) + tmpres[j] = ~(CTRL & I[j]); + else if(CTRL === 1'b0) + tmpres[j] = 1'b0; + else + tmpres[j] = 1'bx; + end + else if(C_GATE_TYPE == 2) // OR gate + begin + if(I[j] !== 1'bx) + tmpres[j] = CTRL | I[j]; + else if(CTRL === 1'b1) + tmpres[j] = 1'b1; + else + tmpres[j] = 1'bx; + end + else if(C_GATE_TYPE == 3) // NOR gate + begin + if(I[j] !== 1'bx) + tmpres[j] = ~(CTRL | I[j]); + else if(CTRL === 1'b1) + tmpres[j] = 1'b1; + else + tmpres[j] = 1'bx; + end + else if(C_GATE_TYPE == 4) // XOR gate + begin + if(I[j] !== 1'bx) + tmpres[j] = CTRL ^ I[j]; + else + tmpres[j] = 1'bx; + end + else if(C_GATE_TYPE == 5) // XNOR gate + begin + if(I[j] !== 1'bx) + tmpres[j] = ~(CTRL ^ I[j]); + else + tmpres[j] = 1'bx; + end + end + end + end + + intO <= tmpres; + end + + always@(I or CTRL) + begin + + if(CTRL === 1'bx) + begin + for(j = 0; j < C_WIDTH; j = j + 1) + begin + if(tmpsig[j] == 1) // Inversion of input bit + begin + if(C_GATE_TYPE == 0) // AND gate + begin + if(I[j] === 1'b1) + tmpres[j] = 1'b0; + else + tmpres[j] = 1'bx; + end + else if(C_GATE_TYPE == 1) // NAND gate + begin + if(I[j] === 1'b1) + tmpres[j] = 1'b1; + else + tmpres[j] = 1'bx; + end + else if(C_GATE_TYPE == 2) // OR gate + begin + if(I[j] === 1'b0) + tmpres[j] = 1'b1; + else + tmpres[j] = 1'bx; + end + else if(C_GATE_TYPE == 3) // NOR gate + begin + if(I[j] === 1'b0) + tmpres[j] = 1'b0; + else + tmpres[j] = 1'bx; + end + else if(C_GATE_TYPE == 4) // XOR gate + tmpres[j] = 1'bx; + else if(C_GATE_TYPE == 5) // XNOR gate + tmpres[j] = 1'bx; + end + else // No input inversion on bit j of input + begin + if(C_GATE_TYPE == 0) // AND gate + begin + if(I[j] === 1'b0) + tmpres[j] = 1'b0; + else + tmpres[j] = 1'bx; + end + else if(C_GATE_TYPE == 1) // NAND gate + begin + if(I[j] === 1'b0) + tmpres[j] = 1'b1; + else + tmpres[j] = 1'bx; + end + else if(C_GATE_TYPE == 2) // OR gate + begin + if(I[j] === 1'b1) + tmpres[j] = 1'b1; + else + tmpres[j] = 1'bx; + end + else if(C_GATE_TYPE == 3) // NOR gate + begin + if(I[j] === 1'b1) + tmpres[j] = 1'b0; + else + tmpres[j] = 1'bx; + end + else if(C_GATE_TYPE == 4) // XOR gate + tmpres[j] = 1'bx; + else if(C_GATE_TYPE == 5) // XNOR gate + tmpres[j] = 1'bx; + end + end + end + else // CTRL is not unknown + begin + for(j = 0; j < C_WIDTH; j = j + 1) + begin + if(tmpsig[j] == 1) + begin + if(C_GATE_TYPE == 0) // AND gate + begin + if(I[j] !== 1'bx) + tmpres[j] = CTRL & ~I[j]; + else if(CTRL === 1'b0) + tmpres[j] = 1'b0; + else + tmpres[j] = 1'bx; + end + else if(C_GATE_TYPE == 1) // NAND gate + begin + if(I[j] !== 1'bx) + tmpres[j] = ~(CTRL & ~I[j]); + else if(CTRL === 1'b0) + tmpres[j] = 1'b1; + else + tmpres[j] = 1'bx; + end + else if(C_GATE_TYPE == 2) // OR gate + begin + if(I[j] !== 1'bx) + tmpres[j] = CTRL | ~I[j]; + else if(CTRL === 1'b1) + tmpres[j] = 1'b1; + else + tmpres[j] = 1'bx; + end + else if(C_GATE_TYPE == 3) // NOR gate + begin + if(I[j] !== 1'bx) + tmpres[j] = ~(CTRL | ~I[j]); + else if(CTRL === 1'b1) + tmpres[j] = 1'b0; + else + tmpres[j] = 1'bx; + end + else if(C_GATE_TYPE == 4) // XOR gate + begin + if(I[j] !== 1'bx) + tmpres[j] = CTRL ^ ~I[j]; + else + tmpres[j] = 1'bx; + end + else if(C_GATE_TYPE == 5) // XNOR gate + begin + if(I[j] !== 1'bx) + tmpres[j] = ~(CTRL ^ ~I[j]); + else + tmpres[j] = 1'bx; + end + end + else // No input inversion on bit j of input + begin + if(C_GATE_TYPE == 0) // AND gate + begin + if(I[j] !== 1'bx) + tmpres[j] = CTRL & I[j]; + else if(CTRL === 1'b0) + tmpres[j] = 1'b0; + else + tmpres[j] = 1'bx; + end + else if(C_GATE_TYPE == 1) // NAND gate + begin + if(I[j] !== 1'bx) + tmpres[j] = ~(CTRL & I[j]); + else if(CTRL === 1'b0) + tmpres[j] = 1'b0; + else + tmpres[j] = 1'bx; + end + else if(C_GATE_TYPE == 2) // OR gate + begin + if(I[j] !== 1'bx) + tmpres[j] = CTRL | I[j]; + else if(CTRL === 1'b1) + tmpres[j] = 1'b1; + else + tmpres[j] = 1'bx; + end + else if(C_GATE_TYPE == 3) // NOR gate + begin + if(I[j] !== 1'bx) + tmpres[j] = ~(CTRL | I[j]); + else if(CTRL === 1'b1) + tmpres[j] = 1'b1; + else + tmpres[j] = 1'bx; + end + else if(C_GATE_TYPE == 4) // XOR gate + begin + if(I[j] !== 1'bx) + tmpres[j] = CTRL ^ I[j]; + else + tmpres[j] = 1'bx; + end + else if(C_GATE_TYPE == 5) // XNOR gate + begin + if(I[j] !== 1'bx) + tmpres[j] = ~(CTRL ^ I[j]); + else + tmpres[j] = 1'bx; + end + end + end + end + + intO <= #1 tmpres; + end + + function defval; + input i; + input hassig; + input val; + begin + if(hassig == 1) + defval = i; + else + defval = val; + end + endfunction + + function [C_WIDTH - 1 : 0] to_bits; + input [C_WIDTH*8 : 1] instring; + integer i; + begin + for(i = C_WIDTH; i > 0; i = i - 1) + begin // Is this character a '0'? (ASCII = 48 = 00110000) + if(instring[(i*8)] == 0 && + instring[(i*8)-1] == 0 && + instring[(i*8)-2] == 1 && + instring[(i*8)-3] == 1 && + instring[(i*8)-4] == 0 && + instring[(i*8)-5] == 0 && + instring[(i*8)-6] == 0 && + instring[(i*8)-7] == 0) + to_bits[i-1] = 0; + // Or is it a '1'? + else if(instring[(i*8)] == 0 && + instring[(i*8)-1] == 0 && + instring[(i*8)-2] == 1 && + instring[(i*8)-3] == 1 && + instring[(i*8)-4] == 0 && + instring[(i*8)-5] == 0 && + instring[(i*8)-6] == 0 && + instring[(i*8)-7] == 1) + + to_bits[i-1] = 1; + // Or is it a ' '? (a null char - in which case insert a '0') + else if(instring[(i*8)] == 0 && + instring[(i*8)-1] == 0 && + instring[(i*8)-2] == 0 && + instring[(i*8)-3] == 0 && + instring[(i*8)-4] == 0 && + instring[(i*8)-5] == 0 && + instring[(i*8)-6] == 0 && + instring[(i*8)-7] == 0) + to_bits[i-1] = 0; + else + begin + $display("Error in %m at time %d ns: non-binary digit in string \"%s\"\nExiting simulation...", $time, instring); + $finish; + end + end + end + endfunction + +endmodule + +`undef c_set +`undef c_clear +`undef c_override +`undef c_no_override +`undef c_and +`undef c_nand +`undef c_or +`undef c_nor +`undef c_xor +`undef c_xnor + + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/C_GATE_BIT_BUS_V6_0.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/C_GATE_BIT_BUS_V6_0.v new file mode 100644 index 0000000..ddd60ff --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/C_GATE_BIT_BUS_V6_0.v @@ -0,0 +1,548 @@ +// Copyright(C) 2002 by Xilinx, Inc. All rights reserved. +// This text contains proprietary, confidential +// information of Xilinx, Inc., is distributed +// under license from Xilinx, Inc., and may be used, +// copied and/or disclosed only pursuant to the terms +// of a valid license agreement with Xilinx, Inc. This copyright +// notice must be retained as part of this text at all times. + + +/* $Id: C_GATE_BIT_BUS_V6_0.v,v 1.16 2008/09/08 20:06:04 akennedy Exp $ +-- +-- Filename - C_GATE_BIT_BUS_V6_0.v +-- Author - Xilinx +-- Creation - 25 Jan 1999 +-- +-- Description - This file contains the Verilog behavior for the Baseblocks C_GATE_BIT_BUS_V6_0 module +*/ + +`timescale 1ns/10ps + +`define c_set 0 +`define c_clear 1 +`define c_override 0 +`define c_no_override 1 +`define c_and 0 +`define c_nand 1 +`define c_or 2 +`define c_nor 3 +`define c_xor 4 +`define c_xnor 5 + +module C_GATE_BIT_BUS_V6_0 (I, CTRL, CLK, CE, ACLR, ASET, AINIT, SCLR, SSET, SINIT, O, Q); + + parameter C_AINIT_VAL = ""; + parameter C_ENABLE_RLOCS = 1; + parameter C_GATE_TYPE = `c_and; + parameter C_HAS_ACLR = 0; + parameter C_HAS_AINIT = 0; + parameter C_HAS_ASET = 0; + parameter C_HAS_CE = 0; + parameter C_HAS_O = 0; + parameter C_HAS_Q = 1; + parameter C_HAS_SCLR = 0; + parameter C_HAS_SINIT = 0; + parameter C_HAS_SSET = 0; + parameter C_INPUT_INV_MASK = ""; + parameter C_SINIT_VAL = ""; + parameter C_SYNC_ENABLE = `c_override; + parameter C_SYNC_PRIORITY = `c_clear; + parameter C_WIDTH = 16; + + + input [C_WIDTH-1 : 0] I; + input CTRL; + input CLK; + input CE; + input ACLR; + input ASET; + input AINIT; + input SCLR; + input SSET; + input SINIT; + output [C_WIDTH-1 : 0] O; + output [C_WIDTH-1 : 0] Q; + + reg [C_WIDTH-1 : 0] intO; + wire [C_WIDTH-1 : 0] intQ; + + wire [C_WIDTH-1 : 0] Q = (C_HAS_Q == 1 ? intQ : {C_WIDTH{1'bx}}); + wire [C_WIDTH-1 : 0] O = (C_HAS_O == 1 ? intO : {C_WIDTH{1'bx}}); + + + integer j; + + reg [C_WIDTH-1 : 0] tmpsig; + reg [C_WIDTH-1 : 0] tmpres; + + // Output register + C_REG_FD_V6_0 #(C_AINIT_VAL, C_ENABLE_RLOCS, C_HAS_ACLR, C_HAS_AINIT, C_HAS_ASET, + C_HAS_CE, C_HAS_SCLR, C_HAS_SINIT, C_HAS_SSET, + C_SINIT_VAL, C_SYNC_ENABLE, C_SYNC_PRIORITY, C_WIDTH) + reg1 (.D(intO), .CLK(CLK), .CE(CE), .ACLR(ACLR), .ASET(ASET), + .AINIT(AINIT), .SCLR(SCLR), .SSET(SSET), .SINIT(SINIT), + .Q(intQ)); + + initial + begin + #1; + + tmpsig = to_bits(C_INPUT_INV_MASK); + if(CTRL === 1'bx) + begin + for(j = 0; j < C_WIDTH; j = j + 1) + begin + if(tmpsig[j] == 1) // Inversion of input bit + begin + if(C_GATE_TYPE == 0) // AND gate + begin + if(I[j] === 1'b1) + tmpres[j] = 1'b0; + else + tmpres[j] = 1'bx; + end + else if(C_GATE_TYPE == 1) // NAND gate + begin + if(I[j] === 1'b1) + tmpres[j] = 1'b1; + else + tmpres[j] = 1'bx; + end + else if(C_GATE_TYPE == 2) // OR gate + begin + if(I[j] === 1'b0) + tmpres[j] = 1'b1; + else + tmpres[j] = 1'bx; + end + else if(C_GATE_TYPE == 3) // NOR gate + begin + if(I[j] === 1'b0) + tmpres[j] = 1'b0; + else + tmpres[j] = 1'bx; + end + else if(C_GATE_TYPE == 4) // XOR gate + tmpres[j] = 1'bx; + else if(C_GATE_TYPE == 5) // XNOR gate + tmpres[j] = 1'bx; + end + else // No input inversion on bit j of input + begin + if(C_GATE_TYPE == 0) // AND gate + begin + if(I[j] === 1'b0) + tmpres[j] = 1'b0; + else + tmpres[j] = 1'bx; + end + else if(C_GATE_TYPE == 1) // NAND gate + begin + if(I[j] === 1'b0) + tmpres[j] = 1'b1; + else + tmpres[j] = 1'bx; + end + else if(C_GATE_TYPE == 2) // OR gate + begin + if(I[j] === 1'b1) + tmpres[j] = 1'b1; + else + tmpres[j] = 1'bx; + end + else if(C_GATE_TYPE == 3) // NOR gate + begin + if(I[j] === 1'b1) + tmpres[j] = 1'b0; + else + tmpres[j] = 1'bx; + end + else if(C_GATE_TYPE == 4) // XOR gate + tmpres[j] = 1'bx; + else if(C_GATE_TYPE == 5) // XNOR gate + tmpres[j] = 1'bx; + end + end + end + else // CTRL is not unknown + begin + for(j = 0; j < C_WIDTH; j = j + 1) + begin + if(tmpsig[j] == 1) + begin + if(C_GATE_TYPE == 0) // AND gate + begin + if(I[j] !== 1'bx) + tmpres[j] = CTRL & ~I[j]; + else if(CTRL === 1'b0) + tmpres[j] = 1'b0; + else + tmpres[j] = 1'bx; + end + else if(C_GATE_TYPE == 1) // NAND gate + begin + if(I[j] !== 1'bx) + tmpres[j] = ~(CTRL & ~I[j]); + else if(CTRL === 1'b0) + tmpres[j] = 1'b1; + else + tmpres[j] = 1'bx; + end + else if(C_GATE_TYPE == 2) // OR gate + begin + if(I[j] !== 1'bx) + tmpres[j] = CTRL | ~I[j]; + else if(CTRL === 1'b1) + tmpres[j] = 1'b1; + else + tmpres[j] = 1'bx; + end + else if(C_GATE_TYPE == 3) // NOR gate + begin + if(I[j] !== 1'bx) + tmpres[j] = ~(CTRL | ~I[j]); + else if(CTRL === 1'b1) + tmpres[j] = 1'b0; + else + tmpres[j] = 1'bx; + end + else if(C_GATE_TYPE == 4) // XOR gate + begin + if(I[j] !== 1'bx) + tmpres[j] = CTRL ^ ~I[j]; + else + tmpres[j] = 1'bx; + end + else if(C_GATE_TYPE == 5) // XNOR gate + begin + if(I[j] !== 1'bx) + tmpres[j] = ~(CTRL ^ ~I[j]); + else + tmpres[j] = 1'bx; + end + end + else // No input inversion on bit j of input + begin + if(C_GATE_TYPE == 0) // AND gate + begin + if(I[j] !== 1'bx) + tmpres[j] = CTRL & I[j]; + else if(CTRL === 1'b0) + tmpres[j] = 1'b0; + else + tmpres[j] = 1'bx; + end + else if(C_GATE_TYPE == 1) // NAND gate + begin + if(I[j] !== 1'bx) + tmpres[j] = ~(CTRL & I[j]); + else if(CTRL === 1'b0) + tmpres[j] = 1'b0; + else + tmpres[j] = 1'bx; + end + else if(C_GATE_TYPE == 2) // OR gate + begin + if(I[j] !== 1'bx) + tmpres[j] = CTRL | I[j]; + else if(CTRL === 1'b1) + tmpres[j] = 1'b1; + else + tmpres[j] = 1'bx; + end + else if(C_GATE_TYPE == 3) // NOR gate + begin + if(I[j] !== 1'bx) + tmpres[j] = ~(CTRL | I[j]); + else if(CTRL === 1'b1) + tmpres[j] = 1'b1; + else + tmpres[j] = 1'bx; + end + else if(C_GATE_TYPE == 4) // XOR gate + begin + if(I[j] !== 1'bx) + tmpres[j] = CTRL ^ I[j]; + else + tmpres[j] = 1'bx; + end + else if(C_GATE_TYPE == 5) // XNOR gate + begin + if(I[j] !== 1'bx) + tmpres[j] = ~(CTRL ^ I[j]); + else + tmpres[j] = 1'bx; + end + end + end + end + + intO <= tmpres; + end + + always@(I or CTRL) + begin + + if(CTRL === 1'bx) + begin + for(j = 0; j < C_WIDTH; j = j + 1) + begin + if(tmpsig[j] == 1) // Inversion of input bit + begin + if(C_GATE_TYPE == 0) // AND gate + begin + if(I[j] === 1'b1) + tmpres[j] = 1'b0; + else + tmpres[j] = 1'bx; + end + else if(C_GATE_TYPE == 1) // NAND gate + begin + if(I[j] === 1'b1) + tmpres[j] = 1'b1; + else + tmpres[j] = 1'bx; + end + else if(C_GATE_TYPE == 2) // OR gate + begin + if(I[j] === 1'b0) + tmpres[j] = 1'b1; + else + tmpres[j] = 1'bx; + end + else if(C_GATE_TYPE == 3) // NOR gate + begin + if(I[j] === 1'b0) + tmpres[j] = 1'b0; + else + tmpres[j] = 1'bx; + end + else if(C_GATE_TYPE == 4) // XOR gate + tmpres[j] = 1'bx; + else if(C_GATE_TYPE == 5) // XNOR gate + tmpres[j] = 1'bx; + end + else // No input inversion on bit j of input + begin + if(C_GATE_TYPE == 0) // AND gate + begin + if(I[j] === 1'b0) + tmpres[j] = 1'b0; + else + tmpres[j] = 1'bx; + end + else if(C_GATE_TYPE == 1) // NAND gate + begin + if(I[j] === 1'b0) + tmpres[j] = 1'b1; + else + tmpres[j] = 1'bx; + end + else if(C_GATE_TYPE == 2) // OR gate + begin + if(I[j] === 1'b1) + tmpres[j] = 1'b1; + else + tmpres[j] = 1'bx; + end + else if(C_GATE_TYPE == 3) // NOR gate + begin + if(I[j] === 1'b1) + tmpres[j] = 1'b0; + else + tmpres[j] = 1'bx; + end + else if(C_GATE_TYPE == 4) // XOR gate + tmpres[j] = 1'bx; + else if(C_GATE_TYPE == 5) // XNOR gate + tmpres[j] = 1'bx; + end + end + end + else // CTRL is not unknown + begin + for(j = 0; j < C_WIDTH; j = j + 1) + begin + if(tmpsig[j] == 1) + begin + if(C_GATE_TYPE == 0) // AND gate + begin + if(I[j] !== 1'bx) + tmpres[j] = CTRL & ~I[j]; + else if(CTRL === 1'b0) + tmpres[j] = 1'b0; + else + tmpres[j] = 1'bx; + end + else if(C_GATE_TYPE == 1) // NAND gate + begin + if(I[j] !== 1'bx) + tmpres[j] = ~(CTRL & ~I[j]); + else if(CTRL === 1'b0) + tmpres[j] = 1'b1; + else + tmpres[j] = 1'bx; + end + else if(C_GATE_TYPE == 2) // OR gate + begin + if(I[j] !== 1'bx) + tmpres[j] = CTRL | ~I[j]; + else if(CTRL === 1'b1) + tmpres[j] = 1'b1; + else + tmpres[j] = 1'bx; + end + else if(C_GATE_TYPE == 3) // NOR gate + begin + if(I[j] !== 1'bx) + tmpres[j] = ~(CTRL | ~I[j]); + else if(CTRL === 1'b1) + tmpres[j] = 1'b0; + else + tmpres[j] = 1'bx; + end + else if(C_GATE_TYPE == 4) // XOR gate + begin + if(I[j] !== 1'bx) + tmpres[j] = CTRL ^ ~I[j]; + else + tmpres[j] = 1'bx; + end + else if(C_GATE_TYPE == 5) // XNOR gate + begin + if(I[j] !== 1'bx) + tmpres[j] = ~(CTRL ^ ~I[j]); + else + tmpres[j] = 1'bx; + end + end + else // No input inversion on bit j of input + begin + if(C_GATE_TYPE == 0) // AND gate + begin + if(I[j] !== 1'bx) + tmpres[j] = CTRL & I[j]; + else if(CTRL === 1'b0) + tmpres[j] = 1'b0; + else + tmpres[j] = 1'bx; + end + else if(C_GATE_TYPE == 1) // NAND gate + begin + if(I[j] !== 1'bx) + tmpres[j] = ~(CTRL & I[j]); + else if(CTRL === 1'b0) + tmpres[j] = 1'b0; + else + tmpres[j] = 1'bx; + end + else if(C_GATE_TYPE == 2) // OR gate + begin + if(I[j] !== 1'bx) + tmpres[j] = CTRL | I[j]; + else if(CTRL === 1'b1) + tmpres[j] = 1'b1; + else + tmpres[j] = 1'bx; + end + else if(C_GATE_TYPE == 3) // NOR gate + begin + if(I[j] !== 1'bx) + tmpres[j] = ~(CTRL | I[j]); + else if(CTRL === 1'b1) + tmpres[j] = 1'b1; + else + tmpres[j] = 1'bx; + end + else if(C_GATE_TYPE == 4) // XOR gate + begin + if(I[j] !== 1'bx) + tmpres[j] = CTRL ^ I[j]; + else + tmpres[j] = 1'bx; + end + else if(C_GATE_TYPE == 5) // XNOR gate + begin + if(I[j] !== 1'bx) + tmpres[j] = ~(CTRL ^ I[j]); + else + tmpres[j] = 1'bx; + end + end + end + end + + intO <= #1 tmpres; + end + + function defval; + input i; + input hassig; + input val; + begin + if(hassig == 1) + defval = i; + else + defval = val; + end + endfunction + + function [C_WIDTH - 1 : 0] to_bits; + input [C_WIDTH*8 : 1] instring; + integer i; + begin + for(i = C_WIDTH; i > 0; i = i - 1) + begin // Is this character a '0'? (ASCII = 48 = 00110000) + if(instring[(i*8)] == 0 && + instring[(i*8)-1] == 0 && + instring[(i*8)-2] == 1 && + instring[(i*8)-3] == 1 && + instring[(i*8)-4] == 0 && + instring[(i*8)-5] == 0 && + instring[(i*8)-6] == 0 && + instring[(i*8)-7] == 0) + to_bits[i-1] = 0; + // Or is it a '1'? + else if(instring[(i*8)] == 0 && + instring[(i*8)-1] == 0 && + instring[(i*8)-2] == 1 && + instring[(i*8)-3] == 1 && + instring[(i*8)-4] == 0 && + instring[(i*8)-5] == 0 && + instring[(i*8)-6] == 0 && + instring[(i*8)-7] == 1) + + to_bits[i-1] = 1; + // Or is it a ' '? (a null char - in which case insert a '0') + else if(instring[(i*8)] == 0 && + instring[(i*8)-1] == 0 && + instring[(i*8)-2] == 0 && + instring[(i*8)-3] == 0 && + instring[(i*8)-4] == 0 && + instring[(i*8)-5] == 0 && + instring[(i*8)-6] == 0 && + instring[(i*8)-7] == 0) + to_bits[i-1] = 0; + else + begin + $display("Error in %m at time %d ns: non-binary digit in string \"%s\"\nExiting simulation...", $time, instring); + $finish; + end + end + end + endfunction + +endmodule + +`undef c_set +`undef c_clear +`undef c_override +`undef c_no_override +`undef c_and +`undef c_nand +`undef c_or +`undef c_nor +`undef c_xor +`undef c_xnor + + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/C_GATE_BIT_BUS_V7_0.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/C_GATE_BIT_BUS_V7_0.v new file mode 100644 index 0000000..540fd69 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/C_GATE_BIT_BUS_V7_0.v @@ -0,0 +1,577 @@ +// Copyright(C) 2003 by Xilinx, Inc. All rights reserved. +// This text/file contains proprietary, confidential +// information of Xilinx, Inc., is distributed under license +// from Xilinx, Inc., and may be used, copied and/or +// disclosed only pursuant to the terms of a valid license +// agreement with Xilinx, Inc. Xilinx hereby grants you +// a license to use this text/file solely for design, simulation, +// implementation and creation of design files limited +// to Xilinx devices or technologies. Use with non-Xilinx +// devices or technologies is expressly prohibited and +// immediately terminates your license unless covered by +// a separate agreement. +// +// Xilinx is providing this design, code, or information +// "as is" solely for use in developing programs and +// solutions for Xilinx devices. By providing this design, +// code, or information as one possible implementation of +// this feature, application or standard, Xilinx is making no +// representation that this implementation is free from any +// claims of infringement. You are responsible for +// obtaining any rights you may require for your implementation. +// Xilinx expressly disclaims any warranty whatsoever with +// respect to the adequacy of the implementation, including +// but not limited to any warranties or representations that this +// implementation is free from claims of infringement, implied +// warranties of merchantability or fitness for a particular +// purpose. +// +// Xilinx products are not intended for use in life support +// appliances, devices, or systems. Use in such applications are +// expressly prohibited. +// +// This copyright and support notice must be retained as part +// of this text at all times. (c) Copyright 1995-2003 Xilinx, Inc. +// All rights reserved. + + + +/* $Id: C_GATE_BIT_BUS_V7_0.v,v 1.13 2008/09/08 20:06:13 akennedy Exp $ +-- +-- Filename - C_GATE_BIT_BUS_V7_0.v +-- Author - Xilinx +-- Creation - 25 Jan 1999 +-- +-- Description - This file contains the Verilog behavior for the Baseblocks C_GATE_BIT_BUS_V7_0 module +*/ + +`timescale 1ns/10ps + +`define c_set 0 +`define c_clear 1 +`define c_override 0 +`define c_no_override 1 +`define c_and 0 +`define c_nand 1 +`define c_or 2 +`define c_nor 3 +`define c_xor 4 +`define c_xnor 5 + +module C_GATE_BIT_BUS_V7_0 (I, CTRL, CLK, CE, ACLR, ASET, AINIT, SCLR, SSET, SINIT, O, Q); + + parameter C_AINIT_VAL = ""; + parameter C_ENABLE_RLOCS = 1; + parameter C_GATE_TYPE = `c_and; + parameter C_HAS_ACLR = 0; + parameter C_HAS_AINIT = 0; + parameter C_HAS_ASET = 0; + parameter C_HAS_CE = 0; + parameter C_HAS_O = 0; + parameter C_HAS_Q = 1; + parameter C_HAS_SCLR = 0; + parameter C_HAS_SINIT = 0; + parameter C_HAS_SSET = 0; + parameter C_INPUT_INV_MASK = ""; + parameter C_SINIT_VAL = ""; + parameter C_SYNC_ENABLE = `c_override; + parameter C_SYNC_PRIORITY = `c_clear; + parameter C_WIDTH = 16; + + + input [C_WIDTH-1 : 0] I; + input CTRL; + input CLK; + input CE; + input ACLR; + input ASET; + input AINIT; + input SCLR; + input SSET; + input SINIT; + output [C_WIDTH-1 : 0] O; + output [C_WIDTH-1 : 0] Q; + + reg [C_WIDTH-1 : 0] intO; + wire [C_WIDTH-1 : 0] intQ; + + wire [C_WIDTH-1 : 0] Q = (C_HAS_Q == 1 ? intQ : {C_WIDTH{1'bx}}); + wire [C_WIDTH-1 : 0] O = (C_HAS_O == 1 ? intO : {C_WIDTH{1'bx}}); + + + integer j; + + reg [C_WIDTH-1 : 0] tmpsig; + reg [C_WIDTH-1 : 0] tmpres; + + // Output register + C_REG_FD_V7_0 #(C_AINIT_VAL, C_ENABLE_RLOCS, C_HAS_ACLR, C_HAS_AINIT, C_HAS_ASET, + C_HAS_CE, C_HAS_SCLR, C_HAS_SINIT, C_HAS_SSET, + C_SINIT_VAL, C_SYNC_ENABLE, C_SYNC_PRIORITY, C_WIDTH) + reg1 (.D(intO), .CLK(CLK), .CE(CE), .ACLR(ACLR), .ASET(ASET), + .AINIT(AINIT), .SCLR(SCLR), .SSET(SSET), .SINIT(SINIT), + .Q(intQ)); + + initial + begin + #1; + + tmpsig = to_bits(C_INPUT_INV_MASK); + if(CTRL === 1'bx) + begin + for(j = 0; j < C_WIDTH; j = j + 1) + begin + if(tmpsig[j] == 1) // Inversion of input bit + begin + if(C_GATE_TYPE == 0) // AND gate + begin + if(I[j] === 1'b1) + tmpres[j] = 1'b0; + else + tmpres[j] = 1'bx; + end + else if(C_GATE_TYPE == 1) // NAND gate + begin + if(I[j] === 1'b1) + tmpres[j] = 1'b1; + else + tmpres[j] = 1'bx; + end + else if(C_GATE_TYPE == 2) // OR gate + begin + if(I[j] === 1'b0) + tmpres[j] = 1'b1; + else + tmpres[j] = 1'bx; + end + else if(C_GATE_TYPE == 3) // NOR gate + begin + if(I[j] === 1'b0) + tmpres[j] = 1'b0; + else + tmpres[j] = 1'bx; + end + else if(C_GATE_TYPE == 4) // XOR gate + tmpres[j] = 1'bx; + else if(C_GATE_TYPE == 5) // XNOR gate + tmpres[j] = 1'bx; + end + else // No input inversion on bit j of input + begin + if(C_GATE_TYPE == 0) // AND gate + begin + if(I[j] === 1'b0) + tmpres[j] = 1'b0; + else + tmpres[j] = 1'bx; + end + else if(C_GATE_TYPE == 1) // NAND gate + begin + if(I[j] === 1'b0) + tmpres[j] = 1'b1; + else + tmpres[j] = 1'bx; + end + else if(C_GATE_TYPE == 2) // OR gate + begin + if(I[j] === 1'b1) + tmpres[j] = 1'b1; + else + tmpres[j] = 1'bx; + end + else if(C_GATE_TYPE == 3) // NOR gate + begin + if(I[j] === 1'b1) + tmpres[j] = 1'b0; + else + tmpres[j] = 1'bx; + end + else if(C_GATE_TYPE == 4) // XOR gate + tmpres[j] = 1'bx; + else if(C_GATE_TYPE == 5) // XNOR gate + tmpres[j] = 1'bx; + end + end + end + else // CTRL is not unknown + begin + for(j = 0; j < C_WIDTH; j = j + 1) + begin + if(tmpsig[j] == 1) + begin + if(C_GATE_TYPE == 0) // AND gate + begin + if(I[j] !== 1'bx) + tmpres[j] = CTRL & ~I[j]; + else if(CTRL === 1'b0) + tmpres[j] = 1'b0; + else + tmpres[j] = 1'bx; + end + else if(C_GATE_TYPE == 1) // NAND gate + begin + if(I[j] !== 1'bx) + tmpres[j] = ~(CTRL & ~I[j]); + else if(CTRL === 1'b0) + tmpres[j] = 1'b1; + else + tmpres[j] = 1'bx; + end + else if(C_GATE_TYPE == 2) // OR gate + begin + if(I[j] !== 1'bx) + tmpres[j] = CTRL | ~I[j]; + else if(CTRL === 1'b1) + tmpres[j] = 1'b1; + else + tmpres[j] = 1'bx; + end + else if(C_GATE_TYPE == 3) // NOR gate + begin + if(I[j] !== 1'bx) + tmpres[j] = ~(CTRL | ~I[j]); + else if(CTRL === 1'b1) + tmpres[j] = 1'b0; + else + tmpres[j] = 1'bx; + end + else if(C_GATE_TYPE == 4) // XOR gate + begin + if(I[j] !== 1'bx) + tmpres[j] = CTRL ^ ~I[j]; + else + tmpres[j] = 1'bx; + end + else if(C_GATE_TYPE == 5) // XNOR gate + begin + if(I[j] !== 1'bx) + tmpres[j] = ~(CTRL ^ ~I[j]); + else + tmpres[j] = 1'bx; + end + end + else // No input inversion on bit j of input + begin + if(C_GATE_TYPE == 0) // AND gate + begin + if(I[j] !== 1'bx) + tmpres[j] = CTRL & I[j]; + else if(CTRL === 1'b0) + tmpres[j] = 1'b0; + else + tmpres[j] = 1'bx; + end + else if(C_GATE_TYPE == 1) // NAND gate + begin + if(I[j] !== 1'bx) + tmpres[j] = ~(CTRL & I[j]); + else if(CTRL === 1'b0) + tmpres[j] = 1'b0; + else + tmpres[j] = 1'bx; + end + else if(C_GATE_TYPE == 2) // OR gate + begin + if(I[j] !== 1'bx) + tmpres[j] = CTRL | I[j]; + else if(CTRL === 1'b1) + tmpres[j] = 1'b1; + else + tmpres[j] = 1'bx; + end + else if(C_GATE_TYPE == 3) // NOR gate + begin + if(I[j] !== 1'bx) + tmpres[j] = ~(CTRL | I[j]); + else if(CTRL === 1'b1) + tmpres[j] = 1'b1; + else + tmpres[j] = 1'bx; + end + else if(C_GATE_TYPE == 4) // XOR gate + begin + if(I[j] !== 1'bx) + tmpres[j] = CTRL ^ I[j]; + else + tmpres[j] = 1'bx; + end + else if(C_GATE_TYPE == 5) // XNOR gate + begin + if(I[j] !== 1'bx) + tmpres[j] = ~(CTRL ^ I[j]); + else + tmpres[j] = 1'bx; + end + end + end + end + + intO <= tmpres; + end + + always@(I or CTRL) + begin + + if(CTRL === 1'bx) + begin + for(j = 0; j < C_WIDTH; j = j + 1) + begin + if(tmpsig[j] == 1) // Inversion of input bit + begin + if(C_GATE_TYPE == 0) // AND gate + begin + if(I[j] === 1'b1) + tmpres[j] = 1'b0; + else + tmpres[j] = 1'bx; + end + else if(C_GATE_TYPE == 1) // NAND gate + begin + if(I[j] === 1'b1) + tmpres[j] = 1'b1; + else + tmpres[j] = 1'bx; + end + else if(C_GATE_TYPE == 2) // OR gate + begin + if(I[j] === 1'b0) + tmpres[j] = 1'b1; + else + tmpres[j] = 1'bx; + end + else if(C_GATE_TYPE == 3) // NOR gate + begin + if(I[j] === 1'b0) + tmpres[j] = 1'b0; + else + tmpres[j] = 1'bx; + end + else if(C_GATE_TYPE == 4) // XOR gate + tmpres[j] = 1'bx; + else if(C_GATE_TYPE == 5) // XNOR gate + tmpres[j] = 1'bx; + end + else // No input inversion on bit j of input + begin + if(C_GATE_TYPE == 0) // AND gate + begin + if(I[j] === 1'b0) + tmpres[j] = 1'b0; + else + tmpres[j] = 1'bx; + end + else if(C_GATE_TYPE == 1) // NAND gate + begin + if(I[j] === 1'b0) + tmpres[j] = 1'b1; + else + tmpres[j] = 1'bx; + end + else if(C_GATE_TYPE == 2) // OR gate + begin + if(I[j] === 1'b1) + tmpres[j] = 1'b1; + else + tmpres[j] = 1'bx; + end + else if(C_GATE_TYPE == 3) // NOR gate + begin + if(I[j] === 1'b1) + tmpres[j] = 1'b0; + else + tmpres[j] = 1'bx; + end + else if(C_GATE_TYPE == 4) // XOR gate + tmpres[j] = 1'bx; + else if(C_GATE_TYPE == 5) // XNOR gate + tmpres[j] = 1'bx; + end + end + end + else // CTRL is not unknown + begin + for(j = 0; j < C_WIDTH; j = j + 1) + begin + if(tmpsig[j] == 1) + begin + if(C_GATE_TYPE == 0) // AND gate + begin + if(I[j] !== 1'bx) + tmpres[j] = CTRL & ~I[j]; + else if(CTRL === 1'b0) + tmpres[j] = 1'b0; + else + tmpres[j] = 1'bx; + end + else if(C_GATE_TYPE == 1) // NAND gate + begin + if(I[j] !== 1'bx) + tmpres[j] = ~(CTRL & ~I[j]); + else if(CTRL === 1'b0) + tmpres[j] = 1'b1; + else + tmpres[j] = 1'bx; + end + else if(C_GATE_TYPE == 2) // OR gate + begin + if(I[j] !== 1'bx) + tmpres[j] = CTRL | ~I[j]; + else if(CTRL === 1'b1) + tmpres[j] = 1'b1; + else + tmpres[j] = 1'bx; + end + else if(C_GATE_TYPE == 3) // NOR gate + begin + if(I[j] !== 1'bx) + tmpres[j] = ~(CTRL | ~I[j]); + else if(CTRL === 1'b1) + tmpres[j] = 1'b0; + else + tmpres[j] = 1'bx; + end + else if(C_GATE_TYPE == 4) // XOR gate + begin + if(I[j] !== 1'bx) + tmpres[j] = CTRL ^ ~I[j]; + else + tmpres[j] = 1'bx; + end + else if(C_GATE_TYPE == 5) // XNOR gate + begin + if(I[j] !== 1'bx) + tmpres[j] = ~(CTRL ^ ~I[j]); + else + tmpres[j] = 1'bx; + end + end + else // No input inversion on bit j of input + begin + if(C_GATE_TYPE == 0) // AND gate + begin + if(I[j] !== 1'bx) + tmpres[j] = CTRL & I[j]; + else if(CTRL === 1'b0) + tmpres[j] = 1'b0; + else + tmpres[j] = 1'bx; + end + else if(C_GATE_TYPE == 1) // NAND gate + begin + if(I[j] !== 1'bx) + tmpres[j] = ~(CTRL & I[j]); + else if(CTRL === 1'b0) + tmpres[j] = 1'b0; + else + tmpres[j] = 1'bx; + end + else if(C_GATE_TYPE == 2) // OR gate + begin + if(I[j] !== 1'bx) + tmpres[j] = CTRL | I[j]; + else if(CTRL === 1'b1) + tmpres[j] = 1'b1; + else + tmpres[j] = 1'bx; + end + else if(C_GATE_TYPE == 3) // NOR gate + begin + if(I[j] !== 1'bx) + tmpres[j] = ~(CTRL | I[j]); + else if(CTRL === 1'b1) + tmpres[j] = 1'b1; + else + tmpres[j] = 1'bx; + end + else if(C_GATE_TYPE == 4) // XOR gate + begin + if(I[j] !== 1'bx) + tmpres[j] = CTRL ^ I[j]; + else + tmpres[j] = 1'bx; + end + else if(C_GATE_TYPE == 5) // XNOR gate + begin + if(I[j] !== 1'bx) + tmpres[j] = ~(CTRL ^ I[j]); + else + tmpres[j] = 1'bx; + end + end + end + end + + intO <= #1 tmpres; + end + + function defval; + input i; + input hassig; + input val; + begin + if(hassig == 1) + defval = i; + else + defval = val; + end + endfunction + + function [C_WIDTH - 1 : 0] to_bits; + input [C_WIDTH*8 : 1] instring; + integer i; + begin + for(i = C_WIDTH; i > 0; i = i - 1) + begin // Is this character a '0'? (ASCII = 48 = 00110000) + if(instring[(i*8)] == 0 && + instring[(i*8)-1] == 0 && + instring[(i*8)-2] == 1 && + instring[(i*8)-3] == 1 && + instring[(i*8)-4] == 0 && + instring[(i*8)-5] == 0 && + instring[(i*8)-6] == 0 && + instring[(i*8)-7] == 0) + to_bits[i-1] = 0; + // Or is it a '1'? + else if(instring[(i*8)] == 0 && + instring[(i*8)-1] == 0 && + instring[(i*8)-2] == 1 && + instring[(i*8)-3] == 1 && + instring[(i*8)-4] == 0 && + instring[(i*8)-5] == 0 && + instring[(i*8)-6] == 0 && + instring[(i*8)-7] == 1) + + to_bits[i-1] = 1; + // Or is it a ' '? (a null char - in which case insert a '0') + else if(instring[(i*8)] == 0 && + instring[(i*8)-1] == 0 && + instring[(i*8)-2] == 0 && + instring[(i*8)-3] == 0 && + instring[(i*8)-4] == 0 && + instring[(i*8)-5] == 0 && + instring[(i*8)-6] == 0 && + instring[(i*8)-7] == 0) + to_bits[i-1] = 0; + else + begin + $display("Error in %m at time %d ns: non-binary digit in string \"%s\"\nExiting simulation...", $time, instring); + $finish; + end + end + end + endfunction + +endmodule + +`undef c_set +`undef c_clear +`undef c_override +`undef c_no_override +`undef c_and +`undef c_nand +`undef c_or +`undef c_nor +`undef c_xor +`undef c_xnor + + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/C_GATE_BIT_V4_0.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/C_GATE_BIT_V4_0.v new file mode 100644 index 0000000..1f14306 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/C_GATE_BIT_V4_0.v @@ -0,0 +1,418 @@ +/* $Id: C_GATE_BIT_V4_0.v,v 1.11 2008/09/08 20:05:46 akennedy Exp $ +-- +-- Filename - C_GATE_BIT_V4_0.v +-- Author - Xilinx +-- Creation - 25 Jan 1999 +-- +-- Description - This file contains the Verilog behavior for the Baseblocks C_GATE_BIT_V4_0 module +*/ + + + +`define c_set 0 +`define c_clear 1 +`define c_override 0 +`define c_no_override 1 +`define c_and 0 +`define c_nand 1 +`define c_or 2 +`define c_nor 3 +`define c_xor 4 +`define c_xnor 5 + +module C_GATE_BIT_V4_0 (I, CLK, CE, ACLR, ASET, AINIT, SCLR, SSET, SINIT, O, Q); + + parameter C_AINIT_VAL = "0"; + parameter C_ENABLE_RLOCS = 0; + parameter C_GATE_TYPE = `c_and; + parameter C_HAS_ACLR = 0; + parameter C_HAS_AINIT = 0; + parameter C_HAS_ASET = 0; + parameter C_HAS_CE = 0; + parameter C_HAS_O = 0; + parameter C_HAS_Q = 1; + parameter C_HAS_SCLR = 0; + parameter C_HAS_SINIT = 0; + parameter C_HAS_SSET = 0; + parameter C_INPUTS = 2; + parameter C_INPUT_INV_MASK = ""; + parameter C_PIPE_STAGES = 0; + parameter C_SINIT_VAL = "0"; + parameter C_SYNC_ENABLE = `c_override; + parameter C_SYNC_PRIORITY = `c_clear; + + + input [C_INPUTS-1 : 0] I; + input CLK; + input CE; + input ACLR; + input ASET; + input AINIT; + input SCLR; + input SSET; + input SINIT; + output O; + output Q; + + // Internal values to drive signals when input is missing + wire intCE; + reg intO; + wire intQ; + reg lastCLK; + + reg [C_PIPE_STAGES+2 : 0] intQpipe; + reg intQpipeend; + + wire Q = (C_HAS_Q == 1 ? intQ : 1'bx); + wire O = (C_HAS_O == 1 ? intO : 1'bx); + + // Sort out default values for missing ports + + assign intCE = defval(CE, C_HAS_CE, 1); + + integer j; + integer pipe; + + reg [C_INPUTS-1 : 0] tmpsig; + reg tmpres; + + // Output register + C_REG_FD_V4_0 #(C_AINIT_VAL, C_ENABLE_RLOCS, C_HAS_ACLR, C_HAS_AINIT, C_HAS_ASET, + C_HAS_CE, C_HAS_SCLR, C_HAS_SINIT, C_HAS_SSET, + C_SINIT_VAL, C_SYNC_ENABLE, C_SYNC_PRIORITY, 1) + reg1 (.D(intQpipeend), .CLK(CLK), .CE(CE), .ACLR(ACLR), .ASET(ASET), + .AINIT(AINIT), .SCLR(SCLR), .SSET(SSET), .SINIT(SINIT), + .Q(intQ)); + + initial + begin + + #1; + + intQpipe = 'b0; + + if(C_GATE_TYPE == 0 || C_GATE_TYPE == 1) // AND or NAND gate? + tmpres = 1; + else + tmpres = 0; + + tmpsig = to_bits(C_INPUT_INV_MASK); + + for(j = 0; j < C_INPUTS; j = j + 1) + begin + if(tmpsig[j] == 1) + begin + if(C_GATE_TYPE == 0) // AND gate + begin + if(I[j] !== 1'bx) + tmpres = tmpres & ~I[j]; + else if(tmpres === 1'b1) + tmpres = 1'bx; + end + else if(C_GATE_TYPE == 1) // NAND gate + begin + if(I[j] !== 1'bx) + tmpres = tmpres & ~I[j]; + else if(tmpres === 1'b1) + tmpres = 1'bx; + end + else if(C_GATE_TYPE == 2) // OR gate + begin + if(I[j] !== 1'bx) + tmpres = tmpres | ~I[j]; + else if(tmpres === 1'b0) + tmpres = 1'bx; + end + else if(C_GATE_TYPE == 3) // NOR gate + begin + if(I[j] !== 1'bx) + tmpres = tmpres | ~I[j]; + else if(tmpres === 1'b0) + tmpres = 1'bx; + end + else if(C_GATE_TYPE == 4) // XOR gate + begin + if(I[j] !== 1'bx) + tmpres = tmpres ^ ~I[j]; + else + tmpres = 1'bx; + end + else if(C_GATE_TYPE == 5) // XNOR gate + begin + if(I[j] !== 1'bx) + tmpres = tmpres ^ ~I[j]; + else + tmpres = 1'bx; + end + end + else // No input inversion on bit j of input + begin + if(C_GATE_TYPE == 0) // AND gate + begin + if(I[j] !== 1'bx) + tmpres = tmpres & I[j]; + else if(tmpres === 1'b1) + tmpres = 1'bx; + end + else if(C_GATE_TYPE == 1) // NAND gate + begin + if(I[j] !== 1'bx) + tmpres = tmpres & I[j]; + else if(tmpres === 1'b1) + tmpres = 1'bx; + end + else if(C_GATE_TYPE == 2) // OR gate + begin + if(I[j] !== 1'bx) + tmpres = tmpres | I[j]; + else if(tmpres === 1'b0) + tmpres = 1'bx; + end + else if(C_GATE_TYPE == 3) // NOR gate + begin + if(I[j] !== 1'bx) + tmpres = tmpres | I[j]; + else if(tmpres === 1'b0) + tmpres = 1'bx; + end + else if(C_GATE_TYPE == 4) // XOR gate + begin + if(I[j] !== 1'bx) + tmpres = tmpres ^ I[j]; + else + tmpres = 1'bx; + end + else if(C_GATE_TYPE == 5) // XNOR gate + begin + if(I[j] !== 1'bx) + tmpres = tmpres ^ I[j]; + else + tmpres = 1'bx; + end + end + end + + if(C_GATE_TYPE == 1 || C_GATE_TYPE == 3 || C_GATE_TYPE == 5) + tmpres = ~tmpres; + + intO <= tmpres; + + if(C_PIPE_STAGES < 2) // No pipeline + intQpipeend = intO; + else // Pipeline stages required + begin + intQpipeend = intQpipe[2]; + end + end + + always @(CLK) + lastCLK <= CLK; + + always@(I) + begin + if(C_GATE_TYPE == 0 || C_GATE_TYPE == 1) // AND or NAND gate? + tmpres = 1; + else + tmpres = 0; + for(j = 0; j < C_INPUTS; j = j + 1) + begin + if(tmpsig[j] == 1) + begin + if(C_GATE_TYPE == 0) // AND gate + begin + if(I[j] !== 1'bx) + tmpres = tmpres & ~I[j]; + else if(tmpres === 1'b1) + tmpres = 1'bx; + end + else if(C_GATE_TYPE == 1) // NAND gate + begin + if(I[j] !== 1'bx) + tmpres = tmpres & ~I[j]; + else if(tmpres === 1'b1) + tmpres = 1'bx; + end + else if(C_GATE_TYPE == 2) // OR gate + begin + if(I[j] !== 1'bx) + tmpres = tmpres | ~I[j]; + else if(tmpres === 1'b0) + tmpres = 1'bx; + end + else if(C_GATE_TYPE == 3) // NOR gate + begin + if(I[j] !== 1'bx) + tmpres = tmpres | ~I[j]; + else if(tmpres === 1'b0) + tmpres = 1'bx; + end + else if(C_GATE_TYPE == 4) // XOR gate + begin + if(I[j] !== 1'bx) + tmpres = tmpres ^ ~I[j]; + else + tmpres = 1'bx; + end + else if(C_GATE_TYPE == 5) // XNOR gate + begin + if(I[j] !== 1'bx) + tmpres = tmpres ^ ~I[j]; + else + tmpres = 1'bx; + end + end + else // No input inversion on bit j of input + begin + if(C_GATE_TYPE == 0) // AND gate + begin + if(I[j] !== 1'bx) + tmpres = tmpres & I[j]; + else if(tmpres === 1'b1) + tmpres = 1'bx; + end + else if(C_GATE_TYPE == 1) // NAND gate + begin + if(I[j] !== 1'bx) + tmpres = tmpres & I[j]; + else if(tmpres === 1'b1) + tmpres = 1'bx; + end + else if(C_GATE_TYPE == 2) // OR gate + begin + if(I[j] !== 1'bx) + tmpres = tmpres | I[j]; + else if(tmpres === 1'b0) + tmpres = 1'bx; + end + else if(C_GATE_TYPE == 3) // NOR gate + begin + if(I[j] !== 1'bx) + tmpres = tmpres | I[j]; + else if(tmpres === 1'b0) + tmpres = 1'bx; + end + else if(C_GATE_TYPE == 4) // XOR gate + begin + if(I[j] !== 1'bx) + tmpres = tmpres ^ I[j]; + else + tmpres = 1'bx; + end + else if(C_GATE_TYPE == 5) // XNOR gate + begin + if(I[j] !== 1'bx) + tmpres = tmpres ^ I[j]; + else + tmpres = 1'bx; + end + end + end + + if(C_GATE_TYPE == 1 || C_GATE_TYPE == 3 || C_GATE_TYPE == 5) + tmpres = ~tmpres; + + intO <= #1 tmpres; + end + + always@(posedge CLK) + begin + if(CLK === 1'b1 && lastCLK === 1'b0 && intCE === 1'b1) // OK! Update pipelines! + begin + for(pipe = 2; pipe <= C_PIPE_STAGES-1; pipe = pipe + 1) + begin + intQpipe[pipe] <= intQpipe[pipe+1]; + end + intQpipe[C_PIPE_STAGES] <= intO; + end + else if((CLK === 1'bx && lastCLK === 1'b0) || (CLK === 1'b1 && lastCLK === 1'bx) || intCE === 1'bx) // POSSIBLY Update pipelines! + begin + for(pipe = 2; pipe <= C_PIPE_STAGES-1; pipe = pipe + 1) + begin + if(intQpipe[pipe] !== intQpipe[pipe+1]) + intQpipe[pipe] <= 1'bx; + end + if(intQpipe[C_PIPE_STAGES] !== intO) + intQpipe[C_PIPE_STAGES] <= 1'bx; + end + end + + always@(intO or intQpipe[2]) + begin + if(C_PIPE_STAGES < 2) // No pipeline + intQpipeend <= intO; + else // Pipeline stages required + begin + intQpipeend <= intQpipe[2]; + end + end + + function defval; + input i; + input hassig; + input val; + begin + if(hassig == 1) + defval = i; + else + defval = val; + end + endfunction + + function [C_INPUTS - 1 : 0] to_bits; + input [C_INPUTS*8 : 1] instring; + integer i; + begin + for(i = C_INPUTS; i > 0; i = i - 1) + begin // Is this character a '0'? (ASCII = 48 = 00110000) + if(instring[(i*8)] == 0 && + instring[(i*8)-1] == 0 && + instring[(i*8)-2] == 1 && + instring[(i*8)-3] == 1 && + instring[(i*8)-4] == 0 && + instring[(i*8)-5] == 0 && + instring[(i*8)-6] == 0 && + instring[(i*8)-7] == 0) + to_bits[i-1] = 0; + // Or is it a '1'? + else if(instring[(i*8)] == 0 && + instring[(i*8)-1] == 0 && + instring[(i*8)-2] == 1 && + instring[(i*8)-3] == 1 && + instring[(i*8)-4] == 0 && + instring[(i*8)-5] == 0 && + instring[(i*8)-6] == 0 && + instring[(i*8)-7] == 1) + + to_bits[i-1] = 1; + // Or is it a ' '? (a null char - in which case insert a '0') + else if(instring[(i*8)] == 0 && + instring[(i*8)-1] == 0 && + instring[(i*8)-2] == 0 && + instring[(i*8)-3] == 0 && + instring[(i*8)-4] == 0 && + instring[(i*8)-5] == 0 && + instring[(i*8)-6] == 0 && + instring[(i*8)-7] == 0) + to_bits[i-1] = 0; + else + begin + $display("Error: non-binary digit in string \"%s\"\nExiting simulation...", instring); + $finish; + end + end + end + endfunction + +endmodule + +`undef c_set +`undef c_clear +`undef c_override +`undef c_no_override +`undef c_and +`undef c_nand +`undef c_or +`undef c_nor +`undef c_xor +`undef c_xnor + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/C_GATE_BIT_V5_0.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/C_GATE_BIT_V5_0.v new file mode 100644 index 0000000..4473495 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/C_GATE_BIT_V5_0.v @@ -0,0 +1,550 @@ +/* $Id: C_GATE_BIT_V5_0.v,v 1.17 2008/09/08 20:05:56 akennedy Exp $ +-- +-- Filename - C_GATE_BIT_V5_0.v +-- Author - Xilinx +-- Creation - 25 Jan 1999 +-- +-- Description - This file contains the Verilog behavior for the Baseblocks C_GATE_BIT_V5_0 module +*/ + +`timescale 1ns/10ps + +`define c_set 0 +`define c_clear 1 +`define c_override 0 +`define c_no_override 1 +`define c_and 0 +`define c_nand 1 +`define c_or 2 +`define c_nor 3 +`define c_xor 4 +`define c_xnor 5 + +module C_GATE_BIT_V5_0 (I, CLK, CE, ACLR, ASET, AINIT, SCLR, SSET, SINIT, T, EN, O, Q); + + parameter C_AINIT_VAL = "0"; + parameter C_ENABLE_RLOCS = 0; + parameter C_GATE_TYPE = `c_and; + parameter C_HAS_ACLR = 0; + parameter C_HAS_AINIT = 0; + parameter C_HAS_ASET = 0; + parameter C_HAS_CE = 0; + parameter C_HAS_O = 0; + parameter C_HAS_Q = 1; + parameter C_HAS_SCLR = 0; + parameter C_HAS_SINIT = 0; + parameter C_HAS_SSET = 0; + parameter C_INPUTS = 2; + parameter C_INPUT_INV_MASK = ""; + parameter C_PIPE_STAGES = 0; + parameter C_SINIT_VAL = "0"; + parameter C_SYNC_ENABLE = `c_override; + parameter C_SYNC_PRIORITY = `c_clear; + + + input [C_INPUTS-1 : 0] I; + input CLK; + input CE; + input ACLR; + input ASET; + input AINIT; + input SCLR; + input SSET; + input SINIT; + input T; + input EN; + output O; + output Q; + + // Internal values to drive signals when input is missing + wire intCE; + reg intO; + wire intQ; + reg lastCLK; + + reg [C_PIPE_STAGES+2 : 0] intQpipe; + reg intQpipeend; + + wire Q = (C_HAS_Q == 1 ? intQ : 1'bx); + wire O = (C_HAS_O == 1 ? intO : 1'bx); + + // Sort out default values for missing ports + + assign intCE = defval(CE, C_HAS_CE, 1); + + integer j; + integer pipe; + + reg [C_INPUTS-1 : 0] tmpsig; + reg tmpres; + + // Output register + C_REG_FD_V5_0 #(C_AINIT_VAL, C_ENABLE_RLOCS, C_HAS_ACLR, C_HAS_AINIT, C_HAS_ASET, + C_HAS_CE, C_HAS_SCLR, C_HAS_SINIT, C_HAS_SSET, + C_SINIT_VAL, C_SYNC_ENABLE, C_SYNC_PRIORITY, 1) + reg1 (.D(intQpipeend), .CLK(CLK), .CE(CE), .ACLR(ACLR), .ASET(ASET), + .AINIT(AINIT), .SCLR(SCLR), .SSET(SSET), .SINIT(SINIT), + .Q(intQ)); + + initial + begin + + #1; + + intQpipe = 'b0; + + if(C_GATE_TYPE == 0 || C_GATE_TYPE == 1) // AND or NAND gate? + tmpres = 1; + else + tmpres = 0; + + tmpsig = to_bits(C_INPUT_INV_MASK); + + for(j = 0; j < C_INPUTS; j = j + 1) + begin + if(tmpsig[j] == 1) + begin + if(C_GATE_TYPE == 0) // AND gate + begin + if(I[j] !== 1'bx) + tmpres = tmpres & ~I[j]; + else if(tmpres === 1'b1) + tmpres = 1'bx; + end + else if(C_GATE_TYPE == 1) // NAND gate + begin + if(I[j] !== 1'bx) + tmpres = tmpres & ~I[j]; + else if(tmpres === 1'b1) + tmpres = 1'bx; + end + else if(C_GATE_TYPE == 2) // OR gate + begin + if(I[j] !== 1'bx) + tmpres = tmpres | ~I[j]; + else if(tmpres === 1'b0) + tmpres = 1'bx; + end + else if(C_GATE_TYPE == 3) // NOR gate + begin + if(I[j] !== 1'bx) + tmpres = tmpres | ~I[j]; + else if(tmpres === 1'b0) + tmpres = 1'bx; + end + else if(C_GATE_TYPE == 4) // XOR gate + begin + if(I[j] !== 1'bx) + tmpres = tmpres ^ ~I[j]; + else + tmpres = 1'bx; + end + else if(C_GATE_TYPE == 5) // XNOR gate + begin + if(I[j] !== 1'bx) + tmpres = tmpres ^ ~I[j]; + else + tmpres = 1'bx; + end + else if(C_GATE_TYPE == 7) // Buffer + begin + if(I[j] !== 1'bx) + tmpres = ~I[j]; + else + tmpres = 1'bx; + end + else if(C_GATE_TYPE == 8) // BUFT + begin + if(I[j] !== 1'bx) + tmpres = ~I[j]; + else + tmpres = 1'bx; + end + else if(C_GATE_TYPE == 9) // BUFE + begin + if(I[j] !== 1'bx) + tmpres = ~I[j]; + else + tmpres = 1'bx; + end + else // INV gate + begin + if(I[j] !== 1'bx) + tmpres = ~I[j]; + else + tmpres = 1'bx; + end + end + else // No input inversion on bit j of input + begin + if(C_GATE_TYPE == 0) // AND gate + begin + if(I[j] !== 1'bx) + tmpres = tmpres & I[j]; + else if(tmpres === 1'b1) + tmpres = 1'bx; + end + else if(C_GATE_TYPE == 1) // NAND gate + begin + if(I[j] !== 1'bx) + tmpres = tmpres & I[j]; + else if(tmpres === 1'b1) + tmpres = 1'bx; + end + else if(C_GATE_TYPE == 2) // OR gate + begin + if(I[j] !== 1'bx) + tmpres = tmpres | I[j]; + else if(tmpres === 1'b0) + tmpres = 1'bx; + end + else if(C_GATE_TYPE == 3) // NOR gate + begin + if(I[j] !== 1'bx) + tmpres = tmpres | I[j]; + else if(tmpres === 1'b0) + tmpres = 1'bx; + end + else if(C_GATE_TYPE == 4) // XOR gate + begin + if(I[j] !== 1'bx) + tmpres = tmpres ^ I[j]; + else + tmpres = 1'bx; + end + else if(C_GATE_TYPE == 5) // XNOR gate + begin + if(I[j] !== 1'bx) + tmpres = tmpres ^ I[j]; + else + tmpres = 1'bx; + end + else if(C_GATE_TYPE == 7) // Buffer + begin + if(I[j] !== 1'bx) + tmpres = I[j]; + else + tmpres = 1'bx; + end + else if(C_GATE_TYPE == 8) // BUFT + begin + if(I[j] !== 1'bx) + if (T == 0) + tmpres = I[j]; + else + tmpres = 1'b1; + else + tmpres = 1'b1; + end + else if(C_GATE_TYPE == 9) // BUFE + begin + if(I[j] !== 1'bx) + if (EN == 0) + tmpres = I[j]; + else + tmpres = 1'b1; + else + tmpres = 1'b1; + end + else // INV gate + begin + if(I[j] !== 1'bx) + tmpres = I[j]; + else + tmpres = 1'bx; + end + end + end + + if(C_GATE_TYPE == 1 || C_GATE_TYPE == 3 || C_GATE_TYPE == 5 || C_GATE_TYPE == 6) + tmpres = ~tmpres; + + intO <= tmpres; + + if(C_PIPE_STAGES < 2) // No pipeline + intQpipeend = intO; + else // Pipeline stages required + begin + intQpipeend = intQpipe[2]; + end + end + + always @(CLK) + lastCLK <= CLK; + + always@(I or T or EN) + begin + if(C_GATE_TYPE == 0 || C_GATE_TYPE == 1) // AND or NAND gate? + tmpres = 1; + else + tmpres = 0; + for(j = 0; j < C_INPUTS; j = j + 1) + begin + if(tmpsig[j] == 1) + begin + if(C_GATE_TYPE == 0) // AND gate + begin + if(I[j] !== 1'bx) + tmpres = tmpres & ~I[j]; + else if(tmpres === 1'b1) + tmpres = 1'bx; + end + else if(C_GATE_TYPE == 1) // NAND gate + begin + if(I[j] !== 1'bx) + tmpres = tmpres & ~I[j]; + else if(tmpres === 1'b1) + tmpres = 1'bx; + end + else if(C_GATE_TYPE == 2) // OR gate + begin + if(I[j] !== 1'bx) + tmpres = tmpres | ~I[j]; + else if(tmpres === 1'b0) + tmpres = 1'bx; + end + else if(C_GATE_TYPE == 3) // NOR gate + begin + if(I[j] !== 1'bx) + tmpres = tmpres | ~I[j]; + else if(tmpres === 1'b0) + tmpres = 1'bx; + end + else if(C_GATE_TYPE == 4) // XOR gate + begin + if(I[j] !== 1'bx) + tmpres = tmpres ^ ~I[j]; + else + tmpres = 1'bx; + end + else if(C_GATE_TYPE == 5) // XNOR gate + begin + if(I[j] !== 1'bx) + tmpres = tmpres ^ ~I[j]; + else + tmpres = 1'bx; + end + else if(C_GATE_TYPE == 7 ) // Buffer + begin + if(I[j] !== 1'bx) + tmpres = ~I[j]; + else + tmpres = 1'bx; + end + else if(C_GATE_TYPE == 8) // BUFT + begin + if(I[j] !== 1'bx) + if (T == 0) + tmpres = ~I[j]; + else + tmpres = 1'b1; + else + tmpres = 1'bx; + end + else if(C_GATE_TYPE == 9) // BUFE + begin + if(I[j] !== 1'bx) + if (EN == 0) + tmpres = ~I[j]; + else + tmpres = 1'b1; + else + tmpres = 1'bx; + end + else // INV gate + begin + if(I[j] !== 1'bx) + tmpres = ~I[j]; + else + tmpres = 1'bx; + end + end + else // No input inversion on bit j of input + begin + if(C_GATE_TYPE == 0) // AND gate + begin + if(I[j] !== 1'bx) + tmpres = tmpres & I[j]; + else if(tmpres === 1'b1) + tmpres = 1'bx; + end + else if(C_GATE_TYPE == 1) // NAND gate + begin + if(I[j] !== 1'bx) + tmpres = tmpres & I[j]; + else if(tmpres === 1'b1) + tmpres = 1'bx; + end + else if(C_GATE_TYPE == 2) // OR gate + begin + if(I[j] !== 1'bx) + tmpres = tmpres | I[j]; + else if(tmpres === 1'b0) + tmpres = 1'bx; + end + else if(C_GATE_TYPE == 3) // NOR gate + begin + if(I[j] !== 1'bx) + tmpres = tmpres | I[j]; + else if(tmpres === 1'b0) + tmpres = 1'bx; + end + else if(C_GATE_TYPE == 4) // XOR gate + begin + if(I[j] !== 1'bx) + tmpres = tmpres ^ I[j]; + else + tmpres = 1'bx; + end + else if(C_GATE_TYPE == 5) // XNOR gate + begin + if(I[j] !== 1'bx) + tmpres = tmpres ^ I[j]; + else + tmpres = 1'bx; + end + else if(C_GATE_TYPE == 7) // Buffer + begin + if(I[j] !== 1'bx) + tmpres = I[j]; + else + tmpres = 1'bx; + end + else if(C_GATE_TYPE == 8) // BUFT + begin + if(I[j] !== 1'bx) + if (T == 0) + tmpres = I[j]; + else + tmpres = 1'b1; + else + tmpres = 1'b1; + end + else if(C_GATE_TYPE == 9) // BUFE + begin + if(I[j] !== 1'bx) + if (EN == 0) + tmpres = I[j]; + else + tmpres = 1'b1; + else + tmpres = 1'b1; + end + + else // INV gate + begin + if(I[j] !== 1'bx) + tmpres = I[j]; + else + tmpres = 1'bx; + end + end + end + + if(C_GATE_TYPE == 1 || C_GATE_TYPE == 3 || C_GATE_TYPE == 5 || C_GATE_TYPE == 6) + tmpres = ~tmpres; + + intO <= #1 tmpres; + end + + always@(posedge CLK) + begin + if(CLK === 1'b1 && lastCLK === 1'b0 && intCE === 1'b1) // OK! Update pipelines! + begin + for(pipe = 2; pipe <= C_PIPE_STAGES-1; pipe = pipe + 1) + begin + intQpipe[pipe] <= intQpipe[pipe+1]; + end + intQpipe[C_PIPE_STAGES] <= intO; + end + else if((CLK === 1'bx && lastCLK === 1'b0) || (CLK === 1'b1 && lastCLK === 1'bx) || intCE === 1'bx) // POSSIBLY Update pipelines! + begin + for(pipe = 2; pipe <= C_PIPE_STAGES-1; pipe = pipe + 1) + begin + if(intQpipe[pipe] !== intQpipe[pipe+1]) + intQpipe[pipe] <= 1'bx; + end + if(intQpipe[C_PIPE_STAGES] !== intO) + intQpipe[C_PIPE_STAGES] <= 1'bx; + end + end + + always@(intO or intQpipe[2]) + begin + if(C_PIPE_STAGES < 2) // No pipeline + intQpipeend <= intO; + else // Pipeline stages required + begin + intQpipeend <= intQpipe[2]; + end + end + + function defval; + input i; + input hassig; + input val; + begin + if(hassig == 1) + defval = i; + else + defval = val; + end + endfunction + + function [C_INPUTS - 1 : 0] to_bits; + input [C_INPUTS*8 : 1] instring; + integer i; + begin + for(i = C_INPUTS; i > 0; i = i - 1) + begin // Is this character a '0'? (ASCII = 48 = 00110000) + if(instring[(i*8)] == 0 && + instring[(i*8)-1] == 0 && + instring[(i*8)-2] == 1 && + instring[(i*8)-3] == 1 && + instring[(i*8)-4] == 0 && + instring[(i*8)-5] == 0 && + instring[(i*8)-6] == 0 && + instring[(i*8)-7] == 0) + to_bits[i-1] = 0; + // Or is it a '1'? + else if(instring[(i*8)] == 0 && + instring[(i*8)-1] == 0 && + instring[(i*8)-2] == 1 && + instring[(i*8)-3] == 1 && + instring[(i*8)-4] == 0 && + instring[(i*8)-5] == 0 && + instring[(i*8)-6] == 0 && + instring[(i*8)-7] == 1) + + to_bits[i-1] = 1; + // Or is it a ' '? (a null char - in which case insert a '0') + else if(instring[(i*8)] == 0 && + instring[(i*8)-1] == 0 && + instring[(i*8)-2] == 0 && + instring[(i*8)-3] == 0 && + instring[(i*8)-4] == 0 && + instring[(i*8)-5] == 0 && + instring[(i*8)-6] == 0 && + instring[(i*8)-7] == 0) + to_bits[i-1] = 0; + else + begin + $display("Error in %m at time %d ns: non-binary digit in string \"%s\"\nExiting simulation...", $time, instring); + $finish; + end + end + end + endfunction + +endmodule + +`undef c_set +`undef c_clear +`undef c_override +`undef c_no_override +`undef c_and +`undef c_nand +`undef c_or +`undef c_nor +`undef c_xor +`undef c_xnor diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/C_GATE_BIT_V6_0.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/C_GATE_BIT_V6_0.v new file mode 100644 index 0000000..43c04c5 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/C_GATE_BIT_V6_0.v @@ -0,0 +1,559 @@ +// Copyright(C) 2002 by Xilinx, Inc. All rights reserved. +// This text contains proprietary, confidential +// information of Xilinx, Inc., is distributed +// under license from Xilinx, Inc., and may be used, +// copied and/or disclosed only pursuant to the terms +// of a valid license agreement with Xilinx, Inc. This copyright +// notice must be retained as part of this text at all times. + + +/* $Id: C_GATE_BIT_V6_0.v,v 1.16 2008/09/08 20:06:04 akennedy Exp $ +-- +-- Filename - C_GATE_BIT_V6_0.v +-- Author - Xilinx +-- Creation - 25 Jan 1999 +-- +-- Description - This file contains the Verilog behavior for the Baseblocks C_GATE_BIT_V6_0 module +*/ + +`timescale 1ns/10ps + +`define c_set 0 +`define c_clear 1 +`define c_override 0 +`define c_no_override 1 +`define c_and 0 +`define c_nand 1 +`define c_or 2 +`define c_nor 3 +`define c_xor 4 +`define c_xnor 5 + +module C_GATE_BIT_V6_0 (I, CLK, CE, ACLR, ASET, AINIT, SCLR, SSET, SINIT, T, EN, O, Q); + + parameter C_AINIT_VAL = "0"; + parameter C_ENABLE_RLOCS = 0; + parameter C_GATE_TYPE = `c_and; + parameter C_HAS_ACLR = 0; + parameter C_HAS_AINIT = 0; + parameter C_HAS_ASET = 0; + parameter C_HAS_CE = 0; + parameter C_HAS_O = 0; + parameter C_HAS_Q = 1; + parameter C_HAS_SCLR = 0; + parameter C_HAS_SINIT = 0; + parameter C_HAS_SSET = 0; + parameter C_INPUTS = 2; + parameter C_INPUT_INV_MASK = ""; + parameter C_PIPE_STAGES = 0; + parameter C_SINIT_VAL = "0"; + parameter C_SYNC_ENABLE = `c_override; + parameter C_SYNC_PRIORITY = `c_clear; + + + input [C_INPUTS-1 : 0] I; + input CLK; + input CE; + input ACLR; + input ASET; + input AINIT; + input SCLR; + input SSET; + input SINIT; + input T; + input EN; + output O; + output Q; + + // Internal values to drive signals when input is missing + wire intCE; + reg intO; + wire intQ; + reg lastCLK; + + reg [C_PIPE_STAGES+2 : 0] intQpipe; + reg intQpipeend; + + wire Q = (C_HAS_Q == 1 ? intQ : 1'bx); + wire O = (C_HAS_O == 1 ? intO : 1'bx); + + // Sort out default values for missing ports + + assign intCE = defval(CE, C_HAS_CE, 1); + + integer j; + integer pipe; + + reg [C_INPUTS-1 : 0] tmpsig; + reg tmpres; + + // Output register + C_REG_FD_V6_0 #(C_AINIT_VAL, C_ENABLE_RLOCS, C_HAS_ACLR, C_HAS_AINIT, C_HAS_ASET, + C_HAS_CE, C_HAS_SCLR, C_HAS_SINIT, C_HAS_SSET, + C_SINIT_VAL, C_SYNC_ENABLE, C_SYNC_PRIORITY, 1) + reg1 (.D(intQpipeend), .CLK(CLK), .CE(CE), .ACLR(ACLR), .ASET(ASET), + .AINIT(AINIT), .SCLR(SCLR), .SSET(SSET), .SINIT(SINIT), + .Q(intQ)); + + initial + begin + +// #1; + + intQpipe = 'b0; + + if(C_GATE_TYPE == 0 || C_GATE_TYPE == 1) // AND or NAND gate? + tmpres = 1; + else + tmpres = 0; + + tmpsig = to_bits(C_INPUT_INV_MASK); + + for(j = 0; j < C_INPUTS; j = j + 1) + begin + if(tmpsig[j] == 1) + begin + if(C_GATE_TYPE == 0) // AND gate + begin + if(I[j] !== 1'bx) + tmpres = tmpres & ~I[j]; + else if(tmpres === 1'b1) + tmpres = 1'bx; + end + else if(C_GATE_TYPE == 1) // NAND gate + begin + if(I[j] !== 1'bx) + tmpres = tmpres & ~I[j]; + else if(tmpres === 1'b1) + tmpres = 1'bx; + end + else if(C_GATE_TYPE == 2) // OR gate + begin + if(I[j] !== 1'bx) + tmpres = tmpres | ~I[j]; + else if(tmpres === 1'b0) + tmpres = 1'bx; + end + else if(C_GATE_TYPE == 3) // NOR gate + begin + if(I[j] !== 1'bx) + tmpres = tmpres | ~I[j]; + else if(tmpres === 1'b0) + tmpres = 1'bx; + end + else if(C_GATE_TYPE == 4) // XOR gate + begin + if(I[j] !== 1'bx) + tmpres = tmpres ^ ~I[j]; + else + tmpres = 1'bx; + end + else if(C_GATE_TYPE == 5) // XNOR gate + begin + if(I[j] !== 1'bx) + tmpres = tmpres ^ ~I[j]; + else + tmpres = 1'bx; + end + else if(C_GATE_TYPE == 7) // Buffer + begin + if(I[j] !== 1'bx) + tmpres = ~I[j]; + else + tmpres = 1'bx; + end + else if(C_GATE_TYPE == 8) // BUFT + begin + if(I[j] !== 1'bx) + tmpres = ~I[j]; + else + tmpres = 1'bx; + end + else if(C_GATE_TYPE == 9) // BUFE + begin + if(I[j] !== 1'bx) + tmpres = ~I[j]; + else + tmpres = 1'bx; + end + else // INV gate + begin + if(I[j] !== 1'bx) + tmpres = ~I[j]; + else + tmpres = 1'bx; + end + end + else // No input inversion on bit j of input + begin + if(C_GATE_TYPE == 0) // AND gate + begin + if(I[j] !== 1'bx) + tmpres = tmpres & I[j]; + else if(tmpres === 1'b1) + tmpres = 1'bx; + end + else if(C_GATE_TYPE == 1) // NAND gate + begin + if(I[j] !== 1'bx) + tmpres = tmpres & I[j]; + else if(tmpres === 1'b1) + tmpres = 1'bx; + end + else if(C_GATE_TYPE == 2) // OR gate + begin + if(I[j] !== 1'bx) + tmpres = tmpres | I[j]; + else if(tmpres === 1'b0) + tmpres = 1'bx; + end + else if(C_GATE_TYPE == 3) // NOR gate + begin + if(I[j] !== 1'bx) + tmpres = tmpres | I[j]; + else if(tmpres === 1'b0) + tmpres = 1'bx; + end + else if(C_GATE_TYPE == 4) // XOR gate + begin + if(I[j] !== 1'bx) + tmpres = tmpres ^ I[j]; + else + tmpres = 1'bx; + end + else if(C_GATE_TYPE == 5) // XNOR gate + begin + if(I[j] !== 1'bx) + tmpres = tmpres ^ I[j]; + else + tmpres = 1'bx; + end + else if(C_GATE_TYPE == 7) // Buffer + begin + if(I[j] !== 1'bx) + tmpres = I[j]; + else + tmpres = 1'bx; + end + else if(C_GATE_TYPE == 8) // BUFT + begin + if(I[j] !== 1'bx) + if (T == 0) + tmpres = I[j]; + else + tmpres = 1'b1; + else + tmpres = 1'b1; + end + else if(C_GATE_TYPE == 9) // BUFE + begin + if(I[j] !== 1'bx) + if (EN == 0) + tmpres = I[j]; + else + tmpres = 1'b1; + else + tmpres = 1'b1; + end + else // INV gate + begin + if(I[j] !== 1'bx) + tmpres = I[j]; + else + tmpres = 1'bx; + end + end + end + + if(C_GATE_TYPE == 1 || C_GATE_TYPE == 3 || C_GATE_TYPE == 5 || C_GATE_TYPE == 6) + tmpres = ~tmpres; + + intO <= tmpres; + + if(C_PIPE_STAGES < 2) // No pipeline + intQpipeend = intO; + else // Pipeline stages required + begin + intQpipeend = intQpipe[2]; + end + end + + always @(CLK) + lastCLK <= CLK; + + always@(I or T or EN) + begin + if(C_GATE_TYPE == 0 || C_GATE_TYPE == 1) // AND or NAND gate? + tmpres = 1; + else + tmpres = 0; + for(j = 0; j < C_INPUTS; j = j + 1) + begin + if(tmpsig[j] == 1) + begin + if(C_GATE_TYPE == 0) // AND gate + begin + if(I[j] !== 1'bx) + tmpres = tmpres & ~I[j]; + else if(tmpres === 1'b1) + tmpres = 1'bx; + end + else if(C_GATE_TYPE == 1) // NAND gate + begin + if(I[j] !== 1'bx) + tmpres = tmpres & ~I[j]; + else if(tmpres === 1'b1) + tmpres = 1'bx; + end + else if(C_GATE_TYPE == 2) // OR gate + begin + if(I[j] !== 1'bx) + tmpres = tmpres | ~I[j]; + else if(tmpres === 1'b0) + tmpres = 1'bx; + end + else if(C_GATE_TYPE == 3) // NOR gate + begin + if(I[j] !== 1'bx) + tmpres = tmpres | ~I[j]; + else if(tmpres === 1'b0) + tmpres = 1'bx; + end + else if(C_GATE_TYPE == 4) // XOR gate + begin + if(I[j] !== 1'bx) + tmpres = tmpres ^ ~I[j]; + else + tmpres = 1'bx; + end + else if(C_GATE_TYPE == 5) // XNOR gate + begin + if(I[j] !== 1'bx) + tmpres = tmpres ^ ~I[j]; + else + tmpres = 1'bx; + end + else if(C_GATE_TYPE == 7 ) // Buffer + begin + if(I[j] !== 1'bx) + tmpres = ~I[j]; + else + tmpres = 1'bx; + end + else if(C_GATE_TYPE == 8) // BUFT + begin + if(I[j] !== 1'bx) + if (T == 0) + tmpres = ~I[j]; + else + tmpres = 1'b1; + else + tmpres = 1'bx; + end + else if(C_GATE_TYPE == 9) // BUFE + begin + if(I[j] !== 1'bx) + if (EN == 0) + tmpres = ~I[j]; + else + tmpres = 1'b1; + else + tmpres = 1'bx; + end + else // INV gate + begin + if(I[j] !== 1'bx) + tmpres = ~I[j]; + else + tmpres = 1'bx; + end + end + else // No input inversion on bit j of input + begin + if(C_GATE_TYPE == 0) // AND gate + begin + if(I[j] !== 1'bx) + tmpres = tmpres & I[j]; + else if(tmpres === 1'b1) + tmpres = 1'bx; + end + else if(C_GATE_TYPE == 1) // NAND gate + begin + if(I[j] !== 1'bx) + tmpres = tmpres & I[j]; + else if(tmpres === 1'b1) + tmpres = 1'bx; + end + else if(C_GATE_TYPE == 2) // OR gate + begin + if(I[j] !== 1'bx) + tmpres = tmpres | I[j]; + else if(tmpres === 1'b0) + tmpres = 1'bx; + end + else if(C_GATE_TYPE == 3) // NOR gate + begin + if(I[j] !== 1'bx) + tmpres = tmpres | I[j]; + else if(tmpres === 1'b0) + tmpres = 1'bx; + end + else if(C_GATE_TYPE == 4) // XOR gate + begin + if(I[j] !== 1'bx) + tmpres = tmpres ^ I[j]; + else + tmpres = 1'bx; + end + else if(C_GATE_TYPE == 5) // XNOR gate + begin + if(I[j] !== 1'bx) + tmpres = tmpres ^ I[j]; + else + tmpres = 1'bx; + end + else if(C_GATE_TYPE == 7) // Buffer + begin + if(I[j] !== 1'bx) + tmpres = I[j]; + else + tmpres = 1'bx; + end + else if(C_GATE_TYPE == 8) // BUFT + begin + if(I[j] !== 1'bx) + if (T == 0) + tmpres = I[j]; + else + tmpres = 1'b1; + else + tmpres = 1'b1; + end + else if(C_GATE_TYPE == 9) // BUFE + begin + if(I[j] !== 1'bx) + if (EN == 0) + tmpres = I[j]; + else + tmpres = 1'b1; + else + tmpres = 1'b1; + end + + else // INV gate + begin + if(I[j] !== 1'bx) + tmpres = I[j]; + else + tmpres = 1'bx; + end + end + end + + if(C_GATE_TYPE == 1 || C_GATE_TYPE == 3 || C_GATE_TYPE == 5 || C_GATE_TYPE == 6) + tmpres = ~tmpres; + + intO <= #1 tmpres; + end + + always@(posedge CLK) + begin + if(CLK === 1'b1 && lastCLK === 1'b0 && intCE === 1'b1) // OK! Update pipelines! + begin + for(pipe = 2; pipe <= C_PIPE_STAGES-1; pipe = pipe + 1) + begin + intQpipe[pipe] <= intQpipe[pipe+1]; + end + intQpipe[C_PIPE_STAGES] <= intO; + end + else if((CLK === 1'bx && lastCLK === 1'b0) || (CLK === 1'b1 && lastCLK === 1'bx) || intCE === 1'bx) // POSSIBLY Update pipelines! + begin + for(pipe = 2; pipe <= C_PIPE_STAGES-1; pipe = pipe + 1) + begin + if(intQpipe[pipe] !== intQpipe[pipe+1]) + intQpipe[pipe] <= 1'bx; + end + if(intQpipe[C_PIPE_STAGES] !== intO) + intQpipe[C_PIPE_STAGES] <= 1'bx; + end + end + + always@(intO or intQpipe[2]) + begin + if(C_PIPE_STAGES < 2) // No pipeline + intQpipeend <= intO; + else // Pipeline stages required + begin + intQpipeend <= intQpipe[2]; + end + end + + function defval; + input i; + input hassig; + input val; + begin + if(hassig == 1) + defval = i; + else + defval = val; + end + endfunction + + function [C_INPUTS - 1 : 0] to_bits; + input [C_INPUTS*8 : 1] instring; + integer i; + begin + for(i = C_INPUTS; i > 0; i = i - 1) + begin // Is this character a '0'? (ASCII = 48 = 00110000) + if(instring[(i*8)] == 0 && + instring[(i*8)-1] == 0 && + instring[(i*8)-2] == 1 && + instring[(i*8)-3] == 1 && + instring[(i*8)-4] == 0 && + instring[(i*8)-5] == 0 && + instring[(i*8)-6] == 0 && + instring[(i*8)-7] == 0) + to_bits[i-1] = 0; + // Or is it a '1'? + else if(instring[(i*8)] == 0 && + instring[(i*8)-1] == 0 && + instring[(i*8)-2] == 1 && + instring[(i*8)-3] == 1 && + instring[(i*8)-4] == 0 && + instring[(i*8)-5] == 0 && + instring[(i*8)-6] == 0 && + instring[(i*8)-7] == 1) + + to_bits[i-1] = 1; + // Or is it a ' '? (a null char - in which case insert a '0') + else if(instring[(i*8)] == 0 && + instring[(i*8)-1] == 0 && + instring[(i*8)-2] == 0 && + instring[(i*8)-3] == 0 && + instring[(i*8)-4] == 0 && + instring[(i*8)-5] == 0 && + instring[(i*8)-6] == 0 && + instring[(i*8)-7] == 0) + to_bits[i-1] = 0; + else + begin + $display("Error in %m at time %d ns: non-binary digit in string \"%s\"\nExiting simulation...", $time, instring); + $finish; + end + end + end + endfunction + +endmodule + +`undef c_set +`undef c_clear +`undef c_override +`undef c_no_override +`undef c_and +`undef c_nand +`undef c_or +`undef c_nor +`undef c_xor +`undef c_xnor diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/C_GATE_BIT_V7_0.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/C_GATE_BIT_V7_0.v new file mode 100644 index 0000000..8036fba --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/C_GATE_BIT_V7_0.v @@ -0,0 +1,588 @@ +// Copyright(C) 2003 by Xilinx, Inc. All rights reserved. +// This text/file contains proprietary, confidential +// information of Xilinx, Inc., is distributed under license +// from Xilinx, Inc., and may be used, copied and/or +// disclosed only pursuant to the terms of a valid license +// agreement with Xilinx, Inc. Xilinx hereby grants you +// a license to use this text/file solely for design, simulation, +// implementation and creation of design files limited +// to Xilinx devices or technologies. Use with non-Xilinx +// devices or technologies is expressly prohibited and +// immediately terminates your license unless covered by +// a separate agreement. +// +// Xilinx is providing this design, code, or information +// "as is" solely for use in developing programs and +// solutions for Xilinx devices. By providing this design, +// code, or information as one possible implementation of +// this feature, application or standard, Xilinx is making no +// representation that this implementation is free from any +// claims of infringement. You are responsible for +// obtaining any rights you may require for your implementation. +// Xilinx expressly disclaims any warranty whatsoever with +// respect to the adequacy of the implementation, including +// but not limited to any warranties or representations that this +// implementation is free from claims of infringement, implied +// warranties of merchantability or fitness for a particular +// purpose. +// +// Xilinx products are not intended for use in life support +// appliances, devices, or systems. Use in such applications are +// expressly prohibited. +// +// This copyright and support notice must be retained as part +// of this text at all times. (c) Copyright 1995-2003 Xilinx, Inc. +// All rights reserved. + + + +/* $Id: C_GATE_BIT_V7_0.v,v 1.13 2008/09/08 20:06:13 akennedy Exp $ +-- +-- Filename - C_GATE_BIT_V7_0.v +-- Author - Xilinx +-- Creation - 25 Jan 1999 +-- +-- Description - This file contains the Verilog behavior for the Baseblocks C_GATE_BIT_V7_0 module +*/ + +`timescale 1ns/10ps + +`define c_set 0 +`define c_clear 1 +`define c_override 0 +`define c_no_override 1 +`define c_and 0 +`define c_nand 1 +`define c_or 2 +`define c_nor 3 +`define c_xor 4 +`define c_xnor 5 + +module C_GATE_BIT_V7_0 (I, CLK, CE, ACLR, ASET, AINIT, SCLR, SSET, SINIT, T, EN, O, Q); + + parameter C_AINIT_VAL = "0"; + parameter C_ENABLE_RLOCS = 0; + parameter C_GATE_TYPE = `c_and; + parameter C_HAS_ACLR = 0; + parameter C_HAS_AINIT = 0; + parameter C_HAS_ASET = 0; + parameter C_HAS_CE = 0; + parameter C_HAS_O = 0; + parameter C_HAS_Q = 1; + parameter C_HAS_SCLR = 0; + parameter C_HAS_SINIT = 0; + parameter C_HAS_SSET = 0; + parameter C_INPUTS = 2; + parameter C_INPUT_INV_MASK = ""; + parameter C_PIPE_STAGES = 0; + parameter C_SINIT_VAL = "0"; + parameter C_SYNC_ENABLE = `c_override; + parameter C_SYNC_PRIORITY = `c_clear; + + + input [C_INPUTS-1 : 0] I; + input CLK; + input CE; + input ACLR; + input ASET; + input AINIT; + input SCLR; + input SSET; + input SINIT; + input T; + input EN; + output O; + output Q; + + // Internal values to drive signals when input is missing + wire intCE; + reg intO; + wire intQ; + reg lastCLK; + + reg [C_PIPE_STAGES+2 : 0] intQpipe; + reg intQpipeend; + + wire Q = (C_HAS_Q == 1 ? intQ : 1'bx); + wire O = (C_HAS_O == 1 ? intO : 1'bx); + + // Sort out default values for missing ports + + assign intCE = defval(CE, C_HAS_CE, 1); + + integer j; + integer pipe; + + reg [C_INPUTS-1 : 0] tmpsig; + reg tmpres; + + // Output register + C_REG_FD_V7_0 #(C_AINIT_VAL, C_ENABLE_RLOCS, C_HAS_ACLR, C_HAS_AINIT, C_HAS_ASET, + C_HAS_CE, C_HAS_SCLR, C_HAS_SINIT, C_HAS_SSET, + C_SINIT_VAL, C_SYNC_ENABLE, C_SYNC_PRIORITY, 1) + reg1 (.D(intQpipeend), .CLK(CLK), .CE(CE), .ACLR(ACLR), .ASET(ASET), + .AINIT(AINIT), .SCLR(SCLR), .SSET(SSET), .SINIT(SINIT), + .Q(intQ)); + + initial + begin + +// #1; + + intQpipe = 'b0; + + if(C_GATE_TYPE == 0 || C_GATE_TYPE == 1) // AND or NAND gate? + tmpres = 1; + else + tmpres = 0; + + tmpsig = to_bits(C_INPUT_INV_MASK); + + for(j = 0; j < C_INPUTS; j = j + 1) + begin + if(tmpsig[j] == 1) + begin + if(C_GATE_TYPE == 0) // AND gate + begin + if(I[j] !== 1'bx) + tmpres = tmpres & ~I[j]; + else if(tmpres === 1'b1) + tmpres = 1'bx; + end + else if(C_GATE_TYPE == 1) // NAND gate + begin + if(I[j] !== 1'bx) + tmpres = tmpres & ~I[j]; + else if(tmpres === 1'b1) + tmpres = 1'bx; + end + else if(C_GATE_TYPE == 2) // OR gate + begin + if(I[j] !== 1'bx) + tmpres = tmpres | ~I[j]; + else if(tmpres === 1'b0) + tmpres = 1'bx; + end + else if(C_GATE_TYPE == 3) // NOR gate + begin + if(I[j] !== 1'bx) + tmpres = tmpres | ~I[j]; + else if(tmpres === 1'b0) + tmpres = 1'bx; + end + else if(C_GATE_TYPE == 4) // XOR gate + begin + if(I[j] !== 1'bx) + tmpres = tmpres ^ ~I[j]; + else + tmpres = 1'bx; + end + else if(C_GATE_TYPE == 5) // XNOR gate + begin + if(I[j] !== 1'bx) + tmpres = tmpres ^ ~I[j]; + else + tmpres = 1'bx; + end + else if(C_GATE_TYPE == 7) // Buffer + begin + if(I[j] !== 1'bx) + tmpres = ~I[j]; + else + tmpres = 1'bx; + end + else if(C_GATE_TYPE == 8) // BUFT + begin + if(I[j] !== 1'bx) + tmpres = ~I[j]; + else + tmpres = 1'bx; + end + else if(C_GATE_TYPE == 9) // BUFE + begin + if(I[j] !== 1'bx) + tmpres = ~I[j]; + else + tmpres = 1'bx; + end + else // INV gate + begin + if(I[j] !== 1'bx) + tmpres = ~I[j]; + else + tmpres = 1'bx; + end + end + else // No input inversion on bit j of input + begin + if(C_GATE_TYPE == 0) // AND gate + begin + if(I[j] !== 1'bx) + tmpres = tmpres & I[j]; + else if(tmpres === 1'b1) + tmpres = 1'bx; + end + else if(C_GATE_TYPE == 1) // NAND gate + begin + if(I[j] !== 1'bx) + tmpres = tmpres & I[j]; + else if(tmpres === 1'b1) + tmpres = 1'bx; + end + else if(C_GATE_TYPE == 2) // OR gate + begin + if(I[j] !== 1'bx) + tmpres = tmpres | I[j]; + else if(tmpres === 1'b0) + tmpres = 1'bx; + end + else if(C_GATE_TYPE == 3) // NOR gate + begin + if(I[j] !== 1'bx) + tmpres = tmpres | I[j]; + else if(tmpres === 1'b0) + tmpres = 1'bx; + end + else if(C_GATE_TYPE == 4) // XOR gate + begin + if(I[j] !== 1'bx) + tmpres = tmpres ^ I[j]; + else + tmpres = 1'bx; + end + else if(C_GATE_TYPE == 5) // XNOR gate + begin + if(I[j] !== 1'bx) + tmpres = tmpres ^ I[j]; + else + tmpres = 1'bx; + end + else if(C_GATE_TYPE == 7) // Buffer + begin + if(I[j] !== 1'bx) + tmpres = I[j]; + else + tmpres = 1'bx; + end + else if(C_GATE_TYPE == 8) // BUFT + begin + if(I[j] !== 1'bx) + if (T == 0) + tmpres = I[j]; + else + tmpres = 1'b1; + else + tmpres = 1'b1; + end + else if(C_GATE_TYPE == 9) // BUFE + begin + if(I[j] !== 1'bx) + if (EN == 0) + tmpres = I[j]; + else + tmpres = 1'b1; + else + tmpres = 1'b1; + end + else // INV gate + begin + if(I[j] !== 1'bx) + tmpres = I[j]; + else + tmpres = 1'bx; + end + end + end + + if(C_GATE_TYPE == 1 || C_GATE_TYPE == 3 || C_GATE_TYPE == 5 || C_GATE_TYPE == 6) + tmpres = ~tmpres; + + intO <= tmpres; + + if(C_PIPE_STAGES < 2) // No pipeline + intQpipeend = intO; + else // Pipeline stages required + begin + intQpipeend = intQpipe[2]; + end + end + + always @(CLK) + lastCLK <= CLK; + + always@(I or T or EN) + begin + if(C_GATE_TYPE == 0 || C_GATE_TYPE == 1) // AND or NAND gate? + tmpres = 1; + else + tmpres = 0; + for(j = 0; j < C_INPUTS; j = j + 1) + begin + if(tmpsig[j] == 1) + begin + if(C_GATE_TYPE == 0) // AND gate + begin + if(I[j] !== 1'bx) + tmpres = tmpres & ~I[j]; + else if(tmpres === 1'b1) + tmpres = 1'bx; + end + else if(C_GATE_TYPE == 1) // NAND gate + begin + if(I[j] !== 1'bx) + tmpres = tmpres & ~I[j]; + else if(tmpres === 1'b1) + tmpres = 1'bx; + end + else if(C_GATE_TYPE == 2) // OR gate + begin + if(I[j] !== 1'bx) + tmpres = tmpres | ~I[j]; + else if(tmpres === 1'b0) + tmpres = 1'bx; + end + else if(C_GATE_TYPE == 3) // NOR gate + begin + if(I[j] !== 1'bx) + tmpres = tmpres | ~I[j]; + else if(tmpres === 1'b0) + tmpres = 1'bx; + end + else if(C_GATE_TYPE == 4) // XOR gate + begin + if(I[j] !== 1'bx) + tmpres = tmpres ^ ~I[j]; + else + tmpres = 1'bx; + end + else if(C_GATE_TYPE == 5) // XNOR gate + begin + if(I[j] !== 1'bx) + tmpres = tmpres ^ ~I[j]; + else + tmpres = 1'bx; + end + else if(C_GATE_TYPE == 7 ) // Buffer + begin + if(I[j] !== 1'bx) + tmpres = ~I[j]; + else + tmpres = 1'bx; + end + else if(C_GATE_TYPE == 8) // BUFT + begin + if(I[j] !== 1'bx) + if (T == 0) + tmpres = ~I[j]; + else + tmpres = 1'b1; + else + tmpres = 1'bx; + end + else if(C_GATE_TYPE == 9) // BUFE + begin + if(I[j] !== 1'bx) + if (EN == 0) + tmpres = ~I[j]; + else + tmpres = 1'b1; + else + tmpres = 1'bx; + end + else // INV gate + begin + if(I[j] !== 1'bx) + tmpres = ~I[j]; + else + tmpres = 1'bx; + end + end + else // No input inversion on bit j of input + begin + if(C_GATE_TYPE == 0) // AND gate + begin + if(I[j] !== 1'bx) + tmpres = tmpres & I[j]; + else if(tmpres === 1'b1) + tmpres = 1'bx; + end + else if(C_GATE_TYPE == 1) // NAND gate + begin + if(I[j] !== 1'bx) + tmpres = tmpres & I[j]; + else if(tmpres === 1'b1) + tmpres = 1'bx; + end + else if(C_GATE_TYPE == 2) // OR gate + begin + if(I[j] !== 1'bx) + tmpres = tmpres | I[j]; + else if(tmpres === 1'b0) + tmpres = 1'bx; + end + else if(C_GATE_TYPE == 3) // NOR gate + begin + if(I[j] !== 1'bx) + tmpres = tmpres | I[j]; + else if(tmpres === 1'b0) + tmpres = 1'bx; + end + else if(C_GATE_TYPE == 4) // XOR gate + begin + if(I[j] !== 1'bx) + tmpres = tmpres ^ I[j]; + else + tmpres = 1'bx; + end + else if(C_GATE_TYPE == 5) // XNOR gate + begin + if(I[j] !== 1'bx) + tmpres = tmpres ^ I[j]; + else + tmpres = 1'bx; + end + else if(C_GATE_TYPE == 7) // Buffer + begin + if(I[j] !== 1'bx) + tmpres = I[j]; + else + tmpres = 1'bx; + end + else if(C_GATE_TYPE == 8) // BUFT + begin + if(I[j] !== 1'bx) + if (T == 0) + tmpres = I[j]; + else + tmpres = 1'b1; + else + tmpres = 1'b1; + end + else if(C_GATE_TYPE == 9) // BUFE + begin + if(I[j] !== 1'bx) + if (EN == 0) + tmpres = I[j]; + else + tmpres = 1'b1; + else + tmpres = 1'b1; + end + + else // INV gate + begin + if(I[j] !== 1'bx) + tmpres = I[j]; + else + tmpres = 1'bx; + end + end + end + + if(C_GATE_TYPE == 1 || C_GATE_TYPE == 3 || C_GATE_TYPE == 5 || C_GATE_TYPE == 6) + tmpres = ~tmpres; + + intO <= #1 tmpres; + end + + always@(posedge CLK) + begin + if(CLK === 1'b1 && lastCLK === 1'b0 && intCE === 1'b1) // OK! Update pipelines! + begin + for(pipe = 2; pipe <= C_PIPE_STAGES-1; pipe = pipe + 1) + begin + intQpipe[pipe] <= intQpipe[pipe+1]; + end + intQpipe[C_PIPE_STAGES] <= intO; + end + else if((CLK === 1'bx && lastCLK === 1'b0) || (CLK === 1'b1 && lastCLK === 1'bx) || intCE === 1'bx) // POSSIBLY Update pipelines! + begin + for(pipe = 2; pipe <= C_PIPE_STAGES-1; pipe = pipe + 1) + begin + if(intQpipe[pipe] !== intQpipe[pipe+1]) + intQpipe[pipe] <= 1'bx; + end + if(intQpipe[C_PIPE_STAGES] !== intO) + intQpipe[C_PIPE_STAGES] <= 1'bx; + end + end + + always@(intO or intQpipe[2]) + begin + if(C_PIPE_STAGES < 2) // No pipeline + intQpipeend <= intO; + else // Pipeline stages required + begin + intQpipeend <= intQpipe[2]; + end + end + + function defval; + input i; + input hassig; + input val; + begin + if(hassig == 1) + defval = i; + else + defval = val; + end + endfunction + + function [C_INPUTS - 1 : 0] to_bits; + input [C_INPUTS*8 : 1] instring; + integer i; + begin + for(i = C_INPUTS; i > 0; i = i - 1) + begin // Is this character a '0'? (ASCII = 48 = 00110000) + if(instring[(i*8)] == 0 && + instring[(i*8)-1] == 0 && + instring[(i*8)-2] == 1 && + instring[(i*8)-3] == 1 && + instring[(i*8)-4] == 0 && + instring[(i*8)-5] == 0 && + instring[(i*8)-6] == 0 && + instring[(i*8)-7] == 0) + to_bits[i-1] = 0; + // Or is it a '1'? + else if(instring[(i*8)] == 0 && + instring[(i*8)-1] == 0 && + instring[(i*8)-2] == 1 && + instring[(i*8)-3] == 1 && + instring[(i*8)-4] == 0 && + instring[(i*8)-5] == 0 && + instring[(i*8)-6] == 0 && + instring[(i*8)-7] == 1) + + to_bits[i-1] = 1; + // Or is it a ' '? (a null char - in which case insert a '0') + else if(instring[(i*8)] == 0 && + instring[(i*8)-1] == 0 && + instring[(i*8)-2] == 0 && + instring[(i*8)-3] == 0 && + instring[(i*8)-4] == 0 && + instring[(i*8)-5] == 0 && + instring[(i*8)-6] == 0 && + instring[(i*8)-7] == 0) + to_bits[i-1] = 0; + else + begin + $display("Error in %m at time %d ns: non-binary digit in string \"%s\"\nExiting simulation...", $time, instring); + $finish; + end + end + end + endfunction + +endmodule + +`undef c_set +`undef c_clear +`undef c_override +`undef c_no_override +`undef c_and +`undef c_nand +`undef c_or +`undef c_nor +`undef c_xor +`undef c_xnor diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/C_GATE_BUS_V4_0.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/C_GATE_BUS_V4_0.v new file mode 100644 index 0000000..6d0566e --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/C_GATE_BUS_V4_0.v @@ -0,0 +1,365 @@ +/* $Id: C_GATE_BUS_V4_0.v,v 1.11 2008/09/08 20:05:46 akennedy Exp $ +-- +-- Filename - C_GATE_BUS_V4_0.v +-- Author - Xilinx +-- Creation - 26 Jan 1999 +-- +-- Description - This file contains the Verilog behavior for the Baseblocks C_GATE_BUS_V4_0 module +*/ + + + +`define c_set 0 +`define c_clear 1 +`define c_override 0 +`define c_no_override 1 +`define c_and 0 +`define c_nand 1 +`define c_or 2 +`define c_nor 3 +`define c_xor 4 +`define c_xnor 5 +`define c_inv 6 +`define c_buf 7 + +module C_GATE_BUS_V4_0 (IA, IB, IC, ID, CLK, CE, ACLR, ASET, AINIT, SCLR, SSET, SINIT, O, Q); + + parameter C_AINIT_VAL = ""; + parameter C_ENABLE_RLOCS = 1; + parameter C_GATE_TYPE = `c_and; + parameter C_HAS_ACLR = 0; + parameter C_HAS_AINIT = 0; + parameter C_HAS_ASET = 0; + parameter C_HAS_CE = 0; + parameter C_HAS_O = 0; + parameter C_HAS_Q = 1; + parameter C_HAS_SCLR = 0; + parameter C_HAS_SINIT = 0; + parameter C_HAS_SSET = 0; + parameter C_INPUTS = 2; + parameter C_INPUT_A_INV_MASK = ""; + parameter C_INPUT_B_INV_MASK = ""; + parameter C_INPUT_C_INV_MASK = ""; + parameter C_INPUT_D_INV_MASK = ""; + parameter C_SINIT_VAL = ""; + parameter C_SYNC_ENABLE = `c_override; + parameter C_SYNC_PRIORITY = `c_clear; + parameter C_WIDTH = 16; + + + input [C_WIDTH-1 : 0] IA; + input [C_WIDTH-1 : 0] IB; + input [C_WIDTH-1 : 0] IC; + input [C_WIDTH-1 : 0] ID; + input CLK; + input CE; + input ACLR; + input ASET; + input AINIT; + input SCLR; + input SSET; + input SINIT; + output [C_WIDTH-1 : 0] O; + output [C_WIDTH-1 : 0] Q; + + // Internal values to drive signals when input is missing + reg [C_WIDTH-1 : 0] intIA; + reg [C_WIDTH-1 : 0] intIB; + reg [C_WIDTH-1 : 0] intIC; + reg [C_WIDTH-1 : 0] intID; + reg [C_WIDTH-1 : 0] intO; + wire [C_WIDTH-1 : 0] intQ; + + wire [C_WIDTH-1 : 0] Q = (C_HAS_Q == 1 ? intQ : {C_WIDTH{1'bx}}); + wire [C_WIDTH-1 : 0] O = (C_HAS_O == 1 ? intO : {C_WIDTH{1'bx}}); + + + integer j; + + reg [C_WIDTH-1 : 0] tmpres; + + // Output register + C_REG_FD_V4_0 #(C_AINIT_VAL, C_ENABLE_RLOCS, C_HAS_ACLR, C_HAS_AINIT, C_HAS_ASET, + C_HAS_CE, C_HAS_SCLR, C_HAS_SINIT, C_HAS_SSET, + C_SINIT_VAL, C_SYNC_ENABLE, C_SYNC_PRIORITY, C_WIDTH) + reg1 (.D(intO), .CLK(CLK), .CE(CE), .ACLR(ACLR), .ASET(ASET), + .AINIT(AINIT), .SCLR(SCLR), .SSET(SSET), .SINIT(SINIT), + .Q(intQ)); + + initial + begin + + #1; + + if(C_INPUTS == 4) + begin + intIA = IA ^ to_bits(C_INPUT_A_INV_MASK); + intIB = IB ^ to_bits(C_INPUT_B_INV_MASK); + intIC = IC ^ to_bits(C_INPUT_C_INV_MASK); + intID = ID ^ to_bits(C_INPUT_D_INV_MASK); + end + else if(C_INPUTS == 3) + begin + intIA = IA ^ to_bits(C_INPUT_A_INV_MASK); + intIB = IB ^ to_bits(C_INPUT_B_INV_MASK); + intIC = IC ^ to_bits(C_INPUT_C_INV_MASK); + if(C_GATE_TYPE == 0 || C_GATE_TYPE == 1) // AND or NAND gate! + intID = {C_WIDTH{1'b1}}; + else + intID = 'b0; + end + else if(C_INPUTS == 2) + begin + intIA = IA ^ to_bits(C_INPUT_A_INV_MASK); + intIB = IB ^ to_bits(C_INPUT_B_INV_MASK); + if(C_GATE_TYPE == 0 || C_GATE_TYPE == 1) // AND or NAND gate! + begin + intIC = {C_WIDTH{1'b1}}; + intID = {C_WIDTH{1'b1}}; + end + else + begin + intIC = 'b0; + intID = 'b0; + end + end + else // inv or buf gates + begin + intID = {C_WIDTH{1'b0}}; + intIC = {C_WIDTH{1'b0}}; + intIB = {C_WIDTH{1'b0}}; + intIA = IA; + end + + for(j = 0; j < C_WIDTH; j = j + 1) + begin + if(intIA[j] === 1'bx || intIB[j] === 1'bx || intIC[j] === 1'bx || intID[j] === 1'bx) + begin // Unknown's on at least one input + if(C_GATE_TYPE == 0) // AND gate + begin + if(intIA[j] === 1'b0 || intIB[j] === 1'b0 || intIC[j] === 1'b0 || intID[j] === 1'b0) + tmpres[j] = 1'b0; + else + tmpres[j] = 1'bx; + end + else if(C_GATE_TYPE == 1) // NAND gate + begin + if(intIA[j] === 1'b0 || intIB[j] === 1'b0 || intIC[j] === 1'b0 || intID[j] === 1'b0) + tmpres[j] = 1'b1; + else + tmpres[j] = 1'bx; + end + else if(C_GATE_TYPE == 2) // OR gate + begin + if(intIA[j] === 1'b1 || intIB[j] === 1'b1 || intIC[j] === 1'b1 || intID[j] === 1'b1) + tmpres[j] = 1'b1; + else + tmpres[j] = 1'bx; + end + else if(C_GATE_TYPE == 3) // NOR gate + begin + if(intIA[j] === 1'b1 || intIB[j] === 1'b1 || intIC[j] === 1'b1 || intID[j] === 1'b1) + tmpres[j] = 1'b0; + else + tmpres[j] = 1'bx; + end + else if(C_GATE_TYPE > 3) // other gate + tmpres[j] = 1'bx; + end + else + begin // No unknowns in inputs + if(C_GATE_TYPE == 0) // AND gate + tmpres[j] = intIA[j] && intIB[j] && intIC[j] && intID[j]; + else if(C_GATE_TYPE == 1) // NAND gate + tmpres[j] = ~(intIA[j] && intIB[j] && intIC[j] && intID[j]); + else if(C_GATE_TYPE == 2) // OR gate + tmpres[j] = intIA[j] || intIB[j] || intIC[j] || intID[j]; + else if(C_GATE_TYPE == 3) // NOR gate + tmpres[j] = ~(intIA[j] || intIB[j] || intIC[j] || intID[j]); + else if(C_GATE_TYPE == 4) // XOR gate + tmpres[j] = intIA[j] ^ intIB[j] ^ intIC[j] ^ intID[j]; + else if(C_GATE_TYPE == 5) // XNOR gate + tmpres[j] = ~(intIA[j] ^ intIB[j] ^ intIC[j] ^ intID[j]); + else if(C_GATE_TYPE == 6) // INV gate + tmpres[j] = ~(intIA[j]); + else if(C_GATE_TYPE == 7) // BUF gate + tmpres[j] = intIA[j]; + end + end + + intO <= tmpres; + end + + always@(IA or IB or IC or ID) + begin + if(C_INPUTS == 4) + begin + intIA = IA ^ to_bits(C_INPUT_A_INV_MASK); + intIB = IB ^ to_bits(C_INPUT_B_INV_MASK); + intIC = IC ^ to_bits(C_INPUT_C_INV_MASK); + intID = ID ^ to_bits(C_INPUT_D_INV_MASK); + end + else if(C_INPUTS == 3) + begin + intIA = IA ^ to_bits(C_INPUT_A_INV_MASK); + intIB = IB ^ to_bits(C_INPUT_B_INV_MASK); + intIC = IC ^ to_bits(C_INPUT_C_INV_MASK); + if(C_GATE_TYPE == 0 || C_GATE_TYPE == 1) // AND or NAND gate! + intID = {C_WIDTH{1'b1}}; + else + intID = 'b0; + end + else if(C_INPUTS == 2) + begin + intIA = IA ^ to_bits(C_INPUT_A_INV_MASK); + intIB = IB ^ to_bits(C_INPUT_B_INV_MASK); + if(C_GATE_TYPE == 0 || C_GATE_TYPE == 1) // AND or NAND gate! + begin + intIC = {C_WIDTH{1'b1}}; + intID = {C_WIDTH{1'b1}}; + end + else + begin + intIC = 'b0; + intID = 'b0; + end + end + else // inv or buf gates + begin + intID = {C_WIDTH{1'b0}}; + intIC = {C_WIDTH{1'b0}}; + intIB = {C_WIDTH{1'b0}}; + intIA = IA; + end + + for(j = 0; j < C_WIDTH; j = j + 1) + begin + if(intIA[j] === 1'bx || intIB[j] === 1'bx || intIC[j] === 1'bx || intID[j] === 1'bx) + begin // Unknown's on at least one input + if(C_GATE_TYPE == 0) // AND gate + begin + if(intIA[j] === 1'b0 || intIB[j] === 1'b0 || intIC[j] === 1'b0 || intID[j] === 1'b0) + tmpres[j] = 1'b0; + else + tmpres[j] = 1'bx; + end + else if(C_GATE_TYPE == 1) // NAND gate + begin + if(intIA[j] === 1'b0 || intIB[j] === 1'b0 || intIC[j] === 1'b0 || intID[j] === 1'b0) + tmpres[j] = 1'b1; + else + tmpres[j] = 1'bx; + end + else if(C_GATE_TYPE == 2) // OR gate + begin + if(intIA[j] === 1'b1 || intIB[j] === 1'b1 || intIC[j] === 1'b1 || intID[j] === 1'b1) + tmpres[j] = 1'b1; + else + tmpres[j] = 1'bx; + end + else if(C_GATE_TYPE == 3) // NOR gate + begin + if(intIA[j] === 1'b1 || intIB[j] === 1'b1 || intIC[j] === 1'b1 || intID[j] === 1'b1) + tmpres[j] = 1'b0; + else + tmpres[j] = 1'bx; + end + else if(C_GATE_TYPE > 3) // other gate + tmpres[j] = 1'bx; + end + else + begin + if(C_GATE_TYPE == 0) // AND gate + tmpres[j] = intIA[j] && intIB[j] && intIC[j] && intID[j]; + else if(C_GATE_TYPE == 1) // NAND gate + tmpres[j] = ~(intIA[j] && intIB[j] && intIC[j] && intID[j]); + else if(C_GATE_TYPE == 2) // OR gate + tmpres[j] = intIA[j] || intIB[j] || intIC[j] || intID[j]; + else if(C_GATE_TYPE == 3) // NOR gate + tmpres[j] = ~(intIA[j] || intIB[j] || intIC[j] || intID[j]); + else if(C_GATE_TYPE == 4) // XOR gate + tmpres[j] = intIA[j] ^ intIB[j] ^ intIC[j] ^ intID[j]; + else if(C_GATE_TYPE == 5) // XNOR gate + tmpres[j] = ~(intIA[j] ^ intIB[j] ^ intIC[j] ^ intID[j]); + else if(C_GATE_TYPE == 6) // INV gate + tmpres[j] = ~(intIA[j]); + else if(C_GATE_TYPE == 7) // BUF gate + tmpres[j] = intIA[j]; + end + end + + intO <= #1 tmpres; + end + + function defval; + input i; + input hassig; + input val; + begin + if(hassig == 1) + defval = i; + else + defval = val; + end + endfunction + + function [C_WIDTH - 1 : 0] to_bits; + input [C_WIDTH*8 : 1] instring; + integer i; + begin + for(i = C_WIDTH; i > 0; i = i - 1) + begin // Is this character a '0'? (ASCII = 48 = 00110000) + if(instring[(i*8)] == 0 && + instring[(i*8)-1] == 0 && + instring[(i*8)-2] == 1 && + instring[(i*8)-3] == 1 && + instring[(i*8)-4] == 0 && + instring[(i*8)-5] == 0 && + instring[(i*8)-6] == 0 && + instring[(i*8)-7] == 0) + to_bits[i-1] = 0; + // Or is it a '1'? + else if(instring[(i*8)] == 0 && + instring[(i*8)-1] == 0 && + instring[(i*8)-2] == 1 && + instring[(i*8)-3] == 1 && + instring[(i*8)-4] == 0 && + instring[(i*8)-5] == 0 && + instring[(i*8)-6] == 0 && + instring[(i*8)-7] == 1) + + to_bits[i-1] = 1; + // Or is it a ' '? (a null char - in which case insert a '0') + else if(instring[(i*8)] == 0 && + instring[(i*8)-1] == 0 && + instring[(i*8)-2] == 0 && + instring[(i*8)-3] == 0 && + instring[(i*8)-4] == 0 && + instring[(i*8)-5] == 0 && + instring[(i*8)-6] == 0 && + instring[(i*8)-7] == 0) + to_bits[i-1] = 0; + else + begin + $display("Error: non-binary digit in string \"%s\"\nExiting simulation...", instring); + $finish; + end + end + end + endfunction + +endmodule + +`undef c_set +`undef c_clear +`undef c_override +`undef c_no_override +`undef c_and +`undef c_nand +`undef c_or +`undef c_nor +`undef c_xor +`undef c_xnor +`undef c_inv +`undef c_buf + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/C_GATE_BUS_V5_0.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/C_GATE_BUS_V5_0.v new file mode 100644 index 0000000..780bccb --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/C_GATE_BUS_V5_0.v @@ -0,0 +1,365 @@ +/* $Id: C_GATE_BUS_V5_0.v,v 1.17 2008/09/08 20:05:56 akennedy Exp $ +-- +-- Filename - C_GATE_BUS_V5_0.v +-- Author - Xilinx +-- Creation - 26 Jan 1999 +-- +-- Description - This file contains the Verilog behavior for the Baseblocks C_GATE_BUS_V5_0 module +*/ + +`timescale 1ns/10ps + +`define c_set 0 +`define c_clear 1 +`define c_override 0 +`define c_no_override 1 +`define c_and 0 +`define c_nand 1 +`define c_or 2 +`define c_nor 3 +`define c_xor 4 +`define c_xnor 5 +`define c_inv 6 +`define c_buf 7 + +module C_GATE_BUS_V5_0 (IA, IB, IC, ID, CLK, CE, ACLR, ASET, AINIT, SCLR, SSET, SINIT, O, Q); + + parameter C_AINIT_VAL = ""; + parameter C_ENABLE_RLOCS = 1; + parameter C_GATE_TYPE = `c_and; + parameter C_HAS_ACLR = 0; + parameter C_HAS_AINIT = 0; + parameter C_HAS_ASET = 0; + parameter C_HAS_CE = 0; + parameter C_HAS_O = 0; + parameter C_HAS_Q = 1; + parameter C_HAS_SCLR = 0; + parameter C_HAS_SINIT = 0; + parameter C_HAS_SSET = 0; + parameter C_INPUTS = 2; + parameter C_INPUT_A_INV_MASK = ""; + parameter C_INPUT_B_INV_MASK = ""; + parameter C_INPUT_C_INV_MASK = ""; + parameter C_INPUT_D_INV_MASK = ""; + parameter C_SINIT_VAL = ""; + parameter C_SYNC_ENABLE = `c_override; + parameter C_SYNC_PRIORITY = `c_clear; + parameter C_WIDTH = 16; + + + input [C_WIDTH-1 : 0] IA; + input [C_WIDTH-1 : 0] IB; + input [C_WIDTH-1 : 0] IC; + input [C_WIDTH-1 : 0] ID; + input CLK; + input CE; + input ACLR; + input ASET; + input AINIT; + input SCLR; + input SSET; + input SINIT; + output [C_WIDTH-1 : 0] O; + output [C_WIDTH-1 : 0] Q; + + // Internal values to drive signals when input is missing + reg [C_WIDTH-1 : 0] intIA; + reg [C_WIDTH-1 : 0] intIB; + reg [C_WIDTH-1 : 0] intIC; + reg [C_WIDTH-1 : 0] intID; + reg [C_WIDTH-1 : 0] intO; + wire [C_WIDTH-1 : 0] intQ; + + wire [C_WIDTH-1 : 0] Q = (C_HAS_Q == 1 ? intQ : {C_WIDTH{1'bx}}); + wire [C_WIDTH-1 : 0] O = (C_HAS_O == 1 ? intO : {C_WIDTH{1'bx}}); + + + integer j; + + reg [C_WIDTH-1 : 0] tmpres; + + // Output register + C_REG_FD_V5_0 #(C_AINIT_VAL, C_ENABLE_RLOCS, C_HAS_ACLR, C_HAS_AINIT, C_HAS_ASET, + C_HAS_CE, C_HAS_SCLR, C_HAS_SINIT, C_HAS_SSET, + C_SINIT_VAL, C_SYNC_ENABLE, C_SYNC_PRIORITY, C_WIDTH) + reg1 (.D(intO), .CLK(CLK), .CE(CE), .ACLR(ACLR), .ASET(ASET), + .AINIT(AINIT), .SCLR(SCLR), .SSET(SSET), .SINIT(SINIT), + .Q(intQ)); + + initial + begin + + #1; + + if(C_INPUTS == 4) + begin + intIA = IA ^ to_bits(C_INPUT_A_INV_MASK); + intIB = IB ^ to_bits(C_INPUT_B_INV_MASK); + intIC = IC ^ to_bits(C_INPUT_C_INV_MASK); + intID = ID ^ to_bits(C_INPUT_D_INV_MASK); + end + else if(C_INPUTS == 3) + begin + intIA = IA ^ to_bits(C_INPUT_A_INV_MASK); + intIB = IB ^ to_bits(C_INPUT_B_INV_MASK); + intIC = IC ^ to_bits(C_INPUT_C_INV_MASK); + if(C_GATE_TYPE == 0 || C_GATE_TYPE == 1) // AND or NAND gate! + intID = {C_WIDTH{1'b1}}; + else + intID = 'b0; + end + else if(C_INPUTS == 2) + begin + intIA = IA ^ to_bits(C_INPUT_A_INV_MASK); + intIB = IB ^ to_bits(C_INPUT_B_INV_MASK); + if(C_GATE_TYPE == 0 || C_GATE_TYPE == 1) // AND or NAND gate! + begin + intIC = {C_WIDTH{1'b1}}; + intID = {C_WIDTH{1'b1}}; + end + else + begin + intIC = 'b0; + intID = 'b0; + end + end + else // inv or buf gates + begin + intID = {C_WIDTH{1'b0}}; + intIC = {C_WIDTH{1'b0}}; + intIB = {C_WIDTH{1'b0}}; + intIA = IA; + end + + for(j = 0; j < C_WIDTH; j = j + 1) + begin + if(intIA[j] === 1'bx || intIB[j] === 1'bx || intIC[j] === 1'bx || intID[j] === 1'bx) + begin // Unknown's on at least one input + if(C_GATE_TYPE == 0) // AND gate + begin + if(intIA[j] === 1'b0 || intIB[j] === 1'b0 || intIC[j] === 1'b0 || intID[j] === 1'b0) + tmpres[j] = 1'b0; + else + tmpres[j] = 1'bx; + end + else if(C_GATE_TYPE == 1) // NAND gate + begin + if(intIA[j] === 1'b0 || intIB[j] === 1'b0 || intIC[j] === 1'b0 || intID[j] === 1'b0) + tmpres[j] = 1'b1; + else + tmpres[j] = 1'bx; + end + else if(C_GATE_TYPE == 2) // OR gate + begin + if(intIA[j] === 1'b1 || intIB[j] === 1'b1 || intIC[j] === 1'b1 || intID[j] === 1'b1) + tmpres[j] = 1'b1; + else + tmpres[j] = 1'bx; + end + else if(C_GATE_TYPE == 3) // NOR gate + begin + if(intIA[j] === 1'b1 || intIB[j] === 1'b1 || intIC[j] === 1'b1 || intID[j] === 1'b1) + tmpres[j] = 1'b0; + else + tmpres[j] = 1'bx; + end + else if(C_GATE_TYPE > 3) // other gate + tmpres[j] = 1'bx; + end + else + begin // No unknowns in inputs + if(C_GATE_TYPE == 0) // AND gate + tmpres[j] = intIA[j] && intIB[j] && intIC[j] && intID[j]; + else if(C_GATE_TYPE == 1) // NAND gate + tmpres[j] = ~(intIA[j] && intIB[j] && intIC[j] && intID[j]); + else if(C_GATE_TYPE == 2) // OR gate + tmpres[j] = intIA[j] || intIB[j] || intIC[j] || intID[j]; + else if(C_GATE_TYPE == 3) // NOR gate + tmpres[j] = ~(intIA[j] || intIB[j] || intIC[j] || intID[j]); + else if(C_GATE_TYPE == 4) // XOR gate + tmpres[j] = intIA[j] ^ intIB[j] ^ intIC[j] ^ intID[j]; + else if(C_GATE_TYPE == 5) // XNOR gate + tmpres[j] = ~(intIA[j] ^ intIB[j] ^ intIC[j] ^ intID[j]); + else if(C_GATE_TYPE == 6) // INV gate + tmpres[j] = ~(intIA[j]); + else if(C_GATE_TYPE == 7) // BUF gate + tmpres[j] = intIA[j]; + end + end + + intO <= tmpres; + end + + always@(IA or IB or IC or ID) + begin + if(C_INPUTS == 4) + begin + intIA = IA ^ to_bits(C_INPUT_A_INV_MASK); + intIB = IB ^ to_bits(C_INPUT_B_INV_MASK); + intIC = IC ^ to_bits(C_INPUT_C_INV_MASK); + intID = ID ^ to_bits(C_INPUT_D_INV_MASK); + end + else if(C_INPUTS == 3) + begin + intIA = IA ^ to_bits(C_INPUT_A_INV_MASK); + intIB = IB ^ to_bits(C_INPUT_B_INV_MASK); + intIC = IC ^ to_bits(C_INPUT_C_INV_MASK); + if(C_GATE_TYPE == 0 || C_GATE_TYPE == 1) // AND or NAND gate! + intID = {C_WIDTH{1'b1}}; + else + intID = 'b0; + end + else if(C_INPUTS == 2) + begin + intIA = IA ^ to_bits(C_INPUT_A_INV_MASK); + intIB = IB ^ to_bits(C_INPUT_B_INV_MASK); + if(C_GATE_TYPE == 0 || C_GATE_TYPE == 1) // AND or NAND gate! + begin + intIC = {C_WIDTH{1'b1}}; + intID = {C_WIDTH{1'b1}}; + end + else + begin + intIC = 'b0; + intID = 'b0; + end + end + else // inv or buf gates + begin + intID = {C_WIDTH{1'b0}}; + intIC = {C_WIDTH{1'b0}}; + intIB = {C_WIDTH{1'b0}}; + intIA = IA; + end + + for(j = 0; j < C_WIDTH; j = j + 1) + begin + if(intIA[j] === 1'bx || intIB[j] === 1'bx || intIC[j] === 1'bx || intID[j] === 1'bx) + begin // Unknown's on at least one input + if(C_GATE_TYPE == 0) // AND gate + begin + if(intIA[j] === 1'b0 || intIB[j] === 1'b0 || intIC[j] === 1'b0 || intID[j] === 1'b0) + tmpres[j] = 1'b0; + else + tmpres[j] = 1'bx; + end + else if(C_GATE_TYPE == 1) // NAND gate + begin + if(intIA[j] === 1'b0 || intIB[j] === 1'b0 || intIC[j] === 1'b0 || intID[j] === 1'b0) + tmpres[j] = 1'b1; + else + tmpres[j] = 1'bx; + end + else if(C_GATE_TYPE == 2) // OR gate + begin + if(intIA[j] === 1'b1 || intIB[j] === 1'b1 || intIC[j] === 1'b1 || intID[j] === 1'b1) + tmpres[j] = 1'b1; + else + tmpres[j] = 1'bx; + end + else if(C_GATE_TYPE == 3) // NOR gate + begin + if(intIA[j] === 1'b1 || intIB[j] === 1'b1 || intIC[j] === 1'b1 || intID[j] === 1'b1) + tmpres[j] = 1'b0; + else + tmpres[j] = 1'bx; + end + else if(C_GATE_TYPE > 3) // other gate + tmpres[j] = 1'bx; + end + else + begin + if(C_GATE_TYPE == 0) // AND gate + tmpres[j] = intIA[j] && intIB[j] && intIC[j] && intID[j]; + else if(C_GATE_TYPE == 1) // NAND gate + tmpres[j] = ~(intIA[j] && intIB[j] && intIC[j] && intID[j]); + else if(C_GATE_TYPE == 2) // OR gate + tmpres[j] = intIA[j] || intIB[j] || intIC[j] || intID[j]; + else if(C_GATE_TYPE == 3) // NOR gate + tmpres[j] = ~(intIA[j] || intIB[j] || intIC[j] || intID[j]); + else if(C_GATE_TYPE == 4) // XOR gate + tmpres[j] = intIA[j] ^ intIB[j] ^ intIC[j] ^ intID[j]; + else if(C_GATE_TYPE == 5) // XNOR gate + tmpres[j] = ~(intIA[j] ^ intIB[j] ^ intIC[j] ^ intID[j]); + else if(C_GATE_TYPE == 6) // INV gate + tmpres[j] = ~(intIA[j]); + else if(C_GATE_TYPE == 7) // BUF gate + tmpres[j] = intIA[j]; + end + end + + intO <= #1 tmpres; + end + + function defval; + input i; + input hassig; + input val; + begin + if(hassig == 1) + defval = i; + else + defval = val; + end + endfunction + + function [C_WIDTH - 1 : 0] to_bits; + input [C_WIDTH*8 : 1] instring; + integer i; + begin + for(i = C_WIDTH; i > 0; i = i - 1) + begin // Is this character a '0'? (ASCII = 48 = 00110000) + if(instring[(i*8)] == 0 && + instring[(i*8)-1] == 0 && + instring[(i*8)-2] == 1 && + instring[(i*8)-3] == 1 && + instring[(i*8)-4] == 0 && + instring[(i*8)-5] == 0 && + instring[(i*8)-6] == 0 && + instring[(i*8)-7] == 0) + to_bits[i-1] = 0; + // Or is it a '1'? + else if(instring[(i*8)] == 0 && + instring[(i*8)-1] == 0 && + instring[(i*8)-2] == 1 && + instring[(i*8)-3] == 1 && + instring[(i*8)-4] == 0 && + instring[(i*8)-5] == 0 && + instring[(i*8)-6] == 0 && + instring[(i*8)-7] == 1) + + to_bits[i-1] = 1; + // Or is it a ' '? (a null char - in which case insert a '0') + else if(instring[(i*8)] == 0 && + instring[(i*8)-1] == 0 && + instring[(i*8)-2] == 0 && + instring[(i*8)-3] == 0 && + instring[(i*8)-4] == 0 && + instring[(i*8)-5] == 0 && + instring[(i*8)-6] == 0 && + instring[(i*8)-7] == 0) + to_bits[i-1] = 0; + else + begin + $display("Error in %m at time %d ns: non-binary digit in string \"%s\"\nExiting simulation...", $time, instring); + $finish; + end + end + end + endfunction + +endmodule + +`undef c_set +`undef c_clear +`undef c_override +`undef c_no_override +`undef c_and +`undef c_nand +`undef c_or +`undef c_nor +`undef c_xor +`undef c_xnor +`undef c_inv +`undef c_buf + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/C_GATE_BUS_V6_0.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/C_GATE_BUS_V6_0.v new file mode 100644 index 0000000..95d8cf2 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/C_GATE_BUS_V6_0.v @@ -0,0 +1,374 @@ +// Copyright(C) 2002 by Xilinx, Inc. All rights reserved. +// This text contains proprietary, confidential +// information of Xilinx, Inc., is distributed +// under license from Xilinx, Inc., and may be used, +// copied and/or disclosed only pursuant to the terms +// of a valid license agreement with Xilinx, Inc. This copyright +// notice must be retained as part of this text at all times. + + +/* $Id: C_GATE_BUS_V6_0.v,v 1.16 2008/09/08 20:06:04 akennedy Exp $ +-- +-- Filename - C_GATE_BUS_V6_0.v +-- Author - Xilinx +-- Creation - 26 Jan 1999 +-- +-- Description - This file contains the Verilog behavior for the Baseblocks C_GATE_BUS_V6_0 module +*/ + +`timescale 1ns/10ps + +`define c_set 0 +`define c_clear 1 +`define c_override 0 +`define c_no_override 1 +`define c_and 0 +`define c_nand 1 +`define c_or 2 +`define c_nor 3 +`define c_xor 4 +`define c_xnor 5 +`define c_inv 6 +`define c_buf 7 + +module C_GATE_BUS_V6_0 (IA, IB, IC, ID, CLK, CE, ACLR, ASET, AINIT, SCLR, SSET, SINIT, O, Q); + + parameter C_AINIT_VAL = ""; + parameter C_ENABLE_RLOCS = 1; + parameter C_GATE_TYPE = `c_and; + parameter C_HAS_ACLR = 0; + parameter C_HAS_AINIT = 0; + parameter C_HAS_ASET = 0; + parameter C_HAS_CE = 0; + parameter C_HAS_O = 0; + parameter C_HAS_Q = 1; + parameter C_HAS_SCLR = 0; + parameter C_HAS_SINIT = 0; + parameter C_HAS_SSET = 0; + parameter C_INPUTS = 2; + parameter C_INPUT_A_INV_MASK = ""; + parameter C_INPUT_B_INV_MASK = ""; + parameter C_INPUT_C_INV_MASK = ""; + parameter C_INPUT_D_INV_MASK = ""; + parameter C_SINIT_VAL = ""; + parameter C_SYNC_ENABLE = `c_override; + parameter C_SYNC_PRIORITY = `c_clear; + parameter C_WIDTH = 16; + + + input [C_WIDTH-1 : 0] IA; + input [C_WIDTH-1 : 0] IB; + input [C_WIDTH-1 : 0] IC; + input [C_WIDTH-1 : 0] ID; + input CLK; + input CE; + input ACLR; + input ASET; + input AINIT; + input SCLR; + input SSET; + input SINIT; + output [C_WIDTH-1 : 0] O; + output [C_WIDTH-1 : 0] Q; + + // Internal values to drive signals when input is missing + reg [C_WIDTH-1 : 0] intIA; + reg [C_WIDTH-1 : 0] intIB; + reg [C_WIDTH-1 : 0] intIC; + reg [C_WIDTH-1 : 0] intID; + reg [C_WIDTH-1 : 0] intO; + wire [C_WIDTH-1 : 0] intQ; + + wire [C_WIDTH-1 : 0] Q = (C_HAS_Q == 1 ? intQ : {C_WIDTH{1'bx}}); + wire [C_WIDTH-1 : 0] O = (C_HAS_O == 1 ? intO : {C_WIDTH{1'bx}}); + + + integer j; + + reg [C_WIDTH-1 : 0] tmpres; + + // Output register + C_REG_FD_V6_0 #(C_AINIT_VAL, C_ENABLE_RLOCS, C_HAS_ACLR, C_HAS_AINIT, C_HAS_ASET, + C_HAS_CE, C_HAS_SCLR, C_HAS_SINIT, C_HAS_SSET, + C_SINIT_VAL, C_SYNC_ENABLE, C_SYNC_PRIORITY, C_WIDTH) + reg1 (.D(intO), .CLK(CLK), .CE(CE), .ACLR(ACLR), .ASET(ASET), + .AINIT(AINIT), .SCLR(SCLR), .SSET(SSET), .SINIT(SINIT), + .Q(intQ)); + + initial + begin + + #1; + + if(C_INPUTS == 4) + begin + intIA = IA ^ to_bits(C_INPUT_A_INV_MASK); + intIB = IB ^ to_bits(C_INPUT_B_INV_MASK); + intIC = IC ^ to_bits(C_INPUT_C_INV_MASK); + intID = ID ^ to_bits(C_INPUT_D_INV_MASK); + end + else if(C_INPUTS == 3) + begin + intIA = IA ^ to_bits(C_INPUT_A_INV_MASK); + intIB = IB ^ to_bits(C_INPUT_B_INV_MASK); + intIC = IC ^ to_bits(C_INPUT_C_INV_MASK); + if(C_GATE_TYPE == 0 || C_GATE_TYPE == 1) // AND or NAND gate! + intID = {C_WIDTH{1'b1}}; + else + intID = 'b0; + end + else if(C_INPUTS == 2) + begin + intIA = IA ^ to_bits(C_INPUT_A_INV_MASK); + intIB = IB ^ to_bits(C_INPUT_B_INV_MASK); + if(C_GATE_TYPE == 0 || C_GATE_TYPE == 1) // AND or NAND gate! + begin + intIC = {C_WIDTH{1'b1}}; + intID = {C_WIDTH{1'b1}}; + end + else + begin + intIC = 'b0; + intID = 'b0; + end + end + else // inv or buf gates + begin + intID = {C_WIDTH{1'b0}}; + intIC = {C_WIDTH{1'b0}}; + intIB = {C_WIDTH{1'b0}}; + intIA = IA; + end + + for(j = 0; j < C_WIDTH; j = j + 1) + begin + if(intIA[j] === 1'bx || intIB[j] === 1'bx || intIC[j] === 1'bx || intID[j] === 1'bx) + begin // Unknown's on at least one input + if(C_GATE_TYPE == 0) // AND gate + begin + if(intIA[j] === 1'b0 || intIB[j] === 1'b0 || intIC[j] === 1'b0 || intID[j] === 1'b0) + tmpres[j] = 1'b0; + else + tmpres[j] = 1'bx; + end + else if(C_GATE_TYPE == 1) // NAND gate + begin + if(intIA[j] === 1'b0 || intIB[j] === 1'b0 || intIC[j] === 1'b0 || intID[j] === 1'b0) + tmpres[j] = 1'b1; + else + tmpres[j] = 1'bx; + end + else if(C_GATE_TYPE == 2) // OR gate + begin + if(intIA[j] === 1'b1 || intIB[j] === 1'b1 || intIC[j] === 1'b1 || intID[j] === 1'b1) + tmpres[j] = 1'b1; + else + tmpres[j] = 1'bx; + end + else if(C_GATE_TYPE == 3) // NOR gate + begin + if(intIA[j] === 1'b1 || intIB[j] === 1'b1 || intIC[j] === 1'b1 || intID[j] === 1'b1) + tmpres[j] = 1'b0; + else + tmpres[j] = 1'bx; + end + else if(C_GATE_TYPE > 3) // other gate + tmpres[j] = 1'bx; + end + else + begin // No unknowns in inputs + if(C_GATE_TYPE == 0) // AND gate + tmpres[j] = intIA[j] && intIB[j] && intIC[j] && intID[j]; + else if(C_GATE_TYPE == 1) // NAND gate + tmpres[j] = ~(intIA[j] && intIB[j] && intIC[j] && intID[j]); + else if(C_GATE_TYPE == 2) // OR gate + tmpres[j] = intIA[j] || intIB[j] || intIC[j] || intID[j]; + else if(C_GATE_TYPE == 3) // NOR gate + tmpres[j] = ~(intIA[j] || intIB[j] || intIC[j] || intID[j]); + else if(C_GATE_TYPE == 4) // XOR gate + tmpres[j] = intIA[j] ^ intIB[j] ^ intIC[j] ^ intID[j]; + else if(C_GATE_TYPE == 5) // XNOR gate + tmpres[j] = ~(intIA[j] ^ intIB[j] ^ intIC[j] ^ intID[j]); + else if(C_GATE_TYPE == 6) // INV gate + tmpres[j] = ~(intIA[j]); + else if(C_GATE_TYPE == 7) // BUF gate + tmpres[j] = intIA[j]; + end + end + + intO <= tmpres; + end + + always@(IA or IB or IC or ID) + begin + if(C_INPUTS == 4) + begin + intIA = IA ^ to_bits(C_INPUT_A_INV_MASK); + intIB = IB ^ to_bits(C_INPUT_B_INV_MASK); + intIC = IC ^ to_bits(C_INPUT_C_INV_MASK); + intID = ID ^ to_bits(C_INPUT_D_INV_MASK); + end + else if(C_INPUTS == 3) + begin + intIA = IA ^ to_bits(C_INPUT_A_INV_MASK); + intIB = IB ^ to_bits(C_INPUT_B_INV_MASK); + intIC = IC ^ to_bits(C_INPUT_C_INV_MASK); + if(C_GATE_TYPE == 0 || C_GATE_TYPE == 1) // AND or NAND gate! + intID = {C_WIDTH{1'b1}}; + else + intID = 'b0; + end + else if(C_INPUTS == 2) + begin + intIA = IA ^ to_bits(C_INPUT_A_INV_MASK); + intIB = IB ^ to_bits(C_INPUT_B_INV_MASK); + if(C_GATE_TYPE == 0 || C_GATE_TYPE == 1) // AND or NAND gate! + begin + intIC = {C_WIDTH{1'b1}}; + intID = {C_WIDTH{1'b1}}; + end + else + begin + intIC = 'b0; + intID = 'b0; + end + end + else // inv or buf gates + begin + intID = {C_WIDTH{1'b0}}; + intIC = {C_WIDTH{1'b0}}; + intIB = {C_WIDTH{1'b0}}; + intIA = IA; + end + + for(j = 0; j < C_WIDTH; j = j + 1) + begin + if(intIA[j] === 1'bx || intIB[j] === 1'bx || intIC[j] === 1'bx || intID[j] === 1'bx) + begin // Unknown's on at least one input + if(C_GATE_TYPE == 0) // AND gate + begin + if(intIA[j] === 1'b0 || intIB[j] === 1'b0 || intIC[j] === 1'b0 || intID[j] === 1'b0) + tmpres[j] = 1'b0; + else + tmpres[j] = 1'bx; + end + else if(C_GATE_TYPE == 1) // NAND gate + begin + if(intIA[j] === 1'b0 || intIB[j] === 1'b0 || intIC[j] === 1'b0 || intID[j] === 1'b0) + tmpres[j] = 1'b1; + else + tmpres[j] = 1'bx; + end + else if(C_GATE_TYPE == 2) // OR gate + begin + if(intIA[j] === 1'b1 || intIB[j] === 1'b1 || intIC[j] === 1'b1 || intID[j] === 1'b1) + tmpres[j] = 1'b1; + else + tmpres[j] = 1'bx; + end + else if(C_GATE_TYPE == 3) // NOR gate + begin + if(intIA[j] === 1'b1 || intIB[j] === 1'b1 || intIC[j] === 1'b1 || intID[j] === 1'b1) + tmpres[j] = 1'b0; + else + tmpres[j] = 1'bx; + end + else if(C_GATE_TYPE > 3) // other gate + tmpres[j] = 1'bx; + end + else + begin + if(C_GATE_TYPE == 0) // AND gate + tmpres[j] = intIA[j] && intIB[j] && intIC[j] && intID[j]; + else if(C_GATE_TYPE == 1) // NAND gate + tmpres[j] = ~(intIA[j] && intIB[j] && intIC[j] && intID[j]); + else if(C_GATE_TYPE == 2) // OR gate + tmpres[j] = intIA[j] || intIB[j] || intIC[j] || intID[j]; + else if(C_GATE_TYPE == 3) // NOR gate + tmpres[j] = ~(intIA[j] || intIB[j] || intIC[j] || intID[j]); + else if(C_GATE_TYPE == 4) // XOR gate + tmpres[j] = intIA[j] ^ intIB[j] ^ intIC[j] ^ intID[j]; + else if(C_GATE_TYPE == 5) // XNOR gate + tmpres[j] = ~(intIA[j] ^ intIB[j] ^ intIC[j] ^ intID[j]); + else if(C_GATE_TYPE == 6) // INV gate + tmpres[j] = ~(intIA[j]); + else if(C_GATE_TYPE == 7) // BUF gate + tmpres[j] = intIA[j]; + end + end + + intO <= #1 tmpres; + end + + function defval; + input i; + input hassig; + input val; + begin + if(hassig == 1) + defval = i; + else + defval = val; + end + endfunction + + function [C_WIDTH - 1 : 0] to_bits; + input [C_WIDTH*8 : 1] instring; + integer i; + begin + for(i = C_WIDTH; i > 0; i = i - 1) + begin // Is this character a '0'? (ASCII = 48 = 00110000) + if(instring[(i*8)] == 0 && + instring[(i*8)-1] == 0 && + instring[(i*8)-2] == 1 && + instring[(i*8)-3] == 1 && + instring[(i*8)-4] == 0 && + instring[(i*8)-5] == 0 && + instring[(i*8)-6] == 0 && + instring[(i*8)-7] == 0) + to_bits[i-1] = 0; + // Or is it a '1'? + else if(instring[(i*8)] == 0 && + instring[(i*8)-1] == 0 && + instring[(i*8)-2] == 1 && + instring[(i*8)-3] == 1 && + instring[(i*8)-4] == 0 && + instring[(i*8)-5] == 0 && + instring[(i*8)-6] == 0 && + instring[(i*8)-7] == 1) + + to_bits[i-1] = 1; + // Or is it a ' '? (a null char - in which case insert a '0') + else if(instring[(i*8)] == 0 && + instring[(i*8)-1] == 0 && + instring[(i*8)-2] == 0 && + instring[(i*8)-3] == 0 && + instring[(i*8)-4] == 0 && + instring[(i*8)-5] == 0 && + instring[(i*8)-6] == 0 && + instring[(i*8)-7] == 0) + to_bits[i-1] = 0; + else + begin + $display("Error in %m at time %d ns: non-binary digit in string \"%s\"\nExiting simulation...", $time, instring); + $finish; + end + end + end + endfunction + +endmodule + +`undef c_set +`undef c_clear +`undef c_override +`undef c_no_override +`undef c_and +`undef c_nand +`undef c_or +`undef c_nor +`undef c_xor +`undef c_xnor +`undef c_inv +`undef c_buf + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/C_GATE_BUS_V7_0.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/C_GATE_BUS_V7_0.v new file mode 100644 index 0000000..70e8baf --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/C_GATE_BUS_V7_0.v @@ -0,0 +1,374 @@ +// Copyright(C) 2002 by Xilinx, Inc. All rights reserved. +// This text contains proprietary, confidential +// information of Xilinx, Inc., is distributed +// under license from Xilinx, Inc., and may be used, +// copied and/or disclosed only pursuant to the terms +// of a valid license agreement with Xilinx, Inc. This copyright +// notice must be retained as part of this text at all times. + + +/* $Id: C_GATE_BUS_V7_0.v,v 1.13 2008/09/08 20:06:13 akennedy Exp $ +-- +-- Filename - C_GATE_BUS_V7_0.v +-- Author - Xilinx +-- Creation - 26 Jan 1999 +-- +-- Description - This file contains the Verilog behavior for the Baseblocks C_GATE_BUS_V7_0 module +*/ + +`timescale 1ns/10ps + +`define c_set 0 +`define c_clear 1 +`define c_override 0 +`define c_no_override 1 +`define c_and 0 +`define c_nand 1 +`define c_or 2 +`define c_nor 3 +`define c_xor 4 +`define c_xnor 5 +`define c_inv 6 +`define c_buf 7 + +module C_GATE_BUS_V7_0 (IA, IB, IC, ID, CLK, CE, ACLR, ASET, AINIT, SCLR, SSET, SINIT, O, Q); + + parameter C_AINIT_VAL = ""; + parameter C_ENABLE_RLOCS = 1; + parameter C_GATE_TYPE = `c_and; + parameter C_HAS_ACLR = 0; + parameter C_HAS_AINIT = 0; + parameter C_HAS_ASET = 0; + parameter C_HAS_CE = 0; + parameter C_HAS_O = 0; + parameter C_HAS_Q = 1; + parameter C_HAS_SCLR = 0; + parameter C_HAS_SINIT = 0; + parameter C_HAS_SSET = 0; + parameter C_INPUTS = 2; + parameter C_INPUT_A_INV_MASK = ""; + parameter C_INPUT_B_INV_MASK = ""; + parameter C_INPUT_C_INV_MASK = ""; + parameter C_INPUT_D_INV_MASK = ""; + parameter C_SINIT_VAL = ""; + parameter C_SYNC_ENABLE = `c_override; + parameter C_SYNC_PRIORITY = `c_clear; + parameter C_WIDTH = 16; + + + input [C_WIDTH-1 : 0] IA; + input [C_WIDTH-1 : 0] IB; + input [C_WIDTH-1 : 0] IC; + input [C_WIDTH-1 : 0] ID; + input CLK; + input CE; + input ACLR; + input ASET; + input AINIT; + input SCLR; + input SSET; + input SINIT; + output [C_WIDTH-1 : 0] O; + output [C_WIDTH-1 : 0] Q; + + // Internal values to drive signals when input is missing + reg [C_WIDTH-1 : 0] intIA; + reg [C_WIDTH-1 : 0] intIB; + reg [C_WIDTH-1 : 0] intIC; + reg [C_WIDTH-1 : 0] intID; + reg [C_WIDTH-1 : 0] intO; + wire [C_WIDTH-1 : 0] intQ; + + wire [C_WIDTH-1 : 0] Q = (C_HAS_Q == 1 ? intQ : {C_WIDTH{1'bx}}); + wire [C_WIDTH-1 : 0] O = (C_HAS_O == 1 ? intO : {C_WIDTH{1'bx}}); + + + integer j; + + reg [C_WIDTH-1 : 0] tmpres; + + // Output register + C_REG_FD_V7_0 #(C_AINIT_VAL, C_ENABLE_RLOCS, C_HAS_ACLR, C_HAS_AINIT, C_HAS_ASET, + C_HAS_CE, C_HAS_SCLR, C_HAS_SINIT, C_HAS_SSET, + C_SINIT_VAL, C_SYNC_ENABLE, C_SYNC_PRIORITY, C_WIDTH) + reg1 (.D(intO), .CLK(CLK), .CE(CE), .ACLR(ACLR), .ASET(ASET), + .AINIT(AINIT), .SCLR(SCLR), .SSET(SSET), .SINIT(SINIT), + .Q(intQ)); + + initial + begin + + #1; + + if(C_INPUTS == 4) + begin + intIA = IA ^ to_bits(C_INPUT_A_INV_MASK); + intIB = IB ^ to_bits(C_INPUT_B_INV_MASK); + intIC = IC ^ to_bits(C_INPUT_C_INV_MASK); + intID = ID ^ to_bits(C_INPUT_D_INV_MASK); + end + else if(C_INPUTS == 3) + begin + intIA = IA ^ to_bits(C_INPUT_A_INV_MASK); + intIB = IB ^ to_bits(C_INPUT_B_INV_MASK); + intIC = IC ^ to_bits(C_INPUT_C_INV_MASK); + if(C_GATE_TYPE == 0 || C_GATE_TYPE == 1) // AND or NAND gate! + intID = {C_WIDTH{1'b1}}; + else + intID = 'b0; + end + else if(C_INPUTS == 2) + begin + intIA = IA ^ to_bits(C_INPUT_A_INV_MASK); + intIB = IB ^ to_bits(C_INPUT_B_INV_MASK); + if(C_GATE_TYPE == 0 || C_GATE_TYPE == 1) // AND or NAND gate! + begin + intIC = {C_WIDTH{1'b1}}; + intID = {C_WIDTH{1'b1}}; + end + else + begin + intIC = 'b0; + intID = 'b0; + end + end + else // inv or buf gates + begin + intID = {C_WIDTH{1'b0}}; + intIC = {C_WIDTH{1'b0}}; + intIB = {C_WIDTH{1'b0}}; + intIA = IA; + end + + for(j = 0; j < C_WIDTH; j = j + 1) + begin + if(intIA[j] === 1'bx || intIB[j] === 1'bx || intIC[j] === 1'bx || intID[j] === 1'bx) + begin // Unknown's on at least one input + if(C_GATE_TYPE == 0) // AND gate + begin + if(intIA[j] === 1'b0 || intIB[j] === 1'b0 || intIC[j] === 1'b0 || intID[j] === 1'b0) + tmpres[j] = 1'b0; + else + tmpres[j] = 1'bx; + end + else if(C_GATE_TYPE == 1) // NAND gate + begin + if(intIA[j] === 1'b0 || intIB[j] === 1'b0 || intIC[j] === 1'b0 || intID[j] === 1'b0) + tmpres[j] = 1'b1; + else + tmpres[j] = 1'bx; + end + else if(C_GATE_TYPE == 2) // OR gate + begin + if(intIA[j] === 1'b1 || intIB[j] === 1'b1 || intIC[j] === 1'b1 || intID[j] === 1'b1) + tmpres[j] = 1'b1; + else + tmpres[j] = 1'bx; + end + else if(C_GATE_TYPE == 3) // NOR gate + begin + if(intIA[j] === 1'b1 || intIB[j] === 1'b1 || intIC[j] === 1'b1 || intID[j] === 1'b1) + tmpres[j] = 1'b0; + else + tmpres[j] = 1'bx; + end + else if(C_GATE_TYPE > 3) // other gate + tmpres[j] = 1'bx; + end + else + begin // No unknowns in inputs + if(C_GATE_TYPE == 0) // AND gate + tmpres[j] = intIA[j] && intIB[j] && intIC[j] && intID[j]; + else if(C_GATE_TYPE == 1) // NAND gate + tmpres[j] = ~(intIA[j] && intIB[j] && intIC[j] && intID[j]); + else if(C_GATE_TYPE == 2) // OR gate + tmpres[j] = intIA[j] || intIB[j] || intIC[j] || intID[j]; + else if(C_GATE_TYPE == 3) // NOR gate + tmpres[j] = ~(intIA[j] || intIB[j] || intIC[j] || intID[j]); + else if(C_GATE_TYPE == 4) // XOR gate + tmpres[j] = intIA[j] ^ intIB[j] ^ intIC[j] ^ intID[j]; + else if(C_GATE_TYPE == 5) // XNOR gate + tmpres[j] = ~(intIA[j] ^ intIB[j] ^ intIC[j] ^ intID[j]); + else if(C_GATE_TYPE == 6) // INV gate + tmpres[j] = ~(intIA[j]); + else if(C_GATE_TYPE == 7) // BUF gate + tmpres[j] = intIA[j]; + end + end + + intO <= tmpres; + end + + always@(IA or IB or IC or ID) + begin + if(C_INPUTS == 4) + begin + intIA = IA ^ to_bits(C_INPUT_A_INV_MASK); + intIB = IB ^ to_bits(C_INPUT_B_INV_MASK); + intIC = IC ^ to_bits(C_INPUT_C_INV_MASK); + intID = ID ^ to_bits(C_INPUT_D_INV_MASK); + end + else if(C_INPUTS == 3) + begin + intIA = IA ^ to_bits(C_INPUT_A_INV_MASK); + intIB = IB ^ to_bits(C_INPUT_B_INV_MASK); + intIC = IC ^ to_bits(C_INPUT_C_INV_MASK); + if(C_GATE_TYPE == 0 || C_GATE_TYPE == 1) // AND or NAND gate! + intID = {C_WIDTH{1'b1}}; + else + intID = 'b0; + end + else if(C_INPUTS == 2) + begin + intIA = IA ^ to_bits(C_INPUT_A_INV_MASK); + intIB = IB ^ to_bits(C_INPUT_B_INV_MASK); + if(C_GATE_TYPE == 0 || C_GATE_TYPE == 1) // AND or NAND gate! + begin + intIC = {C_WIDTH{1'b1}}; + intID = {C_WIDTH{1'b1}}; + end + else + begin + intIC = 'b0; + intID = 'b0; + end + end + else // inv or buf gates + begin + intID = {C_WIDTH{1'b0}}; + intIC = {C_WIDTH{1'b0}}; + intIB = {C_WIDTH{1'b0}}; + intIA = IA; + end + + for(j = 0; j < C_WIDTH; j = j + 1) + begin + if(intIA[j] === 1'bx || intIB[j] === 1'bx || intIC[j] === 1'bx || intID[j] === 1'bx) + begin // Unknown's on at least one input + if(C_GATE_TYPE == 0) // AND gate + begin + if(intIA[j] === 1'b0 || intIB[j] === 1'b0 || intIC[j] === 1'b0 || intID[j] === 1'b0) + tmpres[j] = 1'b0; + else + tmpres[j] = 1'bx; + end + else if(C_GATE_TYPE == 1) // NAND gate + begin + if(intIA[j] === 1'b0 || intIB[j] === 1'b0 || intIC[j] === 1'b0 || intID[j] === 1'b0) + tmpres[j] = 1'b1; + else + tmpres[j] = 1'bx; + end + else if(C_GATE_TYPE == 2) // OR gate + begin + if(intIA[j] === 1'b1 || intIB[j] === 1'b1 || intIC[j] === 1'b1 || intID[j] === 1'b1) + tmpres[j] = 1'b1; + else + tmpres[j] = 1'bx; + end + else if(C_GATE_TYPE == 3) // NOR gate + begin + if(intIA[j] === 1'b1 || intIB[j] === 1'b1 || intIC[j] === 1'b1 || intID[j] === 1'b1) + tmpres[j] = 1'b0; + else + tmpres[j] = 1'bx; + end + else if(C_GATE_TYPE > 3) // other gate + tmpres[j] = 1'bx; + end + else + begin + if(C_GATE_TYPE == 0) // AND gate + tmpres[j] = intIA[j] && intIB[j] && intIC[j] && intID[j]; + else if(C_GATE_TYPE == 1) // NAND gate + tmpres[j] = ~(intIA[j] && intIB[j] && intIC[j] && intID[j]); + else if(C_GATE_TYPE == 2) // OR gate + tmpres[j] = intIA[j] || intIB[j] || intIC[j] || intID[j]; + else if(C_GATE_TYPE == 3) // NOR gate + tmpres[j] = ~(intIA[j] || intIB[j] || intIC[j] || intID[j]); + else if(C_GATE_TYPE == 4) // XOR gate + tmpres[j] = intIA[j] ^ intIB[j] ^ intIC[j] ^ intID[j]; + else if(C_GATE_TYPE == 5) // XNOR gate + tmpres[j] = ~(intIA[j] ^ intIB[j] ^ intIC[j] ^ intID[j]); + else if(C_GATE_TYPE == 6) // INV gate + tmpres[j] = ~(intIA[j]); + else if(C_GATE_TYPE == 7) // BUF gate + tmpres[j] = intIA[j]; + end + end + + intO <= #1 tmpres; + end + + function defval; + input i; + input hassig; + input val; + begin + if(hassig == 1) + defval = i; + else + defval = val; + end + endfunction + + function [C_WIDTH - 1 : 0] to_bits; + input [C_WIDTH*8 : 1] instring; + integer i; + begin + for(i = C_WIDTH; i > 0; i = i - 1) + begin // Is this character a '0'? (ASCII = 48 = 00110000) + if(instring[(i*8)] == 0 && + instring[(i*8)-1] == 0 && + instring[(i*8)-2] == 1 && + instring[(i*8)-3] == 1 && + instring[(i*8)-4] == 0 && + instring[(i*8)-5] == 0 && + instring[(i*8)-6] == 0 && + instring[(i*8)-7] == 0) + to_bits[i-1] = 0; + // Or is it a '1'? + else if(instring[(i*8)] == 0 && + instring[(i*8)-1] == 0 && + instring[(i*8)-2] == 1 && + instring[(i*8)-3] == 1 && + instring[(i*8)-4] == 0 && + instring[(i*8)-5] == 0 && + instring[(i*8)-6] == 0 && + instring[(i*8)-7] == 1) + + to_bits[i-1] = 1; + // Or is it a ' '? (a null char - in which case insert a '0') + else if(instring[(i*8)] == 0 && + instring[(i*8)-1] == 0 && + instring[(i*8)-2] == 0 && + instring[(i*8)-3] == 0 && + instring[(i*8)-4] == 0 && + instring[(i*8)-5] == 0 && + instring[(i*8)-6] == 0 && + instring[(i*8)-7] == 0) + to_bits[i-1] = 0; + else + begin + $display("Error in %m at time %d ns: non-binary digit in string \"%s\"\nExiting simulation...", $time, instring); + $finish; + end + end + end + endfunction + +endmodule + +`undef c_set +`undef c_clear +`undef c_override +`undef c_no_override +`undef c_and +`undef c_nand +`undef c_or +`undef c_nor +`undef c_xor +`undef c_xnor +`undef c_inv +`undef c_buf + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/C_MUX_BIT_V4_0.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/C_MUX_BIT_V4_0.v new file mode 100644 index 0000000..4dfac3b --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/C_MUX_BIT_V4_0.v @@ -0,0 +1,191 @@ +/* $Id: C_MUX_BIT_V4_0.v,v 1.11 2008/09/08 20:05:46 akennedy Exp $ +-- +-- Filename - C_MUX_BIT_V4_0.v +-- Author - Xilinx +-- Creation - 21 Oct 1998 +-- +-- Description - This file contains the Verilog behavior for the Baseblocks C_MUX_BIT_V4_0 module +*/ + + + +`define c_set 0 +`define c_clear 1 +`define c_override 0 +`define c_no_override 1 + +module C_MUX_BIT_V4_0 (M, S, CLK, CE, ACLR, ASET, AINIT, SCLR, SSET, SINIT, O, Q); + + parameter C_AINIT_VAL = ""; + parameter C_ENABLE_RLOCS = 1; + parameter C_HAS_ACLR = 0; + parameter C_HAS_AINIT = 0; + parameter C_HAS_ASET = 0; + parameter C_HAS_CE = 0; + parameter C_HAS_O = 0; + parameter C_HAS_Q = 1; + parameter C_HAS_SCLR = 0; + parameter C_HAS_SINIT = 0; + parameter C_HAS_SSET = 0; + parameter C_INPUTS = 2; + parameter C_LATENCY = 0; + parameter C_PIPE_STAGES = 0; + parameter C_SEL_WIDTH = 1; + parameter C_SINIT_VAL = ""; + parameter C_SYNC_ENABLE = `c_override; + parameter C_SYNC_PRIORITY = `c_clear; + + // Parameters used to drive additional registers for pipelining. + + parameter PIPE_HAS_ACLR = (C_LATENCY == 1 ? C_HAS_ACLR : 1'b0); + parameter PIPE_HAS_AINIT = (C_LATENCY == 1 ? C_HAS_AINIT : 1'b0); + parameter PIPE_HAS_ASET = (C_LATENCY == 1 ? C_HAS_ASET : 1'b0); + parameter PIPE_HAS_SSET = (C_LATENCY == 1 ? C_HAS_SSET : 1'b0); + parameter PIPE_HAS_SINIT = (C_LATENCY == 1 ? C_HAS_SINIT : 1'b0); + + parameter PIPE2_HAS_ACLR = (C_LATENCY == 2 ? C_HAS_ACLR : 1'b0); + parameter PIPE2_HAS_AINIT = (C_LATENCY == 2 ? C_HAS_AINIT : 1'b0); + parameter PIPE2_HAS_ASET = (C_LATENCY == 2 ? C_HAS_ASET : 1'b0); + parameter PIPE2_HAS_SSET = (C_LATENCY == 2 ? C_HAS_SSET : 1'b0); + parameter PIPE2_HAS_SINIT = (C_LATENCY == 2 ? C_HAS_SINIT : 1'b0); + + + input [C_INPUTS-1 : 0] M; + input [C_SEL_WIDTH-1 : 0] S; + input CLK; + input CE; + input ACLR; + input ASET; + input AINIT; + input SCLR; + input SSET; + input SINIT; + output O; + output Q; + + // Internal values to drive signals when input is missing + + reg intO; + reg intQ; +// reg lastCLK; + + wire STAGE1; + wire STAGE2; + wire STAGE3; + + wire Q = (C_HAS_Q == 1 ? intQ : 1'bx); + wire O = (C_HAS_O == 1 ? intO : 1'bx); + + // Sort out default values for missing ports + + integer j, k; + integer m, unknown; + + // Register on output by default + C_REG_FD_V4_0 #(C_AINIT_VAL, C_ENABLE_RLOCS, PIPE_HAS_ACLR, PIPE_HAS_AINIT, PIPE_HAS_ASET, + C_HAS_CE, C_HAS_SCLR, PIPE_HAS_SINIT, PIPE_HAS_SSET, + C_SINIT_VAL, C_SYNC_ENABLE, C_SYNC_PRIORITY, 1) + reg1 (.D(intO), .CLK(CLK), .CE(CE), .ACLR(ACLR), .ASET(ASET), + .AINIT(AINIT), .SCLR(SCLR), .SSET(SSET), .SINIT(SINIT), + .Q(STAGE1)); + + C_REG_FD_V4_0 #(C_AINIT_VAL, C_ENABLE_RLOCS, PIPE2_HAS_ACLR, PIPE2_HAS_AINIT, PIPE2_HAS_ASET, + C_HAS_CE, C_HAS_SCLR, PIPE2_HAS_SINIT, PIPE2_HAS_SSET, + C_SINIT_VAL, C_SYNC_ENABLE, C_SYNC_PRIORITY, 1) + reg2 (.D(STAGE1), .CLK(CLK), .CE(CE), .ACLR(ACLR), .ASET(ASET), + .AINIT(AINIT), .SCLR(SCLR), .SSET(SSET), .SINIT(SINIT), + .Q(STAGE2)); + + C_REG_FD_V4_0 #(C_AINIT_VAL, C_ENABLE_RLOCS, C_HAS_ACLR, C_HAS_AINIT, C_HAS_ASET, + C_HAS_CE, C_HAS_SCLR, C_HAS_SINIT, C_HAS_SSET, + C_SINIT_VAL, C_SYNC_ENABLE, C_SYNC_PRIORITY, 1) + reg3 (.D(STAGE2), .CLK(CLK), .CE(CE), .ACLR(ACLR), .ASET(ASET), + .AINIT(AINIT), .SCLR(SCLR), .SSET(SSET), .SINIT(SINIT), + .Q(STAGE3)); + + initial + begin + + #1; + + k = 1; + m = 1; + unknown = 0; + for(j = 0; j < C_SEL_WIDTH; j = j + 1) + begin + if(S[j] === 1) + k = k + m; + else if(S[j] === 1'bz || S[j] === 1'bx) + unknown = 1; + m = m * 2; + end + + if(unknown == 1) + intO <= 1'bx; + else + intO <= M[k-1]; + + end + +// always @(CLK) +// lastCLK <= CLK; + + always@(M or S) + begin + k = 1; + m = 1; + unknown = 0; + for(j = 0; j < C_SEL_WIDTH; j = j + 1) + begin + if(S[j] === 1) + k = k + m; + else if(S[j] === 1'bz || S[j] === 1'bx) + unknown = 1; + m = m * 2; + end + + if(unknown == 1) + intO <= #1 1'bx; + else + intO <= #1 M[k-1]; + end + + + // Register Output Settings + always + begin + //------------------------------ + //-- REGISTER CLOCKED OUTPUTS -- + //------------------------------ + if (C_LATENCY === 1) + intQ = STAGE1; + + else if (C_LATENCY === 2) + intQ = STAGE2; + + else + intQ = STAGE3; + + @(STAGE1 or STAGE2 or STAGE3); + end + + + function defval; + input i; + input hassig; + input val; + begin + if(hassig == 1) + defval = i; + else + defval = val; + end + endfunction + +endmodule + +`undef c_set +`undef c_clear +`undef c_override +`undef c_no_override + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/C_MUX_BIT_V5_0.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/C_MUX_BIT_V5_0.v new file mode 100644 index 0000000..de8bd76 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/C_MUX_BIT_V5_0.v @@ -0,0 +1,190 @@ +/* $Id: C_MUX_BIT_V5_0.v,v 1.17 2008/09/08 20:05:56 akennedy Exp $ +-- +-- Filename - C_MUX_BIT_V5_0.v +-- Author - Xilinx +-- Creation - 21 Oct 1998 +-- +-- Description - This file contains the Verilog behavior for the Baseblocks C_MUX_BIT_V5_0 module +*/ + +`timescale 1ns/10ps + +`define c_set 0 +`define c_clear 1 +`define c_override 0 +`define c_no_override 1 + +module C_MUX_BIT_V5_0 (M, S, CLK, CE, ACLR, ASET, AINIT, SCLR, SSET, SINIT, O, Q); + + parameter C_AINIT_VAL = ""; + parameter C_ENABLE_RLOCS = 1; + parameter C_HAS_ACLR = 0; + parameter C_HAS_AINIT = 0; + parameter C_HAS_ASET = 0; + parameter C_HAS_CE = 0; + parameter C_HAS_O = 0; + parameter C_HAS_Q = 1; + parameter C_HAS_SCLR = 0; + parameter C_HAS_SINIT = 0; + parameter C_HAS_SSET = 0; + parameter C_INPUTS = 2; + parameter C_LATENCY = 0; + parameter C_PIPE_STAGES = 0; + parameter C_SEL_WIDTH = 1; + parameter C_SINIT_VAL = ""; + parameter C_SYNC_ENABLE = `c_override; + parameter C_SYNC_PRIORITY = `c_clear; + + // Parameters used to drive additional registers for pipelining. + + parameter PIPE_HAS_ACLR = (C_LATENCY == 1 ? C_HAS_ACLR : 1'b0); + parameter PIPE_HAS_AINIT = (C_LATENCY == 1 ? C_HAS_AINIT : 1'b0); + parameter PIPE_HAS_ASET = (C_LATENCY == 1 ? C_HAS_ASET : 1'b0); + parameter PIPE_HAS_SSET = (C_LATENCY == 1 ? C_HAS_SSET : 1'b0); + parameter PIPE_HAS_SINIT = (C_LATENCY == 1 ? C_HAS_SINIT : 1'b0); + + parameter PIPE2_HAS_ACLR = (C_LATENCY == 2 ? C_HAS_ACLR : 1'b0); + parameter PIPE2_HAS_AINIT = (C_LATENCY == 2 ? C_HAS_AINIT : 1'b0); + parameter PIPE2_HAS_ASET = (C_LATENCY == 2 ? C_HAS_ASET : 1'b0); + parameter PIPE2_HAS_SSET = (C_LATENCY == 2 ? C_HAS_SSET : 1'b0); + parameter PIPE2_HAS_SINIT = (C_LATENCY == 2 ? C_HAS_SINIT : 1'b0); + + + input [C_INPUTS-1 : 0] M; + input [C_SEL_WIDTH-1 : 0] S; + input CLK; + input CE; + input ACLR; + input ASET; + input AINIT; + input SCLR; + input SSET; + input SINIT; + output O; + output Q; + + // Internal values to drive signals when input is missing + + reg intO; + reg intQ; +// reg lastCLK; + + wire STAGE1; + wire STAGE2; + wire STAGE3; + + wire Q = (C_HAS_Q == 1 ? intQ : 1'bx); + wire O = (C_HAS_O == 1 ? intO : 1'bx); + + // Sort out default values for missing ports + + integer j, k; + integer m, unknown; + + // Register on output by default + C_REG_FD_V5_0 #(C_AINIT_VAL, C_ENABLE_RLOCS, PIPE_HAS_ACLR, PIPE_HAS_AINIT, PIPE_HAS_ASET, + C_HAS_CE, C_HAS_SCLR, PIPE_HAS_SINIT, PIPE_HAS_SSET, + C_SINIT_VAL, C_SYNC_ENABLE, C_SYNC_PRIORITY, 1) + reg1 (.D(intO), .CLK(CLK), .CE(CE), .ACLR(ACLR), .ASET(ASET), + .AINIT(AINIT), .SCLR(SCLR), .SSET(SSET), .SINIT(SINIT), + .Q(STAGE1)); + + C_REG_FD_V5_0 #(C_AINIT_VAL, C_ENABLE_RLOCS, PIPE2_HAS_ACLR, PIPE2_HAS_AINIT, PIPE2_HAS_ASET, + C_HAS_CE, C_HAS_SCLR, PIPE2_HAS_SINIT, PIPE2_HAS_SSET, + C_SINIT_VAL, C_SYNC_ENABLE, C_SYNC_PRIORITY, 1) + reg2 (.D(STAGE1), .CLK(CLK), .CE(CE), .ACLR(ACLR), .ASET(ASET), + .AINIT(AINIT), .SCLR(SCLR), .SSET(SSET), .SINIT(SINIT), + .Q(STAGE2)); + + C_REG_FD_V5_0 #(C_AINIT_VAL, C_ENABLE_RLOCS, C_HAS_ACLR, C_HAS_AINIT, C_HAS_ASET, + C_HAS_CE, C_HAS_SCLR, C_HAS_SINIT, C_HAS_SSET, + C_SINIT_VAL, C_SYNC_ENABLE, C_SYNC_PRIORITY, 1) + reg3 (.D(STAGE2), .CLK(CLK), .CE(CE), .ACLR(ACLR), .ASET(ASET), + .AINIT(AINIT), .SCLR(SCLR), .SSET(SSET), .SINIT(SINIT), + .Q(STAGE3)); + + initial + begin + + #1; + + k = 1; + m = 1; + unknown = 0; + for(j = 0; j < C_SEL_WIDTH; j = j + 1) + begin + if(S[j] === 1) + k = k + m; + else if(S[j] === 1'bz || S[j] === 1'bx) + unknown = 1; + m = m * 2; + end + + if(unknown == 1) + intO <= 1'bx; + else + intO <= M[k-1]; + + end + +// always @(CLK) +// lastCLK <= CLK; + + always@(M or S) + begin + k = 1; + m = 1; + unknown = 0; + for(j = 0; j < C_SEL_WIDTH; j = j + 1) + begin + if(S[j] === 1) + k = k + m; + else if(S[j] === 1'bz || S[j] === 1'bx) + unknown = 1; + m = m * 2; + end + + if(unknown == 1) + intO <= #1 1'bx; + else + intO <= #1 M[k-1]; + end + + + // Register Output Settings + always + begin + //------------------------------ + //-- REGISTER CLOCKED OUTPUTS -- + //------------------------------ + if (C_LATENCY === 1) + intQ = STAGE1; + + else if (C_LATENCY === 2) + intQ = STAGE2; + + else + intQ = STAGE3; + + @(STAGE1 or STAGE2 or STAGE3); + end + + + function defval; + input i; + input hassig; + input val; + begin + if(hassig == 1) + defval = i; + else + defval = val; + end + endfunction + +endmodule + +`undef c_set +`undef c_clear +`undef c_override +`undef c_no_override diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/C_MUX_BIT_V6_0.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/C_MUX_BIT_V6_0.v new file mode 100644 index 0000000..c9ae528 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/C_MUX_BIT_V6_0.v @@ -0,0 +1,222 @@ +// Copyright(C) 2002 by Xilinx, Inc. All rights reserved. +// This text contains proprietary, confidential +// information of Xilinx, Inc., is distributed +// under license from Xilinx, Inc., and may be used, +// copied and/or disclosed only pursuant to the terms +// of a valid license agreement with Xilinx, Inc. This copyright +// notice must be retained as part of this text at all times. + + +/* $Id: C_MUX_BIT_V6_0.v,v 1.16 2008/09/08 20:06:04 akennedy Exp $ +-- +-- Filename - C_MUX_BIT_V6_0.v +-- Author - Xilinx +-- Creation - 21 Oct 1998 +-- +-- Description - This file contains the Verilog behavior for the Baseblocks C_MUX_BIT_V6_0 module +*/ + +`timescale 1ns/10ps + +`define c_set 0 +`define c_clear 1 +`define c_override 0 +`define c_no_override 1 + +module C_MUX_BIT_V6_0 (M, S, CLK, CE, ACLR, ASET, AINIT, SCLR, SSET, SINIT, O, Q); + + parameter C_AINIT_VAL = ""; + parameter C_ENABLE_RLOCS = 1; + parameter C_HAS_ACLR = 0; + parameter C_HAS_AINIT = 0; + parameter C_HAS_ASET = 0; + parameter C_HAS_CE = 0; + parameter C_HAS_O = 0; + parameter C_HAS_Q = 1; + parameter C_HAS_SCLR = 0; + parameter C_HAS_SINIT = 0; + parameter C_HAS_SSET = 0; + parameter C_HEIGHT = 0; + parameter C_INPUTS = 2; + parameter C_LATENCY = 0; + parameter C_PIPE_STAGES = 0; + parameter C_SEL_WIDTH = 1; + parameter C_SINIT_VAL = ""; + parameter C_SYNC_ENABLE = `c_override; + parameter C_SYNC_PRIORITY = `c_clear; + + // Parameters used to drive additional registers for pipelining. + + parameter PIPE_HAS_ACLR = (C_LATENCY == 1 ? C_HAS_ACLR : 1'b0); + parameter PIPE_HAS_AINIT = (C_LATENCY == 1 ? C_HAS_AINIT : 1'b0); + parameter PIPE_HAS_ASET = (C_LATENCY == 1 ? C_HAS_ASET : 1'b0); + parameter PIPE_HAS_SSET = (C_LATENCY == 1 ? C_HAS_SSET : 1'b0); + parameter PIPE_HAS_SINIT = (C_LATENCY == 1 ? C_HAS_SINIT : 1'b0); + + parameter PIPE2_HAS_ACLR = (C_LATENCY == 2 ? C_HAS_ACLR : 1'b0); + parameter PIPE2_HAS_AINIT = (C_LATENCY == 2 ? C_HAS_AINIT : 1'b0); + parameter PIPE2_HAS_ASET = (C_LATENCY == 2 ? C_HAS_ASET : 1'b0); + parameter PIPE2_HAS_SSET = (C_LATENCY == 2 ? C_HAS_SSET : 1'b0); + parameter PIPE2_HAS_SINIT = (C_LATENCY == 2 ? C_HAS_SINIT : 1'b0); + + + input [C_INPUTS-1 : 0] M; + input [C_SEL_WIDTH-1 : 0] S; + input CLK; + input CE; + input ACLR; + input ASET; + input AINIT; + input SCLR; + input SSET; + input SINIT; + output O; + output Q; + + // Internal values to drive signals when input is missing + + reg intO; + reg intQ; +// reg lastCLK; + + wire STAGE1; + wire STAGE2; + wire STAGE3; + + wire Q = (C_HAS_Q == 1 ? intQ : 1'bx); + wire O = (C_HAS_O == 1 ? intO : 1'bx); + + // Sort out default values for missing ports + + integer j, k; + integer m, unknown; + + // Register on output by default + + C_REG_FD_V6_0 #(C_AINIT_VAL, C_ENABLE_RLOCS, PIPE_HAS_ACLR, PIPE_HAS_AINIT, PIPE_HAS_ASET, + C_HAS_CE, C_HAS_SCLR, PIPE_HAS_SINIT, PIPE_HAS_SSET, + C_SINIT_VAL, C_SYNC_ENABLE, C_SYNC_PRIORITY, 1) + reg1 (.D(intO), .CLK(CLK), .CE(CE), .ACLR(ACLR), .ASET(ASET), + .AINIT(AINIT), .SCLR(SCLR), .SSET(SSET), .SINIT(SINIT), + .Q(STAGE1)); + + + C_REG_FD_V6_0 #(C_AINIT_VAL, C_ENABLE_RLOCS, PIPE2_HAS_ACLR, PIPE2_HAS_AINIT, PIPE2_HAS_ASET, + C_HAS_CE, C_HAS_SCLR, PIPE2_HAS_SINIT, PIPE2_HAS_SSET, + C_SINIT_VAL, C_SYNC_ENABLE, C_SYNC_PRIORITY, 1) + reg2 (.D(STAGE1), .CLK(CLK), .CE(CE), .ACLR(ACLR), .ASET(ASET), + .AINIT(AINIT), .SCLR(SCLR), .SSET(SSET), .SINIT(SINIT), + .Q(STAGE2)); + + + /* These two register could be used if full options were desired for internal + pipelining registers... + + C_REG_FD_V6_0 #(C_AINIT_VAL, C_ENABLE_RLOCS, C_HAS_ACLR, C_HAS_AINIT, C_HAS_ASET, + C_HAS_CE, C_HAS_SCLR, C_HAS_SINIT, C_HAS_SSET, + C_SINIT_VAL, C_SYNC_ENABLE, C_SYNC_PRIORITY, 1) + reg1 (.D(intO), .CLK(CLK), .CE(CE), .ACLR(ACLR), .ASET(ASET), + .AINIT(AINIT), .SCLR(SCLR), .SSET(SSET), .SINIT(SINIT), + .Q(STAGE1)); + + C_REG_FD_V6_0 #(C_AINIT_VAL, C_ENABLE_RLOCS, C_HAS_ACLR, C_HAS_AINIT, C_HAS_ASET, + C_HAS_CE, C_HAS_SCLR, C_HAS_SINIT, C_HAS_SSET, + C_SINIT_VAL, C_SYNC_ENABLE, C_SYNC_PRIORITY, 1) + reg2 (.D(STAGE1), .CLK(CLK), .CE(CE), .ACLR(ACLR), .ASET(ASET), + .AINIT(AINIT), .SCLR(SCLR), .SSET(SSET), .SINIT(SINIT), + .Q(STAGE2)); */ + + + + C_REG_FD_V6_0 #(C_AINIT_VAL, C_ENABLE_RLOCS, C_HAS_ACLR, C_HAS_AINIT, C_HAS_ASET, + C_HAS_CE, C_HAS_SCLR, C_HAS_SINIT, C_HAS_SSET, + C_SINIT_VAL, C_SYNC_ENABLE, C_SYNC_PRIORITY, 1) + reg3 (.D(STAGE2), .CLK(CLK), .CE(CE), .ACLR(ACLR), .ASET(ASET), + .AINIT(AINIT), .SCLR(SCLR), .SSET(SSET), .SINIT(SINIT), + .Q(STAGE3)); + + initial + begin + + #1; + + k = 1; + m = 1; + unknown = 0; + for(j = 0; j < C_SEL_WIDTH; j = j + 1) + begin + if(S[j] === 1) + k = k + m; + else if(S[j] === 1'bz || S[j] === 1'bx) + unknown = 1; + m = m * 2; + end + + if(unknown == 1) + intO <= 1'bx; + else + intO <= M[k-1]; + + end + +// always @(CLK) +// lastCLK <= CLK; + + always@(M or S) + begin + k = 1; + m = 1; + unknown = 0; + for(j = 0; j < C_SEL_WIDTH; j = j + 1) + begin + if(S[j] === 1) + k = k + m; + else if(S[j] === 1'bz || S[j] === 1'bx) + unknown = 1; + m = m * 2; + end + + if(unknown == 1) + intO <= #1 1'bx; + else + intO <= #1 M[k-1]; + end + + + // Register Output Settings + always + begin + //------------------------------ + //-- REGISTER CLOCKED OUTPUTS -- + //------------------------------ + if (C_LATENCY === 1) + intQ = STAGE1; + + else if (C_LATENCY === 2) + intQ = STAGE2; + + else + intQ = STAGE3; + + @(STAGE1 or STAGE2 or STAGE3); + end + + + function defval; + input i; + input hassig; + input val; + begin + if(hassig == 1) + defval = i; + else + defval = val; + end + endfunction + +endmodule + +`undef c_set +`undef c_clear +`undef c_override +`undef c_no_override diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/C_MUX_BIT_V7_0.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/C_MUX_BIT_V7_0.v new file mode 100644 index 0000000..e96de0a --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/C_MUX_BIT_V7_0.v @@ -0,0 +1,251 @@ +// Copyright(C) 2003 by Xilinx, Inc. All rights reserved. +// This text/file contains proprietary, confidential +// information of Xilinx, Inc., is distributed under license +// from Xilinx, Inc., and may be used, copied and/or +// disclosed only pursuant to the terms of a valid license +// agreement with Xilinx, Inc. Xilinx hereby grants you +// a license to use this text/file solely for design, simulation, +// implementation and creation of design files limited +// to Xilinx devices or technologies. Use with non-Xilinx +// devices or technologies is expressly prohibited and +// immediately terminates your license unless covered by +// a separate agreement. +// +// Xilinx is providing this design, code, or information +// "as is" solely for use in developing programs and +// solutions for Xilinx devices. By providing this design, +// code, or information as one possible implementation of +// this feature, application or standard, Xilinx is making no +// representation that this implementation is free from any +// claims of infringement. You are responsible for +// obtaining any rights you may require for your implementation. +// Xilinx expressly disclaims any warranty whatsoever with +// respect to the adequacy of the implementation, including +// but not limited to any warranties or representations that this +// implementation is free from claims of infringement, implied +// warranties of merchantability or fitness for a particular +// purpose. +// +// Xilinx products are not intended for use in life support +// appliances, devices, or systems. Use in such applications are +// expressly prohibited. +// +// This copyright and support notice must be retained as part +// of this text at all times. (c) Copyright 1995-2003 Xilinx, Inc. +// All rights reserved. + + + +/* $Id: C_MUX_BIT_V7_0.v,v 1.13 2008/09/08 20:06:13 akennedy Exp $ +-- +-- Filename - C_MUX_BIT_V7_0.v +-- Author - Xilinx +-- Creation - 21 Oct 1998 +-- +-- Description - This file contains the Verilog behavior for the Baseblocks C_MUX_BIT_V7_0 module +*/ + +`timescale 1ns/10ps + +`define c_set 0 +`define c_clear 1 +`define c_override 0 +`define c_no_override 1 + +module C_MUX_BIT_V7_0 (M, S, CLK, CE, ACLR, ASET, AINIT, SCLR, SSET, SINIT, O, Q); + + parameter C_AINIT_VAL = ""; + parameter C_ENABLE_RLOCS = 1; + parameter C_HAS_ACLR = 0; + parameter C_HAS_AINIT = 0; + parameter C_HAS_ASET = 0; + parameter C_HAS_CE = 0; + parameter C_HAS_O = 0; + parameter C_HAS_Q = 1; + parameter C_HAS_SCLR = 0; + parameter C_HAS_SINIT = 0; + parameter C_HAS_SSET = 0; + parameter C_HEIGHT = 0; + parameter C_INPUTS = 2; + parameter C_LATENCY = 0; + parameter C_PIPE_STAGES = 0; + parameter C_SEL_WIDTH = 1; + parameter C_SINIT_VAL = ""; + parameter C_SYNC_ENABLE = `c_override; + parameter C_SYNC_PRIORITY = `c_clear; + + // Parameters used to drive additional registers for pipelining. + + parameter PIPE_HAS_ACLR = (C_LATENCY == 1 ? C_HAS_ACLR : 1'b0); + parameter PIPE_HAS_AINIT = (C_LATENCY == 1 ? C_HAS_AINIT : 1'b0); + parameter PIPE_HAS_ASET = (C_LATENCY == 1 ? C_HAS_ASET : 1'b0); + parameter PIPE_HAS_SSET = (C_LATENCY == 1 ? C_HAS_SSET : 1'b0); + parameter PIPE_HAS_SINIT = (C_LATENCY == 1 ? C_HAS_SINIT : 1'b0); + + parameter PIPE2_HAS_ACLR = (C_LATENCY == 2 ? C_HAS_ACLR : 1'b0); + parameter PIPE2_HAS_AINIT = (C_LATENCY == 2 ? C_HAS_AINIT : 1'b0); + parameter PIPE2_HAS_ASET = (C_LATENCY == 2 ? C_HAS_ASET : 1'b0); + parameter PIPE2_HAS_SSET = (C_LATENCY == 2 ? C_HAS_SSET : 1'b0); + parameter PIPE2_HAS_SINIT = (C_LATENCY == 2 ? C_HAS_SINIT : 1'b0); + + + input [C_INPUTS-1 : 0] M; + input [C_SEL_WIDTH-1 : 0] S; + input CLK; + input CE; + input ACLR; + input ASET; + input AINIT; + input SCLR; + input SSET; + input SINIT; + output O; + output Q; + + // Internal values to drive signals when input is missing + + reg intO; + reg intQ; +// reg lastCLK; + + wire STAGE1; + wire STAGE2; + wire STAGE3; + + wire Q = (C_HAS_Q == 1 ? intQ : 1'bx); + wire O = (C_HAS_O == 1 ? intO : 1'bx); + + // Sort out default values for missing ports + + integer j, k; + integer m, unknown; + + // Register on output by default + + C_REG_FD_V7_0 #(C_AINIT_VAL, C_ENABLE_RLOCS, PIPE_HAS_ACLR, PIPE_HAS_AINIT, PIPE_HAS_ASET, + C_HAS_CE, C_HAS_SCLR, PIPE_HAS_SINIT, PIPE_HAS_SSET, + C_SINIT_VAL, C_SYNC_ENABLE, C_SYNC_PRIORITY, 1) + reg1 (.D(intO), .CLK(CLK), .CE(CE), .ACLR(ACLR), .ASET(ASET), + .AINIT(AINIT), .SCLR(SCLR), .SSET(SSET), .SINIT(SINIT), + .Q(STAGE1)); + + + C_REG_FD_V7_0 #(C_AINIT_VAL, C_ENABLE_RLOCS, PIPE2_HAS_ACLR, PIPE2_HAS_AINIT, PIPE2_HAS_ASET, + C_HAS_CE, C_HAS_SCLR, PIPE2_HAS_SINIT, PIPE2_HAS_SSET, + C_SINIT_VAL, C_SYNC_ENABLE, C_SYNC_PRIORITY, 1) + reg2 (.D(STAGE1), .CLK(CLK), .CE(CE), .ACLR(ACLR), .ASET(ASET), + .AINIT(AINIT), .SCLR(SCLR), .SSET(SSET), .SINIT(SINIT), + .Q(STAGE2)); + + + /* These two register could be used if full options were desired for internal + pipelining registers... + + C_REG_FD_V7_0 #(C_AINIT_VAL, C_ENABLE_RLOCS, C_HAS_ACLR, C_HAS_AINIT, C_HAS_ASET, + C_HAS_CE, C_HAS_SCLR, C_HAS_SINIT, C_HAS_SSET, + C_SINIT_VAL, C_SYNC_ENABLE, C_SYNC_PRIORITY, 1) + reg1 (.D(intO), .CLK(CLK), .CE(CE), .ACLR(ACLR), .ASET(ASET), + .AINIT(AINIT), .SCLR(SCLR), .SSET(SSET), .SINIT(SINIT), + .Q(STAGE1)); + + C_REG_FD_V7_0 #(C_AINIT_VAL, C_ENABLE_RLOCS, C_HAS_ACLR, C_HAS_AINIT, C_HAS_ASET, + C_HAS_CE, C_HAS_SCLR, C_HAS_SINIT, C_HAS_SSET, + C_SINIT_VAL, C_SYNC_ENABLE, C_SYNC_PRIORITY, 1) + reg2 (.D(STAGE1), .CLK(CLK), .CE(CE), .ACLR(ACLR), .ASET(ASET), + .AINIT(AINIT), .SCLR(SCLR), .SSET(SSET), .SINIT(SINIT), + .Q(STAGE2)); */ + + + + C_REG_FD_V7_0 #(C_AINIT_VAL, C_ENABLE_RLOCS, C_HAS_ACLR, C_HAS_AINIT, C_HAS_ASET, + C_HAS_CE, C_HAS_SCLR, C_HAS_SINIT, C_HAS_SSET, + C_SINIT_VAL, C_SYNC_ENABLE, C_SYNC_PRIORITY, 1) + reg3 (.D(STAGE2), .CLK(CLK), .CE(CE), .ACLR(ACLR), .ASET(ASET), + .AINIT(AINIT), .SCLR(SCLR), .SSET(SSET), .SINIT(SINIT), + .Q(STAGE3)); + + initial + begin + + #1; + + k = 1; + m = 1; + unknown = 0; + for(j = 0; j < C_SEL_WIDTH; j = j + 1) + begin + if(S[j] === 1) + k = k + m; + else if(S[j] === 1'bz || S[j] === 1'bx) + unknown = 1; + m = m * 2; + end + + if(unknown == 1) + intO <= 1'bx; + else + intO <= M[k-1]; + + end + +// always @(CLK) +// lastCLK <= CLK; + + always@(M or S) + begin + k = 1; + m = 1; + unknown = 0; + for(j = 0; j < C_SEL_WIDTH; j = j + 1) + begin + if(S[j] === 1) + k = k + m; + else if(S[j] === 1'bz || S[j] === 1'bx) + unknown = 1; + m = m * 2; + end + + if(unknown == 1) + intO <= #1 1'bx; + else + intO <= #1 M[k-1]; + end + + + // Register Output Settings + always + begin + //------------------------------ + //-- REGISTER CLOCKED OUTPUTS -- + //------------------------------ + if (C_LATENCY === 1) + intQ = STAGE1; + + else if (C_LATENCY === 2) + intQ = STAGE2; + + else + intQ = STAGE3; + + @(STAGE1 or STAGE2 or STAGE3); + end + + + function defval; + input i; + input hassig; + input val; + begin + if(hassig == 1) + defval = i; + else + defval = val; + end + endfunction + +endmodule + +`undef c_set +`undef c_clear +`undef c_override +`undef c_no_override diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/C_MUX_BUS_V4_0.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/C_MUX_BUS_V4_0.v new file mode 100644 index 0000000..5049030 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/C_MUX_BUS_V4_0.v @@ -0,0 +1,399 @@ +/* $Id: C_MUX_BUS_V4_0.v,v 1.11 2008/09/08 20:05:46 akennedy Exp $ +-- +-- Filename - C_MUX_BUS_V4_0.v +-- Author - Xilinx +-- Creation - 4 Feb 1999 +-- +-- Description - This file contains the Verilog behavior for the Baseblocks C_MUX_BUS_V4_0 module +*/ + + + +`define c_set 0 +`define c_clear 1 +`define c_override 0 +`define c_no_override 1 +`define c_lut_based 0 +`define c_buft_based 1 + + + +`define allmyXs {C_WIDTH{1'bx}} +`define allmyZs {C_WIDTH{1'bz}} + +module C_MUX_BUS_V4_0 (MA, MB, MC, MD, ME, MF, MG, MH, + MAA, MAB, MAC, MAD, MAE, MAF, MAG, MAH, + MBA, MBB, MBC, MBD, MBE, MBF, MBG, MBH, + MCA, MCB, MCC, MCD, MCE, MCF, MCG, MCH, + S, CLK, CE, EN, ACLR, ASET, AINIT, + SCLR, SSET, SINIT, O, Q); + + parameter C_AINIT_VAL = ""; + parameter C_ENABLE_RLOCS = 1; + parameter C_HAS_ACLR = 0; + parameter C_HAS_AINIT = 0; + parameter C_HAS_ASET = 0; + parameter C_HAS_CE = 0; + parameter C_HAS_EN = 0; + parameter C_HAS_O = 0; + parameter C_HAS_Q = 1; + parameter C_HAS_SCLR = 1; + parameter C_HAS_SINIT = 0; + parameter C_HAS_SSET = 1; + parameter C_INPUTS = 2; + parameter C_LATENCY = 1; + parameter C_MUX_TYPE = `c_lut_based; + parameter C_SEL_WIDTH = 1; + parameter C_SINIT_VAL = ""; + parameter C_SYNC_ENABLE = `c_override; + parameter C_SYNC_PRIORITY = `c_clear; + parameter C_WIDTH = 2; + + // Parameters, used to drive additional register, for pipelining. + parameter PIPE_HAS_ACLR = (C_LATENCY == 1 ? C_HAS_ACLR : 1'b0); + parameter PIPE_HAS_AINIT = (C_LATENCY == 1 ? C_HAS_AINIT : 1'b0); + parameter PIPE_HAS_ASET = (C_LATENCY == 1 ? C_HAS_ASET : 1'b0); + parameter PIPE_HAS_SSET = (C_LATENCY == 1 ? C_HAS_SSET : 1'b0); + parameter PIPE_HAS_SINIT = (C_LATENCY == 1 ? C_HAS_SINIT : 1'b0); + + + input [C_WIDTH-1 : 0] MA; + input [C_WIDTH-1 : 0] MB; + input [C_WIDTH-1 : 0] MC; + input [C_WIDTH-1 : 0] MD; + input [C_WIDTH-1 : 0] ME; + input [C_WIDTH-1 : 0] MF; + input [C_WIDTH-1 : 0] MG; + input [C_WIDTH-1 : 0] MH; + input [C_WIDTH-1 : 0] MAA; + input [C_WIDTH-1 : 0] MAB; + input [C_WIDTH-1 : 0] MAC; + input [C_WIDTH-1 : 0] MAD; + input [C_WIDTH-1 : 0] MAE; + input [C_WIDTH-1 : 0] MAF; + input [C_WIDTH-1 : 0] MAG; + input [C_WIDTH-1 : 0] MAH; + input [C_WIDTH-1 : 0] MBA; + input [C_WIDTH-1 : 0] MBB; + input [C_WIDTH-1 : 0] MBC; + input [C_WIDTH-1 : 0] MBD; + input [C_WIDTH-1 : 0] MBE; + input [C_WIDTH-1 : 0] MBF; + input [C_WIDTH-1 : 0] MBG; + input [C_WIDTH-1 : 0] MBH; + input [C_WIDTH-1 : 0] MCA; + input [C_WIDTH-1 : 0] MCB; + input [C_WIDTH-1 : 0] MCC; + input [C_WIDTH-1 : 0] MCD; + input [C_WIDTH-1 : 0] MCE; + input [C_WIDTH-1 : 0] MCF; + input [C_WIDTH-1 : 0] MCG; + input [C_WIDTH-1 : 0] MCH; + input [C_SEL_WIDTH-1 : 0] S; + input CLK; + input CE; + input EN; + input ACLR; + input ASET; + input AINIT; + input SCLR; + input SSET; + input SINIT; + output [C_WIDTH-1 : 0] O; + output [C_WIDTH-1 : 0] Q; + + // Internal values to drive signals when input is missing + wire [C_WIDTH-1 : 0] intMA = MA; + wire [C_WIDTH-1 : 0] intMB = MB; + wire [C_WIDTH-1 : 0] intMC = (C_INPUTS > 2 ? MC : `allmyXs); + wire [C_WIDTH-1 : 0] intMD = (C_INPUTS > 3 ? MD : `allmyXs); + wire [C_WIDTH-1 : 0] intME = (C_INPUTS > 4 ? ME : `allmyXs); + wire [C_WIDTH-1 : 0] intMF = (C_INPUTS > 5 ? MF : `allmyXs); + wire [C_WIDTH-1 : 0] intMG = (C_INPUTS > 6 ? MG : `allmyXs); + wire [C_WIDTH-1 : 0] intMH = (C_INPUTS > 7 ? MH : `allmyXs); + wire [C_WIDTH-1 : 0] intMAA = (C_INPUTS > 8 ? MAA : `allmyXs); + wire [C_WIDTH-1 : 0] intMAB = (C_INPUTS > 9 ? MAB : `allmyXs); + wire [C_WIDTH-1 : 0] intMAC = (C_INPUTS > 10 ? MAC : `allmyXs); + wire [C_WIDTH-1 : 0] intMAD = (C_INPUTS > 11 ? MAD : `allmyXs); + wire [C_WIDTH-1 : 0] intMAE = (C_INPUTS > 12 ? MAE : `allmyXs); + wire [C_WIDTH-1 : 0] intMAF = (C_INPUTS > 13 ? MAF : `allmyXs); + wire [C_WIDTH-1 : 0] intMAG = (C_INPUTS > 14 ? MAG : `allmyXs); + wire [C_WIDTH-1 : 0] intMAH = (C_INPUTS > 15 ? MAH : `allmyXs); + wire [C_WIDTH-1 : 0] intMBA = (C_INPUTS > 16 ? MBA : `allmyXs); + wire [C_WIDTH-1 : 0] intMBB = (C_INPUTS > 17 ? MBB : `allmyXs); + wire [C_WIDTH-1 : 0] intMBC = (C_INPUTS > 18 ? MBC : `allmyXs); + wire [C_WIDTH-1 : 0] intMBD = (C_INPUTS > 19 ? MBD : `allmyXs); + wire [C_WIDTH-1 : 0] intMBE = (C_INPUTS > 20 ? MBE : `allmyXs); + wire [C_WIDTH-1 : 0] intMBF = (C_INPUTS > 21 ? MBF : `allmyXs); + wire [C_WIDTH-1 : 0] intMBG = (C_INPUTS > 22 ? MBG : `allmyXs); + wire [C_WIDTH-1 : 0] intMBH = (C_INPUTS > 23 ? MBH : `allmyXs); + wire [C_WIDTH-1 : 0] intMCA = (C_INPUTS > 24 ? MCA : `allmyXs); + wire [C_WIDTH-1 : 0] intMCB = (C_INPUTS > 25 ? MCB : `allmyXs); + wire [C_WIDTH-1 : 0] intMCC = (C_INPUTS > 26 ? MCC : `allmyXs); + wire [C_WIDTH-1 : 0] intMCD = (C_INPUTS > 27 ? MCD : `allmyXs); + wire [C_WIDTH-1 : 0] intMCE = (C_INPUTS > 28 ? MCE : `allmyXs); + wire [C_WIDTH-1 : 0] intMCF = (C_INPUTS > 29 ? MCF : `allmyXs); + wire [C_WIDTH-1 : 0] intMCG = (C_INPUTS > 30 ? MCG : `allmyXs); + wire [C_WIDTH-1 : 0] intMCH = (C_INPUTS > 31 ? MCH : `allmyXs); + + reg [C_WIDTH-1 : 0] intO; + reg [C_WIDTH-1 : 0] intQ; + + wire [C_WIDTH-1 : 0] STAGE1; + wire [C_WIDTH-1 : 0] STAGE2; + wire [C_SEL_WIDTH-1 : 0] intS = S; + wire [C_WIDTH-1 : 0] Q = (C_HAS_Q == 1 ? intQ : `allmyXs); + wire [C_WIDTH-1 : 0] O = (C_HAS_O == 1 ? intO : `allmyXs); + wire intEN; + + + assign intEN = defval(EN, C_HAS_EN, 1); + + + integer j, k, j1, k1; + integer m, unknown, m1, unknown1; + + // Register on output by default + + C_REG_FD_V4_0 #(C_AINIT_VAL, C_ENABLE_RLOCS, PIPE_HAS_ACLR, PIPE_HAS_AINIT, PIPE_HAS_ASET, + C_HAS_CE, C_HAS_SCLR, PIPE_HAS_SINIT, PIPE_HAS_SSET, + C_SINIT_VAL, C_SYNC_ENABLE, C_SYNC_PRIORITY, C_WIDTH) + REG1 (.D(intO), .CLK(CLK), .CE(CE), .ACLR(ACLR), .ASET(ASET), + .AINIT(AINIT), .SCLR(SCLR), .SSET(SSET), .SINIT(SINIT), + .Q(STAGE1)); + + + C_REG_FD_V4_0 #(C_AINIT_VAL, C_ENABLE_RLOCS, C_HAS_ACLR, C_HAS_AINIT, C_HAS_ASET, + C_HAS_CE, C_HAS_SCLR, C_HAS_SINIT, C_HAS_SSET, + C_SINIT_VAL, C_SYNC_ENABLE, C_SYNC_PRIORITY, C_WIDTH) + REG2 (.D(STAGE1), .CLK(CLK), .CE(CE), .ACLR(ACLR), .ASET(ASET), + .AINIT(AINIT), .SCLR(SCLR), .SSET(SSET), .SINIT(SINIT), + .Q(STAGE2)); + + + initial + begin + + #1; + k = 1; + m = 1; + unknown = 0; + for(j = 0; j < C_SEL_WIDTH; j = j + 1) + begin + if(intS[j] === 1) + k = k + m; + else if(intS[j] === 1'bz || intS[j] === 1'bx) + unknown = 1; + m = m * 2; + end + + if(intEN === 1'b0) + intO <= #1 `allmyZs; + else if(intEN === 1'bx) + intO <= #1 `allmyXs; + else if(unknown == 1) + intO <= #1 `allmyXs; + else if (k == 1) + intO <= #1 intMA; + else if (k == 2) + intO <= #1 intMB; + else if (k == 3) + intO <= #1 intMC; + else if (k == 4) + intO <= #1 intMD; + else if (k == 5) + intO <= #1 intME; + else if (k == 6) + intO <= #1 intMF; + else if (k == 7) + intO <= #1 intMG; + else if (k == 8) + intO <= #1 intMH; + else if (k == 9) + intO <= #1 intMAA; + else if (k == 10) + intO <= #1 intMAB; + else if (k == 11) + intO <= #1 intMAC; + else if (k == 12) + intO <= #1 intMAD; + else if (k == 13) + intO <= #1 intMAE; + else if (k == 14) + intO <= #1 intMAF; + else if (k == 15) + intO <= #1 intMAG; + else if (k == 16) + intO <= #1 intMAH; + else if (k == 17) + intO <= #1 intMBA; + else if (k == 18) + intO <= #1 intMBB; + else if (k == 19) + intO <= #1 intMBC; + else if (k == 20) + intO <= #1 intMBD; + else if (k == 21) + intO <= #1 intMBE; + else if (k == 22) + intO <= #1 intMBF; + else if (k == 23) + intO <= #1 intMBG; + else if (k == 24) + intO <= #1 intMBH; + else if (k == 25) + intO <= #1 intMCA; + else if (k == 26) + intO <= #1 intMCB; + else if (k == 27) + intO <= #1 intMCC; + else if (k == 28) + intO <= #1 intMCD; + else if (k == 29) + intO <= #1 intMCE; + else if (k == 30) + intO <= #1 intMCF; + else if (k == 31) + intO <= #1 intMCG; + else if (k == 32) + intO <= #1 intMCH; + else + intO <= #1 `allmyXs; + + end + + always@(intMA or intMB or intMC or intMD or intME or intMF or intMG or intMH or + intMAA or intMAB or intMAC or intMAD or intMAE or intMAF or intMAG or intMAH or + intMBA or intMBB or intMBC or intMBD or intMBE or intMBF or intMBG or intMBH or + intMCA or intMCB or intMCC or intMCD or intMCE or intMCF or intMCG or intMCH or + intEN or intS) + begin + + k1 = 1; + m1 = 1; + unknown1 = 0; + for(j1 = 0; j1 < C_SEL_WIDTH; j1 = j1 + 1) + begin + if(intS[j1] === 1) + k1 = k1 + m1; + else if(intS[j1] === 1'bz || intS[j1] === 1'bx) + unknown1 = 1; + m1 = m1 * 2; + end + + + if(intEN === 1'b0) + intO = #1 `allmyZs; + else if(intEN === 1'bx) + intO = #1 `allmyXs; + else if(unknown1 == 1) + intO <= #1 `allmyXs; + else if (k1 == 1) + intO <= #1 intMA; + else if (k1 == 2) + intO <= #1 intMB; + else if (k1 == 3) + intO <= #1 intMC; + else if (k1 == 4) + intO <= #1 intMD; + else if (k1 == 5) + intO <= #1 intME; + else if (k1 == 6) + intO <= #1 intMF; + else if (k1 == 7) + intO <= #1 intMG; + else if (k1 == 8) + intO <= #1 intMH; + else if (k1 == 9) + intO <= #1 intMAA; + else if (k1 == 10) + intO <= #1 intMAB; + else if (k1 == 11) + intO <= #1 intMAC; + else if (k1 == 12) + intO <= #1 intMAD; + else if (k1 == 13) + intO <= #1 intMAE; + else if (k1 == 14) + intO <= #1 intMAF; + else if (k1 == 15) + intO <= #1 intMAG; + else if (k1 == 16) + intO <= #1 intMAH; + else if (k1 == 17) + intO <= #1 intMBA; + else if (k1 == 18) + intO <= #1 intMBB; + else if (k1 == 19) + intO <= #1 intMBC; + else if (k1 == 20) + intO <= #1 intMBD; + else if (k1 == 21) + intO <= #1 intMBE; + else if (k1 == 22) + intO <= #1 intMBF; + else if (k1 == 23) + intO <= #1 intMBG; + else if (k1 == 24) + intO <= #1 intMBH; + else if (k1 == 25) + intO <= #1 intMCA; + else if (k1 == 26) + intO <= #1 intMCB; + else if (k1 == 27) + intO <= #1 intMCC; + else if (k1 == 28) + intO <= #1 intMCD; + else if (k1 == 29) + intO <= #1 intMCE; + else if (k1 == 30) + intO <= #1 intMCF; + else if (k1 == 31) + intO <= #1 intMCG; + else if (k1 == 32) + intO <= #1 intMCH; + else + intO <= #1 `allmyXs; + + end + +// Register output settings +always +begin + //------------------------------ + //-- REGISTER CLOCKED OUTPUTS -- + //------------------------------ + if (C_LATENCY === 1) + intQ = STAGE1; + else + intQ = STAGE2; + @(STAGE1 or STAGE2); +end + + + function defval; + input i; + input hassig; + input val; + begin + if(hassig == 1) + defval = i; + else + defval = val; + end + endfunction + +endmodule + +`undef c_set +`undef c_clear +`undef c_override +`undef c_no_override +`undef c_lut_based +`undef c_buft_based + +`undef allmyXs +`undef allmyZs + + + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/C_MUX_BUS_V5_0.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/C_MUX_BUS_V5_0.v new file mode 100644 index 0000000..332c257 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/C_MUX_BUS_V5_0.v @@ -0,0 +1,396 @@ +/* $Id: C_MUX_BUS_V5_0.v,v 1.17 2008/09/08 20:05:56 akennedy Exp $ +-- +-- Filename - C_MUX_BUS_V5_0.v +-- Author - Xilinx +-- Creation - 4 Feb 1999 +-- +-- Description - This file contains the Verilog behavior for the Baseblocks C_MUX_BUS_V5_0 module +*/ + +`timescale 1ns/10ps + +`define c_set 0 +`define c_clear 1 +`define c_override 0 +`define c_no_override 1 +`define c_lut_based 0 +`define c_buft_based 1 + + + +`define allmyXs {C_WIDTH{1'bx}} +`define allmyZs {C_WIDTH{1'bz}} + +module C_MUX_BUS_V5_0 (MA, MB, MC, MD, ME, MF, MG, MH, + MAA, MAB, MAC, MAD, MAE, MAF, MAG, MAH, + MBA, MBB, MBC, MBD, MBE, MBF, MBG, MBH, + MCA, MCB, MCC, MCD, MCE, MCF, MCG, MCH, + S, CLK, CE, EN, ACLR, ASET, AINIT, + SCLR, SSET, SINIT, O, Q); + + parameter C_AINIT_VAL = ""; + parameter C_ENABLE_RLOCS = 1; + parameter C_HAS_ACLR = 0; + parameter C_HAS_AINIT = 0; + parameter C_HAS_ASET = 0; + parameter C_HAS_CE = 0; + parameter C_HAS_EN = 0; + parameter C_HAS_O = 0; + parameter C_HAS_Q = 1; + parameter C_HAS_SCLR = 1; + parameter C_HAS_SINIT = 0; + parameter C_HAS_SSET = 1; + parameter C_INPUTS = 2; + parameter C_LATENCY = 1; + parameter C_MUX_TYPE = `c_lut_based; + parameter C_SEL_WIDTH = 1; + parameter C_SINIT_VAL = ""; + parameter C_SYNC_ENABLE = `c_override; + parameter C_SYNC_PRIORITY = `c_clear; + parameter C_WIDTH = 2; + + // Parameters, used to drive additional register, for pipelining. + parameter PIPE_HAS_ACLR = (C_LATENCY == 1 ? C_HAS_ACLR : 1'b0); + parameter PIPE_HAS_AINIT = (C_LATENCY == 1 ? C_HAS_AINIT : 1'b0); + parameter PIPE_HAS_ASET = (C_LATENCY == 1 ? C_HAS_ASET : 1'b0); + parameter PIPE_HAS_SSET = (C_LATENCY == 1 ? C_HAS_SSET : 1'b0); + parameter PIPE_HAS_SINIT = (C_LATENCY == 1 ? C_HAS_SINIT : 1'b0); + + + input [C_WIDTH-1 : 0] MA; + input [C_WIDTH-1 : 0] MB; + input [C_WIDTH-1 : 0] MC; + input [C_WIDTH-1 : 0] MD; + input [C_WIDTH-1 : 0] ME; + input [C_WIDTH-1 : 0] MF; + input [C_WIDTH-1 : 0] MG; + input [C_WIDTH-1 : 0] MH; + input [C_WIDTH-1 : 0] MAA; + input [C_WIDTH-1 : 0] MAB; + input [C_WIDTH-1 : 0] MAC; + input [C_WIDTH-1 : 0] MAD; + input [C_WIDTH-1 : 0] MAE; + input [C_WIDTH-1 : 0] MAF; + input [C_WIDTH-1 : 0] MAG; + input [C_WIDTH-1 : 0] MAH; + input [C_WIDTH-1 : 0] MBA; + input [C_WIDTH-1 : 0] MBB; + input [C_WIDTH-1 : 0] MBC; + input [C_WIDTH-1 : 0] MBD; + input [C_WIDTH-1 : 0] MBE; + input [C_WIDTH-1 : 0] MBF; + input [C_WIDTH-1 : 0] MBG; + input [C_WIDTH-1 : 0] MBH; + input [C_WIDTH-1 : 0] MCA; + input [C_WIDTH-1 : 0] MCB; + input [C_WIDTH-1 : 0] MCC; + input [C_WIDTH-1 : 0] MCD; + input [C_WIDTH-1 : 0] MCE; + input [C_WIDTH-1 : 0] MCF; + input [C_WIDTH-1 : 0] MCG; + input [C_WIDTH-1 : 0] MCH; + input [C_SEL_WIDTH-1 : 0] S; + input CLK; + input CE; + input EN; + input ACLR; + input ASET; + input AINIT; + input SCLR; + input SSET; + input SINIT; + output [C_WIDTH-1 : 0] O; + output [C_WIDTH-1 : 0] Q; + + // Internal values to drive signals when input is missing + wire [C_WIDTH-1 : 0] intMA = MA; + wire [C_WIDTH-1 : 0] intMB = MB; + wire [C_WIDTH-1 : 0] intMC = (C_INPUTS > 2 ? MC : `allmyXs); + wire [C_WIDTH-1 : 0] intMD = (C_INPUTS > 3 ? MD : `allmyXs); + wire [C_WIDTH-1 : 0] intME = (C_INPUTS > 4 ? ME : `allmyXs); + wire [C_WIDTH-1 : 0] intMF = (C_INPUTS > 5 ? MF : `allmyXs); + wire [C_WIDTH-1 : 0] intMG = (C_INPUTS > 6 ? MG : `allmyXs); + wire [C_WIDTH-1 : 0] intMH = (C_INPUTS > 7 ? MH : `allmyXs); + wire [C_WIDTH-1 : 0] intMAA = (C_INPUTS > 8 ? MAA : `allmyXs); + wire [C_WIDTH-1 : 0] intMAB = (C_INPUTS > 9 ? MAB : `allmyXs); + wire [C_WIDTH-1 : 0] intMAC = (C_INPUTS > 10 ? MAC : `allmyXs); + wire [C_WIDTH-1 : 0] intMAD = (C_INPUTS > 11 ? MAD : `allmyXs); + wire [C_WIDTH-1 : 0] intMAE = (C_INPUTS > 12 ? MAE : `allmyXs); + wire [C_WIDTH-1 : 0] intMAF = (C_INPUTS > 13 ? MAF : `allmyXs); + wire [C_WIDTH-1 : 0] intMAG = (C_INPUTS > 14 ? MAG : `allmyXs); + wire [C_WIDTH-1 : 0] intMAH = (C_INPUTS > 15 ? MAH : `allmyXs); + wire [C_WIDTH-1 : 0] intMBA = (C_INPUTS > 16 ? MBA : `allmyXs); + wire [C_WIDTH-1 : 0] intMBB = (C_INPUTS > 17 ? MBB : `allmyXs); + wire [C_WIDTH-1 : 0] intMBC = (C_INPUTS > 18 ? MBC : `allmyXs); + wire [C_WIDTH-1 : 0] intMBD = (C_INPUTS > 19 ? MBD : `allmyXs); + wire [C_WIDTH-1 : 0] intMBE = (C_INPUTS > 20 ? MBE : `allmyXs); + wire [C_WIDTH-1 : 0] intMBF = (C_INPUTS > 21 ? MBF : `allmyXs); + wire [C_WIDTH-1 : 0] intMBG = (C_INPUTS > 22 ? MBG : `allmyXs); + wire [C_WIDTH-1 : 0] intMBH = (C_INPUTS > 23 ? MBH : `allmyXs); + wire [C_WIDTH-1 : 0] intMCA = (C_INPUTS > 24 ? MCA : `allmyXs); + wire [C_WIDTH-1 : 0] intMCB = (C_INPUTS > 25 ? MCB : `allmyXs); + wire [C_WIDTH-1 : 0] intMCC = (C_INPUTS > 26 ? MCC : `allmyXs); + wire [C_WIDTH-1 : 0] intMCD = (C_INPUTS > 27 ? MCD : `allmyXs); + wire [C_WIDTH-1 : 0] intMCE = (C_INPUTS > 28 ? MCE : `allmyXs); + wire [C_WIDTH-1 : 0] intMCF = (C_INPUTS > 29 ? MCF : `allmyXs); + wire [C_WIDTH-1 : 0] intMCG = (C_INPUTS > 30 ? MCG : `allmyXs); + wire [C_WIDTH-1 : 0] intMCH = (C_INPUTS > 31 ? MCH : `allmyXs); + + reg [C_WIDTH-1 : 0] intO; + reg [C_WIDTH-1 : 0] intQ; + + wire [C_WIDTH-1 : 0] STAGE1; + wire [C_WIDTH-1 : 0] STAGE2; + wire [C_SEL_WIDTH-1 : 0] intS = S; + wire [C_WIDTH-1 : 0] Q = (C_HAS_Q == 1 ? intQ : `allmyXs); + wire [C_WIDTH-1 : 0] O = (C_HAS_O == 1 ? intO : `allmyXs); + wire intEN; + + + assign intEN = defval(EN, C_HAS_EN, 1); + + + integer j, k, j1, k1; + integer m, unknown, m1, unknown1; + + // Register on output by default + + C_REG_FD_V5_0 #(C_AINIT_VAL, C_ENABLE_RLOCS, PIPE_HAS_ACLR, PIPE_HAS_AINIT, PIPE_HAS_ASET, + C_HAS_CE, C_HAS_SCLR, PIPE_HAS_SINIT, PIPE_HAS_SSET, + C_SINIT_VAL, C_SYNC_ENABLE, C_SYNC_PRIORITY, C_WIDTH) + REG1 (.D(intO), .CLK(CLK), .CE(CE), .ACLR(ACLR), .ASET(ASET), + .AINIT(AINIT), .SCLR(SCLR), .SSET(SSET), .SINIT(SINIT), + .Q(STAGE1)); + + + C_REG_FD_V5_0 #(C_AINIT_VAL, C_ENABLE_RLOCS, C_HAS_ACLR, C_HAS_AINIT, C_HAS_ASET, + C_HAS_CE, C_HAS_SCLR, C_HAS_SINIT, C_HAS_SSET, + C_SINIT_VAL, C_SYNC_ENABLE, C_SYNC_PRIORITY, C_WIDTH) + REG2 (.D(STAGE1), .CLK(CLK), .CE(CE), .ACLR(ACLR), .ASET(ASET), + .AINIT(AINIT), .SCLR(SCLR), .SSET(SSET), .SINIT(SINIT), + .Q(STAGE2)); + + + initial + begin + + #1; + k = 1; + m = 1; + unknown = 0; + for(j = 0; j < C_SEL_WIDTH; j = j + 1) + begin + if(intS[j] === 1) + k = k + m; + else if(intS[j] === 1'bz || intS[j] === 1'bx) + unknown = 1; + m = m * 2; + end + + if(intEN === 1'b0) + intO <= #1 `allmyZs; + else if(intEN === 1'bx) + intO <= #1 `allmyXs; + else if(unknown == 1) + intO <= #1 `allmyXs; + else if (k == 1) + intO <= #1 intMA; + else if (k == 2) + intO <= #1 intMB; + else if (k == 3) + intO <= #1 intMC; + else if (k == 4) + intO <= #1 intMD; + else if (k == 5) + intO <= #1 intME; + else if (k == 6) + intO <= #1 intMF; + else if (k == 7) + intO <= #1 intMG; + else if (k == 8) + intO <= #1 intMH; + else if (k == 9) + intO <= #1 intMAA; + else if (k == 10) + intO <= #1 intMAB; + else if (k == 11) + intO <= #1 intMAC; + else if (k == 12) + intO <= #1 intMAD; + else if (k == 13) + intO <= #1 intMAE; + else if (k == 14) + intO <= #1 intMAF; + else if (k == 15) + intO <= #1 intMAG; + else if (k == 16) + intO <= #1 intMAH; + else if (k == 17) + intO <= #1 intMBA; + else if (k == 18) + intO <= #1 intMBB; + else if (k == 19) + intO <= #1 intMBC; + else if (k == 20) + intO <= #1 intMBD; + else if (k == 21) + intO <= #1 intMBE; + else if (k == 22) + intO <= #1 intMBF; + else if (k == 23) + intO <= #1 intMBG; + else if (k == 24) + intO <= #1 intMBH; + else if (k == 25) + intO <= #1 intMCA; + else if (k == 26) + intO <= #1 intMCB; + else if (k == 27) + intO <= #1 intMCC; + else if (k == 28) + intO <= #1 intMCD; + else if (k == 29) + intO <= #1 intMCE; + else if (k == 30) + intO <= #1 intMCF; + else if (k == 31) + intO <= #1 intMCG; + else if (k == 32) + intO <= #1 intMCH; + else + intO <= #1 `allmyXs; + + end + + always@(intMA or intMB or intMC or intMD or intME or intMF or intMG or intMH or + intMAA or intMAB or intMAC or intMAD or intMAE or intMAF or intMAG or intMAH or + intMBA or intMBB or intMBC or intMBD or intMBE or intMBF or intMBG or intMBH or + intMCA or intMCB or intMCC or intMCD or intMCE or intMCF or intMCG or intMCH or + intEN or intS) + begin + + k1 = 1; + m1 = 1; + unknown1 = 0; + for(j1 = 0; j1 < C_SEL_WIDTH; j1 = j1 + 1) + begin + if(intS[j1] === 1) + k1 = k1 + m1; + else if(intS[j1] === 1'bz || intS[j1] === 1'bx) + unknown1 = 1; + m1 = m1 * 2; + end + + + if(intEN === 1'b0) + intO = #1 `allmyZs; + else if(intEN === 1'bx) + intO = #1 `allmyXs; + else if(unknown1 == 1) + intO <= #1 `allmyXs; + else if (k1 == 1) + intO <= #1 intMA; + else if (k1 == 2) + intO <= #1 intMB; + else if (k1 == 3) + intO <= #1 intMC; + else if (k1 == 4) + intO <= #1 intMD; + else if (k1 == 5) + intO <= #1 intME; + else if (k1 == 6) + intO <= #1 intMF; + else if (k1 == 7) + intO <= #1 intMG; + else if (k1 == 8) + intO <= #1 intMH; + else if (k1 == 9) + intO <= #1 intMAA; + else if (k1 == 10) + intO <= #1 intMAB; + else if (k1 == 11) + intO <= #1 intMAC; + else if (k1 == 12) + intO <= #1 intMAD; + else if (k1 == 13) + intO <= #1 intMAE; + else if (k1 == 14) + intO <= #1 intMAF; + else if (k1 == 15) + intO <= #1 intMAG; + else if (k1 == 16) + intO <= #1 intMAH; + else if (k1 == 17) + intO <= #1 intMBA; + else if (k1 == 18) + intO <= #1 intMBB; + else if (k1 == 19) + intO <= #1 intMBC; + else if (k1 == 20) + intO <= #1 intMBD; + else if (k1 == 21) + intO <= #1 intMBE; + else if (k1 == 22) + intO <= #1 intMBF; + else if (k1 == 23) + intO <= #1 intMBG; + else if (k1 == 24) + intO <= #1 intMBH; + else if (k1 == 25) + intO <= #1 intMCA; + else if (k1 == 26) + intO <= #1 intMCB; + else if (k1 == 27) + intO <= #1 intMCC; + else if (k1 == 28) + intO <= #1 intMCD; + else if (k1 == 29) + intO <= #1 intMCE; + else if (k1 == 30) + intO <= #1 intMCF; + else if (k1 == 31) + intO <= #1 intMCG; + else if (k1 == 32) + intO <= #1 intMCH; + else + intO <= #1 `allmyXs; + + end + +// Register output settings +always +begin + //------------------------------ + //-- REGISTER CLOCKED OUTPUTS -- + //------------------------------ + if (C_LATENCY === 1) + intQ = STAGE1; + else + intQ = STAGE2; + @(STAGE1 or STAGE2); +end + + + function defval; + input i; + input hassig; + input val; + begin + if(hassig == 1) + defval = i; + else + defval = val; + end + endfunction + +endmodule + +`undef c_set +`undef c_clear +`undef c_override +`undef c_no_override +`undef c_lut_based +`undef c_buft_based + +`undef allmyXs +`undef allmyZs diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/C_MUX_BUS_V6_0.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/C_MUX_BUS_V6_0.v new file mode 100644 index 0000000..9f433f5 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/C_MUX_BUS_V6_0.v @@ -0,0 +1,415 @@ +// Copyright(C) 2002 by Xilinx, Inc. All rights reserved. +// This text contains proprietary, confidential +// information of Xilinx, Inc., is distributed +// under license from Xilinx, Inc., and may be used, +// copied and/or disclosed only pursuant to the terms +// of a valid license agreement with Xilinx, Inc. This copyright +// notice must be retained as part of this text at all times. + + +/* $Id: C_MUX_BUS_V6_0.v,v 1.16 2008/09/08 20:06:04 akennedy Exp $ +-- +-- Filename - C_MUX_BUS_V6_0.v +-- Author - Xilinx +-- Creation - 4 Feb 1999 +-- +-- Description - This file contains the Verilog behavior for the Baseblocks C_MUX_BUS_V6_0 module +*/ + +`timescale 1ns/10ps + +`define c_set 0 +`define c_clear 1 +`define c_override 0 +`define c_no_override 1 +`define c_lut_based 0 +`define c_buft_based 1 + + + +`define allmyXs {C_WIDTH{1'bx}} +`define allmyZs {C_WIDTH{1'bz}} + +module C_MUX_BUS_V6_0 (MA, MB, MC, MD, ME, MF, MG, MH, + MAA, MAB, MAC, MAD, MAE, MAF, MAG, MAH, + MBA, MBB, MBC, MBD, MBE, MBF, MBG, MBH, + MCA, MCB, MCC, MCD, MCE, MCF, MCG, MCH, + S, CLK, CE, EN, ACLR, ASET, AINIT, + SCLR, SSET, SINIT, O, Q); + + parameter C_AINIT_VAL = ""; + parameter C_ENABLE_RLOCS = 1; + parameter C_HAS_ACLR = 0; + parameter C_HAS_AINIT = 0; + parameter C_HAS_ASET = 0; + parameter C_HAS_CE = 0; + parameter C_HAS_EN = 0; + parameter C_HAS_O = 0; + parameter C_HAS_Q = 1; + parameter C_HAS_SCLR = 1; + parameter C_HAS_SINIT = 0; + parameter C_HAS_SSET = 1; + parameter C_HEIGHT = 0; + parameter C_INPUTS = 2; + parameter C_LATENCY = 1; + parameter C_MUX_TYPE = `c_lut_based; + parameter C_SEL_WIDTH = 1; + parameter C_SINIT_VAL = ""; + parameter C_SYNC_ENABLE = `c_override; + parameter C_SYNC_PRIORITY = `c_clear; + parameter C_WIDTH = 2; + + // Parameters, used to drive additional register, for pipelining. + parameter PIPE_HAS_ACLR = (C_LATENCY == 1 ? C_HAS_ACLR : 1'b0); + parameter PIPE_HAS_AINIT = (C_LATENCY == 1 ? C_HAS_AINIT : 1'b0); + parameter PIPE_HAS_ASET = (C_LATENCY == 1 ? C_HAS_ASET : 1'b0); + parameter PIPE_HAS_SSET = (C_LATENCY == 1 ? C_HAS_SSET : 1'b0); + parameter PIPE_HAS_SINIT = (C_LATENCY == 1 ? C_HAS_SINIT : 1'b0); + + + input [C_WIDTH-1 : 0] MA; + input [C_WIDTH-1 : 0] MB; + input [C_WIDTH-1 : 0] MC; + input [C_WIDTH-1 : 0] MD; + input [C_WIDTH-1 : 0] ME; + input [C_WIDTH-1 : 0] MF; + input [C_WIDTH-1 : 0] MG; + input [C_WIDTH-1 : 0] MH; + input [C_WIDTH-1 : 0] MAA; + input [C_WIDTH-1 : 0] MAB; + input [C_WIDTH-1 : 0] MAC; + input [C_WIDTH-1 : 0] MAD; + input [C_WIDTH-1 : 0] MAE; + input [C_WIDTH-1 : 0] MAF; + input [C_WIDTH-1 : 0] MAG; + input [C_WIDTH-1 : 0] MAH; + input [C_WIDTH-1 : 0] MBA; + input [C_WIDTH-1 : 0] MBB; + input [C_WIDTH-1 : 0] MBC; + input [C_WIDTH-1 : 0] MBD; + input [C_WIDTH-1 : 0] MBE; + input [C_WIDTH-1 : 0] MBF; + input [C_WIDTH-1 : 0] MBG; + input [C_WIDTH-1 : 0] MBH; + input [C_WIDTH-1 : 0] MCA; + input [C_WIDTH-1 : 0] MCB; + input [C_WIDTH-1 : 0] MCC; + input [C_WIDTH-1 : 0] MCD; + input [C_WIDTH-1 : 0] MCE; + input [C_WIDTH-1 : 0] MCF; + input [C_WIDTH-1 : 0] MCG; + input [C_WIDTH-1 : 0] MCH; + input [C_SEL_WIDTH-1 : 0] S; + input CLK; + input CE; + input EN; + input ACLR; + input ASET; + input AINIT; + input SCLR; + input SSET; + input SINIT; + output [C_WIDTH-1 : 0] O; + output [C_WIDTH-1 : 0] Q; + + // Internal values to drive signals when input is missing + wire [C_WIDTH-1 : 0] intMA = MA; + wire [C_WIDTH-1 : 0] intMB = MB; + wire [C_WIDTH-1 : 0] intMC = (C_INPUTS > 2 ? MC : `allmyXs); + wire [C_WIDTH-1 : 0] intMD = (C_INPUTS > 3 ? MD : `allmyXs); + wire [C_WIDTH-1 : 0] intME = (C_INPUTS > 4 ? ME : `allmyXs); + wire [C_WIDTH-1 : 0] intMF = (C_INPUTS > 5 ? MF : `allmyXs); + wire [C_WIDTH-1 : 0] intMG = (C_INPUTS > 6 ? MG : `allmyXs); + wire [C_WIDTH-1 : 0] intMH = (C_INPUTS > 7 ? MH : `allmyXs); + wire [C_WIDTH-1 : 0] intMAA = (C_INPUTS > 8 ? MAA : `allmyXs); + wire [C_WIDTH-1 : 0] intMAB = (C_INPUTS > 9 ? MAB : `allmyXs); + wire [C_WIDTH-1 : 0] intMAC = (C_INPUTS > 10 ? MAC : `allmyXs); + wire [C_WIDTH-1 : 0] intMAD = (C_INPUTS > 11 ? MAD : `allmyXs); + wire [C_WIDTH-1 : 0] intMAE = (C_INPUTS > 12 ? MAE : `allmyXs); + wire [C_WIDTH-1 : 0] intMAF = (C_INPUTS > 13 ? MAF : `allmyXs); + wire [C_WIDTH-1 : 0] intMAG = (C_INPUTS > 14 ? MAG : `allmyXs); + wire [C_WIDTH-1 : 0] intMAH = (C_INPUTS > 15 ? MAH : `allmyXs); + wire [C_WIDTH-1 : 0] intMBA = (C_INPUTS > 16 ? MBA : `allmyXs); + wire [C_WIDTH-1 : 0] intMBB = (C_INPUTS > 17 ? MBB : `allmyXs); + wire [C_WIDTH-1 : 0] intMBC = (C_INPUTS > 18 ? MBC : `allmyXs); + wire [C_WIDTH-1 : 0] intMBD = (C_INPUTS > 19 ? MBD : `allmyXs); + wire [C_WIDTH-1 : 0] intMBE = (C_INPUTS > 20 ? MBE : `allmyXs); + wire [C_WIDTH-1 : 0] intMBF = (C_INPUTS > 21 ? MBF : `allmyXs); + wire [C_WIDTH-1 : 0] intMBG = (C_INPUTS > 22 ? MBG : `allmyXs); + wire [C_WIDTH-1 : 0] intMBH = (C_INPUTS > 23 ? MBH : `allmyXs); + wire [C_WIDTH-1 : 0] intMCA = (C_INPUTS > 24 ? MCA : `allmyXs); + wire [C_WIDTH-1 : 0] intMCB = (C_INPUTS > 25 ? MCB : `allmyXs); + wire [C_WIDTH-1 : 0] intMCC = (C_INPUTS > 26 ? MCC : `allmyXs); + wire [C_WIDTH-1 : 0] intMCD = (C_INPUTS > 27 ? MCD : `allmyXs); + wire [C_WIDTH-1 : 0] intMCE = (C_INPUTS > 28 ? MCE : `allmyXs); + wire [C_WIDTH-1 : 0] intMCF = (C_INPUTS > 29 ? MCF : `allmyXs); + wire [C_WIDTH-1 : 0] intMCG = (C_INPUTS > 30 ? MCG : `allmyXs); + wire [C_WIDTH-1 : 0] intMCH = (C_INPUTS > 31 ? MCH : `allmyXs); + + reg [C_WIDTH-1 : 0] intO; + reg [C_WIDTH-1 : 0] intQ; + + wire [C_WIDTH-1 : 0] STAGE1; + wire [C_WIDTH-1 : 0] STAGE2; + wire [C_SEL_WIDTH-1 : 0] intS = S; + wire [C_WIDTH-1 : 0] Q = (C_HAS_Q == 1 ? intQ : `allmyXs); + wire [C_WIDTH-1 : 0] O = (C_HAS_O == 1 ? intO : `allmyXs); + wire intEN; + + + assign intEN = defval(EN, C_HAS_EN, 1); + + + integer j, k, j1, k1; + integer m, unknown, m1, unknown1; + + // Register on output by default + + + C_REG_FD_V6_0 #(C_AINIT_VAL, C_ENABLE_RLOCS, PIPE_HAS_ACLR, PIPE_HAS_AINIT, PIPE_HAS_ASET, + C_HAS_CE, C_HAS_SCLR, PIPE_HAS_SINIT, PIPE_HAS_SSET, + C_SINIT_VAL, C_SYNC_ENABLE, C_SYNC_PRIORITY, C_WIDTH) + REG1 (.D(intO), .CLK(CLK), .CE(CE), .ACLR(ACLR), .ASET(ASET), + .AINIT(AINIT), .SCLR(SCLR), .SSET(SSET), .SINIT(SINIT), + .Q(STAGE1)); + + /* Just in case someone would want full register options on this register... + C_REG_FD_V6_0 #(C_AINIT_VAL, C_ENABLE_RLOCS, C_HAS_ACLR, C_HAS_AINIT, C_HAS_ASET, + C_HAS_CE, C_HAS_SCLR, C_HAS_SINIT, C_HAS_SSET, + C_SINIT_VAL, C_SYNC_ENABLE, C_SYNC_PRIORITY, C_WIDTH) + REG1 (.D(intO), .CLK(CLK), .CE(CE), .ACLR(ACLR), .ASET(ASET), + .AINIT(AINIT), .SCLR(SCLR), .SSET(SSET), .SINIT(SINIT), + .Q(STAGE1)); + */ + + C_REG_FD_V6_0 #(C_AINIT_VAL, C_ENABLE_RLOCS, C_HAS_ACLR, C_HAS_AINIT, C_HAS_ASET, + C_HAS_CE, C_HAS_SCLR, C_HAS_SINIT, C_HAS_SSET, + C_SINIT_VAL, C_SYNC_ENABLE, C_SYNC_PRIORITY, C_WIDTH) + REG2 (.D(STAGE1), .CLK(CLK), .CE(CE), .ACLR(ACLR), .ASET(ASET), + .AINIT(AINIT), .SCLR(SCLR), .SSET(SSET), .SINIT(SINIT), + .Q(STAGE2)); + + + initial + begin + + #1; + k = 1; + m = 1; + unknown = 0; + for(j = 0; j < C_SEL_WIDTH; j = j + 1) + begin + if(intS[j] === 1) + k = k + m; + else if(intS[j] === 1'bz || intS[j] === 1'bx) + unknown = 1; + m = m * 2; + end + + if(intEN === 1'b0) + intO <= #1 `allmyZs; + else if(intEN === 1'bx) + intO <= #1 `allmyXs; + else if(unknown == 1) + intO <= #1 `allmyXs; + else if (k == 1) + intO <= #1 intMA; + else if (k == 2) + intO <= #1 intMB; + else if (k == 3) + intO <= #1 intMC; + else if (k == 4) + intO <= #1 intMD; + else if (k == 5) + intO <= #1 intME; + else if (k == 6) + intO <= #1 intMF; + else if (k == 7) + intO <= #1 intMG; + else if (k == 8) + intO <= #1 intMH; + else if (k == 9) + intO <= #1 intMAA; + else if (k == 10) + intO <= #1 intMAB; + else if (k == 11) + intO <= #1 intMAC; + else if (k == 12) + intO <= #1 intMAD; + else if (k == 13) + intO <= #1 intMAE; + else if (k == 14) + intO <= #1 intMAF; + else if (k == 15) + intO <= #1 intMAG; + else if (k == 16) + intO <= #1 intMAH; + else if (k == 17) + intO <= #1 intMBA; + else if (k == 18) + intO <= #1 intMBB; + else if (k == 19) + intO <= #1 intMBC; + else if (k == 20) + intO <= #1 intMBD; + else if (k == 21) + intO <= #1 intMBE; + else if (k == 22) + intO <= #1 intMBF; + else if (k == 23) + intO <= #1 intMBG; + else if (k == 24) + intO <= #1 intMBH; + else if (k == 25) + intO <= #1 intMCA; + else if (k == 26) + intO <= #1 intMCB; + else if (k == 27) + intO <= #1 intMCC; + else if (k == 28) + intO <= #1 intMCD; + else if (k == 29) + intO <= #1 intMCE; + else if (k == 30) + intO <= #1 intMCF; + else if (k == 31) + intO <= #1 intMCG; + else if (k == 32) + intO <= #1 intMCH; + else + intO <= #1 `allmyXs; + + end + + always@(intMA or intMB or intMC or intMD or intME or intMF or intMG or intMH or + intMAA or intMAB or intMAC or intMAD or intMAE or intMAF or intMAG or intMAH or + intMBA or intMBB or intMBC or intMBD or intMBE or intMBF or intMBG or intMBH or + intMCA or intMCB or intMCC or intMCD or intMCE or intMCF or intMCG or intMCH or + intEN or intS) + begin + + k1 = 1; + m1 = 1; + unknown1 = 0; + for(j1 = 0; j1 < C_SEL_WIDTH; j1 = j1 + 1) + begin + if(intS[j1] === 1) + k1 = k1 + m1; + else if(intS[j1] === 1'bz || intS[j1] === 1'bx) + unknown1 = 1; + m1 = m1 * 2; + end + + + if(intEN === 1'b0) + intO = #1 `allmyZs; + else if(intEN === 1'bx) + intO = #1 `allmyXs; + else if(unknown1 == 1) + intO <= #1 `allmyXs; + else if (k1 == 1) + intO <= #1 intMA; + else if (k1 == 2) + intO <= #1 intMB; + else if (k1 == 3) + intO <= #1 intMC; + else if (k1 == 4) + intO <= #1 intMD; + else if (k1 == 5) + intO <= #1 intME; + else if (k1 == 6) + intO <= #1 intMF; + else if (k1 == 7) + intO <= #1 intMG; + else if (k1 == 8) + intO <= #1 intMH; + else if (k1 == 9) + intO <= #1 intMAA; + else if (k1 == 10) + intO <= #1 intMAB; + else if (k1 == 11) + intO <= #1 intMAC; + else if (k1 == 12) + intO <= #1 intMAD; + else if (k1 == 13) + intO <= #1 intMAE; + else if (k1 == 14) + intO <= #1 intMAF; + else if (k1 == 15) + intO <= #1 intMAG; + else if (k1 == 16) + intO <= #1 intMAH; + else if (k1 == 17) + intO <= #1 intMBA; + else if (k1 == 18) + intO <= #1 intMBB; + else if (k1 == 19) + intO <= #1 intMBC; + else if (k1 == 20) + intO <= #1 intMBD; + else if (k1 == 21) + intO <= #1 intMBE; + else if (k1 == 22) + intO <= #1 intMBF; + else if (k1 == 23) + intO <= #1 intMBG; + else if (k1 == 24) + intO <= #1 intMBH; + else if (k1 == 25) + intO <= #1 intMCA; + else if (k1 == 26) + intO <= #1 intMCB; + else if (k1 == 27) + intO <= #1 intMCC; + else if (k1 == 28) + intO <= #1 intMCD; + else if (k1 == 29) + intO <= #1 intMCE; + else if (k1 == 30) + intO <= #1 intMCF; + else if (k1 == 31) + intO <= #1 intMCG; + else if (k1 == 32) + intO <= #1 intMCH; + else + intO <= #1 `allmyXs; + + end + +// Register output settings +always +begin + //------------------------------ + //-- REGISTER CLOCKED OUTPUTS -- + //------------------------------ + if (C_LATENCY === 1) + intQ = STAGE1; + else + intQ = STAGE2; + @(STAGE1 or STAGE2); +end + + + function defval; + input i; + input hassig; + input val; + begin + if(hassig == 1) + defval = i; + else + defval = val; + end + endfunction + +endmodule + +`undef c_set +`undef c_clear +`undef c_override +`undef c_no_override +`undef c_lut_based +`undef c_buft_based + +`undef allmyXs +`undef allmyZs diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/C_MUX_BUS_V7_0.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/C_MUX_BUS_V7_0.v new file mode 100644 index 0000000..4e60a65 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/C_MUX_BUS_V7_0.v @@ -0,0 +1,444 @@ +// Copyright(C) 2003 by Xilinx, Inc. All rights reserved. +// This text/file contains proprietary, confidential +// information of Xilinx, Inc., is distributed under license +// from Xilinx, Inc., and may be used, copied and/or +// disclosed only pursuant to the terms of a valid license +// agreement with Xilinx, Inc. Xilinx hereby grants you +// a license to use this text/file solely for design, simulation, +// implementation and creation of design files limited +// to Xilinx devices or technologies. Use with non-Xilinx +// devices or technologies is expressly prohibited and +// immediately terminates your license unless covered by +// a separate agreement. +// +// Xilinx is providing this design, code, or information +// "as is" solely for use in developing programs and +// solutions for Xilinx devices. By providing this design, +// code, or information as one possible implementation of +// this feature, application or standard, Xilinx is making no +// representation that this implementation is free from any +// claims of infringement. You are responsible for +// obtaining any rights you may require for your implementation. +// Xilinx expressly disclaims any warranty whatsoever with +// respect to the adequacy of the implementation, including +// but not limited to any warranties or representations that this +// implementation is free from claims of infringement, implied +// warranties of merchantability or fitness for a particular +// purpose. +// +// Xilinx products are not intended for use in life support +// appliances, devices, or systems. Use in such applications are +// expressly prohibited. +// +// This copyright and support notice must be retained as part +// of this text at all times. (c) Copyright 1995-2003 Xilinx, Inc. +// All rights reserved. + + + +/* $Id: C_MUX_BUS_V7_0.v,v 1.13 2008/09/08 20:06:13 akennedy Exp $ +-- +-- Filename - C_MUX_BUS_V7_0.v +-- Author - Xilinx +-- Creation - 4 Feb 1999 +-- +-- Description - This file contains the Verilog behavior for the Baseblocks C_MUX_BUS_V7_0 module +*/ + +`timescale 1ns/10ps + +`define c_set 0 +`define c_clear 1 +`define c_override 0 +`define c_no_override 1 +`define c_lut_based 0 +`define c_buft_based 1 + + + +`define allmyXs {C_WIDTH{1'bx}} +`define allmyZs {C_WIDTH{1'bz}} + +module C_MUX_BUS_V7_0 (MA, MB, MC, MD, ME, MF, MG, MH, + MAA, MAB, MAC, MAD, MAE, MAF, MAG, MAH, + MBA, MBB, MBC, MBD, MBE, MBF, MBG, MBH, + MCA, MCB, MCC, MCD, MCE, MCF, MCG, MCH, + S, CLK, CE, EN, ACLR, ASET, AINIT, + SCLR, SSET, SINIT, O, Q); + + parameter C_AINIT_VAL = ""; + parameter C_ENABLE_RLOCS = 1; + parameter C_HAS_ACLR = 0; + parameter C_HAS_AINIT = 0; + parameter C_HAS_ASET = 0; + parameter C_HAS_CE = 0; + parameter C_HAS_EN = 0; + parameter C_HAS_O = 0; + parameter C_HAS_Q = 1; + parameter C_HAS_SCLR = 1; + parameter C_HAS_SINIT = 0; + parameter C_HAS_SSET = 1; + parameter C_HEIGHT = 0; + parameter C_INPUTS = 2; + parameter C_LATENCY = 1; + parameter C_MUX_TYPE = `c_lut_based; + parameter C_SEL_WIDTH = 1; + parameter C_SINIT_VAL = ""; + parameter C_SYNC_ENABLE = `c_override; + parameter C_SYNC_PRIORITY = `c_clear; + parameter C_WIDTH = 2; + + // Parameters, used to drive additional register, for pipelining. + parameter PIPE_HAS_ACLR = (C_LATENCY == 1 ? C_HAS_ACLR : 1'b0); + parameter PIPE_HAS_AINIT = (C_LATENCY == 1 ? C_HAS_AINIT : 1'b0); + parameter PIPE_HAS_ASET = (C_LATENCY == 1 ? C_HAS_ASET : 1'b0); + parameter PIPE_HAS_SSET = (C_LATENCY == 1 ? C_HAS_SSET : 1'b0); + parameter PIPE_HAS_SINIT = (C_LATENCY == 1 ? C_HAS_SINIT : 1'b0); + + + input [C_WIDTH-1 : 0] MA; + input [C_WIDTH-1 : 0] MB; + input [C_WIDTH-1 : 0] MC; + input [C_WIDTH-1 : 0] MD; + input [C_WIDTH-1 : 0] ME; + input [C_WIDTH-1 : 0] MF; + input [C_WIDTH-1 : 0] MG; + input [C_WIDTH-1 : 0] MH; + input [C_WIDTH-1 : 0] MAA; + input [C_WIDTH-1 : 0] MAB; + input [C_WIDTH-1 : 0] MAC; + input [C_WIDTH-1 : 0] MAD; + input [C_WIDTH-1 : 0] MAE; + input [C_WIDTH-1 : 0] MAF; + input [C_WIDTH-1 : 0] MAG; + input [C_WIDTH-1 : 0] MAH; + input [C_WIDTH-1 : 0] MBA; + input [C_WIDTH-1 : 0] MBB; + input [C_WIDTH-1 : 0] MBC; + input [C_WIDTH-1 : 0] MBD; + input [C_WIDTH-1 : 0] MBE; + input [C_WIDTH-1 : 0] MBF; + input [C_WIDTH-1 : 0] MBG; + input [C_WIDTH-1 : 0] MBH; + input [C_WIDTH-1 : 0] MCA; + input [C_WIDTH-1 : 0] MCB; + input [C_WIDTH-1 : 0] MCC; + input [C_WIDTH-1 : 0] MCD; + input [C_WIDTH-1 : 0] MCE; + input [C_WIDTH-1 : 0] MCF; + input [C_WIDTH-1 : 0] MCG; + input [C_WIDTH-1 : 0] MCH; + input [C_SEL_WIDTH-1 : 0] S; + input CLK; + input CE; + input EN; + input ACLR; + input ASET; + input AINIT; + input SCLR; + input SSET; + input SINIT; + output [C_WIDTH-1 : 0] O; + output [C_WIDTH-1 : 0] Q; + + // Internal values to drive signals when input is missing + wire [C_WIDTH-1 : 0] intMA = MA; + wire [C_WIDTH-1 : 0] intMB = MB; + wire [C_WIDTH-1 : 0] intMC = (C_INPUTS > 2 ? MC : `allmyXs); + wire [C_WIDTH-1 : 0] intMD = (C_INPUTS > 3 ? MD : `allmyXs); + wire [C_WIDTH-1 : 0] intME = (C_INPUTS > 4 ? ME : `allmyXs); + wire [C_WIDTH-1 : 0] intMF = (C_INPUTS > 5 ? MF : `allmyXs); + wire [C_WIDTH-1 : 0] intMG = (C_INPUTS > 6 ? MG : `allmyXs); + wire [C_WIDTH-1 : 0] intMH = (C_INPUTS > 7 ? MH : `allmyXs); + wire [C_WIDTH-1 : 0] intMAA = (C_INPUTS > 8 ? MAA : `allmyXs); + wire [C_WIDTH-1 : 0] intMAB = (C_INPUTS > 9 ? MAB : `allmyXs); + wire [C_WIDTH-1 : 0] intMAC = (C_INPUTS > 10 ? MAC : `allmyXs); + wire [C_WIDTH-1 : 0] intMAD = (C_INPUTS > 11 ? MAD : `allmyXs); + wire [C_WIDTH-1 : 0] intMAE = (C_INPUTS > 12 ? MAE : `allmyXs); + wire [C_WIDTH-1 : 0] intMAF = (C_INPUTS > 13 ? MAF : `allmyXs); + wire [C_WIDTH-1 : 0] intMAG = (C_INPUTS > 14 ? MAG : `allmyXs); + wire [C_WIDTH-1 : 0] intMAH = (C_INPUTS > 15 ? MAH : `allmyXs); + wire [C_WIDTH-1 : 0] intMBA = (C_INPUTS > 16 ? MBA : `allmyXs); + wire [C_WIDTH-1 : 0] intMBB = (C_INPUTS > 17 ? MBB : `allmyXs); + wire [C_WIDTH-1 : 0] intMBC = (C_INPUTS > 18 ? MBC : `allmyXs); + wire [C_WIDTH-1 : 0] intMBD = (C_INPUTS > 19 ? MBD : `allmyXs); + wire [C_WIDTH-1 : 0] intMBE = (C_INPUTS > 20 ? MBE : `allmyXs); + wire [C_WIDTH-1 : 0] intMBF = (C_INPUTS > 21 ? MBF : `allmyXs); + wire [C_WIDTH-1 : 0] intMBG = (C_INPUTS > 22 ? MBG : `allmyXs); + wire [C_WIDTH-1 : 0] intMBH = (C_INPUTS > 23 ? MBH : `allmyXs); + wire [C_WIDTH-1 : 0] intMCA = (C_INPUTS > 24 ? MCA : `allmyXs); + wire [C_WIDTH-1 : 0] intMCB = (C_INPUTS > 25 ? MCB : `allmyXs); + wire [C_WIDTH-1 : 0] intMCC = (C_INPUTS > 26 ? MCC : `allmyXs); + wire [C_WIDTH-1 : 0] intMCD = (C_INPUTS > 27 ? MCD : `allmyXs); + wire [C_WIDTH-1 : 0] intMCE = (C_INPUTS > 28 ? MCE : `allmyXs); + wire [C_WIDTH-1 : 0] intMCF = (C_INPUTS > 29 ? MCF : `allmyXs); + wire [C_WIDTH-1 : 0] intMCG = (C_INPUTS > 30 ? MCG : `allmyXs); + wire [C_WIDTH-1 : 0] intMCH = (C_INPUTS > 31 ? MCH : `allmyXs); + + reg [C_WIDTH-1 : 0] intO; + reg [C_WIDTH-1 : 0] intQ; + + wire [C_WIDTH-1 : 0] STAGE1; + wire [C_WIDTH-1 : 0] STAGE2; + wire [C_SEL_WIDTH-1 : 0] intS = S; + wire [C_WIDTH-1 : 0] Q = (C_HAS_Q == 1 ? intQ : `allmyXs); + wire [C_WIDTH-1 : 0] O = (C_HAS_O == 1 ? intO : `allmyXs); + wire intEN; + + + assign intEN = defval(EN, C_HAS_EN, 1); + + + integer j, k, j1, k1; + integer m, unknown, m1, unknown1; + + // Register on output by default + + + C_REG_FD_V7_0 #(C_AINIT_VAL, C_ENABLE_RLOCS, PIPE_HAS_ACLR, PIPE_HAS_AINIT, PIPE_HAS_ASET, + C_HAS_CE, C_HAS_SCLR, PIPE_HAS_SINIT, PIPE_HAS_SSET, + C_SINIT_VAL, C_SYNC_ENABLE, C_SYNC_PRIORITY, C_WIDTH) + REG1 (.D(intO), .CLK(CLK), .CE(CE), .ACLR(ACLR), .ASET(ASET), + .AINIT(AINIT), .SCLR(SCLR), .SSET(SSET), .SINIT(SINIT), + .Q(STAGE1)); + + /* Just in case someone would want full register options on this register... + C_REG_FD_V7_0 #(C_AINIT_VAL, C_ENABLE_RLOCS, C_HAS_ACLR, C_HAS_AINIT, C_HAS_ASET, + C_HAS_CE, C_HAS_SCLR, C_HAS_SINIT, C_HAS_SSET, + C_SINIT_VAL, C_SYNC_ENABLE, C_SYNC_PRIORITY, C_WIDTH) + REG1 (.D(intO), .CLK(CLK), .CE(CE), .ACLR(ACLR), .ASET(ASET), + .AINIT(AINIT), .SCLR(SCLR), .SSET(SSET), .SINIT(SINIT), + .Q(STAGE1)); + */ + + C_REG_FD_V7_0 #(C_AINIT_VAL, C_ENABLE_RLOCS, C_HAS_ACLR, C_HAS_AINIT, C_HAS_ASET, + C_HAS_CE, C_HAS_SCLR, C_HAS_SINIT, C_HAS_SSET, + C_SINIT_VAL, C_SYNC_ENABLE, C_SYNC_PRIORITY, C_WIDTH) + REG2 (.D(STAGE1), .CLK(CLK), .CE(CE), .ACLR(ACLR), .ASET(ASET), + .AINIT(AINIT), .SCLR(SCLR), .SSET(SSET), .SINIT(SINIT), + .Q(STAGE2)); + + + initial + begin + + #1; + k = 1; + m = 1; + unknown = 0; + for(j = 0; j < C_SEL_WIDTH; j = j + 1) + begin + if(intS[j] === 1) + k = k + m; + else if(intS[j] === 1'bz || intS[j] === 1'bx) + unknown = 1; + m = m * 2; + end + + if(intEN === 1'b0) + intO <= #1 `allmyZs; + else if(intEN === 1'bx) + intO <= #1 `allmyXs; + else if(unknown == 1) + intO <= #1 `allmyXs; + else if (k == 1) + intO <= #1 intMA; + else if (k == 2) + intO <= #1 intMB; + else if (k == 3) + intO <= #1 intMC; + else if (k == 4) + intO <= #1 intMD; + else if (k == 5) + intO <= #1 intME; + else if (k == 6) + intO <= #1 intMF; + else if (k == 7) + intO <= #1 intMG; + else if (k == 8) + intO <= #1 intMH; + else if (k == 9) + intO <= #1 intMAA; + else if (k == 10) + intO <= #1 intMAB; + else if (k == 11) + intO <= #1 intMAC; + else if (k == 12) + intO <= #1 intMAD; + else if (k == 13) + intO <= #1 intMAE; + else if (k == 14) + intO <= #1 intMAF; + else if (k == 15) + intO <= #1 intMAG; + else if (k == 16) + intO <= #1 intMAH; + else if (k == 17) + intO <= #1 intMBA; + else if (k == 18) + intO <= #1 intMBB; + else if (k == 19) + intO <= #1 intMBC; + else if (k == 20) + intO <= #1 intMBD; + else if (k == 21) + intO <= #1 intMBE; + else if (k == 22) + intO <= #1 intMBF; + else if (k == 23) + intO <= #1 intMBG; + else if (k == 24) + intO <= #1 intMBH; + else if (k == 25) + intO <= #1 intMCA; + else if (k == 26) + intO <= #1 intMCB; + else if (k == 27) + intO <= #1 intMCC; + else if (k == 28) + intO <= #1 intMCD; + else if (k == 29) + intO <= #1 intMCE; + else if (k == 30) + intO <= #1 intMCF; + else if (k == 31) + intO <= #1 intMCG; + else if (k == 32) + intO <= #1 intMCH; + else + intO <= #1 `allmyXs; + + end + + always@(intMA or intMB or intMC or intMD or intME or intMF or intMG or intMH or + intMAA or intMAB or intMAC or intMAD or intMAE or intMAF or intMAG or intMAH or + intMBA or intMBB or intMBC or intMBD or intMBE or intMBF or intMBG or intMBH or + intMCA or intMCB or intMCC or intMCD or intMCE or intMCF or intMCG or intMCH or + intEN or intS) + begin + + k1 = 1; + m1 = 1; + unknown1 = 0; + for(j1 = 0; j1 < C_SEL_WIDTH; j1 = j1 + 1) + begin + if(intS[j1] === 1) + k1 = k1 + m1; + else if(intS[j1] === 1'bz || intS[j1] === 1'bx) + unknown1 = 1; + m1 = m1 * 2; + end + + + if(intEN === 1'b0) + intO <= #1 `allmyZs; + else if(intEN === 1'bx) + intO <= #1 `allmyXs; + else if(unknown1 == 1) + intO <= #1 `allmyXs; + else if (k1 == 1) + intO <= #1 intMA; + else if (k1 == 2) + intO <= #1 intMB; + else if (k1 == 3) + intO <= #1 intMC; + else if (k1 == 4) + intO <= #1 intMD; + else if (k1 == 5) + intO <= #1 intME; + else if (k1 == 6) + intO <= #1 intMF; + else if (k1 == 7) + intO <= #1 intMG; + else if (k1 == 8) + intO <= #1 intMH; + else if (k1 == 9) + intO <= #1 intMAA; + else if (k1 == 10) + intO <= #1 intMAB; + else if (k1 == 11) + intO <= #1 intMAC; + else if (k1 == 12) + intO <= #1 intMAD; + else if (k1 == 13) + intO <= #1 intMAE; + else if (k1 == 14) + intO <= #1 intMAF; + else if (k1 == 15) + intO <= #1 intMAG; + else if (k1 == 16) + intO <= #1 intMAH; + else if (k1 == 17) + intO <= #1 intMBA; + else if (k1 == 18) + intO <= #1 intMBB; + else if (k1 == 19) + intO <= #1 intMBC; + else if (k1 == 20) + intO <= #1 intMBD; + else if (k1 == 21) + intO <= #1 intMBE; + else if (k1 == 22) + intO <= #1 intMBF; + else if (k1 == 23) + intO <= #1 intMBG; + else if (k1 == 24) + intO <= #1 intMBH; + else if (k1 == 25) + intO <= #1 intMCA; + else if (k1 == 26) + intO <= #1 intMCB; + else if (k1 == 27) + intO <= #1 intMCC; + else if (k1 == 28) + intO <= #1 intMCD; + else if (k1 == 29) + intO <= #1 intMCE; + else if (k1 == 30) + intO <= #1 intMCF; + else if (k1 == 31) + intO <= #1 intMCG; + else if (k1 == 32) + intO <= #1 intMCH; + else + intO <= #1 `allmyXs; + + end + +// Register output settings +always +begin + //------------------------------ + //-- REGISTER CLOCKED OUTPUTS -- + //------------------------------ + if (C_LATENCY === 1) + intQ = STAGE1; + else + intQ = STAGE2; + @(STAGE1 or STAGE2); +end + + + function defval; + input i; + input hassig; + input val; + begin + if(hassig == 1) + defval = i; + else + defval = val; + end + endfunction + +endmodule + +`undef c_set +`undef c_clear +`undef c_override +`undef c_no_override +`undef c_lut_based +`undef c_buft_based + +`undef allmyXs +`undef allmyZs diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/C_MUX_SLICE_BUFE_V4_0.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/C_MUX_SLICE_BUFE_V4_0.v new file mode 100644 index 0000000..4eeec68 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/C_MUX_SLICE_BUFE_V4_0.v @@ -0,0 +1,51 @@ +/* $Id: C_MUX_SLICE_BUFE_V4_0.v,v 1.11 2008/09/08 20:05:46 akennedy Exp $ +-- +-- Filename - C_MUX_SLICE_BUFE_V4_0.v +-- Author - Xilinx +-- Creation - 4 Feb 1999 +-- +-- Description - This file contains the Verilog behavior for the Baseblocks C_MUX_SLICE_BUFE_V4_0 module +*/ + + +`define allXs {C_WIDTH{1'bx}} +`define allZs {C_WIDTH{1'bz}} + +module C_MUX_SLICE_BUFE_V4_0 (I, OE, O); + + parameter C_WIDTH = 16; /* Width of the single input */ + + input [C_WIDTH-1 : 0] I; + input OE; + output [C_WIDTH-1 : 0] O; + + reg [C_WIDTH-1 : 0] intO; + + wire [C_WIDTH-1 : 0] #1 O = intO; + + initial + begin + + if (OE == 1) + intO = I; + else if (OE == 0) + intO = `allZs; + else + intO = `allXs; + end + + always@(I or OE) + begin + if (OE == 1) + intO <= I; + else if (OE == 0) + intO <= `allZs; + else + intO <= `allXs; + end + +endmodule + +`undef allXs +`undef allZs + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/C_MUX_SLICE_BUFE_V5_0.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/C_MUX_SLICE_BUFE_V5_0.v new file mode 100644 index 0000000..0b52acd --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/C_MUX_SLICE_BUFE_V5_0.v @@ -0,0 +1,51 @@ +/* $Id: C_MUX_SLICE_BUFE_V5_0.v,v 1.17 2008/09/08 20:05:56 akennedy Exp $ +-- +-- Filename - C_MUX_SLICE_BUFE_V5_0.v +-- Author - Xilinx +-- Creation - 4 Feb 1999 +-- +-- Description - This file contains the Verilog behavior for the Baseblocks C_MUX_SLICE_BUFE_V5_0 module +*/ + +`timescale 1ns/10ps + +`define allXs {C_WIDTH{1'bx}} +`define allZs {C_WIDTH{1'bz}} + +module C_MUX_SLICE_BUFE_V5_0 (I, OE, O); + + parameter C_WIDTH = 16; /* Width of the single input */ + + input [C_WIDTH-1 : 0] I; + input OE; + output [C_WIDTH-1 : 0] O; + + reg [C_WIDTH-1 : 0] intO; + + wire [C_WIDTH-1 : 0] #1 O = intO; + + initial + begin + + if (OE == 1) + intO = I; + else if (OE == 0) + intO = `allZs; + else + intO = `allXs; + end + + always@(I or OE) + begin + if (OE == 1) + intO <= I; + else if (OE == 0) + intO <= `allZs; + else + intO <= `allXs; + end + +endmodule + +`undef allXs +`undef allZs diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/C_MUX_SLICE_BUFE_V6_0.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/C_MUX_SLICE_BUFE_V6_0.v new file mode 100644 index 0000000..5ab1b12 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/C_MUX_SLICE_BUFE_V6_0.v @@ -0,0 +1,60 @@ +// Copyright(C) 2002 by Xilinx, Inc. All rights reserved. +// This text contains proprietary, confidential +// information of Xilinx, Inc., is distributed +// under license from Xilinx, Inc., and may be used, +// copied and/or disclosed only pursuant to the terms +// of a valid license agreement with Xilinx, Inc. This copyright +// notice must be retained as part of this text at all times. + + +/* $Id: C_MUX_SLICE_BUFE_V6_0.v,v 1.16 2008/09/08 20:06:04 akennedy Exp $ +-- +-- Filename - C_MUX_SLICE_BUFE_V6_0.v +-- Author - Xilinx +-- Creation - 4 Feb 1999 +-- +-- Description - This file contains the Verilog behavior for the Baseblocks C_MUX_SLICE_BUFE_V6_0 module +*/ + +`timescale 1ns/10ps + +`define allXs {C_WIDTH{1'bx}} +`define allZs {C_WIDTH{1'bz}} + +module C_MUX_SLICE_BUFE_V6_0 (I, OE, O); + + parameter C_WIDTH = 16; /* Width of the single input */ + + input [C_WIDTH-1 : 0] I; + input OE; + output [C_WIDTH-1 : 0] O; + + reg [C_WIDTH-1 : 0] intO; + + wire [C_WIDTH-1 : 0] #1 O = intO; + + initial + begin + + if (OE == 1) + intO = I; + else if (OE == 0) + intO = `allZs; + else + intO = `allXs; + end + + always@(I or OE) + begin + if (OE == 1) + intO <= I; + else if (OE == 0) + intO <= `allZs; + else + intO <= `allXs; + end + +endmodule + +`undef allXs +`undef allZs diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/C_MUX_SLICE_BUFE_V7_0.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/C_MUX_SLICE_BUFE_V7_0.v new file mode 100644 index 0000000..fc283fb --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/C_MUX_SLICE_BUFE_V7_0.v @@ -0,0 +1,89 @@ +// Copyright(C) 2003 by Xilinx, Inc. All rights reserved. +// This text/file contains proprietary, confidential +// information of Xilinx, Inc., is distributed under license +// from Xilinx, Inc., and may be used, copied and/or +// disclosed only pursuant to the terms of a valid license +// agreement with Xilinx, Inc. Xilinx hereby grants you +// a license to use this text/file solely for design, simulation, +// implementation and creation of design files limited +// to Xilinx devices or technologies. Use with non-Xilinx +// devices or technologies is expressly prohibited and +// immediately terminates your license unless covered by +// a separate agreement. +// +// Xilinx is providing this design, code, or information +// "as is" solely for use in developing programs and +// solutions for Xilinx devices. By providing this design, +// code, or information as one possible implementation of +// this feature, application or standard, Xilinx is making no +// representation that this implementation is free from any +// claims of infringement. You are responsible for +// obtaining any rights you may require for your implementation. +// Xilinx expressly disclaims any warranty whatsoever with +// respect to the adequacy of the implementation, including +// but not limited to any warranties or representations that this +// implementation is free from claims of infringement, implied +// warranties of merchantability or fitness for a particular +// purpose. +// +// Xilinx products are not intended for use in life support +// appliances, devices, or systems. Use in such applications are +// expressly prohibited. +// +// This copyright and support notice must be retained as part +// of this text at all times. (c) Copyright 1995-2003 Xilinx, Inc. +// All rights reserved. + + + +/* $Id: C_MUX_SLICE_BUFE_V7_0.v,v 1.13 2008/09/08 20:06:13 akennedy Exp $ +-- +-- Filename - C_MUX_SLICE_BUFE_V7_0.v +-- Author - Xilinx +-- Creation - 4 Feb 1999 +-- +-- Description - This file contains the Verilog behavior for the Baseblocks C_MUX_SLICE_BUFE_V7_0 module +*/ + +`timescale 1ns/10ps + +`define allXs {C_WIDTH{1'bx}} +`define allZs {C_WIDTH{1'bz}} + +module C_MUX_SLICE_BUFE_V7_0 (I, OE, O); + + parameter C_WIDTH = 16; /* Width of the single input */ + + input [C_WIDTH-1 : 0] I; + input OE; + output [C_WIDTH-1 : 0] O; + + reg [C_WIDTH-1 : 0] intO; + + wire [C_WIDTH-1 : 0] #1 O = intO; + + initial + begin + + if (OE == 1) + intO = I; + else if (OE == 0) + intO = `allZs; + else + intO = `allXs; + end + + always@(I or OE) + begin + if (OE == 1) + intO <= I; + else if (OE == 0) + intO <= `allZs; + else + intO <= `allXs; + end + +endmodule + +`undef allXs +`undef allZs diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/C_MUX_SLICE_BUFT_V4_0.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/C_MUX_SLICE_BUFT_V4_0.v new file mode 100644 index 0000000..817d216 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/C_MUX_SLICE_BUFT_V4_0.v @@ -0,0 +1,51 @@ +/* $Id: C_MUX_SLICE_BUFT_V4_0.v,v 1.11 2008/09/08 20:05:46 akennedy Exp $ +-- +-- Filename - C_MUX_SLICE_BUFT_V4_0.v +-- Author - Xilinx +-- Creation - 4 Feb 1999 +-- +-- Description - This file contains the Verilog behavior for the Baseblocks C_MUX_SLICE_BUFT_V4_0 module +*/ + + +`define allXs {C_WIDTH{1'bx}} +`define allZs {C_WIDTH{1'bz}} + +module C_MUX_SLICE_BUFT_V4_0 (I, T, O); + + parameter C_WIDTH = 16; /* Width of the single input */ + + input [C_WIDTH-1 : 0] I; + input T; + output [C_WIDTH-1 : 0] O; + + reg [C_WIDTH-1 : 0] intO; + + wire [C_WIDTH-1 : 0] #1 O = intO; + + initial + begin + + if (T == 0) + intO = I; + else if (T == 1) + intO = `allZs; + else + intO = `allXs; + end + + always@(I or T) + begin + if (T == 0) + intO <= I; + else if (T == 1) + intO <= `allZs; + else + intO <= `allXs; + end + +endmodule + +`undef allXs +`undef allZs + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/C_MUX_SLICE_BUFT_V5_0.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/C_MUX_SLICE_BUFT_V5_0.v new file mode 100644 index 0000000..fa0f0ac --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/C_MUX_SLICE_BUFT_V5_0.v @@ -0,0 +1,52 @@ +/* $Id: C_MUX_SLICE_BUFT_V5_0.v,v 1.17 2008/09/08 20:05:56 akennedy Exp $ +-- +-- Filename - C_MUX_SLICE_BUFT_V5_0.v +-- Author - Xilinx +-- Creation - 4 Feb 1999 +-- +-- Description - This file contains the Verilog behavior for the Baseblocks C_MUX_SLICE_BUFT_V5_0 module +*/ + +`timescale 1ns/10ps + +`define allXs {C_WIDTH{1'bx}} +`define allZs {C_WIDTH{1'bz}} + +module C_MUX_SLICE_BUFT_V5_0 (I, T, O); + + parameter C_WIDTH = 16; /* Width of the single input */ + + input [C_WIDTH-1 : 0] I; + input T; + output [C_WIDTH-1 : 0] O; + + reg [C_WIDTH-1 : 0] intO; + + wire [C_WIDTH-1 : 0] #1 O = intO; + + initial + begin + + if (T == 0) + intO = I; + else if (T == 1) + intO = `allZs; + else + intO = `allXs; + end + + always@(I or T) + begin + if (T == 0) + intO <= I; + else if (T == 1) + intO <= `allZs; + else + intO <= `allXs; + end + +endmodule + +`undef allXs +`undef allZs + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/C_MUX_SLICE_BUFT_V6_0.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/C_MUX_SLICE_BUFT_V6_0.v new file mode 100644 index 0000000..3d516b2 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/C_MUX_SLICE_BUFT_V6_0.v @@ -0,0 +1,61 @@ +// Copyright(C) 2002 by Xilinx, Inc. All rights reserved. +// This text contains proprietary, confidential +// information of Xilinx, Inc., is distributed +// under license from Xilinx, Inc., and may be used, +// copied and/or disclosed only pursuant to the terms +// of a valid license agreement with Xilinx, Inc. This copyright +// notice must be retained as part of this text at all times. + + +/* $Id: C_MUX_SLICE_BUFT_V6_0.v,v 1.16 2008/09/08 20:06:04 akennedy Exp $ +-- +-- Filename - C_MUX_SLICE_BUFT_V6_0.v +-- Author - Xilinx +-- Creation - 4 Feb 1999 +-- +-- Description - This file contains the Verilog behavior for the Baseblocks C_MUX_SLICE_BUFT_V6_0 module +*/ + +`timescale 1ns/10ps + +`define allXs {C_WIDTH{1'bx}} +`define allZs {C_WIDTH{1'bz}} + +module C_MUX_SLICE_BUFT_V6_0 (I, T, O); + + parameter C_WIDTH = 16; /* Width of the single input */ + + input [C_WIDTH-1 : 0] I; + input T; + output [C_WIDTH-1 : 0] O; + + reg [C_WIDTH-1 : 0] intO; + + wire [C_WIDTH-1 : 0] #1 O = intO; + + initial + begin + + if (T == 0) + intO = I; + else if (T == 1) + intO = `allZs; + else + intO = `allXs; + end + + always@(I or T) + begin + if (T == 0) + intO <= I; + else if (T == 1) + intO <= `allZs; + else + intO <= `allXs; + end + +endmodule + +`undef allXs +`undef allZs + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/C_MUX_SLICE_BUFT_V7_0.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/C_MUX_SLICE_BUFT_V7_0.v new file mode 100644 index 0000000..2168af4 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/C_MUX_SLICE_BUFT_V7_0.v @@ -0,0 +1,90 @@ +// Copyright(C) 2003 by Xilinx, Inc. All rights reserved. +// This text/file contains proprietary, confidential +// information of Xilinx, Inc., is distributed under license +// from Xilinx, Inc., and may be used, copied and/or +// disclosed only pursuant to the terms of a valid license +// agreement with Xilinx, Inc. Xilinx hereby grants you +// a license to use this text/file solely for design, simulation, +// implementation and creation of design files limited +// to Xilinx devices or technologies. Use with non-Xilinx +// devices or technologies is expressly prohibited and +// immediately terminates your license unless covered by +// a separate agreement. +// +// Xilinx is providing this design, code, or information +// "as is" solely for use in developing programs and +// solutions for Xilinx devices. By providing this design, +// code, or information as one possible implementation of +// this feature, application or standard, Xilinx is making no +// representation that this implementation is free from any +// claims of infringement. You are responsible for +// obtaining any rights you may require for your implementation. +// Xilinx expressly disclaims any warranty whatsoever with +// respect to the adequacy of the implementation, including +// but not limited to any warranties or representations that this +// implementation is free from claims of infringement, implied +// warranties of merchantability or fitness for a particular +// purpose. +// +// Xilinx products are not intended for use in life support +// appliances, devices, or systems. Use in such applications are +// expressly prohibited. +// +// This copyright and support notice must be retained as part +// of this text at all times. (c) Copyright 1995-2003 Xilinx, Inc. +// All rights reserved. + + + +/* $Id: C_MUX_SLICE_BUFT_V7_0.v,v 1.13 2008/09/08 20:06:13 akennedy Exp $ +-- +-- Filename - C_MUX_SLICE_BUFT_V7_0.v +-- Author - Xilinx +-- Creation - 4 Feb 1999 +-- +-- Description - This file contains the Verilog behavior for the Baseblocks C_MUX_SLICE_BUFT_V7_0 module +*/ + +`timescale 1ns/10ps + +`define allXs {C_WIDTH{1'bx}} +`define allZs {C_WIDTH{1'bz}} + +module C_MUX_SLICE_BUFT_V7_0 (I, T, O); + + parameter C_WIDTH = 16; /* Width of the single input */ + + input [C_WIDTH-1 : 0] I; + input T; + output [C_WIDTH-1 : 0] O; + + reg [C_WIDTH-1 : 0] intO; + + wire [C_WIDTH-1 : 0] #1 O = intO; + + initial + begin + + if (T == 0) + intO = I; + else if (T == 1) + intO = `allZs; + else + intO = `allXs; + end + + always@(I or T) + begin + if (T == 0) + intO <= I; + else if (T == 1) + intO <= `allZs; + else + intO <= `allXs; + end + +endmodule + +`undef allXs +`undef allZs + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/C_REG_FD_V4_0.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/C_REG_FD_V4_0.v new file mode 100644 index 0000000..52c2364 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/C_REG_FD_V4_0.v @@ -0,0 +1,333 @@ +/* $Id: C_REG_FD_V4_0.v,v 1.11 2008/09/08 20:05:46 akennedy Exp $ +-- +-- Filename - C_REG_FD_V4_0.v +-- Author - Xilinx +-- Creation - 21 Oct 1998 +-- +-- Description - This file contains the Verilog behavior for the baseblocks C_REG_FD_V4_0 module +*/ + + +`define c_set 0 +`define c_clear 1 +`define c_override 0 +`define c_no_override 1 + +`define all1s {C_WIDTH{1'b1}} +`define all0s 'b0 +`define allXs {C_WIDTH{1'bx}} + +module C_REG_FD_V4_0 (D, CLK, CE, ACLR, ASET, AINIT, SCLR, SSET, SINIT, Q); + + parameter C_AINIT_VAL = ""; + parameter C_ENABLE_RLOCS = 1; + parameter C_HAS_ACLR = 0; + parameter C_HAS_AINIT = 0; + parameter C_HAS_ASET = 0; + parameter C_HAS_CE = 0; + parameter C_HAS_SCLR = 0; + parameter C_HAS_SINIT = 0; + parameter C_HAS_SSET = 0; + parameter C_SINIT_VAL = ""; + parameter C_SYNC_ENABLE = `c_override; + parameter C_SYNC_PRIORITY = `c_clear; + parameter C_WIDTH = 16; + + + input [C_WIDTH-1 : 0] D; + input CLK; + input CE; + input ACLR; + input ASET; + input AINIT; + input SCLR; + input SSET; + input SINIT; + output [C_WIDTH-1 : 0] Q; + + reg [C_WIDTH-1 : 0] data; + reg [C_WIDTH-1 : 0] datatmp; + // Internal values to drive signals when input is missing + wire intCE; + wire intACLR; + wire intASET; + wire intAINIT; + wire intSCLR; + wire intSSET; + wire intSINIT; + wire intCLK; + + wire [C_WIDTH-1 : 0] #1 Q = data; + + // Sort out default values for missing ports + + assign intCLK = CLK; + assign intACLR = defval(ACLR, C_HAS_ACLR, 0); + assign intASET = defval(ASET, C_HAS_ASET, 0); + assign intAINIT = defval(AINIT, C_HAS_AINIT, 0); + assign intSCLR = defval(SCLR, C_HAS_SCLR, 0); + assign intSSET = defval(SSET, C_HAS_SSET, 0); + assign intSINIT = defval(SINIT, C_HAS_SINIT, 0); + assign intCE = ((((C_HAS_ACLR == 1 || C_HAS_ASET == 1 || C_HAS_AINIT == 1) && + (C_HAS_SCLR == 1 || C_HAS_SSET == 1 || C_HAS_SINIT == 1)) || + (C_HAS_SCLR == 1 && C_HAS_SSET == 1 && C_SYNC_PRIORITY == `c_set)) && + (C_HAS_CE == 1) && (C_SYNC_ENABLE == `c_override) ? + (CE | intSCLR | intSSET | intSINIT) : ((C_HAS_CE == 1) ? CE : 1'b1)); + + reg lastCLK; + reg lastintACLR; + reg lastintASET; + + reg [C_WIDTH-1 : 0] AIV; + reg [C_WIDTH-1 : 0] SIV; + + + integer i; + integer ASYNC_CTRL; + + initial + begin + ASYNC_CTRL <= 1; + lastCLK = #1 1'b0; + lastintACLR <= 1'b0; + lastintASET <= 1'b0; + AIV = to_bits(C_AINIT_VAL); + SIV = to_bits(C_SINIT_VAL); + if(C_HAS_ACLR === 1) + data <= #1 `all0s; + else if(C_HAS_ASET === 1) + data <= #1 `all1s; + else if(C_HAS_AINIT === 1) + data <= #1 AIV; + else if(C_HAS_SCLR === 1) + data <= #1 `all0s; + else if(C_HAS_SSET === 1) + data <= #1 `all1s; + else if(C_HAS_SINIT === 1) + data <= #1 SIV; + else + data <= #1 AIV; + end + + // intCE removed from sensitivity list. + // Fix CR 128989 + //Neil Ritchie 8 Dec 2000 + + always@(posedge intCLK or intACLR or intASET or intAINIT) + begin + datatmp = data; + + for(i = 0; i < C_WIDTH; i = i + 1) + begin + if(intACLR === 1'b1) + datatmp[i] = 1'b0; + else if(intACLR === 1'b0 && intASET === 1'b1) + datatmp[i] = 1'b1; + else if(intAINIT === 1'b1) + datatmp[i] = AIV[i]; + else if(intACLR === 1'bx && intASET !== 1'b0) + datatmp[i] = 1'bx; + else if(intACLR != lastintACLR && lastintASET != intASET + && lastintACLR === 1'b1 && lastintASET === 1'b1 + && intACLR === 1'b0 && intASET === 1'b0) + datatmp[i] = 1'bx; + else + begin + ASYNC_CTRL = 0; + if(lastCLK !== intCLK && lastCLK === 1'b0 && intCLK === 1'b1) + begin + if((intCE !== 1'b0 || C_SYNC_ENABLE === 0) && + (C_SYNC_PRIORITY == 0 && intSSET === 1'bx && intSCLR !== 1'b0)) + begin + datatmp[i] = 1'bx; + ASYNC_CTRL = 1; + end + if((intCE !== 1'b0 || C_SYNC_ENABLE === 0) && + (C_SYNC_PRIORITY == 1 && intSSET !== 1'b0 && intSCLR === 1'bx)) + begin + datatmp[i] = 1'bx; + ASYNC_CTRL = 1; + end + if(intCE === 1'b1 && intSCLR !== 1'b1 && intSSET !== 1'b1 && intSINIT !== 1'b1 && ASYNC_CTRL == 0) + datatmp[i] = D[i]; + else if(intCE === 1'bx && datatmp[i] !== D[i] && intSCLR !== 1'b1 && intSSET !== 1'b1 && intSINIT !== 1'b1 && ASYNC_CTRL == 0) + datatmp[i] = 1'bx; + + if(intSINIT === 1'b1 && (intCE === 1'b1 || C_SYNC_ENABLE == 0) && ASYNC_CTRL == 0) + datatmp[i] = SIV[i]; + else if(intSINIT === 1'b1 && (intCE === 1'bx && C_SYNC_ENABLE == 1) && datatmp[i] !== SIV[i]) + datatmp[i] = 1'bx; + else if(intSINIT === 1'bx && (intCE !== 1'b0 || C_SYNC_ENABLE == 0) && datatmp[i] !== SIV[i]) + datatmp[i] = 1'bx; + + if(intSCLR === 1'b1 && (intCE === 1'b1 || C_SYNC_ENABLE == 0) && (C_SYNC_PRIORITY == 1 || intSSET === 1'b0) && ASYNC_CTRL == 0) + datatmp[i] = 1'b0; + else if(intSCLR === 1'b1 && (intCE === 1'bx && C_SYNC_ENABLE == 1) && datatmp[i] !== 1'b0 && (C_SYNC_PRIORITY == 1 || intSSET === 1'b0)) + datatmp[i] = 1'bx; + else if(intSCLR === 1'bx && (intCE !== 1'b0 || C_SYNC_ENABLE == 0) && datatmp[i] !== 1'b0 && (C_SYNC_PRIORITY == 1 || intSSET === 1'b0)) + datatmp[i] = 1'bx; + + if(intSSET === 1'b1 && (intCE === 1'b1 || C_SYNC_ENABLE == 0) && (C_SYNC_PRIORITY == 0 || intSCLR === 1'b0) && ASYNC_CTRL == 0) + datatmp[i] = 1'b1; + else if(intSSET === 1'b1 && (intCE === 1'bx && C_SYNC_ENABLE == 1) && datatmp[i] !== 1'b1 && (C_SYNC_PRIORITY == 0 || intSCLR === 1'b0)) + datatmp[i] = 1'bx; + else if(intSSET === 1'bx && (intCE !== 1'b0 || C_SYNC_ENABLE == 0) && datatmp[i] !== 1'b1 && (C_SYNC_PRIORITY == 0 || intSCLR === 1'b0)) + datatmp[i] = 1'bx; + end + else if(lastCLK !== intCLK && ((lastCLK === 1'b0 && intCLK === 1'bx) + || (lastCLK === 1'bx && intCLK === 1'b1))) + begin + if((intCE !== 1'b0 || C_SYNC_ENABLE == 0) && (C_SYNC_PRIORITY == 0 && intSSET === 1'bx && intSCLR !== 1'b0)) + datatmp[i] = 1'bx; + else if((intCE !== 1'b0 || C_SYNC_ENABLE == 0) && (C_SYNC_PRIORITY == 1 && intSSET !== 1'b0 && intSCLR === 1'bx)) + datatmp[i] = 1'bx; + + if(intCE !== 1'b0 && intSCLR !== 1'b1 && intSSET !== 1'b1 && intSINIT !== 1'b1 && datatmp[i] !== D[i]) + datatmp[i] = 1'bx; + + if(intSINIT !== 1'b0 && (intCE !== 1'b0 || C_SYNC_ENABLE == 0) && datatmp[i] !== SIV[i]) + datatmp[i] = 1'bx; + + if(intSCLR !== 1'b0 && (intCE !== 1'b0 || C_SYNC_ENABLE == 0) && (C_SYNC_PRIORITY == 1 || intSSET === 1'b0) && datatmp[i] !== 1'b0) + datatmp[i] = 1'bx; + + if(intSSET !== 1'b0 && (intCE !== 1'b0 || C_SYNC_ENABLE == 0) && (C_SYNC_PRIORITY == 0 || intSCLR === 1'b0) && datatmp[i] !== 1'b1) + datatmp[i] = 1'bx; + end + + if(intACLR === 1'b0 && intASET === 1'bx) + begin + if(datatmp[i] !== 1'b1) + begin + datatmp[i] = 1'bx; + ASYNC_CTRL = 1; + end + end + else if(intACLR === 1'bx && intASET === 1'b0) + begin + if(datatmp[i] !== 1'b0) + begin + datatmp[i] = 1'bx; + ASYNC_CTRL = 1; + end + end + else if(intAINIT === 1'bx) + begin + if(datatmp[i] !== AIV[i]) + begin + datatmp[i] = 1'bx; + ASYNC_CTRL = 1; + end + end + end + end + + data <= datatmp; + end + + + always@(intACLR or intASET) + begin + lastintACLR <= intACLR; + lastintASET <= intASET; + if($time != 0) + if(intACLR === 1'b0 && intASET === 1'b0 && lastintACLR !== 1'b0 && lastintASET !== 1'b0) // RACE + data <= `allXs; + end + + always@(intCLK) + lastCLK <= intCLK; + + + function defval; + input i; + input hassig; + input val; + begin + if(hassig == 1) + defval = i; + else + defval = val; + end + endfunction + + function [C_WIDTH - 1 : 0] to_bits; + input [C_WIDTH*8 : 1] instring; + integer i; + integer non_null_string; + begin + non_null_string = 0; + for(i = C_WIDTH; i > 0; i = i - 1) + begin // Is the string empty? + if(instring[(i*8)] == 0 && + instring[(i*8)-1] == 0 && + instring[(i*8)-2] == 0 && + instring[(i*8)-3] == 0 && + instring[(i*8)-4] == 0 && + instring[(i*8)-5] == 0 && + instring[(i*8)-6] == 0 && + instring[(i*8)-7] == 0 && + non_null_string == 0) + non_null_string = 0; // Use the return value to flag a non-empty string + else + non_null_string = 1; // Non-null character! + end + if(non_null_string == 0) // String IS empty! Just return the value to be all '0's + begin + for(i = C_WIDTH; i > 0; i = i - 1) + to_bits[i-1] = 0; + end + else + begin + for(i = C_WIDTH; i > 0; i = i - 1) + begin // Is this character a '0'? (ASCII = 48 = 00110000) + if(instring[(i*8)] == 0 && + instring[(i*8)-1] == 0 && + instring[(i*8)-2] == 1 && + instring[(i*8)-3] == 1 && + instring[(i*8)-4] == 0 && + instring[(i*8)-5] == 0 && + instring[(i*8)-6] == 0 && + instring[(i*8)-7] == 0) + to_bits[i-1] = 0; + // Or is it a '1'? + else if(instring[(i*8)] == 0 && + instring[(i*8)-1] == 0 && + instring[(i*8)-2] == 1 && + instring[(i*8)-3] == 1 && + instring[(i*8)-4] == 0 && + instring[(i*8)-5] == 0 && + instring[(i*8)-6] == 0 && + instring[(i*8)-7] == 1) + to_bits[i-1] = 1; + // Or is it a ' '? (a null char - in which case insert a '0') + else if(instring[(i*8)] == 0 && + instring[(i*8)-1] == 0 && + instring[(i*8)-2] == 0 && + instring[(i*8)-3] == 0 && + instring[(i*8)-4] == 0 && + instring[(i*8)-5] == 0 && + instring[(i*8)-6] == 0 && + instring[(i*8)-7] == 0) + to_bits[i-1] = 0; + else + begin + $display("Error: non-binary digit in string \"%s\"\nExiting simulation...", instring); + $finish; + end + end + end + end + endfunction + +endmodule + +`undef c_set +`undef c_clear +`undef c_override +`undef c_no_override + +`undef all1s +`undef all0s +`undef allXs + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/C_REG_FD_V5_0.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/C_REG_FD_V5_0.v new file mode 100644 index 0000000..0a09d66 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/C_REG_FD_V5_0.v @@ -0,0 +1,334 @@ +/* $Id: C_REG_FD_V5_0.v,v 1.17 2008/09/08 20:05:56 akennedy Exp $ +-- +-- Filename - C_REG_FD_V5_0.v +-- Author - Xilinx +-- Creation - 21 Oct 1998 +-- +-- Description - This file contains the Verilog behavior for the baseblocks C_REG_FD_V5_0 module +*/ + +`timescale 1ns/10ps + +`define c_set 0 +`define c_clear 1 +`define c_override 0 +`define c_no_override 1 + +`define all1s {C_WIDTH{1'b1}} +`define all0s 'b0 +`define allXs {C_WIDTH{1'bx}} + +module C_REG_FD_V5_0 (D, CLK, CE, ACLR, ASET, AINIT, SCLR, SSET, SINIT, Q); + + parameter C_AINIT_VAL = ""; + parameter C_ENABLE_RLOCS = 1; + parameter C_HAS_ACLR = 0; + parameter C_HAS_AINIT = 0; + parameter C_HAS_ASET = 0; + parameter C_HAS_CE = 0; + parameter C_HAS_SCLR = 0; + parameter C_HAS_SINIT = 0; + parameter C_HAS_SSET = 0; + parameter C_SINIT_VAL = ""; + parameter C_SYNC_ENABLE = `c_override; + parameter C_SYNC_PRIORITY = `c_clear; + parameter C_WIDTH = 16; + + + input [C_WIDTH-1 : 0] D; + input CLK; + input CE; + input ACLR; + input ASET; + input AINIT; + input SCLR; + input SSET; + input SINIT; + output [C_WIDTH-1 : 0] Q; + + reg [C_WIDTH-1 : 0] data; + reg [C_WIDTH-1 : 0] datatmp; + // Internal values to drive signals when input is missing + wire intCE; + wire intACLR; + wire intASET; + wire intAINIT; + wire intSCLR; + wire intSSET; + wire intSINIT; + wire intCLK; + + wire [C_WIDTH-1 : 0] #1 Q = data; + + // Sort out default values for missing ports + + assign intCLK = CLK; + assign intACLR = defval(ACLR, C_HAS_ACLR, 0); + assign intASET = defval(ASET, C_HAS_ASET, 0); + assign intAINIT = defval(AINIT, C_HAS_AINIT, 0); + assign intSCLR = defval(SCLR, C_HAS_SCLR, 0); + assign intSSET = defval(SSET, C_HAS_SSET, 0); + assign intSINIT = defval(SINIT, C_HAS_SINIT, 0); + assign intCE = ((((C_HAS_ACLR == 1 || C_HAS_ASET == 1 || C_HAS_AINIT == 1) && + (C_HAS_SCLR == 1 || C_HAS_SSET == 1 || C_HAS_SINIT == 1)) || + (C_HAS_SCLR == 1 && C_HAS_SSET == 1 && C_SYNC_PRIORITY == `c_set)) && + (C_HAS_CE == 1) && (C_SYNC_ENABLE == `c_override) ? + (CE | intSCLR | intSSET | intSINIT) : ((C_HAS_CE == 1) ? CE : 1'b1)); + + reg lastCLK; + reg lastintACLR; + reg lastintASET; + + reg [C_WIDTH-1 : 0] AIV; + reg [C_WIDTH-1 : 0] SIV; + + + integer i; + integer ASYNC_CTRL; + + initial + begin + ASYNC_CTRL <= 1; + lastCLK = #1 1'b0; + lastintACLR <= 1'b0; + lastintASET <= 1'b0; + AIV = to_bits(C_AINIT_VAL); + SIV = to_bits(C_SINIT_VAL); + if(C_HAS_ACLR === 1) + data <= #1 `all0s; + else if(C_HAS_ASET === 1) + data <= #1 `all1s; + else if(C_HAS_AINIT === 1) + data <= #1 AIV; + else if(C_HAS_SCLR === 1) + data <= #1 `all0s; + else if(C_HAS_SSET === 1) + data <= #1 `all1s; + else if(C_HAS_SINIT === 1) + data <= #1 SIV; + else + data <= #1 AIV; + end + + // intCE removed from sensitivity list. + // Fix CR 128989 + //Neil Ritchie 8 Dec 2000 + + always@(posedge intCLK or intACLR or intASET or intAINIT) + begin + datatmp = data; + + for(i = 0; i < C_WIDTH; i = i + 1) + begin + if(intACLR === 1'b1) + datatmp[i] = 1'b0; + else if(intACLR === 1'b0 && intASET === 1'b1) + datatmp[i] = 1'b1; + else if(intAINIT === 1'b1) + datatmp[i] = AIV[i]; + else if(intACLR === 1'bx && intASET !== 1'b0) + datatmp[i] = 1'bx; + else if(intACLR != lastintACLR && lastintASET != intASET + && lastintACLR === 1'b1 && lastintASET === 1'b1 + && intACLR === 1'b0 && intASET === 1'b0) + datatmp[i] = 1'bx; + else + begin + ASYNC_CTRL = 0; + if(lastCLK !== intCLK && lastCLK === 1'b0 && intCLK === 1'b1) + begin + if((intCE !== 1'b0 || C_SYNC_ENABLE === 0) && + (C_SYNC_PRIORITY == 0 && intSSET === 1'bx && intSCLR !== 1'b0)) + begin + datatmp[i] = 1'bx; + ASYNC_CTRL = 1; + end + if((intCE !== 1'b0 || C_SYNC_ENABLE === 0) && + (C_SYNC_PRIORITY == 1 && intSSET !== 1'b0 && intSCLR === 1'bx)) + begin + datatmp[i] = 1'bx; + ASYNC_CTRL = 1; + end + if(intCE === 1'b1 && intSCLR !== 1'b1 && intSSET !== 1'b1 && intSINIT !== 1'b1 && ASYNC_CTRL == 0) + datatmp[i] = D[i]; + else if(intCE === 1'bx && datatmp[i] !== D[i] && intSCLR !== 1'b1 && intSSET !== 1'b1 && intSINIT !== 1'b1 && ASYNC_CTRL == 0) + datatmp[i] = 1'bx; + + if(intSINIT === 1'b1 && (intCE === 1'b1 || C_SYNC_ENABLE == 0) && ASYNC_CTRL == 0) + datatmp[i] = SIV[i]; + else if(intSINIT === 1'b1 && (intCE === 1'bx && C_SYNC_ENABLE == 1) && datatmp[i] !== SIV[i]) + datatmp[i] = 1'bx; + else if(intSINIT === 1'bx && (intCE !== 1'b0 || C_SYNC_ENABLE == 0) && datatmp[i] !== SIV[i]) + datatmp[i] = 1'bx; + + if(intSCLR === 1'b1 && (intCE === 1'b1 || C_SYNC_ENABLE == 0) && (C_SYNC_PRIORITY == 1 || intSSET === 1'b0) && ASYNC_CTRL == 0) + datatmp[i] = 1'b0; + else if(intSCLR === 1'b1 && (intCE === 1'bx && C_SYNC_ENABLE == 1) && datatmp[i] !== 1'b0 && (C_SYNC_PRIORITY == 1 || intSSET === 1'b0)) + datatmp[i] = 1'bx; + else if(intSCLR === 1'bx && (intCE !== 1'b0 || C_SYNC_ENABLE == 0) && datatmp[i] !== 1'b0 && (C_SYNC_PRIORITY == 1 || intSSET === 1'b0)) + datatmp[i] = 1'bx; + + if(intSSET === 1'b1 && (intCE === 1'b1 || C_SYNC_ENABLE == 0) && (C_SYNC_PRIORITY == 0 || intSCLR === 1'b0) && ASYNC_CTRL == 0) + datatmp[i] = 1'b1; + else if(intSSET === 1'b1 && (intCE === 1'bx && C_SYNC_ENABLE == 1) && datatmp[i] !== 1'b1 && (C_SYNC_PRIORITY == 0 || intSCLR === 1'b0)) + datatmp[i] = 1'bx; + else if(intSSET === 1'bx && (intCE !== 1'b0 || C_SYNC_ENABLE == 0) && datatmp[i] !== 1'b1 && (C_SYNC_PRIORITY == 0 || intSCLR === 1'b0)) + datatmp[i] = 1'bx; + end + else if(lastCLK !== intCLK && ((lastCLK === 1'b0 && intCLK === 1'bx) + || (lastCLK === 1'bx && intCLK === 1'b1))) + begin + if((intCE !== 1'b0 || C_SYNC_ENABLE == 0) && (C_SYNC_PRIORITY == 0 && intSSET === 1'bx && intSCLR !== 1'b0)) + datatmp[i] = 1'bx; + else if((intCE !== 1'b0 || C_SYNC_ENABLE == 0) && (C_SYNC_PRIORITY == 1 && intSSET !== 1'b0 && intSCLR === 1'bx)) + datatmp[i] = 1'bx; + + if(intCE !== 1'b0 && intSCLR !== 1'b1 && intSSET !== 1'b1 && intSINIT !== 1'b1 && datatmp[i] !== D[i]) + datatmp[i] = 1'bx; + + if(intSINIT !== 1'b0 && (intCE !== 1'b0 || C_SYNC_ENABLE == 0) && datatmp[i] !== SIV[i]) + datatmp[i] = 1'bx; + + if(intSCLR !== 1'b0 && (intCE !== 1'b0 || C_SYNC_ENABLE == 0) && (C_SYNC_PRIORITY == 1 || intSSET === 1'b0) && datatmp[i] !== 1'b0) + datatmp[i] = 1'bx; + + if(intSSET !== 1'b0 && (intCE !== 1'b0 || C_SYNC_ENABLE == 0) && (C_SYNC_PRIORITY == 0 || intSCLR === 1'b0) && datatmp[i] !== 1'b1) + datatmp[i] = 1'bx; + end + + if(intACLR === 1'b0 && intASET === 1'bx) + begin + if(datatmp[i] !== 1'b1) + begin + datatmp[i] = 1'bx; + ASYNC_CTRL = 1; + end + end + else if(intACLR === 1'bx && intASET === 1'b0) + begin + if(datatmp[i] !== 1'b0) + begin + datatmp[i] = 1'bx; + ASYNC_CTRL = 1; + end + end + else if(intAINIT === 1'bx) + begin + if(datatmp[i] !== AIV[i]) + begin + datatmp[i] = 1'bx; + ASYNC_CTRL = 1; + end + end + end + end + + data <= datatmp; + end + + + always@(intACLR or intASET) + begin + lastintACLR <= intACLR; + lastintASET <= intASET; + if($time != 0) + if(intACLR === 1'b0 && intASET === 1'b0 && lastintACLR !== 1'b0 && lastintASET !== 1'b0) // RACE + data <= `allXs; + end + + always@(intCLK) + lastCLK <= intCLK; + + + function defval; + input i; + input hassig; + input val; + begin + if(hassig == 1) + defval = i; + else + defval = val; + end + endfunction + + function [C_WIDTH - 1 : 0] to_bits; + input [C_WIDTH*8 : 1] instring; + integer i; + integer non_null_string; + begin + non_null_string = 0; + for(i = C_WIDTH; i > 0; i = i - 1) + begin // Is the string empty? + if(instring[(i*8)] == 0 && + instring[(i*8)-1] == 0 && + instring[(i*8)-2] == 0 && + instring[(i*8)-3] == 0 && + instring[(i*8)-4] == 0 && + instring[(i*8)-5] == 0 && + instring[(i*8)-6] == 0 && + instring[(i*8)-7] == 0 && + non_null_string == 0) + non_null_string = 0; // Use the return value to flag a non-empty string + else + non_null_string = 1; // Non-null character! + end + if(non_null_string == 0) // String IS empty! Just return the value to be all '0's + begin + for(i = C_WIDTH; i > 0; i = i - 1) + to_bits[i-1] = 0; + end + else + begin + for(i = C_WIDTH; i > 0; i = i - 1) + begin // Is this character a '0'? (ASCII = 48 = 00110000) + if(instring[(i*8)] == 0 && + instring[(i*8)-1] == 0 && + instring[(i*8)-2] == 1 && + instring[(i*8)-3] == 1 && + instring[(i*8)-4] == 0 && + instring[(i*8)-5] == 0 && + instring[(i*8)-6] == 0 && + instring[(i*8)-7] == 0) + to_bits[i-1] = 0; + // Or is it a '1'? + else if(instring[(i*8)] == 0 && + instring[(i*8)-1] == 0 && + instring[(i*8)-2] == 1 && + instring[(i*8)-3] == 1 && + instring[(i*8)-4] == 0 && + instring[(i*8)-5] == 0 && + instring[(i*8)-6] == 0 && + instring[(i*8)-7] == 1) + to_bits[i-1] = 1; + // Or is it a ' '? (a null char - in which case insert a '0') + else if(instring[(i*8)] == 0 && + instring[(i*8)-1] == 0 && + instring[(i*8)-2] == 0 && + instring[(i*8)-3] == 0 && + instring[(i*8)-4] == 0 && + instring[(i*8)-5] == 0 && + instring[(i*8)-6] == 0 && + instring[(i*8)-7] == 0) + to_bits[i-1] = 0; + else + begin + $display("Error in %m at time %d ns: non-binary digit in string \"%s\"\nExiting simulation...", $time, instring); + $finish; + end + end + end + end + endfunction + +endmodule + +`undef c_set +`undef c_clear +`undef c_override +`undef c_no_override + +`undef all1s +`undef all0s +`undef allXs + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/C_REG_FD_V6_0.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/C_REG_FD_V6_0.v new file mode 100644 index 0000000..e35f3ab --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/C_REG_FD_V6_0.v @@ -0,0 +1,349 @@ +// Copyright(C) 2002 by Xilinx, Inc. All rights reserved. +// This text contains proprietary, confidential +// information of Xilinx, Inc., is distributed +// under license from Xilinx, Inc., and may be used, +// copied and/or disclosed only pursuant to the terms +// of a valid license agreement with Xilinx, Inc. This copyright +// notice must be retained as part of this text at all times. + + +/* $Id: C_REG_FD_V6_0.v,v 1.16 2008/09/08 20:06:04 akennedy Exp $ +-- +-- Filename - C_REG_FD_V6_0.v +-- Author - Xilinx +-- Creation - 21 Oct 1998 +-- +-- Description - This file contains the Verilog behavior for the baseblocks C_REG_FD_V6_0 module +*/ + +`timescale 1ns/10ps + +`define c_set 0 +`define c_clear 1 +`define c_override 0 +`define c_no_override 1 + +`define all1s {C_WIDTH{1'b1}} +`define all0s 'b0 +`define allXs {C_WIDTH{1'bx}} + +module C_REG_FD_V6_0 (D, CLK, CE, ACLR, ASET, AINIT, SCLR, SSET, SINIT, Q); + + parameter C_AINIT_VAL = ""; + parameter C_ENABLE_RLOCS = 1; + parameter C_HAS_ACLR = 0; + parameter C_HAS_AINIT = 0; + parameter C_HAS_ASET = 0; + parameter C_HAS_CE = 0; + parameter C_HAS_SCLR = 0; + parameter C_HAS_SINIT = 0; + parameter C_HAS_SSET = 0; + parameter C_SINIT_VAL = ""; + parameter C_SYNC_ENABLE = `c_override; + parameter C_SYNC_PRIORITY = `c_clear; + parameter C_WIDTH = 16; + + + input [C_WIDTH-1 : 0] D; + input CLK; + input CE; + input ACLR; + input ASET; + input AINIT; + input SCLR; + input SSET; + input SINIT; + output [C_WIDTH-1 : 0] Q; + + reg [C_WIDTH-1 : 0] data; + reg [C_WIDTH-1 : 0] datatmp; + // Internal values to drive signals when input is missing + wire intCE; + wire intACLR; + wire intASET; + wire intAINIT; + wire intSCLR; + wire intSSET; + wire intSINIT; + wire intCLK; + + wire [C_WIDTH-1 : 0] #1 Q = data; + + // Sort out default values for missing ports + + assign intCLK = CLK; + assign intACLR = defval(ACLR, C_HAS_ACLR, 0); + assign intASET = defval(ASET, C_HAS_ASET, 0); + assign intAINIT = defval(AINIT, C_HAS_AINIT, 0); + assign intSCLR = defval(SCLR, C_HAS_SCLR, 0); + assign intSSET = defval(SSET, C_HAS_SSET, 0); + assign intSINIT = defval(SINIT, C_HAS_SINIT, 0); + assign intCE = ((((C_HAS_ACLR == 1 || C_HAS_ASET == 1 || C_HAS_AINIT == 1) && + (C_HAS_SCLR == 1 || C_HAS_SSET == 1 || C_HAS_SINIT == 1)) || + (C_HAS_SCLR == 1 && C_HAS_SSET == 1 && C_SYNC_PRIORITY == `c_set)) && + (C_HAS_CE == 1) && (C_SYNC_ENABLE == `c_override) ? + (CE | intSCLR | intSSET | intSINIT) : ((C_HAS_CE == 1) ? CE : 1'b1)); + + reg lastCLK; + reg lastintACLR; + reg lastintASET; + + reg [C_WIDTH-1 : 0] AIV; + reg [C_WIDTH-1 : 0] SIV; + + + integer i; + integer ASYNC_CTRL; + + initial + begin + ASYNC_CTRL <= 1; + lastCLK = intCLK; + lastintACLR <= 1'b0; + lastintASET <= 1'b0; + AIV = to_bits(C_AINIT_VAL); + SIV = to_bits(C_SINIT_VAL); + if(C_HAS_ACLR === 1) + data <= #1 `all0s; + else if(C_HAS_ASET === 1) + data <= #1 `all1s; + else if(C_HAS_AINIT === 1) + data <= #1 AIV; + else if(C_HAS_SCLR === 1) + data <= #1 `all0s; + else if(C_HAS_SSET === 1) + data <= #1 `all1s; + else if(C_HAS_SINIT === 1) + data <= #1 SIV; + else + data <= #1 AIV; + end + + // intCE removed from sensitivity list. + // Fix CR 128989 + //Neil Ritchie 8 Dec 2000 + + always@(posedge intCLK or intACLR or intASET or intAINIT) + begin + datatmp = data; + +// for(i = 0; i < C_WIDTH; i = i + 1) +// begin + if(intACLR === 1'b1) + datatmp = `all0s; + else if(intACLR === 1'b0 && intASET === 1'b1) + datatmp = `all1s; + else if(intAINIT === 1'b1) + datatmp = AIV; + else if(intACLR === 1'bx && intASET !== 1'b0) + datatmp = `allXs; + else if(intACLR != lastintACLR && lastintASET != intASET + && lastintACLR === 1'b1 && lastintASET === 1'b1 + && intACLR === 1'b0 && intASET === 1'b0) + datatmp = `allXs; + else + begin + ASYNC_CTRL = 0; + if(lastCLK !== intCLK && lastCLK === 1'b0 && intCLK === 1'b1) + begin + if((intCE !== 1'b0 || C_SYNC_ENABLE === 0) && + (C_SYNC_PRIORITY == 0 && intSSET === 1'bx && intSCLR !== 1'b0)) + begin + datatmp = `allXs; + ASYNC_CTRL = 1; + end + if((intCE !== 1'b0 || C_SYNC_ENABLE === 0) && + (C_SYNC_PRIORITY == 1 && intSSET !== 1'b0 && intSCLR === 1'bx)) + begin + datatmp = `allXs; + ASYNC_CTRL = 1; + end + if(intCE === 1'b1 && intSCLR !== 1'b1 && intSSET !== 1'b1 && intSINIT !== 1'b1 && ASYNC_CTRL == 0) + datatmp = D; + else if(intCE === 1'bx && intSCLR !== 1'b1 && intSSET !== 1'b1 && intSINIT !== 1'b1 && ASYNC_CTRL == 0) + datatmp = ~((~(datatmp ^ D) | `allXs) ^ datatmp); + + if(intSINIT === 1'b1 && (intCE === 1'b1 || C_SYNC_ENABLE == 0) && ASYNC_CTRL == 0) + datatmp = SIV; + else if(intSINIT === 1'b1 && (intCE === 1'bx && C_SYNC_ENABLE == 1)) + datatmp = ~((~(datatmp ^ SIV) | `allXs) ^ datatmp); + else if(intSINIT === 1'bx && (intCE !== 1'b0 || C_SYNC_ENABLE == 0)) + datatmp = ~((~(datatmp ^ SIV) | `allXs) ^ datatmp); + + if(intSCLR === 1'b1 && (intCE === 1'b1 || C_SYNC_ENABLE == 0) && (C_SYNC_PRIORITY == 1 || intSSET === 1'b0) && ASYNC_CTRL == 0) + datatmp = `all0s; + else if(intSCLR === 1'b1 && (intCE === 1'bx && C_SYNC_ENABLE == 1) && (C_SYNC_PRIORITY == 1 || intSSET === 1'b0)) + datatmp = ~(~datatmp | `allXs); + else if(intSCLR === 1'bx && (intCE !== 1'b0 || C_SYNC_ENABLE == 0) && (C_SYNC_PRIORITY == 1 || intSSET === 1'b0)) + datatmp = ~(~datatmp | `allXs); + + if(intSSET === 1'b1 && (intCE === 1'b1 || C_SYNC_ENABLE == 0) && (C_SYNC_PRIORITY == 0 || intSCLR === 1'b0) && ASYNC_CTRL == 0) + datatmp = `all1s; + else if(intSSET === 1'b1 && (intCE === 1'bx && C_SYNC_ENABLE == 1) && (C_SYNC_PRIORITY == 0 || intSCLR === 1'b0)) + datatmp = datatmp | `allXs; + else if(intSSET === 1'bx && (intCE !== 1'b0 || C_SYNC_ENABLE == 0) && (C_SYNC_PRIORITY == 0 || intSCLR === 1'b0)) + datatmp = datatmp | `allXs; + end + else if(lastCLK !== intCLK && ((lastCLK === 1'b0 && intCLK === 1'bx) + || (lastCLK === 1'bx && intCLK === 1'b1))) + begin + if((intCE !== 1'b0 || C_SYNC_ENABLE == 0) && (C_SYNC_PRIORITY == 0 && intSSET === 1'bx && intSCLR !== 1'b0)) + datatmp = `allXs; + else if((intCE !== 1'b0 || C_SYNC_ENABLE == 0) && (C_SYNC_PRIORITY == 1 && intSSET !== 1'b0 && intSCLR === 1'bx)) + datatmp = `allXs; + + if(intCE !== 1'b0 && intSCLR !== 1'b1 && intSSET !== 1'b1 && intSINIT !== 1'b1) + datatmp = ~((~(datatmp ^ D) | `allXs) ^ datatmp); + + if(intSINIT !== 1'b0 && (intCE !== 1'b0 || C_SYNC_ENABLE == 0)) + datatmp = ~((~(datatmp ^ SIV) | `allXs) ^ datatmp); + + if(intSCLR !== 1'b0 && (intCE !== 1'b0 || C_SYNC_ENABLE == 0) && (C_SYNC_PRIORITY == 1 || intSSET === 1'b0)) + datatmp = ~(~datatmp | `allXs); + + if(intSSET !== 1'b0 && (intCE !== 1'b0 || C_SYNC_ENABLE == 0) && (C_SYNC_PRIORITY == 0 || intSCLR === 1'b0)) + datatmp = datatmp | `allXs; + end + + if(intACLR === 1'b0 && intASET === 1'bx) + begin +// if(datatmp[i] !== 1'b1) +// begin +// datatmp[i] = 1'bx; +// ASYNC_CTRL = 1; +// end + ASYNC_CTRL = |(~datatmp) ? 1 : 0; + datatmp = datatmp | `allXs; + end + else if(intACLR === 1'bx && intASET === 1'b0) + begin +// if(datatmp[i] !== 1'b0) +// begin +// datatmp[i] = 1'bx; +// ASYNC_CTRL = 1; +// end + ASYNC_CTRL = |datatmp ? 1 : 0; + datatmp = datatmp & `allXs; + end + else if(intAINIT === 1'bx) + begin +// if(datatmp[i] !== AIV[i]) +// begin +// datatmp[i] = 1'bx; +// ASYNC_CTRL = 1; +// end + ASYNC_CTRL = |(datatmp ^ AIV) ? 1 : 0; + datatmp = ~((~(datatmp ^ AIV) | `allXs) ^ datatmp); + end + end +// end + + data <= datatmp; + end + + + always@(intACLR or intASET) + begin + lastintACLR <= intACLR; + lastintASET <= intASET; + if($time != 0) + if(intACLR === 1'b0 && intASET === 1'b0 && lastintACLR !== 1'b0 && lastintASET !== 1'b0) // RACE + data <= `allXs; + end + + always@(intCLK) + lastCLK <= intCLK; + + + function defval; + input i; + input hassig; + input val; + begin + if(hassig == 1) + defval = i; + else + defval = val; + end + endfunction + + function [C_WIDTH - 1 : 0] to_bits; + input [C_WIDTH*8 : 1] instring; + integer i; + integer non_null_string; + begin + non_null_string = 0; + for(i = C_WIDTH; i > 0; i = i - 1) + begin // Is the string empty? + if(instring[(i*8)] == 0 && + instring[(i*8)-1] == 0 && + instring[(i*8)-2] == 0 && + instring[(i*8)-3] == 0 && + instring[(i*8)-4] == 0 && + instring[(i*8)-5] == 0 && + instring[(i*8)-6] == 0 && + instring[(i*8)-7] == 0 && + non_null_string == 0) + non_null_string = 0; // Use the return value to flag a non-empty string + else + non_null_string = 1; // Non-null character! + end + if(non_null_string == 0) // String IS empty! Just return the value to be all '0's + begin + for(i = C_WIDTH; i > 0; i = i - 1) + to_bits[i-1] = 0; + end + else + begin + for(i = C_WIDTH; i > 0; i = i - 1) + begin // Is this character a '0'? (ASCII = 48 = 00110000) + if(instring[(i*8)] == 0 && + instring[(i*8)-1] == 0 && + instring[(i*8)-2] == 1 && + instring[(i*8)-3] == 1 && + instring[(i*8)-4] == 0 && + instring[(i*8)-5] == 0 && + instring[(i*8)-6] == 0 && + instring[(i*8)-7] == 0) + to_bits[i-1] = 0; + // Or is it a '1'? + else if(instring[(i*8)] == 0 && + instring[(i*8)-1] == 0 && + instring[(i*8)-2] == 1 && + instring[(i*8)-3] == 1 && + instring[(i*8)-4] == 0 && + instring[(i*8)-5] == 0 && + instring[(i*8)-6] == 0 && + instring[(i*8)-7] == 1) + to_bits[i-1] = 1; + // Or is it a ' '? (a null char - in which case insert a '0') + else if(instring[(i*8)] == 0 && + instring[(i*8)-1] == 0 && + instring[(i*8)-2] == 0 && + instring[(i*8)-3] == 0 && + instring[(i*8)-4] == 0 && + instring[(i*8)-5] == 0 && + instring[(i*8)-6] == 0 && + instring[(i*8)-7] == 0) + to_bits[i-1] = 0; + else + begin + $display("Error in %m at time %d ns: non-binary digit in string \"%s\"\nExiting simulation...", $time, instring); + $finish; + end + end + end + end + endfunction + +endmodule + +`undef c_set +`undef c_clear +`undef c_override +`undef c_no_override + +`undef all1s +`undef all0s +`undef allXs + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/C_REG_FD_V7_0.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/C_REG_FD_V7_0.v new file mode 100644 index 0000000..ee9c254 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/C_REG_FD_V7_0.v @@ -0,0 +1,378 @@ +// Copyright(C) 2003 by Xilinx, Inc. All rights reserved. +// This text/file contains proprietary, confidential +// information of Xilinx, Inc., is distributed under license +// from Xilinx, Inc., and may be used, copied and/or +// disclosed only pursuant to the terms of a valid license +// agreement with Xilinx, Inc. Xilinx hereby grants you +// a license to use this text/file solely for design, simulation, +// implementation and creation of design files limited +// to Xilinx devices or technologies. Use with non-Xilinx +// devices or technologies is expressly prohibited and +// immediately terminates your license unless covered by +// a separate agreement. +// +// Xilinx is providing this design, code, or information +// "as is" solely for use in developing programs and +// solutions for Xilinx devices. By providing this design, +// code, or information as one possible implementation of +// this feature, application or standard, Xilinx is making no +// representation that this implementation is free from any +// claims of infringement. You are responsible for +// obtaining any rights you may require for your implementation. +// Xilinx expressly disclaims any warranty whatsoever with +// respect to the adequacy of the implementation, including +// but not limited to any warranties or representations that this +// implementation is free from claims of infringement, implied +// warranties of merchantability or fitness for a particular +// purpose. +// +// Xilinx products are not intended for use in life support +// appliances, devices, or systems. Use in such applications are +// expressly prohibited. +// +// This copyright and support notice must be retained as part +// of this text at all times. (c) Copyright 1995-2003 Xilinx, Inc. +// All rights reserved. + + + +/* $Id: C_REG_FD_V7_0.v,v 1.13 2008/09/08 20:06:13 akennedy Exp $ +-- +-- Filename - C_REG_FD_V7_0.v +-- Author - Xilinx +-- Creation - 21 Oct 1998 +-- +-- Description - This file contains the Verilog behavior for the baseblocks C_REG_FD_V7_0 module +*/ + +`timescale 1ns/10ps + +`define c_set 0 +`define c_clear 1 +`define c_override 0 +`define c_no_override 1 + +`define all1s {C_WIDTH{1'b1}} +`define all0s 'b0 +`define allXs {C_WIDTH{1'bx}} + +module C_REG_FD_V7_0 (D, CLK, CE, ACLR, ASET, AINIT, SCLR, SSET, SINIT, Q); + + parameter C_AINIT_VAL = ""; + parameter C_ENABLE_RLOCS = 1; + parameter C_HAS_ACLR = 0; + parameter C_HAS_AINIT = 0; + parameter C_HAS_ASET = 0; + parameter C_HAS_CE = 0; + parameter C_HAS_SCLR = 0; + parameter C_HAS_SINIT = 0; + parameter C_HAS_SSET = 0; + parameter C_SINIT_VAL = ""; + parameter C_SYNC_ENABLE = `c_override; + parameter C_SYNC_PRIORITY = `c_clear; + parameter C_WIDTH = 16; + + + input [C_WIDTH-1 : 0] D; + input CLK; + input CE; + input ACLR; + input ASET; + input AINIT; + input SCLR; + input SSET; + input SINIT; + output [C_WIDTH-1 : 0] Q; + + reg [C_WIDTH-1 : 0] data; + reg [C_WIDTH-1 : 0] datatmp; + // Internal values to drive signals when input is missing + wire intCE; + wire intACLR; + wire intASET; + wire intAINIT; + wire intSCLR; + wire intSSET; + wire intSINIT; + wire intCLK; + + wire [C_WIDTH-1 : 0] #1 Q = data; + + // Sort out default values for missing ports + + assign intCLK = CLK; + assign intACLR = defval(ACLR, C_HAS_ACLR, 0); + assign intASET = defval(ASET, C_HAS_ASET, 0); + assign intAINIT = defval(AINIT, C_HAS_AINIT, 0); + assign intSCLR = defval(SCLR, C_HAS_SCLR, 0); + assign intSSET = defval(SSET, C_HAS_SSET, 0); + assign intSINIT = defval(SINIT, C_HAS_SINIT, 0); + assign intCE = ((((C_HAS_ACLR == 1 || C_HAS_ASET == 1 || C_HAS_AINIT == 1) && + (C_HAS_SCLR == 1 || C_HAS_SSET == 1 || C_HAS_SINIT == 1)) || + (C_HAS_SCLR == 1 && C_HAS_SSET == 1 && C_SYNC_PRIORITY == `c_set)) && + (C_HAS_CE == 1) && (C_SYNC_ENABLE == `c_override) ? + (CE | intSCLR | intSSET | intSINIT) : ((C_HAS_CE == 1) ? CE : 1'b1)); + + reg lastCLK; + reg lastintACLR; + reg lastintASET; + + reg [C_WIDTH-1 : 0] AIV; + reg [C_WIDTH-1 : 0] SIV; + + + integer i; + integer ASYNC_CTRL; + + initial + begin + ASYNC_CTRL <= 1; + lastCLK = intCLK; + lastintACLR <= 1'b0; + lastintASET <= 1'b0; + AIV = to_bits(C_AINIT_VAL); + SIV = to_bits(C_SINIT_VAL); + if(C_HAS_ACLR === 1) + data <= #1 `all0s; + else if(C_HAS_ASET === 1) + data <= #1 `all1s; + else if(C_HAS_AINIT === 1) + data <= #1 AIV; + else if(C_HAS_SCLR === 1) + data <= #1 `all0s; + else if(C_HAS_SSET === 1) + data <= #1 `all1s; + else if(C_HAS_SINIT === 1) + data <= #1 SIV; + else + data <= #1 AIV; + end + + // intCE removed from sensitivity list. + // Fix CR 128989 + //Neil Ritchie 8 Dec 2000 + + always@(posedge intCLK or intACLR or intASET or intAINIT) + begin + datatmp = data; + +// for(i = 0; i < C_WIDTH; i = i + 1) +// begin + if(intACLR === 1'b1) + datatmp = `all0s; + else if(intACLR === 1'b0 && intASET === 1'b1) + datatmp = `all1s; + else if(intAINIT === 1'b1) + datatmp = AIV; + else if(intACLR === 1'bx && intASET !== 1'b0) + datatmp = `allXs; + else if(intACLR != lastintACLR && lastintASET != intASET + && lastintACLR === 1'b1 && lastintASET === 1'b1 + && intACLR === 1'b0 && intASET === 1'b0) + datatmp = `allXs; + else + begin + ASYNC_CTRL = 0; + if(lastCLK !== intCLK && lastCLK === 1'b0 && intCLK === 1'b1) + begin + if((intCE !== 1'b0 || C_SYNC_ENABLE === 0) && + (C_SYNC_PRIORITY == 0 && intSSET === 1'bx && intSCLR !== 1'b0)) + begin + datatmp = `allXs; + ASYNC_CTRL = 1; + end + if((intCE !== 1'b0 || C_SYNC_ENABLE === 0) && + (C_SYNC_PRIORITY == 1 && intSSET !== 1'b0 && intSCLR === 1'bx)) + begin + datatmp = `allXs; + ASYNC_CTRL = 1; + end + if(intCE === 1'b1 && intSCLR !== 1'b1 && intSSET !== 1'b1 && intSINIT !== 1'b1 && ASYNC_CTRL == 0) + datatmp = D; + else if(intCE === 1'bx && intSCLR !== 1'b1 && intSSET !== 1'b1 && intSINIT !== 1'b1 && ASYNC_CTRL == 0) + datatmp = ~((~(datatmp ^ D) | `allXs) ^ datatmp); + + if(intSINIT === 1'b1 && (intCE === 1'b1 || C_SYNC_ENABLE == 0) && ASYNC_CTRL == 0) + datatmp = SIV; + else if(intSINIT === 1'b1 && (intCE === 1'bx && C_SYNC_ENABLE == 1)) + datatmp = ~((~(datatmp ^ SIV) | `allXs) ^ datatmp); + else if(intSINIT === 1'bx && (intCE !== 1'b0 || C_SYNC_ENABLE == 0)) + datatmp = ~((~(datatmp ^ SIV) | `allXs) ^ datatmp); + + if(intSCLR === 1'b1 && (intCE === 1'b1 || C_SYNC_ENABLE == 0) && (C_SYNC_PRIORITY == 1 || intSSET === 1'b0) && ASYNC_CTRL == 0) + datatmp = `all0s; + else if(intSCLR === 1'b1 && (intCE === 1'bx && C_SYNC_ENABLE == 1) && (C_SYNC_PRIORITY == 1 || intSSET === 1'b0)) + datatmp = ~(~datatmp | `allXs); + else if(intSCLR === 1'bx && (intCE !== 1'b0 || C_SYNC_ENABLE == 0) && (C_SYNC_PRIORITY == 1 || intSSET === 1'b0)) + datatmp = ~(~datatmp | `allXs); + + if(intSSET === 1'b1 && (intCE === 1'b1 || C_SYNC_ENABLE == 0) && (C_SYNC_PRIORITY == 0 || intSCLR === 1'b0) && ASYNC_CTRL == 0) + datatmp = `all1s; + else if(intSSET === 1'b1 && (intCE === 1'bx && C_SYNC_ENABLE == 1) && (C_SYNC_PRIORITY == 0 || intSCLR === 1'b0)) + datatmp = datatmp | `allXs; + else if(intSSET === 1'bx && (intCE !== 1'b0 || C_SYNC_ENABLE == 0) && (C_SYNC_PRIORITY == 0 || intSCLR === 1'b0)) + datatmp = datatmp | `allXs; + end + else if(lastCLK !== intCLK && ((lastCLK === 1'b0 && intCLK === 1'bx) + || (lastCLK === 1'bx && intCLK === 1'b1))) + begin + if((intCE !== 1'b0 || C_SYNC_ENABLE == 0) && (C_SYNC_PRIORITY == 0 && intSSET === 1'bx && intSCLR !== 1'b0)) + datatmp = `allXs; + else if((intCE !== 1'b0 || C_SYNC_ENABLE == 0) && (C_SYNC_PRIORITY == 1 && intSSET !== 1'b0 && intSCLR === 1'bx)) + datatmp = `allXs; + + if(intCE !== 1'b0 && intSCLR !== 1'b1 && intSSET !== 1'b1 && intSINIT !== 1'b1) + datatmp = ~((~(datatmp ^ D) | `allXs) ^ datatmp); + + if(intSINIT !== 1'b0 && (intCE !== 1'b0 || C_SYNC_ENABLE == 0)) + datatmp = ~((~(datatmp ^ SIV) | `allXs) ^ datatmp); + + if(intSCLR !== 1'b0 && (intCE !== 1'b0 || C_SYNC_ENABLE == 0) && (C_SYNC_PRIORITY == 1 || intSSET === 1'b0)) + datatmp = ~(~datatmp | `allXs); + + if(intSSET !== 1'b0 && (intCE !== 1'b0 || C_SYNC_ENABLE == 0) && (C_SYNC_PRIORITY == 0 || intSCLR === 1'b0)) + datatmp = datatmp | `allXs; + end + + if(intACLR === 1'b0 && intASET === 1'bx) + begin +// if(datatmp[i] !== 1'b1) +// begin +// datatmp[i] = 1'bx; +// ASYNC_CTRL = 1; +// end + ASYNC_CTRL = |(~datatmp) ? 1 : 0; + datatmp = datatmp | `allXs; + end + else if(intACLR === 1'bx && intASET === 1'b0) + begin +// if(datatmp[i] !== 1'b0) +// begin +// datatmp[i] = 1'bx; +// ASYNC_CTRL = 1; +// end + ASYNC_CTRL = |datatmp ? 1 : 0; + datatmp = datatmp & `allXs; + end + else if(intAINIT === 1'bx) + begin +// if(datatmp[i] !== AIV[i]) +// begin +// datatmp[i] = 1'bx; +// ASYNC_CTRL = 1; +// end + ASYNC_CTRL = |(datatmp ^ AIV) ? 1 : 0; + datatmp = ~((~(datatmp ^ AIV) | `allXs) ^ datatmp); + end + end +// end + + data <= datatmp; + end + + + always@(intACLR or intASET) + begin + lastintACLR <= intACLR; + lastintASET <= intASET; + if($time != 0) + if(intACLR === 1'b0 && intASET === 1'b0 && lastintACLR !== 1'b0 && lastintASET !== 1'b0) // RACE + data <= `allXs; + end + + always@(intCLK) + lastCLK <= intCLK; + + + function defval; + input i; + input hassig; + input val; + begin + if(hassig == 1) + defval = i; + else + defval = val; + end + endfunction + + function [C_WIDTH - 1 : 0] to_bits; + input [C_WIDTH*8 : 1] instring; + integer i; + integer non_null_string; + begin + non_null_string = 0; + for(i = C_WIDTH; i > 0; i = i - 1) + begin // Is the string empty? + if(instring[(i*8)] == 0 && + instring[(i*8)-1] == 0 && + instring[(i*8)-2] == 0 && + instring[(i*8)-3] == 0 && + instring[(i*8)-4] == 0 && + instring[(i*8)-5] == 0 && + instring[(i*8)-6] == 0 && + instring[(i*8)-7] == 0 && + non_null_string == 0) + non_null_string = 0; // Use the return value to flag a non-empty string + else + non_null_string = 1; // Non-null character! + end + if(non_null_string == 0) // String IS empty! Just return the value to be all '0's + begin + for(i = C_WIDTH; i > 0; i = i - 1) + to_bits[i-1] = 0; + end + else + begin + for(i = C_WIDTH; i > 0; i = i - 1) + begin // Is this character a '0'? (ASCII = 48 = 00110000) + if(instring[(i*8)] == 0 && + instring[(i*8)-1] == 0 && + instring[(i*8)-2] == 1 && + instring[(i*8)-3] == 1 && + instring[(i*8)-4] == 0 && + instring[(i*8)-5] == 0 && + instring[(i*8)-6] == 0 && + instring[(i*8)-7] == 0) + to_bits[i-1] = 0; + // Or is it a '1'? + else if(instring[(i*8)] == 0 && + instring[(i*8)-1] == 0 && + instring[(i*8)-2] == 1 && + instring[(i*8)-3] == 1 && + instring[(i*8)-4] == 0 && + instring[(i*8)-5] == 0 && + instring[(i*8)-6] == 0 && + instring[(i*8)-7] == 1) + to_bits[i-1] = 1; + // Or is it a ' '? (a null char - in which case insert a '0') + else if(instring[(i*8)] == 0 && + instring[(i*8)-1] == 0 && + instring[(i*8)-2] == 0 && + instring[(i*8)-3] == 0 && + instring[(i*8)-4] == 0 && + instring[(i*8)-5] == 0 && + instring[(i*8)-6] == 0 && + instring[(i*8)-7] == 0) + to_bits[i-1] = 0; + else + begin + $display("Error in %m at time %d ns: non-binary digit in string \"%s\"\nExiting simulation...", $time, instring); + $finish; + end + end + end + end + endfunction + +endmodule + +`undef c_set +`undef c_clear +`undef c_override +`undef c_no_override + +`undef all1s +`undef all0s +`undef allXs + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/C_REG_LD_V4_0.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/C_REG_LD_V4_0.v new file mode 100644 index 0000000..3955d44 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/C_REG_LD_V4_0.v @@ -0,0 +1,319 @@ +/* $Id: C_REG_LD_V4_0.v,v 1.11 2008/09/08 20:05:46 akennedy Exp $ +-- +-- Filename - C_REG_LD_V4_0.v +-- Author - Xilinx +-- Creation - 21 Oct 1998 +-- +-- Description - This file contains the Verilog behavior for the baseblocks C_REG_LD_V4_0 module +*/ + + +`define c_set 0 +`define c_clear 1 +`define c_override 0 +`define c_no_override 1 + +`define all1s {C_WIDTH{1'b1}} +`define all0s 'b0 +`define allXs {C_WIDTH{1'bx}} + +module C_REG_LD_V4_0 (D, G, GE, ACLR, ASET, AINIT, SCLR, SSET, SINIT, Q); + + parameter C_AINIT_VAL = ""; + parameter C_ENABLE_RLOCS = 1; + parameter C_HAS_ACLR = 0; + parameter C_HAS_AINIT = 0; + parameter C_HAS_ASET = 0; + parameter C_HAS_GE = 0; + parameter C_HAS_SCLR = 0; + parameter C_HAS_SINIT = 0; + parameter C_HAS_SSET = 0; + parameter C_SINIT_VAL = ""; + parameter C_SYNC_ENABLE = `c_override; + parameter C_SYNC_PRIORITY = `c_clear; + parameter C_WIDTH = 16; + + + input [C_WIDTH-1 : 0] D; + input G; + input GE; + input ACLR; + input ASET; + input AINIT; + input SCLR; + input SSET; + input SINIT; + output [C_WIDTH-1 : 0] Q; + + reg [C_WIDTH-1 : 0] data; + reg [C_WIDTH-1 : 0] datatmp; + // Internal values to drive signals when input is missing + wire intGE; + wire intACLR; + wire intASET; + wire intAINIT; + wire intSCLR; + wire intSSET; + wire intSINIT; + + wire [C_WIDTH-1 : 0] #1 Q = data; + + // Sort out default values for missing ports + + assign intACLR = defval(ACLR, C_HAS_ACLR, 0); + assign intASET = defval(ASET, C_HAS_ASET, 0); + assign intAINIT = defval(AINIT, C_HAS_AINIT, 0); + assign intSCLR = defval(SCLR, C_HAS_SCLR, 0); + assign intSSET = defval(SSET, C_HAS_SSET, 0); + assign intSINIT = defval(SINIT, C_HAS_SINIT, 0); + assign intGE = ((C_HAS_SCLR == 1 || C_HAS_SSET == 1 || C_HAS_SINIT == 1) && + (C_HAS_GE == 1) && (C_SYNC_ENABLE == `c_override) ? + (GE | intSCLR | intSSET | intSINIT) : ((C_HAS_GE == 1) ? GE : 1'b1)); + + reg lastintACLR; + reg lastintASET; + + reg [C_WIDTH-1 : 0] AIV; + reg [C_WIDTH-1 : 0] SIV; + + + integer i; + integer ASYNC_CTRL; + + initial + begin + ASYNC_CTRL = 1; + lastintACLR = 1'b0; + lastintASET = 1'b0; + AIV = to_bits(C_AINIT_VAL); + SIV = to_bits(C_SINIT_VAL); + if(C_HAS_ACLR === 1) + #1 data = `all0s; + else if(C_HAS_ASET === 1) + #1 data = `all1s; + else if(C_HAS_AINIT === 1) + #1 data = AIV; +// else if(C_HAS_SCLR === 1) +// #1 data = `all0s; +// else if(C_HAS_SSET === 1) +// #1 data = `all1s; +// else if(C_HAS_SINIT === 1) +// #1 data = SIV; + else + #1 data = AIV; + end + + always@(G or intGE or intACLR or intASET or intAINIT or intSCLR or intSSET or intSINIT or D) + begin + datatmp = data; + + for(i = 0; i < C_WIDTH; i = i + 1) + begin + if(intACLR === 1'b1) + datatmp[i] = 1'b0; + else if(intACLR === 1'b0 && intASET === 1'b1) + datatmp[i] = 1'b1; + else if(intAINIT === 1'b1) + datatmp[i] = AIV[i]; + else if(intACLR === 1'bx && intASET !== 1'b0) + datatmp[i] = 1'bx; + else if(intACLR != lastintACLR && lastintASET != intASET + && lastintACLR === 1'b1 && lastintASET === 1'b1 + && intACLR === 1'b0 && intASET === 1'b0) + datatmp[i] = 1'bx; + else + begin + ASYNC_CTRL = 0; + if(G === 1'b1) + begin + if((intGE !== 1'b0 || C_SYNC_ENABLE === 0) && + (C_SYNC_PRIORITY == 0 && intSSET === 1'bx && intSCLR !== 1'b0)) + begin + datatmp[i] = 1'bx; + ASYNC_CTRL = 1; + end + if((intGE !== 1'b0 || C_SYNC_ENABLE === 0) && + (C_SYNC_PRIORITY == 1 && intSSET !== 1'b0 && intSCLR === 1'bx)) + begin + datatmp[i] = 1'bx; + ASYNC_CTRL = 1; + end + if(intGE === 1'b1 && intSCLR !== 1'b1 && intSSET !== 1'b1 && intSINIT !== 1'b1 && ASYNC_CTRL == 0) + datatmp[i] = D[i]; + else if(intGE === 1'bx && datatmp[i] !== D[i] && intSCLR !== 1'b1 && intSSET !== 1'b1 && intSINIT !== 1'b1 && ASYNC_CTRL == 0) + datatmp[i] = 1'bx; + + if(intSINIT === 1'b1 && (intGE === 1'b1 || C_SYNC_ENABLE == 0) && ASYNC_CTRL == 0) + datatmp[i] = SIV[i]; + else if(intSINIT === 1'b1 && (intGE === 1'bx && C_SYNC_ENABLE == 1) && datatmp[i] !== SIV[i]) + datatmp[i] = 1'bx; + else if(intSINIT === 1'bx && (intGE !== 1'b0 || C_SYNC_ENABLE == 0) && datatmp[i] !== SIV[i]) + datatmp[i] = 1'bx; + + if(intSCLR === 1'b1 && (intGE === 1'b1 || C_SYNC_ENABLE == 0) && (C_SYNC_PRIORITY == 1 || intSSET === 1'b0) && ASYNC_CTRL == 0) + datatmp[i] = 1'b0; + else if(intSCLR === 1'b1 && (intGE === 1'bx && C_SYNC_ENABLE == 1) && datatmp[i] !== 1'b0 && (C_SYNC_PRIORITY == 1 || intSSET === 1'b0)) + datatmp[i] = 1'bx; + else if(intSCLR === 1'bx && (intGE !== 1'b0 || C_SYNC_ENABLE == 0) && datatmp[i] !== 1'b0 && (C_SYNC_PRIORITY == 1 || intSSET === 1'b0)) + datatmp[i] = 1'bx; + + if(intSSET === 1'b1 && (intGE === 1'b1 || C_SYNC_ENABLE == 0) && (C_SYNC_PRIORITY == 0 || intSCLR === 1'b0) && ASYNC_CTRL == 0) + datatmp[i] = 1'b1; + else if(intSSET === 1'b1 && (intGE === 1'bx && C_SYNC_ENABLE == 1) && datatmp[i] !== 1'b1 && (C_SYNC_PRIORITY == 0 || intSCLR === 1'b0)) + datatmp[i] = 1'bx; + else if(intSSET === 1'bx && (intGE !== 1'b0 || C_SYNC_ENABLE == 0) && datatmp[i] !== 1'b1 && (C_SYNC_PRIORITY == 0 || intSCLR === 1'b0)) + datatmp[i] = 1'bx; + end + else if(G === 1'bx) + begin + if((intGE !== 1'b0 || C_SYNC_ENABLE == 0) && (C_SYNC_PRIORITY == 0 && intSSET === 1'bx && intSCLR !== 1'b0)) + datatmp[i] = 1'bx; + else if((intGE !== 1'b0 || C_SYNC_ENABLE == 0) && (C_SYNC_PRIORITY == 1 && intSSET !== 1'b0 && intSCLR === 1'bx)) + datatmp[i] = 1'bx; + + if((intGE !== 1'b0 || (C_SYNC_ENABLE == 0 && (intSCLR !== 1'b0 || intSSET !== 1'b0 || intSINIT !== 1'b0))) && intSCLR !== 1'b1 && intSSET !== 1'b1 && intSINIT !== 1'b1 && datatmp[i] !== D[i]) + datatmp[i] = 1'bx; + + if(intSINIT !== 1'b0 && (intGE !== 1'b0 || C_SYNC_ENABLE == 0) && datatmp[i] !== SIV[i]) + datatmp[i] = 1'bx; + + if(intSCLR !== 1'b0 && (intGE !== 1'b0 || C_SYNC_ENABLE == 0) && (C_SYNC_PRIORITY == 1 || intSSET === 1'b0) && datatmp[i] !== 1'b0) + datatmp[i] = 1'bx; + + if(intSSET !== 1'b0 && (intGE !== 1'b0 || C_SYNC_ENABLE == 0) && (C_SYNC_PRIORITY == 0 || intSCLR === 1'b0) && datatmp[i] !== 1'b1) + datatmp[i] = 1'bx; + end + + if(intACLR === 1'b0 && intASET === 1'bx) + begin + if(datatmp[i] !== 1'b1) + begin + datatmp[i] = 1'bx; + ASYNC_CTRL = 1; + end + end + else if(intACLR === 1'bx && intASET === 1'b0) + begin + if(datatmp[i] !== 1'b0) + begin + datatmp[i] = 1'bx; + ASYNC_CTRL = 1; + end + end + else if(intAINIT === 1'bx) + begin + if(datatmp[i] !== AIV[i]) + begin + datatmp[i] = 1'bx; + ASYNC_CTRL = 1; + end + end + end + end + + data <= datatmp; + end + + + always@(intACLR or intASET) + begin + lastintACLR <= intACLR; + lastintASET <= intASET; + if($time != 0) + if(intACLR === 1'b0 && intASET === 1'b0 && lastintACLR !== 1'b0 && lastintASET !== 1'b0) // RACE + data <= `allXs; + end + + + function defval; + input i; + input hassig; + input val; + begin + if(hassig == 1) + defval = i; + else + defval = val; + end + endfunction + + function [C_WIDTH - 1 : 0] to_bits; + input [C_WIDTH*8 : 1] instring; + integer i; + integer non_null_string; + begin + non_null_string = 0; + for(i = C_WIDTH; i > 0; i = i - 1) + begin // Is the string empty? + if(instring[(i*8)] == 0 && + instring[(i*8)-1] == 0 && + instring[(i*8)-2] == 0 && + instring[(i*8)-3] == 0 && + instring[(i*8)-4] == 0 && + instring[(i*8)-5] == 0 && + instring[(i*8)-6] == 0 && + instring[(i*8)-7] == 0 && + non_null_string == 0) + non_null_string = 0; // Use the return value to flag a non-empty string + else + non_null_string = 1; // Non-null character! + end + if(non_null_string == 0) // String IS empty! Just return the value to be all '0's + begin + for(i = C_WIDTH; i > 0; i = i - 1) + to_bits[i-1] = 0; + end + else + begin + for(i = C_WIDTH; i > 0; i = i - 1) + begin // Is this character a '0'? (ASCII = 48 = 00110000) + if(instring[(i*8)] == 0 && + instring[(i*8)-1] == 0 && + instring[(i*8)-2] == 1 && + instring[(i*8)-3] == 1 && + instring[(i*8)-4] == 0 && + instring[(i*8)-5] == 0 && + instring[(i*8)-6] == 0 && + instring[(i*8)-7] == 0) + to_bits[i-1] = 0; + // Or is it a '1'? + else if(instring[(i*8)] == 0 && + instring[(i*8)-1] == 0 && + instring[(i*8)-2] == 1 && + instring[(i*8)-3] == 1 && + instring[(i*8)-4] == 0 && + instring[(i*8)-5] == 0 && + instring[(i*8)-6] == 0 && + instring[(i*8)-7] == 1) + to_bits[i-1] = 1; + // Or is it a ' '? (a null char - in which case insert a '0') + else if(instring[(i*8)] == 0 && + instring[(i*8)-1] == 0 && + instring[(i*8)-2] == 0 && + instring[(i*8)-3] == 0 && + instring[(i*8)-4] == 0 && + instring[(i*8)-5] == 0 && + instring[(i*8)-6] == 0 && + instring[(i*8)-7] == 0) + to_bits[i-1] = 0; + else + begin + $display("Error: non-binary digit in string \"%s\"\nExiting simulation...", instring); + $finish; + end + end + end + end + endfunction + +endmodule + +`undef c_set +`undef c_clear +`undef c_override +`undef c_no_override + +`undef all1s +`undef all0s +`undef allXs + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/C_REG_LD_V5_0.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/C_REG_LD_V5_0.v new file mode 100644 index 0000000..369cbeb --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/C_REG_LD_V5_0.v @@ -0,0 +1,319 @@ +/* $Id: C_REG_LD_V5_0.v,v 1.17 2008/09/08 20:05:56 akennedy Exp $ +-- +-- Filename - C_REG_LD_V5_0.v +-- Author - Xilinx +-- Creation - 21 Oct 1998 +-- +-- Description - This file contains the Verilog behavior for the baseblocks C_REG_LD_V5_0 module +*/ + +`timescale 1ns/10ps + +`define c_set 0 +`define c_clear 1 +`define c_override 0 +`define c_no_override 1 + +`define all1s {C_WIDTH{1'b1}} +`define all0s 'b0 +`define allXs {C_WIDTH{1'bx}} + +module C_REG_LD_V5_0 (D, G, GE, ACLR, ASET, AINIT, SCLR, SSET, SINIT, Q); + + parameter C_AINIT_VAL = ""; + parameter C_ENABLE_RLOCS = 1; + parameter C_HAS_ACLR = 0; + parameter C_HAS_AINIT = 0; + parameter C_HAS_ASET = 0; + parameter C_HAS_GE = 0; + parameter C_HAS_SCLR = 0; + parameter C_HAS_SINIT = 0; + parameter C_HAS_SSET = 0; + parameter C_SINIT_VAL = ""; + parameter C_SYNC_ENABLE = `c_override; + parameter C_SYNC_PRIORITY = `c_clear; + parameter C_WIDTH = 16; + + + input [C_WIDTH-1 : 0] D; + input G; + input GE; + input ACLR; + input ASET; + input AINIT; + input SCLR; + input SSET; + input SINIT; + output [C_WIDTH-1 : 0] Q; + + reg [C_WIDTH-1 : 0] data; + reg [C_WIDTH-1 : 0] datatmp; + // Internal values to drive signals when input is missing + wire intGE; + wire intACLR; + wire intASET; + wire intAINIT; + wire intSCLR; + wire intSSET; + wire intSINIT; + + wire [C_WIDTH-1 : 0] #1 Q = data; + + // Sort out default values for missing ports + + assign intACLR = defval(ACLR, C_HAS_ACLR, 0); + assign intASET = defval(ASET, C_HAS_ASET, 0); + assign intAINIT = defval(AINIT, C_HAS_AINIT, 0); + assign intSCLR = defval(SCLR, C_HAS_SCLR, 0); + assign intSSET = defval(SSET, C_HAS_SSET, 0); + assign intSINIT = defval(SINIT, C_HAS_SINIT, 0); + assign intGE = ((C_HAS_SCLR == 1 || C_HAS_SSET == 1 || C_HAS_SINIT == 1) && + (C_HAS_GE == 1) && (C_SYNC_ENABLE == `c_override) ? + (GE | intSCLR | intSSET | intSINIT) : ((C_HAS_GE == 1) ? GE : 1'b1)); + + reg lastintACLR; + reg lastintASET; + + reg [C_WIDTH-1 : 0] AIV; + reg [C_WIDTH-1 : 0] SIV; + + + integer i; + integer ASYNC_CTRL; + + initial + begin + ASYNC_CTRL = 1; + lastintACLR = 1'b0; + lastintASET = 1'b0; + AIV = to_bits(C_AINIT_VAL); + SIV = to_bits(C_SINIT_VAL); + if(C_HAS_ACLR === 1) + #1 data = `all0s; + else if(C_HAS_ASET === 1) + #1 data = `all1s; + else if(C_HAS_AINIT === 1) + #1 data = AIV; +// else if(C_HAS_SCLR === 1) +// #1 data = `all0s; +// else if(C_HAS_SSET === 1) +// #1 data = `all1s; +// else if(C_HAS_SINIT === 1) +// #1 data = SIV; + else + #1 data = AIV; + end + + always@(G or intGE or intACLR or intASET or intAINIT or intSCLR or intSSET or intSINIT or D) + begin + datatmp = data; + + for(i = 0; i < C_WIDTH; i = i + 1) + begin + if(intACLR === 1'b1) + datatmp[i] = 1'b0; + else if(intACLR === 1'b0 && intASET === 1'b1) + datatmp[i] = 1'b1; + else if(intAINIT === 1'b1) + datatmp[i] = AIV[i]; + else if(intACLR === 1'bx && intASET !== 1'b0) + datatmp[i] = 1'bx; + else if(intACLR != lastintACLR && lastintASET != intASET + && lastintACLR === 1'b1 && lastintASET === 1'b1 + && intACLR === 1'b0 && intASET === 1'b0) + datatmp[i] = 1'bx; + else + begin + ASYNC_CTRL = 0; + if(G === 1'b1) + begin + if((intGE !== 1'b0 || C_SYNC_ENABLE === 0) && + (C_SYNC_PRIORITY == 0 && intSSET === 1'bx && intSCLR !== 1'b0)) + begin + datatmp[i] = 1'bx; + ASYNC_CTRL = 1; + end + if((intGE !== 1'b0 || C_SYNC_ENABLE === 0) && + (C_SYNC_PRIORITY == 1 && intSSET !== 1'b0 && intSCLR === 1'bx)) + begin + datatmp[i] = 1'bx; + ASYNC_CTRL = 1; + end + if(intGE === 1'b1 && intSCLR !== 1'b1 && intSSET !== 1'b1 && intSINIT !== 1'b1 && ASYNC_CTRL == 0) + datatmp[i] = D[i]; + else if(intGE === 1'bx && datatmp[i] !== D[i] && intSCLR !== 1'b1 && intSSET !== 1'b1 && intSINIT !== 1'b1 && ASYNC_CTRL == 0) + datatmp[i] = 1'bx; + + if(intSINIT === 1'b1 && (intGE === 1'b1 || C_SYNC_ENABLE == 0) && ASYNC_CTRL == 0) + datatmp[i] = SIV[i]; + else if(intSINIT === 1'b1 && (intGE === 1'bx && C_SYNC_ENABLE == 1) && datatmp[i] !== SIV[i]) + datatmp[i] = 1'bx; + else if(intSINIT === 1'bx && (intGE !== 1'b0 || C_SYNC_ENABLE == 0) && datatmp[i] !== SIV[i]) + datatmp[i] = 1'bx; + + if(intSCLR === 1'b1 && (intGE === 1'b1 || C_SYNC_ENABLE == 0) && (C_SYNC_PRIORITY == 1 || intSSET === 1'b0) && ASYNC_CTRL == 0) + datatmp[i] = 1'b0; + else if(intSCLR === 1'b1 && (intGE === 1'bx && C_SYNC_ENABLE == 1) && datatmp[i] !== 1'b0 && (C_SYNC_PRIORITY == 1 || intSSET === 1'b0)) + datatmp[i] = 1'bx; + else if(intSCLR === 1'bx && (intGE !== 1'b0 || C_SYNC_ENABLE == 0) && datatmp[i] !== 1'b0 && (C_SYNC_PRIORITY == 1 || intSSET === 1'b0)) + datatmp[i] = 1'bx; + + if(intSSET === 1'b1 && (intGE === 1'b1 || C_SYNC_ENABLE == 0) && (C_SYNC_PRIORITY == 0 || intSCLR === 1'b0) && ASYNC_CTRL == 0) + datatmp[i] = 1'b1; + else if(intSSET === 1'b1 && (intGE === 1'bx && C_SYNC_ENABLE == 1) && datatmp[i] !== 1'b1 && (C_SYNC_PRIORITY == 0 || intSCLR === 1'b0)) + datatmp[i] = 1'bx; + else if(intSSET === 1'bx && (intGE !== 1'b0 || C_SYNC_ENABLE == 0) && datatmp[i] !== 1'b1 && (C_SYNC_PRIORITY == 0 || intSCLR === 1'b0)) + datatmp[i] = 1'bx; + end + else if(G === 1'bx) + begin + if((intGE !== 1'b0 || C_SYNC_ENABLE == 0) && (C_SYNC_PRIORITY == 0 && intSSET === 1'bx && intSCLR !== 1'b0)) + datatmp[i] = 1'bx; + else if((intGE !== 1'b0 || C_SYNC_ENABLE == 0) && (C_SYNC_PRIORITY == 1 && intSSET !== 1'b0 && intSCLR === 1'bx)) + datatmp[i] = 1'bx; + + if((intGE !== 1'b0 || (C_SYNC_ENABLE == 0 && (intSCLR !== 1'b0 || intSSET !== 1'b0 || intSINIT !== 1'b0))) && intSCLR !== 1'b1 && intSSET !== 1'b1 && intSINIT !== 1'b1 && datatmp[i] !== D[i]) + datatmp[i] = 1'bx; + + if(intSINIT !== 1'b0 && (intGE !== 1'b0 || C_SYNC_ENABLE == 0) && datatmp[i] !== SIV[i]) + datatmp[i] = 1'bx; + + if(intSCLR !== 1'b0 && (intGE !== 1'b0 || C_SYNC_ENABLE == 0) && (C_SYNC_PRIORITY == 1 || intSSET === 1'b0) && datatmp[i] !== 1'b0) + datatmp[i] = 1'bx; + + if(intSSET !== 1'b0 && (intGE !== 1'b0 || C_SYNC_ENABLE == 0) && (C_SYNC_PRIORITY == 0 || intSCLR === 1'b0) && datatmp[i] !== 1'b1) + datatmp[i] = 1'bx; + end + + if(intACLR === 1'b0 && intASET === 1'bx) + begin + if(datatmp[i] !== 1'b1) + begin + datatmp[i] = 1'bx; + ASYNC_CTRL = 1; + end + end + else if(intACLR === 1'bx && intASET === 1'b0) + begin + if(datatmp[i] !== 1'b0) + begin + datatmp[i] = 1'bx; + ASYNC_CTRL = 1; + end + end + else if(intAINIT === 1'bx) + begin + if(datatmp[i] !== AIV[i]) + begin + datatmp[i] = 1'bx; + ASYNC_CTRL = 1; + end + end + end + end + + data <= datatmp; + end + + + always@(intACLR or intASET) + begin + lastintACLR <= intACLR; + lastintASET <= intASET; + if($time != 0) + if(intACLR === 1'b0 && intASET === 1'b0 && lastintACLR !== 1'b0 && lastintASET !== 1'b0) // RACE + data <= `allXs; + end + + + function defval; + input i; + input hassig; + input val; + begin + if(hassig == 1) + defval = i; + else + defval = val; + end + endfunction + + function [C_WIDTH - 1 : 0] to_bits; + input [C_WIDTH*8 : 1] instring; + integer i; + integer non_null_string; + begin + non_null_string = 0; + for(i = C_WIDTH; i > 0; i = i - 1) + begin // Is the string empty? + if(instring[(i*8)] == 0 && + instring[(i*8)-1] == 0 && + instring[(i*8)-2] == 0 && + instring[(i*8)-3] == 0 && + instring[(i*8)-4] == 0 && + instring[(i*8)-5] == 0 && + instring[(i*8)-6] == 0 && + instring[(i*8)-7] == 0 && + non_null_string == 0) + non_null_string = 0; // Use the return value to flag a non-empty string + else + non_null_string = 1; // Non-null character! + end + if(non_null_string == 0) // String IS empty! Just return the value to be all '0's + begin + for(i = C_WIDTH; i > 0; i = i - 1) + to_bits[i-1] = 0; + end + else + begin + for(i = C_WIDTH; i > 0; i = i - 1) + begin // Is this character a '0'? (ASCII = 48 = 00110000) + if(instring[(i*8)] == 0 && + instring[(i*8)-1] == 0 && + instring[(i*8)-2] == 1 && + instring[(i*8)-3] == 1 && + instring[(i*8)-4] == 0 && + instring[(i*8)-5] == 0 && + instring[(i*8)-6] == 0 && + instring[(i*8)-7] == 0) + to_bits[i-1] = 0; + // Or is it a '1'? + else if(instring[(i*8)] == 0 && + instring[(i*8)-1] == 0 && + instring[(i*8)-2] == 1 && + instring[(i*8)-3] == 1 && + instring[(i*8)-4] == 0 && + instring[(i*8)-5] == 0 && + instring[(i*8)-6] == 0 && + instring[(i*8)-7] == 1) + to_bits[i-1] = 1; + // Or is it a ' '? (a null char - in which case insert a '0') + else if(instring[(i*8)] == 0 && + instring[(i*8)-1] == 0 && + instring[(i*8)-2] == 0 && + instring[(i*8)-3] == 0 && + instring[(i*8)-4] == 0 && + instring[(i*8)-5] == 0 && + instring[(i*8)-6] == 0 && + instring[(i*8)-7] == 0) + to_bits[i-1] = 0; + else + begin + $display("Error in %m at time %d ns: non-binary digit in string \"%s\"\nExiting simulation...", $time, instring); + $finish; + end + end + end + end + endfunction + +endmodule + +`undef c_set +`undef c_clear +`undef c_override +`undef c_no_override + +`undef all1s +`undef all0s +`undef allXs diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/C_REG_LD_V6_0.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/C_REG_LD_V6_0.v new file mode 100644 index 0000000..60e9256 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/C_REG_LD_V6_0.v @@ -0,0 +1,369 @@ +// Copyright(C) 2002 by Xilinx, Inc. All rights reserved. +// This text contains proprietary, confidential +// information of Xilinx, Inc., is distributed +// under license from Xilinx, Inc., and may be used, +// copied and/or disclosed only pursuant to the terms +// of a valid license agreement with Xilinx, Inc. This copyright +// notice must be retained as part of this text at all times. + + +/* $Id: C_REG_LD_V6_0.v,v 1.16 2008/09/08 20:06:05 akennedy Exp $ +-- +-- Filename - C_REG_LD_V6_0.v +-- Author - Xilinx +-- Creation - 21 Oct 1998 +-- +-- Description - This file contains the Verilog behavior for the baseblocks C_REG_LD_V6_0 module +*/ + +`timescale 1ns/10ps + +`define c_set 0 +`define c_clear 1 +`define c_override 0 +`define c_no_override 1 + +`define all1s {C_WIDTH{1'b1}} +`define all0s 'b0 +`define allXs {C_WIDTH{1'bx}} + +module C_REG_LD_V6_0 (D, G, GE, ACLR, ASET, AINIT, SCLR, SSET, SINIT, Q); + + parameter C_AINIT_VAL = ""; + parameter C_ENABLE_RLOCS = 1; + parameter C_HAS_ACLR = 0; + parameter C_HAS_AINIT = 0; + parameter C_HAS_ASET = 0; + parameter C_HAS_GE = 0; + parameter C_HAS_SCLR = 0; + parameter C_HAS_SINIT = 0; + parameter C_HAS_SSET = 0; + parameter C_SINIT_VAL = ""; + parameter C_SYNC_ENABLE = `c_override; + parameter C_SYNC_PRIORITY = `c_clear; + parameter C_WIDTH = 16; + + + input [C_WIDTH-1 : 0] D; + input G; + input GE; + input ACLR; + input ASET; + input AINIT; + input SCLR; + input SSET; + input SINIT; + output [C_WIDTH-1 : 0] Q; + + reg [C_WIDTH-1 : 0] data; + reg [C_WIDTH-1 : 0] datatmp; + // Internal values to drive signals when input is missing + wire intGE; + wire intACLR; + wire intASET; + wire intAINIT; + wire intSCLR; + wire intSSET; + wire intSINIT; + + wire [C_WIDTH-1 : 0] #1 Q = data; + + // Sort out default values for missing ports + + assign intACLR = defval(ACLR, C_HAS_ACLR, 0); + assign intASET = defval(ASET, C_HAS_ASET, 0); + assign intAINIT = defval(AINIT, C_HAS_AINIT, 0); + assign intSCLR = defval(SCLR, C_HAS_SCLR, 0); + assign intSSET = defval(SSET, C_HAS_SSET, 0); + assign intSINIT = defval(SINIT, C_HAS_SINIT, 0); + assign intGE = ((C_HAS_SCLR == 1 || C_HAS_SSET == 1 || C_HAS_SINIT == 1) && + (C_HAS_GE == 1) && (C_SYNC_ENABLE == `c_override) ? + (GE | intSCLR | intSSET | intSINIT) : ((C_HAS_GE == 1) ? GE : 1'b1)); + + reg lastintACLR; + reg lastintASET; + + reg [C_WIDTH-1 : 0] AIV; + reg [C_WIDTH-1 : 0] SIV; + + + integer i; + integer ASYNC_CTRL; + + initial + begin + ASYNC_CTRL = 1; + lastintACLR = 1'b0; + lastintASET = 1'b0; + AIV = to_bits(C_AINIT_VAL); + SIV = to_bits(C_SINIT_VAL); + if(C_HAS_ACLR === 1) + #1 data = `all0s; + else if(C_HAS_ASET === 1) + #1 data = `all1s; + else if(C_HAS_AINIT === 1) + #1 data = AIV; +// else if(C_HAS_SCLR === 1) +// #1 data = `all0s; +// else if(C_HAS_SSET === 1) +// #1 data = `all1s; +// else if(C_HAS_SINIT === 1) +// #1 data = SIV; + else + #1 data = AIV; + end + + always@(G or intGE or intACLR or intASET or intAINIT or intSCLR or intSSET or intSINIT or D) + begin + datatmp = data; + +// for(i = 0; i < C_WIDTH; i = i + 1) +// begin + if(intACLR === 1'b1) +// datatmp[i] = 1'b0; + datatmp = `all0s; + else if(intACLR === 1'b0 && intASET === 1'b1) +// datatmp[i] = 1'b1; + datatmp = `all1s; + else if(intAINIT === 1'b1) +// datatmp[i] = AIV[i]; + datatmp = AIV; + else if(intACLR === 1'bx && intASET !== 1'b0) +// datatmp[i] = 1'bx; + datatmp = `allXs; + else if(intACLR != lastintACLR && lastintASET != intASET + && lastintACLR === 1'b1 && lastintASET === 1'b1 + && intACLR === 1'b0 && intASET === 1'b0) +// datatmp[i] = 1'bx; + datatmp = `allXs; + else + begin + ASYNC_CTRL = 0; + if(G === 1'b1) + begin + if((intGE !== 1'b0 || C_SYNC_ENABLE === 0) && + (C_SYNC_PRIORITY == 0 && intSSET === 1'bx && intSCLR !== 1'b0)) + begin +// datatmp[i] = 1'bx; + datatmp = `allXs; + ASYNC_CTRL = 1; + end + if((intGE !== 1'b0 || C_SYNC_ENABLE === 0) && + (C_SYNC_PRIORITY == 1 && intSSET !== 1'b0 && intSCLR === 1'bx)) + begin +// datatmp[i] = 1'bx; + datatmp = `allXs; + ASYNC_CTRL = 1; + end + if(intGE === 1'b1 && intSCLR !== 1'b1 && intSSET !== 1'b1 && intSINIT !== 1'b1 && ASYNC_CTRL == 0) +// datatmp[i] = D[i]; + datatmp = D; +// else if(intGE === 1'bx && datatmp[i] !== D[i] && intSCLR !== 1'b1 && intSSET !== 1'b1 && intSINIT !== 1'b1 && ASYNC_CTRL == 0) + else if(intGE === 1'bx && intSCLR !== 1'b1 && intSSET !== 1'b1 && intSINIT !== 1'b1 && ASYNC_CTRL == 0) +// datatmp[i] = 1'bx; + datatmp = ~((~(datatmp ^ D) | `allXs) ^ datatmp); + + if(intSINIT === 1'b1 && (intGE === 1'b1 || C_SYNC_ENABLE == 0) && ASYNC_CTRL == 0) +// datatmp[i] = SIV[i]; + datatmp = SIV; +// else if(intSINIT === 1'b1 && (intGE === 1'bx && C_SYNC_ENABLE == 1) && datatmp[i] !== SIV[i]) + else if(intSINIT === 1'b1 && (intGE === 1'bx && C_SYNC_ENABLE == 1)) +// datatmp[i] = 1'bx; + datatmp = ~((~(datatmp ^ SIV) | `allXs) ^ datatmp); +// else if(intSINIT === 1'bx && (intGE !== 1'b0 || C_SYNC_ENABLE == 0) && datatmp[i] !== SIV[i]) + else if(intSINIT === 1'bx && (intGE !== 1'b0 || C_SYNC_ENABLE == 0)) +// datatmp[i] = 1'bx; + datatmp = ~((~(datatmp ^ SIV) | `allXs) ^ datatmp); + + if(intSCLR === 1'b1 && (intGE === 1'b1 || C_SYNC_ENABLE == 0) && (C_SYNC_PRIORITY == 1 || intSSET === 1'b0) && ASYNC_CTRL == 0) +// datatmp[i] = 1'b0; + datatmp = `all0s; +// else if(intSCLR === 1'b1 && (intGE === 1'bx && C_SYNC_ENABLE == 1) && datatmp[i] !== 1'b0 && (C_SYNC_PRIORITY == 1 || intSSET === 1'b0)) + else if(intSCLR === 1'b1 && (intGE === 1'bx && C_SYNC_ENABLE == 1) && (C_SYNC_PRIORITY == 1 || intSSET === 1'b0)) +// datatmp[i] = 1'bx; + datatmp = ~(~datatmp | `allXs); +// else if(intSCLR === 1'bx && (intGE !== 1'b0 || C_SYNC_ENABLE == 0) && datatmp[i] !== 1'b0 && (C_SYNC_PRIORITY == 1 || intSSET === 1'b0)) + else if(intSCLR === 1'bx && (intGE !== 1'b0 || C_SYNC_ENABLE == 0) && (C_SYNC_PRIORITY == 1 || intSSET === 1'b0)) +// datatmp[i] = 1'bx; + datatmp = ~(~datatmp | `allXs); + + if(intSSET === 1'b1 && (intGE === 1'b1 || C_SYNC_ENABLE == 0) && (C_SYNC_PRIORITY == 0 || intSCLR === 1'b0) && ASYNC_CTRL == 0) +// datatmp[i] = 1'b1; + datatmp = `all1s; +// else if(intSSET === 1'b1 && (intGE === 1'bx && C_SYNC_ENABLE == 1) && datatmp[i] !== 1'b1 && (C_SYNC_PRIORITY == 0 || intSCLR === 1'b0)) + else if(intSSET === 1'b1 && (intGE === 1'bx && C_SYNC_ENABLE == 1) && (C_SYNC_PRIORITY == 0 || intSCLR === 1'b0)) +// datatmp[i] = 1'bx; + datatmp = datatmp | `allXs; +// else if(intSSET === 1'bx && (intGE !== 1'b0 || C_SYNC_ENABLE == 0) && datatmp[i] !== 1'b1 && (C_SYNC_PRIORITY == 0 || intSCLR === 1'b0)) + else if(intSSET === 1'bx && (intGE !== 1'b0 || C_SYNC_ENABLE == 0) && (C_SYNC_PRIORITY == 0 || intSCLR === 1'b0)) +// datatmp[i] = 1'bx; + datatmp = datatmp | `allXs; + end + else if(G === 1'bx) + begin + if((intGE !== 1'b0 || C_SYNC_ENABLE == 0) && (C_SYNC_PRIORITY == 0 && intSSET === 1'bx && intSCLR !== 1'b0)) +// datatmp[i] = 1'bx; + datatmp = `allXs; + else if((intGE !== 1'b0 || C_SYNC_ENABLE == 0) && (C_SYNC_PRIORITY == 1 && intSSET !== 1'b0 && intSCLR === 1'bx)) +// datatmp[i] = 1'bx; + datatmp = `allXs; + +// if((intGE !== 1'b0 || (C_SYNC_ENABLE == 0 && (intSCLR !== 1'b0 || intSSET !== 1'b0 || intSINIT !== 1'b0))) && intSCLR !== 1'b1 && intSSET !== 1'b1 && intSINIT !== 1'b1 && datatmp[i] !== D[i]) + if((intGE !== 1'b0 || (C_SYNC_ENABLE == 0 && (intSCLR !== 1'b0 || intSSET !== 1'b0 || intSINIT !== 1'b0))) && intSCLR !== 1'b1 && intSSET !== 1'b1 && intSINIT !== 1'b1) +// datatmp[i] = 1'bx; + datatmp = ~((~(datatmp ^ D) | `allXs) ^ datatmp); + +// if(intSINIT !== 1'b0 && (intGE !== 1'b0 || C_SYNC_ENABLE == 0) && datatmp[i] !== SIV[i]) + if(intSINIT !== 1'b0 && (intGE !== 1'b0 || C_SYNC_ENABLE == 0)) +// datatmp[i] = 1'bx; + datatmp = ~((~(datatmp ^ SIV) | `allXs) ^ datatmp); + +// if(intSCLR !== 1'b0 && (intGE !== 1'b0 || C_SYNC_ENABLE == 0) && (C_SYNC_PRIORITY == 1 || intSSET === 1'b0) && datatmp[i] !== 1'b0) + if(intSCLR !== 1'b0 && (intGE !== 1'b0 || C_SYNC_ENABLE == 0) && (C_SYNC_PRIORITY == 1 || intSSET === 1'b0)) +// datatmp[i] = 1'bx; + datatmp = ~(~datatmp | `allXs); + +// if(intSSET !== 1'b0 && (intGE !== 1'b0 || C_SYNC_ENABLE == 0) && (C_SYNC_PRIORITY == 0 || intSCLR === 1'b0) && datatmp[i] !== 1'b1) + if(intSSET !== 1'b0 && (intGE !== 1'b0 || C_SYNC_ENABLE == 0) && (C_SYNC_PRIORITY == 0 || intSCLR === 1'b0)) +// datatmp[i] = 1'bx; + datatmp = datatmp | `allXs; + end + + if(intACLR === 1'b0 && intASET === 1'bx) + begin +/* if(datatmp[i] !== 1'b1) + begin + datatmp[i] = 1'bx; + ASYNC_CTRL = 1; + end*/ + ASYNC_CTRL = |(~datatmp) ? 1 : 0; + datatmp = datatmp | `allXs; + end + else if(intACLR === 1'bx && intASET === 1'b0) + begin +/* if(datatmp[i] !== 1'b0) + begin + datatmp[i] = 1'bx; + ASYNC_CTRL = 1; + end*/ + ASYNC_CTRL = |datatmp ? 1 : 0; + datatmp = datatmp & `allXs; + end + else if(intAINIT === 1'bx) + begin +/* if(datatmp[i] !== AIV[i]) + begin + datatmp[i] = 1'bx; + ASYNC_CTRL = 1; + end*/ + ASYNC_CTRL = |(datatmp ^ AIV) ? 1 : 0; + datatmp = ~((~(datatmp ^ AIV) | `allXs) ^ datatmp); + end + end +// end + + data <= datatmp; + end + + + always@(intACLR or intASET) + begin + lastintACLR <= intACLR; + lastintASET <= intASET; + if($time != 0) + if(intACLR === 1'b0 && intASET === 1'b0 && lastintACLR !== 1'b0 && lastintASET !== 1'b0) // RACE + data <= `allXs; + end + + + function defval; + input i; + input hassig; + input val; + begin + if(hassig == 1) + defval = i; + else + defval = val; + end + endfunction + + function [C_WIDTH - 1 : 0] to_bits; + input [C_WIDTH*8 : 1] instring; + integer i; + integer non_null_string; + begin + non_null_string = 0; + for(i = C_WIDTH; i > 0; i = i - 1) + begin // Is the string empty? + if(instring[(i*8)] == 0 && + instring[(i*8)-1] == 0 && + instring[(i*8)-2] == 0 && + instring[(i*8)-3] == 0 && + instring[(i*8)-4] == 0 && + instring[(i*8)-5] == 0 && + instring[(i*8)-6] == 0 && + instring[(i*8)-7] == 0 && + non_null_string == 0) + non_null_string = 0; // Use the return value to flag a non-empty string + else + non_null_string = 1; // Non-null character! + end + if(non_null_string == 0) // String IS empty! Just return the value to be all '0's + begin + for(i = C_WIDTH; i > 0; i = i - 1) + to_bits[i-1] = 0; + end + else + begin + for(i = C_WIDTH; i > 0; i = i - 1) + begin // Is this character a '0'? (ASCII = 48 = 00110000) + if(instring[(i*8)] == 0 && + instring[(i*8)-1] == 0 && + instring[(i*8)-2] == 1 && + instring[(i*8)-3] == 1 && + instring[(i*8)-4] == 0 && + instring[(i*8)-5] == 0 && + instring[(i*8)-6] == 0 && + instring[(i*8)-7] == 0) + to_bits[i-1] = 0; + // Or is it a '1'? + else if(instring[(i*8)] == 0 && + instring[(i*8)-1] == 0 && + instring[(i*8)-2] == 1 && + instring[(i*8)-3] == 1 && + instring[(i*8)-4] == 0 && + instring[(i*8)-5] == 0 && + instring[(i*8)-6] == 0 && + instring[(i*8)-7] == 1) + to_bits[i-1] = 1; + // Or is it a ' '? (a null char - in which case insert a '0') + else if(instring[(i*8)] == 0 && + instring[(i*8)-1] == 0 && + instring[(i*8)-2] == 0 && + instring[(i*8)-3] == 0 && + instring[(i*8)-4] == 0 && + instring[(i*8)-5] == 0 && + instring[(i*8)-6] == 0 && + instring[(i*8)-7] == 0) + to_bits[i-1] = 0; + else + begin + $display("Error in %m at time %d ns: non-binary digit in string \"%s\"\nExiting simulation...", $time, instring); + $finish; + end + end + end + end + endfunction + +endmodule + +`undef c_set +`undef c_clear +`undef c_override +`undef c_no_override + +`undef all1s +`undef all0s +`undef allXs diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/C_REG_LD_V7_0.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/C_REG_LD_V7_0.v new file mode 100644 index 0000000..b9a6b05 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/C_REG_LD_V7_0.v @@ -0,0 +1,398 @@ +// Copyright(C) 2003 by Xilinx, Inc. All rights reserved. +// This text/file contains proprietary, confidential +// information of Xilinx, Inc., is distributed under license +// from Xilinx, Inc., and may be used, copied and/or +// disclosed only pursuant to the terms of a valid license +// agreement with Xilinx, Inc. Xilinx hereby grants you +// a license to use this text/file solely for design, simulation, +// implementation and creation of design files limited +// to Xilinx devices or technologies. Use with non-Xilinx +// devices or technologies is expressly prohibited and +// immediately terminates your license unless covered by +// a separate agreement. +// +// Xilinx is providing this design, code, or information +// "as is" solely for use in developing programs and +// solutions for Xilinx devices. By providing this design, +// code, or information as one possible implementation of +// this feature, application or standard, Xilinx is making no +// representation that this implementation is free from any +// claims of infringement. You are responsible for +// obtaining any rights you may require for your implementation. +// Xilinx expressly disclaims any warranty whatsoever with +// respect to the adequacy of the implementation, including +// but not limited to any warranties or representations that this +// implementation is free from claims of infringement, implied +// warranties of merchantability or fitness for a particular +// purpose. +// +// Xilinx products are not intended for use in life support +// appliances, devices, or systems. Use in such applications are +// expressly prohibited. +// +// This copyright and support notice must be retained as part +// of this text at all times. (c) Copyright 1995-2003 Xilinx, Inc. +// All rights reserved. + + + +/* $Id: C_REG_LD_V7_0.v,v 1.13 2008/09/08 20:06:13 akennedy Exp $ +-- +-- Filename - C_REG_LD_V7_0.v +-- Author - Xilinx +-- Creation - 21 Oct 1998 +-- +-- Description - This file contains the Verilog behavior for the baseblocks C_REG_LD_V7_0 module +*/ + +`timescale 1ns/10ps + +`define c_set 0 +`define c_clear 1 +`define c_override 0 +`define c_no_override 1 + +`define all1s {C_WIDTH{1'b1}} +`define all0s 'b0 +`define allXs {C_WIDTH{1'bx}} + +module C_REG_LD_V7_0 (D, G, GE, ACLR, ASET, AINIT, SCLR, SSET, SINIT, Q); + + parameter C_AINIT_VAL = ""; + parameter C_ENABLE_RLOCS = 1; + parameter C_HAS_ACLR = 0; + parameter C_HAS_AINIT = 0; + parameter C_HAS_ASET = 0; + parameter C_HAS_GE = 0; + parameter C_HAS_SCLR = 0; + parameter C_HAS_SINIT = 0; + parameter C_HAS_SSET = 0; + parameter C_SINIT_VAL = ""; + parameter C_SYNC_ENABLE = `c_override; + parameter C_SYNC_PRIORITY = `c_clear; + parameter C_WIDTH = 16; + + + input [C_WIDTH-1 : 0] D; + input G; + input GE; + input ACLR; + input ASET; + input AINIT; + input SCLR; + input SSET; + input SINIT; + output [C_WIDTH-1 : 0] Q; + + reg [C_WIDTH-1 : 0] data; + reg [C_WIDTH-1 : 0] datatmp; + // Internal values to drive signals when input is missing + wire intGE; + wire intACLR; + wire intASET; + wire intAINIT; + wire intSCLR; + wire intSSET; + wire intSINIT; + + wire [C_WIDTH-1 : 0] #1 Q = data; + + // Sort out default values for missing ports + + assign intACLR = defval(ACLR, C_HAS_ACLR, 0); + assign intASET = defval(ASET, C_HAS_ASET, 0); + assign intAINIT = defval(AINIT, C_HAS_AINIT, 0); + assign intSCLR = defval(SCLR, C_HAS_SCLR, 0); + assign intSSET = defval(SSET, C_HAS_SSET, 0); + assign intSINIT = defval(SINIT, C_HAS_SINIT, 0); + assign intGE = ((C_HAS_SCLR == 1 || C_HAS_SSET == 1 || C_HAS_SINIT == 1) && + (C_HAS_GE == 1) && (C_SYNC_ENABLE == `c_override) ? + (GE | intSCLR | intSSET | intSINIT) : ((C_HAS_GE == 1) ? GE : 1'b1)); + + reg lastintACLR; + reg lastintASET; + + reg [C_WIDTH-1 : 0] AIV; + reg [C_WIDTH-1 : 0] SIV; + + + integer i; + integer ASYNC_CTRL; + + initial + begin + ASYNC_CTRL = 1; + lastintACLR = 1'b0; + lastintASET = 1'b0; + AIV = to_bits(C_AINIT_VAL); + SIV = to_bits(C_SINIT_VAL); + if(C_HAS_ACLR === 1) + #1 data = `all0s; + else if(C_HAS_ASET === 1) + #1 data = `all1s; + else if(C_HAS_AINIT === 1) + #1 data = AIV; +// else if(C_HAS_SCLR === 1) +// #1 data = `all0s; +// else if(C_HAS_SSET === 1) +// #1 data = `all1s; +// else if(C_HAS_SINIT === 1) +// #1 data = SIV; + else + #1 data = AIV; + end + + always@(G or intGE or intACLR or intASET or intAINIT or intSCLR or intSSET or intSINIT or D) + begin + datatmp = data; + +// for(i = 0; i < C_WIDTH; i = i + 1) +// begin + if(intACLR === 1'b1) +// datatmp[i] = 1'b0; + datatmp = `all0s; + else if(intACLR === 1'b0 && intASET === 1'b1) +// datatmp[i] = 1'b1; + datatmp = `all1s; + else if(intAINIT === 1'b1) +// datatmp[i] = AIV[i]; + datatmp = AIV; + else if(intACLR === 1'bx && intASET !== 1'b0) +// datatmp[i] = 1'bx; + datatmp = `allXs; + else if(intACLR != lastintACLR && lastintASET != intASET + && lastintACLR === 1'b1 && lastintASET === 1'b1 + && intACLR === 1'b0 && intASET === 1'b0) +// datatmp[i] = 1'bx; + datatmp = `allXs; + else + begin + ASYNC_CTRL = 0; + if(G === 1'b1) + begin + if((intGE !== 1'b0 || C_SYNC_ENABLE === 0) && + (C_SYNC_PRIORITY == 0 && intSSET === 1'bx && intSCLR !== 1'b0)) + begin +// datatmp[i] = 1'bx; + datatmp = `allXs; + ASYNC_CTRL = 1; + end + if((intGE !== 1'b0 || C_SYNC_ENABLE === 0) && + (C_SYNC_PRIORITY == 1 && intSSET !== 1'b0 && intSCLR === 1'bx)) + begin +// datatmp[i] = 1'bx; + datatmp = `allXs; + ASYNC_CTRL = 1; + end + if(intGE === 1'b1 && intSCLR !== 1'b1 && intSSET !== 1'b1 && intSINIT !== 1'b1 && ASYNC_CTRL == 0) +// datatmp[i] = D[i]; + datatmp = D; +// else if(intGE === 1'bx && datatmp[i] !== D[i] && intSCLR !== 1'b1 && intSSET !== 1'b1 && intSINIT !== 1'b1 && ASYNC_CTRL == 0) + else if(intGE === 1'bx && intSCLR !== 1'b1 && intSSET !== 1'b1 && intSINIT !== 1'b1 && ASYNC_CTRL == 0) +// datatmp[i] = 1'bx; + datatmp = ~((~(datatmp ^ D) | `allXs) ^ datatmp); + + if(intSINIT === 1'b1 && (intGE === 1'b1 || C_SYNC_ENABLE == 0) && ASYNC_CTRL == 0) +// datatmp[i] = SIV[i]; + datatmp = SIV; +// else if(intSINIT === 1'b1 && (intGE === 1'bx && C_SYNC_ENABLE == 1) && datatmp[i] !== SIV[i]) + else if(intSINIT === 1'b1 && (intGE === 1'bx && C_SYNC_ENABLE == 1)) +// datatmp[i] = 1'bx; + datatmp = ~((~(datatmp ^ SIV) | `allXs) ^ datatmp); +// else if(intSINIT === 1'bx && (intGE !== 1'b0 || C_SYNC_ENABLE == 0) && datatmp[i] !== SIV[i]) + else if(intSINIT === 1'bx && (intGE !== 1'b0 || C_SYNC_ENABLE == 0)) +// datatmp[i] = 1'bx; + datatmp = ~((~(datatmp ^ SIV) | `allXs) ^ datatmp); + + if(intSCLR === 1'b1 && (intGE === 1'b1 || C_SYNC_ENABLE == 0) && (C_SYNC_PRIORITY == 1 || intSSET === 1'b0) && ASYNC_CTRL == 0) +// datatmp[i] = 1'b0; + datatmp = `all0s; +// else if(intSCLR === 1'b1 && (intGE === 1'bx && C_SYNC_ENABLE == 1) && datatmp[i] !== 1'b0 && (C_SYNC_PRIORITY == 1 || intSSET === 1'b0)) + else if(intSCLR === 1'b1 && (intGE === 1'bx && C_SYNC_ENABLE == 1) && (C_SYNC_PRIORITY == 1 || intSSET === 1'b0)) +// datatmp[i] = 1'bx; + datatmp = ~(~datatmp | `allXs); +// else if(intSCLR === 1'bx && (intGE !== 1'b0 || C_SYNC_ENABLE == 0) && datatmp[i] !== 1'b0 && (C_SYNC_PRIORITY == 1 || intSSET === 1'b0)) + else if(intSCLR === 1'bx && (intGE !== 1'b0 || C_SYNC_ENABLE == 0) && (C_SYNC_PRIORITY == 1 || intSSET === 1'b0)) +// datatmp[i] = 1'bx; + datatmp = ~(~datatmp | `allXs); + + if(intSSET === 1'b1 && (intGE === 1'b1 || C_SYNC_ENABLE == 0) && (C_SYNC_PRIORITY == 0 || intSCLR === 1'b0) && ASYNC_CTRL == 0) +// datatmp[i] = 1'b1; + datatmp = `all1s; +// else if(intSSET === 1'b1 && (intGE === 1'bx && C_SYNC_ENABLE == 1) && datatmp[i] !== 1'b1 && (C_SYNC_PRIORITY == 0 || intSCLR === 1'b0)) + else if(intSSET === 1'b1 && (intGE === 1'bx && C_SYNC_ENABLE == 1) && (C_SYNC_PRIORITY == 0 || intSCLR === 1'b0)) +// datatmp[i] = 1'bx; + datatmp = datatmp | `allXs; +// else if(intSSET === 1'bx && (intGE !== 1'b0 || C_SYNC_ENABLE == 0) && datatmp[i] !== 1'b1 && (C_SYNC_PRIORITY == 0 || intSCLR === 1'b0)) + else if(intSSET === 1'bx && (intGE !== 1'b0 || C_SYNC_ENABLE == 0) && (C_SYNC_PRIORITY == 0 || intSCLR === 1'b0)) +// datatmp[i] = 1'bx; + datatmp = datatmp | `allXs; + end + else if(G === 1'bx) + begin + if((intGE !== 1'b0 || C_SYNC_ENABLE == 0) && (C_SYNC_PRIORITY == 0 && intSSET === 1'bx && intSCLR !== 1'b0)) +// datatmp[i] = 1'bx; + datatmp = `allXs; + else if((intGE !== 1'b0 || C_SYNC_ENABLE == 0) && (C_SYNC_PRIORITY == 1 && intSSET !== 1'b0 && intSCLR === 1'bx)) +// datatmp[i] = 1'bx; + datatmp = `allXs; + +// if((intGE !== 1'b0 || (C_SYNC_ENABLE == 0 && (intSCLR !== 1'b0 || intSSET !== 1'b0 || intSINIT !== 1'b0))) && intSCLR !== 1'b1 && intSSET !== 1'b1 && intSINIT !== 1'b1 && datatmp[i] !== D[i]) + if((intGE !== 1'b0 || (C_SYNC_ENABLE == 0 && (intSCLR !== 1'b0 || intSSET !== 1'b0 || intSINIT !== 1'b0))) && intSCLR !== 1'b1 && intSSET !== 1'b1 && intSINIT !== 1'b1) +// datatmp[i] = 1'bx; + datatmp = ~((~(datatmp ^ D) | `allXs) ^ datatmp); + +// if(intSINIT !== 1'b0 && (intGE !== 1'b0 || C_SYNC_ENABLE == 0) && datatmp[i] !== SIV[i]) + if(intSINIT !== 1'b0 && (intGE !== 1'b0 || C_SYNC_ENABLE == 0)) +// datatmp[i] = 1'bx; + datatmp = ~((~(datatmp ^ SIV) | `allXs) ^ datatmp); + +// if(intSCLR !== 1'b0 && (intGE !== 1'b0 || C_SYNC_ENABLE == 0) && (C_SYNC_PRIORITY == 1 || intSSET === 1'b0) && datatmp[i] !== 1'b0) + if(intSCLR !== 1'b0 && (intGE !== 1'b0 || C_SYNC_ENABLE == 0) && (C_SYNC_PRIORITY == 1 || intSSET === 1'b0)) +// datatmp[i] = 1'bx; + datatmp = ~(~datatmp | `allXs); + +// if(intSSET !== 1'b0 && (intGE !== 1'b0 || C_SYNC_ENABLE == 0) && (C_SYNC_PRIORITY == 0 || intSCLR === 1'b0) && datatmp[i] !== 1'b1) + if(intSSET !== 1'b0 && (intGE !== 1'b0 || C_SYNC_ENABLE == 0) && (C_SYNC_PRIORITY == 0 || intSCLR === 1'b0)) +// datatmp[i] = 1'bx; + datatmp = datatmp | `allXs; + end + + if(intACLR === 1'b0 && intASET === 1'bx) + begin +/* if(datatmp[i] !== 1'b1) + begin + datatmp[i] = 1'bx; + ASYNC_CTRL = 1; + end*/ + ASYNC_CTRL = |(~datatmp) ? 1 : 0; + datatmp = datatmp | `allXs; + end + else if(intACLR === 1'bx && intASET === 1'b0) + begin +/* if(datatmp[i] !== 1'b0) + begin + datatmp[i] = 1'bx; + ASYNC_CTRL = 1; + end*/ + ASYNC_CTRL = |datatmp ? 1 : 0; + datatmp = datatmp & `allXs; + end + else if(intAINIT === 1'bx) + begin +/* if(datatmp[i] !== AIV[i]) + begin + datatmp[i] = 1'bx; + ASYNC_CTRL = 1; + end*/ + ASYNC_CTRL = |(datatmp ^ AIV) ? 1 : 0; + datatmp = ~((~(datatmp ^ AIV) | `allXs) ^ datatmp); + end + end +// end + + data <= datatmp; + end + + + always@(intACLR or intASET) + begin + lastintACLR <= intACLR; + lastintASET <= intASET; + if($time != 0) + if(intACLR === 1'b0 && intASET === 1'b0 && lastintACLR !== 1'b0 && lastintASET !== 1'b0) // RACE + data <= `allXs; + end + + + function defval; + input i; + input hassig; + input val; + begin + if(hassig == 1) + defval = i; + else + defval = val; + end + endfunction + + function [C_WIDTH - 1 : 0] to_bits; + input [C_WIDTH*8 : 1] instring; + integer i; + integer non_null_string; + begin + non_null_string = 0; + for(i = C_WIDTH; i > 0; i = i - 1) + begin // Is the string empty? + if(instring[(i*8)] == 0 && + instring[(i*8)-1] == 0 && + instring[(i*8)-2] == 0 && + instring[(i*8)-3] == 0 && + instring[(i*8)-4] == 0 && + instring[(i*8)-5] == 0 && + instring[(i*8)-6] == 0 && + instring[(i*8)-7] == 0 && + non_null_string == 0) + non_null_string = 0; // Use the return value to flag a non-empty string + else + non_null_string = 1; // Non-null character! + end + if(non_null_string == 0) // String IS empty! Just return the value to be all '0's + begin + for(i = C_WIDTH; i > 0; i = i - 1) + to_bits[i-1] = 0; + end + else + begin + for(i = C_WIDTH; i > 0; i = i - 1) + begin // Is this character a '0'? (ASCII = 48 = 00110000) + if(instring[(i*8)] == 0 && + instring[(i*8)-1] == 0 && + instring[(i*8)-2] == 1 && + instring[(i*8)-3] == 1 && + instring[(i*8)-4] == 0 && + instring[(i*8)-5] == 0 && + instring[(i*8)-6] == 0 && + instring[(i*8)-7] == 0) + to_bits[i-1] = 0; + // Or is it a '1'? + else if(instring[(i*8)] == 0 && + instring[(i*8)-1] == 0 && + instring[(i*8)-2] == 1 && + instring[(i*8)-3] == 1 && + instring[(i*8)-4] == 0 && + instring[(i*8)-5] == 0 && + instring[(i*8)-6] == 0 && + instring[(i*8)-7] == 1) + to_bits[i-1] = 1; + // Or is it a ' '? (a null char - in which case insert a '0') + else if(instring[(i*8)] == 0 && + instring[(i*8)-1] == 0 && + instring[(i*8)-2] == 0 && + instring[(i*8)-3] == 0 && + instring[(i*8)-4] == 0 && + instring[(i*8)-5] == 0 && + instring[(i*8)-6] == 0 && + instring[(i*8)-7] == 0) + to_bits[i-1] = 0; + else + begin + $display("Error in %m at time %d ns: non-binary digit in string \"%s\"\nExiting simulation...", $time, instring); + $finish; + end + end + end + end + endfunction + +endmodule + +`undef c_set +`undef c_clear +`undef c_override +`undef c_no_override + +`undef all1s +`undef all0s +`undef allXs diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/C_SHIFT_FD_V4_0.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/C_SHIFT_FD_V4_0.v new file mode 100644 index 0000000..696c46b --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/C_SHIFT_FD_V4_0.v @@ -0,0 +1,205 @@ +/* $Id: C_SHIFT_FD_V4_0.v,v 1.11 2008/09/08 20:05:46 akennedy Exp $ +-- +-- Filename - C_SHIFT_FD_V4_0.v +-- Author - Xilinx +-- Creation - 29 June 1999 +-- +-- Description - This file contains the Verilog behavior for the baseblocks C_SHIFT_FD_V4_0 module +*/ + + + + + +`define c_set 0 +`define c_clear 1 +`define c_override 0 +`define c_no_override 1 +`define c_zeros 0 +`define c_ones 1 +`define c_lsb 2 +`define c_msb 3 +`define c_wrap 4 +`define c_sdin 5 +`define c_lsb_to_msb 0 +`define c_msb_to_lsb 1 +`define c_bidirectional 2 + + +`define all1s {C_WIDTH{1'b1}} +`define all0s 'b0 +`define allXs {C_WIDTH{1'bx}} + +module C_SHIFT_FD_V4_0 (LSB_2_MSB, SDIN, D, P_LOAD, CLK, CE, ACLR, ASET, AINIT, SCLR, SSET, SINIT, SDOUT, Q); + + parameter C_AINIT_VAL = ""; + parameter C_ENABLE_RLOCS = 1; + parameter C_FILL_DATA = `c_sdin; + parameter C_HAS_ACLR = 0; + parameter C_HAS_AINIT = 0; + parameter C_HAS_ASET = 0; + parameter C_HAS_CE = 0; + parameter C_HAS_D = 0; + parameter C_HAS_LSB_2_MSB = 0; + parameter C_HAS_Q = 1; + parameter C_HAS_SCLR = 0; + parameter C_HAS_SDIN = 1; + parameter C_HAS_SDOUT = 0; + parameter C_HAS_SINIT = 0; + parameter C_HAS_SSET = 0; + parameter C_SHIFT_TYPE = `c_lsb_to_msb; + parameter C_SINIT_VAL = ""; + parameter C_SYNC_ENABLE = `c_override; + parameter C_SYNC_PRIORITY = `c_clear; + parameter C_WIDTH = 16; + + //san 13/12/99 + parameter MUX_BUS_INIT_VAL = {C_WIDTH-(C_WIDTH>2?2:0){"0"}}; + + input LSB_2_MSB; + input SDIN; + input [C_WIDTH-1 : 0] D; + input P_LOAD; + input CLK; + input CE; + input ACLR; + input ASET; + input AINIT; + input SCLR; + input SSET; + input SINIT; + output SDOUT; + output [C_WIDTH-1 : 0] Q; + + // Internal values to drive signals when input is missing + wire intLSB_2_MSB; + wire intSDIN; + wire [C_WIDTH-1 : 0] intD; + wire intP_LOAD; + wire intCE; + wire intACLR; + wire intASET; + wire intAINIT; + wire intSCLR; + wire intSSET; + wire intSINIT; + wire intSDOUT; + wire [C_WIDTH-1 : 0] intQ; + + wire [C_WIDTH-1 : 0] Q = (C_HAS_Q == 1 ? intQ : `allXs); + wire SDOUT = (C_HAS_SDOUT == 1 ? intSDOUT : 1'bx); + + wire [C_WIDTH-1 : 0] regsin; + wire [C_WIDTH-1 : 0] regsout; + wire [3 : 0] MSBmuxi; + wire [3 : 0] LSBmuxi; + wire [1 : 0] muxc; + + wire MSBmuxo; + wire LSBmuxo; + wire [C_WIDTH-(C_WIDTH>2?2:0) : 1] shmuxo; + + wire [C_WIDTH-(C_WIDTH>2?2:0) : 1] shmuxi0; + wire [C_WIDTH-(C_WIDTH>2?2:0) : 1] shmuxi1; + wire [C_WIDTH-(C_WIDTH>2?2:0) : 1] shmuxi2; + wire [C_WIDTH-(C_WIDTH>2?2:0) : 1] shmuxi3; + // Sort out default values for missing ports + + assign intLSB_2_MSB = (C_SHIFT_TYPE == `c_bidirectional ? (C_HAS_LSB_2_MSB == 1 ? (C_WIDTH == 1 ? 1'b1 : LSB_2_MSB) : 1'bx) : (C_SHIFT_TYPE == `c_lsb_to_msb ? 1'b1 : (C_WIDTH == 1 ? 1'b1 :1'b0))); + assign intSDIN = (C_HAS_SDIN == 1 ? SDIN : (C_FILL_DATA == `c_zeros ? 1'b0 : (C_FILL_DATA == `c_ones ? 1'b1 : (C_FILL_DATA == `c_lsb ? regsout[0] : (C_FILL_DATA == `c_msb ? regsout[C_WIDTH-1] : (C_FILL_DATA == `c_wrap ? (intLSB_2_MSB === 1'b0 ? regsout[0] : regsout[C_WIDTH-1]) : 1'bx)))))); + assign intD = (C_HAS_D == 1 ? D : `allXs); + assign intP_LOAD = (C_HAS_D == 1 ? P_LOAD : 1'b0); + assign intCE = defval(CE, C_HAS_CE, 1); + assign intACLR = defval(ACLR, C_HAS_ACLR, 0); + assign intASET = defval(ASET, C_HAS_ASET, 0); + assign intAINIT = defval(AINIT, C_HAS_AINIT, 0); + assign intSCLR = defval(SCLR, C_HAS_SCLR, 0); + assign intSSET = defval(SSET, C_HAS_SSET, 0); + assign intSINIT = defval(SINIT, C_HAS_SINIT, 0); + + assign intSDOUT = (C_SHIFT_TYPE == `c_lsb_to_msb || C_SHIFT_TYPE == `c_bidirectional ? regsout[C_WIDTH-1] : regsout[0]); + assign intQ = (C_HAS_Q == 1 ? regsout : `allXs); + + assign LSBmuxi[0] = regsout[(C_WIDTH>1?1:0)]; + assign LSBmuxi[1] = intSDIN; + assign LSBmuxi[2] = intD[0]; + assign LSBmuxi[3] = intD[0]; + + assign MSBmuxi[0] = intSDIN; + assign MSBmuxi[1] = regsout[C_WIDTH-(C_WIDTH>1?2:1)]; + assign MSBmuxi[2] = intD[C_WIDTH-1]; + assign MSBmuxi[3] = intD[C_WIDTH-1]; + + assign shmuxi0 = regsout[C_WIDTH-1 : (C_WIDTH>2?2:0)]; + assign shmuxi1 = regsout[C_WIDTH-(C_WIDTH>2?3:1) : 0]; + assign shmuxi2 = intD[C_WIDTH-(C_WIDTH>2?2:1) : (C_WIDTH>2?1:0)]; + assign shmuxi3 = intD[C_WIDTH-(C_WIDTH>2?2:1) : (C_WIDTH>2?1:0)]; + + assign muxc[0] = intLSB_2_MSB; + assign muxc[1] = intP_LOAD; + + assign regsin[0] = LSBmuxo; + assign regsin[C_WIDTH-1] = (C_WIDTH == 1 ? LSBmuxo : MSBmuxo); + assign regsin[C_WIDTH-(C_WIDTH>2?2:1) : (C_WIDTH>2?1:0)] = (C_WIDTH == 1 ? LSBmuxo : (C_WIDTH == 2 ? {MSBmuxo, LSBmuxo} : shmuxo)); + + integer i, j, k; + integer m, unknown; + + // Register implements SR + C_REG_FD_V4_0 #(C_AINIT_VAL, C_ENABLE_RLOCS, C_HAS_ACLR, C_HAS_AINIT, C_HAS_ASET, + C_HAS_CE, C_HAS_SCLR, C_HAS_SINIT, C_HAS_SSET, + C_SINIT_VAL, C_SYNC_ENABLE, C_SYNC_PRIORITY, C_WIDTH) + shreg (.D(regsin), .CLK(CLK), .CE(intCE), .ACLR(intACLR), .ASET(intASET), + .AINIT(intAINIT), .SCLR(intSCLR), .SSET(intSSET), .SINIT(intSINIT), + .Q(regsout)); + + // Muxes to steer data + C_MUX_BIT_V4_0 #("0000", 1, 0, 0, 0, + 0, 1, 0, 0, 0, 0, + 4, 0, 0, 2, "0000", 0, 0) + MSBmux (.M(MSBmuxi), .S(muxc), .O(MSBmuxo)); // Feeds regsin[C_WIDTH-1] + + C_MUX_BIT_V4_0 #("0000", 1, 0, 0, 0, + 0, 1, 0, 0, 0, 0, + 4, 0, 0, 2, "0000", 0, 0) + LSBmux(.M(LSBmuxi), .S(muxc), .O(LSBmuxo)); // Feeds regsin[0]; + + //Edited SAN 13/12/99 //Added extra latency parameter, nritchie 15/9/00 + C_MUX_BUS_V4_0 #(MUX_BUS_INIT_VAL, 1, 0, 0, 0, + 0, 0, 1, 0, 0, 0, 0, + 4, 0, 0, 2, MUX_BUS_INIT_VAL, 0, 0, C_WIDTH-(C_WIDTH>2?2:0)) + shmux (.MA(shmuxi0), .MB(shmuxi1), .MC(shmuxi2), .MD(shmuxi3), .S(muxc), .O(shmuxo)); // Feeds regsin[C_WIDTH-2 : 1] + + + function defval; + input i; + input hassig; + input val; + begin + if(hassig == 1) + defval = i; + else + defval = val; + end + endfunction + +endmodule + +`undef c_set +`undef c_clear +`undef c_override +`undef c_no_override +`undef c_zeros +`undef c_ones +`undef c_lsb +`undef c_msb +`undef c_wrap +`undef c_sdin +`undef c_lsb_to_msb +`undef c_msb_to_lsb +`undef c_bidirectional + +`undef all1s +`undef all0s +`undef allXs + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/C_SHIFT_FD_V5_0.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/C_SHIFT_FD_V5_0.v new file mode 100644 index 0000000..c4bd9e6 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/C_SHIFT_FD_V5_0.v @@ -0,0 +1,219 @@ +/* $Id: C_SHIFT_FD_V5_0.v,v 1.17 2008/09/08 20:05:56 akennedy Exp $ +-- +-- Filename - C_SHIFT_FD_V5_0.v +-- Author - Xilinx +-- Creation - 29 June 1999 +-- +-- Description - This file contains the Verilog behavior for the baseblocks C_SHIFT_FD_V5_0 module +*/ + +`timescale 1ns/10ps + +`define c_set 0 +`define c_clear 1 +`define c_override 0 +`define c_no_override 1 +`define c_zeros 0 +`define c_ones 1 +`define c_lsb 2 +`define c_msb 3 +`define c_wrap 4 +`define c_sdin 5 +`define c_lsb_to_msb 0 +`define c_msb_to_lsb 1 +`define c_bidirectional 2 + + +`define all1s {C_WIDTH{1'b1}} +`define all0s 'b0 +`define allXs {C_WIDTH{1'bx}} + +module C_SHIFT_FD_V5_0 (LSB_2_MSB, SDIN, D, P_LOAD, CLK, CE, ACLR, ASET, AINIT, SCLR, SSET, SINIT, SDOUT, Q); + + parameter C_AINIT_VAL = ""; + parameter C_ENABLE_RLOCS = 1; + parameter C_FILL_DATA = `c_sdin; + parameter C_HAS_ACLR = 0; + parameter C_HAS_AINIT = 0; + parameter C_HAS_ASET = 0; + parameter C_HAS_CE = 0; + parameter C_HAS_D = 0; + parameter C_HAS_LSB_2_MSB = 0; + parameter C_HAS_Q = 1; + parameter C_HAS_SCLR = 0; + parameter C_HAS_SDIN = 1; + parameter C_HAS_SDOUT = 0; + parameter C_HAS_SINIT = 0; + parameter C_HAS_SSET = 0; + parameter C_SHIFT_TYPE = `c_lsb_to_msb; + parameter C_SINIT_VAL = ""; + parameter C_SYNC_ENABLE = `c_override; + parameter C_SYNC_PRIORITY = `c_clear; + parameter C_WIDTH = 16; + + //san 13/12/99 + parameter MUX_BUS_INIT_VAL = {C_WIDTH-(C_WIDTH>2?2:0){"0"}}; + + input LSB_2_MSB; + input SDIN; + input [C_WIDTH-1 : 0] D; + input P_LOAD; + input CLK; + input CE; + input ACLR; + input ASET; + input AINIT; + input SCLR; + input SSET; + input SINIT; + output SDOUT; + output [C_WIDTH-1 : 0] Q; + + // Internal values to drive signals when input is missing + wire intLSB_2_MSB; + wire intSDIN; + wire [C_WIDTH-1 : 0] intD; + wire intP_LOAD; + wire intCE; + wire intACLR; + wire intASET; + wire intAINIT; + wire intSCLR; + wire intSSET; + wire intSINIT; + wire intSDOUT; + wire [C_WIDTH-1 : 0] intQ; + + wire [C_WIDTH-1 : 0] Q = (C_HAS_Q == 1 ? intQ : `allXs); + wire SDOUT = (C_HAS_SDOUT == 1 ? intSDOUT : 1'bx); + + wire [C_WIDTH-1 : 0] regsin; + wire [C_WIDTH-1 : 0] regsout; + wire [3 : 0] MSBmuxi; + wire [3 : 0] LSBmuxi; + wire [1 : 0] muxc; + + wire MSBmuxo; + wire LSBmuxo; + wire [C_WIDTH-(C_WIDTH>2?2:0) : 1] shmuxo; + + wire [C_WIDTH-(C_WIDTH>2?2:0) : 1] shmuxi0; + wire [C_WIDTH-(C_WIDTH>2?2:0) : 1] shmuxi1; + wire [C_WIDTH-(C_WIDTH>2?2:0) : 1] shmuxi2; + wire [C_WIDTH-(C_WIDTH>2?2:0) : 1] shmuxi3; + // Sort out default values for missing ports + + assign intLSB_2_MSB = (C_SHIFT_TYPE == `c_bidirectional ? (C_HAS_LSB_2_MSB == 1 ? (C_WIDTH == 1 ? 1'b1 : LSB_2_MSB) : 1'bx) : (C_SHIFT_TYPE == `c_lsb_to_msb ? 1'b1 : (C_WIDTH == 1 ? 1'b1 :1'b0))); + assign intSDIN = (C_HAS_SDIN == 1 ? SDIN : (C_FILL_DATA == `c_zeros ? 1'b0 : (C_FILL_DATA == `c_ones ? 1'b1 : (C_FILL_DATA == `c_lsb ? regsout[0] : (C_FILL_DATA == `c_msb ? regsout[C_WIDTH-1] : (C_FILL_DATA == `c_wrap ? (intLSB_2_MSB === 1'b0 ? regsout[0] : regsout[C_WIDTH-1]) : 1'bx)))))); + assign intD = (C_HAS_D == 1 ? D : `allXs); + assign intP_LOAD = (C_HAS_D == 1 ? P_LOAD : 1'b0); + assign intCE = defval(CE, C_HAS_CE, 1); + assign intACLR = defval(ACLR, C_HAS_ACLR, 0); + assign intASET = defval(ASET, C_HAS_ASET, 0); + assign intAINIT = defval(AINIT, C_HAS_AINIT, 0); + assign intSCLR = defval(SCLR, C_HAS_SCLR, 0); + assign intSSET = defval(SSET, C_HAS_SSET, 0); + assign intSINIT = defval(SINIT, C_HAS_SINIT, 0); + + assign intSDOUT = (C_SHIFT_TYPE == `c_lsb_to_msb || C_SHIFT_TYPE == `c_bidirectional ? regsout[C_WIDTH-1] : regsout[0]); + assign intQ = (C_HAS_Q == 1 ? regsout : `allXs); + + assign LSBmuxi[0] = regsout[(C_WIDTH>1?1:0)]; + assign LSBmuxi[1] = intSDIN; + assign LSBmuxi[2] = intD[0]; + assign LSBmuxi[3] = intD[0]; + + assign MSBmuxi[0] = intSDIN; + assign MSBmuxi[1] = regsout[C_WIDTH-(C_WIDTH>1?2:1)]; + assign MSBmuxi[2] = intD[C_WIDTH-1]; + assign MSBmuxi[3] = intD[C_WIDTH-1]; + + assign shmuxi0 = regsout[C_WIDTH-1 : (C_WIDTH>2?2:0)]; + assign shmuxi1 = regsout[C_WIDTH-(C_WIDTH>2?3:1) : 0]; + assign shmuxi2 = intD[C_WIDTH-(C_WIDTH>2?2:1) : (C_WIDTH>2?1:0)]; + assign shmuxi3 = intD[C_WIDTH-(C_WIDTH>2?2:1) : (C_WIDTH>2?1:0)]; + + assign muxc[0] = intLSB_2_MSB; + assign muxc[1] = intP_LOAD; + + assign regsin[0] = LSBmuxo; + assign regsin[C_WIDTH-1] = (C_WIDTH == 1 ? LSBmuxo : MSBmuxo); + assign regsin[C_WIDTH-(C_WIDTH>2?2:1) : (C_WIDTH>2?1:0)] = (C_WIDTH == 1 ? LSBmuxo : (C_WIDTH == 2 ? {MSBmuxo, LSBmuxo} : shmuxo)); + + integer i, j, k; + integer m, unknown; + + // Register implements SR + C_REG_FD_V5_0 #(C_AINIT_VAL, C_ENABLE_RLOCS, C_HAS_ACLR, C_HAS_AINIT, C_HAS_ASET, + C_HAS_CE, C_HAS_SCLR, C_HAS_SINIT, C_HAS_SSET, + C_SINIT_VAL, C_SYNC_ENABLE, C_SYNC_PRIORITY, C_WIDTH) + shreg (.D(regsin), .CLK(CLK), .CE(intCE), .ACLR(intACLR), .ASET(intASET), + .AINIT(intAINIT), .SCLR(intSCLR), .SSET(intSSET), .SINIT(intSINIT), + .Q(regsout)); + + // Muxes to steer data + C_MUX_BIT_V5_0 #("0000", 1, 0, 0, 0, + 0, 1, 0, 0, 0, 0, + 4, 0, 0, 2, "0000", 0, 0) + MSBmux (.M(MSBmuxi), .S(muxc), + .CLK(), .CE(), + .ACLR(), .ASET(), .AINIT(), + .SCLR(), .SSET(), .SINIT(), + .O(MSBmuxo), .Q()); // Feeds regsin[C_WIDTH-1] + + C_MUX_BIT_V5_0 #("0000", 1, 0, 0, 0, + 0, 1, 0, 0, 0, 0, + 4, 0, 0, 2, "0000", 0, 0) + LSBmux(.M(LSBmuxi), .S(muxc), + .CLK(), .CE(), + .ACLR(), .ASET(), .AINIT(), + .SCLR(), .SSET(), .SINIT(), + .O(LSBmuxo), .Q()); // Feeds regsin[0]; + + //Edited SAN 13/12/99 //Added extra latency parameter, nritchie 15/9/00 + C_MUX_BUS_V5_0 #(MUX_BUS_INIT_VAL, 1, 0, 0, 0, + 0, 0, 1, 0, 0, 0, 0, + 4, 0, 0, 2, MUX_BUS_INIT_VAL, 0, 0, C_WIDTH-(C_WIDTH>2?2:0)) + shmux (.MA(shmuxi0), .MB(shmuxi1), .MC(shmuxi2), .MD(shmuxi3), .ME(), .MF(), .MG(), .MH(), + .MAA(), .MAB(), .MAC(), .MAD(), .MAE(), .MAF(), .MAG(), .MAH(), + .MBA(), .MBB(), .MBC(), .MBD(), .MBE(), .MBF(), .MBG(), .MBH(), + .MCA(), .MCB(), .MCC(), .MCD(), .MCE(), .MCF(), .MCG(), .MCH(), + .S(muxc), + .CLK(), .CE(), .EN(), + .ACLR(), .ASET(), .AINIT(), + .SCLR(), .SSET(), .SINIT(), + .O(shmuxo), .Q()); // Feeds regsin[C_WIDTH-2 : 1] + + + function defval; + input i; + input hassig; + input val; + begin + if(hassig == 1) + defval = i; + else + defval = val; + end + endfunction + +endmodule + +`undef c_set +`undef c_clear +`undef c_override +`undef c_no_override +`undef c_zeros +`undef c_ones +`undef c_lsb +`undef c_msb +`undef c_wrap +`undef c_sdin +`undef c_lsb_to_msb +`undef c_msb_to_lsb +`undef c_bidirectional + +`undef all1s +`undef all0s +`undef allXs + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/C_SHIFT_FD_V6_0.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/C_SHIFT_FD_V6_0.v new file mode 100644 index 0000000..2c2466f --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/C_SHIFT_FD_V6_0.v @@ -0,0 +1,228 @@ +// Copyright(C) 2002 by Xilinx, Inc. All rights reserved. +// This text contains proprietary, confidential +// information of Xilinx, Inc., is distributed +// under license from Xilinx, Inc., and may be used, +// copied and/or disclosed only pursuant to the terms +// of a valid license agreement with Xilinx, Inc. This copyright +// notice must be retained as part of this text at all times. + + +/* $Id: C_SHIFT_FD_V6_0.v,v 1.16 2008/09/08 20:06:05 akennedy Exp $ +-- +-- Filename - C_SHIFT_FD_V6_0.v +-- Author - Xilinx +-- Creation - 29 June 1999 +-- +-- Description - This file contains the Verilog behavior for the baseblocks C_SHIFT_FD_V6_0 module +*/ + +`timescale 1ns/10ps + +`define c_set 0 +`define c_clear 1 +`define c_override 0 +`define c_no_override 1 +`define c_zeros 0 +`define c_ones 1 +`define c_lsb 2 +`define c_msb 3 +`define c_wrap 4 +`define c_sdin 5 +`define c_lsb_to_msb 0 +`define c_msb_to_lsb 1 +`define c_bidirectional 2 + + +`define all1s {C_WIDTH{1'b1}} +`define all0s 'b0 +`define allXs {C_WIDTH{1'bx}} + +module C_SHIFT_FD_V6_0 (LSB_2_MSB, SDIN, D, P_LOAD, CLK, CE, ACLR, ASET, AINIT, SCLR, SSET, SINIT, SDOUT, Q); + + parameter C_AINIT_VAL = ""; + parameter C_ENABLE_RLOCS = 1; + parameter C_FILL_DATA = `c_sdin; + parameter C_HAS_ACLR = 0; + parameter C_HAS_AINIT = 0; + parameter C_HAS_ASET = 0; + parameter C_HAS_CE = 0; + parameter C_HAS_D = 0; + parameter C_HAS_LSB_2_MSB = 0; + parameter C_HAS_Q = 1; + parameter C_HAS_SCLR = 0; + parameter C_HAS_SDIN = 1; + parameter C_HAS_SDOUT = 0; + parameter C_HAS_SINIT = 0; + parameter C_HAS_SSET = 0; + parameter C_SHIFT_TYPE = `c_lsb_to_msb; + parameter C_SINIT_VAL = ""; + parameter C_SYNC_ENABLE = `c_override; + parameter C_SYNC_PRIORITY = `c_clear; + parameter C_WIDTH = 16; + + //san 13/12/99 + parameter MUX_BUS_INIT_VAL = {C_WIDTH-(C_WIDTH>2?2:0){"0"}}; + + input LSB_2_MSB; + input SDIN; + input [C_WIDTH-1 : 0] D; + input P_LOAD; + input CLK; + input CE; + input ACLR; + input ASET; + input AINIT; + input SCLR; + input SSET; + input SINIT; + output SDOUT; + output [C_WIDTH-1 : 0] Q; + + // Internal values to drive signals when input is missing + wire intLSB_2_MSB; + wire intSDIN; + wire [C_WIDTH-1 : 0] intD; + wire intP_LOAD; + wire intCE; + wire intACLR; + wire intASET; + wire intAINIT; + wire intSCLR; + wire intSSET; + wire intSINIT; + wire intSDOUT; + wire [C_WIDTH-1 : 0] intQ; + + wire [C_WIDTH-1 : 0] Q = (C_HAS_Q == 1 ? intQ : `allXs); + wire SDOUT = (C_HAS_SDOUT == 1 ? intSDOUT : 1'bx); + + wire [C_WIDTH-1 : 0] regsin; + wire [C_WIDTH-1 : 0] regsout; + wire [3 : 0] MSBmuxi; + wire [3 : 0] LSBmuxi; + wire [1 : 0] muxc; + + wire MSBmuxo; + wire LSBmuxo; + wire [C_WIDTH-(C_WIDTH>2?2:0) : 1] shmuxo; + + wire [C_WIDTH-(C_WIDTH>2?2:0) : 1] shmuxi0; + wire [C_WIDTH-(C_WIDTH>2?2:0) : 1] shmuxi1; + wire [C_WIDTH-(C_WIDTH>2?2:0) : 1] shmuxi2; + wire [C_WIDTH-(C_WIDTH>2?2:0) : 1] shmuxi3; + // Sort out default values for missing ports + + assign intLSB_2_MSB = (C_SHIFT_TYPE == `c_bidirectional ? (C_HAS_LSB_2_MSB == 1 ? (C_WIDTH == 1 ? 1'b1 : LSB_2_MSB) : 1'bx) : (C_SHIFT_TYPE == `c_lsb_to_msb ? 1'b1 : (C_WIDTH == 1 ? 1'b1 :1'b0))); + assign intSDIN = (C_HAS_SDIN == 1 ? SDIN : (C_FILL_DATA == `c_zeros ? 1'b0 : (C_FILL_DATA == `c_ones ? 1'b1 : (C_FILL_DATA == `c_lsb ? regsout[0] : (C_FILL_DATA == `c_msb ? regsout[C_WIDTH-1] : (C_FILL_DATA == `c_wrap ? (intLSB_2_MSB === 1'b0 ? regsout[0] : regsout[C_WIDTH-1]) : 1'bx)))))); + assign intD = (C_HAS_D == 1 ? D : `allXs); + assign intP_LOAD = (C_HAS_D == 1 ? P_LOAD : 1'b0); + assign intCE = defval(CE, C_HAS_CE, 1); + assign intACLR = defval(ACLR, C_HAS_ACLR, 0); + assign intASET = defval(ASET, C_HAS_ASET, 0); + assign intAINIT = defval(AINIT, C_HAS_AINIT, 0); + assign intSCLR = defval(SCLR, C_HAS_SCLR, 0); + assign intSSET = defval(SSET, C_HAS_SSET, 0); + assign intSINIT = defval(SINIT, C_HAS_SINIT, 0); + + assign intSDOUT = (C_SHIFT_TYPE == `c_lsb_to_msb || C_SHIFT_TYPE == `c_bidirectional ? regsout[C_WIDTH-1] : regsout[0]); + assign intQ = (C_HAS_Q == 1 ? regsout : `allXs); + + assign LSBmuxi[0] = regsout[(C_WIDTH>1?1:0)]; + assign LSBmuxi[1] = intSDIN; + assign LSBmuxi[2] = intD[0]; + assign LSBmuxi[3] = intD[0]; + + assign MSBmuxi[0] = intSDIN; + assign MSBmuxi[1] = regsout[C_WIDTH-(C_WIDTH>1?2:1)]; + assign MSBmuxi[2] = intD[C_WIDTH-1]; + assign MSBmuxi[3] = intD[C_WIDTH-1]; + + assign shmuxi0 = regsout[C_WIDTH-1 : (C_WIDTH>2?2:0)]; + assign shmuxi1 = regsout[C_WIDTH-(C_WIDTH>2?3:1) : 0]; + assign shmuxi2 = intD[C_WIDTH-(C_WIDTH>2?2:1) : (C_WIDTH>2?1:0)]; + assign shmuxi3 = intD[C_WIDTH-(C_WIDTH>2?2:1) : (C_WIDTH>2?1:0)]; + + assign muxc[0] = intLSB_2_MSB; + assign muxc[1] = intP_LOAD; + + assign regsin[0] = LSBmuxo; + assign regsin[C_WIDTH-1] = (C_WIDTH == 1 ? LSBmuxo : MSBmuxo); + assign regsin[C_WIDTH-(C_WIDTH>2?2:1) : (C_WIDTH>2?1:0)] = (C_WIDTH == 1 ? LSBmuxo : (C_WIDTH == 2 ? {MSBmuxo, LSBmuxo} : shmuxo)); + + integer i, j, k; + integer m, unknown; + + // Register implements SR + C_REG_FD_V6_0 #(C_AINIT_VAL, C_ENABLE_RLOCS, C_HAS_ACLR, C_HAS_AINIT, C_HAS_ASET, + C_HAS_CE, C_HAS_SCLR, C_HAS_SINIT, C_HAS_SSET, + C_SINIT_VAL, C_SYNC_ENABLE, C_SYNC_PRIORITY, C_WIDTH) + shreg (.D(regsin), .CLK(CLK), .CE(intCE), .ACLR(intACLR), .ASET(intASET), + .AINIT(intAINIT), .SCLR(intSCLR), .SSET(intSSET), .SINIT(intSINIT), + .Q(regsout)); + + // Muxes to steer data + C_MUX_BIT_V6_0 #("0000", 1, 0, 0, 0, + 0, 1, 0, 0, 0, 0, + 0, 4, 0, 0, 2, "0000", 0, 0) + MSBmux (.M(MSBmuxi), .S(muxc), + .CLK(), .CE(), + .ACLR(), .ASET(), .AINIT(), + .SCLR(), .SSET(), .SINIT(), + .O(MSBmuxo), .Q()); // Feeds regsin[C_WIDTH-1] + + C_MUX_BIT_V6_0 #("0000", 1, 0, 0, 0, + 0, 1, 0, 0, 0, 0, + 0, 4, 0, 0, 2, "0000", 0, 0) + LSBmux(.M(LSBmuxi), .S(muxc), + .CLK(), .CE(), + .ACLR(), .ASET(), .AINIT(), + .SCLR(), .SSET(), .SINIT(), + .O(LSBmuxo), .Q()); // Feeds regsin[0]; + + //Edited SAN 13/12/99 //Added extra latency parameter, nritchie 15/9/00 + C_MUX_BUS_V6_0 #(MUX_BUS_INIT_VAL, 1, 0, 0, 0, + 0, 0, 1, 0, 0, 0, 0, + 0, 4, 0, 0, 2, MUX_BUS_INIT_VAL, 0, 0, C_WIDTH-(C_WIDTH>2?2:0)) + shmux (.MA(shmuxi0), .MB(shmuxi1), .MC(shmuxi2), .MD(shmuxi3), .ME(), .MF(), .MG(), .MH(), + .MAA(), .MAB(), .MAC(), .MAD(), .MAE(), .MAF(), .MAG(), .MAH(), + .MBA(), .MBB(), .MBC(), .MBD(), .MBE(), .MBF(), .MBG(), .MBH(), + .MCA(), .MCB(), .MCC(), .MCD(), .MCE(), .MCF(), .MCG(), .MCH(), + .S(muxc), + .CLK(), .CE(), .EN(), + .ACLR(), .ASET(), .AINIT(), + .SCLR(), .SSET(), .SINIT(), + .O(shmuxo), .Q()); // Feeds regsin[C_WIDTH-2 : 1] + + + function defval; + input i; + input hassig; + input val; + begin + if(hassig == 1) + defval = i; + else + defval = val; + end + endfunction + +endmodule + +`undef c_set +`undef c_clear +`undef c_override +`undef c_no_override +`undef c_zeros +`undef c_ones +`undef c_lsb +`undef c_msb +`undef c_wrap +`undef c_sdin +`undef c_lsb_to_msb +`undef c_msb_to_lsb +`undef c_bidirectional + +`undef all1s +`undef all0s +`undef allXs + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/C_SHIFT_FD_V7_0.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/C_SHIFT_FD_V7_0.v new file mode 100644 index 0000000..6f320bc --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/C_SHIFT_FD_V7_0.v @@ -0,0 +1,256 @@ +// Copyright(C) 2003 by Xilinx, Inc. All rights reserved. +// This text/file contains proprietary, confidential +// information of Xilinx, Inc., is distributed under license +// from Xilinx, Inc., and may be used, copied and/or +// disclosed only pursuant to the terms of a valid license +// agreement with Xilinx, Inc. Xilinx hereby grants you +// a license to use this text/file solely for design, simulation, +// implementation and creation of design files limited +// to Xilinx devices or technologies. Use with non-Xilinx +// devices or technologies is expressly prohibited and +// immediately terminates your license unless covered by +// a separate agreement. +// +// Xilinx is providing this design, code, or information +// "as is" solely for use in developing programs and +// solutions for Xilinx devices. By providing this design, +// code, or information as one possible implementation of +// this feature, application or standard, Xilinx is making no +// representation that this implementation is free from any +// claims of infringement. You are responsible for +// obtaining any rights you may require for your implementation. +// Xilinx expressly disclaims any warranty whatsoever with +// respect to the adequacy of the implementation, including +// but not limited to any warranties or representations that this +// implementation is free from claims of infringement, implied +// warranties of merchantability or fitness for a particular +// purpose. +// +// Xilinx products are not intended for use in life support +// appliances, devices, or systems. Use in such applications are +// expressly prohibited. +// +// This copyright and support notice must be retained as part +// of this text at all times. (c) Copyright 1995-2003 Xilinx, Inc. +// All rights reserved. + + +/* $Id: C_SHIFT_FD_V7_0.v,v 1.13 2008/09/08 20:06:14 akennedy Exp $ +-- +-- Filename - C_SHIFT_FD_V7_0.v +-- Author - Xilinx +-- Creation - 29 June 1999 +-- +-- Description - This file contains the Verilog behavior for the baseblocks C_SHIFT_FD_V7_0 module +*/ + +`timescale 1ns/10ps + +`define c_set 0 +`define c_clear 1 +`define c_override 0 +`define c_no_override 1 +`define c_zeros 0 +`define c_ones 1 +`define c_lsb 2 +`define c_msb 3 +`define c_wrap 4 +`define c_sdin 5 +`define c_lsb_to_msb 0 +`define c_msb_to_lsb 1 +`define c_bidirectional 2 + + +`define all1s {C_WIDTH{1'b1}} +`define all0s 'b0 +`define allXs {C_WIDTH{1'bx}} + +module C_SHIFT_FD_V7_0 (LSB_2_MSB, SDIN, D, P_LOAD, CLK, CE, ACLR, ASET, AINIT, SCLR, SSET, SINIT, SDOUT, Q); + + parameter C_AINIT_VAL = ""; + parameter C_ENABLE_RLOCS = 1; + parameter C_FILL_DATA = `c_sdin; + parameter C_HAS_ACLR = 0; + parameter C_HAS_AINIT = 0; + parameter C_HAS_ASET = 0; + parameter C_HAS_CE = 0; + parameter C_HAS_D = 0; + parameter C_HAS_LSB_2_MSB = 0; + parameter C_HAS_Q = 1; + parameter C_HAS_SCLR = 0; + parameter C_HAS_SDIN = 1; + parameter C_HAS_SDOUT = 0; + parameter C_HAS_SINIT = 0; + parameter C_HAS_SSET = 0; + parameter C_SHIFT_TYPE = `c_lsb_to_msb; + parameter C_SINIT_VAL = ""; + parameter C_SYNC_ENABLE = `c_override; + parameter C_SYNC_PRIORITY = `c_clear; + parameter C_WIDTH = 16; + + //san 13/12/99 + parameter MUX_BUS_INIT_VAL = {C_WIDTH-(C_WIDTH>2?2:0){"0"}}; + + input LSB_2_MSB; + input SDIN; + input [C_WIDTH-1 : 0] D; + input P_LOAD; + input CLK; + input CE; + input ACLR; + input ASET; + input AINIT; + input SCLR; + input SSET; + input SINIT; + output SDOUT; + output [C_WIDTH-1 : 0] Q; + + // Internal values to drive signals when input is missing + wire intLSB_2_MSB; + wire intSDIN; + wire [C_WIDTH-1 : 0] intD; + wire intP_LOAD; + wire intCE; + wire intACLR; + wire intASET; + wire intAINIT; + wire intSCLR; + wire intSSET; + wire intSINIT; + wire intSDOUT; + wire [C_WIDTH-1 : 0] intQ; + + wire [C_WIDTH-1 : 0] Q = (C_HAS_Q == 1 ? intQ : `allXs); + wire SDOUT = (C_HAS_SDOUT == 1 ? intSDOUT : 1'bx); + + wire [C_WIDTH-1 : 0] regsin; + wire [C_WIDTH-1 : 0] regsout; + wire [3 : 0] MSBmuxi; + wire [3 : 0] LSBmuxi; + wire [1 : 0] muxc; + + wire MSBmuxo; + wire LSBmuxo; + wire [C_WIDTH-(C_WIDTH>2?2:0) : 1] shmuxo; + + wire [C_WIDTH-(C_WIDTH>2?2:0) : 1] shmuxi0; + wire [C_WIDTH-(C_WIDTH>2?2:0) : 1] shmuxi1; + wire [C_WIDTH-(C_WIDTH>2?2:0) : 1] shmuxi2; + wire [C_WIDTH-(C_WIDTH>2?2:0) : 1] shmuxi3; + // Sort out default values for missing ports + + assign intLSB_2_MSB = (C_SHIFT_TYPE == `c_bidirectional ? (C_HAS_LSB_2_MSB == 1 ? (C_WIDTH == 1 ? 1'b1 : LSB_2_MSB) : 1'bx) : (C_SHIFT_TYPE == `c_lsb_to_msb ? 1'b1 : (C_WIDTH == 1 ? 1'b1 :1'b0))); + assign intSDIN = (C_HAS_SDIN == 1 ? SDIN : (C_FILL_DATA == `c_zeros ? 1'b0 : (C_FILL_DATA == `c_ones ? 1'b1 : (C_FILL_DATA == `c_lsb ? regsout[0] : (C_FILL_DATA == `c_msb ? regsout[C_WIDTH-1] : (C_FILL_DATA == `c_wrap ? (intLSB_2_MSB === 1'b0 ? regsout[0] : regsout[C_WIDTH-1]) : 1'bx)))))); + assign intD = (C_HAS_D == 1 ? D : `allXs); + assign intP_LOAD = (C_HAS_D == 1 ? P_LOAD : 1'b0); + assign intCE = defval(CE, C_HAS_CE, 1); + assign intACLR = defval(ACLR, C_HAS_ACLR, 0); + assign intASET = defval(ASET, C_HAS_ASET, 0); + assign intAINIT = defval(AINIT, C_HAS_AINIT, 0); + assign intSCLR = defval(SCLR, C_HAS_SCLR, 0); + assign intSSET = defval(SSET, C_HAS_SSET, 0); + assign intSINIT = defval(SINIT, C_HAS_SINIT, 0); + + assign intSDOUT = (C_SHIFT_TYPE == `c_lsb_to_msb || C_SHIFT_TYPE == `c_bidirectional ? regsout[C_WIDTH-1] : regsout[0]); + assign intQ = (C_HAS_Q == 1 ? regsout : `allXs); + + assign LSBmuxi[0] = regsout[(C_WIDTH>1?1:0)]; + assign LSBmuxi[1] = intSDIN; + assign LSBmuxi[2] = intD[0]; + assign LSBmuxi[3] = intD[0]; + + assign MSBmuxi[0] = intSDIN; + assign MSBmuxi[1] = regsout[C_WIDTH-(C_WIDTH>1?2:1)]; + assign MSBmuxi[2] = intD[C_WIDTH-1]; + assign MSBmuxi[3] = intD[C_WIDTH-1]; + + assign shmuxi0 = regsout[C_WIDTH-1 : (C_WIDTH>2?2:0)]; + assign shmuxi1 = regsout[C_WIDTH-(C_WIDTH>2?3:1) : 0]; + assign shmuxi2 = intD[C_WIDTH-(C_WIDTH>2?2:1) : (C_WIDTH>2?1:0)]; + assign shmuxi3 = intD[C_WIDTH-(C_WIDTH>2?2:1) : (C_WIDTH>2?1:0)]; + + assign muxc[0] = intLSB_2_MSB; + assign muxc[1] = intP_LOAD; + + assign regsin[0] = LSBmuxo; + assign regsin[C_WIDTH-1] = (C_WIDTH == 1 ? LSBmuxo : MSBmuxo); + assign regsin[C_WIDTH-(C_WIDTH>2?2:1) : (C_WIDTH>2?1:0)] = (C_WIDTH == 1 ? LSBmuxo : (C_WIDTH == 2 ? {MSBmuxo, LSBmuxo} : shmuxo)); + + integer i, j, k; + integer m, unknown; + + // Register implements SR + C_REG_FD_V7_0 #(C_AINIT_VAL, C_ENABLE_RLOCS, C_HAS_ACLR, C_HAS_AINIT, C_HAS_ASET, + C_HAS_CE, C_HAS_SCLR, C_HAS_SINIT, C_HAS_SSET, + C_SINIT_VAL, C_SYNC_ENABLE, C_SYNC_PRIORITY, C_WIDTH) + shreg (.D(regsin), .CLK(CLK), .CE(intCE), .ACLR(intACLR), .ASET(intASET), + .AINIT(intAINIT), .SCLR(intSCLR), .SSET(intSSET), .SINIT(intSINIT), + .Q(regsout)); + + // Muxes to steer data + C_MUX_BIT_V7_0 #("0000", 1, 0, 0, 0, + 0, 1, 0, 0, 0, 0, + 0, 4, 0, 0, 2, "0000", 0, 0) + MSBmux (.M(MSBmuxi), .S(muxc), + .CLK(), .CE(), + .ACLR(), .ASET(), .AINIT(), + .SCLR(), .SSET(), .SINIT(), + .O(MSBmuxo), .Q()); // Feeds regsin[C_WIDTH-1] + + C_MUX_BIT_V7_0 #("0000", 1, 0, 0, 0, + 0, 1, 0, 0, 0, 0, + 0, 4, 0, 0, 2, "0000", 0, 0) + LSBmux(.M(LSBmuxi), .S(muxc), + .CLK(), .CE(), + .ACLR(), .ASET(), .AINIT(), + .SCLR(), .SSET(), .SINIT(), + .O(LSBmuxo), .Q()); // Feeds regsin[0]; + + //Edited SAN 13/12/99 //Added extra latency parameter, nritchie 15/9/00 + C_MUX_BUS_V7_0 #(MUX_BUS_INIT_VAL, 1, 0, 0, 0, + 0, 0, 1, 0, 0, 0, 0, + 0, 4, 0, 0, 2, MUX_BUS_INIT_VAL, 0, 0, C_WIDTH-(C_WIDTH>2?2:0)) + shmux (.MA(shmuxi0), .MB(shmuxi1), .MC(shmuxi2), .MD(shmuxi3), .ME(), .MF(), .MG(), .MH(), + .MAA(), .MAB(), .MAC(), .MAD(), .MAE(), .MAF(), .MAG(), .MAH(), + .MBA(), .MBB(), .MBC(), .MBD(), .MBE(), .MBF(), .MBG(), .MBH(), + .MCA(), .MCB(), .MCC(), .MCD(), .MCE(), .MCF(), .MCG(), .MCH(), + .S(muxc), + .CLK(), .CE(), .EN(), + .ACLR(), .ASET(), .AINIT(), + .SCLR(), .SSET(), .SINIT(), + .O(shmuxo), .Q()); // Feeds regsin[C_WIDTH-2 : 1] + + + function defval; + input i; + input hassig; + input val; + begin + if(hassig == 1) + defval = i; + else + defval = val; + end + endfunction + +endmodule + +`undef c_set +`undef c_clear +`undef c_override +`undef c_no_override +`undef c_zeros +`undef c_ones +`undef c_lsb +`undef c_msb +`undef c_wrap +`undef c_sdin +`undef c_lsb_to_msb +`undef c_msb_to_lsb +`undef c_bidirectional + +`undef all1s +`undef all0s +`undef allXs + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/C_SHIFT_RAM_V4_0.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/C_SHIFT_RAM_V4_0.v new file mode 100644 index 0000000..2b7d064 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/C_SHIFT_RAM_V4_0.v @@ -0,0 +1,332 @@ +/* $Id: C_SHIFT_RAM_V4_0.v,v 1.12 2008/09/08 20:05:46 akennedy Exp $ +-- +-- Filename - C_SHIFT_RAM_V4_0.v +-- Author - Xilinx +-- Creation - 24 Mar 1999 +-- +-- Description +-- RAM based Shift Register Simulation Model +*/ + + +module C_SHIFT_RAM_V4_0 (A, D, CLK, CE, ACLR, ASET, AINIT, SCLR, SSET, SINIT, Q); + + parameter C_ADDR_WIDTH = 4; + parameter C_AINIT_VAL = ""; + parameter C_DEFAULT_DATA = "0"; + parameter C_DEFAULT_DATA_RADIX = 1; + parameter C_DEPTH = 16; + parameter C_ENABLE_RLOCS = 1; + parameter C_GENERATE_MIF = 0; // Unused by the behavioural model + parameter C_HAS_A = 0; + parameter C_HAS_ACLR = 0; + parameter C_HAS_AINIT = 0; + parameter C_HAS_ASET = 0; + parameter C_HAS_CE = 0; + parameter C_HAS_SCLR = 0; + parameter C_HAS_SINIT = 0; + parameter C_HAS_SSET = 0; + parameter C_MEM_INIT_FILE = "null.mif"; + parameter C_MEM_INIT_RADIX = 1; // for backwards compatibility + parameter C_READ_MIF = 0; + parameter C_REG_LAST_BIT = 0; + parameter C_SHIFT_TYPE = 0; // c_fixed + parameter C_SINIT_VAL = ""; + parameter C_SYNC_ENABLE = 0; // c_override + parameter C_SYNC_PRIORITY = 1; // c_clear + parameter C_WIDTH = 16; + parameter C_DEPTH_TEMP = ((C_DEPTH/16)+1)*16; // to enable vsim to work + parameter radix = (C_DEFAULT_DATA_RADIX == 1 ? C_MEM_INIT_RADIX : C_DEFAULT_DATA_RADIX); + + input [C_WIDTH-1 : 0] D; + input [C_ADDR_WIDTH-1 : 0] A; + input CLK; + input CE; + input ACLR; + input ASET; + input AINIT; + input SCLR; + input SSET; + input SINIT; + output [C_WIDTH-1 : 0] Q; + + wire [C_WIDTH-1 : 0] shift_out; + wire [C_WIDTH-1 : 0] shift_out_1; + wire [C_WIDTH-1 : 0] shift_out_2; + wire [C_WIDTH-1 : 0] reg_out; + // Internal values to drive signals when input is missing + wire [C_WIDTH-1 : 0] intQ; + wire [C_WIDTH-1 : 0] #1 Q = intQ; + wire intCE; + + reg lastCLK; + wire [C_WIDTH-1 : 0] feedin; + wire [C_ADDR_WIDTH-1 : 0] addtop; + wire [3 : 0] addlow; + wire [C_ADDR_WIDTH-1 : 0] intA; + + integer i; + integer rdeep; + + reg [C_WIDTH-1 : 0] default_data; + reg [C_WIDTH-1 : 0] ram_data [0 : C_DEPTH]; + reg [C_WIDTH-1 : 0] shifter [0 : ((C_SHIFT_TYPE === 0 || C_DEPTH%16 == 0)?C_DEPTH:C_DEPTH_TEMP)]; + + function integer ADDR_IS_X; + input [C_ADDR_WIDTH-1 : 0] value; + integer i; + begin + ADDR_IS_X = 0; + for(i = 0; i < C_ADDR_WIDTH; i = i + 1) + if(value[i] === 1'bX) + ADDR_IS_X = 1; + end + endfunction + + // Sort out default values for missing ports + + assign intQ = (C_REG_LAST_BIT === 1)?reg_out:shift_out; + assign intCE = defval(CE, C_HAS_CE, 1); + assign intA = (C_HAS_A ? A : C_DEPTH-1); + assign addtop = (C_ADDR_WIDTH > 4 ? intA[C_ADDR_WIDTH-1 : (C_ADDR_WIDTH>4?4:0)] : 0); + assign addlow = intA[(C_ADDR_WIDTH>3?3:(C_ADDR_WIDTH-1)) : 0]; // modified by dlunn on 21/10/99 from intA[3:0] + assign shift_out_1 = (ADDR_IS_X(intA) ? {C_WIDTH{1'bx}} : (intA < rdeep ? shifter[intA] : 1'bx)); // DLUNN MODIFIED FINAL EXPRESSION FROM 0 FOR ILLEGAL ADDRESSING + assign shift_out_2 = (ADDR_IS_X(addlow) ? {C_WIDTH{1'bx}} : shifter[rdeep-16+addlow]); + assign shift_out = ((C_DEPTH == 1 && C_REG_LAST_BIT) ? D[0] : + C_SHIFT_TYPE == 0 ? shifter[C_DEPTH-C_REG_LAST_BIT-1] : + (C_SHIFT_TYPE == 1 ? shift_out_1 : shift_out_2)); + assign feedin = (ADDR_IS_X(addtop) ? {C_WIDTH{1'bx}} : (addtop === 0 ? D : (addtop < rdeep/16 ? shifter[(addtop*16)-1] : {C_WIDTH{1'bx}}))); // DLUNN MODIFIED FINAL EXPRESSION FROM 0 FOR ILLEGAL ADDRESSING + + // Register on output by default + C_REG_FD_V4_0 #(C_AINIT_VAL, C_ENABLE_RLOCS, C_HAS_ACLR, C_HAS_AINIT, C_HAS_ASET, + C_HAS_CE, C_HAS_SCLR, C_HAS_SINIT, C_HAS_SSET, + C_SINIT_VAL, C_SYNC_ENABLE, C_SYNC_PRIORITY, C_WIDTH) + final_reg (.D(shift_out), .CLK(CLK), .CE(CE), .ACLR(ACLR), .ASET(ASET), + .AINIT(AINIT), .SCLR(SCLR), .SSET(SSET), .SINIT(SINIT), + .Q(reg_out)); + + + initial + begin + #1; + rdeep = (C_SHIFT_TYPE === 0 || C_DEPTH%16 == 0)?C_DEPTH:((C_DEPTH/16)+1)*16; + for(i = 0; i < rdeep; i = i + 1) shifter[i] = {C_WIDTH{1'b0}}; + default_data = 'b0; + case (radix) + 3 : default_data = decstr_conv(C_DEFAULT_DATA); + 2 : default_data = binstr_conv(C_DEFAULT_DATA); + 1 : default_data = hexstr_conv(C_DEFAULT_DATA); + default : $display("ERROR : BAD DATA RADIX"); + endcase + + for(i = 0; i < C_DEPTH; i = i + 1) + ram_data[i] = default_data; + + if(C_READ_MIF == 1) + begin + $readmemb(C_MEM_INIT_FILE, ram_data); + end + if (C_GENERATE_MIF == 1) + write_meminit_file; + + for(i = 0; i < C_DEPTH; i = i + 1) + shifter[i] = ram_data[i]; + end + + always@(posedge CLK or intA) + begin + if(CLK !== lastCLK && (intCE === 1'b1 && CLK !== 1'bx && lastCLK !== 1'bx)) + begin + if(C_SHIFT_TYPE === 2) + begin + for(i = rdeep-1; i > rdeep-16; i = i - 1) shifter[i] <= shifter[i-1]; + shifter[rdeep-16] <= feedin; + for(i = rdeep-17; i > 0; i = i - 1) shifter[i] <= shifter[i-1]; + end + else + for(i = rdeep-1; i > 0; i = i - 1) shifter[i] <= shifter[i-1]; + + shifter[0] <= D; + end + if(CLK !== lastCLK && (intCE === 1'bx || CLK === 1'bx || lastCLK === 1'bx)) + for(i = 0; i < rdeep; i = i + 1) shifter[i] <= {C_WIDTH{1'bx}}; + end + + + always@(CLK) + lastCLK <= CLK; + + function defval; + input i; + input hassig; + input val; + begin + if(hassig == 1) + defval = i; + else + defval = val; + end + endfunction + + function [C_WIDTH-1:0] binstr_conv; + input [(C_WIDTH*8)-1:0] def_data; + + integer index,i; + + begin + index = 0; + binstr_conv = 'b0; + + for( i=C_WIDTH-1; i>=0; i=i-1 ) + begin + case (def_data[7:0]) + 8'b00000000 : i = -1; + 8'b00110000 : binstr_conv[index] = 1'b0; + 8'b00110001 : binstr_conv[index] = 1'b1; + default : + begin + $display("ERROR : NOT A BINARY CHARACTER"); + binstr_conv[index] = 1'bx; + end + endcase + index = index + 1; + def_data = def_data >> 8; + end + end + endfunction + + function [C_WIDTH-1:0] hexstr_conv; + input [(C_WIDTH*8)-1:0] def_data; + + integer index,i,j; + reg [3:0] bin; + + begin + index = 0; + hexstr_conv = 'b0; + for( i=C_WIDTH-1; i>=0; i=i-1 ) + begin + case (def_data[7:0]) + 8'b00000000 : + begin + bin = 4'b0000; + i = -1; + end + 8'b00110000 : bin = 4'b0000; + 8'b00110001 : bin = 4'b0001; + 8'b00110010 : bin = 4'b0010; + 8'b00110011 : bin = 4'b0011; + 8'b00110100 : bin = 4'b0100; + 8'b00110101 : bin = 4'b0101; + 8'b00110110 : bin = 4'b0110; + 8'b00110111 : bin = 4'b0111; + 8'b00111000 : bin = 4'b1000; + 8'b00111001 : bin = 4'b1001; + 8'b01000001 : bin = 4'b1010; + 8'b01000010 : bin = 4'b1011; + 8'b01000011 : bin = 4'b1100; + 8'b01000100 : bin = 4'b1101; + 8'b01000101 : bin = 4'b1110; + 8'b01000110 : bin = 4'b1111; + 8'b01100001 : bin = 4'b1010; + 8'b01100010 : bin = 4'b1011; + 8'b01100011 : bin = 4'b1100; + 8'b01100100 : bin = 4'b1101; + 8'b01100101 : bin = 4'b1110; + 8'b01100110 : bin = 4'b1111; + default : + begin + $display("ERROR : NOT A HEX CHARACTER"); + bin = 4'bx; + end + endcase + for( j=0; j<4; j=j+1) + begin + if ((index*4)+j < C_WIDTH) + begin + hexstr_conv[(index*4)+j] = bin[j]; + end + end + index = index + 1; + def_data = def_data >> 8; + end + end + endfunction + + function [C_WIDTH-1:0] decstr_conv; + input [(C_WIDTH*8)-1:0] def_data; + + integer index,i,j; + reg [3:0] bin; + + begin + index = 0; + decstr_conv = 'b0; + for( i=C_WIDTH-1; i>=0; i=i-1 ) + begin + case (def_data[7:0]) + 8'b00000000 : + begin + bin = 4'b0000; + i = -1; + end + 8'b00110000 : bin = 4'b0000; + 8'b00110001 : bin = 4'b0001; + 8'b00110010 : bin = 4'b0010; + 8'b00110011 : bin = 4'b0011; + 8'b00110100 : bin = 4'b0100; + 8'b00110101 : bin = 4'b0101; + 8'b00110110 : bin = 4'b0110; + 8'b00110111 : bin = 4'b0111; + 8'b00111000 : bin = 4'b1000; + 8'b00111001 : bin = 4'b1001; + 8'b01000001 : bin = 4'b1010; + 8'b01000010 : bin = 4'b1011; + 8'b01000011 : bin = 4'b1100; + 8'b01000100 : bin = 4'b1101; + 8'b01000101 : bin = 4'b1110; + 8'b01000110 : bin = 4'b1111; + default : + begin + $display("ERROR : NOT A DECIMAL CHARACTER"); + bin = 4'bx; + end + endcase + for( j=0; j<4; j=j+1) + begin + if ((index*4)+j < C_WIDTH) + begin + decstr_conv[(index*4)+j] = bin[j]; + end + end + index = index + 1; + def_data = def_data >> 8; + end + end + endfunction + + task write_meminit_file; + + integer addrs, outfile, bit_index; + + reg [C_WIDTH-1 : 0] conts; + reg anyX; + + begin + outfile = $fopen(C_MEM_INIT_FILE); + for( addrs = 0; addrs < C_DEPTH; addrs=addrs+1) + begin + anyX = 1'b0; + conts = ram_data[addrs]; + for(bit_index = 0; bit_index < C_WIDTH; bit_index=bit_index+1) + if(conts[bit_index] === 1'bx) anyX = 1'b1; + if(anyX == 1'b1) + $display("ERROR : MEMORY CONTAINS UNKNOWNS"); + $fdisplay(outfile,"%b",ram_data[addrs]); + end + $fclose(outfile); + end + endtask + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/C_SHIFT_RAM_V5_0.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/C_SHIFT_RAM_V5_0.v new file mode 100644 index 0000000..bfb314c --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/C_SHIFT_RAM_V5_0.v @@ -0,0 +1,333 @@ +/* $Id: C_SHIFT_RAM_V5_0.v,v 1.17 2008/09/08 20:05:56 akennedy Exp $ +-- +-- Filename - C_SHIFT_RAM_V5_0.v +-- Author - Xilinx +-- Creation - 24 Mar 1999 +-- +-- Description +-- RAM based Shift Register Simulation Model +*/ + +`timescale 1ns/10ps + +module C_SHIFT_RAM_V5_0 (A, D, CLK, CE, ACLR, ASET, AINIT, SCLR, SSET, SINIT, Q); + + parameter C_ADDR_WIDTH = 4; + parameter C_AINIT_VAL = ""; + parameter C_DEFAULT_DATA = "0"; + parameter C_DEFAULT_DATA_RADIX = 1; + parameter C_DEPTH = 16; + parameter C_ENABLE_RLOCS = 1; + parameter C_GENERATE_MIF = 0; // Unused by the behavioural model + parameter C_HAS_A = 0; + parameter C_HAS_ACLR = 0; + parameter C_HAS_AINIT = 0; + parameter C_HAS_ASET = 0; + parameter C_HAS_CE = 0; + parameter C_HAS_SCLR = 0; + parameter C_HAS_SINIT = 0; + parameter C_HAS_SSET = 0; + parameter C_MEM_INIT_FILE = "null.mif"; + parameter C_MEM_INIT_RADIX = 1; // for backwards compatibility + parameter C_READ_MIF = 0; + parameter C_REG_LAST_BIT = 0; + parameter C_SHIFT_TYPE = 0; // c_fixed + parameter C_SINIT_VAL = ""; + parameter C_SYNC_ENABLE = 0; // c_override + parameter C_SYNC_PRIORITY = 1; // c_clear + parameter C_WIDTH = 16; + parameter C_DEPTH_TEMP = ((C_DEPTH/16)+1)*16; // to enable vsim to work + parameter radix = (C_DEFAULT_DATA_RADIX == 1 ? C_MEM_INIT_RADIX : C_DEFAULT_DATA_RADIX); + + input [C_WIDTH-1 : 0] D; + input [C_ADDR_WIDTH-1 : 0] A; + input CLK; + input CE; + input ACLR; + input ASET; + input AINIT; + input SCLR; + input SSET; + input SINIT; + output [C_WIDTH-1 : 0] Q; + + wire [C_WIDTH-1 : 0] shift_out; + wire [C_WIDTH-1 : 0] shift_out_1; + wire [C_WIDTH-1 : 0] shift_out_2; + wire [C_WIDTH-1 : 0] reg_out; + // Internal values to drive signals when input is missing + wire [C_WIDTH-1 : 0] intQ; + wire [C_WIDTH-1 : 0] #1 Q = intQ; + wire intCE; + + reg lastCLK; + wire [C_WIDTH-1 : 0] feedin; + wire [C_ADDR_WIDTH-1 : 0] addtop; + wire [3 : 0] addlow; + wire [C_ADDR_WIDTH-1 : 0] intA; + + integer i; + integer rdeep; + + reg [C_WIDTH-1 : 0] default_data; + reg [C_WIDTH-1 : 0] ram_data [0 : C_DEPTH]; + reg [C_WIDTH-1 : 0] shifter [0 : ((C_SHIFT_TYPE === 0 || C_DEPTH%16 == 0)?C_DEPTH:C_DEPTH_TEMP)]; + + function integer ADDR_IS_X; + input [C_ADDR_WIDTH-1 : 0] value; + integer i; + begin + ADDR_IS_X = 0; + for(i = 0; i < C_ADDR_WIDTH; i = i + 1) + if(value[i] === 1'bX) + ADDR_IS_X = 1; + end + endfunction + + // Sort out default values for missing ports + + assign intQ = (C_REG_LAST_BIT === 1)?reg_out:shift_out; + assign intCE = defval(CE, C_HAS_CE, 1); + assign intA = (C_HAS_A ? A : C_DEPTH-1); + assign addtop = (C_ADDR_WIDTH > 4 ? intA[C_ADDR_WIDTH-1 : (C_ADDR_WIDTH>4?4:0)] : 0); + assign addlow = intA[(C_ADDR_WIDTH>3?3:(C_ADDR_WIDTH-1)) : 0]; // modified by dlunn on 21/10/99 from intA[3:0] + assign shift_out_1 = (ADDR_IS_X(intA) ? {C_WIDTH{1'bx}} : (intA < rdeep ? shifter[intA] : 1'bx)); // DLUNN MODIFIED FINAL EXPRESSION FROM 0 FOR ILLEGAL ADDRESSING + assign shift_out_2 = (ADDR_IS_X(addlow) ? {C_WIDTH{1'bx}} : shifter[rdeep-16+addlow]); + assign shift_out = ((C_DEPTH == 1 && C_REG_LAST_BIT) ? D[0] : + C_SHIFT_TYPE == 0 ? shifter[C_DEPTH-C_REG_LAST_BIT-1] : + (C_SHIFT_TYPE == 1 ? shift_out_1 : shift_out_2)); + assign feedin = (ADDR_IS_X(addtop) ? {C_WIDTH{1'bx}} : (addtop === 0 ? D : (addtop < rdeep/16 ? shifter[(addtop*16)-1] : {C_WIDTH{1'bx}}))); // DLUNN MODIFIED FINAL EXPRESSION FROM 0 FOR ILLEGAL ADDRESSING + + // Register on output by default + C_REG_FD_V5_0 #(C_AINIT_VAL, C_ENABLE_RLOCS, C_HAS_ACLR, C_HAS_AINIT, C_HAS_ASET, + C_HAS_CE, C_HAS_SCLR, C_HAS_SINIT, C_HAS_SSET, + C_SINIT_VAL, C_SYNC_ENABLE, C_SYNC_PRIORITY, C_WIDTH) + final_reg (.D(shift_out), .CLK(CLK), .CE(CE), .ACLR(ACLR), .ASET(ASET), + .AINIT(AINIT), .SCLR(SCLR), .SSET(SSET), .SINIT(SINIT), + .Q(reg_out)); + + + initial + begin + #1; + rdeep = (C_SHIFT_TYPE === 0 || C_DEPTH%16 == 0)?C_DEPTH:((C_DEPTH/16)+1)*16; + for(i = 0; i < rdeep; i = i + 1) shifter[i] = {C_WIDTH{1'b0}}; + default_data = 'b0; + case (radix) + 3 : default_data = decstr_conv(C_DEFAULT_DATA); + 2 : default_data = binstr_conv(C_DEFAULT_DATA); + 1 : default_data = hexstr_conv(C_DEFAULT_DATA); + default : $display("ERROR in %m at time %d ns : BAD DATA RADIX", $time); + endcase + + for(i = 0; i < C_DEPTH; i = i + 1) + ram_data[i] = default_data; + + if(C_READ_MIF == 1) + begin + $readmemb(C_MEM_INIT_FILE, ram_data); + end + if (C_GENERATE_MIF == 1) + write_meminit_file; + + for(i = 0; i < C_DEPTH; i = i + 1) + shifter[i] = ram_data[i]; + end + + always@(posedge CLK or intA) + begin + if(CLK !== lastCLK && (intCE === 1'b1 && CLK !== 1'bx && lastCLK !== 1'bx)) + begin + if(C_SHIFT_TYPE === 2) + begin + for(i = rdeep-1; i > rdeep-16; i = i - 1) shifter[i] <= shifter[i-1]; + shifter[rdeep-16] <= feedin; + for(i = rdeep-17; i > 0; i = i - 1) shifter[i] <= shifter[i-1]; + end + else + for(i = rdeep-1; i > 0; i = i - 1) shifter[i] <= shifter[i-1]; + + shifter[0] <= D; + end + if(CLK !== lastCLK && (intCE === 1'bx || CLK === 1'bx || lastCLK === 1'bx)) + for(i = 0; i < rdeep; i = i + 1) shifter[i] <= {C_WIDTH{1'bx}}; + end + + + always@(CLK) + lastCLK <= CLK; + + function defval; + input i; + input hassig; + input val; + begin + if(hassig == 1) + defval = i; + else + defval = val; + end + endfunction + + function [C_WIDTH-1:0] binstr_conv; + input [(C_WIDTH*8)-1:0] def_data; + + integer index,i; + + begin + index = 0; + binstr_conv = 'b0; + + for( i=C_WIDTH-1; i>=0; i=i-1 ) + begin + case (def_data[7:0]) + 8'b00000000 : i = -1; + 8'b00110000 : binstr_conv[index] = 1'b0; + 8'b00110001 : binstr_conv[index] = 1'b1; + default : + begin + $display("ERROR in %m at time %d ns: NOT A BINARY CHARACTER", $time); + binstr_conv[index] = 1'bx; + end + endcase + index = index + 1; + def_data = def_data >> 8; + end + end + endfunction + + function [C_WIDTH-1:0] hexstr_conv; + input [(C_WIDTH*8)-1:0] def_data; + + integer index,i,j; + reg [3:0] bin; + + begin + index = 0; + hexstr_conv = 'b0; + for( i=C_WIDTH-1; i>=0; i=i-1 ) + begin + case (def_data[7:0]) + 8'b00000000 : + begin + bin = 4'b0000; + i = -1; + end + 8'b00110000 : bin = 4'b0000; + 8'b00110001 : bin = 4'b0001; + 8'b00110010 : bin = 4'b0010; + 8'b00110011 : bin = 4'b0011; + 8'b00110100 : bin = 4'b0100; + 8'b00110101 : bin = 4'b0101; + 8'b00110110 : bin = 4'b0110; + 8'b00110111 : bin = 4'b0111; + 8'b00111000 : bin = 4'b1000; + 8'b00111001 : bin = 4'b1001; + 8'b01000001 : bin = 4'b1010; + 8'b01000010 : bin = 4'b1011; + 8'b01000011 : bin = 4'b1100; + 8'b01000100 : bin = 4'b1101; + 8'b01000101 : bin = 4'b1110; + 8'b01000110 : bin = 4'b1111; + 8'b01100001 : bin = 4'b1010; + 8'b01100010 : bin = 4'b1011; + 8'b01100011 : bin = 4'b1100; + 8'b01100100 : bin = 4'b1101; + 8'b01100101 : bin = 4'b1110; + 8'b01100110 : bin = 4'b1111; + default : + begin + $display("ERROR in %m at time %d ns : NOT A HEX CHARACTER", $time); + bin = 4'bx; + end + endcase + for( j=0; j<4; j=j+1) + begin + if ((index*4)+j < C_WIDTH) + begin + hexstr_conv[(index*4)+j] = bin[j]; + end + end + index = index + 1; + def_data = def_data >> 8; + end + end + endfunction + + function [C_WIDTH-1:0] decstr_conv; + input [(C_WIDTH*8)-1:0] def_data; + + integer index,i,j; + reg [3:0] bin; + + begin + index = 0; + decstr_conv = 'b0; + for( i=C_WIDTH-1; i>=0; i=i-1 ) + begin + case (def_data[7:0]) + 8'b00000000 : + begin + bin = 4'b0000; + i = -1; + end + 8'b00110000 : bin = 4'b0000; + 8'b00110001 : bin = 4'b0001; + 8'b00110010 : bin = 4'b0010; + 8'b00110011 : bin = 4'b0011; + 8'b00110100 : bin = 4'b0100; + 8'b00110101 : bin = 4'b0101; + 8'b00110110 : bin = 4'b0110; + 8'b00110111 : bin = 4'b0111; + 8'b00111000 : bin = 4'b1000; + 8'b00111001 : bin = 4'b1001; + 8'b01000001 : bin = 4'b1010; + 8'b01000010 : bin = 4'b1011; + 8'b01000011 : bin = 4'b1100; + 8'b01000100 : bin = 4'b1101; + 8'b01000101 : bin = 4'b1110; + 8'b01000110 : bin = 4'b1111; + default : + begin + $display("ERROR in %m at time %d ns : NOT A DECIMAL CHARACTER", $time); + bin = 4'bx; + end + endcase + for( j=0; j<4; j=j+1) + begin + if ((index*4)+j < C_WIDTH) + begin + decstr_conv[(index*4)+j] = bin[j]; + end + end + index = index + 1; + def_data = def_data >> 8; + end + end + endfunction + + task write_meminit_file; + + integer addrs, outfile, bit_index; + + reg [C_WIDTH-1 : 0] conts; + reg anyX; + + begin + outfile = $fopen(C_MEM_INIT_FILE); + for( addrs = 0; addrs < C_DEPTH; addrs=addrs+1) + begin + anyX = 1'b0; + conts = ram_data[addrs]; + for(bit_index = 0; bit_index < C_WIDTH; bit_index=bit_index+1) + if(conts[bit_index] === 1'bx) anyX = 1'b1; + if(anyX == 1'b1) + $display("ERROR in %m at time %d ns: MEMORY CONTAINS UNKNOWNS", $time); + $fdisplay(outfile,"%b",ram_data[addrs]); + end + $fclose(outfile); + end + endtask + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/C_SHIFT_RAM_V6_0.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/C_SHIFT_RAM_V6_0.v new file mode 100644 index 0000000..caf5421 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/C_SHIFT_RAM_V6_0.v @@ -0,0 +1,380 @@ +// Copyright(C) 2002 by Xilinx, Inc. All rights reserved. +// This text contains proprietary, confidential +// information of Xilinx, Inc., is distributed +// under license from Xilinx, Inc., and may be used, +// copied and/or disclosed only pursuant to the terms +// of a valid license agreement with Xilinx, Inc. This copyright +// notice must be retained as part of this text at all times. + + +/* $Revision: 1.16 $ $Date: 2008/09/08 20:06:05 $ +-- +-- Filename - C_SHIFT_RAM_V6_0.v +-- Author - Xilinx +-- Creation - 24 Mar 1999 +-- +-- Description +-- RAM based Shift Register Simulation Model +*/ + +`timescale 1ns/10ps + +module C_SHIFT_RAM_V6_0 (A, D, CLK, CE, ACLR, ASET, AINIT, SCLR, SSET, SINIT, Q); + + parameter C_ADDR_WIDTH = 4; + parameter C_AINIT_VAL = ""; + parameter C_DEFAULT_DATA = "0"; + parameter C_DEFAULT_DATA_RADIX = 1; + parameter C_DEPTH = 16; + parameter C_ENABLE_RLOCS = 1; + parameter C_GENERATE_MIF = 0; // Unused by the behavioural model + parameter C_HAS_A = 0; + parameter C_HAS_ACLR = 0; + parameter C_HAS_AINIT = 0; + parameter C_HAS_ASET = 0; + parameter C_HAS_CE = 0; + parameter C_HAS_SCLR = 0; + parameter C_HAS_SINIT = 0; + parameter C_HAS_SSET = 0; + parameter C_MEM_INIT_FILE = "null.mif"; + parameter C_MEM_INIT_RADIX = 1; // for backwards compatibility + parameter C_READ_MIF = 0; + parameter C_REG_LAST_BIT = 0; + parameter C_SHIFT_TYPE = 0; // c_fixed + parameter C_SINIT_VAL = ""; + parameter C_SYNC_ENABLE = 0; // c_override + parameter C_SYNC_PRIORITY = 1; // c_clear + parameter C_WIDTH = 16; + + parameter C_DEPTH_TEMP = (C_SHIFT_TYPE == 0 ? ((C_DEPTH-1/17)+1)*17 : ((C_DEPTH-1/16)+1)*16); // to enable vsim to work + parameter radix = (C_DEFAULT_DATA_RADIX == 1 ? C_MEM_INIT_RADIX : C_DEFAULT_DATA_RADIX); + + input [C_WIDTH-1 : 0] D; + input [C_ADDR_WIDTH-1 : 0] A; + input CLK; + input CE; + input ACLR; + input ASET; + input AINIT; + input SCLR; + input SSET; + input SINIT; + output [C_WIDTH-1 : 0] Q; + + wire [C_WIDTH-1 : 0] shift_out; + wire [C_WIDTH-1 : 0] shift_out_1; + wire [C_WIDTH-1 : 0] shift_out_2; + wire [C_WIDTH-1 : 0] reg_out; + // Internal values to drive signals when input is missing + wire [C_WIDTH-1 : 0] intQ; + wire [C_WIDTH-1 : 0] #1 Q = intQ; + wire intCE; + + reg lastCLK; + wire [C_WIDTH-1 : 0] feedin; + wire [C_ADDR_WIDTH-1 : 0] addtop; + wire [3 : 0] addlow; + wire [C_ADDR_WIDTH-1 : 0] intA; + + integer i; + integer rdeep; + + reg [C_WIDTH-1 : 0] default_data; + reg [C_WIDTH-1 : 0] ram_data [0 : C_DEPTH_TEMP]; +// reg [C_WIDTH-1 : 0] shifter [0 : ((C_SHIFT_TYPE === 0 || C_DEPTH%16 == 0)?C_DEPTH:C_DEPTH_TEMP)]; + reg [C_WIDTH-1 : 0] shifter [0 : C_DEPTH_TEMP]; + + + function integer ADDR_IS_X; + input [C_ADDR_WIDTH-1 : 0] value; + integer i; + begin + ADDR_IS_X = 0; + for(i = 0; i < C_ADDR_WIDTH; i = i + 1) + if(value[i] === 1'bX) + ADDR_IS_X = 1; + end + endfunction + + // Sort out default values for missing ports + assign intQ = (C_REG_LAST_BIT === 1)?reg_out:shift_out; + assign intCE = defval(CE, C_HAS_CE, 1); + assign intA = (C_HAS_A ? A : C_DEPTH-1); + assign addtop = (C_ADDR_WIDTH > 4 ? intA[C_ADDR_WIDTH-1 : (C_ADDR_WIDTH>4?4:0)] : 0); + + // modified from intA[3:0] + assign addlow = intA[(C_ADDR_WIDTH>3?3:(C_ADDR_WIDTH-1)) : 0]; + + // MODIFIED FINAL EXPRESSION FROM 0 FOR ILLEGAL ADDRESSING + //assign shift_out_1 = (ADDR_IS_X(intA) ? {C_WIDTH{1'bx}} : (intA < rdeep ? shifter[intA] : 1'bx)); + assign shift_out_1 = (ADDR_IS_X(intA) ? {C_WIDTH{1'bx}} : (intA < rdeep+1 ? shifter[intA+1] : 1'bx)); + //assign shift_out_2 = (ADDR_IS_X(addlow) ? {C_WIDTH{1'bx}} : shifter[rdeep-16+addlow]); + assign shift_out_2 = (ADDR_IS_X(addlow) ? {C_WIDTH{1'bx}} : shifter[rdeep-15+addlow]); + + assign shift_out = ((C_DEPTH == 1 && C_REG_LAST_BIT) ? D : // modified from D[0] +// C_SHIFT_TYPE == 0 ? shifter[C_DEPTH-C_REG_LAST_BIT-1] : + C_SHIFT_TYPE == 0 ? shifter[C_DEPTH-C_REG_LAST_BIT] : + (C_SHIFT_TYPE == 1 ? shift_out_1 : shift_out_2)); + + // MODIFIED FINAL EXPRESSION FROM 0 FOR ILLEGAL ADDRESSING + assign feedin = (ADDR_IS_X(addtop) ? {C_WIDTH{1'bx}} : + (addtop === 0 ? D : +// (addtop < rdeep/16 ? shifter[(addtop*16)-1] : + (addtop < rdeep/16 ? shifter[(addtop*16)] : + {C_WIDTH{1'bx}}))); + + // Register on output by default + C_REG_FD_V6_0 #(C_AINIT_VAL, C_ENABLE_RLOCS, C_HAS_ACLR, C_HAS_AINIT, C_HAS_ASET, + C_HAS_CE, C_HAS_SCLR, C_HAS_SINIT, C_HAS_SSET, + C_SINIT_VAL, C_SYNC_ENABLE, C_SYNC_PRIORITY, C_WIDTH) + final_reg (.D(shift_out), .CLK(CLK), .CE(CE), .ACLR(ACLR), .ASET(ASET), + .AINIT(AINIT), .SCLR(SCLR), .SSET(SSET), .SINIT(SINIT), + .Q(reg_out)); + + initial + begin + #1; + rdeep = (C_SHIFT_TYPE === 0 || C_DEPTH%16 == 0)?C_DEPTH:((C_DEPTH/16)+1)*16; + //for(i = 0; i < rdeep; i = i + 1) + for(i = 1; i < rdeep + 1; i = i + 1) + shifter[i] = {C_WIDTH{1'b0}}; + + default_data = 'b0; + case (radix) + 3 : default_data = decstr_conv(C_DEFAULT_DATA); + 2 : default_data = binstr_conv(C_DEFAULT_DATA); + 1 : default_data = hexstr_conv(C_DEFAULT_DATA); + default : $display("ERROR in %m at time %d ns : BAD DATA RADIX", $time); + endcase + + for(i = 0; i < C_DEPTH_TEMP; i = i + 1) + ram_data[i] = default_data; + + if(C_READ_MIF == 1) + begin + $readmemb(C_MEM_INIT_FILE, ram_data, 0, C_DEPTH_TEMP-1); + end + +/* if(C_READ_MIF == 1 && C_SHIFT_TYPE == 0) + begin + $readmemb(C_MEM_INIT_FILE, ram_data, 0, C_DEPTH_TEMP2 - 1); + end */ + + if (C_GENERATE_MIF == 1) + write_meminit_file; + + for(i = 0; i < C_DEPTH; i = i + 1) + //shifter[i] = ram_data[i]; + shifter[i+1] = ram_data[i]; + end + + always@(posedge CLK or intA) + begin + if(CLK !== lastCLK && (intCE === 1'b1 && CLK !== 1'bx && lastCLK !== 1'bx)) + begin + if(C_SHIFT_TYPE === 2) + begin + //for(i = rdeep-1; i > rdeep-16; i = i - 1) + for(i=rdeep; i > rdeep-15; i = i - 1) + shifter[i] <= shifter[i-1]; + + //shifter[rdeep-16] <= feedin; + shifter[rdeep-15] <= feedin; + + + //for(i = rdeep-17; i > 0; i = i - 1) + for(i = rdeep-16; i > 1; i = i - 1) + shifter[i] <= shifter[i-1]; + end + else + //for(i = rdeep-1; i > 0; i = i - 1) + for(i = rdeep; i > 1; i = i - 1) + shifter[i] <= shifter[i-1]; + + //shifter[0] <= D; + shifter[1] <= D; + end + + if(CLK !== lastCLK && (intCE === 1'bx || CLK === 1'bx || lastCLK === 1'bx)) + //for(i = 0; i < rdeep; i = i + 1) + for(i = 1; i < rdeep + 1; i = i + 1) + shifter[i] <= {C_WIDTH{1'bx}}; + end // end(CLK or intA) + + + always@(CLK) + lastCLK <= CLK; + + function defval; + input i; + input hassig; + input val; + begin + if(hassig == 1) + defval = i; + else + defval = val; + end + endfunction + + function [C_WIDTH-1:0] binstr_conv; + input [(C_WIDTH*8)-1:0] def_data; + + integer index,i; + + begin + index = 0; + binstr_conv = 'b0; + + for( i=C_WIDTH-1; i>=0; i=i-1 ) + begin + case (def_data[7:0]) + 8'b00000000 : i = -1; + 8'b00110000 : binstr_conv[index] = 1'b0; + 8'b00110001 : binstr_conv[index] = 1'b1; + default : + begin + $display("ERROR in %m at time %d ns: NOT A BINARY CHARACTER", $time); + binstr_conv[index] = 1'bx; + end + endcase + index = index + 1; + def_data = def_data >> 8; + end + end + endfunction + + function [C_WIDTH-1:0] hexstr_conv; + input [(C_WIDTH*8)-1:0] def_data; + + integer index,i,j; + reg [3:0] bin; + + begin + index = 0; + hexstr_conv = 'b0; + for( i=C_WIDTH-1; i>=0; i=i-1 ) + begin + case (def_data[7:0]) + 8'b00000000 : + begin + bin = 4'b0000; + i = -1; + end + 8'b00110000 : bin = 4'b0000; + 8'b00110001 : bin = 4'b0001; + 8'b00110010 : bin = 4'b0010; + 8'b00110011 : bin = 4'b0011; + 8'b00110100 : bin = 4'b0100; + 8'b00110101 : bin = 4'b0101; + 8'b00110110 : bin = 4'b0110; + 8'b00110111 : bin = 4'b0111; + 8'b00111000 : bin = 4'b1000; + 8'b00111001 : bin = 4'b1001; + 8'b01000001 : bin = 4'b1010; + 8'b01000010 : bin = 4'b1011; + 8'b01000011 : bin = 4'b1100; + 8'b01000100 : bin = 4'b1101; + 8'b01000101 : bin = 4'b1110; + 8'b01000110 : bin = 4'b1111; + 8'b01100001 : bin = 4'b1010; + 8'b01100010 : bin = 4'b1011; + 8'b01100011 : bin = 4'b1100; + 8'b01100100 : bin = 4'b1101; + 8'b01100101 : bin = 4'b1110; + 8'b01100110 : bin = 4'b1111; + default : + begin + $display("ERROR in %m at time %d ns : NOT A HEX CHARACTER", $time); + bin = 4'bx; + end + endcase + for( j=0; j<4; j=j+1) + begin + if ((index*4)+j < C_WIDTH) + begin + hexstr_conv[(index*4)+j] = bin[j]; + end + end + index = index + 1; + def_data = def_data >> 8; + end + end + endfunction + + function [C_WIDTH-1:0] decstr_conv; + input [(C_WIDTH*8)-1:0] def_data; + + integer index,i,j; + reg [3:0] bin; + + begin + index = 0; + decstr_conv = 'b0; + for( i=C_WIDTH-1; i>=0; i=i-1 ) + begin + case (def_data[7:0]) + 8'b00000000 : + begin + bin = 4'b0000; + i = -1; + end + 8'b00110000 : bin = 4'b0000; + 8'b00110001 : bin = 4'b0001; + 8'b00110010 : bin = 4'b0010; + 8'b00110011 : bin = 4'b0011; + 8'b00110100 : bin = 4'b0100; + 8'b00110101 : bin = 4'b0101; + 8'b00110110 : bin = 4'b0110; + 8'b00110111 : bin = 4'b0111; + 8'b00111000 : bin = 4'b1000; + 8'b00111001 : bin = 4'b1001; + 8'b01000001 : bin = 4'b1010; + 8'b01000010 : bin = 4'b1011; + 8'b01000011 : bin = 4'b1100; + 8'b01000100 : bin = 4'b1101; + 8'b01000101 : bin = 4'b1110; + 8'b01000110 : bin = 4'b1111; + default : + begin + $display("ERROR in %m at time %d ns : NOT A DECIMAL CHARACTER", $time); + bin = 4'bx; + end + endcase + for( j=0; j<4; j=j+1) + begin + if ((index*4)+j < C_WIDTH) + begin + decstr_conv[(index*4)+j] = bin[j]; + end + end + index = index + 1; + def_data = def_data >> 8; + end + end + endfunction + + task write_meminit_file; + + integer addrs, outfile, bit_index; + + reg [C_WIDTH-1 : 0] conts; + reg anyX; + + begin + outfile = $fopen(C_MEM_INIT_FILE); + for( addrs = 0; addrs < C_DEPTH; addrs=addrs+1) + begin + anyX = 1'b0; + conts = ram_data[addrs]; + for(bit_index = 0; bit_index < C_WIDTH; bit_index=bit_index+1) + if(conts[bit_index] === 1'bx) anyX = 1'b1; + if(anyX == 1'b1) + $display("ERROR in %m at time %d ns: MEMORY CONTAINS UNKNOWNS", $time); + $fdisplay(outfile,"%b",ram_data[addrs]); + end + $fclose(outfile); + end + endtask + +endmodule // C_SHIFT_RAM_V6_0 diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/C_SHIFT_RAM_V7_0.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/C_SHIFT_RAM_V7_0.v new file mode 100644 index 0000000..ed86477 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/C_SHIFT_RAM_V7_0.v @@ -0,0 +1,408 @@ +// Copyright(C) 2003 by Xilinx, Inc. All rights reserved. +// This text/file contains proprietary, confidential +// information of Xilinx, Inc., is distributed under license +// from Xilinx, Inc., and may be used, copied and/or +// disclosed only pursuant to the terms of a valid license +// agreement with Xilinx, Inc. Xilinx hereby grants you +// a license to use this text/file solely for design, simulation, +// implementation and creation of design files limited +// to Xilinx devices or technologies. Use with non-Xilinx +// devices or technologies is expressly prohibited and +// immediately terminates your license unless covered by +// a separate agreement. +// +// Xilinx is providing this design, code, or information +// "as is" solely for use in developing programs and +// solutions for Xilinx devices. By providing this design, +// code, or information as one possible implementation of +// this feature, application or standard, Xilinx is making no +// representation that this implementation is free from any +// claims of infringement. You are responsible for +// obtaining any rights you may require for your implementation. +// Xilinx expressly disclaims any warranty whatsoever with +// respect to the adequacy of the implementation, including +// but not limited to any warranties or representations that this +// implementation is free from claims of infringement, implied +// warranties of merchantability or fitness for a particular +// purpose. +// +// Xilinx products are not intended for use in life support +// appliances, devices, or systems. Use in such applications are +// expressly prohibited. +// +// This copyright and support notice must be retained as part +// of this text at all times. (c) Copyright 1995-2003 Xilinx, Inc. +// All rights reserved. + + +/* $Revision: 1.13 $ $Date: 2008/09/08 20:06:14 $ +-- +-- Filename - C_SHIFT_RAM_V7_0.v +-- Author - Xilinx +-- Creation - 24 Mar 1999 +-- +-- Description +-- RAM based Shift Register Simulation Model +*/ + +`timescale 1ns/10ps + +module C_SHIFT_RAM_V7_0 (A, D, CLK, CE, ACLR, ASET, AINIT, SCLR, SSET, SINIT, Q); + + parameter C_ADDR_WIDTH = 4; + parameter C_AINIT_VAL = ""; + parameter C_DEFAULT_DATA = "0"; + parameter C_DEFAULT_DATA_RADIX = 1; + parameter C_DEPTH = 16; + parameter C_ENABLE_RLOCS = 1; + parameter C_GENERATE_MIF = 0; // Unused by the behavioural model + parameter C_HAS_A = 0; + parameter C_HAS_ACLR = 0; + parameter C_HAS_AINIT = 0; + parameter C_HAS_ASET = 0; + parameter C_HAS_CE = 0; + parameter C_HAS_SCLR = 0; + parameter C_HAS_SINIT = 0; + parameter C_HAS_SSET = 0; + parameter C_MEM_INIT_FILE = "null.mif"; + parameter C_MEM_INIT_RADIX = 1; // for backwards compatibility + parameter C_READ_MIF = 0; + parameter C_REG_LAST_BIT = 0; + parameter C_SHIFT_TYPE = 0; // c_fixed + parameter C_SINIT_VAL = ""; + parameter C_SYNC_ENABLE = 0; // c_override + parameter C_SYNC_PRIORITY = 1; // c_clear + parameter C_WIDTH = 16; + + parameter C_DEPTH_TEMP = (C_SHIFT_TYPE == 0 ? ((C_DEPTH-1/17)+1)*17 : ((C_DEPTH-1/16)+1)*16); // to enable vsim to work + parameter radix = (C_DEFAULT_DATA_RADIX == 1 ? C_MEM_INIT_RADIX : C_DEFAULT_DATA_RADIX); + + input [C_WIDTH-1 : 0] D; + input [C_ADDR_WIDTH-1 : 0] A; + input CLK; + input CE; + input ACLR; + input ASET; + input AINIT; + input SCLR; + input SSET; + input SINIT; + output [C_WIDTH-1 : 0] Q; + + wire [C_WIDTH-1 : 0] shift_out; + wire [C_WIDTH-1 : 0] shift_out_1; + wire [C_WIDTH-1 : 0] shift_out_2; + wire [C_WIDTH-1 : 0] reg_out; + // Internal values to drive signals when input is missing + wire [C_WIDTH-1 : 0] intQ; + wire [C_WIDTH-1 : 0] #1 Q = intQ; + wire intCE; + + reg lastCLK; + wire [C_WIDTH-1 : 0] feedin; + wire [C_ADDR_WIDTH-1 : 0] addtop; + wire [3 : 0] addlow; + wire [C_ADDR_WIDTH-1 : 0] intA; + + integer i; + integer rdeep; + + reg [C_WIDTH-1 : 0] default_data; + reg [C_WIDTH-1 : 0] ram_data [0 : C_DEPTH_TEMP]; +// reg [C_WIDTH-1 : 0] shifter [0 : ((C_SHIFT_TYPE === 0 || C_DEPTH%16 == 0)?C_DEPTH:C_DEPTH_TEMP)]; + reg [C_WIDTH-1 : 0] shifter [0 : C_DEPTH_TEMP]; + + + function integer ADDR_IS_X; + input [C_ADDR_WIDTH-1 : 0] value; + integer i; + begin + ADDR_IS_X = 0; + for(i = 0; i < C_ADDR_WIDTH; i = i + 1) + if(value[i] === 1'bX) + ADDR_IS_X = 1; + end + endfunction + + // Sort out default values for missing ports + assign intQ = (C_REG_LAST_BIT === 1)?reg_out:shift_out; + assign intCE = defval(CE, C_HAS_CE, 1); + assign intA = (C_HAS_A ? A : C_DEPTH-1); + assign addtop = (C_ADDR_WIDTH > 4 ? intA[C_ADDR_WIDTH-1 : (C_ADDR_WIDTH>4?4:0)] : 0); + + // modified from intA[3:0] + assign addlow = intA[(C_ADDR_WIDTH>3?3:(C_ADDR_WIDTH-1)) : 0]; + + // MODIFIED FINAL EXPRESSION FROM 0 FOR ILLEGAL ADDRESSING + //assign shift_out_1 = (ADDR_IS_X(intA) ? {C_WIDTH{1'bx}} : (intA < rdeep ? shifter[intA] : 1'bx)); + assign shift_out_1 = (ADDR_IS_X(intA) ? {C_WIDTH{1'bx}} : (intA < rdeep+1 ? shifter[intA+1] : 1'bx)); + //assign shift_out_2 = (ADDR_IS_X(addlow) ? {C_WIDTH{1'bx}} : shifter[rdeep-16+addlow]); + assign shift_out_2 = (ADDR_IS_X(addlow) ? {C_WIDTH{1'bx}} : shifter[rdeep-15+addlow]); + + assign shift_out = ((C_DEPTH == 1 && C_REG_LAST_BIT) ? D : // modified from D[0] +// C_SHIFT_TYPE == 0 ? shifter[C_DEPTH-C_REG_LAST_BIT-1] : + C_SHIFT_TYPE == 0 ? shifter[C_DEPTH-C_REG_LAST_BIT] : + (C_SHIFT_TYPE == 1 ? shift_out_1 : shift_out_2)); + + // MODIFIED FINAL EXPRESSION FROM 0 FOR ILLEGAL ADDRESSING + assign feedin = (ADDR_IS_X(addtop) ? {C_WIDTH{1'bx}} : + (addtop === 0 ? D : +// (addtop < rdeep/16 ? shifter[(addtop*16)-1] : + (addtop < rdeep/16 ? shifter[(addtop*16)] : + {C_WIDTH{1'bx}}))); + + // Register on output by default + C_REG_FD_V7_0 #(C_AINIT_VAL, C_ENABLE_RLOCS, C_HAS_ACLR, C_HAS_AINIT, C_HAS_ASET, + C_HAS_CE, C_HAS_SCLR, C_HAS_SINIT, C_HAS_SSET, + C_SINIT_VAL, C_SYNC_ENABLE, C_SYNC_PRIORITY, C_WIDTH) + final_reg (.D(shift_out), .CLK(CLK), .CE(CE), .ACLR(ACLR), .ASET(ASET), + .AINIT(AINIT), .SCLR(SCLR), .SSET(SSET), .SINIT(SINIT), + .Q(reg_out)); + + initial + begin + #1; + rdeep = (C_SHIFT_TYPE === 0 || C_DEPTH%16 == 0)?C_DEPTH:((C_DEPTH/16)+1)*16; + //for(i = 0; i < rdeep; i = i + 1) + for(i = 1; i < rdeep + 1; i = i + 1) + shifter[i] = {C_WIDTH{1'b0}}; + + default_data = 'b0; + case (radix) + 3 : default_data = decstr_conv(C_DEFAULT_DATA); + 2 : default_data = binstr_conv(C_DEFAULT_DATA); + 1 : default_data = hexstr_conv(C_DEFAULT_DATA); + default : $display("ERROR in %m at time %d ns : BAD DATA RADIX", $time); + endcase + + for(i = 0; i < C_DEPTH_TEMP; i = i + 1) + ram_data[i] = default_data; + + if(C_READ_MIF == 1) + begin + $readmemb(C_MEM_INIT_FILE, ram_data, 0, C_DEPTH_TEMP-1); + end + +/* if(C_READ_MIF == 1 && C_SHIFT_TYPE == 0) + begin + $readmemb(C_MEM_INIT_FILE, ram_data, 0, C_DEPTH_TEMP2 - 1); + end */ + + if (C_GENERATE_MIF == 1) + write_meminit_file; + + for(i = 0; i < C_DEPTH; i = i + 1) + //shifter[i] = ram_data[i]; + shifter[i+1] = ram_data[i]; + end + + always@(posedge CLK or intA) + begin + if(CLK !== lastCLK && (intCE === 1'b1 && CLK !== 1'bx && lastCLK !== 1'bx)) + begin + if(C_SHIFT_TYPE === 2) + begin + //for(i = rdeep-1; i > rdeep-16; i = i - 1) + for(i=rdeep; i > rdeep-15; i = i - 1) + shifter[i] <= shifter[i-1]; + + //shifter[rdeep-16] <= feedin; + shifter[rdeep-15] <= feedin; + + + //for(i = rdeep-17; i > 0; i = i - 1) + for(i = rdeep-16; i > 1; i = i - 1) + shifter[i] <= shifter[i-1]; + end + else + //for(i = rdeep-1; i > 0; i = i - 1) + for(i = rdeep; i > 1; i = i - 1) + shifter[i] <= shifter[i-1]; + + //shifter[0] <= D; + shifter[1] <= D; + end + + if(CLK !== lastCLK && (intCE === 1'bx || CLK === 1'bx || lastCLK === 1'bx)) + //for(i = 0; i < rdeep; i = i + 1) + for(i = 1; i < rdeep + 1; i = i + 1) + shifter[i] <= {C_WIDTH{1'bx}}; + end // end(CLK or intA) + + + always@(CLK) + lastCLK <= CLK; + + function defval; + input i; + input hassig; + input val; + begin + if(hassig == 1) + defval = i; + else + defval = val; + end + endfunction + + function [C_WIDTH-1:0] binstr_conv; + input [(C_WIDTH*8)-1:0] def_data; + + integer index,i; + + begin + index = 0; + binstr_conv = 'b0; + + for( i=C_WIDTH-1; i>=0; i=i-1 ) + begin + case (def_data[7:0]) + 8'b00000000 : i = -1; + 8'b00110000 : binstr_conv[index] = 1'b0; + 8'b00110001 : binstr_conv[index] = 1'b1; + default : + begin + $display("ERROR in %m at time %d ns: NOT A BINARY CHARACTER", $time); + binstr_conv[index] = 1'bx; + end + endcase + index = index + 1; + def_data = def_data >> 8; + end + end + endfunction + + function [C_WIDTH-1:0] hexstr_conv; + input [(C_WIDTH*8)-1:0] def_data; + + integer index,i,j; + reg [3:0] bin; + + begin + index = 0; + hexstr_conv = 'b0; + for( i=C_WIDTH-1; i>=0; i=i-1 ) + begin + case (def_data[7:0]) + 8'b00000000 : + begin + bin = 4'b0000; + i = -1; + end + 8'b00110000 : bin = 4'b0000; + 8'b00110001 : bin = 4'b0001; + 8'b00110010 : bin = 4'b0010; + 8'b00110011 : bin = 4'b0011; + 8'b00110100 : bin = 4'b0100; + 8'b00110101 : bin = 4'b0101; + 8'b00110110 : bin = 4'b0110; + 8'b00110111 : bin = 4'b0111; + 8'b00111000 : bin = 4'b1000; + 8'b00111001 : bin = 4'b1001; + 8'b01000001 : bin = 4'b1010; + 8'b01000010 : bin = 4'b1011; + 8'b01000011 : bin = 4'b1100; + 8'b01000100 : bin = 4'b1101; + 8'b01000101 : bin = 4'b1110; + 8'b01000110 : bin = 4'b1111; + 8'b01100001 : bin = 4'b1010; + 8'b01100010 : bin = 4'b1011; + 8'b01100011 : bin = 4'b1100; + 8'b01100100 : bin = 4'b1101; + 8'b01100101 : bin = 4'b1110; + 8'b01100110 : bin = 4'b1111; + default : + begin + $display("ERROR in %m at time %d ns : NOT A HEX CHARACTER", $time); + bin = 4'bx; + end + endcase + for( j=0; j<4; j=j+1) + begin + if ((index*4)+j < C_WIDTH) + begin + hexstr_conv[(index*4)+j] = bin[j]; + end + end + index = index + 1; + def_data = def_data >> 8; + end + end + endfunction + + function [C_WIDTH-1:0] decstr_conv; + input [(C_WIDTH*8)-1:0] def_data; + + integer index,i,j; + reg [3:0] bin; + + begin + index = 0; + decstr_conv = 'b0; + for( i=C_WIDTH-1; i>=0; i=i-1 ) + begin + case (def_data[7:0]) + 8'b00000000 : + begin + bin = 4'b0000; + i = -1; + end + 8'b00110000 : bin = 4'b0000; + 8'b00110001 : bin = 4'b0001; + 8'b00110010 : bin = 4'b0010; + 8'b00110011 : bin = 4'b0011; + 8'b00110100 : bin = 4'b0100; + 8'b00110101 : bin = 4'b0101; + 8'b00110110 : bin = 4'b0110; + 8'b00110111 : bin = 4'b0111; + 8'b00111000 : bin = 4'b1000; + 8'b00111001 : bin = 4'b1001; + 8'b01000001 : bin = 4'b1010; + 8'b01000010 : bin = 4'b1011; + 8'b01000011 : bin = 4'b1100; + 8'b01000100 : bin = 4'b1101; + 8'b01000101 : bin = 4'b1110; + 8'b01000110 : bin = 4'b1111; + default : + begin + $display("ERROR in %m at time %d ns : NOT A DECIMAL CHARACTER", $time); + bin = 4'bx; + end + endcase + for( j=0; j<4; j=j+1) + begin + if ((index*4)+j < C_WIDTH) + begin + decstr_conv[(index*4)+j] = bin[j]; + end + end + index = index + 1; + def_data = def_data >> 8; + end + end + endfunction + + task write_meminit_file; + + integer addrs, outfile, bit_index; + + reg [C_WIDTH-1 : 0] conts; + reg anyX; + + begin + outfile = $fopen(C_MEM_INIT_FILE); + for( addrs = 0; addrs < C_DEPTH; addrs=addrs+1) + begin + anyX = 1'b0; + conts = ram_data[addrs]; + for(bit_index = 0; bit_index < C_WIDTH; bit_index=bit_index+1) + if(conts[bit_index] === 1'bx) anyX = 1'b1; + if(anyX == 1'b1) + $display("ERROR in %m at time %d ns: MEMORY CONTAINS UNKNOWNS", $time); + $fdisplay(outfile,"%b",ram_data[addrs]); + end + $fclose(outfile); + end + endtask + +endmodule // C_SHIFT_RAM_V7_0 diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/C_SIN_COS_V5_0.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/C_SIN_COS_V5_0.v new file mode 100644 index 0000000..13ca613 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/C_SIN_COS_V5_0.v @@ -0,0 +1,286 @@ +// Copyright(C) 2004 by Xilinx, Inc. All rights reserved. +// This text contains proprietary, confidential +// information of Xilinx, Inc., is distributed +// under license from Xilinx, Inc., and may be used, +// copied and/or disclosed only pursuant to the terms +// of a valid license agreement with Xilinx, Inc. This copyright +// notice must be retained as part of this text at all times. + +// $Revision: 1.12 $ $Date: 2008/09/08 20:09:48 $ + +`timescale 1ns/10ps + +`define SINE_ONLY 0 +`define COSINE_ONLY 1 +`define SINE_AND_COSINE 2 +`define DIST_ROM 0 +`define BLOCK_ROM 1 +`define allUKs {C_OUTPUT_WIDTH{1'bX}} +`define c_sdin 5 + +module C_SIN_COS_V5_0 (ACLR,CE,CLK,COSINE,ND,RDY,RFD,SCLR,SINE,THETA) ; + + parameter C_ENABLE_RLOCS = 0; + parameter C_HAS_ACLR = 0; + parameter C_HAS_CE = 0; + parameter C_HAS_CLK = 0; + parameter C_HAS_ND = 1; + parameter C_HAS_RDY = 1; + parameter C_HAS_RFD = 1; + parameter C_HAS_SCLR = 0; + parameter C_LATENCY = 0; + parameter C_MEM_TYPE = `DIST_ROM; + parameter C_NEGATIVE_COSINE = 0; + parameter C_NEGATIVE_SINE = 0; + parameter C_OUTPUTS_REQUIRED = `SINE_ONLY; + parameter C_OUTPUT_WIDTH = 16; + parameter C_PIPE_STAGES = 0; + parameter C_REG_INPUT = 0; + parameter C_REG_OUTPUT = 0; + parameter C_SYMMETRIC = 0; + parameter C_THETA_WIDTH = 4; + + + parameter hasOutputRegCe = (C_HAS_CE || C_HAS_ND || C_LATENCY > 1)?1:0; + parameter latencyOutRegCe = (C_LATENCY>1)?C_LATENCY:2; + parameter latencyRdyPipeline = (C_LATENCY>0)?C_LATENCY:1; + + // ------------ Port declarations --------- // + input ACLR; + wire ACLR; + input CE; + wire CE; + input CLK; + wire CLK; + input ND; + wire ND; + input SCLR; + wire SCLR; + input [C_THETA_WIDTH-1:0] THETA; + wire [C_THETA_WIDTH-1:0] THETA; + + output RDY; + wire RDY; + output RFD; + wire RFD; + output [C_OUTPUT_WIDTH-1:0] COSINE; + wire [C_OUTPUT_WIDTH-1:0] COSINE; + output [C_OUTPUT_WIDTH-1:0] SINE; + wire [C_OUTPUT_WIDTH-1:0] SINE; + + // ----------------- Constants ------------ // + parameter DANGLING_INPUT_CONSTANT = 1'bZ; + + // ----------- Signal declarations -------- // + wire ceInt = (C_HAS_CE?CE:1'b1); + wire [C_OUTPUT_WIDTH-1:0] cos_outreg; + wire [C_OUTPUT_WIDTH-1:0] cos_pipe; + wire [C_OUTPUT_WIDTH-1:0] cos_pipeout; + wire delayedCe; + wire [latencyOutRegCe-2:0] hasOutRegCe1_open; + wire ndInt; + wire rdyInt; + wire [latencyOutRegCe-2:0] outRegCeDangle; + reg outputRegCe; + wire [latencyRdyPipeline-1:0] rdyPipelineDangle; + wire [latencyRdyPipeline-1:0] rdy_pipeline_open; + wire [C_OUTPUT_WIDTH-1:0] sin_outreg; + wire [C_OUTPUT_WIDTH-1:0] sin_pipe; + wire [C_OUTPUT_WIDTH-1:0] sin_pipeout; + wire [C_THETA_WIDTH-1:0] thetaInt; + reg [C_THETA_WIDTH-1:0] thetaReg; + + // ---- Declaration for Dangling inputs ----// + wire Dangling_Input_Signal = DANGLING_INPUT_CONSTANT; + + // ------- User defined Verilog code -------// + + //----- Verilog statement0 ----// + always @(delayedCe or ceInt or ndInt) + begin + if (C_HAS_CE==1 && (C_LATENCY > 1)) + outputRegCe <= ceInt && delayedCe; + else if (C_LATENCY > 1) + outputRegCe <= delayedCe; + else outputRegCe <= ceInt && ndInt; + //else if (C_HAS_CE==1 && C_HAS_ND==1) + // outputRegCe <= CE && ND; + //else if (C_HAS_CE) + // outputRegCe <= CE; + end + + //----- Verilog statement1 ----// + wire [C_OUTPUT_WIDTH-1 : 0] sineInt = (C_REG_OUTPUT==1 ? sin_outreg : sin_pipeout); + assign SINE = (((C_OUTPUTS_REQUIRED == `SINE_ONLY) || + (C_OUTPUTS_REQUIRED == `SINE_AND_COSINE)) ? sineInt : `allUKs); + wire [C_OUTPUT_WIDTH-1 : 0] cosineInt = (C_REG_OUTPUT==1 ? cos_outreg : cos_pipeout); + assign COSINE = (((C_OUTPUTS_REQUIRED == `COSINE_ONLY) || + (C_OUTPUTS_REQUIRED == `SINE_AND_COSINE)) ? cosineInt : `allUKs); + assign ndInt = (C_HAS_ND == 1 ? ND : 1'b1); + assign RFD = (C_HAS_RFD == 1 ? 1'b1 : 1'bX); + wire rdyInt2 = (C_HAS_RDY==1 && (C_LATENCY==0) ? ndInt : 1'bX); + assign RDY = (C_HAS_RDY==1 && (C_LATENCY>0) ? rdyInt : rdyInt2); + assign thetaInt = (C_REG_INPUT ==1 ? thetaReg : THETA); + + //----- Verilog statement2 ----// + always @(posedge CLK) + begin + if (ceInt) + thetaReg <= THETA; + end + + //----- Verilog statement3 ----// + initial + begin + thetaReg <= 0; + end + + TRIG_TABLE_V5_0 trig_arrays + ( + .cos_table(cos_pipe[C_OUTPUT_WIDTH-1:0]), + .sin_table(sin_pipe[C_OUTPUT_WIDTH-1:0]), + .theta(thetaInt[C_THETA_WIDTH-1:0]) + ); + + defparam trig_arrays.minusCos = C_NEGATIVE_COSINE; + defparam trig_arrays.minusSin = C_NEGATIVE_SINE; + defparam trig_arrays.output_width = C_OUTPUT_WIDTH; + defparam trig_arrays.theta_width = C_THETA_WIDTH; + defparam trig_arrays.symmetric = C_SYMMETRIC; + + PIPE_BHV_V5_0 sine_pipeline + ( + .ACLR(ACLR), + .CE(ceInt), + .CLK(CLK), + .D(sin_pipe[C_OUTPUT_WIDTH-1:0]), + .Q(sin_pipeout[C_OUTPUT_WIDTH-1:0]), + .SCLR(SCLR) + ); + + defparam sine_pipeline.C_HAS_ACLR = C_HAS_ACLR*C_REG_OUTPUT; + defparam sine_pipeline.C_HAS_CE = C_HAS_CE; + defparam sine_pipeline.C_HAS_SCLR = C_HAS_SCLR*C_REG_OUTPUT; + defparam sine_pipeline.C_PIPE_STAGES = C_LATENCY-C_REG_OUTPUT-C_REG_INPUT; + defparam sine_pipeline.C_WIDTH = C_OUTPUT_WIDTH; + + PIPE_BHV_V5_0 cosine_pipeline + ( + .ACLR(ACLR), + .CE(ceInt), + .CLK(CLK), + .D(cos_pipe[C_OUTPUT_WIDTH-1:0]), + .Q(cos_pipeout[C_OUTPUT_WIDTH-1:0]), + .SCLR(SCLR) + ); + + defparam cosine_pipeline.C_HAS_ACLR = C_HAS_ACLR*C_REG_OUTPUT; + defparam cosine_pipeline.C_HAS_CE = C_HAS_CE; + defparam cosine_pipeline.C_HAS_SCLR = C_HAS_SCLR*C_REG_OUTPUT; + defparam cosine_pipeline.C_PIPE_STAGES = C_LATENCY-C_REG_OUTPUT-C_REG_INPUT; + defparam cosine_pipeline.C_WIDTH = C_OUTPUT_WIDTH; + + C_REG_FD_V7_0 sin_output_reg + ( + .ACLR(ACLR), + .AINIT(Dangling_Input_Signal), + .ASET(Dangling_Input_Signal), + .CE(outputRegCe), + .CLK(CLK), + .D(sin_pipeout[C_OUTPUT_WIDTH-1:0]), + .Q(sin_outreg[C_OUTPUT_WIDTH-1:0]), + .SCLR(SCLR), + .SINIT(Dangling_Input_Signal), + .SSET(Dangling_Input_Signal) + ); + + defparam sin_output_reg.C_HAS_ACLR = C_HAS_ACLR*C_REG_OUTPUT; + defparam sin_output_reg.C_HAS_CE = hasOutputRegCe; + defparam sin_output_reg.C_HAS_SCLR = C_HAS_SCLR*C_REG_OUTPUT; + defparam sin_output_reg.C_WIDTH = C_OUTPUT_WIDTH; + + C_REG_FD_V7_0 cos_output_reg + ( + .ACLR(ACLR), + .AINIT(Dangling_Input_Signal), + .ASET(Dangling_Input_Signal), + .CE(outputRegCe), + .CLK(CLK), + .D(cos_pipeout[C_OUTPUT_WIDTH-1:0]), + .Q(cos_outreg[C_OUTPUT_WIDTH-1:0]), + .SCLR(SCLR), + .SINIT(Dangling_Input_Signal), + .SSET(Dangling_Input_Signal) + ); + + defparam cos_output_reg.C_HAS_ACLR = C_HAS_ACLR*C_REG_OUTPUT; + defparam cos_output_reg.C_HAS_CE = hasOutputRegCe; + defparam cos_output_reg.C_HAS_SCLR = C_HAS_SCLR*C_REG_OUTPUT; + defparam cos_output_reg.C_WIDTH = C_OUTPUT_WIDTH; + + C_SHIFT_FD_V7_0 hasOutRegCe1 + ( + .ACLR(ACLR), + .AINIT(Dangling_Input_Signal), + .ASET(Dangling_Input_Signal), + .CE(ceInt), + .CLK(CLK), + .D(outRegCeDangle[latencyOutRegCe-2:0]), + .LSB_2_MSB(Dangling_Input_Signal), + .P_LOAD(Dangling_Input_Signal), + .Q(hasOutRegCe1_open[latencyOutRegCe-2:0]), + .SCLR(SCLR), + .SDIN(ndInt), + .SDOUT(delayedCe), + .SINIT(Dangling_Input_Signal), + .SSET(Dangling_Input_Signal) + ); + + defparam hasOutRegCe1.C_FILL_DATA = `c_sdin; + defparam hasOutRegCe1.C_HAS_ACLR = C_HAS_ACLR*C_REG_OUTPUT; + defparam hasOutRegCe1.C_HAS_CE = C_HAS_CE; + defparam hasOutRegCe1.C_HAS_Q = 0; + defparam hasOutRegCe1.C_HAS_SCLR = C_HAS_SCLR*C_REG_OUTPUT; + defparam hasOutRegCe1.C_HAS_SDIN = 1; + defparam hasOutRegCe1.C_HAS_SDOUT = 1; + defparam hasOutRegCe1.C_SYNC_PRIORITY = 0; + defparam hasOutRegCe1.C_WIDTH = latencyOutRegCe-1; + + C_SHIFT_FD_V7_0 rdy_pipeline + ( + .ACLR(ACLR), + .AINIT(Dangling_Input_Signal), + .ASET(Dangling_Input_Signal), + .CE(ceInt), + .CLK(CLK), + .D(rdyPipelineDangle[latencyRdyPipeline-1:0]), + .LSB_2_MSB(Dangling_Input_Signal), + .P_LOAD(Dangling_Input_Signal), + .Q(rdy_pipeline_open[latencyRdyPipeline-1:0]), + .SCLR(SCLR), + .SDIN(ndInt), + .SDOUT(rdyInt), + .SINIT(Dangling_Input_Signal), + .SSET(Dangling_Input_Signal) + ); + + defparam rdy_pipeline.C_FILL_DATA = `c_sdin; + defparam rdy_pipeline.C_HAS_ACLR = C_HAS_ACLR*C_REG_OUTPUT; + defparam rdy_pipeline.C_HAS_CE = C_HAS_CE; + defparam rdy_pipeline.C_HAS_LSB_2_MSB = 1; + defparam rdy_pipeline.C_HAS_Q = 0; + defparam rdy_pipeline.C_HAS_SCLR = C_HAS_SCLR*C_REG_OUTPUT; + defparam rdy_pipeline.C_HAS_SDIN = 1; + defparam rdy_pipeline.C_HAS_SDOUT = 1; + defparam rdy_pipeline.C_SYNC_PRIORITY = 0; + defparam rdy_pipeline.C_WIDTH = latencyRdyPipeline; + +endmodule + +`undef SINE_ONLY +`undef COSINE_ONLY +`undef SINE_AND_COSINE +`undef DIST_ROM +`undef BLOCK_ROM +`undef allUKs +`undef c_sdin diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/C_SIN_COS_V5_1.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/C_SIN_COS_V5_1.v new file mode 100644 index 0000000..3a646e7 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/C_SIN_COS_V5_1.v @@ -0,0 +1,286 @@ +// Copyright(C) 2004 by Xilinx, Inc. All rights reserved. +// This text contains proprietary, confidential +// information of Xilinx, Inc., is distributed +// under license from Xilinx, Inc., and may be used, +// copied and/or disclosed only pursuant to the terms +// of a valid license agreement with Xilinx, Inc. This copyright +// notice must be retained as part of this text at all times. + +// $Revision: 1.10 $ $Date: 2008/09/08 16:51:31 $ + +`timescale 1ns/10ps + +`define SINE_ONLY 0 +`define COSINE_ONLY 1 +`define SINE_AND_COSINE 2 +`define DIST_ROM 0 +`define BLOCK_ROM 1 +`define allUKs {C_OUTPUT_WIDTH{1'bX}} +`define c_sdin 5 + +module C_SIN_COS_V5_1 (ACLR,CE,CLK,COSINE,ND,RDY,RFD,SCLR,SINE,THETA) ; + + parameter C_ENABLE_RLOCS = 0; + parameter C_HAS_ACLR = 0; + parameter C_HAS_CE = 0; + parameter C_HAS_CLK = 0; + parameter C_HAS_ND = 1; + parameter C_HAS_RDY = 1; + parameter C_HAS_RFD = 1; + parameter C_HAS_SCLR = 0; + parameter C_LATENCY = 0; + parameter C_MEM_TYPE = `DIST_ROM; + parameter C_NEGATIVE_COSINE = 0; + parameter C_NEGATIVE_SINE = 0; + parameter C_OUTPUTS_REQUIRED = `SINE_ONLY; + parameter C_OUTPUT_WIDTH = 16; + parameter C_PIPE_STAGES = 0; + parameter C_REG_INPUT = 0; + parameter C_REG_OUTPUT = 0; + parameter C_SYMMETRIC = 0; + parameter C_THETA_WIDTH = 4; + + + parameter hasOutputRegCe = (C_HAS_CE || C_HAS_ND || C_LATENCY > 1)?1:0; + parameter latencyOutRegCe = (C_LATENCY>1)?C_LATENCY:2; + parameter latencyRdyPipeline = (C_LATENCY>0)?C_LATENCY:1; + + // ------------ Port declarations --------- // + input ACLR; + wire ACLR; + input CE; + wire CE; + input CLK; + wire CLK; + input ND; + wire ND; + input SCLR; + wire SCLR; + input [C_THETA_WIDTH-1:0] THETA; + wire [C_THETA_WIDTH-1:0] THETA; + + output RDY; + wire RDY; + output RFD; + wire RFD; + output [C_OUTPUT_WIDTH-1:0] COSINE; + wire [C_OUTPUT_WIDTH-1:0] COSINE; + output [C_OUTPUT_WIDTH-1:0] SINE; + wire [C_OUTPUT_WIDTH-1:0] SINE; + + // ----------------- Constants ------------ // + parameter DANGLING_INPUT_CONSTANT = 1'bZ; + + // ----------- Signal declarations -------- // + wire ceInt = (C_HAS_CE?CE:1'b1); + wire [C_OUTPUT_WIDTH-1:0] cos_outreg; + wire [C_OUTPUT_WIDTH-1:0] cos_pipe; + wire [C_OUTPUT_WIDTH-1:0] cos_pipeout; + wire delayedCe; + wire [latencyOutRegCe-2:0] hasOutRegCe1_open; + wire ndInt; + wire rdyInt; + wire [latencyOutRegCe-2:0] outRegCeDangle; + reg outputRegCe; + wire [latencyRdyPipeline-1:0] rdyPipelineDangle; + wire [latencyRdyPipeline-1:0] rdy_pipeline_open; + wire [C_OUTPUT_WIDTH-1:0] sin_outreg; + wire [C_OUTPUT_WIDTH-1:0] sin_pipe; + wire [C_OUTPUT_WIDTH-1:0] sin_pipeout; + wire [C_THETA_WIDTH-1:0] thetaInt; + reg [C_THETA_WIDTH-1:0] thetaReg; + + // ---- Declaration for Dangling inputs ----// + wire Dangling_Input_Signal = DANGLING_INPUT_CONSTANT; + + // ------- User defined Verilog code -------// + + //----- Verilog statement0 ----// + always @(delayedCe or ceInt or ndInt) + begin + if (C_HAS_CE==1 && (C_LATENCY > 1)) + outputRegCe <= ceInt && delayedCe; + else if (C_LATENCY > 1) + outputRegCe <= delayedCe; + else outputRegCe <= ceInt && ndInt; + //else if (C_HAS_CE==1 && C_HAS_ND==1) + // outputRegCe <= CE && ND; + //else if (C_HAS_CE) + // outputRegCe <= CE; + end + + //----- Verilog statement1 ----// + wire [C_OUTPUT_WIDTH-1 : 0] sineInt = (C_REG_OUTPUT==1 ? sin_outreg : sin_pipeout); + assign SINE = (((C_OUTPUTS_REQUIRED == `SINE_ONLY) || + (C_OUTPUTS_REQUIRED == `SINE_AND_COSINE)) ? sineInt : `allUKs); + wire [C_OUTPUT_WIDTH-1 : 0] cosineInt = (C_REG_OUTPUT==1 ? cos_outreg : cos_pipeout); + assign COSINE = (((C_OUTPUTS_REQUIRED == `COSINE_ONLY) || + (C_OUTPUTS_REQUIRED == `SINE_AND_COSINE)) ? cosineInt : `allUKs); + assign ndInt = (C_HAS_ND == 1 ? ND : 1'b1); + assign RFD = (C_HAS_RFD == 1 ? 1'b1 : 1'bX); + wire rdyInt2 = (C_HAS_RDY==1 && (C_LATENCY==0) ? ndInt : 1'bX); + assign RDY = (C_HAS_RDY==1 && (C_LATENCY>0) ? rdyInt : rdyInt2); + assign thetaInt = (C_REG_INPUT ==1 ? thetaReg : THETA); + + //----- Verilog statement2 ----// + always @(posedge CLK) + begin + if (ceInt) + thetaReg <= THETA; + end + + //----- Verilog statement3 ----// + initial + begin + thetaReg <= 0; + end + + TRIG_TABLE_V5_1 trig_arrays + ( + .cos_table(cos_pipe[C_OUTPUT_WIDTH-1:0]), + .sin_table(sin_pipe[C_OUTPUT_WIDTH-1:0]), + .theta(thetaInt[C_THETA_WIDTH-1:0]) + ); + + defparam trig_arrays.minusCos = C_NEGATIVE_COSINE; + defparam trig_arrays.minusSin = C_NEGATIVE_SINE; + defparam trig_arrays.output_width = C_OUTPUT_WIDTH; + defparam trig_arrays.theta_width = C_THETA_WIDTH; + defparam trig_arrays.symmetric = C_SYMMETRIC; + + PIPE_BHV_V5_1 sine_pipeline + ( + .ACLR(ACLR), + .CE(ceInt), + .CLK(CLK), + .D(sin_pipe[C_OUTPUT_WIDTH-1:0]), + .Q(sin_pipeout[C_OUTPUT_WIDTH-1:0]), + .SCLR(SCLR) + ); + + defparam sine_pipeline.C_HAS_ACLR = C_HAS_ACLR*C_REG_OUTPUT; + defparam sine_pipeline.C_HAS_CE = C_HAS_CE; + defparam sine_pipeline.C_HAS_SCLR = C_HAS_SCLR*C_REG_OUTPUT; + defparam sine_pipeline.C_PIPE_STAGES = C_LATENCY-C_REG_OUTPUT-C_REG_INPUT; + defparam sine_pipeline.C_WIDTH = C_OUTPUT_WIDTH; + + PIPE_BHV_V5_1 cosine_pipeline + ( + .ACLR(ACLR), + .CE(ceInt), + .CLK(CLK), + .D(cos_pipe[C_OUTPUT_WIDTH-1:0]), + .Q(cos_pipeout[C_OUTPUT_WIDTH-1:0]), + .SCLR(SCLR) + ); + + defparam cosine_pipeline.C_HAS_ACLR = C_HAS_ACLR*C_REG_OUTPUT; + defparam cosine_pipeline.C_HAS_CE = C_HAS_CE; + defparam cosine_pipeline.C_HAS_SCLR = C_HAS_SCLR*C_REG_OUTPUT; + defparam cosine_pipeline.C_PIPE_STAGES = C_LATENCY-C_REG_OUTPUT-C_REG_INPUT; + defparam cosine_pipeline.C_WIDTH = C_OUTPUT_WIDTH; + + C_REG_FD_V7_0 sin_output_reg + ( + .ACLR(ACLR), + .AINIT(Dangling_Input_Signal), + .ASET(Dangling_Input_Signal), + .CE(outputRegCe), + .CLK(CLK), + .D(sin_pipeout[C_OUTPUT_WIDTH-1:0]), + .Q(sin_outreg[C_OUTPUT_WIDTH-1:0]), + .SCLR(SCLR), + .SINIT(Dangling_Input_Signal), + .SSET(Dangling_Input_Signal) + ); + + defparam sin_output_reg.C_HAS_ACLR = C_HAS_ACLR*C_REG_OUTPUT; + defparam sin_output_reg.C_HAS_CE = hasOutputRegCe; + defparam sin_output_reg.C_HAS_SCLR = C_HAS_SCLR*C_REG_OUTPUT; + defparam sin_output_reg.C_WIDTH = C_OUTPUT_WIDTH; + + C_REG_FD_V7_0 cos_output_reg + ( + .ACLR(ACLR), + .AINIT(Dangling_Input_Signal), + .ASET(Dangling_Input_Signal), + .CE(outputRegCe), + .CLK(CLK), + .D(cos_pipeout[C_OUTPUT_WIDTH-1:0]), + .Q(cos_outreg[C_OUTPUT_WIDTH-1:0]), + .SCLR(SCLR), + .SINIT(Dangling_Input_Signal), + .SSET(Dangling_Input_Signal) + ); + + defparam cos_output_reg.C_HAS_ACLR = C_HAS_ACLR*C_REG_OUTPUT; + defparam cos_output_reg.C_HAS_CE = hasOutputRegCe; + defparam cos_output_reg.C_HAS_SCLR = C_HAS_SCLR*C_REG_OUTPUT; + defparam cos_output_reg.C_WIDTH = C_OUTPUT_WIDTH; + + C_SHIFT_FD_V7_0 hasOutRegCe1 + ( + .ACLR(ACLR), + .AINIT(Dangling_Input_Signal), + .ASET(Dangling_Input_Signal), + .CE(ceInt), + .CLK(CLK), + .D(outRegCeDangle[latencyOutRegCe-2:0]), + .LSB_2_MSB(Dangling_Input_Signal), + .P_LOAD(Dangling_Input_Signal), + .Q(hasOutRegCe1_open[latencyOutRegCe-2:0]), + .SCLR(SCLR), + .SDIN(ndInt), + .SDOUT(delayedCe), + .SINIT(Dangling_Input_Signal), + .SSET(Dangling_Input_Signal) + ); + + defparam hasOutRegCe1.C_FILL_DATA = `c_sdin; + defparam hasOutRegCe1.C_HAS_ACLR = C_HAS_ACLR*C_REG_OUTPUT; + defparam hasOutRegCe1.C_HAS_CE = C_HAS_CE; + defparam hasOutRegCe1.C_HAS_Q = 0; + defparam hasOutRegCe1.C_HAS_SCLR = C_HAS_SCLR*C_REG_OUTPUT; + defparam hasOutRegCe1.C_HAS_SDIN = 1; + defparam hasOutRegCe1.C_HAS_SDOUT = 1; + defparam hasOutRegCe1.C_SYNC_PRIORITY = 0; + defparam hasOutRegCe1.C_WIDTH = latencyOutRegCe-1; + + C_SHIFT_FD_V7_0 rdy_pipeline + ( + .ACLR(ACLR), + .AINIT(Dangling_Input_Signal), + .ASET(Dangling_Input_Signal), + .CE(ceInt), + .CLK(CLK), + .D(rdyPipelineDangle[latencyRdyPipeline-1:0]), + .LSB_2_MSB(Dangling_Input_Signal), + .P_LOAD(Dangling_Input_Signal), + .Q(rdy_pipeline_open[latencyRdyPipeline-1:0]), + .SCLR(SCLR), + .SDIN(ndInt), + .SDOUT(rdyInt), + .SINIT(Dangling_Input_Signal), + .SSET(Dangling_Input_Signal) + ); + + defparam rdy_pipeline.C_FILL_DATA = `c_sdin; + defparam rdy_pipeline.C_HAS_ACLR = C_HAS_ACLR*C_REG_OUTPUT; + defparam rdy_pipeline.C_HAS_CE = C_HAS_CE; + defparam rdy_pipeline.C_HAS_LSB_2_MSB = 1; + defparam rdy_pipeline.C_HAS_Q = 0; + defparam rdy_pipeline.C_HAS_SCLR = C_HAS_SCLR*C_REG_OUTPUT; + defparam rdy_pipeline.C_HAS_SDIN = 1; + defparam rdy_pipeline.C_HAS_SDOUT = 1; + defparam rdy_pipeline.C_SYNC_PRIORITY = 0; + defparam rdy_pipeline.C_WIDTH = latencyRdyPipeline; + +endmodule + +`undef SINE_ONLY +`undef COSINE_ONLY +`undef SINE_AND_COSINE +`undef DIST_ROM +`undef BLOCK_ROM +`undef allUKs +`undef c_sdin diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/C_TWOS_COMP_V4_0.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/C_TWOS_COMP_V4_0.v new file mode 100644 index 0000000..81e9e7f --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/C_TWOS_COMP_V4_0.v @@ -0,0 +1,207 @@ +/* $Id: C_TWOS_COMP_V4_0.v,v 1.11 2008/09/08 20:05:46 akennedy Exp $ +-- +-- Filename - C_TWOS_COMP_V4_0.v +-- Author - Xilinx +-- Creation - 3 Feb 1999 +-- +-- Description - This file contains the Verilog behavior for the Baseblocks C_TWOS_COMP_V4_0 module +*/ + + + +`define c_set 0 +`define c_clear 1 +`define c_override 0 +`define c_no_override 1 + +module C_TWOS_COMP_V4_0 (A, BYPASS, CLK, CE, ACLR, ASET, AINIT, SCLR, SSET, SINIT, S, Q); + + parameter C_AINIT_VAL = ""; + parameter C_BYPASS_ENABLE = `c_override; + parameter C_BYPASS_LOW = 0; + parameter C_ENABLE_RLOCS = 1; + parameter C_HAS_ACLR = 0; + parameter C_HAS_AINIT = 0; + parameter C_HAS_ASET = 0; + parameter C_HAS_BYPASS = 0; + parameter C_HAS_CE = 0; + parameter C_HAS_Q = 1; + parameter C_HAS_S = 0; + parameter C_HAS_SCLR = 0; + parameter C_HAS_SINIT = 0; + parameter C_HAS_SSET = 0; + parameter C_PIPE_STAGES = 0; + parameter C_SINIT_VAL = ""; + parameter C_SYNC_ENABLE = `c_override; + parameter C_SYNC_PRIORITY = `c_clear; + parameter C_WIDTH = 16; + + + input [C_WIDTH-1 : 0] A; + input BYPASS; + input CLK; + input CE; + input ACLR; + input ASET; + input AINIT; + input SCLR; + input SSET; + input SINIT; + output [C_WIDTH : 0] S; + output [C_WIDTH : 0] Q; + + // Internal values to drive signals when input is missing + wire intBYPASS; + wire intCE; + wire intQCE; + reg [C_WIDTH : 0] intS; + reg [C_WIDTH : 0] tmpS; + wire [C_WIDTH : 0] intQ; + reg lastCLK; + + reg [C_WIDTH : 0] intQpipe [C_PIPE_STAGES+2 : 0]; + reg [C_WIDTH : 0] intQpipeend; + reg [C_WIDTH : 0] tmp_pipe1; + reg [C_WIDTH : 0] tmp_pipe2; + + wire [C_WIDTH : 0] Q = (C_HAS_Q == 1 ? intQ : {C_WIDTH{1'bx}}); + wire [C_WIDTH : 0] S = (C_HAS_S == 1 ? intS : {C_WIDTH{1'bx}}); + + // Sort out default values for missing ports + + assign intBYPASS = (C_HAS_BYPASS === 1) ? ((C_BYPASS_LOW === 1) ? !BYPASS : BYPASS) : 0; + assign intCE = defval(CE, C_HAS_CE, 1); + assign intQCE = (C_HAS_CE === 1 ? (C_HAS_BYPASS === 1 ? (C_BYPASS_ENABLE === `c_override ? CE || intBYPASS : CE) : CE) : 1'b1); + + integer j; + integer pipe, pipe1; + + // Register on output by default + C_REG_FD_V4_0 #(C_AINIT_VAL, C_ENABLE_RLOCS, C_HAS_ACLR, C_HAS_AINIT, C_HAS_ASET, + C_HAS_CE, C_HAS_SCLR, C_HAS_SINIT, C_HAS_SSET, + C_SINIT_VAL, C_SYNC_ENABLE, C_SYNC_PRIORITY, C_WIDTH + 1) + reg1 (.D(intQpipeend), .CLK(CLK), .CE(intQCE), .ACLR(ACLR), .ASET(ASET), + .AINIT(AINIT), .SCLR(SCLR), .SSET(SSET), .SINIT(SINIT), + .Q(intQ)); + + initial + begin + #1; + if(intBYPASS == 1) + begin + intS[C_WIDTH-1 : 0] = A; + intS[C_WIDTH] = A[C_WIDTH-1]; + end + else if(intBYPASS === 1'bx || is_X(A) == 1'bx) + intS = 'bx; + else + begin + tmpS[C_WIDTH-1 : 0] = ~A; + tmpS[C_WIDTH] = ~A[C_WIDTH-1]; + intS = (tmpS + 1); + end + + + if(C_PIPE_STAGES < 2) // No pipeline + intQpipeend = intS; + else // Pipeline stages required + begin + intQpipeend = intQpipe[2]; + end + end + + always @(CLK) + lastCLK <= CLK; + + always@(A or intBYPASS) + begin + if(intBYPASS == 1) + begin + intS[C_WIDTH-1 : 0] <= #1 A; + intS[C_WIDTH] <= #1 A[C_WIDTH-1]; + end + else if(intBYPASS === 1'bx || is_X(A) == 1'bx) + intS <= #1 'bx; + else + begin + tmpS[C_WIDTH-1 : 0] = ~A; + tmpS[C_WIDTH] = ~A[C_WIDTH-1]; + intS <= #1 (tmpS + 1); + end + end + + always@(posedge CLK) + begin + if(CLK === 1'b1 && lastCLK === 1'b0 && intCE === 1'b1) // OK! Update pipelines! + begin + for(pipe = 2; pipe <= C_PIPE_STAGES-1; pipe = pipe + 1) + begin + intQpipe[pipe] <= intQpipe[pipe+1]; + end + intQpipe[C_PIPE_STAGES] <= intS; + end + else if((CLK === 1'bx && lastCLK === 1'b0) || (CLK === 1'b1 && lastCLK === 1'bx) || intCE === 1'bx) // POSSIBLY Update pipelines! + begin + for(pipe = 2; pipe <= C_PIPE_STAGES-1; pipe = pipe + 1) + begin + tmp_pipe1 = intQpipe[pipe]; + tmp_pipe2 = intQpipe[pipe+1]; + for(pipe1 = 0; pipe1 < C_WIDTH; pipe1 = pipe1 + 1) + begin + if(tmp_pipe1[pipe1] !== tmp_pipe2[pipe1]) + tmp_pipe1[pipe1] = 1'bx; + end + intQpipe[pipe] <= tmp_pipe1; + end + tmp_pipe1 = intQpipe[C_PIPE_STAGES]; + for(pipe1 = 0; pipe1 < C_WIDTH; pipe1 = pipe1 + 1) + begin + if(tmp_pipe1[pipe1] !== intS[pipe1]) + tmp_pipe1[pipe1] = 1'bx; + end + intQpipe[C_PIPE_STAGES] <= tmp_pipe1; + end + end + + always@(intS or intQpipe[2]) + begin + if(C_PIPE_STAGES < 2) // No pipeline + intQpipeend <= intS; + else // Pipeline stages required + begin + intQpipeend <= intQpipe[2]; + end + end + + + function defval; + input i; + input hassig; + input val; + begin + if(hassig == 1) + defval = i; + else + defval = val; + end + endfunction + + function is_X; + input [C_WIDTH-1 : 0] i; + begin + is_X = 1'b0; + for(j = 0; j < C_WIDTH; j = j + 1) + begin + if(i[j] === 1'bx) + is_X = 1'b1; + end // loop + end + endfunction + +endmodule + +`undef c_set +`undef c_clear +`undef c_override +`undef c_no_override + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/C_TWOS_COMP_V5_0.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/C_TWOS_COMP_V5_0.v new file mode 100644 index 0000000..f3b1802 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/C_TWOS_COMP_V5_0.v @@ -0,0 +1,207 @@ +/* $Id: C_TWOS_COMP_V5_0.v,v 1.17 2008/09/08 20:05:56 akennedy Exp $ +-- +-- Filename - C_TWOS_COMP_V5_0.v +-- Author - Xilinx +-- Creation - 3 Feb 1999 +-- +-- Description - This file contains the Verilog behavior for the Baseblocks C_TWOS_COMP_V5_0 module +*/ + +`timescale 1ns/10ps + +`define c_set 0 +`define c_clear 1 +`define c_override 0 +`define c_no_override 1 + +module C_TWOS_COMP_V5_0 (A, BYPASS, CLK, CE, ACLR, ASET, AINIT, SCLR, SSET, SINIT, S, Q); + + parameter C_AINIT_VAL = ""; + parameter C_BYPASS_ENABLE = `c_override; + parameter C_BYPASS_LOW = 0; + parameter C_ENABLE_RLOCS = 1; + parameter C_HAS_ACLR = 0; + parameter C_HAS_AINIT = 0; + parameter C_HAS_ASET = 0; + parameter C_HAS_BYPASS = 0; + parameter C_HAS_CE = 0; + parameter C_HAS_Q = 1; + parameter C_HAS_S = 0; + parameter C_HAS_SCLR = 0; + parameter C_HAS_SINIT = 0; + parameter C_HAS_SSET = 0; + parameter C_PIPE_STAGES = 0; + parameter C_SINIT_VAL = ""; + parameter C_SYNC_ENABLE = `c_override; + parameter C_SYNC_PRIORITY = `c_clear; + parameter C_WIDTH = 16; + + + input [C_WIDTH-1 : 0] A; + input BYPASS; + input CLK; + input CE; + input ACLR; + input ASET; + input AINIT; + input SCLR; + input SSET; + input SINIT; + output [C_WIDTH : 0] S; + output [C_WIDTH : 0] Q; + + // Internal values to drive signals when input is missing + wire intBYPASS; + wire intCE; + wire intQCE; + reg [C_WIDTH : 0] intS; + reg [C_WIDTH : 0] tmpS; + wire [C_WIDTH : 0] intQ; + reg lastCLK; + + reg [C_WIDTH : 0] intQpipe [C_PIPE_STAGES+2 : 0]; + reg [C_WIDTH : 0] intQpipeend; + reg [C_WIDTH : 0] tmp_pipe1; + reg [C_WIDTH : 0] tmp_pipe2; + + wire [C_WIDTH : 0] Q = (C_HAS_Q == 1 ? intQ : {C_WIDTH{1'bx}}); + wire [C_WIDTH : 0] S = (C_HAS_S == 1 ? intS : {C_WIDTH{1'bx}}); + + // Sort out default values for missing ports + + assign intBYPASS = (C_HAS_BYPASS === 1) ? ((C_BYPASS_LOW === 1) ? !BYPASS : BYPASS) : 0; + assign intCE = defval(CE, C_HAS_CE, 1); + assign intQCE = (C_HAS_CE === 1 ? (C_HAS_BYPASS === 1 ? (C_BYPASS_ENABLE === `c_override ? CE || intBYPASS : CE) : CE) : 1'b1); + + integer j; + integer pipe, pipe1; + + // Register on output by default + C_REG_FD_V5_0 #(C_AINIT_VAL, C_ENABLE_RLOCS, C_HAS_ACLR, C_HAS_AINIT, C_HAS_ASET, + C_HAS_CE, C_HAS_SCLR, C_HAS_SINIT, C_HAS_SSET, + C_SINIT_VAL, C_SYNC_ENABLE, C_SYNC_PRIORITY, C_WIDTH + 1) + reg1 (.D(intQpipeend), .CLK(CLK), .CE(intQCE), .ACLR(ACLR), .ASET(ASET), + .AINIT(AINIT), .SCLR(SCLR), .SSET(SSET), .SINIT(SINIT), + .Q(intQ)); + + initial + begin + #1; + if(intBYPASS == 1) + begin + intS[C_WIDTH-1 : 0] = A; + intS[C_WIDTH] = A[C_WIDTH-1]; + end + else if(intBYPASS === 1'bx || is_X(A) == 1'bx) + intS = 'bx; + else + begin + tmpS[C_WIDTH-1 : 0] = ~A; + tmpS[C_WIDTH] = ~A[C_WIDTH-1]; + intS = (tmpS + 1); + end + + + if(C_PIPE_STAGES < 2) // No pipeline + intQpipeend = intS; + else // Pipeline stages required + begin + intQpipeend = intQpipe[2]; + end + end + + always @(CLK) + lastCLK <= CLK; + + always@(A or intBYPASS) + begin + if(intBYPASS == 1) + begin + intS[C_WIDTH-1 : 0] <= #1 A; + intS[C_WIDTH] <= #1 A[C_WIDTH-1]; + end + else if(intBYPASS === 1'bx || is_X(A) == 1'bx) + intS <= #1 'bx; + else + begin + tmpS[C_WIDTH-1 : 0] = ~A; + tmpS[C_WIDTH] = ~A[C_WIDTH-1]; + intS <= #1 (tmpS + 1); + end + end + + always@(posedge CLK) + begin + if(CLK === 1'b1 && lastCLK === 1'b0 && intCE === 1'b1) // OK! Update pipelines! + begin + for(pipe = 2; pipe <= C_PIPE_STAGES-1; pipe = pipe + 1) + begin + intQpipe[pipe] <= intQpipe[pipe+1]; + end + intQpipe[C_PIPE_STAGES] <= intS; + end + else if((CLK === 1'bx && lastCLK === 1'b0) || (CLK === 1'b1 && lastCLK === 1'bx) || intCE === 1'bx) // POSSIBLY Update pipelines! + begin + for(pipe = 2; pipe <= C_PIPE_STAGES-1; pipe = pipe + 1) + begin + tmp_pipe1 = intQpipe[pipe]; + tmp_pipe2 = intQpipe[pipe+1]; + for(pipe1 = 0; pipe1 < C_WIDTH; pipe1 = pipe1 + 1) + begin + if(tmp_pipe1[pipe1] !== tmp_pipe2[pipe1]) + tmp_pipe1[pipe1] = 1'bx; + end + intQpipe[pipe] <= tmp_pipe1; + end + tmp_pipe1 = intQpipe[C_PIPE_STAGES]; + for(pipe1 = 0; pipe1 < C_WIDTH; pipe1 = pipe1 + 1) + begin + if(tmp_pipe1[pipe1] !== intS[pipe1]) + tmp_pipe1[pipe1] = 1'bx; + end + intQpipe[C_PIPE_STAGES] <= tmp_pipe1; + end + end + + always@(intS or intQpipe[2]) + begin + if(C_PIPE_STAGES < 2) // No pipeline + intQpipeend <= intS; + else // Pipeline stages required + begin + intQpipeend <= intQpipe[2]; + end + end + + + function defval; + input i; + input hassig; + input val; + begin + if(hassig == 1) + defval = i; + else + defval = val; + end + endfunction + + function is_X; + input [C_WIDTH-1 : 0] i; + begin + is_X = 1'b0; + for(j = 0; j < C_WIDTH; j = j + 1) + begin + if(i[j] === 1'bx) + is_X = 1'b1; + end // loop + end + endfunction + +endmodule + +`undef c_set +`undef c_clear +`undef c_override +`undef c_no_override + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/C_TWOS_COMP_V6_0.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/C_TWOS_COMP_V6_0.v new file mode 100644 index 0000000..a884e95 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/C_TWOS_COMP_V6_0.v @@ -0,0 +1,216 @@ +// Copyright(C) 2002 by Xilinx, Inc. All rights reserved. +// This text contains proprietary, confidential +// information of Xilinx, Inc., is distributed +// under license from Xilinx, Inc., and may be used, +// copied and/or disclosed only pursuant to the terms +// of a valid license agreement with Xilinx, Inc. This copyright +// notice must be retained as part of this text at all times. + + +/* $Id: C_TWOS_COMP_V6_0.v,v 1.16 2008/09/08 20:06:05 akennedy Exp $ +-- +-- Filename - C_TWOS_COMP_V6_0.v +-- Author - Xilinx +-- Creation - 3 Feb 1999 +-- +-- Description - This file contains the Verilog behavior for the Baseblocks C_TWOS_COMP_V6_0 module +*/ + +`timescale 1ns/10ps + +`define c_set 0 +`define c_clear 1 +`define c_override 0 +`define c_no_override 1 + +module C_TWOS_COMP_V6_0 (A, BYPASS, CLK, CE, ACLR, ASET, AINIT, SCLR, SSET, SINIT, S, Q); + + parameter C_AINIT_VAL = ""; + parameter C_BYPASS_ENABLE = `c_override; + parameter C_BYPASS_LOW = 0; + parameter C_ENABLE_RLOCS = 1; + parameter C_HAS_ACLR = 0; + parameter C_HAS_AINIT = 0; + parameter C_HAS_ASET = 0; + parameter C_HAS_BYPASS = 0; + parameter C_HAS_CE = 0; + parameter C_HAS_Q = 1; + parameter C_HAS_S = 0; + parameter C_HAS_SCLR = 0; + parameter C_HAS_SINIT = 0; + parameter C_HAS_SSET = 0; + parameter C_PIPE_STAGES = 0; + parameter C_SINIT_VAL = ""; + parameter C_SYNC_ENABLE = `c_override; + parameter C_SYNC_PRIORITY = `c_clear; + parameter C_WIDTH = 16; + + + input [C_WIDTH-1 : 0] A; + input BYPASS; + input CLK; + input CE; + input ACLR; + input ASET; + input AINIT; + input SCLR; + input SSET; + input SINIT; + output [C_WIDTH : 0] S; + output [C_WIDTH : 0] Q; + + // Internal values to drive signals when input is missing + wire intBYPASS; + wire intCE; + wire intQCE; + reg [C_WIDTH : 0] intS; + reg [C_WIDTH : 0] tmpS; + wire [C_WIDTH : 0] intQ; + reg lastCLK; + + reg [C_WIDTH : 0] intQpipe [C_PIPE_STAGES+2 : 0]; + reg [C_WIDTH : 0] intQpipeend; + reg [C_WIDTH : 0] tmp_pipe1; + reg [C_WIDTH : 0] tmp_pipe2; + + wire [C_WIDTH : 0] Q = (C_HAS_Q == 1 ? intQ : {C_WIDTH{1'bx}}); + wire [C_WIDTH : 0] S = (C_HAS_S == 1 ? intS : {C_WIDTH{1'bx}}); + + // Sort out default values for missing ports + + assign intBYPASS = (C_HAS_BYPASS === 1) ? ((C_BYPASS_LOW === 1) ? !BYPASS : BYPASS) : 0; + assign intCE = defval(CE, C_HAS_CE, 1); + assign intQCE = (C_HAS_CE === 1 ? (C_HAS_BYPASS === 1 ? (C_BYPASS_ENABLE === `c_override ? CE || intBYPASS : CE) : CE) : 1'b1); + + integer j; + integer pipe, pipe1; + + // Register on output by default + C_REG_FD_V6_0 #(C_AINIT_VAL, C_ENABLE_RLOCS, C_HAS_ACLR, C_HAS_AINIT, C_HAS_ASET, + C_HAS_CE, C_HAS_SCLR, C_HAS_SINIT, C_HAS_SSET, + C_SINIT_VAL, C_SYNC_ENABLE, C_SYNC_PRIORITY, C_WIDTH + 1) + reg1 (.D(intQpipeend), .CLK(CLK), .CE(intQCE), .ACLR(ACLR), .ASET(ASET), + .AINIT(AINIT), .SCLR(SCLR), .SSET(SSET), .SINIT(SINIT), + .Q(intQ)); + + initial + begin + #1; + if(intBYPASS == 1) + begin + intS[C_WIDTH-1 : 0] = A; + intS[C_WIDTH] = A[C_WIDTH-1]; + end + else if(intBYPASS === 1'bx || is_X(A) == 1'bx) + intS = 'bx; + else + begin + tmpS[C_WIDTH-1 : 0] = ~A; + tmpS[C_WIDTH] = ~A[C_WIDTH-1]; + intS = (tmpS + 1); + end + + + if(C_PIPE_STAGES < 2) // No pipeline + intQpipeend = intS; + else // Pipeline stages required + begin + intQpipeend = intQpipe[2]; + end + end + + always @(CLK) + lastCLK <= CLK; + + always@(A or intBYPASS) + begin + if(intBYPASS == 1) + begin + intS[C_WIDTH-1 : 0] <= #1 A; + intS[C_WIDTH] <= #1 A[C_WIDTH-1]; + end + else if(intBYPASS === 1'bx || is_X(A) == 1'bx) + intS <= #1 'bx; + else + begin + tmpS[C_WIDTH-1 : 0] = ~A; + tmpS[C_WIDTH] = ~A[C_WIDTH-1]; + intS <= #1 (tmpS + 1); + end + end + + always@(posedge CLK) + begin + if(CLK === 1'b1 && lastCLK === 1'b0 && intCE === 1'b1) // OK! Update pipelines! + begin + for(pipe = 2; pipe <= C_PIPE_STAGES-1; pipe = pipe + 1) + begin + intQpipe[pipe] <= intQpipe[pipe+1]; + end + intQpipe[C_PIPE_STAGES] <= intS; + end + else if((CLK === 1'bx && lastCLK === 1'b0) || (CLK === 1'b1 && lastCLK === 1'bx) || intCE === 1'bx) // POSSIBLY Update pipelines! + begin + for(pipe = 2; pipe <= C_PIPE_STAGES-1; pipe = pipe + 1) + begin + tmp_pipe1 = intQpipe[pipe]; + tmp_pipe2 = intQpipe[pipe+1]; + for(pipe1 = 0; pipe1 < C_WIDTH; pipe1 = pipe1 + 1) + begin + if(tmp_pipe1[pipe1] !== tmp_pipe2[pipe1]) + tmp_pipe1[pipe1] = 1'bx; + end + intQpipe[pipe] <= tmp_pipe1; + end + tmp_pipe1 = intQpipe[C_PIPE_STAGES]; + for(pipe1 = 0; pipe1 < C_WIDTH; pipe1 = pipe1 + 1) + begin + if(tmp_pipe1[pipe1] !== intS[pipe1]) + tmp_pipe1[pipe1] = 1'bx; + end + intQpipe[C_PIPE_STAGES] <= tmp_pipe1; + end + end + + always@(intS or intQpipe[2]) + begin + if(C_PIPE_STAGES < 2) // No pipeline + intQpipeend <= intS; + else // Pipeline stages required + begin + intQpipeend <= intQpipe[2]; + end + end + + + function defval; + input i; + input hassig; + input val; + begin + if(hassig == 1) + defval = i; + else + defval = val; + end + endfunction + + function is_X; + input [C_WIDTH-1 : 0] i; + begin + is_X = 1'b0; + for(j = 0; j < C_WIDTH; j = j + 1) + begin + if(i[j] === 1'bx) + is_X = 1'b1; + end // loop + end + endfunction + +endmodule + +`undef c_set +`undef c_clear +`undef c_override +`undef c_no_override + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/C_TWOS_COMP_V7_0.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/C_TWOS_COMP_V7_0.v new file mode 100644 index 0000000..81a2538 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/C_TWOS_COMP_V7_0.v @@ -0,0 +1,245 @@ +// Copyright(C) 2003 by Xilinx, Inc. All rights reserved. +// This text/file contains proprietary, confidential +// information of Xilinx, Inc., is distributed under license +// from Xilinx, Inc., and may be used, copied and/or +// disclosed only pursuant to the terms of a valid license +// agreement with Xilinx, Inc. Xilinx hereby grants you +// a license to use this text/file solely for design, simulation, +// implementation and creation of design files limited +// to Xilinx devices or technologies. Use with non-Xilinx +// devices or technologies is expressly prohibited and +// immediately terminates your license unless covered by +// a separate agreement. +// +// Xilinx is providing this design, code, or information +// "as is" solely for use in developing programs and +// solutions for Xilinx devices. By providing this design, +// code, or information as one possible implementation of +// this feature, application or standard, Xilinx is making no +// representation that this implementation is free from any +// claims of infringement. You are responsible for +// obtaining any rights you may require for your implementation. +// Xilinx expressly disclaims any warranty whatsoever with +// respect to the adequacy of the implementation, including +// but not limited to any warranties or representations that this +// implementation is free from claims of infringement, implied +// warranties of merchantability or fitness for a particular +// purpose. +// +// Xilinx products are not intended for use in life support +// appliances, devices, or systems. Use in such applications are +// expressly prohibited. +// +// This copyright and support notice must be retained as part +// of this text at all times. (c) Copyright 1995-2003 Xilinx, Inc. +// All rights reserved. + + + +/* $Id: C_TWOS_COMP_V7_0.v,v 1.13 2008/09/08 20:06:14 akennedy Exp $ +-- +-- Filename - C_TWOS_COMP_V7_0.v +-- Author - Xilinx +-- Creation - 3 Feb 1999 +-- +-- Description - This file contains the Verilog behavior for the Baseblocks C_TWOS_COMP_V7_0 module +*/ + +`timescale 1ns/10ps + +`define c_set 0 +`define c_clear 1 +`define c_override 0 +`define c_no_override 1 + +module C_TWOS_COMP_V7_0 (A, BYPASS, CLK, CE, ACLR, ASET, AINIT, SCLR, SSET, SINIT, S, Q); + + parameter C_AINIT_VAL = ""; + parameter C_BYPASS_ENABLE = `c_override; + parameter C_BYPASS_LOW = 0; + parameter C_ENABLE_RLOCS = 1; + parameter C_HAS_ACLR = 0; + parameter C_HAS_AINIT = 0; + parameter C_HAS_ASET = 0; + parameter C_HAS_BYPASS = 0; + parameter C_HAS_CE = 0; + parameter C_HAS_Q = 1; + parameter C_HAS_S = 0; + parameter C_HAS_SCLR = 0; + parameter C_HAS_SINIT = 0; + parameter C_HAS_SSET = 0; + parameter C_PIPE_STAGES = 0; + parameter C_SINIT_VAL = ""; + parameter C_SYNC_ENABLE = `c_override; + parameter C_SYNC_PRIORITY = `c_clear; + parameter C_WIDTH = 16; + + + input [C_WIDTH-1 : 0] A; + input BYPASS; + input CLK; + input CE; + input ACLR; + input ASET; + input AINIT; + input SCLR; + input SSET; + input SINIT; + output [C_WIDTH : 0] S; + output [C_WIDTH : 0] Q; + + // Internal values to drive signals when input is missing + wire intBYPASS; + wire intCE; + wire intQCE; + reg [C_WIDTH : 0] intS; + reg [C_WIDTH : 0] tmpS; + wire [C_WIDTH : 0] intQ; + reg lastCLK; + + reg [C_WIDTH : 0] intQpipe [C_PIPE_STAGES+2 : 0]; + reg [C_WIDTH : 0] intQpipeend; + reg [C_WIDTH : 0] tmp_pipe1; + reg [C_WIDTH : 0] tmp_pipe2; + + wire [C_WIDTH : 0] Q = (C_HAS_Q == 1 ? intQ : {C_WIDTH{1'bx}}); + wire [C_WIDTH : 0] S = (C_HAS_S == 1 ? intS : {C_WIDTH{1'bx}}); + + // Sort out default values for missing ports + + assign intBYPASS = (C_HAS_BYPASS === 1) ? ((C_BYPASS_LOW === 1) ? !BYPASS : BYPASS) : 0; + assign intCE = defval(CE, C_HAS_CE, 1); + assign intQCE = (C_HAS_CE === 1 ? (C_HAS_BYPASS === 1 ? (C_BYPASS_ENABLE === `c_override ? CE || intBYPASS : CE) : CE) : 1'b1); + + integer j; + integer pipe, pipe1; + + // Register on output by default + C_REG_FD_V7_0 #(C_AINIT_VAL, C_ENABLE_RLOCS, C_HAS_ACLR, C_HAS_AINIT, C_HAS_ASET, + C_HAS_CE, C_HAS_SCLR, C_HAS_SINIT, C_HAS_SSET, + C_SINIT_VAL, C_SYNC_ENABLE, C_SYNC_PRIORITY, C_WIDTH + 1) + reg1 (.D(intQpipeend), .CLK(CLK), .CE(intQCE), .ACLR(ACLR), .ASET(ASET), + .AINIT(AINIT), .SCLR(SCLR), .SSET(SSET), .SINIT(SINIT), + .Q(intQ)); + + initial + begin + #1; + if(intBYPASS == 1) + begin + intS[C_WIDTH-1 : 0] = A; + intS[C_WIDTH] = A[C_WIDTH-1]; + end + else if(intBYPASS === 1'bx || is_X(A) == 1'bx) + intS = 'bx; + else + begin + tmpS[C_WIDTH-1 : 0] = ~A; + tmpS[C_WIDTH] = ~A[C_WIDTH-1]; + intS = (tmpS + 1); + end + + + if(C_PIPE_STAGES < 2) // No pipeline + intQpipeend = intS; + else // Pipeline stages required + begin + intQpipeend = intQpipe[2]; + end + end + + always @(CLK) + lastCLK <= CLK; + + always@(A or intBYPASS) + begin + if(intBYPASS == 1) + begin + intS[C_WIDTH-1 : 0] <= #1 A; + intS[C_WIDTH] <= #1 A[C_WIDTH-1]; + end + else if(intBYPASS === 1'bx || is_X(A) == 1'bx) + intS <= #1 'bx; + else + begin + tmpS[C_WIDTH-1 : 0] = ~A; + tmpS[C_WIDTH] = ~A[C_WIDTH-1]; + intS <= #1 (tmpS + 1); + end + end + + always@(posedge CLK) + begin + if(CLK === 1'b1 && lastCLK === 1'b0 && intCE === 1'b1) // OK! Update pipelines! + begin + for(pipe = 2; pipe <= C_PIPE_STAGES-1; pipe = pipe + 1) + begin + intQpipe[pipe] <= intQpipe[pipe+1]; + end + intQpipe[C_PIPE_STAGES] <= intS; + end + else if((CLK === 1'bx && lastCLK === 1'b0) || (CLK === 1'b1 && lastCLK === 1'bx) || intCE === 1'bx) // POSSIBLY Update pipelines! + begin + for(pipe = 2; pipe <= C_PIPE_STAGES-1; pipe = pipe + 1) + begin + tmp_pipe1 = intQpipe[pipe]; + tmp_pipe2 = intQpipe[pipe+1]; + for(pipe1 = 0; pipe1 < C_WIDTH; pipe1 = pipe1 + 1) + begin + if(tmp_pipe1[pipe1] !== tmp_pipe2[pipe1]) + tmp_pipe1[pipe1] = 1'bx; + end + intQpipe[pipe] <= tmp_pipe1; + end + tmp_pipe1 = intQpipe[C_PIPE_STAGES]; + for(pipe1 = 0; pipe1 < C_WIDTH; pipe1 = pipe1 + 1) + begin + if(tmp_pipe1[pipe1] !== intS[pipe1]) + tmp_pipe1[pipe1] = 1'bx; + end + intQpipe[C_PIPE_STAGES] <= tmp_pipe1; + end + end + + always@(intS or intQpipe[2]) + begin + if(C_PIPE_STAGES < 2) // No pipeline + intQpipeend <= intS; + else // Pipeline stages required + begin + intQpipeend <= intQpipe[2]; + end + end + + + function defval; + input i; + input hassig; + input val; + begin + if(hassig == 1) + defval = i; + else + defval = val; + end + endfunction + + function is_X; + input [C_WIDTH-1 : 0] i; + begin + is_X = 1'b0; + for(j = 0; j < C_WIDTH; j = j + 1) + begin + if(i[j] === 1'bx) + is_X = 1'b1; + end // loop + end + endfunction + +endmodule + +`undef c_set +`undef c_clear +`undef c_override +`undef c_no_override + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/DIST_MEM_GEN_V3_1.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/DIST_MEM_GEN_V3_1.v new file mode 100644 index 0000000..700623a --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/DIST_MEM_GEN_V3_1.v @@ -0,0 +1,529 @@ +// Copyright(C) 2004-2006 by Xilinx, Inc. All rights reserved. +// This text/file contains proprietary, confidential +// information of Xilinx, Inc., is distributed under license +// from Xilinx, Inc., and may be used, copied and/or +// disclosed only pursuant to the terms of a valid license +// agreement with Xilinx, Inc. Xilinx hereby grants you +// a license to use this text/file solely for design, simulation, +// implementation and creation of design files limited +// to Xilinx devices or technologies. Use with non-Xilinx +// devices or technologies is expressly prohibited and +// immediately terminates your license unless covered by +// a separate agreement. +// +// Xilinx is providing this design, code, or information +// "as is" solely for use in developing programs and +// solutions for Xilinx devices. By providing this design, +// code, or information as one possible implementation of +// this feature, application or standard, Xilinx is making no +// representation that this implementation is free from any +// claims of infringement. You are responsible for +// obtaining any rights you may require for your implementation. +// Xilinx expressly disclaims any warranty whatsoever with +// respect to the adequacy of the implementation, including +// but not limited to any warranties or representations that this +// implementation is free from claims of infringement, implied +// warranties of merchantability or fitness for a particular +// purpose. +// +// Xilinx products are not intended for use in life support +// appliances, devices, or systems. Use in such applications are +// expressly prohibited. +// +// This copyright and support notice must be retained as part +// of this text at all times. (c) Copyright 1995-2006 Xilinx, Inc. +// All rights reserved. + + + +/* $RCSfile: DIST_MEM_GEN_V3_1.v,v $ $Revision: 1.8 $ $Date: 2008/09/08 19:37:01 $ +-- +-- Filename - DIST_MEM_GEN_V3_1.v +-- Author - Xilinx +-- Creation - 27 Nov 2004 +-- +-- Description +-- Distributed Memory Simulation Model +*/ + + +`timescale 1ps/1ps + +`define all0s {C_WIDTH{1'b0}} +`define allXs {C_WIDTH{1'bx}} +`define c_rom 0 +`define c_sp_ram 1 +`define c_dp_ram 2 +`define c_srl16 3 + +module DIST_MEM_GEN_V3_1 (A, D, DPRA, SPRA, CLK, WE, I_CE, QSPO_CE, QDPO_CE, QDPO_CLK, QSPO_RST, QDPO_RST, QSPO_SRST, QDPO_SRST, SPO, DPO, QSPO, QDPO); + + parameter C_ADDR_WIDTH = 6; + parameter C_DEFAULT_DATA = "0"; + parameter C_DEPTH = 64; + parameter C_HAS_CLK = 1; + parameter C_HAS_D = 1; + parameter C_HAS_DPO = 0; + parameter C_HAS_DPRA = 0; + parameter C_HAS_I_CE = 0; + parameter C_HAS_QDPO = 0; + parameter C_HAS_QDPO_CE = 0; + parameter C_HAS_QDPO_CLK = 0; + parameter C_HAS_QDPO_RST = 0; + parameter C_HAS_QDPO_SRST = 0; + parameter C_HAS_QSPO = 0; + parameter C_HAS_QSPO_CE = 0; + parameter C_HAS_QSPO_RST = 0; + parameter C_HAS_QSPO_SRST = 0; + parameter C_HAS_SPO = 1; + parameter C_HAS_SPRA = 0; + parameter C_HAS_WE = 1; + parameter C_MEM_INIT_FILE = "null.mif"; + parameter C_MEM_TYPE = 1; + parameter C_QCE_JOINED = 0; + parameter C_QUALIFY_WE = 0; + parameter C_READ_MIF = 0; + parameter C_REG_A_D_INPUTS = 0; + parameter C_REG_DPRA_INPUT = 0; + parameter C_SYNC_ENABLE = 0; + parameter C_WIDTH = 16; + + + input [C_ADDR_WIDTH-1 - (C_ADDR_WIDTH>4?(4*C_HAS_SPRA):0) : 0] A; + input [C_WIDTH-1 : 0] D; + input [C_ADDR_WIDTH-1 : 0] DPRA; + input [C_ADDR_WIDTH-1 : 0] SPRA; + input CLK; + input WE; + input I_CE; + input QSPO_CE; + input QDPO_CE; + input QDPO_CLK; + input QSPO_RST; + input QDPO_RST; + input QSPO_SRST; + input QDPO_SRST; + output [C_WIDTH-1 : 0] SPO; + output [C_WIDTH-1 : 0] QSPO; + output [C_WIDTH-1 : 0] DPO; + output [C_WIDTH-1 : 0] QDPO; + + // Address signal connected to memory + wire [C_ADDR_WIDTH - 1 : 0] a_int; + + // Read Address connected to srl16 memory + wire [C_ADDR_WIDTH - 1 : 0] spra_int; + + // Input data signal connected to memory + wire [C_WIDTH - 1 : 0] d_int; + + // Internal Write Enable + wire we_int; + + // Internal QSPO Clock Enable + wire qspo_ce_int; + + // Internal QDPO Clock + wire qdpo_clk_int; + + // Internal Dual Port Read Address connected to memory + wire [C_ADDR_WIDTH - 1 : 0] dpra_int; + + // Internal QDPO Clock Enable + wire qdpo_ce_int; + + // Registered Write Enable + reg we_reg; + + // Registered Address connected to memory + reg [C_ADDR_WIDTH - 1 : 0] a_reg; + + // Registered Read Address connected to srl16 memory + reg [C_ADDR_WIDTH - 1 : 0] spra_reg; + + // Registered data signal connected to memory + reg [C_WIDTH-1 : 0] d_reg; + + // Registered QSPO Clock Enable + reg qspo_ce_reg; + + // Registered Dual Port Read Address connected to memory + reg [C_ADDR_WIDTH - 1 : 0] dpra_reg; + + // Registered QDPO Clock Enable + reg qdpo_ce_reg; + + // Internal Single Port RAM output signal + wire [C_WIDTH - 1 : 0] spo_int; + + // Internal Dual Port RAM output signal + wire [C_WIDTH - 1 : 0] dpo_int; + + // Internal ROM/Single Port RAM/SRL16 RAM + // registered output + reg [C_WIDTH - 1 : 0] qspo_int; + + // Internal Dual Port RAM registered output + reg [C_WIDTH - 1 : 0] qdpo_int; + + reg [C_WIDTH-1 : 0] ram_data [(2**C_ADDR_WIDTH)-1 : 0]; + reg [C_WIDTH-1 : 0] ram_data_tmp[C_DEPTH-1 : 0]; + + + reg [C_WIDTH-1 : 0] default_data; + + wire [C_WIDTH-1 : 0] data_sp; + wire [C_WIDTH-1 : 0] data_dp; + wire [C_WIDTH-1 : 0] data_srl; + + wire [C_WIDTH-1 : 0] data_sp_over; + wire [C_WIDTH-1 : 0] data_dp_over; + wire [C_WIDTH-1 : 0] data_srl_over; + + wire [C_ADDR_WIDTH - 1 : 0] a_over; + wire [C_ADDR_WIDTH - 1 : 0] dpra_over; + wire [C_ADDR_WIDTH - 1 : 0] spra_over; + + wire a_is_over; + wire dpra_is_over; + wire spra_is_over; + + reg [C_ADDR_WIDTH-1 : 0] max_address; + + integer i; + integer j; + integer srl_start; + integer srl_end; + + + // Initial block - initialise the memory, + // and when appropriate write content into the given address. + initial + begin + $display("WARNING: This core is supplied with a behavioral model. To model cycle-accurate behavior you must run timing simulation."); + + + default_data = 'b0; + default_data = binstr_conv(C_DEFAULT_DATA); + + // Assign that C_DEFAULT_DATA to each address in the memory. + for (i = 0; i < C_DEPTH; i = i + 1) + begin + ram_data[i] = default_data; + ram_data_tmp[i] = default_data; + end + + //Read the MIF file, and use it to initialise the content of ram_data + //if that is required. + if (C_READ_MIF) + begin + $readmemb(C_MEM_INIT_FILE, ram_data_tmp, 0, C_DEPTH-1); + + for (i = 0; i < C_DEPTH; i = i + 1) + ram_data[i] = ram_data_tmp[i]; + + end + + if (C_DEPTH != (2**C_ADDR_WIDTH)) + begin + for (i = C_DEPTH; i < (2**C_ADDR_WIDTH); i = i + 1) + ram_data[i] = 'b0; + end + + a_reg = 'b0; + we_reg = 1'b0; + spra_reg = 'b0; + d_reg = 'b0; + qspo_ce_reg = 1'b0; + dpra_reg = 'b0; + qdpo_ce_reg = 1'b0; + + qspo_int = default_data; + qdpo_int = default_data; + + max_address = C_DEPTH-1; + + srl_start = 0; + srl_end = 15; + + end // initial begin + + // Now look for writes to the memory (note that this means the + // memory is not a ROM and that the Write Enable WE is active. + always@(posedge CLK) + begin + if (C_MEM_TYPE != `c_rom && we_int) + begin + if (C_MEM_TYPE == `c_srl16) + begin + if (C_ADDR_WIDTH > 4) + begin + srl_start = a_int * 16; + if (srl_start + 16 > C_DEPTH) + srl_end = C_DEPTH - 1; + else + srl_end = (a_int*16) + 15; + end + else + begin + srl_start = 0; + srl_end = 15; + end + + for (i = srl_end; i > srl_start; i = i - 1) + ram_data[i] <= #100 ram_data[i-1]; + + ram_data[srl_start] <= #100 d_int; + end + else if (a_is_over) + begin + $display("WARNING in %m at time %d ns", $time); + $write("Writing to out of range address. "); + $display("Max address in %m is %d", C_DEPTH-1); + $display("Write will be ignored."); + end + else + ram_data[a_int] <= #100 d_int; + end // if (C_MEM_TYPE != `c_rom && we_int) + end // always@ (posedge CLK) + + // Model optional input registers, which operate in the CLK clock domain. + always @(posedge CLK) + begin + if (!C_HAS_I_CE) + begin + we_reg <= #100 WE; + a_reg <= #100 A; + spra_reg <= #100 SPRA; + d_reg <= #100 D; + end + else if (!C_QUALIFY_WE) + begin + we_reg <= #100 WE; + if (I_CE) + begin + a_reg <= #100 A; + spra_reg <= #100 SPRA; + d_reg <= #100 D; + end + end + else if (C_QUALIFY_WE) + if (I_CE) + begin + we_reg <= #100 WE; + a_reg <= #100 A; + spra_reg <= #100 SPRA; + d_reg <= #100 D; + end + + qspo_ce_reg <= #100 QSPO_CE; + end // always @ (posedge CLK) + + + assign we_int = (C_HAS_WE ? (C_REG_A_D_INPUTS ? we_reg : WE) : 1'b0); + assign d_int = (C_MEM_TYPE > 0 ? (C_REG_A_D_INPUTS ? d_reg : D) : 'b0); + assign a_int = (C_REG_A_D_INPUTS ? a_reg : A); + + assign spra_int = (C_MEM_TYPE == `c_srl16 ? (C_REG_A_D_INPUTS ? spra_reg : SPRA) : 'b0); + assign qspo_ce_int = (C_HAS_QSPO_CE ? (C_REG_A_D_INPUTS ? qspo_ce_reg : QSPO_CE) : 1'b0); + + assign qdpo_clk_int = (C_MEM_TYPE == `c_dp_ram ? + (C_HAS_QDPO_CLK == 1 ? QDPO_CLK : CLK) : 1'b0); + + always@(posedge qdpo_clk_int) + begin + if (C_QCE_JOINED) + begin + if (!C_HAS_QSPO_CE) + dpra_reg <= #100 DPRA; + else if (QSPO_CE) + dpra_reg <= #100 DPRA; + end + else + begin + if (!C_HAS_QDPO_CE) + dpra_reg <= #100 DPRA; + else if (QDPO_CE) + dpra_reg <= #100 DPRA; + end // else: !if(C_QCE_JOINED) + + qdpo_ce_reg <= #100 QDPO_CE; + + end // always@ (posedge qdpo_clk_int) + + assign dpra_int = (C_MEM_TYPE == `c_dp_ram ? + (C_REG_DPRA_INPUT == 1 ? dpra_reg : DPRA) : 1'b0); + + assign qdpo_ce_int = (C_MEM_TYPE == `c_dp_ram ? + (C_HAS_QDPO_CE ? (C_REG_DPRA_INPUT ? qdpo_ce_reg : QDPO_CE) : 1'b0) : 1'b0); + + always@(spra_is_over) + begin + if (C_MEM_TYPE == `c_srl16) + begin + $display("WARNING in %m at time %d ns: ", $time); + $write("Reading from out-of-range address. "); + $display("Max address in %m is %d", C_DEPTH-1); + end // if (C_MEM_TYPE == `c_srl16) + end // always@ (spra_int or CLK) + + always@(a_is_over) + begin + if (C_MEM_TYPE != `c_srl16) + begin + $display("WARNING in %m at time %d ns: ", $time); + $write("Reading from out-of-range address. "); + $display("Max address in %m is %d", C_DEPTH-1); + end // if (C_MEM_TYPE != `c_srl16) + end // always@ (a_int or posedge CLK) + + assign SPO = (C_HAS_SPO ? spo_int : `allXs); + + always@(dpra_is_over) + begin + if (C_MEM_TYPE == `c_dp_ram) + begin + $display("WARNING in %m at time %d ns: ", $time); + $write("Reading from out-of-range address. "); + $display("Max address in %m is %d", C_DEPTH-1); + end // if (C_MEM_TYPE == `c_dp_ram) + end // always@ (dpra_int) + + assign spo_int = (C_MEM_TYPE == `c_srl16 ? (spra_is_over ? data_srl_over : data_srl) : + (a_is_over ? data_sp_over : data_sp)); + + assign dpo_int = (C_MEM_TYPE == `c_dp_ram ? (dpra_is_over ? data_dp_over : data_dp) : `allXs); + + assign data_sp = ram_data[a_int]; + assign data_dp = ram_data[dpra_int]; + assign data_srl = ram_data[spra_int]; + + assign a_is_over = (a_int > max_address ? 1'b1 : 1'b0); + assign dpra_is_over = (dpra_int > max_address ? 1'b1 : 1'b0); + assign spra_is_over = (spra_int > max_address ? 1'b1 : 1'b0); + + assign a_over = a_int & max_address; + assign dpra_over = dpra_int & max_address; + assign spra_over = spra_int & max_address; + + assign data_sp_over = 'bx; + assign data_dp_over = 'bx; + assign data_srl_over = 'bx; + + assign DPO = (C_HAS_DPO ? dpo_int : `allXs); + + always@(posedge CLK or posedge QSPO_RST) + begin + if (C_HAS_QSPO_RST && QSPO_RST) + qspo_int <= 'b0; + + else if (C_HAS_QSPO_SRST && QSPO_SRST) + begin + if (!C_HAS_QSPO_CE) + qspo_int <= #100 'b0; + + else if (!C_SYNC_ENABLE) + qspo_int <= #100 'b0; + + else if (C_HAS_QSPO_CE && qspo_ce_int) + qspo_int <= #100 'b0; + end // if (C_HAS_QSPO_SRST && QSPO_SRST) + + else if (C_HAS_QSPO_CE && qspo_ce_int) + qspo_int <= #100 spo_int; + + else if (!C_HAS_QSPO_CE) + qspo_int <= #100 spo_int; + + end // always@ (posedge CLK or QSPO_RST) + + assign QSPO = (C_HAS_QSPO == 1 ? qspo_int : `allXs); + + always@(posedge qdpo_clk_int or posedge QDPO_RST) + begin + if (C_HAS_QDPO_RST && QDPO_RST) + qdpo_int <= 'b0; + + else if (C_HAS_QDPO_SRST && QDPO_SRST) + begin + if (!C_SYNC_ENABLE) + qdpo_int <= #100 'b0; + + else if (!C_QCE_JOINED) + begin + if (!C_HAS_QDPO_CE) + qdpo_int <= #100 'b0; + + else if (C_HAS_QDPO_CE && qdpo_ce_int) + qdpo_int <= #100 'b0; + + end + else + begin + if (!C_HAS_QSPO_CE) + qdpo_int <= #100 'b0; + + else if (C_HAS_QSPO_CE && qspo_ce_int) + qdpo_int <= #100 'b0; + + end + + end // if (C_HAS_QDPO_SRST && QDPO_SRST) + + else if (!C_QCE_JOINED) + begin + if (!C_HAS_QDPO_CE) + qdpo_int <= #100 dpo_int; + + else if (C_HAS_QDPO_CE && qdpo_ce_int) + qdpo_int <= #100 dpo_int; + end + + else if (C_QCE_JOINED) + begin + if (C_HAS_QSPO_CE && qspo_ce_int) + qdpo_int <= #100 dpo_int; + + else if (!C_HAS_QSPO_CE) + qdpo_int <= #100 dpo_int; + end + + end // always@ (qdpo_clk_int or QDPO_RST) + + assign QDPO = (C_HAS_QDPO == 1 ? qdpo_int : `allXs); + + function [C_WIDTH - 1 : 0] binstr_conv; + input [(C_WIDTH * 8) - 1 : 0] def_data; + integer index,i; + begin + index = 0; + binstr_conv = 'b0; + + for (i=C_WIDTH-1; i>=0; i=i-1) + begin + case (def_data[7:0]) + 8'b00000000 : i = -1; + 8'b00110000 : binstr_conv[index] = 1'b0; + 8'b00110001 : binstr_conv[index] = 1'b1; + default : + begin + $display("ERROR in %m at time %d ns: NOT A BINARY CHARACTER", $time); + binstr_conv[index] = 1'bx; + end + endcase // case(def_data[7:0]) + + index = index + 1; + def_data = def_data >> 8; + end // for (i=C_WIDTH-1; i>=0; i=i-1) + + end + endfunction // binstr_conv + +endmodule // DIST_MEM_GEN_V1_1 + +`undef all0s +`undef allXs +`undef c_rom +`undef c_sp_ram +`undef c_dp_ram +`undef c_srl16 diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/DIST_MEM_GEN_V3_2.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/DIST_MEM_GEN_V3_2.v new file mode 100644 index 0000000..c829f04 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/DIST_MEM_GEN_V3_2.v @@ -0,0 +1,611 @@ +// Copyright(C) 2004-2006 by Xilinx, Inc. All rights reserved. +// This text/file contains proprietary, confidential +// information of Xilinx, Inc., is distributed under license +// from Xilinx, Inc., and may be used, copied and/or +// disclosed only pursuant to the terms of a valid license +// agreement with Xilinx, Inc. Xilinx hereby grants you +// a license to use this text/file solely for design, simulation, +// implementation and creation of design files limited +// to Xilinx devices or technologies. Use with non-Xilinx +// devices or technologies is expressly prohibited and +// immediately terminates your license unless covered by +// a separate agreement. +// +// Xilinx is providing this design, code, or information +// "as is" solely for use in developing programs and +// solutions for Xilinx devices. By providing this design, +// code, or information as one possible implementation of +// this feature, application or standard, Xilinx is making no +// representation that this implementation is free from any +// claims of infringement. You are responsible for +// obtaining any rights you may require for your implementation. +// Xilinx expressly disclaims any warranty whatsoever with +// respect to the adequacy of the implementation, including +// but not limited to any warranties or representations that this +// implementation is free from claims of infringement, implied +// warranties of merchantability or fitness for a particular +// purpose. +// +// Xilinx products are not intended for use in life support +// appliances, devices, or systems. Use in such applications are +// expressly prohibited. +// +// This copyright and support notice must be retained as part +// of this text at all times. (c) Copyright 1995-2006 Xilinx, Inc. +// All rights reserved. + + + +/* $RCSfile: DIST_MEM_GEN_V3_2.v,v $ $Revision: 1.8 $ $Date: 2008/09/08 19:37:02 $ +-- +-- Filename - DIST_MEM_GEN_V3_2.v +-- Author - Xilinx +-- Creation - 27 Nov 2004 +-- +-- Description +-- Distributed Memory Simulation Model +*/ + + +`timescale 1ps/1ps + +`define all0s {C_WIDTH{1'b0}} +`define allXs {C_WIDTH{1'bx}} +`define c_rom 0 +`define c_sp_ram 1 +`define c_dp_ram 2 +`define c_srl16 3 + +module DIST_MEM_GEN_V3_2 (A, D, DPRA, SPRA, CLK, WE, I_CE, QSPO_CE, QDPO_CE, QDPO_CLK, QSPO_RST, QDPO_RST, QSPO_SRST, QDPO_SRST, SPO, DPO, QSPO, QDPO); + + parameter C_ADDR_WIDTH = 6; + parameter C_DEFAULT_DATA = "0"; + parameter C_DEPTH = 64; + parameter C_HAS_CLK = 1; + parameter C_HAS_D = 1; + parameter C_HAS_DPO = 0; + parameter C_HAS_DPRA = 0; + parameter C_HAS_I_CE = 0; + parameter C_HAS_QDPO = 0; + parameter C_HAS_QDPO_CE = 0; + parameter C_HAS_QDPO_CLK = 0; + parameter C_HAS_QDPO_RST = 0; + parameter C_HAS_QDPO_SRST = 0; + parameter C_HAS_QSPO = 0; + parameter C_HAS_QSPO_CE = 0; + parameter C_HAS_QSPO_RST = 0; + parameter C_HAS_QSPO_SRST = 0; + parameter C_HAS_SPO = 1; + parameter C_HAS_SPRA = 0; + parameter C_HAS_WE = 1; + parameter C_MEM_INIT_FILE = "null.mif"; + parameter C_MEM_TYPE = 1; + parameter C_PIPELINE_STAGES = 0; + parameter C_QCE_JOINED = 0; + parameter C_QUALIFY_WE = 0; + parameter C_READ_MIF = 0; + parameter C_REG_A_D_INPUTS = 0; + parameter C_REG_DPRA_INPUT = 0; + parameter C_SYNC_ENABLE = 0; + parameter C_WIDTH = 16; + + input [C_ADDR_WIDTH-1 - (C_ADDR_WIDTH>4?(4*C_HAS_SPRA):0) : 0] A; + input [C_WIDTH-1 : 0] D; + input [C_ADDR_WIDTH-1 : 0] DPRA; + input [C_ADDR_WIDTH-1 : 0] SPRA; + input CLK; + input WE; + input I_CE; + input QSPO_CE; + input QDPO_CE; + input QDPO_CLK; + input QSPO_RST; + input QDPO_RST; + input QSPO_SRST; + input QDPO_SRST; + output [C_WIDTH-1 : 0] SPO; + output [C_WIDTH-1 : 0] QSPO; + output [C_WIDTH-1 : 0] DPO; + output [C_WIDTH-1 : 0] QDPO; + + // Address signal connected to memory + wire [C_ADDR_WIDTH - 1 : 0] a_int; + + // Read Address connected to srl16 memory + wire [C_ADDR_WIDTH - 1 : 0] spra_int; + + // Input data signal connected to memory + wire [C_WIDTH - 1 : 0] d_int; + + // Internal Write Enable + wire we_int; + + // Internal QSPO Clock Enable + wire qspo_ce_int; + + // Internal QDPO Clock + wire qdpo_clk_int; + + // Internal Dual Port Read Address connected to memory + wire [C_ADDR_WIDTH - 1 : 0] dpra_int; + + // Internal QDPO Clock Enable + wire qdpo_ce_int; + + // Registered Write Enable + reg we_reg; + + // Registered Address connected to memory + reg [C_ADDR_WIDTH - 1 : 0] a_reg; + + // Registered Read Address connected to srl16 memory + reg [C_ADDR_WIDTH - 1 : 0] spra_reg; + + // Registered data signal connected to memory + reg [C_WIDTH-1 : 0] d_reg; + + // Registered QSPO Clock Enable + reg qspo_ce_reg; + + // Registered Dual Port Read Address connected to memory + reg [C_ADDR_WIDTH - 1 : 0] dpra_reg; + + // Registered QDPO Clock Enable + reg qdpo_ce_reg; + + // Internal Single Port RAM output signal + wire [C_WIDTH - 1 : 0] spo_int; + + // Internal Dual Port RAM output signal + wire [C_WIDTH - 1 : 0] dpo_int; + + // Internal ROM/Single Port RAM/SRL16 RAM + // registered output + reg [C_WIDTH - 1 : 0] qspo_int; + + // Pipeline registers + reg [C_WIDTH - 1 : 0] qspo_pipe; + + // Internal Dual Port RAM registered output + reg [C_WIDTH - 1 : 0] qdpo_int; + + // Pipeline registers + reg [C_WIDTH - 1 : 0] qdpo_pipe; + + reg [C_WIDTH-1 : 0] ram_data [(2**C_ADDR_WIDTH)-1 : 0]; + reg [C_WIDTH-1 : 0] ram_data_tmp[C_DEPTH-1 : 0]; + + + reg [C_WIDTH-1 : 0] default_data; + + wire [C_WIDTH-1 : 0] data_sp; + wire [C_WIDTH-1 : 0] data_dp; + wire [C_WIDTH-1 : 0] data_srl; + + wire [C_WIDTH-1 : 0] data_sp_over; + wire [C_WIDTH-1 : 0] data_dp_over; + wire [C_WIDTH-1 : 0] data_srl_over; + + wire [C_ADDR_WIDTH - 1 : 0] a_over; + wire [C_ADDR_WIDTH - 1 : 0] dpra_over; + wire [C_ADDR_WIDTH - 1 : 0] spra_over; + + wire a_is_over; + wire dpra_is_over; + wire spra_is_over; + + reg [C_ADDR_WIDTH-1 : 0] max_address; + + integer i; + integer j; + integer srl_start; + integer srl_end; + + + // Initial block - initialise the memory, + // and when appropriate write content into the given address. + initial + begin + $display("WARNING: This core is supplied with a behavioral model. To model cycle-accurate behavior you must run timing simulation."); + + + default_data = 'b0; + default_data = binstr_conv(C_DEFAULT_DATA); + + // Assign that C_DEFAULT_DATA to each address in the memory. + for (i = 0; i < C_DEPTH; i = i + 1) + begin + ram_data[i] = default_data; + ram_data_tmp[i] = default_data; + end + + //Read the MIF file, and use it to initialise the content of ram_data + //if that is required. + if (C_READ_MIF) + begin + $readmemb(C_MEM_INIT_FILE, ram_data_tmp, 0, C_DEPTH-1); + + for (i = 0; i < C_DEPTH; i = i + 1) + ram_data[i] = ram_data_tmp[i]; + + end + + if (C_DEPTH != (2**C_ADDR_WIDTH)) + begin + for (i = C_DEPTH; i < (2**C_ADDR_WIDTH); i = i + 1) + ram_data[i] = 'b0; + end + + a_reg = 'b0; + we_reg = 1'b0; + spra_reg = 'b0; + d_reg = 'b0; + qspo_ce_reg = 1'b0; + dpra_reg = 'b0; + qdpo_ce_reg = 1'b0; + + qspo_int = default_data; + qspo_pipe = 'b0; + qdpo_int = default_data; + qdpo_pipe = 'b0; + + max_address = C_DEPTH-1; + + srl_start = 0; + srl_end = 15; + + end // initial begin + + // Now look for writes to the memory (note that this means the + // memory is not a ROM and that the Write Enable WE is active. + always@(posedge CLK) + begin + if (C_MEM_TYPE != `c_rom && we_int) + begin + if (C_MEM_TYPE == `c_srl16) + begin + if (C_ADDR_WIDTH > 4) + begin + srl_start = a_int * 16; + if (srl_start + 16 > C_DEPTH) + srl_end = C_DEPTH - 1; + else + srl_end = (a_int*16) + 15; + end + else + begin + srl_start = 0; + srl_end = 15; + end + + for (i = srl_end; i > srl_start; i = i - 1) + ram_data[i] <= #100 ram_data[i-1]; + + ram_data[srl_start] <= #100 d_int; + end + else if (a_is_over) + begin + $display("WARNING in %m at time %d ns", $time); + $write("Writing to out of range address. "); + $display("Max address in %m is %d", C_DEPTH-1); + $display("Write will be ignored."); + end + else + ram_data[a_int] <= #100 d_int; + end // if (C_MEM_TYPE != `c_rom && we_int) + end // always@ (posedge CLK) + + // Model optional input registers, which operate in the CLK clock domain. + always @(posedge CLK) + begin + if (!C_HAS_I_CE) + begin + we_reg <= #100 WE; + a_reg <= #100 A; + spra_reg <= #100 SPRA; + d_reg <= #100 D; + end + else if (!C_QUALIFY_WE) + begin + we_reg <= #100 WE; + if (I_CE) + begin + a_reg <= #100 A; + spra_reg <= #100 SPRA; + d_reg <= #100 D; + end + end + else if (C_QUALIFY_WE) + if (I_CE) + begin + we_reg <= #100 WE; + a_reg <= #100 A; + spra_reg <= #100 SPRA; + d_reg <= #100 D; + end + + qspo_ce_reg <= #100 QSPO_CE; + end // always @ (posedge CLK) + + + assign we_int = (C_HAS_WE ? (C_REG_A_D_INPUTS ? we_reg : WE) : 1'b0); + assign d_int = (C_MEM_TYPE > 0 ? (C_REG_A_D_INPUTS ? d_reg : D) : 'b0); + assign a_int = (C_REG_A_D_INPUTS ? a_reg : A); + + assign spra_int = (C_MEM_TYPE == `c_srl16 ? (C_REG_A_D_INPUTS ? spra_reg : SPRA) : 'b0); + assign qspo_ce_int = (C_HAS_QSPO_CE ? (C_REG_A_D_INPUTS ? qspo_ce_reg : QSPO_CE) : 1'b0); + + assign qdpo_clk_int = (C_MEM_TYPE == `c_dp_ram ? + (C_HAS_QDPO_CLK == 1 ? QDPO_CLK : CLK) : 1'b0); + + always@(posedge qdpo_clk_int) + begin + if (C_QCE_JOINED) + begin + if (!C_HAS_QSPO_CE) + dpra_reg <= #100 DPRA; + else if (QSPO_CE) + dpra_reg <= #100 DPRA; + end + else + begin + if (!C_HAS_QDPO_CE) + dpra_reg <= #100 DPRA; + else if (QDPO_CE) + dpra_reg <= #100 DPRA; + end // else: !if(C_QCE_JOINED) + + qdpo_ce_reg <= #100 QDPO_CE; + + end // always@ (posedge qdpo_clk_int) + + assign dpra_int = (C_MEM_TYPE == `c_dp_ram ? + (C_REG_DPRA_INPUT == 1 ? dpra_reg : DPRA) : 1'b0); + + assign qdpo_ce_int = (C_MEM_TYPE == `c_dp_ram ? + (C_HAS_QDPO_CE ? (C_REG_DPRA_INPUT ? qdpo_ce_reg : QDPO_CE) : 1'b0) : 1'b0); + + always@(posedge spra_is_over) + begin + if (C_MEM_TYPE == `c_srl16) + begin + $display("WARNING in %m at time %d ns: ", $time); + $write("Reading from out-of-range address. "); + $display("Max address in %m is %d", C_DEPTH-1); + end // if (C_MEM_TYPE == `c_srl16) + end // always@ (spra_int or CLK) + + always@(posedge a_is_over) + begin + if (C_MEM_TYPE != `c_srl16) + begin + $display("WARNING in %m at time %d ns: ", $time); + $write("Reading from out-of-range address. "); + $display("Max address in %m is %d", C_DEPTH-1); + end // if (C_MEM_TYPE != `c_srl16) + end // always@ (a_int or posedge CLK) + + assign SPO = (C_HAS_SPO ? spo_int : `allXs); + + always@(posedge dpra_is_over) + begin + if (C_MEM_TYPE == `c_dp_ram) + begin + $display("WARNING in %m at time %d ns: ", $time); + $write("Reading from out-of-range address. "); + $display("Max address in %m is %d", C_DEPTH-1); + end // if (C_MEM_TYPE == `c_dp_ram) + end // always@ (dpra_int) + + assign spo_int = (C_MEM_TYPE == `c_srl16 ? (spra_is_over ? data_srl_over : data_srl) : + (a_is_over ? data_sp_over : data_sp)); + + assign dpo_int = (C_MEM_TYPE == `c_dp_ram ? (dpra_is_over ? data_dp_over : data_dp) : `allXs); + + assign data_sp = ram_data[a_int]; + assign data_dp = ram_data[dpra_int]; + assign data_srl = ram_data[spra_int]; + + assign a_is_over = (a_int > max_address ? 1'b1 : 1'b0); + assign dpra_is_over = (dpra_int > max_address ? 1'b1 : 1'b0); + assign spra_is_over = (spra_int > max_address ? 1'b1 : 1'b0); + + assign a_over = a_int & max_address; + assign dpra_over = dpra_int & max_address; + assign spra_over = spra_int & max_address; + + assign data_sp_over = 'bx; + assign data_dp_over = 'bx; + assign data_srl_over = 'bx; + + assign DPO = (C_HAS_DPO ? dpo_int : `allXs); + + always@(posedge CLK or posedge QSPO_RST) + begin + if (C_HAS_QSPO_RST && QSPO_RST) + begin + qspo_pipe <= 'b0; + qspo_int <= 'b0; + end + else if (C_HAS_QSPO_SRST && QSPO_SRST) + begin + if (!C_HAS_QSPO_CE) + begin + qspo_pipe <= #100 'b0; + qspo_int <= #100 'b0; + end + else if (!C_SYNC_ENABLE) + begin + qspo_pipe <= #100 'b0; + qspo_int <= #100 'b0; + end + else if (C_HAS_QSPO_CE && qspo_ce_int) + begin + qspo_pipe <= #100 'b0; + qspo_int <= #100 'b0; + end + end // if (C_HAS_QSPO_SRST && QSPO_SRST) + + else if (C_HAS_QSPO_CE && qspo_ce_int) + begin + if (C_PIPELINE_STAGES == 1) + begin + qspo_int <= #100 qspo_pipe; + end + else + begin + qspo_int <= #100 spo_int; + end + qspo_pipe <= #100 spo_int; + end + else if (!C_HAS_QSPO_CE) + begin + if (C_PIPELINE_STAGES == 1) + begin + qspo_int <= #100 qspo_pipe; + end + else + begin + qspo_int <= #100 spo_int; + end + qspo_pipe <= #100 spo_int; + end // if (!C_HAS_QSPO_CE) + end // always@ (posedge CLK or QSPO_RST) + + assign QSPO = (C_HAS_QSPO == 1 ? qspo_int : `allXs); + + always@(posedge qdpo_clk_int or posedge QDPO_RST) + begin + if (C_HAS_QDPO_RST && QDPO_RST) + begin + qdpo_pipe <= 'b0; + qdpo_int <= 'b0; + end + else if (C_HAS_QDPO_SRST && QDPO_SRST) + begin + if (!C_SYNC_ENABLE) + begin + qdpo_pipe <= #100 'b0; + qdpo_int <= #100 'b0; + end + else if (!C_QCE_JOINED) + begin + if (!C_HAS_QDPO_CE) + begin + qdpo_pipe <= #100 'b0; + qdpo_int <= #100 'b0; + end + else if (C_HAS_QDPO_CE && qdpo_ce_int) + begin + qdpo_pipe <= #100 'b0; + qdpo_int <= #100 'b0; + end + end + else + begin + if (!C_HAS_QSPO_CE) + begin + qdpo_pipe <= #100 'b0; + qdpo_int <= #100 'b0; + end + else if (C_HAS_QSPO_CE && qspo_ce_int) + begin + qdpo_pipe <= #100 'b0; + qdpo_int <= #100 'b0; + end + end + end // if (C_HAS_QDPO_SRST && QDPO_SRST) + + else if (!C_QCE_JOINED) + begin + if (!C_HAS_QDPO_CE) + begin + qdpo_pipe <= #100 dpo_int; + if (C_PIPELINE_STAGES == 1) + begin + qdpo_int <= #100 qdpo_pipe; + end + else + begin + qdpo_int <= #100 dpo_int; + end + end // if (!C_HAS_QDPO_CE) + else if (C_HAS_QDPO_CE && qdpo_ce_int) + begin + qdpo_pipe <= #100 dpo_int; + if (C_PIPELINE_STAGES == 1) + begin + qdpo_int <= #100 qdpo_pipe; + end + else + begin + qdpo_int <= #100 dpo_int; + end + end // if (C_HAS_QDPO_CE && qdpo_ce_int) + end // if (!C_QCE_JOINED) + else if (C_QCE_JOINED) + begin + if (C_HAS_QSPO_CE && qspo_ce_int) + begin + qdpo_pipe <= #100 dpo_int; + if (C_PIPELINE_STAGES == 1) + begin + qdpo_int <= #100 qdpo_pipe; + end + else + begin + qdpo_int <= #100 dpo_int; + end + end // if (C_HAS_QSPO_CE && qspo_ce_int) + else if (!C_HAS_QSPO_CE) + begin + qdpo_pipe <= #100 dpo_int; + if (C_PIPELINE_STAGES == 1) + begin + qdpo_int <= #100 qdpo_pipe; + end + else + begin + qdpo_int <= #100 dpo_int; + end + end // if (!C_HAS_QSPO_CE) + end // if (C_QCE_JOINED) + end // always@ (posedge qdpo_clk_int or posedge QDPO_RST) + + assign QDPO = (C_HAS_QDPO == 1 ? qdpo_int : `allXs); + + function [C_WIDTH - 1 : 0] binstr_conv; + input [(C_WIDTH * 8) - 1 : 0] def_data; + integer index,i; + begin + index = 0; + binstr_conv = 'b0; + + for (i=C_WIDTH-1; i>=0; i=i-1) + begin + case (def_data[7:0]) + 8'b00000000 : i = -1; + 8'b00110000 : binstr_conv[index] = 1'b0; + 8'b00110001 : binstr_conv[index] = 1'b1; + default : + begin + $display("ERROR in %m at time %d ns: NOT A BINARY CHARACTER", $time); + binstr_conv[index] = 1'bx; + end + endcase // case(def_data[7:0]) + + index = index + 1; + def_data = def_data >> 8; + end // for (i=C_WIDTH-1; i>=0; i=i-1) + + end + endfunction // binstr_conv + +endmodule // DIST_MEM_GEN_V3_2 + +`undef all0s +`undef allXs +`undef c_rom +`undef c_sp_ram +`undef c_dp_ram +`undef c_srl16 diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/DIST_MEM_GEN_V3_3.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/DIST_MEM_GEN_V3_3.v new file mode 100644 index 0000000..f111c79 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/DIST_MEM_GEN_V3_3.v @@ -0,0 +1,611 @@ +// Copyright(C) 2004-2006 by Xilinx, Inc. All rights reserved. +// This text/file contains proprietary, confidential +// information of Xilinx, Inc., is distributed under license +// from Xilinx, Inc., and may be used, copied and/or +// disclosed only pursuant to the terms of a valid license +// agreement with Xilinx, Inc. Xilinx hereby grants you +// a license to use this text/file solely for design, simulation, +// implementation and creation of design files limited +// to Xilinx devices or technologies. Use with non-Xilinx +// devices or technologies is expressly prohibited and +// immediately terminates your license unless covered by +// a separate agreement. +// +// Xilinx is providing this design, code, or information +// "as is" solely for use in developing programs and +// solutions for Xilinx devices. By providing this design, +// code, or information as one possible implementation of +// this feature, application or standard, Xilinx is making no +// representation that this implementation is free from any +// claims of infringement. You are responsible for +// obtaining any rights you may require for your implementation. +// Xilinx expressly disclaims any warranty whatsoever with +// respect to the adequacy of the implementation, including +// but not limited to any warranties or representations that this +// implementation is free from claims of infringement, implied +// warranties of merchantability or fitness for a particular +// purpose. +// +// Xilinx products are not intended for use in life support +// appliances, devices, or systems. Use in such applications are +// expressly prohibited. +// +// This copyright and support notice must be retained as part +// of this text at all times. (c) Copyright 1995-2006 Xilinx, Inc. +// All rights reserved. + + + +/* $RCSfile: DIST_MEM_GEN_V3_3.v,v $ $Revision: 1.7 $ $Date: 2008/09/09 19:56:22 $ +-- +-- Filename - DIST_MEM_GEN_V3_3.v +-- Author - Xilinx +-- Creation - 27 Nov 2004 +-- +-- Description +-- Distributed Memory Simulation Model +*/ + + +`timescale 1ps/1ps + +`define all0s {C_WIDTH{1'b0}} +`define allXs {C_WIDTH{1'bx}} +`define c_rom 0 +`define c_sp_ram 1 +`define c_dp_ram 2 +`define c_srl16 3 + +module DIST_MEM_GEN_V3_3 (A, D, DPRA, SPRA, CLK, WE, I_CE, QSPO_CE, QDPO_CE, QDPO_CLK, QSPO_RST, QDPO_RST, QSPO_SRST, QDPO_SRST, SPO, DPO, QSPO, QDPO); + + parameter C_ADDR_WIDTH = 6; + parameter C_DEFAULT_DATA = "0"; + parameter C_DEPTH = 64; + parameter C_HAS_CLK = 1; + parameter C_HAS_D = 1; + parameter C_HAS_DPO = 0; + parameter C_HAS_DPRA = 0; + parameter C_HAS_I_CE = 0; + parameter C_HAS_QDPO = 0; + parameter C_HAS_QDPO_CE = 0; + parameter C_HAS_QDPO_CLK = 0; + parameter C_HAS_QDPO_RST = 0; + parameter C_HAS_QDPO_SRST = 0; + parameter C_HAS_QSPO = 0; + parameter C_HAS_QSPO_CE = 0; + parameter C_HAS_QSPO_RST = 0; + parameter C_HAS_QSPO_SRST = 0; + parameter C_HAS_SPO = 1; + parameter C_HAS_SPRA = 0; + parameter C_HAS_WE = 1; + parameter C_MEM_INIT_FILE = "null.mif"; + parameter C_MEM_TYPE = 1; + parameter C_PIPELINE_STAGES = 0; + parameter C_QCE_JOINED = 0; + parameter C_QUALIFY_WE = 0; + parameter C_READ_MIF = 0; + parameter C_REG_A_D_INPUTS = 0; + parameter C_REG_DPRA_INPUT = 0; + parameter C_SYNC_ENABLE = 0; + parameter C_WIDTH = 16; + + input [C_ADDR_WIDTH-1 - (C_ADDR_WIDTH>4?(4*C_HAS_SPRA):0) : 0] A; + input [C_WIDTH-1 : 0] D; + input [C_ADDR_WIDTH-1 : 0] DPRA; + input [C_ADDR_WIDTH-1 : 0] SPRA; + input CLK; + input WE; + input I_CE; + input QSPO_CE; + input QDPO_CE; + input QDPO_CLK; + input QSPO_RST; + input QDPO_RST; + input QSPO_SRST; + input QDPO_SRST; + output [C_WIDTH-1 : 0] SPO; + output [C_WIDTH-1 : 0] QSPO; + output [C_WIDTH-1 : 0] DPO; + output [C_WIDTH-1 : 0] QDPO; + + // Address signal connected to memory + wire [C_ADDR_WIDTH - 1 : 0] a_int; + + // Read Address connected to srl16 memory + wire [C_ADDR_WIDTH - 1 : 0] spra_int; + + // Input data signal connected to memory + wire [C_WIDTH - 1 : 0] d_int; + + // Internal Write Enable + wire we_int; + + // Internal QSPO Clock Enable + wire qspo_ce_int; + + // Internal QDPO Clock + wire qdpo_clk_int; + + // Internal Dual Port Read Address connected to memory + wire [C_ADDR_WIDTH - 1 : 0] dpra_int; + + // Internal QDPO Clock Enable + wire qdpo_ce_int; + + // Registered Write Enable + reg we_reg; + + // Registered Address connected to memory + reg [C_ADDR_WIDTH - 1 : 0] a_reg; + + // Registered Read Address connected to srl16 memory + reg [C_ADDR_WIDTH - 1 : 0] spra_reg; + + // Registered data signal connected to memory + reg [C_WIDTH-1 : 0] d_reg; + + // Registered QSPO Clock Enable + reg qspo_ce_reg; + + // Registered Dual Port Read Address connected to memory + reg [C_ADDR_WIDTH - 1 : 0] dpra_reg; + + // Registered QDPO Clock Enable + reg qdpo_ce_reg; + + // Internal Single Port RAM output signal + wire [C_WIDTH - 1 : 0] spo_int; + + // Internal Dual Port RAM output signal + wire [C_WIDTH - 1 : 0] dpo_int; + + // Internal ROM/Single Port RAM/SRL16 RAM + // registered output + reg [C_WIDTH - 1 : 0] qspo_int; + + // Pipeline registers + reg [C_WIDTH - 1 : 0] qspo_pipe; + + // Internal Dual Port RAM registered output + reg [C_WIDTH - 1 : 0] qdpo_int; + + // Pipeline registers + reg [C_WIDTH - 1 : 0] qdpo_pipe; + + reg [C_WIDTH-1 : 0] ram_data [(2**C_ADDR_WIDTH)-1 : 0]; + reg [C_WIDTH-1 : 0] ram_data_tmp[C_DEPTH-1 : 0]; + + + reg [C_WIDTH-1 : 0] default_data; + + wire [C_WIDTH-1 : 0] data_sp; + wire [C_WIDTH-1 : 0] data_dp; + wire [C_WIDTH-1 : 0] data_srl; + + wire [C_WIDTH-1 : 0] data_sp_over; + wire [C_WIDTH-1 : 0] data_dp_over; + wire [C_WIDTH-1 : 0] data_srl_over; + + wire [C_ADDR_WIDTH - 1 : 0] a_over; + wire [C_ADDR_WIDTH - 1 : 0] dpra_over; + wire [C_ADDR_WIDTH - 1 : 0] spra_over; + + wire a_is_over; + wire dpra_is_over; + wire spra_is_over; + + reg [C_ADDR_WIDTH-1 : 0] max_address; + + integer i; + integer j; + integer srl_start; + integer srl_end; + + + // Initial block - initialise the memory, + // and when appropriate write content into the given address. + initial + begin + $display("WARNING: This core is supplied with a behavioral model. To model cycle-accurate behavior you must run timing simulation."); + + + default_data = 'b0; + default_data = binstr_conv(C_DEFAULT_DATA); + + // Assign that C_DEFAULT_DATA to each address in the memory. + for (i = 0; i < C_DEPTH; i = i + 1) + begin + ram_data[i] = default_data; + ram_data_tmp[i] = default_data; + end + + //Read the MIF file, and use it to initialise the content of ram_data + //if that is required. + if (C_READ_MIF) + begin + $readmemb(C_MEM_INIT_FILE, ram_data_tmp, 0, C_DEPTH-1); + + for (i = 0; i < C_DEPTH; i = i + 1) + ram_data[i] = ram_data_tmp[i]; + + end + + if (C_DEPTH != (2**C_ADDR_WIDTH)) + begin + for (i = C_DEPTH; i < (2**C_ADDR_WIDTH); i = i + 1) + ram_data[i] = 'b0; + end + + a_reg = 'b0; + we_reg = 1'b0; + spra_reg = 'b0; + d_reg = 'b0; + qspo_ce_reg = 1'b0; + dpra_reg = 'b0; + qdpo_ce_reg = 1'b0; + + qspo_int = default_data; + qspo_pipe = 'b0; + qdpo_int = default_data; + qdpo_pipe = 'b0; + + max_address = C_DEPTH-1; + + srl_start = 0; + srl_end = 15; + + end // initial begin + + // Now look for writes to the memory (note that this means the + // memory is not a ROM and that the Write Enable WE is active. + always@(posedge CLK) + begin + if (C_MEM_TYPE != `c_rom && we_int) + begin + if (C_MEM_TYPE == `c_srl16) + begin + if (C_ADDR_WIDTH > 4) + begin + srl_start = a_int * 16; + if (srl_start + 16 > C_DEPTH) + srl_end = C_DEPTH - 1; + else + srl_end = (a_int*16) + 15; + end + else + begin + srl_start = 0; + srl_end = 15; + end + + for (i = srl_end; i > srl_start; i = i - 1) + ram_data[i] <= #100 ram_data[i-1]; + + ram_data[srl_start] <= #100 d_int; + end + else if (a_is_over) + begin + $display("WARNING in %m at time %d ns", $time); + $write("Writing to out of range address. "); + $display("Max address in %m is %d", C_DEPTH-1); + $display("Write will be ignored."); + end + else + ram_data[a_int] <= #100 d_int; + end // if (C_MEM_TYPE != `c_rom && we_int) + end // always@ (posedge CLK) + + // Model optional input registers, which operate in the CLK clock domain. + always @(posedge CLK) + begin + if (!C_HAS_I_CE) + begin + we_reg <= #100 WE; + a_reg <= #100 A; + spra_reg <= #100 SPRA; + d_reg <= #100 D; + end + else if (!C_QUALIFY_WE) + begin + we_reg <= #100 WE; + if (I_CE) + begin + a_reg <= #100 A; + spra_reg <= #100 SPRA; + d_reg <= #100 D; + end + end + else if (C_QUALIFY_WE) + if (I_CE) + begin + we_reg <= #100 WE; + a_reg <= #100 A; + spra_reg <= #100 SPRA; + d_reg <= #100 D; + end + + qspo_ce_reg <= #100 QSPO_CE; + end // always @ (posedge CLK) + + + assign we_int = (C_HAS_WE ? (C_REG_A_D_INPUTS ? we_reg : WE) : 1'b0); + assign d_int = (C_MEM_TYPE > 0 ? (C_REG_A_D_INPUTS ? d_reg : D) : 'b0); + assign a_int = (C_REG_A_D_INPUTS ? a_reg : A); + + assign spra_int = (C_MEM_TYPE == `c_srl16 ? (C_REG_A_D_INPUTS ? spra_reg : SPRA) : 'b0); + assign qspo_ce_int = (C_HAS_QSPO_CE ? (C_REG_A_D_INPUTS ? qspo_ce_reg : QSPO_CE) : 1'b0); + + assign qdpo_clk_int = (C_MEM_TYPE == `c_dp_ram ? + (C_HAS_QDPO_CLK == 1 ? QDPO_CLK : CLK) : 1'b0); + + always@(posedge qdpo_clk_int) + begin + if (C_QCE_JOINED) + begin + if (!C_HAS_QSPO_CE) + dpra_reg <= #100 DPRA; + else if (QSPO_CE) + dpra_reg <= #100 DPRA; + end + else + begin + if (!C_HAS_QDPO_CE) + dpra_reg <= #100 DPRA; + else if (QDPO_CE) + dpra_reg <= #100 DPRA; + end // else: !if(C_QCE_JOINED) + + qdpo_ce_reg <= #100 QDPO_CE; + + end // always@ (posedge qdpo_clk_int) + + assign dpra_int = (C_MEM_TYPE == `c_dp_ram ? + (C_REG_DPRA_INPUT == 1 ? dpra_reg : DPRA) : 1'b0); + + assign qdpo_ce_int = (C_MEM_TYPE == `c_dp_ram ? + (C_HAS_QDPO_CE ? (C_REG_DPRA_INPUT ? qdpo_ce_reg : QDPO_CE) : 1'b0) : 1'b0); + + always@(posedge spra_is_over) + begin + if (C_MEM_TYPE == `c_srl16) + begin + $display("WARNING in %m at time %d ns: ", $time); + $write("Reading from out-of-range address. "); + $display("Max address in %m is %d", C_DEPTH-1); + end // if (C_MEM_TYPE == `c_srl16) + end // always@ (spra_int or CLK) + + always@(posedge a_is_over) + begin + if (C_MEM_TYPE != `c_srl16) + begin + $display("WARNING in %m at time %d ns: ", $time); + $write("Reading from out-of-range address. "); + $display("Max address in %m is %d", C_DEPTH-1); + end // if (C_MEM_TYPE != `c_srl16) + end // always@ (a_int or posedge CLK) + + assign SPO = (C_HAS_SPO ? spo_int : `allXs); + + always@(posedge dpra_is_over) + begin + if (C_MEM_TYPE == `c_dp_ram) + begin + $display("WARNING in %m at time %d ns: ", $time); + $write("Reading from out-of-range address. "); + $display("Max address in %m is %d", C_DEPTH-1); + end // if (C_MEM_TYPE == `c_dp_ram) + end // always@ (dpra_int) + + assign spo_int = (C_MEM_TYPE == `c_srl16 ? (spra_is_over ? data_srl_over : data_srl) : + (a_is_over ? data_sp_over : data_sp)); + + assign dpo_int = (C_MEM_TYPE == `c_dp_ram ? (dpra_is_over ? data_dp_over : data_dp) : `allXs); + + assign data_sp = ram_data[a_int]; + assign data_dp = ram_data[dpra_int]; + assign data_srl = ram_data[spra_int]; + + assign a_is_over = (a_int > max_address ? 1'b1 : 1'b0); + assign dpra_is_over = (dpra_int > max_address ? 1'b1 : 1'b0); + assign spra_is_over = (spra_int > max_address ? 1'b1 : 1'b0); + + assign a_over = a_int & max_address; + assign dpra_over = dpra_int & max_address; + assign spra_over = spra_int & max_address; + + assign data_sp_over = 'bx; + assign data_dp_over = 'bx; + assign data_srl_over = 'bx; + + assign DPO = (C_HAS_DPO ? dpo_int : `allXs); + + always@(posedge CLK or posedge QSPO_RST) + begin + if (C_HAS_QSPO_RST && QSPO_RST) + begin + qspo_pipe <= 'b0; + qspo_int <= 'b0; + end + else if (C_HAS_QSPO_SRST && QSPO_SRST) + begin + if (!C_HAS_QSPO_CE) + begin + qspo_pipe <= #100 'b0; + qspo_int <= #100 'b0; + end + else if (!C_SYNC_ENABLE) + begin + qspo_pipe <= #100 'b0; + qspo_int <= #100 'b0; + end + else if (C_HAS_QSPO_CE && qspo_ce_int) + begin + qspo_pipe <= #100 'b0; + qspo_int <= #100 'b0; + end + end // if (C_HAS_QSPO_SRST && QSPO_SRST) + + else if (C_HAS_QSPO_CE && qspo_ce_int) + begin + if (C_PIPELINE_STAGES == 1) + begin + qspo_int <= #100 qspo_pipe; + end + else + begin + qspo_int <= #100 spo_int; + end + qspo_pipe <= #100 spo_int; + end + else if (!C_HAS_QSPO_CE) + begin + if (C_PIPELINE_STAGES == 1) + begin + qspo_int <= #100 qspo_pipe; + end + else + begin + qspo_int <= #100 spo_int; + end + qspo_pipe <= #100 spo_int; + end // if (!C_HAS_QSPO_CE) + end // always@ (posedge CLK or QSPO_RST) + + assign QSPO = (C_HAS_QSPO == 1 ? qspo_int : `allXs); + + always@(posedge qdpo_clk_int or posedge QDPO_RST) + begin + if (C_HAS_QDPO_RST && QDPO_RST) + begin + qdpo_pipe <= 'b0; + qdpo_int <= 'b0; + end + else if (C_HAS_QDPO_SRST && QDPO_SRST) + begin + if (!C_SYNC_ENABLE) + begin + qdpo_pipe <= #100 'b0; + qdpo_int <= #100 'b0; + end + else if (!C_QCE_JOINED) + begin + if (!C_HAS_QDPO_CE) + begin + qdpo_pipe <= #100 'b0; + qdpo_int <= #100 'b0; + end + else if (C_HAS_QDPO_CE && qdpo_ce_int) + begin + qdpo_pipe <= #100 'b0; + qdpo_int <= #100 'b0; + end + end + else + begin + if (!C_HAS_QSPO_CE) + begin + qdpo_pipe <= #100 'b0; + qdpo_int <= #100 'b0; + end + else if (C_HAS_QSPO_CE && qspo_ce_int) + begin + qdpo_pipe <= #100 'b0; + qdpo_int <= #100 'b0; + end + end + end // if (C_HAS_QDPO_SRST && QDPO_SRST) + + else if (!C_QCE_JOINED) + begin + if (!C_HAS_QDPO_CE) + begin + qdpo_pipe <= #100 dpo_int; + if (C_PIPELINE_STAGES == 1) + begin + qdpo_int <= #100 qdpo_pipe; + end + else + begin + qdpo_int <= #100 dpo_int; + end + end // if (!C_HAS_QDPO_CE) + else if (C_HAS_QDPO_CE && qdpo_ce_int) + begin + qdpo_pipe <= #100 dpo_int; + if (C_PIPELINE_STAGES == 1) + begin + qdpo_int <= #100 qdpo_pipe; + end + else + begin + qdpo_int <= #100 dpo_int; + end + end // if (C_HAS_QDPO_CE && qdpo_ce_int) + end // if (!C_QCE_JOINED) + else if (C_QCE_JOINED) + begin + if (C_HAS_QSPO_CE && qspo_ce_int) + begin + qdpo_pipe <= #100 dpo_int; + if (C_PIPELINE_STAGES == 1) + begin + qdpo_int <= #100 qdpo_pipe; + end + else + begin + qdpo_int <= #100 dpo_int; + end + end // if (C_HAS_QSPO_CE && qspo_ce_int) + else if (!C_HAS_QSPO_CE) + begin + qdpo_pipe <= #100 dpo_int; + if (C_PIPELINE_STAGES == 1) + begin + qdpo_int <= #100 qdpo_pipe; + end + else + begin + qdpo_int <= #100 dpo_int; + end + end // if (!C_HAS_QSPO_CE) + end // if (C_QCE_JOINED) + end // always@ (posedge qdpo_clk_int or posedge QDPO_RST) + + assign QDPO = (C_HAS_QDPO == 1 ? qdpo_int : `allXs); + + function [C_WIDTH - 1 : 0] binstr_conv; + input [(C_WIDTH * 8) - 1 : 0] def_data; + integer index,i; + begin + index = 0; + binstr_conv = 'b0; + + for (i=C_WIDTH-1; i>=0; i=i-1) + begin + case (def_data[7:0]) + 8'b00000000 : i = -1; + 8'b00110000 : binstr_conv[index] = 1'b0; + 8'b00110001 : binstr_conv[index] = 1'b1; + default : + begin + $display("ERROR in %m at time %d ns: NOT A BINARY CHARACTER", $time); + binstr_conv[index] = 1'bx; + end + endcase // case(def_data[7:0]) + + index = index + 1; + def_data = def_data >> 8; + end // for (i=C_WIDTH-1; i>=0; i=i-1) + + end + endfunction // binstr_conv + +endmodule // DIST_MEM_GEN_V3_3 + +`undef all0s +`undef allXs +`undef c_rom +`undef c_sp_ram +`undef c_dp_ram +`undef c_srl16 diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/DIST_MEM_GEN_V3_4.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/DIST_MEM_GEN_V3_4.v new file mode 100644 index 0000000..c7e5363 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/DIST_MEM_GEN_V3_4.v @@ -0,0 +1,611 @@ +// Copyright(C) 2004-2006 by Xilinx, Inc. All rights reserved. +// This text/file contains proprietary, confidential +// information of Xilinx, Inc., is distributed under license +// from Xilinx, Inc., and may be used, copied and/or +// disclosed only pursuant to the terms of a valid license +// agreement with Xilinx, Inc. Xilinx hereby grants you +// a license to use this text/file solely for design, simulation, +// implementation and creation of design files limited +// to Xilinx devices or technologies. Use with non-Xilinx +// devices or technologies is expressly prohibited and +// immediately terminates your license unless covered by +// a separate agreement. +// +// Xilinx is providing this design, code, or information +// "as is" solely for use in developing programs and +// solutions for Xilinx devices. By providing this design, +// code, or information as one possible implementation of +// this feature, application or standard, Xilinx is making no +// representation that this implementation is free from any +// claims of infringement. You are responsible for +// obtaining any rights you may require for your implementation. +// Xilinx expressly disclaims any warranty whatsoever with +// respect to the adequacy of the implementation, including +// but not limited to any warranties or representations that this +// implementation is free from claims of infringement, implied +// warranties of merchantability or fitness for a particular +// purpose. +// +// Xilinx products are not intended for use in life support +// appliances, devices, or systems. Use in such applications are +// expressly prohibited. +// +// This copyright and support notice must be retained as part +// of this text at all times. (c) Copyright 1995-2006 Xilinx, Inc. +// All rights reserved. + + + +/* $RCSfile: DIST_MEM_GEN_V3_4.v,v $ $Revision: 1.3 $ $Date: 2008/09/09 20:24:20 $ +-- +-- Filename - DIST_MEM_GEN_V3_4.v +-- Author - Xilinx +-- Creation - 27 Nov 2004 +-- +-- Description +-- Distributed Memory Simulation Model +*/ + + +`timescale 1ps/1ps + +`define all0s {C_WIDTH{1'b0}} +`define allXs {C_WIDTH{1'bx}} +`define c_rom 0 +`define c_sp_ram 1 +`define c_dp_ram 2 +`define c_srl16 3 + +module DIST_MEM_GEN_V3_4 (A, D, DPRA, SPRA, CLK, WE, I_CE, QSPO_CE, QDPO_CE, QDPO_CLK, QSPO_RST, QDPO_RST, QSPO_SRST, QDPO_SRST, SPO, DPO, QSPO, QDPO); + + parameter C_ADDR_WIDTH = 6; + parameter C_DEFAULT_DATA = "0"; + parameter C_DEPTH = 64; + parameter C_HAS_CLK = 1; + parameter C_HAS_D = 1; + parameter C_HAS_DPO = 0; + parameter C_HAS_DPRA = 0; + parameter C_HAS_I_CE = 0; + parameter C_HAS_QDPO = 0; + parameter C_HAS_QDPO_CE = 0; + parameter C_HAS_QDPO_CLK = 0; + parameter C_HAS_QDPO_RST = 0; + parameter C_HAS_QDPO_SRST = 0; + parameter C_HAS_QSPO = 0; + parameter C_HAS_QSPO_CE = 0; + parameter C_HAS_QSPO_RST = 0; + parameter C_HAS_QSPO_SRST = 0; + parameter C_HAS_SPO = 1; + parameter C_HAS_SPRA = 0; + parameter C_HAS_WE = 1; + parameter C_MEM_INIT_FILE = "null.mif"; + parameter C_MEM_TYPE = 1; + parameter C_PIPELINE_STAGES = 0; + parameter C_QCE_JOINED = 0; + parameter C_QUALIFY_WE = 0; + parameter C_READ_MIF = 0; + parameter C_REG_A_D_INPUTS = 0; + parameter C_REG_DPRA_INPUT = 0; + parameter C_SYNC_ENABLE = 0; + parameter C_WIDTH = 16; + + input [C_ADDR_WIDTH-1 - (C_ADDR_WIDTH>4?(4*C_HAS_SPRA):0) : 0] A; + input [C_WIDTH-1 : 0] D; + input [C_ADDR_WIDTH-1 : 0] DPRA; + input [C_ADDR_WIDTH-1 : 0] SPRA; + input CLK; + input WE; + input I_CE; + input QSPO_CE; + input QDPO_CE; + input QDPO_CLK; + input QSPO_RST; + input QDPO_RST; + input QSPO_SRST; + input QDPO_SRST; + output [C_WIDTH-1 : 0] SPO; + output [C_WIDTH-1 : 0] QSPO; + output [C_WIDTH-1 : 0] DPO; + output [C_WIDTH-1 : 0] QDPO; + + // Address signal connected to memory + wire [C_ADDR_WIDTH - 1 : 0] a_int; + + // Read Address connected to srl16 memory + wire [C_ADDR_WIDTH - 1 : 0] spra_int; + + // Input data signal connected to memory + wire [C_WIDTH - 1 : 0] d_int; + + // Internal Write Enable + wire we_int; + + // Internal QSPO Clock Enable + wire qspo_ce_int; + + // Internal QDPO Clock + wire qdpo_clk_int; + + // Internal Dual Port Read Address connected to memory + wire [C_ADDR_WIDTH - 1 : 0] dpra_int; + + // Internal QDPO Clock Enable + wire qdpo_ce_int; + + // Registered Write Enable + reg we_reg; + + // Registered Address connected to memory + reg [C_ADDR_WIDTH - 1 : 0] a_reg; + + // Registered Read Address connected to srl16 memory + reg [C_ADDR_WIDTH - 1 : 0] spra_reg; + + // Registered data signal connected to memory + reg [C_WIDTH-1 : 0] d_reg; + + // Registered QSPO Clock Enable + reg qspo_ce_reg; + + // Registered Dual Port Read Address connected to memory + reg [C_ADDR_WIDTH - 1 : 0] dpra_reg; + + // Registered QDPO Clock Enable + reg qdpo_ce_reg; + + // Internal Single Port RAM output signal + wire [C_WIDTH - 1 : 0] spo_int; + + // Internal Dual Port RAM output signal + wire [C_WIDTH - 1 : 0] dpo_int; + + // Internal ROM/Single Port RAM/SRL16 RAM + // registered output + reg [C_WIDTH - 1 : 0] qspo_int; + + // Pipeline registers + reg [C_WIDTH - 1 : 0] qspo_pipe; + + // Internal Dual Port RAM registered output + reg [C_WIDTH - 1 : 0] qdpo_int; + + // Pipeline registers + reg [C_WIDTH - 1 : 0] qdpo_pipe; + + reg [C_WIDTH-1 : 0] ram_data [(2**C_ADDR_WIDTH)-1 : 0]; + reg [C_WIDTH-1 : 0] ram_data_tmp[C_DEPTH-1 : 0]; + + + reg [C_WIDTH-1 : 0] default_data; + + wire [C_WIDTH-1 : 0] data_sp; + wire [C_WIDTH-1 : 0] data_dp; + wire [C_WIDTH-1 : 0] data_srl; + + wire [C_WIDTH-1 : 0] data_sp_over; + wire [C_WIDTH-1 : 0] data_dp_over; + wire [C_WIDTH-1 : 0] data_srl_over; + + wire [C_ADDR_WIDTH - 1 : 0] a_over; + wire [C_ADDR_WIDTH - 1 : 0] dpra_over; + wire [C_ADDR_WIDTH - 1 : 0] spra_over; + + wire a_is_over; + wire dpra_is_over; + wire spra_is_over; + + reg [C_ADDR_WIDTH-1 : 0] max_address; + + integer i; + integer j; + integer srl_start; + integer srl_end; + + + // Initial block - initialise the memory, + // and when appropriate write content into the given address. + initial + begin + $display("WARNING: This core is supplied with a behavioral model. To model cycle-accurate behavior you must run timing simulation."); + + + default_data = 'b0; + default_data = binstr_conv(C_DEFAULT_DATA); + + // Assign that C_DEFAULT_DATA to each address in the memory. + for (i = 0; i < C_DEPTH; i = i + 1) + begin + ram_data[i] = default_data; + ram_data_tmp[i] = default_data; + end + + //Read the MIF file, and use it to initialise the content of ram_data + //if that is required. + if (C_READ_MIF) + begin + $readmemb(C_MEM_INIT_FILE, ram_data_tmp, 0, C_DEPTH-1); + + for (i = 0; i < C_DEPTH; i = i + 1) + ram_data[i] = ram_data_tmp[i]; + + end + + if (C_DEPTH != (2**C_ADDR_WIDTH)) + begin + for (i = C_DEPTH; i < (2**C_ADDR_WIDTH); i = i + 1) + ram_data[i] = 'b0; + end + + a_reg = 'b0; + we_reg = 1'b0; + spra_reg = 'b0; + d_reg = 'b0; + qspo_ce_reg = 1'b0; + dpra_reg = 'b0; + qdpo_ce_reg = 1'b0; + + qspo_int = default_data; + qspo_pipe = 'b0; + qdpo_int = default_data; + qdpo_pipe = 'b0; + + max_address = C_DEPTH-1; + + srl_start = 0; + srl_end = 15; + + end // initial begin + + // Now look for writes to the memory (note that this means the + // memory is not a ROM and that the Write Enable WE is active. + always@(posedge CLK) + begin + if (C_MEM_TYPE != `c_rom && we_int) + begin + if (C_MEM_TYPE == `c_srl16) + begin + if (C_ADDR_WIDTH > 4) + begin + srl_start = a_int * 16; + if (srl_start + 16 > C_DEPTH) + srl_end = C_DEPTH - 1; + else + srl_end = (a_int*16) + 15; + end + else + begin + srl_start = 0; + srl_end = 15; + end + + for (i = srl_end; i > srl_start; i = i - 1) + ram_data[i] <= #100 ram_data[i-1]; + + ram_data[srl_start] <= #100 d_int; + end + else if (a_is_over) + begin + $display("WARNING in %m at time %d ns", $time); + $write("Writing to out of range address. "); + $display("Max address in %m is %d", C_DEPTH-1); + $display("Write will be ignored."); + end + else + ram_data[a_int] <= #100 d_int; + end // if (C_MEM_TYPE != `c_rom && we_int) + end // always@ (posedge CLK) + + // Model optional input registers, which operate in the CLK clock domain. + always @(posedge CLK) + begin + if (!C_HAS_I_CE) + begin + we_reg <= #100 WE; + a_reg <= #100 A; + spra_reg <= #100 SPRA; + d_reg <= #100 D; + end + else if (!C_QUALIFY_WE) + begin + we_reg <= #100 WE; + if (I_CE) + begin + a_reg <= #100 A; + spra_reg <= #100 SPRA; + d_reg <= #100 D; + end + end + else if (C_QUALIFY_WE) + if (I_CE) + begin + we_reg <= #100 WE; + a_reg <= #100 A; + spra_reg <= #100 SPRA; + d_reg <= #100 D; + end + + qspo_ce_reg <= #100 QSPO_CE; + end // always @ (posedge CLK) + + + assign we_int = (C_HAS_WE ? (C_REG_A_D_INPUTS ? we_reg : WE) : 1'b0); + assign d_int = (C_MEM_TYPE > 0 ? (C_REG_A_D_INPUTS ? d_reg : D) : 'b0); + assign a_int = (C_REG_A_D_INPUTS ? a_reg : A); + + assign spra_int = (C_MEM_TYPE == `c_srl16 ? (C_REG_A_D_INPUTS ? spra_reg : SPRA) : 'b0); + assign qspo_ce_int = (C_HAS_QSPO_CE ? (C_REG_A_D_INPUTS ? qspo_ce_reg : QSPO_CE) : 1'b0); + + assign qdpo_clk_int = (C_MEM_TYPE == `c_dp_ram ? + (C_HAS_QDPO_CLK == 1 ? QDPO_CLK : CLK) : 1'b0); + + always@(posedge qdpo_clk_int) + begin + if (C_QCE_JOINED) + begin + if (!C_HAS_QSPO_CE) + dpra_reg <= #100 DPRA; + else if (QSPO_CE) + dpra_reg <= #100 DPRA; + end + else + begin + if (!C_HAS_QDPO_CE) + dpra_reg <= #100 DPRA; + else if (QDPO_CE) + dpra_reg <= #100 DPRA; + end // else: !if(C_QCE_JOINED) + + qdpo_ce_reg <= #100 QDPO_CE; + + end // always@ (posedge qdpo_clk_int) + + assign dpra_int = (C_MEM_TYPE == `c_dp_ram ? + (C_REG_DPRA_INPUT == 1 ? dpra_reg : DPRA) : 1'b0); + + assign qdpo_ce_int = (C_MEM_TYPE == `c_dp_ram ? + (C_HAS_QDPO_CE ? (C_REG_DPRA_INPUT ? qdpo_ce_reg : QDPO_CE) : 1'b0) : 1'b0); + + always@(posedge spra_is_over) + begin + if (C_MEM_TYPE == `c_srl16) + begin + $display("WARNING in %m at time %d ns: ", $time); + $write("Reading from out-of-range address. "); + $display("Max address in %m is %d", C_DEPTH-1); + end // if (C_MEM_TYPE == `c_srl16) + end // always@ (spra_int or CLK) + + always@(posedge a_is_over) + begin + if (C_MEM_TYPE != `c_srl16) + begin + $display("WARNING in %m at time %d ns: ", $time); + $write("Reading from out-of-range address. "); + $display("Max address in %m is %d", C_DEPTH-1); + end // if (C_MEM_TYPE != `c_srl16) + end // always@ (a_int or posedge CLK) + + assign SPO = (C_HAS_SPO ? spo_int : `allXs); + + always@(posedge dpra_is_over) + begin + if (C_MEM_TYPE == `c_dp_ram) + begin + $display("WARNING in %m at time %d ns: ", $time); + $write("Reading from out-of-range address. "); + $display("Max address in %m is %d", C_DEPTH-1); + end // if (C_MEM_TYPE == `c_dp_ram) + end // always@ (dpra_int) + + assign spo_int = (C_MEM_TYPE == `c_srl16 ? (spra_is_over ? data_srl_over : data_srl) : + (a_is_over ? data_sp_over : data_sp)); + + assign dpo_int = (C_MEM_TYPE == `c_dp_ram ? (dpra_is_over ? data_dp_over : data_dp) : `allXs); + + assign data_sp = ram_data[a_int]; + assign data_dp = ram_data[dpra_int]; + assign data_srl = ram_data[spra_int]; + + assign a_is_over = (a_int > max_address ? 1'b1 : 1'b0); + assign dpra_is_over = (dpra_int > max_address ? 1'b1 : 1'b0); + assign spra_is_over = (spra_int > max_address ? 1'b1 : 1'b0); + + assign a_over = a_int & max_address; + assign dpra_over = dpra_int & max_address; + assign spra_over = spra_int & max_address; + + assign data_sp_over = 'bx; + assign data_dp_over = 'bx; + assign data_srl_over = 'bx; + + assign DPO = (C_HAS_DPO ? dpo_int : `allXs); + + always@(posedge CLK or posedge QSPO_RST) + begin + if (C_HAS_QSPO_RST && QSPO_RST) + begin + qspo_pipe <= 'b0; + qspo_int <= 'b0; + end + else if (C_HAS_QSPO_SRST && QSPO_SRST) + begin + if (!C_HAS_QSPO_CE) + begin + qspo_pipe <= #100 'b0; + qspo_int <= #100 'b0; + end + else if (!C_SYNC_ENABLE) + begin + qspo_pipe <= #100 'b0; + qspo_int <= #100 'b0; + end + else if (C_HAS_QSPO_CE && qspo_ce_int) + begin + qspo_pipe <= #100 'b0; + qspo_int <= #100 'b0; + end + end // if (C_HAS_QSPO_SRST && QSPO_SRST) + + else if (C_HAS_QSPO_CE && qspo_ce_int) + begin + if (C_PIPELINE_STAGES == 1) + begin + qspo_int <= #100 qspo_pipe; + end + else + begin + qspo_int <= #100 spo_int; + end + qspo_pipe <= #100 spo_int; + end + else if (!C_HAS_QSPO_CE) + begin + if (C_PIPELINE_STAGES == 1) + begin + qspo_int <= #100 qspo_pipe; + end + else + begin + qspo_int <= #100 spo_int; + end + qspo_pipe <= #100 spo_int; + end // if (!C_HAS_QSPO_CE) + end // always@ (posedge CLK or QSPO_RST) + + assign QSPO = (C_HAS_QSPO == 1 ? qspo_int : `allXs); + + always@(posedge qdpo_clk_int or posedge QDPO_RST) + begin + if (C_HAS_QDPO_RST && QDPO_RST) + begin + qdpo_pipe <= 'b0; + qdpo_int <= 'b0; + end + else if (C_HAS_QDPO_SRST && QDPO_SRST) + begin + if (!C_SYNC_ENABLE) + begin + qdpo_pipe <= #100 'b0; + qdpo_int <= #100 'b0; + end + else if (!C_QCE_JOINED) + begin + if (!C_HAS_QDPO_CE) + begin + qdpo_pipe <= #100 'b0; + qdpo_int <= #100 'b0; + end + else if (C_HAS_QDPO_CE && qdpo_ce_int) + begin + qdpo_pipe <= #100 'b0; + qdpo_int <= #100 'b0; + end + end + else + begin + if (!C_HAS_QSPO_CE) + begin + qdpo_pipe <= #100 'b0; + qdpo_int <= #100 'b0; + end + else if (C_HAS_QSPO_CE && qspo_ce_int) + begin + qdpo_pipe <= #100 'b0; + qdpo_int <= #100 'b0; + end + end + end // if (C_HAS_QDPO_SRST && QDPO_SRST) + + else if (!C_QCE_JOINED) + begin + if (!C_HAS_QDPO_CE) + begin + qdpo_pipe <= #100 dpo_int; + if (C_PIPELINE_STAGES == 1) + begin + qdpo_int <= #100 qdpo_pipe; + end + else + begin + qdpo_int <= #100 dpo_int; + end + end // if (!C_HAS_QDPO_CE) + else if (C_HAS_QDPO_CE && qdpo_ce_int) + begin + qdpo_pipe <= #100 dpo_int; + if (C_PIPELINE_STAGES == 1) + begin + qdpo_int <= #100 qdpo_pipe; + end + else + begin + qdpo_int <= #100 dpo_int; + end + end // if (C_HAS_QDPO_CE && qdpo_ce_int) + end // if (!C_QCE_JOINED) + else if (C_QCE_JOINED) + begin + if (C_HAS_QSPO_CE && qspo_ce_int) + begin + qdpo_pipe <= #100 dpo_int; + if (C_PIPELINE_STAGES == 1) + begin + qdpo_int <= #100 qdpo_pipe; + end + else + begin + qdpo_int <= #100 dpo_int; + end + end // if (C_HAS_QSPO_CE && qspo_ce_int) + else if (!C_HAS_QSPO_CE) + begin + qdpo_pipe <= #100 dpo_int; + if (C_PIPELINE_STAGES == 1) + begin + qdpo_int <= #100 qdpo_pipe; + end + else + begin + qdpo_int <= #100 dpo_int; + end + end // if (!C_HAS_QSPO_CE) + end // if (C_QCE_JOINED) + end // always@ (posedge qdpo_clk_int or posedge QDPO_RST) + + assign QDPO = (C_HAS_QDPO == 1 ? qdpo_int : `allXs); + + function [C_WIDTH - 1 : 0] binstr_conv; + input [(C_WIDTH * 8) - 1 : 0] def_data; + integer index,i; + begin + index = 0; + binstr_conv = 'b0; + + for (i=C_WIDTH-1; i>=0; i=i-1) + begin + case (def_data[7:0]) + 8'b00000000 : i = -1; + 8'b00110000 : binstr_conv[index] = 1'b0; + 8'b00110001 : binstr_conv[index] = 1'b1; + default : + begin + $display("ERROR in %m at time %d ns: NOT A BINARY CHARACTER", $time); + binstr_conv[index] = 1'bx; + end + endcase // case(def_data[7:0]) + + index = index + 1; + def_data = def_data >> 8; + end // for (i=C_WIDTH-1; i>=0; i=i-1) + + end + endfunction // binstr_conv + +endmodule // DIST_MEM_GEN_V3_4 + +`undef all0s +`undef allXs +`undef c_rom +`undef c_sp_ram +`undef c_dp_ram +`undef c_srl16 diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/DIST_MEM_GEN_V3_4_XST.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/DIST_MEM_GEN_V3_4_XST.v new file mode 100644 index 0000000..a102572 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/DIST_MEM_GEN_V3_4_XST.v @@ -0,0 +1,165 @@ +// Copyright(C) 2007 by Xilinx, Inc. All rights reserved. +// This text/file contains proprietary, confidential +// information of Xilinx, Inc., is distributed under license +// from Xilinx, Inc., and may be used, copied and/or +// disclosed only pursuant to the terms of a valid license +// agreement with Xilinx, Inc. Xilinx hereby grants you +// a license to use this text/file solely for design, simulation, +// implementation and creation of design files limited +// to Xilinx devices or technologies. Use with non-Xilinx +// devices or technologies is expressly prohibited and +// immediately terminates your license unless covered by +// a separate agreement. +// +// Xilinx is providing this design, code, or information +// "as is" solely for use in developing programs and +// solutions for Xilinx devices. By providing this design, +// code, or information as one possible implementation of +// this feature, application or standard, Xilinx is making no +// representation that this implementation is free from any +// claims of infringement. You are responsible for +// obtaining any rights you may require for your implementation. +// Xilinx expressly disclaims any warranty whatsoever with +// respect to the adequacy of the implementation, including +// but not limited to any warranties or representations that this +// implementation is free from claims of infringement, implied +// warranties of merchantability or fitness for a particular +// purpose. +// +// Xilinx products are not intended for use in life support +// appliances, devices, or systems. Use in such applications are +// expressly prohibited. +// +// This copyright and support notice must be retained as part +// of this text at all times. (c) Copyright 1995-2006 Xilinx, Inc. +// All rights reserved. + + + +/* $RCSfile: DIST_MEM_GEN_V3_4_XST.v,v $ +-- +-- Filename - DIST_MEM_GEN_V3_4_XST.v +-- Author - Xilinx +-- Creation - 14 Nov 2007 +-- +-- Description +-- Distributed Memory Simulation Model +*/ + + +`timescale 1ps/1ps + +module DIST_MEM_GEN_V3_4_XST +#( + parameter C_ADDR_WIDTH = 6, + parameter C_DEFAULT_DATA = "0", + parameter C_DEPTH = 64, + parameter C_HAS_CLK = 1, + parameter C_HAS_D = 1, + parameter C_HAS_DPO = 0, + parameter C_HAS_DPRA = 0, + parameter C_HAS_I_CE = 0, + parameter C_HAS_QDPO = 0, + parameter C_HAS_QDPO_CE = 0, + parameter C_HAS_QDPO_CLK = 0, + parameter C_HAS_QDPO_RST = 0, + parameter C_HAS_QDPO_SRST = 0, + parameter C_HAS_QSPO = 0, + parameter C_HAS_QSPO_CE = 0, + parameter C_HAS_QSPO_RST = 0, + parameter C_HAS_QSPO_SRST = 0, + parameter C_HAS_SPO = 1, + parameter C_HAS_SPRA = 0, + parameter C_HAS_WE = 1, + parameter C_MEM_INIT_FILE = "null.mif", + parameter C_ELABORATION_DIR = "./", + parameter C_MEM_TYPE = 1, + parameter C_PIPELINE_STAGES = 0, + parameter C_QCE_JOINED = 0, + parameter C_QUALIFY_WE = 0, + parameter C_READ_MIF = 0, + parameter C_REG_A_D_INPUTS = 0, + parameter C_REG_DPRA_INPUT = 0, + parameter C_SYNC_ENABLE = 0, + parameter C_WIDTH = 16 +) +( + input [C_ADDR_WIDTH-1 - (C_ADDR_WIDTH>4?(4*C_HAS_SPRA):0) : 0] A, + input [C_WIDTH-1 : 0] D, + input [C_ADDR_WIDTH-1 : 0] DPRA, + input [C_ADDR_WIDTH-1 : 0] SPRA, + input CLK, + input WE, + input I_CE, + input QSPO_CE, + input QDPO_CE, + input QDPO_CLK, + input QSPO_RST, + input QDPO_RST, + input QSPO_SRST, + input QDPO_SRST, + output [C_WIDTH-1 : 0] SPO, + output [C_WIDTH-1 : 0] QSPO, + output [C_WIDTH-1 : 0] DPO, + output [C_WIDTH-1 : 0] QDPO +); + + DIST_MEM_GEN_V3_4 + #( + .C_ADDR_WIDTH (C_ADDR_WIDTH), + .C_DEFAULT_DATA (C_DEFAULT_DATA), + .C_DEPTH (C_DEPTH), + .C_HAS_CLK (C_HAS_CLK), + .C_HAS_D (C_HAS_D), + .C_HAS_DPO (C_HAS_DPO), + .C_HAS_DPRA (C_HAS_DPRA), + .C_HAS_I_CE (C_HAS_I_CE), + .C_HAS_QDPO (C_HAS_QDPO), + .C_HAS_QDPO_CE (C_HAS_QDPO_CE), + .C_HAS_QDPO_CLK (C_HAS_QDPO_CLK), + .C_HAS_QDPO_RST (C_HAS_QDPO_RST), + .C_HAS_QDPO_SRST (C_HAS_QDPO_SRST), + .C_HAS_QSPO (C_HAS_QSPO), + .C_HAS_QSPO_CE (C_HAS_QSPO_CE), + .C_HAS_QSPO_RST (C_HAS_QSPO_RST), + .C_HAS_QSPO_SRST (C_HAS_QSPO_SRST), + .C_HAS_SPO (C_HAS_SPO), + .C_HAS_SPRA (C_HAS_SPRA), + .C_HAS_WE (C_HAS_WE), + .C_MEM_INIT_FILE (C_MEM_INIT_FILE), + .C_ELABORATION_DIR (C_ELABORATION_DIR), + .C_MEM_TYPE (C_MEM_TYPE), + .C_PIPELINE_STAGES (C_PIPELINE_STAGES), + .C_QCE_JOINED (C_QCE_JOINED), + .C_QUALIFY_WE (C_QUALIFY_WE), + .C_READ_MIF (C_READ_MIF), + .C_REG_A_D_INPUTS (C_REG_A_D_INPUTS), + .C_REG_DPRA_INPUT (C_REG_DPRA_INPUT), + .C_SYNC_ENABLE (C_SYNC_ENABLE), + .C_WIDTH (C_WIDTH) + ) dist_mem_gen_v3_4_dut + ( + .A (A), + .D (D), + .DPRA (DPRA), + .SPRA (SPRA), + .CLK (CLK), + .WE (WR), + .I_CE (I_CE), + .QSPO_CE (QSPO_CE), + .QDPO_CE (QDPO_CE), + .QDPO_CLK (QDPO_CLK), + .QSPO_RST (QSPO_RST), + .QDPO_RST (QDPO_RST), + .QSPO_SRST (QSPO_SRST ), + .QDPO_SRST (QDPO_SRS), + .SPO (SPO), + .DPO (DPO), + .QSPO (QSPO), + .QDPO (QDPO) + ); + +endmodule + + + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/DIST_MEM_GEN_V4_1.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/DIST_MEM_GEN_V4_1.v new file mode 100644 index 0000000..dde3db5 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/DIST_MEM_GEN_V4_1.v @@ -0,0 +1,618 @@ +// Copyright(C) 2004-2006 by Xilinx, Inc. All rights reserved. +// This text/file contains proprietary, confidential +// information of Xilinx, Inc., is distributed under license +// from Xilinx, Inc., and may be used, copied and/or +// disclosed only pursuant to the terms of a valid license +// agreement with Xilinx, Inc. Xilinx hereby grants you +// a license to use this text/file solely for design, simulation, +// implementation and creation of design files limited +// to Xilinx devices or technologies. Use with non-Xilinx +// devices or technologies is expressly prohibited and +// immediately terminates your license unless covered by +// a separate agreement. +// +// Xilinx is providing this design, code, or information +// "as is" solely for use in developing programs and +// solutions for Xilinx devices. By providing this design, +// code, or information as one possible implementation of +// this feature, application or standard, Xilinx is making no +// representation that this implementation is free from any +// claims of infringement. You are responsible for +// obtaining any rights you may require for your implementation. +// Xilinx expressly disclaims any warranty whatsoever with +// respect to the adequacy of the implementation, including +// but not limited to any warranties or representations that this +// implementation is free from claims of infringement, implied +// warranties of merchantability or fitness for a particular +// purpose. +// +// Xilinx products are not intended for use in life support +// appliances, devices, or systems. Use in such applications are +// expressly prohibited. +// +// This copyright and support notice must be retained as part +// of this text at all times. (c) Copyright 1995-2006 Xilinx, Inc. +// All rights reserved. + + + +/* $RCSfile: DIST_MEM_GEN_V4_1.v,v $ $Revision: 1.3 $ $Date: 2009/09/08 15:24:34 $ +-- +-- Filename - DIST_MEM_GEN_V4_1.v +-- Author - Xilinx +-- Creation - 27 Nov 2004 +-- +-- Description +-- Distributed Memory Simulation Model +*/ + + +`timescale 1ps/1ps +`ifndef TCQ + `define TCQ 100 +`endif + +`define all0s {C_WIDTH{1'b0}} +`define allXs {C_WIDTH{1'bx}} +`define c_rom 0 +`define c_sp_ram 1 +`define c_dp_ram 2 +`define c_srl16 3 + +module DIST_MEM_GEN_V4_1 (A, D, DPRA, SPRA, CLK, WE, I_CE, QSPO_CE, QDPO_CE, QDPO_CLK, QSPO_RST, QDPO_RST, QSPO_SRST, QDPO_SRST, SPO, DPO, QSPO, QDPO); + + parameter C_FAMILY = "virtex5"; + parameter C_ADDR_WIDTH = 6; + parameter C_DEFAULT_DATA = "0"; + parameter C_DEPTH = 64; + parameter C_HAS_CLK = 1; + parameter C_HAS_D = 1; + parameter C_HAS_DPO = 0; + parameter C_HAS_DPRA = 0; + parameter C_HAS_I_CE = 0; + parameter C_HAS_QDPO = 0; + parameter C_HAS_QDPO_CE = 0; + parameter C_HAS_QDPO_CLK = 0; + parameter C_HAS_QDPO_RST = 0; + parameter C_HAS_QDPO_SRST = 0; + parameter C_HAS_QSPO = 0; + parameter C_HAS_QSPO_CE = 0; + parameter C_HAS_QSPO_RST = 0; + parameter C_HAS_QSPO_SRST = 0; + parameter C_HAS_SPO = 1; + parameter C_HAS_SPRA = 0; + parameter C_HAS_WE = 1; + parameter C_MEM_INIT_FILE = "null.mif"; + parameter C_MEM_TYPE = 1; + parameter C_PIPELINE_STAGES = 0; + parameter C_QCE_JOINED = 0; + parameter C_QUALIFY_WE = 0; + parameter C_READ_MIF = 0; + parameter C_REG_A_D_INPUTS = 0; + parameter C_REG_DPRA_INPUT = 0; + parameter C_SYNC_ENABLE = 0; + parameter C_WIDTH = 16; + parameter C_PARSER_TYPE = 1; + + input [C_ADDR_WIDTH-1 - (C_ADDR_WIDTH>4?(4*C_HAS_SPRA):0) : 0] A; + input [C_WIDTH-1 : 0] D; + input [C_ADDR_WIDTH-1 : 0] DPRA; + input [C_ADDR_WIDTH-1 : 0] SPRA; + input CLK; + input WE; + input I_CE; + input QSPO_CE; + input QDPO_CE; + input QDPO_CLK; + input QSPO_RST; + input QDPO_RST; + input QSPO_SRST; + input QDPO_SRST; + output [C_WIDTH-1 : 0] SPO; + output [C_WIDTH-1 : 0] QSPO; + output [C_WIDTH-1 : 0] DPO; + output [C_WIDTH-1 : 0] QDPO; + + // Address signal connected to memory + wire [C_ADDR_WIDTH - 1 : 0] a_int; + + // Read Address connected to srl16 memory + wire [C_ADDR_WIDTH - 1 : 0] spra_int; + + // Input data signal connected to memory + wire [C_WIDTH - 1 : 0] d_int; + + // Internal Write Enable + wire we_int; + + // Internal QSPO Clock Enable + wire qspo_ce_int; + + // Internal QDPO Clock + wire qdpo_clk_int; + + // Internal Dual Port Read Address connected to memory + wire [C_ADDR_WIDTH - 1 : 0] dpra_int; + + // Internal QDPO Clock Enable + wire qdpo_ce_int; + + // Registered Write Enable + reg we_reg; + + // Registered Address connected to memory + reg [C_ADDR_WIDTH - 1 : 0] a_reg; + + // Registered Read Address connected to srl16 memory + reg [C_ADDR_WIDTH - 1 : 0] spra_reg; + + // Registered data signal connected to memory + reg [C_WIDTH-1 : 0] d_reg; + + // Registered QSPO Clock Enable + reg qspo_ce_reg; + + // Registered Dual Port Read Address connected to memory + reg [C_ADDR_WIDTH - 1 : 0] dpra_reg; + + // Registered QDPO Clock Enable + reg qdpo_ce_reg; + + // Internal Single Port RAM output signal + wire [C_WIDTH - 1 : 0] spo_int; + + // Internal Dual Port RAM output signal + wire [C_WIDTH - 1 : 0] dpo_int; + + // Internal ROM/Single Port RAM/SRL16 RAM + // registered output + reg [C_WIDTH - 1 : 0] qspo_int; + + // Pipeline registers + reg [C_WIDTH - 1 : 0] qspo_pipe; + + // Internal Dual Port RAM registered output + reg [C_WIDTH - 1 : 0] qdpo_int; + + // Pipeline registers + reg [C_WIDTH - 1 : 0] qdpo_pipe; + + reg [C_WIDTH-1 : 0] ram_data [(2**C_ADDR_WIDTH)-1 : 0]; + reg [C_WIDTH-1 : 0] ram_data_tmp[C_DEPTH-1 : 0]; + + + reg [C_WIDTH-1 : 0] default_data; + + wire [C_WIDTH-1 : 0] data_sp; + wire [C_WIDTH-1 : 0] data_dp; + wire [C_WIDTH-1 : 0] data_srl; + + wire [C_WIDTH-1 : 0] data_sp_over; + wire [C_WIDTH-1 : 0] data_dp_over; + wire [C_WIDTH-1 : 0] data_srl_over; + + wire [C_ADDR_WIDTH - 1 : 0] a_over; + wire [C_ADDR_WIDTH - 1 : 0] dpra_over; + wire [C_ADDR_WIDTH - 1 : 0] spra_over; + + wire a_is_over; + wire dpra_is_over; + wire spra_is_over; + + reg [C_ADDR_WIDTH-1 : 0] max_address; + + integer i; + integer j; + integer srl_start; + integer srl_end; + + + // Initial block - initialise the memory, + // and when appropriate write content into the given address. + initial + begin + $display("WARNING: This core is supplied with a behavioral model. To model cycle-accurate behavior you must run timing simulation."); + + + default_data = 'b0; + default_data = binstr_conv(C_DEFAULT_DATA); + + // Assign that C_DEFAULT_DATA to each address in the memory. + for (i = 0; i < C_DEPTH; i = i + 1) + begin + ram_data[i] = default_data; + ram_data_tmp[i] = default_data; + end + + //Read the MIF file, and use it to initialise the content of ram_data + //if that is required. + if (C_READ_MIF) + begin + $readmemb(C_MEM_INIT_FILE, ram_data_tmp, 0, C_DEPTH-1); + + for (i = 0; i < C_DEPTH; i = i + 1) + ram_data[i] = ram_data_tmp[i]; + + end + + if (C_DEPTH != (2**C_ADDR_WIDTH)) + begin + for (i = C_DEPTH; i < (2**C_ADDR_WIDTH); i = i + 1) + ram_data[i] = 'b0; + end + + a_reg = 'b0; + we_reg = 1'b0; + spra_reg = 'b0; + d_reg = 'b0; + qspo_ce_reg = 1'b0; + dpra_reg = 'b0; + qdpo_ce_reg = 1'b0; + + //qspo_int = default_data; + qspo_int = (C_FAMILY == "spartan6")? 0: default_data; + qspo_pipe = 'b0; + //qdpo_int = default_data; + qdpo_int = (C_FAMILY == "spartan6")? 0: default_data; + qdpo_pipe = 'b0; + + max_address = C_DEPTH-1; + + srl_start = 0; + srl_end = 15; + + end // initial begin + + // Now look for writes to the memory (note that this means the + // memory is not a ROM and that the Write Enable WE is active. + always@(posedge CLK) + begin + if (C_MEM_TYPE != `c_rom && we_int) + begin + if (C_MEM_TYPE == `c_srl16) + begin + if (C_ADDR_WIDTH > 4) + begin + srl_start = a_int * 16; + if (srl_start + 16 > C_DEPTH) + srl_end = C_DEPTH - 1; + else + srl_end = (a_int*16) + 15; + end + else + begin + srl_start = 0; + srl_end = 15; + end + + for (i = srl_end; i > srl_start; i = i - 1) + ram_data[i] <= #`TCQ ram_data[i-1]; + + ram_data[srl_start] <= #`TCQ d_int; + end + else if (a_is_over) + begin + $display("WARNING in %m at time %d ns", $time); + $write("Writing to out of range address. "); + $display("Max address in %m is %d", C_DEPTH-1); + $display("Write will be ignored."); + end + else + ram_data[a_int] <= #`TCQ d_int; + end // if (C_MEM_TYPE != `c_rom && we_int) + end // always@ (posedge CLK) + + // Model optional input registers, which operate in the CLK clock domain. + always @(posedge CLK) + begin + if (!C_HAS_I_CE) + begin + we_reg <= #`TCQ WE; + a_reg <= #`TCQ A; + spra_reg <= #`TCQ SPRA; + d_reg <= #`TCQ D; + end + else if (!C_QUALIFY_WE) + begin + we_reg <= #`TCQ WE; + if (I_CE) + begin + a_reg <= #`TCQ A; + spra_reg <= #`TCQ SPRA; + d_reg <= #`TCQ D; + end + end + else if (C_QUALIFY_WE) + if (I_CE) + begin + we_reg <= #`TCQ WE; + a_reg <= #`TCQ A; + spra_reg <= #`TCQ SPRA; + d_reg <= #`TCQ D; + end + + qspo_ce_reg <= #`TCQ QSPO_CE; + end // always @ (posedge CLK) + + + assign we_int = (C_HAS_WE ? (C_REG_A_D_INPUTS ? we_reg : WE) : 1'b0); + assign d_int = (C_MEM_TYPE > 0 ? (C_REG_A_D_INPUTS ? d_reg : D) : 'b0); + assign a_int = (C_REG_A_D_INPUTS ? a_reg : A); + + assign spra_int = (C_MEM_TYPE == `c_srl16 ? (C_REG_A_D_INPUTS ? spra_reg : SPRA) : 'b0); + assign qspo_ce_int = (C_HAS_QSPO_CE ? (C_REG_A_D_INPUTS ? qspo_ce_reg : QSPO_CE) : 1'b0); + + assign qdpo_clk_int = (C_MEM_TYPE == `c_dp_ram ? + (C_HAS_QDPO_CLK == 1 ? QDPO_CLK : CLK) : 1'b0); + + always@(posedge qdpo_clk_int) + begin + if (C_QCE_JOINED) + begin + if (!C_HAS_QSPO_CE) + dpra_reg <= #`TCQ DPRA; + else if (QSPO_CE) + dpra_reg <= #`TCQ DPRA; + end + else + begin + if (!C_HAS_QDPO_CE) + dpra_reg <= #`TCQ DPRA; + else if (QDPO_CE) + dpra_reg <= #`TCQ DPRA; + end // else: !if(C_QCE_JOINED) + + qdpo_ce_reg <= #`TCQ QDPO_CE; + + end // always@ (posedge qdpo_clk_int) + + assign dpra_int = (C_MEM_TYPE == `c_dp_ram ? + (C_REG_DPRA_INPUT == 1 ? dpra_reg : DPRA) : 1'b0); + + assign qdpo_ce_int = (C_MEM_TYPE == `c_dp_ram ? + (C_HAS_QDPO_CE ? (C_REG_DPRA_INPUT ? qdpo_ce_reg : QDPO_CE) : 1'b0) : 1'b0); + + always@(posedge spra_is_over) + begin + if (C_MEM_TYPE == `c_srl16) + begin + $display("WARNING in %m at time %d ns: ", $time); + $write("Reading from out-of-range address. "); + $display("Max address in %m is %d", C_DEPTH-1); + end // if (C_MEM_TYPE == `c_srl16) + end // always@ (spra_int or CLK) + + always@(posedge a_is_over) + begin + if (C_MEM_TYPE != `c_srl16) + begin + $display("WARNING in %m at time %d ns: ", $time); + $write("Reading from out-of-range address. "); + $display("Max address in %m is %d", C_DEPTH-1); + end // if (C_MEM_TYPE != `c_srl16) + end // always@ (a_int or posedge CLK) + + assign SPO = (C_HAS_SPO ? spo_int : `allXs); + + always@(posedge dpra_is_over) + begin + if (C_MEM_TYPE == `c_dp_ram) + begin + $display("WARNING in %m at time %d ns: ", $time); + $write("Reading from out-of-range address. "); + $display("Max address in %m is %d", C_DEPTH-1); + end // if (C_MEM_TYPE == `c_dp_ram) + end // always@ (dpra_int) + + assign spo_int = (C_MEM_TYPE == `c_srl16 ? (spra_is_over ? data_srl_over : data_srl) : + (a_is_over ? data_sp_over : data_sp)); + + assign dpo_int = (C_MEM_TYPE == `c_dp_ram ? (dpra_is_over ? data_dp_over : data_dp) : `allXs); + + assign data_sp = ram_data[a_int]; + assign data_dp = ram_data[dpra_int]; + assign data_srl = ram_data[spra_int]; + + assign a_is_over = (a_int > max_address ? 1'b1 : 1'b0); + assign dpra_is_over = (dpra_int > max_address ? 1'b1 : 1'b0); + assign spra_is_over = (spra_int > max_address ? 1'b1 : 1'b0); + + assign a_over = a_int & max_address; + assign dpra_over = dpra_int & max_address; + assign spra_over = spra_int & max_address; + + assign data_sp_over = 'bx; + assign data_dp_over = 'bx; + assign data_srl_over = 'bx; + + assign DPO = (C_HAS_DPO ? dpo_int : `allXs); + + always@(posedge CLK or posedge QSPO_RST) + begin + if (C_HAS_QSPO_RST && QSPO_RST) + begin + qspo_pipe <= 'b0; + qspo_int <= 'b0; + end + else if (C_HAS_QSPO_SRST && QSPO_SRST) + begin + if (!C_HAS_QSPO_CE) + begin + qspo_pipe <= #`TCQ 'b0; + qspo_int <= #`TCQ 'b0; + end + else if (!C_SYNC_ENABLE) + begin + qspo_pipe <= #`TCQ 'b0; + qspo_int <= #`TCQ 'b0; + end + else if (C_HAS_QSPO_CE && qspo_ce_int) + begin + qspo_pipe <= #`TCQ 'b0; + qspo_int <= #`TCQ 'b0; + end + end // if (C_HAS_QSPO_SRST && QSPO_SRST) + + else if (C_HAS_QSPO_CE && qspo_ce_int) + begin + if (C_PIPELINE_STAGES == 1) + begin + qspo_int <= #`TCQ qspo_pipe; + end + else + begin + qspo_int <= #`TCQ spo_int; + end + qspo_pipe <= #`TCQ spo_int; + end + else if (!C_HAS_QSPO_CE) + begin + if (C_PIPELINE_STAGES == 1) + begin + qspo_int <= #`TCQ qspo_pipe; + end + else + begin + qspo_int <= #`TCQ spo_int; + end + qspo_pipe <= #`TCQ spo_int; + end // if (!C_HAS_QSPO_CE) + end // always@ (posedge CLK or QSPO_RST) + + assign QSPO = (C_HAS_QSPO == 1 ? qspo_int : `allXs); + + always@(posedge qdpo_clk_int or posedge QDPO_RST) + begin + if (C_HAS_QDPO_RST && QDPO_RST) + begin + qdpo_pipe <= 'b0; + qdpo_int <= 'b0; + end + else if (C_HAS_QDPO_SRST && QDPO_SRST) + begin + if (!C_SYNC_ENABLE) + begin + qdpo_pipe <= #`TCQ 'b0; + qdpo_int <= #`TCQ 'b0; + end + else if (!C_QCE_JOINED) + begin + if (!C_HAS_QDPO_CE) + begin + qdpo_pipe <= #`TCQ 'b0; + qdpo_int <= #`TCQ 'b0; + end + else if (C_HAS_QDPO_CE && qdpo_ce_int) + begin + qdpo_pipe <= #`TCQ 'b0; + qdpo_int <= #`TCQ 'b0; + end + end + else + begin + if (!C_HAS_QSPO_CE) + begin + qdpo_pipe <= #`TCQ 'b0; + qdpo_int <= #`TCQ 'b0; + end + else if (C_HAS_QSPO_CE && qspo_ce_int) + begin + qdpo_pipe <= #`TCQ 'b0; + qdpo_int <= #`TCQ 'b0; + end + end + end // if (C_HAS_QDPO_SRST && QDPO_SRST) + + else if (!C_QCE_JOINED) + begin + if (!C_HAS_QDPO_CE) + begin + qdpo_pipe <= #`TCQ dpo_int; + if (C_PIPELINE_STAGES == 1) + begin + qdpo_int <= #`TCQ qdpo_pipe; + end + else + begin + qdpo_int <= #`TCQ dpo_int; + end + end // if (!C_HAS_QDPO_CE) + else if (C_HAS_QDPO_CE && qdpo_ce_int) + begin + qdpo_pipe <= #`TCQ dpo_int; + if (C_PIPELINE_STAGES == 1) + begin + qdpo_int <= #`TCQ qdpo_pipe; + end + else + begin + qdpo_int <= #`TCQ dpo_int; + end + end // if (C_HAS_QDPO_CE && qdpo_ce_int) + end // if (!C_QCE_JOINED) + else if (C_QCE_JOINED) + begin + if (C_HAS_QSPO_CE && qspo_ce_int) + begin + qdpo_pipe <= #`TCQ dpo_int; + if (C_PIPELINE_STAGES == 1) + begin + qdpo_int <= #`TCQ qdpo_pipe; + end + else + begin + qdpo_int <= #`TCQ dpo_int; + end + end // if (C_HAS_QSPO_CE && qspo_ce_int) + else if (!C_HAS_QSPO_CE) + begin + qdpo_pipe <= #`TCQ dpo_int; + if (C_PIPELINE_STAGES == 1) + begin + qdpo_int <= #`TCQ qdpo_pipe; + end + else + begin + qdpo_int <= #`TCQ dpo_int; + end + end // if (!C_HAS_QSPO_CE) + end // if (C_QCE_JOINED) + end // always@ (posedge qdpo_clk_int or posedge QDPO_RST) + + assign QDPO = (C_HAS_QDPO == 1 ? qdpo_int : `allXs); + + function [C_WIDTH - 1 : 0] binstr_conv; + input [(C_WIDTH * 8) - 1 : 0] def_data; + integer index,i; + begin + index = 0; + binstr_conv = 'b0; + + for (i=C_WIDTH-1; i>=0; i=i-1) + begin + case (def_data[7:0]) + 8'b00000000 : i = -1; + 8'b00110000 : binstr_conv[index] = 1'b0; + 8'b00110001 : binstr_conv[index] = 1'b1; + default : + begin + $display("ERROR in %m at time %d ns: NOT A BINARY CHARACTER", $time); + binstr_conv[index] = 1'bx; + end + endcase // case(def_data[7:0]) + + index = index + 1; + def_data = def_data >> 8; + end // for (i=C_WIDTH-1; i>=0; i=i-1) + + end + endfunction // binstr_conv + +endmodule // DIST_MEM_GEN_V4_1 + +`undef all0s +`undef allXs +`undef c_rom +`undef c_sp_ram +`undef c_dp_ram +`undef c_srl16 diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/DIST_MEM_GEN_V4_1_XST.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/DIST_MEM_GEN_V4_1_XST.v new file mode 100644 index 0000000..0104554 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/DIST_MEM_GEN_V4_1_XST.v @@ -0,0 +1,169 @@ +// Copyright(C) 2007 by Xilinx, Inc. All rights reserved. +// This text/file contains proprietary, confidential +// information of Xilinx, Inc., is distributed under license +// from Xilinx, Inc., and may be used, copied and/or +// disclosed only pursuant to the terms of a valid license +// agreement with Xilinx, Inc. Xilinx hereby grants you +// a license to use this text/file solely for design, simulation, +// implementation and creation of design files limited +// to Xilinx devices or technologies. Use with non-Xilinx +// devices or technologies is expressly prohibited and +// immediately terminates your license unless covered by +// a separate agreement. +// +// Xilinx is providing this design, code, or information +// "as is" solely for use in developing programs and +// solutions for Xilinx devices. By providing this design, +// code, or information as one possible implementation of +// this feature, application or standard, Xilinx is making no +// representation that this implementation is free from any +// claims of infringement. You are responsible for +// obtaining any rights you may require for your implementation. +// Xilinx expressly disclaims any warranty whatsoever with +// respect to the adequacy of the implementation, including +// but not limited to any warranties or representations that this +// implementation is free from claims of infringement, implied +// warranties of merchantability or fitness for a particular +// purpose. +// +// Xilinx products are not intended for use in life support +// appliances, devices, or systems. Use in such applications are +// expressly prohibited. +// +// This copyright and support notice must be retained as part +// of this text at all times. (c) Copyright 1995-2006 Xilinx, Inc. +// All rights reserved. + + + +/* $RCSfile: DIST_MEM_GEN_V4_1_XST.v,v $ +-- +-- Filename - DIST_MEM_GEN_V4_1_XST.v +-- Author - Xilinx +-- Creation - 14 Nov 2007 +-- +-- Description +-- Distributed Memory Simulation Model +*/ + + +`timescale 1ps/1ps + +module DIST_MEM_GEN_V4_1_XST +#( + parameter C_FAMILY = "virtex5", + parameter C_ADDR_WIDTH = 6, + parameter C_DEFAULT_DATA = "0", + parameter C_DEPTH = 64, + parameter C_HAS_CLK = 1, + parameter C_HAS_D = 1, + parameter C_HAS_DPO = 0, + parameter C_HAS_DPRA = 0, + parameter C_HAS_I_CE = 0, + parameter C_HAS_QDPO = 0, + parameter C_HAS_QDPO_CE = 0, + parameter C_HAS_QDPO_CLK = 0, + parameter C_HAS_QDPO_RST = 0, + parameter C_HAS_QDPO_SRST = 0, + parameter C_HAS_QSPO = 0, + parameter C_HAS_QSPO_CE = 0, + parameter C_HAS_QSPO_RST = 0, + parameter C_HAS_QSPO_SRST = 0, + parameter C_HAS_SPO = 1, + parameter C_HAS_SPRA = 0, + parameter C_HAS_WE = 1, + parameter C_MEM_INIT_FILE = "null.mif", + parameter C_ELABORATION_DIR = "./", + parameter C_MEM_TYPE = 1, + parameter C_PIPELINE_STAGES = 0, + parameter C_QCE_JOINED = 0, + parameter C_QUALIFY_WE = 0, + parameter C_READ_MIF = 0, + parameter C_REG_A_D_INPUTS = 0, + parameter C_REG_DPRA_INPUT = 0, + parameter C_SYNC_ENABLE = 0, + parameter C_WIDTH = 16, + parameter C_PARSER_TYPE = 1 +) +( + input [C_ADDR_WIDTH-1 - (C_ADDR_WIDTH>4?(4*C_HAS_SPRA):0) : 0] A, + input [C_WIDTH-1 : 0] D, + input [C_ADDR_WIDTH-1 : 0] DPRA, + input [C_ADDR_WIDTH-1 : 0] SPRA, + input CLK, + input WE, + input I_CE, + input QSPO_CE, + input QDPO_CE, + input QDPO_CLK, + input QSPO_RST, + input QDPO_RST, + input QSPO_SRST, + input QDPO_SRST, + output [C_WIDTH-1 : 0] SPO, + output [C_WIDTH-1 : 0] QSPO, + output [C_WIDTH-1 : 0] DPO, + output [C_WIDTH-1 : 0] QDPO +); + + DIST_MEM_GEN_V4_1 + #( + .C_FAMILY (C_FAMILY), + .C_ADDR_WIDTH (C_ADDR_WIDTH), + .C_DEFAULT_DATA (C_DEFAULT_DATA), + .C_DEPTH (C_DEPTH), + .C_HAS_CLK (C_HAS_CLK), + .C_HAS_D (C_HAS_D), + .C_HAS_DPO (C_HAS_DPO), + .C_HAS_DPRA (C_HAS_DPRA), + .C_HAS_I_CE (C_HAS_I_CE), + .C_HAS_QDPO (C_HAS_QDPO), + .C_HAS_QDPO_CE (C_HAS_QDPO_CE), + .C_HAS_QDPO_CLK (C_HAS_QDPO_CLK), + .C_HAS_QDPO_RST (C_HAS_QDPO_RST), + .C_HAS_QDPO_SRST (C_HAS_QDPO_SRST), + .C_HAS_QSPO (C_HAS_QSPO), + .C_HAS_QSPO_CE (C_HAS_QSPO_CE), + .C_HAS_QSPO_RST (C_HAS_QSPO_RST), + .C_HAS_QSPO_SRST (C_HAS_QSPO_SRST), + .C_HAS_SPO (C_HAS_SPO), + .C_HAS_SPRA (C_HAS_SPRA), + .C_HAS_WE (C_HAS_WE), + .C_MEM_INIT_FILE (C_MEM_INIT_FILE), + .C_ELABORATION_DIR (C_ELABORATION_DIR), + .C_MEM_TYPE (C_MEM_TYPE), + .C_PIPELINE_STAGES (C_PIPELINE_STAGES), + .C_QCE_JOINED (C_QCE_JOINED), + .C_QUALIFY_WE (C_QUALIFY_WE), + .C_READ_MIF (C_READ_MIF), + .C_REG_A_D_INPUTS (C_REG_A_D_INPUTS), + .C_REG_DPRA_INPUT (C_REG_DPRA_INPUT), + .C_SYNC_ENABLE (C_SYNC_ENABLE), + .C_WIDTH (C_WIDTH), + .C_PARSER_TYPE (C_PARSER_TYPE) + ) dist_mem_gen_v4_1_dut + ( + .A (A), + .D (D), + .DPRA (DPRA), + .SPRA (SPRA), + .CLK (CLK), + .WE (WR), + .I_CE (I_CE), + .QSPO_CE (QSPO_CE), + .QDPO_CE (QDPO_CE), + .QDPO_CLK (QDPO_CLK), + .QSPO_RST (QSPO_RST), + .QDPO_RST (QDPO_RST), + .QSPO_SRST (QSPO_SRST ), + .QDPO_SRST (QDPO_SRS), + .SPO (SPO), + .DPO (DPO), + .QSPO (QSPO), + .QDPO (QDPO) + ); + +endmodule + + + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/DIST_MEM_GEN_V4_2.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/DIST_MEM_GEN_V4_2.v new file mode 100644 index 0000000..ca321b1 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/DIST_MEM_GEN_V4_2.v @@ -0,0 +1,616 @@ +// Copyright(C) 2004-2006 by Xilinx, Inc. All rights reserved. +// This text/file contains proprietary, confidential +// information of Xilinx, Inc., is distributed under license +// from Xilinx, Inc., and may be used, copied and/or +// disclosed only pursuant to the terms of a valid license +// agreement with Xilinx, Inc. Xilinx hereby grants you +// a license to use this text/file solely for design, simulation, +// implementation and creation of design files limited +// to Xilinx devices or technologies. Use with non-Xilinx +// devices or technologies is expressly prohibited and +// immediately terminates your license unless covered by +// a separate agreement. +// +// Xilinx is providing this design, code, or information +// "as is" solely for use in developing programs and +// solutions for Xilinx devices. By providing this design, +// code, or information as one possible implementation of +// this feature, application or standard, Xilinx is making no +// representation that this implementation is free from any +// claims of infringement. You are responsible for +// obtaining any rights you may require for your implementation. +// Xilinx expressly disclaims any warranty whatsoever with +// respect to the adequacy of the implementation, including +// but not limited to any warranties or representations that this +// implementation is free from claims of infringement, implied +// warranties of merchantability or fitness for a particular +// purpose. +// +// Xilinx products are not intended for use in life support +// appliances, devices, or systems. Use in such applications are +// expressly prohibited. +// +// This copyright and support notice must be retained as part +// of this text at all times. (c) Copyright 1995-2006 Xilinx, Inc. +// All rights reserved. + + + +/* $RCSfile: DIST_MEM_GEN_V4_2.v,v $ $Revision: 1.2 $ $Date: 2009/09/08 15:24:39 $ +-- +-- Filename - DIST_MEM_GEN_V4_2.v +-- Author - Xilinx +-- Creation - 27 Nov 2004 +-- +-- Description +-- Distributed Memory Simulation Model +*/ + + +`timescale 1ps/1ps +`ifndef TCQ + `define TCQ 100 +`endif + +`define all0s {C_WIDTH{1'b0}} +`define allXs {C_WIDTH{1'bx}} +`define c_rom 0 +`define c_sp_ram 1 +`define c_dp_ram 2 +`define c_srl16 3 + +module DIST_MEM_GEN_V4_2 (A, D, DPRA, SPRA, CLK, WE, I_CE, QSPO_CE, QDPO_CE, QDPO_CLK, QSPO_RST, QDPO_RST, QSPO_SRST, QDPO_SRST, SPO, DPO, QSPO, QDPO); + + parameter C_FAMILY = "virtex5"; + parameter C_ADDR_WIDTH = 6; + parameter C_DEFAULT_DATA = "0"; + parameter C_DEPTH = 64; + parameter C_HAS_CLK = 1; + parameter C_HAS_D = 1; + parameter C_HAS_DPO = 0; + parameter C_HAS_DPRA = 0; + parameter C_HAS_I_CE = 0; + parameter C_HAS_QDPO = 0; + parameter C_HAS_QDPO_CE = 0; + parameter C_HAS_QDPO_CLK = 0; + parameter C_HAS_QDPO_RST = 0; + parameter C_HAS_QDPO_SRST = 0; + parameter C_HAS_QSPO = 0; + parameter C_HAS_QSPO_CE = 0; + parameter C_HAS_QSPO_RST = 0; + parameter C_HAS_QSPO_SRST = 0; + parameter C_HAS_SPO = 1; + parameter C_HAS_SPRA = 0; + parameter C_HAS_WE = 1; + parameter C_MEM_INIT_FILE = "null.mif"; + parameter C_MEM_TYPE = 1; + parameter C_PIPELINE_STAGES = 0; + parameter C_QCE_JOINED = 0; + parameter C_QUALIFY_WE = 0; + parameter C_READ_MIF = 0; + parameter C_REG_A_D_INPUTS = 0; + parameter C_REG_DPRA_INPUT = 0; + parameter C_SYNC_ENABLE = 0; + parameter C_WIDTH = 16; + parameter C_PARSER_TYPE = 1; + + input [C_ADDR_WIDTH-1 - (C_ADDR_WIDTH>4?(4*C_HAS_SPRA):0) : 0] A; + input [C_WIDTH-1 : 0] D; + input [C_ADDR_WIDTH-1 : 0] DPRA; + input [C_ADDR_WIDTH-1 : 0] SPRA; + input CLK; + input WE; + input I_CE; + input QSPO_CE; + input QDPO_CE; + input QDPO_CLK; + input QSPO_RST; + input QDPO_RST; + input QSPO_SRST; + input QDPO_SRST; + output [C_WIDTH-1 : 0] SPO; + output [C_WIDTH-1 : 0] QSPO; + output [C_WIDTH-1 : 0] DPO; + output [C_WIDTH-1 : 0] QDPO; + + // Address signal connected to memory + wire [C_ADDR_WIDTH - 1 : 0] a_int; + + // Read Address connected to srl16 memory + wire [C_ADDR_WIDTH - 1 : 0] spra_int; + + // Input data signal connected to memory + wire [C_WIDTH - 1 : 0] d_int; + + // Internal Write Enable + wire we_int; + + // Internal QSPO Clock Enable + wire qspo_ce_int; + + // Internal QDPO Clock + wire qdpo_clk_int; + + // Internal Dual Port Read Address connected to memory + wire [C_ADDR_WIDTH - 1 : 0] dpra_int; + + // Internal QDPO Clock Enable + wire qdpo_ce_int; + + // Registered Write Enable + reg we_reg; + + // Registered Address connected to memory + reg [C_ADDR_WIDTH - 1 : 0] a_reg; + + // Registered Read Address connected to srl16 memory + reg [C_ADDR_WIDTH - 1 : 0] spra_reg; + + // Registered data signal connected to memory + reg [C_WIDTH-1 : 0] d_reg; + + // Registered QSPO Clock Enable + reg qspo_ce_reg; + + // Registered Dual Port Read Address connected to memory + reg [C_ADDR_WIDTH - 1 : 0] dpra_reg; + + // Registered QDPO Clock Enable + reg qdpo_ce_reg; + + // Internal Single Port RAM output signal + wire [C_WIDTH - 1 : 0] spo_int; + + // Internal Dual Port RAM output signal + wire [C_WIDTH - 1 : 0] dpo_int; + + // Internal ROM/Single Port RAM/SRL16 RAM + // registered output + reg [C_WIDTH - 1 : 0] qspo_int; + + // Pipeline registers + reg [C_WIDTH - 1 : 0] qspo_pipe; + + // Internal Dual Port RAM registered output + reg [C_WIDTH - 1 : 0] qdpo_int; + + // Pipeline registers + reg [C_WIDTH - 1 : 0] qdpo_pipe; + + reg [C_WIDTH-1 : 0] ram_data [(2**C_ADDR_WIDTH)-1 : 0]; + reg [C_WIDTH-1 : 0] ram_data_tmp[C_DEPTH-1 : 0]; + + + reg [C_WIDTH-1 : 0] default_data; + + wire [C_WIDTH-1 : 0] data_sp; + wire [C_WIDTH-1 : 0] data_dp; + wire [C_WIDTH-1 : 0] data_srl; + + wire [C_WIDTH-1 : 0] data_sp_over; + wire [C_WIDTH-1 : 0] data_dp_over; + wire [C_WIDTH-1 : 0] data_srl_over; + + wire [C_ADDR_WIDTH - 1 : 0] a_over; + wire [C_ADDR_WIDTH - 1 : 0] dpra_over; + wire [C_ADDR_WIDTH - 1 : 0] spra_over; + + wire a_is_over; + wire dpra_is_over; + wire spra_is_over; + + reg [C_ADDR_WIDTH-1 : 0] max_address; + + integer i; + integer j; + integer srl_start; + integer srl_end; + + + // Initial block - initialise the memory, + // and when appropriate write content into the given address. + initial + begin + $display("WARNING: This core is supplied with a behavioral model. To model cycle-accurate behavior you must run timing simulation."); + + + default_data = 'b0; + default_data = binstr_conv(C_DEFAULT_DATA); + + // Assign that C_DEFAULT_DATA to each address in the memory. + for (i = 0; i < C_DEPTH; i = i + 1) + begin + ram_data[i] = default_data; + ram_data_tmp[i] = default_data; + end + + //Read the MIF file, and use it to initialise the content of ram_data + //if that is required. + if (C_READ_MIF) + begin + $readmemb(C_MEM_INIT_FILE, ram_data_tmp, 0, C_DEPTH-1); + + for (i = 0; i < C_DEPTH; i = i + 1) + ram_data[i] = ram_data_tmp[i]; + + end + + if (C_DEPTH != (2**C_ADDR_WIDTH)) + begin + for (i = C_DEPTH; i < (2**C_ADDR_WIDTH); i = i + 1) + ram_data[i] = 'b0; + end + + a_reg = 'b0; + we_reg = 1'b0; + spra_reg = 'b0; + d_reg = 'b0; + qspo_ce_reg = 1'b0; + dpra_reg = 'b0; + qdpo_ce_reg = 1'b0; + + qspo_int = default_data; + qspo_pipe = 'b0; + qdpo_int = default_data; + qdpo_pipe = 'b0; + + max_address = C_DEPTH-1; + + srl_start = 0; + srl_end = 15; + + end // initial begin + + // Now look for writes to the memory (note that this means the + // memory is not a ROM and that the Write Enable WE is active. + always@(posedge CLK) + begin + if (C_MEM_TYPE != `c_rom && we_int) + begin + if (C_MEM_TYPE == `c_srl16) + begin + if (C_ADDR_WIDTH > 4) + begin + srl_start = a_int * 16; + if (srl_start + 16 > C_DEPTH) + srl_end = C_DEPTH - 1; + else + srl_end = (a_int*16) + 15; + end + else + begin + srl_start = 0; + srl_end = 15; + end + + for (i = srl_end; i > srl_start; i = i - 1) + ram_data[i] <= #`TCQ ram_data[i-1]; + + ram_data[srl_start] <= #`TCQ d_int; + end + else if (a_is_over) + begin + $display("WARNING in %m at time %d ns", $time); + $write("Writing to out of range address. "); + $display("Max address in %m is %d", C_DEPTH-1); + $display("Write will be ignored."); + end + else + ram_data[a_int] <= #`TCQ d_int; + end // if (C_MEM_TYPE != `c_rom && we_int) + end // always@ (posedge CLK) + + // Model optional input registers, which operate in the CLK clock domain. + always @(posedge CLK) + begin + if (!C_HAS_I_CE) + begin + we_reg <= #`TCQ WE; + a_reg <= #`TCQ A; + spra_reg <= #`TCQ SPRA; + d_reg <= #`TCQ D; + end + else if (!C_QUALIFY_WE) + begin + we_reg <= #`TCQ WE; + if (I_CE) + begin + a_reg <= #`TCQ A; + spra_reg <= #`TCQ SPRA; + d_reg <= #`TCQ D; + end + end + else if (C_QUALIFY_WE) + if (I_CE) + begin + we_reg <= #`TCQ WE; + a_reg <= #`TCQ A; + spra_reg <= #`TCQ SPRA; + d_reg <= #`TCQ D; + end + + qspo_ce_reg <= #`TCQ QSPO_CE; + end // always @ (posedge CLK) + + + assign we_int = (C_HAS_WE ? (C_REG_A_D_INPUTS ? we_reg : WE) : 1'b0); + assign d_int = (C_MEM_TYPE > 0 ? (C_REG_A_D_INPUTS ? d_reg : D) : 'b0); + assign a_int = (C_REG_A_D_INPUTS ? a_reg : A); + + assign spra_int = (C_MEM_TYPE == `c_srl16 ? (C_REG_A_D_INPUTS ? spra_reg : SPRA) : 'b0); + assign qspo_ce_int = (C_HAS_QSPO_CE ? (C_REG_A_D_INPUTS ? qspo_ce_reg : QSPO_CE) : 1'b0); + + assign qdpo_clk_int = (C_MEM_TYPE == `c_dp_ram ? + (C_HAS_QDPO_CLK == 1 ? QDPO_CLK : CLK) : 1'b0); + + always@(posedge qdpo_clk_int) + begin + if (C_QCE_JOINED) + begin + if (!C_HAS_QSPO_CE) + dpra_reg <= #`TCQ DPRA; + else if (QSPO_CE) + dpra_reg <= #`TCQ DPRA; + end + else + begin + if (!C_HAS_QDPO_CE) + dpra_reg <= #`TCQ DPRA; + else if (QDPO_CE) + dpra_reg <= #`TCQ DPRA; + end // else: !if(C_QCE_JOINED) + + qdpo_ce_reg <= #`TCQ QDPO_CE; + + end // always@ (posedge qdpo_clk_int) + + assign dpra_int = (C_MEM_TYPE == `c_dp_ram ? + (C_REG_DPRA_INPUT == 1 ? dpra_reg : DPRA) : 1'b0); + + assign qdpo_ce_int = (C_MEM_TYPE == `c_dp_ram ? + (C_HAS_QDPO_CE ? (C_REG_DPRA_INPUT ? qdpo_ce_reg : QDPO_CE) : 1'b0) : 1'b0); + + always@(posedge spra_is_over) + begin + if (C_MEM_TYPE == `c_srl16) + begin + $display("WARNING in %m at time %d ns: ", $time); + $write("Reading from out-of-range address. "); + $display("Max address in %m is %d", C_DEPTH-1); + end // if (C_MEM_TYPE == `c_srl16) + end // always@ (spra_int or CLK) + + always@(posedge a_is_over) + begin + if (C_MEM_TYPE != `c_srl16) + begin + $display("WARNING in %m at time %d ns: ", $time); + $write("Reading from out-of-range address. "); + $display("Max address in %m is %d", C_DEPTH-1); + end // if (C_MEM_TYPE != `c_srl16) + end // always@ (a_int or posedge CLK) + + assign SPO = (C_HAS_SPO ? spo_int : `allXs); + + always@(posedge dpra_is_over) + begin + if (C_MEM_TYPE == `c_dp_ram) + begin + $display("WARNING in %m at time %d ns: ", $time); + $write("Reading from out-of-range address. "); + $display("Max address in %m is %d", C_DEPTH-1); + end // if (C_MEM_TYPE == `c_dp_ram) + end // always@ (dpra_int) + + assign spo_int = (C_MEM_TYPE == `c_srl16 ? (spra_is_over ? data_srl_over : data_srl) : + (a_is_over ? data_sp_over : data_sp)); + + assign dpo_int = (C_MEM_TYPE == `c_dp_ram ? (dpra_is_over ? data_dp_over : data_dp) : `allXs); + + assign data_sp = ram_data[a_int]; + assign data_dp = ram_data[dpra_int]; + assign data_srl = ram_data[spra_int]; + + assign a_is_over = (a_int > max_address ? 1'b1 : 1'b0); + assign dpra_is_over = (dpra_int > max_address ? 1'b1 : 1'b0); + assign spra_is_over = (spra_int > max_address ? 1'b1 : 1'b0); + + assign a_over = a_int & max_address; + assign dpra_over = dpra_int & max_address; + assign spra_over = spra_int & max_address; + + assign data_sp_over = 'bx; + assign data_dp_over = 'bx; + assign data_srl_over = 'bx; + + assign DPO = (C_HAS_DPO ? dpo_int : `allXs); + + always@(posedge CLK or posedge QSPO_RST) + begin + if (C_HAS_QSPO_RST && QSPO_RST) + begin + qspo_pipe <= 'b0; + qspo_int <= 'b0; + end + else if (C_HAS_QSPO_SRST && QSPO_SRST) + begin + if (!C_HAS_QSPO_CE) + begin + qspo_pipe <= #`TCQ 'b0; + qspo_int <= #`TCQ 'b0; + end + else if (!C_SYNC_ENABLE) + begin + qspo_pipe <= #`TCQ 'b0; + qspo_int <= #`TCQ 'b0; + end + else if (C_HAS_QSPO_CE && qspo_ce_int) + begin + qspo_pipe <= #`TCQ 'b0; + qspo_int <= #`TCQ 'b0; + end + end // if (C_HAS_QSPO_SRST && QSPO_SRST) + + else if (C_HAS_QSPO_CE && qspo_ce_int) + begin + if (C_PIPELINE_STAGES == 1) + begin + qspo_int <= #`TCQ qspo_pipe; + end + else + begin + qspo_int <= #`TCQ spo_int; + end + qspo_pipe <= #`TCQ spo_int; + end + else if (!C_HAS_QSPO_CE) + begin + if (C_PIPELINE_STAGES == 1) + begin + qspo_int <= #`TCQ qspo_pipe; + end + else + begin + qspo_int <= #`TCQ spo_int; + end + qspo_pipe <= #`TCQ spo_int; + end // if (!C_HAS_QSPO_CE) + end // always@ (posedge CLK or QSPO_RST) + + assign QSPO = (C_HAS_QSPO == 1 ? qspo_int : `allXs); + + always@(posedge qdpo_clk_int or posedge QDPO_RST) + begin + if (C_HAS_QDPO_RST && QDPO_RST) + begin + qdpo_pipe <= 'b0; + qdpo_int <= 'b0; + end + else if (C_HAS_QDPO_SRST && QDPO_SRST) + begin + if (!C_SYNC_ENABLE) + begin + qdpo_pipe <= #`TCQ 'b0; + qdpo_int <= #`TCQ 'b0; + end + else if (!C_QCE_JOINED) + begin + if (!C_HAS_QDPO_CE) + begin + qdpo_pipe <= #`TCQ 'b0; + qdpo_int <= #`TCQ 'b0; + end + else if (C_HAS_QDPO_CE && qdpo_ce_int) + begin + qdpo_pipe <= #`TCQ 'b0; + qdpo_int <= #`TCQ 'b0; + end + end + else + begin + if (!C_HAS_QSPO_CE) + begin + qdpo_pipe <= #`TCQ 'b0; + qdpo_int <= #`TCQ 'b0; + end + else if (C_HAS_QSPO_CE && qspo_ce_int) + begin + qdpo_pipe <= #`TCQ 'b0; + qdpo_int <= #`TCQ 'b0; + end + end + end // if (C_HAS_QDPO_SRST && QDPO_SRST) + + else if (!C_QCE_JOINED) + begin + if (!C_HAS_QDPO_CE) + begin + qdpo_pipe <= #`TCQ dpo_int; + if (C_PIPELINE_STAGES == 1) + begin + qdpo_int <= #`TCQ qdpo_pipe; + end + else + begin + qdpo_int <= #`TCQ dpo_int; + end + end // if (!C_HAS_QDPO_CE) + else if (C_HAS_QDPO_CE && qdpo_ce_int) + begin + qdpo_pipe <= #`TCQ dpo_int; + if (C_PIPELINE_STAGES == 1) + begin + qdpo_int <= #`TCQ qdpo_pipe; + end + else + begin + qdpo_int <= #`TCQ dpo_int; + end + end // if (C_HAS_QDPO_CE && qdpo_ce_int) + end // if (!C_QCE_JOINED) + else if (C_QCE_JOINED) + begin + if (C_HAS_QSPO_CE && qspo_ce_int) + begin + qdpo_pipe <= #`TCQ dpo_int; + if (C_PIPELINE_STAGES == 1) + begin + qdpo_int <= #`TCQ qdpo_pipe; + end + else + begin + qdpo_int <= #`TCQ dpo_int; + end + end // if (C_HAS_QSPO_CE && qspo_ce_int) + else if (!C_HAS_QSPO_CE) + begin + qdpo_pipe <= #`TCQ dpo_int; + if (C_PIPELINE_STAGES == 1) + begin + qdpo_int <= #`TCQ qdpo_pipe; + end + else + begin + qdpo_int <= #`TCQ dpo_int; + end + end // if (!C_HAS_QSPO_CE) + end // if (C_QCE_JOINED) + end // always@ (posedge qdpo_clk_int or posedge QDPO_RST) + + assign QDPO = (C_HAS_QDPO == 1 ? qdpo_int : `allXs); + + function [C_WIDTH - 1 : 0] binstr_conv; + input [(C_WIDTH * 8) - 1 : 0] def_data; + integer index,i; + begin + index = 0; + binstr_conv = 'b0; + + for (i=C_WIDTH-1; i>=0; i=i-1) + begin + case (def_data[7:0]) + 8'b00000000 : i = -1; + 8'b00110000 : binstr_conv[index] = 1'b0; + 8'b00110001 : binstr_conv[index] = 1'b1; + default : + begin + $display("ERROR in %m at time %d ns: NOT A BINARY CHARACTER", $time); + binstr_conv[index] = 1'bx; + end + endcase // case(def_data[7:0]) + + index = index + 1; + def_data = def_data >> 8; + end // for (i=C_WIDTH-1; i>=0; i=i-1) + + end + endfunction // binstr_conv + +endmodule // DIST_MEM_GEN_V4_2 + +`undef all0s +`undef allXs +`undef c_rom +`undef c_sp_ram +`undef c_dp_ram +`undef c_srl16 diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/DIST_MEM_GEN_V4_2_XST.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/DIST_MEM_GEN_V4_2_XST.v new file mode 100644 index 0000000..1d84e6a --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/DIST_MEM_GEN_V4_2_XST.v @@ -0,0 +1,169 @@ +// Copyright(C) 2007 by Xilinx, Inc. All rights reserved. +// This text/file contains proprietary, confidential +// information of Xilinx, Inc., is distributed under license +// from Xilinx, Inc., and may be used, copied and/or +// disclosed only pursuant to the terms of a valid license +// agreement with Xilinx, Inc. Xilinx hereby grants you +// a license to use this text/file solely for design, simulation, +// implementation and creation of design files limited +// to Xilinx devices or technologies. Use with non-Xilinx +// devices or technologies is expressly prohibited and +// immediately terminates your license unless covered by +// a separate agreement. +// +// Xilinx is providing this design, code, or information +// "as is" solely for use in developing programs and +// solutions for Xilinx devices. By providing this design, +// code, or information as one possible implementation of +// this feature, application or standard, Xilinx is making no +// representation that this implementation is free from any +// claims of infringement. You are responsible for +// obtaining any rights you may require for your implementation. +// Xilinx expressly disclaims any warranty whatsoever with +// respect to the adequacy of the implementation, including +// but not limited to any warranties or representations that this +// implementation is free from claims of infringement, implied +// warranties of merchantability or fitness for a particular +// purpose. +// +// Xilinx products are not intended for use in life support +// appliances, devices, or systems. Use in such applications are +// expressly prohibited. +// +// This copyright and support notice must be retained as part +// of this text at all times. (c) Copyright 1995-2006 Xilinx, Inc. +// All rights reserved. + + + +/* $RCSfile: DIST_MEM_GEN_V4_2_XST.v,v $ +-- +-- Filename - DIST_MEM_GEN_V4_2_XST.v +-- Author - Xilinx +-- Creation - 14 Nov 2007 +-- +-- Description +-- Distributed Memory Simulation Model +*/ + + +`timescale 1ps/1ps + +module DIST_MEM_GEN_V4_2_XST +#( + parameter C_FAMILY = "virtex5", + parameter C_ADDR_WIDTH = 6, + parameter C_DEFAULT_DATA = "0", + parameter C_DEPTH = 64, + parameter C_HAS_CLK = 1, + parameter C_HAS_D = 1, + parameter C_HAS_DPO = 0, + parameter C_HAS_DPRA = 0, + parameter C_HAS_I_CE = 0, + parameter C_HAS_QDPO = 0, + parameter C_HAS_QDPO_CE = 0, + parameter C_HAS_QDPO_CLK = 0, + parameter C_HAS_QDPO_RST = 0, + parameter C_HAS_QDPO_SRST = 0, + parameter C_HAS_QSPO = 0, + parameter C_HAS_QSPO_CE = 0, + parameter C_HAS_QSPO_RST = 0, + parameter C_HAS_QSPO_SRST = 0, + parameter C_HAS_SPO = 1, + parameter C_HAS_SPRA = 0, + parameter C_HAS_WE = 1, + parameter C_MEM_INIT_FILE = "null.mif", + parameter C_ELABORATION_DIR = "./", + parameter C_MEM_TYPE = 1, + parameter C_PIPELINE_STAGES = 0, + parameter C_QCE_JOINED = 0, + parameter C_QUALIFY_WE = 0, + parameter C_READ_MIF = 0, + parameter C_REG_A_D_INPUTS = 0, + parameter C_REG_DPRA_INPUT = 0, + parameter C_SYNC_ENABLE = 0, + parameter C_WIDTH = 16, + parameter C_PARSER_TYPE = 1 +) +( + input [C_ADDR_WIDTH-1 - (C_ADDR_WIDTH>4?(4*C_HAS_SPRA):0) : 0] A, + input [C_WIDTH-1 : 0] D, + input [C_ADDR_WIDTH-1 : 0] DPRA, + input [C_ADDR_WIDTH-1 : 0] SPRA, + input CLK, + input WE, + input I_CE, + input QSPO_CE, + input QDPO_CE, + input QDPO_CLK, + input QSPO_RST, + input QDPO_RST, + input QSPO_SRST, + input QDPO_SRST, + output [C_WIDTH-1 : 0] SPO, + output [C_WIDTH-1 : 0] QSPO, + output [C_WIDTH-1 : 0] DPO, + output [C_WIDTH-1 : 0] QDPO +); + + DIST_MEM_GEN_V4_2 + #( + .C_FAMILY (C_FAMILY), + .C_ADDR_WIDTH (C_ADDR_WIDTH), + .C_DEFAULT_DATA (C_DEFAULT_DATA), + .C_DEPTH (C_DEPTH), + .C_HAS_CLK (C_HAS_CLK), + .C_HAS_D (C_HAS_D), + .C_HAS_DPO (C_HAS_DPO), + .C_HAS_DPRA (C_HAS_DPRA), + .C_HAS_I_CE (C_HAS_I_CE), + .C_HAS_QDPO (C_HAS_QDPO), + .C_HAS_QDPO_CE (C_HAS_QDPO_CE), + .C_HAS_QDPO_CLK (C_HAS_QDPO_CLK), + .C_HAS_QDPO_RST (C_HAS_QDPO_RST), + .C_HAS_QDPO_SRST (C_HAS_QDPO_SRST), + .C_HAS_QSPO (C_HAS_QSPO), + .C_HAS_QSPO_CE (C_HAS_QSPO_CE), + .C_HAS_QSPO_RST (C_HAS_QSPO_RST), + .C_HAS_QSPO_SRST (C_HAS_QSPO_SRST), + .C_HAS_SPO (C_HAS_SPO), + .C_HAS_SPRA (C_HAS_SPRA), + .C_HAS_WE (C_HAS_WE), + .C_MEM_INIT_FILE (C_MEM_INIT_FILE), + .C_ELABORATION_DIR (C_ELABORATION_DIR), + .C_MEM_TYPE (C_MEM_TYPE), + .C_PIPELINE_STAGES (C_PIPELINE_STAGES), + .C_QCE_JOINED (C_QCE_JOINED), + .C_QUALIFY_WE (C_QUALIFY_WE), + .C_READ_MIF (C_READ_MIF), + .C_REG_A_D_INPUTS (C_REG_A_D_INPUTS), + .C_REG_DPRA_INPUT (C_REG_DPRA_INPUT), + .C_SYNC_ENABLE (C_SYNC_ENABLE), + .C_WIDTH (C_WIDTH), + .C_PARSER_TYPE (C_PARSER_TYPE) + ) dist_mem_gen_v4_2_dut + ( + .A (A), + .D (D), + .DPRA (DPRA), + .SPRA (SPRA), + .CLK (CLK), + .WE (WR), + .I_CE (I_CE), + .QSPO_CE (QSPO_CE), + .QDPO_CE (QDPO_CE), + .QDPO_CLK (QDPO_CLK), + .QSPO_RST (QSPO_RST), + .QDPO_RST (QDPO_RST), + .QSPO_SRST (QSPO_SRST ), + .QDPO_SRST (QDPO_SRS), + .SPO (SPO), + .DPO (DPO), + .QSPO (QSPO), + .QDPO (QDPO) + ); + +endmodule + + + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/DIST_MEM_GEN_V4_3.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/DIST_MEM_GEN_V4_3.v new file mode 100644 index 0000000..9522a32 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/DIST_MEM_GEN_V4_3.v @@ -0,0 +1,634 @@ +/* + ******************************************************************************* + * + * Distributed Memory Generator - Verilog Behavioral Model + * + ******************************************************************************* + * + * (c) Copyright 1995 - 2009 Xilinx, Inc. All rights reserved. + * + * This file contains confidential and proprietary information + * of Xilinx, Inc. and is protected under U.S. and + * international copyright and other intellectual property + * laws. + * + * DISCLAIMER + * This disclaimer is not a license and does not grant any + * rights to the materials distributed herewith. Except as + * otherwise provided in a valid license issued to you by + * Xilinx, and to the maximum extent permitted by applicable + * law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND + * WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES + * AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING + * BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- + * INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and + * (2) Xilinx shall not be liable (whether in contract or tort, + * including negligence, or under any other theory of + * liability) for any loss or damage of any kind or nature + * related to, arising under or in connection with these + * materials, including for any direct, or any indirect, + * special, incidental, or consequential loss or damage + * (including loss of data, profits, goodwill, or any type of + * loss or damage suffered as a result of any action brought + * by a third party) even if such damage or loss was + * reasonably foreseeable or Xilinx had been advised of the + * possibility of the same. + * + * CRITICAL APPLICATIONS + * Xilinx products are not designed or intended to be fail- + * safe, or for use in any application requiring fail-safe + * performance, such as life-support or safety devices or + * systems, Class III medical devices, nuclear facilities, + * applications related to the deployment of airbags, or any + * other applications that could lead to death, personal + * injury, or severe property or environmental damage + * (individually and collectively, "Critical + * Applications"). Customer assumes the sole risk and + * liability of any use of Xilinx products in Critical + * Applications, subject only to applicable laws and + * regulations governing limitations on product liability. + * + * THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS + * PART OF THIS FILE AT ALL TIMES. + * + ******************************************************************************* + ******************************************************************************* + * + * Filename : DIST_MEM_GEN_V4_3.v + * + * Author : Xilinx + * + * Description : Distributed Memory Simulation Model + * + ******************************************************************************* + */ + +`timescale 1ps/1ps +`ifndef TCQ + `define TCQ 100 +`endif + +`define all0s {C_WIDTH{1'b0}} +`define allXs {C_WIDTH{1'bx}} +`define c_rom 0 +`define c_sp_ram 1 +`define c_dp_ram 2 +`define c_srl16 3 +`define c_sdp_ram 4 + +module DIST_MEM_GEN_V4_3 (A, D, DPRA, SPRA, CLK, WE, I_CE, QSPO_CE, QDPO_CE, QDPO_CLK, QSPO_RST, QDPO_RST, QSPO_SRST, QDPO_SRST, SPO, DPO, QSPO, QDPO); + + parameter C_FAMILY = "virtex5"; + parameter C_ADDR_WIDTH = 6; + parameter C_DEFAULT_DATA = "0"; + parameter C_DEPTH = 64; + parameter C_HAS_CLK = 1; + parameter C_HAS_D = 1; + parameter C_HAS_DPO = 0; + parameter C_HAS_DPRA = 0; + parameter C_HAS_I_CE = 0; + parameter C_HAS_QDPO = 0; + parameter C_HAS_QDPO_CE = 0; + parameter C_HAS_QDPO_CLK = 0; + parameter C_HAS_QDPO_RST = 0; + parameter C_HAS_QDPO_SRST = 0; + parameter C_HAS_QSPO = 0; + parameter C_HAS_QSPO_CE = 0; + parameter C_HAS_QSPO_RST = 0; + parameter C_HAS_QSPO_SRST = 0; + parameter C_HAS_SPO = 1; + parameter C_HAS_SPRA = 0; + parameter C_HAS_WE = 1; + parameter C_MEM_INIT_FILE = "null.mif"; + parameter C_MEM_TYPE = 1; + parameter C_PIPELINE_STAGES = 0; + parameter C_QCE_JOINED = 0; + parameter C_QUALIFY_WE = 0; + parameter C_READ_MIF = 0; + parameter C_REG_A_D_INPUTS = 0; + parameter C_REG_DPRA_INPUT = 0; + parameter C_SYNC_ENABLE = 0; + parameter C_WIDTH = 16; + parameter C_PARSER_TYPE = 1; + + input [C_ADDR_WIDTH-1 - (C_ADDR_WIDTH>4?(4*C_HAS_SPRA):0) : 0] A; + input [C_WIDTH-1 : 0] D; + input [C_ADDR_WIDTH-1 : 0] DPRA; + input [C_ADDR_WIDTH-1 : 0] SPRA; + input CLK; + input WE; + input I_CE; + input QSPO_CE; + input QDPO_CE; + input QDPO_CLK; + input QSPO_RST; + input QDPO_RST; + input QSPO_SRST; + input QDPO_SRST; + output [C_WIDTH-1 : 0] SPO; + output [C_WIDTH-1 : 0] QSPO; + output [C_WIDTH-1 : 0] DPO; + output [C_WIDTH-1 : 0] QDPO; + + // Address signal connected to memory + wire [C_ADDR_WIDTH - 1 : 0] a_int; + + // Read Address connected to srl16 memory + wire [C_ADDR_WIDTH - 1 : 0] spra_int; + + // Input data signal connected to memory + wire [C_WIDTH - 1 : 0] d_int; + + // Internal Write Enable + wire we_int; + + // Internal QSPO Clock Enable + wire qspo_ce_int; + + // Internal QDPO Clock + wire qdpo_clk_int; + + // Internal Dual Port Read Address connected to memory + wire [C_ADDR_WIDTH - 1 : 0] dpra_int; + + // Internal QDPO Clock Enable + wire qdpo_ce_int; + + // Registered Write Enable + reg we_reg; + + // Registered Address connected to memory + reg [C_ADDR_WIDTH - 1 : 0] a_reg; + + // Registered Read Address connected to srl16 memory + reg [C_ADDR_WIDTH - 1 : 0] spra_reg; + + // Registered data signal connected to memory + reg [C_WIDTH-1 : 0] d_reg; + + // Registered QSPO Clock Enable + reg qspo_ce_reg; + + // Registered Dual Port Read Address connected to memory + reg [C_ADDR_WIDTH - 1 : 0] dpra_reg; + + // Registered QDPO Clock Enable + reg qdpo_ce_reg; + + // Internal Single Port RAM output signal + wire [C_WIDTH - 1 : 0] spo_int; + + // Internal Dual Port RAM output signal + wire [C_WIDTH - 1 : 0] dpo_int; + + // Internal ROM/Single Port RAM/SRL16 RAM + // registered output + reg [C_WIDTH - 1 : 0] qspo_int; + + // Pipeline registers + reg [C_WIDTH - 1 : 0] qspo_pipe; + + // Internal Dual Port RAM registered output + reg [C_WIDTH - 1 : 0] qdpo_int; + + // Pipeline registers + reg [C_WIDTH - 1 : 0] qdpo_pipe; + + reg [C_WIDTH-1 : 0] ram_data [(2**C_ADDR_WIDTH)-1 : 0]; + reg [C_WIDTH-1 : 0] ram_data_tmp[C_DEPTH-1 : 0]; + + + reg [C_WIDTH-1 : 0] default_data; + + wire [C_WIDTH-1 : 0] data_sp; + wire [C_WIDTH-1 : 0] data_dp; + wire [C_WIDTH-1 : 0] data_srl; + + wire [C_WIDTH-1 : 0] data_sp_over; + wire [C_WIDTH-1 : 0] data_dp_over; + wire [C_WIDTH-1 : 0] data_srl_over; + + wire [C_ADDR_WIDTH - 1 : 0] a_over; + wire [C_ADDR_WIDTH - 1 : 0] dpra_over; + wire [C_ADDR_WIDTH - 1 : 0] spra_over; + + wire a_is_over; + wire dpra_is_over; + wire spra_is_over; + + reg [C_ADDR_WIDTH-1 : 0] max_address; + + integer i; + integer j; + integer srl_start; + integer srl_end; + + + // Initial block - initialise the memory, + // and when appropriate write content into the given address. + initial + begin + $display("WARNING: This core is supplied with a behavioral model. To model cycle-accurate behavior you must run timing simulation."); + + + default_data = 'b0; + default_data = binstr_conv(C_DEFAULT_DATA); + + // Assign that C_DEFAULT_DATA to each address in the memory. + for (i = 0; i < C_DEPTH; i = i + 1) + begin + ram_data[i] = default_data; + ram_data_tmp[i] = default_data; + end + + //Read the MIF file, and use it to initialise the content of ram_data + //if that is required. + if (C_READ_MIF) + begin + $readmemb(C_MEM_INIT_FILE, ram_data_tmp, 0, C_DEPTH-1); + + for (i = 0; i < C_DEPTH; i = i + 1) + ram_data[i] = ram_data_tmp[i]; + + end + + if (C_DEPTH != (2**C_ADDR_WIDTH)) + begin + for (i = C_DEPTH; i < (2**C_ADDR_WIDTH); i = i + 1) + ram_data[i] = 'b0; + end + + a_reg = 'b0; + we_reg = 1'b0; + spra_reg = 'b0; + d_reg = 'b0; + qspo_ce_reg = 1'b0; + dpra_reg = 'b0; + qdpo_ce_reg = 1'b0; + + qspo_int = default_data; + qspo_pipe = 'b0; + qdpo_int = default_data; + qdpo_pipe = 'b0; + + max_address = C_DEPTH-1; + + srl_start = 0; + srl_end = 15; + + end // initial begin + + // Now look for writes to the memory (note that this means the + // memory is not a ROM and that the Write Enable WE is active. + always@(posedge CLK) + begin + if (C_MEM_TYPE != `c_rom && we_int) + begin + if (C_MEM_TYPE == `c_srl16) + begin + if (C_ADDR_WIDTH > 4) + begin + srl_start = a_int * 16; + if (srl_start + 16 > C_DEPTH) + srl_end = C_DEPTH - 1; + else + srl_end = (a_int*16) + 15; + end + else + begin + srl_start = 0; + srl_end = 15; + end + + for (i = srl_end; i > srl_start; i = i - 1) + ram_data[i] <= #`TCQ ram_data[i-1]; + + ram_data[srl_start] <= #`TCQ d_int; + end + else if (a_is_over) + begin + $display("WARNING in %m at time %d ns", $time); + $write("Writing to out of range address. "); + $display("Max address in %m is %d", C_DEPTH-1); + $display("Write will be ignored."); + end + else + ram_data[a_int] <= #`TCQ d_int; + end // if (C_MEM_TYPE != `c_rom && we_int) + end // always@ (posedge CLK) + + // Model optional input registers, which operate in the CLK clock domain. + always @(posedge CLK) + begin + if (!C_HAS_I_CE) + begin + we_reg <= #`TCQ WE; + a_reg <= #`TCQ A; + spra_reg <= #`TCQ SPRA; + d_reg <= #`TCQ D; + end + else if (!C_QUALIFY_WE) + begin + we_reg <= #`TCQ WE; + if (I_CE) + begin + a_reg <= #`TCQ A; + spra_reg <= #`TCQ SPRA; + d_reg <= #`TCQ D; + end + end + else if (C_QUALIFY_WE) + if (I_CE) + begin + we_reg <= #`TCQ WE; + a_reg <= #`TCQ A; + spra_reg <= #`TCQ SPRA; + d_reg <= #`TCQ D; + end + + qspo_ce_reg <= #`TCQ QSPO_CE; + end // always @ (posedge CLK) + + + assign we_int = (C_HAS_WE ? (C_REG_A_D_INPUTS ? we_reg : WE) : 1'b0); + assign d_int = (C_MEM_TYPE > 0 ? (C_REG_A_D_INPUTS ? d_reg : D) : 'b0); + assign a_int = (C_REG_A_D_INPUTS ? a_reg : A); + + assign spra_int = (C_MEM_TYPE == `c_srl16 ? (C_REG_A_D_INPUTS ? spra_reg : SPRA) : 'b0); + assign qspo_ce_int = (C_HAS_QSPO_CE ? (C_REG_A_D_INPUTS ? qspo_ce_reg : QSPO_CE) : 1'b0); + + assign qdpo_clk_int = (((C_MEM_TYPE == `c_dp_ram) || (C_MEM_TYPE == `c_sdp_ram)) ? + (C_HAS_QDPO_CLK == 1 ? QDPO_CLK : CLK) : 1'b0); + + always@(posedge qdpo_clk_int) + begin + if (C_QCE_JOINED) + begin + if (!C_HAS_QSPO_CE) + dpra_reg <= #`TCQ DPRA; + else if (QSPO_CE) + dpra_reg <= #`TCQ DPRA; + end + else + begin + if (!C_HAS_QDPO_CE) + dpra_reg <= #`TCQ DPRA; + else if (QDPO_CE) + dpra_reg <= #`TCQ DPRA; + end // else: !if(C_QCE_JOINED) + + qdpo_ce_reg <= #`TCQ QDPO_CE; + + end // always@ (posedge qdpo_clk_int) + + assign dpra_int = (((C_MEM_TYPE == `c_dp_ram) || (C_MEM_TYPE == `c_sdp_ram)) ? + (C_REG_DPRA_INPUT == 1 ? dpra_reg : DPRA) : 1'b0); + + assign qdpo_ce_int = (((C_MEM_TYPE == `c_dp_ram) || (C_MEM_TYPE == `c_sdp_ram)) ? + (C_HAS_QDPO_CE ? (C_REG_DPRA_INPUT ? qdpo_ce_reg : QDPO_CE) : 1'b0) : 1'b0); + + always@(posedge spra_is_over) + begin + if (C_MEM_TYPE == `c_srl16) + begin + $display("WARNING in %m at time %d ns: ", $time); + $write("Reading from out-of-range address. "); + $display("Max address in %m is %d", C_DEPTH-1); + end // if (C_MEM_TYPE == `c_srl16) + end // always@ (spra_int or CLK) + + always@(posedge a_is_over) + begin + if (C_MEM_TYPE != `c_srl16) + begin + $display("WARNING in %m at time %d ns: ", $time); + $write("Reading from out-of-range address. "); + $display("Max address in %m is %d", C_DEPTH-1); + end // if (C_MEM_TYPE != `c_srl16) + end // always@ (a_int or posedge CLK) + + assign SPO = (C_HAS_SPO ? spo_int : `allXs); + + always@(posedge dpra_is_over) + begin + if ((C_MEM_TYPE == `c_dp_ram) || (C_MEM_TYPE == `c_sdp_ram)) + begin + $display("WARNING in %m at time %d ns: ", $time); + $write("Reading from out-of-range address. "); + $display("Max address in %m is %d", C_DEPTH-1); + end // if (C_MEM_TYPE == `c_dp_ram) + end // always@ (dpra_int) + + assign spo_int = (C_MEM_TYPE == `c_srl16 ? (spra_is_over ? data_srl_over : data_srl) : + (a_is_over ? data_sp_over : data_sp)); + + assign dpo_int = (((C_MEM_TYPE == `c_dp_ram) || (C_MEM_TYPE == `c_sdp_ram)) ? (dpra_is_over ? data_dp_over : data_dp) : `allXs); + + assign data_sp = ram_data[a_int]; + assign data_dp = ram_data[dpra_int]; + assign data_srl = ram_data[spra_int]; + + assign a_is_over = (a_int > max_address ? 1'b1 : 1'b0); + assign dpra_is_over = (dpra_int > max_address ? 1'b1 : 1'b0); + assign spra_is_over = (spra_int > max_address ? 1'b1 : 1'b0); + + assign a_over = a_int & max_address; + assign dpra_over = dpra_int & max_address; + assign spra_over = spra_int & max_address; + + assign data_sp_over = 'bx; + assign data_dp_over = 'bx; + assign data_srl_over = 'bx; + + assign DPO = (C_HAS_DPO ? dpo_int : `allXs); + + always@(posedge CLK or posedge QSPO_RST) + begin + if (C_HAS_QSPO_RST && QSPO_RST) + begin + qspo_pipe <= 'b0; + qspo_int <= 'b0; + end + else if (C_HAS_QSPO_SRST && QSPO_SRST) + begin + if (!C_HAS_QSPO_CE) + begin + qspo_pipe <= #`TCQ 'b0; + qspo_int <= #`TCQ 'b0; + end + else if (!C_SYNC_ENABLE) + begin + qspo_pipe <= #`TCQ 'b0; + qspo_int <= #`TCQ 'b0; + end + else if (C_HAS_QSPO_CE && qspo_ce_int) + begin + qspo_pipe <= #`TCQ 'b0; + qspo_int <= #`TCQ 'b0; + end + end // if (C_HAS_QSPO_SRST && QSPO_SRST) + + else if (C_HAS_QSPO_CE && qspo_ce_int) + begin + if (C_PIPELINE_STAGES == 1) + begin + qspo_int <= #`TCQ qspo_pipe; + end + else + begin + qspo_int <= #`TCQ spo_int; + end + qspo_pipe <= #`TCQ spo_int; + end + else if (!C_HAS_QSPO_CE) + begin + if (C_PIPELINE_STAGES == 1) + begin + qspo_int <= #`TCQ qspo_pipe; + end + else + begin + qspo_int <= #`TCQ spo_int; + end + qspo_pipe <= #`TCQ spo_int; + end // if (!C_HAS_QSPO_CE) + end // always@ (posedge CLK or QSPO_RST) + + assign QSPO = (C_HAS_QSPO == 1 ? qspo_int : `allXs); + + always@(posedge qdpo_clk_int or posedge QDPO_RST) + begin + if (C_HAS_QDPO_RST && QDPO_RST) + begin + qdpo_pipe <= 'b0; + qdpo_int <= 'b0; + end + else if (C_HAS_QDPO_SRST && QDPO_SRST) + begin + if (!C_SYNC_ENABLE) + begin + qdpo_pipe <= #`TCQ 'b0; + qdpo_int <= #`TCQ 'b0; + end + else if (!C_QCE_JOINED) + begin + if (!C_HAS_QDPO_CE) + begin + qdpo_pipe <= #`TCQ 'b0; + qdpo_int <= #`TCQ 'b0; + end + else if (C_HAS_QDPO_CE && qdpo_ce_int) + begin + qdpo_pipe <= #`TCQ 'b0; + qdpo_int <= #`TCQ 'b0; + end + end + else + begin + if (!C_HAS_QSPO_CE) + begin + qdpo_pipe <= #`TCQ 'b0; + qdpo_int <= #`TCQ 'b0; + end + else if (C_HAS_QSPO_CE && qspo_ce_int) + begin + qdpo_pipe <= #`TCQ 'b0; + qdpo_int <= #`TCQ 'b0; + end + end + end // if (C_HAS_QDPO_SRST && QDPO_SRST) + + else if (!C_QCE_JOINED) + begin + if (!C_HAS_QDPO_CE) + begin + qdpo_pipe <= #`TCQ dpo_int; + if (C_PIPELINE_STAGES == 1) + begin + qdpo_int <= #`TCQ qdpo_pipe; + end + else + begin + qdpo_int <= #`TCQ dpo_int; + end + end // if (!C_HAS_QDPO_CE) + else if (C_HAS_QDPO_CE && qdpo_ce_int) + begin + qdpo_pipe <= #`TCQ dpo_int; + if (C_PIPELINE_STAGES == 1) + begin + qdpo_int <= #`TCQ qdpo_pipe; + end + else + begin + qdpo_int <= #`TCQ dpo_int; + end + end // if (C_HAS_QDPO_CE && qdpo_ce_int) + end // if (!C_QCE_JOINED) + else if (C_QCE_JOINED) + begin + if (C_HAS_QSPO_CE && qspo_ce_int) + begin + qdpo_pipe <= #`TCQ dpo_int; + if (C_PIPELINE_STAGES == 1) + begin + qdpo_int <= #`TCQ qdpo_pipe; + end + else + begin + qdpo_int <= #`TCQ dpo_int; + end + end // if (C_HAS_QSPO_CE && qspo_ce_int) + else if (!C_HAS_QSPO_CE) + begin + qdpo_pipe <= #`TCQ dpo_int; + if (C_PIPELINE_STAGES == 1) + begin + qdpo_int <= #`TCQ qdpo_pipe; + end + else + begin + qdpo_int <= #`TCQ dpo_int; + end + end // if (!C_HAS_QSPO_CE) + end // if (C_QCE_JOINED) + end // always@ (posedge qdpo_clk_int or posedge QDPO_RST) + + assign QDPO = (C_HAS_QDPO == 1 ? qdpo_int : `allXs); + + function [C_WIDTH - 1 : 0] binstr_conv; + input [(C_WIDTH * 8) - 1 : 0] def_data; + integer index,i; + begin + index = 0; + binstr_conv = 'b0; + + for (i=C_WIDTH-1; i>=0; i=i-1) + begin + case (def_data[7:0]) + 8'b00000000 : i = -1; + 8'b00110000 : binstr_conv[index] = 1'b0; + 8'b00110001 : binstr_conv[index] = 1'b1; + default : + begin + $display("ERROR in %m at time %d ns: NOT A BINARY CHARACTER", $time); + binstr_conv[index] = 1'bx; + end + endcase // case(def_data[7:0]) + + index = index + 1; + def_data = def_data >> 8; + end // for (i=C_WIDTH-1; i>=0; i=i-1) + + end + endfunction // binstr_conv + +endmodule // DIST_MEM_GEN_V4_3 + +`undef all0s +`undef allXs +`undef c_rom +`undef c_sp_ram +`undef c_dp_ram +`undef c_srl16 +`undef c_sdp_ram diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/DIST_MEM_GEN_V4_3_XST.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/DIST_MEM_GEN_V4_3_XST.v new file mode 100644 index 0000000..f7bfec1 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/DIST_MEM_GEN_V4_3_XST.v @@ -0,0 +1,174 @@ +/* + ******************************************************************************* + * + * (c) Copyright 1995 - 2009 Xilinx, Inc. All rights reserved. + * + * This file contains confidential and proprietary information + * of Xilinx, Inc. and is protected under U.S. and + * international copyright and other intellectual property + * laws. + * + * DISCLAIMER + * This disclaimer is not a license and does not grant any + * rights to the materials distributed herewith. Except as + * otherwise provided in a valid license issued to you by + * Xilinx, and to the maximum extent permitted by applicable + * law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND + * WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES + * AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING + * BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- + * INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and + * (2) Xilinx shall not be liable (whether in contract or tort, + * including negligence, or under any other theory of + * liability) for any loss or damage of any kind or nature + * related to, arising under or in connection with these + * materials, including for any direct, or any indirect, + * special, incidental, or consequential loss or damage + * (including loss of data, profits, goodwill, or any type of + * loss or damage suffered as a result of any action brought + * by a third party) even if such damage or loss was + * reasonably foreseeable or Xilinx had been advised of the + * possibility of the same. + * + * CRITICAL APPLICATIONS + * Xilinx products are not designed or intended to be fail- + * safe, or for use in any application requiring fail-safe + * performance, such as life-support or safety devices or + * systems, Class III medical devices, nuclear facilities, + * applications related to the deployment of airbags, or any + * other applications that could lead to death, personal + * injury, or severe property or environmental damage + * (individually and collectively, "Critical + * Applications"). Customer assumes the sole risk and + * liability of any use of Xilinx products in Critical + * Applications, subject only to applicable laws and + * regulations governing limitations on product liability. + * + * THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS + * PART OF THIS FILE AT ALL TIMES. + * + ******************************************************************************* + ******************************************************************************* + */ + + +`timescale 1ps/1ps + +module DIST_MEM_GEN_V4_3_XST +#( + parameter C_FAMILY = "virtex5", + parameter C_ADDR_WIDTH = 6, + parameter C_DEFAULT_DATA = "0", + parameter C_DEPTH = 64, + parameter C_HAS_CLK = 1, + parameter C_HAS_D = 1, + parameter C_HAS_DPO = 0, + parameter C_HAS_DPRA = 0, + parameter C_HAS_I_CE = 0, + parameter C_HAS_QDPO = 0, + parameter C_HAS_QDPO_CE = 0, + parameter C_HAS_QDPO_CLK = 0, + parameter C_HAS_QDPO_RST = 0, + parameter C_HAS_QDPO_SRST = 0, + parameter C_HAS_QSPO = 0, + parameter C_HAS_QSPO_CE = 0, + parameter C_HAS_QSPO_RST = 0, + parameter C_HAS_QSPO_SRST = 0, + parameter C_HAS_SPO = 1, + parameter C_HAS_SPRA = 0, + parameter C_HAS_WE = 1, + parameter C_MEM_INIT_FILE = "null.mif", + parameter C_ELABORATION_DIR = "./", + parameter C_MEM_TYPE = 1, + parameter C_PIPELINE_STAGES = 0, + parameter C_QCE_JOINED = 0, + parameter C_QUALIFY_WE = 0, + parameter C_READ_MIF = 0, + parameter C_REG_A_D_INPUTS = 0, + parameter C_REG_DPRA_INPUT = 0, + parameter C_SYNC_ENABLE = 0, + parameter C_WIDTH = 16, + parameter C_PARSER_TYPE = 1 +) +( + input [C_ADDR_WIDTH-1 - (C_ADDR_WIDTH>4?(4*C_HAS_SPRA):0) : 0] A, + input [C_WIDTH-1 : 0] D, + input [C_ADDR_WIDTH-1 : 0] DPRA, + input [C_ADDR_WIDTH-1 : 0] SPRA, + input CLK, + input WE, + input I_CE, + input QSPO_CE, + input QDPO_CE, + input QDPO_CLK, + input QSPO_RST, + input QDPO_RST, + input QSPO_SRST, + input QDPO_SRST, + output [C_WIDTH-1 : 0] SPO, + output [C_WIDTH-1 : 0] QSPO, + output [C_WIDTH-1 : 0] DPO, + output [C_WIDTH-1 : 0] QDPO +); + + DIST_MEM_GEN_V4_3 + #( + .C_FAMILY (C_FAMILY), + .C_ADDR_WIDTH (C_ADDR_WIDTH), + .C_DEFAULT_DATA (C_DEFAULT_DATA), + .C_DEPTH (C_DEPTH), + .C_HAS_CLK (C_HAS_CLK), + .C_HAS_D (C_HAS_D), + .C_HAS_DPO (C_HAS_DPO), + .C_HAS_DPRA (C_HAS_DPRA), + .C_HAS_I_CE (C_HAS_I_CE), + .C_HAS_QDPO (C_HAS_QDPO), + .C_HAS_QDPO_CE (C_HAS_QDPO_CE), + .C_HAS_QDPO_CLK (C_HAS_QDPO_CLK), + .C_HAS_QDPO_RST (C_HAS_QDPO_RST), + .C_HAS_QDPO_SRST (C_HAS_QDPO_SRST), + .C_HAS_QSPO (C_HAS_QSPO), + .C_HAS_QSPO_CE (C_HAS_QSPO_CE), + .C_HAS_QSPO_RST (C_HAS_QSPO_RST), + .C_HAS_QSPO_SRST (C_HAS_QSPO_SRST), + .C_HAS_SPO (C_HAS_SPO), + .C_HAS_SPRA (C_HAS_SPRA), + .C_HAS_WE (C_HAS_WE), + .C_MEM_INIT_FILE (C_MEM_INIT_FILE), + .C_ELABORATION_DIR (C_ELABORATION_DIR), + .C_MEM_TYPE (C_MEM_TYPE), + .C_PIPELINE_STAGES (C_PIPELINE_STAGES), + .C_QCE_JOINED (C_QCE_JOINED), + .C_QUALIFY_WE (C_QUALIFY_WE), + .C_READ_MIF (C_READ_MIF), + .C_REG_A_D_INPUTS (C_REG_A_D_INPUTS), + .C_REG_DPRA_INPUT (C_REG_DPRA_INPUT), + .C_SYNC_ENABLE (C_SYNC_ENABLE), + .C_WIDTH (C_WIDTH), + .C_PARSER_TYPE (C_PARSER_TYPE) + ) dist_mem_gen_v4_3_dut + ( + .A (A), + .D (D), + .DPRA (DPRA), + .SPRA (SPRA), + .CLK (CLK), + .WE (WR), + .I_CE (I_CE), + .QSPO_CE (QSPO_CE), + .QDPO_CE (QDPO_CE), + .QDPO_CLK (QDPO_CLK), + .QSPO_RST (QSPO_RST), + .QDPO_RST (QDPO_RST), + .QSPO_SRST (QSPO_SRST ), + .QDPO_SRST (QDPO_SRS), + .SPO (SPO), + .DPO (DPO), + .QSPO (QSPO), + .QDPO (QDPO) + ); + +endmodule + + + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/DIST_MEM_GEN_V5_1.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/DIST_MEM_GEN_V5_1.v new file mode 100644 index 0000000..477e6a7 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/DIST_MEM_GEN_V5_1.v @@ -0,0 +1,640 @@ +/* + ******************************************************************************* + * + * Distributed Memory Generator - Verilog Behavioral Model + * + ******************************************************************************* + * + * (c) Copyright 1995 - 2009 Xilinx, Inc. All rights reserved. + * + * This file contains confidential and proprietary information + * of Xilinx, Inc. and is protected under U.S. and + * international copyright and other intellectual property + * laws. + * + * DISCLAIMER + * This disclaimer is not a license and does not grant any + * rights to the materials distributed herewith. Except as + * otherwise provided in a valid license issued to you by + * Xilinx, and to the maximum extent permitted by applicable + * law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND + * WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES + * AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING + * BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- + * INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and + * (2) Xilinx shall not be liable (whether in contract or tort, + * including negligence, or under any other theory of + * liability) for any loss or damage of any kind or nature + * related to, arising under or in connection with these + * materials, including for any direct, or any indirect, + * special, incidental, or consequential loss or damage + * (including loss of data, profits, goodwill, or any type of + * loss or damage suffered as a result of any action brought + * by a third party) even if such damage or loss was + * reasonably foreseeable or Xilinx had been advised of the + * possibility of the same. + * + * CRITICAL APPLICATIONS + * Xilinx products are not designed or intended to be fail- + * safe, or for use in any application requiring fail-safe + * performance, such as life-support or safety devices or + * systems, Class III medical devices, nuclear facilities, + * applications related to the deployment of airbags, or any + * other applications that could lead to death, personal + * injury, or severe property or environmental damage + * (individually and collectively, "Critical + * Applications"). Customer assumes the sole risk and + * liability of any use of Xilinx products in Critical + * Applications, subject only to applicable laws and + * regulations governing limitations on product liability. + * + * THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS + * PART OF THIS FILE AT ALL TIMES. + * + ******************************************************************************* + ******************************************************************************* + * + * Filename : DIST_MEM_GEN_V5_1.v + * + * Author : Xilinx + * + * Description : Distributed Memory Simulation Model + * + ******************************************************************************* + */ + +`timescale 1ps/1ps +`ifndef TCQ + `define TCQ 100 +`endif + +`define all0s {C_WIDTH{1'b0}} +`define allXs {C_WIDTH{1'bx}} +`define c_rom 0 +`define c_sp_ram 1 +`define c_dp_ram 2 +`define c_srl16 3 +`define c_sdp_ram 4 + +module DIST_MEM_GEN_V5_1 (A, D, DPRA, SPRA, CLK, WE, I_CE, QSPO_CE, QDPO_CE, QDPO_CLK, QSPO_RST, QDPO_RST, QSPO_SRST, QDPO_SRST, SPO, DPO, QSPO, QDPO); + + parameter C_FAMILY = "virtex5"; + parameter C_ADDR_WIDTH = 6; + parameter C_DEFAULT_DATA = "0"; + parameter C_DEPTH = 64; + parameter C_HAS_CLK = 1; + parameter C_HAS_D = 1; + parameter C_HAS_DPO = 0; + parameter C_HAS_DPRA = 0; + parameter C_HAS_I_CE = 0; + parameter C_HAS_QDPO = 0; + parameter C_HAS_QDPO_CE = 0; + parameter C_HAS_QDPO_CLK = 0; + parameter C_HAS_QDPO_RST = 0; + parameter C_HAS_QDPO_SRST = 0; + parameter C_HAS_QSPO = 0; + parameter C_HAS_QSPO_CE = 0; + parameter C_HAS_QSPO_RST = 0; + parameter C_HAS_QSPO_SRST = 0; + parameter C_HAS_SPO = 1; + parameter C_HAS_SPRA = 0; + parameter C_HAS_WE = 1; + parameter C_MEM_INIT_FILE = "null.mif"; + parameter C_MEM_TYPE = 1; + parameter C_PIPELINE_STAGES = 0; + parameter C_QCE_JOINED = 0; + parameter C_QUALIFY_WE = 0; + parameter C_READ_MIF = 0; + parameter C_REG_A_D_INPUTS = 0; + parameter C_REG_DPRA_INPUT = 0; + parameter C_SYNC_ENABLE = 0; + parameter C_WIDTH = 16; + parameter C_PARSER_TYPE = 1; + + input [C_ADDR_WIDTH-1 - (C_ADDR_WIDTH>4?(4*C_HAS_SPRA):0) : 0] A; + input [C_WIDTH-1 : 0] D; + input [C_ADDR_WIDTH-1 : 0] DPRA; + input [C_ADDR_WIDTH-1 : 0] SPRA; + input CLK; + input WE; + input I_CE; + input QSPO_CE; + input QDPO_CE; + input QDPO_CLK; + input QSPO_RST; + input QDPO_RST; + input QSPO_SRST; + input QDPO_SRST; + output [C_WIDTH-1 : 0] SPO; + output [C_WIDTH-1 : 0] QSPO; + output [C_WIDTH-1 : 0] DPO; + output [C_WIDTH-1 : 0] QDPO; + + // Address signal connected to memory + wire [C_ADDR_WIDTH - 1 : 0] a_int; + + // Read Address connected to srl16 memory + wire [C_ADDR_WIDTH - 1 : 0] spra_int; + + // Input data signal connected to memory + wire [C_WIDTH - 1 : 0] d_int; + + // Internal Write Enable + wire we_int; + + // Internal QSPO Clock Enable + wire qspo_ce_int; + + // Internal QDPO Clock + wire qdpo_clk_int; + + // Internal Dual Port Read Address connected to memory + wire [C_ADDR_WIDTH - 1 : 0] dpra_int; + + // Internal QDPO Clock Enable + wire qdpo_ce_int; + + // Registered Write Enable + reg we_reg; + + // Registered Address connected to memory + reg [C_ADDR_WIDTH - 1 : 0] a_reg; + + // Registered Read Address connected to srl16 memory + reg [C_ADDR_WIDTH - 1 : 0] spra_reg; + + // Registered data signal connected to memory + reg [C_WIDTH-1 : 0] d_reg; + + // Registered QSPO Clock Enable + reg qspo_ce_reg; + + // Registered Dual Port Read Address connected to memory + reg [C_ADDR_WIDTH - 1 : 0] dpra_reg; + + // Registered QDPO Clock Enable + reg qdpo_ce_reg; + + // Internal Single Port RAM output signal + wire [C_WIDTH - 1 : 0] spo_int; + + // Internal Dual Port RAM output signal + wire [C_WIDTH - 1 : 0] dpo_int; + + // Internal ROM/Single Port RAM/SRL16 RAM + // registered output + reg [C_WIDTH - 1 : 0] qspo_int; + + // Pipeline registers + reg [C_WIDTH - 1 : 0] qspo_pipe; + + // Internal Dual Port RAM registered output + reg [C_WIDTH - 1 : 0] qdpo_int; + + // Pipeline registers + reg [C_WIDTH - 1 : 0] qdpo_pipe; + + reg [C_WIDTH-1 : 0] ram_data [(2**C_ADDR_WIDTH)-1 : 0]; + reg [C_WIDTH-1 : 0] ram_data_tmp[C_DEPTH-1 : 0]; + + + reg [C_WIDTH-1 : 0] default_data; + + wire [C_WIDTH-1 : 0] data_sp; + wire [C_WIDTH-1 : 0] data_dp; + wire [C_WIDTH-1 : 0] data_srl; + + wire [C_WIDTH-1 : 0] data_sp_over; + wire [C_WIDTH-1 : 0] data_dp_over; + wire [C_WIDTH-1 : 0] data_srl_over; + + wire [C_ADDR_WIDTH - 1 : 0] a_over; + wire [C_ADDR_WIDTH - 1 : 0] dpra_over; + wire [C_ADDR_WIDTH - 1 : 0] spra_over; + + wire a_is_over; + wire dpra_is_over; + wire spra_is_over; + + reg [C_ADDR_WIDTH-1 : 0] max_address; + + integer i; + integer j; + integer srl_start; + integer srl_end; + + + // Initial block - initialise the memory, + // and when appropriate write content into the given address. + initial + begin + $display("WARNING: This core is supplied with a behavioral model. To model cycle-accurate behavior you must run timing simulation."); + + + default_data = 'b0; + default_data = binstr_conv(C_DEFAULT_DATA); + + // Assign that C_DEFAULT_DATA to each address in the memory. + for (i = 0; i < C_DEPTH; i = i + 1) + begin + ram_data[i] = default_data; + ram_data_tmp[i] = default_data; + end + + //Read the MIF file, and use it to initialise the content of ram_data + //if that is required. + if (C_READ_MIF) + begin + $readmemb(C_MEM_INIT_FILE, ram_data_tmp, 0, C_DEPTH-1); + + for (i = 0; i < C_DEPTH; i = i + 1) + ram_data[i] = ram_data_tmp[i]; + + end + + if (C_DEPTH != (2**C_ADDR_WIDTH)) + begin + for (i = C_DEPTH; i < (2**C_ADDR_WIDTH); i = i + 1) + ram_data[i] = 'b0; + end + + a_reg = 'b0; + we_reg = 1'b0; + spra_reg = 'b0; + d_reg = 'b0; + qspo_ce_reg = 1'b0; + dpra_reg = 'b0; + qdpo_ce_reg = 1'b0; + + qspo_int = default_data; + qspo_pipe = 'b0; + qdpo_int = default_data; + qdpo_pipe = 'b0; + + max_address = C_DEPTH-1; + + srl_start = 0; + srl_end = 15; + + end // initial begin + + // Now look for writes to the memory (note that this means the + // memory is not a ROM and that the Write Enable WE is active. + always@(posedge CLK) + begin + if (C_MEM_TYPE != `c_rom && we_int) + begin + if (C_MEM_TYPE == `c_srl16) + begin + if (C_ADDR_WIDTH > 4) + begin + srl_start = a_int * 16; + if (srl_start + 16 > C_DEPTH) + srl_end = C_DEPTH - 1; + else + srl_end = (a_int*16) + 15; + end + else + begin + srl_start = 0; + srl_end = 15; + end + + for (i = srl_end; i > srl_start; i = i - 1) + ram_data[i] <= #`TCQ ram_data[i-1]; + + ram_data[srl_start] <= #`TCQ d_int; + end + else if (a_is_over) + begin + $display("WARNING in %m at time %d ns", $time); + $write("Writing to out of range address. "); + $display("Max address in %m is %d", C_DEPTH-1); + $display("Write will be ignored."); + end + else + ram_data[a_int] <= #`TCQ d_int; + end // if (C_MEM_TYPE != `c_rom && we_int) + end // always@ (posedge CLK) + + // Model optional input registers, which operate in the CLK clock domain. + always @(posedge CLK) + begin + if (C_MEM_TYPE == 0) begin // ROM + if (C_HAS_QSPO_CE == 1) begin + if (QSPO_CE == 1) + a_reg <= #`TCQ A; + end else + a_reg <= #`TCQ A; + end else if (!C_HAS_I_CE) + begin + we_reg <= #`TCQ WE; + a_reg <= #`TCQ A; + spra_reg <= #`TCQ SPRA; + d_reg <= #`TCQ D; + end + else if (!C_QUALIFY_WE) + begin + we_reg <= #`TCQ WE; + if (I_CE) + begin + a_reg <= #`TCQ A; + spra_reg <= #`TCQ SPRA; + d_reg <= #`TCQ D; + end + end + else if (C_QUALIFY_WE) + if (I_CE) + begin + we_reg <= #`TCQ WE; + a_reg <= #`TCQ A; + spra_reg <= #`TCQ SPRA; + d_reg <= #`TCQ D; + end + + qspo_ce_reg <= #`TCQ QSPO_CE; + end // always @ (posedge CLK) + + + assign we_int = (C_HAS_WE ? (C_REG_A_D_INPUTS ? we_reg : WE) : 1'b0); + assign d_int = (C_MEM_TYPE > 0 ? (C_REG_A_D_INPUTS ? d_reg : D) : 'b0); + assign a_int = (C_REG_A_D_INPUTS ? a_reg : A); + + assign spra_int = (C_MEM_TYPE == `c_srl16 ? (C_REG_A_D_INPUTS ? spra_reg : SPRA) : 'b0); + assign qspo_ce_int = (C_HAS_QSPO_CE ? (C_REG_A_D_INPUTS ? qspo_ce_reg : QSPO_CE) : 1'b0); + + assign qdpo_clk_int = (((C_MEM_TYPE == `c_dp_ram) || (C_MEM_TYPE == `c_sdp_ram)) ? + (C_HAS_QDPO_CLK == 1 ? QDPO_CLK : CLK) : 1'b0); + + always@(posedge qdpo_clk_int) + begin + if (C_QCE_JOINED) + begin + if (!C_HAS_QSPO_CE) + dpra_reg <= #`TCQ DPRA; + else if (QSPO_CE) + dpra_reg <= #`TCQ DPRA; + end + else + begin + if (!C_HAS_QDPO_CE) + dpra_reg <= #`TCQ DPRA; + else if (QDPO_CE) + dpra_reg <= #`TCQ DPRA; + end // else: !if(C_QCE_JOINED) + + qdpo_ce_reg <= #`TCQ QDPO_CE; + + end // always@ (posedge qdpo_clk_int) + + assign dpra_int = (((C_MEM_TYPE == `c_dp_ram) || (C_MEM_TYPE == `c_sdp_ram)) ? + (C_REG_DPRA_INPUT == 1 ? dpra_reg : DPRA) : 1'b0); + + assign qdpo_ce_int = (((C_MEM_TYPE == `c_dp_ram) || (C_MEM_TYPE == `c_sdp_ram)) ? + (C_HAS_QDPO_CE ? (C_REG_DPRA_INPUT ? qdpo_ce_reg : QDPO_CE) : 1'b0) : 1'b0); + + always@(posedge spra_is_over) + begin + if (C_MEM_TYPE == `c_srl16) + begin + $display("WARNING in %m at time %d ns: ", $time); + $write("Reading from out-of-range address. "); + $display("Max address in %m is %d", C_DEPTH-1); + end // if (C_MEM_TYPE == `c_srl16) + end // always@ (spra_int or CLK) + + always@(posedge a_is_over) + begin + if (C_MEM_TYPE != `c_srl16) + begin + $display("WARNING in %m at time %d ns: ", $time); + $write("Reading from out-of-range address. "); + $display("Max address in %m is %d", C_DEPTH-1); + end // if (C_MEM_TYPE != `c_srl16) + end // always@ (a_int or posedge CLK) + + assign SPO = (C_HAS_SPO ? spo_int : `allXs); + + always@(posedge dpra_is_over) + begin + if ((C_MEM_TYPE == `c_dp_ram) || (C_MEM_TYPE == `c_sdp_ram)) + begin + $display("WARNING in %m at time %d ns: ", $time); + $write("Reading from out-of-range address. "); + $display("Max address in %m is %d", C_DEPTH-1); + end // if (C_MEM_TYPE == `c_dp_ram) + end // always@ (dpra_int) + + assign spo_int = (C_MEM_TYPE == `c_srl16 ? (spra_is_over ? data_srl_over : data_srl) : + (a_is_over ? data_sp_over : data_sp)); + + assign dpo_int = (((C_MEM_TYPE == `c_dp_ram) || (C_MEM_TYPE == `c_sdp_ram)) ? (dpra_is_over ? data_dp_over : data_dp) : `allXs); + + assign data_sp = ram_data[a_int]; + assign data_dp = ram_data[dpra_int]; + assign data_srl = ram_data[spra_int]; + + assign a_is_over = (a_int > max_address ? 1'b1 : 1'b0); + assign dpra_is_over = (dpra_int > max_address ? 1'b1 : 1'b0); + assign spra_is_over = (spra_int > max_address ? 1'b1 : 1'b0); + + assign a_over = a_int & max_address; + assign dpra_over = dpra_int & max_address; + assign spra_over = spra_int & max_address; + + assign data_sp_over = 'bx; + assign data_dp_over = 'bx; + assign data_srl_over = 'bx; + + assign DPO = (C_HAS_DPO ? dpo_int : `allXs); + + always@(posedge CLK or posedge QSPO_RST) + begin + if (C_HAS_QSPO_RST && QSPO_RST) + begin + qspo_pipe <= 'b0; + qspo_int <= 'b0; + end + else if (C_HAS_QSPO_SRST && QSPO_SRST) + begin + if (!C_HAS_QSPO_CE) + begin + qspo_pipe <= #`TCQ 'b0; + qspo_int <= #`TCQ 'b0; + end + else if (!C_SYNC_ENABLE) + begin + qspo_pipe <= #`TCQ 'b0; + qspo_int <= #`TCQ 'b0; + end + else if (C_HAS_QSPO_CE && qspo_ce_int) + begin + qspo_pipe <= #`TCQ 'b0; + qspo_int <= #`TCQ 'b0; + end + end // if (C_HAS_QSPO_SRST && QSPO_SRST) + + else if (C_HAS_QSPO_CE && qspo_ce_int) + begin + if (C_PIPELINE_STAGES == 1) + begin + qspo_int <= #`TCQ qspo_pipe; + end + else + begin + qspo_int <= #`TCQ spo_int; + end + qspo_pipe <= #`TCQ spo_int; + end + else if (!C_HAS_QSPO_CE) + begin + if (C_PIPELINE_STAGES == 1) + begin + qspo_int <= #`TCQ qspo_pipe; + end + else + begin + qspo_int <= #`TCQ spo_int; + end + qspo_pipe <= #`TCQ spo_int; + end // if (!C_HAS_QSPO_CE) + end // always@ (posedge CLK or QSPO_RST) + + assign QSPO = (C_HAS_QSPO == 1 ? qspo_int : `allXs); + + always@(posedge qdpo_clk_int or posedge QDPO_RST) + begin + if (C_HAS_QDPO_RST && QDPO_RST) + begin + qdpo_pipe <= 'b0; + qdpo_int <= 'b0; + end + else if (C_HAS_QDPO_SRST && QDPO_SRST) + begin + if (!C_SYNC_ENABLE) + begin + qdpo_pipe <= #`TCQ 'b0; + qdpo_int <= #`TCQ 'b0; + end + else if (!C_QCE_JOINED) + begin + if (!C_HAS_QDPO_CE) + begin + qdpo_pipe <= #`TCQ 'b0; + qdpo_int <= #`TCQ 'b0; + end + else if (C_HAS_QDPO_CE && qdpo_ce_int) + begin + qdpo_pipe <= #`TCQ 'b0; + qdpo_int <= #`TCQ 'b0; + end + end + else + begin + if (!C_HAS_QSPO_CE) + begin + qdpo_pipe <= #`TCQ 'b0; + qdpo_int <= #`TCQ 'b0; + end + else if (C_HAS_QSPO_CE && qspo_ce_int) + begin + qdpo_pipe <= #`TCQ 'b0; + qdpo_int <= #`TCQ 'b0; + end + end + end // if (C_HAS_QDPO_SRST && QDPO_SRST) + + else if (!C_QCE_JOINED) + begin + if (!C_HAS_QDPO_CE) + begin + qdpo_pipe <= #`TCQ dpo_int; + if (C_PIPELINE_STAGES == 1) + begin + qdpo_int <= #`TCQ qdpo_pipe; + end + else + begin + qdpo_int <= #`TCQ dpo_int; + end + end // if (!C_HAS_QDPO_CE) + else if (C_HAS_QDPO_CE && qdpo_ce_int) + begin + qdpo_pipe <= #`TCQ dpo_int; + if (C_PIPELINE_STAGES == 1) + begin + qdpo_int <= #`TCQ qdpo_pipe; + end + else + begin + qdpo_int <= #`TCQ dpo_int; + end + end // if (C_HAS_QDPO_CE && qdpo_ce_int) + end // if (!C_QCE_JOINED) + else if (C_QCE_JOINED) + begin + if (C_HAS_QSPO_CE && qspo_ce_int) + begin + qdpo_pipe <= #`TCQ dpo_int; + if (C_PIPELINE_STAGES == 1) + begin + qdpo_int <= #`TCQ qdpo_pipe; + end + else + begin + qdpo_int <= #`TCQ dpo_int; + end + end // if (C_HAS_QSPO_CE && qspo_ce_int) + else if (!C_HAS_QSPO_CE) + begin + qdpo_pipe <= #`TCQ dpo_int; + if (C_PIPELINE_STAGES == 1) + begin + qdpo_int <= #`TCQ qdpo_pipe; + end + else + begin + qdpo_int <= #`TCQ dpo_int; + end + end // if (!C_HAS_QSPO_CE) + end // if (C_QCE_JOINED) + end // always@ (posedge qdpo_clk_int or posedge QDPO_RST) + + assign QDPO = (C_HAS_QDPO == 1 ? qdpo_int : `allXs); + + function [C_WIDTH - 1 : 0] binstr_conv; + input [(C_WIDTH * 8) - 1 : 0] def_data; + integer index,i; + begin + index = 0; + binstr_conv = 'b0; + + for (i=C_WIDTH-1; i>=0; i=i-1) + begin + case (def_data[7:0]) + 8'b00000000 : i = -1; + 8'b00110000 : binstr_conv[index] = 1'b0; + 8'b00110001 : binstr_conv[index] = 1'b1; + default : + begin + $display("ERROR in %m at time %d ns: NOT A BINARY CHARACTER", $time); + binstr_conv[index] = 1'bx; + end + endcase // case(def_data[7:0]) + + index = index + 1; + def_data = def_data >> 8; + end // for (i=C_WIDTH-1; i>=0; i=i-1) + + end + endfunction // binstr_conv + +endmodule // DIST_MEM_GEN_V5_1 + +`undef all0s +`undef allXs +`undef c_rom +`undef c_sp_ram +`undef c_dp_ram +`undef c_srl16 +`undef c_sdp_ram diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/DIST_MEM_GEN_V5_1_XST.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/DIST_MEM_GEN_V5_1_XST.v new file mode 100644 index 0000000..9d0e8ed --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/DIST_MEM_GEN_V5_1_XST.v @@ -0,0 +1,174 @@ +/* + ******************************************************************************* + * + * (c) Copyright 1995 - 2009 Xilinx, Inc. All rights reserved. + * + * This file contains confidential and proprietary information + * of Xilinx, Inc. and is protected under U.S. and + * international copyright and other intellectual property + * laws. + * + * DISCLAIMER + * This disclaimer is not a license and does not grant any + * rights to the materials distributed herewith. Except as + * otherwise provided in a valid license issued to you by + * Xilinx, and to the maximum extent permitted by applicable + * law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND + * WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES + * AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING + * BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- + * INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and + * (2) Xilinx shall not be liable (whether in contract or tort, + * including negligence, or under any other theory of + * liability) for any loss or damage of any kind or nature + * related to, arising under or in connection with these + * materials, including for any direct, or any indirect, + * special, incidental, or consequential loss or damage + * (including loss of data, profits, goodwill, or any type of + * loss or damage suffered as a result of any action brought + * by a third party) even if such damage or loss was + * reasonably foreseeable or Xilinx had been advised of the + * possibility of the same. + * + * CRITICAL APPLICATIONS + * Xilinx products are not designed or intended to be fail- + * safe, or for use in any application requiring fail-safe + * performance, such as life-support or safety devices or + * systems, Class III medical devices, nuclear facilities, + * applications related to the deployment of airbags, or any + * other applications that could lead to death, personal + * injury, or severe property or environmental damage + * (individually and collectively, "Critical + * Applications"). Customer assumes the sole risk and + * liability of any use of Xilinx products in Critical + * Applications, subject only to applicable laws and + * regulations governing limitations on product liability. + * + * THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS + * PART OF THIS FILE AT ALL TIMES. + * + ******************************************************************************* + ******************************************************************************* + */ + + +`timescale 1ps/1ps + +module DIST_MEM_GEN_V5_1_XST +#( + parameter C_FAMILY = "virtex5", + parameter C_ADDR_WIDTH = 6, + parameter C_DEFAULT_DATA = "0", + parameter C_DEPTH = 64, + parameter C_HAS_CLK = 1, + parameter C_HAS_D = 1, + parameter C_HAS_DPO = 0, + parameter C_HAS_DPRA = 0, + parameter C_HAS_I_CE = 0, + parameter C_HAS_QDPO = 0, + parameter C_HAS_QDPO_CE = 0, + parameter C_HAS_QDPO_CLK = 0, + parameter C_HAS_QDPO_RST = 0, + parameter C_HAS_QDPO_SRST = 0, + parameter C_HAS_QSPO = 0, + parameter C_HAS_QSPO_CE = 0, + parameter C_HAS_QSPO_RST = 0, + parameter C_HAS_QSPO_SRST = 0, + parameter C_HAS_SPO = 1, + parameter C_HAS_SPRA = 0, + parameter C_HAS_WE = 1, + parameter C_MEM_INIT_FILE = "null.mif", + parameter C_ELABORATION_DIR = "./", + parameter C_MEM_TYPE = 1, + parameter C_PIPELINE_STAGES = 0, + parameter C_QCE_JOINED = 0, + parameter C_QUALIFY_WE = 0, + parameter C_READ_MIF = 0, + parameter C_REG_A_D_INPUTS = 0, + parameter C_REG_DPRA_INPUT = 0, + parameter C_SYNC_ENABLE = 0, + parameter C_WIDTH = 16, + parameter C_PARSER_TYPE = 1 +) +( + input [C_ADDR_WIDTH-1 - (C_ADDR_WIDTH>4?(4*C_HAS_SPRA):0) : 0] A, + input [C_WIDTH-1 : 0] D, + input [C_ADDR_WIDTH-1 : 0] DPRA, + input [C_ADDR_WIDTH-1 : 0] SPRA, + input CLK, + input WE, + input I_CE, + input QSPO_CE, + input QDPO_CE, + input QDPO_CLK, + input QSPO_RST, + input QDPO_RST, + input QSPO_SRST, + input QDPO_SRST, + output [C_WIDTH-1 : 0] SPO, + output [C_WIDTH-1 : 0] QSPO, + output [C_WIDTH-1 : 0] DPO, + output [C_WIDTH-1 : 0] QDPO +); + + DIST_MEM_GEN_V5_1 + #( + .C_FAMILY (C_FAMILY), + .C_ADDR_WIDTH (C_ADDR_WIDTH), + .C_DEFAULT_DATA (C_DEFAULT_DATA), + .C_DEPTH (C_DEPTH), + .C_HAS_CLK (C_HAS_CLK), + .C_HAS_D (C_HAS_D), + .C_HAS_DPO (C_HAS_DPO), + .C_HAS_DPRA (C_HAS_DPRA), + .C_HAS_I_CE (C_HAS_I_CE), + .C_HAS_QDPO (C_HAS_QDPO), + .C_HAS_QDPO_CE (C_HAS_QDPO_CE), + .C_HAS_QDPO_CLK (C_HAS_QDPO_CLK), + .C_HAS_QDPO_RST (C_HAS_QDPO_RST), + .C_HAS_QDPO_SRST (C_HAS_QDPO_SRST), + .C_HAS_QSPO (C_HAS_QSPO), + .C_HAS_QSPO_CE (C_HAS_QSPO_CE), + .C_HAS_QSPO_RST (C_HAS_QSPO_RST), + .C_HAS_QSPO_SRST (C_HAS_QSPO_SRST), + .C_HAS_SPO (C_HAS_SPO), + .C_HAS_SPRA (C_HAS_SPRA), + .C_HAS_WE (C_HAS_WE), + .C_MEM_INIT_FILE (C_MEM_INIT_FILE), + .C_ELABORATION_DIR (C_ELABORATION_DIR), + .C_MEM_TYPE (C_MEM_TYPE), + .C_PIPELINE_STAGES (C_PIPELINE_STAGES), + .C_QCE_JOINED (C_QCE_JOINED), + .C_QUALIFY_WE (C_QUALIFY_WE), + .C_READ_MIF (C_READ_MIF), + .C_REG_A_D_INPUTS (C_REG_A_D_INPUTS), + .C_REG_DPRA_INPUT (C_REG_DPRA_INPUT), + .C_SYNC_ENABLE (C_SYNC_ENABLE), + .C_WIDTH (C_WIDTH), + .C_PARSER_TYPE (C_PARSER_TYPE) + ) dist_mem_gen_v5_1_dut + ( + .A (A), + .D (D), + .DPRA (DPRA), + .SPRA (SPRA), + .CLK (CLK), + .WE (WR), + .I_CE (I_CE), + .QSPO_CE (QSPO_CE), + .QDPO_CE (QDPO_CE), + .QDPO_CLK (QDPO_CLK), + .QSPO_RST (QSPO_RST), + .QDPO_RST (QDPO_RST), + .QSPO_SRST (QSPO_SRST ), + .QDPO_SRST (QDPO_SRS), + .SPO (SPO), + .DPO (DPO), + .QSPO (QSPO), + .QDPO (QDPO) + ); + +endmodule + + + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/FAMILY.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/FAMILY.v new file mode 100644 index 0000000..7e33b79 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/FAMILY.v @@ -0,0 +1,270 @@ +/* $Header: /devl/xcs/repo/env/Databases/ip/src/com/xilinx/ip/unisim/simulation/FAMILY.v,v 1.19 2008/09/08 20:10:25 akennedy Exp $ +-- +-- Description - +*/ + +`define any "any" +`define x4k "x4k" +`define x4ke "x4ke" +`define x4kl "x4kl" +`define x4kex "x4kex" +`define x4kxl "x4kxl" +`define x4kxv "x4kxv" +`define x4kxla "x4kxla" +`define spartan "spartan" +`define spartanxl "spartanxl" +`define spartan2 "spartan2" +`define spartan2e "spartan2e" +`define virtex "virtex" +`define virtexe "virtexe" +`define virtex2 "virtex2" +`define virtex2p "virtex2p" +`define spartan3 "spartan3" +`define spartan3a "spartan3a" +`define spartan3adsp "spartan3adsp" +`define spartan3e "spartan3e" +`define aspartan3e "aspartan3e" +`define aspartan3 "aspartan3" +`define virtex4 "virtex4" +`define virtex5 "virtex5" +`define qrvirtex "qrvirtex" +`define qrvirtex2 "qrvirtex2" +`define qvirtex "qvirtex" +`define qvirtex2 "qvirtex2" +`define qvirtexe "qvirtexe" + +module family ( ); + +/* + * True if architecture "child" is derived from, or equal to, + * the architecture "ancestor". + * ANY, X4K, SPARTAN, SPARTANXL + * ANY, X4K, X4KE, X4KL + * ANY, X4K, X4KEX, X4KXL, X4KXV, X4KXLA + * ANY, VIRTEX, SPARTAN2, SPARTAN2E + * ANY, VIRTEX, VIRTEXE + * ANY, VIRTEX, VIRTEX2, SPARTAN3, ASPARTAN3E + * ANY, VIRTEX, VIRTEX2, SPARTAN3, SPARTAN3A, SPARTAN3ADSP + * ANY, VIRTEX, VIRTEX2, SPARTAN3, ASPARTAN3 + * ANY, VIRTEX, VIRTEX2, VIRTEX2P + * ANY, VIRTEX, VIRTEX5 + * ANY, VIRTEX, VIRTEX4 + * ANY, VIRTEX, QRVIRTEX + * ANY, VIRTEX, VIRTEX2, QRVIRTEX2 + * ANY, VIRTEX, QVIRTEX + * ANY, VIRTEX, VIRTEX2, QVIRTEX2 + * ANY, VIRTEX, QVIRTEX + */ + +function derived; + input [9*8:1] child; + input [9*8:1] ancestor; + begin + derived = 0; + if ( child == `virtex ) + begin + if ( ancestor == `virtex || ancestor == `any ) + begin + derived = 1; + end + end + else if ( child == `qvirtexe ) + begin + if ( ancestor == `qvirtexe || ancestor == `virtex || ancestor == `any ) + begin + derived = 1; + end + end + else if ( child == `qvirtex2 ) + begin + if ( ancestor == `qvirtex2 || ancestor == `virtex2 || ancestor == `virtex || ancestor == `any ) + begin + derived = 1; + end + end + else if ( child == `qvirtex ) + begin + if ( ancestor == `qvirtex || ancestor == `virtex || ancestor == `any ) + begin + derived = 1; + end + end + else if ( child == `qrvirtex2 ) + begin + if ( ancestor == `qrvirtex2 || ancestor == `virtex2 || ancestor == `virtex || ancestor == `any ) + begin + derived = 1; + end + end + else if ( child == `qrvirtex ) + begin + if ( ancestor == `qrvirtex || ancestor == `virtex || ancestor == `any ) + begin + derived = 1; + end + end + else if ( child == `virtex5 ) + begin + if ( ancestor == `virtex5 || ancestor == `virtex || ancestor == `any ) + begin + derived = 1; + end + end + else if ( child == `virtex4 ) + begin + if ( ancestor == `virtex4 || ancestor == `virtex || ancestor == `any ) + begin + derived = 1; + end + end + else if ( child == `virtex2 ) + begin + if ( ancestor == `virtex2 || ancestor == `virtex || ancestor == `any ) + begin + derived = 1; + end + end + else if ( child == `virtex2p ) + begin + if ( ancestor == `virtex2p || ancestor == `virtex2 || ancestor == `virtex || ancestor == `any ) + begin + derived = 1; + end + end + else if ( child == `spartan3e ) + begin + if ( ancestor == `spartan3e || ancestor == `spartan3 || ancestor == `virtex2 || ancestor == `virtex || ancestor == `any ) + begin + derived = 1; + end + end + else if ( child == `aspartan3e ) + begin + if ( ancestor == `aspartan3e || ancestor == `spartan3e || ancestor == `spartan3 || ancestor == `virtex2 || ancestor == `virtex || ancestor == `any ) + begin + derived = 1; + end + end + else if ( child == `spartan3a ) + begin + if ( ancestor == `spartan3a || ancestor == `spartan3 || ancestor == `virtex2 || ancestor == `virtex || ancestor == `any ) + begin + derived = 1; + end + end + else if ( child == `spartan3adsp ) + begin + if ( ancestor == `spartan3adsp || ancestor == `spartan3a || ancestor == `spartan3 || ancestor == `virtex2 || ancestor == `virtex || ancestor == `any ) + begin + derived = 1; + end + end + else if ( child == `aspartan3 ) + begin + if ( ancestor == `aspartan3 || ancestor == `spartan3 || ancestor == `virtex2 || ancestor == `virtex || ancestor == `any ) + begin + derived = 1; + end + end + else if ( child == `spartan3 ) + begin + if ( ancestor == `spartan3 || ancestor == `virtex2 || ancestor == `virtex || ancestor == `any ) + begin + derived = 1; + end + end + else if ( child == `virtexe ) + begin + if ( ancestor == `virtexe || ancestor == `virtex || ancestor == `any ) + begin + derived = 1; + end + end + else if ( child == `spartan2 ) + begin + if ( ancestor == `spartan2 || ancestor == `virtex || ancestor == `any ) + begin + derived = 1; + end + end + else if ( child == `spartan2e ) + begin + if ( ancestor == `spartan2e || ancestor == `spartan2 || ancestor == `virtex || ancestor == `any ) + begin + derived = 1; + end + end + else if ( child == `x4k ) + begin + if ( ancestor == `x4k || ancestor == `any ) + begin + derived = 1; + end + end + else if ( child == `x4kex ) + begin + if ( ancestor == `x4kex || ancestor == `x4k || ancestor == `any ) + begin + derived = 1; + end + end + else if ( child == `x4kxl ) + begin + if ( ancestor == `x4kxl || ancestor == `x4kex || ancestor == `x4k || ancestor == `any ) + begin + derived = 1; + end + end + else if ( child == `x4kxv ) + begin + if ( ancestor == `x4kxv || ancestor == `x4kxl || ancestor == `x4kex || ancestor == `x4k || ancestor == `any ) + begin + derived = 1; + end + end + else if ( child == `x4kxla ) + begin + if ( ancestor == `x4kxla || ancestor == `x4kxv || ancestor == `x4kxl || ancestor == `x4kex || ancestor == `x4k || ancestor == `any ) + begin + derived = 1; + end + end + else if ( child == `x4ke ) + begin + if ( ancestor == `x4ke || ancestor == `x4k || ancestor == `any ) + begin + derived = 1; + end + end + else if ( child == `x4kl ) + begin + if ( ancestor == `x4kl || ancestor == `x4ke || ancestor == `x4k || ancestor == `any ) + begin + derived = 1; + end + end + else if ( child == `spartan ) + begin + if ( ancestor == `spartan || ancestor == `x4k || ancestor == `any ) + begin + derived = 1; + end + end + else if ( child == `spartanxl ) + begin + if ( ancestor == `spartanxl || ancestor == `spartan || ancestor == `x4k || ancestor == `any ) + begin + derived = 1; + end + end + else if ( child == `any ) + begin + if ( ancestor == `any ) + begin + derived = 1; + end + end + end +endfunction //my_func + +endmodule diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/FIFO_GENERATOR_V3_3.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/FIFO_GENERATOR_V3_3.v new file mode 100644 index 0000000..ae8f0c5 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/FIFO_GENERATOR_V3_3.v @@ -0,0 +1,3423 @@ +/* + * $RDCfile: $ $Revision: 1.7 $ $Date: 2008/09/09 19:56:58 $ + ******************************************************************************* + * + * FIFO Generator v3.3 - Verilog Behavioral Model + * + ******************************************************************************* + * + * Copyright(C) 2006 by Xilinx, Inc. All rights reserved. + * This text/file contains proprietary, confidential + * information of Xilinx, Inc., is distributed under + * license from Xilinx, Inc., and may be used, copied + * and/or disclosed only pursuant to the terms of a valid + * license agreement with Xilinx, Inc. Xilinx hereby + * grants you a license to use this text/file solely for + * design, simulation, implementation and creation of + * design files limited to Xilinx devices or technologies. + * Use with non-Xilinx devices or technologies is expressly + * prohibited and immediately terminates your license unless + * covered by a separate agreement. + * + * Xilinx is providing theis design, code, or information + * "as-is" solely for use in developing programs and + * solutions for Xilinx devices, with no obligation on the + * part of Xilinx to provide support. By providing this design, + * code, or information as one possible implementation of + * this feature, application or standard. Xilinx is making no + * representation that this implementation is free from any + * claims of infringement. You are responsible for obtaining + * any rights you may require for your implementation. + * Xilinx expressly disclaims any warranty whatsoever with + * respect to the adequacy of the implementation, including + * but not limited to any warranties or representations that this + * implementation is free from claims of infringement, implied + * warranties of merchantability or fitness for a particular + * purpose. + * + * Xilinx products are not intended for use in life support + * appliances, devices, or systems. Use in such applications is + * expressly prohibited. + * + * This copyright and support notice must be retained as part + * of this text at all times. (c)Copyright 1995-2006 Xilinx, Inc. + * All rights reserved. + * + ******************************************************************************* + * + * Filename: fifo_generator_v3_3_bhv.v + * + * Description: + * The verilog behavioral model for the FIFO generator core. + * + ******************************************************************************* + */ + +`timescale 1ps/1ps + +/******************************************************************************* + * Declaration of top-level module + ******************************************************************************/ +module FIFO_GENERATOR_V3_3 + ( + BACKUP, + BACKUP_MARKER, + CLK, + DIN, + PROG_EMPTY_THRESH, + PROG_EMPTY_THRESH_ASSERT, + PROG_EMPTY_THRESH_NEGATE, + PROG_FULL_THRESH, + PROG_FULL_THRESH_ASSERT, + PROG_FULL_THRESH_NEGATE, + RD_CLK, + RD_EN, + RD_RST, + RST, + //Added Synchronous Reset feature for v3.3 (IP2_Im) + SRST, + WR_CLK, + WR_EN, + WR_RST, + + ALMOST_EMPTY, + ALMOST_FULL, + DATA_COUNT, + DOUT, + EMPTY, + FULL, + OVERFLOW, + PROG_EMPTY, + PROG_FULL, + RD_DATA_COUNT, + UNDERFLOW, + VALID, + WR_ACK, + WR_DATA_COUNT, + SBITERR, + DBITERR + ); + +/****************************************************************************** + * Definition of Ports + * + * + ***************************************************************************** + * Definition of Parameters + * + * + *****************************************************************************/ + +/****************************************************************************** + * Declare user parameters and their defaults + *****************************************************************************/ + parameter C_COMMON_CLOCK = 0; + parameter C_COUNT_TYPE = 0; + parameter C_DATA_COUNT_WIDTH = 2; + parameter C_DEFAULT_VALUE = ""; + parameter C_DIN_WIDTH = 8; + parameter C_DOUT_RST_VAL = ""; + parameter C_DOUT_WIDTH = 8; + parameter C_ENABLE_RLOCS = 0; + parameter C_FAMILY = "virtex2"; //Not allowed in Verilog model + parameter C_HAS_ALMOST_EMPTY = 0; + parameter C_HAS_ALMOST_FULL = 0; + parameter C_HAS_BACKUP = 0; + parameter C_HAS_DATA_COUNT = 0; + parameter C_HAS_MEMINIT_FILE = 0; + parameter C_HAS_OVERFLOW = 0; + parameter C_HAS_RD_DATA_COUNT = 0; + parameter C_HAS_RD_RST = 0; + parameter C_HAS_RST = 0; + //Added Synchronous Reset feature for v3.2 (IP2_Im) + parameter C_HAS_SRST = 0; + parameter C_HAS_UNDERFLOW = 0; + parameter C_HAS_VALID = 0; + parameter C_HAS_WR_ACK = 0; + parameter C_HAS_WR_DATA_COUNT = 0; + parameter C_HAS_WR_RST = 0; + parameter C_IMPLEMENTATION_TYPE = 0; + parameter C_INIT_WR_PNTR_VAL = 0; + parameter C_MEMORY_TYPE = 1; + parameter C_MIF_FILE_NAME = ""; + parameter C_OPTIMIZATION_MODE = 0; + parameter C_OVERFLOW_LOW = 0; + parameter C_PRELOAD_LATENCY = 1; + parameter C_PRELOAD_REGS = 0; + parameter C_PRIM_FIFO_TYPE = 512; + parameter C_PROG_EMPTY_THRESH_ASSERT_VAL = 0; + parameter C_PROG_EMPTY_THRESH_NEGATE_VAL = 0; + parameter C_PROG_EMPTY_TYPE = 0; + parameter C_PROG_FULL_THRESH_ASSERT_VAL = 0; + parameter C_PROG_FULL_THRESH_NEGATE_VAL = 0; + parameter C_PROG_FULL_TYPE = 0; + parameter C_RD_DATA_COUNT_WIDTH = 2; + parameter C_RD_DEPTH = 256; + parameter C_RD_FREQ = 1; + parameter C_RD_PNTR_WIDTH = 8; + parameter C_UNDERFLOW_LOW = 0; + parameter C_USE_FIFO16_FLAGS = 0; + parameter C_VALID_LOW = 0; + parameter C_WR_ACK_LOW = 0; + parameter C_WR_DATA_COUNT_WIDTH = 2; + parameter C_WR_DEPTH = 256; + parameter C_WR_FREQ = 1; + parameter C_WR_PNTR_WIDTH = 8; + parameter C_WR_RESPONSE_LATENCY = 1; + parameter C_USE_ECC = 0; + + //There are 2 Verilog behavioral models + // 0 = Synchronous FIFO/ShiftRam FIFO + // 1 = Asynchronous FIFO + parameter C_VERILOG_IMPL = (C_IMPLEMENTATION_TYPE==0 ? 0 : + (C_IMPLEMENTATION_TYPE==1 ? 0 : + (C_IMPLEMENTATION_TYPE==2 ? 1 : 0))); + + + /****************************************************************************** + * Declare Input and Output Ports + *****************************************************************************/ + input CLK; + input BACKUP; + input BACKUP_MARKER; + input [C_DIN_WIDTH-1:0] DIN; + input [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH; + input [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_ASSERT; + input [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_NEGATE; + input [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH; + input [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_ASSERT; + input [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_NEGATE; + input RD_CLK; + input RD_EN; + input RD_RST; + input RST; + //Added Synchronous Reset feature for v3.2 (IP2_Im) + input SRST; + input WR_CLK; + input WR_EN; + input WR_RST; + + output ALMOST_EMPTY; + output ALMOST_FULL; + output [C_DATA_COUNT_WIDTH-1:0] DATA_COUNT; + output [C_DOUT_WIDTH-1:0] DOUT; + output EMPTY; + output FULL; + output OVERFLOW; + output PROG_EMPTY; + output PROG_FULL; + output VALID; + output [C_RD_DATA_COUNT_WIDTH-1:0] RD_DATA_COUNT; + output UNDERFLOW; + output WR_ACK; + output [C_WR_DATA_COUNT_WIDTH-1:0] WR_DATA_COUNT; + output SBITERR; + output DBITERR; + + + wire ALMOST_EMPTY; + wire ALMOST_FULL; + wire [C_DATA_COUNT_WIDTH-1:0] DATA_COUNT; + wire [C_DOUT_WIDTH-1:0] DOUT; + wire EMPTY; + wire FULL; + wire OVERFLOW; + wire PROG_EMPTY; + wire PROG_FULL; + wire VALID; + wire [C_RD_DATA_COUNT_WIDTH-1:0] RD_DATA_COUNT; + wire UNDERFLOW; + wire WR_ACK; + wire [C_WR_DATA_COUNT_WIDTH-1:0] WR_DATA_COUNT; + + + wire RD_CLK_P0_IN; + wire RST_P0_IN; + wire RD_EN_FIFO_IN; + wire RD_EN_P0_IN; + + wire ALMOST_EMPTY_FIFO_OUT; + wire ALMOST_FULL_FIFO_OUT; + wire [C_DATA_COUNT_WIDTH-1:0] DATA_COUNT_FIFO_OUT; + wire [C_DOUT_WIDTH-1:0] DOUT_FIFO_OUT; + wire EMPTY_FIFO_OUT; + wire FULL_FIFO_OUT; + wire OVERFLOW_FIFO_OUT; + wire PROG_EMPTY_FIFO_OUT; + wire PROG_FULL_FIFO_OUT; + wire VALID_FIFO_OUT; + wire [C_RD_DATA_COUNT_WIDTH-1:0] RD_DATA_COUNT_FIFO_OUT; + wire UNDERFLOW_FIFO_OUT; + wire WR_ACK_FIFO_OUT; + wire [C_WR_DATA_COUNT_WIDTH-1:0] WR_DATA_COUNT_FIFO_OUT; + + + //*************************************************************************** + // Internal Signals + // The core uses either the internal_ wires or the preload0_ wires depending + // on whether the core uses Preload0 or not. + // When using preload0, the internal signals connect the internal core to + // the preload logic, and the external core's interfaces are tied to the + // preload0 signals from the preload logic. + //*************************************************************************** + wire [C_DOUT_WIDTH-1:0] DATA_P0_OUT; + wire VALID_P0_OUT; + wire EMPTY_P0_OUT; + wire ALMOSTEMPTY_P0_OUT; + reg EMPTY_P0_OUT_Q; + reg ALMOSTEMPTY_P0_OUT_Q; + wire UNDERFLOW_P0_OUT; + wire RDEN_P0_OUT; + wire [C_DOUT_WIDTH-1:0] DATA_P0_IN; + wire EMPTY_P0_IN; + + assign SBITERR = 1'b0; + assign DBITERR = 1'b0; + +// choose the base FIFO implementation for simulation +generate +case (C_VERILOG_IMPL) +0 : begin : block1 + fifo_generator_v3_3_bhv_ver_ss + #( + C_COMMON_CLOCK, + C_COUNT_TYPE, + C_DATA_COUNT_WIDTH, + C_DEFAULT_VALUE, + C_DIN_WIDTH, + C_DOUT_RST_VAL, + C_DOUT_WIDTH, + C_ENABLE_RLOCS, + C_FAMILY,//Not allowed in Verilog model + C_HAS_ALMOST_EMPTY, + C_HAS_ALMOST_FULL, + C_HAS_BACKUP, + C_HAS_DATA_COUNT, + C_HAS_MEMINIT_FILE, + C_HAS_OVERFLOW, + C_HAS_RD_DATA_COUNT, + C_HAS_RD_RST, + C_HAS_RST, + //Added Synchronous Reset feature for v3.2 (IP2_Im) + C_HAS_SRST, + C_HAS_UNDERFLOW, + C_HAS_VALID, + C_HAS_WR_ACK, + C_HAS_WR_DATA_COUNT, + C_HAS_WR_RST, + C_IMPLEMENTATION_TYPE, + C_INIT_WR_PNTR_VAL, + C_MEMORY_TYPE, + C_MIF_FILE_NAME, + C_OPTIMIZATION_MODE, + C_OVERFLOW_LOW, + C_PRELOAD_LATENCY, + C_PRELOAD_REGS, + C_PROG_EMPTY_THRESH_ASSERT_VAL, + C_PROG_EMPTY_THRESH_NEGATE_VAL, + C_PROG_EMPTY_TYPE, + C_PROG_FULL_THRESH_ASSERT_VAL, + C_PROG_FULL_THRESH_NEGATE_VAL, + C_PROG_FULL_TYPE, + C_RD_DATA_COUNT_WIDTH, + C_RD_DEPTH, + C_RD_PNTR_WIDTH, + C_UNDERFLOW_LOW, + C_VALID_LOW, + C_WR_ACK_LOW, + C_WR_DATA_COUNT_WIDTH, + C_WR_DEPTH, + C_WR_PNTR_WIDTH, + C_WR_RESPONSE_LATENCY + ) + gen_ss + ( + .CLK (CLK), + .RST (RST), + //Added Synchronous Reset feature for v3.2 (IP2_Im) + .SRST (SRST), + .DIN (DIN), + .WR_EN (WR_EN), + .RD_EN (RD_EN_FIFO_IN), + .PROG_EMPTY_THRESH (PROG_EMPTY_THRESH), + .PROG_EMPTY_THRESH_ASSERT (PROG_EMPTY_THRESH_ASSERT), + .PROG_EMPTY_THRESH_NEGATE (PROG_EMPTY_THRESH_NEGATE), + .PROG_FULL_THRESH (PROG_FULL_THRESH), + .PROG_FULL_THRESH_ASSERT (PROG_FULL_THRESH_ASSERT), + .PROG_FULL_THRESH_NEGATE (PROG_FULL_THRESH_NEGATE), + .DOUT (DOUT_FIFO_OUT), + .FULL (FULL_FIFO_OUT), + .ALMOST_FULL (ALMOST_FULL_FIFO_OUT), + .WR_ACK (WR_ACK_FIFO_OUT), + .OVERFLOW (OVERFLOW_FIFO_OUT), + .EMPTY (EMPTY_FIFO_OUT), + .ALMOST_EMPTY (ALMOST_EMPTY_FIFO_OUT), + .VALID (VALID_FIFO_OUT), + .UNDERFLOW (UNDERFLOW_FIFO_OUT), + .DATA_COUNT (DATA_COUNT_FIFO_OUT), + .PROG_FULL (PROG_FULL_FIFO_OUT), + .PROG_EMPTY (PROG_EMPTY_FIFO_OUT) + ); +end +1 : begin : block1 + fifo_generator_v3_3_bhv_ver_as + #( + C_COMMON_CLOCK, + C_COUNT_TYPE, + C_DATA_COUNT_WIDTH, + C_DEFAULT_VALUE, + C_DIN_WIDTH, + C_DOUT_RST_VAL, + C_DOUT_WIDTH, + C_ENABLE_RLOCS, + C_FAMILY,//Not allowed in Verilog model + C_HAS_ALMOST_EMPTY, + C_HAS_ALMOST_FULL, + C_HAS_BACKUP, + C_HAS_DATA_COUNT, + C_HAS_MEMINIT_FILE, + C_HAS_OVERFLOW, + C_HAS_RD_DATA_COUNT, + C_HAS_RD_RST, + C_HAS_RST, + C_HAS_UNDERFLOW, + C_HAS_VALID, + C_HAS_WR_ACK, + C_HAS_WR_DATA_COUNT, + C_HAS_WR_RST, + C_IMPLEMENTATION_TYPE, + C_INIT_WR_PNTR_VAL, + C_MEMORY_TYPE, + C_MIF_FILE_NAME, + C_OPTIMIZATION_MODE, + C_OVERFLOW_LOW, + C_PRELOAD_LATENCY, + C_PRELOAD_REGS, + C_PROG_EMPTY_THRESH_ASSERT_VAL, + C_PROG_EMPTY_THRESH_NEGATE_VAL, + C_PROG_EMPTY_TYPE, + C_PROG_FULL_THRESH_ASSERT_VAL, + C_PROG_FULL_THRESH_NEGATE_VAL, + C_PROG_FULL_TYPE, + C_RD_DATA_COUNT_WIDTH, + C_RD_DEPTH, + C_RD_PNTR_WIDTH, + C_UNDERFLOW_LOW, + C_VALID_LOW, + C_WR_ACK_LOW, + C_WR_DATA_COUNT_WIDTH, + C_WR_DEPTH, + C_WR_PNTR_WIDTH, + C_WR_RESPONSE_LATENCY + ) + gen_as + ( + .WR_CLK (WR_CLK), + .RD_CLK (RD_CLK), + .RST (RST), + .DIN (DIN), + .WR_EN (WR_EN), + .RD_EN (RD_EN_FIFO_IN), + .PROG_EMPTY_THRESH (PROG_EMPTY_THRESH), + .PROG_EMPTY_THRESH_ASSERT (PROG_EMPTY_THRESH_ASSERT), + .PROG_EMPTY_THRESH_NEGATE (PROG_EMPTY_THRESH_NEGATE), + .PROG_FULL_THRESH (PROG_FULL_THRESH), + .PROG_FULL_THRESH_ASSERT (PROG_FULL_THRESH_ASSERT), + .PROG_FULL_THRESH_NEGATE (PROG_FULL_THRESH_NEGATE), + .DOUT (DOUT_FIFO_OUT), + .FULL (FULL_FIFO_OUT), + .ALMOST_FULL (ALMOST_FULL_FIFO_OUT), + .WR_ACK (WR_ACK_FIFO_OUT), + .OVERFLOW (OVERFLOW_FIFO_OUT), + .EMPTY (EMPTY_FIFO_OUT), + .ALMOST_EMPTY (ALMOST_EMPTY_FIFO_OUT), + .VALID (VALID_FIFO_OUT), + .UNDERFLOW (UNDERFLOW_FIFO_OUT), + .RD_DATA_COUNT (RD_DATA_COUNT_FIFO_OUT), + .WR_DATA_COUNT (WR_DATA_COUNT_FIFO_OUT), + .PROG_FULL (PROG_FULL_FIFO_OUT), + .PROG_EMPTY (PROG_EMPTY_FIFO_OUT) + ); +end + +default : begin : block1 + fifo_generator_v3_3_bhv_ver_as + #( + C_COMMON_CLOCK, + C_COUNT_TYPE, + C_DATA_COUNT_WIDTH, + C_DEFAULT_VALUE, + C_DIN_WIDTH, + C_DOUT_RST_VAL, + C_DOUT_WIDTH, + C_ENABLE_RLOCS, + C_FAMILY,//Not allowed in Verilog model + C_HAS_ALMOST_EMPTY, + C_HAS_ALMOST_FULL, + C_HAS_BACKUP, + C_HAS_DATA_COUNT, + C_HAS_MEMINIT_FILE, + C_HAS_OVERFLOW, + C_HAS_RD_DATA_COUNT, + C_HAS_RD_RST, + C_HAS_RST, + C_HAS_UNDERFLOW, + C_HAS_VALID, + C_HAS_WR_ACK, + C_HAS_WR_DATA_COUNT, + C_HAS_WR_RST, + C_IMPLEMENTATION_TYPE, + C_INIT_WR_PNTR_VAL, + C_MEMORY_TYPE, + C_MIF_FILE_NAME, + C_OPTIMIZATION_MODE, + C_OVERFLOW_LOW, + C_PRELOAD_LATENCY, + C_PRELOAD_REGS, + C_PROG_EMPTY_THRESH_ASSERT_VAL, + C_PROG_EMPTY_THRESH_NEGATE_VAL, + C_PROG_EMPTY_TYPE, + C_PROG_FULL_THRESH_ASSERT_VAL, + C_PROG_FULL_THRESH_NEGATE_VAL, + C_PROG_FULL_TYPE, + C_RD_DATA_COUNT_WIDTH, + C_RD_DEPTH, + C_RD_PNTR_WIDTH, + C_UNDERFLOW_LOW, + C_VALID_LOW, + C_WR_ACK_LOW, + C_WR_DATA_COUNT_WIDTH, + C_WR_DEPTH, + C_WR_PNTR_WIDTH, + C_WR_RESPONSE_LATENCY + ) + gen_as + ( + .WR_CLK (WR_CLK), + .RD_CLK (RD_CLK), + .RST (RST), + .DIN (DIN), + .WR_EN (WR_EN), + .RD_EN (RD_EN_FIFO_IN), + .PROG_EMPTY_THRESH (PROG_EMPTY_THRESH), + .PROG_EMPTY_THRESH_ASSERT (PROG_EMPTY_THRESH_ASSERT), + .PROG_EMPTY_THRESH_NEGATE (PROG_EMPTY_THRESH_NEGATE), + .PROG_FULL_THRESH (PROG_FULL_THRESH), + .PROG_FULL_THRESH_ASSERT (PROG_FULL_THRESH_ASSERT), + .PROG_FULL_THRESH_NEGATE (PROG_FULL_THRESH_NEGATE), + .DOUT (DOUT_FIFO_OUT), + .FULL (FULL_FIFO_OUT), + .ALMOST_FULL (ALMOST_FULL_FIFO_OUT), + .WR_ACK (WR_ACK_FIFO_OUT), + .OVERFLOW (OVERFLOW_FIFO_OUT), + .EMPTY (EMPTY_FIFO_OUT), + .ALMOST_EMPTY (ALMOST_EMPTY_FIFO_OUT), + .VALID (VALID_FIFO_OUT), + .UNDERFLOW (UNDERFLOW_FIFO_OUT), + .RD_DATA_COUNT (RD_DATA_COUNT_FIFO_OUT), + .WR_DATA_COUNT (WR_DATA_COUNT_FIFO_OUT), + .PROG_FULL (PROG_FULL_FIFO_OUT), + .PROG_EMPTY (PROG_EMPTY_FIFO_OUT) + ); +end + +endcase +endgenerate + + +//************************************************************************** +// Connect Internal Signals +// (Signals labeled internal_*) +// In the normal case, these signals tie directly to the FIFO's inputs and +// outputs. +// In the case of Preload Latency 0 or 1, there are intermediate +// signals between the internal FIFO and the preload logic. +//************************************************************************** + +generate +if (C_PRELOAD_REGS==1 && C_PRELOAD_LATENCY==0) + begin : block2 + +fifo_generator_v3_3_bhv_ver_preload0 + #( + C_DOUT_RST_VAL, + C_DOUT_WIDTH, + C_HAS_RST, + C_VALID_LOW, + C_UNDERFLOW_LOW + ) + fgpl0 +( + .RD_CLK (RD_CLK_P0_IN), + .RD_RST (RST_P0_IN), + .RD_EN (RD_EN_P0_IN), + .FIFOEMPTY (EMPTY_P0_IN), + .FIFODATA (DATA_P0_IN), + .USERDATA (DATA_P0_OUT), + .USERVALID (VALID_P0_OUT), + .USEREMPTY (EMPTY_P0_OUT), + .USERALMOSTEMPTY (ALMOSTEMPTY_P0_OUT), + .USERUNDERFLOW (UNDERFLOW_P0_OUT), + .RAMVALID (RAMVALID_P0_OUT), + .FIFORDEN (RDEN_P0_OUT) + ); + + assign RD_CLK_P0_IN = ((C_VERILOG_IMPL == 0) ? CLK : RD_CLK); + assign RST_P0_IN = RST; + assign RD_EN_P0_IN = RD_EN; + + assign RD_EN_FIFO_IN = RDEN_P0_OUT; + + assign DOUT = DATA_P0_OUT; + assign DATA_P0_IN = DOUT_FIFO_OUT; + assign VALID = VALID_P0_OUT ; + assign EMPTY = EMPTY_P0_OUT; + assign ALMOST_EMPTY = ALMOSTEMPTY_P0_OUT; + assign EMPTY_P0_IN = EMPTY_FIFO_OUT; + assign UNDERFLOW = UNDERFLOW_P0_OUT ; + + always @ (posedge RD_CLK or posedge RST) + begin + if (RST) + begin + EMPTY_P0_OUT_Q <= 1; + ALMOSTEMPTY_P0_OUT_Q <= 1; + end + else + begin + EMPTY_P0_OUT_Q <= EMPTY_P0_OUT; + ALMOSTEMPTY_P0_OUT_Q <= ALMOSTEMPTY_P0_OUT; + end + end + + end +else + begin : block2 + + assign RD_CLK_P0_IN = 0; + assign RST_P0_IN = 0; + assign RD_EN_P0_IN = 0; + + assign RD_EN_FIFO_IN = RD_EN; + + assign DOUT = DOUT_FIFO_OUT; + assign DATA_P0_IN = 0; + assign VALID = VALID_FIFO_OUT; + assign EMPTY = EMPTY_FIFO_OUT; + assign ALMOST_EMPTY = ALMOST_EMPTY_FIFO_OUT; + assign EMPTY_P0_IN = 0; + assign UNDERFLOW = UNDERFLOW_FIFO_OUT; + + end +endgenerate + + +//Connect Data Count Signals +generate +if (C_PRELOAD_REGS==1 && C_PRELOAD_LATENCY==0 && (C_RD_DATA_COUNT_WIDTH>C_RD_PNTR_WIDTH)) begin : block3 + assign RD_DATA_COUNT = (EMPTY_P0_OUT_Q | RST) ? 0 : (ALMOSTEMPTY_P0_OUT_Q ? 1 : RD_DATA_COUNT_FIFO_OUT + 2); +end +else begin : block3 + assign RD_DATA_COUNT = RD_DATA_COUNT_FIFO_OUT; +end +endgenerate + +generate +if (C_PRELOAD_REGS==1 && C_PRELOAD_LATENCY==0 && (C_WR_DATA_COUNT_WIDTH>C_WR_PNTR_WIDTH)) begin : block4 + assign WR_DATA_COUNT = WR_DATA_COUNT_FIFO_OUT + 2; +end +else begin : block4 + assign WR_DATA_COUNT = WR_DATA_COUNT_FIFO_OUT; +end +endgenerate + + + assign FULL = FULL_FIFO_OUT; + assign ALMOST_FULL = ALMOST_FULL_FIFO_OUT; + assign WR_ACK = WR_ACK_FIFO_OUT; + assign OVERFLOW = OVERFLOW_FIFO_OUT; + assign PROG_FULL = PROG_FULL_FIFO_OUT; + assign PROG_EMPTY = PROG_EMPTY_FIFO_OUT; + assign DATA_COUNT = DATA_COUNT_FIFO_OUT; + + + // if an asynchronous FIFO has been selected, display a message that the FIFO + // will not be cycle-accurate in simulation + initial begin + //if (C_IMPLEMENTATION_TYPE == 1) begin //bug in v3.1 + if (C_IMPLEMENTATION_TYPE == 2) begin //fixed in v3.2 (IP2_Im) + $display("Warning in %m at time %t: When using an asynchronous configuration for the FIFO Generator, the behavioral model is not cycle-accurate. You may wish to choose the structural simulation model instead of the behavioral model. This will ensure accurate behavior and latencies during simulation. You can enable this from CORE Generator by selecting Project -> Project Options -> Generation tab -> Structural Simulation. See the FIFO Generator User Guide for more information.", $time); + end else if (C_IMPLEMENTATION_TYPE == 3 || C_IMPLEMENTATION_TYPE == 4) begin + $display("Failure in %m at time %t: Use of Virtex-4 and Virtex-5 built-in FIFO configurations is currently not supported. Please use the structural simulation model. You can enable this from CORE Generator by selecting Project -> Project Options -> Generation tab -> Structural Simulation. See the FIFO Generator User Guide for more information.", $time); + $finish; + end + + end + +endmodule //fifo_generator_v3_3_bhv_ver + + + + + + +/******************************************************************************* + * Declaration of asynchronous FIFO Module + ******************************************************************************/ +module fifo_generator_v3_3_bhv_ver_as + ( + WR_CLK, RD_CLK, RST, DIN, WR_EN, RD_EN, + PROG_EMPTY_THRESH, PROG_EMPTY_THRESH_ASSERT, PROG_EMPTY_THRESH_NEGATE, + PROG_FULL_THRESH, PROG_FULL_THRESH_ASSERT, PROG_FULL_THRESH_NEGATE, + DOUT, FULL, ALMOST_FULL, WR_ACK, OVERFLOW, EMPTY, ALMOST_EMPTY, VALID, + UNDERFLOW, RD_DATA_COUNT, WR_DATA_COUNT, PROG_FULL, PROG_EMPTY + ); + +/****************************************************************************** + * Declare user parameters and their defaults + *****************************************************************************/ + parameter C_COMMON_CLOCK = 0; + parameter C_COUNT_TYPE = 0; + parameter C_DATA_COUNT_WIDTH = 2; + parameter C_DEFAULT_VALUE = ""; + parameter C_DIN_WIDTH = 8; + parameter C_DOUT_RST_VAL = ""; + parameter C_DOUT_WIDTH = 8; + parameter C_ENABLE_RLOCS = 0; + parameter C_FAMILY = "virtex2"; //Not allowed in Verilog model + parameter C_HAS_ALMOST_EMPTY = 0; + parameter C_HAS_ALMOST_FULL = 0; + parameter C_HAS_BACKUP = 0; + parameter C_HAS_DATA_COUNT = 0; + parameter C_HAS_MEMINIT_FILE = 0; + parameter C_HAS_OVERFLOW = 0; + parameter C_HAS_RD_DATA_COUNT = 0; + parameter C_HAS_RD_RST = 0; + parameter C_HAS_RST = 0; + parameter C_HAS_UNDERFLOW = 0; + parameter C_HAS_VALID = 0; + parameter C_HAS_WR_ACK = 0; + parameter C_HAS_WR_DATA_COUNT = 0; + parameter C_HAS_WR_RST = 0; + parameter C_IMPLEMENTATION_TYPE = 0; + parameter C_INIT_WR_PNTR_VAL = 0; + parameter C_MEMORY_TYPE = 1; + parameter C_MIF_FILE_NAME = ""; + parameter C_OPTIMIZATION_MODE = 0; + parameter C_OVERFLOW_LOW = 0; + parameter C_PRELOAD_LATENCY = 1; + parameter C_PRELOAD_REGS = 0; + parameter C_PROG_EMPTY_THRESH_ASSERT_VAL = 0; + parameter C_PROG_EMPTY_THRESH_NEGATE_VAL = 0; + parameter C_PROG_EMPTY_TYPE = 0; + parameter C_PROG_FULL_THRESH_ASSERT_VAL = 0; + parameter C_PROG_FULL_THRESH_NEGATE_VAL = 0; + parameter C_PROG_FULL_TYPE = 0; + parameter C_RD_DATA_COUNT_WIDTH = 2; + parameter C_RD_DEPTH = 256; + parameter C_RD_PNTR_WIDTH = 8; + parameter C_UNDERFLOW_LOW = 0; + parameter C_VALID_LOW = 0; + parameter C_WR_ACK_LOW = 0; + parameter C_WR_DATA_COUNT_WIDTH = 2; + parameter C_WR_DEPTH = 256; + parameter C_WR_PNTR_WIDTH = 8; + parameter C_WR_RESPONSE_LATENCY = 1; + +/****************************************************************************** + * Declare Input and Output Ports + *****************************************************************************/ + input [C_DIN_WIDTH-1:0] DIN; + input [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH; + input [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_ASSERT; + input [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_NEGATE; + input [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH; + input [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_ASSERT; + input [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_NEGATE; + input RD_CLK; + input RD_EN; + input RST; + input WR_CLK; + input WR_EN; + output ALMOST_EMPTY; + output ALMOST_FULL; + output [C_DOUT_WIDTH-1:0] DOUT; + output EMPTY; + output FULL; + output OVERFLOW; + output PROG_EMPTY; + output PROG_FULL; + output VALID; + output [C_RD_DATA_COUNT_WIDTH-1:0] RD_DATA_COUNT; + output UNDERFLOW; + output WR_ACK; + output [C_WR_DATA_COUNT_WIDTH-1:0] WR_DATA_COUNT; + +/******************************************************************************* + * Input and output register declarations + ******************************************************************************/ +/******************************************************************************* + * Parameters used as constants + ******************************************************************************/ + //When RST is present, set FULL reset value to '1'. + //If core has no RST, make sure FULL powers-on as '0'. + parameter C_FULL_RESET_VAL = C_HAS_RST; + parameter C_ALMOST_FULL_RESET_VAL = C_HAS_RST; + parameter C_PROG_FULL_RESET_VAL = C_HAS_RST; + parameter C_HAS_FAST_FIFO = 0; + parameter C_RATIO_W = (C_WR_DEPTH>C_RD_DEPTH) ? (C_WR_DEPTH/C_RD_DEPTH) : 1; + parameter C_RATIO_R = (C_RD_DEPTH>C_WR_DEPTH) ? (C_RD_DEPTH/C_WR_DEPTH) : 1; + parameter C_FIFO_WR_DEPTH = (C_HAS_FAST_FIFO || (C_PRELOAD_REGS && C_PRELOAD_LATENCY) || C_COMMON_CLOCK) ? C_WR_DEPTH : C_WR_DEPTH - 1; + parameter C_FIFO_RD_DEPTH = (C_HAS_FAST_FIFO || (C_PRELOAD_REGS && C_PRELOAD_LATENCY) || C_COMMON_CLOCK) ? C_RD_DEPTH : C_RD_DEPTH - 1; + + parameter C_PROG_FULL_REG = 0; + parameter C_PROG_EMPTY_REG = 0; + + + //Memory which will be used to simulate a FIFO + reg [C_DIN_WIDTH-1:0] memory[C_WR_DEPTH-1:0]; + reg [31:0] num_wr_bits; + reg [31:0] num_rd_bits; + reg [31:0] next_num_wr_bits; + reg [31:0] next_num_rd_bits; + reg [31:0] wr_ptr; + reg [31:0] rd_ptr; + reg [31:0] wr_ptr_rdclk; + reg [31:0] wr_ptr_rdclk_q; + reg [31:0] wr_ptr_rdclk_next; + reg [31:0] rd_ptr_wrclk; + reg [31:0] rd_ptr_wrclk_q; + reg [31:0] rd_ptr_wrclk_next; + wire [31:0] num_read_words = num_rd_bits/C_DOUT_WIDTH; + wire [31:0] num_read_words_pe = num_rd_bits/(C_DOUT_WIDTH/C_RATIO_W); + wire [C_RD_DATA_COUNT_WIDTH-1:0] num_read_words_sized = num_read_words[C_RD_PNTR_WIDTH-1 : ((C_RD_DATA_COUNT_WIDTH>C_RD_PNTR_WIDTH) ? 0 : C_RD_PNTR_WIDTH-C_RD_DATA_COUNT_WIDTH)]; + wire [31:0] num_write_words = num_wr_bits/C_DIN_WIDTH; + wire [31:0] num_write_words_pf = num_wr_bits/(C_DIN_WIDTH/C_RATIO_R); + wire [C_WR_DATA_COUNT_WIDTH-1:0] num_write_words_sized = num_write_words[C_WR_PNTR_WIDTH-1 : ((C_WR_DATA_COUNT_WIDTH>C_WR_PNTR_WIDTH) ? 0 : C_WR_PNTR_WIDTH-C_WR_DATA_COUNT_WIDTH)]; + wire [31:0] reads_per_write = C_DIN_WIDTH/C_DOUT_WIDTH; + wire [31:0] log2_reads_per_write = log2_val(reads_per_write); + wire [31:0] writes_per_read = C_DOUT_WIDTH/C_DIN_WIDTH; + wire [31:0] log2_writes_per_read = log2_val(writes_per_read); + + /******************************************************************************* + * Internal Registers and wires + ******************************************************************************/ + wire wr_ack_i; + wire overflow_i; + wire underflow_i; + wire valid_i; + wire rst_i; + + + + //Special ideal FIFO signals + reg [C_DOUT_WIDTH-1:0] ideal_dout; + reg ideal_wr_ack; + reg ideal_valid; + reg ideal_overflow; + reg ideal_underflow; + reg ideal_full; + reg ideal_empty; + reg ideal_almost_full; + reg ideal_almost_empty; + reg ideal_prog_full; + reg ideal_prog_empty; + + //MSBs of the counts + reg [C_WR_DATA_COUNT_WIDTH-1 : 0] ideal_wr_count; + reg [C_WR_DATA_COUNT_WIDTH-1 : 0] ideal_wr_count_q; + reg [C_RD_DATA_COUNT_WIDTH-1 : 0] ideal_rd_count; + reg [C_RD_DATA_COUNT_WIDTH-1 : 0] ideal_rd_count_q; + + //user specified value for reseting the size of the fifo + reg [C_DOUT_WIDTH-1:0] dout_reset_val; + + //temporary registers for WR_RESPONSE_LATENCY feature + reg ideal_wr_ack_q; + reg ideal_overflow_q; + + integer tmp_wr_listsize; + integer tmp_rd_listsize; + + //Signal for registered version of prog full and empty + reg prog_full_d; + reg prog_empty_d; + + //Threshold values for Programmable Flags + integer prog_empty_actual_thresh_assert; + integer prog_empty_actual_thresh_negate; + integer prog_full_actual_thresh_assert; + integer prog_full_actual_thresh_negate; + + + /**************************************************************************** + * Function Declarations + ***************************************************************************/ + + task write_fifo; + begin + memory[wr_ptr] <= DIN; + if (wr_ptr == 0) begin + wr_ptr <= C_WR_DEPTH - 1; + end else begin + wr_ptr <= wr_ptr - 1; + end + end + endtask // write_fifo + + task read_fifo; + integer i; + reg [C_DOUT_WIDTH-1:0] tmp_dout; + reg [C_DIN_WIDTH-1:0] memory_read; + reg [31:0] tmp_rd_ptr; + reg [31:0] rd_ptr_high; + reg [31:0] rd_ptr_low; + begin + // output is wider than input + if (reads_per_write == 0) begin + tmp_dout = 0; + tmp_rd_ptr = (rd_ptr << log2_writes_per_read)+(writes_per_read-1); + for (i = writes_per_read - 1; i >= 0; i = i - 1) begin + tmp_dout = tmp_dout << C_DIN_WIDTH; + tmp_dout = tmp_dout | memory[tmp_rd_ptr]; + if (tmp_rd_ptr == 0) begin + tmp_rd_ptr = C_WR_DEPTH - 1; + end else begin + tmp_rd_ptr = tmp_rd_ptr - 1; + end + end + + // output is symmetric + end else if (reads_per_write == 1) begin + tmp_dout = memory[rd_ptr]; + + // input is wider than output + end else begin + rd_ptr_high = rd_ptr >> log2_reads_per_write; + rd_ptr_low = rd_ptr & (reads_per_write - 1); + memory_read = memory[rd_ptr_high]; + tmp_dout = memory_read >> (rd_ptr_low*C_DOUT_WIDTH); + end + ideal_dout <= tmp_dout; + if (rd_ptr == 0) begin + rd_ptr <= C_RD_DEPTH - 1; + end else begin + rd_ptr <= rd_ptr - 1; + end + end + endtask + + /**************************************************************************** + * log2_val + * Returns the 'log2' value for the input value for the supported ratios + ***************************************************************************/ + function [31:0] log2_val; + input [31:0] binary_val; + + begin + if (binary_val == 8) begin + log2_val = 3; + end else if (binary_val == 4) begin + log2_val = 2; + end else begin + log2_val = 1; + end + end + endfunction + + /************************************************************************* + * hexstr_conv + * Converts a string of type hex to a binary value (for C_DOUT_RST_VAL) + ***********************************************************************/ + function [C_DOUT_WIDTH-1:0] hexstr_conv; + input [(C_DOUT_WIDTH*8)-1:0] def_data; + + integer index,i,j; + reg [3:0] bin; + + begin + index = 0; + hexstr_conv = 'b0; + for( i=C_DOUT_WIDTH-1; i>=0; i=i-1 ) + begin + case (def_data[7:0]) + 8'b00000000 : + begin + bin = 4'b0000; + i = -1; + end + 8'b00110000 : bin = 4'b0000; + 8'b00110001 : bin = 4'b0001; + 8'b00110010 : bin = 4'b0010; + 8'b00110011 : bin = 4'b0011; + 8'b00110100 : bin = 4'b0100; + 8'b00110101 : bin = 4'b0101; + 8'b00110110 : bin = 4'b0110; + 8'b00110111 : bin = 4'b0111; + 8'b00111000 : bin = 4'b1000; + 8'b00111001 : bin = 4'b1001; + 8'b01000001 : bin = 4'b1010; + 8'b01000010 : bin = 4'b1011; + 8'b01000011 : bin = 4'b1100; + 8'b01000100 : bin = 4'b1101; + 8'b01000101 : bin = 4'b1110; + 8'b01000110 : bin = 4'b1111; + 8'b01100001 : bin = 4'b1010; + 8'b01100010 : bin = 4'b1011; + 8'b01100011 : bin = 4'b1100; + 8'b01100100 : bin = 4'b1101; + 8'b01100101 : bin = 4'b1110; + 8'b01100110 : bin = 4'b1111; + default : + begin + bin = 4'bx; + end + endcase + for( j=0; j<4; j=j+1) + begin + if ((index*4)+j < C_DOUT_WIDTH) + begin + hexstr_conv[(index*4)+j] = bin[j]; + end + end + index = index + 1; + def_data = def_data >> 8; + end + end + endfunction + + /************************************************************************* + * Initialize Signals for clean power-on simulation + *************************************************************************/ + initial + begin + num_wr_bits = 0; + num_rd_bits = 0; + next_num_wr_bits = 0; + next_num_rd_bits = 0; + rd_ptr = C_RD_DEPTH - 1; + wr_ptr = C_WR_DEPTH - 1; + rd_ptr_wrclk = rd_ptr; + rd_ptr_wrclk_q = rd_ptr; + wr_ptr_rdclk = wr_ptr; + wr_ptr_rdclk_q = wr_ptr; + dout_reset_val = hexstr_conv(C_DOUT_RST_VAL); + if (C_MEMORY_TYPE == 1) begin + ideal_dout = dout_reset_val; + end else begin + ideal_dout = 0; + end + ideal_wr_ack = 1'b0; + ideal_valid = 1'b0; + ideal_overflow = 1'b0; + ideal_underflow = 1'b0; + //Modified the start-up value of FULL to '0' in v3.2 (IP2_Im) + //ideal_full = C_FULL_RESET_VAL; //was in v3.1 + ideal_full = 1'b0; //v3.2 + ideal_empty = 1'b1; + //Modified the start-up value of ALMOST_FULL to '0' in v3.2 (IP2_Im) + //ideal_almost_full = C_ALMOST_FULL_RESET_VAL; //was in v3.1 + ideal_almost_full = 1'b0; //v3.2 + ideal_almost_empty = 1'b1; + ideal_wr_count = 0; + ideal_rd_count = 0; + //Modified the start-up value of PROG_FULL to '0' in v3.2 (IP2_Im) + //ideal_prog_full = C_PROG_FULL_RESET_VAL; //was in v3.1 + ideal_prog_full = 1'b0; //v3.2 + ideal_prog_empty = 1'b1; + //Modified the start-up value of PROG_FULL to '0' in v3.2 (IP2_Im) + //Therefore, prog_full_d has to start-up at '0' too + //prog_full_d = C_PROG_FULL_RESET_VAL; //was in v3.1 + prog_full_d = 1'b0; //v3.2 + prog_empty_d = 1'b1; + end + + + + /************************************************************************* + * Assign Internal ideal signals to output ports + *************************************************************************/ + assign DOUT = ideal_dout; + assign FULL = ideal_full; + assign EMPTY = ideal_empty; + assign ALMOST_FULL = ideal_almost_full; + assign ALMOST_EMPTY = ideal_almost_empty; + assign WR_DATA_COUNT = ideal_wr_count; + assign RD_DATA_COUNT = ideal_rd_count; + assign PROG_FULL = (C_PROG_FULL_REG==1) ? ideal_prog_full : prog_full_d; + assign PROG_EMPTY = (C_PROG_EMPTY_REG==1) ? ideal_prog_empty : prog_empty_d; + + //Handshaking signals can be active low, depending on _LOW parameters + assign valid_i = (C_PRELOAD_LATENCY==0) ? (RD_EN & ~EMPTY) : ideal_valid; + assign VALID = valid_i ? !C_VALID_LOW : C_VALID_LOW; + assign underflow_i = (C_PRELOAD_LATENCY==0) ? (RD_EN & EMPTY) : ideal_underflow; + assign UNDERFLOW = underflow_i ? !C_UNDERFLOW_LOW : C_UNDERFLOW_LOW; + + assign WR_ACK = wr_ack_i ? !C_WR_ACK_LOW : C_WR_ACK_LOW; + assign wr_ack_i = (C_WR_RESPONSE_LATENCY==2) ? ideal_wr_ack_q : + (C_WR_RESPONSE_LATENCY==1) ? ideal_wr_ack : + (WR_EN & !FULL); + assign OVERFLOW = overflow_i ? !C_OVERFLOW_LOW : C_OVERFLOW_LOW; + assign overflow_i = (C_WR_RESPONSE_LATENCY==2) ? ideal_overflow_q : + (C_WR_RESPONSE_LATENCY==1) ? ideal_overflow : + (WR_EN & FULL); + + assign rst_i = C_HAS_RST ? RST : 0; + + + always @(posedge WR_CLK or posedge rst_i) begin : gen_fifo_w + + /****** Reset fifo (case 1)***************************************/ + if (rst_i == 1'b1) begin + num_wr_bits <= 0; + next_num_wr_bits <= 0; + wr_ptr <= C_WR_DEPTH - 1; + rd_ptr_wrclk <= C_RD_DEPTH - 1; + rd_ptr_wrclk_q <= C_RD_DEPTH - 1; + ideal_wr_ack <= 0; + //Overflow reports an overflow error when a user writes to a + // Full FIFO, even if the core is in RESET + ideal_overflow <= WR_EN & ideal_full; + ideal_full <= C_FULL_RESET_VAL; + ideal_almost_full <= C_ALMOST_FULL_RESET_VAL; + ideal_wr_count <= 0; + ideal_wr_count_q <= 0; + + ideal_prog_full <= C_PROG_FULL_RESET_VAL; + prog_full_d <= C_PROG_FULL_RESET_VAL; + + end else begin //rst_i==0 + + //Determine the current number of words in the FIFO + tmp_wr_listsize = (C_RATIO_R > 1) ? num_wr_bits/C_DOUT_WIDTH : + num_wr_bits/C_DIN_WIDTH; + rd_ptr_wrclk_next = rd_ptr; + if (rd_ptr_wrclk < rd_ptr_wrclk_next) begin + next_num_wr_bits = num_wr_bits - + C_DOUT_WIDTH*(rd_ptr_wrclk + C_RD_DEPTH + - rd_ptr_wrclk_next); + end else begin + next_num_wr_bits = num_wr_bits - + C_DOUT_WIDTH*(rd_ptr_wrclk - rd_ptr_wrclk_next); + end + + //If this is a write, handle the write by adding the value + // to the linked list, and updating all outputs appropriately + if (WR_EN == 1'b1) begin + if (ideal_full == 1'b1) begin + + //If the FIFO is full, do NOT perform the write, + // update flags accordingly + if ((tmp_wr_listsize + C_RATIO_R - 1)/C_RATIO_R >= C_FIFO_WR_DEPTH) + begin + //write unsuccessful - do not change contents + + //Do not acknowledge the write + ideal_wr_ack <= 0; + //throw an overflow error + ideal_overflow <= 1; + //Reminder that FIFO is still full + ideal_full <= 1'b1; + ideal_almost_full <= 1'b1; + + ideal_wr_count <= num_write_words_sized; + + //If the FIFO is one from full, but reporting full + end else if ((tmp_wr_listsize + C_RATIO_R - 1)/C_RATIO_R == + C_FIFO_WR_DEPTH-1) begin + //No change to FIFO + + //Write not successful + ideal_wr_ack <= 0; + ideal_overflow <= 1; + //With DEPTH-1 words in the FIFO, it is almost_full + ideal_full <= 1'b0; + ideal_almost_full <= 1'b1; + + ideal_wr_count <= num_write_words_sized; + + + //If the FIFO is completely empty, but it is + // reporting FULL for some reason (like reset) + end else if ((tmp_wr_listsize + C_RATIO_R - 1)/C_RATIO_R <= + C_FIFO_WR_DEPTH-2) begin + //No change to FIFO + + //Write not successful + ideal_wr_ack <= 0; + ideal_overflow <= 1; + //FIFO is really not close to full, so change flag status. + ideal_full <= 1'b0; + ideal_almost_full <= 1'b0; + + ideal_wr_count <= num_write_words_sized; + end //(tmp_wr_listsize == 0) + + end else begin + + //If the FIFO is full, do NOT perform the write, + // update flags accordingly + if ((tmp_wr_listsize + C_RATIO_R - 1)/C_RATIO_R >= + C_FIFO_WR_DEPTH) begin + //write unsuccessful - do not change contents + + //Do not acknowledge the write + ideal_wr_ack <= 0; + //throw an overflow error + ideal_overflow <= 1; + //Reminder that FIFO is still full + ideal_full <= 1'b1; + ideal_almost_full <= 1'b1; + + ideal_wr_count <= num_write_words_sized; + + //If the FIFO is one from full + end else if ((tmp_wr_listsize + C_RATIO_R - 1)/C_RATIO_R == + C_FIFO_WR_DEPTH-1) begin + //Add value on DIN port to FIFO + write_fifo; + next_num_wr_bits = next_num_wr_bits + C_DIN_WIDTH; + + //Write successful, so issue acknowledge + // and no error + ideal_wr_ack <= 1; + ideal_overflow <= 0; + //This write is CAUSING the FIFO to go full + ideal_full <= 1'b1; + ideal_almost_full <= 1'b1; + + ideal_wr_count <= num_write_words_sized; + + //If the FIFO is 2 from full + end else if ((tmp_wr_listsize + C_RATIO_R - 1)/C_RATIO_R == + C_FIFO_WR_DEPTH-2) begin + //Add value on DIN port to FIFO + write_fifo; + next_num_wr_bits = next_num_wr_bits + C_DIN_WIDTH; + //Write successful, so issue acknowledge + // and no error + ideal_wr_ack <= 1; + ideal_overflow <= 0; + //Still 2 from full + ideal_full <= 1'b0; + //2 from full, and writing, so set almost_full + ideal_almost_full <= 1'b1; + + ideal_wr_count <= num_write_words_sized; + + //If the FIFO is not close to being full + end else if ((tmp_wr_listsize + C_RATIO_R - 1)/C_RATIO_R < + C_FIFO_WR_DEPTH-2) begin + //Add value on DIN port to FIFO + write_fifo; + next_num_wr_bits = next_num_wr_bits + C_DIN_WIDTH; + //Write successful, so issue acknowledge + // and no error + ideal_wr_ack <= 1; + ideal_overflow <= 0; + //Not even close to full. + ideal_full <= 1'b0; + ideal_almost_full <= 1'b0; + + ideal_wr_count <= num_write_words_sized; + + end + + end + + end else begin //(WR_EN == 1'b1) + + //If user did not attempt a write, then do not + // give ack or err + ideal_wr_ack <= 0; + ideal_overflow <= 0; + + //Implied statements: + //ideal_empty <= ideal_empty; + //ideal_almost_empty <= ideal_almost_empty; + + //Check for full + if ((tmp_wr_listsize + C_RATIO_R - 1)/C_RATIO_R >= C_FIFO_WR_DEPTH) + ideal_full <= 1'b1; + else + ideal_full <= 1'b0; + + //Check for almost_full + if ((tmp_wr_listsize + C_RATIO_R - 1)/C_RATIO_R >= C_FIFO_WR_DEPTH-1) + ideal_almost_full <= 1'b1; + else + ideal_almost_full <= 1'b0; + + ideal_wr_count <= num_write_words_sized; + end + + /********************************************************* + * Programmable FULL flags + *********************************************************/ + //Determine the Assert and Negate thresholds for Programmable Full + // (Subtract 2 read-sized words when using Preload 0) + + //Single Programmable Full Constant Threshold + if (C_PROG_FULL_TYPE==1) begin + if (C_PRELOAD_REGS==1 && C_PRELOAD_LATENCY==0) begin + prog_full_actual_thresh_assert = C_PROG_FULL_THRESH_ASSERT_VAL*C_RATIO_R-2*C_RATIO_W; + prog_full_actual_thresh_negate = C_PROG_FULL_THRESH_ASSERT_VAL*C_RATIO_R-2*C_RATIO_W; + end else begin + prog_full_actual_thresh_assert = C_PROG_FULL_THRESH_ASSERT_VAL*C_RATIO_R; + prog_full_actual_thresh_negate = C_PROG_FULL_THRESH_ASSERT_VAL*C_RATIO_R; + end + + //Two Programmable Full Constant Thresholds + end else if (C_PROG_FULL_TYPE==2) begin + if (C_PRELOAD_REGS==1 && C_PRELOAD_LATENCY==0) begin + prog_full_actual_thresh_assert = C_PROG_FULL_THRESH_ASSERT_VAL*C_RATIO_R-2*C_RATIO_W; + prog_full_actual_thresh_negate = C_PROG_FULL_THRESH_NEGATE_VAL*C_RATIO_R-2*C_RATIO_W; + end else begin + prog_full_actual_thresh_assert = C_PROG_FULL_THRESH_ASSERT_VAL*C_RATIO_R; + prog_full_actual_thresh_negate = C_PROG_FULL_THRESH_NEGATE_VAL*C_RATIO_R; + end + + //Single Programmable Full Threshold Input + end else if (C_PROG_FULL_TYPE==3) begin + if (C_PRELOAD_REGS==1 && C_PRELOAD_LATENCY==0) begin + prog_full_actual_thresh_assert = PROG_FULL_THRESH*C_RATIO_R-2*C_RATIO_W; + prog_full_actual_thresh_negate = PROG_FULL_THRESH*C_RATIO_R-2*C_RATIO_W; + end else begin + prog_full_actual_thresh_assert = PROG_FULL_THRESH*C_RATIO_R; + prog_full_actual_thresh_negate = PROG_FULL_THRESH*C_RATIO_R; + end + + //Two Programmable Full Threshold Inputs + end else if (C_PROG_FULL_TYPE==4) begin + if (C_PRELOAD_REGS==1 && C_PRELOAD_LATENCY==0) begin + prog_full_actual_thresh_assert = PROG_FULL_THRESH_ASSERT*C_RATIO_R-2*C_RATIO_W; + prog_full_actual_thresh_negate = PROG_FULL_THRESH_NEGATE*C_RATIO_R-2*C_RATIO_W; + end else begin + prog_full_actual_thresh_assert = PROG_FULL_THRESH_ASSERT*C_RATIO_R; + prog_full_actual_thresh_negate = PROG_FULL_THRESH_NEGATE*C_RATIO_R; + end + end //C_PROG_FULL_TYPE + + // If we will be going at or above prog_full_actual_thresh_assert + // threshold on the next clock cycle, then assert + // PROG_FULL. There may be pending reads that haven't caught + // up yet, but we need to assume the worst + if ((num_write_words_pf >= prog_full_actual_thresh_assert-1) && WR_EN) begin + prog_full_d <= 1'b1; + + // If we are at or above the prog_full_actual_thresh_assert, then + // assert PROG_FULL + end else if (num_write_words_pf >= prog_full_actual_thresh_assert) begin + prog_full_d <= 1'b1; + + // If we are below the prog_full_actual_thresh_negate, then + // de-assert PROG_FULL + end else if (num_write_words_pf < prog_full_actual_thresh_negate) begin + prog_full_d <= 1'b0; + end + + + + ideal_prog_full <= prog_full_d; + num_wr_bits <= next_num_wr_bits; + rd_ptr_wrclk_q <= rd_ptr_wrclk; + rd_ptr_wrclk <= rd_ptr; + ideal_wr_count_q <= ideal_wr_count; + + end //rst_i==0 + end // write always + + always @(posedge RD_CLK or posedge rst_i) begin : gen_fifo_r + + /****** Reset fifo (case 1)***************************************/ + if (rst_i) begin + num_rd_bits <= 0; + next_num_rd_bits <= 0; + rd_ptr <= C_RD_DEPTH -1; + wr_ptr_rdclk <= C_WR_DEPTH -1; + ideal_dout <= dout_reset_val; + ideal_valid <= 1'b0; + //Underflow reports an underflow error when a user reads from an + // Empty FIFO, even if the core is in RESET + ideal_underflow <= ideal_empty & RD_EN; + ideal_empty <= 1'b1; + ideal_almost_empty <= 1'b1; + ideal_rd_count <= 0; + ideal_rd_count_q <= 0; + + ideal_prog_empty <= 1'b1; + prog_empty_d <= 1; + + + end else begin //rst_i==0 + + //Determine the current number of words in the FIFO + tmp_rd_listsize = (C_RATIO_W > 1) ? num_rd_bits/C_DIN_WIDTH : + num_rd_bits/C_DOUT_WIDTH; + wr_ptr_rdclk_next = wr_ptr; + if (wr_ptr_rdclk < wr_ptr_rdclk_next) begin + next_num_rd_bits = num_rd_bits + + C_DIN_WIDTH*(wr_ptr_rdclk +C_WR_DEPTH + - wr_ptr_rdclk_next); + end else begin + next_num_rd_bits = num_rd_bits + + C_DIN_WIDTH*(wr_ptr_rdclk - wr_ptr_rdclk_next); + end + + /*****************************************************************/ + // Read Operation - Read Latency 1 + /*****************************************************************/ + if (C_PRELOAD_LATENCY==1) begin + + if (RD_EN == 1'b1) begin + + if (ideal_empty == 1'b1) begin + + //If the FIFO is completely empty, and is reporting empty + if (tmp_rd_listsize/C_RATIO_W <= 0) + begin + //Do not change the contents of the FIFO + + //Do not acknowledge the read from empty FIFO + ideal_valid <= 1'b0; + //Throw an underflow error + ideal_underflow <= 1'b1; + //Reminder that FIFO is still empty + ideal_empty <= 1'b1; + ideal_almost_empty <= 1'b1; + + ideal_rd_count <= num_read_words_sized; + end // if (tmp_rd_listsize <= 0) + + //If the FIFO is one from empty, but it is reporting empty + else if (tmp_rd_listsize/C_RATIO_W == 1) + begin + //Do not change the contents of the FIFO + + //Do not acknowledge the read from empty FIFO + ideal_valid <= 1'b0; + //Throw an underflow error + ideal_underflow <= 1'b1; + //Note that FIFO is no longer empty, but is almost empty (has one word left) + ideal_empty <= 1'b0; + ideal_almost_empty <= 1'b1; + + ideal_rd_count <= num_read_words_sized; + + end // if (tmp_rd_listsize == 1) + + //If the FIFO is two from empty, and is reporting empty + else if (tmp_rd_listsize/C_RATIO_W == 2) + begin + //Do not change the contents of the FIFO + + //Do not acknowledge the read from empty FIFO + ideal_valid <= 1'b0; + //Throw an underflow error + ideal_underflow <= 1'b1; + //Fifo has two words, so is neither empty or almost empty + ideal_empty <= 1'b0; + ideal_almost_empty <= 1'b0; + + ideal_rd_count <= num_read_words_sized; + + end // if (tmp_rd_listsize == 2) + + //If the FIFO is not close to empty, but is reporting that it is + // Treat the FIFO as empty this time, but unset EMPTY flags. + if ((tmp_rd_listsize/C_RATIO_W > 2) && (tmp_rd_listsize/C_RATIO_W 2) && (tmp_rd_listsize<=C_FIFO_RD_DEPTH-1)) + end // else: if(ideal_empty == 1'b1) + + else //if (ideal_empty == 1'b0) + begin + + //If the FIFO is completely full, and we are successfully reading from it + if (tmp_rd_listsize/C_RATIO_W >= C_FIFO_RD_DEPTH) + begin + //Read the value from the FIFO + read_fifo; + next_num_rd_bits = next_num_rd_bits - C_DOUT_WIDTH; + + //Acknowledge the read from the FIFO, no error + ideal_valid <= 1'b1; + ideal_underflow <= 1'b0; + //Not close to empty + ideal_empty <= 1'b0; + ideal_almost_empty <= 1'b0; + + ideal_rd_count <= num_read_words_sized; + + end // if (tmp_rd_listsize == C_FIFO_RD_DEPTH) + + //If the FIFO is not close to being empty + else if ((tmp_rd_listsize/C_RATIO_W > 2) && (tmp_rd_listsize/C_RATIO_W<=C_FIFO_RD_DEPTH)) + begin + //Read the value from the FIFO + read_fifo; + next_num_rd_bits = next_num_rd_bits - C_DOUT_WIDTH; + + //Acknowledge the read from the FIFO, no error + ideal_valid <= 1'b1; + ideal_underflow <= 1'b0; + //Not close to empty + ideal_empty <= 1'b0; + ideal_almost_empty <= 1'b0; + + ideal_rd_count <= num_read_words_sized; + + end // if ((tmp_rd_listsize > 2) && (tmp_rd_listsize<=C_FIFO_RD_DEPTH-1)) + + //If the FIFO is two from empty + else if (tmp_rd_listsize/C_RATIO_W == 2) + begin + //Read the value from the FIFO + read_fifo; + next_num_rd_bits = next_num_rd_bits - C_DOUT_WIDTH; + + //Acknowledge the read from the FIFO, no error + ideal_valid <= 1'b1; + ideal_underflow <= 1'b0; + //Fifo is not yet empty. It is going almost_empty + ideal_empty <= 1'b0; + ideal_almost_empty <= 1'b1; + + ideal_rd_count <= num_read_words_sized; + + end // if (tmp_rd_listsize == 2) + + //If the FIFO is one from empty + else if ((tmp_rd_listsize/C_RATIO_W == 1)) + begin + //Read the value from the FIFO + read_fifo; + next_num_rd_bits = next_num_rd_bits - C_DOUT_WIDTH; + + //Acknowledge the read from the FIFO, no error + ideal_valid <= 1'b1; + ideal_underflow <= 1'b0; + //Note that FIFO is GOING empty + ideal_empty <= 1'b1; + ideal_almost_empty <= 1'b1; + + ideal_rd_count <= num_read_words_sized; + + end // if (tmp_rd_listsize == 1) + + + //If the FIFO is completely empty + else if (tmp_rd_listsize/C_RATIO_W <= 0) + begin + //Do not change the contents of the FIFO + + //Do not acknowledge the read from empty FIFO + ideal_valid <= 1'b0; + //Throw an underflow error + ideal_underflow <= 1'b1; + //Reminder that FIFO is still empty + ideal_empty <= 1'b1; + ideal_almost_empty <= 1'b1; + + ideal_rd_count <= num_read_words_sized; + + end // if (tmp_rd_listsize <= 0) + + end // if (ideal_empty == 1'b0) + + end //(RD_EN == 1'b1) + + else //if (RD_EN == 1'b0) + begin + //If user did not attempt a read, do not give an ack or err + ideal_valid <= 1'b0; + ideal_underflow <= 1'b0; + + //Check for empty + if (tmp_rd_listsize/C_RATIO_W <= 0) + ideal_empty <= 1'b1; + else + ideal_empty <= 1'b0; + + //Check for almost_empty + if (tmp_rd_listsize/C_RATIO_W <= 1) + ideal_almost_empty <= 1'b1; + else + ideal_almost_empty <= 1'b0; + + ideal_rd_count <= num_read_words_sized; + + end // else: !if(RD_EN == 1'b1) + + /*****************************************************************/ + // Read Operation - Read Latency 0 + /*****************************************************************/ + end else if (C_PRELOAD_REGS==1 && C_PRELOAD_LATENCY==0) begin + if (RD_EN == 1'b1) begin + + if (ideal_empty == 1'b1) begin + + //If the FIFO is completely empty, and is reporting empty + if (tmp_rd_listsize/C_RATIO_W <= 0) begin + //Do not change the contents of the FIFO + + //Do not acknowledge the read from empty FIFO + ideal_valid <= 1'b0; + //Throw an underflow error + ideal_underflow <= 1'b1; + //Reminder that FIFO is still empty + ideal_empty <= 1'b1; + ideal_almost_empty <= 1'b1; + + ideal_rd_count <= num_read_words_sized; + + //If the FIFO is one from empty, but it is reporting empty + end else if (tmp_rd_listsize/C_RATIO_W == 1) begin + //Do not change the contents of the FIFO + + //Do not acknowledge the read from empty FIFO + ideal_valid <= 1'b0; + //Throw an underflow error + ideal_underflow <= 1'b1; + //Note that FIFO is no longer empty, but is almost empty (has one word left) + ideal_empty <= 1'b0; + ideal_almost_empty <= 1'b1; + + ideal_rd_count <= num_read_words_sized; + + //If the FIFO is two from empty, and is reporting empty + end else if (tmp_rd_listsize/C_RATIO_W == 2) begin + //Do not change the contents of the FIFO + + //Do not acknowledge the read from empty FIFO + ideal_valid <= 1'b0; + //Throw an underflow error + ideal_underflow <= 1'b1; + //Fifo has two words, so is neither empty or almost empty + ideal_empty <= 1'b0; + ideal_almost_empty <= 1'b0; + + ideal_rd_count <= num_read_words_sized; + + //If the FIFO is not close to empty, but is reporting that it is + // Treat the FIFO as empty this time, but unset EMPTY flags. + end else if ((tmp_rd_listsize/C_RATIO_W > 2) && + (tmp_rd_listsize/C_RATIO_W 2) && (tmp_rd_listsize<=C_FIFO_RD_DEPTH-1)) + + end else begin + + //If the FIFO is completely full, and we are successfully reading from it + if (tmp_rd_listsize/C_RATIO_W >= C_FIFO_RD_DEPTH) begin + //Read the value from the FIFO + read_fifo; + next_num_rd_bits = next_num_rd_bits - C_DOUT_WIDTH; + + //Acknowledge the read from the FIFO, no error + ideal_valid <= 1'b1; + ideal_underflow <= 1'b0; + //Not close to empty + ideal_empty <= 1'b0; + ideal_almost_empty <= 1'b0; + + ideal_rd_count <= num_read_words_sized; + + //If the FIFO is not close to being empty + end else if ((tmp_rd_listsize/C_RATIO_W > 2) && + (tmp_rd_listsize/C_RATIO_W<=C_FIFO_RD_DEPTH)) begin + //Read the value from the FIFO + read_fifo; + next_num_rd_bits = next_num_rd_bits - C_DOUT_WIDTH; + + //Acknowledge the read from the FIFO, no error + ideal_valid <= 1'b1; + ideal_underflow <= 1'b0; + //Not close to empty + ideal_empty <= 1'b0; + ideal_almost_empty <= 1'b0; + + ideal_rd_count <= num_read_words_sized; + + //If the FIFO is two from empty + end else if (tmp_rd_listsize/C_RATIO_W == 2) begin + //Read the value from the FIFO + read_fifo; + next_num_rd_bits = next_num_rd_bits - C_DOUT_WIDTH; + + //Acknowledge the read from the FIFO, no error + ideal_valid <= 1'b1; + ideal_underflow <= 1'b0; + //Fifo is not yet empty. It is going almost_empty + ideal_empty <= 1'b0; + ideal_almost_empty <= 1'b1; + + ideal_rd_count <= num_read_words_sized; + + //If the FIFO is one from empty + end else if (tmp_rd_listsize/C_RATIO_W == 1) begin + //Read the value from the FIFO + read_fifo; + next_num_rd_bits = next_num_rd_bits - C_DOUT_WIDTH; + + //Acknowledge the read from the FIFO, no error + ideal_valid <= 1'b1; + ideal_underflow <= 1'b0; + //Note that FIFO is GOING empty + ideal_empty <= 1'b1; + ideal_almost_empty <= 1'b1; + + ideal_rd_count <= num_read_words_sized; + + //If the FIFO is completely empty + end else if (tmp_rd_listsize/C_RATIO_W <= 0) begin + //Do not change the contents of the FIFO + + //Do not acknowledge the read from empty FIFO + ideal_valid <= 1'b0; + //Throw an underflow error + ideal_underflow <= 1'b1; + //Reminder that FIFO is still empty + ideal_empty <= 1'b1; + ideal_almost_empty <= 1'b1; + + ideal_rd_count <= num_read_words_sized; + + end // if (tmp_rd_listsize <= 0) + + end // if (ideal_empty == 1'b0) + + end //(RD_EN == 1'b1) + + else //if (RD_EN == 1'b0) + begin + //If user did not attempt a read, do not give an ack or err + ideal_valid <= 1'b0; + ideal_underflow <= 1'b0; + + //Check for empty + if (tmp_rd_listsize/C_RATIO_W <= 0) + ideal_empty <= 1'b1; + else + ideal_empty <= 1'b0; + + //Check for almost_empty + if (tmp_rd_listsize/C_RATIO_W <= 1) + ideal_almost_empty <= 1'b1; + else + ideal_almost_empty <= 1'b0; + + ideal_rd_count <= num_read_words_sized; + + end // else: !if(RD_EN == 1'b1) + end //if (C_PRELOAD_REGS==1 && C_PRELOAD_LATENCY==0) + + + /********************************************************* + * Programmable EMPTY flags + *********************************************************/ + //Determine the Assert and Negate thresholds for Programmable Empty + // (Subtract 2 read-sized words when using Preload 0) + + //Single Programmable Empty Constant Threshold + if (C_PROG_EMPTY_TYPE==1) begin + if (C_PRELOAD_REGS==1 && C_PRELOAD_LATENCY==0) begin + prog_empty_actual_thresh_assert = C_PROG_EMPTY_THRESH_ASSERT_VAL-2; + prog_empty_actual_thresh_negate = C_PROG_EMPTY_THRESH_ASSERT_VAL-2; + end + else begin + prog_empty_actual_thresh_assert = C_PROG_EMPTY_THRESH_ASSERT_VAL; + prog_empty_actual_thresh_negate = C_PROG_EMPTY_THRESH_ASSERT_VAL; + end + + //Two Programmable Empty Constant Thresholds + end else if (C_PROG_EMPTY_TYPE==2) begin + if (C_PRELOAD_REGS==1 && C_PRELOAD_LATENCY==0) begin + prog_empty_actual_thresh_assert = C_PROG_EMPTY_THRESH_ASSERT_VAL-2; + prog_empty_actual_thresh_negate = C_PROG_EMPTY_THRESH_NEGATE_VAL-2; + end + else begin + prog_empty_actual_thresh_assert = C_PROG_EMPTY_THRESH_ASSERT_VAL; + prog_empty_actual_thresh_negate = C_PROG_EMPTY_THRESH_NEGATE_VAL; + end + + //Single Programmable Empty Constant Threshold + end else if (C_PROG_EMPTY_TYPE==3) begin + if (C_PRELOAD_REGS==1 && C_PRELOAD_LATENCY==0) begin + prog_empty_actual_thresh_assert = PROG_EMPTY_THRESH-2; + prog_empty_actual_thresh_negate = PROG_EMPTY_THRESH-2; + end + else begin + prog_empty_actual_thresh_assert = PROG_EMPTY_THRESH; + prog_empty_actual_thresh_negate = PROG_EMPTY_THRESH; + + end + //Two Programmable Empty Constant Thresholds + end else if (C_PROG_EMPTY_TYPE==4) begin + if (C_PRELOAD_REGS==1 && C_PRELOAD_LATENCY==0) begin + prog_empty_actual_thresh_assert = PROG_EMPTY_THRESH_ASSERT-2; + prog_empty_actual_thresh_negate = PROG_EMPTY_THRESH_NEGATE-2; + end + else begin + prog_empty_actual_thresh_assert = PROG_EMPTY_THRESH_ASSERT; + prog_empty_actual_thresh_negate = PROG_EMPTY_THRESH_NEGATE; + end + end + + // If we will be going at or below the + // prog_empty_actual_thresh_assert threshold on the next clock + // cycle, then assert PROG_EMPTY. There may be pending + // writes that haven't caught up yet, but we need to assume the worst + if ((num_read_words_pe/C_RATIO_W == prog_empty_actual_thresh_assert+1) && RD_EN) begin + prog_empty_d <= 1'b1; + + // If we are at or below the prog_empty_actual_thresh_assert, + // then assert PROG_EMPTY + end else if (num_read_words_pe/C_RATIO_W <= prog_empty_actual_thresh_assert) begin + prog_empty_d <= 1'b1; + + // If we are above the prog_empty_actual_thresh_negate, then + // de-assert PROG_EMPTY + end else if (num_read_words_pe/C_RATIO_W > prog_empty_actual_thresh_negate) begin + prog_empty_d <= 1'b0; + end + + + ideal_prog_empty <= prog_empty_d; + ideal_rd_count_q <= ideal_rd_count; + num_rd_bits <= next_num_rd_bits; + wr_ptr_rdclk_q <= wr_ptr_rdclk; + wr_ptr_rdclk <= wr_ptr; + end //rst_i==0 + end //always + +endmodule // fifo_generator_v3_3_bhv_ver_as + + +/******************************************************************************* + * Declaration of top-level module + ******************************************************************************/ +module fifo_generator_v3_3_bhv_ver_ss + ( + CLK, RST, SRST, DIN, WR_EN, RD_EN, + PROG_FULL_THRESH, PROG_FULL_THRESH_ASSERT, PROG_FULL_THRESH_NEGATE, + PROG_EMPTY_THRESH, PROG_EMPTY_THRESH_ASSERT, PROG_EMPTY_THRESH_NEGATE, + DOUT, FULL, ALMOST_FULL, WR_ACK, OVERFLOW, EMPTY, + ALMOST_EMPTY, VALID, UNDERFLOW, DATA_COUNT, + PROG_FULL, PROG_EMPTY + ); + +/****************************************************************************** + * Declare user parameters and their defaults + *****************************************************************************/ + parameter C_COMMON_CLOCK = 0; + parameter C_COUNT_TYPE = 0; + parameter C_DATA_COUNT_WIDTH = 2; + parameter C_DEFAULT_VALUE = ""; + parameter C_DIN_WIDTH = 8; + parameter C_DOUT_RST_VAL = ""; + parameter C_DOUT_WIDTH = 8; + parameter C_ENABLE_RLOCS = 0; + parameter C_FAMILY = "virtex2"; //Not allowed in Verilog model + parameter C_HAS_ALMOST_EMPTY = 0; + parameter C_HAS_ALMOST_FULL = 0; + parameter C_HAS_BACKUP = 0; + parameter C_HAS_DATA_COUNT = 0; + parameter C_HAS_MEMINIT_FILE = 0; + parameter C_HAS_OVERFLOW = 0; + parameter C_HAS_RD_DATA_COUNT = 0; + parameter C_HAS_RD_RST = 0; + parameter C_HAS_RST = 0; + //Added Synchronous Reset feature for v3.2 (IP2_Im) + parameter C_HAS_SRST = 0; + parameter C_HAS_UNDERFLOW = 0; + parameter C_HAS_VALID = 0; + parameter C_HAS_WR_ACK = 0; + parameter C_HAS_WR_DATA_COUNT = 0; + parameter C_HAS_WR_RST = 0; + parameter C_IMPLEMENTATION_TYPE = 0; + parameter C_INIT_WR_PNTR_VAL = 0; + parameter C_MEMORY_TYPE = 1; + parameter C_MIF_FILE_NAME = ""; + parameter C_OPTIMIZATION_MODE = 0; + parameter C_OVERFLOW_LOW = 0; + parameter C_PRELOAD_LATENCY = 1; + parameter C_PRELOAD_REGS = 0; + parameter C_PROG_EMPTY_THRESH_ASSERT_VAL = 0; + parameter C_PROG_EMPTY_THRESH_NEGATE_VAL = 0; + parameter C_PROG_EMPTY_TYPE = 0; + parameter C_PROG_FULL_THRESH_ASSERT_VAL = 0; + parameter C_PROG_FULL_THRESH_NEGATE_VAL = 0; + parameter C_PROG_FULL_TYPE = 0; + parameter C_RD_DATA_COUNT_WIDTH = 2; + parameter C_RD_DEPTH = 256; + parameter C_RD_PNTR_WIDTH = 8; + parameter C_UNDERFLOW_LOW = 0; + parameter C_VALID_LOW = 0; + parameter C_WR_ACK_LOW = 0; + parameter C_WR_DATA_COUNT_WIDTH = 2; + parameter C_WR_DEPTH = 256; + parameter C_WR_PNTR_WIDTH = 8; + parameter C_WR_RESPONSE_LATENCY = 1; + + +/****************************************************************************** + * Declare Input and Output Ports + *****************************************************************************/ + input CLK; + input [C_DIN_WIDTH-1:0] DIN; + input [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH; + input [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_ASSERT; + input [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_NEGATE; + input [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH; + input [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_ASSERT; + input [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_NEGATE; + input RD_EN; + input RST; + //Added Synchronous Reset feature for v3.2 (IP2_Im) + input SRST; + input WR_EN; + output ALMOST_EMPTY; + output ALMOST_FULL; + output [C_DATA_COUNT_WIDTH-1:0] DATA_COUNT; + output [C_DOUT_WIDTH-1:0] DOUT; + output EMPTY; + output FULL; + output OVERFLOW; + output PROG_EMPTY; + output PROG_FULL; + output VALID; + output UNDERFLOW; + output WR_ACK; + +/******************************************************************************* + * Input and output register declarations + ******************************************************************************/ +/******************************************************************************* + * Parameters used as constants + ******************************************************************************/ + //When RST is present, set FULL reset value to '1'. + //If core has no RST, make sure FULL powers-on as '0'. + //The reset value assignments for FULL, ALMOST_FULL, and PROG_FULL are not + //changed for v3.2(IP2_Im). When the core has Sync Reset, C_HAS_SRST=1 and C_HAS_RST=0. + // Therefore, during SRST, all the FULL flags reset to 0. + parameter C_FULL_RESET_VAL = C_HAS_RST; + parameter C_ALMOST_FULL_RESET_VAL = C_HAS_RST; + parameter C_PROG_FULL_RESET_VAL = C_HAS_RST; + parameter C_HAS_FAST_FIFO = 0; + parameter C_FIFO_WR_DEPTH = (C_HAS_FAST_FIFO || (C_PRELOAD_REGS && C_PRELOAD_LATENCY) || C_COMMON_CLOCK) ? C_WR_DEPTH : C_WR_DEPTH - 1; + parameter C_FIFO_RD_DEPTH = (C_HAS_FAST_FIFO || (C_PRELOAD_REGS && C_PRELOAD_LATENCY) || C_COMMON_CLOCK) ? C_RD_DEPTH : C_RD_DEPTH - 1; + + /**************************************************************************** + * Internal Registers and wires + ***************************************************************************/ + wire wr_ack_i; + wire overflow_i; + wire underflow_i; + wire valid_i; + wire rst_i; + //Added Synchronous Reset feature for v3.2 (IP2_Im) + wire srst_i; + + + //Memory which will be used to simulate a FIFO + reg [C_DIN_WIDTH-1:0] memory[C_WR_DEPTH-1:0]; + reg [31:0] num_bits; + reg [31:0] wr_ptr; + reg [31:0] rd_ptr; + wire [31:0] num_read_words = num_bits/C_DOUT_WIDTH; + reg [31:0] num_read_words_q; + wire [31:0] num_write_words = num_bits/C_DIN_WIDTH; + reg [31:0] num_write_words_q; + //Removed power_on_timer in v3.2 (IP2_Im). For all reset types (Async, Sync, or no reset), the power-on values of the flags in the core are modified so that the core is ready to use from the very first clock cycle. + //reg [3:0] power_on_timer; + + //Special ideal FIFO signals + reg [C_DOUT_WIDTH-1:0] ideal_dout; + reg ideal_wr_ack; + reg ideal_valid; + reg ideal_overflow; + reg ideal_underflow; + reg ideal_full; + reg ideal_empty; + reg ideal_almost_full; + reg ideal_almost_empty; + reg ideal_prog_full; + reg ideal_prog_empty; + + + //MSBs of the counts + wire [C_DATA_COUNT_WIDTH-1:0] ideal_d_count; + + //user specified value for reseting the size of the fifo + reg [C_DOUT_WIDTH-1:0] dout_reset_val; + + + //temporary registers for WR_RESPONSE_LATENCY feature + reg ideal_wr_ack_q; + reg ideal_overflow_q; + + reg prog_full_d; + reg prog_empty_d; + + //Delayed version of RST + reg rst_q; + reg rst_qq; + + /**************************************************************************** + * Function Declarations + ***************************************************************************/ + task write_fifo; + begin + memory[wr_ptr] <= DIN; + if (wr_ptr == 0) begin + wr_ptr <= C_WR_DEPTH - 1; + end else begin + wr_ptr <= wr_ptr - 1; + end + end + endtask // write_fifo + + task read_fifo; + begin + ideal_dout <= memory[rd_ptr]; + if (rd_ptr == 0) begin + rd_ptr <= C_RD_DEPTH - 1; + end else begin + rd_ptr <= rd_ptr - 1; + end + end + endtask + + /**************************************************************************** + * log2_val + * Returns the 'log2' value for the input value for the supported ratios + ***************************************************************************/ + function [31:0] log2_val; + input [31:0] binary_val; + + begin + if (binary_val == 8) begin + log2_val = 3; + end else if (binary_val == 4) begin + log2_val = 2; + end else begin + log2_val = 1; + end + end + endfunction + + /**************************************************************************** + * hexstr_conv + * Converts a string of type hex to a binary value (for C_DOUT_RST_VAL) + ***************************************************************************/ + function [C_DOUT_WIDTH-1:0] hexstr_conv; + input [(C_DOUT_WIDTH*8)-1:0] def_data; + + integer index,i,j; + reg [3:0] bin; + + begin + index = 0; + hexstr_conv = 'b0; + for( i=C_DOUT_WIDTH-1; i>=0; i=i-1 ) + begin + case (def_data[7:0]) + 8'b00000000 : + begin + bin = 4'b0000; + i = -1; + end + 8'b00110000 : bin = 4'b0000; + 8'b00110001 : bin = 4'b0001; + 8'b00110010 : bin = 4'b0010; + 8'b00110011 : bin = 4'b0011; + 8'b00110100 : bin = 4'b0100; + 8'b00110101 : bin = 4'b0101; + 8'b00110110 : bin = 4'b0110; + 8'b00110111 : bin = 4'b0111; + 8'b00111000 : bin = 4'b1000; + 8'b00111001 : bin = 4'b1001; + 8'b01000001 : bin = 4'b1010; + 8'b01000010 : bin = 4'b1011; + 8'b01000011 : bin = 4'b1100; + 8'b01000100 : bin = 4'b1101; + 8'b01000101 : bin = 4'b1110; + 8'b01000110 : bin = 4'b1111; + 8'b01100001 : bin = 4'b1010; + 8'b01100010 : bin = 4'b1011; + 8'b01100011 : bin = 4'b1100; + 8'b01100100 : bin = 4'b1101; + 8'b01100101 : bin = 4'b1110; + 8'b01100110 : bin = 4'b1111; + default : + begin + bin = 4'bx; + end + endcase + for( j=0; j<4; j=j+1) + begin + if ((index*4)+j < C_DOUT_WIDTH) + begin + hexstr_conv[(index*4)+j] = bin[j]; + end + end + index = index + 1; + def_data = def_data >> 8; + end + end + endfunction + + /***************************************************************************** + * Initialize Signals + ****************************************************************************/ + initial begin + num_bits = 0; + num_read_words_q = 0; + num_write_words_q = 0; + rd_ptr = C_RD_DEPTH -1; + wr_ptr = C_WR_DEPTH -1; + dout_reset_val = hexstr_conv(C_DOUT_RST_VAL); + if (C_MEMORY_TYPE == 1) begin + ideal_dout = dout_reset_val; + end else begin + ideal_dout = 0; + end + ideal_wr_ack = 1'b0; + ideal_valid = 1'b0; + ideal_overflow = 1'b0; + ideal_underflow = 1'b0; + //Modified the start-up value of FULL to '0' in v3.2 (IP2_Im) + //ideal_full = C_FULL_RESET_VAL; //was in v3.1 + ideal_full = 1'b0; //v3.2 + ideal_empty = 1'b1; + //Modified the start-up value of ALMOST_FULL to '0' in v3.2 (IP2_Im) + //ideal_almost_full = C_ALMOST_FULL_RESET_VAL; //was in v3.1 + ideal_almost_full = 1'b0; + ideal_almost_empty = 1'b1; + //Modified the start-up value of PROG_FULL to '0' in v3.2 (IP2_Im) + //ideal_prog_full = C_PROG_FULL_RESET_VAL; //was in v3.1 + ideal_prog_full = 1'b0; //v3.2 + ideal_prog_empty = 1'b1; + + //Modified the start-up value of PROG_FULL to '0' in v3.2 (IP2_Im) + //Therefore, prog_full_d is also changed + //prog_full_d = C_PROG_FULL_RESET_VAL; //was in v3.1 + prog_full_d = 1'b0; //v3.2 + prog_empty_d = 1'b1; + + //Removed in v3.2 + //power_on_timer = C_HAS_RST ? 4'h3 : 4'h0; + + //Added these initial values in v3.2 to make it consistent with the synchronization flop stages in the core. + rst_q = 1'b0; + rst_qq = 1'b0; + end + + + /***************************************************************************** + * Assign Internal ideal signals to output ports + ****************************************************************************/ + assign DOUT = ideal_dout; + //was in v3.1 + //assign FULL = (power_on_timer) ? C_FULL_RESET_VAL : ideal_full; + //v3.2 + assign FULL = ideal_full; + + assign EMPTY = ideal_empty; + //was in v3.1 + //assign ALMOST_FULL = (power_on_timer) ? C_ALMOST_FULL_RESET_VAL : ideal_almost_full; + //v3.2 + assign ALMOST_FULL = ideal_almost_full; + + assign ALMOST_EMPTY = ideal_almost_empty; + + assign ideal_d_count = num_read_words[C_RD_PNTR_WIDTH-1:C_RD_PNTR_WIDTH-C_DATA_COUNT_WIDTH]; + assign DATA_COUNT = ideal_d_count; + + //was in v3.1 + //assign PROG_FULL = (power_on_timer) ? C_PROG_FULL_RESET_VAL : ideal_prog_full; + //v3.2 + assign PROG_FULL = ideal_prog_full; + + assign PROG_EMPTY = ideal_prog_empty; + + //Handshaking signals can be active low, depending on _LOW parameters + assign valid_i = (C_PRELOAD_LATENCY==0) ? (RD_EN & ~EMPTY) : ideal_valid; + assign VALID = valid_i ? !C_VALID_LOW : C_VALID_LOW; + assign underflow_i = (C_PRELOAD_LATENCY==0) ? (RD_EN & EMPTY) : ideal_underflow; + assign UNDERFLOW = underflow_i ? !C_UNDERFLOW_LOW : C_UNDERFLOW_LOW; + + assign WR_ACK = wr_ack_i ? !C_WR_ACK_LOW : C_WR_ACK_LOW; + assign wr_ack_i = (C_WR_RESPONSE_LATENCY==2) ? ideal_wr_ack_q : + (C_WR_RESPONSE_LATENCY==1) ? ideal_wr_ack : + (WR_EN & !FULL); + assign OVERFLOW = overflow_i ? !C_OVERFLOW_LOW : C_OVERFLOW_LOW; + assign overflow_i = (C_WR_RESPONSE_LATENCY==2) ? ideal_overflow_q : + (C_WR_RESPONSE_LATENCY==1) ? ideal_overflow : + (WR_EN & FULL); + + assign rst_i = C_HAS_RST ? RST : 0; + //Added Synchronous Reset feature for v3.2 (IP2_Im) + assign srst_i = C_HAS_SRST ? SRST : 0; + + + always @(posedge CLK or posedge rst_i) + begin : gen_wr_ack_resp + + //Register reset + rst_q <= rst_i; + rst_qq <= rst_q; + + //Register output signals to achieve desired WR_RESPONSE latency + if (C_WR_RESPONSE_LATENCY == 2) begin + if (rst_i == 1) begin + ideal_wr_ack_q <= 0; + ideal_overflow_q <= 0; + end else begin + ideal_wr_ack_q <= ideal_wr_ack; + ideal_overflow_q <= ideal_overflow; + end + end + + //Removed in v3.2 + /* + if (rst_i == 1) begin + power_on_timer <= 0; + end else if (power_on_timer > 0) begin + power_on_timer <= power_on_timer -1; + end else begin + power_on_timer <= 0; + end + */ + end // block: gen_wr_ack_resp + + // block memory has a synchronous reset + //Added Synchronous Reset feature (for the core) for v3.2 (IP2_Im) + always @(posedge CLK) begin : gen_fifo_blkmemdout + //Changed the latency of during async reset to '1' instead of '2' to make it consistent with the core. + //if (rst_i || rst_q || rst_qq) begin //was in v3.1 + if (rst_i || rst_q || srst_i) begin //v3.2 + /******Initialize Read Domain Signals************************************/ + if (C_MEMORY_TYPE == 1) begin + ideal_dout <= dout_reset_val; + end + //v3.2 + //end else begin + //if (C_MEMORY_TYPE == 1 && power_on_timer >= 2) begin //was in v3.1 + // if (C_MEMORY_TYPE == 1) begin //v3.2 + // ideal_dout <= dout_reset_val; + // end + end + end + + always @(posedge CLK or posedge rst_i) begin : gen_fifo + + /****** Reset fifo - Asynchronous Reset*************************************/ + //Changed the latency of during async reset to '1' instead of '2' to make it consistent with the core. + //if (rst_i || rst_q || rst_qq) begin //was in v3.1 + if (rst_i || rst_q) begin //v3.2 + /******Initialize Generic FIFO constructs********************************/ + num_bits <= 0; + wr_ptr <= C_WR_DEPTH - 1; + rd_ptr <= C_RD_DEPTH - 1; + num_read_words_q <= 0; + num_write_words_q <= 0; + + + /******Initialize Write Domain Signals***********************************/ + ideal_wr_ack <= 0; + //Overflow reports an overflow error when a user writes to a + // Full FIFO, even if the core is in RESET + ideal_overflow <= WR_EN & ideal_full; + ideal_full <= C_FULL_RESET_VAL; + ideal_almost_full <= C_ALMOST_FULL_RESET_VAL; + + /******Initialize Read Domain Signals************************************/ + if (C_MEMORY_TYPE != 1) begin + ideal_dout <= dout_reset_val; + end + ideal_valid <= 1'b0; + //Underflow reports an underflow error when a user reads from an + // Empty FIFO, even if the core is in RESET + ideal_underflow <= ideal_empty & RD_EN; + ideal_empty <= 1'b1; + ideal_almost_empty <= 1'b1; + + end else begin + /****** Reset fifo - Synchronous Reset. Added for v3.2(IP2_Im) ********/ + if (srst_i) begin + // SRST is available only for Sync BRAM and Sync DRAM. Not for SSHFT. + if (C_MEMORY_TYPE == 1 || C_MEMORY_TYPE == 2) begin + /******Initialize Generic FIFO constructs********************************/ + num_bits <= 0; + wr_ptr <= C_WR_DEPTH - 1; + rd_ptr <= C_RD_DEPTH - 1; + num_read_words_q <= 0; + num_write_words_q <= 0; + + /******Initialize Write Domain Signals***********************************/ + ideal_wr_ack <= 0; + //Overflow reports an overflow error when a user writes to a + // Full FIFO, even if the core is in RESET + ideal_overflow <= WR_EN & ideal_full; + ideal_full <= C_FULL_RESET_VAL; //'0' + ideal_almost_full <= C_ALMOST_FULL_RESET_VAL; //'0' + + /******Initialize Read Domain Signals************************************/ + //Reset DOUT of Sync DRAM. Sync BRAM DOUT was reset in the above always block. + if (C_MEMORY_TYPE == 2) begin + ideal_dout <= dout_reset_val; + end + ideal_valid <= 1'b0; + //Underflow reports an underflow error when a user reads from an + // Empty FIFO, even if the core is in RESET + ideal_underflow <= ideal_empty & RD_EN; + ideal_empty <= 1'b1; + ideal_almost_empty <= 1'b1; + end + + end else begin //normal operating conditions + /**********************************************************************/ + // Synchronous FIFO Condition #1 : Writing and not reading + /**********************************************************************/ + if (WR_EN & ~RD_EN) begin + + /*********************************/ + //If the FIFO is full, do NOT perform the write, + // update flags accordingly + /*********************************/ + if (num_write_words >= C_FIFO_WR_DEPTH) begin + //overflow condition + ideal_overflow <= 1; + ideal_wr_ack <= 0; + + //still full + ideal_full <= 1'b1; + ideal_almost_full <= 1'b1; + + //write unsuccessful - do not change contents + + // no read attempted + ideal_valid <= 1'b0; + ideal_underflow <= 1'b0; + + //Not near empty + ideal_empty <= 1'b0; + ideal_almost_empty <= 1'b0; + + + /*********************************/ + //If the FIFO is reporting FULL + // (Startup condition) + /*********************************/ + end else if ((num_write_words < C_FIFO_WR_DEPTH) && (ideal_full == 1'b1)) begin + //overflow condition + ideal_overflow <= 1; + ideal_wr_ack <= 0; + + //still full + ideal_full <= 1'b0; + ideal_almost_full <= 1'b0; + + //write unsuccessful - do not change contents + + // no read attempted + ideal_valid <= 1'b0; + ideal_underflow <= 1'b0; + + //FIFO EMPTY in this state can not be determined + //ideal_empty <= 1'b0; + //ideal_almost_empty <= 1'b0; + + + /*********************************/ + //If the FIFO is one from full + /*********************************/ + end else if (num_write_words == C_FIFO_WR_DEPTH-1) begin + //good write + ideal_overflow <= 0; + ideal_wr_ack <= 1; + + //FIFO is one from FULL and going FULL + ideal_full <= 1'b1; + ideal_almost_full <= 1'b1; + + //Add input data + write_fifo; + + // no read attempted + ideal_valid <= 1'b0; + ideal_underflow <= 1'b0; + + //Not near empty + ideal_empty <= 1'b0; + ideal_almost_empty <= 1'b0; + + num_bits <= num_bits + C_DIN_WIDTH; + + /*********************************/ + //If the FIFO is 2 from full + /*********************************/ + end else if (num_write_words == C_FIFO_WR_DEPTH-2) begin + //good write + ideal_overflow <= 0; + ideal_wr_ack <= 1; + + //2 from full, and writing, so set almost_full + ideal_full <= 1'b0; + ideal_almost_full <= 1'b1; + + //Add input data + write_fifo; + + //no read attempted + ideal_valid <= 1'b0; + ideal_underflow <= 1'b0; + + //Not near empty + ideal_empty <= 1'b0; + ideal_almost_empty <= 1'b0; + + num_bits <= num_bits + C_DIN_WIDTH; + + /*********************************/ + //If the FIFO is ALMOST EMPTY + /*********************************/ + end else if (num_read_words == 1) begin + //good write + ideal_overflow <= 0; + ideal_wr_ack <= 1; + + //Not near FULL + ideal_full <= 1'b0; + ideal_almost_full <= 1'b0; + + //Add input data + write_fifo; + + // no read attempted + ideal_valid <= 1'b0; + ideal_underflow <= 1'b0; + + //Leaving ALMOST_EMPTY + ideal_empty <= 1'b0; + ideal_almost_empty <= 1'b0; + + num_bits <= num_bits + C_DIN_WIDTH; + + /*********************************/ + //If the FIFO is EMPTY + /*********************************/ + end else if (num_read_words == 0) begin + // good write + ideal_overflow <= 0; + ideal_wr_ack <= 1; + + //Not near FULL + ideal_full <= 1'b0; + ideal_almost_full <= 1'b0; + + //Add input data + write_fifo; + + // no read attempted + ideal_valid <= 1'b0; + ideal_underflow <= 1'b0; + + //Leaving EMPTY (still ALMOST_EMPTY) + ideal_empty <= 1'b0; + ideal_almost_empty <= 1'b1; + + num_bits <= num_bits + C_DIN_WIDTH; + + /*********************************/ + //If the FIFO is not near EMPTY or FULL + /*********************************/ + end else begin + // good write + ideal_overflow <= 0; + ideal_wr_ack <= 1; + + //Not near FULL + ideal_full <= 1'b0; + ideal_almost_full <= 1'b0; + + //Add input data + write_fifo; + + // no read attempted + ideal_valid <= 1'b0; + ideal_underflow <= 1'b0; + + //Not near EMPTY + ideal_empty <= 1'b0; + ideal_almost_empty <= 1'b0; + + num_bits <= num_bits + C_DIN_WIDTH; + + end // average case + + + /**********************************************************************/ + // Synchronous FIFO Condition #2 : Reading and not writing + /**********************************************************************/ + end else if (~WR_EN & RD_EN) begin + + /*********************************/ + //If the FIFO is EMPTY + /*********************************/ + if ((num_read_words == 0) || (ideal_empty == 1'b1)) begin + //no write attemped + ideal_overflow <= 0; + ideal_wr_ack <= 0; + + //FIFO is not near FULL + ideal_full <= 1'b0; + ideal_almost_full <= 1'b0; + + //Read will fail + ideal_valid <= 1'b0; + ideal_underflow <= 1'b1; + + //FIFO is still empty + ideal_empty <= 1'b1; + ideal_almost_empty <= 1'b1; + + //No read + + /*********************************/ + //If the FIFO is ALMOST EMPTY + /*********************************/ + end else if (num_read_words == 1) begin + //no write attempted + ideal_overflow <= 0; + ideal_wr_ack <= 0; + + //FIFO is not near FULL + ideal_full <= 1'b0; + ideal_almost_full <= 1'b0; + + //Read successful + ideal_valid <= 1'b1; + ideal_underflow <= 1'b0; + + //This read will make FIFO go empty + ideal_empty <= 1'b1; + ideal_almost_empty <= 1'b1; + + //Get the data from the FIFO + read_fifo; + num_bits <= num_bits - C_DIN_WIDTH; + + + /*********************************/ + //If the FIFO is 2 from EMPTY + /*********************************/ + end else if (num_read_words == 2) begin + + //no write attempted + ideal_overflow <= 0; + ideal_wr_ack <= 0; + + //FIFO is not near FULL + ideal_full <= 1'b0; + ideal_almost_full <= 1'b0; + + //Read successful + ideal_valid <= 1'b1; + ideal_underflow <= 1'b0; + + //FIFO is going ALMOST_EMPTY + ideal_empty <= 1'b0; + ideal_almost_empty <= 1'b1; + + //Get the data from the FIFO + read_fifo; + num_bits <= num_bits - C_DOUT_WIDTH; + + + + /*********************************/ + //If the FIFO is one from full + /*********************************/ + end else if (num_write_words == C_FIFO_WR_DEPTH-1) begin + + //no write attempted + ideal_overflow <= 0; + ideal_wr_ack <= 0; + + //FIFO is leaving ALMOST FULL + ideal_full <= 1'b0; + ideal_almost_full <= 1'b0; + + //Read successful + ideal_valid <= 1'b1; + ideal_underflow <= 1'b0; + + //Not near empty + ideal_empty <= 1'b0; + ideal_almost_empty <= 1'b0; + + //Read from the FIFO + read_fifo; + num_bits <= num_bits - C_DOUT_WIDTH; + + + /*********************************/ + // FIFO is FULL + /*********************************/ + end else if (num_write_words >= C_FIFO_WR_DEPTH) + begin + //no write attempted + ideal_overflow <= 0; + ideal_wr_ack <= 0; + + //FIFO is leaving FULL, but is still ALMOST_FULL + ideal_full <= 1'b0; + ideal_almost_full <= 1'b1; + + //Read successful + ideal_valid <= 1'b1; + ideal_underflow <= 1'b0; + + //Not near empty + ideal_empty <= 1'b0; + ideal_almost_empty <= 1'b0; + + //Read from the FIFO + read_fifo; + num_bits <= num_bits - C_DOUT_WIDTH; + + /*********************************/ + //If the FIFO is not near EMPTY or FULL + /*********************************/ + end else begin + //no write attemped + ideal_overflow <= 0; + ideal_wr_ack <= 0; + + //Not near empty + ideal_full <= 1'b0; + ideal_almost_full <= 1'b0; + + //Read successful + ideal_valid <= 1'b1; + ideal_underflow <= 1'b0; + + //Not near empty + ideal_empty <= 1'b0; + ideal_almost_empty <= 1'b0; + + //Read from the FIFO + read_fifo; + num_bits <= num_bits - C_DOUT_WIDTH; + + + end // average read + + + /**********************************************************************/ + // Synchronous FIFO Condition #3 : Reading and writing + /**********************************************************************/ + end else if (WR_EN & RD_EN) begin + + /*********************************/ + // FIFO is FULL + /*********************************/ + if (num_write_words >= C_FIFO_WR_DEPTH) begin + + //throw an overflow --> netlist has latency on read + ideal_overflow <= 1; + ideal_wr_ack <= 0; + + //Read will be successful, so FIFO will leave FULL + ideal_full <= 1'b0; + ideal_almost_full <= 1'b1; + + //Read successful + ideal_valid <= 1'b1; + ideal_underflow <= 1'b0; + + //Not near empty + ideal_empty <= 1'b0; + ideal_almost_empty <= 1'b0; + + //Read from the FIFO + read_fifo; + num_bits <= num_bits - C_DOUT_WIDTH; + + + /*********************************/ + // FIFO is reporting FULL, but it is empty + // (This is a special case, when coming out of RST + /*********************************/ + end else if ((num_write_words == 0) && (ideal_full == 1'b1)) begin + + //throw an overflow --> netlist has latency on read + ideal_overflow <= 1; + ideal_wr_ack <= 0; + + //Read will be successful, so FIFO will leave FULL + ideal_full <= 1'b0; + ideal_almost_full <= 1'b0; + + //Read unsuccessful + ideal_valid <= 1'b0; + ideal_underflow <= 1'b1; + + //Report empty condition + ideal_empty <= 1'b1; + ideal_almost_empty <= 1'b1; + + //Do not read from empty FIFO + // Read from the FIFO + + + /*********************************/ + //If the FIFO is one from full + /*********************************/ + end else if (num_write_words == C_FIFO_WR_DEPTH-1) begin + + //Write successful + ideal_overflow <= 0; + ideal_wr_ack <= 1; + + //FIFO will remain ALMOST_FULL + ideal_full <= 1'b0; + ideal_almost_full <= 1'b1; + + // put the data into the FIFO + write_fifo; + + //Read successful + ideal_valid <= 1'b1; + ideal_underflow <= 1'b0; + + //Not near empty + ideal_empty <= 1'b0; + ideal_almost_empty <= 1'b0; + + //Read from the FIFO + read_fifo; + num_bits <= num_bits + C_DIN_WIDTH - C_DOUT_WIDTH; + + /*********************************/ + //If the FIFO is ALMOST EMPTY + /*********************************/ + end else if (num_read_words == 1) begin + + //Write successful + ideal_overflow <= 0; + ideal_wr_ack <= 1; + + // Not near FULL + ideal_full <= 1'b0; + ideal_almost_full <= 1'b0; + + // put the data into the FIFO + write_fifo; + + //Read successful + ideal_valid <= 1'b1; + ideal_underflow <= 1'b0; + + //FIFO will stay ALMOST_EMPTY + ideal_empty <= 1'b0; + ideal_almost_empty <= 1'b1; + + //Read from the FIFO + read_fifo; + num_bits <= num_bits + C_DIN_WIDTH - C_DOUT_WIDTH; + + + /*********************************/ + //If the FIFO is EMPTY + /*********************************/ + end else if (num_read_words == 0) begin + + //Write successful + ideal_overflow <= 0; + ideal_wr_ack <= 1; + + // Not near FULL + ideal_full <= 1'b0; + ideal_almost_full <= 1'b0; + + // put the data into the FIFO + write_fifo; + + //Read will fail + ideal_valid <= 1'b0; + ideal_underflow <= 1'b1; + + //FIFO will leave EMPTY + ideal_empty <= 1'b0; + ideal_almost_empty <= 1'b1; + + // No read + num_bits <= num_bits + C_DIN_WIDTH; + + + /*********************************/ + //If the FIFO is not near EMPTY or FULL + /*********************************/ + end else begin + + //Write successful + ideal_overflow <= 0; + ideal_wr_ack <= 1; + + // Not near FULL + ideal_full <= 1'b0; + ideal_almost_full <= 1'b0; + + // put the data into the FIFO + write_fifo; + + //Read successful + ideal_valid <= 1'b1; + ideal_underflow <= 1'b0; + + // Not near EMPTY + ideal_empty <= 1'b0; + ideal_almost_empty <= 1'b0; + + //Read from the FIFO + read_fifo; + num_bits <= num_bits + C_DIN_WIDTH - C_DOUT_WIDTH; + + end // average case + + /**********************************************************************/ + // Synchronous FIFO Condition #4 : Not reading or writing + /*** + *******************************************************************/ + end else begin + + /*********************************/ + // FIFO is FULL + /*********************************/ + if (num_write_words >= C_FIFO_WR_DEPTH) begin + + //No write + ideal_overflow <= 0; + ideal_wr_ack <= 0; + ideal_full <= 1'b1; + ideal_almost_full <= 1'b1; + + //No read + ideal_valid <= 1'b0; + ideal_underflow <= 1'b0; + ideal_empty <= 1'b0; + ideal_almost_empty <= 1'b0; + + //No change to memory + + /*********************************/ + //If the FIFO is one from full + /*********************************/ + end else if (num_write_words == C_FIFO_WR_DEPTH-1) begin + + //No write + ideal_overflow <= 0; + ideal_wr_ack <= 0; + ideal_full <= 1'b0; + ideal_almost_full <= 1'b1; + + //No read + ideal_valid <= 1'b0; + ideal_underflow <= 1'b0; + ideal_empty <= 1'b0; + ideal_almost_empty <= 1'b0; + + //No change to memory + + /*********************************/ + //If the FIFO is ALMOST EMPTY + /*********************************/ + end else if (num_read_words == 1) begin + //No write + ideal_overflow <= 0; + ideal_wr_ack <= 0; + ideal_full <= 1'b0; + ideal_almost_full <= 1'b0; + + //No read + ideal_valid <= 1'b0; + ideal_underflow <= 1'b0; + ideal_empty <= 1'b0; + ideal_almost_empty <= 1'b1; + + //No change to memory + + end // almost empty + + + /*********************************/ + //If the FIFO is EMPTY + /*********************************/ + else if (num_read_words == 0) + begin + //No write + ideal_overflow <= 0; + ideal_wr_ack <= 0; + ideal_full <= 1'b0; + ideal_almost_full <= 1'b0; + + //No read + ideal_valid <= 1'b0; + ideal_underflow <= 1'b0; + ideal_empty <= 1'b1; + ideal_almost_empty <= 1'b1; + + //No change to memory + + /*********************************/ + //If the FIFO is not near EMPTY or FULL + /*********************************/ + end else begin + + //No write + ideal_overflow <= 0; + ideal_wr_ack <= 0; + ideal_full <= 1'b0; + ideal_almost_full <= 1'b0; + + //No read + ideal_valid <= 1'b0; + ideal_underflow <= 1'b0; + ideal_empty <= 1'b0; + ideal_almost_empty <= 1'b0; + + //No change to memory + + end // average case + + end // neither reading or writing + + num_read_words_q <= num_read_words; + num_write_words_q <= num_write_words; + + end //normal operating conditions + end + + end // block: gen_fifo + + always @(posedge CLK or posedge rst_i) begin : gen_fifo_p + + /****** Reset fifo - Async Reset****************************************/ + //The latency of de-assertion of the flags is reduced by 1 to be consistent with the core. + //if (rst_i || rst_q) begin //was in v3.1 + if (rst_i) begin //v3.2 + ideal_prog_full <= C_PROG_FULL_RESET_VAL; + ideal_prog_empty <= 1'b1; + prog_full_d <= C_PROG_FULL_RESET_VAL; + prog_empty_d <= 1'b1; + + end else begin + /****** Reset fifo - Sync Reset. Added for v3.2(IP2_Im)************/ + if (srst_i) begin + //SRST is available only for Sync BRAM and Sync DRAM. Not for SSHFT. + if (C_MEMORY_TYPE == 1 || C_MEMORY_TYPE == 2) begin + ideal_prog_full <= C_PROG_FULL_RESET_VAL; + ideal_prog_empty <= 1'b1; + prog_full_d <= C_PROG_FULL_RESET_VAL; + prog_empty_d <= 1'b1; + end + end else begin + + /***************************************************************** + * Programmable FULL flags + ****************************************************************/ + if (C_PROG_FULL_TYPE == 1) begin + //If we are at or above the PROG_FULL_THRESH, or we will + //be next clock cycle, then assert PROG_FULL + //The latency of de-assertion of the flag is reduced by 1 to be consistent with the core. + //if (((num_write_words == C_PROG_FULL_THRESH_ASSERT_VAL) + // && RD_EN && !WR_EN) || (rst_qq && !rst_q)) begin //was in v3.1 + if (((num_write_words == C_PROG_FULL_THRESH_ASSERT_VAL) + && RD_EN && !WR_EN) || (rst_q && !rst_i)) begin //v3.2 + prog_full_d <= 1'b0; + end else if ((num_write_words == C_PROG_FULL_THRESH_ASSERT_VAL) || + ((num_write_words >= C_PROG_FULL_THRESH_ASSERT_VAL-1) + && WR_EN && !RD_EN)) begin + prog_full_d <= 1'b1; + end + end else if (C_PROG_FULL_TYPE == 2) begin + // If we will be going at or above the + // C_PROG_FULL_ASSERT threshold on the next clock cycle, + // then assert PROG_FULL + if ((num_write_words >= C_PROG_FULL_THRESH_ASSERT_VAL-1) + && WR_EN && !RD_EN) begin + prog_full_d <= 1'b1; + // If we will be going below C_PROG_FULL_NEGATE on the + // next clock cycle, then de-assert PROG_FULL + end else if ((num_write_words == C_PROG_FULL_THRESH_NEGATE_VAL) + && RD_EN && !WR_EN) begin + prog_full_d <= 1'b0; + // If we are at or above the C_PROG_FULL_ASSERT, then + // assert PROG_FULL + end else if (num_write_words >= C_PROG_FULL_THRESH_ASSERT_VAL) begin + prog_full_d <= 1'b1; + // If we are below the C_PROG_FULL_NEGATE, then + // de-assert PROG_FULL + end else if (num_write_words < C_PROG_FULL_THRESH_NEGATE_VAL) begin + prog_full_d <= 1'b0; + end + end else if (C_PROG_FULL_TYPE == 3) begin + //If we are at or above the PROG_FULL_THRESH, or we will + //be next clock cycle, then assert PROG_FULL + //The latency of de-assertion of the flag is reduced by 1 to be consistent with the core. + //if (((num_write_words == PROG_FULL_THRESH) && RD_EN + // && !WR_EN) || (rst_qq && !rst_q)) begin //was in v3.1 + if (((num_write_words == PROG_FULL_THRESH) && RD_EN + && !WR_EN) || (rst_q && !rst_i)) begin //v3.2 + prog_full_d <= 1'b0; + end else if ((num_write_words >= PROG_FULL_THRESH) || + ((num_write_words == PROG_FULL_THRESH-1) + && WR_EN && !RD_EN)) begin + prog_full_d <= 1'b1; + end + + end else begin + //If we are at or above the PROG_FULL_THRESH, or we will + //be next clock cycle, then assert PROG_FULL + //The latency of de-assertion of the flag is reduced by 1 to be consistent with the core. + //if (((num_write_words == PROG_FULL_THRESH_NEGATE) + // && RD_EN && !WR_EN) || (rst_qq & !rst_q)) begin //was in v3.1 + if (((num_write_words == PROG_FULL_THRESH_NEGATE) + && RD_EN && !WR_EN) || (rst_q & !rst_i)) begin //v3.2 + prog_full_d <= 1'b0; + end else if (((num_write_words == PROG_FULL_THRESH_ASSERT-1) + && WR_EN && !RD_EN)) begin + prog_full_d <= 1'b1; + end + end + + /***************************************************************** + * Programmable EMPTY flags + ****************************************************************/ + if (C_PROG_EMPTY_TYPE == 1) begin + // If we are at or below the PROG_EMPTY_THRESH, or + // we will be the next clock cycle, then assert + // PROG_EMPTY + if ((num_read_words == C_PROG_EMPTY_THRESH_ASSERT_VAL) + && WR_EN && !RD_EN) begin + prog_empty_d <= 1'b0; + end else if ((num_read_words <= C_PROG_EMPTY_THRESH_ASSERT_VAL) + && WR_EN && RD_EN) begin + prog_empty_d <= 1'b1; + end else if (((num_read_words == C_PROG_EMPTY_THRESH_ASSERT_VAL+1) + && RD_EN && !WR_EN)) begin + prog_empty_d <= 1'b1; + end + end else if (C_PROG_EMPTY_TYPE == 2) begin + // If we will be going at or below the + // C_PROG_EMPTY_ASSERT threshold + //on the next clock cycle, then assert PROG_EMPTY + if ((num_read_words <= C_PROG_EMPTY_THRESH_ASSERT_VAL+1) + && RD_EN) begin + prog_empty_d <= 1'b1; + // If we will be going above C_PROG_EMPTY_NEGATE on the + // next clock cycle, then de-assert PROG_EMPTY + end else if((num_read_words >= C_PROG_EMPTY_THRESH_NEGATE_VAL) + && WR_EN && !RD_EN) begin + prog_empty_d <= 1'b0; + // If we are at or below the C_PROG_EMPTY_ASSERT, then + // assert PROG_EMPTY + end else if (num_read_words <= C_PROG_EMPTY_THRESH_ASSERT_VAL) begin + prog_empty_d <= 1'b1; + // If we are above the C_PROG_EMPTY_NEGATE, then + // de-assert PROG_EMPTY + end else if (num_read_words > C_PROG_EMPTY_THRESH_NEGATE_VAL) begin + prog_empty_d <= 1'b0; + end + end else if (C_PROG_EMPTY_TYPE == 3) begin + // If we are at or below the PROG_EMPTY_THRESH, or + // we will be the next clock cycle, then assert + // PROG_EMPTY + if (((num_read_words == PROG_EMPTY_THRESH) + && WR_EN && !RD_EN)) begin + prog_empty_d <= 1'b0; + end else if ((num_read_words <= PROG_EMPTY_THRESH) + && RD_EN) begin + prog_empty_d <= 1'b1; + end else if (((num_read_words == PROG_EMPTY_THRESH+1) + && RD_EN && !WR_EN)) begin + prog_empty_d <= 1'b1; + end + end else begin + // If we will be going at or below the + // PROG_EMPTY_ASSERT threshold + //on the next clock cycle, then assert PROG_EMPTY + if ((num_read_words == PROG_EMPTY_THRESH_ASSERT+1) + && RD_EN) begin + prog_empty_d <= 1'b1; + // If we will be going above PROG_EMPTY_NEGATE on the + // next clock cycle, then de-assert PROG_EMPTY + end else if ((num_read_words == PROG_EMPTY_THRESH_NEGATE) + && WR_EN && !RD_EN) begin + prog_empty_d <= 1'b0; + // If we are at or below the PROG_EMPTY_ASSERT, then + // assert PROG_EMPTY + end else if (num_read_words <= PROG_EMPTY_THRESH_ASSERT) begin + prog_empty_d <= 1'b1; + // If we are above the PROG_EMPTY_NEGATE, then + // de-assert PROG_EMPTY + end else if (num_read_words > PROG_EMPTY_THRESH_NEGATE) begin + prog_empty_d <= 1'b0; + end + end + ideal_prog_empty <= prog_empty_d; + ideal_prog_full <= prog_full_d; + + end + end + end +endmodule // fifo_generator_v3_3_bhv_ver_ss + + +module fifo_generator_v3_3_bhv_ver_preload0 + ( + RD_CLK, + RD_RST, + RD_EN, + FIFOEMPTY, + FIFODATA, + USERDATA, + USERVALID, + USERUNDERFLOW, + USEREMPTY, + USERALMOSTEMPTY, + RAMVALID, + FIFORDEN + ); + + + parameter C_DOUT_RST_VAL = ""; + parameter C_DOUT_WIDTH = 8; + parameter C_HAS_RST = 0; + parameter C_USERVALID_LOW = 0; + parameter C_USERUNDERFLOW_LOW = 0; + + + input RD_CLK; + input RD_RST; + input RD_EN; + input FIFOEMPTY; + input [C_DOUT_WIDTH-1:0] FIFODATA; + output [C_DOUT_WIDTH-1:0] USERDATA; + output USERVALID; + output USERUNDERFLOW; + output USEREMPTY; + output USERALMOSTEMPTY; + output RAMVALID; + output FIFORDEN; + + wire RD_CLK; + wire RD_RST; + wire RD_EN; + wire FIFOEMPTY; + wire [C_DOUT_WIDTH-1:0] FIFODATA; + reg [C_DOUT_WIDTH-1:0] USERDATA; + wire USERVALID; + wire USERUNDERFLOW; + wire USEREMPTY; + wire USERALMOSTEMPTY; + wire RAMVALID; + wire FIFORDEN; + + wire preloadstage1; + wire preloadstage2; + reg ram_valid_i; + reg read_data_valid_i; + wire ram_regout_en; + wire ram_rd_en; + reg empty_i = 1'b1; + reg empty_q = 1'b1; + reg rd_en_q = 1'b0; //Fix for CR:236270 in v3.2 //prasanna + reg almost_empty_i = 1'b1; + reg almost_empty_q = 1'b1; + wire rd_rst_i; + + +/************************************************************************* +* FUNCTIONS +*************************************************************************/ + + /************************************************************************* + * hexstr_conv + * Converts a string of type hex to a binary value (for C_DOUT_RST_VAL) + ***********************************************************************/ + function [C_DOUT_WIDTH-1:0] hexstr_conv; + input [(C_DOUT_WIDTH*8)-1:0] def_data; + + integer index,i,j; + reg [3:0] bin; + + begin + index = 0; + hexstr_conv = 'b0; + for( i=C_DOUT_WIDTH-1; i>=0; i=i-1 ) + begin + case (def_data[7:0]) + 8'b00000000 : + begin + bin = 4'b0000; + i = -1; + end + 8'b00110000 : bin = 4'b0000; + 8'b00110001 : bin = 4'b0001; + 8'b00110010 : bin = 4'b0010; + 8'b00110011 : bin = 4'b0011; + 8'b00110100 : bin = 4'b0100; + 8'b00110101 : bin = 4'b0101; + 8'b00110110 : bin = 4'b0110; + 8'b00110111 : bin = 4'b0111; + 8'b00111000 : bin = 4'b1000; + 8'b00111001 : bin = 4'b1001; + 8'b01000001 : bin = 4'b1010; + 8'b01000010 : bin = 4'b1011; + 8'b01000011 : bin = 4'b1100; + 8'b01000100 : bin = 4'b1101; + 8'b01000101 : bin = 4'b1110; + 8'b01000110 : bin = 4'b1111; + 8'b01100001 : bin = 4'b1010; + 8'b01100010 : bin = 4'b1011; + 8'b01100011 : bin = 4'b1100; + 8'b01100100 : bin = 4'b1101; + 8'b01100101 : bin = 4'b1110; + 8'b01100110 : bin = 4'b1111; + default : + begin + bin = 4'bx; + end + endcase + for( j=0; j<4; j=j+1) + begin + if ((index*4)+j < C_DOUT_WIDTH) + begin + hexstr_conv[(index*4)+j] = bin[j]; + end + end + index = index + 1; + def_data = def_data >> 8; + end + end + endfunction + +initial + begin + ram_valid_i = 1'b0; + read_data_valid_i = 1'b0; + USERDATA = hexstr_conv(C_DOUT_RST_VAL); + end + + + //****************************************************************************** + // connect up optional reset + //****************************************************************************** + assign rd_rst_i = C_HAS_RST ? RD_RST : 0; + + + //****************************************************************************** + // preloadstage2 indicates that stage2 needs to be updated. This is true + // whenever read_data_valid is false, and RAM_valid is true. + //****************************************************************************** + assign preloadstage2 = ram_valid_i & (~read_data_valid_i | RD_EN); + + //****************************************************************************** + // preloadstage1 indicates that stage1 needs to be updated. This is true + // whenever the RAM has data (RAM_EMPTY is false), and either RAM_Valid is + // false (indicating that Stage1 needs updating), or preloadstage2 is active + // (indicating that Stage2 is going to update, so Stage1, therefore, must + // also be updated to keep it valid. + //****************************************************************************** + assign preloadstage1 = ((~ram_valid_i | preloadstage2) & ~FIFOEMPTY); + + //****************************************************************************** + // Calculate RAM_REGOUT_EN + // The output registers are controlled by the ram_regout_en signal. + // These registers should be updated either when the output in Stage2 is + // invalid (preloadstage2), OR when the user is reading, in which case the + // Stage2 value will go invalid unless it is replenished. + //****************************************************************************** + assign ram_regout_en = preloadstage2; + + //****************************************************************************** + // Calculate RAM_RD_EN + // RAM_RD_EN will be asserted whenever the RAM needs to be read in order to + // update the value in Stage1. + // One case when this happens is when preloadstage1=true, which indicates + // that the data in Stage1 or Stage2 is invalid, and needs to automatically + // be updated. + // The other case is when the user is reading from the FIFO, which guarantees + // that Stage1 or Stage2 will be invalid on the next clock cycle, unless it is + // replinished by data from the memory. So, as long as the RAM has data in it, + // a read of the RAM should occur. + //****************************************************************************** + assign ram_rd_en = (RD_EN & ~FIFOEMPTY) | preloadstage1; + + //****************************************************************************** + // Calculate RAMVALID_P0_OUT + // RAMVALID_P0_OUT indicates that the data in Stage1 is valid. + // + // If the RAM is being read from on this clock cycle (ram_rd_en=1), then + // RAMVALID_P0_OUT is certainly going to be true. + // If the RAM is not being read from, but the output registers are being + // updated to fill Stage2 (ram_regout_en=1), then Stage1 will be emptying, + // therefore causing RAMVALID_P0_OUT to be false. + // Otherwise, RAMVALID_P0_OUT will remain unchanged. + //****************************************************************************** + always @ (posedge RD_CLK or posedge rd_rst_i) + begin // PROCESS regout_valid + if (rd_rst_i) // asynchronous reset (active high) + ram_valid_i <= 1'b0; + else + begin + if (ram_rd_en == 1'b1) + ram_valid_i <= 1'b1; + else + if (ram_regout_en == 1'b1) + ram_valid_i <= 1'b0; + else + ram_valid_i <= ram_valid_i; + end //rd_rst_i + end //always + + //****************************************************************************** + // Calculate READ_DATA_VALID + // READ_DATA_VALID indicates whether the value in Stage2 is valid or not. + // Stage2 has valid data whenever Stage1 had valid data and ram_regout_en_i=1, + // such that the data in Stage1 is propogated into Stage2. + //****************************************************************************** + always @ (posedge RD_CLK or posedge rd_rst_i) + begin + if (rd_rst_i) + read_data_valid_i <= 1'b0; + else + read_data_valid_i <= ram_valid_i | (read_data_valid_i & ~RD_EN); + end //always + + + //***************************************************************************** + // Calculate EMPTY + // Defined as the inverse of READ_DATA_VALID + // + // Description: + // + // If read_data_valid_i indicates that the output is not valid, + // and there is no valid data on the output of the ram to preload it + // with, then we will report empty. + // + // If there is no valid data on the output of the ram and we are + // reading, then the FIFO will go empty. + // + //***************************************************************************** + always @ (posedge RD_CLK or posedge rd_rst_i) + begin + if (rd_rst_i) // asynchronous reset (active high) + begin + empty_i <= 1'b1; + empty_q <= 1'b1; + end + else // rising clock edge + begin + empty_i <= (~ram_valid_i & ~read_data_valid_i) | (~ram_valid_i & RD_EN); + empty_q <= empty_i; + end + end //always + + //Fix for CR:236270 //prasanna + //Register RD_EN from user to calculate USERUNDERFLOW. + always @ (posedge RD_CLK or posedge rd_rst_i) + begin + if (rd_rst_i) // asynchronous reset (active high) + begin + rd_en_q <= 1'b0; + end + else // rising clock edge + begin + rd_en_q <= RD_EN; + end + end //always + + + //***************************************************************************** + // Calculate user_almost_empty + // user_almost_empty is defined such that, unless more words are written + // to the FIFO, the next read will cause the FIFO to go EMPTY. + // + // In most cases, whenever the output registers are updated (due to a user + // read or a preload condition), then user_almost_empty will update to + // whatever RAM_EMPTY is. + // + // The exception is when the output is valid, the user is not reading, and + // Stage1 is not empty. In this condition, Stage1 will be preloaded from the + // memory, so we need to make sure user_almost_empty deasserts properly under + // this condition. + //***************************************************************************** + always @ (posedge RD_CLK or posedge rd_rst_i) + begin + if (rd_rst_i) // asynchronous reset (active high) + begin + almost_empty_i <= 1'b1; + almost_empty_q <= 1'b1; + end + else // rising clock edge + begin + if ((ram_regout_en) | (~FIFOEMPTY & read_data_valid_i & ~RD_EN)) + begin + almost_empty_i <= FIFOEMPTY; + end + almost_empty_q <= empty_i; + end + end //always + + + assign USEREMPTY = empty_i; + assign USERALMOSTEMPTY = almost_empty_i; + assign FIFORDEN = ram_rd_en; + assign RAMVALID = ram_valid_i; + assign USERVALID = C_USERVALID_LOW ? ~read_data_valid_i : read_data_valid_i; + //assign USERUNDERFLOW = C_USERUNDERFLOW_LOW ? ~(empty_q & RD_EN) : empty_q & RD_EN; //Bug in v3.1 (CR:236270) + assign USERUNDERFLOW = C_USERUNDERFLOW_LOW ? ~(empty_q & rd_en_q) : empty_q & rd_en_q; //Fix for CR:236270 in v3.2 //prasanna + + always @ (posedge RD_CLK or posedge rd_rst_i) + begin + if (rd_rst_i) // asynchronous reset (active high) + USERDATA <= hexstr_conv(C_DOUT_RST_VAL); + else // rising clock edge + if (ram_regout_en) + USERDATA <= FIFODATA; + end //always + + + + + +endmodule diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/FIFO_GENERATOR_V3_3_XST.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/FIFO_GENERATOR_V3_3_XST.v new file mode 100644 index 0000000..0ebeadb --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/FIFO_GENERATOR_V3_3_XST.v @@ -0,0 +1,305 @@ +/* + * $RDCfile: $ $Revision: 1.7 $ $Date: 2008/09/09 19:56:58 $ + ******************************************************************************* + * + * FIFO Generator v3.3 - Verilog Behavioral Model + * + ******************************************************************************* + * + * Copyright(C) 2006 by Xilinx, Inc. All rights reserved. + * This text/file contains proprietary, confidential + * information of Xilinx, Inc., is distributed under + * license from Xilinx, Inc., and may be used, copied + * and/or disclosed only pursuant to the terms of a valid + * license agreement with Xilinx, Inc. Xilinx hereby + * grants you a license to use this text/file solely for + * design, simulation, implementation and creation of + * design files limited to Xilinx devices or technologies. + * Use with non-Xilinx devices or technologies is expressly + * prohibited and immediately terminates your license unless + * covered by a separate agreement. + * + * Xilinx is providing theis design, code, or information + * "as-is" solely for use in developing programs and + * solutions for Xilinx devices, with no obligation on the + * part of Xilinx to provide support. By providing this design, + * code, or information as one possible implementation of + * this feature, application or standard. Xilinx is making no + * representation that this implementation is free from any + * claims of infringement. You are responsible for obtaining + * any rights you may require for your implementation. + * Xilinx expressly disclaims any warranty whatsoever with + * respect to the adequacy of the implementation, including + * but not limited to any warranties or representations that this + * implementation is free from claims of infringement, implied + * warranties of merchantability or fitness for a particular + * purpose. + * + * Xilinx products are not intended for use in life support + * appliances, devices, or systems. Use in such applications is + * expressly prohibited. + * + * This copyright and support notice must be retained as part + * of this text at all times. (c)Copyright 1995-2006 Xilinx, Inc. + * All rights reserved. + * + ******************************************************************************* + * + * Filename: fifo_generator_v3_3_bhv.v + * + * Description: + * The verilog behavioral model for the FIFO generator core. + * + ******************************************************************************* + */ + +`timescale 1ps/1ps + +/******************************************************************************* + * Declaration of top-level module + ******************************************************************************/ +module FIFO_GENERATOR_V3_3_XST + ( + BACKUP, + BACKUP_MARKER, + CLK, + DIN, + PROG_EMPTY_THRESH, + PROG_EMPTY_THRESH_ASSERT, + PROG_EMPTY_THRESH_NEGATE, + PROG_FULL_THRESH, + PROG_FULL_THRESH_ASSERT, + PROG_FULL_THRESH_NEGATE, + RD_CLK, + RD_EN, + RD_RST, + RST, + //Added Synchronous Reset feature for v3.2 (IP2_Im) + SRST, + WR_CLK, + WR_EN, + WR_RST, + + ALMOST_EMPTY, + ALMOST_FULL, + DATA_COUNT, + DOUT, + EMPTY, + FULL, + OVERFLOW, + PROG_EMPTY, + PROG_FULL, + RD_DATA_COUNT, + UNDERFLOW, + VALID, + WR_ACK, + WR_DATA_COUNT, + SBITERR, + DBITERR + ); + +/****************************************************************************** + * Definition of Ports + * + * + ***************************************************************************** + * Definition of Parameters + * + * + *****************************************************************************/ + +/****************************************************************************** + * Declare user parameters and their defaults + *****************************************************************************/ + parameter C_COMMON_CLOCK = 0; + parameter C_COUNT_TYPE = 0; + parameter C_DATA_COUNT_WIDTH = 2; + parameter C_DEFAULT_VALUE = ""; + parameter C_DIN_WIDTH = 8; + parameter C_DOUT_RST_VAL = ""; + parameter C_DOUT_WIDTH = 8; + parameter C_ENABLE_RLOCS = 0; + parameter C_FAMILY = "virtex2"; //Not allowed in Verilog model + parameter C_HAS_ALMOST_EMPTY = 0; + parameter C_HAS_ALMOST_FULL = 0; + parameter C_HAS_BACKUP = 0; + parameter C_HAS_DATA_COUNT = 0; + parameter C_HAS_MEMINIT_FILE = 0; + parameter C_HAS_OVERFLOW = 0; + parameter C_HAS_RD_DATA_COUNT = 0; + parameter C_HAS_RD_RST = 0; + parameter C_HAS_RST = 0; + //Added Synchronous Reset feature for v3.2 (IP2_Im) + parameter C_HAS_SRST = 0; + parameter C_HAS_UNDERFLOW = 0; + parameter C_HAS_VALID = 0; + parameter C_HAS_WR_ACK = 0; + parameter C_HAS_WR_DATA_COUNT = 0; + parameter C_HAS_WR_RST = 0; + parameter C_IMPLEMENTATION_TYPE = 0; + parameter C_INIT_WR_PNTR_VAL = 0; + parameter C_MEMORY_TYPE = 1; + parameter C_MIF_FILE_NAME = ""; + parameter C_OPTIMIZATION_MODE = 0; + parameter C_OVERFLOW_LOW = 0; + parameter C_PRELOAD_LATENCY = 1; + parameter C_PRELOAD_REGS = 0; + parameter C_PRIM_FIFO_TYPE = 512; + parameter C_PROG_EMPTY_THRESH_ASSERT_VAL = 0; + parameter C_PROG_EMPTY_THRESH_NEGATE_VAL = 0; + parameter C_PROG_EMPTY_TYPE = 0; + parameter C_PROG_FULL_THRESH_ASSERT_VAL = 0; + parameter C_PROG_FULL_THRESH_NEGATE_VAL = 0; + parameter C_PROG_FULL_TYPE = 0; + parameter C_RD_DATA_COUNT_WIDTH = 2; + parameter C_RD_DEPTH = 256; + parameter C_RD_FREQ = 1; + parameter C_RD_PNTR_WIDTH = 8; + parameter C_UNDERFLOW_LOW = 0; + parameter C_USE_FIFO16_FLAGS = 0; + parameter C_VALID_LOW = 0; + parameter C_WR_ACK_LOW = 0; + parameter C_WR_DATA_COUNT_WIDTH = 2; + parameter C_WR_DEPTH = 256; + parameter C_WR_FREQ = 1; + parameter C_WR_PNTR_WIDTH = 8; + parameter C_WR_RESPONSE_LATENCY = 1; + parameter C_USE_ECC = 0; + + /****************************************************************************** + * Declare Input and Output Ports + *****************************************************************************/ + input CLK; + input BACKUP; + input BACKUP_MARKER; + input [C_DIN_WIDTH-1:0] DIN; + input [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH; + input [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_ASSERT; + input [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_NEGATE; + input [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH; + input [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_ASSERT; + input [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_NEGATE; + input RD_CLK; + input RD_EN; + input RD_RST; + input RST; + //Added Synchronous Reset feature for v3.2 (IP2_Im) + input SRST; + input WR_CLK; + input WR_EN; + input WR_RST; + + output ALMOST_EMPTY; + output ALMOST_FULL; + output [C_DATA_COUNT_WIDTH-1:0] DATA_COUNT; + output [C_DOUT_WIDTH-1:0] DOUT; + output EMPTY; + output FULL; + output OVERFLOW; + output PROG_EMPTY; + output PROG_FULL; + output VALID; + output [C_RD_DATA_COUNT_WIDTH-1:0] RD_DATA_COUNT; + output UNDERFLOW; + output WR_ACK; + output [C_WR_DATA_COUNT_WIDTH-1:0] WR_DATA_COUNT; + output SBITERR; + output DBITERR; + + //Fixed CRS:422807 in v3.2 //prasanna + FIFO_GENERATOR_V3_3 + #( + .C_COMMON_CLOCK (C_COMMON_CLOCK), + .C_COUNT_TYPE (C_COUNT_TYPE), + .C_DATA_COUNT_WIDTH (C_DATA_COUNT_WIDTH), + .C_DEFAULT_VALUE (C_DEFAULT_VALUE), + .C_DIN_WIDTH (C_DIN_WIDTH), + .C_DOUT_RST_VAL (C_DOUT_RST_VAL), + .C_DOUT_WIDTH (C_DOUT_WIDTH), + .C_ENABLE_RLOCS (C_ENABLE_RLOCS), + .C_FAMILY (C_FAMILY),//Not allowed in Verilog model + .C_HAS_ALMOST_EMPTY (C_HAS_ALMOST_EMPTY), + .C_HAS_ALMOST_FULL (C_HAS_ALMOST_FULL), + .C_HAS_BACKUP (C_HAS_BACKUP), + .C_HAS_DATA_COUNT (C_HAS_DATA_COUNT), + .C_HAS_MEMINIT_FILE (C_HAS_MEMINIT_FILE), + .C_HAS_OVERFLOW (C_HAS_OVERFLOW), + .C_HAS_RD_DATA_COUNT (C_HAS_RD_DATA_COUNT), + .C_HAS_RD_RST (C_HAS_RD_RST), + .C_HAS_RST (C_HAS_RST), + //Added Synchronous Reset feature for v3.2 (IP2_Im) + .C_HAS_SRST (C_HAS_SRST), + .C_HAS_UNDERFLOW (C_HAS_UNDERFLOW), + .C_HAS_VALID (C_HAS_VALID), + .C_HAS_WR_ACK (C_HAS_WR_ACK), + .C_HAS_WR_DATA_COUNT (C_HAS_WR_DATA_COUNT), + .C_HAS_WR_RST (C_HAS_WR_RST), + .C_IMPLEMENTATION_TYPE (C_IMPLEMENTATION_TYPE), + .C_INIT_WR_PNTR_VAL (C_INIT_WR_PNTR_VAL), + .C_MEMORY_TYPE (C_MEMORY_TYPE), + .C_MIF_FILE_NAME (C_MIF_FILE_NAME), + .C_OPTIMIZATION_MODE (C_OPTIMIZATION_MODE), + .C_OVERFLOW_LOW (C_OVERFLOW_LOW), + .C_PRELOAD_LATENCY (C_PRELOAD_LATENCY), + .C_PRELOAD_REGS (C_PRELOAD_REGS), + .C_PRIM_FIFO_TYPE (C_PRIM_FIFO_TYPE), + .C_PROG_EMPTY_THRESH_ASSERT_VAL (C_PROG_EMPTY_THRESH_ASSERT_VAL), + .C_PROG_EMPTY_THRESH_NEGATE_VAL (C_PROG_EMPTY_THRESH_NEGATE_VAL), + .C_PROG_EMPTY_TYPE (C_PROG_EMPTY_TYPE), + .C_PROG_FULL_THRESH_ASSERT_VAL (C_PROG_FULL_THRESH_ASSERT_VAL), + .C_PROG_FULL_THRESH_NEGATE_VAL (C_PROG_FULL_THRESH_NEGATE_VAL), + .C_PROG_FULL_TYPE (C_PROG_FULL_TYPE), + .C_RD_DATA_COUNT_WIDTH (C_RD_DATA_COUNT_WIDTH), + .C_RD_DEPTH (C_RD_DEPTH), + .C_RD_FREQ (C_RD_FREQ), + .C_RD_PNTR_WIDTH (C_RD_PNTR_WIDTH), + .C_UNDERFLOW_LOW (C_UNDERFLOW_LOW), + .C_USE_FIFO16_FLAGS (C_USE_FIFO16_FLAGS), + .C_VALID_LOW (C_VALID_LOW), + .C_WR_ACK_LOW (C_WR_ACK_LOW), + .C_WR_DATA_COUNT_WIDTH (C_WR_DATA_COUNT_WIDTH), + .C_WR_DEPTH (C_WR_DEPTH), + .C_WR_FREQ (C_WR_FREQ), + .C_WR_PNTR_WIDTH (C_WR_PNTR_WIDTH), + .C_WR_RESPONSE_LATENCY (C_WR_RESPONSE_LATENCY) + ) + fifo_generator_v3_3_dut + ( + .BACKUP (BACKUP), + .BACKUP_MARKER (BACKUP_MARKER), + .CLK (CLK), + .RST (RST), + //Added Synchronous Reset feature for v3.2 (IP2_Im) + .SRST (SRST), + .WR_CLK (WR_CLK), + .WR_RST (WR_RST), + .RD_CLK (RD_CLK), + .RD_RST (RD_RST), + .DIN (DIN), + .WR_EN (WR_EN), + .RD_EN (RD_EN), + .PROG_EMPTY_THRESH (PROG_EMPTY_THRESH), + .PROG_EMPTY_THRESH_ASSERT (PROG_EMPTY_THRESH_ASSERT), + .PROG_EMPTY_THRESH_NEGATE (PROG_EMPTY_THRESH_NEGATE), + .PROG_FULL_THRESH (PROG_FULL_THRESH), + .PROG_FULL_THRESH_ASSERT (PROG_FULL_THRESH_ASSERT), + .PROG_FULL_THRESH_NEGATE (PROG_FULL_THRESH_NEGATE), + .DOUT (DOUT), + .FULL (FULL), + .ALMOST_FULL (ALMOST_FULL), + .WR_ACK (WR_ACK), + .OVERFLOW (OVERFLOW), + .EMPTY (EMPTY), + .ALMOST_EMPTY (ALMOST_EMPTY), + .VALID (VALID), + .UNDERFLOW (UNDERFLOW), + .DATA_COUNT (DATA_COUNT), + .RD_DATA_COUNT (RD_DATA_COUNT), + .WR_DATA_COUNT (WR_DATA_COUNT), + .PROG_FULL (PROG_FULL), + .PROG_EMPTY (PROG_EMPTY), + .SBITERR (SBITERR), + .DBITERR (DBITERR) + ); + +endmodule diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/FIFO_GENERATOR_V4_3.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/FIFO_GENERATOR_V4_3.v new file mode 100644 index 0000000..577e45e --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/FIFO_GENERATOR_V4_3.v @@ -0,0 +1,4093 @@ +/* + * $RDCfile: $ $Revision: 1.3 $ $Date: 2008/09/09 20:25:23 $ + ******************************************************************************* + * + * FIFO Generator - Verilog Behavioral Model + * + ******************************************************************************* + * + * Copyright(C) 2006 by Xilinx, Inc. All rights reserved. + * This text/file contains proprietary, confidential + * information of Xilinx, Inc., is distributed under + * license from Xilinx, Inc., and may be used, copied + * and/or disclosed only pursuant to the terms of a valid + * license agreement with Xilinx, Inc. Xilinx hereby + * grants you a license to use this text/file solely for + * design, simulation, implementation and creation of + * design files limited to Xilinx devices or technologies. + * Use with non-Xilinx devices or technologies is expressly + * prohibited and immediately terminates your license unless + * covered by a separate agreement. + * + * Xilinx is providing theis design, code, or information + * "as-is" solely for use in developing programs and + * solutions for Xilinx devices, with no obligation on the + * part of Xilinx to provide support. By providing this design, + * code, or information as one possible implementation of + * this feature, application or standard. Xilinx is making no + * representation that this implementation is free from any + * claims of infringement. You are responsible for obtaining + * any rights you may require for your implementation. + * Xilinx expressly disclaims any warranty whatsoever with + * respect to the adequacy of the implementation, including + * but not limited to any warranties or representations that this + * implementation is free from claims of infringement, implied + * warranties of merchantability or fitness for a particular + * purpose. + * + * Xilinx products are not intended for use in life support + * appliances, devices, or systems. Use in such applications is + * expressly prohibited. + * + * This copyright and support notice must be retained as part + * of this text at all times. (c)Copyright 1995-2006 Xilinx, Inc. + * All rights reserved. + * + ******************************************************************************* + * + * Filename: FIFO_GENERATOR_V4_3.v + * + * Author : Xilinx + * + ******************************************************************************* + * Structure: + * + * fifo_generator_v4_3.vhd + * | + * +-fifo_generator_v4_3_bhv_as + * | + * +-fifo_generator_v4_3_bhv_ss + * | + * +-fifo_generator_v4_3_bhv_preload0 + * + ******************************************************************************* + * Description: + * + * The Verilog behavioral model for the FIFO Generator. + * + * The behavioral model has three parts: + * - The behavioral model for independent clocks FIFOs (_as) + * - The behavioral model for common clock FIFOs (_ss) + * - The "preload logic" block which implements First-word Fall-through + * + ******************************************************************************* + * Description: + * The verilog behavioral model for the FIFO generator core. + * + ******************************************************************************* + */ + +`timescale 1ps/1ps + +/******************************************************************************* + * Declaration of top-level module + ******************************************************************************/ +module FIFO_GENERATOR_V4_3 +( + BACKUP, //not used + BACKUP_MARKER, //not used + CLK, + DIN, + PROG_EMPTY_THRESH, + PROG_EMPTY_THRESH_ASSERT, + PROG_EMPTY_THRESH_NEGATE, + PROG_FULL_THRESH, + PROG_FULL_THRESH_ASSERT, + PROG_FULL_THRESH_NEGATE, + RD_CLK, + RD_EN, + RD_RST, //not used + RST, + SRST, + WR_CLK, + WR_EN, + WR_RST, //not used + INT_CLK, + + ALMOST_EMPTY, + ALMOST_FULL, + DATA_COUNT, + DOUT, + EMPTY, + FULL, + OVERFLOW, + PROG_EMPTY, + PROG_FULL, + RD_DATA_COUNT, + UNDERFLOW, + VALID, + WR_ACK, + WR_DATA_COUNT, + + SBITERR, + DBITERR + ); + +/* + ****************************************************************************** + * Definition of Parameters + ****************************************************************************** + * C_COMMON_CLOCK : Common Clock (1), Independent Clocks (0) + * C_COUNT_TYPE : *not used + * C_DATA_COUNT_WIDTH : Width of DATA_COUNT bus + * C_DEFAULT_VALUE : *not used + * C_DIN_WIDTH : Width of DIN bus + * C_DOUT_RST_VAL : Reset value of DOUT + * C_DOUT_WIDTH : Width of DOUT bus + * C_ENABLE_RLOCS : *not used + * C_FAMILY : not used in bhv model + * C_FULL_FLAGS_RST_VAL : Full flags rst val (0 or 1) + * C_HAS_ALMOST_EMPTY : 1=Core has ALMOST_EMPTY flag + * C_HAS_ALMOST_FULL : 1=Core has ALMOST_FULL flag + * C_HAS_BACKUP : *not used + * C_HAS_DATA_COUNT : 1=Core has DATA_COUNT bus + * C_HAS_INT_CLK : not used in bhv model + * C_HAS_MEMINIT_FILE : *not used + * C_HAS_OVERFLOW : 1=Core has OVERFLOW flag + * C_HAS_RD_DATA_COUNT : 1=Core has RD_DATA_COUNT bus + * C_HAS_RD_RST : *not used + * C_HAS_RST : 1=Core has Async Rst + * C_HAS_SRST : 1=Core has Sync Rst + * C_HAS_UNDERFLOW : 1=Core has UNDERFLOW flag + * C_HAS_VALID : 1=Core has VALID flag + * C_HAS_WR_ACK : 1=Core has WR_ACK flag + * C_HAS_WR_DATA_COUNT : 1=Core has WR_DATA_COUNT bus + * C_HAS_WR_RST : *not used + * C_IMPLEMENTATION_TYPE : 0=Common-Clock Bram/Dram + * 1=Common-Clock ShiftRam + * 2=Indep. Clocks Bram/Dram + * 3=Virtex-4 Built-in + * 4=Virtex-5 Built-in + * C_INIT_WR_PNTR_VAL : *not used + * C_MEMORY_TYPE : 1=Block RAM + * 2=Distributed RAM + * 3=Shift RAM + * 4=Built-in FIFO + * C_MIF_FILE_NAME : *not used + * C_OPTIMIZATION_MODE : *not used + * C_OVERFLOW_LOW : 1=OVERFLOW active low + * C_PRELOAD_LATENCY : Latency of read: 0, 1, 2 + * C_PRELOAD_REGS : 1=Use output registers + * C_PRIM_FIFO_TYPE : not used in bhv model + * C_PROG_EMPTY_THRESH_ASSERT_VAL: PROG_EMPTY assert threshold + * C_PROG_EMPTY_THRESH_NEGATE_VAL: PROG_EMPTY negate threshold + * C_PROG_EMPTY_TYPE : 0=No programmable empty + * 1=Single prog empty thresh constant + * 2=Multiple prog empty thresh constants + * 3=Single prog empty thresh input + * 4=Multiple prog empty thresh inputs + * C_PROG_FULL_THRESH_ASSERT_VAL : PROG_FULL assert threshold + * C_PROG_FULL_THRESH_NEGATE_VAL : PROG_FULL negate threshold + * C_PROG_FULL_TYPE : 0=No prog full + * 1=Single prog full thresh constant + * 2=Multiple prog full thresh constants + * 3=Single prog full thresh input + * 4=Multiple prog full thresh inputs + * C_RD_DATA_COUNT_WIDTH : Width of RD_DATA_COUNT bus + * C_RD_DEPTH : Depth of read interface (2^N) + * C_RD_FREQ : not used in bhv model + * C_RD_PNTR_WIDTH : always log2(C_RD_DEPTH) + * C_UNDERFLOW_LOW : 1=UNDERFLOW active low + * C_USE_DOUT_RST : 1=Resets DOUT on RST + * C_USE_ECC : not used in bhv model + * C_USE_EMBEDDED_REG : 1=Use BRAM embedded output register + * C_USE_FIFO16_FLAGS : not used in bhv model + * C_USE_FWFT_DATA_COUNT : 1=Use extra logic for FWFT data count + * C_VALID_LOW : 1=VALID active low + * C_WR_ACK_LOW : 1=WR_ACK active low + * C_WR_DATA_COUNT_WIDTH : Width of WR_DATA_COUNT bus + * C_WR_DEPTH : Depth of write interface (2^N) + * C_WR_FREQ : not used in bhv model + * C_WR_PNTR_WIDTH : always log2(C_WR_DEPTH) + * C_WR_RESPONSE_LATENCY : *not used + * C_MSGON_VAL : *not used by bhv model + ****************************************************************************** + * Definition of Ports + ****************************************************************************** + * BACKUP : Not used + * BACKUP_MARKER: Not used + * CLK : Clock + * DIN : Input data bus + * PROG_EMPTY_THRESH : Threshold for Programmable Empty Flag + * PROG_EMPTY_THRESH_ASSERT: Threshold for Programmable Empty Flag + * PROG_EMPTY_THRESH_NEGATE: Threshold for Programmable Empty Flag + * PROG_FULL_THRESH : Threshold for Programmable Full Flag + * PROG_FULL_THRESH_ASSERT : Threshold for Programmable Full Flag + * PROG_FULL_THRESH_NEGATE : Threshold for Programmable Full Flag + * RD_CLK : Read Domain Clock + * RD_EN : Read enable + * RD_RST : Not used + * RST : Asynchronous Reset + * SRST : Synchronous Reset + * WR_CLK : Write Domain Clock + * WR_EN : Write enable + * WR_RST : Not used + * INT_CLK : Internal Clock + * ALMOST_EMPTY : One word remaining in FIFO + * ALMOST_FULL : One empty space remaining in FIFO + * DATA_COUNT : Number of data words in fifo( synchronous to CLK) + * DOUT : Output data bus + * EMPTY : Empty flag + * FULL : Full flag + * OVERFLOW : Last write rejected + * PROG_EMPTY : Programmable Empty Flag + * PROG_FULL : Programmable Full Flag + * RD_DATA_COUNT: Number of data words in fifo (synchronous to RD_CLK) + * UNDERFLOW : Last read rejected + * VALID : Last read acknowledged, DOUT bus VALID + * WR_ACK : Last write acknowledged + * WR_DATA_COUNT: Number of data words in fifo (synchronous to WR_CLK) + * SBITERR : Single Bit ECC Error Detected + * DBITERR : Double Bit ECC Error Detected + ****************************************************************************** + */ + + + /**************************************************************************** + * Declare user parameters and their defaults + *****************************************************************************/ + parameter C_COMMON_CLOCK = 0; + parameter C_COUNT_TYPE = 0; //not used + parameter C_DATA_COUNT_WIDTH = 2; + parameter C_DEFAULT_VALUE = ""; //not used + parameter C_DIN_WIDTH = 8; + parameter C_DOUT_RST_VAL = ""; + parameter C_DOUT_WIDTH = 8; + parameter C_ENABLE_RLOCS = 0; //not used + parameter C_FAMILY = "virtex2"; //not used in bhv model + parameter C_FULL_FLAGS_RST_VAL = 1; + parameter C_HAS_ALMOST_EMPTY = 0; + parameter C_HAS_ALMOST_FULL = 0; + parameter C_HAS_BACKUP = 0; //not used + parameter C_HAS_DATA_COUNT = 0; + parameter C_HAS_INT_CLK = 0; //not used in bhv model + parameter C_HAS_MEMINIT_FILE = 0; //not used + parameter C_HAS_OVERFLOW = 0; + parameter C_HAS_RD_DATA_COUNT = 0; + parameter C_HAS_RD_RST = 0; //not used + parameter C_HAS_RST = 0; + parameter C_HAS_SRST = 0; + parameter C_HAS_UNDERFLOW = 0; + parameter C_HAS_VALID = 0; + parameter C_HAS_WR_ACK = 0; + parameter C_HAS_WR_DATA_COUNT = 0; + parameter C_HAS_WR_RST = 0; //not used + parameter C_IMPLEMENTATION_TYPE = 0; + parameter C_INIT_WR_PNTR_VAL = 0; //not used + parameter C_MEMORY_TYPE = 1; + parameter C_MIF_FILE_NAME = ""; //not used + parameter C_OPTIMIZATION_MODE = 0; //not used + parameter C_OVERFLOW_LOW = 0; + parameter C_PRELOAD_LATENCY = 1; + parameter C_PRELOAD_REGS = 0; + parameter C_PRIM_FIFO_TYPE = 512; //not used in bhv model + parameter C_PROG_EMPTY_THRESH_ASSERT_VAL = 0; + parameter C_PROG_EMPTY_THRESH_NEGATE_VAL = 0; + parameter C_PROG_EMPTY_TYPE = 0; + parameter C_PROG_FULL_THRESH_ASSERT_VAL = 0; + parameter C_PROG_FULL_THRESH_NEGATE_VAL = 0; + parameter C_PROG_FULL_TYPE = 0; + parameter C_RD_DATA_COUNT_WIDTH = 2; + parameter C_RD_DEPTH = 256; + parameter C_RD_FREQ = 1; //not used in bhv model + parameter C_RD_PNTR_WIDTH = 8; + parameter C_UNDERFLOW_LOW = 0; + parameter C_USE_DOUT_RST = 0; + parameter C_USE_ECC = 0; //not used in bhv model + parameter C_USE_EMBEDDED_REG = 0; + parameter C_USE_FIFO16_FLAGS = 0; //not used in bhv model + parameter C_USE_FWFT_DATA_COUNT = 0; + parameter C_VALID_LOW = 0; + parameter C_WR_ACK_LOW = 0; + parameter C_WR_DATA_COUNT_WIDTH = 2; + parameter C_WR_DEPTH = 256; + parameter C_WR_FREQ = 1; //not used in bhv model + parameter C_WR_PNTR_WIDTH = 8; + parameter C_WR_RESPONSE_LATENCY = 1; //not used + parameter C_MSGON_VAL = 1; //not used + + + + /***************************************************************************** + * Derived parameters + ****************************************************************************/ + //There are 2 Verilog behavioral models + // 0 = Common-Clock FIFO/ShiftRam FIFO + // 1 = Independent Clocks FIFO + parameter C_VERILOG_IMPL = (C_IMPLEMENTATION_TYPE==0 ? 0 : + (C_IMPLEMENTATION_TYPE==1 ? 0 : + (C_IMPLEMENTATION_TYPE==2 ? 1 : 0))); + + /***************************************************************************** + * Declare Input and Output Ports + ****************************************************************************/ + input CLK; + input BACKUP; + input BACKUP_MARKER; + input [C_DIN_WIDTH-1:0] DIN; + input [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH; + input [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_ASSERT; + input [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_NEGATE; + input [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH; + input [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_ASSERT; + input [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_NEGATE; + input RD_CLK; + input RD_EN; + input RD_RST; + input RST; + input SRST; + input WR_CLK; + input WR_EN; + input WR_RST; + input INT_CLK; + + output ALMOST_EMPTY; + output ALMOST_FULL; + output [C_DATA_COUNT_WIDTH-1:0] DATA_COUNT; + output [C_DOUT_WIDTH-1:0] DOUT; + output EMPTY; + output FULL; + output OVERFLOW; + output PROG_EMPTY; + output PROG_FULL; + output VALID; + output [C_RD_DATA_COUNT_WIDTH-1:0] RD_DATA_COUNT; + output UNDERFLOW; + output WR_ACK; + output [C_WR_DATA_COUNT_WIDTH-1:0] WR_DATA_COUNT; + output SBITERR; + output DBITERR; + + + wire ALMOST_EMPTY; + wire ALMOST_FULL; + wire [C_DATA_COUNT_WIDTH-1:0] DATA_COUNT; + wire [C_DOUT_WIDTH-1:0] DOUT; + wire EMPTY; + wire FULL; + wire OVERFLOW; + wire PROG_EMPTY; + wire PROG_FULL; + wire VALID; + wire [C_RD_DATA_COUNT_WIDTH-1:0] RD_DATA_COUNT; + wire UNDERFLOW; + wire WR_ACK; + wire [C_WR_DATA_COUNT_WIDTH-1:0] WR_DATA_COUNT; + + + wire RD_CLK_P0_IN; + wire RST_P0_IN; + wire RD_EN_FIFO_IN; + wire RD_EN_P0_IN; + + wire ALMOST_EMPTY_FIFO_OUT; + wire ALMOST_FULL_FIFO_OUT; + wire [C_DATA_COUNT_WIDTH-1:0] DATA_COUNT_FIFO_OUT; + wire [C_DOUT_WIDTH-1:0] DOUT_FIFO_OUT; + wire EMPTY_FIFO_OUT; + wire FULL_FIFO_OUT; + wire OVERFLOW_FIFO_OUT; + wire PROG_EMPTY_FIFO_OUT; + wire PROG_FULL_FIFO_OUT; + wire VALID_FIFO_OUT; + wire [C_RD_DATA_COUNT_WIDTH-1:0] RD_DATA_COUNT_FIFO_OUT; + wire UNDERFLOW_FIFO_OUT; + wire WR_ACK_FIFO_OUT; + wire [C_WR_DATA_COUNT_WIDTH-1:0] WR_DATA_COUNT_FIFO_OUT; + + + //*************************************************************************** + // Internal Signals + // The core uses either the internal_ wires or the preload0_ wires depending + // on whether the core uses Preload0 or not. + // When using preload0, the internal signals connect the internal core to + // the preload logic, and the external core's interfaces are tied to the + // preload0 signals from the preload logic. + //*************************************************************************** + wire [C_DOUT_WIDTH-1:0] DATA_P0_OUT; + wire VALID_P0_OUT; + wire EMPTY_P0_OUT; + wire ALMOSTEMPTY_P0_OUT; + reg EMPTY_P0_OUT_Q; + reg ALMOSTEMPTY_P0_OUT_Q; + wire UNDERFLOW_P0_OUT; + wire RDEN_P0_OUT; + wire [C_DOUT_WIDTH-1:0] DATA_P0_IN; + wire EMPTY_P0_IN; + reg [31:0] DATA_COUNT_FWFT; + reg SS_FWFT_WR ; + reg SS_FWFT_RD ; + + assign SBITERR = 1'b0; + assign DBITERR = 1'b0; + + +// Choose the behavioral model to instantiate based on the C_VERILOG_IMPL +// parameter (1=Independent Clocks, 0=Common Clock) +generate +case (C_VERILOG_IMPL) +0 : begin : block1 + //Common Clock Behavioral Model + fifo_generator_v4_3_bhv_ver_ss + #( + C_DATA_COUNT_WIDTH, + C_DIN_WIDTH, + C_DOUT_RST_VAL, + C_DOUT_WIDTH, + C_FULL_FLAGS_RST_VAL, + C_HAS_ALMOST_EMPTY, + C_HAS_ALMOST_FULL, + C_HAS_DATA_COUNT, + C_HAS_OVERFLOW, + C_HAS_RD_DATA_COUNT, + C_HAS_RST, + C_HAS_SRST, + C_HAS_UNDERFLOW, + C_HAS_VALID, + C_HAS_WR_ACK, + C_HAS_WR_DATA_COUNT, + C_IMPLEMENTATION_TYPE, + C_MEMORY_TYPE, + C_OVERFLOW_LOW, + C_PRELOAD_LATENCY, + C_PRELOAD_REGS, + C_PROG_EMPTY_THRESH_ASSERT_VAL, + C_PROG_EMPTY_THRESH_NEGATE_VAL, + C_PROG_EMPTY_TYPE, + C_PROG_FULL_THRESH_ASSERT_VAL, + C_PROG_FULL_THRESH_NEGATE_VAL, + C_PROG_FULL_TYPE, + C_RD_DATA_COUNT_WIDTH, + C_RD_DEPTH, + C_RD_PNTR_WIDTH, + C_UNDERFLOW_LOW, + C_USE_DOUT_RST, + C_USE_EMBEDDED_REG, + C_USE_FWFT_DATA_COUNT, + C_VALID_LOW, + C_WR_ACK_LOW, + C_WR_DATA_COUNT_WIDTH, + C_WR_DEPTH, + C_WR_PNTR_WIDTH + ) + gen_ss + ( + .CLK (CLK), + .RST (RST), + .SRST (SRST), + .DIN (DIN), + .WR_EN (WR_EN), + .RD_EN (RD_EN_FIFO_IN), + .PROG_EMPTY_THRESH (PROG_EMPTY_THRESH), + .PROG_EMPTY_THRESH_ASSERT (PROG_EMPTY_THRESH_ASSERT), + .PROG_EMPTY_THRESH_NEGATE (PROG_EMPTY_THRESH_NEGATE), + .PROG_FULL_THRESH (PROG_FULL_THRESH), + .PROG_FULL_THRESH_ASSERT (PROG_FULL_THRESH_ASSERT), + .PROG_FULL_THRESH_NEGATE (PROG_FULL_THRESH_NEGATE), + .DOUT (DOUT_FIFO_OUT), + .FULL (FULL_FIFO_OUT), + .ALMOST_FULL (ALMOST_FULL_FIFO_OUT), + .WR_ACK (WR_ACK_FIFO_OUT), + .OVERFLOW (OVERFLOW_FIFO_OUT), + .EMPTY (EMPTY_FIFO_OUT), + .ALMOST_EMPTY (ALMOST_EMPTY_FIFO_OUT), + .VALID (VALID_FIFO_OUT), + .UNDERFLOW (UNDERFLOW_FIFO_OUT), + .DATA_COUNT (DATA_COUNT_FIFO_OUT), + .PROG_FULL (PROG_FULL_FIFO_OUT), + .PROG_EMPTY (PROG_EMPTY_FIFO_OUT) + ); +end +1 : begin : block1 + //Independent Clocks Behavioral Model + fifo_generator_v4_3_bhv_ver_as + #( + C_DATA_COUNT_WIDTH, + C_DIN_WIDTH, + C_DOUT_RST_VAL, + C_DOUT_WIDTH, + C_FULL_FLAGS_RST_VAL, + C_HAS_ALMOST_EMPTY, + C_HAS_ALMOST_FULL, + C_HAS_DATA_COUNT, + C_HAS_OVERFLOW, + C_HAS_RD_DATA_COUNT, + C_HAS_RST, + C_HAS_UNDERFLOW, + C_HAS_VALID, + C_HAS_WR_ACK, + C_HAS_WR_DATA_COUNT, + C_IMPLEMENTATION_TYPE, + C_MEMORY_TYPE, + C_OVERFLOW_LOW, + C_PRELOAD_LATENCY, + C_PRELOAD_REGS, + C_PROG_EMPTY_THRESH_ASSERT_VAL, + C_PROG_EMPTY_THRESH_NEGATE_VAL, + C_PROG_EMPTY_TYPE, + C_PROG_FULL_THRESH_ASSERT_VAL, + C_PROG_FULL_THRESH_NEGATE_VAL, + C_PROG_FULL_TYPE, + C_RD_DATA_COUNT_WIDTH, + C_RD_DEPTH, + C_RD_PNTR_WIDTH, + C_UNDERFLOW_LOW, + C_USE_DOUT_RST, + C_USE_EMBEDDED_REG, + C_USE_FWFT_DATA_COUNT, + C_VALID_LOW, + C_WR_ACK_LOW, + C_WR_DATA_COUNT_WIDTH, + C_WR_DEPTH, + C_WR_PNTR_WIDTH + ) + gen_as + ( + .WR_CLK (WR_CLK), + .RD_CLK (RD_CLK), + .RST (RST), + .DIN (DIN), + .WR_EN (WR_EN), + .RD_EN (RD_EN_FIFO_IN), + .PROG_EMPTY_THRESH (PROG_EMPTY_THRESH), + .PROG_EMPTY_THRESH_ASSERT (PROG_EMPTY_THRESH_ASSERT), + .PROG_EMPTY_THRESH_NEGATE (PROG_EMPTY_THRESH_NEGATE), + .PROG_FULL_THRESH (PROG_FULL_THRESH), + .PROG_FULL_THRESH_ASSERT (PROG_FULL_THRESH_ASSERT), + .PROG_FULL_THRESH_NEGATE (PROG_FULL_THRESH_NEGATE), + .DOUT (DOUT_FIFO_OUT), + .FULL (FULL_FIFO_OUT), + .ALMOST_FULL (ALMOST_FULL_FIFO_OUT), + .WR_ACK (WR_ACK_FIFO_OUT), + .OVERFLOW (OVERFLOW_FIFO_OUT), + .EMPTY (EMPTY_FIFO_OUT), + .ALMOST_EMPTY (ALMOST_EMPTY_FIFO_OUT), + .VALID (VALID_FIFO_OUT), + .UNDERFLOW (UNDERFLOW_FIFO_OUT), + .RD_DATA_COUNT (RD_DATA_COUNT_FIFO_OUT), + .WR_DATA_COUNT (WR_DATA_COUNT_FIFO_OUT), + .PROG_FULL (PROG_FULL_FIFO_OUT), + .PROG_EMPTY (PROG_EMPTY_FIFO_OUT) + ); +end + +default : begin : block1 + //Independent Clocks Behavioral Model + fifo_generator_v4_3_bhv_ver_as + #( + C_DATA_COUNT_WIDTH, + C_DIN_WIDTH, + C_DOUT_RST_VAL, + C_DOUT_WIDTH, + C_FULL_FLAGS_RST_VAL, + C_HAS_ALMOST_EMPTY, + C_HAS_ALMOST_FULL, + C_HAS_DATA_COUNT, + C_HAS_OVERFLOW, + C_HAS_RD_DATA_COUNT, + C_HAS_RST, + C_HAS_UNDERFLOW, + C_HAS_VALID, + C_HAS_WR_ACK, + C_HAS_WR_DATA_COUNT, + C_IMPLEMENTATION_TYPE, + C_MEMORY_TYPE, + C_OVERFLOW_LOW, + C_PRELOAD_LATENCY, + C_PRELOAD_REGS, + C_PROG_EMPTY_THRESH_ASSERT_VAL, + C_PROG_EMPTY_THRESH_NEGATE_VAL, + C_PROG_EMPTY_TYPE, + C_PROG_FULL_THRESH_ASSERT_VAL, + C_PROG_FULL_THRESH_NEGATE_VAL, + C_PROG_FULL_TYPE, + C_RD_DATA_COUNT_WIDTH, + C_RD_DEPTH, + C_RD_PNTR_WIDTH, + C_UNDERFLOW_LOW, + C_USE_DOUT_RST, + C_USE_EMBEDDED_REG, + C_USE_FWFT_DATA_COUNT, + C_VALID_LOW, + C_WR_ACK_LOW, + C_WR_DATA_COUNT_WIDTH, + C_WR_DEPTH, + C_WR_PNTR_WIDTH + ) + gen_as + ( + .WR_CLK (WR_CLK), + .RD_CLK (RD_CLK), + .RST (RST), + .DIN (DIN), + .WR_EN (WR_EN), + .RD_EN (RD_EN_FIFO_IN), + .PROG_EMPTY_THRESH (PROG_EMPTY_THRESH), + .PROG_EMPTY_THRESH_ASSERT (PROG_EMPTY_THRESH_ASSERT), + .PROG_EMPTY_THRESH_NEGATE (PROG_EMPTY_THRESH_NEGATE), + .PROG_FULL_THRESH (PROG_FULL_THRESH), + .PROG_FULL_THRESH_ASSERT (PROG_FULL_THRESH_ASSERT), + .PROG_FULL_THRESH_NEGATE (PROG_FULL_THRESH_NEGATE), + .DOUT (DOUT_FIFO_OUT), + .FULL (FULL_FIFO_OUT), + .ALMOST_FULL (ALMOST_FULL_FIFO_OUT), + .WR_ACK (WR_ACK_FIFO_OUT), + .OVERFLOW (OVERFLOW_FIFO_OUT), + .EMPTY (EMPTY_FIFO_OUT), + .ALMOST_EMPTY (ALMOST_EMPTY_FIFO_OUT), + .VALID (VALID_FIFO_OUT), + .UNDERFLOW (UNDERFLOW_FIFO_OUT), + .RD_DATA_COUNT (RD_DATA_COUNT_FIFO_OUT), + .WR_DATA_COUNT (WR_DATA_COUNT_FIFO_OUT), + .PROG_FULL (PROG_FULL_FIFO_OUT), + .PROG_EMPTY (PROG_EMPTY_FIFO_OUT) + ); +end + +endcase +endgenerate + + + //************************************************************************** + // Connect Internal Signals + // (Signals labeled internal_*) + // In the normal case, these signals tie directly to the FIFO's inputs and + // outputs. + // In the case of Preload Latency 0 or 1, there are intermediate + // signals between the internal FIFO and the preload logic. + //************************************************************************** + + + //*********************************************** + // If First-Word Fall-Through, instantiate + // the preload0 (FWFT) module + //*********************************************** + generate + if (C_PRELOAD_REGS==1 && C_PRELOAD_LATENCY==0) begin : block2 + + + fifo_generator_v4_3_bhv_ver_preload0 + #( + C_DOUT_RST_VAL, + C_DOUT_WIDTH, + C_HAS_RST, + C_USE_DOUT_RST, + C_VALID_LOW, + C_UNDERFLOW_LOW + ) + fgpl0 + ( + .RD_CLK (RD_CLK_P0_IN), + .RD_RST (RST_P0_IN), + .RD_EN (RD_EN_P0_IN), + .FIFOEMPTY (EMPTY_P0_IN), + .FIFODATA (DATA_P0_IN), + .USERDATA (DATA_P0_OUT), + .USERVALID (VALID_P0_OUT), + .USEREMPTY (EMPTY_P0_OUT), + .USERALMOSTEMPTY (ALMOSTEMPTY_P0_OUT), + .USERUNDERFLOW (UNDERFLOW_P0_OUT), + .RAMVALID (RAMVALID_P0_OUT), + .FIFORDEN (RDEN_P0_OUT) + ); + + + //*********************************************** + // Connect inputs to preload (FWFT) module + //*********************************************** + //Connect the RD_CLK of the Preload (FWFT) module to CLK if we + // have a common-clock FIFO, or RD_CLK if we have an + // independent clock FIFO + assign RD_CLK_P0_IN = ((C_VERILOG_IMPL == 0) ? CLK : RD_CLK); + assign RST_P0_IN = RST; + assign RD_EN_P0_IN = RD_EN; + assign EMPTY_P0_IN = EMPTY_FIFO_OUT; + assign DATA_P0_IN = DOUT_FIFO_OUT; + + //*********************************************** + // Connect outputs from preload (FWFT) module + //*********************************************** + assign DOUT = DATA_P0_OUT; + assign VALID = VALID_P0_OUT ; + assign EMPTY = EMPTY_P0_OUT; + assign ALMOST_EMPTY = ALMOSTEMPTY_P0_OUT; + assign UNDERFLOW = UNDERFLOW_P0_OUT ; + + assign RD_EN_FIFO_IN = RDEN_P0_OUT; + + + //*********************************************** + // Create DATA_COUNT from First-Word Fall-Through + // data count + //*********************************************** + assign DATA_COUNT = (C_DATA_COUNT_WIDTH>C_RD_PNTR_WIDTH) ? + DATA_COUNT_FWFT[C_RD_PNTR_WIDTH:0] : + DATA_COUNT_FWFT[C_RD_PNTR_WIDTH:C_RD_PNTR_WIDTH-C_DATA_COUNT_WIDTH+1]; + + //*********************************************** + // Create DATA_COUNT from First-Word Fall-Through + // data count + //*********************************************** + always @ (posedge RD_CLK or posedge RST) begin + if (RST) begin + EMPTY_P0_OUT_Q <= 1; + ALMOSTEMPTY_P0_OUT_Q <= 1; + end else begin + EMPTY_P0_OUT_Q <= EMPTY_P0_OUT; + ALMOSTEMPTY_P0_OUT_Q <= ALMOSTEMPTY_P0_OUT; + end + end //always + + + //*********************************************** + // logic for common-clock data count when FWFT is selected + //*********************************************** + initial begin + SS_FWFT_RD = 1'b0; + DATA_COUNT_FWFT = 0 ; + SS_FWFT_WR = 1'b0 ; + end //initial + + + //*********************************************** + // common-clock data count is implemented as an + // up-down counter. SS_FWFT_WR and SS_FWFT_RD + // are the up/down enables for the counter. + //*********************************************** + always @ (RD_EN or VALID_P0_OUT or WR_EN or FULL_FIFO_OUT) begin + SS_FWFT_RD = RD_EN && VALID_P0_OUT ; + SS_FWFT_WR = (WR_EN && (~FULL_FIFO_OUT)) ; + end + + //*********************************************** + // common-clock data count is implemented as an + // up-down counter for FWFT. This always block + // calculates the counter. + //*********************************************** + always @ (posedge RD_CLK_P0_IN or posedge RST) begin + if (RST && (C_HAS_RST == 1) ) begin + DATA_COUNT_FWFT <= 0; + end else begin + if (SRST && (C_HAS_SRST == 1) ) begin + DATA_COUNT_FWFT <= 0; + end else begin + case ( {SS_FWFT_WR, SS_FWFT_RD}) + 2'b00: DATA_COUNT_FWFT <= DATA_COUNT_FWFT ; + 2'b01: DATA_COUNT_FWFT <= DATA_COUNT_FWFT - 1 ; + 2'b10: DATA_COUNT_FWFT <= DATA_COUNT_FWFT + 1 ; + 2'b11: DATA_COUNT_FWFT <= DATA_COUNT_FWFT ; + endcase + end //if SRST + end //IF RST + end //always + + + end else begin : block2 //if !(C_PRELOAD_REGS==1 && C_PRELOAD_LATENCY==0) + + //*********************************************** + // If NOT First-Word Fall-Through, wire the outputs + // of the internal _ss or _as FIFO directly to the + // output, and do not instantiate the preload0 + // module. + //*********************************************** + + assign RD_CLK_P0_IN = 0; + assign RST_P0_IN = 0; + assign RD_EN_P0_IN = 0; + + assign RD_EN_FIFO_IN = RD_EN; + + assign DOUT = DOUT_FIFO_OUT; + assign DATA_P0_IN = 0; + assign VALID = VALID_FIFO_OUT; + assign EMPTY = EMPTY_FIFO_OUT; + assign ALMOST_EMPTY = ALMOST_EMPTY_FIFO_OUT; + assign EMPTY_P0_IN = 0; + assign UNDERFLOW = UNDERFLOW_FIFO_OUT; + assign DATA_COUNT = DATA_COUNT_FIFO_OUT; + + end //if !(C_PRELOAD_REGS==1 && C_PRELOAD_LATENCY==0) + endgenerate + + + //*********************************************** + // Connect user flags to internal signals + //*********************************************** + + //If we are using extra logic for the FWFT data count, then override the + //RD_DATA_COUNT output when we are EMPTY or ALMOST_EMPTY. + //RD_DATA_COUNT is 0 when EMPTY and 1 when ALMOST_EMPTY. + generate + if (C_USE_FWFT_DATA_COUNT==1 && (C_RD_DATA_COUNT_WIDTH>C_RD_PNTR_WIDTH) ) begin : block3 + assign RD_DATA_COUNT = (EMPTY_P0_OUT_Q | RST) ? 0 : (ALMOSTEMPTY_P0_OUT_Q ? 1 : RD_DATA_COUNT_FIFO_OUT); + end //block3 + endgenerate + + //If we are using extra logic for the FWFT data count, then override the + //RD_DATA_COUNT output when we are EMPTY or ALMOST_EMPTY. + //Due to asymmetric ports, RD_DATA_COUNT is 0 when EMPTY or ALMOST_EMPTY. + generate + if (C_USE_FWFT_DATA_COUNT==1 && (C_RD_DATA_COUNT_WIDTH <=C_RD_PNTR_WIDTH) ) begin : block30 + assign RD_DATA_COUNT = (EMPTY_P0_OUT_Q | RST) ? 0 : (ALMOSTEMPTY_P0_OUT_Q ? 0 : RD_DATA_COUNT_FIFO_OUT); + end //block30 + endgenerate + + //If we are not using extra logic for the FWFT data count, + //then connect RD_DATA_COUNT to the RD_DATA_COUNT from the + //internal FIFO instance + generate + if (C_USE_FWFT_DATA_COUNT==0 ) begin : block31 + assign RD_DATA_COUNT = RD_DATA_COUNT_FIFO_OUT; + end + endgenerate + + //Always connect WR_DATA_COUNT to the WR_DATA_COUNT from the internal + //FIFO instance + generate + if (C_USE_FWFT_DATA_COUNT==1) begin : block4 + assign WR_DATA_COUNT = WR_DATA_COUNT_FIFO_OUT; + end + else begin : block4 + assign WR_DATA_COUNT = WR_DATA_COUNT_FIFO_OUT; + end + endgenerate + + + //Connect other flags to the internal FIFO instance + assign FULL = FULL_FIFO_OUT; + assign ALMOST_FULL = ALMOST_FULL_FIFO_OUT; + assign WR_ACK = WR_ACK_FIFO_OUT; + assign OVERFLOW = OVERFLOW_FIFO_OUT; + assign PROG_FULL = PROG_FULL_FIFO_OUT; + assign PROG_EMPTY = PROG_EMPTY_FIFO_OUT; + + + // if an asynchronous FIFO has been selected, display a message that the FIFO + // will not be cycle-accurate in simulation + initial begin + if (C_IMPLEMENTATION_TYPE == 2) begin + $display("Warning in %m at time %t: When using an asynchronous configuration for the FIFO Generator, the behavioral model is not cycle-accurate. You may wish to choose the structural simulation model instead of the behavioral model. This will ensure accurate behavior and latencies during simulation. You can enable this from CORE Generator by selecting Project -> Project Options -> Generation tab -> Structural Simulation. See the FIFO Generator User Guide for more information.", $time); + end else if (C_IMPLEMENTATION_TYPE == 3 || C_IMPLEMENTATION_TYPE == 4) begin + $display("Failure in %m at time %t: Use of Virtex-4 and Virtex-5 built-in FIFO configurations is currently not supported. Please use the structural simulation model. You can enable this from CORE Generator by selecting Project -> Project Options -> Generation tab -> Structural Simulation. See the FIFO Generator User Guide for more information.", $time); + $finish; + end + end //initial + +endmodule //FIFO_GENERATOR_V4_3 + + + +/******************************************************************************* + * Declaration of Independent-Clocks FIFO Module + ******************************************************************************/ +module fifo_generator_v4_3_bhv_ver_as + ( + WR_CLK, RD_CLK, RST, DIN, WR_EN, RD_EN, + PROG_EMPTY_THRESH, PROG_EMPTY_THRESH_ASSERT, PROG_EMPTY_THRESH_NEGATE, + PROG_FULL_THRESH, PROG_FULL_THRESH_ASSERT, PROG_FULL_THRESH_NEGATE, + DOUT, FULL, ALMOST_FULL, WR_ACK, OVERFLOW, EMPTY, ALMOST_EMPTY, VALID, + UNDERFLOW, RD_DATA_COUNT, WR_DATA_COUNT, PROG_FULL, PROG_EMPTY + ); + + /*************************************************************************** + * Declare user parameters and their defaults + ***************************************************************************/ + parameter C_DATA_COUNT_WIDTH = 2; + parameter C_DIN_WIDTH = 8; + parameter C_DOUT_RST_VAL = ""; + parameter C_DOUT_WIDTH = 8; + parameter C_FULL_FLAGS_RST_VAL = 1; + parameter C_HAS_ALMOST_EMPTY = 0; + parameter C_HAS_ALMOST_FULL = 0; + parameter C_HAS_DATA_COUNT = 0; + parameter C_HAS_OVERFLOW = 0; + parameter C_HAS_RD_DATA_COUNT = 0; + parameter C_HAS_RST = 0; + parameter C_HAS_UNDERFLOW = 0; + parameter C_HAS_VALID = 0; + parameter C_HAS_WR_ACK = 0; + parameter C_HAS_WR_DATA_COUNT = 0; + parameter C_IMPLEMENTATION_TYPE = 0; + parameter C_MEMORY_TYPE = 1; + parameter C_OVERFLOW_LOW = 0; + parameter C_PRELOAD_LATENCY = 1; + parameter C_PRELOAD_REGS = 0; + parameter C_PROG_EMPTY_THRESH_ASSERT_VAL = 0; + parameter C_PROG_EMPTY_THRESH_NEGATE_VAL = 0; + parameter C_PROG_EMPTY_TYPE = 0; + parameter C_PROG_FULL_THRESH_ASSERT_VAL = 0; + parameter C_PROG_FULL_THRESH_NEGATE_VAL = 0; + parameter C_PROG_FULL_TYPE = 0; + parameter C_RD_DATA_COUNT_WIDTH = 2; + parameter C_RD_DEPTH = 256; + parameter C_RD_PNTR_WIDTH = 8; + parameter C_UNDERFLOW_LOW = 0; + parameter C_USE_DOUT_RST = 0; + parameter C_USE_EMBEDDED_REG = 0; + parameter C_USE_FWFT_DATA_COUNT = 0; + parameter C_VALID_LOW = 0; + parameter C_WR_ACK_LOW = 0; + parameter C_WR_DATA_COUNT_WIDTH = 2; + parameter C_WR_DEPTH = 256; + parameter C_WR_PNTR_WIDTH = 8; + + /*************************************************************************** + * Declare Input and Output Ports + ***************************************************************************/ + input [C_DIN_WIDTH-1:0] DIN; + input [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH; + input [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_ASSERT; + input [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_NEGATE; + input [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH; + input [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_ASSERT; + input [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_NEGATE; + input RD_CLK; + input RD_EN; + input RST; + input WR_CLK; + input WR_EN; + output ALMOST_EMPTY; + output ALMOST_FULL; + output [C_DOUT_WIDTH-1:0] DOUT; + output EMPTY; + output FULL; + output OVERFLOW; + output PROG_EMPTY; + output PROG_FULL; + output VALID; + output [C_RD_DATA_COUNT_WIDTH-1:0] RD_DATA_COUNT; + output UNDERFLOW; + output WR_ACK; + output [C_WR_DATA_COUNT_WIDTH-1:0] WR_DATA_COUNT; + + /************************************************************************* + * Declare the type for each Input/Output port, and connect each I/O + * to it's associated internal signal in the behavioral model + * + * The values for the outputs are assigned in assign statements immediately + * following wire, parameter, and function declarations in this code. + *************************************************************************/ + //Inputs + wire [C_DIN_WIDTH-1:0] DIN; + wire [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH; + wire [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_ASSERT; + wire [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_NEGATE; + wire [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH; + wire [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_ASSERT; + wire [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_NEGATE; + wire RD_CLK; + wire RD_EN; + wire RST; + wire WR_CLK; + wire WR_EN; + + //Outputs + wire ALMOST_EMPTY; + wire ALMOST_FULL; + wire [C_DOUT_WIDTH-1:0] DOUT; + wire EMPTY; + wire FULL; + wire OVERFLOW; + wire PROG_EMPTY; + wire PROG_FULL; + wire VALID; + wire [C_RD_DATA_COUNT_WIDTH-1:0] RD_DATA_COUNT; + wire UNDERFLOW; + wire WR_ACK; + wire [C_WR_DATA_COUNT_WIDTH-1:0] WR_DATA_COUNT; + + + /*************************************************************************** + * Parameters used as constants + **************************************************************************/ + //When RST is present, set FULL reset value to '1'. + //If core has no RST, make sure FULL powers-on as '0'. + parameter C_DEPTH_RATIO_WR = + (C_WR_DEPTH>C_RD_DEPTH) ? (C_WR_DEPTH/C_RD_DEPTH) : 1; + parameter C_DEPTH_RATIO_RD = + (C_RD_DEPTH>C_WR_DEPTH) ? (C_RD_DEPTH/C_WR_DEPTH) : 1; + parameter C_FIFO_WR_DEPTH = C_WR_DEPTH - 1; + parameter C_FIFO_RD_DEPTH = C_RD_DEPTH - 1; + + + // EXTRA_WORDS = 2 * C_DEPTH_RATIO_WR / C_DEPTH_RATIO_RD + // WR_DEPTH : RD_DEPTH = 1:2 => EXTRA_WORDS = 1 + // WR_DEPTH : RD_DEPTH = 1:4 => EXTRA_WORDS = 1 (rounded to ceiling) + // WR_DEPTH : RD_DEPTH = 2:1 => EXTRA_WORDS = 4 + // WR_DEPTH : RD_DEPTH = 4:1 => EXTRA_WORDS = 8 + parameter EXTRA_WORDS = (C_DEPTH_RATIO_RD > 1)? 1:(2 * C_DEPTH_RATIO_WR); + // extra_words_dc = 2 * C_DEPTH_RATIO_WR / C_DEPTH_RATIO_RD + // C_DEPTH_RATIO_WR | C_DEPTH_RATIO_RD | C_PNTR_WIDTH | EXTRA_WORDS_DC + // -----------------|------------------|-----------------|--------------- + // 1 | 8 | C_RD_PNTR_WIDTH | 0 + // 1 | 4 | C_RD_PNTR_WIDTH | 0 + // 1 | 2 | C_RD_PNTR_WIDTH | 1 + // 1 | 1 | C_WR_PNTR_WIDTH | 2 + // 2 | 1 | C_WR_PNTR_WIDTH | 4 + // 4 | 1 | C_WR_PNTR_WIDTH | 8 + // 8 | 1 | C_WR_PNTR_WIDTH | 16 + parameter EXTRA_WORDS_DC = ( C_DEPTH_RATIO_RD > 2)? + 0:(2 * C_DEPTH_RATIO_WR/C_DEPTH_RATIO_RD); + + + parameter [31:0] reads_per_write = C_DIN_WIDTH/C_DOUT_WIDTH; + + parameter [31:0] log2_reads_per_write = log2_val(reads_per_write); + + parameter [31:0] writes_per_read = C_DOUT_WIDTH/C_DIN_WIDTH; + + parameter [31:0] log2_writes_per_read = log2_val(writes_per_read); + + + + /************************************************************************** + * FIFO Contents Tracking and Data Count Calculations + *************************************************************************/ + + //Memory which will be used to simulate a FIFO + reg [C_DIN_WIDTH-1:0] memory[C_WR_DEPTH-1:0]; + + //The amount of data stored in the FIFO at any time is given + // by num_wr_bits (in the WR_CLK domain) and num_rd_bits (in the RD_CLK + // domain. + //num_wr_bits is calculated by considering the total words in the FIFO, + // and the state of the read pointer (which may not have yet crossed clock + // domains.) + //num_rd_bits is calculated by considering the total words in the FIFO, + // and the state of the write pointer (which may not have yet crossed clock + // domains.) + reg [31:0] num_wr_bits; + reg [31:0] num_rd_bits; + reg [31:0] next_num_wr_bits; + reg [31:0] next_num_rd_bits; + + //The write pointer - tracks write operations + // (Works opposite to core: wr_ptr is a DOWN counter) + reg [31:0] wr_ptr; + + //The read pointer - tracks read operations + // (Works opposite to core: rd_ptr is a DOWN counter) + reg [31:0] rd_ptr; + + //Pointers passed into opposite clock domain + reg [31:0] wr_ptr_rdclk; + reg [31:0] wr_ptr_rdclk_next; + reg [31:0] rd_ptr_wrclk; + reg [31:0] rd_ptr_wrclk_next; + + //Amount of data stored in the FIFO scaled to the narrowest (deepest) port + // (Do not include data in FWFT stages) + //Used to calculate PROG_EMPTY. + wire [31:0] num_read_words_pe = + num_rd_bits/(C_DOUT_WIDTH/C_DEPTH_RATIO_WR); + + //Amount of data stored in the FIFO scaled to the narrowest (deepest) port + // (Do not include data in FWFT stages) + //Used to calculate PROG_FULL. + wire [31:0] num_write_words_pf = + num_wr_bits/(C_DIN_WIDTH/C_DEPTH_RATIO_RD); + + /************************** + * Read Data Count + *************************/ + + /* ORIGINAL CODE - Removed 10/24/07 jeo + //Amount of data stored in the FIFO scaled to read words + // (Do not include data in FWFT stages) + //Not used in the code. + wire [31:0] num_read_words_dc = num_rd_bits/C_DOUT_WIDTH; + + //Amount of data stored in the FIFO scaled to read words + // (Include data in FWFT stages) + //Not used in the code. + wire [31:0] num_read_words_fwft_dc = (num_rd_bits/C_DOUT_WIDTH+2); + + //Not used in the code. + wire [31:0] num_read_words_dc_i = + C_USE_FWFT_DATA_COUNT ? num_read_words_fwft_dc : num_read_words_dc; + + //Not used in the code. + wire [C_RD_DATA_COUNT_WIDTH-1:0] num_read_words_sized = + num_read_words_dc_i[C_RD_PNTR_WIDTH-1 : C_RD_PNTR_WIDTH-C_RD_DATA_COUNT_WIDTH]; + + //Not used in the code. + wire [C_RD_DATA_COUNT_WIDTH-1:0] num_read_words_sized_fwft = + num_read_words_dc_i[C_RD_PNTR_WIDTH : C_RD_PNTR_WIDTH-C_RD_DATA_COUNT_WIDTH+1]; + + //Used to calculate ideal_rd_count (RD_DATA_COUNT) + wire [C_RD_DATA_COUNT_WIDTH-1:0] num_read_words_sized_i = + C_USE_FWFT_DATA_COUNT ? num_read_words_sized_fwft : num_read_words_sized; + */ + + reg [31:0] num_read_words_dc; + reg [C_RD_DATA_COUNT_WIDTH-1:0] num_read_words_sized_i; + + always @(num_rd_bits) begin + if (C_USE_FWFT_DATA_COUNT) begin + + //If using extra logic for FWFT Data Counts, + // then scale FIFO contents to read domain, + // and add two read words for FWFT stages + //This value is only a temporary value and not used in the code. + num_read_words_dc = (num_rd_bits/C_DOUT_WIDTH+2); + + //Trim the read words for use with RD_DATA_COUNT + num_read_words_sized_i = + num_read_words_dc[C_RD_PNTR_WIDTH : C_RD_PNTR_WIDTH-C_RD_DATA_COUNT_WIDTH+1]; + + end else begin + + //If not using extra logic for FWFT Data Counts, + // then scale FIFO contents to read domain. + //This value is only a temporary value and not used in the code. + num_read_words_dc = num_rd_bits/C_DOUT_WIDTH; + + //Trim the read words for use with RD_DATA_COUNT + num_read_words_sized_i = + num_read_words_dc[C_RD_PNTR_WIDTH-1 : C_RD_PNTR_WIDTH-C_RD_DATA_COUNT_WIDTH]; + + end //if (C_USE_FWFT_DATA_COUNT) + end //always + + + + + + + + + /************************** + * Write Data Count + *************************/ + /* ORIGINAL CODE - Removed 10/24/07 jeo + + //Calculate the Data Count value for the number of write words, when not + // using First-Word Fall-Through with extra logic for Data Counts. This + // calculates only the number of words in the internal FIFO. + //The expression (((A-1)/B))+1 divides A/B, but takes the + // ceiling of the result. + //When num_wr_bits==0, set the result manually to prevent division errors. + wire [31:0] num_write_words_dc = + (num_wr_bits==0) ? 0 : ((num_wr_bits-1)/C_DIN_WIDTH) + 1; + + //Calculate the Data Count value for the number of write words, when using + // First-Word Fall-Through with extra logic for Data Counts. This takes into + // consideration the number of words that are expected to be stored in the + // FWFT register stages (it always assumes they are filled). + //The expression (((A-1)/B))+1 divides A/B, but takes the + // ceiling of the result. + //When num_wr_bits==0, set the result manually to prevent division errors. + //EXTRA_WORDS_DC is the number of words added to write_words due to FWFT. + wire [31:0] num_write_words_fwft_dc = + (num_wr_bits==0) ? EXTRA_WORDS_DC : (((num_wr_bits-1)/C_DIN_WIDTH) + 1) + EXTRA_WORDS_DC ; + + wire [31:0] num_write_words_dc_i = + C_USE_FWFT_DATA_COUNT ? num_write_words_fwft_dc : num_write_words_dc; + + + + wire [C_WR_DATA_COUNT_WIDTH-1:0] num_write_words_sized = + num_write_words_dc_i[C_WR_PNTR_WIDTH-1 : C_WR_PNTR_WIDTH-C_WR_DATA_COUNT_WIDTH]; + + wire [C_WR_DATA_COUNT_WIDTH-1:0] num_write_words_sized_fwft = + num_write_words_dc_i[C_WR_PNTR_WIDTH : C_WR_PNTR_WIDTH-C_WR_DATA_COUNT_WIDTH+1]; + + wire [C_WR_DATA_COUNT_WIDTH-1:0] num_write_words_sized_i = C_USE_FWFT_DATA_COUNT? + num_write_words_sized_fwft:num_write_words_sized; + + */ + + reg [31:0] num_write_words_dc; + reg [C_WR_DATA_COUNT_WIDTH-1:0] num_write_words_sized_i; + + always @(num_wr_bits) begin + if (C_USE_FWFT_DATA_COUNT) begin + + //Calculate the Data Count value for the number of write words, + // when using First-Word Fall-Through with extra logic for Data + // Counts. This takes into consideration the number of words that + // are expected to be stored in the FWFT register stages (it always + // assumes they are filled). + //This value is scaled to the Write Domain. + //The expression (((A-1)/B))+1 divides A/B, but takes the + // ceiling of the result. + //When num_wr_bits==0, set the result manually to prevent + // division errors. + //EXTRA_WORDS_DC is the number of words added to write_words + // due to FWFT. + //This value is only a temporary value and not used in the code. + num_write_words_dc = (num_wr_bits==0) ? EXTRA_WORDS_DC : (((num_wr_bits-1)/C_DIN_WIDTH)+1) + EXTRA_WORDS_DC ; + + //Trim the write words for use with WR_DATA_COUNT + num_write_words_sized_i = + num_write_words_dc[C_WR_PNTR_WIDTH : C_WR_PNTR_WIDTH-C_WR_DATA_COUNT_WIDTH+1]; + + end else begin + + //Calculate the Data Count value for the number of write words, when NOT + // using First-Word Fall-Through with extra logic for Data Counts. This + // calculates only the number of words in the internal FIFO. + //The expression (((A-1)/B))+1 divides A/B, but takes the + // ceiling of the result. + //This value is scaled to the Write Domain. + //When num_wr_bits==0, set the result manually to prevent + // division errors. + //This value is only a temporary value and not used in the code. + num_write_words_dc = (num_wr_bits==0) ? 0 : ((num_wr_bits-1)/C_DIN_WIDTH)+1; + + //Trim the read words for use with RD_DATA_COUNT + num_write_words_sized_i = + num_write_words_dc[C_WR_PNTR_WIDTH-1 : C_WR_PNTR_WIDTH-C_WR_DATA_COUNT_WIDTH]; + + end //if (C_USE_FWFT_DATA_COUNT) + end //always + + + + /*************************************************************************** + * Internal registers and wires + **************************************************************************/ + + //Temporary signals used for calculating the model's outputs. These + //are only used in the assign statements immediately following wire, + //parameter, and function declarations. + wire [C_DOUT_WIDTH-1:0] ideal_dout_out; + wire valid_i; + wire valid_out; + wire underflow_i; + + //Ideal FIFO signals. These are the raw output of the behavioral model, + //which behaves like an ideal FIFO. + reg [C_DOUT_WIDTH-1:0] ideal_dout; + reg [C_DOUT_WIDTH-1:0] ideal_dout_d1; + reg ideal_wr_ack; + reg ideal_valid; + reg ideal_overflow; + reg ideal_underflow; + reg ideal_full; + reg ideal_empty; + reg ideal_almost_full; + reg ideal_almost_empty; + reg ideal_prog_full; + reg ideal_prog_empty; + reg [C_WR_DATA_COUNT_WIDTH-1 : 0] ideal_wr_count; + reg [C_RD_DATA_COUNT_WIDTH-1 : 0] ideal_rd_count; + + //Assorted reg values for delayed versions of signals + reg valid_d1; + reg prog_full_d; + reg prog_empty_d; + + //Internal reset signals + reg rd_rst_asreg =0; + reg rd_rst_asreg_d1 =0; + reg rd_rst_asreg_d2 =0; + reg rd_rst_reg =0; + reg rd_rst_d1 =0; + reg wr_rst_asreg =0; + reg wr_rst_asreg_d1 =0; + reg wr_rst_asreg_d2 =0; + reg wr_rst_reg =0; + reg wr_rst_d1 =0; + + wire rd_rst_comb; + wire rd_rst_i; + wire wr_rst_comb; + wire wr_rst_i; + + + //user specified value for reseting the size of the fifo + reg [C_DOUT_WIDTH-1:0] dout_reset_val; + + //temporary registers for WR_RESPONSE_LATENCY feature + + integer tmp_wr_listsize; + integer tmp_rd_listsize; + + //Signal for registered version of prog full and empty + + //Threshold values for Programmable Flags + integer prog_empty_actual_thresh_assert; + integer prog_empty_actual_thresh_negate; + integer prog_full_actual_thresh_assert; + integer prog_full_actual_thresh_negate; + + + /**************************************************************************** + * Function Declarations + ***************************************************************************/ + + /************************************************************************** + * write_fifo + * This task writes a word to the FIFO memory and updates the + * write pointer. + * FIFO size is relative to write domain. + ***************************************************************************/ + task write_fifo; + begin + memory[wr_ptr] <= DIN; + // (Works opposite to core: wr_ptr is a DOWN counter) + if (wr_ptr == 0) begin + wr_ptr <= C_WR_DEPTH - 1; + end else begin + wr_ptr <= wr_ptr - 1; + end + end + endtask // write_fifo + + /************************************************************************** + * read_fifo + * This task reads a word from the FIFO memory and updates the read + * pointer. It's output is the ideal_dout bus. + * FIFO size is relative to write domain. + ***************************************************************************/ + task read_fifo; + integer i; + reg [C_DOUT_WIDTH-1:0] tmp_dout; + reg [C_DIN_WIDTH-1:0] memory_read; + reg [31:0] tmp_rd_ptr; + reg [31:0] rd_ptr_high; + reg [31:0] rd_ptr_low; + begin + // output is wider than input + if (reads_per_write == 0) begin + tmp_dout = 0; + tmp_rd_ptr = (rd_ptr << log2_writes_per_read)+(writes_per_read-1); + for (i = writes_per_read - 1; i >= 0; i = i - 1) begin + tmp_dout = tmp_dout << C_DIN_WIDTH; + tmp_dout = tmp_dout | memory[tmp_rd_ptr]; + + // (Works opposite to core: rd_ptr is a DOWN counter) + if (tmp_rd_ptr == 0) begin + tmp_rd_ptr = C_WR_DEPTH - 1; + end else begin + tmp_rd_ptr = tmp_rd_ptr - 1; + end + end + + // output is symmetric + end else if (reads_per_write == 1) begin + tmp_dout = memory[rd_ptr]; + + // input is wider than output + end else begin + rd_ptr_high = rd_ptr >> log2_reads_per_write; + rd_ptr_low = rd_ptr & (reads_per_write - 1); + memory_read = memory[rd_ptr_high]; + tmp_dout = memory_read >> (rd_ptr_low*C_DOUT_WIDTH); + end + ideal_dout <= tmp_dout; + + // (Works opposite to core: rd_ptr is a DOWN counter) + if (rd_ptr == 0) begin + rd_ptr <= C_RD_DEPTH - 1; + end else begin + rd_ptr <= rd_ptr - 1; + end + end + endtask + + /************************************************************************** + * log2_val + * Returns the 'log2' value for the input value for the supported ratios + ***************************************************************************/ + function [31:0] log2_val; + input [31:0] binary_val; + + begin + if (binary_val == 8) begin + log2_val = 3; + end else if (binary_val == 4) begin + log2_val = 2; + end else begin + log2_val = 1; + end + end + endfunction + + /*********************************************************************** + * hexstr_conv + * Converts a string of type hex to a binary value (for C_DOUT_RST_VAL) + ***********************************************************************/ + function [C_DOUT_WIDTH-1:0] hexstr_conv; + input [(C_DOUT_WIDTH*8)-1:0] def_data; + + integer index,i,j; + reg [3:0] bin; + + begin + index = 0; + hexstr_conv = 'b0; + for( i=C_DOUT_WIDTH-1; i>=0; i=i-1 ) + begin + case (def_data[7:0]) + 8'b00000000 : + begin + bin = 4'b0000; + i = -1; + end + 8'b00110000 : bin = 4'b0000; + 8'b00110001 : bin = 4'b0001; + 8'b00110010 : bin = 4'b0010; + 8'b00110011 : bin = 4'b0011; + 8'b00110100 : bin = 4'b0100; + 8'b00110101 : bin = 4'b0101; + 8'b00110110 : bin = 4'b0110; + 8'b00110111 : bin = 4'b0111; + 8'b00111000 : bin = 4'b1000; + 8'b00111001 : bin = 4'b1001; + 8'b01000001 : bin = 4'b1010; + 8'b01000010 : bin = 4'b1011; + 8'b01000011 : bin = 4'b1100; + 8'b01000100 : bin = 4'b1101; + 8'b01000101 : bin = 4'b1110; + 8'b01000110 : bin = 4'b1111; + 8'b01100001 : bin = 4'b1010; + 8'b01100010 : bin = 4'b1011; + 8'b01100011 : bin = 4'b1100; + 8'b01100100 : bin = 4'b1101; + 8'b01100101 : bin = 4'b1110; + 8'b01100110 : bin = 4'b1111; + default : + begin + bin = 4'bx; + end + endcase + for( j=0; j<4; j=j+1) + begin + if ((index*4)+j < C_DOUT_WIDTH) + begin + hexstr_conv[(index*4)+j] = bin[j]; + end + end + index = index + 1; + def_data = def_data >> 8; + end + end + endfunction + + /************************************************************************* + * Initialize Signals for clean power-on simulation + *************************************************************************/ + initial begin + num_wr_bits = 0; + num_rd_bits = 0; + next_num_wr_bits = 0; + next_num_rd_bits = 0; + rd_ptr = C_RD_DEPTH - 1; + wr_ptr = C_WR_DEPTH - 1; + rd_ptr_wrclk = rd_ptr; + wr_ptr_rdclk = wr_ptr; + dout_reset_val = hexstr_conv(C_DOUT_RST_VAL); + ideal_dout = dout_reset_val; + ideal_dout_d1 = 0 ; + ideal_wr_ack = 1'b0; + ideal_valid = 1'b0; + valid_d1 = 1'b0; + ideal_overflow = 1'b0; + ideal_underflow = 1'b0; + ideal_full = 1'b0; + ideal_empty = 1'b1; + ideal_almost_full = 1'b0; + ideal_almost_empty = 1'b1; + ideal_wr_count = 0; + ideal_rd_count = 0; + ideal_prog_full = 1'b0; + ideal_prog_empty = 1'b1; + prog_full_d = 1'b0; + prog_empty_d = 1'b1; + end + + + /************************************************************************* + * Connect the module inputs and outputs to the internal signals of the + * behavioral model. + *************************************************************************/ + //Inputs + /* + wire [C_DIN_WIDTH-1:0] DIN; + wire [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH; + wire [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_ASSERT; + wire [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_NEGATE; + wire [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH; + wire [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_ASSERT; + wire [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_NEGATE; + wire RD_CLK; + wire RD_EN; + wire RST; + wire WR_CLK; + wire WR_EN; + */ + + //Outputs + assign ALMOST_EMPTY = ideal_almost_empty; + assign ALMOST_FULL = ideal_almost_full; + + //Dout may change behavior based on latency + assign ideal_dout_out[C_DOUT_WIDTH-1:0] = (C_PRELOAD_LATENCY==2 && + (C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1))? + ideal_dout_d1: ideal_dout; + assign DOUT[C_DOUT_WIDTH-1:0] = ideal_dout_out; + + assign EMPTY = ideal_empty; + assign FULL = ideal_full; + + //Overflow may be active-low + assign OVERFLOW = ideal_overflow ? !C_OVERFLOW_LOW : C_OVERFLOW_LOW; + + assign PROG_EMPTY = ideal_prog_empty; + assign PROG_FULL = ideal_prog_full; + + //Valid may change behavior based on latency or active-low + assign valid_i = (C_PRELOAD_LATENCY==0) ? (RD_EN & ~EMPTY) : ideal_valid; + assign valid_out = (C_PRELOAD_LATENCY==2 && + (C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1))? + valid_d1: valid_i; + assign VALID = valid_out ? !C_VALID_LOW : C_VALID_LOW; + + assign RD_DATA_COUNT[C_RD_DATA_COUNT_WIDTH-1:0] = ideal_rd_count; + + //Underflow may change behavior based on latency or active-low + assign underflow_i = (C_PRELOAD_LATENCY==0) ? (RD_EN & EMPTY) : ideal_underflow; + assign UNDERFLOW = underflow_i ? !C_UNDERFLOW_LOW : C_UNDERFLOW_LOW; + + //Write acknowledge may be active low + assign WR_ACK = ideal_wr_ack ? !C_WR_ACK_LOW : C_WR_ACK_LOW; + + assign WR_DATA_COUNT[C_WR_DATA_COUNT_WIDTH-1:0] = ideal_wr_count; + + + /************************************************************************** + * Internal reset logic + **************************************************************************/ + assign wr_rst_comb = !wr_rst_asreg_d2 && wr_rst_asreg; + assign rd_rst_comb = !rd_rst_asreg_d2 && rd_rst_asreg; + assign wr_rst_i = C_HAS_RST ? wr_rst_reg : 0; + assign rd_rst_i = C_HAS_RST ? rd_rst_reg : 0; + + + always @(posedge WR_CLK or posedge RST) begin + if (RST == 1'b1) begin + wr_rst_asreg <= 1'b1; + end else begin + if (wr_rst_asreg_d1 == 1'b1) begin + wr_rst_asreg <= 1'b0; + end else begin + wr_rst_asreg <= wr_rst_asreg; + end + end + end + + always @(posedge WR_CLK) begin + wr_rst_asreg_d1 <= wr_rst_asreg; + wr_rst_asreg_d2 <= wr_rst_asreg_d1; + end + + always @(posedge WR_CLK or posedge wr_rst_comb) begin + if (wr_rst_comb == 1'b1) begin + wr_rst_reg <= 1'b1; + end else begin + wr_rst_reg <= 1'b0; + end + end + + always @(posedge WR_CLK or posedge wr_rst_i) begin + if (wr_rst_i == 1'b1) begin + wr_rst_d1 <= 1'b1; + end else begin + wr_rst_d1 <= wr_rst_i; + end + end + always @(posedge RD_CLK or posedge RST) begin + if (RST == 1'b1) begin + rd_rst_asreg <= 1'b1; + end else begin + if (rd_rst_asreg_d1 == 1'b1) begin + rd_rst_asreg <= 1'b0; + end else begin + rd_rst_asreg <= rd_rst_asreg; + end + end + end + + always @(posedge RD_CLK) begin + rd_rst_asreg_d1 <= rd_rst_asreg; + rd_rst_asreg_d2 <= rd_rst_asreg_d1; + end + + always @(posedge RD_CLK or posedge rd_rst_comb) begin + if (rd_rst_comb == 1'b1) begin + rd_rst_reg <= 1'b1; + end else begin + rd_rst_reg <= 1'b0; + end + end + + /************************************************************************** + * Assorted registers for delayed versions of signals + **************************************************************************/ + //Capture delayed version of valid + always @(posedge RD_CLK or posedge rd_rst_i) begin + if (rd_rst_i == 1'b1) begin + valid_d1 <= 1'b0; + end else begin + valid_d1 <= valid_i; + end + end + + //Capture delayed version of dout + always @(posedge RD_CLK or posedge rd_rst_i) begin + if (rd_rst_i == 1'b1 && C_USE_DOUT_RST == 1) begin + ideal_dout_d1 <= dout_reset_val; + end else begin + ideal_dout_d1 <= ideal_dout; + end + end + + /************************************************************************** + * Overflow and Underflow Flag calculation + * (handled separately because they don't support rst) + **************************************************************************/ + always @(posedge WR_CLK) begin + ideal_overflow <= WR_EN & ideal_full; + end + + always @(posedge RD_CLK) begin + ideal_underflow <= ideal_empty & RD_EN; + end + + /************************************************************************** + * Write Domain Logic + **************************************************************************/ + always @(posedge WR_CLK or posedge wr_rst_i) begin : gen_fifo_w + + /****** Reset fifo (case 1)***************************************/ + if (wr_rst_i == 1'b1) begin + num_wr_bits <= 0; + next_num_wr_bits <= 0; + wr_ptr <= C_WR_DEPTH - 1; + rd_ptr_wrclk <= C_RD_DEPTH - 1; + ideal_wr_ack <= 0; + ideal_full <= C_FULL_FLAGS_RST_VAL; + ideal_almost_full <= C_FULL_FLAGS_RST_VAL; + ideal_wr_count <= 0; + + ideal_prog_full <= C_FULL_FLAGS_RST_VAL; + prog_full_d <= C_FULL_FLAGS_RST_VAL; + + end else begin //wr_rst_i==0 + + //Determine the current number of words in the FIFO + tmp_wr_listsize = (C_DEPTH_RATIO_RD > 1) ? num_wr_bits/C_DOUT_WIDTH : + num_wr_bits/C_DIN_WIDTH; + rd_ptr_wrclk_next = rd_ptr; + if (rd_ptr_wrclk < rd_ptr_wrclk_next) begin + next_num_wr_bits = num_wr_bits - + C_DOUT_WIDTH*(rd_ptr_wrclk + C_RD_DEPTH + - rd_ptr_wrclk_next); + end else begin + next_num_wr_bits = num_wr_bits - + C_DOUT_WIDTH*(rd_ptr_wrclk - rd_ptr_wrclk_next); + end + + //If this is a write, handle the write by adding the value + // to the linked list, and updating all outputs appropriately + if (WR_EN == 1'b1) begin + if (ideal_full == 1'b1) begin + + //If the FIFO is full, do NOT perform the write, + // update flags accordingly + if ((tmp_wr_listsize + C_DEPTH_RATIO_RD - 1)/C_DEPTH_RATIO_RD + >= C_FIFO_WR_DEPTH) begin + //write unsuccessful - do not change contents + + //Do not acknowledge the write + ideal_wr_ack <= 0; + //Reminder that FIFO is still full + ideal_full <= 1'b1; + ideal_almost_full <= 1'b1; + + ideal_wr_count <= num_write_words_sized_i; + + //If the FIFO is one from full, but reporting full + end else + if ((tmp_wr_listsize + C_DEPTH_RATIO_RD - 1)/C_DEPTH_RATIO_RD == + C_FIFO_WR_DEPTH-1) begin + //No change to FIFO + + //Write not successful + ideal_wr_ack <= 0; + //With DEPTH-1 words in the FIFO, it is almost_full + ideal_full <= 1'b0; + ideal_almost_full <= 1'b1; + + ideal_wr_count <= num_write_words_sized_i; + + + //If the FIFO is completely empty, but it is + // reporting FULL for some reason (like reset) + end else + if ((tmp_wr_listsize + C_DEPTH_RATIO_RD - 1)/C_DEPTH_RATIO_RD <= + C_FIFO_WR_DEPTH-2) begin + //No change to FIFO + + //Write not successful + ideal_wr_ack <= 0; + //FIFO is really not close to full, so change flag status. + ideal_full <= 1'b0; + ideal_almost_full <= 1'b0; + + ideal_wr_count <= num_write_words_sized_i; + end //(tmp_wr_listsize == 0) + + end else begin + + //If the FIFO is full, do NOT perform the write, + // update flags accordingly + if ((tmp_wr_listsize + C_DEPTH_RATIO_RD - 1)/C_DEPTH_RATIO_RD >= + C_FIFO_WR_DEPTH) begin + //write unsuccessful - do not change contents + + //Do not acknowledge the write + ideal_wr_ack <= 0; + //Reminder that FIFO is still full + ideal_full <= 1'b1; + ideal_almost_full <= 1'b1; + + ideal_wr_count <= num_write_words_sized_i; + + //If the FIFO is one from full + end else + if ((tmp_wr_listsize + C_DEPTH_RATIO_RD - 1)/C_DEPTH_RATIO_RD == + C_FIFO_WR_DEPTH-1) begin + //Add value on DIN port to FIFO + write_fifo; + next_num_wr_bits = next_num_wr_bits + C_DIN_WIDTH; + + //Write successful, so issue acknowledge + // and no error + ideal_wr_ack <= 1; + //This write is CAUSING the FIFO to go full + ideal_full <= 1'b1; + ideal_almost_full <= 1'b1; + + ideal_wr_count <= num_write_words_sized_i; + + //If the FIFO is 2 from full + end else + if ((tmp_wr_listsize + C_DEPTH_RATIO_RD - 1)/C_DEPTH_RATIO_RD == + C_FIFO_WR_DEPTH-2) begin + //Add value on DIN port to FIFO + write_fifo; + next_num_wr_bits = next_num_wr_bits + C_DIN_WIDTH; + //Write successful, so issue acknowledge + // and no error + ideal_wr_ack <= 1; + //Still 2 from full + ideal_full <= 1'b0; + //2 from full, and writing, so set almost_full + ideal_almost_full <= 1'b1; + + ideal_wr_count <= num_write_words_sized_i; + + //If the FIFO is not close to being full + end else + if ((tmp_wr_listsize + C_DEPTH_RATIO_RD - 1)/C_DEPTH_RATIO_RD < + C_FIFO_WR_DEPTH-2) begin + //Add value on DIN port to FIFO + write_fifo; + next_num_wr_bits = next_num_wr_bits + C_DIN_WIDTH; + //Write successful, so issue acknowledge + // and no error + ideal_wr_ack <= 1; + //Not even close to full. + ideal_full <= 1'b0; + ideal_almost_full <= 1'b0; + + ideal_wr_count <= num_write_words_sized_i; + + end + + end + + end else begin //(WR_EN == 1'b1) + + //If user did not attempt a write, then do not + // give ack or err + ideal_wr_ack <= 0; + + //Implied statements: + //ideal_empty <= ideal_empty; + //ideal_almost_empty <= ideal_almost_empty; + + //Check for full + if ((tmp_wr_listsize + C_DEPTH_RATIO_RD - 1)/C_DEPTH_RATIO_RD >= C_FIFO_WR_DEPTH) + ideal_full <= 1'b1; + else + ideal_full <= 1'b0; + + //Check for almost_full + if ((tmp_wr_listsize + C_DEPTH_RATIO_RD - 1)/C_DEPTH_RATIO_RD >= C_FIFO_WR_DEPTH-1) + ideal_almost_full <= 1'b1; + else + ideal_almost_full <= 1'b0; + + ideal_wr_count <= num_write_words_sized_i; + end + + /********************************************************* + * Programmable FULL flags + *********************************************************/ + //Single Programmable Full Constant Threshold + if (C_PROG_FULL_TYPE==1) begin + if (C_PRELOAD_REGS==1 && C_PRELOAD_LATENCY==0) begin + prog_full_actual_thresh_assert = C_PROG_FULL_THRESH_ASSERT_VAL-EXTRA_WORDS; + prog_full_actual_thresh_negate = C_PROG_FULL_THRESH_ASSERT_VAL-EXTRA_WORDS; + end else begin + prog_full_actual_thresh_assert = C_PROG_FULL_THRESH_ASSERT_VAL; + prog_full_actual_thresh_negate = C_PROG_FULL_THRESH_ASSERT_VAL; + end + + //Two Programmable Full Constant Thresholds + end else if (C_PROG_FULL_TYPE==2) begin + if (C_PRELOAD_REGS==1 && C_PRELOAD_LATENCY==0) begin + prog_full_actual_thresh_assert = C_PROG_FULL_THRESH_ASSERT_VAL-EXTRA_WORDS; + prog_full_actual_thresh_negate = C_PROG_FULL_THRESH_NEGATE_VAL-EXTRA_WORDS; + end else begin + prog_full_actual_thresh_assert = C_PROG_FULL_THRESH_ASSERT_VAL; + prog_full_actual_thresh_negate = C_PROG_FULL_THRESH_NEGATE_VAL; + end + + //Single Programmable Full Threshold Input + end else if (C_PROG_FULL_TYPE==3) begin + if (C_PRELOAD_REGS==1 && C_PRELOAD_LATENCY==0) begin + prog_full_actual_thresh_assert = PROG_FULL_THRESH-EXTRA_WORDS; + prog_full_actual_thresh_negate = PROG_FULL_THRESH-EXTRA_WORDS; + end else begin + prog_full_actual_thresh_assert = PROG_FULL_THRESH; + prog_full_actual_thresh_negate = PROG_FULL_THRESH; + end + + //Two Programmable Full Threshold Inputs + end else if (C_PROG_FULL_TYPE==4) begin + if (C_PRELOAD_REGS==1 && C_PRELOAD_LATENCY==0) begin + prog_full_actual_thresh_assert = PROG_FULL_THRESH_ASSERT-EXTRA_WORDS; + prog_full_actual_thresh_negate = PROG_FULL_THRESH_NEGATE-EXTRA_WORDS; + end else begin + prog_full_actual_thresh_assert = PROG_FULL_THRESH_ASSERT; + prog_full_actual_thresh_negate = PROG_FULL_THRESH_NEGATE; + end + end //C_PROG_FULL_TYPE + + if (num_write_words_pf==0) begin + prog_full_d <= 1'b0; + end else begin + if (((1+(num_write_words_pf-1)/C_DEPTH_RATIO_RD) + == prog_full_actual_thresh_assert-1) && WR_EN) begin + prog_full_d <= 1'b1; + end else if ((1+(num_write_words_pf-1)/C_DEPTH_RATIO_RD) + >= prog_full_actual_thresh_assert) begin + prog_full_d <= 1'b1; + end else if ((1+(num_write_words_pf-1)/C_DEPTH_RATIO_RD) + < prog_full_actual_thresh_negate) begin + prog_full_d <= 1'b0; + end + end + + if (wr_rst_d1==1 && wr_rst_i==0) begin + ideal_prog_full <= 0; + end else begin + ideal_prog_full <= prog_full_d; + end + num_wr_bits <= next_num_wr_bits; + rd_ptr_wrclk <= rd_ptr; + + end //wr_rst_i==0 + end // write always + + + /************************************************************************** + * Read Domain Logic + **************************************************************************/ + always @(posedge RD_CLK or posedge rd_rst_i) begin : gen_fifo_r + + /****** Reset fifo (case 1)***************************************/ + if (rd_rst_i) begin + num_rd_bits <= 0; + next_num_rd_bits <= 0; + rd_ptr <= C_RD_DEPTH -1; + wr_ptr_rdclk <= C_WR_DEPTH -1; + if (C_USE_DOUT_RST == 1) begin + ideal_dout <= dout_reset_val; + end else begin + ideal_dout <= ideal_dout; + end + ideal_valid <= 1'b0; + ideal_empty <= 1'b1; + ideal_almost_empty <= 1'b1; + ideal_rd_count <= 0; + + ideal_prog_empty <= 1'b1; + prog_empty_d <= 1; + + + end else begin //rd_rst_i==0 + + //Determine the current number of words in the FIFO + tmp_rd_listsize = (C_DEPTH_RATIO_WR > 1) ? num_rd_bits/C_DIN_WIDTH : + num_rd_bits/C_DOUT_WIDTH; + wr_ptr_rdclk_next = wr_ptr; + + if (wr_ptr_rdclk < wr_ptr_rdclk_next) begin + next_num_rd_bits = num_rd_bits + + C_DIN_WIDTH*(wr_ptr_rdclk +C_WR_DEPTH + - wr_ptr_rdclk_next); + end else begin + next_num_rd_bits = num_rd_bits + + C_DIN_WIDTH*(wr_ptr_rdclk - wr_ptr_rdclk_next); + end + + /*****************************************************************/ + // Read Operation - Read Latency 1 + /*****************************************************************/ + if (C_PRELOAD_LATENCY==1 || C_PRELOAD_LATENCY==2) begin + + if (RD_EN == 1'b1) begin + + if (ideal_empty == 1'b1) begin + + //If the FIFO is completely empty, and is reporting empty + if (tmp_rd_listsize/C_DEPTH_RATIO_WR <= 0) + begin + //Do not change the contents of the FIFO + + //Do not acknowledge the read from empty FIFO + ideal_valid <= 1'b0; + //Reminder that FIFO is still empty + ideal_empty <= 1'b1; + ideal_almost_empty <= 1'b1; + + ideal_rd_count <= num_read_words_sized_i; + end // if (tmp_rd_listsize <= 0) + + //If the FIFO is one from empty, but it is reporting empty + else if (tmp_rd_listsize/C_DEPTH_RATIO_WR == 1) + begin + //Do not change the contents of the FIFO + + //Do not acknowledge the read from empty FIFO + ideal_valid <= 1'b0; + //Note that FIFO is no longer empty, but is almost empty (has one word left) + ideal_empty <= 1'b0; + ideal_almost_empty <= 1'b1; + + ideal_rd_count <= num_read_words_sized_i; + + end // if (tmp_rd_listsize == 1) + + //If the FIFO is two from empty, and is reporting empty + else if (tmp_rd_listsize/C_DEPTH_RATIO_WR == 2) + begin + //Do not change the contents of the FIFO + + //Do not acknowledge the read from empty FIFO + ideal_valid <= 1'b0; + //Fifo has two words, so is neither empty or almost empty + ideal_empty <= 1'b0; + ideal_almost_empty <= 1'b0; + + ideal_rd_count <= num_read_words_sized_i; + + end // if (tmp_rd_listsize == 2) + + //If the FIFO is not close to empty, but is reporting that it is + // Treat the FIFO as empty this time, but unset EMPTY flags. + if ((tmp_rd_listsize/C_DEPTH_RATIO_WR > 2) && (tmp_rd_listsize/C_DEPTH_RATIO_WR 2) && (tmp_rd_listsize<=C_FIFO_RD_DEPTH-1)) + end // else: if(ideal_empty == 1'b1) + + else //if (ideal_empty == 1'b0) + begin + + //If the FIFO is completely full, and we are successfully reading from it + if (tmp_rd_listsize/C_DEPTH_RATIO_WR >= C_FIFO_RD_DEPTH) + begin + //Read the value from the FIFO + read_fifo; + next_num_rd_bits = next_num_rd_bits - C_DOUT_WIDTH; + + //Acknowledge the read from the FIFO, no error + ideal_valid <= 1'b1; + //Not close to empty + ideal_empty <= 1'b0; + ideal_almost_empty <= 1'b0; + + ideal_rd_count <= num_read_words_sized_i; + + end // if (tmp_rd_listsize == C_FIFO_RD_DEPTH) + + //If the FIFO is not close to being empty + else if ((tmp_rd_listsize/C_DEPTH_RATIO_WR > 2) && (tmp_rd_listsize/C_DEPTH_RATIO_WR<=C_FIFO_RD_DEPTH)) + begin + //Read the value from the FIFO + read_fifo; + next_num_rd_bits = next_num_rd_bits - C_DOUT_WIDTH; + + //Acknowledge the read from the FIFO, no error + ideal_valid <= 1'b1; + //Not close to empty + ideal_empty <= 1'b0; + ideal_almost_empty <= 1'b0; + + ideal_rd_count <= num_read_words_sized_i; + + end // if ((tmp_rd_listsize > 2) && (tmp_rd_listsize<=C_FIFO_RD_DEPTH-1)) + + //If the FIFO is two from empty + else if (tmp_rd_listsize/C_DEPTH_RATIO_WR == 2) + begin + //Read the value from the FIFO + read_fifo; + next_num_rd_bits = next_num_rd_bits - C_DOUT_WIDTH; + + //Acknowledge the read from the FIFO, no error + ideal_valid <= 1'b1; + //Fifo is not yet empty. It is going almost_empty + ideal_empty <= 1'b0; + ideal_almost_empty <= 1'b1; + + ideal_rd_count <= num_read_words_sized_i; + + end // if (tmp_rd_listsize == 2) + + //If the FIFO is one from empty + else if ((tmp_rd_listsize/C_DEPTH_RATIO_WR == 1)) + begin + //Read the value from the FIFO + read_fifo; + next_num_rd_bits = next_num_rd_bits - C_DOUT_WIDTH; + + //Acknowledge the read from the FIFO, no error + ideal_valid <= 1'b1; + //Note that FIFO is GOING empty + ideal_empty <= 1'b1; + ideal_almost_empty <= 1'b1; + + ideal_rd_count <= num_read_words_sized_i; + + end // if (tmp_rd_listsize == 1) + + + //If the FIFO is completely empty + else if (tmp_rd_listsize/C_DEPTH_RATIO_WR <= 0) + begin + //Do not change the contents of the FIFO + + //Do not acknowledge the read from empty FIFO + ideal_valid <= 1'b0; + //Reminder that FIFO is still empty + ideal_empty <= 1'b1; + ideal_almost_empty <= 1'b1; + + ideal_rd_count <= num_read_words_sized_i; + + end // if (tmp_rd_listsize <= 0) + + end // if (ideal_empty == 1'b0) + + end //(RD_EN == 1'b1) + + else //if (RD_EN == 1'b0) + begin + //If user did not attempt a read, do not give an ack or err + ideal_valid <= 1'b0; + + //Check for empty + if (tmp_rd_listsize/C_DEPTH_RATIO_WR <= 0) + ideal_empty <= 1'b1; + else + ideal_empty <= 1'b0; + + //Check for almost_empty + if (tmp_rd_listsize/C_DEPTH_RATIO_WR <= 1) + ideal_almost_empty <= 1'b1; + else + ideal_almost_empty <= 1'b0; + + ideal_rd_count <= num_read_words_sized_i; + + end // else: !if(RD_EN == 1'b1) + + /*****************************************************************/ + // Read Operation - Read Latency 0 + /*****************************************************************/ + end else if (C_PRELOAD_REGS==1 && C_PRELOAD_LATENCY==0) begin + if (RD_EN == 1'b1) begin + + if (ideal_empty == 1'b1) begin + + //If the FIFO is completely empty, and is reporting empty + if (tmp_rd_listsize/C_DEPTH_RATIO_WR <= 0) begin + //Do not change the contents of the FIFO + + //Do not acknowledge the read from empty FIFO + ideal_valid <= 1'b0; + //Reminder that FIFO is still empty + ideal_empty <= 1'b1; + ideal_almost_empty <= 1'b1; + + ideal_rd_count <= num_read_words_sized_i; + + //If the FIFO is one from empty, but it is reporting empty + end else if (tmp_rd_listsize/C_DEPTH_RATIO_WR == 1) begin + //Do not change the contents of the FIFO + + //Do not acknowledge the read from empty FIFO + ideal_valid <= 1'b0; + //Note that FIFO is no longer empty, but is almost empty (has one word left) + ideal_empty <= 1'b0; + ideal_almost_empty <= 1'b1; + + ideal_rd_count <= num_read_words_sized_i; + + //If the FIFO is two from empty, and is reporting empty + end else if (tmp_rd_listsize/C_DEPTH_RATIO_WR == 2) begin + //Do not change the contents of the FIFO + + //Do not acknowledge the read from empty FIFO + ideal_valid <= 1'b0; + //Fifo has two words, so is neither empty or almost empty + ideal_empty <= 1'b0; + ideal_almost_empty <= 1'b0; + + ideal_rd_count <= num_read_words_sized_i; + + //If the FIFO is not close to empty, but is reporting that it is + // Treat the FIFO as empty this time, but unset EMPTY flags. + end else if ((tmp_rd_listsize/C_DEPTH_RATIO_WR > 2) && + (tmp_rd_listsize/C_DEPTH_RATIO_WR 2) && (tmp_rd_listsize<=C_FIFO_RD_DEPTH-1)) + + end else begin + + //If the FIFO is completely full, and we are successfully reading from it + if (tmp_rd_listsize/C_DEPTH_RATIO_WR >= C_FIFO_RD_DEPTH) begin + //Read the value from the FIFO + read_fifo; + next_num_rd_bits = next_num_rd_bits - C_DOUT_WIDTH; + + //Acknowledge the read from the FIFO, no error + ideal_valid <= 1'b1; + //Not close to empty + ideal_empty <= 1'b0; + ideal_almost_empty <= 1'b0; + + ideal_rd_count <= num_read_words_sized_i; + + //If the FIFO is not close to being empty + end else if ((tmp_rd_listsize/C_DEPTH_RATIO_WR > 2) && + (tmp_rd_listsize/C_DEPTH_RATIO_WR<=C_FIFO_RD_DEPTH)) begin + //Read the value from the FIFO + read_fifo; + next_num_rd_bits = next_num_rd_bits - C_DOUT_WIDTH; + + //Acknowledge the read from the FIFO, no error + ideal_valid <= 1'b1; + //Not close to empty + ideal_empty <= 1'b0; + ideal_almost_empty <= 1'b0; + + ideal_rd_count <= num_read_words_sized_i; + + //If the FIFO is two from empty + end else if (tmp_rd_listsize/C_DEPTH_RATIO_WR == 2) begin + //Read the value from the FIFO + read_fifo; + next_num_rd_bits = next_num_rd_bits - C_DOUT_WIDTH; + + //Acknowledge the read from the FIFO, no error + ideal_valid <= 1'b1; + //Fifo is not yet empty. It is going almost_empty + ideal_empty <= 1'b0; + ideal_almost_empty <= 1'b1; + + ideal_rd_count <= num_read_words_sized_i; + + //If the FIFO is one from empty + end else if (tmp_rd_listsize/C_DEPTH_RATIO_WR == 1) begin + //Read the value from the FIFO + read_fifo; + next_num_rd_bits = next_num_rd_bits - C_DOUT_WIDTH; + + //Acknowledge the read from the FIFO, no error + ideal_valid <= 1'b1; + //Note that FIFO is GOING empty + ideal_empty <= 1'b1; + ideal_almost_empty <= 1'b1; + + ideal_rd_count <= num_read_words_sized_i; + + //If the FIFO is completely empty + end else if (tmp_rd_listsize/C_DEPTH_RATIO_WR <= 0) begin + //Do not change the contents of the FIFO + + //Do not acknowledge the read from empty FIFO + ideal_valid <= 1'b0; + //Reminder that FIFO is still empty + ideal_empty <= 1'b1; + ideal_almost_empty <= 1'b1; + + ideal_rd_count <= num_read_words_sized_i; + + end // if (tmp_rd_listsize <= 0) + + end // if (ideal_empty == 1'b0) + + end else begin//(RD_EN == 1'b0) + + + //If user did not attempt a read, do not give an ack or err + ideal_valid <= 1'b0; + + //Check for empty + if (tmp_rd_listsize/C_DEPTH_RATIO_WR <= 0) + ideal_empty <= 1'b1; + else + ideal_empty <= 1'b0; + + //Check for almost_empty + if (tmp_rd_listsize/C_DEPTH_RATIO_WR <= 1) + ideal_almost_empty <= 1'b1; + else + ideal_almost_empty <= 1'b0; + + ideal_rd_count <= num_read_words_sized_i; + + end // else: !if(RD_EN == 1'b1) + end //if (C_PRELOAD_REGS==1 && C_PRELOAD_LATENCY==0) + + + /********************************************************* + * Programmable EMPTY flags + *********************************************************/ + //Determine the Assert and Negate thresholds for Programmable Empty + // (Subtract 2 read-sized words when using Preload 0) + + //Single Programmable Empty Constant Threshold + if (C_PROG_EMPTY_TYPE==1) begin + if (C_PRELOAD_REGS==1 && C_PRELOAD_LATENCY==0) begin + prog_empty_actual_thresh_assert = C_PROG_EMPTY_THRESH_ASSERT_VAL-2; + prog_empty_actual_thresh_negate = C_PROG_EMPTY_THRESH_ASSERT_VAL-2; + end + else begin + prog_empty_actual_thresh_assert = C_PROG_EMPTY_THRESH_ASSERT_VAL; + prog_empty_actual_thresh_negate = C_PROG_EMPTY_THRESH_ASSERT_VAL; + end + + //Two Programmable Empty Constant Thresholds + end else if (C_PROG_EMPTY_TYPE==2) begin + if (C_PRELOAD_REGS==1 && C_PRELOAD_LATENCY==0) begin + prog_empty_actual_thresh_assert = C_PROG_EMPTY_THRESH_ASSERT_VAL-2; + prog_empty_actual_thresh_negate = C_PROG_EMPTY_THRESH_NEGATE_VAL-2; + end + else begin + prog_empty_actual_thresh_assert = C_PROG_EMPTY_THRESH_ASSERT_VAL; + prog_empty_actual_thresh_negate = C_PROG_EMPTY_THRESH_NEGATE_VAL; + end + + //Single Programmable Empty Constant Threshold + end else if (C_PROG_EMPTY_TYPE==3) begin + if (C_PRELOAD_REGS==1 && C_PRELOAD_LATENCY==0) begin + prog_empty_actual_thresh_assert = PROG_EMPTY_THRESH-2; + prog_empty_actual_thresh_negate = PROG_EMPTY_THRESH-2; + end + else begin + prog_empty_actual_thresh_assert = PROG_EMPTY_THRESH; + prog_empty_actual_thresh_negate = PROG_EMPTY_THRESH; + + end + //Two Programmable Empty Constant Thresholds + end else if (C_PROG_EMPTY_TYPE==4) begin + if (C_PRELOAD_REGS==1 && C_PRELOAD_LATENCY==0) begin + prog_empty_actual_thresh_assert = PROG_EMPTY_THRESH_ASSERT-2; + prog_empty_actual_thresh_negate = PROG_EMPTY_THRESH_NEGATE-2; + end + else begin + prog_empty_actual_thresh_assert = PROG_EMPTY_THRESH_ASSERT; + prog_empty_actual_thresh_negate = PROG_EMPTY_THRESH_NEGATE; + end + end + + if ((num_read_words_pe/C_DEPTH_RATIO_WR == prog_empty_actual_thresh_assert+1) + && RD_EN) begin + prog_empty_d <= 1'b1; + end else if (num_read_words_pe/C_DEPTH_RATIO_WR + <= prog_empty_actual_thresh_assert) begin + prog_empty_d <= 1'b1; + end else if (num_read_words_pe/C_DEPTH_RATIO_WR + > prog_empty_actual_thresh_negate) begin + prog_empty_d <= 1'b0; + end + + + ideal_prog_empty <= prog_empty_d; + num_rd_bits <= next_num_rd_bits; + wr_ptr_rdclk <= wr_ptr; + end //rd_rst_i==0 + end //always + +endmodule // fifo_generator_v4_3_bhv_ver_as + + +/******************************************************************************* + * Declaration of top-level module + ******************************************************************************/ +module fifo_generator_v4_3_bhv_ver_ss + ( + CLK, RST, SRST, DIN, WR_EN, RD_EN, + PROG_FULL_THRESH, PROG_FULL_THRESH_ASSERT, PROG_FULL_THRESH_NEGATE, + PROG_EMPTY_THRESH, PROG_EMPTY_THRESH_ASSERT, PROG_EMPTY_THRESH_NEGATE, + DOUT, FULL, ALMOST_FULL, WR_ACK, OVERFLOW, EMPTY, + ALMOST_EMPTY, VALID, UNDERFLOW, DATA_COUNT, + PROG_FULL, PROG_EMPTY + ); + + /************************************************************************** + * Declare user parameters and their defaults + *************************************************************************/ + parameter C_DATA_COUNT_WIDTH = 2; + parameter C_DIN_WIDTH = 8; + parameter C_DOUT_RST_VAL = ""; + parameter C_DOUT_WIDTH = 8; + parameter C_FULL_FLAGS_RST_VAL = 1; + parameter C_HAS_ALMOST_EMPTY = 0; + parameter C_HAS_ALMOST_FULL = 0; + parameter C_HAS_DATA_COUNT = 0; + parameter C_HAS_OVERFLOW = 0; + parameter C_HAS_RD_DATA_COUNT = 0; + parameter C_HAS_RST = 0; + parameter C_HAS_SRST = 0; + parameter C_HAS_UNDERFLOW = 0; + parameter C_HAS_VALID = 0; + parameter C_HAS_WR_ACK = 0; + parameter C_HAS_WR_DATA_COUNT = 0; + parameter C_IMPLEMENTATION_TYPE = 0; + parameter C_MEMORY_TYPE = 1; + parameter C_OVERFLOW_LOW = 0; + parameter C_PRELOAD_LATENCY = 1; + parameter C_PRELOAD_REGS = 0; + parameter C_PROG_EMPTY_THRESH_ASSERT_VAL = 0; + parameter C_PROG_EMPTY_THRESH_NEGATE_VAL = 0; + parameter C_PROG_EMPTY_TYPE = 0; + parameter C_PROG_FULL_THRESH_ASSERT_VAL = 0; + parameter C_PROG_FULL_THRESH_NEGATE_VAL = 0; + parameter C_PROG_FULL_TYPE = 0; + parameter C_RD_DATA_COUNT_WIDTH = 2; + parameter C_RD_DEPTH = 256; + parameter C_RD_PNTR_WIDTH = 8; + parameter C_UNDERFLOW_LOW = 0; + parameter C_USE_DOUT_RST = 0; + parameter C_USE_EMBEDDED_REG = 0; + parameter C_USE_FWFT_DATA_COUNT = 0; + parameter C_VALID_LOW = 0; + parameter C_WR_ACK_LOW = 0; + parameter C_WR_DATA_COUNT_WIDTH = 2; + parameter C_WR_DEPTH = 256; + parameter C_WR_PNTR_WIDTH = 8; + + + /************************************************************************** + * Declare Input and Output Ports + *************************************************************************/ + //Inputs + input CLK; + input [C_DIN_WIDTH-1:0] DIN; + input [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH; + input [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_ASSERT; + input [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_NEGATE; + input [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH; + input [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_ASSERT; + input [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_NEGATE; + input RD_EN; + input RST; + input SRST; + input WR_EN; + + //Outputs + output ALMOST_EMPTY; + output ALMOST_FULL; + output [C_DATA_COUNT_WIDTH-1:0] DATA_COUNT; + output [C_DOUT_WIDTH-1:0] DOUT; + output EMPTY; + output FULL; + output OVERFLOW; + output PROG_EMPTY; + output PROG_FULL; + output VALID; + output UNDERFLOW; + output WR_ACK; + + /************************************************************************* + * Declare the type for each Input/Output port, and connect each I/O + * to it's associated internal signal in the behavioral model + * + * The values for the outputs are assigned in assign statements immediately + * following wire, parameter, and function declarations in this code. + *************************************************************************/ + //Inputs + wire CLK; + wire [C_DIN_WIDTH-1:0] DIN; + wire [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH; + wire [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_ASSERT; + wire [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_NEGATE; + wire [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH; + wire [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_ASSERT; + wire [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_NEGATE; + wire RD_EN; + wire RST; + wire SRST; + wire WR_EN; + + //Outputs + wire ALMOST_EMPTY; + wire ALMOST_FULL; + reg [C_DATA_COUNT_WIDTH-1:0] DATA_COUNT; + wire [C_DOUT_WIDTH-1:0] DOUT; + wire EMPTY; + wire FULL; + wire OVERFLOW; + wire PROG_EMPTY; + wire PROG_FULL; + wire VALID; + wire UNDERFLOW; + wire WR_ACK; + + + /*************************************************************************** + * Parameters used as constants + **************************************************************************/ + //When RST is present, set FULL reset value to '1'. + //If core has no RST, make sure FULL powers-on as '0'. + //The reset value assignments for FULL, ALMOST_FULL, and PROG_FULL are not + //changed for v3.2(IP2_Im). When the core has Sync Reset, C_HAS_SRST=1 and C_HAS_RST=0. + // Therefore, during SRST, all the FULL flags reset to 0. + parameter C_HAS_FAST_FIFO = 0; + parameter C_FIFO_WR_DEPTH = C_WR_DEPTH; + parameter C_FIFO_RD_DEPTH = C_RD_DEPTH; + + /************************************************************************** + * FIFO Contents Tracking and Data Count Calculations + *************************************************************************/ + //Memory which will be used to simulate a FIFO + reg [C_DIN_WIDTH-1:0] memory[C_WR_DEPTH-1:0]; + + //The amount of data stored in the FIFO at any time is given + // by num_bits. + //num_bits is calculated by from the total words in the FIFO. + reg [31:0] num_bits; + + //The write pointer - tracks write operations + // (Works opposite to core: wr_ptr is a DOWN counter) + reg [31:0] wr_ptr; + + //The write pointer - tracks read operations + // (Works opposite to core: rd_ptr is a DOWN counter) + reg [31:0] rd_ptr; + + /************************** + * Data Count + *************************/ + //Amount of data stored in the FIFO scaled to read words + wire [31:0] num_read_words = num_bits/C_DOUT_WIDTH; + //num_read_words delayed 1 clock cycle + reg [31:0] num_read_words_q; + + //Amount of data stored in the FIFO scaled to write words + wire [31:0] num_write_words = num_bits/C_DIN_WIDTH; + //num_write_words delayed 1 clock cycle + reg [31:0] num_write_words_q; + + + /************************************************************************** + * Internal Registers and wires + *************************************************************************/ + + //Temporary signals used for calculating the model's outputs. These + //are only used in the assign statements immediately following wire, + //parameter, and function declarations. + wire underflow_i; + wire valid_i; + wire valid_out; + + //Ideal FIFO signals. These are the raw output of the behavioral model, + //which behaves like an ideal FIFO. + reg [C_DOUT_WIDTH-1:0] ideal_dout; + reg [C_DOUT_WIDTH-1:0] ideal_dout_d1; + wire [C_DOUT_WIDTH-1:0] ideal_dout_out; + reg ideal_wr_ack; + reg ideal_valid; + reg ideal_overflow; + reg ideal_underflow; + reg ideal_full; + reg ideal_empty; + reg ideal_almost_full; + reg ideal_almost_empty; + reg ideal_prog_full; + reg ideal_prog_empty; + + //Assorted reg values for delayed versions of signals + reg valid_d1; + reg prog_full_d; + reg prog_empty_d; + + + //Internal reset signals + reg rst_asreg =0; + reg rst_asreg_d1 =0; + reg rst_asreg_d2 =0; + reg rst_reg =0; + reg rst_d1 =0; + wire rst_comb; + wire rst_i; + wire srst_i; + + //Delayed version of RST + reg rst_q; + reg rst_qq; + + //user specified value for reseting the size of the fifo + reg [C_DOUT_WIDTH-1:0] dout_reset_val; + + + /**************************************************************************** + * Function Declarations + ***************************************************************************/ + + /************************************************************************** + * write_fifo + * This task writes a word to the FIFO memory and updates the + * write pointer. + * FIFO size is relative to write domain. + ***************************************************************************/ + task write_fifo; + begin + memory[wr_ptr] <= DIN; + if (wr_ptr == 0) begin + wr_ptr <= C_WR_DEPTH - 1; + end else begin + wr_ptr <= wr_ptr - 1; + end + end + endtask // write_fifo + + /************************************************************************** + * read_fifo + * This task reads a word from the FIFO memory and updates the read + * pointer. It's output is the ideal_dout bus. + * FIFO size is relative to write domain. + ***************************************************************************/ + task read_fifo; + begin + ideal_dout <= memory[rd_ptr]; + if (rd_ptr == 0) begin + rd_ptr <= C_RD_DEPTH - 1; + end else begin + rd_ptr <= rd_ptr - 1; + end + end + endtask + + /**************************************************************************** + * log2_val + * Returns the 'log2' value for the input value for the supported ratios + ***************************************************************************/ + function [31:0] log2_val; + input [31:0] binary_val; + + begin + if (binary_val == 8) begin + log2_val = 3; + end else if (binary_val == 4) begin + log2_val = 2; + end else begin + log2_val = 1; + end + end + endfunction + + /**************************************************************************** + * hexstr_conv + * Converts a string of type hex to a binary value (for C_DOUT_RST_VAL) + ***************************************************************************/ + function [C_DOUT_WIDTH-1:0] hexstr_conv; + input [(C_DOUT_WIDTH*8)-1:0] def_data; + + integer index,i,j; + reg [3:0] bin; + + begin + index = 0; + hexstr_conv = 'b0; + for( i=C_DOUT_WIDTH-1; i>=0; i=i-1 ) + begin + case (def_data[7:0]) + 8'b00000000 : + begin + bin = 4'b0000; + i = -1; + end + 8'b00110000 : bin = 4'b0000; + 8'b00110001 : bin = 4'b0001; + 8'b00110010 : bin = 4'b0010; + 8'b00110011 : bin = 4'b0011; + 8'b00110100 : bin = 4'b0100; + 8'b00110101 : bin = 4'b0101; + 8'b00110110 : bin = 4'b0110; + 8'b00110111 : bin = 4'b0111; + 8'b00111000 : bin = 4'b1000; + 8'b00111001 : bin = 4'b1001; + 8'b01000001 : bin = 4'b1010; + 8'b01000010 : bin = 4'b1011; + 8'b01000011 : bin = 4'b1100; + 8'b01000100 : bin = 4'b1101; + 8'b01000101 : bin = 4'b1110; + 8'b01000110 : bin = 4'b1111; + 8'b01100001 : bin = 4'b1010; + 8'b01100010 : bin = 4'b1011; + 8'b01100011 : bin = 4'b1100; + 8'b01100100 : bin = 4'b1101; + 8'b01100101 : bin = 4'b1110; + 8'b01100110 : bin = 4'b1111; + default : + begin + bin = 4'bx; + end + endcase + for( j=0; j<4; j=j+1) + begin + if ((index*4)+j < C_DOUT_WIDTH) + begin + hexstr_conv[(index*4)+j] = bin[j]; + end + end + index = index + 1; + def_data = def_data >> 8; + end + end + endfunction + + + /************************************************************************* + * Initialize Signals for clean power-on simulation + *************************************************************************/ + initial begin + num_bits = 0; + num_read_words_q = 0; + num_write_words_q = 0; + rd_ptr = C_RD_DEPTH -1; + wr_ptr = C_WR_DEPTH -1; + dout_reset_val = hexstr_conv(C_DOUT_RST_VAL); + ideal_dout = dout_reset_val; + ideal_wr_ack = 1'b0; + ideal_valid = 1'b0; + valid_d1 = 1'b0; + ideal_overflow = 1'b0; + ideal_underflow = 1'b0; + ideal_full = 1'b0; + ideal_empty = 1'b1; + ideal_almost_full = 1'b0; + ideal_almost_empty = 1'b1; + ideal_prog_full = 1'b0; + ideal_prog_empty = 1'b1; + prog_full_d = 1'b0; + prog_empty_d = 1'b1; + rst_q = 1'b0; + rst_qq = 1'b0; + end + + + /************************************************************************* + * Connect the module inputs and outputs to the internal signals of the + * behavioral model. + *************************************************************************/ + //Inputs + /* + wire CLK; + wire [C_DIN_WIDTH-1:0] DIN; + wire [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH; + wire [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_ASSERT; + wire [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_NEGATE; + wire [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH; + wire [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_ASSERT; + wire [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_NEGATE; + wire RD_EN; + wire RST; + wire WR_EN; + */ + + //Outputs + assign ALMOST_EMPTY = ideal_almost_empty; + assign ALMOST_FULL = ideal_almost_full; + + //Dout may change behavior based on latency + assign ideal_dout_out= (C_USE_EMBEDDED_REG==1 && + (C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1))? + ideal_dout_d1: ideal_dout; + assign DOUT = ideal_dout_out; + + assign EMPTY = ideal_empty; + assign FULL = ideal_full; + + //Overflow may be active-low + assign OVERFLOW = ideal_overflow ? !C_OVERFLOW_LOW : C_OVERFLOW_LOW; + + assign PROG_EMPTY = ideal_prog_empty; + assign PROG_FULL = ideal_prog_full; + + //Valid may change behavior based on latency or active-low + assign valid_i = (C_PRELOAD_LATENCY==0) ? (RD_EN & ~EMPTY) : ideal_valid; + assign valid_out = (C_PRELOAD_LATENCY==2 && + (C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1))? + valid_d1: valid_i; + assign VALID = valid_out ? !C_VALID_LOW : C_VALID_LOW; + + //Trim data count differently depending on set widths + always @(num_read_words) begin + if (C_DATA_COUNT_WIDTH>C_RD_PNTR_WIDTH) begin + DATA_COUNT = num_read_words[C_RD_PNTR_WIDTH:0]; + end else begin + DATA_COUNT = + num_read_words[C_RD_PNTR_WIDTH-1:C_RD_PNTR_WIDTH-C_DATA_COUNT_WIDTH]; + end //if + end //always + + //Underflow may change behavior based on latency or active-low + assign underflow_i = (C_PRELOAD_LATENCY==0) ? (RD_EN & EMPTY) : ideal_underflow; + assign UNDERFLOW = underflow_i ? !C_UNDERFLOW_LOW : C_UNDERFLOW_LOW; + + + //Write acknowledge may be active low + assign WR_ACK = ideal_wr_ack ? !C_WR_ACK_LOW : C_WR_ACK_LOW; + + + + /***************************************************************************** + * Internal reset logic + ****************************************************************************/ + assign srst_i = C_HAS_SRST ? SRST : 0; + assign rst_comb = !rst_asreg_d2 && rst_asreg; + assign rst_i = C_HAS_RST ? rst_reg : 0; + + always @(posedge CLK or posedge RST) begin + if (RST == 1'b1) begin + rst_asreg <= 1'b1; + end else begin + if (rst_asreg_d1 == 1'b1) begin + rst_asreg <= 1'b0; + end else begin + rst_asreg <= rst_asreg; + end + end + end + + always @(posedge CLK) begin + rst_asreg_d1 <= rst_asreg; + rst_asreg_d2 <= rst_asreg_d1; + end + + always @(posedge CLK or posedge rst_comb) begin + if (rst_comb == 1'b1) begin + rst_reg <= 1'b1; + end else begin + rst_reg <= 1'b0; + end + end + + /************************************************************************** + * Assorted registers for delayed versions of signals + **************************************************************************/ + //Capture delayed version of valid + always @(posedge CLK or posedge rst_i) begin + if (rst_i == 1'b1) begin + valid_d1 <= 1'b0; + end else begin + if (srst_i) begin + valid_d1 <= 1'b0; + end else begin + valid_d1 <= valid_i; + end + end + end // always @ (posedge CLK or posedge rst_i) + + //Capture delayed version of dout + always @(posedge CLK or posedge rst_i) begin + if (rst_i == 1'b1 && C_USE_DOUT_RST == 1) begin + ideal_dout_d1 <= dout_reset_val; + end else begin + if (srst_i && C_USE_DOUT_RST == 1) begin + ideal_dout_d1 <= dout_reset_val; + end else begin + ideal_dout_d1 <= ideal_dout; + end + end + end + + /************************************************************************** + * Overflow and Underflow Flag calculation + * (handled separately because they don't support rst) + **************************************************************************/ + always @(posedge CLK) begin + ideal_overflow <= WR_EN & ideal_full; + ideal_underflow <= ideal_empty & RD_EN; + end + + /************************************************************************* + * Write and Read Logic + ************************************************************************/ + always @(posedge CLK or posedge rst_i) + begin : gen_wr_ack_resp + + //Register reset + rst_q <= rst_i; + rst_qq <= rst_q; + + end // block: gen_wr_ack_resp + + // block memory has a synchronous reset + always @(posedge CLK) begin : gen_fifo_blkmemdout + //Changed the latency of during async reset to '1' instead of '2' to + // make it consistent with the core. + if (rst_i || rst_q || srst_i) begin + /******Initialize Read Domain Signals*********************************/ + if (C_MEMORY_TYPE == 1 && C_USE_DOUT_RST == 1) begin + ideal_dout <= dout_reset_val; + end + end + end //always + + always @(posedge CLK or posedge rst_i) begin : gen_fifo + + /****** Reset fifo - Asynchronous Reset**********************************/ + //Changed the latency of during async reset to '1' instead of '2' to + // make it consistent with the core. + if (rst_i) begin //v3.2 + /******Initialize Generic FIFO constructs*****************************/ + num_bits <= 0; + wr_ptr <= C_WR_DEPTH - 1; + rd_ptr <= C_RD_DEPTH - 1; + num_read_words_q <= 0; + num_write_words_q <= 0; + + + /******Initialize Write Domain Signals********************************/ + ideal_wr_ack <= 0; + ideal_full <= C_FULL_FLAGS_RST_VAL; + ideal_almost_full <= C_FULL_FLAGS_RST_VAL; + + /******Initialize Read Domain Signals*********************************/ + if (C_MEMORY_TYPE != 1 && C_USE_DOUT_RST == 1) begin + ideal_dout <= dout_reset_val; + end + ideal_valid <= 1'b0; + ideal_empty <= 1'b1; + ideal_almost_empty <= 1'b1; + + end else begin + if (srst_i) begin + // SRST is available only for Sync BRAM and Sync DRAM. + // Not for SSHFT. + if (C_MEMORY_TYPE == 1 || C_MEMORY_TYPE == 2) begin + /******Initialize Generic FIFO constructs***********************/ + num_bits <= 0; + wr_ptr <= C_WR_DEPTH - 1; + rd_ptr <= C_RD_DEPTH - 1; + num_read_words_q <= 0; + num_write_words_q <= 0; + + /******Initialize Write Domain Signals**************************/ + ideal_wr_ack <= 0; + ideal_full <= 0; //'0' + ideal_almost_full <= 0; //'0' + + /******Initialize Read Domain Signals***************************/ + //Reset DOUT of Sync DRAM. Sync BRAM DOUT was reset in the + // above always block. + if (C_MEMORY_TYPE == 2 && C_USE_DOUT_RST == 1 ) begin + ideal_dout <= dout_reset_val; + end + ideal_valid <= 1'b0; + ideal_empty <= 1'b1; + ideal_almost_empty <= 1'b1; + end + + end else begin //normal operating conditions + /********************************************************************/ + // Synchronous FIFO Condition #1 : Writing and not reading + /********************************************************************/ + if (WR_EN & ~RD_EN) begin + + /*********************************/ + //If the FIFO is full, do NOT perform the write, + // update flags accordingly + /*********************************/ + if (num_write_words >= C_FIFO_WR_DEPTH) begin + ideal_wr_ack <= 0; + + //still full + ideal_full <= 1'b1; + ideal_almost_full <= 1'b1; + + //write unsuccessful - do not change contents + + // no read attempted + ideal_valid <= 1'b0; + + //Not near empty + ideal_empty <= 1'b0; + ideal_almost_empty <= 1'b0; + + + /*********************************/ + //If the FIFO is reporting FULL + // (Startup condition) + /*********************************/ + end else if ((num_write_words < C_FIFO_WR_DEPTH) && (ideal_full == 1'b1)) begin + ideal_wr_ack <= 0; + + //still full + ideal_full <= 1'b0; + ideal_almost_full <= 1'b0; + + //write unsuccessful - do not change contents + + // no read attempted + ideal_valid <= 1'b0; + + //FIFO EMPTY in this state can not be determined + //ideal_empty <= 1'b0; + //ideal_almost_empty <= 1'b0; + + + /*********************************/ + //If the FIFO is one from full + /*********************************/ + end else if (num_write_words == C_FIFO_WR_DEPTH-1) begin + //good write + ideal_wr_ack <= 1; + + //FIFO is one from FULL and going FULL + ideal_full <= 1'b1; + ideal_almost_full <= 1'b1; + + //Add input data + write_fifo; + + // no read attempted + ideal_valid <= 1'b0; + + //Not near empty + ideal_empty <= 1'b0; + ideal_almost_empty <= 1'b0; + + num_bits <= num_bits + C_DIN_WIDTH; + + /*********************************/ + //If the FIFO is 2 from full + /*********************************/ + end else if (num_write_words == C_FIFO_WR_DEPTH-2) begin + //good write + ideal_wr_ack <= 1; + + //2 from full, and writing, so set almost_full + ideal_full <= 1'b0; + ideal_almost_full <= 1'b1; + + //Add input data + write_fifo; + + //no read attempted + ideal_valid <= 1'b0; + + //Not near empty + ideal_empty <= 1'b0; + ideal_almost_empty <= 1'b0; + + num_bits <= num_bits + C_DIN_WIDTH; + + /*********************************/ + //If the FIFO is ALMOST EMPTY + /*********************************/ + end else if (num_read_words == 1) begin + //good write + ideal_wr_ack <= 1; + + //Not near FULL + ideal_full <= 1'b0; + ideal_almost_full <= 1'b0; + + //Add input data + write_fifo; + + // no read attempted + ideal_valid <= 1'b0; + + //Leaving ALMOST_EMPTY + ideal_empty <= 1'b0; + ideal_almost_empty <= 1'b0; + + num_bits <= num_bits + C_DIN_WIDTH; + + /*********************************/ + //If the FIFO is EMPTY + /*********************************/ + end else if (num_read_words == 0) begin + // good write + ideal_wr_ack <= 1; + + //Not near FULL + ideal_full <= 1'b0; + ideal_almost_full <= 1'b0; + + //Add input data + write_fifo; + + // no read attempted + ideal_valid <= 1'b0; + + //Leaving EMPTY (still ALMOST_EMPTY) + ideal_empty <= 1'b0; + ideal_almost_empty <= 1'b1; + + num_bits <= num_bits + C_DIN_WIDTH; + + /*********************************/ + //If the FIFO is not near EMPTY or FULL + /*********************************/ + end else begin + // good write + ideal_wr_ack <= 1; + + //Not near FULL + ideal_full <= 1'b0; + ideal_almost_full <= 1'b0; + + //Add input data + write_fifo; + + // no read attempted + ideal_valid <= 1'b0; + + //Not near EMPTY + ideal_empty <= 1'b0; + ideal_almost_empty <= 1'b0; + + num_bits <= num_bits + C_DIN_WIDTH; + + end // average case + + + /******************************************************************/ + // Synchronous FIFO Condition #2 : Reading and not writing + /******************************************************************/ + end else if (~WR_EN & RD_EN) begin + + /*********************************/ + //If the FIFO is EMPTY + /*********************************/ + if ((num_read_words == 0) || (ideal_empty == 1'b1)) begin + //no write attemped + ideal_wr_ack <= 0; + + //FIFO is not near FULL + ideal_full <= 1'b0; + ideal_almost_full <= 1'b0; + + //Read will fail + ideal_valid <= 1'b0; + + //FIFO is still empty + ideal_empty <= 1'b1; + ideal_almost_empty <= 1'b1; + + //No read + + /*********************************/ + //If the FIFO is ALMOST EMPTY + /*********************************/ + end else if (num_read_words == 1) begin + //no write attempted + ideal_wr_ack <= 0; + + //FIFO is not near FULL + ideal_full <= 1'b0; + ideal_almost_full <= 1'b0; + + //Read successful + ideal_valid <= 1'b1; + + //This read will make FIFO go empty + ideal_empty <= 1'b1; + ideal_almost_empty <= 1'b1; + + //Get the data from the FIFO + read_fifo; + num_bits <= num_bits - C_DIN_WIDTH; + + + /*********************************/ + //If the FIFO is 2 from EMPTY + /*********************************/ + end else if (num_read_words == 2) begin + + //no write attempted + ideal_wr_ack <= 0; + + //FIFO is not near FULL + ideal_full <= 1'b0; + ideal_almost_full <= 1'b0; + + //Read successful + ideal_valid <= 1'b1; + + //FIFO is going ALMOST_EMPTY + ideal_empty <= 1'b0; + ideal_almost_empty <= 1'b1; + + //Get the data from the FIFO + read_fifo; + num_bits <= num_bits - C_DOUT_WIDTH; + + + + /*********************************/ + //If the FIFO is one from full + /*********************************/ + end else if (num_write_words == C_FIFO_WR_DEPTH-1) begin + + //no write attempted + ideal_wr_ack <= 0; + + //FIFO is leaving ALMOST FULL + ideal_full <= 1'b0; + ideal_almost_full <= 1'b0; + + //Read successful + ideal_valid <= 1'b1; + + //Not near empty + ideal_empty <= 1'b0; + ideal_almost_empty <= 1'b0; + + //Read from the FIFO + read_fifo; + num_bits <= num_bits - C_DOUT_WIDTH; + + + /*********************************/ + // FIFO is FULL + /*********************************/ + end else if (num_write_words >= C_FIFO_WR_DEPTH) + begin + //no write attempted + ideal_wr_ack <= 0; + + //FIFO is leaving FULL, but is still ALMOST_FULL + ideal_full <= 1'b0; + ideal_almost_full <= 1'b1; + + //Read successful + ideal_valid <= 1'b1; + + //Not near empty + ideal_empty <= 1'b0; + ideal_almost_empty <= 1'b0; + + //Read from the FIFO + read_fifo; + num_bits <= num_bits - C_DOUT_WIDTH; + + /*********************************/ + //If the FIFO is not near EMPTY or FULL + /*********************************/ + end else begin + //no write attemped + ideal_wr_ack <= 0; + + //Not near empty + ideal_full <= 1'b0; + ideal_almost_full <= 1'b0; + + //Read successful + ideal_valid <= 1'b1; + + //Not near empty + ideal_empty <= 1'b0; + ideal_almost_empty <= 1'b0; + + //Read from the FIFO + read_fifo; + num_bits <= num_bits - C_DOUT_WIDTH; + + + end // average read + + + /******************************************************************/ + // Synchronous FIFO Condition #3 : Reading and writing + /******************************************************************/ + end else if (WR_EN & RD_EN) begin + + /*********************************/ + // FIFO is FULL + /*********************************/ + if (num_write_words >= C_FIFO_WR_DEPTH) begin + + ideal_wr_ack <= 0; + + //Read will be successful, so FIFO will leave FULL + ideal_full <= 1'b0; + ideal_almost_full <= 1'b1; + + //Read successful + ideal_valid <= 1'b1; + + //Not near empty + ideal_empty <= 1'b0; + ideal_almost_empty <= 1'b0; + + //Read from the FIFO + read_fifo; + num_bits <= num_bits - C_DOUT_WIDTH; + + + /*********************************/ + // FIFO is reporting FULL, but it is empty + // (This is a special case, when coming out of RST + /*********************************/ + end else if ((num_write_words == 0) && (ideal_full == 1'b1)) begin + + ideal_wr_ack <= 0; + + //Read will be successful, so FIFO will leave FULL + ideal_full <= 1'b0; + ideal_almost_full <= 1'b0; + + //Read unsuccessful + ideal_valid <= 1'b0; + + //Report empty condition + ideal_empty <= 1'b1; + ideal_almost_empty <= 1'b1; + + //Do not read from empty FIFO + // Read from the FIFO + + + /*********************************/ + //If the FIFO is one from full + /*********************************/ + end else if (num_write_words == C_FIFO_WR_DEPTH-1) begin + + //Write successful + ideal_wr_ack <= 1; + + //FIFO will remain ALMOST_FULL + ideal_full <= 1'b0; + ideal_almost_full <= 1'b1; + + // put the data into the FIFO + write_fifo; + + //Read successful + ideal_valid <= 1'b1; + + //Not near empty + ideal_empty <= 1'b0; + ideal_almost_empty <= 1'b0; + + //Read from the FIFO + read_fifo; + num_bits <= num_bits + C_DIN_WIDTH - C_DOUT_WIDTH; + + /*********************************/ + //If the FIFO is ALMOST EMPTY + /*********************************/ + end else if (num_read_words == 1) begin + + //Write successful + ideal_wr_ack <= 1; + + // Not near FULL + ideal_full <= 1'b0; + ideal_almost_full <= 1'b0; + + // put the data into the FIFO + write_fifo; + + //Read successful + ideal_valid <= 1'b1; + + //FIFO will stay ALMOST_EMPTY + ideal_empty <= 1'b0; + ideal_almost_empty <= 1'b1; + + //Read from the FIFO + read_fifo; + num_bits <= num_bits + C_DIN_WIDTH - C_DOUT_WIDTH; + + + /*********************************/ + //If the FIFO is EMPTY + /*********************************/ + end else if (num_read_words == 0) begin + + //Write successful + ideal_wr_ack <= 1; + + // Not near FULL + ideal_full <= 1'b0; + ideal_almost_full <= 1'b0; + + // put the data into the FIFO + write_fifo; + + //Read will fail + ideal_valid <= 1'b0; + + //FIFO will leave EMPTY + ideal_empty <= 1'b0; + ideal_almost_empty <= 1'b1; + + // No read + num_bits <= num_bits + C_DIN_WIDTH; + + + /*********************************/ + //If the FIFO is not near EMPTY or FULL + /*********************************/ + end else begin + + //Write successful + ideal_wr_ack <= 1; + + // Not near FULL + ideal_full <= 1'b0; + ideal_almost_full <= 1'b0; + + // put the data into the FIFO + write_fifo; + + //Read successful + ideal_valid <= 1'b1; + + // Not near EMPTY + ideal_empty <= 1'b0; + ideal_almost_empty <= 1'b0; + + //Read from the FIFO + read_fifo; + num_bits <= num_bits + C_DIN_WIDTH - C_DOUT_WIDTH; + + end // average case + + /******************************************************************/ + // Synchronous FIFO Condition #4 : Not reading or writing + /******************************************************************/ + end else begin + + /*********************************/ + // FIFO is FULL + /*********************************/ + if (num_write_words >= C_FIFO_WR_DEPTH) begin + + //No write + ideal_wr_ack <= 0; + ideal_full <= 1'b1; + ideal_almost_full <= 1'b1; + + //No read + ideal_valid <= 1'b0; + ideal_empty <= 1'b0; + ideal_almost_empty <= 1'b0; + + //No change to memory + + /*********************************/ + //If the FIFO is one from full + /*********************************/ + end else if (num_write_words == C_FIFO_WR_DEPTH-1) begin + + //No write + ideal_wr_ack <= 0; + ideal_full <= 1'b0; + ideal_almost_full <= 1'b1; + + //No read + ideal_valid <= 1'b0; + ideal_empty <= 1'b0; + ideal_almost_empty <= 1'b0; + + //No change to memory + + /*********************************/ + //If the FIFO is ALMOST EMPTY + /*********************************/ + end else if (num_read_words == 1) begin + //No write + ideal_wr_ack <= 0; + ideal_full <= 1'b0; + ideal_almost_full <= 1'b0; + + //No read + ideal_valid <= 1'b0; + ideal_empty <= 1'b0; + ideal_almost_empty <= 1'b1; + + //No change to memory + + end // almost empty + + + /*********************************/ + //If the FIFO is EMPTY + /*********************************/ + else if (num_read_words == 0) + begin + //No write + ideal_wr_ack <= 0; + ideal_full <= 1'b0; + ideal_almost_full <= 1'b0; + + //No read + ideal_valid <= 1'b0; + ideal_empty <= 1'b1; + ideal_almost_empty <= 1'b1; + + //No change to memory + + /*********************************/ + //If the FIFO is not near EMPTY or FULL + /*********************************/ + end else begin + + //No write + ideal_wr_ack <= 0; + ideal_full <= 1'b0; + ideal_almost_full <= 1'b0; + + //No read + ideal_valid <= 1'b0; + ideal_empty <= 1'b0; + ideal_almost_empty <= 1'b0; + + //No change to memory + + end // average case + + end // neither reading or writing + + num_read_words_q <= num_read_words; + num_write_words_q <= num_write_words; + + end //normal operating conditions + end + + end // block: gen_fifo + + + always @(posedge CLK or posedge rst_i) begin : gen_fifo_p + + /****** Reset fifo - Async Reset****************************************/ + //The latency of de-assertion of the flags is reduced by 1 to be + // consistent with the core. + if (rst_i) begin + ideal_prog_full <= C_FULL_FLAGS_RST_VAL; + ideal_prog_empty <= 1'b1; + prog_full_d <= C_FULL_FLAGS_RST_VAL; + prog_empty_d <= 1'b1; + + end else begin + if (srst_i) begin + //SRST is available only for Sync BRAM and Sync DRAM. Not for SSHFT. + if (C_MEMORY_TYPE == 1 || C_MEMORY_TYPE == 2) begin + ideal_prog_full <= 1'b0; + ideal_prog_empty <= 1'b1; + prog_full_d <= 1'b0; + prog_empty_d <= 1'b1; + end + end else begin + + /*************************************************************** + * Programmable FULL flags + ****************************************************************/ + //calculation for standard fifo and latency =2 + if (! (C_PRELOAD_REGS==1 && C_PRELOAD_LATENCY==0) ) begin + //Single constant threshold + if (C_PROG_FULL_TYPE == 1) begin + if ((num_write_words >= C_PROG_FULL_THRESH_ASSERT_VAL-1) + && WR_EN && !RD_EN) begin + prog_full_d <= 1'b1; + end else if (((num_write_words == C_PROG_FULL_THRESH_ASSERT_VAL) + && RD_EN && !WR_EN) || (rst_q && !rst_i)) begin + prog_full_d <= 1'b0; + end + + //Dual constant thresholds + end else if (C_PROG_FULL_TYPE == 2) begin + if ((num_write_words == C_PROG_FULL_THRESH_ASSERT_VAL-1) + && WR_EN && !RD_EN) begin + prog_full_d <= 1'b1; + end else if ((num_write_words == C_PROG_FULL_THRESH_NEGATE_VAL) + && RD_EN && !WR_EN) begin + prog_full_d <= 1'b0; + end + + //Single input threshold + end else if (C_PROG_FULL_TYPE == 3) begin + if ((num_write_words == PROG_FULL_THRESH-1) + && WR_EN && !RD_EN) begin + prog_full_d <= 1'b1; + end else if ((num_write_words == PROG_FULL_THRESH) + && !WR_EN && RD_EN) begin + prog_full_d <= 1'b0; + end else if (num_write_words >= PROG_FULL_THRESH) begin + prog_full_d <= 1'b1; + end else if (num_write_words < PROG_FULL_THRESH) begin + prog_full_d <= 1'b0; + end + + //Dual input thresholds + end else begin + if ((num_write_words == PROG_FULL_THRESH_ASSERT-1) + && WR_EN && !RD_EN) begin + prog_full_d <= 1'b1; + end else if ((num_write_words == PROG_FULL_THRESH_NEGATE) + && !WR_EN && RD_EN)begin + prog_full_d <= 1'b0; + end else if (num_write_words >= PROG_FULL_THRESH_ASSERT) begin + prog_full_d <= 1'b1; + end else if (num_write_words < PROG_FULL_THRESH_NEGATE) begin + prog_full_d <= 1'b0; + end + end + end // (~ (C_PRELOAD_REGS==1 && C_PRELOAD_LATENCY==0) ) + + + //calculation for FWFT fifo + if (C_PRELOAD_REGS==1 && C_PRELOAD_LATENCY==0) begin + if (C_PROG_FULL_TYPE == 1) begin + if ((num_write_words >= C_PROG_FULL_THRESH_ASSERT_VAL-1 - 2) + && WR_EN && !RD_EN) begin + prog_full_d <= 1'b1; + end else if (((num_write_words == C_PROG_FULL_THRESH_ASSERT_VAL - 2) + && RD_EN && !WR_EN) || (rst_q && !rst_i)) begin + prog_full_d <= 1'b0; + end + + //Dual constant thresholds + end else if (C_PROG_FULL_TYPE == 2) begin + if ((num_write_words == C_PROG_FULL_THRESH_ASSERT_VAL-1 - 2) + && WR_EN && !RD_EN) begin + prog_full_d <= 1'b1; + end else if ((num_write_words == C_PROG_FULL_THRESH_NEGATE_VAL - 2) + && RD_EN && !WR_EN) begin + prog_full_d <= 1'b0; + end + + //Single input threshold + end else if (C_PROG_FULL_TYPE == 3) begin + if ((num_write_words == PROG_FULL_THRESH-1 - 2) + && WR_EN && !RD_EN) begin + prog_full_d <= 1'b1; + end else if ((num_write_words == PROG_FULL_THRESH - 2) + && !WR_EN && RD_EN) begin + prog_full_d <= 1'b0; + end else if (num_write_words >= PROG_FULL_THRESH - 2) begin + prog_full_d <= 1'b1; + end else if (num_write_words < PROG_FULL_THRESH - 2) begin + prog_full_d <= 1'b0; + end + + //Dual input thresholds + end else begin + if ((num_write_words == PROG_FULL_THRESH_ASSERT-1 - 2) + && WR_EN && !RD_EN) begin + prog_full_d <= 1'b1; + end else if ((num_write_words == PROG_FULL_THRESH_NEGATE - 2) + && !WR_EN && RD_EN)begin + prog_full_d <= 1'b0; + end else if (num_write_words >= PROG_FULL_THRESH_ASSERT - 2) begin + prog_full_d <= 1'b1; + end else if (num_write_words < PROG_FULL_THRESH_NEGATE - 2) begin + prog_full_d <= 1'b0; + end + end + end // (C_PRELOAD_REGS==1 && C_PRELOAD_LATENCY==0) + + /***************************************************************** + * Programmable EMPTY flags + ****************************************************************/ + //calculation for standard fifo and latency = 2 + if (! (C_PRELOAD_REGS==1 && C_PRELOAD_LATENCY==0) ) begin + //Single constant threshold + if (C_PROG_EMPTY_TYPE == 1) begin + if ((num_read_words == C_PROG_EMPTY_THRESH_ASSERT_VAL+1) + && RD_EN && !WR_EN) begin + prog_empty_d <= 1'b1; + end else if ((num_read_words == C_PROG_EMPTY_THRESH_ASSERT_VAL) + && WR_EN && !RD_EN) begin + prog_empty_d <= 1'b0; + end + //Dual constant thresholds + end else if (C_PROG_EMPTY_TYPE == 2) begin + if ((num_read_words == C_PROG_EMPTY_THRESH_ASSERT_VAL+1) + && RD_EN && !WR_EN) begin + prog_empty_d <= 1'b1; + end else if ((num_read_words == C_PROG_EMPTY_THRESH_NEGATE_VAL) + && !RD_EN && WR_EN) begin + prog_empty_d <= 1'b0; + end + + //Single input threshold + end else if (C_PROG_EMPTY_TYPE == 3) begin + if ((num_read_words == PROG_EMPTY_THRESH+1) + && RD_EN && !WR_EN) begin + prog_empty_d <= 1'b1; + end else if ((num_read_words == PROG_EMPTY_THRESH) + && !RD_EN && WR_EN) begin + prog_empty_d <= 1'b0; + end else if (num_read_words <= PROG_EMPTY_THRESH) begin + prog_empty_d <= 1'b1; + end else if (num_read_words > PROG_EMPTY_THRESH)begin + prog_empty_d <= 1'b0; + end + + //Dual input thresholds + end else begin + if (num_read_words <= PROG_EMPTY_THRESH_ASSERT) begin + prog_empty_d <= 1'b1; + end else if ((num_read_words == PROG_EMPTY_THRESH_ASSERT+1) + && RD_EN && !WR_EN) begin + prog_empty_d <= 1'b1; + end else if (num_read_words > PROG_EMPTY_THRESH_NEGATE)begin + prog_empty_d <= 1'b0; + end else if ((num_read_words == PROG_EMPTY_THRESH_NEGATE) + && !RD_EN && WR_EN) begin + prog_empty_d <= 1'b0; + end + end + end // (~ (C_PRELOAD_REGS==1 && C_PRELOAD_LATENCY==0) ) + + //calculation for FWFT fifo + if (C_PRELOAD_REGS==1 && C_PRELOAD_LATENCY==0) begin + //Single constant threshold + if (C_PROG_EMPTY_TYPE == 1) begin + if ((num_read_words == C_PROG_EMPTY_THRESH_ASSERT_VAL+1 - 2) + && RD_EN && !WR_EN) begin + prog_empty_d <= 1'b1; + end else if ((num_read_words == C_PROG_EMPTY_THRESH_ASSERT_VAL - 2) + && WR_EN && !RD_EN) begin + prog_empty_d <= 1'b0; + end + //Dual constant thresholds + end else if (C_PROG_EMPTY_TYPE == 2) begin + if ((num_read_words == C_PROG_EMPTY_THRESH_ASSERT_VAL+1 - 2) + && RD_EN && !WR_EN) begin + prog_empty_d <= 1'b1; + end else if ((num_read_words == C_PROG_EMPTY_THRESH_NEGATE_VAL - 2) + && !RD_EN && WR_EN) begin + prog_empty_d <= 1'b0; + end + + //Single input threshold + end else if (C_PROG_EMPTY_TYPE == 3) begin + if ((num_read_words == PROG_EMPTY_THRESH+1 - 2) + && RD_EN && !WR_EN) begin + prog_empty_d <= 1'b1; + end else if ((num_read_words == PROG_EMPTY_THRESH - 2) + && !RD_EN && WR_EN) begin + prog_empty_d <= 1'b0; + end else if (num_read_words <= PROG_EMPTY_THRESH - 2) begin + prog_empty_d <= 1'b1; + end else if (num_read_words > PROG_EMPTY_THRESH - 2)begin + prog_empty_d <= 1'b0; + end + + //Dual input thresholds + end else begin + if (num_read_words <= PROG_EMPTY_THRESH_ASSERT - 2) begin + prog_empty_d <= 1'b1; + end else if ((num_read_words == PROG_EMPTY_THRESH_ASSERT+1 - 2) + && RD_EN && !WR_EN) begin + prog_empty_d <= 1'b1; + end else if (num_read_words > PROG_EMPTY_THRESH_NEGATE - 2)begin + prog_empty_d <= 1'b0; + end else if ((num_read_words == PROG_EMPTY_THRESH_NEGATE - 2) + && !RD_EN && WR_EN) begin + prog_empty_d <= 1'b0; + end + end + end // (~ (C_PRELOAD_REGS==1 && C_PRELOAD_LATENCY==0) ) + + ideal_prog_empty <= prog_empty_d; + if (rst_q && !rst_i) begin + ideal_prog_full <= 1'b0; + prog_full_d <= 1'b0; + end else begin + ideal_prog_full <= prog_full_d; + end + + end //if (srst_i) begin + end //if (rst_i) begin + end //always @(posedge CLK or posedge rst_i) begin : gen_fifo_p +endmodule // fifo_generator_v4_3_bhv_ver_ss + + + +/************************************************************************** + * First-Word Fall-Through module (preload 0) + **************************************************************************/ +module fifo_generator_v4_3_bhv_ver_preload0 + ( + RD_CLK, + RD_RST, + RD_EN, + FIFOEMPTY, + FIFODATA, + USERDATA, + USERVALID, + USERUNDERFLOW, + USEREMPTY, + USERALMOSTEMPTY, + RAMVALID, + FIFORDEN + ); + + parameter C_DOUT_RST_VAL = ""; + parameter C_DOUT_WIDTH = 8; + parameter C_HAS_RST = 0; + parameter C_USE_DOUT_RST = 0; + parameter C_USERVALID_LOW = 0; + parameter C_USERUNDERFLOW_LOW = 0; + + //Inputs + input RD_CLK; + input RD_RST; + input RD_EN; + input FIFOEMPTY; + input [C_DOUT_WIDTH-1:0] FIFODATA; + + //Outputs + output [C_DOUT_WIDTH-1:0] USERDATA; + output USERVALID; + output USERUNDERFLOW; + output USEREMPTY; + output USERALMOSTEMPTY; + output RAMVALID; + output FIFORDEN; + + //Inputs + wire RD_CLK; + wire RD_RST; + wire RD_EN; + wire FIFOEMPTY; + wire [C_DOUT_WIDTH-1:0] FIFODATA; + + //Outputs + reg [C_DOUT_WIDTH-1:0] USERDATA; + wire USERVALID; + wire USERUNDERFLOW; + wire USEREMPTY; + wire USERALMOSTEMPTY; + wire RAMVALID; + wire FIFORDEN; + + //Internal signals + wire preloadstage1; + wire preloadstage2; + reg ram_valid_i; + reg read_data_valid_i; + wire ram_regout_en; + wire ram_rd_en; + reg empty_i = 1'b1; + reg empty_q = 1'b1; + reg rd_en_q = 1'b0; + reg almost_empty_i = 1'b1; + reg almost_empty_q = 1'b1; + wire rd_rst_i; + + +/************************************************************************* +* FUNCTIONS +*************************************************************************/ + + /************************************************************************* + * hexstr_conv + * Converts a string of type hex to a binary value (for C_DOUT_RST_VAL) + ***********************************************************************/ + function [C_DOUT_WIDTH-1:0] hexstr_conv; + input [(C_DOUT_WIDTH*8)-1:0] def_data; + + integer index,i,j; + reg [3:0] bin; + + begin + index = 0; + hexstr_conv = 'b0; + for( i=C_DOUT_WIDTH-1; i>=0; i=i-1 ) + begin + case (def_data[7:0]) + 8'b00000000 : + begin + bin = 4'b0000; + i = -1; + end + 8'b00110000 : bin = 4'b0000; + 8'b00110001 : bin = 4'b0001; + 8'b00110010 : bin = 4'b0010; + 8'b00110011 : bin = 4'b0011; + 8'b00110100 : bin = 4'b0100; + 8'b00110101 : bin = 4'b0101; + 8'b00110110 : bin = 4'b0110; + 8'b00110111 : bin = 4'b0111; + 8'b00111000 : bin = 4'b1000; + 8'b00111001 : bin = 4'b1001; + 8'b01000001 : bin = 4'b1010; + 8'b01000010 : bin = 4'b1011; + 8'b01000011 : bin = 4'b1100; + 8'b01000100 : bin = 4'b1101; + 8'b01000101 : bin = 4'b1110; + 8'b01000110 : bin = 4'b1111; + 8'b01100001 : bin = 4'b1010; + 8'b01100010 : bin = 4'b1011; + 8'b01100011 : bin = 4'b1100; + 8'b01100100 : bin = 4'b1101; + 8'b01100101 : bin = 4'b1110; + 8'b01100110 : bin = 4'b1111; + default : + begin + bin = 4'bx; + end + endcase + for( j=0; j<4; j=j+1) + begin + if ((index*4)+j < C_DOUT_WIDTH) + begin + hexstr_conv[(index*4)+j] = bin[j]; + end + end + index = index + 1; + def_data = def_data >> 8; + end + end + endfunction + + + //************************************************************************* + // Set power-on states for regs + //************************************************************************* + initial begin + ram_valid_i = 1'b0; + read_data_valid_i = 1'b0; + USERDATA = hexstr_conv(C_DOUT_RST_VAL); + end //initial + + //*************************************************************************** + // connect up optional reset + //*************************************************************************** + assign rd_rst_i = C_HAS_RST ? RD_RST : 0; + + + //*************************************************************************** + // preloadstage2 indicates that stage2 needs to be updated. This is true + // whenever read_data_valid is false, and RAM_valid is true. + //*************************************************************************** + assign preloadstage2 = ram_valid_i & (~read_data_valid_i | RD_EN); + + //*************************************************************************** + // preloadstage1 indicates that stage1 needs to be updated. This is true + // whenever the RAM has data (RAM_EMPTY is false), and either RAM_Valid is + // false (indicating that Stage1 needs updating), or preloadstage2 is active + // (indicating that Stage2 is going to update, so Stage1, therefore, must + // also be updated to keep it valid. + //*************************************************************************** + assign preloadstage1 = ((~ram_valid_i | preloadstage2) & ~FIFOEMPTY); + + //*************************************************************************** + // Calculate RAM_REGOUT_EN + // The output registers are controlled by the ram_regout_en signal. + // These registers should be updated either when the output in Stage2 is + // invalid (preloadstage2), OR when the user is reading, in which case the + // Stage2 value will go invalid unless it is replenished. + //*************************************************************************** + assign ram_regout_en = preloadstage2; + + //*************************************************************************** + // Calculate RAM_RD_EN + // RAM_RD_EN will be asserted whenever the RAM needs to be read in order to + // update the value in Stage1. + // One case when this happens is when preloadstage1=true, which indicates + // that the data in Stage1 or Stage2 is invalid, and needs to automatically + // be updated. + // The other case is when the user is reading from the FIFO, which + // guarantees that Stage1 or Stage2 will be invalid on the next clock + // cycle, unless it is replinished by data from the memory. So, as long + // as the RAM has data in it, a read of the RAM should occur. + //*************************************************************************** + assign ram_rd_en = (RD_EN & ~FIFOEMPTY) | preloadstage1; + + //*************************************************************************** + // Calculate RAMVALID_P0_OUT + // RAMVALID_P0_OUT indicates that the data in Stage1 is valid. + // + // If the RAM is being read from on this clock cycle (ram_rd_en=1), then + // RAMVALID_P0_OUT is certainly going to be true. + // If the RAM is not being read from, but the output registers are being + // updated to fill Stage2 (ram_regout_en=1), then Stage1 will be emptying, + // therefore causing RAMVALID_P0_OUT to be false. + // Otherwise, RAMVALID_P0_OUT will remain unchanged. + //*************************************************************************** + // PROCESS regout_valid + always @ (posedge RD_CLK or posedge rd_rst_i) begin + if (rd_rst_i) begin + // asynchronous reset (active high) + ram_valid_i <= 1'b0; + end else begin + if (ram_rd_en == 1'b1) begin + ram_valid_i <= 1'b1; + end else begin + if (ram_regout_en == 1'b1) + ram_valid_i <= 1'b0; + else + ram_valid_i <= ram_valid_i; + end + end //rd_rst_i + end //always + + //*************************************************************************** + // Calculate READ_DATA_VALID + // READ_DATA_VALID indicates whether the value in Stage2 is valid or not. + // Stage2 has valid data whenever Stage1 had valid data and + // ram_regout_en_i=1, such that the data in Stage1 is propogated + // into Stage2. + //*************************************************************************** + always @ (posedge RD_CLK or posedge rd_rst_i) begin + if (rd_rst_i) + read_data_valid_i <= 1'b0; + else + read_data_valid_i <= ram_valid_i | (read_data_valid_i & ~RD_EN); + end //always + + + //************************************************************************** + // Calculate EMPTY + // Defined as the inverse of READ_DATA_VALID + // + // Description: + // + // If read_data_valid_i indicates that the output is not valid, + // and there is no valid data on the output of the ram to preload it + // with, then we will report empty. + // + // If there is no valid data on the output of the ram and we are + // reading, then the FIFO will go empty. + // + //************************************************************************** + always @ (posedge RD_CLK or posedge rd_rst_i) begin + if (rd_rst_i) begin + // asynchronous reset (active high) + empty_i <= 1'b1; + empty_q <= 1'b1; + end else begin + // rising clock edge + empty_i <= (~ram_valid_i & ~read_data_valid_i) | (~ram_valid_i & RD_EN); + empty_q <= empty_i; + end + end //always + + //Register RD_EN from user to calculate USERUNDERFLOW. + always @ (posedge RD_CLK or posedge rd_rst_i) begin + if (rd_rst_i) begin + // asynchronous reset (active high) + rd_en_q <= 1'b0; + end else begin + // rising clock edge + rd_en_q <= RD_EN; + end + end //always + + + //*************************************************************************** + // Calculate user_almost_empty + // user_almost_empty is defined such that, unless more words are written + // to the FIFO, the next read will cause the FIFO to go EMPTY. + // + // In most cases, whenever the output registers are updated (due to a user + // read or a preload condition), then user_almost_empty will update to + // whatever RAM_EMPTY is. + // + // The exception is when the output is valid, the user is not reading, and + // Stage1 is not empty. In this condition, Stage1 will be preloaded from the + // memory, so we need to make sure user_almost_empty deasserts properly under + // this condition. + //*************************************************************************** + always @ (posedge RD_CLK or posedge rd_rst_i) + begin + if (rd_rst_i) // asynchronous reset (active high) + begin + almost_empty_i <= 1'b1; + almost_empty_q <= 1'b1; + end + else // rising clock edge + begin + if ((ram_regout_en) | (~FIFOEMPTY & read_data_valid_i & ~RD_EN)) + begin + almost_empty_i <= FIFOEMPTY; + end + almost_empty_q <= empty_i; + end + end //always + + + assign USEREMPTY = empty_i; + assign USERALMOSTEMPTY = almost_empty_i; + assign FIFORDEN = ram_rd_en; + assign RAMVALID = ram_valid_i; + assign USERVALID = C_USERVALID_LOW ? ~read_data_valid_i : read_data_valid_i; + assign USERUNDERFLOW = C_USERUNDERFLOW_LOW ? ~(empty_q & rd_en_q) : empty_q & rd_en_q; + + always @ (posedge RD_CLK or posedge rd_rst_i) + begin + if (rd_rst_i && C_USE_DOUT_RST == 1) //asynchronous reset (active high) + USERDATA <= hexstr_conv(C_DOUT_RST_VAL); + else // rising clock edge + if (ram_regout_en) + USERDATA <= FIFODATA; + end //always + + + + + +endmodule diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/FIFO_GENERATOR_V4_3_XST.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/FIFO_GENERATOR_V4_3_XST.v new file mode 100644 index 0000000..5c494cd --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/FIFO_GENERATOR_V4_3_XST.v @@ -0,0 +1,317 @@ +/* + * $RDCfile: $ $Revision: 1.3 $ $Date: 2008/09/09 20:25:23 $ + ******************************************************************************* + * + * FIFO Generator - Verilog Behavioral Model + * + ******************************************************************************* + * + * Copyright(C) 2006 by Xilinx, Inc. All rights reserved. + * This text/file contains proprietary, confidential + * information of Xilinx, Inc., is distributed under + * license from Xilinx, Inc., and may be used, copied + * and/or disclosed only pursuant to the terms of a valid + * license agreement with Xilinx, Inc. Xilinx hereby + * grants you a license to use this text/file solely for + * design, simulation, implementation and creation of + * design files limited to Xilinx devices or technologies. + * Use with non-Xilinx devices or technologies is expressly + * prohibited and immediately terminates your license unless + * covered by a separate agreement. + * + * Xilinx is providing theis design, code, or information + * "as-is" solely for use in developing programs and + * solutions for Xilinx devices, with no obligation on the + * part of Xilinx to provide support. By providing this design, + * code, or information as one possible implementation of + * this feature, application or standard. Xilinx is making no + * representation that this implementation is free from any + * claims of infringement. You are responsible for obtaining + * any rights you may require for your implementation. + * Xilinx expressly disclaims any warranty whatsoever with + * respect to the adequacy of the implementation, including + * but not limited to any warranties or representations that this + * implementation is free from claims of infringement, implied + * warranties of merchantability or fitness for a particular + * purpose. + * + * Xilinx products are not intended for use in life support + * appliances, devices, or systems. Use in such applications is + * expressly prohibited. + * + * This copyright and support notice must be retained as part + * of this text at all times. (c)Copyright 1995-2006 Xilinx, Inc. + * All rights reserved. + * + ******************************************************************************* + * + * Filename: fifo_generator_v4_3_bhv.v + * + * Description: + * The verilog behavioral model for the FIFO generator core. + * + ******************************************************************************* + */ + +`timescale 1ps/1ps + +/******************************************************************************* + * Declaration of top-level module + ******************************************************************************/ +module FIFO_GENERATOR_V4_3_XST + ( + BACKUP, + BACKUP_MARKER, + CLK, + DIN, + PROG_EMPTY_THRESH, + PROG_EMPTY_THRESH_ASSERT, + PROG_EMPTY_THRESH_NEGATE, + PROG_FULL_THRESH, + PROG_FULL_THRESH_ASSERT, + PROG_FULL_THRESH_NEGATE, + RD_CLK, + RD_EN, + RD_RST, + RST, + SRST, + WR_CLK, + WR_EN, + WR_RST, + INT_CLK, + + ALMOST_EMPTY, + ALMOST_FULL, + DATA_COUNT, + DOUT, + EMPTY, + FULL, + OVERFLOW, + PROG_EMPTY, + PROG_FULL, + RD_DATA_COUNT, + UNDERFLOW, + VALID, + WR_ACK, + WR_DATA_COUNT, + SBITERR, + DBITERR + ); + +/****************************************************************************** + * Definition of Ports + * + * + ***************************************************************************** + * Definition of Parameters + * + * + *****************************************************************************/ + +/****************************************************************************** + * Declare user parameters and their defaults + *****************************************************************************/ + parameter C_COMMON_CLOCK = 0; + parameter C_COUNT_TYPE = 0; + parameter C_DATA_COUNT_WIDTH = 2; + parameter C_DEFAULT_VALUE = ""; + parameter C_DIN_WIDTH = 8; + parameter C_DOUT_RST_VAL = ""; + parameter C_DOUT_WIDTH = 8; + parameter C_ENABLE_RLOCS = 0; + parameter C_FAMILY = "virtex2"; //Not allowed in Verilog model + parameter C_HAS_ALMOST_EMPTY = 0; + parameter C_HAS_ALMOST_FULL = 0; + parameter C_HAS_BACKUP = 0; + parameter C_HAS_DATA_COUNT = 0; + parameter C_HAS_MEMINIT_FILE = 0; + parameter C_HAS_OVERFLOW = 0; + parameter C_HAS_RD_DATA_COUNT = 0; + parameter C_HAS_RD_RST = 0; + parameter C_HAS_RST = 0; + parameter C_HAS_SRST = 0; + parameter C_HAS_UNDERFLOW = 0; + parameter C_HAS_VALID = 0; + parameter C_HAS_WR_ACK = 0; + parameter C_HAS_WR_DATA_COUNT = 0; + parameter C_HAS_WR_RST = 0; + parameter C_IMPLEMENTATION_TYPE = 0; + parameter C_INIT_WR_PNTR_VAL = 0; + parameter C_MEMORY_TYPE = 1; + parameter C_MIF_FILE_NAME = ""; + parameter C_OPTIMIZATION_MODE = 0; + parameter C_OVERFLOW_LOW = 0; + parameter C_PRELOAD_LATENCY = 1; + parameter C_PRELOAD_REGS = 0; + parameter C_PRIM_FIFO_TYPE = 512; + parameter C_PROG_EMPTY_THRESH_ASSERT_VAL = 0; + parameter C_PROG_EMPTY_THRESH_NEGATE_VAL = 0; + parameter C_PROG_EMPTY_TYPE = 0; + parameter C_PROG_FULL_THRESH_ASSERT_VAL = 0; + parameter C_PROG_FULL_THRESH_NEGATE_VAL = 0; + parameter C_PROG_FULL_TYPE = 0; + parameter C_RD_DATA_COUNT_WIDTH = 2; + parameter C_RD_DEPTH = 256; + parameter C_RD_FREQ = 1; + parameter C_RD_PNTR_WIDTH = 8; + parameter C_UNDERFLOW_LOW = 0; + parameter C_USE_DOUT_RST = 0; + parameter C_USE_EMBEDDED_REG = 0; + parameter C_USE_FIFO16_FLAGS = 0; + parameter C_USE_FWFT_DATA_COUNT = 0; + parameter C_VALID_LOW = 0; + parameter C_WR_ACK_LOW = 0; + parameter C_WR_DATA_COUNT_WIDTH = 2; + parameter C_WR_DEPTH = 256; + parameter C_WR_FREQ = 1; + parameter C_WR_PNTR_WIDTH = 8; + parameter C_WR_RESPONSE_LATENCY = 1; + parameter C_USE_ECC = 0; + parameter C_FULL_FLAGS_RST_VAL = 1; + parameter C_HAS_INT_CLK = 0; + parameter C_MSGON_VAL = 1; + + + /****************************************************************************** + * Declare Input and Output Ports + *****************************************************************************/ + input CLK; + input BACKUP; + input BACKUP_MARKER; + input [C_DIN_WIDTH-1:0] DIN; + input [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH; + input [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_ASSERT; + input [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_NEGATE; + input [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH; + input [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_ASSERT; + input [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_NEGATE; + input RD_CLK; + input RD_EN; + input RD_RST; + input RST; + input SRST; + input WR_CLK; + input WR_EN; + input WR_RST; + input INT_CLK; + + output ALMOST_EMPTY; + output ALMOST_FULL; + output [C_DATA_COUNT_WIDTH-1:0] DATA_COUNT; + output [C_DOUT_WIDTH-1:0] DOUT; + output EMPTY; + output FULL; + output OVERFLOW; + output PROG_EMPTY; + output PROG_FULL; + output VALID; + output [C_RD_DATA_COUNT_WIDTH-1:0] RD_DATA_COUNT; + output UNDERFLOW; + output WR_ACK; + output [C_WR_DATA_COUNT_WIDTH-1:0] WR_DATA_COUNT; + output SBITERR; + output DBITERR; + + //Fixed CRS:432807 in v3.2 //prasanna + FIFO_GENERATOR_V4_3 + #( + .C_COMMON_CLOCK (C_COMMON_CLOCK), + .C_COUNT_TYPE (C_COUNT_TYPE), + .C_DATA_COUNT_WIDTH (C_DATA_COUNT_WIDTH), + .C_DEFAULT_VALUE (C_DEFAULT_VALUE), + .C_DIN_WIDTH (C_DIN_WIDTH), + .C_DOUT_RST_VAL (C_DOUT_RST_VAL), + .C_DOUT_WIDTH (C_DOUT_WIDTH), + .C_ENABLE_RLOCS (C_ENABLE_RLOCS), + .C_FAMILY (C_FAMILY),//Not allowed in Verilog model + .C_HAS_ALMOST_EMPTY (C_HAS_ALMOST_EMPTY), + .C_HAS_ALMOST_FULL (C_HAS_ALMOST_FULL), + .C_HAS_BACKUP (C_HAS_BACKUP), + .C_HAS_DATA_COUNT (C_HAS_DATA_COUNT), + .C_HAS_MEMINIT_FILE (C_HAS_MEMINIT_FILE), + .C_HAS_OVERFLOW (C_HAS_OVERFLOW), + .C_HAS_RD_DATA_COUNT (C_HAS_RD_DATA_COUNT), + .C_HAS_RD_RST (C_HAS_RD_RST), + .C_HAS_RST (C_HAS_RST), + .C_HAS_SRST (C_HAS_SRST), + .C_HAS_UNDERFLOW (C_HAS_UNDERFLOW), + .C_HAS_VALID (C_HAS_VALID), + .C_HAS_WR_ACK (C_HAS_WR_ACK), + .C_HAS_WR_DATA_COUNT (C_HAS_WR_DATA_COUNT), + .C_HAS_WR_RST (C_HAS_WR_RST), + .C_IMPLEMENTATION_TYPE (C_IMPLEMENTATION_TYPE), + .C_INIT_WR_PNTR_VAL (C_INIT_WR_PNTR_VAL), + .C_MEMORY_TYPE (C_MEMORY_TYPE), + .C_MIF_FILE_NAME (C_MIF_FILE_NAME), + .C_OPTIMIZATION_MODE (C_OPTIMIZATION_MODE), + .C_OVERFLOW_LOW (C_OVERFLOW_LOW), + .C_PRELOAD_LATENCY (C_PRELOAD_LATENCY), + .C_PRELOAD_REGS (C_PRELOAD_REGS), + .C_PRIM_FIFO_TYPE (C_PRIM_FIFO_TYPE), + .C_PROG_EMPTY_THRESH_ASSERT_VAL (C_PROG_EMPTY_THRESH_ASSERT_VAL), + .C_PROG_EMPTY_THRESH_NEGATE_VAL (C_PROG_EMPTY_THRESH_NEGATE_VAL), + .C_PROG_EMPTY_TYPE (C_PROG_EMPTY_TYPE), + .C_PROG_FULL_THRESH_ASSERT_VAL (C_PROG_FULL_THRESH_ASSERT_VAL), + .C_PROG_FULL_THRESH_NEGATE_VAL (C_PROG_FULL_THRESH_NEGATE_VAL), + .C_PROG_FULL_TYPE (C_PROG_FULL_TYPE), + .C_RD_DATA_COUNT_WIDTH (C_RD_DATA_COUNT_WIDTH), + .C_RD_DEPTH (C_RD_DEPTH), + .C_RD_FREQ (C_RD_FREQ), + .C_RD_PNTR_WIDTH (C_RD_PNTR_WIDTH), + .C_UNDERFLOW_LOW (C_UNDERFLOW_LOW), + .C_USE_DOUT_RST (C_USE_DOUT_RST), + .C_USE_EMBEDDED_REG (C_USE_EMBEDDED_REG), + .C_USE_FIFO16_FLAGS (C_USE_FIFO16_FLAGS), + .C_USE_FWFT_DATA_COUNT (C_USE_FWFT_DATA_COUNT), + .C_VALID_LOW (C_VALID_LOW), + .C_WR_ACK_LOW (C_WR_ACK_LOW), + .C_WR_DATA_COUNT_WIDTH (C_WR_DATA_COUNT_WIDTH), + .C_WR_DEPTH (C_WR_DEPTH), + .C_WR_FREQ (C_WR_FREQ), + .C_WR_PNTR_WIDTH (C_WR_PNTR_WIDTH), + .C_WR_RESPONSE_LATENCY (C_WR_RESPONSE_LATENCY), + .C_USE_ECC (C_USE_ECC), + .C_FULL_FLAGS_RST_VAL (C_FULL_FLAGS_RST_VAL), + .C_HAS_INT_CLK (C_HAS_INT_CLK), + .C_MSGON_VAL (C_MSGON_VAL) + ) + fifo_generator_v4_3_dut + ( + .BACKUP (BACKUP), + .BACKUP_MARKER (BACKUP_MARKER), + .CLK (CLK), + .RST (RST), + .SRST (SRST), + .WR_CLK (WR_CLK), + .WR_RST (WR_RST), + .RD_CLK (RD_CLK), + .RD_RST (RD_RST), + .DIN (DIN), + .WR_EN (WR_EN), + .RD_EN (RD_EN), + .PROG_EMPTY_THRESH (PROG_EMPTY_THRESH), + .PROG_EMPTY_THRESH_ASSERT (PROG_EMPTY_THRESH_ASSERT), + .PROG_EMPTY_THRESH_NEGATE (PROG_EMPTY_THRESH_NEGATE), + .PROG_FULL_THRESH (PROG_FULL_THRESH), + .PROG_FULL_THRESH_ASSERT (PROG_FULL_THRESH_ASSERT), + .PROG_FULL_THRESH_NEGATE (PROG_FULL_THRESH_NEGATE), + .INT_CLK (INT_CLK), + .DOUT (DOUT), + .FULL (FULL), + .ALMOST_FULL (ALMOST_FULL), + .WR_ACK (WR_ACK), + .OVERFLOW (OVERFLOW), + .EMPTY (EMPTY), + .ALMOST_EMPTY (ALMOST_EMPTY), + .VALID (VALID), + .UNDERFLOW (UNDERFLOW), + .DATA_COUNT (DATA_COUNT), + .RD_DATA_COUNT (RD_DATA_COUNT), + .WR_DATA_COUNT (WR_DATA_COUNT), + .PROG_FULL (PROG_FULL), + .PROG_EMPTY (PROG_EMPTY), + .SBITERR (SBITERR), + .DBITERR (DBITERR) + ); + +endmodule diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/FIFO_GENERATOR_V4_4.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/FIFO_GENERATOR_V4_4.v new file mode 100644 index 0000000..5f1c2ae --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/FIFO_GENERATOR_V4_4.v @@ -0,0 +1,4223 @@ +/* + * $RDCfile: $ $Revision: 1.2 $ $Date: 2008/09/09 20:25:45 $ + ******************************************************************************* + * + * FIFO Generator - Verilog Behavioral Model + * + ******************************************************************************* + * + * Copyright(C) 2006 by Xilinx, Inc. All rights reserved. + * This text/file contains proprietary, confidential + * information of Xilinx, Inc., is distributed under + * license from Xilinx, Inc., and may be used, copied + * and/or disclosed only pursuant to the terms of a valid + * license agreement with Xilinx, Inc. Xilinx hereby + * grants you a license to use this text/file solely for + * design, simulation, implementation and creation of + * design files limited to Xilinx devices or technologies. + * Use with non-Xilinx devices or technologies is expressly + * prohibited and immediately terminates your license unless + * covered by a separate agreement. + * + * Xilinx is providing theis design, code, or information + * "as-is" solely for use in developing programs and + * solutions for Xilinx devices, with no obligation on the + * part of Xilinx to provide support. By providing this design, + * code, or information as one possible implementation of + * this feature, application or standard. Xilinx is making no + * representation that this implementation is free from any + * claims of infringement. You are responsible for obtaining + * any rights you may require for your implementation. + * Xilinx expressly disclaims any warranty whatsoever with + * respect to the adequacy of the implementation, including + * but not limited to any warranties or representations that this + * implementation is free from claims of infringement, implied + * warranties of merchantability or fitness for a particular + * purpose. + * + * Xilinx products are not intended for use in life support + * appliances, devices, or systems. Use in such applications is + * expressly prohibited. + * + * This copyright and support notice must be retained as part + * of this text at all times. (c)Copyright 1995-2006 Xilinx, Inc. + * All rights reserved. + * + ******************************************************************************* + * + * Filename: FIFO_GENERATOR_V4_4.v + * + * Author : Xilinx + * + ******************************************************************************* + * Structure: + * + * fifo_generator_v4_4.vhd + * | + * +-fifo_generator_v4_4_bhv_as + * | + * +-fifo_generator_v4_4_bhv_ss + * | + * +-fifo_generator_v4_4_bhv_preload0 + * + ******************************************************************************* + * Description: + * + * The Verilog behavioral model for the FIFO Generator. + * + * The behavioral model has three parts: + * - The behavioral model for independent clocks FIFOs (_as) + * - The behavioral model for common clock FIFOs (_ss) + * - The "preload logic" block which implements First-word Fall-through + * + ******************************************************************************* + * Description: + * The verilog behavioral model for the FIFO generator core. + * + ******************************************************************************* + */ + +`timescale 1ps/1ps + +/******************************************************************************* + * Declaration of top-level module + ******************************************************************************/ +module FIFO_GENERATOR_V4_4 +( + BACKUP, //not used + BACKUP_MARKER, //not used + CLK, + DIN, + PROG_EMPTY_THRESH, + PROG_EMPTY_THRESH_ASSERT, + PROG_EMPTY_THRESH_NEGATE, + PROG_FULL_THRESH, + PROG_FULL_THRESH_ASSERT, + PROG_FULL_THRESH_NEGATE, + RD_CLK, + RD_EN, + RD_RST, //not used + RST, + SRST, + WR_CLK, + WR_EN, + WR_RST, //not used + INT_CLK, + + ALMOST_EMPTY, + ALMOST_FULL, + DATA_COUNT, + DOUT, + EMPTY, + FULL, + OVERFLOW, + PROG_EMPTY, + PROG_FULL, + RD_DATA_COUNT, + UNDERFLOW, + VALID, + WR_ACK, + WR_DATA_COUNT, + + SBITERR, + DBITERR + ); + +/* + ****************************************************************************** + * Definition of Parameters + ****************************************************************************** + * C_COMMON_CLOCK : Common Clock (1), Independent Clocks (0) + * C_COUNT_TYPE : *not used + * C_DATA_COUNT_WIDTH : Width of DATA_COUNT bus + * C_DEFAULT_VALUE : *not used + * C_DIN_WIDTH : Width of DIN bus + * C_DOUT_RST_VAL : Reset value of DOUT + * C_DOUT_WIDTH : Width of DOUT bus + * C_ENABLE_RLOCS : *not used + * C_FAMILY : not used in bhv model + * C_FULL_FLAGS_RST_VAL : Full flags rst val (0 or 1) + * C_HAS_ALMOST_EMPTY : 1=Core has ALMOST_EMPTY flag + * C_HAS_ALMOST_FULL : 1=Core has ALMOST_FULL flag + * C_HAS_BACKUP : *not used + * C_HAS_DATA_COUNT : 1=Core has DATA_COUNT bus + * C_HAS_INT_CLK : not used in bhv model + * C_HAS_MEMINIT_FILE : *not used + * C_HAS_OVERFLOW : 1=Core has OVERFLOW flag + * C_HAS_RD_DATA_COUNT : 1=Core has RD_DATA_COUNT bus + * C_HAS_RD_RST : *not used + * C_HAS_RST : 1=Core has Async Rst + * C_HAS_SRST : 1=Core has Sync Rst + * C_HAS_UNDERFLOW : 1=Core has UNDERFLOW flag + * C_HAS_VALID : 1=Core has VALID flag + * C_HAS_WR_ACK : 1=Core has WR_ACK flag + * C_HAS_WR_DATA_COUNT : 1=Core has WR_DATA_COUNT bus + * C_HAS_WR_RST : *not used + * C_IMPLEMENTATION_TYPE : 0=Common-Clock Bram/Dram + * 1=Common-Clock ShiftRam + * 2=Indep. Clocks Bram/Dram + * 3=Virtex-4 Built-in + * 4=Virtex-5 Built-in + * C_INIT_WR_PNTR_VAL : *not used + * C_MEMORY_TYPE : 1=Block RAM + * 2=Distributed RAM + * 3=Shift RAM + * 4=Built-in FIFO + * C_MIF_FILE_NAME : *not used + * C_OPTIMIZATION_MODE : *not used + * C_OVERFLOW_LOW : 1=OVERFLOW active low + * C_PRELOAD_LATENCY : Latency of read: 0, 1, 2 + * C_PRELOAD_REGS : 1=Use output registers + * C_PRIM_FIFO_TYPE : not used in bhv model + * C_PROG_EMPTY_THRESH_ASSERT_VAL: PROG_EMPTY assert threshold + * C_PROG_EMPTY_THRESH_NEGATE_VAL: PROG_EMPTY negate threshold + * C_PROG_EMPTY_TYPE : 0=No programmable empty + * 1=Single prog empty thresh constant + * 2=Multiple prog empty thresh constants + * 3=Single prog empty thresh input + * 4=Multiple prog empty thresh inputs + * C_PROG_FULL_THRESH_ASSERT_VAL : PROG_FULL assert threshold + * C_PROG_FULL_THRESH_NEGATE_VAL : PROG_FULL negate threshold + * C_PROG_FULL_TYPE : 0=No prog full + * 1=Single prog full thresh constant + * 2=Multiple prog full thresh constants + * 3=Single prog full thresh input + * 4=Multiple prog full thresh inputs + * C_RD_DATA_COUNT_WIDTH : Width of RD_DATA_COUNT bus + * C_RD_DEPTH : Depth of read interface (2^N) + * C_RD_FREQ : not used in bhv model + * C_RD_PNTR_WIDTH : always log2(C_RD_DEPTH) + * C_UNDERFLOW_LOW : 1=UNDERFLOW active low + * C_USE_DOUT_RST : 1=Resets DOUT on RST + * C_USE_ECC : not used in bhv model + * C_USE_EMBEDDED_REG : 1=Use BRAM embedded output register + * C_USE_FIFO16_FLAGS : not used in bhv model + * C_USE_FWFT_DATA_COUNT : 1=Use extra logic for FWFT data count + * C_VALID_LOW : 1=VALID active low + * C_WR_ACK_LOW : 1=WR_ACK active low + * C_WR_DATA_COUNT_WIDTH : Width of WR_DATA_COUNT bus + * C_WR_DEPTH : Depth of write interface (2^N) + * C_WR_FREQ : not used in bhv model + * C_WR_PNTR_WIDTH : always log2(C_WR_DEPTH) + * C_WR_RESPONSE_LATENCY : *not used + * C_MSGON_VAL : *not used by bhv model + ****************************************************************************** + * Definition of Ports + ****************************************************************************** + * BACKUP : Not used + * BACKUP_MARKER: Not used + * CLK : Clock + * DIN : Input data bus + * PROG_EMPTY_THRESH : Threshold for Programmable Empty Flag + * PROG_EMPTY_THRESH_ASSERT: Threshold for Programmable Empty Flag + * PROG_EMPTY_THRESH_NEGATE: Threshold for Programmable Empty Flag + * PROG_FULL_THRESH : Threshold for Programmable Full Flag + * PROG_FULL_THRESH_ASSERT : Threshold for Programmable Full Flag + * PROG_FULL_THRESH_NEGATE : Threshold for Programmable Full Flag + * RD_CLK : Read Domain Clock + * RD_EN : Read enable + * RD_RST : Not used + * RST : Asynchronous Reset + * SRST : Synchronous Reset + * WR_CLK : Write Domain Clock + * WR_EN : Write enable + * WR_RST : Not used + * INT_CLK : Internal Clock + * ALMOST_EMPTY : One word remaining in FIFO + * ALMOST_FULL : One empty space remaining in FIFO + * DATA_COUNT : Number of data words in fifo( synchronous to CLK) + * DOUT : Output data bus + * EMPTY : Empty flag + * FULL : Full flag + * OVERFLOW : Last write rejected + * PROG_EMPTY : Programmable Empty Flag + * PROG_FULL : Programmable Full Flag + * RD_DATA_COUNT: Number of data words in fifo (synchronous to RD_CLK) + * UNDERFLOW : Last read rejected + * VALID : Last read acknowledged, DOUT bus VALID + * WR_ACK : Last write acknowledged + * WR_DATA_COUNT: Number of data words in fifo (synchronous to WR_CLK) + * SBITERR : Single Bit ECC Error Detected + * DBITERR : Double Bit ECC Error Detected + ****************************************************************************** + */ + + + /**************************************************************************** + * Declare user parameters and their defaults + *****************************************************************************/ + parameter C_COMMON_CLOCK = 0; + parameter C_COUNT_TYPE = 0; //not used + parameter C_DATA_COUNT_WIDTH = 2; + parameter C_DEFAULT_VALUE = ""; //not used + parameter C_DIN_WIDTH = 8; + parameter C_DOUT_RST_VAL = ""; + parameter C_DOUT_WIDTH = 8; + parameter C_ENABLE_RLOCS = 0; //not used + parameter C_FAMILY = "virtex2"; //not used in bhv model + parameter C_FULL_FLAGS_RST_VAL = 1; + parameter C_HAS_ALMOST_EMPTY = 0; + parameter C_HAS_ALMOST_FULL = 0; + parameter C_HAS_BACKUP = 0; //not used + parameter C_HAS_DATA_COUNT = 0; + parameter C_HAS_INT_CLK = 0; //not used in bhv model + parameter C_HAS_MEMINIT_FILE = 0; //not used + parameter C_HAS_OVERFLOW = 0; + parameter C_HAS_RD_DATA_COUNT = 0; + parameter C_HAS_RD_RST = 0; //not used + parameter C_HAS_RST = 0; + parameter C_HAS_SRST = 0; + parameter C_HAS_UNDERFLOW = 0; + parameter C_HAS_VALID = 0; + parameter C_HAS_WR_ACK = 0; + parameter C_HAS_WR_DATA_COUNT = 0; + parameter C_HAS_WR_RST = 0; //not used + parameter C_IMPLEMENTATION_TYPE = 0; + parameter C_INIT_WR_PNTR_VAL = 0; //not used + parameter C_MEMORY_TYPE = 1; + parameter C_MIF_FILE_NAME = ""; //not used + parameter C_OPTIMIZATION_MODE = 0; //not used + parameter C_OVERFLOW_LOW = 0; + parameter C_PRELOAD_LATENCY = 1; + parameter C_PRELOAD_REGS = 0; + parameter C_PRIM_FIFO_TYPE = 512; //not used in bhv model + parameter C_PROG_EMPTY_THRESH_ASSERT_VAL = 0; + parameter C_PROG_EMPTY_THRESH_NEGATE_VAL = 0; + parameter C_PROG_EMPTY_TYPE = 0; + parameter C_PROG_FULL_THRESH_ASSERT_VAL = 0; + parameter C_PROG_FULL_THRESH_NEGATE_VAL = 0; + parameter C_PROG_FULL_TYPE = 0; + parameter C_RD_DATA_COUNT_WIDTH = 2; + parameter C_RD_DEPTH = 256; + parameter C_RD_FREQ = 1; //not used in bhv model + parameter C_RD_PNTR_WIDTH = 8; + parameter C_UNDERFLOW_LOW = 0; + parameter C_USE_DOUT_RST = 0; + parameter C_USE_ECC = 0; //not used in bhv model + parameter C_USE_EMBEDDED_REG = 0; + parameter C_USE_FIFO16_FLAGS = 0; //not used in bhv model + parameter C_USE_FWFT_DATA_COUNT = 0; + parameter C_VALID_LOW = 0; + parameter C_WR_ACK_LOW = 0; + parameter C_WR_DATA_COUNT_WIDTH = 2; + parameter C_WR_DEPTH = 256; + parameter C_WR_FREQ = 1; //not used in bhv model + parameter C_WR_PNTR_WIDTH = 8; + parameter C_WR_RESPONSE_LATENCY = 1; //not used + parameter C_MSGON_VAL = 1; //not used + + + + /***************************************************************************** + * Derived parameters + ****************************************************************************/ + //There are 2 Verilog behavioral models + // 0 = Common-Clock FIFO/ShiftRam FIFO + // 1 = Independent Clocks FIFO + parameter C_VERILOG_IMPL = (C_IMPLEMENTATION_TYPE==0 ? 0 : + (C_IMPLEMENTATION_TYPE==1 ? 0 : + (C_IMPLEMENTATION_TYPE==2 ? 1 : 0))); + + /***************************************************************************** + * Declare Input and Output Ports + ****************************************************************************/ + input CLK; + input BACKUP; + input BACKUP_MARKER; + input [C_DIN_WIDTH-1:0] DIN; + input [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH; + input [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_ASSERT; + input [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_NEGATE; + input [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH; + input [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_ASSERT; + input [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_NEGATE; + input RD_CLK; + input RD_EN; + input RD_RST; + input RST; + input SRST; + input WR_CLK; + input WR_EN; + input WR_RST; + input INT_CLK; + + output ALMOST_EMPTY; + output ALMOST_FULL; + output [C_DATA_COUNT_WIDTH-1:0] DATA_COUNT; + output [C_DOUT_WIDTH-1:0] DOUT; + output EMPTY; + output FULL; + output OVERFLOW; + output PROG_EMPTY; + output PROG_FULL; + output VALID; + output [C_RD_DATA_COUNT_WIDTH-1:0] RD_DATA_COUNT; + output UNDERFLOW; + output WR_ACK; + output [C_WR_DATA_COUNT_WIDTH-1:0] WR_DATA_COUNT; + output SBITERR; + output DBITERR; + + + wire ALMOST_EMPTY; + wire ALMOST_FULL; + wire [C_DATA_COUNT_WIDTH-1:0] DATA_COUNT; + wire [C_DOUT_WIDTH-1:0] DOUT; + wire EMPTY; + wire FULL; + wire OVERFLOW; + wire PROG_EMPTY; + wire PROG_FULL; + wire VALID; + wire [C_RD_DATA_COUNT_WIDTH-1:0] RD_DATA_COUNT; + wire UNDERFLOW; + wire WR_ACK; + wire [C_WR_DATA_COUNT_WIDTH-1:0] WR_DATA_COUNT; + + + wire RD_CLK_P0_IN; + wire RST_P0_IN; + wire RD_EN_FIFO_IN; + wire RD_EN_P0_IN; + + wire ALMOST_EMPTY_FIFO_OUT; + wire ALMOST_FULL_FIFO_OUT; + wire [C_DATA_COUNT_WIDTH-1:0] DATA_COUNT_FIFO_OUT; + wire [C_DOUT_WIDTH-1:0] DOUT_FIFO_OUT; + wire EMPTY_FIFO_OUT; + wire FULL_FIFO_OUT; + wire OVERFLOW_FIFO_OUT; + wire PROG_EMPTY_FIFO_OUT; + wire PROG_FULL_FIFO_OUT; + wire VALID_FIFO_OUT; + wire [C_RD_DATA_COUNT_WIDTH-1:0] RD_DATA_COUNT_FIFO_OUT; + wire UNDERFLOW_FIFO_OUT; + wire WR_ACK_FIFO_OUT; + wire [C_WR_DATA_COUNT_WIDTH-1:0] WR_DATA_COUNT_FIFO_OUT; + + + //*************************************************************************** + // Internal Signals + // The core uses either the internal_ wires or the preload0_ wires depending + // on whether the core uses Preload0 or not. + // When using preload0, the internal signals connect the internal core to + // the preload logic, and the external core's interfaces are tied to the + // preload0 signals from the preload logic. + //*************************************************************************** + wire [C_DOUT_WIDTH-1:0] DATA_P0_OUT; + wire VALID_P0_OUT; + wire EMPTY_P0_OUT; + wire ALMOSTEMPTY_P0_OUT; + reg EMPTY_P0_OUT_Q; + reg ALMOSTEMPTY_P0_OUT_Q; + wire UNDERFLOW_P0_OUT; + wire RDEN_P0_OUT; + wire [C_DOUT_WIDTH-1:0] DATA_P0_IN; + wire EMPTY_P0_IN; + reg [31:0] DATA_COUNT_FWFT; + reg SS_FWFT_WR ; + reg SS_FWFT_RD ; + + assign SBITERR = 1'b0; + assign DBITERR = 1'b0; + + +// Choose the behavioral model to instantiate based on the C_VERILOG_IMPL +// parameter (1=Independent Clocks, 0=Common Clock) +generate +case (C_VERILOG_IMPL) +0 : begin : block1 + //Common Clock Behavioral Model + fifo_generator_v4_4_bhv_ver_ss + #( + C_DATA_COUNT_WIDTH, + C_DIN_WIDTH, + C_DOUT_RST_VAL, + C_DOUT_WIDTH, + C_FULL_FLAGS_RST_VAL, + C_HAS_ALMOST_EMPTY, + C_HAS_ALMOST_FULL, + C_HAS_DATA_COUNT, + C_HAS_OVERFLOW, + C_HAS_RD_DATA_COUNT, + C_HAS_RST, + C_HAS_SRST, + C_HAS_UNDERFLOW, + C_HAS_VALID, + C_HAS_WR_ACK, + C_HAS_WR_DATA_COUNT, + C_IMPLEMENTATION_TYPE, + C_MEMORY_TYPE, + C_OVERFLOW_LOW, + C_PRELOAD_LATENCY, + C_PRELOAD_REGS, + C_PROG_EMPTY_THRESH_ASSERT_VAL, + C_PROG_EMPTY_THRESH_NEGATE_VAL, + C_PROG_EMPTY_TYPE, + C_PROG_FULL_THRESH_ASSERT_VAL, + C_PROG_FULL_THRESH_NEGATE_VAL, + C_PROG_FULL_TYPE, + C_RD_DATA_COUNT_WIDTH, + C_RD_DEPTH, + C_RD_PNTR_WIDTH, + C_UNDERFLOW_LOW, + C_USE_DOUT_RST, + C_USE_EMBEDDED_REG, + C_USE_FWFT_DATA_COUNT, + C_VALID_LOW, + C_WR_ACK_LOW, + C_WR_DATA_COUNT_WIDTH, + C_WR_DEPTH, + C_WR_PNTR_WIDTH + ) + gen_ss + ( + .CLK (CLK), + .RST (RST), + .SRST (SRST), + .DIN (DIN), + .WR_EN (WR_EN), + .RD_EN (RD_EN_FIFO_IN), + .PROG_EMPTY_THRESH (PROG_EMPTY_THRESH), + .PROG_EMPTY_THRESH_ASSERT (PROG_EMPTY_THRESH_ASSERT), + .PROG_EMPTY_THRESH_NEGATE (PROG_EMPTY_THRESH_NEGATE), + .PROG_FULL_THRESH (PROG_FULL_THRESH), + .PROG_FULL_THRESH_ASSERT (PROG_FULL_THRESH_ASSERT), + .PROG_FULL_THRESH_NEGATE (PROG_FULL_THRESH_NEGATE), + .DOUT (DOUT_FIFO_OUT), + .FULL (FULL_FIFO_OUT), + .ALMOST_FULL (ALMOST_FULL_FIFO_OUT), + .WR_ACK (WR_ACK_FIFO_OUT), + .OVERFLOW (OVERFLOW_FIFO_OUT), + .EMPTY (EMPTY_FIFO_OUT), + .ALMOST_EMPTY (ALMOST_EMPTY_FIFO_OUT), + .VALID (VALID_FIFO_OUT), + .UNDERFLOW (UNDERFLOW_FIFO_OUT), + .DATA_COUNT (DATA_COUNT_FIFO_OUT), + .PROG_FULL (PROG_FULL_FIFO_OUT), + .PROG_EMPTY (PROG_EMPTY_FIFO_OUT) + ); +end +1 : begin : block1 + //Independent Clocks Behavioral Model + fifo_generator_v4_4_bhv_ver_as + #( + C_DATA_COUNT_WIDTH, + C_DIN_WIDTH, + C_DOUT_RST_VAL, + C_DOUT_WIDTH, + C_FULL_FLAGS_RST_VAL, + C_HAS_ALMOST_EMPTY, + C_HAS_ALMOST_FULL, + C_HAS_DATA_COUNT, + C_HAS_OVERFLOW, + C_HAS_RD_DATA_COUNT, + C_HAS_RST, + C_HAS_UNDERFLOW, + C_HAS_VALID, + C_HAS_WR_ACK, + C_HAS_WR_DATA_COUNT, + C_IMPLEMENTATION_TYPE, + C_MEMORY_TYPE, + C_OVERFLOW_LOW, + C_PRELOAD_LATENCY, + C_PRELOAD_REGS, + C_PROG_EMPTY_THRESH_ASSERT_VAL, + C_PROG_EMPTY_THRESH_NEGATE_VAL, + C_PROG_EMPTY_TYPE, + C_PROG_FULL_THRESH_ASSERT_VAL, + C_PROG_FULL_THRESH_NEGATE_VAL, + C_PROG_FULL_TYPE, + C_RD_DATA_COUNT_WIDTH, + C_RD_DEPTH, + C_RD_PNTR_WIDTH, + C_UNDERFLOW_LOW, + C_USE_DOUT_RST, + C_USE_EMBEDDED_REG, + C_USE_FWFT_DATA_COUNT, + C_VALID_LOW, + C_WR_ACK_LOW, + C_WR_DATA_COUNT_WIDTH, + C_WR_DEPTH, + C_WR_PNTR_WIDTH + ) + gen_as + ( + .WR_CLK (WR_CLK), + .RD_CLK (RD_CLK), + .RST (RST), + .DIN (DIN), + .WR_EN (WR_EN), + .RD_EN (RD_EN_FIFO_IN), + .PROG_EMPTY_THRESH (PROG_EMPTY_THRESH), + .PROG_EMPTY_THRESH_ASSERT (PROG_EMPTY_THRESH_ASSERT), + .PROG_EMPTY_THRESH_NEGATE (PROG_EMPTY_THRESH_NEGATE), + .PROG_FULL_THRESH (PROG_FULL_THRESH), + .PROG_FULL_THRESH_ASSERT (PROG_FULL_THRESH_ASSERT), + .PROG_FULL_THRESH_NEGATE (PROG_FULL_THRESH_NEGATE), + .DOUT (DOUT_FIFO_OUT), + .FULL (FULL_FIFO_OUT), + .ALMOST_FULL (ALMOST_FULL_FIFO_OUT), + .WR_ACK (WR_ACK_FIFO_OUT), + .OVERFLOW (OVERFLOW_FIFO_OUT), + .EMPTY (EMPTY_FIFO_OUT), + .ALMOST_EMPTY (ALMOST_EMPTY_FIFO_OUT), + .VALID (VALID_FIFO_OUT), + .UNDERFLOW (UNDERFLOW_FIFO_OUT), + .RD_DATA_COUNT (RD_DATA_COUNT_FIFO_OUT), + .WR_DATA_COUNT (WR_DATA_COUNT_FIFO_OUT), + .PROG_FULL (PROG_FULL_FIFO_OUT), + .PROG_EMPTY (PROG_EMPTY_FIFO_OUT) + ); +end + +default : begin : block1 + //Independent Clocks Behavioral Model + fifo_generator_v4_4_bhv_ver_as + #( + C_DATA_COUNT_WIDTH, + C_DIN_WIDTH, + C_DOUT_RST_VAL, + C_DOUT_WIDTH, + C_FULL_FLAGS_RST_VAL, + C_HAS_ALMOST_EMPTY, + C_HAS_ALMOST_FULL, + C_HAS_DATA_COUNT, + C_HAS_OVERFLOW, + C_HAS_RD_DATA_COUNT, + C_HAS_RST, + C_HAS_UNDERFLOW, + C_HAS_VALID, + C_HAS_WR_ACK, + C_HAS_WR_DATA_COUNT, + C_IMPLEMENTATION_TYPE, + C_MEMORY_TYPE, + C_OVERFLOW_LOW, + C_PRELOAD_LATENCY, + C_PRELOAD_REGS, + C_PROG_EMPTY_THRESH_ASSERT_VAL, + C_PROG_EMPTY_THRESH_NEGATE_VAL, + C_PROG_EMPTY_TYPE, + C_PROG_FULL_THRESH_ASSERT_VAL, + C_PROG_FULL_THRESH_NEGATE_VAL, + C_PROG_FULL_TYPE, + C_RD_DATA_COUNT_WIDTH, + C_RD_DEPTH, + C_RD_PNTR_WIDTH, + C_UNDERFLOW_LOW, + C_USE_DOUT_RST, + C_USE_EMBEDDED_REG, + C_USE_FWFT_DATA_COUNT, + C_VALID_LOW, + C_WR_ACK_LOW, + C_WR_DATA_COUNT_WIDTH, + C_WR_DEPTH, + C_WR_PNTR_WIDTH + ) + gen_as + ( + .WR_CLK (WR_CLK), + .RD_CLK (RD_CLK), + .RST (RST), + .DIN (DIN), + .WR_EN (WR_EN), + .RD_EN (RD_EN_FIFO_IN), + .PROG_EMPTY_THRESH (PROG_EMPTY_THRESH), + .PROG_EMPTY_THRESH_ASSERT (PROG_EMPTY_THRESH_ASSERT), + .PROG_EMPTY_THRESH_NEGATE (PROG_EMPTY_THRESH_NEGATE), + .PROG_FULL_THRESH (PROG_FULL_THRESH), + .PROG_FULL_THRESH_ASSERT (PROG_FULL_THRESH_ASSERT), + .PROG_FULL_THRESH_NEGATE (PROG_FULL_THRESH_NEGATE), + .DOUT (DOUT_FIFO_OUT), + .FULL (FULL_FIFO_OUT), + .ALMOST_FULL (ALMOST_FULL_FIFO_OUT), + .WR_ACK (WR_ACK_FIFO_OUT), + .OVERFLOW (OVERFLOW_FIFO_OUT), + .EMPTY (EMPTY_FIFO_OUT), + .ALMOST_EMPTY (ALMOST_EMPTY_FIFO_OUT), + .VALID (VALID_FIFO_OUT), + .UNDERFLOW (UNDERFLOW_FIFO_OUT), + .RD_DATA_COUNT (RD_DATA_COUNT_FIFO_OUT), + .WR_DATA_COUNT (WR_DATA_COUNT_FIFO_OUT), + .PROG_FULL (PROG_FULL_FIFO_OUT), + .PROG_EMPTY (PROG_EMPTY_FIFO_OUT) + ); +end + +endcase +endgenerate + + + //************************************************************************** + // Connect Internal Signals + // (Signals labeled internal_*) + // In the normal case, these signals tie directly to the FIFO's inputs and + // outputs. + // In the case of Preload Latency 0 or 1, there are intermediate + // signals between the internal FIFO and the preload logic. + //************************************************************************** + + + //*********************************************** + // If First-Word Fall-Through, instantiate + // the preload0 (FWFT) module + //*********************************************** + generate + if (C_PRELOAD_REGS==1 && C_PRELOAD_LATENCY==0) begin : block2 + + + fifo_generator_v4_4_bhv_ver_preload0 + #( + C_DOUT_RST_VAL, + C_DOUT_WIDTH, + C_HAS_RST, + C_HAS_SRST, + C_USE_DOUT_RST, + C_VALID_LOW, + C_UNDERFLOW_LOW + ) + fgpl0 + ( + .RD_CLK (RD_CLK_P0_IN), + .RD_RST (RST_P0_IN), + .SRST (SRST), + .RD_EN (RD_EN_P0_IN), + .FIFOEMPTY (EMPTY_P0_IN), + .FIFODATA (DATA_P0_IN), + .USERDATA (DATA_P0_OUT), + .USERVALID (VALID_P0_OUT), + .USEREMPTY (EMPTY_P0_OUT), + .USERALMOSTEMPTY (ALMOSTEMPTY_P0_OUT), + .USERUNDERFLOW (UNDERFLOW_P0_OUT), + .RAMVALID (RAMVALID_P0_OUT), + .FIFORDEN (RDEN_P0_OUT) + ); + + + //*********************************************** + // Connect inputs to preload (FWFT) module + //*********************************************** + //Connect the RD_CLK of the Preload (FWFT) module to CLK if we + // have a common-clock FIFO, or RD_CLK if we have an + // independent clock FIFO + assign RD_CLK_P0_IN = ((C_VERILOG_IMPL == 0) ? CLK : RD_CLK); + assign RST_P0_IN = RST; + assign RD_EN_P0_IN = RD_EN; + assign EMPTY_P0_IN = EMPTY_FIFO_OUT; + assign DATA_P0_IN = DOUT_FIFO_OUT; + + //*********************************************** + // Connect outputs from preload (FWFT) module + //*********************************************** + assign DOUT = DATA_P0_OUT; + assign VALID = VALID_P0_OUT ; + assign EMPTY = EMPTY_P0_OUT; + assign ALMOST_EMPTY = ALMOSTEMPTY_P0_OUT; + assign UNDERFLOW = UNDERFLOW_P0_OUT ; + + assign RD_EN_FIFO_IN = RDEN_P0_OUT; + + + //*********************************************** + // Create DATA_COUNT from First-Word Fall-Through + // data count + //*********************************************** + assign DATA_COUNT = (C_USE_FWFT_DATA_COUNT == 0)? DATA_COUNT_FIFO_OUT: + (C_DATA_COUNT_WIDTH>C_RD_PNTR_WIDTH) ? DATA_COUNT_FWFT[C_RD_PNTR_WIDTH:0] : + DATA_COUNT_FWFT[C_RD_PNTR_WIDTH:C_RD_PNTR_WIDTH-C_DATA_COUNT_WIDTH+1]; + + //*********************************************** + // Create DATA_COUNT from First-Word Fall-Through + // data count + //*********************************************** + always @ (posedge RD_CLK or posedge RST) begin + if (RST) begin + EMPTY_P0_OUT_Q <= 1; + ALMOSTEMPTY_P0_OUT_Q <= 1; + end else begin + EMPTY_P0_OUT_Q <= EMPTY_P0_OUT; + ALMOSTEMPTY_P0_OUT_Q <= ALMOSTEMPTY_P0_OUT; + end + end //always + + + //*********************************************** + // logic for common-clock data count when FWFT is selected + //*********************************************** + initial begin + SS_FWFT_RD = 1'b0; + DATA_COUNT_FWFT = 0 ; + SS_FWFT_WR = 1'b0 ; + end //initial + + + //*********************************************** + // common-clock data count is implemented as an + // up-down counter. SS_FWFT_WR and SS_FWFT_RD + // are the up/down enables for the counter. + //*********************************************** + always @ (RD_EN or VALID_P0_OUT or WR_EN or FULL_FIFO_OUT) begin + SS_FWFT_RD = RD_EN && VALID_P0_OUT ; + SS_FWFT_WR = (WR_EN && (~FULL_FIFO_OUT)) ; + end + + //*********************************************** + // common-clock data count is implemented as an + // up-down counter for FWFT. This always block + // calculates the counter. + //*********************************************** + always @ (posedge RD_CLK_P0_IN or posedge RST) begin + if (RST && (C_HAS_RST == 1) ) begin + DATA_COUNT_FWFT <= 0; + end else begin + if (SRST && (C_HAS_SRST == 1) ) begin + DATA_COUNT_FWFT <= 0; + end else begin + case ( {SS_FWFT_WR, SS_FWFT_RD}) + 2'b00: DATA_COUNT_FWFT <= DATA_COUNT_FWFT ; + 2'b01: DATA_COUNT_FWFT <= DATA_COUNT_FWFT - 1 ; + 2'b10: DATA_COUNT_FWFT <= DATA_COUNT_FWFT + 1 ; + 2'b11: DATA_COUNT_FWFT <= DATA_COUNT_FWFT ; + endcase + end //if SRST + end //IF RST + end //always + + + end else begin : block2 //if !(C_PRELOAD_REGS==1 && C_PRELOAD_LATENCY==0) + + //*********************************************** + // If NOT First-Word Fall-Through, wire the outputs + // of the internal _ss or _as FIFO directly to the + // output, and do not instantiate the preload0 + // module. + //*********************************************** + + assign RD_CLK_P0_IN = 0; + assign RST_P0_IN = 0; + assign RD_EN_P0_IN = 0; + + assign RD_EN_FIFO_IN = RD_EN; + + assign DOUT = DOUT_FIFO_OUT; + assign DATA_P0_IN = 0; + assign VALID = VALID_FIFO_OUT; + assign EMPTY = EMPTY_FIFO_OUT; + assign ALMOST_EMPTY = ALMOST_EMPTY_FIFO_OUT; + assign EMPTY_P0_IN = 0; + assign UNDERFLOW = UNDERFLOW_FIFO_OUT; + assign DATA_COUNT = DATA_COUNT_FIFO_OUT; + + end //if !(C_PRELOAD_REGS==1 && C_PRELOAD_LATENCY==0) + endgenerate + + + //*********************************************** + // Connect user flags to internal signals + //*********************************************** + + //If we are using extra logic for the FWFT data count, then override the + //RD_DATA_COUNT output when we are EMPTY or ALMOST_EMPTY. + //RD_DATA_COUNT is 0 when EMPTY and 1 when ALMOST_EMPTY. + generate + if (C_USE_FWFT_DATA_COUNT==1 && (C_RD_DATA_COUNT_WIDTH>C_RD_PNTR_WIDTH) ) begin : block3 + assign RD_DATA_COUNT = (EMPTY_P0_OUT_Q | RST) ? 0 : (ALMOSTEMPTY_P0_OUT_Q ? 1 : RD_DATA_COUNT_FIFO_OUT); + end //block3 + endgenerate + + //If we are using extra logic for the FWFT data count, then override the + //RD_DATA_COUNT output when we are EMPTY or ALMOST_EMPTY. + //Due to asymmetric ports, RD_DATA_COUNT is 0 when EMPTY or ALMOST_EMPTY. + generate + if (C_USE_FWFT_DATA_COUNT==1 && (C_RD_DATA_COUNT_WIDTH <=C_RD_PNTR_WIDTH) ) begin : block30 + assign RD_DATA_COUNT = (EMPTY_P0_OUT_Q | RST) ? 0 : (ALMOSTEMPTY_P0_OUT_Q ? 0 : RD_DATA_COUNT_FIFO_OUT); + end //block30 + endgenerate + + //If we are not using extra logic for the FWFT data count, + //then connect RD_DATA_COUNT to the RD_DATA_COUNT from the + //internal FIFO instance + generate + if (C_USE_FWFT_DATA_COUNT==0 ) begin : block31 + assign RD_DATA_COUNT = RD_DATA_COUNT_FIFO_OUT; + end + endgenerate + + //Always connect WR_DATA_COUNT to the WR_DATA_COUNT from the internal + //FIFO instance + generate + if (C_USE_FWFT_DATA_COUNT==1) begin : block4 + assign WR_DATA_COUNT = WR_DATA_COUNT_FIFO_OUT; + end + else begin : block4 + assign WR_DATA_COUNT = WR_DATA_COUNT_FIFO_OUT; + end + endgenerate + + + //Connect other flags to the internal FIFO instance + assign FULL = FULL_FIFO_OUT; + assign ALMOST_FULL = ALMOST_FULL_FIFO_OUT; + assign WR_ACK = WR_ACK_FIFO_OUT; + assign OVERFLOW = OVERFLOW_FIFO_OUT; + assign PROG_FULL = PROG_FULL_FIFO_OUT; + assign PROG_EMPTY = PROG_EMPTY_FIFO_OUT; + + + // if an asynchronous FIFO has been selected, display a message that the FIFO + // will not be cycle-accurate in simulation + initial begin + if (C_IMPLEMENTATION_TYPE == 2) begin + $display("Warning in %m at time %t: When using an asynchronous configuration for the FIFO Generator, the behavioral model is not cycle-accurate. You may wish to choose the structural simulation model instead of the behavioral model. This will ensure accurate behavior and latencies during simulation. You can enable this from CORE Generator by selecting Project -> Project Options -> Generation tab -> Structural Simulation. See the FIFO Generator User Guide for more information.", $time); + end else if (C_IMPLEMENTATION_TYPE == 3 || C_IMPLEMENTATION_TYPE == 4) begin + //$display("Failure in %m at time %t: Use of Virtex-4 and Virtex-5 built-in FIFO configurations is currently not supported. Please use the structural simulation model. You can enable this from CORE Generator by selecting Project -> Project Options -> Generation tab -> Structural Simulation. See the FIFO Generator User Guide for more information.", $time); + $display("Failure in %m at time %t: Behavioral models for Virtex-4 and Virtex-5 built-in FIFO configurations is currently not supported. Please select the structural simulation model option in CORE Generator. You can enable this in CORE Generator by selecting Project -> Project Options -> Generation tab -> Structural Simulation. See the FIFO Generator User Guide for more information.", $time); + $finish; + end + end //initial + +endmodule //FIFO_GENERATOR_V4_4 + + + +/******************************************************************************* + * Declaration of Independent-Clocks FIFO Module + ******************************************************************************/ +module fifo_generator_v4_4_bhv_ver_as + ( + WR_CLK, RD_CLK, RST, DIN, WR_EN, RD_EN, + PROG_EMPTY_THRESH, PROG_EMPTY_THRESH_ASSERT, PROG_EMPTY_THRESH_NEGATE, + PROG_FULL_THRESH, PROG_FULL_THRESH_ASSERT, PROG_FULL_THRESH_NEGATE, + DOUT, FULL, ALMOST_FULL, WR_ACK, OVERFLOW, EMPTY, ALMOST_EMPTY, VALID, + UNDERFLOW, RD_DATA_COUNT, WR_DATA_COUNT, PROG_FULL, PROG_EMPTY + ); + + /*************************************************************************** + * Declare user parameters and their defaults + ***************************************************************************/ + parameter C_DATA_COUNT_WIDTH = 2; + parameter C_DIN_WIDTH = 8; + parameter C_DOUT_RST_VAL = ""; + parameter C_DOUT_WIDTH = 8; + parameter C_FULL_FLAGS_RST_VAL = 1; + parameter C_HAS_ALMOST_EMPTY = 0; + parameter C_HAS_ALMOST_FULL = 0; + parameter C_HAS_DATA_COUNT = 0; + parameter C_HAS_OVERFLOW = 0; + parameter C_HAS_RD_DATA_COUNT = 0; + parameter C_HAS_RST = 0; + parameter C_HAS_UNDERFLOW = 0; + parameter C_HAS_VALID = 0; + parameter C_HAS_WR_ACK = 0; + parameter C_HAS_WR_DATA_COUNT = 0; + parameter C_IMPLEMENTATION_TYPE = 0; + parameter C_MEMORY_TYPE = 1; + parameter C_OVERFLOW_LOW = 0; + parameter C_PRELOAD_LATENCY = 1; + parameter C_PRELOAD_REGS = 0; + parameter C_PROG_EMPTY_THRESH_ASSERT_VAL = 0; + parameter C_PROG_EMPTY_THRESH_NEGATE_VAL = 0; + parameter C_PROG_EMPTY_TYPE = 0; + parameter C_PROG_FULL_THRESH_ASSERT_VAL = 0; + parameter C_PROG_FULL_THRESH_NEGATE_VAL = 0; + parameter C_PROG_FULL_TYPE = 0; + parameter C_RD_DATA_COUNT_WIDTH = 2; + parameter C_RD_DEPTH = 256; + parameter C_RD_PNTR_WIDTH = 8; + parameter C_UNDERFLOW_LOW = 0; + parameter C_USE_DOUT_RST = 0; + parameter C_USE_EMBEDDED_REG = 0; + parameter C_USE_FWFT_DATA_COUNT = 0; + parameter C_VALID_LOW = 0; + parameter C_WR_ACK_LOW = 0; + parameter C_WR_DATA_COUNT_WIDTH = 2; + parameter C_WR_DEPTH = 256; + parameter C_WR_PNTR_WIDTH = 8; + + /*************************************************************************** + * Declare Input and Output Ports + ***************************************************************************/ + input [C_DIN_WIDTH-1:0] DIN; + input [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH; + input [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_ASSERT; + input [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_NEGATE; + input [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH; + input [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_ASSERT; + input [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_NEGATE; + input RD_CLK; + input RD_EN; + input RST; + input WR_CLK; + input WR_EN; + output ALMOST_EMPTY; + output ALMOST_FULL; + output [C_DOUT_WIDTH-1:0] DOUT; + output EMPTY; + output FULL; + output OVERFLOW; + output PROG_EMPTY; + output PROG_FULL; + output VALID; + output [C_RD_DATA_COUNT_WIDTH-1:0] RD_DATA_COUNT; + output UNDERFLOW; + output WR_ACK; + output [C_WR_DATA_COUNT_WIDTH-1:0] WR_DATA_COUNT; + + /************************************************************************* + * Declare the type for each Input/Output port, and connect each I/O + * to it's associated internal signal in the behavioral model + * + * The values for the outputs are assigned in assign statements immediately + * following wire, parameter, and function declarations in this code. + *************************************************************************/ + //Inputs + wire [C_DIN_WIDTH-1:0] DIN; + wire [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH; + wire [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_ASSERT; + wire [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_NEGATE; + wire [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH; + wire [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_ASSERT; + wire [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_NEGATE; + wire RD_CLK; + wire RD_EN; + wire RST; + wire WR_CLK; + wire WR_EN; + + //Outputs + wire ALMOST_EMPTY; + wire ALMOST_FULL; + wire [C_DOUT_WIDTH-1:0] DOUT; + wire EMPTY; + wire FULL; + wire OVERFLOW; + wire PROG_EMPTY; + wire PROG_FULL; + wire VALID; + wire [C_RD_DATA_COUNT_WIDTH-1:0] RD_DATA_COUNT; + wire UNDERFLOW; + wire WR_ACK; + wire [C_WR_DATA_COUNT_WIDTH-1:0] WR_DATA_COUNT; + + + /*************************************************************************** + * Parameters used as constants + **************************************************************************/ + //When RST is present, set FULL reset value to '1'. + //If core has no RST, make sure FULL powers-on as '0'. + parameter C_DEPTH_RATIO_WR = + (C_WR_DEPTH>C_RD_DEPTH) ? (C_WR_DEPTH/C_RD_DEPTH) : 1; + parameter C_DEPTH_RATIO_RD = + (C_RD_DEPTH>C_WR_DEPTH) ? (C_RD_DEPTH/C_WR_DEPTH) : 1; + parameter C_FIFO_WR_DEPTH = C_WR_DEPTH - 1; + parameter C_FIFO_RD_DEPTH = C_RD_DEPTH - 1; + + + // EXTRA_WORDS = 2 * C_DEPTH_RATIO_WR / C_DEPTH_RATIO_RD + // WR_DEPTH : RD_DEPTH = 1:2 => EXTRA_WORDS = 1 + // WR_DEPTH : RD_DEPTH = 1:4 => EXTRA_WORDS = 1 (rounded to ceiling) + // WR_DEPTH : RD_DEPTH = 2:1 => EXTRA_WORDS = 4 + // WR_DEPTH : RD_DEPTH = 4:1 => EXTRA_WORDS = 8 + parameter EXTRA_WORDS = (C_DEPTH_RATIO_RD > 1)? 1:(2 * C_DEPTH_RATIO_WR); + // extra_words_dc = 2 * C_DEPTH_RATIO_WR / C_DEPTH_RATIO_RD + // C_DEPTH_RATIO_WR | C_DEPTH_RATIO_RD | C_PNTR_WIDTH | EXTRA_WORDS_DC + // -----------------|------------------|-----------------|--------------- + // 1 | 8 | C_RD_PNTR_WIDTH | 0 + // 1 | 4 | C_RD_PNTR_WIDTH | 0 + // 1 | 2 | C_RD_PNTR_WIDTH | 1 + // 1 | 1 | C_WR_PNTR_WIDTH | 2 + // 2 | 1 | C_WR_PNTR_WIDTH | 4 + // 4 | 1 | C_WR_PNTR_WIDTH | 8 + // 8 | 1 | C_WR_PNTR_WIDTH | 16 + parameter EXTRA_WORDS_DC = ( C_DEPTH_RATIO_RD > 2)? + 0:(2 * C_DEPTH_RATIO_WR/C_DEPTH_RATIO_RD); + + + parameter [31:0] reads_per_write = C_DIN_WIDTH/C_DOUT_WIDTH; + + parameter [31:0] log2_reads_per_write = log2_val(reads_per_write); + + parameter [31:0] writes_per_read = C_DOUT_WIDTH/C_DIN_WIDTH; + + parameter [31:0] log2_writes_per_read = log2_val(writes_per_read); + + + + /************************************************************************** + * FIFO Contents Tracking and Data Count Calculations + *************************************************************************/ + + //Memory which will be used to simulate a FIFO + reg [C_DIN_WIDTH-1:0] memory[C_WR_DEPTH-1:0]; + + //The amount of data stored in the FIFO at any time is given + // by num_wr_bits (in the WR_CLK domain) and num_rd_bits (in the RD_CLK + // domain. + //num_wr_bits is calculated by considering the total words in the FIFO, + // and the state of the read pointer (which may not have yet crossed clock + // domains.) + //num_rd_bits is calculated by considering the total words in the FIFO, + // and the state of the write pointer (which may not have yet crossed clock + // domains.) + reg [31:0] num_wr_bits; + reg [31:0] num_rd_bits; + reg [31:0] next_num_wr_bits; + reg [31:0] next_num_rd_bits; + + //The write pointer - tracks write operations + // (Works opposite to core: wr_ptr is a DOWN counter) + reg [31:0] wr_ptr; + + //The read pointer - tracks read operations + // (Works opposite to core: rd_ptr is a DOWN counter) + reg [31:0] rd_ptr; + + //Pointers passed into opposite clock domain + reg [31:0] wr_ptr_rdclk; + reg [31:0] wr_ptr_rdclk_next; + reg [31:0] rd_ptr_wrclk; + reg [31:0] rd_ptr_wrclk_next; + + //Amount of data stored in the FIFO scaled to the narrowest (deepest) port + // (Do not include data in FWFT stages) + //Used to calculate PROG_EMPTY. + wire [31:0] num_read_words_pe = + num_rd_bits/(C_DOUT_WIDTH/C_DEPTH_RATIO_WR); + + //Amount of data stored in the FIFO scaled to the narrowest (deepest) port + // (Do not include data in FWFT stages) + //Used to calculate PROG_FULL. + wire [31:0] num_write_words_pf = + num_wr_bits/(C_DIN_WIDTH/C_DEPTH_RATIO_RD); + + /************************** + * Read Data Count + *************************/ + + /* ORIGINAL CODE - Removed 10/24/07 jeo + //Amount of data stored in the FIFO scaled to read words + // (Do not include data in FWFT stages) + //Not used in the code. + wire [31:0] num_read_words_dc = num_rd_bits/C_DOUT_WIDTH; + + //Amount of data stored in the FIFO scaled to read words + // (Include data in FWFT stages) + //Not used in the code. + wire [31:0] num_read_words_fwft_dc = (num_rd_bits/C_DOUT_WIDTH+2); + + //Not used in the code. + wire [31:0] num_read_words_dc_i = + C_USE_FWFT_DATA_COUNT ? num_read_words_fwft_dc : num_read_words_dc; + + //Not used in the code. + wire [C_RD_DATA_COUNT_WIDTH-1:0] num_read_words_sized = + num_read_words_dc_i[C_RD_PNTR_WIDTH-1 : C_RD_PNTR_WIDTH-C_RD_DATA_COUNT_WIDTH]; + + //Not used in the code. + wire [C_RD_DATA_COUNT_WIDTH-1:0] num_read_words_sized_fwft = + num_read_words_dc_i[C_RD_PNTR_WIDTH : C_RD_PNTR_WIDTH-C_RD_DATA_COUNT_WIDTH+1]; + + //Used to calculate ideal_rd_count (RD_DATA_COUNT) + wire [C_RD_DATA_COUNT_WIDTH-1:0] num_read_words_sized_i = + C_USE_FWFT_DATA_COUNT ? num_read_words_sized_fwft : num_read_words_sized; + */ + + reg [31:0] num_read_words_dc; + reg [C_RD_DATA_COUNT_WIDTH-1:0] num_read_words_sized_i; + + always @(num_rd_bits) begin + if (C_USE_FWFT_DATA_COUNT) begin + + //If using extra logic for FWFT Data Counts, + // then scale FIFO contents to read domain, + // and add two read words for FWFT stages + //This value is only a temporary value and not used in the code. + num_read_words_dc = (num_rd_bits/C_DOUT_WIDTH+2); + + //Trim the read words for use with RD_DATA_COUNT + num_read_words_sized_i = + num_read_words_dc[C_RD_PNTR_WIDTH : C_RD_PNTR_WIDTH-C_RD_DATA_COUNT_WIDTH+1]; + + end else begin + + //If not using extra logic for FWFT Data Counts, + // then scale FIFO contents to read domain. + //This value is only a temporary value and not used in the code. + num_read_words_dc = num_rd_bits/C_DOUT_WIDTH; + + //Trim the read words for use with RD_DATA_COUNT + num_read_words_sized_i = + num_read_words_dc[C_RD_PNTR_WIDTH-1 : C_RD_PNTR_WIDTH-C_RD_DATA_COUNT_WIDTH]; + + end //if (C_USE_FWFT_DATA_COUNT) + end //always + + + + + + + + + /************************** + * Write Data Count + *************************/ + /* ORIGINAL CODE - Removed 10/24/07 jeo + + //Calculate the Data Count value for the number of write words, when not + // using First-Word Fall-Through with extra logic for Data Counts. This + // calculates only the number of words in the internal FIFO. + //The expression (((A-1)/B))+1 divides A/B, but takes the + // ceiling of the result. + //When num_wr_bits==0, set the result manually to prevent division errors. + wire [31:0] num_write_words_dc = + (num_wr_bits==0) ? 0 : ((num_wr_bits-1)/C_DIN_WIDTH) + 1; + + //Calculate the Data Count value for the number of write words, when using + // First-Word Fall-Through with extra logic for Data Counts. This takes into + // consideration the number of words that are expected to be stored in the + // FWFT register stages (it always assumes they are filled). + //The expression (((A-1)/B))+1 divides A/B, but takes the + // ceiling of the result. + //When num_wr_bits==0, set the result manually to prevent division errors. + //EXTRA_WORDS_DC is the number of words added to write_words due to FWFT. + wire [31:0] num_write_words_fwft_dc = + (num_wr_bits==0) ? EXTRA_WORDS_DC : (((num_wr_bits-1)/C_DIN_WIDTH) + 1) + EXTRA_WORDS_DC ; + + wire [31:0] num_write_words_dc_i = + C_USE_FWFT_DATA_COUNT ? num_write_words_fwft_dc : num_write_words_dc; + + + + wire [C_WR_DATA_COUNT_WIDTH-1:0] num_write_words_sized = + num_write_words_dc_i[C_WR_PNTR_WIDTH-1 : C_WR_PNTR_WIDTH-C_WR_DATA_COUNT_WIDTH]; + + wire [C_WR_DATA_COUNT_WIDTH-1:0] num_write_words_sized_fwft = + num_write_words_dc_i[C_WR_PNTR_WIDTH : C_WR_PNTR_WIDTH-C_WR_DATA_COUNT_WIDTH+1]; + + wire [C_WR_DATA_COUNT_WIDTH-1:0] num_write_words_sized_i = C_USE_FWFT_DATA_COUNT? + num_write_words_sized_fwft:num_write_words_sized; + + */ + + reg [31:0] num_write_words_dc; + reg [C_WR_DATA_COUNT_WIDTH-1:0] num_write_words_sized_i; + + always @(num_wr_bits) begin + if (C_USE_FWFT_DATA_COUNT) begin + + //Calculate the Data Count value for the number of write words, + // when using First-Word Fall-Through with extra logic for Data + // Counts. This takes into consideration the number of words that + // are expected to be stored in the FWFT register stages (it always + // assumes they are filled). + //This value is scaled to the Write Domain. + //The expression (((A-1)/B))+1 divides A/B, but takes the + // ceiling of the result. + //When num_wr_bits==0, set the result manually to prevent + // division errors. + //EXTRA_WORDS_DC is the number of words added to write_words + // due to FWFT. + //This value is only a temporary value and not used in the code. + num_write_words_dc = (num_wr_bits==0) ? EXTRA_WORDS_DC : (((num_wr_bits-1)/C_DIN_WIDTH)+1) + EXTRA_WORDS_DC ; + + //Trim the write words for use with WR_DATA_COUNT + num_write_words_sized_i = + num_write_words_dc[C_WR_PNTR_WIDTH : C_WR_PNTR_WIDTH-C_WR_DATA_COUNT_WIDTH+1]; + + end else begin + + //Calculate the Data Count value for the number of write words, when NOT + // using First-Word Fall-Through with extra logic for Data Counts. This + // calculates only the number of words in the internal FIFO. + //The expression (((A-1)/B))+1 divides A/B, but takes the + // ceiling of the result. + //This value is scaled to the Write Domain. + //When num_wr_bits==0, set the result manually to prevent + // division errors. + //This value is only a temporary value and not used in the code. + num_write_words_dc = (num_wr_bits==0) ? 0 : ((num_wr_bits-1)/C_DIN_WIDTH)+1; + + //Trim the read words for use with RD_DATA_COUNT + num_write_words_sized_i = + num_write_words_dc[C_WR_PNTR_WIDTH-1 : C_WR_PNTR_WIDTH-C_WR_DATA_COUNT_WIDTH]; + + end //if (C_USE_FWFT_DATA_COUNT) + end //always + + + + /*************************************************************************** + * Internal registers and wires + **************************************************************************/ + + //Temporary signals used for calculating the model's outputs. These + //are only used in the assign statements immediately following wire, + //parameter, and function declarations. + wire [C_DOUT_WIDTH-1:0] ideal_dout_out; + wire valid_i; + wire valid_out; + wire underflow_i; + + //Ideal FIFO signals. These are the raw output of the behavioral model, + //which behaves like an ideal FIFO. + reg [C_DOUT_WIDTH-1:0] ideal_dout; + reg [C_DOUT_WIDTH-1:0] ideal_dout_d1; + reg ideal_wr_ack; + reg ideal_valid; + reg ideal_overflow; + reg ideal_underflow; + reg ideal_full; + reg ideal_empty; + reg ideal_almost_full; + reg ideal_almost_empty; + reg ideal_prog_full; + reg ideal_prog_empty; + reg [C_WR_DATA_COUNT_WIDTH-1 : 0] ideal_wr_count; + reg [C_RD_DATA_COUNT_WIDTH-1 : 0] ideal_rd_count; + + //Assorted reg values for delayed versions of signals + reg valid_d1; + reg prog_full_d; + reg prog_empty_d; + + //Internal reset signals + reg rd_rst_asreg =0; + reg rd_rst_asreg_d1 =0; + reg rd_rst_asreg_d2 =0; + reg rd_rst_reg =0; + reg rd_rst_d1 =0; + reg wr_rst_asreg =0; + reg wr_rst_asreg_d1 =0; + reg wr_rst_asreg_d2 =0; + reg wr_rst_reg =0; + reg wr_rst_d1 =0; + + wire rd_rst_comb; + wire rd_rst_i; + wire wr_rst_comb; + wire wr_rst_i; + + + //user specified value for reseting the size of the fifo + reg [C_DOUT_WIDTH-1:0] dout_reset_val; + + //temporary registers for WR_RESPONSE_LATENCY feature + + integer tmp_wr_listsize; + integer tmp_rd_listsize; + + //Signal for registered version of prog full and empty + + //Threshold values for Programmable Flags + integer prog_empty_actual_thresh_assert; + integer prog_empty_actual_thresh_negate; + integer prog_full_actual_thresh_assert; + integer prog_full_actual_thresh_negate; + + + /**************************************************************************** + * Function Declarations + ***************************************************************************/ + + /************************************************************************** + * write_fifo + * This task writes a word to the FIFO memory and updates the + * write pointer. + * FIFO size is relative to write domain. + ***************************************************************************/ + task write_fifo; + begin + memory[wr_ptr] <= DIN; + // (Works opposite to core: wr_ptr is a DOWN counter) + if (wr_ptr == 0) begin + wr_ptr <= C_WR_DEPTH - 1; + end else begin + wr_ptr <= wr_ptr - 1; + end + end + endtask // write_fifo + + /************************************************************************** + * read_fifo + * This task reads a word from the FIFO memory and updates the read + * pointer. It's output is the ideal_dout bus. + * FIFO size is relative to write domain. + ***************************************************************************/ + task read_fifo; + integer i; + reg [C_DOUT_WIDTH-1:0] tmp_dout; + reg [C_DIN_WIDTH-1:0] memory_read; + reg [31:0] tmp_rd_ptr; + reg [31:0] rd_ptr_high; + reg [31:0] rd_ptr_low; + begin + // output is wider than input + if (reads_per_write == 0) begin + tmp_dout = 0; + tmp_rd_ptr = (rd_ptr << log2_writes_per_read)+(writes_per_read-1); + for (i = writes_per_read - 1; i >= 0; i = i - 1) begin + tmp_dout = tmp_dout << C_DIN_WIDTH; + tmp_dout = tmp_dout | memory[tmp_rd_ptr]; + + // (Works opposite to core: rd_ptr is a DOWN counter) + if (tmp_rd_ptr == 0) begin + tmp_rd_ptr = C_WR_DEPTH - 1; + end else begin + tmp_rd_ptr = tmp_rd_ptr - 1; + end + end + + // output is symmetric + end else if (reads_per_write == 1) begin + tmp_dout = memory[rd_ptr]; + + // input is wider than output + end else begin + rd_ptr_high = rd_ptr >> log2_reads_per_write; + rd_ptr_low = rd_ptr & (reads_per_write - 1); + memory_read = memory[rd_ptr_high]; + tmp_dout = memory_read >> (rd_ptr_low*C_DOUT_WIDTH); + end + ideal_dout <= tmp_dout; + + // (Works opposite to core: rd_ptr is a DOWN counter) + if (rd_ptr == 0) begin + rd_ptr <= C_RD_DEPTH - 1; + end else begin + rd_ptr <= rd_ptr - 1; + end + end + endtask + + /************************************************************************** + * log2_val + * Returns the 'log2' value for the input value for the supported ratios + ***************************************************************************/ + function [31:0] log2_val; + input [31:0] binary_val; + + begin + if (binary_val == 8) begin + log2_val = 3; + end else if (binary_val == 4) begin + log2_val = 2; + end else begin + log2_val = 1; + end + end + endfunction + + /*********************************************************************** + * hexstr_conv + * Converts a string of type hex to a binary value (for C_DOUT_RST_VAL) + ***********************************************************************/ + function [C_DOUT_WIDTH-1:0] hexstr_conv; + input [(C_DOUT_WIDTH*8)-1:0] def_data; + + integer index,i,j; + reg [3:0] bin; + + begin + index = 0; + hexstr_conv = 'b0; + for( i=C_DOUT_WIDTH-1; i>=0; i=i-1 ) + begin + case (def_data[7:0]) + 8'b00000000 : + begin + bin = 4'b0000; + i = -1; + end + 8'b00110000 : bin = 4'b0000; + 8'b00110001 : bin = 4'b0001; + 8'b00110010 : bin = 4'b0010; + 8'b00110011 : bin = 4'b0011; + 8'b00110100 : bin = 4'b0100; + 8'b00110101 : bin = 4'b0101; + 8'b00110110 : bin = 4'b0110; + 8'b00110111 : bin = 4'b0111; + 8'b00111000 : bin = 4'b1000; + 8'b00111001 : bin = 4'b1001; + 8'b01000001 : bin = 4'b1010; + 8'b01000010 : bin = 4'b1011; + 8'b01000011 : bin = 4'b1100; + 8'b01000100 : bin = 4'b1101; + 8'b01000101 : bin = 4'b1110; + 8'b01000110 : bin = 4'b1111; + 8'b01100001 : bin = 4'b1010; + 8'b01100010 : bin = 4'b1011; + 8'b01100011 : bin = 4'b1100; + 8'b01100100 : bin = 4'b1101; + 8'b01100101 : bin = 4'b1110; + 8'b01100110 : bin = 4'b1111; + default : + begin + bin = 4'bx; + end + endcase + for( j=0; j<4; j=j+1) + begin + if ((index*4)+j < C_DOUT_WIDTH) + begin + hexstr_conv[(index*4)+j] = bin[j]; + end + end + index = index + 1; + def_data = def_data >> 8; + end + end + endfunction + + /************************************************************************* + * Initialize Signals for clean power-on simulation + *************************************************************************/ + initial begin + num_wr_bits = 0; + num_rd_bits = 0; + next_num_wr_bits = 0; + next_num_rd_bits = 0; + rd_ptr = C_RD_DEPTH - 1; + wr_ptr = C_WR_DEPTH - 1; + rd_ptr_wrclk = rd_ptr; + wr_ptr_rdclk = wr_ptr; + dout_reset_val = hexstr_conv(C_DOUT_RST_VAL); + ideal_dout = dout_reset_val; + ideal_dout_d1 = 0 ; + ideal_wr_ack = 1'b0; + ideal_valid = 1'b0; + valid_d1 = 1'b0; + ideal_overflow = 1'b0; + ideal_underflow = 1'b0; + ideal_full = 1'b0; + ideal_empty = 1'b1; + ideal_almost_full = 1'b0; + ideal_almost_empty = 1'b1; + ideal_wr_count = 0; + ideal_rd_count = 0; + ideal_prog_full = 1'b0; + ideal_prog_empty = 1'b1; + prog_full_d = 1'b0; + prog_empty_d = 1'b1; + end + + + /************************************************************************* + * Connect the module inputs and outputs to the internal signals of the + * behavioral model. + *************************************************************************/ + //Inputs + /* + wire [C_DIN_WIDTH-1:0] DIN; + wire [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH; + wire [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_ASSERT; + wire [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_NEGATE; + wire [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH; + wire [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_ASSERT; + wire [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_NEGATE; + wire RD_CLK; + wire RD_EN; + wire RST; + wire WR_CLK; + wire WR_EN; + */ + + //Outputs + generate + if (C_HAS_ALMOST_EMPTY==1) begin : blockAE1 + assign ALMOST_EMPTY = ideal_almost_empty; + end + endgenerate + + generate + if (C_HAS_ALMOST_FULL==1) begin : blockAF1 + assign ALMOST_FULL = ideal_almost_full; + end + endgenerate + + //Dout may change behavior based on latency + assign ideal_dout_out[C_DOUT_WIDTH-1:0] = (C_PRELOAD_LATENCY==2 && + (C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1))? + ideal_dout_d1: ideal_dout; + assign DOUT[C_DOUT_WIDTH-1:0] = ideal_dout_out; + + assign EMPTY = ideal_empty; + assign FULL = ideal_full; + + //Overflow may be active-low + generate + if (C_HAS_OVERFLOW==1) begin : blockOF1 + assign OVERFLOW = ideal_overflow ? !C_OVERFLOW_LOW : C_OVERFLOW_LOW; + end + endgenerate + + assign PROG_EMPTY = ideal_prog_empty; + assign PROG_FULL = ideal_prog_full; + + //Valid may change behavior based on latency or active-low + generate + if (C_HAS_VALID==1) begin : blockVL1 + assign valid_i = (C_PRELOAD_LATENCY==0) ? (RD_EN & ~EMPTY) : ideal_valid; + assign valid_out = (C_PRELOAD_LATENCY==2 && + (C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1))? + valid_d1: valid_i; + assign VALID = valid_out ? !C_VALID_LOW : C_VALID_LOW; + end + endgenerate + + generate + if (C_HAS_RD_DATA_COUNT==1) begin : blockRC1 + assign RD_DATA_COUNT[C_RD_DATA_COUNT_WIDTH-1:0] = ideal_rd_count; + end + endgenerate + + //Underflow may change behavior based on latency or active-low + generate + if (C_HAS_UNDERFLOW==1) begin : blockUF1 + assign underflow_i = (C_PRELOAD_LATENCY==0) ? (RD_EN & EMPTY) : ideal_underflow; + assign UNDERFLOW = underflow_i ? !C_UNDERFLOW_LOW : C_UNDERFLOW_LOW; + end + endgenerate + + //Write acknowledge may be active low + generate + if (C_HAS_WR_ACK==1) begin : blockWK1 + assign WR_ACK = ideal_wr_ack ? !C_WR_ACK_LOW : C_WR_ACK_LOW; + end + endgenerate + + generate + if (C_HAS_WR_DATA_COUNT==1) begin : blockWC1 + assign WR_DATA_COUNT[C_WR_DATA_COUNT_WIDTH-1:0] = ideal_wr_count; + end + endgenerate + + /************************************************************************** + * Internal reset logic + **************************************************************************/ + assign wr_rst_i = C_HAS_RST ? wr_rst_reg : 0; + assign rd_rst_i = C_HAS_RST ? rd_rst_reg : 0; + + generate + if (C_HAS_RST==1) begin : blockRST2 + assign wr_rst_comb = !wr_rst_asreg_d2 && wr_rst_asreg; + assign rd_rst_comb = !rd_rst_asreg_d2 && rd_rst_asreg; + + always @(posedge WR_CLK or posedge RST) begin + if (RST == 1'b1) begin + wr_rst_asreg <= 1'b1; + end else begin + if (wr_rst_asreg_d1 == 1'b1) begin + wr_rst_asreg <= 1'b0; + end else begin + wr_rst_asreg <= wr_rst_asreg; + end + end + end + + always @(posedge WR_CLK) begin + wr_rst_asreg_d1 <= wr_rst_asreg; + wr_rst_asreg_d2 <= wr_rst_asreg_d1; + end + + always @(posedge WR_CLK or posedge wr_rst_comb) begin + if (wr_rst_comb == 1'b1) begin + wr_rst_reg <= 1'b1; + end else begin + wr_rst_reg <= 1'b0; + end + end + + always @(posedge WR_CLK or posedge wr_rst_i) begin + if (wr_rst_i == 1'b1) begin + wr_rst_d1 <= 1'b1; + end else begin + wr_rst_d1 <= wr_rst_i; + end + end + + always @(posedge RD_CLK or posedge RST) begin + if (RST == 1'b1) begin + rd_rst_asreg <= 1'b1; + end else begin + if (rd_rst_asreg_d1 == 1'b1) begin + rd_rst_asreg <= 1'b0; + end else begin + rd_rst_asreg <= rd_rst_asreg; + end + end + end + + always @(posedge RD_CLK) begin + rd_rst_asreg_d1 <= rd_rst_asreg; + rd_rst_asreg_d2 <= rd_rst_asreg_d1; + end + + always @(posedge RD_CLK or posedge rd_rst_comb) begin + if (rd_rst_comb == 1'b1) begin + rd_rst_reg <= 1'b1; + end else begin + rd_rst_reg <= 1'b0; + end + end + end + endgenerate + + /************************************************************************** + * Assorted registers for delayed versions of signals + **************************************************************************/ + //Capture delayed version of valid + generate + if (C_HAS_VALID==1) begin : blockVL2 + always @(posedge RD_CLK or posedge rd_rst_i) begin + if (rd_rst_i == 1'b1) begin + valid_d1 <= 1'b0; + end else begin + valid_d1 <= valid_i; + end + end + end + endgenerate + + //Capture delayed version of dout + always @(posedge RD_CLK or posedge rd_rst_i) begin + if (rd_rst_i == 1'b1 && C_USE_DOUT_RST == 1) begin + ideal_dout_d1 <= dout_reset_val; + end else begin + ideal_dout_d1 <= ideal_dout; + end + end + + /************************************************************************** + * Overflow and Underflow Flag calculation + * (handled separately because they don't support rst) + **************************************************************************/ + generate + if (C_HAS_OVERFLOW==1) begin : blockOF2 + always @(posedge WR_CLK) begin + ideal_overflow <= WR_EN & ideal_full; + end + end + endgenerate + + generate + if (C_HAS_UNDERFLOW==1) begin : blockUF2 + always @(posedge RD_CLK) begin + ideal_underflow <= ideal_empty & RD_EN; + end + end + endgenerate + + /************************************************************************** + * Write Domain Logic + **************************************************************************/ + always @(posedge WR_CLK or posedge wr_rst_i) begin : gen_fifo_w + + /****** Reset fifo (case 1)***************************************/ + if (wr_rst_i == 1'b1) begin + num_wr_bits <= 0; + next_num_wr_bits <= 0; + wr_ptr <= C_WR_DEPTH - 1; + rd_ptr_wrclk <= C_RD_DEPTH - 1; + ideal_wr_ack <= 0; + ideal_full <= C_FULL_FLAGS_RST_VAL; + ideal_almost_full <= C_FULL_FLAGS_RST_VAL; + ideal_wr_count <= 0; + + ideal_prog_full <= C_FULL_FLAGS_RST_VAL; + prog_full_d <= C_FULL_FLAGS_RST_VAL; + + end else begin //wr_rst_i==0 + + //Determine the current number of words in the FIFO + tmp_wr_listsize = (C_DEPTH_RATIO_RD > 1) ? num_wr_bits/C_DOUT_WIDTH : + num_wr_bits/C_DIN_WIDTH; + rd_ptr_wrclk_next = rd_ptr; + if (rd_ptr_wrclk < rd_ptr_wrclk_next) begin + next_num_wr_bits = num_wr_bits - + C_DOUT_WIDTH*(rd_ptr_wrclk + C_RD_DEPTH + - rd_ptr_wrclk_next); + end else begin + next_num_wr_bits = num_wr_bits - + C_DOUT_WIDTH*(rd_ptr_wrclk - rd_ptr_wrclk_next); + end + + //If this is a write, handle the write by adding the value + // to the linked list, and updating all outputs appropriately + if (WR_EN == 1'b1) begin + if (ideal_full == 1'b1) begin + + //If the FIFO is full, do NOT perform the write, + // update flags accordingly + if ((tmp_wr_listsize + C_DEPTH_RATIO_RD - 1)/C_DEPTH_RATIO_RD + >= C_FIFO_WR_DEPTH) begin + //write unsuccessful - do not change contents + + //Do not acknowledge the write + ideal_wr_ack <= 0; + //Reminder that FIFO is still full + ideal_full <= 1'b1; + ideal_almost_full <= 1'b1; + + ideal_wr_count <= num_write_words_sized_i; + + //If the FIFO is one from full, but reporting full + end else + if ((tmp_wr_listsize + C_DEPTH_RATIO_RD - 1)/C_DEPTH_RATIO_RD == + C_FIFO_WR_DEPTH-1) begin + //No change to FIFO + + //Write not successful + ideal_wr_ack <= 0; + //With DEPTH-1 words in the FIFO, it is almost_full + ideal_full <= 1'b0; + ideal_almost_full <= 1'b1; + + ideal_wr_count <= num_write_words_sized_i; + + + //If the FIFO is completely empty, but it is + // reporting FULL for some reason (like reset) + end else + if ((tmp_wr_listsize + C_DEPTH_RATIO_RD - 1)/C_DEPTH_RATIO_RD <= + C_FIFO_WR_DEPTH-2) begin + //No change to FIFO + + //Write not successful + ideal_wr_ack <= 0; + //FIFO is really not close to full, so change flag status. + ideal_full <= 1'b0; + ideal_almost_full <= 1'b0; + + ideal_wr_count <= num_write_words_sized_i; + end //(tmp_wr_listsize == 0) + + end else begin + + //If the FIFO is full, do NOT perform the write, + // update flags accordingly + if ((tmp_wr_listsize + C_DEPTH_RATIO_RD - 1)/C_DEPTH_RATIO_RD >= + C_FIFO_WR_DEPTH) begin + //write unsuccessful - do not change contents + + //Do not acknowledge the write + ideal_wr_ack <= 0; + //Reminder that FIFO is still full + ideal_full <= 1'b1; + ideal_almost_full <= 1'b1; + + ideal_wr_count <= num_write_words_sized_i; + + //If the FIFO is one from full + end else + if ((tmp_wr_listsize + C_DEPTH_RATIO_RD - 1)/C_DEPTH_RATIO_RD == + C_FIFO_WR_DEPTH-1) begin + //Add value on DIN port to FIFO + write_fifo; + next_num_wr_bits = next_num_wr_bits + C_DIN_WIDTH; + + //Write successful, so issue acknowledge + // and no error + ideal_wr_ack <= 1; + //This write is CAUSING the FIFO to go full + ideal_full <= 1'b1; + ideal_almost_full <= 1'b1; + + ideal_wr_count <= num_write_words_sized_i; + + //If the FIFO is 2 from full + end else + if ((tmp_wr_listsize + C_DEPTH_RATIO_RD - 1)/C_DEPTH_RATIO_RD == + C_FIFO_WR_DEPTH-2) begin + //Add value on DIN port to FIFO + write_fifo; + next_num_wr_bits = next_num_wr_bits + C_DIN_WIDTH; + //Write successful, so issue acknowledge + // and no error + ideal_wr_ack <= 1; + //Still 2 from full + ideal_full <= 1'b0; + //2 from full, and writing, so set almost_full + ideal_almost_full <= 1'b1; + + ideal_wr_count <= num_write_words_sized_i; + + //If the FIFO is not close to being full + end else + if ((tmp_wr_listsize + C_DEPTH_RATIO_RD - 1)/C_DEPTH_RATIO_RD < + C_FIFO_WR_DEPTH-2) begin + //Add value on DIN port to FIFO + write_fifo; + next_num_wr_bits = next_num_wr_bits + C_DIN_WIDTH; + //Write successful, so issue acknowledge + // and no error + ideal_wr_ack <= 1; + //Not even close to full. + ideal_full <= 1'b0; + ideal_almost_full <= 1'b0; + + ideal_wr_count <= num_write_words_sized_i; + + end + + end + + end else begin //(WR_EN == 1'b1) + + //If user did not attempt a write, then do not + // give ack or err + ideal_wr_ack <= 0; + + //Implied statements: + //ideal_empty <= ideal_empty; + //ideal_almost_empty <= ideal_almost_empty; + + //Check for full + if ((tmp_wr_listsize + C_DEPTH_RATIO_RD - 1)/C_DEPTH_RATIO_RD >= C_FIFO_WR_DEPTH) + ideal_full <= 1'b1; + else + ideal_full <= 1'b0; + + //Check for almost_full + if ((tmp_wr_listsize + C_DEPTH_RATIO_RD - 1)/C_DEPTH_RATIO_RD >= C_FIFO_WR_DEPTH-1) + ideal_almost_full <= 1'b1; + else + ideal_almost_full <= 1'b0; + + ideal_wr_count <= num_write_words_sized_i; + end + + /********************************************************* + * Programmable FULL flags + *********************************************************/ + //Single Programmable Full Constant Threshold + if (C_PROG_FULL_TYPE==1) begin + if (C_PRELOAD_REGS==1 && C_PRELOAD_LATENCY==0) begin + prog_full_actual_thresh_assert = C_PROG_FULL_THRESH_ASSERT_VAL-EXTRA_WORDS; + prog_full_actual_thresh_negate = C_PROG_FULL_THRESH_ASSERT_VAL-EXTRA_WORDS; + end else begin + prog_full_actual_thresh_assert = C_PROG_FULL_THRESH_ASSERT_VAL; + prog_full_actual_thresh_negate = C_PROG_FULL_THRESH_ASSERT_VAL; + end + + //Two Programmable Full Constant Thresholds + end else if (C_PROG_FULL_TYPE==2) begin + if (C_PRELOAD_REGS==1 && C_PRELOAD_LATENCY==0) begin + prog_full_actual_thresh_assert = C_PROG_FULL_THRESH_ASSERT_VAL-EXTRA_WORDS; + prog_full_actual_thresh_negate = C_PROG_FULL_THRESH_NEGATE_VAL-EXTRA_WORDS; + end else begin + prog_full_actual_thresh_assert = C_PROG_FULL_THRESH_ASSERT_VAL; + prog_full_actual_thresh_negate = C_PROG_FULL_THRESH_NEGATE_VAL; + end + + //Single Programmable Full Threshold Input + end else if (C_PROG_FULL_TYPE==3) begin + if (C_PRELOAD_REGS==1 && C_PRELOAD_LATENCY==0) begin + prog_full_actual_thresh_assert = PROG_FULL_THRESH-EXTRA_WORDS; + prog_full_actual_thresh_negate = PROG_FULL_THRESH-EXTRA_WORDS; + end else begin + prog_full_actual_thresh_assert = PROG_FULL_THRESH; + prog_full_actual_thresh_negate = PROG_FULL_THRESH; + end + + //Two Programmable Full Threshold Inputs + end else if (C_PROG_FULL_TYPE==4) begin + if (C_PRELOAD_REGS==1 && C_PRELOAD_LATENCY==0) begin + prog_full_actual_thresh_assert = PROG_FULL_THRESH_ASSERT-EXTRA_WORDS; + prog_full_actual_thresh_negate = PROG_FULL_THRESH_NEGATE-EXTRA_WORDS; + end else begin + prog_full_actual_thresh_assert = PROG_FULL_THRESH_ASSERT; + prog_full_actual_thresh_negate = PROG_FULL_THRESH_NEGATE; + end + end //C_PROG_FULL_TYPE + + if (num_write_words_pf==0) begin + prog_full_d <= 1'b0; + end else begin + if (((1+(num_write_words_pf-1)/C_DEPTH_RATIO_RD) + == prog_full_actual_thresh_assert-1) && WR_EN) begin + prog_full_d <= 1'b1; + end else if ((1+(num_write_words_pf-1)/C_DEPTH_RATIO_RD) + >= prog_full_actual_thresh_assert) begin + prog_full_d <= 1'b1; + end else if ((1+(num_write_words_pf-1)/C_DEPTH_RATIO_RD) + < prog_full_actual_thresh_negate) begin + prog_full_d <= 1'b0; + end + end + + if (wr_rst_d1==1 && wr_rst_i==0) begin + ideal_prog_full <= 0; + end else begin + ideal_prog_full <= prog_full_d; + end + num_wr_bits <= next_num_wr_bits; + rd_ptr_wrclk <= rd_ptr; + + end //wr_rst_i==0 + end // write always + + + /************************************************************************** + * Read Domain Logic + **************************************************************************/ + always @(posedge RD_CLK or posedge rd_rst_i) begin : gen_fifo_r + + /****** Reset fifo (case 1)***************************************/ + if (rd_rst_i) begin + num_rd_bits <= 0; + next_num_rd_bits <= 0; + rd_ptr <= C_RD_DEPTH -1; + wr_ptr_rdclk <= C_WR_DEPTH -1; + if (C_USE_DOUT_RST == 1) begin + ideal_dout <= dout_reset_val; + end else begin + ideal_dout <= ideal_dout; + end + ideal_valid <= 1'b0; + ideal_empty <= 1'b1; + ideal_almost_empty <= 1'b1; + ideal_rd_count <= 0; + + ideal_prog_empty <= 1'b1; + prog_empty_d <= 1; + + + end else begin //rd_rst_i==0 + + //Determine the current number of words in the FIFO + tmp_rd_listsize = (C_DEPTH_RATIO_WR > 1) ? num_rd_bits/C_DIN_WIDTH : + num_rd_bits/C_DOUT_WIDTH; + wr_ptr_rdclk_next = wr_ptr; + + if (wr_ptr_rdclk < wr_ptr_rdclk_next) begin + next_num_rd_bits = num_rd_bits + + C_DIN_WIDTH*(wr_ptr_rdclk +C_WR_DEPTH + - wr_ptr_rdclk_next); + end else begin + next_num_rd_bits = num_rd_bits + + C_DIN_WIDTH*(wr_ptr_rdclk - wr_ptr_rdclk_next); + end + + /*****************************************************************/ + // Read Operation - Read Latency 1 + /*****************************************************************/ + if (C_PRELOAD_LATENCY==1 || C_PRELOAD_LATENCY==2) begin + + if (RD_EN == 1'b1) begin + + if (ideal_empty == 1'b1) begin + + //If the FIFO is completely empty, and is reporting empty + if (tmp_rd_listsize/C_DEPTH_RATIO_WR <= 0) + begin + //Do not change the contents of the FIFO + + //Do not acknowledge the read from empty FIFO + ideal_valid <= 1'b0; + //Reminder that FIFO is still empty + ideal_empty <= 1'b1; + ideal_almost_empty <= 1'b1; + + ideal_rd_count <= num_read_words_sized_i; + end // if (tmp_rd_listsize <= 0) + + //If the FIFO is one from empty, but it is reporting empty + else if (tmp_rd_listsize/C_DEPTH_RATIO_WR == 1) + begin + //Do not change the contents of the FIFO + + //Do not acknowledge the read from empty FIFO + ideal_valid <= 1'b0; + //Note that FIFO is no longer empty, but is almost empty (has one word left) + ideal_empty <= 1'b0; + ideal_almost_empty <= 1'b1; + + ideal_rd_count <= num_read_words_sized_i; + + end // if (tmp_rd_listsize == 1) + + //If the FIFO is two from empty, and is reporting empty + else if (tmp_rd_listsize/C_DEPTH_RATIO_WR == 2) + begin + //Do not change the contents of the FIFO + + //Do not acknowledge the read from empty FIFO + ideal_valid <= 1'b0; + //Fifo has two words, so is neither empty or almost empty + ideal_empty <= 1'b0; + ideal_almost_empty <= 1'b0; + + ideal_rd_count <= num_read_words_sized_i; + + end // if (tmp_rd_listsize == 2) + + //If the FIFO is not close to empty, but is reporting that it is + // Treat the FIFO as empty this time, but unset EMPTY flags. + if ((tmp_rd_listsize/C_DEPTH_RATIO_WR > 2) && (tmp_rd_listsize/C_DEPTH_RATIO_WR 2) && (tmp_rd_listsize<=C_FIFO_RD_DEPTH-1)) + end // else: if(ideal_empty == 1'b1) + + else //if (ideal_empty == 1'b0) + begin + + //If the FIFO is completely full, and we are successfully reading from it + if (tmp_rd_listsize/C_DEPTH_RATIO_WR >= C_FIFO_RD_DEPTH) + begin + //Read the value from the FIFO + read_fifo; + next_num_rd_bits = next_num_rd_bits - C_DOUT_WIDTH; + + //Acknowledge the read from the FIFO, no error + ideal_valid <= 1'b1; + //Not close to empty + ideal_empty <= 1'b0; + ideal_almost_empty <= 1'b0; + + ideal_rd_count <= num_read_words_sized_i; + + end // if (tmp_rd_listsize == C_FIFO_RD_DEPTH) + + //If the FIFO is not close to being empty + else if ((tmp_rd_listsize/C_DEPTH_RATIO_WR > 2) && (tmp_rd_listsize/C_DEPTH_RATIO_WR<=C_FIFO_RD_DEPTH)) + begin + //Read the value from the FIFO + read_fifo; + next_num_rd_bits = next_num_rd_bits - C_DOUT_WIDTH; + + //Acknowledge the read from the FIFO, no error + ideal_valid <= 1'b1; + //Not close to empty + ideal_empty <= 1'b0; + ideal_almost_empty <= 1'b0; + + ideal_rd_count <= num_read_words_sized_i; + + end // if ((tmp_rd_listsize > 2) && (tmp_rd_listsize<=C_FIFO_RD_DEPTH-1)) + + //If the FIFO is two from empty + else if (tmp_rd_listsize/C_DEPTH_RATIO_WR == 2) + begin + //Read the value from the FIFO + read_fifo; + next_num_rd_bits = next_num_rd_bits - C_DOUT_WIDTH; + + //Acknowledge the read from the FIFO, no error + ideal_valid <= 1'b1; + //Fifo is not yet empty. It is going almost_empty + ideal_empty <= 1'b0; + ideal_almost_empty <= 1'b1; + + ideal_rd_count <= num_read_words_sized_i; + + end // if (tmp_rd_listsize == 2) + + //If the FIFO is one from empty + else if ((tmp_rd_listsize/C_DEPTH_RATIO_WR == 1)) + begin + //Read the value from the FIFO + read_fifo; + next_num_rd_bits = next_num_rd_bits - C_DOUT_WIDTH; + + //Acknowledge the read from the FIFO, no error + ideal_valid <= 1'b1; + //Note that FIFO is GOING empty + ideal_empty <= 1'b1; + ideal_almost_empty <= 1'b1; + + ideal_rd_count <= num_read_words_sized_i; + + end // if (tmp_rd_listsize == 1) + + + //If the FIFO is completely empty + else if (tmp_rd_listsize/C_DEPTH_RATIO_WR <= 0) + begin + //Do not change the contents of the FIFO + + //Do not acknowledge the read from empty FIFO + ideal_valid <= 1'b0; + //Reminder that FIFO is still empty + ideal_empty <= 1'b1; + ideal_almost_empty <= 1'b1; + + ideal_rd_count <= num_read_words_sized_i; + + end // if (tmp_rd_listsize <= 0) + + end // if (ideal_empty == 1'b0) + + end //(RD_EN == 1'b1) + + else //if (RD_EN == 1'b0) + begin + //If user did not attempt a read, do not give an ack or err + ideal_valid <= 1'b0; + + //Check for empty + if (tmp_rd_listsize/C_DEPTH_RATIO_WR <= 0) + ideal_empty <= 1'b1; + else + ideal_empty <= 1'b0; + + //Check for almost_empty + if (tmp_rd_listsize/C_DEPTH_RATIO_WR <= 1) + ideal_almost_empty <= 1'b1; + else + ideal_almost_empty <= 1'b0; + + ideal_rd_count <= num_read_words_sized_i; + + end // else: !if(RD_EN == 1'b1) + + /*****************************************************************/ + // Read Operation - Read Latency 0 + /*****************************************************************/ + end else if (C_PRELOAD_REGS==1 && C_PRELOAD_LATENCY==0) begin + if (RD_EN == 1'b1) begin + + if (ideal_empty == 1'b1) begin + + //If the FIFO is completely empty, and is reporting empty + if (tmp_rd_listsize/C_DEPTH_RATIO_WR <= 0) begin + //Do not change the contents of the FIFO + + //Do not acknowledge the read from empty FIFO + ideal_valid <= 1'b0; + //Reminder that FIFO is still empty + ideal_empty <= 1'b1; + ideal_almost_empty <= 1'b1; + + ideal_rd_count <= num_read_words_sized_i; + + //If the FIFO is one from empty, but it is reporting empty + end else if (tmp_rd_listsize/C_DEPTH_RATIO_WR == 1) begin + //Do not change the contents of the FIFO + + //Do not acknowledge the read from empty FIFO + ideal_valid <= 1'b0; + //Note that FIFO is no longer empty, but is almost empty (has one word left) + ideal_empty <= 1'b0; + ideal_almost_empty <= 1'b1; + + ideal_rd_count <= num_read_words_sized_i; + + //If the FIFO is two from empty, and is reporting empty + end else if (tmp_rd_listsize/C_DEPTH_RATIO_WR == 2) begin + //Do not change the contents of the FIFO + + //Do not acknowledge the read from empty FIFO + ideal_valid <= 1'b0; + //Fifo has two words, so is neither empty or almost empty + ideal_empty <= 1'b0; + ideal_almost_empty <= 1'b0; + + ideal_rd_count <= num_read_words_sized_i; + + //If the FIFO is not close to empty, but is reporting that it is + // Treat the FIFO as empty this time, but unset EMPTY flags. + end else if ((tmp_rd_listsize/C_DEPTH_RATIO_WR > 2) && + (tmp_rd_listsize/C_DEPTH_RATIO_WR 2) && (tmp_rd_listsize<=C_FIFO_RD_DEPTH-1)) + + end else begin + + //If the FIFO is completely full, and we are successfully reading from it + if (tmp_rd_listsize/C_DEPTH_RATIO_WR >= C_FIFO_RD_DEPTH) begin + //Read the value from the FIFO + read_fifo; + next_num_rd_bits = next_num_rd_bits - C_DOUT_WIDTH; + + //Acknowledge the read from the FIFO, no error + ideal_valid <= 1'b1; + //Not close to empty + ideal_empty <= 1'b0; + ideal_almost_empty <= 1'b0; + + ideal_rd_count <= num_read_words_sized_i; + + //If the FIFO is not close to being empty + end else if ((tmp_rd_listsize/C_DEPTH_RATIO_WR > 2) && + (tmp_rd_listsize/C_DEPTH_RATIO_WR<=C_FIFO_RD_DEPTH)) begin + //Read the value from the FIFO + read_fifo; + next_num_rd_bits = next_num_rd_bits - C_DOUT_WIDTH; + + //Acknowledge the read from the FIFO, no error + ideal_valid <= 1'b1; + //Not close to empty + ideal_empty <= 1'b0; + ideal_almost_empty <= 1'b0; + + ideal_rd_count <= num_read_words_sized_i; + + //If the FIFO is two from empty + end else if (tmp_rd_listsize/C_DEPTH_RATIO_WR == 2) begin + //Read the value from the FIFO + read_fifo; + next_num_rd_bits = next_num_rd_bits - C_DOUT_WIDTH; + + //Acknowledge the read from the FIFO, no error + ideal_valid <= 1'b1; + //Fifo is not yet empty. It is going almost_empty + ideal_empty <= 1'b0; + ideal_almost_empty <= 1'b1; + + ideal_rd_count <= num_read_words_sized_i; + + //If the FIFO is one from empty + end else if (tmp_rd_listsize/C_DEPTH_RATIO_WR == 1) begin + //Read the value from the FIFO + read_fifo; + next_num_rd_bits = next_num_rd_bits - C_DOUT_WIDTH; + + //Acknowledge the read from the FIFO, no error + ideal_valid <= 1'b1; + //Note that FIFO is GOING empty + ideal_empty <= 1'b1; + ideal_almost_empty <= 1'b1; + + ideal_rd_count <= num_read_words_sized_i; + + //If the FIFO is completely empty + end else if (tmp_rd_listsize/C_DEPTH_RATIO_WR <= 0) begin + //Do not change the contents of the FIFO + + //Do not acknowledge the read from empty FIFO + ideal_valid <= 1'b0; + //Reminder that FIFO is still empty + ideal_empty <= 1'b1; + ideal_almost_empty <= 1'b1; + + ideal_rd_count <= num_read_words_sized_i; + + end // if (tmp_rd_listsize <= 0) + + end // if (ideal_empty == 1'b0) + + end else begin//(RD_EN == 1'b0) + + + //If user did not attempt a read, do not give an ack or err + ideal_valid <= 1'b0; + + //Check for empty + if (tmp_rd_listsize/C_DEPTH_RATIO_WR <= 0) + ideal_empty <= 1'b1; + else + ideal_empty <= 1'b0; + + //Check for almost_empty + if (tmp_rd_listsize/C_DEPTH_RATIO_WR <= 1) + ideal_almost_empty <= 1'b1; + else + ideal_almost_empty <= 1'b0; + + ideal_rd_count <= num_read_words_sized_i; + + end // else: !if(RD_EN == 1'b1) + end //if (C_PRELOAD_REGS==1 && C_PRELOAD_LATENCY==0) + + + /********************************************************* + * Programmable EMPTY flags + *********************************************************/ + //Determine the Assert and Negate thresholds for Programmable Empty + // (Subtract 2 read-sized words when using Preload 0) + + //Single Programmable Empty Constant Threshold + if (C_PROG_EMPTY_TYPE==1) begin + if (C_PRELOAD_REGS==1 && C_PRELOAD_LATENCY==0) begin + prog_empty_actual_thresh_assert = C_PROG_EMPTY_THRESH_ASSERT_VAL-2; + prog_empty_actual_thresh_negate = C_PROG_EMPTY_THRESH_ASSERT_VAL-2; + end + else begin + prog_empty_actual_thresh_assert = C_PROG_EMPTY_THRESH_ASSERT_VAL; + prog_empty_actual_thresh_negate = C_PROG_EMPTY_THRESH_ASSERT_VAL; + end + + //Two Programmable Empty Constant Thresholds + end else if (C_PROG_EMPTY_TYPE==2) begin + if (C_PRELOAD_REGS==1 && C_PRELOAD_LATENCY==0) begin + prog_empty_actual_thresh_assert = C_PROG_EMPTY_THRESH_ASSERT_VAL-2; + prog_empty_actual_thresh_negate = C_PROG_EMPTY_THRESH_NEGATE_VAL-2; + end + else begin + prog_empty_actual_thresh_assert = C_PROG_EMPTY_THRESH_ASSERT_VAL; + prog_empty_actual_thresh_negate = C_PROG_EMPTY_THRESH_NEGATE_VAL; + end + + //Single Programmable Empty Constant Threshold + end else if (C_PROG_EMPTY_TYPE==3) begin + if (C_PRELOAD_REGS==1 && C_PRELOAD_LATENCY==0) begin + prog_empty_actual_thresh_assert = PROG_EMPTY_THRESH-2; + prog_empty_actual_thresh_negate = PROG_EMPTY_THRESH-2; + end + else begin + prog_empty_actual_thresh_assert = PROG_EMPTY_THRESH; + prog_empty_actual_thresh_negate = PROG_EMPTY_THRESH; + + end + //Two Programmable Empty Constant Thresholds + end else if (C_PROG_EMPTY_TYPE==4) begin + if (C_PRELOAD_REGS==1 && C_PRELOAD_LATENCY==0) begin + prog_empty_actual_thresh_assert = PROG_EMPTY_THRESH_ASSERT-2; + prog_empty_actual_thresh_negate = PROG_EMPTY_THRESH_NEGATE-2; + end + else begin + prog_empty_actual_thresh_assert = PROG_EMPTY_THRESH_ASSERT; + prog_empty_actual_thresh_negate = PROG_EMPTY_THRESH_NEGATE; + end + end + + if ((num_read_words_pe/C_DEPTH_RATIO_WR == prog_empty_actual_thresh_assert+1) + && RD_EN) begin + prog_empty_d <= 1'b1; + end else if (num_read_words_pe/C_DEPTH_RATIO_WR + <= prog_empty_actual_thresh_assert) begin + prog_empty_d <= 1'b1; + end else if (num_read_words_pe/C_DEPTH_RATIO_WR + > prog_empty_actual_thresh_negate) begin + prog_empty_d <= 1'b0; + end + + + ideal_prog_empty <= prog_empty_d; + num_rd_bits <= next_num_rd_bits; + wr_ptr_rdclk <= wr_ptr; + end //rd_rst_i==0 + end //always + +endmodule // fifo_generator_v4_4_bhv_ver_as + + +/******************************************************************************* + * Declaration of top-level module + ******************************************************************************/ +module fifo_generator_v4_4_bhv_ver_ss + ( + CLK, RST, SRST, DIN, WR_EN, RD_EN, + PROG_FULL_THRESH, PROG_FULL_THRESH_ASSERT, PROG_FULL_THRESH_NEGATE, + PROG_EMPTY_THRESH, PROG_EMPTY_THRESH_ASSERT, PROG_EMPTY_THRESH_NEGATE, + DOUT, FULL, ALMOST_FULL, WR_ACK, OVERFLOW, EMPTY, + ALMOST_EMPTY, VALID, UNDERFLOW, DATA_COUNT, + PROG_FULL, PROG_EMPTY + ); + + /************************************************************************** + * Declare user parameters and their defaults + *************************************************************************/ + parameter C_DATA_COUNT_WIDTH = 2; + parameter C_DIN_WIDTH = 8; + parameter C_DOUT_RST_VAL = ""; + parameter C_DOUT_WIDTH = 8; + parameter C_FULL_FLAGS_RST_VAL = 1; + parameter C_HAS_ALMOST_EMPTY = 0; + parameter C_HAS_ALMOST_FULL = 0; + parameter C_HAS_DATA_COUNT = 0; + parameter C_HAS_OVERFLOW = 0; + parameter C_HAS_RD_DATA_COUNT = 0; + parameter C_HAS_RST = 0; + parameter C_HAS_SRST = 0; + parameter C_HAS_UNDERFLOW = 0; + parameter C_HAS_VALID = 0; + parameter C_HAS_WR_ACK = 0; + parameter C_HAS_WR_DATA_COUNT = 0; + parameter C_IMPLEMENTATION_TYPE = 0; + parameter C_MEMORY_TYPE = 1; + parameter C_OVERFLOW_LOW = 0; + parameter C_PRELOAD_LATENCY = 1; + parameter C_PRELOAD_REGS = 0; + parameter C_PROG_EMPTY_THRESH_ASSERT_VAL = 0; + parameter C_PROG_EMPTY_THRESH_NEGATE_VAL = 0; + parameter C_PROG_EMPTY_TYPE = 0; + parameter C_PROG_FULL_THRESH_ASSERT_VAL = 0; + parameter C_PROG_FULL_THRESH_NEGATE_VAL = 0; + parameter C_PROG_FULL_TYPE = 0; + parameter C_RD_DATA_COUNT_WIDTH = 2; + parameter C_RD_DEPTH = 256; + parameter C_RD_PNTR_WIDTH = 8; + parameter C_UNDERFLOW_LOW = 0; + parameter C_USE_DOUT_RST = 0; + parameter C_USE_EMBEDDED_REG = 0; + parameter C_USE_FWFT_DATA_COUNT = 0; + parameter C_VALID_LOW = 0; + parameter C_WR_ACK_LOW = 0; + parameter C_WR_DATA_COUNT_WIDTH = 2; + parameter C_WR_DEPTH = 256; + parameter C_WR_PNTR_WIDTH = 8; + + + /************************************************************************** + * Declare Input and Output Ports + *************************************************************************/ + //Inputs + input CLK; + input [C_DIN_WIDTH-1:0] DIN; + input [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH; + input [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_ASSERT; + input [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_NEGATE; + input [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH; + input [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_ASSERT; + input [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_NEGATE; + input RD_EN; + input RST; + input SRST; + input WR_EN; + + //Outputs + output ALMOST_EMPTY; + output ALMOST_FULL; + output [C_DATA_COUNT_WIDTH-1:0] DATA_COUNT; + output [C_DOUT_WIDTH-1:0] DOUT; + output EMPTY; + output FULL; + output OVERFLOW; + output PROG_EMPTY; + output PROG_FULL; + output VALID; + output UNDERFLOW; + output WR_ACK; + + /************************************************************************* + * Declare the type for each Input/Output port, and connect each I/O + * to it's associated internal signal in the behavioral model + * + * The values for the outputs are assigned in assign statements immediately + * following wire, parameter, and function declarations in this code. + *************************************************************************/ + //Inputs + wire CLK; + wire [C_DIN_WIDTH-1:0] DIN; + wire [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH; + wire [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_ASSERT; + wire [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_NEGATE; + wire [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH; + wire [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_ASSERT; + wire [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_NEGATE; + wire RD_EN; + wire RST; + wire SRST; + wire WR_EN; + + //Outputs + wire ALMOST_EMPTY; + wire ALMOST_FULL; + reg [C_DATA_COUNT_WIDTH-1:0] DATA_COUNT; + wire [C_DOUT_WIDTH-1:0] DOUT; + wire EMPTY; + wire FULL; + wire OVERFLOW; + wire PROG_EMPTY; + wire PROG_FULL; + wire VALID; + wire UNDERFLOW; + wire WR_ACK; + + + /*************************************************************************** + * Parameters used as constants + **************************************************************************/ + //When RST is present, set FULL reset value to '1'. + //If core has no RST, make sure FULL powers-on as '0'. + //The reset value assignments for FULL, ALMOST_FULL, and PROG_FULL are not + //changed for v3.2(IP2_Im). When the core has Sync Reset, C_HAS_SRST=1 and C_HAS_RST=0. + // Therefore, during SRST, all the FULL flags reset to 0. + parameter C_HAS_FAST_FIFO = 0; + parameter C_FIFO_WR_DEPTH = C_WR_DEPTH; + parameter C_FIFO_RD_DEPTH = C_RD_DEPTH; + + /************************************************************************** + * FIFO Contents Tracking and Data Count Calculations + *************************************************************************/ + //Memory which will be used to simulate a FIFO + reg [C_DIN_WIDTH-1:0] memory[C_WR_DEPTH-1:0]; + + //The amount of data stored in the FIFO at any time is given + // by num_bits. + //num_bits is calculated by from the total words in the FIFO. + reg [31:0] num_bits; + + //The write pointer - tracks write operations + // (Works opposite to core: wr_ptr is a DOWN counter) + reg [31:0] wr_ptr; + + //The write pointer - tracks read operations + // (Works opposite to core: rd_ptr is a DOWN counter) + reg [31:0] rd_ptr; + + /************************** + * Data Count + *************************/ + //Amount of data stored in the FIFO scaled to read words + wire [31:0] num_read_words = num_bits/C_DOUT_WIDTH; + //num_read_words delayed 1 clock cycle + reg [31:0] num_read_words_q; + + //Amount of data stored in the FIFO scaled to write words + wire [31:0] num_write_words = num_bits/C_DIN_WIDTH; + //num_write_words delayed 1 clock cycle + reg [31:0] num_write_words_q; + + + /************************************************************************** + * Internal Registers and wires + *************************************************************************/ + + //Temporary signals used for calculating the model's outputs. These + //are only used in the assign statements immediately following wire, + //parameter, and function declarations. + wire underflow_i; + wire valid_i; + wire valid_out; + + //Ideal FIFO signals. These are the raw output of the behavioral model, + //which behaves like an ideal FIFO. + reg [C_DOUT_WIDTH-1:0] ideal_dout; + reg [C_DOUT_WIDTH-1:0] ideal_dout_d1; + wire [C_DOUT_WIDTH-1:0] ideal_dout_out; + wire fwft_enabled; + reg ideal_wr_ack; + reg ideal_valid; + reg ideal_overflow; + reg ideal_underflow; + reg ideal_full; + reg ideal_empty; + reg ideal_almost_full; + reg ideal_almost_empty; + reg ideal_prog_full; + reg ideal_prog_empty; + + //Assorted reg values for delayed versions of signals + reg valid_d1; + reg prog_full_d; + reg prog_empty_d; + + + //Internal reset signals + reg rst_asreg =0; + reg rst_asreg_d1 =0; + reg rst_asreg_d2 =0; + reg rst_reg =0; + reg rst_d1 =0; + wire rst_comb; + wire rst_i; + wire srst_i; + + //Delayed version of RST + reg rst_q; + reg rst_qq; + + //user specified value for reseting the size of the fifo + reg [C_DOUT_WIDTH-1:0] dout_reset_val; + + + /**************************************************************************** + * Function Declarations + ***************************************************************************/ + + /************************************************************************** + * write_fifo + * This task writes a word to the FIFO memory and updates the + * write pointer. + * FIFO size is relative to write domain. + ***************************************************************************/ + task write_fifo; + begin + memory[wr_ptr] <= DIN; + if (wr_ptr == 0) begin + wr_ptr <= C_WR_DEPTH - 1; + end else begin + wr_ptr <= wr_ptr - 1; + end + end + endtask // write_fifo + + /************************************************************************** + * read_fifo + * This task reads a word from the FIFO memory and updates the read + * pointer. It's output is the ideal_dout bus. + * FIFO size is relative to write domain. + ***************************************************************************/ + task read_fifo; + begin + ideal_dout <= memory[rd_ptr]; + if (rd_ptr == 0) begin + rd_ptr <= C_RD_DEPTH - 1; + end else begin + rd_ptr <= rd_ptr - 1; + end + end + endtask + + /**************************************************************************** + * log2_val + * Returns the 'log2' value for the input value for the supported ratios + ***************************************************************************/ + function [31:0] log2_val; + input [31:0] binary_val; + + begin + if (binary_val == 8) begin + log2_val = 3; + end else if (binary_val == 4) begin + log2_val = 2; + end else begin + log2_val = 1; + end + end + endfunction + + /**************************************************************************** + * hexstr_conv + * Converts a string of type hex to a binary value (for C_DOUT_RST_VAL) + ***************************************************************************/ + function [C_DOUT_WIDTH-1:0] hexstr_conv; + input [(C_DOUT_WIDTH*8)-1:0] def_data; + + integer index,i,j; + reg [3:0] bin; + + begin + index = 0; + hexstr_conv = 'b0; + for( i=C_DOUT_WIDTH-1; i>=0; i=i-1 ) + begin + case (def_data[7:0]) + 8'b00000000 : + begin + bin = 4'b0000; + i = -1; + end + 8'b00110000 : bin = 4'b0000; + 8'b00110001 : bin = 4'b0001; + 8'b00110010 : bin = 4'b0010; + 8'b00110011 : bin = 4'b0011; + 8'b00110100 : bin = 4'b0100; + 8'b00110101 : bin = 4'b0101; + 8'b00110110 : bin = 4'b0110; + 8'b00110111 : bin = 4'b0111; + 8'b00111000 : bin = 4'b1000; + 8'b00111001 : bin = 4'b1001; + 8'b01000001 : bin = 4'b1010; + 8'b01000010 : bin = 4'b1011; + 8'b01000011 : bin = 4'b1100; + 8'b01000100 : bin = 4'b1101; + 8'b01000101 : bin = 4'b1110; + 8'b01000110 : bin = 4'b1111; + 8'b01100001 : bin = 4'b1010; + 8'b01100010 : bin = 4'b1011; + 8'b01100011 : bin = 4'b1100; + 8'b01100100 : bin = 4'b1101; + 8'b01100101 : bin = 4'b1110; + 8'b01100110 : bin = 4'b1111; + default : + begin + bin = 4'bx; + end + endcase + for( j=0; j<4; j=j+1) + begin + if ((index*4)+j < C_DOUT_WIDTH) + begin + hexstr_conv[(index*4)+j] = bin[j]; + end + end + index = index + 1; + def_data = def_data >> 8; + end + end + endfunction + + + /************************************************************************* + * Initialize Signals for clean power-on simulation + *************************************************************************/ + initial begin + num_bits = 0; + num_read_words_q = 0; + num_write_words_q = 0; + rd_ptr = C_RD_DEPTH -1; + wr_ptr = C_WR_DEPTH -1; + dout_reset_val = hexstr_conv(C_DOUT_RST_VAL); + ideal_dout = dout_reset_val; + ideal_wr_ack = 1'b0; + ideal_valid = 1'b0; + valid_d1 = 1'b0; + ideal_overflow = 1'b0; + ideal_underflow = 1'b0; + ideal_full = 1'b0; + ideal_empty = 1'b1; + ideal_almost_full = 1'b0; + ideal_almost_empty = 1'b1; + ideal_prog_full = 1'b0; + ideal_prog_empty = 1'b1; + prog_full_d = 1'b0; + prog_empty_d = 1'b1; + rst_q = 1'b0; + rst_qq = 1'b0; + end + + + /************************************************************************* + * Connect the module inputs and outputs to the internal signals of the + * behavioral model. + *************************************************************************/ + //Inputs + /* + wire CLK; + wire [C_DIN_WIDTH-1:0] DIN; + wire [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH; + wire [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_ASSERT; + wire [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_NEGATE; + wire [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH; + wire [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_ASSERT; + wire [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_NEGATE; + wire RD_EN; + wire RST; + wire WR_EN; + */ + + //Outputs + generate + if (C_HAS_ALMOST_EMPTY==1) begin : blockAE10 + assign ALMOST_EMPTY = ideal_almost_empty; + end + endgenerate + + generate + if (C_HAS_ALMOST_FULL==1) begin : blockAF10 + assign ALMOST_FULL = ideal_almost_full; + end + endgenerate + + //Dout may change behavior based on latency + assign fwft_enabled = (C_PRELOAD_LATENCY == 0 && C_PRELOAD_REGS == 1)? + 1: 0; + assign ideal_dout_out= ((C_USE_EMBEDDED_REG==1 && (fwft_enabled == 0)) && + (C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1))? + ideal_dout_d1: ideal_dout; + assign DOUT = ideal_dout_out; + + assign EMPTY = ideal_empty; + assign FULL = ideal_full; + + //Overflow may be active-low + generate + if (C_HAS_OVERFLOW==1) begin : blockOF10 + assign OVERFLOW = ideal_overflow ? !C_OVERFLOW_LOW : C_OVERFLOW_LOW; + end + endgenerate + + assign PROG_EMPTY = ideal_prog_empty; + assign PROG_FULL = ideal_prog_full; + + //Valid may change behavior based on latency or active-low + generate + if (C_HAS_VALID==1) begin : blockVL10 + assign valid_i = (C_PRELOAD_LATENCY==0) ? (RD_EN & ~EMPTY) : ideal_valid; + assign valid_out = (C_PRELOAD_LATENCY==2 && + (C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1))? + valid_d1: valid_i; + assign VALID = valid_out ? !C_VALID_LOW : C_VALID_LOW; + end + endgenerate + + //Trim data count differently depending on set widths + generate + if (C_HAS_DATA_COUNT==1) begin : blockDC1 + always @(num_read_words) begin + if (C_DATA_COUNT_WIDTH>C_RD_PNTR_WIDTH) begin + DATA_COUNT = num_read_words[C_RD_PNTR_WIDTH:0]; + end else begin + DATA_COUNT = + num_read_words[C_RD_PNTR_WIDTH-1:C_RD_PNTR_WIDTH-C_DATA_COUNT_WIDTH]; + end //if + end //always + end + endgenerate + + //Underflow may change behavior based on latency or active-low + generate + if (C_HAS_UNDERFLOW==1) begin : blockUF10 + assign underflow_i = (C_PRELOAD_LATENCY==0) ? (RD_EN & EMPTY) : ideal_underflow; + assign UNDERFLOW = underflow_i ? !C_UNDERFLOW_LOW : C_UNDERFLOW_LOW; + end + endgenerate + + + //Write acknowledge may be active low + generate + if (C_HAS_WR_ACK==1) begin : blockWK10 + assign WR_ACK = ideal_wr_ack ? !C_WR_ACK_LOW : C_WR_ACK_LOW; + end + endgenerate + + + /***************************************************************************** + * Internal reset logic + ****************************************************************************/ + assign srst_i = C_HAS_SRST ? SRST : 0; + assign rst_i = C_HAS_RST ? rst_reg : 0; + + generate + if (C_HAS_RST==1) begin : blockRST3 + assign rst_comb = !rst_asreg_d2 && rst_asreg; + + always @(posedge CLK or posedge RST) begin + if (RST == 1'b1) begin + rst_asreg <= 1'b1; + end else begin + if (rst_asreg_d1 == 1'b1) begin + rst_asreg <= 1'b0; + end else begin + rst_asreg <= rst_asreg; + end + end + end + + always @(posedge CLK) begin + rst_asreg_d1 <= rst_asreg; + rst_asreg_d2 <= rst_asreg_d1; + end + + always @(posedge CLK or posedge rst_comb) begin + if (rst_comb == 1'b1) begin + rst_reg <= 1'b1; + end else begin + rst_reg <= 1'b0; + end + end + end + endgenerate + + /************************************************************************** + * Assorted registers for delayed versions of signals + **************************************************************************/ + //Capture delayed version of valid + generate + if (C_HAS_VALID==1) begin : blockVL20 + always @(posedge CLK or posedge rst_i) begin + if (rst_i == 1'b1) begin + valid_d1 <= 1'b0; + end else begin + if (srst_i) begin + valid_d1 <= 1'b0; + end else begin + valid_d1 <= valid_i; + end + end + end // always @ (posedge CLK or posedge rst_i) + end + endgenerate + + //Capture delayed version of dout + always @(posedge CLK or posedge rst_i) begin + if (rst_i == 1'b1 && C_USE_DOUT_RST == 1) begin + ideal_dout_d1 <= dout_reset_val; + end else begin + if (srst_i && C_USE_DOUT_RST == 1) begin + ideal_dout_d1 <= dout_reset_val; + end else begin + ideal_dout_d1 <= ideal_dout; + end + end + end + + /************************************************************************** + * Overflow and Underflow Flag calculation + * (handled separately because they don't support rst) + **************************************************************************/ + generate + if (C_HAS_OVERFLOW==1) begin : blockOF20 + always @(posedge CLK) begin + ideal_overflow <= WR_EN & ideal_full; + end + end + endgenerate + + generate + if (C_HAS_UNDERFLOW==1) begin : blockUF20 + always @(posedge CLK) begin + ideal_underflow <= ideal_empty & RD_EN; + end + end + endgenerate + + /************************************************************************* + * Write and Read Logic + ************************************************************************/ + always @(posedge CLK or posedge rst_i) + begin : gen_wr_ack_resp + + //Register reset + rst_q <= rst_i; + rst_qq <= rst_q; + + end // block: gen_wr_ack_resp + + // block memory has a synchronous reset + always @(posedge CLK) begin : gen_fifo_blkmemdout + //Changed the latency of during async reset to '1' instead of '2' to + // make it consistent with the core. + if (rst_i || rst_q || srst_i) begin + /******Initialize Read Domain Signals*********************************/ + if (C_MEMORY_TYPE == 1 && C_USE_DOUT_RST == 1) begin + ideal_dout <= dout_reset_val; + end + end + end //always + + always @(posedge CLK or posedge rst_i) begin : gen_fifo + + /****** Reset fifo - Asynchronous Reset**********************************/ + //Changed the latency of during async reset to '1' instead of '2' to + // make it consistent with the core. + if (rst_i) begin //v3.2 + /******Initialize Generic FIFO constructs*****************************/ + num_bits <= 0; + wr_ptr <= C_WR_DEPTH - 1; + rd_ptr <= C_RD_DEPTH - 1; + num_read_words_q <= 0; + num_write_words_q <= 0; + + + /******Initialize Write Domain Signals********************************/ + ideal_wr_ack <= 0; + ideal_full <= C_FULL_FLAGS_RST_VAL; + ideal_almost_full <= C_FULL_FLAGS_RST_VAL; + + /******Initialize Read Domain Signals*********************************/ + if (C_MEMORY_TYPE != 1 && C_USE_DOUT_RST == 1) begin + ideal_dout <= dout_reset_val; + end + ideal_valid <= 1'b0; + ideal_empty <= 1'b1; + ideal_almost_empty <= 1'b1; + + end else begin + if (srst_i) begin + // SRST is available only for Sync BRAM and Sync DRAM. + // Not for SSHFT. + if (C_MEMORY_TYPE == 1 || C_MEMORY_TYPE == 2) begin + /******Initialize Generic FIFO constructs***********************/ + num_bits <= 0; + wr_ptr <= C_WR_DEPTH - 1; + rd_ptr <= C_RD_DEPTH - 1; + num_read_words_q <= 0; + num_write_words_q <= 0; + + /******Initialize Write Domain Signals**************************/ + ideal_wr_ack <= 0; + ideal_full <= 0; //'0' + ideal_almost_full <= 0; //'0' + + /******Initialize Read Domain Signals***************************/ + //Reset DOUT of Sync DRAM. Sync BRAM DOUT was reset in the + // above always block. + if (C_MEMORY_TYPE == 2 && C_USE_DOUT_RST == 1 ) begin + ideal_dout <= dout_reset_val; + end + ideal_valid <= 1'b0; + ideal_empty <= 1'b1; + ideal_almost_empty <= 1'b1; + end + + end else begin //normal operating conditions + /********************************************************************/ + // Synchronous FIFO Condition #1 : Writing and not reading + /********************************************************************/ + if (WR_EN & ~RD_EN) begin + + /*********************************/ + //If the FIFO is full, do NOT perform the write, + // update flags accordingly + /*********************************/ + if (num_write_words >= C_FIFO_WR_DEPTH) begin + ideal_wr_ack <= 0; + + //still full + ideal_full <= 1'b1; + ideal_almost_full <= 1'b1; + + //write unsuccessful - do not change contents + + // no read attempted + ideal_valid <= 1'b0; + + //Not near empty + ideal_empty <= 1'b0; + ideal_almost_empty <= 1'b0; + + + /*********************************/ + //If the FIFO is reporting FULL + // (Startup condition) + /*********************************/ + end else if ((num_write_words < C_FIFO_WR_DEPTH) && (ideal_full == 1'b1)) begin + ideal_wr_ack <= 0; + + //still full + ideal_full <= 1'b0; + ideal_almost_full <= 1'b0; + + //write unsuccessful - do not change contents + + // no read attempted + ideal_valid <= 1'b0; + + //FIFO EMPTY in this state can not be determined + //ideal_empty <= 1'b0; + //ideal_almost_empty <= 1'b0; + + + /*********************************/ + //If the FIFO is one from full + /*********************************/ + end else if (num_write_words == C_FIFO_WR_DEPTH-1) begin + //good write + ideal_wr_ack <= 1; + + //FIFO is one from FULL and going FULL + ideal_full <= 1'b1; + ideal_almost_full <= 1'b1; + + //Add input data + write_fifo; + + // no read attempted + ideal_valid <= 1'b0; + + //Not near empty + ideal_empty <= 1'b0; + ideal_almost_empty <= 1'b0; + + num_bits <= num_bits + C_DIN_WIDTH; + + /*********************************/ + //If the FIFO is 2 from full + /*********************************/ + end else if (num_write_words == C_FIFO_WR_DEPTH-2) begin + //good write + ideal_wr_ack <= 1; + + //2 from full, and writing, so set almost_full + ideal_full <= 1'b0; + ideal_almost_full <= 1'b1; + + //Add input data + write_fifo; + + //no read attempted + ideal_valid <= 1'b0; + + //Not near empty + ideal_empty <= 1'b0; + ideal_almost_empty <= 1'b0; + + num_bits <= num_bits + C_DIN_WIDTH; + + /*********************************/ + //If the FIFO is ALMOST EMPTY + /*********************************/ + end else if (num_read_words == 1) begin + //good write + ideal_wr_ack <= 1; + + //Not near FULL + ideal_full <= 1'b0; + ideal_almost_full <= 1'b0; + + //Add input data + write_fifo; + + // no read attempted + ideal_valid <= 1'b0; + + //Leaving ALMOST_EMPTY + ideal_empty <= 1'b0; + ideal_almost_empty <= 1'b0; + + num_bits <= num_bits + C_DIN_WIDTH; + + /*********************************/ + //If the FIFO is EMPTY + /*********************************/ + end else if (num_read_words == 0) begin + // good write + ideal_wr_ack <= 1; + + //Not near FULL + ideal_full <= 1'b0; + ideal_almost_full <= 1'b0; + + //Add input data + write_fifo; + + // no read attempted + ideal_valid <= 1'b0; + + //Leaving EMPTY (still ALMOST_EMPTY) + ideal_empty <= 1'b0; + ideal_almost_empty <= 1'b1; + + num_bits <= num_bits + C_DIN_WIDTH; + + /*********************************/ + //If the FIFO is not near EMPTY or FULL + /*********************************/ + end else begin + // good write + ideal_wr_ack <= 1; + + //Not near FULL + ideal_full <= 1'b0; + ideal_almost_full <= 1'b0; + + //Add input data + write_fifo; + + // no read attempted + ideal_valid <= 1'b0; + + //Not near EMPTY + ideal_empty <= 1'b0; + ideal_almost_empty <= 1'b0; + + num_bits <= num_bits + C_DIN_WIDTH; + + end // average case + + + /******************************************************************/ + // Synchronous FIFO Condition #2 : Reading and not writing + /******************************************************************/ + end else if (~WR_EN & RD_EN) begin + + /*********************************/ + //If the FIFO is EMPTY + /*********************************/ + if ((num_read_words == 0) || (ideal_empty == 1'b1)) begin + //no write attemped + ideal_wr_ack <= 0; + + //FIFO is not near FULL + ideal_full <= 1'b0; + ideal_almost_full <= 1'b0; + + //Read will fail + ideal_valid <= 1'b0; + + //FIFO is still empty + ideal_empty <= 1'b1; + ideal_almost_empty <= 1'b1; + + //No read + + /*********************************/ + //If the FIFO is ALMOST EMPTY + /*********************************/ + end else if (num_read_words == 1) begin + //no write attempted + ideal_wr_ack <= 0; + + //FIFO is not near FULL + ideal_full <= 1'b0; + ideal_almost_full <= 1'b0; + + //Read successful + ideal_valid <= 1'b1; + + //This read will make FIFO go empty + ideal_empty <= 1'b1; + ideal_almost_empty <= 1'b1; + + //Get the data from the FIFO + read_fifo; + num_bits <= num_bits - C_DIN_WIDTH; + + + /*********************************/ + //If the FIFO is 2 from EMPTY + /*********************************/ + end else if (num_read_words == 2) begin + + //no write attempted + ideal_wr_ack <= 0; + + //FIFO is not near FULL + ideal_full <= 1'b0; + ideal_almost_full <= 1'b0; + + //Read successful + ideal_valid <= 1'b1; + + //FIFO is going ALMOST_EMPTY + ideal_empty <= 1'b0; + ideal_almost_empty <= 1'b1; + + //Get the data from the FIFO + read_fifo; + num_bits <= num_bits - C_DOUT_WIDTH; + + + + /*********************************/ + //If the FIFO is one from full + /*********************************/ + end else if (num_write_words == C_FIFO_WR_DEPTH-1) begin + + //no write attempted + ideal_wr_ack <= 0; + + //FIFO is leaving ALMOST FULL + ideal_full <= 1'b0; + ideal_almost_full <= 1'b0; + + //Read successful + ideal_valid <= 1'b1; + + //Not near empty + ideal_empty <= 1'b0; + ideal_almost_empty <= 1'b0; + + //Read from the FIFO + read_fifo; + num_bits <= num_bits - C_DOUT_WIDTH; + + + /*********************************/ + // FIFO is FULL + /*********************************/ + end else if (num_write_words >= C_FIFO_WR_DEPTH) + begin + //no write attempted + ideal_wr_ack <= 0; + + //FIFO is leaving FULL, but is still ALMOST_FULL + ideal_full <= 1'b0; + ideal_almost_full <= 1'b1; + + //Read successful + ideal_valid <= 1'b1; + + //Not near empty + ideal_empty <= 1'b0; + ideal_almost_empty <= 1'b0; + + //Read from the FIFO + read_fifo; + num_bits <= num_bits - C_DOUT_WIDTH; + + /*********************************/ + //If the FIFO is not near EMPTY or FULL + /*********************************/ + end else begin + //no write attemped + ideal_wr_ack <= 0; + + //Not near empty + ideal_full <= 1'b0; + ideal_almost_full <= 1'b0; + + //Read successful + ideal_valid <= 1'b1; + + //Not near empty + ideal_empty <= 1'b0; + ideal_almost_empty <= 1'b0; + + //Read from the FIFO + read_fifo; + num_bits <= num_bits - C_DOUT_WIDTH; + + + end // average read + + + /******************************************************************/ + // Synchronous FIFO Condition #3 : Reading and writing + /******************************************************************/ + end else if (WR_EN & RD_EN) begin + + /*********************************/ + // FIFO is FULL + /*********************************/ + if (num_write_words >= C_FIFO_WR_DEPTH) begin + + ideal_wr_ack <= 0; + + //Read will be successful, so FIFO will leave FULL + ideal_full <= 1'b0; + ideal_almost_full <= 1'b1; + + //Read successful + ideal_valid <= 1'b1; + + //Not near empty + ideal_empty <= 1'b0; + ideal_almost_empty <= 1'b0; + + //Read from the FIFO + read_fifo; + num_bits <= num_bits - C_DOUT_WIDTH; + + + /*********************************/ + // FIFO is reporting FULL, but it is empty + // (This is a special case, when coming out of RST + /*********************************/ + end else if ((num_write_words == 0) && (ideal_full == 1'b1)) begin + + ideal_wr_ack <= 0; + + //Read will be successful, so FIFO will leave FULL + ideal_full <= 1'b0; + ideal_almost_full <= 1'b0; + + //Read unsuccessful + ideal_valid <= 1'b0; + + //Report empty condition + ideal_empty <= 1'b1; + ideal_almost_empty <= 1'b1; + + //Do not read from empty FIFO + // Read from the FIFO + + + /*********************************/ + //If the FIFO is one from full + /*********************************/ + end else if (num_write_words == C_FIFO_WR_DEPTH-1) begin + + //Write successful + ideal_wr_ack <= 1; + + //FIFO will remain ALMOST_FULL + ideal_full <= 1'b0; + ideal_almost_full <= 1'b1; + + // put the data into the FIFO + write_fifo; + + //Read successful + ideal_valid <= 1'b1; + + //Not near empty + ideal_empty <= 1'b0; + ideal_almost_empty <= 1'b0; + + //Read from the FIFO + read_fifo; + num_bits <= num_bits + C_DIN_WIDTH - C_DOUT_WIDTH; + + /*********************************/ + //If the FIFO is ALMOST EMPTY + /*********************************/ + end else if (num_read_words == 1) begin + + //Write successful + ideal_wr_ack <= 1; + + // Not near FULL + ideal_full <= 1'b0; + ideal_almost_full <= 1'b0; + + // put the data into the FIFO + write_fifo; + + //Read successful + ideal_valid <= 1'b1; + + //FIFO will stay ALMOST_EMPTY + ideal_empty <= 1'b0; + ideal_almost_empty <= 1'b1; + + //Read from the FIFO + read_fifo; + num_bits <= num_bits + C_DIN_WIDTH - C_DOUT_WIDTH; + + + /*********************************/ + //If the FIFO is EMPTY + /*********************************/ + end else if (num_read_words == 0) begin + + //Write successful + ideal_wr_ack <= 1; + + // Not near FULL + ideal_full <= 1'b0; + ideal_almost_full <= 1'b0; + + // put the data into the FIFO + write_fifo; + + //Read will fail + ideal_valid <= 1'b0; + + //FIFO will leave EMPTY + ideal_empty <= 1'b0; + ideal_almost_empty <= 1'b1; + + // No read + num_bits <= num_bits + C_DIN_WIDTH; + + + /*********************************/ + //If the FIFO is not near EMPTY or FULL + /*********************************/ + end else begin + + //Write successful + ideal_wr_ack <= 1; + + // Not near FULL + ideal_full <= 1'b0; + ideal_almost_full <= 1'b0; + + // put the data into the FIFO + write_fifo; + + //Read successful + ideal_valid <= 1'b1; + + // Not near EMPTY + ideal_empty <= 1'b0; + ideal_almost_empty <= 1'b0; + + //Read from the FIFO + read_fifo; + num_bits <= num_bits + C_DIN_WIDTH - C_DOUT_WIDTH; + + end // average case + + /******************************************************************/ + // Synchronous FIFO Condition #4 : Not reading or writing + /******************************************************************/ + end else begin + + /*********************************/ + // FIFO is FULL + /*********************************/ + if (num_write_words >= C_FIFO_WR_DEPTH) begin + + //No write + ideal_wr_ack <= 0; + ideal_full <= 1'b1; + ideal_almost_full <= 1'b1; + + //No read + ideal_valid <= 1'b0; + ideal_empty <= 1'b0; + ideal_almost_empty <= 1'b0; + + //No change to memory + + /*********************************/ + //If the FIFO is one from full + /*********************************/ + end else if (num_write_words == C_FIFO_WR_DEPTH-1) begin + + //No write + ideal_wr_ack <= 0; + ideal_full <= 1'b0; + ideal_almost_full <= 1'b1; + + //No read + ideal_valid <= 1'b0; + ideal_empty <= 1'b0; + ideal_almost_empty <= 1'b0; + + //No change to memory + + /*********************************/ + //If the FIFO is ALMOST EMPTY + /*********************************/ + end else if (num_read_words == 1) begin + //No write + ideal_wr_ack <= 0; + ideal_full <= 1'b0; + ideal_almost_full <= 1'b0; + + //No read + ideal_valid <= 1'b0; + ideal_empty <= 1'b0; + ideal_almost_empty <= 1'b1; + + //No change to memory + + end // almost empty + + + /*********************************/ + //If the FIFO is EMPTY + /*********************************/ + else if (num_read_words == 0) + begin + //No write + ideal_wr_ack <= 0; + ideal_full <= 1'b0; + ideal_almost_full <= 1'b0; + + //No read + ideal_valid <= 1'b0; + ideal_empty <= 1'b1; + ideal_almost_empty <= 1'b1; + + //No change to memory + + /*********************************/ + //If the FIFO is not near EMPTY or FULL + /*********************************/ + end else begin + + //No write + ideal_wr_ack <= 0; + ideal_full <= 1'b0; + ideal_almost_full <= 1'b0; + + //No read + ideal_valid <= 1'b0; + ideal_empty <= 1'b0; + ideal_almost_empty <= 1'b0; + + //No change to memory + + end // average case + + end // neither reading or writing + + num_read_words_q <= num_read_words; + num_write_words_q <= num_write_words; + + end //normal operating conditions + end + + end // block: gen_fifo + + + always @(posedge CLK or posedge rst_i) begin : gen_fifo_p + + /****** Reset fifo - Async Reset****************************************/ + //The latency of de-assertion of the flags is reduced by 1 to be + // consistent with the core. + if (rst_i) begin + ideal_prog_full <= C_FULL_FLAGS_RST_VAL; + ideal_prog_empty <= 1'b1; + prog_full_d <= C_FULL_FLAGS_RST_VAL; + prog_empty_d <= 1'b1; + + end else begin + if (srst_i) begin + //SRST is available only for Sync BRAM and Sync DRAM. Not for SSHFT. + if (C_MEMORY_TYPE == 1 || C_MEMORY_TYPE == 2) begin + ideal_prog_full <= 1'b0; + ideal_prog_empty <= 1'b1; + prog_full_d <= 1'b0; + prog_empty_d <= 1'b1; + end + end else begin + + /*************************************************************** + * Programmable FULL flags + ****************************************************************/ + //calculation for standard fifo and latency =2 + if (! (C_PRELOAD_REGS==1 && C_PRELOAD_LATENCY==0) ) begin + //Single constant threshold + if (C_PROG_FULL_TYPE == 1) begin + if ((num_write_words >= C_PROG_FULL_THRESH_ASSERT_VAL-1) + && WR_EN && !RD_EN) begin + prog_full_d <= 1'b1; + end else if (((num_write_words == C_PROG_FULL_THRESH_ASSERT_VAL) + && RD_EN && !WR_EN) || (rst_q && !rst_i)) begin + prog_full_d <= 1'b0; + end + + //Dual constant thresholds + end else if (C_PROG_FULL_TYPE == 2) begin + if ((num_write_words == C_PROG_FULL_THRESH_ASSERT_VAL-1) + && WR_EN && !RD_EN) begin + prog_full_d <= 1'b1; + end else if ((num_write_words == C_PROG_FULL_THRESH_NEGATE_VAL) + && RD_EN && !WR_EN) begin + prog_full_d <= 1'b0; + end + + //Single input threshold + end else if (C_PROG_FULL_TYPE == 3) begin + if ((num_write_words == PROG_FULL_THRESH-1) + && WR_EN && !RD_EN) begin + prog_full_d <= 1'b1; + end else if ((num_write_words == PROG_FULL_THRESH) + && !WR_EN && RD_EN) begin + prog_full_d <= 1'b0; + end else if (num_write_words >= PROG_FULL_THRESH) begin + prog_full_d <= 1'b1; + end else if (num_write_words < PROG_FULL_THRESH) begin + prog_full_d <= 1'b0; + end + + //Dual input thresholds + end else begin + if ((num_write_words == PROG_FULL_THRESH_ASSERT-1) + && WR_EN && !RD_EN) begin + prog_full_d <= 1'b1; + end else if ((num_write_words == PROG_FULL_THRESH_NEGATE) + && !WR_EN && RD_EN)begin + prog_full_d <= 1'b0; + end else if (num_write_words >= PROG_FULL_THRESH_ASSERT) begin + prog_full_d <= 1'b1; + end else if (num_write_words < PROG_FULL_THRESH_NEGATE) begin + prog_full_d <= 1'b0; + end + end + end // (~ (C_PRELOAD_REGS==1 && C_PRELOAD_LATENCY==0) ) + + + //calculation for FWFT fifo + if (C_PRELOAD_REGS==1 && C_PRELOAD_LATENCY==0) begin + if (C_PROG_FULL_TYPE == 1) begin + if ((num_write_words >= C_PROG_FULL_THRESH_ASSERT_VAL-1 - 2) + && WR_EN && !RD_EN) begin + prog_full_d <= 1'b1; + end else if (((num_write_words == C_PROG_FULL_THRESH_ASSERT_VAL - 2) + && RD_EN && !WR_EN) || (rst_q && !rst_i)) begin + prog_full_d <= 1'b0; + end + + //Dual constant thresholds + end else if (C_PROG_FULL_TYPE == 2) begin + if ((num_write_words == C_PROG_FULL_THRESH_ASSERT_VAL-1 - 2) + && WR_EN && !RD_EN) begin + prog_full_d <= 1'b1; + end else if ((num_write_words == C_PROG_FULL_THRESH_NEGATE_VAL - 2) + && RD_EN && !WR_EN) begin + prog_full_d <= 1'b0; + end + + //Single input threshold + end else if (C_PROG_FULL_TYPE == 3) begin + if ((num_write_words == PROG_FULL_THRESH-1 - 2) + && WR_EN && !RD_EN) begin + prog_full_d <= 1'b1; + end else if ((num_write_words == PROG_FULL_THRESH - 2) + && !WR_EN && RD_EN) begin + prog_full_d <= 1'b0; + end else if (num_write_words >= PROG_FULL_THRESH - 2) begin + prog_full_d <= 1'b1; + end else if (num_write_words < PROG_FULL_THRESH - 2) begin + prog_full_d <= 1'b0; + end + + //Dual input thresholds + end else begin + if ((num_write_words == PROG_FULL_THRESH_ASSERT-1 - 2) + && WR_EN && !RD_EN) begin + prog_full_d <= 1'b1; + end else if ((num_write_words == PROG_FULL_THRESH_NEGATE - 2) + && !WR_EN && RD_EN)begin + prog_full_d <= 1'b0; + end else if (num_write_words >= PROG_FULL_THRESH_ASSERT - 2) begin + prog_full_d <= 1'b1; + end else if (num_write_words < PROG_FULL_THRESH_NEGATE - 2) begin + prog_full_d <= 1'b0; + end + end + end // (C_PRELOAD_REGS==1 && C_PRELOAD_LATENCY==0) + + /***************************************************************** + * Programmable EMPTY flags + ****************************************************************/ + //calculation for standard fifo and latency = 2 + if (! (C_PRELOAD_REGS==1 && C_PRELOAD_LATENCY==0) ) begin + //Single constant threshold + if (C_PROG_EMPTY_TYPE == 1) begin + if ((num_read_words == C_PROG_EMPTY_THRESH_ASSERT_VAL+1) + && RD_EN && !WR_EN) begin + prog_empty_d <= 1'b1; + end else if ((num_read_words == C_PROG_EMPTY_THRESH_ASSERT_VAL) + && WR_EN && !RD_EN) begin + prog_empty_d <= 1'b0; + end + //Dual constant thresholds + end else if (C_PROG_EMPTY_TYPE == 2) begin + if ((num_read_words == C_PROG_EMPTY_THRESH_ASSERT_VAL+1) + && RD_EN && !WR_EN) begin + prog_empty_d <= 1'b1; + end else if ((num_read_words == C_PROG_EMPTY_THRESH_NEGATE_VAL) + && !RD_EN && WR_EN) begin + prog_empty_d <= 1'b0; + end + + //Single input threshold + end else if (C_PROG_EMPTY_TYPE == 3) begin + if ((num_read_words == PROG_EMPTY_THRESH+1) + && RD_EN && !WR_EN) begin + prog_empty_d <= 1'b1; + end else if ((num_read_words == PROG_EMPTY_THRESH) + && !RD_EN && WR_EN) begin + prog_empty_d <= 1'b0; + end else if (num_read_words <= PROG_EMPTY_THRESH) begin + prog_empty_d <= 1'b1; + end else if (num_read_words > PROG_EMPTY_THRESH)begin + prog_empty_d <= 1'b0; + end + + //Dual input thresholds + end else begin + if (num_read_words <= PROG_EMPTY_THRESH_ASSERT) begin + prog_empty_d <= 1'b1; + end else if ((num_read_words == PROG_EMPTY_THRESH_ASSERT+1) + && RD_EN && !WR_EN) begin + prog_empty_d <= 1'b1; + end else if (num_read_words > PROG_EMPTY_THRESH_NEGATE)begin + prog_empty_d <= 1'b0; + end else if ((num_read_words == PROG_EMPTY_THRESH_NEGATE) + && !RD_EN && WR_EN) begin + prog_empty_d <= 1'b0; + end + end + end // (~ (C_PRELOAD_REGS==1 && C_PRELOAD_LATENCY==0) ) + + //calculation for FWFT fifo + if (C_PRELOAD_REGS==1 && C_PRELOAD_LATENCY==0) begin + //Single constant threshold + if (C_PROG_EMPTY_TYPE == 1) begin + if ((num_read_words == C_PROG_EMPTY_THRESH_ASSERT_VAL+1 - 2) + && RD_EN && !WR_EN) begin + prog_empty_d <= 1'b1; + end else if ((num_read_words == C_PROG_EMPTY_THRESH_ASSERT_VAL - 2) + && WR_EN && !RD_EN) begin + prog_empty_d <= 1'b0; + end + //Dual constant thresholds + end else if (C_PROG_EMPTY_TYPE == 2) begin + if ((num_read_words == C_PROG_EMPTY_THRESH_ASSERT_VAL+1 - 2) + && RD_EN && !WR_EN) begin + prog_empty_d <= 1'b1; + end else if ((num_read_words == C_PROG_EMPTY_THRESH_NEGATE_VAL - 2) + && !RD_EN && WR_EN) begin + prog_empty_d <= 1'b0; + end + + //Single input threshold + end else if (C_PROG_EMPTY_TYPE == 3) begin + if ((num_read_words == PROG_EMPTY_THRESH+1 - 2) + && RD_EN && !WR_EN) begin + prog_empty_d <= 1'b1; + end else if ((num_read_words == PROG_EMPTY_THRESH - 2) + && !RD_EN && WR_EN) begin + prog_empty_d <= 1'b0; + end else if (num_read_words <= PROG_EMPTY_THRESH - 2) begin + prog_empty_d <= 1'b1; + end else if (num_read_words > PROG_EMPTY_THRESH - 2)begin + prog_empty_d <= 1'b0; + end + + //Dual input thresholds + end else begin + if (num_read_words <= PROG_EMPTY_THRESH_ASSERT - 2) begin + prog_empty_d <= 1'b1; + end else if ((num_read_words == PROG_EMPTY_THRESH_ASSERT+1 - 2) + && RD_EN && !WR_EN) begin + prog_empty_d <= 1'b1; + end else if (num_read_words > PROG_EMPTY_THRESH_NEGATE - 2)begin + prog_empty_d <= 1'b0; + end else if ((num_read_words == PROG_EMPTY_THRESH_NEGATE - 2) + && !RD_EN && WR_EN) begin + prog_empty_d <= 1'b0; + end + end + end // (~ (C_PRELOAD_REGS==1 && C_PRELOAD_LATENCY==0) ) + + ideal_prog_empty <= prog_empty_d; + if (rst_q && !rst_i) begin + ideal_prog_full <= 1'b0; + prog_full_d <= 1'b0; + end else begin + ideal_prog_full <= prog_full_d; + end + + end //if (srst_i) begin + end //if (rst_i) begin + end //always @(posedge CLK or posedge rst_i) begin : gen_fifo_p +endmodule // fifo_generator_v4_4_bhv_ver_ss + + + +/************************************************************************** + * First-Word Fall-Through module (preload 0) + **************************************************************************/ +module fifo_generator_v4_4_bhv_ver_preload0 + ( + RD_CLK, + RD_RST, + SRST, + RD_EN, + FIFOEMPTY, + FIFODATA, + USERDATA, + USERVALID, + USERUNDERFLOW, + USEREMPTY, + USERALMOSTEMPTY, + RAMVALID, + FIFORDEN + ); + + parameter C_DOUT_RST_VAL = ""; + parameter C_DOUT_WIDTH = 8; + parameter C_HAS_RST = 0; + parameter C_HAS_SRST = 0; + parameter C_USE_DOUT_RST = 0; + parameter C_USERVALID_LOW = 0; + parameter C_USERUNDERFLOW_LOW = 0; + + //Inputs + input RD_CLK; + input RD_RST; + input SRST; + input RD_EN; + input FIFOEMPTY; + input [C_DOUT_WIDTH-1:0] FIFODATA; + + //Outputs + output [C_DOUT_WIDTH-1:0] USERDATA; + output USERVALID; + output USERUNDERFLOW; + output USEREMPTY; + output USERALMOSTEMPTY; + output RAMVALID; + output FIFORDEN; + + //Inputs + wire RD_CLK; + wire RD_RST; + wire RD_EN; + wire FIFOEMPTY; + wire [C_DOUT_WIDTH-1:0] FIFODATA; + + //Outputs + reg [C_DOUT_WIDTH-1:0] USERDATA; + wire USERVALID; + wire USERUNDERFLOW; + wire USEREMPTY; + wire USERALMOSTEMPTY; + wire RAMVALID; + wire FIFORDEN; + + //Internal signals + wire preloadstage1; + wire preloadstage2; + reg ram_valid_i; + reg read_data_valid_i; + wire ram_regout_en; + wire ram_rd_en; + reg empty_i = 1'b1; + reg empty_q = 1'b1; + reg rd_en_q = 1'b0; + reg almost_empty_i = 1'b1; + reg almost_empty_q = 1'b1; + wire rd_rst_i; + wire srst_i; + + +/************************************************************************* +* FUNCTIONS +*************************************************************************/ + + /************************************************************************* + * hexstr_conv + * Converts a string of type hex to a binary value (for C_DOUT_RST_VAL) + ***********************************************************************/ + function [C_DOUT_WIDTH-1:0] hexstr_conv; + input [(C_DOUT_WIDTH*8)-1:0] def_data; + + integer index,i,j; + reg [3:0] bin; + + begin + index = 0; + hexstr_conv = 'b0; + for( i=C_DOUT_WIDTH-1; i>=0; i=i-1 ) + begin + case (def_data[7:0]) + 8'b00000000 : + begin + bin = 4'b0000; + i = -1; + end + 8'b00110000 : bin = 4'b0000; + 8'b00110001 : bin = 4'b0001; + 8'b00110010 : bin = 4'b0010; + 8'b00110011 : bin = 4'b0011; + 8'b00110100 : bin = 4'b0100; + 8'b00110101 : bin = 4'b0101; + 8'b00110110 : bin = 4'b0110; + 8'b00110111 : bin = 4'b0111; + 8'b00111000 : bin = 4'b1000; + 8'b00111001 : bin = 4'b1001; + 8'b01000001 : bin = 4'b1010; + 8'b01000010 : bin = 4'b1011; + 8'b01000011 : bin = 4'b1100; + 8'b01000100 : bin = 4'b1101; + 8'b01000101 : bin = 4'b1110; + 8'b01000110 : bin = 4'b1111; + 8'b01100001 : bin = 4'b1010; + 8'b01100010 : bin = 4'b1011; + 8'b01100011 : bin = 4'b1100; + 8'b01100100 : bin = 4'b1101; + 8'b01100101 : bin = 4'b1110; + 8'b01100110 : bin = 4'b1111; + default : + begin + bin = 4'bx; + end + endcase + for( j=0; j<4; j=j+1) + begin + if ((index*4)+j < C_DOUT_WIDTH) + begin + hexstr_conv[(index*4)+j] = bin[j]; + end + end + index = index + 1; + def_data = def_data >> 8; + end + end + endfunction + + + //************************************************************************* + // Set power-on states for regs + //************************************************************************* + initial begin + ram_valid_i = 1'b0; + read_data_valid_i = 1'b0; + USERDATA = hexstr_conv(C_DOUT_RST_VAL); + end //initial + + //*************************************************************************** + // connect up optional reset + //*************************************************************************** + assign rd_rst_i = C_HAS_RST ? RD_RST : 0; + assign srst_i = C_HAS_SRST ? SRST : 0; + + + //*************************************************************************** + // preloadstage2 indicates that stage2 needs to be updated. This is true + // whenever read_data_valid is false, and RAM_valid is true. + //*************************************************************************** + assign preloadstage2 = ram_valid_i & (~read_data_valid_i | RD_EN); + + //*************************************************************************** + // preloadstage1 indicates that stage1 needs to be updated. This is true + // whenever the RAM has data (RAM_EMPTY is false), and either RAM_Valid is + // false (indicating that Stage1 needs updating), or preloadstage2 is active + // (indicating that Stage2 is going to update, so Stage1, therefore, must + // also be updated to keep it valid. + //*************************************************************************** + assign preloadstage1 = ((~ram_valid_i | preloadstage2) & ~FIFOEMPTY); + + //*************************************************************************** + // Calculate RAM_REGOUT_EN + // The output registers are controlled by the ram_regout_en signal. + // These registers should be updated either when the output in Stage2 is + // invalid (preloadstage2), OR when the user is reading, in which case the + // Stage2 value will go invalid unless it is replenished. + //*************************************************************************** + assign ram_regout_en = preloadstage2; + + //*************************************************************************** + // Calculate RAM_RD_EN + // RAM_RD_EN will be asserted whenever the RAM needs to be read in order to + // update the value in Stage1. + // One case when this happens is when preloadstage1=true, which indicates + // that the data in Stage1 or Stage2 is invalid, and needs to automatically + // be updated. + // The other case is when the user is reading from the FIFO, which + // guarantees that Stage1 or Stage2 will be invalid on the next clock + // cycle, unless it is replinished by data from the memory. So, as long + // as the RAM has data in it, a read of the RAM should occur. + //*************************************************************************** + assign ram_rd_en = (RD_EN & ~FIFOEMPTY) | preloadstage1; + + //*************************************************************************** + // Calculate RAMVALID_P0_OUT + // RAMVALID_P0_OUT indicates that the data in Stage1 is valid. + // + // If the RAM is being read from on this clock cycle (ram_rd_en=1), then + // RAMVALID_P0_OUT is certainly going to be true. + // If the RAM is not being read from, but the output registers are being + // updated to fill Stage2 (ram_regout_en=1), then Stage1 will be emptying, + // therefore causing RAMVALID_P0_OUT to be false. + // Otherwise, RAMVALID_P0_OUT will remain unchanged. + //*************************************************************************** + // PROCESS regout_valid + always @ (posedge RD_CLK or posedge rd_rst_i) begin + if (rd_rst_i) begin + // asynchronous reset (active high) + ram_valid_i <= 1'b0; + end else begin + if (srst_i) begin + // synchronous reset (active high) + ram_valid_i <= 1'b0; + end else begin + if (ram_rd_en == 1'b1) begin + ram_valid_i <= 1'b1; + end else begin + if (ram_regout_en == 1'b1) + ram_valid_i <= 1'b0; + else + ram_valid_i <= ram_valid_i; + end + end //srst_i + end //rd_rst_i + end //always + + //*************************************************************************** + // Calculate READ_DATA_VALID + // READ_DATA_VALID indicates whether the value in Stage2 is valid or not. + // Stage2 has valid data whenever Stage1 had valid data and + // ram_regout_en_i=1, such that the data in Stage1 is propogated + // into Stage2. + //*************************************************************************** + always @ (posedge RD_CLK or posedge rd_rst_i) begin + if (rd_rst_i) + read_data_valid_i <= 1'b0; + else if (srst_i) + read_data_valid_i <= 1'b0; + else + read_data_valid_i <= ram_valid_i | (read_data_valid_i & ~RD_EN); + end //always + + + //************************************************************************** + // Calculate EMPTY + // Defined as the inverse of READ_DATA_VALID + // + // Description: + // + // If read_data_valid_i indicates that the output is not valid, + // and there is no valid data on the output of the ram to preload it + // with, then we will report empty. + // + // If there is no valid data on the output of the ram and we are + // reading, then the FIFO will go empty. + // + //************************************************************************** + always @ (posedge RD_CLK or posedge rd_rst_i) begin + if (rd_rst_i) begin + // asynchronous reset (active high) + empty_i <= 1'b1; + empty_q <= 1'b1; + end else begin + if (srst_i) begin + // synchronous reset (active high) + empty_i <= 1'b1; + empty_q <= 1'b1; + end else begin + // rising clock edge + empty_i <= (~ram_valid_i & ~read_data_valid_i) | (~ram_valid_i & RD_EN); + empty_q <= empty_i; + end + end + end //always + + //Register RD_EN from user to calculate USERUNDERFLOW. + always @ (posedge RD_CLK or posedge rd_rst_i) begin + if (rd_rst_i) begin + // asynchronous reset (active high) + rd_en_q <= 1'b0; + end else begin + if (srst_i) begin + // synchronous reset (active high) + rd_en_q <= 1'b0; + end else begin + // rising clock edge + rd_en_q <= RD_EN; + end + end + end //always + + + //*************************************************************************** + // Calculate user_almost_empty + // user_almost_empty is defined such that, unless more words are written + // to the FIFO, the next read will cause the FIFO to go EMPTY. + // + // In most cases, whenever the output registers are updated (due to a user + // read or a preload condition), then user_almost_empty will update to + // whatever RAM_EMPTY is. + // + // The exception is when the output is valid, the user is not reading, and + // Stage1 is not empty. In this condition, Stage1 will be preloaded from the + // memory, so we need to make sure user_almost_empty deasserts properly under + // this condition. + //*************************************************************************** + always @ (posedge RD_CLK or posedge rd_rst_i) + begin + if (rd_rst_i) begin // asynchronous reset (active high) + almost_empty_i <= 1'b1; + almost_empty_q <= 1'b1; + end else begin // rising clock edge + if (srst_i) begin // synchronous reset (active high) + almost_empty_i <= 1'b1; + almost_empty_q <= 1'b1; + end else begin + if ((ram_regout_en) | (~FIFOEMPTY & read_data_valid_i & ~RD_EN)) begin + almost_empty_i <= FIFOEMPTY; + end + almost_empty_q <= empty_i; + end + end + end //always + + + assign USEREMPTY = empty_i; + assign USERALMOSTEMPTY = almost_empty_i; + assign FIFORDEN = ram_rd_en; + assign RAMVALID = ram_valid_i; + assign USERVALID = C_USERVALID_LOW ? ~read_data_valid_i : read_data_valid_i; + assign USERUNDERFLOW = C_USERUNDERFLOW_LOW ? ~(empty_q & rd_en_q) : empty_q & rd_en_q; + + always @ (posedge RD_CLK or posedge rd_rst_i) + begin + if (rd_rst_i && C_USE_DOUT_RST == 1) //asynchronous reset (active high) + USERDATA <= hexstr_conv(C_DOUT_RST_VAL); + else begin // rising clock edge + if (srst_i && C_USE_DOUT_RST == 1) + USERDATA <= hexstr_conv(C_DOUT_RST_VAL); + else if (ram_regout_en) + USERDATA <= FIFODATA; + end + end //always + + + + + +endmodule diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/FIFO_GENERATOR_V4_4_XST.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/FIFO_GENERATOR_V4_4_XST.v new file mode 100644 index 0000000..7176555 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/FIFO_GENERATOR_V4_4_XST.v @@ -0,0 +1,316 @@ +/* + * $RDCfile: $ $Revision: 1.2 $ $Date: 2008/09/09 20:25:45 $ + ******************************************************************************* + * + * FIFO Generator - Verilog Behavioral Model + * + ******************************************************************************* + * + * Copyright(C) 2006 by Xilinx, Inc. All rights reserved. + * This text/file contains proprietary, confidential + * information of Xilinx, Inc., is distributed under + * license from Xilinx, Inc., and may be used, copied + * and/or disclosed only pursuant to the terms of a valid + * license agreement with Xilinx, Inc. Xilinx hereby + * grants you a license to use this text/file solely for + * design, simulation, implementation and creation of + * design files limited to Xilinx devices or technologies. + * Use with non-Xilinx devices or technologies is expressly + * prohibited and immediately terminates your license unless + * covered by a separate agreement. + * + * Xilinx is providing theis design, code, or information + * "as-is" solely for use in developing programs and + * solutions for Xilinx devices, with no obligation on the + * part of Xilinx to provide support. By providing this design, + * code, or information as one possible implementation of + * this feature, application or standard. Xilinx is making no + * representation that this implementation is free from any + * claims of infringement. You are responsible for obtaining + * any rights you may require for your implementation. + * Xilinx expressly disclaims any warranty whatsoever with + * respect to the adequacy of the implementation, including + * but not limited to any warranties or representations that this + * implementation is free from claims of infringement, implied + * warranties of merchantability or fitness for a particular + * purpose. + * + * Xilinx products are not intended for use in life support + * appliances, devices, or systems. Use in such applications is + * expressly prohibited. + * + * This copyright and support notice must be retained as part + * of this text at all times. (c)Copyright 1995-2006 Xilinx, Inc. + * All rights reserved. + * + ******************************************************************************* + * + * Filename: fifo_generator_v4_4_bhv.v + * + * Description: + * The verilog behavioral model for the FIFO generator core. + * + ******************************************************************************* + */ + +`timescale 1ps/1ps + +/******************************************************************************* + * Declaration of top-level module + ******************************************************************************/ +module FIFO_GENERATOR_V4_4_XST + ( + BACKUP, + BACKUP_MARKER, + CLK, + DIN, + PROG_EMPTY_THRESH, + PROG_EMPTY_THRESH_ASSERT, + PROG_EMPTY_THRESH_NEGATE, + PROG_FULL_THRESH, + PROG_FULL_THRESH_ASSERT, + PROG_FULL_THRESH_NEGATE, + RD_CLK, + RD_EN, + RD_RST, + RST, + SRST, + WR_CLK, + WR_EN, + WR_RST, + INT_CLK, + + ALMOST_EMPTY, + ALMOST_FULL, + DATA_COUNT, + DOUT, + EMPTY, + FULL, + OVERFLOW, + PROG_EMPTY, + PROG_FULL, + RD_DATA_COUNT, + UNDERFLOW, + VALID, + WR_ACK, + WR_DATA_COUNT, + SBITERR, + DBITERR + ); + +/****************************************************************************** + * Definition of Ports + * + * + ***************************************************************************** + * Definition of Parameters + * + * + *****************************************************************************/ + +/****************************************************************************** + * Declare user parameters and their defaults + *****************************************************************************/ + parameter C_COMMON_CLOCK = 0; + parameter C_COUNT_TYPE = 0; + parameter C_DATA_COUNT_WIDTH = 2; + parameter C_DEFAULT_VALUE = ""; + parameter C_DIN_WIDTH = 8; + parameter C_DOUT_RST_VAL = ""; + parameter C_DOUT_WIDTH = 8; + parameter C_ENABLE_RLOCS = 0; + parameter C_FAMILY = "virtex2"; //Not allowed in Verilog model + parameter C_HAS_ALMOST_EMPTY = 0; + parameter C_HAS_ALMOST_FULL = 0; + parameter C_HAS_BACKUP = 0; + parameter C_HAS_DATA_COUNT = 0; + parameter C_HAS_MEMINIT_FILE = 0; + parameter C_HAS_OVERFLOW = 0; + parameter C_HAS_RD_DATA_COUNT = 0; + parameter C_HAS_RD_RST = 0; + parameter C_HAS_RST = 0; + parameter C_HAS_SRST = 0; + parameter C_HAS_UNDERFLOW = 0; + parameter C_HAS_VALID = 0; + parameter C_HAS_WR_ACK = 0; + parameter C_HAS_WR_DATA_COUNT = 0; + parameter C_HAS_WR_RST = 0; + parameter C_IMPLEMENTATION_TYPE = 0; + parameter C_INIT_WR_PNTR_VAL = 0; + parameter C_MEMORY_TYPE = 1; + parameter C_MIF_FILE_NAME = ""; + parameter C_OPTIMIZATION_MODE = 0; + parameter C_OVERFLOW_LOW = 0; + parameter C_PRELOAD_LATENCY = 1; + parameter C_PRELOAD_REGS = 0; + parameter C_PRIM_FIFO_TYPE = 512; + parameter C_PROG_EMPTY_THRESH_ASSERT_VAL = 0; + parameter C_PROG_EMPTY_THRESH_NEGATE_VAL = 0; + parameter C_PROG_EMPTY_TYPE = 0; + parameter C_PROG_FULL_THRESH_ASSERT_VAL = 0; + parameter C_PROG_FULL_THRESH_NEGATE_VAL = 0; + parameter C_PROG_FULL_TYPE = 0; + parameter C_RD_DATA_COUNT_WIDTH = 2; + parameter C_RD_DEPTH = 256; + parameter C_RD_FREQ = 1; + parameter C_RD_PNTR_WIDTH = 8; + parameter C_UNDERFLOW_LOW = 0; + parameter C_USE_DOUT_RST = 0; + parameter C_USE_EMBEDDED_REG = 0; + parameter C_USE_FIFO16_FLAGS = 0; + parameter C_USE_FWFT_DATA_COUNT = 0; + parameter C_VALID_LOW = 0; + parameter C_WR_ACK_LOW = 0; + parameter C_WR_DATA_COUNT_WIDTH = 2; + parameter C_WR_DEPTH = 256; + parameter C_WR_FREQ = 1; + parameter C_WR_PNTR_WIDTH = 8; + parameter C_WR_RESPONSE_LATENCY = 1; + parameter C_USE_ECC = 0; + parameter C_FULL_FLAGS_RST_VAL = 1; + parameter C_HAS_INT_CLK = 0; + parameter C_MSGON_VAL = 1; + + + /****************************************************************************** + * Declare Input and Output Ports + *****************************************************************************/ + input CLK; + input BACKUP; + input BACKUP_MARKER; + input [C_DIN_WIDTH-1:0] DIN; + input [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH; + input [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_ASSERT; + input [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_NEGATE; + input [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH; + input [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_ASSERT; + input [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_NEGATE; + input RD_CLK; + input RD_EN; + input RD_RST; + input RST; + input SRST; + input WR_CLK; + input WR_EN; + input WR_RST; + input INT_CLK; + + output ALMOST_EMPTY; + output ALMOST_FULL; + output [C_DATA_COUNT_WIDTH-1:0] DATA_COUNT; + output [C_DOUT_WIDTH-1:0] DOUT; + output EMPTY; + output FULL; + output OVERFLOW; + output PROG_EMPTY; + output PROG_FULL; + output VALID; + output [C_RD_DATA_COUNT_WIDTH-1:0] RD_DATA_COUNT; + output UNDERFLOW; + output WR_ACK; + output [C_WR_DATA_COUNT_WIDTH-1:0] WR_DATA_COUNT; + output SBITERR; + output DBITERR; + + FIFO_GENERATOR_V4_4 + #( + .C_COMMON_CLOCK (C_COMMON_CLOCK), + .C_COUNT_TYPE (C_COUNT_TYPE), + .C_DATA_COUNT_WIDTH (C_DATA_COUNT_WIDTH), + .C_DEFAULT_VALUE (C_DEFAULT_VALUE), + .C_DIN_WIDTH (C_DIN_WIDTH), + .C_DOUT_RST_VAL (C_DOUT_RST_VAL), + .C_DOUT_WIDTH (C_DOUT_WIDTH), + .C_ENABLE_RLOCS (C_ENABLE_RLOCS), + .C_FAMILY (C_FAMILY),//Not allowed in Verilog model + .C_HAS_ALMOST_EMPTY (C_HAS_ALMOST_EMPTY), + .C_HAS_ALMOST_FULL (C_HAS_ALMOST_FULL), + .C_HAS_BACKUP (C_HAS_BACKUP), + .C_HAS_DATA_COUNT (C_HAS_DATA_COUNT), + .C_HAS_MEMINIT_FILE (C_HAS_MEMINIT_FILE), + .C_HAS_OVERFLOW (C_HAS_OVERFLOW), + .C_HAS_RD_DATA_COUNT (C_HAS_RD_DATA_COUNT), + .C_HAS_RD_RST (C_HAS_RD_RST), + .C_HAS_RST (C_HAS_RST), + .C_HAS_SRST (C_HAS_SRST), + .C_HAS_UNDERFLOW (C_HAS_UNDERFLOW), + .C_HAS_VALID (C_HAS_VALID), + .C_HAS_WR_ACK (C_HAS_WR_ACK), + .C_HAS_WR_DATA_COUNT (C_HAS_WR_DATA_COUNT), + .C_HAS_WR_RST (C_HAS_WR_RST), + .C_IMPLEMENTATION_TYPE (C_IMPLEMENTATION_TYPE), + .C_INIT_WR_PNTR_VAL (C_INIT_WR_PNTR_VAL), + .C_MEMORY_TYPE (C_MEMORY_TYPE), + .C_MIF_FILE_NAME (C_MIF_FILE_NAME), + .C_OPTIMIZATION_MODE (C_OPTIMIZATION_MODE), + .C_OVERFLOW_LOW (C_OVERFLOW_LOW), + .C_PRELOAD_LATENCY (C_PRELOAD_LATENCY), + .C_PRELOAD_REGS (C_PRELOAD_REGS), + .C_PRIM_FIFO_TYPE (C_PRIM_FIFO_TYPE), + .C_PROG_EMPTY_THRESH_ASSERT_VAL (C_PROG_EMPTY_THRESH_ASSERT_VAL), + .C_PROG_EMPTY_THRESH_NEGATE_VAL (C_PROG_EMPTY_THRESH_NEGATE_VAL), + .C_PROG_EMPTY_TYPE (C_PROG_EMPTY_TYPE), + .C_PROG_FULL_THRESH_ASSERT_VAL (C_PROG_FULL_THRESH_ASSERT_VAL), + .C_PROG_FULL_THRESH_NEGATE_VAL (C_PROG_FULL_THRESH_NEGATE_VAL), + .C_PROG_FULL_TYPE (C_PROG_FULL_TYPE), + .C_RD_DATA_COUNT_WIDTH (C_RD_DATA_COUNT_WIDTH), + .C_RD_DEPTH (C_RD_DEPTH), + .C_RD_FREQ (C_RD_FREQ), + .C_RD_PNTR_WIDTH (C_RD_PNTR_WIDTH), + .C_UNDERFLOW_LOW (C_UNDERFLOW_LOW), + .C_USE_DOUT_RST (C_USE_DOUT_RST), + .C_USE_EMBEDDED_REG (C_USE_EMBEDDED_REG), + .C_USE_FIFO16_FLAGS (C_USE_FIFO16_FLAGS), + .C_USE_FWFT_DATA_COUNT (C_USE_FWFT_DATA_COUNT), + .C_VALID_LOW (C_VALID_LOW), + .C_WR_ACK_LOW (C_WR_ACK_LOW), + .C_WR_DATA_COUNT_WIDTH (C_WR_DATA_COUNT_WIDTH), + .C_WR_DEPTH (C_WR_DEPTH), + .C_WR_FREQ (C_WR_FREQ), + .C_WR_PNTR_WIDTH (C_WR_PNTR_WIDTH), + .C_WR_RESPONSE_LATENCY (C_WR_RESPONSE_LATENCY), + .C_USE_ECC (C_USE_ECC), + .C_FULL_FLAGS_RST_VAL (C_FULL_FLAGS_RST_VAL), + .C_HAS_INT_CLK (C_HAS_INT_CLK), + .C_MSGON_VAL (C_MSGON_VAL) + ) + fifo_generator_v4_4_dut + ( + .BACKUP (BACKUP), + .BACKUP_MARKER (BACKUP_MARKER), + .CLK (CLK), + .RST (RST), + .SRST (SRST), + .WR_CLK (WR_CLK), + .WR_RST (WR_RST), + .RD_CLK (RD_CLK), + .RD_RST (RD_RST), + .DIN (DIN), + .WR_EN (WR_EN), + .RD_EN (RD_EN), + .PROG_EMPTY_THRESH (PROG_EMPTY_THRESH), + .PROG_EMPTY_THRESH_ASSERT (PROG_EMPTY_THRESH_ASSERT), + .PROG_EMPTY_THRESH_NEGATE (PROG_EMPTY_THRESH_NEGATE), + .PROG_FULL_THRESH (PROG_FULL_THRESH), + .PROG_FULL_THRESH_ASSERT (PROG_FULL_THRESH_ASSERT), + .PROG_FULL_THRESH_NEGATE (PROG_FULL_THRESH_NEGATE), + .INT_CLK (INT_CLK), + .DOUT (DOUT), + .FULL (FULL), + .ALMOST_FULL (ALMOST_FULL), + .WR_ACK (WR_ACK), + .OVERFLOW (OVERFLOW), + .EMPTY (EMPTY), + .ALMOST_EMPTY (ALMOST_EMPTY), + .VALID (VALID), + .UNDERFLOW (UNDERFLOW), + .DATA_COUNT (DATA_COUNT), + .RD_DATA_COUNT (RD_DATA_COUNT), + .WR_DATA_COUNT (WR_DATA_COUNT), + .PROG_FULL (PROG_FULL), + .PROG_EMPTY (PROG_EMPTY), + .SBITERR (SBITERR), + .DBITERR (DBITERR) + ); + +endmodule diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/FIFO_GENERATOR_V5_1.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/FIFO_GENERATOR_V5_1.v new file mode 100644 index 0000000..cf96ebd --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/FIFO_GENERATOR_V5_1.v @@ -0,0 +1,4440 @@ +/* + * $RDCfile: $ $Revision: 1.3 $ $Date: 2009/09/08 15:26:50 $ + ******************************************************************************* + * + * FIFO Generator - Verilog Behavioral Model + * + ******************************************************************************* + * + * (c) Copyright 1995 - 2009 Xilinx, Inc. All rights reserved. + * + * This file contains confidential and proprietary information + * of Xilinx, Inc. and is protected under U.S. and + * international copyright and other intellectual property + * laws. + * + * DISCLAIMER + * This disclaimer is not a license and does not grant any + * rights to the materials distributed herewith. Except as + * otherwise provided in a valid license issued to you by + * Xilinx, and to the maximum extent permitted by applicable + * law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND + * WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES + * AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING + * BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- + * INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and + * (2) Xilinx shall not be liable (whether in contract or tort, + * including negligence, or under any other theory of + * liability) for any loss or damage of any kind or nature + * related to, arising under or in connection with these + * materials, including for any direct, or any indirect, + * special, incidental, or consequential loss or damage + * (including loss of data, profits, goodwill, or any type of + * loss or damage suffered as a result of any action brought + * by a third party) even if such damage or loss was + * reasonably foreseeable or Xilinx had been advised of the + * possibility of the same. + * + * CRITICAL APPLICATIONS + * Xilinx products are not designed or intended to be fail- + * safe, or for use in any application requiring fail-safe + * performance, such as life-support or safety devices or + * systems, Class III medical devices, nuclear facilities, + * applications related to the deployment of airbags, or any + * other applications that could lead to death, personal + * injury, or severe property or environmental damage + * (individually and collectively, "Critical + * Applications"). Customer assumes the sole risk and + * liability of any use of Xilinx products in Critical + * Applications, subject only to applicable laws and + * regulations governing limitations on product liability. + * + * THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS + * PART OF THIS FILE AT ALL TIMES. + * + ******************************************************************************* + ******************************************************************************* + * + * Filename: FIFO_GENERATOR_V5_1.v + * + * Author : Xilinx + * + ******************************************************************************* + * Structure: + * + * fifo_generator_v5_1.vhd + * | + * +-fifo_generator_v5_1_bhv_as + * | + * +-fifo_generator_v5_1_bhv_ss + * | + * +-fifo_generator_v5_1_bhv_preload0 + * + ******************************************************************************* + * Description: + * + * The Verilog behavioral model for the FIFO Generator. + * + * The behavioral model has three parts: + * - The behavioral model for independent clocks FIFOs (_as) + * - The behavioral model for common clock FIFOs (_ss) + * - The "preload logic" block which implements First-word Fall-through + * + ******************************************************************************* + * Description: + * The verilog behavioral model for the FIFO generator core. + * + ******************************************************************************* + */ + +`timescale 1ps/1ps +`ifndef TCQ + `define TCQ 100 +`endif + + +/******************************************************************************* + * Declaration of top-level module + ******************************************************************************/ +module FIFO_GENERATOR_V5_1 +( + BACKUP, //not used + BACKUP_MARKER, //not used + CLK, + DIN, + PROG_EMPTY_THRESH, + PROG_EMPTY_THRESH_ASSERT, + PROG_EMPTY_THRESH_NEGATE, + PROG_FULL_THRESH, + PROG_FULL_THRESH_ASSERT, + PROG_FULL_THRESH_NEGATE, + RD_CLK, + RD_EN, + RD_RST, + RST, + SRST, + WR_CLK, + WR_EN, + WR_RST, + INT_CLK, + INJECTDBITERR, + INJECTSBITERR, + + ALMOST_EMPTY, + ALMOST_FULL, + DATA_COUNT, + DOUT, + EMPTY, + FULL, + OVERFLOW, + PROG_EMPTY, + PROG_FULL, + RD_DATA_COUNT, + UNDERFLOW, + VALID, + WR_ACK, + WR_DATA_COUNT, + + SBITERR, + DBITERR + ); + +/* + ****************************************************************************** + * Definition of Parameters + ****************************************************************************** + * C_COMMON_CLOCK : Common Clock (1), Independent Clocks (0) + * C_COUNT_TYPE : *not used + * C_DATA_COUNT_WIDTH : Width of DATA_COUNT bus + * C_DEFAULT_VALUE : *not used + * C_DIN_WIDTH : Width of DIN bus + * C_DOUT_RST_VAL : Reset value of DOUT + * C_DOUT_WIDTH : Width of DOUT bus + * C_ENABLE_RLOCS : *not used + * C_FAMILY : not used in bhv model + * C_FULL_FLAGS_RST_VAL : Full flags rst val (0 or 1) + * C_HAS_ALMOST_EMPTY : 1=Core has ALMOST_EMPTY flag + * C_HAS_ALMOST_FULL : 1=Core has ALMOST_FULL flag + * C_HAS_BACKUP : *not used + * C_HAS_DATA_COUNT : 1=Core has DATA_COUNT bus + * C_HAS_INT_CLK : not used in bhv model + * C_HAS_MEMINIT_FILE : *not used + * C_HAS_OVERFLOW : 1=Core has OVERFLOW flag + * C_HAS_RD_DATA_COUNT : 1=Core has RD_DATA_COUNT bus + * C_HAS_RD_RST : *not used + * C_HAS_RST : 1=Core has Async Rst + * C_HAS_SRST : 1=Core has Sync Rst + * C_HAS_UNDERFLOW : 1=Core has UNDERFLOW flag + * C_HAS_VALID : 1=Core has VALID flag + * C_HAS_WR_ACK : 1=Core has WR_ACK flag + * C_HAS_WR_DATA_COUNT : 1=Core has WR_DATA_COUNT bus + * C_HAS_WR_RST : *not used + * C_IMPLEMENTATION_TYPE : 0=Common-Clock Bram/Dram + * 1=Common-Clock ShiftRam + * 2=Indep. Clocks Bram/Dram + * 3=Virtex-4 Built-in + * 4=Virtex-5 Built-in + * C_INIT_WR_PNTR_VAL : *not used + * C_MEMORY_TYPE : 1=Block RAM + * 2=Distributed RAM + * 3=Shift RAM + * 4=Built-in FIFO + * C_MIF_FILE_NAME : *not used + * C_OPTIMIZATION_MODE : *not used + * C_OVERFLOW_LOW : 1=OVERFLOW active low + * C_PRELOAD_LATENCY : Latency of read: 0, 1, 2 + * C_PRELOAD_REGS : 1=Use output registers + * C_PRIM_FIFO_TYPE : not used in bhv model + * C_PROG_EMPTY_THRESH_ASSERT_VAL: PROG_EMPTY assert threshold + * C_PROG_EMPTY_THRESH_NEGATE_VAL: PROG_EMPTY negate threshold + * C_PROG_EMPTY_TYPE : 0=No programmable empty + * 1=Single prog empty thresh constant + * 2=Multiple prog empty thresh constants + * 3=Single prog empty thresh input + * 4=Multiple prog empty thresh inputs + * C_PROG_FULL_THRESH_ASSERT_VAL : PROG_FULL assert threshold + * C_PROG_FULL_THRESH_NEGATE_VAL : PROG_FULL negate threshold + * C_PROG_FULL_TYPE : 0=No prog full + * 1=Single prog full thresh constant + * 2=Multiple prog full thresh constants + * 3=Single prog full thresh input + * 4=Multiple prog full thresh inputs + * C_RD_DATA_COUNT_WIDTH : Width of RD_DATA_COUNT bus + * C_RD_DEPTH : Depth of read interface (2^N) + * C_RD_FREQ : not used in bhv model + * C_RD_PNTR_WIDTH : always log2(C_RD_DEPTH) + * C_UNDERFLOW_LOW : 1=UNDERFLOW active low + * C_USE_DOUT_RST : 1=Resets DOUT on RST + * C_USE_ECC : Used for error injection purpose + * C_USE_EMBEDDED_REG : 1=Use BRAM embedded output register + * C_USE_FIFO16_FLAGS : not used in bhv model + * C_USE_FWFT_DATA_COUNT : 1=Use extra logic for FWFT data count + * C_VALID_LOW : 1=VALID active low + * C_WR_ACK_LOW : 1=WR_ACK active low + * C_WR_DATA_COUNT_WIDTH : Width of WR_DATA_COUNT bus + * C_WR_DEPTH : Depth of write interface (2^N) + * C_WR_FREQ : not used in bhv model + * C_WR_PNTR_WIDTH : always log2(C_WR_DEPTH) + * C_WR_RESPONSE_LATENCY : *not used + * C_MSGON_VAL : *not used by bhv model + * C_ENABLE_RST_SYNC : 0 = Use WR_RST & RD_RST + * 1 = Use RST + * C_ERROR_INJECTION_TYPE : 0 = No error injection + * 1 = Single bit error injection only + * 2 = Double bit error injection only + * 1 = Single and double bit error injection + ****************************************************************************** + * Definition of Ports + ****************************************************************************** + * BACKUP : Not used + * BACKUP_MARKER: Not used + * CLK : Clock + * DIN : Input data bus + * PROG_EMPTY_THRESH : Threshold for Programmable Empty Flag + * PROG_EMPTY_THRESH_ASSERT: Threshold for Programmable Empty Flag + * PROG_EMPTY_THRESH_NEGATE: Threshold for Programmable Empty Flag + * PROG_FULL_THRESH : Threshold for Programmable Full Flag + * PROG_FULL_THRESH_ASSERT : Threshold for Programmable Full Flag + * PROG_FULL_THRESH_NEGATE : Threshold for Programmable Full Flag + * RD_CLK : Read Domain Clock + * RD_EN : Read enable + * RD_RST : Read Reset + * RST : Asynchronous Reset + * SRST : Synchronous Reset + * WR_CLK : Write Domain Clock + * WR_EN : Write enable + * WR_RST : Write Reset + * INT_CLK : Internal Clock + * INJECTSBITERR: Inject Signle bit error + * INJECTDBITERR: Inject Double bit error + * ALMOST_EMPTY : One word remaining in FIFO + * ALMOST_FULL : One empty space remaining in FIFO + * DATA_COUNT : Number of data words in fifo( synchronous to CLK) + * DOUT : Output data bus + * EMPTY : Empty flag + * FULL : Full flag + * OVERFLOW : Last write rejected + * PROG_EMPTY : Programmable Empty Flag + * PROG_FULL : Programmable Full Flag + * RD_DATA_COUNT: Number of data words in fifo (synchronous to RD_CLK) + * UNDERFLOW : Last read rejected + * VALID : Last read acknowledged, DOUT bus VALID + * WR_ACK : Last write acknowledged + * WR_DATA_COUNT: Number of data words in fifo (synchronous to WR_CLK) + * SBITERR : Single Bit ECC Error Detected + * DBITERR : Double Bit ECC Error Detected + ****************************************************************************** + */ + + + /**************************************************************************** + * Declare user parameters and their defaults + *****************************************************************************/ + parameter C_COMMON_CLOCK = 0; + parameter C_COUNT_TYPE = 0; //not used + parameter C_DATA_COUNT_WIDTH = 2; + parameter C_DEFAULT_VALUE = ""; //not used + parameter C_DIN_WIDTH = 8; + parameter C_DOUT_RST_VAL = ""; + parameter C_DOUT_WIDTH = 8; + parameter C_ENABLE_RLOCS = 0; //not used + parameter C_FAMILY = "virtex2"; //not used in bhv model + parameter C_FULL_FLAGS_RST_VAL = 1; + parameter C_HAS_ALMOST_EMPTY = 0; + parameter C_HAS_ALMOST_FULL = 0; + parameter C_HAS_BACKUP = 0; //not used + parameter C_HAS_DATA_COUNT = 0; + parameter C_HAS_INT_CLK = 0; //not used in bhv model + parameter C_HAS_MEMINIT_FILE = 0; //not used + parameter C_HAS_OVERFLOW = 0; + parameter C_HAS_RD_DATA_COUNT = 0; + parameter C_HAS_RD_RST = 0; //not used + parameter C_HAS_RST = 0; + parameter C_HAS_SRST = 0; + parameter C_HAS_UNDERFLOW = 0; + parameter C_HAS_VALID = 0; + parameter C_HAS_WR_ACK = 0; + parameter C_HAS_WR_DATA_COUNT = 0; + parameter C_HAS_WR_RST = 0; //not used + parameter C_IMPLEMENTATION_TYPE = 0; + parameter C_INIT_WR_PNTR_VAL = 0; //not used + parameter C_MEMORY_TYPE = 1; + parameter C_MIF_FILE_NAME = ""; //not used + parameter C_OPTIMIZATION_MODE = 0; //not used + parameter C_OVERFLOW_LOW = 0; + parameter C_PRELOAD_LATENCY = 1; + parameter C_PRELOAD_REGS = 0; + parameter C_PRIM_FIFO_TYPE = ""; //not used in bhv model + parameter C_PROG_EMPTY_THRESH_ASSERT_VAL = 0; + parameter C_PROG_EMPTY_THRESH_NEGATE_VAL = 0; + parameter C_PROG_EMPTY_TYPE = 0; + parameter C_PROG_FULL_THRESH_ASSERT_VAL = 0; + parameter C_PROG_FULL_THRESH_NEGATE_VAL = 0; + parameter C_PROG_FULL_TYPE = 0; + parameter C_RD_DATA_COUNT_WIDTH = 2; + parameter C_RD_DEPTH = 256; + parameter C_RD_FREQ = 1; //not used in bhv model + parameter C_RD_PNTR_WIDTH = 8; + parameter C_UNDERFLOW_LOW = 0; + parameter C_USE_DOUT_RST = 0; + parameter C_USE_ECC = 0; //not used in bhv model + parameter C_USE_EMBEDDED_REG = 0; + parameter C_USE_FIFO16_FLAGS = 0; //not used in bhv model + parameter C_USE_FWFT_DATA_COUNT = 0; + parameter C_VALID_LOW = 0; + parameter C_WR_ACK_LOW = 0; + parameter C_WR_DATA_COUNT_WIDTH = 2; + parameter C_WR_DEPTH = 256; + parameter C_WR_FREQ = 1; //not used in bhv model + parameter C_WR_PNTR_WIDTH = 8; + parameter C_WR_RESPONSE_LATENCY = 1; //not used + parameter C_MSGON_VAL = 1; //not used + parameter C_ENABLE_RST_SYNC = 1; + parameter C_ERROR_INJECTION_TYPE = 0; + + + + /***************************************************************************** + * Derived parameters + ****************************************************************************/ + //There are 2 Verilog behavioral models + // 0 = Common-Clock FIFO/ShiftRam FIFO + // 1 = Independent Clocks FIFO + parameter C_VERILOG_IMPL = (C_IMPLEMENTATION_TYPE==0 ? 0 : + (C_IMPLEMENTATION_TYPE==1 ? 0 : + (C_IMPLEMENTATION_TYPE==2 ? 1 : 0))); + + /***************************************************************************** + * Declare Input and Output Ports + ****************************************************************************/ + input CLK; + input BACKUP; + input BACKUP_MARKER; + input [C_DIN_WIDTH-1:0] DIN; + input [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH; + input [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_ASSERT; + input [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_NEGATE; + input [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH; + input [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_ASSERT; + input [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_NEGATE; + input RD_CLK; + input RD_EN; + input RD_RST; + input RST; + input SRST; + input WR_CLK; + input WR_EN; + input WR_RST; + input INT_CLK; + input INJECTDBITERR; + input INJECTSBITERR; + + output ALMOST_EMPTY; + output ALMOST_FULL; + output [C_DATA_COUNT_WIDTH-1:0] DATA_COUNT; + output [C_DOUT_WIDTH-1:0] DOUT; + output EMPTY; + output FULL; + output OVERFLOW; + output PROG_EMPTY; + output PROG_FULL; + output VALID; + output [C_RD_DATA_COUNT_WIDTH-1:0] RD_DATA_COUNT; + output UNDERFLOW; + output WR_ACK; + output [C_WR_DATA_COUNT_WIDTH-1:0] WR_DATA_COUNT; + output SBITERR; + output DBITERR; + + + wire ALMOST_EMPTY; + wire ALMOST_FULL; + wire [C_DATA_COUNT_WIDTH-1:0] DATA_COUNT; + wire [C_DOUT_WIDTH-1:0] DOUT; + wire EMPTY; + wire FULL; + wire OVERFLOW; + wire PROG_EMPTY; + wire PROG_FULL; + wire VALID; + wire [C_RD_DATA_COUNT_WIDTH-1:0] RD_DATA_COUNT; + wire UNDERFLOW; + wire WR_ACK; + wire [C_WR_DATA_COUNT_WIDTH-1:0] WR_DATA_COUNT; + + + wire RD_CLK_P0_IN; + wire RST_P0_IN; + wire RD_EN_FIFO_IN; + wire RD_EN_P0_IN; + + wire ALMOST_EMPTY_FIFO_OUT; + wire ALMOST_FULL_FIFO_OUT; + wire [C_DATA_COUNT_WIDTH-1:0] DATA_COUNT_FIFO_OUT; + wire [C_DOUT_WIDTH-1:0] DOUT_FIFO_OUT; + wire EMPTY_FIFO_OUT; + wire FULL_FIFO_OUT; + wire OVERFLOW_FIFO_OUT; + wire PROG_EMPTY_FIFO_OUT; + wire PROG_FULL_FIFO_OUT; + wire VALID_FIFO_OUT; + wire [C_RD_DATA_COUNT_WIDTH-1:0] RD_DATA_COUNT_FIFO_OUT; + wire UNDERFLOW_FIFO_OUT; + wire WR_ACK_FIFO_OUT; + wire [C_WR_DATA_COUNT_WIDTH-1:0] WR_DATA_COUNT_FIFO_OUT; + + + //*************************************************************************** + // Internal Signals + // The core uses either the internal_ wires or the preload0_ wires depending + // on whether the core uses Preload0 or not. + // When using preload0, the internal signals connect the internal core to + // the preload logic, and the external core's interfaces are tied to the + // preload0 signals from the preload logic. + //*************************************************************************** + wire [C_DOUT_WIDTH-1:0] DATA_P0_OUT; + wire VALID_P0_OUT; + wire EMPTY_P0_OUT; + wire ALMOSTEMPTY_P0_OUT; + reg EMPTY_P0_OUT_Q; + reg ALMOSTEMPTY_P0_OUT_Q; + wire UNDERFLOW_P0_OUT; + wire RDEN_P0_OUT; + wire [C_DOUT_WIDTH-1:0] DATA_P0_IN; + wire EMPTY_P0_IN; + reg [31:0] DATA_COUNT_FWFT; + reg SS_FWFT_WR ; + reg SS_FWFT_RD ; + + wire SBITERR; + wire DBITERR; + wire sbiterr_fifo_out; + wire dbiterr_fifo_out; + + +// Choose the behavioral model to instantiate based on the C_VERILOG_IMPL +// parameter (1=Independent Clocks, 0=Common Clock) +generate +case (C_VERILOG_IMPL) +0 : begin : block1 + //Common Clock Behavioral Model + fifo_generator_v5_1_bhv_ver_ss + #( + C_DATA_COUNT_WIDTH, + C_DIN_WIDTH, + C_DOUT_RST_VAL, + C_DOUT_WIDTH, + C_FULL_FLAGS_RST_VAL, + C_HAS_ALMOST_EMPTY, + C_HAS_ALMOST_FULL, + C_HAS_DATA_COUNT, + C_HAS_OVERFLOW, + C_HAS_RD_DATA_COUNT, + C_HAS_RST, + C_HAS_SRST, + C_HAS_UNDERFLOW, + C_HAS_VALID, + C_HAS_WR_ACK, + C_HAS_WR_DATA_COUNT, + C_IMPLEMENTATION_TYPE, + C_MEMORY_TYPE, + C_OVERFLOW_LOW, + C_PRELOAD_LATENCY, + C_PRELOAD_REGS, + C_PROG_EMPTY_THRESH_ASSERT_VAL, + C_PROG_EMPTY_THRESH_NEGATE_VAL, + C_PROG_EMPTY_TYPE, + C_PROG_FULL_THRESH_ASSERT_VAL, + C_PROG_FULL_THRESH_NEGATE_VAL, + C_PROG_FULL_TYPE, + C_RD_DATA_COUNT_WIDTH, + C_RD_DEPTH, + C_RD_PNTR_WIDTH, + C_UNDERFLOW_LOW, + C_USE_DOUT_RST, + C_USE_EMBEDDED_REG, + C_USE_FWFT_DATA_COUNT, + C_VALID_LOW, + C_WR_ACK_LOW, + C_WR_DATA_COUNT_WIDTH, + C_WR_DEPTH, + C_WR_PNTR_WIDTH, + C_USE_ECC, + C_ENABLE_RST_SYNC, + C_ERROR_INJECTION_TYPE + ) + gen_ss + ( + .CLK (CLK), + .RST (RST), + .SRST (SRST), + .DIN (DIN), + .WR_EN (WR_EN), + .RD_EN (RD_EN_FIFO_IN), + .PROG_EMPTY_THRESH (PROG_EMPTY_THRESH), + .PROG_EMPTY_THRESH_ASSERT (PROG_EMPTY_THRESH_ASSERT), + .PROG_EMPTY_THRESH_NEGATE (PROG_EMPTY_THRESH_NEGATE), + .PROG_FULL_THRESH (PROG_FULL_THRESH), + .PROG_FULL_THRESH_ASSERT (PROG_FULL_THRESH_ASSERT), + .PROG_FULL_THRESH_NEGATE (PROG_FULL_THRESH_NEGATE), + .INJECTSBITERR (INJECTSBITERR), + .INJECTDBITERR (INJECTDBITERR), + .DOUT (DOUT_FIFO_OUT), + .FULL (FULL_FIFO_OUT), + .ALMOST_FULL (ALMOST_FULL_FIFO_OUT), + .WR_ACK (WR_ACK_FIFO_OUT), + .OVERFLOW (OVERFLOW_FIFO_OUT), + .EMPTY (EMPTY_FIFO_OUT), + .ALMOST_EMPTY (ALMOST_EMPTY_FIFO_OUT), + .VALID (VALID_FIFO_OUT), + .UNDERFLOW (UNDERFLOW_FIFO_OUT), + .DATA_COUNT (DATA_COUNT_FIFO_OUT), + .PROG_FULL (PROG_FULL_FIFO_OUT), + .PROG_EMPTY (PROG_EMPTY_FIFO_OUT), + .SBITERR (sbiterr_fifo_out), + .DBITERR (dbiterr_fifo_out) + ); +end +1 : begin : block1 + //Independent Clocks Behavioral Model + fifo_generator_v5_1_bhv_ver_as + #( + C_DATA_COUNT_WIDTH, + C_DIN_WIDTH, + C_DOUT_RST_VAL, + C_DOUT_WIDTH, + C_FULL_FLAGS_RST_VAL, + C_HAS_ALMOST_EMPTY, + C_HAS_ALMOST_FULL, + C_HAS_DATA_COUNT, + C_HAS_OVERFLOW, + C_HAS_RD_DATA_COUNT, + C_HAS_RST, + C_HAS_UNDERFLOW, + C_HAS_VALID, + C_HAS_WR_ACK, + C_HAS_WR_DATA_COUNT, + C_IMPLEMENTATION_TYPE, + C_MEMORY_TYPE, + C_OVERFLOW_LOW, + C_PRELOAD_LATENCY, + C_PRELOAD_REGS, + C_PROG_EMPTY_THRESH_ASSERT_VAL, + C_PROG_EMPTY_THRESH_NEGATE_VAL, + C_PROG_EMPTY_TYPE, + C_PROG_FULL_THRESH_ASSERT_VAL, + C_PROG_FULL_THRESH_NEGATE_VAL, + C_PROG_FULL_TYPE, + C_RD_DATA_COUNT_WIDTH, + C_RD_DEPTH, + C_RD_PNTR_WIDTH, + C_UNDERFLOW_LOW, + C_USE_DOUT_RST, + C_USE_EMBEDDED_REG, + C_USE_FWFT_DATA_COUNT, + C_VALID_LOW, + C_WR_ACK_LOW, + C_WR_DATA_COUNT_WIDTH, + C_WR_DEPTH, + C_WR_PNTR_WIDTH, + C_USE_ECC, + C_ENABLE_RST_SYNC, + C_ERROR_INJECTION_TYPE + ) + gen_as + ( + .WR_CLK (WR_CLK), + .RD_CLK (RD_CLK), + .RST (RST), + .WR_RST (WR_RST), + .RD_RST (RD_RST), + .DIN (DIN), + .WR_EN (WR_EN), + .RD_EN (RD_EN_FIFO_IN), + .PROG_EMPTY_THRESH (PROG_EMPTY_THRESH), + .PROG_EMPTY_THRESH_ASSERT (PROG_EMPTY_THRESH_ASSERT), + .PROG_EMPTY_THRESH_NEGATE (PROG_EMPTY_THRESH_NEGATE), + .PROG_FULL_THRESH (PROG_FULL_THRESH), + .PROG_FULL_THRESH_ASSERT (PROG_FULL_THRESH_ASSERT), + .PROG_FULL_THRESH_NEGATE (PROG_FULL_THRESH_NEGATE), + .INJECTSBITERR (INJECTSBITERR), + .INJECTDBITERR (INJECTDBITERR), + .DOUT (DOUT_FIFO_OUT), + .FULL (FULL_FIFO_OUT), + .ALMOST_FULL (ALMOST_FULL_FIFO_OUT), + .WR_ACK (WR_ACK_FIFO_OUT), + .OVERFLOW (OVERFLOW_FIFO_OUT), + .EMPTY (EMPTY_FIFO_OUT), + .ALMOST_EMPTY (ALMOST_EMPTY_FIFO_OUT), + .VALID (VALID_FIFO_OUT), + .UNDERFLOW (UNDERFLOW_FIFO_OUT), + .RD_DATA_COUNT (RD_DATA_COUNT_FIFO_OUT), + .WR_DATA_COUNT (WR_DATA_COUNT_FIFO_OUT), + .PROG_FULL (PROG_FULL_FIFO_OUT), + .PROG_EMPTY (PROG_EMPTY_FIFO_OUT), + .SBITERR (sbiterr_fifo_out), + .DBITERR (dbiterr_fifo_out) + ); +end + +default : begin : block1 + //Independent Clocks Behavioral Model + fifo_generator_v5_1_bhv_ver_as + #( + C_DATA_COUNT_WIDTH, + C_DIN_WIDTH, + C_DOUT_RST_VAL, + C_DOUT_WIDTH, + C_FULL_FLAGS_RST_VAL, + C_HAS_ALMOST_EMPTY, + C_HAS_ALMOST_FULL, + C_HAS_DATA_COUNT, + C_HAS_OVERFLOW, + C_HAS_RD_DATA_COUNT, + C_HAS_RST, + C_HAS_UNDERFLOW, + C_HAS_VALID, + C_HAS_WR_ACK, + C_HAS_WR_DATA_COUNT, + C_IMPLEMENTATION_TYPE, + C_MEMORY_TYPE, + C_OVERFLOW_LOW, + C_PRELOAD_LATENCY, + C_PRELOAD_REGS, + C_PROG_EMPTY_THRESH_ASSERT_VAL, + C_PROG_EMPTY_THRESH_NEGATE_VAL, + C_PROG_EMPTY_TYPE, + C_PROG_FULL_THRESH_ASSERT_VAL, + C_PROG_FULL_THRESH_NEGATE_VAL, + C_PROG_FULL_TYPE, + C_RD_DATA_COUNT_WIDTH, + C_RD_DEPTH, + C_RD_PNTR_WIDTH, + C_UNDERFLOW_LOW, + C_USE_DOUT_RST, + C_USE_EMBEDDED_REG, + C_USE_FWFT_DATA_COUNT, + C_VALID_LOW, + C_WR_ACK_LOW, + C_WR_DATA_COUNT_WIDTH, + C_WR_DEPTH, + C_WR_PNTR_WIDTH, + C_USE_ECC, + C_ENABLE_RST_SYNC, + C_ERROR_INJECTION_TYPE + ) + gen_as + ( + .WR_CLK (WR_CLK), + .RD_CLK (RD_CLK), + .RST (RST), + .WR_RST (WR_RST), + .RD_RST (RD_RST), + .DIN (DIN), + .WR_EN (WR_EN), + .RD_EN (RD_EN_FIFO_IN), + .PROG_EMPTY_THRESH (PROG_EMPTY_THRESH), + .PROG_EMPTY_THRESH_ASSERT (PROG_EMPTY_THRESH_ASSERT), + .PROG_EMPTY_THRESH_NEGATE (PROG_EMPTY_THRESH_NEGATE), + .PROG_FULL_THRESH (PROG_FULL_THRESH), + .PROG_FULL_THRESH_ASSERT (PROG_FULL_THRESH_ASSERT), + .PROG_FULL_THRESH_NEGATE (PROG_FULL_THRESH_NEGATE), + .INJECTSBITERR (INJECTSBITERR), + .INJECTDBITERR (INJECTDBITERR), + .DOUT (DOUT_FIFO_OUT), + .FULL (FULL_FIFO_OUT), + .ALMOST_FULL (ALMOST_FULL_FIFO_OUT), + .WR_ACK (WR_ACK_FIFO_OUT), + .OVERFLOW (OVERFLOW_FIFO_OUT), + .EMPTY (EMPTY_FIFO_OUT), + .ALMOST_EMPTY (ALMOST_EMPTY_FIFO_OUT), + .VALID (VALID_FIFO_OUT), + .UNDERFLOW (UNDERFLOW_FIFO_OUT), + .RD_DATA_COUNT (RD_DATA_COUNT_FIFO_OUT), + .WR_DATA_COUNT (WR_DATA_COUNT_FIFO_OUT), + .PROG_FULL (PROG_FULL_FIFO_OUT), + .PROG_EMPTY (PROG_EMPTY_FIFO_OUT), + .SBITERR (sbiterr_fifo_out), + .DBITERR (dbiterr_fifo_out) + ); +end + +endcase +endgenerate + + + //************************************************************************** + // Connect Internal Signals + // (Signals labeled internal_*) + // In the normal case, these signals tie directly to the FIFO's inputs and + // outputs. + // In the case of Preload Latency 0 or 1, there are intermediate + // signals between the internal FIFO and the preload logic. + //************************************************************************** + + + //*********************************************** + // If First-Word Fall-Through, instantiate + // the preload0 (FWFT) module + //*********************************************** + generate + if (C_PRELOAD_REGS==1 && C_PRELOAD_LATENCY==0) begin : block2 + + + fifo_generator_v5_1_bhv_ver_preload0 + #( + C_DOUT_RST_VAL, + C_DOUT_WIDTH, + C_HAS_RST, + C_ENABLE_RST_SYNC, + C_HAS_SRST, + C_USE_DOUT_RST, + C_VALID_LOW, + C_UNDERFLOW_LOW + ) + fgpl0 + ( + .RD_CLK (RD_CLK_P0_IN), + .RD_RST (RST_P0_IN), + .SRST (SRST), + .RD_EN (RD_EN_P0_IN), + .FIFOEMPTY (EMPTY_P0_IN), + .FIFODATA (DATA_P0_IN), + .FIFOSBITERR (sbiterr_fifo_out), + .FIFODBITERR (dbiterr_fifo_out), + .USERDATA (DATA_P0_OUT), + .USERVALID (VALID_P0_OUT), + .USEREMPTY (EMPTY_P0_OUT), + .USERALMOSTEMPTY (ALMOSTEMPTY_P0_OUT), + .USERUNDERFLOW (UNDERFLOW_P0_OUT), + .RAMVALID (RAMVALID_P0_OUT), + .FIFORDEN (RDEN_P0_OUT), + .USERSBITERR (SBITERR), + .USERDBITERR (DBITERR) + ); + + + //*********************************************** + // Connect inputs to preload (FWFT) module + //*********************************************** + //Connect the RD_CLK of the Preload (FWFT) module to CLK if we + // have a common-clock FIFO, or RD_CLK if we have an + // independent clock FIFO + assign RD_CLK_P0_IN = ((C_VERILOG_IMPL == 0) ? CLK : RD_CLK); + assign RST_P0_IN = (C_ENABLE_RST_SYNC == 0) ? RD_RST : RST; + assign RD_EN_P0_IN = RD_EN; + assign EMPTY_P0_IN = EMPTY_FIFO_OUT; + assign DATA_P0_IN = DOUT_FIFO_OUT; + + //*********************************************** + // Connect outputs from preload (FWFT) module + //*********************************************** + assign DOUT = DATA_P0_OUT; + assign VALID = VALID_P0_OUT ; + assign EMPTY = EMPTY_P0_OUT; + assign ALMOST_EMPTY = ALMOSTEMPTY_P0_OUT; + assign UNDERFLOW = UNDERFLOW_P0_OUT ; + + assign RD_EN_FIFO_IN = RDEN_P0_OUT; + + + //*********************************************** + // Create DATA_COUNT from First-Word Fall-Through + // data count + //*********************************************** + assign DATA_COUNT = (C_USE_FWFT_DATA_COUNT == 0)? DATA_COUNT_FIFO_OUT: + (C_DATA_COUNT_WIDTH>C_RD_PNTR_WIDTH) ? DATA_COUNT_FWFT[C_RD_PNTR_WIDTH:0] : + DATA_COUNT_FWFT[C_RD_PNTR_WIDTH:C_RD_PNTR_WIDTH-C_DATA_COUNT_WIDTH+1]; + + //*********************************************** + // Create DATA_COUNT from First-Word Fall-Through + // data count + //*********************************************** + always @ (posedge RD_CLK or posedge RST_P0_IN) begin + if (RST_P0_IN) begin + EMPTY_P0_OUT_Q <= #`TCQ 1; + ALMOSTEMPTY_P0_OUT_Q <= #`TCQ 1; + end else begin + EMPTY_P0_OUT_Q <= #`TCQ EMPTY_P0_OUT; + ALMOSTEMPTY_P0_OUT_Q <= #`TCQ ALMOSTEMPTY_P0_OUT; + end + end //always + + + //*********************************************** + // logic for common-clock data count when FWFT is selected + //*********************************************** + initial begin + SS_FWFT_RD = 1'b0; + DATA_COUNT_FWFT = 0 ; + SS_FWFT_WR = 1'b0 ; + end //initial + + + //*********************************************** + // common-clock data count is implemented as an + // up-down counter. SS_FWFT_WR and SS_FWFT_RD + // are the up/down enables for the counter. + //*********************************************** + always @ (RD_EN or VALID_P0_OUT or WR_EN or FULL_FIFO_OUT) begin + if (C_VALID_LOW == 1) begin + SS_FWFT_RD = RD_EN && ~VALID_P0_OUT ; + end else begin + SS_FWFT_RD = RD_EN && VALID_P0_OUT ; + end + SS_FWFT_WR = (WR_EN && (~FULL_FIFO_OUT)) ; + end + + //*********************************************** + // common-clock data count is implemented as an + // up-down counter for FWFT. This always block + // calculates the counter. + //*********************************************** + always @ (posedge RD_CLK_P0_IN or posedge RST_P0_IN) begin + if (RST_P0_IN) begin + DATA_COUNT_FWFT <= #`TCQ 0; + end else begin + if (SRST && (C_HAS_SRST == 1) ) begin + DATA_COUNT_FWFT <= #`TCQ 0; + end else begin + case ( {SS_FWFT_WR, SS_FWFT_RD}) + 2'b00: DATA_COUNT_FWFT <= #`TCQ DATA_COUNT_FWFT ; + 2'b01: DATA_COUNT_FWFT <= #`TCQ DATA_COUNT_FWFT - 1 ; + 2'b10: DATA_COUNT_FWFT <= #`TCQ DATA_COUNT_FWFT + 1 ; + 2'b11: DATA_COUNT_FWFT <= #`TCQ DATA_COUNT_FWFT ; + endcase + end //if SRST + end //IF RST + end //always + + + end else begin : block2 //if !(C_PRELOAD_REGS==1 && C_PRELOAD_LATENCY==0) + + //*********************************************** + // If NOT First-Word Fall-Through, wire the outputs + // of the internal _ss or _as FIFO directly to the + // output, and do not instantiate the preload0 + // module. + //*********************************************** + + assign RD_CLK_P0_IN = 0; + assign RST_P0_IN = 0; + assign RD_EN_P0_IN = 0; + + assign RD_EN_FIFO_IN = RD_EN; + + assign DOUT = DOUT_FIFO_OUT; + assign DATA_P0_IN = 0; + assign VALID = VALID_FIFO_OUT; + assign EMPTY = EMPTY_FIFO_OUT; + assign ALMOST_EMPTY = ALMOST_EMPTY_FIFO_OUT; + assign EMPTY_P0_IN = 0; + assign UNDERFLOW = UNDERFLOW_FIFO_OUT; + assign DATA_COUNT = DATA_COUNT_FIFO_OUT; + assign SBITERR = sbiterr_fifo_out; + assign DBITERR = dbiterr_fifo_out; + + end //if !(C_PRELOAD_REGS==1 && C_PRELOAD_LATENCY==0) + endgenerate + + + //*********************************************** + // Connect user flags to internal signals + //*********************************************** + + //If we are using extra logic for the FWFT data count, then override the + //RD_DATA_COUNT output when we are EMPTY or ALMOST_EMPTY. + //RD_DATA_COUNT is 0 when EMPTY and 1 when ALMOST_EMPTY. + generate + if (C_USE_FWFT_DATA_COUNT==1 && (C_RD_DATA_COUNT_WIDTH>C_RD_PNTR_WIDTH) ) begin : block3 + assign RD_DATA_COUNT = (EMPTY_P0_OUT_Q | RST_P0_IN) ? 0 : (ALMOSTEMPTY_P0_OUT_Q ? 1 : RD_DATA_COUNT_FIFO_OUT); + end //block3 + endgenerate + + //If we are using extra logic for the FWFT data count, then override the + //RD_DATA_COUNT output when we are EMPTY or ALMOST_EMPTY. + //Due to asymmetric ports, RD_DATA_COUNT is 0 when EMPTY or ALMOST_EMPTY. + generate + if (C_USE_FWFT_DATA_COUNT==1 && (C_RD_DATA_COUNT_WIDTH <=C_RD_PNTR_WIDTH) ) begin : block30 + assign RD_DATA_COUNT = (EMPTY_P0_OUT_Q | RST_P0_IN) ? 0 : (ALMOSTEMPTY_P0_OUT_Q ? 0 : RD_DATA_COUNT_FIFO_OUT); + end //block30 + endgenerate + + //If we are not using extra logic for the FWFT data count, + //then connect RD_DATA_COUNT to the RD_DATA_COUNT from the + //internal FIFO instance + generate + if (C_USE_FWFT_DATA_COUNT==0 ) begin : block31 + assign RD_DATA_COUNT = RD_DATA_COUNT_FIFO_OUT; + end + endgenerate + + //Always connect WR_DATA_COUNT to the WR_DATA_COUNT from the internal + //FIFO instance + generate + if (C_USE_FWFT_DATA_COUNT==1) begin : block4 + assign WR_DATA_COUNT = WR_DATA_COUNT_FIFO_OUT; + end + else begin : block4 + assign WR_DATA_COUNT = WR_DATA_COUNT_FIFO_OUT; + end + endgenerate + + + //Connect other flags to the internal FIFO instance + assign FULL = FULL_FIFO_OUT; + assign ALMOST_FULL = ALMOST_FULL_FIFO_OUT; + assign WR_ACK = WR_ACK_FIFO_OUT; + assign OVERFLOW = OVERFLOW_FIFO_OUT; + assign PROG_FULL = PROG_FULL_FIFO_OUT; + assign PROG_EMPTY = PROG_EMPTY_FIFO_OUT; + + + // if an asynchronous FIFO has been selected, display a message that the FIFO + // will not be cycle-accurate in simulation + initial begin + if (C_IMPLEMENTATION_TYPE == 2) begin + $display("WARNING: Behavioral models for independent clock FIFO configurations are not cycle-accurate. You may wish to choose the structural simulation model instead of the behavioral model. This will ensure accurate behavior and latencies during simulation. You can enable this from CORE Generator by selecting Project -> Project Options -> Generation tab -> Structural Simulation. See the FIFO Generator User Guide for more information."); + end else if (C_MEMORY_TYPE == 4) begin + $display("FAILURE : Behavioral models for Virtex-4, Virtex-5 and Virtex-6 built-in FIFO configurations is currently not supported. Please select the structural simulation model option in CORE Generator. You can enable this in CORE Generator by selecting Project -> Project Options -> Generation tab -> Structural Simulation. See the FIFO Generator User Guide for more information."); + $finish; + end + end //initial + +endmodule //FIFO_GENERATOR_V5_1 + + + +/******************************************************************************* + * Declaration of Independent-Clocks FIFO Module + ******************************************************************************/ +module fifo_generator_v5_1_bhv_ver_as + ( + WR_CLK, RD_CLK, RST, WR_RST, RD_RST, DIN, WR_EN, RD_EN, + PROG_EMPTY_THRESH, PROG_EMPTY_THRESH_ASSERT, PROG_EMPTY_THRESH_NEGATE, + PROG_FULL_THRESH, PROG_FULL_THRESH_ASSERT, PROG_FULL_THRESH_NEGATE, + INJECTDBITERR, INJECTSBITERR, DOUT, FULL, ALMOST_FULL, WR_ACK, OVERFLOW, + EMPTY, ALMOST_EMPTY, VALID, UNDERFLOW, RD_DATA_COUNT, WR_DATA_COUNT, + PROG_FULL, PROG_EMPTY, SBITERR, DBITERR + ); + + /*************************************************************************** + * Declare user parameters and their defaults + ***************************************************************************/ + parameter C_DATA_COUNT_WIDTH = 2; + parameter C_DIN_WIDTH = 8; + parameter C_DOUT_RST_VAL = ""; + parameter C_DOUT_WIDTH = 8; + parameter C_FULL_FLAGS_RST_VAL = 1; + parameter C_HAS_ALMOST_EMPTY = 0; + parameter C_HAS_ALMOST_FULL = 0; + parameter C_HAS_DATA_COUNT = 0; + parameter C_HAS_OVERFLOW = 0; + parameter C_HAS_RD_DATA_COUNT = 0; + parameter C_HAS_RST = 0; + parameter C_HAS_UNDERFLOW = 0; + parameter C_HAS_VALID = 0; + parameter C_HAS_WR_ACK = 0; + parameter C_HAS_WR_DATA_COUNT = 0; + parameter C_IMPLEMENTATION_TYPE = 0; + parameter C_MEMORY_TYPE = 1; + parameter C_OVERFLOW_LOW = 0; + parameter C_PRELOAD_LATENCY = 1; + parameter C_PRELOAD_REGS = 0; + parameter C_PROG_EMPTY_THRESH_ASSERT_VAL = 0; + parameter C_PROG_EMPTY_THRESH_NEGATE_VAL = 0; + parameter C_PROG_EMPTY_TYPE = 0; + parameter C_PROG_FULL_THRESH_ASSERT_VAL = 0; + parameter C_PROG_FULL_THRESH_NEGATE_VAL = 0; + parameter C_PROG_FULL_TYPE = 0; + parameter C_RD_DATA_COUNT_WIDTH = 2; + parameter C_RD_DEPTH = 256; + parameter C_RD_PNTR_WIDTH = 8; + parameter C_UNDERFLOW_LOW = 0; + parameter C_USE_DOUT_RST = 0; + parameter C_USE_EMBEDDED_REG = 0; + parameter C_USE_FWFT_DATA_COUNT = 0; + parameter C_VALID_LOW = 0; + parameter C_WR_ACK_LOW = 0; + parameter C_WR_DATA_COUNT_WIDTH = 2; + parameter C_WR_DEPTH = 256; + parameter C_WR_PNTR_WIDTH = 8; + parameter C_USE_ECC = 0; + parameter C_ENABLE_RST_SYNC = 1; + parameter C_ERROR_INJECTION_TYPE = 0; + + /*************************************************************************** + * Declare Input and Output Ports + ***************************************************************************/ + input [C_DIN_WIDTH-1:0] DIN; + input [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH; + input [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_ASSERT; + input [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_NEGATE; + input [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH; + input [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_ASSERT; + input [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_NEGATE; + input RD_CLK; + input RD_EN; + input RST; + input WR_RST; + input RD_RST; + input WR_CLK; + input WR_EN; + input INJECTDBITERR; + input INJECTSBITERR; + output ALMOST_EMPTY; + output ALMOST_FULL; + output [C_DOUT_WIDTH-1:0] DOUT; + output EMPTY; + output FULL; + output OVERFLOW; + output PROG_EMPTY; + output PROG_FULL; + output VALID; + output [C_RD_DATA_COUNT_WIDTH-1:0] RD_DATA_COUNT; + output UNDERFLOW; + output WR_ACK; + output [C_WR_DATA_COUNT_WIDTH-1:0] WR_DATA_COUNT; + output SBITERR; + output DBITERR; + + /************************************************************************* + * Declare the type for each Input/Output port, and connect each I/O + * to it's associated internal signal in the behavioral model + * + * The values for the outputs are assigned in assign statements immediately + * following wire, parameter, and function declarations in this code. + *************************************************************************/ + //Inputs + wire [C_DIN_WIDTH-1:0] DIN; + wire [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH; + wire [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_ASSERT; + wire [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_NEGATE; + wire [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH; + wire [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_ASSERT; + wire [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_NEGATE; + wire RD_CLK; + wire RD_EN; + wire RST; + wire WR_RST; + wire RD_RST; + wire WR_CLK; + wire WR_EN; + wire INJECTSBITERR; + wire INJECTDBITERR; + + //Outputs + wire ALMOST_EMPTY; + wire ALMOST_FULL; + wire [C_DOUT_WIDTH-1:0] DOUT; + wire EMPTY; + wire FULL; + wire OVERFLOW; + wire PROG_EMPTY; + wire PROG_FULL; + wire VALID; + wire [C_RD_DATA_COUNT_WIDTH-1:0] RD_DATA_COUNT; + wire UNDERFLOW; + wire WR_ACK; + wire [C_WR_DATA_COUNT_WIDTH-1:0] WR_DATA_COUNT; + wire SBITERR; + wire DBITERR; + + + /*************************************************************************** + * Parameters used as constants + **************************************************************************/ + //When RST is present, set FULL reset value to '1'. + //If core has no RST, make sure FULL powers-on as '0'. + parameter C_DEPTH_RATIO_WR = + (C_WR_DEPTH>C_RD_DEPTH) ? (C_WR_DEPTH/C_RD_DEPTH) : 1; + parameter C_DEPTH_RATIO_RD = + (C_RD_DEPTH>C_WR_DEPTH) ? (C_RD_DEPTH/C_WR_DEPTH) : 1; + parameter C_FIFO_WR_DEPTH = C_WR_DEPTH - 1; + parameter C_FIFO_RD_DEPTH = C_RD_DEPTH - 1; + + + // EXTRA_WORDS = 2 * C_DEPTH_RATIO_WR / C_DEPTH_RATIO_RD + // WR_DEPTH : RD_DEPTH = 1:2 => EXTRA_WORDS = 1 + // WR_DEPTH : RD_DEPTH = 1:4 => EXTRA_WORDS = 1 (rounded to ceiling) + // WR_DEPTH : RD_DEPTH = 2:1 => EXTRA_WORDS = 4 + // WR_DEPTH : RD_DEPTH = 4:1 => EXTRA_WORDS = 8 + parameter EXTRA_WORDS = (C_DEPTH_RATIO_RD > 1)? 1:(2 * C_DEPTH_RATIO_WR); + // extra_words_dc = 2 * C_DEPTH_RATIO_WR / C_DEPTH_RATIO_RD + // C_DEPTH_RATIO_WR | C_DEPTH_RATIO_RD | C_PNTR_WIDTH | EXTRA_WORDS_DC + // -----------------|------------------|-----------------|--------------- + // 1 | 8 | C_RD_PNTR_WIDTH | 0 + // 1 | 4 | C_RD_PNTR_WIDTH | 0 + // 1 | 2 | C_RD_PNTR_WIDTH | 1 + // 1 | 1 | C_WR_PNTR_WIDTH | 2 + // 2 | 1 | C_WR_PNTR_WIDTH | 4 + // 4 | 1 | C_WR_PNTR_WIDTH | 8 + // 8 | 1 | C_WR_PNTR_WIDTH | 16 + parameter EXTRA_WORDS_DC = ( C_DEPTH_RATIO_RD > 2)? + 0:(2 * C_DEPTH_RATIO_WR/C_DEPTH_RATIO_RD); + + + parameter [31:0] reads_per_write = C_DIN_WIDTH/C_DOUT_WIDTH; + + parameter [31:0] log2_reads_per_write = log2_val(reads_per_write); + + parameter [31:0] writes_per_read = C_DOUT_WIDTH/C_DIN_WIDTH; + + parameter [31:0] log2_writes_per_read = log2_val(writes_per_read); + + + + /************************************************************************** + * FIFO Contents Tracking and Data Count Calculations + *************************************************************************/ + + // Memory which will be used to simulate a FIFO + reg [C_DIN_WIDTH-1:0] memory[C_WR_DEPTH-1:0]; + // Local parameters used to determine whether to inject ECC error or not + localparam SYMMETRIC_PORT = (C_DIN_WIDTH == C_DOUT_WIDTH) ? 1 : 0; + localparam ERR_INJECTION = (C_ERROR_INJECTION_TYPE != 0) ? 1 : 0; + localparam ENABLE_ERR_INJECTION = C_USE_ECC && SYMMETRIC_PORT && ERR_INJECTION; + // Array that holds the error injection type (single/double bit error) on + // a specific write operation, which is returned on read to corrupt the + // output data. + reg [1:0] ecc_err[C_WR_DEPTH-1:0]; + + //The amount of data stored in the FIFO at any time is given + // by num_wr_bits (in the WR_CLK domain) and num_rd_bits (in the RD_CLK + // domain. + //num_wr_bits is calculated by considering the total words in the FIFO, + // and the state of the read pointer (which may not have yet crossed clock + // domains.) + //num_rd_bits is calculated by considering the total words in the FIFO, + // and the state of the write pointer (which may not have yet crossed clock + // domains.) + reg [31:0] num_wr_bits; + reg [31:0] num_rd_bits; + reg [31:0] next_num_wr_bits; + reg [31:0] next_num_rd_bits; + + //The write pointer - tracks write operations + // (Works opposite to core: wr_ptr is a DOWN counter) + reg [31:0] wr_ptr; + + //The read pointer - tracks read operations + // (Works opposite to core: rd_ptr is a DOWN counter) + reg [31:0] rd_ptr; + + //Pointers passed into opposite clock domain + reg [31:0] wr_ptr_rdclk; + reg [31:0] wr_ptr_rdclk_next; + reg [31:0] rd_ptr_wrclk; + reg [31:0] rd_ptr_wrclk_next; + + //Amount of data stored in the FIFO scaled to the narrowest (deepest) port + // (Do not include data in FWFT stages) + //Used to calculate PROG_EMPTY. + wire [31:0] num_read_words_pe = + num_rd_bits/(C_DOUT_WIDTH/C_DEPTH_RATIO_WR); + + //Amount of data stored in the FIFO scaled to the narrowest (deepest) port + // (Do not include data in FWFT stages) + //Used to calculate PROG_FULL. + wire [31:0] num_write_words_pf = + num_wr_bits/(C_DIN_WIDTH/C_DEPTH_RATIO_RD); + + /************************** + * Read Data Count + *************************/ + + /* ORIGINAL CODE - Removed 10/24/07 jeo + //Amount of data stored in the FIFO scaled to read words + // (Do not include data in FWFT stages) + //Not used in the code. + wire [31:0] num_read_words_dc = num_rd_bits/C_DOUT_WIDTH; + + //Amount of data stored in the FIFO scaled to read words + // (Include data in FWFT stages) + //Not used in the code. + wire [31:0] num_read_words_fwft_dc = (num_rd_bits/C_DOUT_WIDTH+2); + + //Not used in the code. + wire [31:0] num_read_words_dc_i = + C_USE_FWFT_DATA_COUNT ? num_read_words_fwft_dc : num_read_words_dc; + + //Not used in the code. + wire [C_RD_DATA_COUNT_WIDTH-1:0] num_read_words_sized = + num_read_words_dc_i[C_RD_PNTR_WIDTH-1 : C_RD_PNTR_WIDTH-C_RD_DATA_COUNT_WIDTH]; + + //Not used in the code. + wire [C_RD_DATA_COUNT_WIDTH-1:0] num_read_words_sized_fwft = + num_read_words_dc_i[C_RD_PNTR_WIDTH : C_RD_PNTR_WIDTH-C_RD_DATA_COUNT_WIDTH+1]; + + //Used to calculate ideal_rd_count (RD_DATA_COUNT) + wire [C_RD_DATA_COUNT_WIDTH-1:0] num_read_words_sized_i = + C_USE_FWFT_DATA_COUNT ? num_read_words_sized_fwft : num_read_words_sized; + */ + + reg [31:0] num_read_words_dc; + reg [C_RD_DATA_COUNT_WIDTH-1:0] num_read_words_sized_i; + + always @(num_rd_bits) begin + if (C_USE_FWFT_DATA_COUNT) begin + + //If using extra logic for FWFT Data Counts, + // then scale FIFO contents to read domain, + // and add two read words for FWFT stages + //This value is only a temporary value and not used in the code. + num_read_words_dc = (num_rd_bits/C_DOUT_WIDTH+2); + + //Trim the read words for use with RD_DATA_COUNT + num_read_words_sized_i = + num_read_words_dc[C_RD_PNTR_WIDTH : C_RD_PNTR_WIDTH-C_RD_DATA_COUNT_WIDTH+1]; + + end else begin + + //If not using extra logic for FWFT Data Counts, + // then scale FIFO contents to read domain. + //This value is only a temporary value and not used in the code. + num_read_words_dc = num_rd_bits/C_DOUT_WIDTH; + + //Trim the read words for use with RD_DATA_COUNT + num_read_words_sized_i = + num_read_words_dc[C_RD_PNTR_WIDTH-1 : C_RD_PNTR_WIDTH-C_RD_DATA_COUNT_WIDTH]; + + end //if (C_USE_FWFT_DATA_COUNT) + end //always + + + + + + + + + /************************** + * Write Data Count + *************************/ + /* ORIGINAL CODE - Removed 10/24/07 jeo + + //Calculate the Data Count value for the number of write words, when not + // using First-Word Fall-Through with extra logic for Data Counts. This + // calculates only the number of words in the internal FIFO. + //The expression (((A-1)/B))+1 divides A/B, but takes the + // ceiling of the result. + //When num_wr_bits==0, set the result manually to prevent division errors. + wire [31:0] num_write_words_dc = + (num_wr_bits==0) ? 0 : ((num_wr_bits-1)/C_DIN_WIDTH) + 1; + + //Calculate the Data Count value for the number of write words, when using + // First-Word Fall-Through with extra logic for Data Counts. This takes into + // consideration the number of words that are expected to be stored in the + // FWFT register stages (it always assumes they are filled). + //The expression (((A-1)/B))+1 divides A/B, but takes the + // ceiling of the result. + //When num_wr_bits==0, set the result manually to prevent division errors. + //EXTRA_WORDS_DC is the number of words added to write_words due to FWFT. + wire [31:0] num_write_words_fwft_dc = + (num_wr_bits==0) ? EXTRA_WORDS_DC : (((num_wr_bits-1)/C_DIN_WIDTH) + 1) + EXTRA_WORDS_DC ; + + wire [31:0] num_write_words_dc_i = + C_USE_FWFT_DATA_COUNT ? num_write_words_fwft_dc : num_write_words_dc; + + + + wire [C_WR_DATA_COUNT_WIDTH-1:0] num_write_words_sized = + num_write_words_dc_i[C_WR_PNTR_WIDTH-1 : C_WR_PNTR_WIDTH-C_WR_DATA_COUNT_WIDTH]; + + wire [C_WR_DATA_COUNT_WIDTH-1:0] num_write_words_sized_fwft = + num_write_words_dc_i[C_WR_PNTR_WIDTH : C_WR_PNTR_WIDTH-C_WR_DATA_COUNT_WIDTH+1]; + + wire [C_WR_DATA_COUNT_WIDTH-1:0] num_write_words_sized_i = C_USE_FWFT_DATA_COUNT? + num_write_words_sized_fwft:num_write_words_sized; + + */ + + reg [31:0] num_write_words_dc; + reg [C_WR_DATA_COUNT_WIDTH-1:0] num_write_words_sized_i; + + always @(num_wr_bits) begin + if (C_USE_FWFT_DATA_COUNT) begin + + //Calculate the Data Count value for the number of write words, + // when using First-Word Fall-Through with extra logic for Data + // Counts. This takes into consideration the number of words that + // are expected to be stored in the FWFT register stages (it always + // assumes they are filled). + //This value is scaled to the Write Domain. + //The expression (((A-1)/B))+1 divides A/B, but takes the + // ceiling of the result. + //When num_wr_bits==0, set the result manually to prevent + // division errors. + //EXTRA_WORDS_DC is the number of words added to write_words + // due to FWFT. + //This value is only a temporary value and not used in the code. + num_write_words_dc = (num_wr_bits==0) ? EXTRA_WORDS_DC : (((num_wr_bits-1)/C_DIN_WIDTH)+1) + EXTRA_WORDS_DC ; + + //Trim the write words for use with WR_DATA_COUNT + num_write_words_sized_i = + num_write_words_dc[C_WR_PNTR_WIDTH : C_WR_PNTR_WIDTH-C_WR_DATA_COUNT_WIDTH+1]; + + end else begin + + //Calculate the Data Count value for the number of write words, when NOT + // using First-Word Fall-Through with extra logic for Data Counts. This + // calculates only the number of words in the internal FIFO. + //The expression (((A-1)/B))+1 divides A/B, but takes the + // ceiling of the result. + //This value is scaled to the Write Domain. + //When num_wr_bits==0, set the result manually to prevent + // division errors. + //This value is only a temporary value and not used in the code. + num_write_words_dc = (num_wr_bits==0) ? 0 : ((num_wr_bits-1)/C_DIN_WIDTH)+1; + + //Trim the read words for use with RD_DATA_COUNT + num_write_words_sized_i = + num_write_words_dc[C_WR_PNTR_WIDTH-1 : C_WR_PNTR_WIDTH-C_WR_DATA_COUNT_WIDTH]; + + end //if (C_USE_FWFT_DATA_COUNT) + end //always + + + + /*************************************************************************** + * Internal registers and wires + **************************************************************************/ + + //Temporary signals used for calculating the model's outputs. These + //are only used in the assign statements immediately following wire, + //parameter, and function declarations. + wire [C_DOUT_WIDTH-1:0] ideal_dout_out; + wire valid_i; + wire valid_out; + wire underflow_i; + + //Ideal FIFO signals. These are the raw output of the behavioral model, + //which behaves like an ideal FIFO. + reg [1:0] err_type = 0; + reg [1:0] err_type_d1 = 0; + reg [C_DOUT_WIDTH-1:0] ideal_dout; + reg [C_DOUT_WIDTH-1:0] ideal_dout_d1; + reg ideal_wr_ack; + reg ideal_valid; + reg ideal_overflow; + reg ideal_underflow; + reg ideal_full; + reg ideal_empty; + reg ideal_almost_full; + reg ideal_almost_empty; + reg ideal_prog_full; + reg ideal_prog_empty; + reg [C_WR_DATA_COUNT_WIDTH-1 : 0] ideal_wr_count; + reg [C_RD_DATA_COUNT_WIDTH-1 : 0] ideal_rd_count; + + //Assorted reg values for delayed versions of signals + reg valid_d1; + reg prog_full_d; + reg prog_empty_d; + + //Internal reset signals + reg rd_rst_asreg =0; + reg rd_rst_asreg_d1 =0; + reg rd_rst_asreg_d2 =0; + reg rd_rst_reg =0; + reg rd_rst_d1 =0; + reg wr_rst_asreg =0; + reg wr_rst_asreg_d1 =0; + reg wr_rst_asreg_d2 =0; + reg wr_rst_reg =0; + reg wr_rst_d1 =0; + + wire rd_rst_comb; + wire rd_rst_i; + wire wr_rst_comb; + wire wr_rst_i; + + + //user specified value for reseting the size of the fifo + reg [C_DOUT_WIDTH-1:0] dout_reset_val; + + //temporary registers for WR_RESPONSE_LATENCY feature + + integer tmp_wr_listsize; + integer tmp_rd_listsize; + + //Signal for registered version of prog full and empty + + //Threshold values for Programmable Flags + integer prog_empty_actual_thresh_assert; + integer prog_empty_actual_thresh_negate; + integer prog_full_actual_thresh_assert; + integer prog_full_actual_thresh_negate; + + + /**************************************************************************** + * Function Declarations + ***************************************************************************/ + + /************************************************************************** + * write_fifo + * This task writes a word to the FIFO memory and updates the + * write pointer. + * FIFO size is relative to write domain. + ***************************************************************************/ + task write_fifo; + begin + memory[wr_ptr] <= DIN; + // Store the type of error injection (double/single) on write + ecc_err[wr_ptr] <= {INJECTDBITERR,INJECTSBITERR}; + // (Works opposite to core: wr_ptr is a DOWN counter) + if (wr_ptr == 0) begin + wr_ptr <= C_WR_DEPTH - 1; + end else begin + wr_ptr <= wr_ptr - 1; + end + end + endtask // write_fifo + + /************************************************************************** + * read_fifo + * This task reads a word from the FIFO memory and updates the read + * pointer. It's output is the ideal_dout bus. + * FIFO size is relative to write domain. + ***************************************************************************/ + task read_fifo; + integer i; + reg [C_DOUT_WIDTH-1:0] tmp_dout; + reg [C_DIN_WIDTH-1:0] memory_read; + reg [31:0] tmp_rd_ptr; + reg [31:0] rd_ptr_high; + reg [31:0] rd_ptr_low; + reg [1:0] tmp_ecc_err; + begin + // output is wider than input + if (reads_per_write == 0) begin + tmp_dout = 0; + tmp_rd_ptr = (rd_ptr << log2_writes_per_read)+(writes_per_read-1); + for (i = writes_per_read - 1; i >= 0; i = i - 1) begin + tmp_dout = tmp_dout << C_DIN_WIDTH; + tmp_dout = tmp_dout | memory[tmp_rd_ptr]; + + // (Works opposite to core: rd_ptr is a DOWN counter) + if (tmp_rd_ptr == 0) begin + tmp_rd_ptr = C_WR_DEPTH - 1; + end else begin + tmp_rd_ptr = tmp_rd_ptr - 1; + end + end + + // output is symmetric + end else if (reads_per_write == 1) begin + tmp_dout = memory[rd_ptr][C_DIN_WIDTH-1:0]; + // Retreive the error injection type. Based on the error injection type + // corrupt the output data. + tmp_ecc_err = ecc_err[rd_ptr]; + if (ENABLE_ERR_INJECTION) begin + if (tmp_ecc_err[1]) begin // Corrupt the output data only for double bit error + if (C_DIN_WIDTH == 2) + tmp_dout = {~tmp_dout[C_DIN_WIDTH-1],~tmp_dout[C_DIN_WIDTH-2]}; + else + tmp_dout = {~tmp_dout[C_DIN_WIDTH-1],~tmp_dout[C_DIN_WIDTH-2],(tmp_dout << 2)}; + end else begin + tmp_dout = tmp_dout[C_DIN_WIDTH-1:0]; + end + err_type <= tmp_ecc_err; + end else begin + err_type <= 0; + end + + // input is wider than output + end else begin + rd_ptr_high = rd_ptr >> log2_reads_per_write; + rd_ptr_low = rd_ptr & (reads_per_write - 1); + memory_read = memory[rd_ptr_high]; + tmp_dout = memory_read >> (rd_ptr_low*C_DOUT_WIDTH); + end + ideal_dout <= tmp_dout; + + // (Works opposite to core: rd_ptr is a DOWN counter) + if (rd_ptr == 0) begin + rd_ptr <= C_RD_DEPTH - 1; + end else begin + rd_ptr <= rd_ptr - 1; + end + end + endtask + + /************************************************************************** + * log2_val + * Returns the 'log2' value for the input value for the supported ratios + ***************************************************************************/ + function [31:0] log2_val; + input [31:0] binary_val; + + begin + if (binary_val == 8) begin + log2_val = 3; + end else if (binary_val == 4) begin + log2_val = 2; + end else begin + log2_val = 1; + end + end + endfunction + + /*********************************************************************** + * hexstr_conv + * Converts a string of type hex to a binary value (for C_DOUT_RST_VAL) + ***********************************************************************/ + function [C_DOUT_WIDTH-1:0] hexstr_conv; + input [(C_DOUT_WIDTH*8)-1:0] def_data; + + integer index,i,j; + reg [3:0] bin; + + begin + index = 0; + hexstr_conv = 'b0; + for( i=C_DOUT_WIDTH-1; i>=0; i=i-1 ) + begin + case (def_data[7:0]) + 8'b00000000 : + begin + bin = 4'b0000; + i = -1; + end + 8'b00110000 : bin = 4'b0000; + 8'b00110001 : bin = 4'b0001; + 8'b00110010 : bin = 4'b0010; + 8'b00110011 : bin = 4'b0011; + 8'b00110100 : bin = 4'b0100; + 8'b00110101 : bin = 4'b0101; + 8'b00110110 : bin = 4'b0110; + 8'b00110111 : bin = 4'b0111; + 8'b00111000 : bin = 4'b1000; + 8'b00111001 : bin = 4'b1001; + 8'b01000001 : bin = 4'b1010; + 8'b01000010 : bin = 4'b1011; + 8'b01000011 : bin = 4'b1100; + 8'b01000100 : bin = 4'b1101; + 8'b01000101 : bin = 4'b1110; + 8'b01000110 : bin = 4'b1111; + 8'b01100001 : bin = 4'b1010; + 8'b01100010 : bin = 4'b1011; + 8'b01100011 : bin = 4'b1100; + 8'b01100100 : bin = 4'b1101; + 8'b01100101 : bin = 4'b1110; + 8'b01100110 : bin = 4'b1111; + default : + begin + bin = 4'bx; + end + endcase + for( j=0; j<4; j=j+1) + begin + if ((index*4)+j < C_DOUT_WIDTH) + begin + hexstr_conv[(index*4)+j] = bin[j]; + end + end + index = index + 1; + def_data = def_data >> 8; + end + end + endfunction + + /************************************************************************* + * Initialize Signals for clean power-on simulation + *************************************************************************/ + initial begin + num_wr_bits = 0; + num_rd_bits = 0; + next_num_wr_bits = 0; + next_num_rd_bits = 0; + rd_ptr = C_RD_DEPTH - 1; + wr_ptr = C_WR_DEPTH - 1; + rd_ptr_wrclk = rd_ptr; + wr_ptr_rdclk = wr_ptr; + dout_reset_val = hexstr_conv(C_DOUT_RST_VAL); + ideal_dout = dout_reset_val; + err_type = 0; + ideal_dout_d1 = 0 ; + ideal_wr_ack = 1'b0; + ideal_valid = 1'b0; + valid_d1 = 1'b0; + ideal_overflow = 1'b0; + ideal_underflow = 1'b0; + ideal_full = 1'b0; + ideal_empty = 1'b1; + ideal_almost_full = 1'b0; + ideal_almost_empty = 1'b1; + ideal_wr_count = 0; + ideal_rd_count = 0; + ideal_prog_full = 1'b0; + ideal_prog_empty = 1'b1; + prog_full_d = 1'b0; + prog_empty_d = 1'b1; + end + + + /************************************************************************* + * Connect the module inputs and outputs to the internal signals of the + * behavioral model. + *************************************************************************/ + //Inputs + /* + wire [C_DIN_WIDTH-1:0] DIN; + wire [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH; + wire [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_ASSERT; + wire [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_NEGATE; + wire [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH; + wire [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_ASSERT; + wire [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_NEGATE; + wire RD_CLK; + wire RD_EN; + wire RST; + wire WR_CLK; + wire WR_EN; + */ + + //Outputs + generate + if (C_HAS_ALMOST_EMPTY==1) begin : blockAE1 + assign ALMOST_EMPTY = ideal_almost_empty; + end + endgenerate + + generate + if (C_HAS_ALMOST_FULL==1) begin : blockAF1 + assign ALMOST_FULL = ideal_almost_full; + end + endgenerate + + //Dout may change behavior based on latency + assign ideal_dout_out[C_DOUT_WIDTH-1:0] = (C_PRELOAD_LATENCY==2 && + (C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1))? + ideal_dout_d1: ideal_dout; + assign DOUT[C_DOUT_WIDTH-1:0] = ideal_dout_out; + + // Assign SBITERR and DBITERR based on latency + assign SBITERR = (C_ERROR_INJECTION_TYPE == 1 || C_ERROR_INJECTION_TYPE == 3) && + (C_PRELOAD_LATENCY == 2 && + (C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1)) ? + err_type_d1[0]: err_type[0]; + assign DBITERR = (C_ERROR_INJECTION_TYPE == 2 || C_ERROR_INJECTION_TYPE == 3) && + (C_PRELOAD_LATENCY==2 && (C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1)) ? + err_type_d1[1]: err_type[1]; + + assign EMPTY = ideal_empty; + assign FULL = ideal_full; + + //Overflow may be active-low + generate + if (C_HAS_OVERFLOW==1) begin : blockOF1 + assign OVERFLOW = ideal_overflow ? !C_OVERFLOW_LOW : C_OVERFLOW_LOW; + end + endgenerate + + assign PROG_EMPTY = ideal_prog_empty; + assign PROG_FULL = ideal_prog_full; + + //Valid may change behavior based on latency or active-low + generate + if (C_HAS_VALID==1) begin : blockVL1 + assign valid_i = (C_PRELOAD_LATENCY==0) ? (RD_EN & ~EMPTY) : ideal_valid; + assign valid_out = (C_PRELOAD_LATENCY==2 && + (C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1))? + valid_d1: valid_i; + assign VALID = valid_out ? !C_VALID_LOW : C_VALID_LOW; + end + endgenerate + + generate + if (C_HAS_RD_DATA_COUNT==1) begin : blockRC1 + assign RD_DATA_COUNT[C_RD_DATA_COUNT_WIDTH-1:0] = ideal_rd_count; + end + endgenerate + + //Underflow may change behavior based on latency or active-low + generate + if (C_HAS_UNDERFLOW==1) begin : blockUF1 + assign underflow_i = (C_PRELOAD_LATENCY==0) ? (RD_EN & EMPTY) : ideal_underflow; + assign UNDERFLOW = underflow_i ? !C_UNDERFLOW_LOW : C_UNDERFLOW_LOW; + end + endgenerate + + //Write acknowledge may be active low + generate + if (C_HAS_WR_ACK==1) begin : blockWK1 + assign WR_ACK = ideal_wr_ack ? !C_WR_ACK_LOW : C_WR_ACK_LOW; + end + endgenerate + + generate + if (C_HAS_WR_DATA_COUNT==1) begin : blockWC1 + assign WR_DATA_COUNT[C_WR_DATA_COUNT_WIDTH-1:0] = ideal_wr_count; + end + endgenerate + + /************************************************************************** + * Internal reset logic + **************************************************************************/ + assign wr_rst_i = (C_HAS_RST == 1 || C_ENABLE_RST_SYNC == 0) ? wr_rst_reg : 0; + assign rd_rst_i = (C_HAS_RST == 1 || C_ENABLE_RST_SYNC == 0) ? rd_rst_reg : 0; + + generate + if (C_ENABLE_RST_SYNC == 0) begin : gnrst_sync + always @* begin + wr_rst_reg <= WR_RST; + rd_rst_reg <= RD_RST; + end + end else if (C_HAS_RST==1) begin : blockRST2 + assign wr_rst_comb = !wr_rst_asreg_d2 && wr_rst_asreg; + assign rd_rst_comb = !rd_rst_asreg_d2 && rd_rst_asreg; + + always @(posedge WR_CLK or posedge RST) begin + if (RST == 1'b1) begin + wr_rst_asreg <= #`TCQ 1'b1; + end else begin + if (wr_rst_asreg_d1 == 1'b1) begin + wr_rst_asreg <= #`TCQ 1'b0; + end else begin + wr_rst_asreg <= #`TCQ wr_rst_asreg; + end + end + end + + always @(posedge WR_CLK) begin + wr_rst_asreg_d1 <= #`TCQ wr_rst_asreg; + wr_rst_asreg_d2 <= #`TCQ wr_rst_asreg_d1; + end + + always @(posedge WR_CLK or posedge wr_rst_comb) begin + if (wr_rst_comb == 1'b1) begin + wr_rst_reg <= #`TCQ 1'b1; + end else begin + wr_rst_reg <= #`TCQ 1'b0; + end + end + + always @(posedge WR_CLK or posedge wr_rst_i) begin + if (wr_rst_i == 1'b1) begin + wr_rst_d1 <= #`TCQ 1'b1; + end else begin + wr_rst_d1 <= #`TCQ wr_rst_i; + end + end + + always @(posedge RD_CLK or posedge RST) begin + if (RST == 1'b1) begin + rd_rst_asreg <= #`TCQ 1'b1; + end else begin + if (rd_rst_asreg_d1 == 1'b1) begin + rd_rst_asreg <= #`TCQ 1'b0; + end else begin + rd_rst_asreg <= #`TCQ rd_rst_asreg; + end + end + end + + always @(posedge RD_CLK) begin + rd_rst_asreg_d1 <= #`TCQ rd_rst_asreg; + rd_rst_asreg_d2 <= #`TCQ rd_rst_asreg_d1; + end + + always @(posedge RD_CLK or posedge rd_rst_comb) begin + if (rd_rst_comb == 1'b1) begin + rd_rst_reg <= #`TCQ 1'b1; + end else begin + rd_rst_reg <= #`TCQ 1'b0; + end + end + end + endgenerate + + /************************************************************************** + * Assorted registers for delayed versions of signals + **************************************************************************/ + //Capture delayed version of valid + generate + if (C_HAS_VALID==1) begin : blockVL2 + always @(posedge RD_CLK or posedge rd_rst_i) begin + if (rd_rst_i == 1'b1) begin + valid_d1 <= #`TCQ 1'b0; + end else begin + valid_d1 <= #`TCQ valid_i; + end + end + end + endgenerate + + //Capture delayed version of dout + always @(posedge RD_CLK or posedge rd_rst_i) begin + if (rd_rst_i == 1'b1) begin + err_type_d1 <= #`TCQ 0; + if (C_USE_DOUT_RST == 1) + ideal_dout_d1 <= #`TCQ dout_reset_val; + end else begin + ideal_dout_d1 <= #`TCQ ideal_dout; + err_type_d1 <= #`TCQ err_type; + end + end + + /************************************************************************** + * Overflow and Underflow Flag calculation + * (handled separately because they don't support rst) + **************************************************************************/ + generate + if (C_HAS_OVERFLOW==1) begin : blockOF2 + always @(posedge WR_CLK) begin + ideal_overflow <= #`TCQ WR_EN & ideal_full; + end + end + endgenerate + + generate + if (C_HAS_UNDERFLOW==1) begin : blockUF2 + always @(posedge RD_CLK) begin + ideal_underflow <= #`TCQ ideal_empty & RD_EN; + end + end + endgenerate + + /************************************************************************** + * Write Domain Logic + **************************************************************************/ + always @(posedge WR_CLK or posedge wr_rst_i) begin : gen_fifo_w + + /****** Reset fifo (case 1)***************************************/ + if (wr_rst_i == 1'b1) begin + num_wr_bits <= #`TCQ 0; + next_num_wr_bits = #`TCQ 0; + wr_ptr <= #`TCQ C_WR_DEPTH - 1; + rd_ptr_wrclk <= #`TCQ C_RD_DEPTH - 1; + ideal_wr_ack <= #`TCQ 0; + ideal_full <= #`TCQ C_FULL_FLAGS_RST_VAL; + ideal_almost_full <= #`TCQ C_FULL_FLAGS_RST_VAL; + ideal_wr_count <= #`TCQ 0; + tmp_wr_listsize = #`TCQ 0; + rd_ptr_wrclk_next <= #`TCQ 0; + + ideal_prog_full <= #`TCQ C_FULL_FLAGS_RST_VAL; + prog_full_d <= #`TCQ C_FULL_FLAGS_RST_VAL; + + end else begin //wr_rst_i==0 + + //Determine the current number of words in the FIFO + tmp_wr_listsize = (C_DEPTH_RATIO_RD > 1) ? num_wr_bits/C_DOUT_WIDTH : + num_wr_bits/C_DIN_WIDTH; + rd_ptr_wrclk_next = rd_ptr; + if (rd_ptr_wrclk < rd_ptr_wrclk_next) begin + next_num_wr_bits = num_wr_bits - + C_DOUT_WIDTH*(rd_ptr_wrclk + C_RD_DEPTH + - rd_ptr_wrclk_next); + end else begin + next_num_wr_bits = num_wr_bits - + C_DOUT_WIDTH*(rd_ptr_wrclk - rd_ptr_wrclk_next); + end + + //If this is a write, handle the write by adding the value + // to the linked list, and updating all outputs appropriately + if (WR_EN == 1'b1) begin + if (ideal_full == 1'b1) begin + + //If the FIFO is full, do NOT perform the write, + // update flags accordingly + if ((tmp_wr_listsize + C_DEPTH_RATIO_RD - 1)/C_DEPTH_RATIO_RD + >= C_FIFO_WR_DEPTH) begin + //write unsuccessful - do not change contents + + //Do not acknowledge the write + ideal_wr_ack <= #`TCQ 0; + //Reminder that FIFO is still full + ideal_full <= #`TCQ 1'b1; + ideal_almost_full <= #`TCQ 1'b1; + + ideal_wr_count <= #`TCQ num_write_words_sized_i; + + //If the FIFO is one from full, but reporting full + end else + if ((tmp_wr_listsize + C_DEPTH_RATIO_RD - 1)/C_DEPTH_RATIO_RD == + C_FIFO_WR_DEPTH-1) begin + //No change to FIFO + + //Write not successful + ideal_wr_ack <= #`TCQ 0; + //With DEPTH-1 words in the FIFO, it is almost_full + ideal_full <= #`TCQ 1'b0; + ideal_almost_full <= #`TCQ 1'b1; + + ideal_wr_count <= #`TCQ num_write_words_sized_i; + + + //If the FIFO is completely empty, but it is + // reporting FULL for some reason (like reset) + end else + if ((tmp_wr_listsize + C_DEPTH_RATIO_RD - 1)/C_DEPTH_RATIO_RD <= + C_FIFO_WR_DEPTH-2) begin + //No change to FIFO + + //Write not successful + ideal_wr_ack <= #`TCQ 0; + //FIFO is really not close to full, so change flag status. + ideal_full <= #`TCQ 1'b0; + ideal_almost_full <= #`TCQ 1'b0; + + ideal_wr_count <= #`TCQ num_write_words_sized_i; + end //(tmp_wr_listsize == 0) + + end else begin + + //If the FIFO is full, do NOT perform the write, + // update flags accordingly + if ((tmp_wr_listsize + C_DEPTH_RATIO_RD - 1)/C_DEPTH_RATIO_RD >= + C_FIFO_WR_DEPTH) begin + //write unsuccessful - do not change contents + + //Do not acknowledge the write + ideal_wr_ack <= #`TCQ 0; + //Reminder that FIFO is still full + ideal_full <= #`TCQ 1'b1; + ideal_almost_full <= #`TCQ 1'b1; + + ideal_wr_count <= #`TCQ num_write_words_sized_i; + + //If the FIFO is one from full + end else + if ((tmp_wr_listsize + C_DEPTH_RATIO_RD - 1)/C_DEPTH_RATIO_RD == + C_FIFO_WR_DEPTH-1) begin + //Add value on DIN port to FIFO + write_fifo; + next_num_wr_bits = next_num_wr_bits + C_DIN_WIDTH; + + //Write successful, so issue acknowledge + // and no error + ideal_wr_ack <= #`TCQ 1; + //This write is CAUSING the FIFO to go full + ideal_full <= #`TCQ 1'b1; + ideal_almost_full <= #`TCQ 1'b1; + + ideal_wr_count <= #`TCQ num_write_words_sized_i; + + //If the FIFO is 2 from full + end else + if ((tmp_wr_listsize + C_DEPTH_RATIO_RD - 1)/C_DEPTH_RATIO_RD == + C_FIFO_WR_DEPTH-2) begin + //Add value on DIN port to FIFO + write_fifo; + next_num_wr_bits = next_num_wr_bits + C_DIN_WIDTH; + //Write successful, so issue acknowledge + // and no error + ideal_wr_ack <= #`TCQ 1; + //Still 2 from full + ideal_full <= #`TCQ 1'b0; + //2 from full, and writing, so set almost_full + ideal_almost_full <= #`TCQ 1'b1; + + ideal_wr_count <= #`TCQ num_write_words_sized_i; + + //If the FIFO is not close to being full + end else + if ((tmp_wr_listsize + C_DEPTH_RATIO_RD - 1)/C_DEPTH_RATIO_RD < + C_FIFO_WR_DEPTH-2) begin + //Add value on DIN port to FIFO + write_fifo; + next_num_wr_bits = next_num_wr_bits + C_DIN_WIDTH; + //Write successful, so issue acknowledge + // and no error + ideal_wr_ack <= #`TCQ 1; + //Not even close to full. + ideal_full <= #`TCQ 1'b0; + ideal_almost_full <= #`TCQ 1'b0; + + ideal_wr_count <= num_write_words_sized_i; + + end + + end + + end else begin //(WR_EN == 1'b1) + + //If user did not attempt a write, then do not + // give ack or err + ideal_wr_ack <= #`TCQ 0; + + //Implied statements: + //ideal_empty <= ideal_empty; + //ideal_almost_empty <= ideal_almost_empty; + + //Check for full + if ((tmp_wr_listsize + C_DEPTH_RATIO_RD - 1)/C_DEPTH_RATIO_RD >= C_FIFO_WR_DEPTH) + ideal_full <= #`TCQ 1'b1; + else + ideal_full <= #`TCQ 1'b0; + + //Check for almost_full + if ((tmp_wr_listsize + C_DEPTH_RATIO_RD - 1)/C_DEPTH_RATIO_RD >= C_FIFO_WR_DEPTH-1) + ideal_almost_full <= #`TCQ 1'b1; + else + ideal_almost_full <= #`TCQ 1'b0; + + ideal_wr_count <= #`TCQ num_write_words_sized_i; + end + + /********************************************************* + * Programmable FULL flags + *********************************************************/ + //Single Programmable Full Constant Threshold + if (C_PROG_FULL_TYPE==1) begin + if (C_PRELOAD_REGS==1 && C_PRELOAD_LATENCY==0) begin + prog_full_actual_thresh_assert = C_PROG_FULL_THRESH_ASSERT_VAL-EXTRA_WORDS; + prog_full_actual_thresh_negate = C_PROG_FULL_THRESH_ASSERT_VAL-EXTRA_WORDS; + end else begin + prog_full_actual_thresh_assert = C_PROG_FULL_THRESH_ASSERT_VAL; + prog_full_actual_thresh_negate = C_PROG_FULL_THRESH_ASSERT_VAL; + end + + //Two Programmable Full Constant Thresholds + end else if (C_PROG_FULL_TYPE==2) begin + if (C_PRELOAD_REGS==1 && C_PRELOAD_LATENCY==0) begin + prog_full_actual_thresh_assert = C_PROG_FULL_THRESH_ASSERT_VAL-EXTRA_WORDS; + prog_full_actual_thresh_negate = C_PROG_FULL_THRESH_NEGATE_VAL-EXTRA_WORDS; + end else begin + prog_full_actual_thresh_assert = C_PROG_FULL_THRESH_ASSERT_VAL; + prog_full_actual_thresh_negate = C_PROG_FULL_THRESH_NEGATE_VAL; + end + + //Single Programmable Full Threshold Input + end else if (C_PROG_FULL_TYPE==3) begin + if (C_PRELOAD_REGS==1 && C_PRELOAD_LATENCY==0) begin + prog_full_actual_thresh_assert = PROG_FULL_THRESH-EXTRA_WORDS; + prog_full_actual_thresh_negate = PROG_FULL_THRESH-EXTRA_WORDS; + end else begin + prog_full_actual_thresh_assert = PROG_FULL_THRESH; + prog_full_actual_thresh_negate = PROG_FULL_THRESH; + end + + //Two Programmable Full Threshold Inputs + end else if (C_PROG_FULL_TYPE==4) begin + if (C_PRELOAD_REGS==1 && C_PRELOAD_LATENCY==0) begin + prog_full_actual_thresh_assert = PROG_FULL_THRESH_ASSERT-EXTRA_WORDS; + prog_full_actual_thresh_negate = PROG_FULL_THRESH_NEGATE-EXTRA_WORDS; + end else begin + prog_full_actual_thresh_assert = PROG_FULL_THRESH_ASSERT; + prog_full_actual_thresh_negate = PROG_FULL_THRESH_NEGATE; + end + end //C_PROG_FULL_TYPE + + if (num_write_words_pf==0) begin + prog_full_d <= #`TCQ 1'b0; + end else begin + if (((1+(num_write_words_pf-1)/C_DEPTH_RATIO_RD) + == prog_full_actual_thresh_assert-1) && WR_EN) begin + prog_full_d <= #`TCQ 1'b1; + end else if ((1+(num_write_words_pf-1)/C_DEPTH_RATIO_RD) + >= prog_full_actual_thresh_assert) begin + prog_full_d <= #`TCQ 1'b1; + end else if ((1+(num_write_words_pf-1)/C_DEPTH_RATIO_RD) + < prog_full_actual_thresh_negate) begin + prog_full_d <= #`TCQ 1'b0; + end + end + + if (wr_rst_d1==1 && wr_rst_i==0) begin + ideal_prog_full <= #`TCQ 0; + end else begin + ideal_prog_full <= #`TCQ prog_full_d; + end + num_wr_bits <= #`TCQ next_num_wr_bits; + rd_ptr_wrclk <= #`TCQ rd_ptr; + + end //wr_rst_i==0 + end // write always + + + /************************************************************************** + * Read Domain Logic + **************************************************************************/ + always @(posedge RD_CLK or posedge rd_rst_i) begin : gen_fifo_r + + /****** Reset fifo (case 1)***************************************/ + if (rd_rst_i) begin + num_rd_bits <= #`TCQ 0; + next_num_rd_bits = #`TCQ 0; + rd_ptr <= #`TCQ C_RD_DEPTH -1; + wr_ptr_rdclk <= #`TCQ C_WR_DEPTH -1; + if (C_USE_DOUT_RST == 1) begin + ideal_dout <= #`TCQ dout_reset_val; + end else begin + ideal_dout <= #`TCQ ideal_dout; + end + err_type <= #`TCQ 1'b0; + ideal_valid <= #`TCQ 1'b0; + ideal_empty <= #`TCQ 1'b1; + ideal_almost_empty <= #`TCQ 1'b1; + ideal_rd_count <= #`TCQ 0; + ideal_prog_empty <= #`TCQ 1'b1; + prog_empty_d <= #`TCQ 1; + + + end else begin //rd_rst_i==0 + + //Determine the current number of words in the FIFO + tmp_rd_listsize = (C_DEPTH_RATIO_WR > 1) ? num_rd_bits/C_DIN_WIDTH : + num_rd_bits/C_DOUT_WIDTH; + wr_ptr_rdclk_next = wr_ptr; + + if (wr_ptr_rdclk < wr_ptr_rdclk_next) begin + next_num_rd_bits = num_rd_bits + + C_DIN_WIDTH*(wr_ptr_rdclk +C_WR_DEPTH + - wr_ptr_rdclk_next); + end else begin + next_num_rd_bits = num_rd_bits + + C_DIN_WIDTH*(wr_ptr_rdclk - wr_ptr_rdclk_next); + end + + /*****************************************************************/ + // Read Operation - Read Latency 1 + /*****************************************************************/ + if (C_PRELOAD_LATENCY==1 || C_PRELOAD_LATENCY==2) begin + + if (RD_EN == 1'b1) begin + + if (ideal_empty == 1'b1) begin + + //If the FIFO is completely empty, and is reporting empty + if (tmp_rd_listsize/C_DEPTH_RATIO_WR <= 0) + begin + //Do not change the contents of the FIFO + + //Do not acknowledge the read from empty FIFO + ideal_valid <= #`TCQ 1'b0; + //Reminder that FIFO is still empty + ideal_empty <= #`TCQ 1'b1; + ideal_almost_empty <= #`TCQ 1'b1; + + ideal_rd_count <= #`TCQ num_read_words_sized_i; + end // if (tmp_rd_listsize <= 0) + + //If the FIFO is one from empty, but it is reporting empty + else if (tmp_rd_listsize/C_DEPTH_RATIO_WR == 1) + begin + //Do not change the contents of the FIFO + + //Do not acknowledge the read from empty FIFO + ideal_valid <= #`TCQ 1'b0; + //Note that FIFO is no longer empty, but is almost empty (has one word left) + ideal_empty <= #`TCQ 1'b0; + ideal_almost_empty <= #`TCQ 1'b1; + + ideal_rd_count <= #`TCQ num_read_words_sized_i; + + end // if (tmp_rd_listsize == 1) + + //If the FIFO is two from empty, and is reporting empty + else if (tmp_rd_listsize/C_DEPTH_RATIO_WR == 2) + begin + //Do not change the contents of the FIFO + + //Do not acknowledge the read from empty FIFO + ideal_valid <= #`TCQ 1'b0; + //Fifo has two words, so is neither empty or almost empty + ideal_empty <= #`TCQ 1'b0; + ideal_almost_empty <= #`TCQ 1'b0; + + ideal_rd_count <= #`TCQ num_read_words_sized_i; + + end // if (tmp_rd_listsize == 2) + + //If the FIFO is not close to empty, but is reporting that it is + // Treat the FIFO as empty this time, but unset EMPTY flags. + if ((tmp_rd_listsize/C_DEPTH_RATIO_WR > 2) && (tmp_rd_listsize/C_DEPTH_RATIO_WR 2) && (tmp_rd_listsize<=C_FIFO_RD_DEPTH-1)) + end // else: if(ideal_empty == 1'b1) + + else //if (ideal_empty == 1'b0) + begin + + //If the FIFO is completely full, and we are successfully reading from it + if (tmp_rd_listsize/C_DEPTH_RATIO_WR >= C_FIFO_RD_DEPTH) + begin + //Read the value from the FIFO + read_fifo; + next_num_rd_bits = next_num_rd_bits - C_DOUT_WIDTH; + + //Acknowledge the read from the FIFO, no error + ideal_valid <= #`TCQ 1'b1; + //Not close to empty + ideal_empty <= #`TCQ 1'b0; + ideal_almost_empty <= #`TCQ 1'b0; + + ideal_rd_count <= #`TCQ num_read_words_sized_i; + + end // if (tmp_rd_listsize == C_FIFO_RD_DEPTH) + + //If the FIFO is not close to being empty + else if ((tmp_rd_listsize/C_DEPTH_RATIO_WR > 2) && (tmp_rd_listsize/C_DEPTH_RATIO_WR<=C_FIFO_RD_DEPTH)) + begin + //Read the value from the FIFO + read_fifo; + next_num_rd_bits = next_num_rd_bits - C_DOUT_WIDTH; + + //Acknowledge the read from the FIFO, no error + ideal_valid <= #`TCQ 1'b1; + //Not close to empty + ideal_empty <= #`TCQ 1'b0; + ideal_almost_empty <= #`TCQ 1'b0; + + ideal_rd_count <= #`TCQ num_read_words_sized_i; + + end // if ((tmp_rd_listsize > 2) && (tmp_rd_listsize<=C_FIFO_RD_DEPTH-1)) + + //If the FIFO is two from empty + else if (tmp_rd_listsize/C_DEPTH_RATIO_WR == 2) + begin + //Read the value from the FIFO + read_fifo; + next_num_rd_bits = next_num_rd_bits - C_DOUT_WIDTH; + + //Acknowledge the read from the FIFO, no error + ideal_valid <= #`TCQ 1'b1; + //Fifo is not yet empty. It is going almost_empty + ideal_empty <= #`TCQ 1'b0; + ideal_almost_empty <= #`TCQ 1'b1; + + ideal_rd_count <= #`TCQ num_read_words_sized_i; + + end // if (tmp_rd_listsize == 2) + + //If the FIFO is one from empty + else if ((tmp_rd_listsize/C_DEPTH_RATIO_WR == 1)) + begin + //Read the value from the FIFO + read_fifo; + next_num_rd_bits = next_num_rd_bits - C_DOUT_WIDTH; + + //Acknowledge the read from the FIFO, no error + ideal_valid <= #`TCQ 1'b1; + //Note that FIFO is GOING empty + ideal_empty <= #`TCQ 1'b1; + ideal_almost_empty <= #`TCQ 1'b1; + + ideal_rd_count <= #`TCQ num_read_words_sized_i; + + end // if (tmp_rd_listsize == 1) + + + //If the FIFO is completely empty + else if (tmp_rd_listsize/C_DEPTH_RATIO_WR <= 0) + begin + //Do not change the contents of the FIFO + + //Do not acknowledge the read from empty FIFO + ideal_valid <= #`TCQ 1'b0; + //Reminder that FIFO is still empty + ideal_empty <= #`TCQ 1'b1; + ideal_almost_empty <= #`TCQ 1'b1; + + ideal_rd_count <= #`TCQ num_read_words_sized_i; + + end // if (tmp_rd_listsize <= 0) + + end // if (ideal_empty == 1'b0) + + end //(RD_EN == 1'b1) + + else //if (RD_EN == 1'b0) + begin + //If user did not attempt a read, do not give an ack or err + ideal_valid <= #`TCQ 1'b0; + + //Check for empty + if (tmp_rd_listsize/C_DEPTH_RATIO_WR <= 0) + ideal_empty <= #`TCQ 1'b1; + else + ideal_empty <= #`TCQ 1'b0; + + //Check for almost_empty + if (tmp_rd_listsize/C_DEPTH_RATIO_WR <= 1) + ideal_almost_empty <= #`TCQ 1'b1; + else + ideal_almost_empty <= #`TCQ 1'b0; + + ideal_rd_count <= #`TCQ num_read_words_sized_i; + + end // else: !if(RD_EN == 1'b1) + + /*****************************************************************/ + // Read Operation - Read Latency 0 + /*****************************************************************/ + end else if (C_PRELOAD_REGS==1 && C_PRELOAD_LATENCY==0) begin + if (RD_EN == 1'b1) begin + + if (ideal_empty == 1'b1) begin + + //If the FIFO is completely empty, and is reporting empty + if (tmp_rd_listsize/C_DEPTH_RATIO_WR <= 0) begin + //Do not change the contents of the FIFO + + //Do not acknowledge the read from empty FIFO + ideal_valid <= #`TCQ 1'b0; + //Reminder that FIFO is still empty + ideal_empty <= #`TCQ 1'b1; + ideal_almost_empty <= #`TCQ 1'b1; + + ideal_rd_count <= #`TCQ num_read_words_sized_i; + + //If the FIFO is one from empty, but it is reporting empty + end else if (tmp_rd_listsize/C_DEPTH_RATIO_WR == 1) begin + //Do not change the contents of the FIFO + + //Do not acknowledge the read from empty FIFO + ideal_valid <= #`TCQ 1'b0; + //Note that FIFO is no longer empty, but is almost empty (has one word left) + ideal_empty <= #`TCQ 1'b0; + ideal_almost_empty <= #`TCQ 1'b1; + + ideal_rd_count <= #`TCQ num_read_words_sized_i; + + //If the FIFO is two from empty, and is reporting empty + end else if (tmp_rd_listsize/C_DEPTH_RATIO_WR == 2) begin + //Do not change the contents of the FIFO + + //Do not acknowledge the read from empty FIFO + ideal_valid <= #`TCQ 1'b0; + //Fifo has two words, so is neither empty or almost empty + ideal_empty <= #`TCQ 1'b0; + ideal_almost_empty <= #`TCQ 1'b0; + + ideal_rd_count <= #`TCQ num_read_words_sized_i; + + //If the FIFO is not close to empty, but is reporting that it is + // Treat the FIFO as empty this time, but unset EMPTY flags. + end else if ((tmp_rd_listsize/C_DEPTH_RATIO_WR > 2) && + (tmp_rd_listsize/C_DEPTH_RATIO_WR 2) && (tmp_rd_listsize<=C_FIFO_RD_DEPTH-1)) + + end else begin + + //If the FIFO is completely full, and we are successfully reading from it + if (tmp_rd_listsize/C_DEPTH_RATIO_WR >= C_FIFO_RD_DEPTH) begin + //Read the value from the FIFO + read_fifo; + next_num_rd_bits = next_num_rd_bits - C_DOUT_WIDTH; + + //Acknowledge the read from the FIFO, no error + ideal_valid <= #`TCQ 1'b1; + //Not close to empty + ideal_empty <= #`TCQ 1'b0; + ideal_almost_empty <= #`TCQ 1'b0; + + ideal_rd_count <= #`TCQ num_read_words_sized_i; + + //If the FIFO is not close to being empty + end else if ((tmp_rd_listsize/C_DEPTH_RATIO_WR > 2) && + (tmp_rd_listsize/C_DEPTH_RATIO_WR<=C_FIFO_RD_DEPTH)) begin + //Read the value from the FIFO + read_fifo; + next_num_rd_bits = next_num_rd_bits - C_DOUT_WIDTH; + + //Acknowledge the read from the FIFO, no error + ideal_valid <= #`TCQ 1'b1; + //Not close to empty + ideal_empty <= #`TCQ 1'b0; + ideal_almost_empty <= #`TCQ 1'b0; + + ideal_rd_count <= #`TCQ num_read_words_sized_i; + + //If the FIFO is two from empty + end else if (tmp_rd_listsize/C_DEPTH_RATIO_WR == 2) begin + //Read the value from the FIFO + read_fifo; + next_num_rd_bits = next_num_rd_bits - C_DOUT_WIDTH; + + //Acknowledge the read from the FIFO, no error + ideal_valid <= #`TCQ 1'b1; + //Fifo is not yet empty. It is going almost_empty + ideal_empty <= #`TCQ 1'b0; + ideal_almost_empty <= #`TCQ 1'b1; + + ideal_rd_count <= #`TCQ num_read_words_sized_i; + + //If the FIFO is one from empty + end else if (tmp_rd_listsize/C_DEPTH_RATIO_WR == 1) begin + //Read the value from the FIFO + read_fifo; + next_num_rd_bits = next_num_rd_bits - C_DOUT_WIDTH; + + //Acknowledge the read from the FIFO, no error + ideal_valid <= #`TCQ 1'b1; + //Note that FIFO is GOING empty + ideal_empty <= #`TCQ 1'b1; + ideal_almost_empty <= #`TCQ 1'b1; + + ideal_rd_count <= #`TCQ num_read_words_sized_i; + + //If the FIFO is completely empty + end else if (tmp_rd_listsize/C_DEPTH_RATIO_WR <= 0) begin + //Do not change the contents of the FIFO + + //Do not acknowledge the read from empty FIFO + ideal_valid <= #`TCQ 1'b0; + //Reminder that FIFO is still empty + ideal_empty <= #`TCQ 1'b1; + ideal_almost_empty <= #`TCQ 1'b1; + + ideal_rd_count <= #`TCQ num_read_words_sized_i; + + end // if (tmp_rd_listsize <= 0) + + end // if (ideal_empty == 1'b0) + + end else begin//(RD_EN == 1'b0) + + + //If user did not attempt a read, do not give an ack or err + ideal_valid <= #`TCQ 1'b0; + + //Check for empty + if (tmp_rd_listsize/C_DEPTH_RATIO_WR <= 0) + ideal_empty <= #`TCQ 1'b1; + else + ideal_empty <= #`TCQ 1'b0; + + //Check for almost_empty + if (tmp_rd_listsize/C_DEPTH_RATIO_WR <= 1) + ideal_almost_empty <= #`TCQ 1'b1; + else + ideal_almost_empty <= #`TCQ 1'b0; + + ideal_rd_count <= #`TCQ num_read_words_sized_i; + + end // else: !if(RD_EN == 1'b1) + end //if (C_PRELOAD_REGS==1 && C_PRELOAD_LATENCY==0) + + + /********************************************************* + * Programmable EMPTY flags + *********************************************************/ + //Determine the Assert and Negate thresholds for Programmable Empty + // (Subtract 2 read-sized words when using Preload 0) + + //Single Programmable Empty Constant Threshold + if (C_PROG_EMPTY_TYPE==1) begin + if (C_PRELOAD_REGS==1 && C_PRELOAD_LATENCY==0) begin + prog_empty_actual_thresh_assert = C_PROG_EMPTY_THRESH_ASSERT_VAL-2; + prog_empty_actual_thresh_negate = C_PROG_EMPTY_THRESH_ASSERT_VAL-2; + end + else begin + prog_empty_actual_thresh_assert = C_PROG_EMPTY_THRESH_ASSERT_VAL; + prog_empty_actual_thresh_negate = C_PROG_EMPTY_THRESH_ASSERT_VAL; + end + + //Two Programmable Empty Constant Thresholds + end else if (C_PROG_EMPTY_TYPE==2) begin + if (C_PRELOAD_REGS==1 && C_PRELOAD_LATENCY==0) begin + prog_empty_actual_thresh_assert = C_PROG_EMPTY_THRESH_ASSERT_VAL-2; + prog_empty_actual_thresh_negate = C_PROG_EMPTY_THRESH_NEGATE_VAL-2; + end + else begin + prog_empty_actual_thresh_assert = C_PROG_EMPTY_THRESH_ASSERT_VAL; + prog_empty_actual_thresh_negate = C_PROG_EMPTY_THRESH_NEGATE_VAL; + end + + //Single Programmable Empty Constant Threshold + end else if (C_PROG_EMPTY_TYPE==3) begin + if (C_PRELOAD_REGS==1 && C_PRELOAD_LATENCY==0) begin + prog_empty_actual_thresh_assert = PROG_EMPTY_THRESH-2; + prog_empty_actual_thresh_negate = PROG_EMPTY_THRESH-2; + end + else begin + prog_empty_actual_thresh_assert = PROG_EMPTY_THRESH; + prog_empty_actual_thresh_negate = PROG_EMPTY_THRESH; + + end + //Two Programmable Empty Constant Thresholds + end else if (C_PROG_EMPTY_TYPE==4) begin + if (C_PRELOAD_REGS==1 && C_PRELOAD_LATENCY==0) begin + prog_empty_actual_thresh_assert = PROG_EMPTY_THRESH_ASSERT-2; + prog_empty_actual_thresh_negate = PROG_EMPTY_THRESH_NEGATE-2; + end + else begin + prog_empty_actual_thresh_assert = PROG_EMPTY_THRESH_ASSERT; + prog_empty_actual_thresh_negate = PROG_EMPTY_THRESH_NEGATE; + end + end + + if ((num_read_words_pe/C_DEPTH_RATIO_WR == prog_empty_actual_thresh_assert+1) + && RD_EN) begin + prog_empty_d <= #`TCQ 1'b1; + end else if (num_read_words_pe/C_DEPTH_RATIO_WR + <= prog_empty_actual_thresh_assert) begin + prog_empty_d <= #`TCQ 1'b1; + end else if (num_read_words_pe/C_DEPTH_RATIO_WR + > prog_empty_actual_thresh_negate) begin + prog_empty_d <= #`TCQ 1'b0; + end + + + ideal_prog_empty <= #`TCQ prog_empty_d; + num_rd_bits <= #`TCQ next_num_rd_bits; + wr_ptr_rdclk <= #`TCQ wr_ptr; + end //rd_rst_i==0 + end //always + +endmodule // fifo_generator_v5_1_bhv_ver_as + + +/******************************************************************************* + * Declaration of top-level module + ******************************************************************************/ +module fifo_generator_v5_1_bhv_ver_ss + ( + CLK, RST, SRST, DIN, WR_EN, RD_EN, + PROG_FULL_THRESH, PROG_FULL_THRESH_ASSERT, PROG_FULL_THRESH_NEGATE, + PROG_EMPTY_THRESH, PROG_EMPTY_THRESH_ASSERT, PROG_EMPTY_THRESH_NEGATE, + INJECTSBITERR, INJECTDBITERR, DOUT, FULL, ALMOST_FULL, WR_ACK, OVERFLOW, + EMPTY, ALMOST_EMPTY, VALID, UNDERFLOW, DATA_COUNT, + PROG_FULL, PROG_EMPTY, SBITERR, DBITERR + ); + + /************************************************************************** + * Declare user parameters and their defaults + *************************************************************************/ + parameter C_DATA_COUNT_WIDTH = 2; + parameter C_DIN_WIDTH = 8; + parameter C_DOUT_RST_VAL = ""; + parameter C_DOUT_WIDTH = 8; + parameter C_FULL_FLAGS_RST_VAL = 1; + parameter C_HAS_ALMOST_EMPTY = 0; + parameter C_HAS_ALMOST_FULL = 0; + parameter C_HAS_DATA_COUNT = 0; + parameter C_HAS_OVERFLOW = 0; + parameter C_HAS_RD_DATA_COUNT = 0; + parameter C_HAS_RST = 0; + parameter C_HAS_SRST = 0; + parameter C_HAS_UNDERFLOW = 0; + parameter C_HAS_VALID = 0; + parameter C_HAS_WR_ACK = 0; + parameter C_HAS_WR_DATA_COUNT = 0; + parameter C_IMPLEMENTATION_TYPE = 0; + parameter C_MEMORY_TYPE = 1; + parameter C_OVERFLOW_LOW = 0; + parameter C_PRELOAD_LATENCY = 1; + parameter C_PRELOAD_REGS = 0; + parameter C_PROG_EMPTY_THRESH_ASSERT_VAL = 0; + parameter C_PROG_EMPTY_THRESH_NEGATE_VAL = 0; + parameter C_PROG_EMPTY_TYPE = 0; + parameter C_PROG_FULL_THRESH_ASSERT_VAL = 0; + parameter C_PROG_FULL_THRESH_NEGATE_VAL = 0; + parameter C_PROG_FULL_TYPE = 0; + parameter C_RD_DATA_COUNT_WIDTH = 2; + parameter C_RD_DEPTH = 256; + parameter C_RD_PNTR_WIDTH = 8; + parameter C_UNDERFLOW_LOW = 0; + parameter C_USE_DOUT_RST = 0; + parameter C_USE_EMBEDDED_REG = 0; + parameter C_USE_FWFT_DATA_COUNT = 0; + parameter C_VALID_LOW = 0; + parameter C_WR_ACK_LOW = 0; + parameter C_WR_DATA_COUNT_WIDTH = 2; + parameter C_WR_DEPTH = 256; + parameter C_WR_PNTR_WIDTH = 8; + parameter C_USE_ECC = 0; + parameter C_ENABLE_RST_SYNC = 1; + parameter C_ERROR_INJECTION_TYPE = 0; + + + /************************************************************************** + * Declare Input and Output Ports + *************************************************************************/ + //Inputs + input CLK; + input [C_DIN_WIDTH-1:0] DIN; + input [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH; + input [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_ASSERT; + input [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_NEGATE; + input [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH; + input [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_ASSERT; + input [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_NEGATE; + input RD_EN; + input RST; + input SRST; + input WR_EN; + input INJECTDBITERR; + input INJECTSBITERR; + + //Outputs + output ALMOST_EMPTY; + output ALMOST_FULL; + output [C_DATA_COUNT_WIDTH-1:0] DATA_COUNT; + output [C_DOUT_WIDTH-1:0] DOUT; + output EMPTY; + output FULL; + output OVERFLOW; + output PROG_EMPTY; + output PROG_FULL; + output VALID; + output UNDERFLOW; + output WR_ACK; + output SBITERR; + output DBITERR; + + /************************************************************************* + * Declare the type for each Input/Output port, and connect each I/O + * to it's associated internal signal in the behavioral model + * + * The values for the outputs are assigned in assign statements immediately + * following wire, parameter, and function declarations in this code. + *************************************************************************/ + //Inputs + wire CLK; + wire [C_DIN_WIDTH-1:0] DIN; + wire [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH; + wire [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_ASSERT; + wire [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_NEGATE; + wire [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH; + wire [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_ASSERT; + wire [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_NEGATE; + wire RD_EN; + wire RST; + wire SRST; + wire WR_EN; + wire INJECTSBITERR; + wire INJECTDBITERR; + + //Outputs + wire ALMOST_EMPTY; + wire ALMOST_FULL; + reg [C_DATA_COUNT_WIDTH-1:0] DATA_COUNT; + wire [C_DOUT_WIDTH-1:0] DOUT; + wire EMPTY; + wire FULL; + wire OVERFLOW; + wire PROG_EMPTY; + wire PROG_FULL; + wire VALID; + wire UNDERFLOW; + wire WR_ACK; + wire SBITERR; + wire DBITERR; + + + /*************************************************************************** + * Parameters used as constants + **************************************************************************/ + //When RST is present, set FULL reset value to '1'. + //If core has no RST, make sure FULL powers-on as '0'. + //The reset value assignments for FULL, ALMOST_FULL, and PROG_FULL are not + //changed for v3.2(IP2_Im). When the core has Sync Reset, C_HAS_SRST=1 and C_HAS_RST=0. + // Therefore, during SRST, all the FULL flags reset to 0. + parameter C_HAS_FAST_FIFO = 0; + parameter C_FIFO_WR_DEPTH = C_WR_DEPTH; + parameter C_FIFO_RD_DEPTH = C_RD_DEPTH; + + /************************************************************************** + * FIFO Contents Tracking and Data Count Calculations + *************************************************************************/ + // Memory which will be used to simulate a FIFO + reg [C_DIN_WIDTH-1:0] memory[C_WR_DEPTH-1:0]; + // Local parameters used to determine whether to inject ECC error or not + localparam SYMMETRIC_PORT = (C_DIN_WIDTH == C_DOUT_WIDTH) ? 1 : 0; + localparam ERR_INJECTION = (C_ERROR_INJECTION_TYPE != 0) ? 1 : 0; + localparam ENABLE_ERR_INJECTION = C_USE_ECC && SYMMETRIC_PORT && ERR_INJECTION; + // Array that holds the error injection type (single/double bit error) on + // a specific write operation, which is returned on read to corrupt the + // output data. + reg [1:0] ecc_err[C_WR_DEPTH-1:0]; + + //The amount of data stored in the FIFO at any time is given + // by num_bits. + //num_bits is calculated by from the total words in the FIFO. + reg [31:0] num_bits; + + //The write pointer - tracks write operations + // (Works opposite to core: wr_ptr is a DOWN counter) + reg [31:0] wr_ptr; + + //The write pointer - tracks read operations + // (Works opposite to core: rd_ptr is a DOWN counter) + reg [31:0] rd_ptr; + + /************************** + * Data Count + *************************/ + //Amount of data stored in the FIFO scaled to read words + wire [31:0] num_read_words = num_bits/C_DOUT_WIDTH; + //num_read_words delayed 1 clock cycle + reg [31:0] num_read_words_q; + + //Amount of data stored in the FIFO scaled to write words + wire [31:0] num_write_words = num_bits/C_DIN_WIDTH; + //num_write_words delayed 1 clock cycle + reg [31:0] num_write_words_q; + + + /************************************************************************** + * Internal Registers and wires + *************************************************************************/ + + //Temporary signals used for calculating the model's outputs. These + //are only used in the assign statements immediately following wire, + //parameter, and function declarations. + wire underflow_i; + wire valid_i; + wire valid_out; + + //Ideal FIFO signals. These are the raw output of the behavioral model, + //which behaves like an ideal FIFO. + reg [1:0] err_type = 0; + reg [1:0] err_type_d1 = 0; + reg [C_DOUT_WIDTH-1:0] ideal_dout; + reg [C_DOUT_WIDTH-1:0] ideal_dout_d1; + wire [C_DOUT_WIDTH-1:0] ideal_dout_out; + wire fwft_enabled; + reg ideal_wr_ack; + reg ideal_valid; + reg ideal_overflow; + reg ideal_underflow; + reg ideal_full; + reg ideal_empty; + reg ideal_almost_full; + reg ideal_almost_empty; + reg ideal_prog_full; + reg ideal_prog_empty; + + //Assorted reg values for delayed versions of signals + reg valid_d1; + reg prog_full_d; + reg prog_empty_d; + + + //Internal reset signals + reg rst_asreg =0; + reg rst_asreg_d1 =0; + reg rst_asreg_d2 =0; + reg rst_reg =0; + reg rst_d1 =0; + wire rst_comb; + wire rst_i; + wire srst_i; + + //Delayed version of RST + reg rst_q; + reg rst_qq; + + //user specified value for reseting the size of the fifo + reg [C_DOUT_WIDTH-1:0] dout_reset_val; + + + /**************************************************************************** + * Function Declarations + ***************************************************************************/ + + /************************************************************************** + * write_fifo + * This task writes a word to the FIFO memory and updates the + * write pointer. + * FIFO size is relative to write domain. + ***************************************************************************/ + task write_fifo; + reg [1:0] corrupted_data; + begin + memory[wr_ptr] <= DIN; + // Store the type of error injection (double/single) on write + ecc_err[wr_ptr] <= {INJECTDBITERR,INJECTSBITERR}; + if (wr_ptr == 0) begin + wr_ptr <= C_WR_DEPTH - 1; + end else begin + wr_ptr <= wr_ptr - 1; + end + end + endtask // write_fifo + + /************************************************************************** + * read_fifo + * This task reads a word from the FIFO memory and updates the read + * pointer. It's output is the ideal_dout bus. + * FIFO size is relative to write domain. + ***************************************************************************/ + task read_fifo; + reg [C_DOUT_WIDTH-1:0] tmp_dout; + reg [1:0] tmp_ecc_err; + begin + tmp_dout = memory[rd_ptr][C_DIN_WIDTH-1:0]; + // Retreive the error injection type. Based on the error injection type + // corrupt the output data. + tmp_ecc_err = ecc_err[rd_ptr]; + if (ENABLE_ERR_INJECTION) begin + if (tmp_ecc_err[1]) begin // Corrupt the output data only for double bit error + if (C_DIN_WIDTH == 2) + tmp_dout = {~tmp_dout[C_DIN_WIDTH-1],~tmp_dout[C_DIN_WIDTH-2]}; + else + tmp_dout = {~tmp_dout[C_DIN_WIDTH-1],~tmp_dout[C_DIN_WIDTH-2],(tmp_dout << 2)}; + end else begin + tmp_dout = tmp_dout[C_DIN_WIDTH-1:0]; + end + err_type <= tmp_ecc_err; + end else begin + err_type <= 0; + end + ideal_dout <= tmp_dout; + + if (rd_ptr == 0) begin + rd_ptr <= C_RD_DEPTH - 1; + end else begin + rd_ptr <= rd_ptr - 1; + end + end + endtask + + /**************************************************************************** + * log2_val + * Returns the 'log2' value for the input value for the supported ratios + ***************************************************************************/ + function [31:0] log2_val; + input [31:0] binary_val; + + begin + if (binary_val == 8) begin + log2_val = 3; + end else if (binary_val == 4) begin + log2_val = 2; + end else begin + log2_val = 1; + end + end + endfunction + + /**************************************************************************** + * hexstr_conv + * Converts a string of type hex to a binary value (for C_DOUT_RST_VAL) + ***************************************************************************/ + function [C_DOUT_WIDTH-1:0] hexstr_conv; + input [(C_DOUT_WIDTH*8)-1:0] def_data; + + integer index,i,j; + reg [3:0] bin; + + begin + index = 0; + hexstr_conv = 'b0; + for( i=C_DOUT_WIDTH-1; i>=0; i=i-1 ) + begin + case (def_data[7:0]) + 8'b00000000 : + begin + bin = 4'b0000; + i = -1; + end + 8'b00110000 : bin = 4'b0000; + 8'b00110001 : bin = 4'b0001; + 8'b00110010 : bin = 4'b0010; + 8'b00110011 : bin = 4'b0011; + 8'b00110100 : bin = 4'b0100; + 8'b00110101 : bin = 4'b0101; + 8'b00110110 : bin = 4'b0110; + 8'b00110111 : bin = 4'b0111; + 8'b00111000 : bin = 4'b1000; + 8'b00111001 : bin = 4'b1001; + 8'b01000001 : bin = 4'b1010; + 8'b01000010 : bin = 4'b1011; + 8'b01000011 : bin = 4'b1100; + 8'b01000100 : bin = 4'b1101; + 8'b01000101 : bin = 4'b1110; + 8'b01000110 : bin = 4'b1111; + 8'b01100001 : bin = 4'b1010; + 8'b01100010 : bin = 4'b1011; + 8'b01100011 : bin = 4'b1100; + 8'b01100100 : bin = 4'b1101; + 8'b01100101 : bin = 4'b1110; + 8'b01100110 : bin = 4'b1111; + default : + begin + bin = 4'bx; + end + endcase + for( j=0; j<4; j=j+1) + begin + if ((index*4)+j < C_DOUT_WIDTH) + begin + hexstr_conv[(index*4)+j] = bin[j]; + end + end + index = index + 1; + def_data = def_data >> 8; + end + end + endfunction + + + /************************************************************************* + * Initialize Signals for clean power-on simulation + *************************************************************************/ + initial begin + num_bits = 0; + num_read_words_q = 0; + num_write_words_q = 0; + rd_ptr = C_RD_DEPTH -1; + wr_ptr = C_WR_DEPTH -1; + dout_reset_val = hexstr_conv(C_DOUT_RST_VAL); + ideal_dout = dout_reset_val; + err_type = 0; + ideal_wr_ack = 1'b0; + ideal_valid = 1'b0; + valid_d1 = 1'b0; + ideal_overflow = 1'b0; + ideal_underflow = 1'b0; + ideal_full = 1'b0; + ideal_empty = 1'b1; + ideal_almost_full = 1'b0; + ideal_almost_empty = 1'b1; + ideal_prog_full = 1'b0; + ideal_prog_empty = 1'b1; + prog_full_d = 1'b0; + prog_empty_d = 1'b1; + rst_q = 1'b0; + rst_qq = 1'b0; + end + + + /************************************************************************* + * Connect the module inputs and outputs to the internal signals of the + * behavioral model. + *************************************************************************/ + //Inputs + /* + wire CLK; + wire [C_DIN_WIDTH-1:0] DIN; + wire [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH; + wire [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_ASSERT; + wire [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_NEGATE; + wire [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH; + wire [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_ASSERT; + wire [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_NEGATE; + wire RD_EN; + wire RST; + wire WR_EN; + */ + + //Outputs + generate + if (C_HAS_ALMOST_EMPTY==1) begin : blockAE10 + assign ALMOST_EMPTY = ideal_almost_empty; + end + endgenerate + + generate + if (C_HAS_ALMOST_FULL==1) begin : blockAF10 + assign ALMOST_FULL = ideal_almost_full; + end + endgenerate + + //Dout may change behavior based on latency + assign fwft_enabled = (C_PRELOAD_LATENCY == 0 && C_PRELOAD_REGS == 1)? + 1: 0; + assign ideal_dout_out= ((C_USE_EMBEDDED_REG==1 && (fwft_enabled == 0)) && + (C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1))? + ideal_dout_d1: ideal_dout; + assign DOUT = ideal_dout_out; + + // Assign SBITERR and DBITERR based on latency + assign SBITERR = (C_ERROR_INJECTION_TYPE == 1 || C_ERROR_INJECTION_TYPE == 3) && + ((C_USE_EMBEDDED_REG==1 && (fwft_enabled == 0)) && + (C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1)) ? + err_type_d1[0]: err_type[0]; + assign DBITERR = (C_ERROR_INJECTION_TYPE == 2 || C_ERROR_INJECTION_TYPE == 3) && + ((C_USE_EMBEDDED_REG==1 && (fwft_enabled == 0)) && + (C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1)) ? + err_type_d1[1]: err_type[1]; + + assign EMPTY = ideal_empty; + assign FULL = ideal_full; + + //Overflow may be active-low + generate + if (C_HAS_OVERFLOW==1) begin : blockOF10 + assign OVERFLOW = ideal_overflow ? !C_OVERFLOW_LOW : C_OVERFLOW_LOW; + end + endgenerate + + assign PROG_EMPTY = ideal_prog_empty; + assign PROG_FULL = ideal_prog_full; + + //Valid may change behavior based on latency or active-low + generate + if (C_HAS_VALID==1) begin : blockVL10 + assign valid_i = (C_PRELOAD_LATENCY==0) ? (RD_EN & ~EMPTY) : ideal_valid; + assign valid_out = (C_PRELOAD_LATENCY==2 && + (C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1))? + valid_d1: valid_i; + assign VALID = valid_out ? !C_VALID_LOW : C_VALID_LOW; + end + endgenerate + + //Trim data count differently depending on set widths + generate + if ((C_HAS_DATA_COUNT == 1) && + (C_DATA_COUNT_WIDTH > C_RD_PNTR_WIDTH)) begin : blockDC1 + always @(num_read_words) + DATA_COUNT = num_read_words[C_RD_PNTR_WIDTH:0]; + end else if (C_HAS_DATA_COUNT == 1) begin : blockDC2 + always @(num_read_words) + DATA_COUNT = num_read_words[C_RD_PNTR_WIDTH-1:C_RD_PNTR_WIDTH-C_DATA_COUNT_WIDTH]; + end //if + endgenerate + + //Underflow may change behavior based on latency or active-low + generate + if (C_HAS_UNDERFLOW==1) begin : blockUF10 + assign underflow_i = (C_PRELOAD_LATENCY==0) ? (RD_EN & EMPTY) : ideal_underflow; + assign UNDERFLOW = underflow_i ? !C_UNDERFLOW_LOW : C_UNDERFLOW_LOW; + end + endgenerate + + + //Write acknowledge may be active low + generate + if (C_HAS_WR_ACK==1) begin : blockWK10 + assign WR_ACK = ideal_wr_ack ? !C_WR_ACK_LOW : C_WR_ACK_LOW; + end + endgenerate + + + /***************************************************************************** + * Internal reset logic + ****************************************************************************/ + assign srst_i = C_HAS_SRST ? SRST : 0; + assign rst_i = C_HAS_RST ? rst_reg : 0; + + generate + if (C_ENABLE_RST_SYNC == 0) begin : gnrst_sync + always @* rst_reg <= 1'b0; + end else if (C_HAS_RST==1) begin : blockRST3 + assign rst_comb = !rst_asreg_d2 && rst_asreg; + + always @(posedge CLK or posedge RST) begin + if (RST == 1'b1) begin + rst_asreg <= #`TCQ 1'b1; + end else begin + if (rst_asreg_d1 == 1'b1) begin + rst_asreg <= #`TCQ 1'b0; + end else begin + rst_asreg <= #`TCQ rst_asreg; + end + end + end + + always @(posedge CLK) begin + rst_asreg_d1 <= #`TCQ rst_asreg; + rst_asreg_d2 <= #`TCQ rst_asreg_d1; + end + + always @(posedge CLK or posedge rst_comb) begin + if (rst_comb == 1'b1) begin + rst_reg <= #`TCQ 1'b1; + end else begin + rst_reg <= #`TCQ 1'b0; + end + end + end + endgenerate + + /************************************************************************** + * Assorted registers for delayed versions of signals + **************************************************************************/ + //Capture delayed version of valid + generate + if (C_HAS_VALID==1) begin : blockVL20 + always @(posedge CLK or posedge rst_i) begin + if (rst_i == 1'b1) begin + valid_d1 <= #`TCQ 1'b0; + end else begin + if (srst_i) begin + valid_d1 <= #`TCQ 1'b0; + end else begin + valid_d1 <= #`TCQ valid_i; + end + end + end // always @ (posedge CLK or posedge rst_i) + end + endgenerate + + //Capture delayed version of dout + always @(posedge CLK or posedge rst_i) begin + if (rst_i == 1'b1) begin + err_type_d1 <= #`TCQ 0; + if (C_USE_DOUT_RST == 1) + ideal_dout_d1 <= #`TCQ dout_reset_val; + end else begin + if (srst_i) begin + err_type_d1 <= #`TCQ 0; + if (C_USE_DOUT_RST == 1) + ideal_dout_d1 <= #`TCQ dout_reset_val; + end else begin + ideal_dout_d1 <= #`TCQ ideal_dout; + err_type_d1 <= #`TCQ err_type; + end + end + end + + /************************************************************************** + * Overflow and Underflow Flag calculation + * (handled separately because they don't support rst) + **************************************************************************/ + generate + if (C_HAS_OVERFLOW==1) begin : blockOF20 + always @(posedge CLK) begin + ideal_overflow <= #`TCQ WR_EN & ideal_full; + end + end + endgenerate + + generate + if (C_HAS_UNDERFLOW==1) begin : blockUF20 + always @(posedge CLK) begin + ideal_underflow <= #`TCQ ideal_empty & RD_EN; + end + end + endgenerate + + /************************************************************************* + * Write and Read Logic + ************************************************************************/ + always @(posedge CLK or posedge rst_i) + begin : gen_wr_ack_resp + + //Register reset + rst_q <= #`TCQ rst_i; + rst_qq <= #`TCQ rst_q; + + end // block: gen_wr_ack_resp + + // block memory has a synchronous reset + always @(posedge CLK) begin : gen_fifo_blkmemdout + //Changed the latency of during async reset to '1' instead of '2' to + // make it consistent with the core. + if (rst_i || rst_q || srst_i) begin + err_type <= #`TCQ 0; + /******Initialize Read Domain Signals*********************************/ + if (C_USE_DOUT_RST == 1 && C_MEMORY_TYPE == 1) begin + ideal_dout <= #`TCQ dout_reset_val; + end + end + end //always + + always @(posedge CLK or posedge rst_i) begin : gen_fifo + + /****** Reset fifo - Asynchronous Reset**********************************/ + //Changed the latency of during async reset to '1' instead of '2' to + // make it consistent with the core. + if (rst_i) begin //v3.2 + /******Initialize Generic FIFO constructs*****************************/ + num_bits <= #`TCQ 0; + wr_ptr <= #`TCQ C_WR_DEPTH - 1; + rd_ptr <= #`TCQ C_RD_DEPTH - 1; + num_read_words_q <= #`TCQ 0; + num_write_words_q <= #`TCQ 0; + err_type <= #`TCQ 0; + + + /******Initialize Write Domain Signals********************************/ + ideal_wr_ack <= #`TCQ 0; + ideal_full <= #`TCQ C_FULL_FLAGS_RST_VAL; + ideal_almost_full <= #`TCQ C_FULL_FLAGS_RST_VAL; + + /******Initialize Read Domain Signals*********************************/ + if (C_MEMORY_TYPE != 1 && C_USE_DOUT_RST == 1) begin + ideal_dout <= #`TCQ dout_reset_val; + end + ideal_valid <= #`TCQ 1'b0; + ideal_empty <= #`TCQ 1'b1; + ideal_almost_empty <= #`TCQ 1'b1; + + end else begin + if (srst_i) begin + // SRST is available only for Sync BRAM and Sync DRAM. + // Not for SSHFT. + if (C_MEMORY_TYPE == 1 || C_MEMORY_TYPE == 2 || C_MEMORY_TYPE == 3) begin + /******Initialize Generic FIFO constructs***********************/ + num_bits <= #`TCQ 0; + wr_ptr <= #`TCQ C_WR_DEPTH - 1; + rd_ptr <= #`TCQ C_RD_DEPTH - 1; + num_read_words_q <= #`TCQ 0; + num_write_words_q <= #`TCQ 0; + err_type <= #`TCQ 0; + + /******Initialize Write Domain Signals**************************/ + ideal_wr_ack <= #`TCQ 0; + ideal_full <= #`TCQ 0; //'0' + ideal_almost_full <= #`TCQ 0; //'0' + + /******Initialize Read Domain Signals***************************/ + //Reset DOUT of Sync DRAM/Shift RAM. Sync BRAM DOUT was reset in the + // above always block. + if (C_USE_DOUT_RST == 1 && (C_MEMORY_TYPE == 2 || C_MEMORY_TYPE == 3)) begin + ideal_dout <= #`TCQ dout_reset_val; + end + ideal_valid <= #`TCQ 1'b0; + ideal_empty <= #`TCQ 1'b1; + ideal_almost_empty <= #`TCQ 1'b1; + end + + end else begin //normal operating conditions + /********************************************************************/ + // Synchronous FIFO Condition #1 : Writing and not reading + /********************************************************************/ + if (WR_EN & ~RD_EN) begin + + /*********************************/ + //If the FIFO is full, do NOT perform the write, + // update flags accordingly + /*********************************/ + if (num_write_words >= C_FIFO_WR_DEPTH) begin + ideal_wr_ack <= #`TCQ 0; + + //still full + ideal_full <= #`TCQ 1'b1; + ideal_almost_full <= #`TCQ 1'b1; + + //write unsuccessful - do not change contents + + // no read attempted + ideal_valid <= #`TCQ 1'b0; + + //Not near empty + ideal_empty <= #`TCQ 1'b0; + ideal_almost_empty <= #`TCQ 1'b0; + + + /*********************************/ + //If the FIFO is reporting FULL + // (Startup condition) + /*********************************/ + end else if ((num_write_words < C_FIFO_WR_DEPTH) && (ideal_full == 1'b1)) begin + ideal_wr_ack <= #`TCQ 0; + + //still full + ideal_full <= #`TCQ 1'b0; + ideal_almost_full <= #`TCQ 1'b0; + + //write unsuccessful - do not change contents + + // no read attempted + ideal_valid <= #`TCQ 1'b0; + + //FIFO EMPTY in this state can not be determined + //ideal_empty <= 1'b0; + //ideal_almost_empty <= 1'b0; + + + /*********************************/ + //If the FIFO is one from full + /*********************************/ + end else if (num_write_words == C_FIFO_WR_DEPTH-1) begin + //good write + ideal_wr_ack <= #`TCQ 1; + + //FIFO is one from FULL and going FULL + ideal_full <= #`TCQ 1'b1; + ideal_almost_full <= #`TCQ 1'b1; + + //Add input data + write_fifo; + + // no read attempted + ideal_valid <= #`TCQ 1'b0; + + //Not near empty + ideal_empty <= #`TCQ 1'b0; + ideal_almost_empty <= #`TCQ 1'b0; + + num_bits <= num_bits + C_DIN_WIDTH; + + /*********************************/ + //If the FIFO is 2 from full + /*********************************/ + end else if (num_write_words == C_FIFO_WR_DEPTH-2) begin + //good write + ideal_wr_ack <= #`TCQ 1; + + //2 from full, and writing, so set almost_full + ideal_full <= #`TCQ 1'b0; + ideal_almost_full <= #`TCQ 1'b1; + + //Add input data + write_fifo; + + //no read attempted + ideal_valid <= #`TCQ 1'b0; + + //Not near empty + ideal_empty <= #`TCQ 1'b0; + ideal_almost_empty <= #`TCQ 1'b0; + + num_bits <= #`TCQ num_bits + C_DIN_WIDTH; + + /*********************************/ + //If the FIFO is ALMOST EMPTY + /*********************************/ + end else if (num_read_words == 1) begin + //good write + ideal_wr_ack <= #`TCQ 1; + + //Not near FULL + ideal_full <= #`TCQ 1'b0; + ideal_almost_full <= #`TCQ 1'b0; + + //Add input data + write_fifo; + + // no read attempted + ideal_valid <= #`TCQ 1'b0; + + //Leaving ALMOST_EMPTY + ideal_empty <= #`TCQ 1'b0; + ideal_almost_empty <= #`TCQ 1'b0; + + num_bits <= #`TCQ num_bits + C_DIN_WIDTH; + + /*********************************/ + //If the FIFO is EMPTY + /*********************************/ + end else if (num_read_words == 0) begin + // good write + ideal_wr_ack <= #`TCQ 1; + + //Not near FULL + ideal_full <= #`TCQ 1'b0; + ideal_almost_full <= #`TCQ 1'b0; + + //Add input data + write_fifo; + + // no read attempted + ideal_valid <= #`TCQ 1'b0; + + //Leaving EMPTY (still ALMOST_EMPTY) + ideal_empty <= #`TCQ 1'b0; + ideal_almost_empty <= #`TCQ 1'b1; + + num_bits <= #`TCQ num_bits + C_DIN_WIDTH; + + /*********************************/ + //If the FIFO is not near EMPTY or FULL + /*********************************/ + end else begin + // good write + ideal_wr_ack <= #`TCQ 1; + + //Not near FULL + ideal_full <= #`TCQ 1'b0; + ideal_almost_full <= #`TCQ 1'b0; + + //Add input data + write_fifo; + + // no read attempted + ideal_valid <= #`TCQ 1'b0; + + //Not near EMPTY + ideal_empty <= #`TCQ 1'b0; + ideal_almost_empty <= #`TCQ 1'b0; + + num_bits <= #`TCQ num_bits + C_DIN_WIDTH; + + end // average case + + + /******************************************************************/ + // Synchronous FIFO Condition #2 : Reading and not writing + /******************************************************************/ + end else if (~WR_EN & RD_EN) begin + + /*********************************/ + //If the FIFO is EMPTY + /*********************************/ + if ((num_read_words == 0) || (ideal_empty == 1'b1)) begin + //no write attemped + ideal_wr_ack <= #`TCQ 0; + + //FIFO is not near FULL + ideal_full <= #`TCQ 1'b0; + ideal_almost_full <= #`TCQ 1'b0; + + //Read will fail + ideal_valid <= #`TCQ 1'b0; + + //FIFO is still empty + ideal_empty <= #`TCQ 1'b1; + ideal_almost_empty <= #`TCQ 1'b1; + + //No read + + /*********************************/ + //If the FIFO is ALMOST EMPTY + /*********************************/ + end else if (num_read_words == 1) begin + //no write attempted + ideal_wr_ack <= #`TCQ 0; + + //FIFO is not near FULL + ideal_full <= #`TCQ 1'b0; + ideal_almost_full <= #`TCQ 1'b0; + + //Read successful + ideal_valid <= #`TCQ 1'b1; + + //This read will make FIFO go empty + ideal_empty <= #`TCQ 1'b1; + ideal_almost_empty <= #`TCQ 1'b1; + + //Get the data from the FIFO + read_fifo; + num_bits <= #`TCQ num_bits - C_DIN_WIDTH; + + + /*********************************/ + //If the FIFO is 2 from EMPTY + /*********************************/ + end else if (num_read_words == 2) begin + + //no write attempted + ideal_wr_ack <= #`TCQ 0; + + //FIFO is not near FULL + ideal_full <= #`TCQ 1'b0; + ideal_almost_full <= #`TCQ 1'b0; + + //Read successful + ideal_valid <= #`TCQ 1'b1; + + //FIFO is going ALMOST_EMPTY + ideal_empty <= #`TCQ 1'b0; + ideal_almost_empty <= #`TCQ 1'b1; + + //Get the data from the FIFO + read_fifo; + num_bits <= #`TCQ num_bits - C_DOUT_WIDTH; + + + + /*********************************/ + //If the FIFO is one from full + /*********************************/ + end else if (num_write_words == C_FIFO_WR_DEPTH-1) begin + + //no write attempted + ideal_wr_ack <= #`TCQ 0; + + //FIFO is leaving ALMOST FULL + ideal_full <= #`TCQ 1'b0; + ideal_almost_full <= #`TCQ 1'b0; + + //Read successful + ideal_valid <= #`TCQ 1'b1; + + //Not near empty + ideal_empty <= #`TCQ 1'b0; + ideal_almost_empty <= #`TCQ 1'b0; + + //Read from the FIFO + read_fifo; + num_bits <= #`TCQ num_bits - C_DOUT_WIDTH; + + + /*********************************/ + // FIFO is FULL + /*********************************/ + end else if (num_write_words >= C_FIFO_WR_DEPTH) + begin + //no write attempted + ideal_wr_ack <= #`TCQ 0; + + //FIFO is leaving FULL, but is still ALMOST_FULL + ideal_full <= #`TCQ 1'b0; + ideal_almost_full <= #`TCQ 1'b1; + + //Read successful + ideal_valid <= #`TCQ 1'b1; + + //Not near empty + ideal_empty <= #`TCQ 1'b0; + ideal_almost_empty <= #`TCQ 1'b0; + + //Read from the FIFO + read_fifo; + num_bits <= #`TCQ num_bits - C_DOUT_WIDTH; + + /*********************************/ + //If the FIFO is not near EMPTY or FULL + /*********************************/ + end else begin + //no write attemped + ideal_wr_ack <= #`TCQ 0; + + //Not near empty + ideal_full <= #`TCQ 1'b0; + ideal_almost_full <= #`TCQ 1'b0; + + //Read successful + ideal_valid <= #`TCQ 1'b1; + + //Not near empty + ideal_empty <= #`TCQ 1'b0; + ideal_almost_empty <= #`TCQ 1'b0; + + //Read from the FIFO + read_fifo; + num_bits <= #`TCQ num_bits - C_DOUT_WIDTH; + + + end // average read + + + /******************************************************************/ + // Synchronous FIFO Condition #3 : Reading and writing + /******************************************************************/ + end else if (WR_EN & RD_EN) begin + + /*********************************/ + // FIFO is FULL + /*********************************/ + if (num_write_words >= C_FIFO_WR_DEPTH) begin + + ideal_wr_ack <= #`TCQ 0; + + //Read will be successful, so FIFO will leave FULL + ideal_full <= #`TCQ 1'b0; + ideal_almost_full <= #`TCQ 1'b1; + + //Read successful + ideal_valid <= #`TCQ 1'b1; + + //Not near empty + ideal_empty <= #`TCQ 1'b0; + ideal_almost_empty <= #`TCQ 1'b0; + + //Read from the FIFO + read_fifo; + num_bits <= #`TCQ num_bits - C_DOUT_WIDTH; + + + /*********************************/ + // FIFO is reporting FULL, but it is empty + // (This is a special case, when coming out of RST + /*********************************/ + end else if ((num_write_words == 0) && (ideal_full == 1'b1)) begin + + ideal_wr_ack <= #`TCQ 0; + + //Read will be successful, so FIFO will leave FULL + ideal_full <= #`TCQ 1'b0; + ideal_almost_full <= #`TCQ 1'b0; + + //Read unsuccessful + ideal_valid <= #`TCQ 1'b0; + + //Report empty condition + ideal_empty <= #`TCQ 1'b1; + ideal_almost_empty <= #`TCQ 1'b1; + + //Do not read from empty FIFO + // Read from the FIFO + + + /*********************************/ + //If the FIFO is one from full + /*********************************/ + end else if (num_write_words == C_FIFO_WR_DEPTH-1) begin + + //Write successful + ideal_wr_ack <= #`TCQ 1; + + //FIFO will remain ALMOST_FULL + ideal_full <= #`TCQ 1'b0; + ideal_almost_full <= #`TCQ 1'b1; + + // put the data into the FIFO + write_fifo; + + //Read successful + ideal_valid <= #`TCQ 1'b1; + + //Not near empty + ideal_empty <= #`TCQ 1'b0; + ideal_almost_empty <= #`TCQ 1'b0; + + //Read from the FIFO + read_fifo; + num_bits <= #`TCQ num_bits + C_DIN_WIDTH - C_DOUT_WIDTH; + + /*********************************/ + //If the FIFO is ALMOST EMPTY + /*********************************/ + end else if (num_read_words == 1) begin + + //Write successful + ideal_wr_ack <= #`TCQ 1; + + // Not near FULL + ideal_full <= #`TCQ 1'b0; + ideal_almost_full <= #`TCQ 1'b0; + + // put the data into the FIFO + write_fifo; + + //Read successful + ideal_valid <= #`TCQ 1'b1; + + //FIFO will stay ALMOST_EMPTY + ideal_empty <= #`TCQ 1'b0; + ideal_almost_empty <= #`TCQ 1'b1; + + //Read from the FIFO + read_fifo; + num_bits <= #`TCQ num_bits + C_DIN_WIDTH - C_DOUT_WIDTH; + + + /*********************************/ + //If the FIFO is EMPTY + /*********************************/ + end else if (num_read_words == 0) begin + + //Write successful + ideal_wr_ack <= #`TCQ 1; + + // Not near FULL + ideal_full <= #`TCQ 1'b0; + ideal_almost_full <= #`TCQ 1'b0; + + // put the data into the FIFO + write_fifo; + + //Read will fail + ideal_valid <= #`TCQ 1'b0; + + //FIFO will leave EMPTY + ideal_empty <= #`TCQ 1'b0; + ideal_almost_empty <= #`TCQ 1'b1; + + // No read + num_bits <= #`TCQ num_bits + C_DIN_WIDTH; + + + /*********************************/ + //If the FIFO is not near EMPTY or FULL + /*********************************/ + end else begin + + //Write successful + ideal_wr_ack <= #`TCQ 1; + + // Not near FULL + ideal_full <= #`TCQ 1'b0; + ideal_almost_full <= #`TCQ 1'b0; + + // put the data into the FIFO + write_fifo; + + //Read successful + ideal_valid <= #`TCQ 1'b1; + + // Not near EMPTY + ideal_empty <= #`TCQ 1'b0; + ideal_almost_empty <= #`TCQ 1'b0; + + //Read from the FIFO + read_fifo; + num_bits <= #`TCQ num_bits + C_DIN_WIDTH - C_DOUT_WIDTH; + + end // average case + + /******************************************************************/ + // Synchronous FIFO Condition #4 : Not reading or writing + /******************************************************************/ + end else begin + + /*********************************/ + // FIFO is FULL + /*********************************/ + if (num_write_words >= C_FIFO_WR_DEPTH) begin + + //No write + ideal_wr_ack <= #`TCQ 0; + ideal_full <= #`TCQ 1'b1; + ideal_almost_full <= #`TCQ 1'b1; + + //No read + ideal_valid <= #`TCQ 1'b0; + ideal_empty <= #`TCQ 1'b0; + ideal_almost_empty <= #`TCQ 1'b0; + + //No change to memory + + /*********************************/ + //If the FIFO is one from full + /*********************************/ + end else if (num_write_words == C_FIFO_WR_DEPTH-1) begin + + //No write + ideal_wr_ack <= #`TCQ 0; + ideal_full <= #`TCQ 1'b0; + ideal_almost_full <= #`TCQ 1'b1; + + //No read + ideal_valid <= #`TCQ 1'b0; + ideal_empty <= #`TCQ 1'b0; + ideal_almost_empty <= #`TCQ 1'b0; + + //No change to memory + + /*********************************/ + //If the FIFO is ALMOST EMPTY + /*********************************/ + end else if (num_read_words == 1) begin + //No write + ideal_wr_ack <= #`TCQ 0; + ideal_full <= #`TCQ 1'b0; + ideal_almost_full <= #`TCQ 1'b0; + + //No read + ideal_valid <= #`TCQ 1'b0; + ideal_empty <= #`TCQ 1'b0; + ideal_almost_empty <= #`TCQ 1'b1; + + //No change to memory + + end // almost empty + + + /*********************************/ + //If the FIFO is EMPTY + /*********************************/ + else if (num_read_words == 0) + begin + //No write + ideal_wr_ack <= #`TCQ 0; + ideal_full <= #`TCQ 1'b0; + ideal_almost_full <= #`TCQ 1'b0; + + //No read + ideal_valid <= #`TCQ 1'b0; + ideal_empty <= #`TCQ 1'b1; + ideal_almost_empty <= #`TCQ 1'b1; + + //No change to memory + + /*********************************/ + //If the FIFO is not near EMPTY or FULL + /*********************************/ + end else begin + + //No write + ideal_wr_ack <= #`TCQ 0; + ideal_full <= #`TCQ 1'b0; + ideal_almost_full <= #`TCQ 1'b0; + + //No read + ideal_valid <= #`TCQ 1'b0; + ideal_empty <= #`TCQ 1'b0; + ideal_almost_empty <= #`TCQ 1'b0; + + //No change to memory + + end // average case + + end // neither reading or writing + + num_read_words_q <= #`TCQ num_read_words; + num_write_words_q <= #`TCQ num_write_words; + + end //normal operating conditions + end + + end // block: gen_fifo + + + always @(posedge CLK or posedge rst_i) begin : gen_fifo_p + + /****** Reset fifo - Async Reset****************************************/ + //The latency of de-assertion of the flags is reduced by 1 to be + // consistent with the core. + if (rst_i) begin + ideal_prog_full <= #`TCQ C_FULL_FLAGS_RST_VAL; + ideal_prog_empty <= #`TCQ 1'b1; + prog_full_d <= #`TCQ C_FULL_FLAGS_RST_VAL; + prog_empty_d <= #`TCQ 1'b1; + + end else begin + if (srst_i) begin + //SRST is available only for Sync BRAM and Sync DRAM. Not for SSHFT. + if (C_MEMORY_TYPE == 1 || C_MEMORY_TYPE == 2 || C_MEMORY_TYPE == 3) begin + ideal_prog_full <= #`TCQ 1'b0; + ideal_prog_empty <= #`TCQ 1'b1; + prog_full_d <= #`TCQ 1'b0; + prog_empty_d <= #`TCQ 1'b1; + end + end else begin + + /*************************************************************** + * Programmable FULL flags + ****************************************************************/ + //calculation for standard fifo and latency =2 + if (! (C_PRELOAD_REGS==1 && C_PRELOAD_LATENCY==0) ) begin + //Single constant threshold + if (C_PROG_FULL_TYPE == 1) begin + if ((num_write_words >= C_PROG_FULL_THRESH_ASSERT_VAL-1) + && WR_EN && !RD_EN) begin + prog_full_d <= #`TCQ 1'b1; + end else if (((num_write_words == C_PROG_FULL_THRESH_ASSERT_VAL) + && RD_EN && !WR_EN) || (rst_q && !rst_i)) begin + prog_full_d <= #`TCQ 1'b0; + end + + //Dual constant thresholds + end else if (C_PROG_FULL_TYPE == 2) begin + if ((num_write_words == C_PROG_FULL_THRESH_ASSERT_VAL-1) + && WR_EN && !RD_EN) begin + prog_full_d <= #`TCQ 1'b1; + end else if ((num_write_words == C_PROG_FULL_THRESH_NEGATE_VAL) + && RD_EN && !WR_EN) begin + prog_full_d <= #`TCQ 1'b0; + end + + //Single input threshold + end else if (C_PROG_FULL_TYPE == 3) begin + if ((num_write_words == PROG_FULL_THRESH-1) + && WR_EN && !RD_EN) begin + prog_full_d <= #`TCQ 1'b1; + end else if ((num_write_words == PROG_FULL_THRESH) + && !WR_EN && RD_EN) begin + prog_full_d <= #`TCQ 1'b0; + end else if (num_write_words >= PROG_FULL_THRESH) begin + prog_full_d <= #`TCQ 1'b1; + end else if (num_write_words < PROG_FULL_THRESH) begin + prog_full_d <= #`TCQ 1'b0; + end + + //Dual input thresholds + end else begin + if ((num_write_words == PROG_FULL_THRESH_ASSERT-1) + && WR_EN && !RD_EN) begin + prog_full_d <= #`TCQ 1'b1; + end else if ((num_write_words == PROG_FULL_THRESH_NEGATE) + && !WR_EN && RD_EN)begin + prog_full_d <= #`TCQ 1'b0; + end else if (num_write_words >= PROG_FULL_THRESH_ASSERT) begin + prog_full_d <= #`TCQ 1'b1; + end else if (num_write_words < PROG_FULL_THRESH_NEGATE) begin + prog_full_d <= #`TCQ 1'b0; + end + end + end // (~ (C_PRELOAD_REGS==1 && C_PRELOAD_LATENCY==0) ) + + + //calculation for FWFT fifo + if (C_PRELOAD_REGS==1 && C_PRELOAD_LATENCY==0) begin + if (C_PROG_FULL_TYPE == 1) begin + if ((num_write_words >= C_PROG_FULL_THRESH_ASSERT_VAL-1 - 2) + && WR_EN && !RD_EN) begin + prog_full_d <= #`TCQ 1'b1; + end else if (((num_write_words == C_PROG_FULL_THRESH_ASSERT_VAL - 2) + && RD_EN && !WR_EN) || (rst_q && !rst_i)) begin + prog_full_d <= #`TCQ 1'b0; + end + + //Dual constant thresholds + end else if (C_PROG_FULL_TYPE == 2) begin + if ((num_write_words == C_PROG_FULL_THRESH_ASSERT_VAL-1 - 2) + && WR_EN && !RD_EN) begin + prog_full_d <= #`TCQ 1'b1; + end else if ((num_write_words == C_PROG_FULL_THRESH_NEGATE_VAL - 2) + && RD_EN && !WR_EN) begin + prog_full_d <= #`TCQ 1'b0; + end + + //Single input threshold + end else if (C_PROG_FULL_TYPE == 3) begin + if ((num_write_words == PROG_FULL_THRESH-1 - 2) + && WR_EN && !RD_EN) begin + prog_full_d <= #`TCQ 1'b1; + end else if ((num_write_words == PROG_FULL_THRESH - 2) + && !WR_EN && RD_EN) begin + prog_full_d <= #`TCQ 1'b0; + end else if (num_write_words >= PROG_FULL_THRESH - 2) begin + prog_full_d <= #`TCQ 1'b1; + end else if (num_write_words < PROG_FULL_THRESH - 2) begin + prog_full_d <= #`TCQ 1'b0; + end + + //Dual input thresholds + end else begin + if ((num_write_words == PROG_FULL_THRESH_ASSERT-1 - 2) + && WR_EN && !RD_EN) begin + prog_full_d <= #`TCQ 1'b1; + end else if ((num_write_words == PROG_FULL_THRESH_NEGATE - 2) + && !WR_EN && RD_EN)begin + prog_full_d <= #`TCQ 1'b0; + end else if (num_write_words >= PROG_FULL_THRESH_ASSERT - 2) begin + prog_full_d <= #`TCQ 1'b1; + end else if (num_write_words < PROG_FULL_THRESH_NEGATE - 2) begin + prog_full_d <= #`TCQ 1'b0; + end + end + end // (C_PRELOAD_REGS==1 && C_PRELOAD_LATENCY==0) + + /***************************************************************** + * Programmable EMPTY flags + ****************************************************************/ + //calculation for standard fifo and latency = 2 + if (! (C_PRELOAD_REGS==1 && C_PRELOAD_LATENCY==0) ) begin + //Single constant threshold + if (C_PROG_EMPTY_TYPE == 1) begin + if ((num_read_words == C_PROG_EMPTY_THRESH_ASSERT_VAL+1) + && RD_EN && !WR_EN) begin + prog_empty_d <= #`TCQ 1'b1; + end else if ((num_read_words == C_PROG_EMPTY_THRESH_ASSERT_VAL) + && WR_EN && !RD_EN) begin + prog_empty_d <= #`TCQ 1'b0; + end + //Dual constant thresholds + end else if (C_PROG_EMPTY_TYPE == 2) begin + if ((num_read_words == C_PROG_EMPTY_THRESH_ASSERT_VAL+1) + && RD_EN && !WR_EN) begin + prog_empty_d <= #`TCQ 1'b1; + end else if ((num_read_words == C_PROG_EMPTY_THRESH_NEGATE_VAL) + && !RD_EN && WR_EN) begin + prog_empty_d <= #`TCQ 1'b0; + end + + //Single input threshold + end else if (C_PROG_EMPTY_TYPE == 3) begin + if ((num_read_words == PROG_EMPTY_THRESH+1) + && RD_EN && !WR_EN) begin + prog_empty_d <= #`TCQ 1'b1; + end else if ((num_read_words == PROG_EMPTY_THRESH) + && !RD_EN && WR_EN) begin + prog_empty_d <= #`TCQ 1'b0; + end else if (num_read_words <= PROG_EMPTY_THRESH) begin + prog_empty_d <= #`TCQ 1'b1; + end else if (num_read_words > PROG_EMPTY_THRESH)begin + prog_empty_d <= #`TCQ 1'b0; + end + + //Dual input thresholds + end else begin + if (num_read_words <= PROG_EMPTY_THRESH_ASSERT) begin + prog_empty_d <= #`TCQ 1'b1; + end else if ((num_read_words == PROG_EMPTY_THRESH_ASSERT+1) + && RD_EN && !WR_EN) begin + prog_empty_d <= #`TCQ 1'b1; + end else if (num_read_words > PROG_EMPTY_THRESH_NEGATE)begin + prog_empty_d <= #`TCQ 1'b0; + end else if ((num_read_words == PROG_EMPTY_THRESH_NEGATE) + && !RD_EN && WR_EN) begin + prog_empty_d <= #`TCQ 1'b0; + end + end + end // (~ (C_PRELOAD_REGS==1 && C_PRELOAD_LATENCY==0) ) + + //calculation for FWFT fifo + if (C_PRELOAD_REGS==1 && C_PRELOAD_LATENCY==0) begin + //Single constant threshold + if (C_PROG_EMPTY_TYPE == 1) begin + if ((num_read_words == C_PROG_EMPTY_THRESH_ASSERT_VAL+1 - 2) + && RD_EN && !WR_EN) begin + prog_empty_d <= #`TCQ 1'b1; + end else if ((num_read_words == C_PROG_EMPTY_THRESH_ASSERT_VAL - 2) + && WR_EN && !RD_EN) begin + prog_empty_d <= #`TCQ 1'b0; + end + //Dual constant thresholds + end else if (C_PROG_EMPTY_TYPE == 2) begin + if ((num_read_words == C_PROG_EMPTY_THRESH_ASSERT_VAL+1 - 2) + && RD_EN && !WR_EN) begin + prog_empty_d <= #`TCQ 1'b1; + end else if ((num_read_words == C_PROG_EMPTY_THRESH_NEGATE_VAL - 2) + && !RD_EN && WR_EN) begin + prog_empty_d <= #`TCQ 1'b0; + end + + //Single input threshold + end else if (C_PROG_EMPTY_TYPE == 3) begin + if ((num_read_words == PROG_EMPTY_THRESH+1 - 2) + && RD_EN && !WR_EN) begin + prog_empty_d <= #`TCQ 1'b1; + end else if ((num_read_words == PROG_EMPTY_THRESH - 2) + && !RD_EN && WR_EN) begin + prog_empty_d <= #`TCQ 1'b0; + end else if (num_read_words <= PROG_EMPTY_THRESH - 2) begin + prog_empty_d <= #`TCQ 1'b1; + end else if (num_read_words > PROG_EMPTY_THRESH - 2)begin + prog_empty_d <= #`TCQ 1'b0; + end + + //Dual input thresholds + end else begin + if (num_read_words <= PROG_EMPTY_THRESH_ASSERT - 2) begin + prog_empty_d <= #`TCQ 1'b1; + end else if ((num_read_words == PROG_EMPTY_THRESH_ASSERT+1 - 2) + && RD_EN && !WR_EN) begin + prog_empty_d <= #`TCQ 1'b1; + end else if (num_read_words > PROG_EMPTY_THRESH_NEGATE - 2)begin + prog_empty_d <= #`TCQ 1'b0; + end else if ((num_read_words == PROG_EMPTY_THRESH_NEGATE - 2) + && !RD_EN && WR_EN) begin + prog_empty_d <= #`TCQ 1'b0; + end + end + end // (~ (C_PRELOAD_REGS==1 && C_PRELOAD_LATENCY==0) ) + + ideal_prog_empty <= prog_empty_d; + if (rst_q && !rst_i) begin + ideal_prog_full <= #`TCQ 1'b0; + prog_full_d <= #`TCQ 1'b0; + end else begin + ideal_prog_full <= #`TCQ prog_full_d; + end + + end //if (srst_i) begin + end //if (rst_i) begin + end //always @(posedge CLK or posedge rst_i) begin : gen_fifo_p +endmodule // fifo_generator_v5_1_bhv_ver_ss + + + +/************************************************************************** + * First-Word Fall-Through module (preload 0) + **************************************************************************/ +module fifo_generator_v5_1_bhv_ver_preload0 + ( + RD_CLK, + RD_RST, + SRST, + RD_EN, + FIFOEMPTY, + FIFODATA, + FIFOSBITERR, + FIFODBITERR, + USERDATA, + USERVALID, + USERUNDERFLOW, + USEREMPTY, + USERALMOSTEMPTY, + RAMVALID, + FIFORDEN, + USERSBITERR, + USERDBITERR, + ); + + parameter C_DOUT_RST_VAL = ""; + parameter C_DOUT_WIDTH = 8; + parameter C_HAS_RST = 0; + parameter C_ENABLE_RST_SYNC = 0; + parameter C_HAS_SRST = 0; + parameter C_USE_DOUT_RST = 0; + parameter C_USERVALID_LOW = 0; + parameter C_USERUNDERFLOW_LOW = 0; + + //Inputs + input RD_CLK; + input RD_RST; + input SRST; + input RD_EN; + input FIFOEMPTY; + input [C_DOUT_WIDTH-1:0] FIFODATA; + input FIFOSBITERR; + input FIFODBITERR; + + //Outputs + output [C_DOUT_WIDTH-1:0] USERDATA; + output USERVALID; + output USERUNDERFLOW; + output USEREMPTY; + output USERALMOSTEMPTY; + output RAMVALID; + output FIFORDEN; + output USERSBITERR; + output USERDBITERR; + + //Inputs + wire RD_CLK; + wire RD_RST; + wire RD_EN; + wire FIFOEMPTY; + wire [C_DOUT_WIDTH-1:0] FIFODATA; + wire FIFOSBITERR; + wire FIFODBITERR; + + //Outputs + reg [C_DOUT_WIDTH-1:0] USERDATA; + wire USERVALID; + wire USERUNDERFLOW; + wire USEREMPTY; + wire USERALMOSTEMPTY; + wire RAMVALID; + wire FIFORDEN; + reg USERSBITERR; + reg USERDBITERR; + + //Internal signals + wire preloadstage1; + wire preloadstage2; + reg ram_valid_i; + reg read_data_valid_i; + wire ram_regout_en; + wire ram_rd_en; + reg empty_i = 1'b1; + reg empty_q = 1'b1; + reg rd_en_q = 1'b0; + reg almost_empty_i = 1'b1; + reg almost_empty_q = 1'b1; + wire rd_rst_i; + wire srst_i; + + +/************************************************************************* +* FUNCTIONS +*************************************************************************/ + + /************************************************************************* + * hexstr_conv + * Converts a string of type hex to a binary value (for C_DOUT_RST_VAL) + ***********************************************************************/ + function [C_DOUT_WIDTH-1:0] hexstr_conv; + input [(C_DOUT_WIDTH*8)-1:0] def_data; + + integer index,i,j; + reg [3:0] bin; + + begin + index = 0; + hexstr_conv = 'b0; + for( i=C_DOUT_WIDTH-1; i>=0; i=i-1 ) + begin + case (def_data[7:0]) + 8'b00000000 : + begin + bin = 4'b0000; + i = -1; + end + 8'b00110000 : bin = 4'b0000; + 8'b00110001 : bin = 4'b0001; + 8'b00110010 : bin = 4'b0010; + 8'b00110011 : bin = 4'b0011; + 8'b00110100 : bin = 4'b0100; + 8'b00110101 : bin = 4'b0101; + 8'b00110110 : bin = 4'b0110; + 8'b00110111 : bin = 4'b0111; + 8'b00111000 : bin = 4'b1000; + 8'b00111001 : bin = 4'b1001; + 8'b01000001 : bin = 4'b1010; + 8'b01000010 : bin = 4'b1011; + 8'b01000011 : bin = 4'b1100; + 8'b01000100 : bin = 4'b1101; + 8'b01000101 : bin = 4'b1110; + 8'b01000110 : bin = 4'b1111; + 8'b01100001 : bin = 4'b1010; + 8'b01100010 : bin = 4'b1011; + 8'b01100011 : bin = 4'b1100; + 8'b01100100 : bin = 4'b1101; + 8'b01100101 : bin = 4'b1110; + 8'b01100110 : bin = 4'b1111; + default : + begin + bin = 4'bx; + end + endcase + for( j=0; j<4; j=j+1) + begin + if ((index*4)+j < C_DOUT_WIDTH) + begin + hexstr_conv[(index*4)+j] = bin[j]; + end + end + index = index + 1; + def_data = def_data >> 8; + end + end + endfunction + + + //************************************************************************* + // Set power-on states for regs + //************************************************************************* + initial begin + ram_valid_i = 1'b0; + read_data_valid_i = 1'b0; + USERDATA = hexstr_conv(C_DOUT_RST_VAL); + USERSBITERR = 1'b0; + USERDBITERR = 1'b0; + end //initial + + //*************************************************************************** + // connect up optional reset + //*************************************************************************** + assign rd_rst_i = (C_HAS_RST == 1 || C_ENABLE_RST_SYNC == 0) ? RD_RST : 0; + assign srst_i = C_HAS_SRST ? SRST : 0; + + + //*************************************************************************** + // preloadstage2 indicates that stage2 needs to be updated. This is true + // whenever read_data_valid is false, and RAM_valid is true. + //*************************************************************************** + assign preloadstage2 = ram_valid_i & (~read_data_valid_i | RD_EN); + + //*************************************************************************** + // preloadstage1 indicates that stage1 needs to be updated. This is true + // whenever the RAM has data (RAM_EMPTY is false), and either RAM_Valid is + // false (indicating that Stage1 needs updating), or preloadstage2 is active + // (indicating that Stage2 is going to update, so Stage1, therefore, must + // also be updated to keep it valid. + //*************************************************************************** + assign preloadstage1 = ((~ram_valid_i | preloadstage2) & ~FIFOEMPTY); + + //*************************************************************************** + // Calculate RAM_REGOUT_EN + // The output registers are controlled by the ram_regout_en signal. + // These registers should be updated either when the output in Stage2 is + // invalid (preloadstage2), OR when the user is reading, in which case the + // Stage2 value will go invalid unless it is replenished. + //*************************************************************************** + assign ram_regout_en = preloadstage2; + + //*************************************************************************** + // Calculate RAM_RD_EN + // RAM_RD_EN will be asserted whenever the RAM needs to be read in order to + // update the value in Stage1. + // One case when this happens is when preloadstage1=true, which indicates + // that the data in Stage1 or Stage2 is invalid, and needs to automatically + // be updated. + // The other case is when the user is reading from the FIFO, which + // guarantees that Stage1 or Stage2 will be invalid on the next clock + // cycle, unless it is replinished by data from the memory. So, as long + // as the RAM has data in it, a read of the RAM should occur. + //*************************************************************************** + assign ram_rd_en = (RD_EN & ~FIFOEMPTY) | preloadstage1; + + //*************************************************************************** + // Calculate RAMVALID_P0_OUT + // RAMVALID_P0_OUT indicates that the data in Stage1 is valid. + // + // If the RAM is being read from on this clock cycle (ram_rd_en=1), then + // RAMVALID_P0_OUT is certainly going to be true. + // If the RAM is not being read from, but the output registers are being + // updated to fill Stage2 (ram_regout_en=1), then Stage1 will be emptying, + // therefore causing RAMVALID_P0_OUT to be false. + // Otherwise, RAMVALID_P0_OUT will remain unchanged. + //*************************************************************************** + // PROCESS regout_valid + always @ (posedge RD_CLK or posedge rd_rst_i) begin + if (rd_rst_i) begin + // asynchronous reset (active high) + ram_valid_i <= #`TCQ 1'b0; + end else begin + if (srst_i) begin + // synchronous reset (active high) + ram_valid_i <= #`TCQ 1'b0; + end else begin + if (ram_rd_en == 1'b1) begin + ram_valid_i <= #`TCQ 1'b1; + end else begin + if (ram_regout_en == 1'b1) + ram_valid_i <= #`TCQ 1'b0; + else + ram_valid_i <= #`TCQ ram_valid_i; + end + end //srst_i + end //rd_rst_i + end //always + + //*************************************************************************** + // Calculate READ_DATA_VALID + // READ_DATA_VALID indicates whether the value in Stage2 is valid or not. + // Stage2 has valid data whenever Stage1 had valid data and + // ram_regout_en_i=1, such that the data in Stage1 is propogated + // into Stage2. + //*************************************************************************** + always @ (posedge RD_CLK or posedge rd_rst_i) begin + if (rd_rst_i) + read_data_valid_i <= #`TCQ 1'b0; + else if (srst_i) + read_data_valid_i <= #`TCQ 1'b0; + else + read_data_valid_i <= #`TCQ ram_valid_i | (read_data_valid_i & ~RD_EN); + end //always + + + //************************************************************************** + // Calculate EMPTY + // Defined as the inverse of READ_DATA_VALID + // + // Description: + // + // If read_data_valid_i indicates that the output is not valid, + // and there is no valid data on the output of the ram to preload it + // with, then we will report empty. + // + // If there is no valid data on the output of the ram and we are + // reading, then the FIFO will go empty. + // + //************************************************************************** + always @ (posedge RD_CLK or posedge rd_rst_i) begin + if (rd_rst_i) begin + // asynchronous reset (active high) + empty_i <= #`TCQ 1'b1; + empty_q <= #`TCQ 1'b1; + end else begin + if (srst_i) begin + // synchronous reset (active high) + empty_i <= #`TCQ 1'b1; + empty_q <= #`TCQ 1'b1; + end else begin + // rising clock edge + empty_i <= #`TCQ (~ram_valid_i & ~read_data_valid_i) | (~ram_valid_i & RD_EN); + empty_q <= #`TCQ empty_i; + end + end + end //always + + //Register RD_EN from user to calculate USERUNDERFLOW. + always @ (posedge RD_CLK or posedge rd_rst_i) begin + if (rd_rst_i) begin + // asynchronous reset (active high) + rd_en_q <= #`TCQ 1'b0; + end else begin + if (srst_i) begin + // synchronous reset (active high) + rd_en_q <= #`TCQ 1'b0; + end else begin + // rising clock edge + rd_en_q <= #`TCQ RD_EN; + end + end + end //always + + + //*************************************************************************** + // Calculate user_almost_empty + // user_almost_empty is defined such that, unless more words are written + // to the FIFO, the next read will cause the FIFO to go EMPTY. + // + // In most cases, whenever the output registers are updated (due to a user + // read or a preload condition), then user_almost_empty will update to + // whatever RAM_EMPTY is. + // + // The exception is when the output is valid, the user is not reading, and + // Stage1 is not empty. In this condition, Stage1 will be preloaded from the + // memory, so we need to make sure user_almost_empty deasserts properly under + // this condition. + //*************************************************************************** + always @ (posedge RD_CLK or posedge rd_rst_i) + begin + if (rd_rst_i) begin // asynchronous reset (active high) + almost_empty_i <= #`TCQ 1'b1; + almost_empty_q <= #`TCQ 1'b1; + end else begin // rising clock edge + if (srst_i) begin // synchronous reset (active high) + almost_empty_i <= #`TCQ 1'b1; + almost_empty_q <= #`TCQ 1'b1; + end else begin + if ((ram_regout_en) | (~FIFOEMPTY & read_data_valid_i & ~RD_EN)) begin + almost_empty_i <= #`TCQ FIFOEMPTY; + end + almost_empty_q <= #`TCQ empty_i; + end + end + end //always + + + assign USEREMPTY = empty_i; + assign USERALMOSTEMPTY = almost_empty_i; + assign FIFORDEN = ram_rd_en; + assign RAMVALID = ram_valid_i; + assign USERVALID = C_USERVALID_LOW ? ~read_data_valid_i : read_data_valid_i; + assign USERUNDERFLOW = C_USERUNDERFLOW_LOW ? ~(empty_q & rd_en_q) : empty_q & rd_en_q; + + always @ (posedge RD_CLK or posedge rd_rst_i) + begin + if (rd_rst_i) begin //asynchronous reset (active high) + USERSBITERR <= #`TCQ 0; + USERDBITERR <= #`TCQ 0; + if (C_USE_DOUT_RST == 1) //asynchronous reset (active high) + USERDATA <= #`TCQ hexstr_conv(C_DOUT_RST_VAL); + end else begin // rising clock edge + if (srst_i) begin + USERSBITERR <= #`TCQ 0; + USERDBITERR <= #`TCQ 0; + if (C_USE_DOUT_RST == 1) + USERDATA <= #`TCQ hexstr_conv(C_DOUT_RST_VAL); + end else if (ram_regout_en) begin + USERDATA <= #`TCQ FIFODATA; + USERSBITERR <= #`TCQ FIFOSBITERR; + USERDBITERR <= #`TCQ FIFODBITERR; + end + end + end //always + + + + + +endmodule diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/FIFO_GENERATOR_V5_1_XST.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/FIFO_GENERATOR_V5_1_XST.v new file mode 100644 index 0000000..8808647 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/FIFO_GENERATOR_V5_1_XST.v @@ -0,0 +1,337 @@ +/* + * $RDCfile: $ $Revision: 1.3 $ $Date: 2009/09/08 15:26:50 $ + ******************************************************************************* + * + * FIFO Generator - Verilog Behavioral Model + * + ******************************************************************************* + * + * (c) Copyright 1995 - 2009 Xilinx, Inc. All rights reserved. + * + * This file contains confidential and proprietary information + * of Xilinx, Inc. and is protected under U.S. and + * international copyright and other intellectual property + * laws. + * + * DISCLAIMER + * This disclaimer is not a license and does not grant any + * rights to the materials distributed herewith. Except as + * otherwise provided in a valid license issued to you by + * Xilinx, and to the maximum extent permitted by applicable + * law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND + * WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES + * AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING + * BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- + * INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and + * (2) Xilinx shall not be liable (whether in contract or tort, + * including negligence, or under any other theory of + * liability) for any loss or damage of any kind or nature + * related to, arising under or in connection with these + * materials, including for any direct, or any indirect, + * special, incidental, or consequential loss or damage + * (including loss of data, profits, goodwill, or any type of + * loss or damage suffered as a result of any action brought + * by a third party) even if such damage or loss was + * reasonably foreseeable or Xilinx had been advised of the + * possibility of the same. + * + * CRITICAL APPLICATIONS + * Xilinx products are not designed or intended to be fail- + * safe, or for use in any application requiring fail-safe + * performance, such as life-support or safety devices or + * systems, Class III medical devices, nuclear facilities, + * applications related to the deployment of airbags, or any + * other applications that could lead to death, personal + * injury, or severe property or environmental damage + * (individually and collectively, "Critical + * Applications"). Customer assumes the sole risk and + * liability of any use of Xilinx products in Critical + * Applications, subject only to applicable laws and + * regulations governing limitations on product liability. + * + * THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS + * PART OF THIS FILE AT ALL TIMES. + * + ******************************************************************************* + ******************************************************************************* + * + * Filename: fifo_generator_v5_1_bhv.v + * + * Description: + * The verilog behavioral model for the FIFO generator core. + * + ******************************************************************************* + */ + +`timescale 1ps/1ps + +/******************************************************************************* + * Declaration of top-level module + ******************************************************************************/ +module FIFO_GENERATOR_V5_1_XST + ( + BACKUP, + BACKUP_MARKER, + CLK, + DIN, + PROG_EMPTY_THRESH, + PROG_EMPTY_THRESH_ASSERT, + PROG_EMPTY_THRESH_NEGATE, + PROG_FULL_THRESH, + PROG_FULL_THRESH_ASSERT, + PROG_FULL_THRESH_NEGATE, + RD_CLK, + RD_EN, + RD_RST, + RST, + SRST, + WR_CLK, + WR_EN, + WR_RST, + INT_CLK, + INJECTDBITERR, + INJECTSBITERR, + + ALMOST_EMPTY, + ALMOST_FULL, + DATA_COUNT, + DOUT, + EMPTY, + FULL, + OVERFLOW, + PROG_EMPTY, + PROG_FULL, + RD_DATA_COUNT, + UNDERFLOW, + VALID, + WR_ACK, + WR_DATA_COUNT, + SBITERR, + DBITERR + ); + +/****************************************************************************** + * Definition of Ports + * + * + ***************************************************************************** + * Definition of Parameters + * + * + *****************************************************************************/ + +/****************************************************************************** + * Declare user parameters and their defaults + *****************************************************************************/ + parameter C_COMMON_CLOCK = 0; + parameter C_COUNT_TYPE = 0; + parameter C_DATA_COUNT_WIDTH = 2; + parameter C_DEFAULT_VALUE = ""; + parameter C_DIN_WIDTH = 8; + parameter C_DOUT_RST_VAL = ""; + parameter C_DOUT_WIDTH = 8; + parameter C_ENABLE_RLOCS = 0; + parameter C_FAMILY = "virtex2"; //Not allowed in Verilog model + parameter C_HAS_ALMOST_EMPTY = 0; + parameter C_HAS_ALMOST_FULL = 0; + parameter C_HAS_BACKUP = 0; + parameter C_HAS_DATA_COUNT = 0; + parameter C_HAS_MEMINIT_FILE = 0; + parameter C_HAS_OVERFLOW = 0; + parameter C_HAS_RD_DATA_COUNT = 0; + parameter C_HAS_RD_RST = 0; + parameter C_HAS_RST = 0; + parameter C_HAS_SRST = 0; + parameter C_HAS_UNDERFLOW = 0; + parameter C_HAS_VALID = 0; + parameter C_HAS_WR_ACK = 0; + parameter C_HAS_WR_DATA_COUNT = 0; + parameter C_HAS_WR_RST = 0; + parameter C_IMPLEMENTATION_TYPE = 0; + parameter C_INIT_WR_PNTR_VAL = 0; + parameter C_MEMORY_TYPE = 1; + parameter C_MIF_FILE_NAME = ""; + parameter C_OPTIMIZATION_MODE = 0; + parameter C_OVERFLOW_LOW = 0; + parameter C_PRELOAD_LATENCY = 1; + parameter C_PRELOAD_REGS = 0; + parameter C_PRIM_FIFO_TYPE = ""; + parameter C_PROG_EMPTY_THRESH_ASSERT_VAL = 0; + parameter C_PROG_EMPTY_THRESH_NEGATE_VAL = 0; + parameter C_PROG_EMPTY_TYPE = 0; + parameter C_PROG_FULL_THRESH_ASSERT_VAL = 0; + parameter C_PROG_FULL_THRESH_NEGATE_VAL = 0; + parameter C_PROG_FULL_TYPE = 0; + parameter C_RD_DATA_COUNT_WIDTH = 2; + parameter C_RD_DEPTH = 256; + parameter C_RD_FREQ = 1; + parameter C_RD_PNTR_WIDTH = 8; + parameter C_UNDERFLOW_LOW = 0; + parameter C_USE_DOUT_RST = 0; + parameter C_USE_EMBEDDED_REG = 0; + parameter C_USE_FIFO16_FLAGS = 0; + parameter C_USE_FWFT_DATA_COUNT = 0; + parameter C_VALID_LOW = 0; + parameter C_WR_ACK_LOW = 0; + parameter C_WR_DATA_COUNT_WIDTH = 2; + parameter C_WR_DEPTH = 256; + parameter C_WR_FREQ = 1; + parameter C_WR_PNTR_WIDTH = 8; + parameter C_WR_RESPONSE_LATENCY = 1; + parameter C_USE_ECC = 0; + parameter C_FULL_FLAGS_RST_VAL = 1; + parameter C_HAS_INT_CLK = 0; + parameter C_MSGON_VAL = 1; + parameter C_ENABLE_RST_SYNC = 1; + parameter C_ERROR_INJECTION_TYPE = 0; + + + /****************************************************************************** + * Declare Input and Output Ports + *****************************************************************************/ + input CLK; + input BACKUP; + input BACKUP_MARKER; + input [C_DIN_WIDTH-1:0] DIN; + input [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH; + input [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_ASSERT; + input [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_NEGATE; + input [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH; + input [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_ASSERT; + input [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_NEGATE; + input RD_CLK; + input RD_EN; + input RD_RST; + input RST; + input SRST; + input WR_CLK; + input WR_EN; + input WR_RST; + input INT_CLK; + input INJECTDBITERR; + input INJECTSBITERR; + + output ALMOST_EMPTY; + output ALMOST_FULL; + output [C_DATA_COUNT_WIDTH-1:0] DATA_COUNT; + output [C_DOUT_WIDTH-1:0] DOUT; + output EMPTY; + output FULL; + output OVERFLOW; + output PROG_EMPTY; + output PROG_FULL; + output VALID; + output [C_RD_DATA_COUNT_WIDTH-1:0] RD_DATA_COUNT; + output UNDERFLOW; + output WR_ACK; + output [C_WR_DATA_COUNT_WIDTH-1:0] WR_DATA_COUNT; + output SBITERR; + output DBITERR; + + FIFO_GENERATOR_V5_1 + #( + .C_COMMON_CLOCK (C_COMMON_CLOCK), + .C_COUNT_TYPE (C_COUNT_TYPE), + .C_DATA_COUNT_WIDTH (C_DATA_COUNT_WIDTH), + .C_DEFAULT_VALUE (C_DEFAULT_VALUE), + .C_DIN_WIDTH (C_DIN_WIDTH), + .C_DOUT_RST_VAL (C_DOUT_RST_VAL), + .C_DOUT_WIDTH (C_DOUT_WIDTH), + .C_ENABLE_RLOCS (C_ENABLE_RLOCS), + .C_FAMILY (C_FAMILY),//Not allowed in Verilog model + .C_HAS_ALMOST_EMPTY (C_HAS_ALMOST_EMPTY), + .C_HAS_ALMOST_FULL (C_HAS_ALMOST_FULL), + .C_HAS_BACKUP (C_HAS_BACKUP), + .C_HAS_DATA_COUNT (C_HAS_DATA_COUNT), + .C_HAS_MEMINIT_FILE (C_HAS_MEMINIT_FILE), + .C_HAS_OVERFLOW (C_HAS_OVERFLOW), + .C_HAS_RD_DATA_COUNT (C_HAS_RD_DATA_COUNT), + .C_HAS_RD_RST (C_HAS_RD_RST), + .C_HAS_RST (C_HAS_RST), + .C_HAS_SRST (C_HAS_SRST), + .C_HAS_UNDERFLOW (C_HAS_UNDERFLOW), + .C_HAS_VALID (C_HAS_VALID), + .C_HAS_WR_ACK (C_HAS_WR_ACK), + .C_HAS_WR_DATA_COUNT (C_HAS_WR_DATA_COUNT), + .C_HAS_WR_RST (C_HAS_WR_RST), + .C_IMPLEMENTATION_TYPE (C_IMPLEMENTATION_TYPE), + .C_INIT_WR_PNTR_VAL (C_INIT_WR_PNTR_VAL), + .C_MEMORY_TYPE (C_MEMORY_TYPE), + .C_MIF_FILE_NAME (C_MIF_FILE_NAME), + .C_OPTIMIZATION_MODE (C_OPTIMIZATION_MODE), + .C_OVERFLOW_LOW (C_OVERFLOW_LOW), + .C_PRELOAD_LATENCY (C_PRELOAD_LATENCY), + .C_PRELOAD_REGS (C_PRELOAD_REGS), + .C_PRIM_FIFO_TYPE (C_PRIM_FIFO_TYPE), + .C_PROG_EMPTY_THRESH_ASSERT_VAL (C_PROG_EMPTY_THRESH_ASSERT_VAL), + .C_PROG_EMPTY_THRESH_NEGATE_VAL (C_PROG_EMPTY_THRESH_NEGATE_VAL), + .C_PROG_EMPTY_TYPE (C_PROG_EMPTY_TYPE), + .C_PROG_FULL_THRESH_ASSERT_VAL (C_PROG_FULL_THRESH_ASSERT_VAL), + .C_PROG_FULL_THRESH_NEGATE_VAL (C_PROG_FULL_THRESH_NEGATE_VAL), + .C_PROG_FULL_TYPE (C_PROG_FULL_TYPE), + .C_RD_DATA_COUNT_WIDTH (C_RD_DATA_COUNT_WIDTH), + .C_RD_DEPTH (C_RD_DEPTH), + .C_RD_FREQ (C_RD_FREQ), + .C_RD_PNTR_WIDTH (C_RD_PNTR_WIDTH), + .C_UNDERFLOW_LOW (C_UNDERFLOW_LOW), + .C_USE_DOUT_RST (C_USE_DOUT_RST), + .C_USE_EMBEDDED_REG (C_USE_EMBEDDED_REG), + .C_USE_FIFO16_FLAGS (C_USE_FIFO16_FLAGS), + .C_USE_FWFT_DATA_COUNT (C_USE_FWFT_DATA_COUNT), + .C_VALID_LOW (C_VALID_LOW), + .C_WR_ACK_LOW (C_WR_ACK_LOW), + .C_WR_DATA_COUNT_WIDTH (C_WR_DATA_COUNT_WIDTH), + .C_WR_DEPTH (C_WR_DEPTH), + .C_WR_FREQ (C_WR_FREQ), + .C_WR_PNTR_WIDTH (C_WR_PNTR_WIDTH), + .C_WR_RESPONSE_LATENCY (C_WR_RESPONSE_LATENCY), + .C_USE_ECC (C_USE_ECC), + .C_FULL_FLAGS_RST_VAL (C_FULL_FLAGS_RST_VAL), + .C_HAS_INT_CLK (C_HAS_INT_CLK), + .C_MSGON_VAL (C_MSGON_VAL), + .C_ENABLE_RST_SYNC (C_ENABLE_RST_SYNC), + .C_ERROR_INJECTION_TYPE (C_ERROR_INJECTION_TYPE) + ) + fifo_generator_v5_1_dut + ( + .BACKUP (BACKUP), + .BACKUP_MARKER (BACKUP_MARKER), + .CLK (CLK), + .RST (RST), + .SRST (SRST), + .WR_CLK (WR_CLK), + .WR_RST (WR_RST), + .RD_CLK (RD_CLK), + .RD_RST (RD_RST), + .DIN (DIN), + .WR_EN (WR_EN), + .RD_EN (RD_EN), + .PROG_EMPTY_THRESH (PROG_EMPTY_THRESH), + .PROG_EMPTY_THRESH_ASSERT (PROG_EMPTY_THRESH_ASSERT), + .PROG_EMPTY_THRESH_NEGATE (PROG_EMPTY_THRESH_NEGATE), + .PROG_FULL_THRESH (PROG_FULL_THRESH), + .PROG_FULL_THRESH_ASSERT (PROG_FULL_THRESH_ASSERT), + .PROG_FULL_THRESH_NEGATE (PROG_FULL_THRESH_NEGATE), + .INT_CLK (INT_CLK), + .INJECTDBITERR (INJECTDBITERR), + .INJECTSBITERR (INJECTSBITERR), + + .DOUT (DOUT), + .FULL (FULL), + .ALMOST_FULL (ALMOST_FULL), + .WR_ACK (WR_ACK), + .OVERFLOW (OVERFLOW), + .EMPTY (EMPTY), + .ALMOST_EMPTY (ALMOST_EMPTY), + .VALID (VALID), + .UNDERFLOW (UNDERFLOW), + .DATA_COUNT (DATA_COUNT), + .RD_DATA_COUNT (RD_DATA_COUNT), + .WR_DATA_COUNT (WR_DATA_COUNT), + .PROG_FULL (PROG_FULL), + .PROG_EMPTY (PROG_EMPTY), + .SBITERR (SBITERR), + .DBITERR (DBITERR) + ); + +endmodule diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/FIFO_GENERATOR_V5_2.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/FIFO_GENERATOR_V5_2.v new file mode 100644 index 0000000..3516b73 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/FIFO_GENERATOR_V5_2.v @@ -0,0 +1,4717 @@ +/* + ******************************************************************************* + * + * FIFO Generator - Verilog Behavioral Model + * + ******************************************************************************* + * + * (c) Copyright 1995 - 2009 Xilinx, Inc. All rights reserved. + * + * This file contains confidential and proprietary information + * of Xilinx, Inc. and is protected under U.S. and + * international copyright and other intellectual property + * laws. + * + * DISCLAIMER + * This disclaimer is not a license and does not grant any + * rights to the materials distributed herewith. Except as + * otherwise provided in a valid license issued to you by + * Xilinx, and to the maximum extent permitted by applicable + * law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND + * WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES + * AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING + * BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- + * INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and + * (2) Xilinx shall not be liable (whether in contract or tort, + * including negligence, or under any other theory of + * liability) for any loss or damage of any kind or nature + * related to, arising under or in connection with these + * materials, including for any direct, or any indirect, + * special, incidental, or consequential loss or damage + * (including loss of data, profits, goodwill, or any type of + * loss or damage suffered as a result of any action brought + * by a third party) even if such damage or loss was + * reasonably foreseeable or Xilinx had been advised of the + * possibility of the same. + * + * CRITICAL APPLICATIONS + * Xilinx products are not designed or intended to be fail- + * safe, or for use in any application requiring fail-safe + * performance, such as life-support or safety devices or + * systems, Class III medical devices, nuclear facilities, + * applications related to the deployment of airbags, or any + * other applications that could lead to death, personal + * injury, or severe property or environmental damage + * (individually and collectively, "Critical + * Applications"). Customer assumes the sole risk and + * liability of any use of Xilinx products in Critical + * Applications, subject only to applicable laws and + * regulations governing limitations on product liability. + * + * THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS + * PART OF THIS FILE AT ALL TIMES. + * + ******************************************************************************* + ******************************************************************************* + * + * Filename: FIFO_GENERATOR_V5_2.v + * + * Author : Xilinx + * + ******************************************************************************* + * Structure: + * + * fifo_generator_v5_2.vhd + * | + * +-fifo_generator_v5_2_bhv_ver_as + * | + * +-fifo_generator_v5_2_bhv_ver_ss + * | + * +-fifo_generator_v5_2_bhv_preload0 + * + ******************************************************************************* + * Description: + * + * The Verilog behavioral model for the FIFO Generator. + * + * The behavioral model has three parts: + * - The behavioral model for independent clocks FIFOs (_as) + * - The behavioral model for common clock FIFOs (_ss) + * - The "preload logic" block which implements First-word Fall-through + * + ******************************************************************************* + * Description: + * The verilog behavioral model for the FIFO generator core. + * + ******************************************************************************* + */ + +`timescale 1ps/1ps +`ifndef TCQ + `define TCQ 100 +`endif + + +/******************************************************************************* + * Declaration of top-level module + ******************************************************************************/ +module FIFO_GENERATOR_V5_2 +( + BACKUP, //not used + BACKUP_MARKER, //not used + CLK, + DIN, + PROG_EMPTY_THRESH, + PROG_EMPTY_THRESH_ASSERT, + PROG_EMPTY_THRESH_NEGATE, + PROG_FULL_THRESH, + PROG_FULL_THRESH_ASSERT, + PROG_FULL_THRESH_NEGATE, + RD_CLK, + RD_EN, + RD_RST, + RST, + SRST, + WR_CLK, + WR_EN, + WR_RST, + INT_CLK, + INJECTDBITERR, + INJECTSBITERR, + + ALMOST_EMPTY, + ALMOST_FULL, + DATA_COUNT, + DOUT, + EMPTY, + FULL, + OVERFLOW, + PROG_EMPTY, + PROG_FULL, + RD_DATA_COUNT, + UNDERFLOW, + VALID, + WR_ACK, + WR_DATA_COUNT, + + SBITERR, + DBITERR + ); + +/* + ****************************************************************************** + * Definition of Parameters + ****************************************************************************** + * C_COMMON_CLOCK : Common Clock (1), Independent Clocks (0) + * C_COUNT_TYPE : *not used + * C_DATA_COUNT_WIDTH : Width of DATA_COUNT bus + * C_DEFAULT_VALUE : *not used + * C_DIN_WIDTH : Width of DIN bus + * C_DOUT_RST_VAL : Reset value of DOUT + * C_DOUT_WIDTH : Width of DOUT bus + * C_ENABLE_RLOCS : *not used + * C_FAMILY : not used in bhv model + * C_FULL_FLAGS_RST_VAL : Full flags rst val (0 or 1) + * C_HAS_ALMOST_EMPTY : 1=Core has ALMOST_EMPTY flag + * C_HAS_ALMOST_FULL : 1=Core has ALMOST_FULL flag + * C_HAS_BACKUP : *not used + * C_HAS_DATA_COUNT : 1=Core has DATA_COUNT bus + * C_HAS_INT_CLK : not used in bhv model + * C_HAS_MEMINIT_FILE : *not used + * C_HAS_OVERFLOW : 1=Core has OVERFLOW flag + * C_HAS_RD_DATA_COUNT : 1=Core has RD_DATA_COUNT bus + * C_HAS_RD_RST : *not used + * C_HAS_RST : 1=Core has Async Rst + * C_HAS_SRST : 1=Core has Sync Rst + * C_HAS_UNDERFLOW : 1=Core has UNDERFLOW flag + * C_HAS_VALID : 1=Core has VALID flag + * C_HAS_WR_ACK : 1=Core has WR_ACK flag + * C_HAS_WR_DATA_COUNT : 1=Core has WR_DATA_COUNT bus + * C_HAS_WR_RST : *not used + * C_IMPLEMENTATION_TYPE : 0=Common-Clock Bram/Dram + * 1=Common-Clock ShiftRam + * 2=Indep. Clocks Bram/Dram + * 3=Virtex-4 Built-in + * 4=Virtex-5 Built-in + * C_INIT_WR_PNTR_VAL : *not used + * C_MEMORY_TYPE : 1=Block RAM + * 2=Distributed RAM + * 3=Shift RAM + * 4=Built-in FIFO + * C_MIF_FILE_NAME : *not used + * C_OPTIMIZATION_MODE : *not used + * C_OVERFLOW_LOW : 1=OVERFLOW active low + * C_PRELOAD_LATENCY : Latency of read: 0, 1, 2 + * C_PRELOAD_REGS : 1=Use output registers + * C_PRIM_FIFO_TYPE : not used in bhv model + * C_PROG_EMPTY_THRESH_ASSERT_VAL: PROG_EMPTY assert threshold + * C_PROG_EMPTY_THRESH_NEGATE_VAL: PROG_EMPTY negate threshold + * C_PROG_EMPTY_TYPE : 0=No programmable empty + * 1=Single prog empty thresh constant + * 2=Multiple prog empty thresh constants + * 3=Single prog empty thresh input + * 4=Multiple prog empty thresh inputs + * C_PROG_FULL_THRESH_ASSERT_VAL : PROG_FULL assert threshold + * C_PROG_FULL_THRESH_NEGATE_VAL : PROG_FULL negate threshold + * C_PROG_FULL_TYPE : 0=No prog full + * 1=Single prog full thresh constant + * 2=Multiple prog full thresh constants + * 3=Single prog full thresh input + * 4=Multiple prog full thresh inputs + * C_RD_DATA_COUNT_WIDTH : Width of RD_DATA_COUNT bus + * C_RD_DEPTH : Depth of read interface (2^N) + * C_RD_FREQ : not used in bhv model + * C_RD_PNTR_WIDTH : always log2(C_RD_DEPTH) + * C_UNDERFLOW_LOW : 1=UNDERFLOW active low + * C_USE_DOUT_RST : 1=Resets DOUT on RST + * C_USE_ECC : Used for error injection purpose + * C_USE_EMBEDDED_REG : 1=Use BRAM embedded output register + * C_USE_FIFO16_FLAGS : not used in bhv model + * C_USE_FWFT_DATA_COUNT : 1=Use extra logic for FWFT data count + * C_VALID_LOW : 1=VALID active low + * C_WR_ACK_LOW : 1=WR_ACK active low + * C_WR_DATA_COUNT_WIDTH : Width of WR_DATA_COUNT bus + * C_WR_DEPTH : Depth of write interface (2^N) + * C_WR_FREQ : not used in bhv model + * C_WR_PNTR_WIDTH : always log2(C_WR_DEPTH) + * C_WR_RESPONSE_LATENCY : *not used + * C_MSGON_VAL : *not used by bhv model + * C_ENABLE_RST_SYNC : 0 = Use WR_RST & RD_RST + * 1 = Use RST + * C_ERROR_INJECTION_TYPE : 0 = No error injection + * 1 = Single bit error injection only + * 2 = Double bit error injection only + * 1 = Single and double bit error injection + ****************************************************************************** + * Definition of Ports + ****************************************************************************** + * BACKUP : Not used + * BACKUP_MARKER: Not used + * CLK : Clock + * DIN : Input data bus + * PROG_EMPTY_THRESH : Threshold for Programmable Empty Flag + * PROG_EMPTY_THRESH_ASSERT: Threshold for Programmable Empty Flag + * PROG_EMPTY_THRESH_NEGATE: Threshold for Programmable Empty Flag + * PROG_FULL_THRESH : Threshold for Programmable Full Flag + * PROG_FULL_THRESH_ASSERT : Threshold for Programmable Full Flag + * PROG_FULL_THRESH_NEGATE : Threshold for Programmable Full Flag + * RD_CLK : Read Domain Clock + * RD_EN : Read enable + * RD_RST : Read Reset + * RST : Asynchronous Reset + * SRST : Synchronous Reset + * WR_CLK : Write Domain Clock + * WR_EN : Write enable + * WR_RST : Write Reset + * INT_CLK : Internal Clock + * INJECTSBITERR: Inject Signle bit error + * INJECTDBITERR: Inject Double bit error + * ALMOST_EMPTY : One word remaining in FIFO + * ALMOST_FULL : One empty space remaining in FIFO + * DATA_COUNT : Number of data words in fifo( synchronous to CLK) + * DOUT : Output data bus + * EMPTY : Empty flag + * FULL : Full flag + * OVERFLOW : Last write rejected + * PROG_EMPTY : Programmable Empty Flag + * PROG_FULL : Programmable Full Flag + * RD_DATA_COUNT: Number of data words in fifo (synchronous to RD_CLK) + * UNDERFLOW : Last read rejected + * VALID : Last read acknowledged, DOUT bus VALID + * WR_ACK : Last write acknowledged + * WR_DATA_COUNT: Number of data words in fifo (synchronous to WR_CLK) + * SBITERR : Single Bit ECC Error Detected + * DBITERR : Double Bit ECC Error Detected + ****************************************************************************** + */ + + + /**************************************************************************** + * Declare user parameters and their defaults + *****************************************************************************/ + parameter C_COMMON_CLOCK = 0; + parameter C_COUNT_TYPE = 0; //not used + parameter C_DATA_COUNT_WIDTH = 2; + parameter C_DEFAULT_VALUE = ""; //not used + parameter C_DIN_WIDTH = 8; + parameter C_DOUT_RST_VAL = ""; + parameter C_DOUT_WIDTH = 8; + parameter C_ENABLE_RLOCS = 0; //not used + parameter C_FAMILY = "virtex2"; //not used in bhv model + parameter C_FULL_FLAGS_RST_VAL = 1; + parameter C_HAS_ALMOST_EMPTY = 0; + parameter C_HAS_ALMOST_FULL = 0; + parameter C_HAS_BACKUP = 0; //not used + parameter C_HAS_DATA_COUNT = 0; + parameter C_HAS_INT_CLK = 0; //not used in bhv model + parameter C_HAS_MEMINIT_FILE = 0; //not used + parameter C_HAS_OVERFLOW = 0; + parameter C_HAS_RD_DATA_COUNT = 0; + parameter C_HAS_RD_RST = 0; //not used + parameter C_HAS_RST = 0; + parameter C_HAS_SRST = 0; + parameter C_HAS_UNDERFLOW = 0; + parameter C_HAS_VALID = 0; + parameter C_HAS_WR_ACK = 0; + parameter C_HAS_WR_DATA_COUNT = 0; + parameter C_HAS_WR_RST = 0; //not used + parameter C_IMPLEMENTATION_TYPE = 0; + parameter C_INIT_WR_PNTR_VAL = 0; //not used + parameter C_MEMORY_TYPE = 1; + parameter C_MIF_FILE_NAME = ""; //not used + parameter C_OPTIMIZATION_MODE = 0; //not used + parameter C_OVERFLOW_LOW = 0; + parameter C_PRELOAD_LATENCY = 1; + parameter C_PRELOAD_REGS = 0; + parameter C_PRIM_FIFO_TYPE = ""; //not used in bhv model + parameter C_PROG_EMPTY_THRESH_ASSERT_VAL = 0; + parameter C_PROG_EMPTY_THRESH_NEGATE_VAL = 0; + parameter C_PROG_EMPTY_TYPE = 0; + parameter C_PROG_FULL_THRESH_ASSERT_VAL = 0; + parameter C_PROG_FULL_THRESH_NEGATE_VAL = 0; + parameter C_PROG_FULL_TYPE = 0; + parameter C_RD_DATA_COUNT_WIDTH = 2; + parameter C_RD_DEPTH = 256; + parameter C_RD_FREQ = 1; //not used in bhv model + parameter C_RD_PNTR_WIDTH = 8; + parameter C_UNDERFLOW_LOW = 0; + parameter C_USE_DOUT_RST = 0; + parameter C_USE_ECC = 0; //not used in bhv model + parameter C_USE_EMBEDDED_REG = 0; + parameter C_USE_FIFO16_FLAGS = 0; //not used in bhv model + parameter C_USE_FWFT_DATA_COUNT = 0; + parameter C_VALID_LOW = 0; + parameter C_WR_ACK_LOW = 0; + parameter C_WR_DATA_COUNT_WIDTH = 2; + parameter C_WR_DEPTH = 256; + parameter C_WR_FREQ = 1; //not used in bhv model + parameter C_WR_PNTR_WIDTH = 8; + parameter C_WR_RESPONSE_LATENCY = 1; //not used + parameter C_MSGON_VAL = 1; //not used + parameter C_ENABLE_RST_SYNC = 1; + parameter C_ERROR_INJECTION_TYPE = 0; + + + + /***************************************************************************** + * Derived parameters + ****************************************************************************/ + //There are 2 Verilog behavioral models + // 0 = Common-Clock FIFO/ShiftRam FIFO + // 1 = Independent Clocks FIFO + parameter C_VERILOG_IMPL = (C_IMPLEMENTATION_TYPE==0 ? 0 : + (C_IMPLEMENTATION_TYPE==1 ? 0 : + (C_IMPLEMENTATION_TYPE==2 ? 1 : 0))); + + /***************************************************************************** + * Declare Input and Output Ports + ****************************************************************************/ + input CLK; + input BACKUP; + input BACKUP_MARKER; + input [C_DIN_WIDTH-1:0] DIN; + input [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH; + input [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_ASSERT; + input [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_NEGATE; + input [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH; + input [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_ASSERT; + input [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_NEGATE; + input RD_CLK; + input RD_EN; + input RD_RST; + input RST; + input SRST; + input WR_CLK; + input WR_EN; + input WR_RST; + input INT_CLK; + input INJECTDBITERR; + input INJECTSBITERR; + + output ALMOST_EMPTY; + output ALMOST_FULL; + output [C_DATA_COUNT_WIDTH-1:0] DATA_COUNT; + output [C_DOUT_WIDTH-1:0] DOUT; + output EMPTY; + output FULL; + output OVERFLOW; + output PROG_EMPTY; + output PROG_FULL; + output VALID; + output [C_RD_DATA_COUNT_WIDTH-1:0] RD_DATA_COUNT; + output UNDERFLOW; + output WR_ACK; + output [C_WR_DATA_COUNT_WIDTH-1:0] WR_DATA_COUNT; + output SBITERR; + output DBITERR; + + + wire ALMOST_EMPTY; + wire ALMOST_FULL; + wire [C_DATA_COUNT_WIDTH-1:0] DATA_COUNT; + wire [C_DOUT_WIDTH-1:0] DOUT; + wire EMPTY; + wire FULL; + wire OVERFLOW; + wire PROG_EMPTY; + wire PROG_FULL; + wire VALID; + wire [C_RD_DATA_COUNT_WIDTH-1:0] RD_DATA_COUNT; + wire UNDERFLOW; + wire WR_ACK; + wire [C_WR_DATA_COUNT_WIDTH-1:0] WR_DATA_COUNT; + + + wire RD_CLK_P0_IN; + wire RST_P0_IN; + wire RD_EN_FIFO_IN; + wire RD_EN_P0_IN; + + wire ALMOST_EMPTY_FIFO_OUT; + wire ALMOST_FULL_FIFO_OUT; + wire [C_DATA_COUNT_WIDTH-1:0] DATA_COUNT_FIFO_OUT; + wire [C_DOUT_WIDTH-1:0] DOUT_FIFO_OUT; + wire EMPTY_FIFO_OUT; + wire FULL_FIFO_OUT; + wire OVERFLOW_FIFO_OUT; + wire PROG_EMPTY_FIFO_OUT; + wire PROG_FULL_FIFO_OUT; + wire VALID_FIFO_OUT; + wire [C_RD_DATA_COUNT_WIDTH-1:0] RD_DATA_COUNT_FIFO_OUT; + wire UNDERFLOW_FIFO_OUT; + wire WR_ACK_FIFO_OUT; + wire [C_WR_DATA_COUNT_WIDTH-1:0] WR_DATA_COUNT_FIFO_OUT; + + + //*************************************************************************** + // Internal Signals + // The core uses either the internal_ wires or the preload0_ wires depending + // on whether the core uses Preload0 or not. + // When using preload0, the internal signals connect the internal core to + // the preload logic, and the external core's interfaces are tied to the + // preload0 signals from the preload logic. + //*************************************************************************** + wire [C_DOUT_WIDTH-1:0] DATA_P0_OUT; + wire VALID_P0_OUT; + wire EMPTY_P0_OUT; + wire ALMOSTEMPTY_P0_OUT; + reg EMPTY_P0_OUT_Q; + reg ALMOSTEMPTY_P0_OUT_Q; + wire UNDERFLOW_P0_OUT; + wire RDEN_P0_OUT; + wire [C_DOUT_WIDTH-1:0] DATA_P0_IN; + wire EMPTY_P0_IN; + reg [31:0] DATA_COUNT_FWFT; + reg SS_FWFT_WR ; + reg SS_FWFT_RD ; + + wire SBITERR; + wire DBITERR; + wire sbiterr_fifo_out; + wire dbiterr_fifo_out; + + +// Choose the behavioral model to instantiate based on the C_VERILOG_IMPL +// parameter (1=Independent Clocks, 0=Common Clock) +generate +case (C_VERILOG_IMPL) +0 : begin : block1 + //Common Clock Behavioral Model + fifo_generator_v5_2_bhv_ver_ss + #( + C_DATA_COUNT_WIDTH, + C_DIN_WIDTH, + C_DOUT_RST_VAL, + C_DOUT_WIDTH, + C_FULL_FLAGS_RST_VAL, + C_HAS_ALMOST_EMPTY, + C_HAS_ALMOST_FULL, + C_HAS_DATA_COUNT, + C_HAS_OVERFLOW, + C_HAS_RD_DATA_COUNT, + C_HAS_RST, + C_HAS_SRST, + C_HAS_UNDERFLOW, + C_HAS_VALID, + C_HAS_WR_ACK, + C_HAS_WR_DATA_COUNT, + C_IMPLEMENTATION_TYPE, + C_MEMORY_TYPE, + C_OVERFLOW_LOW, + C_PRELOAD_LATENCY, + C_PRELOAD_REGS, + C_PROG_EMPTY_THRESH_ASSERT_VAL, + C_PROG_EMPTY_THRESH_NEGATE_VAL, + C_PROG_EMPTY_TYPE, + C_PROG_FULL_THRESH_ASSERT_VAL, + C_PROG_FULL_THRESH_NEGATE_VAL, + C_PROG_FULL_TYPE, + C_RD_DATA_COUNT_WIDTH, + C_RD_DEPTH, + C_RD_PNTR_WIDTH, + C_UNDERFLOW_LOW, + C_USE_DOUT_RST, + C_USE_EMBEDDED_REG, + C_USE_FWFT_DATA_COUNT, + C_VALID_LOW, + C_WR_ACK_LOW, + C_WR_DATA_COUNT_WIDTH, + C_WR_DEPTH, + C_WR_PNTR_WIDTH, + C_USE_ECC, + C_ENABLE_RST_SYNC, + C_ERROR_INJECTION_TYPE + ) + gen_ss + ( + .CLK (CLK), + .RST (RST), + .SRST (SRST), + .DIN (DIN), + .WR_EN (WR_EN), + .RD_EN (RD_EN_FIFO_IN), + .PROG_EMPTY_THRESH (PROG_EMPTY_THRESH), + .PROG_EMPTY_THRESH_ASSERT (PROG_EMPTY_THRESH_ASSERT), + .PROG_EMPTY_THRESH_NEGATE (PROG_EMPTY_THRESH_NEGATE), + .PROG_FULL_THRESH (PROG_FULL_THRESH), + .PROG_FULL_THRESH_ASSERT (PROG_FULL_THRESH_ASSERT), + .PROG_FULL_THRESH_NEGATE (PROG_FULL_THRESH_NEGATE), + .INJECTSBITERR (INJECTSBITERR), + .INJECTDBITERR (INJECTDBITERR), + .DOUT (DOUT_FIFO_OUT), + .FULL (FULL_FIFO_OUT), + .ALMOST_FULL (ALMOST_FULL_FIFO_OUT), + .WR_ACK (WR_ACK_FIFO_OUT), + .OVERFLOW (OVERFLOW_FIFO_OUT), + .EMPTY (EMPTY_FIFO_OUT), + .ALMOST_EMPTY (ALMOST_EMPTY_FIFO_OUT), + .VALID (VALID_FIFO_OUT), + .UNDERFLOW (UNDERFLOW_FIFO_OUT), + .DATA_COUNT (DATA_COUNT_FIFO_OUT), + .PROG_FULL (PROG_FULL_FIFO_OUT), + .PROG_EMPTY (PROG_EMPTY_FIFO_OUT), + .SBITERR (sbiterr_fifo_out), + .DBITERR (dbiterr_fifo_out) + ); +end +1 : begin : block1 + //Independent Clocks Behavioral Model + fifo_generator_v5_2_bhv_ver_as + #( + C_DATA_COUNT_WIDTH, + C_DIN_WIDTH, + C_DOUT_RST_VAL, + C_DOUT_WIDTH, + C_FULL_FLAGS_RST_VAL, + C_HAS_ALMOST_EMPTY, + C_HAS_ALMOST_FULL, + C_HAS_DATA_COUNT, + C_HAS_OVERFLOW, + C_HAS_RD_DATA_COUNT, + C_HAS_RST, + C_HAS_UNDERFLOW, + C_HAS_VALID, + C_HAS_WR_ACK, + C_HAS_WR_DATA_COUNT, + C_IMPLEMENTATION_TYPE, + C_MEMORY_TYPE, + C_OVERFLOW_LOW, + C_PRELOAD_LATENCY, + C_PRELOAD_REGS, + C_PROG_EMPTY_THRESH_ASSERT_VAL, + C_PROG_EMPTY_THRESH_NEGATE_VAL, + C_PROG_EMPTY_TYPE, + C_PROG_FULL_THRESH_ASSERT_VAL, + C_PROG_FULL_THRESH_NEGATE_VAL, + C_PROG_FULL_TYPE, + C_RD_DATA_COUNT_WIDTH, + C_RD_DEPTH, + C_RD_PNTR_WIDTH, + C_UNDERFLOW_LOW, + C_USE_DOUT_RST, + C_USE_EMBEDDED_REG, + C_USE_FWFT_DATA_COUNT, + C_VALID_LOW, + C_WR_ACK_LOW, + C_WR_DATA_COUNT_WIDTH, + C_WR_DEPTH, + C_WR_PNTR_WIDTH, + C_USE_ECC, + C_ENABLE_RST_SYNC, + C_ERROR_INJECTION_TYPE + ) + gen_as + ( + .WR_CLK (WR_CLK), + .RD_CLK (RD_CLK), + .RST (RST), + .WR_RST (WR_RST), + .RD_RST (RD_RST), + .DIN (DIN), + .WR_EN (WR_EN), + .RD_EN (RD_EN_FIFO_IN), + .PROG_EMPTY_THRESH (PROG_EMPTY_THRESH), + .PROG_EMPTY_THRESH_ASSERT (PROG_EMPTY_THRESH_ASSERT), + .PROG_EMPTY_THRESH_NEGATE (PROG_EMPTY_THRESH_NEGATE), + .PROG_FULL_THRESH (PROG_FULL_THRESH), + .PROG_FULL_THRESH_ASSERT (PROG_FULL_THRESH_ASSERT), + .PROG_FULL_THRESH_NEGATE (PROG_FULL_THRESH_NEGATE), + .INJECTSBITERR (INJECTSBITERR), + .INJECTDBITERR (INJECTDBITERR), + .DOUT (DOUT_FIFO_OUT), + .FULL (FULL_FIFO_OUT), + .ALMOST_FULL (ALMOST_FULL_FIFO_OUT), + .WR_ACK (WR_ACK_FIFO_OUT), + .OVERFLOW (OVERFLOW_FIFO_OUT), + .EMPTY (EMPTY_FIFO_OUT), + .ALMOST_EMPTY (ALMOST_EMPTY_FIFO_OUT), + .VALID (VALID_FIFO_OUT), + .UNDERFLOW (UNDERFLOW_FIFO_OUT), + .RD_DATA_COUNT (RD_DATA_COUNT_FIFO_OUT), + .WR_DATA_COUNT (WR_DATA_COUNT_FIFO_OUT), + .PROG_FULL (PROG_FULL_FIFO_OUT), + .PROG_EMPTY (PROG_EMPTY_FIFO_OUT), + .SBITERR (sbiterr_fifo_out), + .DBITERR (dbiterr_fifo_out) + ); +end + +default : begin : block1 + //Independent Clocks Behavioral Model + fifo_generator_v5_2_bhv_ver_as + #( + C_DATA_COUNT_WIDTH, + C_DIN_WIDTH, + C_DOUT_RST_VAL, + C_DOUT_WIDTH, + C_FULL_FLAGS_RST_VAL, + C_HAS_ALMOST_EMPTY, + C_HAS_ALMOST_FULL, + C_HAS_DATA_COUNT, + C_HAS_OVERFLOW, + C_HAS_RD_DATA_COUNT, + C_HAS_RST, + C_HAS_UNDERFLOW, + C_HAS_VALID, + C_HAS_WR_ACK, + C_HAS_WR_DATA_COUNT, + C_IMPLEMENTATION_TYPE, + C_MEMORY_TYPE, + C_OVERFLOW_LOW, + C_PRELOAD_LATENCY, + C_PRELOAD_REGS, + C_PROG_EMPTY_THRESH_ASSERT_VAL, + C_PROG_EMPTY_THRESH_NEGATE_VAL, + C_PROG_EMPTY_TYPE, + C_PROG_FULL_THRESH_ASSERT_VAL, + C_PROG_FULL_THRESH_NEGATE_VAL, + C_PROG_FULL_TYPE, + C_RD_DATA_COUNT_WIDTH, + C_RD_DEPTH, + C_RD_PNTR_WIDTH, + C_UNDERFLOW_LOW, + C_USE_DOUT_RST, + C_USE_EMBEDDED_REG, + C_USE_FWFT_DATA_COUNT, + C_VALID_LOW, + C_WR_ACK_LOW, + C_WR_DATA_COUNT_WIDTH, + C_WR_DEPTH, + C_WR_PNTR_WIDTH, + C_USE_ECC, + C_ENABLE_RST_SYNC, + C_ERROR_INJECTION_TYPE + ) + gen_as + ( + .WR_CLK (WR_CLK), + .RD_CLK (RD_CLK), + .RST (RST), + .WR_RST (WR_RST), + .RD_RST (RD_RST), + .DIN (DIN), + .WR_EN (WR_EN), + .RD_EN (RD_EN_FIFO_IN), + .PROG_EMPTY_THRESH (PROG_EMPTY_THRESH), + .PROG_EMPTY_THRESH_ASSERT (PROG_EMPTY_THRESH_ASSERT), + .PROG_EMPTY_THRESH_NEGATE (PROG_EMPTY_THRESH_NEGATE), + .PROG_FULL_THRESH (PROG_FULL_THRESH), + .PROG_FULL_THRESH_ASSERT (PROG_FULL_THRESH_ASSERT), + .PROG_FULL_THRESH_NEGATE (PROG_FULL_THRESH_NEGATE), + .INJECTSBITERR (INJECTSBITERR), + .INJECTDBITERR (INJECTDBITERR), + .DOUT (DOUT_FIFO_OUT), + .FULL (FULL_FIFO_OUT), + .ALMOST_FULL (ALMOST_FULL_FIFO_OUT), + .WR_ACK (WR_ACK_FIFO_OUT), + .OVERFLOW (OVERFLOW_FIFO_OUT), + .EMPTY (EMPTY_FIFO_OUT), + .ALMOST_EMPTY (ALMOST_EMPTY_FIFO_OUT), + .VALID (VALID_FIFO_OUT), + .UNDERFLOW (UNDERFLOW_FIFO_OUT), + .RD_DATA_COUNT (RD_DATA_COUNT_FIFO_OUT), + .WR_DATA_COUNT (WR_DATA_COUNT_FIFO_OUT), + .PROG_FULL (PROG_FULL_FIFO_OUT), + .PROG_EMPTY (PROG_EMPTY_FIFO_OUT), + .SBITERR (sbiterr_fifo_out), + .DBITERR (dbiterr_fifo_out) + ); +end + +endcase +endgenerate + + + //************************************************************************** + // Connect Internal Signals + // (Signals labeled internal_*) + // In the normal case, these signals tie directly to the FIFO's inputs and + // outputs. + // In the case of Preload Latency 0 or 1, there are intermediate + // signals between the internal FIFO and the preload logic. + //************************************************************************** + + + //*********************************************** + // If First-Word Fall-Through, instantiate + // the preload0 (FWFT) module + //*********************************************** + generate + if (C_PRELOAD_REGS==1 && C_PRELOAD_LATENCY==0) begin : block2 + + + fifo_generator_v5_2_bhv_ver_preload0 + #( + C_DOUT_RST_VAL, + C_DOUT_WIDTH, + C_HAS_RST, + C_ENABLE_RST_SYNC, + C_HAS_SRST, + C_USE_DOUT_RST, + C_VALID_LOW, + C_UNDERFLOW_LOW + ) + fgpl0 + ( + .RD_CLK (RD_CLK_P0_IN), + .RD_RST (RST_P0_IN), + .SRST (SRST), + .RD_EN (RD_EN_P0_IN), + .FIFOEMPTY (EMPTY_P0_IN), + .FIFODATA (DATA_P0_IN), + .FIFOSBITERR (sbiterr_fifo_out), + .FIFODBITERR (dbiterr_fifo_out), + .USERDATA (DATA_P0_OUT), + .USERVALID (VALID_P0_OUT), + .USEREMPTY (EMPTY_P0_OUT), + .USERALMOSTEMPTY (ALMOSTEMPTY_P0_OUT), + .USERUNDERFLOW (UNDERFLOW_P0_OUT), + .RAMVALID (RAMVALID_P0_OUT), + .FIFORDEN (RDEN_P0_OUT), + .USERSBITERR (SBITERR), + .USERDBITERR (DBITERR) + ); + + + //*********************************************** + // Connect inputs to preload (FWFT) module + //*********************************************** + //Connect the RD_CLK of the Preload (FWFT) module to CLK if we + // have a common-clock FIFO, or RD_CLK if we have an + // independent clock FIFO + assign RD_CLK_P0_IN = ((C_VERILOG_IMPL == 0) ? CLK : RD_CLK); + assign RST_P0_IN = (C_ENABLE_RST_SYNC == 0) ? RD_RST : RST; + assign RD_EN_P0_IN = RD_EN; + assign EMPTY_P0_IN = EMPTY_FIFO_OUT; + assign DATA_P0_IN = DOUT_FIFO_OUT; + + //*********************************************** + // Connect outputs from preload (FWFT) module + //*********************************************** + assign DOUT = DATA_P0_OUT; + assign VALID = VALID_P0_OUT ; + assign EMPTY = EMPTY_P0_OUT; + assign ALMOST_EMPTY = ALMOSTEMPTY_P0_OUT; + assign UNDERFLOW = UNDERFLOW_P0_OUT ; + + assign RD_EN_FIFO_IN = RDEN_P0_OUT; + + + //*********************************************** + // Create DATA_COUNT from First-Word Fall-Through + // data count + //*********************************************** + assign DATA_COUNT = (C_USE_FWFT_DATA_COUNT == 0)? DATA_COUNT_FIFO_OUT: + (C_DATA_COUNT_WIDTH>C_RD_PNTR_WIDTH) ? DATA_COUNT_FWFT[C_RD_PNTR_WIDTH:0] : + DATA_COUNT_FWFT[C_RD_PNTR_WIDTH:C_RD_PNTR_WIDTH-C_DATA_COUNT_WIDTH+1]; + + //*********************************************** + // Create DATA_COUNT from First-Word Fall-Through + // data count + //*********************************************** + always @ (posedge RD_CLK or posedge RST_P0_IN) begin + if (RST_P0_IN) begin + EMPTY_P0_OUT_Q <= #`TCQ 1; + ALMOSTEMPTY_P0_OUT_Q <= #`TCQ 1; + end else begin + EMPTY_P0_OUT_Q <= #`TCQ EMPTY_P0_OUT; + ALMOSTEMPTY_P0_OUT_Q <= #`TCQ ALMOSTEMPTY_P0_OUT; + end + end //always + + + //*********************************************** + // logic for common-clock data count when FWFT is selected + //*********************************************** + initial begin + SS_FWFT_RD = 1'b0; + DATA_COUNT_FWFT = 0 ; + SS_FWFT_WR = 1'b0 ; + end //initial + + + //*********************************************** + // common-clock data count is implemented as an + // up-down counter. SS_FWFT_WR and SS_FWFT_RD + // are the up/down enables for the counter. + //*********************************************** + always @ (RD_EN or VALID_P0_OUT or WR_EN or FULL_FIFO_OUT) begin + if (C_VALID_LOW == 1) begin + SS_FWFT_RD = RD_EN && ~VALID_P0_OUT ; + end else begin + SS_FWFT_RD = RD_EN && VALID_P0_OUT ; + end + SS_FWFT_WR = (WR_EN && (~FULL_FIFO_OUT)) ; + end + + //*********************************************** + // common-clock data count is implemented as an + // up-down counter for FWFT. This always block + // calculates the counter. + //*********************************************** + always @ (posedge RD_CLK_P0_IN or posedge RST_P0_IN) begin + if (RST_P0_IN) begin + DATA_COUNT_FWFT <= #`TCQ 0; + end else begin + if (SRST && (C_HAS_SRST == 1) ) begin + DATA_COUNT_FWFT <= #`TCQ 0; + end else begin + case ( {SS_FWFT_WR, SS_FWFT_RD}) + 2'b00: DATA_COUNT_FWFT <= #`TCQ DATA_COUNT_FWFT ; + 2'b01: DATA_COUNT_FWFT <= #`TCQ DATA_COUNT_FWFT - 1 ; + 2'b10: DATA_COUNT_FWFT <= #`TCQ DATA_COUNT_FWFT + 1 ; + 2'b11: DATA_COUNT_FWFT <= #`TCQ DATA_COUNT_FWFT ; + endcase + end //if SRST + end //IF RST + end //always + + + end else begin : block2 //if !(C_PRELOAD_REGS==1 && C_PRELOAD_LATENCY==0) + + //*********************************************** + // If NOT First-Word Fall-Through, wire the outputs + // of the internal _ss or _as FIFO directly to the + // output, and do not instantiate the preload0 + // module. + //*********************************************** + + assign RD_CLK_P0_IN = 0; + assign RST_P0_IN = 0; + assign RD_EN_P0_IN = 0; + + assign RD_EN_FIFO_IN = RD_EN; + + assign DOUT = DOUT_FIFO_OUT; + assign DATA_P0_IN = 0; + assign VALID = VALID_FIFO_OUT; + assign EMPTY = EMPTY_FIFO_OUT; + assign ALMOST_EMPTY = ALMOST_EMPTY_FIFO_OUT; + assign EMPTY_P0_IN = 0; + assign UNDERFLOW = UNDERFLOW_FIFO_OUT; + assign DATA_COUNT = DATA_COUNT_FIFO_OUT; + assign SBITERR = sbiterr_fifo_out; + assign DBITERR = dbiterr_fifo_out; + + end //if !(C_PRELOAD_REGS==1 && C_PRELOAD_LATENCY==0) + endgenerate + + + //*********************************************** + // Connect user flags to internal signals + //*********************************************** + + //If we are using extra logic for the FWFT data count, then override the + //RD_DATA_COUNT output when we are EMPTY or ALMOST_EMPTY. + //RD_DATA_COUNT is 0 when EMPTY and 1 when ALMOST_EMPTY. + generate + if (C_USE_FWFT_DATA_COUNT==1 && (C_RD_DATA_COUNT_WIDTH>C_RD_PNTR_WIDTH) ) begin : block3 + assign RD_DATA_COUNT = (EMPTY_P0_OUT_Q | RST_P0_IN) ? 0 : (ALMOSTEMPTY_P0_OUT_Q ? 1 : RD_DATA_COUNT_FIFO_OUT); + end //block3 + endgenerate + + //If we are using extra logic for the FWFT data count, then override the + //RD_DATA_COUNT output when we are EMPTY or ALMOST_EMPTY. + //Due to asymmetric ports, RD_DATA_COUNT is 0 when EMPTY or ALMOST_EMPTY. + generate + if (C_USE_FWFT_DATA_COUNT==1 && (C_RD_DATA_COUNT_WIDTH <=C_RD_PNTR_WIDTH) ) begin : block30 + assign RD_DATA_COUNT = (EMPTY_P0_OUT_Q | RST_P0_IN) ? 0 : (ALMOSTEMPTY_P0_OUT_Q ? 0 : RD_DATA_COUNT_FIFO_OUT); + end //block30 + endgenerate + + //If we are not using extra logic for the FWFT data count, + //then connect RD_DATA_COUNT to the RD_DATA_COUNT from the + //internal FIFO instance + generate + if (C_USE_FWFT_DATA_COUNT==0 ) begin : block31 + assign RD_DATA_COUNT = RD_DATA_COUNT_FIFO_OUT; + end + endgenerate + + //Always connect WR_DATA_COUNT to the WR_DATA_COUNT from the internal + //FIFO instance + generate + if (C_USE_FWFT_DATA_COUNT==1) begin : block4 + assign WR_DATA_COUNT = WR_DATA_COUNT_FIFO_OUT; + end + else begin : block4 + assign WR_DATA_COUNT = WR_DATA_COUNT_FIFO_OUT; + end + endgenerate + + + //Connect other flags to the internal FIFO instance + assign FULL = FULL_FIFO_OUT; + assign ALMOST_FULL = ALMOST_FULL_FIFO_OUT; + assign WR_ACK = WR_ACK_FIFO_OUT; + assign OVERFLOW = OVERFLOW_FIFO_OUT; + assign PROG_FULL = PROG_FULL_FIFO_OUT; + assign PROG_EMPTY = PROG_EMPTY_FIFO_OUT; + + + // if an asynchronous FIFO has been selected, display a message that the FIFO + // will not be cycle-accurate in simulation + initial begin + if (C_IMPLEMENTATION_TYPE == 2) begin + $display("WARNING: Behavioral models for independent clock FIFO configurations are not cycle-accurate. You may wish to choose the structural simulation model instead of the behavioral model. This will ensure accurate behavior and latencies during simulation. You can enable this from CORE Generator by selecting Project -> Project Options -> Generation tab -> Structural Simulation. See the FIFO Generator User Guide for more information."); + end else if (C_MEMORY_TYPE == 4) begin + $display("FAILURE : Behavioral models for Virtex-4, Virtex-5 and Virtex-6 built-in FIFO configurations is currently not supported. Please select the structural simulation model option in CORE Generator. You can enable this in CORE Generator by selecting Project -> Project Options -> Generation tab -> Structural Simulation. See the FIFO Generator User Guide for more information."); + $finish; + end + end //initial + +endmodule //FIFO_GENERATOR_V5_2 + + + +/******************************************************************************* + * Declaration of Independent-Clocks FIFO Module + ******************************************************************************/ +module fifo_generator_v5_2_bhv_ver_as + ( + WR_CLK, RD_CLK, RST, WR_RST, RD_RST, DIN, WR_EN, RD_EN, + PROG_EMPTY_THRESH, PROG_EMPTY_THRESH_ASSERT, PROG_EMPTY_THRESH_NEGATE, + PROG_FULL_THRESH, PROG_FULL_THRESH_ASSERT, PROG_FULL_THRESH_NEGATE, + INJECTDBITERR, INJECTSBITERR, DOUT, FULL, ALMOST_FULL, WR_ACK, OVERFLOW, + EMPTY, ALMOST_EMPTY, VALID, UNDERFLOW, RD_DATA_COUNT, WR_DATA_COUNT, + PROG_FULL, PROG_EMPTY, SBITERR, DBITERR + ); + + /*************************************************************************** + * Declare user parameters and their defaults + ***************************************************************************/ + parameter C_DATA_COUNT_WIDTH = 2; + parameter C_DIN_WIDTH = 8; + parameter C_DOUT_RST_VAL = ""; + parameter C_DOUT_WIDTH = 8; + parameter C_FULL_FLAGS_RST_VAL = 1; + parameter C_HAS_ALMOST_EMPTY = 0; + parameter C_HAS_ALMOST_FULL = 0; + parameter C_HAS_DATA_COUNT = 0; + parameter C_HAS_OVERFLOW = 0; + parameter C_HAS_RD_DATA_COUNT = 0; + parameter C_HAS_RST = 0; + parameter C_HAS_UNDERFLOW = 0; + parameter C_HAS_VALID = 0; + parameter C_HAS_WR_ACK = 0; + parameter C_HAS_WR_DATA_COUNT = 0; + parameter C_IMPLEMENTATION_TYPE = 0; + parameter C_MEMORY_TYPE = 1; + parameter C_OVERFLOW_LOW = 0; + parameter C_PRELOAD_LATENCY = 1; + parameter C_PRELOAD_REGS = 0; + parameter C_PROG_EMPTY_THRESH_ASSERT_VAL = 0; + parameter C_PROG_EMPTY_THRESH_NEGATE_VAL = 0; + parameter C_PROG_EMPTY_TYPE = 0; + parameter C_PROG_FULL_THRESH_ASSERT_VAL = 0; + parameter C_PROG_FULL_THRESH_NEGATE_VAL = 0; + parameter C_PROG_FULL_TYPE = 0; + parameter C_RD_DATA_COUNT_WIDTH = 2; + parameter C_RD_DEPTH = 256; + parameter C_RD_PNTR_WIDTH = 8; + parameter C_UNDERFLOW_LOW = 0; + parameter C_USE_DOUT_RST = 0; + parameter C_USE_EMBEDDED_REG = 0; + parameter C_USE_FWFT_DATA_COUNT = 0; + parameter C_VALID_LOW = 0; + parameter C_WR_ACK_LOW = 0; + parameter C_WR_DATA_COUNT_WIDTH = 2; + parameter C_WR_DEPTH = 256; + parameter C_WR_PNTR_WIDTH = 8; + parameter C_USE_ECC = 0; + parameter C_ENABLE_RST_SYNC = 1; + parameter C_ERROR_INJECTION_TYPE = 0; + + /*************************************************************************** + * Declare Input and Output Ports + ***************************************************************************/ + input [C_DIN_WIDTH-1:0] DIN; + input [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH; + input [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_ASSERT; + input [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_NEGATE; + input [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH; + input [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_ASSERT; + input [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_NEGATE; + input RD_CLK; + input RD_EN; + input RST; + input WR_RST; + input RD_RST; + input WR_CLK; + input WR_EN; + input INJECTDBITERR; + input INJECTSBITERR; + output ALMOST_EMPTY; + output ALMOST_FULL; + output [C_DOUT_WIDTH-1:0] DOUT; + output EMPTY; + output FULL; + output OVERFLOW; + output PROG_EMPTY; + output PROG_FULL; + output VALID; + output [C_RD_DATA_COUNT_WIDTH-1:0] RD_DATA_COUNT; + output UNDERFLOW; + output WR_ACK; + output [C_WR_DATA_COUNT_WIDTH-1:0] WR_DATA_COUNT; + output SBITERR; + output DBITERR; + + /************************************************************************* + * Declare the type for each Input/Output port, and connect each I/O + * to it's associated internal signal in the behavioral model + * + * The values for the outputs are assigned in assign statements immediately + * following wire, parameter, and function declarations in this code. + *************************************************************************/ + //Inputs + wire [C_DIN_WIDTH-1:0] DIN; + wire [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH; + wire [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_ASSERT; + wire [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_NEGATE; + wire [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH; + wire [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_ASSERT; + wire [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_NEGATE; + wire RD_CLK; + wire RD_EN; + wire RST; + wire WR_RST; + wire RD_RST; + wire WR_CLK; + wire WR_EN; + wire INJECTSBITERR; + wire INJECTDBITERR; + + //Outputs + reg ALMOST_EMPTY = 1'b1; + reg ALMOST_FULL = C_FULL_FLAGS_RST_VAL; + wire [C_DOUT_WIDTH-1:0] DOUT; + reg EMPTY = 1'b1; + reg FULL = C_FULL_FLAGS_RST_VAL; + wire OVERFLOW; + wire PROG_EMPTY; + wire PROG_FULL; + wire VALID; + wire [C_RD_DATA_COUNT_WIDTH-1:0] RD_DATA_COUNT; + reg [C_RD_PNTR_WIDTH:0] rd_data_count_int; + wire UNDERFLOW; + wire WR_ACK; + wire [C_WR_DATA_COUNT_WIDTH-1:0] WR_DATA_COUNT; + reg [C_WR_PNTR_WIDTH:0] wr_data_count_int; + reg [C_WR_PNTR_WIDTH:0] wdc_fwft_ext_as; + wire SBITERR; + wire DBITERR; + + + /*************************************************************************** + * Parameters used as constants + **************************************************************************/ + //When RST is present, set FULL reset value to '1'. + //If core has no RST, make sure FULL powers-on as '0'. + parameter C_DEPTH_RATIO_WR = + (C_WR_DEPTH>C_RD_DEPTH) ? (C_WR_DEPTH/C_RD_DEPTH) : 1; + parameter C_DEPTH_RATIO_RD = + (C_RD_DEPTH>C_WR_DEPTH) ? (C_RD_DEPTH/C_WR_DEPTH) : 1; + parameter C_FIFO_WR_DEPTH = C_WR_DEPTH - 1; + parameter C_FIFO_RD_DEPTH = C_RD_DEPTH - 1; + + + // EXTRA_WORDS = 2 * C_DEPTH_RATIO_WR / C_DEPTH_RATIO_RD + // WR_DEPTH : RD_DEPTH = 1:2 => EXTRA_WORDS = 1 + // WR_DEPTH : RD_DEPTH = 1:4 => EXTRA_WORDS = 1 (rounded to ceiling) + // WR_DEPTH : RD_DEPTH = 2:1 => EXTRA_WORDS = 4 + // WR_DEPTH : RD_DEPTH = 4:1 => EXTRA_WORDS = 8 + parameter EXTRA_WORDS = (C_DEPTH_RATIO_RD > 1)? 1:(2 * C_DEPTH_RATIO_WR); + // C_DEPTH_RATIO_WR | C_DEPTH_RATIO_RD | C_PNTR_WIDTH | EXTRA_WORDS_DC + // -----------------|------------------|-----------------|--------------- + // 1 | 8 | C_RD_PNTR_WIDTH | 2 + // 1 | 4 | C_RD_PNTR_WIDTH | 2 + // 1 | 2 | C_RD_PNTR_WIDTH | 2 + // 1 | 1 | C_WR_PNTR_WIDTH | 2 + // 2 | 1 | C_WR_PNTR_WIDTH | 4 + // 4 | 1 | C_WR_PNTR_WIDTH | 8 + // 8 | 1 | C_WR_PNTR_WIDTH | 16 + + localparam C_PNTR_WIDTH = (C_WR_PNTR_WIDTH>=C_RD_PNTR_WIDTH) ? C_WR_PNTR_WIDTH : C_RD_PNTR_WIDTH; + wire [C_PNTR_WIDTH:0] EXTRA_WORDS_DC = (C_DEPTH_RATIO_WR == 1) ? 2 : (2 * C_DEPTH_RATIO_WR/C_DEPTH_RATIO_RD); + + parameter [31:0] reads_per_write = C_DIN_WIDTH/C_DOUT_WIDTH; + + parameter [31:0] log2_reads_per_write = log2_val(reads_per_write); + + parameter [31:0] writes_per_read = C_DOUT_WIDTH/C_DIN_WIDTH; + + parameter [31:0] log2_writes_per_read = log2_val(writes_per_read); + + + + /************************************************************************** + * FIFO Contents Tracking and Data Count Calculations + *************************************************************************/ + + // Memory which will be used to simulate a FIFO + reg [C_DIN_WIDTH-1:0] memory[C_WR_DEPTH-1:0]; + // Local parameters used to determine whether to inject ECC error or not + localparam SYMMETRIC_PORT = (C_DIN_WIDTH == C_DOUT_WIDTH) ? 1 : 0; + localparam ERR_INJECTION = (C_ERROR_INJECTION_TYPE != 0) ? 1 : 0; + localparam ENABLE_ERR_INJECTION = C_USE_ECC && SYMMETRIC_PORT && ERR_INJECTION; + // Array that holds the error injection type (single/double bit error) on + // a specific write operation, which is returned on read to corrupt the + // output data. + reg [1:0] ecc_err[C_WR_DEPTH-1:0]; + + //The amount of data stored in the FIFO at any time is given + // by num_wr_bits (in the WR_CLK domain) and num_rd_bits (in the RD_CLK + // domain. + //num_wr_bits is calculated by considering the total words in the FIFO, + // and the state of the read pointer (which may not have yet crossed clock + // domains.) + //num_rd_bits is calculated by considering the total words in the FIFO, + // and the state of the write pointer (which may not have yet crossed clock + // domains.) + reg [31:0] num_wr_bits; + reg [31:0] num_rd_bits; + reg [31:0] next_num_wr_bits; + reg [31:0] next_num_rd_bits; + + //The write pointer - tracks write operations + // (Works opposite to core: wr_ptr is a DOWN counter) + reg [31:0] wr_ptr; + reg [C_WR_PNTR_WIDTH-1:0] wr_pntr = 0; // UP counter: Rolls back to 0 when reaches to max value. + reg [C_WR_PNTR_WIDTH-1:0] wr_pntr_rd1 = 0; + reg [C_WR_PNTR_WIDTH-1:0] wr_pntr_rd2 = 0; + reg [C_WR_PNTR_WIDTH-1:0] wr_pntr_rd3 = 0; + wire [C_RD_PNTR_WIDTH-1:0] adj_wr_pntr_rd; + reg [C_WR_PNTR_WIDTH-1:0] wr_pntr_rd = 0; + wire wr_rst_i; + reg wr_rst_d1 =0; + + //The read pointer - tracks read operations + // (rd_ptr Works opposite to core: rd_ptr is a DOWN counter) + reg [31:0] rd_ptr; + reg [C_RD_PNTR_WIDTH-1:0] rd_pntr = 0; // UP counter: Rolls back to 0 when reaches to max value. + reg [C_RD_PNTR_WIDTH-1:0] rd_pntr_wr1 = 0; + reg [C_RD_PNTR_WIDTH-1:0] rd_pntr_wr2 = 0; + reg [C_RD_PNTR_WIDTH-1:0] rd_pntr_wr3 = 0; + reg [C_RD_PNTR_WIDTH-1:0] rd_pntr_wr4 = 0; + wire [C_WR_PNTR_WIDTH-1:0] adj_rd_pntr_wr; + reg [C_RD_PNTR_WIDTH-1:0] rd_pntr_wr = 0; + wire rd_rst_i; + + // Write pointer adjustment based on pointers width for EMPTY/ALMOST_EMPTY generation + generate + if (C_RD_PNTR_WIDTH > C_WR_PNTR_WIDTH) begin : rdg // Read depth greater than write depth + assign adj_wr_pntr_rd[C_RD_PNTR_WIDTH-1:C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH] = wr_pntr_rd; + assign adj_wr_pntr_rd[C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH-1:0] = 0; + end else begin : rdl // Read depth lesser than or equal to write depth + assign adj_wr_pntr_rd = wr_pntr_rd[C_WR_PNTR_WIDTH-1:C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH]; + end + endgenerate + + // Generate Empty and Almost Empty + // ram_rd_en used to determine EMPTY should depend on the EMPTY. + assign ram_rd_en = RD_EN & !EMPTY; + assign empty_int = ((adj_wr_pntr_rd == rd_pntr) || (ram_rd_en && (adj_wr_pntr_rd == (rd_pntr+1'h1)))); + assign almost_empty_int = ((adj_wr_pntr_rd == (rd_pntr+1'h1)) || (ram_rd_en && (adj_wr_pntr_rd == (rd_pntr+2'h2)))); + + // Register Empty and Almost Empty + always @ (posedge RD_CLK or posedge rd_rst_i) + begin + if (rd_rst_i) begin + EMPTY <= #`TCQ 1'b1; + ALMOST_EMPTY <= #`TCQ 1'b1; + rd_data_count_int <= #`TCQ {C_RD_PNTR_WIDTH-1{1'b0}}; + end else begin + rd_data_count_int <= #`TCQ {(adj_wr_pntr_rd[C_RD_PNTR_WIDTH-1:0] - rd_pntr[C_RD_PNTR_WIDTH-1:0]), 1'b0}; + + if (empty_int) + EMPTY <= #`TCQ 1'b1; + else + EMPTY <= #`TCQ 1'b0; + + if (!EMPTY) begin + if (almost_empty_int) + ALMOST_EMPTY <= #`TCQ 1'b1; + else + ALMOST_EMPTY <= #`TCQ 1'b0; + end + end // rd_rst_i + end // always + + // Read pointer adjustment based on pointers width for EMPTY/ALMOST_EMPTY generation + generate + if (C_WR_PNTR_WIDTH > C_RD_PNTR_WIDTH) begin : wdg // Write depth greater than read depth + assign adj_rd_pntr_wr[C_WR_PNTR_WIDTH-1:C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH] = rd_pntr_wr; + assign adj_rd_pntr_wr[C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH-1:0] = 0; + end else begin : wdl // Write depth lesser than or equal to read depth + assign adj_rd_pntr_wr = rd_pntr_wr[C_RD_PNTR_WIDTH-1:C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH]; + end + endgenerate + + // Generate FULL and ALMOST_FULL + // ram_wr_en used to determine FULL should depend on the FULL. + assign ram_wr_en = WR_EN & !FULL; + assign full_int = ((adj_rd_pntr_wr == (wr_pntr+1'h1)) || (ram_wr_en && (adj_rd_pntr_wr == (wr_pntr+2'h2)))); + assign almost_full_int = ((adj_rd_pntr_wr == (wr_pntr+2'h2)) || (ram_wr_en && (adj_rd_pntr_wr == (wr_pntr+3'h3)))); + + // Register FULL and ALMOST_FULL Empty + always @ (posedge WR_CLK or posedge wr_rst_i) + begin + if (wr_rst_i) begin + FULL <= #`TCQ C_FULL_FLAGS_RST_VAL; + ALMOST_FULL <= #`TCQ C_FULL_FLAGS_RST_VAL; + wr_data_count_int <= #`TCQ {C_WR_DATA_COUNT_WIDTH-1{1'b0}}; + end else begin + wr_data_count_int <= #`TCQ {(wr_pntr[C_WR_PNTR_WIDTH-1:0] - adj_rd_pntr_wr[C_WR_PNTR_WIDTH-1:0]), 1'b0}; + if (full_int) begin + FULL <= #`TCQ 1'b1; + end else begin + FULL <= #`TCQ 1'b0; + end + + if (wr_rst_d1 && !wr_rst_i) begin + ALMOST_FULL <= #`TCQ 1'b0; + end else if (!FULL) begin + if (almost_full_int) + ALMOST_FULL <= #`TCQ 1'b1; + else + ALMOST_FULL <= #`TCQ 1'b0; + end + end // wr_rst_i + end // always + + // Counter used to determine FWFT reads have been performed or not + integer rd_fwft_cnt; + reg empty_d1 = 0; + reg empty_d2 = 0; + generate + if (C_PRELOAD_LATENCY == 0) begin : grd_fwft_proc + always @ (posedge RD_CLK or posedge rd_rst_i) + begin + if (rd_rst_i) begin + rd_fwft_cnt <= #`TCQ 0; + empty_d1 <= #`TCQ 0; + empty_d2 <= #`TCQ 0; + end else begin + empty_d1 <= #`TCQ EMPTY; + empty_d2 <= #`TCQ empty_d1; + if (!empty_int && EMPTY && rd_fwft_cnt > 4) begin + rd_fwft_cnt <= #`TCQ 0; + end else if (!EMPTY) begin + if (RD_EN && (rd_fwft_cnt < 5)) begin + rd_fwft_cnt <= #`TCQ rd_fwft_cnt +1; + end + end // !EMPTY + end // rd_rst_i + end // always + end else begin : gnrd_fwft_proc + always @* rd_fwft_cnt = 2; + end + endgenerate + + + + + //Pointers passed into opposite clock domain + reg [31:0] wr_ptr_rdclk; + reg [31:0] wr_ptr_rdclk_next; + reg [31:0] rd_ptr_wrclk; + reg [31:0] rd_ptr_wrclk_next; + + //Amount of data stored in the FIFO scaled to the narrowest (deepest) port + // (Do not include data in FWFT stages) + //Used to calculate PROG_EMPTY. + wire [31:0] num_read_words_pe = + num_rd_bits/(C_DOUT_WIDTH/C_DEPTH_RATIO_WR); + + //Amount of data stored in the FIFO scaled to the narrowest (deepest) port + // (Do not include data in FWFT stages) + //Used to calculate PROG_FULL. + wire [31:0] num_write_words_pf = + num_wr_bits/(C_DIN_WIDTH/C_DEPTH_RATIO_RD); + + /************************** + * Read Data Count + *************************/ + + /* ORIGINAL CODE - Removed 10/24/07 jeo + //Amount of data stored in the FIFO scaled to read words + // (Do not include data in FWFT stages) + //Not used in the code. + wire [31:0] num_read_words_dc = num_rd_bits/C_DOUT_WIDTH; + + //Amount of data stored in the FIFO scaled to read words + // (Include data in FWFT stages) + //Not used in the code. + wire [31:0] num_read_words_fwft_dc = (num_rd_bits/C_DOUT_WIDTH+2); + + //Not used in the code. + wire [31:0] num_read_words_dc_i = + C_USE_FWFT_DATA_COUNT ? num_read_words_fwft_dc : num_read_words_dc; + + //Not used in the code. + wire [C_RD_DATA_COUNT_WIDTH-1:0] num_read_words_sized = + num_read_words_dc_i[C_RD_PNTR_WIDTH-1 : C_RD_PNTR_WIDTH-C_RD_DATA_COUNT_WIDTH]; + + //Not used in the code. + wire [C_RD_DATA_COUNT_WIDTH-1:0] num_read_words_sized_fwft = + num_read_words_dc_i[C_RD_PNTR_WIDTH : C_RD_PNTR_WIDTH-C_RD_DATA_COUNT_WIDTH+1]; + + //Used to calculate ideal_rd_count (RD_DATA_COUNT) + wire [C_RD_DATA_COUNT_WIDTH-1:0] num_read_words_sized_i = + C_USE_FWFT_DATA_COUNT ? num_read_words_sized_fwft : num_read_words_sized; + */ + + reg [31:0] num_read_words_dc; + reg [C_RD_DATA_COUNT_WIDTH-1:0] num_read_words_sized_i; + + always @(num_rd_bits) begin + if (C_USE_FWFT_DATA_COUNT) begin + + //If using extra logic for FWFT Data Counts, + // then scale FIFO contents to read domain, + // and add two read words for FWFT stages + //This value is only a temporary value and not used in the code. + num_read_words_dc = (num_rd_bits/C_DOUT_WIDTH+2); + + //Trim the read words for use with RD_DATA_COUNT + num_read_words_sized_i = + num_read_words_dc[C_RD_PNTR_WIDTH : C_RD_PNTR_WIDTH-C_RD_DATA_COUNT_WIDTH+1]; + + end else begin + + //If not using extra logic for FWFT Data Counts, + // then scale FIFO contents to read domain. + //This value is only a temporary value and not used in the code. + num_read_words_dc = num_rd_bits/C_DOUT_WIDTH; + + //Trim the read words for use with RD_DATA_COUNT + num_read_words_sized_i = + num_read_words_dc[C_RD_PNTR_WIDTH-1 : C_RD_PNTR_WIDTH-C_RD_DATA_COUNT_WIDTH]; + + end //if (C_USE_FWFT_DATA_COUNT) + end //always + + + + + + + + + /************************** + * Write Data Count + *************************/ + /* ORIGINAL CODE - Removed 10/24/07 jeo + + //Calculate the Data Count value for the number of write words, when not + // using First-Word Fall-Through with extra logic for Data Counts. This + // calculates only the number of words in the internal FIFO. + //The expression (((A-1)/B))+1 divides A/B, but takes the + // ceiling of the result. + //When num_wr_bits==0, set the result manually to prevent division errors. + wire [31:0] num_write_words_dc = + (num_wr_bits==0) ? 0 : ((num_wr_bits-1)/C_DIN_WIDTH) + 1; + + //Calculate the Data Count value for the number of write words, when using + // First-Word Fall-Through with extra logic for Data Counts. This takes into + // consideration the number of words that are expected to be stored in the + // FWFT register stages (it always assumes they are filled). + //The expression (((A-1)/B))+1 divides A/B, but takes the + // ceiling of the result. + //When num_wr_bits==0, set the result manually to prevent division errors. + //EXTRA_WORDS_DC is the number of words added to write_words due to FWFT. + wire [31:0] num_write_words_fwft_dc = + (num_wr_bits==0) ? EXTRA_WORDS_DC : (((num_wr_bits-1)/C_DIN_WIDTH) + 1) + EXTRA_WORDS_DC ; + + wire [31:0] num_write_words_dc_i = + C_USE_FWFT_DATA_COUNT ? num_write_words_fwft_dc : num_write_words_dc; + + + + wire [C_WR_DATA_COUNT_WIDTH-1:0] num_write_words_sized = + num_write_words_dc_i[C_WR_PNTR_WIDTH-1 : C_WR_PNTR_WIDTH-C_WR_DATA_COUNT_WIDTH]; + + wire [C_WR_DATA_COUNT_WIDTH-1:0] num_write_words_sized_fwft = + num_write_words_dc_i[C_WR_PNTR_WIDTH : C_WR_PNTR_WIDTH-C_WR_DATA_COUNT_WIDTH+1]; + + wire [C_WR_DATA_COUNT_WIDTH-1:0] num_write_words_sized_i = C_USE_FWFT_DATA_COUNT? + num_write_words_sized_fwft:num_write_words_sized; + + */ + + reg [31:0] num_write_words_dc; + reg [C_WR_DATA_COUNT_WIDTH-1:0] num_write_words_sized_i; + + always @(num_wr_bits) begin + if (C_USE_FWFT_DATA_COUNT) begin + + //Calculate the Data Count value for the number of write words, + // when using First-Word Fall-Through with extra logic for Data + // Counts. This takes into consideration the number of words that + // are expected to be stored in the FWFT register stages (it always + // assumes they are filled). + //This value is scaled to the Write Domain. + //The expression (((A-1)/B))+1 divides A/B, but takes the + // ceiling of the result. + //When num_wr_bits==0, set the result manually to prevent + // division errors. + //EXTRA_WORDS_DC is the number of words added to write_words + // due to FWFT. + //This value is only a temporary value and not used in the code. + num_write_words_dc = (num_wr_bits==0) ? EXTRA_WORDS_DC : (((num_wr_bits-1)/C_DIN_WIDTH)+1) + EXTRA_WORDS_DC ; + + //Trim the write words for use with WR_DATA_COUNT + num_write_words_sized_i = + num_write_words_dc[C_WR_PNTR_WIDTH : C_WR_PNTR_WIDTH-C_WR_DATA_COUNT_WIDTH+1]; + + end else begin + + //Calculate the Data Count value for the number of write words, when NOT + // using First-Word Fall-Through with extra logic for Data Counts. This + // calculates only the number of words in the internal FIFO. + //The expression (((A-1)/B))+1 divides A/B, but takes the + // ceiling of the result. + //This value is scaled to the Write Domain. + //When num_wr_bits==0, set the result manually to prevent + // division errors. + //This value is only a temporary value and not used in the code. + num_write_words_dc = (num_wr_bits==0) ? 0 : ((num_wr_bits-1)/C_DIN_WIDTH)+1; + + //Trim the read words for use with RD_DATA_COUNT + num_write_words_sized_i = + num_write_words_dc[C_WR_PNTR_WIDTH-1 : C_WR_PNTR_WIDTH-C_WR_DATA_COUNT_WIDTH]; + + end //if (C_USE_FWFT_DATA_COUNT) + end //always + + + + /*************************************************************************** + * Internal registers and wires + **************************************************************************/ + + //Temporary signals used for calculating the model's outputs. These + //are only used in the assign statements immediately following wire, + //parameter, and function declarations. + wire [C_DOUT_WIDTH-1:0] ideal_dout_out; + wire valid_i; + wire valid_out; + wire underflow_i; + + //Ideal FIFO signals. These are the raw output of the behavioral model, + //which behaves like an ideal FIFO. + reg [1:0] err_type = 0; + reg [1:0] err_type_d1 = 0; + reg [C_DOUT_WIDTH-1:0] ideal_dout; + reg [C_DOUT_WIDTH-1:0] ideal_dout_d1; + reg ideal_wr_ack; + reg ideal_valid; + reg ideal_overflow; + reg ideal_underflow; +// reg ideal_full; +// reg ideal_empty; +// reg ideal_almost_full; +// reg ideal_almost_empty; + reg ideal_prog_full; + reg ideal_prog_empty; + reg [C_WR_DATA_COUNT_WIDTH-1 : 0] ideal_wr_count; + reg [C_RD_DATA_COUNT_WIDTH-1 : 0] ideal_rd_count; + + //Assorted reg values for delayed versions of signals + reg valid_d1; + reg prog_full_d; + reg prog_empty_d; + + //Internal reset signals + reg rd_rst_asreg =0; + reg rd_rst_asreg_d1 =0; + reg rd_rst_asreg_d2 =0; + reg rd_rst_reg =0; + reg rd_rst_d1 =0; + reg wr_rst_asreg =0; + reg wr_rst_asreg_d1 =0; + reg wr_rst_asreg_d2 =0; + reg wr_rst_reg =0; + + wire rd_rst_comb; + wire wr_rst_comb; + + + //user specified value for reseting the size of the fifo + reg [C_DOUT_WIDTH-1:0] dout_reset_val; + + //temporary registers for WR_RESPONSE_LATENCY feature + + integer tmp_wr_listsize; + integer tmp_rd_listsize; + + //Signal for registered version of prog full and empty + + //Threshold values for Programmable Flags + integer prog_empty_actual_thresh_assert; + integer prog_empty_actual_thresh_negate; + integer prog_full_actual_thresh_assert; + integer prog_full_actual_thresh_negate; + + + /**************************************************************************** + * Function Declarations + ***************************************************************************/ + + /************************************************************************** + * write_fifo + * This task writes a word to the FIFO memory and updates the + * write pointer. + * FIFO size is relative to write domain. + ***************************************************************************/ + task write_fifo; + begin + memory[wr_ptr] <= DIN; + wr_pntr <= #`TCQ wr_pntr + 1; + // Store the type of error injection (double/single) on write + ecc_err[wr_ptr] <= {INJECTDBITERR,INJECTSBITERR}; + // (Works opposite to core: wr_ptr is a DOWN counter) + if (wr_ptr == 0) begin + wr_ptr <= C_WR_DEPTH - 1; + end else begin + wr_ptr <= wr_ptr - 1; + end + end + endtask // write_fifo + + /************************************************************************** + * read_fifo + * This task reads a word from the FIFO memory and updates the read + * pointer. It's output is the ideal_dout bus. + * FIFO size is relative to write domain. + ***************************************************************************/ + task read_fifo; + integer i; + reg [C_DOUT_WIDTH-1:0] tmp_dout; + reg [C_DIN_WIDTH-1:0] memory_read; + reg [31:0] tmp_rd_ptr; + reg [31:0] rd_ptr_high; + reg [31:0] rd_ptr_low; + reg [1:0] tmp_ecc_err; + begin + rd_pntr <= #`TCQ rd_pntr + 1; + // output is wider than input + if (reads_per_write == 0) begin + tmp_dout = 0; + tmp_rd_ptr = (rd_ptr << log2_writes_per_read)+(writes_per_read-1); + for (i = writes_per_read - 1; i >= 0; i = i - 1) begin + tmp_dout = tmp_dout << C_DIN_WIDTH; + tmp_dout = tmp_dout | memory[tmp_rd_ptr]; + + // (Works opposite to core: rd_ptr is a DOWN counter) + if (tmp_rd_ptr == 0) begin + tmp_rd_ptr = C_WR_DEPTH - 1; + end else begin + tmp_rd_ptr = tmp_rd_ptr - 1; + end + end + + // output is symmetric + end else if (reads_per_write == 1) begin + tmp_dout = memory[rd_ptr][C_DIN_WIDTH-1:0]; + // Retreive the error injection type. Based on the error injection type + // corrupt the output data. + tmp_ecc_err = ecc_err[rd_ptr]; + if (ENABLE_ERR_INJECTION && C_DIN_WIDTH == C_DOUT_WIDTH) begin +// if (tmp_ecc_err[1] && C_DIN_WIDTH > 1) begin // Corrupt the output data only for double bit error + if (tmp_ecc_err[1]) begin // Corrupt the output data only for double bit error + if (C_DOUT_WIDTH == 1) + tmp_dout = tmp_dout[C_DOUT_WIDTH-1:0]; + else if (C_DOUT_WIDTH == 2) + tmp_dout = {~tmp_dout[C_DOUT_WIDTH-1],~tmp_dout[C_DOUT_WIDTH-2]}; + else + tmp_dout = {~tmp_dout[C_DOUT_WIDTH-1],~tmp_dout[C_DOUT_WIDTH-2],(tmp_dout << 2)}; + end else begin + tmp_dout = tmp_dout[C_DOUT_WIDTH-1:0]; + end + err_type <= {tmp_ecc_err[1], tmp_ecc_err[0] & !tmp_ecc_err[1]}; + end else begin + err_type <= 0; + end + + // input is wider than output + end else begin + rd_ptr_high = rd_ptr >> log2_reads_per_write; + rd_ptr_low = rd_ptr & (reads_per_write - 1); + memory_read = memory[rd_ptr_high]; + tmp_dout = memory_read >> (rd_ptr_low*C_DOUT_WIDTH); + end + ideal_dout <= tmp_dout; + + // (Works opposite to core: rd_ptr is a DOWN counter) + if (rd_ptr == 0) begin + rd_ptr <= C_RD_DEPTH - 1; + end else begin + rd_ptr <= rd_ptr - 1; + end + end + endtask + + /************************************************************************** + * log2_val + * Returns the 'log2' value for the input value for the supported ratios + ***************************************************************************/ + function [31:0] log2_val; + input [31:0] binary_val; + + begin + if (binary_val == 8) begin + log2_val = 3; + end else if (binary_val == 4) begin + log2_val = 2; + end else begin + log2_val = 1; + end + end + endfunction + + /*********************************************************************** + * hexstr_conv + * Converts a string of type hex to a binary value (for C_DOUT_RST_VAL) + ***********************************************************************/ + function [C_DOUT_WIDTH-1:0] hexstr_conv; + input [(C_DOUT_WIDTH*8)-1:0] def_data; + + integer index,i,j; + reg [3:0] bin; + + begin + index = 0; + hexstr_conv = 'b0; + for( i=C_DOUT_WIDTH-1; i>=0; i=i-1 ) + begin + case (def_data[7:0]) + 8'b00000000 : + begin + bin = 4'b0000; + i = -1; + end + 8'b00110000 : bin = 4'b0000; + 8'b00110001 : bin = 4'b0001; + 8'b00110010 : bin = 4'b0010; + 8'b00110011 : bin = 4'b0011; + 8'b00110100 : bin = 4'b0100; + 8'b00110101 : bin = 4'b0101; + 8'b00110110 : bin = 4'b0110; + 8'b00110111 : bin = 4'b0111; + 8'b00111000 : bin = 4'b1000; + 8'b00111001 : bin = 4'b1001; + 8'b01000001 : bin = 4'b1010; + 8'b01000010 : bin = 4'b1011; + 8'b01000011 : bin = 4'b1100; + 8'b01000100 : bin = 4'b1101; + 8'b01000101 : bin = 4'b1110; + 8'b01000110 : bin = 4'b1111; + 8'b01100001 : bin = 4'b1010; + 8'b01100010 : bin = 4'b1011; + 8'b01100011 : bin = 4'b1100; + 8'b01100100 : bin = 4'b1101; + 8'b01100101 : bin = 4'b1110; + 8'b01100110 : bin = 4'b1111; + default : + begin + bin = 4'bx; + end + endcase + for( j=0; j<4; j=j+1) + begin + if ((index*4)+j < C_DOUT_WIDTH) + begin + hexstr_conv[(index*4)+j] = bin[j]; + end + end + index = index + 1; + def_data = def_data >> 8; + end + end + endfunction + + /************************************************************************* + * Initialize Signals for clean power-on simulation + *************************************************************************/ + initial begin + num_wr_bits = 0; + num_rd_bits = 0; + next_num_wr_bits = 0; + next_num_rd_bits = 0; + rd_ptr = C_RD_DEPTH - 1; + wr_ptr = C_WR_DEPTH - 1; + wr_pntr = 0; + rd_pntr = 0; + rd_ptr_wrclk = rd_ptr; + wr_ptr_rdclk = wr_ptr; + dout_reset_val = hexstr_conv(C_DOUT_RST_VAL); + ideal_dout = dout_reset_val; + err_type = 0; + ideal_dout_d1 = 0 ; + ideal_wr_ack = 1'b0; + ideal_valid = 1'b0; + valid_d1 = 1'b0; + ideal_overflow = 1'b0; + ideal_underflow = 1'b0; +// ideal_full = 1'b0; +// ideal_empty = 1'b1; +// ideal_almost_full = 1'b0; +// ideal_almost_empty = 1'b1; + ideal_wr_count = 0; + ideal_rd_count = 0; + ideal_prog_full = 1'b0; + ideal_prog_empty = 1'b1; + prog_full_d = 1'b0; + prog_empty_d = 1'b1; + end + + + /************************************************************************* + * Connect the module inputs and outputs to the internal signals of the + * behavioral model. + *************************************************************************/ + //Inputs + /* + wire [C_DIN_WIDTH-1:0] DIN; + wire [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH; + wire [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_ASSERT; + wire [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_NEGATE; + wire [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH; + wire [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_ASSERT; + wire [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_NEGATE; + wire RD_CLK; + wire RD_EN; + wire RST; + wire WR_CLK; + wire WR_EN; + */ + + //*************************************************************************** + // Dout may change behavior based on latency + //*************************************************************************** + assign ideal_dout_out[C_DOUT_WIDTH-1:0] = (C_PRELOAD_LATENCY==2 && + (C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1))? + ideal_dout_d1: ideal_dout; + assign DOUT[C_DOUT_WIDTH-1:0] = ideal_dout_out; + + //*************************************************************************** + // Assign SBITERR and DBITERR based on latency + //*************************************************************************** + assign SBITERR = (C_ERROR_INJECTION_TYPE == 1 || C_ERROR_INJECTION_TYPE == 3) && + (C_PRELOAD_LATENCY == 2 && + (C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1)) ? + err_type_d1[0]: err_type[0]; + assign DBITERR = (C_ERROR_INJECTION_TYPE == 2 || C_ERROR_INJECTION_TYPE == 3) && + (C_PRELOAD_LATENCY==2 && (C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1)) ? + err_type_d1[1]: err_type[1]; + + + //*************************************************************************** + // Overflow may be active-low + //*************************************************************************** + generate + if (C_HAS_OVERFLOW==1) begin : blockOF1 + assign OVERFLOW = ideal_overflow ? !C_OVERFLOW_LOW : C_OVERFLOW_LOW; + end + endgenerate + + assign PROG_EMPTY = ideal_prog_empty; + assign PROG_FULL = ideal_prog_full; + + //*************************************************************************** + // Valid may change behavior based on latency or active-low + //*************************************************************************** + generate + if (C_HAS_VALID==1) begin : blockVL1 + assign valid_i = (C_PRELOAD_LATENCY==0) ? (RD_EN & ~EMPTY) : ideal_valid; + assign valid_out = (C_PRELOAD_LATENCY==2 && + (C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1))? + valid_d1: valid_i; + assign VALID = valid_out ? !C_VALID_LOW : C_VALID_LOW; + end + endgenerate + + + //*************************************************************************** + // Underflow may change behavior based on latency or active-low + //*************************************************************************** + generate + if (C_HAS_UNDERFLOW==1) begin : blockUF1 + assign underflow_i = (C_PRELOAD_LATENCY==0) ? (RD_EN & EMPTY) : ideal_underflow; + assign UNDERFLOW = underflow_i ? !C_UNDERFLOW_LOW : C_UNDERFLOW_LOW; + end + endgenerate + + //*************************************************************************** + // Write acknowledge may be active low + //*************************************************************************** + generate + if (C_HAS_WR_ACK==1) begin : blockWK1 + assign WR_ACK = ideal_wr_ack ? !C_WR_ACK_LOW : C_WR_ACK_LOW; + end + endgenerate + + + //*************************************************************************** + // Generate RD_DATA_COUNT if Use Extra Logic option is selected + //*************************************************************************** + generate + if (C_HAS_WR_DATA_COUNT == 1 && C_USE_FWFT_DATA_COUNT == 1) begin : wdc_fwft_ext + + reg [C_PNTR_WIDTH-1:0] adjusted_wr_pntr = 0; + reg [C_PNTR_WIDTH-1:0] adjusted_rd_pntr = 0; + wire [C_PNTR_WIDTH-1:0] diff_wr_rd_tmp; + wire [C_PNTR_WIDTH:0] diff_wr_rd; + reg [C_PNTR_WIDTH:0] wr_data_count_i = 0; + always @* begin + if (C_WR_PNTR_WIDTH > C_RD_PNTR_WIDTH) begin + adjusted_wr_pntr = wr_pntr; + adjusted_rd_pntr = 0; + adjusted_rd_pntr[C_PNTR_WIDTH-1:C_PNTR_WIDTH-C_RD_PNTR_WIDTH] = rd_pntr_wr; + end else if (C_WR_PNTR_WIDTH < C_RD_PNTR_WIDTH) begin + adjusted_rd_pntr = rd_pntr_wr; + adjusted_wr_pntr = 0; + adjusted_wr_pntr[C_PNTR_WIDTH-1:C_PNTR_WIDTH-C_WR_PNTR_WIDTH] = wr_pntr; + end else begin + adjusted_wr_pntr = wr_pntr; + adjusted_rd_pntr = rd_pntr_wr; + end + end // always @* + + assign diff_wr_rd_tmp = adjusted_wr_pntr - adjusted_rd_pntr; + assign diff_wr_rd = {1'b0,diff_wr_rd_tmp}; + + always @ (posedge wr_rst_i or posedge WR_CLK) + begin + if (wr_rst_i) + wr_data_count_i <= #`TCQ 0; + else + wr_data_count_i <= #`TCQ diff_wr_rd + EXTRA_WORDS_DC; + end // always @ (posedge WR_CLK or posedge WR_CLK) + + always @* begin + if (C_WR_PNTR_WIDTH >= C_RD_PNTR_WIDTH) + wdc_fwft_ext_as = wr_data_count_i[C_PNTR_WIDTH:0]; + else + wdc_fwft_ext_as = wr_data_count_i[C_PNTR_WIDTH:C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH]; + end // always @* + end // wdc_fwft_ext + endgenerate + + //*************************************************************************** + // Generate RD_DATA_COUNT if Use Extra Logic option is selected + //*************************************************************************** + reg [C_RD_PNTR_WIDTH:0] rdc_fwft_ext_as = 0; + + generate + if (C_HAS_RD_DATA_COUNT == 1 && C_USE_FWFT_DATA_COUNT == 1) begin : rdc_fwft_ext + reg [C_RD_PNTR_WIDTH-1:0] adjusted_wr_pntr_rd = 0; + wire [C_RD_PNTR_WIDTH-1:0] diff_rd_wr_tmp; + wire [C_RD_PNTR_WIDTH:0] diff_rd_wr; + always @* begin + if (C_RD_PNTR_WIDTH > C_WR_PNTR_WIDTH) begin + adjusted_wr_pntr_rd = 0; + adjusted_wr_pntr_rd[C_RD_PNTR_WIDTH-1:C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH] = wr_pntr_rd; + end else begin + adjusted_wr_pntr_rd = wr_pntr_rd[C_WR_PNTR_WIDTH-1:C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH]; + end + end // always @* + + assign diff_rd_wr_tmp = adjusted_wr_pntr_rd - rd_pntr; + assign diff_rd_wr = {1'b0,diff_rd_wr_tmp}; + + always @ (posedge rd_rst_i or posedge RD_CLK) + begin + if (rd_rst_i) begin + rdc_fwft_ext_as <= #`TCQ 0; + end else begin + if (rd_fwft_cnt < 2) + rdc_fwft_ext_as <= #`TCQ 0; +// else if (empty_d1 && ~empty_d2) + else if (empty_d1 && ~empty_d2 && rd_fwft_cnt < 2) + rdc_fwft_ext_as <= #`TCQ 1; + else + rdc_fwft_ext_as <= #`TCQ diff_rd_wr + 2'h2; + end + end // always @ (posedge WR_CLK or posedge WR_CLK) + end // rdc_fwft_ext + endgenerate + + //*************************************************************************** + // Assign the read data count value only if it is selected, + // otherwise output zeros. + //*************************************************************************** + generate + if (C_HAS_RD_DATA_COUNT == 1) begin : grdc + assign RD_DATA_COUNT[C_RD_DATA_COUNT_WIDTH-1:0] = C_USE_FWFT_DATA_COUNT ? + rdc_fwft_ext_as[C_RD_PNTR_WIDTH:C_RD_PNTR_WIDTH+1-C_RD_DATA_COUNT_WIDTH] : + rd_data_count_int[C_RD_PNTR_WIDTH:C_RD_PNTR_WIDTH+1-C_RD_DATA_COUNT_WIDTH]; + end + endgenerate + + generate + if (C_HAS_RD_DATA_COUNT == 0) begin : gnrdc + assign RD_DATA_COUNT[C_RD_DATA_COUNT_WIDTH-1:0] = {C_RD_DATA_COUNT_WIDTH-1{1'b0}}; + end + endgenerate + + //*************************************************************************** + // Assign the write data count value only if it is selected, + // otherwise output zeros + //*************************************************************************** + generate + if (C_HAS_WR_DATA_COUNT == 1) begin : gwdc + assign WR_DATA_COUNT[C_WR_DATA_COUNT_WIDTH-1:0] = (C_USE_FWFT_DATA_COUNT == 1) ? + wdc_fwft_ext_as[C_WR_PNTR_WIDTH:C_WR_PNTR_WIDTH+1-C_WR_DATA_COUNT_WIDTH] : + wr_data_count_int[C_WR_PNTR_WIDTH:C_WR_PNTR_WIDTH+1-C_WR_DATA_COUNT_WIDTH]; + end + endgenerate + + generate + if (C_HAS_WR_DATA_COUNT == 0) begin : gnwdc + assign WR_DATA_COUNT[C_WR_DATA_COUNT_WIDTH-1:0] = {C_WR_DATA_COUNT_WIDTH-1{1'b0}}; + end + endgenerate + + /************************************************************************** + * Internal reset logic + **************************************************************************/ + assign wr_rst_i = (C_HAS_RST == 1 || C_ENABLE_RST_SYNC == 0) ? wr_rst_reg : 0; + assign rd_rst_i = (C_HAS_RST == 1 || C_ENABLE_RST_SYNC == 0) ? rd_rst_reg : 0; + + generate + if (C_ENABLE_RST_SYNC == 0) begin : gnrst_sync + always @* begin + wr_rst_reg <= WR_RST; + rd_rst_reg <= RD_RST; + end + end else if (C_HAS_RST==1) begin : blockRST2 + assign wr_rst_comb = !wr_rst_asreg_d2 && wr_rst_asreg; + assign rd_rst_comb = !rd_rst_asreg_d2 && rd_rst_asreg; + + always @(posedge WR_CLK or posedge RST) begin + if (RST == 1'b1) begin + wr_rst_asreg <= #`TCQ 1'b1; + end else begin + if (wr_rst_asreg_d1 == 1'b1) begin + wr_rst_asreg <= #`TCQ 1'b0; + end else begin + wr_rst_asreg <= #`TCQ wr_rst_asreg; + end + end + end + + always @(posedge WR_CLK) begin + wr_rst_asreg_d1 <= #`TCQ wr_rst_asreg; + wr_rst_asreg_d2 <= #`TCQ wr_rst_asreg_d1; + end + + always @(posedge WR_CLK or posedge wr_rst_comb) begin + if (wr_rst_comb == 1'b1) begin + wr_rst_reg <= #`TCQ 1'b1; + end else begin + wr_rst_reg <= #`TCQ 1'b0; + end + end + + always @(posedge RD_CLK or posedge RST) begin + if (RST == 1'b1) begin + rd_rst_asreg <= #`TCQ 1'b1; + end else begin + if (rd_rst_asreg_d1 == 1'b1) begin + rd_rst_asreg <= #`TCQ 1'b0; + end else begin + rd_rst_asreg <= #`TCQ rd_rst_asreg; + end + end + end + + always @(posedge RD_CLK) begin + rd_rst_asreg_d1 <= #`TCQ rd_rst_asreg; + rd_rst_asreg_d2 <= #`TCQ rd_rst_asreg_d1; + end + + always @(posedge RD_CLK or posedge rd_rst_comb) begin + if (rd_rst_comb == 1'b1) begin + rd_rst_reg <= #`TCQ 1'b1; + end else begin + rd_rst_reg <= #`TCQ 1'b0; + end + end + end + endgenerate + + always @(posedge WR_CLK or posedge wr_rst_i) begin + if (wr_rst_i == 1'b1) begin + wr_rst_d1 <= #`TCQ 1'b1; + end else begin + wr_rst_d1 <= #`TCQ wr_rst_i; + end + end + + /************************************************************************** + * Assorted registers for delayed versions of signals + **************************************************************************/ + //Capture delayed version of valid + generate + if (C_HAS_VALID==1) begin : blockVL2 + always @(posedge RD_CLK or posedge rd_rst_i) begin + if (rd_rst_i == 1'b1) begin + valid_d1 <= #`TCQ 1'b0; + end else begin + valid_d1 <= #`TCQ valid_i; + end + end + end + endgenerate + + //Capture delayed version of dout + always @(posedge RD_CLK or posedge rd_rst_i) begin + if (rd_rst_i == 1'b1) begin + err_type_d1 <= #`TCQ 0; + if (C_USE_DOUT_RST == 1) + ideal_dout_d1 <= #`TCQ dout_reset_val; + end else begin + ideal_dout_d1 <= #`TCQ ideal_dout; + err_type_d1 <= #`TCQ err_type; + end + end + + /************************************************************************** + * Overflow and Underflow Flag calculation + * (handled separately because they don't support rst) + **************************************************************************/ + generate + if (C_HAS_OVERFLOW==1) begin : blockOF2 + always @(posedge WR_CLK) begin +// ideal_overflow <= #`TCQ WR_EN & ideal_full; + ideal_overflow <= #`TCQ WR_EN & FULL; + end + end + endgenerate + + generate + if (C_HAS_UNDERFLOW==1) begin : blockUF2 + always @(posedge RD_CLK) begin +// ideal_underflow <= #`TCQ ideal_empty & RD_EN; + ideal_underflow <= #`TCQ EMPTY & RD_EN; + end + end + endgenerate + + /************************************************************************** + * Write Domain Logic + **************************************************************************/ + always @(posedge WR_CLK or posedge wr_rst_i) begin : gen_fifo_w + + /****** Reset fifo (case 1)***************************************/ + if (wr_rst_i == 1'b1) begin + num_wr_bits <= #`TCQ 0; + next_num_wr_bits = #`TCQ 0; + wr_ptr <= #`TCQ C_WR_DEPTH - 1; + rd_ptr_wrclk <= #`TCQ C_RD_DEPTH - 1; + ideal_wr_ack <= #`TCQ 0; +// ideal_full <= #`TCQ C_FULL_FLAGS_RST_VAL; +// ideal_almost_full <= #`TCQ C_FULL_FLAGS_RST_VAL; + ideal_wr_count <= #`TCQ 0; + tmp_wr_listsize = #`TCQ 0; + rd_ptr_wrclk_next <= #`TCQ 0; + wr_pntr <= #`TCQ 0; + rd_pntr_wr1 <= #`TCQ 0; + rd_pntr_wr2 <= #`TCQ 0; + rd_pntr_wr3 <= #`TCQ 0; + rd_pntr_wr4 <= #`TCQ 0; + rd_pntr_wr <= #`TCQ 0; + + ideal_prog_full <= #`TCQ C_FULL_FLAGS_RST_VAL; + prog_full_d <= #`TCQ C_FULL_FLAGS_RST_VAL; + + end else begin //wr_rst_i==0 + + // Synchronize the rd_pntr in read domain + rd_pntr_wr1 <= #`TCQ rd_pntr; + rd_pntr_wr2 <= #`TCQ rd_pntr_wr1; + rd_pntr_wr3 <= #`TCQ rd_pntr_wr2; + if (C_PRELOAD_LATENCY == 0 && C_USE_FWFT_DATA_COUNT == 0) begin + rd_pntr_wr4 <= #`TCQ rd_pntr_wr2; + end else begin + if (rd_fwft_cnt < 2) begin + rd_pntr_wr4 <= #`TCQ rd_pntr_wr3; + end else begin + rd_pntr_wr4 <= #`TCQ rd_pntr_wr2; + end + end + rd_pntr_wr <= #`TCQ rd_pntr_wr4; + + + + //Determine the current number of words in the FIFO + tmp_wr_listsize = (C_DEPTH_RATIO_RD > 1) ? num_wr_bits/C_DOUT_WIDTH : + num_wr_bits/C_DIN_WIDTH; + rd_ptr_wrclk_next = rd_ptr; + if (rd_ptr_wrclk < rd_ptr_wrclk_next) begin + next_num_wr_bits = num_wr_bits - + C_DOUT_WIDTH*(rd_ptr_wrclk + C_RD_DEPTH + - rd_ptr_wrclk_next); + end else begin + next_num_wr_bits = num_wr_bits - + C_DOUT_WIDTH*(rd_ptr_wrclk - rd_ptr_wrclk_next); + end + + //If this is a write, handle the write by adding the value + // to the linked list, and updating all outputs appropriately + if (WR_EN == 1'b1) begin +// if (ideal_full == 1'b1) begin + if (FULL == 1'b1) begin + + //If the FIFO is full, do NOT perform the write, + // update flags accordingly + if ((tmp_wr_listsize + C_DEPTH_RATIO_RD - 1)/C_DEPTH_RATIO_RD + >= C_FIFO_WR_DEPTH) begin + //write unsuccessful - do not change contents + + //Do not acknowledge the write + ideal_wr_ack <= #`TCQ 0; + //Reminder that FIFO is still full +// ideal_full <= #`TCQ 1'b1; +// ideal_almost_full <= #`TCQ 1'b1; + + ideal_wr_count <= #`TCQ num_write_words_sized_i; + + //If the FIFO is one from full, but reporting full + end else + if ((tmp_wr_listsize + C_DEPTH_RATIO_RD - 1)/C_DEPTH_RATIO_RD == + C_FIFO_WR_DEPTH-1) begin + //No change to FIFO + + //Write not successful + ideal_wr_ack <= #`TCQ 0; + //With DEPTH-1 words in the FIFO, it is almost_full +// ideal_full <= #`TCQ 1'b0; +// ideal_almost_full <= #`TCQ 1'b1; + + ideal_wr_count <= #`TCQ num_write_words_sized_i; + + + //If the FIFO is completely empty, but it is + // reporting FULL for some reason (like reset) + end else + if ((tmp_wr_listsize + C_DEPTH_RATIO_RD - 1)/C_DEPTH_RATIO_RD <= + C_FIFO_WR_DEPTH-2) begin + //No change to FIFO + + //Write not successful + ideal_wr_ack <= #`TCQ 0; + //FIFO is really not close to full, so change flag status. +// ideal_full <= #`TCQ 1'b0; +// ideal_almost_full <= #`TCQ 1'b0; + + ideal_wr_count <= #`TCQ num_write_words_sized_i; + end //(tmp_wr_listsize == 0) + + end else begin + + //If the FIFO is full, do NOT perform the write, + // update flags accordingly + if ((tmp_wr_listsize + C_DEPTH_RATIO_RD - 1)/C_DEPTH_RATIO_RD >= + C_FIFO_WR_DEPTH) begin + //write unsuccessful - do not change contents + + //Do not acknowledge the write + ideal_wr_ack <= #`TCQ 0; + //Reminder that FIFO is still full +// ideal_full <= #`TCQ 1'b1; +// ideal_almost_full <= #`TCQ 1'b1; + + ideal_wr_count <= #`TCQ num_write_words_sized_i; + + //If the FIFO is one from full + end else + if ((tmp_wr_listsize + C_DEPTH_RATIO_RD - 1)/C_DEPTH_RATIO_RD == + C_FIFO_WR_DEPTH-1) begin + //Add value on DIN port to FIFO + write_fifo; + next_num_wr_bits = next_num_wr_bits + C_DIN_WIDTH; + + //Write successful, so issue acknowledge + // and no error + ideal_wr_ack <= #`TCQ 1; + //This write is CAUSING the FIFO to go full +// ideal_full <= #`TCQ 1'b1; +// ideal_almost_full <= #`TCQ 1'b1; + + ideal_wr_count <= #`TCQ num_write_words_sized_i; + + //If the FIFO is 2 from full + end else + if ((tmp_wr_listsize + C_DEPTH_RATIO_RD - 1)/C_DEPTH_RATIO_RD == + C_FIFO_WR_DEPTH-2) begin + //Add value on DIN port to FIFO + write_fifo; + next_num_wr_bits = next_num_wr_bits + C_DIN_WIDTH; + //Write successful, so issue acknowledge + // and no error + ideal_wr_ack <= #`TCQ 1; + //Still 2 from full +// ideal_full <= #`TCQ 1'b0; +// //2 from full, and writing, so set almost_full +// ideal_almost_full <= #`TCQ 1'b1; + + ideal_wr_count <= #`TCQ num_write_words_sized_i; + + //If the FIFO is not close to being full + end else + if ((tmp_wr_listsize + C_DEPTH_RATIO_RD - 1)/C_DEPTH_RATIO_RD < + C_FIFO_WR_DEPTH-2) begin + //Add value on DIN port to FIFO + write_fifo; + next_num_wr_bits = next_num_wr_bits + C_DIN_WIDTH; + //Write successful, so issue acknowledge + // and no error + ideal_wr_ack <= #`TCQ 1; + //Not even close to full. +// ideal_full <= #`TCQ 1'b0; +// ideal_almost_full <= #`TCQ 1'b0; + + ideal_wr_count <= num_write_words_sized_i; + + end + + end + + end else begin //(WR_EN == 1'b1) + + //If user did not attempt a write, then do not + // give ack or err + ideal_wr_ack <= #`TCQ 0; + + //Implied statements: + //ideal_empty <= ideal_empty; + //ideal_almost_empty <= ideal_almost_empty; + + //Check for full +// if ((tmp_wr_listsize + C_DEPTH_RATIO_RD - 1)/C_DEPTH_RATIO_RD >= C_FIFO_WR_DEPTH) +// ideal_full <= #`TCQ 1'b1; +// else +// ideal_full <= #`TCQ 1'b0; +// +// //Check for almost_full +// if ((tmp_wr_listsize + C_DEPTH_RATIO_RD - 1)/C_DEPTH_RATIO_RD >= C_FIFO_WR_DEPTH-1) +// ideal_almost_full <= #`TCQ 1'b1; +// else +// ideal_almost_full <= #`TCQ 1'b0; + + ideal_wr_count <= #`TCQ num_write_words_sized_i; + end + + /********************************************************* + * Programmable FULL flags + *********************************************************/ + //Single Programmable Full Constant Threshold + if (C_PROG_FULL_TYPE==1) begin + if (C_PRELOAD_REGS==1 && C_PRELOAD_LATENCY==0) begin + prog_full_actual_thresh_assert = C_PROG_FULL_THRESH_ASSERT_VAL-EXTRA_WORDS; + prog_full_actual_thresh_negate = C_PROG_FULL_THRESH_ASSERT_VAL-EXTRA_WORDS; + end else begin + prog_full_actual_thresh_assert = C_PROG_FULL_THRESH_ASSERT_VAL; + prog_full_actual_thresh_negate = C_PROG_FULL_THRESH_ASSERT_VAL; + end + + //Two Programmable Full Constant Thresholds + end else if (C_PROG_FULL_TYPE==2) begin + if (C_PRELOAD_REGS==1 && C_PRELOAD_LATENCY==0) begin + prog_full_actual_thresh_assert = C_PROG_FULL_THRESH_ASSERT_VAL-EXTRA_WORDS; + prog_full_actual_thresh_negate = C_PROG_FULL_THRESH_NEGATE_VAL-EXTRA_WORDS; + end else begin + prog_full_actual_thresh_assert = C_PROG_FULL_THRESH_ASSERT_VAL; + prog_full_actual_thresh_negate = C_PROG_FULL_THRESH_NEGATE_VAL; + end + + //Single Programmable Full Threshold Input + end else if (C_PROG_FULL_TYPE==3) begin + if (C_PRELOAD_REGS==1 && C_PRELOAD_LATENCY==0) begin + prog_full_actual_thresh_assert = PROG_FULL_THRESH-EXTRA_WORDS; + prog_full_actual_thresh_negate = PROG_FULL_THRESH-EXTRA_WORDS; + end else begin + prog_full_actual_thresh_assert = PROG_FULL_THRESH; + prog_full_actual_thresh_negate = PROG_FULL_THRESH; + end + + //Two Programmable Full Threshold Inputs + end else if (C_PROG_FULL_TYPE==4) begin + if (C_PRELOAD_REGS==1 && C_PRELOAD_LATENCY==0) begin + prog_full_actual_thresh_assert = PROG_FULL_THRESH_ASSERT-EXTRA_WORDS; + prog_full_actual_thresh_negate = PROG_FULL_THRESH_NEGATE-EXTRA_WORDS; + end else begin + prog_full_actual_thresh_assert = PROG_FULL_THRESH_ASSERT; + prog_full_actual_thresh_negate = PROG_FULL_THRESH_NEGATE; + end + end //C_PROG_FULL_TYPE + + if (num_write_words_pf==0) begin + prog_full_d <= #`TCQ 1'b0; + end else begin + if (((1+(num_write_words_pf-1)/C_DEPTH_RATIO_RD) + == prog_full_actual_thresh_assert-1) && WR_EN) begin + prog_full_d <= #`TCQ 1'b1; + end else if ((1+(num_write_words_pf-1)/C_DEPTH_RATIO_RD) + >= prog_full_actual_thresh_assert) begin + prog_full_d <= #`TCQ 1'b1; + end else if ((1+(num_write_words_pf-1)/C_DEPTH_RATIO_RD) + < prog_full_actual_thresh_negate) begin + prog_full_d <= #`TCQ 1'b0; + end + end + + if (wr_rst_d1==1 && wr_rst_i==0) begin + ideal_prog_full <= #`TCQ 0; + end else begin + ideal_prog_full <= #`TCQ prog_full_d; + end + num_wr_bits <= #`TCQ next_num_wr_bits; + rd_ptr_wrclk <= #`TCQ rd_ptr; + + end //wr_rst_i==0 + end // write always + + + /************************************************************************** + * Read Domain Logic + **************************************************************************/ + always @(posedge RD_CLK or posedge rd_rst_i) begin : gen_fifo_r + + /****** Reset fifo (case 1)***************************************/ + if (rd_rst_i) begin + num_rd_bits <= #`TCQ 0; + next_num_rd_bits = #`TCQ 0; + rd_ptr <= #`TCQ C_RD_DEPTH -1; + rd_pntr <= #`TCQ 0; + wr_pntr_rd1 <= #`TCQ 0; + wr_pntr_rd2 <= #`TCQ 0; + wr_pntr_rd3 <= #`TCQ 0; + wr_pntr_rd <= #`TCQ 0; + wr_ptr_rdclk <= #`TCQ C_WR_DEPTH -1; + if (C_USE_DOUT_RST == 1) begin + ideal_dout <= #`TCQ dout_reset_val; + end else begin + ideal_dout <= #`TCQ ideal_dout; + end + err_type <= #`TCQ 1'b0; + ideal_valid <= #`TCQ 1'b0; +// ideal_empty <= #`TCQ 1'b1; +// ideal_almost_empty <= #`TCQ 1'b1; + ideal_rd_count <= #`TCQ 0; + ideal_prog_empty <= #`TCQ 1'b1; + prog_empty_d <= #`TCQ 1; + + + end else begin //rd_rst_i==0 + + // Synchronize the wr_pntr in read domain + wr_pntr_rd1 <= #`TCQ wr_pntr; + wr_pntr_rd2 <= #`TCQ wr_pntr_rd1; + wr_pntr_rd3 <= #`TCQ wr_pntr_rd2; + wr_pntr_rd <= #`TCQ wr_pntr_rd3; + + + + //Determine the current number of words in the FIFO + tmp_rd_listsize = (C_DEPTH_RATIO_WR > 1) ? num_rd_bits/C_DIN_WIDTH : + num_rd_bits/C_DOUT_WIDTH; + wr_ptr_rdclk_next = wr_ptr; + + if (wr_ptr_rdclk < wr_ptr_rdclk_next) begin + next_num_rd_bits = num_rd_bits + + C_DIN_WIDTH*(wr_ptr_rdclk +C_WR_DEPTH + - wr_ptr_rdclk_next); + end else begin + next_num_rd_bits = num_rd_bits + + C_DIN_WIDTH*(wr_ptr_rdclk - wr_ptr_rdclk_next); + end + + /*****************************************************************/ + // Read Operation - Read Latency 1 + /*****************************************************************/ + if (C_PRELOAD_LATENCY==1 || C_PRELOAD_LATENCY==2) begin + + if (RD_EN == 1'b1) begin + +// if (ideal_empty == 1'b1) begin + if (EMPTY == 1'b1) begin + + //If the FIFO is completely empty, and is reporting empty + if (tmp_rd_listsize/C_DEPTH_RATIO_WR <= 0) + begin + //Do not change the contents of the FIFO + + //Do not acknowledge the read from empty FIFO + ideal_valid <= #`TCQ 1'b0; + //Reminder that FIFO is still empty +// ideal_empty <= #`TCQ 1'b1; +// ideal_almost_empty <= #`TCQ 1'b1; + + ideal_rd_count <= #`TCQ num_read_words_sized_i; + end // if (tmp_rd_listsize <= 0) + + //If the FIFO is one from empty, but it is reporting empty + else if (tmp_rd_listsize/C_DEPTH_RATIO_WR == 1) + begin + //Do not change the contents of the FIFO + + //Do not acknowledge the read from empty FIFO + ideal_valid <= #`TCQ 1'b0; + //Note that FIFO is no longer empty, but is almost empty (has one word left) +// ideal_empty <= #`TCQ 1'b0; +// ideal_almost_empty <= #`TCQ 1'b1; + + ideal_rd_count <= #`TCQ num_read_words_sized_i; + + end // if (tmp_rd_listsize == 1) + + //If the FIFO is two from empty, and is reporting empty + else if (tmp_rd_listsize/C_DEPTH_RATIO_WR == 2) + begin + //Do not change the contents of the FIFO + + //Do not acknowledge the read from empty FIFO + ideal_valid <= #`TCQ 1'b0; + //Fifo has two words, so is neither empty or almost empty +// ideal_empty <= #`TCQ 1'b0; +// ideal_almost_empty <= #`TCQ 1'b0; + + ideal_rd_count <= #`TCQ num_read_words_sized_i; + + end // if (tmp_rd_listsize == 2) + + //If the FIFO is not close to empty, but is reporting that it is + // Treat the FIFO as empty this time, but unset EMPTY flags. + if ((tmp_rd_listsize/C_DEPTH_RATIO_WR > 2) && (tmp_rd_listsize/C_DEPTH_RATIO_WR 2) && (tmp_rd_listsize<=C_FIFO_RD_DEPTH-1)) + end // else: if(ideal_empty == 1'b1) + + else //if (ideal_empty == 1'b0) + begin + + //If the FIFO is completely full, and we are successfully reading from it + if (tmp_rd_listsize/C_DEPTH_RATIO_WR >= C_FIFO_RD_DEPTH) + begin + //Read the value from the FIFO + read_fifo; + next_num_rd_bits = next_num_rd_bits - C_DOUT_WIDTH; + + //Acknowledge the read from the FIFO, no error + ideal_valid <= #`TCQ 1'b1; + //Not close to empty +// ideal_empty <= #`TCQ 1'b0; +// ideal_almost_empty <= #`TCQ 1'b0; + + ideal_rd_count <= #`TCQ num_read_words_sized_i; + + end // if (tmp_rd_listsize == C_FIFO_RD_DEPTH) + + //If the FIFO is not close to being empty + else if ((tmp_rd_listsize/C_DEPTH_RATIO_WR > 2) && (tmp_rd_listsize/C_DEPTH_RATIO_WR<=C_FIFO_RD_DEPTH)) + begin + //Read the value from the FIFO + read_fifo; + next_num_rd_bits = next_num_rd_bits - C_DOUT_WIDTH; + + //Acknowledge the read from the FIFO, no error + ideal_valid <= #`TCQ 1'b1; + //Not close to empty +// ideal_empty <= #`TCQ 1'b0; +// ideal_almost_empty <= #`TCQ 1'b0; + + ideal_rd_count <= #`TCQ num_read_words_sized_i; + + end // if ((tmp_rd_listsize > 2) && (tmp_rd_listsize<=C_FIFO_RD_DEPTH-1)) + + //If the FIFO is two from empty + else if (tmp_rd_listsize/C_DEPTH_RATIO_WR == 2) + begin + //Read the value from the FIFO + read_fifo; + next_num_rd_bits = next_num_rd_bits - C_DOUT_WIDTH; + + //Acknowledge the read from the FIFO, no error + ideal_valid <= #`TCQ 1'b1; + //Fifo is not yet empty. It is going almost_empty +// ideal_empty <= #`TCQ 1'b0; +// ideal_almost_empty <= #`TCQ 1'b1; + + ideal_rd_count <= #`TCQ num_read_words_sized_i; + + end // if (tmp_rd_listsize == 2) + + //If the FIFO is one from empty + else if ((tmp_rd_listsize/C_DEPTH_RATIO_WR == 1)) + begin + //Read the value from the FIFO + read_fifo; + next_num_rd_bits = next_num_rd_bits - C_DOUT_WIDTH; + + //Acknowledge the read from the FIFO, no error + ideal_valid <= #`TCQ 1'b1; + //Note that FIFO is GOING empty +// ideal_empty <= #`TCQ 1'b1; +// ideal_almost_empty <= #`TCQ 1'b1; + + ideal_rd_count <= #`TCQ num_read_words_sized_i; + + end // if (tmp_rd_listsize == 1) + + + //If the FIFO is completely empty + else if (tmp_rd_listsize/C_DEPTH_RATIO_WR <= 0) + begin + //Do not change the contents of the FIFO + + //Do not acknowledge the read from empty FIFO + ideal_valid <= #`TCQ 1'b0; + //Reminder that FIFO is still empty +// ideal_empty <= #`TCQ 1'b1; +// ideal_almost_empty <= #`TCQ 1'b1; + + ideal_rd_count <= #`TCQ num_read_words_sized_i; + + end // if (tmp_rd_listsize <= 0) + + end // if (ideal_empty == 1'b0) + + end //(RD_EN == 1'b1) + + else //if (RD_EN == 1'b0) + begin + //If user did not attempt a read, do not give an ack or err + ideal_valid <= #`TCQ 1'b0; + + //Check for empty +// if (tmp_rd_listsize/C_DEPTH_RATIO_WR <= 0) +// ideal_empty <= #`TCQ 1'b1; +// else +// ideal_empty <= #`TCQ 1'b0; +// +// //Check for almost_empty +// if (tmp_rd_listsize/C_DEPTH_RATIO_WR <= 1) +// ideal_almost_empty <= #`TCQ 1'b1; +// else +// ideal_almost_empty <= #`TCQ 1'b0; + + ideal_rd_count <= #`TCQ num_read_words_sized_i; + + end // else: !if(RD_EN == 1'b1) + + /*****************************************************************/ + // Read Operation - Read Latency 0 + /*****************************************************************/ + end else if (C_PRELOAD_REGS==1 && C_PRELOAD_LATENCY==0) begin + if (RD_EN == 1'b1) begin + +// if (ideal_empty == 1'b1) begin + if (EMPTY == 1'b1) begin + + //If the FIFO is completely empty, and is reporting empty + if (tmp_rd_listsize/C_DEPTH_RATIO_WR <= 0) begin + //Do not change the contents of the FIFO + + //Do not acknowledge the read from empty FIFO + ideal_valid <= #`TCQ 1'b0; + //Reminder that FIFO is still empty +// ideal_empty <= #`TCQ 1'b1; +// ideal_almost_empty <= #`TCQ 1'b1; + + ideal_rd_count <= #`TCQ num_read_words_sized_i; + + //If the FIFO is one from empty, but it is reporting empty + end else if (tmp_rd_listsize/C_DEPTH_RATIO_WR == 1) begin + //Do not change the contents of the FIFO + + //Do not acknowledge the read from empty FIFO + ideal_valid <= #`TCQ 1'b0; + //Note that FIFO is no longer empty, but is almost empty (has one word left) +// ideal_empty <= #`TCQ 1'b0; +// ideal_almost_empty <= #`TCQ 1'b1; + + ideal_rd_count <= #`TCQ num_read_words_sized_i; + + //If the FIFO is two from empty, and is reporting empty + end else if (tmp_rd_listsize/C_DEPTH_RATIO_WR == 2) begin + //Do not change the contents of the FIFO + + //Do not acknowledge the read from empty FIFO + ideal_valid <= #`TCQ 1'b0; + //Fifo has two words, so is neither empty or almost empty +// ideal_empty <= #`TCQ 1'b0; +// ideal_almost_empty <= #`TCQ 1'b0; + + ideal_rd_count <= #`TCQ num_read_words_sized_i; + + //If the FIFO is not close to empty, but is reporting that it is + // Treat the FIFO as empty this time, but unset EMPTY flags. + end else if ((tmp_rd_listsize/C_DEPTH_RATIO_WR > 2) && + (tmp_rd_listsize/C_DEPTH_RATIO_WR 2) && (tmp_rd_listsize<=C_FIFO_RD_DEPTH-1)) + + end else begin + + //If the FIFO is completely full, and we are successfully reading from it + if (tmp_rd_listsize/C_DEPTH_RATIO_WR >= C_FIFO_RD_DEPTH) begin + //Read the value from the FIFO + read_fifo; + next_num_rd_bits = next_num_rd_bits - C_DOUT_WIDTH; + + //Acknowledge the read from the FIFO, no error + ideal_valid <= #`TCQ 1'b1; + //Not close to empty +// ideal_empty <= #`TCQ 1'b0; +// ideal_almost_empty <= #`TCQ 1'b0; + + ideal_rd_count <= #`TCQ num_read_words_sized_i; + + //If the FIFO is not close to being empty + end else if ((tmp_rd_listsize/C_DEPTH_RATIO_WR > 2) && + (tmp_rd_listsize/C_DEPTH_RATIO_WR<=C_FIFO_RD_DEPTH)) begin + //Read the value from the FIFO + read_fifo; + next_num_rd_bits = next_num_rd_bits - C_DOUT_WIDTH; + + //Acknowledge the read from the FIFO, no error + ideal_valid <= #`TCQ 1'b1; + //Not close to empty +// ideal_empty <= #`TCQ 1'b0; +// ideal_almost_empty <= #`TCQ 1'b0; + + ideal_rd_count <= #`TCQ num_read_words_sized_i; + + //If the FIFO is two from empty + end else if (tmp_rd_listsize/C_DEPTH_RATIO_WR == 2) begin + //Read the value from the FIFO + read_fifo; + next_num_rd_bits = next_num_rd_bits - C_DOUT_WIDTH; + + //Acknowledge the read from the FIFO, no error + ideal_valid <= #`TCQ 1'b1; + //Fifo is not yet empty. It is going almost_empty +// ideal_empty <= #`TCQ 1'b0; +// ideal_almost_empty <= #`TCQ 1'b1; + + ideal_rd_count <= #`TCQ num_read_words_sized_i; + + //If the FIFO is one from empty + end else if (tmp_rd_listsize/C_DEPTH_RATIO_WR == 1) begin + //Read the value from the FIFO + read_fifo; + next_num_rd_bits = next_num_rd_bits - C_DOUT_WIDTH; + + //Acknowledge the read from the FIFO, no error + ideal_valid <= #`TCQ 1'b1; + //Note that FIFO is GOING empty +// ideal_empty <= #`TCQ 1'b1; +// ideal_almost_empty <= #`TCQ 1'b1; + + ideal_rd_count <= #`TCQ num_read_words_sized_i; + + //If the FIFO is completely empty + end else if (tmp_rd_listsize/C_DEPTH_RATIO_WR <= 0) begin + //Do not change the contents of the FIFO + + //Do not acknowledge the read from empty FIFO + ideal_valid <= #`TCQ 1'b0; + //Reminder that FIFO is still empty +// ideal_empty <= #`TCQ 1'b1; +// ideal_almost_empty <= #`TCQ 1'b1; + + ideal_rd_count <= #`TCQ num_read_words_sized_i; + + end // if (tmp_rd_listsize <= 0) + + end // if (ideal_empty == 1'b0) + + end else begin//(RD_EN == 1'b0) + + + //If user did not attempt a read, do not give an ack or err + ideal_valid <= #`TCQ 1'b0; + + //Check for empty +// if (tmp_rd_listsize/C_DEPTH_RATIO_WR <= 0) +// ideal_empty <= #`TCQ 1'b1; +// else +// ideal_empty <= #`TCQ 1'b0; +// +// //Check for almost_empty +// if (tmp_rd_listsize/C_DEPTH_RATIO_WR <= 1) +// ideal_almost_empty <= #`TCQ 1'b1; +// else +// ideal_almost_empty <= #`TCQ 1'b0; + + ideal_rd_count <= #`TCQ num_read_words_sized_i; + + end // else: !if(RD_EN == 1'b1) + end //if (C_PRELOAD_REGS==1 && C_PRELOAD_LATENCY==0) + + + /********************************************************* + * Programmable EMPTY flags + *********************************************************/ + //Determine the Assert and Negate thresholds for Programmable Empty + // (Subtract 2 read-sized words when using Preload 0) + + //Single Programmable Empty Constant Threshold + if (C_PROG_EMPTY_TYPE==1) begin + if (C_PRELOAD_REGS==1 && C_PRELOAD_LATENCY==0) begin + prog_empty_actual_thresh_assert = C_PROG_EMPTY_THRESH_ASSERT_VAL-2; + prog_empty_actual_thresh_negate = C_PROG_EMPTY_THRESH_ASSERT_VAL-2; + end + else begin + prog_empty_actual_thresh_assert = C_PROG_EMPTY_THRESH_ASSERT_VAL; + prog_empty_actual_thresh_negate = C_PROG_EMPTY_THRESH_ASSERT_VAL; + end + + //Two Programmable Empty Constant Thresholds + end else if (C_PROG_EMPTY_TYPE==2) begin + if (C_PRELOAD_REGS==1 && C_PRELOAD_LATENCY==0) begin + prog_empty_actual_thresh_assert = C_PROG_EMPTY_THRESH_ASSERT_VAL-2; + prog_empty_actual_thresh_negate = C_PROG_EMPTY_THRESH_NEGATE_VAL-2; + end + else begin + prog_empty_actual_thresh_assert = C_PROG_EMPTY_THRESH_ASSERT_VAL; + prog_empty_actual_thresh_negate = C_PROG_EMPTY_THRESH_NEGATE_VAL; + end + + //Single Programmable Empty Constant Threshold + end else if (C_PROG_EMPTY_TYPE==3) begin + if (C_PRELOAD_REGS==1 && C_PRELOAD_LATENCY==0) begin + prog_empty_actual_thresh_assert = PROG_EMPTY_THRESH-2; + prog_empty_actual_thresh_negate = PROG_EMPTY_THRESH-2; + end + else begin + prog_empty_actual_thresh_assert = PROG_EMPTY_THRESH; + prog_empty_actual_thresh_negate = PROG_EMPTY_THRESH; + + end + //Two Programmable Empty Constant Thresholds + end else if (C_PROG_EMPTY_TYPE==4) begin + if (C_PRELOAD_REGS==1 && C_PRELOAD_LATENCY==0) begin + prog_empty_actual_thresh_assert = PROG_EMPTY_THRESH_ASSERT-2; + prog_empty_actual_thresh_negate = PROG_EMPTY_THRESH_NEGATE-2; + end + else begin + prog_empty_actual_thresh_assert = PROG_EMPTY_THRESH_ASSERT; + prog_empty_actual_thresh_negate = PROG_EMPTY_THRESH_NEGATE; + end + end + + if ((num_read_words_pe/C_DEPTH_RATIO_WR == prog_empty_actual_thresh_assert+1) + && RD_EN) begin + prog_empty_d <= #`TCQ 1'b1; + end else if (num_read_words_pe/C_DEPTH_RATIO_WR + <= prog_empty_actual_thresh_assert) begin + prog_empty_d <= #`TCQ 1'b1; + end else if (num_read_words_pe/C_DEPTH_RATIO_WR + > prog_empty_actual_thresh_negate) begin + prog_empty_d <= #`TCQ 1'b0; + end + + + ideal_prog_empty <= #`TCQ prog_empty_d; + num_rd_bits <= #`TCQ next_num_rd_bits; + wr_ptr_rdclk <= #`TCQ wr_ptr; + end //rd_rst_i==0 + end //always + +endmodule // fifo_generator_v5_2_bhv_ver_as + + +/******************************************************************************* + * Declaration of top-level module + ******************************************************************************/ +module fifo_generator_v5_2_bhv_ver_ss + ( + CLK, RST, SRST, DIN, WR_EN, RD_EN, + PROG_FULL_THRESH, PROG_FULL_THRESH_ASSERT, PROG_FULL_THRESH_NEGATE, + PROG_EMPTY_THRESH, PROG_EMPTY_THRESH_ASSERT, PROG_EMPTY_THRESH_NEGATE, + INJECTSBITERR, INJECTDBITERR, DOUT, FULL, ALMOST_FULL, WR_ACK, OVERFLOW, + EMPTY, ALMOST_EMPTY, VALID, UNDERFLOW, DATA_COUNT, + PROG_FULL, PROG_EMPTY, SBITERR, DBITERR + ); + + /************************************************************************** + * Declare user parameters and their defaults + *************************************************************************/ + parameter C_DATA_COUNT_WIDTH = 2; + parameter C_DIN_WIDTH = 8; + parameter C_DOUT_RST_VAL = ""; + parameter C_DOUT_WIDTH = 8; + parameter C_FULL_FLAGS_RST_VAL = 1; + parameter C_HAS_ALMOST_EMPTY = 0; + parameter C_HAS_ALMOST_FULL = 0; + parameter C_HAS_DATA_COUNT = 0; + parameter C_HAS_OVERFLOW = 0; + parameter C_HAS_RD_DATA_COUNT = 0; + parameter C_HAS_RST = 0; + parameter C_HAS_SRST = 0; + parameter C_HAS_UNDERFLOW = 0; + parameter C_HAS_VALID = 0; + parameter C_HAS_WR_ACK = 0; + parameter C_HAS_WR_DATA_COUNT = 0; + parameter C_IMPLEMENTATION_TYPE = 0; + parameter C_MEMORY_TYPE = 1; + parameter C_OVERFLOW_LOW = 0; + parameter C_PRELOAD_LATENCY = 1; + parameter C_PRELOAD_REGS = 0; + parameter C_PROG_EMPTY_THRESH_ASSERT_VAL = 0; + parameter C_PROG_EMPTY_THRESH_NEGATE_VAL = 0; + parameter C_PROG_EMPTY_TYPE = 0; + parameter C_PROG_FULL_THRESH_ASSERT_VAL = 0; + parameter C_PROG_FULL_THRESH_NEGATE_VAL = 0; + parameter C_PROG_FULL_TYPE = 0; + parameter C_RD_DATA_COUNT_WIDTH = 2; + parameter C_RD_DEPTH = 256; + parameter C_RD_PNTR_WIDTH = 8; + parameter C_UNDERFLOW_LOW = 0; + parameter C_USE_DOUT_RST = 0; + parameter C_USE_EMBEDDED_REG = 0; + parameter C_USE_FWFT_DATA_COUNT = 0; + parameter C_VALID_LOW = 0; + parameter C_WR_ACK_LOW = 0; + parameter C_WR_DATA_COUNT_WIDTH = 2; + parameter C_WR_DEPTH = 256; + parameter C_WR_PNTR_WIDTH = 8; + parameter C_USE_ECC = 0; + parameter C_ENABLE_RST_SYNC = 1; + parameter C_ERROR_INJECTION_TYPE = 0; + + + /************************************************************************** + * Declare Input and Output Ports + *************************************************************************/ + //Inputs + input CLK; + input [C_DIN_WIDTH-1:0] DIN; + input [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH; + input [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_ASSERT; + input [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_NEGATE; + input [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH; + input [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_ASSERT; + input [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_NEGATE; + input RD_EN; + input RST; + input SRST; + input WR_EN; + input INJECTDBITERR; + input INJECTSBITERR; + + //Outputs + output ALMOST_EMPTY; + output ALMOST_FULL; + output [C_DATA_COUNT_WIDTH-1:0] DATA_COUNT; + output [C_DOUT_WIDTH-1:0] DOUT; + output EMPTY; + output FULL; + output OVERFLOW; + output PROG_EMPTY; + output PROG_FULL; + output VALID; + output UNDERFLOW; + output WR_ACK; + output SBITERR; + output DBITERR; + + /************************************************************************* + * Declare the type for each Input/Output port, and connect each I/O + * to it's associated internal signal in the behavioral model + * + * The values for the outputs are assigned in assign statements immediately + * following wire, parameter, and function declarations in this code. + *************************************************************************/ + //Inputs + wire CLK; + wire [C_DIN_WIDTH-1:0] DIN; + wire [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH; + wire [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_ASSERT; + wire [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_NEGATE; + wire [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH; + wire [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_ASSERT; + wire [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_NEGATE; + wire RD_EN; + wire RST; + wire SRST; + wire WR_EN; + wire INJECTSBITERR; + wire INJECTDBITERR; + + //Outputs + wire ALMOST_EMPTY; + wire ALMOST_FULL; + reg [C_DATA_COUNT_WIDTH-1:0] DATA_COUNT; + wire [C_DOUT_WIDTH-1:0] DOUT; + wire EMPTY; + wire FULL; + wire OVERFLOW; + wire PROG_EMPTY; + wire PROG_FULL; + wire VALID; + wire UNDERFLOW; + wire WR_ACK; + wire SBITERR; + wire DBITERR; + + + /*************************************************************************** + * Parameters used as constants + **************************************************************************/ + //When RST is present, set FULL reset value to '1'. + //If core has no RST, make sure FULL powers-on as '0'. + //The reset value assignments for FULL, ALMOST_FULL, and PROG_FULL are not + //changed for v3.2(IP2_Im). When the core has Sync Reset, C_HAS_SRST=1 and C_HAS_RST=0. + // Therefore, during SRST, all the FULL flags reset to 0. + parameter C_HAS_FAST_FIFO = 0; + parameter C_FIFO_WR_DEPTH = C_WR_DEPTH; + parameter C_FIFO_RD_DEPTH = C_RD_DEPTH; + + /************************************************************************** + * FIFO Contents Tracking and Data Count Calculations + *************************************************************************/ + // Memory which will be used to simulate a FIFO + reg [C_DIN_WIDTH-1:0] memory[C_WR_DEPTH-1:0]; + // Local parameters used to determine whether to inject ECC error or not + localparam SYMMETRIC_PORT = (C_DIN_WIDTH == C_DOUT_WIDTH) ? 1 : 0; + localparam ERR_INJECTION = (C_ERROR_INJECTION_TYPE != 0) ? 1 : 0; + localparam ENABLE_ERR_INJECTION = C_USE_ECC && SYMMETRIC_PORT && ERR_INJECTION; + // Array that holds the error injection type (single/double bit error) on + // a specific write operation, which is returned on read to corrupt the + // output data. + reg [1:0] ecc_err[C_WR_DEPTH-1:0]; + + //The amount of data stored in the FIFO at any time is given + // by num_bits. + //num_bits is calculated by from the total words in the FIFO. + reg [31:0] num_bits; + + //The write pointer - tracks write operations + // (Works opposite to core: wr_ptr is a DOWN counter) + reg [31:0] wr_ptr; + + //The write pointer - tracks read operations + // (Works opposite to core: rd_ptr is a DOWN counter) + reg [31:0] rd_ptr; + + /************************** + * Data Count + *************************/ + //Amount of data stored in the FIFO scaled to read words + wire [31:0] num_read_words = num_bits/C_DOUT_WIDTH; + //num_read_words delayed 1 clock cycle + reg [31:0] num_read_words_q; + + //Amount of data stored in the FIFO scaled to write words + wire [31:0] num_write_words = num_bits/C_DIN_WIDTH; + //num_write_words delayed 1 clock cycle + reg [31:0] num_write_words_q; + + + /************************************************************************** + * Internal Registers and wires + *************************************************************************/ + + //Temporary signals used for calculating the model's outputs. These + //are only used in the assign statements immediately following wire, + //parameter, and function declarations. + wire underflow_i; + wire valid_i; + wire valid_out; + + //Ideal FIFO signals. These are the raw output of the behavioral model, + //which behaves like an ideal FIFO. + reg [1:0] err_type = 0; + reg [1:0] err_type_d1 = 0; + reg [C_DOUT_WIDTH-1:0] ideal_dout; + reg [C_DOUT_WIDTH-1:0] ideal_dout_d1; + wire [C_DOUT_WIDTH-1:0] ideal_dout_out; + wire fwft_enabled; + reg ideal_wr_ack; + reg ideal_valid; + reg ideal_overflow; + reg ideal_underflow; + reg ideal_full; + reg ideal_empty; + reg ideal_almost_full; + reg ideal_almost_empty; + reg ideal_prog_full; + reg ideal_prog_empty; + + //Assorted reg values for delayed versions of signals + reg valid_d1; + reg prog_full_d; + reg prog_empty_d; + + + //Internal reset signals + reg rst_asreg =0; + reg rst_asreg_d1 =0; + reg rst_asreg_d2 =0; + reg rst_reg =0; + reg rst_d1 =0; + wire rst_comb; + wire rst_i; + wire srst_i; + + //Delayed version of RST + reg rst_q; + reg rst_qq; + + //user specified value for reseting the size of the fifo + reg [C_DOUT_WIDTH-1:0] dout_reset_val; + + + /**************************************************************************** + * Function Declarations + ***************************************************************************/ + + /************************************************************************** + * write_fifo + * This task writes a word to the FIFO memory and updates the + * write pointer. + * FIFO size is relative to write domain. + ***************************************************************************/ + task write_fifo; + reg [1:0] corrupted_data; + begin + memory[wr_ptr] <= DIN; + // Store the type of error injection (double/single) on write + ecc_err[wr_ptr] <= {INJECTDBITERR,INJECTSBITERR}; + if (wr_ptr == 0) begin + wr_ptr <= C_WR_DEPTH - 1; + end else begin + wr_ptr <= wr_ptr - 1; + end + end + endtask // write_fifo + + /************************************************************************** + * read_fifo + * This task reads a word from the FIFO memory and updates the read + * pointer. It's output is the ideal_dout bus. + * FIFO size is relative to write domain. + ***************************************************************************/ + task read_fifo; + reg [C_DOUT_WIDTH-1:0] tmp_dout; + reg [1:0] tmp_ecc_err; + begin + tmp_dout = memory[rd_ptr][C_DOUT_WIDTH-1:0]; + // Retreive the error injection type. Based on the error injection type + // corrupt the output data. + tmp_ecc_err = ecc_err[rd_ptr]; + if (ENABLE_ERR_INJECTION) begin + if (tmp_ecc_err[1]) begin // Corrupt the output data only for double bit error + if (C_DOUT_WIDTH == 1) + tmp_dout = tmp_dout[C_DOUT_WIDTH-1:0]; + else if (C_DOUT_WIDTH == 2) + tmp_dout = {~tmp_dout[C_DOUT_WIDTH-1],~tmp_dout[C_DOUT_WIDTH-2]}; + else + tmp_dout = {~tmp_dout[C_DOUT_WIDTH-1],~tmp_dout[C_DOUT_WIDTH-2],(tmp_dout << 2)}; + end else begin + tmp_dout = tmp_dout[C_DOUT_WIDTH-1:0]; + end + err_type <= {tmp_ecc_err[1], tmp_ecc_err[0] & !tmp_ecc_err[1]}; + end else begin + err_type <= 0; + end + ideal_dout <= tmp_dout; + + if (rd_ptr == 0) begin + rd_ptr <= C_RD_DEPTH - 1; + end else begin + rd_ptr <= rd_ptr - 1; + end + end + endtask + + /**************************************************************************** + * log2_val + * Returns the 'log2' value for the input value for the supported ratios + ***************************************************************************/ + function [31:0] log2_val; + input [31:0] binary_val; + + begin + if (binary_val == 8) begin + log2_val = 3; + end else if (binary_val == 4) begin + log2_val = 2; + end else begin + log2_val = 1; + end + end + endfunction + + /**************************************************************************** + * hexstr_conv + * Converts a string of type hex to a binary value (for C_DOUT_RST_VAL) + ***************************************************************************/ + function [C_DOUT_WIDTH-1:0] hexstr_conv; + input [(C_DOUT_WIDTH*8)-1:0] def_data; + + integer index,i,j; + reg [3:0] bin; + + begin + index = 0; + hexstr_conv = 'b0; + for( i=C_DOUT_WIDTH-1; i>=0; i=i-1 ) + begin + case (def_data[7:0]) + 8'b00000000 : + begin + bin = 4'b0000; + i = -1; + end + 8'b00110000 : bin = 4'b0000; + 8'b00110001 : bin = 4'b0001; + 8'b00110010 : bin = 4'b0010; + 8'b00110011 : bin = 4'b0011; + 8'b00110100 : bin = 4'b0100; + 8'b00110101 : bin = 4'b0101; + 8'b00110110 : bin = 4'b0110; + 8'b00110111 : bin = 4'b0111; + 8'b00111000 : bin = 4'b1000; + 8'b00111001 : bin = 4'b1001; + 8'b01000001 : bin = 4'b1010; + 8'b01000010 : bin = 4'b1011; + 8'b01000011 : bin = 4'b1100; + 8'b01000100 : bin = 4'b1101; + 8'b01000101 : bin = 4'b1110; + 8'b01000110 : bin = 4'b1111; + 8'b01100001 : bin = 4'b1010; + 8'b01100010 : bin = 4'b1011; + 8'b01100011 : bin = 4'b1100; + 8'b01100100 : bin = 4'b1101; + 8'b01100101 : bin = 4'b1110; + 8'b01100110 : bin = 4'b1111; + default : + begin + bin = 4'bx; + end + endcase + for( j=0; j<4; j=j+1) + begin + if ((index*4)+j < C_DOUT_WIDTH) + begin + hexstr_conv[(index*4)+j] = bin[j]; + end + end + index = index + 1; + def_data = def_data >> 8; + end + end + endfunction + + + /************************************************************************* + * Initialize Signals for clean power-on simulation + *************************************************************************/ + initial begin + num_bits = 0; + num_read_words_q = 0; + num_write_words_q = 0; + rd_ptr = C_RD_DEPTH -1; + wr_ptr = C_WR_DEPTH -1; + dout_reset_val = hexstr_conv(C_DOUT_RST_VAL); + ideal_dout = dout_reset_val; + err_type = 0; + ideal_wr_ack = 1'b0; + ideal_valid = 1'b0; + valid_d1 = 1'b0; + ideal_overflow = 1'b0; + ideal_underflow = 1'b0; + ideal_full = 1'b0; + ideal_empty = 1'b1; + ideal_almost_full = 1'b0; + ideal_almost_empty = 1'b1; + ideal_prog_full = 1'b0; + ideal_prog_empty = 1'b1; + prog_full_d = 1'b0; + prog_empty_d = 1'b1; + rst_q = 1'b0; + rst_qq = 1'b0; + end + + + /************************************************************************* + * Connect the module inputs and outputs to the internal signals of the + * behavioral model. + *************************************************************************/ + //Inputs + /* + wire CLK; + wire [C_DIN_WIDTH-1:0] DIN; + wire [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH; + wire [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_ASSERT; + wire [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_NEGATE; + wire [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH; + wire [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_ASSERT; + wire [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_NEGATE; + wire RD_EN; + wire RST; + wire WR_EN; + */ + + //Outputs + generate + if (C_HAS_ALMOST_EMPTY==1) begin : blockAE10 + assign ALMOST_EMPTY = ideal_almost_empty; + end + endgenerate + + generate + if (C_HAS_ALMOST_FULL==1) begin : blockAF10 + assign ALMOST_FULL = ideal_almost_full; + end + endgenerate + + //Dout may change behavior based on latency + assign fwft_enabled = (C_PRELOAD_LATENCY == 0 && C_PRELOAD_REGS == 1)? + 1: 0; + assign ideal_dout_out= ((C_USE_EMBEDDED_REG==1 && (fwft_enabled == 0)) && + (C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1))? + ideal_dout_d1: ideal_dout; + assign DOUT = ideal_dout_out; + + // Assign SBITERR and DBITERR based on latency + assign SBITERR = (C_ERROR_INJECTION_TYPE == 1 || C_ERROR_INJECTION_TYPE == 3) && + ((C_USE_EMBEDDED_REG==1 && (fwft_enabled == 0)) && + (C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1)) ? + err_type_d1[0]: err_type[0]; + assign DBITERR = (C_ERROR_INJECTION_TYPE == 2 || C_ERROR_INJECTION_TYPE == 3) && + ((C_USE_EMBEDDED_REG==1 && (fwft_enabled == 0)) && + (C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1)) ? + err_type_d1[1]: err_type[1]; + + assign EMPTY = ideal_empty; + assign FULL = ideal_full; + + //Overflow may be active-low + generate + if (C_HAS_OVERFLOW==1) begin : blockOF10 + assign OVERFLOW = ideal_overflow ? !C_OVERFLOW_LOW : C_OVERFLOW_LOW; + end + endgenerate + + assign PROG_EMPTY = ideal_prog_empty; + assign PROG_FULL = ideal_prog_full; + + //Valid may change behavior based on latency or active-low + generate + if (C_HAS_VALID==1) begin : blockVL10 + assign valid_i = (C_PRELOAD_LATENCY==0) ? (RD_EN & ~EMPTY) : ideal_valid; + assign valid_out = (C_PRELOAD_LATENCY==2 && + (C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1))? + valid_d1: valid_i; + assign VALID = valid_out ? !C_VALID_LOW : C_VALID_LOW; + end + endgenerate + + //Trim data count differently depending on set widths + generate + if ((C_HAS_DATA_COUNT == 1) && + (C_DATA_COUNT_WIDTH > C_RD_PNTR_WIDTH)) begin : blockDC1 + always @(num_read_words) + DATA_COUNT = num_read_words[C_RD_PNTR_WIDTH:0]; + end else if (C_HAS_DATA_COUNT == 1) begin : blockDC2 + always @(num_read_words) + DATA_COUNT = num_read_words[C_RD_PNTR_WIDTH-1:C_RD_PNTR_WIDTH-C_DATA_COUNT_WIDTH]; + end //if + endgenerate + + //Underflow may change behavior based on latency or active-low + generate + if (C_HAS_UNDERFLOW==1) begin : blockUF10 +// assign underflow_i = (C_PRELOAD_LATENCY==0) ? (RD_EN & EMPTY) : ideal_underflow; + assign underflow_i = ideal_underflow; + assign UNDERFLOW = underflow_i ? !C_UNDERFLOW_LOW : C_UNDERFLOW_LOW; + end + endgenerate + + + //Write acknowledge may be active low + generate + if (C_HAS_WR_ACK==1) begin : blockWK10 + assign WR_ACK = ideal_wr_ack ? !C_WR_ACK_LOW : C_WR_ACK_LOW; + end + endgenerate + + + /***************************************************************************** + * Internal reset logic + ****************************************************************************/ + assign srst_i = C_HAS_SRST ? SRST : 0; + assign rst_i = C_HAS_RST ? rst_reg : 0; + + generate + if (C_ENABLE_RST_SYNC == 0) begin : gnrst_sync + always @* rst_reg <= 1'b0; + end else if (C_HAS_RST==1) begin : blockRST3 + assign rst_comb = !rst_asreg_d2 && rst_asreg; + + always @(posedge CLK or posedge RST) begin + if (RST == 1'b1) begin + rst_asreg <= #`TCQ 1'b1; + end else begin + if (rst_asreg_d1 == 1'b1) begin + rst_asreg <= #`TCQ 1'b0; + end else begin + rst_asreg <= #`TCQ rst_asreg; + end + end + end + + always @(posedge CLK) begin + rst_asreg_d1 <= #`TCQ rst_asreg; + rst_asreg_d2 <= #`TCQ rst_asreg_d1; + end + + always @(posedge CLK or posedge rst_comb) begin + if (rst_comb == 1'b1) begin + rst_reg <= #`TCQ 1'b1; + end else begin + rst_reg <= #`TCQ 1'b0; + end + end + end + endgenerate + + /************************************************************************** + * Assorted registers for delayed versions of signals + **************************************************************************/ + //Capture delayed version of valid + generate + if (C_HAS_VALID==1) begin : blockVL20 + always @(posedge CLK or posedge rst_i) begin + if (rst_i == 1'b1) begin + valid_d1 <= #`TCQ 1'b0; + end else begin + if (srst_i) begin + valid_d1 <= #`TCQ 1'b0; + end else begin + valid_d1 <= #`TCQ valid_i; + end + end + end // always @ (posedge CLK or posedge rst_i) + end + endgenerate + + //Capture delayed version of dout + always @(posedge CLK or posedge rst_i) begin + if (rst_i == 1'b1) begin + err_type_d1 <= #`TCQ 0; + if (C_USE_DOUT_RST == 1) + ideal_dout_d1 <= #`TCQ dout_reset_val; + end else begin + if (srst_i) begin + err_type_d1 <= #`TCQ 0; + if (C_USE_DOUT_RST == 1) + ideal_dout_d1 <= #`TCQ dout_reset_val; + end else begin + ideal_dout_d1 <= #`TCQ ideal_dout; + err_type_d1 <= #`TCQ err_type; + end + end + end + + /************************************************************************** + * Overflow and Underflow Flag calculation + * (handled separately because they don't support rst) + **************************************************************************/ + generate + if (C_HAS_OVERFLOW==1) begin : blockOF20 + always @(posedge CLK) begin + ideal_overflow <= #`TCQ WR_EN & ideal_full; + end + end + endgenerate + + generate + if (C_HAS_UNDERFLOW==1) begin : blockUF20 + always @(posedge CLK) begin + ideal_underflow <= #`TCQ ideal_empty & RD_EN; + end + end + endgenerate + + /************************************************************************* + * Write and Read Logic + ************************************************************************/ + always @(posedge CLK or posedge rst_i) + begin : gen_wr_ack_resp + + //Register reset + rst_q <= #`TCQ rst_i; + rst_qq <= #`TCQ rst_q; + + end // block: gen_wr_ack_resp + + // block memory has a synchronous reset + always @(posedge CLK) begin : gen_fifo_blkmemdout + //Changed the latency of during async reset to '1' instead of '2' to + // make it consistent with the core. + if (rst_i || rst_q || srst_i) begin + err_type <= #`TCQ 0; + /******Initialize Read Domain Signals*********************************/ + if (C_USE_DOUT_RST == 1 && C_MEMORY_TYPE == 1) begin + ideal_dout <= #`TCQ dout_reset_val; + end + end + end //always + + always @(posedge CLK or posedge rst_i) begin : gen_fifo + + /****** Reset fifo - Asynchronous Reset**********************************/ + //Changed the latency of during async reset to '1' instead of '2' to + // make it consistent with the core. + if (rst_i) begin //v3.2 + /******Initialize Generic FIFO constructs*****************************/ + num_bits <= #`TCQ 0; + wr_ptr <= #`TCQ C_WR_DEPTH - 1; + rd_ptr <= #`TCQ C_RD_DEPTH - 1; + num_read_words_q <= #`TCQ 0; + num_write_words_q <= #`TCQ 0; + err_type <= #`TCQ 0; + + + /******Initialize Write Domain Signals********************************/ + ideal_wr_ack <= #`TCQ 0; + ideal_full <= #`TCQ C_FULL_FLAGS_RST_VAL; + ideal_almost_full <= #`TCQ C_FULL_FLAGS_RST_VAL; + + /******Initialize Read Domain Signals*********************************/ + if (C_MEMORY_TYPE != 1 && C_USE_DOUT_RST == 1) begin + ideal_dout <= #`TCQ dout_reset_val; + end + ideal_valid <= #`TCQ 1'b0; + ideal_empty <= #`TCQ 1'b1; + ideal_almost_empty <= #`TCQ 1'b1; + + end else begin + if (srst_i) begin + // SRST is available only for Sync BRAM and Sync DRAM. + // Not for SSHFT. + if (C_MEMORY_TYPE == 1 || C_MEMORY_TYPE == 2 || C_MEMORY_TYPE == 3) begin + /******Initialize Generic FIFO constructs***********************/ + num_bits <= #`TCQ 0; + wr_ptr <= #`TCQ C_WR_DEPTH - 1; + rd_ptr <= #`TCQ C_RD_DEPTH - 1; + num_read_words_q <= #`TCQ 0; + num_write_words_q <= #`TCQ 0; + err_type <= #`TCQ 0; + + /******Initialize Write Domain Signals**************************/ + ideal_wr_ack <= #`TCQ 0; + ideal_full <= #`TCQ 0; //'0' + ideal_almost_full <= #`TCQ 0; //'0' + + /******Initialize Read Domain Signals***************************/ + //Reset DOUT of Sync DRAM/Shift RAM. Sync BRAM DOUT was reset in the + // above always block. + if (C_USE_DOUT_RST == 1 && (C_MEMORY_TYPE == 2 || C_MEMORY_TYPE == 3)) begin + ideal_dout <= #`TCQ dout_reset_val; + end + ideal_valid <= #`TCQ 1'b0; + ideal_empty <= #`TCQ 1'b1; + ideal_almost_empty <= #`TCQ 1'b1; + end + + end else begin //normal operating conditions + /********************************************************************/ + // Synchronous FIFO Condition #1 : Writing and not reading + /********************************************************************/ + if (WR_EN & ~RD_EN) begin + + /*********************************/ + //If the FIFO is full, do NOT perform the write, + // update flags accordingly + /*********************************/ + if (num_write_words >= C_FIFO_WR_DEPTH) begin + ideal_wr_ack <= #`TCQ 0; + + //still full + ideal_full <= #`TCQ 1'b1; + ideal_almost_full <= #`TCQ 1'b1; + + //write unsuccessful - do not change contents + + // no read attempted + ideal_valid <= #`TCQ 1'b0; + + //Not near empty + ideal_empty <= #`TCQ 1'b0; + ideal_almost_empty <= #`TCQ 1'b0; + + + /*********************************/ + //If the FIFO is reporting FULL + // (Startup condition) + /*********************************/ + end else if ((num_write_words < C_FIFO_WR_DEPTH) && (ideal_full == 1'b1)) begin + ideal_wr_ack <= #`TCQ 0; + + //still full + ideal_full <= #`TCQ 1'b0; + ideal_almost_full <= #`TCQ 1'b0; + + //write unsuccessful - do not change contents + + // no read attempted + ideal_valid <= #`TCQ 1'b0; + + //FIFO EMPTY in this state can not be determined + //ideal_empty <= 1'b0; + //ideal_almost_empty <= 1'b0; + + + /*********************************/ + //If the FIFO is one from full + /*********************************/ + end else if (num_write_words == C_FIFO_WR_DEPTH-1) begin + //good write + ideal_wr_ack <= #`TCQ 1; + + //FIFO is one from FULL and going FULL + ideal_full <= #`TCQ 1'b1; + ideal_almost_full <= #`TCQ 1'b1; + + //Add input data + write_fifo; + + // no read attempted + ideal_valid <= #`TCQ 1'b0; + + //Not near empty + ideal_empty <= #`TCQ 1'b0; + ideal_almost_empty <= #`TCQ 1'b0; + + num_bits <= num_bits + C_DIN_WIDTH; + + /*********************************/ + //If the FIFO is 2 from full + /*********************************/ + end else if (num_write_words == C_FIFO_WR_DEPTH-2) begin + //good write + ideal_wr_ack <= #`TCQ 1; + + //2 from full, and writing, so set almost_full + ideal_full <= #`TCQ 1'b0; + ideal_almost_full <= #`TCQ 1'b1; + + //Add input data + write_fifo; + + //no read attempted + ideal_valid <= #`TCQ 1'b0; + + //Not near empty + ideal_empty <= #`TCQ 1'b0; + ideal_almost_empty <= #`TCQ 1'b0; + + num_bits <= #`TCQ num_bits + C_DIN_WIDTH; + + /*********************************/ + //If the FIFO is ALMOST EMPTY + /*********************************/ + end else if (num_read_words == 1) begin + //good write + ideal_wr_ack <= #`TCQ 1; + + //Not near FULL + ideal_full <= #`TCQ 1'b0; + ideal_almost_full <= #`TCQ 1'b0; + + //Add input data + write_fifo; + + // no read attempted + ideal_valid <= #`TCQ 1'b0; + + //Leaving ALMOST_EMPTY + ideal_empty <= #`TCQ 1'b0; + ideal_almost_empty <= #`TCQ 1'b0; + + num_bits <= #`TCQ num_bits + C_DIN_WIDTH; + + /*********************************/ + //If the FIFO is EMPTY + /*********************************/ + end else if (num_read_words == 0) begin + // good write + ideal_wr_ack <= #`TCQ 1; + + //Not near FULL + ideal_full <= #`TCQ 1'b0; + ideal_almost_full <= #`TCQ 1'b0; + + //Add input data + write_fifo; + + // no read attempted + ideal_valid <= #`TCQ 1'b0; + + //Leaving EMPTY (still ALMOST_EMPTY) + ideal_empty <= #`TCQ 1'b0; + ideal_almost_empty <= #`TCQ 1'b1; + + num_bits <= #`TCQ num_bits + C_DIN_WIDTH; + + /*********************************/ + //If the FIFO is not near EMPTY or FULL + /*********************************/ + end else begin + // good write + ideal_wr_ack <= #`TCQ 1; + + //Not near FULL + ideal_full <= #`TCQ 1'b0; + ideal_almost_full <= #`TCQ 1'b0; + + //Add input data + write_fifo; + + // no read attempted + ideal_valid <= #`TCQ 1'b0; + + //Not near EMPTY + ideal_empty <= #`TCQ 1'b0; + ideal_almost_empty <= #`TCQ 1'b0; + + num_bits <= #`TCQ num_bits + C_DIN_WIDTH; + + end // average case + + + /******************************************************************/ + // Synchronous FIFO Condition #2 : Reading and not writing + /******************************************************************/ + end else if (~WR_EN & RD_EN) begin + + /*********************************/ + //If the FIFO is EMPTY + /*********************************/ + if ((num_read_words == 0) || (ideal_empty == 1'b1)) begin + //no write attemped + ideal_wr_ack <= #`TCQ 0; + + //FIFO is not near FULL + ideal_full <= #`TCQ 1'b0; + ideal_almost_full <= #`TCQ 1'b0; + + //Read will fail + ideal_valid <= #`TCQ 1'b0; + + //FIFO is still empty + ideal_empty <= #`TCQ 1'b1; + ideal_almost_empty <= #`TCQ 1'b1; + + //No read + + /*********************************/ + //If the FIFO is ALMOST EMPTY + /*********************************/ + end else if (num_read_words == 1) begin + //no write attempted + ideal_wr_ack <= #`TCQ 0; + + //FIFO is not near FULL + ideal_full <= #`TCQ 1'b0; + ideal_almost_full <= #`TCQ 1'b0; + + //Read successful + ideal_valid <= #`TCQ 1'b1; + + //This read will make FIFO go empty + ideal_empty <= #`TCQ 1'b1; + ideal_almost_empty <= #`TCQ 1'b1; + + //Get the data from the FIFO + read_fifo; + num_bits <= #`TCQ num_bits - C_DIN_WIDTH; + + + /*********************************/ + //If the FIFO is 2 from EMPTY + /*********************************/ + end else if (num_read_words == 2) begin + + //no write attempted + ideal_wr_ack <= #`TCQ 0; + + //FIFO is not near FULL + ideal_full <= #`TCQ 1'b0; + ideal_almost_full <= #`TCQ 1'b0; + + //Read successful + ideal_valid <= #`TCQ 1'b1; + + //FIFO is going ALMOST_EMPTY + ideal_empty <= #`TCQ 1'b0; + ideal_almost_empty <= #`TCQ 1'b1; + + //Get the data from the FIFO + read_fifo; + num_bits <= #`TCQ num_bits - C_DOUT_WIDTH; + + + + /*********************************/ + //If the FIFO is one from full + /*********************************/ + end else if (num_write_words == C_FIFO_WR_DEPTH-1) begin + + //no write attempted + ideal_wr_ack <= #`TCQ 0; + + //FIFO is leaving ALMOST FULL + ideal_full <= #`TCQ 1'b0; + ideal_almost_full <= #`TCQ 1'b0; + + //Read successful + ideal_valid <= #`TCQ 1'b1; + + //Not near empty + ideal_empty <= #`TCQ 1'b0; + ideal_almost_empty <= #`TCQ 1'b0; + + //Read from the FIFO + read_fifo; + num_bits <= #`TCQ num_bits - C_DOUT_WIDTH; + + + /*********************************/ + // FIFO is FULL + /*********************************/ + end else if (num_write_words >= C_FIFO_WR_DEPTH) + begin + //no write attempted + ideal_wr_ack <= #`TCQ 0; + + //FIFO is leaving FULL, but is still ALMOST_FULL + ideal_full <= #`TCQ 1'b0; + ideal_almost_full <= #`TCQ 1'b1; + + //Read successful + ideal_valid <= #`TCQ 1'b1; + + //Not near empty + ideal_empty <= #`TCQ 1'b0; + ideal_almost_empty <= #`TCQ 1'b0; + + //Read from the FIFO + read_fifo; + num_bits <= #`TCQ num_bits - C_DOUT_WIDTH; + + /*********************************/ + //If the FIFO is not near EMPTY or FULL + /*********************************/ + end else begin + //no write attemped + ideal_wr_ack <= #`TCQ 0; + + //Not near empty + ideal_full <= #`TCQ 1'b0; + ideal_almost_full <= #`TCQ 1'b0; + + //Read successful + ideal_valid <= #`TCQ 1'b1; + + //Not near empty + ideal_empty <= #`TCQ 1'b0; + ideal_almost_empty <= #`TCQ 1'b0; + + //Read from the FIFO + read_fifo; + num_bits <= #`TCQ num_bits - C_DOUT_WIDTH; + + + end // average read + + + /******************************************************************/ + // Synchronous FIFO Condition #3 : Reading and writing + /******************************************************************/ + end else if (WR_EN & RD_EN) begin + + /*********************************/ + // FIFO is FULL + /*********************************/ + if (num_write_words >= C_FIFO_WR_DEPTH) begin + + ideal_wr_ack <= #`TCQ 0; + + //Read will be successful, so FIFO will leave FULL + ideal_full <= #`TCQ 1'b0; + ideal_almost_full <= #`TCQ 1'b1; + + //Read successful + ideal_valid <= #`TCQ 1'b1; + + //Not near empty + ideal_empty <= #`TCQ 1'b0; + ideal_almost_empty <= #`TCQ 1'b0; + + //Read from the FIFO + read_fifo; + num_bits <= #`TCQ num_bits - C_DOUT_WIDTH; + + + /*********************************/ + // FIFO is reporting FULL, but it is empty + // (This is a special case, when coming out of RST + /*********************************/ + end else if ((num_write_words == 0) && (ideal_full == 1'b1)) begin + + ideal_wr_ack <= #`TCQ 0; + + //Read will be successful, so FIFO will leave FULL + ideal_full <= #`TCQ 1'b0; + ideal_almost_full <= #`TCQ 1'b0; + + //Read unsuccessful + ideal_valid <= #`TCQ 1'b0; + + //Report empty condition + ideal_empty <= #`TCQ 1'b1; + ideal_almost_empty <= #`TCQ 1'b1; + + //Do not read from empty FIFO + // Read from the FIFO + + + /*********************************/ + //If the FIFO is one from full + /*********************************/ + end else if (num_write_words == C_FIFO_WR_DEPTH-1) begin + + //Write successful + ideal_wr_ack <= #`TCQ 1; + + //FIFO will remain ALMOST_FULL + ideal_full <= #`TCQ 1'b0; + ideal_almost_full <= #`TCQ 1'b1; + + // put the data into the FIFO + write_fifo; + + //Read successful + ideal_valid <= #`TCQ 1'b1; + + //Not near empty + ideal_empty <= #`TCQ 1'b0; + ideal_almost_empty <= #`TCQ 1'b0; + + //Read from the FIFO + read_fifo; + num_bits <= #`TCQ num_bits + C_DIN_WIDTH - C_DOUT_WIDTH; + + /*********************************/ + //If the FIFO is ALMOST EMPTY + /*********************************/ + end else if (num_read_words == 1) begin + + //Write successful + ideal_wr_ack <= #`TCQ 1; + + // Not near FULL + ideal_full <= #`TCQ 1'b0; + ideal_almost_full <= #`TCQ 1'b0; + + // put the data into the FIFO + write_fifo; + + //Read successful + ideal_valid <= #`TCQ 1'b1; + + //FIFO will stay ALMOST_EMPTY + ideal_empty <= #`TCQ 1'b0; + ideal_almost_empty <= #`TCQ 1'b1; + + //Read from the FIFO + read_fifo; + num_bits <= #`TCQ num_bits + C_DIN_WIDTH - C_DOUT_WIDTH; + + + /*********************************/ + //If the FIFO is EMPTY + /*********************************/ + end else if (num_read_words == 0) begin + + //Write successful + ideal_wr_ack <= #`TCQ 1; + + // Not near FULL + ideal_full <= #`TCQ 1'b0; + ideal_almost_full <= #`TCQ 1'b0; + + // put the data into the FIFO + write_fifo; + + //Read will fail + ideal_valid <= #`TCQ 1'b0; + + //FIFO will leave EMPTY + ideal_empty <= #`TCQ 1'b0; + ideal_almost_empty <= #`TCQ 1'b1; + + // No read + num_bits <= #`TCQ num_bits + C_DIN_WIDTH; + + + /*********************************/ + //If the FIFO is not near EMPTY or FULL + /*********************************/ + end else begin + + //Write successful + ideal_wr_ack <= #`TCQ 1; + + // Not near FULL + ideal_full <= #`TCQ 1'b0; + ideal_almost_full <= #`TCQ 1'b0; + + // put the data into the FIFO + write_fifo; + + //Read successful + ideal_valid <= #`TCQ 1'b1; + + // Not near EMPTY + ideal_empty <= #`TCQ 1'b0; + ideal_almost_empty <= #`TCQ 1'b0; + + //Read from the FIFO + read_fifo; + num_bits <= #`TCQ num_bits + C_DIN_WIDTH - C_DOUT_WIDTH; + + end // average case + + /******************************************************************/ + // Synchronous FIFO Condition #4 : Not reading or writing + /******************************************************************/ + end else begin + + /*********************************/ + // FIFO is FULL + /*********************************/ + if (num_write_words >= C_FIFO_WR_DEPTH) begin + + //No write + ideal_wr_ack <= #`TCQ 0; + ideal_full <= #`TCQ 1'b1; + ideal_almost_full <= #`TCQ 1'b1; + + //No read + ideal_valid <= #`TCQ 1'b0; + ideal_empty <= #`TCQ 1'b0; + ideal_almost_empty <= #`TCQ 1'b0; + + //No change to memory + + /*********************************/ + //If the FIFO is one from full + /*********************************/ + end else if (num_write_words == C_FIFO_WR_DEPTH-1) begin + + //No write + ideal_wr_ack <= #`TCQ 0; + ideal_full <= #`TCQ 1'b0; + ideal_almost_full <= #`TCQ 1'b1; + + //No read + ideal_valid <= #`TCQ 1'b0; + ideal_empty <= #`TCQ 1'b0; + ideal_almost_empty <= #`TCQ 1'b0; + + //No change to memory + + /*********************************/ + //If the FIFO is ALMOST EMPTY + /*********************************/ + end else if (num_read_words == 1) begin + //No write + ideal_wr_ack <= #`TCQ 0; + ideal_full <= #`TCQ 1'b0; + ideal_almost_full <= #`TCQ 1'b0; + + //No read + ideal_valid <= #`TCQ 1'b0; + ideal_empty <= #`TCQ 1'b0; + ideal_almost_empty <= #`TCQ 1'b1; + + //No change to memory + + end // almost empty + + + /*********************************/ + //If the FIFO is EMPTY + /*********************************/ + else if (num_read_words == 0) + begin + //No write + ideal_wr_ack <= #`TCQ 0; + ideal_full <= #`TCQ 1'b0; + ideal_almost_full <= #`TCQ 1'b0; + + //No read + ideal_valid <= #`TCQ 1'b0; + ideal_empty <= #`TCQ 1'b1; + ideal_almost_empty <= #`TCQ 1'b1; + + //No change to memory + + /*********************************/ + //If the FIFO is not near EMPTY or FULL + /*********************************/ + end else begin + + //No write + ideal_wr_ack <= #`TCQ 0; + ideal_full <= #`TCQ 1'b0; + ideal_almost_full <= #`TCQ 1'b0; + + //No read + ideal_valid <= #`TCQ 1'b0; + ideal_empty <= #`TCQ 1'b0; + ideal_almost_empty <= #`TCQ 1'b0; + + //No change to memory + + end // average case + + end // neither reading or writing + + num_read_words_q <= #`TCQ num_read_words; + num_write_words_q <= #`TCQ num_write_words; + + end //normal operating conditions + end + + end // block: gen_fifo + + + always @(posedge CLK or posedge rst_i) begin : gen_fifo_p + + /****** Reset fifo - Async Reset****************************************/ + //The latency of de-assertion of the flags is reduced by 1 to be + // consistent with the core. + if (rst_i) begin + ideal_prog_full <= #`TCQ C_FULL_FLAGS_RST_VAL; + ideal_prog_empty <= #`TCQ 1'b1; + prog_full_d <= #`TCQ C_FULL_FLAGS_RST_VAL; + prog_empty_d <= #`TCQ 1'b1; + + end else begin + if (srst_i) begin + //SRST is available only for Sync BRAM and Sync DRAM. Not for SSHFT. + if (C_MEMORY_TYPE == 1 || C_MEMORY_TYPE == 2 || C_MEMORY_TYPE == 3) begin + ideal_prog_full <= #`TCQ 1'b0; + ideal_prog_empty <= #`TCQ 1'b1; + prog_full_d <= #`TCQ 1'b0; + prog_empty_d <= #`TCQ 1'b1; + end + end else begin + + /*************************************************************** + * Programmable FULL flags + ****************************************************************/ + //calculation for standard fifo and latency =2 + if (! (C_PRELOAD_REGS==1 && C_PRELOAD_LATENCY==0) ) begin + //Single constant threshold + if (C_PROG_FULL_TYPE == 1) begin + if ((num_write_words >= C_PROG_FULL_THRESH_ASSERT_VAL-1) + && WR_EN && !RD_EN) begin + prog_full_d <= #`TCQ 1'b1; + end else if (((num_write_words == C_PROG_FULL_THRESH_ASSERT_VAL) + && RD_EN && !WR_EN) || (rst_q && !rst_i)) begin + prog_full_d <= #`TCQ 1'b0; + end + + //Dual constant thresholds + end else if (C_PROG_FULL_TYPE == 2) begin + if ((num_write_words == C_PROG_FULL_THRESH_ASSERT_VAL-1) + && WR_EN && !RD_EN) begin + prog_full_d <= #`TCQ 1'b1; + end else if ((num_write_words == C_PROG_FULL_THRESH_NEGATE_VAL) + && RD_EN && !WR_EN) begin + prog_full_d <= #`TCQ 1'b0; + end + + //Single input threshold + end else if (C_PROG_FULL_TYPE == 3) begin + if ((num_write_words == PROG_FULL_THRESH-1) + && WR_EN && !RD_EN) begin + prog_full_d <= #`TCQ 1'b1; + end else if ((num_write_words == PROG_FULL_THRESH) + && !WR_EN && RD_EN) begin + prog_full_d <= #`TCQ 1'b0; + end else if (num_write_words >= PROG_FULL_THRESH) begin + prog_full_d <= #`TCQ 1'b1; + end else if (num_write_words < PROG_FULL_THRESH) begin + prog_full_d <= #`TCQ 1'b0; + end + + //Dual input thresholds + end else begin + if ((num_write_words == PROG_FULL_THRESH_ASSERT-1) + && WR_EN && !RD_EN) begin + prog_full_d <= #`TCQ 1'b1; + end else if ((num_write_words == PROG_FULL_THRESH_NEGATE) + && !WR_EN && RD_EN)begin + prog_full_d <= #`TCQ 1'b0; + end else if (num_write_words >= PROG_FULL_THRESH_ASSERT) begin + prog_full_d <= #`TCQ 1'b1; + end else if (num_write_words < PROG_FULL_THRESH_NEGATE) begin + prog_full_d <= #`TCQ 1'b0; + end + end + end // (~ (C_PRELOAD_REGS==1 && C_PRELOAD_LATENCY==0) ) + + + //calculation for FWFT fifo + if (C_PRELOAD_REGS==1 && C_PRELOAD_LATENCY==0) begin + if (C_PROG_FULL_TYPE == 1) begin + if ((num_write_words >= C_PROG_FULL_THRESH_ASSERT_VAL-1 - 2) + && WR_EN && !RD_EN) begin + prog_full_d <= #`TCQ 1'b1; + end else if (((num_write_words == C_PROG_FULL_THRESH_ASSERT_VAL - 2) + && RD_EN && !WR_EN) || (rst_q && !rst_i)) begin + prog_full_d <= #`TCQ 1'b0; + end + + //Dual constant thresholds + end else if (C_PROG_FULL_TYPE == 2) begin + if ((num_write_words == C_PROG_FULL_THRESH_ASSERT_VAL-1 - 2) + && WR_EN && !RD_EN) begin + prog_full_d <= #`TCQ 1'b1; + end else if ((num_write_words == C_PROG_FULL_THRESH_NEGATE_VAL - 2) + && RD_EN && !WR_EN) begin + prog_full_d <= #`TCQ 1'b0; + end + + //Single input threshold + end else if (C_PROG_FULL_TYPE == 3) begin + if ((num_write_words == PROG_FULL_THRESH-1 - 2) + && WR_EN && !RD_EN) begin + prog_full_d <= #`TCQ 1'b1; + end else if ((num_write_words == PROG_FULL_THRESH - 2) + && !WR_EN && RD_EN) begin + prog_full_d <= #`TCQ 1'b0; + end else if (num_write_words >= PROG_FULL_THRESH - 2) begin + prog_full_d <= #`TCQ 1'b1; + end else if (num_write_words < PROG_FULL_THRESH - 2) begin + prog_full_d <= #`TCQ 1'b0; + end + + //Dual input thresholds + end else begin + if ((num_write_words == PROG_FULL_THRESH_ASSERT-1 - 2) + && WR_EN && !RD_EN) begin + prog_full_d <= #`TCQ 1'b1; + end else if ((num_write_words == PROG_FULL_THRESH_NEGATE - 2) + && !WR_EN && RD_EN)begin + prog_full_d <= #`TCQ 1'b0; + end else if (num_write_words >= PROG_FULL_THRESH_ASSERT - 2) begin + prog_full_d <= #`TCQ 1'b1; + end else if (num_write_words < PROG_FULL_THRESH_NEGATE - 2) begin + prog_full_d <= #`TCQ 1'b0; + end + end + end // (C_PRELOAD_REGS==1 && C_PRELOAD_LATENCY==0) + + /***************************************************************** + * Programmable EMPTY flags + ****************************************************************/ + //calculation for standard fifo and latency = 2 + if (! (C_PRELOAD_REGS==1 && C_PRELOAD_LATENCY==0) ) begin + //Single constant threshold + if (C_PROG_EMPTY_TYPE == 1) begin + if ((num_read_words == C_PROG_EMPTY_THRESH_ASSERT_VAL+1) + && RD_EN && !WR_EN) begin + prog_empty_d <= #`TCQ 1'b1; + end else if ((num_read_words == C_PROG_EMPTY_THRESH_ASSERT_VAL) + && WR_EN && !RD_EN) begin + prog_empty_d <= #`TCQ 1'b0; + end + //Dual constant thresholds + end else if (C_PROG_EMPTY_TYPE == 2) begin + if ((num_read_words == C_PROG_EMPTY_THRESH_ASSERT_VAL+1) + && RD_EN && !WR_EN) begin + prog_empty_d <= #`TCQ 1'b1; + end else if ((num_read_words == C_PROG_EMPTY_THRESH_NEGATE_VAL) + && !RD_EN && WR_EN) begin + prog_empty_d <= #`TCQ 1'b0; + end + + //Single input threshold + end else if (C_PROG_EMPTY_TYPE == 3) begin + if ((num_read_words == PROG_EMPTY_THRESH+1) + && RD_EN && !WR_EN) begin + prog_empty_d <= #`TCQ 1'b1; + end else if ((num_read_words == PROG_EMPTY_THRESH) + && !RD_EN && WR_EN) begin + prog_empty_d <= #`TCQ 1'b0; + end else if (num_read_words <= PROG_EMPTY_THRESH) begin + prog_empty_d <= #`TCQ 1'b1; + end else if (num_read_words > PROG_EMPTY_THRESH)begin + prog_empty_d <= #`TCQ 1'b0; + end + + //Dual input thresholds + end else begin + if (num_read_words <= PROG_EMPTY_THRESH_ASSERT) begin + prog_empty_d <= #`TCQ 1'b1; + end else if ((num_read_words == PROG_EMPTY_THRESH_ASSERT+1) + && RD_EN && !WR_EN) begin + prog_empty_d <= #`TCQ 1'b1; + end else if (num_read_words > PROG_EMPTY_THRESH_NEGATE)begin + prog_empty_d <= #`TCQ 1'b0; + end else if ((num_read_words == PROG_EMPTY_THRESH_NEGATE) + && !RD_EN && WR_EN) begin + prog_empty_d <= #`TCQ 1'b0; + end + end + end // (~ (C_PRELOAD_REGS==1 && C_PRELOAD_LATENCY==0) ) + + //calculation for FWFT fifo + if (C_PRELOAD_REGS==1 && C_PRELOAD_LATENCY==0) begin + //Single constant threshold + if (C_PROG_EMPTY_TYPE == 1) begin + if ((num_read_words == C_PROG_EMPTY_THRESH_ASSERT_VAL+1 - 2) + && RD_EN && !WR_EN) begin + prog_empty_d <= #`TCQ 1'b1; + end else if ((num_read_words == C_PROG_EMPTY_THRESH_ASSERT_VAL - 2) + && WR_EN && !RD_EN) begin + prog_empty_d <= #`TCQ 1'b0; + end + //Dual constant thresholds + end else if (C_PROG_EMPTY_TYPE == 2) begin + if ((num_read_words == C_PROG_EMPTY_THRESH_ASSERT_VAL+1 - 2) + && RD_EN && !WR_EN) begin + prog_empty_d <= #`TCQ 1'b1; + end else if ((num_read_words == C_PROG_EMPTY_THRESH_NEGATE_VAL - 2) + && !RD_EN && WR_EN) begin + prog_empty_d <= #`TCQ 1'b0; + end + + //Single input threshold + end else if (C_PROG_EMPTY_TYPE == 3) begin + if ((num_read_words == PROG_EMPTY_THRESH+1 - 2) + && RD_EN && !WR_EN) begin + prog_empty_d <= #`TCQ 1'b1; + end else if ((num_read_words == PROG_EMPTY_THRESH - 2) + && !RD_EN && WR_EN) begin + prog_empty_d <= #`TCQ 1'b0; + end else if (num_read_words <= PROG_EMPTY_THRESH - 2) begin + prog_empty_d <= #`TCQ 1'b1; + end else if (num_read_words > PROG_EMPTY_THRESH - 2)begin + prog_empty_d <= #`TCQ 1'b0; + end + + //Dual input thresholds + end else begin + if (num_read_words <= PROG_EMPTY_THRESH_ASSERT - 2) begin + prog_empty_d <= #`TCQ 1'b1; + end else if ((num_read_words == PROG_EMPTY_THRESH_ASSERT+1 - 2) + && RD_EN && !WR_EN) begin + prog_empty_d <= #`TCQ 1'b1; + end else if (num_read_words > PROG_EMPTY_THRESH_NEGATE - 2)begin + prog_empty_d <= #`TCQ 1'b0; + end else if ((num_read_words == PROG_EMPTY_THRESH_NEGATE - 2) + && !RD_EN && WR_EN) begin + prog_empty_d <= #`TCQ 1'b0; + end + end + end // (~ (C_PRELOAD_REGS==1 && C_PRELOAD_LATENCY==0) ) + + ideal_prog_empty <= prog_empty_d; + if (rst_q && !rst_i) begin + ideal_prog_full <= #`TCQ 1'b0; + prog_full_d <= #`TCQ 1'b0; + end else begin + ideal_prog_full <= #`TCQ prog_full_d; + end + + end //if (srst_i) begin + end //if (rst_i) begin + end //always @(posedge CLK or posedge rst_i) begin : gen_fifo_p +endmodule // fifo_generator_v5_2_bhv_ver_ss + + + +/************************************************************************** + * First-Word Fall-Through module (preload 0) + **************************************************************************/ +module fifo_generator_v5_2_bhv_ver_preload0 + ( + RD_CLK, + RD_RST, + SRST, + RD_EN, + FIFOEMPTY, + FIFODATA, + FIFOSBITERR, + FIFODBITERR, + USERDATA, + USERVALID, + USERUNDERFLOW, + USEREMPTY, + USERALMOSTEMPTY, + RAMVALID, + FIFORDEN, + USERSBITERR, + USERDBITERR + ); + + parameter C_DOUT_RST_VAL = ""; + parameter C_DOUT_WIDTH = 8; + parameter C_HAS_RST = 0; + parameter C_ENABLE_RST_SYNC = 0; + parameter C_HAS_SRST = 0; + parameter C_USE_DOUT_RST = 0; + parameter C_USERVALID_LOW = 0; + parameter C_USERUNDERFLOW_LOW = 0; + + //Inputs + input RD_CLK; + input RD_RST; + input SRST; + input RD_EN; + input FIFOEMPTY; + input [C_DOUT_WIDTH-1:0] FIFODATA; + input FIFOSBITERR; + input FIFODBITERR; + + //Outputs + output [C_DOUT_WIDTH-1:0] USERDATA; + output USERVALID; + output USERUNDERFLOW; + output USEREMPTY; + output USERALMOSTEMPTY; + output RAMVALID; + output FIFORDEN; + output USERSBITERR; + output USERDBITERR; + + //Inputs + wire RD_CLK; + wire RD_RST; + wire RD_EN; + wire FIFOEMPTY; + wire [C_DOUT_WIDTH-1:0] FIFODATA; + wire FIFOSBITERR; + wire FIFODBITERR; + + //Outputs + reg [C_DOUT_WIDTH-1:0] USERDATA; + wire USERVALID; + wire USERUNDERFLOW; + wire USEREMPTY; + wire USERALMOSTEMPTY; + wire RAMVALID; + wire FIFORDEN; + reg USERSBITERR; + reg USERDBITERR; + + //Internal signals + wire preloadstage1; + wire preloadstage2; + reg ram_valid_i; + reg read_data_valid_i; + wire ram_regout_en; + wire ram_rd_en; + reg empty_i = 1'b1; + reg empty_q = 1'b1; + reg rd_en_q = 1'b0; + reg almost_empty_i = 1'b1; + reg almost_empty_q = 1'b1; + wire rd_rst_i; + wire srst_i; + + +/************************************************************************* +* FUNCTIONS +*************************************************************************/ + + /************************************************************************* + * hexstr_conv + * Converts a string of type hex to a binary value (for C_DOUT_RST_VAL) + ***********************************************************************/ + function [C_DOUT_WIDTH-1:0] hexstr_conv; + input [(C_DOUT_WIDTH*8)-1:0] def_data; + + integer index,i,j; + reg [3:0] bin; + + begin + index = 0; + hexstr_conv = 'b0; + for( i=C_DOUT_WIDTH-1; i>=0; i=i-1 ) + begin + case (def_data[7:0]) + 8'b00000000 : + begin + bin = 4'b0000; + i = -1; + end + 8'b00110000 : bin = 4'b0000; + 8'b00110001 : bin = 4'b0001; + 8'b00110010 : bin = 4'b0010; + 8'b00110011 : bin = 4'b0011; + 8'b00110100 : bin = 4'b0100; + 8'b00110101 : bin = 4'b0101; + 8'b00110110 : bin = 4'b0110; + 8'b00110111 : bin = 4'b0111; + 8'b00111000 : bin = 4'b1000; + 8'b00111001 : bin = 4'b1001; + 8'b01000001 : bin = 4'b1010; + 8'b01000010 : bin = 4'b1011; + 8'b01000011 : bin = 4'b1100; + 8'b01000100 : bin = 4'b1101; + 8'b01000101 : bin = 4'b1110; + 8'b01000110 : bin = 4'b1111; + 8'b01100001 : bin = 4'b1010; + 8'b01100010 : bin = 4'b1011; + 8'b01100011 : bin = 4'b1100; + 8'b01100100 : bin = 4'b1101; + 8'b01100101 : bin = 4'b1110; + 8'b01100110 : bin = 4'b1111; + default : + begin + bin = 4'bx; + end + endcase + for( j=0; j<4; j=j+1) + begin + if ((index*4)+j < C_DOUT_WIDTH) + begin + hexstr_conv[(index*4)+j] = bin[j]; + end + end + index = index + 1; + def_data = def_data >> 8; + end + end + endfunction + + + //************************************************************************* + // Set power-on states for regs + //************************************************************************* + initial begin + ram_valid_i = 1'b0; + read_data_valid_i = 1'b0; + USERDATA = hexstr_conv(C_DOUT_RST_VAL); + USERSBITERR = 1'b0; + USERDBITERR = 1'b0; + end //initial + + //*************************************************************************** + // connect up optional reset + //*************************************************************************** + assign rd_rst_i = (C_HAS_RST == 1 || C_ENABLE_RST_SYNC == 0) ? RD_RST : 0; + assign srst_i = C_HAS_SRST ? SRST : 0; + + + //*************************************************************************** + // preloadstage2 indicates that stage2 needs to be updated. This is true + // whenever read_data_valid is false, and RAM_valid is true. + //*************************************************************************** + assign preloadstage2 = ram_valid_i & (~read_data_valid_i | RD_EN); + + //*************************************************************************** + // preloadstage1 indicates that stage1 needs to be updated. This is true + // whenever the RAM has data (RAM_EMPTY is false), and either RAM_Valid is + // false (indicating that Stage1 needs updating), or preloadstage2 is active + // (indicating that Stage2 is going to update, so Stage1, therefore, must + // also be updated to keep it valid. + //*************************************************************************** + assign preloadstage1 = ((~ram_valid_i | preloadstage2) & ~FIFOEMPTY); + + //*************************************************************************** + // Calculate RAM_REGOUT_EN + // The output registers are controlled by the ram_regout_en signal. + // These registers should be updated either when the output in Stage2 is + // invalid (preloadstage2), OR when the user is reading, in which case the + // Stage2 value will go invalid unless it is replenished. + //*************************************************************************** + assign ram_regout_en = preloadstage2; + + //*************************************************************************** + // Calculate RAM_RD_EN + // RAM_RD_EN will be asserted whenever the RAM needs to be read in order to + // update the value in Stage1. + // One case when this happens is when preloadstage1=true, which indicates + // that the data in Stage1 or Stage2 is invalid, and needs to automatically + // be updated. + // The other case is when the user is reading from the FIFO, which + // guarantees that Stage1 or Stage2 will be invalid on the next clock + // cycle, unless it is replinished by data from the memory. So, as long + // as the RAM has data in it, a read of the RAM should occur. + //*************************************************************************** + assign ram_rd_en = (RD_EN & ~FIFOEMPTY) | preloadstage1; + + //*************************************************************************** + // Calculate RAMVALID_P0_OUT + // RAMVALID_P0_OUT indicates that the data in Stage1 is valid. + // + // If the RAM is being read from on this clock cycle (ram_rd_en=1), then + // RAMVALID_P0_OUT is certainly going to be true. + // If the RAM is not being read from, but the output registers are being + // updated to fill Stage2 (ram_regout_en=1), then Stage1 will be emptying, + // therefore causing RAMVALID_P0_OUT to be false. + // Otherwise, RAMVALID_P0_OUT will remain unchanged. + //*************************************************************************** + // PROCESS regout_valid + always @ (posedge RD_CLK or posedge rd_rst_i) begin + if (rd_rst_i) begin + // asynchronous reset (active high) + ram_valid_i <= #`TCQ 1'b0; + end else begin + if (srst_i) begin + // synchronous reset (active high) + ram_valid_i <= #`TCQ 1'b0; + end else begin + if (ram_rd_en == 1'b1) begin + ram_valid_i <= #`TCQ 1'b1; + end else begin + if (ram_regout_en == 1'b1) + ram_valid_i <= #`TCQ 1'b0; + else + ram_valid_i <= #`TCQ ram_valid_i; + end + end //srst_i + end //rd_rst_i + end //always + + //*************************************************************************** + // Calculate READ_DATA_VALID + // READ_DATA_VALID indicates whether the value in Stage2 is valid or not. + // Stage2 has valid data whenever Stage1 had valid data and + // ram_regout_en_i=1, such that the data in Stage1 is propogated + // into Stage2. + //*************************************************************************** + always @ (posedge RD_CLK or posedge rd_rst_i) begin + if (rd_rst_i) + read_data_valid_i <= #`TCQ 1'b0; + else if (srst_i) + read_data_valid_i <= #`TCQ 1'b0; + else + read_data_valid_i <= #`TCQ ram_valid_i | (read_data_valid_i & ~RD_EN); + end //always + + + //************************************************************************** + // Calculate EMPTY + // Defined as the inverse of READ_DATA_VALID + // + // Description: + // + // If read_data_valid_i indicates that the output is not valid, + // and there is no valid data on the output of the ram to preload it + // with, then we will report empty. + // + // If there is no valid data on the output of the ram and we are + // reading, then the FIFO will go empty. + // + //************************************************************************** + always @ (posedge RD_CLK or posedge rd_rst_i) begin + if (rd_rst_i) begin + // asynchronous reset (active high) + empty_i <= #`TCQ 1'b1; + end else begin + if (srst_i) begin + // synchronous reset (active high) + empty_i <= #`TCQ 1'b1; + end else begin + // rising clock edge + empty_i <= #`TCQ (~ram_valid_i & ~read_data_valid_i) | (~ram_valid_i & RD_EN); + end + end + end //always + + // Register RD_EN from user to calculate USERUNDERFLOW. + // Register empty_i to calculate USERUNDERFLOW. + always @ (posedge RD_CLK) begin + rd_en_q <= #`TCQ RD_EN; + empty_q <= #`TCQ empty_i; + end //always + + + //*************************************************************************** + // Calculate user_almost_empty + // user_almost_empty is defined such that, unless more words are written + // to the FIFO, the next read will cause the FIFO to go EMPTY. + // + // In most cases, whenever the output registers are updated (due to a user + // read or a preload condition), then user_almost_empty will update to + // whatever RAM_EMPTY is. + // + // The exception is when the output is valid, the user is not reading, and + // Stage1 is not empty. In this condition, Stage1 will be preloaded from the + // memory, so we need to make sure user_almost_empty deasserts properly under + // this condition. + //*************************************************************************** + always @ (posedge RD_CLK or posedge rd_rst_i) + begin + if (rd_rst_i) begin // asynchronous reset (active high) + almost_empty_i <= #`TCQ 1'b1; + almost_empty_q <= #`TCQ 1'b1; + end else begin // rising clock edge + if (srst_i) begin // synchronous reset (active high) + almost_empty_i <= #`TCQ 1'b1; + almost_empty_q <= #`TCQ 1'b1; + end else begin + if ((ram_regout_en) | (~FIFOEMPTY & read_data_valid_i & ~RD_EN)) begin + almost_empty_i <= #`TCQ FIFOEMPTY; + end + almost_empty_q <= #`TCQ empty_i; + end + end + end //always + + + assign USEREMPTY = empty_i; + assign USERALMOSTEMPTY = almost_empty_i; + assign FIFORDEN = ram_rd_en; + assign RAMVALID = ram_valid_i; + assign USERVALID = C_USERVALID_LOW ? ~read_data_valid_i : read_data_valid_i; + assign USERUNDERFLOW = C_USERUNDERFLOW_LOW ? ~(empty_q & rd_en_q) : empty_q & rd_en_q; + + always @ (posedge RD_CLK or posedge rd_rst_i) + begin + if (rd_rst_i) begin //asynchronous reset (active high) + USERSBITERR <= #`TCQ 0; + USERDBITERR <= #`TCQ 0; + if (C_USE_DOUT_RST == 1) //asynchronous reset (active high) + USERDATA <= #`TCQ hexstr_conv(C_DOUT_RST_VAL); + end else begin // rising clock edge + if (srst_i) begin + USERSBITERR <= #`TCQ 0; + USERDBITERR <= #`TCQ 0; + if (C_USE_DOUT_RST == 1) + USERDATA <= #`TCQ hexstr_conv(C_DOUT_RST_VAL); + end else begin + if (ram_regout_en) begin + USERDATA <= #`TCQ FIFODATA; + USERSBITERR <= #`TCQ FIFOSBITERR; + USERDBITERR <= #`TCQ FIFODBITERR; + end + end + end + end //always + + + + + +endmodule diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/FIFO_GENERATOR_V5_2_XST.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/FIFO_GENERATOR_V5_2_XST.v new file mode 100644 index 0000000..6a2624f --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/FIFO_GENERATOR_V5_2_XST.v @@ -0,0 +1,336 @@ +/* + ******************************************************************************* + * + * FIFO Generator - Verilog Behavioral Model + * + ******************************************************************************* + * + * (c) Copyright 1995 - 2009 Xilinx, Inc. All rights reserved. + * + * This file contains confidential and proprietary information + * of Xilinx, Inc. and is protected under U.S. and + * international copyright and other intellectual property + * laws. + * + * DISCLAIMER + * This disclaimer is not a license and does not grant any + * rights to the materials distributed herewith. Except as + * otherwise provided in a valid license issued to you by + * Xilinx, and to the maximum extent permitted by applicable + * law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND + * WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES + * AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING + * BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- + * INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and + * (2) Xilinx shall not be liable (whether in contract or tort, + * including negligence, or under any other theory of + * liability) for any loss or damage of any kind or nature + * related to, arising under or in connection with these + * materials, including for any direct, or any indirect, + * special, incidental, or consequential loss or damage + * (including loss of data, profits, goodwill, or any type of + * loss or damage suffered as a result of any action brought + * by a third party) even if such damage or loss was + * reasonably foreseeable or Xilinx had been advised of the + * possibility of the same. + * + * CRITICAL APPLICATIONS + * Xilinx products are not designed or intended to be fail- + * safe, or for use in any application requiring fail-safe + * performance, such as life-support or safety devices or + * systems, Class III medical devices, nuclear facilities, + * applications related to the deployment of airbags, or any + * other applications that could lead to death, personal + * injury, or severe property or environmental damage + * (individually and collectively, "Critical + * Applications"). Customer assumes the sole risk and + * liability of any use of Xilinx products in Critical + * Applications, subject only to applicable laws and + * regulations governing limitations on product liability. + * + * THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS + * PART OF THIS FILE AT ALL TIMES. + * + ******************************************************************************* + ******************************************************************************* + * + * Filename: fifo_generator_v5_2_bhv.v + * + * Description: + * The verilog behavioral model for the FIFO generator core. + * + ******************************************************************************* + */ + +`timescale 1ps/1ps + +/******************************************************************************* + * Declaration of top-level module + ******************************************************************************/ +module FIFO_GENERATOR_V5_2_XST + ( + BACKUP, + BACKUP_MARKER, + CLK, + DIN, + PROG_EMPTY_THRESH, + PROG_EMPTY_THRESH_ASSERT, + PROG_EMPTY_THRESH_NEGATE, + PROG_FULL_THRESH, + PROG_FULL_THRESH_ASSERT, + PROG_FULL_THRESH_NEGATE, + RD_CLK, + RD_EN, + RD_RST, + RST, + SRST, + WR_CLK, + WR_EN, + WR_RST, + INT_CLK, + INJECTDBITERR, + INJECTSBITERR, + + ALMOST_EMPTY, + ALMOST_FULL, + DATA_COUNT, + DOUT, + EMPTY, + FULL, + OVERFLOW, + PROG_EMPTY, + PROG_FULL, + RD_DATA_COUNT, + UNDERFLOW, + VALID, + WR_ACK, + WR_DATA_COUNT, + SBITERR, + DBITERR + ); + +/****************************************************************************** + * Definition of Ports + * + * + ***************************************************************************** + * Definition of Parameters + * + * + *****************************************************************************/ + +/****************************************************************************** + * Declare user parameters and their defaults + *****************************************************************************/ + parameter C_COMMON_CLOCK = 0; + parameter C_COUNT_TYPE = 0; + parameter C_DATA_COUNT_WIDTH = 2; + parameter C_DEFAULT_VALUE = ""; + parameter C_DIN_WIDTH = 8; + parameter C_DOUT_RST_VAL = ""; + parameter C_DOUT_WIDTH = 8; + parameter C_ENABLE_RLOCS = 0; + parameter C_FAMILY = "virtex2"; //Not allowed in Verilog model + parameter C_HAS_ALMOST_EMPTY = 0; + parameter C_HAS_ALMOST_FULL = 0; + parameter C_HAS_BACKUP = 0; + parameter C_HAS_DATA_COUNT = 0; + parameter C_HAS_MEMINIT_FILE = 0; + parameter C_HAS_OVERFLOW = 0; + parameter C_HAS_RD_DATA_COUNT = 0; + parameter C_HAS_RD_RST = 0; + parameter C_HAS_RST = 0; + parameter C_HAS_SRST = 0; + parameter C_HAS_UNDERFLOW = 0; + parameter C_HAS_VALID = 0; + parameter C_HAS_WR_ACK = 0; + parameter C_HAS_WR_DATA_COUNT = 0; + parameter C_HAS_WR_RST = 0; + parameter C_IMPLEMENTATION_TYPE = 0; + parameter C_INIT_WR_PNTR_VAL = 0; + parameter C_MEMORY_TYPE = 1; + parameter C_MIF_FILE_NAME = ""; + parameter C_OPTIMIZATION_MODE = 0; + parameter C_OVERFLOW_LOW = 0; + parameter C_PRELOAD_LATENCY = 1; + parameter C_PRELOAD_REGS = 0; + parameter C_PRIM_FIFO_TYPE = ""; + parameter C_PROG_EMPTY_THRESH_ASSERT_VAL = 0; + parameter C_PROG_EMPTY_THRESH_NEGATE_VAL = 0; + parameter C_PROG_EMPTY_TYPE = 0; + parameter C_PROG_FULL_THRESH_ASSERT_VAL = 0; + parameter C_PROG_FULL_THRESH_NEGATE_VAL = 0; + parameter C_PROG_FULL_TYPE = 0; + parameter C_RD_DATA_COUNT_WIDTH = 2; + parameter C_RD_DEPTH = 256; + parameter C_RD_FREQ = 1; + parameter C_RD_PNTR_WIDTH = 8; + parameter C_UNDERFLOW_LOW = 0; + parameter C_USE_DOUT_RST = 0; + parameter C_USE_EMBEDDED_REG = 0; + parameter C_USE_FIFO16_FLAGS = 0; + parameter C_USE_FWFT_DATA_COUNT = 0; + parameter C_VALID_LOW = 0; + parameter C_WR_ACK_LOW = 0; + parameter C_WR_DATA_COUNT_WIDTH = 2; + parameter C_WR_DEPTH = 256; + parameter C_WR_FREQ = 1; + parameter C_WR_PNTR_WIDTH = 8; + parameter C_WR_RESPONSE_LATENCY = 1; + parameter C_USE_ECC = 0; + parameter C_FULL_FLAGS_RST_VAL = 1; + parameter C_HAS_INT_CLK = 0; + parameter C_MSGON_VAL = 1; + parameter C_ENABLE_RST_SYNC = 1; + parameter C_ERROR_INJECTION_TYPE = 0; + + + /****************************************************************************** + * Declare Input and Output Ports + *****************************************************************************/ + input CLK; + input BACKUP; + input BACKUP_MARKER; + input [C_DIN_WIDTH-1:0] DIN; + input [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH; + input [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_ASSERT; + input [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_NEGATE; + input [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH; + input [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_ASSERT; + input [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_NEGATE; + input RD_CLK; + input RD_EN; + input RD_RST; + input RST; + input SRST; + input WR_CLK; + input WR_EN; + input WR_RST; + input INT_CLK; + input INJECTDBITERR; + input INJECTSBITERR; + + output ALMOST_EMPTY; + output ALMOST_FULL; + output [C_DATA_COUNT_WIDTH-1:0] DATA_COUNT; + output [C_DOUT_WIDTH-1:0] DOUT; + output EMPTY; + output FULL; + output OVERFLOW; + output PROG_EMPTY; + output PROG_FULL; + output VALID; + output [C_RD_DATA_COUNT_WIDTH-1:0] RD_DATA_COUNT; + output UNDERFLOW; + output WR_ACK; + output [C_WR_DATA_COUNT_WIDTH-1:0] WR_DATA_COUNT; + output SBITERR; + output DBITERR; + + FIFO_GENERATOR_V5_2 + #( + .C_COMMON_CLOCK (C_COMMON_CLOCK), + .C_COUNT_TYPE (C_COUNT_TYPE), + .C_DATA_COUNT_WIDTH (C_DATA_COUNT_WIDTH), + .C_DEFAULT_VALUE (C_DEFAULT_VALUE), + .C_DIN_WIDTH (C_DIN_WIDTH), + .C_DOUT_RST_VAL (C_DOUT_RST_VAL), + .C_DOUT_WIDTH (C_DOUT_WIDTH), + .C_ENABLE_RLOCS (C_ENABLE_RLOCS), + .C_FAMILY (C_FAMILY),//Not allowed in Verilog model + .C_HAS_ALMOST_EMPTY (C_HAS_ALMOST_EMPTY), + .C_HAS_ALMOST_FULL (C_HAS_ALMOST_FULL), + .C_HAS_BACKUP (C_HAS_BACKUP), + .C_HAS_DATA_COUNT (C_HAS_DATA_COUNT), + .C_HAS_MEMINIT_FILE (C_HAS_MEMINIT_FILE), + .C_HAS_OVERFLOW (C_HAS_OVERFLOW), + .C_HAS_RD_DATA_COUNT (C_HAS_RD_DATA_COUNT), + .C_HAS_RD_RST (C_HAS_RD_RST), + .C_HAS_RST (C_HAS_RST), + .C_HAS_SRST (C_HAS_SRST), + .C_HAS_UNDERFLOW (C_HAS_UNDERFLOW), + .C_HAS_VALID (C_HAS_VALID), + .C_HAS_WR_ACK (C_HAS_WR_ACK), + .C_HAS_WR_DATA_COUNT (C_HAS_WR_DATA_COUNT), + .C_HAS_WR_RST (C_HAS_WR_RST), + .C_IMPLEMENTATION_TYPE (C_IMPLEMENTATION_TYPE), + .C_INIT_WR_PNTR_VAL (C_INIT_WR_PNTR_VAL), + .C_MEMORY_TYPE (C_MEMORY_TYPE), + .C_MIF_FILE_NAME (C_MIF_FILE_NAME), + .C_OPTIMIZATION_MODE (C_OPTIMIZATION_MODE), + .C_OVERFLOW_LOW (C_OVERFLOW_LOW), + .C_PRELOAD_LATENCY (C_PRELOAD_LATENCY), + .C_PRELOAD_REGS (C_PRELOAD_REGS), + .C_PRIM_FIFO_TYPE (C_PRIM_FIFO_TYPE), + .C_PROG_EMPTY_THRESH_ASSERT_VAL (C_PROG_EMPTY_THRESH_ASSERT_VAL), + .C_PROG_EMPTY_THRESH_NEGATE_VAL (C_PROG_EMPTY_THRESH_NEGATE_VAL), + .C_PROG_EMPTY_TYPE (C_PROG_EMPTY_TYPE), + .C_PROG_FULL_THRESH_ASSERT_VAL (C_PROG_FULL_THRESH_ASSERT_VAL), + .C_PROG_FULL_THRESH_NEGATE_VAL (C_PROG_FULL_THRESH_NEGATE_VAL), + .C_PROG_FULL_TYPE (C_PROG_FULL_TYPE), + .C_RD_DATA_COUNT_WIDTH (C_RD_DATA_COUNT_WIDTH), + .C_RD_DEPTH (C_RD_DEPTH), + .C_RD_FREQ (C_RD_FREQ), + .C_RD_PNTR_WIDTH (C_RD_PNTR_WIDTH), + .C_UNDERFLOW_LOW (C_UNDERFLOW_LOW), + .C_USE_DOUT_RST (C_USE_DOUT_RST), + .C_USE_EMBEDDED_REG (C_USE_EMBEDDED_REG), + .C_USE_FIFO16_FLAGS (C_USE_FIFO16_FLAGS), + .C_USE_FWFT_DATA_COUNT (C_USE_FWFT_DATA_COUNT), + .C_VALID_LOW (C_VALID_LOW), + .C_WR_ACK_LOW (C_WR_ACK_LOW), + .C_WR_DATA_COUNT_WIDTH (C_WR_DATA_COUNT_WIDTH), + .C_WR_DEPTH (C_WR_DEPTH), + .C_WR_FREQ (C_WR_FREQ), + .C_WR_PNTR_WIDTH (C_WR_PNTR_WIDTH), + .C_WR_RESPONSE_LATENCY (C_WR_RESPONSE_LATENCY), + .C_USE_ECC (C_USE_ECC), + .C_FULL_FLAGS_RST_VAL (C_FULL_FLAGS_RST_VAL), + .C_HAS_INT_CLK (C_HAS_INT_CLK), + .C_MSGON_VAL (C_MSGON_VAL), + .C_ENABLE_RST_SYNC (C_ENABLE_RST_SYNC), + .C_ERROR_INJECTION_TYPE (C_ERROR_INJECTION_TYPE) + ) + fifo_generator_v5_2_dut + ( + .BACKUP (BACKUP), + .BACKUP_MARKER (BACKUP_MARKER), + .CLK (CLK), + .RST (RST), + .SRST (SRST), + .WR_CLK (WR_CLK), + .WR_RST (WR_RST), + .RD_CLK (RD_CLK), + .RD_RST (RD_RST), + .DIN (DIN), + .WR_EN (WR_EN), + .RD_EN (RD_EN), + .PROG_EMPTY_THRESH (PROG_EMPTY_THRESH), + .PROG_EMPTY_THRESH_ASSERT (PROG_EMPTY_THRESH_ASSERT), + .PROG_EMPTY_THRESH_NEGATE (PROG_EMPTY_THRESH_NEGATE), + .PROG_FULL_THRESH (PROG_FULL_THRESH), + .PROG_FULL_THRESH_ASSERT (PROG_FULL_THRESH_ASSERT), + .PROG_FULL_THRESH_NEGATE (PROG_FULL_THRESH_NEGATE), + .INT_CLK (INT_CLK), + .INJECTDBITERR (INJECTDBITERR), + .INJECTSBITERR (INJECTSBITERR), + + .DOUT (DOUT), + .FULL (FULL), + .ALMOST_FULL (ALMOST_FULL), + .WR_ACK (WR_ACK), + .OVERFLOW (OVERFLOW), + .EMPTY (EMPTY), + .ALMOST_EMPTY (ALMOST_EMPTY), + .VALID (VALID), + .UNDERFLOW (UNDERFLOW), + .DATA_COUNT (DATA_COUNT), + .RD_DATA_COUNT (RD_DATA_COUNT), + .WR_DATA_COUNT (WR_DATA_COUNT), + .PROG_FULL (PROG_FULL), + .PROG_EMPTY (PROG_EMPTY), + .SBITERR (SBITERR), + .DBITERR (DBITERR) + ); + +endmodule diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/FIFO_GENERATOR_V5_3.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/FIFO_GENERATOR_V5_3.v new file mode 100644 index 0000000..eb7cc6b --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/FIFO_GENERATOR_V5_3.v @@ -0,0 +1,4668 @@ +/* + ******************************************************************************* + * + * FIFO Generator - Verilog Behavioral Model + * + ******************************************************************************* + * + * (c) Copyright 1995 - 2009 Xilinx, Inc. All rights reserved. + * + * This file contains confidential and proprietary information + * of Xilinx, Inc. and is protected under U.S. and + * international copyright and other intellectual property + * laws. + * + * DISCLAIMER + * This disclaimer is not a license and does not grant any + * rights to the materials distributed herewith. Except as + * otherwise provided in a valid license issued to you by + * Xilinx, and to the maximum extent permitted by applicable + * law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND + * WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES + * AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING + * BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- + * INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and + * (2) Xilinx shall not be liable (whether in contract or tort, + * including negligence, or under any other theory of + * liability) for any loss or damage of any kind or nature + * related to, arising under or in connection with these + * materials, including for any direct, or any indirect, + * special, incidental, or consequential loss or damage + * (including loss of data, profits, goodwill, or any type of + * loss or damage suffered as a result of any action brought + * by a third party) even if such damage or loss was + * reasonably foreseeable or Xilinx had been advised of the + * possibility of the same. + * + * CRITICAL APPLICATIONS + * Xilinx products are not designed or intended to be fail- + * safe, or for use in any application requiring fail-safe + * performance, such as life-support or safety devices or + * systems, Class III medical devices, nuclear facilities, + * applications related to the deployment of airbags, or any + * other applications that could lead to death, personal + * injury, or severe property or environmental damage + * (individually and collectively, "Critical + * Applications"). Customer assumes the sole risk and + * liability of any use of Xilinx products in Critical + * Applications, subject only to applicable laws and + * regulations governing limitations on product liability. + * + * THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS + * PART OF THIS FILE AT ALL TIMES. + * + ******************************************************************************* + ******************************************************************************* + * + * Filename: FIFO_GENERATOR_V5_3.v + * + * Author : Xilinx + * + ******************************************************************************* + * Structure: + * + * fifo_generator_v5_3.vhd + * | + * +-fifo_generator_v5_3_bhv_ver_as + * | + * +-fifo_generator_v5_3_bhv_ver_ss + * | + * +-fifo_generator_v5_3_bhv_ver_preload0 + * + ******************************************************************************* + * Description: + * + * The Verilog behavioral model for the FIFO Generator. + * + * The behavioral model has three parts: + * - The behavioral model for independent clocks FIFOs (_as) + * - The behavioral model for common clock FIFOs (_ss) + * - The "preload logic" block which implements First-word Fall-through + * + ******************************************************************************* + * Description: + * The verilog behavioral model for the FIFO generator core. + * + ******************************************************************************* + */ + +`timescale 1ps/1ps +`ifndef TCQ + `define TCQ 100 +`endif + + +/******************************************************************************* + * Declaration of top-level module + ******************************************************************************/ +module FIFO_GENERATOR_V5_3 +( + BACKUP, + BACKUP_MARKER, + CLK, + RST, + SRST, + WR_CLK, + WR_RST, + RD_CLK, + RD_RST, + DIN, + WR_EN, + RD_EN, + PROG_EMPTY_THRESH, + PROG_EMPTY_THRESH_ASSERT, + PROG_EMPTY_THRESH_NEGATE, + PROG_FULL_THRESH, + PROG_FULL_THRESH_ASSERT, + PROG_FULL_THRESH_NEGATE, + INT_CLK, + INJECTDBITERR, + INJECTSBITERR, + + DOUT, + FULL, + ALMOST_FULL, + WR_ACK, + OVERFLOW, + EMPTY, + ALMOST_EMPTY, + VALID, + UNDERFLOW, + DATA_COUNT, + RD_DATA_COUNT, + WR_DATA_COUNT, + PROG_FULL, + PROG_EMPTY, + SBITERR, + DBITERR + ); + +/* + ****************************************************************************** + * Definition of Parameters + ****************************************************************************** + * C_COMMON_CLOCK : Common Clock (1), Independent Clocks (0) + * C_COUNT_TYPE : *not used + * C_DATA_COUNT_WIDTH : Width of DATA_COUNT bus + * C_DEFAULT_VALUE : *not used + * C_DIN_WIDTH : Width of DIN bus + * C_DOUT_RST_VAL : Reset value of DOUT + * C_DOUT_WIDTH : Width of DOUT bus + * C_ENABLE_RLOCS : *not used + * C_FAMILY : not used in bhv model + * C_FULL_FLAGS_RST_VAL : Full flags rst val (0 or 1) + * C_HAS_ALMOST_EMPTY : 1=Core has ALMOST_EMPTY flag + * C_HAS_ALMOST_FULL : 1=Core has ALMOST_FULL flag + * C_HAS_BACKUP : *not used + * C_HAS_DATA_COUNT : 1=Core has DATA_COUNT bus + * C_HAS_INT_CLK : not used in bhv model + * C_HAS_MEMINIT_FILE : *not used + * C_HAS_OVERFLOW : 1=Core has OVERFLOW flag + * C_HAS_RD_DATA_COUNT : 1=Core has RD_DATA_COUNT bus + * C_HAS_RD_RST : *not used + * C_HAS_RST : 1=Core has Async Rst + * C_HAS_SRST : 1=Core has Sync Rst + * C_HAS_UNDERFLOW : 1=Core has UNDERFLOW flag + * C_HAS_VALID : 1=Core has VALID flag + * C_HAS_WR_ACK : 1=Core has WR_ACK flag + * C_HAS_WR_DATA_COUNT : 1=Core has WR_DATA_COUNT bus + * C_HAS_WR_RST : *not used + * C_IMPLEMENTATION_TYPE : 0=Common-Clock Bram/Dram + * 1=Common-Clock ShiftRam + * 2=Indep. Clocks Bram/Dram + * 3=Virtex-4 Built-in + * 4=Virtex-5 Built-in + * C_INIT_WR_PNTR_VAL : *not used + * C_MEMORY_TYPE : 1=Block RAM + * 2=Distributed RAM + * 3=Shift RAM + * 4=Built-in FIFO + * C_MIF_FILE_NAME : *not used + * C_OPTIMIZATION_MODE : *not used + * C_OVERFLOW_LOW : 1=OVERFLOW active low + * C_PRELOAD_LATENCY : Latency of read: 0, 1, 2 + * C_PRELOAD_REGS : 1=Use output registers + * C_PRIM_FIFO_TYPE : not used in bhv model + * C_PROG_EMPTY_THRESH_ASSERT_VAL: PROG_EMPTY assert threshold + * C_PROG_EMPTY_THRESH_NEGATE_VAL: PROG_EMPTY negate threshold + * C_PROG_EMPTY_TYPE : 0=No programmable empty + * 1=Single prog empty thresh constant + * 2=Multiple prog empty thresh constants + * 3=Single prog empty thresh input + * 4=Multiple prog empty thresh inputs + * C_PROG_FULL_THRESH_ASSERT_VAL : PROG_FULL assert threshold + * C_PROG_FULL_THRESH_NEGATE_VAL : PROG_FULL negate threshold + * C_PROG_FULL_TYPE : 0=No prog full + * 1=Single prog full thresh constant + * 2=Multiple prog full thresh constants + * 3=Single prog full thresh input + * 4=Multiple prog full thresh inputs + * C_RD_DATA_COUNT_WIDTH : Width of RD_DATA_COUNT bus + * C_RD_DEPTH : Depth of read interface (2^N) + * C_RD_FREQ : not used in bhv model + * C_RD_PNTR_WIDTH : always log2(C_RD_DEPTH) + * C_UNDERFLOW_LOW : 1=UNDERFLOW active low + * C_USE_DOUT_RST : 1=Resets DOUT on RST + * C_USE_ECC : Used for error injection purpose + * C_USE_EMBEDDED_REG : 1=Use BRAM embedded output register + * C_USE_FIFO16_FLAGS : not used in bhv model + * C_USE_FWFT_DATA_COUNT : 1=Use extra logic for FWFT data count + * C_VALID_LOW : 1=VALID active low + * C_WR_ACK_LOW : 1=WR_ACK active low + * C_WR_DATA_COUNT_WIDTH : Width of WR_DATA_COUNT bus + * C_WR_DEPTH : Depth of write interface (2^N) + * C_WR_FREQ : not used in bhv model + * C_WR_PNTR_WIDTH : always log2(C_WR_DEPTH) + * C_WR_RESPONSE_LATENCY : *not used + * C_MSGON_VAL : *not used by bhv model + * C_ENABLE_RST_SYNC : 0 = Use WR_RST & RD_RST + * 1 = Use RST + * C_ERROR_INJECTION_TYPE : 0 = No error injection + * 1 = Single bit error injection only + * 2 = Double bit error injection only + * 3 = Single and double bit error injection + ****************************************************************************** + * Definition of Ports + ****************************************************************************** + * BACKUP : Not used + * BACKUP_MARKER: Not used + * CLK : Clock + * DIN : Input data bus + * PROG_EMPTY_THRESH : Threshold for Programmable Empty Flag + * PROG_EMPTY_THRESH_ASSERT: Threshold for Programmable Empty Flag + * PROG_EMPTY_THRESH_NEGATE: Threshold for Programmable Empty Flag + * PROG_FULL_THRESH : Threshold for Programmable Full Flag + * PROG_FULL_THRESH_ASSERT : Threshold for Programmable Full Flag + * PROG_FULL_THRESH_NEGATE : Threshold for Programmable Full Flag + * RD_CLK : Read Domain Clock + * RD_EN : Read enable + * RD_RST : Read Reset + * RST : Asynchronous Reset + * SRST : Synchronous Reset + * WR_CLK : Write Domain Clock + * WR_EN : Write enable + * WR_RST : Write Reset + * INT_CLK : Internal Clock + * INJECTSBITERR: Inject Signle bit error + * INJECTDBITERR: Inject Double bit error + * ALMOST_EMPTY : One word remaining in FIFO + * ALMOST_FULL : One empty space remaining in FIFO + * DATA_COUNT : Number of data words in fifo( synchronous to CLK) + * DOUT : Output data bus + * EMPTY : Empty flag + * FULL : Full flag + * OVERFLOW : Last write rejected + * PROG_EMPTY : Programmable Empty Flag + * PROG_FULL : Programmable Full Flag + * RD_DATA_COUNT: Number of data words in fifo (synchronous to RD_CLK) + * UNDERFLOW : Last read rejected + * VALID : Last read acknowledged, DOUT bus VALID + * WR_ACK : Last write acknowledged + * WR_DATA_COUNT: Number of data words in fifo (synchronous to WR_CLK) + * SBITERR : Single Bit ECC Error Detected + * DBITERR : Double Bit ECC Error Detected + ****************************************************************************** + */ + + + /**************************************************************************** + * Declare user parameters and their defaults + *****************************************************************************/ + parameter C_COMMON_CLOCK = 0; + parameter C_COUNT_TYPE = 0; + parameter C_DATA_COUNT_WIDTH = 2; + parameter C_DEFAULT_VALUE = ""; + parameter C_DIN_WIDTH = 8; + parameter C_DOUT_RST_VAL = ""; + parameter C_DOUT_WIDTH = 8; + parameter C_ENABLE_RLOCS = 0; + parameter C_FAMILY = "virtex2"; //Not allowed in Verilog model + parameter C_FULL_FLAGS_RST_VAL = 1; + parameter C_HAS_ALMOST_EMPTY = 0; + parameter C_HAS_ALMOST_FULL = 0; + parameter C_HAS_BACKUP = 0; + parameter C_HAS_DATA_COUNT = 0; + parameter C_HAS_INT_CLK = 0; + parameter C_HAS_MEMINIT_FILE = 0; + parameter C_HAS_OVERFLOW = 0; + parameter C_HAS_RD_DATA_COUNT = 0; + parameter C_HAS_RD_RST = 0; + parameter C_HAS_RST = 0; + parameter C_HAS_SRST = 0; + parameter C_HAS_UNDERFLOW = 0; + parameter C_HAS_VALID = 0; + parameter C_HAS_WR_ACK = 0; + parameter C_HAS_WR_DATA_COUNT = 0; + parameter C_HAS_WR_RST = 0; + parameter C_IMPLEMENTATION_TYPE = 0; + parameter C_INIT_WR_PNTR_VAL = 0; + parameter C_MEMORY_TYPE = 1; + parameter C_MIF_FILE_NAME = ""; + parameter C_OPTIMIZATION_MODE = 0; + parameter C_OVERFLOW_LOW = 0; + parameter C_PRELOAD_LATENCY = 1; + parameter C_PRELOAD_REGS = 0; + parameter C_PRIM_FIFO_TYPE = ""; + parameter C_PROG_EMPTY_THRESH_ASSERT_VAL = 0; + parameter C_PROG_EMPTY_THRESH_NEGATE_VAL = 0; + parameter C_PROG_EMPTY_TYPE = 0; + parameter C_PROG_FULL_THRESH_ASSERT_VAL = 0; + parameter C_PROG_FULL_THRESH_NEGATE_VAL = 0; + parameter C_PROG_FULL_TYPE = 0; + parameter C_RD_DATA_COUNT_WIDTH = 2; + parameter C_RD_DEPTH = 256; + parameter C_RD_FREQ = 1; + parameter C_RD_PNTR_WIDTH = 8; + parameter C_UNDERFLOW_LOW = 0; + parameter C_USE_DOUT_RST = 0; + parameter C_USE_ECC = 0; + parameter C_USE_EMBEDDED_REG = 0; + parameter C_USE_FIFO16_FLAGS = 0; + parameter C_USE_FWFT_DATA_COUNT = 0; + parameter C_VALID_LOW = 0; + parameter C_WR_ACK_LOW = 0; + parameter C_WR_DATA_COUNT_WIDTH = 2; + parameter C_WR_DEPTH = 256; + parameter C_WR_FREQ = 1; + parameter C_WR_PNTR_WIDTH = 8; + parameter C_WR_RESPONSE_LATENCY = 1; + parameter C_MSGON_VAL = 1; + parameter C_ENABLE_RST_SYNC = 1; + parameter C_ERROR_INJECTION_TYPE = 0; + + + + /***************************************************************************** + * Derived parameters + ****************************************************************************/ + //There are 2 Verilog behavioral models + // 0 = Common-Clock FIFO/ShiftRam FIFO + // 1 = Independent Clocks FIFO + parameter C_VERILOG_IMPL = (C_IMPLEMENTATION_TYPE==0 ? 0 : + (C_IMPLEMENTATION_TYPE==1 ? 0 : + (C_IMPLEMENTATION_TYPE==2 ? 1 : 0))); + + /***************************************************************************** + * Declare Input and Output Ports + ****************************************************************************/ + input CLK; + input BACKUP; + input BACKUP_MARKER; + input [C_DIN_WIDTH-1:0] DIN; + input [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH; + input [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_ASSERT; + input [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_NEGATE; + input [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH; + input [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_ASSERT; + input [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_NEGATE; + input RD_CLK; + input RD_EN; + input RD_RST; + input RST; + input SRST; + input WR_CLK; + input WR_EN; + input WR_RST; + input INT_CLK; + input INJECTDBITERR; + input INJECTSBITERR; + + output ALMOST_EMPTY; + output ALMOST_FULL; + output [C_DATA_COUNT_WIDTH-1:0] DATA_COUNT; + output [C_DOUT_WIDTH-1:0] DOUT; + output EMPTY; + output FULL; + output OVERFLOW; + output PROG_EMPTY; + output PROG_FULL; + output VALID; + output [C_RD_DATA_COUNT_WIDTH-1:0] RD_DATA_COUNT; + output UNDERFLOW; + output WR_ACK; + output [C_WR_DATA_COUNT_WIDTH-1:0] WR_DATA_COUNT; + output SBITERR; + output DBITERR; + + + wire ALMOST_EMPTY; + wire ALMOST_FULL; + wire [C_DATA_COUNT_WIDTH-1:0] DATA_COUNT; + wire [C_DOUT_WIDTH-1:0] DOUT; + wire EMPTY; + wire FULL; + wire OVERFLOW; + wire PROG_EMPTY; + wire PROG_FULL; + wire VALID; + wire [C_RD_DATA_COUNT_WIDTH-1:0] RD_DATA_COUNT; + wire UNDERFLOW; + wire WR_ACK; + wire [C_WR_DATA_COUNT_WIDTH-1:0] WR_DATA_COUNT; + + + wire RD_CLK_P0_IN; + wire RST_P0_IN; + wire RD_EN_FIFO_IN; + wire RD_EN_P0_IN; + + wire ALMOST_EMPTY_FIFO_OUT; + wire ALMOST_FULL_FIFO_OUT; + wire [C_DATA_COUNT_WIDTH-1:0] DATA_COUNT_FIFO_OUT; + wire [C_DOUT_WIDTH-1:0] DOUT_FIFO_OUT; + wire EMPTY_FIFO_OUT; + wire FULL_FIFO_OUT; + wire OVERFLOW_FIFO_OUT; + wire PROG_EMPTY_FIFO_OUT; + wire PROG_FULL_FIFO_OUT; + wire VALID_FIFO_OUT; + wire [C_RD_DATA_COUNT_WIDTH-1:0] RD_DATA_COUNT_FIFO_OUT; + wire UNDERFLOW_FIFO_OUT; + wire WR_ACK_FIFO_OUT; + wire [C_WR_DATA_COUNT_WIDTH-1:0] WR_DATA_COUNT_FIFO_OUT; + + + //*************************************************************************** + // Internal Signals + // The core uses either the internal_ wires or the preload0_ wires depending + // on whether the core uses Preload0 or not. + // When using preload0, the internal signals connect the internal core to + // the preload logic, and the external core's interfaces are tied to the + // preload0 signals from the preload logic. + //*************************************************************************** + wire [C_DOUT_WIDTH-1:0] DATA_P0_OUT; + wire VALID_P0_OUT; + wire EMPTY_P0_OUT; + wire ALMOSTEMPTY_P0_OUT; + reg EMPTY_P0_OUT_Q; + reg ALMOSTEMPTY_P0_OUT_Q; + wire UNDERFLOW_P0_OUT; + wire RDEN_P0_OUT; + wire [C_DOUT_WIDTH-1:0] DATA_P0_IN; + wire EMPTY_P0_IN; + reg [31:0] DATA_COUNT_FWFT; + reg SS_FWFT_WR ; + reg SS_FWFT_RD ; + + wire SBITERR; + wire DBITERR; + wire sbiterr_fifo_out; + wire dbiterr_fifo_out; + + // Assign 0 if not selected to avoid 'X' propogation to S/DBITERR. + assign inject_sbit_err = ((C_ERROR_INJECTION_TYPE == 1) || (C_ERROR_INJECTION_TYPE == 3)) ? + INJECTSBITERR : 0; + assign inject_dbit_err = ((C_ERROR_INJECTION_TYPE == 2) || (C_ERROR_INJECTION_TYPE == 3)) ? + INJECTDBITERR : 0; + + +// Choose the behavioral model to instantiate based on the C_VERILOG_IMPL +// parameter (1=Independent Clocks, 0=Common Clock) +generate +case (C_VERILOG_IMPL) +0 : begin : block1 + //Common Clock Behavioral Model + fifo_generator_v5_3_bhv_ver_ss + #( + C_DATA_COUNT_WIDTH, + C_DIN_WIDTH, + C_DOUT_RST_VAL, + C_DOUT_WIDTH, + C_FULL_FLAGS_RST_VAL, + C_HAS_ALMOST_EMPTY, + C_HAS_ALMOST_FULL, + C_HAS_DATA_COUNT, + C_HAS_OVERFLOW, + C_HAS_RD_DATA_COUNT, + C_HAS_RST, + C_HAS_SRST, + C_HAS_UNDERFLOW, + C_HAS_VALID, + C_HAS_WR_ACK, + C_HAS_WR_DATA_COUNT, + C_IMPLEMENTATION_TYPE, + C_MEMORY_TYPE, + C_OVERFLOW_LOW, + C_PRELOAD_LATENCY, + C_PRELOAD_REGS, + C_PROG_EMPTY_THRESH_ASSERT_VAL, + C_PROG_EMPTY_THRESH_NEGATE_VAL, + C_PROG_EMPTY_TYPE, + C_PROG_FULL_THRESH_ASSERT_VAL, + C_PROG_FULL_THRESH_NEGATE_VAL, + C_PROG_FULL_TYPE, + C_RD_DATA_COUNT_WIDTH, + C_RD_DEPTH, + C_RD_PNTR_WIDTH, + C_UNDERFLOW_LOW, + C_USE_DOUT_RST, + C_USE_EMBEDDED_REG, + C_USE_FWFT_DATA_COUNT, + C_VALID_LOW, + C_WR_ACK_LOW, + C_WR_DATA_COUNT_WIDTH, + C_WR_DEPTH, + C_WR_PNTR_WIDTH, + C_USE_ECC, + C_ENABLE_RST_SYNC, + C_ERROR_INJECTION_TYPE + ) + gen_ss + ( + .CLK (CLK), + .RST (RST), + .SRST (SRST), + .DIN (DIN), + .WR_EN (WR_EN), + .RD_EN (RD_EN_FIFO_IN), + .PROG_EMPTY_THRESH (PROG_EMPTY_THRESH), + .PROG_EMPTY_THRESH_ASSERT (PROG_EMPTY_THRESH_ASSERT), + .PROG_EMPTY_THRESH_NEGATE (PROG_EMPTY_THRESH_NEGATE), + .PROG_FULL_THRESH (PROG_FULL_THRESH), + .PROG_FULL_THRESH_ASSERT (PROG_FULL_THRESH_ASSERT), + .PROG_FULL_THRESH_NEGATE (PROG_FULL_THRESH_NEGATE), + .INJECTSBITERR (inject_sbit_err), + .INJECTDBITERR (inject_dbit_err), + .DOUT (DOUT_FIFO_OUT), + .FULL (FULL_FIFO_OUT), + .ALMOST_FULL (ALMOST_FULL_FIFO_OUT), + .WR_ACK (WR_ACK_FIFO_OUT), + .OVERFLOW (OVERFLOW_FIFO_OUT), + .EMPTY (EMPTY_FIFO_OUT), + .ALMOST_EMPTY (ALMOST_EMPTY_FIFO_OUT), + .VALID (VALID_FIFO_OUT), + .UNDERFLOW (UNDERFLOW_FIFO_OUT), + .DATA_COUNT (DATA_COUNT_FIFO_OUT), + .PROG_FULL (PROG_FULL_FIFO_OUT), + .PROG_EMPTY (PROG_EMPTY_FIFO_OUT), + .SBITERR (sbiterr_fifo_out), + .DBITERR (dbiterr_fifo_out) + ); +end +1 : begin : block1 + //Independent Clocks Behavioral Model + fifo_generator_v5_3_bhv_ver_as + #( + C_DATA_COUNT_WIDTH, + C_DIN_WIDTH, + C_DOUT_RST_VAL, + C_DOUT_WIDTH, + C_FULL_FLAGS_RST_VAL, + C_HAS_ALMOST_EMPTY, + C_HAS_ALMOST_FULL, + C_HAS_DATA_COUNT, + C_HAS_OVERFLOW, + C_HAS_RD_DATA_COUNT, + C_HAS_RST, + C_HAS_UNDERFLOW, + C_HAS_VALID, + C_HAS_WR_ACK, + C_HAS_WR_DATA_COUNT, + C_IMPLEMENTATION_TYPE, + C_MEMORY_TYPE, + C_OVERFLOW_LOW, + C_PRELOAD_LATENCY, + C_PRELOAD_REGS, + C_PROG_EMPTY_THRESH_ASSERT_VAL, + C_PROG_EMPTY_THRESH_NEGATE_VAL, + C_PROG_EMPTY_TYPE, + C_PROG_FULL_THRESH_ASSERT_VAL, + C_PROG_FULL_THRESH_NEGATE_VAL, + C_PROG_FULL_TYPE, + C_RD_DATA_COUNT_WIDTH, + C_RD_DEPTH, + C_RD_PNTR_WIDTH, + C_UNDERFLOW_LOW, + C_USE_DOUT_RST, + C_USE_EMBEDDED_REG, + C_USE_FWFT_DATA_COUNT, + C_VALID_LOW, + C_WR_ACK_LOW, + C_WR_DATA_COUNT_WIDTH, + C_WR_DEPTH, + C_WR_PNTR_WIDTH, + C_USE_ECC, + C_ENABLE_RST_SYNC, + C_ERROR_INJECTION_TYPE + ) + gen_as + ( + .WR_CLK (WR_CLK), + .RD_CLK (RD_CLK), + .RST (RST), + .WR_RST (WR_RST), + .RD_RST (RD_RST), + .DIN (DIN), + .WR_EN (WR_EN), + .RD_EN (RD_EN_FIFO_IN), + .RD_EN_USER (RD_EN), + .PROG_EMPTY_THRESH (PROG_EMPTY_THRESH), + .PROG_EMPTY_THRESH_ASSERT (PROG_EMPTY_THRESH_ASSERT), + .PROG_EMPTY_THRESH_NEGATE (PROG_EMPTY_THRESH_NEGATE), + .PROG_FULL_THRESH (PROG_FULL_THRESH), + .PROG_FULL_THRESH_ASSERT (PROG_FULL_THRESH_ASSERT), + .PROG_FULL_THRESH_NEGATE (PROG_FULL_THRESH_NEGATE), + .INJECTSBITERR (inject_sbit_err), + .INJECTDBITERR (inject_dbit_err), + .USER_EMPTY_FB (EMPTY_P0_OUT), + .DOUT (DOUT_FIFO_OUT), + .FULL (FULL_FIFO_OUT), + .ALMOST_FULL (ALMOST_FULL_FIFO_OUT), + .WR_ACK (WR_ACK_FIFO_OUT), + .OVERFLOW (OVERFLOW_FIFO_OUT), + .EMPTY (EMPTY_FIFO_OUT), + .ALMOST_EMPTY (ALMOST_EMPTY_FIFO_OUT), + .VALID (VALID_FIFO_OUT), + .UNDERFLOW (UNDERFLOW_FIFO_OUT), + .RD_DATA_COUNT (RD_DATA_COUNT_FIFO_OUT), + .WR_DATA_COUNT (WR_DATA_COUNT_FIFO_OUT), + .PROG_FULL (PROG_FULL_FIFO_OUT), + .PROG_EMPTY (PROG_EMPTY_FIFO_OUT), + .SBITERR (sbiterr_fifo_out), + .DBITERR (dbiterr_fifo_out) + ); +end + +default : begin : block1 + //Independent Clocks Behavioral Model + fifo_generator_v5_3_bhv_ver_as + #( + C_DATA_COUNT_WIDTH, + C_DIN_WIDTH, + C_DOUT_RST_VAL, + C_DOUT_WIDTH, + C_FULL_FLAGS_RST_VAL, + C_HAS_ALMOST_EMPTY, + C_HAS_ALMOST_FULL, + C_HAS_DATA_COUNT, + C_HAS_OVERFLOW, + C_HAS_RD_DATA_COUNT, + C_HAS_RST, + C_HAS_UNDERFLOW, + C_HAS_VALID, + C_HAS_WR_ACK, + C_HAS_WR_DATA_COUNT, + C_IMPLEMENTATION_TYPE, + C_MEMORY_TYPE, + C_OVERFLOW_LOW, + C_PRELOAD_LATENCY, + C_PRELOAD_REGS, + C_PROG_EMPTY_THRESH_ASSERT_VAL, + C_PROG_EMPTY_THRESH_NEGATE_VAL, + C_PROG_EMPTY_TYPE, + C_PROG_FULL_THRESH_ASSERT_VAL, + C_PROG_FULL_THRESH_NEGATE_VAL, + C_PROG_FULL_TYPE, + C_RD_DATA_COUNT_WIDTH, + C_RD_DEPTH, + C_RD_PNTR_WIDTH, + C_UNDERFLOW_LOW, + C_USE_DOUT_RST, + C_USE_EMBEDDED_REG, + C_USE_FWFT_DATA_COUNT, + C_VALID_LOW, + C_WR_ACK_LOW, + C_WR_DATA_COUNT_WIDTH, + C_WR_DEPTH, + C_WR_PNTR_WIDTH, + C_USE_ECC, + C_ENABLE_RST_SYNC, + C_ERROR_INJECTION_TYPE + ) + gen_as + ( + .WR_CLK (WR_CLK), + .RD_CLK (RD_CLK), + .RST (RST), + .WR_RST (WR_RST), + .RD_RST (RD_RST), + .DIN (DIN), + .WR_EN (WR_EN), + .RD_EN (RD_EN_FIFO_IN), + .RD_EN_USER (RD_EN), + .PROG_EMPTY_THRESH (PROG_EMPTY_THRESH), + .PROG_EMPTY_THRESH_ASSERT (PROG_EMPTY_THRESH_ASSERT), + .PROG_EMPTY_THRESH_NEGATE (PROG_EMPTY_THRESH_NEGATE), + .PROG_FULL_THRESH (PROG_FULL_THRESH), + .PROG_FULL_THRESH_ASSERT (PROG_FULL_THRESH_ASSERT), + .PROG_FULL_THRESH_NEGATE (PROG_FULL_THRESH_NEGATE), + .INJECTSBITERR (inject_sbit_err), + .INJECTDBITERR (inject_dbit_err), + .USER_EMPTY_FB (EMPTY_P0_OUT), + .DOUT (DOUT_FIFO_OUT), + .FULL (FULL_FIFO_OUT), + .ALMOST_FULL (ALMOST_FULL_FIFO_OUT), + .WR_ACK (WR_ACK_FIFO_OUT), + .OVERFLOW (OVERFLOW_FIFO_OUT), + .EMPTY (EMPTY_FIFO_OUT), + .ALMOST_EMPTY (ALMOST_EMPTY_FIFO_OUT), + .VALID (VALID_FIFO_OUT), + .UNDERFLOW (UNDERFLOW_FIFO_OUT), + .RD_DATA_COUNT (RD_DATA_COUNT_FIFO_OUT), + .WR_DATA_COUNT (WR_DATA_COUNT_FIFO_OUT), + .PROG_FULL (PROG_FULL_FIFO_OUT), + .PROG_EMPTY (PROG_EMPTY_FIFO_OUT), + .SBITERR (sbiterr_fifo_out), + .DBITERR (dbiterr_fifo_out) + ); +end + +endcase +endgenerate + + + //************************************************************************** + // Connect Internal Signals + // (Signals labeled internal_*) + // In the normal case, these signals tie directly to the FIFO's inputs and + // outputs. + // In the case of Preload Latency 0 or 1, there are intermediate + // signals between the internal FIFO and the preload logic. + //************************************************************************** + + + //*********************************************** + // If First-Word Fall-Through, instantiate + // the preload0 (FWFT) module + //*********************************************** + generate + if (C_PRELOAD_REGS==1 && C_PRELOAD_LATENCY==0) begin : block2 + + + fifo_generator_v5_3_bhv_ver_preload0 + #( + C_DOUT_RST_VAL, + C_DOUT_WIDTH, + C_HAS_RST, + C_ENABLE_RST_SYNC, + C_HAS_SRST, + C_USE_DOUT_RST, + C_USE_ECC, + C_VALID_LOW, + C_UNDERFLOW_LOW, + C_MEMORY_TYPE + ) + fgpl0 + ( + .RD_CLK (RD_CLK_P0_IN), + .RD_RST (RST_P0_IN), + .SRST (SRST), + .RD_EN (RD_EN_P0_IN), + .FIFOEMPTY (EMPTY_P0_IN), + .FIFODATA (DATA_P0_IN), + .FIFOSBITERR (sbiterr_fifo_out), + .FIFODBITERR (dbiterr_fifo_out), + .USERDATA (DATA_P0_OUT), + .USERVALID (VALID_P0_OUT), + .USEREMPTY (EMPTY_P0_OUT), + .USERALMOSTEMPTY (ALMOSTEMPTY_P0_OUT), + .USERUNDERFLOW (UNDERFLOW_P0_OUT), + .RAMVALID (RAMVALID_P0_OUT), + .FIFORDEN (RDEN_P0_OUT), + .USERSBITERR (SBITERR), + .USERDBITERR (DBITERR) + ); + + + //*********************************************** + // Connect inputs to preload (FWFT) module + //*********************************************** + //Connect the RD_CLK of the Preload (FWFT) module to CLK if we + // have a common-clock FIFO, or RD_CLK if we have an + // independent clock FIFO + assign RD_CLK_P0_IN = ((C_VERILOG_IMPL == 0) ? CLK : RD_CLK); + assign RST_P0_IN = (C_ENABLE_RST_SYNC == 0) ? RD_RST : (C_HAS_RST == 1) ? RST : 0; + assign RD_EN_P0_IN = RD_EN; + assign EMPTY_P0_IN = EMPTY_FIFO_OUT; + assign DATA_P0_IN = DOUT_FIFO_OUT; + + //*********************************************** + // Connect outputs from preload (FWFT) module + //*********************************************** + assign DOUT = DATA_P0_OUT; + assign VALID = VALID_P0_OUT ; + assign EMPTY = EMPTY_P0_OUT; + assign ALMOST_EMPTY = ALMOSTEMPTY_P0_OUT; + assign UNDERFLOW = UNDERFLOW_P0_OUT ; + + assign RD_EN_FIFO_IN = RDEN_P0_OUT; + + + //*********************************************** + // Create DATA_COUNT from First-Word Fall-Through + // data count + //*********************************************** + assign DATA_COUNT = (C_USE_FWFT_DATA_COUNT == 0)? DATA_COUNT_FIFO_OUT: + (C_DATA_COUNT_WIDTH>C_RD_PNTR_WIDTH) ? DATA_COUNT_FWFT[C_RD_PNTR_WIDTH:0] : + DATA_COUNT_FWFT[C_RD_PNTR_WIDTH:C_RD_PNTR_WIDTH-C_DATA_COUNT_WIDTH+1]; + + //*********************************************** + // Create DATA_COUNT from First-Word Fall-Through + // data count + //*********************************************** + always @ (posedge RD_CLK or posedge RST_P0_IN) begin + if (RST_P0_IN) begin + EMPTY_P0_OUT_Q <= #`TCQ 1; + ALMOSTEMPTY_P0_OUT_Q <= #`TCQ 1; + end else begin + EMPTY_P0_OUT_Q <= #`TCQ EMPTY_P0_OUT; + ALMOSTEMPTY_P0_OUT_Q <= #`TCQ ALMOSTEMPTY_P0_OUT; + end + end //always + + + //*********************************************** + // logic for common-clock data count when FWFT is selected + //*********************************************** + initial begin + SS_FWFT_RD = 1'b0; + DATA_COUNT_FWFT = 0 ; + SS_FWFT_WR = 1'b0 ; + end //initial + + + //*********************************************** + // common-clock data count is implemented as an + // up-down counter. SS_FWFT_WR and SS_FWFT_RD + // are the up/down enables for the counter. + //*********************************************** + always @ (RD_EN or VALID_P0_OUT or WR_EN or FULL_FIFO_OUT) begin + if (C_VALID_LOW == 1) begin + SS_FWFT_RD = RD_EN && ~VALID_P0_OUT ; + end else begin + SS_FWFT_RD = RD_EN && VALID_P0_OUT ; + end + SS_FWFT_WR = (WR_EN && (~FULL_FIFO_OUT)) ; + end + + //*********************************************** + // common-clock data count is implemented as an + // up-down counter for FWFT. This always block + // calculates the counter. + //*********************************************** + always @ (posedge RD_CLK_P0_IN or posedge RST_P0_IN) begin + if (RST_P0_IN) begin + DATA_COUNT_FWFT <= #`TCQ 0; + end else begin + if (SRST && (C_HAS_SRST == 1) ) begin + DATA_COUNT_FWFT <= #`TCQ 0; + end else begin + case ( {SS_FWFT_WR, SS_FWFT_RD}) + 2'b00: DATA_COUNT_FWFT <= #`TCQ DATA_COUNT_FWFT ; + 2'b01: DATA_COUNT_FWFT <= #`TCQ DATA_COUNT_FWFT - 1 ; + 2'b10: DATA_COUNT_FWFT <= #`TCQ DATA_COUNT_FWFT + 1 ; + 2'b11: DATA_COUNT_FWFT <= #`TCQ DATA_COUNT_FWFT ; + endcase + end //if SRST + end //IF RST + end //always + + + end else begin : block2 //if !(C_PRELOAD_REGS==1 && C_PRELOAD_LATENCY==0) + + //*********************************************** + // If NOT First-Word Fall-Through, wire the outputs + // of the internal _ss or _as FIFO directly to the + // output, and do not instantiate the preload0 + // module. + //*********************************************** + + assign RD_CLK_P0_IN = 0; + assign RST_P0_IN = 0; + assign RD_EN_P0_IN = 0; + + assign RD_EN_FIFO_IN = RD_EN; + + assign DOUT = DOUT_FIFO_OUT; + assign DATA_P0_IN = 0; + assign VALID = VALID_FIFO_OUT; + assign EMPTY = EMPTY_FIFO_OUT; + assign ALMOST_EMPTY = ALMOST_EMPTY_FIFO_OUT; + assign EMPTY_P0_IN = 0; + assign UNDERFLOW = UNDERFLOW_FIFO_OUT; + assign DATA_COUNT = DATA_COUNT_FIFO_OUT; + assign SBITERR = sbiterr_fifo_out; + assign DBITERR = dbiterr_fifo_out; + + end //if !(C_PRELOAD_REGS==1 && C_PRELOAD_LATENCY==0) + endgenerate + + + //*********************************************** + // Connect user flags to internal signals + //*********************************************** + + //If we are using extra logic for the FWFT data count, then override the + //RD_DATA_COUNT output when we are EMPTY or ALMOST_EMPTY. + //RD_DATA_COUNT is 0 when EMPTY and 1 when ALMOST_EMPTY. + generate + if (C_USE_FWFT_DATA_COUNT==1 && (C_RD_DATA_COUNT_WIDTH>C_RD_PNTR_WIDTH) ) begin : block3 + assign RD_DATA_COUNT = (EMPTY_P0_OUT_Q | RST_P0_IN) ? 0 : (ALMOSTEMPTY_P0_OUT_Q ? 1 : RD_DATA_COUNT_FIFO_OUT); + end //block3 + endgenerate + + //If we are using extra logic for the FWFT data count, then override the + //RD_DATA_COUNT output when we are EMPTY or ALMOST_EMPTY. + //Due to asymmetric ports, RD_DATA_COUNT is 0 when EMPTY or ALMOST_EMPTY. + generate + if (C_USE_FWFT_DATA_COUNT==1 && (C_RD_DATA_COUNT_WIDTH <=C_RD_PNTR_WIDTH) ) begin : block30 + assign RD_DATA_COUNT = (EMPTY_P0_OUT_Q | RST_P0_IN) ? 0 : (ALMOSTEMPTY_P0_OUT_Q ? 0 : RD_DATA_COUNT_FIFO_OUT); + end //block30 + endgenerate + + //If we are not using extra logic for the FWFT data count, + //then connect RD_DATA_COUNT to the RD_DATA_COUNT from the + //internal FIFO instance + generate + if (C_USE_FWFT_DATA_COUNT==0 ) begin : block31 + assign RD_DATA_COUNT = RD_DATA_COUNT_FIFO_OUT; + end + endgenerate + + //Always connect WR_DATA_COUNT to the WR_DATA_COUNT from the internal + //FIFO instance + generate + if (C_USE_FWFT_DATA_COUNT==1) begin : block4 + assign WR_DATA_COUNT = WR_DATA_COUNT_FIFO_OUT; + end + else begin : block4 + assign WR_DATA_COUNT = WR_DATA_COUNT_FIFO_OUT; + end + endgenerate + + + //Connect other flags to the internal FIFO instance + assign FULL = FULL_FIFO_OUT; + assign ALMOST_FULL = ALMOST_FULL_FIFO_OUT; + assign WR_ACK = WR_ACK_FIFO_OUT; + assign OVERFLOW = OVERFLOW_FIFO_OUT; + assign PROG_FULL = PROG_FULL_FIFO_OUT; + assign PROG_EMPTY = PROG_EMPTY_FIFO_OUT; + + + // if an asynchronous FIFO has been selected, display a message that the FIFO + // will not be cycle-accurate in simulation + initial begin + if (C_IMPLEMENTATION_TYPE == 2) begin + $display("WARNING: Behavioral models for independent clock FIFO configurations are not cycle-accurate. You may wish to choose the structural simulation model instead of the behavioral model. This will ensure accurate behavior and latencies during simulation. You can enable this from CORE Generator by selecting Project -> Project Options -> Generation tab -> Structural Simulation. See the FIFO Generator User Guide for more information."); + end else if (C_MEMORY_TYPE == 4) begin + $display("FAILURE : Behavioral models for Virtex-4, Virtex-5 and Virtex-6 built-in FIFO configurations is currently not supported. Please select the structural simulation model option in CORE Generator. You can enable this in CORE Generator by selecting Project -> Project Options -> Generation tab -> Structural Simulation. See the FIFO Generator User Guide for more information."); + $finish; + end + end //initial + +endmodule //FIFO_GENERATOR_V5_3 + + + +/******************************************************************************* + * Declaration of Independent-Clocks FIFO Module + ******************************************************************************/ +module fifo_generator_v5_3_bhv_ver_as + ( + WR_CLK, RD_CLK, RST, WR_RST, RD_RST, DIN, WR_EN, RD_EN, RD_EN_USER, + PROG_EMPTY_THRESH, PROG_EMPTY_THRESH_ASSERT, PROG_EMPTY_THRESH_NEGATE, + PROG_FULL_THRESH, PROG_FULL_THRESH_ASSERT, PROG_FULL_THRESH_NEGATE, + INJECTDBITERR, INJECTSBITERR, USER_EMPTY_FB, DOUT, FULL, ALMOST_FULL, WR_ACK, OVERFLOW, + EMPTY, ALMOST_EMPTY, VALID, UNDERFLOW, RD_DATA_COUNT, WR_DATA_COUNT, + PROG_FULL, PROG_EMPTY, SBITERR, DBITERR + ); + + /*************************************************************************** + * Declare user parameters and their defaults + ***************************************************************************/ + parameter C_DATA_COUNT_WIDTH = 2; + parameter C_DIN_WIDTH = 8; + parameter C_DOUT_RST_VAL = ""; + parameter C_DOUT_WIDTH = 8; + parameter C_FULL_FLAGS_RST_VAL = 1; + parameter C_HAS_ALMOST_EMPTY = 0; + parameter C_HAS_ALMOST_FULL = 0; + parameter C_HAS_DATA_COUNT = 0; + parameter C_HAS_OVERFLOW = 0; + parameter C_HAS_RD_DATA_COUNT = 0; + parameter C_HAS_RST = 0; + parameter C_HAS_UNDERFLOW = 0; + parameter C_HAS_VALID = 0; + parameter C_HAS_WR_ACK = 0; + parameter C_HAS_WR_DATA_COUNT = 0; + parameter C_IMPLEMENTATION_TYPE = 0; + parameter C_MEMORY_TYPE = 1; + parameter C_OVERFLOW_LOW = 0; + parameter C_PRELOAD_LATENCY = 1; + parameter C_PRELOAD_REGS = 0; + parameter C_PROG_EMPTY_THRESH_ASSERT_VAL = 0; + parameter C_PROG_EMPTY_THRESH_NEGATE_VAL = 0; + parameter C_PROG_EMPTY_TYPE = 0; + parameter C_PROG_FULL_THRESH_ASSERT_VAL = 0; + parameter C_PROG_FULL_THRESH_NEGATE_VAL = 0; + parameter C_PROG_FULL_TYPE = 0; + parameter C_RD_DATA_COUNT_WIDTH = 2; + parameter C_RD_DEPTH = 256; + parameter C_RD_PNTR_WIDTH = 8; + parameter C_UNDERFLOW_LOW = 0; + parameter C_USE_DOUT_RST = 0; + parameter C_USE_EMBEDDED_REG = 0; + parameter C_USE_FWFT_DATA_COUNT = 0; + parameter C_VALID_LOW = 0; + parameter C_WR_ACK_LOW = 0; + parameter C_WR_DATA_COUNT_WIDTH = 2; + parameter C_WR_DEPTH = 256; + parameter C_WR_PNTR_WIDTH = 8; + parameter C_USE_ECC = 0; + parameter C_ENABLE_RST_SYNC = 1; + parameter C_ERROR_INJECTION_TYPE = 0; + + /*************************************************************************** + * Declare Input and Output Ports + ***************************************************************************/ + input [C_DIN_WIDTH-1:0] DIN; + input [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH; + input [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_ASSERT; + input [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_NEGATE; + input [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH; + input [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_ASSERT; + input [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_NEGATE; + input RD_CLK; + input RD_EN; + input RD_EN_USER; + input RST; + input WR_RST; + input RD_RST; + input WR_CLK; + input WR_EN; + input INJECTDBITERR; + input INJECTSBITERR; + input USER_EMPTY_FB; + output ALMOST_EMPTY; + output ALMOST_FULL; + output [C_DOUT_WIDTH-1:0] DOUT; + output EMPTY; + output FULL; + output OVERFLOW; + output PROG_EMPTY; + output PROG_FULL; + output VALID; + output [C_RD_DATA_COUNT_WIDTH-1:0] RD_DATA_COUNT; + output UNDERFLOW; + output WR_ACK; + output [C_WR_DATA_COUNT_WIDTH-1:0] WR_DATA_COUNT; + output SBITERR; + output DBITERR; + + /************************************************************************* + * Declare the type for each Input/Output port, and connect each I/O + * to it's associated internal signal in the behavioral model + * + * The values for the outputs are assigned in assign statements immediately + * following wire, parameter, and function declarations in this code. + *************************************************************************/ + //Inputs + wire [C_DIN_WIDTH-1:0] DIN; + wire [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH; + wire [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_ASSERT; + wire [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_NEGATE; + wire [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH; + wire [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_ASSERT; + wire [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_NEGATE; + wire RD_CLK; + wire RD_EN; + wire RD_EN_USER; + wire RST; + wire WR_RST; + wire RD_RST; + wire WR_CLK; + wire WR_EN; + wire INJECTSBITERR; + wire INJECTDBITERR; + + //Outputs + reg ALMOST_EMPTY = 1'b1; + reg ALMOST_FULL = C_FULL_FLAGS_RST_VAL; + wire [C_DOUT_WIDTH-1:0] DOUT; + reg EMPTY = 1'b1; + reg FULL = C_FULL_FLAGS_RST_VAL; + wire OVERFLOW; + wire PROG_EMPTY; + wire PROG_FULL; + wire VALID; + wire [C_RD_DATA_COUNT_WIDTH-1:0] RD_DATA_COUNT; + reg [C_RD_PNTR_WIDTH:0] rd_data_count_int = 0; + wire UNDERFLOW; + wire WR_ACK; + wire [C_WR_DATA_COUNT_WIDTH-1:0] WR_DATA_COUNT; + reg [C_WR_PNTR_WIDTH:0] wr_data_count_int = 0; + reg [C_WR_PNTR_WIDTH:0] wdc_fwft_ext_as = 0; + wire SBITERR; + wire DBITERR; + + + /*************************************************************************** + * Parameters used as constants + **************************************************************************/ + //When RST is present, set FULL reset value to '1'. + //If core has no RST, make sure FULL powers-on as '0'. + parameter C_DEPTH_RATIO_WR = + (C_WR_DEPTH>C_RD_DEPTH) ? (C_WR_DEPTH/C_RD_DEPTH) : 1; + parameter C_DEPTH_RATIO_RD = + (C_RD_DEPTH>C_WR_DEPTH) ? (C_RD_DEPTH/C_WR_DEPTH) : 1; + parameter C_FIFO_WR_DEPTH = C_WR_DEPTH - 1; + parameter C_FIFO_RD_DEPTH = C_RD_DEPTH - 1; + + // C_DEPTH_RATIO_WR | C_DEPTH_RATIO_RD | C_PNTR_WIDTH | EXTRA_WORDS_DC + // -----------------|------------------|-----------------|--------------- + // 1 | 8 | C_RD_PNTR_WIDTH | 2 + // 1 | 4 | C_RD_PNTR_WIDTH | 2 + // 1 | 2 | C_RD_PNTR_WIDTH | 2 + // 1 | 1 | C_WR_PNTR_WIDTH | 2 + // 2 | 1 | C_WR_PNTR_WIDTH | 4 + // 4 | 1 | C_WR_PNTR_WIDTH | 8 + // 8 | 1 | C_WR_PNTR_WIDTH | 16 + + localparam C_PNTR_WIDTH = (C_WR_PNTR_WIDTH>=C_RD_PNTR_WIDTH) ? C_WR_PNTR_WIDTH : C_RD_PNTR_WIDTH; + wire [C_PNTR_WIDTH:0] EXTRA_WORDS_DC = (C_DEPTH_RATIO_WR == 1) ? 2 : (2 * C_DEPTH_RATIO_WR/C_DEPTH_RATIO_RD); + + parameter [31:0] reads_per_write = C_DIN_WIDTH/C_DOUT_WIDTH; + + parameter [31:0] log2_reads_per_write = log2_val(reads_per_write); + + parameter [31:0] writes_per_read = C_DOUT_WIDTH/C_DIN_WIDTH; + + parameter [31:0] log2_writes_per_read = log2_val(writes_per_read); + + + + /************************************************************************** + * FIFO Contents Tracking and Data Count Calculations + *************************************************************************/ + + // Memory which will be used to simulate a FIFO + reg [C_DIN_WIDTH-1:0] memory[C_WR_DEPTH-1:0]; + // Local parameters used to determine whether to inject ECC error or not + localparam SYMMETRIC_PORT = (C_DIN_WIDTH == C_DOUT_WIDTH) ? 1 : 0; + localparam ERR_INJECTION = (C_ERROR_INJECTION_TYPE != 0) ? 1 : 0; + localparam ENABLE_ERR_INJECTION = C_USE_ECC && SYMMETRIC_PORT && ERR_INJECTION; + // Array that holds the error injection type (single/double bit error) on + // a specific write operation, which is returned on read to corrupt the + // output data. + reg [1:0] ecc_err[C_WR_DEPTH-1:0]; + + //The amount of data stored in the FIFO at any time is given + // by num_wr_bits (in the WR_CLK domain) and num_rd_bits (in the RD_CLK + // domain. + //num_wr_bits is calculated by considering the total words in the FIFO, + // and the state of the read pointer (which may not have yet crossed clock + // domains.) + //num_rd_bits is calculated by considering the total words in the FIFO, + // and the state of the write pointer (which may not have yet crossed clock + // domains.) + reg [31:0] num_wr_bits; + reg [31:0] num_rd_bits; + reg [31:0] next_num_wr_bits; + reg [31:0] next_num_rd_bits; + + //The write pointer - tracks write operations + // (Works opposite to core: wr_ptr is a DOWN counter) + reg [31:0] wr_ptr; + reg [C_WR_PNTR_WIDTH-1:0] wr_pntr = 0; // UP counter: Rolls back to 0 when reaches to max value. + reg [C_WR_PNTR_WIDTH-1:0] wr_pntr_rd1 = 0; + reg [C_WR_PNTR_WIDTH-1:0] wr_pntr_rd2 = 0; + reg [C_WR_PNTR_WIDTH-1:0] wr_pntr_rd3 = 0; + wire [C_RD_PNTR_WIDTH-1:0] adj_wr_pntr_rd; + reg [C_WR_PNTR_WIDTH-1:0] wr_pntr_rd = 0; + wire wr_rst_i; + reg wr_rst_d1 =0; + + //The read pointer - tracks read operations + // (rd_ptr Works opposite to core: rd_ptr is a DOWN counter) + reg [31:0] rd_ptr; + reg [C_RD_PNTR_WIDTH-1:0] rd_pntr = 0; // UP counter: Rolls back to 0 when reaches to max value. + reg [C_RD_PNTR_WIDTH-1:0] rd_pntr_wr1 = 0; + reg [C_RD_PNTR_WIDTH-1:0] rd_pntr_wr2 = 0; + reg [C_RD_PNTR_WIDTH-1:0] rd_pntr_wr3 = 0; + reg [C_RD_PNTR_WIDTH-1:0] rd_pntr_wr4 = 0; + wire [C_WR_PNTR_WIDTH-1:0] adj_rd_pntr_wr; + reg [C_RD_PNTR_WIDTH-1:0] rd_pntr_wr = 0; + wire rd_rst_i; + wire ram_rd_en; + reg ram_rd_en_d1 = 1'b0; + + + // Delayed ram_rd_en is needed only for STD Embedded register option + generate + if (C_PRELOAD_LATENCY == 2) begin : grd_d + always @ (posedge RD_CLK or posedge rd_rst_i) begin + if (rd_rst_i) + ram_rd_en_d1 <= #`TCQ 1'b0; + else + ram_rd_en_d1 <= #`TCQ ram_rd_en; + end + end + endgenerate + + // Write pointer adjustment based on pointers width for EMPTY/ALMOST_EMPTY generation + generate + if (C_RD_PNTR_WIDTH > C_WR_PNTR_WIDTH) begin : rdg // Read depth greater than write depth + assign adj_wr_pntr_rd[C_RD_PNTR_WIDTH-1:C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH] = wr_pntr_rd; + assign adj_wr_pntr_rd[C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH-1:0] = 0; + end else begin : rdl // Read depth lesser than or equal to write depth + assign adj_wr_pntr_rd = wr_pntr_rd[C_WR_PNTR_WIDTH-1:C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH]; + end + endgenerate + + // Generate Empty and Almost Empty + // ram_rd_en used to determine EMPTY should depend on the EMPTY. + assign ram_rd_en = RD_EN & !EMPTY; + assign empty_int = ((adj_wr_pntr_rd == rd_pntr) || (ram_rd_en && (adj_wr_pntr_rd == (rd_pntr+1'h1)))); + assign almost_empty_int = ((adj_wr_pntr_rd == (rd_pntr+1'h1)) || (ram_rd_en && (adj_wr_pntr_rd == (rd_pntr+2'h2)))); + + // Register Empty and Almost Empty + always @ (posedge RD_CLK or posedge rd_rst_i) + begin + if (rd_rst_i) begin + EMPTY <= #`TCQ 1'b1; + ALMOST_EMPTY <= #`TCQ 1'b1; + rd_data_count_int <= #`TCQ {C_RD_PNTR_WIDTH-1{1'b0}}; + end else begin + rd_data_count_int <= #`TCQ {(adj_wr_pntr_rd[C_RD_PNTR_WIDTH-1:0] - rd_pntr[C_RD_PNTR_WIDTH-1:0]), 1'b0}; + + if (empty_int) + EMPTY <= #`TCQ 1'b1; + else + EMPTY <= #`TCQ 1'b0; + + if (!EMPTY) begin + if (almost_empty_int) + ALMOST_EMPTY <= #`TCQ 1'b1; + else + ALMOST_EMPTY <= #`TCQ 1'b0; + end + end // rd_rst_i + end // always + + // Read pointer adjustment based on pointers width for EMPTY/ALMOST_EMPTY generation + generate + if (C_WR_PNTR_WIDTH > C_RD_PNTR_WIDTH) begin : wdg // Write depth greater than read depth + assign adj_rd_pntr_wr[C_WR_PNTR_WIDTH-1:C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH] = rd_pntr_wr; + assign adj_rd_pntr_wr[C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH-1:0] = 0; + end else begin : wdl // Write depth lesser than or equal to read depth + assign adj_rd_pntr_wr = rd_pntr_wr[C_RD_PNTR_WIDTH-1:C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH]; + end + endgenerate + + // Generate FULL and ALMOST_FULL + // ram_wr_en used to determine FULL should depend on the FULL. + assign ram_wr_en = WR_EN & !FULL; + assign full_int = ((adj_rd_pntr_wr == (wr_pntr+1'h1)) || (ram_wr_en && (adj_rd_pntr_wr == (wr_pntr+2'h2)))); + assign almost_full_int = ((adj_rd_pntr_wr == (wr_pntr+2'h2)) || (ram_wr_en && (adj_rd_pntr_wr == (wr_pntr+3'h3)))); + + // Register FULL and ALMOST_FULL Empty + always @ (posedge WR_CLK or posedge wr_rst_i) + begin + if (wr_rst_i) begin + FULL <= #`TCQ C_FULL_FLAGS_RST_VAL; + ALMOST_FULL <= #`TCQ C_FULL_FLAGS_RST_VAL; + wr_data_count_int <= #`TCQ {C_WR_DATA_COUNT_WIDTH-1{1'b0}}; + end else begin + wr_data_count_int <= #`TCQ {(wr_pntr[C_WR_PNTR_WIDTH-1:0] - adj_rd_pntr_wr[C_WR_PNTR_WIDTH-1:0]), 1'b0}; + if (full_int) begin + FULL <= #`TCQ 1'b1; + end else begin + FULL <= #`TCQ 1'b0; + end + + if (wr_rst_d1 && !wr_rst_i) begin + ALMOST_FULL <= #`TCQ 1'b0; + end else if (!FULL) begin + if (almost_full_int) + ALMOST_FULL <= #`TCQ 1'b1; + else + ALMOST_FULL <= #`TCQ 1'b0; + end + end // wr_rst_i + end // always + + // Determine which stage in FWFT registers are valid + reg stage1_valid = 0; + reg stage2_valid = 0; + generate + if (C_PRELOAD_LATENCY == 0) begin : grd_fwft_proc + always @ (posedge RD_CLK or posedge rd_rst_i) begin + if (rd_rst_i) begin + stage1_valid <= #`TCQ 0; + stage2_valid <= #`TCQ 0; + end else begin + + if (!stage1_valid && !stage2_valid) begin + if (!EMPTY) + stage1_valid <= #`TCQ 1'b1; + else + stage1_valid <= #`TCQ 1'b0; + end else if (stage1_valid && !stage2_valid) begin + if (EMPTY) begin + stage1_valid <= #`TCQ 1'b0; + stage2_valid <= #`TCQ 1'b1; + end else begin + stage1_valid <= #`TCQ 1'b1; + stage2_valid <= #`TCQ 1'b1; + end + end else if (!stage1_valid && stage2_valid) begin + if (EMPTY && RD_EN_USER) begin + stage1_valid <= #`TCQ 1'b0; + stage2_valid <= #`TCQ 1'b0; + end else if (!EMPTY && RD_EN_USER) begin + stage1_valid <= #`TCQ 1'b1; + stage2_valid <= #`TCQ 1'b0; + end else if (!EMPTY && !RD_EN_USER) begin + stage1_valid <= #`TCQ 1'b1; + stage2_valid <= #`TCQ 1'b1; + end else begin + stage1_valid <= #`TCQ 1'b0; + stage2_valid <= #`TCQ 1'b1; + end + end else if (stage1_valid && stage2_valid) begin + if (EMPTY && RD_EN_USER) begin + stage1_valid <= #`TCQ 1'b0; + stage2_valid <= #`TCQ 1'b1; + end else begin + stage1_valid <= #`TCQ 1'b1; + stage2_valid <= #`TCQ 1'b1; + end + end else begin + stage1_valid <= #`TCQ 1'b0; + stage2_valid <= #`TCQ 1'b0; + end + end // rd_rst_i + end // always + end + endgenerate + + //Pointers passed into opposite clock domain + reg [31:0] wr_ptr_rdclk; + reg [31:0] wr_ptr_rdclk_next; + reg [31:0] rd_ptr_wrclk; + reg [31:0] rd_ptr_wrclk_next; + + //Amount of data stored in the FIFO scaled to the narrowest (deepest) port + // (Do not include data in FWFT stages) + //Used to calculate PROG_EMPTY. + wire [31:0] num_read_words_pe = + num_rd_bits/(C_DOUT_WIDTH/C_DEPTH_RATIO_WR); + + //Amount of data stored in the FIFO scaled to the narrowest (deepest) port + // (Do not include data in FWFT stages) + //Used to calculate PROG_FULL. + wire [31:0] num_write_words_pf = + num_wr_bits/(C_DIN_WIDTH/C_DEPTH_RATIO_RD); + + /************************** + * Read Data Count + *************************/ + + reg [31:0] num_read_words_dc; + reg [C_RD_DATA_COUNT_WIDTH-1:0] num_read_words_sized_i; + + always @(num_rd_bits) begin + if (C_USE_FWFT_DATA_COUNT) begin + + //If using extra logic for FWFT Data Counts, + // then scale FIFO contents to read domain, + // and add two read words for FWFT stages + //This value is only a temporary value and not used in the code. + num_read_words_dc = (num_rd_bits/C_DOUT_WIDTH+2); + + //Trim the read words for use with RD_DATA_COUNT + num_read_words_sized_i = + num_read_words_dc[C_RD_PNTR_WIDTH : C_RD_PNTR_WIDTH-C_RD_DATA_COUNT_WIDTH+1]; + + end else begin + + //If not using extra logic for FWFT Data Counts, + // then scale FIFO contents to read domain. + //This value is only a temporary value and not used in the code. + num_read_words_dc = num_rd_bits/C_DOUT_WIDTH; + + //Trim the read words for use with RD_DATA_COUNT + num_read_words_sized_i = + num_read_words_dc[C_RD_PNTR_WIDTH-1 : C_RD_PNTR_WIDTH-C_RD_DATA_COUNT_WIDTH]; + + end //if (C_USE_FWFT_DATA_COUNT) + end //always + + + /************************** + * Write Data Count + *************************/ + + reg [31:0] num_write_words_dc; + reg [C_WR_DATA_COUNT_WIDTH-1:0] num_write_words_sized_i; + + always @(num_wr_bits) begin + if (C_USE_FWFT_DATA_COUNT) begin + + //Calculate the Data Count value for the number of write words, + // when using First-Word Fall-Through with extra logic for Data + // Counts. This takes into consideration the number of words that + // are expected to be stored in the FWFT register stages (it always + // assumes they are filled). + //This value is scaled to the Write Domain. + //The expression (((A-1)/B))+1 divides A/B, but takes the + // ceiling of the result. + //When num_wr_bits==0, set the result manually to prevent + // division errors. + //EXTRA_WORDS_DC is the number of words added to write_words + // due to FWFT. + //This value is only a temporary value and not used in the code. + num_write_words_dc = (num_wr_bits==0) ? EXTRA_WORDS_DC : (((num_wr_bits-1)/C_DIN_WIDTH)+1) + EXTRA_WORDS_DC ; + + //Trim the write words for use with WR_DATA_COUNT + num_write_words_sized_i = + num_write_words_dc[C_WR_PNTR_WIDTH : C_WR_PNTR_WIDTH-C_WR_DATA_COUNT_WIDTH+1]; + + end else begin + + //Calculate the Data Count value for the number of write words, when NOT + // using First-Word Fall-Through with extra logic for Data Counts. This + // calculates only the number of words in the internal FIFO. + //The expression (((A-1)/B))+1 divides A/B, but takes the + // ceiling of the result. + //This value is scaled to the Write Domain. + //When num_wr_bits==0, set the result manually to prevent + // division errors. + //This value is only a temporary value and not used in the code. + num_write_words_dc = (num_wr_bits==0) ? 0 : ((num_wr_bits-1)/C_DIN_WIDTH)+1; + + //Trim the read words for use with RD_DATA_COUNT + num_write_words_sized_i = + num_write_words_dc[C_WR_PNTR_WIDTH-1 : C_WR_PNTR_WIDTH-C_WR_DATA_COUNT_WIDTH]; + + end //if (C_USE_FWFT_DATA_COUNT) + end //always + + + + /*************************************************************************** + * Internal registers and wires + **************************************************************************/ + + //Temporary signals used for calculating the model's outputs. These + //are only used in the assign statements immediately following wire, + //parameter, and function declarations. + wire [C_DOUT_WIDTH-1:0] ideal_dout_out; + wire valid_i; + wire valid_out; + wire underflow_i; + + //Ideal FIFO signals. These are the raw output of the behavioral model, + //which behaves like an ideal FIFO. + reg [1:0] err_type = 0; + reg [1:0] err_type_d1 = 0; + reg [C_DOUT_WIDTH-1:0] ideal_dout = 0; + reg [C_DOUT_WIDTH-1:0] ideal_dout_d1 = 0; + reg ideal_wr_ack = 0; + reg ideal_valid = 0; + reg ideal_overflow = 0; + reg ideal_underflow = 0; + reg ideal_prog_full = 0; + reg ideal_prog_empty = 1; + reg [C_WR_DATA_COUNT_WIDTH-1 : 0] ideal_wr_count = 0; + reg [C_RD_DATA_COUNT_WIDTH-1 : 0] ideal_rd_count = 0; + + //Assorted reg values for delayed versions of signals + reg valid_d1 = 0; + + //Internal reset signals + reg rd_rst_asreg =0; + reg rd_rst_asreg_d1 =0; + reg rd_rst_asreg_d2 =0; + reg rd_rst_reg =0; + reg rd_rst_d1 =0; + reg wr_rst_asreg =0; + reg wr_rst_asreg_d1 =0; + reg wr_rst_asreg_d2 =0; + reg wr_rst_reg =0; + + wire rd_rst_comb; + wire wr_rst_comb; + + + //user specified value for reseting the size of the fifo + reg [C_DOUT_WIDTH-1:0] dout_reset_val = 0; + + //temporary registers for WR_RESPONSE_LATENCY feature + + integer tmp_wr_listsize; + integer tmp_rd_listsize; + + //Signal for registered version of prog full and empty + + //Threshold values for Programmable Flags + integer prog_empty_actual_thresh_assert; + integer prog_empty_actual_thresh_negate; + integer prog_full_actual_thresh_assert; + integer prog_full_actual_thresh_negate; + + + /**************************************************************************** + * Function Declarations + ***************************************************************************/ + + /************************************************************************** + * write_fifo + * This task writes a word to the FIFO memory and updates the + * write pointer. + * FIFO size is relative to write domain. + ***************************************************************************/ + task write_fifo; + begin + memory[wr_ptr] <= DIN; + wr_pntr <= #`TCQ wr_pntr + 1; + // Store the type of error injection (double/single) on write + case (C_ERROR_INJECTION_TYPE) + 3: ecc_err[wr_ptr] <= {INJECTDBITERR,INJECTSBITERR}; + 2: ecc_err[wr_ptr] <= {INJECTDBITERR,1'b0}; + 1: ecc_err[wr_ptr] <= {1'b0,INJECTSBITERR}; + default: ecc_err[wr_ptr] <= 0; + endcase + // (Works opposite to core: wr_ptr is a DOWN counter) + if (wr_ptr == 0) begin + wr_ptr <= C_WR_DEPTH - 1; + end else begin + wr_ptr <= wr_ptr - 1; + end + end + endtask // write_fifo + + /************************************************************************** + * read_fifo + * This task reads a word from the FIFO memory and updates the read + * pointer. It's output is the ideal_dout bus. + * FIFO size is relative to write domain. + ***************************************************************************/ + task read_fifo; + integer i; + reg [C_DOUT_WIDTH-1:0] tmp_dout; + reg [C_DIN_WIDTH-1:0] memory_read; + reg [31:0] tmp_rd_ptr; + reg [31:0] rd_ptr_high; + reg [31:0] rd_ptr_low; + reg [1:0] tmp_ecc_err; + begin + rd_pntr <= #`TCQ rd_pntr + 1; + // output is wider than input + if (reads_per_write == 0) begin + tmp_dout = 0; + tmp_rd_ptr = (rd_ptr << log2_writes_per_read)+(writes_per_read-1); + for (i = writes_per_read - 1; i >= 0; i = i - 1) begin + tmp_dout = tmp_dout << C_DIN_WIDTH; + tmp_dout = tmp_dout | memory[tmp_rd_ptr]; + + // (Works opposite to core: rd_ptr is a DOWN counter) + if (tmp_rd_ptr == 0) begin + tmp_rd_ptr = C_WR_DEPTH - 1; + end else begin + tmp_rd_ptr = tmp_rd_ptr - 1; + end + end + + // output is symmetric + end else if (reads_per_write == 1) begin + tmp_dout = memory[rd_ptr][C_DIN_WIDTH-1:0]; + // Retreive the error injection type. Based on the error injection type + // corrupt the output data. + tmp_ecc_err = ecc_err[rd_ptr]; + if (ENABLE_ERR_INJECTION && C_DIN_WIDTH == C_DOUT_WIDTH) begin + if (tmp_ecc_err[1]) begin // Corrupt the output data only for double bit error + if (C_DOUT_WIDTH == 1) + tmp_dout = tmp_dout[C_DOUT_WIDTH-1:0]; + else if (C_DOUT_WIDTH == 2) + tmp_dout = {~tmp_dout[C_DOUT_WIDTH-1],~tmp_dout[C_DOUT_WIDTH-2]}; + else + tmp_dout = {~tmp_dout[C_DOUT_WIDTH-1],~tmp_dout[C_DOUT_WIDTH-2],(tmp_dout << 2)}; + end else begin + tmp_dout = tmp_dout[C_DOUT_WIDTH-1:0]; + end + err_type <= {tmp_ecc_err[1], tmp_ecc_err[0] & !tmp_ecc_err[1]}; + end else begin + err_type <= 0; + end + + // input is wider than output + end else begin + rd_ptr_high = rd_ptr >> log2_reads_per_write; + rd_ptr_low = rd_ptr & (reads_per_write - 1); + memory_read = memory[rd_ptr_high]; + tmp_dout = memory_read >> (rd_ptr_low*C_DOUT_WIDTH); + end + ideal_dout <= tmp_dout; + + // (Works opposite to core: rd_ptr is a DOWN counter) + if (rd_ptr == 0) begin + rd_ptr <= C_RD_DEPTH - 1; + end else begin + rd_ptr <= rd_ptr - 1; + end + end + endtask + + /************************************************************************** + * log2_val + * Returns the 'log2' value for the input value for the supported ratios + ***************************************************************************/ + function [31:0] log2_val; + input [31:0] binary_val; + + begin + if (binary_val == 8) begin + log2_val = 3; + end else if (binary_val == 4) begin + log2_val = 2; + end else begin + log2_val = 1; + end + end + endfunction + + /*********************************************************************** + * hexstr_conv + * Converts a string of type hex to a binary value (for C_DOUT_RST_VAL) + ***********************************************************************/ + function [C_DOUT_WIDTH-1:0] hexstr_conv; + input [(C_DOUT_WIDTH*8)-1:0] def_data; + + integer index,i,j; + reg [3:0] bin; + + begin + index = 0; + hexstr_conv = 'b0; + for( i=C_DOUT_WIDTH-1; i>=0; i=i-1 ) + begin + case (def_data[7:0]) + 8'b00000000 : + begin + bin = 4'b0000; + i = -1; + end + 8'b00110000 : bin = 4'b0000; + 8'b00110001 : bin = 4'b0001; + 8'b00110010 : bin = 4'b0010; + 8'b00110011 : bin = 4'b0011; + 8'b00110100 : bin = 4'b0100; + 8'b00110101 : bin = 4'b0101; + 8'b00110110 : bin = 4'b0110; + 8'b00110111 : bin = 4'b0111; + 8'b00111000 : bin = 4'b1000; + 8'b00111001 : bin = 4'b1001; + 8'b01000001 : bin = 4'b1010; + 8'b01000010 : bin = 4'b1011; + 8'b01000011 : bin = 4'b1100; + 8'b01000100 : bin = 4'b1101; + 8'b01000101 : bin = 4'b1110; + 8'b01000110 : bin = 4'b1111; + 8'b01100001 : bin = 4'b1010; + 8'b01100010 : bin = 4'b1011; + 8'b01100011 : bin = 4'b1100; + 8'b01100100 : bin = 4'b1101; + 8'b01100101 : bin = 4'b1110; + 8'b01100110 : bin = 4'b1111; + default : + begin + bin = 4'bx; + end + endcase + for( j=0; j<4; j=j+1) + begin + if ((index*4)+j < C_DOUT_WIDTH) + begin + hexstr_conv[(index*4)+j] = bin[j]; + end + end + index = index + 1; + def_data = def_data >> 8; + end + end + endfunction + + /************************************************************************* + * Initialize Signals for clean power-on simulation + *************************************************************************/ + initial begin + num_wr_bits = 0; + num_rd_bits = 0; + next_num_wr_bits = 0; + next_num_rd_bits = 0; + rd_ptr = C_RD_DEPTH - 1; + wr_ptr = C_WR_DEPTH - 1; + wr_pntr = 0; + rd_pntr = 0; + rd_ptr_wrclk = rd_ptr; + wr_ptr_rdclk = wr_ptr; + dout_reset_val = hexstr_conv(C_DOUT_RST_VAL); + ideal_dout = dout_reset_val; + err_type = 0; + ideal_dout_d1 = dout_reset_val; + ideal_wr_ack = 1'b0; + ideal_valid = 1'b0; + valid_d1 = 1'b0; + ideal_overflow = 1'b0; + ideal_underflow = 1'b0; + ideal_wr_count = 0; + ideal_rd_count = 0; + ideal_prog_full = 1'b0; + ideal_prog_empty = 1'b1; + end + + + /************************************************************************* + * Connect the module inputs and outputs to the internal signals of the + * behavioral model. + *************************************************************************/ + //Inputs + /* + wire [C_DIN_WIDTH-1:0] DIN; + wire [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH; + wire [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_ASSERT; + wire [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_NEGATE; + wire [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH; + wire [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_ASSERT; + wire [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_NEGATE; + wire RD_CLK; + wire RD_EN; + wire RST; + wire WR_CLK; + wire WR_EN; + */ + + //*************************************************************************** + // Dout may change behavior based on latency + //*************************************************************************** + assign ideal_dout_out[C_DOUT_WIDTH-1:0] = (C_PRELOAD_LATENCY==2 && + (C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1))? + ideal_dout_d1: ideal_dout; + assign DOUT[C_DOUT_WIDTH-1:0] = ideal_dout_out; + + //*************************************************************************** + // Assign SBITERR and DBITERR based on latency + //*************************************************************************** + assign SBITERR = (C_ERROR_INJECTION_TYPE == 1 || C_ERROR_INJECTION_TYPE == 3) && + (C_PRELOAD_LATENCY == 2 && + (C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1)) ? + err_type_d1[0]: err_type[0]; + assign DBITERR = (C_ERROR_INJECTION_TYPE == 2 || C_ERROR_INJECTION_TYPE == 3) && + (C_PRELOAD_LATENCY==2 && (C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1)) ? + err_type_d1[1]: err_type[1]; + + + //*************************************************************************** + // Overflow may be active-low + //*************************************************************************** + generate + if (C_HAS_OVERFLOW==1) begin : blockOF1 + assign OVERFLOW = ideal_overflow ? !C_OVERFLOW_LOW : C_OVERFLOW_LOW; + end + endgenerate + + assign PROG_EMPTY = ideal_prog_empty; + assign PROG_FULL = ideal_prog_full; + + //*************************************************************************** + // Valid may change behavior based on latency or active-low + //*************************************************************************** + generate + if (C_HAS_VALID==1) begin : blockVL1 + assign valid_i = (C_PRELOAD_LATENCY==0) ? (RD_EN & ~EMPTY) : ideal_valid; + assign valid_out = (C_PRELOAD_LATENCY==2 && + (C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1))? + valid_d1: valid_i; + assign VALID = valid_out ? !C_VALID_LOW : C_VALID_LOW; + end + endgenerate + + + //*************************************************************************** + // Underflow may change behavior based on latency or active-low + //*************************************************************************** + generate + if (C_HAS_UNDERFLOW==1) begin : blockUF1 + assign underflow_i = (C_PRELOAD_LATENCY==0) ? (RD_EN & EMPTY) : ideal_underflow; + assign UNDERFLOW = underflow_i ? !C_UNDERFLOW_LOW : C_UNDERFLOW_LOW; + end + endgenerate + + //*************************************************************************** + // Write acknowledge may be active low + //*************************************************************************** + generate + if (C_HAS_WR_ACK==1) begin : blockWK1 + assign WR_ACK = ideal_wr_ack ? !C_WR_ACK_LOW : C_WR_ACK_LOW; + end + endgenerate + + + //*************************************************************************** + // Generate RD_DATA_COUNT if Use Extra Logic option is selected + //*************************************************************************** + generate + if (C_HAS_WR_DATA_COUNT == 1 && C_USE_FWFT_DATA_COUNT == 1) begin : wdc_fwft_ext + + reg [C_PNTR_WIDTH-1:0] adjusted_wr_pntr = 0; + reg [C_PNTR_WIDTH-1:0] adjusted_rd_pntr = 0; + wire [C_PNTR_WIDTH-1:0] diff_wr_rd_tmp; + wire [C_PNTR_WIDTH:0] diff_wr_rd; + reg [C_PNTR_WIDTH:0] wr_data_count_i = 0; + always @* begin + if (C_WR_PNTR_WIDTH > C_RD_PNTR_WIDTH) begin + adjusted_wr_pntr = wr_pntr; + adjusted_rd_pntr = 0; + adjusted_rd_pntr[C_PNTR_WIDTH-1:C_PNTR_WIDTH-C_RD_PNTR_WIDTH] = rd_pntr_wr; + end else if (C_WR_PNTR_WIDTH < C_RD_PNTR_WIDTH) begin + adjusted_rd_pntr = rd_pntr_wr; + adjusted_wr_pntr = 0; + adjusted_wr_pntr[C_PNTR_WIDTH-1:C_PNTR_WIDTH-C_WR_PNTR_WIDTH] = wr_pntr; + end else begin + adjusted_wr_pntr = wr_pntr; + adjusted_rd_pntr = rd_pntr_wr; + end + end // always @* + + assign diff_wr_rd_tmp = adjusted_wr_pntr - adjusted_rd_pntr; + assign diff_wr_rd = {1'b0,diff_wr_rd_tmp}; + + always @ (posedge wr_rst_i or posedge WR_CLK) + begin + if (wr_rst_i) + wr_data_count_i <= #`TCQ 0; + else + wr_data_count_i <= #`TCQ diff_wr_rd + EXTRA_WORDS_DC; + end // always @ (posedge WR_CLK or posedge WR_CLK) + + always @* begin + if (C_WR_PNTR_WIDTH >= C_RD_PNTR_WIDTH) + wdc_fwft_ext_as = wr_data_count_i[C_PNTR_WIDTH:0]; + else + wdc_fwft_ext_as = wr_data_count_i[C_PNTR_WIDTH:C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH]; + end // always @* + end // wdc_fwft_ext + endgenerate + + //*************************************************************************** + // Generate RD_DATA_COUNT if Use Extra Logic option is selected + //*************************************************************************** + reg [C_RD_PNTR_WIDTH:0] rdc_fwft_ext_as = 0; + + generate + if (C_HAS_RD_DATA_COUNT == 1 && C_USE_FWFT_DATA_COUNT == 1) begin : rdc_fwft_ext + reg [C_RD_PNTR_WIDTH-1:0] adjusted_wr_pntr_rd = 0; + wire [C_RD_PNTR_WIDTH-1:0] diff_rd_wr_tmp; + wire [C_RD_PNTR_WIDTH:0] diff_rd_wr; + always @* begin + if (C_RD_PNTR_WIDTH > C_WR_PNTR_WIDTH) begin + adjusted_wr_pntr_rd = 0; + adjusted_wr_pntr_rd[C_RD_PNTR_WIDTH-1:C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH] = wr_pntr_rd; + end else begin + adjusted_wr_pntr_rd = wr_pntr_rd[C_WR_PNTR_WIDTH-1:C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH]; + end + end // always @* + + assign diff_rd_wr_tmp = adjusted_wr_pntr_rd - rd_pntr; + assign diff_rd_wr = {1'b0,diff_rd_wr_tmp}; + + always @ (posedge rd_rst_i or posedge RD_CLK) + begin + if (rd_rst_i) begin + rdc_fwft_ext_as <= #`TCQ 0; + end else begin + if (!stage2_valid) + rdc_fwft_ext_as <= #`TCQ 0; + else if (!stage1_valid && stage2_valid) + rdc_fwft_ext_as <= #`TCQ 1; + else + rdc_fwft_ext_as <= #`TCQ diff_rd_wr + 2'h2; + end + end // always @ (posedge WR_CLK or posedge WR_CLK) + end // rdc_fwft_ext + endgenerate + + //*************************************************************************** + // Assign the read data count value only if it is selected, + // otherwise output zeros. + //*************************************************************************** + generate + if (C_HAS_RD_DATA_COUNT == 1) begin : grdc + assign RD_DATA_COUNT[C_RD_DATA_COUNT_WIDTH-1:0] = C_USE_FWFT_DATA_COUNT ? + rdc_fwft_ext_as[C_RD_PNTR_WIDTH:C_RD_PNTR_WIDTH+1-C_RD_DATA_COUNT_WIDTH] : + rd_data_count_int[C_RD_PNTR_WIDTH:C_RD_PNTR_WIDTH+1-C_RD_DATA_COUNT_WIDTH]; + end + endgenerate + + generate + if (C_HAS_RD_DATA_COUNT == 0) begin : gnrdc + assign RD_DATA_COUNT[C_RD_DATA_COUNT_WIDTH-1:0] = {C_RD_DATA_COUNT_WIDTH-1{1'b0}}; + end + endgenerate + + //*************************************************************************** + // Assign the write data count value only if it is selected, + // otherwise output zeros + //*************************************************************************** + generate + if (C_HAS_WR_DATA_COUNT == 1) begin : gwdc + assign WR_DATA_COUNT[C_WR_DATA_COUNT_WIDTH-1:0] = (C_USE_FWFT_DATA_COUNT == 1) ? + wdc_fwft_ext_as[C_WR_PNTR_WIDTH:C_WR_PNTR_WIDTH+1-C_WR_DATA_COUNT_WIDTH] : + wr_data_count_int[C_WR_PNTR_WIDTH:C_WR_PNTR_WIDTH+1-C_WR_DATA_COUNT_WIDTH]; + end + endgenerate + + generate + if (C_HAS_WR_DATA_COUNT == 0) begin : gnwdc + assign WR_DATA_COUNT[C_WR_DATA_COUNT_WIDTH-1:0] = {C_WR_DATA_COUNT_WIDTH-1{1'b0}}; + end + endgenerate + + /************************************************************************** + * Internal reset logic + **************************************************************************/ + assign wr_rst_i = (C_HAS_RST == 1 || C_ENABLE_RST_SYNC == 0) ? wr_rst_reg : 0; + assign rd_rst_i = (C_HAS_RST == 1 || C_ENABLE_RST_SYNC == 0) ? rd_rst_reg : 0; + + generate + if (C_ENABLE_RST_SYNC == 0) begin : gnrst_sync + always @* begin + wr_rst_reg <= WR_RST; + rd_rst_reg <= RD_RST; + end + end else if (C_HAS_RST==1) begin : blockRST2 + assign wr_rst_comb = !wr_rst_asreg_d2 && wr_rst_asreg; + assign rd_rst_comb = !rd_rst_asreg_d2 && rd_rst_asreg; + + always @(posedge WR_CLK or posedge RST) begin + if (RST == 1'b1) begin + wr_rst_asreg <= #`TCQ 1'b1; + end else begin + if (wr_rst_asreg_d1 == 1'b1) begin + wr_rst_asreg <= #`TCQ 1'b0; + end else begin + wr_rst_asreg <= #`TCQ wr_rst_asreg; + end + end + end + + always @(posedge WR_CLK) begin + wr_rst_asreg_d1 <= #`TCQ wr_rst_asreg; + wr_rst_asreg_d2 <= #`TCQ wr_rst_asreg_d1; + end + + always @(posedge WR_CLK or posedge wr_rst_comb) begin + if (wr_rst_comb == 1'b1) begin + wr_rst_reg <= #`TCQ 1'b1; + end else begin + wr_rst_reg <= #`TCQ 1'b0; + end + end + + always @(posedge RD_CLK or posedge RST) begin + if (RST == 1'b1) begin + rd_rst_asreg <= #`TCQ 1'b1; + end else begin + if (rd_rst_asreg_d1 == 1'b1) begin + rd_rst_asreg <= #`TCQ 1'b0; + end else begin + rd_rst_asreg <= #`TCQ rd_rst_asreg; + end + end + end + + always @(posedge RD_CLK) begin + rd_rst_asreg_d1 <= #`TCQ rd_rst_asreg; + rd_rst_asreg_d2 <= #`TCQ rd_rst_asreg_d1; + end + + always @(posedge RD_CLK or posedge rd_rst_comb) begin + if (rd_rst_comb == 1'b1) begin + rd_rst_reg <= #`TCQ 1'b1; + end else begin + rd_rst_reg <= #`TCQ 1'b0; + end + end + end + endgenerate + + always @(posedge WR_CLK or posedge wr_rst_i) begin + if (wr_rst_i == 1'b1) begin + wr_rst_d1 <= #`TCQ 1'b1; + end else begin + wr_rst_d1 <= #`TCQ wr_rst_i; + end + end + + /************************************************************************** + * Assorted registers for delayed versions of signals + **************************************************************************/ + //Capture delayed version of valid + generate + if (C_HAS_VALID==1) begin : blockVL2 + always @(posedge RD_CLK or posedge rd_rst_i) begin + if (rd_rst_i == 1'b1) begin + valid_d1 <= #`TCQ 1'b0; + end else begin + valid_d1 <= #`TCQ valid_i; + end + end + end + endgenerate + + //Capture delayed version of dout + always @(posedge RD_CLK or posedge rd_rst_i) begin + if (rd_rst_i == 1'b1) begin + // Reset err_type only if ECC is not selected + if (C_USE_ECC == 0) + err_type_d1 <= #`TCQ 0; + end else if (ram_rd_en_d1) begin + ideal_dout_d1 <= #`TCQ ideal_dout; + err_type_d1 <= #`TCQ err_type; + end + end + + /************************************************************************** + * Overflow and Underflow Flag calculation + * (handled separately because they don't support rst) + **************************************************************************/ + generate + if (C_HAS_OVERFLOW==1) begin : blockOF2 + always @(posedge WR_CLK) begin + ideal_overflow <= #`TCQ WR_EN & FULL; + end + end + endgenerate + + generate + if (C_HAS_UNDERFLOW==1) begin : blockUF2 + always @(posedge RD_CLK) begin + ideal_underflow <= #`TCQ EMPTY & RD_EN; + end + end + endgenerate + + /************************************************************************** + * Write Domain Logic + **************************************************************************/ + reg [C_WR_PNTR_WIDTH-1:0] diff_pntr = 0; + always @(posedge WR_CLK or posedge wr_rst_i) begin : gen_fifo_w + + /****** Reset fifo (case 1)***************************************/ + if (wr_rst_i == 1'b1) begin + num_wr_bits <= #`TCQ 0; + next_num_wr_bits = #`TCQ 0; + wr_ptr <= #`TCQ C_WR_DEPTH - 1; + rd_ptr_wrclk <= #`TCQ C_RD_DEPTH - 1; + ideal_wr_ack <= #`TCQ 0; + ideal_wr_count <= #`TCQ 0; + tmp_wr_listsize = #`TCQ 0; + rd_ptr_wrclk_next <= #`TCQ 0; + wr_pntr <= #`TCQ 0; + wr_pntr_rd1 <= #`TCQ 0; + rd_pntr_wr2 <= #`TCQ 0; + rd_pntr_wr3 <= #`TCQ 0; + rd_pntr_wr4 <= #`TCQ 0; + rd_pntr_wr <= #`TCQ 0; + + + end else begin //wr_rst_i==0 + + wr_pntr_rd1 <= #`TCQ wr_pntr; + + // Synchronize the rd_pntr in read domain + rd_pntr_wr2 <= #`TCQ rd_pntr_wr1; + rd_pntr_wr3 <= #`TCQ rd_pntr_wr2; + rd_pntr_wr4 <= #`TCQ rd_pntr_wr2; + rd_pntr_wr <= #`TCQ rd_pntr_wr4; + + + + //Determine the current number of words in the FIFO + tmp_wr_listsize = (C_DEPTH_RATIO_RD > 1) ? num_wr_bits/C_DOUT_WIDTH : + num_wr_bits/C_DIN_WIDTH; + rd_ptr_wrclk_next = rd_ptr; + if (rd_ptr_wrclk < rd_ptr_wrclk_next) begin + next_num_wr_bits = num_wr_bits - + C_DOUT_WIDTH*(rd_ptr_wrclk + C_RD_DEPTH + - rd_ptr_wrclk_next); + end else begin + next_num_wr_bits = num_wr_bits - + C_DOUT_WIDTH*(rd_ptr_wrclk - rd_ptr_wrclk_next); + end + + //If this is a write, handle the write by adding the value + // to the linked list, and updating all outputs appropriately + if (WR_EN == 1'b1) begin + if (FULL == 1'b1) begin + + //If the FIFO is full, do NOT perform the write, + // update flags accordingly + if ((tmp_wr_listsize + C_DEPTH_RATIO_RD - 1)/C_DEPTH_RATIO_RD + >= C_FIFO_WR_DEPTH) begin + //write unsuccessful - do not change contents + + //Do not acknowledge the write + ideal_wr_ack <= #`TCQ 0; + //Reminder that FIFO is still full + + ideal_wr_count <= #`TCQ num_write_words_sized_i; + + //If the FIFO is one from full, but reporting full + end else + if ((tmp_wr_listsize + C_DEPTH_RATIO_RD - 1)/C_DEPTH_RATIO_RD == + C_FIFO_WR_DEPTH-1) begin + //No change to FIFO + + //Write not successful + ideal_wr_ack <= #`TCQ 0; + //With DEPTH-1 words in the FIFO, it is almost_full + + ideal_wr_count <= #`TCQ num_write_words_sized_i; + + + //If the FIFO is completely empty, but it is + // reporting FULL for some reason (like reset) + end else + if ((tmp_wr_listsize + C_DEPTH_RATIO_RD - 1)/C_DEPTH_RATIO_RD <= + C_FIFO_WR_DEPTH-2) begin + //No change to FIFO + + //Write not successful + ideal_wr_ack <= #`TCQ 0; + //FIFO is really not close to full, so change flag status. + + ideal_wr_count <= #`TCQ num_write_words_sized_i; + end //(tmp_wr_listsize == 0) + + end else begin + + //If the FIFO is full, do NOT perform the write, + // update flags accordingly + if ((tmp_wr_listsize + C_DEPTH_RATIO_RD - 1)/C_DEPTH_RATIO_RD >= + C_FIFO_WR_DEPTH) begin + //write unsuccessful - do not change contents + + //Do not acknowledge the write + ideal_wr_ack <= #`TCQ 0; + //Reminder that FIFO is still full + + ideal_wr_count <= #`TCQ num_write_words_sized_i; + + //If the FIFO is one from full + end else + if ((tmp_wr_listsize + C_DEPTH_RATIO_RD - 1)/C_DEPTH_RATIO_RD == + C_FIFO_WR_DEPTH-1) begin + //Add value on DIN port to FIFO + write_fifo; + next_num_wr_bits = next_num_wr_bits + C_DIN_WIDTH; + + //Write successful, so issue acknowledge + // and no error + ideal_wr_ack <= #`TCQ 1; + //This write is CAUSING the FIFO to go full + + ideal_wr_count <= #`TCQ num_write_words_sized_i; + + //If the FIFO is 2 from full + end else + if ((tmp_wr_listsize + C_DEPTH_RATIO_RD - 1)/C_DEPTH_RATIO_RD == + C_FIFO_WR_DEPTH-2) begin + //Add value on DIN port to FIFO + write_fifo; + next_num_wr_bits = next_num_wr_bits + C_DIN_WIDTH; + //Write successful, so issue acknowledge + // and no error + ideal_wr_ack <= #`TCQ 1; + //Still 2 from full + + ideal_wr_count <= #`TCQ num_write_words_sized_i; + + //If the FIFO is not close to being full + end else + if ((tmp_wr_listsize + C_DEPTH_RATIO_RD - 1)/C_DEPTH_RATIO_RD < + C_FIFO_WR_DEPTH-2) begin + //Add value on DIN port to FIFO + write_fifo; + next_num_wr_bits = next_num_wr_bits + C_DIN_WIDTH; + //Write successful, so issue acknowledge + // and no error + ideal_wr_ack <= #`TCQ 1; + //Not even close to full. + + ideal_wr_count <= num_write_words_sized_i; + + end + + end + + end else begin //(WR_EN == 1'b1) + + //If user did not attempt a write, then do not + // give ack or err + ideal_wr_ack <= #`TCQ 0; + ideal_wr_count <= #`TCQ num_write_words_sized_i; + end + num_wr_bits <= #`TCQ next_num_wr_bits; + rd_ptr_wrclk <= #`TCQ rd_ptr; + + end //wr_rst_i==0 + end // write always + + + /*************************************************************************** + * Programmable FULL flags + ***************************************************************************/ + + always @(posedge WR_CLK or posedge wr_rst_i) begin : gen_pf + + if (wr_rst_i == 1'b1) begin + diff_pntr <= 0; + ideal_prog_full <= #`TCQ C_FULL_FLAGS_RST_VAL; + end else begin + if (ram_wr_en) + diff_pntr <= #`TCQ (wr_pntr - adj_rd_pntr_wr + 2'h1); + else if (!ram_wr_en) + diff_pntr <= #`TCQ (wr_pntr - adj_rd_pntr_wr); + + if (wr_rst_d1 == 1 && wr_rst_i == 0) + ideal_prog_full <= #`TCQ 0; + //Single Programmable Full Constant Threshold + else if (C_PROG_FULL_TYPE == 1) begin + if (FULL == 0) begin + if (diff_pntr >= C_PROG_FULL_THRESH_ASSERT_VAL) + ideal_prog_full <= #`TCQ 1; + else + ideal_prog_full <= #`TCQ 0; + end else + ideal_prog_full <= #`TCQ ideal_prog_full; + //Two Programmable Full Constant Thresholds + end else if (C_PROG_FULL_TYPE == 2) begin + if (FULL == 0) begin + if (diff_pntr >= C_PROG_FULL_THRESH_ASSERT_VAL) + ideal_prog_full <= #`TCQ 1; + else if (diff_pntr < C_PROG_FULL_THRESH_NEGATE_VAL) + ideal_prog_full <= #`TCQ 0; + else + ideal_prog_full <= #`TCQ ideal_prog_full; + end else + ideal_prog_full <= #`TCQ ideal_prog_full; + //Single Programmable Full Threshold Input + end else if (C_PROG_FULL_TYPE == 3) begin + if (FULL == 0) begin + if (diff_pntr >= PROG_FULL_THRESH) + ideal_prog_full <= #`TCQ 1; + else + ideal_prog_full <= #`TCQ 0; + end else + ideal_prog_full <= #`TCQ ideal_prog_full; + //Two Programmable Full Threshold Inputs + end else if (C_PROG_FULL_TYPE == 4) begin + if (FULL == 0) begin + if (diff_pntr >= PROG_FULL_THRESH_ASSERT) + ideal_prog_full <= #`TCQ 1; + else if (diff_pntr < PROG_FULL_THRESH_NEGATE) + ideal_prog_full <= #`TCQ 0; + else + ideal_prog_full <= #`TCQ ideal_prog_full; + end else + ideal_prog_full <= #`TCQ ideal_prog_full; + end // C_PROG_FULL_TYPE + + end //wr_rst_i==0 + end // + + + /************************************************************************** + * Read Domain Logic + **************************************************************************/ + + + /********************************************************* + * Programmable EMPTY flags + *********************************************************/ + //Determine the Assert and Negate thresholds for Programmable Empty + + reg [C_RD_PNTR_WIDTH-1:0] pe_thr_assert_val = 0; + reg [C_RD_PNTR_WIDTH-1:0] pe_thr_negate_val = 0; + reg [C_RD_PNTR_WIDTH-1:0] diff_pntr_rd = 0; + always @* begin + + if (C_PROG_EMPTY_TYPE == 3) begin + + // If empty input threshold is selected, then subtract 2 for FWFT to + // compensate the FWFT stage, otherwise assign the input value. + if (C_PRELOAD_REGS == 1 && C_PRELOAD_LATENCY == 0) // FWFT + pe_thr_assert_val <= PROG_EMPTY_THRESH - 2'h2; + else + pe_thr_assert_val <= PROG_EMPTY_THRESH; + + end else if (C_PROG_EMPTY_TYPE == 4) begin + + // If empty input threshold is selected, then subtract 2 for FWFT to + // compensate the FWFT stage, otherwise assign the input value. + if (C_PRELOAD_REGS == 1 && C_PRELOAD_LATENCY == 0) begin // FWFT + pe_thr_assert_val <= PROG_EMPTY_THRESH_ASSERT - 2'h2; + pe_thr_negate_val <= PROG_EMPTY_THRESH_NEGATE - 2'h2; + end else begin + pe_thr_assert_val <= PROG_EMPTY_THRESH_ASSERT; + pe_thr_negate_val <= PROG_EMPTY_THRESH_NEGATE; + end + end else begin + + if (C_PRELOAD_REGS == 1 && C_PRELOAD_LATENCY == 0) begin // FWFT + pe_thr_assert_val <= C_PROG_EMPTY_THRESH_ASSERT_VAL - 2; + pe_thr_negate_val <= C_PROG_EMPTY_THRESH_NEGATE_VAL - 2; + end else begin + pe_thr_assert_val <= C_PROG_EMPTY_THRESH_ASSERT_VAL; + pe_thr_negate_val <= C_PROG_EMPTY_THRESH_NEGATE_VAL; + end + end + end // always @* + + always @(posedge RD_CLK or posedge rd_rst_i) begin : gen_pe + + if (rd_rst_i) begin + diff_pntr_rd <= 0; + ideal_prog_empty <= 1'b1; + end else begin + if (ram_rd_en) + diff_pntr_rd <= #`TCQ (adj_wr_pntr_rd - rd_pntr) - 1'h1; + else if (!ram_rd_en) + diff_pntr_rd <= #`TCQ (adj_wr_pntr_rd - rd_pntr); + else + diff_pntr_rd <= #`TCQ diff_pntr_rd; + + if (C_PROG_EMPTY_TYPE == 1) begin + if (EMPTY == 0) begin + if (diff_pntr_rd <= pe_thr_assert_val) + ideal_prog_empty <= #`TCQ 1; + else + ideal_prog_empty <= #`TCQ 0; + end else + ideal_prog_empty <= #`TCQ ideal_prog_empty; + end else if (C_PROG_EMPTY_TYPE == 2) begin + if (EMPTY == 0) begin + if (diff_pntr_rd <= pe_thr_assert_val) + ideal_prog_empty <= #`TCQ 1; + else if (diff_pntr_rd > pe_thr_negate_val) + ideal_prog_empty <= #`TCQ 0; + else + ideal_prog_empty <= #`TCQ ideal_prog_empty; + end else + ideal_prog_empty <= #`TCQ ideal_prog_empty; + end else if (C_PROG_EMPTY_TYPE == 3) begin + if (EMPTY == 0) begin + if (diff_pntr_rd <= pe_thr_assert_val) + ideal_prog_empty <= #`TCQ 1; + else + ideal_prog_empty <= #`TCQ 0; + end else + ideal_prog_empty <= #`TCQ ideal_prog_empty; + end else if (C_PROG_EMPTY_TYPE == 4) begin + if (EMPTY == 0) begin + if (diff_pntr_rd >= pe_thr_assert_val) + ideal_prog_empty <= #`TCQ 1; + else if (diff_pntr_rd > pe_thr_negate_val) + ideal_prog_empty <= #`TCQ 0; + else + ideal_prog_empty <= #`TCQ ideal_prog_empty; + end else + ideal_prog_empty <= #`TCQ ideal_prog_empty; + end //C_PROG_EMPTY_TYPE + end + end + + // block memory has a synchronous reset + always @(posedge RD_CLK) begin : gen_fifo_blkmemdout + // make it consistent with the core. + if (rd_rst_i) begin + // Reset err_type only if ECC is not selected + if (C_USE_ECC == 0 && C_MEMORY_TYPE < 2) + err_type <= #`TCQ 0; + + // BRAM resets synchronously + if (C_USE_DOUT_RST == 1 && C_MEMORY_TYPE < 2) begin + ideal_dout <= #`TCQ dout_reset_val; + ideal_dout_d1 <= #`TCQ dout_reset_val; + end + end + end //always + + always @(posedge RD_CLK or posedge rd_rst_i) begin : gen_fifo_r + + /****** Reset fifo (case 1)***************************************/ + if (rd_rst_i) begin + num_rd_bits <= #`TCQ 0; + next_num_rd_bits = #`TCQ 0; + rd_ptr <= #`TCQ C_RD_DEPTH -1; + rd_pntr <= #`TCQ 0; + rd_pntr_wr1 <= #`TCQ 0; + wr_pntr_rd2 <= #`TCQ 0; + wr_pntr_rd3 <= #`TCQ 0; + wr_pntr_rd <= #`TCQ 0; + wr_ptr_rdclk <= #`TCQ C_WR_DEPTH -1; + + // DRAM resets asynchronously + if (C_MEMORY_TYPE == 2 && C_USE_DOUT_RST == 1) + ideal_dout <= #`TCQ dout_reset_val; + + // Reset err_type only if ECC is not selected + if (C_USE_ECC == 0) + err_type <= #`TCQ 0; + ideal_valid <= #`TCQ 1'b0; + ideal_rd_count <= #`TCQ 0; + + end else begin //rd_rst_i==0 + + rd_pntr_wr1 <= #`TCQ rd_pntr; + + // Synchronize the wr_pntr in read domain + wr_pntr_rd2 <= #`TCQ wr_pntr_rd1; + wr_pntr_rd3 <= #`TCQ wr_pntr_rd2; + wr_pntr_rd <= #`TCQ wr_pntr_rd3; + + + + //Determine the current number of words in the FIFO + tmp_rd_listsize = (C_DEPTH_RATIO_WR > 1) ? num_rd_bits/C_DIN_WIDTH : + num_rd_bits/C_DOUT_WIDTH; + wr_ptr_rdclk_next = wr_ptr; + + if (wr_ptr_rdclk < wr_ptr_rdclk_next) begin + next_num_rd_bits = num_rd_bits + + C_DIN_WIDTH*(wr_ptr_rdclk +C_WR_DEPTH + - wr_ptr_rdclk_next); + end else begin + next_num_rd_bits = num_rd_bits + + C_DIN_WIDTH*(wr_ptr_rdclk - wr_ptr_rdclk_next); + end + + /*****************************************************************/ + // Read Operation - Read Latency 1 + /*****************************************************************/ + if (C_PRELOAD_LATENCY==1 || C_PRELOAD_LATENCY==2) begin + ideal_valid <= #`TCQ 1'b0; + + if (ram_rd_en == 1'b1) begin + + if (EMPTY == 1'b1) begin + + //If the FIFO is completely empty, and is reporting empty + if (tmp_rd_listsize/C_DEPTH_RATIO_WR <= 0) + begin + //Do not change the contents of the FIFO + + //Do not acknowledge the read from empty FIFO + ideal_valid <= #`TCQ 1'b0; + //Reminder that FIFO is still empty + + ideal_rd_count <= #`TCQ num_read_words_sized_i; + end // if (tmp_rd_listsize <= 0) + + //If the FIFO is one from empty, but it is reporting empty + else if (tmp_rd_listsize/C_DEPTH_RATIO_WR == 1) + begin + //Do not change the contents of the FIFO + + //Do not acknowledge the read from empty FIFO + ideal_valid <= #`TCQ 1'b0; + //Note that FIFO is no longer empty, but is almost empty (has one word left) + + ideal_rd_count <= #`TCQ num_read_words_sized_i; + + end // if (tmp_rd_listsize == 1) + + //If the FIFO is two from empty, and is reporting empty + else if (tmp_rd_listsize/C_DEPTH_RATIO_WR == 2) + begin + //Do not change the contents of the FIFO + + //Do not acknowledge the read from empty FIFO + ideal_valid <= #`TCQ 1'b0; + //Fifo has two words, so is neither empty or almost empty + + ideal_rd_count <= #`TCQ num_read_words_sized_i; + + end // if (tmp_rd_listsize == 2) + + //If the FIFO is not close to empty, but is reporting that it is + // Treat the FIFO as empty this time, but unset EMPTY flags. + if ((tmp_rd_listsize/C_DEPTH_RATIO_WR > 2) && (tmp_rd_listsize/C_DEPTH_RATIO_WR 2) && (tmp_rd_listsize<=C_FIFO_RD_DEPTH-1)) + end // else: if(ideal_empty == 1'b1) + + else //if (ideal_empty == 1'b0) + begin + + //If the FIFO is completely full, and we are successfully reading from it + if (tmp_rd_listsize/C_DEPTH_RATIO_WR >= C_FIFO_RD_DEPTH) + begin + //Read the value from the FIFO + read_fifo; + next_num_rd_bits = next_num_rd_bits - C_DOUT_WIDTH; + + //Acknowledge the read from the FIFO, no error + ideal_valid <= #`TCQ 1'b1; + //Not close to empty + + ideal_rd_count <= #`TCQ num_read_words_sized_i; + + end // if (tmp_rd_listsize == C_FIFO_RD_DEPTH) + + //If the FIFO is not close to being empty + else if ((tmp_rd_listsize/C_DEPTH_RATIO_WR > 2) && (tmp_rd_listsize/C_DEPTH_RATIO_WR<=C_FIFO_RD_DEPTH)) + begin + //Read the value from the FIFO + read_fifo; + next_num_rd_bits = next_num_rd_bits - C_DOUT_WIDTH; + + //Acknowledge the read from the FIFO, no error + ideal_valid <= #`TCQ 1'b1; + //Not close to empty + + ideal_rd_count <= #`TCQ num_read_words_sized_i; + + end // if ((tmp_rd_listsize > 2) && (tmp_rd_listsize<=C_FIFO_RD_DEPTH-1)) + + //If the FIFO is two from empty + else if (tmp_rd_listsize/C_DEPTH_RATIO_WR == 2) + begin + //Read the value from the FIFO + read_fifo; + next_num_rd_bits = next_num_rd_bits - C_DOUT_WIDTH; + + //Acknowledge the read from the FIFO, no error + ideal_valid <= #`TCQ 1'b1; + //Fifo is not yet empty. It is going almost_empty + + ideal_rd_count <= #`TCQ num_read_words_sized_i; + + end // if (tmp_rd_listsize == 2) + + //If the FIFO is one from empty + else if ((tmp_rd_listsize/C_DEPTH_RATIO_WR == 1)) + begin + //Read the value from the FIFO + read_fifo; + next_num_rd_bits = next_num_rd_bits - C_DOUT_WIDTH; + + //Acknowledge the read from the FIFO, no error + ideal_valid <= #`TCQ 1'b1; + //Note that FIFO is GOING empty + + ideal_rd_count <= #`TCQ num_read_words_sized_i; + + end // if (tmp_rd_listsize == 1) + + + //If the FIFO is completely empty + else if (tmp_rd_listsize/C_DEPTH_RATIO_WR <= 0) + begin + //Do not change the contents of the FIFO + + //Do not acknowledge the read from empty FIFO + ideal_valid <= #`TCQ 1'b0; + + ideal_rd_count <= #`TCQ num_read_words_sized_i; + + end // if (tmp_rd_listsize <= 0) + + end // if (ideal_empty == 1'b0) + + end //(RD_EN == 1'b1) + + else //if (RD_EN == 1'b0) + begin + //If user did not attempt a read, do not give an ack or err + ideal_valid <= #`TCQ 1'b0; + + ideal_rd_count <= #`TCQ num_read_words_sized_i; + + end // else: !if(RD_EN == 1'b1) + + /*****************************************************************/ + // Read Operation - Read Latency 0 + /*****************************************************************/ + end else if (C_PRELOAD_REGS==1 && C_PRELOAD_LATENCY==0) begin + ideal_valid <= #`TCQ 1'b0; + if (ram_rd_en == 1'b1) begin + + if (EMPTY == 1'b1) begin + + //If the FIFO is completely empty, and is reporting empty + if (tmp_rd_listsize/C_DEPTH_RATIO_WR <= 0) begin + //Do not change the contents of the FIFO + + //Do not acknowledge the read from empty FIFO + ideal_valid <= #`TCQ 1'b0; + //Reminder that FIFO is still empty + + ideal_rd_count <= #`TCQ num_read_words_sized_i; + + //If the FIFO is one from empty, but it is reporting empty + end else if (tmp_rd_listsize/C_DEPTH_RATIO_WR == 1) begin + //Do not change the contents of the FIFO + + //Do not acknowledge the read from empty FIFO + ideal_valid <= #`TCQ 1'b0; + //Note that FIFO is no longer empty, but is almost empty (has one word left) + + ideal_rd_count <= #`TCQ num_read_words_sized_i; + + //If the FIFO is two from empty, and is reporting empty + end else if (tmp_rd_listsize/C_DEPTH_RATIO_WR == 2) begin + //Do not change the contents of the FIFO + + //Do not acknowledge the read from empty FIFO + ideal_valid <= #`TCQ 1'b0; + //Fifo has two words, so is neither empty or almost empty + + ideal_rd_count <= #`TCQ num_read_words_sized_i; + + //If the FIFO is not close to empty, but is reporting that it is + // Treat the FIFO as empty this time, but unset EMPTY flags. + end else if ((tmp_rd_listsize/C_DEPTH_RATIO_WR > 2) && + (tmp_rd_listsize/C_DEPTH_RATIO_WR 2) && (tmp_rd_listsize<=C_FIFO_RD_DEPTH-1)) + + end else begin + + //If the FIFO is completely full, and we are successfully reading from it + if (tmp_rd_listsize/C_DEPTH_RATIO_WR >= C_FIFO_RD_DEPTH) begin + //Read the value from the FIFO + read_fifo; + next_num_rd_bits = next_num_rd_bits - C_DOUT_WIDTH; + + //Acknowledge the read from the FIFO, no error + ideal_valid <= #`TCQ 1'b1; + //Not close to empty + + ideal_rd_count <= #`TCQ num_read_words_sized_i; + + //If the FIFO is not close to being empty + end else if ((tmp_rd_listsize/C_DEPTH_RATIO_WR > 2) && + (tmp_rd_listsize/C_DEPTH_RATIO_WR<=C_FIFO_RD_DEPTH)) begin + //Read the value from the FIFO + read_fifo; + next_num_rd_bits = next_num_rd_bits - C_DOUT_WIDTH; + + //Acknowledge the read from the FIFO, no error + ideal_valid <= #`TCQ 1'b1; + //Not close to empty + + ideal_rd_count <= #`TCQ num_read_words_sized_i; + + //If the FIFO is two from empty + end else if (tmp_rd_listsize/C_DEPTH_RATIO_WR == 2) begin + //Read the value from the FIFO + read_fifo; + next_num_rd_bits = next_num_rd_bits - C_DOUT_WIDTH; + + //Acknowledge the read from the FIFO, no error + ideal_valid <= #`TCQ 1'b1; + //Fifo is not yet empty. It is going almost_empty + + ideal_rd_count <= #`TCQ num_read_words_sized_i; + + //If the FIFO is one from empty + end else if (tmp_rd_listsize/C_DEPTH_RATIO_WR == 1) begin + //Read the value from the FIFO + read_fifo; + next_num_rd_bits = next_num_rd_bits - C_DOUT_WIDTH; + + //Acknowledge the read from the FIFO, no error + ideal_valid <= #`TCQ 1'b1; + //Note that FIFO is GOING empty + + ideal_rd_count <= #`TCQ num_read_words_sized_i; + + //If the FIFO is completely empty + end else if (tmp_rd_listsize/C_DEPTH_RATIO_WR <= 0) begin + //Do not change the contents of the FIFO + + //Do not acknowledge the read from empty FIFO + ideal_valid <= #`TCQ 1'b0; + //Reminder that FIFO is still empty + + ideal_rd_count <= #`TCQ num_read_words_sized_i; + + end // if (tmp_rd_listsize <= 0) + + end // if (ideal_empty == 1'b0) + + end else begin//(RD_EN == 1'b0) + + + //If user did not attempt a read, do not give an ack or err + ideal_valid <= #`TCQ 1'b0; + ideal_rd_count <= #`TCQ num_read_words_sized_i; + + end // else: !if(RD_EN == 1'b1) + end //if (C_PRELOAD_REGS==1 && C_PRELOAD_LATENCY==0) + + num_rd_bits <= #`TCQ next_num_rd_bits; + wr_ptr_rdclk <= #`TCQ wr_ptr; + end //rd_rst_i==0 + end //always + +endmodule // fifo_generator_v5_3_bhv_ver_as + + +/******************************************************************************* + * Declaration of top-level module + ******************************************************************************/ +module fifo_generator_v5_3_bhv_ver_ss + ( + CLK, RST, SRST, DIN, WR_EN, RD_EN, + PROG_FULL_THRESH, PROG_FULL_THRESH_ASSERT, PROG_FULL_THRESH_NEGATE, + PROG_EMPTY_THRESH, PROG_EMPTY_THRESH_ASSERT, PROG_EMPTY_THRESH_NEGATE, + INJECTSBITERR, INJECTDBITERR, DOUT, FULL, ALMOST_FULL, WR_ACK, OVERFLOW, + EMPTY, ALMOST_EMPTY, VALID, UNDERFLOW, DATA_COUNT, + PROG_FULL, PROG_EMPTY, SBITERR, DBITERR + ); + + /************************************************************************** + * Declare user parameters and their defaults + *************************************************************************/ + parameter C_DATA_COUNT_WIDTH = 2; + parameter C_DIN_WIDTH = 8; + parameter C_DOUT_RST_VAL = ""; + parameter C_DOUT_WIDTH = 8; + parameter C_FULL_FLAGS_RST_VAL = 1; + parameter C_HAS_ALMOST_EMPTY = 0; + parameter C_HAS_ALMOST_FULL = 0; + parameter C_HAS_DATA_COUNT = 0; + parameter C_HAS_OVERFLOW = 0; + parameter C_HAS_RD_DATA_COUNT = 0; + parameter C_HAS_RST = 0; + parameter C_HAS_SRST = 0; + parameter C_HAS_UNDERFLOW = 0; + parameter C_HAS_VALID = 0; + parameter C_HAS_WR_ACK = 0; + parameter C_HAS_WR_DATA_COUNT = 0; + parameter C_IMPLEMENTATION_TYPE = 0; + parameter C_MEMORY_TYPE = 1; + parameter C_OVERFLOW_LOW = 0; + parameter C_PRELOAD_LATENCY = 1; + parameter C_PRELOAD_REGS = 0; + parameter C_PROG_EMPTY_THRESH_ASSERT_VAL = 0; + parameter C_PROG_EMPTY_THRESH_NEGATE_VAL = 0; + parameter C_PROG_EMPTY_TYPE = 0; + parameter C_PROG_FULL_THRESH_ASSERT_VAL = 0; + parameter C_PROG_FULL_THRESH_NEGATE_VAL = 0; + parameter C_PROG_FULL_TYPE = 0; + parameter C_RD_DATA_COUNT_WIDTH = 2; + parameter C_RD_DEPTH = 256; + parameter C_RD_PNTR_WIDTH = 8; + parameter C_UNDERFLOW_LOW = 0; + parameter C_USE_DOUT_RST = 0; + parameter C_USE_EMBEDDED_REG = 0; + parameter C_USE_FWFT_DATA_COUNT = 0; + parameter C_VALID_LOW = 0; + parameter C_WR_ACK_LOW = 0; + parameter C_WR_DATA_COUNT_WIDTH = 2; + parameter C_WR_DEPTH = 256; + parameter C_WR_PNTR_WIDTH = 8; + parameter C_USE_ECC = 0; + parameter C_ENABLE_RST_SYNC = 1; + parameter C_ERROR_INJECTION_TYPE = 0; + + + /************************************************************************** + * Declare Input and Output Ports + *************************************************************************/ + //Inputs + input CLK; + input [C_DIN_WIDTH-1:0] DIN; + input [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH; + input [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_ASSERT; + input [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_NEGATE; + input [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH; + input [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_ASSERT; + input [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_NEGATE; + input RD_EN; + input RST; + input SRST; + input WR_EN; + input INJECTDBITERR; + input INJECTSBITERR; + + //Outputs + output ALMOST_EMPTY; + output ALMOST_FULL; + output [C_DATA_COUNT_WIDTH-1:0] DATA_COUNT; + output [C_DOUT_WIDTH-1:0] DOUT; + output EMPTY; + output FULL; + output OVERFLOW; + output PROG_EMPTY; + output PROG_FULL; + output VALID; + output UNDERFLOW; + output WR_ACK; + output SBITERR; + output DBITERR; + + /************************************************************************* + * Declare the type for each Input/Output port, and connect each I/O + * to it's associated internal signal in the behavioral model + * + * The values for the outputs are assigned in assign statements immediately + * following wire, parameter, and function declarations in this code. + *************************************************************************/ + //Inputs + wire CLK; + wire [C_DIN_WIDTH-1:0] DIN; + wire [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH; + wire [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_ASSERT; + wire [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_NEGATE; + wire [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH; + wire [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_ASSERT; + wire [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_NEGATE; + wire RD_EN; + wire RST; + wire SRST; + wire WR_EN; + wire INJECTSBITERR; + wire INJECTDBITERR; + + //Outputs + wire ALMOST_EMPTY; + wire ALMOST_FULL; + reg [C_DATA_COUNT_WIDTH-1:0] DATA_COUNT; + wire [C_DOUT_WIDTH-1:0] DOUT; + wire EMPTY; + wire FULL; + wire OVERFLOW; + wire PROG_EMPTY; + wire PROG_FULL; + wire VALID; + wire UNDERFLOW; + wire WR_ACK; + wire SBITERR; + wire DBITERR; + + + /*************************************************************************** + * Parameters used as constants + **************************************************************************/ + //When RST is present, set FULL reset value to '1'. + //If core has no RST, make sure FULL powers-on as '0'. + //The reset value assignments for FULL, ALMOST_FULL, and PROG_FULL are not + //changed for v3.2(IP2_Im). When the core has Sync Reset, C_HAS_SRST=1 and C_HAS_RST=0. + // Therefore, during SRST, all the FULL flags reset to 0. + parameter C_HAS_FAST_FIFO = 0; + parameter C_FIFO_WR_DEPTH = C_WR_DEPTH; + parameter C_FIFO_RD_DEPTH = C_RD_DEPTH; + + /************************************************************************** + * FIFO Contents Tracking and Data Count Calculations + *************************************************************************/ + // Memory which will be used to simulate a FIFO + reg [C_DIN_WIDTH-1:0] memory[C_WR_DEPTH-1:0]; + // Local parameters used to determine whether to inject ECC error or not + localparam SYMMETRIC_PORT = (C_DIN_WIDTH == C_DOUT_WIDTH) ? 1 : 0; + localparam ERR_INJECTION = (C_ERROR_INJECTION_TYPE != 0) ? 1 : 0; + localparam ENABLE_ERR_INJECTION = C_USE_ECC && SYMMETRIC_PORT && ERR_INJECTION; + // Array that holds the error injection type (single/double bit error) on + // a specific write operation, which is returned on read to corrupt the + // output data. + reg [1:0] ecc_err[C_WR_DEPTH-1:0]; + + //The amount of data stored in the FIFO at any time is given + // by num_bits. + //num_bits is calculated by from the total words in the FIFO. + reg [31:0] num_bits; + + //The write pointer - tracks write operations + // (Works opposite to core: wr_ptr is a DOWN counter) + reg [31:0] wr_ptr; + + //The write pointer - tracks read operations + // (Works opposite to core: rd_ptr is a DOWN counter) + reg [31:0] rd_ptr; + + /************************** + * Data Count + *************************/ + //Amount of data stored in the FIFO scaled to read words + wire [31:0] num_read_words = num_bits/C_DOUT_WIDTH; + //num_read_words delayed 1 clock cycle + reg [31:0] num_read_words_q; + + //Amount of data stored in the FIFO scaled to write words + wire [31:0] num_write_words = num_bits/C_DIN_WIDTH; + //num_write_words delayed 1 clock cycle + reg [31:0] num_write_words_q; + + + /************************************************************************** + * Internal Registers and wires + *************************************************************************/ + + //Temporary signals used for calculating the model's outputs. These + //are only used in the assign statements immediately following wire, + //parameter, and function declarations. + wire underflow_i; + wire valid_i; + wire valid_out; + + //Ideal FIFO signals. These are the raw output of the behavioral model, + //which behaves like an ideal FIFO. + reg [1:0] err_type = 0; + reg [1:0] err_type_d1 = 0; + reg [C_DOUT_WIDTH-1:0] ideal_dout = 0; + reg [C_DOUT_WIDTH-1:0] ideal_dout_d1 = 0; + wire [C_DOUT_WIDTH-1:0] ideal_dout_out; + wire fwft_enabled; + reg ideal_wr_ack = 0; + reg ideal_valid = 0; + reg ideal_overflow = 0; + reg ideal_underflow = 0; + reg ideal_full = 0; + reg ideal_empty = 1; + reg ideal_almost_full = 0; + reg ideal_almost_empty = 1; + reg ideal_prog_full = 0; + reg ideal_prog_empty = 1; + + //Assorted reg values for delayed versions of signals + reg valid_d1 = 0; + reg prog_full_d = 0; + reg prog_empty_d = 1; + + + //Internal reset signals + reg rst_asreg = 0; + reg rst_asreg_d1 = 0; + reg rst_asreg_d2 = 0; + reg rst_reg = 0; + reg rst_d1 = 0; + wire rst_comb; + wire rst_i; + wire srst_i; + + //Delayed version of RST + reg rst_q; + reg rst_qq; + + //user specified value for reseting the size of the fifo + reg [C_DOUT_WIDTH-1:0] dout_reset_val = 0; + + + /**************************************************************************** + * Function Declarations + ***************************************************************************/ + + /************************************************************************** + * write_fifo + * This task writes a word to the FIFO memory and updates the + * write pointer. + * FIFO size is relative to write domain. + ***************************************************************************/ + task write_fifo; + reg [1:0] corrupted_data; + begin + memory[wr_ptr] <= DIN; + // Store the type of error injection (double/single) on write + case (C_ERROR_INJECTION_TYPE) + 3: ecc_err[wr_ptr] <= {INJECTDBITERR,INJECTSBITERR}; + 2: ecc_err[wr_ptr] <= {INJECTDBITERR,1'b0}; + 1: ecc_err[wr_ptr] <= {1'b0,INJECTSBITERR}; + default: ecc_err[wr_ptr] <= 0; + endcase + if (wr_ptr == 0) begin + wr_ptr <= C_WR_DEPTH - 1; + end else begin + wr_ptr <= wr_ptr - 1; + end + end + endtask // write_fifo + + /************************************************************************** + * read_fifo + * This task reads a word from the FIFO memory and updates the read + * pointer. It's output is the ideal_dout bus. + * FIFO size is relative to write domain. + ***************************************************************************/ + task read_fifo; + reg [C_DOUT_WIDTH-1:0] tmp_dout; + reg [1:0] tmp_ecc_err; + begin + tmp_dout = memory[rd_ptr][C_DOUT_WIDTH-1:0]; + // Retreive the error injection type. Based on the error injection type + // corrupt the output data. + tmp_ecc_err = ecc_err[rd_ptr]; + if (ENABLE_ERR_INJECTION) begin + if (tmp_ecc_err[1]) begin // Corrupt the output data only for double bit error + if (C_DOUT_WIDTH == 1) + tmp_dout = tmp_dout[C_DOUT_WIDTH-1:0]; + else if (C_DOUT_WIDTH == 2) + tmp_dout = {~tmp_dout[C_DOUT_WIDTH-1],~tmp_dout[C_DOUT_WIDTH-2]}; + else + tmp_dout = {~tmp_dout[C_DOUT_WIDTH-1],~tmp_dout[C_DOUT_WIDTH-2],(tmp_dout << 2)}; + end else begin + tmp_dout = tmp_dout[C_DOUT_WIDTH-1:0]; + end + err_type <= {tmp_ecc_err[1], tmp_ecc_err[0] & !tmp_ecc_err[1]}; + end else begin + err_type <= 0; + end + ideal_dout <= tmp_dout; + + if (rd_ptr == 0) begin + rd_ptr <= C_RD_DEPTH - 1; + end else begin + rd_ptr <= rd_ptr - 1; + end + end + endtask + + /**************************************************************************** + * log2_val + * Returns the 'log2' value for the input value for the supported ratios + ***************************************************************************/ + function [31:0] log2_val; + input [31:0] binary_val; + + begin + if (binary_val == 8) begin + log2_val = 3; + end else if (binary_val == 4) begin + log2_val = 2; + end else begin + log2_val = 1; + end + end + endfunction + + /**************************************************************************** + * hexstr_conv + * Converts a string of type hex to a binary value (for C_DOUT_RST_VAL) + ***************************************************************************/ + function [C_DOUT_WIDTH-1:0] hexstr_conv; + input [(C_DOUT_WIDTH*8)-1:0] def_data; + + integer index,i,j; + reg [3:0] bin; + + begin + index = 0; + hexstr_conv = 'b0; + for( i=C_DOUT_WIDTH-1; i>=0; i=i-1 ) + begin + case (def_data[7:0]) + 8'b00000000 : + begin + bin = 4'b0000; + i = -1; + end + 8'b00110000 : bin = 4'b0000; + 8'b00110001 : bin = 4'b0001; + 8'b00110010 : bin = 4'b0010; + 8'b00110011 : bin = 4'b0011; + 8'b00110100 : bin = 4'b0100; + 8'b00110101 : bin = 4'b0101; + 8'b00110110 : bin = 4'b0110; + 8'b00110111 : bin = 4'b0111; + 8'b00111000 : bin = 4'b1000; + 8'b00111001 : bin = 4'b1001; + 8'b01000001 : bin = 4'b1010; + 8'b01000010 : bin = 4'b1011; + 8'b01000011 : bin = 4'b1100; + 8'b01000100 : bin = 4'b1101; + 8'b01000101 : bin = 4'b1110; + 8'b01000110 : bin = 4'b1111; + 8'b01100001 : bin = 4'b1010; + 8'b01100010 : bin = 4'b1011; + 8'b01100011 : bin = 4'b1100; + 8'b01100100 : bin = 4'b1101; + 8'b01100101 : bin = 4'b1110; + 8'b01100110 : bin = 4'b1111; + default : + begin + bin = 4'bx; + end + endcase + for( j=0; j<4; j=j+1) + begin + if ((index*4)+j < C_DOUT_WIDTH) + begin + hexstr_conv[(index*4)+j] = bin[j]; + end + end + index = index + 1; + def_data = def_data >> 8; + end + end + endfunction + + + /************************************************************************* + * Initialize Signals for clean power-on simulation + *************************************************************************/ + initial begin + num_bits = 0; + num_read_words_q = 0; + num_write_words_q = 0; + rd_ptr = C_RD_DEPTH -1; + wr_ptr = C_WR_DEPTH -1; + dout_reset_val = hexstr_conv(C_DOUT_RST_VAL); + ideal_dout = dout_reset_val; + err_type = 0; + ideal_wr_ack = 1'b0; + ideal_valid = 1'b0; + valid_d1 = 1'b0; + ideal_overflow = 1'b0; + ideal_underflow = 1'b0; + ideal_full = 1'b0; + ideal_empty = 1'b1; + ideal_almost_full = 1'b0; + ideal_almost_empty = 1'b1; + ideal_prog_full = 1'b0; + ideal_prog_empty = 1'b1; + prog_full_d = 1'b0; + prog_empty_d = 1'b1; + rst_q = 1'b0; + rst_qq = 1'b0; + end + + + /************************************************************************* + * Connect the module inputs and outputs to the internal signals of the + * behavioral model. + *************************************************************************/ + //Inputs + /* + wire CLK; + wire [C_DIN_WIDTH-1:0] DIN; + wire [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH; + wire [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_ASSERT; + wire [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_NEGATE; + wire [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH; + wire [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_ASSERT; + wire [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_NEGATE; + wire RD_EN; + wire RST; + wire WR_EN; + */ + + //Outputs + generate + if (C_HAS_ALMOST_EMPTY==1) begin : blockAE10 + assign ALMOST_EMPTY = ideal_almost_empty; + end + endgenerate + + generate + if (C_HAS_ALMOST_FULL==1) begin : blockAF10 + assign ALMOST_FULL = ideal_almost_full; + end + endgenerate + + //Dout may change behavior based on latency + assign fwft_enabled = (C_PRELOAD_LATENCY == 0 && C_PRELOAD_REGS == 1)? + 1: 0; + assign ideal_dout_out= ((C_USE_EMBEDDED_REG==1 && (fwft_enabled == 0)) && + (C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1))? + ideal_dout_d1: ideal_dout; + assign DOUT = ideal_dout_out; + + // Assign SBITERR and DBITERR based on latency + assign SBITERR = (C_ERROR_INJECTION_TYPE == 1 || C_ERROR_INJECTION_TYPE == 3) && + ((C_USE_EMBEDDED_REG==1 && (fwft_enabled == 0)) && + (C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1)) ? + err_type_d1[0]: err_type[0]; + assign DBITERR = (C_ERROR_INJECTION_TYPE == 2 || C_ERROR_INJECTION_TYPE == 3) && + ((C_USE_EMBEDDED_REG==1 && (fwft_enabled == 0)) && + (C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1)) ? + err_type_d1[1]: err_type[1]; + + assign EMPTY = ideal_empty; + assign FULL = ideal_full; + + //Overflow may be active-low + generate + if (C_HAS_OVERFLOW==1) begin : blockOF10 + assign OVERFLOW = ideal_overflow ? !C_OVERFLOW_LOW : C_OVERFLOW_LOW; + end + endgenerate + + assign PROG_EMPTY = ideal_prog_empty; + assign PROG_FULL = ideal_prog_full; + + //Valid may change behavior based on latency or active-low + generate + if (C_HAS_VALID==1) begin : blockVL10 + assign valid_i = (C_PRELOAD_LATENCY==0) ? (RD_EN & ~EMPTY) : ideal_valid; + assign valid_out = (C_PRELOAD_LATENCY==2 && + (C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1))? + valid_d1: valid_i; + assign VALID = valid_out ? !C_VALID_LOW : C_VALID_LOW; + end + endgenerate + + //Trim data count differently depending on set widths + generate + if ((C_HAS_DATA_COUNT == 1) && + (C_DATA_COUNT_WIDTH > C_RD_PNTR_WIDTH)) begin : blockDC1 + always @(num_read_words) + DATA_COUNT = num_read_words[C_RD_PNTR_WIDTH:0]; + end else if (C_HAS_DATA_COUNT == 1) begin : blockDC2 + always @(num_read_words) + DATA_COUNT = num_read_words[C_RD_PNTR_WIDTH-1:C_RD_PNTR_WIDTH-C_DATA_COUNT_WIDTH]; + end //if + endgenerate + + //Underflow may change behavior based on latency or active-low + generate + if (C_HAS_UNDERFLOW==1) begin : blockUF10 + assign underflow_i = ideal_underflow; + assign UNDERFLOW = underflow_i ? !C_UNDERFLOW_LOW : C_UNDERFLOW_LOW; + end + endgenerate + + + //Write acknowledge may be active low + generate + if (C_HAS_WR_ACK==1) begin : blockWK10 + assign WR_ACK = ideal_wr_ack ? !C_WR_ACK_LOW : C_WR_ACK_LOW; + end + endgenerate + + + /***************************************************************************** + * Internal reset logic + ****************************************************************************/ + assign srst_i = C_HAS_SRST ? SRST : 0; + assign rst_i = C_HAS_RST ? rst_reg : 0; + + generate + if (C_ENABLE_RST_SYNC == 0) begin : gnrst_sync + always @* rst_reg <= 1'b0; + end else if (C_HAS_RST==1) begin : blockRST3 + assign rst_comb = !rst_asreg_d2 && rst_asreg; + + always @(posedge CLK or posedge RST) begin + if (RST == 1'b1) begin + rst_asreg <= #`TCQ 1'b1; + end else begin + if (rst_asreg_d1 == 1'b1) begin + rst_asreg <= #`TCQ 1'b0; + end else begin + rst_asreg <= #`TCQ rst_asreg; + end + end + end + + always @(posedge CLK) begin + rst_asreg_d1 <= #`TCQ rst_asreg; + rst_asreg_d2 <= #`TCQ rst_asreg_d1; + end + + always @(posedge CLK or posedge rst_comb) begin + if (rst_comb == 1'b1) begin + rst_reg <= #`TCQ 1'b1; + end else begin + rst_reg <= #`TCQ 1'b0; + end + end + end + endgenerate + + /************************************************************************** + * Assorted registers for delayed versions of signals + **************************************************************************/ + //Capture delayed version of valid + generate + if (C_HAS_VALID==1) begin : blockVL20 + always @(posedge CLK or posedge rst_i) begin + if (rst_i == 1'b1) begin + valid_d1 <= #`TCQ 1'b0; + end else begin + if (srst_i) begin + valid_d1 <= #`TCQ 1'b0; + end else begin + valid_d1 <= #`TCQ valid_i; + end + end + end // always @ (posedge CLK or posedge rst_i) + end + endgenerate + + + // block memory has a synchronous reset + always @(posedge CLK) begin : gen_fifo_blkmemdout_emb + // make it consistent with the core. + if (rst_i || srst_i) begin + // BRAM resets synchronously + if (C_USE_DOUT_RST == 1 && C_MEMORY_TYPE < 2) begin + ideal_dout_d1 <= #`TCQ dout_reset_val; + end + end + end //always + + reg ram_rd_en_d1 = 1'b0; + //Capture delayed version of dout + always @(posedge CLK or posedge rst_i) begin + if (rst_i == 1'b1) begin + // Reset err_type only if ECC is not selected + if (C_USE_ECC == 0) + err_type_d1 <= #`TCQ 0; + + // DRAM and SRAM reset asynchronously + if ((C_MEMORY_TYPE == 2 || C_MEMORY_TYPE == 3) && C_USE_DOUT_RST == 1) + ideal_dout_d1 <= #`TCQ dout_reset_val; + + ram_rd_en_d1 <= #`TCQ 1'b0; + end else begin + ram_rd_en_d1 <= #`TCQ RD_EN & !EMPTY; + if (srst_i) begin + ram_rd_en_d1 <= #`TCQ 1'b0; + // Reset err_type only if ECC is not selected + if (C_USE_ECC == 0) + err_type_d1 <= #`TCQ 0; + // Reset DRAM and SRAM based FIFO, BRAM based FIFO is reset above + if ((C_MEMORY_TYPE == 2 || C_MEMORY_TYPE == 3) && C_USE_DOUT_RST == 1) + ideal_dout_d1 <= #`TCQ dout_reset_val; + end else if (ram_rd_en_d1) begin + ideal_dout_d1 <= #`TCQ ideal_dout; + err_type_d1 <= #`TCQ err_type; + end + end + end + + /************************************************************************** + * Overflow and Underflow Flag calculation + * (handled separately because they don't support rst) + **************************************************************************/ + generate + if (C_HAS_OVERFLOW==1) begin : blockOF20 + always @(posedge CLK) begin + ideal_overflow <= #`TCQ WR_EN & ideal_full; + end + end + endgenerate + + generate + if (C_HAS_UNDERFLOW==1) begin : blockUF20 + always @(posedge CLK) begin + ideal_underflow <= #`TCQ ideal_empty & RD_EN; + end + end + endgenerate + + /************************************************************************* + * Write and Read Logic + ************************************************************************/ + always @(posedge CLK or posedge rst_i) + begin : gen_wr_ack_resp + + //Register reset + rst_q <= #`TCQ rst_i; + rst_qq <= #`TCQ rst_q; + + end // block: gen_wr_ack_resp + + // block memory has a synchronous reset + always @(posedge CLK) begin : gen_fifo_blkmemdout + //Changed the latency of during async reset to '1' instead of '2' to + // make it consistent with the core. + if (rst_i || rst_q || srst_i) begin + // Reset err_type only if ECC is not selected + if (C_USE_ECC == 0 && C_MEMORY_TYPE == 1) + err_type <= #`TCQ 0; + /******Initialize Read Domain Signals*********************************/ + if (C_USE_DOUT_RST == 1 && C_MEMORY_TYPE < 2) begin + ideal_dout <= #`TCQ dout_reset_val; + end + end + end //always + + always @(posedge CLK or posedge rst_i) begin : gen_fifo + + /****** Reset fifo - Asynchronous Reset**********************************/ + //Changed the latency of during async reset to '1' instead of '2' to + // make it consistent with the core. + if (rst_i) begin //v3.2 + /******Initialize Generic FIFO constructs*****************************/ + num_bits <= #`TCQ 0; + wr_ptr <= #`TCQ C_WR_DEPTH - 1; + rd_ptr <= #`TCQ C_RD_DEPTH - 1; + num_read_words_q <= #`TCQ 0; + num_write_words_q <= #`TCQ 0; + // Reset err_type only if ECC is not selected + if (C_USE_ECC == 0 && C_MEMORY_TYPE != 1) + err_type <= #`TCQ 0; + + + /******Initialize Write Domain Signals********************************/ + ideal_wr_ack <= #`TCQ 0; + ideal_full <= #`TCQ C_FULL_FLAGS_RST_VAL; + ideal_almost_full <= #`TCQ C_FULL_FLAGS_RST_VAL; + + /******Initialize Read Domain Signals*********************************/ + // DRAM and SRAM reset asynchronously + if (C_USE_DOUT_RST == 1 && (C_MEMORY_TYPE == 2 || C_MEMORY_TYPE == 3)) begin + ideal_dout <= #`TCQ dout_reset_val; + end + ideal_valid <= #`TCQ 1'b0; + ideal_empty <= #`TCQ 1'b1; + ideal_almost_empty <= #`TCQ 1'b1; + + end else begin + if (srst_i) begin + // SRST is available only for Sync BRAM, DRAM and SRAM. + if (C_MEMORY_TYPE == 1 || C_MEMORY_TYPE == 2 || C_MEMORY_TYPE == 3) begin + /******Initialize Generic FIFO constructs***********************/ + num_bits <= #`TCQ 0; + wr_ptr <= #`TCQ C_WR_DEPTH - 1; + rd_ptr <= #`TCQ C_RD_DEPTH - 1; + num_read_words_q <= #`TCQ 0; + num_write_words_q <= #`TCQ 0; + // Reset err_type only if ECC is not selected + if (C_USE_ECC == 0) + err_type <= #`TCQ 0; + + /******Initialize Write Domain Signals**************************/ + ideal_wr_ack <= #`TCQ 0; + ideal_full <= #`TCQ 0; + ideal_almost_full <= #`TCQ 0; + + /******Initialize Read Domain Signals***************************/ + //Reset DOUT of Sync DRAM/Shift RAM. Sync BRAM DOUT was reset in the + // above always block. + if (C_USE_DOUT_RST == 1 && (C_MEMORY_TYPE == 2 || C_MEMORY_TYPE == 3)) begin + ideal_dout <= #`TCQ dout_reset_val; + end + ideal_valid <= #`TCQ 1'b0; + ideal_empty <= #`TCQ 1'b1; + ideal_almost_empty <= #`TCQ 1'b1; + end + + end else begin //normal operating conditions + /********************************************************************/ + // Synchronous FIFO Condition #1 : Writing and not reading + /********************************************************************/ + ideal_valid <= #`TCQ 1'b0; + if (WR_EN & ~RD_EN) begin + + /*********************************/ + //If the FIFO is full, do NOT perform the write, + // update flags accordingly + /*********************************/ + if (num_write_words >= C_FIFO_WR_DEPTH) begin + ideal_wr_ack <= #`TCQ 0; + + //still full + ideal_full <= #`TCQ 1'b1; + ideal_almost_full <= #`TCQ 1'b1; + + //write unsuccessful - do not change contents + + // no read attempted + ideal_valid <= #`TCQ 1'b0; + + //Not near empty + ideal_empty <= #`TCQ 1'b0; + ideal_almost_empty <= #`TCQ 1'b0; + + + /*********************************/ + //If the FIFO is reporting FULL + // (Startup condition) + /*********************************/ + end else if ((num_write_words < C_FIFO_WR_DEPTH) && (ideal_full == 1'b1)) begin + ideal_wr_ack <= #`TCQ 0; + + //still full + ideal_full <= #`TCQ 1'b0; + ideal_almost_full <= #`TCQ 1'b0; + + //write unsuccessful - do not change contents + + // no read attempted + ideal_valid <= #`TCQ 1'b0; + + //FIFO EMPTY in this state can not be determined + //ideal_empty <= 1'b0; + //ideal_almost_empty <= 1'b0; + + + /*********************************/ + //If the FIFO is one from full + /*********************************/ + end else if (num_write_words == C_FIFO_WR_DEPTH-1) begin + //good write + ideal_wr_ack <= #`TCQ 1; + + //FIFO is one from FULL and going FULL + ideal_full <= #`TCQ 1'b1; + ideal_almost_full <= #`TCQ 1'b1; + + //Add input data + write_fifo; + + // no read attempted + ideal_valid <= #`TCQ 1'b0; + + //Not near empty + ideal_empty <= #`TCQ 1'b0; + ideal_almost_empty <= #`TCQ 1'b0; + + num_bits <= num_bits + C_DIN_WIDTH; + + /*********************************/ + //If the FIFO is 2 from full + /*********************************/ + end else if (num_write_words == C_FIFO_WR_DEPTH-2) begin + //good write + ideal_wr_ack <= #`TCQ 1; + + //2 from full, and writing, so set almost_full + ideal_full <= #`TCQ 1'b0; + ideal_almost_full <= #`TCQ 1'b1; + + //Add input data + write_fifo; + + //no read attempted + ideal_valid <= #`TCQ 1'b0; + + //Not near empty + ideal_empty <= #`TCQ 1'b0; + ideal_almost_empty <= #`TCQ 1'b0; + + num_bits <= #`TCQ num_bits + C_DIN_WIDTH; + + /*********************************/ + //If the FIFO is ALMOST EMPTY + /*********************************/ + end else if (num_read_words == 1) begin + //good write + ideal_wr_ack <= #`TCQ 1; + + //Not near FULL + ideal_full <= #`TCQ 1'b0; + ideal_almost_full <= #`TCQ 1'b0; + + //Add input data + write_fifo; + + // no read attempted + ideal_valid <= #`TCQ 1'b0; + + //Leaving ALMOST_EMPTY + ideal_empty <= #`TCQ 1'b0; + ideal_almost_empty <= #`TCQ 1'b0; + + num_bits <= #`TCQ num_bits + C_DIN_WIDTH; + + /*********************************/ + //If the FIFO is EMPTY + /*********************************/ + end else if (num_read_words == 0) begin + // good write + ideal_wr_ack <= #`TCQ 1; + + //Not near FULL + ideal_full <= #`TCQ 1'b0; + ideal_almost_full <= #`TCQ 1'b0; + + //Add input data + write_fifo; + + // no read attempted + ideal_valid <= #`TCQ 1'b0; + + //Leaving EMPTY (still ALMOST_EMPTY) + ideal_empty <= #`TCQ 1'b0; + ideal_almost_empty <= #`TCQ 1'b1; + + num_bits <= #`TCQ num_bits + C_DIN_WIDTH; + + /*********************************/ + //If the FIFO is not near EMPTY or FULL + /*********************************/ + end else begin + // good write + ideal_wr_ack <= #`TCQ 1; + + //Not near FULL + ideal_full <= #`TCQ 1'b0; + ideal_almost_full <= #`TCQ 1'b0; + + //Add input data + write_fifo; + + // no read attempted + ideal_valid <= #`TCQ 1'b0; + + //Not near EMPTY + ideal_empty <= #`TCQ 1'b0; + ideal_almost_empty <= #`TCQ 1'b0; + + num_bits <= #`TCQ num_bits + C_DIN_WIDTH; + + end // average case + + + /******************************************************************/ + // Synchronous FIFO Condition #2 : Reading and not writing + /******************************************************************/ + end else if (~WR_EN & RD_EN) begin + + /*********************************/ + //If the FIFO is EMPTY + /*********************************/ + if ((num_read_words == 0) || (ideal_empty == 1'b1)) begin + //no write attemped + ideal_wr_ack <= #`TCQ 0; + + //FIFO is not near FULL + ideal_full <= #`TCQ 1'b0; + ideal_almost_full <= #`TCQ 1'b0; + + //Read will fail + ideal_valid <= #`TCQ 1'b0; + + //FIFO is still empty + ideal_empty <= #`TCQ 1'b1; + ideal_almost_empty <= #`TCQ 1'b1; + + //No read + + /*********************************/ + //If the FIFO is ALMOST EMPTY + /*********************************/ + end else if (num_read_words == 1) begin + //no write attempted + ideal_wr_ack <= #`TCQ 0; + + //FIFO is not near FULL + ideal_full <= #`TCQ 1'b0; + ideal_almost_full <= #`TCQ 1'b0; + + //Read successful + ideal_valid <= #`TCQ 1'b1; + + //This read will make FIFO go empty + ideal_empty <= #`TCQ 1'b1; + ideal_almost_empty <= #`TCQ 1'b1; + + //Get the data from the FIFO + read_fifo; + num_bits <= #`TCQ num_bits - C_DIN_WIDTH; + + + /*********************************/ + //If the FIFO is 2 from EMPTY + /*********************************/ + end else if (num_read_words == 2) begin + + //no write attempted + ideal_wr_ack <= #`TCQ 0; + + //FIFO is not near FULL + ideal_full <= #`TCQ 1'b0; + ideal_almost_full <= #`TCQ 1'b0; + + //Read successful + ideal_valid <= #`TCQ 1'b1; + + //FIFO is going ALMOST_EMPTY + ideal_empty <= #`TCQ 1'b0; + ideal_almost_empty <= #`TCQ 1'b1; + + //Get the data from the FIFO + read_fifo; + num_bits <= #`TCQ num_bits - C_DOUT_WIDTH; + + + + /*********************************/ + //If the FIFO is one from full + /*********************************/ + end else if (num_write_words == C_FIFO_WR_DEPTH-1) begin + + //no write attempted + ideal_wr_ack <= #`TCQ 0; + + //FIFO is leaving ALMOST FULL + ideal_full <= #`TCQ 1'b0; + ideal_almost_full <= #`TCQ 1'b0; + + //Read successful + ideal_valid <= #`TCQ 1'b1; + + //Not near empty + ideal_empty <= #`TCQ 1'b0; + ideal_almost_empty <= #`TCQ 1'b0; + + //Read from the FIFO + read_fifo; + num_bits <= #`TCQ num_bits - C_DOUT_WIDTH; + + + /*********************************/ + // FIFO is FULL + /*********************************/ + end else if (num_write_words >= C_FIFO_WR_DEPTH) + begin + //no write attempted + ideal_wr_ack <= #`TCQ 0; + + //FIFO is leaving FULL, but is still ALMOST_FULL + ideal_full <= #`TCQ 1'b0; + ideal_almost_full <= #`TCQ 1'b1; + + //Read successful + ideal_valid <= #`TCQ 1'b1; + + //Not near empty + ideal_empty <= #`TCQ 1'b0; + ideal_almost_empty <= #`TCQ 1'b0; + + //Read from the FIFO + read_fifo; + num_bits <= #`TCQ num_bits - C_DOUT_WIDTH; + + /*********************************/ + //If the FIFO is not near EMPTY or FULL + /*********************************/ + end else begin + //no write attemped + ideal_wr_ack <= #`TCQ 0; + + //Not near empty + ideal_full <= #`TCQ 1'b0; + ideal_almost_full <= #`TCQ 1'b0; + + //Read successful + ideal_valid <= #`TCQ 1'b1; + + //Not near empty + ideal_empty <= #`TCQ 1'b0; + ideal_almost_empty <= #`TCQ 1'b0; + + //Read from the FIFO + read_fifo; + num_bits <= #`TCQ num_bits - C_DOUT_WIDTH; + + + end // average read + + + /******************************************************************/ + // Synchronous FIFO Condition #3 : Reading and writing + /******************************************************************/ + end else if (WR_EN & RD_EN) begin + + /*********************************/ + // FIFO is FULL + /*********************************/ + if (num_write_words >= C_FIFO_WR_DEPTH) begin + + ideal_wr_ack <= #`TCQ 0; + + //Read will be successful, so FIFO will leave FULL + ideal_full <= #`TCQ 1'b0; + ideal_almost_full <= #`TCQ 1'b1; + + //Read successful + ideal_valid <= #`TCQ 1'b1; + + //Not near empty + ideal_empty <= #`TCQ 1'b0; + ideal_almost_empty <= #`TCQ 1'b0; + + //Read from the FIFO + read_fifo; + num_bits <= #`TCQ num_bits - C_DOUT_WIDTH; + + + /*********************************/ + // FIFO is reporting FULL, but it is empty + // (This is a special case, when coming out of RST + /*********************************/ + end else if ((num_write_words == 0) && (ideal_full == 1'b1)) begin + + ideal_wr_ack <= #`TCQ 0; + + //Read will be successful, so FIFO will leave FULL + ideal_full <= #`TCQ 1'b0; + ideal_almost_full <= #`TCQ 1'b0; + + //Read unsuccessful + ideal_valid <= #`TCQ 1'b0; + + //Report empty condition + ideal_empty <= #`TCQ 1'b1; + ideal_almost_empty <= #`TCQ 1'b1; + + //Do not read from empty FIFO + // Read from the FIFO + + + /*********************************/ + //If the FIFO is one from full + /*********************************/ + end else if (num_write_words == C_FIFO_WR_DEPTH-1) begin + + //Write successful + ideal_wr_ack <= #`TCQ 1; + + //FIFO will remain ALMOST_FULL + ideal_full <= #`TCQ 1'b0; + ideal_almost_full <= #`TCQ 1'b1; + + // put the data into the FIFO + write_fifo; + + //Read successful + ideal_valid <= #`TCQ 1'b1; + + //Not near empty + ideal_empty <= #`TCQ 1'b0; + ideal_almost_empty <= #`TCQ 1'b0; + + //Read from the FIFO + read_fifo; + num_bits <= #`TCQ num_bits + C_DIN_WIDTH - C_DOUT_WIDTH; + + /*********************************/ + //If the FIFO is ALMOST EMPTY + /*********************************/ + end else if (num_read_words == 1) begin + + //Write successful + ideal_wr_ack <= #`TCQ 1; + + // Not near FULL + ideal_full <= #`TCQ 1'b0; + ideal_almost_full <= #`TCQ 1'b0; + + // put the data into the FIFO + write_fifo; + + //Read successful + ideal_valid <= #`TCQ 1'b1; + + //FIFO will stay ALMOST_EMPTY + ideal_empty <= #`TCQ 1'b0; + ideal_almost_empty <= #`TCQ 1'b1; + + //Read from the FIFO + read_fifo; + num_bits <= #`TCQ num_bits + C_DIN_WIDTH - C_DOUT_WIDTH; + + + /*********************************/ + //If the FIFO is EMPTY + /*********************************/ + end else if (num_read_words == 0) begin + + //Write successful + ideal_wr_ack <= #`TCQ 1; + + // Not near FULL + ideal_full <= #`TCQ 1'b0; + ideal_almost_full <= #`TCQ 1'b0; + + // put the data into the FIFO + write_fifo; + + //Read will fail + ideal_valid <= #`TCQ 1'b0; + + //FIFO will leave EMPTY + ideal_empty <= #`TCQ 1'b0; + ideal_almost_empty <= #`TCQ 1'b1; + + // No read + num_bits <= #`TCQ num_bits + C_DIN_WIDTH; + + + /*********************************/ + //If the FIFO is not near EMPTY or FULL + /*********************************/ + end else begin + + //Write successful + ideal_wr_ack <= #`TCQ 1; + + // Not near FULL + ideal_full <= #`TCQ 1'b0; + ideal_almost_full <= #`TCQ 1'b0; + + // put the data into the FIFO + write_fifo; + + //Read successful + ideal_valid <= #`TCQ 1'b1; + + // Not near EMPTY + ideal_empty <= #`TCQ 1'b0; + ideal_almost_empty <= #`TCQ 1'b0; + + //Read from the FIFO + read_fifo; + num_bits <= #`TCQ num_bits + C_DIN_WIDTH - C_DOUT_WIDTH; + + end // average case + + /******************************************************************/ + // Synchronous FIFO Condition #4 : Not reading or writing + /******************************************************************/ + end else begin + + /*********************************/ + // FIFO is FULL + /*********************************/ + if (num_write_words >= C_FIFO_WR_DEPTH) begin + + //No write + ideal_wr_ack <= #`TCQ 0; + ideal_full <= #`TCQ 1'b1; + ideal_almost_full <= #`TCQ 1'b1; + + //No read + ideal_valid <= #`TCQ 1'b0; + ideal_empty <= #`TCQ 1'b0; + ideal_almost_empty <= #`TCQ 1'b0; + + //No change to memory + + /*********************************/ + //If the FIFO is one from full + /*********************************/ + end else if (num_write_words == C_FIFO_WR_DEPTH-1) begin + + //No write + ideal_wr_ack <= #`TCQ 0; + ideal_full <= #`TCQ 1'b0; + ideal_almost_full <= #`TCQ 1'b1; + + //No read + ideal_valid <= #`TCQ 1'b0; + ideal_empty <= #`TCQ 1'b0; + ideal_almost_empty <= #`TCQ 1'b0; + + //No change to memory + + /*********************************/ + //If the FIFO is ALMOST EMPTY + /*********************************/ + end else if (num_read_words == 1) begin + //No write + ideal_wr_ack <= #`TCQ 0; + ideal_full <= #`TCQ 1'b0; + ideal_almost_full <= #`TCQ 1'b0; + + //No read + ideal_valid <= #`TCQ 1'b0; + ideal_empty <= #`TCQ 1'b0; + ideal_almost_empty <= #`TCQ 1'b1; + + //No change to memory + + end // almost empty + + + /*********************************/ + //If the FIFO is EMPTY + /*********************************/ + else if (num_read_words == 0) + begin + //No write + ideal_wr_ack <= #`TCQ 0; + ideal_full <= #`TCQ 1'b0; + ideal_almost_full <= #`TCQ 1'b0; + + //No read + ideal_valid <= #`TCQ 1'b0; + ideal_empty <= #`TCQ 1'b1; + ideal_almost_empty <= #`TCQ 1'b1; + + //No change to memory + + /*********************************/ + //If the FIFO is not near EMPTY or FULL + /*********************************/ + end else begin + + //No write + ideal_wr_ack <= #`TCQ 0; + ideal_full <= #`TCQ 1'b0; + ideal_almost_full <= #`TCQ 1'b0; + + //No read + ideal_valid <= #`TCQ 1'b0; + ideal_empty <= #`TCQ 1'b0; + ideal_almost_empty <= #`TCQ 1'b0; + + //No change to memory + + end // average case + + end // neither reading or writing + + num_read_words_q <= #`TCQ num_read_words; + num_write_words_q <= #`TCQ num_write_words; + + end //normal operating conditions + end + + end // block: gen_fifo + + + always @(posedge CLK or posedge rst_i) begin : gen_fifo_p + + /****** Reset fifo - Async Reset****************************************/ + //The latency of de-assertion of the flags is reduced by 1 to be + // consistent with the core. + if (rst_i) begin + ideal_prog_full <= #`TCQ C_FULL_FLAGS_RST_VAL; + ideal_prog_empty <= #`TCQ 1'b1; + prog_full_d <= #`TCQ C_FULL_FLAGS_RST_VAL; + prog_empty_d <= #`TCQ 1'b1; + + end else begin + if (srst_i) begin + //SRST is available only for Sync BRAM and Sync DRAM. Not for SSHFT. + if (C_MEMORY_TYPE == 1 || C_MEMORY_TYPE == 2 || C_MEMORY_TYPE == 3) begin + ideal_prog_full <= #`TCQ 1'b0; + ideal_prog_empty <= #`TCQ 1'b1; + prog_full_d <= #`TCQ 1'b0; + prog_empty_d <= #`TCQ 1'b1; + end + end else begin + + /*************************************************************** + * Programmable FULL flags + ****************************************************************/ + //calculation for standard fifo and latency =2 + if (! (C_PRELOAD_REGS==1 && C_PRELOAD_LATENCY==0) ) begin + //Single constant threshold + if (C_PROG_FULL_TYPE == 1) begin + if ((num_write_words >= C_PROG_FULL_THRESH_ASSERT_VAL-1) + && WR_EN && !RD_EN) begin + prog_full_d <= #`TCQ 1'b1; + end else if (((num_write_words == C_PROG_FULL_THRESH_ASSERT_VAL) + && RD_EN && !WR_EN) || (rst_q && !rst_i)) begin + prog_full_d <= #`TCQ 1'b0; + end + + //Dual constant thresholds + end else if (C_PROG_FULL_TYPE == 2) begin + if ((num_write_words == C_PROG_FULL_THRESH_ASSERT_VAL-1) + && WR_EN && !RD_EN) begin + prog_full_d <= #`TCQ 1'b1; + end else if ((num_write_words == C_PROG_FULL_THRESH_NEGATE_VAL) + && RD_EN && !WR_EN) begin + prog_full_d <= #`TCQ 1'b0; + end + + //Single input threshold + end else if (C_PROG_FULL_TYPE == 3) begin + if ((num_write_words == PROG_FULL_THRESH-1) + && WR_EN && !RD_EN) begin + prog_full_d <= #`TCQ 1'b1; + end else if ((num_write_words == PROG_FULL_THRESH) + && !WR_EN && RD_EN) begin + prog_full_d <= #`TCQ 1'b0; + end else if (num_write_words >= PROG_FULL_THRESH) begin + prog_full_d <= #`TCQ 1'b1; + end else if (num_write_words < PROG_FULL_THRESH) begin + prog_full_d <= #`TCQ 1'b0; + end + + //Dual input thresholds + end else begin + if ((num_write_words == PROG_FULL_THRESH_ASSERT-1) + && WR_EN && !RD_EN) begin + prog_full_d <= #`TCQ 1'b1; + end else if ((num_write_words == PROG_FULL_THRESH_NEGATE) + && !WR_EN && RD_EN)begin + prog_full_d <= #`TCQ 1'b0; + end else if (num_write_words >= PROG_FULL_THRESH_ASSERT) begin + prog_full_d <= #`TCQ 1'b1; + end else if (num_write_words < PROG_FULL_THRESH_NEGATE) begin + prog_full_d <= #`TCQ 1'b0; + end + end + end // (~ (C_PRELOAD_REGS==1 && C_PRELOAD_LATENCY==0) ) + + + //calculation for FWFT fifo + if (C_PRELOAD_REGS==1 && C_PRELOAD_LATENCY==0) begin + if (C_PROG_FULL_TYPE == 1) begin + if ((num_write_words >= C_PROG_FULL_THRESH_ASSERT_VAL-1 - 2) + && WR_EN && !RD_EN) begin + prog_full_d <= #`TCQ 1'b1; + end else if (((num_write_words == C_PROG_FULL_THRESH_ASSERT_VAL - 2) + && RD_EN && !WR_EN) || (rst_q && !rst_i)) begin + prog_full_d <= #`TCQ 1'b0; + end + + //Dual constant thresholds + end else if (C_PROG_FULL_TYPE == 2) begin + if ((num_write_words == C_PROG_FULL_THRESH_ASSERT_VAL-1 - 2) + && WR_EN && !RD_EN) begin + prog_full_d <= #`TCQ 1'b1; + end else if ((num_write_words == C_PROG_FULL_THRESH_NEGATE_VAL - 2) + && RD_EN && !WR_EN) begin + prog_full_d <= #`TCQ 1'b0; + end + + //Single input threshold + end else if (C_PROG_FULL_TYPE == 3) begin + if ((num_write_words == PROG_FULL_THRESH-1 - 2) + && WR_EN && !RD_EN) begin + prog_full_d <= #`TCQ 1'b1; + end else if ((num_write_words == PROG_FULL_THRESH - 2) + && !WR_EN && RD_EN) begin + prog_full_d <= #`TCQ 1'b0; + end else if (num_write_words >= PROG_FULL_THRESH - 2) begin + prog_full_d <= #`TCQ 1'b1; + end else if (num_write_words < PROG_FULL_THRESH - 2) begin + prog_full_d <= #`TCQ 1'b0; + end + + //Dual input thresholds + end else begin + if ((num_write_words == PROG_FULL_THRESH_ASSERT-1 - 2) + && WR_EN && !RD_EN) begin + prog_full_d <= #`TCQ 1'b1; + end else if ((num_write_words == PROG_FULL_THRESH_NEGATE - 2) + && !WR_EN && RD_EN)begin + prog_full_d <= #`TCQ 1'b0; + end else if (num_write_words >= PROG_FULL_THRESH_ASSERT - 2) begin + prog_full_d <= #`TCQ 1'b1; + end else if (num_write_words < PROG_FULL_THRESH_NEGATE - 2) begin + prog_full_d <= #`TCQ 1'b0; + end + end + end // (C_PRELOAD_REGS==1 && C_PRELOAD_LATENCY==0) + + /***************************************************************** + * Programmable EMPTY flags + ****************************************************************/ + //calculation for standard fifo and latency = 2 + if (! (C_PRELOAD_REGS==1 && C_PRELOAD_LATENCY==0) ) begin + //Single constant threshold + if (C_PROG_EMPTY_TYPE == 1) begin + if ((num_read_words == C_PROG_EMPTY_THRESH_ASSERT_VAL+1) + && RD_EN && !WR_EN) begin + prog_empty_d <= #`TCQ 1'b1; + end else if ((num_read_words == C_PROG_EMPTY_THRESH_ASSERT_VAL) + && WR_EN && !RD_EN) begin + prog_empty_d <= #`TCQ 1'b0; + end + //Dual constant thresholds + end else if (C_PROG_EMPTY_TYPE == 2) begin + if ((num_read_words == C_PROG_EMPTY_THRESH_ASSERT_VAL+1) + && RD_EN && !WR_EN) begin + prog_empty_d <= #`TCQ 1'b1; + end else if ((num_read_words == C_PROG_EMPTY_THRESH_NEGATE_VAL) + && !RD_EN && WR_EN) begin + prog_empty_d <= #`TCQ 1'b0; + end + + //Single input threshold + end else if (C_PROG_EMPTY_TYPE == 3) begin + if ((num_read_words == PROG_EMPTY_THRESH+1) + && RD_EN && !WR_EN) begin + prog_empty_d <= #`TCQ 1'b1; + end else if ((num_read_words == PROG_EMPTY_THRESH) + && !RD_EN && WR_EN) begin + prog_empty_d <= #`TCQ 1'b0; + end else if (num_read_words <= PROG_EMPTY_THRESH) begin + prog_empty_d <= #`TCQ 1'b1; + end else if (num_read_words > PROG_EMPTY_THRESH)begin + prog_empty_d <= #`TCQ 1'b0; + end + + //Dual input thresholds + end else begin + if (num_read_words <= PROG_EMPTY_THRESH_ASSERT) begin + prog_empty_d <= #`TCQ 1'b1; + end else if ((num_read_words == PROG_EMPTY_THRESH_ASSERT+1) + && RD_EN && !WR_EN) begin + prog_empty_d <= #`TCQ 1'b1; + end else if (num_read_words > PROG_EMPTY_THRESH_NEGATE)begin + prog_empty_d <= #`TCQ 1'b0; + end else if ((num_read_words == PROG_EMPTY_THRESH_NEGATE) + && !RD_EN && WR_EN) begin + prog_empty_d <= #`TCQ 1'b0; + end + end + end // (~ (C_PRELOAD_REGS==1 && C_PRELOAD_LATENCY==0) ) + + //calculation for FWFT fifo + if (C_PRELOAD_REGS==1 && C_PRELOAD_LATENCY==0) begin + //Single constant threshold + if (C_PROG_EMPTY_TYPE == 1) begin + if ((num_read_words == C_PROG_EMPTY_THRESH_ASSERT_VAL+1 - 2) + && RD_EN && !WR_EN) begin + prog_empty_d <= #`TCQ 1'b1; + end else if ((num_read_words == C_PROG_EMPTY_THRESH_ASSERT_VAL - 2) + && WR_EN && !RD_EN) begin + prog_empty_d <= #`TCQ 1'b0; + end + //Dual constant thresholds + end else if (C_PROG_EMPTY_TYPE == 2) begin + if ((num_read_words == C_PROG_EMPTY_THRESH_ASSERT_VAL+1 - 2) + && RD_EN && !WR_EN) begin + prog_empty_d <= #`TCQ 1'b1; + end else if ((num_read_words == C_PROG_EMPTY_THRESH_NEGATE_VAL - 2) + && !RD_EN && WR_EN) begin + prog_empty_d <= #`TCQ 1'b0; + end + + //Single input threshold + end else if (C_PROG_EMPTY_TYPE == 3) begin + if ((num_read_words == PROG_EMPTY_THRESH+1 - 2) + && RD_EN && !WR_EN) begin + prog_empty_d <= #`TCQ 1'b1; + end else if ((num_read_words == PROG_EMPTY_THRESH - 2) + && !RD_EN && WR_EN) begin + prog_empty_d <= #`TCQ 1'b0; + end else if (num_read_words <= PROG_EMPTY_THRESH - 2) begin + prog_empty_d <= #`TCQ 1'b1; + end else if (num_read_words > PROG_EMPTY_THRESH - 2)begin + prog_empty_d <= #`TCQ 1'b0; + end + + //Dual input thresholds + end else begin + if (num_read_words <= PROG_EMPTY_THRESH_ASSERT - 2) begin + prog_empty_d <= #`TCQ 1'b1; + end else if ((num_read_words == PROG_EMPTY_THRESH_ASSERT+1 - 2) + && RD_EN && !WR_EN) begin + prog_empty_d <= #`TCQ 1'b1; + end else if (num_read_words > PROG_EMPTY_THRESH_NEGATE - 2)begin + prog_empty_d <= #`TCQ 1'b0; + end else if ((num_read_words == PROG_EMPTY_THRESH_NEGATE - 2) + && !RD_EN && WR_EN) begin + prog_empty_d <= #`TCQ 1'b0; + end + end + end // (~ (C_PRELOAD_REGS==1 && C_PRELOAD_LATENCY==0) ) + + ideal_prog_empty <= prog_empty_d; + if (rst_q && !rst_i) begin + ideal_prog_full <= #`TCQ 1'b0; + prog_full_d <= #`TCQ 1'b0; + end else begin + ideal_prog_full <= #`TCQ prog_full_d; + end + + end //if (srst_i) begin + end //if (rst_i) begin + end //always @(posedge CLK or posedge rst_i) begin : gen_fifo_p +endmodule // fifo_generator_v5_3_bhv_ver_ss + + + +/************************************************************************** + * First-Word Fall-Through module (preload 0) + **************************************************************************/ +module fifo_generator_v5_3_bhv_ver_preload0 + ( + RD_CLK, + RD_RST, + SRST, + RD_EN, + FIFOEMPTY, + FIFODATA, + FIFOSBITERR, + FIFODBITERR, + USERDATA, + USERVALID, + USERUNDERFLOW, + USEREMPTY, + USERALMOSTEMPTY, + RAMVALID, + FIFORDEN, + USERSBITERR, + USERDBITERR + ); + + parameter C_DOUT_RST_VAL = ""; + parameter C_DOUT_WIDTH = 8; + parameter C_HAS_RST = 0; + parameter C_ENABLE_RST_SYNC = 0; + parameter C_HAS_SRST = 0; + parameter C_USE_DOUT_RST = 0; + parameter C_USE_ECC = 0; + parameter C_USERVALID_LOW = 0; + parameter C_USERUNDERFLOW_LOW = 0; + parameter C_MEMORY_TYPE = 0; + + //Inputs + input RD_CLK; + input RD_RST; + input SRST; + input RD_EN; + input FIFOEMPTY; + input [C_DOUT_WIDTH-1:0] FIFODATA; + input FIFOSBITERR; + input FIFODBITERR; + + //Outputs + output [C_DOUT_WIDTH-1:0] USERDATA; + output USERVALID; + output USERUNDERFLOW; + output USEREMPTY; + output USERALMOSTEMPTY; + output RAMVALID; + output FIFORDEN; + output USERSBITERR; + output USERDBITERR; + + //Inputs + wire RD_CLK; + wire RD_RST; + wire RD_EN; + wire FIFOEMPTY; + wire [C_DOUT_WIDTH-1:0] FIFODATA; + wire FIFOSBITERR; + wire FIFODBITERR; + + //Outputs + reg [C_DOUT_WIDTH-1:0] USERDATA; + wire USERVALID; + wire USERUNDERFLOW; + wire USEREMPTY; + wire USERALMOSTEMPTY; + wire RAMVALID; + wire FIFORDEN; + reg USERSBITERR; + reg USERDBITERR; + + //Internal signals + wire preloadstage1; + wire preloadstage2; + reg ram_valid_i; + reg read_data_valid_i; + wire ram_regout_en; + wire ram_rd_en; + reg empty_i = 1'b1; + reg empty_q = 1'b1; + reg rd_en_q = 1'b0; + reg almost_empty_i = 1'b1; + reg almost_empty_q = 1'b1; + wire rd_rst_i; + wire srst_i; + + +/************************************************************************* +* FUNCTIONS +*************************************************************************/ + + /************************************************************************* + * hexstr_conv + * Converts a string of type hex to a binary value (for C_DOUT_RST_VAL) + ***********************************************************************/ + function [C_DOUT_WIDTH-1:0] hexstr_conv; + input [(C_DOUT_WIDTH*8)-1:0] def_data; + + integer index,i,j; + reg [3:0] bin; + + begin + index = 0; + hexstr_conv = 'b0; + for( i=C_DOUT_WIDTH-1; i>=0; i=i-1 ) + begin + case (def_data[7:0]) + 8'b00000000 : + begin + bin = 4'b0000; + i = -1; + end + 8'b00110000 : bin = 4'b0000; + 8'b00110001 : bin = 4'b0001; + 8'b00110010 : bin = 4'b0010; + 8'b00110011 : bin = 4'b0011; + 8'b00110100 : bin = 4'b0100; + 8'b00110101 : bin = 4'b0101; + 8'b00110110 : bin = 4'b0110; + 8'b00110111 : bin = 4'b0111; + 8'b00111000 : bin = 4'b1000; + 8'b00111001 : bin = 4'b1001; + 8'b01000001 : bin = 4'b1010; + 8'b01000010 : bin = 4'b1011; + 8'b01000011 : bin = 4'b1100; + 8'b01000100 : bin = 4'b1101; + 8'b01000101 : bin = 4'b1110; + 8'b01000110 : bin = 4'b1111; + 8'b01100001 : bin = 4'b1010; + 8'b01100010 : bin = 4'b1011; + 8'b01100011 : bin = 4'b1100; + 8'b01100100 : bin = 4'b1101; + 8'b01100101 : bin = 4'b1110; + 8'b01100110 : bin = 4'b1111; + default : + begin + bin = 4'bx; + end + endcase + for( j=0; j<4; j=j+1) + begin + if ((index*4)+j < C_DOUT_WIDTH) + begin + hexstr_conv[(index*4)+j] = bin[j]; + end + end + index = index + 1; + def_data = def_data >> 8; + end + end + endfunction + + + //************************************************************************* + // Set power-on states for regs + //************************************************************************* + initial begin + ram_valid_i = 1'b0; + read_data_valid_i = 1'b0; + USERDATA = hexstr_conv(C_DOUT_RST_VAL); + USERSBITERR = 1'b0; + USERDBITERR = 1'b0; + end //initial + + //*************************************************************************** + // connect up optional reset + //*************************************************************************** + assign rd_rst_i = (C_HAS_RST == 1 || C_ENABLE_RST_SYNC == 0) ? RD_RST : 0; + assign srst_i = C_HAS_SRST ? SRST : 0; + + + //*************************************************************************** + // preloadstage2 indicates that stage2 needs to be updated. This is true + // whenever read_data_valid is false, and RAM_valid is true. + //*************************************************************************** + assign preloadstage2 = ram_valid_i & (~read_data_valid_i | RD_EN); + + //*************************************************************************** + // preloadstage1 indicates that stage1 needs to be updated. This is true + // whenever the RAM has data (RAM_EMPTY is false), and either RAM_Valid is + // false (indicating that Stage1 needs updating), or preloadstage2 is active + // (indicating that Stage2 is going to update, so Stage1, therefore, must + // also be updated to keep it valid. + //*************************************************************************** + assign preloadstage1 = ((~ram_valid_i | preloadstage2) & ~FIFOEMPTY); + + //*************************************************************************** + // Calculate RAM_REGOUT_EN + // The output registers are controlled by the ram_regout_en signal. + // These registers should be updated either when the output in Stage2 is + // invalid (preloadstage2), OR when the user is reading, in which case the + // Stage2 value will go invalid unless it is replenished. + //*************************************************************************** + assign ram_regout_en = preloadstage2; + + //*************************************************************************** + // Calculate RAM_RD_EN + // RAM_RD_EN will be asserted whenever the RAM needs to be read in order to + // update the value in Stage1. + // One case when this happens is when preloadstage1=true, which indicates + // that the data in Stage1 or Stage2 is invalid, and needs to automatically + // be updated. + // The other case is when the user is reading from the FIFO, which + // guarantees that Stage1 or Stage2 will be invalid on the next clock + // cycle, unless it is replinished by data from the memory. So, as long + // as the RAM has data in it, a read of the RAM should occur. + //*************************************************************************** + assign ram_rd_en = (RD_EN & ~FIFOEMPTY) | preloadstage1; + + //*************************************************************************** + // Calculate RAMVALID_P0_OUT + // RAMVALID_P0_OUT indicates that the data in Stage1 is valid. + // + // If the RAM is being read from on this clock cycle (ram_rd_en=1), then + // RAMVALID_P0_OUT is certainly going to be true. + // If the RAM is not being read from, but the output registers are being + // updated to fill Stage2 (ram_regout_en=1), then Stage1 will be emptying, + // therefore causing RAMVALID_P0_OUT to be false. + // Otherwise, RAMVALID_P0_OUT will remain unchanged. + //*************************************************************************** + // PROCESS regout_valid + always @ (posedge RD_CLK or posedge rd_rst_i) begin + if (rd_rst_i) begin + // asynchronous reset (active high) + ram_valid_i <= #`TCQ 1'b0; + end else begin + if (srst_i) begin + // synchronous reset (active high) + ram_valid_i <= #`TCQ 1'b0; + end else begin + if (ram_rd_en == 1'b1) begin + ram_valid_i <= #`TCQ 1'b1; + end else begin + if (ram_regout_en == 1'b1) + ram_valid_i <= #`TCQ 1'b0; + else + ram_valid_i <= #`TCQ ram_valid_i; + end + end //srst_i + end //rd_rst_i + end //always + + //*************************************************************************** + // Calculate READ_DATA_VALID + // READ_DATA_VALID indicates whether the value in Stage2 is valid or not. + // Stage2 has valid data whenever Stage1 had valid data and + // ram_regout_en_i=1, such that the data in Stage1 is propogated + // into Stage2. + //*************************************************************************** + always @ (posedge RD_CLK or posedge rd_rst_i) begin + if (rd_rst_i) + read_data_valid_i <= #`TCQ 1'b0; + else if (srst_i) + read_data_valid_i <= #`TCQ 1'b0; + else + read_data_valid_i <= #`TCQ ram_valid_i | (read_data_valid_i & ~RD_EN); + end //always + + + //************************************************************************** + // Calculate EMPTY + // Defined as the inverse of READ_DATA_VALID + // + // Description: + // + // If read_data_valid_i indicates that the output is not valid, + // and there is no valid data on the output of the ram to preload it + // with, then we will report empty. + // + // If there is no valid data on the output of the ram and we are + // reading, then the FIFO will go empty. + // + //************************************************************************** + always @ (posedge RD_CLK or posedge rd_rst_i) begin + if (rd_rst_i) begin + // asynchronous reset (active high) + empty_i <= #`TCQ 1'b1; + end else begin + if (srst_i) begin + // synchronous reset (active high) + empty_i <= #`TCQ 1'b1; + end else begin + // rising clock edge + empty_i <= #`TCQ (~ram_valid_i & ~read_data_valid_i) | (~ram_valid_i & RD_EN); + end + end + end //always + + // Register RD_EN from user to calculate USERUNDERFLOW. + // Register empty_i to calculate USERUNDERFLOW. + always @ (posedge RD_CLK) begin + rd_en_q <= #`TCQ RD_EN; + empty_q <= #`TCQ empty_i; + end //always + + + //*************************************************************************** + // Calculate user_almost_empty + // user_almost_empty is defined such that, unless more words are written + // to the FIFO, the next read will cause the FIFO to go EMPTY. + // + // In most cases, whenever the output registers are updated (due to a user + // read or a preload condition), then user_almost_empty will update to + // whatever RAM_EMPTY is. + // + // The exception is when the output is valid, the user is not reading, and + // Stage1 is not empty. In this condition, Stage1 will be preloaded from the + // memory, so we need to make sure user_almost_empty deasserts properly under + // this condition. + //*************************************************************************** + always @ (posedge RD_CLK or posedge rd_rst_i) + begin + if (rd_rst_i) begin // asynchronous reset (active high) + almost_empty_i <= #`TCQ 1'b1; + almost_empty_q <= #`TCQ 1'b1; + end else begin // rising clock edge + if (srst_i) begin // synchronous reset (active high) + almost_empty_i <= #`TCQ 1'b1; + almost_empty_q <= #`TCQ 1'b1; + end else begin + if ((ram_regout_en) | (~FIFOEMPTY & read_data_valid_i & ~RD_EN)) begin + almost_empty_i <= #`TCQ FIFOEMPTY; + end + almost_empty_q <= #`TCQ empty_i; + end + end + end //always + + + assign USEREMPTY = empty_i; + assign USERALMOSTEMPTY = almost_empty_i; + assign FIFORDEN = ram_rd_en; + assign RAMVALID = ram_valid_i; + assign USERVALID = C_USERVALID_LOW ? ~read_data_valid_i : read_data_valid_i; + assign USERUNDERFLOW = C_USERUNDERFLOW_LOW ? ~(empty_q & rd_en_q) : empty_q & rd_en_q; + + // BRAM resets synchronously + always @ (posedge RD_CLK) + begin + if (rd_rst_i || srst_i) begin + if (C_USE_DOUT_RST == 1 && C_MEMORY_TYPE < 2) + USERDATA <= #`TCQ hexstr_conv(C_DOUT_RST_VAL); + end + end //always + + + always @ (posedge RD_CLK or posedge rd_rst_i) + begin + if (rd_rst_i) begin //asynchronous reset (active high) + if (C_USE_ECC == 0) begin // Reset S/DBITERR only if ECC is OFF + USERSBITERR <= #`TCQ 0; + USERDBITERR <= #`TCQ 0; + end + // DRAM resets asynchronously + if (C_USE_DOUT_RST == 1 && C_MEMORY_TYPE == 2) //asynchronous reset (active high) + USERDATA <= #`TCQ hexstr_conv(C_DOUT_RST_VAL); + end else begin // rising clock edge + if (srst_i) begin + if (C_USE_ECC == 0) begin // Reset S/DBITERR only if ECC is OFF + USERSBITERR <= #`TCQ 0; + USERDBITERR <= #`TCQ 0; + end + if (C_USE_DOUT_RST == 1 && C_MEMORY_TYPE == 2) + USERDATA <= #`TCQ hexstr_conv(C_DOUT_RST_VAL); + end else begin + if (ram_regout_en) begin + USERDATA <= #`TCQ FIFODATA; + USERSBITERR <= #`TCQ FIFOSBITERR; + USERDBITERR <= #`TCQ FIFODBITERR; + end + end + end + end //always + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/FIFO_GENERATOR_V5_3_XST.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/FIFO_GENERATOR_V5_3_XST.v new file mode 100644 index 0000000..24f7d7e --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/FIFO_GENERATOR_V5_3_XST.v @@ -0,0 +1,336 @@ +/* + ******************************************************************************* + * + * FIFO Generator - Verilog Behavioral Model + * + ******************************************************************************* + * + * (c) Copyright 1995 - 2009 Xilinx, Inc. All rights reserved. + * + * This file contains confidential and proprietary information + * of Xilinx, Inc. and is protected under U.S. and + * international copyright and other intellectual property + * laws. + * + * DISCLAIMER + * This disclaimer is not a license and does not grant any + * rights to the materials distributed herewith. Except as + * otherwise provided in a valid license issued to you by + * Xilinx, and to the maximum extent permitted by applicable + * law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND + * WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES + * AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING + * BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- + * INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and + * (2) Xilinx shall not be liable (whether in contract or tort, + * including negligence, or under any other theory of + * liability) for any loss or damage of any kind or nature + * related to, arising under or in connection with these + * materials, including for any direct, or any indirect, + * special, incidental, or consequential loss or damage + * (including loss of data, profits, goodwill, or any type of + * loss or damage suffered as a result of any action brought + * by a third party) even if such damage or loss was + * reasonably foreseeable or Xilinx had been advised of the + * possibility of the same. + * + * CRITICAL APPLICATIONS + * Xilinx products are not designed or intended to be fail- + * safe, or for use in any application requiring fail-safe + * performance, such as life-support or safety devices or + * systems, Class III medical devices, nuclear facilities, + * applications related to the deployment of airbags, or any + * other applications that could lead to death, personal + * injury, or severe property or environmental damage + * (individually and collectively, "Critical + * Applications"). Customer assumes the sole risk and + * liability of any use of Xilinx products in Critical + * Applications, subject only to applicable laws and + * regulations governing limitations on product liability. + * + * THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS + * PART OF THIS FILE AT ALL TIMES. + * + ******************************************************************************* + ******************************************************************************* + * + * Filename: fifo_generator_v5_3_bhv.v + * + * Description: + * The verilog behavioral model for the FIFO generator core. + * + ******************************************************************************* + */ + +`timescale 1ps/1ps + +/******************************************************************************* + * Declaration of top-level module + ******************************************************************************/ +module FIFO_GENERATOR_V5_3_XST + ( + BACKUP, + BACKUP_MARKER, + CLK, + RST, + SRST, + WR_CLK, + WR_RST, + RD_CLK, + RD_RST, + DIN, + WR_EN, + RD_EN, + PROG_EMPTY_THRESH, + PROG_EMPTY_THRESH_ASSERT, + PROG_EMPTY_THRESH_NEGATE, + PROG_FULL_THRESH, + PROG_FULL_THRESH_ASSERT, + PROG_FULL_THRESH_NEGATE, + INT_CLK, + INJECTDBITERR, + INJECTSBITERR, + + DOUT, + FULL, + ALMOST_FULL, + WR_ACK, + OVERFLOW, + EMPTY, + ALMOST_EMPTY, + VALID, + UNDERFLOW, + DATA_COUNT, + RD_DATA_COUNT, + WR_DATA_COUNT, + PROG_FULL, + PROG_EMPTY, + SBITERR, + DBITERR + ); + +/****************************************************************************** + * Definition of Ports + * + * + ***************************************************************************** + * Definition of Parameters + * + * + *****************************************************************************/ + +/****************************************************************************** + * Declare user parameters and their defaults + *****************************************************************************/ + parameter C_COMMON_CLOCK = 0; + parameter C_COUNT_TYPE = 0; + parameter C_DATA_COUNT_WIDTH = 2; + parameter C_DEFAULT_VALUE = ""; + parameter C_DIN_WIDTH = 8; + parameter C_DOUT_RST_VAL = ""; + parameter C_DOUT_WIDTH = 8; + parameter C_ENABLE_RLOCS = 0; + parameter C_FAMILY = "virtex2"; //Not allowed in Verilog model + parameter C_FULL_FLAGS_RST_VAL = 1; + parameter C_HAS_ALMOST_EMPTY = 0; + parameter C_HAS_ALMOST_FULL = 0; + parameter C_HAS_BACKUP = 0; + parameter C_HAS_DATA_COUNT = 0; + parameter C_HAS_INT_CLK = 0; + parameter C_HAS_MEMINIT_FILE = 0; + parameter C_HAS_OVERFLOW = 0; + parameter C_HAS_RD_DATA_COUNT = 0; + parameter C_HAS_RD_RST = 0; + parameter C_HAS_RST = 0; + parameter C_HAS_SRST = 0; + parameter C_HAS_UNDERFLOW = 0; + parameter C_HAS_VALID = 0; + parameter C_HAS_WR_ACK = 0; + parameter C_HAS_WR_DATA_COUNT = 0; + parameter C_HAS_WR_RST = 0; + parameter C_IMPLEMENTATION_TYPE = 0; + parameter C_INIT_WR_PNTR_VAL = 0; + parameter C_MEMORY_TYPE = 1; + parameter C_MIF_FILE_NAME = ""; + parameter C_OPTIMIZATION_MODE = 0; + parameter C_OVERFLOW_LOW = 0; + parameter C_PRELOAD_LATENCY = 1; + parameter C_PRELOAD_REGS = 0; + parameter C_PRIM_FIFO_TYPE = ""; + parameter C_PROG_EMPTY_THRESH_ASSERT_VAL = 0; + parameter C_PROG_EMPTY_THRESH_NEGATE_VAL = 0; + parameter C_PROG_EMPTY_TYPE = 0; + parameter C_PROG_FULL_THRESH_ASSERT_VAL = 0; + parameter C_PROG_FULL_THRESH_NEGATE_VAL = 0; + parameter C_PROG_FULL_TYPE = 0; + parameter C_RD_DATA_COUNT_WIDTH = 2; + parameter C_RD_DEPTH = 256; + parameter C_RD_FREQ = 1; + parameter C_RD_PNTR_WIDTH = 8; + parameter C_UNDERFLOW_LOW = 0; + parameter C_USE_DOUT_RST = 0; + parameter C_USE_ECC = 0; + parameter C_USE_EMBEDDED_REG = 0; + parameter C_USE_FIFO16_FLAGS = 0; + parameter C_USE_FWFT_DATA_COUNT = 0; + parameter C_VALID_LOW = 0; + parameter C_WR_ACK_LOW = 0; + parameter C_WR_DATA_COUNT_WIDTH = 2; + parameter C_WR_DEPTH = 256; + parameter C_WR_FREQ = 1; + parameter C_WR_PNTR_WIDTH = 8; + parameter C_WR_RESPONSE_LATENCY = 1; + parameter C_MSGON_VAL = 1; + parameter C_ENABLE_RST_SYNC = 1; + parameter C_ERROR_INJECTION_TYPE = 0; + + + /****************************************************************************** + * Declare Input and Output Ports + *****************************************************************************/ + input CLK; + input BACKUP; + input BACKUP_MARKER; + input [C_DIN_WIDTH-1:0] DIN; + input [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH; + input [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_ASSERT; + input [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_NEGATE; + input [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH; + input [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_ASSERT; + input [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_NEGATE; + input RD_CLK; + input RD_EN; + input RD_RST; + input RST; + input SRST; + input WR_CLK; + input WR_EN; + input WR_RST; + input INT_CLK; + input INJECTDBITERR; + input INJECTSBITERR; + + output ALMOST_EMPTY; + output ALMOST_FULL; + output [C_DATA_COUNT_WIDTH-1:0] DATA_COUNT; + output [C_DOUT_WIDTH-1:0] DOUT; + output EMPTY; + output FULL; + output OVERFLOW; + output PROG_EMPTY; + output PROG_FULL; + output VALID; + output [C_RD_DATA_COUNT_WIDTH-1:0] RD_DATA_COUNT; + output UNDERFLOW; + output WR_ACK; + output [C_WR_DATA_COUNT_WIDTH-1:0] WR_DATA_COUNT; + output SBITERR; + output DBITERR; + + FIFO_GENERATOR_V5_3 + #( + .C_COMMON_CLOCK (C_COMMON_CLOCK), + .C_COUNT_TYPE (C_COUNT_TYPE), + .C_DATA_COUNT_WIDTH (C_DATA_COUNT_WIDTH), + .C_DEFAULT_VALUE (C_DEFAULT_VALUE), + .C_DIN_WIDTH (C_DIN_WIDTH), + .C_DOUT_RST_VAL (C_DOUT_RST_VAL), + .C_DOUT_WIDTH (C_DOUT_WIDTH), + .C_ENABLE_RLOCS (C_ENABLE_RLOCS), + .C_FAMILY (C_FAMILY),//Not allowed in Verilog model + .C_FULL_FLAGS_RST_VAL (C_FULL_FLAGS_RST_VAL), + .C_HAS_ALMOST_EMPTY (C_HAS_ALMOST_EMPTY), + .C_HAS_ALMOST_FULL (C_HAS_ALMOST_FULL), + .C_HAS_BACKUP (C_HAS_BACKUP), + .C_HAS_DATA_COUNT (C_HAS_DATA_COUNT), + .C_HAS_INT_CLK (C_HAS_INT_CLK), + .C_HAS_MEMINIT_FILE (C_HAS_MEMINIT_FILE), + .C_HAS_OVERFLOW (C_HAS_OVERFLOW), + .C_HAS_RD_DATA_COUNT (C_HAS_RD_DATA_COUNT), + .C_HAS_RD_RST (C_HAS_RD_RST), + .C_HAS_RST (C_HAS_RST), + .C_HAS_SRST (C_HAS_SRST), + .C_HAS_UNDERFLOW (C_HAS_UNDERFLOW), + .C_HAS_VALID (C_HAS_VALID), + .C_HAS_WR_ACK (C_HAS_WR_ACK), + .C_HAS_WR_DATA_COUNT (C_HAS_WR_DATA_COUNT), + .C_HAS_WR_RST (C_HAS_WR_RST), + .C_IMPLEMENTATION_TYPE (C_IMPLEMENTATION_TYPE), + .C_INIT_WR_PNTR_VAL (C_INIT_WR_PNTR_VAL), + .C_MEMORY_TYPE (C_MEMORY_TYPE), + .C_MIF_FILE_NAME (C_MIF_FILE_NAME), + .C_OPTIMIZATION_MODE (C_OPTIMIZATION_MODE), + .C_OVERFLOW_LOW (C_OVERFLOW_LOW), + .C_PRELOAD_LATENCY (C_PRELOAD_LATENCY), + .C_PRELOAD_REGS (C_PRELOAD_REGS), + .C_PRIM_FIFO_TYPE (C_PRIM_FIFO_TYPE), + .C_PROG_EMPTY_THRESH_ASSERT_VAL (C_PROG_EMPTY_THRESH_ASSERT_VAL), + .C_PROG_EMPTY_THRESH_NEGATE_VAL (C_PROG_EMPTY_THRESH_NEGATE_VAL), + .C_PROG_EMPTY_TYPE (C_PROG_EMPTY_TYPE), + .C_PROG_FULL_THRESH_ASSERT_VAL (C_PROG_FULL_THRESH_ASSERT_VAL), + .C_PROG_FULL_THRESH_NEGATE_VAL (C_PROG_FULL_THRESH_NEGATE_VAL), + .C_PROG_FULL_TYPE (C_PROG_FULL_TYPE), + .C_RD_DATA_COUNT_WIDTH (C_RD_DATA_COUNT_WIDTH), + .C_RD_DEPTH (C_RD_DEPTH), + .C_RD_FREQ (C_RD_FREQ), + .C_RD_PNTR_WIDTH (C_RD_PNTR_WIDTH), + .C_UNDERFLOW_LOW (C_UNDERFLOW_LOW), + .C_USE_DOUT_RST (C_USE_DOUT_RST), + .C_USE_ECC (C_USE_ECC), + .C_USE_EMBEDDED_REG (C_USE_EMBEDDED_REG), + .C_USE_FIFO16_FLAGS (C_USE_FIFO16_FLAGS), + .C_USE_FWFT_DATA_COUNT (C_USE_FWFT_DATA_COUNT), + .C_VALID_LOW (C_VALID_LOW), + .C_WR_ACK_LOW (C_WR_ACK_LOW), + .C_WR_DATA_COUNT_WIDTH (C_WR_DATA_COUNT_WIDTH), + .C_WR_DEPTH (C_WR_DEPTH), + .C_WR_FREQ (C_WR_FREQ), + .C_WR_PNTR_WIDTH (C_WR_PNTR_WIDTH), + .C_WR_RESPONSE_LATENCY (C_WR_RESPONSE_LATENCY), + .C_MSGON_VAL (C_MSGON_VAL), + .C_ENABLE_RST_SYNC (C_ENABLE_RST_SYNC), + .C_ERROR_INJECTION_TYPE (C_ERROR_INJECTION_TYPE) + ) + fifo_generator_v5_3_dut + ( + .BACKUP (BACKUP), + .BACKUP_MARKER (BACKUP_MARKER), + .CLK (CLK), + .RST (RST), + .SRST (SRST), + .WR_CLK (WR_CLK), + .WR_RST (WR_RST), + .RD_CLK (RD_CLK), + .RD_RST (RD_RST), + .DIN (DIN), + .WR_EN (WR_EN), + .RD_EN (RD_EN), + .PROG_EMPTY_THRESH (PROG_EMPTY_THRESH), + .PROG_EMPTY_THRESH_ASSERT (PROG_EMPTY_THRESH_ASSERT), + .PROG_EMPTY_THRESH_NEGATE (PROG_EMPTY_THRESH_NEGATE), + .PROG_FULL_THRESH (PROG_FULL_THRESH), + .PROG_FULL_THRESH_ASSERT (PROG_FULL_THRESH_ASSERT), + .PROG_FULL_THRESH_NEGATE (PROG_FULL_THRESH_NEGATE), + .INT_CLK (INT_CLK), + .INJECTDBITERR (INJECTDBITERR), + .INJECTSBITERR (INJECTSBITERR), + + .DOUT (DOUT), + .FULL (FULL), + .ALMOST_FULL (ALMOST_FULL), + .WR_ACK (WR_ACK), + .OVERFLOW (OVERFLOW), + .EMPTY (EMPTY), + .ALMOST_EMPTY (ALMOST_EMPTY), + .VALID (VALID), + .UNDERFLOW (UNDERFLOW), + .DATA_COUNT (DATA_COUNT), + .RD_DATA_COUNT (RD_DATA_COUNT), + .WR_DATA_COUNT (WR_DATA_COUNT), + .PROG_FULL (PROG_FULL), + .PROG_EMPTY (PROG_EMPTY), + .SBITERR (SBITERR), + .DBITERR (DBITERR) + ); + +endmodule diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/FIFO_GENERATOR_V6_1.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/FIFO_GENERATOR_V6_1.v new file mode 100644 index 0000000..65bbac4 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/FIFO_GENERATOR_V6_1.v @@ -0,0 +1,4575 @@ +/* + ******************************************************************************* + * + * FIFO Generator - Verilog Behavioral Model + * + ******************************************************************************* + * + * (c) Copyright 1995 - 2009 Xilinx, Inc. All rights reserved. + * + * This file contains confidential and proprietary information + * of Xilinx, Inc. and is protected under U.S. and + * international copyright and other intellectual property + * laws. + * + * DISCLAIMER + * This disclaimer is not a license and does not grant any + * rights to the materials distributed herewith. Except as + * otherwise provided in a valid license issued to you by + * Xilinx, and to the maximum extent permitted by applicable + * law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND + * WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES + * AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING + * BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- + * INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and + * (2) Xilinx shall not be liable (whether in contract or tort, + * including negligence, or under any other theory of + * liability) for any loss or damage of any kind or nature + * related to, arising under or in connection with these + * materials, including for any direct, or any indirect, + * special, incidental, or consequential loss or damage + * (including loss of data, profits, goodwill, or any type of + * loss or damage suffered as a result of any action brought + * by a third party) even if such damage or loss was + * reasonably foreseeable or Xilinx had been advised of the + * possibility of the same. + * + * CRITICAL APPLICATIONS + * Xilinx products are not designed or intended to be fail- + * safe, or for use in any application requiring fail-safe + * performance, such as life-support or safety devices or + * systems, Class III medical devices, nuclear facilities, + * applications related to the deployment of airbags, or any + * other applications that could lead to death, personal + * injury, or severe property or environmental damage + * (individually and collectively, "Critical + * Applications"). Customer assumes the sole risk and + * liability of any use of Xilinx products in Critical + * Applications, subject only to applicable laws and + * regulations governing limitations on product liability. + * + * THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS + * PART OF THIS FILE AT ALL TIMES. + * + ******************************************************************************* + ******************************************************************************* + * + * Filename: FIFO_GENERATOR_V6_1.v + * + * Author : Xilinx + * + ******************************************************************************* + * Structure: + * + * fifo_generator_v6_1.vhd + * | + * +-fifo_generator_v6_1_bhv_ver_as + * | + * +-fifo_generator_v6_1_bhv_ver_ss + * | + * +-fifo_generator_v6_1_bhv_ver_preload0 + * + ******************************************************************************* + * Description: + * + * The Verilog behavioral model for the FIFO Generator. + * + * The behavioral model has three parts: + * - The behavioral model for independent clocks FIFOs (_as) + * - The behavioral model for common clock FIFOs (_ss) + * - The "preload logic" block which implements First-word Fall-through + * + ******************************************************************************* + * Description: + * The verilog behavioral model for the FIFO generator core. + * + ******************************************************************************* + */ + +`timescale 1ps/1ps +`ifndef TCQ + `define TCQ 100 +`endif + + +/******************************************************************************* + * Declaration of top-level module + ******************************************************************************/ +module FIFO_GENERATOR_V6_1 + #( + parameter C_COMMON_CLOCK = 0, + parameter C_COUNT_TYPE = 0, + parameter C_DATA_COUNT_WIDTH = 2, + parameter C_DEFAULT_VALUE = "", + parameter C_DIN_WIDTH = 8, + parameter C_DOUT_RST_VAL = "", + parameter C_DOUT_WIDTH = 8, + parameter C_ENABLE_RLOCS = 0, + parameter C_FAMILY = "virtex6", //Not allowed in Verilog model + parameter C_FULL_FLAGS_RST_VAL = 1, + parameter C_HAS_ALMOST_EMPTY = 0, + parameter C_HAS_ALMOST_FULL = 0, + parameter C_HAS_BACKUP = 0, + parameter C_HAS_DATA_COUNT = 0, + parameter C_HAS_INT_CLK = 0, + parameter C_HAS_MEMINIT_FILE = 0, + parameter C_HAS_OVERFLOW = 0, + parameter C_HAS_RD_DATA_COUNT = 0, + parameter C_HAS_RD_RST = 0, + parameter C_HAS_RST = 0, + parameter C_HAS_SRST = 0, + parameter C_HAS_UNDERFLOW = 0, + parameter C_HAS_VALID = 0, + parameter C_HAS_WR_ACK = 0, + parameter C_HAS_WR_DATA_COUNT = 0, + parameter C_HAS_WR_RST = 0, + parameter C_IMPLEMENTATION_TYPE = 0, + parameter C_INIT_WR_PNTR_VAL = 0, + parameter C_MEMORY_TYPE = 1, + parameter C_MIF_FILE_NAME = "", + parameter C_OPTIMIZATION_MODE = 0, + parameter C_OVERFLOW_LOW = 0, + parameter C_PRELOAD_LATENCY = 1, + parameter C_PRELOAD_REGS = 0, + parameter C_PRIM_FIFO_TYPE = "", + parameter C_PROG_EMPTY_THRESH_ASSERT_VAL = 0, + parameter C_PROG_EMPTY_THRESH_NEGATE_VAL = 0, + parameter C_PROG_EMPTY_TYPE = 0, + parameter C_PROG_FULL_THRESH_ASSERT_VAL = 0, + parameter C_PROG_FULL_THRESH_NEGATE_VAL = 0, + parameter C_PROG_FULL_TYPE = 0, + parameter C_RD_DATA_COUNT_WIDTH = 2, + parameter C_RD_DEPTH = 256, + parameter C_RD_FREQ = 1, + parameter C_RD_PNTR_WIDTH = 8, + parameter C_UNDERFLOW_LOW = 0, + parameter C_USE_DOUT_RST = 0, + parameter C_USE_ECC = 0, + parameter C_USE_EMBEDDED_REG = 0, + parameter C_USE_FIFO16_FLAGS = 0, + parameter C_USE_FWFT_DATA_COUNT = 0, + parameter C_VALID_LOW = 0, + parameter C_WR_ACK_LOW = 0, + parameter C_WR_DATA_COUNT_WIDTH = 2, + parameter C_WR_DEPTH = 256, + parameter C_WR_FREQ = 1, + parameter C_WR_PNTR_WIDTH = 8, + parameter C_WR_RESPONSE_LATENCY = 1, + parameter C_MSGON_VAL = 1, + parameter C_ENABLE_RST_SYNC = 1, + parameter C_ERROR_INJECTION_TYPE = 0 + ) + + ( + input BACKUP, + input BACKUP_MARKER, + input CLK, + input RST, + input SRST, + input WR_CLK, + input WR_RST, + input RD_CLK, + input RD_RST, + input [C_DIN_WIDTH-1:0] DIN, + input WR_EN, + input RD_EN, + input [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH, + input [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_ASSERT, + input [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_NEGATE, + input [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH, + input [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_ASSERT, + input [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_NEGATE, + input INT_CLK, + input INJECTDBITERR, + input INJECTSBITERR, + + output [C_DOUT_WIDTH-1:0] DOUT, + output FULL, + output ALMOST_FULL, + output WR_ACK, + output OVERFLOW, + output EMPTY, + output ALMOST_EMPTY, + output VALID, + output UNDERFLOW, + output [C_DATA_COUNT_WIDTH-1:0] DATA_COUNT, + output [C_RD_DATA_COUNT_WIDTH-1:0] RD_DATA_COUNT, + output [C_WR_DATA_COUNT_WIDTH-1:0] WR_DATA_COUNT, + output PROG_FULL, + output PROG_EMPTY, + output SBITERR, + output DBITERR + ); + +/* + ****************************************************************************** + * Definition of Parameters + ****************************************************************************** + * C_COMMON_CLOCK : Common Clock (1), Independent Clocks (0) + * C_COUNT_TYPE : *not used + * C_DATA_COUNT_WIDTH : Width of DATA_COUNT bus + * C_DEFAULT_VALUE : *not used + * C_DIN_WIDTH : Width of DIN bus + * C_DOUT_RST_VAL : Reset value of DOUT + * C_DOUT_WIDTH : Width of DOUT bus + * C_ENABLE_RLOCS : *not used + * C_FAMILY : not used in bhv model + * C_FULL_FLAGS_RST_VAL : Full flags rst val (0 or 1) + * C_HAS_ALMOST_EMPTY : 1=Core has ALMOST_EMPTY flag + * C_HAS_ALMOST_FULL : 1=Core has ALMOST_FULL flag + * C_HAS_BACKUP : *not used + * C_HAS_DATA_COUNT : 1=Core has DATA_COUNT bus + * C_HAS_INT_CLK : not used in bhv model + * C_HAS_MEMINIT_FILE : *not used + * C_HAS_OVERFLOW : 1=Core has OVERFLOW flag + * C_HAS_RD_DATA_COUNT : 1=Core has RD_DATA_COUNT bus + * C_HAS_RD_RST : *not used + * C_HAS_RST : 1=Core has Async Rst + * C_HAS_SRST : 1=Core has Sync Rst + * C_HAS_UNDERFLOW : 1=Core has UNDERFLOW flag + * C_HAS_VALID : 1=Core has VALID flag + * C_HAS_WR_ACK : 1=Core has WR_ACK flag + * C_HAS_WR_DATA_COUNT : 1=Core has WR_DATA_COUNT bus + * C_HAS_WR_RST : *not used + * C_IMPLEMENTATION_TYPE : 0=Common-Clock Bram/Dram + * 1=Common-Clock ShiftRam + * 2=Indep. Clocks Bram/Dram + * 3=Virtex-4 Built-in + * 4=Virtex-5 Built-in + * C_INIT_WR_PNTR_VAL : *not used + * C_MEMORY_TYPE : 1=Block RAM + * 2=Distributed RAM + * 3=Shift RAM + * 4=Built-in FIFO + * C_MIF_FILE_NAME : *not used + * C_OPTIMIZATION_MODE : *not used + * C_OVERFLOW_LOW : 1=OVERFLOW active low + * C_PRELOAD_LATENCY : Latency of read: 0, 1, 2 + * C_PRELOAD_REGS : 1=Use output registers + * C_PRIM_FIFO_TYPE : not used in bhv model + * C_PROG_EMPTY_THRESH_ASSERT_VAL: PROG_EMPTY assert threshold + * C_PROG_EMPTY_THRESH_NEGATE_VAL: PROG_EMPTY negate threshold + * C_PROG_EMPTY_TYPE : 0=No programmable empty + * 1=Single prog empty thresh constant + * 2=Multiple prog empty thresh constants + * 3=Single prog empty thresh input + * 4=Multiple prog empty thresh inputs + * C_PROG_FULL_THRESH_ASSERT_VAL : PROG_FULL assert threshold + * C_PROG_FULL_THRESH_NEGATE_VAL : PROG_FULL negate threshold + * C_PROG_FULL_TYPE : 0=No prog full + * 1=Single prog full thresh constant + * 2=Multiple prog full thresh constants + * 3=Single prog full thresh input + * 4=Multiple prog full thresh inputs + * C_RD_DATA_COUNT_WIDTH : Width of RD_DATA_COUNT bus + * C_RD_DEPTH : Depth of read interface (2^N) + * C_RD_FREQ : not used in bhv model + * C_RD_PNTR_WIDTH : always log2(C_RD_DEPTH) + * C_UNDERFLOW_LOW : 1=UNDERFLOW active low + * C_USE_DOUT_RST : 1=Resets DOUT on RST + * C_USE_ECC : Used for error injection purpose + * C_USE_EMBEDDED_REG : 1=Use BRAM embedded output register + * C_USE_FIFO16_FLAGS : not used in bhv model + * C_USE_FWFT_DATA_COUNT : 1=Use extra logic for FWFT data count + * C_VALID_LOW : 1=VALID active low + * C_WR_ACK_LOW : 1=WR_ACK active low + * C_WR_DATA_COUNT_WIDTH : Width of WR_DATA_COUNT bus + * C_WR_DEPTH : Depth of write interface (2^N) + * C_WR_FREQ : not used in bhv model + * C_WR_PNTR_WIDTH : always log2(C_WR_DEPTH) + * C_WR_RESPONSE_LATENCY : *not used + * C_MSGON_VAL : *not used by bhv model + * C_ENABLE_RST_SYNC : 0 = Use WR_RST & RD_RST + * 1 = Use RST + * C_ERROR_INJECTION_TYPE : 0 = No error injection + * 1 = Single bit error injection only + * 2 = Double bit error injection only + * 3 = Single and double bit error injection + ****************************************************************************** + * Definition of Ports + ****************************************************************************** + * BACKUP : Not used + * BACKUP_MARKER: Not used + * CLK : Clock + * DIN : Input data bus + * PROG_EMPTY_THRESH : Threshold for Programmable Empty Flag + * PROG_EMPTY_THRESH_ASSERT: Threshold for Programmable Empty Flag + * PROG_EMPTY_THRESH_NEGATE: Threshold for Programmable Empty Flag + * PROG_FULL_THRESH : Threshold for Programmable Full Flag + * PROG_FULL_THRESH_ASSERT : Threshold for Programmable Full Flag + * PROG_FULL_THRESH_NEGATE : Threshold for Programmable Full Flag + * RD_CLK : Read Domain Clock + * RD_EN : Read enable + * RD_RST : Read Reset + * RST : Asynchronous Reset + * SRST : Synchronous Reset + * WR_CLK : Write Domain Clock + * WR_EN : Write enable + * WR_RST : Write Reset + * INT_CLK : Internal Clock + * INJECTSBITERR: Inject Signle bit error + * INJECTDBITERR: Inject Double bit error + * ALMOST_EMPTY : One word remaining in FIFO + * ALMOST_FULL : One empty space remaining in FIFO + * DATA_COUNT : Number of data words in fifo( synchronous to CLK) + * DOUT : Output data bus + * EMPTY : Empty flag + * FULL : Full flag + * OVERFLOW : Last write rejected + * PROG_EMPTY : Programmable Empty Flag + * PROG_FULL : Programmable Full Flag + * RD_DATA_COUNT: Number of data words in fifo (synchronous to RD_CLK) + * UNDERFLOW : Last read rejected + * VALID : Last read acknowledged, DOUT bus VALID + * WR_ACK : Last write acknowledged + * WR_DATA_COUNT: Number of data words in fifo (synchronous to WR_CLK) + * SBITERR : Single Bit ECC Error Detected + * DBITERR : Double Bit ECC Error Detected + ****************************************************************************** + */ + + + /***************************************************************************** + * Derived parameters + ****************************************************************************/ + //There are 2 Verilog behavioral models + // 0 = Common-Clock FIFO/ShiftRam FIFO + // 1 = Independent Clocks FIFO + parameter C_VERILOG_IMPL = (C_IMPLEMENTATION_TYPE == 2) ? 1 : 0; + + //Internal reset signals + reg rd_rst_asreg = 0; + reg rd_rst_asreg_d1 = 0; + reg rd_rst_asreg_d2 = 0; + reg rd_rst_reg = 0; + wire rd_rst_comb; + reg rd_rst_d1 = 0; + reg wr_rst_asreg = 0; + reg wr_rst_asreg_d1 = 0; + reg wr_rst_asreg_d2 = 0; + reg wr_rst_reg = 0; + wire wr_rst_comb; + wire wr_rst_i; + wire rd_rst_i; + wire rst_i; + + //Internal reset signals + reg rst_asreg = 0; + reg rst_asreg_d1 = 0; + reg rst_asreg_d2 = 0; + reg rst_reg = 0; + wire rst_comb; + wire rst_full_gen_i; + wire rst_full_ff_i; + + wire RD_CLK_P0_IN; + wire RST_P0_IN; + wire RD_EN_FIFO_IN; + wire RD_EN_P0_IN; + + wire ALMOST_EMPTY_FIFO_OUT; + wire ALMOST_FULL_FIFO_OUT; + wire [C_DATA_COUNT_WIDTH-1:0] DATA_COUNT_FIFO_OUT; + wire [C_DOUT_WIDTH-1:0] DOUT_FIFO_OUT; + wire EMPTY_FIFO_OUT; + wire FULL_FIFO_OUT; + wire OVERFLOW_FIFO_OUT; + wire PROG_EMPTY_FIFO_OUT; + wire PROG_FULL_FIFO_OUT; + wire VALID_FIFO_OUT; + wire [C_RD_DATA_COUNT_WIDTH-1:0] RD_DATA_COUNT_FIFO_OUT; + wire UNDERFLOW_FIFO_OUT; + wire WR_ACK_FIFO_OUT; + wire [C_WR_DATA_COUNT_WIDTH-1:0] WR_DATA_COUNT_FIFO_OUT; + + + //*************************************************************************** + // Internal Signals + // The core uses either the internal_ wires or the preload0_ wires depending + // on whether the core uses Preload0 or not. + // When using preload0, the internal signals connect the internal core to + // the preload logic, and the external core's interfaces are tied to the + // preload0 signals from the preload logic. + //*************************************************************************** + wire [C_DOUT_WIDTH-1:0] DATA_P0_OUT; + wire VALID_P0_OUT; + wire EMPTY_P0_OUT; + wire ALMOSTEMPTY_P0_OUT; + reg EMPTY_P0_OUT_Q; + reg ALMOSTEMPTY_P0_OUT_Q; + wire UNDERFLOW_P0_OUT; + wire RDEN_P0_OUT; + wire [C_DOUT_WIDTH-1:0] DATA_P0_IN; + wire EMPTY_P0_IN; + reg [31:0] DATA_COUNT_FWFT; + reg SS_FWFT_WR ; + reg SS_FWFT_RD ; + + wire sbiterr_fifo_out; + wire dbiterr_fifo_out; + + // Assign 0 if not selected to avoid 'X' propogation to S/DBITERR. + assign inject_sbit_err = ((C_ERROR_INJECTION_TYPE == 1) || (C_ERROR_INJECTION_TYPE == 3)) ? + INJECTSBITERR : 0; + assign inject_dbit_err = ((C_ERROR_INJECTION_TYPE == 2) || (C_ERROR_INJECTION_TYPE == 3)) ? + INJECTDBITERR : 0; + + +// Choose the behavioral model to instantiate based on the C_VERILOG_IMPL +// parameter (1=Independent Clocks, 0=Common Clock) + + localparam FULL_FLAGS_RST_VAL = (C_HAS_SRST == 1) ? 0 : C_FULL_FLAGS_RST_VAL; +generate +case (C_VERILOG_IMPL) +0 : begin : block1 + //Common Clock Behavioral Model + fifo_generator_v6_1_bhv_ver_ss + #( + C_DATA_COUNT_WIDTH, + C_DIN_WIDTH, + C_DOUT_RST_VAL, + C_DOUT_WIDTH, +// C_FULL_FLAGS_RST_VAL, + FULL_FLAGS_RST_VAL, + C_HAS_ALMOST_EMPTY, + C_HAS_ALMOST_FULL, + C_HAS_DATA_COUNT, + C_HAS_OVERFLOW, + C_HAS_RD_DATA_COUNT, + C_HAS_RST, + C_HAS_SRST, + C_HAS_UNDERFLOW, + C_HAS_VALID, + C_HAS_WR_ACK, + C_HAS_WR_DATA_COUNT, + C_IMPLEMENTATION_TYPE, + C_MEMORY_TYPE, + C_OVERFLOW_LOW, + C_PRELOAD_LATENCY, + C_PRELOAD_REGS, + C_PROG_EMPTY_THRESH_ASSERT_VAL, + C_PROG_EMPTY_THRESH_NEGATE_VAL, + C_PROG_EMPTY_TYPE, + C_PROG_FULL_THRESH_ASSERT_VAL, + C_PROG_FULL_THRESH_NEGATE_VAL, + C_PROG_FULL_TYPE, + C_RD_DATA_COUNT_WIDTH, + C_RD_DEPTH, + C_RD_PNTR_WIDTH, + C_UNDERFLOW_LOW, + C_USE_DOUT_RST, + C_USE_EMBEDDED_REG, + C_USE_FWFT_DATA_COUNT, + C_VALID_LOW, + C_WR_ACK_LOW, + C_WR_DATA_COUNT_WIDTH, + C_WR_DEPTH, + C_WR_PNTR_WIDTH, + C_USE_ECC, + C_ENABLE_RST_SYNC, + C_ERROR_INJECTION_TYPE + ) + gen_ss + ( + .CLK (CLK), + .RST (rst_i), + .SRST (SRST), + .RST_FULL_GEN (rst_full_gen_i), + .RST_FULL_FF (rst_full_ff_i), + .DIN (DIN), + .WR_EN (WR_EN), + .RD_EN (RD_EN_FIFO_IN), + .PROG_EMPTY_THRESH (PROG_EMPTY_THRESH), + .PROG_EMPTY_THRESH_ASSERT (PROG_EMPTY_THRESH_ASSERT), + .PROG_EMPTY_THRESH_NEGATE (PROG_EMPTY_THRESH_NEGATE), + .PROG_FULL_THRESH (PROG_FULL_THRESH), + .PROG_FULL_THRESH_ASSERT (PROG_FULL_THRESH_ASSERT), + .PROG_FULL_THRESH_NEGATE (PROG_FULL_THRESH_NEGATE), + .INJECTSBITERR (inject_sbit_err), + .INJECTDBITERR (inject_dbit_err), + .DOUT (DOUT_FIFO_OUT), + .FULL (FULL_FIFO_OUT), + .ALMOST_FULL (ALMOST_FULL_FIFO_OUT), + .WR_ACK (WR_ACK_FIFO_OUT), + .OVERFLOW (OVERFLOW_FIFO_OUT), + .EMPTY (EMPTY_FIFO_OUT), + .ALMOST_EMPTY (ALMOST_EMPTY_FIFO_OUT), + .VALID (VALID_FIFO_OUT), + .UNDERFLOW (UNDERFLOW_FIFO_OUT), + .DATA_COUNT (DATA_COUNT_FIFO_OUT), + .PROG_FULL (PROG_FULL_FIFO_OUT), + .PROG_EMPTY (PROG_EMPTY_FIFO_OUT), + .SBITERR (sbiterr_fifo_out), + .DBITERR (dbiterr_fifo_out) + ); +end +1 : begin : block1 + //Independent Clocks Behavioral Model + fifo_generator_v6_1_bhv_ver_as + #( + C_DATA_COUNT_WIDTH, + C_DIN_WIDTH, + C_DOUT_RST_VAL, + C_DOUT_WIDTH, + C_FULL_FLAGS_RST_VAL, + C_HAS_ALMOST_EMPTY, + C_HAS_ALMOST_FULL, + C_HAS_DATA_COUNT, + C_HAS_OVERFLOW, + C_HAS_RD_DATA_COUNT, + C_HAS_RST, + C_HAS_UNDERFLOW, + C_HAS_VALID, + C_HAS_WR_ACK, + C_HAS_WR_DATA_COUNT, + C_IMPLEMENTATION_TYPE, + C_MEMORY_TYPE, + C_OVERFLOW_LOW, + C_PRELOAD_LATENCY, + C_PRELOAD_REGS, + C_PROG_EMPTY_THRESH_ASSERT_VAL, + C_PROG_EMPTY_THRESH_NEGATE_VAL, + C_PROG_EMPTY_TYPE, + C_PROG_FULL_THRESH_ASSERT_VAL, + C_PROG_FULL_THRESH_NEGATE_VAL, + C_PROG_FULL_TYPE, + C_RD_DATA_COUNT_WIDTH, + C_RD_DEPTH, + C_RD_PNTR_WIDTH, + C_UNDERFLOW_LOW, + C_USE_DOUT_RST, + C_USE_EMBEDDED_REG, + C_USE_FWFT_DATA_COUNT, + C_VALID_LOW, + C_WR_ACK_LOW, + C_WR_DATA_COUNT_WIDTH, + C_WR_DEPTH, + C_WR_PNTR_WIDTH, + C_USE_ECC, + C_ENABLE_RST_SYNC, + C_ERROR_INJECTION_TYPE + ) + gen_as + ( + .WR_CLK (WR_CLK), + .RD_CLK (RD_CLK), + .RST (rst_i), + .RST_FULL_GEN (rst_full_gen_i), + .RST_FULL_FF (rst_full_ff_i), + .WR_RST (wr_rst_i), + .RD_RST (rd_rst_i), + .DIN (DIN), + .WR_EN (WR_EN), + .RD_EN (RD_EN_FIFO_IN), + .RD_EN_USER (RD_EN), + .PROG_EMPTY_THRESH (PROG_EMPTY_THRESH), + .PROG_EMPTY_THRESH_ASSERT (PROG_EMPTY_THRESH_ASSERT), + .PROG_EMPTY_THRESH_NEGATE (PROG_EMPTY_THRESH_NEGATE), + .PROG_FULL_THRESH (PROG_FULL_THRESH), + .PROG_FULL_THRESH_ASSERT (PROG_FULL_THRESH_ASSERT), + .PROG_FULL_THRESH_NEGATE (PROG_FULL_THRESH_NEGATE), + .INJECTSBITERR (inject_sbit_err), + .INJECTDBITERR (inject_dbit_err), + .USER_EMPTY_FB (EMPTY_P0_OUT), + .DOUT (DOUT_FIFO_OUT), + .FULL (FULL_FIFO_OUT), + .ALMOST_FULL (ALMOST_FULL_FIFO_OUT), + .WR_ACK (WR_ACK_FIFO_OUT), + .OVERFLOW (OVERFLOW_FIFO_OUT), + .EMPTY (EMPTY_FIFO_OUT), + .ALMOST_EMPTY (ALMOST_EMPTY_FIFO_OUT), + .VALID (VALID_FIFO_OUT), + .UNDERFLOW (UNDERFLOW_FIFO_OUT), + .RD_DATA_COUNT (RD_DATA_COUNT_FIFO_OUT), + .WR_DATA_COUNT (WR_DATA_COUNT_FIFO_OUT), + .PROG_FULL (PROG_FULL_FIFO_OUT), + .PROG_EMPTY (PROG_EMPTY_FIFO_OUT), + .SBITERR (sbiterr_fifo_out), + .DBITERR (dbiterr_fifo_out) + ); +end + +default : begin : block1 + //Independent Clocks Behavioral Model + fifo_generator_v6_1_bhv_ver_as + #( + C_DATA_COUNT_WIDTH, + C_DIN_WIDTH, + C_DOUT_RST_VAL, + C_DOUT_WIDTH, + C_FULL_FLAGS_RST_VAL, + C_HAS_ALMOST_EMPTY, + C_HAS_ALMOST_FULL, + C_HAS_DATA_COUNT, + C_HAS_OVERFLOW, + C_HAS_RD_DATA_COUNT, + C_HAS_RST, + C_HAS_UNDERFLOW, + C_HAS_VALID, + C_HAS_WR_ACK, + C_HAS_WR_DATA_COUNT, + C_IMPLEMENTATION_TYPE, + C_MEMORY_TYPE, + C_OVERFLOW_LOW, + C_PRELOAD_LATENCY, + C_PRELOAD_REGS, + C_PROG_EMPTY_THRESH_ASSERT_VAL, + C_PROG_EMPTY_THRESH_NEGATE_VAL, + C_PROG_EMPTY_TYPE, + C_PROG_FULL_THRESH_ASSERT_VAL, + C_PROG_FULL_THRESH_NEGATE_VAL, + C_PROG_FULL_TYPE, + C_RD_DATA_COUNT_WIDTH, + C_RD_DEPTH, + C_RD_PNTR_WIDTH, + C_UNDERFLOW_LOW, + C_USE_DOUT_RST, + C_USE_EMBEDDED_REG, + C_USE_FWFT_DATA_COUNT, + C_VALID_LOW, + C_WR_ACK_LOW, + C_WR_DATA_COUNT_WIDTH, + C_WR_DEPTH, + C_WR_PNTR_WIDTH, + C_USE_ECC, + C_ENABLE_RST_SYNC, + C_ERROR_INJECTION_TYPE + ) + gen_as + ( + .WR_CLK (WR_CLK), + .RD_CLK (RD_CLK), + .RST (rst_i), + .RST_FULL_GEN (rst_full_gen_i), + .RST_FULL_FF (rst_full_ff_i), + .WR_RST (wr_rst_i), + .RD_RST (rd_rst_i), + .DIN (DIN), + .WR_EN (WR_EN), + .RD_EN (RD_EN_FIFO_IN), + .RD_EN_USER (RD_EN), + .PROG_EMPTY_THRESH (PROG_EMPTY_THRESH), + .PROG_EMPTY_THRESH_ASSERT (PROG_EMPTY_THRESH_ASSERT), + .PROG_EMPTY_THRESH_NEGATE (PROG_EMPTY_THRESH_NEGATE), + .PROG_FULL_THRESH (PROG_FULL_THRESH), + .PROG_FULL_THRESH_ASSERT (PROG_FULL_THRESH_ASSERT), + .PROG_FULL_THRESH_NEGATE (PROG_FULL_THRESH_NEGATE), + .INJECTSBITERR (inject_sbit_err), + .INJECTDBITERR (inject_dbit_err), + .USER_EMPTY_FB (EMPTY_P0_OUT), + .DOUT (DOUT_FIFO_OUT), + .FULL (FULL_FIFO_OUT), + .ALMOST_FULL (ALMOST_FULL_FIFO_OUT), + .WR_ACK (WR_ACK_FIFO_OUT), + .OVERFLOW (OVERFLOW_FIFO_OUT), + .EMPTY (EMPTY_FIFO_OUT), + .ALMOST_EMPTY (ALMOST_EMPTY_FIFO_OUT), + .VALID (VALID_FIFO_OUT), + .UNDERFLOW (UNDERFLOW_FIFO_OUT), + .RD_DATA_COUNT (RD_DATA_COUNT_FIFO_OUT), + .WR_DATA_COUNT (WR_DATA_COUNT_FIFO_OUT), + .PROG_FULL (PROG_FULL_FIFO_OUT), + .PROG_EMPTY (PROG_EMPTY_FIFO_OUT), + .SBITERR (sbiterr_fifo_out), + .DBITERR (dbiterr_fifo_out) + ); +end + +endcase +endgenerate + + + //************************************************************************** + // Connect Internal Signals + // (Signals labeled internal_*) + // In the normal case, these signals tie directly to the FIFO's inputs and + // outputs. + // In the case of Preload Latency 0 or 1, there are intermediate + // signals between the internal FIFO and the preload logic. + //************************************************************************** + + + //*********************************************** + // If First-Word Fall-Through, instantiate + // the preload0 (FWFT) module + //*********************************************** + generate + if (C_PRELOAD_REGS==1 && C_PRELOAD_LATENCY==0) begin : block2 + + + fifo_generator_v6_1_bhv_ver_preload0 + #( + C_DOUT_RST_VAL, + C_DOUT_WIDTH, + C_HAS_RST, + C_ENABLE_RST_SYNC, + C_HAS_SRST, + C_USE_DOUT_RST, + C_USE_ECC, + C_VALID_LOW, + C_UNDERFLOW_LOW, + C_MEMORY_TYPE + ) + fgpl0 + ( + .RD_CLK (RD_CLK_P0_IN), + .RD_RST (RST_P0_IN), + .SRST (SRST), + .RD_EN (RD_EN_P0_IN), + .FIFOEMPTY (EMPTY_P0_IN), + .FIFODATA (DATA_P0_IN), + .FIFOSBITERR (sbiterr_fifo_out), + .FIFODBITERR (dbiterr_fifo_out), + .USERDATA (DATA_P0_OUT), + .USERVALID (VALID_P0_OUT), + .USEREMPTY (EMPTY_P0_OUT), + .USERALMOSTEMPTY (ALMOSTEMPTY_P0_OUT), + .USERUNDERFLOW (UNDERFLOW_P0_OUT), + .RAMVALID (RAMVALID_P0_OUT), + .FIFORDEN (RDEN_P0_OUT), + .USERSBITERR (SBITERR), + .USERDBITERR (DBITERR) + ); + + + //*********************************************** + // Connect inputs to preload (FWFT) module + //*********************************************** + //Connect the RD_CLK of the Preload (FWFT) module to CLK if we + // have a common-clock FIFO, or RD_CLK if we have an + // independent clock FIFO + assign RD_CLK_P0_IN = ((C_VERILOG_IMPL == 0) ? CLK : RD_CLK); + assign RST_P0_IN = (C_COMMON_CLOCK == 0) ? rd_rst_i : (C_HAS_RST == 1) ? rst_i : 0; + assign RD_EN_P0_IN = RD_EN; + assign EMPTY_P0_IN = EMPTY_FIFO_OUT; + assign DATA_P0_IN = DOUT_FIFO_OUT; + + //*********************************************** + // Connect outputs from preload (FWFT) module + //*********************************************** + assign DOUT = DATA_P0_OUT; + assign VALID = VALID_P0_OUT ; + assign EMPTY = EMPTY_P0_OUT; + assign ALMOST_EMPTY = ALMOSTEMPTY_P0_OUT; + assign UNDERFLOW = UNDERFLOW_P0_OUT ; + + assign RD_EN_FIFO_IN = RDEN_P0_OUT; + + + //*********************************************** + // Create DATA_COUNT from First-Word Fall-Through + // data count + //*********************************************** + assign DATA_COUNT = (C_USE_FWFT_DATA_COUNT == 0)? DATA_COUNT_FIFO_OUT: + (C_DATA_COUNT_WIDTH>C_RD_PNTR_WIDTH) ? DATA_COUNT_FWFT[C_RD_PNTR_WIDTH:0] : + DATA_COUNT_FWFT[C_RD_PNTR_WIDTH:C_RD_PNTR_WIDTH-C_DATA_COUNT_WIDTH+1]; + + //*********************************************** + // Create DATA_COUNT from First-Word Fall-Through + // data count + //*********************************************** + always @ (posedge RD_CLK or posedge RST_P0_IN) begin + if (RST_P0_IN) begin + EMPTY_P0_OUT_Q <= #`TCQ 1; + ALMOSTEMPTY_P0_OUT_Q <= #`TCQ 1; + end else begin + EMPTY_P0_OUT_Q <= #`TCQ EMPTY_P0_OUT; + ALMOSTEMPTY_P0_OUT_Q <= #`TCQ ALMOSTEMPTY_P0_OUT; + end + end //always + + + //*********************************************** + // logic for common-clock data count when FWFT is selected + //*********************************************** + initial begin + SS_FWFT_RD = 1'b0; + DATA_COUNT_FWFT = 0 ; + SS_FWFT_WR = 1'b0 ; + end //initial + + + //*********************************************** + // common-clock data count is implemented as an + // up-down counter. SS_FWFT_WR and SS_FWFT_RD + // are the up/down enables for the counter. + //*********************************************** + always @ (RD_EN or VALID_P0_OUT or WR_EN or FULL_FIFO_OUT) begin + if (C_VALID_LOW == 1) begin + SS_FWFT_RD = RD_EN && ~VALID_P0_OUT ; + end else begin + SS_FWFT_RD = RD_EN && VALID_P0_OUT ; + end + SS_FWFT_WR = (WR_EN && (~FULL_FIFO_OUT)) ; + end + + //*********************************************** + // common-clock data count is implemented as an + // up-down counter for FWFT. This always block + // calculates the counter. + //*********************************************** + always @ (posedge RD_CLK_P0_IN or posedge RST_P0_IN) begin + if (RST_P0_IN) begin + DATA_COUNT_FWFT <= #`TCQ 0; + end else begin + if (SRST && (C_HAS_SRST == 1) ) begin + DATA_COUNT_FWFT <= #`TCQ 0; + end else begin + case ( {SS_FWFT_WR, SS_FWFT_RD}) + 2'b00: DATA_COUNT_FWFT <= #`TCQ DATA_COUNT_FWFT ; + 2'b01: DATA_COUNT_FWFT <= #`TCQ DATA_COUNT_FWFT - 1 ; + 2'b10: DATA_COUNT_FWFT <= #`TCQ DATA_COUNT_FWFT + 1 ; + 2'b11: DATA_COUNT_FWFT <= #`TCQ DATA_COUNT_FWFT ; + endcase + end //if SRST + end //IF RST + end //always + + + end else begin : block2 //if !(C_PRELOAD_REGS==1 && C_PRELOAD_LATENCY==0) + + //*********************************************** + // If NOT First-Word Fall-Through, wire the outputs + // of the internal _ss or _as FIFO directly to the + // output, and do not instantiate the preload0 + // module. + //*********************************************** + + assign RD_CLK_P0_IN = 0; + assign RST_P0_IN = 0; + assign RD_EN_P0_IN = 0; + + assign RD_EN_FIFO_IN = RD_EN; + + assign DOUT = DOUT_FIFO_OUT; + assign DATA_P0_IN = 0; + assign VALID = VALID_FIFO_OUT; + assign EMPTY = EMPTY_FIFO_OUT; + assign ALMOST_EMPTY = ALMOST_EMPTY_FIFO_OUT; + assign EMPTY_P0_IN = 0; + assign UNDERFLOW = UNDERFLOW_FIFO_OUT; + assign DATA_COUNT = DATA_COUNT_FIFO_OUT; + assign SBITERR = sbiterr_fifo_out; + assign DBITERR = dbiterr_fifo_out; + + end //if !(C_PRELOAD_REGS==1 && C_PRELOAD_LATENCY==0) + endgenerate + + + //*********************************************** + // Connect user flags to internal signals + //*********************************************** + + //If we are using extra logic for the FWFT data count, then override the + //RD_DATA_COUNT output when we are EMPTY or ALMOST_EMPTY. + //RD_DATA_COUNT is 0 when EMPTY and 1 when ALMOST_EMPTY. + generate + if (C_USE_FWFT_DATA_COUNT==1 && (C_RD_DATA_COUNT_WIDTH>C_RD_PNTR_WIDTH) ) begin : block3 + assign RD_DATA_COUNT = (EMPTY_P0_OUT_Q | RST_P0_IN) ? 0 : (ALMOSTEMPTY_P0_OUT_Q ? 1 : RD_DATA_COUNT_FIFO_OUT); + end //block3 + endgenerate + + //If we are using extra logic for the FWFT data count, then override the + //RD_DATA_COUNT output when we are EMPTY or ALMOST_EMPTY. + //Due to asymmetric ports, RD_DATA_COUNT is 0 when EMPTY or ALMOST_EMPTY. + generate + if (C_USE_FWFT_DATA_COUNT==1 && (C_RD_DATA_COUNT_WIDTH <=C_RD_PNTR_WIDTH) ) begin : block30 + assign RD_DATA_COUNT = (EMPTY_P0_OUT_Q | RST_P0_IN) ? 0 : (ALMOSTEMPTY_P0_OUT_Q ? 0 : RD_DATA_COUNT_FIFO_OUT); + end //block30 + endgenerate + + //If we are not using extra logic for the FWFT data count, + //then connect RD_DATA_COUNT to the RD_DATA_COUNT from the + //internal FIFO instance + generate + if (C_USE_FWFT_DATA_COUNT==0 ) begin : block31 + assign RD_DATA_COUNT = RD_DATA_COUNT_FIFO_OUT; + end + endgenerate + + //Always connect WR_DATA_COUNT to the WR_DATA_COUNT from the internal + //FIFO instance + generate + if (C_USE_FWFT_DATA_COUNT==1) begin : block4 + assign WR_DATA_COUNT = WR_DATA_COUNT_FIFO_OUT; + end + else begin : block4 + assign WR_DATA_COUNT = WR_DATA_COUNT_FIFO_OUT; + end + endgenerate + + + //Connect other flags to the internal FIFO instance + assign FULL = FULL_FIFO_OUT; + assign ALMOST_FULL = ALMOST_FULL_FIFO_OUT; + assign WR_ACK = WR_ACK_FIFO_OUT; + assign OVERFLOW = OVERFLOW_FIFO_OUT; + assign PROG_FULL = PROG_FULL_FIFO_OUT; + assign PROG_EMPTY = PROG_EMPTY_FIFO_OUT; + + + // if an asynchronous FIFO has been selected, display a message that the FIFO + // will not be cycle-accurate in simulation + initial begin + if (C_IMPLEMENTATION_TYPE == 2) begin + $display("WARNING: Behavioral models for independent clock FIFO configurations are not cycle-accurate. You may wish to choose the structural simulation model instead of the behavioral model. This will ensure accurate behavior and latencies during simulation. You can enable this from CORE Generator by selecting Project -> Project Options -> Generation tab -> Structural Simulation. See the FIFO Generator User Guide for more information."); + end else if (C_MEMORY_TYPE == 4) begin + $display("FAILURE : Behavioral models for Virtex-4, Virtex-5 and Virtex-6 built-in FIFO configurations is currently not supported. Please select the structural simulation model option in CORE Generator. You can enable this in CORE Generator by selecting Project -> Project Options -> Generation tab -> Structural Simulation. See the FIFO Generator User Guide for more information."); + $finish; + end + end //initial + + /************************************************************************** + * Internal reset logic + **************************************************************************/ + assign wr_rst_i = (C_HAS_RST == 1 || C_ENABLE_RST_SYNC == 0) ? wr_rst_reg : 0; + assign rd_rst_i = (C_HAS_RST == 1 || C_ENABLE_RST_SYNC == 0) ? rd_rst_reg : 0; + assign rst_i = C_HAS_RST ? rst_reg : 0; + + wire rst_2_sync; + wire clk_2_sync = (C_COMMON_CLOCK == 1) ? CLK : WR_CLK; + generate + if (C_ENABLE_RST_SYNC == 0) begin : gnrst_sync + always @* begin + wr_rst_reg <= WR_RST; + rd_rst_reg <= RD_RST; + rst_reg <= 1'b0; + end + assign rst_2_sync = WR_RST; + end else if (C_HAS_RST == 1 && C_COMMON_CLOCK == 0) begin : gic_rst + assign wr_rst_comb = !wr_rst_asreg_d2 && wr_rst_asreg; + assign rd_rst_comb = !rd_rst_asreg_d2 && rd_rst_asreg; + assign rst_2_sync = RST; + + always @(posedge WR_CLK or posedge RST) begin + if (RST == 1'b1) begin + wr_rst_asreg <= #`TCQ 1'b1; + end else begin + if (wr_rst_asreg_d1 == 1'b1) begin + wr_rst_asreg <= #`TCQ 1'b0; + end else begin + wr_rst_asreg <= #`TCQ wr_rst_asreg; + end + end + end + + always @(posedge WR_CLK) begin + wr_rst_asreg_d1 <= #`TCQ wr_rst_asreg; + wr_rst_asreg_d2 <= #`TCQ wr_rst_asreg_d1; + end + + always @(posedge WR_CLK or posedge wr_rst_comb) begin + if (wr_rst_comb == 1'b1) begin + wr_rst_reg <= #`TCQ 1'b1; + end else begin + wr_rst_reg <= #`TCQ 1'b0; + end + end + + always @(posedge RD_CLK or posedge RST) begin + if (RST == 1'b1) begin + rd_rst_asreg <= #`TCQ 1'b1; + end else begin + if (rd_rst_asreg_d1 == 1'b1) begin + rd_rst_asreg <= #`TCQ 1'b0; + end else begin + rd_rst_asreg <= #`TCQ rd_rst_asreg; + end + end + end + + always @(posedge RD_CLK) begin + rd_rst_asreg_d1 <= #`TCQ rd_rst_asreg; + rd_rst_asreg_d2 <= #`TCQ rd_rst_asreg_d1; + end + + always @(posedge RD_CLK or posedge rd_rst_comb) begin + if (rd_rst_comb == 1'b1) begin + rd_rst_reg <= #`TCQ 1'b1; + end else begin + rd_rst_reg <= #`TCQ 1'b0; + end + end + end else if (C_HAS_RST == 1 && C_COMMON_CLOCK == 1) begin : gcc_rst + assign rst_comb = !rst_asreg_d2 && rst_asreg; + assign rst_2_sync = RST; + + always @(posedge CLK or posedge RST) begin + if (RST == 1'b1) begin + rst_asreg <= #`TCQ 1'b1; + end else begin + if (rst_asreg_d1 == 1'b1) begin + rst_asreg <= #`TCQ 1'b0; + end else begin + rst_asreg <= #`TCQ rst_asreg; + end + end + end + + always @(posedge CLK) begin + rst_asreg_d1 <= #`TCQ rst_asreg; + rst_asreg_d2 <= #`TCQ rst_asreg_d1; + end + + always @(posedge CLK or posedge rst_comb) begin + if (rst_comb == 1'b1) begin + rst_reg <= #`TCQ 1'b1; + end else begin + rst_reg <= #`TCQ 1'b0; + end + end + end + endgenerate + + reg rst_d1 = 1'b0; + reg rst_d2 = 1'b0; + reg rst_d3 = 1'b0; + reg rst_d4 = 1'b0; + generate + if ((C_HAS_RST == 1 || C_HAS_SRST == 1 || C_ENABLE_RST_SYNC == 0) && C_FULL_FLAGS_RST_VAL == 1) begin : grstd1 + // RST_FULL_GEN replaces the reset falling edge detection used to de-assert + // FULL, ALMOST_FULL & PROG_FULL flags if C_FULL_FLAGS_RST_VAL = 1. + + // RST_FULL_FF goes to the reset pin of the final flop of FULL, ALMOST_FULL & + // PROG_FULL + + always @ (posedge rst_2_sync or posedge clk_2_sync) begin + if (rst_2_sync) begin + rst_d1 <= 1'b1; + rst_d2 <= 1'b1; + rst_d3 <= 1'b1; + rst_d4 <= 1'b0; + end else begin + if (SRST) begin + rst_d1 <= #`TCQ 1'b1; + rst_d2 <= #`TCQ 1'b1; + rst_d3 <= #`TCQ 1'b1; + rst_d4 <= #`TCQ 1'b0; + end else begin + rst_d1 <= #`TCQ 1'b0; + rst_d2 <= #`TCQ rst_d1; + rst_d3 <= #`TCQ rst_d2; + rst_d4 <= #`TCQ rst_d3; + end + end + end + assign rst_full_ff_i = (C_HAS_SRST == 0) ? rst_d2 : 1'b0 ; + assign rst_full_gen_i = rst_d4; + + end else if ((C_HAS_RST == 1 || C_HAS_SRST == 1 || C_ENABLE_RST_SYNC == 0) && C_FULL_FLAGS_RST_VAL == 0) begin : gnrst_full + assign rst_full_gen_i = 1'b0; + assign rst_full_ff_i = (C_COMMON_CLOCK == 0) ? wr_rst_i : rst_i; + end + endgenerate + +endmodule //FIFO_GENERATOR_V6_1 + + + +/******************************************************************************* + * Declaration of Independent-Clocks FIFO Module + ******************************************************************************/ +module fifo_generator_v6_1_bhv_ver_as + + /*************************************************************************** + * Declare user parameters and their defaults + ***************************************************************************/ + #( + parameter C_DATA_COUNT_WIDTH = 2, + parameter C_DIN_WIDTH = 8, + parameter C_DOUT_RST_VAL = "", + parameter C_DOUT_WIDTH = 8, + parameter C_FULL_FLAGS_RST_VAL = 1, + parameter C_HAS_ALMOST_EMPTY = 0, + parameter C_HAS_ALMOST_FULL = 0, + parameter C_HAS_DATA_COUNT = 0, + parameter C_HAS_OVERFLOW = 0, + parameter C_HAS_RD_DATA_COUNT = 0, + parameter C_HAS_RST = 0, + parameter C_HAS_UNDERFLOW = 0, + parameter C_HAS_VALID = 0, + parameter C_HAS_WR_ACK = 0, + parameter C_HAS_WR_DATA_COUNT = 0, + parameter C_IMPLEMENTATION_TYPE = 0, + parameter C_MEMORY_TYPE = 1, + parameter C_OVERFLOW_LOW = 0, + parameter C_PRELOAD_LATENCY = 1, + parameter C_PRELOAD_REGS = 0, + parameter C_PROG_EMPTY_THRESH_ASSERT_VAL = 0, + parameter C_PROG_EMPTY_THRESH_NEGATE_VAL = 0, + parameter C_PROG_EMPTY_TYPE = 0, + parameter C_PROG_FULL_THRESH_ASSERT_VAL = 0, + parameter C_PROG_FULL_THRESH_NEGATE_VAL = 0, + parameter C_PROG_FULL_TYPE = 0, + parameter C_RD_DATA_COUNT_WIDTH = 2, + parameter C_RD_DEPTH = 256, + parameter C_RD_PNTR_WIDTH = 8, + parameter C_UNDERFLOW_LOW = 0, + parameter C_USE_DOUT_RST = 0, + parameter C_USE_EMBEDDED_REG = 0, + parameter C_USE_FWFT_DATA_COUNT = 0, + parameter C_VALID_LOW = 0, + parameter C_WR_ACK_LOW = 0, + parameter C_WR_DATA_COUNT_WIDTH = 2, + parameter C_WR_DEPTH = 256, + parameter C_WR_PNTR_WIDTH = 8, + parameter C_USE_ECC = 0, + parameter C_ENABLE_RST_SYNC = 1, + parameter C_ERROR_INJECTION_TYPE = 0 + ) + + /*************************************************************************** + * Declare Input and Output Ports + ***************************************************************************/ + ( + input [C_DIN_WIDTH-1:0] DIN, + input [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH, + input [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_ASSERT, + input [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_NEGATE, + input [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH, + input [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_ASSERT, + input [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_NEGATE, + input RD_CLK, + input RD_EN, + input RD_EN_USER, + input RST, + input RST_FULL_GEN, + input RST_FULL_FF, + input WR_RST, + input RD_RST, + input WR_CLK, + input WR_EN, + input INJECTDBITERR, + input INJECTSBITERR, + input USER_EMPTY_FB, + output reg ALMOST_EMPTY = 1'b1, + output reg ALMOST_FULL = C_FULL_FLAGS_RST_VAL, + output [C_DOUT_WIDTH-1:0] DOUT, + output reg EMPTY = 1'b1, + output reg FULL = C_FULL_FLAGS_RST_VAL, + output OVERFLOW, + output PROG_EMPTY, + output PROG_FULL, + output VALID, + output [C_RD_DATA_COUNT_WIDTH-1:0] RD_DATA_COUNT, + output UNDERFLOW, + output WR_ACK, + output [C_WR_DATA_COUNT_WIDTH-1:0] WR_DATA_COUNT, + output SBITERR, + output DBITERR + ); + + reg [C_RD_PNTR_WIDTH:0] rd_data_count_int = 0; + reg [C_WR_PNTR_WIDTH:0] wr_data_count_int = 0; + reg [C_WR_PNTR_WIDTH:0] wdc_fwft_ext_as = 0; + + + /*************************************************************************** + * Parameters used as constants + **************************************************************************/ + //When RST is present, set FULL reset value to '1'. + //If core has no RST, make sure FULL powers-on as '0'. + parameter C_DEPTH_RATIO_WR = + (C_WR_DEPTH>C_RD_DEPTH) ? (C_WR_DEPTH/C_RD_DEPTH) : 1; + parameter C_DEPTH_RATIO_RD = + (C_RD_DEPTH>C_WR_DEPTH) ? (C_RD_DEPTH/C_WR_DEPTH) : 1; + parameter C_FIFO_WR_DEPTH = C_WR_DEPTH - 1; + parameter C_FIFO_RD_DEPTH = C_RD_DEPTH - 1; + + // C_DEPTH_RATIO_WR | C_DEPTH_RATIO_RD | C_PNTR_WIDTH | EXTRA_WORDS_DC + // -----------------|------------------|-----------------|--------------- + // 1 | 8 | C_RD_PNTR_WIDTH | 2 + // 1 | 4 | C_RD_PNTR_WIDTH | 2 + // 1 | 2 | C_RD_PNTR_WIDTH | 2 + // 1 | 1 | C_WR_PNTR_WIDTH | 2 + // 2 | 1 | C_WR_PNTR_WIDTH | 4 + // 4 | 1 | C_WR_PNTR_WIDTH | 8 + // 8 | 1 | C_WR_PNTR_WIDTH | 16 + + localparam C_PNTR_WIDTH = (C_WR_PNTR_WIDTH>=C_RD_PNTR_WIDTH) ? C_WR_PNTR_WIDTH : C_RD_PNTR_WIDTH; + wire [C_PNTR_WIDTH:0] EXTRA_WORDS_DC = (C_DEPTH_RATIO_WR == 1) ? 2 : (2 * C_DEPTH_RATIO_WR/C_DEPTH_RATIO_RD); + + parameter [31:0] reads_per_write = C_DIN_WIDTH/C_DOUT_WIDTH; + + parameter [31:0] log2_reads_per_write = log2_val(reads_per_write); + + parameter [31:0] writes_per_read = C_DOUT_WIDTH/C_DIN_WIDTH; + + parameter [31:0] log2_writes_per_read = log2_val(writes_per_read); + + + + /************************************************************************** + * FIFO Contents Tracking and Data Count Calculations + *************************************************************************/ + + // Memory which will be used to simulate a FIFO + reg [C_DIN_WIDTH-1:0] memory[C_WR_DEPTH-1:0]; + // Local parameters used to determine whether to inject ECC error or not + localparam SYMMETRIC_PORT = (C_DIN_WIDTH == C_DOUT_WIDTH) ? 1 : 0; + localparam ERR_INJECTION = (C_ERROR_INJECTION_TYPE != 0) ? 1 : 0; + localparam ENABLE_ERR_INJECTION = C_USE_ECC && SYMMETRIC_PORT && ERR_INJECTION; + // Array that holds the error injection type (single/double bit error) on + // a specific write operation, which is returned on read to corrupt the + // output data. + reg [1:0] ecc_err[C_WR_DEPTH-1:0]; + + //The amount of data stored in the FIFO at any time is given + // by num_wr_bits (in the WR_CLK domain) and num_rd_bits (in the RD_CLK + // domain. + //num_wr_bits is calculated by considering the total words in the FIFO, + // and the state of the read pointer (which may not have yet crossed clock + // domains.) + //num_rd_bits is calculated by considering the total words in the FIFO, + // and the state of the write pointer (which may not have yet crossed clock + // domains.) + reg [31:0] num_wr_bits; + reg [31:0] num_rd_bits; + reg [31:0] next_num_wr_bits; + reg [31:0] next_num_rd_bits; + + //The write pointer - tracks write operations + // (Works opposite to core: wr_ptr is a DOWN counter) + reg [31:0] wr_ptr; + reg [C_WR_PNTR_WIDTH-1:0] wr_pntr = 0; // UP counter: Rolls back to 0 when reaches to max value. + reg [C_WR_PNTR_WIDTH-1:0] wr_pntr_rd1 = 0; + reg [C_WR_PNTR_WIDTH-1:0] wr_pntr_rd2 = 0; + reg [C_WR_PNTR_WIDTH-1:0] wr_pntr_rd3 = 0; + wire [C_RD_PNTR_WIDTH-1:0] adj_wr_pntr_rd; + reg [C_WR_PNTR_WIDTH-1:0] wr_pntr_rd = 0; + wire wr_rst_i = WR_RST; + reg wr_rst_d1 =0; + + //The read pointer - tracks read operations + // (rd_ptr Works opposite to core: rd_ptr is a DOWN counter) + reg [31:0] rd_ptr; + reg [C_RD_PNTR_WIDTH-1:0] rd_pntr = 0; // UP counter: Rolls back to 0 when reaches to max value. + reg [C_RD_PNTR_WIDTH-1:0] rd_pntr_wr1 = 0; + reg [C_RD_PNTR_WIDTH-1:0] rd_pntr_wr2 = 0; + reg [C_RD_PNTR_WIDTH-1:0] rd_pntr_wr3 = 0; + reg [C_RD_PNTR_WIDTH-1:0] rd_pntr_wr4 = 0; + wire [C_WR_PNTR_WIDTH-1:0] adj_rd_pntr_wr; + reg [C_RD_PNTR_WIDTH-1:0] rd_pntr_wr = 0; + wire rd_rst_i = RD_RST; + wire ram_rd_en; + reg ram_rd_en_d1 = 1'b0; + + + // Delayed ram_rd_en is needed only for STD Embedded register option + generate + if (C_PRELOAD_LATENCY == 2) begin : grd_d + always @ (posedge RD_CLK or posedge rd_rst_i) begin + if (rd_rst_i) + ram_rd_en_d1 <= #`TCQ 1'b0; + else + ram_rd_en_d1 <= #`TCQ ram_rd_en; + end + end + endgenerate + + // Write pointer adjustment based on pointers width for EMPTY/ALMOST_EMPTY generation + generate + if (C_RD_PNTR_WIDTH > C_WR_PNTR_WIDTH) begin : rdg // Read depth greater than write depth + assign adj_wr_pntr_rd[C_RD_PNTR_WIDTH-1:C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH] = wr_pntr_rd; + assign adj_wr_pntr_rd[C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH-1:0] = 0; + end else begin : rdl // Read depth lesser than or equal to write depth + assign adj_wr_pntr_rd = wr_pntr_rd[C_WR_PNTR_WIDTH-1:C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH]; + end + endgenerate + + // Generate Empty and Almost Empty + // ram_rd_en used to determine EMPTY should depend on the EMPTY. + assign ram_rd_en = RD_EN & !EMPTY; + assign empty_int = ((adj_wr_pntr_rd == rd_pntr) || (ram_rd_en && (adj_wr_pntr_rd == (rd_pntr+1'h1)))); + assign almost_empty_int = ((adj_wr_pntr_rd == (rd_pntr+1'h1)) || (ram_rd_en && (adj_wr_pntr_rd == (rd_pntr+2'h2)))); + + // Register Empty and Almost Empty + always @ (posedge RD_CLK or posedge rd_rst_i) + begin + if (rd_rst_i) begin + EMPTY <= #`TCQ 1'b1; + ALMOST_EMPTY <= #`TCQ 1'b1; + rd_data_count_int <= #`TCQ {C_RD_PNTR_WIDTH-1{1'b0}}; + end else begin + rd_data_count_int <= #`TCQ {(adj_wr_pntr_rd[C_RD_PNTR_WIDTH-1:0] - rd_pntr[C_RD_PNTR_WIDTH-1:0]), 1'b0}; + + if (empty_int) + EMPTY <= #`TCQ 1'b1; + else + EMPTY <= #`TCQ 1'b0; + + if (!EMPTY) begin + if (almost_empty_int) + ALMOST_EMPTY <= #`TCQ 1'b1; + else + ALMOST_EMPTY <= #`TCQ 1'b0; + end + end // rd_rst_i + end // always + + // Read pointer adjustment based on pointers width for EMPTY/ALMOST_EMPTY generation + generate + if (C_WR_PNTR_WIDTH > C_RD_PNTR_WIDTH) begin : wdg // Write depth greater than read depth + assign adj_rd_pntr_wr[C_WR_PNTR_WIDTH-1:C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH] = rd_pntr_wr; + assign adj_rd_pntr_wr[C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH-1:0] = 0; + end else begin : wdl // Write depth lesser than or equal to read depth + assign adj_rd_pntr_wr = rd_pntr_wr[C_RD_PNTR_WIDTH-1:C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH]; + end + endgenerate + + // Generate FULL and ALMOST_FULL + // ram_wr_en used to determine FULL should depend on the FULL. + assign ram_wr_en = WR_EN & !FULL; + assign full_int = ((adj_rd_pntr_wr == (wr_pntr+1'h1)) || (ram_wr_en && (adj_rd_pntr_wr == (wr_pntr+2'h2)))); + assign almost_full_int = ((adj_rd_pntr_wr == (wr_pntr+2'h2)) || (ram_wr_en && (adj_rd_pntr_wr == (wr_pntr+3'h3)))); + + // Register FULL and ALMOST_FULL Empty + always @ (posedge WR_CLK or posedge RST_FULL_FF) + begin + if (RST_FULL_FF) begin + FULL <= #`TCQ C_FULL_FLAGS_RST_VAL; + ALMOST_FULL <= #`TCQ C_FULL_FLAGS_RST_VAL; + wr_data_count_int <= #`TCQ {C_WR_DATA_COUNT_WIDTH-1{1'b0}}; + end else begin + wr_data_count_int <= #`TCQ {(wr_pntr[C_WR_PNTR_WIDTH-1:0] - adj_rd_pntr_wr[C_WR_PNTR_WIDTH-1:0]), 1'b0}; + if (full_int) begin + FULL <= #`TCQ 1'b1; + end else begin + FULL <= #`TCQ 1'b0; + end + + if (RST_FULL_GEN) begin + ALMOST_FULL <= #`TCQ 1'b0; + end else if (!FULL) begin + if (almost_full_int) + ALMOST_FULL <= #`TCQ 1'b1; + else + ALMOST_FULL <= #`TCQ 1'b0; + end + end // wr_rst_i + end // always + + // Determine which stage in FWFT registers are valid + reg stage1_valid = 0; + reg stage2_valid = 0; + generate + if (C_PRELOAD_LATENCY == 0) begin : grd_fwft_proc + always @ (posedge RD_CLK or posedge rd_rst_i) begin + if (rd_rst_i) begin + stage1_valid <= #`TCQ 0; + stage2_valid <= #`TCQ 0; + end else begin + + if (!stage1_valid && !stage2_valid) begin + if (!EMPTY) + stage1_valid <= #`TCQ 1'b1; + else + stage1_valid <= #`TCQ 1'b0; + end else if (stage1_valid && !stage2_valid) begin + if (EMPTY) begin + stage1_valid <= #`TCQ 1'b0; + stage2_valid <= #`TCQ 1'b1; + end else begin + stage1_valid <= #`TCQ 1'b1; + stage2_valid <= #`TCQ 1'b1; + end + end else if (!stage1_valid && stage2_valid) begin + if (EMPTY && RD_EN_USER) begin + stage1_valid <= #`TCQ 1'b0; + stage2_valid <= #`TCQ 1'b0; + end else if (!EMPTY && RD_EN_USER) begin + stage1_valid <= #`TCQ 1'b1; + stage2_valid <= #`TCQ 1'b0; + end else if (!EMPTY && !RD_EN_USER) begin + stage1_valid <= #`TCQ 1'b1; + stage2_valid <= #`TCQ 1'b1; + end else begin + stage1_valid <= #`TCQ 1'b0; + stage2_valid <= #`TCQ 1'b1; + end + end else if (stage1_valid && stage2_valid) begin + if (EMPTY && RD_EN_USER) begin + stage1_valid <= #`TCQ 1'b0; + stage2_valid <= #`TCQ 1'b1; + end else begin + stage1_valid <= #`TCQ 1'b1; + stage2_valid <= #`TCQ 1'b1; + end + end else begin + stage1_valid <= #`TCQ 1'b0; + stage2_valid <= #`TCQ 1'b0; + end + end // rd_rst_i + end // always + end + endgenerate + + //Pointers passed into opposite clock domain + reg [31:0] wr_ptr_rdclk; + reg [31:0] wr_ptr_rdclk_next; + reg [31:0] rd_ptr_wrclk; + reg [31:0] rd_ptr_wrclk_next; + + //Amount of data stored in the FIFO scaled to the narrowest (deepest) port + // (Do not include data in FWFT stages) + //Used to calculate PROG_EMPTY. + wire [31:0] num_read_words_pe = + num_rd_bits/(C_DOUT_WIDTH/C_DEPTH_RATIO_WR); + + //Amount of data stored in the FIFO scaled to the narrowest (deepest) port + // (Do not include data in FWFT stages) + //Used to calculate PROG_FULL. + wire [31:0] num_write_words_pf = + num_wr_bits/(C_DIN_WIDTH/C_DEPTH_RATIO_RD); + + /************************** + * Read Data Count + *************************/ + + reg [31:0] num_read_words_dc; + reg [C_RD_DATA_COUNT_WIDTH-1:0] num_read_words_sized_i; + + always @(num_rd_bits) begin + if (C_USE_FWFT_DATA_COUNT) begin + + //If using extra logic for FWFT Data Counts, + // then scale FIFO contents to read domain, + // and add two read words for FWFT stages + //This value is only a temporary value and not used in the code. + num_read_words_dc = (num_rd_bits/C_DOUT_WIDTH+2); + + //Trim the read words for use with RD_DATA_COUNT + num_read_words_sized_i = + num_read_words_dc[C_RD_PNTR_WIDTH : C_RD_PNTR_WIDTH-C_RD_DATA_COUNT_WIDTH+1]; + + end else begin + + //If not using extra logic for FWFT Data Counts, + // then scale FIFO contents to read domain. + //This value is only a temporary value and not used in the code. + num_read_words_dc = num_rd_bits/C_DOUT_WIDTH; + + //Trim the read words for use with RD_DATA_COUNT + num_read_words_sized_i = + num_read_words_dc[C_RD_PNTR_WIDTH-1 : C_RD_PNTR_WIDTH-C_RD_DATA_COUNT_WIDTH]; + + end //if (C_USE_FWFT_DATA_COUNT) + end //always + + + /************************** + * Write Data Count + *************************/ + + reg [31:0] num_write_words_dc; + reg [C_WR_DATA_COUNT_WIDTH-1:0] num_write_words_sized_i; + + always @(num_wr_bits) begin + if (C_USE_FWFT_DATA_COUNT) begin + + //Calculate the Data Count value for the number of write words, + // when using First-Word Fall-Through with extra logic for Data + // Counts. This takes into consideration the number of words that + // are expected to be stored in the FWFT register stages (it always + // assumes they are filled). + //This value is scaled to the Write Domain. + //The expression (((A-1)/B))+1 divides A/B, but takes the + // ceiling of the result. + //When num_wr_bits==0, set the result manually to prevent + // division errors. + //EXTRA_WORDS_DC is the number of words added to write_words + // due to FWFT. + //This value is only a temporary value and not used in the code. + num_write_words_dc = (num_wr_bits==0) ? EXTRA_WORDS_DC : (((num_wr_bits-1)/C_DIN_WIDTH)+1) + EXTRA_WORDS_DC ; + + //Trim the write words for use with WR_DATA_COUNT + num_write_words_sized_i = + num_write_words_dc[C_WR_PNTR_WIDTH : C_WR_PNTR_WIDTH-C_WR_DATA_COUNT_WIDTH+1]; + + end else begin + + //Calculate the Data Count value for the number of write words, when NOT + // using First-Word Fall-Through with extra logic for Data Counts. This + // calculates only the number of words in the internal FIFO. + //The expression (((A-1)/B))+1 divides A/B, but takes the + // ceiling of the result. + //This value is scaled to the Write Domain. + //When num_wr_bits==0, set the result manually to prevent + // division errors. + //This value is only a temporary value and not used in the code. + num_write_words_dc = (num_wr_bits==0) ? 0 : ((num_wr_bits-1)/C_DIN_WIDTH)+1; + + //Trim the read words for use with RD_DATA_COUNT + num_write_words_sized_i = + num_write_words_dc[C_WR_PNTR_WIDTH-1 : C_WR_PNTR_WIDTH-C_WR_DATA_COUNT_WIDTH]; + + end //if (C_USE_FWFT_DATA_COUNT) + end //always + + + + /*************************************************************************** + * Internal registers and wires + **************************************************************************/ + + //Temporary signals used for calculating the model's outputs. These + //are only used in the assign statements immediately following wire, + //parameter, and function declarations. + wire [C_DOUT_WIDTH-1:0] ideal_dout_out; + wire valid_i; + wire valid_out; + wire underflow_i; + + //Ideal FIFO signals. These are the raw output of the behavioral model, + //which behaves like an ideal FIFO. + reg [1:0] err_type = 0; + reg [1:0] err_type_d1 = 0; + reg [C_DOUT_WIDTH-1:0] ideal_dout = 0; + reg [C_DOUT_WIDTH-1:0] ideal_dout_d1 = 0; + reg ideal_wr_ack = 0; + reg ideal_valid = 0; + reg ideal_overflow = 0; + reg ideal_underflow = 0; + reg ideal_prog_full = 0; + reg ideal_prog_empty = 1; + reg [C_WR_DATA_COUNT_WIDTH-1 : 0] ideal_wr_count = 0; + reg [C_RD_DATA_COUNT_WIDTH-1 : 0] ideal_rd_count = 0; + + //Assorted reg values for delayed versions of signals + reg valid_d1 = 0; + + + //user specified value for reseting the size of the fifo + reg [C_DOUT_WIDTH-1:0] dout_reset_val = 0; + + //temporary registers for WR_RESPONSE_LATENCY feature + + integer tmp_wr_listsize; + integer tmp_rd_listsize; + + //Signal for registered version of prog full and empty + + //Threshold values for Programmable Flags + integer prog_empty_actual_thresh_assert; + integer prog_empty_actual_thresh_negate; + integer prog_full_actual_thresh_assert; + integer prog_full_actual_thresh_negate; + + + /**************************************************************************** + * Function Declarations + ***************************************************************************/ + + /************************************************************************** + * write_fifo + * This task writes a word to the FIFO memory and updates the + * write pointer. + * FIFO size is relative to write domain. + ***************************************************************************/ + task write_fifo; + begin + memory[wr_ptr] <= DIN; + wr_pntr <= #`TCQ wr_pntr + 1; + // Store the type of error injection (double/single) on write + case (C_ERROR_INJECTION_TYPE) + 3: ecc_err[wr_ptr] <= {INJECTDBITERR,INJECTSBITERR}; + 2: ecc_err[wr_ptr] <= {INJECTDBITERR,1'b0}; + 1: ecc_err[wr_ptr] <= {1'b0,INJECTSBITERR}; + default: ecc_err[wr_ptr] <= 0; + endcase + // (Works opposite to core: wr_ptr is a DOWN counter) + if (wr_ptr == 0) begin + wr_ptr <= C_WR_DEPTH - 1; + end else begin + wr_ptr <= wr_ptr - 1; + end + end + endtask // write_fifo + + /************************************************************************** + * read_fifo + * This task reads a word from the FIFO memory and updates the read + * pointer. It's output is the ideal_dout bus. + * FIFO size is relative to write domain. + ***************************************************************************/ + task read_fifo; + integer i; + reg [C_DOUT_WIDTH-1:0] tmp_dout; + reg [C_DIN_WIDTH-1:0] memory_read; + reg [31:0] tmp_rd_ptr; + reg [31:0] rd_ptr_high; + reg [31:0] rd_ptr_low; + reg [1:0] tmp_ecc_err; + begin + rd_pntr <= #`TCQ rd_pntr + 1; + // output is wider than input + if (reads_per_write == 0) begin + tmp_dout = 0; + tmp_rd_ptr = (rd_ptr << log2_writes_per_read)+(writes_per_read-1); + for (i = writes_per_read - 1; i >= 0; i = i - 1) begin + tmp_dout = tmp_dout << C_DIN_WIDTH; + tmp_dout = tmp_dout | memory[tmp_rd_ptr]; + + // (Works opposite to core: rd_ptr is a DOWN counter) + if (tmp_rd_ptr == 0) begin + tmp_rd_ptr = C_WR_DEPTH - 1; + end else begin + tmp_rd_ptr = tmp_rd_ptr - 1; + end + end + + // output is symmetric + end else if (reads_per_write == 1) begin + tmp_dout = memory[rd_ptr][C_DIN_WIDTH-1:0]; + // Retreive the error injection type. Based on the error injection type + // corrupt the output data. + tmp_ecc_err = ecc_err[rd_ptr]; + if (ENABLE_ERR_INJECTION && C_DIN_WIDTH == C_DOUT_WIDTH) begin + if (tmp_ecc_err[1]) begin // Corrupt the output data only for double bit error + if (C_DOUT_WIDTH == 1) + tmp_dout = tmp_dout[C_DOUT_WIDTH-1:0]; + else if (C_DOUT_WIDTH == 2) + tmp_dout = {~tmp_dout[C_DOUT_WIDTH-1],~tmp_dout[C_DOUT_WIDTH-2]}; + else + tmp_dout = {~tmp_dout[C_DOUT_WIDTH-1],~tmp_dout[C_DOUT_WIDTH-2],(tmp_dout << 2)}; + end else begin + tmp_dout = tmp_dout[C_DOUT_WIDTH-1:0]; + end + err_type <= {tmp_ecc_err[1], tmp_ecc_err[0] & !tmp_ecc_err[1]}; + end else begin + err_type <= 0; + end + + // input is wider than output + end else begin + rd_ptr_high = rd_ptr >> log2_reads_per_write; + rd_ptr_low = rd_ptr & (reads_per_write - 1); + memory_read = memory[rd_ptr_high]; + tmp_dout = memory_read >> (rd_ptr_low*C_DOUT_WIDTH); + end + ideal_dout <= tmp_dout; + + // (Works opposite to core: rd_ptr is a DOWN counter) + if (rd_ptr == 0) begin + rd_ptr <= C_RD_DEPTH - 1; + end else begin + rd_ptr <= rd_ptr - 1; + end + end + endtask + + /************************************************************************** + * log2_val + * Returns the 'log2' value for the input value for the supported ratios + ***************************************************************************/ + function [31:0] log2_val; + input [31:0] binary_val; + + begin + if (binary_val == 8) begin + log2_val = 3; + end else if (binary_val == 4) begin + log2_val = 2; + end else begin + log2_val = 1; + end + end + endfunction + + /*********************************************************************** + * hexstr_conv + * Converts a string of type hex to a binary value (for C_DOUT_RST_VAL) + ***********************************************************************/ + function [C_DOUT_WIDTH-1:0] hexstr_conv; + input [(C_DOUT_WIDTH*8)-1:0] def_data; + + integer index,i,j; + reg [3:0] bin; + + begin + index = 0; + hexstr_conv = 'b0; + for( i=C_DOUT_WIDTH-1; i>=0; i=i-1 ) + begin + case (def_data[7:0]) + 8'b00000000 : + begin + bin = 4'b0000; + i = -1; + end + 8'b00110000 : bin = 4'b0000; + 8'b00110001 : bin = 4'b0001; + 8'b00110010 : bin = 4'b0010; + 8'b00110011 : bin = 4'b0011; + 8'b00110100 : bin = 4'b0100; + 8'b00110101 : bin = 4'b0101; + 8'b00110110 : bin = 4'b0110; + 8'b00110111 : bin = 4'b0111; + 8'b00111000 : bin = 4'b1000; + 8'b00111001 : bin = 4'b1001; + 8'b01000001 : bin = 4'b1010; + 8'b01000010 : bin = 4'b1011; + 8'b01000011 : bin = 4'b1100; + 8'b01000100 : bin = 4'b1101; + 8'b01000101 : bin = 4'b1110; + 8'b01000110 : bin = 4'b1111; + 8'b01100001 : bin = 4'b1010; + 8'b01100010 : bin = 4'b1011; + 8'b01100011 : bin = 4'b1100; + 8'b01100100 : bin = 4'b1101; + 8'b01100101 : bin = 4'b1110; + 8'b01100110 : bin = 4'b1111; + default : + begin + bin = 4'bx; + end + endcase + for( j=0; j<4; j=j+1) + begin + if ((index*4)+j < C_DOUT_WIDTH) + begin + hexstr_conv[(index*4)+j] = bin[j]; + end + end + index = index + 1; + def_data = def_data >> 8; + end + end + endfunction + + /************************************************************************* + * Initialize Signals for clean power-on simulation + *************************************************************************/ + initial begin + num_wr_bits = 0; + num_rd_bits = 0; + next_num_wr_bits = 0; + next_num_rd_bits = 0; + rd_ptr = C_RD_DEPTH - 1; + wr_ptr = C_WR_DEPTH - 1; + wr_pntr = 0; + rd_pntr = 0; + rd_ptr_wrclk = rd_ptr; + wr_ptr_rdclk = wr_ptr; + dout_reset_val = hexstr_conv(C_DOUT_RST_VAL); + ideal_dout = dout_reset_val; + err_type = 0; + ideal_dout_d1 = dout_reset_val; + ideal_wr_ack = 1'b0; + ideal_valid = 1'b0; + valid_d1 = 1'b0; + ideal_overflow = 1'b0; + ideal_underflow = 1'b0; + ideal_wr_count = 0; + ideal_rd_count = 0; + ideal_prog_full = 1'b0; + ideal_prog_empty = 1'b1; + end + + + /************************************************************************* + * Connect the module inputs and outputs to the internal signals of the + * behavioral model. + *************************************************************************/ + //Inputs + /* + wire [C_DIN_WIDTH-1:0] DIN; + wire [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH; + wire [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_ASSERT; + wire [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_NEGATE; + wire [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH; + wire [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_ASSERT; + wire [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_NEGATE; + wire RD_CLK; + wire RD_EN; + wire RST; + wire WR_CLK; + wire WR_EN; + */ + + //*************************************************************************** + // Dout may change behavior based on latency + //*************************************************************************** + assign ideal_dout_out[C_DOUT_WIDTH-1:0] = (C_PRELOAD_LATENCY==2 && + (C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1))? + ideal_dout_d1: ideal_dout; + assign DOUT[C_DOUT_WIDTH-1:0] = ideal_dout_out; + + //*************************************************************************** + // Assign SBITERR and DBITERR based on latency + //*************************************************************************** + assign SBITERR = (C_ERROR_INJECTION_TYPE == 1 || C_ERROR_INJECTION_TYPE == 3) && + (C_PRELOAD_LATENCY == 2 && + (C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1)) ? + err_type_d1[0]: err_type[0]; + assign DBITERR = (C_ERROR_INJECTION_TYPE == 2 || C_ERROR_INJECTION_TYPE == 3) && + (C_PRELOAD_LATENCY==2 && (C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1)) ? + err_type_d1[1]: err_type[1]; + + + //*************************************************************************** + // Overflow may be active-low + //*************************************************************************** + generate + if (C_HAS_OVERFLOW==1) begin : blockOF1 + assign OVERFLOW = ideal_overflow ? !C_OVERFLOW_LOW : C_OVERFLOW_LOW; + end + endgenerate + + assign PROG_EMPTY = ideal_prog_empty; + assign PROG_FULL = ideal_prog_full; + + //*************************************************************************** + // Valid may change behavior based on latency or active-low + //*************************************************************************** + generate + if (C_HAS_VALID==1) begin : blockVL1 + assign valid_i = (C_PRELOAD_LATENCY==0) ? (RD_EN & ~EMPTY) : ideal_valid; + assign valid_out = (C_PRELOAD_LATENCY==2 && + (C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1))? + valid_d1: valid_i; + assign VALID = valid_out ? !C_VALID_LOW : C_VALID_LOW; + end + endgenerate + + + //*************************************************************************** + // Underflow may change behavior based on latency or active-low + //*************************************************************************** + generate + if (C_HAS_UNDERFLOW==1) begin : blockUF1 + assign underflow_i = (C_PRELOAD_LATENCY==0) ? (RD_EN & EMPTY) : ideal_underflow; + assign UNDERFLOW = underflow_i ? !C_UNDERFLOW_LOW : C_UNDERFLOW_LOW; + end + endgenerate + + //*************************************************************************** + // Write acknowledge may be active low + //*************************************************************************** + generate + if (C_HAS_WR_ACK==1) begin : blockWK1 + assign WR_ACK = ideal_wr_ack ? !C_WR_ACK_LOW : C_WR_ACK_LOW; + end + endgenerate + + + //*************************************************************************** + // Generate RD_DATA_COUNT if Use Extra Logic option is selected + //*************************************************************************** + generate + if (C_HAS_WR_DATA_COUNT == 1 && C_USE_FWFT_DATA_COUNT == 1) begin : wdc_fwft_ext + + reg [C_PNTR_WIDTH-1:0] adjusted_wr_pntr = 0; + reg [C_PNTR_WIDTH-1:0] adjusted_rd_pntr = 0; + wire [C_PNTR_WIDTH-1:0] diff_wr_rd_tmp; + wire [C_PNTR_WIDTH:0] diff_wr_rd; + reg [C_PNTR_WIDTH:0] wr_data_count_i = 0; + always @* begin + if (C_WR_PNTR_WIDTH > C_RD_PNTR_WIDTH) begin + adjusted_wr_pntr = wr_pntr; + adjusted_rd_pntr = 0; + adjusted_rd_pntr[C_PNTR_WIDTH-1:C_PNTR_WIDTH-C_RD_PNTR_WIDTH] = rd_pntr_wr; + end else if (C_WR_PNTR_WIDTH < C_RD_PNTR_WIDTH) begin + adjusted_rd_pntr = rd_pntr_wr; + adjusted_wr_pntr = 0; + adjusted_wr_pntr[C_PNTR_WIDTH-1:C_PNTR_WIDTH-C_WR_PNTR_WIDTH] = wr_pntr; + end else begin + adjusted_wr_pntr = wr_pntr; + adjusted_rd_pntr = rd_pntr_wr; + end + end // always @* + + assign diff_wr_rd_tmp = adjusted_wr_pntr - adjusted_rd_pntr; + assign diff_wr_rd = {1'b0,diff_wr_rd_tmp}; + + always @ (posedge wr_rst_i or posedge WR_CLK) + begin + if (wr_rst_i) + wr_data_count_i <= #`TCQ 0; + else + wr_data_count_i <= #`TCQ diff_wr_rd + EXTRA_WORDS_DC; + end // always @ (posedge WR_CLK or posedge WR_CLK) + + always @* begin + if (C_WR_PNTR_WIDTH >= C_RD_PNTR_WIDTH) + wdc_fwft_ext_as = wr_data_count_i[C_PNTR_WIDTH:0]; + else + wdc_fwft_ext_as = wr_data_count_i[C_PNTR_WIDTH:C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH]; + end // always @* + end // wdc_fwft_ext + endgenerate + + //*************************************************************************** + // Generate RD_DATA_COUNT if Use Extra Logic option is selected + //*************************************************************************** + reg [C_RD_PNTR_WIDTH:0] rdc_fwft_ext_as = 0; + + generate + if (C_HAS_RD_DATA_COUNT == 1 && C_USE_FWFT_DATA_COUNT == 1) begin : rdc_fwft_ext + reg [C_RD_PNTR_WIDTH-1:0] adjusted_wr_pntr_rd = 0; + wire [C_RD_PNTR_WIDTH-1:0] diff_rd_wr_tmp; + wire [C_RD_PNTR_WIDTH:0] diff_rd_wr; + always @* begin + if (C_RD_PNTR_WIDTH > C_WR_PNTR_WIDTH) begin + adjusted_wr_pntr_rd = 0; + adjusted_wr_pntr_rd[C_RD_PNTR_WIDTH-1:C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH] = wr_pntr_rd; + end else begin + adjusted_wr_pntr_rd = wr_pntr_rd[C_WR_PNTR_WIDTH-1:C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH]; + end + end // always @* + + assign diff_rd_wr_tmp = adjusted_wr_pntr_rd - rd_pntr; + assign diff_rd_wr = {1'b0,diff_rd_wr_tmp}; + + always @ (posedge rd_rst_i or posedge RD_CLK) + begin + if (rd_rst_i) begin + rdc_fwft_ext_as <= #`TCQ 0; + end else begin + if (!stage2_valid) + rdc_fwft_ext_as <= #`TCQ 0; + else if (!stage1_valid && stage2_valid) + rdc_fwft_ext_as <= #`TCQ 1; + else + rdc_fwft_ext_as <= #`TCQ diff_rd_wr + 2'h2; + end + end // always @ (posedge WR_CLK or posedge WR_CLK) + end // rdc_fwft_ext + endgenerate + + //*************************************************************************** + // Assign the read data count value only if it is selected, + // otherwise output zeros. + //*************************************************************************** + generate + if (C_HAS_RD_DATA_COUNT == 1) begin : grdc + assign RD_DATA_COUNT[C_RD_DATA_COUNT_WIDTH-1:0] = C_USE_FWFT_DATA_COUNT ? + rdc_fwft_ext_as[C_RD_PNTR_WIDTH:C_RD_PNTR_WIDTH+1-C_RD_DATA_COUNT_WIDTH] : + rd_data_count_int[C_RD_PNTR_WIDTH:C_RD_PNTR_WIDTH+1-C_RD_DATA_COUNT_WIDTH]; + end + endgenerate + + generate + if (C_HAS_RD_DATA_COUNT == 0) begin : gnrdc + assign RD_DATA_COUNT[C_RD_DATA_COUNT_WIDTH-1:0] = {C_RD_DATA_COUNT_WIDTH-1{1'b0}}; + end + endgenerate + + //*************************************************************************** + // Assign the write data count value only if it is selected, + // otherwise output zeros + //*************************************************************************** + generate + if (C_HAS_WR_DATA_COUNT == 1) begin : gwdc + assign WR_DATA_COUNT[C_WR_DATA_COUNT_WIDTH-1:0] = (C_USE_FWFT_DATA_COUNT == 1) ? + wdc_fwft_ext_as[C_WR_PNTR_WIDTH:C_WR_PNTR_WIDTH+1-C_WR_DATA_COUNT_WIDTH] : + wr_data_count_int[C_WR_PNTR_WIDTH:C_WR_PNTR_WIDTH+1-C_WR_DATA_COUNT_WIDTH]; + end + endgenerate + + generate + if (C_HAS_WR_DATA_COUNT == 0) begin : gnwdc + assign WR_DATA_COUNT[C_WR_DATA_COUNT_WIDTH-1:0] = {C_WR_DATA_COUNT_WIDTH-1{1'b0}}; + end + endgenerate + + + /************************************************************************** + * Assorted registers for delayed versions of signals + **************************************************************************/ + //Capture delayed version of valid + generate + if (C_HAS_VALID==1) begin : blockVL2 + always @(posedge RD_CLK or posedge rd_rst_i) begin + if (rd_rst_i == 1'b1) begin + valid_d1 <= #`TCQ 1'b0; + end else begin + valid_d1 <= #`TCQ valid_i; + end + end + end + endgenerate + + //Capture delayed version of dout + always @(posedge RD_CLK or posedge rd_rst_i) begin + if (rd_rst_i == 1'b1) begin + // Reset err_type only if ECC is not selected + if (C_USE_ECC == 0) + err_type_d1 <= #`TCQ 0; + end else if (ram_rd_en_d1) begin + ideal_dout_d1 <= #`TCQ ideal_dout; + err_type_d1 <= #`TCQ err_type; + end + end + + /************************************************************************** + * Overflow and Underflow Flag calculation + * (handled separately because they don't support rst) + **************************************************************************/ + generate + if (C_HAS_OVERFLOW==1) begin : blockOF2 + always @(posedge WR_CLK) begin + ideal_overflow <= #`TCQ WR_EN & FULL; + end + end + endgenerate + + generate + if (C_HAS_UNDERFLOW==1) begin : blockUF2 + always @(posedge RD_CLK) begin + ideal_underflow <= #`TCQ EMPTY & RD_EN; + end + end + endgenerate + + /************************************************************************** + * Write Domain Logic + **************************************************************************/ + reg [C_WR_PNTR_WIDTH-1:0] diff_pntr = 0; + always @(posedge WR_CLK or posedge wr_rst_i) begin : gen_fifo_w + + /****** Reset fifo (case 1)***************************************/ + if (wr_rst_i == 1'b1) begin + num_wr_bits <= #`TCQ 0; + next_num_wr_bits = #`TCQ 0; + wr_ptr <= #`TCQ C_WR_DEPTH - 1; + rd_ptr_wrclk <= #`TCQ C_RD_DEPTH - 1; + ideal_wr_ack <= #`TCQ 0; + ideal_wr_count <= #`TCQ 0; + tmp_wr_listsize = #`TCQ 0; + rd_ptr_wrclk_next <= #`TCQ 0; + wr_pntr <= #`TCQ 0; + wr_pntr_rd1 <= #`TCQ 0; + rd_pntr_wr2 <= #`TCQ 0; + rd_pntr_wr3 <= #`TCQ 0; + rd_pntr_wr4 <= #`TCQ 0; + rd_pntr_wr <= #`TCQ 0; + + + end else begin //wr_rst_i==0 + + wr_pntr_rd1 <= #`TCQ wr_pntr; + + // Synchronize the rd_pntr in read domain + rd_pntr_wr2 <= #`TCQ rd_pntr_wr1; + rd_pntr_wr3 <= #`TCQ rd_pntr_wr2; + rd_pntr_wr4 <= #`TCQ rd_pntr_wr2; + rd_pntr_wr <= #`TCQ rd_pntr_wr4; + + + + //Determine the current number of words in the FIFO + tmp_wr_listsize = (C_DEPTH_RATIO_RD > 1) ? num_wr_bits/C_DOUT_WIDTH : + num_wr_bits/C_DIN_WIDTH; + rd_ptr_wrclk_next = rd_ptr; + if (rd_ptr_wrclk < rd_ptr_wrclk_next) begin + next_num_wr_bits = num_wr_bits - + C_DOUT_WIDTH*(rd_ptr_wrclk + C_RD_DEPTH + - rd_ptr_wrclk_next); + end else begin + next_num_wr_bits = num_wr_bits - + C_DOUT_WIDTH*(rd_ptr_wrclk - rd_ptr_wrclk_next); + end + + //If this is a write, handle the write by adding the value + // to the linked list, and updating all outputs appropriately + if (WR_EN == 1'b1) begin + if (FULL == 1'b1) begin + + //If the FIFO is full, do NOT perform the write, + // update flags accordingly + if ((tmp_wr_listsize + C_DEPTH_RATIO_RD - 1)/C_DEPTH_RATIO_RD + >= C_FIFO_WR_DEPTH) begin + //write unsuccessful - do not change contents + + //Do not acknowledge the write + ideal_wr_ack <= #`TCQ 0; + //Reminder that FIFO is still full + + ideal_wr_count <= #`TCQ num_write_words_sized_i; + + //If the FIFO is one from full, but reporting full + end else + if ((tmp_wr_listsize + C_DEPTH_RATIO_RD - 1)/C_DEPTH_RATIO_RD == + C_FIFO_WR_DEPTH-1) begin + //No change to FIFO + + //Write not successful + ideal_wr_ack <= #`TCQ 0; + //With DEPTH-1 words in the FIFO, it is almost_full + + ideal_wr_count <= #`TCQ num_write_words_sized_i; + + + //If the FIFO is completely empty, but it is + // reporting FULL for some reason (like reset) + end else + if ((tmp_wr_listsize + C_DEPTH_RATIO_RD - 1)/C_DEPTH_RATIO_RD <= + C_FIFO_WR_DEPTH-2) begin + //No change to FIFO + + //Write not successful + ideal_wr_ack <= #`TCQ 0; + //FIFO is really not close to full, so change flag status. + + ideal_wr_count <= #`TCQ num_write_words_sized_i; + end //(tmp_wr_listsize == 0) + + end else begin + + //If the FIFO is full, do NOT perform the write, + // update flags accordingly + if ((tmp_wr_listsize + C_DEPTH_RATIO_RD - 1)/C_DEPTH_RATIO_RD >= + C_FIFO_WR_DEPTH) begin + //write unsuccessful - do not change contents + + //Do not acknowledge the write + ideal_wr_ack <= #`TCQ 0; + //Reminder that FIFO is still full + + ideal_wr_count <= #`TCQ num_write_words_sized_i; + + //If the FIFO is one from full + end else + if ((tmp_wr_listsize + C_DEPTH_RATIO_RD - 1)/C_DEPTH_RATIO_RD == + C_FIFO_WR_DEPTH-1) begin + //Add value on DIN port to FIFO + write_fifo; + next_num_wr_bits = next_num_wr_bits + C_DIN_WIDTH; + + //Write successful, so issue acknowledge + // and no error + ideal_wr_ack <= #`TCQ 1; + //This write is CAUSING the FIFO to go full + + ideal_wr_count <= #`TCQ num_write_words_sized_i; + + //If the FIFO is 2 from full + end else + if ((tmp_wr_listsize + C_DEPTH_RATIO_RD - 1)/C_DEPTH_RATIO_RD == + C_FIFO_WR_DEPTH-2) begin + //Add value on DIN port to FIFO + write_fifo; + next_num_wr_bits = next_num_wr_bits + C_DIN_WIDTH; + //Write successful, so issue acknowledge + // and no error + ideal_wr_ack <= #`TCQ 1; + //Still 2 from full + + ideal_wr_count <= #`TCQ num_write_words_sized_i; + + //If the FIFO is not close to being full + end else + if ((tmp_wr_listsize + C_DEPTH_RATIO_RD - 1)/C_DEPTH_RATIO_RD < + C_FIFO_WR_DEPTH-2) begin + //Add value on DIN port to FIFO + write_fifo; + next_num_wr_bits = next_num_wr_bits + C_DIN_WIDTH; + //Write successful, so issue acknowledge + // and no error + ideal_wr_ack <= #`TCQ 1; + //Not even close to full. + + ideal_wr_count <= num_write_words_sized_i; + + end + + end + + end else begin //(WR_EN == 1'b1) + + //If user did not attempt a write, then do not + // give ack or err + ideal_wr_ack <= #`TCQ 0; + ideal_wr_count <= #`TCQ num_write_words_sized_i; + end + num_wr_bits <= #`TCQ next_num_wr_bits; + rd_ptr_wrclk <= #`TCQ rd_ptr; + + end //wr_rst_i==0 + end // write always + + + /*************************************************************************** + * Programmable FULL flags + ***************************************************************************/ + + always @(posedge WR_CLK or posedge RST_FULL_FF) begin : gen_pf + + if (RST_FULL_FF == 1'b1) begin + diff_pntr <= 0; + ideal_prog_full <= #`TCQ C_FULL_FLAGS_RST_VAL; + end else begin + if (ram_wr_en) + diff_pntr <= #`TCQ (wr_pntr - adj_rd_pntr_wr + 2'h1); + else if (!ram_wr_en) + diff_pntr <= #`TCQ (wr_pntr - adj_rd_pntr_wr); + + if (RST_FULL_GEN) + ideal_prog_full <= #`TCQ 0; + //Single Programmable Full Constant Threshold + else if (C_PROG_FULL_TYPE == 1) begin + if (FULL == 0) begin + if (diff_pntr >= C_PROG_FULL_THRESH_ASSERT_VAL) + ideal_prog_full <= #`TCQ 1; + else + ideal_prog_full <= #`TCQ 0; + end else + ideal_prog_full <= #`TCQ ideal_prog_full; + //Two Programmable Full Constant Thresholds + end else if (C_PROG_FULL_TYPE == 2) begin + if (FULL == 0) begin + if (diff_pntr >= C_PROG_FULL_THRESH_ASSERT_VAL) + ideal_prog_full <= #`TCQ 1; + else if (diff_pntr < C_PROG_FULL_THRESH_NEGATE_VAL) + ideal_prog_full <= #`TCQ 0; + else + ideal_prog_full <= #`TCQ ideal_prog_full; + end else + ideal_prog_full <= #`TCQ ideal_prog_full; + //Single Programmable Full Threshold Input + end else if (C_PROG_FULL_TYPE == 3) begin + if (FULL == 0) begin + if (diff_pntr >= PROG_FULL_THRESH) + ideal_prog_full <= #`TCQ 1; + else + ideal_prog_full <= #`TCQ 0; + end else + ideal_prog_full <= #`TCQ ideal_prog_full; + //Two Programmable Full Threshold Inputs + end else if (C_PROG_FULL_TYPE == 4) begin + if (FULL == 0) begin + if (diff_pntr >= PROG_FULL_THRESH_ASSERT) + ideal_prog_full <= #`TCQ 1; + else if (diff_pntr < PROG_FULL_THRESH_NEGATE) + ideal_prog_full <= #`TCQ 0; + else + ideal_prog_full <= #`TCQ ideal_prog_full; + end else + ideal_prog_full <= #`TCQ ideal_prog_full; + end // C_PROG_FULL_TYPE + + end //wr_rst_i==0 + end // + + + /************************************************************************** + * Read Domain Logic + **************************************************************************/ + + + /********************************************************* + * Programmable EMPTY flags + *********************************************************/ + //Determine the Assert and Negate thresholds for Programmable Empty + + reg [C_RD_PNTR_WIDTH-1:0] pe_thr_assert_val = 0; + reg [C_RD_PNTR_WIDTH-1:0] pe_thr_negate_val = 0; + reg [C_RD_PNTR_WIDTH-1:0] diff_pntr_rd = 0; + always @* begin + + if (C_PROG_EMPTY_TYPE == 3) begin + + // If empty input threshold is selected, then subtract 2 for FWFT to + // compensate the FWFT stage, otherwise assign the input value. + if (C_PRELOAD_REGS == 1 && C_PRELOAD_LATENCY == 0) // FWFT + pe_thr_assert_val <= PROG_EMPTY_THRESH - 2'h2; + else + pe_thr_assert_val <= PROG_EMPTY_THRESH; + + end else if (C_PROG_EMPTY_TYPE == 4) begin + + // If empty input threshold is selected, then subtract 2 for FWFT to + // compensate the FWFT stage, otherwise assign the input value. + if (C_PRELOAD_REGS == 1 && C_PRELOAD_LATENCY == 0) begin // FWFT + pe_thr_assert_val <= PROG_EMPTY_THRESH_ASSERT - 2'h2; + pe_thr_negate_val <= PROG_EMPTY_THRESH_NEGATE - 2'h2; + end else begin + pe_thr_assert_val <= PROG_EMPTY_THRESH_ASSERT; + pe_thr_negate_val <= PROG_EMPTY_THRESH_NEGATE; + end + end else begin + + if (C_PRELOAD_REGS == 1 && C_PRELOAD_LATENCY == 0) begin // FWFT + pe_thr_assert_val <= C_PROG_EMPTY_THRESH_ASSERT_VAL - 2; + pe_thr_negate_val <= C_PROG_EMPTY_THRESH_NEGATE_VAL - 2; + end else begin + pe_thr_assert_val <= C_PROG_EMPTY_THRESH_ASSERT_VAL; + pe_thr_negate_val <= C_PROG_EMPTY_THRESH_NEGATE_VAL; + end + end + end // always @* + + always @(posedge RD_CLK or posedge rd_rst_i) begin : gen_pe + + if (rd_rst_i) begin + diff_pntr_rd <= #`TCQ 0; + ideal_prog_empty <= #`TCQ 1'b1; + end else begin + if (ram_rd_en) + diff_pntr_rd <= #`TCQ (adj_wr_pntr_rd - rd_pntr) - 1'h1; + else if (!ram_rd_en) + diff_pntr_rd <= #`TCQ (adj_wr_pntr_rd - rd_pntr); + else + diff_pntr_rd <= #`TCQ diff_pntr_rd; + + if (C_PROG_EMPTY_TYPE == 1) begin + if (EMPTY == 0) begin + if (diff_pntr_rd <= pe_thr_assert_val) + ideal_prog_empty <= #`TCQ 1; + else + ideal_prog_empty <= #`TCQ 0; + end else + ideal_prog_empty <= #`TCQ ideal_prog_empty; + end else if (C_PROG_EMPTY_TYPE == 2) begin + if (EMPTY == 0) begin + if (diff_pntr_rd <= pe_thr_assert_val) + ideal_prog_empty <= #`TCQ 1; + else if (diff_pntr_rd > pe_thr_negate_val) + ideal_prog_empty <= #`TCQ 0; + else + ideal_prog_empty <= #`TCQ ideal_prog_empty; + end else + ideal_prog_empty <= #`TCQ ideal_prog_empty; + end else if (C_PROG_EMPTY_TYPE == 3) begin + if (EMPTY == 0) begin + if (diff_pntr_rd <= pe_thr_assert_val) + ideal_prog_empty <= #`TCQ 1; + else + ideal_prog_empty <= #`TCQ 0; + end else + ideal_prog_empty <= #`TCQ ideal_prog_empty; + end else if (C_PROG_EMPTY_TYPE == 4) begin + if (EMPTY == 0) begin + if (diff_pntr_rd >= pe_thr_assert_val) + ideal_prog_empty <= #`TCQ 1; + else if (diff_pntr_rd > pe_thr_negate_val) + ideal_prog_empty <= #`TCQ 0; + else + ideal_prog_empty <= #`TCQ ideal_prog_empty; + end else + ideal_prog_empty <= #`TCQ ideal_prog_empty; + end //C_PROG_EMPTY_TYPE + end + end + + // block memory has a synchronous reset + always @(posedge RD_CLK) begin : gen_fifo_blkmemdout + // make it consistent with the core. + if (rd_rst_i) begin + // Reset err_type only if ECC is not selected + if (C_USE_ECC == 0 && C_MEMORY_TYPE < 2) + err_type <= #`TCQ 0; + + // BRAM resets synchronously + if (C_USE_DOUT_RST == 1 && C_MEMORY_TYPE < 2) begin + ideal_dout <= #`TCQ dout_reset_val; + ideal_dout_d1 <= #`TCQ dout_reset_val; + end + end + end //always + + always @(posedge RD_CLK or posedge rd_rst_i) begin : gen_fifo_r + + /****** Reset fifo (case 1)***************************************/ + if (rd_rst_i) begin + num_rd_bits <= #`TCQ 0; + next_num_rd_bits = #`TCQ 0; + rd_ptr <= #`TCQ C_RD_DEPTH -1; + rd_pntr <= #`TCQ 0; + rd_pntr_wr1 <= #`TCQ 0; + wr_pntr_rd2 <= #`TCQ 0; + wr_pntr_rd3 <= #`TCQ 0; + wr_pntr_rd <= #`TCQ 0; + wr_ptr_rdclk <= #`TCQ C_WR_DEPTH -1; + + // DRAM resets asynchronously + if (C_MEMORY_TYPE == 2 && C_USE_DOUT_RST == 1) + ideal_dout <= #`TCQ dout_reset_val; + + // Reset err_type only if ECC is not selected + if (C_USE_ECC == 0) + err_type <= #`TCQ 0; + ideal_valid <= #`TCQ 1'b0; + ideal_rd_count <= #`TCQ 0; + + end else begin //rd_rst_i==0 + + rd_pntr_wr1 <= #`TCQ rd_pntr; + + // Synchronize the wr_pntr in read domain + wr_pntr_rd2 <= #`TCQ wr_pntr_rd1; + wr_pntr_rd3 <= #`TCQ wr_pntr_rd2; + wr_pntr_rd <= #`TCQ wr_pntr_rd3; + + + + //Determine the current number of words in the FIFO + tmp_rd_listsize = (C_DEPTH_RATIO_WR > 1) ? num_rd_bits/C_DIN_WIDTH : + num_rd_bits/C_DOUT_WIDTH; + wr_ptr_rdclk_next = wr_ptr; + + if (wr_ptr_rdclk < wr_ptr_rdclk_next) begin + next_num_rd_bits = num_rd_bits + + C_DIN_WIDTH*(wr_ptr_rdclk +C_WR_DEPTH + - wr_ptr_rdclk_next); + end else begin + next_num_rd_bits = num_rd_bits + + C_DIN_WIDTH*(wr_ptr_rdclk - wr_ptr_rdclk_next); + end + + /*****************************************************************/ + // Read Operation - Read Latency 1 + /*****************************************************************/ + if (C_PRELOAD_LATENCY==1 || C_PRELOAD_LATENCY==2) begin + ideal_valid <= #`TCQ 1'b0; + + if (ram_rd_en == 1'b1) begin + + if (EMPTY == 1'b1) begin + + //If the FIFO is completely empty, and is reporting empty + if (tmp_rd_listsize/C_DEPTH_RATIO_WR <= 0) + begin + //Do not change the contents of the FIFO + + //Do not acknowledge the read from empty FIFO + ideal_valid <= #`TCQ 1'b0; + //Reminder that FIFO is still empty + + ideal_rd_count <= #`TCQ num_read_words_sized_i; + end // if (tmp_rd_listsize <= 0) + + //If the FIFO is one from empty, but it is reporting empty + else if (tmp_rd_listsize/C_DEPTH_RATIO_WR == 1) + begin + //Do not change the contents of the FIFO + + //Do not acknowledge the read from empty FIFO + ideal_valid <= #`TCQ 1'b0; + //Note that FIFO is no longer empty, but is almost empty (has one word left) + + ideal_rd_count <= #`TCQ num_read_words_sized_i; + + end // if (tmp_rd_listsize == 1) + + //If the FIFO is two from empty, and is reporting empty + else if (tmp_rd_listsize/C_DEPTH_RATIO_WR == 2) + begin + //Do not change the contents of the FIFO + + //Do not acknowledge the read from empty FIFO + ideal_valid <= #`TCQ 1'b0; + //Fifo has two words, so is neither empty or almost empty + + ideal_rd_count <= #`TCQ num_read_words_sized_i; + + end // if (tmp_rd_listsize == 2) + + //If the FIFO is not close to empty, but is reporting that it is + // Treat the FIFO as empty this time, but unset EMPTY flags. + if ((tmp_rd_listsize/C_DEPTH_RATIO_WR > 2) && (tmp_rd_listsize/C_DEPTH_RATIO_WR 2) && (tmp_rd_listsize<=C_FIFO_RD_DEPTH-1)) + end // else: if(ideal_empty == 1'b1) + + else //if (ideal_empty == 1'b0) + begin + + //If the FIFO is completely full, and we are successfully reading from it + if (tmp_rd_listsize/C_DEPTH_RATIO_WR >= C_FIFO_RD_DEPTH) + begin + //Read the value from the FIFO + read_fifo; + next_num_rd_bits = next_num_rd_bits - C_DOUT_WIDTH; + + //Acknowledge the read from the FIFO, no error + ideal_valid <= #`TCQ 1'b1; + //Not close to empty + + ideal_rd_count <= #`TCQ num_read_words_sized_i; + + end // if (tmp_rd_listsize == C_FIFO_RD_DEPTH) + + //If the FIFO is not close to being empty + else if ((tmp_rd_listsize/C_DEPTH_RATIO_WR > 2) && (tmp_rd_listsize/C_DEPTH_RATIO_WR<=C_FIFO_RD_DEPTH)) + begin + //Read the value from the FIFO + read_fifo; + next_num_rd_bits = next_num_rd_bits - C_DOUT_WIDTH; + + //Acknowledge the read from the FIFO, no error + ideal_valid <= #`TCQ 1'b1; + //Not close to empty + + ideal_rd_count <= #`TCQ num_read_words_sized_i; + + end // if ((tmp_rd_listsize > 2) && (tmp_rd_listsize<=C_FIFO_RD_DEPTH-1)) + + //If the FIFO is two from empty + else if (tmp_rd_listsize/C_DEPTH_RATIO_WR == 2) + begin + //Read the value from the FIFO + read_fifo; + next_num_rd_bits = next_num_rd_bits - C_DOUT_WIDTH; + + //Acknowledge the read from the FIFO, no error + ideal_valid <= #`TCQ 1'b1; + //Fifo is not yet empty. It is going almost_empty + + ideal_rd_count <= #`TCQ num_read_words_sized_i; + + end // if (tmp_rd_listsize == 2) + + //If the FIFO is one from empty + else if ((tmp_rd_listsize/C_DEPTH_RATIO_WR == 1)) + begin + //Read the value from the FIFO + read_fifo; + next_num_rd_bits = next_num_rd_bits - C_DOUT_WIDTH; + + //Acknowledge the read from the FIFO, no error + ideal_valid <= #`TCQ 1'b1; + //Note that FIFO is GOING empty + + ideal_rd_count <= #`TCQ num_read_words_sized_i; + + end // if (tmp_rd_listsize == 1) + + + //If the FIFO is completely empty + else if (tmp_rd_listsize/C_DEPTH_RATIO_WR <= 0) + begin + //Do not change the contents of the FIFO + + //Do not acknowledge the read from empty FIFO + ideal_valid <= #`TCQ 1'b0; + + ideal_rd_count <= #`TCQ num_read_words_sized_i; + + end // if (tmp_rd_listsize <= 0) + + end // if (ideal_empty == 1'b0) + + end //(RD_EN == 1'b1) + + else //if (RD_EN == 1'b0) + begin + //If user did not attempt a read, do not give an ack or err + ideal_valid <= #`TCQ 1'b0; + + ideal_rd_count <= #`TCQ num_read_words_sized_i; + + end // else: !if(RD_EN == 1'b1) + + /*****************************************************************/ + // Read Operation - Read Latency 0 + /*****************************************************************/ + end else if (C_PRELOAD_REGS==1 && C_PRELOAD_LATENCY==0) begin + ideal_valid <= #`TCQ 1'b0; + if (ram_rd_en == 1'b1) begin + + if (EMPTY == 1'b1) begin + + //If the FIFO is completely empty, and is reporting empty + if (tmp_rd_listsize/C_DEPTH_RATIO_WR <= 0) begin + //Do not change the contents of the FIFO + + //Do not acknowledge the read from empty FIFO + ideal_valid <= #`TCQ 1'b0; + //Reminder that FIFO is still empty + + ideal_rd_count <= #`TCQ num_read_words_sized_i; + + //If the FIFO is one from empty, but it is reporting empty + end else if (tmp_rd_listsize/C_DEPTH_RATIO_WR == 1) begin + //Do not change the contents of the FIFO + + //Do not acknowledge the read from empty FIFO + ideal_valid <= #`TCQ 1'b0; + //Note that FIFO is no longer empty, but is almost empty (has one word left) + + ideal_rd_count <= #`TCQ num_read_words_sized_i; + + //If the FIFO is two from empty, and is reporting empty + end else if (tmp_rd_listsize/C_DEPTH_RATIO_WR == 2) begin + //Do not change the contents of the FIFO + + //Do not acknowledge the read from empty FIFO + ideal_valid <= #`TCQ 1'b0; + //Fifo has two words, so is neither empty or almost empty + + ideal_rd_count <= #`TCQ num_read_words_sized_i; + + //If the FIFO is not close to empty, but is reporting that it is + // Treat the FIFO as empty this time, but unset EMPTY flags. + end else if ((tmp_rd_listsize/C_DEPTH_RATIO_WR > 2) && + (tmp_rd_listsize/C_DEPTH_RATIO_WR 2) && (tmp_rd_listsize<=C_FIFO_RD_DEPTH-1)) + + end else begin + + //If the FIFO is completely full, and we are successfully reading from it + if (tmp_rd_listsize/C_DEPTH_RATIO_WR >= C_FIFO_RD_DEPTH) begin + //Read the value from the FIFO + read_fifo; + next_num_rd_bits = next_num_rd_bits - C_DOUT_WIDTH; + + //Acknowledge the read from the FIFO, no error + ideal_valid <= #`TCQ 1'b1; + //Not close to empty + + ideal_rd_count <= #`TCQ num_read_words_sized_i; + + //If the FIFO is not close to being empty + end else if ((tmp_rd_listsize/C_DEPTH_RATIO_WR > 2) && + (tmp_rd_listsize/C_DEPTH_RATIO_WR<=C_FIFO_RD_DEPTH)) begin + //Read the value from the FIFO + read_fifo; + next_num_rd_bits = next_num_rd_bits - C_DOUT_WIDTH; + + //Acknowledge the read from the FIFO, no error + ideal_valid <= #`TCQ 1'b1; + //Not close to empty + + ideal_rd_count <= #`TCQ num_read_words_sized_i; + + //If the FIFO is two from empty + end else if (tmp_rd_listsize/C_DEPTH_RATIO_WR == 2) begin + //Read the value from the FIFO + read_fifo; + next_num_rd_bits = next_num_rd_bits - C_DOUT_WIDTH; + + //Acknowledge the read from the FIFO, no error + ideal_valid <= #`TCQ 1'b1; + //Fifo is not yet empty. It is going almost_empty + + ideal_rd_count <= #`TCQ num_read_words_sized_i; + + //If the FIFO is one from empty + end else if (tmp_rd_listsize/C_DEPTH_RATIO_WR == 1) begin + //Read the value from the FIFO + read_fifo; + next_num_rd_bits = next_num_rd_bits - C_DOUT_WIDTH; + + //Acknowledge the read from the FIFO, no error + ideal_valid <= #`TCQ 1'b1; + //Note that FIFO is GOING empty + + ideal_rd_count <= #`TCQ num_read_words_sized_i; + + //If the FIFO is completely empty + end else if (tmp_rd_listsize/C_DEPTH_RATIO_WR <= 0) begin + //Do not change the contents of the FIFO + + //Do not acknowledge the read from empty FIFO + ideal_valid <= #`TCQ 1'b0; + //Reminder that FIFO is still empty + + ideal_rd_count <= #`TCQ num_read_words_sized_i; + + end // if (tmp_rd_listsize <= 0) + + end // if (ideal_empty == 1'b0) + + end else begin//(RD_EN == 1'b0) + + + //If user did not attempt a read, do not give an ack or err + ideal_valid <= #`TCQ 1'b0; + ideal_rd_count <= #`TCQ num_read_words_sized_i; + + end // else: !if(RD_EN == 1'b1) + end //if (C_PRELOAD_REGS==1 && C_PRELOAD_LATENCY==0) + + num_rd_bits <= #`TCQ next_num_rd_bits; + wr_ptr_rdclk <= #`TCQ wr_ptr; + end //rd_rst_i==0 + end //always + +endmodule // fifo_generator_v6_1_bhv_ver_as + + +/******************************************************************************* + * Declaration of top-level module + ******************************************************************************/ +module fifo_generator_v6_1_bhv_ver_ss + + /************************************************************************** + * Declare user parameters and their defaults + *************************************************************************/ + #( + parameter C_DATA_COUNT_WIDTH = 2, + parameter C_DIN_WIDTH = 8, + parameter C_DOUT_RST_VAL = "", + parameter C_DOUT_WIDTH = 8, + parameter C_FULL_FLAGS_RST_VAL = 1, + parameter C_HAS_ALMOST_EMPTY = 0, + parameter C_HAS_ALMOST_FULL = 0, + parameter C_HAS_DATA_COUNT = 0, + parameter C_HAS_OVERFLOW = 0, + parameter C_HAS_RD_DATA_COUNT = 0, + parameter C_HAS_RST = 0, + parameter C_HAS_SRST = 0, + parameter C_HAS_UNDERFLOW = 0, + parameter C_HAS_VALID = 0, + parameter C_HAS_WR_ACK = 0, + parameter C_HAS_WR_DATA_COUNT = 0, + parameter C_IMPLEMENTATION_TYPE = 0, + parameter C_MEMORY_TYPE = 1, + parameter C_OVERFLOW_LOW = 0, + parameter C_PRELOAD_LATENCY = 1, + parameter C_PRELOAD_REGS = 0, + parameter C_PROG_EMPTY_THRESH_ASSERT_VAL = 0, + parameter C_PROG_EMPTY_THRESH_NEGATE_VAL = 0, + parameter C_PROG_EMPTY_TYPE = 0, + parameter C_PROG_FULL_THRESH_ASSERT_VAL = 0, + parameter C_PROG_FULL_THRESH_NEGATE_VAL = 0, + parameter C_PROG_FULL_TYPE = 0, + parameter C_RD_DATA_COUNT_WIDTH = 2, + parameter C_RD_DEPTH = 256, + parameter C_RD_PNTR_WIDTH = 8, + parameter C_UNDERFLOW_LOW = 0, + parameter C_USE_DOUT_RST = 0, + parameter C_USE_EMBEDDED_REG = 0, + parameter C_USE_FWFT_DATA_COUNT = 0, + parameter C_VALID_LOW = 0, + parameter C_WR_ACK_LOW = 0, + parameter C_WR_DATA_COUNT_WIDTH = 2, + parameter C_WR_DEPTH = 256, + parameter C_WR_PNTR_WIDTH = 8, + parameter C_USE_ECC = 0, + parameter C_ENABLE_RST_SYNC = 1, + parameter C_ERROR_INJECTION_TYPE = 0 + ) + + /************************************************************************** + * Declare Input and Output Ports + *************************************************************************/ + ( + //Inputs + input CLK, + input [C_DIN_WIDTH-1:0] DIN, + input [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH, + input [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_ASSERT, + input [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_NEGATE, + input [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH, + input [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_ASSERT, + input [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_NEGATE, + input RD_EN, + input RST, + input RST_FULL_GEN, + input RST_FULL_FF, + input SRST, + input WR_EN, + input INJECTDBITERR, + input INJECTSBITERR, + + //Outputs + output ALMOST_EMPTY, + output ALMOST_FULL, + output reg [C_DATA_COUNT_WIDTH-1:0] DATA_COUNT, + output [C_DOUT_WIDTH-1:0] DOUT, + output EMPTY, + output FULL, + output OVERFLOW, + output PROG_EMPTY, + output PROG_FULL, + output VALID, + output UNDERFLOW, + output WR_ACK, + output SBITERR, + output DBITERR + ); + + + /*************************************************************************** + * Parameters used as constants + **************************************************************************/ + //When RST is present, set FULL reset value to '1'. + //If core has no RST, make sure FULL powers-on as '0'. + //The reset value assignments for FULL, ALMOST_FULL, and PROG_FULL are not + //changed for v3.2(IP2_Im). When the core has Sync Reset, C_HAS_SRST=1 and C_HAS_RST=0. + // Therefore, during SRST, all the FULL flags reset to 0. + parameter C_HAS_FAST_FIFO = 0; + parameter C_FIFO_WR_DEPTH = C_WR_DEPTH; + parameter C_FIFO_RD_DEPTH = C_RD_DEPTH; + + /************************************************************************** + * FIFO Contents Tracking and Data Count Calculations + *************************************************************************/ + // Memory which will be used to simulate a FIFO + reg [C_DIN_WIDTH-1:0] memory[C_WR_DEPTH-1:0]; + // Local parameters used to determine whether to inject ECC error or not + localparam SYMMETRIC_PORT = (C_DIN_WIDTH == C_DOUT_WIDTH) ? 1 : 0; + localparam ERR_INJECTION = (C_ERROR_INJECTION_TYPE != 0) ? 1 : 0; + localparam ENABLE_ERR_INJECTION = C_USE_ECC && SYMMETRIC_PORT && ERR_INJECTION; + // Array that holds the error injection type (single/double bit error) on + // a specific write operation, which is returned on read to corrupt the + // output data. + reg [1:0] ecc_err[C_WR_DEPTH-1:0]; + + //The amount of data stored in the FIFO at any time is given + // by num_bits. + //num_bits is calculated by from the total words in the FIFO. + reg [31:0] num_bits; + + //The write pointer - tracks write operations + // (Works opposite to core: wr_ptr is a DOWN counter) + reg [31:0] wr_ptr; + + //The write pointer - tracks read operations + // (Works opposite to core: rd_ptr is a DOWN counter) + reg [31:0] rd_ptr; + + /************************** + * Data Count + *************************/ + //Amount of data stored in the FIFO scaled to read words + wire [31:0] num_read_words = num_bits/C_DOUT_WIDTH; + //num_read_words delayed 1 clock cycle + reg [31:0] num_read_words_q; + + //Amount of data stored in the FIFO scaled to write words + wire [31:0] num_write_words = num_bits/C_DIN_WIDTH; + //num_write_words delayed 1 clock cycle + reg [31:0] num_write_words_q; + + + /************************************************************************** + * Internal Registers and wires + *************************************************************************/ + + //Temporary signals used for calculating the model's outputs. These + //are only used in the assign statements immediately following wire, + //parameter, and function declarations. + wire underflow_i; + wire valid_i; + wire valid_out; + + //Ideal FIFO signals. These are the raw output of the behavioral model, + //which behaves like an ideal FIFO. + reg [1:0] err_type = 0; + reg [1:0] err_type_d1 = 0; + reg [C_DOUT_WIDTH-1:0] ideal_dout = 0; + reg [C_DOUT_WIDTH-1:0] ideal_dout_d1 = 0; + wire [C_DOUT_WIDTH-1:0] ideal_dout_out; + wire fwft_enabled; + reg ideal_wr_ack = 0; + reg ideal_valid = 0; + reg ideal_overflow = 0; + reg ideal_underflow = 0; + reg ideal_full = 0; + reg ideal_empty = 1; + reg ideal_almost_full = 0; + reg ideal_almost_empty = 1; + reg ideal_prog_full = 0; + reg ideal_prog_empty = 1; + + //Assorted reg values for delayed versions of signals + reg valid_d1 = 0; + reg prog_full_d = 0; + reg prog_empty_d = 1; + + wire rst_i; + wire srst_i; + + //Delayed version of RST + reg rst_q; + reg rst_qq; + + //user specified value for reseting the size of the fifo + reg [C_DOUT_WIDTH-1:0] dout_reset_val = 0; + + + /**************************************************************************** + * Function Declarations + ***************************************************************************/ + + /************************************************************************** + * write_fifo + * This task writes a word to the FIFO memory and updates the + * write pointer. + * FIFO size is relative to write domain. + ***************************************************************************/ + task write_fifo; + reg [1:0] corrupted_data; + begin + memory[wr_ptr] <= DIN; + // Store the type of error injection (double/single) on write + case (C_ERROR_INJECTION_TYPE) + 3: ecc_err[wr_ptr] <= {INJECTDBITERR,INJECTSBITERR}; + 2: ecc_err[wr_ptr] <= {INJECTDBITERR,1'b0}; + 1: ecc_err[wr_ptr] <= {1'b0,INJECTSBITERR}; + default: ecc_err[wr_ptr] <= 0; + endcase + if (wr_ptr == 0) begin + wr_ptr <= C_WR_DEPTH - 1; + end else begin + wr_ptr <= wr_ptr - 1; + end + end + endtask // write_fifo + + /************************************************************************** + * read_fifo + * This task reads a word from the FIFO memory and updates the read + * pointer. It's output is the ideal_dout bus. + * FIFO size is relative to write domain. + ***************************************************************************/ + task read_fifo; + reg [C_DOUT_WIDTH-1:0] tmp_dout; + reg [1:0] tmp_ecc_err; + begin + tmp_dout = memory[rd_ptr][C_DOUT_WIDTH-1:0]; + // Retreive the error injection type. Based on the error injection type + // corrupt the output data. + tmp_ecc_err = ecc_err[rd_ptr]; + if (ENABLE_ERR_INJECTION) begin + if (tmp_ecc_err[1]) begin // Corrupt the output data only for double bit error + if (C_DOUT_WIDTH == 1) + tmp_dout = tmp_dout[C_DOUT_WIDTH-1:0]; + else if (C_DOUT_WIDTH == 2) + tmp_dout = {~tmp_dout[C_DOUT_WIDTH-1],~tmp_dout[C_DOUT_WIDTH-2]}; + else + tmp_dout = {~tmp_dout[C_DOUT_WIDTH-1],~tmp_dout[C_DOUT_WIDTH-2],(tmp_dout << 2)}; + end else begin + tmp_dout = tmp_dout[C_DOUT_WIDTH-1:0]; + end + err_type <= {tmp_ecc_err[1], tmp_ecc_err[0] & !tmp_ecc_err[1]}; + end else begin + err_type <= 0; + end + ideal_dout <= tmp_dout; + + if (rd_ptr == 0) begin + rd_ptr <= C_RD_DEPTH - 1; + end else begin + rd_ptr <= rd_ptr - 1; + end + end + endtask + + /**************************************************************************** + * log2_val + * Returns the 'log2' value for the input value for the supported ratios + ***************************************************************************/ + function [31:0] log2_val; + input [31:0] binary_val; + + begin + if (binary_val == 8) begin + log2_val = 3; + end else if (binary_val == 4) begin + log2_val = 2; + end else begin + log2_val = 1; + end + end + endfunction + + /**************************************************************************** + * hexstr_conv + * Converts a string of type hex to a binary value (for C_DOUT_RST_VAL) + ***************************************************************************/ + function [C_DOUT_WIDTH-1:0] hexstr_conv; + input [(C_DOUT_WIDTH*8)-1:0] def_data; + + integer index,i,j; + reg [3:0] bin; + + begin + index = 0; + hexstr_conv = 'b0; + for( i=C_DOUT_WIDTH-1; i>=0; i=i-1 ) + begin + case (def_data[7:0]) + 8'b00000000 : + begin + bin = 4'b0000; + i = -1; + end + 8'b00110000 : bin = 4'b0000; + 8'b00110001 : bin = 4'b0001; + 8'b00110010 : bin = 4'b0010; + 8'b00110011 : bin = 4'b0011; + 8'b00110100 : bin = 4'b0100; + 8'b00110101 : bin = 4'b0101; + 8'b00110110 : bin = 4'b0110; + 8'b00110111 : bin = 4'b0111; + 8'b00111000 : bin = 4'b1000; + 8'b00111001 : bin = 4'b1001; + 8'b01000001 : bin = 4'b1010; + 8'b01000010 : bin = 4'b1011; + 8'b01000011 : bin = 4'b1100; + 8'b01000100 : bin = 4'b1101; + 8'b01000101 : bin = 4'b1110; + 8'b01000110 : bin = 4'b1111; + 8'b01100001 : bin = 4'b1010; + 8'b01100010 : bin = 4'b1011; + 8'b01100011 : bin = 4'b1100; + 8'b01100100 : bin = 4'b1101; + 8'b01100101 : bin = 4'b1110; + 8'b01100110 : bin = 4'b1111; + default : + begin + bin = 4'bx; + end + endcase + for( j=0; j<4; j=j+1) + begin + if ((index*4)+j < C_DOUT_WIDTH) + begin + hexstr_conv[(index*4)+j] = bin[j]; + end + end + index = index + 1; + def_data = def_data >> 8; + end + end + endfunction + + + /************************************************************************* + * Initialize Signals for clean power-on simulation + *************************************************************************/ + initial begin + num_bits = 0; + num_read_words_q = 0; + num_write_words_q = 0; + rd_ptr = C_RD_DEPTH -1; + wr_ptr = C_WR_DEPTH -1; + dout_reset_val = hexstr_conv(C_DOUT_RST_VAL); + ideal_dout = dout_reset_val; + err_type = 0; + ideal_wr_ack = 1'b0; + ideal_valid = 1'b0; + valid_d1 = 1'b0; + ideal_overflow = 1'b0; + ideal_underflow = 1'b0; + ideal_full = 1'b0; + ideal_empty = 1'b1; + ideal_almost_full = 1'b0; + ideal_almost_empty = 1'b1; + ideal_prog_full = 1'b0; + ideal_prog_empty = 1'b1; + prog_full_d = 1'b0; + prog_empty_d = 1'b1; + rst_q = 1'b0; + rst_qq = 1'b0; + end + + + /************************************************************************* + * Connect the module inputs and outputs to the internal signals of the + * behavioral model. + *************************************************************************/ + //Inputs + /* + wire CLK; + wire [C_DIN_WIDTH-1:0] DIN; + wire [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH; + wire [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_ASSERT; + wire [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_NEGATE; + wire [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH; + wire [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_ASSERT; + wire [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_NEGATE; + wire RD_EN; + wire RST; + wire WR_EN; + */ + + //Outputs + generate + if (C_HAS_ALMOST_EMPTY==1) begin : blockAE10 + assign ALMOST_EMPTY = ideal_almost_empty; + end + endgenerate + + generate + if (C_HAS_ALMOST_FULL==1) begin : blockAF10 + assign ALMOST_FULL = ideal_almost_full; + end + endgenerate + + //Dout may change behavior based on latency + assign fwft_enabled = (C_PRELOAD_LATENCY == 0 && C_PRELOAD_REGS == 1)? + 1: 0; + assign ideal_dout_out= ((C_USE_EMBEDDED_REG==1 && (fwft_enabled == 0)) && + (C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1))? + ideal_dout_d1: ideal_dout; + assign DOUT = ideal_dout_out; + + // Assign SBITERR and DBITERR based on latency + assign SBITERR = (C_ERROR_INJECTION_TYPE == 1 || C_ERROR_INJECTION_TYPE == 3) && + ((C_USE_EMBEDDED_REG==1 && (fwft_enabled == 0)) && + (C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1)) ? + err_type_d1[0]: err_type[0]; + assign DBITERR = (C_ERROR_INJECTION_TYPE == 2 || C_ERROR_INJECTION_TYPE == 3) && + ((C_USE_EMBEDDED_REG==1 && (fwft_enabled == 0)) && + (C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1)) ? + err_type_d1[1]: err_type[1]; + + assign EMPTY = ideal_empty; + assign FULL = ideal_full; + + //Overflow may be active-low + generate + if (C_HAS_OVERFLOW==1) begin : blockOF10 + assign OVERFLOW = ideal_overflow ? !C_OVERFLOW_LOW : C_OVERFLOW_LOW; + end + endgenerate + + assign PROG_EMPTY = ideal_prog_empty; + assign PROG_FULL = ideal_prog_full; + + //Valid may change behavior based on latency or active-low + generate + if (C_HAS_VALID==1) begin : blockVL10 + assign valid_i = (C_PRELOAD_LATENCY==0) ? (RD_EN & ~EMPTY) : ideal_valid; + assign valid_out = (C_PRELOAD_LATENCY==2 && + (C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1))? + valid_d1: valid_i; + assign VALID = valid_out ? !C_VALID_LOW : C_VALID_LOW; + end + endgenerate + + //Trim data count differently depending on set widths + generate + if ((C_HAS_DATA_COUNT == 1) && + (C_DATA_COUNT_WIDTH > C_RD_PNTR_WIDTH)) begin : blockDC1 + always @(num_read_words) + DATA_COUNT = num_read_words[C_RD_PNTR_WIDTH:0]; + end else if (C_HAS_DATA_COUNT == 1) begin : blockDC2 + always @(num_read_words) + DATA_COUNT = num_read_words[C_RD_PNTR_WIDTH-1:C_RD_PNTR_WIDTH-C_DATA_COUNT_WIDTH]; + end //if + endgenerate + + //Underflow may change behavior based on latency or active-low + generate + if (C_HAS_UNDERFLOW==1) begin : blockUF10 + assign underflow_i = ideal_underflow; + assign UNDERFLOW = underflow_i ? !C_UNDERFLOW_LOW : C_UNDERFLOW_LOW; + end + endgenerate + + + //Write acknowledge may be active low + generate + if (C_HAS_WR_ACK==1) begin : blockWK10 + assign WR_ACK = ideal_wr_ack ? !C_WR_ACK_LOW : C_WR_ACK_LOW; + end + endgenerate + + + /***************************************************************************** + * Internal reset logic + ****************************************************************************/ + assign srst_i = C_HAS_SRST ? SRST : 0; + assign rst_i = C_HAS_RST ? RST : 0; + + /************************************************************************** + * Assorted registers for delayed versions of signals + **************************************************************************/ + //Capture delayed version of valid + generate + if (C_HAS_VALID==1) begin : blockVL20 + always @(posedge CLK or posedge rst_i) begin + if (rst_i == 1'b1) begin + valid_d1 <= #`TCQ 1'b0; + end else begin + if (srst_i) begin + valid_d1 <= #`TCQ 1'b0; + end else begin + valid_d1 <= #`TCQ valid_i; + end + end + end // always @ (posedge CLK or posedge rst_i) + end + endgenerate + + + // block memory has a synchronous reset + always @(posedge CLK) begin : gen_fifo_blkmemdout_emb + // make it consistent with the core. + if (rst_i || srst_i) begin + // BRAM resets synchronously + if (C_USE_DOUT_RST == 1 && C_MEMORY_TYPE < 2) begin + ideal_dout_d1 <= #`TCQ dout_reset_val; + end + end + end //always + + reg ram_rd_en_d1 = 1'b0; + //Capture delayed version of dout + always @(posedge CLK or posedge rst_i) begin + if (rst_i == 1'b1) begin + // Reset err_type only if ECC is not selected + if (C_USE_ECC == 0) + err_type_d1 <= #`TCQ 0; + + // DRAM and SRAM reset asynchronously + if ((C_MEMORY_TYPE == 2 || C_MEMORY_TYPE == 3) && C_USE_DOUT_RST == 1) + ideal_dout_d1 <= #`TCQ dout_reset_val; + + ram_rd_en_d1 <= #`TCQ 1'b0; + end else begin + ram_rd_en_d1 <= #`TCQ RD_EN & !EMPTY; + if (srst_i) begin + ram_rd_en_d1 <= #`TCQ 1'b0; + // Reset err_type only if ECC is not selected + if (C_USE_ECC == 0) + err_type_d1 <= #`TCQ 0; + // Reset DRAM and SRAM based FIFO, BRAM based FIFO is reset above + if ((C_MEMORY_TYPE == 2 || C_MEMORY_TYPE == 3) && C_USE_DOUT_RST == 1) + ideal_dout_d1 <= #`TCQ dout_reset_val; + end else if (ram_rd_en_d1) begin + ideal_dout_d1 <= #`TCQ ideal_dout; + err_type_d1 <= #`TCQ err_type; + end + end + end + + /************************************************************************** + * Overflow and Underflow Flag calculation + * (handled separately because they don't support rst) + **************************************************************************/ + generate + if (C_HAS_OVERFLOW==1) begin : blockOF20 + always @(posedge CLK) begin + ideal_overflow <= #`TCQ WR_EN & ideal_full; + end + end + endgenerate + + generate + if (C_HAS_UNDERFLOW==1) begin : blockUF20 + always @(posedge CLK) begin + ideal_underflow <= #`TCQ ideal_empty & RD_EN; + end + end + endgenerate + + /************************************************************************* + * Write and Read Logic + ************************************************************************/ + always @(posedge CLK or posedge rst_i) + begin : gen_wr_ack_resp + + //Register reset + rst_q <= #`TCQ rst_i; + rst_qq <= #`TCQ rst_q; + + end // block: gen_wr_ack_resp + + // block memory has a synchronous reset + always @(posedge CLK) begin : gen_fifo_blkmemdout + //Changed the latency of during async reset to '1' instead of '2' to + // make it consistent with the core. + if (rst_i || rst_q || srst_i) begin + // Reset err_type only if ECC is not selected + if (C_USE_ECC == 0 && C_MEMORY_TYPE == 1) + err_type <= #`TCQ 0; + /******Initialize Read Domain Signals*********************************/ + if (C_USE_DOUT_RST == 1 && C_MEMORY_TYPE < 2) begin + ideal_dout <= #`TCQ dout_reset_val; + end + end + end //always + + // FULL_FLAG_RESET value given for SRST as well. + reg srst_i_d1 = 0; + reg srst_i_d2 = 0; + always @(posedge CLK or posedge RST_FULL_FF) begin : gen_fifo + + /****** Reset fifo - Asynchronous Reset**********************************/ + //Changed the latency of during async reset to '1' instead of '2' to + // make it consistent with the core. + if (RST_FULL_FF) begin //v3.2 + /******Initialize Generic FIFO constructs*****************************/ + num_bits <= #`TCQ 0; + wr_ptr <= #`TCQ C_WR_DEPTH - 1; + rd_ptr <= #`TCQ C_RD_DEPTH - 1; + num_read_words_q <= #`TCQ 0; + num_write_words_q <= #`TCQ 0; + // Reset err_type only if ECC is not selected + if (C_USE_ECC == 0 && C_MEMORY_TYPE != 1) + err_type <= #`TCQ 0; + + + /******Initialize Write Domain Signals********************************/ + ideal_wr_ack <= #`TCQ 0; + ideal_full <= #`TCQ C_FULL_FLAGS_RST_VAL; + ideal_almost_full <= #`TCQ C_FULL_FLAGS_RST_VAL; + + /******Initialize Read Domain Signals*********************************/ + // DRAM and SRAM reset asynchronously + if (C_USE_DOUT_RST == 1 && (C_MEMORY_TYPE == 2 || C_MEMORY_TYPE == 3)) begin + ideal_dout <= #`TCQ dout_reset_val; + end + ideal_valid <= #`TCQ 1'b0; + ideal_empty <= #`TCQ 1'b1; + ideal_almost_empty <= #`TCQ 1'b1; + + end else begin + // Register SRST twice to be consistant with RST behavior + srst_i_d1 <= #`TCQ srst_i; + srst_i_d2 <= #`TCQ srst_i_d1; + if (srst_i) begin + // SRST is available only for Sync BRAM, DRAM and SRAM. + if (C_MEMORY_TYPE == 1 || C_MEMORY_TYPE == 2 || C_MEMORY_TYPE == 3) begin + /******Initialize Generic FIFO constructs***********************/ + num_bits <= #`TCQ 0; + wr_ptr <= #`TCQ C_WR_DEPTH - 1; + rd_ptr <= #`TCQ C_RD_DEPTH - 1; + num_read_words_q <= #`TCQ 0; + num_write_words_q <= #`TCQ 0; + // Reset err_type only if ECC is not selected + if (C_USE_ECC == 0) + err_type <= #`TCQ 0; + + /******Initialize Write Domain Signals**************************/ + ideal_wr_ack <= #`TCQ 0; + ideal_full <= #`TCQ C_FULL_FLAGS_RST_VAL; + ideal_almost_full <= #`TCQ C_FULL_FLAGS_RST_VAL; + + /******Initialize Read Domain Signals***************************/ + //Reset DOUT of Sync DRAM/Shift RAM. Sync BRAM DOUT was reset in the + // above always block. + if (C_USE_DOUT_RST == 1 && (C_MEMORY_TYPE == 2 || C_MEMORY_TYPE == 3)) begin + ideal_dout <= #`TCQ dout_reset_val; + end + ideal_valid <= #`TCQ 1'b0; + ideal_empty <= #`TCQ 1'b1; + ideal_almost_empty <= #`TCQ 1'b1; + end + + end else if ((srst_i_d1 || srst_i_d2) && (C_FULL_FLAGS_RST_VAL == 1)) begin //Hold full flag reset value set during RST/SRST + ideal_full <= #`TCQ C_FULL_FLAGS_RST_VAL; + ideal_almost_full <= #`TCQ C_FULL_FLAGS_RST_VAL; + end else begin //normal operating conditions + /********************************************************************/ + // Synchronous FIFO Condition #1 : Writing and not reading + /********************************************************************/ + ideal_valid <= #`TCQ 1'b0; + if (WR_EN & ~RD_EN) begin + + /*********************************/ + //If the FIFO is full, do NOT perform the write, + // update flags accordingly + /*********************************/ + if (num_write_words >= C_FIFO_WR_DEPTH) begin + ideal_wr_ack <= #`TCQ 0; + + //still full + ideal_full <= #`TCQ 1'b1; + ideal_almost_full <= #`TCQ 1'b1; + + //write unsuccessful - do not change contents + + // no read attempted + ideal_valid <= #`TCQ 1'b0; + + //Not near empty + ideal_empty <= #`TCQ 1'b0; + ideal_almost_empty <= #`TCQ 1'b0; + + + /*********************************/ + //If the FIFO is reporting FULL + // (Startup condition) + /*********************************/ + end else if ((num_write_words < C_FIFO_WR_DEPTH) && (ideal_full == 1'b1)) begin + ideal_wr_ack <= #`TCQ 0; + + //still full + ideal_full <= #`TCQ 1'b0; + ideal_almost_full <= #`TCQ 1'b0; + + //write unsuccessful - do not change contents + + // no read attempted + ideal_valid <= #`TCQ 1'b0; + + //FIFO EMPTY in this state can not be determined + //ideal_empty <= 1'b0; + //ideal_almost_empty <= 1'b0; + + + /*********************************/ + //If the FIFO is one from full + /*********************************/ + end else if (num_write_words == C_FIFO_WR_DEPTH-1) begin + //good write + ideal_wr_ack <= #`TCQ 1; + + //FIFO is one from FULL and going FULL + ideal_full <= #`TCQ 1'b1; + ideal_almost_full <= #`TCQ 1'b1; + + //Add input data + write_fifo; + + // no read attempted + ideal_valid <= #`TCQ 1'b0; + + //Not near empty + ideal_empty <= #`TCQ 1'b0; + ideal_almost_empty <= #`TCQ 1'b0; + + num_bits <= num_bits + C_DIN_WIDTH; + + /*********************************/ + //If the FIFO is 2 from full + /*********************************/ + end else if (num_write_words == C_FIFO_WR_DEPTH-2) begin + //good write + ideal_wr_ack <= #`TCQ 1; + + //2 from full, and writing, so set almost_full + ideal_full <= #`TCQ 1'b0; + ideal_almost_full <= #`TCQ 1'b1; + + //Add input data + write_fifo; + + //no read attempted + ideal_valid <= #`TCQ 1'b0; + + //Not near empty + ideal_empty <= #`TCQ 1'b0; + ideal_almost_empty <= #`TCQ 1'b0; + + num_bits <= #`TCQ num_bits + C_DIN_WIDTH; + + /*********************************/ + //If the FIFO is ALMOST EMPTY + /*********************************/ + end else if (num_read_words == 1) begin + //good write + ideal_wr_ack <= #`TCQ 1; + + //Not near FULL + ideal_full <= #`TCQ 1'b0; + ideal_almost_full <= #`TCQ 1'b0; + + //Add input data + write_fifo; + + // no read attempted + ideal_valid <= #`TCQ 1'b0; + + //Leaving ALMOST_EMPTY + ideal_empty <= #`TCQ 1'b0; + ideal_almost_empty <= #`TCQ 1'b0; + + num_bits <= #`TCQ num_bits + C_DIN_WIDTH; + + /*********************************/ + //If the FIFO is EMPTY + /*********************************/ + end else if (num_read_words == 0) begin + // good write + ideal_wr_ack <= #`TCQ 1; + + //Not near FULL + ideal_full <= #`TCQ 1'b0; + ideal_almost_full <= #`TCQ 1'b0; + + //Add input data + write_fifo; + + // no read attempted + ideal_valid <= #`TCQ 1'b0; + + //Leaving EMPTY (still ALMOST_EMPTY) + ideal_empty <= #`TCQ 1'b0; + ideal_almost_empty <= #`TCQ 1'b1; + + num_bits <= #`TCQ num_bits + C_DIN_WIDTH; + + /*********************************/ + //If the FIFO is not near EMPTY or FULL + /*********************************/ + end else begin + // good write + ideal_wr_ack <= #`TCQ 1; + + //Not near FULL + ideal_full <= #`TCQ 1'b0; + ideal_almost_full <= #`TCQ 1'b0; + + //Add input data + write_fifo; + + // no read attempted + ideal_valid <= #`TCQ 1'b0; + + //Not near EMPTY + ideal_empty <= #`TCQ 1'b0; + ideal_almost_empty <= #`TCQ 1'b0; + + num_bits <= #`TCQ num_bits + C_DIN_WIDTH; + + end // average case + + + /******************************************************************/ + // Synchronous FIFO Condition #2 : Reading and not writing + /******************************************************************/ + end else if (~WR_EN & RD_EN) begin + + /*********************************/ + //If the FIFO is EMPTY + /*********************************/ + if ((num_read_words == 0) || (ideal_empty == 1'b1)) begin + //no write attemped + ideal_wr_ack <= #`TCQ 0; + + //FIFO is not near FULL + ideal_full <= #`TCQ 1'b0; + ideal_almost_full <= #`TCQ 1'b0; + + //Read will fail + ideal_valid <= #`TCQ 1'b0; + + //FIFO is still empty + ideal_empty <= #`TCQ 1'b1; + ideal_almost_empty <= #`TCQ 1'b1; + + //No read + + /*********************************/ + //If the FIFO is ALMOST EMPTY + /*********************************/ + end else if (num_read_words == 1) begin + //no write attempted + ideal_wr_ack <= #`TCQ 0; + + //FIFO is not near FULL + ideal_full <= #`TCQ 1'b0; + ideal_almost_full <= #`TCQ 1'b0; + + //Read successful + ideal_valid <= #`TCQ 1'b1; + + //This read will make FIFO go empty + ideal_empty <= #`TCQ 1'b1; + ideal_almost_empty <= #`TCQ 1'b1; + + //Get the data from the FIFO + read_fifo; + num_bits <= #`TCQ num_bits - C_DIN_WIDTH; + + + /*********************************/ + //If the FIFO is 2 from EMPTY + /*********************************/ + end else if (num_read_words == 2) begin + + //no write attempted + ideal_wr_ack <= #`TCQ 0; + + //FIFO is not near FULL + ideal_full <= #`TCQ 1'b0; + ideal_almost_full <= #`TCQ 1'b0; + + //Read successful + ideal_valid <= #`TCQ 1'b1; + + //FIFO is going ALMOST_EMPTY + ideal_empty <= #`TCQ 1'b0; + ideal_almost_empty <= #`TCQ 1'b1; + + //Get the data from the FIFO + read_fifo; + num_bits <= #`TCQ num_bits - C_DOUT_WIDTH; + + + + /*********************************/ + //If the FIFO is one from full + /*********************************/ + end else if (num_write_words == C_FIFO_WR_DEPTH-1) begin + + //no write attempted + ideal_wr_ack <= #`TCQ 0; + + //FIFO is leaving ALMOST FULL + ideal_full <= #`TCQ 1'b0; + ideal_almost_full <= #`TCQ 1'b0; + + //Read successful + ideal_valid <= #`TCQ 1'b1; + + //Not near empty + ideal_empty <= #`TCQ 1'b0; + ideal_almost_empty <= #`TCQ 1'b0; + + //Read from the FIFO + read_fifo; + num_bits <= #`TCQ num_bits - C_DOUT_WIDTH; + + + /*********************************/ + // FIFO is FULL + /*********************************/ + end else if (num_write_words >= C_FIFO_WR_DEPTH) + begin + //no write attempted + ideal_wr_ack <= #`TCQ 0; + + //FIFO is leaving FULL, but is still ALMOST_FULL + ideal_full <= #`TCQ 1'b0; + ideal_almost_full <= #`TCQ 1'b1; + + //Read successful + ideal_valid <= #`TCQ 1'b1; + + //Not near empty + ideal_empty <= #`TCQ 1'b0; + ideal_almost_empty <= #`TCQ 1'b0; + + //Read from the FIFO + read_fifo; + num_bits <= #`TCQ num_bits - C_DOUT_WIDTH; + + /*********************************/ + //If the FIFO is not near EMPTY or FULL + /*********************************/ + end else begin + //no write attemped + ideal_wr_ack <= #`TCQ 0; + + //Not near empty + ideal_full <= #`TCQ 1'b0; + ideal_almost_full <= #`TCQ 1'b0; + + //Read successful + ideal_valid <= #`TCQ 1'b1; + + //Not near empty + ideal_empty <= #`TCQ 1'b0; + ideal_almost_empty <= #`TCQ 1'b0; + + //Read from the FIFO + read_fifo; + num_bits <= #`TCQ num_bits - C_DOUT_WIDTH; + + + end // average read + + + /******************************************************************/ + // Synchronous FIFO Condition #3 : Reading and writing + /******************************************************************/ + end else if (WR_EN & RD_EN) begin + + /*********************************/ + // FIFO is FULL + /*********************************/ + if (num_write_words >= C_FIFO_WR_DEPTH) begin + + ideal_wr_ack <= #`TCQ 0; + + //Read will be successful, so FIFO will leave FULL + ideal_full <= #`TCQ 1'b0; + ideal_almost_full <= #`TCQ 1'b1; + + //Read successful + ideal_valid <= #`TCQ 1'b1; + + //Not near empty + ideal_empty <= #`TCQ 1'b0; + ideal_almost_empty <= #`TCQ 1'b0; + + //Read from the FIFO + read_fifo; + num_bits <= #`TCQ num_bits - C_DOUT_WIDTH; + + + /*********************************/ + // FIFO is reporting FULL, but it is empty + // (This is a special case, when coming out of RST + /*********************************/ + end else if ((num_write_words == 0) && (ideal_full == 1'b1)) begin + + ideal_wr_ack <= #`TCQ 0; + + //Read will be successful, so FIFO will leave FULL + ideal_full <= #`TCQ 1'b0; + ideal_almost_full <= #`TCQ 1'b0; + + //Read unsuccessful + ideal_valid <= #`TCQ 1'b0; + + //Report empty condition + ideal_empty <= #`TCQ 1'b1; + ideal_almost_empty <= #`TCQ 1'b1; + + //Do not read from empty FIFO + // Read from the FIFO + + + /*********************************/ + //If the FIFO is one from full + /*********************************/ + end else if (num_write_words == C_FIFO_WR_DEPTH-1) begin + + //Write successful + ideal_wr_ack <= #`TCQ 1; + + //FIFO will remain ALMOST_FULL + ideal_full <= #`TCQ 1'b0; + ideal_almost_full <= #`TCQ 1'b1; + + // put the data into the FIFO + write_fifo; + + //Read successful + ideal_valid <= #`TCQ 1'b1; + + //Not near empty + ideal_empty <= #`TCQ 1'b0; + ideal_almost_empty <= #`TCQ 1'b0; + + //Read from the FIFO + read_fifo; + num_bits <= #`TCQ num_bits + C_DIN_WIDTH - C_DOUT_WIDTH; + + /*********************************/ + //If the FIFO is ALMOST EMPTY + /*********************************/ + end else if (num_read_words == 1) begin + + //Write successful + ideal_wr_ack <= #`TCQ 1; + + // Not near FULL + ideal_full <= #`TCQ 1'b0; + ideal_almost_full <= #`TCQ 1'b0; + + // put the data into the FIFO + write_fifo; + + //Read successful + ideal_valid <= #`TCQ 1'b1; + + //FIFO will stay ALMOST_EMPTY + ideal_empty <= #`TCQ 1'b0; + ideal_almost_empty <= #`TCQ 1'b1; + + //Read from the FIFO + read_fifo; + num_bits <= #`TCQ num_bits + C_DIN_WIDTH - C_DOUT_WIDTH; + + + /*********************************/ + //If the FIFO is EMPTY + /*********************************/ + end else if (num_read_words == 0) begin + + //Write successful + ideal_wr_ack <= #`TCQ 1; + + // Not near FULL + ideal_full <= #`TCQ 1'b0; + ideal_almost_full <= #`TCQ 1'b0; + + // put the data into the FIFO + write_fifo; + + //Read will fail + ideal_valid <= #`TCQ 1'b0; + + //FIFO will leave EMPTY + ideal_empty <= #`TCQ 1'b0; + ideal_almost_empty <= #`TCQ 1'b1; + + // No read + num_bits <= #`TCQ num_bits + C_DIN_WIDTH; + + + /*********************************/ + //If the FIFO is not near EMPTY or FULL + /*********************************/ + end else begin + + //Write successful + ideal_wr_ack <= #`TCQ 1; + + // Not near FULL + ideal_full <= #`TCQ 1'b0; + ideal_almost_full <= #`TCQ 1'b0; + + // put the data into the FIFO + write_fifo; + + //Read successful + ideal_valid <= #`TCQ 1'b1; + + // Not near EMPTY + ideal_empty <= #`TCQ 1'b0; + ideal_almost_empty <= #`TCQ 1'b0; + + //Read from the FIFO + read_fifo; + num_bits <= #`TCQ num_bits + C_DIN_WIDTH - C_DOUT_WIDTH; + + end // average case + + /******************************************************************/ + // Synchronous FIFO Condition #4 : Not reading or writing + /******************************************************************/ + end else begin + + /*********************************/ + // FIFO is FULL + /*********************************/ + if (num_write_words >= C_FIFO_WR_DEPTH) begin + + //No write + ideal_wr_ack <= #`TCQ 0; + ideal_full <= #`TCQ 1'b1; + ideal_almost_full <= #`TCQ 1'b1; + + //No read + ideal_valid <= #`TCQ 1'b0; + ideal_empty <= #`TCQ 1'b0; + ideal_almost_empty <= #`TCQ 1'b0; + + //No change to memory + + /*********************************/ + //If the FIFO is one from full + /*********************************/ + end else if (num_write_words == C_FIFO_WR_DEPTH-1) begin + + //No write + ideal_wr_ack <= #`TCQ 0; + ideal_full <= #`TCQ 1'b0; + ideal_almost_full <= #`TCQ 1'b1; + + //No read + ideal_valid <= #`TCQ 1'b0; + ideal_empty <= #`TCQ 1'b0; + ideal_almost_empty <= #`TCQ 1'b0; + + //No change to memory + + /*********************************/ + //If the FIFO is ALMOST EMPTY + /*********************************/ + end else if (num_read_words == 1) begin + //No write + ideal_wr_ack <= #`TCQ 0; + ideal_full <= #`TCQ 1'b0; + ideal_almost_full <= #`TCQ 1'b0; + + //No read + ideal_valid <= #`TCQ 1'b0; + ideal_empty <= #`TCQ 1'b0; + ideal_almost_empty <= #`TCQ 1'b1; + + //No change to memory + + end // almost empty + + + /*********************************/ + //If the FIFO is EMPTY + /*********************************/ + else if (num_read_words == 0) + begin + //No write + ideal_wr_ack <= #`TCQ 0; + ideal_full <= #`TCQ 1'b0; + ideal_almost_full <= #`TCQ 1'b0; + + //No read + ideal_valid <= #`TCQ 1'b0; + ideal_empty <= #`TCQ 1'b1; + ideal_almost_empty <= #`TCQ 1'b1; + + //No change to memory + + /*********************************/ + //If the FIFO is not near EMPTY or FULL + /*********************************/ + end else begin + + //No write + ideal_wr_ack <= #`TCQ 0; + ideal_full <= #`TCQ 1'b0; + ideal_almost_full <= #`TCQ 1'b0; + + //No read + ideal_valid <= #`TCQ 1'b0; + ideal_empty <= #`TCQ 1'b0; + ideal_almost_empty <= #`TCQ 1'b0; + + //No change to memory + + end // average case + + end // neither reading or writing + + num_read_words_q <= #`TCQ num_read_words; + num_write_words_q <= #`TCQ num_write_words; + + end //normal operating conditions + end + + end // block: gen_fifo + + + always @(posedge CLK or posedge RST_FULL_FF) begin : gen_fifo_p + + /****** Reset fifo - Async Reset****************************************/ + //The latency of de-assertion of the flags is reduced by 1 to be + // consistent with the core. + if (RST_FULL_FF) begin + ideal_prog_full <= #`TCQ C_FULL_FLAGS_RST_VAL; + ideal_prog_empty <= #`TCQ 1'b1; + prog_full_d <= #`TCQ C_FULL_FLAGS_RST_VAL; + prog_empty_d <= #`TCQ 1'b1; + + end else begin + if (srst_i) begin + //SRST is available only for Sync BRAM and Sync DRAM. Not for SSHFT. + if (C_MEMORY_TYPE == 1 || C_MEMORY_TYPE == 2 || C_MEMORY_TYPE == 3) begin + ideal_prog_empty <= #`TCQ 1'b1; + prog_empty_d <= #`TCQ 1'b1; + ideal_prog_full <= #`TCQ C_FULL_FLAGS_RST_VAL; + prog_full_d <= #`TCQ C_FULL_FLAGS_RST_VAL; + end + end else if ((srst_i_d1 || srst_i_d2) && (C_FULL_FLAGS_RST_VAL == 1)) begin + ideal_prog_full <= #`TCQ C_FULL_FLAGS_RST_VAL; + prog_full_d <= #`TCQ C_FULL_FLAGS_RST_VAL; + end else begin + + /*************************************************************** + * Programmable FULL flags + ****************************************************************/ + //calculation for standard fifo and latency =2 + if (! (C_PRELOAD_REGS==1 && C_PRELOAD_LATENCY==0) ) begin + //Single constant threshold + if (C_PROG_FULL_TYPE == 1) begin + if ((num_write_words >= C_PROG_FULL_THRESH_ASSERT_VAL-1) + && WR_EN && !RD_EN) begin + prog_full_d <= #`TCQ 1'b1; + end else if (((num_write_words == C_PROG_FULL_THRESH_ASSERT_VAL) + && RD_EN && !WR_EN) || (RST_FULL_GEN)) begin + prog_full_d <= #`TCQ 1'b0; + end + + //Dual constant thresholds + end else if (C_PROG_FULL_TYPE == 2) begin + if ((num_write_words == C_PROG_FULL_THRESH_ASSERT_VAL-1) + && WR_EN && !RD_EN) begin + prog_full_d <= #`TCQ 1'b1; + end else if ((num_write_words == C_PROG_FULL_THRESH_NEGATE_VAL) + && RD_EN && !WR_EN) begin + prog_full_d <= #`TCQ 1'b0; + end + + //Single input threshold + end else if (C_PROG_FULL_TYPE == 3) begin + if ((num_write_words == PROG_FULL_THRESH-1) + && WR_EN && !RD_EN) begin + prog_full_d <= #`TCQ 1'b1; + end else if ((num_write_words == PROG_FULL_THRESH) + && !WR_EN && RD_EN) begin + prog_full_d <= #`TCQ 1'b0; + end else if (num_write_words >= PROG_FULL_THRESH) begin + prog_full_d <= #`TCQ 1'b1; + end else if (num_write_words < PROG_FULL_THRESH) begin + prog_full_d <= #`TCQ 1'b0; + end + + //Dual input thresholds + end else begin + if ((num_write_words == PROG_FULL_THRESH_ASSERT-1) + && WR_EN && !RD_EN) begin + prog_full_d <= #`TCQ 1'b1; + end else if ((num_write_words == PROG_FULL_THRESH_NEGATE) + && !WR_EN && RD_EN)begin + prog_full_d <= #`TCQ 1'b0; + end else if (num_write_words >= PROG_FULL_THRESH_ASSERT) begin + prog_full_d <= #`TCQ 1'b1; + end else if (num_write_words < PROG_FULL_THRESH_NEGATE) begin + prog_full_d <= #`TCQ 1'b0; + end + end + end // (~ (C_PRELOAD_REGS==1 && C_PRELOAD_LATENCY==0) ) + + + //calculation for FWFT fifo + if (C_PRELOAD_REGS==1 && C_PRELOAD_LATENCY==0) begin + if (C_PROG_FULL_TYPE == 1) begin + if ((num_write_words >= C_PROG_FULL_THRESH_ASSERT_VAL-1 - 2) + && WR_EN && !RD_EN) begin + prog_full_d <= #`TCQ 1'b1; + end else if (((num_write_words == C_PROG_FULL_THRESH_ASSERT_VAL - 2) + && RD_EN && !WR_EN) || (RST_FULL_GEN)) begin + prog_full_d <= #`TCQ 1'b0; + end + + //Dual constant thresholds + end else if (C_PROG_FULL_TYPE == 2) begin + if ((num_write_words == C_PROG_FULL_THRESH_ASSERT_VAL-1 - 2) + && WR_EN && !RD_EN) begin + prog_full_d <= #`TCQ 1'b1; + end else if ((num_write_words == C_PROG_FULL_THRESH_NEGATE_VAL - 2) + && RD_EN && !WR_EN) begin + prog_full_d <= #`TCQ 1'b0; + end + + //Single input threshold + end else if (C_PROG_FULL_TYPE == 3) begin + if ((num_write_words == PROG_FULL_THRESH-1 - 2) + && WR_EN && !RD_EN) begin + prog_full_d <= #`TCQ 1'b1; + end else if ((num_write_words == PROG_FULL_THRESH - 2) + && !WR_EN && RD_EN) begin + prog_full_d <= #`TCQ 1'b0; + end else if (num_write_words >= PROG_FULL_THRESH - 2) begin + prog_full_d <= #`TCQ 1'b1; + end else if (num_write_words < PROG_FULL_THRESH - 2) begin + prog_full_d <= #`TCQ 1'b0; + end + + //Dual input thresholds + end else begin + if ((num_write_words == PROG_FULL_THRESH_ASSERT-1 - 2) + && WR_EN && !RD_EN) begin + prog_full_d <= #`TCQ 1'b1; + end else if ((num_write_words == PROG_FULL_THRESH_NEGATE - 2) + && !WR_EN && RD_EN)begin + prog_full_d <= #`TCQ 1'b0; + end else if (num_write_words >= PROG_FULL_THRESH_ASSERT - 2) begin + prog_full_d <= #`TCQ 1'b1; + end else if (num_write_words < PROG_FULL_THRESH_NEGATE - 2) begin + prog_full_d <= #`TCQ 1'b0; + end + end + end // (C_PRELOAD_REGS==1 && C_PRELOAD_LATENCY==0) + + /***************************************************************** + * Programmable EMPTY flags + ****************************************************************/ + //calculation for standard fifo and latency = 2 + if (! (C_PRELOAD_REGS==1 && C_PRELOAD_LATENCY==0) ) begin + //Single constant threshold + if (C_PROG_EMPTY_TYPE == 1) begin + if ((num_read_words == C_PROG_EMPTY_THRESH_ASSERT_VAL+1) + && RD_EN && !WR_EN) begin + prog_empty_d <= #`TCQ 1'b1; + end else if ((num_read_words == C_PROG_EMPTY_THRESH_ASSERT_VAL) + && WR_EN && !RD_EN) begin + prog_empty_d <= #`TCQ 1'b0; + end + //Dual constant thresholds + end else if (C_PROG_EMPTY_TYPE == 2) begin + if ((num_read_words == C_PROG_EMPTY_THRESH_ASSERT_VAL+1) + && RD_EN && !WR_EN) begin + prog_empty_d <= #`TCQ 1'b1; + end else if ((num_read_words == C_PROG_EMPTY_THRESH_NEGATE_VAL) + && !RD_EN && WR_EN) begin + prog_empty_d <= #`TCQ 1'b0; + end + + //Single input threshold + end else if (C_PROG_EMPTY_TYPE == 3) begin + if ((num_read_words == PROG_EMPTY_THRESH+1) + && RD_EN && !WR_EN) begin + prog_empty_d <= #`TCQ 1'b1; + end else if ((num_read_words == PROG_EMPTY_THRESH) + && !RD_EN && WR_EN) begin + prog_empty_d <= #`TCQ 1'b0; + end else if (num_read_words <= PROG_EMPTY_THRESH) begin + prog_empty_d <= #`TCQ 1'b1; + end else if (num_read_words > PROG_EMPTY_THRESH)begin + prog_empty_d <= #`TCQ 1'b0; + end + + //Dual input thresholds + end else begin + if (num_read_words <= PROG_EMPTY_THRESH_ASSERT) begin + prog_empty_d <= #`TCQ 1'b1; + end else if ((num_read_words == PROG_EMPTY_THRESH_ASSERT+1) + && RD_EN && !WR_EN) begin + prog_empty_d <= #`TCQ 1'b1; + end else if (num_read_words > PROG_EMPTY_THRESH_NEGATE)begin + prog_empty_d <= #`TCQ 1'b0; + end else if ((num_read_words == PROG_EMPTY_THRESH_NEGATE) + && !RD_EN && WR_EN) begin + prog_empty_d <= #`TCQ 1'b0; + end + end + end // (~ (C_PRELOAD_REGS==1 && C_PRELOAD_LATENCY==0) ) + + //calculation for FWFT fifo + if (C_PRELOAD_REGS==1 && C_PRELOAD_LATENCY==0) begin + //Single constant threshold + if (C_PROG_EMPTY_TYPE == 1) begin + if ((num_read_words == C_PROG_EMPTY_THRESH_ASSERT_VAL+1 - 2) + && RD_EN && !WR_EN) begin + prog_empty_d <= #`TCQ 1'b1; + end else if ((num_read_words == C_PROG_EMPTY_THRESH_ASSERT_VAL - 2) + && WR_EN && !RD_EN) begin + prog_empty_d <= #`TCQ 1'b0; + end + //Dual constant thresholds + end else if (C_PROG_EMPTY_TYPE == 2) begin + if ((num_read_words == C_PROG_EMPTY_THRESH_ASSERT_VAL+1 - 2) + && RD_EN && !WR_EN) begin + prog_empty_d <= #`TCQ 1'b1; + end else if ((num_read_words == C_PROG_EMPTY_THRESH_NEGATE_VAL - 2) + && !RD_EN && WR_EN) begin + prog_empty_d <= #`TCQ 1'b0; + end + + //Single input threshold + end else if (C_PROG_EMPTY_TYPE == 3) begin + if ((num_read_words == PROG_EMPTY_THRESH+1 - 2) + && RD_EN && !WR_EN) begin + prog_empty_d <= #`TCQ 1'b1; + end else if ((num_read_words == PROG_EMPTY_THRESH - 2) + && !RD_EN && WR_EN) begin + prog_empty_d <= #`TCQ 1'b0; + end else if (num_read_words <= PROG_EMPTY_THRESH - 2) begin + prog_empty_d <= #`TCQ 1'b1; + end else if (num_read_words > PROG_EMPTY_THRESH - 2)begin + prog_empty_d <= #`TCQ 1'b0; + end + + //Dual input thresholds + end else begin + if (num_read_words <= PROG_EMPTY_THRESH_ASSERT - 2) begin + prog_empty_d <= #`TCQ 1'b1; + end else if ((num_read_words == PROG_EMPTY_THRESH_ASSERT+1 - 2) + && RD_EN && !WR_EN) begin + prog_empty_d <= #`TCQ 1'b1; + end else if (num_read_words > PROG_EMPTY_THRESH_NEGATE - 2)begin + prog_empty_d <= #`TCQ 1'b0; + end else if ((num_read_words == PROG_EMPTY_THRESH_NEGATE - 2) + && !RD_EN && WR_EN) begin + prog_empty_d <= #`TCQ 1'b0; + end + end + end // (~ (C_PRELOAD_REGS==1 && C_PRELOAD_LATENCY==0) ) + + ideal_prog_empty <= prog_empty_d; + if (RST_FULL_GEN) begin + ideal_prog_full <= #`TCQ 1'b0; + prog_full_d <= #`TCQ 1'b0; + end else begin + ideal_prog_full <= #`TCQ prog_full_d; + end + + end //if (srst_i) begin + end //if (rst_i) begin + end //always @(posedge CLK or posedge rst_i) begin : gen_fifo_p +endmodule // fifo_generator_v6_1_bhv_ver_ss + + + +/************************************************************************** + * First-Word Fall-Through module (preload 0) + **************************************************************************/ +module fifo_generator_v6_1_bhv_ver_preload0 + ( + RD_CLK, + RD_RST, + SRST, + RD_EN, + FIFOEMPTY, + FIFODATA, + FIFOSBITERR, + FIFODBITERR, + USERDATA, + USERVALID, + USERUNDERFLOW, + USEREMPTY, + USERALMOSTEMPTY, + RAMVALID, + FIFORDEN, + USERSBITERR, + USERDBITERR + ); + + parameter C_DOUT_RST_VAL = ""; + parameter C_DOUT_WIDTH = 8; + parameter C_HAS_RST = 0; + parameter C_ENABLE_RST_SYNC = 0; + parameter C_HAS_SRST = 0; + parameter C_USE_DOUT_RST = 0; + parameter C_USE_ECC = 0; + parameter C_USERVALID_LOW = 0; + parameter C_USERUNDERFLOW_LOW = 0; + parameter C_MEMORY_TYPE = 0; + + //Inputs + input RD_CLK; + input RD_RST; + input SRST; + input RD_EN; + input FIFOEMPTY; + input [C_DOUT_WIDTH-1:0] FIFODATA; + input FIFOSBITERR; + input FIFODBITERR; + + //Outputs + output [C_DOUT_WIDTH-1:0] USERDATA; + output USERVALID; + output USERUNDERFLOW; + output USEREMPTY; + output USERALMOSTEMPTY; + output RAMVALID; + output FIFORDEN; + output USERSBITERR; + output USERDBITERR; + + //Inputs + wire RD_CLK; + wire RD_RST; + wire RD_EN; + wire FIFOEMPTY; + wire [C_DOUT_WIDTH-1:0] FIFODATA; + wire FIFOSBITERR; + wire FIFODBITERR; + + //Outputs + reg [C_DOUT_WIDTH-1:0] USERDATA; + wire USERVALID; + wire USERUNDERFLOW; + wire USEREMPTY; + wire USERALMOSTEMPTY; + wire RAMVALID; + wire FIFORDEN; + reg USERSBITERR; + reg USERDBITERR; + + //Internal signals + wire preloadstage1; + wire preloadstage2; + reg ram_valid_i; + reg read_data_valid_i; + wire ram_regout_en; + wire ram_rd_en; + reg empty_i = 1'b1; + reg empty_q = 1'b1; + reg rd_en_q = 1'b0; + reg almost_empty_i = 1'b1; + reg almost_empty_q = 1'b1; + wire rd_rst_i; + wire srst_i; + + +/************************************************************************* +* FUNCTIONS +*************************************************************************/ + + /************************************************************************* + * hexstr_conv + * Converts a string of type hex to a binary value (for C_DOUT_RST_VAL) + ***********************************************************************/ + function [C_DOUT_WIDTH-1:0] hexstr_conv; + input [(C_DOUT_WIDTH*8)-1:0] def_data; + + integer index,i,j; + reg [3:0] bin; + + begin + index = 0; + hexstr_conv = 'b0; + for( i=C_DOUT_WIDTH-1; i>=0; i=i-1 ) + begin + case (def_data[7:0]) + 8'b00000000 : + begin + bin = 4'b0000; + i = -1; + end + 8'b00110000 : bin = 4'b0000; + 8'b00110001 : bin = 4'b0001; + 8'b00110010 : bin = 4'b0010; + 8'b00110011 : bin = 4'b0011; + 8'b00110100 : bin = 4'b0100; + 8'b00110101 : bin = 4'b0101; + 8'b00110110 : bin = 4'b0110; + 8'b00110111 : bin = 4'b0111; + 8'b00111000 : bin = 4'b1000; + 8'b00111001 : bin = 4'b1001; + 8'b01000001 : bin = 4'b1010; + 8'b01000010 : bin = 4'b1011; + 8'b01000011 : bin = 4'b1100; + 8'b01000100 : bin = 4'b1101; + 8'b01000101 : bin = 4'b1110; + 8'b01000110 : bin = 4'b1111; + 8'b01100001 : bin = 4'b1010; + 8'b01100010 : bin = 4'b1011; + 8'b01100011 : bin = 4'b1100; + 8'b01100100 : bin = 4'b1101; + 8'b01100101 : bin = 4'b1110; + 8'b01100110 : bin = 4'b1111; + default : + begin + bin = 4'bx; + end + endcase + for( j=0; j<4; j=j+1) + begin + if ((index*4)+j < C_DOUT_WIDTH) + begin + hexstr_conv[(index*4)+j] = bin[j]; + end + end + index = index + 1; + def_data = def_data >> 8; + end + end + endfunction + + + //************************************************************************* + // Set power-on states for regs + //************************************************************************* + initial begin + ram_valid_i = 1'b0; + read_data_valid_i = 1'b0; + USERDATA = hexstr_conv(C_DOUT_RST_VAL); + USERSBITERR = 1'b0; + USERDBITERR = 1'b0; + end //initial + + //*************************************************************************** + // connect up optional reset + //*************************************************************************** + assign rd_rst_i = (C_HAS_RST == 1 || C_ENABLE_RST_SYNC == 0) ? RD_RST : 0; + assign srst_i = C_HAS_SRST ? SRST : 0; + + + //*************************************************************************** + // preloadstage2 indicates that stage2 needs to be updated. This is true + // whenever read_data_valid is false, and RAM_valid is true. + //*************************************************************************** + assign preloadstage2 = ram_valid_i & (~read_data_valid_i | RD_EN); + + //*************************************************************************** + // preloadstage1 indicates that stage1 needs to be updated. This is true + // whenever the RAM has data (RAM_EMPTY is false), and either RAM_Valid is + // false (indicating that Stage1 needs updating), or preloadstage2 is active + // (indicating that Stage2 is going to update, so Stage1, therefore, must + // also be updated to keep it valid. + //*************************************************************************** + assign preloadstage1 = ((~ram_valid_i | preloadstage2) & ~FIFOEMPTY); + + //*************************************************************************** + // Calculate RAM_REGOUT_EN + // The output registers are controlled by the ram_regout_en signal. + // These registers should be updated either when the output in Stage2 is + // invalid (preloadstage2), OR when the user is reading, in which case the + // Stage2 value will go invalid unless it is replenished. + //*************************************************************************** + assign ram_regout_en = preloadstage2; + + //*************************************************************************** + // Calculate RAM_RD_EN + // RAM_RD_EN will be asserted whenever the RAM needs to be read in order to + // update the value in Stage1. + // One case when this happens is when preloadstage1=true, which indicates + // that the data in Stage1 or Stage2 is invalid, and needs to automatically + // be updated. + // The other case is when the user is reading from the FIFO, which + // guarantees that Stage1 or Stage2 will be invalid on the next clock + // cycle, unless it is replinished by data from the memory. So, as long + // as the RAM has data in it, a read of the RAM should occur. + //*************************************************************************** + assign ram_rd_en = (RD_EN & ~FIFOEMPTY) | preloadstage1; + + //*************************************************************************** + // Calculate RAMVALID_P0_OUT + // RAMVALID_P0_OUT indicates that the data in Stage1 is valid. + // + // If the RAM is being read from on this clock cycle (ram_rd_en=1), then + // RAMVALID_P0_OUT is certainly going to be true. + // If the RAM is not being read from, but the output registers are being + // updated to fill Stage2 (ram_regout_en=1), then Stage1 will be emptying, + // therefore causing RAMVALID_P0_OUT to be false. + // Otherwise, RAMVALID_P0_OUT will remain unchanged. + //*************************************************************************** + // PROCESS regout_valid + always @ (posedge RD_CLK or posedge rd_rst_i) begin + if (rd_rst_i) begin + // asynchronous reset (active high) + ram_valid_i <= #`TCQ 1'b0; + end else begin + if (srst_i) begin + // synchronous reset (active high) + ram_valid_i <= #`TCQ 1'b0; + end else begin + if (ram_rd_en == 1'b1) begin + ram_valid_i <= #`TCQ 1'b1; + end else begin + if (ram_regout_en == 1'b1) + ram_valid_i <= #`TCQ 1'b0; + else + ram_valid_i <= #`TCQ ram_valid_i; + end + end //srst_i + end //rd_rst_i + end //always + + //*************************************************************************** + // Calculate READ_DATA_VALID + // READ_DATA_VALID indicates whether the value in Stage2 is valid or not. + // Stage2 has valid data whenever Stage1 had valid data and + // ram_regout_en_i=1, such that the data in Stage1 is propogated + // into Stage2. + //*************************************************************************** + always @ (posedge RD_CLK or posedge rd_rst_i) begin + if (rd_rst_i) + read_data_valid_i <= #`TCQ 1'b0; + else if (srst_i) + read_data_valid_i <= #`TCQ 1'b0; + else + read_data_valid_i <= #`TCQ ram_valid_i | (read_data_valid_i & ~RD_EN); + end //always + + + //************************************************************************** + // Calculate EMPTY + // Defined as the inverse of READ_DATA_VALID + // + // Description: + // + // If read_data_valid_i indicates that the output is not valid, + // and there is no valid data on the output of the ram to preload it + // with, then we will report empty. + // + // If there is no valid data on the output of the ram and we are + // reading, then the FIFO will go empty. + // + //************************************************************************** + always @ (posedge RD_CLK or posedge rd_rst_i) begin + if (rd_rst_i) begin + // asynchronous reset (active high) + empty_i <= #`TCQ 1'b1; + end else begin + if (srst_i) begin + // synchronous reset (active high) + empty_i <= #`TCQ 1'b1; + end else begin + // rising clock edge + empty_i <= #`TCQ (~ram_valid_i & ~read_data_valid_i) | (~ram_valid_i & RD_EN); + end + end + end //always + + // Register RD_EN from user to calculate USERUNDERFLOW. + // Register empty_i to calculate USERUNDERFLOW. + always @ (posedge RD_CLK) begin + rd_en_q <= #`TCQ RD_EN; + empty_q <= #`TCQ empty_i; + end //always + + + //*************************************************************************** + // Calculate user_almost_empty + // user_almost_empty is defined such that, unless more words are written + // to the FIFO, the next read will cause the FIFO to go EMPTY. + // + // In most cases, whenever the output registers are updated (due to a user + // read or a preload condition), then user_almost_empty will update to + // whatever RAM_EMPTY is. + // + // The exception is when the output is valid, the user is not reading, and + // Stage1 is not empty. In this condition, Stage1 will be preloaded from the + // memory, so we need to make sure user_almost_empty deasserts properly under + // this condition. + //*************************************************************************** + always @ (posedge RD_CLK or posedge rd_rst_i) + begin + if (rd_rst_i) begin // asynchronous reset (active high) + almost_empty_i <= #`TCQ 1'b1; + almost_empty_q <= #`TCQ 1'b1; + end else begin // rising clock edge + if (srst_i) begin // synchronous reset (active high) + almost_empty_i <= #`TCQ 1'b1; + almost_empty_q <= #`TCQ 1'b1; + end else begin + if ((ram_regout_en) | (~FIFOEMPTY & read_data_valid_i & ~RD_EN)) begin + almost_empty_i <= #`TCQ FIFOEMPTY; + end + almost_empty_q <= #`TCQ empty_i; + end + end + end //always + + + assign USEREMPTY = empty_i; + assign USERALMOSTEMPTY = almost_empty_i; + assign FIFORDEN = ram_rd_en; + assign RAMVALID = ram_valid_i; + assign USERVALID = C_USERVALID_LOW ? ~read_data_valid_i : read_data_valid_i; + assign USERUNDERFLOW = C_USERUNDERFLOW_LOW ? ~(empty_q & rd_en_q) : empty_q & rd_en_q; + + // BRAM resets synchronously + always @ (posedge RD_CLK) + begin + if (rd_rst_i || srst_i) begin + if (C_USE_DOUT_RST == 1 && C_MEMORY_TYPE < 2) + USERDATA <= #`TCQ hexstr_conv(C_DOUT_RST_VAL); + end + end //always + + + always @ (posedge RD_CLK or posedge rd_rst_i) + begin + if (rd_rst_i) begin //asynchronous reset (active high) + if (C_USE_ECC == 0) begin // Reset S/DBITERR only if ECC is OFF + USERSBITERR <= #`TCQ 0; + USERDBITERR <= #`TCQ 0; + end + // DRAM resets asynchronously + if (C_USE_DOUT_RST == 1 && C_MEMORY_TYPE == 2) //asynchronous reset (active high) + USERDATA <= #`TCQ hexstr_conv(C_DOUT_RST_VAL); + end else begin // rising clock edge + if (srst_i) begin + if (C_USE_ECC == 0) begin // Reset S/DBITERR only if ECC is OFF + USERSBITERR <= #`TCQ 0; + USERDBITERR <= #`TCQ 0; + end + if (C_USE_DOUT_RST == 1 && C_MEMORY_TYPE == 2) + USERDATA <= #`TCQ hexstr_conv(C_DOUT_RST_VAL); + end else begin + if (ram_regout_en) begin + USERDATA <= #`TCQ FIFODATA; + USERSBITERR <= #`TCQ FIFOSBITERR; + USERDBITERR <= #`TCQ FIFODBITERR; + end + end + end + end //always + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/FIFO_GENERATOR_V6_1_XST.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/FIFO_GENERATOR_V6_1_XST.v new file mode 100644 index 0000000..84501dc --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/FIFO_GENERATOR_V6_1_XST.v @@ -0,0 +1,336 @@ +/* + ******************************************************************************* + * + * FIFO Generator - Verilog Behavioral Model + * + ******************************************************************************* + * + * (c) Copyright 1995 - 2009 Xilinx, Inc. All rights reserved. + * + * This file contains confidential and proprietary information + * of Xilinx, Inc. and is protected under U.S. and + * international copyright and other intellectual property + * laws. + * + * DISCLAIMER + * This disclaimer is not a license and does not grant any + * rights to the materials distributed herewith. Except as + * otherwise provided in a valid license issued to you by + * Xilinx, and to the maximum extent permitted by applicable + * law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND + * WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES + * AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING + * BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- + * INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and + * (2) Xilinx shall not be liable (whether in contract or tort, + * including negligence, or under any other theory of + * liability) for any loss or damage of any kind or nature + * related to, arising under or in connection with these + * materials, including for any direct, or any indirect, + * special, incidental, or consequential loss or damage + * (including loss of data, profits, goodwill, or any type of + * loss or damage suffered as a result of any action brought + * by a third party) even if such damage or loss was + * reasonably foreseeable or Xilinx had been advised of the + * possibility of the same. + * + * CRITICAL APPLICATIONS + * Xilinx products are not designed or intended to be fail- + * safe, or for use in any application requiring fail-safe + * performance, such as life-support or safety devices or + * systems, Class III medical devices, nuclear facilities, + * applications related to the deployment of airbags, or any + * other applications that could lead to death, personal + * injury, or severe property or environmental damage + * (individually and collectively, "Critical + * Applications"). Customer assumes the sole risk and + * liability of any use of Xilinx products in Critical + * Applications, subject only to applicable laws and + * regulations governing limitations on product liability. + * + * THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS + * PART OF THIS FILE AT ALL TIMES. + * + ******************************************************************************* + ******************************************************************************* + * + * Filename: fifo_generator_v6_1_bhv.v + * + * Description: + * The verilog behavioral model for the FIFO generator core. + * + ******************************************************************************* + */ + +`timescale 1ps/1ps + +/******************************************************************************* + * Declaration of top-level module + ******************************************************************************/ +module FIFO_GENERATOR_V6_1_XST + ( + BACKUP, + BACKUP_MARKER, + CLK, + RST, + SRST, + WR_CLK, + WR_RST, + RD_CLK, + RD_RST, + DIN, + WR_EN, + RD_EN, + PROG_EMPTY_THRESH, + PROG_EMPTY_THRESH_ASSERT, + PROG_EMPTY_THRESH_NEGATE, + PROG_FULL_THRESH, + PROG_FULL_THRESH_ASSERT, + PROG_FULL_THRESH_NEGATE, + INT_CLK, + INJECTDBITERR, + INJECTSBITERR, + + DOUT, + FULL, + ALMOST_FULL, + WR_ACK, + OVERFLOW, + EMPTY, + ALMOST_EMPTY, + VALID, + UNDERFLOW, + DATA_COUNT, + RD_DATA_COUNT, + WR_DATA_COUNT, + PROG_FULL, + PROG_EMPTY, + SBITERR, + DBITERR + ); + +/****************************************************************************** + * Definition of Ports + * + * + ***************************************************************************** + * Definition of Parameters + * + * + *****************************************************************************/ + +/****************************************************************************** + * Declare user parameters and their defaults + *****************************************************************************/ + parameter C_COMMON_CLOCK = 0; + parameter C_COUNT_TYPE = 0; + parameter C_DATA_COUNT_WIDTH = 2; + parameter C_DEFAULT_VALUE = ""; + parameter C_DIN_WIDTH = 8; + parameter C_DOUT_RST_VAL = ""; + parameter C_DOUT_WIDTH = 8; + parameter C_ENABLE_RLOCS = 0; + parameter C_FAMILY = "virtex2"; //Not allowed in Verilog model + parameter C_FULL_FLAGS_RST_VAL = 1; + parameter C_HAS_ALMOST_EMPTY = 0; + parameter C_HAS_ALMOST_FULL = 0; + parameter C_HAS_BACKUP = 0; + parameter C_HAS_DATA_COUNT = 0; + parameter C_HAS_INT_CLK = 0; + parameter C_HAS_MEMINIT_FILE = 0; + parameter C_HAS_OVERFLOW = 0; + parameter C_HAS_RD_DATA_COUNT = 0; + parameter C_HAS_RD_RST = 0; + parameter C_HAS_RST = 0; + parameter C_HAS_SRST = 0; + parameter C_HAS_UNDERFLOW = 0; + parameter C_HAS_VALID = 0; + parameter C_HAS_WR_ACK = 0; + parameter C_HAS_WR_DATA_COUNT = 0; + parameter C_HAS_WR_RST = 0; + parameter C_IMPLEMENTATION_TYPE = 0; + parameter C_INIT_WR_PNTR_VAL = 0; + parameter C_MEMORY_TYPE = 1; + parameter C_MIF_FILE_NAME = ""; + parameter C_OPTIMIZATION_MODE = 0; + parameter C_OVERFLOW_LOW = 0; + parameter C_PRELOAD_LATENCY = 1; + parameter C_PRELOAD_REGS = 0; + parameter C_PRIM_FIFO_TYPE = ""; + parameter C_PROG_EMPTY_THRESH_ASSERT_VAL = 0; + parameter C_PROG_EMPTY_THRESH_NEGATE_VAL = 0; + parameter C_PROG_EMPTY_TYPE = 0; + parameter C_PROG_FULL_THRESH_ASSERT_VAL = 0; + parameter C_PROG_FULL_THRESH_NEGATE_VAL = 0; + parameter C_PROG_FULL_TYPE = 0; + parameter C_RD_DATA_COUNT_WIDTH = 2; + parameter C_RD_DEPTH = 256; + parameter C_RD_FREQ = 1; + parameter C_RD_PNTR_WIDTH = 8; + parameter C_UNDERFLOW_LOW = 0; + parameter C_USE_DOUT_RST = 0; + parameter C_USE_ECC = 0; + parameter C_USE_EMBEDDED_REG = 0; + parameter C_USE_FIFO16_FLAGS = 0; + parameter C_USE_FWFT_DATA_COUNT = 0; + parameter C_VALID_LOW = 0; + parameter C_WR_ACK_LOW = 0; + parameter C_WR_DATA_COUNT_WIDTH = 2; + parameter C_WR_DEPTH = 256; + parameter C_WR_FREQ = 1; + parameter C_WR_PNTR_WIDTH = 8; + parameter C_WR_RESPONSE_LATENCY = 1; + parameter C_MSGON_VAL = 1; + parameter C_ENABLE_RST_SYNC = 1; + parameter C_ERROR_INJECTION_TYPE = 0; + + + /****************************************************************************** + * Declare Input and Output Ports + *****************************************************************************/ + input CLK; + input BACKUP; + input BACKUP_MARKER; + input [C_DIN_WIDTH-1:0] DIN; + input [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH; + input [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_ASSERT; + input [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_NEGATE; + input [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH; + input [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_ASSERT; + input [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_NEGATE; + input RD_CLK; + input RD_EN; + input RD_RST; + input RST; + input SRST; + input WR_CLK; + input WR_EN; + input WR_RST; + input INT_CLK; + input INJECTDBITERR; + input INJECTSBITERR; + + output ALMOST_EMPTY; + output ALMOST_FULL; + output [C_DATA_COUNT_WIDTH-1:0] DATA_COUNT; + output [C_DOUT_WIDTH-1:0] DOUT; + output EMPTY; + output FULL; + output OVERFLOW; + output PROG_EMPTY; + output PROG_FULL; + output VALID; + output [C_RD_DATA_COUNT_WIDTH-1:0] RD_DATA_COUNT; + output UNDERFLOW; + output WR_ACK; + output [C_WR_DATA_COUNT_WIDTH-1:0] WR_DATA_COUNT; + output SBITERR; + output DBITERR; + + FIFO_GENERATOR_V6_1 + #( + .C_COMMON_CLOCK (C_COMMON_CLOCK), + .C_COUNT_TYPE (C_COUNT_TYPE), + .C_DATA_COUNT_WIDTH (C_DATA_COUNT_WIDTH), + .C_DEFAULT_VALUE (C_DEFAULT_VALUE), + .C_DIN_WIDTH (C_DIN_WIDTH), + .C_DOUT_RST_VAL (C_DOUT_RST_VAL), + .C_DOUT_WIDTH (C_DOUT_WIDTH), + .C_ENABLE_RLOCS (C_ENABLE_RLOCS), + .C_FAMILY (C_FAMILY),//Not allowed in Verilog model + .C_FULL_FLAGS_RST_VAL (C_FULL_FLAGS_RST_VAL), + .C_HAS_ALMOST_EMPTY (C_HAS_ALMOST_EMPTY), + .C_HAS_ALMOST_FULL (C_HAS_ALMOST_FULL), + .C_HAS_BACKUP (C_HAS_BACKUP), + .C_HAS_DATA_COUNT (C_HAS_DATA_COUNT), + .C_HAS_INT_CLK (C_HAS_INT_CLK), + .C_HAS_MEMINIT_FILE (C_HAS_MEMINIT_FILE), + .C_HAS_OVERFLOW (C_HAS_OVERFLOW), + .C_HAS_RD_DATA_COUNT (C_HAS_RD_DATA_COUNT), + .C_HAS_RD_RST (C_HAS_RD_RST), + .C_HAS_RST (C_HAS_RST), + .C_HAS_SRST (C_HAS_SRST), + .C_HAS_UNDERFLOW (C_HAS_UNDERFLOW), + .C_HAS_VALID (C_HAS_VALID), + .C_HAS_WR_ACK (C_HAS_WR_ACK), + .C_HAS_WR_DATA_COUNT (C_HAS_WR_DATA_COUNT), + .C_HAS_WR_RST (C_HAS_WR_RST), + .C_IMPLEMENTATION_TYPE (C_IMPLEMENTATION_TYPE), + .C_INIT_WR_PNTR_VAL (C_INIT_WR_PNTR_VAL), + .C_MEMORY_TYPE (C_MEMORY_TYPE), + .C_MIF_FILE_NAME (C_MIF_FILE_NAME), + .C_OPTIMIZATION_MODE (C_OPTIMIZATION_MODE), + .C_OVERFLOW_LOW (C_OVERFLOW_LOW), + .C_PRELOAD_LATENCY (C_PRELOAD_LATENCY), + .C_PRELOAD_REGS (C_PRELOAD_REGS), + .C_PRIM_FIFO_TYPE (C_PRIM_FIFO_TYPE), + .C_PROG_EMPTY_THRESH_ASSERT_VAL (C_PROG_EMPTY_THRESH_ASSERT_VAL), + .C_PROG_EMPTY_THRESH_NEGATE_VAL (C_PROG_EMPTY_THRESH_NEGATE_VAL), + .C_PROG_EMPTY_TYPE (C_PROG_EMPTY_TYPE), + .C_PROG_FULL_THRESH_ASSERT_VAL (C_PROG_FULL_THRESH_ASSERT_VAL), + .C_PROG_FULL_THRESH_NEGATE_VAL (C_PROG_FULL_THRESH_NEGATE_VAL), + .C_PROG_FULL_TYPE (C_PROG_FULL_TYPE), + .C_RD_DATA_COUNT_WIDTH (C_RD_DATA_COUNT_WIDTH), + .C_RD_DEPTH (C_RD_DEPTH), + .C_RD_FREQ (C_RD_FREQ), + .C_RD_PNTR_WIDTH (C_RD_PNTR_WIDTH), + .C_UNDERFLOW_LOW (C_UNDERFLOW_LOW), + .C_USE_DOUT_RST (C_USE_DOUT_RST), + .C_USE_ECC (C_USE_ECC), + .C_USE_EMBEDDED_REG (C_USE_EMBEDDED_REG), + .C_USE_FIFO16_FLAGS (C_USE_FIFO16_FLAGS), + .C_USE_FWFT_DATA_COUNT (C_USE_FWFT_DATA_COUNT), + .C_VALID_LOW (C_VALID_LOW), + .C_WR_ACK_LOW (C_WR_ACK_LOW), + .C_WR_DATA_COUNT_WIDTH (C_WR_DATA_COUNT_WIDTH), + .C_WR_DEPTH (C_WR_DEPTH), + .C_WR_FREQ (C_WR_FREQ), + .C_WR_PNTR_WIDTH (C_WR_PNTR_WIDTH), + .C_WR_RESPONSE_LATENCY (C_WR_RESPONSE_LATENCY), + .C_MSGON_VAL (C_MSGON_VAL), + .C_ENABLE_RST_SYNC (C_ENABLE_RST_SYNC), + .C_ERROR_INJECTION_TYPE (C_ERROR_INJECTION_TYPE) + ) + fifo_generator_v6_1_dut + ( + .BACKUP (BACKUP), + .BACKUP_MARKER (BACKUP_MARKER), + .CLK (CLK), + .RST (RST), + .SRST (SRST), + .WR_CLK (WR_CLK), + .WR_RST (WR_RST), + .RD_CLK (RD_CLK), + .RD_RST (RD_RST), + .DIN (DIN), + .WR_EN (WR_EN), + .RD_EN (RD_EN), + .PROG_EMPTY_THRESH (PROG_EMPTY_THRESH), + .PROG_EMPTY_THRESH_ASSERT (PROG_EMPTY_THRESH_ASSERT), + .PROG_EMPTY_THRESH_NEGATE (PROG_EMPTY_THRESH_NEGATE), + .PROG_FULL_THRESH (PROG_FULL_THRESH), + .PROG_FULL_THRESH_ASSERT (PROG_FULL_THRESH_ASSERT), + .PROG_FULL_THRESH_NEGATE (PROG_FULL_THRESH_NEGATE), + .INT_CLK (INT_CLK), + .INJECTDBITERR (INJECTDBITERR), + .INJECTSBITERR (INJECTSBITERR), + + .DOUT (DOUT), + .FULL (FULL), + .ALMOST_FULL (ALMOST_FULL), + .WR_ACK (WR_ACK), + .OVERFLOW (OVERFLOW), + .EMPTY (EMPTY), + .ALMOST_EMPTY (ALMOST_EMPTY), + .VALID (VALID), + .UNDERFLOW (UNDERFLOW), + .DATA_COUNT (DATA_COUNT), + .RD_DATA_COUNT (RD_DATA_COUNT), + .WR_DATA_COUNT (WR_DATA_COUNT), + .PROG_FULL (PROG_FULL), + .PROG_EMPTY (PROG_EMPTY), + .SBITERR (SBITERR), + .DBITERR (DBITERR) + ); + +endmodule diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/FIFO_GENERATOR_V6_2.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/FIFO_GENERATOR_V6_2.v new file mode 100644 index 0000000..88be2cb --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/FIFO_GENERATOR_V6_2.v @@ -0,0 +1,4662 @@ +/* + ******************************************************************************* + * + * FIFO Generator - Verilog Behavioral Model + * + ******************************************************************************* + * + * (c) Copyright 1995 - 2009 Xilinx, Inc. All rights reserved. + * + * This file contains confidential and proprietary information + * of Xilinx, Inc. and is protected under U.S. and + * international copyright and other intellectual property + * laws. + * + * DISCLAIMER + * This disclaimer is not a license and does not grant any + * rights to the materials distributed herewith. Except as + * otherwise provided in a valid license issued to you by + * Xilinx, and to the maximum extent permitted by applicable + * law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND + * WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES + * AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING + * BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- + * INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and + * (2) Xilinx shall not be liable (whether in contract or tort, + * including negligence, or under any other theory of + * liability) for any loss or damage of any kind or nature + * related to, arising under or in connection with these + * materials, including for any direct, or any indirect, + * special, incidental, or consequential loss or damage + * (including loss of data, profits, goodwill, or any type of + * loss or damage suffered as a result of any action brought + * by a third party) even if such damage or loss was + * reasonably foreseeable or Xilinx had been advised of the + * possibility of the same. + * + * CRITICAL APPLICATIONS + * Xilinx products are not designed or intended to be fail- + * safe, or for use in any application requiring fail-safe + * performance, such as life-support or safety devices or + * systems, Class III medical devices, nuclear facilities, + * applications related to the deployment of airbags, or any + * other applications that could lead to death, personal + * injury, or severe property or environmental damage + * (individually and collectively, "Critical + * Applications"). Customer assumes the sole risk and + * liability of any use of Xilinx products in Critical + * Applications, subject only to applicable laws and + * regulations governing limitations on product liability. + * + * THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS + * PART OF THIS FILE AT ALL TIMES. + * + ******************************************************************************* + ******************************************************************************* + * + * Filename: FIFO_GENERATOR_V6_2.v + * + * Author : Xilinx + * + ******************************************************************************* + * Structure: + * + * fifo_generator_v6_2.vhd + * | + * +-fifo_generator_v6_2_bhv_ver_as + * | + * +-fifo_generator_v6_2_bhv_ver_ss + * | + * +-fifo_generator_v6_2_bhv_ver_preload0 + * + ******************************************************************************* + * Description: + * + * The Verilog behavioral model for the FIFO Generator. + * + * The behavioral model has three parts: + * - The behavioral model for independent clocks FIFOs (_as) + * - The behavioral model for common clock FIFOs (_ss) + * - The "preload logic" block which implements First-word Fall-through + * + ******************************************************************************* + * Description: + * The verilog behavioral model for the FIFO generator core. + * + ******************************************************************************* + */ + +`timescale 1ps/1ps +`ifndef TCQ + `define TCQ 100 +`endif + + +/******************************************************************************* + * Declaration of top-level module + ******************************************************************************/ +module FIFO_GENERATOR_V6_2 + #( + parameter C_COMMON_CLOCK = 0, + parameter C_COUNT_TYPE = 0, + parameter C_DATA_COUNT_WIDTH = 2, + parameter C_DEFAULT_VALUE = "", + parameter C_DIN_WIDTH = 8, + parameter C_DOUT_RST_VAL = "", + parameter C_DOUT_WIDTH = 8, + parameter C_ENABLE_RLOCS = 0, + parameter C_FAMILY = "virtex6", //Not allowed in Verilog model + parameter C_FULL_FLAGS_RST_VAL = 1, + parameter C_HAS_ALMOST_EMPTY = 0, + parameter C_HAS_ALMOST_FULL = 0, + parameter C_HAS_BACKUP = 0, + parameter C_HAS_DATA_COUNT = 0, + parameter C_HAS_INT_CLK = 0, + parameter C_HAS_MEMINIT_FILE = 0, + parameter C_HAS_OVERFLOW = 0, + parameter C_HAS_RD_DATA_COUNT = 0, + parameter C_HAS_RD_RST = 0, + parameter C_HAS_RST = 0, + parameter C_HAS_SRST = 0, + parameter C_HAS_UNDERFLOW = 0, + parameter C_HAS_VALID = 0, + parameter C_HAS_WR_ACK = 0, + parameter C_HAS_WR_DATA_COUNT = 0, + parameter C_HAS_WR_RST = 0, + parameter C_IMPLEMENTATION_TYPE = 0, + parameter C_INIT_WR_PNTR_VAL = 0, + parameter C_MEMORY_TYPE = 1, + parameter C_MIF_FILE_NAME = "", + parameter C_OPTIMIZATION_MODE = 0, + parameter C_OVERFLOW_LOW = 0, + parameter C_PRELOAD_LATENCY = 1, + parameter C_PRELOAD_REGS = 0, + parameter C_PRIM_FIFO_TYPE = "", + parameter C_PROG_EMPTY_THRESH_ASSERT_VAL = 0, + parameter C_PROG_EMPTY_THRESH_NEGATE_VAL = 0, + parameter C_PROG_EMPTY_TYPE = 0, + parameter C_PROG_FULL_THRESH_ASSERT_VAL = 0, + parameter C_PROG_FULL_THRESH_NEGATE_VAL = 0, + parameter C_PROG_FULL_TYPE = 0, + parameter C_RD_DATA_COUNT_WIDTH = 2, + parameter C_RD_DEPTH = 256, + parameter C_RD_FREQ = 1, + parameter C_RD_PNTR_WIDTH = 8, + parameter C_UNDERFLOW_LOW = 0, + parameter C_USE_DOUT_RST = 0, + parameter C_USE_ECC = 0, + parameter C_USE_EMBEDDED_REG = 0, + parameter C_USE_FIFO16_FLAGS = 0, + parameter C_USE_FWFT_DATA_COUNT = 0, + parameter C_VALID_LOW = 0, + parameter C_WR_ACK_LOW = 0, + parameter C_WR_DATA_COUNT_WIDTH = 2, + parameter C_WR_DEPTH = 256, + parameter C_WR_FREQ = 1, + parameter C_WR_PNTR_WIDTH = 8, + parameter C_WR_RESPONSE_LATENCY = 1, + parameter C_MSGON_VAL = 1, + parameter C_ENABLE_RST_SYNC = 1, + parameter C_ERROR_INJECTION_TYPE = 0 + ) + + ( + input BACKUP, + input BACKUP_MARKER, + input CLK, + input RST, + input SRST, + input WR_CLK, + input WR_RST, + input RD_CLK, + input RD_RST, + input [C_DIN_WIDTH-1:0] DIN, + input WR_EN, + input RD_EN, + input [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH, + input [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_ASSERT, + input [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_NEGATE, + input [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH, + input [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_ASSERT, + input [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_NEGATE, + input INT_CLK, + input INJECTDBITERR, + input INJECTSBITERR, + + output [C_DOUT_WIDTH-1:0] DOUT, + output FULL, + output ALMOST_FULL, + output WR_ACK, + output OVERFLOW, + output EMPTY, + output ALMOST_EMPTY, + output VALID, + output UNDERFLOW, + output [C_DATA_COUNT_WIDTH-1:0] DATA_COUNT, + output [C_RD_DATA_COUNT_WIDTH-1:0] RD_DATA_COUNT, + output [C_WR_DATA_COUNT_WIDTH-1:0] WR_DATA_COUNT, + output PROG_FULL, + output PROG_EMPTY, + output SBITERR, + output DBITERR + ); + +/* + ****************************************************************************** + * Definition of Parameters + ****************************************************************************** + * C_COMMON_CLOCK : Common Clock (1), Independent Clocks (0) + * C_COUNT_TYPE : *not used + * C_DATA_COUNT_WIDTH : Width of DATA_COUNT bus + * C_DEFAULT_VALUE : *not used + * C_DIN_WIDTH : Width of DIN bus + * C_DOUT_RST_VAL : Reset value of DOUT + * C_DOUT_WIDTH : Width of DOUT bus + * C_ENABLE_RLOCS : *not used + * C_FAMILY : not used in bhv model + * C_FULL_FLAGS_RST_VAL : Full flags rst val (0 or 1) + * C_HAS_ALMOST_EMPTY : 1=Core has ALMOST_EMPTY flag + * C_HAS_ALMOST_FULL : 1=Core has ALMOST_FULL flag + * C_HAS_BACKUP : *not used + * C_HAS_DATA_COUNT : 1=Core has DATA_COUNT bus + * C_HAS_INT_CLK : not used in bhv model + * C_HAS_MEMINIT_FILE : *not used + * C_HAS_OVERFLOW : 1=Core has OVERFLOW flag + * C_HAS_RD_DATA_COUNT : 1=Core has RD_DATA_COUNT bus + * C_HAS_RD_RST : *not used + * C_HAS_RST : 1=Core has Async Rst + * C_HAS_SRST : 1=Core has Sync Rst + * C_HAS_UNDERFLOW : 1=Core has UNDERFLOW flag + * C_HAS_VALID : 1=Core has VALID flag + * C_HAS_WR_ACK : 1=Core has WR_ACK flag + * C_HAS_WR_DATA_COUNT : 1=Core has WR_DATA_COUNT bus + * C_HAS_WR_RST : *not used + * C_IMPLEMENTATION_TYPE : 0=Common-Clock Bram/Dram + * 1=Common-Clock ShiftRam + * 2=Indep. Clocks Bram/Dram + * 3=Virtex-4 Built-in + * 4=Virtex-5 Built-in + * C_INIT_WR_PNTR_VAL : *not used + * C_MEMORY_TYPE : 1=Block RAM + * 2=Distributed RAM + * 3=Shift RAM + * 4=Built-in FIFO + * C_MIF_FILE_NAME : *not used + * C_OPTIMIZATION_MODE : *not used + * C_OVERFLOW_LOW : 1=OVERFLOW active low + * C_PRELOAD_LATENCY : Latency of read: 0, 1, 2 + * C_PRELOAD_REGS : 1=Use output registers + * C_PRIM_FIFO_TYPE : not used in bhv model + * C_PROG_EMPTY_THRESH_ASSERT_VAL: PROG_EMPTY assert threshold + * C_PROG_EMPTY_THRESH_NEGATE_VAL: PROG_EMPTY negate threshold + * C_PROG_EMPTY_TYPE : 0=No programmable empty + * 1=Single prog empty thresh constant + * 2=Multiple prog empty thresh constants + * 3=Single prog empty thresh input + * 4=Multiple prog empty thresh inputs + * C_PROG_FULL_THRESH_ASSERT_VAL : PROG_FULL assert threshold + * C_PROG_FULL_THRESH_NEGATE_VAL : PROG_FULL negate threshold + * C_PROG_FULL_TYPE : 0=No prog full + * 1=Single prog full thresh constant + * 2=Multiple prog full thresh constants + * 3=Single prog full thresh input + * 4=Multiple prog full thresh inputs + * C_RD_DATA_COUNT_WIDTH : Width of RD_DATA_COUNT bus + * C_RD_DEPTH : Depth of read interface (2^N) + * C_RD_FREQ : not used in bhv model + * C_RD_PNTR_WIDTH : always log2(C_RD_DEPTH) + * C_UNDERFLOW_LOW : 1=UNDERFLOW active low + * C_USE_DOUT_RST : 1=Resets DOUT on RST + * C_USE_ECC : Used for error injection purpose + * C_USE_EMBEDDED_REG : 1=Use BRAM embedded output register + * C_USE_FIFO16_FLAGS : not used in bhv model + * C_USE_FWFT_DATA_COUNT : 1=Use extra logic for FWFT data count + * C_VALID_LOW : 1=VALID active low + * C_WR_ACK_LOW : 1=WR_ACK active low + * C_WR_DATA_COUNT_WIDTH : Width of WR_DATA_COUNT bus + * C_WR_DEPTH : Depth of write interface (2^N) + * C_WR_FREQ : not used in bhv model + * C_WR_PNTR_WIDTH : always log2(C_WR_DEPTH) + * C_WR_RESPONSE_LATENCY : *not used + * C_MSGON_VAL : *not used by bhv model + * C_ENABLE_RST_SYNC : 0 = Use WR_RST & RD_RST + * 1 = Use RST + * C_ERROR_INJECTION_TYPE : 0 = No error injection + * 1 = Single bit error injection only + * 2 = Double bit error injection only + * 3 = Single and double bit error injection + ****************************************************************************** + * Definition of Ports + ****************************************************************************** + * BACKUP : Not used + * BACKUP_MARKER: Not used + * CLK : Clock + * DIN : Input data bus + * PROG_EMPTY_THRESH : Threshold for Programmable Empty Flag + * PROG_EMPTY_THRESH_ASSERT: Threshold for Programmable Empty Flag + * PROG_EMPTY_THRESH_NEGATE: Threshold for Programmable Empty Flag + * PROG_FULL_THRESH : Threshold for Programmable Full Flag + * PROG_FULL_THRESH_ASSERT : Threshold for Programmable Full Flag + * PROG_FULL_THRESH_NEGATE : Threshold for Programmable Full Flag + * RD_CLK : Read Domain Clock + * RD_EN : Read enable + * RD_RST : Read Reset + * RST : Asynchronous Reset + * SRST : Synchronous Reset + * WR_CLK : Write Domain Clock + * WR_EN : Write enable + * WR_RST : Write Reset + * INT_CLK : Internal Clock + * INJECTSBITERR: Inject Signle bit error + * INJECTDBITERR: Inject Double bit error + * ALMOST_EMPTY : One word remaining in FIFO + * ALMOST_FULL : One empty space remaining in FIFO + * DATA_COUNT : Number of data words in fifo( synchronous to CLK) + * DOUT : Output data bus + * EMPTY : Empty flag + * FULL : Full flag + * OVERFLOW : Last write rejected + * PROG_EMPTY : Programmable Empty Flag + * PROG_FULL : Programmable Full Flag + * RD_DATA_COUNT: Number of data words in fifo (synchronous to RD_CLK) + * UNDERFLOW : Last read rejected + * VALID : Last read acknowledged, DOUT bus VALID + * WR_ACK : Last write acknowledged + * WR_DATA_COUNT: Number of data words in fifo (synchronous to WR_CLK) + * SBITERR : Single Bit ECC Error Detected + * DBITERR : Double Bit ECC Error Detected + ****************************************************************************** + */ + + + /***************************************************************************** + * Derived parameters + ****************************************************************************/ + //There are 2 Verilog behavioral models + // 0 = Common-Clock FIFO/ShiftRam FIFO + // 1 = Independent Clocks FIFO + parameter C_VERILOG_IMPL = (C_IMPLEMENTATION_TYPE == 2) ? 1 : 0; + + //Internal reset signals + reg rd_rst_asreg = 0; + reg rd_rst_asreg_d1 = 0; + reg rd_rst_asreg_d2 = 0; + reg rd_rst_reg = 0; + wire rd_rst_comb; + reg rd_rst_d1 = 0; + reg wr_rst_asreg = 0; + reg wr_rst_asreg_d1 = 0; + reg wr_rst_asreg_d2 = 0; + reg wr_rst_reg = 0; + wire wr_rst_comb; + wire wr_rst_i; + wire rd_rst_i; + wire rst_i; + + //Internal reset signals + reg rst_asreg = 0; + reg rst_asreg_d1 = 0; + reg rst_asreg_d2 = 0; + reg rst_reg = 0; + wire rst_comb; + wire rst_full_gen_i; + wire rst_full_ff_i; + + wire RD_CLK_P0_IN; + wire RST_P0_IN; + wire RD_EN_FIFO_IN; + wire RD_EN_P0_IN; + + wire ALMOST_EMPTY_FIFO_OUT; + wire ALMOST_FULL_FIFO_OUT; + wire [C_DATA_COUNT_WIDTH-1:0] DATA_COUNT_FIFO_OUT; + wire [C_DOUT_WIDTH-1:0] DOUT_FIFO_OUT; + wire EMPTY_FIFO_OUT; + wire FULL_FIFO_OUT; + wire OVERFLOW_FIFO_OUT; + wire PROG_EMPTY_FIFO_OUT; + wire PROG_FULL_FIFO_OUT; + wire VALID_FIFO_OUT; + wire [C_RD_DATA_COUNT_WIDTH-1:0] RD_DATA_COUNT_FIFO_OUT; + wire UNDERFLOW_FIFO_OUT; + wire WR_ACK_FIFO_OUT; + wire [C_WR_DATA_COUNT_WIDTH-1:0] WR_DATA_COUNT_FIFO_OUT; + + + //*************************************************************************** + // Internal Signals + // The core uses either the internal_ wires or the preload0_ wires depending + // on whether the core uses Preload0 or not. + // When using preload0, the internal signals connect the internal core to + // the preload logic, and the external core's interfaces are tied to the + // preload0 signals from the preload logic. + //*************************************************************************** + wire [C_DOUT_WIDTH-1:0] DATA_P0_OUT; + wire VALID_P0_OUT; + wire EMPTY_P0_OUT; + wire ALMOSTEMPTY_P0_OUT; + reg EMPTY_P0_OUT_Q; + reg ALMOSTEMPTY_P0_OUT_Q; + wire UNDERFLOW_P0_OUT; + wire RDEN_P0_OUT; + wire [C_DOUT_WIDTH-1:0] DATA_P0_IN; + wire EMPTY_P0_IN; + reg [31:0] DATA_COUNT_FWFT; + reg SS_FWFT_WR ; + reg SS_FWFT_RD ; + + wire sbiterr_fifo_out; + wire dbiterr_fifo_out; + + // Assign 0 if not selected to avoid 'X' propogation to S/DBITERR. + assign inject_sbit_err = ((C_ERROR_INJECTION_TYPE == 1) || (C_ERROR_INJECTION_TYPE == 3)) ? + INJECTSBITERR : 0; + assign inject_dbit_err = ((C_ERROR_INJECTION_TYPE == 2) || (C_ERROR_INJECTION_TYPE == 3)) ? + INJECTDBITERR : 0; + + +// Choose the behavioral model to instantiate based on the C_VERILOG_IMPL +// parameter (1=Independent Clocks, 0=Common Clock) + + localparam FULL_FLAGS_RST_VAL = (C_HAS_SRST == 1) ? 0 : C_FULL_FLAGS_RST_VAL; +generate +case (C_VERILOG_IMPL) +0 : begin : block1 + //Common Clock Behavioral Model + fifo_generator_v6_2_bhv_ver_ss + #( + C_DATA_COUNT_WIDTH, + C_DIN_WIDTH, + C_DOUT_RST_VAL, + C_DOUT_WIDTH, +// C_FULL_FLAGS_RST_VAL, + FULL_FLAGS_RST_VAL, + C_HAS_ALMOST_EMPTY, + C_HAS_ALMOST_FULL, + C_HAS_DATA_COUNT, + C_HAS_OVERFLOW, + C_HAS_RD_DATA_COUNT, + C_HAS_RST, + C_HAS_SRST, + C_HAS_UNDERFLOW, + C_HAS_VALID, + C_HAS_WR_ACK, + C_HAS_WR_DATA_COUNT, + C_IMPLEMENTATION_TYPE, + C_MEMORY_TYPE, + C_OVERFLOW_LOW, + C_PRELOAD_LATENCY, + C_PRELOAD_REGS, + C_PROG_EMPTY_THRESH_ASSERT_VAL, + C_PROG_EMPTY_THRESH_NEGATE_VAL, + C_PROG_EMPTY_TYPE, + C_PROG_FULL_THRESH_ASSERT_VAL, + C_PROG_FULL_THRESH_NEGATE_VAL, + C_PROG_FULL_TYPE, + C_RD_DATA_COUNT_WIDTH, + C_RD_DEPTH, + C_RD_PNTR_WIDTH, + C_UNDERFLOW_LOW, + C_USE_DOUT_RST, + C_USE_EMBEDDED_REG, + C_USE_FWFT_DATA_COUNT, + C_VALID_LOW, + C_WR_ACK_LOW, + C_WR_DATA_COUNT_WIDTH, + C_WR_DEPTH, + C_WR_PNTR_WIDTH, + C_USE_ECC, + C_ENABLE_RST_SYNC, + C_ERROR_INJECTION_TYPE + ) + gen_ss + ( + .CLK (CLK), + .RST (rst_i), + .SRST (SRST), + .RST_FULL_GEN (rst_full_gen_i), + .RST_FULL_FF (rst_full_ff_i), + .DIN (DIN), + .WR_EN (WR_EN), + .RD_EN (RD_EN_FIFO_IN), + .PROG_EMPTY_THRESH (PROG_EMPTY_THRESH), + .PROG_EMPTY_THRESH_ASSERT (PROG_EMPTY_THRESH_ASSERT), + .PROG_EMPTY_THRESH_NEGATE (PROG_EMPTY_THRESH_NEGATE), + .PROG_FULL_THRESH (PROG_FULL_THRESH), + .PROG_FULL_THRESH_ASSERT (PROG_FULL_THRESH_ASSERT), + .PROG_FULL_THRESH_NEGATE (PROG_FULL_THRESH_NEGATE), + .INJECTSBITERR (inject_sbit_err), + .INJECTDBITERR (inject_dbit_err), + .DOUT (DOUT_FIFO_OUT), + .FULL (FULL_FIFO_OUT), + .ALMOST_FULL (ALMOST_FULL_FIFO_OUT), + .WR_ACK (WR_ACK_FIFO_OUT), + .OVERFLOW (OVERFLOW_FIFO_OUT), + .EMPTY (EMPTY_FIFO_OUT), + .ALMOST_EMPTY (ALMOST_EMPTY_FIFO_OUT), + .VALID (VALID_FIFO_OUT), + .UNDERFLOW (UNDERFLOW_FIFO_OUT), + .DATA_COUNT (DATA_COUNT_FIFO_OUT), + .PROG_FULL (PROG_FULL_FIFO_OUT), + .PROG_EMPTY (PROG_EMPTY_FIFO_OUT), + .SBITERR (sbiterr_fifo_out), + .DBITERR (dbiterr_fifo_out) + ); +end +1 : begin : block1 + //Independent Clocks Behavioral Model + fifo_generator_v6_2_bhv_ver_as + #( + C_DATA_COUNT_WIDTH, + C_DIN_WIDTH, + C_DOUT_RST_VAL, + C_DOUT_WIDTH, + C_FULL_FLAGS_RST_VAL, + C_HAS_ALMOST_EMPTY, + C_HAS_ALMOST_FULL, + C_HAS_DATA_COUNT, + C_HAS_OVERFLOW, + C_HAS_RD_DATA_COUNT, + C_HAS_RST, + C_HAS_UNDERFLOW, + C_HAS_VALID, + C_HAS_WR_ACK, + C_HAS_WR_DATA_COUNT, + C_IMPLEMENTATION_TYPE, + C_MEMORY_TYPE, + C_OVERFLOW_LOW, + C_PRELOAD_LATENCY, + C_PRELOAD_REGS, + C_PROG_EMPTY_THRESH_ASSERT_VAL, + C_PROG_EMPTY_THRESH_NEGATE_VAL, + C_PROG_EMPTY_TYPE, + C_PROG_FULL_THRESH_ASSERT_VAL, + C_PROG_FULL_THRESH_NEGATE_VAL, + C_PROG_FULL_TYPE, + C_RD_DATA_COUNT_WIDTH, + C_RD_DEPTH, + C_RD_PNTR_WIDTH, + C_UNDERFLOW_LOW, + C_USE_DOUT_RST, + C_USE_EMBEDDED_REG, + C_USE_FWFT_DATA_COUNT, + C_VALID_LOW, + C_WR_ACK_LOW, + C_WR_DATA_COUNT_WIDTH, + C_WR_DEPTH, + C_WR_PNTR_WIDTH, + C_USE_ECC, + C_ENABLE_RST_SYNC, + C_ERROR_INJECTION_TYPE + ) + gen_as + ( + .WR_CLK (WR_CLK), + .RD_CLK (RD_CLK), + .RST (rst_i), + .RST_FULL_GEN (rst_full_gen_i), + .RST_FULL_FF (rst_full_ff_i), + .WR_RST (wr_rst_i), + .RD_RST (rd_rst_i), + .DIN (DIN), + .WR_EN (WR_EN), + .RD_EN (RD_EN_FIFO_IN), + .RD_EN_USER (RD_EN), + .PROG_EMPTY_THRESH (PROG_EMPTY_THRESH), + .PROG_EMPTY_THRESH_ASSERT (PROG_EMPTY_THRESH_ASSERT), + .PROG_EMPTY_THRESH_NEGATE (PROG_EMPTY_THRESH_NEGATE), + .PROG_FULL_THRESH (PROG_FULL_THRESH), + .PROG_FULL_THRESH_ASSERT (PROG_FULL_THRESH_ASSERT), + .PROG_FULL_THRESH_NEGATE (PROG_FULL_THRESH_NEGATE), + .INJECTSBITERR (inject_sbit_err), + .INJECTDBITERR (inject_dbit_err), + .USER_EMPTY_FB (EMPTY_P0_OUT), + .DOUT (DOUT_FIFO_OUT), + .FULL (FULL_FIFO_OUT), + .ALMOST_FULL (ALMOST_FULL_FIFO_OUT), + .WR_ACK (WR_ACK_FIFO_OUT), + .OVERFLOW (OVERFLOW_FIFO_OUT), + .EMPTY (EMPTY_FIFO_OUT), + .ALMOST_EMPTY (ALMOST_EMPTY_FIFO_OUT), + .VALID (VALID_FIFO_OUT), + .UNDERFLOW (UNDERFLOW_FIFO_OUT), + .RD_DATA_COUNT (RD_DATA_COUNT_FIFO_OUT), + .WR_DATA_COUNT (WR_DATA_COUNT_FIFO_OUT), + .PROG_FULL (PROG_FULL_FIFO_OUT), + .PROG_EMPTY (PROG_EMPTY_FIFO_OUT), + .SBITERR (sbiterr_fifo_out), + .DBITERR (dbiterr_fifo_out) + ); +end + +default : begin : block1 + //Independent Clocks Behavioral Model + fifo_generator_v6_2_bhv_ver_as + #( + C_DATA_COUNT_WIDTH, + C_DIN_WIDTH, + C_DOUT_RST_VAL, + C_DOUT_WIDTH, + C_FULL_FLAGS_RST_VAL, + C_HAS_ALMOST_EMPTY, + C_HAS_ALMOST_FULL, + C_HAS_DATA_COUNT, + C_HAS_OVERFLOW, + C_HAS_RD_DATA_COUNT, + C_HAS_RST, + C_HAS_UNDERFLOW, + C_HAS_VALID, + C_HAS_WR_ACK, + C_HAS_WR_DATA_COUNT, + C_IMPLEMENTATION_TYPE, + C_MEMORY_TYPE, + C_OVERFLOW_LOW, + C_PRELOAD_LATENCY, + C_PRELOAD_REGS, + C_PROG_EMPTY_THRESH_ASSERT_VAL, + C_PROG_EMPTY_THRESH_NEGATE_VAL, + C_PROG_EMPTY_TYPE, + C_PROG_FULL_THRESH_ASSERT_VAL, + C_PROG_FULL_THRESH_NEGATE_VAL, + C_PROG_FULL_TYPE, + C_RD_DATA_COUNT_WIDTH, + C_RD_DEPTH, + C_RD_PNTR_WIDTH, + C_UNDERFLOW_LOW, + C_USE_DOUT_RST, + C_USE_EMBEDDED_REG, + C_USE_FWFT_DATA_COUNT, + C_VALID_LOW, + C_WR_ACK_LOW, + C_WR_DATA_COUNT_WIDTH, + C_WR_DEPTH, + C_WR_PNTR_WIDTH, + C_USE_ECC, + C_ENABLE_RST_SYNC, + C_ERROR_INJECTION_TYPE + ) + gen_as + ( + .WR_CLK (WR_CLK), + .RD_CLK (RD_CLK), + .RST (rst_i), + .RST_FULL_GEN (rst_full_gen_i), + .RST_FULL_FF (rst_full_ff_i), + .WR_RST (wr_rst_i), + .RD_RST (rd_rst_i), + .DIN (DIN), + .WR_EN (WR_EN), + .RD_EN (RD_EN_FIFO_IN), + .RD_EN_USER (RD_EN), + .PROG_EMPTY_THRESH (PROG_EMPTY_THRESH), + .PROG_EMPTY_THRESH_ASSERT (PROG_EMPTY_THRESH_ASSERT), + .PROG_EMPTY_THRESH_NEGATE (PROG_EMPTY_THRESH_NEGATE), + .PROG_FULL_THRESH (PROG_FULL_THRESH), + .PROG_FULL_THRESH_ASSERT (PROG_FULL_THRESH_ASSERT), + .PROG_FULL_THRESH_NEGATE (PROG_FULL_THRESH_NEGATE), + .INJECTSBITERR (inject_sbit_err), + .INJECTDBITERR (inject_dbit_err), + .USER_EMPTY_FB (EMPTY_P0_OUT), + .DOUT (DOUT_FIFO_OUT), + .FULL (FULL_FIFO_OUT), + .ALMOST_FULL (ALMOST_FULL_FIFO_OUT), + .WR_ACK (WR_ACK_FIFO_OUT), + .OVERFLOW (OVERFLOW_FIFO_OUT), + .EMPTY (EMPTY_FIFO_OUT), + .ALMOST_EMPTY (ALMOST_EMPTY_FIFO_OUT), + .VALID (VALID_FIFO_OUT), + .UNDERFLOW (UNDERFLOW_FIFO_OUT), + .RD_DATA_COUNT (RD_DATA_COUNT_FIFO_OUT), + .WR_DATA_COUNT (WR_DATA_COUNT_FIFO_OUT), + .PROG_FULL (PROG_FULL_FIFO_OUT), + .PROG_EMPTY (PROG_EMPTY_FIFO_OUT), + .SBITERR (sbiterr_fifo_out), + .DBITERR (dbiterr_fifo_out) + ); +end + +endcase +endgenerate + + + //************************************************************************** + // Connect Internal Signals + // (Signals labeled internal_*) + // In the normal case, these signals tie directly to the FIFO's inputs and + // outputs. + // In the case of Preload Latency 0 or 1, there are intermediate + // signals between the internal FIFO and the preload logic. + //************************************************************************** + + + //*********************************************** + // If First-Word Fall-Through, instantiate + // the preload0 (FWFT) module + //*********************************************** + generate + if (C_PRELOAD_REGS==1 && C_PRELOAD_LATENCY==0) begin : block2 + + + fifo_generator_v6_2_bhv_ver_preload0 + #( + C_DOUT_RST_VAL, + C_DOUT_WIDTH, + C_HAS_RST, + C_ENABLE_RST_SYNC, + C_HAS_SRST, + C_USE_DOUT_RST, + C_USE_ECC, + C_VALID_LOW, + C_UNDERFLOW_LOW, + C_MEMORY_TYPE + ) + fgpl0 + ( + .RD_CLK (RD_CLK_P0_IN), + .RD_RST (RST_P0_IN), + .SRST (SRST), + .RD_EN (RD_EN_P0_IN), + .FIFOEMPTY (EMPTY_P0_IN), + .FIFODATA (DATA_P0_IN), + .FIFOSBITERR (sbiterr_fifo_out), + .FIFODBITERR (dbiterr_fifo_out), + .USERDATA (DATA_P0_OUT), + .USERVALID (VALID_P0_OUT), + .USEREMPTY (EMPTY_P0_OUT), + .USERALMOSTEMPTY (ALMOSTEMPTY_P0_OUT), + .USERUNDERFLOW (UNDERFLOW_P0_OUT), + .RAMVALID (RAMVALID_P0_OUT), + .FIFORDEN (RDEN_P0_OUT), + .USERSBITERR (SBITERR), + .USERDBITERR (DBITERR) + ); + + + //*********************************************** + // Connect inputs to preload (FWFT) module + //*********************************************** + //Connect the RD_CLK of the Preload (FWFT) module to CLK if we + // have a common-clock FIFO, or RD_CLK if we have an + // independent clock FIFO + assign RD_CLK_P0_IN = ((C_VERILOG_IMPL == 0) ? CLK : RD_CLK); + assign RST_P0_IN = (C_COMMON_CLOCK == 0) ? rd_rst_i : (C_HAS_RST == 1) ? rst_i : 0; + assign RD_EN_P0_IN = RD_EN; + assign EMPTY_P0_IN = EMPTY_FIFO_OUT; + assign DATA_P0_IN = DOUT_FIFO_OUT; + + //*********************************************** + // Connect outputs from preload (FWFT) module + //*********************************************** + assign DOUT = DATA_P0_OUT; + assign VALID = VALID_P0_OUT ; + assign EMPTY = EMPTY_P0_OUT; + assign ALMOST_EMPTY = ALMOSTEMPTY_P0_OUT; + assign UNDERFLOW = UNDERFLOW_P0_OUT ; + + assign RD_EN_FIFO_IN = RDEN_P0_OUT; + + + //*********************************************** + // Create DATA_COUNT from First-Word Fall-Through + // data count + //*********************************************** + assign DATA_COUNT = (C_USE_FWFT_DATA_COUNT == 0)? DATA_COUNT_FIFO_OUT: + (C_DATA_COUNT_WIDTH>C_RD_PNTR_WIDTH) ? DATA_COUNT_FWFT[C_RD_PNTR_WIDTH:0] : + DATA_COUNT_FWFT[C_RD_PNTR_WIDTH:C_RD_PNTR_WIDTH-C_DATA_COUNT_WIDTH+1]; + + //*********************************************** + // Create DATA_COUNT from First-Word Fall-Through + // data count + //*********************************************** + always @ (posedge RD_CLK or posedge RST_P0_IN) begin + if (RST_P0_IN) begin + EMPTY_P0_OUT_Q <= #`TCQ 1; + ALMOSTEMPTY_P0_OUT_Q <= #`TCQ 1; + end else begin + EMPTY_P0_OUT_Q <= #`TCQ EMPTY_P0_OUT; + ALMOSTEMPTY_P0_OUT_Q <= #`TCQ ALMOSTEMPTY_P0_OUT; + end + end //always + + + //*********************************************** + // logic for common-clock data count when FWFT is selected + //*********************************************** + initial begin + SS_FWFT_RD = 1'b0; + DATA_COUNT_FWFT = 0 ; + SS_FWFT_WR = 1'b0 ; + end //initial + + + //*********************************************** + // common-clock data count is implemented as an + // up-down counter. SS_FWFT_WR and SS_FWFT_RD + // are the up/down enables for the counter. + //*********************************************** + always @ (RD_EN or VALID_P0_OUT or WR_EN or FULL_FIFO_OUT) begin + if (C_VALID_LOW == 1) begin + SS_FWFT_RD = RD_EN && ~VALID_P0_OUT ; + end else begin + SS_FWFT_RD = RD_EN && VALID_P0_OUT ; + end + SS_FWFT_WR = (WR_EN && (~FULL_FIFO_OUT)) ; + end + + //*********************************************** + // common-clock data count is implemented as an + // up-down counter for FWFT. This always block + // calculates the counter. + //*********************************************** + always @ (posedge RD_CLK_P0_IN or posedge RST_P0_IN) begin + if (RST_P0_IN) begin + DATA_COUNT_FWFT <= #`TCQ 0; + end else begin + if (SRST && (C_HAS_SRST == 1) ) begin + DATA_COUNT_FWFT <= #`TCQ 0; + end else begin + case ( {SS_FWFT_WR, SS_FWFT_RD}) + 2'b00: DATA_COUNT_FWFT <= #`TCQ DATA_COUNT_FWFT ; + 2'b01: DATA_COUNT_FWFT <= #`TCQ DATA_COUNT_FWFT - 1 ; + 2'b10: DATA_COUNT_FWFT <= #`TCQ DATA_COUNT_FWFT + 1 ; + 2'b11: DATA_COUNT_FWFT <= #`TCQ DATA_COUNT_FWFT ; + endcase + end //if SRST + end //IF RST + end //always + + + end else begin : block2 //if !(C_PRELOAD_REGS==1 && C_PRELOAD_LATENCY==0) + + //*********************************************** + // If NOT First-Word Fall-Through, wire the outputs + // of the internal _ss or _as FIFO directly to the + // output, and do not instantiate the preload0 + // module. + //*********************************************** + + assign RD_CLK_P0_IN = 0; + assign RST_P0_IN = 0; + assign RD_EN_P0_IN = 0; + + assign RD_EN_FIFO_IN = RD_EN; + + assign DOUT = DOUT_FIFO_OUT; + assign DATA_P0_IN = 0; + assign VALID = VALID_FIFO_OUT; + assign EMPTY = EMPTY_FIFO_OUT; + assign ALMOST_EMPTY = ALMOST_EMPTY_FIFO_OUT; + assign EMPTY_P0_IN = 0; + assign UNDERFLOW = UNDERFLOW_FIFO_OUT; + assign DATA_COUNT = DATA_COUNT_FIFO_OUT; + assign SBITERR = sbiterr_fifo_out; + assign DBITERR = dbiterr_fifo_out; + + end //if !(C_PRELOAD_REGS==1 && C_PRELOAD_LATENCY==0) + endgenerate + + + //*********************************************** + // Connect user flags to internal signals + //*********************************************** + + //If we are using extra logic for the FWFT data count, then override the + //RD_DATA_COUNT output when we are EMPTY or ALMOST_EMPTY. + //RD_DATA_COUNT is 0 when EMPTY and 1 when ALMOST_EMPTY. + generate + if (C_USE_FWFT_DATA_COUNT==1 && (C_RD_DATA_COUNT_WIDTH>C_RD_PNTR_WIDTH) ) begin : block3 + assign RD_DATA_COUNT = (EMPTY_P0_OUT_Q | RST_P0_IN) ? 0 : (ALMOSTEMPTY_P0_OUT_Q ? 1 : RD_DATA_COUNT_FIFO_OUT); + end //block3 + endgenerate + + //If we are using extra logic for the FWFT data count, then override the + //RD_DATA_COUNT output when we are EMPTY or ALMOST_EMPTY. + //Due to asymmetric ports, RD_DATA_COUNT is 0 when EMPTY or ALMOST_EMPTY. + generate + if (C_USE_FWFT_DATA_COUNT==1 && (C_RD_DATA_COUNT_WIDTH <=C_RD_PNTR_WIDTH) ) begin : block30 + assign RD_DATA_COUNT = (EMPTY_P0_OUT_Q | RST_P0_IN) ? 0 : (ALMOSTEMPTY_P0_OUT_Q ? 0 : RD_DATA_COUNT_FIFO_OUT); + end //block30 + endgenerate + + //If we are not using extra logic for the FWFT data count, + //then connect RD_DATA_COUNT to the RD_DATA_COUNT from the + //internal FIFO instance + generate + if (C_USE_FWFT_DATA_COUNT==0 ) begin : block31 + assign RD_DATA_COUNT = RD_DATA_COUNT_FIFO_OUT; + end + endgenerate + + //Always connect WR_DATA_COUNT to the WR_DATA_COUNT from the internal + //FIFO instance + generate + if (C_USE_FWFT_DATA_COUNT==1) begin : block4 + assign WR_DATA_COUNT = WR_DATA_COUNT_FIFO_OUT; + end + else begin : block4 + assign WR_DATA_COUNT = WR_DATA_COUNT_FIFO_OUT; + end + endgenerate + + + //Connect other flags to the internal FIFO instance + assign FULL = FULL_FIFO_OUT; + assign ALMOST_FULL = ALMOST_FULL_FIFO_OUT; + assign WR_ACK = WR_ACK_FIFO_OUT; + assign OVERFLOW = OVERFLOW_FIFO_OUT; + assign PROG_FULL = PROG_FULL_FIFO_OUT; + assign PROG_EMPTY = PROG_EMPTY_FIFO_OUT; + + + /************************************************************************** + * find_log2 + * Returns the 'log2' value for the input value for the supported ratios + ***************************************************************************/ + function integer find_log2; + input integer int_val; + integer i,j; + begin + i = 1; + j = 0; + for (i = 1; i < int_val; i = i*2) begin + j = j + 1; + end + find_log2 = j; + end + endfunction + + // if an asynchronous FIFO has been selected, display a message that the FIFO + // will not be cycle-accurate in simulation + initial begin + if (C_IMPLEMENTATION_TYPE == 2) begin + $display("WARNING: Behavioral models for independent clock FIFO configurations do not model synchronization delays. The behavioral models are functionally correct, and will represent the behavior of the configured FIFO. See the FIFO Generator User Guide for more information."); + end else if (C_MEMORY_TYPE == 4) begin + $display("FAILURE : Behavioral models for Virtex-4, Virtex-5 and Virtex-6 built-in FIFO configurations is currently not supported. Please select the structural simulation model option in CORE Generator. You can enable this in CORE Generator by selecting Project -> Project Options -> Generation tab -> Structural Simulation. See the FIFO Generator User Guide for more information."); + $finish; + end + + if (C_WR_PNTR_WIDTH != find_log2(C_WR_DEPTH)) begin + $display("FAILURE : C_WR_PNTR_WIDTH is not log2 of C_WR_DEPTH."); + $finish; + end + + if (C_RD_PNTR_WIDTH != find_log2(C_RD_DEPTH)) begin + $display("FAILURE : C_RD_PNTR_WIDTH is not log2 of C_RD_DEPTH."); + $finish; + end + + end //initial + + /************************************************************************** + * Internal reset logic + **************************************************************************/ + assign wr_rst_i = (C_HAS_RST == 1 || C_ENABLE_RST_SYNC == 0) ? wr_rst_reg : 0; + assign rd_rst_i = (C_HAS_RST == 1 || C_ENABLE_RST_SYNC == 0) ? rd_rst_reg : 0; + assign rst_i = C_HAS_RST ? rst_reg : 0; + + wire rst_2_sync; + wire clk_2_sync = (C_COMMON_CLOCK == 1) ? CLK : WR_CLK; + generate + if (C_ENABLE_RST_SYNC == 0) begin : gnrst_sync + always @* begin + wr_rst_reg <= WR_RST; + rd_rst_reg <= RD_RST; + rst_reg <= 1'b0; + end + assign rst_2_sync = WR_RST; + end else if (C_HAS_RST == 1 && C_COMMON_CLOCK == 0) begin : gic_rst + assign wr_rst_comb = !wr_rst_asreg_d2 && wr_rst_asreg; + assign rd_rst_comb = !rd_rst_asreg_d2 && rd_rst_asreg; + assign rst_2_sync = RST; + + always @(posedge WR_CLK or posedge RST) begin + if (RST == 1'b1) begin + wr_rst_asreg <= #`TCQ 1'b1; + end else begin + if (wr_rst_asreg_d1 == 1'b1) begin + wr_rst_asreg <= #`TCQ 1'b0; + end else begin + wr_rst_asreg <= #`TCQ wr_rst_asreg; + end + end + end + + always @(posedge WR_CLK) begin + wr_rst_asreg_d1 <= #`TCQ wr_rst_asreg; + wr_rst_asreg_d2 <= #`TCQ wr_rst_asreg_d1; + end + + always @(posedge WR_CLK or posedge wr_rst_comb) begin + if (wr_rst_comb == 1'b1) begin + wr_rst_reg <= #`TCQ 1'b1; + end else begin + wr_rst_reg <= #`TCQ 1'b0; + end + end + + always @(posedge RD_CLK or posedge RST) begin + if (RST == 1'b1) begin + rd_rst_asreg <= #`TCQ 1'b1; + end else begin + if (rd_rst_asreg_d1 == 1'b1) begin + rd_rst_asreg <= #`TCQ 1'b0; + end else begin + rd_rst_asreg <= #`TCQ rd_rst_asreg; + end + end + end + + always @(posedge RD_CLK) begin + rd_rst_asreg_d1 <= #`TCQ rd_rst_asreg; + rd_rst_asreg_d2 <= #`TCQ rd_rst_asreg_d1; + end + + always @(posedge RD_CLK or posedge rd_rst_comb) begin + if (rd_rst_comb == 1'b1) begin + rd_rst_reg <= #`TCQ 1'b1; + end else begin + rd_rst_reg <= #`TCQ 1'b0; + end + end + end else if (C_HAS_RST == 1 && C_COMMON_CLOCK == 1) begin : gcc_rst + assign rst_comb = !rst_asreg_d2 && rst_asreg; + assign rst_2_sync = RST; + + always @(posedge CLK or posedge RST) begin + if (RST == 1'b1) begin + rst_asreg <= #`TCQ 1'b1; + end else begin + if (rst_asreg_d1 == 1'b1) begin + rst_asreg <= #`TCQ 1'b0; + end else begin + rst_asreg <= #`TCQ rst_asreg; + end + end + end + + always @(posedge CLK) begin + rst_asreg_d1 <= #`TCQ rst_asreg; + rst_asreg_d2 <= #`TCQ rst_asreg_d1; + end + + always @(posedge CLK or posedge rst_comb) begin + if (rst_comb == 1'b1) begin + rst_reg <= #`TCQ 1'b1; + end else begin + rst_reg <= #`TCQ 1'b0; + end + end + end + endgenerate + + reg rst_d1 = 1'b0; + reg rst_d2 = 1'b0; + reg rst_d3 = 1'b0; + reg rst_d4 = 1'b0; + generate + if ((C_HAS_RST == 1 || C_HAS_SRST == 1 || C_ENABLE_RST_SYNC == 0) && C_FULL_FLAGS_RST_VAL == 1) begin : grstd1 + // RST_FULL_GEN replaces the reset falling edge detection used to de-assert + // FULL, ALMOST_FULL & PROG_FULL flags if C_FULL_FLAGS_RST_VAL = 1. + + // RST_FULL_FF goes to the reset pin of the final flop of FULL, ALMOST_FULL & + // PROG_FULL + + always @ (posedge rst_2_sync or posedge clk_2_sync) begin + if (rst_2_sync) begin + rst_d1 <= 1'b1; + rst_d2 <= 1'b1; + rst_d3 <= 1'b1; + rst_d4 <= 1'b0; + end else begin + if (SRST) begin + rst_d1 <= #`TCQ 1'b1; + rst_d2 <= #`TCQ 1'b1; + rst_d3 <= #`TCQ 1'b1; + rst_d4 <= #`TCQ 1'b0; + end else begin + rst_d1 <= #`TCQ 1'b0; + rst_d2 <= #`TCQ rst_d1; + rst_d3 <= #`TCQ rst_d2; + rst_d4 <= #`TCQ rst_d3; + end + end + end + assign rst_full_ff_i = (C_HAS_SRST == 0) ? rst_d2 : 1'b0 ; + assign rst_full_gen_i = rst_d4; + + end else if ((C_HAS_RST == 1 || C_HAS_SRST == 1 || C_ENABLE_RST_SYNC == 0) && C_FULL_FLAGS_RST_VAL == 0) begin : gnrst_full + assign rst_full_gen_i = 1'b0; + assign rst_full_ff_i = (C_COMMON_CLOCK == 0) ? wr_rst_i : rst_i; + end + endgenerate + +endmodule //FIFO_GENERATOR_V6_2 + + + +/******************************************************************************* + * Declaration of Independent-Clocks FIFO Module + ******************************************************************************/ +module fifo_generator_v6_2_bhv_ver_as + + /*************************************************************************** + * Declare user parameters and their defaults + ***************************************************************************/ + #( + parameter C_DATA_COUNT_WIDTH = 2, + parameter C_DIN_WIDTH = 8, + parameter C_DOUT_RST_VAL = "", + parameter C_DOUT_WIDTH = 8, + parameter C_FULL_FLAGS_RST_VAL = 1, + parameter C_HAS_ALMOST_EMPTY = 0, + parameter C_HAS_ALMOST_FULL = 0, + parameter C_HAS_DATA_COUNT = 0, + parameter C_HAS_OVERFLOW = 0, + parameter C_HAS_RD_DATA_COUNT = 0, + parameter C_HAS_RST = 0, + parameter C_HAS_UNDERFLOW = 0, + parameter C_HAS_VALID = 0, + parameter C_HAS_WR_ACK = 0, + parameter C_HAS_WR_DATA_COUNT = 0, + parameter C_IMPLEMENTATION_TYPE = 0, + parameter C_MEMORY_TYPE = 1, + parameter C_OVERFLOW_LOW = 0, + parameter C_PRELOAD_LATENCY = 1, + parameter C_PRELOAD_REGS = 0, + parameter C_PROG_EMPTY_THRESH_ASSERT_VAL = 0, + parameter C_PROG_EMPTY_THRESH_NEGATE_VAL = 0, + parameter C_PROG_EMPTY_TYPE = 0, + parameter C_PROG_FULL_THRESH_ASSERT_VAL = 0, + parameter C_PROG_FULL_THRESH_NEGATE_VAL = 0, + parameter C_PROG_FULL_TYPE = 0, + parameter C_RD_DATA_COUNT_WIDTH = 2, + parameter C_RD_DEPTH = 256, + parameter C_RD_PNTR_WIDTH = 8, + parameter C_UNDERFLOW_LOW = 0, + parameter C_USE_DOUT_RST = 0, + parameter C_USE_EMBEDDED_REG = 0, + parameter C_USE_FWFT_DATA_COUNT = 0, + parameter C_VALID_LOW = 0, + parameter C_WR_ACK_LOW = 0, + parameter C_WR_DATA_COUNT_WIDTH = 2, + parameter C_WR_DEPTH = 256, + parameter C_WR_PNTR_WIDTH = 8, + parameter C_USE_ECC = 0, + parameter C_ENABLE_RST_SYNC = 1, + parameter C_ERROR_INJECTION_TYPE = 0 + ) + + /*************************************************************************** + * Declare Input and Output Ports + ***************************************************************************/ + ( + input [C_DIN_WIDTH-1:0] DIN, + input [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH, + input [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_ASSERT, + input [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_NEGATE, + input [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH, + input [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_ASSERT, + input [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_NEGATE, + input RD_CLK, + input RD_EN, + input RD_EN_USER, + input RST, + input RST_FULL_GEN, + input RST_FULL_FF, + input WR_RST, + input RD_RST, + input WR_CLK, + input WR_EN, + input INJECTDBITERR, + input INJECTSBITERR, + input USER_EMPTY_FB, + output reg ALMOST_EMPTY = 1'b1, + output reg ALMOST_FULL = C_FULL_FLAGS_RST_VAL, + output [C_DOUT_WIDTH-1:0] DOUT, + output reg EMPTY = 1'b1, + output reg FULL = C_FULL_FLAGS_RST_VAL, + output OVERFLOW, + output PROG_EMPTY, + output PROG_FULL, + output VALID, + output [C_RD_DATA_COUNT_WIDTH-1:0] RD_DATA_COUNT, + output UNDERFLOW, + output WR_ACK, + output [C_WR_DATA_COUNT_WIDTH-1:0] WR_DATA_COUNT, + output SBITERR, + output DBITERR + ); + + reg [C_RD_PNTR_WIDTH:0] rd_data_count_int = 0; + reg [C_WR_PNTR_WIDTH:0] wr_data_count_int = 0; + reg [C_WR_PNTR_WIDTH:0] wdc_fwft_ext_as = 0; + + + /*************************************************************************** + * Parameters used as constants + **************************************************************************/ + //When RST is present, set FULL reset value to '1'. + //If core has no RST, make sure FULL powers-on as '0'. + parameter C_DEPTH_RATIO_WR = + (C_WR_DEPTH>C_RD_DEPTH) ? (C_WR_DEPTH/C_RD_DEPTH) : 1; + parameter C_DEPTH_RATIO_RD = + (C_RD_DEPTH>C_WR_DEPTH) ? (C_RD_DEPTH/C_WR_DEPTH) : 1; + parameter C_FIFO_WR_DEPTH = C_WR_DEPTH - 1; + parameter C_FIFO_RD_DEPTH = C_RD_DEPTH - 1; + + // C_DEPTH_RATIO_WR | C_DEPTH_RATIO_RD | C_PNTR_WIDTH | EXTRA_WORDS_DC + // -----------------|------------------|-----------------|--------------- + // 1 | 8 | C_RD_PNTR_WIDTH | 2 + // 1 | 4 | C_RD_PNTR_WIDTH | 2 + // 1 | 2 | C_RD_PNTR_WIDTH | 2 + // 1 | 1 | C_WR_PNTR_WIDTH | 2 + // 2 | 1 | C_WR_PNTR_WIDTH | 4 + // 4 | 1 | C_WR_PNTR_WIDTH | 8 + // 8 | 1 | C_WR_PNTR_WIDTH | 16 + + localparam C_PNTR_WIDTH = (C_WR_PNTR_WIDTH>=C_RD_PNTR_WIDTH) ? C_WR_PNTR_WIDTH : C_RD_PNTR_WIDTH; + wire [C_PNTR_WIDTH:0] EXTRA_WORDS_DC = (C_DEPTH_RATIO_WR == 1) ? 2 : (2 * C_DEPTH_RATIO_WR/C_DEPTH_RATIO_RD); + + parameter [31:0] reads_per_write = C_DIN_WIDTH/C_DOUT_WIDTH; + + parameter [31:0] log2_reads_per_write = log2_val(reads_per_write); + + parameter [31:0] writes_per_read = C_DOUT_WIDTH/C_DIN_WIDTH; + + parameter [31:0] log2_writes_per_read = log2_val(writes_per_read); + + + + /************************************************************************** + * FIFO Contents Tracking and Data Count Calculations + *************************************************************************/ + + // Memory which will be used to simulate a FIFO + reg [C_DIN_WIDTH-1:0] memory[C_WR_DEPTH-1:0]; + // Local parameters used to determine whether to inject ECC error or not + localparam SYMMETRIC_PORT = (C_DIN_WIDTH == C_DOUT_WIDTH) ? 1 : 0; + localparam ERR_INJECTION = (C_ERROR_INJECTION_TYPE != 0) ? 1 : 0; + localparam ENABLE_ERR_INJECTION = C_USE_ECC && SYMMETRIC_PORT && ERR_INJECTION; + // Array that holds the error injection type (single/double bit error) on + // a specific write operation, which is returned on read to corrupt the + // output data. + reg [1:0] ecc_err[C_WR_DEPTH-1:0]; + + //The amount of data stored in the FIFO at any time is given + // by num_wr_bits (in the WR_CLK domain) and num_rd_bits (in the RD_CLK + // domain. + //num_wr_bits is calculated by considering the total words in the FIFO, + // and the state of the read pointer (which may not have yet crossed clock + // domains.) + //num_rd_bits is calculated by considering the total words in the FIFO, + // and the state of the write pointer (which may not have yet crossed clock + // domains.) + reg [31:0] num_wr_bits; + reg [31:0] num_rd_bits; + reg [31:0] next_num_wr_bits; + reg [31:0] next_num_rd_bits; + + //The write pointer - tracks write operations + // (Works opposite to core: wr_ptr is a DOWN counter) + reg [31:0] wr_ptr; + reg [C_WR_PNTR_WIDTH-1:0] wr_pntr = 0; // UP counter: Rolls back to 0 when reaches to max value. + reg [C_WR_PNTR_WIDTH-1:0] wr_pntr_rd1 = 0; + reg [C_WR_PNTR_WIDTH-1:0] wr_pntr_rd2 = 0; + reg [C_WR_PNTR_WIDTH-1:0] wr_pntr_rd3 = 0; + wire [C_RD_PNTR_WIDTH-1:0] adj_wr_pntr_rd; + reg [C_WR_PNTR_WIDTH-1:0] wr_pntr_rd = 0; + wire wr_rst_i = WR_RST; + reg wr_rst_d1 =0; + + //The read pointer - tracks read operations + // (rd_ptr Works opposite to core: rd_ptr is a DOWN counter) + reg [31:0] rd_ptr; + reg [C_RD_PNTR_WIDTH-1:0] rd_pntr = 0; // UP counter: Rolls back to 0 when reaches to max value. + reg [C_RD_PNTR_WIDTH-1:0] rd_pntr_wr1 = 0; + reg [C_RD_PNTR_WIDTH-1:0] rd_pntr_wr2 = 0; + reg [C_RD_PNTR_WIDTH-1:0] rd_pntr_wr3 = 0; + reg [C_RD_PNTR_WIDTH-1:0] rd_pntr_wr4 = 0; + wire [C_WR_PNTR_WIDTH-1:0] adj_rd_pntr_wr; + reg [C_RD_PNTR_WIDTH-1:0] rd_pntr_wr = 0; + wire rd_rst_i = RD_RST; + wire ram_rd_en; + reg ram_rd_en_d1 = 1'b0; + + + // Delayed ram_rd_en is needed only for STD Embedded register option + generate + if (C_PRELOAD_LATENCY == 2) begin : grd_d + always @ (posedge RD_CLK or posedge rd_rst_i) begin + if (rd_rst_i) + ram_rd_en_d1 <= #`TCQ 1'b0; + else + ram_rd_en_d1 <= #`TCQ ram_rd_en; + end + end + endgenerate + + // Write pointer adjustment based on pointers width for EMPTY/ALMOST_EMPTY generation + generate + if (C_RD_PNTR_WIDTH > C_WR_PNTR_WIDTH) begin : rdg // Read depth greater than write depth + assign adj_wr_pntr_rd[C_RD_PNTR_WIDTH-1:C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH] = wr_pntr_rd; + assign adj_wr_pntr_rd[C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH-1:0] = 0; + end else begin : rdl // Read depth lesser than or equal to write depth + assign adj_wr_pntr_rd = wr_pntr_rd[C_WR_PNTR_WIDTH-1:C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH]; + end + endgenerate + + // Generate Empty and Almost Empty + // ram_rd_en used to determine EMPTY should depend on the EMPTY. + assign ram_rd_en = RD_EN & !EMPTY; + assign empty_int = ((adj_wr_pntr_rd == rd_pntr) || (ram_rd_en && (adj_wr_pntr_rd == (rd_pntr+1'h1)))); + assign almost_empty_int = ((adj_wr_pntr_rd == (rd_pntr+1'h1)) || (ram_rd_en && (adj_wr_pntr_rd == (rd_pntr+2'h2)))); + + // Register Empty and Almost Empty + always @ (posedge RD_CLK or posedge rd_rst_i) + begin + if (rd_rst_i) begin + EMPTY <= #`TCQ 1'b1; + ALMOST_EMPTY <= #`TCQ 1'b1; + rd_data_count_int <= #`TCQ {C_RD_PNTR_WIDTH-1{1'b0}}; + end else begin + rd_data_count_int <= #`TCQ {(adj_wr_pntr_rd[C_RD_PNTR_WIDTH-1:0] - rd_pntr[C_RD_PNTR_WIDTH-1:0]), 1'b0}; + + if (empty_int) + EMPTY <= #`TCQ 1'b1; + else + EMPTY <= #`TCQ 1'b0; + + if (!EMPTY) begin + if (almost_empty_int) + ALMOST_EMPTY <= #`TCQ 1'b1; + else + ALMOST_EMPTY <= #`TCQ 1'b0; + end + end // rd_rst_i + end // always + + // Read pointer adjustment based on pointers width for EMPTY/ALMOST_EMPTY generation + generate + if (C_WR_PNTR_WIDTH > C_RD_PNTR_WIDTH) begin : wdg // Write depth greater than read depth + assign adj_rd_pntr_wr[C_WR_PNTR_WIDTH-1:C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH] = rd_pntr_wr; + assign adj_rd_pntr_wr[C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH-1:0] = 0; + end else begin : wdl // Write depth lesser than or equal to read depth + assign adj_rd_pntr_wr = rd_pntr_wr[C_RD_PNTR_WIDTH-1:C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH]; + end + endgenerate + + // Generate FULL and ALMOST_FULL + // ram_wr_en used to determine FULL should depend on the FULL. + assign ram_wr_en = WR_EN & !FULL; + assign full_int = ((adj_rd_pntr_wr == (wr_pntr+1'h1)) || (ram_wr_en && (adj_rd_pntr_wr == (wr_pntr+2'h2)))); + assign almost_full_int = ((adj_rd_pntr_wr == (wr_pntr+2'h2)) || (ram_wr_en && (adj_rd_pntr_wr == (wr_pntr+3'h3)))); + + // Register FULL and ALMOST_FULL Empty + always @ (posedge WR_CLK or posedge RST_FULL_FF) + begin + if (RST_FULL_FF) begin + FULL <= #`TCQ C_FULL_FLAGS_RST_VAL; + ALMOST_FULL <= #`TCQ C_FULL_FLAGS_RST_VAL; + wr_data_count_int <= #`TCQ {C_WR_DATA_COUNT_WIDTH-1{1'b0}}; + end else begin + wr_data_count_int <= #`TCQ {(wr_pntr[C_WR_PNTR_WIDTH-1:0] - adj_rd_pntr_wr[C_WR_PNTR_WIDTH-1:0]), 1'b0}; + if (full_int) begin + FULL <= #`TCQ 1'b1; + end else begin + FULL <= #`TCQ 1'b0; + end + + if (RST_FULL_GEN) begin + ALMOST_FULL <= #`TCQ 1'b0; + end else if (!FULL) begin + if (almost_full_int) + ALMOST_FULL <= #`TCQ 1'b1; + else + ALMOST_FULL <= #`TCQ 1'b0; + end + end // wr_rst_i + end // always + + // Determine which stage in FWFT registers are valid + reg stage1_valid = 0; + reg stage2_valid = 0; + generate + if (C_PRELOAD_LATENCY == 0) begin : grd_fwft_proc + always @ (posedge RD_CLK or posedge rd_rst_i) begin + if (rd_rst_i) begin + stage1_valid <= #`TCQ 0; + stage2_valid <= #`TCQ 0; + end else begin + + if (!stage1_valid && !stage2_valid) begin + if (!EMPTY) + stage1_valid <= #`TCQ 1'b1; + else + stage1_valid <= #`TCQ 1'b0; + end else if (stage1_valid && !stage2_valid) begin + if (EMPTY) begin + stage1_valid <= #`TCQ 1'b0; + stage2_valid <= #`TCQ 1'b1; + end else begin + stage1_valid <= #`TCQ 1'b1; + stage2_valid <= #`TCQ 1'b1; + end + end else if (!stage1_valid && stage2_valid) begin + if (EMPTY && RD_EN_USER) begin + stage1_valid <= #`TCQ 1'b0; + stage2_valid <= #`TCQ 1'b0; + end else if (!EMPTY && RD_EN_USER) begin + stage1_valid <= #`TCQ 1'b1; + stage2_valid <= #`TCQ 1'b0; + end else if (!EMPTY && !RD_EN_USER) begin + stage1_valid <= #`TCQ 1'b1; + stage2_valid <= #`TCQ 1'b1; + end else begin + stage1_valid <= #`TCQ 1'b0; + stage2_valid <= #`TCQ 1'b1; + end + end else if (stage1_valid && stage2_valid) begin + if (EMPTY && RD_EN_USER) begin + stage1_valid <= #`TCQ 1'b0; + stage2_valid <= #`TCQ 1'b1; + end else begin + stage1_valid <= #`TCQ 1'b1; + stage2_valid <= #`TCQ 1'b1; + end + end else begin + stage1_valid <= #`TCQ 1'b0; + stage2_valid <= #`TCQ 1'b0; + end + end // rd_rst_i + end // always + end + endgenerate + + //Pointers passed into opposite clock domain + reg [31:0] wr_ptr_rdclk; + reg [31:0] wr_ptr_rdclk_next; + reg [31:0] rd_ptr_wrclk; + reg [31:0] rd_ptr_wrclk_next; + + //Amount of data stored in the FIFO scaled to the narrowest (deepest) port + // (Do not include data in FWFT stages) + //Used to calculate PROG_EMPTY. + wire [31:0] num_read_words_pe = + num_rd_bits/(C_DOUT_WIDTH/C_DEPTH_RATIO_WR); + + //Amount of data stored in the FIFO scaled to the narrowest (deepest) port + // (Do not include data in FWFT stages) + //Used to calculate PROG_FULL. + wire [31:0] num_write_words_pf = + num_wr_bits/(C_DIN_WIDTH/C_DEPTH_RATIO_RD); + + /************************** + * Read Data Count + *************************/ + + reg [31:0] num_read_words_dc; + reg [C_RD_DATA_COUNT_WIDTH-1:0] num_read_words_sized_i; + + always @(num_rd_bits) begin + if (C_USE_FWFT_DATA_COUNT) begin + + //If using extra logic for FWFT Data Counts, + // then scale FIFO contents to read domain, + // and add two read words for FWFT stages + //This value is only a temporary value and not used in the code. + num_read_words_dc = (num_rd_bits/C_DOUT_WIDTH+2); + + //Trim the read words for use with RD_DATA_COUNT + num_read_words_sized_i = + num_read_words_dc[C_RD_PNTR_WIDTH : C_RD_PNTR_WIDTH-C_RD_DATA_COUNT_WIDTH+1]; + + end else begin + + //If not using extra logic for FWFT Data Counts, + // then scale FIFO contents to read domain. + //This value is only a temporary value and not used in the code. + num_read_words_dc = num_rd_bits/C_DOUT_WIDTH; + + //Trim the read words for use with RD_DATA_COUNT + num_read_words_sized_i = + num_read_words_dc[C_RD_PNTR_WIDTH-1 : C_RD_PNTR_WIDTH-C_RD_DATA_COUNT_WIDTH]; + + end //if (C_USE_FWFT_DATA_COUNT) + end //always + + + /************************** + * Write Data Count + *************************/ + + reg [31:0] num_write_words_dc; + reg [C_WR_DATA_COUNT_WIDTH-1:0] num_write_words_sized_i; + + always @(num_wr_bits) begin + if (C_USE_FWFT_DATA_COUNT) begin + + //Calculate the Data Count value for the number of write words, + // when using First-Word Fall-Through with extra logic for Data + // Counts. This takes into consideration the number of words that + // are expected to be stored in the FWFT register stages (it always + // assumes they are filled). + //This value is scaled to the Write Domain. + //The expression (((A-1)/B))+1 divides A/B, but takes the + // ceiling of the result. + //When num_wr_bits==0, set the result manually to prevent + // division errors. + //EXTRA_WORDS_DC is the number of words added to write_words + // due to FWFT. + //This value is only a temporary value and not used in the code. + num_write_words_dc = (num_wr_bits==0) ? EXTRA_WORDS_DC : (((num_wr_bits-1)/C_DIN_WIDTH)+1) + EXTRA_WORDS_DC ; + + //Trim the write words for use with WR_DATA_COUNT + num_write_words_sized_i = + num_write_words_dc[C_WR_PNTR_WIDTH : C_WR_PNTR_WIDTH-C_WR_DATA_COUNT_WIDTH+1]; + + end else begin + + //Calculate the Data Count value for the number of write words, when NOT + // using First-Word Fall-Through with extra logic for Data Counts. This + // calculates only the number of words in the internal FIFO. + //The expression (((A-1)/B))+1 divides A/B, but takes the + // ceiling of the result. + //This value is scaled to the Write Domain. + //When num_wr_bits==0, set the result manually to prevent + // division errors. + //This value is only a temporary value and not used in the code. + num_write_words_dc = (num_wr_bits==0) ? 0 : ((num_wr_bits-1)/C_DIN_WIDTH)+1; + + //Trim the read words for use with RD_DATA_COUNT + num_write_words_sized_i = + num_write_words_dc[C_WR_PNTR_WIDTH-1 : C_WR_PNTR_WIDTH-C_WR_DATA_COUNT_WIDTH]; + + end //if (C_USE_FWFT_DATA_COUNT) + end //always + + + + /*************************************************************************** + * Internal registers and wires + **************************************************************************/ + + //Temporary signals used for calculating the model's outputs. These + //are only used in the assign statements immediately following wire, + //parameter, and function declarations. + wire [C_DOUT_WIDTH-1:0] ideal_dout_out; + wire valid_i; + wire valid_out; + wire underflow_i; + + //Ideal FIFO signals. These are the raw output of the behavioral model, + //which behaves like an ideal FIFO. + reg [1:0] err_type = 0; + reg [1:0] err_type_d1 = 0; + reg [C_DOUT_WIDTH-1:0] ideal_dout = 0; + reg [C_DOUT_WIDTH-1:0] ideal_dout_d1 = 0; + reg ideal_wr_ack = 0; + reg ideal_valid = 0; + reg ideal_overflow = 0; + reg ideal_underflow = 0; + reg ideal_prog_full = 0; + reg ideal_prog_empty = 1; + reg [C_WR_DATA_COUNT_WIDTH-1 : 0] ideal_wr_count = 0; + reg [C_RD_DATA_COUNT_WIDTH-1 : 0] ideal_rd_count = 0; + + //Assorted reg values for delayed versions of signals + reg valid_d1 = 0; + + + //user specified value for reseting the size of the fifo + reg [C_DOUT_WIDTH-1:0] dout_reset_val = 0; + + //temporary registers for WR_RESPONSE_LATENCY feature + + integer tmp_wr_listsize; + integer tmp_rd_listsize; + + //Signal for registered version of prog full and empty + + //Threshold values for Programmable Flags + integer prog_empty_actual_thresh_assert; + integer prog_empty_actual_thresh_negate; + integer prog_full_actual_thresh_assert; + integer prog_full_actual_thresh_negate; + + + /**************************************************************************** + * Function Declarations + ***************************************************************************/ + + /************************************************************************** + * write_fifo + * This task writes a word to the FIFO memory and updates the + * write pointer. + * FIFO size is relative to write domain. + ***************************************************************************/ + task write_fifo; + begin + memory[wr_ptr] <= DIN; + wr_pntr <= #`TCQ wr_pntr + 1; + // Store the type of error injection (double/single) on write + case (C_ERROR_INJECTION_TYPE) + 3: ecc_err[wr_ptr] <= {INJECTDBITERR,INJECTSBITERR}; + 2: ecc_err[wr_ptr] <= {INJECTDBITERR,1'b0}; + 1: ecc_err[wr_ptr] <= {1'b0,INJECTSBITERR}; + default: ecc_err[wr_ptr] <= 0; + endcase + // (Works opposite to core: wr_ptr is a DOWN counter) + if (wr_ptr == 0) begin + wr_ptr <= C_WR_DEPTH - 1; + end else begin + wr_ptr <= wr_ptr - 1; + end + end + endtask // write_fifo + + /************************************************************************** + * read_fifo + * This task reads a word from the FIFO memory and updates the read + * pointer. It's output is the ideal_dout bus. + * FIFO size is relative to write domain. + ***************************************************************************/ + task read_fifo; + integer i; + reg [C_DOUT_WIDTH-1:0] tmp_dout; + reg [C_DIN_WIDTH-1:0] memory_read; + reg [31:0] tmp_rd_ptr; + reg [31:0] rd_ptr_high; + reg [31:0] rd_ptr_low; + reg [1:0] tmp_ecc_err; + begin + rd_pntr <= #`TCQ rd_pntr + 1; + // output is wider than input + if (reads_per_write == 0) begin + tmp_dout = 0; + tmp_rd_ptr = (rd_ptr << log2_writes_per_read)+(writes_per_read-1); + for (i = writes_per_read - 1; i >= 0; i = i - 1) begin + tmp_dout = tmp_dout << C_DIN_WIDTH; + tmp_dout = tmp_dout | memory[tmp_rd_ptr]; + + // (Works opposite to core: rd_ptr is a DOWN counter) + if (tmp_rd_ptr == 0) begin + tmp_rd_ptr = C_WR_DEPTH - 1; + end else begin + tmp_rd_ptr = tmp_rd_ptr - 1; + end + end + + // output is symmetric + end else if (reads_per_write == 1) begin + tmp_dout = memory[rd_ptr][C_DIN_WIDTH-1:0]; + // Retreive the error injection type. Based on the error injection type + // corrupt the output data. + tmp_ecc_err = ecc_err[rd_ptr]; + if (ENABLE_ERR_INJECTION && C_DIN_WIDTH == C_DOUT_WIDTH) begin + if (tmp_ecc_err[1]) begin // Corrupt the output data only for double bit error + if (C_DOUT_WIDTH == 1) + tmp_dout = tmp_dout[C_DOUT_WIDTH-1:0]; + else if (C_DOUT_WIDTH == 2) + tmp_dout = {~tmp_dout[C_DOUT_WIDTH-1],~tmp_dout[C_DOUT_WIDTH-2]}; + else + tmp_dout = {~tmp_dout[C_DOUT_WIDTH-1],~tmp_dout[C_DOUT_WIDTH-2],(tmp_dout << 2)}; + end else begin + tmp_dout = tmp_dout[C_DOUT_WIDTH-1:0]; + end + err_type <= {tmp_ecc_err[1], tmp_ecc_err[0] & !tmp_ecc_err[1]}; + end else begin + err_type <= 0; + end + + // input is wider than output + end else begin + rd_ptr_high = rd_ptr >> log2_reads_per_write; + rd_ptr_low = rd_ptr & (reads_per_write - 1); + memory_read = memory[rd_ptr_high]; + tmp_dout = memory_read >> (rd_ptr_low*C_DOUT_WIDTH); + end + ideal_dout <= tmp_dout; + + // (Works opposite to core: rd_ptr is a DOWN counter) + if (rd_ptr == 0) begin + rd_ptr <= C_RD_DEPTH - 1; + end else begin + rd_ptr <= rd_ptr - 1; + end + end + endtask + + /************************************************************************** + * log2_val + * Returns the 'log2' value for the input value for the supported ratios + ***************************************************************************/ + function [31:0] log2_val; + input [31:0] binary_val; + + begin + if (binary_val == 8) begin + log2_val = 3; + end else if (binary_val == 4) begin + log2_val = 2; + end else begin + log2_val = 1; + end + end + endfunction + + /*********************************************************************** + * hexstr_conv + * Converts a string of type hex to a binary value (for C_DOUT_RST_VAL) + ***********************************************************************/ + function [C_DOUT_WIDTH-1:0] hexstr_conv; + input [(C_DOUT_WIDTH*8)-1:0] def_data; + + integer index,i,j; + reg [3:0] bin; + + begin + index = 0; + hexstr_conv = 'b0; + for( i=C_DOUT_WIDTH-1; i>=0; i=i-1 ) + begin + case (def_data[7:0]) + 8'b00000000 : + begin + bin = 4'b0000; + i = -1; + end + 8'b00110000 : bin = 4'b0000; + 8'b00110001 : bin = 4'b0001; + 8'b00110010 : bin = 4'b0010; + 8'b00110011 : bin = 4'b0011; + 8'b00110100 : bin = 4'b0100; + 8'b00110101 : bin = 4'b0101; + 8'b00110110 : bin = 4'b0110; + 8'b00110111 : bin = 4'b0111; + 8'b00111000 : bin = 4'b1000; + 8'b00111001 : bin = 4'b1001; + 8'b01000001 : bin = 4'b1010; + 8'b01000010 : bin = 4'b1011; + 8'b01000011 : bin = 4'b1100; + 8'b01000100 : bin = 4'b1101; + 8'b01000101 : bin = 4'b1110; + 8'b01000110 : bin = 4'b1111; + 8'b01100001 : bin = 4'b1010; + 8'b01100010 : bin = 4'b1011; + 8'b01100011 : bin = 4'b1100; + 8'b01100100 : bin = 4'b1101; + 8'b01100101 : bin = 4'b1110; + 8'b01100110 : bin = 4'b1111; + default : + begin + bin = 4'bx; + end + endcase + for( j=0; j<4; j=j+1) + begin + if ((index*4)+j < C_DOUT_WIDTH) + begin + hexstr_conv[(index*4)+j] = bin[j]; + end + end + index = index + 1; + def_data = def_data >> 8; + end + end + endfunction + + /************************************************************************* + * Initialize Signals for clean power-on simulation + *************************************************************************/ + initial begin + num_wr_bits = 0; + num_rd_bits = 0; + next_num_wr_bits = 0; + next_num_rd_bits = 0; + rd_ptr = C_RD_DEPTH - 1; + wr_ptr = C_WR_DEPTH - 1; + wr_pntr = 0; + rd_pntr = 0; + rd_ptr_wrclk = rd_ptr; + wr_ptr_rdclk = wr_ptr; + dout_reset_val = hexstr_conv(C_DOUT_RST_VAL); + ideal_dout = dout_reset_val; + err_type = 0; + ideal_dout_d1 = dout_reset_val; + ideal_wr_ack = 1'b0; + ideal_valid = 1'b0; + valid_d1 = 1'b0; + ideal_overflow = 1'b0; + ideal_underflow = 1'b0; + ideal_wr_count = 0; + ideal_rd_count = 0; + ideal_prog_full = 1'b0; + ideal_prog_empty = 1'b1; + end + + + /************************************************************************* + * Connect the module inputs and outputs to the internal signals of the + * behavioral model. + *************************************************************************/ + //Inputs + /* + wire [C_DIN_WIDTH-1:0] DIN; + wire [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH; + wire [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_ASSERT; + wire [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_NEGATE; + wire [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH; + wire [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_ASSERT; + wire [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_NEGATE; + wire RD_CLK; + wire RD_EN; + wire RST; + wire WR_CLK; + wire WR_EN; + */ + + //*************************************************************************** + // Dout may change behavior based on latency + //*************************************************************************** + assign ideal_dout_out[C_DOUT_WIDTH-1:0] = (C_PRELOAD_LATENCY==2 && + (C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1))? + ideal_dout_d1: ideal_dout; + assign DOUT[C_DOUT_WIDTH-1:0] = ideal_dout_out; + + //*************************************************************************** + // Assign SBITERR and DBITERR based on latency + //*************************************************************************** + assign SBITERR = (C_ERROR_INJECTION_TYPE == 1 || C_ERROR_INJECTION_TYPE == 3) && + (C_PRELOAD_LATENCY == 2 && + (C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1)) ? + err_type_d1[0]: err_type[0]; + assign DBITERR = (C_ERROR_INJECTION_TYPE == 2 || C_ERROR_INJECTION_TYPE == 3) && + (C_PRELOAD_LATENCY==2 && (C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1)) ? + err_type_d1[1]: err_type[1]; + + + //*************************************************************************** + // Overflow may be active-low + //*************************************************************************** + generate + if (C_HAS_OVERFLOW==1) begin : blockOF1 + assign OVERFLOW = ideal_overflow ? !C_OVERFLOW_LOW : C_OVERFLOW_LOW; + end + endgenerate + + assign PROG_EMPTY = ideal_prog_empty; + assign PROG_FULL = ideal_prog_full; + + //*************************************************************************** + // Valid may change behavior based on latency or active-low + //*************************************************************************** + generate + if (C_HAS_VALID==1) begin : blockVL1 + assign valid_i = (C_PRELOAD_LATENCY==0) ? (RD_EN & ~EMPTY) : ideal_valid; + assign valid_out = (C_PRELOAD_LATENCY==2 && + (C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1))? + valid_d1: valid_i; + assign VALID = valid_out ? !C_VALID_LOW : C_VALID_LOW; + end + endgenerate + + + //*************************************************************************** + // Underflow may change behavior based on latency or active-low + //*************************************************************************** + generate + if (C_HAS_UNDERFLOW==1) begin : blockUF1 + assign underflow_i = (C_PRELOAD_LATENCY==0) ? (RD_EN & EMPTY) : ideal_underflow; + assign UNDERFLOW = underflow_i ? !C_UNDERFLOW_LOW : C_UNDERFLOW_LOW; + end + endgenerate + + //*************************************************************************** + // Write acknowledge may be active low + //*************************************************************************** + generate + if (C_HAS_WR_ACK==1) begin : blockWK1 + assign WR_ACK = ideal_wr_ack ? !C_WR_ACK_LOW : C_WR_ACK_LOW; + end + endgenerate + + + //*************************************************************************** + // Generate RD_DATA_COUNT if Use Extra Logic option is selected + //*************************************************************************** + generate + if (C_HAS_WR_DATA_COUNT == 1 && C_USE_FWFT_DATA_COUNT == 1) begin : wdc_fwft_ext + + reg [C_PNTR_WIDTH-1:0] adjusted_wr_pntr = 0; + reg [C_PNTR_WIDTH-1:0] adjusted_rd_pntr = 0; + wire [C_PNTR_WIDTH-1:0] diff_wr_rd_tmp; + wire [C_PNTR_WIDTH:0] diff_wr_rd; + reg [C_PNTR_WIDTH:0] wr_data_count_i = 0; + always @* begin + if (C_WR_PNTR_WIDTH > C_RD_PNTR_WIDTH) begin + adjusted_wr_pntr = wr_pntr; + adjusted_rd_pntr = 0; + adjusted_rd_pntr[C_PNTR_WIDTH-1:C_PNTR_WIDTH-C_RD_PNTR_WIDTH] = rd_pntr_wr; + end else if (C_WR_PNTR_WIDTH < C_RD_PNTR_WIDTH) begin + adjusted_rd_pntr = rd_pntr_wr; + adjusted_wr_pntr = 0; + adjusted_wr_pntr[C_PNTR_WIDTH-1:C_PNTR_WIDTH-C_WR_PNTR_WIDTH] = wr_pntr; + end else begin + adjusted_wr_pntr = wr_pntr; + adjusted_rd_pntr = rd_pntr_wr; + end + end // always @* + + assign diff_wr_rd_tmp = adjusted_wr_pntr - adjusted_rd_pntr; + assign diff_wr_rd = {1'b0,diff_wr_rd_tmp}; + + always @ (posedge wr_rst_i or posedge WR_CLK) + begin + if (wr_rst_i) + wr_data_count_i <= #`TCQ 0; + else + wr_data_count_i <= #`TCQ diff_wr_rd + EXTRA_WORDS_DC; + end // always @ (posedge WR_CLK or posedge WR_CLK) + + always @* begin + if (C_WR_PNTR_WIDTH >= C_RD_PNTR_WIDTH) + wdc_fwft_ext_as = wr_data_count_i[C_PNTR_WIDTH:0]; + else + wdc_fwft_ext_as = wr_data_count_i[C_PNTR_WIDTH:C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH]; + end // always @* + end // wdc_fwft_ext + endgenerate + + //*************************************************************************** + // Generate RD_DATA_COUNT if Use Extra Logic option is selected + //*************************************************************************** + reg [C_RD_PNTR_WIDTH:0] rdc_fwft_ext_as = 0; + + generate + if (C_HAS_RD_DATA_COUNT == 1 && C_USE_FWFT_DATA_COUNT == 1) begin : rdc_fwft_ext + reg [C_RD_PNTR_WIDTH-1:0] adjusted_wr_pntr_rd = 0; + wire [C_RD_PNTR_WIDTH-1:0] diff_rd_wr_tmp; + wire [C_RD_PNTR_WIDTH:0] diff_rd_wr; + always @* begin + if (C_RD_PNTR_WIDTH > C_WR_PNTR_WIDTH) begin + adjusted_wr_pntr_rd = 0; + adjusted_wr_pntr_rd[C_RD_PNTR_WIDTH-1:C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH] = wr_pntr_rd; + end else begin + adjusted_wr_pntr_rd = wr_pntr_rd[C_WR_PNTR_WIDTH-1:C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH]; + end + end // always @* + + assign diff_rd_wr_tmp = adjusted_wr_pntr_rd - rd_pntr; + assign diff_rd_wr = {1'b0,diff_rd_wr_tmp}; + + always @ (posedge rd_rst_i or posedge RD_CLK) + begin + if (rd_rst_i) begin + rdc_fwft_ext_as <= #`TCQ 0; + end else begin + if (!stage2_valid) + rdc_fwft_ext_as <= #`TCQ 0; + else if (!stage1_valid && stage2_valid) + rdc_fwft_ext_as <= #`TCQ 1; + else + rdc_fwft_ext_as <= #`TCQ diff_rd_wr + 2'h2; + end + end // always @ (posedge WR_CLK or posedge WR_CLK) + end // rdc_fwft_ext + endgenerate + + //*************************************************************************** + // Assign the read data count value only if it is selected, + // otherwise output zeros. + //*************************************************************************** + generate + if (C_HAS_RD_DATA_COUNT == 1) begin : grdc + assign RD_DATA_COUNT[C_RD_DATA_COUNT_WIDTH-1:0] = C_USE_FWFT_DATA_COUNT ? + rdc_fwft_ext_as[C_RD_PNTR_WIDTH:C_RD_PNTR_WIDTH+1-C_RD_DATA_COUNT_WIDTH] : + rd_data_count_int[C_RD_PNTR_WIDTH:C_RD_PNTR_WIDTH+1-C_RD_DATA_COUNT_WIDTH]; + end + endgenerate + + generate + if (C_HAS_RD_DATA_COUNT == 0) begin : gnrdc + assign RD_DATA_COUNT[C_RD_DATA_COUNT_WIDTH-1:0] = {C_RD_DATA_COUNT_WIDTH-1{1'b0}}; + end + endgenerate + + //*************************************************************************** + // Assign the write data count value only if it is selected, + // otherwise output zeros + //*************************************************************************** + generate + if (C_HAS_WR_DATA_COUNT == 1) begin : gwdc + assign WR_DATA_COUNT[C_WR_DATA_COUNT_WIDTH-1:0] = (C_USE_FWFT_DATA_COUNT == 1) ? + wdc_fwft_ext_as[C_WR_PNTR_WIDTH:C_WR_PNTR_WIDTH+1-C_WR_DATA_COUNT_WIDTH] : + wr_data_count_int[C_WR_PNTR_WIDTH:C_WR_PNTR_WIDTH+1-C_WR_DATA_COUNT_WIDTH]; + end + endgenerate + + generate + if (C_HAS_WR_DATA_COUNT == 0) begin : gnwdc + assign WR_DATA_COUNT[C_WR_DATA_COUNT_WIDTH-1:0] = {C_WR_DATA_COUNT_WIDTH-1{1'b0}}; + end + endgenerate + + + /************************************************************************** + * Assorted registers for delayed versions of signals + **************************************************************************/ + //Capture delayed version of valid + generate + if (C_HAS_VALID==1) begin : blockVL2 + always @(posedge RD_CLK or posedge rd_rst_i) begin + if (rd_rst_i == 1'b1) begin + valid_d1 <= #`TCQ 1'b0; + end else begin + valid_d1 <= #`TCQ valid_i; + end + end + end + endgenerate + + //Capture delayed version of dout + always @(posedge RD_CLK or posedge rd_rst_i) begin + if (rd_rst_i == 1'b1) begin + // Reset err_type only if ECC is not selected + if (C_USE_ECC == 0) + err_type_d1 <= #`TCQ 0; + end else if (ram_rd_en_d1) begin + ideal_dout_d1 <= #`TCQ ideal_dout; + err_type_d1 <= #`TCQ err_type; + end + end + + /************************************************************************** + * Overflow and Underflow Flag calculation + * (handled separately because they don't support rst) + **************************************************************************/ + generate + if (C_HAS_OVERFLOW==1) begin : blockOF2 + always @(posedge WR_CLK) begin + ideal_overflow <= #`TCQ WR_EN & FULL; + end + end + endgenerate + + generate + if (C_HAS_UNDERFLOW==1) begin : blockUF2 + always @(posedge RD_CLK) begin + ideal_underflow <= #`TCQ EMPTY & RD_EN; + end + end + endgenerate + + /************************************************************************** + * Write Domain Logic + **************************************************************************/ + reg [C_WR_PNTR_WIDTH-1:0] diff_pntr = 0; + always @(posedge WR_CLK or posedge wr_rst_i) begin : gen_fifo_w + + /****** Reset fifo (case 1)***************************************/ + if (wr_rst_i == 1'b1) begin + num_wr_bits <= #`TCQ 0; + next_num_wr_bits = #`TCQ 0; + wr_ptr <= #`TCQ C_WR_DEPTH - 1; + rd_ptr_wrclk <= #`TCQ C_RD_DEPTH - 1; + ideal_wr_ack <= #`TCQ 0; + ideal_wr_count <= #`TCQ 0; + tmp_wr_listsize = #`TCQ 0; + rd_ptr_wrclk_next <= #`TCQ 0; + wr_pntr <= #`TCQ 0; + wr_pntr_rd1 <= #`TCQ 0; + rd_pntr_wr2 <= #`TCQ 0; + rd_pntr_wr3 <= #`TCQ 0; + rd_pntr_wr4 <= #`TCQ 0; + rd_pntr_wr <= #`TCQ 0; + + + end else begin //wr_rst_i==0 + + wr_pntr_rd1 <= #`TCQ wr_pntr; + + // Synchronize the rd_pntr in read domain + rd_pntr_wr2 <= #`TCQ rd_pntr_wr1; + rd_pntr_wr3 <= #`TCQ rd_pntr_wr2; + rd_pntr_wr4 <= #`TCQ rd_pntr_wr2; + rd_pntr_wr <= #`TCQ rd_pntr_wr4; + + + + //Determine the current number of words in the FIFO + tmp_wr_listsize = (C_DEPTH_RATIO_RD > 1) ? num_wr_bits/C_DOUT_WIDTH : + num_wr_bits/C_DIN_WIDTH; + rd_ptr_wrclk_next = rd_ptr; + if (rd_ptr_wrclk < rd_ptr_wrclk_next) begin + next_num_wr_bits = num_wr_bits - + C_DOUT_WIDTH*(rd_ptr_wrclk + C_RD_DEPTH + - rd_ptr_wrclk_next); + end else begin + next_num_wr_bits = num_wr_bits - + C_DOUT_WIDTH*(rd_ptr_wrclk - rd_ptr_wrclk_next); + end + + //If this is a write, handle the write by adding the value + // to the linked list, and updating all outputs appropriately + if (WR_EN == 1'b1) begin + if (FULL == 1'b1) begin + + //If the FIFO is full, do NOT perform the write, + // update flags accordingly + if ((tmp_wr_listsize + C_DEPTH_RATIO_RD - 1)/C_DEPTH_RATIO_RD + >= C_FIFO_WR_DEPTH) begin + //write unsuccessful - do not change contents + + //Do not acknowledge the write + ideal_wr_ack <= #`TCQ 0; + //Reminder that FIFO is still full + + ideal_wr_count <= #`TCQ num_write_words_sized_i; + + //If the FIFO is one from full, but reporting full + end else + if ((tmp_wr_listsize + C_DEPTH_RATIO_RD - 1)/C_DEPTH_RATIO_RD == + C_FIFO_WR_DEPTH-1) begin + //No change to FIFO + + //Write not successful + ideal_wr_ack <= #`TCQ 0; + //With DEPTH-1 words in the FIFO, it is almost_full + + ideal_wr_count <= #`TCQ num_write_words_sized_i; + + + //If the FIFO is completely empty, but it is + // reporting FULL for some reason (like reset) + end else + if ((tmp_wr_listsize + C_DEPTH_RATIO_RD - 1)/C_DEPTH_RATIO_RD <= + C_FIFO_WR_DEPTH-2) begin + //No change to FIFO + + //Write not successful + ideal_wr_ack <= #`TCQ 0; + //FIFO is really not close to full, so change flag status. + + ideal_wr_count <= #`TCQ num_write_words_sized_i; + end //(tmp_wr_listsize == 0) + + end else begin + + //If the FIFO is full, do NOT perform the write, + // update flags accordingly + if ((tmp_wr_listsize + C_DEPTH_RATIO_RD - 1)/C_DEPTH_RATIO_RD >= + C_FIFO_WR_DEPTH) begin + //write unsuccessful - do not change contents + + //Do not acknowledge the write + ideal_wr_ack <= #`TCQ 0; + //Reminder that FIFO is still full + + ideal_wr_count <= #`TCQ num_write_words_sized_i; + + //If the FIFO is one from full + end else + if ((tmp_wr_listsize + C_DEPTH_RATIO_RD - 1)/C_DEPTH_RATIO_RD == + C_FIFO_WR_DEPTH-1) begin + //Add value on DIN port to FIFO + write_fifo; + next_num_wr_bits = next_num_wr_bits + C_DIN_WIDTH; + + //Write successful, so issue acknowledge + // and no error + ideal_wr_ack <= #`TCQ 1; + //This write is CAUSING the FIFO to go full + + ideal_wr_count <= #`TCQ num_write_words_sized_i; + + //If the FIFO is 2 from full + end else + if ((tmp_wr_listsize + C_DEPTH_RATIO_RD - 1)/C_DEPTH_RATIO_RD == + C_FIFO_WR_DEPTH-2) begin + //Add value on DIN port to FIFO + write_fifo; + next_num_wr_bits = next_num_wr_bits + C_DIN_WIDTH; + //Write successful, so issue acknowledge + // and no error + ideal_wr_ack <= #`TCQ 1; + //Still 2 from full + + ideal_wr_count <= #`TCQ num_write_words_sized_i; + + //If the FIFO is not close to being full + end else + if ((tmp_wr_listsize + C_DEPTH_RATIO_RD - 1)/C_DEPTH_RATIO_RD < + C_FIFO_WR_DEPTH-2) begin + //Add value on DIN port to FIFO + write_fifo; + next_num_wr_bits = next_num_wr_bits + C_DIN_WIDTH; + //Write successful, so issue acknowledge + // and no error + ideal_wr_ack <= #`TCQ 1; + //Not even close to full. + + ideal_wr_count <= num_write_words_sized_i; + + end + + end + + end else begin //(WR_EN == 1'b1) + + //If user did not attempt a write, then do not + // give ack or err + ideal_wr_ack <= #`TCQ 0; + ideal_wr_count <= #`TCQ num_write_words_sized_i; + end + num_wr_bits <= #`TCQ next_num_wr_bits; + rd_ptr_wrclk <= #`TCQ rd_ptr; + + end //wr_rst_i==0 + end // write always + + + /*************************************************************************** + * Programmable FULL flags + ***************************************************************************/ + + reg [C_WR_PNTR_WIDTH-1:0] pf_thr_assert_val = 0; + reg [C_WR_PNTR_WIDTH-1:0] pf_thr_negate_val = 0; + + always @(posedge WR_CLK or posedge RST_FULL_FF) begin : gen_pf + + if (RST_FULL_FF == 1'b1) begin + diff_pntr <= 0; + ideal_prog_full <= #`TCQ C_FULL_FLAGS_RST_VAL; + end else begin + if (ram_wr_en) + diff_pntr <= #`TCQ (wr_pntr - adj_rd_pntr_wr + 2'h1); + else if (!ram_wr_en) + diff_pntr <= #`TCQ (wr_pntr - adj_rd_pntr_wr); + + if (C_PRELOAD_REGS == 1 && C_PRELOAD_LATENCY == 0) begin // FWFT + pf_thr_assert_val <= #`TCQ C_PROG_FULL_THRESH_ASSERT_VAL - EXTRA_WORDS_DC; + pf_thr_negate_val <= #`TCQ C_PROG_FULL_THRESH_NEGATE_VAL - EXTRA_WORDS_DC; + end else begin + pf_thr_assert_val <= #`TCQ C_PROG_FULL_THRESH_ASSERT_VAL; + pf_thr_negate_val <= #`TCQ C_PROG_FULL_THRESH_NEGATE_VAL; + end + + if (RST_FULL_GEN) + ideal_prog_full <= #`TCQ 0; + //Single Programmable Full Constant Threshold + else if (C_PROG_FULL_TYPE == 1) begin + if (FULL == 0) begin + if (diff_pntr >= pf_thr_assert_val) + ideal_prog_full <= #`TCQ 1; + else + ideal_prog_full <= #`TCQ 0; + end else + ideal_prog_full <= #`TCQ ideal_prog_full; + //Two Programmable Full Constant Thresholds + end else if (C_PROG_FULL_TYPE == 2) begin + if (FULL == 0) begin + if (diff_pntr >= pf_thr_assert_val) + ideal_prog_full <= #`TCQ 1; + else if (diff_pntr < pf_thr_negate_val) + ideal_prog_full <= #`TCQ 0; + else + ideal_prog_full <= #`TCQ ideal_prog_full; + end else + ideal_prog_full <= #`TCQ ideal_prog_full; + //Single Programmable Full Threshold Input + end else if (C_PROG_FULL_TYPE == 3) begin + if (FULL == 0) begin + if (C_PRELOAD_REGS == 1 && C_PRELOAD_LATENCY == 0) begin // FWFT + if (diff_pntr >= (PROG_FULL_THRESH - EXTRA_WORDS_DC)) + ideal_prog_full <= #`TCQ 1; + else + ideal_prog_full <= #`TCQ 0; + end else begin // STD + if (diff_pntr >= PROG_FULL_THRESH) + ideal_prog_full <= #`TCQ 1; + else + ideal_prog_full <= #`TCQ 0; + end + end else + ideal_prog_full <= #`TCQ ideal_prog_full; + //Two Programmable Full Threshold Inputs + end else if (C_PROG_FULL_TYPE == 4) begin + if (FULL == 0) begin + if (C_PRELOAD_REGS == 1 && C_PRELOAD_LATENCY == 0) begin // FWFT + if (diff_pntr >= (PROG_FULL_THRESH_ASSERT - EXTRA_WORDS_DC)) + ideal_prog_full <= #`TCQ 1; + else if (diff_pntr < (PROG_FULL_THRESH_NEGATE - EXTRA_WORDS_DC)) + ideal_prog_full <= #`TCQ 0; + else + ideal_prog_full <= #`TCQ ideal_prog_full; + end else begin // STD + if (diff_pntr >= PROG_FULL_THRESH_ASSERT) + ideal_prog_full <= #`TCQ 1; + else if (diff_pntr < PROG_FULL_THRESH_NEGATE) + ideal_prog_full <= #`TCQ 0; + else + ideal_prog_full <= #`TCQ ideal_prog_full; + end + end else + ideal_prog_full <= #`TCQ ideal_prog_full; + end // C_PROG_FULL_TYPE + + end //wr_rst_i==0 + end // + + + /************************************************************************** + * Read Domain Logic + **************************************************************************/ + + + /********************************************************* + * Programmable EMPTY flags + *********************************************************/ + //Determine the Assert and Negate thresholds for Programmable Empty + + reg [C_RD_PNTR_WIDTH-1:0] pe_thr_assert_val = 0; + reg [C_RD_PNTR_WIDTH-1:0] pe_thr_negate_val = 0; + reg [C_RD_PNTR_WIDTH-1:0] diff_pntr_rd = 0; +// always @* begin +// +// if (C_PROG_EMPTY_TYPE == 3) begin +// +// // If empty input threshold is selected, then subtract 2 for FWFT to +// // compensate the FWFT stage, otherwise assign the input value. +// if (C_PRELOAD_REGS == 1 && C_PRELOAD_LATENCY == 0) // FWFT +// pe_thr_assert_val <= PROG_EMPTY_THRESH - 2'h2; +// else +// pe_thr_assert_val <= PROG_EMPTY_THRESH; +// +// end else if (C_PROG_EMPTY_TYPE == 4) begin +// +// // If empty input threshold is selected, then subtract 2 for FWFT to +// // compensate the FWFT stage, otherwise assign the input value. +// if (C_PRELOAD_REGS == 1 && C_PRELOAD_LATENCY == 0) begin // FWFT +// pe_thr_assert_val <= PROG_EMPTY_THRESH_ASSERT - 2'h2; +// pe_thr_negate_val <= PROG_EMPTY_THRESH_NEGATE - 2'h2; +// end else begin +// pe_thr_assert_val <= PROG_EMPTY_THRESH_ASSERT; +// pe_thr_negate_val <= PROG_EMPTY_THRESH_NEGATE; +// end +// end else begin +// +// if (C_PRELOAD_REGS == 1 && C_PRELOAD_LATENCY == 0) begin // FWFT +// pe_thr_assert_val <= C_PROG_EMPTY_THRESH_ASSERT_VAL - 2; +// pe_thr_negate_val <= C_PROG_EMPTY_THRESH_NEGATE_VAL - 2; +// end else begin +// pe_thr_assert_val <= C_PROG_EMPTY_THRESH_ASSERT_VAL; +// pe_thr_negate_val <= C_PROG_EMPTY_THRESH_NEGATE_VAL; +// end +// end +// end // always @* + + always @(posedge RD_CLK or posedge rd_rst_i) begin : gen_pe + + if (rd_rst_i) begin + diff_pntr_rd <= #`TCQ 0; + ideal_prog_empty <= #`TCQ 1'b1; + end else begin + if (ram_rd_en) + diff_pntr_rd <= #`TCQ (adj_wr_pntr_rd - rd_pntr) - 1'h1; + else if (!ram_rd_en) + diff_pntr_rd <= #`TCQ (adj_wr_pntr_rd - rd_pntr); + else + diff_pntr_rd <= #`TCQ diff_pntr_rd; + + if (C_PROG_EMPTY_TYPE == 1) begin + if (EMPTY == 0) begin + if (diff_pntr_rd <= pe_thr_assert_val) + ideal_prog_empty <= #`TCQ 1; + else + ideal_prog_empty <= #`TCQ 0; + end else + ideal_prog_empty <= #`TCQ ideal_prog_empty; + end else if (C_PROG_EMPTY_TYPE == 2) begin + if (EMPTY == 0) begin + if (diff_pntr_rd <= pe_thr_assert_val) + ideal_prog_empty <= #`TCQ 1; + else if (diff_pntr_rd > pe_thr_negate_val) + ideal_prog_empty <= #`TCQ 0; + else + ideal_prog_empty <= #`TCQ ideal_prog_empty; + end else + ideal_prog_empty <= #`TCQ ideal_prog_empty; + end else if (C_PROG_EMPTY_TYPE == 3) begin + if (EMPTY == 0) begin + if (diff_pntr_rd <= pe_thr_assert_val) + ideal_prog_empty <= #`TCQ 1; + else + ideal_prog_empty <= #`TCQ 0; + end else + ideal_prog_empty <= #`TCQ ideal_prog_empty; + end else if (C_PROG_EMPTY_TYPE == 4) begin + if (EMPTY == 0) begin + if (diff_pntr_rd >= pe_thr_assert_val) + ideal_prog_empty <= #`TCQ 1; + else if (diff_pntr_rd > pe_thr_negate_val) + ideal_prog_empty <= #`TCQ 0; + else + ideal_prog_empty <= #`TCQ ideal_prog_empty; + end else + ideal_prog_empty <= #`TCQ ideal_prog_empty; + end //C_PROG_EMPTY_TYPE + end + + if (C_PROG_EMPTY_TYPE == 3) begin + + // If empty input threshold is selected, then subtract 2 for FWFT to + // compensate the FWFT stage, otherwise assign the input value. + if (C_PRELOAD_REGS == 1 && C_PRELOAD_LATENCY == 0) // FWFT + pe_thr_assert_val <= PROG_EMPTY_THRESH - 2'h2; + else + pe_thr_assert_val <= PROG_EMPTY_THRESH; + + end else if (C_PROG_EMPTY_TYPE == 4) begin + + // If empty input threshold is selected, then subtract 2 for FWFT to + // compensate the FWFT stage, otherwise assign the input value. + if (C_PRELOAD_REGS == 1 && C_PRELOAD_LATENCY == 0) begin // FWFT + pe_thr_assert_val <= PROG_EMPTY_THRESH_ASSERT - 2'h2; + pe_thr_negate_val <= PROG_EMPTY_THRESH_NEGATE - 2'h2; + end else begin + pe_thr_assert_val <= PROG_EMPTY_THRESH_ASSERT; + pe_thr_negate_val <= PROG_EMPTY_THRESH_NEGATE; + end + end else begin + + if (C_PRELOAD_REGS == 1 && C_PRELOAD_LATENCY == 0) begin // FWFT + pe_thr_assert_val <= C_PROG_EMPTY_THRESH_ASSERT_VAL - 2; + pe_thr_negate_val <= C_PROG_EMPTY_THRESH_NEGATE_VAL - 2; + end else begin + pe_thr_assert_val <= C_PROG_EMPTY_THRESH_ASSERT_VAL; + pe_thr_negate_val <= C_PROG_EMPTY_THRESH_NEGATE_VAL; + end + end + + end + + // block memory has a synchronous reset + always @(posedge RD_CLK) begin : gen_fifo_blkmemdout + // make it consistent with the core. + if (rd_rst_i) begin + // Reset err_type only if ECC is not selected + if (C_USE_ECC == 0 && C_MEMORY_TYPE < 2) + err_type <= #`TCQ 0; + + // BRAM resets synchronously + if (C_USE_DOUT_RST == 1 && C_MEMORY_TYPE < 2) begin + ideal_dout <= #`TCQ dout_reset_val; + ideal_dout_d1 <= #`TCQ dout_reset_val; + end + end + end //always + + always @(posedge RD_CLK or posedge rd_rst_i) begin : gen_fifo_r + + /****** Reset fifo (case 1)***************************************/ + if (rd_rst_i) begin + num_rd_bits <= #`TCQ 0; + next_num_rd_bits = #`TCQ 0; + rd_ptr <= #`TCQ C_RD_DEPTH -1; + rd_pntr <= #`TCQ 0; + rd_pntr_wr1 <= #`TCQ 0; + wr_pntr_rd2 <= #`TCQ 0; + wr_pntr_rd3 <= #`TCQ 0; + wr_pntr_rd <= #`TCQ 0; + wr_ptr_rdclk <= #`TCQ C_WR_DEPTH -1; + + // DRAM resets asynchronously + if (C_MEMORY_TYPE == 2 && C_USE_DOUT_RST == 1) + ideal_dout <= #`TCQ dout_reset_val; + + // Reset err_type only if ECC is not selected + if (C_USE_ECC == 0) + err_type <= #`TCQ 0; + ideal_valid <= #`TCQ 1'b0; + ideal_rd_count <= #`TCQ 0; + + end else begin //rd_rst_i==0 + + rd_pntr_wr1 <= #`TCQ rd_pntr; + + // Synchronize the wr_pntr in read domain + wr_pntr_rd2 <= #`TCQ wr_pntr_rd1; + wr_pntr_rd3 <= #`TCQ wr_pntr_rd2; + wr_pntr_rd <= #`TCQ wr_pntr_rd3; + + + + //Determine the current number of words in the FIFO + tmp_rd_listsize = (C_DEPTH_RATIO_WR > 1) ? num_rd_bits/C_DIN_WIDTH : + num_rd_bits/C_DOUT_WIDTH; + wr_ptr_rdclk_next = wr_ptr; + + if (wr_ptr_rdclk < wr_ptr_rdclk_next) begin + next_num_rd_bits = num_rd_bits + + C_DIN_WIDTH*(wr_ptr_rdclk +C_WR_DEPTH + - wr_ptr_rdclk_next); + end else begin + next_num_rd_bits = num_rd_bits + + C_DIN_WIDTH*(wr_ptr_rdclk - wr_ptr_rdclk_next); + end + + /*****************************************************************/ + // Read Operation - Read Latency 1 + /*****************************************************************/ + if (C_PRELOAD_LATENCY==1 || C_PRELOAD_LATENCY==2) begin + ideal_valid <= #`TCQ 1'b0; + + if (ram_rd_en == 1'b1) begin + + if (EMPTY == 1'b1) begin + + //If the FIFO is completely empty, and is reporting empty + if (tmp_rd_listsize/C_DEPTH_RATIO_WR <= 0) + begin + //Do not change the contents of the FIFO + + //Do not acknowledge the read from empty FIFO + ideal_valid <= #`TCQ 1'b0; + //Reminder that FIFO is still empty + + ideal_rd_count <= #`TCQ num_read_words_sized_i; + end // if (tmp_rd_listsize <= 0) + + //If the FIFO is one from empty, but it is reporting empty + else if (tmp_rd_listsize/C_DEPTH_RATIO_WR == 1) + begin + //Do not change the contents of the FIFO + + //Do not acknowledge the read from empty FIFO + ideal_valid <= #`TCQ 1'b0; + //Note that FIFO is no longer empty, but is almost empty (has one word left) + + ideal_rd_count <= #`TCQ num_read_words_sized_i; + + end // if (tmp_rd_listsize == 1) + + //If the FIFO is two from empty, and is reporting empty + else if (tmp_rd_listsize/C_DEPTH_RATIO_WR == 2) + begin + //Do not change the contents of the FIFO + + //Do not acknowledge the read from empty FIFO + ideal_valid <= #`TCQ 1'b0; + //Fifo has two words, so is neither empty or almost empty + + ideal_rd_count <= #`TCQ num_read_words_sized_i; + + end // if (tmp_rd_listsize == 2) + + //If the FIFO is not close to empty, but is reporting that it is + // Treat the FIFO as empty this time, but unset EMPTY flags. + if ((tmp_rd_listsize/C_DEPTH_RATIO_WR > 2) && (tmp_rd_listsize/C_DEPTH_RATIO_WR 2) && (tmp_rd_listsize<=C_FIFO_RD_DEPTH-1)) + end // else: if(ideal_empty == 1'b1) + + else //if (ideal_empty == 1'b0) + begin + + //If the FIFO is completely full, and we are successfully reading from it + if (tmp_rd_listsize/C_DEPTH_RATIO_WR >= C_FIFO_RD_DEPTH) + begin + //Read the value from the FIFO + read_fifo; + next_num_rd_bits = next_num_rd_bits - C_DOUT_WIDTH; + + //Acknowledge the read from the FIFO, no error + ideal_valid <= #`TCQ 1'b1; + //Not close to empty + + ideal_rd_count <= #`TCQ num_read_words_sized_i; + + end // if (tmp_rd_listsize == C_FIFO_RD_DEPTH) + + //If the FIFO is not close to being empty + else if ((tmp_rd_listsize/C_DEPTH_RATIO_WR > 2) && (tmp_rd_listsize/C_DEPTH_RATIO_WR<=C_FIFO_RD_DEPTH)) + begin + //Read the value from the FIFO + read_fifo; + next_num_rd_bits = next_num_rd_bits - C_DOUT_WIDTH; + + //Acknowledge the read from the FIFO, no error + ideal_valid <= #`TCQ 1'b1; + //Not close to empty + + ideal_rd_count <= #`TCQ num_read_words_sized_i; + + end // if ((tmp_rd_listsize > 2) && (tmp_rd_listsize<=C_FIFO_RD_DEPTH-1)) + + //If the FIFO is two from empty + else if (tmp_rd_listsize/C_DEPTH_RATIO_WR == 2) + begin + //Read the value from the FIFO + read_fifo; + next_num_rd_bits = next_num_rd_bits - C_DOUT_WIDTH; + + //Acknowledge the read from the FIFO, no error + ideal_valid <= #`TCQ 1'b1; + //Fifo is not yet empty. It is going almost_empty + + ideal_rd_count <= #`TCQ num_read_words_sized_i; + + end // if (tmp_rd_listsize == 2) + + //If the FIFO is one from empty + else if ((tmp_rd_listsize/C_DEPTH_RATIO_WR == 1)) + begin + //Read the value from the FIFO + read_fifo; + next_num_rd_bits = next_num_rd_bits - C_DOUT_WIDTH; + + //Acknowledge the read from the FIFO, no error + ideal_valid <= #`TCQ 1'b1; + //Note that FIFO is GOING empty + + ideal_rd_count <= #`TCQ num_read_words_sized_i; + + end // if (tmp_rd_listsize == 1) + + + //If the FIFO is completely empty + else if (tmp_rd_listsize/C_DEPTH_RATIO_WR <= 0) + begin + //Do not change the contents of the FIFO + + //Do not acknowledge the read from empty FIFO + ideal_valid <= #`TCQ 1'b0; + + ideal_rd_count <= #`TCQ num_read_words_sized_i; + + end // if (tmp_rd_listsize <= 0) + + end // if (ideal_empty == 1'b0) + + end //(RD_EN == 1'b1) + + else //if (RD_EN == 1'b0) + begin + //If user did not attempt a read, do not give an ack or err + ideal_valid <= #`TCQ 1'b0; + + ideal_rd_count <= #`TCQ num_read_words_sized_i; + + end // else: !if(RD_EN == 1'b1) + + /*****************************************************************/ + // Read Operation - Read Latency 0 + /*****************************************************************/ + end else if (C_PRELOAD_REGS==1 && C_PRELOAD_LATENCY==0) begin + ideal_valid <= #`TCQ 1'b0; + if (ram_rd_en == 1'b1) begin + + if (EMPTY == 1'b1) begin + + //If the FIFO is completely empty, and is reporting empty + if (tmp_rd_listsize/C_DEPTH_RATIO_WR <= 0) begin + //Do not change the contents of the FIFO + + //Do not acknowledge the read from empty FIFO + ideal_valid <= #`TCQ 1'b0; + //Reminder that FIFO is still empty + + ideal_rd_count <= #`TCQ num_read_words_sized_i; + + //If the FIFO is one from empty, but it is reporting empty + end else if (tmp_rd_listsize/C_DEPTH_RATIO_WR == 1) begin + //Do not change the contents of the FIFO + + //Do not acknowledge the read from empty FIFO + ideal_valid <= #`TCQ 1'b0; + //Note that FIFO is no longer empty, but is almost empty (has one word left) + + ideal_rd_count <= #`TCQ num_read_words_sized_i; + + //If the FIFO is two from empty, and is reporting empty + end else if (tmp_rd_listsize/C_DEPTH_RATIO_WR == 2) begin + //Do not change the contents of the FIFO + + //Do not acknowledge the read from empty FIFO + ideal_valid <= #`TCQ 1'b0; + //Fifo has two words, so is neither empty or almost empty + + ideal_rd_count <= #`TCQ num_read_words_sized_i; + + //If the FIFO is not close to empty, but is reporting that it is + // Treat the FIFO as empty this time, but unset EMPTY flags. + end else if ((tmp_rd_listsize/C_DEPTH_RATIO_WR > 2) && + (tmp_rd_listsize/C_DEPTH_RATIO_WR 2) && (tmp_rd_listsize<=C_FIFO_RD_DEPTH-1)) + + end else begin + + //If the FIFO is completely full, and we are successfully reading from it + if (tmp_rd_listsize/C_DEPTH_RATIO_WR >= C_FIFO_RD_DEPTH) begin + //Read the value from the FIFO + read_fifo; + next_num_rd_bits = next_num_rd_bits - C_DOUT_WIDTH; + + //Acknowledge the read from the FIFO, no error + ideal_valid <= #`TCQ 1'b1; + //Not close to empty + + ideal_rd_count <= #`TCQ num_read_words_sized_i; + + //If the FIFO is not close to being empty + end else if ((tmp_rd_listsize/C_DEPTH_RATIO_WR > 2) && + (tmp_rd_listsize/C_DEPTH_RATIO_WR<=C_FIFO_RD_DEPTH)) begin + //Read the value from the FIFO + read_fifo; + next_num_rd_bits = next_num_rd_bits - C_DOUT_WIDTH; + + //Acknowledge the read from the FIFO, no error + ideal_valid <= #`TCQ 1'b1; + //Not close to empty + + ideal_rd_count <= #`TCQ num_read_words_sized_i; + + //If the FIFO is two from empty + end else if (tmp_rd_listsize/C_DEPTH_RATIO_WR == 2) begin + //Read the value from the FIFO + read_fifo; + next_num_rd_bits = next_num_rd_bits - C_DOUT_WIDTH; + + //Acknowledge the read from the FIFO, no error + ideal_valid <= #`TCQ 1'b1; + //Fifo is not yet empty. It is going almost_empty + + ideal_rd_count <= #`TCQ num_read_words_sized_i; + + //If the FIFO is one from empty + end else if (tmp_rd_listsize/C_DEPTH_RATIO_WR == 1) begin + //Read the value from the FIFO + read_fifo; + next_num_rd_bits = next_num_rd_bits - C_DOUT_WIDTH; + + //Acknowledge the read from the FIFO, no error + ideal_valid <= #`TCQ 1'b1; + //Note that FIFO is GOING empty + + ideal_rd_count <= #`TCQ num_read_words_sized_i; + + //If the FIFO is completely empty + end else if (tmp_rd_listsize/C_DEPTH_RATIO_WR <= 0) begin + //Do not change the contents of the FIFO + + //Do not acknowledge the read from empty FIFO + ideal_valid <= #`TCQ 1'b0; + //Reminder that FIFO is still empty + + ideal_rd_count <= #`TCQ num_read_words_sized_i; + + end // if (tmp_rd_listsize <= 0) + + end // if (ideal_empty == 1'b0) + + end else begin//(RD_EN == 1'b0) + + + //If user did not attempt a read, do not give an ack or err + ideal_valid <= #`TCQ 1'b0; + ideal_rd_count <= #`TCQ num_read_words_sized_i; + + end // else: !if(RD_EN == 1'b1) + end //if (C_PRELOAD_REGS==1 && C_PRELOAD_LATENCY==0) + + num_rd_bits <= #`TCQ next_num_rd_bits; + wr_ptr_rdclk <= #`TCQ wr_ptr; + end //rd_rst_i==0 + end //always + +endmodule // fifo_generator_v6_2_bhv_ver_as + + +/******************************************************************************* + * Declaration of top-level module + ******************************************************************************/ +module fifo_generator_v6_2_bhv_ver_ss + + /************************************************************************** + * Declare user parameters and their defaults + *************************************************************************/ + #( + parameter C_DATA_COUNT_WIDTH = 2, + parameter C_DIN_WIDTH = 8, + parameter C_DOUT_RST_VAL = "", + parameter C_DOUT_WIDTH = 8, + parameter C_FULL_FLAGS_RST_VAL = 1, + parameter C_HAS_ALMOST_EMPTY = 0, + parameter C_HAS_ALMOST_FULL = 0, + parameter C_HAS_DATA_COUNT = 0, + parameter C_HAS_OVERFLOW = 0, + parameter C_HAS_RD_DATA_COUNT = 0, + parameter C_HAS_RST = 0, + parameter C_HAS_SRST = 0, + parameter C_HAS_UNDERFLOW = 0, + parameter C_HAS_VALID = 0, + parameter C_HAS_WR_ACK = 0, + parameter C_HAS_WR_DATA_COUNT = 0, + parameter C_IMPLEMENTATION_TYPE = 0, + parameter C_MEMORY_TYPE = 1, + parameter C_OVERFLOW_LOW = 0, + parameter C_PRELOAD_LATENCY = 1, + parameter C_PRELOAD_REGS = 0, + parameter C_PROG_EMPTY_THRESH_ASSERT_VAL = 0, + parameter C_PROG_EMPTY_THRESH_NEGATE_VAL = 0, + parameter C_PROG_EMPTY_TYPE = 0, + parameter C_PROG_FULL_THRESH_ASSERT_VAL = 0, + parameter C_PROG_FULL_THRESH_NEGATE_VAL = 0, + parameter C_PROG_FULL_TYPE = 0, + parameter C_RD_DATA_COUNT_WIDTH = 2, + parameter C_RD_DEPTH = 256, + parameter C_RD_PNTR_WIDTH = 8, + parameter C_UNDERFLOW_LOW = 0, + parameter C_USE_DOUT_RST = 0, + parameter C_USE_EMBEDDED_REG = 0, + parameter C_USE_FWFT_DATA_COUNT = 0, + parameter C_VALID_LOW = 0, + parameter C_WR_ACK_LOW = 0, + parameter C_WR_DATA_COUNT_WIDTH = 2, + parameter C_WR_DEPTH = 256, + parameter C_WR_PNTR_WIDTH = 8, + parameter C_USE_ECC = 0, + parameter C_ENABLE_RST_SYNC = 1, + parameter C_ERROR_INJECTION_TYPE = 0 + ) + + /************************************************************************** + * Declare Input and Output Ports + *************************************************************************/ + ( + //Inputs + input CLK, + input [C_DIN_WIDTH-1:0] DIN, + input [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH, + input [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_ASSERT, + input [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_NEGATE, + input [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH, + input [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_ASSERT, + input [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_NEGATE, + input RD_EN, + input RST, + input RST_FULL_GEN, + input RST_FULL_FF, + input SRST, + input WR_EN, + input INJECTDBITERR, + input INJECTSBITERR, + + //Outputs + output ALMOST_EMPTY, + output ALMOST_FULL, + output reg [C_DATA_COUNT_WIDTH-1:0] DATA_COUNT, + output [C_DOUT_WIDTH-1:0] DOUT, + output EMPTY, + output FULL, + output OVERFLOW, + output PROG_EMPTY, + output PROG_FULL, + output VALID, + output UNDERFLOW, + output WR_ACK, + output SBITERR, + output DBITERR + ); + + + /*************************************************************************** + * Parameters used as constants + **************************************************************************/ + //When RST is present, set FULL reset value to '1'. + //If core has no RST, make sure FULL powers-on as '0'. + //The reset value assignments for FULL, ALMOST_FULL, and PROG_FULL are not + //changed for v3.2(IP2_Im). When the core has Sync Reset, C_HAS_SRST=1 and C_HAS_RST=0. + // Therefore, during SRST, all the FULL flags reset to 0. + parameter C_HAS_FAST_FIFO = 0; + parameter C_FIFO_WR_DEPTH = C_WR_DEPTH; + parameter C_FIFO_RD_DEPTH = C_RD_DEPTH; + + /************************************************************************** + * FIFO Contents Tracking and Data Count Calculations + *************************************************************************/ + // Memory which will be used to simulate a FIFO + reg [C_DIN_WIDTH-1:0] memory[C_WR_DEPTH-1:0]; + // Local parameters used to determine whether to inject ECC error or not + localparam SYMMETRIC_PORT = (C_DIN_WIDTH == C_DOUT_WIDTH) ? 1 : 0; + localparam ERR_INJECTION = (C_ERROR_INJECTION_TYPE != 0) ? 1 : 0; + localparam ENABLE_ERR_INJECTION = C_USE_ECC && SYMMETRIC_PORT && ERR_INJECTION; + // Array that holds the error injection type (single/double bit error) on + // a specific write operation, which is returned on read to corrupt the + // output data. + reg [1:0] ecc_err[C_WR_DEPTH-1:0]; + + //The amount of data stored in the FIFO at any time is given + // by num_bits. + //num_bits is calculated by from the total words in the FIFO. + reg [31:0] num_bits; + + //The write pointer - tracks write operations + // (Works opposite to core: wr_ptr is a DOWN counter) + reg [31:0] wr_ptr; + + //The write pointer - tracks read operations + // (Works opposite to core: rd_ptr is a DOWN counter) + reg [31:0] rd_ptr; + + /************************** + * Data Count + *************************/ + //Amount of data stored in the FIFO scaled to read words + wire [31:0] num_read_words = num_bits/C_DOUT_WIDTH; + //num_read_words delayed 1 clock cycle + reg [31:0] num_read_words_q; + + //Amount of data stored in the FIFO scaled to write words + wire [31:0] num_write_words = num_bits/C_DIN_WIDTH; + //num_write_words delayed 1 clock cycle + reg [31:0] num_write_words_q; + + + /************************************************************************** + * Internal Registers and wires + *************************************************************************/ + + //Temporary signals used for calculating the model's outputs. These + //are only used in the assign statements immediately following wire, + //parameter, and function declarations. + wire underflow_i; + wire valid_i; + wire valid_out; + + //Ideal FIFO signals. These are the raw output of the behavioral model, + //which behaves like an ideal FIFO. + reg [1:0] err_type = 0; + reg [1:0] err_type_d1 = 0; + reg [C_DOUT_WIDTH-1:0] ideal_dout = 0; + reg [C_DOUT_WIDTH-1:0] ideal_dout_d1 = 0; + wire [C_DOUT_WIDTH-1:0] ideal_dout_out; + wire fwft_enabled; + reg ideal_wr_ack = 0; + reg ideal_valid = 0; + reg ideal_overflow = 0; + reg ideal_underflow = 0; + reg ideal_full = 0; + reg ideal_empty = 1; + reg ideal_almost_full = 0; + reg ideal_almost_empty = 1; + reg ideal_prog_full = 0; + reg ideal_prog_empty = 1; + + //Assorted reg values for delayed versions of signals + reg valid_d1 = 0; + reg prog_full_d = 0; + reg prog_empty_d = 1; + + wire rst_i; + wire srst_i; + + //Delayed version of RST + reg rst_q; + reg rst_qq; + + //user specified value for reseting the size of the fifo + reg [C_DOUT_WIDTH-1:0] dout_reset_val = 0; + + + /**************************************************************************** + * Function Declarations + ***************************************************************************/ + + /************************************************************************** + * write_fifo + * This task writes a word to the FIFO memory and updates the + * write pointer. + * FIFO size is relative to write domain. + ***************************************************************************/ + task write_fifo; + reg [1:0] corrupted_data; + begin + memory[wr_ptr] <= DIN; + // Store the type of error injection (double/single) on write + case (C_ERROR_INJECTION_TYPE) + 3: ecc_err[wr_ptr] <= {INJECTDBITERR,INJECTSBITERR}; + 2: ecc_err[wr_ptr] <= {INJECTDBITERR,1'b0}; + 1: ecc_err[wr_ptr] <= {1'b0,INJECTSBITERR}; + default: ecc_err[wr_ptr] <= 0; + endcase + if (wr_ptr == 0) begin + wr_ptr <= C_WR_DEPTH - 1; + end else begin + wr_ptr <= wr_ptr - 1; + end + end + endtask // write_fifo + + /************************************************************************** + * read_fifo + * This task reads a word from the FIFO memory and updates the read + * pointer. It's output is the ideal_dout bus. + * FIFO size is relative to write domain. + ***************************************************************************/ + task read_fifo; + reg [C_DOUT_WIDTH-1:0] tmp_dout; + reg [1:0] tmp_ecc_err; + begin + tmp_dout = memory[rd_ptr][C_DOUT_WIDTH-1:0]; + // Retreive the error injection type. Based on the error injection type + // corrupt the output data. + tmp_ecc_err = ecc_err[rd_ptr]; + if (ENABLE_ERR_INJECTION) begin + if (tmp_ecc_err[1]) begin // Corrupt the output data only for double bit error + if (C_DOUT_WIDTH == 1) + tmp_dout = tmp_dout[C_DOUT_WIDTH-1:0]; + else if (C_DOUT_WIDTH == 2) + tmp_dout = {~tmp_dout[C_DOUT_WIDTH-1],~tmp_dout[C_DOUT_WIDTH-2]}; + else + tmp_dout = {~tmp_dout[C_DOUT_WIDTH-1],~tmp_dout[C_DOUT_WIDTH-2],(tmp_dout << 2)}; + end else begin + tmp_dout = tmp_dout[C_DOUT_WIDTH-1:0]; + end + err_type <= {tmp_ecc_err[1], tmp_ecc_err[0] & !tmp_ecc_err[1]}; + end else begin + err_type <= 0; + end + ideal_dout <= tmp_dout; + + if (rd_ptr == 0) begin + rd_ptr <= C_RD_DEPTH - 1; + end else begin + rd_ptr <= rd_ptr - 1; + end + end + endtask + + /**************************************************************************** + * log2_val + * Returns the 'log2' value for the input value for the supported ratios + ***************************************************************************/ + function [31:0] log2_val; + input [31:0] binary_val; + + begin + if (binary_val == 8) begin + log2_val = 3; + end else if (binary_val == 4) begin + log2_val = 2; + end else begin + log2_val = 1; + end + end + endfunction + + /**************************************************************************** + * hexstr_conv + * Converts a string of type hex to a binary value (for C_DOUT_RST_VAL) + ***************************************************************************/ + function [C_DOUT_WIDTH-1:0] hexstr_conv; + input [(C_DOUT_WIDTH*8)-1:0] def_data; + + integer index,i,j; + reg [3:0] bin; + + begin + index = 0; + hexstr_conv = 'b0; + for( i=C_DOUT_WIDTH-1; i>=0; i=i-1 ) + begin + case (def_data[7:0]) + 8'b00000000 : + begin + bin = 4'b0000; + i = -1; + end + 8'b00110000 : bin = 4'b0000; + 8'b00110001 : bin = 4'b0001; + 8'b00110010 : bin = 4'b0010; + 8'b00110011 : bin = 4'b0011; + 8'b00110100 : bin = 4'b0100; + 8'b00110101 : bin = 4'b0101; + 8'b00110110 : bin = 4'b0110; + 8'b00110111 : bin = 4'b0111; + 8'b00111000 : bin = 4'b1000; + 8'b00111001 : bin = 4'b1001; + 8'b01000001 : bin = 4'b1010; + 8'b01000010 : bin = 4'b1011; + 8'b01000011 : bin = 4'b1100; + 8'b01000100 : bin = 4'b1101; + 8'b01000101 : bin = 4'b1110; + 8'b01000110 : bin = 4'b1111; + 8'b01100001 : bin = 4'b1010; + 8'b01100010 : bin = 4'b1011; + 8'b01100011 : bin = 4'b1100; + 8'b01100100 : bin = 4'b1101; + 8'b01100101 : bin = 4'b1110; + 8'b01100110 : bin = 4'b1111; + default : + begin + bin = 4'bx; + end + endcase + for( j=0; j<4; j=j+1) + begin + if ((index*4)+j < C_DOUT_WIDTH) + begin + hexstr_conv[(index*4)+j] = bin[j]; + end + end + index = index + 1; + def_data = def_data >> 8; + end + end + endfunction + + + /************************************************************************* + * Initialize Signals for clean power-on simulation + *************************************************************************/ + initial begin + num_bits = 0; + num_read_words_q = 0; + num_write_words_q = 0; + rd_ptr = C_RD_DEPTH -1; + wr_ptr = C_WR_DEPTH -1; + dout_reset_val = hexstr_conv(C_DOUT_RST_VAL); + ideal_dout = dout_reset_val; + err_type = 0; + ideal_wr_ack = 1'b0; + ideal_valid = 1'b0; + valid_d1 = 1'b0; + ideal_overflow = 1'b0; + ideal_underflow = 1'b0; + ideal_full = 1'b0; + ideal_empty = 1'b1; + ideal_almost_full = 1'b0; + ideal_almost_empty = 1'b1; + ideal_prog_full = 1'b0; + ideal_prog_empty = 1'b1; + prog_full_d = 1'b0; + prog_empty_d = 1'b1; + rst_q = 1'b0; + rst_qq = 1'b0; + end + + + /************************************************************************* + * Connect the module inputs and outputs to the internal signals of the + * behavioral model. + *************************************************************************/ + //Inputs + /* + wire CLK; + wire [C_DIN_WIDTH-1:0] DIN; + wire [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH; + wire [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_ASSERT; + wire [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_NEGATE; + wire [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH; + wire [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_ASSERT; + wire [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_NEGATE; + wire RD_EN; + wire RST; + wire WR_EN; + */ + + //Outputs + generate + if (C_HAS_ALMOST_EMPTY==1) begin : blockAE10 + assign ALMOST_EMPTY = ideal_almost_empty; + end + endgenerate + + generate + if (C_HAS_ALMOST_FULL==1) begin : blockAF10 + assign ALMOST_FULL = ideal_almost_full; + end + endgenerate + + //Dout may change behavior based on latency + assign fwft_enabled = (C_PRELOAD_LATENCY == 0 && C_PRELOAD_REGS == 1)? + 1: 0; + assign ideal_dout_out= ((C_USE_EMBEDDED_REG==1 && (fwft_enabled == 0)) && + (C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1))? + ideal_dout_d1: ideal_dout; + assign DOUT = ideal_dout_out; + + // Assign SBITERR and DBITERR based on latency + assign SBITERR = (C_ERROR_INJECTION_TYPE == 1 || C_ERROR_INJECTION_TYPE == 3) && + ((C_USE_EMBEDDED_REG==1 && (fwft_enabled == 0)) && + (C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1)) ? + err_type_d1[0]: err_type[0]; + assign DBITERR = (C_ERROR_INJECTION_TYPE == 2 || C_ERROR_INJECTION_TYPE == 3) && + ((C_USE_EMBEDDED_REG==1 && (fwft_enabled == 0)) && + (C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1)) ? + err_type_d1[1]: err_type[1]; + + assign EMPTY = ideal_empty; + assign FULL = ideal_full; + + //Overflow may be active-low + generate + if (C_HAS_OVERFLOW==1) begin : blockOF10 + assign OVERFLOW = ideal_overflow ? !C_OVERFLOW_LOW : C_OVERFLOW_LOW; + end + endgenerate + + assign PROG_EMPTY = ideal_prog_empty; + assign PROG_FULL = ideal_prog_full; + + //Valid may change behavior based on latency or active-low + generate + if (C_HAS_VALID==1) begin : blockVL10 + assign valid_i = (C_PRELOAD_LATENCY==0) ? (RD_EN & ~EMPTY) : ideal_valid; + assign valid_out = (C_PRELOAD_LATENCY==2 && + (C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1))? + valid_d1: valid_i; + assign VALID = valid_out ? !C_VALID_LOW : C_VALID_LOW; + end + endgenerate + + //Trim data count differently depending on set widths + generate + if ((C_HAS_DATA_COUNT == 1) && + (C_DATA_COUNT_WIDTH > C_RD_PNTR_WIDTH)) begin : blockDC1 + always @(num_read_words) + DATA_COUNT = num_read_words[C_RD_PNTR_WIDTH:0]; + end else if (C_HAS_DATA_COUNT == 1) begin : blockDC2 + always @(num_read_words) + DATA_COUNT = num_read_words[C_RD_PNTR_WIDTH-1:C_RD_PNTR_WIDTH-C_DATA_COUNT_WIDTH]; + end //if + endgenerate + + //Underflow may change behavior based on latency or active-low + generate + if (C_HAS_UNDERFLOW==1) begin : blockUF10 + assign underflow_i = ideal_underflow; + assign UNDERFLOW = underflow_i ? !C_UNDERFLOW_LOW : C_UNDERFLOW_LOW; + end + endgenerate + + + //Write acknowledge may be active low + generate + if (C_HAS_WR_ACK==1) begin : blockWK10 + assign WR_ACK = ideal_wr_ack ? !C_WR_ACK_LOW : C_WR_ACK_LOW; + end + endgenerate + + + /***************************************************************************** + * Internal reset logic + ****************************************************************************/ + assign srst_i = C_HAS_SRST ? SRST : 0; + assign rst_i = C_HAS_RST ? RST : 0; + + /************************************************************************** + * Assorted registers for delayed versions of signals + **************************************************************************/ + //Capture delayed version of valid + generate + if (C_HAS_VALID==1) begin : blockVL20 + always @(posedge CLK or posedge rst_i) begin + if (rst_i == 1'b1) begin + valid_d1 <= #`TCQ 1'b0; + end else begin + if (srst_i) begin + valid_d1 <= #`TCQ 1'b0; + end else begin + valid_d1 <= #`TCQ valid_i; + end + end + end // always @ (posedge CLK or posedge rst_i) + end + endgenerate + + + // block memory has a synchronous reset + always @(posedge CLK) begin : gen_fifo_blkmemdout_emb + // make it consistent with the core. + if (rst_i || srst_i) begin + // BRAM resets synchronously + if (C_USE_DOUT_RST == 1 && C_MEMORY_TYPE < 2) begin + ideal_dout_d1 <= #`TCQ dout_reset_val; + end + end + end //always + + reg ram_rd_en_d1 = 1'b0; + //Capture delayed version of dout + always @(posedge CLK or posedge rst_i) begin + if (rst_i == 1'b1) begin + // Reset err_type only if ECC is not selected + if (C_USE_ECC == 0) + err_type_d1 <= #`TCQ 0; + + // DRAM and SRAM reset asynchronously + if ((C_MEMORY_TYPE == 2 || C_MEMORY_TYPE == 3) && C_USE_DOUT_RST == 1) + ideal_dout_d1 <= #`TCQ dout_reset_val; + + ram_rd_en_d1 <= #`TCQ 1'b0; + end else begin + ram_rd_en_d1 <= #`TCQ RD_EN & !EMPTY; + if (srst_i) begin + ram_rd_en_d1 <= #`TCQ 1'b0; + // Reset err_type only if ECC is not selected + if (C_USE_ECC == 0) + err_type_d1 <= #`TCQ 0; + // Reset DRAM and SRAM based FIFO, BRAM based FIFO is reset above + if ((C_MEMORY_TYPE == 2 || C_MEMORY_TYPE == 3) && C_USE_DOUT_RST == 1) + ideal_dout_d1 <= #`TCQ dout_reset_val; + end else if (ram_rd_en_d1) begin + ideal_dout_d1 <= #`TCQ ideal_dout; + err_type_d1 <= #`TCQ err_type; + end + end + end + + /************************************************************************** + * Overflow and Underflow Flag calculation + * (handled separately because they don't support rst) + **************************************************************************/ + generate + if (C_HAS_OVERFLOW==1) begin : blockOF20 + always @(posedge CLK) begin + ideal_overflow <= #`TCQ WR_EN & ideal_full; + end + end + endgenerate + + generate + if (C_HAS_UNDERFLOW==1) begin : blockUF20 + always @(posedge CLK) begin + ideal_underflow <= #`TCQ ideal_empty & RD_EN; + end + end + endgenerate + + /************************************************************************* + * Write and Read Logic + ************************************************************************/ + always @(posedge CLK or posedge rst_i) + begin : gen_wr_ack_resp + + //Register reset + rst_q <= #`TCQ rst_i; + rst_qq <= #`TCQ rst_q; + + end // block: gen_wr_ack_resp + + // block memory has a synchronous reset + always @(posedge CLK) begin : gen_fifo_blkmemdout + //Changed the latency of during async reset to '1' instead of '2' to + // make it consistent with the core. + if (rst_i || rst_q || srst_i) begin + // Reset err_type only if ECC is not selected + if (C_USE_ECC == 0 && C_MEMORY_TYPE == 1) + err_type <= #`TCQ 0; + /******Initialize Read Domain Signals*********************************/ + if (C_USE_DOUT_RST == 1 && C_MEMORY_TYPE < 2) begin + ideal_dout <= #`TCQ dout_reset_val; + end + end + end //always + + // FULL_FLAG_RESET value given for SRST as well. + reg srst_i_d1 = 0; + reg srst_i_d2 = 0; + always @(posedge CLK or posedge RST_FULL_FF) begin : gen_fifo + + /****** Reset fifo - Asynchronous Reset**********************************/ + //Changed the latency of during async reset to '1' instead of '2' to + // make it consistent with the core. + if (RST_FULL_FF) begin //v3.2 + /******Initialize Generic FIFO constructs*****************************/ + num_bits <= #`TCQ 0; + wr_ptr <= #`TCQ C_WR_DEPTH - 1; + rd_ptr <= #`TCQ C_RD_DEPTH - 1; + num_read_words_q <= #`TCQ 0; + num_write_words_q <= #`TCQ 0; + // Reset err_type only if ECC is not selected + if (C_USE_ECC == 0 && C_MEMORY_TYPE != 1) + err_type <= #`TCQ 0; + + + /******Initialize Write Domain Signals********************************/ + ideal_wr_ack <= #`TCQ 0; + ideal_full <= #`TCQ C_FULL_FLAGS_RST_VAL; + ideal_almost_full <= #`TCQ C_FULL_FLAGS_RST_VAL; + + /******Initialize Read Domain Signals*********************************/ + // DRAM and SRAM reset asynchronously + if (C_USE_DOUT_RST == 1 && (C_MEMORY_TYPE == 2 || C_MEMORY_TYPE == 3)) begin + ideal_dout <= #`TCQ dout_reset_val; + end + ideal_valid <= #`TCQ 1'b0; + ideal_empty <= #`TCQ 1'b1; + ideal_almost_empty <= #`TCQ 1'b1; + + end else begin + // Register SRST twice to be consistant with RST behavior + srst_i_d1 <= #`TCQ srst_i; + srst_i_d2 <= #`TCQ srst_i_d1; + if (srst_i) begin + // SRST is available only for Sync BRAM, DRAM and SRAM. + if (C_MEMORY_TYPE == 1 || C_MEMORY_TYPE == 2 || C_MEMORY_TYPE == 3) begin + /******Initialize Generic FIFO constructs***********************/ + num_bits <= #`TCQ 0; + wr_ptr <= #`TCQ C_WR_DEPTH - 1; + rd_ptr <= #`TCQ C_RD_DEPTH - 1; + num_read_words_q <= #`TCQ 0; + num_write_words_q <= #`TCQ 0; + // Reset err_type only if ECC is not selected + if (C_USE_ECC == 0) + err_type <= #`TCQ 0; + + /******Initialize Write Domain Signals**************************/ + ideal_wr_ack <= #`TCQ 0; + ideal_full <= #`TCQ C_FULL_FLAGS_RST_VAL; + ideal_almost_full <= #`TCQ C_FULL_FLAGS_RST_VAL; + + /******Initialize Read Domain Signals***************************/ + //Reset DOUT of Sync DRAM/Shift RAM. Sync BRAM DOUT was reset in the + // above always block. + if (C_USE_DOUT_RST == 1 && (C_MEMORY_TYPE == 2 || C_MEMORY_TYPE == 3)) begin + ideal_dout <= #`TCQ dout_reset_val; + end + ideal_valid <= #`TCQ 1'b0; + ideal_empty <= #`TCQ 1'b1; + ideal_almost_empty <= #`TCQ 1'b1; + end + + end else if ((srst_i_d1 || srst_i_d2) && (C_FULL_FLAGS_RST_VAL == 1)) begin //Hold full flag reset value set during RST/SRST + ideal_full <= #`TCQ C_FULL_FLAGS_RST_VAL; + ideal_almost_full <= #`TCQ C_FULL_FLAGS_RST_VAL; + end else begin //normal operating conditions + /********************************************************************/ + // Synchronous FIFO Condition #1 : Writing and not reading + /********************************************************************/ + ideal_valid <= #`TCQ 1'b0; + if (WR_EN & ~RD_EN) begin + + /*********************************/ + //If the FIFO is full, do NOT perform the write, + // update flags accordingly + /*********************************/ + if (num_write_words >= C_FIFO_WR_DEPTH) begin + ideal_wr_ack <= #`TCQ 0; + + //still full + ideal_full <= #`TCQ 1'b1; + ideal_almost_full <= #`TCQ 1'b1; + + //write unsuccessful - do not change contents + + // no read attempted + ideal_valid <= #`TCQ 1'b0; + + //Not near empty + ideal_empty <= #`TCQ 1'b0; + ideal_almost_empty <= #`TCQ 1'b0; + + + /*********************************/ + //If the FIFO is reporting FULL + // (Startup condition) + /*********************************/ + end else if ((num_write_words < C_FIFO_WR_DEPTH) && (ideal_full == 1'b1)) begin + ideal_wr_ack <= #`TCQ 0; + + //still full + ideal_full <= #`TCQ 1'b0; + ideal_almost_full <= #`TCQ 1'b0; + + //write unsuccessful - do not change contents + + // no read attempted + ideal_valid <= #`TCQ 1'b0; + + //FIFO EMPTY in this state can not be determined + //ideal_empty <= 1'b0; + //ideal_almost_empty <= 1'b0; + + + /*********************************/ + //If the FIFO is one from full + /*********************************/ + end else if (num_write_words == C_FIFO_WR_DEPTH-1) begin + //good write + ideal_wr_ack <= #`TCQ 1; + + //FIFO is one from FULL and going FULL + ideal_full <= #`TCQ 1'b1; + ideal_almost_full <= #`TCQ 1'b1; + + //Add input data + write_fifo; + + // no read attempted + ideal_valid <= #`TCQ 1'b0; + + //Not near empty + ideal_empty <= #`TCQ 1'b0; + ideal_almost_empty <= #`TCQ 1'b0; + + num_bits <= num_bits + C_DIN_WIDTH; + + /*********************************/ + //If the FIFO is 2 from full + /*********************************/ + end else if (num_write_words == C_FIFO_WR_DEPTH-2) begin + //good write + ideal_wr_ack <= #`TCQ 1; + + //2 from full, and writing, so set almost_full + ideal_full <= #`TCQ 1'b0; + ideal_almost_full <= #`TCQ 1'b1; + + //Add input data + write_fifo; + + //no read attempted + ideal_valid <= #`TCQ 1'b0; + + //Not near empty + ideal_empty <= #`TCQ 1'b0; + ideal_almost_empty <= #`TCQ 1'b0; + + num_bits <= #`TCQ num_bits + C_DIN_WIDTH; + + /*********************************/ + //If the FIFO is ALMOST EMPTY + /*********************************/ + end else if (num_read_words == 1) begin + //good write + ideal_wr_ack <= #`TCQ 1; + + //Not near FULL + ideal_full <= #`TCQ 1'b0; + ideal_almost_full <= #`TCQ 1'b0; + + //Add input data + write_fifo; + + // no read attempted + ideal_valid <= #`TCQ 1'b0; + + //Leaving ALMOST_EMPTY + ideal_empty <= #`TCQ 1'b0; + ideal_almost_empty <= #`TCQ 1'b0; + + num_bits <= #`TCQ num_bits + C_DIN_WIDTH; + + /*********************************/ + //If the FIFO is EMPTY + /*********************************/ + end else if (num_read_words == 0) begin + // good write + ideal_wr_ack <= #`TCQ 1; + + //Not near FULL + ideal_full <= #`TCQ 1'b0; + ideal_almost_full <= #`TCQ 1'b0; + + //Add input data + write_fifo; + + // no read attempted + ideal_valid <= #`TCQ 1'b0; + + //Leaving EMPTY (still ALMOST_EMPTY) + ideal_empty <= #`TCQ 1'b0; + ideal_almost_empty <= #`TCQ 1'b1; + + num_bits <= #`TCQ num_bits + C_DIN_WIDTH; + + /*********************************/ + //If the FIFO is not near EMPTY or FULL + /*********************************/ + end else begin + // good write + ideal_wr_ack <= #`TCQ 1; + + //Not near FULL + ideal_full <= #`TCQ 1'b0; + ideal_almost_full <= #`TCQ 1'b0; + + //Add input data + write_fifo; + + // no read attempted + ideal_valid <= #`TCQ 1'b0; + + //Not near EMPTY + ideal_empty <= #`TCQ 1'b0; + ideal_almost_empty <= #`TCQ 1'b0; + + num_bits <= #`TCQ num_bits + C_DIN_WIDTH; + + end // average case + + + /******************************************************************/ + // Synchronous FIFO Condition #2 : Reading and not writing + /******************************************************************/ + end else if (~WR_EN & RD_EN) begin + + /*********************************/ + //If the FIFO is EMPTY + /*********************************/ + if ((num_read_words == 0) || (ideal_empty == 1'b1)) begin + //no write attemped + ideal_wr_ack <= #`TCQ 0; + + //FIFO is not near FULL + ideal_full <= #`TCQ 1'b0; + ideal_almost_full <= #`TCQ 1'b0; + + //Read will fail + ideal_valid <= #`TCQ 1'b0; + + //FIFO is still empty + ideal_empty <= #`TCQ 1'b1; + ideal_almost_empty <= #`TCQ 1'b1; + + //No read + + /*********************************/ + //If the FIFO is ALMOST EMPTY + /*********************************/ + end else if (num_read_words == 1) begin + //no write attempted + ideal_wr_ack <= #`TCQ 0; + + //FIFO is not near FULL + ideal_full <= #`TCQ 1'b0; + ideal_almost_full <= #`TCQ 1'b0; + + //Read successful + ideal_valid <= #`TCQ 1'b1; + + //This read will make FIFO go empty + ideal_empty <= #`TCQ 1'b1; + ideal_almost_empty <= #`TCQ 1'b1; + + //Get the data from the FIFO + read_fifo; + num_bits <= #`TCQ num_bits - C_DIN_WIDTH; + + + /*********************************/ + //If the FIFO is 2 from EMPTY + /*********************************/ + end else if (num_read_words == 2) begin + + //no write attempted + ideal_wr_ack <= #`TCQ 0; + + //FIFO is not near FULL + ideal_full <= #`TCQ 1'b0; + ideal_almost_full <= #`TCQ 1'b0; + + //Read successful + ideal_valid <= #`TCQ 1'b1; + + //FIFO is going ALMOST_EMPTY + ideal_empty <= #`TCQ 1'b0; + ideal_almost_empty <= #`TCQ 1'b1; + + //Get the data from the FIFO + read_fifo; + num_bits <= #`TCQ num_bits - C_DOUT_WIDTH; + + + + /*********************************/ + //If the FIFO is one from full + /*********************************/ + end else if (num_write_words == C_FIFO_WR_DEPTH-1) begin + + //no write attempted + ideal_wr_ack <= #`TCQ 0; + + //FIFO is leaving ALMOST FULL + ideal_full <= #`TCQ 1'b0; + ideal_almost_full <= #`TCQ 1'b0; + + //Read successful + ideal_valid <= #`TCQ 1'b1; + + //Not near empty + ideal_empty <= #`TCQ 1'b0; + ideal_almost_empty <= #`TCQ 1'b0; + + //Read from the FIFO + read_fifo; + num_bits <= #`TCQ num_bits - C_DOUT_WIDTH; + + + /*********************************/ + // FIFO is FULL + /*********************************/ + end else if (num_write_words >= C_FIFO_WR_DEPTH) + begin + //no write attempted + ideal_wr_ack <= #`TCQ 0; + + //FIFO is leaving FULL, but is still ALMOST_FULL + ideal_full <= #`TCQ 1'b0; + ideal_almost_full <= #`TCQ 1'b1; + + //Read successful + ideal_valid <= #`TCQ 1'b1; + + //Not near empty + ideal_empty <= #`TCQ 1'b0; + ideal_almost_empty <= #`TCQ 1'b0; + + //Read from the FIFO + read_fifo; + num_bits <= #`TCQ num_bits - C_DOUT_WIDTH; + + /*********************************/ + //If the FIFO is not near EMPTY or FULL + /*********************************/ + end else begin + //no write attemped + ideal_wr_ack <= #`TCQ 0; + + //Not near empty + ideal_full <= #`TCQ 1'b0; + ideal_almost_full <= #`TCQ 1'b0; + + //Read successful + ideal_valid <= #`TCQ 1'b1; + + //Not near empty + ideal_empty <= #`TCQ 1'b0; + ideal_almost_empty <= #`TCQ 1'b0; + + //Read from the FIFO + read_fifo; + num_bits <= #`TCQ num_bits - C_DOUT_WIDTH; + + + end // average read + + + /******************************************************************/ + // Synchronous FIFO Condition #3 : Reading and writing + /******************************************************************/ + end else if (WR_EN & RD_EN) begin + + /*********************************/ + // FIFO is FULL + /*********************************/ + if (num_write_words >= C_FIFO_WR_DEPTH) begin + + ideal_wr_ack <= #`TCQ 0; + + //Read will be successful, so FIFO will leave FULL + ideal_full <= #`TCQ 1'b0; + ideal_almost_full <= #`TCQ 1'b1; + + //Read successful + ideal_valid <= #`TCQ 1'b1; + + //Not near empty + ideal_empty <= #`TCQ 1'b0; + ideal_almost_empty <= #`TCQ 1'b0; + + //Read from the FIFO + read_fifo; + num_bits <= #`TCQ num_bits - C_DOUT_WIDTH; + + + /*********************************/ + // FIFO is reporting FULL, but it is empty + // (This is a special case, when coming out of RST + /*********************************/ + end else if ((num_write_words == 0) && (ideal_full == 1'b1)) begin + + ideal_wr_ack <= #`TCQ 0; + + //Read will be successful, so FIFO will leave FULL + ideal_full <= #`TCQ 1'b0; + ideal_almost_full <= #`TCQ 1'b0; + + //Read unsuccessful + ideal_valid <= #`TCQ 1'b0; + + //Report empty condition + ideal_empty <= #`TCQ 1'b1; + ideal_almost_empty <= #`TCQ 1'b1; + + //Do not read from empty FIFO + // Read from the FIFO + + + /*********************************/ + //If the FIFO is one from full + /*********************************/ + end else if (num_write_words == C_FIFO_WR_DEPTH-1) begin + + //Write successful + ideal_wr_ack <= #`TCQ 1; + + //FIFO will remain ALMOST_FULL + ideal_full <= #`TCQ 1'b0; + ideal_almost_full <= #`TCQ 1'b1; + + // put the data into the FIFO + write_fifo; + + //Read successful + ideal_valid <= #`TCQ 1'b1; + + //Not near empty + ideal_empty <= #`TCQ 1'b0; + ideal_almost_empty <= #`TCQ 1'b0; + + //Read from the FIFO + read_fifo; + num_bits <= #`TCQ num_bits + C_DIN_WIDTH - C_DOUT_WIDTH; + + /*********************************/ + //If the FIFO is ALMOST EMPTY + /*********************************/ + end else if (num_read_words == 1) begin + + //Write successful + ideal_wr_ack <= #`TCQ 1; + + // Not near FULL + ideal_full <= #`TCQ 1'b0; + ideal_almost_full <= #`TCQ 1'b0; + + // put the data into the FIFO + write_fifo; + + //Read successful + ideal_valid <= #`TCQ 1'b1; + + //FIFO will stay ALMOST_EMPTY + ideal_empty <= #`TCQ 1'b0; + ideal_almost_empty <= #`TCQ 1'b1; + + //Read from the FIFO + read_fifo; + num_bits <= #`TCQ num_bits + C_DIN_WIDTH - C_DOUT_WIDTH; + + + /*********************************/ + //If the FIFO is EMPTY + /*********************************/ + end else if (num_read_words == 0) begin + + //Write successful + ideal_wr_ack <= #`TCQ 1; + + // Not near FULL + ideal_full <= #`TCQ 1'b0; + ideal_almost_full <= #`TCQ 1'b0; + + // put the data into the FIFO + write_fifo; + + //Read will fail + ideal_valid <= #`TCQ 1'b0; + + //FIFO will leave EMPTY + ideal_empty <= #`TCQ 1'b0; + ideal_almost_empty <= #`TCQ 1'b1; + + // No read + num_bits <= #`TCQ num_bits + C_DIN_WIDTH; + + + /*********************************/ + //If the FIFO is not near EMPTY or FULL + /*********************************/ + end else begin + + //Write successful + ideal_wr_ack <= #`TCQ 1; + + // Not near FULL + ideal_full <= #`TCQ 1'b0; + ideal_almost_full <= #`TCQ 1'b0; + + // put the data into the FIFO + write_fifo; + + //Read successful + ideal_valid <= #`TCQ 1'b1; + + // Not near EMPTY + ideal_empty <= #`TCQ 1'b0; + ideal_almost_empty <= #`TCQ 1'b0; + + //Read from the FIFO + read_fifo; + num_bits <= #`TCQ num_bits + C_DIN_WIDTH - C_DOUT_WIDTH; + + end // average case + + /******************************************************************/ + // Synchronous FIFO Condition #4 : Not reading or writing + /******************************************************************/ + end else begin + + /*********************************/ + // FIFO is FULL + /*********************************/ + if (num_write_words >= C_FIFO_WR_DEPTH) begin + + //No write + ideal_wr_ack <= #`TCQ 0; + ideal_full <= #`TCQ 1'b1; + ideal_almost_full <= #`TCQ 1'b1; + + //No read + ideal_valid <= #`TCQ 1'b0; + ideal_empty <= #`TCQ 1'b0; + ideal_almost_empty <= #`TCQ 1'b0; + + //No change to memory + + /*********************************/ + //If the FIFO is one from full + /*********************************/ + end else if (num_write_words == C_FIFO_WR_DEPTH-1) begin + + //No write + ideal_wr_ack <= #`TCQ 0; + ideal_full <= #`TCQ 1'b0; + ideal_almost_full <= #`TCQ 1'b1; + + //No read + ideal_valid <= #`TCQ 1'b0; + ideal_empty <= #`TCQ 1'b0; + ideal_almost_empty <= #`TCQ 1'b0; + + //No change to memory + + /*********************************/ + //If the FIFO is ALMOST EMPTY + /*********************************/ + end else if (num_read_words == 1) begin + //No write + ideal_wr_ack <= #`TCQ 0; + ideal_full <= #`TCQ 1'b0; + ideal_almost_full <= #`TCQ 1'b0; + + //No read + ideal_valid <= #`TCQ 1'b0; + ideal_empty <= #`TCQ 1'b0; + ideal_almost_empty <= #`TCQ 1'b1; + + //No change to memory + + end // almost empty + + + /*********************************/ + //If the FIFO is EMPTY + /*********************************/ + else if (num_read_words == 0) + begin + //No write + ideal_wr_ack <= #`TCQ 0; + ideal_full <= #`TCQ 1'b0; + ideal_almost_full <= #`TCQ 1'b0; + + //No read + ideal_valid <= #`TCQ 1'b0; + ideal_empty <= #`TCQ 1'b1; + ideal_almost_empty <= #`TCQ 1'b1; + + //No change to memory + + /*********************************/ + //If the FIFO is not near EMPTY or FULL + /*********************************/ + end else begin + + //No write + ideal_wr_ack <= #`TCQ 0; + ideal_full <= #`TCQ 1'b0; + ideal_almost_full <= #`TCQ 1'b0; + + //No read + ideal_valid <= #`TCQ 1'b0; + ideal_empty <= #`TCQ 1'b0; + ideal_almost_empty <= #`TCQ 1'b0; + + //No change to memory + + end // average case + + end // neither reading or writing + + num_read_words_q <= #`TCQ num_read_words; + num_write_words_q <= #`TCQ num_write_words; + + end //normal operating conditions + end + + end // block: gen_fifo + + + always @(posedge CLK or posedge RST_FULL_FF) begin : gen_fifo_p + + /****** Reset fifo - Async Reset****************************************/ + //The latency of de-assertion of the flags is reduced by 1 to be + // consistent with the core. + if (RST_FULL_FF) begin + ideal_prog_full <= #`TCQ C_FULL_FLAGS_RST_VAL; + ideal_prog_empty <= #`TCQ 1'b1; + prog_full_d <= #`TCQ C_FULL_FLAGS_RST_VAL; + prog_empty_d <= #`TCQ 1'b1; + + end else begin + if (srst_i) begin + //SRST is available only for Sync BRAM and Sync DRAM. Not for SSHFT. + if (C_MEMORY_TYPE == 1 || C_MEMORY_TYPE == 2 || C_MEMORY_TYPE == 3) begin + ideal_prog_empty <= #`TCQ 1'b1; + prog_empty_d <= #`TCQ 1'b1; + ideal_prog_full <= #`TCQ C_FULL_FLAGS_RST_VAL; + prog_full_d <= #`TCQ C_FULL_FLAGS_RST_VAL; + end + end else if ((srst_i_d1 || srst_i_d2) && (C_FULL_FLAGS_RST_VAL == 1)) begin + ideal_prog_full <= #`TCQ C_FULL_FLAGS_RST_VAL; + prog_full_d <= #`TCQ C_FULL_FLAGS_RST_VAL; + end else begin + + /*************************************************************** + * Programmable FULL flags + ****************************************************************/ + //calculation for standard fifo and latency =2 + if (! (C_PRELOAD_REGS==1 && C_PRELOAD_LATENCY==0) ) begin + //Single constant threshold + if (C_PROG_FULL_TYPE == 1) begin + if ((num_write_words >= C_PROG_FULL_THRESH_ASSERT_VAL-1) + && WR_EN && !RD_EN) begin + prog_full_d <= #`TCQ 1'b1; + end else if (((num_write_words == C_PROG_FULL_THRESH_ASSERT_VAL) + && RD_EN && !WR_EN) || (RST_FULL_GEN)) begin + prog_full_d <= #`TCQ 1'b0; + end + + //Dual constant thresholds + end else if (C_PROG_FULL_TYPE == 2) begin + if ((num_write_words == C_PROG_FULL_THRESH_ASSERT_VAL-1) + && WR_EN && !RD_EN) begin + prog_full_d <= #`TCQ 1'b1; + end else if ((num_write_words == C_PROG_FULL_THRESH_NEGATE_VAL) + && RD_EN && !WR_EN) begin + prog_full_d <= #`TCQ 1'b0; + end + + //Single input threshold + end else if (C_PROG_FULL_TYPE == 3) begin + if ((num_write_words == PROG_FULL_THRESH-1) + && WR_EN && !RD_EN) begin + prog_full_d <= #`TCQ 1'b1; + end else if ((num_write_words == PROG_FULL_THRESH) + && !WR_EN && RD_EN) begin + prog_full_d <= #`TCQ 1'b0; + end else if (num_write_words >= PROG_FULL_THRESH) begin + prog_full_d <= #`TCQ 1'b1; + end else if (num_write_words < PROG_FULL_THRESH) begin + prog_full_d <= #`TCQ 1'b0; + end + + //Dual input thresholds + end else begin + if ((num_write_words == PROG_FULL_THRESH_ASSERT-1) + && WR_EN && !RD_EN) begin + prog_full_d <= #`TCQ 1'b1; + end else if ((num_write_words == PROG_FULL_THRESH_NEGATE) + && !WR_EN && RD_EN)begin + prog_full_d <= #`TCQ 1'b0; + end else if (num_write_words >= PROG_FULL_THRESH_ASSERT) begin + prog_full_d <= #`TCQ 1'b1; + end else if (num_write_words < PROG_FULL_THRESH_NEGATE) begin + prog_full_d <= #`TCQ 1'b0; + end + end + end // (~ (C_PRELOAD_REGS==1 && C_PRELOAD_LATENCY==0) ) + + + //calculation for FWFT fifo + if (C_PRELOAD_REGS==1 && C_PRELOAD_LATENCY==0) begin + if (C_PROG_FULL_TYPE == 1) begin + if ((num_write_words >= C_PROG_FULL_THRESH_ASSERT_VAL-1 - 2) + && WR_EN && !RD_EN) begin + prog_full_d <= #`TCQ 1'b1; + end else if (((num_write_words == C_PROG_FULL_THRESH_ASSERT_VAL - 2) + && RD_EN && !WR_EN) || (RST_FULL_GEN)) begin + prog_full_d <= #`TCQ 1'b0; + end + + //Dual constant thresholds + end else if (C_PROG_FULL_TYPE == 2) begin + if ((num_write_words == C_PROG_FULL_THRESH_ASSERT_VAL-1 - 2) + && WR_EN && !RD_EN) begin + prog_full_d <= #`TCQ 1'b1; + end else if ((num_write_words == C_PROG_FULL_THRESH_NEGATE_VAL - 2) + && RD_EN && !WR_EN) begin + prog_full_d <= #`TCQ 1'b0; + end + + //Single input threshold + end else if (C_PROG_FULL_TYPE == 3) begin + if ((num_write_words == PROG_FULL_THRESH-1 - 2) + && WR_EN && !RD_EN) begin + prog_full_d <= #`TCQ 1'b1; + end else if ((num_write_words == PROG_FULL_THRESH - 2) + && !WR_EN && RD_EN) begin + prog_full_d <= #`TCQ 1'b0; + end else if (num_write_words >= PROG_FULL_THRESH - 2) begin + prog_full_d <= #`TCQ 1'b1; + end else if (num_write_words < PROG_FULL_THRESH - 2) begin + prog_full_d <= #`TCQ 1'b0; + end + + //Dual input thresholds + end else begin + if ((num_write_words == PROG_FULL_THRESH_ASSERT-1 - 2) + && WR_EN && !RD_EN) begin + prog_full_d <= #`TCQ 1'b1; + end else if ((num_write_words == PROG_FULL_THRESH_NEGATE - 2) + && !WR_EN && RD_EN)begin + prog_full_d <= #`TCQ 1'b0; + end else if (num_write_words >= PROG_FULL_THRESH_ASSERT - 2) begin + prog_full_d <= #`TCQ 1'b1; + end else if (num_write_words < PROG_FULL_THRESH_NEGATE - 2) begin + prog_full_d <= #`TCQ 1'b0; + end + end + end // (C_PRELOAD_REGS==1 && C_PRELOAD_LATENCY==0) + + /***************************************************************** + * Programmable EMPTY flags + ****************************************************************/ + //calculation for standard fifo and latency = 2 + if (! (C_PRELOAD_REGS==1 && C_PRELOAD_LATENCY==0) ) begin + //Single constant threshold + if (C_PROG_EMPTY_TYPE == 1) begin + if ((num_read_words == C_PROG_EMPTY_THRESH_ASSERT_VAL+1) + && RD_EN && !WR_EN) begin + prog_empty_d <= #`TCQ 1'b1; + end else if ((num_read_words == C_PROG_EMPTY_THRESH_ASSERT_VAL) + && WR_EN && !RD_EN) begin + prog_empty_d <= #`TCQ 1'b0; + end + //Dual constant thresholds + end else if (C_PROG_EMPTY_TYPE == 2) begin + if ((num_read_words == C_PROG_EMPTY_THRESH_ASSERT_VAL+1) + && RD_EN && !WR_EN) begin + prog_empty_d <= #`TCQ 1'b1; + end else if ((num_read_words == C_PROG_EMPTY_THRESH_NEGATE_VAL) + && !RD_EN && WR_EN) begin + prog_empty_d <= #`TCQ 1'b0; + end + + //Single input threshold + end else if (C_PROG_EMPTY_TYPE == 3) begin + if ((num_read_words == PROG_EMPTY_THRESH+1) + && RD_EN && !WR_EN) begin + prog_empty_d <= #`TCQ 1'b1; + end else if ((num_read_words == PROG_EMPTY_THRESH) + && !RD_EN && WR_EN) begin + prog_empty_d <= #`TCQ 1'b0; + end else if (num_read_words <= PROG_EMPTY_THRESH) begin + prog_empty_d <= #`TCQ 1'b1; + end else if (num_read_words > PROG_EMPTY_THRESH)begin + prog_empty_d <= #`TCQ 1'b0; + end + + //Dual input thresholds + end else begin + if (num_read_words <= PROG_EMPTY_THRESH_ASSERT) begin + prog_empty_d <= #`TCQ 1'b1; + end else if ((num_read_words == PROG_EMPTY_THRESH_ASSERT+1) + && RD_EN && !WR_EN) begin + prog_empty_d <= #`TCQ 1'b1; + end else if (num_read_words > PROG_EMPTY_THRESH_NEGATE)begin + prog_empty_d <= #`TCQ 1'b0; + end else if ((num_read_words == PROG_EMPTY_THRESH_NEGATE) + && !RD_EN && WR_EN) begin + prog_empty_d <= #`TCQ 1'b0; + end + end + end // (~ (C_PRELOAD_REGS==1 && C_PRELOAD_LATENCY==0) ) + + //calculation for FWFT fifo + if (C_PRELOAD_REGS==1 && C_PRELOAD_LATENCY==0) begin + //Single constant threshold + if (C_PROG_EMPTY_TYPE == 1) begin + if ((num_read_words == C_PROG_EMPTY_THRESH_ASSERT_VAL+1 - 2) + && RD_EN && !WR_EN) begin + prog_empty_d <= #`TCQ 1'b1; + end else if ((num_read_words == C_PROG_EMPTY_THRESH_ASSERT_VAL - 2) + && WR_EN && !RD_EN) begin + prog_empty_d <= #`TCQ 1'b0; + end + //Dual constant thresholds + end else if (C_PROG_EMPTY_TYPE == 2) begin + if ((num_read_words == C_PROG_EMPTY_THRESH_ASSERT_VAL+1 - 2) + && RD_EN && !WR_EN) begin + prog_empty_d <= #`TCQ 1'b1; + end else if ((num_read_words == C_PROG_EMPTY_THRESH_NEGATE_VAL - 2) + && !RD_EN && WR_EN) begin + prog_empty_d <= #`TCQ 1'b0; + end + + //Single input threshold + end else if (C_PROG_EMPTY_TYPE == 3) begin + if ((num_read_words == PROG_EMPTY_THRESH+1 - 2) + && RD_EN && !WR_EN) begin + prog_empty_d <= #`TCQ 1'b1; + end else if ((num_read_words == PROG_EMPTY_THRESH - 2) + && !RD_EN && WR_EN) begin + prog_empty_d <= #`TCQ 1'b0; + end else if (num_read_words <= PROG_EMPTY_THRESH - 2) begin + prog_empty_d <= #`TCQ 1'b1; + end else if (num_read_words > PROG_EMPTY_THRESH - 2)begin + prog_empty_d <= #`TCQ 1'b0; + end + + //Dual input thresholds + end else begin + if (num_read_words <= PROG_EMPTY_THRESH_ASSERT - 2) begin + prog_empty_d <= #`TCQ 1'b1; + end else if ((num_read_words == PROG_EMPTY_THRESH_ASSERT+1 - 2) + && RD_EN && !WR_EN) begin + prog_empty_d <= #`TCQ 1'b1; + end else if (num_read_words > PROG_EMPTY_THRESH_NEGATE - 2)begin + prog_empty_d <= #`TCQ 1'b0; + end else if ((num_read_words == PROG_EMPTY_THRESH_NEGATE - 2) + && !RD_EN && WR_EN) begin + prog_empty_d <= #`TCQ 1'b0; + end + end + end // (~ (C_PRELOAD_REGS==1 && C_PRELOAD_LATENCY==0) ) + + ideal_prog_empty <= prog_empty_d; + if (RST_FULL_GEN) begin + ideal_prog_full <= #`TCQ 1'b0; + prog_full_d <= #`TCQ 1'b0; + end else begin + ideal_prog_full <= #`TCQ prog_full_d; + end + + end //if (srst_i) begin + end //if (rst_i) begin + end //always @(posedge CLK or posedge rst_i) begin : gen_fifo_p +endmodule // fifo_generator_v6_2_bhv_ver_ss + + + +/************************************************************************** + * First-Word Fall-Through module (preload 0) + **************************************************************************/ +module fifo_generator_v6_2_bhv_ver_preload0 + ( + RD_CLK, + RD_RST, + SRST, + RD_EN, + FIFOEMPTY, + FIFODATA, + FIFOSBITERR, + FIFODBITERR, + USERDATA, + USERVALID, + USERUNDERFLOW, + USEREMPTY, + USERALMOSTEMPTY, + RAMVALID, + FIFORDEN, + USERSBITERR, + USERDBITERR + ); + + parameter C_DOUT_RST_VAL = ""; + parameter C_DOUT_WIDTH = 8; + parameter C_HAS_RST = 0; + parameter C_ENABLE_RST_SYNC = 0; + parameter C_HAS_SRST = 0; + parameter C_USE_DOUT_RST = 0; + parameter C_USE_ECC = 0; + parameter C_USERVALID_LOW = 0; + parameter C_USERUNDERFLOW_LOW = 0; + parameter C_MEMORY_TYPE = 0; + + //Inputs + input RD_CLK; + input RD_RST; + input SRST; + input RD_EN; + input FIFOEMPTY; + input [C_DOUT_WIDTH-1:0] FIFODATA; + input FIFOSBITERR; + input FIFODBITERR; + + //Outputs + output [C_DOUT_WIDTH-1:0] USERDATA; + output USERVALID; + output USERUNDERFLOW; + output USEREMPTY; + output USERALMOSTEMPTY; + output RAMVALID; + output FIFORDEN; + output USERSBITERR; + output USERDBITERR; + + //Inputs + wire RD_CLK; + wire RD_RST; + wire RD_EN; + wire FIFOEMPTY; + wire [C_DOUT_WIDTH-1:0] FIFODATA; + wire FIFOSBITERR; + wire FIFODBITERR; + + //Outputs + reg [C_DOUT_WIDTH-1:0] USERDATA; + wire USERVALID; + wire USERUNDERFLOW; + wire USEREMPTY; + wire USERALMOSTEMPTY; + wire RAMVALID; + wire FIFORDEN; + reg USERSBITERR; + reg USERDBITERR; + + //Internal signals + wire preloadstage1; + wire preloadstage2; + reg ram_valid_i; + reg read_data_valid_i; + wire ram_regout_en; + wire ram_rd_en; + reg empty_i = 1'b1; + reg empty_q = 1'b1; + reg rd_en_q = 1'b0; + reg almost_empty_i = 1'b1; + reg almost_empty_q = 1'b1; + wire rd_rst_i; + wire srst_i; + + +/************************************************************************* +* FUNCTIONS +*************************************************************************/ + + /************************************************************************* + * hexstr_conv + * Converts a string of type hex to a binary value (for C_DOUT_RST_VAL) + ***********************************************************************/ + function [C_DOUT_WIDTH-1:0] hexstr_conv; + input [(C_DOUT_WIDTH*8)-1:0] def_data; + + integer index,i,j; + reg [3:0] bin; + + begin + index = 0; + hexstr_conv = 'b0; + for( i=C_DOUT_WIDTH-1; i>=0; i=i-1 ) + begin + case (def_data[7:0]) + 8'b00000000 : + begin + bin = 4'b0000; + i = -1; + end + 8'b00110000 : bin = 4'b0000; + 8'b00110001 : bin = 4'b0001; + 8'b00110010 : bin = 4'b0010; + 8'b00110011 : bin = 4'b0011; + 8'b00110100 : bin = 4'b0100; + 8'b00110101 : bin = 4'b0101; + 8'b00110110 : bin = 4'b0110; + 8'b00110111 : bin = 4'b0111; + 8'b00111000 : bin = 4'b1000; + 8'b00111001 : bin = 4'b1001; + 8'b01000001 : bin = 4'b1010; + 8'b01000010 : bin = 4'b1011; + 8'b01000011 : bin = 4'b1100; + 8'b01000100 : bin = 4'b1101; + 8'b01000101 : bin = 4'b1110; + 8'b01000110 : bin = 4'b1111; + 8'b01100001 : bin = 4'b1010; + 8'b01100010 : bin = 4'b1011; + 8'b01100011 : bin = 4'b1100; + 8'b01100100 : bin = 4'b1101; + 8'b01100101 : bin = 4'b1110; + 8'b01100110 : bin = 4'b1111; + default : + begin + bin = 4'bx; + end + endcase + for( j=0; j<4; j=j+1) + begin + if ((index*4)+j < C_DOUT_WIDTH) + begin + hexstr_conv[(index*4)+j] = bin[j]; + end + end + index = index + 1; + def_data = def_data >> 8; + end + end + endfunction + + + //************************************************************************* + // Set power-on states for regs + //************************************************************************* + initial begin + ram_valid_i = 1'b0; + read_data_valid_i = 1'b0; + USERDATA = hexstr_conv(C_DOUT_RST_VAL); + USERSBITERR = 1'b0; + USERDBITERR = 1'b0; + end //initial + + //*************************************************************************** + // connect up optional reset + //*************************************************************************** + assign rd_rst_i = (C_HAS_RST == 1 || C_ENABLE_RST_SYNC == 0) ? RD_RST : 0; + assign srst_i = C_HAS_SRST ? SRST : 0; + + + //*************************************************************************** + // preloadstage2 indicates that stage2 needs to be updated. This is true + // whenever read_data_valid is false, and RAM_valid is true. + //*************************************************************************** + assign preloadstage2 = ram_valid_i & (~read_data_valid_i | RD_EN); + + //*************************************************************************** + // preloadstage1 indicates that stage1 needs to be updated. This is true + // whenever the RAM has data (RAM_EMPTY is false), and either RAM_Valid is + // false (indicating that Stage1 needs updating), or preloadstage2 is active + // (indicating that Stage2 is going to update, so Stage1, therefore, must + // also be updated to keep it valid. + //*************************************************************************** + assign preloadstage1 = ((~ram_valid_i | preloadstage2) & ~FIFOEMPTY); + + //*************************************************************************** + // Calculate RAM_REGOUT_EN + // The output registers are controlled by the ram_regout_en signal. + // These registers should be updated either when the output in Stage2 is + // invalid (preloadstage2), OR when the user is reading, in which case the + // Stage2 value will go invalid unless it is replenished. + //*************************************************************************** + assign ram_regout_en = preloadstage2; + + //*************************************************************************** + // Calculate RAM_RD_EN + // RAM_RD_EN will be asserted whenever the RAM needs to be read in order to + // update the value in Stage1. + // One case when this happens is when preloadstage1=true, which indicates + // that the data in Stage1 or Stage2 is invalid, and needs to automatically + // be updated. + // The other case is when the user is reading from the FIFO, which + // guarantees that Stage1 or Stage2 will be invalid on the next clock + // cycle, unless it is replinished by data from the memory. So, as long + // as the RAM has data in it, a read of the RAM should occur. + //*************************************************************************** + assign ram_rd_en = (RD_EN & ~FIFOEMPTY) | preloadstage1; + + //*************************************************************************** + // Calculate RAMVALID_P0_OUT + // RAMVALID_P0_OUT indicates that the data in Stage1 is valid. + // + // If the RAM is being read from on this clock cycle (ram_rd_en=1), then + // RAMVALID_P0_OUT is certainly going to be true. + // If the RAM is not being read from, but the output registers are being + // updated to fill Stage2 (ram_regout_en=1), then Stage1 will be emptying, + // therefore causing RAMVALID_P0_OUT to be false. + // Otherwise, RAMVALID_P0_OUT will remain unchanged. + //*************************************************************************** + // PROCESS regout_valid + always @ (posedge RD_CLK or posedge rd_rst_i) begin + if (rd_rst_i) begin + // asynchronous reset (active high) + ram_valid_i <= #`TCQ 1'b0; + end else begin + if (srst_i) begin + // synchronous reset (active high) + ram_valid_i <= #`TCQ 1'b0; + end else begin + if (ram_rd_en == 1'b1) begin + ram_valid_i <= #`TCQ 1'b1; + end else begin + if (ram_regout_en == 1'b1) + ram_valid_i <= #`TCQ 1'b0; + else + ram_valid_i <= #`TCQ ram_valid_i; + end + end //srst_i + end //rd_rst_i + end //always + + //*************************************************************************** + // Calculate READ_DATA_VALID + // READ_DATA_VALID indicates whether the value in Stage2 is valid or not. + // Stage2 has valid data whenever Stage1 had valid data and + // ram_regout_en_i=1, such that the data in Stage1 is propogated + // into Stage2. + //*************************************************************************** + always @ (posedge RD_CLK or posedge rd_rst_i) begin + if (rd_rst_i) + read_data_valid_i <= #`TCQ 1'b0; + else if (srst_i) + read_data_valid_i <= #`TCQ 1'b0; + else + read_data_valid_i <= #`TCQ ram_valid_i | (read_data_valid_i & ~RD_EN); + end //always + + + //************************************************************************** + // Calculate EMPTY + // Defined as the inverse of READ_DATA_VALID + // + // Description: + // + // If read_data_valid_i indicates that the output is not valid, + // and there is no valid data on the output of the ram to preload it + // with, then we will report empty. + // + // If there is no valid data on the output of the ram and we are + // reading, then the FIFO will go empty. + // + //************************************************************************** + always @ (posedge RD_CLK or posedge rd_rst_i) begin + if (rd_rst_i) begin + // asynchronous reset (active high) + empty_i <= #`TCQ 1'b1; + end else begin + if (srst_i) begin + // synchronous reset (active high) + empty_i <= #`TCQ 1'b1; + end else begin + // rising clock edge + empty_i <= #`TCQ (~ram_valid_i & ~read_data_valid_i) | (~ram_valid_i & RD_EN); + end + end + end //always + + // Register RD_EN from user to calculate USERUNDERFLOW. + // Register empty_i to calculate USERUNDERFLOW. + always @ (posedge RD_CLK) begin + rd_en_q <= #`TCQ RD_EN; + empty_q <= #`TCQ empty_i; + end //always + + + //*************************************************************************** + // Calculate user_almost_empty + // user_almost_empty is defined such that, unless more words are written + // to the FIFO, the next read will cause the FIFO to go EMPTY. + // + // In most cases, whenever the output registers are updated (due to a user + // read or a preload condition), then user_almost_empty will update to + // whatever RAM_EMPTY is. + // + // The exception is when the output is valid, the user is not reading, and + // Stage1 is not empty. In this condition, Stage1 will be preloaded from the + // memory, so we need to make sure user_almost_empty deasserts properly under + // this condition. + //*************************************************************************** + always @ (posedge RD_CLK or posedge rd_rst_i) + begin + if (rd_rst_i) begin // asynchronous reset (active high) + almost_empty_i <= #`TCQ 1'b1; + almost_empty_q <= #`TCQ 1'b1; + end else begin // rising clock edge + if (srst_i) begin // synchronous reset (active high) + almost_empty_i <= #`TCQ 1'b1; + almost_empty_q <= #`TCQ 1'b1; + end else begin + if ((ram_regout_en) | (~FIFOEMPTY & read_data_valid_i & ~RD_EN)) begin + almost_empty_i <= #`TCQ FIFOEMPTY; + end + almost_empty_q <= #`TCQ empty_i; + end + end + end //always + + + assign USEREMPTY = empty_i; + assign USERALMOSTEMPTY = almost_empty_i; + assign FIFORDEN = ram_rd_en; + assign RAMVALID = ram_valid_i; + assign USERVALID = C_USERVALID_LOW ? ~read_data_valid_i : read_data_valid_i; + assign USERUNDERFLOW = C_USERUNDERFLOW_LOW ? ~(empty_q & rd_en_q) : empty_q & rd_en_q; + + // BRAM resets synchronously + always @ (posedge RD_CLK) + begin + if (rd_rst_i || srst_i) begin + if (C_USE_DOUT_RST == 1 && C_MEMORY_TYPE < 2) + USERDATA <= #`TCQ hexstr_conv(C_DOUT_RST_VAL); + end + end //always + + + always @ (posedge RD_CLK or posedge rd_rst_i) + begin + if (rd_rst_i) begin //asynchronous reset (active high) + if (C_USE_ECC == 0) begin // Reset S/DBITERR only if ECC is OFF + USERSBITERR <= #`TCQ 0; + USERDBITERR <= #`TCQ 0; + end + // DRAM resets asynchronously + if (C_USE_DOUT_RST == 1 && C_MEMORY_TYPE == 2) //asynchronous reset (active high) + USERDATA <= #`TCQ hexstr_conv(C_DOUT_RST_VAL); + end else begin // rising clock edge + if (srst_i) begin + if (C_USE_ECC == 0) begin // Reset S/DBITERR only if ECC is OFF + USERSBITERR <= #`TCQ 0; + USERDBITERR <= #`TCQ 0; + end + if (C_USE_DOUT_RST == 1 && C_MEMORY_TYPE == 2) + USERDATA <= #`TCQ hexstr_conv(C_DOUT_RST_VAL); + end else begin + if (ram_regout_en) begin + USERDATA <= #`TCQ FIFODATA; + USERSBITERR <= #`TCQ FIFOSBITERR; + USERDBITERR <= #`TCQ FIFODBITERR; + end + end + end + end //always + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/FIFO_GENERATOR_V6_2_XST.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/FIFO_GENERATOR_V6_2_XST.v new file mode 100644 index 0000000..f73be13 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/FIFO_GENERATOR_V6_2_XST.v @@ -0,0 +1,336 @@ +/* + ******************************************************************************* + * + * FIFO Generator - Verilog Behavioral Model + * + ******************************************************************************* + * + * (c) Copyright 1995 - 2009 Xilinx, Inc. All rights reserved. + * + * This file contains confidential and proprietary information + * of Xilinx, Inc. and is protected under U.S. and + * international copyright and other intellectual property + * laws. + * + * DISCLAIMER + * This disclaimer is not a license and does not grant any + * rights to the materials distributed herewith. Except as + * otherwise provided in a valid license issued to you by + * Xilinx, and to the maximum extent permitted by applicable + * law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND + * WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES + * AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING + * BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- + * INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and + * (2) Xilinx shall not be liable (whether in contract or tort, + * including negligence, or under any other theory of + * liability) for any loss or damage of any kind or nature + * related to, arising under or in connection with these + * materials, including for any direct, or any indirect, + * special, incidental, or consequential loss or damage + * (including loss of data, profits, goodwill, or any type of + * loss or damage suffered as a result of any action brought + * by a third party) even if such damage or loss was + * reasonably foreseeable or Xilinx had been advised of the + * possibility of the same. + * + * CRITICAL APPLICATIONS + * Xilinx products are not designed or intended to be fail- + * safe, or for use in any application requiring fail-safe + * performance, such as life-support or safety devices or + * systems, Class III medical devices, nuclear facilities, + * applications related to the deployment of airbags, or any + * other applications that could lead to death, personal + * injury, or severe property or environmental damage + * (individually and collectively, "Critical + * Applications"). Customer assumes the sole risk and + * liability of any use of Xilinx products in Critical + * Applications, subject only to applicable laws and + * regulations governing limitations on product liability. + * + * THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS + * PART OF THIS FILE AT ALL TIMES. + * + ******************************************************************************* + ******************************************************************************* + * + * Filename: fifo_generator_v6_2_bhv.v + * + * Description: + * The verilog behavioral model for the FIFO generator core. + * + ******************************************************************************* + */ + +`timescale 1ps/1ps + +/******************************************************************************* + * Declaration of top-level module + ******************************************************************************/ +module FIFO_GENERATOR_V6_2_XST + ( + BACKUP, + BACKUP_MARKER, + CLK, + RST, + SRST, + WR_CLK, + WR_RST, + RD_CLK, + RD_RST, + DIN, + WR_EN, + RD_EN, + PROG_EMPTY_THRESH, + PROG_EMPTY_THRESH_ASSERT, + PROG_EMPTY_THRESH_NEGATE, + PROG_FULL_THRESH, + PROG_FULL_THRESH_ASSERT, + PROG_FULL_THRESH_NEGATE, + INT_CLK, + INJECTDBITERR, + INJECTSBITERR, + + DOUT, + FULL, + ALMOST_FULL, + WR_ACK, + OVERFLOW, + EMPTY, + ALMOST_EMPTY, + VALID, + UNDERFLOW, + DATA_COUNT, + RD_DATA_COUNT, + WR_DATA_COUNT, + PROG_FULL, + PROG_EMPTY, + SBITERR, + DBITERR + ); + +/****************************************************************************** + * Definition of Ports + * + * + ***************************************************************************** + * Definition of Parameters + * + * + *****************************************************************************/ + +/****************************************************************************** + * Declare user parameters and their defaults + *****************************************************************************/ + parameter C_COMMON_CLOCK = 0; + parameter C_COUNT_TYPE = 0; + parameter C_DATA_COUNT_WIDTH = 2; + parameter C_DEFAULT_VALUE = ""; + parameter C_DIN_WIDTH = 8; + parameter C_DOUT_RST_VAL = ""; + parameter C_DOUT_WIDTH = 8; + parameter C_ENABLE_RLOCS = 0; + parameter C_FAMILY = "virtex2"; //Not allowed in Verilog model + parameter C_FULL_FLAGS_RST_VAL = 1; + parameter C_HAS_ALMOST_EMPTY = 0; + parameter C_HAS_ALMOST_FULL = 0; + parameter C_HAS_BACKUP = 0; + parameter C_HAS_DATA_COUNT = 0; + parameter C_HAS_INT_CLK = 0; + parameter C_HAS_MEMINIT_FILE = 0; + parameter C_HAS_OVERFLOW = 0; + parameter C_HAS_RD_DATA_COUNT = 0; + parameter C_HAS_RD_RST = 0; + parameter C_HAS_RST = 0; + parameter C_HAS_SRST = 0; + parameter C_HAS_UNDERFLOW = 0; + parameter C_HAS_VALID = 0; + parameter C_HAS_WR_ACK = 0; + parameter C_HAS_WR_DATA_COUNT = 0; + parameter C_HAS_WR_RST = 0; + parameter C_IMPLEMENTATION_TYPE = 0; + parameter C_INIT_WR_PNTR_VAL = 0; + parameter C_MEMORY_TYPE = 1; + parameter C_MIF_FILE_NAME = ""; + parameter C_OPTIMIZATION_MODE = 0; + parameter C_OVERFLOW_LOW = 0; + parameter C_PRELOAD_LATENCY = 1; + parameter C_PRELOAD_REGS = 0; + parameter C_PRIM_FIFO_TYPE = ""; + parameter C_PROG_EMPTY_THRESH_ASSERT_VAL = 0; + parameter C_PROG_EMPTY_THRESH_NEGATE_VAL = 0; + parameter C_PROG_EMPTY_TYPE = 0; + parameter C_PROG_FULL_THRESH_ASSERT_VAL = 0; + parameter C_PROG_FULL_THRESH_NEGATE_VAL = 0; + parameter C_PROG_FULL_TYPE = 0; + parameter C_RD_DATA_COUNT_WIDTH = 2; + parameter C_RD_DEPTH = 256; + parameter C_RD_FREQ = 1; + parameter C_RD_PNTR_WIDTH = 8; + parameter C_UNDERFLOW_LOW = 0; + parameter C_USE_DOUT_RST = 0; + parameter C_USE_ECC = 0; + parameter C_USE_EMBEDDED_REG = 0; + parameter C_USE_FIFO16_FLAGS = 0; + parameter C_USE_FWFT_DATA_COUNT = 0; + parameter C_VALID_LOW = 0; + parameter C_WR_ACK_LOW = 0; + parameter C_WR_DATA_COUNT_WIDTH = 2; + parameter C_WR_DEPTH = 256; + parameter C_WR_FREQ = 1; + parameter C_WR_PNTR_WIDTH = 8; + parameter C_WR_RESPONSE_LATENCY = 1; + parameter C_MSGON_VAL = 1; + parameter C_ENABLE_RST_SYNC = 1; + parameter C_ERROR_INJECTION_TYPE = 0; + + + /****************************************************************************** + * Declare Input and Output Ports + *****************************************************************************/ + input CLK; + input BACKUP; + input BACKUP_MARKER; + input [C_DIN_WIDTH-1:0] DIN; + input [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH; + input [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_ASSERT; + input [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_NEGATE; + input [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH; + input [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_ASSERT; + input [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_NEGATE; + input RD_CLK; + input RD_EN; + input RD_RST; + input RST; + input SRST; + input WR_CLK; + input WR_EN; + input WR_RST; + input INT_CLK; + input INJECTDBITERR; + input INJECTSBITERR; + + output ALMOST_EMPTY; + output ALMOST_FULL; + output [C_DATA_COUNT_WIDTH-1:0] DATA_COUNT; + output [C_DOUT_WIDTH-1:0] DOUT; + output EMPTY; + output FULL; + output OVERFLOW; + output PROG_EMPTY; + output PROG_FULL; + output VALID; + output [C_RD_DATA_COUNT_WIDTH-1:0] RD_DATA_COUNT; + output UNDERFLOW; + output WR_ACK; + output [C_WR_DATA_COUNT_WIDTH-1:0] WR_DATA_COUNT; + output SBITERR; + output DBITERR; + + FIFO_GENERATOR_V6_2 + #( + .C_COMMON_CLOCK (C_COMMON_CLOCK), + .C_COUNT_TYPE (C_COUNT_TYPE), + .C_DATA_COUNT_WIDTH (C_DATA_COUNT_WIDTH), + .C_DEFAULT_VALUE (C_DEFAULT_VALUE), + .C_DIN_WIDTH (C_DIN_WIDTH), + .C_DOUT_RST_VAL (C_DOUT_RST_VAL), + .C_DOUT_WIDTH (C_DOUT_WIDTH), + .C_ENABLE_RLOCS (C_ENABLE_RLOCS), + .C_FAMILY (C_FAMILY),//Not allowed in Verilog model + .C_FULL_FLAGS_RST_VAL (C_FULL_FLAGS_RST_VAL), + .C_HAS_ALMOST_EMPTY (C_HAS_ALMOST_EMPTY), + .C_HAS_ALMOST_FULL (C_HAS_ALMOST_FULL), + .C_HAS_BACKUP (C_HAS_BACKUP), + .C_HAS_DATA_COUNT (C_HAS_DATA_COUNT), + .C_HAS_INT_CLK (C_HAS_INT_CLK), + .C_HAS_MEMINIT_FILE (C_HAS_MEMINIT_FILE), + .C_HAS_OVERFLOW (C_HAS_OVERFLOW), + .C_HAS_RD_DATA_COUNT (C_HAS_RD_DATA_COUNT), + .C_HAS_RD_RST (C_HAS_RD_RST), + .C_HAS_RST (C_HAS_RST), + .C_HAS_SRST (C_HAS_SRST), + .C_HAS_UNDERFLOW (C_HAS_UNDERFLOW), + .C_HAS_VALID (C_HAS_VALID), + .C_HAS_WR_ACK (C_HAS_WR_ACK), + .C_HAS_WR_DATA_COUNT (C_HAS_WR_DATA_COUNT), + .C_HAS_WR_RST (C_HAS_WR_RST), + .C_IMPLEMENTATION_TYPE (C_IMPLEMENTATION_TYPE), + .C_INIT_WR_PNTR_VAL (C_INIT_WR_PNTR_VAL), + .C_MEMORY_TYPE (C_MEMORY_TYPE), + .C_MIF_FILE_NAME (C_MIF_FILE_NAME), + .C_OPTIMIZATION_MODE (C_OPTIMIZATION_MODE), + .C_OVERFLOW_LOW (C_OVERFLOW_LOW), + .C_PRELOAD_LATENCY (C_PRELOAD_LATENCY), + .C_PRELOAD_REGS (C_PRELOAD_REGS), + .C_PRIM_FIFO_TYPE (C_PRIM_FIFO_TYPE), + .C_PROG_EMPTY_THRESH_ASSERT_VAL (C_PROG_EMPTY_THRESH_ASSERT_VAL), + .C_PROG_EMPTY_THRESH_NEGATE_VAL (C_PROG_EMPTY_THRESH_NEGATE_VAL), + .C_PROG_EMPTY_TYPE (C_PROG_EMPTY_TYPE), + .C_PROG_FULL_THRESH_ASSERT_VAL (C_PROG_FULL_THRESH_ASSERT_VAL), + .C_PROG_FULL_THRESH_NEGATE_VAL (C_PROG_FULL_THRESH_NEGATE_VAL), + .C_PROG_FULL_TYPE (C_PROG_FULL_TYPE), + .C_RD_DATA_COUNT_WIDTH (C_RD_DATA_COUNT_WIDTH), + .C_RD_DEPTH (C_RD_DEPTH), + .C_RD_FREQ (C_RD_FREQ), + .C_RD_PNTR_WIDTH (C_RD_PNTR_WIDTH), + .C_UNDERFLOW_LOW (C_UNDERFLOW_LOW), + .C_USE_DOUT_RST (C_USE_DOUT_RST), + .C_USE_ECC (C_USE_ECC), + .C_USE_EMBEDDED_REG (C_USE_EMBEDDED_REG), + .C_USE_FIFO16_FLAGS (C_USE_FIFO16_FLAGS), + .C_USE_FWFT_DATA_COUNT (C_USE_FWFT_DATA_COUNT), + .C_VALID_LOW (C_VALID_LOW), + .C_WR_ACK_LOW (C_WR_ACK_LOW), + .C_WR_DATA_COUNT_WIDTH (C_WR_DATA_COUNT_WIDTH), + .C_WR_DEPTH (C_WR_DEPTH), + .C_WR_FREQ (C_WR_FREQ), + .C_WR_PNTR_WIDTH (C_WR_PNTR_WIDTH), + .C_WR_RESPONSE_LATENCY (C_WR_RESPONSE_LATENCY), + .C_MSGON_VAL (C_MSGON_VAL), + .C_ENABLE_RST_SYNC (C_ENABLE_RST_SYNC), + .C_ERROR_INJECTION_TYPE (C_ERROR_INJECTION_TYPE) + ) + fifo_generator_v6_2_dut + ( + .BACKUP (BACKUP), + .BACKUP_MARKER (BACKUP_MARKER), + .CLK (CLK), + .RST (RST), + .SRST (SRST), + .WR_CLK (WR_CLK), + .WR_RST (WR_RST), + .RD_CLK (RD_CLK), + .RD_RST (RD_RST), + .DIN (DIN), + .WR_EN (WR_EN), + .RD_EN (RD_EN), + .PROG_EMPTY_THRESH (PROG_EMPTY_THRESH), + .PROG_EMPTY_THRESH_ASSERT (PROG_EMPTY_THRESH_ASSERT), + .PROG_EMPTY_THRESH_NEGATE (PROG_EMPTY_THRESH_NEGATE), + .PROG_FULL_THRESH (PROG_FULL_THRESH), + .PROG_FULL_THRESH_ASSERT (PROG_FULL_THRESH_ASSERT), + .PROG_FULL_THRESH_NEGATE (PROG_FULL_THRESH_NEGATE), + .INT_CLK (INT_CLK), + .INJECTDBITERR (INJECTDBITERR), + .INJECTSBITERR (INJECTSBITERR), + + .DOUT (DOUT), + .FULL (FULL), + .ALMOST_FULL (ALMOST_FULL), + .WR_ACK (WR_ACK), + .OVERFLOW (OVERFLOW), + .EMPTY (EMPTY), + .ALMOST_EMPTY (ALMOST_EMPTY), + .VALID (VALID), + .UNDERFLOW (UNDERFLOW), + .DATA_COUNT (DATA_COUNT), + .RD_DATA_COUNT (RD_DATA_COUNT), + .WR_DATA_COUNT (WR_DATA_COUNT), + .PROG_FULL (PROG_FULL), + .PROG_EMPTY (PROG_EMPTY), + .SBITERR (SBITERR), + .DBITERR (DBITERR) + ); + +endmodule diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/MULT_GEN_V6_0.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/MULT_GEN_V6_0.v new file mode 100644 index 0000000..3a6183a --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/MULT_GEN_V6_0.v @@ -0,0 +1,166 @@ +// Copyright(C) 2002 by Xilinx, Inc. All rights reserved. +// This text contains proprietary, confidential +// information of Xilinx, Inc., is distributed +// under license from Xilinx, Inc., and may be used, +// copied and/or disclosed only pursuant to the terms +// of a valid license agreement with Xilinx, Inc. This copyright +// notice must be retained as part of this text at all times. + + +/* $Id: MULT_GEN_V6_0.v,v 1.15 2008/09/08 20:09:13 akennedy Exp $ +-- +-- Filename - MULT_GEN_V6_0.v +-- Author - Xilinx +-- Creation - 22 Mar 1999 +-- +-- Description - This file contains the Verilog behavior for the multiplier module +*/ + +`timescale 1ns/10ps +`define c_set 0 +`define c_clear 1 +`define c_override 0 +`define c_no_override 1 +`define c_add 0 +`define c_sub 1 +`define c_add_sub 2 +`define c_signed 0 +`define c_unsigned 1 +`define c_pin 2 +`define c_distributed 0 +`define c_dp_block 2 + +module MULT_GEN_V6_0 (A, B, CLK, A_SIGNED, CE, ACLR, + SCLR, LOADB, LOAD_DONE, SWAPB, RFD, + ND, RDY, O, Q); + + parameter BRAM_ADDR_WIDTH = 8; + parameter C_A_TYPE = `c_signed; + parameter C_A_WIDTH = 16; + parameter C_BAAT = 2; + parameter C_B_CONSTANT = `c_signed; + parameter C_B_TYPE = `c_signed; + parameter C_B_VALUE = "0000000000000001"; + parameter C_B_WIDTH = 16; + parameter C_ENABLE_RLOCS = 1; + parameter C_HAS_ACLR = 0; + parameter C_HAS_A_SIGNED = 0; + parameter C_HAS_B = 1; + parameter C_HAS_CE = 0; + parameter C_HAS_LOADB = 0; + parameter C_HAS_LOAD_DONE = 0; + parameter C_HAS_ND = 0; + parameter C_HAS_O = 0; + parameter C_HAS_Q = 1; + parameter C_HAS_RDY = 0; + parameter C_HAS_RFD = 0; + parameter C_HAS_SCLR = 0; + parameter C_HAS_SWAPB = 0; + parameter C_MEM_INIT_PREFIX = "mem"; + parameter C_MEM_TYPE = 0; + parameter C_MULT_TYPE = 0; + parameter C_OUTPUT_HOLD = 0; + parameter C_OUT_WIDTH = 16; + parameter C_PIPELINE = 0; + parameter C_REG_A_B_INPUTS = 1; + parameter C_SQM_TYPE = 0; + parameter C_STACK_ADDERS = 0; + parameter C_STANDALONE = 0; + parameter C_SYNC_ENABLE = 0; + parameter C_USE_LUTS = 1; + parameter C_V2_SPEED = 1; + + parameter non_seq_cawidth = (C_BAAT == C_A_WIDTH ? (C_BAAT == 1 ? C_A_WIDTH+1 : C_A_WIDTH) : C_A_WIDTH); + parameter non_seq_cbaat = (C_BAAT == C_A_WIDTH ? 1 : C_BAAT); + parameter ser_seq_cawidth = (C_BAAT == C_A_WIDTH ? (C_BAAT == 1 ? C_A_WIDTH+1 : C_A_WIDTH) : (C_SQM_TYPE == 0 ? C_A_WIDTH : 1)); + parameter non_seq_cbwidth = (C_BAAT == C_A_WIDTH ? (C_B_WIDTH == 1 ? 2 : C_B_WIDTH) : C_B_WIDTH); + parameter non_seq_out_width = (C_BAAT == C_A_WIDTH ? 1 : C_OUT_WIDTH); + + parameter INT_C_SYNC_ENABLE = (C_HAS_CE == 1 ? C_SYNC_ENABLE : 0); + + input [(C_A_WIDTH-1-((C_A_WIDTH-1)*C_SQM_TYPE)) : 0] A; + input [C_B_WIDTH-1 : 0] B; + input CLK; + input CE; + input A_SIGNED; + input LOADB; + input SWAPB; + input ND; + input ACLR; + input SCLR; + output RFD; + output RDY; + output LOAD_DONE; + output [C_OUT_WIDTH-1 : 0] O; + output [C_OUT_WIDTH-1 : 0] Q; + + wire RFD_seq; + wire RFD_non_seq; + wire RDY_seq; + wire RDY_non_seq; + wire LOAD_DONE_seq; + wire LOAD_DONE_non_seq; + wire [non_seq_out_width-1 : 0] O_seq; + wire [C_OUT_WIDTH-1 : 0] O_non_seq; + wire [non_seq_out_width-1 : 0] Q_seq; + wire [C_OUT_WIDTH-1 : 0] Q_non_seq; + + wire [(2*C_A_WIDTH)-1:0] dummyA = A + A; + wire [ser_seq_cawidth-1:0] seqA = (C_BAAT == C_A_WIDTH ? (C_BAAT == 1 ? dummyA : A) : A); + + wire [(2*C_B_WIDTH)-1:0] dummyB = B + B; + wire [non_seq_cbwidth-1:0] seqB = (C_BAAT == C_A_WIDTH ? (C_B_WIDTH == 1 ? dummyB : B) : B); + + wire intLOADB = ((C_HAS_LOADB == 1 && C_MULT_TYPE > 2) ? LOADB : 0); + wire intSWAPB = ((C_HAS_SWAPB == 1 && C_MULT_TYPE == 4) ? SWAPB : 0); + + wire RFD = (C_HAS_RFD == 1 ? (C_BAAT == C_A_WIDTH ? RFD_non_seq : RFD_seq) : 1'bx); + wire RDY = (C_HAS_RDY == 1 ? (C_BAAT == C_A_WIDTH ? RDY_non_seq : RDY_seq) : 1'bx); + wire LOAD_DONE = (C_HAS_LOAD_DONE == 1 ? (C_BAAT == C_A_WIDTH ? LOAD_DONE_non_seq : LOAD_DONE_seq) : 1'bx); + wire [C_OUT_WIDTH-1 : 0] O = (C_HAS_O == 1 ? (C_BAAT == C_A_WIDTH ? O_non_seq : O_seq) : 1'bx); + wire [C_OUT_WIDTH-1 : 0] Q = (C_HAS_Q == 1 ? (C_BAAT == C_A_WIDTH ? Q_non_seq : Q_seq) : 1'bx); + + MULT_GEN_V6_0_NON_SEQ #(BRAM_ADDR_WIDTH, C_A_TYPE, C_A_WIDTH, C_BAAT, C_B_CONSTANT, + C_B_TYPE, C_B_VALUE, C_B_WIDTH, C_ENABLE_RLOCS, C_HAS_ACLR, + C_HAS_A_SIGNED, C_HAS_B, C_HAS_CE, C_HAS_LOADB, C_HAS_LOAD_DONE, + C_HAS_ND, C_HAS_O, C_HAS_Q, C_HAS_RDY, C_HAS_RFD, C_HAS_SCLR, + C_HAS_SWAPB, C_MEM_INIT_PREFIX, C_MEM_TYPE, C_MULT_TYPE, C_OUTPUT_HOLD, + C_OUT_WIDTH, C_PIPELINE, 0, C_REG_A_B_INPUTS, C_SQM_TYPE, + C_STACK_ADDERS, C_STANDALONE, INT_C_SYNC_ENABLE, C_USE_LUTS, C_V2_SPEED) + non_seq_mult (.A(A), .B(B), .CLK(CLK), .A_SIGNED(A_SIGNED), .CE(CE), + .ACLR(ACLR), .SCLR(SCLR), .LOADB(intLOADB), + .LOAD_DONE(LOAD_DONE_non_seq), .SWAPB(intSWAPB), .RFD(RFD_non_seq), + .ND(ND), .RDY(RDY_non_seq), .O(O_non_seq), + .Q(Q_non_seq)); + + MULT_GEN_V6_0_SEQ #(BRAM_ADDR_WIDTH, C_A_TYPE, non_seq_cawidth, non_seq_cbaat, C_B_CONSTANT, + C_B_TYPE, C_B_VALUE, non_seq_cbwidth, C_ENABLE_RLOCS, C_HAS_ACLR, + C_HAS_A_SIGNED, C_HAS_B, C_HAS_CE, C_HAS_LOADB, C_HAS_LOAD_DONE, + C_HAS_ND, C_HAS_O, C_HAS_Q, C_HAS_RDY, C_HAS_RFD, C_HAS_SCLR, + C_HAS_SWAPB, C_MEM_INIT_PREFIX, C_MEM_TYPE, C_MULT_TYPE, C_OUTPUT_HOLD, + non_seq_out_width, C_PIPELINE, C_REG_A_B_INPUTS, C_SQM_TYPE, + C_STACK_ADDERS, C_STANDALONE, INT_C_SYNC_ENABLE, C_USE_LUTS) + seq_mult (.A(seqA), .B(seqB), .CLK(CLK), .A_SIGNED(A_SIGNED), .CE(CE), + .ACLR(ACLR), .SCLR(SCLR), .LOADB(intLOADB), + .LOAD_DONE(LOAD_DONE_seq), .SWAPB(intSWAPB), .RFD(RFD_seq), .ND(ND), + .RDY(RDY_seq), .O(O_seq), + .Q(Q_seq)); + + initial + begin + + end + +endmodule + +`undef c_set +`undef c_clear +`undef c_override +`undef c_no_override +`undef c_add +`undef c_sub +`undef c_add_sub +`undef c_signed +`undef c_unsigned +`undef c_pin + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/MULT_GEN_V6_0_NON_SEQ.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/MULT_GEN_V6_0_NON_SEQ.v new file mode 100644 index 0000000..9c2e0b7 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/MULT_GEN_V6_0_NON_SEQ.v @@ -0,0 +1,2919 @@ +// Copyright(C) 2002 by Xilinx, Inc. All rights reserved. +// This text contains proprietary, confidential +// information of Xilinx, Inc., is distributed +// under license from Xilinx, Inc., and may be used, +// copied and/or disclosed only pursuant to the terms +// of a valid license agreement with Xilinx, Inc. This copyright +// notice must be retained as part of this text at all times. + + +/* $Id: +-- +-- Filename - MULT_GEN_V6_0_NON_SEQ.v +-- Author - Xilinx +-- Creation - 22 Mar 1999 +-- +-- Description - This file contains the Verilog behavior for the +-- non-sequential multiplier module +*/ + +`timescale 1ns/10ps + +`define c_set 0 +`define c_clear 1 +`define c_override 0 +`define c_no_override 1 +`define c_add 0 +`define c_sub 1 +`define c_add_sub 2 +`define c_signed 0 +`define c_unsigned 1 +`define c_pin 2 +`define c_distributed 0 +`define c_dp_block 2 +`define allUKs {(C_OUT_WIDTH)+1{1'bx}} +`define all0s {(C_OUT_WIDTH)+1{1'b0}} +`define ball0s {(C_B_WIDTH)+1{1'b0}} +`define ballxs {(C_B_WIDTH)+1{1'bx}} +`define aall0s {(C_BAAT+C_HAS_A_SIGNED)+1{1'b0}} +`define aall1s {(C_BAAT+C_HAS_A_SIGNED)+1{1'b1}} +`define aallxs {(C_BAAT+C_HAS_A_SIGNED)+1{1'bx}} +`define inall0s {(C_A_WIDTH-1-((C_A_WIDTH-1)*C_SQM_TYPE))+1{1'b0}} +`define baatall0s {(C_BAAT)+1{1'b0}} +`define baatall1s {(C_BAAT)+1{1'b1}} +`define baatallxs {(C_BAAT)+1{1'bx}} + +module MULT_GEN_V6_0_NON_SEQ (A, B, CLK, A_SIGNED, CE, ACLR, + SCLR, LOADB, LOAD_DONE, SWAPB, RFD, + ND, RDY, O, Q); + + parameter BRAM_ADDR_WIDTH = 8; + parameter C_A_TYPE = `c_signed; + parameter C_A_WIDTH = 16; + parameter C_BAAT = 2; + parameter C_B_CONSTANT = `c_signed; + parameter C_B_TYPE = `c_signed; + parameter C_B_VALUE = "0000000000000001"; + parameter C_B_WIDTH = 16; + parameter C_ENABLE_RLOCS = 1; + parameter C_HAS_ACLR = 0; + parameter C_HAS_A_SIGNED = 0; + parameter C_HAS_B = 1; + parameter C_HAS_CE = 0; + parameter C_HAS_LOADB = 0; + parameter C_HAS_LOAD_DONE = 0; + parameter C_HAS_ND = 0; + parameter C_HAS_O = 0; + parameter C_HAS_Q = 1; + parameter C_HAS_RDY = 0; + parameter C_HAS_RFD = 0; + parameter C_HAS_SCLR = 0; + parameter C_HAS_SWAPB = 0; + parameter C_MEM_INIT_PREFIX = "mem"; + parameter C_MEM_TYPE = 0; + parameter C_MULT_TYPE = 0; + parameter C_OUTPUT_HOLD = 0; + parameter C_OUT_WIDTH = 16; + parameter C_PIPELINE = 0; + parameter C_PRE_DELAY = 0; + parameter C_REG_A_B_INPUTS = 1; + parameter C_SQM_TYPE = 0; + parameter C_STACK_ADDERS = 0; + parameter C_STANDALONE = 0; + parameter C_SYNC_ENABLE = 0; + parameter C_USE_LUTS = 1; + + //Internal parameters + + parameter incA = (((C_HAS_A_SIGNED == 1 || C_A_TYPE == `c_signed) && C_B_TYPE == `c_unsigned) ? 1 : 0) ; + parameter incB = (C_B_TYPE == `c_signed ? 1 : 0) ; + parameter inc = ((C_B_TYPE == `c_unsigned && C_A_TYPE == `c_unsigned) ? 0 : 1) ; + parameter dec = ((C_B_TYPE == `c_unsigned && C_A_TYPE == `c_unsigned) ? 1 : 0) ; + parameter inc_a_width = ((C_BAAT < C_A_WIDTH && (C_HAS_A_SIGNED == 1 || C_A_TYPE == `c_signed) && C_HAS_LOADB == 0) ? 1 : 0) ; + parameter decrement = ((C_HAS_A_SIGNED == 1 || (C_A_TYPE == `c_signed && C_BAAT < C_A_WIDTH)) ? 1 : 0) ; + + //Parameters to calculate the latency for the parallel multiplier. + parameter a_ext_width_par = (C_HAS_A_SIGNED == 1 ? C_BAAT+1 : C_BAAT) ; + parameter a_ext_width_seq = ((C_HAS_A_SIGNED == 1 || C_A_TYPE == `c_signed) ? C_BAAT+1 : C_BAAT) ; + parameter a_ext_width = (C_BAAT < C_A_WIDTH ? a_ext_width_seq : a_ext_width_par) ; + + /* Compare the width of the A port, to the width of the B port + If the A port is smaller, then swap these over, otherwise leave + alone */ + + parameter a_t_2 = (C_A_TYPE == `c_pin ? `c_signed : C_A_TYPE); + + parameter a_w = (C_A_WIDTH < C_B_WIDTH ? C_B_WIDTH : a_ext_width); + parameter a_t = (C_A_WIDTH < C_B_WIDTH ? C_B_TYPE : a_t_2); + parameter b_w = (C_A_WIDTH < C_B_WIDTH ? a_ext_width : C_B_WIDTH); + parameter b_t = (C_A_WIDTH < C_B_WIDTH ? a_t_2 : C_B_TYPE); + + // The mult18 parameter signifies if the final mult18x18 primitive is used + // without having to pad with zeros, or sign extending - thus leading to + // a more efficient implementation - e.g. a 35x35 (signed x signed) multiplier + // mult18, is used in the calculation of a_prods and b_prods, which indicate + // how many mult18x18 primitives are requred. + + parameter mult18 = (((a_t == `c_signed && a_w % 17 == 1) + && ((b_t == `c_signed && b_w <= a_w) || (b_t == `c_unsigned && b_w < a_w))) ? 1 : 0); + + parameter a_prods = (a_ext_width-1)/(17 + mult18) + 1 ; + parameter b_prods = (C_B_WIDTH-1)/(17 + mult18) + 1 ; + parameter a_count = (a_ext_width+1)/2 ; + parameter b_count = (C_B_WIDTH+1)/2 ; + parameter parm_numAdders = (C_MULT_TYPE == 1 ? (a_prods*b_prods) : ((a_ext_width <= C_B_WIDTH) ? a_count : b_count)) ; + parameter ignore_nd = ((C_HAS_ND == 0 || (C_HAS_ND == 1 && C_REG_A_B_INPUTS == 0 && C_HAS_Q == 0 && (C_PIPELINE == 0 || parm_numAdders == 1))) ? 1 : 0); + parameter true_ce = (C_HAS_CE == 1 ? 1 : (ignore_nd == 1 ? 0 : 1)); + parameter mult18s = (C_MULT_TYPE != 1 ? 0 : ((C_HAS_ACLR == 0 && (~(C_SYNC_ENABLE == 1 && C_HAS_SCLR == 1 && true_ce == 1))) ? 1 : 0)); + + //Parameters to calculate the latency for the constant coefficient multiplier. + parameter rom_addr_width = (C_MEM_TYPE == `c_distributed ? 4 : BRAM_ADDR_WIDTH) ; + parameter sig_addr_bits = (C_BAAT >= rom_addr_width ? rom_addr_width : C_BAAT) ; + parameter effective_op_width = ((C_BAAT == C_A_WIDTH && (C_HAS_A_SIGNED == 0 || C_HAS_LOADB == 1)) ? C_BAAT : ((C_BAAT == C_A_WIDTH) ? C_BAAT+1 : (C_BAAT < C_A_WIDTH ? C_BAAT+inc_a_width : C_BAAT+1))) ; + parameter a_input_width = ((effective_op_width % rom_addr_width == 0) ? effective_op_width : effective_op_width + rom_addr_width - (effective_op_width % rom_addr_width)) ; + parameter mod = a_input_width % rom_addr_width ; + parameter op_width = (mod == 0 ? a_input_width : (a_input_width + rom_addr_width) - mod) ; + parameter a_width = (C_BAAT < C_A_WIDTH ? C_A_WIDTH : op_width) ; + parameter need_addsub = ((C_HAS_LOADB == 1 && (C_A_TYPE == `c_signed || C_HAS_A_SIGNED == 1)) ? 1 : 0) ; + parameter ccm_numAdders_1 = (mod == 0 ? (a_input_width/rom_addr_width) : (a_input_width/rom_addr_width)+1) ; + parameter need_0_minus_pp = ((need_addsub == 1 && ccm_numAdders_1 <= 1) ? 1 : 0) ; + parameter ccm_numAdders = (need_0_minus_pp == 1 ? 1 : ccm_numAdders_1 - 1) ; + parameter ccm_init1 = ((C_HAS_LOADB == 1 && C_MEM_TYPE == `c_dp_block) ? 1 : 0) ; + parameter ccm_init2 = ((C_HAS_LOADB == 1 && (C_A_TYPE == `c_signed || C_HAS_A_SIGNED == 1) && C_PIPELINE == 1) ? 1 : 0) ; + parameter ccm_init3 = (((ccm_numAdders > 0 || C_HAS_SWAPB == 1) && (C_PIPELINE == 1 || C_MEM_TYPE == `c_dp_block)) ? 1 : 0) ; + parameter ccm_init4 = ((ccm_numAdders > 0 && C_HAS_SWAPB == 1 && C_PIPELINE == 1) ? 1 : 0) ; + parameter ccm_initial_latency = ccm_init1 + ccm_init2 + ccm_init3 + ccm_init4 ; + + //Latency calculation + parameter numAdders = (C_MULT_TYPE < 2 ? parm_numAdders - 1 : ccm_numAdders) ; + parameter log = (C_PIPELINE == 1 ? (numAdders < 2 ? 0 : (numAdders < 4 ? 1 : (numAdders < 8 ? 2 : (numAdders < 16 ? 3 : (numAdders < 32 ? 4 : (numAdders < 64 ? 5 : (numAdders < 128 ? 6 : 7))))))) : 0) ; + parameter C_LATENCY_sub = (C_MULT_TYPE < 2 ? (numAdders > 0 ? (mult18s + log + 1) : (C_PIPELINE == 1 ? mult18s : 0)) : (numAdders > 0 ? (ccm_initial_latency + log) : ccm_initial_latency)) ; + parameter C_LATENCY = (C_PIPELINE == 1 ? C_LATENCY_sub : (C_MULT_TYPE < 2 ? 0 : C_LATENCY_sub)) ; + + parameter c_pipe = (C_PIPELINE == 1 || C_LATENCY > 0) ? 1 : 0 ; + + parameter multWidth = C_A_WIDTH+C_B_WIDTH+decrement+1 ; + parameter rfd_stages = 1; + + parameter no_aclr = (C_MULT_TYPE == 2 && (C_HAS_Q == 0 || (numAdders == 0 && C_MEM_TYPE == 2)) && + C_REG_A_B_INPUTS == 0 && C_HAS_RFD == 0 && + (C_LATENCY == 0 || (numAdders == 1 && C_MEM_TYPE == 2) || (C_LATENCY == 1 && + C_PIPELINE == 0 && C_MEM_TYPE == 2 && C_MULT_TYPE == 2)) && + ~(C_B_WIDTH == 1 && C_MULT_TYPE == 2 && C_HAS_Q == 1 && C_MEM_TYPE == 2) ? 1 : 0); + + parameter ncelab_inta_high = ((C_A_WIDTH == C_BAAT) ? C_A_WIDTH : (C_SQM_TYPE == 0 ? C_A_WIDTH : 1)); + + `define mall0s {(multWidth)+1{1'b0}} + `define mallUKs {(multWidth)+1{1'bx}} + + input [(C_A_WIDTH-1-((C_A_WIDTH-1)*C_SQM_TYPE)) : 0] A; + input [C_B_WIDTH-1 : 0] B; + input CLK; + input CE; + input A_SIGNED; + input LOADB; + input SWAPB; + input ND; + input ACLR; + input SCLR; + output RFD; + output RDY; + output LOAD_DONE; + output [C_OUT_WIDTH-1 : 0] O; + output [C_OUT_WIDTH-1 : 0] Q; + + // Internal values to drive signals when input is missing + wire [C_B_WIDTH-1 : 0] intBconst; + reg [C_B_WIDTH-1 : 0] intB; + reg [(C_A_WIDTH-1-((C_A_WIDTH-1)*C_SQM_TYPE)) : 0] intA; + wire [C_B_WIDTH-1 : 0] regB; + wire [C_B_WIDTH-1 : 0] regB_cased; + wire [(C_A_WIDTH-1-((C_A_WIDTH-1)*C_SQM_TYPE)) : 0] regA; + wire [C_B_WIDTH-1 : 0] B_DLY_1; + wire [C_B_WIDTH-1 : 0] B_DLY_2; + wire LOADB_DLY_1; + wire LOADB_DLY_2; + wire SWAPB_DLY_1; + wire SWAPB_DLY_2; + reg [C_B_WIDTH-1 : 0] b_const0; + reg [C_B_WIDTH-1 : 0] b_const1; + reg [C_B_WIDTH-1 : 0] loadb_value ; + reg [C_B_WIDTH-1 : 0] B_INPUT; + + wire intCE; + wire intCE_cased; + reg intA_SIGNED; + wire regA_SIGNED; + reg intACLR; + reg intSCLR; + wire ND_I; + wire [(C_A_WIDTH-1-((C_A_WIDTH-1)*C_SQM_TYPE)) : 0] A_I; + wire [C_B_WIDTH-1 : 0] B_I; + wire LOADB_I; + wire SWAPB_I; + wire initial_intCLK; + reg intCLK; + reg last_clk; + wire intLOADB; + wire intLOADB_no_predelay; + reg loaded; + wire intSWAPB; + reg regND_nonseq; + wire regND_ccm; + wire regND_parm; + wire regND; + wire intND ; + wire intRDY; + reg intRDY_rl; + wire intRDY_rl_pre_reg; + reg intRFD; + reg intRFD_rel; + reg regRFD ; + reg regRDY ; + reg intLOAD_DONE; + reg [C_OUT_WIDTH-1 : 0 ] O_I; + reg [C_OUT_WIDTH-1 : 0 ] Q_I; + reg RDY_I; + reg [C_OUT_WIDTH-1 : 0 ] intO; + reg lastCLK; + reg [C_BAAT-1 : 0] max_a_val ; + reg power_2; + + reg [multWidth-1 : 0] a_value ; + reg [multWidth-1 : 0] b_value ; + reg [multWidth-1 : 0] max_result ; + reg [multWidth : 0] max_result1 ; + reg [multWidth : 0] max_result2 ; + + reg [C_OUT_WIDTH-1 : 0] intQpipe [C_LATENCY+1 : 0]; + reg [C_LATENCY : 0] intRDYpipe; + + // Output ports. + wire [C_OUT_WIDTH-1 : 0] Q; + wire [C_OUT_WIDTH-1 : 0] O; + wire RDY; + wire RFD; + wire LOAD_DONE; + + // Assign values to the output ports after a delay. + assign #1 Q = (C_HAS_Q == 1 ? Q_I : `allUKs); + assign #1 O = (C_HAS_O == 1 ? O_I : `allUKs); + assign #1 RDY = (C_HAS_RDY == 1 ? (C_HAS_ND == 1 ? (C_HAS_Q == 1 ? regRDY : RDY_I) : 1) : 1'bx); + assign #1 RFD = (C_HAS_RFD == 1 ? intRFD : 1'bx); + assign #1 LOAD_DONE = (C_HAS_LOAD_DONE == 1 ? intLOAD_DONE : 1'bx); + + // Sort out default values for missing ports + assign regND = regND_nonseq; + assign intCE = (C_HAS_CE == 1 ? CE : 1); + assign intCE_cased = ((C_HAS_CE == 1 && C_HAS_ND == 1) ? + (C_SYNC_ENABLE == 1 ? ((~intLOAD_DONE) | (intCE & ND_I)) + : ((~intLOAD_DONE) | (intCE & ND_I) | intSCLR)) + : (C_HAS_ND == 1 ? + (C_SYNC_ENABLE == 1 ? ((~intLOAD_DONE) | ND_I) + : ((~intLOAD_DONE) | ND_I | intSCLR)) + : 1'b1)); + assign initial_intCLK = CLK; + assign intND = ((C_HAS_ND == 1 && ND !== 1'bz) ? ND : 1); + + assign intLOADB = ((C_HAS_LOADB == 1 && C_MULT_TYPE > 2) ? LOADB_I : 0) ; + assign intLOADB_no_predelay = ((C_HAS_LOADB == 1 && C_MULT_TYPE > 2) ? LOADB : 0); + assign intSWAPB = ((C_HAS_SWAPB == 1 && C_MULT_TYPE > 2) ? SWAPB_I : 0) ; + + //assign intSCLR = (C_HAS_SCLR == 1 ? SCLR : 0); + assign ND_I = ((C_HAS_ND == 1 && ND !== 1'bz) ? ND : 1); + assign A_I = A; + assign B_I = (C_PRE_DELAY == 0 ? B : (C_PRE_DELAY == 1 ? B_DLY_1 : B_DLY_2)); + assign SWAPB_I = (C_PRE_DELAY == 0 ? SWAPB : (C_PRE_DELAY == 1 ? SWAPB_DLY_1 : SWAPB_DLY_2)); + assign LOADB_I = (C_PRE_DELAY == 0 ? LOADB : (C_PRE_DELAY == 1 ? LOADB_DLY_1 : LOADB_DLY_2)); + + assign intRDY_rl_pre_reg = intND & intLOAD_DONE; + assign intRDY = (C_MULT_TYPE == 3 ? (C_REG_A_B_INPUTS == 0 ? ND_I & intLOAD_DONE : intRDY_rl) + : (C_MULT_TYPE > 1 ? (C_REG_A_B_INPUTS == 0 ? ND_I : regND) + : ((C_LATENCY+C_REG_A_B_INPUTS == 0 || (C_LATENCY == 1 && C_REG_A_B_INPUTS == 0 && C_HAS_Q == 0)) ? ND_I & intCE + : ((C_LATENCY == 0 && C_REG_A_B_INPUTS == 1 && C_HAS_Q == 0) ? regND_ccm : regND & intCE)))); + + integer j, k, test1, msb; + integer pipe, pipe1; + integer i; + integer cycle, loadb_count, loadb_count_no_predelay, loadb_count_dly, loadb_count_dly_int, out_width, tmp_out_width, b_is_negative, b_width, new_data_present; + integer stay_x, bank_sel, bank_sel_pre, loadb_delay, pre_delay_comp ; + integer shift_bits, real_latency ; + integer loading, cycle_discarded, b_is_zero, b_is_one, a_negative, b_negative ; + + reg [C_B_WIDTH-1 : 0] initB_INPUT; + reg [multWidth-1 : 0] tmpA; + reg [multWidth-1 : 0] tmpB; + reg [multWidth-1 : 0] tmpAB; + reg tmpA_SIGNED ; + + reg [multWidth-1 : 0] one; + reg [multWidth-1 : 0] zero ; + reg cleared; + + reg [multWidth-1 : 0] product ; + reg [multWidth-1 : 0] product_delayed ; + reg [C_LATENCY : 0] intPRODUCTpipe [multWidth-1 : 0] ; + + //Input registers. + C_REG_FD_V6_0 #("0", C_ENABLE_RLOCS, C_HAS_ACLR, 0, 0, + C_HAS_CE, C_HAS_SCLR, 0, 0, + "0", C_SYNC_ENABLE, 0, (C_A_WIDTH-1-((C_A_WIDTH-1)*C_SQM_TYPE))+1) + rega (.D(A_I), .CLK(intCLK), .CE(intCE), .ACLR(intACLR), .ASET(1'b0), + .AINIT(1'b0), .SCLR(intSCLR), .SSET(1'b0), .SINIT(1'b0), + .Q(regA)); + + C_REG_FD_V6_0 #("0", C_ENABLE_RLOCS, C_HAS_ACLR, 0, 0, + C_HAS_CE, C_HAS_SCLR, 0, 0, + "0", C_SYNC_ENABLE, 0, C_B_WIDTH) + regad1 (.D(B), .CLK(intCLK), .CE(intCE), .ACLR(intACLR), .ASET(1'b0), + .AINIT(1'b0), .SCLR(intSCLR), .SSET(1'b0), .SINIT(1'b0), + .Q(B_DLY_1)); + + C_REG_FD_V6_0 #("0", C_ENABLE_RLOCS, C_HAS_ACLR, 0, 0, + C_HAS_CE, C_HAS_SCLR, 0, 0, + "0", C_SYNC_ENABLE, 0, C_B_WIDTH) + regad2 (.D(B_DLY_1), .CLK(intCLK), .CE(intCE), .ACLR(intACLR), .ASET(1'b0), + .AINIT(1'b0), .SCLR(intSCLR), .SSET(1'b0), .SINIT(1'b0), + .Q(B_DLY_2)); + + C_REG_FD_V6_0 #("0", C_ENABLE_RLOCS, C_HAS_ACLR, 0, 0, + C_HAS_CE, C_HAS_SCLR, 0, 0, + "0", C_SYNC_ENABLE, 0, 1) + regswapb1 (.D(SWAPB), .CLK(intCLK), .CE(intCE), .ACLR(intACLR), .ASET(1'b0), + .AINIT(1'b0), .SCLR(intSCLR), .SSET(1'b0), .SINIT(1'b0), + .Q(SWAPB_DLY_1)); + + C_REG_FD_V6_0 #("0", C_ENABLE_RLOCS, C_HAS_ACLR, 0, 0, + C_HAS_CE, C_HAS_SCLR, 0, 0, + "0", C_SYNC_ENABLE, 0, 1) + regswapb2 (.D(SWAPB_DLY_1), .CLK(intCLK), .CE(intCE), .ACLR(intACLR), .ASET(1'b0), + .AINIT(1'b0), .SCLR(intSCLR), .SSET(1'b0), .SINIT(1'b0), + .Q(SWAPB_DLY_2)); + + C_REG_FD_V6_0 #("0", C_ENABLE_RLOCS, C_HAS_ACLR, 0, 0, + C_HAS_CE, C_HAS_SCLR, 0, 0, + "0", C_SYNC_ENABLE, 0, 1) + regloadb1 (.D(LOADB), .CLK(intCLK), .CE(intCE), .ACLR(intACLR), .ASET(1'b0), + .AINIT(1'b0), .SCLR(intSCLR), .SSET(1'b0), .SINIT(1'b0), + .Q(LOADB_DLY_1)); + + C_REG_FD_V6_0 #("0", C_ENABLE_RLOCS, C_HAS_ACLR, 0, 0, + C_HAS_CE, C_HAS_SCLR, 0, 0, + "0", C_SYNC_ENABLE, 0, 1) + regloadb2 (.D(LOADB_DLY_1), .CLK(intCLK), .CE(intCE), .ACLR(intACLR), .ASET(1'b0), + .AINIT(1'b0), .SCLR(intSCLR), .SSET(1'b0), .SINIT(1'b0), + .Q(LOADB_DLY_2)); + + C_REG_FD_V6_0 #("0", C_ENABLE_RLOCS, C_HAS_ACLR, 0, 0, + C_HAS_CE, C_HAS_SCLR, 0, 0, + "0", C_SYNC_ENABLE, 0, C_B_WIDTH) + regb (.D(B_INPUT), .CLK(intCLK), .CE(intCE), .ACLR(intACLR), .ASET(1'b0), + .AINIT(1'b0), .SCLR(intSCLR), .SSET(1'b0), .SINIT(1'b0), + .Q(regB)); + + C_REG_FD_V6_0 #("0", C_ENABLE_RLOCS, C_HAS_ACLR, 0, 0, + 1, C_HAS_SCLR, 0, 0, + "0", C_SYNC_ENABLE, 0, C_B_WIDTH) + regb_cased (.D(B_INPUT), .CLK(intCLK), .CE(intCE_cased), .ACLR(intACLR), .ASET(1'b0), + .AINIT(1'b0), .SCLR(intSCLR), .SSET(1'b0), .SINIT(1'b0), + .Q(regB_cased)); + + C_REG_FD_V6_0 #("0", C_ENABLE_RLOCS, C_HAS_ACLR, 0, 0, + C_HAS_CE, C_HAS_SCLR, 0, 0, + "0", C_SYNC_ENABLE, 0, 1) + regnd (.D(ND), .CLK(intCLK), .CE(intCE), .ACLR(intACLR), .ASET(1'b0), + .AINIT(1'b0), .SCLR(intSCLR), .SSET(1'b0), .SINIT(1'b0), + .Q(regND_ccm)); + + C_REG_FD_V6_0 #("0", C_ENABLE_RLOCS, C_HAS_ACLR, 0, 0, + 0, C_HAS_SCLR, 0, 0, + "0", C_SYNC_ENABLE, 0, 1) + regndparm (.D(ND), .CLK(intCLK), .CE(intCE), .ACLR(intACLR), .ASET(1'b0), + .AINIT(1'b0), .SCLR(intSCLR), .SSET(1'b0), .SINIT(1'b0), + .Q(regND_parm)); + + C_REG_FD_V6_0 #("0", C_ENABLE_RLOCS, C_HAS_ACLR, 0, 0, + C_HAS_CE, C_HAS_SCLR, 0, 0, + "0", C_SYNC_ENABLE, 0, 1) + regasig (.D(A_SIGNED), .CLK(intCLK), .CE(intCE), .ACLR(intACLR), .ASET(1'b0), + .AINIT(1'b0), .SCLR(intSCLR), .SSET(1'b0), .SINIT(1'b0), + .Q(regA_SIGNED)); + + initial + begin + B_INPUT = (C_MULT_TYPE < 2) ? B : to_bitsB(C_B_VALUE); + if (C_MULT_TYPE > 2 && C_B_TYPE == `c_signed) + begin + j = 0 ; + msb = 0 ; + //Find the length of the C_B_VALUE string + for(i = 0; i < (C_B_WIDTH*8); i = i + 1) + begin + if(C_B_VALUE[i] == 0 || C_B_VALUE[i] == 1) + msb = i/8 ; + end + //Pad it with 1's if it is signed and negative. + for(i = msb; i < C_B_WIDTH; i = i + 1) + begin + B_INPUT[i] = B_INPUT[msb]; + end + end + //Initialise all the signals that need to be initialised at start up. + intRFD = 1 ; + regRFD = 1 ; + loading = 0 ; + intRFD_rel = 1; + + if (C_HAS_ND == 1 && C_BAAT == C_A_WIDTH) + begin + regRDY = 0; + RDY_I = 0; + intRDY_rl = 0; + end + else + begin + regRDY = 1; + RDY_I = 1; + intRDY_rl = 1; + end + + O_I = `all0s; + bank_sel = 0 ; + bank_sel_pre = 0; + b_const0 = B_INPUT ; + b_const1 = B_INPUT ; + loadb_value = B_INPUT ; + intB = B_INPUT ; + tmpB = B_INPUT ; + intLOAD_DONE = 1 ; + loadb_count = -1 ; + loadb_count_no_predelay = -1; + loaded = 0 ; + stay_x = 0; + tmpA = `aallxs; + //tmpAB = `mall0s; + intACLR = 0; + intSCLR = 0; + cleared = 0; + + if (C_HAS_ND == 0) + begin + for(k = 0 ; k <= C_LATENCY; k = k + 1) + begin + intRDYpipe[k] = 1 ; + end + end + else if (C_HAS_ND == 1) + begin + for(k = 0 ; k <= C_LATENCY; k = k + 1) + begin + intRDYpipe[k] = 0 ; + end + end + initB_INPUT = (C_MULT_TYPE < 2) ? B : to_bitsB(C_B_VALUE); + new_data_present = 0 ; + + //Clear the pipeline and the inputs if there are registers involved. + for(j = 0; j < multWidth; j = j + 1) + begin + if (C_REG_A_B_INPUTS == 1) + begin + intA[j] = 0 ; + tmpA[j] = 0 ; + if(C_MULT_TYPE < 2) + begin + intB[j] = 0 ; + tmpB[j] = 0 ; + end + end + end + for (j = 0; j <= C_LATENCY; j = j + 1) + begin + intQpipe[j] = `all0s ; + end + + for(i = 0; i < multWidth; i = i + 1) + begin + if (i > 0) + begin + one[i] = 0 ; + zero[i] = 0 ; + end + else + begin + one[i] = 1 ; + zero[i] = 0 ; + end + end + + if (C_MULT_TYPE > 2) + begin + loadb_delay = 1 ; + for(i = 0; i < sig_addr_bits; i = i + 1) + begin + loadb_delay = 2*loadb_delay ; + end + loadb_delay = loadb_delay-1 ; + if (C_PRE_DELAY == 0) + pre_delay_comp = 0; + else if (C_PRE_DELAY == 1) + pre_delay_comp = 1; + else if (C_PRE_DELAY == 2 && loadb_delay > 1) + pre_delay_comp = 2; + else + pre_delay_comp = loadb_delay; + end + + //Find the real b input width + if (C_MULT_TYPE > 1 && C_HAS_LOADB == 0) + begin + b_width = 0 ; + for(i = 0; i < C_B_WIDTH; i = i + 1) + begin + if(initB_INPUT[i] == 1) + b_width = i+1 ; + end + end + else + begin + b_width = C_B_WIDTH ; + end + + //Calculate the output width of the multiplier. + a_negative = 0 ; + b_negative = 0 ; + + power_2 = 1'b1; + for (i = 0; i < C_B_WIDTH; i = i + 1) + begin + if ((initB_INPUT[i] == 1) && (i!=C_B_WIDTH-1)) + power_2 = 1'b0; + end + + if (C_A_TYPE == `c_signed) + begin + a_negative = 1 ; + max_a_val = `aall0s ; + max_a_val[C_BAAT-1] = 1; + end + else + begin + max_a_val = `aall1s ; + end + + if ((initB_INPUT[b_width-1] == 1) && (C_B_TYPE == `c_signed)) + b_negative = 1 ; + + for (i = 0; i < b_width; i = i + 1) + begin + if ((initB_INPUT[b_width-1] == 1) && (C_B_TYPE == `c_signed)) + begin + b_value[i] = ~initB_INPUT[i] ; + end + else + begin + b_value[i] = initB_INPUT[i] ; + end + end + + for (i = 0; i < C_BAAT; i = i + 1) + begin + a_value[i] = max_a_val[i] ; + end + for (i = C_BAAT; i < multWidth; i = i + 1) + begin + if(a_negative == 1 && power_2 ==1 ) + a_value[i] = 1 ; + else + a_value[i] = 0 ; + end + + for (i = b_width; i < multWidth; i = i + 1) + begin + if (C_B_TYPE == `c_signed && b_value[b_width-1] == 1) + begin + b_value[i] = 1 ; + end + else + begin + b_value[i] = 0 ; + end + end + + if ((initB_INPUT[b_width-1] == 1) && (C_B_TYPE == `c_signed)) + begin + b_value = add(b_value, one) ; + end + + for (i = b_width; i < multWidth; i = i + 1) + begin + if (C_B_TYPE == `c_signed && b_value[b_width-1] == 1) + begin + b_value[i] = 1 ; + end + else + begin + b_value[i] = 0 ; + end + end + + max_result = a_value * b_value ; + + j = 0 ; + if ((max_result[multWidth-1] == 1) && (C_B_TYPE == `c_signed || C_A_TYPE == `c_signed || C_HAS_A_SIGNED == 1)) + j = 1 ; + + if (C_MULT_TYPE > 1 && C_HAS_LOADB == 0) + begin + if (C_A_WIDTH == 1) + begin + if (C_A_TYPE == `c_signed || C_A_TYPE == `c_pin) + begin + out_width = C_B_WIDTH+1; + end + else + begin + out_width = C_B_WIDTH; + end + end + else + begin + for(i = 0; i < multWidth; i = i + 1) + begin + if(max_result[i] == 1) + out_width = i+1 ; + end + tmp_out_width = out_width ; + if (a_negative == 1 && b_negative == 1) + out_width = out_width+1 ; + else if ((a_negative == 1 && b_negative == 0) || (a_negative == 0 && b_negative == 1)) + begin + max_result1 = max_result; + if (power_2 == 1) + begin + max_result1[multWidth] = 1; + + for(i = 0; i <= multWidth; i = i + 1) + begin + if(max_result1[i] == 1) + tmp_out_width = i+1 ; + end + for(i = 0; i <= tmp_out_width; i = i + 1) + begin + if(max_result1[i] == 0) + out_width = i+2 ; + end + end + else if ((power_2 !=1)) + begin + for (i = 0; i <= multWidth; i = i + 1) + begin + max_result[i] = ~max_result[i] ; + end + max_result = add(max_result, one) ; + for(i = 0; i <= multWidth; i = i + 1) + begin + if(max_result[i] == 1) + tmp_out_width = i+1 ; + end + for(i = 0; i < tmp_out_width; i = i + 1) + begin + if(max_result[i] == 0) + out_width = i+2 ; + end + end + end + + if (C_HAS_A_SIGNED == 1 && C_B_TYPE == `c_unsigned) + out_width = out_width + 1 ; + end + end + else + begin + if (C_MULT_TYPE > 2 && C_B_WIDTH == 1) + begin + if (C_HAS_A_SIGNED == 1 && C_B_TYPE == `c_unsigned) + out_width = C_A_WIDTH + 1 ; + else + out_width = C_A_WIDTH ; + end + else if (C_MULT_TYPE > 2 && C_A_WIDTH == 1) + begin + if (C_HAS_A_SIGNED == 1 && C_B_TYPE == `c_unsigned) + out_width = C_B_WIDTH + 1 ; + else + out_width = C_B_WIDTH ; + end + else + begin + if (C_HAS_A_SIGNED == 1 && C_B_TYPE == `c_unsigned) + out_width = C_A_WIDTH + C_B_WIDTH + 1 ; + else + out_width = C_A_WIDTH + C_B_WIDTH ; + end + end + + //Calculate the shift bits + if (C_MULT_TYPE != 2) + begin + shift_bits = 0 ; + end + else + begin + shift_bits = 0 ; + for(i = C_B_WIDTH-1; i >= 0; i = i - 1) + begin + if (b_value[i] == 1) + shift_bits = i ; + end + end + + if (C_MULT_TYPE == 2 && ((C_B_TYPE == `c_unsigned && (b_width-shift_bits) == 1 && C_HAS_LOADB == 0) || (C_HAS_LOADB == 0 && b_width == 0))) + begin + if(C_BAAT == C_A_WIDTH) + begin + real_latency = 0 ; + if(C_MULT_TYPE == 2 && + B_INPUT[0] == 0 && + b_width == 0) + begin + b_is_zero = 1 ; + b_is_one = 0 ; + end + else if(((C_MULT_TYPE == 2 && + B_INPUT[0] == 1 && + b_width == 1) || power_2 === 1'b1) && C_B_TYPE == `c_unsigned) + begin + b_is_zero = 0 ; + b_is_one = 1 ; + end + else + begin + b_is_zero = 0 ; + b_is_one = 0 ; + end + end + else + begin + real_latency = C_LATENCY ; + b_is_zero = 0 ; + b_is_one = 0 ; + end + end + else + begin + real_latency = C_LATENCY ; + b_is_zero = 0 ; + b_is_one = 0 ; + end + + if (C_MULT_TYPE < 3 && C_REG_A_B_INPUTS == 1) + begin + tmpA <= `aall0s; + tmpAB <= `mall0s; + end + //if (C_MULT_TYPE < 3) + //begin + intO <= `all0s; + intQpipe[0] <= `all0s; + //end + for (j = 0; j <= real_latency; j = j + 1) + begin + intQpipe[j] = `all0s ; + end + + //O_I = `all0s; + Q_I = `all0s; + + end + + always@(initial_intCLK) + begin + last_clk <= intCLK ; + intCLK <= initial_intCLK ; + end + + always@(ACLR) + begin + if (C_HAS_ACLR == 1 && ACLR === 1'bz) + intACLR = 1'b0; + else if (C_HAS_ACLR == 1 && real_latency == 0 && C_REG_A_B_INPUTS == 0 + && C_MULT_TYPE < 3 && C_HAS_Q == 0) + intACLR = 1'b0; + else if (C_HAS_ACLR == 1) + intACLR = ACLR; + else + intACLR = 1'b0; + end + + always@(SCLR) + begin + if (C_HAS_SCLR == 1 && real_latency == 0 && C_REG_A_B_INPUTS == 0 + && C_MULT_TYPE < 3 && C_HAS_Q == 0) + intSCLR = 1'b0; + else if (C_HAS_SCLR == 1) //&& ~(C_MULT_TYPE == 3 && loadb_count != -1)) + intSCLR = SCLR; + else + intSCLR = 1'b0; + end + + //Choose between regND_ccm and regND_parm depending on the type of multiplier + //that has been instantiated. + always@(regND_ccm or regND_parm) + begin + if (C_HAS_ND == 1) + begin + if (C_MULT_TYPE < 2 && C_BAAT == C_A_WIDTH) + begin + regND_nonseq = regND_parm; + end + else + begin + regND_nonseq = regND_ccm; + end + end + else //no ND + begin + regND_nonseq = 1; + end + end + + //Calculate the RFD output for the non-sequential multiplier. + //The effect of reloading on the RFD is taken into account later on. + always@(intACLR or intSCLR or intRFD_rel) + begin + if (intACLR === 1'b1 || intSCLR === 1'b1 || intRFD_rel === 1'b0) + begin + intRFD = 0; + end + else if (intACLR === 1'bx || intSCLR === 1'bx || intRFD_rel === 1'bx) + begin + intRFD = 1'bx; + end + else + begin + intRFD = 1; + end + end + + // Multiplication processes for the non-sequential multiplier. + // The following occurs asynchronously to the clock. It helps us set + // up the inputs to the multiplication stage. + always@(regA or regB or A_I or B_INPUT or A_SIGNED or regA_SIGNED or intACLR or intND) + begin + if (C_BAAT == C_A_WIDTH) + begin + if (C_REG_A_B_INPUTS == 1 && C_MULT_TYPE < 3) + begin + if (C_HAS_ND == 1 && ((C_HAS_Q == 1 && C_HAS_O == 0 && C_MULT_TYPE == 2) || real_latency > 0)) + begin + intA = regA; + intB = regB; + intA_SIGNED = regA_SIGNED; + end + else if (C_HAS_ND == 1) + begin + if (intACLR === 1'b1) + begin + intA = `aall0s; + intB = `ball0s; + intA_SIGNED = 0; + end + else if (intACLR === 1'bx) + begin + intA = `aallxs; + intB = `ballxs; + intA_SIGNED = 1'bx; + end + end + else // no ND + begin + intA = regA; + intB = regB; + intA_SIGNED = regA_SIGNED; + end + end + else if (C_MULT_TYPE >= 3 && C_REG_A_B_INPUTS == 1) + begin + if (C_HAS_ND == 1) + begin + if (intACLR === 1'b1) + begin + intA = `aall0s; + intA_SIGNED = 0; + end + else if (intACLR === 1'bx) + begin + intA = `aallxs; + intA_SIGNED = 1'bx; + end + end + else // no ND + begin + intA = regA; + intA_SIGNED = regA_SIGNED; + end + if (C_MULT_TYPE == 3 && real_latency == 0 && C_HAS_O == 1 && C_HAS_ND == 1) + begin + intB = regB_cased; + end + else if (C_HAS_LOADB == 1 && C_HAS_SWAPB == 0) + begin + intB = B_INPUT; + end + else + begin + intB = regB; + end + end + else //C_REG_A_B_INPUTS = 0 + begin + if (C_MULT_TYPE < 3 || real_latency == 0) + begin + intA = A_I; + intA_SIGNED = A_SIGNED; + end + else + begin + if (intACLR === 1'b1) + begin + intA = `aall0s; + intA_SIGNED = 0; + end + else if (intACLR === 1'bx) + begin + intA = `aallxs; + intA_SIGNED = 1'bx; + end + end + if (real_latency == 0 && C_MULT_TYPE == 3 + && C_HAS_ND == 1 && intND === 1'b1 && (intCE === 1'b1 || C_HAS_CE == 0)) + begin + intB = B_INPUT; + end + else if (~(C_MULT_TYPE == 3 && C_HAS_ND == 1)) + begin + intB = B_INPUT; + end + end + end + end + + //Also have to perform the input processing that occurs synchronously to the clock. + always@(posedge intCLK) + begin + if (C_BAAT == C_A_WIDTH) + begin + if (C_REG_A_B_INPUTS == 1 && C_MULT_TYPE < 3) + begin + if (C_HAS_ND == 1 && ~((C_HAS_Q == 1 && C_HAS_O == 0 && C_MULT_TYPE == 2) || real_latency > 0)) //C_MULT_TYPE == 2 is Change 51101a. + begin + if (last_clk !== intCLK && intCLK === 1'b1 && last_clk === 1'b0 && intACLR === 1'b0) + begin + if (intSCLR === 1'b1 && (intCE === 1'b1 || C_SYNC_ENABLE == 0)) + begin + intA <= `aall0s; + intB <= `ball0s; + intA_SIGNED <= 0; + end + else if (intSCLR === 1'bx && (intCE === 1'b1 || C_SYNC_ENABLE == 0)) + begin + intA <= `aallxs; + intB <= `ballxs; + intA_SIGNED <= 1'bx; + end + else if (intSCLR === 1'b1 && (intCE === 1'bx && C_SYNC_ENABLE == 1)) + begin + intA <= `aallxs; + intB <= `ballxs; + intA_SIGNED <= 1'bx; + end + else if (ND_I === 1'b1 && intCE === 1'b1) + begin + intA <= A_I; + intB <= B_INPUT; + intA_SIGNED <= A_SIGNED; + end + else if (ND_I === 1'bx || intCE === 1'bx) + begin + intA <= `aallxs; + intB <= `ballxs; + intA_SIGNED <= 1'bx; + end + end + end + end + else if (C_MULT_TYPE >= 3 && C_REG_A_B_INPUTS == 1) + begin + if (C_HAS_ND == 1) + begin + if (last_clk !== intCLK && intCLK === 1'b1 && last_clk === 1'b0 && intACLR === 1'b0) + begin + if (intSCLR === 1'b1 && (intCE === 1'b1 || C_SYNC_ENABLE == 0)) + begin + intA <= `aall0s; + intA_SIGNED <= 0; + end + else if (intSCLR === 1'bx && (intCE === 1'b1 || C_SYNC_ENABLE == 0)) + begin + intA <= `aallxs; + intA_SIGNED <= 1'bx; + end + else if (intSCLR === 1'b1 && (intCE === 1'bx && C_SYNC_ENABLE == 1)) + begin + intA <= `aallxs; + intA_SIGNED <= 1'bx; + end + else if (intND === 1'b1 && intCE === 1'b1) + begin + intA <= A_I; + intA_SIGNED <= A_SIGNED; + end + else if (intND === 1'bx || intCE === 1'bx) + begin + intA <= `aallxs; + intA_SIGNED <= 1'bx; + end + end + end + end + else // C_REG_A_B_INPUTS = 0 + begin + if (last_clk !== intCLK && intCLK === 1'b1 && last_clk === 1'b0 && intACLR === 1'b0) // && ~(C_MULT_TYPE < 3 || C_LATENCY == 0)) + begin + if (C_MULT_TYPE == 3 && C_HAS_ND == 1) + begin + //if (intSCLR === 1'b1 && (intCE === 1'b1 || C_SYNC_ENABLE == 0)) + //begin + // intB = `ball0s; + //end + //else if (intLOAD_DONE === 1'b0 || (intND === 1'b1 && (intCE === 1'b1 || C_HAS_CE == 0))) + if (intLOAD_DONE === 1'b0 || (intND === 1'b1 && (intCE === 1'b1 || C_HAS_CE == 0))) + begin + intB = B_INPUT; + end + end + if (~(C_MULT_TYPE < 3 || C_LATENCY == 0)) + begin + if (intSCLR === 1'b1 && (intCE === 1'b1 || C_SYNC_ENABLE == 0)) + begin + intA <= `aall0s; + intA_SIGNED <= 0; + end + else if (intSCLR === 1'bx && (intCE === 1'b1 || C_SYNC_ENABLE == 0)) + begin + intA <= `aallxs; + intA_SIGNED <= 1'bx; + end + else if (intSCLR === 1'b1 && (intCE === 1'bx && C_SYNC_ENABLE == 1)) + begin + intA <= `aallxs; + intA_SIGNED <= 1'bx; + end + else if (intCE === 1'b1 && ((intND === 1'b1 && C_HAS_ND == 1) || C_HAS_ND == 0)) + begin + intA <= A_I; + intA_SIGNED <= A_SIGNED; + end + else if ((intCE === 1'bx || (intND === 1'bx && C_HAS_ND == 1)) || (intCE === 1'bx && C_HAS_ND == 0)) + begin + intA <= `aallxs; + intA_SIGNED <= 1'bx; + end + end + end + else if (((last_clk !== intCLK && intCLK === 1'bx && last_clk === 1'b0) || + (last_clk !== intCLK && intCLK === 1'b1 && last_clk === 1'bx)) && + (intACLR === 1'b0 && ~(C_MULT_TYPE < 3 || C_LATENCY == 0))) + begin + if ((intCE !== 1'b0 || C_SYNC_ENABLE == 0) && intSCLR !== 1'b0) + begin + intA <= `aallxs; + intA_SIGNED <= 1'bx; + end + else if (intCE !== 1'b0 && intSCLR !== 1'b1) + begin + intA <= `aallxs; + intA_SIGNED <= 1'bx; + end + else if (intCE !== 1'b0 || C_SYNC_ENABLE == 0) + begin + intA <= `aallxs; + intA_SIGNED <= 1'bx; + end + end + end + end + end + + // Now do the actual multiplication. + always@(intA or intB or intA_SIGNED or loadb_count or loadb_count_dly_int) + begin + if (C_BAAT == C_A_WIDTH) + begin + //Sign extend the A input. + if ((C_A_TYPE == `c_signed && C_HAS_A_SIGNED == 0) || (C_HAS_A_SIGNED == 1 && intA_SIGNED === 1'b1)) + begin + for(j = multWidth-1; j >= C_A_WIDTH; j = j - 1) + begin + //tmpA[j] = intA[C_A_WIDTH-1]; + tmpA[j] = intA[ncelab_inta_high-1]; + end + end + else if(C_HAS_A_SIGNED == 1 && intA_SIGNED === 1'bx) + begin + for(j = multWidth-1; j >= C_A_WIDTH; j = j - 1) + begin + tmpA[j] = 1'bx; + end + end + else if((C_A_TYPE == `c_unsigned && C_HAS_A_SIGNED == 0) || (C_HAS_A_SIGNED == 1 && intA_SIGNED == 0)) + begin + for(j = multWidth-1; j >= C_A_WIDTH; j = j - 1) + begin + tmpA[j] = 0; + end + end + tmpA[C_A_WIDTH-1 : 0] = intA; + tmpA_SIGNED = intA_SIGNED ; + + //Sign extend the B input. + if (C_B_TYPE == `c_signed) + begin + for(j = multWidth-1; j >= 0; j = j - 1) + begin + if (j >= b_width) + tmpB[j] = intB[b_width-1]; + else + tmpB[j] = intB[j] ; + end + end + else if(C_B_TYPE == `c_unsigned) + begin + for(j = multWidth-1; j >= 0; j = j - 1) + begin + if (j >= b_width) + tmpB[j] = 0; + else + tmpB[j] = intB[j] ; + end + end + if (C_HAS_LOADB == 1 && C_HAS_SWAPB == 0 && real_latency == 0 && loadb_count != -1 && loaded == 1) + begin + for (i = 0; i < multWidth; i = i + 1) + begin + tmpAB[i] = 1'bx ; + end + end + else if (C_HAS_LOADB == 1 && C_HAS_SWAPB == 0 && real_latency != 0 && (loadb_count != -1 || loadb_count_dly_int != -1) && loaded == 1) + begin + for (i = 0; i < multWidth; i = i + 1) + begin + tmpAB[i] = 1'bx ; + end + end + else if (is_X(tmpA) || is_X(tmpB)) + begin + tmpAB = `mallUKs; + end + else + begin + tmpAB = tmpA * tmpB; + end + end + end + + // Add intRDY_rl. The ready for the reloadable multiplier. + always@(intACLR) + begin + if (intACLR === 1'b1) + begin + intRDY_rl = 0; + end + else if (intACLR === 1'bx && intRDY_rl !== 1'b0) + begin + intRDY_rl = 1'bx; + end + end + + always@(posedge intCLK) + begin + if (last_clk !== intCLK && intCLK === 1'b1 && last_clk === 1'b0 && + (intACLR === 1'b0 || (intACLR === 1'bx && intRDY_rl === 1'b0))) + begin + if (intSCLR === 1'b1 && (intCE === 1'b1 || C_SYNC_ENABLE == 0)) + begin + intRDY_rl <= 0; + end + else if (intSCLR === 1'bx && (intCE === 1'b1 || C_SYNC_ENABLE == 0)) + begin + if (intRDY_rl_pre_reg !== 1'b0) + intRDY_rl <= 1'bx; + else + intRDY_rl <= 1'b0; + end + else if (intSCLR === 1'b1 && (intCE === 1'bx && C_SYNC_ENABLE == 1)) + begin + if (intRDY_rl !== 1'b0) + intRDY_rl <= 1'bx; + else + intRDY_rl <= 1'b0; + end + else if (intCE === 1'b1) + begin + intRDY_rl <= intRDY_rl_pre_reg; + end + else if (intCE === 1'bx && intRDY_rl !== intRDY_rl_pre_reg) + begin + intRDY_rl <= 1'bx; + end + end + else if (((last_clk !== intCLK && intCLK === 1'bx && last_clk === 1'b0) || + (last_clk !== intCLK && intCLK === 1'b1 && last_clk === 1'bx)) && + (intACLR === 1'b0 || (intACLR === 1'bx && intRDY_rl === 1'b0))) + begin + if ((intCE !== 1'b0 || C_SYNC_ENABLE == 0) && intSCLR !== 1'b0) + begin + intRDY_rl <= 1'bx; + end + else if (intCE !== 1'b0 && intSCLR !== 1'b1 && intRDY_rl !== intRDY_rl_pre_reg) + begin + intRDY_rl <= 1'bx; + end + else if ((intCE !== 1'b0 || C_SYNC_ENABLE == 0) && intRDY_rl !== 1'b0) + begin + intRDY_rl <= 1'bx; + end + end + end + + //The rccm can have undefined outputs after an ACLR. The cleared signal helps us model + //this. + always@(intACLR) + begin + if (intACLR === 1'b0) + cleared = 0; + end + + always@(posedge intCLK) + begin + if (last_clk != intCLK && intCLK === 1'b1 && last_clk === 1'b0 && intACLR === 1'b1 && intCE === 1'b1) + cleared <= 1; + end + + //Model the pipeline for the non sequential multiplier. + //Firstly do the asynchronous stuff. + always@(tmpAB or intACLR or loadb_count or loadb_count_no_predelay) + begin + if (C_BAAT == C_A_WIDTH) + begin + //if ((loadb_count != -1 || loadb_count_no_predelay != -1) && C_HAS_SWAPB == 0) + //if (loadb_count == -2 && C_MULT_TYPE == 3) + //begin + // intO = `allUKs; + //end + //else if (C_MULT_TYPE > 2 && real_latency > 0 && C_REG_A_B_INPUTS == 0) + if (C_MULT_TYPE > 2 && real_latency > 0 && C_REG_A_B_INPUTS == 0) + begin + intO = mult_convert(tmpAB); + end + else if (C_REG_A_B_INPUTS == 1) + begin + if (C_HAS_Q == 0 && real_latency == 0) + begin + intO = mult_convert(tmpAB); + end + else // Some registers after the input stage. + begin + if (intACLR === 1'b1 && (C_MULT_TYPE < 2 || C_MEM_TYPE == 0 || b_is_one == 1)) + begin + intO = `all0s; + end + else if (intACLR === 1'bx && (C_MULT_TYPE < 2 || C_MEM_TYPE == 0 || b_is_one == 1)) + begin + intO = `allUKs; + end + end + end + else //C_REG_A_B_INPUTS = 0 + begin + if (real_latency == 0 && C_HAS_Q == 0) + begin + intO = mult_convert(tmpAB); + end + else if (C_HAS_ND == 0 && ~(C_MULT_TYPE == 2 && real_latency >= 1 && C_MEM_TYPE == 2)) + // No ACLR for the block memory. + begin + if (~(C_MULT_TYPE >= 2 && C_MEM_TYPE == 2 && b_is_one == 0)) + begin + if (intACLR === 1'b1) + begin + intO = `all0s; + end + else if (intACLR === 1'bx) + begin + intO = `allUKs; + end + end + end + else if (C_HAS_ND == 1 && (C_MULT_TYPE < 2 && ~(real_latency == 1 && C_HAS_O == 1)) + && ~(C_MULT_TYPE == 2 && real_latency >= 1 && C_MEM_TYPE == 2)) + begin + if (intACLR === 1'b1) + begin + intO = `all0s; + end + else if (intACLR === 1'bx) + begin + intO = `allUKs; + end + end + else if (~(C_MULT_TYPE == 2 && real_latency >= 1 && C_MEM_TYPE == 2)) //C_HAS_ND = 1 + begin + if (intACLR == 1'b1 && (C_MULT_TYPE < 2 || C_MEM_TYPE == 0 || b_is_one == 1)) + begin + intO = `all0s; + end + else if (intACLR === 1'bx) + begin + intO = `allUKs; + end + end + end + // Clear intO whenever we clear sub_product(0) in the vhdl. + if ((intACLR === 1'b1)) + begin + if (C_MEM_TYPE == 2 && C_MULT_TYPE > 2 && real_latency > 1) + begin + if (cleared == 0) + begin + for (j = 1; j <= real_latency; j = j + 1) + begin + intO = `allUKs; + end + end + end + end + end + end + + //Now change the intO output on the clock. + always@(posedge intCLK) + begin + if (C_BAAT == C_A_WIDTH) + begin + if (C_REG_A_B_INPUTS == 1) // && (~(loadb_count != -1 && C_HAS_SWAPB == 0))) + begin + if (~(C_HAS_Q == 0 && real_latency == 0)) + begin + if (last_clk !== intCLK && intCLK === 1'b1 && last_clk === 1'b0 && (intACLR === 1'b0 || (C_MULT_TYPE > 1 && C_MEM_TYPE == 2 && b_is_one == 0))) + begin + if (intSCLR === 1'b1 && (intCE === 1'b1 || C_SYNC_ENABLE == 0) && + ~(C_MULT_TYPE == 3 && loadb_count != -1)) + begin + intO <= `all0s; + end + else if (intSCLR === 1'bx && (intCE === 1'b1 || C_SYNC_ENABLE == 0)) + begin + intO <= `allUKs; + end + else if (intSCLR === 1'b1 && (intCE === 1'bx && C_SYNC_ENABLE == 1)) + begin + intO <= `allUKs; + end + // Ignore the ND in these cases. + else if ((C_MULT_TYPE < 2 && real_latency == 0) || + (C_HAS_SWAPB == 1 || C_HAS_ND == 0)) + begin + if (intCE === 1'b1) + begin + intO <= mult_convert(tmpAB); + end + else if (intCE === 1'bx) + begin + intO <= `allUKs; + end + end + // Otherwise wait for the ND to appear before clocking the + // result into the pipeline. + else if ((regND === 1'b1 || (C_MULT_TYPE == 3 && loadb_count != -1)) + && intCE === 1'b1) + begin + intO <= mult_convert(tmpAB); + end + else if (regND === 1'bx || intCE === 1'bx) + begin + intO <= `allUKs; + end + end + else if (((last_clk !== intCLK && intCLK === 1'bx && last_clk === 1'b0) || + (last_clk !== intCLK && intCLK === 1'b1 && last_clk === 1'bx)) && + (intACLR === 1'b0 || (C_MULT_TYPE > 1 && C_MEM_TYPE == 2 && b_is_one == 0))) + begin + if ((intCE !== 1'b0 || C_SYNC_ENABLE == 0) && intSCLR !== 1'b0) + begin + intO <= `allUKs; + end + else if (intCE !== 1'b0 && intSCLR !== 1'b1) + begin + intO <= `allUKs; + end + else if (intCE !== 1'b0 || C_SYNC_ENABLE == 0) + begin + intO <= `allUKs; + end + end + end + end + //else if ((~(loadb_count != -1 && C_HAS_SWAPB == 0)) && + // (~(C_MULT_TYPE > 2 && real_latency > 0 && C_REG_A_B_INPUTS == 0))) + else if (C_MULT_TYPE > 2 && real_latency > 0 && C_REG_A_B_INPUTS == 0) + begin + intO = mult_convert(tmpAB); + end + else if (~(C_MULT_TYPE > 2 && real_latency > 0 && C_REG_A_B_INPUTS == 0)) + begin + //C_REG_A_B_INPUTS = 0 + if ((~(real_latency == 0 && C_HAS_Q == 0)) && C_HAS_ND == 0) + begin + if (last_clk !== intCLK && last_clk === 1'b0 && intCLK === 1'b1 && (intACLR === 1'b0 || (C_MULT_TYPE > 1 && C_MEM_TYPE == 2 && b_is_one == 0))) + begin + if ((intSCLR === 1'b1 && (intCE === 1'b1 || C_SYNC_ENABLE == 0)) + && ~(C_MULT_TYPE == 3 && loadb_count != -1)) + begin + intO <= `all0s; + end + else if (intSCLR === 1'bx && (intCE === 1'b1 || C_SYNC_ENABLE == 0)) + begin + intO <= `allUKs; + end + else if (intSCLR === 1'b1 && (intCE === 1'bx && C_SYNC_ENABLE == 1)) + begin + intO <= `allUKs; + end + else if (intCE === 1'b1) + begin + intO <= mult_convert(tmpAB); + end + else if (intCE === 1'bx) + begin + intO <= `allUKs; + end + end + else if (((last_clk !== intCLK && intCLK === 1'bx && last_clk === 1'b0) || + (last_clk !== intCLK && intCLK === 1'b1 && last_clk === 1'bx)) && + (intACLR === 1'b0 || (C_MULT_TYPE > 1 && C_MEM_TYPE == 2 && b_is_one == 0))) + begin + if ((intCE !== 1'b0 || C_SYNC_ENABLE == 0) && intSCLR !== 1'b0) + begin + intO <= `allUKs; + end + else if (intCE !== 1'b0 && intSCLR !== 1'b1) + begin + intO <= `allUKs; + end + else if (intCE !== 1'b0 || C_SYNC_ENABLE == 0) + begin + intO <= `allUKs; + end + end + end + else if ((~(real_latency == 0 && C_HAS_Q == 0)) + && (C_HAS_ND == 1 && C_MULT_TYPE < 2 && ~(real_latency == 1 && C_HAS_O == 1))) + begin + if (last_clk !== intCLK && last_clk === 1'b0 && intCLK === 1'b1 && (intACLR === 1'b0 || (C_MULT_TYPE > 1 && C_MEM_TYPE == 2 && b_is_one == 0))) + begin + if ((intSCLR === 1'b1 && (intCE === 1'b1 || C_SYNC_ENABLE == 0)) + && ~(C_MULT_TYPE == 3 && loadb_count != -1)) + begin + intO <= `all0s; + end + else if (intSCLR === 1'bx && (intCE === 1'b1 || C_SYNC_ENABLE == 0)) + begin + intO <= `allUKs; + end + else if (intSCLR === 1'b1 && (intCE === 1'bx && C_SYNC_ENABLE == 1)) + begin + intO <= `allUKs; + end + else if ((intCE === 1'b1 && real_latency == 0 && C_HAS_Q == 1 && intND === 1'b1) + || (intCE === 1'b1 && ~(real_latency == 0 && C_HAS_Q == 1))) + begin + intO <= mult_convert(tmpAB); + end + else if (intCE === 1'bx) + begin + intO <= `allUKs; + end + end + else if (((last_clk !== intCLK && intCLK === 1'bx && last_clk === 1'b0) || + (last_clk !== intCLK && intCLK === 1'b1 && last_clk === 1'bx)) && + (intACLR === 1'b0 || (C_MULT_TYPE > 1 && C_MEM_TYPE == 2 && b_is_one == 0))) + begin + if ((intCE !== 1'b0 || C_SYNC_ENABLE == 0) && intSCLR !== 1'b0) + begin + intO <= `allUKs; + end + else if (intCE !== 1'b0 && intSCLR !== 1'b1) + begin + intO <= `allUKs; + end + else if (intCE !== 1'b0 || C_SYNC_ENABLE == 0) + begin + intO <= `allUKs; + end + end + end + else if (~(real_latency == 0 && C_HAS_Q == 0)) //C_HAS_ND = 1 + begin + if (real_latency == 0) + begin + if (last_clk !== intCLK && last_clk === 1'b0 && intCLK === 1'b1 && (intACLR === 1'b0 || (C_MULT_TYPE > 1 && C_MEM_TYPE == 2 && b_is_one == 0))) + begin + if ((intSCLR === 1'b1 && (intCE === 1'b1 || C_SYNC_ENABLE == 0)) + && ~(C_MULT_TYPE == 3 && loadb_count != -1)) + begin + intO <= `all0s; + end + else if (intSCLR === 1'bx && (intCE === 1'b1 || C_SYNC_ENABLE == 0)) + begin + intO <= `allUKs; + end + else if (intSCLR === 1'b1 && (intCE === 1'bx && C_SYNC_ENABLE == 1)) + begin + intO <= `allUKs; + end + else if ((ND_I === 1'b1 || (C_MULT_TYPE == 3 && loadb_count != -1)) + && intCE === 1'b1) + begin + intO <= mult_convert(tmpAB); + end + else if (ND_I === 1'bx || intCE === 1'bx) + begin + intO <= `allUKs; + end + end + else if (((last_clk !== intCLK && intCLK === 1'bx && last_clk === 1'b0) || + (last_clk !== intCLK && intCLK === 1'b1 && last_clk === 1'bx)) && + (intACLR === 1'b0 || (C_MULT_TYPE > 1 && C_MEM_TYPE == 2 && b_is_one == 0))) + begin + if ((intCE !== 1'b0 || C_SYNC_ENABLE == 0) && intSCLR !== 1'b0) + begin + intO <= `allUKs; + end + else if (intCE !== 1'b0 && intSCLR !== 1'b1) + begin + intO <= `allUKs; + end + else if (intCE !== 1'b0 || C_SYNC_ENABLE == 0) + begin + intO <= `allUKs; + end + end + end + else //latency > 0 + begin + if (last_clk !== intCLK && last_clk === 1'b0 && intCLK === 1'b1 && (intACLR === 1'b0 || (C_MULT_TYPE > 1 && C_MEM_TYPE == 2 && b_is_one == 0))) + begin + if ((intSCLR === 1'b1 && (intCE === 1'b1 || C_SYNC_ENABLE == 0)) + && ~(C_MULT_TYPE == 3 && loadb_count != -1)) + begin + intO <= `all0s; + end + else if (intSCLR === 1'bx && (intCE === 1'b1 || C_SYNC_ENABLE == 0)) + begin + intO <= `allUKs; + end + else if (intSCLR === 1'b1 && (intCE === 1'bx && C_SYNC_ENABLE == 1)) + begin + intO <= `allUKs; + end + else if (intCE === 1'b1 && ((ND_I === 1'b1 + || (C_MULT_TYPE == 3 && loadb_count != -1)) + || intSWAPB === 1'b1)) + begin + intO <= mult_convert(tmpAB); + end + else if (intCE === 1'bx || (ND_I === 1'bx && intSWAPB !== 1'b0) + || (ND_I !== 1'b0 && intSWAPB === 1'bx)) + begin + intO <= `allUKs; + end + end + else if (((last_clk !== intCLK && intCLK === 1'bx && last_clk === 1'b0) || + (last_clk !== intCLK && intCLK === 1'b1 && last_clk === 1'bx)) && + (intACLR === 1'b0 || (C_MULT_TYPE > 1 && C_MEM_TYPE == 2 && b_is_one == 0))) + begin + if ((intCE !== 1'b0 || C_SYNC_ENABLE == 0) && intSCLR !== 1'b0) + begin + intO <= `allUKs; + end + else if (intCE !== 1'b0 && intSCLR !== 1'b1) + begin + intO <= `allUKs; + end + else if (intCE !== 1'b0 || C_SYNC_ENABLE == 0) + begin + intO <= `allUKs; + end + end + end + end + end + // Clear intO when we clear intQpipe[0]. + //if ((last_clk !== intCLK && last_clk === 1'b0 && intCLK === 1'b1) && + // (~(loadb_count != -1 && C_HAS_SWAPB == 0))) + if (last_clk !== intCLK && last_clk === 1'b0 && intCLK === 1'b1) + begin + if (intACLR == 1'b1) + begin + if (C_MEM_TYPE == 2 && C_MULT_TYPE > 2 && (real_latency > 1 || (C_MULT_TYPE == 3 && C_MEM_TYPE == 2 && real_latency == 1))) + begin + if (cleared == 0) + begin + intO = `allUKs; + end + end + end + else if ((intSCLR === 1'b1 && (intCE === 1'b1 || C_SYNC_ENABLE == 0)) + && ~(C_MULT_TYPE == 3 && loadb_count != -1)) + begin + if (loadb_count == -1 && (C_MEM_TYPE == 0 || C_MULT_TYPE < 2 || C_SYNC_ENABLE == 1 || intCE === 1'b1)) + begin + intO <= `all0s; + end + end + else if (intSCLR === 1'b1 && (intCE === 1'bx || C_SYNC_ENABLE == 0)) + begin + intO <= `allUKs; + end + else if (intSCLR === 1'bx && (intCE === 1'b1 || C_SYNC_ENABLE == 0)) + begin + intO <= `allUKs; + end + end + else if (((last_clk !== intCLK && intCLK === 1'bx && last_clk === 1'b0) || + (last_clk !== intCLK && intCLK === 1'b1 && last_clk === 1'bx)) && + (intACLR === 1'b0 || (C_MEM_TYPE == 2 && C_MULT_TYPE > 2 && real_latency > 1 && intCE === 1'b1))) + begin + if ((intCE !== 1'b0 || C_SYNC_ENABLE == 0) && intSCLR !== 1'b0) + begin + intO <= `allUKs; + end + else if (intCE !== 1'b0 && intSCLR !== 1'b1) + begin + intO <= `allUKs; + end + else if (intCE !== 1'b0 || C_SYNC_ENABLE == 0) + begin + intO <= `allUKs; + end + end + end + end + + //Load intO into the pipeline + always@(intACLR or intO) + begin + if ((intSCLR === 1'b1 && loadb_count == -1 && (intCE === 1'b1 || C_SYNC_ENABLE == 0)) && + (C_MEM_TYPE == 0 || C_MULT_TYPE < 2 || C_SYNC_ENABLE == 1 || intCE === 1'b1) && + (last_clk !== intCLK && last_clk === 1'b0 && intCLK === 1'b1 && + (intACLR === 1'b0 || (C_MEM_TYPE == 2 && C_MULT_TYPE > 2 + && (real_latency > 1 || (C_MEM_TYPE == 2 && C_MULT_TYPE == 3 && real_latency == 1)) && intCE === 1'b1)))) + begin + intQpipe[0] = `all0s; + end + else if ((intACLR === 1'b1 && C_MEM_TYPE == 2 && C_MULT_TYPE > 2 && (real_latency > 1 || (C_MULT_TYPE == 3 && C_MEM_TYPE == 2 && real_latency == 1)) + && intCE === 1'b1) && + (last_clk !== intCLK && last_clk === 1'b0 && intCLK === 1'b1)) + begin + intQpipe[0] = `all0s; + end + else + begin + intQpipe[0] = intO; + end + end + + //Load the pipleine. + always@(posedge intCLK) + begin + if (last_clk !== intCLK && last_clk === 1'b0 && intCLK === 1'b1 && intSCLR === 1'b0 && intACLR === 1'b0) + intQpipe[0] <= intO; + end + + //This process clears the pipeline for the non-sequential multiplier. + always@(intACLR) + begin + if (C_BAAT == C_A_WIDTH) + begin + if (intACLR === 1'b1) + begin + if (C_MEM_TYPE == 2 && C_MULT_TYPE > 2 && (real_latency > 1 || (C_MULT_TYPE == 3 && C_MEM_TYPE == 2 && real_latency == 1))) + begin + if (cleared == 0) + begin + for (j = 1; j <= real_latency; j = j + 1) + begin + intQpipe[j] = `allUKs; + end + end + end + else if (real_latency > 0 && (C_MULT_TYPE < 3 || C_MEM_TYPE == 0)) + begin + for (j = 1; j <= real_latency; j = j + 1) + begin + intQpipe[j] = `all0s; + end + end + end + else if (intACLR === 1'bx) + begin + if (C_MEM_TYPE == 2 && C_MULT_TYPE > 2 && real_latency > 1) + begin + if (cleared == 0) + begin + for (j = 1; j <= real_latency; j = j + 1) + begin + intQpipe[j] = `allUKs; + end + end + end + else if (real_latency > 0) + begin + for (j = 1; j <= real_latency; j = j + 1) + begin + intQpipe[j] = `allUKs; + end + end + end + end + end + + //This process updates the pipeline for the non-sequential multiplier. + always@(posedge intCLK) + begin + if (C_BAAT == C_A_WIDTH) + begin + if (last_clk !== intCLK && last_clk === 1'b0 && intCLK === 1'b1 ) + begin + if (intACLR == 1'b1 && C_MEM_TYPE == 2 && C_MULT_TYPE > 2 + && (real_latency > 1 || (C_MULT_TYPE == 3 && C_MEM_TYPE == 2 && real_latency == 1)) + && intCE === 1'b1) + begin + if (cleared == 0) + begin + intQpipe[real_latency] = `all0s; + end + end + else if ((intACLR === 1'b0)) + begin + if ((intSCLR === 1'b1 && (intCE === 1'b1 || C_SYNC_ENABLE == 0)) + && ~(C_MULT_TYPE == 3 && loadb_count != -1)) + begin + if (C_MEM_TYPE == 0 || C_MULT_TYPE < 2 || C_SYNC_ENABLE == 1 || intCE === 1'b1) + begin + if (C_MULT_TYPE > 2 && C_MEM_TYPE == 2 && C_HAS_LOADB == 1 && C_HAS_SWAPB == 0 && real_latency > 1 && loadb_count != -1) + begin + for(j = real_latency-1; j <= real_latency; j = j + 1) + begin + intQpipe[j] <= `all0s; + end + end + else if (real_latency >= 1) + begin + for(j = 1; j <= real_latency; j = j + 1) + begin + intQpipe[j] <= `all0s; + end + end + end + else if (real_latency > 0) + begin + if (C_MULT_TYPE > 2 && C_MEM_TYPE == 2 && C_HAS_LOADB == 1 && C_HAS_SWAPB == 0 && real_latency > 1 && loadb_count != - 1) + begin + for(j = real_latency-1; j <= real_latency; j = j + 1) + begin + intQpipe[j] <= `all0s; + end + end + else + begin + for(j = 1; j <= real_latency; j = j + 1) + begin + intQpipe[j] <= `all0s; + end + end + end + end + else if (intSCLR === 1'b1 && (intCE === 1'bx || C_SYNC_ENABLE == 0)) + begin + for(j = 0; j <= real_latency; j = j + 1) + begin + intQpipe[j] <= `allUKs; + end + end + else if (intSCLR === 1'bx && (intCE === 1'b1 || C_SYNC_ENABLE == 0)) + begin + for(j = 0; j <= real_latency; j = j + 1) + begin + intQpipe[j] <= `allUKs; + end + end + else if (intCE === 1'b1) + begin + if (C_REG_A_B_INPUTS == 1 || C_HAS_ND == 0 || + (C_MULT_TYPE > 1 || (C_MULT_TYPE < 2 && real_latency == 1 && C_HAS_O == 1)) || + C_PIPELINE == 0) + begin + for(j = real_latency; j >= 1; j = j - 1) + begin + intQpipe[j] <= intQpipe[j-1]; + end + end + else + begin + if (real_latency > 1) + begin + for(j = real_latency; j >= 2; j = j - 1) + begin + intQpipe[j] <= intQpipe[j-1]; + end + end + if (real_latency > 0) + begin + if (regND_nonseq === 1'b1) + intQpipe[1] <= intQpipe[0]; + else if (regND_nonseq === 1'bx) + intQpipe[1] <= `allUKs; + end + end + end + else if (intCE === 1'bx) + begin + if (C_REG_A_B_INPUTS == 1 || C_HAS_ND == 0 || + (C_MULT_TYPE > 1 || (C_MULT_TYPE < 2 && real_latency == 1 && C_HAS_O == 1)) || + C_PIPELINE == 0) + begin + for(j = real_latency; j >= 1; j = j - 1) + begin + intQpipe[j] <= `allUKs; + end + end + else + begin + if (real_latency > 0) + begin + for(j = real_latency; j >= 0; j = j - 1) + begin + intQpipe[j] <= `allUKs; + end + end + end + end + end + end + else if (((last_clk !== intCLK && intCLK === 1'bx && last_clk === 1'b0) || + (last_clk !== intCLK && intCLK === 1'b1 && last_clk === 1'bx)) && + (intACLR === 1'b0 || (C_MEM_TYPE == 2 && C_MULT_TYPE > 2 && real_latency > 1 + && intCE === 1'b1))) + begin + if ((intCE !== 1'b0 || C_SYNC_ENABLE == 0) && intSCLR !== 1'b0) + begin + for(j = real_latency; j >= 0; j = j - 1) + begin + intQpipe[j] <= `allUKs; + end + end + else if (intCE !== 1'b0 && intSCLR !== 1'b1) + begin + for(j = real_latency; j >= 0; j = j - 1) + begin + intQpipe[j] <= `allUKs; + end + end + else if (intCE !== 1'b0 || C_SYNC_ENABLE == 0) + begin + for(j = real_latency; j >= 0; j = j - 1) + begin + intQpipe[j] <= `allUKs; + end + end + end + end + end + + //Model the ready output pipeline. First do the asynchronous updates. + always@(intACLR or intRDY) + begin + if (C_BAAT == C_A_WIDTH) + begin + if (intACLR === 1'b0 || intACLR === 1'bx || real_latency == 0) + begin + intRDYpipe[0] = intRDY; + end + else if (intACLR === 1'b1) + begin + for(j = 0; j <= real_latency; j = j + 1) + begin + intRDYpipe[j] = 0; + end + end + else if (intACLR === 1'bx) + begin + for(j = 0; j <= real_latency; j = j + 1) + begin + if (intRDYpipe[j] !== 1'b0) + begin + intRDYpipe[j] = 1'bx; + end + end + end + end + end + + //Model the synchronous part of the ready pipeline. + always@(posedge intCLK) + begin + if (C_BAAT == C_A_WIDTH) + begin + if (last_clk !== intCLK && last_clk === 1'b0 && intCLK === 1'b1 && intACLR !== 1'b1) + begin + if (intSCLR === 1'b1 && (intCE === 1'b1 || C_SYNC_ENABLE == 0)) + begin + for(j = real_latency; j >= 0; j = j - 1) + begin + intRDYpipe[j] <= 0; + end + end + else if (intSCLR === 1'bx && (intCE === 1'b1 || C_SYNC_ENABLE == 0)) + begin + for(j = real_latency; j >= 1; j = j - 1) + begin + if (intRDYpipe[j-1] !== 1'b0) + begin + intRDYpipe[j] <= 1'bx; + end + else + begin + intRDYpipe[j] <= 1'b0; + end + end + end + else if (intSCLR === 1'b1 && (intCE === 1'bx && C_SYNC_ENABLE == 1)) + begin + for(j = real_latency; j >= 0; j = j - 1) + begin + if (intRDYpipe[j] !== 1'b0) + intRDYpipe[j] <= 1'bx; + else + intRDYpipe[j] <= 1'b0; + end + end + else if (intCE === 1'b1 && intACLR === 1'b0) + begin + for(j = real_latency; j >= 1; j = j - 1) + begin + intRDYpipe[j] <= intRDYpipe[j-1]; + end + end + else if (intCE === 1'b1 && intACLR === 1'bx) + begin + for(j = real_latency; j >= 1; j = j - 1) + begin + if (intRDYpipe[j-1] === 1'b0) + intRDYpipe[j] <= intRDYpipe[j-1]; + else + intRDYpipe[j] <= 1'bx; + end + end + else if (intCE === 1'bx) + begin + for(j = real_latency; j >= 1; j = j - 1) + begin + if (intRDYpipe[j] !== intRDYpipe[j-1]) + begin + intRDYpipe[j] <= 1'bx; + end + end + end + end + else if (((last_clk !== intCLK && intCLK === 1'bx && last_clk === 1'b0) || + (last_clk !== intCLK && intCLK === 1'b1 && last_clk === 1'bx)) && + (intACLR !== 1'b1)) + begin + if ((intCE !== 1'b0 || C_SYNC_ENABLE == 0) && intSCLR !== 1'b0) + begin + for(j = real_latency; j >= 1; j = j - 1) + begin + intRDYpipe[j] <= 1'bx; + end + end + else if (intCE !== 1'b0 && intSCLR !== 1'b1) + begin + for(j = real_latency; j >= 1; j = j - 1) + begin + if (intRDYpipe[j] !== intRDYpipe[j-1]) + intRDYpipe[j] <= 1'bx; + end + end + else if (intCE !== 1'b0 || C_SYNC_ENABLE == 0) + begin + for(j = real_latency; j >= 1; j = j - 1) + begin + if (intRDYpipe[j] !== 1'b0) + intQpipe[j] <= 1'bx; + end + end + end + end + end + + //Now drive the internal versions of the O, Q and RDY outputs. + //Again do the asynchronous updates first. + always@(intO or tmpAB or intQpipe[real_latency] or intQpipe[0] or intQpipe[real_latency-1] or intRDYpipe or intACLR or intSCLR or intCE or intCLK or ND_I) + begin + if (C_BAAT == C_A_WIDTH) + begin + if (real_latency == 0) + begin + // Assign O Output. + O_I = mult_convert(tmpAB); + // Assign Q Output. + if (b_is_zero == 1) + begin + Q_I = `all0s; + end + else if (C_MEM_TYPE == 0 || C_MULT_TYPE < 2) + begin + if (intACLR === 1'b1) + Q_I = `all0s; + else if (intACLR === 1'bx) + Q_I = `allUKs; + else + Q_I = intQpipe[0]; + end + else + begin + Q_I = intQpipe[0]; + end + + // Assign RDY Output. + if (C_HAS_ND == 1) + begin + if (b_is_zero == 1) + RDY_I = ND_I; + else + RDY_I = intRDYpipe[0]; + end + else + begin + RDY_I = 1; + end + + end + else + begin + if (C_MEM_TYPE == 2 && C_MULT_TYPE > 2 && real_latency > 2 && (C_PIPELINE == 0 || real_latency > 3)) + begin + if (intACLR === 1'b1) + begin + O_I = `all0s; + Q_I = `all0s; + end + else if (intACLR === 1'bx) + begin + O_I = `allUKs; + Q_I = `allUKs; + end + else + begin + O_I = intQpipe[real_latency-1]; + Q_I = intQpipe[real_latency]; + end + end + else if (C_MEM_TYPE == 2 && C_MULT_TYPE > 2 && (real_latency == 2 || (C_PIPELINE == 1 && real_latency > 1))) + begin + O_I = intQpipe[real_latency-1]; + if (intACLR === 1'b1) + begin + Q_I = `all0s; + end + else if (intACLR === 1'bx) + begin + Q_I = `allUKs; + end + else + begin + Q_I = intQpipe[real_latency]; + end + end + else + begin + O_I = intQpipe[real_latency-1]; + Q_I = intQpipe[real_latency]; + end + if (C_HAS_ND == 1) + if (C_REG_A_B_INPUTS == 1 || C_MULT_TYPE > 1 || C_PIPELINE == 0 || C_LATENCY < 1 || + (C_PIPELINE == 1 && C_HAS_ND == 1 && C_MULT_TYPE < 2 && real_latency == 1 && + C_REG_A_B_INPUTS == 0 && C_HAS_Q == 0)) + + RDY_I = intRDYpipe[real_latency]; + else + RDY_I = intRDYpipe[real_latency-1]; + else + RDY_I = 1; + end + end + end + + //Register the RFD and RDY signals. + //Asynchronous clear. + always@(intACLR) + begin + if (intACLR === 1'b1) + begin + if (b_is_zero == 0) + begin + regRFD = 0; + regRDY = 0; + end + else + begin + regRFD = 0; + end + end + else if (intACLR === 1'bx && regRDY !== 1'b0 && b_is_zero == 0) + begin + regRDY = 1'bx; + end + else if (intACLR === 1'bx && regRFD !== 1'b0) + begin + regRFD = 1'bx; + end + end + + always@(ND_I) + begin + if (b_is_zero == 1) + begin + regRDY = ND_I; + end + end + + //Synchronous clear and registered output. + always@(posedge intCLK) + begin + if (b_is_zero == 0 && last_clk !== intCLK && last_clk === 1'b0 && intCLK === 1'b1 && intACLR !== 1'b1) + begin + if (intSCLR === 1'b1 && (intCE === 1'b1 || C_SYNC_ENABLE == 0)) + begin + regRFD <= 0; + regRDY <= 0; + end + else if (intSCLR === 1'bx && (intCE === 1'b1 || C_SYNC_ENABLE == 0)) + begin + if (intRFD !== 1'b0) + regRFD <= 1'bx; + else + regRFD <= 1'b0; + if (RDY_I !== 1'b0) + regRDY <= 1'bx; + else + regRDY <= 1'b0; + end + else if (intSCLR === 1'b1 && (intCE === 1'bx && C_SYNC_ENABLE == 1)) + begin + if (regRFD !== 1'b0) + regRFD <= 1'bx; + else + regRFD <= 1'b0; + if (regRDY !== 1'b0) + regRDY <= 1'bx; + else + regRDY <= 1'b0; + end + else if (intCE === 1'b1 && intACLR === 1'b0) + begin + regRFD <= intRFD; + regRDY <= RDY_I; + end + else if (intCE === 1'b1 && intACLR === 1'bx) + begin + if (intRFD === 1'b0) + regRFD <= intRFD; + else + regRFD <= 1'bx; + if (RDY_I === 1'b0) + regRDY <= RDY_I; + else + regRDY <= 1'bx; + end + else if (intCE === 1'bx) + begin + if (regRFD !== intRFD) + regRFD <= 1'bx; + if (regRDY !== RDY_I) + regRDY <= 1'bx; + end + end + else if (((last_clk !== intCLK && intCLK === 1'bx && last_clk === 1'b0) || + (last_clk !== intCLK && intCLK === 1'b1 && last_clk === 1'bx)) && + (intACLR !== 1'b1)) + begin + if ((intCE !== 1'b0 || C_SYNC_ENABLE == 0) && intSCLR !== 1'b0) + begin + regRDY <= 1'bx; + regRFD <= 1'bx; + end + else if (intCE !== 1'b0 && intSCLR !== 1'b1) + begin + if (regRFD !== intRFD) + regRFD <= 1'bx; + if (regRDY !== RDY_I) + regRDY <= 1'bx; + end + else if (intCE !== 1'b0 || C_SYNC_ENABLE == 0) + begin + if (regRFD !== 1'b0) + regRFD <= 1'bx; + if (regRDY !== 1'b0) + regRDY <= 1'bx; + end + end + end + + //Model the reloading process for a reloadable constant coefficient multiplier. + //This is a synchronous process but we must deal with the asynchronous clear first. + always@(intACLR) + begin + if (C_HAS_LOADB == 1) + begin + if (intACLR === 1'b1) + begin + if (loadb_count != -1 && loadb_count != -2) // -1 = Load finished + begin + loadb_count = -2; // -2 = Load interrupted by clear. + loadb_count_no_predelay = -2; + end + intLOAD_DONE = 1; + intRFD_rel = 1; + end + else if (intACLR === 1'bx) + begin + if (loadb_count != -1 && loadb_count != -2) + begin + loadb_count = -3; // -3 = Undefined. + intLOAD_DONE = 1'bx; + if (C_HAS_SWAPB == 0) + intRFD_rel = 1'bx; + else + intRFD_rel = 1'b1; + end + end + end + end + + //Now do the synchronous update on the rising clock edge. + always@(posedge intCLK) + begin + if (last_clk !== intCLK && last_clk === 1'b0 && intCLK === 1'b1 && C_HAS_LOADB == 1 && intACLR !== 1'b1 && intLOADB === 1'bx && intCE !== 1'b0) + begin + loadb_count = -3; + if (C_HAS_SWAPB == 1 && bank_sel === 1'bx ) + begin + b_const0 <= `ballxs; + b_const1 <= `ballxs; + end + else if (C_HAS_SWAPB == 1 && bank_sel === 1'b0) + begin + b_const1 <= `ballxs; + end + else + begin + b_const0 <= `ballxs; + end + end + else if (last_clk !== intCLK && last_clk === 1'b0 && intCLK === 1'b1 && C_HAS_LOADB == 1 && intACLR === 1'b0) + begin + if (intSCLR === 1'b1 && (intCE === 1'b1 || C_SYNC_ENABLE == 0)) + begin + if (loadb_count != -1 && loadb_count != -2) + begin + loadb_count <= -2; + end + end + else if (intSCLR === 1'bx && (intCE === 1'b1 || C_SYNC_ENABLE == 0)) + begin + if (loadb_count != -1 && loadb_count != -2) + begin + loadb_count <= -2-sig_addr_bits; + end + end + else if (intCE === 1'b1) + begin + if (intLOADB === 1'b1) + begin + if (C_REG_A_B_INPUTS == 1 || C_HAS_A_SIGNED == 1 || C_A_TYPE == `c_signed) + begin + loadb_count <= loadb_delay+1+C_REG_A_B_INPUTS; + end + else + begin + loadb_count <= loadb_delay; + end + loadb_value <= B_I; + loaded <= 1; + end + else //loadb == 0. + begin + if (C_HAS_O == 1 && C_MULT_TYPE == 3 && C_HAS_SWAPB == 0 && + loadb_count == 2 && loadb_delay > 2 && C_HAS_ND == 1) + //Load early in this case. + begin + b_const0 <= loadb_value; + loadb_count <= loadb_count - 1; + end + else if (loadb_count > 0) + begin + loadb_count <= loadb_count - 1; + end + else if (loadb_count <= -3) //Undefined state + begin + if (loadb_count != -2-sig_addr_bits && C_REG_A_B_INPUTS == 0 && real_latency == 0) + // Wait for sig_addr_bits cycles before setting the op + // to undefined. + begin + loadb_count <= loadb_count - 1; + end + end + else if (loadb_count == 0) + begin + if (C_HAS_SWAPB == 1 && bank_sel === 1'b0) + b_const1 <= loadb_value; + else + b_const0 <= loadb_value; + //if (ND_I === 1'b1 || (C_HAS_SWAPB == 1 || C_HAS_ND == 0 || C_REG_A_B_INPUTS == 1)) + //begin + loadb_count <= -1; + //end + loaded <= 1; + end + else if (loadb_count == -2) //Load has been interrupted by a clear. + begin + if (C_HAS_SWAPB == 1 && bank_sel == 0) + b_const1 <= `ballxs; + else + b_const0 <= `ballxs; + loaded <= 1; + end + end + end + else if (intCE === 1'bx) + begin + if (loadb_count != -1 && loadb_count != -2 && (loadb_count != -2-sig_addr_bits && C_REG_A_B_INPUTS == 0 && real_latency == 0)) + begin + if (loadb_count > 0) + loadb_count <= -3; + else + loadb_count <= loadb_count-1; + end + else if (loadb_count == -2-sig_addr_bits || (loadb_count != -1 && loadb_count != -2 && (C_REG_A_B_INPUTS == 1 || real_latency > 0))) + // Propogate the 'X' through when the TC from the load engines + // counter goes to 'X' or if the inputs are registered. + begin + if (C_REG_A_B_INPUTS == 1 || real_latency > 0) + loadb_count <= -3; + end + end + end + end + + // The load done and RFD outputs don't depend on the C_PREDELAY parameter. + always@(posedge intCLK) + begin + if (last_clk !== intCLK && last_clk === 1'b0 && intCLK === 1'b1 && C_HAS_LOADB == 1 && intACLR !== 1'b1 && intLOADB_no_predelay === 1'bx && intCE !== 1'b0) + begin + loadb_count_no_predelay = -3; + intLOAD_DONE <= 1'bx; + if (C_HAS_SWAPB == 0) + intRFD_rel <= 1'bx; + else + intRFD_rel <= 1'b1; + end + else if (last_clk !== intCLK && last_clk === 1'b0 && intCLK === 1'b1 && C_HAS_LOADB == 1 && intACLR === 1'b0) + begin + if (intSCLR === 1'b1 && (intCE === 1'b1 || C_SYNC_ENABLE == 0)) + begin + intLOAD_DONE <= 1; + intRFD_rel <= 1; + if (loadb_count != -1 && loadb_count != -2) + begin + loadb_count_no_predelay <= -2; + end + end + else if (intSCLR === 1'bx && (intCE === 1'b1 || C_SYNC_ENABLE == 0)) + begin + if (loadb_count != -1 && loadb_count != -2) + begin + intLOAD_DONE <= 1'bx; + if (C_HAS_SWAPB == 0) + intRFD_rel <= 1'bx; + else + intRFD_rel <= 1'b1; + loadb_count_no_predelay <= -2-sig_addr_bits; + end + end + else if (intCE === 1'b1) + begin + if (intLOADB_no_predelay === 1'b1) + begin + loadb_count_no_predelay <= loadb_delay; + intLOAD_DONE <= 0; + if (C_HAS_SWAPB == 0) + intRFD_rel <= 0; + else + intRFD_rel <= 1; + + //If the load comes when the load_done is undefined in the following + //cases then the load_done signal goes to 'X' during the load. + if (C_HAS_SWAPB == 1 && loadb_count == -3 && (real_latency > 0 || C_REG_A_B_INPUTS == 1)) + stay_x <= 1; + else + stay_x <= 0; + + end + else //loadb == 0. + begin + if (loadb_count_no_predelay > 0) + begin + if (loadb_count_no_predelay > 0) + begin + loadb_count_no_predelay <= loadb_count_no_predelay - 1; + end + if (stay_x == 1) + intLOAD_DONE <= 1'bx; + else + intLOAD_DONE <= 1'b0; + end + else if (loadb_count_no_predelay <= -3) + begin + if (~(loadb_count != -2-sig_addr_bits && C_REG_A_B_INPUTS == 0 && real_latency == 0)) + // Wait for sig_addr_bits cycles before setting the op + // to undefined. + begin + if (C_HAS_SWAPB == 0) + intRFD_rel <= 1'bx; + else + intRFD_rel <= 1'b1; + intLOAD_DONE <= 1'bx; + end + end + else if (loadb_count_no_predelay == 0) + begin + intLOAD_DONE <= 1; + intRFD_rel <= 1; + stay_x <= 0; + if (ND_I === 1'b1 || (C_HAS_SWAPB == 1 || C_HAS_ND == 0 || C_REG_A_B_INPUTS == 1)) + begin + loadb_count_no_predelay <= -1; + end + end + else if (loadb_count_no_predelay == -2) + begin + intLOAD_DONE <= 1; + intRFD_rel <= 1; + end + end + end + else if (intCE === 1'bx) + begin + if (loadb_count != -1 && loadb_count != -2 && (loadb_count != -2-sig_addr_bits && C_REG_A_B_INPUTS == 0 && real_latency == 0)) + begin + end + else if (loadb_count == -2-sig_addr_bits || (loadb_count != -1 && loadb_count != -2 && (C_REG_A_B_INPUTS == 1 || real_latency > 0))) + // Propogate the 'X' through when the TC from the load engines + // counter goes to 'X' or if the inputs are registered. + begin + intLOAD_DONE <= 1'bx; + if (C_HAS_SWAPB == 0) + intRFD_rel <= 1'bx; + else + intRFD_rel <= 1'b1; + end + end + end + end + + //Loadb_count_dly will mask out the first reult after a load. This is + //necessary in some cases. + always@(intACLR) + begin + if (intACLR === 1'b1) + loadb_count_dly = -1; + loadb_count_dly_int = -1; + end + + always@(posedge intCLK) + begin + if (last_clk !== intCLK && last_clk === 1'b0 && intCLK === 1'b1 && intCE === 1'b1 && intACLR === 1'b0) + begin + loadb_count_dly_int <= loadb_count; + //if (ND_I === 1'b1 || (C_HAS_SWAPB == 1 || C_HAS_ND == 0 || C_REG_A_B_INPUTS == 1)) + //begin + loadb_count_dly <= loadb_count_dly_int; + //end + end + end + + //Do the B input calculation. This can be an input, a constant or a reloadable constant. + always@(B or b_const0 or b_const1 or intLOAD_DONE or ND_I or bank_sel or posedge intCLK) + begin + if (C_MULT_TYPE < 2) + begin + B_INPUT = B; + end + else if (~((C_MULT_TYPE < 3) || (loaded == 0 && intLOADB === 1'b0))) + begin + //if (intLOAD_DONE === 1'b1 || C_HAS_SWAPB == 1) + if (loadb_count == -1 || C_HAS_SWAPB == 1) + begin + if (bank_sel == 0 && C_MULT_TYPE > 2 && loaded == 1) + begin + if ((C_HAS_ND == 0) || (C_HAS_SWAPB == 1 && loadb_count < 0)) + begin + B_INPUT = b_const0; + end + else if (C_HAS_ND == 1 && C_HAS_SWAPB == 0 && ND_I == 1) + begin + B_INPUT = b_const0; + end + end + else if (bank_sel == 1 && C_MULT_TYPE > 2 && loaded == 1 && loadb_count < 0) + begin + B_INPUT = b_const1; + end + else if (bank_sel == 2 && C_MULT_TYPE > 2 && loaded == 1 && loadb_count < 0) + begin + B_INPUT = `ballxs; + end + end + else + begin + B_INPUT = `ballxs; + end + end + end + + //Swap between the two banks of memory if the core has a SWAPB pin. + always@(intACLR) + begin + if (C_HAS_SWAPB == 1) + begin + if (intACLR === 1'b1) + begin + bank_sel = 0; + bank_sel_pre = 0; + end + else if (intACLR === 1'bx) + begin + if (bank_sel != 0) + bank_sel = 2; + bank_sel_pre = 2; + end + end + end + + always@(posedge intCLK) + begin + if (last_clk !== intCLK && last_clk === 1'b0 && intCLK === 1'b1 && intACLR === 1'b0) + begin + if (intSCLR === 1'b1 && (intCE === 1'b1 || C_SYNC_ENABLE == 0)) + begin + bank_sel <= 0; + bank_sel_pre <= 0; + end + else if (intSCLR === 1'bx && (intCE === 1'b1 || C_SYNC_ENABLE == 0)) + begin + if (bank_sel != 0) + bank_sel <= 2; + bank_sel_pre <= 2; + end + else if (intSCLR === 1'b1 && (intCE === 1'bx || C_SYNC_ENABLE == 0)) + begin + if (bank_sel != 0) + bank_sel <= 2; + bank_sel_pre <= 2; + end + else if (intCE === 1'b1) + begin + if (C_REG_A_B_INPUTS == 0 && real_latency > 0 && C_HAS_SWAPB == 1) + begin + bank_sel <= bank_sel_pre; + end + + if ((C_REG_A_B_INPUTS == 1 || real_latency == 0) && C_HAS_SWAPB == 1 && intSWAPB === 1'b1 && loadb_count < 0) + begin + if (bank_sel == 0) + bank_sel <= 1 ; + else + bank_sel <= 0 ; + end + else if ((C_REG_A_B_INPUTS == 1 || real_latency == 0) && C_HAS_SWAPB == 1 && intSWAPB === 1'bx && loadb_count < 0) + begin + bank_sel <= 2 ; + end + else if (C_REG_A_B_INPUTS == 0 && real_latency > 0 && C_HAS_SWAPB == 1 && intSWAPB === 1'b1 && loadb_count < 0) + begin + if (bank_sel_pre == 0) + bank_sel_pre <= 1 ; + else + bank_sel_pre <= 0 ; + end + else if (C_REG_A_B_INPUTS == 0 && real_latency > 0 && C_HAS_SWAPB == 1 && intSWAPB === 1'bx && loadb_count < 0) + begin + bank_sel_pre <= 2 ; + end + end + else if (intCE === 1'bx) + begin + if ((C_REG_A_B_INPUTS == 1 || real_latency == 0) && C_HAS_SWAPB == 1 && intSWAPB !== 1'b0) + begin + bank_sel <= 2 ; + end + else if (C_REG_A_B_INPUTS == 0 && real_latency > 0 && C_HAS_SWAPB == 1 && intSWAPB !== 1'b0) + begin + bank_sel_pre <= 2 ; + end + end + end + else if (((last_clk !== intCLK && intCLK === 1'bx && last_clk === 1'b0) || + (last_clk !== intCLK && intCLK === 1'b1 && last_clk === 1'bx)) && + (intACLR !== 1'b1)) + begin + if ((C_REG_A_B_INPUTS == 1 || real_latency == 0) && C_HAS_SWAPB == 1 && intSWAPB !== 1'b0) + begin + bank_sel <= 2 ; + end + else if (C_REG_A_B_INPUTS == 0 && real_latency > 0 && C_HAS_SWAPB == 1 && intSWAPB !== 1'b0) + begin + bank_sel_pre <= 2 ; + end + end + end + + +/* helper functions */ + + function defval; + input i; + input hassig; + input val; + begin + if(hassig == 1) + defval = i; + else + defval = val; + end + endfunction + + function [C_B_WIDTH - 1 : 0] to_bitsB; + input [C_B_WIDTH*8 : 1] instring; + integer i; + integer non_null_string; + begin + non_null_string = 0; + for(i = C_B_WIDTH; i > 0; i = i - 1) + begin // Is the string empty? + if(instring[(i*8)] == 0 && + instring[(i*8)-1] == 0 && + instring[(i*8)-2] == 0 && + instring[(i*8)-3] == 0 && + instring[(i*8)-4] == 0 && + instring[(i*8)-5] == 0 && + instring[(i*8)-6] == 0 && + instring[(i*8)-7] == 0 && + non_null_string == 0) + non_null_string = 0; // Use the return value to flag a non-empty string + else + non_null_string = 1; // Non-null character! + end + if(non_null_string == 0) // String IS empty! Just return the value to be all '0's + begin + for(i = C_B_WIDTH; i > 0; i = i - 1) + to_bitsB[i-1] = 0; + end + else + begin + for(i = C_B_WIDTH; i > 0; i = i - 1) + begin // Is this character a '0'? (ASCII = 48 = 00110000) + if(instring[(i*8)] == 0 && + instring[(i*8)-1] == 0 && + instring[(i*8)-2] == 1 && + instring[(i*8)-3] == 1 && + instring[(i*8)-4] == 0 && + instring[(i*8)-5] == 0 && + instring[(i*8)-6] == 0 && + instring[(i*8)-7] == 0) + to_bitsB[i-1] = 0; + // Or is it a '1'? + else if(instring[(i*8)] == 0 && + instring[(i*8)-1] == 0 && + instring[(i*8)-2] == 1 && + instring[(i*8)-3] == 1 && + instring[(i*8)-4] == 0 && + instring[(i*8)-5] == 0 && + instring[(i*8)-6] == 0 && + instring[(i*8)-7] == 1) + to_bitsB[i-1] = 1; + // Or is it a ' '? (a null char - in which case insert a '0') + else if(instring[(i*8)] == 0 && + instring[(i*8)-1] == 0 && + instring[(i*8)-2] == 0 && + instring[(i*8)-3] == 0 && + instring[(i*8)-4] == 0 && + instring[(i*8)-5] == 0 && + instring[(i*8)-6] == 0 && + instring[(i*8)-7] == 0) + to_bitsB[i-1] = 0; + else + begin + $display("Error in %m at time %d ns: non-binary digit in string \"%s\"\nExiting simulation...",$time, instring); + $finish; + end + end + end + end + endfunction + + function findB_width; + input [C_B_WIDTH-1 : 0] b_input; + integer i; + begin + for(i = C_B_WIDTH-1; i > 0; i = i - 1) + begin + if(b_input[i] == 1) + findB_width = i ; + else + findB_width = findB_width ; + end + end + endfunction + + function modulus; + input a ; + input b ; + integer divide ; + begin + divide = (a < b ? 0 : (a / b)) ; + modulus = a - (b*divide) ; + end + endfunction + + function max; + input a; + input b; + begin + max = (a > b) ? a : b; + end + endfunction + + function is_X; + input [multWidth-1 : 0] i; + begin + is_X = 1'b0; + for(j = 0; j < multWidth; j = j + 1) + begin + if(i[j] === 1'bx) + is_X = 1'b1; + end // loop + end + endfunction + + function [C_OUT_WIDTH-1 : 0] mult_convert; + input [multWidth-1 : 0] in_sum; + integer bit_index; + begin + for(bit_index = C_OUT_WIDTH-1; bit_index >= 0; bit_index = bit_index - 1) + begin + if (out_width > C_OUT_WIDTH) + begin + mult_convert[bit_index] = in_sum[(out_width-C_OUT_WIDTH)+bit_index] ; + end + else + begin + if (bit_index <= out_width) + begin + mult_convert[bit_index] = in_sum[bit_index]; + end + else if (C_A_TYPE == `c_signed || (C_A_TYPE == `c_pin && tmpA_SIGNED == 1) + || C_B_TYPE == `c_signed) + begin + if (C_MULT_TYPE > 2 && C_HAS_LOADB == 1 && C_A_WIDTH == 1 && C_A_TYPE == `c_pin + && C_HAS_A_SIGNED == 1 && C_B_TYPE == `c_signed) + mult_convert[bit_index] = in_sum[out_width]; + else + mult_convert[bit_index] = in_sum[out_width-1]; + end + else + begin + if (is_X(in_sum)) + mult_convert[bit_index] = 1'bx; + else + mult_convert[bit_index] = 0; + end + end + end + end + endfunction + + function [multWidth-1 : 0] add; + input [multWidth-1 : 0] i1; + input [multWidth-1 : 0] i2; + integer bit_index; + integer carryin, carryout; + begin + carryin = 0; + carryout = 0; + for(bit_index=0; bit_index < multWidth; bit_index = bit_index + 1) + begin + if (i1[bit_index] === 1'bx || i2[bit_index] === 1'bx) + begin + add[bit_index] = 1'bx ; + carryout = 1'bx ; + carryin = carryout ; + end + else if (carryin === 1'bx) + begin + add[bit_index] = 1'bx ; + carryout = 0 ; + carryin = carryout ; + end + else + begin + add[bit_index] = i1[bit_index] ^ i2[bit_index] ^ carryin; + carryout = (i1[bit_index] && i2[bit_index]) || (carryin && (i1[bit_index] || i2[bit_index])); + carryin = carryout; + end + end + end + endfunction + +endmodule + +`undef c_set +`undef c_clear +`undef c_override +`undef c_no_override +`undef c_add +`undef c_sub +`undef c_add_sub +`undef c_signed +`undef c_unsigned +`undef c_pin +`undef allUKs +`undef all0s +`undef ball0s +`undef ballxs +`undef aall0s +`undef aallxs +`undef baatall0s +`undef baatall1s +`undef baatallxs +`undef c_distributed +`undef c_dp_block +`undef mall0s +`undef mallUKs +`undef inall0s + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/MULT_GEN_V6_0_SEQ.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/MULT_GEN_V6_0_SEQ.v new file mode 100644 index 0000000..7b41ced --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/MULT_GEN_V6_0_SEQ.v @@ -0,0 +1,940 @@ +// Copyright(C) 2002 by Xilinx, Inc. All rights reserved. +// This text contains proprietary, confidential +// information of Xilinx, Inc., is distributed +// under license from Xilinx, Inc., and may be used, +// copied and/or disclosed only pursuant to the terms +// of a valid license agreement with Xilinx, Inc. This copyright +// notice must be retained as part of this text at all times. + + +/* $Id: MULT_GEN_V6_0_SEQ.v,v 1.15 2008/09/08 20:09:13 akennedy Exp $ +-- +-- Filename - MULT_GEN_V6_0.v +-- Author - Xilinx +-- Creation - 22 Mar 1999 +-- +-- Description - This file contains the Verilog behavior for the sequential part of the multiplier module +*/ + +`timescale 1ns/10ps + +`define c_set 0 +`define c_clear 1 +`define c_override 0 +`define c_no_override 1 +`define c_add 0 +`define c_sub 1 +`define c_add_sub 2 +`define c_signed 0 +`define c_unsigned 1 +`define c_pin 2 +`define c_distributed 0 +`define c_dp_block 2 +`define allUKs {(C_OUT_WIDTH)+1{1'bx}} + +`define awidthall0s {C_A_WIDTH{1'b0}} +`define accumall0s {accum_width{1'b0}} +`define storeall0s {(C_BAAT*(number_clocks-1)){1'b0}} +`define aloadall0s {(C_BAAT*(number_clocks)){1'b0}} +`define accumpipeall0s {(C_LATENCY+1){1'b0}} +`define rfdpipeall0s {(number_clocks-C_REG_A_B_INPUTS){1'b0}} +`define multsignedpipeall0s {(C_REG_A_B_INPUTS+1-ccm_serial+temp_mult+mult_signed_pipe_rubbish+mult_signed_pipe_rubbish2){1'b0}} +`define accumsignpipeall0s {(C_LATENCY+accum_sign_pipe_rubbish2){1'b0}} +`define intrdypipeall0s {(rdy_delay+1){1'b0}} +`define accumcompall0s {(accum_width+accum_store_width){1'b0}} +`define outputall0s {C_OUT_WIDTH{1'b0}} +`define accumstoreall0s {accum_store_width{1'b0}} + +module MULT_GEN_V6_0_SEQ (A, B, CLK, A_SIGNED, CE, ACLR, + SCLR, LOADB, LOAD_DONE, SWAPB, RFD, + ND, RDY, O, Q); + + parameter BRAM_ADDR_WIDTH = 8; + parameter C_A_TYPE = `c_signed; + parameter C_A_WIDTH = 16; + parameter C_BAAT = 2; + parameter C_B_CONSTANT = `c_signed; + parameter C_B_TYPE = `c_signed; + parameter C_B_VALUE = "0000000000000001"; + parameter C_B_WIDTH = 16; + parameter C_ENABLE_RLOCS = 1; + parameter C_HAS_ACLR = 0; + parameter C_HAS_A_SIGNED = 0; + parameter C_HAS_B = 1; + parameter C_HAS_CE = 0; + parameter C_HAS_LOADB = 0; + parameter C_HAS_LOAD_DONE = 0; + parameter C_HAS_ND = 0; + parameter C_HAS_O = 0; + parameter C_HAS_Q = 1; + parameter C_HAS_RDY = 0; + parameter C_HAS_RFD = 0; + parameter C_HAS_SCLR = 0; + parameter C_HAS_SWAPB = 0; + parameter C_MEM_INIT_PREFIX = "mem"; + parameter C_MEM_TYPE = 0; + parameter C_MULT_TYPE = 0; + parameter C_OUTPUT_HOLD = 0; + parameter C_OUT_WIDTH = 16; + parameter C_PIPELINE = 0; + parameter C_REG_A_B_INPUTS = 1; + parameter C_SQM_TYPE = 0; + parameter C_STACK_ADDERS = 0; + parameter C_STANDALONE = 0; + parameter C_SYNC_ENABLE = 0; + parameter C_USE_LUTS = 1; + + //Internal parameters + + //has ce selection for final output register + parameter has_q_ce = ((C_HAS_CE == 1 || C_OUTPUT_HOLD == 1) ? 1 : 0); + //has_a_signed selectionf for internal multiplier + parameter mult_has_a_signed = (C_A_TYPE == `c_signed ? 1 : (C_HAS_A_SIGNED == 1 ? 1 : 0)); + //a_type for internal multiplier + parameter mult_a_type = (C_A_TYPE == `c_signed ? `c_pin : (C_A_TYPE == `c_pin ? `c_pin : `c_unsigned)); + //output width for internal multiplier + parameter mult_width = (C_B_TYPE == `c_signed ? C_BAAT + C_B_WIDTH : (C_B_WIDTH == 1 ? C_BAAT + mult_has_a_signed : C_BAAT + C_B_WIDTH + mult_has_a_signed)); + + + //***********************THIS SECTION CALCULATES INTERNAL MULTIPLIER LATENCY**************************************** + + parameter incA = (((mult_has_a_signed == 1 || mult_a_type == `c_signed) && C_B_TYPE == `c_unsigned) ? 1 : 0) ; + parameter incB = (C_B_TYPE == `c_signed ? 1 : 0) ; + parameter inc = ((C_B_TYPE == `c_unsigned && mult_a_type == `c_unsigned) ? 0 : 1) ; + parameter dec = ((C_B_TYPE == `c_unsigned && mult_a_type == `c_unsigned) ? 1 : 0) ; + parameter inc_a_width = 0; + parameter decrement = (mult_has_a_signed == 1 ? 1 : 0) ; + + //Parameters to calculate the latency for the parallel multiplier. + parameter a_ext_width_par = (mult_has_a_signed == 1 ? C_BAAT+1 : C_BAAT) ; + parameter a_ext_width_seq = ((mult_has_a_signed == 1 || mult_a_type == `c_signed) ? C_BAAT+1 : C_BAAT) ; + parameter a_ext_width = a_ext_width_par; + + /* Compare the width of the A port, to the width of the B port + If the A port is smaller, then swap these over, otherwise leave + alone */ + + parameter a_w = (C_BAAT < C_B_WIDTH ? C_B_WIDTH : a_ext_width); + parameter a_t = (C_BAAT < C_B_WIDTH ? C_B_TYPE : mult_a_type); + parameter b_w = (C_A_WIDTH < C_B_WIDTH ? a_ext_width : C_B_WIDTH); + parameter b_t = (C_A_WIDTH < C_B_WIDTH ? mult_a_type : C_B_TYPE); + + // The mult18 parameter signifies if the final mult18x18 primitive is used + // without having to pad with zeros, or sign extending - thus leading to + // a more efficient implementation - e.g. a 35x35 (signed x signed) multiplier + // mult18, is used in the calculation of a_prods and b_prods, which indicate + // how many mult18x18 primitives are requred. + + parameter mult18 = (((a_t == `c_signed && a_w % 17 == 1) + && ((b_t == `c_signed && b_w <= a_w) || (b_t == `c_unsigned && b_w < a_w))) ? 1 : 0); + + parameter a_prods = (a_ext_width-1)/(17 + mult18) + 1 ; + parameter b_prods = (C_B_WIDTH-1)/(17 + mult18) + 1 ; + parameter a_count = (a_ext_width+1)/2 ; + parameter b_count = (C_B_WIDTH+1)/2 ; + parameter parm_numAdders = (C_MULT_TYPE == 1 ? (a_prods*b_prods) : ((a_ext_width <= C_B_WIDTH) ? a_count : b_count)) ; + + //Parameters to calculate the latency for the constant coefficient multiplier. + parameter rom_addr_width = (C_MEM_TYPE == `c_distributed ? 4 : BRAM_ADDR_WIDTH) ; + parameter sig_addr_bits = (C_BAAT >= rom_addr_width ? rom_addr_width : C_BAAT) ; + parameter effective_op_width = ((mult_has_a_signed == 0 || C_HAS_LOADB == 1) ? C_BAAT : C_BAAT+1) ; + parameter a_input_width = ((effective_op_width % rom_addr_width == 0) ? effective_op_width : effective_op_width + rom_addr_width - (effective_op_width % rom_addr_width)) ; + parameter mod = a_input_width % rom_addr_width ; + parameter op_width = (mod == 0 ? a_input_width : (a_input_width + rom_addr_width) - mod) ; + parameter a_width = op_width; + parameter need_addsub = ((C_HAS_LOADB == 1 && (mult_a_type == `c_signed || mult_has_a_signed == 1)) ? 1 : 0) ; + parameter ccm_numAdders_1 = (mod == 0 ? (a_input_width/rom_addr_width) : (a_input_width/rom_addr_width)+1) ; + parameter need_0_minus_pp = ((need_addsub == 1 && ccm_numAdders_1 <= 1) ? 1 : 0) ; + parameter ccm_numAdders = (need_0_minus_pp == 1 ? 1 : ccm_numAdders_1 - 1) ; + parameter ccm_init1 = ((C_HAS_LOADB == 1 && C_MEM_TYPE == `c_dp_block) ? 1 : 0) ; + parameter ccm_init2 = ((C_HAS_LOADB == 1 && (mult_a_type == `c_signed || mult_has_a_signed == 1) && C_PIPELINE == 1) ? 1 : 0) ; + parameter ccm_init3 = (((ccm_numAdders > 0 || C_HAS_SWAPB == 1) && (C_PIPELINE == 1 || C_MEM_TYPE == `c_dp_block)) ? 1 : 0) ; + parameter ccm_init4 = ((ccm_numAdders > 0 && C_HAS_SWAPB == 1 && C_PIPELINE == 1) ? 1 : 0) ; + parameter ccm_initial_latency = ccm_init1 + ccm_init2 + ccm_init3 + ccm_init4 ; + parameter add_one = 0 ; + parameter extra_cycles = 0 ; + + //Latency calculation + parameter numAdders = (C_MULT_TYPE < 2 ? parm_numAdders - 1 : ccm_numAdders) ; + parameter log = (C_PIPELINE == 1 ? (numAdders < 2 ? 0 : (numAdders < 4 ? 1 : (numAdders < 8 ? 2 : (numAdders < 16 ? 3 : (numAdders < 32 ? 4 : (numAdders < 64 ? 5 : (numAdders < 128 ? 6 : 7))))))) : 0) ; + parameter C_LATENCY_sub = (C_MULT_TYPE < 2 ? (numAdders > 0 ? (extra_cycles + log + 1) : 0) : (numAdders > 0 ? (ccm_initial_latency + extra_cycles + log + add_one) : ccm_initial_latency)) ; + parameter C_LATENCY_nonseq = (C_PIPELINE == 1 ? C_LATENCY_sub : (C_MULT_TYPE < 2 ? 0 : C_LATENCY_sub)) ; //+extra_latency : 0) ; + parameter serial_adjust1 = (C_SQM_TYPE == 1 && C_MULT_TYPE > 1 ) ? 1 : 0 ; + parameter serial_adjust = (C_SQM_TYPE == 1 && C_MULT_TYPE > 1) ? 1 : 0 ; + parameter blk_mem_adjust = ((C_MULT_TYPE > 1 && C_MEM_TYPE == `c_dp_block && C_PIPELINE == 0 && ccm_numAdders_1 == 1) ? 1 : 0) ; // && C_LATENCY_nonseq == 0) ? 1 : 0) ; + parameter slicer_adjust = 0; // && C_PIPELINE == 0)) ? 1 : 0) ; + parameter reg_adjust = (C_SQM_TYPE == 0 && C_PIPELINE == 0 && C_LATENCY_nonseq == 0 ? 1 : 0) ; + parameter pipe_adjust = ((C_SQM_TYPE == 1 && C_PIPELINE == 0 && serial_adjust == 0) ? 1 : 0) ; + parameter C_LATENCY_seq = C_LATENCY_nonseq + slicer_adjust + blk_mem_adjust ; + parameter nd_adjust = (C_HAS_ND == 1 && C_LATENCY_nonseq > 1 ) ? 1 : 0 ; //&& ~(C_MEM_TYPE == `c_dp_block && C_HAS_LOADB == 1 && C_HAS_SWAPB == 1 && C_PIPELINE == 0)) ? 1 : 0 ; + parameter desperation = C_PIPELINE ; + parameter C_LATENCY = (C_LATENCY_nonseq+C_PIPELINE+blk_mem_adjust); + //********************************************************************************************************** + + //Parameters to calculate the number of cycles that the sequential mult takes to process the inputs. + parameter div_cycle = (C_A_WIDTH/C_BAAT) ; + parameter mod_cycle = (C_A_WIDTH - (C_BAAT*div_cycle)) ; + parameter no_of_cycles = (mod_cycle == 0 ? div_cycle : div_cycle+1) ; + parameter number_clocks = no_of_cycles; + + //Determine if the slicer is going to be avoided + parameter ccm_serial = (C_SQM_TYPE == 1 ? (C_MULT_TYPE >= 2 ? 1 : 0) : 0); + //Calculate pipeline delay for the accum_sign + parameter accum_delay = C_LATENCY-ccm_serial; + //Calculate is accum_sign is actually needed + parameter accum_sign_needed = (C_B_TYPE == `c_signed ? 1 : (mult_has_a_signed == 1 ? 1 : 0)); + //Calculate size of mult_width + sign extension if needed + parameter accum_mult_width = mult_width + accum_sign_needed; + //Calculate pipeline delay for ready + parameter rdy_delay = C_HAS_Q+C_REG_A_B_INPUTS+C_LATENCY-ccm_serial+2-C_OUTPUT_HOLD; + //Calculate size of accumulator output + parameter accum_width = mult_width+1; //accum_mult_width+1; + //Calculate size of accumulator storage bits + parameter accum_store_width = (C_BAAT*(number_clocks-1)); + //Determine if internal multiplier has an rfd + parameter mult_has_rfd = (C_HAS_SWAPB ? 0 : (C_HAS_LOADB ? 1 : 0)); + //Offsets to ensure that verilog does not complain about reverse logic unnecessarily + parameter temp_offset = (C_A_WIDTH == (C_BAAT*number_clocks) ? 1 : 0); + parameter temp_mult = (C_REG_A_B_INPUTS+1-ccm_serial <= 1 ? 2-C_REG_A_B_INPUTS+1-ccm_serial : 0); + parameter temp_accum = 0; //(accum_store_width > C_BAAT ? 0 : C_BAAT); + parameter temp_mult_out = (accum_mult_width > 1 ? 0 : 1); + //Calculate predelay value for internal multiplier + parameter predelay = (C_MULT_TYPE > 2 ? 1 + C_REG_A_B_INPUTS - C_SQM_TYPE : 0); + parameter rubbish = (C_LATENCY == 0 ? 1 : 0); + parameter accum_sign_pipe_rubbish = (C_LATENCY == 0 ? 1 : 0); + parameter accum_sign_pipe_rubbish2 = (C_LATENCY < 2 ? 2 : 0); + parameter mult_signed_pipe_rubbish = (C_REG_A_B_INPUTS+1-ccm_serial == 0 ? 1 : 0); + parameter mult_signed_pipe_rubbish2 = (C_REG_A_B_INPUTS+1-ccm_serial < 2 ? 1 : 0); + parameter intO_rubbish = (C_A_WIDTH+C_B_WIDTH+C_HAS_A_SIGNED-C_OUT_WIDTH > 0 ? C_A_WIDTH+C_B_WIDTH+C_HAS_A_SIGNED-C_OUT_WIDTH : 0); + + parameter ncelab_accum_complete_low = ((C_OUT_WIDTH <= C_A_WIDTH+C_B_WIDTH+C_HAS_A_SIGNED) ? (C_A_WIDTH+C_B_WIDTH+C_HAS_A_SIGNED-C_OUT_WIDTH) : 0); + parameter ncelab_into_high = ((C_OUT_WIDTH <= C_A_WIDTH+C_B_WIDTH+C_HAS_A_SIGNED) ? (C_OUT_WIDTH) : (C_A_WIDTH+C_B_WIDTH+C_HAS_A_SIGNED)); + + parameter ncelab_rfd_pipe_select = ((number_clocks-C_REG_A_B_INPUTS-1 > 0) ? number_clocks-C_REG_A_B_INPUTS-2 : 0); + parameter ncelab_rfd_pipe_low = ((number_clocks-C_REG_A_B_INPUTS > 1) ? 1 : 0); + + parameter ncelab_accum_store_low = ((accum_store_width > C_BAAT) ? C_BAAT : 0); + parameter ncelab_accum_store_high = ((accum_store_width > C_BAAT) ? (accum_store_width-C_BAAT) : accum_store_width); + + input [(C_A_WIDTH-1-((C_A_WIDTH-1)*C_SQM_TYPE)) : 0] A; + input [C_B_WIDTH-1 : 0] B; + input CLK; + input CE; + input A_SIGNED; + input LOADB; + input SWAPB; + input ND; + input ACLR; + input SCLR; + output RFD; + output RDY; + output LOAD_DONE; + output [C_OUT_WIDTH-1 : 0] O; + output [C_OUT_WIDTH-1 : 0] Q; + + //Clock enable signal for q registers + wire int_q_ce; + //Held a_input + reg [(C_BAAT*number_clocks)-1 : 0] a_load; + wire [C_B_WIDTH-1 : 0] regB; + wire [(C_A_WIDTH-1-((C_A_WIDTH-1)*C_SQM_TYPE)) : 0] regA; + wire [C_B_WIDTH-1 : 0] regBB; + wire [(C_A_WIDTH-1-((C_A_WIDTH-1)*C_SQM_TYPE)) : 0] regAA; + wire intCE; + reg intA_SIGNED; + wire regA_SIGNED; + wire intACLR; + wire intSCLR; + wire initial_intCLK; + reg intCLK; + reg last_clk; + wire intLOADB; + wire intSWAPB = (C_HAS_SWAPB ? SWAPB : 0); + wire regND; + wire intND ; + reg intRFD; + reg reg_rfd; + wire intLOAD_DONE; + reg [C_OUT_WIDTH-1 : 0 ] intO; + wire [C_OUT_WIDTH-1 : 0] intQ; + wire a_signed_held; + reg accum_load; + wire RDY; + reg [C_LATENCY+1 : 0] accum_pipe; + reg [number_clocks-C_REG_A_B_INPUTS-1 : 0] rfd_pipe; + wire intSCLR_pure; + wire a_slice_load; + wire a_slice_load_sclr; + wire [C_BAAT-1 : 0] a_slice; + wire [C_B_WIDTH-1 : 0] b_held; + wire [C_B_WIDTH-1 : 0] b_reg; + wire [(C_A_WIDTH-1-((C_A_WIDTH-1)*C_SQM_TYPE)) : 0] a_reg; + wire a_signed_reg; + wire slice_rfd; + wire int_nd; + reg [accum_width+accum_store_width-1 : 0] accum_complete; + reg [accum_width-1 : 0] accum_out; + reg [accum_store_width-1 : 0] accum_store; + reg [accum_width-1 : 0] accum_feedback; + wire int_sclr_loadb_swapb; + wire int_a_signed; + wire pipe_rfd; + wire mult_signed; + reg int_mult_signed1; + reg int_mult_signed2; + reg int_mult_signed3; + wire pipe_mult_signed; + reg [C_REG_A_B_INPUTS+1-ccm_serial+temp_mult+mult_signed_pipe_rubbish+mult_signed_pipe_rubbish2 : 0] mult_signed_pipe; + reg [accum_mult_width-1 : 0] accum_in; + wire [mult_width-1 : 0] mult_out; + reg accum_sign; + reg [C_LATENCY-1+accum_sign_pipe_rubbish2 : 0] accum_sign_pipe; + reg int_rdy; + reg int_rdy_op_hold; + reg int_rfd_reg; + wire accum_mult_out_msb; + + wire [C_OUT_WIDTH-1 : 0] Q = (C_HAS_Q == 1 ? intQ : `allUKs); + wire [C_OUT_WIDTH-1 : 0] O = (C_HAS_O == 1 ? intO : `allUKs); + wire RFD = (C_HAS_RFD == 1 ? intRFD : 1'bx); + wire LOAD_DONE = (C_HAS_LOAD_DONE == 1 ? intLOAD_DONE : 1'bx); + wire [mult_width-1 : 0] mult_o; + wire [mult_width-1 : 0] mult_q; + wire dummy; + wire mult_rfd; + reg [rdy_delay : 0] int_rdy_pipe; + reg [C_B_WIDTH-1 : 0] initB_INPUT; + + integer i, b_width, shift_bits, real_latency, real_rdy_delay; + + assign intCE = (C_HAS_CE == 1 ? CE : 1); + assign initial_intCLK = CLK; + assign intACLR = (C_HAS_ACLR == 1 ? ACLR : 0) ; + //Combine SCLR with CE where appropriate depending on C_SYNC_ENABLE + assign intSCLR = (C_HAS_SCLR == 1 ? (C_HAS_CE == 1 ? (C_SYNC_ENABLE == 0 ? SCLR : SCLR & CE) : SCLR) : 0); + assign intSCLR_pure = (C_HAS_SCLR == 1 ? SCLR : 0); + + assign int_nd = (C_HAS_ND == 1 ? (C_REG_A_B_INPUTS == 1 ? regND : ND) : 1); + assign a_slice_load = intCE & int_nd & slice_rfd; + //Combine a_slice_load with sclr and CE where appropriate depending on C_SYNC_ENABLE + assign a_slice_load_sclr = (C_HAS_SCLR == 1 ? (C_SYNC_ENABLE == 1 ? a_slice_load | (intSCLR & intCE) : a_slice_load) : a_slice_load); + assign a_slice = a_load[C_BAAT-1 : 0]; + assign b_held = (C_MULT_TYPE < 2 ? regBB : (C_MULT_TYPE > 2 ? B : b_reg)); + assign a_reg = (C_REG_A_B_INPUTS == 1 ? regA : A); + assign b_reg = (C_REG_A_B_INPUTS == 1 ? regB : B); + assign a_signed_reg = (C_REG_A_B_INPUTS == 1 ? regA_SIGNED : A_SIGNED); + assign slice_rfd = (C_REG_A_B_INPUTS == 1 ? reg_rfd : intRFD); + //Combine int_sclr, loadb and swapb, CE and mult_rfd to reset rfd as appropriate depending on C_SYNC_ENABLE + assign int_sclr_loadb_swapb = (C_HAS_SWAPB == 1 ? ((C_SYNC_ENABLE == 1 && C_HAS_CE == 1) ? (intSCLR | (intSWAPB & intCE)) : intSCLR | intSWAPB) : (C_HAS_LOADB == 1 ? ((C_SYNC_ENABLE == 1 && C_HAS_CE == 1) ? (intSCLR | ((!mult_rfd) & intCE)) : intSCLR | (!mult_rfd)) : intSCLR)); + assign int_a_signed = (C_HAS_A_SIGNED == 1 ? a_signed_held : (C_A_TYPE == `c_signed && C_SQM_TYPE == 0 ? 1 : 0)); + assign pipe_rfd = (number_clocks-C_REG_A_B_INPUTS-1 > 0 ? rfd_pipe[ncelab_rfd_pipe_select] : a_slice_load_sclr); + assign mult_signed = (C_HAS_A_SIGNED == 1 ? (C_REG_A_B_INPUTS+1-ccm_serial == 0 ? int_mult_signed1 : pipe_mult_signed) : pipe_mult_signed & a_slice[C_BAAT-1]); + assign pipe_mult_signed = (C_REG_A_B_INPUTS+1-ccm_serial == 0 ? pipe_rfd : mult_signed_pipe[C_REG_A_B_INPUTS+1-ccm_serial-1+mult_signed_pipe_rubbish]); + + assign RDY = (C_HAS_RDY == 1 ? (C_OUTPUT_HOLD == 1 ? int_rdy_op_hold : int_rdy) : 1'bx); + + assign mult_out = (C_PIPELINE == 1 ? mult_q : (blk_mem_adjust == 1 ? mult_q : mult_o)); + assign int_q_ce = (C_OUTPUT_HOLD == 1 ? (intCE & int_rdy) : intCE); + assign accum_mult_out_msb = accum_in[accum_mult_width-1]; + assign intLOADB = (C_HAS_LOADB == 1 ? LOADB : 1'b0); + + MULT_GEN_V6_0_NON_SEQ #(BRAM_ADDR_WIDTH, mult_a_type, C_BAAT, C_BAAT, C_B_CONSTANT, C_B_TYPE, + C_B_VALUE, C_B_WIDTH, C_ENABLE_RLOCS, C_HAS_ACLR, mult_has_a_signed, + C_HAS_B, C_HAS_CE, C_HAS_LOADB, C_HAS_LOAD_DONE, 0, 1, + 1, 0, mult_has_rfd, C_HAS_SCLR, C_HAS_SWAPB, C_MEM_INIT_PREFIX, + C_MEM_TYPE, C_MULT_TYPE, 0, mult_width, C_PIPELINE, predelay, 0, 0, 1, + 0, C_SYNC_ENABLE, C_USE_LUTS) + int_mult (.A(a_slice), .B(b_held), .CLK(intCLK), .A_SIGNED(mult_signed), .CE(intCE), .ACLR(intACLR), + .SCLR(intSCLR), .LOADB(intLOADB), .LOAD_DONE(intLOAD_DONE), .SWAPB(intSWAPB), .RFD(mult_rfd), + .ND(1'b0), .RDY(dummy), .O(mult_o), .Q(mult_q)); + + C_REG_FD_V6_0 #("0", C_ENABLE_RLOCS, C_HAS_ACLR, 0, 0, + C_HAS_CE, C_HAS_SCLR, 0, 0, + "0", C_SYNC_ENABLE, 0, (C_A_WIDTH-1-((C_A_WIDTH-1)*C_SQM_TYPE))+1) + rega (.D(A), .CLK(intCLK), .CE(intCE), .ACLR(intACLR), .ASET(1'b0), + .AINIT(1'b0), .SCLR(intSCLR_pure), .SSET(1'b0), .SINIT(1'b0), + .Q(regA)); + + C_REG_FD_V6_0 #("0", C_ENABLE_RLOCS, C_HAS_ACLR, 0, 0, + C_HAS_CE, C_HAS_SCLR, 0, 0, + "0", C_SYNC_ENABLE, 0, C_B_WIDTH) + regb (.D(B), .CLK(intCLK), .CE(intCE), .ACLR(intACLR), .ASET(1'b0), + .AINIT(1'b0), .SCLR(intSCLR_pure), .SSET(1'b0), .SINIT(1'b0), + .Q(regB)); + + C_REG_FD_V6_0 #("0", C_ENABLE_RLOCS, C_HAS_ACLR, 0, 0, + 1, C_HAS_SCLR, 0, 0, + "0", C_SYNC_ENABLE, 0, C_B_WIDTH) + regbb (.D(b_reg), .CLK(intCLK), .CE(a_slice_load_sclr), .ACLR(intACLR), .ASET(1'b0), + .AINIT(1'b0), .SCLR(intSCLR_pure), .SSET(1'b0), .SINIT(1'b0), + .Q(regBB)); + + C_REG_FD_V6_0 #("0", C_ENABLE_RLOCS, C_HAS_ACLR, 0, 0, + has_q_ce, C_HAS_SCLR, 0, 0, + "0", C_SYNC_ENABLE, 0, C_OUT_WIDTH) + regq (.D(intO), .CLK(intCLK), .CE(int_q_ce), .ACLR(intACLR), .ASET(1'b0), + .AINIT(1'b0), .SCLR(intSCLR_pure), .SSET(1'b0), .SINIT(1'b0), + .Q(intQ)); + + C_REG_FD_V6_0 #("0", C_ENABLE_RLOCS, C_HAS_ACLR, 0, 0, + C_HAS_CE, C_HAS_SCLR, 0, 0, + "0", C_SYNC_ENABLE, 0, 1) + regnd (.D(ND), .CLK(intCLK), .CE(intCE), .ACLR(intACLR), .ASET(1'b0), + .AINIT(1'b0), .SCLR(intSCLR_pure), .SSET(1'b0), .SINIT(1'b0), + .Q(regND)); + + C_REG_FD_V6_0 #("0", C_ENABLE_RLOCS, C_HAS_ACLR, 0, 0, + C_HAS_CE, C_HAS_SCLR, 0, 0, + "0", C_SYNC_ENABLE, 0, 1) + regasig (.D(A_SIGNED), .CLK(intCLK), .CE(intCE), .ACLR(intACLR), .ASET(1'b0), + .AINIT(1'b0), .SCLR(intSCLR_pure), .SSET(1'b0), .SINIT(1'b0), + .Q(regA_SIGNED)); + + C_REG_FD_V6_0 #("0", C_ENABLE_RLOCS, C_HAS_ACLR, 0, 0, + C_HAS_CE, C_HAS_SCLR, 0, 0, + "0", C_SYNC_ENABLE, 0, 1) + regmultmsb (.D(accum_mult_out_msb), .CLK(intCLK), .CE(intCE), .ACLR(intACLR), .ASET(1'b0), + .AINIT(1'b0), .SCLR(intSCLR_pure), .SSET(1'b0), .SINIT(1'b0), + .Q(accum_mult_out_msb_delayed)); + + C_REG_FD_V6_0 #("0", C_ENABLE_RLOCS, 0, 0, 0, + 1, 0, 0, 0, + "0", C_SYNC_ENABLE, 0, 1) + latchasig (.D(a_signed_reg), .CLK(intCLK), .CE(a_slice_load_sclr), .ACLR(1'b0), .ASET(1'b0), + .AINIT(1'b0), .SCLR(1'b0), .SSET(1'b0), .SINIT(1'b0), + .Q(a_signed_held)); + + initial + begin + intRFD = 1 ; + int_rfd_reg = 1; + int_rdy_pipe = `intrdypipeall0s; + rfd_pipe = `rfdpipeall0s; + reg_rfd = 0; + + int_rdy = 0; + int_rdy_op_hold = 0; + + accum_out = `accumall0s; + accum_store = `accumstoreall0s; + + //Calculate the shift bits + initB_INPUT = (C_MULT_TYPE < 2) ? B : to_bitsB(C_B_VALUE); + + //Find the real b input width + if (C_MULT_TYPE > 1 && C_HAS_LOADB == 0) + begin + b_width = 0 ; + for(i = 0; i < C_B_WIDTH; i = i + 1) + begin + if(initB_INPUT[i] == 1) + b_width = i+1 ; + end + end + else + begin + b_width = C_B_WIDTH ; + end + + if (C_MULT_TYPE != 2) + begin + shift_bits = 0 ; + end + else + begin + shift_bits = 0 ; + for(i = C_B_WIDTH-1; i >= 0; i = i - 1) + begin + if (initB_INPUT[i] == 1) + shift_bits = i ; + end + end + + if ((C_B_TYPE == `c_unsigned && (b_width-shift_bits) == 1 && C_HAS_LOADB == 0) || (C_HAS_LOADB == 0 && b_width == 0)) + begin + real_latency = C_PIPELINE+blk_mem_adjust ; + end + else + begin + real_latency = C_LATENCY ; + end + + real_rdy_delay = C_HAS_Q+C_REG_A_B_INPUTS+real_latency-ccm_serial+2-C_OUTPUT_HOLD; + + end + + always@(initial_intCLK) + begin + last_clk <= intCLK ; + intCLK <= initial_intCLK ; + end + + always@(accum_pipe or a_slice_load_sclr) + begin + if ((real_latency-ccm_serial) >= 0) + accum_load = accum_pipe[real_latency-ccm_serial]; + else + accum_load = a_slice_load_sclr; + end + + always@(accum_sign_pipe or mult_signed) + begin + if (real_latency > 0) + accum_sign = accum_sign_pipe[real_latency+accum_sign_pipe_rubbish-1]; + else + accum_sign = mult_signed; + end + + always@(int_rdy_pipe) + begin + if (real_rdy_delay > 0) + begin + int_rdy = int_rdy_pipe[real_rdy_delay-1]; + int_rdy_op_hold = int_rdy_pipe[real_rdy_delay]; + end + else + begin + int_rdy = int_rdy_pipe[0]; + int_rdy_op_hold = int_rdy_pipe[0]; + end + end + + //Process to calculate output when the clears go high. + //In addition action on the SWAPB and LOADB pins also cause the sequential multiplier to + //de-assert RFD. + always@(intACLR or intSCLR or int_sclr_loadb_swapb or int_rfd_reg) + begin + if (intACLR == 1 || int_sclr_loadb_swapb == 1) + intRFD = 0 ; + else + intRFD = int_rfd_reg; + end + + //Register rfd for serial parallel type + always@(posedge intCLK) + begin + if (int_sclr_loadb_swapb == 1) + reg_rfd <= 0; + else + begin + if (intCE == 1 && intACLR != 1) + reg_rfd <= intRFD; + end + end + + //int_rfd_reg + always@(posedge intCLK) + begin + if (int_sclr_loadb_swapb == 1) + int_rfd_reg <= 1; + else + begin + if (intCE == 1 && intACLR != 1) + begin + if (C_HAS_ND == 1) + int_rfd_reg <= (pipe_rfd && !intRFD) || (intRFD && !ND); + else + int_rfd_reg <= pipe_rfd && !intRFD; + end + end + end + + //mult_sign serial + always@(pipe_rfd or a_signed_reg or a_signed_held) + begin + if (C_HAS_A_SIGNED == 1 && C_REG_A_B_INPUTS+1-ccm_serial == 0) + begin + if (number_clocks-C_REG_A_B_INPUTS == 1) + int_mult_signed1 <= pipe_rfd & a_signed_reg; + else + int_mult_signed1 <= pipe_rfd & a_signed_held; + end + end + + //int_mult_signed + always@(pipe_rfd or a_signed_reg or a_signed_held or pipe_mult_signed or a_slice) + begin + if (C_HAS_A_SIGNED == 1) + begin + if (number_clocks-C_REG_A_B_INPUTS == 1) + int_mult_signed2 <= pipe_rfd & a_signed_reg; + else + int_mult_signed2 <= pipe_rfd & a_signed_held; + end + else + int_mult_signed2 <= pipe_rfd; + end + + //int_rdy + always@(posedge intCLK) + begin + if (intSCLR == 1) + int_rdy_pipe <= `intrdypipeall0s; + else if (intCE == 1 && intACLR == 0) + begin + if (rdy_delay > 0) + int_rdy_pipe[rdy_delay : 1] <= int_rdy_pipe[rdy_delay-1 : 0]; + int_rdy_pipe[0] <= pipe_rfd; + end + end + + + //For a serial, CCM type, we don't need any slicing + always@(a_reg) + begin + if (C_SQM_TYPE == 1 && C_MULT_TYPE >= 2) + a_load <= a_reg; + end + + //Aclr all registers + always@(intACLR) + begin + if (intACLR == 1) + begin + if (C_SQM_TYPE != 1 || C_MULT_TYPE < 2) + a_load = `aloadall0s; + accum_out = `accumall0s; + accum_store = `storeall0s; + if (real_latency >= 0) + accum_pipe = `accumpipeall0s; + rfd_pipe = `rfdpipeall0s; + reg_rfd = 0; + int_rfd_reg = 1; + if (C_REG_A_B_INPUTS+1-ccm_serial > 0) + mult_signed_pipe[C_REG_A_B_INPUTS+1-ccm_serial+mult_signed_pipe_rubbish+mult_signed_pipe_rubbish2-1 : 0] <= `multsignedpipeall0s; + int_mult_signed2 = 0; + if (real_latency > 0) + accum_sign_pipe <= `accumsignpipeall0s; + int_rdy_pipe <= `intrdypipeall0s; + end + end + + //Pipelines + always@(posedge intCLK) + begin + if (intSCLR == 1) + begin + if (real_latency >= 0) + accum_pipe <= `accumpipeall0s; + if (C_REG_A_B_INPUTS+1-ccm_serial > 0) + mult_signed_pipe[C_REG_A_B_INPUTS+1-ccm_serial+mult_signed_pipe_rubbish+mult_signed_pipe_rubbish2-1 : 0] <= `multsignedpipeall0s; + end + else if (intCE == 1 && intACLR == 0) + begin + if (C_LATENCY > 0) + accum_pipe[C_LATENCY+rubbish : 1] <= accum_pipe[C_LATENCY+rubbish-1 : 0]; + if (real_latency >= 0) + accum_pipe[0] <= a_slice_load_sclr; + if (C_REG_A_B_INPUTS+1-ccm_serial > 1) + mult_signed_pipe[C_REG_A_B_INPUTS+1-ccm_serial-1+temp_mult+mult_signed_pipe_rubbish+mult_signed_pipe_rubbish2 : 1] <= mult_signed_pipe[C_REG_A_B_INPUTS+1-ccm_serial-2+temp_mult+mult_signed_pipe_rubbish+mult_signed_pipe_rubbish2 : 0]; + if (C_REG_A_B_INPUTS+1-ccm_serial+temp_mult > 0) + mult_signed_pipe[0] <= int_mult_signed2; + end + end + + //rfd pipeline + always@(posedge intCLK) + begin + if (int_sclr_loadb_swapb == 1) + rfd_pipe <= `rfdpipeall0s; + else + begin + if (intCE == 1 && intACLR == 0) + begin + if (number_clocks-C_REG_A_B_INPUTS > 1) + rfd_pipe[number_clocks-C_REG_A_B_INPUTS-1 : ncelab_rfd_pipe_low] <= rfd_pipe[ncelab_rfd_pipe_select : 0]; + rfd_pipe[0] <= a_slice_load_sclr; + end + end + end + + //Slice the A input + always@(posedge intCLK) + begin + if (intSCLR == 1) + begin + if (C_SQM_TYPE != 1 || C_MULT_TYPE < 2) + a_load <= `aloadall0s; + end + else if (intCE == 1 && intACLR != 1) + begin + if (C_SQM_TYPE == 0) //need to slice + begin + if (a_slice_load == 1) + begin + a_load[C_A_WIDTH-1 : 0] <= a_reg; + for (i = 0; i < (C_BAAT*number_clocks)-C_A_WIDTH; i = i + 1) //sign extend as required + begin + if (C_HAS_A_SIGNED == 1) + begin + if (a_signed_reg == 1) + a_load[(C_BAAT*number_clocks)+temp_offset-1-i] <= a_reg[C_A_WIDTH-1-((C_A_WIDTH-1)*C_SQM_TYPE)]; + else + a_load[(C_BAAT*number_clocks)+temp_offset-1-i] <= 0; + end + else if (C_A_TYPE == `c_signed) + a_load[(C_BAAT*number_clocks)+temp_offset-1-i] <= a_reg[C_A_WIDTH-1-((C_A_WIDTH-1)*C_SQM_TYPE)]; + else + a_load[(C_BAAT*number_clocks)+temp_offset-1-i] <= 0; + end + end + else + begin + a_load[(C_BAAT*(number_clocks-1))-1 : 0] <= a_load[(C_BAAT*number_clocks)-1 : C_BAAT]; + for (i = 0; i < C_BAAT; i = i + 1) + begin + if (int_a_signed == 1) + a_load[(C_BAAT*number_clocks)-1-i] <= a_load[(C_BAAT*number_clocks)-1]; + else + a_load[(C_BAAT*number_clocks)-1-i] <= 0; + end + end + end + else //need to pipeline balance if parm + begin + if (C_MULT_TYPE < 2) + begin + if ((intCE == 1 && slice_rfd == 0) || a_slice_load == 1) + a_load <= a_reg; + end + end + end + end + + //Accumulate result + always@(posedge intCLK) + begin + if (intSCLR == 1) + begin + accum_out <= `accumall0s; + accum_store <= `storeall0s; + end + else if (intCE == 1 && intACLR != 1) + begin + if (accum_store_width > C_BAAT) + //accum_store[accum_store_width-1-C_BAAT+temp_accum : 0] <= accum_store[accum_store_width-1+temp_accum : C_BAAT]; + accum_store[ncelab_accum_store_high-1 : 0] <= accum_store[accum_store_width-1+temp_accum : ncelab_accum_store_low]; + accum_store[accum_store_width-1 : accum_store_width-C_BAAT] <= accum_out[C_BAAT-1 : 0]; + if (accum_load == 1) + accum_out <= accum_in; + else + accum_out <= accum_in + accum_feedback; + end + end + + //Feedback accumulator output + always@(accum_out) + begin + accum_feedback[accum_width-C_BAAT-1 : 0] <= accum_out[accum_width-1 : C_BAAT]; + if (C_B_TYPE == `c_signed) + begin + for(i = 0; i < C_BAAT; i = i + 1) + accum_feedback[accum_width-1-i] <= accum_out[accum_width-1]; + end + else + begin + for(i = 0; i < C_BAAT; i = i + 1) + accum_feedback[accum_width-1-i] <= 0; + end + end + + //accum_in + always@(mult_out or accum_sign) + begin + if (accum_sign_needed == 1) + begin + if (C_B_TYPE == `c_signed) + accum_in[accum_mult_width-1] = mult_out[accum_mult_width-2+temp_mult_out]; + else if (mult_has_a_signed == 1) + accum_in[accum_mult_width-1] = accum_sign & mult_out[accum_mult_width-2+temp_mult_out]; + end + else + accum_in[accum_mult_width-1] = mult_out[mult_width-1]; + end + + always@(mult_out) + begin + if (accum_mult_width > 1) + accum_in[accum_mult_width-2+temp_mult_out : 0] = mult_out[accum_mult_width-2+temp_mult_out :0]; + end + + //accum_sign + always@(posedge intCLK) + begin + if (intSCLR == 1) + begin + if (real_latency > 0) + accum_sign_pipe <= `accumsignpipeall0s; + end + else if (intCE == 1 && intACLR != 1) + begin + if (real_latency > 1) + accum_sign_pipe[C_LATENCY-1+(accum_sign_pipe_rubbish2) : 1] <= accum_sign_pipe[C_LATENCY-2+(accum_sign_pipe_rubbish2) : 0]; + if (real_latency > 0) + accum_sign_pipe[0] <= mult_signed; + end + end + + //accum_complete + always@(accum_out or accum_store) + begin + accum_complete[accum_width+accum_store_width-1 : accum_store_width] = accum_out[accum_width-1 : 0]; //removed padding + accum_complete[accum_store_width-1 : 0] = accum_store; + end + + //O generation + always@(accum_complete or accum_mult_out_msb_delayed) + begin + if (C_OUT_WIDTH <= C_A_WIDTH+C_B_WIDTH+C_HAS_A_SIGNED) //accum_width+accum_store_width-padding) + //intO <= accum_complete[C_A_WIDTH+C_B_WIDTH+C_HAS_A_SIGNED-1 : C_A_WIDTH+C_B_WIDTH+C_HAS_A_SIGNED-C_OUT_WIDTH]; + intO[ncelab_into_high-1:0] <= accum_complete[C_A_WIDTH+C_B_WIDTH+C_HAS_A_SIGNED-1 : ncelab_accum_complete_low]; + else + begin + intO[C_A_WIDTH+C_B_WIDTH+C_HAS_A_SIGNED-1-intO_rubbish : 0] <= accum_complete[C_A_WIDTH+C_B_WIDTH+C_HAS_A_SIGNED-1-intO_rubbish : 0]; + if (accum_sign_needed == 1) + begin + if (C_B_TYPE == `c_signed) + begin + for (i = 0; i < (C_OUT_WIDTH-(C_A_WIDTH+C_B_WIDTH+C_HAS_A_SIGNED)); i = i+1) + intO[C_OUT_WIDTH-1-i] <= accum_complete[accum_width+accum_store_width-1]; //C_A_WIDTH+C_B_WIDTH+C_HAS_A_SIGNED-1]; + end + else + begin + for (i = 0; i < (C_OUT_WIDTH-(C_A_WIDTH+C_B_WIDTH+C_HAS_A_SIGNED)); i = i+1) + intO[C_OUT_WIDTH-1-i] <= accum_mult_out_msb_delayed; + end + end + else + begin + for (i = 0; i < (C_OUT_WIDTH-(C_A_WIDTH+C_B_WIDTH+C_HAS_A_SIGNED)); i = i+1) + intO[C_OUT_WIDTH-1-i] <= 0; + end + end + end + + function [C_B_WIDTH - 1 : 0] to_bitsB; + input [C_B_WIDTH*8 : 1] instring; + integer i; + integer non_null_string; + begin + non_null_string = 0; + for(i = C_B_WIDTH; i > 0; i = i - 1) + begin // Is the string empty? + if(instring[(i*8)] == 0 && + instring[(i*8)-1] == 0 && + instring[(i*8)-2] == 0 && + instring[(i*8)-3] == 0 && + instring[(i*8)-4] == 0 && + instring[(i*8)-5] == 0 && + instring[(i*8)-6] == 0 && + instring[(i*8)-7] == 0 && + non_null_string == 0) + non_null_string = 0; // Use the return value to flag a non-empty string + else + non_null_string = 1; // Non-null character! + end + if(non_null_string == 0) // String IS empty! Just return the value to be all '0's + begin + for(i = C_B_WIDTH; i > 0; i = i - 1) + to_bitsB[i-1] = 0; + end + else + begin + for(i = C_B_WIDTH; i > 0; i = i - 1) + begin // Is this character a '0'? (ASCII = 48 = 00110000) + if(instring[(i*8)] == 0 && + instring[(i*8)-1] == 0 && + instring[(i*8)-2] == 1 && + instring[(i*8)-3] == 1 && + instring[(i*8)-4] == 0 && + instring[(i*8)-5] == 0 && + instring[(i*8)-6] == 0 && + instring[(i*8)-7] == 0) + to_bitsB[i-1] = 0; + // Or is it a '1'? + else if(instring[(i*8)] == 0 && + instring[(i*8)-1] == 0 && + instring[(i*8)-2] == 1 && + instring[(i*8)-3] == 1 && + instring[(i*8)-4] == 0 && + instring[(i*8)-5] == 0 && + instring[(i*8)-6] == 0 && + instring[(i*8)-7] == 1) + to_bitsB[i-1] = 1; + // Or is it a ' '? (a null char - in which case insert a '0') + else if(instring[(i*8)] == 0 && + instring[(i*8)-1] == 0 && + instring[(i*8)-2] == 0 && + instring[(i*8)-3] == 0 && + instring[(i*8)-4] == 0 && + instring[(i*8)-5] == 0 && + instring[(i*8)-6] == 0 && + instring[(i*8)-7] == 0) + to_bitsB[i-1] = 0; + else + begin + $display("Error in %m at time %d ns: non-binary digit in string \"%s\"\nExiting simulation...",$time, instring); + $finish; + end + end + end + end + endfunction + +endmodule + +`undef c_set +`undef c_clear +`undef c_override +`undef c_no_override +`undef c_add +`undef c_sub +`undef c_add_sub +`undef c_signed +`undef c_unsigned +`undef c_pin +`undef c_distributed +`undef c_dp_block +`undef awidthall0s +`undef accumall0s +`undef storeall0s +`undef aloadall0s +`undef accumpipeall0s +`undef rfdpipeall0s +`undef multsignedpipeall0s +`undef accumsignpipeall0s +`undef intrdypipeall0s +`undef allUKs +`undef accumcompall0s +`undef outputall0s +`undef accumstoreall0s + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/MULT_GEN_V7_0.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/MULT_GEN_V7_0.v new file mode 100644 index 0000000..4a2763e --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/MULT_GEN_V7_0.v @@ -0,0 +1,168 @@ +// Copyright(C) 2004 by Xilinx, Inc. All rights reserved. +// This text contains proprietary, confidential +// information of Xilinx, Inc., is distributed +// under license from Xilinx, Inc., and may be used, +// copied and/or disclosed only pursuant to the terms +// of a valid license agreement with Xilinx, Inc. This copyright +// notice must be retained as part of this text at all times. + + +/* $Id: MULT_GEN_V7_0.v,v 1.13 2008/09/08 20:09:14 akennedy Exp $ +-- +-- Filename - MULT_GEN_V7_0.v +-- Author - Xilinx +-- Creation - 22 Mar 1999 +-- +-- Description - This file contains the Verilog behavior for the multiplier module +*/ + +`timescale 1ns/10ps +`define c_set 0 +`define c_clear 1 +`define c_override 0 +`define c_no_override 1 +`define c_add 0 +`define c_sub 1 +`define c_add_sub 2 +`define c_signed 0 +`define c_unsigned 1 +`define c_pin 2 +`define c_distributed 0 +`define c_dp_block 2 + +module MULT_GEN_V7_0 (A, B, CLK, A_SIGNED, CE, ACLR, + SCLR, LOADB, LOAD_DONE, SWAPB, RFD, + ND, RDY, O, Q); + + parameter BRAM_ADDR_WIDTH = 8; + parameter C_A_TYPE = `c_signed; + parameter C_A_WIDTH = 16; + parameter C_BAAT = 2; + parameter C_B_CONSTANT = `c_signed; + parameter C_B_TYPE = `c_signed; + parameter C_B_VALUE = "0000000000000001"; + parameter C_B_WIDTH = 16; + parameter C_ENABLE_RLOCS = 1; + parameter C_HAS_ACLR = 0; + parameter C_HAS_A_SIGNED = 0; + parameter C_HAS_B = 1; + parameter C_HAS_CE = 0; + parameter C_HAS_LOADB = 0; + parameter C_HAS_LOAD_DONE = 0; + parameter C_HAS_ND = 0; + parameter C_HAS_O = 0; + parameter C_HAS_Q = 1; + parameter C_HAS_RDY = 0; + parameter C_HAS_RFD = 0; + parameter C_HAS_SCLR = 0; + parameter C_HAS_SWAPB = 0; + parameter C_MEM_INIT_PREFIX = "mem"; + parameter C_MEM_TYPE = 0; + parameter C_MULT_TYPE = 0; + parameter C_OUTPUT_HOLD = 0; + parameter C_OUT_WIDTH = 16; + parameter C_PIPELINE = 0; + parameter C_REG_A_B_INPUTS = 1; + parameter C_SQM_TYPE = 0; + parameter C_STACK_ADDERS = 0; + parameter C_STANDALONE = 0; + parameter C_SYNC_ENABLE = 0; + parameter C_USE_LUTS = 1; + parameter C_V2_SPEED = 1; + + parameter non_seq_cawidth = (C_BAAT == C_A_WIDTH ? (C_BAAT == 1 ? C_A_WIDTH+1 : C_A_WIDTH) : C_A_WIDTH); + parameter non_seq_cbaat = (C_BAAT == C_A_WIDTH ? 1 : C_BAAT); + parameter ser_seq_cawidth = (C_BAAT == C_A_WIDTH ? (C_BAAT == 1 ? C_A_WIDTH+1 : C_A_WIDTH) : (C_SQM_TYPE == 0 ? C_A_WIDTH : 1)); + parameter non_seq_cbwidth = (C_BAAT == C_A_WIDTH ? (C_B_WIDTH == 1 ? 2 : C_B_WIDTH) : C_B_WIDTH); + parameter non_seq_out_width = (C_BAAT == C_A_WIDTH ? 1 : C_OUT_WIDTH); + + parameter INT_C_SYNC_ENABLE = (C_HAS_CE == 1 ? C_SYNC_ENABLE : 0); + + parameter NEW_TYPE = C_MULT_TYPE; //(C_MULT_TYPE == 5 ? 1 : C_MULT_TYPE); + + input [(C_A_WIDTH-1-((C_A_WIDTH-1)*C_SQM_TYPE)) : 0] A; + input [C_B_WIDTH-1 : 0] B; + input CLK; + input CE; + input A_SIGNED; + input LOADB; + input SWAPB; + input ND; + input ACLR; + input SCLR; + output RFD; + output RDY; + output LOAD_DONE; + output [C_OUT_WIDTH-1 : 0] O; + output [C_OUT_WIDTH-1 : 0] Q; + + wire RFD_seq; + wire RFD_non_seq; + wire RDY_seq; + wire RDY_non_seq; + wire LOAD_DONE_seq; + wire LOAD_DONE_non_seq; + wire [non_seq_out_width-1 : 0] O_seq; + wire [C_OUT_WIDTH-1 : 0] O_non_seq; + wire [non_seq_out_width-1 : 0] Q_seq; + wire [C_OUT_WIDTH-1 : 0] Q_non_seq; + + wire [(2*C_A_WIDTH)-1:0] dummyA = A + A; + wire [ser_seq_cawidth-1:0] seqA = (C_BAAT == C_A_WIDTH ? (C_BAAT == 1 ? dummyA : A) : A); + + wire [(2*C_B_WIDTH)-1:0] dummyB = B + B; + wire [non_seq_cbwidth-1:0] seqB = (C_BAAT == C_A_WIDTH ? (C_B_WIDTH == 1 ? dummyB : B) : B); + + wire intLOADB = ((C_HAS_LOADB == 1 && C_MULT_TYPE > 2 && C_MULT_TYPE < 5) ? LOADB : 0); + wire intSWAPB = ((C_HAS_SWAPB == 1 && C_MULT_TYPE == 4) ? SWAPB : 0); + + wire RFD = (C_HAS_RFD == 1 ? (C_BAAT == C_A_WIDTH ? RFD_non_seq : RFD_seq) : 1'bx); + wire RDY = (C_HAS_RDY == 1 ? (C_BAAT == C_A_WIDTH ? RDY_non_seq : RDY_seq) : 1'bx); + wire LOAD_DONE = (C_HAS_LOAD_DONE == 1 ? (C_BAAT == C_A_WIDTH ? LOAD_DONE_non_seq : LOAD_DONE_seq) : 1'bx); + wire [C_OUT_WIDTH-1 : 0] O = (C_HAS_O == 1 ? (C_BAAT == C_A_WIDTH ? O_non_seq : O_seq) : 1'bx); + wire [C_OUT_WIDTH-1 : 0] Q = (C_HAS_Q == 1 ? (C_BAAT == C_A_WIDTH ? Q_non_seq : Q_seq) : 1'bx); + + MULT_GEN_V7_0_NON_SEQ #(BRAM_ADDR_WIDTH, C_A_TYPE, C_A_WIDTH, C_BAAT, C_B_CONSTANT, + C_B_TYPE, C_B_VALUE, C_B_WIDTH, C_ENABLE_RLOCS, C_HAS_ACLR, + C_HAS_A_SIGNED, C_HAS_B, C_HAS_CE, C_HAS_LOADB, C_HAS_LOAD_DONE, + C_HAS_ND, C_HAS_O, C_HAS_Q, C_HAS_RDY, C_HAS_RFD, C_HAS_SCLR, + C_HAS_SWAPB, C_MEM_INIT_PREFIX, C_MEM_TYPE, NEW_TYPE, C_OUTPUT_HOLD, + C_OUT_WIDTH, C_PIPELINE, 0, C_REG_A_B_INPUTS, C_SQM_TYPE, + C_STACK_ADDERS, C_STANDALONE, INT_C_SYNC_ENABLE, C_USE_LUTS, C_V2_SPEED) + non_seq_mult (.A(A), .B(B), .CLK(CLK), .A_SIGNED(A_SIGNED), .CE(CE), + .ACLR(ACLR), .SCLR(SCLR), .LOADB(intLOADB), + .LOAD_DONE(LOAD_DONE_non_seq), .SWAPB(intSWAPB), .RFD(RFD_non_seq), + .ND(ND), .RDY(RDY_non_seq), .O(O_non_seq), + .Q(Q_non_seq)); + + MULT_GEN_V7_0_SEQ #(BRAM_ADDR_WIDTH, C_A_TYPE, non_seq_cawidth, non_seq_cbaat, C_B_CONSTANT, + C_B_TYPE, C_B_VALUE, non_seq_cbwidth, C_ENABLE_RLOCS, C_HAS_ACLR, + C_HAS_A_SIGNED, C_HAS_B, C_HAS_CE, C_HAS_LOADB, C_HAS_LOAD_DONE, + C_HAS_ND, C_HAS_O, C_HAS_Q, C_HAS_RDY, C_HAS_RFD, C_HAS_SCLR, + C_HAS_SWAPB, C_MEM_INIT_PREFIX, C_MEM_TYPE, NEW_TYPE, C_OUTPUT_HOLD, + non_seq_out_width, C_PIPELINE, C_REG_A_B_INPUTS, C_SQM_TYPE, + C_STACK_ADDERS, C_STANDALONE, INT_C_SYNC_ENABLE, C_USE_LUTS) + seq_mult (.A(seqA), .B(seqB), .CLK(CLK), .A_SIGNED(A_SIGNED), .CE(CE), + .ACLR(ACLR), .SCLR(SCLR), .LOADB(intLOADB), + .LOAD_DONE(LOAD_DONE_seq), .SWAPB(intSWAPB), .RFD(RFD_seq), .ND(ND), + .RDY(RDY_seq), .O(O_seq), + .Q(Q_seq)); + + initial + begin + + end + +endmodule + +`undef c_set +`undef c_clear +`undef c_override +`undef c_no_override +`undef c_add +`undef c_sub +`undef c_add_sub +`undef c_signed +`undef c_unsigned +`undef c_pin + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/MULT_GEN_V7_0_NON_SEQ.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/MULT_GEN_V7_0_NON_SEQ.v new file mode 100644 index 0000000..aa803be --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/MULT_GEN_V7_0_NON_SEQ.v @@ -0,0 +1,2926 @@ +// Copyright(C) 2004 by Xilinx, Inc. All rights reserved. +// This text contains proprietary, confidential +// information of Xilinx, Inc., is distributed +// under license from Xilinx, Inc., and may be used, +// copied and/or disclosed only pursuant to the terms +// of a valid license agreement with Xilinx, Inc. This copyright +// notice must be retained as part of this text at all times. + + +/* $Id: +-- +-- Filename - MULT_GEN_V7_0_NON_SEQ.v +-- Author - Xilinx +-- Creation - 22 Mar 1999 +-- +-- Description - This file contains the Verilog behavior for the +-- non-sequential multiplier module +*/ + +`timescale 1ns/10ps + +`define c_set 0 +`define c_clear 1 +`define c_override 0 +`define c_no_override 1 +`define c_add 0 +`define c_sub 1 +`define c_add_sub 2 +`define c_signed 0 +`define c_unsigned 1 +`define c_pin 2 +`define c_distributed 0 +`define c_dp_block 2 +`define allUKs {(C_OUT_WIDTH)+1{1'bx}} +`define all0s {(C_OUT_WIDTH)+1{1'b0}} +`define ball0s {(C_B_WIDTH)+1{1'b0}} +`define ballxs {(C_B_WIDTH)+1{1'bx}} +`define aall0s {(C_BAAT+C_HAS_A_SIGNED)+1{1'b0}} +`define aall1s {(C_BAAT+C_HAS_A_SIGNED)+1{1'b1}} +`define aallxs {(C_BAAT+C_HAS_A_SIGNED)+1{1'bx}} +`define inall0s {(C_A_WIDTH-1-((C_A_WIDTH-1)*C_SQM_TYPE))+1{1'b0}} +`define baatall0s {(C_BAAT)+1{1'b0}} +`define baatall1s {(C_BAAT)+1{1'b1}} +`define baatallxs {(C_BAAT)+1{1'bx}} + +module MULT_GEN_V7_0_NON_SEQ (A, B, CLK, A_SIGNED, CE, ACLR, + SCLR, LOADB, LOAD_DONE, SWAPB, RFD, + ND, RDY, O, Q); + + parameter BRAM_ADDR_WIDTH = 8; + parameter C_A_TYPE = `c_signed; + parameter C_A_WIDTH = 16; + parameter C_BAAT = 2; + parameter C_B_CONSTANT = `c_signed; + parameter C_B_TYPE = `c_signed; + parameter C_B_VALUE = "0000000000000001"; + parameter C_B_WIDTH = 16; + parameter C_ENABLE_RLOCS = 1; + parameter C_HAS_ACLR = 0; + parameter C_HAS_A_SIGNED = 0; + parameter C_HAS_B = 1; + parameter C_HAS_CE = 0; + parameter C_HAS_LOADB = 0; + parameter C_HAS_LOAD_DONE = 0; + parameter C_HAS_ND = 0; + parameter C_HAS_O = 0; + parameter C_HAS_Q = 1; + parameter C_HAS_RDY = 0; + parameter C_HAS_RFD = 0; + parameter C_HAS_SCLR = 0; + parameter C_HAS_SWAPB = 0; + parameter C_MEM_INIT_PREFIX = "mem"; + parameter C_MEM_TYPE = 0; + parameter C_MULT_TYPE = 0; + parameter C_OUTPUT_HOLD = 0; + parameter C_OUT_WIDTH = 16; + parameter C_PIPELINE = 0; + parameter C_PRE_DELAY = 0; + parameter C_REG_A_B_INPUTS = 1; + parameter C_SQM_TYPE = 0; + parameter C_STACK_ADDERS = 0; + parameter C_STANDALONE = 0; + parameter C_SYNC_ENABLE = 0; + parameter C_USE_LUTS = 1; + + //Internal parameters + + parameter incA = (((C_HAS_A_SIGNED == 1 || C_A_TYPE == `c_signed) && C_B_TYPE == `c_unsigned) ? 1 : 0) ; + parameter incB = (C_B_TYPE == `c_signed ? 1 : 0) ; + parameter inc = ((C_B_TYPE == `c_unsigned && C_A_TYPE == `c_unsigned) ? 0 : 1) ; + parameter dec = ((C_B_TYPE == `c_unsigned && C_A_TYPE == `c_unsigned) ? 1 : 0) ; + parameter inc_a_width = ((C_BAAT < C_A_WIDTH && (C_HAS_A_SIGNED == 1 || C_A_TYPE == `c_signed) && C_HAS_LOADB == 0) ? 1 : 0) ; + parameter decrement = ((C_HAS_A_SIGNED == 1 || (C_A_TYPE == `c_signed && C_BAAT < C_A_WIDTH)) ? 1 : 0) ; + + //Parameters to calculate the latency for the parallel multiplier. + parameter a_ext_width_par = (C_HAS_A_SIGNED == 1 ? C_BAAT+1 : C_BAAT) ; + parameter a_ext_width_seq = ((C_HAS_A_SIGNED == 1 || C_A_TYPE == `c_signed) ? C_BAAT+1 : C_BAAT) ; + parameter a_ext_width = (C_BAAT < C_A_WIDTH ? a_ext_width_seq : a_ext_width_par) ; + + /* Compare the width of the A port, to the width of the B port + If the A port is smaller, then swap these over, otherwise leave + alone */ + + parameter a_t_2 = (C_A_TYPE == `c_pin ? `c_signed : C_A_TYPE); + + parameter a_w = (C_A_WIDTH < C_B_WIDTH ? C_B_WIDTH : a_ext_width); + parameter a_t = (C_A_WIDTH < C_B_WIDTH ? C_B_TYPE : a_t_2); + parameter b_w = (C_A_WIDTH < C_B_WIDTH ? a_ext_width : C_B_WIDTH); + parameter b_t = (C_A_WIDTH < C_B_WIDTH ? a_t_2 : C_B_TYPE); + + // The mult18 parameter signifies if the final mult18x18 primitive is used + // without having to pad with zeros, or sign extending - thus leading to + // a more efficient implementation - e.g. a 35x35 (signed x signed) multiplier + // mult18, is used in the calculation of a_prods and b_prods, which indicate + // how many mult18x18 primitives are requred. + + //parameter mult18 = (((a_t == `c_signed && a_w % 17 == 1) + // && ((b_t == `c_signed && b_w <= a_w) || (b_t == `c_unsigned && b_w < a_w)) && (b_w % 18 != 0)) ? 1 : 0); + parameter mult18a = (a_t == `c_signed && a_w % 17 == 1); + parameter mult18b = (b_t == `c_signed && b_w % 17 == 1); + + parameter a_prods = ((a_w-1)/(17+mult18a)) + 1; //(a_ext_width-1)/(17 + mult18a) + 1 ; + parameter b_prods = ((b_w-1)/(17+mult18b)) + 1; //(C_B_WIDTH-1)/(17 + mult18b) + 1 ; + parameter a_count = (a_ext_width+1)/2 ; + parameter b_count = (C_B_WIDTH+1)/2 ; + parameter parm_numAdders = ((C_MULT_TYPE == 1 || C_MULT_TYPE == 5) ? (a_prods*b_prods) : ((a_ext_width <= C_B_WIDTH) ? a_count : b_count)) ; + parameter ignore_nd = ((C_HAS_ND == 0 || (C_HAS_ND == 1 && C_REG_A_B_INPUTS == 0 && C_HAS_Q == 0 && (C_PIPELINE == 0 || parm_numAdders == 1))) ? 1 : 0); + parameter true_ce = (C_HAS_CE == 1 ? 1 : (ignore_nd == 1 ? 0 : 1)); + parameter mult18s = (C_MULT_TYPE == 5 ? 1 : (C_MULT_TYPE != 1 ? 0 : ((C_HAS_ACLR == 0 && (~(C_SYNC_ENABLE == 1 && C_HAS_SCLR == 1 && true_ce == 1))) ? 1 : 0))); + + //Parameters to calculate the latency for the constant coefficient multiplier. + parameter rom_addr_width = (C_MEM_TYPE == `c_distributed ? 4 : BRAM_ADDR_WIDTH) ; + parameter sig_addr_bits = (C_BAAT >= rom_addr_width ? rom_addr_width : C_BAAT) ; + parameter effective_op_width = ((C_BAAT == C_A_WIDTH && (C_HAS_A_SIGNED == 0 || C_HAS_LOADB == 1)) ? C_BAAT : ((C_BAAT == C_A_WIDTH) ? C_BAAT+1 : (C_BAAT < C_A_WIDTH ? C_BAAT+inc_a_width : C_BAAT+1))) ; + parameter a_input_width = ((effective_op_width % rom_addr_width == 0) ? effective_op_width : effective_op_width + rom_addr_width - (effective_op_width % rom_addr_width)) ; + parameter mod = a_input_width % rom_addr_width ; + parameter op_width = (mod == 0 ? a_input_width : (a_input_width + rom_addr_width) - mod) ; + parameter a_width = (C_BAAT < C_A_WIDTH ? C_A_WIDTH : op_width) ; + parameter need_addsub = ((C_HAS_LOADB == 1 && (C_A_TYPE == `c_signed || C_HAS_A_SIGNED == 1)) ? 1 : 0) ; + parameter ccm_numAdders_1 = (mod == 0 ? (a_input_width/rom_addr_width) : (a_input_width/rom_addr_width)+1) ; + parameter need_0_minus_pp = ((need_addsub == 1 && ccm_numAdders_1 <= 1) ? 1 : 0) ; + parameter ccm_numAdders = (need_0_minus_pp == 1 ? 1 : ccm_numAdders_1 - 1) ; + parameter ccm_init1 = ((C_HAS_LOADB == 1 && C_MEM_TYPE == `c_dp_block) ? 1 : 0) ; + parameter ccm_init2 = ((C_HAS_LOADB == 1 && (C_A_TYPE == `c_signed || C_HAS_A_SIGNED == 1) && C_PIPELINE == 1) ? 1 : 0) ; + parameter ccm_init3 = (((ccm_numAdders > 0 || C_HAS_SWAPB == 1) && (C_PIPELINE == 1 || C_MEM_TYPE == `c_dp_block)) ? 1 : 0) ; + parameter ccm_init4 = ((ccm_numAdders > 0 && C_HAS_SWAPB == 1 && C_PIPELINE == 1) ? 1 : 0) ; + parameter ccm_initial_latency = ccm_init1 + ccm_init2 + ccm_init3 + ccm_init4 ; + + //Latency calculation + parameter numAdders = ((C_MULT_TYPE < 2 || C_MULT_TYPE == 5) ? parm_numAdders - 1 : ccm_numAdders) ; + parameter log = (C_PIPELINE == 1 ? (numAdders < 2 ? 0 : (numAdders < 4 ? 1 : (numAdders < 8 ? 2 : (numAdders < 16 ? 3 : (numAdders < 32 ? 4 : (numAdders < 64 ? 5 : (numAdders < 128 ? 6 : 7))))))) : 0) ; + parameter C_LATENCY_sub1 = (C_MULT_TYPE < 2 ? (numAdders > 0 ? (mult18s + log + 1) : (C_PIPELINE == 1 ? mult18s : 0)) : (numAdders > 0 ? (ccm_initial_latency + log) : ccm_initial_latency)) ; + parameter C_LATENCY_V4 = (C_PIPELINE == 1 ? (parm_numAdders + 1) : 0); + parameter C_LATENCY_sub = (C_MULT_TYPE == 5 ? C_LATENCY_V4 : C_LATENCY_sub1); + parameter C_LATENCY = (C_PIPELINE == 1 ? C_LATENCY_sub : (C_MULT_TYPE < 2 ? 0 : C_LATENCY_sub)) ; + + parameter MULT_TYPE = (C_MULT_TYPE == 5 ? 1 : C_MULT_TYPE); + parameter c_pipe = (C_PIPELINE == 1 || C_LATENCY > 0) ? 1 : 0 ; + + parameter multWidth = C_A_WIDTH+C_B_WIDTH+decrement+1 ; + parameter rfd_stages = 1; + + parameter no_aclr = (MULT_TYPE == 2 && (C_HAS_Q == 0 || (numAdders == 0 && C_MEM_TYPE == 2)) && + C_REG_A_B_INPUTS == 0 && C_HAS_RFD == 0 && + (C_LATENCY == 0 || (numAdders == 1 && C_MEM_TYPE == 2) || (C_LATENCY == 1 && + C_PIPELINE == 0 && C_MEM_TYPE == 2 && MULT_TYPE == 2)) && + ~(C_B_WIDTH == 1 && MULT_TYPE == 2 && C_HAS_Q == 1 && C_MEM_TYPE == 2) ? 1 : 0); + + parameter ncelab_inta_high = ((C_A_WIDTH == C_BAAT) ? C_A_WIDTH : (C_SQM_TYPE == 0 ? C_A_WIDTH : 1)); + + `define mall0s {(multWidth)+1{1'b0}} + `define mallUKs {(multWidth)+1{1'bx}} + + input [(C_A_WIDTH-1-((C_A_WIDTH-1)*C_SQM_TYPE)) : 0] A; + input [C_B_WIDTH-1 : 0] B; + input CLK; + input CE; + input A_SIGNED; + input LOADB; + input SWAPB; + input ND; + input ACLR; + input SCLR; + output RFD; + output RDY; + output LOAD_DONE; + output [C_OUT_WIDTH-1 : 0] O; + output [C_OUT_WIDTH-1 : 0] Q; + + // Internal values to drive signals when input is missing + wire [C_B_WIDTH-1 : 0] intBconst; + reg [C_B_WIDTH-1 : 0] intB; + reg [(C_A_WIDTH-1-((C_A_WIDTH-1)*C_SQM_TYPE)) : 0] intA; + wire [C_B_WIDTH-1 : 0] regB; + wire [C_B_WIDTH-1 : 0] regB_cased; + wire [(C_A_WIDTH-1-((C_A_WIDTH-1)*C_SQM_TYPE)) : 0] regA; + wire [C_B_WIDTH-1 : 0] B_DLY_1; + wire [C_B_WIDTH-1 : 0] B_DLY_2; + wire LOADB_DLY_1; + wire LOADB_DLY_2; + wire SWAPB_DLY_1; + wire SWAPB_DLY_2; + reg [C_B_WIDTH-1 : 0] b_const0; + reg [C_B_WIDTH-1 : 0] b_const1; + reg [C_B_WIDTH-1 : 0] loadb_value ; + reg [C_B_WIDTH-1 : 0] B_INPUT; + + wire intCE; + wire intCE_cased; + reg intA_SIGNED; + wire regA_SIGNED; + reg intACLR; + reg intSCLR; + wire ND_I; + wire [(C_A_WIDTH-1-((C_A_WIDTH-1)*C_SQM_TYPE)) : 0] A_I; + wire [C_B_WIDTH-1 : 0] B_I; + wire LOADB_I; + wire SWAPB_I; + wire initial_intCLK; + reg intCLK; + reg last_clk; + wire intLOADB; + wire intLOADB_no_predelay; + reg loaded; + wire intSWAPB; + reg regND_nonseq; + wire regND_ccm; + wire regND_parm; + wire regND; + wire intND ; + wire intRDY; + reg intRDY_rl; + wire intRDY_rl_pre_reg; + reg intRFD; + reg intRFD_rel; + reg regRFD ; + reg regRDY ; + reg intLOAD_DONE; + reg [C_OUT_WIDTH-1 : 0 ] O_I; + reg [C_OUT_WIDTH-1 : 0 ] Q_I; + reg RDY_I; + reg [C_OUT_WIDTH-1 : 0 ] intO; + reg lastCLK; + reg [C_BAAT-1 : 0] max_a_val ; + reg power_2; + + reg [multWidth-1 : 0] a_value ; + reg [multWidth-1 : 0] b_value ; + reg [multWidth-1 : 0] max_result ; + reg [multWidth : 0] max_result1 ; + reg [multWidth : 0] max_result2 ; + + reg [C_OUT_WIDTH-1 : 0] intQpipe [C_LATENCY+1 : 0]; + reg [C_LATENCY : 0] intRDYpipe; + + // Output ports. + wire [C_OUT_WIDTH-1 : 0] Q; + wire [C_OUT_WIDTH-1 : 0] O; + wire RDY; + wire RFD; + wire LOAD_DONE; + + // Assign values to the output ports after a delay. + assign #1 Q = (C_HAS_Q == 1 ? Q_I : `allUKs); + assign #1 O = (C_HAS_O == 1 ? O_I : `allUKs); + assign #1 RDY = (C_HAS_RDY == 1 ? (C_HAS_ND == 1 ? (C_HAS_Q == 1 ? regRDY : RDY_I) : 1) : 1'bx); + assign #1 RFD = (C_HAS_RFD == 1 ? intRFD : 1'bx); + assign #1 LOAD_DONE = (C_HAS_LOAD_DONE == 1 ? intLOAD_DONE : 1'bx); + + // Sort out default values for missing ports + assign regND = regND_nonseq; + assign intCE = (C_HAS_CE == 1 ? CE : 1); + assign intCE_cased = ((C_HAS_CE == 1 && C_HAS_ND == 1) ? + (C_SYNC_ENABLE == 1 ? ((~intLOAD_DONE) | (intCE & ND_I)) + : ((~intLOAD_DONE) | (intCE & ND_I) | intSCLR)) + : (C_HAS_ND == 1 ? + (C_SYNC_ENABLE == 1 ? ((~intLOAD_DONE) | ND_I) + : ((~intLOAD_DONE) | ND_I | intSCLR)) + : 1'b1)); + assign initial_intCLK = CLK; + assign intND = ((C_HAS_ND == 1 && ND !== 1'bz) ? ND : 1); + + assign intLOADB = ((C_HAS_LOADB == 1 && MULT_TYPE > 2) ? LOADB_I : 0) ; + assign intLOADB_no_predelay = ((C_HAS_LOADB == 1 && MULT_TYPE > 2) ? LOADB : 0); + assign intSWAPB = ((C_HAS_SWAPB == 1 && MULT_TYPE > 2) ? SWAPB_I : 0) ; + + //assign intSCLR = (C_HAS_SCLR == 1 ? SCLR : 0); + assign ND_I = ((C_HAS_ND == 1 && ND !== 1'bz) ? ND : 1); + assign A_I = A; + assign B_I = (C_PRE_DELAY == 0 ? B : (C_PRE_DELAY == 1 ? B_DLY_1 : B_DLY_2)); + assign SWAPB_I = (C_PRE_DELAY == 0 ? SWAPB : (C_PRE_DELAY == 1 ? SWAPB_DLY_1 : SWAPB_DLY_2)); + assign LOADB_I = (C_PRE_DELAY == 0 ? LOADB : (C_PRE_DELAY == 1 ? LOADB_DLY_1 : LOADB_DLY_2)); + + assign intRDY_rl_pre_reg = intND & intLOAD_DONE; + assign intRDY = (MULT_TYPE == 3 ? (C_REG_A_B_INPUTS == 0 ? ND_I & intLOAD_DONE : intRDY_rl) + : (MULT_TYPE > 1 ? (C_REG_A_B_INPUTS == 0 ? ND_I : regND) + : ((C_LATENCY+C_REG_A_B_INPUTS == 0 || (C_LATENCY == 1 && C_REG_A_B_INPUTS == 0 && C_HAS_Q == 0)) ? ND_I & intCE + : ((C_LATENCY == 0 && C_REG_A_B_INPUTS == 1 && C_HAS_Q == 0) ? regND_ccm : regND & intCE)))); + + integer j, k, test1, msb; + integer pipe, pipe1; + integer i; + integer cycle, loadb_count, loadb_count_no_predelay, loadb_count_dly, loadb_count_dly_int, out_width, tmp_out_width, b_is_negative, b_width, new_data_present; + integer stay_x, bank_sel, bank_sel_pre, loadb_delay, pre_delay_comp ; + integer shift_bits, real_latency ; + integer loading, cycle_discarded, b_is_zero, b_is_one, a_negative, b_negative ; + + reg [C_B_WIDTH-1 : 0] initB_INPUT; + reg [multWidth-1 : 0] tmpA; + reg [multWidth-1 : 0] tmpB; + reg [multWidth-1 : 0] tmpAB; + reg tmpA_SIGNED ; + + reg [multWidth-1 : 0] one; + reg [multWidth-1 : 0] zero ; + reg cleared; + + reg [multWidth-1 : 0] product ; + reg [multWidth-1 : 0] product_delayed ; + reg [C_LATENCY : 0] intPRODUCTpipe [multWidth-1 : 0] ; + + //Input registers. + C_REG_FD_V7_0 #("0", C_ENABLE_RLOCS, C_HAS_ACLR, 0, 0, + C_HAS_CE, C_HAS_SCLR, 0, 0, + "0", C_SYNC_ENABLE, 0, (C_A_WIDTH-1-((C_A_WIDTH-1)*C_SQM_TYPE))+1) + rega (.D(A_I), .CLK(intCLK), .CE(intCE), .ACLR(intACLR), .ASET(1'b0), + .AINIT(1'b0), .SCLR(intSCLR), .SSET(1'b0), .SINIT(1'b0), + .Q(regA)); + + C_REG_FD_V7_0 #("0", C_ENABLE_RLOCS, C_HAS_ACLR, 0, 0, + C_HAS_CE, C_HAS_SCLR, 0, 0, + "0", C_SYNC_ENABLE, 0, C_B_WIDTH) + regad1 (.D(B), .CLK(intCLK), .CE(intCE), .ACLR(intACLR), .ASET(1'b0), + .AINIT(1'b0), .SCLR(intSCLR), .SSET(1'b0), .SINIT(1'b0), + .Q(B_DLY_1)); + + C_REG_FD_V7_0 #("0", C_ENABLE_RLOCS, C_HAS_ACLR, 0, 0, + C_HAS_CE, C_HAS_SCLR, 0, 0, + "0", C_SYNC_ENABLE, 0, C_B_WIDTH) + regad2 (.D(B_DLY_1), .CLK(intCLK), .CE(intCE), .ACLR(intACLR), .ASET(1'b0), + .AINIT(1'b0), .SCLR(intSCLR), .SSET(1'b0), .SINIT(1'b0), + .Q(B_DLY_2)); + + C_REG_FD_V7_0 #("0", C_ENABLE_RLOCS, C_HAS_ACLR, 0, 0, + C_HAS_CE, C_HAS_SCLR, 0, 0, + "0", C_SYNC_ENABLE, 0, 1) + regswapb1 (.D(SWAPB), .CLK(intCLK), .CE(intCE), .ACLR(intACLR), .ASET(1'b0), + .AINIT(1'b0), .SCLR(intSCLR), .SSET(1'b0), .SINIT(1'b0), + .Q(SWAPB_DLY_1)); + + C_REG_FD_V7_0 #("0", C_ENABLE_RLOCS, C_HAS_ACLR, 0, 0, + C_HAS_CE, C_HAS_SCLR, 0, 0, + "0", C_SYNC_ENABLE, 0, 1) + regswapb2 (.D(SWAPB_DLY_1), .CLK(intCLK), .CE(intCE), .ACLR(intACLR), .ASET(1'b0), + .AINIT(1'b0), .SCLR(intSCLR), .SSET(1'b0), .SINIT(1'b0), + .Q(SWAPB_DLY_2)); + + C_REG_FD_V7_0 #("0", C_ENABLE_RLOCS, C_HAS_ACLR, 0, 0, + C_HAS_CE, C_HAS_SCLR, 0, 0, + "0", C_SYNC_ENABLE, 0, 1) + regloadb1 (.D(LOADB), .CLK(intCLK), .CE(intCE), .ACLR(intACLR), .ASET(1'b0), + .AINIT(1'b0), .SCLR(intSCLR), .SSET(1'b0), .SINIT(1'b0), + .Q(LOADB_DLY_1)); + + C_REG_FD_V7_0 #("0", C_ENABLE_RLOCS, C_HAS_ACLR, 0, 0, + C_HAS_CE, C_HAS_SCLR, 0, 0, + "0", C_SYNC_ENABLE, 0, 1) + regloadb2 (.D(LOADB_DLY_1), .CLK(intCLK), .CE(intCE), .ACLR(intACLR), .ASET(1'b0), + .AINIT(1'b0), .SCLR(intSCLR), .SSET(1'b0), .SINIT(1'b0), + .Q(LOADB_DLY_2)); + + C_REG_FD_V7_0 #("0", C_ENABLE_RLOCS, C_HAS_ACLR, 0, 0, + C_HAS_CE, C_HAS_SCLR, 0, 0, + "0", C_SYNC_ENABLE, 0, C_B_WIDTH) + regb (.D(B_INPUT), .CLK(intCLK), .CE(intCE), .ACLR(intACLR), .ASET(1'b0), + .AINIT(1'b0), .SCLR(intSCLR), .SSET(1'b0), .SINIT(1'b0), + .Q(regB)); + + C_REG_FD_V7_0 #("0", C_ENABLE_RLOCS, C_HAS_ACLR, 0, 0, + 1, C_HAS_SCLR, 0, 0, + "0", C_SYNC_ENABLE, 0, C_B_WIDTH) + regb_cased (.D(B_INPUT), .CLK(intCLK), .CE(intCE_cased), .ACLR(intACLR), .ASET(1'b0), + .AINIT(1'b0), .SCLR(intSCLR), .SSET(1'b0), .SINIT(1'b0), + .Q(regB_cased)); + + C_REG_FD_V7_0 #("0", C_ENABLE_RLOCS, C_HAS_ACLR, 0, 0, + C_HAS_CE, C_HAS_SCLR, 0, 0, + "0", C_SYNC_ENABLE, 0, 1) + regnd (.D(ND), .CLK(intCLK), .CE(intCE), .ACLR(intACLR), .ASET(1'b0), + .AINIT(1'b0), .SCLR(intSCLR), .SSET(1'b0), .SINIT(1'b0), + .Q(regND_ccm)); + + C_REG_FD_V7_0 #("0", C_ENABLE_RLOCS, C_HAS_ACLR, 0, 0, + 0, C_HAS_SCLR, 0, 0, + "0", C_SYNC_ENABLE, 0, 1) + regndparm (.D(ND), .CLK(intCLK), .CE(intCE), .ACLR(intACLR), .ASET(1'b0), + .AINIT(1'b0), .SCLR(intSCLR), .SSET(1'b0), .SINIT(1'b0), + .Q(regND_parm)); + + C_REG_FD_V7_0 #("0", C_ENABLE_RLOCS, C_HAS_ACLR, 0, 0, + C_HAS_CE, C_HAS_SCLR, 0, 0, + "0", C_SYNC_ENABLE, 0, 1) + regasig (.D(A_SIGNED), .CLK(intCLK), .CE(intCE), .ACLR(intACLR), .ASET(1'b0), + .AINIT(1'b0), .SCLR(intSCLR), .SSET(1'b0), .SINIT(1'b0), + .Q(regA_SIGNED)); + + initial + begin + B_INPUT = (MULT_TYPE < 2) ? B : to_bitsB(C_B_VALUE); + if (MULT_TYPE > 2 && C_B_TYPE == `c_signed) + begin + j = 0 ; + msb = 0 ; + //Find the length of the C_B_VALUE string + for(i = 0; i < (C_B_WIDTH*8); i = i + 1) + begin + if(C_B_VALUE[i] == 0 || C_B_VALUE[i] == 1) + msb = i/8 ; + end + //Pad it with 1's if it is signed and negative. + for(i = msb; i < C_B_WIDTH; i = i + 1) + begin + B_INPUT[i] = B_INPUT[msb]; + end + end + //Initialise all the signals that need to be initialised at start up. + intRFD = 1 ; + regRFD = 1 ; + loading = 0 ; + intRFD_rel = 1; + + if (C_HAS_ND == 1 && C_BAAT == C_A_WIDTH) + begin + regRDY = 0; + RDY_I = 0; + intRDY_rl = 0; + end + else + begin + regRDY = 1; + RDY_I = 1; + intRDY_rl = 1; + end + + O_I = `all0s; + bank_sel = 0 ; + bank_sel_pre = 0; + b_const0 = B_INPUT ; + b_const1 = B_INPUT ; + loadb_value = B_INPUT ; + intB = B_INPUT ; + tmpB = B_INPUT ; + intLOAD_DONE = 1 ; + loadb_count = -1 ; + loadb_count_no_predelay = -1; + loaded = 0 ; + stay_x = 0; + tmpA = `aallxs; + //tmpAB = `mall0s; + intACLR = 0; + intSCLR = 0; + cleared = 0; + + if (C_HAS_ND == 0) + begin + for(k = 0 ; k <= C_LATENCY; k = k + 1) + begin + intRDYpipe[k] = 1 ; + end + end + else if (C_HAS_ND == 1) + begin + for(k = 0 ; k <= C_LATENCY; k = k + 1) + begin + intRDYpipe[k] = 0 ; + end + end + initB_INPUT = (MULT_TYPE < 2) ? B : to_bitsB(C_B_VALUE); + new_data_present = 0 ; + + //Clear the pipeline and the inputs if there are registers involved. + for(j = 0; j < multWidth; j = j + 1) + begin + if (C_REG_A_B_INPUTS == 1) + begin + intA[j] = 0 ; + tmpA[j] = 0 ; + if(MULT_TYPE < 2) + begin + intB[j] = 0 ; + tmpB[j] = 0 ; + end + end + end + for (j = 0; j <= C_LATENCY; j = j + 1) + begin + intQpipe[j] = `all0s ; + end + + for(i = 0; i < multWidth; i = i + 1) + begin + if (i > 0) + begin + one[i] = 0 ; + zero[i] = 0 ; + end + else + begin + one[i] = 1 ; + zero[i] = 0 ; + end + end + + if (MULT_TYPE > 2) + begin + loadb_delay = 1 ; + for(i = 0; i < sig_addr_bits; i = i + 1) + begin + loadb_delay = 2*loadb_delay ; + end + loadb_delay = loadb_delay-1 ; + if (C_PRE_DELAY == 0) + pre_delay_comp = 0; + else if (C_PRE_DELAY == 1) + pre_delay_comp = 1; + else if (C_PRE_DELAY == 2 && loadb_delay > 1) + pre_delay_comp = 2; + else + pre_delay_comp = loadb_delay; + end + + //Find the real b input width + if (MULT_TYPE > 1 && C_HAS_LOADB == 0) + begin + b_width = 0 ; + for(i = 0; i < C_B_WIDTH; i = i + 1) + begin + if(initB_INPUT[i] == 1) + b_width = i+1 ; + end + end + else + begin + b_width = C_B_WIDTH ; + end + + //Calculate the output width of the multiplier. + a_negative = 0 ; + b_negative = 0 ; + + power_2 = 1'b1; + for (i = 0; i < C_B_WIDTH; i = i + 1) + begin + if ((initB_INPUT[i] == 1) && (i!=C_B_WIDTH-1)) + power_2 = 1'b0; + end + + if (C_A_TYPE == `c_signed) + begin + a_negative = 1 ; + max_a_val = `aall0s ; + max_a_val[C_BAAT-1] = 1; + end + else + begin + max_a_val = `aall1s ; + end + + if ((initB_INPUT[b_width-1] == 1) && (C_B_TYPE == `c_signed)) + b_negative = 1 ; + + for (i = 0; i < b_width; i = i + 1) + begin + if ((initB_INPUT[b_width-1] == 1) && (C_B_TYPE == `c_signed)) + begin + b_value[i] = ~initB_INPUT[i] ; + end + else + begin + b_value[i] = initB_INPUT[i] ; + end + end + + for (i = 0; i < C_BAAT; i = i + 1) + begin + a_value[i] = max_a_val[i] ; + end + for (i = C_BAAT; i < multWidth; i = i + 1) + begin + if(a_negative == 1 && power_2 ==1 ) + a_value[i] = 1 ; + else + a_value[i] = 0 ; + end + + for (i = b_width; i < multWidth; i = i + 1) + begin + if (C_B_TYPE == `c_signed && b_value[b_width-1] == 1) + begin + b_value[i] = 1 ; + end + else + begin + b_value[i] = 0 ; + end + end + + if ((initB_INPUT[b_width-1] == 1) && (C_B_TYPE == `c_signed)) + begin + b_value = add(b_value, one) ; + end + + for (i = b_width; i < multWidth; i = i + 1) + begin + if (C_B_TYPE == `c_signed && b_value[b_width-1] == 1) + begin + b_value[i] = 1 ; + end + else + begin + b_value[i] = 0 ; + end + end + + max_result = a_value * b_value ; + + j = 0 ; + if ((max_result[multWidth-1] == 1) && (C_B_TYPE == `c_signed || C_A_TYPE == `c_signed || C_HAS_A_SIGNED == 1)) + j = 1 ; + + if (MULT_TYPE > 1 && C_HAS_LOADB == 0) + begin + if (C_A_WIDTH == 1) + begin + if (C_A_TYPE == `c_signed || C_A_TYPE == `c_pin) + begin + out_width = C_B_WIDTH+1; + end + else + begin + out_width = C_B_WIDTH; + end + end + else + begin + for(i = 0; i < multWidth; i = i + 1) + begin + if(max_result[i] == 1) + out_width = i+1 ; + end + tmp_out_width = out_width ; + if (a_negative == 1 && b_negative == 1) + out_width = out_width+1 ; + else if ((a_negative == 1 && b_negative == 0) || (a_negative == 0 && b_negative == 1)) + begin + max_result1 = max_result; + if (power_2 == 1) + begin + max_result1[multWidth] = 1; + + for(i = 0; i <= multWidth; i = i + 1) + begin + if(max_result1[i] == 1) + tmp_out_width = i+1 ; + end + for(i = 0; i <= tmp_out_width; i = i + 1) + begin + if(max_result1[i] == 0) + out_width = i+2 ; + end + end + else if ((power_2 !=1)) + begin + for (i = 0; i <= multWidth; i = i + 1) + begin + max_result[i] = ~max_result[i] ; + end + max_result = add(max_result, one) ; + for(i = 0; i <= multWidth; i = i + 1) + begin + if(max_result[i] == 1) + tmp_out_width = i+1 ; + end + for(i = 0; i < tmp_out_width; i = i + 1) + begin + if(max_result[i] == 0) + out_width = i+2 ; + end + end + end + + if (C_HAS_A_SIGNED == 1 && C_B_TYPE == `c_unsigned) + out_width = out_width + 1 ; + end + end + else + begin + if (MULT_TYPE > 2 && C_B_WIDTH == 1) + begin + if (C_HAS_A_SIGNED == 1 && C_B_TYPE == `c_unsigned) + out_width = C_A_WIDTH + 1 ; + else + out_width = C_A_WIDTH ; + end + else if (MULT_TYPE > 2 && C_A_WIDTH == 1) + begin + if (C_HAS_A_SIGNED == 1 && C_B_TYPE == `c_unsigned) + out_width = C_B_WIDTH + 1 ; + else + out_width = C_B_WIDTH ; + end + else + begin + if (C_HAS_A_SIGNED == 1 && C_B_TYPE == `c_unsigned) + out_width = C_A_WIDTH + C_B_WIDTH + 1 ; + else + out_width = C_A_WIDTH + C_B_WIDTH ; + end + end + + //Calculate the shift bits + if (MULT_TYPE != 2) + begin + shift_bits = 0 ; + end + else + begin + shift_bits = 0 ; + for(i = C_B_WIDTH-1; i >= 0; i = i - 1) + begin + if (b_value[i] == 1) + shift_bits = i ; + end + end + + if (MULT_TYPE == 2 && ((C_B_TYPE == `c_unsigned && (b_width-shift_bits) == 1 && C_HAS_LOADB == 0) || (C_HAS_LOADB == 0 && b_width == 0))) + begin + if(C_BAAT == C_A_WIDTH) + begin + real_latency = 0 ; + if(MULT_TYPE == 2 && + B_INPUT[0] == 0 && + b_width == 0) + begin + b_is_zero = 1 ; + b_is_one = 0 ; + end + else if(((MULT_TYPE == 2 && + B_INPUT[0] == 1 && + b_width == 1) || power_2 === 1'b1) && C_B_TYPE == `c_unsigned) + begin + b_is_zero = 0 ; + b_is_one = 1 ; + end + else + begin + b_is_zero = 0 ; + b_is_one = 0 ; + end + end + else + begin + real_latency = C_LATENCY ; + b_is_zero = 0 ; + b_is_one = 0 ; + end + end + else + begin + real_latency = C_LATENCY ; + b_is_zero = 0 ; + b_is_one = 0 ; + end + + if (MULT_TYPE < 3 && C_REG_A_B_INPUTS == 1) + begin + tmpA <= `aall0s; + tmpAB <= `mall0s; + end + //if (MULT_TYPE < 3) + //begin + intO <= `all0s; + intQpipe[0] <= `all0s; + //end + for (j = 0; j <= real_latency; j = j + 1) + begin + intQpipe[j] = `all0s ; + end + + //O_I = `all0s; + Q_I = `all0s; + + end + + always@(initial_intCLK) + begin + last_clk <= intCLK ; + intCLK <= initial_intCLK ; + end + + always@(ACLR) + begin + if (C_HAS_ACLR == 1 && ACLR === 1'bz) + intACLR = 1'b0; + else if (C_HAS_ACLR == 1 && real_latency == 0 && C_REG_A_B_INPUTS == 0 + && MULT_TYPE < 3 && C_HAS_Q == 0) + intACLR = 1'b0; + else if (C_HAS_ACLR == 1) + intACLR = ACLR; + else + intACLR = 1'b0; + end + + always@(SCLR) + begin + if (C_HAS_SCLR == 1 && real_latency == 0 && C_REG_A_B_INPUTS == 0 + && MULT_TYPE < 3 && C_HAS_Q == 0) + intSCLR = 1'b0; + else if (C_HAS_SCLR == 1) //&& ~(MULT_TYPE == 3 && loadb_count != -1)) + intSCLR = SCLR; + else + intSCLR = 1'b0; + end + + //Choose between regND_ccm and regND_parm depending on the type of multiplier + //that has been instantiated. + always@(regND_ccm or regND_parm) + begin + if (C_HAS_ND == 1) + begin + if (MULT_TYPE < 2 && C_BAAT == C_A_WIDTH) + begin + regND_nonseq = regND_parm; + end + else + begin + regND_nonseq = regND_ccm; + end + end + else //no ND + begin + regND_nonseq = 1; + end + end + + //Calculate the RFD output for the non-sequential multiplier. + //The effect of reloading on the RFD is taken into account later on. + always@(intACLR or intSCLR or intRFD_rel) + begin + if (intACLR === 1'b1 || intSCLR === 1'b1 || intRFD_rel === 1'b0) + begin + intRFD = 0; + end + else if (intACLR === 1'bx || intSCLR === 1'bx || intRFD_rel === 1'bx) + begin + intRFD = 1'bx; + end + else + begin + intRFD = 1; + end + end + + // Multiplication processes for the non-sequential multiplier. + // The following occurs asynchronously to the clock. It helps us set + // up the inputs to the multiplication stage. + always@(regA or regB or A_I or B_INPUT or A_SIGNED or regA_SIGNED or intACLR or intND) + begin + if (C_BAAT == C_A_WIDTH) + begin + if (C_REG_A_B_INPUTS == 1 && MULT_TYPE < 3) + begin + if (C_HAS_ND == 1 && ((C_HAS_Q == 1 && C_HAS_O == 0 && MULT_TYPE == 2) || real_latency > 0)) + begin + intA = regA; + intB = regB; + intA_SIGNED = regA_SIGNED; + end + else if (C_HAS_ND == 1) + begin + if (intACLR === 1'b1) + begin + intA = `aall0s; + intB = `ball0s; + intA_SIGNED = 0; + end + else if (intACLR === 1'bx) + begin + intA = `aallxs; + intB = `ballxs; + intA_SIGNED = 1'bx; + end + end + else // no ND + begin + intA = regA; + intB = regB; + intA_SIGNED = regA_SIGNED; + end + end + else if (MULT_TYPE >= 3 && C_REG_A_B_INPUTS == 1) + begin + if (C_HAS_ND == 1) + begin + if (intACLR === 1'b1) + begin + intA = `aall0s; + intA_SIGNED = 0; + end + else if (intACLR === 1'bx) + begin + intA = `aallxs; + intA_SIGNED = 1'bx; + end + end + else // no ND + begin + intA = regA; + intA_SIGNED = regA_SIGNED; + end + if (MULT_TYPE == 3 && real_latency == 0 && C_HAS_O == 1 && C_HAS_ND == 1) + begin + intB = regB_cased; + end + else if (C_HAS_LOADB == 1 && C_HAS_SWAPB == 0) + begin + intB = B_INPUT; + end + else + begin + intB = regB; + end + end + else //C_REG_A_B_INPUTS = 0 + begin + if (MULT_TYPE < 3 || real_latency == 0) + begin + intA = A_I; + intA_SIGNED = A_SIGNED; + end + else + begin + if (intACLR === 1'b1) + begin + intA = `aall0s; + intA_SIGNED = 0; + end + else if (intACLR === 1'bx) + begin + intA = `aallxs; + intA_SIGNED = 1'bx; + end + end + if (real_latency == 0 && MULT_TYPE == 3 + && C_HAS_ND == 1 && intND === 1'b1 && (intCE === 1'b1 || C_HAS_CE == 0)) + begin + intB = B_INPUT; + end + else if (~(MULT_TYPE == 3 && C_HAS_ND == 1)) + begin + intB = B_INPUT; + end + end + end + end + + //Also have to perform the input processing that occurs synchronously to the clock. + always@(posedge intCLK) + begin + if (C_BAAT == C_A_WIDTH) + begin + if (C_REG_A_B_INPUTS == 1 && MULT_TYPE < 3) + begin + if (C_HAS_ND == 1 && ~((C_HAS_Q == 1 && C_HAS_O == 0 && MULT_TYPE == 2) || real_latency > 0)) //MULT_TYPE == 2 is Change 51101a. + begin + if (last_clk !== intCLK && intCLK === 1'b1 && last_clk === 1'b0 && intACLR === 1'b0) + begin + if (intSCLR === 1'b1 && (intCE === 1'b1 || C_SYNC_ENABLE == 0)) + begin + intA <= `aall0s; + intB <= `ball0s; + intA_SIGNED <= 0; + end + else if (intSCLR === 1'bx && (intCE === 1'b1 || C_SYNC_ENABLE == 0)) + begin + intA <= `aallxs; + intB <= `ballxs; + intA_SIGNED <= 1'bx; + end + else if (intSCLR === 1'b1 && (intCE === 1'bx && C_SYNC_ENABLE == 1)) + begin + intA <= `aallxs; + intB <= `ballxs; + intA_SIGNED <= 1'bx; + end + else if (ND_I === 1'b1 && intCE === 1'b1) + begin + intA <= A_I; + intB <= B_INPUT; + intA_SIGNED <= A_SIGNED; + end + else if (ND_I === 1'bx || intCE === 1'bx) + begin + intA <= `aallxs; + intB <= `ballxs; + intA_SIGNED <= 1'bx; + end + end + end + end + else if (MULT_TYPE >= 3 && C_REG_A_B_INPUTS == 1) + begin + if (C_HAS_ND == 1) + begin + if (last_clk !== intCLK && intCLK === 1'b1 && last_clk === 1'b0 && intACLR === 1'b0) + begin + if (intSCLR === 1'b1 && (intCE === 1'b1 || C_SYNC_ENABLE == 0)) + begin + intA <= `aall0s; + intA_SIGNED <= 0; + end + else if (intSCLR === 1'bx && (intCE === 1'b1 || C_SYNC_ENABLE == 0)) + begin + intA <= `aallxs; + intA_SIGNED <= 1'bx; + end + else if (intSCLR === 1'b1 && (intCE === 1'bx && C_SYNC_ENABLE == 1)) + begin + intA <= `aallxs; + intA_SIGNED <= 1'bx; + end + else if (intND === 1'b1 && intCE === 1'b1) + begin + intA <= A_I; + intA_SIGNED <= A_SIGNED; + end + else if (intND === 1'bx || intCE === 1'bx) + begin + intA <= `aallxs; + intA_SIGNED <= 1'bx; + end + end + end + end + else // C_REG_A_B_INPUTS = 0 + begin + if (last_clk !== intCLK && intCLK === 1'b1 && last_clk === 1'b0 && intACLR === 1'b0) // && ~(MULT_TYPE < 3 || C_LATENCY == 0)) + begin + if (MULT_TYPE == 3 && C_HAS_ND == 1) + begin + //if (intSCLR === 1'b1 && (intCE === 1'b1 || C_SYNC_ENABLE == 0)) + //begin + // intB = `ball0s; + //end + //else if (intLOAD_DONE === 1'b0 || (intND === 1'b1 && (intCE === 1'b1 || C_HAS_CE == 0))) + if (intLOAD_DONE === 1'b0 || (intND === 1'b1 && (intCE === 1'b1 || C_HAS_CE == 0))) + begin + intB = B_INPUT; + end + end + if (~(MULT_TYPE < 3 || C_LATENCY == 0)) + begin + if (intSCLR === 1'b1 && (intCE === 1'b1 || C_SYNC_ENABLE == 0)) + begin + intA <= `aall0s; + intA_SIGNED <= 0; + end + else if (intSCLR === 1'bx && (intCE === 1'b1 || C_SYNC_ENABLE == 0)) + begin + intA <= `aallxs; + intA_SIGNED <= 1'bx; + end + else if (intSCLR === 1'b1 && (intCE === 1'bx && C_SYNC_ENABLE == 1)) + begin + intA <= `aallxs; + intA_SIGNED <= 1'bx; + end + else if (intCE === 1'b1 && (((intND === 1'b1 && C_HAS_ND == 1) || C_HAS_ND == 0) || + (MULT_TYPE == 4 && real_latency == 1 && C_MEM_TYPE == 0 && + C_HAS_Q == 0 && C_HAS_SWAPB == 1))) + begin + intA <= A_I; + intA_SIGNED <= A_SIGNED; + end + else if ((intCE === 1'bx || (intND === 1'bx && C_HAS_ND == 1)) || (intCE === 1'bx && C_HAS_ND == 0)) + begin + intA <= `aallxs; + intA_SIGNED <= 1'bx; + end + end + end + else if (((last_clk !== intCLK && intCLK === 1'bx && last_clk === 1'b0) || + (last_clk !== intCLK && intCLK === 1'b1 && last_clk === 1'bx)) && + (intACLR === 1'b0 && ~(MULT_TYPE < 3 || C_LATENCY == 0))) + begin + if ((intCE !== 1'b0 || C_SYNC_ENABLE == 0) && intSCLR !== 1'b0) + begin + intA <= `aallxs; + intA_SIGNED <= 1'bx; + end + else if (intCE !== 1'b0 && intSCLR !== 1'b1) + begin + intA <= `aallxs; + intA_SIGNED <= 1'bx; + end + else if (intCE !== 1'b0 || C_SYNC_ENABLE == 0) + begin + intA <= `aallxs; + intA_SIGNED <= 1'bx; + end + end + end + end + end + + // Now do the actual multiplication. + always@(intA or intB or intA_SIGNED or loadb_count or loadb_count_dly_int) + begin + if (C_BAAT == C_A_WIDTH) + begin + //Sign extend the A input. + if ((C_A_TYPE == `c_signed && C_HAS_A_SIGNED == 0) || (C_HAS_A_SIGNED == 1 && intA_SIGNED === 1'b1)) + begin + for(j = multWidth-1; j >= C_A_WIDTH; j = j - 1) + begin + //tmpA[j] = intA[C_A_WIDTH-1]; + tmpA[j] = intA[ncelab_inta_high-1]; + end + end + else if(C_HAS_A_SIGNED == 1 && intA_SIGNED === 1'bx) + begin + for(j = multWidth-1; j >= C_A_WIDTH; j = j - 1) + begin + tmpA[j] = 1'bx; + end + end + else if((C_A_TYPE == `c_unsigned && C_HAS_A_SIGNED == 0) || (C_HAS_A_SIGNED == 1 && intA_SIGNED == 0)) + begin + for(j = multWidth-1; j >= C_A_WIDTH; j = j - 1) + begin + tmpA[j] = 0; + end + end + tmpA[C_A_WIDTH-1 : 0] = intA; + tmpA_SIGNED = intA_SIGNED ; + + //Sign extend the B input. + if (C_B_TYPE == `c_signed) + begin + for(j = multWidth-1; j >= 0; j = j - 1) + begin + if (j >= b_width) + tmpB[j] = intB[b_width-1]; + else + tmpB[j] = intB[j] ; + end + end + else if(C_B_TYPE == `c_unsigned) + begin + for(j = multWidth-1; j >= 0; j = j - 1) + begin + if (j >= b_width) + tmpB[j] = 0; + else + tmpB[j] = intB[j] ; + end + end + if (C_HAS_LOADB == 1 && C_HAS_SWAPB == 0 && real_latency == 0 && loadb_count != -1 && loaded == 1) + begin + for (i = 0; i < multWidth; i = i + 1) + begin + tmpAB[i] = 1'bx ; + end + end + else if (C_HAS_LOADB == 1 && C_HAS_SWAPB == 0 && real_latency != 0 && (loadb_count != -1 || loadb_count_dly_int != -1) && loaded == 1) + begin + for (i = 0; i < multWidth; i = i + 1) + begin + tmpAB[i] = 1'bx ; + end + end + else if (is_X(tmpA) || is_X(tmpB)) + begin + tmpAB = `mallUKs; + end + else + begin + tmpAB = tmpA * tmpB; + end + end + end + + // Add intRDY_rl. The ready for the reloadable multiplier. + always@(intACLR) + begin + if (intACLR === 1'b1) + begin + intRDY_rl = 0; + end + else if (intACLR === 1'bx && intRDY_rl !== 1'b0) + begin + intRDY_rl = 1'bx; + end + end + + always@(posedge intCLK) + begin + if (last_clk !== intCLK && intCLK === 1'b1 && last_clk === 1'b0 && + (intACLR === 1'b0 || (intACLR === 1'bx && intRDY_rl === 1'b0))) + begin + if (intSCLR === 1'b1 && (intCE === 1'b1 || C_SYNC_ENABLE == 0)) + begin + intRDY_rl <= 0; + end + else if (intSCLR === 1'bx && (intCE === 1'b1 || C_SYNC_ENABLE == 0)) + begin + if (intRDY_rl_pre_reg !== 1'b0) + intRDY_rl <= 1'bx; + else + intRDY_rl <= 1'b0; + end + else if (intSCLR === 1'b1 && (intCE === 1'bx && C_SYNC_ENABLE == 1)) + begin + if (intRDY_rl !== 1'b0) + intRDY_rl <= 1'bx; + else + intRDY_rl <= 1'b0; + end + else if (intCE === 1'b1) + begin + intRDY_rl <= intRDY_rl_pre_reg; + end + else if (intCE === 1'bx && intRDY_rl !== intRDY_rl_pre_reg) + begin + intRDY_rl <= 1'bx; + end + end + else if (((last_clk !== intCLK && intCLK === 1'bx && last_clk === 1'b0) || + (last_clk !== intCLK && intCLK === 1'b1 && last_clk === 1'bx)) && + (intACLR === 1'b0 || (intACLR === 1'bx && intRDY_rl === 1'b0))) + begin + if ((intCE !== 1'b0 || C_SYNC_ENABLE == 0) && intSCLR !== 1'b0) + begin + intRDY_rl <= 1'bx; + end + else if (intCE !== 1'b0 && intSCLR !== 1'b1 && intRDY_rl !== intRDY_rl_pre_reg) + begin + intRDY_rl <= 1'bx; + end + else if ((intCE !== 1'b0 || C_SYNC_ENABLE == 0) && intRDY_rl !== 1'b0) + begin + intRDY_rl <= 1'bx; + end + end + end + + //The rccm can have undefined outputs after an ACLR. The cleared signal helps us model + //this. + always@(intACLR) + begin + if (intACLR === 1'b0) + cleared = 0; + end + + always@(posedge intCLK) + begin + if (last_clk != intCLK && intCLK === 1'b1 && last_clk === 1'b0 && intACLR === 1'b1 && intCE === 1'b1) + cleared <= 1; + end + + //Model the pipeline for the non sequential multiplier. + //Firstly do the asynchronous stuff. + always@(tmpAB or intACLR or loadb_count or loadb_count_no_predelay) + begin + if (C_BAAT == C_A_WIDTH) + begin + //if ((loadb_count != -1 || loadb_count_no_predelay != -1) && C_HAS_SWAPB == 0) + //if (loadb_count == -2 && MULT_TYPE == 3) + //begin + // intO = `allUKs; + //end + //else if (MULT_TYPE > 2 && real_latency > 0 && C_REG_A_B_INPUTS == 0) + if (MULT_TYPE > 2 && real_latency > 0 && C_REG_A_B_INPUTS == 0) + begin + intO = mult_convert(tmpAB); + end + else if (C_REG_A_B_INPUTS == 1) + begin + if (C_HAS_Q == 0 && real_latency == 0) + begin + intO = mult_convert(tmpAB); + end + else // Some registers after the input stage. + begin + if (intACLR === 1'b1 && (MULT_TYPE < 2 || C_MEM_TYPE == 0 || b_is_one == 1)) + begin + intO = `all0s; + end + else if (intACLR === 1'bx && (MULT_TYPE < 2 || C_MEM_TYPE == 0 || b_is_one == 1)) + begin + intO = `allUKs; + end + end + end + else //C_REG_A_B_INPUTS = 0 + begin + if (real_latency == 0 && C_HAS_Q == 0) + begin + intO = mult_convert(tmpAB); + end + else if (C_HAS_ND == 0 && ~(MULT_TYPE == 2 && real_latency >= 1 && C_MEM_TYPE == 2)) + // No ACLR for the block memory. + begin + if (~(MULT_TYPE >= 2 && C_MEM_TYPE == 2 && b_is_one == 0)) + begin + if (intACLR === 1'b1) + begin + intO = `all0s; + end + else if (intACLR === 1'bx) + begin + intO = `allUKs; + end + end + end + else if (C_HAS_ND == 1 && (MULT_TYPE < 2 && ~(real_latency == 1 && C_HAS_O == 1)) + && ~(MULT_TYPE == 2 && real_latency >= 1 && C_MEM_TYPE == 2)) + begin + if (intACLR === 1'b1) + begin + intO = `all0s; + end + else if (intACLR === 1'bx) + begin + intO = `allUKs; + end + end + else if (~(MULT_TYPE == 2 && real_latency >= 1 && C_MEM_TYPE == 2)) //C_HAS_ND = 1 + begin + if (intACLR == 1'b1 && (MULT_TYPE < 2 || C_MEM_TYPE == 0 || b_is_one == 1)) + begin + intO = `all0s; + end + else if (intACLR === 1'bx) + begin + intO = `allUKs; + end + end + end + // Clear intO whenever we clear sub_product(0) in the vhdl. + if ((intACLR === 1'b1)) + begin + if (C_MEM_TYPE == 2 && MULT_TYPE > 2 && real_latency > 1) + begin + if (cleared == 0) + begin + for (j = 1; j <= real_latency; j = j + 1) + begin + intO = `allUKs; + end + end + end + end + end + end + + //Now change the intO output on the clock. + always@(posedge intCLK) + begin + if (C_BAAT == C_A_WIDTH) + begin + if (C_REG_A_B_INPUTS == 1) // && (~(loadb_count != -1 && C_HAS_SWAPB == 0))) + begin + if (~(C_HAS_Q == 0 && real_latency == 0)) + begin + if (last_clk !== intCLK && intCLK === 1'b1 && last_clk === 1'b0 && (intACLR === 1'b0 || (MULT_TYPE > 1 && C_MEM_TYPE == 2 && b_is_one == 0))) + begin + if (intSCLR === 1'b1 && (intCE === 1'b1 || C_SYNC_ENABLE == 0) && + ~(MULT_TYPE == 3 && loadb_count != -1)) + begin + intO <= `all0s; + end + else if (intSCLR === 1'bx && (intCE === 1'b1 || C_SYNC_ENABLE == 0)) + begin + intO <= `allUKs; + end + else if (intSCLR === 1'b1 && (intCE === 1'bx && C_SYNC_ENABLE == 1)) + begin + intO <= `allUKs; + end + // Ignore the ND in these cases. + else if ((MULT_TYPE < 2 && real_latency == 0) || + (C_HAS_SWAPB == 1 || C_HAS_ND == 0)) + begin + if (intCE === 1'b1) + begin + intO <= mult_convert(tmpAB); + end + else if (intCE === 1'bx) + begin + intO <= `allUKs; + end + end + // Otherwise wait for the ND to appear before clocking the + // result into the pipeline. + else if ((regND === 1'b1 || (MULT_TYPE == 3 && loadb_count != -1)) + && intCE === 1'b1) + begin + intO <= mult_convert(tmpAB); + end + else if (regND === 1'bx || intCE === 1'bx) + begin + intO <= `allUKs; + end + end + else if (((last_clk !== intCLK && intCLK === 1'bx && last_clk === 1'b0) || + (last_clk !== intCLK && intCLK === 1'b1 && last_clk === 1'bx)) && + (intACLR === 1'b0 || (MULT_TYPE > 1 && C_MEM_TYPE == 2 && b_is_one == 0))) + begin + if ((intCE !== 1'b0 || C_SYNC_ENABLE == 0) && intSCLR !== 1'b0) + begin + intO <= `allUKs; + end + else if (intCE !== 1'b0 && intSCLR !== 1'b1) + begin + intO <= `allUKs; + end + else if (intCE !== 1'b0 || C_SYNC_ENABLE == 0) + begin + intO <= `allUKs; + end + end + end + end + //else if ((~(loadb_count != -1 && C_HAS_SWAPB == 0)) && + // (~(MULT_TYPE > 2 && real_latency > 0 && C_REG_A_B_INPUTS == 0))) + else if (MULT_TYPE > 2 && real_latency > 0 && C_REG_A_B_INPUTS == 0) + begin + intO = mult_convert(tmpAB); + end + else if (~(MULT_TYPE > 2 && real_latency > 0 && C_REG_A_B_INPUTS == 0)) + begin + //C_REG_A_B_INPUTS = 0 + if ((~(real_latency == 0 && C_HAS_Q == 0)) && C_HAS_ND == 0) + begin + if (last_clk !== intCLK && last_clk === 1'b0 && intCLK === 1'b1 && (intACLR === 1'b0 || (MULT_TYPE > 1 && C_MEM_TYPE == 2 && b_is_one == 0))) + begin + if ((intSCLR === 1'b1 && (intCE === 1'b1 || C_SYNC_ENABLE == 0)) + && ~(MULT_TYPE == 3 && loadb_count != -1)) + begin + intO <= `all0s; + end + else if (intSCLR === 1'bx && (intCE === 1'b1 || C_SYNC_ENABLE == 0)) + begin + intO <= `allUKs; + end + else if (intSCLR === 1'b1 && (intCE === 1'bx && C_SYNC_ENABLE == 1)) + begin + intO <= `allUKs; + end + else if (intCE === 1'b1) + begin + intO <= mult_convert(tmpAB); + end + else if (intCE === 1'bx) + begin + intO <= `allUKs; + end + end + else if (((last_clk !== intCLK && intCLK === 1'bx && last_clk === 1'b0) || + (last_clk !== intCLK && intCLK === 1'b1 && last_clk === 1'bx)) && + (intACLR === 1'b0 || (MULT_TYPE > 1 && C_MEM_TYPE == 2 && b_is_one == 0))) + begin + if ((intCE !== 1'b0 || C_SYNC_ENABLE == 0) && intSCLR !== 1'b0) + begin + intO <= `allUKs; + end + else if (intCE !== 1'b0 && intSCLR !== 1'b1) + begin + intO <= `allUKs; + end + else if (intCE !== 1'b0 || C_SYNC_ENABLE == 0) + begin + intO <= `allUKs; + end + end + end + else if ((~(real_latency == 0 && C_HAS_Q == 0)) + && (C_HAS_ND == 1 && MULT_TYPE < 2 && ~(real_latency == 1 && C_HAS_O == 1))) + begin + if (last_clk !== intCLK && last_clk === 1'b0 && intCLK === 1'b1 && (intACLR === 1'b0 || (MULT_TYPE > 1 && C_MEM_TYPE == 2 && b_is_one == 0))) + begin + if ((intSCLR === 1'b1 && (intCE === 1'b1 || C_SYNC_ENABLE == 0)) + && ~(MULT_TYPE == 3 && loadb_count != -1)) + begin + intO <= `all0s; + end + else if (intSCLR === 1'bx && (intCE === 1'b1 || C_SYNC_ENABLE == 0)) + begin + intO <= `allUKs; + end + else if (intSCLR === 1'b1 && (intCE === 1'bx && C_SYNC_ENABLE == 1)) + begin + intO <= `allUKs; + end + else if ((intCE === 1'b1 && real_latency == 0 && C_HAS_Q == 1 && intND === 1'b1) + || (intCE === 1'b1 && ~(real_latency == 0 && C_HAS_Q == 1))) + begin + intO <= mult_convert(tmpAB); + end + else if (intCE === 1'bx) + begin + intO <= `allUKs; + end + end + else if (((last_clk !== intCLK && intCLK === 1'bx && last_clk === 1'b0) || + (last_clk !== intCLK && intCLK === 1'b1 && last_clk === 1'bx)) && + (intACLR === 1'b0 || (MULT_TYPE > 1 && C_MEM_TYPE == 2 && b_is_one == 0))) + begin + if ((intCE !== 1'b0 || C_SYNC_ENABLE == 0) && intSCLR !== 1'b0) + begin + intO <= `allUKs; + end + else if (intCE !== 1'b0 && intSCLR !== 1'b1) + begin + intO <= `allUKs; + end + else if (intCE !== 1'b0 || C_SYNC_ENABLE == 0) + begin + intO <= `allUKs; + end + end + end + else if (~(real_latency == 0 && C_HAS_Q == 0)) //C_HAS_ND = 1 + begin + if (real_latency == 0) + begin + if (last_clk !== intCLK && last_clk === 1'b0 && intCLK === 1'b1 && (intACLR === 1'b0 || (MULT_TYPE > 1 && C_MEM_TYPE == 2 && b_is_one == 0))) + begin + if ((intSCLR === 1'b1 && (intCE === 1'b1 || C_SYNC_ENABLE == 0)) + && ~(MULT_TYPE == 3 && loadb_count != -1)) + begin + intO <= `all0s; + end + else if (intSCLR === 1'bx && (intCE === 1'b1 || C_SYNC_ENABLE == 0)) + begin + intO <= `allUKs; + end + else if (intSCLR === 1'b1 && (intCE === 1'bx && C_SYNC_ENABLE == 1)) + begin + intO <= `allUKs; + end + else if ((ND_I === 1'b1 || (MULT_TYPE == 3 && loadb_count != -1)) + && intCE === 1'b1) + begin + intO <= mult_convert(tmpAB); + end + else if (ND_I === 1'bx || intCE === 1'bx) + begin + intO <= `allUKs; + end + end + else if (((last_clk !== intCLK && intCLK === 1'bx && last_clk === 1'b0) || + (last_clk !== intCLK && intCLK === 1'b1 && last_clk === 1'bx)) && + (intACLR === 1'b0 || (MULT_TYPE > 1 && C_MEM_TYPE == 2 && b_is_one == 0))) + begin + if ((intCE !== 1'b0 || C_SYNC_ENABLE == 0) && intSCLR !== 1'b0) + begin + intO <= `allUKs; + end + else if (intCE !== 1'b0 && intSCLR !== 1'b1) + begin + intO <= `allUKs; + end + else if (intCE !== 1'b0 || C_SYNC_ENABLE == 0) + begin + intO <= `allUKs; + end + end + end + else //latency > 0 + begin + if (last_clk !== intCLK && last_clk === 1'b0 && intCLK === 1'b1 && (intACLR === 1'b0 || (MULT_TYPE > 1 && C_MEM_TYPE == 2 && b_is_one == 0))) + begin + if ((intSCLR === 1'b1 && (intCE === 1'b1 || C_SYNC_ENABLE == 0)) + && ~(MULT_TYPE == 3 && loadb_count != -1)) + begin + intO <= `all0s; + end + else if (intSCLR === 1'bx && (intCE === 1'b1 || C_SYNC_ENABLE == 0)) + begin + intO <= `allUKs; + end + else if (intSCLR === 1'b1 && (intCE === 1'bx && C_SYNC_ENABLE == 1)) + begin + intO <= `allUKs; + end + else if (intCE === 1'b1 && ((ND_I === 1'b1 + || (MULT_TYPE == 3 && loadb_count != -1)) + || intSWAPB === 1'b1)) + begin + intO <= mult_convert(tmpAB); + end + else if (intCE === 1'bx || (ND_I === 1'bx && intSWAPB !== 1'b0) + || (ND_I !== 1'b0 && intSWAPB === 1'bx)) + begin + intO <= `allUKs; + end + end + else if (((last_clk !== intCLK && intCLK === 1'bx && last_clk === 1'b0) || + (last_clk !== intCLK && intCLK === 1'b1 && last_clk === 1'bx)) && + (intACLR === 1'b0 || (MULT_TYPE > 1 && C_MEM_TYPE == 2 && b_is_one == 0))) + begin + if ((intCE !== 1'b0 || C_SYNC_ENABLE == 0) && intSCLR !== 1'b0) + begin + intO <= `allUKs; + end + else if (intCE !== 1'b0 && intSCLR !== 1'b1) + begin + intO <= `allUKs; + end + else if (intCE !== 1'b0 || C_SYNC_ENABLE == 0) + begin + intO <= `allUKs; + end + end + end + end + end + // Clear intO when we clear intQpipe[0]. + //if ((last_clk !== intCLK && last_clk === 1'b0 && intCLK === 1'b1) && + // (~(loadb_count != -1 && C_HAS_SWAPB == 0))) + if (last_clk !== intCLK && last_clk === 1'b0 && intCLK === 1'b1) + begin + if (intACLR == 1'b1) + begin + if (C_MEM_TYPE == 2 && MULT_TYPE > 2 && (real_latency > 1 || (MULT_TYPE == 3 && C_MEM_TYPE == 2 && real_latency == 1))) + begin + if (cleared == 0) + begin + intO = `allUKs; + end + end + end + else if ((intSCLR === 1'b1 && (intCE === 1'b1 || C_SYNC_ENABLE == 0)) + && ~(MULT_TYPE == 3 && loadb_count != -1)) + begin + if (loadb_count == -1 && (C_MEM_TYPE == 0 || MULT_TYPE < 2 || C_SYNC_ENABLE == 1 || intCE === 1'b1)) + begin + intO <= `all0s; + end + end + else if (intSCLR === 1'b1 && (intCE === 1'bx || C_SYNC_ENABLE == 0)) + begin + intO <= `allUKs; + end + else if (intSCLR === 1'bx && (intCE === 1'b1 || C_SYNC_ENABLE == 0)) + begin + intO <= `allUKs; + end + end + else if (((last_clk !== intCLK && intCLK === 1'bx && last_clk === 1'b0) || + (last_clk !== intCLK && intCLK === 1'b1 && last_clk === 1'bx)) && + (intACLR === 1'b0 || (C_MEM_TYPE == 2 && MULT_TYPE > 2 && real_latency > 1 && intCE === 1'b1))) + begin + if ((intCE !== 1'b0 || C_SYNC_ENABLE == 0) && intSCLR !== 1'b0) + begin + intO <= `allUKs; + end + else if (intCE !== 1'b0 && intSCLR !== 1'b1) + begin + intO <= `allUKs; + end + else if (intCE !== 1'b0 || C_SYNC_ENABLE == 0) + begin + intO <= `allUKs; + end + end + end + end + + //Load intO into the pipeline + always@(intACLR or intO) + begin + if ((intSCLR === 1'b1 && loadb_count == -1 && (intCE === 1'b1 || C_SYNC_ENABLE == 0)) && + (C_MEM_TYPE == 0 || MULT_TYPE < 2 || C_SYNC_ENABLE == 1 || intCE === 1'b1) && + (last_clk !== intCLK && last_clk === 1'b0 && intCLK === 1'b1 && + (intACLR === 1'b0 || (C_MEM_TYPE == 2 && MULT_TYPE > 2 + && (real_latency > 1 || (C_MEM_TYPE == 2 && MULT_TYPE == 3 && real_latency == 1)) && intCE === 1'b1)))) + begin + intQpipe[0] = `all0s; + end + else if ((intACLR === 1'b1 && C_MEM_TYPE == 2 && MULT_TYPE > 2 && (real_latency > 1 || (MULT_TYPE == 3 && C_MEM_TYPE == 2 && real_latency == 1)) + && intCE === 1'b1) && + (last_clk !== intCLK && last_clk === 1'b0 && intCLK === 1'b1)) + begin + intQpipe[0] = `all0s; + end + else + begin + intQpipe[0] = intO; + end + end + + //Load the pipleine. + always@(posedge intCLK) + begin + if (last_clk !== intCLK && last_clk === 1'b0 && intCLK === 1'b1 && intSCLR === 1'b0 && intACLR === 1'b0) + intQpipe[0] <= intO; + end + + //This process clears the pipeline for the non-sequential multiplier. + always@(intACLR) + begin + if (C_BAAT == C_A_WIDTH) + begin + if (intACLR === 1'b1) + begin + if (C_MEM_TYPE == 2 && MULT_TYPE > 2 && (real_latency > 1 || (MULT_TYPE == 3 && C_MEM_TYPE == 2 && real_latency == 1))) + begin + if (cleared == 0) + begin + for (j = 1; j <= real_latency; j = j + 1) + begin + intQpipe[j] = `allUKs; + end + end + end + else if (real_latency > 0 && (MULT_TYPE < 3 || C_MEM_TYPE == 0)) + begin + for (j = 1; j <= real_latency; j = j + 1) + begin + intQpipe[j] = `all0s; + end + end + end + else if (intACLR === 1'bx) + begin + if (C_MEM_TYPE == 2 && MULT_TYPE > 2 && real_latency > 1) + begin + if (cleared == 0) + begin + for (j = 1; j <= real_latency; j = j + 1) + begin + intQpipe[j] = `allUKs; + end + end + end + else if (real_latency > 0) + begin + for (j = 1; j <= real_latency; j = j + 1) + begin + intQpipe[j] = `allUKs; + end + end + end + end + end + + //This process updates the pipeline for the non-sequential multiplier. + always@(posedge intCLK) + begin + if (C_BAAT == C_A_WIDTH) + begin + if (last_clk !== intCLK && last_clk === 1'b0 && intCLK === 1'b1 ) + begin + if (intACLR == 1'b1 && C_MEM_TYPE == 2 && MULT_TYPE > 2 + && (real_latency > 1 || (MULT_TYPE == 3 && C_MEM_TYPE == 2 && real_latency == 1)) + && intCE === 1'b1) + begin + if (cleared == 0) + begin + intQpipe[real_latency] = `all0s; + end + end + else if ((intACLR === 1'b0)) + begin + if ((intSCLR === 1'b1 && (intCE === 1'b1 || C_SYNC_ENABLE == 0)) + && ~(MULT_TYPE == 3 && loadb_count != -1 && (C_MEM_TYPE == 2 || real_latency < 3))) + begin + if (C_MEM_TYPE == 0 || MULT_TYPE < 2 || C_SYNC_ENABLE == 1 || intCE === 1'b1) + begin + if (MULT_TYPE > 2 && C_MEM_TYPE == 2 && C_HAS_LOADB == 1 && C_HAS_SWAPB == 0 && real_latency > 1 && loadb_count != -1) + begin + for(j = real_latency-1; j <= real_latency; j = j + 1) + begin + intQpipe[j] <= `all0s; + end + end + else if (real_latency >= 1) + begin + for(j = 1; j <= real_latency; j = j + 1) + begin + intQpipe[j] <= `all0s; + end + end + end + else if (real_latency > 0) + begin + if (MULT_TYPE > 2 && C_MEM_TYPE == 2 && C_HAS_LOADB == 1 && C_HAS_SWAPB == 0 && real_latency > 1 && loadb_count != - 1) + begin + for(j = real_latency-1; j <= real_latency; j = j + 1) + begin + intQpipe[j] <= `all0s; + end + end + else + begin + for(j = 1; j <= real_latency; j = j + 1) + begin + intQpipe[j] <= `all0s; + end + end + end + end + else if (intSCLR === 1'b1 && (intCE === 1'bx || C_SYNC_ENABLE == 0)) + begin + for(j = 0; j <= real_latency; j = j + 1) + begin + intQpipe[j] <= `allUKs; + end + end + else if (intSCLR === 1'bx && (intCE === 1'b1 || C_SYNC_ENABLE == 0)) + begin + for(j = 0; j <= real_latency; j = j + 1) + begin + intQpipe[j] <= `allUKs; + end + end + else if (intCE === 1'b1) + begin + if (C_REG_A_B_INPUTS == 1 || C_HAS_ND == 0 || + (MULT_TYPE > 1 || (MULT_TYPE < 2 && real_latency == 1 && C_HAS_O == 1)) || + C_PIPELINE == 0) + begin + for(j = real_latency; j >= 1; j = j - 1) + begin + intQpipe[j] <= intQpipe[j-1]; + end + end + else + begin + if (real_latency > 1) + begin + for(j = real_latency; j >= 2; j = j - 1) + begin + intQpipe[j] <= intQpipe[j-1]; + end + end + if (real_latency > 0) + begin + if (regND_nonseq === 1'b1) + intQpipe[1] <= intQpipe[0]; + else if (regND_nonseq === 1'bx) + intQpipe[1] <= `allUKs; + end + end + end + else if (intCE === 1'bx) + begin + if (C_REG_A_B_INPUTS == 1 || C_HAS_ND == 0 || + (MULT_TYPE > 1 || (MULT_TYPE < 2 && real_latency == 1 && C_HAS_O == 1)) || + C_PIPELINE == 0) + begin + for(j = real_latency; j >= 1; j = j - 1) + begin + intQpipe[j] <= `allUKs; + end + end + else + begin + if (real_latency > 0) + begin + for(j = real_latency; j >= 0; j = j - 1) + begin + intQpipe[j] <= `allUKs; + end + end + end + end + end + end + else if (((last_clk !== intCLK && intCLK === 1'bx && last_clk === 1'b0) || + (last_clk !== intCLK && intCLK === 1'b1 && last_clk === 1'bx)) && + (intACLR === 1'b0 || (C_MEM_TYPE == 2 && MULT_TYPE > 2 && real_latency > 1 + && intCE === 1'b1))) + begin + if ((intCE !== 1'b0 || C_SYNC_ENABLE == 0) && intSCLR !== 1'b0) + begin + for(j = real_latency; j >= 0; j = j - 1) + begin + intQpipe[j] <= `allUKs; + end + end + else if (intCE !== 1'b0 && intSCLR !== 1'b1) + begin + for(j = real_latency; j >= 0; j = j - 1) + begin + intQpipe[j] <= `allUKs; + end + end + else if (intCE !== 1'b0 || C_SYNC_ENABLE == 0) + begin + for(j = real_latency; j >= 0; j = j - 1) + begin + intQpipe[j] <= `allUKs; + end + end + end + end + end + + //Model the ready output pipeline. First do the asynchronous updates. + always@(intACLR or intRDY) + begin + if (C_BAAT == C_A_WIDTH) + begin + if (intACLR === 1'b0 || intACLR === 1'bx || real_latency == 0) + begin + intRDYpipe[0] = intRDY; + end + else if (intACLR === 1'b1) + begin + for(j = 0; j <= real_latency; j = j + 1) + begin + intRDYpipe[j] = 0; + end + end + else if (intACLR === 1'bx) + begin + for(j = 0; j <= real_latency; j = j + 1) + begin + if (intRDYpipe[j] !== 1'b0) + begin + intRDYpipe[j] = 1'bx; + end + end + end + end + end + + //Model the synchronous part of the ready pipeline. + always@(posedge intCLK) + begin + if (C_BAAT == C_A_WIDTH) + begin + if (last_clk !== intCLK && last_clk === 1'b0 && intCLK === 1'b1 && intACLR !== 1'b1) + begin + if (intSCLR === 1'b1 && (intCE === 1'b1 || C_SYNC_ENABLE == 0)) + begin + for(j = real_latency; j >= 0; j = j - 1) + begin + intRDYpipe[j] <= 0; + end + end + else if (intSCLR === 1'bx && (intCE === 1'b1 || C_SYNC_ENABLE == 0)) + begin + for(j = real_latency; j >= 1; j = j - 1) + begin + if (intRDYpipe[j-1] !== 1'b0) + begin + intRDYpipe[j] <= 1'bx; + end + else + begin + intRDYpipe[j] <= 1'b0; + end + end + end + else if (intSCLR === 1'b1 && (intCE === 1'bx && C_SYNC_ENABLE == 1)) + begin + for(j = real_latency; j >= 0; j = j - 1) + begin + if (intRDYpipe[j] !== 1'b0) + intRDYpipe[j] <= 1'bx; + else + intRDYpipe[j] <= 1'b0; + end + end + else if (intCE === 1'b1 && intACLR === 1'b0) + begin + for(j = real_latency; j >= 1; j = j - 1) + begin + intRDYpipe[j] <= intRDYpipe[j-1]; + end + end + else if (intCE === 1'b1 && intACLR === 1'bx) + begin + for(j = real_latency; j >= 1; j = j - 1) + begin + if (intRDYpipe[j-1] === 1'b0) + intRDYpipe[j] <= intRDYpipe[j-1]; + else + intRDYpipe[j] <= 1'bx; + end + end + else if (intCE === 1'bx) + begin + for(j = real_latency; j >= 1; j = j - 1) + begin + if (intRDYpipe[j] !== intRDYpipe[j-1]) + begin + intRDYpipe[j] <= 1'bx; + end + end + end + end + else if (((last_clk !== intCLK && intCLK === 1'bx && last_clk === 1'b0) || + (last_clk !== intCLK && intCLK === 1'b1 && last_clk === 1'bx)) && + (intACLR !== 1'b1)) + begin + if ((intCE !== 1'b0 || C_SYNC_ENABLE == 0) && intSCLR !== 1'b0) + begin + for(j = real_latency; j >= 1; j = j - 1) + begin + intRDYpipe[j] <= 1'bx; + end + end + else if (intCE !== 1'b0 && intSCLR !== 1'b1) + begin + for(j = real_latency; j >= 1; j = j - 1) + begin + if (intRDYpipe[j] !== intRDYpipe[j-1]) + intRDYpipe[j] <= 1'bx; + end + end + else if (intCE !== 1'b0 || C_SYNC_ENABLE == 0) + begin + for(j = real_latency; j >= 1; j = j - 1) + begin + if (intRDYpipe[j] !== 1'b0) + intQpipe[j] <= 1'bx; + end + end + end + end + end + + //Now drive the internal versions of the O, Q and RDY outputs. + //Again do the asynchronous updates first. + always@(intO or tmpAB or intQpipe[real_latency] or intQpipe[0] or intQpipe[real_latency-1] or intRDYpipe or intACLR or intSCLR or intCE or intCLK or ND_I) + begin + if (C_BAAT == C_A_WIDTH) + begin + if (real_latency == 0) + begin + // Assign O Output. + O_I = mult_convert(tmpAB); + // Assign Q Output. + if (b_is_zero == 1) + begin + Q_I = `all0s; + end + else if (C_MEM_TYPE == 0 || MULT_TYPE < 2) + begin + if (intACLR === 1'b1) + Q_I = `all0s; + else if (intACLR === 1'bx) + Q_I = `allUKs; + else + Q_I = intQpipe[0]; + end + else + begin + Q_I = intQpipe[0]; + end + + // Assign RDY Output. + if (C_HAS_ND == 1) + begin + if (b_is_zero == 1) + RDY_I = ND_I; + else + RDY_I = intRDYpipe[0]; + end + else + begin + RDY_I = 1; + end + + end + else + begin + if (C_MEM_TYPE == 2 && MULT_TYPE > 2 && real_latency > 2 && (C_PIPELINE == 0 || real_latency > 3)) + begin + if (intACLR === 1'b1) + begin + O_I = `all0s; + Q_I = `all0s; + end + else if (intACLR === 1'bx) + begin + O_I = `allUKs; + Q_I = `allUKs; + end + else + begin + O_I = intQpipe[real_latency-1]; + Q_I = intQpipe[real_latency]; + end + end + else if (C_MEM_TYPE == 2 && MULT_TYPE > 2 && (real_latency == 2 || (C_PIPELINE == 1 && real_latency > 1))) + begin + O_I = intQpipe[real_latency-1]; + if (intACLR === 1'b1) + begin + Q_I = `all0s; + end + else if (intACLR === 1'bx) + begin + Q_I = `allUKs; + end + else + begin + Q_I = intQpipe[real_latency]; + end + end + else + begin + O_I = intQpipe[real_latency-1]; + Q_I = intQpipe[real_latency]; + end + if (C_HAS_ND == 1) + if (C_REG_A_B_INPUTS == 1 || MULT_TYPE > 1 || C_PIPELINE == 0 || C_LATENCY < 1 || + (C_PIPELINE == 1 && C_HAS_ND == 1 && MULT_TYPE < 2 && real_latency == 1 && + C_REG_A_B_INPUTS == 0 && C_HAS_Q == 0)) + + RDY_I = intRDYpipe[real_latency]; + else + RDY_I = intRDYpipe[real_latency-1]; + else + RDY_I = 1; + end + end + end + + //Register the RFD and RDY signals. + //Asynchronous clear. + always@(intACLR) + begin + if (intACLR === 1'b1) + begin + if (b_is_zero == 0) + begin + regRFD = 0; + regRDY = 0; + end + else + begin + regRFD = 0; + end + end + else if (intACLR === 1'bx && regRDY !== 1'b0 && b_is_zero == 0) + begin + regRDY = 1'bx; + end + else if (intACLR === 1'bx && regRFD !== 1'b0) + begin + regRFD = 1'bx; + end + end + + always@(ND_I) + begin + if (b_is_zero == 1) + begin + regRDY = ND_I; + end + end + + //Synchronous clear and registered output. + always@(posedge intCLK) + begin + if (b_is_zero == 0 && last_clk !== intCLK && last_clk === 1'b0 && intCLK === 1'b1 && intACLR !== 1'b1) + begin + if (intSCLR === 1'b1 && (intCE === 1'b1 || C_SYNC_ENABLE == 0)) + begin + regRFD <= 0; + regRDY <= 0; + end + else if (intSCLR === 1'bx && (intCE === 1'b1 || C_SYNC_ENABLE == 0)) + begin + if (intRFD !== 1'b0) + regRFD <= 1'bx; + else + regRFD <= 1'b0; + if (RDY_I !== 1'b0) + regRDY <= 1'bx; + else + regRDY <= 1'b0; + end + else if (intSCLR === 1'b1 && (intCE === 1'bx && C_SYNC_ENABLE == 1)) + begin + if (regRFD !== 1'b0) + regRFD <= 1'bx; + else + regRFD <= 1'b0; + if (regRDY !== 1'b0) + regRDY <= 1'bx; + else + regRDY <= 1'b0; + end + else if (intCE === 1'b1 && intACLR === 1'b0) + begin + regRFD <= intRFD; + regRDY <= RDY_I; + end + else if (intCE === 1'b1 && intACLR === 1'bx) + begin + if (intRFD === 1'b0) + regRFD <= intRFD; + else + regRFD <= 1'bx; + if (RDY_I === 1'b0) + regRDY <= RDY_I; + else + regRDY <= 1'bx; + end + else if (intCE === 1'bx) + begin + if (regRFD !== intRFD) + regRFD <= 1'bx; + if (regRDY !== RDY_I) + regRDY <= 1'bx; + end + end + else if (((last_clk !== intCLK && intCLK === 1'bx && last_clk === 1'b0) || + (last_clk !== intCLK && intCLK === 1'b1 && last_clk === 1'bx)) && + (intACLR !== 1'b1)) + begin + if ((intCE !== 1'b0 || C_SYNC_ENABLE == 0) && intSCLR !== 1'b0) + begin + regRDY <= 1'bx; + regRFD <= 1'bx; + end + else if (intCE !== 1'b0 && intSCLR !== 1'b1) + begin + if (regRFD !== intRFD) + regRFD <= 1'bx; + if (regRDY !== RDY_I) + regRDY <= 1'bx; + end + else if (intCE !== 1'b0 || C_SYNC_ENABLE == 0) + begin + if (regRFD !== 1'b0) + regRFD <= 1'bx; + if (regRDY !== 1'b0) + regRDY <= 1'bx; + end + end + end + + //Model the reloading process for a reloadable constant coefficient multiplier. + //This is a synchronous process but we must deal with the asynchronous clear first. + always@(intACLR) + begin + if (C_HAS_LOADB == 1) + begin + if (intACLR === 1'b1) + begin + if (loadb_count != -1 && loadb_count != -2) // -1 = Load finished + begin + loadb_count = -2; // -2 = Load interrupted by clear. + loadb_count_no_predelay = -2; + end + intLOAD_DONE = 1; + intRFD_rel = 1; + end + else if (intACLR === 1'bx) + begin + if (loadb_count != -1 && loadb_count != -2) + begin + loadb_count = -3; // -3 = Undefined. + intLOAD_DONE = 1'bx; + if (C_HAS_SWAPB == 0) + intRFD_rel = 1'bx; + else + intRFD_rel = 1'b1; + end + end + end + end + + //Now do the synchronous update on the rising clock edge. + always@(posedge intCLK) + begin + if (last_clk !== intCLK && last_clk === 1'b0 && intCLK === 1'b1 && C_HAS_LOADB == 1 && intACLR !== 1'b1 && intLOADB === 1'bx && intCE !== 1'b0) + begin + loadb_count = -3; + if (C_HAS_SWAPB == 1 && bank_sel === 1'bx ) + begin + b_const0 <= `ballxs; + b_const1 <= `ballxs; + end + else if (C_HAS_SWAPB == 1 && bank_sel === 1'b0) + begin + b_const1 <= `ballxs; + end + else + begin + b_const0 <= `ballxs; + end + end + else if (last_clk !== intCLK && last_clk === 1'b0 && intCLK === 1'b1 && C_HAS_LOADB == 1 && intACLR === 1'b0) + begin + if (intSCLR === 1'b1 && (intCE === 1'b1 || C_SYNC_ENABLE == 0)) + begin + if (loadb_count != -1 && loadb_count != -2) + begin + loadb_count <= -2; + end + end + else if (intSCLR === 1'bx && (intCE === 1'b1 || C_SYNC_ENABLE == 0)) + begin + if (loadb_count != -1 && loadb_count != -2) + begin + loadb_count <= -2-sig_addr_bits; + end + end + else if (intCE === 1'b1) + begin + if (intLOADB === 1'b1) + begin + if (C_REG_A_B_INPUTS == 1 || C_HAS_A_SIGNED == 1 || C_A_TYPE == `c_signed) + begin + loadb_count <= loadb_delay+1+C_REG_A_B_INPUTS; + end + else + begin + loadb_count <= loadb_delay; + end + loadb_value <= B_I; + loaded <= 1; + end + else //loadb == 0. + begin + if (C_HAS_O == 1 && MULT_TYPE == 3 && C_HAS_SWAPB == 0 && + loadb_count == 2 && loadb_delay > 2 && C_HAS_ND == 1) + //Load early in this case. + begin + b_const0 <= loadb_value; + loadb_count <= loadb_count - 1; + end + else if (loadb_count > 0) + begin + loadb_count <= loadb_count - 1; + end + else if (loadb_count <= -3) //Undefined state + begin + if (loadb_count != -2-sig_addr_bits && C_REG_A_B_INPUTS == 0 && real_latency == 0) + // Wait for sig_addr_bits cycles before setting the op + // to undefined. + begin + loadb_count <= loadb_count - 1; + end + end + else if (loadb_count == 0) + begin + if (C_HAS_SWAPB == 1 && bank_sel === 1'b0) + b_const1 <= loadb_value; + else + b_const0 <= loadb_value; + //if (ND_I === 1'b1 || (C_HAS_SWAPB == 1 || C_HAS_ND == 0 || C_REG_A_B_INPUTS == 1)) + //begin + loadb_count <= -1; + //end + loaded <= 1; + end + else if (loadb_count == -2) //Load has been interrupted by a clear. + begin + if (C_HAS_SWAPB == 1 && bank_sel == 0) + b_const1 <= `ballxs; + else + b_const0 <= `ballxs; + loaded <= 1; + end + end + end + else if (intCE === 1'bx) + begin + if (loadb_count != -1 && loadb_count != -2 && (loadb_count != -2-sig_addr_bits && C_REG_A_B_INPUTS == 0 && real_latency == 0)) + begin + if (loadb_count > 0) + loadb_count <= -3; + else + loadb_count <= loadb_count-1; + end + else if (loadb_count == -2-sig_addr_bits || (loadb_count != -1 && loadb_count != -2 && (C_REG_A_B_INPUTS == 1 || real_latency > 0))) + // Propogate the 'X' through when the TC from the load engines + // counter goes to 'X' or if the inputs are registered. + begin + if (C_REG_A_B_INPUTS == 1 || real_latency > 0) + loadb_count <= -3; + end + end + end + end + + // The load done and RFD outputs don't depend on the C_PREDELAY parameter. + always@(posedge intCLK) + begin + if (last_clk !== intCLK && last_clk === 1'b0 && intCLK === 1'b1 && C_HAS_LOADB == 1 && intACLR !== 1'b1 && intLOADB_no_predelay === 1'bx && intCE !== 1'b0) + begin + loadb_count_no_predelay = -3; + intLOAD_DONE <= 1'bx; + if (C_HAS_SWAPB == 0) + intRFD_rel <= 1'bx; + else + intRFD_rel <= 1'b1; + end + else if (last_clk !== intCLK && last_clk === 1'b0 && intCLK === 1'b1 && C_HAS_LOADB == 1 && intACLR === 1'b0) + begin + if (intSCLR === 1'b1 && (intCE === 1'b1 || C_SYNC_ENABLE == 0)) + begin + intLOAD_DONE <= 1; + intRFD_rel <= 1; + if (loadb_count != -1 && loadb_count != -2) + begin + loadb_count_no_predelay <= -2; + end + end + else if (intSCLR === 1'bx && (intCE === 1'b1 || C_SYNC_ENABLE == 0)) + begin + if (loadb_count != -1 && loadb_count != -2) + begin + intLOAD_DONE <= 1'bx; + if (C_HAS_SWAPB == 0) + intRFD_rel <= 1'bx; + else + intRFD_rel <= 1'b1; + loadb_count_no_predelay <= -2-sig_addr_bits; + end + end + else if (intCE === 1'b1) + begin + if (intLOADB_no_predelay === 1'b1) + begin + loadb_count_no_predelay <= loadb_delay; + intLOAD_DONE <= 0; + if (C_HAS_SWAPB == 0) + intRFD_rel <= 0; + else + intRFD_rel <= 1; + + //If the load comes when the load_done is undefined in the following + //cases then the load_done signal goes to 'X' during the load. + if (C_HAS_SWAPB == 1 && loadb_count == -3 && (real_latency > 0 || C_REG_A_B_INPUTS == 1)) + stay_x <= 1; + else + stay_x <= 0; + + end + else //loadb == 0. + begin + if (loadb_count_no_predelay > 0) + begin + if (loadb_count_no_predelay > 0) + begin + loadb_count_no_predelay <= loadb_count_no_predelay - 1; + end + if (stay_x == 1) + intLOAD_DONE <= 1'bx; + else + intLOAD_DONE <= 1'b0; + end + else if (loadb_count_no_predelay <= -3) + begin + if (~(loadb_count != -2-sig_addr_bits && C_REG_A_B_INPUTS == 0 && real_latency == 0)) + // Wait for sig_addr_bits cycles before setting the op + // to undefined. + begin + if (C_HAS_SWAPB == 0) + intRFD_rel <= 1'bx; + else + intRFD_rel <= 1'b1; + intLOAD_DONE <= 1'bx; + end + end + else if (loadb_count_no_predelay == 0) + begin + intLOAD_DONE <= 1; + intRFD_rel <= 1; + stay_x <= 0; + if (ND_I === 1'b1 || (C_HAS_SWAPB == 1 || C_HAS_ND == 0 || C_REG_A_B_INPUTS == 1)) + begin + loadb_count_no_predelay <= -1; + end + end + else if (loadb_count_no_predelay == -2) + begin + intLOAD_DONE <= 1; + intRFD_rel <= 1; + end + end + end + else if (intCE === 1'bx) + begin + if (loadb_count != -1 && loadb_count != -2 && (loadb_count != -2-sig_addr_bits && C_REG_A_B_INPUTS == 0 && real_latency == 0)) + begin + end + else if (loadb_count == -2-sig_addr_bits || (loadb_count != -1 && loadb_count != -2 && (C_REG_A_B_INPUTS == 1 || real_latency > 0))) + // Propogate the 'X' through when the TC from the load engines + // counter goes to 'X' or if the inputs are registered. + begin + intLOAD_DONE <= 1'bx; + if (C_HAS_SWAPB == 0) + intRFD_rel <= 1'bx; + else + intRFD_rel <= 1'b1; + end + end + end + end + + //Loadb_count_dly will mask out the first reult after a load. This is + //necessary in some cases. + always@(intACLR) + begin + if (intACLR === 1'b1) + loadb_count_dly = -1; + loadb_count_dly_int = -1; + end + + always@(posedge intCLK) + begin + if (last_clk !== intCLK && last_clk === 1'b0 && intCLK === 1'b1 && intCE === 1'b1 && intACLR === 1'b0) + begin + loadb_count_dly_int <= loadb_count; + //if (ND_I === 1'b1 || (C_HAS_SWAPB == 1 || C_HAS_ND == 0 || C_REG_A_B_INPUTS == 1)) + //begin + loadb_count_dly <= loadb_count_dly_int; + //end + end + end + + //Do the B input calculation. This can be an input, a constant or a reloadable constant. + always@(B or b_const0 or b_const1 or intLOAD_DONE or ND_I or bank_sel or posedge intCLK) + begin + if (MULT_TYPE < 2) + begin + B_INPUT = B; + end + else if (~((MULT_TYPE < 3) || (loaded == 0 && intLOADB === 1'b0))) + begin + //if (intLOAD_DONE === 1'b1 || C_HAS_SWAPB == 1) + if (loadb_count == -1 || C_HAS_SWAPB == 1) + begin + if (bank_sel == 0 && MULT_TYPE > 2 && loaded == 1) + begin + if ((C_HAS_ND == 0) || (C_HAS_SWAPB == 1 && loadb_count < 0)) + begin + B_INPUT = b_const0; + end + else if (C_HAS_ND == 1 && C_HAS_SWAPB == 0 && ND_I == 1) + begin + B_INPUT = b_const0; + end + end + else if (bank_sel == 1 && MULT_TYPE > 2 && loaded == 1 && loadb_count < 0) + begin + B_INPUT = b_const1; + end + else if (bank_sel == 2 && MULT_TYPE > 2 && loaded == 1 && loadb_count < 0) + begin + B_INPUT = `ballxs; + end + end + else + begin + B_INPUT = `ballxs; + end + end + end + + //Swap between the two banks of memory if the core has a SWAPB pin. + always@(intACLR) + begin + if (C_HAS_SWAPB == 1) + begin + if (intACLR === 1'b1) + begin + bank_sel = 0; + bank_sel_pre = 0; + end + else if (intACLR === 1'bx) + begin + if (bank_sel != 0) + bank_sel = 2; + bank_sel_pre = 2; + end + end + end + + always@(posedge intCLK) + begin + if (last_clk !== intCLK && last_clk === 1'b0 && intCLK === 1'b1 && intACLR === 1'b0) + begin + if (intSCLR === 1'b1 && (intCE === 1'b1 || C_SYNC_ENABLE == 0)) + begin + bank_sel <= 0; + bank_sel_pre <= 0; + end + else if (intSCLR === 1'bx && (intCE === 1'b1 || C_SYNC_ENABLE == 0)) + begin + if (bank_sel != 0) + bank_sel <= 2; + bank_sel_pre <= 2; + end + else if (intSCLR === 1'b1 && (intCE === 1'bx || C_SYNC_ENABLE == 0)) + begin + if (bank_sel != 0) + bank_sel <= 2; + bank_sel_pre <= 2; + end + else if (intCE === 1'b1) + begin + if (C_REG_A_B_INPUTS == 0 && real_latency > 0 && C_HAS_SWAPB == 1) + begin + bank_sel <= bank_sel_pre; + end + + if ((C_REG_A_B_INPUTS == 1 || real_latency == 0) && C_HAS_SWAPB == 1 && intSWAPB === 1'b1 && loadb_count < 0) + begin + if (bank_sel == 0) + bank_sel <= 1 ; + else + bank_sel <= 0 ; + end + else if ((C_REG_A_B_INPUTS == 1 || real_latency == 0) && C_HAS_SWAPB == 1 && intSWAPB === 1'bx && loadb_count < 0) + begin + bank_sel <= 2 ; + end + else if (C_REG_A_B_INPUTS == 0 && real_latency > 0 && C_HAS_SWAPB == 1 && intSWAPB === 1'b1 && loadb_count < 0) + begin + if (bank_sel_pre == 0) + bank_sel_pre <= 1 ; + else + bank_sel_pre <= 0 ; + end + else if (C_REG_A_B_INPUTS == 0 && real_latency > 0 && C_HAS_SWAPB == 1 && intSWAPB === 1'bx && loadb_count < 0) + begin + bank_sel_pre <= 2 ; + end + end + else if (intCE === 1'bx) + begin + if ((C_REG_A_B_INPUTS == 1 || real_latency == 0) && C_HAS_SWAPB == 1 && intSWAPB !== 1'b0) + begin + bank_sel <= 2 ; + end + else if (C_REG_A_B_INPUTS == 0 && real_latency > 0 && C_HAS_SWAPB == 1 && intSWAPB !== 1'b0) + begin + bank_sel_pre <= 2 ; + end + end + end + else if (((last_clk !== intCLK && intCLK === 1'bx && last_clk === 1'b0) || + (last_clk !== intCLK && intCLK === 1'b1 && last_clk === 1'bx)) && + (intACLR !== 1'b1)) + begin + if ((C_REG_A_B_INPUTS == 1 || real_latency == 0) && C_HAS_SWAPB == 1 && intSWAPB !== 1'b0) + begin + bank_sel <= 2 ; + end + else if (C_REG_A_B_INPUTS == 0 && real_latency > 0 && C_HAS_SWAPB == 1 && intSWAPB !== 1'b0) + begin + bank_sel_pre <= 2 ; + end + end + end + + +/* helper functions */ + + function defval; + input i; + input hassig; + input val; + begin + if(hassig == 1) + defval = i; + else + defval = val; + end + endfunction + + function [C_B_WIDTH - 1 : 0] to_bitsB; + input [C_B_WIDTH*8 : 1] instring; + integer i; + integer non_null_string; + begin + non_null_string = 0; + for(i = C_B_WIDTH; i > 0; i = i - 1) + begin // Is the string empty? + if(instring[(i*8)] == 0 && + instring[(i*8)-1] == 0 && + instring[(i*8)-2] == 0 && + instring[(i*8)-3] == 0 && + instring[(i*8)-4] == 0 && + instring[(i*8)-5] == 0 && + instring[(i*8)-6] == 0 && + instring[(i*8)-7] == 0 && + non_null_string == 0) + non_null_string = 0; // Use the return value to flag a non-empty string + else + non_null_string = 1; // Non-null character! + end + if(non_null_string == 0) // String IS empty! Just return the value to be all '0's + begin + for(i = C_B_WIDTH; i > 0; i = i - 1) + to_bitsB[i-1] = 0; + end + else + begin + for(i = C_B_WIDTH; i > 0; i = i - 1) + begin // Is this character a '0'? (ASCII = 48 = 00110000) + if(instring[(i*8)] == 0 && + instring[(i*8)-1] == 0 && + instring[(i*8)-2] == 1 && + instring[(i*8)-3] == 1 && + instring[(i*8)-4] == 0 && + instring[(i*8)-5] == 0 && + instring[(i*8)-6] == 0 && + instring[(i*8)-7] == 0) + to_bitsB[i-1] = 0; + // Or is it a '1'? + else if(instring[(i*8)] == 0 && + instring[(i*8)-1] == 0 && + instring[(i*8)-2] == 1 && + instring[(i*8)-3] == 1 && + instring[(i*8)-4] == 0 && + instring[(i*8)-5] == 0 && + instring[(i*8)-6] == 0 && + instring[(i*8)-7] == 1) + to_bitsB[i-1] = 1; + // Or is it a ' '? (a null char - in which case insert a '0') + else if(instring[(i*8)] == 0 && + instring[(i*8)-1] == 0 && + instring[(i*8)-2] == 0 && + instring[(i*8)-3] == 0 && + instring[(i*8)-4] == 0 && + instring[(i*8)-5] == 0 && + instring[(i*8)-6] == 0 && + instring[(i*8)-7] == 0) + to_bitsB[i-1] = 0; + else + begin + $display("Error in %m at time %d ns: non-binary digit in string \"%s\"\nExiting simulation...",$time, instring); + $finish; + end + end + end + end + endfunction + + function findB_width; + input [C_B_WIDTH-1 : 0] b_input; + integer i; + begin + for(i = C_B_WIDTH-1; i > 0; i = i - 1) + begin + if(b_input[i] == 1) + findB_width = i ; + else + findB_width = findB_width ; + end + end + endfunction + + function modulus; + input a ; + input b ; + integer divide ; + begin + divide = (a < b ? 0 : (a / b)) ; + modulus = a - (b*divide) ; + end + endfunction + + function max; + input a; + input b; + begin + max = (a > b) ? a : b; + end + endfunction + + function is_X; + input [multWidth-1 : 0] i; + begin + is_X = 1'b0; + for(j = 0; j < multWidth; j = j + 1) + begin + if(i[j] === 1'bx) + is_X = 1'b1; + end // loop + end + endfunction + + function [C_OUT_WIDTH-1 : 0] mult_convert; + input [multWidth-1 : 0] in_sum; + integer bit_index; + begin + for(bit_index = C_OUT_WIDTH-1; bit_index >= 0; bit_index = bit_index - 1) + begin + if (out_width > C_OUT_WIDTH) + begin + mult_convert[bit_index] = in_sum[(out_width-C_OUT_WIDTH)+bit_index] ; + end + else + begin + if (bit_index <= out_width) + begin + mult_convert[bit_index] = in_sum[bit_index]; + end + else if (C_A_TYPE == `c_signed || (C_A_TYPE == `c_pin && tmpA_SIGNED == 1) + || C_B_TYPE == `c_signed) + begin + if (MULT_TYPE > 2 && C_HAS_LOADB == 1 && C_A_WIDTH == 1 && C_A_TYPE == `c_pin + && C_HAS_A_SIGNED == 1 && C_B_TYPE == `c_signed) + mult_convert[bit_index] = in_sum[out_width]; + else + mult_convert[bit_index] = in_sum[out_width-1]; + end + else + begin + if (is_X(in_sum)) + mult_convert[bit_index] = 1'bx; + else + mult_convert[bit_index] = 0; + end + end + end + end + endfunction + + function [multWidth-1 : 0] add; + input [multWidth-1 : 0] i1; + input [multWidth-1 : 0] i2; + integer bit_index; + integer carryin, carryout; + begin + carryin = 0; + carryout = 0; + for(bit_index=0; bit_index < multWidth; bit_index = bit_index + 1) + begin + if (i1[bit_index] === 1'bx || i2[bit_index] === 1'bx) + begin + add[bit_index] = 1'bx ; + carryout = 1'bx ; + carryin = carryout ; + end + else if (carryin === 1'bx) + begin + add[bit_index] = 1'bx ; + carryout = 0 ; + carryin = carryout ; + end + else + begin + add[bit_index] = i1[bit_index] ^ i2[bit_index] ^ carryin; + carryout = (i1[bit_index] && i2[bit_index]) || (carryin && (i1[bit_index] || i2[bit_index])); + carryin = carryout; + end + end + end + endfunction + +endmodule + +`undef c_set +`undef c_clear +`undef c_override +`undef c_no_override +`undef c_add +`undef c_sub +`undef c_add_sub +`undef c_signed +`undef c_unsigned +`undef c_pin +`undef allUKs +`undef all0s +`undef ball0s +`undef ballxs +`undef aall0s +`undef aallxs +`undef baatall0s +`undef baatall1s +`undef baatallxs +`undef c_distributed +`undef c_dp_block +`undef mall0s +`undef mallUKs +`undef inall0s + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/MULT_GEN_V7_0_SEQ.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/MULT_GEN_V7_0_SEQ.v new file mode 100644 index 0000000..edd4f28 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/MULT_GEN_V7_0_SEQ.v @@ -0,0 +1,940 @@ +// Copyright(C) 2004 by Xilinx, Inc. All rights reserved. +// This text contains proprietary, confidential +// information of Xilinx, Inc., is distributed +// under license from Xilinx, Inc., and may be used, +// copied and/or disclosed only pursuant to the terms +// of a valid license agreement with Xilinx, Inc. This copyright +// notice must be retained as part of this text at all times. + + +/* $Id: MULT_GEN_V7_0_SEQ.v,v 1.13 2008/09/08 20:09:14 akennedy Exp $ +-- +-- Filename - MULT_GEN_V7_0.v +-- Author - Xilinx +-- Creation - 22 Mar 1999 +-- +-- Description - This file contains the Verilog behavior for the sequential part of the multiplier module +*/ + +`timescale 1ns/10ps + +`define c_set 0 +`define c_clear 1 +`define c_override 0 +`define c_no_override 1 +`define c_add 0 +`define c_sub 1 +`define c_add_sub 2 +`define c_signed 0 +`define c_unsigned 1 +`define c_pin 2 +`define c_distributed 0 +`define c_dp_block 2 +`define allUKs {(C_OUT_WIDTH)+1{1'bx}} + +`define awidthall0s {C_A_WIDTH{1'b0}} +`define accumall0s {accum_width{1'b0}} +`define storeall0s {(C_BAAT*(number_clocks-1)){1'b0}} +`define aloadall0s {(C_BAAT*(number_clocks)){1'b0}} +`define accumpipeall0s {(C_LATENCY+1){1'b0}} +`define rfdpipeall0s {(number_clocks-C_REG_A_B_INPUTS){1'b0}} +`define multsignedpipeall0s {(C_REG_A_B_INPUTS+1-ccm_serial+temp_mult+mult_signed_pipe_rubbish+mult_signed_pipe_rubbish2){1'b0}} +`define accumsignpipeall0s {(C_LATENCY+accum_sign_pipe_rubbish2){1'b0}} +`define intrdypipeall0s {(rdy_delay+1){1'b0}} +`define accumcompall0s {(accum_width+accum_store_width){1'b0}} +`define outputall0s {C_OUT_WIDTH{1'b0}} +`define accumstoreall0s {accum_store_width{1'b0}} + +module MULT_GEN_V7_0_SEQ (A, B, CLK, A_SIGNED, CE, ACLR, + SCLR, LOADB, LOAD_DONE, SWAPB, RFD, + ND, RDY, O, Q); + + parameter BRAM_ADDR_WIDTH = 8; + parameter C_A_TYPE = `c_signed; + parameter C_A_WIDTH = 16; + parameter C_BAAT = 2; + parameter C_B_CONSTANT = `c_signed; + parameter C_B_TYPE = `c_signed; + parameter C_B_VALUE = "0000000000000001"; + parameter C_B_WIDTH = 16; + parameter C_ENABLE_RLOCS = 1; + parameter C_HAS_ACLR = 0; + parameter C_HAS_A_SIGNED = 0; + parameter C_HAS_B = 1; + parameter C_HAS_CE = 0; + parameter C_HAS_LOADB = 0; + parameter C_HAS_LOAD_DONE = 0; + parameter C_HAS_ND = 0; + parameter C_HAS_O = 0; + parameter C_HAS_Q = 1; + parameter C_HAS_RDY = 0; + parameter C_HAS_RFD = 0; + parameter C_HAS_SCLR = 0; + parameter C_HAS_SWAPB = 0; + parameter C_MEM_INIT_PREFIX = "mem"; + parameter C_MEM_TYPE = 0; + parameter C_MULT_TYPE = 0; + parameter C_OUTPUT_HOLD = 0; + parameter C_OUT_WIDTH = 16; + parameter C_PIPELINE = 0; + parameter C_REG_A_B_INPUTS = 1; + parameter C_SQM_TYPE = 0; + parameter C_STACK_ADDERS = 0; + parameter C_STANDALONE = 0; + parameter C_SYNC_ENABLE = 0; + parameter C_USE_LUTS = 1; + + //Internal parameters + + //has ce selection for final output register + parameter has_q_ce = ((C_HAS_CE == 1 || C_OUTPUT_HOLD == 1) ? 1 : 0); + //has_a_signed selectionf for internal multiplier + parameter mult_has_a_signed = (C_A_TYPE == `c_signed ? 1 : (C_HAS_A_SIGNED == 1 ? 1 : 0)); + //a_type for internal multiplier + parameter mult_a_type = (C_A_TYPE == `c_signed ? `c_pin : (C_A_TYPE == `c_pin ? `c_pin : `c_unsigned)); + //output width for internal multiplier + parameter mult_width = (C_B_TYPE == `c_signed ? C_BAAT + C_B_WIDTH : (C_B_WIDTH == 1 ? C_BAAT + mult_has_a_signed : C_BAAT + C_B_WIDTH + mult_has_a_signed)); + + + //***********************THIS SECTION CALCULATES INTERNAL MULTIPLIER LATENCY**************************************** + + parameter incA = (((mult_has_a_signed == 1 || mult_a_type == `c_signed) && C_B_TYPE == `c_unsigned) ? 1 : 0) ; + parameter incB = (C_B_TYPE == `c_signed ? 1 : 0) ; + parameter inc = ((C_B_TYPE == `c_unsigned && mult_a_type == `c_unsigned) ? 0 : 1) ; + parameter dec = ((C_B_TYPE == `c_unsigned && mult_a_type == `c_unsigned) ? 1 : 0) ; + parameter inc_a_width = 0; + parameter decrement = (mult_has_a_signed == 1 ? 1 : 0) ; + + //Parameters to calculate the latency for the parallel multiplier. + parameter a_ext_width_par = (mult_has_a_signed == 1 ? C_BAAT+1 : C_BAAT) ; + parameter a_ext_width_seq = ((mult_has_a_signed == 1 || mult_a_type == `c_signed) ? C_BAAT+1 : C_BAAT) ; + parameter a_ext_width = a_ext_width_par; + + /* Compare the width of the A port, to the width of the B port + If the A port is smaller, then swap these over, otherwise leave + alone */ + + parameter a_w = (C_BAAT < C_B_WIDTH ? C_B_WIDTH : a_ext_width); + parameter a_t = (C_BAAT < C_B_WIDTH ? C_B_TYPE : mult_a_type); + parameter b_w = (C_A_WIDTH < C_B_WIDTH ? a_ext_width : C_B_WIDTH); + parameter b_t = (C_A_WIDTH < C_B_WIDTH ? mult_a_type : C_B_TYPE); + + // The mult18 parameter signifies if the final mult18x18 primitive is used + // without having to pad with zeros, or sign extending - thus leading to + // a more efficient implementation - e.g. a 35x35 (signed x signed) multiplier + // mult18, is used in the calculation of a_prods and b_prods, which indicate + // how many mult18x18 primitives are requred. + + parameter mult18 = (((a_t == `c_signed && a_w % 17 == 1) + && ((b_t == `c_signed && b_w <= a_w) || (b_t == `c_unsigned && b_w < a_w))) ? 1 : 0); + + parameter a_prods = (a_ext_width-1)/(17 + mult18) + 1 ; + parameter b_prods = (C_B_WIDTH-1)/(17 + mult18) + 1 ; + parameter a_count = (a_ext_width+1)/2 ; + parameter b_count = (C_B_WIDTH+1)/2 ; + parameter parm_numAdders = (C_MULT_TYPE == 1 ? (a_prods*b_prods) : ((a_ext_width <= C_B_WIDTH) ? a_count : b_count)) ; + + //Parameters to calculate the latency for the constant coefficient multiplier. + parameter rom_addr_width = (C_MEM_TYPE == `c_distributed ? 4 : BRAM_ADDR_WIDTH) ; + parameter sig_addr_bits = (C_BAAT >= rom_addr_width ? rom_addr_width : C_BAAT) ; + parameter effective_op_width = ((mult_has_a_signed == 0 || C_HAS_LOADB == 1) ? C_BAAT : C_BAAT+1) ; + parameter a_input_width = ((effective_op_width % rom_addr_width == 0) ? effective_op_width : effective_op_width + rom_addr_width - (effective_op_width % rom_addr_width)) ; + parameter mod = a_input_width % rom_addr_width ; + parameter op_width = (mod == 0 ? a_input_width : (a_input_width + rom_addr_width) - mod) ; + parameter a_width = op_width; + parameter need_addsub = ((C_HAS_LOADB == 1 && (mult_a_type == `c_signed || mult_has_a_signed == 1)) ? 1 : 0) ; + parameter ccm_numAdders_1 = (mod == 0 ? (a_input_width/rom_addr_width) : (a_input_width/rom_addr_width)+1) ; + parameter need_0_minus_pp = ((need_addsub == 1 && ccm_numAdders_1 <= 1) ? 1 : 0) ; + parameter ccm_numAdders = (need_0_minus_pp == 1 ? 1 : ccm_numAdders_1 - 1) ; + parameter ccm_init1 = ((C_HAS_LOADB == 1 && C_MEM_TYPE == `c_dp_block) ? 1 : 0) ; + parameter ccm_init2 = ((C_HAS_LOADB == 1 && (mult_a_type == `c_signed || mult_has_a_signed == 1) && C_PIPELINE == 1) ? 1 : 0) ; + parameter ccm_init3 = (((ccm_numAdders > 0 || C_HAS_SWAPB == 1) && (C_PIPELINE == 1 || C_MEM_TYPE == `c_dp_block)) ? 1 : 0) ; + parameter ccm_init4 = ((ccm_numAdders > 0 && C_HAS_SWAPB == 1 && C_PIPELINE == 1) ? 1 : 0) ; + parameter ccm_initial_latency = ccm_init1 + ccm_init2 + ccm_init3 + ccm_init4 ; + parameter add_one = 0 ; + parameter extra_cycles = 0 ; + + //Latency calculation + parameter numAdders = (C_MULT_TYPE < 2 ? parm_numAdders - 1 : ccm_numAdders) ; + parameter log = (C_PIPELINE == 1 ? (numAdders < 2 ? 0 : (numAdders < 4 ? 1 : (numAdders < 8 ? 2 : (numAdders < 16 ? 3 : (numAdders < 32 ? 4 : (numAdders < 64 ? 5 : (numAdders < 128 ? 6 : 7))))))) : 0) ; + parameter C_LATENCY_sub = (C_MULT_TYPE < 2 ? (numAdders > 0 ? (extra_cycles + log + 1) : 0) : (numAdders > 0 ? (ccm_initial_latency + extra_cycles + log + add_one) : ccm_initial_latency)) ; + parameter C_LATENCY_nonseq = (C_PIPELINE == 1 ? C_LATENCY_sub : (C_MULT_TYPE < 2 ? 0 : C_LATENCY_sub)) ; //+extra_latency : 0) ; + parameter serial_adjust1 = (C_SQM_TYPE == 1 && C_MULT_TYPE > 1 ) ? 1 : 0 ; + parameter serial_adjust = (C_SQM_TYPE == 1 && C_MULT_TYPE > 1) ? 1 : 0 ; + parameter blk_mem_adjust = ((C_MULT_TYPE > 1 && C_MEM_TYPE == `c_dp_block && C_PIPELINE == 0 && ccm_numAdders_1 == 1) ? 1 : 0) ; // && C_LATENCY_nonseq == 0) ? 1 : 0) ; + parameter slicer_adjust = 0; // && C_PIPELINE == 0)) ? 1 : 0) ; + parameter reg_adjust = (C_SQM_TYPE == 0 && C_PIPELINE == 0 && C_LATENCY_nonseq == 0 ? 1 : 0) ; + parameter pipe_adjust = ((C_SQM_TYPE == 1 && C_PIPELINE == 0 && serial_adjust == 0) ? 1 : 0) ; + parameter C_LATENCY_seq = C_LATENCY_nonseq + slicer_adjust + blk_mem_adjust ; + parameter nd_adjust = (C_HAS_ND == 1 && C_LATENCY_nonseq > 1 ) ? 1 : 0 ; //&& ~(C_MEM_TYPE == `c_dp_block && C_HAS_LOADB == 1 && C_HAS_SWAPB == 1 && C_PIPELINE == 0)) ? 1 : 0 ; + parameter desperation = C_PIPELINE ; + parameter C_LATENCY = (C_LATENCY_nonseq+C_PIPELINE+blk_mem_adjust); + //********************************************************************************************************** + + //Parameters to calculate the number of cycles that the sequential mult takes to process the inputs. + parameter div_cycle = (C_A_WIDTH/C_BAAT) ; + parameter mod_cycle = (C_A_WIDTH - (C_BAAT*div_cycle)) ; + parameter no_of_cycles = (mod_cycle == 0 ? div_cycle : div_cycle+1) ; + parameter number_clocks = no_of_cycles; + + //Determine if the slicer is going to be avoided + parameter ccm_serial = (C_SQM_TYPE == 1 ? (C_MULT_TYPE >= 2 ? 1 : 0) : 0); + //Calculate pipeline delay for the accum_sign + parameter accum_delay = C_LATENCY-ccm_serial; + //Calculate is accum_sign is actually needed + parameter accum_sign_needed = (C_B_TYPE == `c_signed ? 1 : (mult_has_a_signed == 1 ? 1 : 0)); + //Calculate size of mult_width + sign extension if needed + parameter accum_mult_width = mult_width + accum_sign_needed; + //Calculate pipeline delay for ready + parameter rdy_delay = C_HAS_Q+C_REG_A_B_INPUTS+C_LATENCY-ccm_serial+2-C_OUTPUT_HOLD; + //Calculate size of accumulator output + parameter accum_width = mult_width+1; //accum_mult_width+1; + //Calculate size of accumulator storage bits + parameter accum_store_width = (C_BAAT*(number_clocks-1)); + //Determine if internal multiplier has an rfd + parameter mult_has_rfd = (C_HAS_SWAPB ? 0 : (C_HAS_LOADB ? 1 : 0)); + //Offsets to ensure that verilog does not complain about reverse logic unnecessarily + parameter temp_offset = (C_A_WIDTH == (C_BAAT*number_clocks) ? 1 : 0); + parameter temp_mult = (C_REG_A_B_INPUTS+1-ccm_serial <= 1 ? 2-C_REG_A_B_INPUTS+1-ccm_serial : 0); + parameter temp_accum = 0; //(accum_store_width > C_BAAT ? 0 : C_BAAT); + parameter temp_mult_out = (accum_mult_width > 1 ? 0 : 1); + //Calculate predelay value for internal multiplier + parameter predelay = (C_MULT_TYPE > 2 ? 1 + C_REG_A_B_INPUTS - C_SQM_TYPE : 0); + parameter rubbish = (C_LATENCY == 0 ? 1 : 0); + parameter accum_sign_pipe_rubbish = (C_LATENCY == 0 ? 1 : 0); + parameter accum_sign_pipe_rubbish2 = (C_LATENCY < 2 ? 2 : 0); + parameter mult_signed_pipe_rubbish = (C_REG_A_B_INPUTS+1-ccm_serial == 0 ? 1 : 0); + parameter mult_signed_pipe_rubbish2 = (C_REG_A_B_INPUTS+1-ccm_serial < 2 ? 1 : 0); + parameter intO_rubbish = (C_A_WIDTH+C_B_WIDTH+C_HAS_A_SIGNED-C_OUT_WIDTH > 0 ? C_A_WIDTH+C_B_WIDTH+C_HAS_A_SIGNED-C_OUT_WIDTH : 0); + + parameter ncelab_accum_complete_low = ((C_OUT_WIDTH <= C_A_WIDTH+C_B_WIDTH+C_HAS_A_SIGNED) ? (C_A_WIDTH+C_B_WIDTH+C_HAS_A_SIGNED-C_OUT_WIDTH) : 0); + parameter ncelab_into_high = ((C_OUT_WIDTH <= C_A_WIDTH+C_B_WIDTH+C_HAS_A_SIGNED) ? (C_OUT_WIDTH) : (C_A_WIDTH+C_B_WIDTH+C_HAS_A_SIGNED)); + + parameter ncelab_rfd_pipe_select = ((number_clocks-C_REG_A_B_INPUTS-1 > 0) ? number_clocks-C_REG_A_B_INPUTS-2 : 0); + parameter ncelab_rfd_pipe_low = ((number_clocks-C_REG_A_B_INPUTS > 1) ? 1 : 0); + + parameter ncelab_accum_store_low = ((accum_store_width > C_BAAT) ? C_BAAT : 0); + parameter ncelab_accum_store_high = ((accum_store_width > C_BAAT) ? (accum_store_width-C_BAAT) : accum_store_width); + + input [(C_A_WIDTH-1-((C_A_WIDTH-1)*C_SQM_TYPE)) : 0] A; + input [C_B_WIDTH-1 : 0] B; + input CLK; + input CE; + input A_SIGNED; + input LOADB; + input SWAPB; + input ND; + input ACLR; + input SCLR; + output RFD; + output RDY; + output LOAD_DONE; + output [C_OUT_WIDTH-1 : 0] O; + output [C_OUT_WIDTH-1 : 0] Q; + + //Clock enable signal for q registers + wire int_q_ce; + //Held a_input + reg [(C_BAAT*number_clocks)-1 : 0] a_load; + wire [C_B_WIDTH-1 : 0] regB; + wire [(C_A_WIDTH-1-((C_A_WIDTH-1)*C_SQM_TYPE)) : 0] regA; + wire [C_B_WIDTH-1 : 0] regBB; + wire [(C_A_WIDTH-1-((C_A_WIDTH-1)*C_SQM_TYPE)) : 0] regAA; + wire intCE; + reg intA_SIGNED; + wire regA_SIGNED; + wire intACLR; + wire intSCLR; + wire initial_intCLK; + reg intCLK; + reg last_clk; + wire intLOADB; + wire intSWAPB = (C_HAS_SWAPB ? SWAPB : 0); + wire regND; + wire intND ; + reg intRFD; + reg reg_rfd; + wire intLOAD_DONE; + reg [C_OUT_WIDTH-1 : 0 ] intO; + wire [C_OUT_WIDTH-1 : 0] intQ; + wire a_signed_held; + reg accum_load; + wire RDY; + reg [C_LATENCY+1 : 0] accum_pipe; + reg [number_clocks-C_REG_A_B_INPUTS-1 : 0] rfd_pipe; + wire intSCLR_pure; + wire a_slice_load; + wire a_slice_load_sclr; + wire [C_BAAT-1 : 0] a_slice; + wire [C_B_WIDTH-1 : 0] b_held; + wire [C_B_WIDTH-1 : 0] b_reg; + wire [(C_A_WIDTH-1-((C_A_WIDTH-1)*C_SQM_TYPE)) : 0] a_reg; + wire a_signed_reg; + wire slice_rfd; + wire int_nd; + reg [accum_width+accum_store_width-1 : 0] accum_complete; + reg [accum_width-1 : 0] accum_out; + reg [accum_store_width-1 : 0] accum_store; + reg [accum_width-1 : 0] accum_feedback; + wire int_sclr_loadb_swapb; + wire int_a_signed; + wire pipe_rfd; + wire mult_signed; + reg int_mult_signed1; + reg int_mult_signed2; + reg int_mult_signed3; + wire pipe_mult_signed; + reg [C_REG_A_B_INPUTS+1-ccm_serial+temp_mult+mult_signed_pipe_rubbish+mult_signed_pipe_rubbish2 : 0] mult_signed_pipe; + reg [accum_mult_width-1 : 0] accum_in; + wire [mult_width-1 : 0] mult_out; + reg accum_sign; + reg [C_LATENCY-1+accum_sign_pipe_rubbish2 : 0] accum_sign_pipe; + reg int_rdy; + reg int_rdy_op_hold; + reg int_rfd_reg; + wire accum_mult_out_msb; + + wire [C_OUT_WIDTH-1 : 0] Q = (C_HAS_Q == 1 ? intQ : `allUKs); + wire [C_OUT_WIDTH-1 : 0] O = (C_HAS_O == 1 ? intO : `allUKs); + wire RFD = (C_HAS_RFD == 1 ? intRFD : 1'bx); + wire LOAD_DONE = (C_HAS_LOAD_DONE == 1 ? intLOAD_DONE : 1'bx); + wire [mult_width-1 : 0] mult_o; + wire [mult_width-1 : 0] mult_q; + wire dummy; + wire mult_rfd; + reg [rdy_delay : 0] int_rdy_pipe; + reg [C_B_WIDTH-1 : 0] initB_INPUT; + + integer i, b_width, shift_bits, real_latency, real_rdy_delay; + + assign intCE = (C_HAS_CE == 1 ? CE : 1); + assign initial_intCLK = CLK; + assign intACLR = (C_HAS_ACLR == 1 ? ACLR : 0) ; + //Combine SCLR with CE where appropriate depending on C_SYNC_ENABLE + assign intSCLR = (C_HAS_SCLR == 1 ? (C_HAS_CE == 1 ? (C_SYNC_ENABLE == 0 ? SCLR : SCLR & CE) : SCLR) : 0); + assign intSCLR_pure = (C_HAS_SCLR == 1 ? SCLR : 0); + + assign int_nd = (C_HAS_ND == 1 ? (C_REG_A_B_INPUTS == 1 ? regND : ND) : 1); + assign a_slice_load = intCE & int_nd & slice_rfd; + //Combine a_slice_load with sclr and CE where appropriate depending on C_SYNC_ENABLE + assign a_slice_load_sclr = (C_HAS_SCLR == 1 ? (C_SYNC_ENABLE == 1 ? a_slice_load | (intSCLR & intCE) : a_slice_load) : a_slice_load); + assign a_slice = a_load[C_BAAT-1 : 0]; + assign b_held = (C_MULT_TYPE < 2 ? regBB : (C_MULT_TYPE > 2 ? B : b_reg)); + assign a_reg = (C_REG_A_B_INPUTS == 1 ? regA : A); + assign b_reg = (C_REG_A_B_INPUTS == 1 ? regB : B); + assign a_signed_reg = (C_REG_A_B_INPUTS == 1 ? regA_SIGNED : A_SIGNED); + assign slice_rfd = (C_REG_A_B_INPUTS == 1 ? reg_rfd : intRFD); + //Combine int_sclr, loadb and swapb, CE and mult_rfd to reset rfd as appropriate depending on C_SYNC_ENABLE + assign int_sclr_loadb_swapb = (C_HAS_SWAPB == 1 ? ((C_SYNC_ENABLE == 1 && C_HAS_CE == 1) ? (intSCLR | (intSWAPB & intCE)) : intSCLR | intSWAPB) : (C_HAS_LOADB == 1 ? ((C_SYNC_ENABLE == 1 && C_HAS_CE == 1) ? (intSCLR | ((!mult_rfd) & intCE)) : intSCLR | (!mult_rfd)) : intSCLR)); + assign int_a_signed = (C_HAS_A_SIGNED == 1 ? a_signed_held : (C_A_TYPE == `c_signed && C_SQM_TYPE == 0 ? 1 : 0)); + assign pipe_rfd = (number_clocks-C_REG_A_B_INPUTS-1 > 0 ? rfd_pipe[ncelab_rfd_pipe_select] : a_slice_load_sclr); + assign mult_signed = (C_HAS_A_SIGNED == 1 ? (C_REG_A_B_INPUTS+1-ccm_serial == 0 ? int_mult_signed1 : pipe_mult_signed) : pipe_mult_signed & a_slice[C_BAAT-1]); + assign pipe_mult_signed = (C_REG_A_B_INPUTS+1-ccm_serial == 0 ? pipe_rfd : mult_signed_pipe[C_REG_A_B_INPUTS+1-ccm_serial-1+mult_signed_pipe_rubbish]); + + assign RDY = (C_HAS_RDY == 1 ? (C_OUTPUT_HOLD == 1 ? int_rdy_op_hold : int_rdy) : 1'bx); + + assign mult_out = (C_PIPELINE == 1 ? mult_q : (blk_mem_adjust == 1 ? mult_q : mult_o)); + assign int_q_ce = (C_OUTPUT_HOLD == 1 ? (intCE & int_rdy) : intCE); + assign accum_mult_out_msb = accum_in[accum_mult_width-1]; + assign intLOADB = (C_HAS_LOADB == 1 ? LOADB : 1'b0); + + MULT_GEN_V7_0_NON_SEQ #(BRAM_ADDR_WIDTH, mult_a_type, C_BAAT, C_BAAT, C_B_CONSTANT, C_B_TYPE, + C_B_VALUE, C_B_WIDTH, C_ENABLE_RLOCS, C_HAS_ACLR, mult_has_a_signed, + C_HAS_B, C_HAS_CE, C_HAS_LOADB, C_HAS_LOAD_DONE, 0, 1, + 1, 0, mult_has_rfd, C_HAS_SCLR, C_HAS_SWAPB, C_MEM_INIT_PREFIX, + C_MEM_TYPE, C_MULT_TYPE, 0, mult_width, C_PIPELINE, predelay, 0, 0, 1, + 0, C_SYNC_ENABLE, C_USE_LUTS) + int_mult (.A(a_slice), .B(b_held), .CLK(intCLK), .A_SIGNED(mult_signed), .CE(intCE), .ACLR(intACLR), + .SCLR(intSCLR), .LOADB(intLOADB), .LOAD_DONE(intLOAD_DONE), .SWAPB(intSWAPB), .RFD(mult_rfd), + .ND(1'b0), .RDY(dummy), .O(mult_o), .Q(mult_q)); + + C_REG_FD_V7_0 #("0", C_ENABLE_RLOCS, C_HAS_ACLR, 0, 0, + C_HAS_CE, C_HAS_SCLR, 0, 0, + "0", C_SYNC_ENABLE, 0, (C_A_WIDTH-1-((C_A_WIDTH-1)*C_SQM_TYPE))+1) + rega (.D(A), .CLK(intCLK), .CE(intCE), .ACLR(intACLR), .ASET(1'b0), + .AINIT(1'b0), .SCLR(intSCLR_pure), .SSET(1'b0), .SINIT(1'b0), + .Q(regA)); + + C_REG_FD_V7_0 #("0", C_ENABLE_RLOCS, C_HAS_ACLR, 0, 0, + C_HAS_CE, C_HAS_SCLR, 0, 0, + "0", C_SYNC_ENABLE, 0, C_B_WIDTH) + regb (.D(B), .CLK(intCLK), .CE(intCE), .ACLR(intACLR), .ASET(1'b0), + .AINIT(1'b0), .SCLR(intSCLR_pure), .SSET(1'b0), .SINIT(1'b0), + .Q(regB)); + + C_REG_FD_V7_0 #("0", C_ENABLE_RLOCS, C_HAS_ACLR, 0, 0, + 1, C_HAS_SCLR, 0, 0, + "0", C_SYNC_ENABLE, 0, C_B_WIDTH) + regbb (.D(b_reg), .CLK(intCLK), .CE(a_slice_load_sclr), .ACLR(intACLR), .ASET(1'b0), + .AINIT(1'b0), .SCLR(intSCLR_pure), .SSET(1'b0), .SINIT(1'b0), + .Q(regBB)); + + C_REG_FD_V7_0 #("0", C_ENABLE_RLOCS, C_HAS_ACLR, 0, 0, + has_q_ce, C_HAS_SCLR, 0, 0, + "0", C_SYNC_ENABLE, 0, C_OUT_WIDTH) + regq (.D(intO), .CLK(intCLK), .CE(int_q_ce), .ACLR(intACLR), .ASET(1'b0), + .AINIT(1'b0), .SCLR(intSCLR_pure), .SSET(1'b0), .SINIT(1'b0), + .Q(intQ)); + + C_REG_FD_V7_0 #("0", C_ENABLE_RLOCS, C_HAS_ACLR, 0, 0, + C_HAS_CE, C_HAS_SCLR, 0, 0, + "0", C_SYNC_ENABLE, 0, 1) + regnd (.D(ND), .CLK(intCLK), .CE(intCE), .ACLR(intACLR), .ASET(1'b0), + .AINIT(1'b0), .SCLR(intSCLR_pure), .SSET(1'b0), .SINIT(1'b0), + .Q(regND)); + + C_REG_FD_V7_0 #("0", C_ENABLE_RLOCS, C_HAS_ACLR, 0, 0, + C_HAS_CE, C_HAS_SCLR, 0, 0, + "0", C_SYNC_ENABLE, 0, 1) + regasig (.D(A_SIGNED), .CLK(intCLK), .CE(intCE), .ACLR(intACLR), .ASET(1'b0), + .AINIT(1'b0), .SCLR(intSCLR_pure), .SSET(1'b0), .SINIT(1'b0), + .Q(regA_SIGNED)); + + C_REG_FD_V7_0 #("0", C_ENABLE_RLOCS, C_HAS_ACLR, 0, 0, + C_HAS_CE, C_HAS_SCLR, 0, 0, + "0", C_SYNC_ENABLE, 0, 1) + regmultmsb (.D(accum_mult_out_msb), .CLK(intCLK), .CE(intCE), .ACLR(intACLR), .ASET(1'b0), + .AINIT(1'b0), .SCLR(intSCLR_pure), .SSET(1'b0), .SINIT(1'b0), + .Q(accum_mult_out_msb_delayed)); + + C_REG_FD_V7_0 #("0", C_ENABLE_RLOCS, 0, 0, 0, + 1, 0, 0, 0, + "0", C_SYNC_ENABLE, 0, 1) + latchasig (.D(a_signed_reg), .CLK(intCLK), .CE(a_slice_load_sclr), .ACLR(1'b0), .ASET(1'b0), + .AINIT(1'b0), .SCLR(1'b0), .SSET(1'b0), .SINIT(1'b0), + .Q(a_signed_held)); + + initial + begin + intRFD = 1 ; + int_rfd_reg = 1; + int_rdy_pipe = `intrdypipeall0s; + rfd_pipe = `rfdpipeall0s; + reg_rfd = 0; + + int_rdy = 0; + int_rdy_op_hold = 0; + + accum_out = `accumall0s; + accum_store = `accumstoreall0s; + + //Calculate the shift bits + initB_INPUT = (C_MULT_TYPE < 2) ? B : to_bitsB(C_B_VALUE); + + //Find the real b input width + if (C_MULT_TYPE > 1 && C_HAS_LOADB == 0) + begin + b_width = 0 ; + for(i = 0; i < C_B_WIDTH; i = i + 1) + begin + if(initB_INPUT[i] == 1) + b_width = i+1 ; + end + end + else + begin + b_width = C_B_WIDTH ; + end + + if (C_MULT_TYPE != 2) + begin + shift_bits = 0 ; + end + else + begin + shift_bits = 0 ; + for(i = C_B_WIDTH-1; i >= 0; i = i - 1) + begin + if (initB_INPUT[i] == 1) + shift_bits = i ; + end + end + + if ((C_B_TYPE == `c_unsigned && (b_width-shift_bits) == 1 && C_HAS_LOADB == 0) || (C_HAS_LOADB == 0 && b_width == 0)) + begin + real_latency = C_PIPELINE+blk_mem_adjust ; + end + else + begin + real_latency = C_LATENCY ; + end + + real_rdy_delay = C_HAS_Q+C_REG_A_B_INPUTS+real_latency-ccm_serial+2-C_OUTPUT_HOLD; + + end + + always@(initial_intCLK) + begin + last_clk <= intCLK ; + intCLK <= initial_intCLK ; + end + + always@(accum_pipe or a_slice_load_sclr) + begin + if ((real_latency-ccm_serial) >= 0) + accum_load = accum_pipe[real_latency-ccm_serial]; + else + accum_load = a_slice_load_sclr; + end + + always@(accum_sign_pipe or mult_signed) + begin + if (real_latency > 0) + accum_sign = accum_sign_pipe[real_latency+accum_sign_pipe_rubbish-1]; + else + accum_sign = mult_signed; + end + + always@(int_rdy_pipe) + begin + if (real_rdy_delay > 0) + begin + int_rdy = int_rdy_pipe[real_rdy_delay-1]; + int_rdy_op_hold = int_rdy_pipe[real_rdy_delay]; + end + else + begin + int_rdy = int_rdy_pipe[0]; + int_rdy_op_hold = int_rdy_pipe[0]; + end + end + + //Process to calculate output when the clears go high. + //In addition action on the SWAPB and LOADB pins also cause the sequential multiplier to + //de-assert RFD. + always@(intACLR or intSCLR or int_sclr_loadb_swapb or int_rfd_reg) + begin + if (intACLR == 1 || int_sclr_loadb_swapb == 1) + intRFD = 0 ; + else + intRFD = int_rfd_reg; + end + + //Register rfd for serial parallel type + always@(posedge intCLK) + begin + if (int_sclr_loadb_swapb == 1) + reg_rfd <= 0; + else + begin + if (intCE == 1 && intACLR != 1) + reg_rfd <= intRFD; + end + end + + //int_rfd_reg + always@(posedge intCLK) + begin + if (int_sclr_loadb_swapb == 1) + int_rfd_reg <= 1; + else + begin + if (intCE == 1 && intACLR != 1) + begin + if (C_HAS_ND == 1) + int_rfd_reg <= (pipe_rfd && !intRFD) || (intRFD && !ND); + else + int_rfd_reg <= pipe_rfd && !intRFD; + end + end + end + + //mult_sign serial + always@(pipe_rfd or a_signed_reg or a_signed_held) + begin + if (C_HAS_A_SIGNED == 1 && C_REG_A_B_INPUTS+1-ccm_serial == 0) + begin + if (number_clocks-C_REG_A_B_INPUTS == 1) + int_mult_signed1 <= pipe_rfd & a_signed_reg; + else + int_mult_signed1 <= pipe_rfd & a_signed_held; + end + end + + //int_mult_signed + always@(pipe_rfd or a_signed_reg or a_signed_held or pipe_mult_signed or a_slice) + begin + if (C_HAS_A_SIGNED == 1) + begin + if (number_clocks-C_REG_A_B_INPUTS == 1) + int_mult_signed2 <= pipe_rfd & a_signed_reg; + else + int_mult_signed2 <= pipe_rfd & a_signed_held; + end + else + int_mult_signed2 <= pipe_rfd; + end + + //int_rdy + always@(posedge intCLK) + begin + if (intSCLR == 1) + int_rdy_pipe <= `intrdypipeall0s; + else if (intCE == 1 && intACLR == 0) + begin + if (rdy_delay > 0) + int_rdy_pipe[rdy_delay : 1] <= int_rdy_pipe[rdy_delay-1 : 0]; + int_rdy_pipe[0] <= pipe_rfd; + end + end + + + //For a serial, CCM type, we don't need any slicing + always@(a_reg) + begin + if (C_SQM_TYPE == 1 && C_MULT_TYPE >= 2) + a_load <= a_reg; + end + + //Aclr all registers + always@(intACLR) + begin + if (intACLR == 1) + begin + if (C_SQM_TYPE != 1 || C_MULT_TYPE < 2) + a_load = `aloadall0s; + accum_out = `accumall0s; + accum_store = `storeall0s; + if (real_latency >= 0) + accum_pipe = `accumpipeall0s; + rfd_pipe = `rfdpipeall0s; + reg_rfd = 0; + int_rfd_reg = 1; + if (C_REG_A_B_INPUTS+1-ccm_serial > 0) + mult_signed_pipe[C_REG_A_B_INPUTS+1-ccm_serial+mult_signed_pipe_rubbish+mult_signed_pipe_rubbish2-1 : 0] <= `multsignedpipeall0s; + int_mult_signed2 = 0; + if (real_latency > 0) + accum_sign_pipe <= `accumsignpipeall0s; + int_rdy_pipe <= `intrdypipeall0s; + end + end + + //Pipelines + always@(posedge intCLK) + begin + if (intSCLR == 1) + begin + if (real_latency >= 0) + accum_pipe <= `accumpipeall0s; + if (C_REG_A_B_INPUTS+1-ccm_serial > 0) + mult_signed_pipe[C_REG_A_B_INPUTS+1-ccm_serial+mult_signed_pipe_rubbish+mult_signed_pipe_rubbish2-1 : 0] <= `multsignedpipeall0s; + end + else if (intCE == 1 && intACLR == 0) + begin + if (C_LATENCY > 0) + accum_pipe[C_LATENCY+rubbish : 1] <= accum_pipe[C_LATENCY+rubbish-1 : 0]; + if (real_latency >= 0) + accum_pipe[0] <= a_slice_load_sclr; + if (C_REG_A_B_INPUTS+1-ccm_serial > 1) + mult_signed_pipe[C_REG_A_B_INPUTS+1-ccm_serial-1+temp_mult+mult_signed_pipe_rubbish+mult_signed_pipe_rubbish2 : 1] <= mult_signed_pipe[C_REG_A_B_INPUTS+1-ccm_serial-2+temp_mult+mult_signed_pipe_rubbish+mult_signed_pipe_rubbish2 : 0]; + if (C_REG_A_B_INPUTS+1-ccm_serial+temp_mult > 0) + mult_signed_pipe[0] <= int_mult_signed2; + end + end + + //rfd pipeline + always@(posedge intCLK) + begin + if (int_sclr_loadb_swapb == 1) + rfd_pipe <= `rfdpipeall0s; + else + begin + if (intCE == 1 && intACLR == 0) + begin + if (number_clocks-C_REG_A_B_INPUTS > 1) + rfd_pipe[number_clocks-C_REG_A_B_INPUTS-1 : ncelab_rfd_pipe_low] <= rfd_pipe[ncelab_rfd_pipe_select : 0]; + rfd_pipe[0] <= a_slice_load_sclr; + end + end + end + + //Slice the A input + always@(posedge intCLK) + begin + if (intSCLR == 1) + begin + if (C_SQM_TYPE != 1 || C_MULT_TYPE < 2) + a_load <= `aloadall0s; + end + else if (intCE == 1 && intACLR != 1) + begin + if (C_SQM_TYPE == 0) //need to slice + begin + if (a_slice_load == 1) + begin + a_load[C_A_WIDTH-1 : 0] <= a_reg; + for (i = 0; i < (C_BAAT*number_clocks)-C_A_WIDTH; i = i + 1) //sign extend as required + begin + if (C_HAS_A_SIGNED == 1) + begin + if (a_signed_reg == 1) + a_load[(C_BAAT*number_clocks)+temp_offset-1-i] <= a_reg[C_A_WIDTH-1-((C_A_WIDTH-1)*C_SQM_TYPE)]; + else + a_load[(C_BAAT*number_clocks)+temp_offset-1-i] <= 0; + end + else if (C_A_TYPE == `c_signed) + a_load[(C_BAAT*number_clocks)+temp_offset-1-i] <= a_reg[C_A_WIDTH-1-((C_A_WIDTH-1)*C_SQM_TYPE)]; + else + a_load[(C_BAAT*number_clocks)+temp_offset-1-i] <= 0; + end + end + else + begin + a_load[(C_BAAT*(number_clocks-1))-1 : 0] <= a_load[(C_BAAT*number_clocks)-1 : C_BAAT]; + for (i = 0; i < C_BAAT; i = i + 1) + begin + if (int_a_signed == 1) + a_load[(C_BAAT*number_clocks)-1-i] <= a_load[(C_BAAT*number_clocks)-1]; + else + a_load[(C_BAAT*number_clocks)-1-i] <= 0; + end + end + end + else //need to pipeline balance if parm + begin + if (C_MULT_TYPE < 2) + begin + if ((intCE == 1 && slice_rfd == 0) || a_slice_load == 1) + a_load <= a_reg; + end + end + end + end + + //Accumulate result + always@(posedge intCLK) + begin + if (intSCLR == 1) + begin + accum_out <= `accumall0s; + accum_store <= `storeall0s; + end + else if (intCE == 1 && intACLR != 1) + begin + if (accum_store_width > C_BAAT) + //accum_store[accum_store_width-1-C_BAAT+temp_accum : 0] <= accum_store[accum_store_width-1+temp_accum : C_BAAT]; + accum_store[ncelab_accum_store_high-1 : 0] <= accum_store[accum_store_width-1+temp_accum : ncelab_accum_store_low]; + accum_store[accum_store_width-1 : accum_store_width-C_BAAT] <= accum_out[C_BAAT-1 : 0]; + if (accum_load == 1) + accum_out <= accum_in; + else + accum_out <= accum_in + accum_feedback; + end + end + + //Feedback accumulator output + always@(accum_out) + begin + accum_feedback[accum_width-C_BAAT-1 : 0] <= accum_out[accum_width-1 : C_BAAT]; + if (C_B_TYPE == `c_signed) + begin + for(i = 0; i < C_BAAT; i = i + 1) + accum_feedback[accum_width-1-i] <= accum_out[accum_width-1]; + end + else + begin + for(i = 0; i < C_BAAT; i = i + 1) + accum_feedback[accum_width-1-i] <= 0; + end + end + + //accum_in + always@(mult_out or accum_sign) + begin + if (accum_sign_needed == 1) + begin + if (C_B_TYPE == `c_signed) + accum_in[accum_mult_width-1] = mult_out[accum_mult_width-2+temp_mult_out]; + else if (mult_has_a_signed == 1) + accum_in[accum_mult_width-1] = accum_sign & mult_out[accum_mult_width-2+temp_mult_out]; + end + else + accum_in[accum_mult_width-1] = mult_out[mult_width-1]; + end + + always@(mult_out) + begin + if (accum_mult_width > 1) + accum_in[accum_mult_width-2+temp_mult_out : 0] = mult_out[accum_mult_width-2+temp_mult_out :0]; + end + + //accum_sign + always@(posedge intCLK) + begin + if (intSCLR == 1) + begin + if (real_latency > 0) + accum_sign_pipe <= `accumsignpipeall0s; + end + else if (intCE == 1 && intACLR != 1) + begin + if (real_latency > 1) + accum_sign_pipe[C_LATENCY-1+(accum_sign_pipe_rubbish2) : 1] <= accum_sign_pipe[C_LATENCY-2+(accum_sign_pipe_rubbish2) : 0]; + if (real_latency > 0) + accum_sign_pipe[0] <= mult_signed; + end + end + + //accum_complete + always@(accum_out or accum_store) + begin + accum_complete[accum_width+accum_store_width-1 : accum_store_width] = accum_out[accum_width-1 : 0]; //removed padding + accum_complete[accum_store_width-1 : 0] = accum_store; + end + + //O generation + always@(accum_complete or accum_mult_out_msb_delayed) + begin + if (C_OUT_WIDTH <= C_A_WIDTH+C_B_WIDTH+C_HAS_A_SIGNED) //accum_width+accum_store_width-padding) + //intO <= accum_complete[C_A_WIDTH+C_B_WIDTH+C_HAS_A_SIGNED-1 : C_A_WIDTH+C_B_WIDTH+C_HAS_A_SIGNED-C_OUT_WIDTH]; + intO[ncelab_into_high-1:0] <= accum_complete[C_A_WIDTH+C_B_WIDTH+C_HAS_A_SIGNED-1 : ncelab_accum_complete_low]; + else + begin + intO[C_A_WIDTH+C_B_WIDTH+C_HAS_A_SIGNED-1-intO_rubbish : 0] <= accum_complete[C_A_WIDTH+C_B_WIDTH+C_HAS_A_SIGNED-1-intO_rubbish : 0]; + if (accum_sign_needed == 1) + begin + if (C_B_TYPE == `c_signed) + begin + for (i = 0; i < (C_OUT_WIDTH-(C_A_WIDTH+C_B_WIDTH+C_HAS_A_SIGNED)); i = i+1) + intO[C_OUT_WIDTH-1-i] <= accum_complete[accum_width+accum_store_width-1]; //C_A_WIDTH+C_B_WIDTH+C_HAS_A_SIGNED-1]; + end + else + begin + for (i = 0; i < (C_OUT_WIDTH-(C_A_WIDTH+C_B_WIDTH+C_HAS_A_SIGNED)); i = i+1) + intO[C_OUT_WIDTH-1-i] <= accum_mult_out_msb_delayed; + end + end + else + begin + for (i = 0; i < (C_OUT_WIDTH-(C_A_WIDTH+C_B_WIDTH+C_HAS_A_SIGNED)); i = i+1) + intO[C_OUT_WIDTH-1-i] <= 0; + end + end + end + + function [C_B_WIDTH - 1 : 0] to_bitsB; + input [C_B_WIDTH*8 : 1] instring; + integer i; + integer non_null_string; + begin + non_null_string = 0; + for(i = C_B_WIDTH; i > 0; i = i - 1) + begin // Is the string empty? + if(instring[(i*8)] == 0 && + instring[(i*8)-1] == 0 && + instring[(i*8)-2] == 0 && + instring[(i*8)-3] == 0 && + instring[(i*8)-4] == 0 && + instring[(i*8)-5] == 0 && + instring[(i*8)-6] == 0 && + instring[(i*8)-7] == 0 && + non_null_string == 0) + non_null_string = 0; // Use the return value to flag a non-empty string + else + non_null_string = 1; // Non-null character! + end + if(non_null_string == 0) // String IS empty! Just return the value to be all '0's + begin + for(i = C_B_WIDTH; i > 0; i = i - 1) + to_bitsB[i-1] = 0; + end + else + begin + for(i = C_B_WIDTH; i > 0; i = i - 1) + begin // Is this character a '0'? (ASCII = 48 = 00110000) + if(instring[(i*8)] == 0 && + instring[(i*8)-1] == 0 && + instring[(i*8)-2] == 1 && + instring[(i*8)-3] == 1 && + instring[(i*8)-4] == 0 && + instring[(i*8)-5] == 0 && + instring[(i*8)-6] == 0 && + instring[(i*8)-7] == 0) + to_bitsB[i-1] = 0; + // Or is it a '1'? + else if(instring[(i*8)] == 0 && + instring[(i*8)-1] == 0 && + instring[(i*8)-2] == 1 && + instring[(i*8)-3] == 1 && + instring[(i*8)-4] == 0 && + instring[(i*8)-5] == 0 && + instring[(i*8)-6] == 0 && + instring[(i*8)-7] == 1) + to_bitsB[i-1] = 1; + // Or is it a ' '? (a null char - in which case insert a '0') + else if(instring[(i*8)] == 0 && + instring[(i*8)-1] == 0 && + instring[(i*8)-2] == 0 && + instring[(i*8)-3] == 0 && + instring[(i*8)-4] == 0 && + instring[(i*8)-5] == 0 && + instring[(i*8)-6] == 0 && + instring[(i*8)-7] == 0) + to_bitsB[i-1] = 0; + else + begin + $display("Error in %m at time %d ns: non-binary digit in string \"%s\"\nExiting simulation...",$time, instring); + $finish; + end + end + end + end + endfunction + +endmodule + +`undef c_set +`undef c_clear +`undef c_override +`undef c_no_override +`undef c_add +`undef c_sub +`undef c_add_sub +`undef c_signed +`undef c_unsigned +`undef c_pin +`undef c_distributed +`undef c_dp_block +`undef awidthall0s +`undef accumall0s +`undef storeall0s +`undef aloadall0s +`undef accumpipeall0s +`undef rfdpipeall0s +`undef multsignedpipeall0s +`undef accumsignpipeall0s +`undef intrdypipeall0s +`undef allUKs +`undef accumcompall0s +`undef outputall0s +`undef accumstoreall0s + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/PIPELINE_V4_0.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/PIPELINE_V4_0.v new file mode 100644 index 0000000..203945f --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/PIPELINE_V4_0.v @@ -0,0 +1,273 @@ +/* $Id: PIPELINE_V4_0.v,v 1.11 2008/09/08 20:05:46 akennedy Exp $ +-- +-- Filename - PIPELINE_V4_0.v +-- Author - Xilinx +-- Creation - 21 Oct 1998 +-- +-- Description - This file contains the Verilog behavior for the baseblocks utility PIPELINE module +*/ + + +`define allXs {C_WIDTH{1'bx}} +`define all1s {C_WIDTH{1'b1}} + +module PIPELINE_V4_0 (D, CLK, CE, ACLR, ASET, AINIT, SCLR, SSET, SINIT, Q); + + parameter C_AINIT_VAL = ""; + parameter C_HAS_ACLR = 0; + parameter C_HAS_AINIT = 0; + parameter C_HAS_ASET = 0; + parameter C_HAS_CE = 0; + parameter C_HAS_SCLR = 0; + parameter C_HAS_SINIT = 0; + parameter C_HAS_SSET = 0; + parameter C_PIPE_STAGES = 1; + parameter C_SINIT_VAL = ""; + parameter C_SYNC_ENABLE = 0; // c_override + parameter C_SYNC_PRIORITY = 1; // c_clear + parameter C_WIDTH = 16; + + + input [C_WIDTH-1 : 0] D; + input CLK; + input CE; + input ACLR; + input ASET; + input AINIT; + input SCLR; + input SSET; + input SINIT; + output [C_WIDTH-1 : 0] Q; + + reg [C_WIDTH-1 : 0] pipeliner [0 : C_PIPE_STAGES-1]; + reg [C_WIDTH-1 : 0] intQ; + // Internal values to drive signals when input is missing + wire intCE; + wire intACLR; + wire intASET; + wire intAINIT; + wire intSCLR; + wire intSSET; + wire intSINIT; + + wire [C_WIDTH-1 : 0] #1 Q = intQ; + + // Sort out default values for missing ports + + assign intCE = defval(CE, C_HAS_CE, 1); + assign intACLR = defval(ACLR, C_HAS_ACLR, 0); + assign intASET = defval(ASET, C_HAS_ASET, 0); + assign intAINIT = defval(AINIT, C_HAS_AINIT, 0); + assign intSCLR = defval(SCLR, C_HAS_SCLR, 0); + assign intSSET = defval(SSET, C_HAS_SSET, 0); + assign intSINIT = defval(SINIT, C_HAS_SINIT, 0); + + reg lastCLK; + reg lastintACLR; + reg lastintASET; + + reg [C_WIDTH-1 : 0] AIV; + reg [C_WIDTH-1 : 0] SIV; + + reg cetmp; + reg set_or_clr; + + integer i; + + initial + begin + lastCLK = 1'b0; + lastintACLR = 1'b0; + lastintASET = 1'b0; + AIV = to_bits(C_AINIT_VAL); + SIV = to_bits(C_SINIT_VAL); + set_or_clr = (C_SYNC_PRIORITY === 0)?1'b0:1'b1; + for(i = 0; i < C_PIPE_STAGES; i = i + 1) + pipeliner[i] = 'b0; + if(C_PIPE_STAGES != 0) + begin + if(C_HAS_ACLR === 1) + pipeliner[C_PIPE_STAGES-1] = 'b0; + else if(C_HAS_ASET === 1) + pipeliner[C_PIPE_STAGES-1] = `all1s; + else if(C_HAS_AINIT === 1) + pipeliner[C_PIPE_STAGES-1] = AIV; + else if(C_HAS_SCLR === 1) + pipeliner[C_PIPE_STAGES-1] = 'b0; + else if(C_HAS_SSET === 1) + pipeliner[C_PIPE_STAGES-1] = `all1s; + else if(C_HAS_SINIT === 1) + pipeliner[C_PIPE_STAGES-1] = SIV; + else + pipeliner[C_PIPE_STAGES-1] = AIV; + intQ = pipeliner[C_PIPE_STAGES-1]; + end + else + assign intQ = D; + end + + always@(posedge CLK or intACLR or intASET or intAINIT) + begin + // Do not do anything if there is no pipeline + if(C_PIPE_STAGES > 0) + begin + // deal with synchronous events first + if (CLK !== lastCLK && CLK !== 1'bx && lastCLK !== 1'bx) + begin + // First the pipeline + if(intCE === 1'bx) + for(i = 0; i < C_PIPE_STAGES; i = i + 1) + pipeliner[i] = `allXs; + else if(intCE === 1'b1) + for(i = C_PIPE_STAGES-1; i > 0; i = i - 1) + pipeliner[i] = pipeliner[i-1]; + + // Unqualified behaviour + if(intCE === 1'b1) + pipeliner[0] = D; + + // Synchronous controls + if(C_SYNC_ENABLE === 0) + cetmp = 1'b1; + else + cetmp = intCE; + + if(cetmp === 1'b1) + begin + if((set_or_clr === 1'b0 && intSSET === 1'bx) || + (set_or_clr === 1'b1 && intSCLR === 1'bx) || + intSINIT === 1'bx) + pipeliner[0] = `allXs; + else if(intSINIT === 1'b1) //Synchronous init + pipeliner[0] = SIV; + else if(intSCLR === 1'b1 && (set_or_clr === 1'b1 || intSSET === 1'b0)) //Synchronous clear + pipeliner[0] = 'b0; + else if(intSSET === 1'b1 && (set_or_clr === 1'b0 || intSCLR === 1'b0)) //Synchronous set + pipeliner[0] = `all1s; + end + end + else if(CLK !== lastCLK && (CLK === 1'bx || lastCLK === 1'bx)) + begin + if(intCE !== 1'b0) + for(i = 0; i < C_PIPE_STAGES; i = i + 1) + pipeliner[i] = `allXs; + else if (C_SYNC_ENABLE === 0) + pipeliner[0] = `allXs; + end + + //Asynchronous Controls - over ride synchronous effects + if(intACLR === 1'bx) + pipeliner[C_PIPE_STAGES-1] = `allXs; + else if(intACLR === 1'b1) + pipeliner[C_PIPE_STAGES-1] = 'b0; + else if(intACLR === 1'b0 && intASET === 1'bx) + pipeliner[C_PIPE_STAGES-1] = `allXs; + else if(intACLR === 1'b0 && intASET === 1'b1) + pipeliner[C_PIPE_STAGES-1] = `all1s; + else if(intAINIT === 1'bx) + pipeliner[C_PIPE_STAGES-1] = `allXs; + else if(intAINIT === 1'b1) + pipeliner[C_PIPE_STAGES-1] = AIV; + + intQ <= pipeliner[C_PIPE_STAGES-1]; + end + end + + always@(intACLR or intASET) + begin + lastintACLR <= intACLR; + lastintASET <= intASET; +// if($time != 0) +// if(intACLR === 1'b0 && intASET === 1'b0 && lastintACLR !== 1'b0 && lastintASET !== 1'b0) // RACE +// pipeliner[C_PIPE_STAGES] = `allXs; + end + + always@(CLK) + lastCLK <= CLK; + + + function defval; + input i; + input hassig; + input val; + begin + if(hassig == 1) + defval = i; + else + defval = val; + end + endfunction + + function [C_WIDTH - 1 : 0] to_bits; + input [C_WIDTH*8 : 1] instring; + integer i; + integer non_null_string; + begin + non_null_string = 0; + for(i = C_WIDTH; i > 0; i = i - 1) + begin // Is the string empty? + if(instring[(i*8)] == 0 && + instring[(i*8)-1] == 0 && + instring[(i*8)-2] == 0 && + instring[(i*8)-3] == 0 && + instring[(i*8)-4] == 0 && + instring[(i*8)-5] == 0 && + instring[(i*8)-6] == 0 && + instring[(i*8)-7] == 0 && + non_null_string == 0) + non_null_string = 0; // Use the return value to flag a non-empty string + else + non_null_string = 1; // Non-null character! + end + if(non_null_string == 0) // String IS empty! Just return the value to be all '0's + begin + for(i = C_WIDTH; i > 0; i = i - 1) + to_bits[i-1] = 0; + end + else + begin + for(i = C_WIDTH; i > 0; i = i - 1) + begin // Is this character a '0'? (ASCII = 48 = 00110000) + if(instring[(i*8)] == 0 && + instring[(i*8)-1] == 0 && + instring[(i*8)-2] == 1 && + instring[(i*8)-3] == 1 && + instring[(i*8)-4] == 0 && + instring[(i*8)-5] == 0 && + instring[(i*8)-6] == 0 && + instring[(i*8)-7] == 0) + to_bits[i-1] = 0; + // Or is it a '1'? + else if(instring[(i*8)] == 0 && + instring[(i*8)-1] == 0 && + instring[(i*8)-2] == 1 && + instring[(i*8)-3] == 1 && + instring[(i*8)-4] == 0 && + instring[(i*8)-5] == 0 && + instring[(i*8)-6] == 0 && + instring[(i*8)-7] == 1) + to_bits[i-1] = 1; + // Or is it a ' '? (a null char - in which case insert a '0') + else if(instring[(i*8)] == 0 && + instring[(i*8)-1] == 0 && + instring[(i*8)-2] == 0 && + instring[(i*8)-3] == 0 && + instring[(i*8)-4] == 0 && + instring[(i*8)-5] == 0 && + instring[(i*8)-6] == 0 && + instring[(i*8)-7] == 0) + to_bits[i-1] = 0; + else + begin + $display("Error: non-binary digit in string \"%s\"\nExiting simulation...", instring); + $finish; + end + end + end + end + endfunction + +endmodule + +`undef allXs + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/PIPELINE_V5_0.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/PIPELINE_V5_0.v new file mode 100644 index 0000000..a2aa5bf --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/PIPELINE_V5_0.v @@ -0,0 +1,274 @@ +/* $Id: PIPELINE_V5_0.v,v 1.17 2008/09/08 20:05:56 akennedy Exp $ +-- +-- Filename - PIPELINE_V5_0.v +-- Author - Xilinx +-- Creation - 21 Oct 1998 +-- +-- Description - This file contains the Verilog behavior for the baseblocks utility PIPELINE module +*/ + +`timescale 1ns/10ps + +`define allXs {C_WIDTH{1'bx}} +`define all1s {C_WIDTH{1'b1}} + +module PIPELINE_V5_0 (D, CLK, CE, ACLR, ASET, AINIT, SCLR, SSET, SINIT, Q); + + parameter C_AINIT_VAL = ""; + parameter C_HAS_ACLR = 0; + parameter C_HAS_AINIT = 0; + parameter C_HAS_ASET = 0; + parameter C_HAS_CE = 0; + parameter C_HAS_SCLR = 0; + parameter C_HAS_SINIT = 0; + parameter C_HAS_SSET = 0; + parameter C_PIPE_STAGES = 1; + parameter C_SINIT_VAL = ""; + parameter C_SYNC_ENABLE = 0; // c_override + parameter C_SYNC_PRIORITY = 1; // c_clear + parameter C_WIDTH = 16; + + + input [C_WIDTH-1 : 0] D; + input CLK; + input CE; + input ACLR; + input ASET; + input AINIT; + input SCLR; + input SSET; + input SINIT; + output [C_WIDTH-1 : 0] Q; + + reg [C_WIDTH-1 : 0] pipeliner [0 : C_PIPE_STAGES-1]; + reg [C_WIDTH-1 : 0] intQ; + // Internal values to drive signals when input is missing + wire intCE; + wire intACLR; + wire intASET; + wire intAINIT; + wire intSCLR; + wire intSSET; + wire intSINIT; + + wire [C_WIDTH-1 : 0] #1 Q = intQ; + + // Sort out default values for missing ports + + assign intCE = defval(CE, C_HAS_CE, 1); + assign intACLR = defval(ACLR, C_HAS_ACLR, 0); + assign intASET = defval(ASET, C_HAS_ASET, 0); + assign intAINIT = defval(AINIT, C_HAS_AINIT, 0); + assign intSCLR = defval(SCLR, C_HAS_SCLR, 0); + assign intSSET = defval(SSET, C_HAS_SSET, 0); + assign intSINIT = defval(SINIT, C_HAS_SINIT, 0); + + reg lastCLK; + reg lastintACLR; + reg lastintASET; + + reg [C_WIDTH-1 : 0] AIV; + reg [C_WIDTH-1 : 0] SIV; + + reg cetmp; + reg set_or_clr; + + integer i; + + initial + begin + lastCLK = 1'b0; + lastintACLR = 1'b0; + lastintASET = 1'b0; + AIV = to_bits(C_AINIT_VAL); + SIV = to_bits(C_SINIT_VAL); + set_or_clr = (C_SYNC_PRIORITY === 0)?1'b0:1'b1; + for(i = 0; i < C_PIPE_STAGES; i = i + 1) + pipeliner[i] = 'b0; + if(C_PIPE_STAGES != 0) + begin + if(C_HAS_ACLR === 1) + pipeliner[C_PIPE_STAGES-1] = 'b0; + else if(C_HAS_ASET === 1) + pipeliner[C_PIPE_STAGES-1] = `all1s; + else if(C_HAS_AINIT === 1) + pipeliner[C_PIPE_STAGES-1] = AIV; + else if(C_HAS_SCLR === 1) + pipeliner[C_PIPE_STAGES-1] = 'b0; + else if(C_HAS_SSET === 1) + pipeliner[C_PIPE_STAGES-1] = `all1s; + else if(C_HAS_SINIT === 1) + pipeliner[C_PIPE_STAGES-1] = SIV; + else + pipeliner[C_PIPE_STAGES-1] = AIV; + intQ = pipeliner[C_PIPE_STAGES-1]; + end + else + assign intQ = D; + end + + always@(posedge CLK or intACLR or intASET or intAINIT) + begin + // Do not do anything if there is no pipeline + if(C_PIPE_STAGES > 0) + begin + // deal with synchronous events first + if (CLK !== lastCLK && CLK !== 1'bx && lastCLK !== 1'bx) + begin + // First the pipeline + if(intCE === 1'bx) + for(i = 0; i < C_PIPE_STAGES; i = i + 1) + pipeliner[i] = `allXs; + else if(intCE === 1'b1) + for(i = C_PIPE_STAGES-1; i > 0; i = i - 1) + pipeliner[i] = pipeliner[i-1]; + + // Unqualified behaviour + if(intCE === 1'b1) + pipeliner[0] = D; + + // Synchronous controls + if(C_SYNC_ENABLE === 0) + cetmp = 1'b1; + else + cetmp = intCE; + + if(cetmp === 1'b1) + begin + if((set_or_clr === 1'b0 && intSSET === 1'bx) || + (set_or_clr === 1'b1 && intSCLR === 1'bx) || + intSINIT === 1'bx) + pipeliner[0] = `allXs; + else if(intSINIT === 1'b1) //Synchronous init + pipeliner[0] = SIV; + else if(intSCLR === 1'b1 && (set_or_clr === 1'b1 || intSSET === 1'b0)) //Synchronous clear + pipeliner[0] = 'b0; + else if(intSSET === 1'b1 && (set_or_clr === 1'b0 || intSCLR === 1'b0)) //Synchronous set + pipeliner[0] = `all1s; + end + end + else if(CLK !== lastCLK && (CLK === 1'bx || lastCLK === 1'bx)) + begin + if(intCE !== 1'b0) + for(i = 0; i < C_PIPE_STAGES; i = i + 1) + pipeliner[i] = `allXs; + else if (C_SYNC_ENABLE === 0) + pipeliner[0] = `allXs; + end + + //Asynchronous Controls - over ride synchronous effects + if(intACLR === 1'bx) + pipeliner[C_PIPE_STAGES-1] = `allXs; + else if(intACLR === 1'b1) + pipeliner[C_PIPE_STAGES-1] = 'b0; + else if(intACLR === 1'b0 && intASET === 1'bx) + pipeliner[C_PIPE_STAGES-1] = `allXs; + else if(intACLR === 1'b0 && intASET === 1'b1) + pipeliner[C_PIPE_STAGES-1] = `all1s; + else if(intAINIT === 1'bx) + pipeliner[C_PIPE_STAGES-1] = `allXs; + else if(intAINIT === 1'b1) + pipeliner[C_PIPE_STAGES-1] = AIV; + + intQ <= pipeliner[C_PIPE_STAGES-1]; + end + end + + always@(intACLR or intASET) + begin + lastintACLR <= intACLR; + lastintASET <= intASET; +// if($time != 0) +// if(intACLR === 1'b0 && intASET === 1'b0 && lastintACLR !== 1'b0 && lastintASET !== 1'b0) // RACE +// pipeliner[C_PIPE_STAGES] = `allXs; + end + + always@(CLK) + lastCLK <= CLK; + + + function defval; + input i; + input hassig; + input val; + begin + if(hassig == 1) + defval = i; + else + defval = val; + end + endfunction + + function [C_WIDTH - 1 : 0] to_bits; + input [C_WIDTH*8 : 1] instring; + integer i; + integer non_null_string; + begin + non_null_string = 0; + for(i = C_WIDTH; i > 0; i = i - 1) + begin // Is the string empty? + if(instring[(i*8)] == 0 && + instring[(i*8)-1] == 0 && + instring[(i*8)-2] == 0 && + instring[(i*8)-3] == 0 && + instring[(i*8)-4] == 0 && + instring[(i*8)-5] == 0 && + instring[(i*8)-6] == 0 && + instring[(i*8)-7] == 0 && + non_null_string == 0) + non_null_string = 0; // Use the return value to flag a non-empty string + else + non_null_string = 1; // Non-null character! + end + if(non_null_string == 0) // String IS empty! Just return the value to be all '0's + begin + for(i = C_WIDTH; i > 0; i = i - 1) + to_bits[i-1] = 0; + end + else + begin + for(i = C_WIDTH; i > 0; i = i - 1) + begin // Is this character a '0'? (ASCII = 48 = 00110000) + if(instring[(i*8)] == 0 && + instring[(i*8)-1] == 0 && + instring[(i*8)-2] == 1 && + instring[(i*8)-3] == 1 && + instring[(i*8)-4] == 0 && + instring[(i*8)-5] == 0 && + instring[(i*8)-6] == 0 && + instring[(i*8)-7] == 0) + to_bits[i-1] = 0; + // Or is it a '1'? + else if(instring[(i*8)] == 0 && + instring[(i*8)-1] == 0 && + instring[(i*8)-2] == 1 && + instring[(i*8)-3] == 1 && + instring[(i*8)-4] == 0 && + instring[(i*8)-5] == 0 && + instring[(i*8)-6] == 0 && + instring[(i*8)-7] == 1) + to_bits[i-1] = 1; + // Or is it a ' '? (a null char - in which case insert a '0') + else if(instring[(i*8)] == 0 && + instring[(i*8)-1] == 0 && + instring[(i*8)-2] == 0 && + instring[(i*8)-3] == 0 && + instring[(i*8)-4] == 0 && + instring[(i*8)-5] == 0 && + instring[(i*8)-6] == 0 && + instring[(i*8)-7] == 0) + to_bits[i-1] = 0; + else + begin + $display("Error in %m at time %d ns: non-binary digit in string \"%s\"\nExiting simulation...", $time, instring); + $finish; + end + end + end + end + endfunction + +endmodule + +`undef allXs +`undef all1s diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/PIPELINE_V6_0.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/PIPELINE_V6_0.v new file mode 100644 index 0000000..9a6aad5 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/PIPELINE_V6_0.v @@ -0,0 +1,283 @@ +// Copyright(C) 2002 by Xilinx, Inc. All rights reserved. +// This text contains proprietary, confidential +// information of Xilinx, Inc., is distributed +// under license from Xilinx, Inc., and may be used, +// copied and/or disclosed only pursuant to the terms +// of a valid license agreement with Xilinx, Inc. This copyright +// notice must be retained as part of this text at all times. + + +/* $Id: PIPELINE_V6_0.v,v 1.16 2008/09/08 20:06:05 akennedy Exp $ +-- +-- Filename - PIPELINE_V6_0.v +-- Author - Xilinx +-- Creation - 21 Oct 1998 +-- +-- Description - This file contains the Verilog behavior for the baseblocks utility PIPELINE module +*/ + +`timescale 1ns/10ps + +`define allXs {C_WIDTH{1'bx}} +`define all1s {C_WIDTH{1'b1}} + +module PIPELINE_V6_0 (D, CLK, CE, ACLR, ASET, AINIT, SCLR, SSET, SINIT, Q); + + parameter C_AINIT_VAL = ""; + parameter C_HAS_ACLR = 0; + parameter C_HAS_AINIT = 0; + parameter C_HAS_ASET = 0; + parameter C_HAS_CE = 0; + parameter C_HAS_SCLR = 0; + parameter C_HAS_SINIT = 0; + parameter C_HAS_SSET = 0; + parameter C_PIPE_STAGES = 1; + parameter C_SINIT_VAL = ""; + parameter C_SYNC_ENABLE = 0; // c_override + parameter C_SYNC_PRIORITY = 1; // c_clear + parameter C_WIDTH = 16; + + + input [C_WIDTH-1 : 0] D; + input CLK; + input CE; + input ACLR; + input ASET; + input AINIT; + input SCLR; + input SSET; + input SINIT; + output [C_WIDTH-1 : 0] Q; + + reg [C_WIDTH-1 : 0] pipeliner [0 : C_PIPE_STAGES-1]; + reg [C_WIDTH-1 : 0] intQ; + // Internal values to drive signals when input is missing + wire intCE; + wire intACLR; + wire intASET; + wire intAINIT; + wire intSCLR; + wire intSSET; + wire intSINIT; + + wire [C_WIDTH-1 : 0] #1 Q = intQ; + + // Sort out default values for missing ports + + assign intCE = defval(CE, C_HAS_CE, 1); + assign intACLR = defval(ACLR, C_HAS_ACLR, 0); + assign intASET = defval(ASET, C_HAS_ASET, 0); + assign intAINIT = defval(AINIT, C_HAS_AINIT, 0); + assign intSCLR = defval(SCLR, C_HAS_SCLR, 0); + assign intSSET = defval(SSET, C_HAS_SSET, 0); + assign intSINIT = defval(SINIT, C_HAS_SINIT, 0); + + reg lastCLK; + reg lastintACLR; + reg lastintASET; + + reg [C_WIDTH-1 : 0] AIV; + reg [C_WIDTH-1 : 0] SIV; + + reg cetmp; + reg set_or_clr; + + integer i; + + initial + begin + lastCLK = 1'b0; + lastintACLR = 1'b0; + lastintASET = 1'b0; + AIV = to_bits(C_AINIT_VAL); + SIV = to_bits(C_SINIT_VAL); + set_or_clr = (C_SYNC_PRIORITY === 0)?1'b0:1'b1; + for(i = 0; i < C_PIPE_STAGES; i = i + 1) + pipeliner[i] = 'b0; + if(C_PIPE_STAGES != 0) + begin + if(C_HAS_ACLR === 1) + pipeliner[C_PIPE_STAGES-1] = 'b0; + else if(C_HAS_ASET === 1) + pipeliner[C_PIPE_STAGES-1] = `all1s; + else if(C_HAS_AINIT === 1) + pipeliner[C_PIPE_STAGES-1] = AIV; + else if(C_HAS_SCLR === 1) + pipeliner[C_PIPE_STAGES-1] = 'b0; + else if(C_HAS_SSET === 1) + pipeliner[C_PIPE_STAGES-1] = `all1s; + else if(C_HAS_SINIT === 1) + pipeliner[C_PIPE_STAGES-1] = SIV; + else + pipeliner[C_PIPE_STAGES-1] = AIV; + intQ = pipeliner[C_PIPE_STAGES-1]; + end + else + assign intQ = D; + end + + always@(posedge CLK or intACLR or intASET or intAINIT) + begin + // Do not do anything if there is no pipeline + if(C_PIPE_STAGES > 0) + begin + // deal with synchronous events first + if (CLK !== lastCLK && CLK !== 1'bx && lastCLK !== 1'bx) + begin + // First the pipeline + if(intCE === 1'bx) + for(i = 0; i < C_PIPE_STAGES; i = i + 1) + pipeliner[i] = `allXs; + else if(intCE === 1'b1) + for(i = C_PIPE_STAGES-1; i > 0; i = i - 1) + pipeliner[i] = pipeliner[i-1]; + + // Unqualified behaviour + if(intCE === 1'b1) + pipeliner[0] = D; + + // Synchronous controls + if(C_SYNC_ENABLE === 0) + cetmp = 1'b1; + else + cetmp = intCE; + + if(cetmp === 1'b1) + begin + if((set_or_clr === 1'b0 && intSSET === 1'bx) || + (set_or_clr === 1'b1 && intSCLR === 1'bx) || + intSINIT === 1'bx) + pipeliner[0] = `allXs; + else if(intSINIT === 1'b1) //Synchronous init + pipeliner[0] = SIV; + else if(intSCLR === 1'b1 && (set_or_clr === 1'b1 || intSSET === 1'b0)) //Synchronous clear + pipeliner[0] = 'b0; + else if(intSSET === 1'b1 && (set_or_clr === 1'b0 || intSCLR === 1'b0)) //Synchronous set + pipeliner[0] = `all1s; + end + end + else if(CLK !== lastCLK && (CLK === 1'bx || lastCLK === 1'bx)) + begin + if(intCE !== 1'b0) + for(i = 0; i < C_PIPE_STAGES; i = i + 1) + pipeliner[i] = `allXs; + else if (C_SYNC_ENABLE === 0) + pipeliner[0] = `allXs; + end + + //Asynchronous Controls - over ride synchronous effects + if(intACLR === 1'bx) + pipeliner[C_PIPE_STAGES-1] = `allXs; + else if(intACLR === 1'b1) + pipeliner[C_PIPE_STAGES-1] = 'b0; + else if(intACLR === 1'b0 && intASET === 1'bx) + pipeliner[C_PIPE_STAGES-1] = `allXs; + else if(intACLR === 1'b0 && intASET === 1'b1) + pipeliner[C_PIPE_STAGES-1] = `all1s; + else if(intAINIT === 1'bx) + pipeliner[C_PIPE_STAGES-1] = `allXs; + else if(intAINIT === 1'b1) + pipeliner[C_PIPE_STAGES-1] = AIV; + + intQ <= pipeliner[C_PIPE_STAGES-1]; + end + end + + always@(intACLR or intASET) + begin + lastintACLR <= intACLR; + lastintASET <= intASET; +// if($time != 0) +// if(intACLR === 1'b0 && intASET === 1'b0 && lastintACLR !== 1'b0 && lastintASET !== 1'b0) // RACE +// pipeliner[C_PIPE_STAGES] = `allXs; + end + + always@(CLK) + lastCLK <= CLK; + + + function defval; + input i; + input hassig; + input val; + begin + if(hassig == 1) + defval = i; + else + defval = val; + end + endfunction + + function [C_WIDTH - 1 : 0] to_bits; + input [C_WIDTH*8 : 1] instring; + integer i; + integer non_null_string; + begin + non_null_string = 0; + for(i = C_WIDTH; i > 0; i = i - 1) + begin // Is the string empty? + if(instring[(i*8)] == 0 && + instring[(i*8)-1] == 0 && + instring[(i*8)-2] == 0 && + instring[(i*8)-3] == 0 && + instring[(i*8)-4] == 0 && + instring[(i*8)-5] == 0 && + instring[(i*8)-6] == 0 && + instring[(i*8)-7] == 0 && + non_null_string == 0) + non_null_string = 0; // Use the return value to flag a non-empty string + else + non_null_string = 1; // Non-null character! + end + if(non_null_string == 0) // String IS empty! Just return the value to be all '0's + begin + for(i = C_WIDTH; i > 0; i = i - 1) + to_bits[i-1] = 0; + end + else + begin + for(i = C_WIDTH; i > 0; i = i - 1) + begin // Is this character a '0'? (ASCII = 48 = 00110000) + if(instring[(i*8)] == 0 && + instring[(i*8)-1] == 0 && + instring[(i*8)-2] == 1 && + instring[(i*8)-3] == 1 && + instring[(i*8)-4] == 0 && + instring[(i*8)-5] == 0 && + instring[(i*8)-6] == 0 && + instring[(i*8)-7] == 0) + to_bits[i-1] = 0; + // Or is it a '1'? + else if(instring[(i*8)] == 0 && + instring[(i*8)-1] == 0 && + instring[(i*8)-2] == 1 && + instring[(i*8)-3] == 1 && + instring[(i*8)-4] == 0 && + instring[(i*8)-5] == 0 && + instring[(i*8)-6] == 0 && + instring[(i*8)-7] == 1) + to_bits[i-1] = 1; + // Or is it a ' '? (a null char - in which case insert a '0') + else if(instring[(i*8)] == 0 && + instring[(i*8)-1] == 0 && + instring[(i*8)-2] == 0 && + instring[(i*8)-3] == 0 && + instring[(i*8)-4] == 0 && + instring[(i*8)-5] == 0 && + instring[(i*8)-6] == 0 && + instring[(i*8)-7] == 0) + to_bits[i-1] = 0; + else + begin + $display("Error in %m at time %d ns: non-binary digit in string \"%s\"\nExiting simulation...", $time, instring); + $finish; + end + end + end + end + endfunction + +endmodule + +`undef allXs +`undef all1s diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/PIPELINE_V7_0.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/PIPELINE_V7_0.v new file mode 100644 index 0000000..e0b25e3 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/PIPELINE_V7_0.v @@ -0,0 +1,312 @@ +// Copyright(C) 2003 by Xilinx, Inc. All rights reserved. +// This text/file contains proprietary, confidential +// information of Xilinx, Inc., is distributed under license +// from Xilinx, Inc., and may be used, copied and/or +// disclosed only pursuant to the terms of a valid license +// agreement with Xilinx, Inc. Xilinx hereby grants you +// a license to use this text/file solely for design, simulation, +// implementation and creation of design files limited +// to Xilinx devices or technologies. Use with non-Xilinx +// devices or technologies is expressly prohibited and +// immediately terminates your license unless covered by +// a separate agreement. +// +// Xilinx is providing this design, code, or information +// "as is" solely for use in developing programs and +// solutions for Xilinx devices. By providing this design, +// code, or information as one possible implementation of +// this feature, application or standard, Xilinx is making no +// representation that this implementation is free from any +// claims of infringement. You are responsible for +// obtaining any rights you may require for your implementation. +// Xilinx expressly disclaims any warranty whatsoever with +// respect to the adequacy of the implementation, including +// but not limited to any warranties or representations that this +// implementation is free from claims of infringement, implied +// warranties of merchantability or fitness for a particular +// purpose. +// +// Xilinx products are not intended for use in life support +// appliances, devices, or systems. Use in such applications are +// expressly prohibited. +// +// This copyright and support notice must be retained as part +// of this text at all times. (c) Copyright 1995-2003 Xilinx, Inc. +// All rights reserved. + + + +/* $Id: PIPELINE_V7_0.v,v 1.13 2008/09/08 20:06:14 akennedy Exp $ +-- +-- Filename - PIPELINE_V7_0.v +-- Author - Xilinx +-- Creation - 21 Oct 1998 +-- +-- Description - This file contains the Verilog behavior for the baseblocks utility PIPELINE module +*/ + +`timescale 1ns/10ps + +`define allXs {C_WIDTH{1'bx}} +`define all1s {C_WIDTH{1'b1}} + +module PIPELINE_V7_0 (D, CLK, CE, ACLR, ASET, AINIT, SCLR, SSET, SINIT, Q); + + parameter C_AINIT_VAL = ""; + parameter C_HAS_ACLR = 0; + parameter C_HAS_AINIT = 0; + parameter C_HAS_ASET = 0; + parameter C_HAS_CE = 0; + parameter C_HAS_SCLR = 0; + parameter C_HAS_SINIT = 0; + parameter C_HAS_SSET = 0; + parameter C_PIPE_STAGES = 1; + parameter C_SINIT_VAL = ""; + parameter C_SYNC_ENABLE = 0; // c_override + parameter C_SYNC_PRIORITY = 1; // c_clear + parameter C_WIDTH = 16; + + + input [C_WIDTH-1 : 0] D; + input CLK; + input CE; + input ACLR; + input ASET; + input AINIT; + input SCLR; + input SSET; + input SINIT; + output [C_WIDTH-1 : 0] Q; + + reg [C_WIDTH-1 : 0] pipeliner [0 : C_PIPE_STAGES-1]; + reg [C_WIDTH-1 : 0] intQ; + // Internal values to drive signals when input is missing + wire intCE; + wire intACLR; + wire intASET; + wire intAINIT; + wire intSCLR; + wire intSSET; + wire intSINIT; + + wire [C_WIDTH-1 : 0] #1 Q = intQ; + + // Sort out default values for missing ports + + assign intCE = defval(CE, C_HAS_CE, 1); + assign intACLR = defval(ACLR, C_HAS_ACLR, 0); + assign intASET = defval(ASET, C_HAS_ASET, 0); + assign intAINIT = defval(AINIT, C_HAS_AINIT, 0); + assign intSCLR = defval(SCLR, C_HAS_SCLR, 0); + assign intSSET = defval(SSET, C_HAS_SSET, 0); + assign intSINIT = defval(SINIT, C_HAS_SINIT, 0); + + reg lastCLK; + reg lastintACLR; + reg lastintASET; + + reg [C_WIDTH-1 : 0] AIV; + reg [C_WIDTH-1 : 0] SIV; + + reg cetmp; + reg set_or_clr; + + integer i; + + initial + begin + lastCLK = 1'b0; + lastintACLR = 1'b0; + lastintASET = 1'b0; + AIV = to_bits(C_AINIT_VAL); + SIV = to_bits(C_SINIT_VAL); + set_or_clr = (C_SYNC_PRIORITY === 0)?1'b0:1'b1; + for(i = 0; i < C_PIPE_STAGES; i = i + 1) + pipeliner[i] = 'b0; + if(C_PIPE_STAGES != 0) + begin + if(C_HAS_ACLR === 1) + pipeliner[C_PIPE_STAGES-1] = 'b0; + else if(C_HAS_ASET === 1) + pipeliner[C_PIPE_STAGES-1] = `all1s; + else if(C_HAS_AINIT === 1) + pipeliner[C_PIPE_STAGES-1] = AIV; + else if(C_HAS_SCLR === 1) + pipeliner[C_PIPE_STAGES-1] = 'b0; + else if(C_HAS_SSET === 1) + pipeliner[C_PIPE_STAGES-1] = `all1s; + else if(C_HAS_SINIT === 1) + pipeliner[C_PIPE_STAGES-1] = SIV; + else + pipeliner[C_PIPE_STAGES-1] = AIV; + intQ = pipeliner[C_PIPE_STAGES-1]; + end + else + assign intQ = D; + end + + always@(posedge CLK or intACLR or intASET or intAINIT) + begin + // Do not do anything if there is no pipeline + if(C_PIPE_STAGES > 0) + begin + // deal with synchronous events first + if (CLK !== lastCLK && CLK !== 1'bx && lastCLK !== 1'bx) + begin + // First the pipeline + if(intCE === 1'bx) + for(i = 0; i < C_PIPE_STAGES; i = i + 1) + pipeliner[i] = `allXs; + else if(intCE === 1'b1) + for(i = C_PIPE_STAGES-1; i > 0; i = i - 1) + pipeliner[i] = pipeliner[i-1]; + + // Unqualified behaviour + if(intCE === 1'b1) + pipeliner[0] = D; + + // Synchronous controls + if(C_SYNC_ENABLE === 0) + cetmp = 1'b1; + else + cetmp = intCE; + + if(cetmp === 1'b1) + begin + if((set_or_clr === 1'b0 && intSSET === 1'bx) || + (set_or_clr === 1'b1 && intSCLR === 1'bx) || + intSINIT === 1'bx) + pipeliner[0] = `allXs; + else if(intSINIT === 1'b1) //Synchronous init + pipeliner[0] = SIV; + else if(intSCLR === 1'b1 && (set_or_clr === 1'b1 || intSSET === 1'b0)) //Synchronous clear + pipeliner[0] = 'b0; + else if(intSSET === 1'b1 && (set_or_clr === 1'b0 || intSCLR === 1'b0)) //Synchronous set + pipeliner[0] = `all1s; + end + end + else if(CLK !== lastCLK && (CLK === 1'bx || lastCLK === 1'bx)) + begin + if(intCE !== 1'b0) + for(i = 0; i < C_PIPE_STAGES; i = i + 1) + pipeliner[i] = `allXs; + else if (C_SYNC_ENABLE === 0) + pipeliner[0] = `allXs; + end + + //Asynchronous Controls - over ride synchronous effects + if(intACLR === 1'bx) + pipeliner[C_PIPE_STAGES-1] = `allXs; + else if(intACLR === 1'b1) + pipeliner[C_PIPE_STAGES-1] = 'b0; + else if(intACLR === 1'b0 && intASET === 1'bx) + pipeliner[C_PIPE_STAGES-1] = `allXs; + else if(intACLR === 1'b0 && intASET === 1'b1) + pipeliner[C_PIPE_STAGES-1] = `all1s; + else if(intAINIT === 1'bx) + pipeliner[C_PIPE_STAGES-1] = `allXs; + else if(intAINIT === 1'b1) + pipeliner[C_PIPE_STAGES-1] = AIV; + + intQ <= pipeliner[C_PIPE_STAGES-1]; + end + end + + always@(intACLR or intASET) + begin + lastintACLR <= intACLR; + lastintASET <= intASET; +// if($time != 0) +// if(intACLR === 1'b0 && intASET === 1'b0 && lastintACLR !== 1'b0 && lastintASET !== 1'b0) // RACE +// pipeliner[C_PIPE_STAGES] = `allXs; + end + + always@(CLK) + lastCLK <= CLK; + + + function defval; + input i; + input hassig; + input val; + begin + if(hassig == 1) + defval = i; + else + defval = val; + end + endfunction + + function [C_WIDTH - 1 : 0] to_bits; + input [C_WIDTH*8 : 1] instring; + integer i; + integer non_null_string; + begin + non_null_string = 0; + for(i = C_WIDTH; i > 0; i = i - 1) + begin // Is the string empty? + if(instring[(i*8)] == 0 && + instring[(i*8)-1] == 0 && + instring[(i*8)-2] == 0 && + instring[(i*8)-3] == 0 && + instring[(i*8)-4] == 0 && + instring[(i*8)-5] == 0 && + instring[(i*8)-6] == 0 && + instring[(i*8)-7] == 0 && + non_null_string == 0) + non_null_string = 0; // Use the return value to flag a non-empty string + else + non_null_string = 1; // Non-null character! + end + if(non_null_string == 0) // String IS empty! Just return the value to be all '0's + begin + for(i = C_WIDTH; i > 0; i = i - 1) + to_bits[i-1] = 0; + end + else + begin + for(i = C_WIDTH; i > 0; i = i - 1) + begin // Is this character a '0'? (ASCII = 48 = 00110000) + if(instring[(i*8)] == 0 && + instring[(i*8)-1] == 0 && + instring[(i*8)-2] == 1 && + instring[(i*8)-3] == 1 && + instring[(i*8)-4] == 0 && + instring[(i*8)-5] == 0 && + instring[(i*8)-6] == 0 && + instring[(i*8)-7] == 0) + to_bits[i-1] = 0; + // Or is it a '1'? + else if(instring[(i*8)] == 0 && + instring[(i*8)-1] == 0 && + instring[(i*8)-2] == 1 && + instring[(i*8)-3] == 1 && + instring[(i*8)-4] == 0 && + instring[(i*8)-5] == 0 && + instring[(i*8)-6] == 0 && + instring[(i*8)-7] == 1) + to_bits[i-1] = 1; + // Or is it a ' '? (a null char - in which case insert a '0') + else if(instring[(i*8)] == 0 && + instring[(i*8)-1] == 0 && + instring[(i*8)-2] == 0 && + instring[(i*8)-3] == 0 && + instring[(i*8)-4] == 0 && + instring[(i*8)-5] == 0 && + instring[(i*8)-6] == 0 && + instring[(i*8)-7] == 0) + to_bits[i-1] = 0; + else + begin + $display("Error in %m at time %d ns: non-binary digit in string \"%s\"\nExiting simulation...", $time, instring); + $finish; + end + end + end + end + endfunction + +endmodule + +`undef allXs +`undef all1s diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/PIPE_BHV_V5_0.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/PIPE_BHV_V5_0.v new file mode 100644 index 0000000..80626f1 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/PIPE_BHV_V5_0.v @@ -0,0 +1,143 @@ +// Copyright(C) 2004 by Xilinx, Inc. All rights reserved. +// This text contains proprietary, confidential +// information of Xilinx, Inc., is distributed +// under license from Xilinx, Inc., and may be used, +// copied and/or disclosed only pursuant to the terms +// of a valid license agreement with Xilinx, Inc. This copyright +// notice must be retained as part of this text at all times. + +// $Revision: 1.12 $ $Date: 2008/09/08 20:09:48 $ + +`timescale 1ns/10ps + +`define allXs {C_WIDTH{1'bx}} +`define all1s {C_WIDTH{1'b1}} + +module PIPE_BHV_V5_0 (D, CLK, CE, ACLR, SCLR, Q); + + parameter C_HAS_ACLR = 0; + parameter C_HAS_CE = 0; + parameter C_HAS_SCLR = 1; + parameter C_PIPE_STAGES = 2; + parameter C_WIDTH = 16; + + + input [C_WIDTH-1 : 0] D; + input CLK; + input CE; + input ACLR; + input SCLR; + output [C_WIDTH-1 : 0] Q; + + reg [C_WIDTH-1 : 0] pipeliner [0 : C_PIPE_STAGES-1]; + reg [C_WIDTH-1 : 0] intQ; + // Internal values to drive signals when input is missing + wire intCE; + wire intACLR; + wire intSCLR; + + wire [C_WIDTH-1 : 0] #1 Q = intQ; + + // Sort out default values for missing ports + + assign intCE = defval(CE, C_HAS_CE, 1); + assign intACLR = defval(ACLR, C_HAS_ACLR, 0); + assign intSCLR = defval(SCLR, C_HAS_SCLR, 0); + + reg lastCLK; + reg lastintACLR; + + integer i; + + initial + begin + lastCLK = 1'b0; + lastintACLR = 1'b0; + for(i = 0; i < C_PIPE_STAGES; i = i + 1) + pipeliner[i] = 'b0; + if(C_PIPE_STAGES != 0) + begin + if(C_HAS_ACLR === 1) + pipeliner[C_PIPE_STAGES-1] = 'b0; + else if(C_HAS_SCLR === 1) + pipeliner[C_PIPE_STAGES-1] = 'b0; + intQ = pipeliner[C_PIPE_STAGES-1]; + end + else + assign intQ = D; + end + + always@(posedge CLK or intACLR) + begin + // Do not do anything if there is no pipeline + if(C_PIPE_STAGES > 0) + begin + // deal with synchronous events first + if (CLK !== lastCLK && CLK !== 1'bx && lastCLK !== 1'bx) + begin + // First the pipeline + if(intCE === 1'bx) + for(i = 0; i < C_PIPE_STAGES; i = i + 1) + pipeliner[i] = `allXs; + else if(intCE === 1'b1) + for(i = C_PIPE_STAGES-1; i > 0; i = i - 1) + pipeliner[i] = pipeliner[i-1]; + + // Unqualified behaviour + if(intCE === 1'b1) + pipeliner[0] = D; + + // Synchronous controls + if(intSCLR === 1'bx) + pipeliner[0] = `allXs; + else if(intSCLR === 1'b1) //Synchronous clear + for(i = 0; i < C_PIPE_STAGES; i = i + 1) + pipeliner[i] = 'b0; + end + else if(CLK !== lastCLK && (CLK === 1'bx || lastCLK === 1'bx)) + begin + if(intCE !== 1'b0) + for(i = 0; i < C_PIPE_STAGES; i = i + 1) + pipeliner[i] = `allXs; + end + + //Asynchronous Controls - over ride synchronous effects + if(intACLR === 1'bx) + pipeliner[C_PIPE_STAGES-1] = `allXs; + else if(intACLR === 1'b1) + for(i = 0; i < C_PIPE_STAGES; i = i + 1) + pipeliner[i] = 'b0; + + intQ <= pipeliner[C_PIPE_STAGES-1]; + end + end + + always@(intACLR) + begin + lastintACLR <= intACLR; + + end + + always@(CLK) + lastCLK <= CLK; + + + function defval; + input i; + input hassig; + input val; + begin + if(hassig == 1) + defval = i; + else + defval = val; + end + endfunction + + +endmodule + +`undef allXs +`undef all1s + + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/PIPE_BHV_V5_1.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/PIPE_BHV_V5_1.v new file mode 100644 index 0000000..f025cff --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/PIPE_BHV_V5_1.v @@ -0,0 +1,143 @@ +// Copyright(C) 2004 by Xilinx, Inc. All rights reserved. +// This text contains proprietary, confidential +// information of Xilinx, Inc., is distributed +// under license from Xilinx, Inc., and may be used, +// copied and/or disclosed only pursuant to the terms +// of a valid license agreement with Xilinx, Inc. This copyright +// notice must be retained as part of this text at all times. + +// $Revision: 1.10 $ $Date: 2008/09/08 16:51:32 $ + +`timescale 1ns/10ps + +`define allXs {C_WIDTH{1'bx}} +`define all1s {C_WIDTH{1'b1}} + +module PIPE_BHV_V5_1 (D, CLK, CE, ACLR, SCLR, Q); + + parameter C_HAS_ACLR = 0; + parameter C_HAS_CE = 0; + parameter C_HAS_SCLR = 1; + parameter C_PIPE_STAGES = 2; + parameter C_WIDTH = 16; + + + input [C_WIDTH-1 : 0] D; + input CLK; + input CE; + input ACLR; + input SCLR; + output [C_WIDTH-1 : 0] Q; + + reg [C_WIDTH-1 : 0] pipeliner [0 : C_PIPE_STAGES-1]; + reg [C_WIDTH-1 : 0] intQ; + // Internal values to drive signals when input is missing + wire intCE; + wire intACLR; + wire intSCLR; + + wire [C_WIDTH-1 : 0] #1 Q = intQ; + + // Sort out default values for missing ports + + assign intCE = defval(CE, C_HAS_CE, 1); + assign intACLR = defval(ACLR, C_HAS_ACLR, 0); + assign intSCLR = defval(SCLR, C_HAS_SCLR, 0); + + reg lastCLK; + reg lastintACLR; + + integer i; + + initial + begin + lastCLK = 1'b0; + lastintACLR = 1'b0; + for(i = 0; i < C_PIPE_STAGES; i = i + 1) + pipeliner[i] = 'b0; + if(C_PIPE_STAGES != 0) + begin + if(C_HAS_ACLR === 1) + pipeliner[C_PIPE_STAGES-1] = 'b0; + else if(C_HAS_SCLR === 1) + pipeliner[C_PIPE_STAGES-1] = 'b0; + intQ = pipeliner[C_PIPE_STAGES-1]; + end + else + assign intQ = D; + end + + always@(posedge CLK or intACLR) + begin + // Do not do anything if there is no pipeline + if(C_PIPE_STAGES > 0) + begin + // deal with synchronous events first + if (CLK !== lastCLK && CLK !== 1'bx && lastCLK !== 1'bx) + begin + // First the pipeline + if(intCE === 1'bx) + for(i = 0; i < C_PIPE_STAGES; i = i + 1) + pipeliner[i] = `allXs; + else if(intCE === 1'b1) + for(i = C_PIPE_STAGES-1; i > 0; i = i - 1) + pipeliner[i] = pipeliner[i-1]; + + // Unqualified behaviour + if(intCE === 1'b1) + pipeliner[0] = D; + + // Synchronous controls + if(intSCLR === 1'bx) + pipeliner[0] = `allXs; + else if(intSCLR === 1'b1) //Synchronous clear + for(i = 0; i < C_PIPE_STAGES; i = i + 1) + pipeliner[i] = 'b0; + end + else if(CLK !== lastCLK && (CLK === 1'bx || lastCLK === 1'bx)) + begin + if(intCE !== 1'b0) + for(i = 0; i < C_PIPE_STAGES; i = i + 1) + pipeliner[i] = `allXs; + end + + //Asynchronous Controls - over ride synchronous effects + if(intACLR === 1'bx) + pipeliner[C_PIPE_STAGES-1] = `allXs; + else if(intACLR === 1'b1) + for(i = 0; i < C_PIPE_STAGES; i = i + 1) + pipeliner[i] = 'b0; + + intQ <= pipeliner[C_PIPE_STAGES-1]; + end + end + + always@(intACLR) + begin + lastintACLR <= intACLR; + + end + + always@(CLK) + lastCLK <= CLK; + + + function defval; + input i; + input hassig; + input val; + begin + if(hassig == 1) + defval = i; + else + defval = val; + end + endfunction + + +endmodule + +`undef allXs +`undef all1s + + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/SYNC_FIFO_V5_0.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/SYNC_FIFO_V5_0.v new file mode 100644 index 0000000..77421f0 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/SYNC_FIFO_V5_0.v @@ -0,0 +1,447 @@ +/********************************************************************************* +$RCSfile: SYNC_FIFO_V5_0.v,v $ $Revision: 1.12 $ $Date: 2008/09/08 20:09:59 $ +********************************************************************************** +* Synchronous Fifo - Verilog Behavioral Model +***************************************************************************** +* +* Filename: sync_fifo_v5_0.v +* +* Description : Synchronous FIFO behavioral model +* +* +***********************************************************************************/ +// Copyright(C) 2004 by Xilinx, Inc. All rights reserved. +// This text/file contains proprietary, confidential +// information of Xilinx, Inc., is distributed under license +// from Xilinx, Inc., and may be used, copied and/or +// disclosed only pursuant to the terms of a valid license +// agreement with Xilinx, Inc. Xilinx hereby grants you +// a license to use this text/file solely for design, simulation, +// implementation and creation of design files limited +// to Xilinx devices or technologies. Use with non-Xilinx +// devices or technologies is expressly prohibited and +// immediately terminates your license unless covered by +// a separate agreement. +// +// Xilinx is providing this design, code, or information +// "as is" solely for use in developing programs and +// solutions for Xilinx devices. By providing this design, +// code, or information as one possible implementation of +// this feature, application or standard, Xilinx is making no +// representation that this implementation is free from any +// claims of infringement. You are responsible for +// obtaining any rights you may require for your implementation. +// Xilinx expressly disclaims any warranty whatsoever with +// respect to the adequacy of the implementation, including +// but not limited to any warranties or representations that this +// implementation is free from claims of infringement, implied +// warranties of merchantability or fitness for a particular +// purpose. +// +// Xilinx products are not intended for use in life support +// appliances, devices, or systems. Use in such applications are +// expressly prohibited. +// +// This copyright and support notice must be retained as part +// of this text at all times. (c) Copyright 1995-2004 Xilinx, Inc. +// All rights reserved. + +`timescale 1ns/10ps + +/********************************************************************************** +* Declare top-level module +**********************************************************************************/ + +module SYNC_FIFO_V5_0 ( CLK, + SINIT, + DIN, + WR_EN, + RD_EN, + DOUT, + FULL, + EMPTY, + RD_ACK, + WR_ACK, + RD_ERR, + WR_ERR, + DATA_COUNT + ); + + +/********************************************************************************** +* Parameter Declarations +**********************************************************************************/ + parameter c_dcount_width = 9 ; // width of the dcount . Adjustable by customer + parameter c_enable_rlocs = 0; // + parameter c_has_dcount = 1 ; // + parameter c_has_rd_ack = 1; // + parameter c_has_rd_err = 1; // + parameter c_has_wr_ack = 1; // + parameter c_has_wr_err = 1; // + parameter c_memory_type = 0; // + parameter c_ports_differ = 0; // + parameter c_rd_ack_low = 0; // + parameter c_rd_err_low = 0 ; // + parameter c_read_data_width = 16 ; // + parameter c_read_depth = 0 ; // + parameter c_write_data_width = 16 ; // + parameter c_write_depth = 16 ; // + parameter c_wr_ack_low = 1 ; // + parameter c_wr_err_low = 1 ; // + + + + +parameter addr_max = (c_write_depth == 16 ? 4: + (c_write_depth == 32 ? 5: + (c_write_depth == 64 ? 6 : + (c_write_depth == 128 ? 7 : + (c_write_depth == 256 ? 8 : + (c_write_depth == 512 ? 9 : + (c_write_depth == 1024 ? 10 : + (c_write_depth == 2048 ? 11 : + (c_write_depth == 4096 ? 12 : + (c_write_depth == 8192 ? 13 : + (c_write_depth == 16384 ? 14 : + (c_write_depth == 32768 ? 15 : + (c_write_depth == 65536 ? 16 : 6))))))))))))); + +/*********************************************************************************** +* Input and Output Declarations +***********************************************************************************/ +input CLK; // CLK Signal. +input SINIT; // High Asserted Reset signal. +input [(c_write_data_width-1):0] DIN; // Data Into FIFO. +input WR_EN; // Write into FIFO Signal. +input RD_EN; // Read From FIFO Signal. + +output [(c_read_data_width-1):0] DOUT; // FIFO Data out. +output FULL; // FIFO Full indicating signal. +output EMPTY; // FIFO Empty indicating signal. +output RD_ACK ; // Read Acknowledge signal +output WR_ACK ; // Write Acknowledge signal +output RD_ERR ; // Rejection of RD_EN active on prior clock edge +output WR_ERR ; // Rejection of WR_EN active on prior clock edge +output [(c_dcount_width-1):0] DATA_COUNT ; + + +reg FULL; +reg EMPTY; +wire RD_ACK_internal ; +wire WR_ACK_internal ; +wire RD_ERR_internal ; +wire WR_ERR_internal ; +wire [(c_dcount_width-1):0] DATA_COUNT_int ; +reg [(c_dcount_width-1):0] DATA_COUNT ; + +integer k,j ; + + + +reg rd_ack_int ; +reg rd_err_int ; +reg wr_ack_int ; +reg wr_err_int ; + +integer N ; + +reg [addr_max:0] fcounter; // counter indicates num of data in FIFO +reg [addr_max:0] fcounter_max ; // value of fcounter OR with MSB of fcounter +reg [(addr_max-1):0] rd_ptr; // current read pointer. +reg [(addr_max-1):0] wr_ptr; // current write pointer. +wire [(c_write_data_width-1):0] memory_dataout; // Data Out from the MemBlk +wire [(c_write_data_width-1):0] memory_datain ; // Data into the MemBlk + +wire write_allow = (WR_EN && (!FULL)) ; +wire read_allow = (RD_EN && (!EMPTY)) ; + +assign DOUT = memory_dataout; +assign memory_datain = DIN; + +assign RD_ACK_internal = (c_rd_ack_low == 0 ) ? rd_ack_int : (!rd_ack_int) ; +assign WR_ACK_internal = (c_wr_ack_low == 0 ) ? wr_ack_int : (!wr_ack_int) ; +assign RD_ERR_internal = (c_rd_err_low == 0 ) ? rd_err_int : (!rd_err_int) ; +assign WR_ERR_internal = (c_wr_err_low == 0 ) ? wr_err_int : (!wr_err_int) ; + +// assign DATA_COUNT = (c_has_dcount == 0 ) ? {c_dcount_width{1'bX}} : DATA_COUNT_int ; +assign RD_ACK = (c_has_rd_ack == 0 ) ? 1'bX : RD_ACK_internal ; +assign WR_ACK = (c_has_wr_ack == 0 ) ? 1'bX : WR_ACK_internal ; +assign RD_ERR = (c_has_rd_err == 0 ) ? 1'bX : RD_ERR_internal ; +assign WR_ERR = (c_has_wr_err == 0 ) ? 1'bX : WR_ERR_internal ; + + + MEM_BLK_V5_0 # (addr_max, c_write_data_width, c_write_depth) memblk(.clk(CLK), + .write_en(write_allow), + .read_en(read_allow), + .rd_addr(rd_ptr), + .wr_addr(wr_ptr), + .data_in(memory_datain), + .data_out(memory_dataout), + .rst(SINIT) + ) ; + +/*********************************************************************************** +* Initialize the outputs for simulation purposes +***********************************************************************************/ + + initial begin + + wr_ack_int = 0 ; + + rd_ack_int = 0 ; + + rd_err_int = 0 ; + + wr_err_int = 0 ; + + FULL = 0 ; + EMPTY = 1 ; + + for (k = 0; k < c_dcount_width; k = k + 1) + DATA_COUNT[k] = 0 ; + end + +// DATA_COUNT assignment + +always @(fcounter_max) +begin + if ((c_has_dcount == 1) && (c_dcount_width <= addr_max ) ) + begin + for (j=(addr_max - c_dcount_width); j=0) + begin + if (minusSin==0) + begin + if (output_width==32 && symmetric==0) + begin + if (sin_int<0) + sin_int = scale-1; + end + else + if (sin_int==scale && symmetric==0) + sin_int = sin_int-1; + end + else + sin_int = -sincosTemp; + end + else + begin + if (minusSin==1) + begin + sin_int = -sincosTemp; + if (output_width==32 && symmetric==0) + begin + if (sin_int<0) + sin_int = scale-1; + end + else + if (sin_int==scale && symmetric==0) + sin_int = sin_int-1; + end + end + sin_array[i] = sin_int; + + sincosTemp = scaleReal * cos($realtobits(angle)); + cos_int = sincosTemp; + if (sincosTemp>=0) + begin + if (minusCos==0) + begin + if (output_width==32 && symmetric==0) + begin + if (cos_int<0) + cos_int = scale-1; + end + else + if (cos_int==scale && symmetric==0) + cos_int = cos_int-1; + end + else + cos_int = -sincosTemp; + end + else + begin + if (minusCos==1) + begin + cos_int = -sincosTemp; + if (output_width==32 && symmetric==0) + begin + if (cos_int<0) + cos_int = scale-1; + end + else + if (cos_int==scale && symmetric==0) + cos_int = cos_int-1; + end + end + cos_array[i] = cos_int; + angle = angle + delta_angle; + end + end + + always @(theta) + begin + sin_table <= sin_array[theta]; + cos_table <= cos_array[theta]; + end + + + // Functions **************************************** + + function real sin; + input [63:0] vector; + + real term, sum, theta; + integer n, loop; + + begin + theta = $bitstoreal(vector); + term = theta; + sum = theta; + n = 1; + + for (loop=0; loop < 100; loop = loop + 1) + begin + n = n + 2; + term = -term*theta*theta/((n-1)*n); + sum = sum + term; + end + sin = sum; + end + endfunction + + function real cos; + input [63:0] vector; + + real term, sum, theta; + integer n, loop; + + begin + term = 1.0; + sum = 1.0; + n = 0; + theta = $bitstoreal(vector); + + for (loop=0; loop < 100; loop = loop + 1) + begin + n = n + 2; + term = (-term)*theta*theta/((n-1)*n); + sum = sum + term; + end + cos = sum; + end + endfunction + +endmodule diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/TRIG_TABLE_V5_1.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/TRIG_TABLE_V5_1.v new file mode 100644 index 0000000..06b669d --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/TRIG_TABLE_V5_1.v @@ -0,0 +1,174 @@ +// Copyright(C) 2004 by Xilinx, Inc. All rights reserved. +// This text contains proprietary, confidential +// information of Xilinx, Inc., is distributed +// under license from Xilinx, Inc., and may be used, +// copied and/or disclosed only pursuant to the terms +// of a valid license agreement with Xilinx, Inc. This copyright +// notice must be retained as part of this text at all times. + +// $Revision: 1.10 $ $Date: 2008/09/08 16:51:32 $ + +`timescale 1ns/10ps + +module TRIG_TABLE_V5_1(theta, sin_table, cos_table); + + parameter theta_width = 10; + parameter output_width = 8; + parameter minusSin = 0; + parameter minusCos = 0; + parameter symmetric = 0; + + + parameter tablesize = 1 << theta_width; + parameter pi = 3.14159265358979323846; + parameter scale = 1 << (output_width - symmetric - 1); + parameter delta_angle = 2.0*pi/tablesize; + + input [theta_width-1 : 0] theta; + output [output_width-1 : 0] sin_table; + output [output_width-1 :0 ] cos_table; + reg [output_width-1 : 0] sin_table; + reg [output_width-1 :0 ] cos_table; + real angle; + reg [output_width-1 :0] sin_array[0:tablesize-1]; + reg [output_width-1 :0] cos_array[0:tablesize-1]; + integer i; + integer sin_int, cos_int; + real sincosTemp; + real scaleReal; + + initial + begin + scaleReal = scale; + if (output_width==32 && symmetric==0) + scaleReal = -scaleReal; + angle = 0.0; + for (i=0; i=0) + begin + if (minusSin==0) + begin + if (output_width==32 && symmetric==0) + begin + if (sin_int<0) + sin_int = scale-1; + end + else + if (sin_int==scale && symmetric==0) + sin_int = sin_int-1; + end + else + sin_int = -sincosTemp; + end + else + begin + if (minusSin==1) + begin + sin_int = -sincosTemp; + if (output_width==32 && symmetric==0) + begin + if (sin_int<0) + sin_int = scale-1; + end + else + if (sin_int==scale && symmetric==0) + sin_int = sin_int-1; + end + end + sin_array[i] = sin_int; + + sincosTemp = scaleReal * cos($realtobits(angle)); + cos_int = sincosTemp; + if (sincosTemp>=0) + begin + if (minusCos==0) + begin + if (output_width==32 && symmetric==0) + begin + if (cos_int<0) + cos_int = scale-1; + end + else + if (cos_int==scale && symmetric==0) + cos_int = cos_int-1; + end + else + cos_int = -sincosTemp; + end + else + begin + if (minusCos==1) + begin + cos_int = -sincosTemp; + if (output_width==32 && symmetric==0) + begin + if (cos_int<0) + cos_int = scale-1; + end + else + if (cos_int==scale && symmetric==0) + cos_int = cos_int-1; + end + end + cos_array[i] = cos_int; + angle = angle + delta_angle; + end + end + + always @(theta) + begin + sin_table <= sin_array[theta]; + cos_table <= cos_array[theta]; + end + + + // Functions **************************************** + + function real sin; + input [63:0] vector; + + real term, sum, theta; + integer n, loop; + + begin + theta = $bitstoreal(vector); + term = theta; + sum = theta; + n = 1; + + for (loop=0; loop < 100; loop = loop + 1) + begin + n = n + 2; + term = -term*theta*theta/((n-1)*n); + sum = sum + term; + end + sin = sum; + end + endfunction + + function real cos; + input [63:0] vector; + + real term, sum, theta; + integer n, loop; + + begin + term = 1.0; + sum = 1.0; + n = 0; + theta = $bitstoreal(vector); + + for (loop=0; loop < 100; loop = loop + 1) + begin + n = n + 2; + term = (-term)*theta*theta/((n-1)*n); + sum = sum + term; + end + cos = sum; + end + endfunction + +endmodule diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/pci_exp_1_lane_64b_dsport.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/pci_exp_1_lane_64b_dsport.v new file mode 100644 index 0000000..48f6534 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/pci_exp_1_lane_64b_dsport.v @@ -0,0 +1,148294 @@ +/************************************************************************** + * PCI Express Downstream Port - Netlist Simulation Model + *************************************************************************/ +// Copyright(C) 2008 by Xilinx, Inc. All rights reserved. +// This text/file contains proprietary, confidential +// information of Xilinx, Inc., is distributed under license +// from Xilinx, Inc., and may be used, copied and/or +// disclosed only pursuant to the terms of a valid license +// agreement with Xilinx, Inc. Xilinx hereby grants you +// a license to use this text/file solely for design, simulation, +// implementation and creation of design files limited +// to Xilinx devices or technologies. Use with non-Xilinx +// devices or technologies is expressly prohibited and +// immediately terminates your license unless covered by +// a separate agreement. +// +// Xilinx is providing this design, code, or information +// "as is" solely for use in developing programs and +// solutions for Xilinx devices. By providing this design, +// code, or information as one possible implementation of +// this feature, application or standard, Xilinx is making no +// representation that this implementation is free from any +// claims of infringement. You are responsible for +// obtaining any rights you may require for your implementation. +// Xilinx expressly disclaims any warranty whatsoever with +// respect to the adequacy of the implementation, including +// but not limited to any warranties or representations that this +// implementation is free from claims of infringement, implied +// warranties of merchantability or fitness for a particular +// purpose. +// +// Xilinx products are not intended for use in life support +// appliances, devices, or systems. Use in such applications are +// expressly prohibited. +// +// This copyright and support notice must be retained as part +// of this text at all times. (c) Copyright 1995-2008 Xilinx, Inc. +// All rights reserved. +//////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995-2008 Xilinx, Inc. All rights reserved. +//////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor: Xilinx +// \ \ \/ Version: I.31 +// \ \ Application: netgen +// / / Filename: pci_exp_1_lane_64b_dsport.v +// /___/ /\ Timestamp: Mon Jun 12 16:53:24 2006 +// \ \ / \ +// \___\/\___\ +// +// Command : -sim -ofmt verilog -ne -w -insert_glbl false -tm pci_exp_1_lane_64b_dsport pci_exp_1_lane_64b_dsport.ngc +// Device : 4vfx40ff672-10 +// Input file : pci_exp_1_lane_64b_dsport.ngc +// Output file : pci_exp_1_lane_64b_dsport.v +// # of Modules : 1 +// Design Name : pci_exp_1_lane_64b_dsport +// Xilinx : /build/xfndry/I.31/rtf +// +// Purpose: +// This verilog netlist is a verification model and uses simulation +// primitives which may not represent the true implementation of the +// device, however the netlist is functionally correct and should not +// be modified. This file cannot be synthesized and should only be used +// with supported simulation tools. +// +// Reference: +// Development System Reference Guide, Chapter 23 +// Synthesis and Simulation Design Guide, Chapter 6 +// +//////////////////////////////////////////////////////////////////////////////// + +`timescale 1 ns/1 ps + +module pci_exp_1_lane_64b_dsport ( + cfg_turnoff_ok_n, cfg_to_turnoff_n, trn_rdst_rdy_n, trn_tdst_dsc_n, cfg_err_posted_n, trn_tdst_rdy_n, cfg_trn_pending_n, cfg_err_cpl_timeout_n, +trn_rnp_ok_n, trn_reof_n, trn_terrfwd_n, cfg_interrupt_n, cfg_interrupt_rdy_n, cfg_err_ur_n, cfg_rd_en_n, trn_reset_n, cfg_err_ecrc_n, +cfg_err_cpl_abort_n, trn_rsrc_dsc_n, trn_clk, cfg_wr_en_n, trn_rerrfwd_n, trn_lnk_up_n, trn_rsof_n, trn_teof_n, cfg_rd_wr_done_n, trn_rsrc_rdy_n, +trn_tsrc_dsc_n, cfg_err_cor_n, sys_reset_n, trn_tsrc_rdy_n, sys_clk, cfg_err_cpl_unexpect_n, trn_tsof_n, cfg_pm_wake_n, cfg_byte_en_n, trn_rfc_ph_av, +trn_rd, trn_td, cfg_err_tlp_cpl_header, trn_rbar_hit_n, trn_rfc_cpld_av, cfg_lcommand, cfg_dstatus, trn_rrem_n, cfg_status, trn_rfc_cplh_av, +cfg_command, pci_exp_txn, pci_exp_txp, trn_trem_n, cfg_cfg, cfg_di, cfg_do, cfg_bus_number, cfg_device_number, cfg_dwaddr, trn_rfc_npd_av, +cfg_dcommand, trn_rfc_nph_av, cfg_pcie_link_state_n, cfg_function_number, cfg_lstatus, pci_exp_rxn, pci_exp_rxp, trn_rfc_pd_av, trn_tbuf_av +); + input cfg_turnoff_ok_n; + output cfg_to_turnoff_n; + input trn_rdst_rdy_n; + output trn_tdst_dsc_n; + input cfg_err_posted_n; + output trn_tdst_rdy_n; + input cfg_trn_pending_n; + input cfg_err_cpl_timeout_n; + input trn_rnp_ok_n; + output trn_reof_n; + input trn_terrfwd_n; + input cfg_interrupt_n; + output cfg_interrupt_rdy_n; + input cfg_err_ur_n; + input cfg_rd_en_n; + output trn_reset_n; + input cfg_err_ecrc_n; + input cfg_err_cpl_abort_n; + output trn_rsrc_dsc_n; + output trn_clk; + input cfg_wr_en_n; + output trn_rerrfwd_n; + output trn_lnk_up_n; + output trn_rsof_n; + input trn_teof_n; + output cfg_rd_wr_done_n; + output trn_rsrc_rdy_n; + input trn_tsrc_dsc_n; + input cfg_err_cor_n; + input sys_reset_n; + input trn_tsrc_rdy_n; + input sys_clk; + input cfg_err_cpl_unexpect_n; + input trn_tsof_n; + input cfg_pm_wake_n; + input [3 : 0] cfg_byte_en_n; + output [7 : 0] trn_rfc_ph_av; + output [63 : 0] trn_rd; + input [63 : 0] trn_td; + input [47 : 0] cfg_err_tlp_cpl_header; + output [6 : 0] trn_rbar_hit_n; + output [11 : 0] trn_rfc_cpld_av; + output [15 : 0] cfg_lcommand; + output [15 : 0] cfg_dstatus; + output [7 : 0] trn_rrem_n; + output [15 : 0] cfg_status; + output [7 : 0] trn_rfc_cplh_av; + output [15 : 0] cfg_command; + output [0 : 0] pci_exp_txn; + output [0 : 0] pci_exp_txp; + input [7 : 0] trn_trem_n; + input [1023 : 0] cfg_cfg; + input [31 : 0] cfg_di; + output [31 : 0] cfg_do; + output [7 : 0] cfg_bus_number; + output [4 : 0] cfg_device_number; + input [9 : 0] cfg_dwaddr; + output [11 : 0] trn_rfc_npd_av; + output [15 : 0] cfg_dcommand; + output [7 : 0] trn_rfc_nph_av; + output [2 : 0] cfg_pcie_link_state_n; + output [2 : 0] cfg_function_number; + output [15 : 0] cfg_lstatus; + input [0 : 0] pci_exp_rxn; + input [0 : 0] pci_exp_rxp; + output [11 : 0] trn_rfc_pd_av; + output [4 : 0] trn_tbuf_av; + wire NlwRenamedSig_OI_trn_clk; + wire NlwRenamedSig_OI_trn_reset_n; + wire NlwRenamedSig_OI_trn_lnk_up_n; + wire NlwRenamedSig_OI_cfg_status_4_; + wire NlwRenamedSig_OI_cfg_status_3_; + wire NlwRenamedSig_OI_cfg_status_8_; + wire NlwRenamedSig_OI_cfg_status_11_; + wire NlwRenamedSig_OI_cfg_status_12_; + wire NlwRenamedSig_OI_cfg_status_13_; + wire NlwRenamedSig_OI_cfg_status_14_; + wire NlwRenamedSig_OI_cfg_status_15_; + wire NlwRenamedSig_OI_cfg_command_0_; + wire NlwRenamedSig_OI_cfg_command_1_; + wire NlwRenamedSig_OI_cfg_command_2_; + wire NlwRenamedSig_OI_cfg_command_6_; + wire NlwRenamedSig_OI_cfg_command_8_; + wire NlwRenamedSig_OI_cfg_command_10_; + wire NlwRenamedSig_OI_cfg_dstatus_0_; + wire NlwRenamedSig_OI_cfg_dstatus_1_; + wire NlwRenamedSig_OI_cfg_dstatus_2_; + wire NlwRenamedSig_OI_cfg_dstatus_3_; + wire NlwRenamedSig_OI_cfg_dstatus_5_; + wire NlwRenamedSig_OI_cfg_lstatus_4_; + wire NlwRenamedSig_OI_cfg_lstatus_12_; + wire NlwRenamedSig_OI_cfg_lcommand_0_; + wire NlwRenamedSig_OI_cfg_lcommand_1_; + wire NlwRenamedSig_OI_cfg_lcommand_3_; + wire NlwRenamedSig_OI_cfg_lcommand_6_; + wire NlwRenamedSig_OI_cfg_lcommand_7_; + wire sys_clkz; + wire com_tlm_u_tlm_rx_data_snk_cur_length_0__2; + wire N_6356_i_3; + wire com_tlm_u_tlm_rx_data_snk_cur_length_1__4; + wire N_6357_i_5; + wire com_tlm_u_tlm_rx_data_snk_cur_length_2__6; + wire N_6358_i_7; + wire com_tlm_u_tlm_rx_data_snk_cur_length_3__8; + wire N_6359_i_9; + wire com_tlm_u_tlm_rx_data_snk_cur_length_4__10; + wire N_6360_i_11; + wire com_tlm_u_tlm_rx_data_snk_cur_length_8__12; + wire N_6364_i_13; + wire com_tlm_u_tlm_rx_data_snk_cur_length_9__14; + wire N_6365_i_15; + wire cfg_cfg_i_224_; + wire cfg_cfg_i_351_; + wire N_57349_i_16; + wire N_57388_i_17; + wire G_32479_18; + wire N_36576; + wire m16_i_0_1_19; + wire m16_i_0_4_20; + wire N_14707_i; + wire plm_link_up_2; + wire plm_link_up_0; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_5; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_3; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_4; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_2; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_3; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_1; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_2; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_0; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_1; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0; + wire N_24768_i; + wire N_24768_i_i_21; + wire N_37268_i; + wire N_37268_i_i_22; + wire N_18912_i; + wire N_18912_i_i_23; + wire N_38578; + wire N_38578_i_24; + wire I_5072_0_a2_0_a2_0_a4_25; + wire N_38691_i_26; + wire I_5137_0_a2_0_a2_0_a4_27; + wire N_38692_i_28; + wire plm_link_up; + wire plm_link_up_i; + wire G_32545_29; + wire mgt_clk; + wire plm_rst; + wire G_32547_30; + wire G_32483_31; + wire G_32549_32; + wire G_32485_33; + wire G_32551_34; + wire G_32487_35; + wire G_32489_36; + wire G_32473_37; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_i_38; + wire G_32477_39; + wire plm_fsm_rl_counter0_reg_rx_expired_40; + wire plm_fsm_reg_state_13__41; + wire N_38240_i; + wire N_18708_i_i_42; + wire plm_fsm_pa_counter0_reg_rx_expired_43; + wire N_38420; + wire N_18705_i_i_44; + wire N_27425; + wire N_27415; + wire N_126_1; + wire N_126; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d64_18__45; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d64_30__46; + wire N_10445_1; + wire N_10438; + wire N_27494; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d64_16__47; + wire N_10461_1; + wire N_10395; + wire N_10393; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d64_22__48; + wire N_10496_1; + wire N_10615; + wire com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_39_; + wire N_217; + wire N_178; + wire N_10542; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d64_19__49; + wire N_27491; + wire N_10444; + wire N_10442_1; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d64_31__50; + wire N_27498; + wire N_10442; + wire N_10528; + wire N_10424_1; + wire N_10423; + wire N_100; + wire N_27429; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_initial_64_51; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d64_3__52; + wire N_106_1; + wire N_27428; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d64_2__53; + wire N_10559_1; + wire N_27511; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d64_20__54; + wire N_10486_1; + wire N_10413_1; + wire G_271_55; + wire G_287_56; + wire plm_tsi0_reg_dec8_7_; + wire plm_tsi0_reg_dec8_0_; + wire plm_tsi0_reg_dec7_6_; + wire plm_tsi0_reg_dec7_13_; + wire N_36389_i; + wire m5_2_i_0_32074_57; + wire N_14703_i; + wire N_14705_i; + wire trn_tsof_n_i; + wire trn_terrfwd_n_i; + wire N_3543; + wire plm_dfm_deframe1_qwfsm_reg_state_1__58; + wire plm_dfm_deframe1_qwfsm_reg_state_0__59; + wire N_3546; + wire plm_dfm_deframe1_qwfsm_reg_state_7__60; + wire plm_dfm_deframe1_qwfsm_reg_state_6__61; + wire N_172; + wire N_223_i; + wire N_176_i_62; + wire N_3004; + wire N_224_i; + wire N_16_i_63; + wire com_cmm_cfg_wr_data_13_; + wire I_5030_0_a2_0_a2_0_a2_64; + wire com_cmm_cfg_wr_data_14_; + wire I_5025_0_a2_0_a2_0_a2_65; + wire com_cmm_cfg_wr_data_15_; + wire I_5020_0_a2_0_a2_66; + wire com_cmm_cfg_wr_data_0_; + wire I_5015_0_a2_0_a2_67; + wire com_cmm_cfg_wr_data_1_; + wire I_5010_0_a2_0_a2_68; + wire com_cmm_cfg_wr_data_2_; + wire I_5005_0_a2_0_a2_69; + wire com_cmm_cfg_wr_data_3_; + wire I_5000_0_a2_0_a2_0_a2_70; + wire com_cmm_cfg_wr_data_4_; + wire I_4995_0_a2_0_a2_0_a2_71; + wire com_cmm_cfg_wr_data_5_; + wire I_4990_0_a2_0_a2_0_a2_72; + wire com_cmm_cfg_wr_data_6_; + wire I_4985_0_a2_0_a2_0_a2_73; + wire com_cmm_cfg_wr_data_7_; + wire I_4980_0_a2_0_a2_0_a2_74; + wire com_cmm_cfg_wr_data_30_; + wire I_4975_0_a2_0_a2_0_a2_0_a2_75; + wire com_cmm_cfg_wr_data_31_; + wire I_4970_0_a2_0_a2_0_a2_0_a2_76; + wire com_cmm_cfg_wr_data_16_; + wire I_4965_0_a2_0_a2_0_a2_77; + wire com_cmm_cfg_wr_data_17_; + wire I_4960_0_a2_0_a2_0_a2_78; + wire com_cmm_cfg_wr_data_18_; + wire I_4955_0_a2_0_a2_0_a2_79; + wire com_cmm_cfg_wr_data_19_; + wire I_4950_0_a2_0_a2_0_a2_80; + wire com_cmm_cfg_wr_data_20_; + wire I_4945_0_a2_0_a2_0_a2_0_a2_81; + wire com_cmm_cfg_wr_data_21_; + wire I_4940_0_a2_0_a2_82; + wire com_cmm_cfg_wr_data_22_; + wire I_4935_0_a2_0_a2_0_a2_83; + wire com_cmm_cfg_wr_data_23_; + wire I_4930_0_a2_0_a2_0_a2_84; + wire com_cmm_cfg_wr_data_8_; + wire I_4925_0_a2_0_a2_0_a2_85; + wire com_cmm_cfg_wr_data_9_; + wire I_4920_0_a2_0_a2_0_a2_86; + wire com_cmm_cfg_wr_data_10_; + wire I_4915_0_a2_0_a2_0_a2_0_a2_87; + wire com_cmm_cfg_wr_data_11_; + wire I_4910_0_a2_0_a2_0_a2_88; + wire com_cmm_cfg_wr_data_12_; + wire I_4905_0_a2_0_a2_0_a2_0_a2_89; + wire com_cmm_cfg_wr_data_28_; + wire I_4900_0_a2_0_a2_0_a2_0_a2_90; + wire com_cmm_cfg_wr_data_29_; + wire I_4895_0_a2_0_a2_0_a2_0_a2_91; + wire I_4890_0_a2_0_a2_0_a2_0_a2_92; + wire I_4885_0_a2_0_a2_93; + wire I_4880_0_a2_0_a2_0_a2_94; + wire I_4875_0_a2_0_a2_95; + wire I_4870_0_a2_0_a2_96; + wire I_4865_0_a2_0_a2_0_a2_97; + wire I_4860_0_a2_0_a2_0_a2_98; + wire I_4855_0_a2_0_a2_0_a2_99; + wire I_4850_0_a2_0_a2_0_a2_100; + wire I_4845_0_a2_0_a2_0_a2_101; + wire I_4840_0_a2_0_a2_0_a2_0_a2_102; + wire I_4835_0_a2_0_a2_0_a2_103; + wire I_4830_0_a2_0_a2_0_a2_104; + wire I_4825_0_a2_0_a2_0_a2_105; + wire I_4820_0_a2_0_a2_0_a2_106; + wire I_4815_0_a2_0_a2_0_a2_0_a2_107; + wire I_4810_0_a2_0_a2_108; + wire I_4805_0_a2_0_a2_0_a2_109; + wire I_4800_0_a2_0_a2_0_a2_110; + wire I_4795_0_a2_0_a2_0_a2_0_a2_111; + wire I_4790_0_a2_0_a2_0_a2_0_a2_112; + wire I_4785_0_a2_0_a2_0_a2_0_a2_113; + wire I_4780_0_a2_0_a2_0_a2_0_a2_114; + wire I_4775_0_a2_0_a2_0_a2_0_a2_115; + wire I_4770_0_a2_0_a2_0_a2_0_a2_116; + wire I_4765_0_a2_0_a2_117; + wire I_4760_0_a2_0_a2_118; + wire I_4755_0_a2_0_a2_119; + wire I_4750_0_a2_0_a2_0_a2_120; + wire I_4745_0_a2_0_a2_0_a2_121; + wire I_4740_0_a2_0_a2_0_a2_122; + wire I_4735_0_a2_0_a2_0_a2_123; + wire I_4730_0_a2_0_a2_0_a2_124; + wire I_4725_0_a2_0_a2_0_a2_0_a2_125; + wire I_4720_0_a2_0_a2_0_a2_0_a2_126; + wire I_4715_0_a2_0_a2_0_a2_0_a2_127; + wire I_4710_0_a2_0_a2_0_a2_128; + wire I_4705_0_a2_0_a2_0_a2_129; + wire I_4700_0_a2_0_a2_0_a2_130; + wire I_4695_0_a2_0_a2_0_a2_0_a2_131; + wire I_4690_0_a2_0_a2_132; + wire I_4685_0_a2_0_a2_0_a2_133; + wire I_4680_0_a2_0_a2_0_a2_134; + wire I_4675_0_a2_0_a2_0_a2_135; + wire I_4670_0_a2_0_a2_0_a2_136; + wire I_4665_0_a2_0_a2_0_a2_0_a2_137; + wire I_4660_0_a2_0_a2_0_a2_138; + wire I_4655_0_a2_0_a2_0_a2_0_a2_139; + wire I_4650_0_a2_0_a2_0_a2_140; + wire I_4645_0_a2_0_a2_0_a2_141; + wire I_4640_0_a2_0_a2_142; + wire I_4635_0_a2_0_a2_143; + wire I_4630_0_a2_0_a2_0_a2_144; + wire I_4625_0_a2_0_a2_0_a2_145; + wire I_4620_0_a2_0_a2_0_a2_146; + wire I_4615_0_a2_0_a2_0_a2_147; + wire I_4610_0_a2_0_a2_0_a2_148; + wire I_4605_0_a2_0_a2_0_a2_0_a2_149; + wire I_4600_0_a2_0_a2_0_a2_0_a2_150; + wire I_4595_0_a2_0_a2_0_a2_0_a2_151; + wire I_4590_0_a2_0_a2_0_a2_0_a2_152; + wire I_4585_0_a2_0_a2_0_a2_153; + wire I_4580_0_a2_0_a2_0_a2_154; + wire I_4575_0_a2_0_a2_0_a2_0_a2_155; + wire I_4570_0_a2_0_a2_156; + wire I_4565_0_a2_0_a2_0_a2_157; + wire I_4560_0_a2_0_a2_0_a2_158; + wire I_4555_0_a2_0_a2_0_a2_159; + wire I_4550_0_a2_0_a2_0_a2_160; + wire I_4545_0_a2_0_a2_0_a2_0_a2_161; + wire I_4540_0_a2_0_a2_0_a2_162; + wire I_4535_0_a2_0_a2_0_a2_0_a2_163; + wire I_4530_0_a2_0_a2_0_a2_164; + wire I_4525_0_a2_0_a2_0_a2_165; + wire I_4520_0_a2_0_a2_166; + wire I_4515_0_a2_0_a2_167; + wire I_4510_0_a2_0_a2_168; + wire I_4505_0_a2_0_a2_0_a2_169; + wire I_4500_0_a2_0_a2_0_a2_170; + wire I_4495_0_a2_0_a2_0_a2_171; + wire I_4490_0_a2_0_a2_0_a2_172; + wire I_4485_0_a2_0_a2_0_a2_0_a2_173; + wire I_4480_0_a2_0_a2_0_a2_0_a2_174; + wire I_4475_0_a2_0_a2_0_a2_0_a2_175; + wire I_4470_0_a2_0_a2_0_a2_0_a2_176; + wire I_4465_0_a2_0_a2_0_a2_177; + wire I_4460_0_a2_0_a2_0_a2_178; + wire I_4455_0_a2_0_a2_0_a2_179; + wire I_4450_0_a2_0_a2_180; + wire I_4445_0_a2_0_a2_0_a2_181; + wire I_4440_0_a2_0_a2_0_a2_182; + wire I_4435_0_a2_0_a2_0_a2_183; + wire I_4430_0_a2_0_a2_0_a2_184; + wire I_4425_0_a2_0_a2_0_a2_0_a2_185; + wire I_4420_0_a2_0_a2_0_a2_186; + wire I_4415_0_a2_0_a2_0_a2_0_a2_187; + wire I_4410_0_a2_0_a2_0_a2_188; + wire I_4405_0_a2_0_a2_0_a2_189; + wire I_4400_0_a2_0_a2_190; + wire I_4395_0_a2_0_a2_191; + wire I_4390_0_a2_0_a2_192; + wire I_4385_0_a2_0_a2_193; + wire I_4380_0_a2_0_a2_0_a2_194; + wire I_4375_0_a2_0_a2_0_a2_195; + wire I_4370_0_a2_0_a2_0_a2_196; + wire I_4365_0_a2_0_a2_0_a2_0_a2_197; + wire I_4360_0_a2_0_a2_0_a2_0_a2_198; + wire I_4355_0_a2_0_a2_0_a2_0_a2_199; + wire I_4350_0_a2_0_a2_0_a2_0_a2_200; + wire I_4345_0_a2_0_a2_0_a2_201; + wire I_4340_0_a2_0_a2_0_a2_202; + wire I_4335_0_a2_0_a2_0_a2_203; + wire I_4330_0_a2_0_a2_0_a2_204; + wire I_4325_0_a2_0_a2_0_a2_0_a2_205; + wire I_4320_0_a2_0_a2_0_a2_206; + wire I_4315_0_a2_0_a2_0_a2_207; + wire I_4310_0_a2_0_a2_0_a2_208; + wire I_4305_0_a2_0_a2_0_a2_0_a2_209; + wire I_4300_0_a2_0_a2_0_a2_210; + wire I_4295_0_a2_0_a2_0_a2_0_a2_211; + wire I_4290_0_a2_0_a2_0_a2_212; + wire I_4285_0_a2_0_a2_0_a2_213; + wire I_4280_0_a2_0_a2_214; + wire I_4275_0_a2_0_a2_215; + wire I_4270_0_a2_0_a2_216; + wire I_4265_0_a2_0_a2_217; + wire I_4260_0_a2_0_a2_0_a2_218; + wire I_4255_0_a2_0_a2_0_a2_219; + wire I_4250_0_a2_0_a2_0_a2_220; + wire I_4245_0_a2_0_a2_0_a2_0_a2_221; + wire I_4240_0_a2_0_a2_0_a2_0_a2_222; + wire I_4235_0_a2_0_a2_0_a2_0_a2_223; + wire I_4230_0_a2_0_a2_0_a2_0_a2_224; + wire I_4225_0_a2_0_a2_0_a2_225; + wire I_4220_0_a2_0_a2_0_a2_226; + wire I_4215_0_a2_0_a2_0_a2_227; + wire I_4210_0_a2_0_a2_0_a2_228; + wire I_4205_0_a2_0_a2_0_a2_0_a2_229; + wire I_4200_0_a2_0_a2_230; + wire I_4195_0_a2_0_a2_0_a2_231; + wire N_48877_i; + wire com_cmml_protocol_err_n; + wire com_tlm_cmmt_err_rbuf_overflow; + wire m4_1_232; + wire N_5_i; + wire N_50488; + wire m12_0_0_0_32183_233; + wire com_tlm_cmmt_err_tlp_malformed; + wire N_13_i; + wire N_48961_i; + wire com_cmm_u_cmm_errman_wtd_ftl_to_incrdf2; + wire N_49558; + wire com_cmm_u_cmm_dataproducer_byte_00_1_sqmuxa_1; + wire com_cmm_u_cmm_dataproducer_req_gnt_code_3__234; + wire N_68622_i_235; + wire cfg_trn_pending_n_i; + wire com_cmm_u_cmm_errman_wtd_nfl_add_input_five_n_d_236; + wire com_cmm_u_cmm_errman_wtd_nfl_add_input_four_n_d_237; + wire com_cmm_u_cmm_errman_wtd_nfl_add_input_one_d_238; + wire com_cmm_u_cmm_errman_wtd_nfl_add_input_two_n_d_239; + wire N_6_i_240; + wire com_cmm_u_cmm_errman_wtd_nfl_to_incr_0df1; + wire com_cmm_u_cmm_errman_wtd_nfl_to_incr_0df2; + wire m7_0_241; + wire m3_0_242; + wire com_cmm_u_cmm_errman_wtd_cor_add_input_five_n_d_243; + wire com_cmm_u_cmm_errman_wtd_cor_add_input_four_n_d_244; + wire N_62724_i_245; + wire m13_0_246; + wire m14_247; + wire com_cmm_u_cmm_errman_wtd_cor_to_incr_0df1; + wire m21_248; + wire m22_249; + wire com_cmm_u_cmm_errman_wtd_cor_to_incr_0df2; + wire N_10582_1; + wire N_27442; + wire N_27500; + wire N_32; + wire N_38123_i; + wire N_38124_i; + wire plm_fsm_cc_counter0_reg_rx_expired_250; + wire plm_rx0_ts2_c; + wire N_38100_i; + wire plm_fsm_rc_counter_ts2_0_reg_rx_expired_251; + wire N_18708_i; + wire N_10448; + wire N_27488; + wire N_10495; + wire plm_fsm_rc_counter_ts1_0_reg_rx_expired_252; + wire plm_rx0_ts1_c; + wire N_38174_i; + wire m12_0_0_0_o3_253; + wire N_53; + wire N_10488; + wire N_14; + wire N_10352_1; + wire N_27418; + wire G_339_32076_254; + wire N_10481; + wire N_36; + wire N_10351; + wire N_27411; + wire N_27564; + wire N_10482; + wire N_10346; + wire N_10480_1; + wire N_10480; + wire N_64; + wire N_10500_1; + wire N_10479; + wire N_10477; + wire N_10574_1; + wire N_10574; + wire N_10_1; + wire N_40; + wire N_10347_1; + wire N_27419; + wire N_10565; + wire N_10340; + wire N_27655; + wire N_10487; + wire N_58_1; + wire N_10339; + wire N_27427; + wire N_10569; + wire G_431_0; + wire N_19_1; + wire N_10499; + wire G_368_0_255; + wire N_41_1; + wire N_92_1; + wire N_10510; + wire G_460_0_256; + wire N_160_1; + wire N_10345; + wire N_10602; + wire N_52; + wire N_159_1; + wire N_10616; + wire m22_am_257; + wire m22_bm_258; + wire com_cmm_u_cmm_errman_wtd_cor_add_input_one_d_259; + wire com_cmm_u_cmm_errman_wtd_cor_add_input_six_n_d_260; + wire com_cmm_u_cmm_errman_wtd_cor_add_input_three_n_d_261; + wire com_cmm_u_cmm_errman_wtd_cor_add_input_two_n_d_262; + wire m10_263; + wire m12_264; + wire N_10453_1; + wire N_27376; + wire N_27398_i_0; + wire N_12; + wire N_22; + wire N_27407; + wire N_10514; + wire N_30; + wire N_10511; + wire N_10343; + wire N_10500; + wire G_318_1_0_265; + wire N_10554_1; + wire N_27402_i_0; + wire N_3; + wire N_10341; + wire N_27523; + wire N_10505; + wire N_10478; + wire N_27412; + wire N_27507; + wire N_27391_i_0; + wire N_36400_i; + wire N_36431_i; + wire m16_i_0_0_266; + wire N_44884_i; + wire com_cmm_rst_267; + wire G_2996_0_a2_0_a2_0_a2_268; + wire N_8824; + wire N_38113_i; + wire N_38; + wire N_51_1; + wire N_27661; + wire N_10483; + wire N_27678; + wire N_10580; + wire N_10394; + wire N_10498_1; + wire N_10498; + wire N_10344; + wire N_27423; + wire N_10489; + wire N_10439_1; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d64_24__269; + wire N_10439; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d64_29__270; + wire N_10348_1; + wire N_27373; + wire N_27405; + wire N_27666; + wire N_112_1; + wire N_27664; + wire G_367_0_271; + wire N_10509; + wire N_55; + wire N_10617; + wire N_10550; + wire N_10551; + wire N_27374; + wire N_27399_i_0; + wire N_27372; + wire N_27401_i_0; + wire N_10347; + wire N_10610_1; + wire N_10610; + wire N_26_1; + wire N_87_1; + wire N_10502_1; + wire N_27400_i_0; + wire G_428_0; + wire N_116; + wire N_136; + wire G_428_272; + wire N_168; + wire N_189; + wire G_437_273; + wire N_131; + wire G_129_274; + wire G_359_275; + wire G_149_276; + wire G_373_277; + wire N_10524_1; + wire G_382_278; + wire N_18705_i; + wire G_463_2_279; + wire N_115; + wire N_118; + wire G_463_280; + wire N_243; + wire N_10388; + wire com_llm_llm_tx_top_tx_dllp_td_27_; + wire com_llm_llm_tx_top_tx_dllp_td_28_; + wire N_10532; + wire N_10549_1; + wire com_llm_llm_tx_top_tx_dllp_td_25_; + wire com_llm_llm_tx_top_tx_dllp_td_26_; + wire com_llm_llm_tx_top_tx_dllp_td_40_; + wire N_10549; + wire G_405_2_281; + wire N_179; + wire com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_29_; + wire N_10547; + wire G_406_1_282; + wire N_10548_1; + wire com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_8_; + wire com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_15_; + wire N_10548; + wire N_10543; + wire N_10567; + wire N_219; + wire N_10374; + wire com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_7_; + wire N_10541; + wire N_10563_1; + wire N_10563; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d64_26__283; + wire G_355_0_284; + wire N_27406; + wire N_27417; + wire G_431_1_285; + wire N_27563; + wire N_10360; + wire N_27410; + wire N_27416; + wire N_27421; + wire N_62; + wire N_27413; + wire N_27526; + wire N_27677; + wire N_35_1; + wire N_27502; + wire N_23; + wire N_27426; + wire N_27422; + wire N_27504; + wire N_75; + wire N_27499; + wire N_42; + wire N_78; + wire N_27503; + wire N_27665; + wire N_27680; + wire N_15; + wire N_27408; + wire N_27654; + wire N_140_1; + wire N_27414; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d64_28__286; + wire N_10342; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d64_15__287; + wire N_27658; + wire N_10484_1; + wire N_60; + wire N_59; + wire N_27510; + wire N_58; + wire N_57; + wire N_54; + wire N_27424; + wire N_27671; + wire N_27409; + wire N_51; + wire N_27524; + wire N_39_1; + wire N_37; + wire N_34; + wire N_10354; + wire N_10353_1; + wire N_160; + wire N_125; + wire N_27430; + wire N_27501; + wire N_112; + wire N_107; + wire N_92; + wire N_90_1; + wire N_89; + wire N_27435; + wire N_88; + wire N_124_1; + wire N_79; + wire N_27679; + wire N_74; + wire N_61; + wire N_27404; + wire N_27490; + wire N_10456_1; + wire N_27497; + wire N_10527; + wire N_10395_1; + wire G_10_1_288; + wire N_66; + wire N_10367; + wire N_10555; + wire N_10512_1; + wire N_10512; + wire N_10496; + wire N_10484; + wire N_10456; + wire N_10455; + wire N_10453; + wire N_10452; + wire N_10450; + wire N_10449; + wire N_10447_1; + wire N_10447; + wire N_10445; + wire N_10443; + wire N_10441; + wire N_140; + wire N_124; + wire N_113_1; + wire N_113; + wire N_108; + wire N_87; + wire N_63; + wire N_10353; + wire N_10554; + wire N_91; + wire N_35; + wire N_3580_m_289; + wire N_10391_1; + wire G_411_290; + wire N_114; + wire G_375_291; + wire N_117; + wire G_436_292; + wire I_5112_i_0_0_o3_0_0_293; + wire I_5112_i_0_0_o3_0_4_294; + wire N_196; + wire com_llm_llm_tx_top_tx_dllp_td_30_; + wire com_llm_llm_tx_top_tx_dllp_td_35_; + wire N_10601; + wire N_10562; + wire N_197; + wire com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_30_; + wire com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_35_; + wire N_10598; + wire N_198; + wire com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_3_; + wire com_llm_llm_rx_top_rx_data_62_; + wire N_10597; + wire N_67; + wire N_10520; + wire com_tlm_cmmt_err_flow_control; + wire N_49663; + wire N_50505_1; + wire com_cmm_u_cmm_dataproducer_req_gnt_code_0__295; + wire G_128_296; + wire G_435_297; + wire G_418_0_298; + wire N_199_1; + wire N_10560_1; + wire G_418_299; + wire N_208; + wire com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_4_; + wire com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_17_; + wire com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_18_; + wire N_10535; + wire N_206; + wire com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_36_; + wire com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_49_; + wire com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_50_; + wire N_10537; + wire N_203; + wire N_216_1; + wire N_10608; + wire G_421_1_1; + wire com_llm_llm_tx_top_tx_dllp_td_32_; + wire com_llm_llm_tx_top_tx_dllp_td_43_; + wire com_llm_llm_tx_top_tx_dllp_td_45_; + wire N_184; + wire N_10523; + wire N_10566; + wire N_181; + wire N_10575; + wire N_247; + wire com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_55_; + wire N_27385_i_0; + wire N_245; + wire com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_23_; + wire N_27386_i_0; + wire N_10375; + wire com_llm_llm_rx_top_rx_data_61_; + wire N_10542_1; + wire N_174; + wire com_llm_llm_tx_top_tx_dllp_td_24_; + wire N_10594; + wire com_llm_llm_tx_top_tx_dllp_td_29_; + wire com_llm_llm_tx_top_tx_dllp_td_34_; + wire com_llm_llm_tx_top_tx_dllp_td_52_; + wire com_llm_llm_tx_top_tx_dllp_td_55_; + wire N_10522_1; + wire com_llm_llm_tx_top_tx_dllp_td_38_; + wire N_10522_2; + wire G_371_300; + wire N_130; + wire N_10518_1; + wire G_376_301; + wire N_129; + wire G_186_302; + wire G_465_303; + wire N_154; + wire G_410_304; + wire G_374_305; + wire G_142_306; + wire G_361_307; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_11_; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_43_; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_start_high_latch_q_308; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_24_; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_start_high_latch_309; + wire N_27432; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d64_7__310; + wire plm_dfm_deframe1_dword_empty; + wire N_27388_i; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_6_; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_22_; + wire N_27619; + wire N_27390_i; + wire com_llm_llm_rx_top_rx_data_59_; + wire N_27618; + wire N_27433; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d64_8__311; + wire N_27512; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d64_21__312; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_2_; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_34_; + wire N_10462_1; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_13_; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_45_; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d64_17__313; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_38_; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d64_25__314; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_14_; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_46_; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d64_23__315; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_0_; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_32_; + wire N_27514; + wire N_27438; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d64_13__316; + wire N_141_1; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d64_5__317; + wire N_27436; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d64_11__318; + wire N_27439; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d64_14__319; + wire N_27434; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d64_9__320; + wire N_27420; + wire N_27508; + wire N_27506; + wire N_27527; + wire N_27509; + wire N_27437; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d64_12__321; + wire N_27505; + wire N_27441; + wire N_27513; + wire N_27431; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d64_6__322; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_3_; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_35_; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d64_27__323; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_12_; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_44_; + wire N_27525; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d64_0__324; + wire com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_25_; + wire com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_26_; + wire com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_40_; + wire com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_47_; + wire G_286_325; + wire G_295_326; + wire N_10558_1; + wire plm_scr0_reg_lfsr_one_1__327; + wire plm_scr0_reg_lfsr_one_15__328; + wire G_323_329; + wire plm_scr0_reg_lfsr_one_3__330; + wire plm_scr0_reg_lfsr_one_13__331; + wire G_324_332; + wire N_10519_1; + wire plm_des0_reg_lfsr_one_1__333; + wire plm_des0_reg_lfsr_one_15__334; + wire G_325_335; + wire plm_des0_reg_lfsr_one_3__336; + wire plm_des0_reg_lfsr_one_13__337; + wire G_326_338; + wire N_10469_1; + wire plm_scr0_reg_lfsr_two_13__339; + wire plm_scr0_reg_lfsr_two_15__340; + wire G_327_341; + wire plm_des0_reg_lfsr_two_0__342; + wire plm_des0_reg_lfsr_two_11__343; + wire plm_des0_reg_lfsr_two_13__344; + wire plm_des0_reg_lfsr_two_15__345; + wire G_329_346; + wire G_422_347; + wire N_10429_1; + wire N_200; + wire N_201; + wire N_202_2; + wire N_202; + wire N_209_1; + wire N_209; + wire N_210_1; + wire N_210; + wire N_211_2; + wire N_211; + wire N_212; + wire N_234_1; + wire N_234; + wire N_237; + wire N_239; + wire N_242; + wire G_255_348; + wire G_285_349; + wire G_157_350; + wire N_162; + wire N_163_1; + wire N_163; + wire N_165_1; + wire N_165; + wire N_169; + wire N_170; + wire G_168_351; + wire N_173_1; + wire N_173; + wire N_190; + wire N_10357_1; + wire N_10358_1; + wire N_135; + wire N_10366_1; + wire G_133_352; + wire N_10369_1; + wire G_134_353; + wire G_144_354; + wire N_155_1; + wire N_155; + wire N_117_1; + wire plm_fsm_pc_counter0_reg_rx_expired_355; + wire plm_fsm_reg_state_2__356; + wire plm_fsm_reg_state_16__357; + wire plm_fsm_ri_counter0_reg_rx_expired_358; + wire plm_rx0_idl_c; + wire plm_fsm_ci_counter0_reg_rx_expired_359; + wire plm_fsm_reg_state_11__360; + wire com_llm_llm_tx_top_tx_dllp_td_33_; + wire com_llm_llm_tx_top_tx_dllp_td_53_; + wire N_10402; + wire com_llm_llm_tx_top_tx_dllp_td_41_; + wire N_10404; + wire com_llm_llm_tx_top_tx_dllp_td_48_; + wire com_llm_llm_tx_top_tx_dllp_td_49_; + wire N_10420; + wire N_10415; + wire com_llm_llm_tx_top_tx_dllp_td_42_; + wire N_258; + wire N_252; + wire N_10432_1; + wire com_llm_llm_tx_top_tx_dllp_td_39_; + wire com_llm_llm_tx_top_tx_dllp_td_54_; + wire com_llm_llm_tx_top_tx_dllp_td_44_; + wire com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_9_; + wire com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_21_; + wire N_10406; + wire N_27394_i_0; + wire N_10458; + wire N_247_1; + wire com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_34_; + wire com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_2_; + wire com_llm_llm_rx_top_rx_data_56_; + wire com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_1_; + wire com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_22_; + wire N_10387; + wire com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_33_; + wire com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_54_; + wire N_10386; + wire com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_38_; + wire com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_46_; + wire N_10385; + wire N_228_1; + wire N_228; + wire N_208_1; + wire com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_10_; + wire com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_12_; + wire com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_42_; + wire com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_44_; + wire com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_45_; + wire com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_53_; + wire com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_41_; + wire com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_48_; + wire N_10421; + wire com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_32_; + wire N_10417; + wire com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_0_; + wire com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_16_; + wire N_10416; + wire com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_27_; + wire N_10405; + wire N_10401_1; + wire N_10401; + wire N_10400; + wire N_10392_1; + wire N_10392; + wire N_249_1; + wire N_249; + wire N_27395_i_0; + wire N_10459; + wire N_10431; + wire com_llm_llm_rx_top_rx_data_57_; + wire N_10430; + wire N_10422_1; + wire N_10422; + wire N_82; + wire N_81_1; + wire N_81; + wire N_72; + wire N_71; + wire N_70; + wire N_69; + wire N_49; + wire N_48; + wire N_47; + wire N_45; + wire N_44; + wire N_166; + wire N_139; + wire N_119; + wire N_103; + wire N_98; + wire N_97; + wire N_10355; + wire N_94; + wire N_85; + wire N_83; + wire N_10408_1; + wire N_221; + wire N_220; + wire N_10418_1; + wire N_215; + wire N_204; + wire N_187; + wire N_10377_1; + wire N_10377; + wire N_185; + wire N_10376; + wire N_182; + wire N_10526; + wire N_10454_1; + wire N_10454; + wire N_10425; + wire N_10418; + wire N_10412; + wire N_10411_1; + wire N_10409; + wire N_10408; + wire N_10407; + wire N_10403; + wire N_93; + wire N_95; + wire G_364_361; + wire N_240; + wire N_194; + wire G_188_362; + wire G_167_363; + wire N_164; + wire N_158; + wire N_157; + wire G_143_364; + wire N_207; + wire com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_19_; + wire com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_20_; + wire com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_5_; + wire com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_51_; + wire com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_52_; + wire com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_37_; + wire com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_43_; + wire com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_11_; + wire com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_13_; + wire com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_14_; + wire N_259; + wire N_10396; + wire N_99; + wire N_110; + wire N_10378; + wire N_205; + wire N_213; + wire N_222; + wire N_10410; + wire N_10494; + wire N_10590; + wire N_102; + wire N_10604; + wire N_10433; + wire N_10424; + wire N_10411; + wire N_224; + wire N_152; + wire N_151; + wire N_10361; + wire N_111_1; + wire N_111; + wire N_109; + wire N_104; + wire N_86; + wire N_84; + wire N_80; + wire N_73; + wire N_68; + wire N_46; + wire N_43; + wire N_10457_1; + wire N_10457; + wire N_10398_1; + wire N_241; + wire plm_des0_reg_lfsr_one_12__365; + wire G_377_366; + wire G_397_367; + wire G_434_368; + wire com_llm_llm_rx_top_rx_data_58_; + wire N_101; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_d64_c_q_2__369; + wire N_105; + wire N_121; + wire N_10446; + wire N_10490; + wire N_10491; + wire N_10492; + wire N_10493; + wire N_10534; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_d64_c_q_5__370; + wire N_10538; + wire N_10544; + wire N_10596; + wire N_10600; + wire N_10613; + wire N_10585_1; + wire N_10528_1; + wire N_10423_1; + wire com_llm_llm_rx_top_rx_data_46_; + wire com_llm_llm_rx_top_rx_data_27_; + wire com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_6_; + wire N_254_1; + wire N_253_1; + wire com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_24_; + wire com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_31_; + wire com_llm_llm_rx_top_rx_data_63_; + wire com_llm_llm_tx_top_tx_dllp_td_31_; + wire plm_rx0_lane_pad; + wire plm_rx0_link_pad; + wire N_38190_i; + wire N_3541; + wire N_10413_2; + wire plm_scr0_reg_lfsr_two_0__371; + wire plm_scr0_reg_lfsr_two_11__372; + wire plm_des0_reg_lfsr_one_0__373; + wire plm_des0_reg_lfsr_one_11__374; + wire plm_scr0_reg_lfsr_one_0__375; + wire plm_scr0_reg_lfsr_one_11__376; + wire plm_des0_reg_lfsr_one_14__377; + wire N_35131_i_0; + wire plm_des0_reg_lfsr_two_4__378; + wire N_35130_i_0; + wire plm_des0_reg_lfsr_two_1__379; + wire plm_des0_reg_lfsr_two_2__380; + wire N_35117_i_0; + wire plm_scr0_reg_lfsr_two_14__381; + wire N_17488_i_0; + wire plm_scr0_reg_lfsr_two_4__382; + wire N_17486_i_0; + wire G_467_383; + wire G_447_384; + wire G_383_385; + wire G_362_386; + wire plm_scr0_reg_lfsr_one_14__387; + wire G_332_388; + wire G_294_389; + wire G_293_390; + wire G_272_391; + wire com_cmm_u_cmm_pm_dev_power_state_eq_d0; + wire plm_link_up_1; + wire N_38550_i; + wire phy_tframe_l; + wire phy_tframe_h; + wire phy_tctrl_l; + wire phy_tctrl_h; + wire phy_rctrl_l; + wire phy_rctrl_h; + wire phy_rferr_l_n; + wire phy_rferr_h_n; + wire phy_rframe_l; + wire phy_rframe_h; + wire cmmp_receiver_err; + wire plm_link_l0; + wire N_50789_i; + wire phy_tstall_n_i; + wire trn_reset_n_i; + wire plm_frm_atomic; + wire plm_tx0_lane_pad; + wire plm_N_3508; + wire plm_un3_frm_clkcmp; + wire plm_tx0_link_pad; + wire plm_reg_sym_sent_0_; + wire plm_reg_sym_sent_6_; + wire plm_reg_sym_sent_5_; + wire plm_rx0_inverted; + wire plm_reg_ts1_1; + wire plm_reg_ts2_1; + wire plm_reg_rx_idl_1; + wire plm_rx_clear_cs; + wire plm_rx0_linkctrl_0_; + wire plm_rx0_linkctrl_3_; + wire plm_reg_disdes; + wire plm_VCC_392; + wire plm_tx0_txinhibit; + wire plm_GND_393; + wire plm_rx0_polarity; + wire plm_N_38584_i_394; + wire plm_noscramble; + wire plm_phy_rbad_dfrm_l; + wire plm_phy_rbad_dfrm_h; + wire plm_reg_raw_tstall_d3_395; + wire plm_reg_raw_tstall_d2_396; + wire plm_raw_tstall; + wire plm_reg_raw_tstall_d1_397; + wire plm_un1_tstall_n_0_a2_398; + wire plm_phy_tstall_n; + wire plm_phy_cke_3_399; + wire plm_phy_cke_2_400; + wire plm_phy_cke_1_401; + wire plm_phy_cke_0_402; + wire plm_phy_cke; + wire plm_v4f_mgt_gt1_drdy; + wire plm_v4f_mgt_gt1_den; + wire plm_v4f_mgt_gt1_dwe; + wire plm_v4f_mgt_gt0_drdy; + wire plm_v4f_mgt_gt0_den; + wire plm_v4f_mgt_gt0_dwe; + wire plm_v4f_mgt_rx_sigdet_n_async; + wire plm_v4f_mgt_rx_sigdet_n_temp; + wire plm_v4f_mgt_N_435_i; + wire plm_v4f_mgt_pma_txlock0; + wire plm_v4f_mgt_N_397_i; + wire plm_v4f_mgt_reg_tx_sync_5_i_m2; + wire plm_v4f_mgt_reg_tx_pcs_init_5_i_m3; + wire plm_v4f_mgt_N_404_i; + wire plm_v4f_mgt_N_394_i; + wire plm_v4f_mgt_N_406_i; + wire plm_v4f_mgt_reset_delay_reg_tx_sync_5_i_0_403; + wire plm_v4f_mgt_N_413_1; + wire plm_v4f_mgt_reset_delay_reg_tx_sync_5_i_a2_1_0; + wire plm_v4f_mgt_reset_delay_reg_tx_pcs_init_5_i_o2_1_404; + wire plm_v4f_mgt_N_419_1; + wire plm_v4f_mgt_reset_delay_reg_tx_pcs_init_5_i_o2_2_405; + wire plm_v4f_mgt_reset_delay_reg_tx_sync_5_i_2_406; + wire plm_v4f_mgt_N_399_i; + wire plm_v4f_mgt_pma_rxlock0; + wire plm_v4f_mgt_G_338_407; + wire plm_v4f_mgt_G_337_408; + wire plm_v4f_mgt_G_336_409; + wire plm_v4f_mgt_G_335_410; + wire plm_v4f_mgt_G_334_411; + wire plm_v4f_mgt_G_333_412; + wire plm_v4f_mgt_G_332_413; + wire plm_v4f_mgt_G_331_414; + wire plm_v4f_mgt_G_330_415; + wire plm_v4f_mgt_G_329_416; + wire plm_v4f_mgt_G_328_417; + wire plm_v4f_mgt_G_327_418; + wire plm_v4f_mgt_G_320_419; + wire plm_v4f_mgt_G_326_420; + wire plm_v4f_mgt_G_324_421; + wire plm_v4f_mgt_G_341_422; + wire plm_v4f_mgt_G_339_423; + wire plm_v4f_mgt_G_340_424; + wire plm_v4f_mgt_reg_mgt_clk_sample_425; + wire plm_v4f_mgt_N_388_i; + wire plm_v4f_mgt_reg_tx_sync_426; + wire plm_v4f_mgt_N_411_i; + wire plm_v4f_mgt_reg_tx_pcs_init_427; + wire plm_v4f_mgt_reg_phy_clk_toggle_i_428; + wire plm_v4f_mgt_reg_phy_clk_toggle_429; + wire plm_v4f_mgt_sys_init_n_i_430; + wire plm_v4f_mgt_N_420_i; + wire plm_v4f_mgt_reg_rx_pcs_init_431; + wire plm_v4f_mgt_un3_reg_pma_cnt_axbxc3_432; + wire plm_v4f_mgt_un3_reg_pma_cnt_axbxc2_433; + wire plm_v4f_mgt_un3_reg_pma_cnt_axbxc1_434; + wire plm_v4f_mgt_un3_reg_dcm_cnt_axbxc3_435; + wire plm_v4f_mgt_un3_reg_dcm_cnt_axbxc2_436; + wire plm_v4f_mgt_un3_reg_dcm_cnt_axbxc1_437; + wire plm_v4f_mgt_dcm_delay_reg_dcm9_438; + wire plm_v4f_mgt_reg_dcm_439; + wire plm_v4f_mgt_pma_delay_reg_pma9_440; + wire plm_v4f_mgt_special_clk; + wire plm_v4f_mgt_reg_pma_441; + wire plm_v4f_mgt_dcm_lock_i_442; + wire plm_v4f_mgt_dcm_lock; + wire plm_v4f_mgt_sys_rst_n_i; + wire plm_v4f_mgt_N_1151_i_443; + wire plm_v4f_mgt_G_342_444; + wire plm_v4f_mgt_delta_detect_reg_phase1_3_445; + wire plm_v4f_mgt_dcm_clkd; + wire plm_v4f_mgt_dcm_clk0; + wire plm_v4f_mgt_pipe_phystatus; + wire plm_v4f_mgt_rx_enter_elecidle; + wire plm_v4f_mgt_gt11_by1_VCC_446; + wire plm_v4f_mgt_gt11_by1_GND_447; + wire plm_v4f_mgt_for_v1_4_cal_inst0_sd_req_448; + wire plm_v4f_mgt_for_v1_4_cal_inst0_N_746_i_449; + wire plm_v4f_mgt_for_v1_4_cal_inst0_sd_state_0__450; + wire plm_v4f_mgt_for_v1_4_cal_inst0_N_800_i; + wire plm_v4f_mgt_for_v1_4_cal_inst0_N_729_i_451; + wire plm_v4f_mgt_for_v1_4_cal_inst0_N_745_i_452; + wire plm_v4f_mgt_for_v1_4_cal_inst0_N_744_i_453; + wire plm_v4f_mgt_for_v1_4_cal_inst0_N_669_i; + wire plm_v4f_mgt_for_v1_4_cal_inst0_N_578_i; + wire plm_v4f_mgt_for_v1_4_cal_inst0_N_670_i; + wire plm_v4f_mgt_for_v1_4_cal_inst0_N_1047_i_454; + wire plm_v4f_mgt_for_v1_4_cal_inst0_sd_state_13__455; + wire plm_v4f_mgt_for_v1_4_cal_inst0_sd_state_12__456; + wire plm_v4f_mgt_for_v1_4_cal_inst0_sd_next_state_0_sqmuxa_3; + wire plm_v4f_mgt_for_v1_4_cal_inst0_sd_state_11__457; + wire plm_v4f_mgt_for_v1_4_cal_inst0_N_680_i_458; + wire plm_v4f_mgt_for_v1_4_cal_inst0_sd_state_10__459; + wire plm_v4f_mgt_for_v1_4_cal_inst0_sd_state_9__460; + wire plm_v4f_mgt_for_v1_4_cal_inst0_sd_next_state_0_sqmuxa_2; + wire plm_v4f_mgt_for_v1_4_cal_inst0_N_1048_i_461; + wire plm_v4f_mgt_for_v1_4_cal_inst0_sd_state_8__462; + wire plm_v4f_mgt_for_v1_4_cal_inst0_sd_state_7__463; + wire plm_v4f_mgt_for_v1_4_cal_inst0_N_682_i_464; + wire plm_v4f_mgt_for_v1_4_cal_inst0_sd_state_6__465; + wire plm_v4f_mgt_for_v1_4_cal_inst0_sd_state_5__466; + wire plm_v4f_mgt_for_v1_4_cal_inst0_sd_next_state_0_sqmuxa_1; + wire plm_v4f_mgt_for_v1_4_cal_inst0_sd_state_4__467; + wire plm_v4f_mgt_for_v1_4_cal_inst0_N_683_i; + wire plm_v4f_mgt_for_v1_4_cal_inst0_sd_state_3__468; + wire plm_v4f_mgt_for_v1_4_cal_inst0_sd_drp_done_469; + wire plm_v4f_mgt_for_v1_4_cal_inst0_drp_next_state_0_sqmuxa; + wire plm_v4f_mgt_for_v1_4_cal_inst0_N_1020_i_470; + wire plm_v4f_mgt_for_v1_4_cal_inst0_drp_state_3__471; + wire plm_v4f_mgt_for_v1_4_cal_inst0_drp_state_1__472; + wire plm_v4f_mgt_for_v1_4_cal_inst0_drp_next_state_0_sqmuxa_1; + wire plm_v4f_mgt_for_v1_4_cal_inst0_sd_write_473; + wire plm_v4f_mgt_for_v1_4_cal_inst0_N_576_i; + wire plm_v4f_mgt_for_v1_4_cal_inst0_sd_read_474; + wire plm_v4f_mgt_for_v1_4_cal_inst0_N_1051_i_475; + wire plm_v4f_mgt_for_v1_4_cal_inst0_drp_state_4__476; + wire plm_v4f_mgt_for_v1_4_cal_inst0_drp_state_0__477; + wire plm_v4f_mgt_for_v1_4_cal_inst0_GT_DEN_3_i_a2_478; + wire plm_v4f_mgt_for_v1_4_cal_inst0_gt_drdy_r_479; + wire plm_v4f_mgt_for_v1_4_cal_inst0_N_1050_i_480; + wire plm_v4f_mgt_for_v1_4_cal_inst0_GND_481; + wire plm_v4f_mgt_for_v1_4_cal_inst0_N_583_i; + wire plm_v4f_mgt_for_v1_4_cal_inst0_N_581_i; + wire plm_v4f_mgt_for_v1_4_cal_inst0_N_1053_i_482; + wire plm_v4f_mgt_for_v1_4_cal_inst0_N_660_i; + wire plm_v4f_mgt_for_v1_4_cal_inst0_N_297_i; + wire plm_v4f_mgt_for_v1_4_cal_inst0_N_293_i; + wire plm_v4f_mgt_for_v1_4_cal_inst0_N_356_i_i; + wire plm_v4f_mgt_for_v1_4_cal_inst0_N_1031_i_483; + wire plm_v4f_mgt_for_v1_4_cal_inst1_VCC_484; + wire plm_v4f_mgt_for_v1_4_cal_inst1_GND_485; + wire plm_v4f_mgt_for_v1_4_cal_inst1_sd_req_486; + wire plm_v4f_mgt_for_v1_4_cal_inst1_N_718_i_487; + wire plm_v4f_mgt_for_v1_4_cal_inst1_N_799_i; + wire plm_v4f_mgt_for_v1_4_cal_inst1_N_717_i_488; + wire plm_v4f_mgt_for_v1_4_cal_inst1_N_716_i_489; + wire plm_v4f_mgt_for_v1_4_cal_inst1_N_715_i_490; + wire plm_v4f_mgt_for_v1_4_cal_inst1_N_284_i; + wire plm_v4f_mgt_for_v1_4_cal_inst1_N_671_i; + wire plm_v4f_mgt_for_v1_4_cal_inst1_N_1056_i_491; + wire plm_v4f_mgt_for_v1_4_cal_inst1_sd_state_12__492; + wire plm_v4f_mgt_for_v1_4_cal_inst1_sd_next_state_0_sqmuxa_3; + wire plm_v4f_mgt_for_v1_4_cal_inst1_sd_state_11__493; + wire plm_v4f_mgt_for_v1_4_cal_inst1_N_677_i; + wire plm_v4f_mgt_for_v1_4_cal_inst1_sd_state_10__494; + wire plm_v4f_mgt_for_v1_4_cal_inst1_N_676_i_495; + wire plm_v4f_mgt_for_v1_4_cal_inst1_sd_state_6__496; + wire plm_v4f_mgt_for_v1_4_cal_inst1_sd_state_5__497; + wire plm_v4f_mgt_for_v1_4_cal_inst1_sd_next_state_0_sqmuxa_1; + wire plm_v4f_mgt_for_v1_4_cal_inst1_sd_state_4__498; + wire plm_v4f_mgt_for_v1_4_cal_inst1_N_674_i_499; + wire plm_v4f_mgt_for_v1_4_cal_inst1_sd_state_3__500; + wire plm_v4f_mgt_for_v1_4_cal_inst1_sd_state_2__501; + wire plm_v4f_mgt_for_v1_4_cal_inst1_sd_next_state_0_sqmuxa; + wire plm_v4f_mgt_for_v1_4_cal_inst1_N_1057_i_502; + wire plm_v4f_mgt_for_v1_4_cal_inst1_sd_state_1__503; + wire plm_v4f_mgt_for_v1_4_cal_inst1_sd_state_0__504; + wire plm_v4f_mgt_for_v1_4_cal_inst1_sd_state_13__505; + wire plm_v4f_mgt_for_v1_4_cal_inst1_sd_drp_done_506; + wire plm_v4f_mgt_for_v1_4_cal_inst1_drp_next_state_0_sqmuxa; + wire plm_v4f_mgt_for_v1_4_cal_inst1_N_1022_i_507; + wire plm_v4f_mgt_for_v1_4_cal_inst1_drp_state_3__508; + wire plm_v4f_mgt_for_v1_4_cal_inst1_drp_state_1__509; + wire plm_v4f_mgt_for_v1_4_cal_inst1_drp_next_state_0_sqmuxa_1_i_i_a3_510; + wire plm_v4f_mgt_for_v1_4_cal_inst1_sd_write_511; + wire plm_v4f_mgt_for_v1_4_cal_inst1_N_282_i; + wire plm_v4f_mgt_for_v1_4_cal_inst1_sd_read_512; + wire plm_v4f_mgt_for_v1_4_cal_inst1_N_1058_i_513; + wire plm_v4f_mgt_for_v1_4_cal_inst1_drp_state_4__514; + wire plm_v4f_mgt_for_v1_4_cal_inst1_drp_state_0__515; + wire plm_v4f_mgt_for_v1_4_cal_inst1_GT_DEN_3_i_0_a2_516; + wire plm_v4f_mgt_for_v1_4_cal_inst1_gt_drdy_r_517; + wire plm_v4f_mgt_for_v1_4_cal_inst1_N_1061_i_518; + wire plm_v4f_mgt_for_v1_4_cal_inst1_N_291_i; + wire plm_v4f_mgt_for_v1_4_cal_inst1_N_289_i; + wire plm_v4f_mgt_for_v1_4_cal_inst1_N_1064_i_519; + wire plm_v4f_mgt_for_v1_4_cal_inst1_N_661_i; + wire plm_v4f_mgt_for_v1_4_cal_inst1_N_313_i; + wire plm_v4f_mgt_for_v1_4_cal_inst1_N_309_i; + wire plm_v4f_mgt_for_v1_4_cal_inst1_N_391_i_i; + wire plm_v4f_mgt_for_v1_4_cal_inst1_N_1030_i_520; + wire plm_des0_one_adv2_1_15__521; + wire plm_des0_one_adv2_1_13__522; + wire plm_des0_two_adv2_1_14__523; + wire plm_des0_two_adv2_1_12__524; + wire plm_des0_two_adv2_1_1__525; + wire plm_des0_two_adv2_1_7__526; + wire plm_des0_one_adv2_1_6__527; + wire plm_des0_one_adv2_1_5__528; + wire plm_des0_one_adv2_1_9__529; + wire plm_des0_two_adv2_1_10__530; + wire plm_des0_two_adv2_1_8__531; + wire plm_des0_two_adv2_1_6__532; + wire plm_des0_two_adv2_1_4__533; + wire plm_des0_m1_0_a2_0_a3_0_a2; + wire plm_des0_N_68296_i; + wire plm_des0_N_11970_i; + wire plm_des0_N_11969_i; + wire plm_des0_N_12017_i; + wire plm_des0_N_12016_i; + wire plm_des0_N_35107_i; + wire plm_des0_reg_lfsr_one_12_iv_i_0_a2_0_12_; + wire plm_des0_reg_lfsr_one_12_iv_i_0_a2_0_10_; + wire plm_des0_reg_lfsr_one_12_iv_i_0_a2_9_; + wire plm_des0_reg_lfsr_one_12_iv_i_0_a2_8_; + wire plm_des0_reg_lfsr_one_12_iv_i_0_a2_0_7_; + wire plm_des0_reg_lfsr_one_12_iv_i_0_a2_0_6_; + wire plm_des0_reg_lfsr_one_12_iv_i_0_a2_0_5_; + wire plm_des0_reg_lfsr_one_12_iv_i_0_a2_3_; + wire plm_des0_two_adv2_15__534; + wire plm_des0_reg_lfsr_two_12_iv_i_0_a2_0_14_; + wire plm_des0_reg_lfsr_two_12_iv_i_0_a2_0_13_; + wire plm_des0_two_adv2_12__535; + wire plm_des0_reg_lfsr_two_12_iv_i_0_a2_0_11_; + wire plm_des0_two_adv2_10__536; + wire plm_des0_reg_lfsr_two_12_iv_0_0_a2_0_9_; + wire plm_des0_reg_lfsr_two_12_iv_0_0_a2_0_8_; + wire plm_des0_two_adv2_7__537; + wire plm_des0_two_adv2_6__538; + wire plm_des0_N_35105_i; + wire plm_des0_reg_lfsr_two_12_iv_0_0_a2_0_5_; + wire plm_des0_reg_lfsr_two_12_iv_i_0_a2_0_4_; + wire plm_des0_reg_lfsr_two_12_iv_0_0_a2_0_3_; + wire plm_des0_reg_lfsr_two_12_iv_i_0_a2_0_2_; + wire plm_des0_reg_lfsr_two_12_iv_i_0_a2_0_1_; + wire plm_des0_reg_lfsr_two_12_iv_i_0_a2_0_0_; + wire plm_des0_N_35110_i_0; + wire plm_des0_N_35106_i; + wire plm_des0_reg_dis_539; + wire plm_des0_N_67774_i; + wire plm_des0_N_67773_i; + wire plm_des0_N_35147_i_0_i; + wire plm_des0_N_35145_i_0_i; + wire plm_des0_N_35143_i_0_i; + wire plm_des0_N_35141_i_0_i; + wire plm_des0_N_35139_i_0_i; + wire plm_des0_N_35137_i_0_i; + wire plm_des0_N_35135_i_0_i; + wire plm_des0_N_35133_i_0_i; + wire plm_des0_N_69382_i; + wire plm_des0_N_69381_i; + wire plm_des0_N_69380_i; + wire plm_des0_N_67782_i; + wire plm_des0_N_69379_i; + wire plm_des0_N_67781_i; + wire plm_des0_reg_lfsr_one_10__540; + wire plm_des0_N_67780_i; + wire plm_des0_reg_lfsr_one_9__541; + wire plm_des0_N_67779_i; + wire plm_des0_reg_lfsr_one_8__542; + wire plm_des0_N_67778_i; + wire plm_des0_reg_lfsr_one_7__543; + wire plm_des0_N_67777_i; + wire plm_des0_reg_lfsr_one_6__544; + wire plm_des0_N_67776_i; + wire plm_des0_reg_lfsr_one_5__545; + wire plm_des0_N_69378_i; + wire plm_des0_reg_lfsr_one_4__546; + wire plm_des0_N_67775_i; + wire plm_des0_N_69377_i; + wire plm_des0_reg_lfsr_one_2__547; + wire plm_des0_N_69376_i; + wire plm_des0_N_69375_i; + wire plm_des0_N_67790_i; + wire plm_des0_N_67789_i; + wire plm_des0_reg_lfsr_two_14__548; + wire plm_des0_N_67788_i; + wire plm_des0_N_8718_i; + wire plm_des0_reg_lfsr_two_12__549; + wire plm_des0_N_67787_i; + wire plm_des0_N_8720_i; + wire plm_des0_reg_lfsr_two_10__550; + wire plm_des0_N_8721_i; + wire plm_des0_reg_lfsr_two_9__551; + wire plm_des0_N_8722_i; + wire plm_des0_reg_lfsr_two_8__552; + wire plm_des0_N_8723_i; + wire plm_des0_reg_lfsr_two_7__553; + wire plm_des0_N_8724_i; + wire plm_des0_reg_lfsr_two_6__554; + wire plm_des0_N_8725_i; + wire plm_des0_reg_lfsr_two_5__555; + wire plm_des0_N_67786_i; + wire plm_des0_N_8727_i; + wire plm_des0_reg_lfsr_two_3__556; + wire plm_des0_N_67785_i; + wire plm_des0_N_67784_i; + wire plm_des0_reg_lfsr_one32_i; + wire plm_des0_N_67783_i; + wire plm_scr0_one_adv2_1_13__557; + wire plm_scr0_one_adv2_1_11__558; + wire plm_scr0_two_adv2_0_15__559; + wire plm_scr0_two_adv2_1_12__560; + wire plm_scr0_two_adv2_1_1__561; + wire plm_scr0_two_adv2_1_7__562; + wire plm_scr0_one_adv2_1_6__563; + wire plm_scr0_reg_tx_data_12_2_m3_0_bm_4_; + wire plm_scr0_reg_tx_data_12_2_m3_0_am_4_; + wire plm_scr0_reg_tx_data_12_2_m3_0_bm_1_; + wire plm_scr0_reg_tx_data_12_2_m3_0_am_1_; + wire plm_scr0_two_adv2_1_8__564; + wire plm_scr0_two_adv2_0_4__565; + wire plm_scr0_two_adv2_1_6__566; + wire plm_scr0_one_adv2_1_5__567; + wire plm_scr0_reg_tx_data_12_2_bm_7_; + wire plm_scr0_reg_tx_data_12_2_am_7_; + wire plm_scr0_reg_tx_data_12_2_bm_6_; + wire plm_scr0_reg_tx_data_12_2_am_6_; + wire plm_scr0_reg_tx_data_12_2_bm_5_; + wire plm_scr0_reg_tx_data_12_2_am_5_; + wire plm_scr0_reg_tx_data_12_2_bm_3_; + wire plm_scr0_reg_tx_data_12_2_am_3_; + wire plm_scr0_reg_tx_data_12_2_bm_2_; + wire plm_scr0_reg_tx_data_12_2_am_2_; + wire plm_scr0_reg_tx_data_12_sn_m2; + wire plm_scr0_reg_tx_data_12_2_bm_0_; + wire plm_scr0_reg_tx_data_12_2_am_0_; + wire plm_scr0_reg_tx_data_12_2_m3_0_4_; + wire plm_scr0_reg_tx_data_12_2_m3_0_1_; + wire plm_scr0_one_adv2_14__568; + wire plm_scr0_reg_lfsr_one_12_iv_i_a2_12_; + wire plm_scr0_reg_lfsr_one_12_iv_i_a2_10_; + wire plm_scr0_reg_lfsr_one_12_iv_i_a2_9_; + wire plm_scr0_reg_lfsr_one_12_iv_i_a2_8_; + wire plm_scr0_reg_lfsr_one_12_iv_i_a2_5_; + wire plm_scr0_reg_lfsr_one_12_iv_i_a2_3_; + wire plm_scr0_one_adv2_15__569; + wire plm_scr0_reg_lfsr_two_12_iv_i_a2_0_15_; + wire plm_scr0_two_adv2_1_14__570; + wire plm_scr0_one_adv2_13__571; + wire plm_scr0_reg_lfsr_two_12_iv_i_a2_0_13_; + wire plm_scr0_two_adv2_12__572; + wire plm_scr0_one_adv2_12__573; + wire plm_scr0_one_adv2_11__574; + wire plm_scr0_reg_lfsr_two_12_iv_i_a2_11_; + wire plm_scr0_two_adv2_10__575; + wire plm_scr0_one_adv2_10__576; + wire plm_scr0_two_adv2_9__577; + wire plm_scr0_reg_lfsr_two_12_iv_i_a2_0_9_; + wire plm_scr0_one_adv2_8__578; + wire plm_scr0_reg_lfsr_two_12_iv_i_a2_0_8_; + wire plm_scr0_two_adv2_7__579; + wire plm_scr0_one_adv2_7__580; + wire plm_scr0_two_adv2_6__581; + wire plm_scr0_one_adv2_6__582; + wire plm_scr0_two_adv2_5__583; + wire plm_scr0_reg_lfsr_one29; + wire plm_scr0_reg_lfsr_two_12_iv_i_a2_5_; + wire plm_scr0_one_adv2_4__584; + wire plm_scr0_reg_lfsr_two_12_iv_i_a2_0_4_; + wire plm_scr0_one_adv2_3__585; + wire plm_scr0_reg_lfsr_two_12_iv_i_a2_0_3_; + wire plm_scr0_reg_lfsr_two_12_iv_i_a2_9_; + wire plm_scr0_one_adv2_2__586; + wire plm_scr0_reg_lfsr_two_12_iv_i_a2_0_2_; + wire plm_scr0_one_adv2_1__587; + wire plm_scr0_reg_lfsr_two_12_iv_i_a2_1_; + wire plm_scr0_un1_reg_com_1_588; + wire plm_scr0_one_adv2_0__589; + wire plm_scr0_reg_lfsr_two_12_iv_i_a2_0_; + wire plm_scr0_N_17481_i; + wire plm_scr0_reg_tx_data_12_6_; + wire plm_scr0_reg_tx_data_12_5_; + wire plm_scr0_N_17494_i; + wire plm_scr0_reg_tx_data_12_3_; + wire plm_scr0_reg_tx_data_12_2_; + wire plm_scr0_N_17493_i; + wire plm_scr0_reg_tx_data_12_0_; + wire plm_scr0_N_12053_i; + wire plm_scr0_N_12052_i; + wire plm_scr0_reg_tx_data_12_7_; + wire plm_scr0_N_17450_i; + wire plm_scr0_N_17452_i; + wire plm_scr0_N_17454_i; + wire plm_scr0_N_67804_i; + wire plm_scr0_reg_lfsr_one_12__590; + wire plm_scr0_N_17458_i; + wire plm_scr0_N_67803_i; + wire plm_scr0_reg_lfsr_one_10__591; + wire plm_scr0_N_67802_i; + wire plm_scr0_reg_lfsr_one_9__592; + wire plm_scr0_N_67801_i; + wire plm_scr0_reg_lfsr_one_8__593; + wire plm_scr0_N_67800_i; + wire plm_scr0_reg_lfsr_one_7__594; + wire plm_scr0_N_67799_i; + wire plm_scr0_reg_lfsr_one_6__595; + wire plm_scr0_N_67798_i; + wire plm_scr0_reg_lfsr_one_5__596; + wire plm_scr0_N_17472_i; + wire plm_scr0_reg_lfsr_one_4__597; + wire plm_scr0_N_67797_i; + wire plm_scr0_N_17476_i; + wire plm_scr0_reg_lfsr_one_2__598; + wire plm_scr0_N_67816_i; + wire plm_scr0_N_67815_i; + wire plm_scr0_N_67814_i; + wire plm_scr0_N_69424_i; + wire plm_scr0_reg_lfsr_two_12__599; + wire plm_scr0_N_67813_i; + wire plm_scr0_N_69423_i; + wire plm_scr0_reg_lfsr_two_10__600; + wire plm_scr0_N_67812_i; + wire plm_scr0_reg_lfsr_two_9__601; + wire plm_scr0_N_67811_i; + wire plm_scr0_reg_lfsr_two_8__602; + wire plm_scr0_N_69422_i; + wire plm_scr0_reg_lfsr_two_7__603; + wire plm_scr0_N_8756_i; + wire plm_scr0_reg_lfsr_two_6__604; + wire plm_scr0_N_67810_i; + wire plm_scr0_reg_lfsr_two_5__605; + wire plm_scr0_N_67809_i; + wire plm_scr0_N_67808_i; + wire plm_scr0_reg_lfsr_two_3__606; + wire plm_scr0_N_67807_i; + wire plm_scr0_reg_lfsr_two_2__607; + wire plm_scr0_N_67806_i; + wire plm_scr0_reg_lfsr_two_1__608; + wire plm_scr0_reg_lfsr_one32_i; + wire plm_scr0_N_67805_i; + wire plm_tsi0_un2_com_data_jog0_609; + wire plm_tsi0_idle_pair_0_a2_0_a2_0_a4_12_610; + wire plm_tsi0_ts2_inv0_jog0_1_5_611; + wire plm_tsi0_ts2_inv0_jog0_1_4_612; + wire plm_tsi0_ts2_inv1_jog0_1_5_613; + wire plm_tsi0_ts2_inv1_jog0_1_4_614; + wire plm_tsi0_ts1_inv0_jog1_1_5_615; + wire plm_tsi0_ts1_inv0_jog1_1_4_616; + wire plm_tsi0_ts1_inv1_jog1_1_5_617; + wire plm_tsi0_ts1_inv1_jog1_1_4_618; + wire plm_tsi0_com_data_jog1_2; + wire plm_tsi0_com_data_jog1_1_619; + wire plm_tsi0_idle_pair_0_a2_0_a2_0_a4_13_620; + wire plm_tsi0_idle_pair_0_a2_0_a2_0_a4_11_621; + wire plm_tsi0_idle_pair_0_a2_0_a2_0_a4_10_622; + wire plm_tsi0_idle_pair_0_a2_0_a2_0_a4_9_623; + wire plm_tsi0_ts1_inv1_jog1_1_624; + wire plm_tsi0_ts2_inv1_jog0_1_625; + wire plm_tsi0_ts1_inv0_jog1_1_626; + wire plm_tsi0_ts2_inv0_jog0_1_627; + wire plm_tsi0_com_data_jog0_628; + wire plm_tsi0_reg_capture_ts2_3_0; + wire plm_tsi0_reg_capture_ts1_3_0; + wire plm_tsi0_ts2_inv1_jog1_629; + wire plm_tsi0_ts2_inv0_jog1_630; + wire plm_tsi0_ts1_inv1_jog1_631; + wire plm_tsi0_ts1_inv0_jog1_632; + wire plm_tsi0_reg_capture_inv_3_5595; + wire plm_tsi0_reg_capture_inv_3_5594; + wire plm_tsi0_un7_reg_ts1_timer_axbxc3_633; + wire plm_tsi0_un2_recent_ts1_634; + wire plm_tsi0_reg_ts1_timer_0_sqmuxa_635; + wire plm_tsi0_un7_reg_ts2_timer_axbxc3_636; + wire plm_tsi0_un2_recent_ts2_637; + wire plm_tsi0_reg_ts2_timer_0_sqmuxa_638; + wire plm_tsi0_reg_dec8_13__639; + wire plm_tsi0_idle_pair; + wire plm_tsi0_reg_ts2_c_3; + wire plm_tsi0_reg_ts1_c_3; + wire plm_tsi0_N_9992_i; + wire plm_tsi0_N_9993_i; + wire plm_tsi0_reg_capture_ts2_640; + wire plm_tsi0_N_9994_i; + wire plm_tsi0_reg_capture_ts1_641; + wire plm_tsi0_N_9996_i; + wire plm_tsi0_reg_capture_jog_642; + wire plm_tsi0_N_9995_i; + wire plm_tsi0_reg_rx_idl_c_3; + wire plm_tsi0_reg_dec2_3__643; + wire plm_tsi0_reg_dec2_2__644; + wire plm_tsi0_reg_dec2_1__645; + wire plm_tsi0_reg_dec5_4__646; + wire plm_tsi0_reg_dec5_3__647; + wire plm_tsi0_reg_dec5_2__648; + wire plm_tsi0_reg_dec5_1__649; + wire plm_tsi0_reg_dec2_11__650; + wire plm_tsi0_reg_dec2_10__651; + wire plm_tsi0_reg_dec2_9__652; + wire plm_tsi0_reg_dec2_8__653; + wire plm_tsi0_reg_dec2_4__654; + wire plm_tsi0_reg_dec7_12__655; + wire plm_tsi0_reg_dec5_11__656; + wire plm_tsi0_reg_dec5_10__657; + wire plm_tsi0_reg_dec5_9__658; + wire plm_tsi0_reg_dec5_8__659; + wire plm_tsi0_reg_dec8_6__660; + wire plm_tsi0_reg_dec7_5__661; + wire plm_tsi0_reg_dec8_5__662; + wire plm_tsi0_reg_dec3_11__663; + wire plm_tsi0_reg_dec4_11__664; + wire plm_tsi0_reg_dec3_10__665; + wire plm_tsi0_reg_dec4_10__666; + wire plm_tsi0_reg_dec3_9__667; + wire plm_tsi0_reg_dec4_9__668; + wire plm_tsi0_reg_dec3_8__669; + wire plm_tsi0_reg_dec4_8__670; + wire plm_tsi0_reg_dec3_4__671; + wire plm_tsi0_reg_dec4_4__672; + wire plm_tsi0_reg_dec3_3__673; + wire plm_tsi0_reg_dec4_3__674; + wire plm_tsi0_reg_dec3_2__675; + wire plm_tsi0_reg_dec4_2__676; + wire plm_tsi0_reg_dec3_1__677; + wire plm_tsi0_reg_dec4_1__678; + wire plm_tsi0_reg_capture_inv_679; + wire plm_tsi0_reg_lane_pad_3; + wire plm_tsi0_reg_link_pad_3; + wire plm_tsi0_reg_linkctrl_3_3_; + wire plm_tsi0_reg_capture_now_680; + wire plm_tsi0_reg_linkctrl_3_0_; + wire plm_tsi0_reg_dec8_0_N_6; + wire plm_tsi0_reg_dec7_0_N_6; + wire plm_tsi0_reg_dec1_2_N_6; + wire plm_tsi0_reg_dec1_1_N_6; + wire plm_tsi0_reg_dec1_0_N_6; + wire plm_tsi0_reg_dec1_N_6; + wire plm_tsi0_VCC_681; + wire plm_tsi0_GND_682; + wire plm_dfm_N_8801_i_0_m2_0_683; + wire plm_dfm_by1_prec_rcverr; + wire plm_dfm_reg_phy_rframe_h_3; + wire plm_dfm_reg_phy_rframe_l_3; + wire plm_dfm_reg_phy_rbad_dfrm_h_3; + wire plm_dfm_reg_phy_rbad_dfrm_l_3; + wire plm_dfm_un4_reg_phy_ferr_h_n_i; + wire plm_dfm_un4_reg_phy_ferr_l_n_i; + wire plm_dfm_N_17411_i_684; + wire plm_dfm_ns_phy_rctrl_l_iv_0_m2_0_685; + wire plm_dfm_deframe1_dword_pop; + wire plm_dfm_deframe1_N_69404_i; + wire plm_dfm_deframe1_high0; + wire plm_dfm_deframe1_high1; + wire plm_dfm_deframe1_high2; + wire plm_dfm_deframe1_high3; + wire plm_dfm_deframe1_ferr; + wire plm_dfm_deframe1_N_18643_i; + wire plm_dfm_deframe1_N_18645_i; + wire plm_dfm_deframe1_push1; + wire plm_dfm_deframe1_det_d0_i; + wire plm_dfm_deframe1_reg_det_d1_686; + wire plm_dfm_deframe1_reg_det_d2_687; + wire plm_dfm_deframe1_reg_det_d3_688; + wire plm_dfm_deframe1_N_13549_i; + wire plm_dfm_deframe1_N_13547_i; + wire plm_dfm_deframe1_reg_dat_1_sqmuxa; + wire plm_dfm_deframe1_reg_dat_1_sqmuxa_1; + wire plm_dfm_deframe1_N_42622_i; + wire plm_dfm_deframe1_N_42621_i; + wire plm_dfm_deframe1_N_13553_i; + wire plm_dfm_deframe1_N_13551_i; + wire plm_dfm_deframe1_N_42623_i; + wire plm_dfm_deframe1_det_d0_i_i_689; + wire plm_dfm_deframe1_dwfsm_reg_ferr_40_i_i_a3_1_0; + wire plm_dfm_deframe1_dwfsm_ns_fsm_framing_iv_i_i_a3_1_690; + wire plm_dfm_deframe1_dwfsm_ns_fsm_errored_iv_0_0_691; + wire plm_dfm_deframe1_dwfsm_N_18662_1; + wire plm_dfm_deframe1_dwfsm_ns_fsm_framing_iv_i_i_0_692; + wire plm_dfm_deframe1_dwfsm_ns_fsm_framing_iv_i_i_a3_3_693; + wire plm_dfm_deframe1_dwfsm_ns_fsm_framing_iv_i_i_a3_0_694; + wire plm_dfm_deframe1_dwfsm_ns_fsm_framing_iv_i_i_a3_695; + wire plm_dfm_deframe1_dwfsm_ns_fsm_errored_iv_0_1_696; + wire plm_dfm_deframe1_dwfsm_N_18673_1; + wire plm_dfm_deframe1_dwfsm_reg_ferr_40_i_i_0; + wire plm_dfm_deframe1_dwfsm_ns_fsm_framing_iv_i_i_o4_697; + wire plm_dfm_deframe1_dwfsm_N_18633_i; + wire plm_dfm_deframe1_dwfsm_reg_fsm_framing_698; + wire plm_dfm_deframe1_dwfsm_N_8660_i; + wire plm_dfm_deframe1_dwfsm_reg_fsm_errored_699; + wire plm_dfm_deframe1_dwfsm_N_18637_i; + wire plm_dfm_deframe1_dwfsm_reg_high60; + wire plm_dfm_deframe1_dwfsm_reg_high59; + wire plm_dfm_deframe1_dwfsm_reg_high58; + wire plm_dfm_deframe1_dwfsm_N_8781_i; + wire plm_dfm_deframe1_dwfsm_N_18639_i; + wire plm_dfm_deframe1_dwfsm_N_18641_i; + wire plm_dfm_deframe1_dwbuf_GND_700; + wire plm_dfm_deframe1_dwbuf_un1_reg_cnt_1_cry_0_0_701; + wire plm_dfm_deframe1_dwbuf_un1_reg_cnt_1_cry_1_0_702; + wire plm_dfm_deframe1_dwbuf_un1_reg_cnt_1_cry_0_703; + wire plm_dfm_deframe1_dwbuf_un1_reg_cnt_1_cry_2_0_704; + wire plm_dfm_deframe1_dwbuf_un1_reg_cnt_1_cry_1_705; + wire plm_dfm_deframe1_dwbuf_un1_reg_cnt_1_cry_2_706; + wire plm_dfm_deframe1_dwbuf_N_22446; + wire plm_dfm_deframe1_dwbuf_N_22447; + wire plm_dfm_deframe1_dwbuf_N_22448; + wire plm_dfm_deframe1_dwbuf_N_22449; + wire plm_dfm_deframe1_dwbuf_N_22450; + wire plm_dfm_deframe1_dwbuf_N_22451; + wire plm_dfm_deframe1_dwbuf_N_22452; + wire plm_dfm_deframe1_dwbuf_N_22453; + wire plm_dfm_deframe1_dwbuf_N_22458; + wire plm_dfm_deframe1_dwbuf_N_22462; + wire plm_dfm_deframe1_dwbuf_N_22463; + wire plm_dfm_deframe1_dwbuf_N_22464; + wire plm_dfm_deframe1_dwbuf_N_22465; + wire plm_dfm_deframe1_dwbuf_N_22466; + wire plm_dfm_deframe1_dwbuf_N_22467; + wire plm_dfm_deframe1_dwbuf_N_22473; + wire plm_dfm_deframe1_dwbuf_N_22474; + wire plm_dfm_deframe1_dwbuf_N_51073; + wire plm_dfm_deframe1_dwbuf_N_51074; + wire plm_dfm_deframe1_dwbuf_N_22477; + wire plm_dfm_deframe1_dwbuf_N_22476; + wire plm_dfm_deframe1_dwbuf_N_22475; + wire plm_dfm_deframe1_dwbuf_N_22472; + wire plm_dfm_deframe1_dwbuf_N_22471; + wire plm_dfm_deframe1_dwbuf_N_22470; + wire plm_dfm_deframe1_dwbuf_N_22469; + wire plm_dfm_deframe1_dwbuf_N_22468; + wire plm_dfm_deframe1_dwbuf_N_22461; + wire plm_dfm_deframe1_dwbuf_N_22460; + wire plm_dfm_deframe1_dwbuf_N_22459; + wire plm_dfm_deframe1_dwbuf_N_22457; + wire plm_dfm_deframe1_dwbuf_N_22456; + wire plm_dfm_deframe1_dwbuf_N_22455; + wire plm_dfm_deframe1_dwbuf_N_22454; + wire plm_dfm_deframe1_dwbuf_N_69361_i_707; + wire plm_dfm_deframe1_dwbuf_N_69360_i_708; + wire plm_dfm_deframe1_dwbuf_reg_empty_5_0; + wire plm_dfm_deframe1_dwbuf_reg_empty_8_0_bm; + wire plm_dfm_deframe1_dwbuf_reg_empty_8_0_am; + wire plm_dfm_deframe1_dwbuf_reg_empty19_i; + wire plm_dfm_deframe1_dwbuf_reg_rp_4_p4; + wire plm_dfm_deframe1_dwbuf_un1_reg_cnt_1_axb_2_709; + wire plm_dfm_deframe1_dwbuf_un1_reg_cnt_1_axb_1_710; + wire plm_dfm_deframe1_dwbuf_reg_wp3_4_p4; + wire plm_dfm_deframe1_dwbuf_reg_wp2_4_p4; + wire plm_dfm_deframe1_dwbuf_reg_wp1_4_p4; + wire plm_dfm_deframe1_dwbuf_reg_wp0_4_p4; + wire plm_dfm_deframe1_dwbuf_reg_empty22_i; + wire plm_dfm_deframe1_dwbuf_un1_reg_cnt_1_s_3_711; + wire plm_dfm_deframe1_dwbuf_un1_reg_cnt_1_s_2_712; + wire plm_dfm_deframe1_dwbuf_un1_reg_cnt_1_s_1_713; + wire plm_dfm_deframe1_dwbuf_un1_reg_cnt_1_axb_0_714; + wire plm_dfm_deframe1_dwbuf_un1_reg_empty19_715; + wire plm_dfm_deframe1_dwbuf_reg_empty_8; + wire plm_dfm_deframe1_dwbuf_reg_empty_716; + wire plm_dfm_deframe1_dwbuf_un1_reg_cnt_1_axb_3_717; + wire plm_dfm_deframe1_qwfsm_pop_iv_1_718; + wire plm_dfm_deframe1_qwfsm_pop_iv_0_719; + wire plm_dfm_deframe1_qwfsm_reg_by1_preh_out16_720; + wire plm_dfm_deframe1_qwfsm_reg_phi0_721; + wire plm_dfm_deframe1_qwfsm_nxt_state_6_sqmuxa_1_722; + wire plm_dfm_deframe1_qwfsm_nxt_state_6_sqmuxa_723; + wire plm_dfm_deframe1_qwfsm_N_9986_i; + wire plm_dfm_deframe1_qwfsm_N_8792_i; + wire plm_dfm_deframe1_qwfsm_N_8793_i; + wire plm_dfm_deframe1_qwfsm_N_8794_i; + wire plm_dfm_deframe1_qwfsm_N_8795_i; + wire plm_dfm_deframe1_qwfsm_N_8796_i; + wire plm_dfm_deframe1_qwfsm_N_8797_i; + wire plm_dfm_deframe1_qwfsm_N_8798_i; + wire plm_dfm_deframe1_qwfsm_N_8799_i; + wire plm_dfm_deframe1_qwfsm_reg_phi1_724; + wire plm_sym_un6_reg_count_cry_0_725; + wire plm_sym_un6_reg_count_cry_1_726; + wire plm_sym_un6_reg_count_cry_2_727; + wire plm_sym_un6_reg_count_cry_3_728; + wire plm_sym_un6_reg_count_cry_4_729; + wire plm_sym_un6_reg_count_cry_5_730; + wire plm_sym_un6_reg_count_cry_6_731; + wire plm_sym_un6_reg_count_cry_7_732; + wire plm_sym_un6_reg_count_cry_8_733; + wire plm_sym_VCC_734; + wire plm_sym_un6_reg_count_cry_9_735; + wire plm_sym_un6_reg_count_cry_10_736; + wire plm_sym_GND_737; + wire plm_sym_un1_reg_outstanding_ccs_1_cry_0_738; + wire plm_sym_un1_reg_outstanding_ccs_1_cry_1_739; + wire plm_sym_un1_reg_outstanding_ccs_1_cry_2_740; + wire plm_sym_un6_reg_count_s_11_sf_741; + wire plm_sym_sym_symbol_3_; + wire plm_sym_sym_symbol_11_; + wire plm_sym_sym_symbol_14_; + wire plm_sym_sym_symbol_15_; + wire plm_sym_sym_symbol_13_; + wire plm_sym_sym_symbol_10_; + wire plm_sym_sym_symbol_2_; + wire plm_sym_sym_symbol_5_; + wire plm_sym_sym_symbol_6_; + wire plm_sym_N_51410; + wire plm_sym_N_8917; + wire plm_sym_insert_ccs_8_742; + wire plm_sym_insert_ccs_7_743; + wire plm_sym_insert_ccs_6_744; + wire plm_sym_sym_symbol_8_; + wire plm_sym_N_38406; + wire plm_sym_N_38411; + wire plm_sym_N_38395; + wire plm_sym_N_3502_i; + wire plm_sym_N_8657_1; + wire plm_sym_reg_tx0_raw_char_8_3_0_0_1_4_; + wire plm_sym_reg_tx0_raw_char_8_i_0_0_0_3_; + wire plm_sym_N_38407; + wire plm_sym_reg_tx0_raw_char_8_3_0_0_1_1_; + wire plm_sym_N_38514; + wire plm_sym_un6_reg_count_s_3_745; + wire plm_sym_un6_reg_count_s_2_746; + wire plm_sym_un6_reg_count_s_1_747; + wire plm_sym_N_51417; + wire plm_sym_N_51416; + wire plm_sym_N_51415; + wire plm_sym_reg_tx0_raw_char_8_i_0_0_0_12_; + wire plm_sym_N_51414; + wire plm_sym_N_51413; + wire plm_sym_N_38489; + wire plm_sym_sym_symbol_1_; + wire plm_sym_N_38246; + wire plm_sym_N_38400; + wire plm_sym_N_39041; + wire plm_sym_N_38402; + wire plm_sym_N_38399; + wire plm_sym_N_39030; + wire plm_sym_reg_tx0_raw_char_is_k_8_i_0_0_0_32080; + wire plm_sym_un1_reg_outstanding_ccs_1_axb_3_748; + wire plm_sym_un1_reg_outstanding_ccs_1_axb_2_749; + wire plm_sym_un1_reg_outstanding_ccs_1_axb_1_750; + wire plm_sym_frm_dispatched_ccs_751; + wire plm_sym_un6_reg_count_s_11_752; + wire plm_sym_un6_reg_count_s_10_753; + wire plm_sym_un6_reg_count_s_9_sf_754; + wire plm_sym_un6_reg_count_s_8_sf_755; + wire plm_sym_un6_reg_count_s_7_756; + wire plm_sym_un6_reg_count_s_6_757; + wire plm_sym_un6_reg_count_s_5_758; + wire plm_sym_un6_reg_count_s_4_759; + wire plm_sym_reg_frm_atomic_760; + wire plm_sym_insert_ccs_761; + wire plm_sym_N_8702_i; + wire plm_sym_N_67888_i; + wire plm_sym_N_8704_i; + wire plm_sym_N_8705_i; + wire plm_sym_N_24851_i; + wire plm_sym_N_69257_i; + wire plm_sym_N_67887_i; + wire plm_sym_reg_count_5_3__762; + wire plm_sym_reg_count_5_2__763; + wire plm_sym_reg_count_5_1__764; + wire plm_sym_reg_count_5_0__765; + wire plm_sym_N_20556_i; + wire plm_sym_N_20554_i; + wire plm_sym_N_20552_i; + wire plm_sym_N_20550_i; + wire plm_sym_N_20548_i; + wire plm_sym_N_20546_i; + wire plm_sym_N_67875_i; + wire plm_sym_N_20543_i; + wire plm_sym_N_37114_i; + wire plm_sym_N_8700_i; + wire plm_sym_N_8701_i; + wire plm_sym_N_20541_i; + wire plm_sym_N_20539_i; + wire plm_sym_un1_reg_outstanding_ccs_1_s_3_766; + wire plm_sym_un1_reg_outstanding_ccs_1_s_2_767; + wire plm_sym_un1_reg_outstanding_ccs_1_s_1_768; + wire plm_sym_un1_reg_outstanding_ccs_1_axb_0_769; + wire plm_sym_reg_count_5_11__770; + wire plm_sym_reg_count_5_10__771; + wire plm_sym_un6_reg_count_s_9_772; + wire plm_sym_un6_reg_count_s_8_773; + wire plm_sym_reg_count_5_7__774; + wire plm_sym_reg_count_5_6__775; + wire plm_sym_reg_count_5_5__776; + wire plm_sym_reg_count_5_4__777; + wire plm_sym_un6_reg_count_s_10_sf_778; + wire plm_sym_un6_reg_count_s_7_sf_779; + wire plm_sym_un6_reg_count_s_6_sf_780; + wire plm_sym_un6_reg_count_s_5_sf_781; + wire plm_sym_un6_reg_count_s_4_sf_782; + wire plm_sym_un6_reg_count_s_3_sf_783; + wire plm_sym_un6_reg_count_s_2_sf_784; + wire plm_sym_un6_reg_count_s_1_sf_785; + wire plm_sym_sym_gen_N_3524_i; + wire plm_sym_sym_gen_N_236; + wire plm_sym_sym_gen_N_148; + wire plm_sym_sym_gen_N_138; + wire plm_sym_sym_gen_N_133_i; + wire plm_sym_sym_gen_N_161; + wire plm_sym_sym_gen_N_3531; + wire plm_sym_sym_gen_N_3523_i; + wire plm_sym_sym_gen_next_addr39; + wire plm_sym_sym_gen_reg_rom_out_27_22_; + wire plm_sym_sym_gen_reg_rom_out_27_9_; + wire plm_sym_sym_gen_N_224_i_i_786; + wire plm_sym_sym_gen_reg_rom_out_27_6_; + wire plm_sym_sym_gen_N_9357_i_787; + wire plm_sym_sym_gen_reg_rom_out_27_4_; + wire plm_sym_sym_gen_reg_rom_out_27_3_; + wire plm_sym_sym_gen_reg_rom_out_27_2_; + wire plm_sym_sym_gen_reg_rom_out_27_1_; + wire plm_sym_sym_gen_reg_rom_out_27_0_; + wire plm_sym_sym_gen_next_addr45; + wire plm_sym_sym_gen_next_addr44; + wire plm_sym_sym_gen_next_addr43; + wire plm_sym_sym_gen_next_addr40; + wire plm_sym_sym_gen_reg_rom_out_27_30_; + wire plm_sym_sym_gen_reg_rom_out_27_29_; + wire plm_sym_sym_gen_reg_rom_out_27_28_; + wire plm_sym_sym_gen_N_9369_i_788; + wire plm_sym_sym_gen_N_9370_i_789; + wire plm_sym_sym_gen_N_9371_i_790; + wire plm_sym_sym_gen_reg_rom_out_27_24_; + wire plm_sym_sym_gen_reg_rom_out_27_23_; + wire plm_sym_sym_gen_reg_rom_out_27_32_; + wire plm_sym_sym_gen_reg_rom_out_27_31_; + wire plm_frm_by1_opportunity_l_791; + wire plm_frm_by1_opportunity_h_792; + wire plm_frm_reg_d1_idleflag_hh_3_4; + wire plm_frm_reg_d1_idleflag_hh_3_0; + wire plm_frm_reg_d1_idleflag_hl_3_4; + wire plm_frm_reg_d1_idleflag_hl_3_0; + wire plm_frm_reg_d1_idleflag_lh_3_4; + wire plm_frm_reg_d1_idleflag_lh_3_0; + wire plm_frm_reg_d1_idleflag_ll_3_4; + wire plm_frm_reg_d1_idleflag_ll_3_0; + wire plm_frm_un1_d1_idle_h_793; + wire plm_frm_un1_d1_idle_l_794; + wire plm_frm_reg_d2_td_13_63_; + wire plm_frm_un1_reg_d2_td_0_sqmuxa_i; + wire plm_frm_d1_start_h_795; + wire plm_frm_N_8807; + wire plm_frm_un1_reg_d2_td_0_sqmuxa_1_i; + wire plm_frm_reg_d2_charisk37; + wire plm_frm_d1_end_h_796; + wire plm_frm_reg_d2_charisk69; + wire plm_frm_d1_end_l_797; + wire plm_frm_by1_frm_atomic; + wire plm_frm_by1_frm0_char_9_; + wire plm_frm_by1_frm0_char_8_; + wire plm_frm_by1_frm0_char_7_; + wire plm_frm_by1_frm0_char_6_; + wire plm_frm_by1_frm0_char_5_; + wire plm_frm_N_8665_i; + wire plm_frm_N_8666_i; + wire plm_frm_N_8667_i; + wire plm_frm_by1_frm0_char_1_; + wire plm_frm_by1_frm0_char_0_; + wire plm_frm_by1_frm0_char_15_; + wire plm_frm_by1_frm0_char_14_; + wire plm_frm_by1_frm0_char_13_; + wire plm_frm_by1_frm0_char_12_; + wire plm_frm_by1_frm0_char_11_; + wire plm_frm_by1_frm0_char_10_; + wire plm_frm_reg_d0_tctrl_h_798; + wire plm_frm_reg_d1_tctrl_h_799; + wire plm_frm_reg_d0_tctrl_l_800; + wire plm_frm_reg_d1_tctrl_l_801; + wire plm_frm_reg_d0_tframe_h_802; + wire plm_frm_reg_d0_tframe_l_803; + wire plm_frm_reg_d1_tframe_h_804; + wire plm_frm_reg_d2_tframe_h_805; + wire plm_frm_reg_d1_tframe_l_806; + wire plm_frm_reg_d2_tframe_l_807; + wire plm_frm_reg_d1_idleflag_hh_3; + wire plm_frm_reg_d1_idleflag_hh_808; + wire plm_frm_reg_d1_idleflag_hl_3; + wire plm_frm_reg_d1_idleflag_hl_809; + wire plm_frm_reg_d1_idleflag_lh_3; + wire plm_frm_reg_d1_idleflag_lh_810; + wire plm_frm_reg_d1_idleflag_ll_3; + wire plm_frm_reg_d1_idleflag_ll_811; + wire plm_frm_N_9970_i_812; + wire plm_frm_reg_d2_idle_h_813; + wire plm_frm_N_9969_i_814; + wire plm_frm_reg_d2_idle_l_815; + wire plm_frm_reg_d2_charisk_1_sqmuxa_2_816; + wire plm_frm_reg_d2_charisk_0__817; + wire plm_frm_reg_d2_charisk_1_sqmuxa_1_818; + wire plm_frm_reg_d2_charisk_7__819; + wire plm_frm_reg_d2_charisk_1_sqmuxa_820; + wire plm_frm_reg_d2_charisk_4__821; + wire plm_frm_reg_d2_charisk_1_sqmuxa_3_822; + wire plm_frm_reg_d2_charisk_3__823; + wire plm_frm_N_8815_i; + wire plm_frm_N_8817_i; + wire plm_frm_N_8818_i; + wire plm_frm_N_8819_i; + wire plm_frm_N_8820_i; + wire plm_frm_N_8821_i_0; + wire plm_frm_N_8823_i; + wire plm_frm_N_8806_i; + wire plm_frm_N_8808_i; + wire plm_frm_N_8809_i; + wire plm_frm_N_8810_i; + wire plm_frm_N_8811_i; + wire plm_frm_N_8812_i_0; + wire plm_frm_N_8814_i; + wire plm_frm_reg_d2_td_13_62_; + wire plm_frm_reg_d2_td_13_60_; + wire plm_frm_reg_d2_td_13_59_; + wire plm_frm_reg_d2_td_13_55_; + wire plm_frm_reg_d2_td_13_54_; + wire plm_frm_reg_d2_td_13_53_; + wire plm_frm_reg_d2_td_13_52_; + wire plm_frm_reg_d2_td_13_51_; + wire plm_frm_reg_d2_td_13_50_; + wire plm_frm_reg_d2_td_13_49_; + wire plm_frm_reg_d2_td_13_48_; + wire plm_frm_reg_d2_td_13_47_; + wire plm_frm_reg_d2_td_13_46_; + wire plm_frm_reg_d2_td_13_45_; + wire plm_frm_reg_d2_td_13_44_; + wire plm_frm_reg_d2_td_13_43_; + wire plm_frm_reg_d2_td_13_42_; + wire plm_frm_reg_d2_td_13_41_; + wire plm_frm_reg_d2_td_13_40_; + wire plm_frm_reg_d2_td_13_39_; + wire plm_frm_reg_d2_td_13_38_; + wire plm_frm_reg_d2_td_13_37_; + wire plm_frm_reg_d2_td_13_36_; + wire plm_frm_reg_d2_td_13_35_; + wire plm_frm_reg_d2_td_13_34_; + wire plm_frm_reg_d2_td_24_30_; + wire plm_frm_reg_d2_td_24_28_; + wire plm_frm_reg_d2_td_24_27_; + wire plm_frm_reg_d2_td_24_23_; + wire plm_frm_reg_d2_td_24_22_; + wire plm_frm_reg_d2_td_24_21_; + wire plm_frm_reg_d2_td_24_20_; + wire plm_frm_reg_d2_td_24_19_; + wire plm_frm_reg_d2_td_24_18_; + wire plm_frm_reg_d2_td_24_17_; + wire plm_frm_reg_d2_td_24_16_; + wire plm_frm_reg_d2_td_24_15_; + wire plm_frm_reg_d2_td_24_14_; + wire plm_frm_reg_d2_td_24_13_; + wire plm_frm_reg_d2_td_24_12_; + wire plm_frm_reg_d2_td_24_11_; + wire plm_frm_reg_d2_td_24_10_; + wire plm_frm_reg_d2_td_24_9_; + wire plm_frm_reg_d2_td_24_8_; + wire plm_frm_reg_d2_td_24_7_; + wire plm_frm_reg_d2_td_24_6_; + wire plm_frm_reg_d2_td_24_5_; + wire plm_frm_reg_d2_td_24_4_; + wire plm_frm_reg_d2_td_24_3_; + wire plm_frm_reg_d2_td_24_2_; + wire plm_frm_frame1_un1_reg_by1_frm0_char_1_sqmuxa_2_0_824; + wire plm_frm_frame1_N_9974; + wire plm_frm_frame1_un1_reg_by1_frm0_char_1_sqmuxa_2_1_825; + wire plm_frm_frame1_N_9975; + wire plm_frm_frame1_reg_by1_frm0_char_0_bm_10__826; + wire plm_frm_frame1_reg_by1_frm0_char_0_am_10__827; + wire plm_frm_frame1_reg_by1_frm0_char_0_bm_12__828; + wire plm_frm_frame1_reg_by1_frm0_char_0_am_12__829; + wire plm_frm_frame1_reg_by1_frm0_char_0_bm_8__830; + wire plm_frm_frame1_reg_by1_frm0_char_0_am_8__831; + wire plm_frm_frame1_reg_by1_frm0_char_sn_m1_0_a3_832; + wire plm_frm_frame1_reg_by1_frm0_char_0_bm_11__833; + wire plm_frm_frame1_reg_by1_frm0_char_0_am_11__834; + wire plm_frm_frame1_N_6132; + wire plm_frm_frame1_reg_by1_frm0_char_0_bm_13__835; + wire plm_frm_frame1_reg_by1_frm0_char_0_am_13__836; + wire plm_frm_frame1_reg_by1_frm0_char_sn_m4_i_a3_837; + wire plm_frm_frame1_reg_by1_frm0_char_sn_m6_i_838; + wire plm_frm_frame1_N_6134; + wire plm_frm_frame1_reg_by1_frm0_char_sn_m9_i_839; + wire plm_frm_frame1_reg_by1_frm0_char_0_bm_15__840; + wire plm_frm_frame1_reg_by1_frm0_char_0_am_15__841; + wire plm_frm_frame1_N_6195; + wire plm_frm_frame1_N_6194; + wire plm_frm_frame1_N_6193; + wire plm_frm_frame1_N_6192; + wire plm_frm_frame1_N_6191; + wire plm_frm_frame1_N_6190; + wire plm_frm_frame1_N_6189; + wire plm_frm_frame1_N_9971; + wire plm_frm_frame1_N_6188; + wire plm_frm_frame1_reg_byp3_842; + wire plm_frm_frame1_reg_byp1_843; + wire plm_fsm_un1_reg_tx_count17_1; + wire plm_fsm_N_38100_i_i; + wire plm_fsm_reg_expired_5_1; + wire plm_fsm_N_38564_i; + wire plm_fsm_reg_tx_expired; + wire plm_fsm_reg_tx_count_4_; + wire plm_fsm_reg_tx_count_10_; + wire plm_fsm_un1_reg_tx_count17_0; + wire plm_fsm_reg_oneshot_0; + wire plm_fsm_N_38476_1; + wire plm_fsm_N_38512_1; + wire plm_fsm_un1_reg_tx_count17; + wire plm_fsm_reg_oneshot; + wire plm_fsm_reg_tx_count_6_10_; + wire plm_fsm_reg_tx_count_6_4_; + wire plm_fsm_ci_cntrout3; + wire plm_fsm_ci_cntrout1; + wire plm_fsm_N_18398_i; + wire plm_fsm_pa_cntrout3; + wire plm_fsm_pa_cntrout2; + wire plm_fsm_pa_cntrout1; + wire plm_fsm_ri_cntrout3; + wire plm_fsm_ri_cntrout2; + wire plm_fsm_ri_cntrout1; + wire plm_fsm_un1_reg_state_4_i_i_844; + wire plm_fsm_pc_cntrout3; + wire plm_fsm_pc_cntrout2; + wire plm_fsm_pc_cntrout1; + wire plm_fsm_un3_xl_clw0_newv_NE_3_845; + wire plm_fsm_un3_clw0_newv_NE_3_846; + wire plm_fsm_rl_cntrout3; + wire plm_fsm_rl_cntrout2; + wire plm_fsm_rl_cntrout1; + wire plm_fsm_reg_123_link_pad_36_0_a2_i_0_a4_6; + wire plm_fsm_reg_123_link_pad_36_0_a2_i_0_a4_5; + wire plm_fsm_ci_idle_data_i_o3_i_a4_0_847; + wire plm_fsm_ci_cntrout2; + wire plm_fsm_ci_cntrout0; + wire plm_fsm_rl_extdout; + wire plm_fsm_un1_linklanematch0_NE_3_848; + wire plm_fsm_un1_linklanematch0_NE_2_849; + wire plm_fsm_un1_linklanematch0_NE_1_850; + wire plm_fsm_un1_linklanematch0_NE_0_851; + wire plm_fsm_N_38118_i; + wire plm_fsm_un3_clw0_newv_NE_2_852; + wire plm_fsm_un3_clw0_newv_NE_1_853; + wire plm_fsm_un3_clw0_newv_NE_0_854; + wire plm_fsm_N_51450; + wire plm_fsm_N_51449; + wire plm_fsm_N_51382; + wire plm_fsm_un3_xl_clw0_newv_NE_4_855; + wire plm_fsm_un3_xl_clw0_newv_NE_2_856; + wire plm_fsm_un3_xl_clw0_newv_NE_1_857; + wire plm_fsm_un3_xl_clw0_newv_NE_0_858; + wire plm_fsm_N_38122_i; + wire plm_fsm_N_38114_i; + wire plm_fsm_N_38341; + wire plm_fsm_N_38139_i; + wire plm_fsm_N_23238_i; + wire plm_fsm_N_38060_i; + wire plm_fsm_N_39026; + wire plm_fsm_N_38988; + wire plm_fsm_N_38611; + wire plm_fsm_N_38735_1; + wire plm_fsm_reg_state86; + wire plm_fsm_N_9824; + wire plm_fsm_reg_state_3_sqmuxa_2_859; + wire plm_fsm_pc_timeout; + wire plm_fsm_pc_cntrout0; + wire plm_fsm_reg_state_141_0_0_0_1_iv_0_0_; + wire plm_fsm_un3_clw0_newv_NE_6_860; + wire plm_fsm_un3_clw0_newv_NE_4_861; + wire plm_fsm_N_38981; + wire plm_fsm_N_39022; + wire plm_fsm_N_38189_i; + wire plm_fsm_reg_state_141_0_0_0_1_iv_0_32192; + wire plm_fsm_N_25635_i; + wire plm_fsm_N_38095_i; + wire plm_fsm_N_38096_i; + wire plm_fsm_N_39050_1; + wire plm_fsm_N_38588; + wire plm_fsm_N_39043; + wire plm_fsm_N_38236_i; + wire plm_fsm_N_38466; + wire plm_fsm_reg_rx_clear_cs_1_sqmuxa_12_1_862; + wire plm_fsm_N_51356; + wire plm_fsm_reg_123_link_pad_36_0_a2_i_0_a4_8; + wire plm_fsm_reg_123_link_pad_36_0_a2_i_0_a4_7; + wire plm_fsm_N_38416; + wire plm_fsm_N_39364_1_i_1; + wire plm_fsm_N_39011; + wire plm_fsm_N_39007; + wire plm_fsm_N_39017; + wire plm_fsm_N_38241_i; + wire plm_fsm_N_38087_i; + wire plm_fsm_N_38987_1; + wire plm_fsm_N_38986; + wire plm_fsm_N_38238_i; + wire plm_fsm_N_39351_i; + wire plm_fsm_N_39348_i; + wire plm_fsm_N_38180_i; + wire plm_fsm_reg_rx_clear_cs_98_0_0_0_1_iv_i_o3_4_1_0_o3_12; + wire plm_fsm_un1_reg_state_18_i_0_0_1_863; + wire plm_fsm_N_38485; + wire plm_fsm_N_38336; + wire plm_fsm_N_39034; + wire plm_fsm_N_38342; + wire plm_fsm_reg_rx_clear_cs_98_0_0_0_1_iv_i_o3_4_1_0_o3_7; + wire plm_fsm_N_38761; + wire plm_fsm_reg_rx_clear_cs_98_0_0_0_1_iv_i_0_o3_17_1; + wire plm_fsm_N_38997; + wire plm_fsm_N_38137_i; + wire plm_fsm_rl_cntrout0; + wire plm_fsm_N_39002; + wire plm_fsm_reg_rx_clear_cs_98_0_0_0_1_iv_i_0_o3_4_0; + wire plm_fsm_N_39361_i; + wire plm_fsm_reg_rx_clear_cs_98_0_0_0_1_iv_i_0_o3_2_1; + wire plm_fsm_N_39015; + wire plm_fsm_N_38157_i; + wire plm_fsm_reg_rx_clear_cs_98_0_0_0_1_iv_i_0_6; + wire plm_fsm_N_38591; + wire plm_fsm_N_38083_i; + wire plm_fsm_N_39051; + wire plm_fsm_N_39029; + wire plm_fsm_N_38161_i; + wire plm_fsm_N_51184; + wire plm_fsm_N_38197_i; + wire plm_fsm_N_51384; + wire plm_fsm_N_38598; + wire plm_fsm_N_38593; + wire plm_fsm_pc_timeout_1; + wire plm_fsm_reg_state_141_0_0_0_1_iv_2_32191; + wire plm_fsm_N_38608; + wire plm_fsm_N_38599; + wire plm_fsm_N_38192_i; + wire plm_fsm_N_38479; + wire plm_fsm_N_38483; + wire plm_fsm_reg_state_3_sqmuxa_5_1_864; + wire plm_fsm_reg_state_1_sqmuxa_2_865; + wire plm_fsm_reg_state_4_sqmuxa_1_1_866; + wire plm_fsm_reg_state_2_sqmuxa_2_867; + wire plm_fsm_reg_link_mode_m_868; + wire plm_fsm_hr_timeout_i_0_0_0_o4; + wire plm_fsm_N_38471; + wire plm_fsm_reg_rx_clear_cs_4_sqmuxa_1_0_0; + wire plm_fsm_N_51392; + wire plm_fsm_N_38733_1; + wire plm_fsm_N_38473_1; + wire plm_fsm_ri_cntrout0; + wire plm_fsm_reg_rx_clear_cs_2_sqmuxa_9_0_869; + wire plm_fsm_reg_state_141_0_0_0_1_iv_0_12_; + wire plm_fsm_N_38132_i; + wire plm_fsm_reg_state_2_sqmuxa_3_1_870; + wire plm_fsm_ci_timeout; + wire plm_fsm_N_51381; + wire plm_fsm_N_38611_1_0; + wire plm_fsm_N_39005; + wire plm_fsm_N_38164_i; + wire plm_fsm_N_38203_i; + wire plm_fsm_N_38173_i; + wire plm_fsm_N_38436; + wire plm_fsm_N_38371; + wire plm_fsm_reg_rx_clear_cs_4_sqmuxa_1_0; + wire plm_fsm_N_67847_2; + wire plm_fsm_N_67847_1; + wire plm_fsm_reg_123_link_pad_36_0_a2_i_0_1; + wire plm_fsm_N_38601_1; + wire plm_fsm_un1_reg_state_22_i_0_0_1_871; + wire plm_fsm_N_38379_i; + wire plm_fsm_reg_rx_clear_cs_98_0_0_0_1_iv_i_0_o3_3_0; + wire plm_fsm_N_8826; + wire plm_fsm_reg_rx_clear_cs_98_0_0_0_1_iv_i_0_5; + wire plm_fsm_reg_rx_clear_cs_98_0_0_0_1_iv_i_0_5_1; + wire plm_fsm_N_39018; + wire plm_fsm_N_38163; + wire plm_fsm_N_38989; + wire plm_fsm_N_38506; + wire plm_fsm_reg_rx_clear_cs_98_0_0_0_1_iv_i_0_2; + wire plm_fsm_reg_rx_clear_cs_98_0_0_0_1_iv_i_0_2_1; + wire plm_fsm_N_38201_i; + wire plm_fsm_N_38061_i; + wire plm_fsm_xl_cls_timeout; + wire plm_fsm_N_51352; + wire plm_fsm_reg_state_1_sqmuxa_10_872; + wire plm_fsm_N_38196_i; + wire plm_fsm_reg_rx_clear_cs_98_0_0_0_1_iv_i_o3_4_1_0_o3_10; + wire plm_fsm_N_39047; + wire plm_fsm_N_38481; + wire plm_fsm_reg_rx_clear_cs_98_0_0_0_1_iv_i_0_o3_20_2; + wire plm_fsm_reg_rx_clear_cs_98_0_0_0_1_iv_i_0_o3_20_2_1; + wire plm_fsm_N_38245_i; + wire plm_fsm_N_38198_i; + wire plm_fsm_N_51318; + wire plm_fsm_N_38465_1; + wire plm_fsm_rc_timeout_1; + wire plm_fsm_N_51397; + wire plm_fsm_pa_cntrout0; + wire plm_fsm_N_38375_i; + wire plm_fsm_N_51395; + wire plm_fsm_N_38130_i; + wire plm_fsm_N_39004; + wire plm_fsm_N_38102_i; + wire plm_fsm_N_38126_i; + wire plm_fsm_N_38117_i; + wire plm_fsm_N_38590; + wire plm_fsm_N_67838_i; + wire plm_fsm_N_9217_i; + wire plm_fsm_reg_state_8__873; + wire plm_fsm_N_67825_i; + wire plm_fsm_reg_state_7__874; + wire plm_fsm_N_9344_i; + wire plm_fsm_reg_state_6__875; + wire plm_fsm_N_69127_i; + wire plm_fsm_reg_state_5__876; + wire plm_fsm_N_69128_i; + wire plm_fsm_reg_state_4__877; + wire plm_fsm_N_67848_i; + wire plm_fsm_reg_state_3__878; + wire plm_fsm_N_9214_i; + wire plm_fsm_N_69295_i; + wire plm_fsm_N_9213_i; + wire plm_fsm_reg_state_0__879; + wire plm_fsm_N_67824_i; + wire plm_fsm_reg_state_23__880; + wire plm_fsm_N_9333_i; + wire plm_fsm_reg_state_22__881; + wire plm_fsm_N_69079_i; + wire plm_fsm_reg_state_21__882; + wire plm_fsm_N_9335_i; + wire plm_fsm_reg_state_20__883; + wire plm_fsm_N_9336_i; + wire plm_fsm_reg_state_19__884; + wire plm_fsm_N_9337_i; + wire plm_fsm_reg_state_18__885; + wire plm_fsm_N_69350_i; + wire plm_fsm_N_69076_i; + wire plm_fsm_N_69358_i; + wire plm_fsm_N_69077_i; + wire plm_fsm_N_69304_i; + wire plm_fsm_N_9220_i; + wire plm_fsm_N_9219_i; + wire plm_fsm_N_69283_i; + wire plm_fsm_reg_state_10__886; + wire plm_fsm_N_67832_i; + wire plm_fsm_reg_send_command_28_2_; + wire plm_fsm_N_38531_i; + wire plm_fsm_reg_send_command_28_0_; + wire plm_fsm_N_67881_i; + wire plm_fsm_reg_state_24__887; + wire plm_fsm_N_38583_i; + wire plm_fsm_N_38556_i; + wire plm_fsm_N_38559_i_888; + wire plm_fsm_N_38537_i_889; + wire plm_fsm_reg_sel_by1_890; + wire plm_fsm_VCC_891; + wire plm_fsm_reg_link_mode_892; + wire plm_fsm_un1_reg_state_22_i_o2_1_i_a2_0_a4_893; + wire plm_fsm_reg_noscramble_27; + wire plm_fsm_N_69263_i_894; + wire plm_fsm_reg_rl_throw_a_bone_895; + wire plm_fsm_reg_fix_polarity_896; + wire plm_fsm_reg_rx0_polarity_3; + wire plm_fsm_N_9826_i_897; + wire plm_fsm_reg_123_lane_pad_35; + wire plm_fsm_reg_123_lane_pad_898; + wire plm_fsm_N_67847_i_899; + wire plm_fsm_N_19146_i; + wire plm_fsm_N_24595_i; + wire plm_fsm_reg_123_link_pad_900; + wire plm_fsm_N_19144_i; + wire plm_fsm_N_19142_i; + wire plm_fsm_reg_state_i_16__901; + wire plm_fsm_reg_state_i_1__902; + wire plm_fsm_reg_state_1__903; + wire plm_fsm_reg_state_i_13__904; + wire plm_fsm_reg_state_i_2__905; + wire plm_fsm_reg_state_i_11__906; + wire plm_fsm_N_38123_i_i_907; + wire plm_fsm_N_38472_1; + wire plm_fsm_N_38983; + wire plm_fsm_N_38983_1; + wire plm_fsm_N_38469; + wire plm_fsm_N_38604_i; + wire plm_fsm_cc_cntrout0; + wire plm_fsm_reg_rx_clear_cs_98_0_0_0_1_iv_i_o3_4_1_0_o3_10_0; + wire plm_fsm_N_26212_i_i_0; + wire plm_fsm_reg_state_15__908; + wire plm_fsm_reg_state_14__909; + wire plm_fsm_rc_cntrout_ts2_0; + wire plm_fsm_N_38134_i; + wire plm_fsm_reg_expired; + wire plm_fsm_N_39033; + wire plm_fsm_reg_state_9__910; + wire plm_fsm_dq_timer_GND_911; + wire plm_fsm_dq_timer_N_51448; + wire plm_fsm_pa_timer_GND_912; + wire plm_fsm_pa_timer_N_51451; + wire plm_fsm_pa_timer_N_51396; + wire plm_fsm_pa_counter0_VCC_913; + wire plm_fsm_pa_counter0_N_38422; + wire plm_fsm_pa_counter0_un1_reg_rx_count_0_a4_5; + wire plm_fsm_pa_counter0_un1_reg_rx_count_0_a4_4; + wire plm_fsm_pa_counter0_un1_reg_tx_count_0_a4_8; + wire plm_fsm_pa_counter0_un1_reg_tx_count_0_a4_7; + wire plm_fsm_pa_counter0_un1_reg_tx_count_0_a4_6; + wire plm_fsm_pa_counter0_N_38421; + wire plm_fsm_pa_counter0_un1_enable_1_i_914; + wire plm_fsm_pa_counter0_N_38532_i_915; + wire plm_fsm_pa_counter0_un1_reg_rx_expired_1_i; + wire plm_fsm_pa_counter0_reg_expired_5; + wire plm_fsm_pa_counter0_N_38549_i; + wire plm_fsm_pa_counter0_reg_tx_expired_916; + wire plm_fsm_pa_counter0_N_38548_i; + wire plm_fsm_pa_counter0_N_9959_i; + wire plm_fsm_pa_counter0_un1_enable_1; + wire plm_fsm_pa_counter1_VCC_917; + wire plm_fsm_pa_counter1_un1_reg_tx_count_0_a4_8; + wire plm_fsm_pa_counter1_un1_reg_tx_count_0_a4_7; + wire plm_fsm_pa_counter1_un1_reg_tx_count_0_a4_6; + wire plm_fsm_pa_counter1_un1_enable_1_i_918; + wire plm_fsm_pa_counter1_N_38533_i_919; + wire plm_fsm_pa_counter1_reg_expired_5; + wire plm_fsm_pa_counter1_N_38547_i; + wire plm_fsm_pa_counter1_N_38546_i; + wire plm_fsm_pa_counter1_reg_tx_expired_920; + wire plm_fsm_pa_counter1_N_38545_i; + wire plm_fsm_pa_counter1_reg_rx_expired_921; + wire plm_fsm_pa_counter1_un1_enable_1; + wire plm_fsm_pa_counter2_VCC_922; + wire plm_fsm_pa_counter2_un1_reg_tx_count_0_a4_8; + wire plm_fsm_pa_counter2_un1_reg_tx_count_0_a4_7; + wire plm_fsm_pa_counter2_un1_reg_tx_count_0_a4_6; + wire plm_fsm_pa_counter2_un1_enable_1_i_923; + wire plm_fsm_pa_counter2_N_38534_i_924; + wire plm_fsm_pa_counter2_reg_expired_5; + wire plm_fsm_pa_counter2_N_38544_i; + wire plm_fsm_pa_counter2_N_38543_i; + wire plm_fsm_pa_counter2_reg_tx_expired_925; + wire plm_fsm_pa_counter2_N_38542_i; + wire plm_fsm_pa_counter2_reg_rx_expired_926; + wire plm_fsm_pa_counter2_un1_enable_1; + wire plm_fsm_pa_counter3_VCC_927; + wire plm_fsm_pa_counter3_un1_reg_tx_count_0_a4_8; + wire plm_fsm_pa_counter3_un1_reg_tx_count_0_a4_7; + wire plm_fsm_pa_counter3_un1_reg_tx_count_0_a4_6; + wire plm_fsm_pa_counter3_un1_enable_1_i_928; + wire plm_fsm_pa_counter3_N_38535_i_929; + wire plm_fsm_pa_counter3_reg_expired_5; + wire plm_fsm_pa_counter3_N_38541_i; + wire plm_fsm_pa_counter3_N_38540_i; + wire plm_fsm_pa_counter3_reg_tx_expired_930; + wire plm_fsm_pa_counter3_N_38539_i; + wire plm_fsm_pa_counter3_reg_rx_expired_931; + wire plm_fsm_pa_counter3_un1_enable_1; + wire plm_fsm_pc_timer_GND_932; + wire plm_fsm_pc_timer_N_51446; + wire plm_fsm_pc_counter0_VCC_933; + wire plm_fsm_pc_counter0_un1_reg_tx_count_0_a2_5; + wire plm_fsm_pc_counter0_un1_reg_tx_count_0_a2_4; + wire plm_fsm_pc_counter0_un1_reg_rx_count_0_a2_5; + wire plm_fsm_pc_counter0_un1_reg_rx_count_0_a2_4; + wire plm_fsm_pc_counter0_N_38554_i_934; + wire plm_fsm_pc_counter0_un1_rx_ts1_i; + wire plm_fsm_pc_counter0_reg_expired_5; + wire plm_fsm_pc_counter0_reg_oneshot_935; + wire plm_fsm_pc_counter0_N_38706_i; + wire plm_fsm_pc_counter0_un1_enable_2_i_936; + wire plm_fsm_pc_counter0_reg_tx_expired_937; + wire plm_fsm_pc_counter0_N_38576_i; + wire plm_fsm_pc_counter0_un1_enable_0_a2_0_a2_0_a4_0; + wire plm_fsm_pc_counter0_un1_enable_1_i_938; + wire plm_fsm_pc_counter0_N_69324_i_939; + wire plm_fsm_pc_counter0_un1_reg_tx_count17; + wire plm_fsm_pc_counter0_un1_enable_1; + wire plm_fsm_pc_counter1_VCC_940; + wire plm_fsm_pc_counter1_un1_reg_tx_count_0_a2_0_a4_5; + wire plm_fsm_pc_counter1_un1_reg_tx_count_0_a2_0_a4_4; + wire plm_fsm_pc_counter1_un1_enable_1_i_941; + wire plm_fsm_pc_counter1_N_38555_i_942; + wire plm_fsm_pc_counter1_reg_expired_5; + wire plm_fsm_pc_counter1_N_38538_i; + wire plm_fsm_pc_counter1_N_38705_i; + wire plm_fsm_pc_counter1_reg_rx_expired_943; + wire plm_fsm_pc_counter1_un1_enable_2_i_944; + wire plm_fsm_pc_counter1_reg_tx_expired_945; + wire plm_fsm_pc_counter1_un1_enable_1; + wire plm_fsm_pc_counter2_VCC_946; + wire plm_fsm_pc_counter2_un1_reg_tx_count_0_a2_0_a4_5; + wire plm_fsm_pc_counter2_un1_reg_tx_count_0_a2_0_a4_4; + wire plm_fsm_pc_counter2_un1_enable_1_i_947; + wire plm_fsm_pc_counter2_N_38628_i_948; + wire plm_fsm_pc_counter2_reg_expired_5; + wire plm_fsm_pc_counter2_N_38704_i; + wire plm_fsm_pc_counter2_N_38703_i; + wire plm_fsm_pc_counter2_reg_rx_expired_949; + wire plm_fsm_pc_counter2_un1_enable_2_i_950; + wire plm_fsm_pc_counter2_reg_tx_expired_951; + wire plm_fsm_pc_counter2_un1_enable_1; + wire plm_fsm_pc_counter3_VCC_952; + wire plm_fsm_pc_counter3_un1_reg_tx_count_0_a2_0_a4_5; + wire plm_fsm_pc_counter3_un1_reg_tx_count_0_a2_0_a4_4; + wire plm_fsm_pc_counter3_un1_enable_1_i_953; + wire plm_fsm_pc_counter3_N_38629_i_954; + wire plm_fsm_pc_counter3_reg_expired_5; + wire plm_fsm_pc_counter3_N_38630_i; + wire plm_fsm_pc_counter3_N_38619_i; + wire plm_fsm_pc_counter3_reg_rx_expired_955; + wire plm_fsm_pc_counter3_un1_enable_2_i_956; + wire plm_fsm_pc_counter3_reg_tx_expired_957; + wire plm_fsm_pc_counter3_un1_enable_1; + wire plm_fsm_cls_timer_GND_958; + wire plm_fsm_cls_timer_N_51461; + wire plm_fsm_cls_timer_N_51383; + wire plm_fsm_cls_timer_un1_reg_state_i_i_959; + wire plm_fsm_cla_timer_GND_960; + wire plm_fsm_cla_timer_un1_expired_2ms_0_a2_0_a2_0_961; + wire plm_fsm_cla_timer_un1_reg_state_1_i_i_962; + wire plm_fsm_clw_timer_GND_963; + wire plm_fsm_clw_timer_N_51455; + wire plm_fsm_clw_timer_un1_expired_2ms_0_a2_0_a4_0_964; + wire plm_fsm_clw_timer_N_51457; + wire plm_fsm_clw_timer_N_51456; + wire plm_fsm_clw_timer_N_51454; + wire plm_fsm_cc_timer_GND_965; + wire plm_fsm_cc_timer_N_51460; + wire plm_fsm_cc_timer_un1_expired_2ms_0_a2_0_a4_0_966; + wire plm_fsm_cc_timer_count_20_; + wire plm_fsm_cc_timer_count_18_; + wire plm_fsm_cc_timer_N_51459; + wire plm_fsm_cc_counter0_VCC_967; + wire plm_fsm_cc_counter0_un1_reg_tx_count_0_a2_0_a4_5; + wire plm_fsm_cc_counter0_un1_reg_tx_count_0_a2_0_a4_4; + wire plm_fsm_cc_counter0_un1_reg_rx_count_0_a4_5; + wire plm_fsm_cc_counter0_un1_reg_rx_count_0_a4_4; + wire plm_fsm_cc_counter0_N_24684_i_i_968; + wire plm_fsm_cc_counter0_N_69226_i_969; + wire plm_fsm_cc_counter0_N_69225_i; + wire plm_fsm_cc_counter0_N_24582_i; + wire plm_fsm_cc_counter0_N_24639_i_i; + wire plm_fsm_cc_counter0_reg_oneshot_970; + wire plm_fsm_cc_counter0_N_69253_i; + wire plm_fsm_cc_counter0_N_69088_i_971; + wire plm_fsm_cc_counter0_reg_tx_expired_972; + wire plm_fsm_cc_counter0_N_69086_i_973; + wire plm_fsm_cc_counter0_N_38368_i; + wire plm_fsm_cc_counter0_N_24684_i; + wire plm_fsm_ci_timer_GND_974; + wire plm_fsm_ci_timer_un1_expired_2ms_1_975; + wire plm_fsm_ci_timer_un1_expired_2ms_0_976; + wire plm_fsm_ci_counter0_VCC_977; + wire plm_fsm_ci_counter0_un1_reg_tx_count_0_a2_5; + wire plm_fsm_ci_counter0_un1_reg_tx_count_0_a2_4; + wire plm_fsm_ci_counter0_un1_reg_rx_count_5; + wire plm_fsm_ci_counter0_un1_reg_rx_count_4; + wire plm_fsm_ci_counter0_N_38660_i_978; + wire plm_fsm_ci_counter0_N_38698_i; + wire plm_fsm_ci_counter0_reg_expired_5; + wire plm_fsm_ci_counter0_N_38699_i; + wire plm_fsm_ci_counter0_reg_oneshot_979; + wire plm_fsm_ci_counter0_N_9912_i; + wire plm_fsm_ci_counter0_N_38719_i_980; + wire plm_fsm_ci_counter0_reg_tx_expired_981; + wire plm_fsm_ci_counter0_N_38659_i_982; + wire plm_fsm_ci_counter0_N_69074_i_983; + wire plm_fsm_ci_counter0_reg_tx_count17_0_a2_0_a2_0_a2_0_a4; + wire plm_fsm_ci_counter0_un1_enable_1_0_a2_0_a2_0_a4_984; + wire plm_fsm_ci_counter1_VCC_985; + wire plm_fsm_ci_counter1_un1_reg_tx_count_0_a2_0_a4_5; + wire plm_fsm_ci_counter1_un1_reg_tx_count_0_a2_0_a4_4; + wire plm_fsm_ci_counter1_N_38661_i_986; + wire plm_fsm_ci_counter1_reg_expired_5; + wire plm_fsm_ci_counter1_N_38671_i; + wire plm_fsm_ci_counter1_N_9908_i; + wire plm_fsm_ci_counter1_reg_rx_expired_987; + wire plm_fsm_ci_counter1_un1_enable_2_i_988; + wire plm_fsm_ci_counter1_reg_tx_expired_989; + wire plm_fsm_ci_counter1_un1_enable_1_i_990; + wire plm_fsm_ci_counter1_un1_enable_1; + wire plm_fsm_ci_counter2_VCC_991; + wire plm_fsm_ci_counter2_un1_reg_tx_count_0_a2_0_a4_5; + wire plm_fsm_ci_counter2_un1_reg_tx_count_0_a2_0_a4_4; + wire plm_fsm_ci_counter2_N_38662_i_992; + wire plm_fsm_ci_counter2_reg_expired_5; + wire plm_fsm_ci_counter2_N_38721_i; + wire plm_fsm_ci_counter2_N_38697_i; + wire plm_fsm_ci_counter2_reg_rx_expired_993; + wire plm_fsm_ci_counter2_un1_enable_2_i_994; + wire plm_fsm_ci_counter2_reg_tx_expired_995; + wire plm_fsm_ci_counter2_un1_enable_1_i_996; + wire plm_fsm_ci_counter2_un1_enable_1; + wire plm_fsm_ci_counter3_VCC_997; + wire plm_fsm_ci_counter3_un1_reg_tx_count_0_a2_5; + wire plm_fsm_ci_counter3_un1_reg_tx_count_0_a2_4; + wire plm_fsm_ci_counter3_N_38663_i_998; + wire plm_fsm_ci_counter3_reg_expired_5; + wire plm_fsm_ci_counter3_N_38720_i; + wire plm_fsm_ci_counter3_N_38696_i; + wire plm_fsm_ci_counter3_reg_rx_expired_999; + wire plm_fsm_ci_counter3_un1_enable_2_i_1000; + wire plm_fsm_ci_counter3_reg_tx_expired_1001; + wire plm_fsm_ci_counter3_un1_enable_1_i_1002; + wire plm_fsm_ci_counter3_un1_enable_1; + wire plm_fsm_rl_timer_GND_1003; + wire plm_fsm_rl_timer_N_51443; + wire plm_fsm_rl_timer_N_51394; + wire plm_fsm_rl_counterx_VCC_1004; + wire plm_fsm_rl_counterx_un1_reg_rx_count_0_a2_5; + wire plm_fsm_rl_counterx_un1_reg_rx_count_0_a2_4; + wire plm_fsm_rl_counterx_un1_reg_tx_count_8; + wire plm_fsm_rl_counterx_un1_reg_tx_count_7; + wire plm_fsm_rl_counterx_un1_reg_tx_count_6; + wire plm_fsm_rl_counterx_N_38536_i_1005; + wire plm_fsm_rl_counterx_reg_expired_5; + wire plm_fsm_rl_counterx_N_9900_i; + wire plm_fsm_rl_counterx_reg_tx_expired_1006; + wire plm_fsm_rl_counterx_N_38565_i; + wire plm_fsm_rl_counterx_reg_rx_expired_1007; + wire plm_fsm_rl_counterx_N_38586_i; + wire plm_fsm_rl_counterx_un1_enable_1_i_1008; + wire plm_fsm_rl_counterx_un1_reg_rx_expired_0_a2_0_a2_0_a4; + wire plm_fsm_rl_counterx_un1_enable_1; + wire plm_fsm_rl_counter0_VCC_1009; + wire plm_fsm_rl_counter0_un1_reg_rx_count_0_a2_5; + wire plm_fsm_rl_counter0_un1_reg_rx_count_0_a2_4; + wire plm_fsm_rl_counter0_un1_reg_rx_expired_1_i; + wire plm_fsm_rl_counter0_reg_expired_5; + wire plm_fsm_rl_counter0_N_38563_i; + wire plm_fsm_rl_counter0_N_69264_i_1010; + wire plm_fsm_rl_counter1_reg_expired_5; + wire plm_fsm_rl_counter1_N_38573_i; + wire plm_fsm_rl_counter1_N_38562_i; + wire plm_fsm_rl_counter1_reg_rx_expired_1011; + wire plm_fsm_rl_counter2_reg_expired_5; + wire plm_fsm_rl_counter2_N_38572_i; + wire plm_fsm_rl_counter2_N_38561_i; + wire plm_fsm_rl_counter2_reg_rx_expired_1012; + wire plm_fsm_rl_counter3_reg_expired_5; + wire plm_fsm_rl_counter3_N_38571_i; + wire plm_fsm_rl_counter3_N_38560_i; + wire plm_fsm_rl_counter3_reg_rx_expired_1013; + wire plm_fsm_rc_timer_GND_1014; + wire plm_fsm_rc_timer_N_51441; + wire plm_fsm_rc_counter_ts1_0_VCC_1015; + wire plm_fsm_rc_counter_ts1_0_un1_reg_tx_count_0_a2_5; + wire plm_fsm_rc_counter_ts1_0_un1_reg_tx_count_0_a2_4; + wire plm_fsm_rc_counter_ts1_0_un1_reg_rx_count_0_a2_5; + wire plm_fsm_rc_counter_ts1_0_un1_reg_rx_count_0_a2_4; + wire plm_fsm_rc_counter_ts1_0_N_38438_1; + wire plm_fsm_rc_counter_ts1_0_N_37210_i_i_1016; + wire plm_fsm_rc_counter_ts1_0_N_69277_i_1017; + wire plm_fsm_rc_counter_ts1_0_N_69223_i; + wire plm_fsm_rc_counter_ts1_0_N_37299_i; + wire plm_fsm_rc_counter_ts1_0_N_69125_i; + wire plm_fsm_rc_counter_ts1_0_reg_oneshot_1018; + wire plm_fsm_rc_counter_ts1_0_N_69114_i; + wire plm_fsm_rc_counter_ts1_0_N_69101_i_1019; + wire plm_fsm_rc_counter_ts1_0_reg_tx_expired_1020; + wire plm_fsm_rc_counter_ts1_0_N_67861_i_1021; + wire plm_fsm_rc_counter_ts1_0_N_38369_i; + wire plm_fsm_rc_counter_ts1_0_N_37210_i; + wire plm_fsm_rc_counter_ts2_0_VCC_1022; + wire plm_fsm_rc_counter_ts2_0_un1_reg_tx_count_0_a2_5; + wire plm_fsm_rc_counter_ts2_0_un1_reg_tx_count_0_a2_4; + wire plm_fsm_rc_counter_ts2_0_un1_reg_rx_count_0_a2_5; + wire plm_fsm_rc_counter_ts2_0_un1_reg_rx_count_0_a2_4; + wire plm_fsm_rc_counter_ts2_0_N_37194_i_i_1023; + wire plm_fsm_rc_counter_ts2_0_N_69278_i_1024; + wire plm_fsm_rc_counter_ts2_0_N_69224_i; + wire plm_fsm_rc_counter_ts2_0_N_37196_i; + wire plm_fsm_rc_counter_ts2_0_N_69115_i; + wire plm_fsm_rc_counter_ts2_0_reg_oneshot_1025; + wire plm_fsm_rc_counter_ts2_0_N_69111_i; + wire plm_fsm_rc_counter_ts2_0_N_69096_i_1026; + wire plm_fsm_rc_counter_ts2_0_reg_tx_expired_1027; + wire plm_fsm_rc_counter_ts2_0_N_69064_i_1028; + wire plm_fsm_rc_counter_ts2_0_N_38370_i; + wire plm_fsm_rc_counter_ts2_0_N_37194_i; + wire plm_fsm_ri_timer_GND_1029; + wire plm_fsm_ri_timer_N_51437; + wire plm_fsm_ri_timer_un1_expired_2ms_0_a2_0_a4_0_1030; + wire plm_fsm_ri_timer_N_51439; + wire plm_fsm_ri_timer_N_51438; + wire plm_fsm_ri_timer_N_51436; + wire plm_fsm_ri_counter0_VCC_1031; + wire plm_fsm_ri_counter0_un1_reg_tx_count_0_a2_0_a4_5; + wire plm_fsm_ri_counter0_un1_reg_tx_count_0_a2_0_a4_4; + wire plm_fsm_ri_counter0_un1_reg_rx_count_5; + wire plm_fsm_ri_counter0_un1_reg_rx_count_4; + wire plm_fsm_ri_counter0_N_38649_i_1032; + wire plm_fsm_ri_counter0_N_38664_i_1033; + wire plm_fsm_ri_counter0_N_38694_i; + wire plm_fsm_ri_counter0_reg_expired_5; + wire plm_fsm_ri_counter0_reg_oneshot_1034; + wire plm_fsm_ri_counter0_N_9853_i; + wire plm_fsm_ri_counter0_N_38651_i_1035; + wire plm_fsm_ri_counter0_reg_tx_expired_1036; + wire plm_fsm_ri_counter0_N_38695_i; + wire plm_fsm_ri_counter0_un1_enable_0_a2_0_a2_0_a4; + wire plm_fsm_ri_counter0_N_69078_i_1037; + wire plm_fsm_ri_counter0_reg_tx_count17_0_a2_0_a2_0_a4; + wire plm_fsm_ri_counter0_un1_enable_1_0_a2_0_a2_0_a4_0; + wire plm_fsm_ri_counter1_VCC_1038; + wire plm_fsm_ri_counter1_un1_reg_tx_count_0_a2_5; + wire plm_fsm_ri_counter1_un1_reg_tx_count_0_a2_4; + wire plm_fsm_ri_counter1_un1_enable_1_i_1039; + wire plm_fsm_ri_counter1_N_38665_i_1040; + wire plm_fsm_ri_counter1_reg_expired_5; + wire plm_fsm_ri_counter1_N_38670_i; + wire plm_fsm_ri_counter1_N_9849_i; + wire plm_fsm_ri_counter1_reg_rx_expired_1041; + wire plm_fsm_ri_counter1_un1_enable_2_i_1042; + wire plm_fsm_ri_counter1_reg_tx_expired_1043; + wire plm_fsm_ri_counter1_un1_enable_1; + wire plm_fsm_ri_counter2_VCC_1044; + wire plm_fsm_ri_counter2_un1_reg_tx_count_5; + wire plm_fsm_ri_counter2_un1_reg_tx_count_4; + wire plm_fsm_ri_counter2_un1_enable_1_i_1045; + wire plm_fsm_ri_counter2_N_38666_i_1046; + wire plm_fsm_ri_counter2_reg_expired_5; + wire plm_fsm_ri_counter2_N_38669_i; + wire plm_fsm_ri_counter2_N_9847_i; + wire plm_fsm_ri_counter2_reg_rx_expired_1047; + wire plm_fsm_ri_counter2_un1_enable_2_i_1048; + wire plm_fsm_ri_counter2_reg_tx_expired_1049; + wire plm_fsm_ri_counter2_un1_enable_1; + wire plm_fsm_ri_counter3_VCC_1050; + wire plm_fsm_ri_counter3_un1_reg_tx_count_0_a2_0_a4_5; + wire plm_fsm_ri_counter3_un1_reg_tx_count_0_a2_0_a4_4; + wire plm_fsm_ri_counter3_un1_enable_1_i_1051; + wire plm_fsm_ri_counter3_N_38667_i_1052; + wire plm_fsm_ri_counter3_reg_expired_5; + wire plm_fsm_ri_counter3_N_38668_i; + wire plm_fsm_ri_counter3_reg_oneshot_1053; + wire plm_fsm_ri_counter3_N_38693_i; + wire plm_fsm_ri_counter3_reg_rx_expired_1054; + wire plm_fsm_ri_counter3_un1_enable_2_i_1055; + wire plm_fsm_ri_counter3_reg_tx_expired_1056; + wire plm_fsm_ri_counter3_un1_enable_1; + wire plm_fsm_hr_timer_GND_1057; + wire plm_fsm_hr_timer_N_51419; + wire plm_fsm_hr_timer_N_51420; + wire plm_fsm_hr_timer_un1_expired_2ms_0_a2_0_a2_0_a4_1_1058; + wire plm_fsm_hr_timer_un1_expired_2ms_0_a2_0_a2_0_a4_2_1059; + wire plm_fsm_hr_timer_un1_expired_2ms_0_a2_0_a2_0_a4_0_1060; + wire plm_fsm_xl_cls_timer_GND_1061; + wire plm_fsm_xl_cls_timer_N_51423; + wire plm_fsm_xl_cls_timer_N_12156; + wire plm_fsm_xl_cls_timer_N_12157; + wire plm_fsm_xl_cla_timer_GND_1062; + wire plm_fsm_xl_cla_timer_N_51427; + wire plm_fsm_xl_cla_timer_un1_expired_2ms_0_a2_0_a4_0_1063; + wire plm_fsm_xl_cla_timer_N_51429; + wire plm_fsm_xl_cla_timer_N_51428; + wire plm_fsm_xl_cla_timer_N_51426; + wire plm_fsm_xl_cla_timer_un1_reg_state_5_i_i_1064; + wire plm_fsm_xl_clw_timer_GND_1065; + wire plm_fsm_xl_clw_timer_N_51432; + wire plm_fsm_xl_clw_timer_un1_expired_2ms_0_a2_0_a4_0_1066; + wire plm_fsm_xl_clw_timer_N_51434; + wire plm_fsm_xl_clw_timer_N_51433; + wire plm_fsm_xl_clw_timer_N_51431; + wire com_cmmt_ppm_suspend_ok; + wire com_cmmt_aspm_suspend_req; + wire com_N_68483_i; + wire com_N_39480_i_i; + wire com_N_39480_i; + wire com_req_pkt_tx; + wire com_gnt_pkt_tx; + wire com_N_48843_i; + wire com_cmmt_tdst_rdy; + wire com_cmmt_trem_n_0_sqmuxa; + wire com_cmmt_ppm_suspend_req_n; + wire com_N_48836_i; + wire com_N_51601; + wire com_N_51600; + wire com_N_51613; + wire com_N_51612; + wire com_N_51611; + wire com_N_51610; + wire com_N_51609; + wire com_N_51608; + wire com_N_51607; + wire com_N_51606; + wire com_N_51605; + wire com_N_51604; + wire com_N_51603; + wire com_N_51602; + wire com_N_51626; + wire com_N_51625; + wire com_N_51624; + wire com_N_51623; + wire com_N_51622; + wire com_N_51621; + wire com_N_51620; + wire com_N_51619; + wire com_N_51618; + wire com_N_51617; + wire com_N_51616; + wire com_N_51615; + wire com_N_51614; + wire com_N_51628; + wire com_N_51627; + wire com_N_51633; + wire com_N_51632; + wire com_N_51631; + wire com_N_51630; + wire com_N_51629; + wire com_grant_reg_iv_0_0_0_a2; + wire com_cmmt_stat_tlp_tx_wr_ep; + wire com_cmmt_ppm_suspend_req_n_i; + wire com_cmmt_err_tlp_p_cpl; + wire com_cmmt_err_tlp_ur; + wire com_cmmt_stat_tlp_rx_cpl_abort; + wire com_cmmt_stat_tlp_rx_cpl_ep; + wire com_cmmt_stat_tlp_rx_cpl_ur; + wire com_cmmt_stat_tlp_rx_ep; + wire com_cmmt_rpm_turn_off; + wire com_cmmt_rpm_set_slot_pwr; + wire com_cmmt_rpm_as_nak_l1; + wire com_cmmt_mem32; + wire com_cmmt_mem64; + wire com_cmmt_rio; + wire com_cmmt_rsrc_rdy; + wire com_cmmt_rdst_rdy_n; + wire com_state_4_; + wire com_state_2_; + wire com_state_0_; + wire com_TLP_data_reg_29_; + wire com_TLP_data_reg_0_; + wire com_TLP_data_reg_30_; + wire com_TLP_data_reg_48_; + wire com_TLP_data_reg_46_; + wire com_TLP_data_reg_44_; + wire com_TLP_data_reg_50_; + wire com_TLP_data_reg_49_; + wire com_TLP_data_reg_14_; + wire com_TLP_data_reg_11_; + wire com_TLP_data_reg_10_; + wire com_TLP_data_reg_9_; + wire com_TLP_data_reg_8_; + wire com_TLP_data_reg_7_; + wire com_TLP_data_reg_6_; + wire com_TLP_data_reg_5_; + wire com_TLP_data_reg_4_; + wire com_TLP_data_reg_3_; + wire com_TLP_data_reg_2_; + wire com_TLP_data_reg_1_; + wire com_TLP_data_reg_27_; + wire com_TLP_data_reg_25_; + wire com_TLP_data_reg_23_; + wire com_TLP_data_reg_19_; + wire com_TLP_data_reg_18_; + wire com_TLP_data_reg_17_; + wire com_TLP_data_reg_16_; + wire com_TLP_data_reg_15_; + wire com_TLP_data_reg_31_; + wire com_tlp_data_27_; + wire com_tlp_data_29_; + wire com_tlp_data_0_; + wire com_cmml_suspend_now_n_i; + wire com_N_42763; + wire com_N_41769_i; + wire com_lnk_tfc_sent_n; + wire com_N_51187_i; + wire com_lnk_tfc_dst_rdy_n; + wire com_un1_lnk_tfc_dst_rdy_i_0_o2_i_a2; + wire com_lnk_tdst_rdy_n; + wire com_lnk_tdst_rdy_n_i; + wire com_lnk_teof; + wire com_lnk_tsof; + wire com_lnk_teof_i; + wire com_lnk_tsof_i; + wire com_reset_i_q; + wire com_cmml_suspend_ok; + wire com_cmml_suspend_now_n; + wire com_lnk_rsrc_rdy_n; + wire com_lnk_rsrc_rdy_n_i; + wire com_lnk_rsof_n; + wire com_lnk_rsof_n_i; + wire com_lnk_reof_n; + wire com_lnk_rsrc_dsc_n; + wire com_rx_tlp_range_err_n; + wire com_rx_tlp_tsn_err_crc_or_ferr; + wire com_N_38451; + wire com_cmml_rpm_ra; + wire com_cmml_bad_dllp_err_n; + wire com_lnk_tretry; + wire com_reg_tx_update_ack; + wire com_replay_timer_expire; + wire com_replay_vld; + wire com_replay_timer_expire_pre; + wire com_lnk_tfc_vc_hit; + wire com_N_3355_i; + wire com_N_3419_i_i; + wire com_N_3419_i; + wire com_N_38093_i; + wire com_reg_tx_update_retry_int; + wire com_reg_tx_update_retry_q; + wire com_llm_rx_dllp_vld; + wire com_llm_reg_rx_dllp_nak_vld; + wire com_llm_reg_rx_dllp_ack_vld; + wire com_llm_ANSeqNum_Eq_AckdSeq_5_0_a2_0_a2_0_a2_1_0; + wire com_llm_link_li2_rcv; + wire com_llm_link_li1_cpl_rcv; + wire com_llm_link_li1_np_rcv; + wire com_llm_link_li1_p_rcv; + wire com_llm_link_update_fc_rcv; + wire com_llm_N_41810_i; + wire com_llm_rx_rsrc_dsc_n; + wire com_llm_reg_dllr_in_progress; + wire com_llm_N_38740; + wire com_llm_N_30821_i; + wire com_llm_lnk_reof_n22_1; + wire com_llm_N_51406_i; + wire com_llm_reg_rx_tlp_tsn_err_0_a2_0_a2_0_a2_0_a4; + wire com_llm_trn_lnk_up_n_i; + wire com_llm_reg_rx_tlp_tsn_dup; + wire com_llm_reg_tx_dllp_dup_vld; + wire com_llm_reg_tx_dllp_ack_vld; + wire com_llm_N_38737_1_i; + wire com_llm_reg_tx_dllp_nak_vld; + wire com_llm_link_status_3_; + wire com_llm_link_status_0_; + wire com_llm_rx_dllp_range_err_n; + wire com_llm_llm_tx_top_tx_dllp_vld_pre_n; + wire com_llm_llm_tx_top_tx_dllp_vld_n; + wire com_llm_llm_tx_top_tx_dllp_accepted; + wire com_llm_llm_tx_top_tx_dllp_tx_next; + wire com_llm_llm_tx_top_tx_dllp_tx_next_pre; + wire com_llm_llm_tx_top_tx_tlp_sof_pre_n; + wire com_llm_llm_tx_top_tx_tlp_sof_n; + wire com_llm_llm_tx_top_tx_tlp_vld_l_n_i; + wire com_llm_llm_tx_top_tx_tlp_eof_n; + wire com_llm_llm_tx_top_N_41766_i; + wire com_llm_llm_tx_top_cmml_suspend_ok_4_i_i_a2_1067; + wire com_llm_llm_tx_top_reg_tx_tkomp_idle; + wire com_llm_llm_tx_top_reg_tx_pp_idle; + wire com_llm_llm_tx_top_reg_tx_djefe_idle; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_d64_sw_57_; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_d64_sw_55_; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_d64_sw_54_; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_d64_sw_53_; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_d64_sw_52_; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_d64_sw_51_; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_d64_sw_50_; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_d64_sw_49_; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_d64_sw_48_; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_d64_sw_63_; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_d64_sw_62_; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_d64_sw_61_; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_d64_sw_60_; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_bat_sof_n_1068; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_un1_tx_pipe_full_0_a2_1069; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_bat_eof_n_1070; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_N_17379_i_1071; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_reg_tx_tkomp_idle_5; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_N_30689_i; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_N_69201_i_1072; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_holy_stashed_data_1073; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_bat_rem_1074; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_N_42045_i_i_1075; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_N_42045_i; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_N_68157_i_1076; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_N_48931_i; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_N_42609; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_GND_1077; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_VCC_1078; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_N_51674; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_N_41721_i; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_N_42608; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_62_N_6; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_216_; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_61_N_6; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_231_; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_60_N_6; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_230_; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_59_N_6; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_229_; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_58_N_6; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_228_; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_57_N_6; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_227_; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_56_N_6; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_226_; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_55_N_6; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_225_; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_54_N_6; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_224_; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_53_N_6; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_223_; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_52_N_6; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_222_; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_51_N_6; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_221_; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_50_N_6; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_220_; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_49_N_6; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_219_; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_48_N_6; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_218_; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_47_N_6; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_217_; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_46_N_6; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_246_; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_45_N_6; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_245_; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_44_N_6; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_244_; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_43_N_6; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_243_; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_42_N_6; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_242_; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_41_N_6; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_241_; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_40_N_6; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_240_; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_39_N_6; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_239_; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_38_N_6; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_238_; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_37_N_6; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_237_; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_36_N_6; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_236_; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_35_N_6; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_235_; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_34_N_6; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_234_; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_33_N_6; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_233_; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_32_N_6; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_232_; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_31_N_6; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_261_; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_30_N_6; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_260_; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_29_N_6; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_259_; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_28_N_6; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_258_; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_27_N_6; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_257_; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_26_N_6; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_256_; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_25_N_6; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_255_; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_24_N_6; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_254_; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_23_N_6; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_253_; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_22_N_6; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_252_; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_21_N_6; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_251_; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_20_N_6; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_250_; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_19_N_6; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_249_; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_18_N_6; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_248_; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_17_N_6; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_247_; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_16_N_6; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_276_; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_15_N_6; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_275_; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_14_N_6; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_274_; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_13_N_6; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_273_; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_12_N_6; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_272_; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_11_N_6; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_271_; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_10_N_6; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_270_; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_9_N_6; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_269_; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_8_N_6; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_268_; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_7_N_6; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_267_; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_6_N_6; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_266_; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_5_N_6; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_265_; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_4_N_6; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_264_; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_3_N_6; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_263_; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_2_N_6; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_262_; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_1_N_6; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_279_; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_0_N_6; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_278_; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_277_; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_tsn_pipe_10_N_6; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_tsn_pipe_47_; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_tsn_pipe_9_N_6; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_tsn_pipe_46_; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_tsn_pipe_8_N_6; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_tsn_pipe_45_; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_tsn_pipe_7_N_6; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_tsn_pipe_44_; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_tsn_pipe_6_N_6; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_tsn_pipe_43_; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_tsn_pipe_5_N_6; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_tsn_pipe_42_; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_tsn_pipe_4_N_6; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_tsn_pipe_41_; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_tsn_pipe_3_N_6; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_tsn_pipe_40_; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_tsn_pipe_2_N_6; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_tsn_pipe_39_; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_tsn_pipe_1_N_6; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_tsn_pipe_38_; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_tsn_pipe_0_N_6; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_tsn_pipe_37_; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_tsn_pipe_N_6; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_tsn_pipe_36_; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_eof_n_pipe_N_6; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_d64_sw_36_; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_d64_sw_37_; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_d64_sw_38_; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_d64_sw_39_; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_2__1079; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_1__1080; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_0__1081; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_d64_sw_40_; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_d64_sw_41_; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_d64_sw_42_; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_d64_sw_43_; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_d64_sw_44_; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_d64_sw_45_; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_d64_sw_46_; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_d64_sw_47_; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_d64_sw_32_; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_d64_sw_33_; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_d64_sw_34_; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_d64_sw_35_; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_15__1082; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_14__1083; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_13__1084; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_12__1085; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_11__1086; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_10__1087; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_9__1088; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_8__1089; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_7__1090; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_6__1091; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_5__1092; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_4__1093; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_3__1094; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_bat_sof_n7; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_tsn_pipe_11__1095; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_tsn_pipe_10__1096; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_tsn_pipe_9__1097; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_tsn_pipe_8__1098; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_tsn_pipe_7__1099; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_tsn_pipe_6__1100; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_tsn_pipe_5__1101; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_tsn_pipe_4__1102; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_tsn_pipe_3__1103; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_tsn_pipe_2__1104; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_tsn_pipe_1__1105; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_tsn_pipe_0__1106; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_N_40550_i; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_N_40548_i; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_N_21250_i; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_N_21248_i; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_N_21246_i; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_N_21244_i; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_N_21242_i; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_N_21240_i; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_N_21238_i; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_N_21236_i; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_N_21234_i; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_N_21232_i; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_d_51_; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_d_50_; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_N_21230_i; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_N_21228_i; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_N_21226_i; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_N_21224_i; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_N_21222_i; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_N_21220_i; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_N_21218_i; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_N_21216_i; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_N_21214_i; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_N_21212_i; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_d_39_; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_d_38_; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_d_37_; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_d_36_; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_d_35_; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_d_34_; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_d_33_; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_d_32_; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_d_31_; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_d_30_; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_d_29_; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_d_28_; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_d_27_; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_d_26_; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_d_25_; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_d_24_; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_d_23_; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_d_22_; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_d_21_; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_d_20_; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_d_19_; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_d_18_; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_d_17_; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_d_16_; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_d_15_; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_d_14_; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_d_13_; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_d_12_; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_d_11_; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_d_10_; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_d_9_; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_d_8_; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_d_7__1107; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_d_6__1108; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_d_5__1109; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_d_4__1110; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_d_3__1111; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_d_2__1112; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_d_1__1113; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_d_0__1114; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mgt_tx_crcint; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_new_c48_1_1_1_; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_bm_1__1115; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_am_1__1116; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_new_c48_1_1_6_; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_bm_6__1117; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_am_6__1118; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_new_c48_1_1_10_; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_bm_10__1119; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_am_10__1120; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_new_c48_1_2_12_; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_bm_12__1121; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_am_12__1122; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_new_c16_1_1_13_; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_am_13__1123; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_new_c48_1_2_14_; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_new_c48_1_0_14_; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_bm_14__1124; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_new_c48_1_3_15_; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_new_c48_1_1_15_; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_bm_15__1125; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_am_15__1126; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_new_c16_1_1_16_; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_am_16__1127; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_new_c48_1_2_17_; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_bm_17__1128; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_am_17__1129; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_new_c48_1_1_18_; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_bm_18__1130; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_am_18__1131; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_new_c48_1_1_19_; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_bm_19__1132; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_am_19__1133; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_new_c48_1_2_20_; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_bm_20__1134; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_am_20__1135; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_new_c48_1_1_21_; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_bm_21__1136; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_am_21__1137; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_new_c48_1_2_27_; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_bm_27__1138; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_am_27__1139; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_new_c48_1_2_28_; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_bm_28__1140; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_am_28__1141; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_new_c48_1_1_30_; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_new_c48_1_0_30_; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_bm_30__1142; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_am_30__1143; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_new_c48_1_2_0_; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_bm_0__1144; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_am_0__1145; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_new_c48_1_1_2_; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_bm_2__1146; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_am_2__1147; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_new_c48_1_2_3_; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_bm_3__1148; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_am_3__1149; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_new_c48_1_1_4_; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_bm_4__1150; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_am_4__1151; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_new_c48_1_1_5_; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_bm_5__1152; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_am_5__1153; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_new_c32_d16_1_3_; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_new_c48_1_3_7_; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_new_c48_1_1_7_; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_bm_7__1154; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_am_7__1155; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_new_c48_1_0_9_; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_bm_9__1156; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_am_9__1157; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_new_c48_1_1_11_; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_bm_11__1158; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_am_11__1159; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_new_c48_1_3_22_; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_bm_22__1160; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_am_22__1161; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_new_c16_1_1_23_; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_new_c48_1_2_23_; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_bm_23__1162; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_am_23__1163; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_new_c48_1_3_24_; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_new_c48_1_2_24_; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_bm_24__1164; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_am_24__1165; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_new_c32_d16_1_25_; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_new_c32_d48_1_2_; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_new_c48_1_1_25_; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_bm_25__1166; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_am_25__1167; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_new_c48_1_1_26_; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_bm_26__1168; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_am_26__1169; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_new_c16_1_1_29_; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_new_c48_1_2_29_; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_bm_29__1170; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_am_29__1171; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_am_14__1172; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_new_c48_1_2_31_; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_new_c32_d16_1_8_; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_new_c48_1_3_8_; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_new_c16_1_1_8_; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_22303_i_1173; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_22304_i_1174; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_22305_i_1175; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_22306_i_1176; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_22307_i_1177; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_22308_i_1178; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_22309_i_1179; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_22310_i_1180; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_22311_i_1181; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_22312_i_1182; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_22313_i_1183; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_22314_i_1184; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_22315_i_1185; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_22335_i_1186; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_22336_i_1187; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_22337_i_1188; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_22338_i_1189; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_22339_i_1190; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_22340_i_1191; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_22341_i_1192; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_22342_i_1193; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_22343_i_1194; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_22344_i_1195; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_22345_i_1196; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_22346_i_1197; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_22347_i_1198; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_22316_i_1199; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_22317_i_1200; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_22318_i_1201; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_22319_i_1202; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_22320_i_1203; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_22321_i_1204; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crcint_qq_1205; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_6013; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_6012; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_6011; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_6010; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_6009; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_6008; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_6007; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_6006; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_6005; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_6004; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_6003; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_6002; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_6001; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_6000; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_5999; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_5998; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_5997; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_5996; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_5995; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_5994; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_5993; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_5992; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_5991; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_5990; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_5989; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_5988; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_5987; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_5986; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_5985; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_5984; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_5983; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_5982; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_5981; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_5980; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_5979; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_5978; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_5977; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_5976; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_5975; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_5974; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_5973; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_5972; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_5971; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_5970; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_5969; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_5968; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_5967; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_5966; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_new_c32_d48_1_12_; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_bm_16__1206; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_bm_1_16__1207; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_bm_13__1208; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_bm_1_13__1209; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_new_c48_1_2_13_; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_d64_c_q_31__1210; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_d64_c_q_30__1211; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_d64_c_q_29__1212; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_d64_c_q_28__1213; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_d64_c_q_27__1214; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_d64_c_q_26__1215; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_d64_c_q_25__1216; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_d64_c_q_24__1217; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_d64_c_q_23__1218; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_d64_c_q_22__1219; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_d64_c_q_21__1220; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_d64_c_q_20__1221; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_d64_c_q_19__1222; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_d64_c_q_18__1223; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_d64_c_q_17__1224; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_d64_c_q_16__1225; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_d64_c_q_15__1226; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_d64_c_q_14__1227; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_d64_c_q_13__1228; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_d64_c_q_12__1229; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_d64_c_q_11__1230; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_d64_c_q_10__1231; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_d64_c_q_9__1232; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_d64_c_q_8__1233; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_d64_c_q_7__1234; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_d64_c_q_6__1235; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_d64_c_q_4__1236; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_d64_c_q_3__1237; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_d64_c_q_1__1238; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_d64_c_q_0__1239; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_1_24__1240; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_0_20__1241; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_0_31__1242; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_23__1243; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_2_2__1244; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_2_25__1245; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_2_26__1246; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_2_26_; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_0_4__1247; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_2_29_; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_1_27__1248; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_0_13__1249; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_0_28__1250; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_2_15__1251; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_2_10__1252; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_1_6_; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_4_31__1253; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_2_30__1254; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_2_29__1255; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_29__1256; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_4_28__1257; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_3_27__1258; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_3_26__1259; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_26__1260; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_5_25__1261; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_3_24__1262; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_3_23__1263; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_5_22__1264; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_4_22__1265; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_4_21__1266; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_2_21__1267; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_4_20__1268; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_0_19__1269; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_4_18__1270; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_3_18__1271; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_4_17__1272; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_2_17__1273; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_5_16__1274; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_1_16__1275; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_6_15__1276; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_15__1277; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_2_14__1278; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_3_13__1279; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_13__1280; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_1_12__1281; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_17__1282; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_3_11__1283; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_2_11__1284; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_6_10__1285; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_5_9__1286; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_2_9__1287; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_5_8__1288; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_1_8__1289; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_4_7__1290; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_3_7__1291; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_5_6__1292; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_2_6_; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_4_5__1293; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_0_5__1294; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_3_4__1295; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_6_3__1296; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_1_3__1297; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_6_2__1298; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_3_1__1299; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_2_1__1300; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_2_1_; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_3_0__1301; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_0__1302; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_4_14__1303; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_14__1304; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c48_new_c48_1_1_0__1305; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c48_new_c48_1_1_29__1306; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c64_new_c64_1_0_25__1307; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c64_new_c64_1_2_22__1308; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c64_new_c32_d64_1_4_; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c64_new_c64_1_0_16__1309; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c64_new_c64_1_1_17__1310; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c64_new_c64_1_2_19__1311; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c64_new_c64_1_1_20__1312; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c64_new_c64_1_1_21__1313; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c64_new_c64_1_1_31__1314; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c64_new_c64_1_1_29__1315; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c64_new_c64_1_2_2__1316; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c64_new_c32_d64_1_2_; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c64_new_c64_1_1_18__1317; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c64_new_c64_1_2_0__1318; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c64_new_c64_1_2_1__1319; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c64_new_c64_1_2_3__1320; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c64_new_c64_1_2_4__1321; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c64_new_c64_1_2_5__1322; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c64_new_c64_1_1_6__1323; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c64_new_c64_1_2_7__1324; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c64_new_c32_d64_1_7_; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c64_new_c64_1_1_8__1325; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c64_new_c64_1_2_9__1326; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c64_new_c64_1_1_10__1327; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c64_new_c64_1_2_11__1328; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c64_new_c64_1_1_12__1329; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c64_new_c64_1_0_13__1330; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c64_new_c64_1_1_14__1331; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c64_new_c32_d64_1_14_; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c64_new_c32_d64_1_6_; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c64_new_c64_1_1_15__1332; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c64_new_c64_1_3_22__1333; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c64_new_c64_1_0_23__1334; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c64_new_c64_1_1_24__1335; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c64_new_c64_1_3_25__1336; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c64_new_c64_1_0_26__1337; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c64_new_c64_1_2_27__1338; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c64_new_c64_1_2_28__1339; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c64_new_c64_1_1_30__1340; + wire com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_fc_queue_empty_i; + wire com_llm_llm_tx_top_llmx08_tx_dllp_jefe_GND_1341; + wire com_llm_llm_tx_top_llmx08_tx_dllp_jefe_crc_an_vld_q_1342; + wire com_llm_llm_tx_top_llmx08_tx_dllp_jefe_N_42781_i_1343; + wire com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_expired_lbits_1344; + wire com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_expired_hbits_1345; + wire com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_expired_lbits12_NE_2_1346; + wire com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_expired_lbits12_0_1347; + wire com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_expired_hbits12_NE_2_1348; + wire com_llm_llm_tx_top_llmx08_tx_dllp_jefe_N_67829_i_1349; + wire com_llm_llm_tx_top_llmx08_tx_dllp_jefe_N_67829_1; + wire com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_expired_lbits_1_sqmuxa_i_1350; + wire com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_expired_lbits12_NE_4_1351; + wire com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_expired_lbits12_NE_1_1352; + wire com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_expired_lbits12_NE_0_1353; + wire com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_expired_hbits_1_sqmuxa_i_1354; + wire com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_expired_hbits12_NE_3_1355; + wire com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_expired_hbits12_NE_1_1356; + wire com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_expired_hbits12_NE_0_1357; + wire com_llm_llm_tx_top_llmx08_tx_dllp_jefe_N_68242_i_1358; + wire com_llm_llm_tx_top_llmx08_tx_dllp_jefe_N_68886_i_1359; + wire com_llm_llm_tx_top_llmx08_tx_dllp_jefe_reg_tx_djefe_idle_3; + wire com_llm_llm_tx_top_llmx08_tx_dllp_jefe_N_12555_i; + wire com_llm_llm_tx_top_llmx08_tx_dllp_jefe_an_next_q_5; + wire com_llm_llm_tx_top_llmx08_tx_dllp_jefe_an_next_q_or_tx_fc_valid_q_7_u_0_0_0_o4_1_1360; + wire com_llm_llm_tx_top_llmx08_tx_dllp_jefe_N_30913_i_i_i_1361; + wire com_llm_llm_tx_top_llmx08_tx_dllp_jefe_N_41722_i; + wire com_llm_llm_tx_top_llmx08_tx_dllp_jefe_N_41717_i; + wire com_llm_llm_tx_top_llmx08_tx_dllp_jefe_N_12579_i; + wire com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_dllp_tx_next_9_f0_i_0_0_0_1362; + wire com_llm_llm_tx_top_llmx08_tx_dllp_jefe_an_next_q_1363; + wire com_llm_llm_tx_top_llmx08_tx_dllp_jefe_N_67930_i_1364; + wire com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_fc_queue_empty; + wire com_llm_llm_tx_top_llmx08_tx_dllp_jefe_an_next_q_or_tx_fc_valid_q_7_u_0_0_0_1_1365; + wire com_llm_llm_tx_top_llmx08_tx_dllp_jefe_an_vld_q_1366; + wire com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_fc_valid_q_1367; + wire com_llm_llm_tx_top_llmx08_tx_dllp_jefe_pm_type_d24; + wire com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_fc_dout_31_; + wire com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_fc_data_q_31__1368; + wire com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_fc_dout_30_; + wire com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_fc_data_q_30__1369; + wire com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_fc_dout_29_; + wire com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_fc_data_q_29__1370; + wire com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_fc_dout_28_; + wire com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_fc_data_q_28__1371; + wire com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_fc_dout_21_; + wire com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_fc_data_q_21__1372; + wire com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_fc_dout_20_; + wire com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_fc_data_q_20__1373; + wire com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_fc_dout_19_; + wire com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_fc_data_q_19__1374; + wire com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_fc_dout_18_; + wire com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_fc_data_q_18__1375; + wire com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_fc_dout_17_; + wire com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_fc_data_q_17__1376; + wire com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_fc_dout_16_; + wire com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_fc_data_q_16__1377; + wire com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_fc_dout_15_; + wire com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_fc_data_q_15__1378; + wire com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_fc_dout_14_; + wire com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_fc_data_q_14__1379; + wire com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_fc_dout_11_; + wire com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_fc_data_q_11__1380; + wire com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_fc_dout_10_; + wire com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_fc_data_q_10__1381; + wire com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_fc_dout_9_; + wire com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_fc_data_q_9__1382; + wire com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_fc_dout_8_; + wire com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_fc_data_q_8__1383; + wire com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_fc_dout_7_; + wire com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_fc_data_q_7__1384; + wire com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_fc_dout_6_; + wire com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_fc_data_q_6__1385; + wire com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_fc_dout_5_; + wire com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_fc_data_q_5__1386; + wire com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_fc_dout_4_; + wire com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_fc_data_q_4__1387; + wire com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_fc_dout_3_; + wire com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_fc_data_q_3__1388; + wire com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_fc_dout_2_; + wire com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_fc_data_q_2__1389; + wire com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_fc_dout_1_; + wire com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_fc_data_q_1__1390; + wire com_llm_llm_tx_top_llmx08_tx_dllp_jefe_N_12558_i; + wire com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_fc_dout_0_; + wire com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_fc_data_q_0__1391; + wire com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_dllp_pre_31_; + wire com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_dllp_pre_30_; + wire com_llm_llm_tx_top_llmx08_tx_dllp_jefe_N_68927_i_1392; + wire com_llm_llm_tx_top_llmx08_tx_dllp_jefe_N_41003_i; + wire com_llm_llm_tx_top_llmx08_tx_dllp_jefe_N_12613_i; + wire com_llm_llm_tx_top_llmx08_tx_dllp_jefe_N_12611_i; + wire com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_dllp_pre_21_; + wire com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_dllp_pre_20_; + wire com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_dllp_pre_19_; + wire com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_dllp_pre_18_; + wire com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_dllp_pre_17_; + wire com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_dllp_pre_16_; + wire com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_dllp_pre_15_; + wire com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_dllp_pre_14_; + wire com_llm_llm_tx_top_llmx08_tx_dllp_jefe_N_41001_i; + wire com_llm_llm_tx_top_llmx08_tx_dllp_jefe_N_40999_i; + wire com_llm_llm_tx_top_llmx08_tx_dllp_jefe_N_40997_i; + wire com_llm_llm_tx_top_llmx08_tx_dllp_jefe_N_40995_i; + wire com_llm_llm_tx_top_llmx08_tx_dllp_jefe_N_40993_i; + wire com_llm_llm_tx_top_llmx08_tx_dllp_jefe_N_40991_i; + wire com_llm_llm_tx_top_llmx08_tx_dllp_jefe_N_40989_i; + wire com_llm_llm_tx_top_llmx08_tx_dllp_jefe_N_40987_i; + wire com_llm_llm_tx_top_llmx08_tx_dllp_jefe_N_40985_i; + wire com_llm_llm_tx_top_llmx08_tx_dllp_jefe_N_40983_i; + wire com_llm_llm_tx_top_llmx08_tx_dllp_jefe_N_40981_i; + wire com_llm_llm_tx_top_llmx08_tx_dllp_jefe_N_40979_i; + wire com_llm_llm_tx_top_llmx08_tx_dllp_jefe_N_41728_i_i_1393; + wire com_llm_llm_tx_top_llmx08_tx_dllp_jefe_N_41728_i; + wire com_llm_llm_tx_top_llmx08_tx_dllp_jefe_N_69205_i_1394; + wire com_llm_llm_tx_top_llmx08_tx_dllp_jefe_N_41762_i_i_1395; + wire com_llm_llm_tx_top_llmx08_tx_dllp_jefe_N_41762_i; + wire com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_latency_timer17_i_o2_0_0_o2_1396; + wire com_llm_llm_tx_top_llmx08_tx_dllp_jefe_llm32_fc_fifo_GND_1397; + wire com_llm_llm_tx_top_llmx08_tx_dllp_jefe_llm32_fc_fifo_un1_data_count_3_s_1_1398; + wire com_llm_llm_tx_top_llmx08_tx_dllp_jefe_llm32_fc_fifo_un1_data_count_3_cry_0_1399; + wire com_llm_llm_tx_top_llmx08_tx_dllp_jefe_llm32_fc_fifo_un1_data_count_3_s_2_1400; + wire com_llm_llm_tx_top_llmx08_tx_dllp_jefe_llm32_fc_fifo_un1_data_count_3_cry_1_1401; + wire com_llm_llm_tx_top_llmx08_tx_dllp_jefe_llm32_fc_fifo_un1_data_count_3_s_3_1402; + wire com_llm_llm_tx_top_llmx08_tx_dllp_jefe_llm32_fc_fifo_un1_data_count_3_cry_2_1403; + wire com_llm_llm_tx_top_llmx08_tx_dllp_jefe_llm32_fc_fifo_un1_data_count_3_axb_0_1404; + wire com_llm_llm_tx_top_llmx08_tx_dllp_jefe_llm32_fc_fifo_N_42051; + wire com_llm_llm_tx_top_llmx08_tx_dllp_jefe_llm32_fc_fifo_N_68899_i_1405; + wire com_llm_llm_tx_top_llmx08_tx_dllp_jefe_llm32_fc_fifo_N_42408_2; + wire com_llm_llm_tx_top_llmx08_tx_dllp_jefe_llm32_fc_fifo_un1_data_count_3_axb_3_1406; + wire com_llm_llm_tx_top_llmx08_tx_dllp_jefe_llm32_fc_fifo_un1_data_count_3_axb_2_1407; + wire com_llm_llm_tx_top_llmx08_tx_dllp_jefe_llm32_fc_fifo_un1_data_count_3_axb_1_1408; + wire com_llm_llm_tx_top_llmx08_tx_dllp_jefe_llm32_fc_fifo_N_12584_i; + wire com_llm_llm_tx_top_llmx08_tx_dllp_jefe_llm32_fc_fifo_un1_rd_en_4_i; + wire com_llm_llm_tx_top_llmx08_tx_dllp_jefe_llm32_fc_fifo_un1_rd_en_4_0_0_0_1_1409; + wire com_llm_llm_tx_top_llmx08_tx_packet_packer_next_arb_state_0_sqmuxa; + wire com_llm_llm_tx_top_llmx08_tx_packet_packer_N_17390; + wire com_llm_llm_tx_top_llmx08_tx_packet_packer_new_c32_1_2_15_; + wire com_llm_llm_tx_top_llmx08_tx_packet_packer_next_arb_state_i_i_0_1_32158_1410; + wire com_llm_llm_tx_top_llmx08_tx_packet_packer_N_42596; + wire com_llm_llm_tx_top_llmx08_tx_packet_packer_N_41820_i; + wire com_llm_llm_tx_top_llmx08_tx_packet_packer_N_17402; + wire com_llm_llm_tx_top_llmx08_tx_packet_packer_N_17401; + wire com_llm_llm_tx_top_llmx08_tx_packet_packer_N_17372_i; + wire com_llm_llm_tx_top_llmx08_tx_packet_packer_new_c32_1_2_7_; + wire com_llm_llm_tx_top_llmx08_tx_packet_packer_new_c32_1_1_7_; + wire com_llm_llm_tx_top_llmx08_tx_packet_packer_new_c32_1_1_6_; + wire com_llm_llm_tx_top_llmx08_tx_packet_packer_new_c32_1_2_4_; + wire com_llm_llm_tx_top_llmx08_tx_packet_packer_new_c32_1_1_2_; + wire com_llm_llm_tx_top_llmx08_tx_packet_packer_new_c32_14_; + wire com_llm_llm_tx_top_llmx08_tx_packet_packer_new_c32_11_; + wire com_llm_llm_tx_top_llmx08_tx_packet_packer_new_c32_10_; + wire com_llm_llm_tx_top_llmx08_tx_packet_packer_new_c32_8_; + wire com_llm_llm_tx_top_llmx08_tx_packet_packer_new_c32_1_2_5_; + wire com_llm_llm_tx_top_llmx08_tx_packet_packer_N_41842_i_1411; + wire com_llm_llm_tx_top_llmx08_tx_packet_packer_N_68888_i_1412; + wire com_llm_llm_tx_top_llmx08_tx_packet_packer_trans_non_aligned_1413; + wire com_llm_llm_tx_top_llmx08_tx_packet_packer_N_40545_i; + wire com_llm_llm_tx_top_llmx08_tx_packet_packer_N_40543_i; + wire com_llm_llm_tx_top_llmx08_tx_packet_packer_N_40541_i; + wire com_llm_llm_tx_top_llmx08_tx_packet_packer_N_40539_i; + wire com_llm_llm_tx_top_llmx08_tx_packet_packer_N_40537_i; + wire com_llm_llm_tx_top_llmx08_tx_packet_packer_N_40535_i; + wire com_llm_llm_tx_top_llmx08_tx_packet_packer_N_40533_i; + wire com_llm_llm_tx_top_llmx08_tx_packet_packer_N_40531_i; + wire com_llm_llm_tx_top_llmx08_tx_packet_packer_new_c32_1_i_12_; + wire com_llm_llm_tx_top_llmx08_tx_packet_packer_new_c32_1_i_13_; + wire com_llm_llm_tx_top_llmx08_tx_packet_packer_new_c32_1_i_0_; + wire com_llm_llm_tx_top_llmx08_tx_packet_packer_new_c32_1_; + wire com_llm_llm_tx_top_llmx08_tx_packet_packer_N_68930_i_1414; + wire com_llm_llm_tx_top_llmx08_tx_packet_packer_N_68931_i_1415; + wire com_llm_llm_tx_top_llmx08_tx_packet_packer_N_68932_i_1416; + wire com_llm_llm_tx_top_llmx08_tx_packet_packer_N_68933_i_1417; + wire com_llm_llm_tx_top_llmx08_tx_packet_packer_N_68934_i_1418; + wire com_llm_llm_tx_top_llmx08_tx_packet_packer_N_68935_i_1419; + wire com_llm_llm_tx_top_llmx08_tx_packet_packer_N_68936_i_1420; + wire com_llm_llm_tx_top_llmx08_tx_packet_packer_N_68937_i_1421; + wire com_llm_llm_tx_top_llmx08_tx_packet_packer_N_40388_i; + wire com_llm_llm_tx_top_llmx08_tx_packet_packer_N_40390_i; + wire com_llm_llm_tx_top_llmx08_tx_packet_packer_N_41774_i; + wire com_llm_llm_tx_top_llmx08_tx_packet_packer_N_40486_i; + wire com_llm_llm_tx_top_llmx08_tx_packet_packer_N_42298; + wire com_llm_llm_tx_top_llmx08_tx_packet_packer_N_40484_i; + wire com_llm_llm_tx_top_llmx08_tx_packet_packer_N_42296; + wire com_llm_llm_tx_top_llmx08_tx_packet_packer_N_40482_i; + wire com_llm_llm_tx_top_llmx08_tx_packet_packer_N_42294; + wire com_llm_llm_tx_top_llmx08_tx_packet_packer_N_40480_i; + wire com_llm_llm_tx_top_llmx08_tx_packet_packer_N_42292; + wire com_llm_llm_tx_top_llmx08_tx_packet_packer_N_40478_i; + wire com_llm_llm_tx_top_llmx08_tx_packet_packer_N_42290; + wire com_llm_llm_tx_top_llmx08_tx_packet_packer_N_40476_i; + wire com_llm_llm_tx_top_llmx08_tx_packet_packer_N_42288; + wire com_llm_llm_tx_top_llmx08_tx_packet_packer_N_40474_i; + wire com_llm_llm_tx_top_llmx08_tx_packet_packer_N_42286; + wire com_llm_llm_tx_top_llmx08_tx_packet_packer_N_40472_i; + wire com_llm_llm_tx_top_llmx08_tx_packet_packer_N_42283; + wire com_llm_llm_tx_top_llmx08_tx_packet_packer_N_67992_i_1422; + wire com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_0_0_55__1423; + wire com_llm_llm_tx_top_llmx08_tx_packet_packer_N_67991_i_1424; + wire com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_0_0_54__1425; + wire com_llm_llm_tx_top_llmx08_tx_packet_packer_N_67951_i_1426; + wire com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_0_0_53__1427; + wire com_llm_llm_tx_top_llmx08_tx_packet_packer_N_67990_i_1428; + wire com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_0_0_52__1429; + wire com_llm_llm_tx_top_llmx08_tx_packet_packer_N_68236_i_1430; + wire com_llm_llm_tx_top_llmx08_tx_packet_packer_N_68237_i_1431; + wire com_llm_llm_tx_top_llmx08_tx_packet_packer_N_67989_i_1432; + wire com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_0_0_49__1433; + wire com_llm_llm_tx_top_llmx08_tx_packet_packer_N_67988_i_1434; + wire com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_0_0_48__1435; + wire com_llm_llm_tx_top_llmx08_tx_packet_packer_N_68238_i_1436; + wire com_llm_llm_tx_top_llmx08_tx_packet_packer_N_68239_i_1437; + wire com_llm_llm_tx_top_llmx08_tx_packet_packer_N_67987_i_1438; + wire com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_0_0_45__1439; + wire com_llm_llm_tx_top_llmx08_tx_packet_packer_N_67986_i_1440; + wire com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_0_0_44__1441; + wire com_llm_llm_tx_top_llmx08_tx_packet_packer_N_67985_i_1442; + wire com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_0_0_43__1443; + wire com_llm_llm_tx_top_llmx08_tx_packet_packer_N_67984_i_1444; + wire com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_0_0_42__1445; + wire com_llm_llm_tx_top_llmx08_tx_packet_packer_N_67983_i_1446; + wire com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_0_0_41__1447; + wire com_llm_llm_tx_top_llmx08_tx_packet_packer_N_67982_i_1448; + wire com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_0_0_40__1449; + wire com_llm_llm_tx_top_llmx08_tx_packet_packer_N_67981_i_1450; + wire com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_0_0_39__1451; + wire com_llm_llm_tx_top_llmx08_tx_packet_packer_N_67980_i_1452; + wire com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_0_0_38__1453; + wire com_llm_llm_tx_top_llmx08_tx_packet_packer_N_68240_i_1454; + wire com_llm_llm_tx_top_llmx08_tx_packet_packer_N_68241_i_1455; + wire com_llm_llm_tx_top_llmx08_tx_packet_packer_N_43102; + wire com_llm_llm_tx_top_llmx08_tx_packet_packer_N_67979_i_1456; + wire com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_0_0_35__1457; + wire com_llm_llm_tx_top_llmx08_tx_packet_packer_N_67978_i_1458; + wire com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_0_0_34__1459; + wire com_llm_llm_tx_top_llmx08_tx_packet_packer_N_67952_i_1460; + wire com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_0_0_33__1461; + wire com_llm_llm_tx_top_llmx08_tx_packet_packer_N_67977_i_1462; + wire com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_0_0_32__1463; + wire com_llm_llm_tx_top_llmx08_tx_packet_packer_N_67976_i_1464; + wire com_llm_llm_tx_top_llmx08_tx_packet_packer_N_42210; + wire com_llm_llm_tx_top_llmx08_tx_packet_packer_N_41794; + wire com_llm_llm_tx_top_llmx08_tx_packet_packer_N_67975_i_1465; + wire com_llm_llm_tx_top_llmx08_tx_packet_packer_N_42208; + wire com_llm_llm_tx_top_llmx08_tx_packet_packer_N_41795; + wire com_llm_llm_tx_top_llmx08_tx_packet_packer_N_67974_i_1466; + wire com_llm_llm_tx_top_llmx08_tx_packet_packer_N_42206; + wire com_llm_llm_tx_top_llmx08_tx_packet_packer_N_41796; + wire com_llm_llm_tx_top_llmx08_tx_packet_packer_N_67973_i_1467; + wire com_llm_llm_tx_top_llmx08_tx_packet_packer_N_42204; + wire com_llm_llm_tx_top_llmx08_tx_packet_packer_N_41797; + wire com_llm_llm_tx_top_llmx08_tx_packet_packer_N_67972_i_1468; + wire com_llm_llm_tx_top_llmx08_tx_packet_packer_N_42202; + wire com_llm_llm_tx_top_llmx08_tx_packet_packer_N_41798; + wire com_llm_llm_tx_top_llmx08_tx_packet_packer_N_67971_i_1469; + wire com_llm_llm_tx_top_llmx08_tx_packet_packer_N_42200; + wire com_llm_llm_tx_top_llmx08_tx_packet_packer_N_41799; + wire com_llm_llm_tx_top_llmx08_tx_packet_packer_N_67970_i_1470; + wire com_llm_llm_tx_top_llmx08_tx_packet_packer_N_42198; + wire com_llm_llm_tx_top_llmx08_tx_packet_packer_N_41800; + wire com_llm_llm_tx_top_llmx08_tx_packet_packer_N_67969_i_1471; + wire com_llm_llm_tx_top_llmx08_tx_packet_packer_N_43110; + wire com_llm_llm_tx_top_llmx08_tx_packet_packer_N_43098; + wire com_llm_llm_tx_top_llmx08_tx_packet_packer_N_42196; + wire com_llm_llm_tx_top_llmx08_tx_packet_packer_N_41801; + wire com_llm_llm_tx_top_llmx08_tx_packet_packer_N_40438_i; + wire com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_i_23_32153_1472; + wire com_llm_llm_tx_top_llmx08_tx_packet_packer_N_51502; + wire com_llm_llm_tx_top_llmx08_tx_packet_packer_N_40436_i; + wire com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_i_22_32085_1473; + wire com_llm_llm_tx_top_llmx08_tx_packet_packer_N_40434_i; + wire com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_i_21_32186_1474; + wire com_llm_llm_tx_top_llmx08_tx_packet_packer_N_51500; + wire com_llm_llm_tx_top_llmx08_tx_packet_packer_N_40432_i; + wire com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_i_20_32154_1475; + wire com_llm_llm_tx_top_llmx08_tx_packet_packer_N_51499; + wire com_llm_llm_tx_top_llmx08_tx_packet_packer_N_40430_i; + wire com_llm_llm_tx_top_llmx08_tx_packet_packer_N_42179; + wire com_llm_llm_tx_top_llmx08_tx_packet_packer_N_40428_i; + wire com_llm_llm_tx_top_llmx08_tx_packet_packer_N_42176; + wire com_llm_llm_tx_top_llmx08_tx_packet_packer_N_40426_i; + wire com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_i_17_32187_1476; + wire com_llm_llm_tx_top_llmx08_tx_packet_packer_N_51496; + wire com_llm_llm_tx_top_llmx08_tx_packet_packer_N_40424_i; + wire com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_i_16_32150_1477; + wire com_llm_llm_tx_top_llmx08_tx_packet_packer_N_51495; + wire com_llm_llm_tx_top_llmx08_tx_packet_packer_N_40422_i; + wire com_llm_llm_tx_top_llmx08_tx_packet_packer_N_42167; + wire com_llm_llm_tx_top_llmx08_tx_packet_packer_N_40420_i; + wire com_llm_llm_tx_top_llmx08_tx_packet_packer_N_42164; + wire com_llm_llm_tx_top_llmx08_tx_packet_packer_N_40418_i; + wire com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_i_13_32151_1478; + wire com_llm_llm_tx_top_llmx08_tx_packet_packer_N_51492; + wire com_llm_llm_tx_top_llmx08_tx_packet_packer_N_40416_i; + wire com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_i_12_32081_1479; + wire com_llm_llm_tx_top_llmx08_tx_packet_packer_N_51491; + wire com_llm_llm_tx_top_llmx08_tx_packet_packer_N_40414_i; + wire com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_i_11_32082_1480; + wire com_llm_llm_tx_top_llmx08_tx_packet_packer_N_51490; + wire com_llm_llm_tx_top_llmx08_tx_packet_packer_N_40412_i; + wire com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_i_10_32083_1481; + wire com_llm_llm_tx_top_llmx08_tx_packet_packer_N_51489; + wire com_llm_llm_tx_top_llmx08_tx_packet_packer_N_40410_i; + wire com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_i_9_32152_1482; + wire com_llm_llm_tx_top_llmx08_tx_packet_packer_N_51488; + wire com_llm_llm_tx_top_llmx08_tx_packet_packer_N_40408_i; + wire com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_i_8_32084_1483; + wire com_llm_llm_tx_top_llmx08_tx_packet_packer_N_51487; + wire com_llm_llm_tx_top_llmx08_tx_packet_packer_N_40406_i; + wire com_llm_llm_tx_top_llmx08_tx_packet_packer_N_40404_i; + wire com_llm_llm_tx_top_llmx08_tx_packet_packer_N_40402_i; + wire com_llm_llm_tx_top_llmx08_tx_packet_packer_N_40400_i; + wire com_llm_llm_tx_top_llmx08_tx_packet_packer_N_43106; + wire com_llm_llm_tx_top_llmx08_tx_packet_packer_N_40398_i; + wire com_llm_llm_tx_top_llmx08_tx_packet_packer_N_40396_i; + wire com_llm_llm_tx_top_llmx08_tx_packet_packer_N_40394_i; + wire com_llm_llm_tx_top_llmx08_tx_packet_packer_N_40392_i; + wire com_llm_llm_tx_top_llmx08_tx_packet_packer_N_43103; + wire com_llm_llm_tx_top_llmx08_tx_packet_packer_N_41737_i; + wire com_llm_llm_tx_top_llmx08_tx_packet_packer_N_17347_i; + wire com_llm_llm_tx_top_llmx08_tx_packet_packer_next_arb_state_i_i_2_32140_1484; + wire com_llm_llm_tx_top_llmx08_tx_packet_packer_next_arb_state_i_i_2_32138_1485; + wire com_llm_llm_tx_top_llmx08_tx_packet_packer_N_17349_i; + wire com_llm_llm_tx_top_llmx08_tx_packet_packer_tx_idle_next_1486; + wire com_llm_llm_tx_top_llmx08_tx_packet_packer_next_arb_state_i_i_0_1_32161_1487; + wire com_llm_llm_tx_top_llmx08_tx_packet_packer_next_arb_state_i_i_0_1_32157_1488; + wire com_llm_llm_tx_top_llmx08_tx_packet_packer_N_42598; + wire com_llm_llm_tx_top_llmx08_tx_packet_packer_N_68078_i_1489; + wire com_llm_llm_tx_top_llmx08_tx_packet_packer_N_17399_3; + wire com_llm_llm_tx_top_llmx08_tx_packet_packer_N_51501; + wire com_llm_llm_tx_top_llmx08_tx_packet_packer_new_c32_1_1_9_; + wire com_llm_llm_tx_top_llmx08_tx_packet_packer_N_43100; + wire com_llm_llm_tx_top_llmx08_tx_packet_packer_aligned_1490; + wire com_llm_llm_tx_top_llmx08_tx_packet_packer_llm_rx_crc16_d32_new_c32_1_0_9__1491; + wire com_llm_llm_tx_top_llmx08_tx_packet_packer_llm_rx_crc16_d32_new_c32_1_1_0__1492; + wire com_llm_llm_tx_top_llmx08_tx_packet_packer_llm_rx_crc16_d32_new_c32_1_0_13__1493; + wire com_llm_llm_tx_top_llmx08_tx_packet_packer_llm_rx_crc16_d32_new_c32_1_1_8__1494; + wire com_llm_llm_tx_top_llmx08_tx_packet_packer_llm_rx_crc16_d32_new_c32_1_0_11__1495; + wire com_llm_llm_tx_top_llmx08_tx_packet_packer_llm_rx_crc16_d32_new_c32_1_1_3__1496; + wire com_llm_llm_rx_top_rx_rsrc_rdy_n; + wire com_llm_llm_rx_top_rx_tlp_ferr_n; + wire com_llm_llm_rx_top_rx_tlp_crc_err_n; + wire com_llm_llm_rx_top_rx_reof_n; + wire com_llm_llm_rx_top_rx_sof_n; + wire com_llm_llm_rx_top_rx_dllp_d_4_i_m3_0_14_; + wire com_llm_llm_rx_top_rx_dllp_d_4_i_m3_0_15_; + wire com_llm_llm_rx_top_rx_dllp_d_4_i_m3_0_21_; + wire com_llm_llm_rx_top_rx_tlp_eof_n; + wire com_llm_llm_rx_top_rx_tlp_eof_n_i; + wire com_llm_llm_rx_top_rx_tlp_sof_n; + wire com_llm_llm_rx_top_rx_tlp_sof_n_i; + wire com_llm_llm_rx_top_rx_tlp_vld_h_n; + wire com_llm_llm_rx_top_rx_tlp_vld_l_n; + wire com_llm_llm_rx_top_rx_dllp_sof_n; + wire com_llm_llm_rx_top_rx_dllp_vld_h_n; + wire com_llm_llm_rx_top_rx_dllp_eof_n; + wire com_llm_llm_rx_top_rx_tlp_nullified; + wire com_llm_llm_rx_top_rx_tferr_n_i; + wire com_llm_llm_rx_top_rx_dllp_sof_n_i; + wire com_llm_llm_rx_top_rx_data_60_; + wire com_llm_llm_rx_top_rx_data_55_; + wire com_llm_llm_rx_top_rx_data_54_; + wire com_llm_llm_rx_top_rx_data_53_; + wire com_llm_llm_rx_top_rx_data_52_; + wire com_llm_llm_rx_top_rx_data_51_; + wire com_llm_llm_rx_top_rx_data_50_; + wire com_llm_llm_rx_top_rx_data_49_; + wire com_llm_llm_rx_top_rx_data_48_; + wire com_llm_llm_rx_top_rx_data_47_; + wire com_llm_llm_rx_top_rx_data_45_; + wire com_llm_llm_rx_top_rx_data_44_; + wire com_llm_llm_rx_top_rx_data_43_; + wire com_llm_llm_rx_top_rx_data_42_; + wire com_llm_llm_rx_top_rx_data_41_; + wire com_llm_llm_rx_top_rx_data_40_; + wire com_llm_llm_rx_top_rx_data_39_; + wire com_llm_llm_rx_top_rx_data_38_; + wire com_llm_llm_rx_top_rx_data_37_; + wire com_llm_llm_rx_top_rx_data_36_; + wire com_llm_llm_rx_top_rx_data_35_; + wire com_llm_llm_rx_top_rx_data_34_; + wire com_llm_llm_rx_top_rx_data_33_; + wire com_llm_llm_rx_top_rx_data_32_; + wire com_llm_llm_rx_top_rx_data_31_; + wire com_llm_llm_rx_top_rx_data_30_; + wire com_llm_llm_rx_top_rx_data_29_; + wire com_llm_llm_rx_top_rx_data_28_; + wire com_llm_llm_rx_top_rx_data_26_; + wire com_llm_llm_rx_top_rx_data_25_; + wire com_llm_llm_rx_top_rx_data_24_; + wire com_llm_llm_rx_top_rx_data_23_; + wire com_llm_llm_rx_top_rx_data_22_; + wire com_llm_llm_rx_top_rx_data_21_; + wire com_llm_llm_rx_top_rx_data_20_; + wire com_llm_llm_rx_top_rx_data_19_; + wire com_llm_llm_rx_top_rx_data_18_; + wire com_llm_llm_rx_top_rx_data_17_; + wire com_llm_llm_rx_top_rx_data_16_; + wire com_llm_llm_rx_top_rx_data_15_; + wire com_llm_llm_rx_top_rx_data_14_; + wire com_llm_llm_rx_top_rx_data_13_; + wire com_llm_llm_rx_top_rx_data_12_; + wire com_llm_llm_rx_top_rx_data_11_; + wire com_llm_llm_rx_top_rx_data_10_; + wire com_llm_llm_rx_top_rx_data_9_; + wire com_llm_llm_rx_top_rx_data_8_; + wire com_llm_llm_rx_top_rx_data_7_; + wire com_llm_llm_rx_top_rx_data_6_; + wire com_llm_llm_rx_top_rx_data_5_; + wire com_llm_llm_rx_top_rx_data_4_; + wire com_llm_llm_rx_top_rx_data_3_; + wire com_llm_llm_rx_top_rx_data_2_; + wire com_llm_llm_rx_top_rx_data_1_; + wire com_llm_llm_rx_top_rx_data_0_; + wire com_llm_llm_rx_top_llm_rx_demux_un4_idle_on_low_n_5_1497; + wire com_llm_llm_rx_top_llm_rx_demux_un4_idle_on_low_n_4_1498; + wire com_llm_llm_rx_top_llm_rx_demux_un10_idle_a_n_5_1499; + wire com_llm_llm_rx_top_llm_rx_demux_un10_idle_a_n_4_1500; + wire com_llm_llm_rx_top_llm_rx_demux_un5_idle_a_n_5_1501; + wire com_llm_llm_rx_top_llm_rx_demux_un5_idle_a_n_4_1502; + wire com_llm_llm_rx_top_llm_rx_demux_dllp_vld_h_n_q_11_iv_i_a3_1; + wire com_llm_llm_rx_top_llm_rx_demux_N_12873_2; + wire com_llm_llm_rx_top_llm_rx_demux_un4_idle_on_high_n_5_1503; + wire com_llm_llm_rx_top_llm_rx_demux_un4_idle_on_high_n_4_1504; + wire com_llm_llm_rx_top_llm_rx_demux_dllp_vld_h_n_q_11_iv_i_a3_1505; + wire com_llm_llm_rx_top_llm_rx_demux_N_12825_i; + wire com_llm_llm_rx_top_llm_rx_demux_dllp_vld_h_n_q_11_iv_i_o3_1506; + wire com_llm_llm_rx_top_llm_rx_demux_tlp_ferr_n_q_9_u_i_a2_1507; + wire com_llm_llm_rx_top_llm_rx_demux_tlp_ferr_n_q_9_u_i_m3_0_1508; + wire com_llm_llm_rx_top_llm_rx_demux_tlp_ferr_n_qq_8_u_i_1_1509; + wire com_llm_llm_rx_top_llm_rx_demux_tlp_vld_l_n_q_13_0_o2_1510; + wire com_llm_llm_rx_top_llm_rx_demux_phy_frame_l_t_1511; + wire com_llm_llm_rx_top_llm_rx_demux_N_12821_i; + wire com_llm_llm_rx_top_llm_rx_demux_phy_frame_h_t_1512; + wire com_llm_llm_rx_top_llm_rx_demux_N_12828_i; + wire com_llm_llm_rx_top_llm_rx_demux_phy_frame_l_q_1513; + wire com_llm_llm_rx_top_llm_rx_demux_phy_frame_h_q_1514; + wire com_llm_llm_rx_top_llm_rx_demux_phy_rbad_frm_q_1515; + wire com_llm_llm_rx_top_llm_rx_demux_N_12778_i; + wire com_llm_llm_rx_top_llm_rx_demux_dllp_eof_n_q13_i_1516; + wire com_llm_llm_rx_top_llm_rx_demux_dllp_eof_n_q_1517; + wire com_llm_llm_rx_top_llm_rx_demux_tlp_align_q13; + wire com_llm_llm_rx_top_llm_rx_demux_tlp_align_q_1518; + wire com_llm_llm_rx_top_llm_rx_demux_N_69444_i_1519; + wire com_llm_llm_rx_top_llm_rx_demux_dllp_sof_n_q_0_sqmuxa; + wire com_llm_llm_rx_top_llm_rx_demux_dllp_u_1520; + wire com_llm_llm_rx_top_llm_rx_demux_tlp_unalign_q13_i_a2_1521; + wire com_llm_llm_rx_top_llm_rx_demux_tlp_unalign_q_1522; + wire com_llm_llm_rx_top_llm_rx_demux_N_67772_i_1523; + wire com_llm_llm_rx_top_llm_rx_demux_N_67819_i_1524; + wire com_llm_llm_rx_top_llm_rx_demux_N_69442_i_1525; + wire com_llm_llm_rx_top_llm_rx_demux_N_69443_i_1526; + wire com_llm_llm_rx_top_llm_rx_demux_dllp_sof_n_q26_m; + wire com_llm_llm_rx_top_llm_rx_demux_dllp_a_1527; + wire com_llm_llm_rx_top_llm_rx_demux_N_12826_i; + wire com_llm_llm_rx_top_llm_rx_demux_tlp_sof_n_q_1528; + wire com_llm_llm_rx_top_llm_rx_demux_N_12852_i_1529; + wire com_llm_llm_rx_top_llm_rx_demux_dllp_vld_h_n_q_1530; + wire com_llm_llm_rx_top_llm_rx_demux_N_67820_i_1531; + wire com_llm_llm_rx_top_llm_rx_demux_tlp_ferr_n_q_1532; + wire com_llm_llm_rx_top_llm_rx_demux_N_12796_i; + wire com_llm_llm_rx_top_llm_rx_demux_dllp_sof_n_q_1533; + wire com_llm_llm_rx_top_llm_rx_demux_N_12784_i; + wire com_llm_llm_rx_top_llm_rx_demux_tlp_ferr_h_n_q_1534; + wire com_llm_llm_rx_top_llm_rx_demux_tlp_sof_n_q_and_tlp_ip_flag_6; + wire com_llm_llm_rx_top_llm_rx_demux_N_67771_i_1535; + wire com_llm_llm_rx_top_llm_rx_demux_rx_tferr_n; + wire com_llm_llm_rx_top_llm_rx_demux_N_12838_i_1536; + wire com_llm_llm_rx_top_llm_rx_demux_long_dllp_u_q13; + wire com_llm_llm_rx_top_llm_rx_demux_long_dllp_u_q_1537; + wire com_llm_llm_rx_top_llm_rx_demux_N_12810_i; + wire com_llm_llm_rx_top_llm_rx_demux_tlp_vld_h_n_q_1538; + wire com_llm_llm_rx_top_llm_rx_demux_N_69446_i_1539; + wire com_llm_llm_rx_top_llm_rx_demux_N_12850_i_1540; + wire com_llm_llm_rx_top_llm_rx_demux_N_9766_i; + wire com_llm_llm_rx_top_llm_rx_demux_tlp_vld_l_n_q_1541; + wire com_llm_llm_rx_top_llm_rx_demux_N_12820_i_i_1542; + wire com_llm_llm_rx_top_llm_rx_demux_N_12820_i; + wire com_llm_llm_rx_top_llm_rx_demux_N_9763_i; + wire com_llm_llm_rx_top_llm_rx_demux_tlp_ip_flag_1543; + wire com_llm_llm_rx_top_llm_rx_demux_tlp_ferr_h_n_q_9_0_1_1544; + wire com_llm_llm_rx_top_llm_rx_demux_N_12822_i; + wire com_llm_llm_rx_top_llm_rx_demux_N_67762_i_1545; + wire com_llm_llm_rx_top_llm_rx_demux_tlp_sof_n_q_and_tlp_ip_flag_1546; + wire com_llm_llm_rx_top_llm_rx_demux_tlp_eof_n_q_1547; + wire com_llm_llm_rx_top_llm_rx_demux_N_67762_i_1_1548; + wire com_llm_llm_rx_top_llm_rx_demux_N_67772_1; + wire com_llm_llm_rx_top_llm_rx_dllp_crc_RX_DLLP_LOW_M1_2_cry_0_1549; + wire com_llm_llm_rx_top_llm_rx_dllp_crc_RX_DLLP_LOW_M1_2_cry_1_1550; + wire com_llm_llm_rx_top_llm_rx_dllp_crc_RX_DLLP_LOW_M1_2_cry_2_1551; + wire com_llm_llm_rx_top_llm_rx_dllp_crc_RX_DLLP_LOW_M1_2_cry_3_1552; + wire com_llm_llm_rx_top_llm_rx_dllp_crc_RX_DLLP_LOW_M1_2_cry_4_1553; + wire com_llm_llm_rx_top_llm_rx_dllp_crc_RX_DLLP_LOW_M1_2_cry_5_1554; + wire com_llm_llm_rx_top_llm_rx_dllp_crc_RX_DLLP_LOW_M1_2_cry_6_1555; + wire com_llm_llm_rx_top_llm_rx_dllp_crc_RX_DLLP_LOW_M1_2_cry_7_1556; + wire com_llm_llm_rx_top_llm_rx_dllp_crc_RX_DLLP_LOW_M1_2_cry_8_1557; + wire com_llm_llm_rx_top_llm_rx_dllp_crc_VCC_1558; + wire com_llm_llm_rx_top_llm_rx_dllp_crc_RX_DLLP_LOW_M1_2_cry_9_1559; + wire com_llm_llm_rx_top_llm_rx_dllp_crc_RX_DLLP_LOW_M1_2_cry_10_1560; + wire com_llm_llm_rx_top_llm_rx_dllp_crc_crc16_ok; + wire com_llm_llm_rx_top_llm_rx_dllp_crc_GND_1561; + wire com_llm_llm_rx_top_llm_rx_dllp_crc_str_dllp; + wire com_llm_llm_rx_top_llm_rx_dllp_crc_str_dllp_q_1562; + wire com_llm_llm_rx_top_llm_rx_dllp_crc_reg_dllp; + wire com_llm_llm_rx_top_llm_rx_dllp_crc_N_23323_i_1563; + wire com_llm_llm_rx_top_llm_rx_dllp_crc_RX_DLLP_VLD_5; + wire com_llm_llm_rx_top_llm_rx_dllp_crc_fr_straddle_q_1564; + wire com_llm_llm_rx_top_llm_rx_dllp_crc_reg_dllp_q_1565; + wire com_llm_llm_rx_top_llm_rx_dllp_crc_reg_dllp_qq_1566; + wire com_llm_llm_rx_top_llm_rx_dllp_crc_crc16_ori_4_i_m2_i_m3_0_3__1567; + wire com_llm_llm_rx_top_llm_rx_dllp_crc_crc16_ori_4_i_m2_i_m3_0_2__1568; + wire com_llm_llm_rx_top_llm_rx_dllp_crc_crc16_ori_4_i_m2_i_m3_0_1__1569; + wire com_llm_llm_rx_top_llm_rx_dllp_crc_crc16_ori_4_i_m2_i_m3_0_0__1570; + wire com_llm_llm_rx_top_llm_rx_dllp_crc_crc16_ori_4_i_m3_0_15__1571; + wire com_llm_llm_rx_top_llm_rx_dllp_crc_crc16_ori_4_i_m2_i_m3_0_14__1572; + wire com_llm_llm_rx_top_llm_rx_dllp_crc_crc16_ori_4_i_m2_i_m3_0_13__1573; + wire com_llm_llm_rx_top_llm_rx_dllp_crc_crc16_ori_4_i_m2_i_m3_0_12__1574; + wire com_llm_llm_rx_top_llm_rx_dllp_crc_crc16_ori_4_i_m3_0_11__1575; + wire com_llm_llm_rx_top_llm_rx_dllp_crc_crc16_ori_4_i_m3_0_10__1576; + wire com_llm_llm_rx_top_llm_rx_dllp_crc_crc16_ori_4_i_m3_0_9__1577; + wire com_llm_llm_rx_top_llm_rx_dllp_crc_crc16_ori_4_i_m3_0_8__1578; + wire com_llm_llm_rx_top_llm_rx_dllp_crc_crc16_ori_4_i_m3_0_7__1579; + wire com_llm_llm_rx_top_llm_rx_dllp_crc_crc16_ori_4_i_m3_0_6__1580; + wire com_llm_llm_rx_top_llm_rx_dllp_crc_crc16_ori_4_i_m3_0_5__1581; + wire com_llm_llm_rx_top_llm_rx_dllp_crc_crc16_ori_4_i_m2_i_m3_0_4__1582; + wire com_llm_llm_rx_top_llm_rx_dllp_crc_rx_dllp_d_4_i_m3_0_4__1583; + wire com_llm_llm_rx_top_llm_rx_dllp_crc_rx_dllp_d_4_i_m2_i_m3_0_3__1584; + wire com_llm_llm_rx_top_llm_rx_dllp_crc_rx_dllp_d_4_i_m3_0_2__1585; + wire com_llm_llm_rx_top_llm_rx_dllp_crc_rx_dllp_d_4_i_m3_0_1__1586; + wire com_llm_llm_rx_top_llm_rx_dllp_crc_rx_dllp_d_4_i_m3_0_0__1587; + wire com_llm_llm_rx_top_llm_rx_dllp_crc_rx_dllp_d_4_i_m3_0_11__1588; + wire com_llm_llm_rx_top_llm_rx_dllp_crc_rx_dllp_d_4_i_m3_0_10__1589; + wire com_llm_llm_rx_top_llm_rx_dllp_crc_rx_dllp_d_4_i_m3_0_9__1590; + wire com_llm_llm_rx_top_llm_rx_dllp_crc_rx_dllp_d_4_i_m3_0_8__1591; + wire com_llm_llm_rx_top_llm_rx_dllp_crc_rx_dllp_d_4_i_m2_i_m3_0_7__1592; + wire com_llm_llm_rx_top_llm_rx_dllp_crc_rx_dllp_d_4_i_m3_0_6__1593; + wire com_llm_llm_rx_top_llm_rx_dllp_crc_rx_dllp_d_4_i_m3_0_5__1594; + wire com_llm_llm_rx_top_llm_rx_dllp_crc_rx_dllp_d_6__1595; + wire com_llm_llm_rx_top_llm_rx_dllp_crc_rx_dllp_d_5__1596; + wire com_llm_llm_rx_top_llm_rx_dllp_crc_rx_dllp_d_4__1597; + wire com_llm_llm_rx_top_llm_rx_dllp_crc_rx_dllp_d_3__1598; + wire com_llm_llm_rx_top_llm_rx_dllp_crc_rx_dllp_d_2__1599; + wire com_llm_llm_rx_top_llm_rx_dllp_crc_rx_dllp_d_1__1600; + wire com_llm_llm_rx_top_llm_rx_dllp_crc_rx_dllp_d_4_i_m3_0_31__1601; + wire com_llm_llm_rx_top_llm_rx_dllp_crc_rx_dllp_d_4_i_m2_i_m3_0_30__1602; + wire com_llm_llm_rx_top_llm_rx_dllp_crc_rx_dllp_d_4_i_m2_i_m3_0_29__1603; + wire com_llm_llm_rx_top_llm_rx_dllp_crc_rx_dllp_d_4_i_m2_i_m3_0_28__1604; + wire com_llm_llm_rx_top_llm_rx_dllp_crc_rx_dllp_d_4_i_m3_0_27__1605; + wire com_llm_llm_rx_top_llm_rx_dllp_crc_rx_dllp_d_4_i_m3_0_26__1606; + wire com_llm_llm_rx_top_llm_rx_dllp_crc_rx_dllp_d_4_i_m3_0_25__1607; + wire com_llm_llm_rx_top_llm_rx_dllp_crc_rx_dllp_d_4_i_m3_0_24__1608; + wire com_llm_llm_rx_top_llm_rx_dllp_crc_rx_dllp_d_25__1609; + wire com_llm_llm_rx_top_llm_rx_dllp_crc_rx_dllp_d_24__1610; + wire com_llm_llm_rx_top_llm_rx_dllp_crc_rx_dllp_d_11__1611; + wire com_llm_llm_rx_top_llm_rx_dllp_crc_rx_dllp_d_10__1612; + wire com_llm_llm_rx_top_llm_rx_dllp_crc_rx_dllp_d_9__1613; + wire com_llm_llm_rx_top_llm_rx_dllp_crc_rx_dllp_d_8__1614; + wire com_llm_llm_rx_top_llm_rx_dllp_crc_rx_dllp_d_7__1615; + wire com_llm_llm_rx_top_llm_rx_dllp_crc_new_c32_nst_i_8_; + wire com_llm_llm_rx_top_llm_rx_dllp_crc_new_c32_1_i_0_7_; + wire com_llm_llm_rx_top_llm_rx_dllp_crc_new_c32_nst_i_6_; + wire com_llm_llm_rx_top_llm_rx_dllp_crc_new_c32_1_i_0_5_; + wire com_llm_llm_rx_top_llm_rx_dllp_crc_new_c32_1_i_0_4_; + wire com_llm_llm_rx_top_llm_rx_dllp_crc_new_c32_1_i_0_3_; + wire com_llm_llm_rx_top_llm_rx_dllp_crc_new_c32_nst_i_2_; + wire com_llm_llm_rx_top_llm_rx_dllp_crc_new_c32_nst_i_1_; + wire com_llm_llm_rx_top_llm_rx_dllp_crc_new_c32_1_i_0_0_; + wire com_llm_llm_rx_top_llm_rx_dllp_crc_rx_dllp_d_31__1616; + wire com_llm_llm_rx_top_llm_rx_dllp_crc_rx_dllp_d_30__1617; + wire com_llm_llm_rx_top_llm_rx_dllp_crc_rx_dllp_d_29__1618; + wire com_llm_llm_rx_top_llm_rx_dllp_crc_rx_dllp_d_28__1619; + wire com_llm_llm_rx_top_llm_rx_dllp_crc_rx_dllp_d_27__1620; + wire com_llm_llm_rx_top_llm_rx_dllp_crc_rx_dllp_d_26__1621; + wire com_llm_llm_rx_top_llm_rx_dllp_crc_new_c32_1_i_7_; + wire com_llm_llm_rx_top_llm_rx_dllp_crc_new_c32_st_i_6_; + wire com_llm_llm_rx_top_llm_rx_dllp_crc_new_c32_1_i_5_; + wire com_llm_llm_rx_top_llm_rx_dllp_crc_new_c32_1_i_4_; + wire com_llm_llm_rx_top_llm_rx_dllp_crc_new_c32_1_i_3_; + wire com_llm_llm_rx_top_llm_rx_dllp_crc_new_c32_st_i_2_; + wire com_llm_llm_rx_top_llm_rx_dllp_crc_new_c32_st_i_1_; + wire com_llm_llm_rx_top_llm_rx_dllp_crc_new_c32_1_i_0_; + wire com_llm_llm_rx_top_llm_rx_dllp_crc_new_c32_nst_i_15_; + wire com_llm_llm_rx_top_llm_rx_dllp_crc_new_c32_nst_i_14_; + wire com_llm_llm_rx_top_llm_rx_dllp_crc_new_c32_1_i_0_13_; + wire com_llm_llm_rx_top_llm_rx_dllp_crc_new_c32_1_i_0_12_; + wire com_llm_llm_rx_top_llm_rx_dllp_crc_new_c32_nst_i_11_; + wire com_llm_llm_rx_top_llm_rx_dllp_crc_new_c32_nst_i_10_; + wire com_llm_llm_rx_top_llm_rx_dllp_crc_new_c32_1_i_0_9_; + wire com_llm_llm_rx_top_llm_rx_dllp_crc_new_c32_st_i_15_; + wire com_llm_llm_rx_top_llm_rx_dllp_crc_new_c32_st_i_14_; + wire com_llm_llm_rx_top_llm_rx_dllp_crc_new_c32_1_i_13_; + wire com_llm_llm_rx_top_llm_rx_dllp_crc_new_c32_1_i_12_; + wire com_llm_llm_rx_top_llm_rx_dllp_crc_new_c32_st_i_11_; + wire com_llm_llm_rx_top_llm_rx_dllp_crc_new_c32_st_i_10_; + wire com_llm_llm_rx_top_llm_rx_dllp_crc_new_c32_1_i_9_; + wire com_llm_llm_rx_top_llm_rx_dllp_crc_new_c32_st_i_8_; + wire com_llm_llm_rx_top_llm_rx_dllp_crc_N_68799_i_1622; + wire com_llm_llm_rx_top_llm_rx_dllp_crc_fr_straddle_1623; + wire com_llm_llm_rx_top_llm_rx_dllp_crc_N_27; + wire com_llm_llm_rx_top_llm_rx_dllp_crc_N_3; + wire com_llm_llm_rx_top_llm_rx_dllp_crc_N_11; + wire com_llm_llm_rx_top_llm_rx_dllp_crc_N_19; + wire com_llm_llm_rx_top_llm_rx_dllp_crc_N_35; + wire com_llm_llm_rx_top_llm_rx_dllp_crc_N_43; + wire com_llm_llm_rx_top_llm_rx_dllp_crc_N_51; + wire com_llm_llm_rx_top_llm_rx_dllp_crc_N_59; + wire com_llm_llm_rx_top_llm_rx_dllp_crc_llm_rx_crc16_d32_st_new_c32_1_0_7__1624; + wire com_llm_llm_rx_top_llm_rx_dllp_crc_llm_rx_crc16_d32_st_new_c32_1_1_5__1625; + wire com_llm_llm_rx_top_llm_rx_dllp_crc_llm_rx_crc16_d32_st_new_c32_1_2_4__1626; + wire com_llm_llm_rx_top_llm_rx_dllp_crc_llm_rx_crc16_d32_st_new_c32_1_i_1_3_; + wire com_llm_llm_rx_top_llm_rx_dllp_crc_llm_rx_crc16_d32_st_new_c32_1_1_3__1627; + wire com_llm_llm_rx_top_llm_rx_dllp_crc_llm_rx_crc16_d32_st_new_c32_1_0_2__1628; + wire com_llm_llm_rx_top_llm_rx_dllp_crc_llm_rx_crc16_d32_st_new_c32_1_1_1__1629; + wire com_llm_llm_rx_top_llm_rx_dllp_crc_llm_rx_crc16_d32_st_new_c32_1_0_0__1630; + wire com_llm_llm_rx_top_llm_rx_dllp_crc_llm_rx_crc16_d32_st_new_c32_1_2_15__1631; + wire com_llm_llm_rx_top_llm_rx_dllp_crc_llm_rx_crc16_d32_st_new_c32_1_0_13__1632; + wire com_llm_llm_rx_top_llm_rx_dllp_crc_llm_rx_crc16_d32_st_new_c32_1_0_12__1633; + wire com_llm_llm_rx_top_llm_rx_dllp_crc_llm_rx_crc16_d32_st_new_c32_1_1_11__1634; + wire com_llm_llm_rx_top_llm_rx_dllp_crc_llm_rx_crc16_d32_st_new_c32_1_2_10__1635; + wire com_llm_llm_rx_top_llm_rx_dllp_crc_llm_rx_crc16_d32_st_new_c32_1_i_1_4_; + wire com_llm_llm_rx_top_llm_rx_dllp_crc_llm_rx_crc16_d32_st_new_c32_1_i_1_0_; + wire com_llm_llm_rx_top_llm_rx_dllp_crc_llm_rx_crc16_d32_st_new_c32_1_0_9__1636; + wire com_llm_llm_rx_top_llm_rx_dllp_crc_llm_rx_crc16_d32_st_new_c32_1_2_8__1637; + wire com_llm_llm_rx_top_llm_rx_dllp_crc_llm_rx_crc16_d32_nst_new_c32_1_1_8__1638; + wire com_llm_llm_rx_top_llm_rx_dllp_crc_llm_rx_crc16_d32_nst_new_c32_1_1_7__1639; + wire com_llm_llm_rx_top_llm_rx_dllp_crc_llm_rx_crc16_d32_nst_new_c32_1_1_5__1640; + wire com_llm_llm_rx_top_llm_rx_dllp_crc_llm_rx_crc16_d32_nst_new_c32_1_2_4__1641; + wire com_llm_llm_rx_top_llm_rx_dllp_crc_llm_rx_crc16_d32_nst_new_c32_1_1_3__1642; + wire com_llm_llm_rx_top_llm_rx_dllp_crc_llm_rx_crc16_d32_nst_new_c32_1_0_2__1643; + wire com_llm_llm_rx_top_llm_rx_dllp_crc_llm_rx_crc16_d32_nst_new_c32_1_1_1__1644; + wire com_llm_llm_rx_top_llm_rx_dllp_crc_llm_rx_crc16_d32_nst_new_c32_1_1_0_; + wire com_llm_llm_rx_top_llm_rx_dllp_crc_llm_rx_crc16_d32_nst_new_c32_1_2_15__1645; + wire com_llm_llm_rx_top_llm_rx_dllp_crc_llm_rx_crc16_d32_nst_new_c32_1_1_13__1646; + wire com_llm_llm_rx_top_llm_rx_dllp_crc_llm_rx_crc16_d32_nst_new_c32_1_0_12__1647; + wire com_llm_llm_rx_top_llm_rx_dllp_crc_llm_rx_crc16_d32_nst_new_c32_1_1_11__1648; + wire com_llm_llm_rx_top_llm_rx_dllp_crc_llm_rx_crc16_d32_nst_new_c32_1_1_10__1649; + wire com_llm_llm_rx_top_llm_rx_dllp_crc_llm_rx_crc16_d32_nst_new_c32_1_1_9__1650; + wire com_llm_llm_rx_top_llm_rx_dllp_decode_link_li1_cpl_rcv_3_1_0; + wire com_llm_llm_rx_top_llm_rx_dllp_decode_cmml_rpm_ra_3_0_a2_0_a2_0_a2_1; + wire com_llm_llm_rx_top_llm_rx_dllp_decode_N_41843; + wire com_llm_llm_rx_top_llm_rx_dllp_decode_N_41802_i; + wire com_llm_llm_rx_top_llm_rx_dllp_decode_N_12895_i; + wire com_llm_llm_rx_top_llm_rx_dllp_decode_link_li1_cpl_rcv_3; + wire com_llm_llm_rx_top_llm_rx_dllp_decode_link_li1_np_rcv_3; + wire com_llm_llm_rx_top_llm_rx_dllp_decode_link_li1_p_rcv_3; + wire com_llm_llm_rx_top_llm_rx_dllp_decode_N_12890_i; + wire com_llm_llm_rx_top_llm_rx_dllp_decode_cmml_rpm_ra_3; + wire com_llm_llm_rx_top_llm_rx_dllp_decode_N_67905_i_1651; + wire com_llm_llm_rx_top_llm_rx_dllp_decode_lnk_rfc_header_6_N_6; + wire com_llm_llm_rx_top_llm_rx_dllp_decode_lnk_rfc_header_5_N_6; + wire com_llm_llm_rx_top_llm_rx_dllp_decode_lnk_rfc_header_4_N_6; + wire com_llm_llm_rx_top_llm_rx_dllp_decode_lnk_rfc_header_3_N_6; + wire com_llm_llm_rx_top_llm_rx_dllp_decode_lnk_rfc_header_2_N_6; + wire com_llm_llm_rx_top_llm_rx_dllp_decode_lnk_rfc_header_1_N_6; + wire com_llm_llm_rx_top_llm_rx_dllp_decode_lnk_rfc_header_0_N_6; + wire com_llm_llm_rx_top_llm_rx_dllp_decode_GND_1652; + wire com_llm_llm_rx_top_llm_rx_dllp_decode_VCC_1653; + wire com_llm_llm_rx_top_llm_rx_dllp_decode_lnk_rfc_header_N_6; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_un6_crc32_res_ok_0_1654; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_un6_crc32_res_ok_1_1655; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_un6_crc32_res_ok_2_1656; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_un6_crc32_res_ok_3_1657; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_un6_crc32_res_ok_4_1658; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_un6_crc32_res_ok_5_1659; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_un6_crc32_res_ok_6_1660; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_VCC_1661; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_un3_crc32_res_ok_0_1662; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_un3_crc32_res_ok_1_1663; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_un3_crc32_res_ok_2_1664; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_un3_crc32_res_ok_3_1665; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_un3_crc32_res_ok_4_1666; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_un3_crc32_res_ok_5_1667; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_un3_crc32_res_ok_6_1668; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_un6_crc32_res_ok_7_1669; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_un3_crc32_res_ok_7_1670; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_RX_TLP_CRC_ERR_N_6_i_0_m2_0_1_1671; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_RX_TLP_CRC_ERR_N_6_i_0_a2_0_0_1672; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_rx_tlp_sof_nqq6_0_0_o3_1673; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_N_27378_i; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_N_27380_i; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_un1_RX_RSRC_DSC_N17_0_0_0_1674; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_N_27369_i; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_RX_TLP_CRC_ERR_N_6_i_0_0_1675; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_RX_TLP_CRC_ERR_N_6_i_0_o3_1676; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_N_27384; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_N_27375; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_RX_TLP_CRC_ERR_N_6_i_0_o3_0_1677; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_I_28_0; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_I_28; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_GND_1678; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_rx_tlp_nullified_q_i_1679; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rsrc_dsc_nd_1680; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_rx_tlp_nullified_q_1681; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_rx_tlp_vld_l_nq_1682; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_rx_tlp_vld_h_nq_1683; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_start_high_latch_qq_1684; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_frame_error_latch_q_1685; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_tlp_64; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_tlp_64_q_1686; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_unaligned_aligned_3; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_unaligned_aligned_1687; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_aligned_unaligned_3; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_aligned_unaligned_1688; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_aligned_aligned_3; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_aligned_aligned_1689; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_RX_REOF_N_5; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_dw_3; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_dw_3q_1690; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_N_13155_i; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_N_68081_i_1691; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_N_68082_i_1692; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_N_68797_i_1693; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_rx_reof_nd_1694; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m2_i_m3_0_10__1695; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m2_i_m3_0_9__1696; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m2_i_m3_0_8__1697; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m2_i_m3_0_7__1698; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m2_i_m3_0_6__1699; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m2_i_m3_0_5__1700; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m2_i_m3_0_4__1701; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m2_i_m3_0_3__1702; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m2_i_m3_0_2__1703; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m2_i_m3_0_1__1704; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m2_i_m3_0_0__1705; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m2_i_m3_0_25__1706; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m2_i_m3_0_24__1707; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m2_i_m3_0_23__1708; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m2_i_m3_0_22__1709; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m2_i_m3_0_21__1710; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m2_i_m3_0_20__1711; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m2_i_m3_0_19__1712; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m2_i_m3_0_18__1713; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m2_i_m3_0_17__1714; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m2_i_m3_0_16__1715; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m2_i_m3_0_15__1716; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m2_i_m3_0_14__1717; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m2_i_m3_0_13__1718; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m2_i_m3_0_12__1719; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m2_i_m3_0_11__1720; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m2_i_m3_0_40__1721; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m2_i_m3_0_39__1722; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m2_i_m3_0_38__1723; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m2_i_m3_0_37__1724; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m2_i_m3_0_36__1725; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m2_i_m3_0_35__1726; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m2_i_m3_0_34__1727; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m2_i_m3_0_33__1728; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m2_i_m3_0_32__1729; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m2_i_m3_0_31__1730; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m2_i_m3_0_30__1731; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m2_i_m3_0_29__1732; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m2_i_m3_0_28__1733; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m2_i_m3_0_27__1734; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m2_i_m3_0_26__1735; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m2_i_m3_0_55__1736; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m2_i_m3_0_54__1737; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m2_i_m3_0_53__1738; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m2_i_m3_0_52__1739; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m2_i_m3_0_51__1740; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m2_i_m3_0_50__1741; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m2_i_m3_0_49__1742; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m2_i_m3_0_48__1743; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m3_0_47__1744; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m2_i_m3_0_46__1745; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m3_0_45__1746; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m2_i_m3_0_44__1747; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m2_i_m3_0_43__1748; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m2_i_m3_0_42__1749; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m2_i_m3_0_41__1750; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m2_i_m3_0_63__1751; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m2_i_m3_0_62__1752; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m2_i_m3_0_61__1753; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m2_i_m3_0_60__1754; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m2_i_m3_0_59__1755; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m2_i_m3_0_58__1756; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m2_i_m3_0_57__1757; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m2_i_m3_0_56__1758; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d64_10__1759; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d64_4__1760; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d64_1__1761; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_10_; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_9_; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_8_; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_7_; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_5_; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_4_; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_1_; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_26_; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_25_; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_23_; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_21_; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_20_; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_19_; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_18_; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_17_; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_16_; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_15_; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_41_; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_40_; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_39_; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_37_; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_36_; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_33_; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_31_; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_30_; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_29_; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_28_; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_27_; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_56__1762; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_55__1763; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_54__1764; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_53__1765; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_52__1766; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_51__1767; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_50__1768; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_49__1769; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_48__1770; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_47_; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_42_; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_63__1771; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_62__1772; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_61__1773; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_60__1774; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_59__1775; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_58__1776; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_57__1777; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_tlp_nullified_latch_1778; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_frame_error_latch_1779; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_start_high_latch_3; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_end_low_latch_3; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_end_low_latch_1780; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_N_30983_i_1781; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rsof_nd_1782; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_N_27393_i_0; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_tlp_in_progress_1783; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_N_68796_i_1784; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_rx_tlp_sof_nqq_1785; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_N_68809_i_1786; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_rx_tlp_eof_nq_1787; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_rx_tlp_sof_nq_i_1788; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_rx_tlp_sof_nq_1789; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_N_99_0; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_N_99; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_N_103; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_N_102; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_un3_crc32_res_ok_7_and; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_un3_crc32_res_ok_6_and; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_un3_crc32_res_ok_5_and; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_un3_crc32_res_ok_4_and; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_un3_crc32_res_ok_3_and; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_un3_crc32_res_ok_2_and; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_un3_crc32_res_ok_1_and; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_un3_crc32_res_ok_0_and; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_un6_crc32_res_ok_7_and; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_un6_crc32_res_ok_6_and; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_un6_crc32_res_ok_5_and; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_un6_crc32_res_ok_4_and; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_un6_crc32_res_ok_3_and; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_un3_crc32_res_ok_7_and_1; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_un6_crc32_res_ok_2_and; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_un6_crc32_res_ok_2_and_1; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_un6_crc32_res_ok_1_and; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_un6_crc32_res_ok_1_and_1; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_un6_crc32_res_ok_0_and; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_N_3_0; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_N_11_0; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_N_19_0; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_N_27_0; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_N_35_0; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_N_43_0; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_N_51_0; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_N_59_0; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_N_67_0; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_N_75_0; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_N_83_0; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_N_91_0; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_N_107_0; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_N_115_0; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_N_123_0; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_N_3; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_N_7; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_N_6; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_N_11; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_N_15; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_N_14; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_N_19; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_N_23; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_N_22; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_N_27; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_N_31; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_N_30; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_N_35; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_N_39; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_N_38; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_N_43; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_N_47; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_N_46; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_N_51; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_N_55; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_N_54; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_N_59; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_N_63; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_N_62; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_N_67; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_N_71; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_N_70; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_N_75; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_N_79; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_N_78; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_N_83; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_N_87; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_N_86; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_N_91; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_N_95; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_N_94; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_N_107; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_N_111; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_N_110; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_N_115; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_N_119; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_N_118; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_N_123; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_N_127; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_N_126; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d16_new_c16_1_0_9__1790; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d16_new_c16_1_1_5__1791; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d16_new_c16_1_1_24_; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d16_new_c16_1_2_22__1792; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d16_new_c16_1_19__1793; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d16_new_c16_1_1_18__1794; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d16_new_c16_1_2_17__1795; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d16_new_c16_1_2_16__1796; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d16_new_c16_1_4__1797; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d16_new_c16_1_0_14__1798; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d16_new_c16_1_2_13__1799; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d16_new_c16_1_11__1800; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d16_new_c16_1_2_31__1801; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d16_new_c16_1_0_30__1802; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d16_new_c16_1_0_29__1803; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d16_new_c16_1_20__1804; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_2_17__1805; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_4_17__1806; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_0_24__1807; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_3_13__1808; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_0_13__1809; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_3_23__1810; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_2_1__1811; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_1_27__1812; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_2_0__1813; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_2_30__1814; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_1_21__1815; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_0_12__1816; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_24__1817; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_1_29__1818; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_4_29__1819; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_14_32043_1820; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_3__1821; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_1_23__1822; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_3_16__1823; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_2_16__1824; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_1_11__1825; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_2_3__1826; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_1_3__1827; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_22__1828; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_1_7__1829; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_3_9__1830; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_2_9__1831; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_2_2_; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_0_2__1832; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_1_8__1833; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_2_6_; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_1_6__1834; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_0_18__1835; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_6_11__1836; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_3_11__1837; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_8_9__1838; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_4_9__1839; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_5__1840; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_6_8__1841; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_4_8__1842; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_5_7__1843; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_4_7__1844; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_5_6__1845; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_6_5__1846; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_2_5__1847; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_4_4__1848; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_3_4__1849; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_6_3__1850; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_3_3__1851; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_2__1852; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_5_2__1853; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_2_2__1854; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_5_1__1855; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_4_1__1856; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_3_1__1857; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_5_0__1858; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_4_0__1859; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_3_0__1860; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_2_26__1861; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_5_25__1862; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_3_25__1863; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_6_24__1864; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_5_24__1865; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_4_24__1866; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_6_23__1867; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_5_23__1868; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_8_22__1869; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_4_22__1870; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_3_22__1871; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_18__1872; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_3_21__1873; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_2_20__1874; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_5_19__1875; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_2_19__1876; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_1_19__1877; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_3_18__1878; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_6_17__1879; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_5_17__1880; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_6_16__1881; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_4_14__1882; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_3_14__1883; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_6_13__1884; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_5_13__1885; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_12__1886; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_3_12__1887; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_2_12__1888; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_2_15_; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_2_31__1889; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_3_30__1890; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_6__1891; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_6_29__1892; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_5_29__1893; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_6_28__1894; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_4_27__1895; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_3_27__1896; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_1_10__1897; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_4_15__1898; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_15__1899; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_5_28__1900; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_4_20__1901; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_3_26__1902; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_26__1903; + wire com_llm_llm_rx_top_llm_rx_tlp_sm_VCC_1904; + wire com_llm_llm_rx_top_llm_rx_tlp_sm_tlp_diff_tsn_cry_0_1905; + wire com_llm_llm_rx_top_llm_rx_tlp_sm_tlp_diff_tsn_cry_1_1906; + wire com_llm_llm_rx_top_llm_rx_tlp_sm_tlp_diff_tsn_cry_2_1907; + wire com_llm_llm_rx_top_llm_rx_tlp_sm_tlp_diff_tsn_cry_3_1908; + wire com_llm_llm_rx_top_llm_rx_tlp_sm_tlp_diff_tsn_cry_4_1909; + wire com_llm_llm_rx_top_llm_rx_tlp_sm_tlp_diff_tsn_cry_5_1910; + wire com_llm_llm_rx_top_llm_rx_tlp_sm_tlp_diff_tsn_cry_6_1911; + wire com_llm_llm_rx_top_llm_rx_tlp_sm_tlp_diff_tsn_cry_7_1912; + wire com_llm_llm_rx_top_llm_rx_tlp_sm_tlp_diff_tsn_cry_8_1913; + wire com_llm_llm_rx_top_llm_rx_tlp_sm_tlp_diff_tsn_cry_9_1914; + wire com_llm_llm_rx_top_llm_rx_tlp_sm_tlp_diff_tsn_cry_10_1915; + wire com_llm_llm_rx_top_llm_rx_tlp_sm_tlp_diff_tsn_axb_11_1916; + wire com_llm_llm_rx_top_llm_rx_tlp_sm_N_30815_i; + wire com_llm_llm_rx_top_llm_rx_tlp_sm_N_30970; + wire com_llm_llm_rx_top_llm_rx_tlp_sm_rx_tlp_tsn_err_crc_or_ferr_3_i_0_1_1917; + wire com_llm_llm_rx_top_llm_rx_tlp_sm_N_30967; + wire com_llm_llm_rx_top_llm_rx_tlp_sm_N_30896; + wire com_llm_llm_rx_top_llm_rx_tlp_sm_tsn_eq; + wire com_llm_llm_rx_top_llm_rx_tlp_sm_GND_1918; + wire com_llm_llm_rx_top_llm_rx_tlp_sm_reg_rx_tlp_tsn_err_lrx_3; + wire com_llm_llm_rx_top_llm_rx_tlp_sm_reg_rx_tlp_tsn_err_lrx_1919; + wire com_llm_llm_rx_top_llm_rx_tlp_sm_link_up_1920; + wire com_llm_llm_rx_top_llm_rx_tlp_sm_N_13392_i; + wire com_llm_llm_rx_top_llm_rx_tlp_sm_N_13390_i; + wire com_llm_llm_rx_top_llm_rx_tlp_sm_reg_rx_tlp_tsn_err_lrfc_1921; + wire com_llm_llm_rx_top_llm_rx_tlp_sm_N_30979_i_1922; + wire com_llm_llm_rx_top_llm_rx_tlp_sm_tlp_ip_q18_i_1923; + wire com_llm_llm_rx_top_llm_rx_tlp_sm_reg_rx_tlp_tsn_err_t_1924; + wire com_llm_llm_rx_top_llm_rx_tlp_sm_N_67882_i_1925; + wire com_llm_llm_rx_top_llm_rx_tlp_sm_lnk_reof_n22_i_1926; + wire com_llm_llm_rx_top_llm_rx_tlp_sm_N_67869_i_1927; + wire com_llm_llm_rx_top_llm_rx_tlp_sm_reg_rx_tlp_tsn_dup_3; + wire com_llm_llm_rx_top_llm_rx_tlp_sm_N_67870_i_1928; + wire com_llm_llm_rx_top_llm_rx_tlp_sm_tlp_range_error17; + wire com_llm_llm_rx_top_llm_rx_tlp_sm_tlp_range_error_1929; + wire com_llm_llm_rx_top_llm_rx_tlp_sm_N_36496_i_1930; + wire com_llm_llm_rx_top_llm_rx_tlp_sm_tlp_ip_q18; + wire com_llm_llm_rx_top_llm_rx_tlp_sm_tlp_ip_q_1931; + wire com_llm_llm_rx_top_llm_rx_tlp_sm_N_27; + wire com_llm_llm_rx_top_llm_rx_tlp_sm_tlp_diff_tsn_axb_10_1932; + wire com_llm_llm_rx_top_llm_rx_tlp_sm_tlp_diff_tsn_axb_9_1933; + wire com_llm_llm_rx_top_llm_rx_tlp_sm_tlp_diff_tsn_axb_8_1934; + wire com_llm_llm_rx_top_llm_rx_tlp_sm_tlp_diff_tsn_axb_7_1935; + wire com_llm_llm_rx_top_llm_rx_tlp_sm_tlp_diff_tsn_axb_6_1936; + wire com_llm_llm_rx_top_llm_rx_tlp_sm_tlp_diff_tsn_axb_5_1937; + wire com_llm_llm_rx_top_llm_rx_tlp_sm_tlp_diff_tsn_axb_4_1938; + wire com_llm_llm_rx_top_llm_rx_tlp_sm_tlp_diff_tsn_axb_3_1939; + wire com_llm_llm_rx_top_llm_rx_tlp_sm_tlp_diff_tsn_axb_2_1940; + wire com_llm_llm_rx_top_llm_rx_tlp_sm_tlp_diff_tsn_axb_1_1941; + wire com_llm_llm_rx_top_llm_rx_tlp_sm_tlp_diff_tsn_axb_0_1942; + wire com_llm_llm_rx_top_llm_rx_tlp_sm_N_3; + wire com_llm_llm_rx_top_llm_rx_tlp_sm_N_11; + wire com_llm_llm_rx_top_llm_rx_tlp_sm_N_19; + wire com_llm_llm_rx_top_llm_rx_tlp_sm_N_35; + wire com_llm_llm_rx_top_llm_rx_tlp_sm_N_43; + wire com_llm_llm_common_N_3355_i_i; + wire com_llm_llm_common_val_1_7_; + wire com_llm_llm_common_val_3_0_; + wire com_llm_llm_common_val_1_0_; + wire com_llm_llm_common_val_1_2_; + wire com_llm_llm_common_val_3_4_; + wire com_llm_llm_common_reg_replay_to_val_3_i_m2_i_m3_i_m3_0_0__1943; + wire com_llm_llm_common_reg_ack_to_val_3_0_i_m2_i_m3_i_m3_0_0__1944; + wire com_llm_llm_common_reg_replay_to_val_3_i_m2_i_m3_i_m3_8__1945; + wire com_llm_llm_common_reg_replay_to_val_3_i_m2_i_m3_i_m3_0_7__1946; + wire com_llm_llm_common_reg_replay_to_val_3_i_m2_i_m3_i_m3_0_6__1947; + wire com_llm_llm_common_reg_replay_to_val_3_i_m2_i_m3_i_m3_5__1948; + wire com_llm_llm_common_N_69352_i_1949; + wire com_llm_llm_common_reg_replay_to_val_3_i_m2_i_m3_i_m3_0_3__1950; + wire com_llm_llm_common_reg_replay_to_val_3_i_m2_i_m3_i_m3_0_2__1951; + wire com_llm_llm_common_reg_replay_to_val_3_i_m2_i_m3_i_m3_1__1952; + wire com_llm_llm_common_reg_ack_to_val_3_12_; + wire com_llm_llm_common_N_69357_i_1953; + wire com_llm_llm_common_reg_ack_to_val_3_8_; + wire com_llm_llm_common_N_69359_i_1954; + wire com_llm_llm_common_reg_ack_to_val_3_0_i_m2_i_m3_i_m3_0_6__1955; + wire com_llm_llm_common_reg_ack_to_val_3_0_i_m2_i_m3_i_m3_0_5__1956; + wire com_llm_llm_common_reg_ack_to_val_3_0_i_m2_i_m3_i_m3_0_4__1957; + wire com_llm_llm_common_reg_ack_to_val_3_0_i_m2_i_m3_i_m3_0_3__1958; + wire com_llm_llm_common_N_69353_i_1959; + wire com_llm_llm_common_llm_link_sm_llm_link_main_sm_link_fcnp_rcvq; + wire com_llm_llm_common_llm_link_sm_llm_link_main_sm_link_fccpl_rcvq; + wire com_llm_llm_common_llm_link_sm_llm_link_main_sm_N_38455; + wire com_llm_llm_common_llm_link_sm_llm_link_main_sm_link_fcp_rcvq; + wire com_llm_llm_common_llm_link_sm_llm_link_main_sm_N_50015_1_0; + wire com_llm_llm_common_llm_link_sm_llm_link_main_sm_N_43066; + wire com_llm_llm_common_llm_link_sm_llm_link_main_sm_N_13559_i; + wire com_llm_llm_common_llm_link_sm_llm_link_main_sm_N_13964_i; + wire com_llm_llm_common_llm_link_sm_llm_link_main_sm_N_40553_i; + wire com_llm_llm_common_llm_link_sm_llm_link_main_sm_N_18596_i; + wire com_llm_llm_common_llm_link_sm_llm_link_main_sm_N_69354_i_1960; + wire com_llm_llm_common_llm_link_sm_llm_link_main_sm_sticky0_q5_i_1961; + wire com_llm_llm_common_llm_link_sm_llm_link_main_sm_sticky0_qc_1962; + wire com_llm_llm_common_llm_link_sm_llm_link_main_sm_sticky1_q5_i_1963; + wire com_llm_llm_common_llm_link_sm_llm_link_main_sm_sticky1_qc_1964; + wire com_llm_llm_common_llm_link_sm_llm_link_main_sm_sticky2_q5_i_1965; + wire com_llm_llm_common_llm_link_sm_llm_link_main_sm_sticky2_qc_1966; + wire com_llm_llm_common_llm_common_reg_replay_timeout_flag; + wire com_llm_llm_common_llm_common_reg_ack_pending; + wire com_llm_llm_common_llm_common_reg_nak_pending; + wire com_llm_llm_common_llm_common_reg_un3_ttrans_st_hiwater_cry_0_1967; + wire com_llm_llm_common_llm_common_reg_un3_ttrans_st_hiwater_cry_1_1968; + wire com_llm_llm_common_llm_common_reg_un3_ttrans_st_hiwater_cry_2_1969; + wire com_llm_llm_common_llm_common_reg_un3_ttrans_st_hiwater_cry_3_1970; + wire com_llm_llm_common_llm_common_reg_un3_ttrans_st_hiwater_cry_4_1971; + wire com_llm_llm_common_llm_common_reg_un3_ttrans_st_hiwater_cry_5_1972; + wire com_llm_llm_common_llm_common_reg_un3_ttrans_st_hiwater_cry_6_1973; + wire com_llm_llm_common_llm_common_reg_un3_ttrans_st_hiwater_cry_7_1974; + wire com_llm_llm_common_llm_common_reg_un3_ttrans_st_hiwater_cry_8_1975; + wire com_llm_llm_common_llm_common_reg_un3_ttrans_st_hiwater_cry_9_1976; + wire com_llm_llm_common_llm_common_reg_un3_ttrans_st_hiwater_cry_10_1977; + wire com_llm_llm_common_llm_common_reg_VCC_1978; + wire com_llm_llm_common_llm_common_reg_un3_tmp_result_cry_0_1979; + wire com_llm_llm_common_llm_common_reg_un3_tmp_result_cry_1_1980; + wire com_llm_llm_common_llm_common_reg_un3_tmp_result_cry_2_1981; + wire com_llm_llm_common_llm_common_reg_un3_tmp_result_cry_3_1982; + wire com_llm_llm_common_llm_common_reg_un3_tmp_result_cry_4_1983; + wire com_llm_llm_common_llm_common_reg_un3_tmp_result_cry_5_1984; + wire com_llm_llm_common_llm_common_reg_un3_tmp_result_cry_6_1985; + wire com_llm_llm_common_llm_common_reg_un3_tmp_result_cry_7_1986; + wire com_llm_llm_common_llm_common_reg_un3_tmp_result_cry_8_1987; + wire com_llm_llm_common_llm_common_reg_un3_tmp_result_cry_9_1988; + wire com_llm_llm_common_llm_common_reg_un3_tmp_result_cry_10_1989; + wire com_llm_llm_common_llm_common_reg_reg_tx_next_tsn_4_cry_0_1990; + wire com_llm_llm_common_llm_common_reg_reg_tx_next_tsn_4_cry_1_1991; + wire com_llm_llm_common_llm_common_reg_reg_tx_next_tsn_4_cry_2_1992; + wire com_llm_llm_common_llm_common_reg_reg_tx_next_tsn_4_cry_3_1993; + wire com_llm_llm_common_llm_common_reg_reg_tx_next_tsn_4_cry_4_1994; + wire com_llm_llm_common_llm_common_reg_reg_tx_next_tsn_4_cry_5_1995; + wire com_llm_llm_common_llm_common_reg_reg_tx_next_tsn_4_cry_6_1996; + wire com_llm_llm_common_llm_common_reg_reg_tx_next_tsn_4_cry_7_1997; + wire com_llm_llm_common_llm_common_reg_reg_tx_next_tsn_4_cry_8_1998; + wire com_llm_llm_common_llm_common_reg_reg_tx_next_tsn_4_cry_9_1999; + wire com_llm_llm_common_llm_common_reg_reg_tx_next_tsn_4_cry_10_2000; + wire com_llm_llm_common_llm_common_reg_lnk_sys_reset_n_0_a2_0_a2_0_a2_2001; + wire com_llm_llm_common_llm_common_reg_N_38195_i; + wire com_llm_llm_common_llm_common_reg_un1_reg_tx_dllp_ack_clr_1_i_0_1_2002; + wire com_llm_llm_common_llm_common_reg_N_13526_i; + wire com_llm_llm_common_llm_common_reg_N_13528_i; + wire com_llm_llm_common_llm_common_reg_un3_ttrans_st_hiwater_axb_11_2003; + wire com_llm_llm_common_llm_common_reg_un3_tmp_result_axb_11_2004; + wire com_llm_llm_common_llm_common_reg_N_41809_i; + wire com_llm_llm_common_llm_common_reg_reg_tx_next_tsn_4_axb_11_2005; + wire com_llm_llm_common_llm_common_reg_reg_tx_next_tsn_4_axb_10_2006; + wire com_llm_llm_common_llm_common_reg_reg_tx_next_tsn_4_axb_9_2007; + wire com_llm_llm_common_llm_common_reg_reg_tx_next_tsn_4_axb_8_2008; + wire com_llm_llm_common_llm_common_reg_reg_tx_next_tsn_4_axb_7_2009; + wire com_llm_llm_common_llm_common_reg_reg_tx_next_tsn_4_axb_6_2010; + wire com_llm_llm_common_llm_common_reg_reg_tx_next_tsn_4_axb_5_2011; + wire com_llm_llm_common_llm_common_reg_reg_tx_next_tsn_4_axb_4_2012; + wire com_llm_llm_common_llm_common_reg_reg_tx_next_tsn_4_axb_3_2013; + wire com_llm_llm_common_llm_common_reg_reg_tx_next_tsn_4_axb_2_2014; + wire com_llm_llm_common_llm_common_reg_reg_tx_next_tsn_4_axb_1_2015; + wire com_llm_llm_common_llm_common_reg_N_42823_i_2016; + wire com_llm_llm_common_llm_common_reg_N_42824_i_2017; + wire com_llm_llm_common_llm_common_reg_N_42825_i_2018; + wire com_llm_llm_common_llm_common_reg_N_42826_i_2019; + wire com_llm_llm_common_llm_common_reg_N_42827_i_2020; + wire com_llm_llm_common_llm_common_reg_N_42828_i_2021; + wire com_llm_llm_common_llm_common_reg_N_42829_i_2022; + wire com_llm_llm_common_llm_common_reg_N_42830_i_2023; + wire com_llm_llm_common_llm_common_reg_N_42831_i_2024; + wire com_llm_llm_common_llm_common_reg_N_42832_i_2025; + wire com_llm_llm_common_llm_common_reg_N_42833_i_2026; + wire com_llm_llm_common_llm_common_reg_N_42834_i_2027; + wire com_llm_llm_common_llm_common_reg_N_30966_1; + wire com_llm_llm_common_llm_common_reg_N_38751; + wire com_llm_llm_common_llm_common_reg_ANSeqNum_Eq_AckdSeq_wire; + wire com_llm_llm_common_llm_common_reg_GND_2028; + wire com_llm_llm_common_llm_common_reg_NxtTxTSN_ANSeqNum_wire_2029; + wire com_llm_llm_common_llm_common_reg_ANSeqNum_AckdSeq_wire_2030; + wire com_llm_llm_common_llm_common_reg_reg_tx_update_clr_q_2031; + wire com_llm_llm_common_llm_common_reg_reg_rx_dllp_nak_vld_q_2032; + wire com_llm_llm_common_llm_common_reg_reg_rx_dllp_ack_vld_q_2033; + wire com_llm_llm_common_llm_common_reg_next_eq_mark_q_3; + wire com_llm_llm_common_llm_common_reg_next_eq_mark_q_2034; + wire com_llm_llm_common_llm_common_reg_curr_eq_mark_q_3; + wire com_llm_llm_common_llm_common_reg_curr_eq_mark_q_2035; + wire com_llm_llm_common_llm_common_reg_rx_tsn_eq_sent_tsn_3; + wire com_llm_llm_common_llm_common_reg_rx_tsn_eq_sent_tsn_2036; + wire com_llm_llm_common_llm_common_reg_un3_ttrans_st_hiwater_s_11_2037; + wire com_llm_llm_common_llm_common_reg_un3_tmp_result_s_11_2038; + wire com_llm_llm_common_llm_common_reg_N_67867_i_2039; + wire com_llm_llm_common_llm_common_reg_ANSeqNum_Eq_AckdSeq_5; + wire com_llm_llm_common_llm_common_reg_ANSeqNum_Eq_AckdSeq_2040; + wire com_llm_llm_common_llm_common_reg_N_69070_i_2041; + wire com_llm_llm_common_llm_common_reg_N_67883_i_2042; + wire com_llm_llm_common_llm_common_reg_reg_dllr_in_progress17; + wire com_llm_llm_common_llm_common_reg_N_42799_i_2043; + wire com_llm_llm_common_llm_common_reg_N_42800_i_2044; + wire com_llm_llm_common_llm_common_reg_N_42801_i_2045; + wire com_llm_llm_common_llm_common_reg_N_42802_i_2046; + wire com_llm_llm_common_llm_common_reg_N_42803_i_2047; + wire com_llm_llm_common_llm_common_reg_N_42804_i_2048; + wire com_llm_llm_common_llm_common_reg_N_42805_i_2049; + wire com_llm_llm_common_llm_common_reg_N_42806_i_2050; + wire com_llm_llm_common_llm_common_reg_N_42807_i_2051; + wire com_llm_llm_common_llm_common_reg_N_42808_i_2052; + wire com_llm_llm_common_llm_common_reg_N_42809_i_2053; + wire com_llm_llm_common_llm_common_reg_N_69071_i; + wire com_llm_llm_common_llm_common_reg_N_42810_i_2054; + wire com_llm_llm_common_llm_common_reg_N_69229_i_2055; + wire com_llm_llm_common_llm_common_reg_reg_tx_dllp_ack_vld18; + wire com_llm_llm_common_llm_common_reg_N_69044_i_2056; + wire com_llm_llm_common_llm_common_reg_N_12552_i; + wire com_llm_llm_common_llm_common_reg_N_67865_i_2057; + wire com_llm_llm_common_llm_common_reg_replay_ip21; + wire com_llm_llm_common_llm_common_reg_replay_ip_2058; + wire com_llm_llm_common_llm_common_reg_N_42811_i_2059; + wire com_llm_llm_common_llm_common_reg_N_42812_i_2060; + wire com_llm_llm_common_llm_common_reg_N_42813_i_2061; + wire com_llm_llm_common_llm_common_reg_N_42814_i_2062; + wire com_llm_llm_common_llm_common_reg_N_42815_i_2063; + wire com_llm_llm_common_llm_common_reg_N_42816_i_2064; + wire com_llm_llm_common_llm_common_reg_N_42817_i_2065; + wire com_llm_llm_common_llm_common_reg_N_42818_i_2066; + wire com_llm_llm_common_llm_common_reg_N_42819_i_2067; + wire com_llm_llm_common_llm_common_reg_N_42820_i_2068; + wire com_llm_llm_common_llm_common_reg_N_42821_i_2069; + wire com_llm_llm_common_llm_common_reg_N_69063_i_2070; + wire com_llm_llm_common_llm_common_reg_N_42822_i_2071; + wire com_llm_llm_common_llm_common_reg_N_42835_i_2072; + wire com_llm_llm_common_llm_common_reg_N_42836_i_2073; + wire com_llm_llm_common_llm_common_reg_N_42837_i_2074; + wire com_llm_llm_common_llm_common_reg_N_42838_i_2075; + wire com_llm_llm_common_llm_common_reg_N_42839_i_2076; + wire com_llm_llm_common_llm_common_reg_N_42840_i_2077; + wire com_llm_llm_common_llm_common_reg_N_42841_i_2078; + wire com_llm_llm_common_llm_common_reg_N_42842_i_2079; + wire com_llm_llm_common_llm_common_reg_N_42843_i_2080; + wire com_llm_llm_common_llm_common_reg_N_42844_i_2081; + wire com_llm_llm_common_llm_common_reg_N_42845_i_2082; + wire com_llm_llm_common_llm_common_reg_N_69244_i_2083; + wire com_llm_llm_common_llm_common_reg_N_42846_i_2084; + wire com_llm_llm_common_llm_common_reg_N_27_2; + wire com_llm_llm_common_llm_common_reg_N_27_1; + wire com_llm_llm_common_llm_common_reg_N_27_0; + wire com_llm_llm_common_llm_common_reg_N_27; + wire com_llm_llm_common_llm_common_reg_reg_tx_next_tsn_4_axb_0_2085; + wire com_llm_llm_common_llm_common_reg_un3_tmp_result_axb_10_2086; + wire com_llm_llm_common_llm_common_reg_un3_tmp_result_axb_9_2087; + wire com_llm_llm_common_llm_common_reg_un3_tmp_result_axb_8_2088; + wire com_llm_llm_common_llm_common_reg_un3_tmp_result_axb_7_2089; + wire com_llm_llm_common_llm_common_reg_un3_tmp_result_axb_6_2090; + wire com_llm_llm_common_llm_common_reg_un3_tmp_result_axb_5_2091; + wire com_llm_llm_common_llm_common_reg_un3_tmp_result_axb_4_2092; + wire com_llm_llm_common_llm_common_reg_un3_tmp_result_axb_3_2093; + wire com_llm_llm_common_llm_common_reg_un3_tmp_result_axb_2_2094; + wire com_llm_llm_common_llm_common_reg_un3_tmp_result_axb_1_2095; + wire com_llm_llm_common_llm_common_reg_un3_tmp_result_axb_0_2096; + wire com_llm_llm_common_llm_common_reg_un3_ttrans_st_hiwater_axb_10_2097; + wire com_llm_llm_common_llm_common_reg_un3_ttrans_st_hiwater_axb_9_2098; + wire com_llm_llm_common_llm_common_reg_un3_ttrans_st_hiwater_axb_8_2099; + wire com_llm_llm_common_llm_common_reg_un3_ttrans_st_hiwater_axb_7_2100; + wire com_llm_llm_common_llm_common_reg_un3_ttrans_st_hiwater_axb_6_2101; + wire com_llm_llm_common_llm_common_reg_un3_ttrans_st_hiwater_axb_5_2102; + wire com_llm_llm_common_llm_common_reg_un3_ttrans_st_hiwater_axb_4_2103; + wire com_llm_llm_common_llm_common_reg_un3_ttrans_st_hiwater_axb_3_2104; + wire com_llm_llm_common_llm_common_reg_un3_ttrans_st_hiwater_axb_2_2105; + wire com_llm_llm_common_llm_common_reg_un3_ttrans_st_hiwater_axb_1_2106; + wire com_llm_llm_common_llm_common_reg_un3_ttrans_st_hiwater_axb_0_2107; + wire com_llm_llm_common_llm_common_reg_N_3_2; + wire com_llm_llm_common_llm_common_reg_N_11_2; + wire com_llm_llm_common_llm_common_reg_N_19_2; + wire com_llm_llm_common_llm_common_reg_N_35_2; + wire com_llm_llm_common_llm_common_reg_N_43_2; + wire com_llm_llm_common_llm_common_reg_N_3_1; + wire com_llm_llm_common_llm_common_reg_N_11_1; + wire com_llm_llm_common_llm_common_reg_N_19_1; + wire com_llm_llm_common_llm_common_reg_N_35_1; + wire com_llm_llm_common_llm_common_reg_N_43_1; + wire com_llm_llm_common_llm_common_reg_N_3_0; + wire com_llm_llm_common_llm_common_reg_N_11_0; + wire com_llm_llm_common_llm_common_reg_N_19_0; + wire com_llm_llm_common_llm_common_reg_N_35_0; + wire com_llm_llm_common_llm_common_reg_N_43_0; + wire com_llm_llm_common_llm_common_reg_N_3; + wire com_llm_llm_common_llm_common_reg_N_11; + wire com_llm_llm_common_llm_common_reg_N_19; + wire com_llm_llm_common_llm_common_reg_N_35; + wire com_llm_llm_common_llm_common_reg_N_43; + wire com_llm_llm_common_llm_common_reg_compare_1_VCC_2108; + wire com_llm_llm_common_llm_common_reg_compare_1_result_cry_0_2109; + wire com_llm_llm_common_llm_common_reg_compare_1_result_cry_1_2110; + wire com_llm_llm_common_llm_common_reg_compare_1_result_cry_2_2111; + wire com_llm_llm_common_llm_common_reg_compare_1_result_cry_3_2112; + wire com_llm_llm_common_llm_common_reg_compare_1_result_cry_4_2113; + wire com_llm_llm_common_llm_common_reg_compare_1_result_cry_5_2114; + wire com_llm_llm_common_llm_common_reg_compare_1_result_cry_6_2115; + wire com_llm_llm_common_llm_common_reg_compare_1_result_cry_7_2116; + wire com_llm_llm_common_llm_common_reg_compare_1_result_cry_8_2117; + wire com_llm_llm_common_llm_common_reg_compare_1_result_cry_9_2118; + wire com_llm_llm_common_llm_common_reg_compare_1_result_cry_10_2119; + wire com_llm_llm_common_llm_common_reg_compare_1_result_axb_11_2120; + wire com_llm_llm_common_llm_common_reg_compare_1_result_axb_10_2121; + wire com_llm_llm_common_llm_common_reg_compare_1_result_axb_9_2122; + wire com_llm_llm_common_llm_common_reg_compare_1_result_axb_8_2123; + wire com_llm_llm_common_llm_common_reg_compare_1_result_axb_7_2124; + wire com_llm_llm_common_llm_common_reg_compare_1_result_axb_6_2125; + wire com_llm_llm_common_llm_common_reg_compare_1_result_axb_5_2126; + wire com_llm_llm_common_llm_common_reg_compare_1_result_axb_4_2127; + wire com_llm_llm_common_llm_common_reg_compare_1_result_axb_3_2128; + wire com_llm_llm_common_llm_common_reg_compare_1_result_axb_2_2129; + wire com_llm_llm_common_llm_common_reg_compare_1_result_axb_1_2130; + wire com_llm_llm_common_llm_common_reg_compare_1_result_axb_0_2131; + wire com_llm_llm_common_llm_common_reg_compare_2_VCC_2132; + wire com_llm_llm_common_llm_common_reg_compare_2_result_cry_0_2133; + wire com_llm_llm_common_llm_common_reg_compare_2_result_cry_1_2134; + wire com_llm_llm_common_llm_common_reg_compare_2_result_cry_2_2135; + wire com_llm_llm_common_llm_common_reg_compare_2_result_cry_3_2136; + wire com_llm_llm_common_llm_common_reg_compare_2_result_cry_4_2137; + wire com_llm_llm_common_llm_common_reg_compare_2_result_cry_5_2138; + wire com_llm_llm_common_llm_common_reg_compare_2_result_cry_6_2139; + wire com_llm_llm_common_llm_common_reg_compare_2_result_cry_7_2140; + wire com_llm_llm_common_llm_common_reg_compare_2_result_cry_8_2141; + wire com_llm_llm_common_llm_common_reg_compare_2_result_cry_9_2142; + wire com_llm_llm_common_llm_common_reg_compare_2_result_cry_10_2143; + wire com_llm_llm_common_llm_common_reg_compare_2_result_axb_11_2144; + wire com_llm_llm_common_llm_common_reg_compare_2_result_axb_10_2145; + wire com_llm_llm_common_llm_common_reg_compare_2_result_axb_9_2146; + wire com_llm_llm_common_llm_common_reg_compare_2_result_axb_8_2147; + wire com_llm_llm_common_llm_common_reg_compare_2_result_axb_7_2148; + wire com_llm_llm_common_llm_common_reg_compare_2_result_axb_6_2149; + wire com_llm_llm_common_llm_common_reg_compare_2_result_axb_5_2150; + wire com_llm_llm_common_llm_common_reg_compare_2_result_axb_4_2151; + wire com_llm_llm_common_llm_common_reg_compare_2_result_axb_3_2152; + wire com_llm_llm_common_llm_common_reg_compare_2_result_axb_2_2153; + wire com_llm_llm_common_llm_common_reg_compare_2_result_axb_1_2154; + wire com_llm_llm_common_llm_common_reg_compare_2_result_axb_0_2155; + wire com_llm_llm_common_llm_common_reg_llm_ack_nak_buf_N_67884_1; + wire com_llm_llm_common_llm_common_reg_llm_ack_nak_buf_N_8834_1_i; + wire com_llm_llm_common_llm_common_reg_llm_ack_nak_buf_N_38452; + wire com_llm_llm_common_llm_common_reg_llm_ack_nak_buf_N_67884_i_2156; + wire com_llm_llm_common_llm_common_reg_llm_ack_nak_buf_nak_pending_8; + wire com_llm_llm_common_llm_common_reg_llm_ack_nak_buf_N_67863_i_2157; + wire com_llm_llm_common_llm_common_reg_llm_ack_nak_buf_N_8834_i; + wire com_llm_llm_common_llm_common_reg_llm_ack_nak_fsm_N_38640; + wire com_llm_llm_common_llm_common_reg_llm_ack_nak_fsm_N_11654_i; + wire com_llm_llm_common_llm_common_reg_llm_ack_nak_fsm_N_68300_i; + wire com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_VCC_2158; + wire com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_set_2159; + wire com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_N_9729_i_2160; + wire com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_clear_2161; + wire com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_num21; + wire com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_N_8619_1; + wire com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_un1_replay_num_c1; + wire com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_un1_replay_num21_1_i_2162; + wire com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_N_18621_i; + wire com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_set_3; + wire com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_N_67866_i_2163; + wire com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_clear_3_i_0_0_a4_0_0_2164; + wire com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_expire_pre_4; + wire com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_I_19; + wire com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_GND_2165; + wire com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_reg_rx_dllp_nak_vld_qq_2166; + wire com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_NxtTxTSN_ANSeqNum_q_2167; + wire com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_ANSeqNum_Eq_AckdSeq_q_2168; + wire com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_ANSeqNum_AckdSeq_q_2169; + wire com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_reg_same_last_ackd_tsn_3; + wire com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_reg_same_last_ackd_tsn_2170; + wire com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_expire_5; + wire com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_vld_q_2171; + wire com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_expire_pre_5; + wire com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_N_18614_i; + wire com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_N_18612_i; + wire com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_N_42787_i_2172; + wire com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_N_42788_i_2173; + wire com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_N_42789_i_2174; + wire com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_N_42790_i_2175; + wire com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_N_42791_i_2176; + wire com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_N_42792_i_2177; + wire com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_N_42793_i_2178; + wire com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_N_42794_i_2179; + wire com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_N_42795_i_2180; + wire com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_N_42796_i_2181; + wire com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_N_42797_i_2182; + wire com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_N_42798_i_2183; + wire com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_N_67880_i_2184; + wire com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timeout_flag17; + wire com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_N_69069_i_2185; + wire com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_waiting_2186; + wire com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_N_27_0; + wire com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_N_7_i; + wire com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_N_27; + wire com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_N_3_0; + wire com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_N_11_0; + wire com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_N_19_0; + wire com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_N_35_0; + wire com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_N_43_0; + wire com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_N_9; + wire com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_N_17; + wire com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_N_25; + wire com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_N_33; + wire com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_N_41; + wire com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_N_49; + wire com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_N_57; + wire com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_N_3; + wire com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_N_11; + wire com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_N_19; + wire com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_N_35; + wire com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_N_43; + wire com_llm_llm_common_llm_common_reg_llm_next_rcv_tsn_GND_2187; + wire com_tlm_aspm_ok; + wire com_tlm_u_tlm_tx_pkt_incoming; + wire com_tlm_u_tlm_tx_cfg_accepted; + wire com_tlm_u_tlm_tx_suspend_credit_rdy; + wire com_tlm_u_tlm_tx_fc_update_vld; + wire com_tlm_u_tlm_tx_fc_init_vld; + wire com_tlm_u_tlm_tx_am_retry_dst_rdy; + wire com_tlm_u_tlm_tx_am_retry_src_rdy; + wire com_tlm_u_tlm_tx_am_retry_lock; + wire com_tlm_u_tlm_tx_N_38179_i; + wire com_tlm_u_tlm_tx_ack_pending; + wire com_tlm_u_tlm_tx_en_qq; + wire com_tlm_u_tlm_tx_vc0_eof; + wire com_tlm_u_tlm_tx_vc0_retry; + wire com_tlm_u_tlm_tx_vc0_errfwd; + wire com_tlm_u_tlm_tx_vc0_sof; + wire com_tlm_u_tlm_tx_vc0_cfg; + wire com_tlm_u_tlm_tx_vc0_src_rdy; + wire com_tlm_u_tlm_tx_ds_buf_src_rdy; + wire com_tlm_u_tlm_tx_cfg_sent; + wire com_tlm_u_tlm_tx_data_src_cfg_sent_d_2188; + wire com_tlm_u_tlm_tx_data_src_GND_2189; + wire com_tlm_u_tlm_tx_data_src_N_17261_i_2190; + wire com_tlm_u_tlm_tx_data_src_lnk_tsrc_rdy; + wire com_tlm_u_tlm_tx_data_src_lnk_tsof_o_5; + wire com_tlm_u_tlm_tx_data_src_lnk_tretry_o_5; + wire com_tlm_u_tlm_tx_data_src_N_17280_i_2191; + wire com_tlm_u_tlm_tx_data_src_cfg_sent_d_3; + wire com_tlm_u_tlm_tx_data_src_stat_tlp_wr_ep_o_5; + wire com_tlm_u_tlm_tx_data_src_buf_src_rdy_o_3; + wire com_tlm_u_tlm_tx_data_src_un1_lnk_tsrc_rdy_o_1_0_a2_2192; + wire com_tlm_u_tlm_tx_data_src_N_69038_i_2193; + wire com_tlm_u_tlm_tx_data_src_lnk_teof_o_5; + wire com_tlm_u_tlm_tx_ack_mgr_un1_oldest_tsn_1_cry_0_2194; + wire com_tlm_u_tlm_tx_ack_mgr_un1_oldest_tsn_1_cry_1_2195; + wire com_tlm_u_tlm_tx_ack_mgr_un1_oldest_tsn_1_cry_2_2196; + wire com_tlm_u_tlm_tx_ack_mgr_un1_oldest_tsn_1_cry_3_2197; + wire com_tlm_u_tlm_tx_ack_mgr_un1_oldest_tsn_1_cry_4_2198; + wire com_tlm_u_tlm_tx_ack_mgr_un1_oldest_tsn_1_cry_5_2199; + wire com_tlm_u_tlm_tx_ack_mgr_un1_oldest_tsn_1_cry_6_2200; + wire com_tlm_u_tlm_tx_ack_mgr_un1_oldest_tsn_1_cry_7_2201; + wire com_tlm_u_tlm_tx_ack_mgr_un1_oldest_tsn_1_cry_8_2202; + wire com_tlm_u_tlm_tx_ack_mgr_un1_oldest_tsn_1_cry_9_2203; + wire com_tlm_u_tlm_tx_ack_mgr_un1_oldest_tsn_1_cry_10_2204; + wire com_tlm_u_tlm_tx_ack_mgr_VCC_2205; + wire com_tlm_u_tlm_tx_ack_mgr_un4_retry_tsn_o_s_1_2206; + wire com_tlm_u_tlm_tx_ack_mgr_un4_retry_tsn_o_cry_0_2207; + wire com_tlm_u_tlm_tx_ack_mgr_un4_retry_tsn_o_s_2_2208; + wire com_tlm_u_tlm_tx_ack_mgr_un4_retry_tsn_o_cry_1_2209; + wire com_tlm_u_tlm_tx_ack_mgr_un4_retry_tsn_o_s_3_2210; + wire com_tlm_u_tlm_tx_ack_mgr_un4_retry_tsn_o_cry_2_2211; + wire com_tlm_u_tlm_tx_ack_mgr_un4_retry_tsn_o_s_4_2212; + wire com_tlm_u_tlm_tx_ack_mgr_un4_retry_tsn_o_cry_3_2213; + wire com_tlm_u_tlm_tx_ack_mgr_un4_retry_tsn_o_s_5_2214; + wire com_tlm_u_tlm_tx_ack_mgr_un4_retry_tsn_o_cry_4_2215; + wire com_tlm_u_tlm_tx_ack_mgr_un4_retry_tsn_o_s_6_2216; + wire com_tlm_u_tlm_tx_ack_mgr_un4_retry_tsn_o_cry_5_2217; + wire com_tlm_u_tlm_tx_ack_mgr_un4_retry_tsn_o_s_7_2218; + wire com_tlm_u_tlm_tx_ack_mgr_un4_retry_tsn_o_cry_6_2219; + wire com_tlm_u_tlm_tx_ack_mgr_un4_retry_tsn_o_s_8_2220; + wire com_tlm_u_tlm_tx_ack_mgr_un4_retry_tsn_o_cry_7_2221; + wire com_tlm_u_tlm_tx_ack_mgr_un4_retry_tsn_o_s_9_2222; + wire com_tlm_u_tlm_tx_ack_mgr_un4_retry_tsn_o_cry_8_2223; + wire com_tlm_u_tlm_tx_ack_mgr_un4_retry_tsn_o_s_10_2224; + wire com_tlm_u_tlm_tx_ack_mgr_un4_retry_tsn_o_cry_9_2225; + wire com_tlm_u_tlm_tx_ack_mgr_un4_retry_tsn_o_s_11_2226; + wire com_tlm_u_tlm_tx_ack_mgr_un4_retry_tsn_o_cry_10_2227; + wire com_tlm_u_tlm_tx_ack_mgr_un1_lnk_rupdate_ack_i_0_a3_0_a2_0_a4_2228; + wire com_tlm_u_tlm_tx_ack_mgr_nak_req_2229; + wire com_tlm_u_tlm_tx_ack_mgr_N_69068_i_2230; + wire com_tlm_u_tlm_tx_ack_mgr_N_38140_i; + wire com_tlm_u_tlm_tx_ack_mgr_mgr_state_12__2231; + wire com_tlm_u_tlm_tx_ack_mgr_N_69235_i_2232; + wire com_tlm_u_tlm_tx_ack_mgr_N_38186_i; + wire com_tlm_u_tlm_tx_ack_mgr_mgr_state_9__2233; + wire com_tlm_u_tlm_tx_ack_mgr_N_69140_i_2234; + wire com_tlm_u_tlm_tx_ack_mgr_N_38388_2; + wire com_tlm_u_tlm_tx_ack_mgr_N_38191_i; + wire com_tlm_u_tlm_tx_ack_mgr_mgr_statec_0_i; + wire com_tlm_u_tlm_tx_ack_mgr_N_38242_i; + wire com_tlm_u_tlm_tx_ack_mgr_N_38101_i; + wire com_tlm_u_tlm_tx_ack_mgr_mgr_statec_1_i; + wire com_tlm_u_tlm_tx_ack_mgr_mgr_statec_1_i_1; + wire com_tlm_u_tlm_tx_ack_mgr_mgr_statec_2_i; + wire com_tlm_u_tlm_tx_ack_mgr_mgr_statec_3_i; + wire com_tlm_u_tlm_tx_ack_mgr_mgr_state_10__2235; + wire com_tlm_u_tlm_tx_ack_mgr_N_38426; + wire com_tlm_u_tlm_tx_ack_mgr_mgr_statec_4_i; + wire com_tlm_u_tlm_tx_ack_mgr_N_38366_i; + wire com_tlm_u_tlm_tx_ack_mgr_N_38146_i; + wire com_tlm_u_tlm_tx_ack_mgr_un1_oldest_tsn_1_axb_11_2236; + wire com_tlm_u_tlm_tx_ack_mgr_un1_oldest_tsn_1_axb_10_2237; + wire com_tlm_u_tlm_tx_ack_mgr_un1_oldest_tsn_1_axb_9_2238; + wire com_tlm_u_tlm_tx_ack_mgr_un1_oldest_tsn_1_axb_8_2239; + wire com_tlm_u_tlm_tx_ack_mgr_un1_oldest_tsn_1_axb_7_2240; + wire com_tlm_u_tlm_tx_ack_mgr_un1_oldest_tsn_1_axb_6_2241; + wire com_tlm_u_tlm_tx_ack_mgr_un1_oldest_tsn_1_axb_5_2242; + wire com_tlm_u_tlm_tx_ack_mgr_un1_oldest_tsn_1_axb_4_2243; + wire com_tlm_u_tlm_tx_ack_mgr_un1_oldest_tsn_1_axb_3_2244; + wire com_tlm_u_tlm_tx_ack_mgr_un1_oldest_tsn_1_axb_2_2245; + wire com_tlm_u_tlm_tx_ack_mgr_un1_oldest_tsn_1_axb_1_2246; + wire com_tlm_u_tlm_tx_ack_mgr_un1_oldest_tsn_1_axb_0_2247; + wire com_tlm_u_tlm_tx_ack_mgr_N_38092_i; + wire com_tlm_u_tlm_tx_ack_mgr_mgr_state_11__2248; + wire com_tlm_u_tlm_tx_ack_mgr_N_38742; + wire com_tlm_u_tlm_tx_ack_mgr_N_38757_i_2249; + wire com_tlm_u_tlm_tx_ack_mgr_fifo_nxt_vld; + wire com_tlm_u_tlm_tx_ack_mgr_nak_in_retry19; + wire com_tlm_u_tlm_tx_ack_mgr_N_38199_i; + wire com_tlm_u_tlm_tx_ack_mgr_un4_retry_tsn_o_axb_11_2250; + wire com_tlm_u_tlm_tx_ack_mgr_un4_retry_tsn_o_axb_10_2251; + wire com_tlm_u_tlm_tx_ack_mgr_un4_retry_tsn_o_axb_9_2252; + wire com_tlm_u_tlm_tx_ack_mgr_un4_retry_tsn_o_axb_8_2253; + wire com_tlm_u_tlm_tx_ack_mgr_un4_retry_tsn_o_axb_7_2254; + wire com_tlm_u_tlm_tx_ack_mgr_un4_retry_tsn_o_axb_6_2255; + wire com_tlm_u_tlm_tx_ack_mgr_un4_retry_tsn_o_axb_5_2256; + wire com_tlm_u_tlm_tx_ack_mgr_un4_retry_tsn_o_axb_4_2257; + wire com_tlm_u_tlm_tx_ack_mgr_un4_retry_tsn_o_axb_3_2258; + wire com_tlm_u_tlm_tx_ack_mgr_un4_retry_tsn_o_axb_2_2259; + wire com_tlm_u_tlm_tx_ack_mgr_un4_retry_tsn_o_axb_1_2260; + wire com_tlm_u_tlm_tx_ack_mgr_N_38266_i_2261; + wire com_tlm_u_tlm_tx_ack_mgr_N_67879_i_2262; + wire com_tlm_u_tlm_tx_ack_mgr_retry_src_rdy_o_3_i_0_0_0_2263; + wire com_tlm_u_tlm_tx_ack_mgr_N_69234_i_2264; + wire com_tlm_u_tlm_tx_ack_mgr_nak_in_retry_2265; + wire com_tlm_u_tlm_tx_ack_mgr_N_39057; + wire com_tlm_u_tlm_tx_ack_mgr_mgr_state_7__2266; + wire com_tlm_u_tlm_tx_ack_mgr_fifo_vld; + wire com_tlm_u_tlm_tx_ack_mgr_N_9704_i_i; + wire com_tlm_u_tlm_tx_ack_mgr_N_9704_i_i_i_2267; + wire com_tlm_u_tlm_tx_ack_mgr_un1_skips_pending; + wire com_tlm_u_tlm_tx_ack_mgr_un1_frees_pending; + wire com_tlm_u_tlm_tx_ack_mgr_GND_2268; + wire com_tlm_u_tlm_tx_ack_mgr_un1_oldest_tsn_1_s_11_2269; + wire com_tlm_u_tlm_tx_ack_mgr_un1_oldest_tsn_1_s_10_2270; + wire com_tlm_u_tlm_tx_ack_mgr_un1_oldest_tsn_1_s_9_2271; + wire com_tlm_u_tlm_tx_ack_mgr_un1_oldest_tsn_1_s_8_2272; + wire com_tlm_u_tlm_tx_ack_mgr_un1_oldest_tsn_1_s_7_2273; + wire com_tlm_u_tlm_tx_ack_mgr_un1_oldest_tsn_1_s_6_2274; + wire com_tlm_u_tlm_tx_ack_mgr_un1_oldest_tsn_1_s_5_2275; + wire com_tlm_u_tlm_tx_ack_mgr_un1_oldest_tsn_1_s_4_2276; + wire com_tlm_u_tlm_tx_ack_mgr_un1_oldest_tsn_1_s_3_2277; + wire com_tlm_u_tlm_tx_ack_mgr_un1_oldest_tsn_1_s_2_2278; + wire com_tlm_u_tlm_tx_ack_mgr_un1_oldest_tsn_1_s_1_2279; + wire com_tlm_u_tlm_tx_ack_mgr_un1_oldest_tsn_1_s_0_2280; + wire com_tlm_u_tlm_tx_ack_mgr_N_69061_i_2281; + wire com_tlm_u_tlm_tx_ack_mgr_mgr_state_8__2282; + wire com_tlm_u_tlm_tx_ack_mgr_N_68235_i_2283; + wire com_tlm_u_tlm_tx_ack_mgr_mgr_state_4__2284; + wire com_tlm_u_tlm_tx_ack_mgr_N_69138_i_2285; + wire com_tlm_u_tlm_tx_ack_mgr_mgr_state_2__2286; + wire com_tlm_u_tlm_tx_ack_mgr_N_8638_i; + wire com_tlm_u_tlm_tx_ack_mgr_mgr_state_0__2287; + wire com_tlm_u_tlm_tx_ack_mgr_N_38168_i_i_2288; + wire com_tlm_u_tlm_tx_ack_mgr_N_38168_i; + wire com_tlm_u_tlm_tx_ack_mgr_N_27_0; + wire com_tlm_u_tlm_tx_ack_mgr_N_27; + wire com_tlm_u_tlm_tx_ack_mgr_un4_retry_tsn_o_axb_0_2289; + wire com_tlm_u_tlm_tx_ack_mgr_jump_retry_tsn_2290; + wire com_tlm_u_tlm_tx_ack_mgr_N_3_0; + wire com_tlm_u_tlm_tx_ack_mgr_N_11_0; + wire com_tlm_u_tlm_tx_ack_mgr_N_19_0; + wire com_tlm_u_tlm_tx_ack_mgr_N_35_0; + wire com_tlm_u_tlm_tx_ack_mgr_N_43_0; + wire com_tlm_u_tlm_tx_ack_mgr_N_3; + wire com_tlm_u_tlm_tx_ack_mgr_N_11; + wire com_tlm_u_tlm_tx_ack_mgr_N_19; + wire com_tlm_u_tlm_tx_ack_mgr_N_35; + wire com_tlm_u_tlm_tx_ack_mgr_N_43; + wire com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_GND_2291; + wire com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_un1_raddr_lo_1_cry_0_2292; + wire com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_un1_raddr_lo_1_cry_1_2293; + wire com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_un1_raddr_lo_1_cry_2_2294; + wire com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_un1_raddr_lo_1_axb_3_2295; + wire com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_N_67901_i_2296; + wire com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_un1_bkp_i_1_i_0_0_a4_2_2297; + wire com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_vld_o_5_i_m2_i_m3_0_2298; + wire com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_bkp_vld_2299; + wire com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_nxt_vld_o_8_iv_i_m2_i_m3_0_2300; + wire com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_bkp_nxt_vld_2301; + wire com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_N_38376_i_2302; + wire com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_un1_bkp_raddr_lo_1_p4_2303; + wire com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_N_34665_i; + wire com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_un1_bkp_raddr_lo_1_c1; + wire com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_un1_raddr_lo_1_s_3_2304; + wire com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_un1_raddr_lo_1_s_2_2305; + wire com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_un1_raddr_lo_1_s_1_2306; + wire com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_un1_raddr_lo_1_axb_0_2307; + wire com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_un1_bkp_raddr_lo_1_ac0_1_2308; + wire com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_N_69139_i; + wire com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_un1_raddr_lo_1_axb_2_2309; + wire com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_un1_raddr_lo_1_axb_1_2310; + wire com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_ct_o35_0_0_o3; + wire com_tlm_u_tlm_tx_vc0_released_buf; + wire com_tlm_u_tlm_tx_vc0_frame_vld; + wire com_tlm_u_tlm_tx_vc0_no_payload; + wire com_tlm_u_tlm_tx_vc0_trn_sof; + wire com_tlm_u_tlm_tx_vc0_N_17214_i; + wire com_tlm_u_tlm_tx_vc0_nxt_seq_state_0_sqmuxa_i_o2_i_a2; + wire com_tlm_u_tlm_tx_vc0_trn_vld; + wire com_tlm_u_tlm_tx_vc0_trn_rem_i; + wire com_tlm_u_tlm_tx_vc0_trn_cfg; + wire com_tlm_u_tlm_tx_vc0_trn_eof; + wire com_tlm_u_tlm_tx_vc0_trn_errfwd; + wire com_tlm_u_tlm_tx_vc0_in_frame; + wire com_tlm_u_tlm_tx_vc0_start_retry; + wire com_tlm_u_tlm_tx_vc0_buf_pool_retry_dd_2311; + wire com_tlm_u_tlm_tx_vc0_buf_pool_errfwd_wen_2312; + wire com_tlm_u_tlm_tx_vc0_buf_pool_VCC_2313; + wire com_tlm_u_tlm_tx_vc0_buf_pool_waddr_l_1_cry_0_2314; + wire com_tlm_u_tlm_tx_vc0_buf_pool_waddr_l_1_cry_1_2315; + wire com_tlm_u_tlm_tx_vc0_buf_pool_waddr_l_1_cry_2_2316; + wire com_tlm_u_tlm_tx_vc0_buf_pool_waddr_l_1_cry_3_2317; + wire com_tlm_u_tlm_tx_vc0_buf_pool_waddr_l_1_cry_4_2318; + wire com_tlm_u_tlm_tx_vc0_buf_pool_waddr_l_1_cry_5_2319; + wire com_tlm_u_tlm_tx_vc0_buf_pool_GND_2320; + wire com_tlm_u_tlm_tx_vc0_buf_pool_start_xfer_q_2321; + wire com_tlm_u_tlm_tx_vc0_buf_pool_rdata_sof_d_hold_2322; + wire com_tlm_u_tlm_tx_vc0_buf_pool_rdata_sof_2323; + wire com_tlm_u_tlm_tx_vc0_buf_pool_N_22083_i; + wire com_tlm_u_tlm_tx_vc0_buf_pool_wdata_vld_any_2324; + wire com_tlm_u_tlm_tx_vc0_buf_pool_N_17124_i; + wire com_tlm_u_tlm_tx_vc0_buf_pool_N_22095_i; + wire com_tlm_u_tlm_tx_vc0_buf_pool_N_17127_i; + wire com_tlm_u_tlm_tx_vc0_buf_pool_N_69239_i_2325; + wire com_tlm_u_tlm_tx_vc0_buf_pool_waddr_l_1_axb_6_2326; + wire com_tlm_u_tlm_tx_vc0_buf_pool_waddr_l_1_axb_5_2327; + wire com_tlm_u_tlm_tx_vc0_buf_pool_waddr_l_1_axb_4_2328; + wire com_tlm_u_tlm_tx_vc0_buf_pool_waddr_l_1_axb_3_2329; + wire com_tlm_u_tlm_tx_vc0_buf_pool_waddr_l_1_axb_2_2330; + wire com_tlm_u_tlm_tx_vc0_buf_pool_waddr_l_1_axb_1_2331; + wire com_tlm_u_tlm_tx_vc0_buf_pool_rdata_q_all_5_68_; + wire com_tlm_u_tlm_tx_vc0_buf_pool_rdata_q_all_5_66_; + wire com_tlm_u_tlm_tx_vc0_buf_pool_rdata_q_all_5_65_; + wire com_tlm_u_tlm_tx_vc0_buf_pool_rdata_q_all_5_64_; + wire com_tlm_u_tlm_tx_vc0_buf_pool_rvld_any_2332; + wire com_tlm_u_tlm_tx_vc0_buf_pool_rdata_sof_d_hold_3; + wire com_tlm_u_tlm_tx_vc0_buf_pool_errfwd; + wire com_tlm_u_tlm_tx_vc0_buf_pool_N_22107_i_2333; + wire com_tlm_u_tlm_tx_vc0_buf_pool_rdata_errfwd_2334; + wire com_tlm_u_tlm_tx_vc0_buf_pool_wdata_66__2335; + wire com_tlm_u_tlm_tx_vc0_buf_pool_wdata_65__2336; + wire com_tlm_u_tlm_tx_vc0_buf_pool_wdata_64__2337; + wire com_tlm_u_tlm_tx_vc0_buf_pool_wdata_63__2338; + wire com_tlm_u_tlm_tx_vc0_buf_pool_wdata_62__2339; + wire com_tlm_u_tlm_tx_vc0_buf_pool_wdata_61__2340; + wire com_tlm_u_tlm_tx_vc0_buf_pool_wdata_60__2341; + wire com_tlm_u_tlm_tx_vc0_buf_pool_wdata_59__2342; + wire com_tlm_u_tlm_tx_vc0_buf_pool_wdata_58__2343; + wire com_tlm_u_tlm_tx_vc0_buf_pool_wdata_57__2344; + wire com_tlm_u_tlm_tx_vc0_buf_pool_wdata_56__2345; + wire com_tlm_u_tlm_tx_vc0_buf_pool_wdata_55__2346; + wire com_tlm_u_tlm_tx_vc0_buf_pool_wdata_54__2347; + wire com_tlm_u_tlm_tx_vc0_buf_pool_wdata_53__2348; + wire com_tlm_u_tlm_tx_vc0_buf_pool_wdata_52__2349; + wire com_tlm_u_tlm_tx_vc0_buf_pool_wdata_51__2350; + wire com_tlm_u_tlm_tx_vc0_buf_pool_wdata_50__2351; + wire com_tlm_u_tlm_tx_vc0_buf_pool_wdata_49__2352; + wire com_tlm_u_tlm_tx_vc0_buf_pool_wdata_48__2353; + wire com_tlm_u_tlm_tx_vc0_buf_pool_wdata_47__2354; + wire com_tlm_u_tlm_tx_vc0_buf_pool_wdata_46__2355; + wire com_tlm_u_tlm_tx_vc0_buf_pool_wdata_45__2356; + wire com_tlm_u_tlm_tx_vc0_buf_pool_wdata_44__2357; + wire com_tlm_u_tlm_tx_vc0_buf_pool_wdata_43__2358; + wire com_tlm_u_tlm_tx_vc0_buf_pool_wdata_42__2359; + wire com_tlm_u_tlm_tx_vc0_buf_pool_wdata_41__2360; + wire com_tlm_u_tlm_tx_vc0_buf_pool_wdata_40__2361; + wire com_tlm_u_tlm_tx_vc0_buf_pool_wdata_39__2362; + wire com_tlm_u_tlm_tx_vc0_buf_pool_wdata_38__2363; + wire com_tlm_u_tlm_tx_vc0_buf_pool_wdata_37__2364; + wire com_tlm_u_tlm_tx_vc0_buf_pool_wdata_36__2365; + wire com_tlm_u_tlm_tx_vc0_buf_pool_wdata_35__2366; + wire com_tlm_u_tlm_tx_vc0_buf_pool_wdata_34__2367; + wire com_tlm_u_tlm_tx_vc0_buf_pool_wdata_33__2368; + wire com_tlm_u_tlm_tx_vc0_buf_pool_wdata_32__2369; + wire com_tlm_u_tlm_tx_vc0_buf_pool_wdata_31__2370; + wire com_tlm_u_tlm_tx_vc0_buf_pool_wdata_30__2371; + wire com_tlm_u_tlm_tx_vc0_buf_pool_wdata_29__2372; + wire com_tlm_u_tlm_tx_vc0_buf_pool_wdata_28__2373; + wire com_tlm_u_tlm_tx_vc0_buf_pool_wdata_27__2374; + wire com_tlm_u_tlm_tx_vc0_buf_pool_wdata_26__2375; + wire com_tlm_u_tlm_tx_vc0_buf_pool_wdata_25__2376; + wire com_tlm_u_tlm_tx_vc0_buf_pool_wdata_24__2377; + wire com_tlm_u_tlm_tx_vc0_buf_pool_wdata_23__2378; + wire com_tlm_u_tlm_tx_vc0_buf_pool_wdata_22__2379; + wire com_tlm_u_tlm_tx_vc0_buf_pool_wdata_21__2380; + wire com_tlm_u_tlm_tx_vc0_buf_pool_wdata_20__2381; + wire com_tlm_u_tlm_tx_vc0_buf_pool_wdata_19__2382; + wire com_tlm_u_tlm_tx_vc0_buf_pool_wdata_18__2383; + wire com_tlm_u_tlm_tx_vc0_buf_pool_wdata_17__2384; + wire com_tlm_u_tlm_tx_vc0_buf_pool_wdata_16__2385; + wire com_tlm_u_tlm_tx_vc0_buf_pool_wdata_15__2386; + wire com_tlm_u_tlm_tx_vc0_buf_pool_wdata_14__2387; + wire com_tlm_u_tlm_tx_vc0_buf_pool_wdata_13__2388; + wire com_tlm_u_tlm_tx_vc0_buf_pool_wdata_12__2389; + wire com_tlm_u_tlm_tx_vc0_buf_pool_wdata_11__2390; + wire com_tlm_u_tlm_tx_vc0_buf_pool_wdata_10__2391; + wire com_tlm_u_tlm_tx_vc0_buf_pool_wdata_9__2392; + wire com_tlm_u_tlm_tx_vc0_buf_pool_wdata_8__2393; + wire com_tlm_u_tlm_tx_vc0_buf_pool_wdata_7__2394; + wire com_tlm_u_tlm_tx_vc0_buf_pool_wdata_6__2395; + wire com_tlm_u_tlm_tx_vc0_buf_pool_wdata_5__2396; + wire com_tlm_u_tlm_tx_vc0_buf_pool_wdata_4__2397; + wire com_tlm_u_tlm_tx_vc0_buf_pool_wdata_3__2398; + wire com_tlm_u_tlm_tx_vc0_buf_pool_wdata_2__2399; + wire com_tlm_u_tlm_tx_vc0_buf_pool_wdata_1__2400; + wire com_tlm_u_tlm_tx_vc0_buf_pool_wdata_0__2401; + wire com_tlm_u_tlm_tx_vc0_buf_pool_N_22106_i; + wire com_tlm_u_tlm_tx_vc0_buf_pool_wdata_68_; + wire com_tlm_u_tlm_tx_vc0_buf_pool_N_68303_i_2402; + wire com_tlm_u_tlm_tx_vc0_buf_pool_wdata_errfwd_2403; + wire com_tlm_u_tlm_tx_vc0_buf_pool_en_ram_i_i; + wire com_tlm_u_tlm_tx_vc0_buf_pool_N_17122_i; + wire com_tlm_u_tlm_tx_vc0_buf_pool_N_51062_i_2404; + wire com_tlm_u_tlm_tx_vc0_buf_pool_rdata_sof_d_0_a2_2405; + wire com_tlm_u_tlm_tx_vc0_buf_pool_N_17214_i_i_2406; + wire com_tlm_u_tlm_tx_vc0_buf_pool_waddr_l_1_axb_0_2407; + wire com_tlm_u_tlm_tx_vc0_buf_pool_bram_0__size8_bram_array_GND_2408; + wire com_tlm_u_tlm_tx_vc0_buf_pool_bram_0__size8_bram_array_VCC_2409; + wire com_tlm_u_tlm_tx_vc0_buf_pool_bram_0__size8_bram_array_N_9690_i_2410; + wire com_tlm_u_tlm_tx_vc0_trn_un1_trn_tbuf_av_o_1_cry_1_0_2411; + wire com_tlm_u_tlm_tx_vc0_trn_un1_trn_tbuf_av_o_1_s_1_2412; + wire com_tlm_u_tlm_tx_vc0_trn_un1_trn_tbuf_av_o_1_cry_0_2413; + wire com_tlm_u_tlm_tx_vc0_trn_un1_trn_tbuf_av_o_1_cry_2_0_2414; + wire com_tlm_u_tlm_tx_vc0_trn_un1_trn_tbuf_av_o_1_s_2_2415; + wire com_tlm_u_tlm_tx_vc0_trn_un1_trn_tbuf_av_o_1_cry_1_2416; + wire com_tlm_u_tlm_tx_vc0_trn_un1_trn_tbuf_av_o_1_cry_3_0_2417; + wire com_tlm_u_tlm_tx_vc0_trn_un1_trn_tbuf_av_o_1_s_3_2418; + wire com_tlm_u_tlm_tx_vc0_trn_un1_trn_tbuf_av_o_1_cry_2_2419; + wire com_tlm_u_tlm_tx_vc0_trn_un1_trn_tbuf_av_o_1_s_4_2420; + wire com_tlm_u_tlm_tx_vc0_trn_un1_trn_tbuf_av_o_1_cry_3_2421; + wire com_tlm_u_tlm_tx_vc0_trn_un1_usr_vld_0_a4_0_a2_0_a2_0_a2_2422; + wire com_tlm_u_tlm_tx_vc0_trn_load_counter_q_2423; + wire com_tlm_u_tlm_tx_vc0_trn_usr_sof_2424; + wire com_tlm_u_tlm_tx_vc0_trn_dsc_in_q_2425; + wire com_tlm_u_tlm_tx_vc0_trn_buf_av_zero_2426; + wire com_tlm_u_tlm_tx_vc0_trn_buffer_rdy_2427; + wire com_tlm_u_tlm_tx_vc0_trn_trn_tdst_rdy_o_3_0_0_0_o2_0_0_2428; + wire com_tlm_u_tlm_tx_vc0_trn_N_39946; + wire com_tlm_u_tlm_tx_vc0_trn_N_68766_i_2429; + wire com_tlm_u_tlm_tx_vc0_trn_usr_dsc_2430; + wire com_tlm_u_tlm_tx_vc0_trn_N_49601; + wire com_tlm_u_tlm_tx_vc0_trn_rem_o_5_0_0_0_o3_1_2431; + wire com_tlm_u_tlm_tx_vc0_trn_N_67955_i_2432; + wire com_tlm_u_tlm_tx_vc0_trn_N_13633_i; + wire com_tlm_u_tlm_tx_vc0_trn_un1_trn_tbuf_av_o_1_axb_0_2433; + wire com_tlm_u_tlm_tx_vc0_trn_N_13650_i; + wire com_tlm_u_tlm_tx_vc0_trn_usr_calc_eof_0_sqmuxa_i_0_0_7_2434; + wire com_tlm_u_tlm_tx_vc0_trn_usr_calc_eof_0_sqmuxa_i_0_0_5_2435; + wire com_tlm_u_tlm_tx_vc0_trn_usr_calc_eof_0_sqmuxa_i_0_0_0_2436; + wire com_tlm_u_tlm_tx_vc0_trn_N_48939_i; + wire com_tlm_u_tlm_tx_vc0_trn_N_48904_i; + wire com_tlm_u_tlm_tx_vc0_trn_N_68960_i_2437; + wire com_tlm_u_tlm_tx_vc0_trn_N_50761_1; + wire com_tlm_u_tlm_tx_vc0_trn_N_68959_i_2438; + wire com_tlm_u_tlm_tx_vc0_trn_un1_usr_abort_8_0_0_0_0_a2_0; + wire com_tlm_u_tlm_tx_vc0_trn_un1_usr_abort_8_0_0_0_0_o3_2439; + wire com_tlm_u_tlm_tx_vc0_trn_usr_calc_eof_2440; + wire com_tlm_u_tlm_tx_vc0_trn_N_39869_i; + wire com_tlm_u_tlm_tx_vc0_trn_N_49591; + wire com_tlm_u_tlm_tx_vc0_trn_N_49588; + wire com_tlm_u_tlm_tx_vc0_trn_trn_rem; + wire com_tlm_u_tlm_tx_vc0_trn_N_48986_i_i_2441; + wire com_tlm_u_tlm_tx_vc0_trn_N_49953_i_2442; + wire com_tlm_u_tlm_tx_vc0_trn_usr_eof_filt; + wire com_tlm_u_tlm_tx_vc0_trn_usr_eof_2443; + wire com_tlm_u_tlm_tx_vc0_trn_N_49952_i_2444; + wire com_tlm_u_tlm_tx_vc0_trn_un13_pkt_incoming_o_i_2445; + wire com_tlm_u_tlm_tx_vc0_trn_N_13635_i; + wire com_tlm_u_tlm_tx_vc0_trn_N_68962_i_2446; + wire com_tlm_u_tlm_tx_vc0_trn_usr_frame_in17; + wire com_tlm_u_tlm_tx_vc0_trn_N_48986_i; + wire com_tlm_u_tlm_tx_vc0_trn_N_28284_i; + wire com_tlm_u_tlm_tx_vc0_trn_eof_o_5_i_0_0_0_2447; + wire com_tlm_u_tlm_tx_vc0_trn_N_28286_i; + wire com_tlm_u_tlm_tx_vc0_trn_usr_errfwd_2448; + wire com_tlm_u_tlm_tx_vc0_trn_N_68957_i_2449; + wire com_tlm_u_tlm_tx_vc0_trn_usr_vld_2450; + wire com_tlm_u_tlm_tx_vc0_trn_usr_sof_filt; + wire com_tlm_u_tlm_tx_vc0_trn_usr_frame_2451; + wire com_tlm_u_tlm_tx_vc0_trn_N_68115_i_2452; + wire com_tlm_u_tlm_tx_vc0_trn_usr_rem_2453; + wire com_tlm_u_tlm_tx_vc0_trn_N_49231; + wire com_tlm_u_tlm_tx_vc0_trn_N_68621_i_2454; + wire com_tlm_u_tlm_tx_vc0_trn_vld_o_5_i_i_a2_i_a3_2455; + wire com_tlm_u_tlm_tx_vc0_trn_vld_o_5_i_i_a2_i_a2_2456; + wire com_tlm_u_tlm_tx_vc0_trn_N_28290_i; + wire com_tlm_u_tlm_tx_vc0_trn_pkts_in_trn_1_sqmuxa_5604_i_0_0_0_o3_2457; + wire com_tlm_u_tlm_tx_vc0_trn_N_68986_i_2458; + wire com_tlm_u_tlm_tx_vc0_trn_cfg_frame_in_2459; + wire com_tlm_u_tlm_tx_vc0_trn_N_49237; + wire com_tlm_u_tlm_tx_vc0_trn_N_68987_i_2460; + wire com_tlm_u_tlm_tx_vc0_trn_usr_frame_in_2461; + wire com_tlm_u_tlm_tx_vc0_trn_trn_tdst_rdy_o_3_0_0_0_a2_0_0; + wire com_tlm_u_tlm_tx_vc0_trn_N_49515; + wire com_tlm_u_tlm_tx_vc0_trn_N_39932; + wire com_tlm_u_tlm_tx_vc0_trn_N_13653_i; + wire com_tlm_u_tlm_tx_vc0_trn_usr_start; + wire com_tlm_u_tlm_tx_vc0_trn_cfg_start; + wire com_tlm_u_tlm_tx_vc0_trn_buffer_rdy_3_i_0_0_0_0_2462; + wire com_tlm_u_tlm_tx_vc0_trn_buf_av_one_2463; + wire com_tlm_u_tlm_tx_vc0_trn_un1_trn_tbuf_av_o_1_axb_4_2464; + wire com_tlm_u_tlm_tx_vc0_trn_un1_trn_tbuf_av_o_1_axb_3_2465; + wire com_tlm_u_tlm_tx_vc0_trn_un1_trn_tbuf_av_o_1_axb_2_2466; + wire com_tlm_u_tlm_tx_vc0_trn_un1_trn_tbuf_av_o_1_axb_1_2467; + wire com_tlm_u_tlm_tx_vc0_trn_N_13806_i; + wire com_tlm_u_tlm_tx_vc0_trn_un1_pkts_in_trn_1_axbxc1_2468; + wire com_tlm_u_tlm_tx_vc0_trn_pkts_in_trn28_i_i; + wire com_tlm_u_tlm_tx_vc0_trn_N_13683_i; + wire com_tlm_u_tlm_tx_vc0_trn_N_49500; + wire com_tlm_u_tlm_tx_vc0_trn_released_buf_x_2469; + wire com_tlm_u_tlm_tx_vc0_trn_start_frame_q_2470; + wire com_tlm_u_tlm_tx_vc0_trn_usr_eof_filt_q_4_; + wire com_tlm_u_tlm_tx_vc0_trn_usr_no_eof_err14; + wire com_tlm_u_tlm_tx_vc0_trn_N_31925_i; + wire com_tlm_u_tlm_tx_vc0_trn_N_31923_i; + wire com_tlm_u_tlm_tx_vc0_trn_N_68408_i_2471; + wire com_tlm_u_tlm_tx_vc0_trn_N_31951_i; + wire com_tlm_u_tlm_tx_vc0_trn_N_68407_i_2472; + wire com_tlm_u_tlm_tx_vc0_trn_N_31948_i; + wire com_tlm_u_tlm_tx_vc0_trn_N_68406_i_2473; + wire com_tlm_u_tlm_tx_vc0_trn_N_31945_i; + wire com_tlm_u_tlm_tx_vc0_trn_N_31943_i; + wire com_tlm_u_tlm_tx_vc0_trn_N_31941_i; + wire com_tlm_u_tlm_tx_vc0_trn_N_31939_i; + wire com_tlm_u_tlm_tx_vc0_trn_N_31937_i; + wire com_tlm_u_tlm_tx_vc0_trn_N_31935_i; + wire com_tlm_u_tlm_tx_vc0_trn_N_31933_i; + wire com_tlm_u_tlm_tx_vc0_trn_N_31931_i; + wire com_tlm_u_tlm_tx_vc0_trn_N_31929_i; + wire com_tlm_u_tlm_tx_vc0_trn_N_31927_i; + wire com_tlm_u_tlm_tx_vc0_trn_N_31980_i; + wire com_tlm_u_tlm_tx_vc0_trn_N_31978_i; + wire com_tlm_u_tlm_tx_vc0_trn_N_31976_i; + wire com_tlm_u_tlm_tx_vc0_trn_N_31974_i; + wire com_tlm_u_tlm_tx_vc0_trn_N_31972_i; + wire com_tlm_u_tlm_tx_vc0_trn_N_31970_i; + wire com_tlm_u_tlm_tx_vc0_trn_N_31968_i; + wire com_tlm_u_tlm_tx_vc0_trn_N_31966_i; + wire com_tlm_u_tlm_tx_vc0_trn_N_31964_i; + wire com_tlm_u_tlm_tx_vc0_trn_N_31962_i; + wire com_tlm_u_tlm_tx_vc0_trn_N_31960_i; + wire com_tlm_u_tlm_tx_vc0_trn_N_31958_i; + wire com_tlm_u_tlm_tx_vc0_trn_N_31956_i; + wire com_tlm_u_tlm_tx_vc0_trn_N_68410_i_2474; + wire com_tlm_u_tlm_tx_vc0_trn_N_68409_i_2475; + wire com_tlm_u_tlm_tx_vc0_trn_N_68421_i_2476; + wire com_tlm_u_tlm_tx_vc0_trn_N_31997_i; + wire com_tlm_u_tlm_tx_vc0_trn_N_31995_i; + wire com_tlm_u_tlm_tx_vc0_trn_N_68420_i_2477; + wire com_tlm_u_tlm_tx_vc0_trn_N_68419_i_2478; + wire com_tlm_u_tlm_tx_vc0_trn_N_68418_i_2479; + wire com_tlm_u_tlm_tx_vc0_trn_N_68417_i_2480; + wire com_tlm_u_tlm_tx_vc0_trn_N_68768_i_2481; + wire com_tlm_u_tlm_tx_vc0_trn_N_68416_i_2482; + wire com_tlm_u_tlm_tx_vc0_trn_N_68415_i_2483; + wire com_tlm_u_tlm_tx_vc0_trn_N_68414_i_2484; + wire com_tlm_u_tlm_tx_vc0_trn_N_68413_i_2485; + wire com_tlm_u_tlm_tx_vc0_trn_N_68412_i_2486; + wire com_tlm_u_tlm_tx_vc0_trn_N_68411_i_2487; + wire com_tlm_u_tlm_tx_vc0_trn_N_48002_i; + wire com_tlm_u_tlm_tx_vc0_trn_N_28282_i; + wire com_tlm_u_tlm_tx_vc0_trn_N_32006_i; + wire com_tlm_u_tlm_tx_vc0_trn_N_28280_i; + wire com_tlm_u_tlm_tx_vc0_trn_N_39535_i; + wire com_tlm_u_tlm_tx_vc0_trn_N_28276_i; + wire com_tlm_u_tlm_tx_vc0_trn_N_39533_i; + wire com_tlm_u_tlm_tx_vc0_trn_N_68427_i_2488; + wire com_tlm_u_tlm_tx_vc0_trn_N_32089_i; + wire com_tlm_u_tlm_tx_vc0_trn_N_32087_i; + wire com_tlm_u_tlm_tx_vc0_trn_N_32085_i; + wire com_tlm_u_tlm_tx_vc0_trn_N_68426_i_2489; + wire com_tlm_u_tlm_tx_vc0_trn_N_68425_i_2490; + wire com_tlm_u_tlm_tx_vc0_trn_N_68424_i_2491; + wire com_tlm_u_tlm_tx_vc0_trn_N_68423_i_2492; + wire com_tlm_u_tlm_tx_vc0_trn_N_68422_i_2493; + wire com_tlm_u_tlm_tx_vc0_trn_N_68767_i_2494; + wire com_tlm_u_tlm_tx_vc0_trn_N_32008_i; + wire com_tlm_u_tlm_tx_vc0_trn_load_value10; + wire com_tlm_u_tlm_tx_vc0_trn_N_48897_i; + wire com_tlm_u_tlm_tx_vc0_trn_load_value10_i; + wire com_tlm_u_tlm_tx_vc0_trn_usr_abort_i_2495; + wire com_tlm_u_tlm_tx_vc0_trn_usr_abort_2496; + wire com_tlm_u_tlm_tx_vc0_trn_trn_tdst_dsc; + wire com_tlm_u_tlm_tx_vc0_trn_trn_tdst_rdy; + wire com_tlm_u_tlm_tx_vc0_trn_usr_eof_filt_q_1__2497; + wire com_tlm_u_tlm_tx_vc0_trn_GND_2498; + wire com_tlm_u_tlm_tx_vc0_trn_usr_eof_filt_q_N_6; + wire com_tlm_u_tlm_tx_vc0_trn_un1_trn_tbuf_av_o_1_cry_0_ma_2499; + wire com_tlm_u_tlm_tx_vc0_trn_VCC_2500; + wire com_tlm_u_tlm_tx_vc0_trn_load_value_6__2501; + wire com_tlm_u_tlm_tx_vc0_trn_load_value_0__2502; + wire com_tlm_u_tlm_tx_vc0_trn_load_counter_2503; + wire com_tlm_u_tlm_tx_vc0_trn_un1_pkts_in_trn_1_axb0_2504; + wire com_tlm_u_tlm_tx_vc0_trn_pkts_in_trn28_i_0_0_0_0_32184_2505; + wire com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_un1_usr_d_i_3_cry_0_2506; + wire com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_un1_usr_d_i_3_cry_1_2507; + wire com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_un1_usr_d_i_3_cry_2_2508; + wire com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_GND_2509; + wire com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_un1_usr_d_i_3_cry_3_2510; + wire com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_un1_usr_d_i_3_cry_4_2511; + wire com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_un1_usr_d_i_3_axb_5_2512; + wire com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_usr_credits14_i_2513; + wire com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_usr_dsc_q_2514; + wire com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_usr_cat19_0_0_0_1_2515; + wire com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_N_68765_i_2516; + wire com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_N_68763_i_2517; + wire com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_frame_vld_o14_0_i_i_a2_1_2518; + wire com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_un1_usr_d_i_3_s_5_2519; + wire com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_un1_usr_d_i_3_s_4_2520; + wire com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_un1_usr_d_i_3_s_3_2521; + wire com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_un1_usr_d_i_3_s_2_2522; + wire com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_un1_usr_d_i_3_s_1_2523; + wire com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_un1_usr_d_i_3_s_0_2524; + wire com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_N_48921_i_2525; + wire com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_un1_usr_sof_i_1_i_0_0_m2_0_2526; + wire com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_usr_cat19_0_0_0_3_2527; + wire com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_N_68764_i_2528; + wire com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_cfg_credits_2529; + wire com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_usr_no_payload_2530; + wire com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_cfg_no_payload_2531; + wire com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_N_68968_i_2532; + wire com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_sof_q_2533; + wire com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_no_payload_o_2_i_m2_i_m3_i_m2_i_m3_0_2534; + wire com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_N_9677_i; + wire com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_un1_usr_d_i_3_axb_4_2535; + wire com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_un1_usr_d_i_3_axb_3_2536; + wire com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_un1_usr_d_i_3_axb_2_2537; + wire com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_un1_usr_d_i_3_axb_1_2538; + wire com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_un1_usr_d_i_3_axb_0_2539; + wire com_tlm_u_tlm_tx_vc0_token_fifo_VCC_2540; + wire com_tlm_u_tlm_tx_vc0_token_fifo_tokens_loaded_0_sqmuxa; + wire com_tlm_u_tlm_tx_vc0_token_fifo_fifo_d_6_i_m2_i_m2_0_2__2541; + wire com_tlm_u_tlm_tx_vc0_token_fifo_N_69042_i_2542; + wire com_tlm_u_tlm_tx_vc0_token_fifo_N_35026; + wire com_tlm_u_tlm_tx_vc0_token_fifo_fifo_d_6_i_m2_i_m2_0_0__2543; + wire com_tlm_u_tlm_tx_vc0_token_fifo_N_69041_i_2544; + wire com_tlm_u_tlm_tx_vc0_token_fifo_un1_token_index_axbxc3_2545; + wire com_tlm_u_tlm_tx_vc0_token_fifo_un1_token_index_p4_2546; + wire com_tlm_u_tlm_tx_vc0_token_fifo_un1_token_index_axbxc2_2547; + wire com_tlm_u_tlm_tx_vc0_token_fifo_un1_token_index_axbxc1_2548; + wire com_tlm_u_tlm_tx_vc0_token_fifo_un1_token_index_axbxc0_2549; + wire com_tlm_u_tlm_tx_vc0_token_fifo_tokens_loaded_2550; + wire com_tlm_u_tlm_tx_vc0_token_fifo_t_fifo_GND_2551; + wire com_tlm_u_tlm_tx_vc0_token_fifo_t_fifo_un1_raddr_lo_1_s_1_0; + wire com_tlm_u_tlm_tx_vc0_token_fifo_t_fifo_un1_raddr_lo_1_cry_0_2552; + wire com_tlm_u_tlm_tx_vc0_token_fifo_t_fifo_un1_raddr_lo_1_s_2_0; + wire com_tlm_u_tlm_tx_vc0_token_fifo_t_fifo_un1_raddr_lo_1_cry_1_2553; + wire com_tlm_u_tlm_tx_vc0_token_fifo_t_fifo_un1_raddr_lo_1_s_3_0; + wire com_tlm_u_tlm_tx_vc0_token_fifo_t_fifo_un1_raddr_lo_1_cry_2_2554; + wire com_tlm_u_tlm_tx_vc0_token_fifo_t_fifo_N_68485_i_2555; + wire com_tlm_u_tlm_tx_vc0_token_fifo_t_fifo_un1_bkp_i_1_i_0_0_0_a2_2_2556; + wire com_tlm_u_tlm_tx_vc0_token_fifo_t_fifo_un1_raddr_lo_1_axb_0_2557; + wire com_tlm_u_tlm_tx_vc0_token_fifo_t_fifo_un1_raddr_lo_1_axb_3_2558; + wire com_tlm_u_tlm_tx_vc0_token_fifo_t_fifo_un1_raddr_lo_1_axb_2_2559; + wire com_tlm_u_tlm_tx_vc0_token_fifo_t_fifo_un1_raddr_lo_1_axb_1_2560; + wire com_tlm_u_tlm_tx_vc0_token_fifo_t_fifo_nxt_vld_o_2561; + wire com_tlm_u_tlm_tx_vc0_token_fifo_t_fifo_N_48885_i; + wire com_tlm_u_tlm_tx_vc0_token_fifo_t_fifo_vld_o_2562; + wire com_tlm_u_tlm_tx_vc0_token_fifo_t_fifo_N_48885_i_i_2563; + wire com_tlm_u_tlm_tx_vc0_frm_seq_consumed_nph_2564; + wire com_tlm_u_tlm_tx_vc0_frm_seq_consumed_ph_2565; + wire com_tlm_u_tlm_tx_vc0_frm_seq_consumed_cplh_2566; + wire com_tlm_u_tlm_tx_vc0_frm_seq_GND_2567; + wire com_tlm_u_tlm_tx_vc0_frm_seq_un4_npd_diff_cry_0_2568; + wire com_tlm_u_tlm_tx_vc0_frm_seq_un4_npd_diff_cry_1_2569; + wire com_tlm_u_tlm_tx_vc0_frm_seq_un4_npd_diff_cry_2_2570; + wire com_tlm_u_tlm_tx_vc0_frm_seq_un4_npd_diff_cry_3_2571; + wire com_tlm_u_tlm_tx_vc0_frm_seq_un4_npd_diff_cry_4_2572; + wire com_tlm_u_tlm_tx_vc0_frm_seq_un4_npd_diff_cry_5_2573; + wire com_tlm_u_tlm_tx_vc0_frm_seq_un4_npd_diff_cry_6_2574; + wire com_tlm_u_tlm_tx_vc0_frm_seq_un4_npd_diff_cry_7_2575; + wire com_tlm_u_tlm_tx_vc0_frm_seq_un4_npd_diff_cry_8_2576; + wire com_tlm_u_tlm_tx_vc0_frm_seq_un4_npd_diff_cry_9_2577; + wire com_tlm_u_tlm_tx_vc0_frm_seq_un4_npd_diff_s_11_2578; + wire com_tlm_u_tlm_tx_vc0_frm_seq_un4_npd_diff_cry_10_2579; + wire com_tlm_u_tlm_tx_vc0_frm_seq_un4_cpld_diff_cry_0_2580; + wire com_tlm_u_tlm_tx_vc0_frm_seq_un4_cpld_diff_cry_1_2581; + wire com_tlm_u_tlm_tx_vc0_frm_seq_un4_cpld_diff_cry_2_2582; + wire com_tlm_u_tlm_tx_vc0_frm_seq_un4_cpld_diff_cry_3_2583; + wire com_tlm_u_tlm_tx_vc0_frm_seq_un4_cpld_diff_cry_4_2584; + wire com_tlm_u_tlm_tx_vc0_frm_seq_un4_cpld_diff_cry_5_2585; + wire com_tlm_u_tlm_tx_vc0_frm_seq_un4_cpld_diff_cry_6_2586; + wire com_tlm_u_tlm_tx_vc0_frm_seq_un4_cpld_diff_cry_7_2587; + wire com_tlm_u_tlm_tx_vc0_frm_seq_un4_cpld_diff_cry_8_2588; + wire com_tlm_u_tlm_tx_vc0_frm_seq_un4_cpld_diff_cry_9_2589; + wire com_tlm_u_tlm_tx_vc0_frm_seq_un4_cpld_diff_s_11_2590; + wire com_tlm_u_tlm_tx_vc0_frm_seq_un4_cpld_diff_cry_10_2591; + wire com_tlm_u_tlm_tx_vc0_frm_seq_un4_bnpd_diff_cry_0_2592; + wire com_tlm_u_tlm_tx_vc0_frm_seq_un4_bnpd_diff_cry_1_2593; + wire com_tlm_u_tlm_tx_vc0_frm_seq_un4_bnpd_diff_cry_2_2594; + wire com_tlm_u_tlm_tx_vc0_frm_seq_un4_bnpd_diff_cry_3_2595; + wire com_tlm_u_tlm_tx_vc0_frm_seq_un4_bnpd_diff_cry_4_2596; + wire com_tlm_u_tlm_tx_vc0_frm_seq_un4_bnpd_diff_cry_5_2597; + wire com_tlm_u_tlm_tx_vc0_frm_seq_un4_bnpd_diff_cry_6_2598; + wire com_tlm_u_tlm_tx_vc0_frm_seq_un4_bnpd_diff_cry_7_2599; + wire com_tlm_u_tlm_tx_vc0_frm_seq_un4_bnpd_diff_cry_8_2600; + wire com_tlm_u_tlm_tx_vc0_frm_seq_un4_bnpd_diff_cry_9_2601; + wire com_tlm_u_tlm_tx_vc0_frm_seq_un4_bnpd_diff_s_11_2602; + wire com_tlm_u_tlm_tx_vc0_frm_seq_un4_bnpd_diff_cry_10_2603; + wire com_tlm_u_tlm_tx_vc0_frm_seq_un4_pd_diff_cry_0_2604; + wire com_tlm_u_tlm_tx_vc0_frm_seq_un4_pd_diff_cry_1_2605; + wire com_tlm_u_tlm_tx_vc0_frm_seq_un4_pd_diff_cry_2_2606; + wire com_tlm_u_tlm_tx_vc0_frm_seq_un4_pd_diff_cry_3_2607; + wire com_tlm_u_tlm_tx_vc0_frm_seq_un4_pd_diff_cry_4_2608; + wire com_tlm_u_tlm_tx_vc0_frm_seq_un4_pd_diff_cry_5_2609; + wire com_tlm_u_tlm_tx_vc0_frm_seq_un4_pd_diff_cry_6_2610; + wire com_tlm_u_tlm_tx_vc0_frm_seq_un4_pd_diff_cry_7_2611; + wire com_tlm_u_tlm_tx_vc0_frm_seq_un4_pd_diff_cry_8_2612; + wire com_tlm_u_tlm_tx_vc0_frm_seq_un4_pd_diff_cry_9_2613; + wire com_tlm_u_tlm_tx_vc0_frm_seq_VCC_2614; + wire com_tlm_u_tlm_tx_vc0_frm_seq_un4_pd_diff_s_11_2615; + wire com_tlm_u_tlm_tx_vc0_frm_seq_un4_pd_diff_cry_10_2616; + wire com_tlm_u_tlm_tx_vc0_frm_seq_oq_vld; + wire com_tlm_u_tlm_tx_vc0_frm_seq_oq_ren_2617; + wire com_tlm_u_tlm_tx_vc0_frm_seq_bq_holdoff13; + wire com_tlm_u_tlm_tx_vc0_frm_seq_cplh_av; + wire com_tlm_u_tlm_tx_vc0_frm_seq_header_vld_bq_2618; + wire com_tlm_u_tlm_tx_vc0_frm_seq_bq_no_payload_qq_2619; + wire com_tlm_u_tlm_tx_vc0_frm_seq_bq_ren_2620; + wire com_tlm_u_tlm_tx_vc0_frm_seq_bq_holdoff_2621; + wire com_tlm_u_tlm_tx_vc0_frm_seq_bq_wen_2622; + wire com_tlm_u_tlm_tx_vc0_frm_seq_N_51066; + wire com_tlm_u_tlm_tx_vc0_frm_seq_ph_av; + wire com_tlm_u_tlm_tx_vc0_frm_seq_start_src_rdy; + wire com_tlm_u_tlm_tx_vc0_frm_seq_oq_no_payload_qq_2623; + wire com_tlm_u_tlm_tx_vc0_frm_seq_header_vld_oq_2624; + wire com_tlm_u_tlm_tx_vc0_frm_seq_N_51067; + wire com_tlm_u_tlm_tx_vc0_frm_seq_N_48967_i; + wire com_tlm_u_tlm_tx_vc0_frm_seq_nonposted_vld_oq_2625; + wire com_tlm_u_tlm_tx_vc0_frm_seq_bq_renc_i; + wire com_tlm_u_tlm_tx_vc0_frm_seq_last_buf_num_match_3; + wire com_tlm_u_tlm_tx_vc0_frm_seq_last_buf_num_match_3_NE_0_2626; + wire com_tlm_u_tlm_tx_vc0_frm_seq_last_buf_num_match_3_0_2627; + wire com_tlm_u_tlm_tx_vc0_frm_seq_header_vld_bq_3; + wire com_tlm_u_tlm_tx_vc0_frm_seq_nph_av; + wire com_tlm_u_tlm_tx_vc0_frm_seq_bq_vld; + wire com_tlm_u_tlm_tx_vc0_frm_seq_av_valid; + wire com_tlm_u_tlm_tx_vc0_frm_seq_nonposted_vld_oq_3; + wire com_tlm_u_tlm_tx_vc0_frm_seq_un4_cpld_diff_s_11_sf_2628; + wire com_tlm_u_tlm_tx_vc0_frm_seq_cpld_av_11_; + wire com_tlm_u_tlm_tx_vc0_frm_seq_un4_npd_diff_s_11_sf_2629; + wire com_tlm_u_tlm_tx_vc0_frm_seq_un4_pd_diff_s_11_sf_2630; + wire com_tlm_u_tlm_tx_vc0_frm_seq_pd_av_11_; + wire com_tlm_u_tlm_tx_vc0_frm_seq_un4_bnpd_diff_s_11_sf_2631; + wire com_tlm_u_tlm_tx_vc0_frm_seq_N_13932_i; + wire com_tlm_u_tlm_tx_vc0_frm_seq_nonposted_vld_oq_3_1; + wire com_tlm_u_tlm_tx_vc0_frm_seq_header_vld_oq_7_u_i_0_0_32086_2632; + wire com_tlm_u_tlm_tx_vc0_frm_seq_N_49531; + wire com_tlm_u_tlm_tx_vc0_frm_seq_N_49528; + wire com_tlm_u_tlm_tx_vc0_frm_seq_N_42589_i_2633; + wire com_tlm_u_tlm_tx_vc0_frm_seq_nxt_seq_state_0_sqmuxa_1; + wire com_tlm_u_tlm_tx_vc0_frm_seq_nxt_seq_state_0_sqmuxa_2; + wire com_tlm_u_tlm_tx_vc0_frm_seq_sq_vld; + wire com_tlm_u_tlm_tx_vc0_frm_seq_N_17156_i; + wire com_tlm_u_tlm_tx_vc0_frm_seq_N_42588; + wire com_tlm_u_tlm_tx_vc0_frm_seq_N_17291; + wire com_tlm_u_tlm_tx_vc0_frm_seq_N_48356_i; + wire com_tlm_u_tlm_tx_vc0_frm_seq_N_48358_i; + wire com_tlm_u_tlm_tx_vc0_frm_seq_consumed_cplh_10_i_i_a2_i_1; + wire com_tlm_u_tlm_tx_vc0_frm_seq_N_67885_i_2634; + wire com_tlm_u_tlm_tx_vc0_frm_seq_nxt_queue_state_1_sqmuxa_1_1; + wire com_tlm_u_tlm_tx_vc0_frm_seq_N_38459; + wire com_tlm_u_tlm_tx_vc0_frm_seq_N_38458; + wire com_tlm_u_tlm_tx_vc0_frm_seq_N_8943_i; + wire com_tlm_u_tlm_tx_vc0_frm_seq_sq_nxt_vld; + wire com_tlm_u_tlm_tx_vc0_frm_seq_N_40766_i; + wire com_tlm_u_tlm_tx_vc0_frm_seq_last_buf_num_match_2635; + wire com_tlm_u_tlm_tx_vc0_frm_seq_N_13930_i; + wire com_tlm_u_tlm_tx_vc0_frm_seq_bq_wen_14_u_i_0_0_0; + wire com_tlm_u_tlm_tx_vc0_frm_seq_N_48937_i; + wire com_tlm_u_tlm_tx_vc0_frm_seq_N_48333_i; + wire com_tlm_u_tlm_tx_vc0_frm_seq_N_49115_i; + wire com_tlm_u_tlm_tx_vc0_frm_seq_N_8842_i; + wire com_tlm_u_tlm_tx_vc0_frm_seq_oq_ren_12_iv_0_0_0_0; + wire com_tlm_u_tlm_tx_vc0_frm_seq_bq_rdy_2636; + wire com_tlm_u_tlm_tx_vc0_frm_seq_oq_rdy_u_i_i_a2_2637; + wire com_tlm_u_tlm_tx_vc0_frm_seq_N_48914_i; + wire com_tlm_u_tlm_tx_vc0_frm_seq_N_41839_i_i_2638; + wire com_tlm_u_tlm_tx_vc0_frm_seq_N_51001_i_i_2639; + wire com_tlm_u_tlm_tx_vc0_frm_seq_N_51001_i; + wire com_tlm_u_tlm_tx_vc0_frm_seq_nxt_queue_state_1_sqmuxa_1; + wire com_tlm_u_tlm_tx_vc0_frm_seq_sq_wen_2640; + wire com_tlm_u_tlm_tx_vc0_frm_seq_un4_pd_diff_axb_5_2641; + wire com_tlm_u_tlm_tx_vc0_frm_seq_pd_av_5_; + wire com_tlm_u_tlm_tx_vc0_frm_seq_un4_pd_diff_axb_4_2642; + wire com_tlm_u_tlm_tx_vc0_frm_seq_pd_av_4_; + wire com_tlm_u_tlm_tx_vc0_frm_seq_un4_pd_diff_axb_3_2643; + wire com_tlm_u_tlm_tx_vc0_frm_seq_pd_av_3_; + wire com_tlm_u_tlm_tx_vc0_frm_seq_un4_pd_diff_axb_2_2644; + wire com_tlm_u_tlm_tx_vc0_frm_seq_pd_av_2_; + wire com_tlm_u_tlm_tx_vc0_frm_seq_un4_pd_diff_axb_1_2645; + wire com_tlm_u_tlm_tx_vc0_frm_seq_pd_av_1_; + wire com_tlm_u_tlm_tx_vc0_frm_seq_un4_pd_diff_axb_0_2646; + wire com_tlm_u_tlm_tx_vc0_frm_seq_pd_av_0_; + wire com_tlm_u_tlm_tx_vc0_frm_seq_un4_bnpd_diff_cry_10_sf_2647; + wire com_tlm_u_tlm_tx_vc0_frm_seq_un4_bnpd_diff_cry_9_sf_2648; + wire com_tlm_u_tlm_tx_vc0_frm_seq_un4_bnpd_diff_cry_8_sf_2649; + wire com_tlm_u_tlm_tx_vc0_frm_seq_un4_bnpd_diff_cry_7_sf_2650; + wire com_tlm_u_tlm_tx_vc0_frm_seq_un4_bnpd_diff_cry_6_sf_2651; + wire com_tlm_u_tlm_tx_vc0_frm_seq_un4_bnpd_diff_axb_5_2652; + wire com_tlm_u_tlm_tx_vc0_frm_seq_un4_bnpd_diff_axb_4_2653; + wire com_tlm_u_tlm_tx_vc0_frm_seq_un4_bnpd_diff_axb_3_2654; + wire com_tlm_u_tlm_tx_vc0_frm_seq_un4_bnpd_diff_axb_2_2655; + wire com_tlm_u_tlm_tx_vc0_frm_seq_un4_bnpd_diff_axb_1_2656; + wire com_tlm_u_tlm_tx_vc0_frm_seq_un4_bnpd_diff_axb_0_2657; + wire com_tlm_u_tlm_tx_vc0_frm_seq_un4_cpld_diff_axb_5_2658; + wire com_tlm_u_tlm_tx_vc0_frm_seq_cpld_av_5_; + wire com_tlm_u_tlm_tx_vc0_frm_seq_un4_cpld_diff_axb_4_2659; + wire com_tlm_u_tlm_tx_vc0_frm_seq_cpld_av_4_; + wire com_tlm_u_tlm_tx_vc0_frm_seq_un4_cpld_diff_axb_3_2660; + wire com_tlm_u_tlm_tx_vc0_frm_seq_cpld_av_3_; + wire com_tlm_u_tlm_tx_vc0_frm_seq_un4_cpld_diff_axb_2_2661; + wire com_tlm_u_tlm_tx_vc0_frm_seq_cpld_av_2_; + wire com_tlm_u_tlm_tx_vc0_frm_seq_un4_cpld_diff_axb_1_2662; + wire com_tlm_u_tlm_tx_vc0_frm_seq_cpld_av_1_; + wire com_tlm_u_tlm_tx_vc0_frm_seq_un4_cpld_diff_axb_0_2663; + wire com_tlm_u_tlm_tx_vc0_frm_seq_cpld_av_0_; + wire com_tlm_u_tlm_tx_vc0_frm_seq_un4_npd_diff_axb_5_2664; + wire com_tlm_u_tlm_tx_vc0_frm_seq_un4_npd_diff_axb_4_2665; + wire com_tlm_u_tlm_tx_vc0_frm_seq_un4_npd_diff_axb_3_2666; + wire com_tlm_u_tlm_tx_vc0_frm_seq_un4_npd_diff_axb_2_2667; + wire com_tlm_u_tlm_tx_vc0_frm_seq_un4_npd_diff_axb_1_2668; + wire com_tlm_u_tlm_tx_vc0_frm_seq_un4_npd_diff_axb_0_2669; + wire com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_GND_2670; + wire com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_un1_raddr_lo_1_s_1_1; + wire com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_un1_raddr_lo_1_cry_0_2671; + wire com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_un1_raddr_lo_1_s_2_1; + wire com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_un1_raddr_lo_1_cry_1_2672; + wire com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_un1_raddr_lo_1_s_3_1; + wire com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_un1_raddr_lo_1_cry_2_2673; + wire com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_un1_raddr_lo_1_axb_0_2674; + wire com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_N_68484_i_2675; + wire com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_un1_bkp_i_1_i_0_0_0_a2_0_2_2676; + wire com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_srl_wen; + wire com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_N_50019_i_2677; + wire com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_un1_raddr_lo_1_axb_3_2678; + wire com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_un1_raddr_lo_1_axb_2_2679; + wire com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_un1_raddr_lo_1_axb_1_2680; + wire com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_nxt_vld_o_1; + wire com_tlm_u_tlm_tx_vc0_frm_seq_bq_fifo_GND_2681; + wire com_tlm_u_tlm_tx_vc0_frm_seq_bq_fifo_un1_raddr_lo_1_s_1_2; + wire com_tlm_u_tlm_tx_vc0_frm_seq_bq_fifo_un1_raddr_lo_1_cry_0_2682; + wire com_tlm_u_tlm_tx_vc0_frm_seq_bq_fifo_un1_raddr_lo_1_s_2_2; + wire com_tlm_u_tlm_tx_vc0_frm_seq_bq_fifo_un1_raddr_lo_1_cry_1_2683; + wire com_tlm_u_tlm_tx_vc0_frm_seq_bq_fifo_un1_raddr_lo_1_s_3_2; + wire com_tlm_u_tlm_tx_vc0_frm_seq_bq_fifo_un1_raddr_lo_1_cry_2_2684; + wire com_tlm_u_tlm_tx_vc0_frm_seq_bq_fifo_N_69265_i_2685; + wire com_tlm_u_tlm_tx_vc0_frm_seq_bq_fifo_un1_bkp_i_1_i_0_0_0_0_a2_2_2686; + wire com_tlm_u_tlm_tx_vc0_frm_seq_bq_fifo_un1_raddr_lo_1_axb_0_2687; + wire com_tlm_u_tlm_tx_vc0_frm_seq_bq_fifo_un1_raddr_lo_1_axb_3_2688; + wire com_tlm_u_tlm_tx_vc0_frm_seq_bq_fifo_un1_raddr_lo_1_axb_2_2689; + wire com_tlm_u_tlm_tx_vc0_frm_seq_bq_fifo_un1_raddr_lo_1_axb_1_2690; + wire com_tlm_u_tlm_tx_vc0_frm_seq_bq_fifo_nxt_vld_o_0; + wire com_tlm_u_tlm_tx_vc0_frm_seq_bq_fifo_N_48886_i; + wire com_tlm_u_tlm_tx_vc0_frm_seq_bq_fifo_N_48886_i_i_2691; + wire com_tlm_u_tlm_tx_vc0_frm_seq_sq_fifo_GND_2692; + wire com_tlm_u_tlm_tx_vc0_frm_seq_sq_fifo_un1_raddr_lo_1_s_1_3; + wire com_tlm_u_tlm_tx_vc0_frm_seq_sq_fifo_un1_raddr_lo_1_cry_0_2693; + wire com_tlm_u_tlm_tx_vc0_frm_seq_sq_fifo_un1_raddr_lo_1_s_2_3; + wire com_tlm_u_tlm_tx_vc0_frm_seq_sq_fifo_un1_raddr_lo_1_cry_1_2694; + wire com_tlm_u_tlm_tx_vc0_frm_seq_sq_fifo_un1_raddr_lo_1_s_3_3; + wire com_tlm_u_tlm_tx_vc0_frm_seq_sq_fifo_un1_raddr_lo_1_cry_2_2695; + wire com_tlm_u_tlm_tx_vc0_frm_seq_sq_fifo_un1_raddr_lo_1_axb_0_2696; + wire com_tlm_u_tlm_tx_vc0_frm_seq_sq_fifo_N_69199_i_2697; + wire com_tlm_u_tlm_tx_vc0_frm_seq_sq_fifo_un1_bkp_i_1_i_0_0_a2_0_2_2698; + wire com_tlm_u_tlm_tx_vc0_frm_seq_sq_fifo_srl_wen; + wire com_tlm_u_tlm_tx_vc0_frm_seq_sq_fifo_N_38461_i_2699; + wire com_tlm_u_tlm_tx_vc0_frm_seq_sq_fifo_un1_ct_o_axbxc2_2700; + wire com_tlm_u_tlm_tx_vc0_frm_seq_sq_fifo_un1_ct_o_p4_2701; + wire com_tlm_u_tlm_tx_vc0_frm_seq_sq_fifo_un1_ct_o_axbxc1_2702; + wire com_tlm_u_tlm_tx_vc0_frm_seq_sq_fifo_un1_ct_o_axb0_2703; + wire com_tlm_u_tlm_tx_vc0_frm_seq_sq_fifo_N_41841_i; + wire com_tlm_u_tlm_tx_vc0_frm_seq_sq_fifo_un1_raddr_lo_1_axb_3_2704; + wire com_tlm_u_tlm_tx_vc0_frm_seq_sq_fifo_un1_raddr_lo_1_axb_2_2705; + wire com_tlm_u_tlm_tx_vc0_frm_seq_sq_fifo_un1_raddr_lo_1_axb_1_2706; + wire com_tlm_u_tlm_tx_vc0_frm_seq_sq_fifo_N_41745_i_i_2707; + wire com_tlm_u_tlm_tx_vc0_frm_seq_sq_fifo_N_41745_i; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un7_credits_ok_cry_0_2708; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un7_credits_ok_cry_1_2709; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un7_credits_ok_cry_2_2710; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un7_credits_ok_cry_3_2711; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un7_credits_ok_cry_4_2712; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un7_credits_ok_cry_5_2713; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un7_credits_ok_cry_6_2714; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un7_credits_ok_cry_7_2715; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un7_credits_ok_cry_8_2716; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un7_credits_ok_cry_9_2717; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un7_credits_ok_cry_10_2718; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_fc_diff_header_cry_0_2719; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_fc_diff_header_cry_1_2720; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_fc_diff_header_cry_2_2721; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_fc_diff_header_cry_3_2722; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_fc_diff_header_cry_4_2723; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_fc_diff_header_cry_5_2724; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_fc_diff_header_cry_6_2725; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_PD_1_cry_0_0_2726; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_PD_1_cry_1_0_2727; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_PD_1_s_1_2728; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_PD_1_cry_0_2729; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_PD_1_cry_2_0_2730; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_PD_1_s_2_2731; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_PD_1_cry_1_2732; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_PD_1_cry_3_0_2733; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_PD_1_s_3_2734; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_PD_1_cry_2_2735; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_PD_1_cry_4_0_2736; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_PD_1_s_4_2737; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_PD_1_cry_3_2738; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_PD_1_cry_5_0_2739; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_PD_1_s_5_2740; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_PD_1_cry_4_2741; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_PD_1_s_6_2742; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_PD_1_cry_5_2743; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_PD_1_s_7_2744; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_PD_1_cry_6_2745; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_PD_1_s_8_2746; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_PD_1_cry_7_2747; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_PD_1_s_9_2748; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_PD_1_cry_8_2749; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_PD_1_s_10_2750; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_PD_1_cry_9_2751; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_PD_1_s_11_2752; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_PD_1_cry_10_2753; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_NPD_1_cry_0_0_2754; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_NPD_1_cry_1_0_2755; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_NPD_1_s_1_2756; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_NPD_1_cry_0_2757; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_NPD_1_cry_2_0_2758; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_NPD_1_s_2_2759; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_NPD_1_cry_1_2760; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_NPD_1_cry_3_0_2761; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_NPD_1_s_3_2762; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_NPD_1_cry_2_2763; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_NPD_1_cry_4_0_2764; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_NPD_1_s_4_2765; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_NPD_1_cry_3_2766; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_NPD_1_cry_5_0_2767; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_NPD_1_s_5_2768; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_NPD_1_cry_4_2769; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_NPD_1_s_6_2770; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_NPD_1_cry_5_2771; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_NPD_1_s_7_2772; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_NPD_1_cry_6_2773; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_NPD_1_s_8_2774; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_NPD_1_cry_7_2775; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_NPD_1_s_9_2776; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_NPD_1_cry_8_2777; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_NPD_1_s_10_2778; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_NPD_1_cry_9_2779; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_NPD_1_s_11_2780; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_NPD_1_cry_10_2781; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_CPLD_1_cry_0_0_2782; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_CPLD_1_cry_1_0_2783; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_CPLD_1_s_1_2784; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_CPLD_1_cry_0_2785; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_CPLD_1_cry_2_0_2786; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_CPLD_1_s_2_2787; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_CPLD_1_cry_1_2788; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_CPLD_1_cry_3_0_2789; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_CPLD_1_s_3_2790; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_CPLD_1_cry_2_2791; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_CPLD_1_cry_4_0_2792; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_CPLD_1_s_4_2793; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_CPLD_1_cry_3_2794; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_CPLD_1_cry_5_0_2795; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_CPLD_1_s_5_2796; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_CPLD_1_cry_4_2797; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_CPLD_1_s_6_2798; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_CPLD_1_cry_5_2799; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_CPLD_1_s_7_2800; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_CPLD_1_cry_6_2801; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_CPLD_1_s_8_2802; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_CPLD_1_cry_7_2803; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_CPLD_1_s_9_2804; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_CPLD_1_cry_8_2805; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_CPLD_1_s_10_2806; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_CPLD_1_cry_9_2807; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_CPLD_1_s_11_2808; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_CPLD_1_cry_10_2809; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_VCC_2810; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_fc_diff_data_cry_0_2811; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_fc_diff_data_cry_1_2812; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_fc_diff_data_cry_2_2813; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_fc_diff_data_cry_3_2814; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_fc_diff_data_cry_4_2815; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_fc_diff_data_cry_5_2816; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_fc_diff_data_cry_6_2817; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_fc_diff_data_cry_7_2818; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_fc_diff_data_cry_8_2819; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_fc_diff_data_cry_9_2820; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_fc_diff_data_cry_10_2821; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_GND_2822; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_cpld_av_o_6_cry_0_0_2823; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_cpld_av_o_6_cry_1_0_2824; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_cpld_av_o_6_cry_0_2825; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_cpld_av_o_6_cry_2_0_2826; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_cpld_av_o_6_cry_1_2827; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_cpld_av_o_6_cry_3_0_2828; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_cpld_av_o_6_cry_2_2829; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_cpld_av_o_6_cry_4_0_2830; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_cpld_av_o_6_cry_3_2831; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_cpld_av_o_6_cry_5_0_2832; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_cpld_av_o_6_cry_4_2833; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_cpld_av_o_6_cry_6_0_2834; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_cpld_av_o_6_cry_5_2835; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_cpld_av_o_6_cry_7_0_2836; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_cpld_av_o_6_cry_6_2837; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_cpld_av_o_6_cry_8_0_2838; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_cpld_av_o_6_cry_7_2839; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_cpld_av_o_6_cry_9_0_2840; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_cpld_av_o_6_cry_8_2841; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_cpld_av_o_6_cry_10_0_2842; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_cpld_av_o_6_cry_9_2843; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_cpld_av_o_6_cry_10_2844; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_npd_av_o_6_cry_0_0_2845; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_npd_av_o_6_cry_1_0_2846; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_npd_av_o_6_cry_0_2847; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_npd_av_o_6_cry_2_0_2848; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_npd_av_o_6_cry_1_2849; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_npd_av_o_6_cry_3_0_2850; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_npd_av_o_6_cry_2_2851; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_npd_av_o_6_cry_4_0_2852; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_npd_av_o_6_cry_3_2853; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_npd_av_o_6_cry_5_0_2854; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_npd_av_o_6_cry_4_2855; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_npd_av_o_6_cry_6_0_2856; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_npd_av_o_6_cry_5_2857; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_npd_av_o_6_cry_7_0_2858; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_npd_av_o_6_cry_6_2859; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_npd_av_o_6_cry_8_0_2860; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_npd_av_o_6_cry_7_2861; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_npd_av_o_6_cry_9_0_2862; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_npd_av_o_6_cry_8_2863; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_npd_av_o_6_cry_10_0_2864; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_npd_av_o_6_cry_9_2865; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_npd_av_o_6_cry_10_2866; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_pd_av_o_6_cry_0_0_2867; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_pd_av_o_6_cry_1_0_2868; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_pd_av_o_6_cry_0_2869; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_pd_av_o_6_cry_2_0_2870; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_pd_av_o_6_cry_1_2871; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_pd_av_o_6_cry_3_0_2872; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_pd_av_o_6_cry_2_2873; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_pd_av_o_6_cry_4_0_2874; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_pd_av_o_6_cry_3_2875; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_pd_av_o_6_cry_5_0_2876; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_pd_av_o_6_cry_4_2877; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_pd_av_o_6_cry_6_0_2878; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_pd_av_o_6_cry_5_2879; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_pd_av_o_6_cry_7_0_2880; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_pd_av_o_6_cry_6_2881; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_pd_av_o_6_cry_8_0_2882; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_pd_av_o_6_cry_7_2883; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_pd_av_o_6_cry_9_0_2884; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_pd_av_o_6_cry_8_2885; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_pd_av_o_6_cry_10_0_2886; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_pd_av_o_6_cry_9_2887; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_pd_av_o_6_cry_10_2888; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_PD_1_axb_0_2889; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_NPD_1_axb_0_2890; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_CPLD_1_axb_0_2891; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_init_cplc_2892; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_init_npc_2893; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_init_pc_2894; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_init_vld_q_2895; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_infinite_NPH_2896; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_infinite_PH_2897; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_new_limit_data_ok; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_nph_av_o_6_3_2898; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_ph_av_o_6_3_2899; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_infinite_CPLH_3_2900; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_N_69425_i_2901; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_update_p_2902; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_init_p_2903; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_N_69426_i_2904; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_update_np_2905; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_init_np_2906; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_N_69427_i_2907; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_update_cpl_2908; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_init_cpl_2909; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_N_57213_i_2910; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_infinite_header_q_2_0_a2_4_2911; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_infinite_header_q_2_0_a2_0_2912; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_infinite_data_q_2_0_a2_8_2913; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_infinite_data_q_2_0_a2_7_2914; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_infinite_data_q_2_0_a2_6_2915; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_infinite_data_q_5_0_0_2916; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_fc_diff_data_axb_11_2917; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_fc_diff_header_axb_7_2918; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_infinite_CPLH_2919; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_infinite_header_q_5_0_0_2920; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_N_13857_i_2921; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_suspend_rdy_o_3_2922; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_update_cpl_3; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_update_np_3; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_update_p_3; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_update_vld_q_2923; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_av_valid_o_4; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_q_2924; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_err_fc_o13; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_update_vld_qq_2925; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_init_vld_qq_2926; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_new_limit_header_ok_3_0_a2_2927; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_N_8620_i_2928; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_infinite_CPLH_4_2929; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_infinite_CPLH_2_2930; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_infinite_CPLH_1_2931; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_infinite_CPLH_0_2932; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_N_8622_i_2933; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_nph_av_o_6_4_2934; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_nph_av_o_6_2_2935; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_nph_av_o_6_1_2936; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_nph_av_o_6_0_2937; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_N_8621_i_2938; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_ph_av_o_6_4_2939; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_ph_av_o_6_2_2940; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_ph_av_o_6_1_2941; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_ph_av_o_6_0_2942; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_N_43791_i; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_N_43789_i; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_N_43787_i; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_N_43785_i; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_N_43783_i; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_N_43781_i; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_N_43779_i; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_N_43777_i; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_N_43775_i; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_N_43773_i; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_N_43771_i; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_N_43769_i; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_N_50493; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_N_68153_i_2943; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_av_hdr_cred_7_iv_i_0_0_0_2944; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un8_suspend_cat_axbxc1_2945; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un7_credits_ok_cry_11_2946; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_av_hdr_cred_2947; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_CPLD_1_axb_11_2948; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_CPLD_1_axb_10_2949; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_CPLD_1_axb_9_2950; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_CPLD_1_axb_8_2951; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_CPLD_1_axb_7_2952; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_CPLD_1_axb_6_2953; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_CPLD_1_axb_5_2954; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_CPLD_1_axb_4_2955; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_CPLD_1_axb_3_2956; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_CPLD_1_axb_2_2957; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_CPLD_1_axb_1_2958; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_NPD_1_axb_11_2959; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_NPD_1_axb_10_2960; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_NPD_1_axb_9_2961; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_NPD_1_axb_8_2962; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_NPD_1_axb_7_2963; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_NPD_1_axb_6_2964; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_NPD_1_axb_5_2965; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_NPD_1_axb_4_2966; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_NPD_1_axb_3_2967; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_NPD_1_axb_2_2968; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_NPD_1_axb_1_2969; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_PD_1_axb_11_2970; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_PD_1_axb_10_2971; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_PD_1_axb_9_2972; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_PD_1_axb_8_2973; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_PD_1_axb_7_2974; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_PD_1_axb_6_2975; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_PD_1_axb_5_2976; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_PD_1_axb_4_2977; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_PD_1_axb_3_2978; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_PD_1_axb_2_2979; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_PD_1_axb_1_2980; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_cpld_av_o_6_axb_10_2981; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_cpld_av_o_6_axb_9_2982; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_cpld_av_o_6_axb_8_2983; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_cpld_av_o_6_axb_7_2984; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_cpld_av_o_6_axb_6_2985; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_cpld_av_o_6_axb_5_2986; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_cpld_av_o_6_axb_4_2987; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_cpld_av_o_6_axb_3_2988; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_cpld_av_o_6_axb_2_2989; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_cpld_av_o_6_axb_1_2990; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_cpld_av_o_6_axb_0_2991; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_npd_av_o_6_axb_10_2992; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_npd_av_o_6_axb_9_2993; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_npd_av_o_6_axb_8_2994; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_npd_av_o_6_axb_7_2995; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_npd_av_o_6_axb_6_2996; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_npd_av_o_6_axb_5_2997; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_npd_av_o_6_axb_4_2998; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_npd_av_o_6_axb_3_2999; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_npd_av_o_6_axb_2_3000; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_npd_av_o_6_axb_1_3001; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_npd_av_o_6_axb_0_3002; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_pd_av_o_6_axb_10_3003; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_pd_av_o_6_axb_9_3004; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_pd_av_o_6_axb_8_3005; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_pd_av_o_6_axb_7_3006; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_pd_av_o_6_axb_6_3007; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_pd_av_o_6_axb_5_3008; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_pd_av_o_6_axb_4_3009; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_pd_av_o_6_axb_3_3010; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_pd_av_o_6_axb_2_3011; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_pd_av_o_6_axb_1_3012; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_pd_av_o_6_axb_0_3013; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_N_43656_i; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_infinite_header_q_2; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_infinite_data_q_2; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_infinite_data_q_5; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_infinite_header_q_3014; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_infinite_header_qq_3015; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_infinite_data_q_3016; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_infinite_data_qq_3017; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_infinite_header_qq_3018; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_infinite_data_q_3019; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_infinite_data_qq_3020; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_infinite_header_q_5; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_infinite_header_q_3021; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_infinite_CPLD_i_3022; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_infinite_NPD_i_3023; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_infinite_PD_i_3024; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_cpld_av_o_6_axb_11_3025; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_infinite_CPLD_3026; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_npd_av_o_6_axb_11_3027; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_infinite_NPD_3028; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_pd_av_o_6_axb_11_3029; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_infinite_PD_3030; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_fc_diff_data_axb_10_3031; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_fc_diff_data_axb_9_3032; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_fc_diff_data_axb_8_3033; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_fc_diff_data_axb_7_3034; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_fc_diff_data_axb_6_3035; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_fc_diff_data_axb_5_3036; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_fc_diff_data_axb_4_3037; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_fc_diff_data_axb_3_3038; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_fc_diff_data_axb_2_3039; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_fc_diff_data_axb_1_3040; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_fc_diff_data_axb_0_3041; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_fc_diff_header_axb_6_3042; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_fc_diff_header_axb_5_3043; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_fc_diff_header_axb_4_3044; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_fc_diff_header_axb_3_3045; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_fc_diff_header_axb_2_3046; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_fc_diff_header_axb_1_3047; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_fc_diff_header_axb_0_3048; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_av_data_cred_i_11__3049; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_av_data_cred_i_10__3050; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_av_data_cred_i_9__3051; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_av_data_cred_i_8__3052; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_av_data_cred_i_7__3053; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_av_data_cred_i_6__3054; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un7_credits_ok_axb_5_i_3055; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un7_credits_ok_axb_4_i_3056; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un7_credits_ok_axb_3_i_3057; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_av_data_cred_i_2__3058; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_av_data_cred_i_1__3059; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un7_credits_ok_axb_0_i_3060; + wire com_tlm_u_tlm_tx_pm_ctrl_GND_3061; + wire com_tlm_u_tlm_tx_pm_ctrl_un1_cfg_ct_s_1_3062; + wire com_tlm_u_tlm_tx_pm_ctrl_un1_cfg_ct_cry_0_3063; + wire com_tlm_u_tlm_tx_pm_ctrl_un1_cfg_ct_s_2_3064; + wire com_tlm_u_tlm_tx_pm_ctrl_un1_cfg_ct_cry_1_3065; + wire com_tlm_u_tlm_tx_pm_ctrl_un1_cfg_ct_s_3_3066; + wire com_tlm_u_tlm_tx_pm_ctrl_un1_cfg_ct_cry_2_3067; + wire com_tlm_u_tlm_tx_pm_ctrl_un1_cfg_ct_s_4_3068; + wire com_tlm_u_tlm_tx_pm_ctrl_un1_cfg_ct_cry_3_3069; + wire com_tlm_u_tlm_tx_pm_ctrl_un1_cfg_ct_axb_0_3070; + wire com_tlm_u_tlm_tx_pm_ctrl_ppm_suspend_ok_o_3; + wire com_tlm_u_tlm_tx_pm_ctrl_cfg_pending_3071; + wire com_tlm_u_tlm_tx_pm_ctrl_N_42587; + wire com_tlm_u_tlm_tx_pm_ctrl_N_17874_i_3072; + wire com_tlm_u_tlm_tx_pm_ctrl_un1_cfg_ct_axb_4_3073; + wire com_tlm_u_tlm_tx_pm_ctrl_un1_cfg_ct_axb_3_3074; + wire com_tlm_u_tlm_tx_pm_ctrl_un1_cfg_ct_axb_2_3075; + wire com_tlm_u_tlm_tx_pm_ctrl_cfg_ct23; + wire com_tlm_u_tlm_tx_pm_ctrl_un1_cfg_ct_axb_1_3076; + wire com_tlm_u_tlm_rx_ds_cpl; + wire com_tlm_u_tlm_rx_ds_rem; + wire com_tlm_u_tlm_rx_ds_eof_i; + wire com_tlm_u_tlm_rx_ds_eof; + wire com_tlm_u_tlm_rx_ds_src_rdy; + wire com_tlm_u_tlm_rx_ds_dsc; + wire com_tlm_u_tlm_rx_wen_aux_oq_3; + wire com_tlm_u_tlm_rx_ds_bar_src_rdy; + wire com_tlm_u_tlm_rx_ds_np; + wire com_tlm_u_tlm_rx_ds_sof; + wire com_tlm_u_tlm_rx_ds_cfg; + wire com_tlm_u_tlm_rx_fc_use_cpl; + wire com_tlm_u_tlm_rx_fc_sched_np; + wire com_tlm_u_tlm_rx_fc_req_np_dst_rdy; + wire com_tlm_u_tlm_rx_fc_send_state_0_sqmuxa_0; + wire com_tlm_u_tlm_rx_fc_use_np; + wire com_tlm_u_tlm_rx_fc_sched_p; + wire com_tlm_u_tlm_rx_fc_req_p_dst_rdy; + wire com_tlm_u_tlm_rx_fc_send_state_0_sqmuxa; + wire com_tlm_u_tlm_rx_fc_use_p; + wire com_tlm_u_tlm_rx_fc_unuse; + wire com_tlm_u_tlm_rx_aspm_ok_i; + wire com_tlm_u_tlm_rx_vc0_trn_reof; + wire com_tlm_u_tlm_rx_vc0_trn_rsof; + wire com_tlm_u_tlm_rx_vc0_N_41738_i; + wire com_tlm_u_tlm_rx_vc0_trn_rrem; + wire com_tlm_u_tlm_rx_vc0_N_41735_i; + wire com_tlm_u_tlm_rx_vc0_N_41743_i; + wire com_tlm_u_tlm_rx_vc0_cmmt_rsof; + wire com_tlm_u_tlm_rx_vc0_cmmt_reof; + wire com_tlm_u_tlm_rx_vc0_trn_rsrc_rdy; + wire com_tlm_u_tlm_rx_vc0_fc_free_eof; + wire com_tlm_u_tlm_rx_vc0_N_41738_i_i; + wire com_tlm_u_tlm_rx_vc0_fifo_cpl; + wire com_tlm_u_tlm_rx_vc0_fifo_np; + wire com_tlm_u_tlm_rx_vc0_fc_free_cpl; + wire com_tlm_u_tlm_rx_vc0_fc_free_np; + wire com_tlm_u_tlm_rx_vc0_fc_free_p; + wire com_tlm_u_tlm_rx_vc0_fc_free_1header; + wire com_tlm_u_tlm_rx_vc0_fc_free_1data; + wire com_tlm_u_tlm_rx_vc0_rd_mon_GND_3077; + wire com_tlm_u_tlm_rx_vc0_rd_mon_fc_free_1data_d_3078; + wire com_tlm_u_tlm_rx_vc0_rd_mon_N_43135; + wire com_tlm_u_tlm_rx_vc0_rd_mon_fc_free_1data_dc_3079; + wire com_tlm_u_tlm_rx_vc0_rd_mon_unaligned_header_q_3080; + wire com_tlm_u_tlm_rx_vc0_rd_mon_fc_free_p_o_3_3081; + wire com_tlm_u_tlm_rx_vc0_rd_mon_np_q_3082; + wire com_tlm_u_tlm_rx_vc0_rd_mon_cpl_q_3083; + wire com_tlm_u_tlm_rx_vc0_rd_mon_N_41825_i_0_i_3084; + wire com_tlm_u_tlm_rx_vc0_rd_mon_fc_free_1header_o_5; + wire com_tlm_u_tlm_rx_vc0_rd_mon_N_68337_i_3085; + wire com_tlm_u_tlm_rx_vc0_rd_mon_in_header_3086; + wire com_tlm_u_tlm_rx_vc0_rd_mon_un1_word_ct_2_0_a2_0_a2_0_a2_3087; + wire com_tlm_u_tlm_rx_vc0_rd_mon_N_13398_i; + wire com_tlm_u_tlm_rx_vc0_rd_mon_N_42463_1; + wire com_tlm_u_tlm_rx_vc0_rd_mon_N_68343_i_3088; + wire com_tlm_u_tlm_rx_vc0_rd_mon_un1_trn_sof_i_1_i_i_0_o2_0_o2_0_o2_3089; + wire com_tlm_u_tlm_rx_vc0_fifo_GND_3090; + wire com_tlm_u_tlm_rx_vc0_fifo_wen_aux_oq_3091; + wire com_tlm_u_tlm_rx_vc0_fifo_nxt_vld_bqr; + wire com_tlm_u_tlm_rx_vc0_fifo_data_bqr_64_; + wire com_tlm_u_tlm_rx_vc0_fifo_aux_vld_oqr; + wire com_tlm_u_tlm_rx_vc0_fifo_sof_hold; + wire com_tlm_u_tlm_rx_vc0_fifo_aux_vld_q; + wire com_tlm_u_tlm_rx_vc0_fifo_aux_vld; + wire com_tlm_u_tlm_rx_vc0_fifo_ep_oqr; + wire com_tlm_u_tlm_rx_vc0_fifo_data_bqr_46_; + wire com_tlm_u_tlm_rx_vc0_fifo_N_9522_i; + wire com_tlm_u_tlm_rx_vc0_fifo_cfg_nxt_rdy; + wire com_tlm_u_tlm_rx_vc0_fifo_adv_pkt_bq_0_3092; + wire com_tlm_u_tlm_rx_vc0_fifo_un4_adv_pkt_oq; + wire com_tlm_u_tlm_rx_vc0_fifo_un1_adv_pkt_oq_1_3093; + wire com_tlm_u_tlm_rx_vc0_fifo_N_9528; + wire com_tlm_u_tlm_rx_vc0_fifo_adv_pkt_out_i_0_0_a2_3094; + wire com_tlm_u_tlm_rx_vc0_fifo_data_bqr_65_; + wire com_tlm_u_tlm_rx_vc0_fifo_adv_pkt_in_i_0_3095; + wire com_tlm_u_tlm_rx_vc0_fifo_adv_pkt_in_i_1_3096; + wire com_tlm_u_tlm_rx_vc0_fifo_N_14286_i; + wire com_tlm_u_tlm_rx_vc0_fifo_sof_oqr; + wire com_tlm_u_tlm_rx_vc0_fifo_N_9516_i_i; + wire com_tlm_u_tlm_rx_vc0_fifo_select_bq_0_sqmuxa_3097; + wire com_tlm_u_tlm_rx_vc0_fifo_reset_i_q_i_3098; + wire com_tlm_u_tlm_rx_vc0_fifo_rem_oqr; + wire com_tlm_u_tlm_rx_vc0_fifo_data_bqr_67_; + wire com_tlm_u_tlm_rx_vc0_fifo_N_9521_i_3099; + wire com_tlm_u_tlm_rx_vc0_fifo_eof_oqr; + wire com_tlm_u_tlm_rx_vc0_fifo_N_9519_i_3100; + wire com_tlm_u_tlm_rx_vc0_fifo_un5_cfg_sof_d_1_3101; + wire com_tlm_u_tlm_rx_vc0_fifo_un4_cfg_sof_d_1; + wire com_tlm_u_tlm_rx_vc0_fifo_usr_src_rdy_d_3_3102; + wire com_tlm_u_tlm_rx_vc0_fifo_select_usr_3103; + wire com_tlm_u_tlm_rx_vc0_fifo_cfg_src_rdy_d_3_3104; + wire com_tlm_u_tlm_rx_vc0_fifo_un5_usr_src_rdy_d_3105; + wire com_tlm_u_tlm_rx_vc0_fifo_select_cfg_3106; + wire com_tlm_u_tlm_rx_vc0_fifo_data_vld_bqr; + wire com_tlm_u_tlm_rx_vc0_fifo_data_oqr_63_; + wire com_tlm_u_tlm_rx_vc0_fifo_data_bqr_63_; + wire com_tlm_u_tlm_rx_vc0_fifo_data_oqr_62_; + wire com_tlm_u_tlm_rx_vc0_fifo_data_bqr_62_; + wire com_tlm_u_tlm_rx_vc0_fifo_data_oqr_61_; + wire com_tlm_u_tlm_rx_vc0_fifo_data_bqr_61_; + wire com_tlm_u_tlm_rx_vc0_fifo_data_oqr_60_; + wire com_tlm_u_tlm_rx_vc0_fifo_data_bqr_60_; + wire com_tlm_u_tlm_rx_vc0_fifo_data_oqr_59_; + wire com_tlm_u_tlm_rx_vc0_fifo_data_bqr_59_; + wire com_tlm_u_tlm_rx_vc0_fifo_data_oqr_58_; + wire com_tlm_u_tlm_rx_vc0_fifo_data_bqr_58_; + wire com_tlm_u_tlm_rx_vc0_fifo_data_oqr_57_; + wire com_tlm_u_tlm_rx_vc0_fifo_data_bqr_57_; + wire com_tlm_u_tlm_rx_vc0_fifo_data_oqr_56_; + wire com_tlm_u_tlm_rx_vc0_fifo_data_bqr_56_; + wire com_tlm_u_tlm_rx_vc0_fifo_data_oqr_55_; + wire com_tlm_u_tlm_rx_vc0_fifo_data_bqr_55_; + wire com_tlm_u_tlm_rx_vc0_fifo_data_oqr_54_; + wire com_tlm_u_tlm_rx_vc0_fifo_data_bqr_54_; + wire com_tlm_u_tlm_rx_vc0_fifo_data_oqr_53_; + wire com_tlm_u_tlm_rx_vc0_fifo_data_bqr_53_; + wire com_tlm_u_tlm_rx_vc0_fifo_data_oqr_52_; + wire com_tlm_u_tlm_rx_vc0_fifo_data_bqr_52_; + wire com_tlm_u_tlm_rx_vc0_fifo_data_oqr_51_; + wire com_tlm_u_tlm_rx_vc0_fifo_data_bqr_51_; + wire com_tlm_u_tlm_rx_vc0_fifo_data_oqr_50_; + wire com_tlm_u_tlm_rx_vc0_fifo_data_bqr_50_; + wire com_tlm_u_tlm_rx_vc0_fifo_data_oqr_49_; + wire com_tlm_u_tlm_rx_vc0_fifo_data_bqr_49_; + wire com_tlm_u_tlm_rx_vc0_fifo_data_oqr_48_; + wire com_tlm_u_tlm_rx_vc0_fifo_data_bqr_48_; + wire com_tlm_u_tlm_rx_vc0_fifo_data_oqr_47_; + wire com_tlm_u_tlm_rx_vc0_fifo_data_bqr_47_; + wire com_tlm_u_tlm_rx_vc0_fifo_data_oqr_45_; + wire com_tlm_u_tlm_rx_vc0_fifo_data_bqr_45_; + wire com_tlm_u_tlm_rx_vc0_fifo_data_oqr_44_; + wire com_tlm_u_tlm_rx_vc0_fifo_data_bqr_44_; + wire com_tlm_u_tlm_rx_vc0_fifo_data_oqr_43_; + wire com_tlm_u_tlm_rx_vc0_fifo_data_bqr_43_; + wire com_tlm_u_tlm_rx_vc0_fifo_data_oqr_42_; + wire com_tlm_u_tlm_rx_vc0_fifo_data_bqr_42_; + wire com_tlm_u_tlm_rx_vc0_fifo_data_oqr_41_; + wire com_tlm_u_tlm_rx_vc0_fifo_data_bqr_41_; + wire com_tlm_u_tlm_rx_vc0_fifo_data_oqr_40_; + wire com_tlm_u_tlm_rx_vc0_fifo_data_bqr_40_; + wire com_tlm_u_tlm_rx_vc0_fifo_data_oqr_39_; + wire com_tlm_u_tlm_rx_vc0_fifo_data_bqr_39_; + wire com_tlm_u_tlm_rx_vc0_fifo_data_oqr_38_; + wire com_tlm_u_tlm_rx_vc0_fifo_data_bqr_38_; + wire com_tlm_u_tlm_rx_vc0_fifo_data_oqr_37_; + wire com_tlm_u_tlm_rx_vc0_fifo_data_bqr_37_; + wire com_tlm_u_tlm_rx_vc0_fifo_data_oqr_36_; + wire com_tlm_u_tlm_rx_vc0_fifo_data_bqr_36_; + wire com_tlm_u_tlm_rx_vc0_fifo_data_oqr_35_; + wire com_tlm_u_tlm_rx_vc0_fifo_data_bqr_35_; + wire com_tlm_u_tlm_rx_vc0_fifo_data_oqr_34_; + wire com_tlm_u_tlm_rx_vc0_fifo_data_bqr_34_; + wire com_tlm_u_tlm_rx_vc0_fifo_data_oqr_33_; + wire com_tlm_u_tlm_rx_vc0_fifo_data_bqr_33_; + wire com_tlm_u_tlm_rx_vc0_fifo_data_oqr_32_; + wire com_tlm_u_tlm_rx_vc0_fifo_data_bqr_32_; + wire com_tlm_u_tlm_rx_vc0_fifo_data_oqr_31_; + wire com_tlm_u_tlm_rx_vc0_fifo_data_bqr_31_; + wire com_tlm_u_tlm_rx_vc0_fifo_data_oqr_30_; + wire com_tlm_u_tlm_rx_vc0_fifo_data_bqr_30_; + wire com_tlm_u_tlm_rx_vc0_fifo_data_oqr_29_; + wire com_tlm_u_tlm_rx_vc0_fifo_data_bqr_29_; + wire com_tlm_u_tlm_rx_vc0_fifo_data_oqr_28_; + wire com_tlm_u_tlm_rx_vc0_fifo_data_bqr_28_; + wire com_tlm_u_tlm_rx_vc0_fifo_data_oqr_27_; + wire com_tlm_u_tlm_rx_vc0_fifo_data_bqr_27_; + wire com_tlm_u_tlm_rx_vc0_fifo_data_oqr_26_; + wire com_tlm_u_tlm_rx_vc0_fifo_data_bqr_26_; + wire com_tlm_u_tlm_rx_vc0_fifo_data_oqr_25_; + wire com_tlm_u_tlm_rx_vc0_fifo_data_bqr_25_; + wire com_tlm_u_tlm_rx_vc0_fifo_data_oqr_24_; + wire com_tlm_u_tlm_rx_vc0_fifo_data_bqr_24_; + wire com_tlm_u_tlm_rx_vc0_fifo_data_oqr_23_; + wire com_tlm_u_tlm_rx_vc0_fifo_data_bqr_23_; + wire com_tlm_u_tlm_rx_vc0_fifo_data_oqr_22_; + wire com_tlm_u_tlm_rx_vc0_fifo_data_bqr_22_; + wire com_tlm_u_tlm_rx_vc0_fifo_data_oqr_21_; + wire com_tlm_u_tlm_rx_vc0_fifo_data_bqr_21_; + wire com_tlm_u_tlm_rx_vc0_fifo_data_oqr_20_; + wire com_tlm_u_tlm_rx_vc0_fifo_data_bqr_20_; + wire com_tlm_u_tlm_rx_vc0_fifo_data_oqr_19_; + wire com_tlm_u_tlm_rx_vc0_fifo_data_bqr_19_; + wire com_tlm_u_tlm_rx_vc0_fifo_data_oqr_18_; + wire com_tlm_u_tlm_rx_vc0_fifo_data_bqr_18_; + wire com_tlm_u_tlm_rx_vc0_fifo_data_oqr_17_; + wire com_tlm_u_tlm_rx_vc0_fifo_data_bqr_17_; + wire com_tlm_u_tlm_rx_vc0_fifo_data_oqr_16_; + wire com_tlm_u_tlm_rx_vc0_fifo_data_bqr_16_; + wire com_tlm_u_tlm_rx_vc0_fifo_data_oqr_15_; + wire com_tlm_u_tlm_rx_vc0_fifo_data_bqr_15_; + wire com_tlm_u_tlm_rx_vc0_fifo_data_oqr_14_; + wire com_tlm_u_tlm_rx_vc0_fifo_data_bqr_14_; + wire com_tlm_u_tlm_rx_vc0_fifo_data_oqr_13_; + wire com_tlm_u_tlm_rx_vc0_fifo_data_bqr_13_; + wire com_tlm_u_tlm_rx_vc0_fifo_data_oqr_12_; + wire com_tlm_u_tlm_rx_vc0_fifo_data_bqr_12_; + wire com_tlm_u_tlm_rx_vc0_fifo_data_oqr_11_; + wire com_tlm_u_tlm_rx_vc0_fifo_data_bqr_11_; + wire com_tlm_u_tlm_rx_vc0_fifo_data_oqr_10_; + wire com_tlm_u_tlm_rx_vc0_fifo_data_bqr_10_; + wire com_tlm_u_tlm_rx_vc0_fifo_data_oqr_9_; + wire com_tlm_u_tlm_rx_vc0_fifo_data_bqr_9_; + wire com_tlm_u_tlm_rx_vc0_fifo_data_oqr_8_; + wire com_tlm_u_tlm_rx_vc0_fifo_data_bqr_8_; + wire com_tlm_u_tlm_rx_vc0_fifo_data_oqr_7_; + wire com_tlm_u_tlm_rx_vc0_fifo_data_bqr_7_; + wire com_tlm_u_tlm_rx_vc0_fifo_data_oqr_6_; + wire com_tlm_u_tlm_rx_vc0_fifo_data_bqr_6_; + wire com_tlm_u_tlm_rx_vc0_fifo_data_oqr_5_; + wire com_tlm_u_tlm_rx_vc0_fifo_data_bqr_5_; + wire com_tlm_u_tlm_rx_vc0_fifo_data_oqr_4_; + wire com_tlm_u_tlm_rx_vc0_fifo_data_bqr_4_; + wire com_tlm_u_tlm_rx_vc0_fifo_data_oqr_3_; + wire com_tlm_u_tlm_rx_vc0_fifo_data_bqr_3_; + wire com_tlm_u_tlm_rx_vc0_fifo_data_oqr_2_; + wire com_tlm_u_tlm_rx_vc0_fifo_data_bqr_2_; + wire com_tlm_u_tlm_rx_vc0_fifo_data_oqr_1_; + wire com_tlm_u_tlm_rx_vc0_fifo_data_bqr_1_; + wire com_tlm_u_tlm_rx_vc0_fifo_select_oq_3107; + wire com_tlm_u_tlm_rx_vc0_fifo_select_bq_3108; + wire com_tlm_u_tlm_rx_vc0_fifo_data_oqr_0_; + wire com_tlm_u_tlm_rx_vc0_fifo_data_bqr_0_; + wire com_tlm_u_tlm_rx_vc0_fifo_select_oq2bq_d_5_3109; + wire com_tlm_u_tlm_rx_vc0_fifo_select_oq2bq_d_3110; + wire com_tlm_u_tlm_rx_vc0_fifo_np_oqr; + wire com_tlm_u_tlm_rx_vc0_fifo_select_bq17_3111; + wire com_tlm_u_tlm_rx_vc0_fifo_select_cfg_7; + wire com_tlm_u_tlm_rx_vc0_fifo_select_usr_7; + wire com_tlm_u_tlm_rx_vc0_fifo_un1_adv_pkt_oq_3112; + wire com_tlm_u_tlm_rx_vc0_fifo_cfg_oqr; + wire com_tlm_u_tlm_rx_vc0_fifo_adv_pkt_bq_3113; + wire com_tlm_u_tlm_rx_vc0_fifo_un1_select_oq2bq_d_1_i_3114; + wire com_tlm_u_tlm_rx_vc0_fifo_select_oq2bq_5; + wire com_tlm_u_tlm_rx_vc0_fifo_select_oq2bq_1_3115; + wire com_tlm_u_tlm_rx_vc0_fifo_wen_aux_bq_3116; + wire com_tlm_u_tlm_rx_vc0_fifo_data_vld_oqr; + wire com_tlm_u_tlm_rx_vc0_fifo_select_oq2bq_3117; + wire com_tlm_u_tlm_rx_vc0_fifo_N_9523_i; + wire com_tlm_u_tlm_rx_vc0_fifo_N_9308_i_3118; + wire com_tlm_u_tlm_rx_vc0_fifo_N_9309_i_3119; + wire com_tlm_u_tlm_rx_vc0_fifo_N_9310_i_3120; + wire com_tlm_u_tlm_rx_vc0_fifo_N_9311_i_3121; + wire com_tlm_u_tlm_rx_vc0_fifo_N_9312_i_3122; + wire com_tlm_u_tlm_rx_vc0_fifo_N_9313_i_3123; + wire com_tlm_u_tlm_rx_vc0_fifo_N_9314_i_3124; + wire com_tlm_u_tlm_rx_vc0_fifo_un8_cpl_d_3125; + wire com_tlm_u_tlm_rx_vc0_fifo_N_68338_i_3126; + wire com_tlm_u_tlm_rx_vc0_fifo_N_9520_i_3127; + wire com_tlm_u_tlm_rx_vc0_fifo_N_9245_i_3128; + wire com_tlm_u_tlm_rx_vc0_fifo_N_9246_i_3129; + wire com_tlm_u_tlm_rx_vc0_fifo_N_9247_i_3130; + wire com_tlm_u_tlm_rx_vc0_fifo_N_9248_i_3131; + wire com_tlm_u_tlm_rx_vc0_fifo_N_9249_i_3132; + wire com_tlm_u_tlm_rx_vc0_fifo_N_14338_i_3133; + wire com_tlm_u_tlm_rx_vc0_fifo_N_14339_i_3134; + wire com_tlm_u_tlm_rx_vc0_fifo_N_14340_i_3135; + wire com_tlm_u_tlm_rx_vc0_fifo_N_14341_i_3136; + wire com_tlm_u_tlm_rx_vc0_fifo_N_14342_i_3137; + wire com_tlm_u_tlm_rx_vc0_fifo_N_14343_i_3138; + wire com_tlm_u_tlm_rx_vc0_fifo_N_14344_i_3139; + wire com_tlm_u_tlm_rx_vc0_fifo_N_14345_i_3140; + wire com_tlm_u_tlm_rx_vc0_fifo_N_14346_i_3141; + wire com_tlm_u_tlm_rx_vc0_fifo_N_14347_i_3142; + wire com_tlm_u_tlm_rx_vc0_fifo_N_14348_i_3143; + wire com_tlm_u_tlm_rx_vc0_fifo_N_14379_i_3144; + wire com_tlm_u_tlm_rx_vc0_fifo_N_14376_i_3145; + wire com_tlm_u_tlm_rx_vc0_fifo_N_9262_i_3146; + wire com_tlm_u_tlm_rx_vc0_fifo_N_9263_i_3147; + wire com_tlm_u_tlm_rx_vc0_fifo_N_9264_i_3148; + wire com_tlm_u_tlm_rx_vc0_fifo_N_9265_i_3149; + wire com_tlm_u_tlm_rx_vc0_fifo_N_9266_i_3150; + wire com_tlm_u_tlm_rx_vc0_fifo_N_9267_i_3151; + wire com_tlm_u_tlm_rx_vc0_fifo_N_9268_i_3152; + wire com_tlm_u_tlm_rx_vc0_fifo_N_9269_i_3153; + wire com_tlm_u_tlm_rx_vc0_fifo_N_9270_i_3154; + wire com_tlm_u_tlm_rx_vc0_fifo_N_9271_i_3155; + wire com_tlm_u_tlm_rx_vc0_fifo_N_9272_i_3156; + wire com_tlm_u_tlm_rx_vc0_fifo_N_9273_i_3157; + wire com_tlm_u_tlm_rx_vc0_fifo_N_9274_i_3158; + wire com_tlm_u_tlm_rx_vc0_fifo_N_9275_i_3159; + wire com_tlm_u_tlm_rx_vc0_fifo_N_9276_i_3160; + wire com_tlm_u_tlm_rx_vc0_fifo_N_9277_i_3161; + wire com_tlm_u_tlm_rx_vc0_fifo_N_9278_i_3162; + wire com_tlm_u_tlm_rx_vc0_fifo_N_9279_i_3163; + wire com_tlm_u_tlm_rx_vc0_fifo_N_9280_i_3164; + wire com_tlm_u_tlm_rx_vc0_fifo_N_9281_i_3165; + wire com_tlm_u_tlm_rx_vc0_fifo_N_9282_i_3166; + wire com_tlm_u_tlm_rx_vc0_fifo_N_9283_i_3167; + wire com_tlm_u_tlm_rx_vc0_fifo_N_14349_i_3168; + wire com_tlm_u_tlm_rx_vc0_fifo_N_14350_i_3169; + wire com_tlm_u_tlm_rx_vc0_fifo_N_14351_i_3170; + wire com_tlm_u_tlm_rx_vc0_fifo_N_14352_i_3171; + wire com_tlm_u_tlm_rx_vc0_fifo_N_14353_i_3172; + wire com_tlm_u_tlm_rx_vc0_fifo_N_14354_i_3173; + wire com_tlm_u_tlm_rx_vc0_fifo_N_14355_i_3174; + wire com_tlm_u_tlm_rx_vc0_fifo_N_14356_i_3175; + wire com_tlm_u_tlm_rx_vc0_fifo_N_14357_i_3176; + wire com_tlm_u_tlm_rx_vc0_fifo_N_14358_i_3177; + wire com_tlm_u_tlm_rx_vc0_fifo_N_14359_i_3178; + wire com_tlm_u_tlm_rx_vc0_fifo_N_14360_i_3179; + wire com_tlm_u_tlm_rx_vc0_fifo_N_14361_i_3180; + wire com_tlm_u_tlm_rx_vc0_fifo_N_14362_i_3181; + wire com_tlm_u_tlm_rx_vc0_fifo_N_14363_i_3182; + wire com_tlm_u_tlm_rx_vc0_fifo_N_14364_i_3183; + wire com_tlm_u_tlm_rx_vc0_fifo_N_14365_i_3184; + wire com_tlm_u_tlm_rx_vc0_fifo_N_14366_i_3185; + wire com_tlm_u_tlm_rx_vc0_fifo_N_14367_i_3186; + wire com_tlm_u_tlm_rx_vc0_fifo_N_14368_i_3187; + wire com_tlm_u_tlm_rx_vc0_fifo_N_14369_i_3188; + wire com_tlm_u_tlm_rx_vc0_fifo_N_14370_i_3189; + wire com_tlm_u_tlm_rx_vc0_fifo_N_14371_i_3190; + wire com_tlm_u_tlm_rx_vc0_fifo_N_14372_i_3191; + wire com_tlm_u_tlm_rx_vc0_fifo_trn_rerrfwd; + wire com_tlm_u_tlm_rx_vc0_fifo_trn_rsrc_dsc; + wire com_tlm_u_tlm_rx_vc0_fifo_N_68339_i_3192; + wire com_tlm_u_tlm_rx_vc0_fifo_adv_out_i_0_3193; + wire com_tlm_u_tlm_rx_vc0_fifo_N_67945_i_3194; + wire com_tlm_u_tlm_rx_vc0_fifo_adv_pkt_in_i_3195; + wire com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_waddr_p1_1_s_0_3196; + wire com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_waddr_p1_1_s_1_3197; + wire com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_waddr_p1_1_cry_0_3198; + wire com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_waddr_p1_1_s_2_3199; + wire com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_waddr_p1_1_cry_1_3200; + wire com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_waddr_p1_1_s_3_3201; + wire com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_waddr_p1_1_cry_2_3202; + wire com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_waddr_p1_1_s_4_3203; + wire com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_waddr_p1_1_cry_3_3204; + wire com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_waddr_p1_1_s_5_3205; + wire com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_waddr_p1_1_cry_4_3206; + wire com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_waddr_p1_1_s_6_3207; + wire com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_waddr_p1_1_cry_5_3208; + wire com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_waddr_p1_1_s_7_3209; + wire com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_waddr_p1_1_cry_6_3210; + wire com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_waddr_p1_1_s_8_3211; + wire com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_waddr_p1_1_cry_7_3212; + wire com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_waddr_p1_1_s_9_3213; + wire com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_waddr_p1_1_cry_8_3214; + wire com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un3_pkt_ct_s_1_3215; + wire com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un3_pkt_ct_cry_0_3216; + wire com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un3_pkt_ct_s_2_3217; + wire com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un3_pkt_ct_cry_1_3218; + wire com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un3_pkt_ct_s_3_3219; + wire com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un3_pkt_ct_cry_2_3220; + wire com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un3_pkt_ct_s_4_3221; + wire com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un3_pkt_ct_cry_3_3222; + wire com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un3_pkt_ct_s_5_3223; + wire com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un3_pkt_ct_cry_4_3224; + wire com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un3_pkt_ct_s_6_3225; + wire com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un3_pkt_ct_cry_5_3226; + wire com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un3_pkt_ct_m1_s_1_3227; + wire com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un3_pkt_ct_m1_cry_0_3228; + wire com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un3_pkt_ct_m1_s_2_3229; + wire com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un3_pkt_ct_m1_cry_1_3230; + wire com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un3_pkt_ct_m1_s_3_3231; + wire com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un3_pkt_ct_m1_cry_2_3232; + wire com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un3_pkt_ct_m1_s_4_3233; + wire com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un3_pkt_ct_m1_cry_3_3234; + wire com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un3_pkt_ct_m1_s_5_3235; + wire com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un3_pkt_ct_m1_cry_4_3236; + wire com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un3_pkt_ct_m1_s_6_3237; + wire com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un3_pkt_ct_m1_cry_5_3238; + wire com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_vld_ct_1_s_1_3239; + wire com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_vld_ct_1_cry_0_3240; + wire com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_vld_ct_1_s_2_3241; + wire com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_vld_ct_1_cry_1_3242; + wire com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_vld_ct_1_s_3_3243; + wire com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_vld_ct_1_cry_2_3244; + wire com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_vld_ct_1_s_4_3245; + wire com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_vld_ct_1_cry_3_3246; + wire com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_vld_ct_1_s_5_3247; + wire com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_vld_ct_1_cry_4_3248; + wire com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_vld_ct_1_s_6_3249; + wire com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_vld_ct_1_cry_5_3250; + wire com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_vld_ct_1_cry_7_0_3251; + wire com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_vld_ct_1_s_7_3252; + wire com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_vld_ct_1_cry_6_3253; + wire com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_vld_ct_1_cry_8_0_3254; + wire com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_vld_ct_1_s_8_3255; + wire com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_vld_ct_1_cry_7_3256; + wire com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_vld_ct_1_s_9_3257; + wire com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_vld_ct_1_cry_8_3258; + wire com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_GND_3259; + wire com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_wen_i_1_0; + wire com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_lockout_3260; + wire com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_wen_i_4; + wire com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_wen_i_2; + wire com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_waddr_p1_3; + wire com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_wen_i_1_3261; + wire com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_vld_ct_1_axb_0_3262; + wire com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_N_9199_i_3263; + wire com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_all_full_3264; + wire com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_vld_ct_eq_1_3265; + wire com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_vld_ct_eq_1_6_3266; + wire com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_vld_ct_eq_1_5_3267; + wire com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_vld_ct_eq_1_2_3268; + wire com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_N_9613_i; + wire com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_wen_i_7; + wire com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_wen_i_6; + wire com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_wen_i_5; + wire com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_N_9613_2; + wire com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un3_pkt_ct_axb_6_3269; + wire com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un3_pkt_ct_axb_5_3270; + wire com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un3_pkt_ct_axb_4_3271; + wire com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un3_pkt_ct_axb_3_3272; + wire com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un3_pkt_ct_axb_2_3273; + wire com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un3_pkt_ct_axb_1_3274; + wire com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un3_pkt_ct_m1_axb_6_3275; + wire com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un3_pkt_ct_m1_axb_5_3276; + wire com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un3_pkt_ct_m1_axb_4_3277; + wire com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un3_pkt_ct_m1_axb_3_3278; + wire com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un3_pkt_ct_m1_axb_2_3279; + wire com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un3_pkt_ct_m1_axb_1_3280; + wire com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_vld_ct_1_axb_9_3281; + wire com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_vld_ct_1_axb_8_3282; + wire com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_vld_ct_1_axb_7_3283; + wire com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_vld_ct_1_axb_6_3284; + wire com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_vld_ct_1_axb_5_3285; + wire com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_vld_ct_1_axb_4_3286; + wire com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_vld_ct_1_axb_3_3287; + wire com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_vld_ct_1_axb_2_3288; + wire com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_vld_ct_1_axb_1_3289; + wire com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_vld_ct25; + wire com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_waddr_p1_1_axb_9_3290; + wire com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_waddr_p1_1_axb_8_3291; + wire com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_waddr_p1_1_axb_7_3292; + wire com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_waddr_p1_1_axb_6_3293; + wire com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_waddr_p1_1_axb_5_3294; + wire com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_waddr_p1_1_axb_4_3295; + wire com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_waddr_p1_1_axb_3_3296; + wire com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_waddr_p1_1_axb_2_3297; + wire com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_waddr_p1_1_axb_1_3298; + wire com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_waddr_p1_1_axb_0_3299; + wire com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr16_3300; + wire com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_vld_ct25_i; + wire com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_frm_vld_3301; + wire com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_pop_3302; + wire com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_nxt_vld_3303; + wire com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_N_9612_i_3304; + wire com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_overflow_1_i; + wire com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_push_3305; + wire com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_N_9616_i_3306; + wire com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_pop_3307; + wire com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_vld_ct_1_cry_6_ma_3308; + wire com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_VCC_3309; + wire com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un3_pkt_ct_m1_axb_0_3310; + wire com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un3_pkt_ct_axb_0_3311; + wire com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_queue_ram_VCC_3312; + wire com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_queue_ram_GND_3313; + wire com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_queue_ram_N_9618_i_3314; + wire com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_GND_3315; + wire com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_un1_raddr_lo_1_cry_1_0_3316; + wire com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_un1_raddr_lo_1_s_1_4; + wire com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_un1_raddr_lo_1_cry_0_3317; + wire com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_un1_raddr_lo_1_cry_2_0_3318; + wire com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_un1_raddr_lo_1_s_2_4; + wire com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_un1_raddr_lo_1_cry_1_3319; + wire com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_un1_raddr_lo_1_s_3_4; + wire com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_un1_raddr_lo_1_cry_2_3320; + wire com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_un1_raddr_lo_1_axb_0_3321; + wire com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_N_14177; + wire com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_N_14176; + wire com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_N_14179; + wire com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_N_14178; + wire com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_N_14181; + wire com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_N_14180; + wire com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_un1_bkp_i_1_i_3322; + wire com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_un1_bkp_i_3_i_3323; + wire com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_un11_nxt_vld_o_en_2_3324; + wire com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_overwrap_2_3325; + wire com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_N_14175_i; + wire com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_nxt_vld_o_2; + wire com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_N_67946_i; + wire com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_N_68076_i; + wire com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_N_68075_i; + wire com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_N_67940_i; + wire com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_N_67941_i; + wire com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_N_67942_i; + wire com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_N_67943_i; + wire com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_N_67944_i; + wire com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_N_68074_i; + wire com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_hi_eq_1_m_i_3326; + wire com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_hi_53_4_; + wire com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_hi_53_0_; + wire com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_N_9609_1; + wire com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_un1_raddr_lo_1_axb_3_3327; + wire com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_un1_raddr_lo_1_axb_2_3328; + wire com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_un1_raddr_lo_1_axb_1_3329; + wire com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_d_o_0_sqmuxa_3330; + wire com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_N_14111; + wire com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_N_9610_i_3331; + wire com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_srl_ren_3332; + wire com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_un1_raddr_lo_1_cry_0_ma_3333; + wire com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_VCC_3334; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_N_14199_i; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_N_14337; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_ren; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_in_86_; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_in_89_; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_in_81_; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_in_82_; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_in_83_; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_in_92_; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_in_85_; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_in_129_; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_in_88_; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_in_90_; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_in_91_; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_in_133_; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_in_93_; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_in_94_; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_in_135_; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_in_95_; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_in_96_; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_in_97_; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_in_98_; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_in_139_; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_in_99_; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_in_100_; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_in_101_; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_in_102_; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_in_103_; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_in_72_; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_in_104_; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_in_113_; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_in_73_; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_in_105_; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_in_114_; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_in_74_; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_in_106_; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_in_115_; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_in_75_; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_in_107_; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_in_76_; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_in_108_; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_in_109_; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_in_118_; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_in_78_; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_in_117_; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_in_77_; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_in_79_; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_in_111_; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_in_84_; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_in_116_; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_in_112_; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_in_121_; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_in_87_; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_in_122_; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_in_136_; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_in_123_; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_in_137_; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_in_124_; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_in_120_; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_in_80_; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_in_125_; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_in_130_; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_in_126_; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_in_132_; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_in_131_; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_in_127_; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_in_110_; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_in_119_; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_in_128_; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_in_134_; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_GND_3335; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_un1_raddr_lo_1_cry_0_3336; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_un1_raddr_lo_1_cry_1_3337; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_un1_raddr_lo_1_cry_2_3338; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_67_; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_65_; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_64_; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_overwrap_0_3339; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_un13_nxt_vld_o_en_1_3340; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_un1_bkp_i_1_i_3341; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_un1_bkp_i_3_i_3342; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_un13_nxt_vld_o_en_3343; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_overwrap_3_3344; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_135_; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_63_; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_134_; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_62_; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_133_; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_61_; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_132_; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_60_; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_131_; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_59_; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_130_; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_58_; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_129_; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_57_; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_128_; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_56_; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_127_; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_55_; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_126_; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_54_; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_125_; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_53_; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_124_; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_52_; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_123_; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_51_; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_122_; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_50_; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_121_; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_49_; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_120_; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_48_; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_119_; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_47_; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_118_; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_46_; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_117_; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_45_; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_116_; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_44_; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_115_; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_43_; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_114_; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_42_; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_113_; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_41_; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_112_; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_40_; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_111_; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_39_; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_110_; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_38_; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_109_; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_37_; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_108_; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_36_; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_107_; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_35_; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_106_; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_34_; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_105_; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_33_; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_104_; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_32_; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_103_; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_31_; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_102_; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_30_; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_101_; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_29_; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_100_; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_28_; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_99_; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_27_; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_98_; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_26_; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_97_; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_25_; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_96_; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_24_; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_95_; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_23_; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_94_; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_22_; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_93_; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_21_; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_92_; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_20_; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_91_; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_19_; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_90_; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_18_; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_89_; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_17_; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_88_; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_16_; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_87_; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_15_; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_86_; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_14_; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_85_; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_13_; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_84_; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_12_; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_83_; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_11_; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_82_; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_10_; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_81_; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_9_; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_80_; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_8_; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_79_; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_7_; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_78_; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_6_; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_77_; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_5_; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_76_; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_4_; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_75_; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_3_; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_74_; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_2_; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_73_; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_1_; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_72_; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_0_; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_hi_eq_1_m_i_3345; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_d_o_d_m_67__3346; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_139_; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_d_o_d_m_65__3347; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_137_; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_d_o_d_m_64__3348; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_136_; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_un1_raddr_lo_1_axb_3_3349; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_un1_raddr_lo_1_axb_2_3350; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_un1_raddr_lo_1_axb_1_3351; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_un1_raddr_lo_1_axb_0_3352; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_un1_raddr_lo_1_s_1_5; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_un1_raddr_lo_1_s_2_5; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_un1_raddr_lo_1_s_3_5; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_d_o_0_sqmuxa_3353; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_9533_i_3354; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_9534_i_3355; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_9535_i_3356; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_9536_i_3357; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_9537_i_3358; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_9538_i_3359; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_9539_i_3360; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_9540_i_3361; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_9541_i_3362; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_9542_i_3363; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_9543_i_3364; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_9544_i_3365; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_9545_i_3366; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_9546_i_3367; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_9547_i_3368; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_9548_i_3369; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_9549_i_3370; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_9550_i_3371; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_9551_i_3372; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_9552_i_3373; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_9553_i_3374; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_9554_i_3375; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_9555_i_3376; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_9556_i_3377; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_9557_i_3378; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_9558_i_3379; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_9559_i_3380; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_9560_i_3381; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_9561_i_3382; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_9562_i_3383; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_9563_i_3384; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_9564_i_3385; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_9565_i_3386; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_9566_i_3387; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_9567_i_3388; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_9568_i_3389; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_9569_i_3390; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_9570_i_3391; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_9571_i_3392; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_9572_i_3393; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_9573_i_3394; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_9574_i_3395; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_9575_i_3396; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_9576_i_3397; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_9577_i_3398; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_9578_i_3399; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_9579_i_3400; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_9580_i_3401; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_9581_i_3402; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_9582_i_3403; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_9583_i_3404; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_9584_i_3405; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_9585_i_3406; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_9586_i_3407; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_9587_i_3408; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_9588_i_3409; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_9589_i_3410; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_9590_i_3411; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_9591_i_3412; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_9592_i_3413; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_9593_i_3414; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_9594_i_3415; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_9595_i_3416; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_9596_i_3417; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_9597_i_3418; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_srl_ren_0; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_queue_aux_queue_GND_3419; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_queue_aux_queue_un1_raddr_lo_1_s_1_6; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_queue_aux_queue_un1_raddr_lo_1_cry_0_3420; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_queue_aux_queue_un1_raddr_lo_1_s_2_6; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_queue_aux_queue_un1_raddr_lo_1_cry_1_3421; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_queue_aux_queue_un1_raddr_lo_1_s_3_6; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_queue_aux_queue_un1_raddr_lo_1_cry_2_3422; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_queue_aux_queue_un1_aux_queue; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_queue_aux_queue_N_9529_i_3423; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_queue_aux_queue_un1_bkp_i_1_i_3424; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_queue_aux_queue_un15_nxt_vld_o_en_2_3425; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_queue_aux_queue_un1_raddr_lo_1_axb_0_3426; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_queue_aux_queue_un1_raddr_lo_1_axb_3_3427; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_queue_aux_queue_un1_raddr_lo_1_axb_2_3428; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_queue_aux_queue_un1_raddr_lo_1_axb_1_3429; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_queue_aux_queue_d_o_0_sqmuxa_3430; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_fc_gnt_3; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_GND_3431; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_N_16796_i_3432; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_err_overflow_o_3_0_a2_3_3433; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_N_42529_i_3434; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_lat_prescale_term10; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_lat_prescale_term_3435; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_N_69387_i_3436; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_un1_lat_timer_i; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_freeze_timer_3437; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_free_q_3438; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_free_h_3439; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_h_o_cry_0_3440; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_h_o_cry_1_3441; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_h_o_cry_2_3442; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_h_o_cry_3_3443; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_h_o_cry_4_3444; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_h_o_cry_5_3445; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_h_o_cry_6_3446; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_d_o_cry_0_0_3447; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_free_d_3448; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_d_o_cry_1_0_3449; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_d_o_cry_0_3450; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_d_o_cry_2_0_3451; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_d_o_cry_1_3452; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_d_o_cry_3_0_3453; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_d_o_cry_2_3454; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_d_o_cry_4_0_3455; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_d_o_cry_3_3456; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_d_o_cry_5_0_3457; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_d_o_cry_4_3458; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_d_o_cry_5_3459; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_d_o_cry_6_3460; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_d_o_cry_7_3461; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_d_o_cry_8_3462; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_d_o_cry_9_3463; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_d_o_cry_10_3464; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_d_av_o_s_1_3465; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_d_av_o_cry_0_3466; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_d_av_o_s_2_3467; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_d_av_o_cry_1_3468; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_d_av_o_s_3_3469; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_d_av_o_cry_2_3470; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_d_av_o_s_4_3471; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_d_av_o_cry_3_3472; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_d_av_o_s_5_3473; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_d_av_o_cry_4_3474; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_d_av_o_s_6_3475; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_d_av_o_cry_5_3476; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_d_av_o_s_7_3477; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_d_av_o_cry_6_3478; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_d_av_o_s_8_3479; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_d_av_o_cry_7_3480; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_d_av_o_s_9_3481; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_d_av_o_cry_8_3482; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_d_av_o_s_10_3483; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_d_av_o_cry_9_3484; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_d_av_o_s_11_3485; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_d_av_o_cry_10_3486; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un1_fc_d_con_1_cry_0_0_3487; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un1_fc_d_con_1_cry_1_0_3488; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un1_fc_d_con_1_s_1_3489; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un1_fc_d_con_1_cry_0_3490; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un1_fc_d_con_1_cry_2_0_3491; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un1_fc_d_con_1_s_2_3492; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un1_fc_d_con_1_cry_1_3493; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un1_fc_d_con_1_cry_3_0_3494; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un1_fc_d_con_1_s_3_3495; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un1_fc_d_con_1_cry_2_3496; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un1_fc_d_con_1_cry_4_0_3497; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un1_fc_d_con_1_s_4_3498; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un1_fc_d_con_1_cry_3_3499; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un1_fc_d_con_1_cry_5_0_3500; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un1_fc_d_con_1_s_5_3501; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un1_fc_d_con_1_cry_4_3502; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un1_fc_d_con_1_s_6_3503; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un1_fc_d_con_1_cry_5_3504; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un1_fc_d_con_1_s_7_3505; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un1_fc_d_con_1_cry_6_3506; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un1_fc_d_con_1_s_8_3507; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un1_fc_d_con_1_cry_7_3508; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un1_fc_d_con_1_s_9_3509; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un1_fc_d_con_1_cry_8_3510; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un1_fc_d_con_1_s_10_3511; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un1_fc_d_con_1_cry_9_3512; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un1_fc_d_con_1_s_11_3513; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un1_fc_d_con_1_cry_10_3514; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_h_av_o_s_1_3515; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_h_av_o_cry_0_3516; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_h_av_o_s_2_3517; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_h_av_o_cry_1_3518; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_h_av_o_s_3_3519; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_h_av_o_cry_2_3520; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_h_av_o_s_4_3521; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_h_av_o_cry_3_3522; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_h_av_o_s_5_3523; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_h_av_o_cry_4_3524; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_h_av_o_s_6_3525; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_h_av_o_cry_5_3526; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_h_av_o_s_7_3527; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_h_av_o_cry_6_3528; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_h_advert_1_cry_0_3529; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_h_advert_1_cry_1_3530; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_h_advert_1_cry_2_3531; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_h_advert_1_cry_3_3532; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_h_advert_1_cry_4_3533; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_h_advert_1_cry_5_3534; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_h_advert_1_cry_6_3535; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_VCC_3536; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_d_advert_1_cry_0_3537; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_d_advert_1_cry_1_3538; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_d_advert_1_cry_2_3539; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_d_advert_1_cry_3_3540; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_d_advert_1_cry_4_3541; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_d_advert_1_cry_5_3542; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_d_advert_1_cry_6_3543; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_d_advert_1_cry_7_3544; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_d_advert_1_cry_8_3545; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_d_advert_1_cry_9_3546; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_d_advert_1_cry_10_3547; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_GND_3548; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_free_hold13; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un1_fc_d_con_1_axb_0_3549; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_free_q2_3550; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_free_hold_3551; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_gnt; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_d_advert_1_axb_11_3552; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_h_advert_1_axb_7_3553; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_free_d_3; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_free_h_3; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_free_q_3; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_h_o_axb_7_3554; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_h_o_axb_6_3555; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_h_o_axb_5_3556; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_h_o_axb_4_3557; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_h_o_axb_3_3558; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_h_o_axb_2_3559; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_h_o_axb_1_3560; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_h_o_axb_0_3561; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_d_av_o_axb_11_3562; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_d_av_o_axb_10_3563; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_d_av_o_axb_9_3564; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_d_av_o_axb_8_3565; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_d_av_o_axb_7_3566; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_d_av_o_axb_6_3567; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_d_av_o_axb_5_3568; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_d_av_o_axb_4_3569; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_d_av_o_axb_3_3570; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_d_av_o_axb_2_3571; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_d_av_o_axb_1_3572; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_d_av_o_axb_0_i_3573; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_d_av_o_axb_0_3574; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_h_av_o_axb_7_3575; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_h_av_o_axb_6_3576; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_h_av_o_axb_5_3577; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_h_av_o_axb_4_3578; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_h_av_o_axb_3_3579; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_h_av_o_axb_2_3580; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_h_av_o_axb_1_3581; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_h_av_o_axb_0_i_3582; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_h_av_o_axb_0_3583; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_d_o_axb_11_3584; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_d_o_axb_10_3585; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_d_o_axb_9_3586; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_d_o_axb_8_3587; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_d_o_axb_7_3588; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_d_o_axb_6_3589; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_d_o_axb_5_3590; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_d_o_axb_4_3591; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_d_o_axb_3_3592; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_d_o_axb_2_3593; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_d_o_axb_1_3594; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_d_o_axb_0_3595; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_N_41749_i; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un1_fc_d_con_1_axb_11_3596; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un1_fc_d_con_1_axb_10_3597; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un1_fc_d_con_1_axb_9_3598; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un1_fc_d_con_1_axb_8_3599; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un1_fc_d_con_1_axb_7_3600; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un1_fc_d_con_1_axb_6_3601; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un1_fc_d_con_1_axb_5_3602; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un1_fc_d_con_1_axb_4_3603; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un1_fc_d_con_1_axb_3_3604; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un1_fc_d_con_1_axb_2_3605; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un1_fc_d_con_1_axb_1_3606; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_N_68902_i_3607; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_N_68903_i_3608; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_req_p_src_rdy; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_N_68904_i_3609; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_send_state_2__3610; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_send_state_0__3611; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_N_42050_i; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_d_advert_1_axb_10_3612; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_d_advert_1_axb_9_3613; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_d_advert_1_axb_8_3614; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_d_advert_1_axb_7_3615; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_d_advert_1_axb_6_3616; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_d_advert_1_axb_5_3617; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_d_advert_1_axb_4_3618; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_d_advert_1_axb_3_3619; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_d_advert_1_axb_2_3620; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_d_advert_1_axb_1_3621; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_d_advert_1_axb_0_3622; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_h_advert_1_axb_6_3623; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_h_advert_1_axb_5_3624; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_h_advert_1_axb_4_3625; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_h_advert_1_axb_3_3626; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_h_advert_1_axb_2_3627; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_h_advert_1_axb_1_3628; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_h_advert_1_axb_0_3629; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_free_q_3630; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_free_h_3631; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_h_o_cry_0_3632; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_h_o_cry_1_3633; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_h_o_cry_2_3634; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_h_o_cry_3_3635; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_h_o_cry_4_3636; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_h_o_cry_5_3637; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_h_o_cry_6_3638; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_d_o_cry_0_0_3639; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_free_d_3640; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_d_o_cry_1_0_3641; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_d_o_cry_0_3642; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_d_o_cry_2_0_3643; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_d_o_cry_1_3644; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_d_o_cry_3_0_3645; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_d_o_cry_2_3646; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_d_o_cry_4_0_3647; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_d_o_cry_3_3648; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_d_o_cry_5_0_3649; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_d_o_cry_4_3650; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_d_o_cry_5_3651; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_d_o_cry_6_3652; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_d_o_cry_7_3653; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_d_o_cry_8_3654; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_d_o_cry_9_3655; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_d_o_cry_10_3656; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un1_fc_d_con_1_cry_0_0_3657; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un1_fc_d_con_1_cry_1_0_3658; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un1_fc_d_con_1_s_1_0; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un1_fc_d_con_1_cry_0_3659; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un1_fc_d_con_1_cry_2_0_3660; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un1_fc_d_con_1_s_2_0; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un1_fc_d_con_1_cry_1_3661; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un1_fc_d_con_1_cry_3_0_3662; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un1_fc_d_con_1_s_3_0; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un1_fc_d_con_1_cry_2_3663; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un1_fc_d_con_1_cry_4_0_3664; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un1_fc_d_con_1_s_4_0; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un1_fc_d_con_1_cry_3_3665; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un1_fc_d_con_1_cry_5_0_3666; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un1_fc_d_con_1_s_5_0; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un1_fc_d_con_1_cry_4_3667; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un1_fc_d_con_1_s_6_0; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un1_fc_d_con_1_cry_5_3668; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un1_fc_d_con_1_s_7_0; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un1_fc_d_con_1_cry_6_3669; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un1_fc_d_con_1_s_8_0; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un1_fc_d_con_1_cry_7_3670; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un1_fc_d_con_1_s_9_0; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un1_fc_d_con_1_cry_8_3671; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un1_fc_d_con_1_s_10_0; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un1_fc_d_con_1_cry_9_3672; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un1_fc_d_con_1_s_11_0; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un1_fc_d_con_1_cry_10_3673; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un35_fc_h_av_o_s_1_3674; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un35_fc_h_av_o_cry_0_3675; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un35_fc_h_av_o_s_2_3676; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un35_fc_h_av_o_cry_1_3677; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un35_fc_h_av_o_s_3_3678; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un35_fc_h_av_o_cry_2_3679; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un35_fc_h_av_o_s_4_3680; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un35_fc_h_av_o_cry_3_3681; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un35_fc_h_av_o_s_5_3682; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un35_fc_h_av_o_cry_4_3683; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un35_fc_h_av_o_s_6_3684; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un35_fc_h_av_o_cry_5_3685; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un35_fc_h_av_o_s_7_3686; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un35_fc_h_av_o_cry_6_3687; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un36_fc_d_av_o_s_1_3688; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un36_fc_d_av_o_cry_0_3689; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un36_fc_d_av_o_s_2_3690; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un36_fc_d_av_o_cry_1_3691; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un36_fc_d_av_o_s_3_3692; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un36_fc_d_av_o_cry_2_3693; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un36_fc_d_av_o_s_4_3694; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un36_fc_d_av_o_cry_3_3695; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un36_fc_d_av_o_s_5_3696; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un36_fc_d_av_o_cry_4_3697; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un36_fc_d_av_o_s_6_3698; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un36_fc_d_av_o_cry_5_3699; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un36_fc_d_av_o_s_7_3700; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un36_fc_d_av_o_cry_6_3701; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un36_fc_d_av_o_s_8_3702; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un36_fc_d_av_o_cry_7_3703; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un36_fc_d_av_o_s_9_3704; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un36_fc_d_av_o_cry_8_3705; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un36_fc_d_av_o_s_10_3706; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un36_fc_d_av_o_cry_9_3707; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un36_fc_d_av_o_s_11_3708; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un36_fc_d_av_o_cry_10_3709; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un5_fc_h_advert_cry_0_3710; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un5_fc_h_advert_cry_1_3711; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un5_fc_h_advert_cry_2_3712; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un5_fc_h_advert_cry_3_3713; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un5_fc_h_advert_cry_4_3714; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un5_fc_h_advert_cry_5_3715; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un5_fc_h_advert_cry_6_3716; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_VCC_3717; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un5_fc_d_advert_cry_0_3718; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un5_fc_d_advert_cry_1_3719; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un5_fc_d_advert_cry_2_3720; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un5_fc_d_advert_cry_3_3721; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un5_fc_d_advert_cry_4_3722; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un5_fc_d_advert_cry_5_3723; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un5_fc_d_advert_cry_6_3724; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un5_fc_d_advert_cry_7_3725; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un5_fc_d_advert_cry_8_3726; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un5_fc_d_advert_cry_9_3727; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un5_fc_d_advert_cry_10_3728; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_GND_3729; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_free_hold34; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un1_fc_d_con_1_axb_0_3730; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_free_q2_3731; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_free_hold_3732; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_gnt; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un5_fc_d_advert_axb_11_3733; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un5_fc_h_advert_axb_7_3734; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_free_d_8; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_free_h_8; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_free_q_8; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_h_o_axb_7_3735; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_h_o_axb_6_3736; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_h_o_axb_5_3737; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_h_o_axb_4_3738; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_h_o_axb_3_3739; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_h_o_axb_2_3740; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_h_o_axb_1_3741; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_h_o_axb_0_3742; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un36_fc_d_av_o_axb_11_3743; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un36_fc_d_av_o_axb_10_3744; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un36_fc_d_av_o_axb_9_3745; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un36_fc_d_av_o_axb_8_3746; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un36_fc_d_av_o_axb_7_3747; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un36_fc_d_av_o_axb_6_3748; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un36_fc_d_av_o_axb_5_3749; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un36_fc_d_av_o_axb_4_3750; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un36_fc_d_av_o_axb_3_3751; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un36_fc_d_av_o_axb_2_3752; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un36_fc_d_av_o_axb_1_3753; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un36_fc_d_av_o_axb_0_i_3754; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un36_fc_d_av_o_axb_0_3755; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un35_fc_h_av_o_axb_7_3756; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un35_fc_h_av_o_axb_6_3757; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un35_fc_h_av_o_axb_5_3758; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un35_fc_h_av_o_axb_4_3759; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un35_fc_h_av_o_axb_3_3760; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un35_fc_h_av_o_axb_2_3761; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un35_fc_h_av_o_axb_1_3762; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un35_fc_h_av_o_axb_0_i_3763; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un35_fc_h_av_o_axb_0_3764; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_d_o_axb_11_3765; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_d_o_axb_10_3766; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_d_o_axb_9_3767; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_d_o_axb_8_3768; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_d_o_axb_7_3769; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_d_o_axb_6_3770; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_d_o_axb_5_3771; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_d_o_axb_4_3772; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_d_o_axb_3_3773; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_d_o_axb_2_3774; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_d_o_axb_1_3775; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_d_o_axb_0_3776; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_N_41750_i; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un1_fc_d_con_1_axb_11_3777; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un1_fc_d_con_1_axb_10_3778; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un1_fc_d_con_1_axb_9_3779; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un1_fc_d_con_1_axb_8_3780; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un1_fc_d_con_1_axb_7_3781; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un1_fc_d_con_1_axb_6_3782; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un1_fc_d_con_1_axb_5_3783; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un1_fc_d_con_1_axb_4_3784; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un1_fc_d_con_1_axb_3_3785; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un1_fc_d_con_1_axb_2_3786; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un1_fc_d_con_1_axb_1_3787; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_N_68905_i_3788; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_N_68906_i_3789; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_req_np_src_rdy; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_N_68907_i_3790; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_send_state_2__3791; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_send_state_0__3792; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_N_42049_i; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un5_fc_d_advert_s_11_3793; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un5_fc_h_advert_s_7_3794; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un5_fc_d_advert_axb_10_3795; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un5_fc_d_advert_axb_9_3796; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un5_fc_d_advert_axb_8_3797; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un5_fc_d_advert_axb_7_3798; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un5_fc_d_advert_axb_6_3799; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un5_fc_d_advert_axb_5_3800; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un5_fc_d_advert_axb_4_3801; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un5_fc_d_advert_axb_3_3802; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un5_fc_d_advert_axb_2_3803; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un5_fc_d_advert_axb_1_3804; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un5_fc_d_advert_axb_0_3805; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un5_fc_h_advert_axb_6_3806; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un5_fc_h_advert_axb_5_3807; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un5_fc_h_advert_axb_4_3808; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un5_fc_h_advert_axb_3_3809; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un5_fc_h_advert_axb_2_3810; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un5_fc_h_advert_axb_1_3811; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un5_fc_h_advert_axb_0_3812; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_h_o_2_cry_0_3813; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_h_o_2_cry_1_3814; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_h_o_2_cry_2_3815; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_h_o_2_cry_3_3816; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_h_o_2_cry_4_3817; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_h_o_2_cry_5_3818; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_h_o_2_cry_6_3819; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_2_cry_1_0_3820; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_2_cry_0_3821; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_2_cry_2_0_3822; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_2_cry_1_3823; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_2_cry_3_0_3824; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_2_cry_2_3825; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_2_cry_3_3826; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_2_cry_5_0_3827; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_2_cry_4_3828; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_2_cry_5_3829; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_2_cry_6_3830; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_2_cry_7_3831; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_2_cry_8_3832; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_2_cry_9_3833; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_2_cry_10_3834; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_d_con_2_cry_0_0_3835; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_d_con_2_cry_1_0_3836; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_d_con_2_s_1_3837; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_d_con_2_cry_0_3838; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_d_con_2_cry_2_0_3839; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_d_con_2_s_2_3840; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_d_con_2_cry_1_3841; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_d_con_2_cry_3_0_3842; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_d_con_2_s_3_3843; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_d_con_2_cry_2_3844; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_d_con_2_cry_4_0_3845; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_d_con_2_s_4_3846; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_d_con_2_cry_3_3847; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_d_con_2_cry_5_0_3848; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_d_con_2_s_5_3849; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_d_con_2_cry_4_3850; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_d_con_2_s_6_3851; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_d_con_2_cry_5_3852; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_d_con_2_s_7_3853; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_d_con_2_cry_6_3854; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_d_con_2_s_8_3855; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_d_con_2_cry_7_3856; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_d_con_2_s_9_3857; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_d_con_2_cry_8_3858; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_d_con_2_s_10_3859; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_d_con_2_cry_9_3860; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_d_con_2_s_11_3861; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_d_con_2_cry_10_3862; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_h_o_1_cry_1_0_3863; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_h_o_1_cry_0_3864; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_h_o_1_cry_1_3865; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_h_o_1_cry_3_0_3866; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_h_o_1_cry_2_3867; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_h_o_1_cry_4_0_3868; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_h_o_1_cry_3_3869; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_h_o_1_cry_4_3870; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_h_o_1_cry_6_0_3871; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_h_o_1_cry_5_3872; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_h_o_1_cry_6_3873; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_1_cry_1_0_3874; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_1_cry_0_3875; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_1_cry_2_0_3876; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_1_cry_1_3877; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_1_cry_3_0_3878; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_1_cry_2_3879; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_1_cry_3_3880; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_1_cry_5_0_3881; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_1_cry_4_3882; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_1_cry_6_0_3883; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_1_cry_5_3884; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_1_cry_6_3885; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_1_cry_8_0_3886; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_1_cry_7_3887; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_1_cry_9_0_3888; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_1_cry_8_3889; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_1_cry_10_0_3890; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_1_cry_9_3891; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_1_cry_10_3892; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_GND_3893; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_free_h_3894; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_free_d_3895; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_d_con_2_axb_0_3896; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_1_axb_0_3897; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_h_o_1_axb_3_3898; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_h_o_1_axb_2_3899; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_h_o_1_axb_1_3900; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_h_o_1_axb_0_3901; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_1_axb_11_3902; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_1_axb_10_3903; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_1_axb_9_3904; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_1_axb_8_3905; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_1_axb_7_3906; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_1_axb_6_3907; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_1_axb_5_3908; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_1_axb_4_3909; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_1_axb_3_3910; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_1_axb_2_3911; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_1_axb_1_3912; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_2_axb_2_3913; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_2_axb_1_3914; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_2_axb_0_3915; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_h_o_2_axb_7_3916; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_h_o_2_axb_6_3917; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_h_o_2_axb_5_3918; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_h_o_2_axb_4_3919; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_h_o_2_axb_3_3920; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_h_o_2_axb_2_3921; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_h_o_2_axb_1_3922; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_h_o_2_axb_0_3923; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_h_o_1_axb_7_3924; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_h_o_1_axb_6_3925; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_h_o_1_axb_5_3926; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_h_o_1_axb_4_3927; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_2_axb_11_3928; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_2_axb_10_3929; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_2_axb_9_3930; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_2_axb_8_3931; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_2_axb_7_3932; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_2_axb_6_3933; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_2_axb_5_3934; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_2_axb_4_3935; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_N_43127; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_2_axb_3_3936; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_free_d_13; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_free_h_13; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_d_con_2_axb_11_3937; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_d_con_2_axb_10_3938; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_d_con_2_axb_9_3939; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_d_con_2_axb_8_3940; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_d_con_2_axb_7_3941; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_d_con_2_axb_6_3942; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_d_con_2_axb_5_3943; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_d_con_2_axb_4_3944; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_d_con_2_axb_3_3945; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_d_con_2_axb_2_3946; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_d_con_2_axb_1_3947; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_N_42502_1; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_1_s_0_3948; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_h_o_1_s_3_3949; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_h_o_1_s_2_3950; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_h_o_1_s_1_3951; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_h_o_1_s_0_3952; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_1_s_11_3953; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_1_s_10_3954; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_1_s_9_3955; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_1_s_8_3956; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_1_s_7_3957; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_1_s_6_3958; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_1_s_5_3959; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_1_s_4_3960; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_1_s_3_3961; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_1_s_2_3962; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_1_s_1_3963; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_2_s_2_3964; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_2_s_1_3965; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_2_s_0_3966; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_h_o_2_s_7_3967; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_h_o_2_s_6_3968; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_h_o_2_s_5_3969; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_h_o_2_s_4_3970; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_h_o_2_s_3_3971; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_h_o_2_s_2_3972; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_h_o_2_s_1_3973; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_h_o_2_s_0_3974; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_h_o_1_s_7_3975; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_h_o_1_s_6_3976; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_h_o_1_s_5_3977; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_h_o_1_s_4_3978; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_2_s_11_3979; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_2_s_10_3980; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_2_s_9_3981; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_2_s_8_3982; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_2_s_7_3983; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_2_s_6_3984; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_2_s_5_3985; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_2_s_4_3986; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_2_s_3_3987; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_h_con_i_1__3988; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_h_con_i_3__3989; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_h_con_i_4__3990; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_h_con_i_6__3991; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_d_con_i_1__3992; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_d_con_i_2__3993; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_d_con_i_3__3994; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_d_con_i_5__3995; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_d_con_i_6__3996; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_d_con_i_8__3997; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_d_con_i_9__3998; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_d_con_i_10__3999; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_1_cry_0_ma_4000; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_1_cry_4_ma_4001; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_1_cry_7_ma_4002; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_N_9006_i_4003; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_h_o_1_cry_0_ma_4004; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_h_o_i_m2_i_m3_i_m3_0_0__4005; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_h_o_1_cry_2_ma_4006; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_h_o_i_m2_i_m3_i_m3_0_2__4007; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_h_o_1_cry_5_ma_4008; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_N_8995_i_4009; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_2_cry_0_ma_4010; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_i_m2_i_m3_i_m3_0_0__4011; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_2_cry_4_ma_4012; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_VCC_4013; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_i_m2_i_m3_i_m3_0_4__4014; + wire com_tlm_u_tlm_rx_data_snk_latch_1st_dword_q3_4015; + wire com_tlm_u_tlm_rx_data_snk_pwr_mgmt_mode_on_4016; + wire com_tlm_u_tlm_rx_data_snk_un4_cur_byte_ct_cry_0_4017; + wire com_tlm_u_tlm_rx_data_snk_un4_cur_byte_ct_cry_1_4018; + wire com_tlm_u_tlm_rx_data_snk_un4_cur_byte_ct_cry_2_4019; + wire com_tlm_u_tlm_rx_data_snk_un4_cur_byte_ct_cry_3_4020; + wire com_tlm_u_tlm_rx_data_snk_un4_cur_byte_ct_cry_4_4021; + wire com_tlm_u_tlm_rx_data_snk_un4_cur_byte_ct_cry_5_4022; + wire com_tlm_u_tlm_rx_data_snk_un4_cur_byte_ct_cry_6_4023; + wire com_tlm_u_tlm_rx_data_snk_un4_cur_byte_ct_cry_7_4024; + wire com_tlm_u_tlm_rx_data_snk_un4_cur_byte_ct_cry_8_4025; + wire com_tlm_u_tlm_rx_data_snk_un4_cur_byte_ct_cry_9_4026; + wire com_tlm_u_tlm_rx_data_snk_un4_cur_byte_ct_cry_10_4027; + wire com_tlm_u_tlm_rx_data_snk_latch_1st_dword_q1_4028; + wire com_tlm_u_tlm_rx_data_snk_un4_cur_byte_ct_s_11_sf_4029; + wire com_tlm_u_tlm_rx_data_snk_N_9484_i_4030; + wire com_tlm_u_tlm_rx_data_snk_N_36443_i; + wire com_tlm_u_tlm_rx_data_snk_N_36447; + wire com_tlm_u_tlm_rx_data_snk_N_36390_i; + wire com_tlm_u_tlm_rx_data_snk_un1_eof_q_2_1_4031; + wire com_tlm_u_tlm_rx_data_snk_tlp_uc; + wire com_tlm_u_tlm_rx_data_snk_cur_pm_msg_detect; + wire com_tlm_u_tlm_rx_data_snk_cur_hp_msg_detect; + wire com_tlm_u_tlm_rx_data_snk_N_36397_i; + wire com_tlm_u_tlm_rx_data_snk_N_36382_i; + wire com_tlm_u_tlm_rx_data_snk_src_rdy_o_8; + wire com_tlm_u_tlm_rx_data_snk_src_rdy_o_8_u_0_bm_4032; + wire com_tlm_u_tlm_rx_data_snk_src_rdy_o_8_u_0_am_4033; + wire com_tlm_u_tlm_rx_data_snk_cur_drop_4034; + wire com_tlm_u_tlm_rx_data_snk_dsc_o_5; + wire com_tlm_u_tlm_rx_data_snk_dsc_o_5_0_am_4035; + wire com_tlm_u_tlm_rx_data_snk_un4_cur_byte_ct_s_3_4036; + wire com_tlm_u_tlm_rx_data_snk_un4_cur_byte_ct_s_2_4037; + wire com_tlm_u_tlm_rx_data_snk_un4_cur_byte_ct_s_1_4038; + wire com_tlm_u_tlm_rx_data_snk_N_14699_i; + wire com_tlm_u_tlm_rx_data_snk_N_14696_i; + wire com_tlm_u_tlm_rx_data_snk_N_14694_i; + wire com_tlm_u_tlm_rx_data_snk_un4_cur_byte_ct_s_11_4039; + wire com_tlm_u_tlm_rx_data_snk_un4_cur_byte_ct_s_10_4040; + wire com_tlm_u_tlm_rx_data_snk_un4_cur_byte_ct_s_9_4041; + wire com_tlm_u_tlm_rx_data_snk_un4_cur_byte_ct_s_8_4042; + wire com_tlm_u_tlm_rx_data_snk_un4_cur_byte_ct_s_7_4043; + wire com_tlm_u_tlm_rx_data_snk_un4_cur_byte_ct_s_6_4044; + wire com_tlm_u_tlm_rx_data_snk_un4_cur_byte_ct_s_5_4045; + wire com_tlm_u_tlm_rx_data_snk_un4_cur_byte_ct_s_4_4046; + wire com_tlm_u_tlm_rx_data_snk_N_36645_1; + wire com_tlm_u_tlm_rx_data_snk_ds_np_i_4047; + wire com_tlm_u_tlm_rx_data_snk_packet_ip_4048; + wire com_tlm_u_tlm_rx_data_snk_cur_fulltype_oh_1_; + wire com_tlm_u_tlm_rx_data_snk_cur_cpl_ep_6; + wire com_tlm_u_tlm_rx_data_snk_N_36411_i; + wire com_tlm_u_tlm_rx_data_snk_err_tlp_malformed_o_3_4049; + wire com_tlm_u_tlm_rx_data_snk_N_13361_i; + wire com_tlm_u_tlm_rx_data_snk_N_13363_i; + wire com_tlm_u_tlm_rx_data_snk_N_36490; + wire com_tlm_u_tlm_rx_data_snk_eof_o_5; + wire com_tlm_u_tlm_rx_data_snk_rem_o_5; + wire com_tlm_u_tlm_rx_data_snk_remove_lastword_4050; + wire com_tlm_u_tlm_rx_data_snk_cur_cpl_abort_6; + wire com_tlm_u_tlm_rx_data_snk_cur_cpl_ur_6; + wire com_tlm_u_tlm_rx_data_snk_remove_lastword_6; + wire com_tlm_u_tlm_rx_data_snk_cur_length1_2_0_a2_0_a2_0_a2_0_a2_5_4051; + wire com_tlm_u_tlm_rx_data_snk_cur_length1_2_0_a2_0_a2_0_a2_0_a2_4_4052; + wire com_tlm_u_tlm_rx_data_snk_err_tlp_ur_o_3_4053; + wire com_tlm_u_tlm_rx_data_snk_tlp_ur; + wire com_tlm_u_tlm_rx_data_snk_malformed; + wire com_tlm_u_tlm_rx_data_snk_N_68789_i_4054; + wire com_tlm_u_tlm_rx_data_snk_N_69055_i_4055; + wire com_tlm_u_tlm_rx_data_snk_fc_use_cpl_o_5_4056; + wire com_tlm_u_tlm_rx_data_snk_fc_use_np_o_5_4057; + wire com_tlm_u_tlm_rx_data_snk_fc_use_p_o_5_4058; + wire com_tlm_u_tlm_rx_data_snk_N_36407_i; + wire com_tlm_u_tlm_rx_data_snk_fc_unuse_o_5_4059; + wire com_tlm_u_tlm_rx_data_snk_N_36409_i; + wire com_tlm_u_tlm_rx_data_snk_N_36395_i; + wire com_tlm_u_tlm_rx_data_snk_cur_fulltype_oh40_1; + wire com_tlm_u_tlm_rx_data_snk_stat_tlp_cpl_abort_o_5_4060; + wire com_tlm_u_tlm_rx_data_snk_cur_cpl_abort_4061; + wire com_tlm_u_tlm_rx_data_snk_stat_tlp_cpl_ep_o_5_4062; + wire com_tlm_u_tlm_rx_data_snk_cur_cpl_ep_4063; + wire com_tlm_u_tlm_rx_data_snk_stat_tlp_cpl_ur_o_5_4064; + wire com_tlm_u_tlm_rx_data_snk_cur_cpl_ur_4065; + wire com_tlm_u_tlm_rx_data_snk_stat_tlp_ep_o_5_4066; + wire com_tlm_u_tlm_rx_data_snk_N_36569_1; + wire com_tlm_u_tlm_rx_data_snk_N_36393_i; + wire com_tlm_u_tlm_rx_data_snk_dsc_o_5_0_bm_4067; + wire com_tlm_u_tlm_rx_data_snk_eof_nd_q_4_; + wire com_tlm_u_tlm_rx_data_snk_cur_byte_ct_6_3_; + wire com_tlm_u_tlm_rx_data_snk_N_36623_i_4068; + wire com_tlm_u_tlm_rx_data_snk_cur_byte_ct_6_1_; + wire com_tlm_u_tlm_rx_data_snk_cur_byte_ct_6_0_; + wire com_tlm_u_tlm_rx_data_snk_cur_bytes_missing_1_axb0_4069; + wire com_tlm_u_tlm_rx_data_snk_cur_byte_ct_6_11_; + wire com_tlm_u_tlm_rx_data_snk_cur_byte_ct_6_10_; + wire com_tlm_u_tlm_rx_data_snk_cur_byte_ct_6_9_; + wire com_tlm_u_tlm_rx_data_snk_cur_byte_ct_6_8_; + wire com_tlm_u_tlm_rx_data_snk_cur_byte_ct_6_7_; + wire com_tlm_u_tlm_rx_data_snk_cur_byte_ct_6_6_; + wire com_tlm_u_tlm_rx_data_snk_cur_byte_ct_6_5_; + wire com_tlm_u_tlm_rx_data_snk_cur_byte_ct_6_4_; + wire com_tlm_u_tlm_rx_data_snk_sof_q_5__4070; + wire com_tlm_u_tlm_rx_data_snk_rem_q_4_; + wire com_tlm_u_tlm_rx_data_snk_rem_q_5__4071; + wire com_tlm_u_tlm_rx_data_snk_eof_q_5__4072; + wire com_tlm_u_tlm_rx_data_snk_eof_q_1__4073; + wire com_tlm_u_tlm_rx_data_snk_eof_q_2__4074; + wire com_tlm_u_tlm_rx_data_snk_dsc_q_4_; + wire com_tlm_u_tlm_rx_data_snk_dsc_q_5__4075; + wire com_tlm_u_tlm_rx_data_snk_src_rdy_q_4_; + wire com_tlm_u_tlm_rx_data_snk_src_rdy_q_5__4076; + wire com_tlm_u_tlm_rx_data_snk_sof_q_4_; + wire com_tlm_u_tlm_rx_data_snk_cur_ep_q_4077; + wire com_tlm_u_tlm_rx_data_snk_cur_td_q_4078; + wire com_tlm_u_tlm_rx_data_snk_cur_ep_4079; + wire com_tlm_u_tlm_rx_data_snk_cur_td_4080; + wire com_tlm_u_tlm_rx_data_snk_cur_rem_0_sqmuxa; + wire com_tlm_u_tlm_rx_data_snk_cur_rem_4081; + wire com_tlm_u_tlm_rx_data_snk_latch_1st_dword_q2; + wire com_tlm_u_tlm_rx_data_snk_cur_np_2; + wire com_tlm_u_tlm_rx_data_snk_cur_tc0_2; + wire com_tlm_u_tlm_rx_data_snk_cur_tc0_4082; + wire com_tlm_u_tlm_rx_data_snk_cur_data_credits_vld; + wire com_tlm_u_tlm_rx_data_snk_eof_q_3__4083; + wire com_tlm_u_tlm_rx_data_snk_cur_cfg; + wire com_tlm_u_tlm_rx_data_snk_cur_cpl_4084; + wire com_tlm_u_tlm_rx_data_snk_latch_1st_dword_q4_4085; + wire com_tlm_u_tlm_rx_data_snk_cur_np_4086; + wire com_tlm_u_tlm_rx_data_snk_cur_length1_2; + wire com_tlm_u_tlm_rx_data_snk_cur_length1_4087; + wire com_tlm_u_tlm_rx_data_snk_N_9480_i; + wire com_tlm_u_tlm_rx_data_snk_cur_fulltype_64_4088; + wire com_tlm_u_tlm_rx_data_snk_cur_fulltype_mem12_i_i; + wire com_tlm_u_tlm_rx_data_snk_cur_fulltype_mem_4089; + wire com_tlm_u_tlm_rx_data_snk_N_21331_i; + wire com_tlm_u_tlm_rx_data_snk_N_21329_i; + wire com_tlm_u_tlm_rx_data_snk_N_21327_i; + wire com_tlm_u_tlm_rx_data_snk_N_21325_i; + wire com_tlm_u_tlm_rx_data_snk_latch_3rd_dword_q1; + wire com_tlm_u_tlm_rx_data_snk_N_21323_i; + wire com_tlm_u_tlm_rx_data_snk_N_9476_i; + wire com_tlm_u_tlm_rx_data_snk_cur_fulltype_oh_7__4090; + wire com_tlm_u_tlm_rx_data_snk_cur_fulltype_oh35_i_a2_0_a2_4091; + wire com_tlm_u_tlm_rx_data_snk_cur_fulltype_oh_5__4092; + wire com_tlm_u_tlm_rx_data_snk_cur_fulltype_oh37; + wire com_tlm_u_tlm_rx_data_snk_cur_fulltype_oh_3__4093; + wire com_tlm_u_tlm_rx_data_snk_latch_2nd_dword; + wire com_tlm_u_tlm_rx_data_snk_cur_fulltype_oh40; + wire com_tlm_u_tlm_rx_data_snk_cur_fulltype_oh_0__4094; + wire com_tlm_u_tlm_rx_data_snk_d_o_62_N_6; + wire com_tlm_u_tlm_rx_data_snk_d_o_61_N_6; + wire com_tlm_u_tlm_rx_data_snk_d_o_60_N_6; + wire com_tlm_u_tlm_rx_data_snk_d_o_59_N_6; + wire com_tlm_u_tlm_rx_data_snk_d_o_58_N_6; + wire com_tlm_u_tlm_rx_data_snk_d_o_57_N_6; + wire com_tlm_u_tlm_rx_data_snk_d_o_56_N_6; + wire com_tlm_u_tlm_rx_data_snk_d_o_55_N_6; + wire com_tlm_u_tlm_rx_data_snk_d_o_54_N_6; + wire com_tlm_u_tlm_rx_data_snk_d_o_53_N_6; + wire com_tlm_u_tlm_rx_data_snk_d_o_52_N_6; + wire com_tlm_u_tlm_rx_data_snk_d_o_51_N_6; + wire com_tlm_u_tlm_rx_data_snk_d_o_50_N_6; + wire com_tlm_u_tlm_rx_data_snk_d_o_49_N_6; + wire com_tlm_u_tlm_rx_data_snk_d_o_48_N_6; + wire com_tlm_u_tlm_rx_data_snk_d_o_47_N_6; + wire com_tlm_u_tlm_rx_data_snk_d_o_46_N_6; + wire com_tlm_u_tlm_rx_data_snk_d_o_45_N_6; + wire com_tlm_u_tlm_rx_data_snk_d_o_44_N_6; + wire com_tlm_u_tlm_rx_data_snk_d_o_43_N_6; + wire com_tlm_u_tlm_rx_data_snk_d_o_42_N_6; + wire com_tlm_u_tlm_rx_data_snk_d_o_41_N_6; + wire com_tlm_u_tlm_rx_data_snk_d_o_40_N_6; + wire com_tlm_u_tlm_rx_data_snk_d_o_39_N_6; + wire com_tlm_u_tlm_rx_data_snk_d_o_38_N_6; + wire com_tlm_u_tlm_rx_data_snk_d_o_37_N_6; + wire com_tlm_u_tlm_rx_data_snk_d_o_36_N_6; + wire com_tlm_u_tlm_rx_data_snk_d_o_35_N_6; + wire com_tlm_u_tlm_rx_data_snk_d_o_34_N_6; + wire com_tlm_u_tlm_rx_data_snk_d_o_33_N_6; + wire com_tlm_u_tlm_rx_data_snk_d_o_32_N_6; + wire com_tlm_u_tlm_rx_data_snk_d_o_31_N_6; + wire com_tlm_u_tlm_rx_data_snk_d_o_30_N_6; + wire com_tlm_u_tlm_rx_data_snk_d_o_29_N_6; + wire com_tlm_u_tlm_rx_data_snk_d_o_28_N_6; + wire com_tlm_u_tlm_rx_data_snk_d_o_27_N_6; + wire com_tlm_u_tlm_rx_data_snk_d_o_26_N_6; + wire com_tlm_u_tlm_rx_data_snk_d_o_25_N_6; + wire com_tlm_u_tlm_rx_data_snk_d_o_24_N_6; + wire com_tlm_u_tlm_rx_data_snk_d_o_23_N_6; + wire com_tlm_u_tlm_rx_data_snk_d_o_22_N_6; + wire com_tlm_u_tlm_rx_data_snk_d_o_21_N_6; + wire com_tlm_u_tlm_rx_data_snk_d_o_20_N_6; + wire com_tlm_u_tlm_rx_data_snk_d_o_19_N_6; + wire com_tlm_u_tlm_rx_data_snk_d_o_18_N_6; + wire com_tlm_u_tlm_rx_data_snk_d_o_17_N_6; + wire com_tlm_u_tlm_rx_data_snk_d_o_16_N_6; + wire com_tlm_u_tlm_rx_data_snk_N_13365_i; + wire com_tlm_u_tlm_rx_data_snk_d_o_15_N_6; + wire com_tlm_u_tlm_rx_data_snk_d_o_14_N_6; + wire com_tlm_u_tlm_rx_data_snk_d_o_13_N_6; + wire com_tlm_u_tlm_rx_data_snk_d_o_12_N_6; + wire com_tlm_u_tlm_rx_data_snk_d_o_11_N_6; + wire com_tlm_u_tlm_rx_data_snk_d_o_10_N_6; + wire com_tlm_u_tlm_rx_data_snk_d_o_9_N_6; + wire com_tlm_u_tlm_rx_data_snk_d_o_8_N_6; + wire com_tlm_u_tlm_rx_data_snk_dsc_q_1__4095; + wire com_tlm_u_tlm_rx_data_snk_dsc_q_N_6; + wire com_tlm_u_tlm_rx_data_snk_eof_nd_q_1__4096; + wire com_tlm_u_tlm_rx_data_snk_eof_nd_q_N_6; + wire com_tlm_u_tlm_rx_data_snk_d_o_7_N_6; + wire com_tlm_u_tlm_rx_data_snk_d_o_6_N_6; + wire com_tlm_u_tlm_rx_data_snk_d_o_5_N_6; + wire com_tlm_u_tlm_rx_data_snk_d_o_4_N_6; + wire com_tlm_u_tlm_rx_data_snk_d_o_3_N_6; + wire com_tlm_u_tlm_rx_data_snk_d_o_2_N_6; + wire com_tlm_u_tlm_rx_data_snk_d_o_1_N_6; + wire com_tlm_u_tlm_rx_data_snk_d_o_0_N_6; + wire com_tlm_u_tlm_rx_data_snk_d_o_N_6; + wire com_tlm_u_tlm_rx_data_snk_sof_q_1__4097; + wire com_tlm_u_tlm_rx_data_snk_sof_q_N_6; + wire com_tlm_u_tlm_rx_data_snk_rem_q_1__4098; + wire com_tlm_u_tlm_rx_data_snk_rem_q_N_6; + wire com_tlm_u_tlm_rx_data_snk_src_rdy_q_1__4099; + wire com_tlm_u_tlm_rx_data_snk_GND_4100; + wire com_tlm_u_tlm_rx_data_snk_VCC_4101; + wire com_tlm_u_tlm_rx_data_snk_src_rdy_q_N_6; + wire com_tlm_u_tlm_rx_data_snk_next_cur_drop_4102; + wire com_tlm_u_tlm_rx_data_snk_eof_o_3; + wire com_tlm_u_tlm_rx_data_snk_N_9481; + wire com_tlm_u_tlm_rx_data_snk_un4_cur_byte_ct_s_10_sf_4103; + wire com_tlm_u_tlm_rx_data_snk_un4_cur_byte_ct_s_9_sf_4104; + wire com_tlm_u_tlm_rx_data_snk_un4_cur_byte_ct_s_8_sf_4105; + wire com_tlm_u_tlm_rx_data_snk_un4_cur_byte_ct_s_7_sf_4106; + wire com_tlm_u_tlm_rx_data_snk_un4_cur_byte_ct_s_6_sf_4107; + wire com_tlm_u_tlm_rx_data_snk_un4_cur_byte_ct_s_5_sf_4108; + wire com_tlm_u_tlm_rx_data_snk_un4_cur_byte_ct_s_4_sf_4109; + wire com_tlm_u_tlm_rx_data_snk_un4_cur_byte_ct_s_3_sf_4110; + wire com_tlm_u_tlm_rx_data_snk_un4_cur_byte_ct_axb_2_4111; + wire com_tlm_u_tlm_rx_data_snk_un4_cur_byte_ct_axb_1_4112; + wire com_tlm_u_tlm_rx_data_snk_un4_cur_byte_ct_cry_0_sf_4113; + wire com_tlm_u_tlm_rx_data_snk_malformed_checks_sof_q3_4114; + wire com_tlm_u_tlm_rx_data_snk_malformed_checks_ur_pwr_mgmt_4115; + wire com_tlm_u_tlm_rx_data_snk_malformed_checks_uc_pwr_mgmt_4116; + wire com_tlm_u_tlm_rx_data_snk_malformed_checks_un6_malformed_maxsize_cry_0_4117; + wire com_tlm_u_tlm_rx_data_snk_malformed_checks_un6_malformed_maxsize_cry_1_4118; + wire com_tlm_u_tlm_rx_data_snk_malformed_checks_un6_malformed_maxsize_cry_2_4119; + wire com_tlm_u_tlm_rx_data_snk_malformed_checks_un6_malformed_maxsize_cry_3_4120; + wire com_tlm_u_tlm_rx_data_snk_malformed_checks_un6_malformed_maxsize_cry_4_4121; + wire com_tlm_u_tlm_rx_data_snk_malformed_checks_un6_malformed_maxsize_cry_5_4122; + wire com_tlm_u_tlm_rx_data_snk_malformed_checks_un6_malformed_maxsize_cry_6_4123; + wire com_tlm_u_tlm_rx_data_snk_malformed_checks_un6_malformed_maxsize_cry_7_4124; + wire com_tlm_u_tlm_rx_data_snk_malformed_checks_un6_malformed_maxsize_cry_8_4125; + wire com_tlm_u_tlm_rx_data_snk_malformed_checks_un1_data_credits_o_cry_0_4126; + wire com_tlm_u_tlm_rx_data_snk_malformed_checks_un1_data_credits_o_cry_1_4127; + wire com_tlm_u_tlm_rx_data_snk_malformed_checks_un1_data_credits_o_cry_2_4128; + wire com_tlm_u_tlm_rx_data_snk_malformed_checks_un1_data_credits_o_cry_3_4129; + wire com_tlm_u_tlm_rx_data_snk_malformed_checks_un1_data_credits_o_cry_4_4130; + wire com_tlm_u_tlm_rx_data_snk_malformed_checks_GND_4131; + wire com_tlm_u_tlm_rx_data_snk_malformed_checks_un4_word_ct_s_1_4132; + wire com_tlm_u_tlm_rx_data_snk_malformed_checks_un4_word_ct_cry_0_4133; + wire com_tlm_u_tlm_rx_data_snk_malformed_checks_un4_word_ct_s_2_4134; + wire com_tlm_u_tlm_rx_data_snk_malformed_checks_un4_word_ct_cry_1_4135; + wire com_tlm_u_tlm_rx_data_snk_malformed_checks_un4_word_ct_s_3_4136; + wire com_tlm_u_tlm_rx_data_snk_malformed_checks_un4_word_ct_cry_2_4137; + wire com_tlm_u_tlm_rx_data_snk_malformed_checks_un4_word_ct_s_4_4138; + wire com_tlm_u_tlm_rx_data_snk_malformed_checks_un4_word_ct_cry_3_4139; + wire com_tlm_u_tlm_rx_data_snk_malformed_checks_VCC_4140; + wire com_tlm_u_tlm_rx_data_snk_malformed_checks_un4_word_ct_s_5_4141; + wire com_tlm_u_tlm_rx_data_snk_malformed_checks_un4_word_ct_cry_4_4142; + wire com_tlm_u_tlm_rx_data_snk_malformed_checks_un4_word_ct_s_6_4143; + wire com_tlm_u_tlm_rx_data_snk_malformed_checks_un4_word_ct_cry_5_4144; + wire com_tlm_u_tlm_rx_data_snk_malformed_checks_eof_q2_4145; + wire com_tlm_u_tlm_rx_data_snk_malformed_checks_tlp_uc_o_0_sqmuxa; + wire com_tlm_u_tlm_rx_data_snk_malformed_checks_uc_format_4146; + wire com_tlm_u_tlm_rx_data_snk_malformed_checks_tlp_ur_o_0_sqmuxa; + wire com_tlm_u_tlm_rx_data_snk_malformed_checks_ur_format_4147; + wire com_tlm_u_tlm_rx_data_snk_malformed_checks_un1_data_credits_o_axb_5_4148; + wire com_tlm_u_tlm_rx_data_snk_malformed_checks_N_36605_i_4149; + wire com_tlm_u_tlm_rx_data_snk_malformed_checks_type_1dw_4150; + wire com_tlm_u_tlm_rx_data_snk_malformed_checks_malformed_message_4151; + wire com_tlm_u_tlm_rx_data_snk_malformed_checks_length_1dw_4152; + wire com_tlm_u_tlm_rx_data_snk_malformed_checks_malformed_over_3_i_0_o3_4_4153; + wire com_tlm_u_tlm_rx_data_snk_malformed_checks_cfg0_ip_0_sqmuxa; + wire com_tlm_u_tlm_rx_data_snk_malformed_checks_malformed_maxsize_3_0_0_a2_0_1_3_4154; + wire com_tlm_u_tlm_rx_data_snk_malformed_checks_N_36403_i_0; + wire com_tlm_u_tlm_rx_data_snk_malformed_checks_cfg1_ip_0_sqmuxa; + wire com_tlm_u_tlm_rx_data_snk_malformed_checks_cfg1_ip_0_sqmuxa_2; + wire com_tlm_u_tlm_rx_data_snk_malformed_checks_N_36479; + wire com_tlm_u_tlm_rx_data_snk_malformed_checks_N_36516; + wire com_tlm_u_tlm_rx_data_snk_malformed_checks_N_11858_i; + wire com_tlm_u_tlm_rx_data_snk_malformed_checks_type_1dw_0_sqmuxa_i_0_0_32148_4155; + wire com_tlm_u_tlm_rx_data_snk_malformed_checks_N_36398_i; + wire com_tlm_u_tlm_rx_data_snk_malformed_checks_delay_ctc_i; + wire com_tlm_u_tlm_rx_data_snk_malformed_checks_un1_data_credits_o_s_3_4156; + wire com_tlm_u_tlm_rx_data_snk_malformed_checks_un1_data_credits_o_s_2_4157; + wire com_tlm_u_tlm_rx_data_snk_malformed_checks_un1_data_credits_o_s_1_4158; + wire com_tlm_u_tlm_rx_data_snk_malformed_checks_un1_data_credits_o_s_0_4159; + wire com_tlm_u_tlm_rx_data_snk_malformed_checks_un1_data_credits_o_s_5_4160; + wire com_tlm_u_tlm_rx_data_snk_malformed_checks_un1_data_credits_o_s_4_4161; + wire com_tlm_u_tlm_rx_data_snk_malformed_checks_N_50795_i_4162; + wire com_tlm_u_tlm_rx_data_snk_malformed_checks_malformed_len_4163; + wire com_tlm_u_tlm_rx_data_snk_malformed_checks_malformed_fmt_4164; + wire com_tlm_u_tlm_rx_data_snk_malformed_checks_N_36604_i_4165; + wire com_tlm_u_tlm_rx_data_snk_malformed_checks_malformed_rem_4166; + wire com_tlm_u_tlm_rx_data_snk_malformed_checks_malformed_min_4167; + wire com_tlm_u_tlm_rx_data_snk_malformed_checks_malformed_eof_4168; + wire com_tlm_u_tlm_rx_data_snk_malformed_checks_msgcode_vendef12_0_a2_0_a2_1; + wire com_tlm_u_tlm_rx_data_snk_malformed_checks_is_usr_leg_ap_3; + wire com_tlm_u_tlm_rx_data_snk_malformed_checks_is_usr_leg_ap_3_0_a2_0_a2_0_a2_0_a2_2_4169; + wire com_tlm_u_tlm_rx_data_snk_malformed_checks_length_1dw_3; + wire com_tlm_u_tlm_rx_data_snk_malformed_checks_N_36455_2; + wire com_tlm_u_tlm_rx_data_snk_malformed_checks_N_21383_i; + wire com_tlm_u_tlm_rx_data_snk_malformed_checks_N_50796_i_4170; + wire com_tlm_u_tlm_rx_data_snk_malformed_checks_is_usr_leg_ap_4171; + wire com_tlm_u_tlm_rx_data_snk_malformed_checks_is_usr_ext_ap_4172; + wire com_tlm_u_tlm_rx_data_snk_malformed_checks_cfg1_ip_4173; + wire com_tlm_u_tlm_rx_data_snk_malformed_checks_cfg0_ip_4174; + wire com_tlm_u_tlm_rx_data_snk_malformed_checks_N_68230_i_4175; + wire com_tlm_u_tlm_rx_data_snk_malformed_checks_malformed_tc_4176; + wire com_tlm_u_tlm_rx_data_snk_malformed_checks_malformed_maxsize_4177; + wire com_tlm_u_tlm_rx_data_snk_malformed_checks_malformed_fulltype_4178; + wire com_tlm_u_tlm_rx_data_snk_malformed_checks_malformed_fmt_3_i_0_2_4179; + wire com_tlm_u_tlm_rx_data_snk_malformed_checks_uc_pwr_mgmt_7; + wire com_tlm_u_tlm_rx_data_snk_malformed_checks_uc_pwr_mgmt_7_0_a2_0_a2_0_a2_1_4180; + wire com_tlm_u_tlm_rx_data_snk_malformed_checks_malformed_rem_3_4181; + wire com_tlm_u_tlm_rx_data_snk_malformed_checks_N_36402_i; + wire com_tlm_u_tlm_rx_data_snk_malformed_checks_N_68324_i_4182; + wire com_tlm_u_tlm_rx_data_snk_malformed_checks_fulltype_tc012_i_0_0_4183; + wire com_tlm_u_tlm_rx_data_snk_malformed_checks_N_67836_i_4184; + wire com_tlm_u_tlm_rx_data_snk_malformed_checks_malformed_fulltype16_0_0_0_0_4185; + wire com_tlm_u_tlm_rx_data_snk_malformed_checks_malformed_fulltype16_0_0_0_32147_4186; + wire com_tlm_u_tlm_rx_data_snk_malformed_checks_msgcode_dmatch_4_0_x2_0_o3_0_1; + wire com_tlm_u_tlm_rx_data_snk_malformed_checks_msgcode_sigdef16_0_0_0_4187; + wire com_tlm_u_tlm_rx_data_snk_malformed_checks_msgcode_sigdef16_0_0_32156_4188; + wire com_tlm_u_tlm_rx_data_snk_malformed_checks_N_11860_i; + wire com_tlm_u_tlm_rx_data_snk_malformed_checks_ur_pwr_mgmt_7_i_0_0_0_4189; + wire com_tlm_u_tlm_rx_data_snk_malformed_checks_N_36412_i; + wire com_tlm_u_tlm_rx_data_snk_malformed_checks_N_24200_i; + wire com_tlm_u_tlm_rx_data_snk_malformed_checks_malformed_over_4190; + wire com_tlm_u_tlm_rx_data_snk_malformed_checks_N_69316_i_4191; + wire com_tlm_u_tlm_rx_data_snk_malformed_checks_un6_malformed_maxsize_cry_9_4192; + wire com_tlm_u_tlm_rx_data_snk_malformed_checks_malformed_maxsize_3_0_0_a2_0_1_4193; + wire com_tlm_u_tlm_rx_data_snk_malformed_checks_N_36455_1; + wire com_tlm_u_tlm_rx_data_snk_malformed_checks_N_9208_i_i; + wire com_tlm_u_tlm_rx_data_snk_malformed_checks_N_9208_i_0_0_0_32079_4194; + wire com_tlm_u_tlm_rx_data_snk_malformed_checks_N_36436; + wire com_tlm_u_tlm_rx_data_snk_malformed_checks_N_36392_i; + wire com_tlm_u_tlm_rx_data_snk_malformed_checks_N_9487_i_1; + wire com_tlm_u_tlm_rx_data_snk_malformed_checks_malformed_eof_3_i_0_a2_0_4_4195; + wire com_tlm_u_tlm_rx_data_snk_malformed_checks_cfg1_ip_0_sqmuxa_1; + wire com_tlm_u_tlm_rx_data_snk_malformed_checks_N_36601; + wire com_tlm_u_tlm_rx_data_snk_malformed_checks_N_36600; + wire com_tlm_u_tlm_rx_data_snk_malformed_checks_N_36599; + wire com_tlm_u_tlm_rx_data_snk_malformed_checks_N_36598; + wire com_tlm_u_tlm_rx_data_snk_malformed_checks_N_36603; + wire com_tlm_u_tlm_rx_data_snk_malformed_checks_N_36602; + wire com_tlm_u_tlm_rx_data_snk_malformed_checks_fulltype_in_5__4196; + wire com_tlm_u_tlm_rx_data_snk_malformed_checks_fulltype_in_0__4197; + wire com_tlm_u_tlm_rx_data_snk_malformed_checks_N_36385_i; + wire com_tlm_u_tlm_rx_data_snk_malformed_checks_msgcode_vendef12; + wire com_tlm_u_tlm_rx_data_snk_malformed_checks_N_68320_i_4198; + wire com_tlm_u_tlm_rx_data_snk_malformed_checks_routing_vendef_4199; + wire com_tlm_u_tlm_rx_data_snk_malformed_checks_N_68107_i_4200; + wire com_tlm_u_tlm_rx_data_snk_malformed_checks_fulltype_tc0_4201; + wire com_tlm_u_tlm_rx_data_snk_malformed_checks_N_9491_i; + wire com_tlm_u_tlm_rx_data_snk_malformed_checks_msgcode_hotplug_4202; + wire com_tlm_u_tlm_rx_data_snk_malformed_checks_N_36442_i_0; + wire com_tlm_u_tlm_rx_data_snk_malformed_checks_msgcode_dmatch_4203; + wire com_tlm_u_tlm_rx_data_snk_malformed_checks_N_9488_i; + wire com_tlm_u_tlm_rx_data_snk_malformed_checks_msgcode_sigdef_4204; + wire com_tlm_u_tlm_rx_data_snk_malformed_checks_msgcode_routing18_i_i; + wire com_tlm_u_tlm_rx_data_snk_malformed_checks_N_9487_i; + wire com_tlm_u_tlm_rx_data_snk_malformed_checks_delay_ct_i_4205; + wire com_tlm_u_tlm_rx_data_snk_malformed_checks_N_67910_i_4206; + wire com_tlm_u_tlm_rx_data_snk_malformed_checks_msgcode_vendef_4207; + wire com_tlm_u_tlm_rx_data_snk_malformed_checks_malformed_message_6_0_0_0_1_4208; + wire com_tlm_u_tlm_rx_data_snk_malformed_checks_N_67910_i_1_4209; + wire com_tlm_u_tlm_rx_data_snk_malformed_checks_N_36450; + wire com_tlm_u_tlm_rx_data_snk_malformed_checks_N_24198_i; + wire com_tlm_u_tlm_rx_data_snk_malformed_checks_malformed_eof_3_i_0_1_4210; + wire com_tlm_u_tlm_rx_data_snk_malformed_checks_delay_ct_4211; + wire com_tlm_u_tlm_rx_data_snk_malformed_checks_N_36439_i; + wire com_tlm_u_tlm_rx_data_snk_malformed_checks_un1_data_credits_o_axb_4_4212; + wire com_tlm_u_tlm_rx_data_snk_malformed_checks_un1_data_credits_o_axb_3_4213; + wire com_tlm_u_tlm_rx_data_snk_malformed_checks_un1_data_credits_o_axb_2_4214; + wire com_tlm_u_tlm_rx_data_snk_malformed_checks_un1_data_credits_o_axb_1_4215; + wire com_tlm_u_tlm_rx_data_snk_malformed_checks_un1_data_credits_o_axb_0_4216; + wire com_tlm_u_tlm_rx_data_snk_malformed_checks_un6_malformed_maxsize_axb_7_i_4217; + wire com_tlm_u_tlm_rx_data_snk_malformed_checks_un6_malformed_maxsize_axb_6_i_4218; + wire com_tlm_u_tlm_rx_data_snk_malformed_checks_un6_malformed_maxsize_axb_5_i_4219; + wire com_tlm_u_tlm_rx_data_snk_pwr_mgmt_cur_pm_as_nak_l1_6_0_a2_0_a2_0_a2_2_1_0_4220; + wire com_tlm_u_tlm_rx_data_snk_pwr_mgmt_N_9485_i_4221; + wire com_tlm_u_tlm_rx_data_snk_pwr_mgmt_pm_as_nak_l1_o_5_4222; + wire com_tlm_u_tlm_rx_data_snk_pwr_mgmt_cur_pm_as_nak_l1_4223; + wire com_tlm_u_tlm_rx_data_snk_pwr_mgmt_pm_set_slot_pwr_o_5_4224; + wire com_tlm_u_tlm_rx_data_snk_pwr_mgmt_cur_pm_set_slot_pwr_4225; + wire com_tlm_u_tlm_rx_data_snk_pwr_mgmt_pm_turn_off_o_5_4226; + wire com_tlm_u_tlm_rx_data_snk_pwr_mgmt_un1_eof_q_2; + wire com_tlm_u_tlm_rx_data_snk_pwr_mgmt_cur_pm_turn_off_4227; + wire com_tlm_u_tlm_rx_data_snk_pwr_mgmt_cur_pm_as_nak_l1_6; + wire com_tlm_u_tlm_rx_data_snk_pwr_mgmt_cur_pm_set_slot_pwr_6; + wire com_tlm_u_tlm_rx_data_snk_pwr_mgmt_cur_pm_set_slot_pwr_6_1; + wire com_tlm_u_tlm_rx_data_snk_pwr_mgmt_cur_pm_turn_off_6; + wire com_tlm_u_tlm_rx_data_snk_pwr_mgmt_cur_pm_turn_off_6_0_a2_0_a2_0_a2_1_4228; + wire com_tlm_u_tlm_rx_data_snk_pwr_mgmt_cur_pm_as_nak_l1_6_2_0_1; + wire com_tlm_u_tlm_rx_data_snk_pwr_mgmt_un1_act_pwr_mgmt_i_1_i_4229; + wire com_tlm_u_tlm_rx_data_snk_pwr_mgmt_act_pwr_mgmt_q1_4230; + wire com_tlm_u_tlm_rx_data_snk_bar_hit_check_rio_o_5; + wire com_tlm_u_tlm_rx_data_snk_bar_hit_check_rmem64_o_5; + wire com_tlm_u_tlm_rx_data_snk_bar_hit_check_rmem32_o_5; + wire com_tlm_u_tlm_rx_data_snk_bar_hit_N_68321_i_4231; + wire com_tlm_u_tlm_rx_data_snk_bar_hit_N_68311_i_4232; + wire com_tlm_u_tlm_rx_data_snk_bar_hit_N_68312_i_4233; + wire com_tlm_u_tlm_rx_data_snk_bar_hit_N_68313_i_4234; + wire com_tlm_u_tlm_rx_data_snk_bar_hit_N_68314_i_4235; + wire com_tlm_u_tlm_rx_data_snk_bar_hit_N_68315_i_4236; + wire com_tlm_u_tlm_rx_data_snk_bar_hit_N_68316_i_4237; + wire com_tlm_u_tlm_rx_data_snk_bar_hit_N_68317_i_4238; + wire com_tlm_u_tlm_rx_data_snk_bar_hit_N_68307_i_4239; + wire com_tlm_u_tlm_rx_data_snk_bar_hit_N_68308_i_4240; + wire com_tlm_u_tlm_rx_data_snk_bar_hit_N_68309_i_4241; + wire com_tlm_u_tlm_rx_data_snk_bar_hit_N_68310_i_4242; + wire com_tlm_u_tlm_rx_data_snk_bar_hit_N_68322_i_4243; + wire com_tlm_u_tlm_rx_data_snk_bar_hit_N_68323_i_4244; + wire com_tlm_u_tlm_rx_data_snk_bar_hit_N_68318_i_4245; + wire com_tlm_u_tlm_rx_data_snk_bar_hit_N_68319_i_4246; + wire com_tlm_u_tlm_rx_fc_src_GND_4247; + wire com_tlm_u_tlm_rx_fc_src_lnk_tfc_src_rdy; + wire com_tlm_u_tlm_rx_fc_src_init_pending_4248; + wire com_tlm_u_tlm_rx_fc_src_lnk_tfc_src_rdy_o_0_sqmuxa_i_i_a2_0_a2_4249; + wire com_tlm_u_tlm_rx_fc_src_N_43114; + wire com_tlm_u_tlm_rx_fc_src_N_43113; + wire com_tlm_u_tlm_rx_fc_src_N_68915_i_4250; + wire com_tlm_u_tlm_rx_fc_src_N_68006_i_4251; + wire com_tlm_u_tlm_rx_fc_src_N_42461; + wire com_tlm_u_tlm_rx_fc_src_initFC_stc_4252; + wire com_tlm_u_tlm_rx_fc_src_initFC_stc_0_i; + wire com_tlm_u_tlm_rx_fc_src_fc_sched_np_o_5; + wire com_tlm_u_tlm_rx_fc_src_np_pending_4253; + wire com_tlm_u_tlm_rx_fc_src_fc_sched_p_o_5; + wire com_tlm_u_tlm_rx_fc_src_p_pending_4254; + wire com_tlm_u_tlm_rx_fc_src_N_41449_i; + wire com_tlm_u_tlm_rx_fc_src_N_41451_i; + wire com_tlm_u_tlm_rx_fc_src_np_pending_6; + wire com_tlm_u_tlm_rx_fc_src_lnk_tfc_data_o_0_sqmuxa; + wire com_tlm_u_tlm_rx_fc_src_N_13880_i; + wire com_tlm_u_tlm_rx_fc_src_init2_seq_det_4255; + wire com_tlm_u_tlm_rx_fc_src_lnk_tfc_data_o_11_i_0_0_11_32180_4256; + wire com_tlm_u_tlm_rx_fc_src_N_51516; + wire com_tlm_u_tlm_rx_fc_src_lnk_tfc_data_o_11_i_0_0_10_32181_4257; + wire com_tlm_u_tlm_rx_fc_src_N_51515; + wire com_tlm_u_tlm_rx_fc_src_lnk_tfc_data_o_11_i_0_0_9_32182_4258; + wire com_tlm_u_tlm_rx_fc_src_N_51514; + wire com_tlm_u_tlm_rx_fc_src_lnk_tfc_data_o_11_i_0_0_8_32164_4259; + wire com_tlm_u_tlm_rx_fc_src_N_51513; + wire com_tlm_u_tlm_rx_fc_src_lnk_tfc_data_o_11_i_0_0_7_32165_4260; + wire com_tlm_u_tlm_rx_fc_src_N_51512; + wire com_tlm_u_tlm_rx_fc_src_lnk_tfc_data_o_11_i_0_0_6_32166_4261; + wire com_tlm_u_tlm_rx_fc_src_N_51511; + wire com_tlm_u_tlm_rx_fc_src_lnk_tfc_data_o_11_i_0_0_5_32162_4262; + wire com_tlm_u_tlm_rx_fc_src_N_51510; + wire com_tlm_u_tlm_rx_fc_src_lnk_tfc_data_o_11_i_0_0_4_32167_4263; + wire com_tlm_u_tlm_rx_fc_src_N_51509; + wire com_tlm_u_tlm_rx_fc_src_lnk_tfc_data_o_11_i_0_0_3_32168_4264; + wire com_tlm_u_tlm_rx_fc_src_N_51508; + wire com_tlm_u_tlm_rx_fc_src_lnk_tfc_data_o_11_i_0_0_2_32169_4265; + wire com_tlm_u_tlm_rx_fc_src_N_51507; + wire com_tlm_u_tlm_rx_fc_src_lnk_tfc_data_o_11_i_0_0_1_32170_4266; + wire com_tlm_u_tlm_rx_fc_src_N_51506; + wire com_tlm_u_tlm_rx_fc_src_lnk_tfc_data_o_11_i_0_0_0_32171_4267; + wire com_tlm_u_tlm_rx_fc_src_N_51505; + wire com_tlm_u_tlm_rx_fc_src_lnk_tfc_header_o_11_3_a2_i_0_7_32163_4268; + wire com_tlm_u_tlm_rx_fc_src_N_51524; + wire com_tlm_u_tlm_rx_fc_src_lnk_tfc_header_o_11_i_0_0_6_32176_4269; + wire com_tlm_u_tlm_rx_fc_src_N_51523; + wire com_tlm_u_tlm_rx_fc_src_lnk_tfc_header_o_11_i_0_0_5_32177_4270; + wire com_tlm_u_tlm_rx_fc_src_N_51522; + wire com_tlm_u_tlm_rx_fc_src_lnk_tfc_header_o_11_3_a2_i_0_4_32172_4271; + wire com_tlm_u_tlm_rx_fc_src_N_51521; + wire com_tlm_u_tlm_rx_fc_src_lnk_tfc_header_o_11_3_a2_i_0_3_32173_4272; + wire com_tlm_u_tlm_rx_fc_src_N_51520; + wire com_tlm_u_tlm_rx_fc_src_lnk_tfc_header_o_11_3_a2_i_0_2_32174_4273; + wire com_tlm_u_tlm_rx_fc_src_N_51519; + wire com_tlm_u_tlm_rx_fc_src_lnk_tfc_header_o_11_i_0_0_1_32178_4274; + wire com_tlm_u_tlm_rx_fc_src_N_51518; + wire com_tlm_u_tlm_rx_fc_src_lnk_tfc_header_o_11_i_0_0_0_32179_4275; + wire com_tlm_u_tlm_rx_fc_src_N_51517; + wire com_tlm_u_tlm_rx_fc_src_N_41729_i; + wire com_tlm_u_tlm_rx_fc_src_N_18216_i; + wire com_tlm_u_tlm_rx_fc_src_np_vld_4276; + wire com_tlm_u_tlm_rx_fc_src_N_41806_i; + wire com_tlm_u_tlm_rx_fc_src_N_41811_i; + wire com_tlm_u_tlm_rx_fc_src_un1_initFC_st_10_0_a2_0_a2_0_a2_4277; + wire com_tlm_u_tlm_rx_fc_src_p_vld_4278; + wire com_tlm_u_tlm_rx_fc_src_N_12919_i; + wire com_tlm_u_tlm_rx_fc_src_N_12917_i; + wire com_tlm_u_tlm_rx_fc_src_N_12915_i; + wire com_tlm_u_tlm_rx_fc_src_N_12913_i; + wire com_tlm_u_tlm_rx_fc_src_N_12911_i; + wire com_tlm_u_tlm_rx_fc_src_N_12909_i; + wire com_tlm_u_tlm_rx_fc_src_N_12907_i; + wire com_tlm_u_tlm_rx_fc_src_N_12905_i; + wire com_tlm_u_tlm_rx_fc_src_N_12903_i; + wire com_tlm_u_tlm_rx_fc_src_N_12901_i; + wire com_tlm_u_tlm_rx_fc_src_N_12899_i; + wire com_tlm_u_tlm_rx_fc_src_N_12897_i; + wire com_tlm_u_tlm_rx_fc_src_N_34413_i; + wire com_tlm_u_tlm_rx_fc_src_N_12930_i; + wire com_tlm_u_tlm_rx_fc_src_N_12928_i; + wire com_tlm_u_tlm_rx_fc_src_N_34411_i; + wire com_tlm_u_tlm_rx_fc_src_N_34409_i; + wire com_tlm_u_tlm_rx_fc_src_N_34407_i; + wire com_tlm_u_tlm_rx_fc_src_N_12923_i; + wire com_tlm_u_tlm_rx_fc_src_N_12921_i; + wire com_tlm_u_tlm_rx_fc_src_un1_initFC_st_2_0_a2_0_a2_0_a2_4279; + wire com_tlm_u_tlm_rx_fc_src_N_41729_i_i_4280; + wire com_tlm_u_tlm_rx_fc_src_N_68992_i_4281; + wire com_tlm_u_tlm_rx_fc_src_N_42600_i_4282; + wire com_tlm_u_tlm_rx_fc_src_N_42600; + wire com_cmm_gnt_arbiter; + wire com_cmm_pme_ack_bar; + wire com_cmm_cmm_arb_pend_req_n; + wire com_cmm_gnt_pm; + wire com_cmm_N_48915_i; + wire com_cmm_N_42917_i; + wire com_cmm_gnt_errman; + wire com_cmm_N_48927_i; + wire com_cmm_detectedparityerror; + wire com_cmm_masterdataparityerror; + wire com_cmm_receivedmasterabort; + wire com_cmm_receivedtargetabort; + wire com_cmm_pme_sent; + wire com_cmm_signaledsystemerror; + wire com_cmm_signaledtargetabort; + wire com_cmm_detectedcorrectable; + wire com_cmm_detectedfatal; + wire com_cmm_detectednonfatal; + wire com_cmm_unsupportedreq; + wire com_cmm_N_48884_i; + wire com_cmm_N_48883_i; + wire com_cmm_bar0_reg_4_; + wire com_cmm_bar0_reg_22_; + wire com_cmm_bar0_reg_10_; + wire com_cmm_bar0_reg_12_; + wire com_cmm_bar0_reg_24_; + wire com_cmm_bar0_reg_14_; + wire com_cmm_bar0_reg_18_; + wire com_cmm_bar0_reg_20_; + wire com_cmm_bar0_reg_16_; + wire com_cmm_bar0_reg_6_; + wire com_cmm_bar0_reg_26_; + wire com_cmm_bar0_reg_28_; + wire com_cmm_bar0_reg_8_; + wire com_cmm_bar0_reg_30_; + wire com_cmm_bar0_reg_0_; + wire com_cmm_bar0_reg_1_; + wire com_cmm_bar0_reg_2_; + wire com_cmm_bar0_reg_5_; + wire com_cmm_bar0_reg_31_; + wire com_cmm_bar0_reg_23_; + wire com_cmm_bar0_reg_11_; + wire com_cmm_bar0_reg_13_; + wire com_cmm_bar0_reg_25_; + wire com_cmm_bar0_reg_15_; + wire com_cmm_bar0_reg_19_; + wire com_cmm_bar0_reg_21_; + wire com_cmm_bar0_reg_17_; + wire com_cmm_bar0_reg_7_; + wire com_cmm_bar0_reg_27_; + wire com_cmm_bar0_reg_29_; + wire com_cmm_bar0_reg_9_; + wire com_cmm_xrom_reg_11_; + wire com_cmm_xrom_reg_29_; + wire com_cmm_xrom_reg_15_; + wire com_cmm_xrom_reg_17_; + wire com_cmm_xrom_reg_21_; + wire com_cmm_xrom_reg_27_; + wire com_cmm_xrom_reg_23_; + wire com_cmm_xrom_reg_25_; + wire com_cmm_xrom_reg_13_; + wire com_cmm_xrom_reg_19_; + wire com_cmm_xrom_reg_31_; + wire com_cmm_xrom_reg_0_; + wire com_cmm_xrom_reg_12_; + wire com_cmm_xrom_reg_30_; + wire com_cmm_xrom_reg_16_; + wire com_cmm_xrom_reg_18_; + wire com_cmm_xrom_reg_22_; + wire com_cmm_xrom_reg_28_; + wire com_cmm_xrom_reg_24_; + wire com_cmm_xrom_reg_26_; + wire com_cmm_xrom_reg_14_; + wire com_cmm_xrom_reg_20_; + wire com_cmm_next_state11_1; + wire com_cmm_state_1_; + wire com_cmm_state_6_; + wire com_cmm_tlm2cfg_wrdata_16_; + wire com_cmm_tlm2cfg_wrdata_0_; + wire com_cmm_tlm2cfg_wrdata_1_; + wire com_cmm_tlm2cfg_wrdata_2_; + wire com_cmm_tlm2cfg_wrdata_3_; + wire com_cmm_tlm2cfg_wrdata_4_; + wire com_cmm_tlm2cfg_wrdata_7_; + wire com_cmm_tlm2cfg_wrdata_6_; + wire com_cmm_tlm2cfg_wrdata_5_; + wire com_cmm_tlp_data_64_; + wire com_cmm_tlp_data_65_; + wire com_cmm_tlp_data_66_; + wire com_cmm_tlp_data_67_; + wire com_cmm_tlp_data_68_; + wire com_cmm_tlp_data_69_; + wire com_cmm_tlp_data_70_; + wire com_cmm_tlp_data_71_; + wire com_cmm_tlp_data_72_; + wire com_cmm_tlp_data_73_; + wire com_cmm_tlp_data_74_; + wire com_cmm_tlp_data_75_; + wire com_cmm_tlp_data_76_; + wire com_cmm_tlp_data_77_; + wire com_cmm_tlp_data_78_; + wire com_cmm_tlp_data_79_; + wire com_cmm_tlp_data_80_; + wire com_cmm_tlp_data_81_; + wire com_cmm_tlp_data_82_; + wire com_cmm_tlp_data_83_; + wire com_cmm_tlp_data_84_; + wire com_cmm_tlp_data_85_; + wire com_cmm_tlp_data_86_; + wire com_cmm_tlp_data_87_; + wire com_cmm_tlp_data_88_; + wire com_cmm_tlp_data_89_; + wire com_cmm_tlp_data_90_; + wire com_cmm_tlp_data_91_; + wire com_cmm_tlp_data_92_; + wire com_cmm_tlp_data_93_; + wire com_cmm_tlp_data_94_; + wire com_cmm_tlp_data_95_; + wire com_cmm_tlp_data_96_; + wire com_cmm_tlp_data_97_; + wire com_cmm_tlp_data_98_; + wire com_cmm_tlp_data_99_; + wire com_cmm_tlp_data_100_; + wire com_cmm_tlp_data_101_; + wire com_cmm_tlp_data_102_; + wire com_cmm_tlp_data_103_; + wire com_cmm_tlp_data_104_; + wire com_cmm_tlp_data_105_; + wire com_cmm_tlp_data_106_; + wire com_cmm_tlp_data_107_; + wire com_cmm_tlp_data_108_; + wire com_cmm_tlp_data_109_; + wire com_cmm_tlp_data_110_; + wire com_cmm_tlp_data_111_; + wire com_cmm_tlp_data_112_; + wire com_cmm_tlp_data_113_; + wire com_cmm_tlp_data_114_; + wire com_cmm_tlp_data_115_; + wire com_cmm_tlp_data_116_; + wire com_cmm_tlp_data_117_; + wire com_cmm_tlp_data_118_; + wire com_cmm_tlp_data_119_; + wire com_cmm_tlp_data_120_; + wire com_cmm_tlp_data_121_; + wire com_cmm_tlp_data_122_; + wire com_cmm_tlp_data_123_; + wire com_cmm_tlp_data_124_; + wire com_cmm_tlp_data_125_; + wire com_cmm_tlp_data_126_; + wire com_cmm_tlp_data_127_; + wire com_cmm_tlp_data_28_; + wire com_cmm_tlp_data_26_; + wire com_cmm_tlp_data_24_; + wire com_cmm_tlp_data_22_; + wire com_cmm_tlp_data_21_; + wire com_cmm_tlp_data_20_; + wire com_cmm_tlp_data_13_; + wire com_cmm_tlp_data_12_; + wire com_cmm_tlp_data_63_; + wire com_cmm_tlp_data_62_; + wire com_cmm_tlp_data_61_; + wire com_cmm_tlp_data_60_; + wire com_cmm_tlp_data_59_; + wire com_cmm_tlp_data_58_; + wire com_cmm_tlp_data_57_; + wire com_cmm_tlp_data_56_; + wire com_cmm_tlp_data_55_; + wire com_cmm_tlp_data_54_; + wire com_cmm_tlp_data_53_; + wire com_cmm_tlp_data_52_; + wire com_cmm_tlp_data_51_; + wire com_cmm_tlp_data_47_; + wire com_cmm_tlp_data_45_; + wire com_cmm_tlp_data_43_; + wire com_cmm_tlp_data_42_; + wire com_cmm_tlp_data_41_; + wire com_cmm_tlp_data_40_; + wire com_cmm_tlp_data_39_; + wire com_cmm_tlp_data_38_; + wire com_cmm_tlp_data_37_; + wire com_cmm_tlp_data_36_; + wire com_cmm_tlp_data_35_; + wire com_cmm_tlp_data_34_; + wire com_cmm_tlp_data_33_; + wire com_cmm_tlp_data_32_; + wire com_cmm_req_valid; + wire com_cmm_req_cfgctrl; + wire com_cmm_gnt_cfgctrl; + wire com_cmm_cfg_wr; + wire com_cmm_N_41751_i; + wire com_cmm_posnd_wr_pack; + wire com_cmm_cfg_rd; + wire com_cmm_N_48846_i; + wire com_cmm_type1_type0_bar; + wire com_cmm_bdf_err_rd_pack; + wire com_cmm_gnt_intr; + wire com_cmm_VCC_4283; + wire com_cmm_GND_4284; + wire com_cmm_req_intr; + wire com_cmm_signaledint; + wire com_cmm_rst_i_4285; + wire com_cmm_cfg_intr_rdy; + wire com_cmm_u_cmm_intr_un5_msi_64_0_4286; + wire com_cmm_u_cmm_intr_un5_msi_64_1_4287; + wire com_cmm_u_cmm_intr_un5_msi_64_2_4288; + wire com_cmm_u_cmm_intr_un5_msi_64_3_4289; + wire com_cmm_u_cmm_intr_un5_msi_64_4_4290; + wire com_cmm_u_cmm_intr_un5_msi_64_5_4291; + wire com_cmm_u_cmm_intr_un5_msi_64_6_4292; + wire com_cmm_u_cmm_intr_N_149_1; + wire com_cmm_u_cmm_intr_N_139_i; + wire com_cmm_u_cmm_intr_un5_msi_64_7_4293; + wire com_cmm_u_cmm_intr_N_264_i_4294; + wire com_cmm_u_cmm_intr_N_263_i_4295; + wire com_cmm_u_cmm_intr_N_262_i_4296; + wire com_cmm_u_cmm_intr_N_265_i_4297; + wire com_cmm_u_cmm_intr_intr_req_4298; + wire com_cmm_u_cmm_intr_intr_req_q_4299; + wire com_cmm_u_cmm_intr_un5_msi_64_7_and_4300; + wire com_cmm_u_cmm_intr_un5_msi_64_6_and_4301; + wire com_cmm_u_cmm_intr_un5_msi_64_5_and_4302; + wire com_cmm_u_cmm_intr_un5_msi_64_4_and_4303; + wire com_cmm_u_cmm_intr_un5_msi_64_3_and_4304; + wire com_cmm_u_cmm_intr_un5_msi_64_2_and_4305; + wire com_cmm_u_cmm_intr_un5_msi_64_1_and_4306; + wire com_cmm_u_cmm_intr_un5_msi_64_0_and_4307; + wire com_cmm_u_cmm_intr_GND_4308; + wire com_cmm_u_cmm_intr_VCC_4309; + wire com_cmm_u_rx_pkt_proc_idle_enable; + wire com_cmm_u_rx_pkt_proc_N_14881_i; + wire com_cmm_u_rx_pkt_proc_un1_dw1_enable_2_0_a2_0_a2_0_a2_0_a2_4310; + wire com_cmm_u_rx_pkt_proc_bdf_err_rd_pack_3_i_o3_0_4311; + wire com_cmm_u_rx_pkt_proc_bdf_err_rd_pack_3_i_0_2_4312; + wire com_cmm_u_rx_pkt_proc_N_42861; + wire com_cmm_u_rx_pkt_proc_N_32324_i; + wire com_cmm_u_rx_pkt_proc_ecrc_4313; + wire com_cmm_u_rx_pkt_proc_cfg_rd_3; + wire com_cmm_u_rx_pkt_proc_type1_type0_bar_3; + wire com_cmm_u_rx_pkt_proc_N_45877_2; + wire com_cmm_u_rx_pkt_proc_N_42531; + wire com_cmm_u_rx_pkt_proc_N_68112_i_4314; + wire com_cmm_u_rx_pkt_proc_posnd_wr_pack_6_i_i_0_0_4315; + wire com_cmm_u_rx_pkt_proc_cfg_wr_3; + wire com_cmm_u_rx_pkt_proc_N_68201_i_4316; + wire com_cmm_u_rx_pkt_proc_bdf_err_rd_pack_3_i_0_4_4317; + wire com_cmm_u_rx_pkt_proc_bdf_err_rd_pack_3_i_0_3_4318; + wire com_cmm_u_rx_pkt_proc_bdf_err_rd_pack_3_i_0_o4_0_4319; + wire com_cmm_u_rx_pkt_proc_N_42532; + wire com_cmm_u_rx_pkt_proc_N_68003_i_4320; + wire com_cmm_u_rx_pkt_proc_next_state_0_sqmuxa_3; + wire com_cmm_u_rx_pkt_proc_N_32102_i; + wire com_cmm_u_rx_pkt_proc_dw1_enable; + wire com_cmm_u_rx_pkt_proc_N_14883_i; + wire com_cmm_u_rx_pkt_proc_N_68909_i_4321; + wire com_cmm_u_tx_pkt_proc_TLP_data_reg_32__4322; + wire com_cmm_u_tx_pkt_proc_TLP_data_reg_33__4323; + wire com_cmm_u_tx_pkt_proc_TLP_data_reg_34__4324; + wire com_cmm_u_tx_pkt_proc_TLP_data_reg_35__4325; + wire com_cmm_u_tx_pkt_proc_TLP_data_reg_36__4326; + wire com_cmm_u_tx_pkt_proc_TLP_data_reg_37__4327; + wire com_cmm_u_tx_pkt_proc_TLP_data_reg_38__4328; + wire com_cmm_u_tx_pkt_proc_TLP_data_reg_39__4329; + wire com_cmm_u_tx_pkt_proc_TLP_data_reg_40__4330; + wire com_cmm_u_tx_pkt_proc_TLP_data_reg_41__4331; + wire com_cmm_u_tx_pkt_proc_TLP_data_reg_42__4332; + wire com_cmm_u_tx_pkt_proc_TLP_data_reg_43__4333; + wire com_cmm_u_tx_pkt_proc_TLP_data_reg_45__4334; + wire com_cmm_u_tx_pkt_proc_TLP_data_reg_47__4335; + wire com_cmm_u_tx_pkt_proc_TLP_data_reg_51__4336; + wire com_cmm_u_tx_pkt_proc_TLP_data_reg_52__4337; + wire com_cmm_u_tx_pkt_proc_TLP_data_reg_53__4338; + wire com_cmm_u_tx_pkt_proc_TLP_data_reg_54__4339; + wire com_cmm_u_tx_pkt_proc_TLP_data_reg_55__4340; + wire com_cmm_u_tx_pkt_proc_TLP_data_reg_56__4341; + wire com_cmm_u_tx_pkt_proc_TLP_data_reg_57__4342; + wire com_cmm_u_tx_pkt_proc_TLP_data_reg_58__4343; + wire com_cmm_u_tx_pkt_proc_TLP_data_reg_59__4344; + wire com_cmm_u_tx_pkt_proc_TLP_data_reg_60__4345; + wire com_cmm_u_tx_pkt_proc_TLP_data_reg_61__4346; + wire com_cmm_u_tx_pkt_proc_TLP_data_reg_62__4347; + wire com_cmm_u_tx_pkt_proc_TLP_data_reg_63__4348; + wire com_cmm_u_tx_pkt_proc_TLP_data_reg_12__4349; + wire com_cmm_u_tx_pkt_proc_TLP_data_reg_13__4350; + wire com_cmm_u_tx_pkt_proc_TLP_data_reg_20__4351; + wire com_cmm_u_tx_pkt_proc_TLP_data_reg_21__4352; + wire com_cmm_u_tx_pkt_proc_TLP_data_reg_22__4353; + wire com_cmm_u_tx_pkt_proc_TLP_data_reg_24__4354; + wire com_cmm_u_tx_pkt_proc_TLP_data_reg_26__4355; + wire com_cmm_u_tx_pkt_proc_TLP_data_reg_28__4356; + wire com_cmm_u_tx_pkt_proc_N_49941_i_4357; + wire com_cmm_u_tx_pkt_proc_N_48955_i; + wire com_cmm_u_tx_pkt_proc_N_49512; + wire com_cmm_u_tx_pkt_proc_TLP_data_reg_10_63_; + wire com_cmm_u_tx_pkt_proc_TLP_data_reg_10_62_; + wire com_cmm_u_tx_pkt_proc_TLP_data_reg_10_61_; + wire com_cmm_u_tx_pkt_proc_TLP_data_reg_10_60_; + wire com_cmm_u_tx_pkt_proc_TLP_data_reg_10_59_; + wire com_cmm_u_tx_pkt_proc_TLP_data_reg_10_58_; + wire com_cmm_u_tx_pkt_proc_TLP_data_reg_10_57_; + wire com_cmm_u_tx_pkt_proc_TLP_data_reg_10_56_; + wire com_cmm_u_tx_pkt_proc_TLP_data_reg_10_55_; + wire com_cmm_u_tx_pkt_proc_TLP_data_reg_10_54_; + wire com_cmm_u_tx_pkt_proc_TLP_data_reg_10_53_; + wire com_cmm_u_tx_pkt_proc_TLP_data_reg_10_52_; + wire com_cmm_u_tx_pkt_proc_TLP_data_reg_10_51_; + wire com_cmm_u_tx_pkt_proc_TLP_data_reg_10_50_; + wire com_cmm_u_tx_pkt_proc_TLP_data_reg_10_49_; + wire com_cmm_u_tx_pkt_proc_TLP_data_reg_10_48_; + wire com_cmm_u_tx_pkt_proc_TLP_data_reg_10_47_; + wire com_cmm_u_tx_pkt_proc_TLP_data_reg_10_46_; + wire com_cmm_u_tx_pkt_proc_TLP_data_reg_10_45_; + wire com_cmm_u_tx_pkt_proc_TLP_data_reg_10_44_; + wire com_cmm_u_tx_pkt_proc_TLP_data_reg_10_43_; + wire com_cmm_u_tx_pkt_proc_TLP_data_reg_10_42_; + wire com_cmm_u_tx_pkt_proc_TLP_data_reg_10_41_; + wire com_cmm_u_tx_pkt_proc_TLP_data_reg_10_40_; + wire com_cmm_u_tx_pkt_proc_TLP_data_reg_10_39_; + wire com_cmm_u_tx_pkt_proc_TLP_data_reg_10_38_; + wire com_cmm_u_tx_pkt_proc_TLP_data_reg_10_37_; + wire com_cmm_u_tx_pkt_proc_TLP_data_reg_10_36_; + wire com_cmm_u_tx_pkt_proc_TLP_data_reg_10_35_; + wire com_cmm_u_tx_pkt_proc_TLP_data_reg_10_34_; + wire com_cmm_u_tx_pkt_proc_TLP_data_reg_10_33_; + wire com_cmm_u_tx_pkt_proc_TLP_data_reg_10_32_; + wire com_cmm_u_tx_pkt_proc_N_28334_i; + wire com_cmm_u_tx_pkt_proc_N_28332_i; + wire com_cmm_u_tx_pkt_proc_N_28330_i; + wire com_cmm_u_tx_pkt_proc_N_28328_i; + wire com_cmm_u_tx_pkt_proc_N_28326_i; + wire com_cmm_u_tx_pkt_proc_N_28324_i; + wire com_cmm_u_tx_pkt_proc_N_28322_i; + wire com_cmm_u_tx_pkt_proc_N_28320_i; + wire com_cmm_u_tx_pkt_proc_N_28318_i; + wire com_cmm_u_tx_pkt_proc_N_28316_i; + wire com_cmm_u_tx_pkt_proc_N_28314_i; + wire com_cmm_u_tx_pkt_proc_N_28312_i; + wire com_cmm_u_tx_pkt_proc_N_28310_i; + wire com_cmm_u_tx_pkt_proc_N_28308_i; + wire com_cmm_u_tx_pkt_proc_N_28306_i; + wire com_cmm_u_tx_pkt_proc_N_28304_i; + wire com_cmm_u_tx_pkt_proc_N_48856_i; + wire com_cmm_u_tx_pkt_proc_TLP_data_reg_10_15_; + wire com_cmm_u_tx_pkt_proc_TLP_data_reg_10_14_; + wire com_cmm_u_tx_pkt_proc_TLP_data_reg_10_13_; + wire com_cmm_u_tx_pkt_proc_TLP_data_reg_10_12_; + wire com_cmm_u_tx_pkt_proc_TLP_data_reg_10_11_; + wire com_cmm_u_tx_pkt_proc_TLP_data_reg_10_10_; + wire com_cmm_u_tx_pkt_proc_TLP_data_reg_10_9_; + wire com_cmm_u_tx_pkt_proc_TLP_data_reg_10_8_; + wire com_cmm_u_tx_pkt_proc_TLP_data_reg_10_7_; + wire com_cmm_u_tx_pkt_proc_TLP_data_reg_10_6_; + wire com_cmm_u_tx_pkt_proc_TLP_data_reg_10_5_; + wire com_cmm_u_tx_pkt_proc_TLP_data_reg_10_4_; + wire com_cmm_u_tx_pkt_proc_TLP_data_reg_10_3_; + wire com_cmm_u_tx_pkt_proc_TLP_data_reg_10_2_; + wire com_cmm_u_tx_pkt_proc_TLP_data_reg_10_1_; + wire com_cmm_u_tx_pkt_proc_TLP_data_reg_10_0_; + wire com_cmm_u_tx_pkt_proc_N_8850_i; + wire com_cmm_u_tx_pkt_proc_N_13621_i; + wire com_cmm_u_tx_pkt_proc_N_68961_i_4358; + wire com_cmm_u_tx_pkt_proc_N_68152_i_4359; + wire com_cmm_u_cfg_ctrl_N_49544; + wire com_cmm_u_cfg_ctrl_N_49600_1; + wire com_cmm_u_cfg_ctrl_N_67939_i_4360; + wire com_cmm_u_cfg_ctrl_N_69000_i_4361; + wire com_cmm_u_cfg_ctrl_N_68910_i_4362; + wire com_cmm_u_cfg_ctrl_N_28302_i_i_i_4363; + wire com_cmm_u_cfg_ctrl_N_28302_i_i; + wire com_cmm_u_cmm_decoder_un11_bar34_64_hit_low_0_4364; + wire com_cmm_u_cmm_decoder_un11_bar34_64_hit_low_1_4365; + wire com_cmm_u_cmm_decoder_un11_bar34_64_hit_low_2_4366; + wire com_cmm_u_cmm_decoder_un11_bar34_64_hit_low_3_4367; + wire com_cmm_u_cmm_decoder_un11_bar34_64_hit_low_4_4368; + wire com_cmm_u_cmm_decoder_un11_bar34_64_hit_low_5_4369; + wire com_cmm_u_cmm_decoder_un11_bar34_64_hit_low_6_4370; + wire com_cmm_u_cmm_decoder_un11_bar5_32_hit_nc_0_4371; + wire com_cmm_u_cmm_decoder_un11_bar5_32_hit_nc_1_4372; + wire com_cmm_u_cmm_decoder_un11_bar5_32_hit_nc_2_4373; + wire com_cmm_u_cmm_decoder_un11_bar5_32_hit_nc_3_4374; + wire com_cmm_u_cmm_decoder_un11_bar5_32_hit_nc_4_4375; + wire com_cmm_u_cmm_decoder_un11_bar5_32_hit_nc_5_4376; + wire com_cmm_u_cmm_decoder_un11_bar5_32_hit_nc_6_4377; + wire com_cmm_u_cmm_decoder_un11_bar4_32_hit_nc_1_4378; + wire com_cmm_u_cmm_decoder_un11_bar4_32_hit_nc_2_4379; + wire com_cmm_u_cmm_decoder_un11_bar4_32_hit_nc_3_4380; + wire com_cmm_u_cmm_decoder_un11_bar4_32_hit_nc_4_4381; + wire com_cmm_u_cmm_decoder_un11_bar4_32_hit_nc_5_4382; + wire com_cmm_u_cmm_decoder_un11_bar4_32_hit_nc_6_4383; + wire com_cmm_u_cmm_decoder_un11_bar4_32_hit_nc_7_4384; + wire com_cmm_u_cmm_decoder_un11_bar3_32_hit_nc_0_4385; + wire com_cmm_u_cmm_decoder_un11_bar3_32_hit_nc_1_4386; + wire com_cmm_u_cmm_decoder_un11_bar3_32_hit_nc_2_4387; + wire com_cmm_u_cmm_decoder_un11_bar3_32_hit_nc_3_4388; + wire com_cmm_u_cmm_decoder_un11_bar3_32_hit_nc_4_4389; + wire com_cmm_u_cmm_decoder_un11_bar3_32_hit_nc_5_4390; + wire com_cmm_u_cmm_decoder_un11_bar3_32_hit_nc_6_4391; + wire com_cmm_u_cmm_decoder_un11_bar2_32_hit_nc_0_4392; + wire com_cmm_u_cmm_decoder_un11_bar2_32_hit_nc_1_4393; + wire com_cmm_u_cmm_decoder_un11_bar2_32_hit_nc_2_4394; + wire com_cmm_u_cmm_decoder_un11_bar2_32_hit_nc_3_4395; + wire com_cmm_u_cmm_decoder_un11_bar2_32_hit_nc_4_4396; + wire com_cmm_u_cmm_decoder_un11_bar2_32_hit_nc_5_4397; + wire com_cmm_u_cmm_decoder_un11_bar2_32_hit_nc_6_4398; + wire com_cmm_u_cmm_decoder_un11_bar1_32_hit_nc_0_4399; + wire com_cmm_u_cmm_decoder_un11_bar1_32_hit_nc_1_4400; + wire com_cmm_u_cmm_decoder_un11_bar1_32_hit_nc_2_4401; + wire com_cmm_u_cmm_decoder_un11_bar1_32_hit_nc_3_4402; + wire com_cmm_u_cmm_decoder_un11_bar1_32_hit_nc_4_4403; + wire com_cmm_u_cmm_decoder_un11_bar1_32_hit_nc_5_4404; + wire com_cmm_u_cmm_decoder_un11_bar1_32_hit_nc_6_4405; + wire com_cmm_u_cmm_decoder_un18_bar4_32_hit_nc_0_4406; + wire com_cmm_u_cmm_decoder_un18_bar4_32_hit_nc_1_4407; + wire com_cmm_u_cmm_decoder_un18_bar4_32_hit_nc_2_4408; + wire com_cmm_u_cmm_decoder_un18_bar4_32_hit_nc_3_4409; + wire com_cmm_u_cmm_decoder_un18_bar4_32_hit_nc_4_4410; + wire com_cmm_u_cmm_decoder_un18_bar4_32_hit_nc_5_4411; + wire com_cmm_u_cmm_decoder_un18_bar4_32_hit_nc_6_4412; + wire com_cmm_u_cmm_decoder_un18_bar3_32_hit_nc_0_4413; + wire com_cmm_u_cmm_decoder_un18_bar3_32_hit_nc_1_4414; + wire com_cmm_u_cmm_decoder_un18_bar3_32_hit_nc_2_4415; + wire com_cmm_u_cmm_decoder_un18_bar3_32_hit_nc_3_4416; + wire com_cmm_u_cmm_decoder_un18_bar3_32_hit_nc_4_4417; + wire com_cmm_u_cmm_decoder_un18_bar3_32_hit_nc_5_4418; + wire com_cmm_u_cmm_decoder_un18_bar3_32_hit_nc_6_4419; + wire com_cmm_u_cmm_decoder_un18_bar2_32_hit_nc_0_4420; + wire com_cmm_u_cmm_decoder_un18_bar2_32_hit_nc_1_4421; + wire com_cmm_u_cmm_decoder_un18_bar2_32_hit_nc_2_4422; + wire com_cmm_u_cmm_decoder_un18_bar2_32_hit_nc_3_4423; + wire com_cmm_u_cmm_decoder_un18_bar2_32_hit_nc_4_4424; + wire com_cmm_u_cmm_decoder_un18_bar2_32_hit_nc_5_4425; + wire com_cmm_u_cmm_decoder_un18_bar2_32_hit_nc_6_4426; + wire com_cmm_u_cmm_decoder_un18_bar1_32_hit_nc_0_4427; + wire com_cmm_u_cmm_decoder_un18_bar1_32_hit_nc_1_4428; + wire com_cmm_u_cmm_decoder_un18_bar1_32_hit_nc_2_4429; + wire com_cmm_u_cmm_decoder_un18_bar1_32_hit_nc_3_4430; + wire com_cmm_u_cmm_decoder_un18_bar1_32_hit_nc_4_4431; + wire com_cmm_u_cmm_decoder_un18_bar1_32_hit_nc_5_4432; + wire com_cmm_u_cmm_decoder_un18_bar1_32_hit_nc_6_4433; + wire com_cmm_u_cmm_decoder_un18_bar0_32_hit_nc_0_4434; + wire com_cmm_u_cmm_decoder_un18_bar0_32_hit_nc_1_4435; + wire com_cmm_u_cmm_decoder_un18_bar0_32_hit_nc_2_4436; + wire com_cmm_u_cmm_decoder_un18_bar0_32_hit_nc_3_4437; + wire com_cmm_u_cmm_decoder_un18_bar0_32_hit_nc_4_4438; + wire com_cmm_u_cmm_decoder_un18_bar0_32_hit_nc_5_4439; + wire com_cmm_u_cmm_decoder_un18_bar0_32_hit_nc_6_4440; + wire com_cmm_u_cmm_decoder_un11_bar0_32_hit_nc_0_4441; + wire com_cmm_u_cmm_decoder_un11_bar0_32_hit_nc_1_4442; + wire com_cmm_u_cmm_decoder_un11_bar0_32_hit_nc_2_4443; + wire com_cmm_u_cmm_decoder_un11_bar0_32_hit_nc_3_4444; + wire com_cmm_u_cmm_decoder_un11_bar0_32_hit_nc_4_4445; + wire com_cmm_u_cmm_decoder_un11_bar0_32_hit_nc_5_4446; + wire com_cmm_u_cmm_decoder_un11_bar0_32_hit_nc_6_4447; + wire com_cmm_u_cmm_decoder_VCC_4448; + wire com_cmm_u_cmm_decoder_un7_bar6_32_hit_nc_0_4449; + wire com_cmm_u_cmm_decoder_un7_bar6_32_hit_nc_1_4450; + wire com_cmm_u_cmm_decoder_un7_bar6_32_hit_nc_2_4451; + wire com_cmm_u_cmm_decoder_un7_bar6_32_hit_nc_3_4452; + wire com_cmm_u_cmm_decoder_un7_bar6_32_hit_nc_4_4453; + wire com_cmm_u_cmm_decoder_un7_bar6_32_hit_nc_5_4454; + wire com_cmm_u_cmm_decoder_un11_bar4_32_hit_nc_0; + wire com_cmm_u_cmm_decoder_N_6_9; + wire com_cmm_u_cmm_decoder_N_14_10; + wire com_cmm_u_cmm_decoder_N_22_9; + wire com_cmm_u_cmm_decoder_N_30_8; + wire com_cmm_u_cmm_decoder_N_38_9; + wire com_cmm_u_cmm_decoder_N_46_9; + wire com_cmm_u_cmm_decoder_N_54_9; + wire com_cmm_u_cmm_decoder_N_62_9; + wire com_cmm_u_cmm_decoder_N_70_9; + wire com_cmm_u_cmm_decoder_N_78_9; + wire com_cmm_u_cmm_decoder_N_86_9; + wire com_cmm_u_cmm_decoder_N_94_9; + wire com_cmm_u_cmm_decoder_N_102_14; + wire com_cmm_u_cmm_decoder_N_107_13; + wire com_cmm_u_cmm_decoder_N_110_6; + wire com_cmm_u_cmm_decoder_bar5_32_hit_nc_3_i_0_0_o3_0_4455; + wire com_cmm_u_cmm_decoder_un7_bar6_32_hit_nc_6_4456; + wire com_cmm_u_cmm_decoder_N_44866_i; + wire com_cmm_u_cmm_decoder_N_48989_i; + wire com_cmm_u_cmm_decoder_N_44997; + wire com_cmm_u_cmm_decoder_un18_bar0_32_hit_nc_7_4457; + wire com_cmm_u_cmm_decoder_bar0_32_hit_nc_3_i_0_0_0_4458; + wire com_cmm_u_cmm_decoder_un11_bar0_32_hit_nc_7_4459; + wire com_cmm_u_cmm_decoder_un18_bar4_32_hit_nc_7_4460; + wire com_cmm_u_cmm_decoder_un11_bar4_32_hit_nc_8_4461; + wire com_cmm_u_cmm_decoder_bar4_32_hit_nc_3_i_0_0_0_1_4462; + wire com_cmm_u_cmm_decoder_N_45436; + wire com_cmm_u_cmm_decoder_un18_bar3_32_hit_nc_7_4463; + wire com_cmm_u_cmm_decoder_bar3_32_hit_nc_3_i_0_1_4464; + wire com_cmm_u_cmm_decoder_un18_bar2_32_hit_nc_7_4465; + wire com_cmm_u_cmm_decoder_bar2_32_hit_nc_3_i_0_0_1_4466; + wire com_cmm_u_cmm_decoder_un18_bar1_32_hit_nc_7_4467; + wire com_cmm_u_cmm_decoder_bar1_32_hit_nc_3_i_0_0_1_4468; + wire com_cmm_u_cmm_decoder_un11_bar5_32_hit_nc_7_4469; + wire com_cmm_u_cmm_decoder_un11_bar34_64_hit_low_7_4470; + wire com_cmm_u_cmm_decoder_un11_bar3_32_hit_nc_7_4471; + wire com_cmm_u_cmm_decoder_un11_bar2_32_hit_nc_7_4472; + wire com_cmm_u_cmm_decoder_un11_bar1_32_hit_nc_7_4473; + wire com_cmm_u_cmm_decoder_bar23_64_hit_low_3_0_a2_0_a2_0; + wire com_cmm_u_cmm_decoder_bar4_32_hit_nc_3_i_0_0_0_0_4474; + wire com_cmm_u_cmm_decoder_bar3_32_hit_nc_3_i_0_0_4475; + wire com_cmm_u_cmm_decoder_bar1_32_hit_nc_3_i_0_0_0_4476; + wire com_cmm_u_cmm_decoder_N_45440; + wire com_cmm_u_cmm_decoder_bar2_32_hit_nc_3_i_0_0_0_4477; + wire com_cmm_u_cmm_decoder_N_49545; + wire com_cmm_u_cmm_decoder_N_45577; + wire com_cmm_u_cmm_decoder_N_45442; + wire com_cmm_u_cmm_decoder_I_10_0; + wire com_cmm_u_cmm_decoder_I_10_1; + wire com_cmm_u_cmm_decoder_I_10_2; + wire com_cmm_u_cmm_decoder_I_10_3; + wire com_cmm_u_cmm_decoder_I_10; + wire com_cmm_u_cmm_decoder_I_28_5; + wire com_cmm_u_cmm_decoder_I_28_4; + wire com_cmm_u_cmm_decoder_I_28_3; + wire com_cmm_u_cmm_decoder_I_28_2; + wire com_cmm_u_cmm_decoder_I_28_1; + wire com_cmm_u_cmm_decoder_GND_4478; + wire com_cmm_u_cmm_decoder_bar3_eq_raddr_3; + wire com_cmm_u_cmm_decoder_bar3_eq_raddr_4479; + wire com_cmm_u_cmm_decoder_bar2_eq_raddr_3; + wire com_cmm_u_cmm_decoder_bar2_eq_raddr_4480; + wire com_cmm_u_cmm_decoder_bar1_eq_raddr_3; + wire com_cmm_u_cmm_decoder_bar1_eq_raddr_4481; + wire com_cmm_u_cmm_decoder_bar0_eq_raddr_3; + wire com_cmm_u_cmm_decoder_bar0_eq_raddr_4482; + wire com_cmm_u_cmm_decoder_bar6_32_hit_nc_3; + wire com_cmm_u_cmm_decoder_bar6_32_hit_nc_4483; + wire com_cmm_u_cmm_decoder_N_15070_i; + wire com_cmm_u_cmm_decoder_bar5_32_hit_nc_4484; + wire com_cmm_u_cmm_decoder_bar6_eq_raddr_3; + wire com_cmm_u_cmm_decoder_bar6_eq_raddr_4485; + wire com_cmm_u_cmm_decoder_bar5_eq_raddr_3; + wire com_cmm_u_cmm_decoder_bar5_eq_raddr_4486; + wire com_cmm_u_cmm_decoder_bar4_eq_raddr_3; + wire com_cmm_u_cmm_decoder_bar4_eq_raddr_4487; + wire com_cmm_u_cmm_decoder_N_15260_i; + wire com_cmm_u_cmm_decoder_bar0_32_hit_nc_4488; + wire com_cmm_u_cmm_decoder_bar45_64_hit_high_3; + wire com_cmm_u_cmm_decoder_bar45_64_hit_high_4489; + wire com_cmm_u_cmm_decoder_bar34_64_hit_high_3; + wire com_cmm_u_cmm_decoder_bar34_64_hit_high_4490; + wire com_cmm_u_cmm_decoder_bar23_64_hit_high_3; + wire com_cmm_u_cmm_decoder_bar23_64_hit_high_4491; + wire com_cmm_u_cmm_decoder_bar12_64_hit_high_3; + wire com_cmm_u_cmm_decoder_bar12_64_hit_high_4492; + wire com_cmm_u_cmm_decoder_bar01_64_hit_high_3; + wire com_cmm_u_cmm_decoder_bar01_64_hit_high_4493; + wire com_cmm_u_cmm_decoder_N_15075_i; + wire com_cmm_u_cmm_decoder_bar4_32_hit_nc_4494; + wire com_cmm_u_cmm_decoder_N_28971_i; + wire com_cmm_u_cmm_decoder_bar3_32_hit_nc_4495; + wire com_cmm_u_cmm_decoder_N_15266_i; + wire com_cmm_u_cmm_decoder_bar2_32_hit_nc_4496; + wire com_cmm_u_cmm_decoder_N_15264_i; + wire com_cmm_u_cmm_decoder_bar1_32_hit_nc_4497; + wire com_cmm_u_cmm_decoder_bar45_64_hit_low_3; + wire com_cmm_u_cmm_decoder_bar45_64_hit_low_4498; + wire com_cmm_u_cmm_decoder_bar34_64_hit_low_3; + wire com_cmm_u_cmm_decoder_bar34_64_hit_low_4499; + wire com_cmm_u_cmm_decoder_bar23_64_hit_low_3; + wire com_cmm_u_cmm_decoder_bar23_64_hit_low_4500; + wire com_cmm_u_cmm_decoder_bar12_64_hit_low_3; + wire com_cmm_u_cmm_decoder_bar12_64_hit_low_4501; + wire com_cmm_u_cmm_decoder_bar01_64_hit_low_3; + wire com_cmm_u_cmm_decoder_bar01_64_hit_low_4502; + wire com_cmm_u_cmm_decoder_bar6_32_hit_4503; + wire com_cmm_u_cmm_decoder_N_15042_i_4504; + wire com_cmm_u_cmm_decoder_N_15043_i_4505; + wire com_cmm_u_cmm_decoder_N_15044_i_4506; + wire com_cmm_u_cmm_decoder_N_15045_i_4507; + wire com_cmm_u_cmm_decoder_N_15046_i_4508; + wire com_cmm_u_cmm_decoder_N_15047_i_4509; + wire com_cmm_u_cmm_decoder_N_99_14; + wire com_cmm_u_cmm_decoder_N_102_13; + wire com_cmm_u_cmm_decoder_N_99_13; + wire com_cmm_u_cmm_decoder_N_102_12; + wire com_cmm_u_cmm_decoder_N_99_12; + wire com_cmm_u_cmm_decoder_N_102_11; + wire com_cmm_u_cmm_decoder_N_99_11; + wire com_cmm_u_cmm_decoder_N_102_10; + wire com_cmm_u_cmm_decoder_N_99_10; + wire com_cmm_u_cmm_decoder_N_102_9; + wire com_cmm_u_cmm_decoder_N_99_9; + wire com_cmm_u_cmm_decoder_N_102_8; + wire com_cmm_u_cmm_decoder_N_99_8; + wire com_cmm_u_cmm_decoder_N_102_7; + wire com_cmm_u_cmm_decoder_N_99_7; + wire com_cmm_u_cmm_decoder_N_99_6; + wire com_cmm_u_cmm_decoder_N_99_5; + wire com_cmm_u_cmm_decoder_N_99_4; + wire com_cmm_u_cmm_decoder_I_10_sf; + wire com_cmm_u_cmm_decoder_N_99_3; + wire com_cmm_u_cmm_decoder_N_7_i; + wire com_cmm_u_cmm_decoder_N_99_2; + wire com_cmm_u_cmm_decoder_N_102_6; + wire com_cmm_u_cmm_decoder_N_99_1; + wire com_cmm_u_cmm_decoder_N_102_5; + wire com_cmm_u_cmm_decoder_N_99_0; + wire com_cmm_u_cmm_decoder_N_102_4; + wire com_cmm_u_cmm_decoder_N_99; + wire com_cmm_u_cmm_decoder_N_102_3; + wire com_cmm_u_cmm_decoder_un7_bar6_32_hit_nc_5_and; + wire com_cmm_u_cmm_decoder_un7_bar6_32_hit_nc_4_and; + wire com_cmm_u_cmm_decoder_un7_bar6_32_hit_nc_3_and; + wire com_cmm_u_cmm_decoder_un7_bar6_32_hit_nc_2_and; + wire com_cmm_u_cmm_decoder_un7_bar6_32_hit_nc_1_and; + wire com_cmm_u_cmm_decoder_un7_bar6_32_hit_nc_0_and_4510; + wire com_cmm_u_cmm_decoder_un11_bar0_32_hit_nc_7_and; + wire com_cmm_u_cmm_decoder_un11_bar0_32_hit_nc_6_and; + wire com_cmm_u_cmm_decoder_un11_bar0_32_hit_nc_5_and; + wire com_cmm_u_cmm_decoder_un11_bar0_32_hit_nc_4_and; + wire com_cmm_u_cmm_decoder_un11_bar0_32_hit_nc_3_and; + wire com_cmm_u_cmm_decoder_un11_bar0_32_hit_nc_2_and; + wire com_cmm_u_cmm_decoder_un11_bar0_32_hit_nc_1_and; + wire com_cmm_u_cmm_decoder_un11_bar0_32_hit_nc_0_and; + wire com_cmm_u_cmm_decoder_un18_bar0_32_hit_nc_7_and; + wire com_cmm_u_cmm_decoder_un18_bar0_32_hit_nc_6_and; + wire com_cmm_u_cmm_decoder_un18_bar0_32_hit_nc_5_and; + wire com_cmm_u_cmm_decoder_un18_bar0_32_hit_nc_4_and; + wire com_cmm_u_cmm_decoder_un18_bar0_32_hit_nc_3_and; + wire com_cmm_u_cmm_decoder_un18_bar0_32_hit_nc_2_and; + wire com_cmm_u_cmm_decoder_un18_bar0_32_hit_nc_1_and; + wire com_cmm_u_cmm_decoder_un18_bar0_32_hit_nc_0_and; + wire com_cmm_u_cmm_decoder_un18_bar0_32_hit_nc_0_and_1; + wire com_cmm_u_cmm_decoder_un18_bar1_32_hit_nc_7_and; + wire com_cmm_u_cmm_decoder_un18_bar1_32_hit_nc_6_and; + wire com_cmm_u_cmm_decoder_un18_bar1_32_hit_nc_5_and; + wire com_cmm_u_cmm_decoder_un18_bar1_32_hit_nc_4_and; + wire com_cmm_u_cmm_decoder_un18_bar1_32_hit_nc_3_and; + wire com_cmm_u_cmm_decoder_un18_bar1_32_hit_nc_2_and; + wire com_cmm_u_cmm_decoder_un18_bar1_32_hit_nc_1_and; + wire com_cmm_u_cmm_decoder_un18_bar1_32_hit_nc_0_and; + wire com_cmm_u_cmm_decoder_bar23_64_hit_high_3_1; + wire com_cmm_u_cmm_decoder_un18_bar2_32_hit_nc_7_and; + wire com_cmm_u_cmm_decoder_un18_bar2_32_hit_nc_6_and; + wire com_cmm_u_cmm_decoder_un18_bar2_32_hit_nc_5_and; + wire com_cmm_u_cmm_decoder_un18_bar2_32_hit_nc_4_and; + wire com_cmm_u_cmm_decoder_un18_bar2_32_hit_nc_3_and; + wire com_cmm_u_cmm_decoder_un18_bar2_32_hit_nc_2_and; + wire com_cmm_u_cmm_decoder_un18_bar2_32_hit_nc_1_and; + wire com_cmm_u_cmm_decoder_un18_bar2_32_hit_nc_0_and; + wire com_cmm_u_cmm_decoder_un18_bar2_32_hit_nc_0_and_1; + wire com_cmm_u_cmm_decoder_un18_bar3_32_hit_nc_7_and; + wire com_cmm_u_cmm_decoder_un18_bar3_32_hit_nc_6_and; + wire com_cmm_u_cmm_decoder_un18_bar3_32_hit_nc_5_and; + wire com_cmm_u_cmm_decoder_un18_bar3_32_hit_nc_4_and; + wire com_cmm_u_cmm_decoder_un18_bar3_32_hit_nc_3_and; + wire com_cmm_u_cmm_decoder_un18_bar3_32_hit_nc_2_and; + wire com_cmm_u_cmm_decoder_un18_bar3_32_hit_nc_1_and; + wire com_cmm_u_cmm_decoder_un18_bar3_32_hit_nc_0_and; + wire com_cmm_u_cmm_decoder_un18_bar3_32_hit_nc_0_and_1; + wire com_cmm_u_cmm_decoder_un18_bar4_32_hit_nc_7_and; + wire com_cmm_u_cmm_decoder_un18_bar4_32_hit_nc_6_and; + wire com_cmm_u_cmm_decoder_un18_bar4_32_hit_nc_5_and; + wire com_cmm_u_cmm_decoder_un18_bar4_32_hit_nc_4_and; + wire com_cmm_u_cmm_decoder_un18_bar4_32_hit_nc_3_and; + wire com_cmm_u_cmm_decoder_un18_bar4_32_hit_nc_2_and; + wire com_cmm_u_cmm_decoder_un18_bar4_32_hit_nc_1_and; + wire com_cmm_u_cmm_decoder_un18_bar4_32_hit_nc_0_and; + wire com_cmm_u_cmm_decoder_un11_bar1_32_hit_nc_7_and; + wire com_cmm_u_cmm_decoder_un11_bar1_32_hit_nc_6_and; + wire com_cmm_u_cmm_decoder_un11_bar1_32_hit_nc_5_and; + wire com_cmm_u_cmm_decoder_un11_bar1_32_hit_nc_4_and; + wire com_cmm_u_cmm_decoder_un11_bar1_32_hit_nc_3_and; + wire com_cmm_u_cmm_decoder_un11_bar1_32_hit_nc_2_and; + wire com_cmm_u_cmm_decoder_un11_bar1_32_hit_nc_1_and; + wire com_cmm_u_cmm_decoder_un11_bar1_32_hit_nc_0_and; + wire com_cmm_u_cmm_decoder_un11_bar2_32_hit_nc_7_and; + wire com_cmm_u_cmm_decoder_un11_bar2_32_hit_nc_6_and; + wire com_cmm_u_cmm_decoder_un11_bar2_32_hit_nc_5_and; + wire com_cmm_u_cmm_decoder_un11_bar2_32_hit_nc_4_and; + wire com_cmm_u_cmm_decoder_un11_bar2_32_hit_nc_3_and; + wire com_cmm_u_cmm_decoder_un11_bar2_32_hit_nc_2_and; + wire com_cmm_u_cmm_decoder_un11_bar2_32_hit_nc_1_and; + wire com_cmm_u_cmm_decoder_un11_bar2_32_hit_nc_0_and; + wire com_cmm_u_cmm_decoder_un11_bar3_32_hit_nc_7_and; + wire com_cmm_u_cmm_decoder_un11_bar3_32_hit_nc_6_and; + wire com_cmm_u_cmm_decoder_un11_bar3_32_hit_nc_5_and; + wire com_cmm_u_cmm_decoder_un11_bar3_32_hit_nc_4_and; + wire com_cmm_u_cmm_decoder_un11_bar3_32_hit_nc_3_and; + wire com_cmm_u_cmm_decoder_un11_bar3_32_hit_nc_2_and; + wire com_cmm_u_cmm_decoder_un11_bar3_32_hit_nc_1_and; + wire com_cmm_u_cmm_decoder_un11_bar3_32_hit_nc_0_and; + wire com_cmm_u_cmm_decoder_un11_bar4_32_hit_nc_7_sf_4511; + wire com_cmm_u_cmm_decoder_un11_bar4_32_hit_nc_7_and; + wire com_cmm_u_cmm_decoder_un11_bar4_32_hit_nc_6_sf_4512; + wire com_cmm_u_cmm_decoder_un11_bar4_32_hit_nc_6_and; + wire com_cmm_u_cmm_decoder_un11_bar4_32_hit_nc_5_sf_4513; + wire com_cmm_u_cmm_decoder_un11_bar4_32_hit_nc_5_and; + wire com_cmm_u_cmm_decoder_un11_bar4_32_hit_nc_4_sf_4514; + wire com_cmm_u_cmm_decoder_un11_bar4_32_hit_nc_4_and; + wire com_cmm_u_cmm_decoder_un11_bar4_32_hit_nc_3_sf_4515; + wire com_cmm_u_cmm_decoder_un11_bar4_32_hit_nc_3_and; + wire com_cmm_u_cmm_decoder_un11_bar4_32_hit_nc_2_sf_4516; + wire com_cmm_u_cmm_decoder_un11_bar4_32_hit_nc_2_and; + wire com_cmm_u_cmm_decoder_un11_bar4_32_hit_nc_1_sf_4517; + wire com_cmm_u_cmm_decoder_un11_bar4_32_hit_nc_1_and; + wire com_cmm_u_cmm_decoder_un11_bar5_32_hit_nc_7_and; + wire com_cmm_u_cmm_decoder_un11_bar5_32_hit_nc_6_and; + wire com_cmm_u_cmm_decoder_un11_bar5_32_hit_nc_5_and; + wire com_cmm_u_cmm_decoder_un11_bar5_32_hit_nc_4_and; + wire com_cmm_u_cmm_decoder_un11_bar5_32_hit_nc_3_and; + wire com_cmm_u_cmm_decoder_un11_bar5_32_hit_nc_2_and; + wire com_cmm_u_cmm_decoder_un11_bar5_32_hit_nc_1_and; + wire com_cmm_u_cmm_decoder_un11_bar5_32_hit_nc_0_and; + wire com_cmm_u_cmm_decoder_N_3_13; + wire com_cmm_u_cmm_decoder_N_6_8; + wire com_cmm_u_cmm_decoder_N_11_14; + wire com_cmm_u_cmm_decoder_N_14_9; + wire com_cmm_u_cmm_decoder_N_19_13; + wire com_cmm_u_cmm_decoder_N_22_8; + wire com_cmm_u_cmm_decoder_N_27_13; + wire com_cmm_u_cmm_decoder_N_30_7; + wire com_cmm_u_cmm_decoder_N_35_13; + wire com_cmm_u_cmm_decoder_N_38_8; + wire com_cmm_u_cmm_decoder_N_43_13; + wire com_cmm_u_cmm_decoder_N_46_8; + wire com_cmm_u_cmm_decoder_N_51_13; + wire com_cmm_u_cmm_decoder_N_54_8; + wire com_cmm_u_cmm_decoder_N_59_13; + wire com_cmm_u_cmm_decoder_N_62_8; + wire com_cmm_u_cmm_decoder_N_67_13; + wire com_cmm_u_cmm_decoder_N_70_8; + wire com_cmm_u_cmm_decoder_N_75_13; + wire com_cmm_u_cmm_decoder_N_78_8; + wire com_cmm_u_cmm_decoder_N_83_13; + wire com_cmm_u_cmm_decoder_N_86_8; + wire com_cmm_u_cmm_decoder_N_91_13; + wire com_cmm_u_cmm_decoder_N_94_8; + wire com_cmm_u_cmm_decoder_N_107_12; + wire com_cmm_u_cmm_decoder_N_110_5; + wire com_cmm_u_cmm_decoder_N_3_12; + wire com_cmm_u_cmm_decoder_N_6_7; + wire com_cmm_u_cmm_decoder_N_11_13; + wire com_cmm_u_cmm_decoder_N_14_8; + wire com_cmm_u_cmm_decoder_N_19_12; + wire com_cmm_u_cmm_decoder_N_22_7; + wire com_cmm_u_cmm_decoder_N_27_12; + wire com_cmm_u_cmm_decoder_N_30_6; + wire com_cmm_u_cmm_decoder_N_35_12; + wire com_cmm_u_cmm_decoder_N_38_7; + wire com_cmm_u_cmm_decoder_N_43_12; + wire com_cmm_u_cmm_decoder_N_46_7; + wire com_cmm_u_cmm_decoder_N_51_12; + wire com_cmm_u_cmm_decoder_N_54_7; + wire com_cmm_u_cmm_decoder_N_59_12; + wire com_cmm_u_cmm_decoder_N_62_7; + wire com_cmm_u_cmm_decoder_N_67_12; + wire com_cmm_u_cmm_decoder_N_70_7; + wire com_cmm_u_cmm_decoder_N_75_12; + wire com_cmm_u_cmm_decoder_N_78_7; + wire com_cmm_u_cmm_decoder_N_83_12; + wire com_cmm_u_cmm_decoder_N_86_7; + wire com_cmm_u_cmm_decoder_N_91_12; + wire com_cmm_u_cmm_decoder_N_94_7; + wire com_cmm_u_cmm_decoder_N_107_11; + wire com_cmm_u_cmm_decoder_N_110_4; + wire com_cmm_u_cmm_decoder_N_3_11; + wire com_cmm_u_cmm_decoder_N_6_6; + wire com_cmm_u_cmm_decoder_N_11_12; + wire com_cmm_u_cmm_decoder_N_14_7; + wire com_cmm_u_cmm_decoder_N_19_11; + wire com_cmm_u_cmm_decoder_N_22_6; + wire com_cmm_u_cmm_decoder_N_27_11; + wire com_cmm_u_cmm_decoder_N_30_5; + wire com_cmm_u_cmm_decoder_N_35_11; + wire com_cmm_u_cmm_decoder_N_38_6; + wire com_cmm_u_cmm_decoder_N_43_11; + wire com_cmm_u_cmm_decoder_N_46_6; + wire com_cmm_u_cmm_decoder_N_51_11; + wire com_cmm_u_cmm_decoder_N_54_6; + wire com_cmm_u_cmm_decoder_N_59_11; + wire com_cmm_u_cmm_decoder_N_62_6; + wire com_cmm_u_cmm_decoder_N_67_11; + wire com_cmm_u_cmm_decoder_N_70_6; + wire com_cmm_u_cmm_decoder_N_75_11; + wire com_cmm_u_cmm_decoder_N_78_6; + wire com_cmm_u_cmm_decoder_N_83_11; + wire com_cmm_u_cmm_decoder_N_86_6; + wire com_cmm_u_cmm_decoder_N_91_11; + wire com_cmm_u_cmm_decoder_N_94_6; + wire com_cmm_u_cmm_decoder_N_107_10; + wire com_cmm_u_cmm_decoder_N_110_3; + wire com_cmm_u_cmm_decoder_N_3_10; + wire com_cmm_u_cmm_decoder_N_6_5; + wire com_cmm_u_cmm_decoder_N_11_11; + wire com_cmm_u_cmm_decoder_N_14_6; + wire com_cmm_u_cmm_decoder_N_19_10; + wire com_cmm_u_cmm_decoder_N_22_5; + wire com_cmm_u_cmm_decoder_N_27_10; + wire com_cmm_u_cmm_decoder_N_30_4; + wire com_cmm_u_cmm_decoder_N_35_10; + wire com_cmm_u_cmm_decoder_N_38_5; + wire com_cmm_u_cmm_decoder_N_43_10; + wire com_cmm_u_cmm_decoder_N_46_5; + wire com_cmm_u_cmm_decoder_N_51_10; + wire com_cmm_u_cmm_decoder_N_54_5; + wire com_cmm_u_cmm_decoder_N_59_10; + wire com_cmm_u_cmm_decoder_N_62_5; + wire com_cmm_u_cmm_decoder_N_67_10; + wire com_cmm_u_cmm_decoder_N_70_5; + wire com_cmm_u_cmm_decoder_N_75_10; + wire com_cmm_u_cmm_decoder_N_78_5; + wire com_cmm_u_cmm_decoder_N_83_10; + wire com_cmm_u_cmm_decoder_N_86_5; + wire com_cmm_u_cmm_decoder_N_91_10; + wire com_cmm_u_cmm_decoder_N_94_5; + wire com_cmm_u_cmm_decoder_N_107_9; + wire com_cmm_u_cmm_decoder_N_110_2; + wire com_cmm_u_cmm_decoder_N_9; + wire com_cmm_u_cmm_decoder_N_12; + wire com_cmm_u_cmm_decoder_N_17; + wire com_cmm_u_cmm_decoder_N_20; + wire com_cmm_u_cmm_decoder_N_25; + wire com_cmm_u_cmm_decoder_N_28; + wire com_cmm_u_cmm_decoder_N_33; + wire com_cmm_u_cmm_decoder_N_36; + wire com_cmm_u_cmm_decoder_N_41; + wire com_cmm_u_cmm_decoder_N_44; + wire com_cmm_u_cmm_decoder_N_49; + wire com_cmm_u_cmm_decoder_N_52; + wire com_cmm_u_cmm_decoder_N_57; + wire com_cmm_u_cmm_decoder_N_60; + wire com_cmm_u_cmm_decoder_N_65; + wire com_cmm_u_cmm_decoder_N_68; + wire com_cmm_u_cmm_decoder_N_73; + wire com_cmm_u_cmm_decoder_N_76; + wire com_cmm_u_cmm_decoder_N_81; + wire com_cmm_u_cmm_decoder_N_84; + wire com_cmm_u_cmm_decoder_I_118_sf; + wire com_cmm_u_cmm_decoder_N_3_9; + wire com_cmm_u_cmm_decoder_I_109_sf; + wire com_cmm_u_cmm_decoder_N_11_10; + wire com_cmm_u_cmm_decoder_I_100_sf; + wire com_cmm_u_cmm_decoder_N_19_9; + wire com_cmm_u_cmm_decoder_I_91_sf; + wire com_cmm_u_cmm_decoder_N_27_9; + wire com_cmm_u_cmm_decoder_I_82_sf; + wire com_cmm_u_cmm_decoder_N_35_9; + wire com_cmm_u_cmm_decoder_I_73_sf; + wire com_cmm_u_cmm_decoder_N_43_9; + wire com_cmm_u_cmm_decoder_I_64_sf; + wire com_cmm_u_cmm_decoder_N_51_9; + wire com_cmm_u_cmm_decoder_I_55_sf; + wire com_cmm_u_cmm_decoder_N_59_9; + wire com_cmm_u_cmm_decoder_I_46_sf; + wire com_cmm_u_cmm_decoder_N_67_9; + wire com_cmm_u_cmm_decoder_I_37_sf; + wire com_cmm_u_cmm_decoder_N_75_9; + wire com_cmm_u_cmm_decoder_I_28_sf; + wire com_cmm_u_cmm_decoder_N_83_9; + wire com_cmm_u_cmm_decoder_I_19_sf; + wire com_cmm_u_cmm_decoder_N_91_9; + wire com_cmm_u_cmm_decoder_N_3_8; + wire com_cmm_u_cmm_decoder_N_11_9; + wire com_cmm_u_cmm_decoder_N_19_8; + wire com_cmm_u_cmm_decoder_N_27_8; + wire com_cmm_u_cmm_decoder_N_35_8; + wire com_cmm_u_cmm_decoder_N_43_8; + wire com_cmm_u_cmm_decoder_N_51_8; + wire com_cmm_u_cmm_decoder_N_59_8; + wire com_cmm_u_cmm_decoder_N_67_8; + wire com_cmm_u_cmm_decoder_N_75_8; + wire com_cmm_u_cmm_decoder_N_83_8; + wire com_cmm_u_cmm_decoder_N_91_8; + wire com_cmm_u_cmm_decoder_N_107_8; + wire com_cmm_u_cmm_decoder_N_3_7; + wire com_cmm_u_cmm_decoder_N_11_8; + wire com_cmm_u_cmm_decoder_N_19_7; + wire com_cmm_u_cmm_decoder_N_27_7; + wire com_cmm_u_cmm_decoder_N_35_7; + wire com_cmm_u_cmm_decoder_N_43_7; + wire com_cmm_u_cmm_decoder_N_51_7; + wire com_cmm_u_cmm_decoder_N_59_7; + wire com_cmm_u_cmm_decoder_N_67_7; + wire com_cmm_u_cmm_decoder_N_75_7; + wire com_cmm_u_cmm_decoder_N_83_7; + wire com_cmm_u_cmm_decoder_N_91_7; + wire com_cmm_u_cmm_decoder_N_107_7; + wire com_cmm_u_cmm_decoder_N_3_6; + wire com_cmm_u_cmm_decoder_N_11_7; + wire com_cmm_u_cmm_decoder_N_19_6; + wire com_cmm_u_cmm_decoder_N_27_6; + wire com_cmm_u_cmm_decoder_N_35_6; + wire com_cmm_u_cmm_decoder_N_43_6; + wire com_cmm_u_cmm_decoder_N_51_6; + wire com_cmm_u_cmm_decoder_N_59_6; + wire com_cmm_u_cmm_decoder_N_67_6; + wire com_cmm_u_cmm_decoder_N_75_6; + wire com_cmm_u_cmm_decoder_N_83_6; + wire com_cmm_u_cmm_decoder_N_91_6; + wire com_cmm_u_cmm_decoder_N_107_6; + wire com_cmm_u_cmm_decoder_N_3_5; + wire com_cmm_u_cmm_decoder_N_11_6; + wire com_cmm_u_cmm_decoder_N_19_5; + wire com_cmm_u_cmm_decoder_N_27_5; + wire com_cmm_u_cmm_decoder_N_35_5; + wire com_cmm_u_cmm_decoder_N_43_5; + wire com_cmm_u_cmm_decoder_N_51_5; + wire com_cmm_u_cmm_decoder_N_59_5; + wire com_cmm_u_cmm_decoder_N_67_5; + wire com_cmm_u_cmm_decoder_N_75_5; + wire com_cmm_u_cmm_decoder_N_83_5; + wire com_cmm_u_cmm_decoder_N_91_5; + wire com_cmm_u_cmm_decoder_N_107_5; + wire com_cmm_u_cmm_decoder_N_3_4; + wire com_cmm_u_cmm_decoder_N_6_4; + wire com_cmm_u_cmm_decoder_N_11_5; + wire com_cmm_u_cmm_decoder_N_14_5; + wire com_cmm_u_cmm_decoder_N_19_4; + wire com_cmm_u_cmm_decoder_N_22_4; + wire com_cmm_u_cmm_decoder_N_27_4; + wire com_cmm_u_cmm_decoder_N_30_3; + wire com_cmm_u_cmm_decoder_N_35_4; + wire com_cmm_u_cmm_decoder_N_38_4; + wire com_cmm_u_cmm_decoder_N_43_4; + wire com_cmm_u_cmm_decoder_N_46_4; + wire com_cmm_u_cmm_decoder_N_51_4; + wire com_cmm_u_cmm_decoder_N_54_4; + wire com_cmm_u_cmm_decoder_N_59_4; + wire com_cmm_u_cmm_decoder_N_62_4; + wire com_cmm_u_cmm_decoder_N_67_4; + wire com_cmm_u_cmm_decoder_N_70_4; + wire com_cmm_u_cmm_decoder_N_75_4; + wire com_cmm_u_cmm_decoder_N_78_4; + wire com_cmm_u_cmm_decoder_N_83_4; + wire com_cmm_u_cmm_decoder_N_86_4; + wire com_cmm_u_cmm_decoder_N_91_4; + wire com_cmm_u_cmm_decoder_N_94_4; + wire com_cmm_u_cmm_decoder_N_107_4; + wire com_cmm_u_cmm_decoder_N_110_1; + wire com_cmm_u_cmm_decoder_N_3_3; + wire com_cmm_u_cmm_decoder_N_6_3; + wire com_cmm_u_cmm_decoder_N_11_4; + wire com_cmm_u_cmm_decoder_N_14_4; + wire com_cmm_u_cmm_decoder_N_19_3; + wire com_cmm_u_cmm_decoder_N_22_3; + wire com_cmm_u_cmm_decoder_N_27_3; + wire com_cmm_u_cmm_decoder_N_30_2; + wire com_cmm_u_cmm_decoder_N_35_3; + wire com_cmm_u_cmm_decoder_N_38_3; + wire com_cmm_u_cmm_decoder_N_43_3; + wire com_cmm_u_cmm_decoder_N_46_3; + wire com_cmm_u_cmm_decoder_N_51_3; + wire com_cmm_u_cmm_decoder_N_54_3; + wire com_cmm_u_cmm_decoder_N_59_3; + wire com_cmm_u_cmm_decoder_N_62_3; + wire com_cmm_u_cmm_decoder_N_67_3; + wire com_cmm_u_cmm_decoder_N_70_3; + wire com_cmm_u_cmm_decoder_N_75_3; + wire com_cmm_u_cmm_decoder_N_78_3; + wire com_cmm_u_cmm_decoder_N_83_3; + wire com_cmm_u_cmm_decoder_N_86_3; + wire com_cmm_u_cmm_decoder_N_91_3; + wire com_cmm_u_cmm_decoder_N_94_3; + wire com_cmm_u_cmm_decoder_N_107_3; + wire com_cmm_u_cmm_decoder_N_110_0; + wire com_cmm_u_cmm_decoder_N_3_2; + wire com_cmm_u_cmm_decoder_N_86_2; + wire com_cmm_u_cmm_decoder_N_11_3; + wire com_cmm_u_cmm_decoder_N_102_2; + wire com_cmm_u_cmm_decoder_N_19_2; + wire com_cmm_u_cmm_decoder_N_14_3; + wire com_cmm_u_cmm_decoder_N_27_2; + wire com_cmm_u_cmm_decoder_N_6_2; + wire com_cmm_u_cmm_decoder_N_35_2; + wire com_cmm_u_cmm_decoder_N_54_2; + wire com_cmm_u_cmm_decoder_N_47_1; + wire com_cmm_u_cmm_decoder_N_43_2; + wire com_cmm_u_cmm_decoder_N_94_2; + wire com_cmm_u_cmm_decoder_N_51_2; + wire com_cmm_u_cmm_decoder_N_46_2; + wire com_cmm_u_cmm_decoder_N_59_2; + wire com_cmm_u_cmm_decoder_N_38_2; + wire com_cmm_u_cmm_decoder_N_67_2; + wire com_cmm_u_cmm_decoder_N_22_2; + wire com_cmm_u_cmm_decoder_N_15_2; + wire com_cmm_u_cmm_decoder_N_75_2; + wire com_cmm_u_cmm_decoder_N_62_2; + wire com_cmm_u_cmm_decoder_N_39_1; + wire com_cmm_u_cmm_decoder_N_83_2; + wire com_cmm_u_cmm_decoder_N_78_2; + wire com_cmm_u_cmm_decoder_N_63_2; + wire com_cmm_u_cmm_decoder_N_91_2; + wire com_cmm_u_cmm_decoder_N_70_2; + wire com_cmm_u_cmm_decoder_N_107_2; + wire com_cmm_u_cmm_decoder_N_30_1; + wire com_cmm_u_cmm_decoder_N_115_2; + wire com_cmm_u_cmm_decoder_N_31_1; + wire com_cmm_u_cmm_decoder_N_123_2; + wire com_cmm_u_cmm_decoder_N_111_2; + wire com_cmm_u_cmm_decoder_N_3_1; + wire com_cmm_u_cmm_decoder_N_86_1; + wire com_cmm_u_cmm_decoder_N_79_0; + wire com_cmm_u_cmm_decoder_N_11_2; + wire com_cmm_u_cmm_decoder_N_102_1; + wire com_cmm_u_cmm_decoder_N_19_1; + wire com_cmm_u_cmm_decoder_N_14_2; + wire com_cmm_u_cmm_decoder_N_27_1; + wire com_cmm_u_cmm_decoder_N_6_1; + wire com_cmm_u_cmm_decoder_N_35_1; + wire com_cmm_u_cmm_decoder_N_54_1; + wire com_cmm_u_cmm_decoder_N_43_1; + wire com_cmm_u_cmm_decoder_N_94_1; + wire com_cmm_u_cmm_decoder_N_51_1; + wire com_cmm_u_cmm_decoder_N_46_1; + wire com_cmm_u_cmm_decoder_N_59_1; + wire com_cmm_u_cmm_decoder_N_38_1; + wire com_cmm_u_cmm_decoder_N_67_1; + wire com_cmm_u_cmm_decoder_N_22_1; + wire com_cmm_u_cmm_decoder_N_15_1; + wire com_cmm_u_cmm_decoder_N_75_1; + wire com_cmm_u_cmm_decoder_N_62_1; + wire com_cmm_u_cmm_decoder_N_39_0; + wire com_cmm_u_cmm_decoder_N_83_1; + wire com_cmm_u_cmm_decoder_N_78_1; + wire com_cmm_u_cmm_decoder_N_63_1; + wire com_cmm_u_cmm_decoder_N_91_1; + wire com_cmm_u_cmm_decoder_N_70_1; + wire com_cmm_u_cmm_decoder_N_107_1; + wire com_cmm_u_cmm_decoder_N_7_0; + wire com_cmm_u_cmm_decoder_N_115_1; + wire com_cmm_u_cmm_decoder_N_31_0; + wire com_cmm_u_cmm_decoder_N_123_1; + wire com_cmm_u_cmm_decoder_N_111_1; + wire com_cmm_u_cmm_decoder_N_3_0; + wire com_cmm_u_cmm_decoder_N_86_0; + wire com_cmm_u_cmm_decoder_N_79; + wire com_cmm_u_cmm_decoder_N_11_1; + wire com_cmm_u_cmm_decoder_N_102_0; + wire com_cmm_u_cmm_decoder_N_19_0; + wire com_cmm_u_cmm_decoder_N_14_1; + wire com_cmm_u_cmm_decoder_N_27_0; + wire com_cmm_u_cmm_decoder_N_6_0; + wire com_cmm_u_cmm_decoder_N_35_0; + wire com_cmm_u_cmm_decoder_N_54_0; + wire com_cmm_u_cmm_decoder_N_47_0; + wire com_cmm_u_cmm_decoder_N_43_0; + wire com_cmm_u_cmm_decoder_N_94_0; + wire com_cmm_u_cmm_decoder_N_51_0; + wire com_cmm_u_cmm_decoder_N_46_0; + wire com_cmm_u_cmm_decoder_N_59_0; + wire com_cmm_u_cmm_decoder_N_38_0; + wire com_cmm_u_cmm_decoder_N_67_0; + wire com_cmm_u_cmm_decoder_N_22_0; + wire com_cmm_u_cmm_decoder_N_15_0; + wire com_cmm_u_cmm_decoder_N_75_0; + wire com_cmm_u_cmm_decoder_N_62_0; + wire com_cmm_u_cmm_decoder_N_39; + wire com_cmm_u_cmm_decoder_N_83_0; + wire com_cmm_u_cmm_decoder_N_78_0; + wire com_cmm_u_cmm_decoder_N_63_0; + wire com_cmm_u_cmm_decoder_N_91_0; + wire com_cmm_u_cmm_decoder_N_70_0; + wire com_cmm_u_cmm_decoder_N_107_0; + wire com_cmm_u_cmm_decoder_N_30_0; + wire com_cmm_u_cmm_decoder_N_115_0; + wire com_cmm_u_cmm_decoder_N_110; + wire com_cmm_u_cmm_decoder_N_123_0; + wire com_cmm_u_cmm_decoder_N_111_0; + wire com_cmm_u_cmm_decoder_N_3; + wire com_cmm_u_cmm_decoder_N_86; + wire com_cmm_u_cmm_decoder_N_11_0; + wire com_cmm_u_cmm_decoder_N_102; + wire com_cmm_u_cmm_decoder_N_19; + wire com_cmm_u_cmm_decoder_N_14_0; + wire com_cmm_u_cmm_decoder_N_27; + wire com_cmm_u_cmm_decoder_N_6; + wire com_cmm_u_cmm_decoder_N_35; + wire com_cmm_u_cmm_decoder_N_54; + wire com_cmm_u_cmm_decoder_N_47; + wire com_cmm_u_cmm_decoder_N_43; + wire com_cmm_u_cmm_decoder_N_94; + wire com_cmm_u_cmm_decoder_N_71; + wire com_cmm_u_cmm_decoder_N_51; + wire com_cmm_u_cmm_decoder_N_46; + wire com_cmm_u_cmm_decoder_N_59; + wire com_cmm_u_cmm_decoder_N_38; + wire com_cmm_u_cmm_decoder_N_67; + wire com_cmm_u_cmm_decoder_N_22; + wire com_cmm_u_cmm_decoder_N_15; + wire com_cmm_u_cmm_decoder_N_75; + wire com_cmm_u_cmm_decoder_N_62; + wire com_cmm_u_cmm_decoder_N_83; + wire com_cmm_u_cmm_decoder_N_78; + wire com_cmm_u_cmm_decoder_N_63; + wire com_cmm_u_cmm_decoder_N_91; + wire com_cmm_u_cmm_decoder_N_70; + wire com_cmm_u_cmm_decoder_N_23; + wire com_cmm_u_cmm_decoder_N_107; + wire com_cmm_u_cmm_decoder_N_30; + wire com_cmm_u_cmm_decoder_N_7; + wire com_cmm_u_cmm_decoder_N_115; + wire com_cmm_u_cmm_decoder_N_31; + wire com_cmm_u_cmm_decoder_N_123; + wire com_cmm_u_cmm_decoder_N_111; + wire com_cmm_u_cmm_decoder_N_11; + wire com_cmm_u_cmm_decoder_N_14; + wire com_cmm_u_cmm_cfgspace_N_9426_i_4518; + wire com_cmm_u_cmm_cfgspace_sel_encodex_en_4519; + wire com_cmm_u_cmm_cfgspace_N_28511_i; + wire com_cmm_u_cmm_cfgspace_low_addr_01_3_0_bm_0__4520; + wire com_cmm_u_cmm_cfgspace_low_addr_01_3_0_am_0__4521; + wire com_cmm_u_cmm_cfgspace_low_addr_01_3_0_bm_10__4522; + wire com_cmm_u_cmm_cfgspace_low_addr_01_3_0_am_10__4523; + wire com_cmm_u_cmm_cfgspace_N_4062; + wire com_cmm_u_cmm_cfgspace_N_4072; + wire com_cmm_u_cmm_cfgspace_low_addr_02_3_0_bm_16__4524; + wire com_cmm_u_cmm_cfgspace_low_addr_02_3_0_am_16__4525; + wire com_cmm_u_cmm_cfgspace_N_4348; + wire com_cmm_u_cmm_cfgspace_N_4350; + wire com_cmm_u_cmm_cfgspace_sel_encodex_en_3_i_0_a2_2_1_0_4526; + wire com_cmm_u_cmm_cfgspace_N_42543; + wire com_cmm_u_cmm_cfgspace_N_50135; + wire com_cmm_u_cmm_cfgspace_N_50137_1; + wire com_cmm_u_cmm_cfgspace_N_50187_1; + wire com_cmm_u_cmm_cfgspace_low_addr_02_3_0_bm_11__4527; + wire com_cmm_u_cmm_cfgspace_low_addr_02_3_0_am_11__4528; + wire com_cmm_u_cmm_cfgspace_low_addr_02_3_0_bm_12__4529; + wire com_cmm_u_cmm_cfgspace_low_addr_02_3_0_am_12__4530; + wire com_cmm_u_cmm_cfgspace_low_addr_02_3_0_bm_14__4531; + wire com_cmm_u_cmm_cfgspace_low_addr_02_3_0_am_14__4532; + wire com_cmm_u_cmm_cfgspace_N_48874_i; + wire com_cmm_u_cmm_cfgspace_N_44842_i; + wire com_cmm_u_cmm_cfgspace_low_addr_01_7_0_bm_16__4533; + wire com_cmm_u_cmm_cfgspace_low_addr_01_7_0_am_16__4534; + wire com_cmm_u_cmm_cfgspace_low_addr_01_7_0_bm_17__4535; + wire com_cmm_u_cmm_cfgspace_low_addr_01_7_0_am_17__4536; + wire com_cmm_u_cmm_cfgspace_low_addr_01_7_0_bm_18__4537; + wire com_cmm_u_cmm_cfgspace_low_addr_01_7_0_am_18__4538; + wire com_cmm_u_cmm_cfgspace_low_addr_01_7_0_bm_20__4539; + wire com_cmm_u_cmm_cfgspace_low_addr_01_7_0_am_20__4540; + wire com_cmm_u_cmm_cfgspace_low_addr_01_7_0_bm_21__4541; + wire com_cmm_u_cmm_cfgspace_low_addr_01_7_0_am_21__4542; + wire com_cmm_u_cmm_cfgspace_low_addr_01_7_0_bm_22__4543; + wire com_cmm_u_cmm_cfgspace_low_addr_01_7_0_am_22__4544; + wire com_cmm_u_cmm_cfgspace_low_addr_01_7_0_bm_23__4545; + wire com_cmm_u_cmm_cfgspace_low_addr_01_7_0_am_23__4546; + wire com_cmm_u_cmm_cfgspace_N_50453; + wire com_cmm_u_cmm_cfgspace_N_50489; + wire com_cmm_u_cmm_cfgspace_N_48992; + wire com_cmm_u_cmm_cfgspace_N_48993; + wire com_cmm_u_cmm_cfgspace_N_50458; + wire com_cmm_u_cmm_cfgspace_N_50455; + wire com_cmm_u_cmm_cfgspace_N_50456; + wire com_cmm_u_cmm_cfgspace_N_50484; + wire com_cmm_u_cmm_cfgspace_N_3935; + wire com_cmm_u_cmm_cfgspace_N_4063; + wire com_cmm_u_cmm_cfgspace_low_addr_01_7_0_bm_1__4547; + wire com_cmm_u_cmm_cfgspace_low_addr_01_7_0_am_1__4548; + wire com_cmm_u_cmm_cfgspace_N_4064; + wire com_cmm_u_cmm_cfgspace_low_addr_01_7_0_bm_2__4549; + wire com_cmm_u_cmm_cfgspace_low_addr_01_7_0_am_2__4550; + wire com_cmm_u_cmm_cfgspace_N_4065; + wire com_cmm_u_cmm_cfgspace_low_addr_01_7_0_bm_3__4551; + wire com_cmm_u_cmm_cfgspace_N_4066; + wire com_cmm_u_cmm_cfgspace_low_addr_01_7_0_bm_4__4552; + wire com_cmm_u_cmm_cfgspace_low_addr_01_7_0_am_4__4553; + wire com_cmm_u_cmm_cfgspace_N_4067; + wire com_cmm_u_cmm_cfgspace_low_addr_01_7_0_bm_5__4554; + wire com_cmm_u_cmm_cfgspace_low_addr_01_7_0_am_5__4555; + wire com_cmm_u_cmm_cfgspace_N_4068; + wire com_cmm_u_cmm_cfgspace_low_addr_01_7_0_bm_6__4556; + wire com_cmm_u_cmm_cfgspace_low_addr_01_7_0_am_6__4557; + wire com_cmm_u_cmm_cfgspace_N_4069; + wire com_cmm_u_cmm_cfgspace_low_addr_01_7_0_bm_7__4558; + wire com_cmm_u_cmm_cfgspace_low_addr_01_7_0_am_7__4559; + wire com_cmm_u_cmm_cfgspace_N_3942; + wire com_cmm_u_cmm_cfgspace_N_4070; + wire com_cmm_u_cmm_cfgspace_low_addr_01_7_0_bm_8__4560; + wire com_cmm_u_cmm_cfgspace_low_addr_01_7_0_am_8__4561; + wire com_cmm_u_cmm_cfgspace_N_4071; + wire com_cmm_u_cmm_cfgspace_low_addr_01_7_0_bm_9__4562; + wire com_cmm_u_cmm_cfgspace_low_addr_01_7_0_am_9__4563; + wire com_cmm_u_cmm_cfgspace_N_3977; + wire com_cmm_u_cmm_cfgspace_N_4073; + wire com_cmm_u_cmm_cfgspace_low_addr_01_7_0_bm_11__4564; + wire com_cmm_u_cmm_cfgspace_low_addr_01_7_0_am_11__4565; + wire com_cmm_u_cmm_cfgspace_N_3978; + wire com_cmm_u_cmm_cfgspace_N_4074; + wire com_cmm_u_cmm_cfgspace_low_addr_01_7_0_bm_12__4566; + wire com_cmm_u_cmm_cfgspace_low_addr_01_7_0_am_12__4567; + wire com_cmm_u_cmm_cfgspace_N_3979; + wire com_cmm_u_cmm_cfgspace_N_4075; + wire com_cmm_u_cmm_cfgspace_low_addr_01_7_0_bm_13__4568; + wire com_cmm_u_cmm_cfgspace_low_addr_01_7_0_am_13__4569; + wire com_cmm_u_cmm_cfgspace_N_3980; + wire com_cmm_u_cmm_cfgspace_N_4076; + wire com_cmm_u_cmm_cfgspace_low_addr_01_7_0_bm_14__4570; + wire com_cmm_u_cmm_cfgspace_low_addr_01_7_0_am_14__4571; + wire com_cmm_u_cmm_cfgspace_N_3981; + wire com_cmm_u_cmm_cfgspace_N_4077; + wire com_cmm_u_cmm_cfgspace_low_addr_01_7_0_bm_15__4572; + wire com_cmm_u_cmm_cfgspace_low_addr_01_7_0_am_15__4573; + wire com_cmm_u_cmm_cfgspace_N_3953; + wire com_cmm_u_cmm_cfgspace_low_addr_01_7_0_bm_19__4574; + wire com_cmm_u_cmm_cfgspace_low_addr_01_7_0_am_19__4575; + wire com_cmm_u_cmm_cfgspace_N_4206; + wire com_cmm_u_cmm_cfgspace_N_4334; + wire com_cmm_u_cmm_cfgspace_low_addr_02_7_0_bm_0__4576; + wire com_cmm_u_cmm_cfgspace_low_addr_02_7_0_am_0__4577; + wire com_cmm_u_cmm_cfgspace_N_4207; + wire com_cmm_u_cmm_cfgspace_N_4335; + wire com_cmm_u_cmm_cfgspace_low_addr_02_7_0_bm_1__4578; + wire com_cmm_u_cmm_cfgspace_low_addr_02_7_0_am_1__4579; + wire com_cmm_u_cmm_cfgspace_N_4336; + wire com_cmm_u_cmm_cfgspace_low_addr_02_7_0_bm_2__4580; + wire com_cmm_u_cmm_cfgspace_low_addr_02_7_0_am_2__4581; + wire com_cmm_u_cmm_cfgspace_N_4209; + wire com_cmm_u_cmm_cfgspace_N_4337; + wire com_cmm_u_cmm_cfgspace_low_addr_02_7_0_bm_3__4582; + wire com_cmm_u_cmm_cfgspace_low_addr_02_7_0_am_3__4583; + wire com_cmm_u_cmm_cfgspace_N_4338; + wire com_cmm_u_cmm_cfgspace_low_addr_02_7_0_bm_4__4584; + wire com_cmm_u_cmm_cfgspace_low_addr_02_7_0_am_4__4585; + wire com_cmm_u_cmm_cfgspace_N_4339; + wire com_cmm_u_cmm_cfgspace_low_addr_02_7_0_bm_5__4586; + wire com_cmm_u_cmm_cfgspace_low_addr_02_7_0_am_5__4587; + wire com_cmm_u_cmm_cfgspace_N_4212; + wire com_cmm_u_cmm_cfgspace_N_4340; + wire com_cmm_u_cmm_cfgspace_low_addr_02_7_0_bm_6__4588; + wire com_cmm_u_cmm_cfgspace_low_addr_02_7_0_am_6__4589; + wire com_cmm_u_cmm_cfgspace_N_4351; + wire com_cmm_u_cmm_cfgspace_low_addr_02_7_0_bm_17__4590; + wire com_cmm_u_cmm_cfgspace_low_addr_02_7_0_am_17__4591; + wire com_cmm_u_cmm_cfgspace_N_4352; + wire com_cmm_u_cmm_cfgspace_low_addr_02_7_0_bm_18__4592; + wire com_cmm_u_cmm_cfgspace_low_addr_02_7_0_am_18__4593; + wire com_cmm_u_cmm_cfgspace_N_4353; + wire com_cmm_u_cmm_cfgspace_low_addr_02_7_0_bm_19__4594; + wire com_cmm_u_cmm_cfgspace_low_addr_02_7_0_am_19__4595; + wire com_cmm_u_cmm_cfgspace_N_4226; + wire com_cmm_u_cmm_cfgspace_N_4354; + wire com_cmm_u_cmm_cfgspace_low_addr_02_7_0_bm_20__4596; + wire com_cmm_u_cmm_cfgspace_low_addr_02_7_0_am_20__4597; + wire com_cmm_u_cmm_cfgspace_N_4355; + wire com_cmm_u_cmm_cfgspace_low_addr_02_7_0_bm_21__4598; + wire com_cmm_u_cmm_cfgspace_low_addr_02_7_0_am_21__4599; + wire com_cmm_u_cmm_cfgspace_N_4356; + wire com_cmm_u_cmm_cfgspace_low_addr_02_7_0_bm_22__4600; + wire com_cmm_u_cmm_cfgspace_low_addr_02_7_0_am_22__4601; + wire com_cmm_u_cmm_cfgspace_N_4357; + wire com_cmm_u_cmm_cfgspace_low_addr_02_7_0_bm_23__4602; + wire com_cmm_u_cmm_cfgspace_low_addr_02_7_0_am_23__4603; + wire com_cmm_u_cmm_cfgspace_N_4358; + wire com_cmm_u_cmm_cfgspace_low_addr_02_7_0_bm_24__4604; + wire com_cmm_u_cmm_cfgspace_low_addr_02_7_0_am_24__4605; + wire com_cmm_u_cmm_cfgspace_N_4359; + wire com_cmm_u_cmm_cfgspace_low_addr_02_7_0_bm_25__4606; + wire com_cmm_u_cmm_cfgspace_low_addr_02_7_0_am_25__4607; + wire com_cmm_u_cmm_cfgspace_N_4360; + wire com_cmm_u_cmm_cfgspace_low_addr_02_7_0_bm_26__4608; + wire com_cmm_u_cmm_cfgspace_low_addr_02_7_0_am_26__4609; + wire com_cmm_u_cmm_cfgspace_N_4361; + wire com_cmm_u_cmm_cfgspace_low_addr_02_7_0_bm_27__4610; + wire com_cmm_u_cmm_cfgspace_low_addr_02_7_0_am_27__4611; + wire com_cmm_u_cmm_cfgspace_N_4234; + wire com_cmm_u_cmm_cfgspace_N_4362; + wire com_cmm_u_cmm_cfgspace_low_addr_02_7_0_bm_28__4612; + wire com_cmm_u_cmm_cfgspace_low_addr_02_7_0_am_28__4613; + wire com_cmm_u_cmm_cfgspace_N_4363; + wire com_cmm_u_cmm_cfgspace_low_addr_02_7_0_bm_29__4614; + wire com_cmm_u_cmm_cfgspace_low_addr_02_7_0_am_29__4615; + wire com_cmm_u_cmm_cfgspace_N_4364; + wire com_cmm_u_cmm_cfgspace_low_addr_02_7_0_bm_30__4616; + wire com_cmm_u_cmm_cfgspace_low_addr_02_7_0_am_30__4617; + wire com_cmm_u_cmm_cfgspace_N_4365; + wire com_cmm_u_cmm_cfgspace_low_addr_02_7_0_bm_31__4618; + wire com_cmm_u_cmm_cfgspace_low_addr_02_7_0_am_31__4619; + wire com_cmm_u_cmm_cfgspace_N_4526; + wire com_cmm_u_cmm_cfgspace_N_4527; + wire com_cmm_u_cmm_cfgspace_N_4432; + wire com_cmm_u_cmm_cfgspace_N_4528; + wire com_cmm_u_cmm_cfgspace_N_4433; + wire com_cmm_u_cmm_cfgspace_N_4529; + wire com_cmm_u_cmm_cfgspace_N_4434; + wire com_cmm_u_cmm_cfgspace_N_4530; + wire com_cmm_u_cmm_cfgspace_N_4435; + wire com_cmm_u_cmm_cfgspace_N_4531; + wire com_cmm_u_cmm_cfgspace_N_4436; + wire com_cmm_u_cmm_cfgspace_N_4532; + wire com_cmm_u_cmm_cfgspace_N_4437; + wire com_cmm_u_cmm_cfgspace_N_4533; + wire com_cmm_u_cmm_cfgspace_N_51549; + wire com_cmm_u_cmm_cfgspace_N_51579; + wire com_cmm_u_cmm_cfgspace_N_51552; + wire com_cmm_u_cmm_cfgspace_N_51582; + wire com_cmm_u_cmm_cfgspace_N_51553; + wire com_cmm_u_cmm_cfgspace_N_51583; + wire com_cmm_u_cmm_cfgspace_N_51554; + wire com_cmm_u_cmm_cfgspace_N_51584; + wire com_cmm_u_cmm_cfgspace_N_51555; + wire com_cmm_u_cmm_cfgspace_N_51585; + wire com_cmm_u_cmm_cfgspace_N_51556; + wire com_cmm_u_cmm_cfgspace_N_51586; + wire com_cmm_u_cmm_cfgspace_N_4213; + wire com_cmm_u_cmm_cfgspace_N_4341; + wire com_cmm_u_cmm_cfgspace_low_addr_02_7_0_bm_7__4620; + wire com_cmm_u_cmm_cfgspace_low_addr_02_7_0_am_7__4621; + wire com_cmm_u_cmm_cfgspace_N_50139; + wire com_cmm_u_cmm_cfgspace_N_50138; + wire com_cmm_u_cmm_cfgspace_N_50457; + wire com_cmm_u_cmm_cfgspace_N_45970; + wire com_cmm_u_cmm_cfgspace_N_45969; + wire com_cmm_u_cmm_cfgspace_N_4214; + wire com_cmm_u_cmm_cfgspace_low_addr_02_7_0_bm_8__4622; + wire com_cmm_u_cmm_cfgspace_low_addr_02_7_0_am_8__4623; + wire com_cmm_u_cmm_cfgspace_N_4215; + wire com_cmm_u_cmm_cfgspace_low_addr_02_7_0_bm_9__4624; + wire com_cmm_u_cmm_cfgspace_low_addr_02_7_0_am_9__4625; + wire com_cmm_u_cmm_cfgspace_N_4216; + wire com_cmm_u_cmm_cfgspace_low_addr_02_7_0_bm_10__4626; + wire com_cmm_u_cmm_cfgspace_low_addr_02_7_0_am_10__4627; + wire com_cmm_u_cmm_cfgspace_N_4219; + wire com_cmm_u_cmm_cfgspace_low_addr_02_7_0_bm_13__4628; + wire com_cmm_u_cmm_cfgspace_low_addr_02_7_0_am_13__4629; + wire com_cmm_u_cmm_cfgspace_N_49913_1; + wire com_cmm_u_cmm_cfgspace_N_4221; + wire com_cmm_u_cmm_cfgspace_N_4349; + wire com_cmm_u_cmm_cfgspace_low_addr_02_7_0_bm_15__4630; + wire com_cmm_u_cmm_cfgspace_low_addr_02_7_0_am_15__4631; + wire com_cmm_u_cmm_cfgspace_low_addr_00_0_0_i_15_32133_4632; + wire com_cmm_u_cmm_cfgspace_sel_encodex_en_3_i_0_o4_0_4633; + wire com_cmm_u_cmm_cfgspace_N_51581; + wire com_cmm_u_cmm_cfgspace_N_51551; + wire com_cmm_u_cmm_cfgspace_N_51580; + wire com_cmm_u_cmm_cfgspace_N_51550; + wire com_cmm_u_cmm_cfgspace_N_50491; + wire com_cmm_u_cmm_cfgspace_low_addr_00_i_0_0_31_32089_4634; + wire com_cmm_u_cmm_cfgspace_low_addr_00_i_0_0_31_32088_4635; + wire com_cmm_u_cmm_cfgspace_low_addr_00_i_30_32094_4636; + wire com_cmm_u_cmm_cfgspace_low_addr_00_i_30_32093_4637; + wire com_cmm_u_cmm_cfgspace_low_addr_00_i_28_32099_4638; + wire com_cmm_u_cmm_cfgspace_low_addr_00_i_28_32098_4639; + wire com_cmm_u_cmm_cfgspace_low_addr_00_i_26_32104_4640; + wire com_cmm_u_cmm_cfgspace_low_addr_00_i_26_32103_4641; + wire com_cmm_u_cmm_cfgspace_low_addr_00_i_25_32109_4642; + wire com_cmm_u_cmm_cfgspace_low_addr_00_i_25_32108_4643; + wire com_cmm_u_cmm_cfgspace_low_addr_00_i_24_32114_4644; + wire com_cmm_u_cmm_cfgspace_low_addr_00_i_24_32113_4645; + wire com_cmm_u_cmm_cfgspace_low_addr_00_i_23_32119_4646; + wire com_cmm_u_cmm_cfgspace_low_addr_00_i_23_32118_4647; + wire com_cmm_u_cmm_cfgspace_low_addr_00_i_22_32124_4648; + wire com_cmm_u_cmm_cfgspace_low_addr_00_i_22_32123_4649; + wire com_cmm_u_cmm_cfgspace_low_addr_00_i_20_32129_4650; + wire com_cmm_u_cmm_cfgspace_low_addr_00_i_20_32128_4651; + wire com_cmm_u_cmm_cfgspace_N_48930_i; + wire com_cmm_u_cmm_cfgspace_N_42634; + wire com_cmm_u_cmm_cfgspace_sel_encodex_en_3_i_0_a2_4_2_4652; + wire com_cmm_u_cmm_cfgspace_N_50496; + wire com_cmm_u_cmm_cfgspace_N_51589; + wire com_cmm_u_cmm_cfgspace_N_3958; + wire com_cmm_u_cmm_cfgspace_low_addr_01_7_0_bm_24__4653; + wire com_cmm_u_cmm_cfgspace_low_addr_01_7_0_am_24__4654; + wire com_cmm_u_cmm_cfgspace_N_50219; + wire com_cmm_u_cmm_cfgspace_low_addr_01_7_0_bm_25__4655; + wire com_cmm_u_cmm_cfgspace_low_addr_01_7_0_am_25__4656; + wire com_cmm_u_cmm_cfgspace_N_50220; + wire com_cmm_u_cmm_cfgspace_low_addr_01_7_0_bm_26__4657; + wire com_cmm_u_cmm_cfgspace_low_addr_01_7_0_am_26__4658; + wire com_cmm_u_cmm_cfgspace_N_51592; + wire com_cmm_u_cmm_cfgspace_N_3961; + wire com_cmm_u_cmm_cfgspace_low_addr_01_7_0_bm_27__4659; + wire com_cmm_u_cmm_cfgspace_low_addr_01_7_0_am_27__4660; + wire com_cmm_u_cmm_cfgspace_N_51593; + wire com_cmm_u_cmm_cfgspace_N_3962; + wire com_cmm_u_cmm_cfgspace_low_addr_01_7_0_bm_28__4661; + wire com_cmm_u_cmm_cfgspace_low_addr_01_7_0_am_28__4662; + wire com_cmm_u_cmm_cfgspace_N_51594; + wire com_cmm_u_cmm_cfgspace_N_3963; + wire com_cmm_u_cmm_cfgspace_low_addr_01_7_0_bm_29__4663; + wire com_cmm_u_cmm_cfgspace_low_addr_01_7_0_am_29__4664; + wire com_cmm_u_cmm_cfgspace_N_51595; + wire com_cmm_u_cmm_cfgspace_N_3964; + wire com_cmm_u_cmm_cfgspace_low_addr_01_7_0_bm_30__4665; + wire com_cmm_u_cmm_cfgspace_low_addr_01_7_0_am_30__4666; + wire com_cmm_u_cmm_cfgspace_N_51596; + wire com_cmm_u_cmm_cfgspace_N_50497; + wire com_cmm_u_cmm_cfgspace_N_3965; + wire com_cmm_u_cmm_cfgspace_low_addr_01_7_0_bm_31__4667; + wire com_cmm_u_cmm_cfgspace_low_addr_01_7_0_am_31__4668; + wire com_cmm_u_cmm_cfgspace_N_49176; + wire com_cmm_u_cmm_cfgspace_N_50463; + wire com_cmm_u_cmm_cfgspace_N_50464; + wire com_cmm_u_cmm_cfgspace_N_49177_1; + wire com_cmm_u_cmm_cfgspace_N_42097; + wire com_cmm_u_cmm_cfgspace_N_49173; + wire com_cmm_u_cmm_cfgspace_N_50466_2; + wire com_cmm_u_cmm_cfgspace_N_49172; + wire com_cmm_u_cmm_cfgspace_sel_0x_3_0_0_0_0; + wire com_cmm_u_cmm_cfgspace_N_48876_i; + wire com_cmm_u_cmm_cfgspace_N_50520_1; + wire com_cmm_u_cmm_cfgspace_N_48875_i; + wire com_cmm_u_cmm_cfgspace_N_48849; + wire com_cmm_u_cmm_cfgspace_N_51562; + wire com_cmm_u_cmm_cfgspace_N_51532; + wire com_cmm_u_cmm_cfgspace_N_51561; + wire com_cmm_u_cmm_cfgspace_N_51531; + wire com_cmm_u_cmm_cfgspace_N_49015; + wire com_cmm_u_cmm_cfgspace_N_42538_1; + wire com_cmm_u_cmm_cfgspace_N_45410_1; + wire com_cmm_u_cmm_cfgspace_N_45424_1; + wire com_cmm_u_cmm_cfgspace_N_48888_i; + wire com_cmm_u_cmm_cfgspace_N_48892_i; + wire com_cmm_u_cmm_cfgspace_bar3_reg_8_1_0_0_0_0_3_; + wire com_cmm_u_cmm_cfgspace_bar3_reg_8_1_0_0_0_2_; + wire com_cmm_u_cmm_cfgspace_bar3_reg_8_1_0_0_0_0_1_; + wire com_cmm_u_cmm_cfgspace_bar3_reg_8_1_0_0_0_0_; + wire com_cmm_u_cmm_cfgspace_N_48891_i; + wire com_cmm_u_cmm_cfgspace_bar4_reg_8_1_0_0_0_3_; + wire com_cmm_u_cmm_cfgspace_bar4_reg_8_1_0_0_0_2_; + wire com_cmm_u_cmm_cfgspace_bar4_reg_8_1_0_0_0_0_; + wire com_cmm_u_cmm_cfgspace_N_48894_i; + wire com_cmm_u_cmm_cfgspace_N_48893_i; + wire com_cmm_u_cmm_cfgspace_N_49117; + wire com_cmm_u_cmm_cfgspace_N_68389_i_4669; + wire com_cmm_u_cmm_cfgspace_N_68388_i_4670; + wire com_cmm_u_cmm_cfgspace_N_48842_i; + wire com_cmm_u_cmm_cfgspace_N_44871_i; + wire com_cmm_u_cmm_cfgspace_N_48863_i; + wire com_cmm_u_cmm_cfgspace_N_48953_i; + wire com_cmm_u_cmm_cfgspace_N_21770_i; + wire com_cmm_u_cmm_cfgspace_low_addr_00_i_0_0_31_32092_4671; + wire com_cmm_u_cmm_cfgspace_N_45565; + wire com_cmm_u_cmm_cfgspace_N_43767_i; + wire com_cmm_u_cmm_cfgspace_low_addr_00_i_30_32097_4672; + wire com_cmm_u_cmm_cfgspace_N_45361; + wire com_cmm_u_cmm_cfgspace_N_68226_i_4673; + wire com_cmm_u_cmm_cfgspace_low_addr_00_i_i_0_2_29__4674; + wire com_cmm_u_cmm_cfgspace_low_addr_00_i_i_0_1_29__4675; + wire com_cmm_u_cmm_cfgspace_N_43765_i; + wire com_cmm_u_cmm_cfgspace_low_addr_00_i_28_32102_4676; + wire com_cmm_u_cmm_cfgspace_N_45355; + wire com_cmm_u_cmm_cfgspace_N_43763_i; + wire com_cmm_u_cmm_cfgspace_low_addr_00_i_0_1_27__4677; + wire com_cmm_u_cmm_cfgspace_N_50144; + wire com_cmm_u_cmm_cfgspace_N_50143; + wire com_cmm_u_cmm_cfgspace_N_43761_i; + wire com_cmm_u_cmm_cfgspace_low_addr_00_i_26_32107_4678; + wire com_cmm_u_cmm_cfgspace_N_45343; + wire com_cmm_u_cmm_cfgspace_N_43759_i; + wire com_cmm_u_cmm_cfgspace_low_addr_00_i_25_32112_4679; + wire com_cmm_u_cmm_cfgspace_N_45337; + wire com_cmm_u_cmm_cfgspace_N_43757_i; + wire com_cmm_u_cmm_cfgspace_low_addr_00_i_24_32117_4680; + wire com_cmm_u_cmm_cfgspace_N_45331; + wire com_cmm_u_cmm_cfgspace_N_43755_i; + wire com_cmm_u_cmm_cfgspace_low_addr_00_i_23_32122_4681; + wire com_cmm_u_cmm_cfgspace_N_45325; + wire com_cmm_u_cmm_cfgspace_N_43753_i; + wire com_cmm_u_cmm_cfgspace_low_addr_00_i_22_32127_4682; + wire com_cmm_u_cmm_cfgspace_N_45319; + wire com_cmm_u_cmm_cfgspace_N_68214_i_4683; + wire com_cmm_u_cmm_cfgspace_low_addr_00_0_2_21__4684; + wire com_cmm_u_cmm_cfgspace_low_addr_00_0_1_21__4685; + wire com_cmm_u_cmm_cfgspace_low_addr_00_0_0_21__4686; + wire com_cmm_u_cmm_cfgspace_N_43750_i; + wire com_cmm_u_cmm_cfgspace_low_addr_00_i_20_32132_4687; + wire com_cmm_u_cmm_cfgspace_N_50452; + wire com_cmm_u_cmm_cfgspace_N_45306; + wire com_cmm_u_cmm_cfgspace_N_68227_i_4688; + wire com_cmm_u_cmm_cfgspace_low_addr_00_i_i_0_2_19__4689; + wire com_cmm_u_cmm_cfgspace_low_addr_00_i_i_0_1_19__4690; + wire com_cmm_u_cmm_cfgspace_low_addr_00_i_i_0_0_19__4691; + wire com_cmm_u_cmm_cfgspace_N_68212_i_4692; + wire com_cmm_u_cmm_cfgspace_low_addr_00_0_2_18__4693; + wire com_cmm_u_cmm_cfgspace_low_addr_00_0_1_18__4694; + wire com_cmm_u_cmm_cfgspace_low_addr_00_0_0_18__4695; + wire com_cmm_u_cmm_cfgspace_N_68225_i_4696; + wire com_cmm_u_cmm_cfgspace_low_addr_00_i_i_0_2_17__4697; + wire com_cmm_u_cmm_cfgspace_low_addr_00_i_i_0_1_17__4698; + wire com_cmm_u_cmm_cfgspace_low_addr_00_i_i_0_0_17__4699; + wire com_cmm_u_cmm_cfgspace_N_43747_i; + wire com_cmm_u_cmm_cfgspace_low_addr_00_i_0_1_16__4700; + wire com_cmm_u_cmm_cfgspace_N_43745_i; + wire com_cmm_u_cmm_cfgspace_low_addr_00_0_0_i_15_32135_4701; + wire com_cmm_u_cmm_cfgspace_low_addr_00_0_0_i_15_32134_4702; + wire com_cmm_u_cmm_cfgspace_N_68184_i_4703; + wire com_cmm_u_cmm_cfgspace_N_68183_i_4704; + wire com_cmm_u_cmm_cfgspace_N_68182_i_4705; + wire com_cmm_u_cmm_cfgspace_N_50451; + wire com_cmm_u_cmm_cfgspace_N_68191_i_4706; + wire com_cmm_u_cmm_cfgspace_N_68210_i_4707; + wire com_cmm_u_cmm_cfgspace_low_addr_00_0_1_10__4708; + wire com_cmm_u_cmm_cfgspace_low_addr_00_0_0_10__4709; + wire com_cmm_u_cmm_cfgspace_N_68209_i_4710; + wire com_cmm_u_cmm_cfgspace_low_addr_00_0_1_9__4711; + wire com_cmm_u_cmm_cfgspace_low_addr_00_0_0_9__4712; + wire com_cmm_u_cmm_cfgspace_N_68208_i_4713; + wire com_cmm_u_cmm_cfgspace_low_addr_00_0_1_8__4714; + wire com_cmm_u_cmm_cfgspace_low_addr_00_0_0_8__4715; + wire com_cmm_u_cmm_cfgspace_N_68207_i_4716; + wire com_cmm_u_cmm_cfgspace_low_addr_00_0_1_7__4717; + wire com_cmm_u_cmm_cfgspace_low_addr_00_0_0_7__4718; + wire com_cmm_u_cmm_cfgspace_N_68206_i_4719; + wire com_cmm_u_cmm_cfgspace_low_addr_00_0_1_6__4720; + wire com_cmm_u_cmm_cfgspace_low_addr_00_0_0_6__4721; + wire com_cmm_u_cmm_cfgspace_N_68205_i_4722; + wire com_cmm_u_cmm_cfgspace_low_addr_00_0_1_5__4723; + wire com_cmm_u_cmm_cfgspace_low_addr_00_0_0_5__4724; + wire com_cmm_u_cmm_cfgspace_N_68204_i_4725; + wire com_cmm_u_cmm_cfgspace_low_addr_00_0_1_4__4726; + wire com_cmm_u_cmm_cfgspace_low_addr_00_0_0_4__4727; + wire com_cmm_u_cmm_cfgspace_N_68203_i_4728; + wire com_cmm_u_cmm_cfgspace_low_addr_00_0_1_3__4729; + wire com_cmm_u_cmm_cfgspace_low_addr_00_0_0_3__4730; + wire com_cmm_u_cmm_cfgspace_N_68202_i_4731; + wire com_cmm_u_cmm_cfgspace_low_addr_00_0_1_2__4732; + wire com_cmm_u_cmm_cfgspace_low_addr_00_0_0_2__4733; + wire com_cmm_u_cmm_cfgspace_N_50454; + wire com_cmm_u_cmm_cfgspace_N_43731_i; + wire com_cmm_u_cmm_cfgspace_low_addr_00_i_0_1_1__4734; + wire com_cmm_u_cmm_cfgspace_N_50495; + wire com_cmm_u_cmm_cfgspace_N_4382; + wire com_cmm_u_cmm_cfgspace_N_4286; + wire com_cmm_u_cmm_cfgspace_N_4380; + wire com_cmm_u_cmm_cfgspace_N_4284; + wire com_cmm_u_cmm_cfgspace_N_4378; + wire com_cmm_u_cmm_cfgspace_N_4282; + wire com_cmm_u_cmm_cfgspace_N_4377; + wire com_cmm_u_cmm_cfgspace_N_4281; + wire com_cmm_u_cmm_cfgspace_N_68098_i_4735; + wire com_cmm_u_cmm_cfgspace_sel_encodex_en_3_i_0_32190_4736; + wire com_cmm_u_cmm_cfgspace_sel_encodex_en_3_i_0_32188_4737; + wire com_cmm_u_cmm_cfgspace_N_49170; + wire com_cmm_u_cmm_cfgspace_N_4104; + wire com_cmm_u_cmm_cfgspace_N_4008; + wire com_cmm_u_cmm_cfgspace_N_4094; + wire com_cmm_u_cmm_cfgspace_N_3998; + wire com_cmm_u_cmm_cfgspace_N_68391_i_4738; + wire com_cmm_u_cmm_cfgspace_N_68392_i_4739; + wire com_cmm_u_cmm_cfgspace_N_68712_i_4740; + wire com_cmm_u_cmm_cfgspace_N_68390_i_4741; + wire com_cmm_u_cmm_cfgspace_N_50498; + wire com_cmm_u_cmm_cfgspace_N_50140; + wire com_cmm_u_cmm_cfgspace_N_50450; + wire com_cmm_u_cmm_cfgspace_N_45979; + wire com_cmm_u_cmm_cfgspace_N_45965; + wire com_cmm_u_cmm_cfgspace_N_45314; + wire com_cmm_u_cmm_cfgspace_N_45300; + wire com_cmm_u_cmm_cfgspace_N_50490; + wire com_cmm_u_cmm_cfgspace_N_43088_1; + wire com_cmm_u_cmm_cfgspace_N_42636_1; + wire com_cmm_u_cmm_cfgspace_N_48878_i; + wire com_cmm_u_cmm_cfgspace_N_48848_i; + wire com_cmm_u_cmm_cfgspace_N_48973_i; + wire com_cmm_u_cmm_cfgspace_N_42634_1; + wire com_cmm_u_cmm_cfgspace_set_unsupportedreq_4742; + wire com_cmm_u_cmm_cfgspace_set_detectednonfatal_4743; + wire com_cmm_u_cmm_cfgspace_set_detectedfatal_4744; + wire com_cmm_u_cmm_cfgspace_set_detectedcorrectable_4745; + wire com_cmm_u_cmm_cfgspace_set_signaledtargetabort_4746; + wire com_cmm_u_cmm_cfgspace_set_signaledsystemerror_4747; + wire com_cmm_u_cmm_cfgspace_set_signaledpme_4748; + wire com_cmm_u_cmm_cfgspace_set_receivedtargetabort_4749; + wire com_cmm_u_cmm_cfgspace_set_receivedmasterabort_4750; + wire com_cmm_u_cmm_cfgspace_set_masterdataparityerror_4751; + wire com_cmm_u_cmm_cfgspace_set_detectedparityerror_4752; + wire com_cmm_u_cmm_cfgspace_N_68405_i; + wire com_cmm_u_cmm_cfgspace_sel_6x_4753; + wire com_cmm_u_cmm_cfgspace_N_68711_i; + wire com_cmm_u_cmm_cfgspace_sel_5x_4754; + wire com_cmm_u_cmm_cfgspace_N_68404_i; + wire com_cmm_u_cmm_cfgspace_sel_4x_4755; + wire com_cmm_u_cmm_cfgspace_N_68336_i; + wire com_cmm_u_cmm_cfgspace_sel_3x_4756; + wire com_cmm_u_cmm_cfgspace_N_68403_i; + wire com_cmm_u_cmm_cfgspace_sel_2x_4757; + wire com_cmm_u_cmm_cfgspace_N_68402_i; + wire com_cmm_u_cmm_cfgspace_sel_1x_4758; + wire com_cmm_u_cmm_cfgspace_N_68101_i; + wire com_cmm_u_cmm_cfgspace_sel_0x_4759; + wire com_cmm_u_cmm_cfgspace_N_28239_i; + wire com_cmm_u_cmm_cfgspace_sel_x0_4760; + wire com_cmm_u_cmm_cfgspace_N_28269_i; + wire com_cmm_u_cmm_cfgspace_sel_xf_4761; + wire com_cmm_u_cmm_cfgspace_N_28267_i; + wire com_cmm_u_cmm_cfgspace_sel_xe_4762; + wire com_cmm_u_cmm_cfgspace_N_28265_i; + wire com_cmm_u_cmm_cfgspace_sel_xd_4763; + wire com_cmm_u_cmm_cfgspace_N_28263_i; + wire com_cmm_u_cmm_cfgspace_sel_xc_4764; + wire com_cmm_u_cmm_cfgspace_N_28261_i; + wire com_cmm_u_cmm_cfgspace_sel_xb_4765; + wire com_cmm_u_cmm_cfgspace_N_28259_i; + wire com_cmm_u_cmm_cfgspace_sel_xa_4766; + wire com_cmm_u_cmm_cfgspace_N_28257_i; + wire com_cmm_u_cmm_cfgspace_sel_x9_4767; + wire com_cmm_u_cmm_cfgspace_N_28255_i; + wire com_cmm_u_cmm_cfgspace_sel_x8_4768; + wire com_cmm_u_cmm_cfgspace_N_28253_i; + wire com_cmm_u_cmm_cfgspace_sel_x7_4769; + wire com_cmm_u_cmm_cfgspace_N_28251_i; + wire com_cmm_u_cmm_cfgspace_sel_x6_4770; + wire com_cmm_u_cmm_cfgspace_N_28249_i; + wire com_cmm_u_cmm_cfgspace_sel_x5_4771; + wire com_cmm_u_cmm_cfgspace_N_28247_i; + wire com_cmm_u_cmm_cfgspace_sel_x4_4772; + wire com_cmm_u_cmm_cfgspace_N_28245_i; + wire com_cmm_u_cmm_cfgspace_sel_x3_4773; + wire com_cmm_u_cmm_cfgspace_N_28243_i; + wire com_cmm_u_cmm_cfgspace_sel_x2_4774; + wire com_cmm_u_cmm_cfgspace_N_28241_i; + wire com_cmm_u_cmm_cfgspace_sel_x1_4775; + wire com_cmm_u_cmm_cfgspace_N_43646_i; + wire com_cmm_u_cmm_cfgspace_N_43644_i; + wire com_cmm_u_cmm_cfgspace_N_8858_i; + wire com_cmm_u_cmm_cfgspace_N_8857_i; + wire com_cmm_u_cmm_cfgspace_N_8856_i; + wire com_cmm_u_cmm_cfgspace_set_signaledint_4776; + wire com_cmm_u_cmm_cfgspace_N_8855_i; + wire com_cmm_u_cmm_cfgspace_N_40379_i; + wire com_cmm_u_cmm_cfgspace_N_44495_i; + wire com_cmm_u_cmm_cfgspace_N_43650_i; + wire com_cmm_u_cmm_cfgspace_N_43648_i; + wire com_cmm_u_cmm_cfgspace_state_5__4777; + wire com_cmm_u_cmm_cfgspace_N_14826_i; + wire com_cmm_u_cmm_cfgspace_state_4__4778; + wire com_cmm_u_cmm_cfgspace_state_2__4779; + wire com_cmm_u_cmm_cfgspace_N_14828_i; + wire com_cmm_u_cmm_cfgspace_state_1__4780; + wire com_cmm_u_cmm_cfgspace_N_68102_i_4781; + wire com_cmm_u_cmm_cfgspace_state_0__4782; + wire com_cmm_u_cmm_cfgspace_set_transaction_pending_4783; + wire com_cmm_u_cmm_cfgspace_N_8854_i; + wire com_cmm_u_cmm_cfgspace_N_8853_i; + wire com_cmm_u_cmm_cfgspace_N_8852_i; + wire com_cmm_u_cmm_cfgspace_N_8851_i; + wire com_cmm_u_cmm_cfgspace_N_8861_i; + wire com_cmm_u_cmm_cfgspace_N_8860_i; + wire com_cmm_u_cmm_cfgspace_N_8859_i; + wire com_cmm_u_cmm_cfgspace_N_44856_i; + wire com_cmm_u_cmm_cfgspace_N_68143_i; + wire com_cmm_u_cmm_cfgspace_N_68008_i; + wire com_cmm_u_cmm_cfgspace_N_68142_i; + wire com_cmm_u_cmm_cfgspace_N_68007_i; + wire com_cmm_u_cmm_cfgspace_bar1_reg58; + wire com_cmm_u_cmm_cfgspace_bar1_reg45; + wire com_cmm_u_cmm_cfgspace_N_44857_i; + wire com_cmm_u_cmm_cfgspace_N_68145_i; + wire com_cmm_u_cmm_cfgspace_N_68010_i; + wire com_cmm_u_cmm_cfgspace_N_68144_i; + wire com_cmm_u_cmm_cfgspace_N_68009_i; + wire com_cmm_u_cmm_cfgspace_bar1_reg70; + wire com_cmm_u_cmm_cfgspace_bar2_reg58; + wire com_cmm_u_cmm_cfgspace_bar2_reg45; + wire com_cmm_u_cmm_cfgspace_N_44858_i; + wire com_cmm_u_cmm_cfgspace_N_68147_i; + wire com_cmm_u_cmm_cfgspace_N_68012_i; + wire com_cmm_u_cmm_cfgspace_N_68146_i; + wire com_cmm_u_cmm_cfgspace_N_68011_i; + wire com_cmm_u_cmm_cfgspace_bar2_reg70; + wire com_cmm_u_cmm_cfgspace_bar3_reg58; + wire com_cmm_u_cmm_cfgspace_bar3_reg45; + wire com_cmm_u_cmm_cfgspace_N_48868_i; + wire com_cmm_u_cmm_cfgspace_N_68151_i; + wire com_cmm_u_cmm_cfgspace_N_68150_i; + wire com_cmm_u_cmm_cfgspace_N_68149_i; + wire com_cmm_u_cmm_cfgspace_N_68148_i; + wire com_cmm_u_cmm_cfgspace_bar3_reg70; + wire com_cmm_u_cmm_cfgspace_bar4_reg58; + wire com_cmm_u_cmm_cfgspace_bar4_reg45; + wire com_cmm_u_cmm_cfgspace_N_68141_i; + wire com_cmm_u_cmm_cfgspace_N_68140_i; + wire com_cmm_u_cmm_cfgspace_N_68139_i; + wire com_cmm_u_cmm_cfgspace_N_68138_i; + wire com_cmm_u_cmm_cfgspace_bar4_reg70; + wire com_cmm_u_cmm_cfgspace_bar5_reg45; + wire com_cmm_u_cmm_cfgspace_N_44854_i; + wire com_cmm_u_cmm_cfgspace_N_68512_i_4784; + wire com_cmm_u_cmm_cfgspace_N_20148_i; + wire com_cmm_u_cmm_cfgspace_N_43713_i; + wire com_cmm_u_cmm_cfgspace_N_29858_i; + wire com_cmm_u_cmm_cfgspace_N_43947_i; + wire com_cmm_u_cmm_cfgspace_bar5_reg70; + wire com_cmm_u_cmm_cfgspace_bar5_reg58; + wire com_cmm_u_cmm_cfgspace_N_29864_i; + wire com_cmm_u_cmm_cfgspace_N_68560_i_4785; + wire com_cmm_u_cmm_cfgspace_N_32900_i; + wire com_cmm_u_cmm_cfgspace_N_68513_i_4786; + wire com_cmm_u_cmm_cfgspace_x_dcmd_1_sqmuxa_1; + wire com_cmm_u_cmm_cfgspace_N_29862_i; + wire com_cmm_u_cmm_cfgspace_N_29860_i; + wire com_cmm_u_cmm_cfgspace_N_20154_i; + wire com_cmm_u_cmm_cfgspace_N_20152_i; + wire com_cmm_u_cmm_cfgspace_N_20150_i; + wire com_cmm_u_cmm_cfgspace_msi_haddr23; + wire com_cmm_u_cmm_cfgspace_msi_haddr12; + wire com_cmm_u_cmm_cfgspace_msi_haddr46; + wire com_cmm_u_cmm_cfgspace_msi_haddr35; + wire com_cmm_u_cmm_cfgspace_msi_data22; + wire com_cmm_u_cmm_cfgspace_msi_data12; + wire com_cmm_u_cmm_cfgspace_command93; + wire com_cmm_u_cmm_cfgspace_command67; + wire com_cmm_u_cmm_cfgspace_x_lcmd22; + wire com_cmm_u_cmm_cfgspace_bar0_reg31; + wire com_cmm_u_cmm_cfgspace_bar0_reg18; + wire com_cmm_u_cmm_cfgspace_bar0_reg56; + wire com_cmm_u_cmm_cfgspace_bar0_reg44; + wire com_cmm_u_cmm_cfgspace_msi_laddr28; + wire com_cmm_u_cmm_cfgspace_msi_laddr16; + wire com_cmm_u_cmm_cfgspace_msi_laddr51; + wire com_cmm_u_cmm_cfgspace_msi_laddr40; + wire com_cmm_u_cmm_cfgspace_VCC_4787; + wire com_cmm_u_cmm_cfgspace_cache_line8; + wire com_cmm_u_cmm_cfgspace_int_line8; + wire com_cmm_u_cmm_cfgspace_msi_control27; + wire com_cmm_u_cmm_cfgspace_xrom_reg_0_sqmuxa; + wire com_cmm_u_cmm_cfgspace_N_68355_i; + wire com_cmm_u_cmm_cfgspace_N_68335_i; + wire com_cmm_u_cmm_cfgspace_N_68334_i; + wire com_cmm_u_cmm_cfgspace_N_68333_i; + wire com_cmm_u_cmm_cfgspace_N_68332_i; + wire com_cmm_u_cmm_cfgspace_N_68354_i; + wire com_cmm_u_cmm_cfgspace_N_68353_i; + wire com_cmm_u_cmm_cfgspace_N_68352_i; + wire com_cmm_u_cmm_cfgspace_N_68401_i; + wire com_cmm_u_cmm_cfgspace_N_68400_i; + wire com_cmm_u_cmm_cfgspace_N_68399_i; + wire com_cmm_u_cmm_cfgspace_N_68398_i; + wire com_cmm_u_cmm_cfgspace_N_68397_i; + wire com_cmm_u_cmm_cfgspace_N_68396_i; + wire com_cmm_u_cmm_cfgspace_N_68395_i; + wire com_cmm_u_cmm_cfgspace_N_68394_i; + wire com_cmm_u_cmm_cfgspace_N_68351_i; + wire com_cmm_u_cmm_cfgspace_N_68350_i; + wire com_cmm_u_cmm_cfgspace_N_68349_i; + wire com_cmm_u_cmm_cfgspace_N_68393_i; + wire com_cmm_u_cmm_cfgspace_N_68348_i; + wire com_cmm_u_cmm_cfgspace_cfg2ulm_valid; + wire com_cmm_u_cmm_cfgspace_N_15295_i; + wire com_cmm_u_cmm_cfgspace_low_addr_00_i_0_0_0_32087_4788; + wire com_cmm_u_cmm_cfgspace_N_42541; + wire com_cmm_u_cmm_errman_cplu_add_sub_b; + wire com_cmm_u_cmm_errman_cplt_add_sub_b; + wire com_cmm_u_cmm_errman_ftl_add_sub_b; + wire com_cmm_u_cmm_errman_nfl_add_sub_b; + wire com_cmm_u_cmm_errman_cor_add_sub_b; + wire com_cmm_u_cmm_errman_to_incr_0ro; + wire com_cmm_u_cmm_errman_reg_decr_nfl; + wire com_cmm_u_cmm_errman_reg_decr_cor; + wire com_cmm_u_cmm_errman_to_incr_2ro; + wire com_cmm_u_cmm_errman_to_incr_1ro; + wire com_cmm_u_cmm_errman_nfl_num_c1_4789; + wire com_cmm_u_cmm_errman_un1_reg_uflow_3_1; + wire com_cmm_u_cmm_errman_send_cor_3_0_a2_4790; + wire com_cmm_u_cmm_errman_un1_reg_uflow_3_0; + wire com_cmm_u_cmm_errman_send_ftl_3_0_a2_4791; + wire com_cmm_u_cmm_errman_un1_reg_uflow_3; + wire com_cmm_u_cmm_errman_reg_detectednonfatal_3_i_0_0_0_1_4792; + wire com_cmm_u_cmm_errman_reg_detectedcorrectable_3_i_0_0_1_4793; + wire com_cmm_u_cmm_errman_reg_detectedcorrectable_3_i_0_0_a2_0_4794; + wire com_cmm_u_cmm_errman_N_48933_i; + wire com_cmm_u_cmm_errman_N_48948_i; + wire com_cmm_u_cmm_errman_N_49571; + wire com_cmm_u_cmm_errman_N_49569; + wire com_cmm_u_cmm_errman_N_48984_i; + wire com_cmm_u_cmm_errman_N_49573_1; + wire com_cmm_u_cmm_errman_N_48944_i; + wire com_cmm_u_cmm_errman_N_48916_i; + wire com_cmm_u_cmm_errman_N_50749; + wire com_cmm_u_cmm_errman_N_49488; + wire com_cmm_u_cmm_errman_N_42551_i_4795; + wire com_cmm_u_cmm_errman_reg_detectedcorrectable_3_i_0_0_a2_4796; + wire com_cmm_u_cmm_errman_replay_vld_i_4797; + wire com_cmm_u_cmm_errman_N_15818_i; + wire com_cmm_u_cmm_errman_N_68760_i_4798; + wire com_cmm_u_cmm_errman_N_49554; + wire com_cmm_u_cmm_errman_N_68492_i_4799; + wire com_cmm_u_cmm_errman_N_68491_i_4800; + wire com_cmm_u_cmm_errman_cfg_is_np_and_cpl_abort; + wire com_cmm_u_cmm_errman_un1_reg_uflow_3_i_1_4801; + wire com_cmm_u_cmm_errman_send_cplt_4802; + wire com_cmm_u_cmm_errman_N_51019_i_4803; + wire com_cmm_u_cmm_errman_send_cor_4804; + wire com_cmm_u_cmm_errman_N_96_2_i; + wire com_cmm_u_cmm_errman_cs_is_ftl32; + wire com_cmm_u_cmm_errman_cs_is_ftl31; + wire com_cmm_u_cmm_errman_cs_is_ftl_4805; + wire com_cmm_u_cmm_errman_cs_is_ftl29; + wire com_cmm_u_cmm_errman_cs_is_cplu_4806; + wire com_cmm_u_cmm_errman_cs_is_ftl30; + wire com_cmm_u_cmm_errman_cs_is_cplt_4807; + wire com_cmm_u_cmm_errman_cs_is_ftl33; + wire com_cmm_u_cmm_errman_cs_is_cor_4808; + wire com_cmm_u_cmm_errman_N_49807; + wire com_cmm_u_cmm_errman_reg_incr_cplu_4809; + wire com_cmm_u_cmm_errman_N_68759_i_4810; + wire com_cmm_u_cmm_errman_reg_masterdataparityerror_3_4811; + wire com_cmm_u_cmm_errman_un1_reg_uflow_3_i_0_4812; + wire com_cmm_u_cmm_errman_send_nfl_4813; + wire com_cmm_u_cmm_errman_N_51043_i_4814; + wire com_cmm_u_cmm_errman_send_ftl_4815; + wire com_cmm_u_cmm_errman_un1_reg_uflow_3_i_4816; + wire com_cmm_u_cmm_errman_send_cplu_4817; + wire com_cmm_u_cmm_errman_N_68187_i_4818; + wire com_cmm_u_cmm_errman_N_67919_i_4819; + wire com_cmm_u_cmm_errman_N_47879_i; + wire com_cmm_u_cmm_errman_N_32752_i; + wire com_cmm_u_cmm_errman_N_32750_i; + wire com_cmm_u_cmm_errman_N_32748_i; + wire com_cmm_u_cmm_errman_N_32746_i; + wire com_cmm_u_cmm_errman_N_32744_i; + wire com_cmm_u_cmm_errman_un1_cs_fsm_1_0_a2_0_a2_0_a2_0_a2_4820; + wire com_cmm_u_cmm_errman_N_68159_i_4821; + wire com_cmm_u_cmm_errman_N_68160_i_4822; + wire com_cmm_u_cmm_errman_N_68198_i_4823; + wire com_cmm_u_cmm_errman_N_68481_i_4824; + wire com_cmm_u_cmm_errman_N_68617_i_4825; + wire com_cmm_u_cmm_errman_N_32782_i; + wire com_cmm_u_cmm_errman_N_32780_i; + wire com_cmm_u_cmm_errman_N_32778_i; + wire com_cmm_u_cmm_errman_N_32776_i; + wire com_cmm_u_cmm_errman_N_32774_i; + wire com_cmm_u_cmm_errman_N_32772_i; + wire com_cmm_u_cmm_errman_N_32770_i; + wire com_cmm_u_cmm_errman_N_32768_i; + wire com_cmm_u_cmm_errman_N_32766_i; + wire com_cmm_u_cmm_errman_N_32764_i; + wire com_cmm_u_cmm_errman_N_32762_i; + wire com_cmm_u_cmm_errman_N_32760_i; + wire com_cmm_u_cmm_errman_N_32758_i; + wire com_cmm_u_cmm_errman_N_32756_i; + wire com_cmm_u_cmm_errman_N_32754_i; + wire com_cmm_u_cmm_errman_N_32812_i; + wire com_cmm_u_cmm_errman_N_32810_i; + wire com_cmm_u_cmm_errman_N_32808_i; + wire com_cmm_u_cmm_errman_N_32806_i; + wire com_cmm_u_cmm_errman_N_32804_i; + wire com_cmm_u_cmm_errman_N_32802_i; + wire com_cmm_u_cmm_errman_N_32800_i; + wire com_cmm_u_cmm_errman_N_32798_i; + wire com_cmm_u_cmm_errman_N_32796_i; + wire com_cmm_u_cmm_errman_N_32794_i; + wire com_cmm_u_cmm_errman_N_32792_i; + wire com_cmm_u_cmm_errman_N_32790_i; + wire com_cmm_u_cmm_errman_N_32788_i; + wire com_cmm_u_cmm_errman_N_32786_i; + wire com_cmm_u_cmm_errman_N_32784_i; + wire com_cmm_u_cmm_errman_reg_cfg_wr_hdr20; + wire com_cmm_u_cmm_errman_cfg_is_np_and_ur; + wire com_cmm_u_cmm_errman_N_32838_i; + wire com_cmm_u_cmm_errman_N_32836_i; + wire com_cmm_u_cmm_errman_N_32834_i; + wire com_cmm_u_cmm_errman_N_32832_i; + wire com_cmm_u_cmm_errman_N_32830_i; + wire com_cmm_u_cmm_errman_N_32828_i; + wire com_cmm_u_cmm_errman_N_32826_i; + wire com_cmm_u_cmm_errman_N_32824_i; + wire com_cmm_u_cmm_errman_N_32822_i; + wire com_cmm_u_cmm_errman_N_32820_i; + wire com_cmm_u_cmm_errman_N_32818_i; + wire com_cmm_u_cmm_errman_N_32816_i; + wire com_cmm_u_cmm_errman_N_32814_i; + wire com_cmm_u_cmm_errman_N_68444_i_4826; + wire com_cmm_u_cmm_errman_N_68443_i_4827; + wire com_cmm_u_cmm_errman_N_68442_i_4828; + wire com_cmm_u_cmm_errman_N_68441_i_4829; + wire com_cmm_u_cmm_errman_N_68440_i_4830; + wire com_cmm_u_cmm_errman_N_68439_i_4831; + wire com_cmm_u_cmm_errman_N_68438_i_4832; + wire com_cmm_u_cmm_errman_N_68437_i_4833; + wire com_cmm_u_cmm_errman_N_68436_i_4834; + wire com_cmm_u_cmm_errman_N_68435_i_4835; + wire com_cmm_u_cmm_errman_N_68434_i_4836; + wire com_cmm_u_cmm_errman_N_68433_i_4837; + wire com_cmm_u_cmm_errman_N_68432_i_4838; + wire com_cmm_u_cmm_errman_N_68431_i_4839; + wire com_cmm_u_cmm_errman_N_68430_i_4840; + wire com_cmm_u_cmm_errman_N_68459_i_4841; + wire com_cmm_u_cmm_errman_N_68458_i_4842; + wire com_cmm_u_cmm_errman_N_68457_i_4843; + wire com_cmm_u_cmm_errman_N_68456_i_4844; + wire com_cmm_u_cmm_errman_N_68455_i_4845; + wire com_cmm_u_cmm_errman_N_68454_i_4846; + wire com_cmm_u_cmm_errman_N_68453_i_4847; + wire com_cmm_u_cmm_errman_N_68452_i_4848; + wire com_cmm_u_cmm_errman_N_68451_i_4849; + wire com_cmm_u_cmm_errman_N_68450_i_4850; + wire com_cmm_u_cmm_errman_N_68449_i_4851; + wire com_cmm_u_cmm_errman_N_68448_i_4852; + wire com_cmm_u_cmm_errman_N_68447_i_4853; + wire com_cmm_u_cmm_errman_N_68446_i_4854; + wire com_cmm_u_cmm_errman_N_68445_i_4855; + wire com_cmm_u_cmm_errman_N_68474_i_4856; + wire com_cmm_u_cmm_errman_N_68473_i_4857; + wire com_cmm_u_cmm_errman_N_68472_i_4858; + wire com_cmm_u_cmm_errman_N_68471_i_4859; + wire com_cmm_u_cmm_errman_N_68470_i_4860; + wire com_cmm_u_cmm_errman_N_68469_i_4861; + wire com_cmm_u_cmm_errman_N_68468_i_4862; + wire com_cmm_u_cmm_errman_N_68467_i_4863; + wire com_cmm_u_cmm_errman_N_68466_i_4864; + wire com_cmm_u_cmm_errman_N_68465_i_4865; + wire com_cmm_u_cmm_errman_N_68464_i_4866; + wire com_cmm_u_cmm_errman_N_68463_i_4867; + wire com_cmm_u_cmm_errman_N_68462_i_4868; + wire com_cmm_u_cmm_errman_N_68461_i_4869; + wire com_cmm_u_cmm_errman_N_68460_i_4870; + wire com_cmm_u_cmm_errman_N_68479_i_4871; + wire com_cmm_u_cmm_errman_N_68478_i_4872; + wire com_cmm_u_cmm_errman_N_68477_i_4873; + wire com_cmm_u_cmm_errman_N_68476_i_4874; + wire com_cmm_u_cmm_errman_N_68475_i_4875; + wire com_cmm_u_cmm_errman_N_48855_i; + wire com_cmm_u_cmm_errman_N_15633_i; + wire com_cmm_u_cmm_errman_reg_signaledsystemerror_9_i_0_0_0_1_4876; + wire com_cmm_u_cmm_errman_cs_is_nfl_4877; + wire com_cmm_u_cmm_errman_wtd_cor_N_50354_i_4878; + wire com_cmm_u_cmm_errman_wtd_cor_N_48971_i_0; + wire com_cmm_u_cmm_errman_wtd_cor_un4_reg_inc_dec_b_0_a2_0_a2_0_o3_0_2_4879; + wire com_cmm_u_cmm_errman_cor_cntr_un14_reg_cnt_cry_0_4880; + wire com_cmm_u_cmm_errman_cor_cntr_un14_reg_cnt_cry_1_4881; + wire com_cmm_u_cmm_errman_cor_cntr_GND_4882; + wire com_cmm_u_cmm_errman_cor_cntr_un14_reg_cnt_cry_2_4883; + wire com_cmm_u_cmm_errman_cor_cntr_un25_reg_cnt_cry_0_4884; + wire com_cmm_u_cmm_errman_cor_cntr_un25_reg_cnt_cry_1_4885; + wire com_cmm_u_cmm_errman_cor_cntr_VCC_4886; + wire com_cmm_u_cmm_errman_cor_cntr_un25_reg_cnt_cry_2_4887; + wire com_cmm_u_cmm_errman_cor_cntr_N_20762_i; + wire com_cmm_u_cmm_errman_cor_cntr_un14_reg_cnt_cry_3_4888; + wire com_cmm_u_cmm_errman_cor_cntr_reg_uflow_3_i_a2_0_4889; + wire com_cmm_u_cmm_errman_cor_cntr_un14_reg_cnt_s_3_4890; + wire com_cmm_u_cmm_errman_cor_cntr_un25_reg_cnt_s_3_4891; + wire com_cmm_u_cmm_errman_cor_cntr_un14_reg_cnt_s_2_4892; + wire com_cmm_u_cmm_errman_cor_cntr_un25_reg_cnt_s_2_4893; + wire com_cmm_u_cmm_errman_cor_cntr_un14_reg_cnt_s_1_4894; + wire com_cmm_u_cmm_errman_cor_cntr_un25_reg_cnt_s_1_4895; + wire com_cmm_u_cmm_errman_cor_cntr_un25_reg_cnt_axb_0_4896; + wire com_cmm_u_cmm_errman_cor_cntr_un14_reg_cnt_axb_0_4897; + wire com_cmm_u_cmm_errman_cor_cntr_reg_inc_dec_b_4898; + wire com_cmm_u_cmm_errman_cor_cntr_reg_extra_6; + wire com_cmm_u_cmm_errman_cor_cntr_reg_extra_4899; + wire com_cmm_u_cmm_errman_cor_cntr_N_15408_i; + wire com_cmm_u_cmm_errman_cor_cntr_N_20776_i; + wire com_cmm_u_cmm_errman_cor_cntr_N_20774_i; + wire com_cmm_u_cmm_errman_cor_cntr_N_20772_i; + wire com_cmm_u_cmm_errman_cor_cntr_N_20770_i; + wire com_cmm_u_cmm_errman_cor_cntr_un25_reg_cnt_s_4_4900; + wire com_cmm_u_cmm_errman_cor_cntr_un25_reg_cnt_cry_3_4901; + wire com_cmm_u_cmm_errman_cor_cntr_un25_reg_cnt_axb_3_i_i_4902; + wire com_cmm_u_cmm_errman_cor_cntr_un25_reg_cnt_axb_2_4903; + wire com_cmm_u_cmm_errman_cor_cntr_un25_reg_cnt_axb_1_4904; + wire com_cmm_u_cmm_errman_cor_cntr_un14_reg_cnt_axb_3_4905; + wire com_cmm_u_cmm_errman_cor_cntr_reg_uflow_4906; + wire com_cmm_u_cmm_errman_cor_cntr_oflow; + wire com_cmm_u_cmm_errman_cor_cntr_un14_reg_cnt_axb_2_4907; + wire com_cmm_u_cmm_errman_cor_cntr_N_20766_i; + wire com_cmm_u_cmm_errman_cor_cntr_un14_reg_cnt_axb_1_4908; + wire com_cmm_u_cmm_errman_cor_cntr_N_20764_i; + wire com_cmm_u_cmm_errman_wtd_nfl_un4_reg_inc_dec_b_i_4909; + wire com_cmm_u_cmm_errman_wtd_nfl_N_48974_i_0; + wire com_cmm_u_cmm_errman_wtd_nfl_N_48970_i; + wire com_cmm_u_cmm_errman_nfl_cntr_un14_reg_cnt_cry_0_4910; + wire com_cmm_u_cmm_errman_nfl_cntr_un14_reg_cnt_cry_1_4911; + wire com_cmm_u_cmm_errman_nfl_cntr_GND_4912; + wire com_cmm_u_cmm_errman_nfl_cntr_un14_reg_cnt_cry_2_4913; + wire com_cmm_u_cmm_errman_nfl_cntr_un25_reg_cnt_cry_0_4914; + wire com_cmm_u_cmm_errman_nfl_cntr_un25_reg_cnt_cry_1_4915; + wire com_cmm_u_cmm_errman_nfl_cntr_VCC_4916; + wire com_cmm_u_cmm_errman_nfl_cntr_un25_reg_cnt_cry_2_4917; + wire com_cmm_u_cmm_errman_nfl_cntr_reg_uflow_3_i_a2_0_4918; + wire com_cmm_u_cmm_errman_nfl_cntr_un25_reg_cnt_axb_0_4919; + wire com_cmm_u_cmm_errman_nfl_cntr_reg_inc_dec_b_4920; + wire com_cmm_u_cmm_errman_nfl_cntr_reg_extra_6_0_u_i_m2_0_1; + wire com_cmm_u_cmm_errman_nfl_cntr_reg_extra_4921; + wire com_cmm_u_cmm_errman_nfl_cntr_N_15453_i; + wire com_cmm_u_cmm_errman_nfl_cntr_reg_uflow_4922; + wire com_cmm_u_cmm_errman_nfl_cntr_N_22217_i; + wire com_cmm_u_cmm_errman_nfl_cntr_un25_reg_cnt_cry_3_4923; + wire com_cmm_u_cmm_errman_nfl_cntr_un25_reg_cnt_axb_3_i_i_4924; + wire com_cmm_u_cmm_errman_nfl_cntr_un25_reg_cnt_axb_2_4925; + wire com_cmm_u_cmm_errman_nfl_cntr_un25_reg_cnt_axb_1_4926; + wire com_cmm_u_cmm_errman_nfl_cntr_un14_reg_cnt_axb_3_4927; + wire com_cmm_u_cmm_errman_nfl_cntr_un25_reg_cnt_axb_3_i; + wire com_cmm_u_cmm_errman_nfl_cntr_un14_reg_cnt_axb_2_4928; + wire com_cmm_u_cmm_errman_nfl_cntr_N_22221_i; + wire com_cmm_u_cmm_errman_nfl_cntr_un14_reg_cnt_axb_1_4929; + wire com_cmm_u_cmm_errman_nfl_cntr_N_22219_i; + wire com_cmm_u_cmm_errman_wtd_ftl_N_50356_i_4930; + wire com_cmm_u_cmm_errman_ftl_cntr_un25_reg_cnt_cry_0_4931; + wire com_cmm_u_cmm_errman_ftl_cntr_un25_reg_cnt_cry_1_4932; + wire com_cmm_u_cmm_errman_ftl_cntr_VCC_4933; + wire com_cmm_u_cmm_errman_ftl_cntr_un25_reg_cnt_cry_2_4934; + wire com_cmm_u_cmm_errman_ftl_cntr_un14_reg_cnt_cry_0_4935; + wire com_cmm_u_cmm_errman_ftl_cntr_un14_reg_cnt_cry_1_4936; + wire com_cmm_u_cmm_errman_ftl_cntr_GND_4937; + wire com_cmm_u_cmm_errman_ftl_cntr_un14_reg_cnt_cry_2_4938; + wire com_cmm_u_cmm_errman_ftl_cntr_un14_reg_cnt_cry_3_4939; + wire com_cmm_u_cmm_errman_ftl_cntr_reg_uflow_3_i_a2_0_4940; + wire com_cmm_u_cmm_errman_ftl_cntr_un14_reg_cnt_s_3_0; + wire com_cmm_u_cmm_errman_ftl_cntr_un25_reg_cnt_s_3_0; + wire com_cmm_u_cmm_errman_ftl_cntr_un14_reg_cnt_s_2_0; + wire com_cmm_u_cmm_errman_ftl_cntr_un25_reg_cnt_s_2_0; + wire com_cmm_u_cmm_errman_ftl_cntr_un14_reg_cnt_s_1_0; + wire com_cmm_u_cmm_errman_ftl_cntr_un25_reg_cnt_s_1_0; + wire com_cmm_u_cmm_errman_ftl_cntr_un14_reg_cnt_axb_0_4941; + wire com_cmm_u_cmm_errman_ftl_cntr_N_49548; + wire com_cmm_u_cmm_errman_ftl_cntr_un25_reg_cnt_axb_0_4942; + wire com_cmm_u_cmm_errman_ftl_cntr_N_22232_i; + wire com_cmm_u_cmm_errman_ftl_cntr_reg_inc_dec_b_4943; + wire com_cmm_u_cmm_errman_ftl_cntr_N_15651_i; + wire com_cmm_u_cmm_errman_ftl_cntr_reg_extra_4944; + wire com_cmm_u_cmm_errman_ftl_cntr_N_15539_i; + wire com_cmm_u_cmm_errman_ftl_cntr_N_15649_i; + wire com_cmm_u_cmm_errman_ftl_cntr_N_15647_i; + wire com_cmm_u_cmm_errman_ftl_cntr_N_15645_i; + wire com_cmm_u_cmm_errman_ftl_cntr_N_15643_i; + wire com_cmm_u_cmm_errman_ftl_cntr_N_22246_i; + wire com_cmm_u_cmm_errman_ftl_cntr_N_22244_i; + wire com_cmm_u_cmm_errman_ftl_cntr_N_22242_i; + wire com_cmm_u_cmm_errman_ftl_cntr_N_22240_i; + wire com_cmm_u_cmm_errman_ftl_cntr_un25_reg_cnt_s_4_0; + wire com_cmm_u_cmm_errman_ftl_cntr_un25_reg_cnt_cry_3_4945; + wire com_cmm_u_cmm_errman_ftl_cntr_un14_reg_cnt_axb_3_4946; + wire com_cmm_u_cmm_errman_ftl_cntr_un14_reg_cnt_axb_2_4947; + wire com_cmm_u_cmm_errman_ftl_cntr_un14_reg_cnt_axb_1_4948; + wire com_cmm_u_cmm_errman_ftl_cntr_un25_reg_cnt_axb_3_i_i_4949; + wire com_cmm_u_cmm_errman_ftl_cntr_reg_uflow_4950; + wire com_cmm_u_cmm_errman_ftl_cntr_oflow; + wire com_cmm_u_cmm_errman_ftl_cntr_un25_reg_cnt_axb_2_4951; + wire com_cmm_u_cmm_errman_ftl_cntr_N_22236_i; + wire com_cmm_u_cmm_errman_ftl_cntr_un25_reg_cnt_axb_1_4952; + wire com_cmm_u_cmm_errman_ftl_cntr_N_22234_i; + wire com_cmm_u_cmm_errman_wtd_cplt_N_50359_i_4953; + wire com_cmm_u_cmm_errman_wtd_cplt_N_48966_i_0; + wire com_cmm_u_cmm_errman_cplt_cntr_un25_reg_cnt_c1_4954; + wire com_cmm_u_cmm_errman_cplt_cntr_un25_reg_cnt_p4_4955; + wire com_cmm_u_cmm_errman_cplt_cntr_un14_reg_cnt_p4_4956; + wire com_cmm_u_cmm_errman_cplt_cntr_reg_inc_dec_b_4957; + wire com_cmm_u_cmm_errman_cplt_cntr_reg_extra_6_0_u_i_m2_0_0; + wire com_cmm_u_cmm_errman_cplt_cntr_reg_extra_4958; + wire com_cmm_u_cmm_errman_cplt_cntr_reg_uflow_3; + wire com_cmm_u_cmm_errman_cplt_cntr_reg_uflow_4959; + wire com_cmm_u_cmm_errman_cplt_cntr_un25_reg_cnt_axb3_i; + wire com_cmm_u_cmm_errman_cplt_cntr_un25_reg_cnt_axb2_i; + wire com_cmm_u_cmm_errman_cplt_cntr_un25_reg_cnt_axb1_i; + wire com_cmm_u_cmm_errman_cplt_cntr_N_22256_i; + wire com_cmm_u_cmm_errman_wtd_cplu_N_68722_i_4960; + wire com_cmm_u_cmm_errman_wtd_cplu_N_32847_i; + wire com_cmm_u_cmm_errman_cplu_cntr_un25_reg_cnt_c1_0; + wire com_cmm_u_cmm_errman_cplu_cntr_un25_reg_cnt_p4_4961; + wire com_cmm_u_cmm_errman_cplu_cntr_un14_reg_cnt_p4_4962; + wire com_cmm_u_cmm_errman_cplu_cntr_reg_uflow_3; + wire com_cmm_u_cmm_errman_cplu_cntr_reg_uflow_4963; + wire com_cmm_u_cmm_errman_cplu_cntr_reg_inc_dec_b_4964; + wire com_cmm_u_cmm_errman_cplu_cntr_reg_extra_6_0_u_i_m2_0_4965; + wire com_cmm_u_cmm_errman_cplu_cntr_reg_extra_4966; + wire com_cmm_u_cmm_errman_cplu_cntr_un25_reg_cnt_axb1_i; + wire com_cmm_u_cmm_errman_cplu_cntr_N_22271_i; + wire com_cmm_u_cmm_errman_cplu_cntr_un25_reg_cnt_axb3_i; + wire com_cmm_u_cmm_errman_cplu_cntr_un25_reg_cnt_axb2_i; + wire com_cmm_u_cmm_errman_cmt_hdr_buf_VCC_4967; + wire com_cmm_u_cmm_errman_cmt_hdr_buf_GND_4968; + wire com_cmm_u_cmm_errman_cfg_hdr_buf_GND_4969; + wire com_cmm_u_cmm_pm_GND_4970; + wire com_cmm_u_cmm_pm_N_42886; + wire com_cmm_u_cmm_pm_N_42574; + wire com_cmm_u_cmm_pm_N_49797_3; + wire com_cmm_u_cmm_pm_N_41807_i; + wire com_cmm_u_cmm_pm_N_48910_i; + wire com_cmm_u_cmm_pm_N_48889_i; + wire com_cmm_u_cmm_pm_un1_cmmt_ppm_suspend_req_n_comb_0_sqmuxa_i_0_0_4971; + wire com_cmm_u_cmm_pm_N_68064_i_1_4972; + wire com_cmm_u_cmm_pm_un1_cmml_suspend_now_n21_i_0_0_a2_0_4973; + wire com_cmm_u_cmm_pm_pme_sent13; + wire com_cmm_u_cmm_pm_N_68083_i_4974; + wire com_cmm_u_cmm_pm_st_pm_0__4975; + wire com_cmm_u_cmm_pm_N_68956_i_4976; + wire com_cmm_u_cmm_pm_st_pm_16__4977; + wire com_cmm_u_cmm_pm_N_42882; + wire com_cmm_u_cmm_pm_st_pm_14__4978; + wire com_cmm_u_cmm_pm_N_42928; + wire com_cmm_u_cmm_pm_N_9229_i; + wire com_cmm_u_cmm_pm_st_pm_10__4979; + wire com_cmm_u_cmm_pm_N_49797; + wire com_cmm_u_cmm_pm_st_pm_8__4980; + wire com_cmm_u_cmm_pm_N_69020_i_4981; + wire com_cmm_u_cmm_pm_st_pm_6__4982; + wire com_cmm_u_cmm_pm_N_68912_i_4983; + wire com_cmm_u_cmm_pm_st_pm_28__4984; + wire com_cmm_u_cmm_pm_N_68913_i_4985; + wire com_cmm_u_cmm_pm_st_pm_27__4986; + wire com_cmm_u_cmm_pm_N_68929_i_4987; + wire com_cmm_u_cmm_pm_N_68977_i_4988; + wire com_cmm_u_cmm_pm_st_pm_25__4989; + wire com_cmm_u_cmm_pm_st_pm_next_3_sqmuxa_i_i_a2_0_a2_0_a2_4990; + wire com_cmm_u_cmm_pm_st_pm_24__4991; + wire com_cmm_u_cmm_pm_st_pm_23__4992; + wire com_cmm_u_cmm_pm_N_68970_i_4993; + wire com_cmm_u_cmm_pm_N_50013; + wire com_cmm_u_cmm_pm_st_pm_21__4994; + wire com_cmm_u_cmm_pm_N_42575; + wire com_cmm_u_cmm_pm_VCC_4995; + wire com_cmm_u_cmm_pm_st_pm_19__4996; + wire com_cmm_u_cmm_pm_N_68911_i_4997; + wire com_cmm_u_cmm_pm_st_pm_18__4998; + wire com_cmm_u_cmm_pm_N_68928_i_4999; + wire com_cmm_u_cmm_pm_st_pm_17__5000; + wire com_cmm_u_cmm_pm_N_68064_i_5001; + wire com_cmm_u_cmm_pm_N_41785_i; + wire com_cmm_u_cmm_pm_N_68005_i_5002; + wire com_cmm_u_cmm_pm_N_42573_i_5003; + wire com_cmm_u_cmm_pm_N_67956_i_5004; + wire com_cmm_u_cmm_pm_st_pm_30__5005; + wire com_cmm_u_cmm_pm_N_67956_i_1_5006; + wire com_cmm_u_cmm_pm_inactivity_timer24; + wire com_cmm_u_cmm_arbiter_N_48922_i; + wire com_cmm_u_cmm_arbiter_N_42901_1; + wire com_cmm_u_cmm_arbiter_req_errman_d8_i_0_0_1_5007; + wire com_cmm_u_cmm_arbiter_N_67934_i_5008; + wire com_cmm_u_cmm_arbiter_req_errman_d8_i_0_0_3_5009; + wire com_cmm_u_cmm_arbiter_N_48890_i; + wire com_cmm_u_cmm_arbiter_N_49665; + wire com_cmm_u_cmm_arbiter_N_42902; + wire com_cmm_u_cmm_arbiter_N_42901; + wire com_cmm_u_cmm_arbiter_ns_fsm_0_i_0_0_0_32141_5010; + wire com_cmm_u_cmm_arbiter_N_49668; + wire com_cmm_u_cmm_arbiter_N_49666; + wire com_cmm_u_cmm_arbiter_N_69018_i_5011; + wire com_cmm_u_cmm_arbiter_N_31243_i; + wire com_cmm_u_cmm_arbiter_N_48959_i; + wire com_cmm_u_cmm_arbiter_N_31258_i; + wire com_cmm_u_cmm_arbiter_req_arbiter_6_i_0_1_32144_5012; + wire com_cmm_u_cmm_arbiter_N_50129; + wire com_cmm_u_cmm_arbiter_N_68969_i_5013; + wire com_cmm_u_cmm_arbiter_N_49662; + wire com_cmm_u_cmm_arbiter_N_31558_i; + wire com_cmm_u_cmm_arbiter_ns_fsm_0_sqmuxa_4; + wire com_cmm_u_cmm_arbiter_ns_fsm_0_sqmuxa_2; + wire com_cmm_u_cmm_arbiter_ns_fsm_0_sqmuxa; + wire com_cmm_u_cmm_arbiter_N_31275_i; + wire com_cmm_u_cmm_arbiter_N_68065_i_5014; + wire com_cmm_u_cmm_arbiter_N_67938_i_5015; + wire com_cmm_u_cmm_arbiter_N_8978_i; + wire com_cmm_u_cmm_arbiter_ns_fsm_0_0_0_0_2_32149_5016; + wire com_cmm_u_cmm_arbiter_N_49490; + wire com_cmm_u_cmm_arbiter_N_31260_i; + wire com_cmm_u_cmm_arbiter_N_42044_i; + wire com_cmm_u_cmm_dataproducer_N_9377_i; + wire com_cmm_u_cmm_dataproducer_N_50468_2; + wire com_cmm_u_cmm_dataproducer_N_50468_1; + wire com_cmm_u_cmm_dataproducer_N_50482; + wire com_cmm_u_cmm_dataproducer_N_49561; + wire com_cmm_u_cmm_dataproducer_N_50006; + wire com_cmm_u_cmm_dataproducer_N_49551; + wire com_cmm_u_cmm_dataproducer_N_49550; + wire com_cmm_u_cmm_dataproducer_N_48950_i; + wire com_cmm_u_cmm_dataproducer_N_49269; + wire com_cmm_u_cmm_dataproducer_N_49267; + wire com_cmm_u_cmm_dataproducer_N_49265; + wire com_cmm_u_cmm_dataproducer_N_49264; + wire com_cmm_u_cmm_dataproducer_N_49263; + wire com_cmm_u_cmm_dataproducer_N_49261; + wire com_cmm_u_cmm_dataproducer_N_49260; + wire com_cmm_u_cmm_dataproducer_N_49258; + wire com_cmm_u_cmm_dataproducer_N_49257; + wire com_cmm_u_cmm_dataproducer_N_49255; + wire com_cmm_u_cmm_dataproducer_N_49254; + wire com_cmm_u_cmm_dataproducer_N_49252; + wire com_cmm_u_cmm_dataproducer_N_49250; + wire com_cmm_u_cmm_dataproducer_N_49249; + wire com_cmm_u_cmm_dataproducer_N_49248; + wire com_cmm_u_cmm_dataproducer_N_49246; + wire com_cmm_u_cmm_dataproducer_N_49245; + wire com_cmm_u_cmm_dataproducer_N_49243; + wire com_cmm_u_cmm_dataproducer_N_49242; + wire com_cmm_u_cmm_dataproducer_N_49240; + wire com_cmm_u_cmm_dataproducer_N_49560; + wire com_cmm_u_cmm_dataproducer_N_50011; + wire com_cmm_u_cmm_dataproducer_N_49678; + wire com_cmm_u_cmm_dataproducer_N_49677; + wire com_cmm_u_cmm_dataproducer_N_49304; + wire com_cmm_u_cmm_dataproducer_N_49303; + wire com_cmm_u_cmm_dataproducer_N_49301; + wire com_cmm_u_cmm_dataproducer_N_49300; + wire com_cmm_u_cmm_dataproducer_N_49298; + wire com_cmm_u_cmm_dataproducer_N_49297; + wire com_cmm_u_cmm_dataproducer_N_49681; + wire com_cmm_u_cmm_dataproducer_N_49680; + wire com_cmm_u_cmm_dataproducer_N_49295; + wire com_cmm_u_cmm_dataproducer_N_49294; + wire com_cmm_u_cmm_dataproducer_N_49292; + wire com_cmm_u_cmm_dataproducer_N_49291; + wire com_cmm_u_cmm_dataproducer_N_49289; + wire com_cmm_u_cmm_dataproducer_N_49288; + wire com_cmm_u_cmm_dataproducer_N_49287; + wire com_cmm_u_cmm_dataproducer_N_49285; + wire com_cmm_u_cmm_dataproducer_N_49284; + wire com_cmm_u_cmm_dataproducer_N_49282; + wire com_cmm_u_cmm_dataproducer_N_49281; + wire com_cmm_u_cmm_dataproducer_N_49279; + wire com_cmm_u_cmm_dataproducer_N_49278; + wire com_cmm_u_cmm_dataproducer_N_49276; + wire com_cmm_u_cmm_dataproducer_N_49275; + wire com_cmm_u_cmm_dataproducer_N_49273; + wire com_cmm_u_cmm_dataproducer_N_50481; + wire com_cmm_u_cmm_dataproducer_N_49272; + wire com_cmm_u_cmm_dataproducer_N_49270; + wire com_cmm_u_cmm_dataproducer_N_50468_3; + wire com_cmm_u_cmm_dataproducer_N_50009; + wire com_cmm_u_cmm_dataproducer_N_50007; + wire com_cmm_u_cmm_dataproducer_N_48969_i; + wire com_cmm_u_cmm_dataproducer_N_48879_i; + wire com_cmm_u_cmm_dataproducer_N_50471; + wire com_cmm_u_cmm_dataproducer_N_14861_i; + wire com_cmm_u_cmm_dataproducer_N_14859_i; + wire com_cmm_u_cmm_dataproducer_N_14857_i; + wire com_cmm_u_cmm_dataproducer_N_14855_i; + wire com_cmm_u_cmm_dataproducer_N_14865_i; + wire com_cmm_u_cmm_dataproducer_N_49542; + wire com_cmm_u_cmm_dataproducer_N_48988_i; + wire com_cmm_u_cmm_dataproducer_nxt_req_gnt_state38; + wire com_cmm_u_cmm_dataproducer_N_68506_i_5017; + wire com_cmm_u_cmm_dataproducer_N_49557_i_5018; + wire com_cmm_u_cmm_dataproducer_byte_06_21_7_; + wire com_cmm_u_cmm_dataproducer_N_68167_i_5019; + wire com_cmm_u_cmm_dataproducer_N_68156_i_5020; + wire com_cmm_u_cmm_dataproducer_N_68155_i_5021; + wire com_cmm_u_cmm_dataproducer_N_68125_i_5022; + wire com_cmm_u_cmm_dataproducer_N_68124_i_5023; + wire com_cmm_u_cmm_dataproducer_N_68123_i_5024; + wire com_cmm_u_cmm_dataproducer_N_68122_i_5025; + wire com_cmm_u_cmm_dataproducer_N_68121_i_5026; + wire com_cmm_u_cmm_dataproducer_N_68120_i_5027; + wire com_cmm_u_cmm_dataproducer_N_68119_i_5028; + wire com_cmm_u_cmm_dataproducer_N_68118_i_5029; + wire com_cmm_u_cmm_dataproducer_N_68117_i_5030; + wire com_cmm_u_cmm_dataproducer_N_68116_i_5031; + wire com_cmm_u_cmm_dataproducer_N_68158_i_5032; + wire com_cmm_u_cmm_dataproducer_N_68561_i_5033; + wire com_cmm_u_cmm_dataproducer_N_68168_i_5034; + wire com_cmm_u_cmm_dataproducer_N_68164_i_5035; + wire com_cmm_u_cmm_dataproducer_N_68137_i_5036; + wire com_cmm_u_cmm_dataproducer_N_68136_i_5037; + wire com_cmm_u_cmm_dataproducer_N_68135_i_5038; + wire com_cmm_u_cmm_dataproducer_N_68165_i_5039; + wire com_cmm_u_cmm_dataproducer_N_68134_i_5040; + wire com_cmm_u_cmm_dataproducer_N_68133_i_5041; + wire com_cmm_u_cmm_dataproducer_N_68132_i_5042; + wire com_cmm_u_cmm_dataproducer_N_68131_i_5043; + wire com_cmm_u_cmm_dataproducer_N_68130_i_5044; + wire com_cmm_u_cmm_dataproducer_N_68129_i_5045; + wire com_cmm_u_cmm_dataproducer_N_68128_i_5046; + wire com_cmm_u_cmm_dataproducer_N_68127_i_5047; + wire com_cmm_u_cmm_dataproducer_N_68126_i_5048; + wire com_cmm_u_cmm_dataproducer_N_16336_i; + wire com_cmm_u_cmm_dataproducer_N_16334_i; + wire com_cmm_u_cmm_dataproducer_N_16332_i; + wire com_cmm_u_cmm_dataproducer_N_48188_i; + wire com_cmm_u_cmm_dataproducer_N_48186_i; + wire com_cmm_u_cmm_dataproducer_N_48184_i; + wire com_cmm_u_cmm_dataproducer_N_68623_i; + wire com_cmm_u_cmm_dataproducer_N_68507_i_5049; + wire com_cmm_u_cmm_dataproducer_N_3727_i_0_a2_0_a3_i_0_i_a3_5050; + wire com_cmm_u_cmm_dataproducer_N_68429_i_5051; + wire com_cmm_u_cmm_dataproducer_N_68428_i_5052; + wire com_cmm_u_cmm_dataproducer_N_16356_i; + wire com_cmm_u_cmm_dataproducer_N_16354_i; + wire com_cmm_u_cmm_dataproducer_N_16352_i; + wire com_cmm_u_cmm_dataproducer_N_16350_i; + wire com_cmm_u_cmm_dataproducer_N_16348_i; + wire com_cmm_u_cmm_dataproducer_N_16346_i; + wire com_cmm_u_cmm_dataproducer_N_16344_i; + wire com_cmm_u_cmm_dataproducer_N_16342_i; + wire com_cmm_u_cmm_dataproducer_N_16340_i; + wire com_cmm_u_cmm_dataproducer_N_16338_i; + wire com_cmm_u_cmm_dataproducer_byte_06_21_3_; + wire com_cmm_u_cmm_dataproducer_byte_06_21_2_; + wire com_cmm_u_cmm_dataproducer_byte_06_21_1_; + wire com_cmm_u_cmm_dataproducer_byte_06_21_0_; + wire com_cmm_u_cmm_dataproducer_N_14863_i; + wire NLW_plm_v4f_mgt_dcm_CLK90_UNCONNECTED; + wire NLW_plm_v4f_mgt_dcm_CLKFX_UNCONNECTED; + wire NLW_plm_v4f_mgt_dcm_CLK2X_UNCONNECTED; + wire NLW_plm_v4f_mgt_dcm_DO_15__UNCONNECTED; + wire NLW_plm_v4f_mgt_dcm_DO_14__UNCONNECTED; + wire NLW_plm_v4f_mgt_dcm_DO_13__UNCONNECTED; + wire NLW_plm_v4f_mgt_dcm_DO_12__UNCONNECTED; + wire NLW_plm_v4f_mgt_dcm_DO_11__UNCONNECTED; + wire NLW_plm_v4f_mgt_dcm_DO_10__UNCONNECTED; + wire NLW_plm_v4f_mgt_dcm_DO_9__UNCONNECTED; + wire NLW_plm_v4f_mgt_dcm_DO_8__UNCONNECTED; + wire NLW_plm_v4f_mgt_dcm_DO_7__UNCONNECTED; + wire NLW_plm_v4f_mgt_dcm_DO_6__UNCONNECTED; + wire NLW_plm_v4f_mgt_dcm_DO_5__UNCONNECTED; + wire NLW_plm_v4f_mgt_dcm_DO_4__UNCONNECTED; + wire NLW_plm_v4f_mgt_dcm_DO_3__UNCONNECTED; + wire NLW_plm_v4f_mgt_dcm_DO_2__UNCONNECTED; + wire NLW_plm_v4f_mgt_dcm_DO_1__UNCONNECTED; + wire NLW_plm_v4f_mgt_dcm_DO_0__UNCONNECTED; + wire NLW_plm_v4f_mgt_dcm_PSDONE_UNCONNECTED; + wire NLW_plm_v4f_mgt_dcm_CLKFX180_UNCONNECTED; + wire NLW_plm_v4f_mgt_dcm_CLK180_UNCONNECTED; + wire NLW_plm_v4f_mgt_dcm_CLK2X180_UNCONNECTED; + wire NLW_plm_v4f_mgt_dcm_CLK270_UNCONNECTED; + wire NLW_plm_v4f_mgt_dcm_DRDY_UNCONNECTED; + wire NLW_plm_v4f_mgt_reg_tee_dlyline_I_2_Q15_UNCONNECTED; + wire NLW_plm_v4f_mgt_reg_tee_dlyline_I_1_Q_UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST_RXBUFERR_UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST_RXSTATUS_5__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST_RXSTATUS_4__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST_RXSTATUS_3__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST_RXSTATUS_2__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST_RXSTATUS_1__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST_RXSTATUS_0__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST_RXNOTINTABLE_7__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST_RXNOTINTABLE_6__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST_RXNOTINTABLE_5__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST_RXNOTINTABLE_4__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST_RXNOTINTABLE_3__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST_RXNOTINTABLE_2__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST_RXCRCOUT_31__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST_RXCRCOUT_30__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST_RXCRCOUT_29__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST_RXCRCOUT_28__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST_RXCRCOUT_27__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST_RXCRCOUT_26__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST_RXCRCOUT_25__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST_RXCRCOUT_24__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST_RXCRCOUT_23__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST_RXCRCOUT_22__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST_RXCRCOUT_21__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST_RXCRCOUT_20__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST_RXCRCOUT_19__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST_RXCRCOUT_18__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST_RXCRCOUT_17__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST_RXCRCOUT_16__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST_RXCRCOUT_15__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST_RXCRCOUT_14__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST_RXCRCOUT_13__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST_RXCRCOUT_12__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST_RXCRCOUT_11__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST_RXCRCOUT_10__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST_RXCRCOUT_9__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST_RXCRCOUT_8__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST_RXCRCOUT_7__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST_RXCRCOUT_6__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST_RXCRCOUT_5__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST_RXCRCOUT_4__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST_RXCRCOUT_3__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST_RXCRCOUT_2__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST_RXCRCOUT_1__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST_RXCRCOUT_0__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST_TXBUFERR_UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST_RXREALIGN_UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST_TXCRCOUT_31__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST_TXCRCOUT_30__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST_TXCRCOUT_29__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST_TXCRCOUT_28__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST_TXCRCOUT_27__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST_TXCRCOUT_26__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST_TXCRCOUT_25__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST_TXCRCOUT_24__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST_TXCRCOUT_23__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST_TXCRCOUT_22__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST_TXCRCOUT_21__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST_TXCRCOUT_20__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST_TXCRCOUT_19__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST_TXCRCOUT_18__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST_TXCRCOUT_17__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST_TXCRCOUT_16__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST_TXCRCOUT_15__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST_TXCRCOUT_14__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST_TXCRCOUT_13__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST_TXCRCOUT_12__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST_TXCRCOUT_11__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST_TXCRCOUT_10__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST_TXCRCOUT_9__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST_TXCRCOUT_8__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST_TXCRCOUT_7__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST_TXCRCOUT_6__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST_TXCRCOUT_5__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST_TXCRCOUT_4__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST_TXCRCOUT_3__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST_TXCRCOUT_2__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST_TXCRCOUT_1__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST_TXCRCOUT_0__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST_RXCYCLELIMIT_UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST_TXCYCLELIMIT_UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST_TXCALFAIL_UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST_RXPCSHCLKOUT_UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST_TXPCSHCLKOUT_UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST_RXDATA_63__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST_RXDATA_62__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST_RXDATA_61__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST_RXDATA_60__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST_RXDATA_59__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST_RXDATA_58__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST_RXDATA_57__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST_RXDATA_56__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST_RXDATA_55__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST_RXDATA_54__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST_RXDATA_53__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST_RXDATA_52__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST_RXDATA_51__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST_RXDATA_50__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST_RXDATA_49__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST_RXDATA_48__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST_RXDATA_47__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST_RXDATA_46__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST_RXDATA_45__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST_RXDATA_44__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST_RXDATA_43__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST_RXDATA_42__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST_RXDATA_41__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST_RXDATA_40__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST_RXDATA_39__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST_RXDATA_38__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST_RXDATA_37__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST_RXDATA_36__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST_RXDATA_35__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST_RXDATA_34__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST_RXDATA_33__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST_RXDATA_32__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST_RXDATA_31__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST_RXDATA_30__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST_RXDATA_29__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST_RXDATA_28__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST_RXDATA_27__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST_RXDATA_26__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST_RXDATA_25__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST_RXDATA_24__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST_RXDATA_23__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST_RXDATA_22__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST_RXDATA_21__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST_RXDATA_20__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST_RXDATA_19__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST_RXDATA_18__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST_RXDATA_17__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST_RXDATA_16__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST_TXRUNDISP_7__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST_TXRUNDISP_6__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST_TXRUNDISP_5__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST_TXRUNDISP_4__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST_TXRUNDISP_3__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST_TXRUNDISP_2__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST_TXRUNDISP_1__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST_TXRUNDISP_0__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST_RXCALFAIL_UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST_RXLOSSOFSYNC_1__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST_RXLOSSOFSYNC_0__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST_RXRUNDISP_7__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST_RXRUNDISP_6__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST_RXRUNDISP_5__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST_RXRUNDISP_4__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST_RXRUNDISP_3__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST_RXRUNDISP_2__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST_RXMCLK_UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST_CHBONDO_4__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST_CHBONDO_3__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST_CHBONDO_2__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST_CHBONDO_1__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST_CHBONDO_0__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST_RXCOMMADET_UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST_TXOUTCLK1_UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST_TXOUTCLK2_UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST_RXRECCLK1_UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST_RXRECCLK2_UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST_RXCHARISK_7__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST_RXCHARISK_6__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST_RXCHARISK_5__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST_RXCHARISK_4__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST_RXCHARISK_3__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST_RXCHARISK_2__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST_RXDISPERR_7__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST_RXDISPERR_6__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST_RXDISPERR_5__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST_RXDISPERR_4__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST_RXDISPERR_3__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST_RXDISPERR_2__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST_RXCHARISCOMMA_7__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST_RXCHARISCOMMA_6__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST_RXCHARISCOMMA_5__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST_RXCHARISCOMMA_4__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST_RXCHARISCOMMA_3__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST_RXCHARISCOMMA_2__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST_RXCHARISCOMMA_1__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST_RXCHARISCOMMA_0__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST_TXKERR_7__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST_TXKERR_6__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST_TXKERR_5__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST_TXKERR_4__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST_TXKERR_3__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST_TXKERR_2__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST_TXKERR_1__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST_TXKERR_0__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2_RXBUFERR_UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2_RXSTATUS_5__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2_RXSTATUS_4__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2_RXSTATUS_3__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2_RXSTATUS_2__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2_RXSTATUS_1__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2_RXSTATUS_0__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2_RXNOTINTABLE_7__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2_RXNOTINTABLE_6__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2_RXNOTINTABLE_5__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2_RXNOTINTABLE_4__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2_RXNOTINTABLE_3__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2_RXNOTINTABLE_2__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2_RXNOTINTABLE_1__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2_RXNOTINTABLE_0__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2_RXCRCOUT_31__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2_RXCRCOUT_30__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2_RXCRCOUT_29__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2_RXCRCOUT_28__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2_RXCRCOUT_27__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2_RXCRCOUT_26__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2_RXCRCOUT_25__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2_RXCRCOUT_24__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2_RXCRCOUT_23__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2_RXCRCOUT_22__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2_RXCRCOUT_21__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2_RXCRCOUT_20__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2_RXCRCOUT_19__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2_RXCRCOUT_18__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2_RXCRCOUT_17__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2_RXCRCOUT_16__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2_RXCRCOUT_15__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2_RXCRCOUT_14__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2_RXCRCOUT_13__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2_RXCRCOUT_12__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2_RXCRCOUT_11__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2_RXCRCOUT_10__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2_RXCRCOUT_9__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2_RXCRCOUT_8__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2_RXCRCOUT_7__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2_RXCRCOUT_6__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2_RXCRCOUT_5__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2_RXCRCOUT_4__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2_RXCRCOUT_3__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2_RXCRCOUT_2__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2_RXCRCOUT_1__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2_RXCRCOUT_0__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2_TXBUFERR_UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2_RXSIGDET_UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2_RXREALIGN_UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2_TXCRCOUT_31__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2_TXCRCOUT_30__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2_TXCRCOUT_29__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2_TXCRCOUT_28__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2_TXCRCOUT_27__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2_TXCRCOUT_26__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2_TXCRCOUT_25__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2_TXCRCOUT_24__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2_TXCRCOUT_23__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2_TXCRCOUT_22__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2_TXCRCOUT_21__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2_TXCRCOUT_20__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2_TXCRCOUT_19__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2_TXCRCOUT_18__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2_TXCRCOUT_17__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2_TXCRCOUT_16__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2_TXCRCOUT_15__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2_TXCRCOUT_14__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2_TXCRCOUT_13__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2_TXCRCOUT_12__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2_TXCRCOUT_11__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2_TXCRCOUT_10__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2_TXCRCOUT_9__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2_TXCRCOUT_8__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2_TXCRCOUT_7__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2_TXCRCOUT_6__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2_TXCRCOUT_5__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2_TXCRCOUT_4__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2_TXCRCOUT_3__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2_TXCRCOUT_2__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2_TXCRCOUT_1__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2_TXCRCOUT_0__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2_RXCYCLELIMIT_UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2_TXCYCLELIMIT_UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2_TXCALFAIL_UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2_RXPCSHCLKOUT_UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2_TXPCSHCLKOUT_UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2_RXDATA_63__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2_RXDATA_62__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2_RXDATA_61__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2_RXDATA_60__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2_RXDATA_59__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2_RXDATA_58__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2_RXDATA_57__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2_RXDATA_56__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2_RXDATA_55__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2_RXDATA_54__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2_RXDATA_53__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2_RXDATA_52__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2_RXDATA_51__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2_RXDATA_50__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2_RXDATA_49__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2_RXDATA_48__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2_RXDATA_47__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2_RXDATA_46__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2_RXDATA_45__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2_RXDATA_44__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2_RXDATA_43__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2_RXDATA_42__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2_RXDATA_41__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2_RXDATA_40__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2_RXDATA_39__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2_RXDATA_38__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2_RXDATA_37__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2_RXDATA_36__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2_RXDATA_35__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2_RXDATA_34__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2_RXDATA_33__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2_RXDATA_32__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2_RXDATA_31__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2_RXDATA_30__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2_RXDATA_29__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2_RXDATA_28__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2_RXDATA_27__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2_RXDATA_26__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2_RXDATA_25__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2_RXDATA_24__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2_RXDATA_23__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2_RXDATA_22__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2_RXDATA_21__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2_RXDATA_20__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2_RXDATA_19__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2_RXDATA_18__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2_RXDATA_17__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2_RXDATA_16__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2_RXDATA_15__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2_RXDATA_14__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2_RXDATA_13__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2_RXDATA_12__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2_RXDATA_11__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2_RXDATA_10__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2_RXDATA_9__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2_RXDATA_8__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2_RXDATA_7__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2_RXDATA_6__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2_RXDATA_5__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2_RXDATA_4__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2_RXDATA_3__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2_RXDATA_2__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2_RXDATA_1__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2_RXDATA_0__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2_TXRUNDISP_7__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2_TXRUNDISP_6__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2_TXRUNDISP_5__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2_TXRUNDISP_4__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2_TXRUNDISP_3__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2_TXRUNDISP_2__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2_TXRUNDISP_1__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2_TXRUNDISP_0__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2_RXCALFAIL_UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2_RXLOSSOFSYNC_1__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2_RXLOSSOFSYNC_0__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2_RXRUNDISP_7__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2_RXRUNDISP_6__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2_RXRUNDISP_5__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2_RXRUNDISP_4__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2_RXRUNDISP_3__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2_RXRUNDISP_2__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2_RXRUNDISP_1__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2_RXRUNDISP_0__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2_RXLOCK_UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2_RXMCLK_UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2_CHBONDO_4__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2_CHBONDO_3__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2_CHBONDO_2__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2_CHBONDO_1__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2_CHBONDO_0__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2_RXCOMMADET_UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2_TXOUTCLK1_UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2_TXOUTCLK2_UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2_RXRECCLK1_UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2_RXRECCLK2_UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2_TXLOCK_UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2_RXCHARISK_7__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2_RXCHARISK_6__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2_RXCHARISK_5__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2_RXCHARISK_4__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2_RXCHARISK_3__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2_RXCHARISK_2__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2_RXCHARISK_1__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2_RXCHARISK_0__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2_RXDISPERR_7__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2_RXDISPERR_6__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2_RXDISPERR_5__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2_RXDISPERR_4__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2_RXDISPERR_3__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2_RXDISPERR_2__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2_RXDISPERR_1__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2_RXDISPERR_0__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2_RXCHARISCOMMA_7__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2_RXCHARISCOMMA_6__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2_RXCHARISCOMMA_5__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2_RXCHARISCOMMA_4__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2_RXCHARISCOMMA_3__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2_RXCHARISCOMMA_2__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2_RXCHARISCOMMA_1__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2_RXCHARISCOMMA_0__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2_TX1N_UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2_TX1P_UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2_TXKERR_7__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2_TXKERR_6__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2_TXKERR_5__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2_TXKERR_4__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2_TXKERR_3__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2_TXKERR_2__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2_TXKERR_1__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2_TXKERR_0__UNCONNECTED; + wire NLW_plm_dfm_deframe1_dwbuf_L0S0_SPO_UNCONNECTED; + wire NLW_plm_dfm_deframe1_dwbuf_L0S1_SPO_UNCONNECTED; + wire NLW_plm_dfm_deframe1_dwbuf_L0B0_SPO_UNCONNECTED; + wire NLW_plm_dfm_deframe1_dwbuf_L0B1_SPO_UNCONNECTED; + wire NLW_plm_dfm_deframe1_dwbuf_L0B2_SPO_UNCONNECTED; + wire NLW_plm_dfm_deframe1_dwbuf_L0B3_SPO_UNCONNECTED; + wire NLW_plm_dfm_deframe1_dwbuf_L0B4_SPO_UNCONNECTED; + wire NLW_plm_dfm_deframe1_dwbuf_L0B5_SPO_UNCONNECTED; + wire NLW_plm_dfm_deframe1_dwbuf_L0B6_SPO_UNCONNECTED; + wire NLW_plm_dfm_deframe1_dwbuf_L0B7_SPO_UNCONNECTED; + wire NLW_plm_dfm_deframe1_dwbuf_L1B0_SPO_UNCONNECTED; + wire NLW_plm_dfm_deframe1_dwbuf_L1B1_SPO_UNCONNECTED; + wire NLW_plm_dfm_deframe1_dwbuf_L1B2_SPO_UNCONNECTED; + wire NLW_plm_dfm_deframe1_dwbuf_L1B3_SPO_UNCONNECTED; + wire NLW_plm_dfm_deframe1_dwbuf_L1B4_SPO_UNCONNECTED; + wire NLW_plm_dfm_deframe1_dwbuf_L1B5_SPO_UNCONNECTED; + wire NLW_plm_dfm_deframe1_dwbuf_L1B6_SPO_UNCONNECTED; + wire NLW_plm_dfm_deframe1_dwbuf_L1B7_SPO_UNCONNECTED; + wire NLW_plm_dfm_deframe1_dwbuf_L2B0_SPO_UNCONNECTED; + wire NLW_plm_dfm_deframe1_dwbuf_L2B1_SPO_UNCONNECTED; + wire NLW_plm_dfm_deframe1_dwbuf_L2B2_SPO_UNCONNECTED; + wire NLW_plm_dfm_deframe1_dwbuf_L2B3_SPO_UNCONNECTED; + wire NLW_plm_dfm_deframe1_dwbuf_L2B4_SPO_UNCONNECTED; + wire NLW_plm_dfm_deframe1_dwbuf_L2B5_SPO_UNCONNECTED; + wire NLW_plm_dfm_deframe1_dwbuf_L2B6_SPO_UNCONNECTED; + wire NLW_plm_dfm_deframe1_dwbuf_L2B7_SPO_UNCONNECTED; + wire NLW_plm_dfm_deframe1_dwbuf_L3B0_SPO_UNCONNECTED; + wire NLW_plm_dfm_deframe1_dwbuf_L3B1_SPO_UNCONNECTED; + wire NLW_plm_dfm_deframe1_dwbuf_L3B2_SPO_UNCONNECTED; + wire NLW_plm_dfm_deframe1_dwbuf_L3B3_SPO_UNCONNECTED; + wire NLW_plm_dfm_deframe1_dwbuf_L3B4_SPO_UNCONNECTED; + wire NLW_plm_dfm_deframe1_dwbuf_L3B5_SPO_UNCONNECTED; + wire NLW_plm_dfm_deframe1_dwbuf_L3B6_SPO_UNCONNECTED; + wire NLW_plm_dfm_deframe1_dwbuf_L3B7_SPO_UNCONNECTED; + wire NLW_plm_dfm_deframe1_dwbuf_L3S0_SPO_UNCONNECTED; + wire NLW_plm_dfm_deframe1_dwbuf_L3S1_SPO_UNCONNECTED; + wire NLW_com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_srlrow_0__srlcol_0__srlinst_Q15_UNCONNECTED; + wire NLW_com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_srlrow_0__srlcol_3__srlinst_Q15_UNCONNECTED; + wire NLW_com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_srlrow_0__srlcol_2__srlinst_Q15_UNCONNECTED; + wire NLW_com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_srlrow_0__srlcol_1__srlinst_Q15_UNCONNECTED; + wire NLW_com_tlm_u_tlm_tx_vc0_buf_pool_errfwd_0_I_1_SPO_UNCONNECTED; + wire NLW_com_tlm_u_tlm_tx_vc0_buf_pool_bram_0__size8_bram_array_ram_row_0__block_ram_0__ram2048x9_bram_DOPA_0__UNCONNECTED; + wire NLW_com_tlm_u_tlm_tx_vc0_buf_pool_bram_0__size8_bram_array_ram_row_0__block_ram_0__ram2048x9_bram_DOA_7__UNCONNECTED; + wire NLW_com_tlm_u_tlm_tx_vc0_buf_pool_bram_0__size8_bram_array_ram_row_0__block_ram_0__ram2048x9_bram_DOA_6__UNCONNECTED; + wire NLW_com_tlm_u_tlm_tx_vc0_buf_pool_bram_0__size8_bram_array_ram_row_0__block_ram_0__ram2048x9_bram_DOA_5__UNCONNECTED; + wire NLW_com_tlm_u_tlm_tx_vc0_buf_pool_bram_0__size8_bram_array_ram_row_0__block_ram_0__ram2048x9_bram_DOA_4__UNCONNECTED; + wire NLW_com_tlm_u_tlm_tx_vc0_buf_pool_bram_0__size8_bram_array_ram_row_0__block_ram_0__ram2048x9_bram_DOA_3__UNCONNECTED; + wire NLW_com_tlm_u_tlm_tx_vc0_buf_pool_bram_0__size8_bram_array_ram_row_0__block_ram_0__ram2048x9_bram_DOA_2__UNCONNECTED; + wire NLW_com_tlm_u_tlm_tx_vc0_buf_pool_bram_0__size8_bram_array_ram_row_0__block_ram_0__ram2048x9_bram_DOA_1__UNCONNECTED; + wire NLW_com_tlm_u_tlm_tx_vc0_buf_pool_bram_0__size8_bram_array_ram_row_0__block_ram_0__ram2048x9_bram_DOA_0__UNCONNECTED; + wire NLW_com_tlm_u_tlm_tx_vc0_buf_pool_bram_0__size8_bram_array_ram_row_0__block_ram_1__ram2048x9_bram_DOPA_0__UNCONNECTED; + wire NLW_com_tlm_u_tlm_tx_vc0_buf_pool_bram_0__size8_bram_array_ram_row_0__block_ram_1__ram2048x9_bram_DOA_7__UNCONNECTED; + wire NLW_com_tlm_u_tlm_tx_vc0_buf_pool_bram_0__size8_bram_array_ram_row_0__block_ram_1__ram2048x9_bram_DOA_6__UNCONNECTED; + wire NLW_com_tlm_u_tlm_tx_vc0_buf_pool_bram_0__size8_bram_array_ram_row_0__block_ram_1__ram2048x9_bram_DOA_5__UNCONNECTED; + wire NLW_com_tlm_u_tlm_tx_vc0_buf_pool_bram_0__size8_bram_array_ram_row_0__block_ram_1__ram2048x9_bram_DOA_4__UNCONNECTED; + wire NLW_com_tlm_u_tlm_tx_vc0_buf_pool_bram_0__size8_bram_array_ram_row_0__block_ram_1__ram2048x9_bram_DOA_3__UNCONNECTED; + wire NLW_com_tlm_u_tlm_tx_vc0_buf_pool_bram_0__size8_bram_array_ram_row_0__block_ram_1__ram2048x9_bram_DOA_2__UNCONNECTED; + wire NLW_com_tlm_u_tlm_tx_vc0_buf_pool_bram_0__size8_bram_array_ram_row_0__block_ram_1__ram2048x9_bram_DOA_1__UNCONNECTED; + wire NLW_com_tlm_u_tlm_tx_vc0_buf_pool_bram_0__size8_bram_array_ram_row_0__block_ram_1__ram2048x9_bram_DOA_0__UNCONNECTED; + wire NLW_com_tlm_u_tlm_tx_vc0_buf_pool_bram_0__size8_bram_array_ram_row_0__block_ram_3__ram2048x9_bram_DOPA_0__UNCONNECTED; + wire NLW_com_tlm_u_tlm_tx_vc0_buf_pool_bram_0__size8_bram_array_ram_row_0__block_ram_3__ram2048x9_bram_DOA_7__UNCONNECTED; + wire NLW_com_tlm_u_tlm_tx_vc0_buf_pool_bram_0__size8_bram_array_ram_row_0__block_ram_3__ram2048x9_bram_DOA_6__UNCONNECTED; + wire NLW_com_tlm_u_tlm_tx_vc0_buf_pool_bram_0__size8_bram_array_ram_row_0__block_ram_3__ram2048x9_bram_DOA_5__UNCONNECTED; + wire NLW_com_tlm_u_tlm_tx_vc0_buf_pool_bram_0__size8_bram_array_ram_row_0__block_ram_3__ram2048x9_bram_DOA_4__UNCONNECTED; + wire NLW_com_tlm_u_tlm_tx_vc0_buf_pool_bram_0__size8_bram_array_ram_row_0__block_ram_3__ram2048x9_bram_DOA_3__UNCONNECTED; + wire NLW_com_tlm_u_tlm_tx_vc0_buf_pool_bram_0__size8_bram_array_ram_row_0__block_ram_3__ram2048x9_bram_DOA_2__UNCONNECTED; + wire NLW_com_tlm_u_tlm_tx_vc0_buf_pool_bram_0__size8_bram_array_ram_row_0__block_ram_3__ram2048x9_bram_DOA_1__UNCONNECTED; + wire NLW_com_tlm_u_tlm_tx_vc0_buf_pool_bram_0__size8_bram_array_ram_row_0__block_ram_3__ram2048x9_bram_DOA_0__UNCONNECTED; + wire NLW_com_tlm_u_tlm_tx_vc0_buf_pool_bram_0__size8_bram_array_ram_row_0__block_ram_4__ram2048x9_bram_DOPA_0__UNCONNECTED; + wire NLW_com_tlm_u_tlm_tx_vc0_buf_pool_bram_0__size8_bram_array_ram_row_0__block_ram_4__ram2048x9_bram_DOA_7__UNCONNECTED; + wire NLW_com_tlm_u_tlm_tx_vc0_buf_pool_bram_0__size8_bram_array_ram_row_0__block_ram_4__ram2048x9_bram_DOA_6__UNCONNECTED; + wire NLW_com_tlm_u_tlm_tx_vc0_buf_pool_bram_0__size8_bram_array_ram_row_0__block_ram_4__ram2048x9_bram_DOA_5__UNCONNECTED; + wire NLW_com_tlm_u_tlm_tx_vc0_buf_pool_bram_0__size8_bram_array_ram_row_0__block_ram_4__ram2048x9_bram_DOA_4__UNCONNECTED; + wire NLW_com_tlm_u_tlm_tx_vc0_buf_pool_bram_0__size8_bram_array_ram_row_0__block_ram_4__ram2048x9_bram_DOA_3__UNCONNECTED; + wire NLW_com_tlm_u_tlm_tx_vc0_buf_pool_bram_0__size8_bram_array_ram_row_0__block_ram_4__ram2048x9_bram_DOA_2__UNCONNECTED; + wire NLW_com_tlm_u_tlm_tx_vc0_buf_pool_bram_0__size8_bram_array_ram_row_0__block_ram_4__ram2048x9_bram_DOA_1__UNCONNECTED; + wire NLW_com_tlm_u_tlm_tx_vc0_buf_pool_bram_0__size8_bram_array_ram_row_0__block_ram_4__ram2048x9_bram_DOA_0__UNCONNECTED; + wire NLW_com_tlm_u_tlm_tx_vc0_buf_pool_bram_0__size8_bram_array_ram_row_0__block_ram_6__ram2048x9_bram_DOPA_0__UNCONNECTED; + wire NLW_com_tlm_u_tlm_tx_vc0_buf_pool_bram_0__size8_bram_array_ram_row_0__block_ram_6__ram2048x9_bram_DOA_7__UNCONNECTED; + wire NLW_com_tlm_u_tlm_tx_vc0_buf_pool_bram_0__size8_bram_array_ram_row_0__block_ram_6__ram2048x9_bram_DOA_6__UNCONNECTED; + wire NLW_com_tlm_u_tlm_tx_vc0_buf_pool_bram_0__size8_bram_array_ram_row_0__block_ram_6__ram2048x9_bram_DOA_5__UNCONNECTED; + wire NLW_com_tlm_u_tlm_tx_vc0_buf_pool_bram_0__size8_bram_array_ram_row_0__block_ram_6__ram2048x9_bram_DOA_4__UNCONNECTED; + wire NLW_com_tlm_u_tlm_tx_vc0_buf_pool_bram_0__size8_bram_array_ram_row_0__block_ram_6__ram2048x9_bram_DOA_3__UNCONNECTED; + wire NLW_com_tlm_u_tlm_tx_vc0_buf_pool_bram_0__size8_bram_array_ram_row_0__block_ram_6__ram2048x9_bram_DOA_2__UNCONNECTED; + wire NLW_com_tlm_u_tlm_tx_vc0_buf_pool_bram_0__size8_bram_array_ram_row_0__block_ram_6__ram2048x9_bram_DOA_1__UNCONNECTED; + wire NLW_com_tlm_u_tlm_tx_vc0_buf_pool_bram_0__size8_bram_array_ram_row_0__block_ram_6__ram2048x9_bram_DOA_0__UNCONNECTED; + wire NLW_com_tlm_u_tlm_tx_vc0_buf_pool_bram_0__size8_bram_array_ram_row_0__block_ram_7__ram2048x9_bram_DOPA_0__UNCONNECTED; + wire NLW_com_tlm_u_tlm_tx_vc0_buf_pool_bram_0__size8_bram_array_ram_row_0__block_ram_7__ram2048x9_bram_DOPB_0__UNCONNECTED; + wire NLW_com_tlm_u_tlm_tx_vc0_buf_pool_bram_0__size8_bram_array_ram_row_0__block_ram_7__ram2048x9_bram_DOA_7__UNCONNECTED; + wire NLW_com_tlm_u_tlm_tx_vc0_buf_pool_bram_0__size8_bram_array_ram_row_0__block_ram_7__ram2048x9_bram_DOA_6__UNCONNECTED; + wire NLW_com_tlm_u_tlm_tx_vc0_buf_pool_bram_0__size8_bram_array_ram_row_0__block_ram_7__ram2048x9_bram_DOA_5__UNCONNECTED; + wire NLW_com_tlm_u_tlm_tx_vc0_buf_pool_bram_0__size8_bram_array_ram_row_0__block_ram_7__ram2048x9_bram_DOA_4__UNCONNECTED; + wire NLW_com_tlm_u_tlm_tx_vc0_buf_pool_bram_0__size8_bram_array_ram_row_0__block_ram_7__ram2048x9_bram_DOA_3__UNCONNECTED; + wire NLW_com_tlm_u_tlm_tx_vc0_buf_pool_bram_0__size8_bram_array_ram_row_0__block_ram_7__ram2048x9_bram_DOA_2__UNCONNECTED; + wire NLW_com_tlm_u_tlm_tx_vc0_buf_pool_bram_0__size8_bram_array_ram_row_0__block_ram_7__ram2048x9_bram_DOA_1__UNCONNECTED; + wire NLW_com_tlm_u_tlm_tx_vc0_buf_pool_bram_0__size8_bram_array_ram_row_0__block_ram_7__ram2048x9_bram_DOA_0__UNCONNECTED; + wire NLW_com_tlm_u_tlm_tx_vc0_buf_pool_bram_0__size8_bram_array_ram_row_0__block_ram_7__ram2048x9_bram_DOB_7__UNCONNECTED; + wire NLW_com_tlm_u_tlm_tx_vc0_buf_pool_bram_0__size8_bram_array_ram_row_0__block_ram_7__ram2048x9_bram_DOB_6__UNCONNECTED; + wire NLW_com_tlm_u_tlm_tx_vc0_buf_pool_bram_0__size8_bram_array_ram_row_0__block_ram_2__ram2048x9_bram_DOPA_0__UNCONNECTED; + wire NLW_com_tlm_u_tlm_tx_vc0_buf_pool_bram_0__size8_bram_array_ram_row_0__block_ram_2__ram2048x9_bram_DOA_7__UNCONNECTED; + wire NLW_com_tlm_u_tlm_tx_vc0_buf_pool_bram_0__size8_bram_array_ram_row_0__block_ram_2__ram2048x9_bram_DOA_6__UNCONNECTED; + wire NLW_com_tlm_u_tlm_tx_vc0_buf_pool_bram_0__size8_bram_array_ram_row_0__block_ram_2__ram2048x9_bram_DOA_5__UNCONNECTED; + wire NLW_com_tlm_u_tlm_tx_vc0_buf_pool_bram_0__size8_bram_array_ram_row_0__block_ram_2__ram2048x9_bram_DOA_4__UNCONNECTED; + wire NLW_com_tlm_u_tlm_tx_vc0_buf_pool_bram_0__size8_bram_array_ram_row_0__block_ram_2__ram2048x9_bram_DOA_3__UNCONNECTED; + wire NLW_com_tlm_u_tlm_tx_vc0_buf_pool_bram_0__size8_bram_array_ram_row_0__block_ram_2__ram2048x9_bram_DOA_2__UNCONNECTED; + wire NLW_com_tlm_u_tlm_tx_vc0_buf_pool_bram_0__size8_bram_array_ram_row_0__block_ram_2__ram2048x9_bram_DOA_1__UNCONNECTED; + wire NLW_com_tlm_u_tlm_tx_vc0_buf_pool_bram_0__size8_bram_array_ram_row_0__block_ram_2__ram2048x9_bram_DOA_0__UNCONNECTED; + wire NLW_com_tlm_u_tlm_tx_vc0_buf_pool_bram_0__size8_bram_array_ram_row_0__block_ram_5__ram2048x9_bram_DOPA_0__UNCONNECTED; + wire NLW_com_tlm_u_tlm_tx_vc0_buf_pool_bram_0__size8_bram_array_ram_row_0__block_ram_5__ram2048x9_bram_DOA_7__UNCONNECTED; + wire NLW_com_tlm_u_tlm_tx_vc0_buf_pool_bram_0__size8_bram_array_ram_row_0__block_ram_5__ram2048x9_bram_DOA_6__UNCONNECTED; + wire NLW_com_tlm_u_tlm_tx_vc0_buf_pool_bram_0__size8_bram_array_ram_row_0__block_ram_5__ram2048x9_bram_DOA_5__UNCONNECTED; + wire NLW_com_tlm_u_tlm_tx_vc0_buf_pool_bram_0__size8_bram_array_ram_row_0__block_ram_5__ram2048x9_bram_DOA_4__UNCONNECTED; + wire NLW_com_tlm_u_tlm_tx_vc0_buf_pool_bram_0__size8_bram_array_ram_row_0__block_ram_5__ram2048x9_bram_DOA_3__UNCONNECTED; + wire NLW_com_tlm_u_tlm_tx_vc0_buf_pool_bram_0__size8_bram_array_ram_row_0__block_ram_5__ram2048x9_bram_DOA_2__UNCONNECTED; + wire NLW_com_tlm_u_tlm_tx_vc0_buf_pool_bram_0__size8_bram_array_ram_row_0__block_ram_5__ram2048x9_bram_DOA_1__UNCONNECTED; + wire NLW_com_tlm_u_tlm_tx_vc0_buf_pool_bram_0__size8_bram_array_ram_row_0__block_ram_5__ram2048x9_bram_DOA_0__UNCONNECTED; + wire NLW_com_tlm_u_tlm_tx_vc0_token_fifo_t_fifo_srlrow_0__srlcol_0__srlinst_Q15_UNCONNECTED; + wire NLW_com_tlm_u_tlm_tx_vc0_token_fifo_t_fifo_srlrow_0__srlcol_3__srlinst_Q15_UNCONNECTED; + wire NLW_com_tlm_u_tlm_tx_vc0_token_fifo_t_fifo_srlrow_0__srlcol_2__srlinst_Q15_UNCONNECTED; + wire NLW_com_tlm_u_tlm_tx_vc0_token_fifo_t_fifo_srlrow_0__srlcol_1__srlinst_Q15_UNCONNECTED; + wire NLW_com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_srlrow_0__srlcol_0__srlinst_Q15_UNCONNECTED; + wire NLW_com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_srlrow_0__srlcol_9__srlinst_Q15_UNCONNECTED; + wire NLW_com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_srlrow_0__srlcol_5__srlinst_Q15_UNCONNECTED; + wire NLW_com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_srlrow_0__srlcol_1__srlinst_Q15_UNCONNECTED; + wire NLW_com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_srlrow_0__srlcol_10__srlinst_Q15_UNCONNECTED; + wire NLW_com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_srlrow_0__srlcol_6__srlinst_Q15_UNCONNECTED; + wire NLW_com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_srlrow_0__srlcol_2__srlinst_Q15_UNCONNECTED; + wire NLW_com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_srlrow_0__srlcol_11__srlinst_Q15_UNCONNECTED; + wire NLW_com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_srlrow_0__srlcol_7__srlinst_Q15_UNCONNECTED; + wire NLW_com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_srlrow_0__srlcol_3__srlinst_Q15_UNCONNECTED; + wire NLW_com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_srlrow_0__srlcol_12__srlinst_Q15_UNCONNECTED; + wire NLW_com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_srlrow_0__srlcol_8__srlinst_Q15_UNCONNECTED; + wire NLW_com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_srlrow_0__srlcol_4__srlinst_Q15_UNCONNECTED; + wire NLW_com_tlm_u_tlm_tx_vc0_frm_seq_bq_fifo_srlrow_0__srlcol_0__srlinst_Q15_UNCONNECTED; + wire NLW_com_tlm_u_tlm_tx_vc0_frm_seq_bq_fifo_srlrow_0__srlcol_5__srlinst_Q15_UNCONNECTED; + wire NLW_com_tlm_u_tlm_tx_vc0_frm_seq_bq_fifo_srlrow_0__srlcol_9__srlinst_Q15_UNCONNECTED; + wire NLW_com_tlm_u_tlm_tx_vc0_frm_seq_bq_fifo_srlrow_0__srlcol_10__srlinst_Q15_UNCONNECTED; + wire NLW_com_tlm_u_tlm_tx_vc0_frm_seq_bq_fifo_srlrow_0__srlcol_6__srlinst_Q15_UNCONNECTED; + wire NLW_com_tlm_u_tlm_tx_vc0_frm_seq_bq_fifo_srlrow_0__srlcol_7__srlinst_Q15_UNCONNECTED; + wire NLW_com_tlm_u_tlm_tx_vc0_frm_seq_bq_fifo_srlrow_0__srlcol_4__srlinst_Q15_UNCONNECTED; + wire NLW_com_tlm_u_tlm_tx_vc0_frm_seq_bq_fifo_srlrow_0__srlcol_3__srlinst_Q15_UNCONNECTED; + wire NLW_com_tlm_u_tlm_tx_vc0_frm_seq_bq_fifo_srlrow_0__srlcol_8__srlinst_Q15_UNCONNECTED; + wire NLW_com_tlm_u_tlm_tx_vc0_frm_seq_bq_fifo_srlrow_0__srlcol_1__srlinst_Q15_UNCONNECTED; + wire NLW_com_tlm_u_tlm_tx_vc0_frm_seq_bq_fifo_srlrow_0__srlcol_2__srlinst_Q15_UNCONNECTED; + wire NLW_com_tlm_u_tlm_tx_vc0_frm_seq_sq_fifo_srlrow_0__srlcol_0__srlinst_Q15_UNCONNECTED; + wire NLW_com_tlm_u_tlm_tx_vc0_frm_seq_sq_fifo_srlrow_0__srlcol_3__srlinst_Q15_UNCONNECTED; + wire NLW_com_tlm_u_tlm_tx_vc0_frm_seq_sq_fifo_srlrow_0__srlcol_2__srlinst_Q15_UNCONNECTED; + wire NLW_com_tlm_u_tlm_tx_vc0_frm_seq_sq_fifo_srlrow_0__srlcol_1__srlinst_Q15_UNCONNECTED; + wire NLW_com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_queue_ram_ram_row_0__block_ram_0__ram1024x18_bram_DOPA_1__UNCONNECTED; + wire NLW_com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_queue_ram_ram_row_0__block_ram_0__ram1024x18_bram_DOPA_0__UNCONNECTED; + wire NLW_com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_queue_ram_ram_row_0__block_ram_0__ram1024x18_bram_DOA_15__UNCONNECTED; + wire NLW_com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_queue_ram_ram_row_0__block_ram_0__ram1024x18_bram_DOA_14__UNCONNECTED; + wire NLW_com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_queue_ram_ram_row_0__block_ram_0__ram1024x18_bram_DOA_13__UNCONNECTED; + wire NLW_com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_queue_ram_ram_row_0__block_ram_0__ram1024x18_bram_DOA_12__UNCONNECTED; + wire NLW_com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_queue_ram_ram_row_0__block_ram_0__ram1024x18_bram_DOA_11__UNCONNECTED; + wire NLW_com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_queue_ram_ram_row_0__block_ram_0__ram1024x18_bram_DOA_10__UNCONNECTED; + wire NLW_com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_queue_ram_ram_row_0__block_ram_0__ram1024x18_bram_DOA_9__UNCONNECTED; + wire NLW_com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_queue_ram_ram_row_0__block_ram_0__ram1024x18_bram_DOA_8__UNCONNECTED; + wire NLW_com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_queue_ram_ram_row_0__block_ram_0__ram1024x18_bram_DOA_7__UNCONNECTED; + wire NLW_com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_queue_ram_ram_row_0__block_ram_0__ram1024x18_bram_DOA_6__UNCONNECTED; + wire NLW_com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_queue_ram_ram_row_0__block_ram_0__ram1024x18_bram_DOA_5__UNCONNECTED; + wire NLW_com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_queue_ram_ram_row_0__block_ram_0__ram1024x18_bram_DOA_4__UNCONNECTED; + wire NLW_com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_queue_ram_ram_row_0__block_ram_0__ram1024x18_bram_DOA_3__UNCONNECTED; + wire NLW_com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_queue_ram_ram_row_0__block_ram_0__ram1024x18_bram_DOA_2__UNCONNECTED; + wire NLW_com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_queue_ram_ram_row_0__block_ram_0__ram1024x18_bram_DOA_1__UNCONNECTED; + wire NLW_com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_queue_ram_ram_row_0__block_ram_0__ram1024x18_bram_DOA_0__UNCONNECTED; + wire NLW_com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_queue_ram_ram_row_0__block_ram_1__ram1024x18_bram_DOPA_1__UNCONNECTED; + wire NLW_com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_queue_ram_ram_row_0__block_ram_1__ram1024x18_bram_DOPA_0__UNCONNECTED; + wire NLW_com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_queue_ram_ram_row_0__block_ram_1__ram1024x18_bram_DOA_15__UNCONNECTED; + wire NLW_com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_queue_ram_ram_row_0__block_ram_1__ram1024x18_bram_DOA_14__UNCONNECTED; + wire NLW_com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_queue_ram_ram_row_0__block_ram_1__ram1024x18_bram_DOA_13__UNCONNECTED; + wire NLW_com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_queue_ram_ram_row_0__block_ram_1__ram1024x18_bram_DOA_12__UNCONNECTED; + wire NLW_com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_queue_ram_ram_row_0__block_ram_1__ram1024x18_bram_DOA_11__UNCONNECTED; + wire NLW_com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_queue_ram_ram_row_0__block_ram_1__ram1024x18_bram_DOA_10__UNCONNECTED; + wire NLW_com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_queue_ram_ram_row_0__block_ram_1__ram1024x18_bram_DOA_9__UNCONNECTED; + wire NLW_com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_queue_ram_ram_row_0__block_ram_1__ram1024x18_bram_DOA_8__UNCONNECTED; + wire NLW_com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_queue_ram_ram_row_0__block_ram_1__ram1024x18_bram_DOA_7__UNCONNECTED; + wire NLW_com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_queue_ram_ram_row_0__block_ram_1__ram1024x18_bram_DOA_6__UNCONNECTED; + wire NLW_com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_queue_ram_ram_row_0__block_ram_1__ram1024x18_bram_DOA_5__UNCONNECTED; + wire NLW_com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_queue_ram_ram_row_0__block_ram_1__ram1024x18_bram_DOA_4__UNCONNECTED; + wire NLW_com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_queue_ram_ram_row_0__block_ram_1__ram1024x18_bram_DOA_3__UNCONNECTED; + wire NLW_com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_queue_ram_ram_row_0__block_ram_1__ram1024x18_bram_DOA_2__UNCONNECTED; + wire NLW_com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_queue_ram_ram_row_0__block_ram_1__ram1024x18_bram_DOA_1__UNCONNECTED; + wire NLW_com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_queue_ram_ram_row_0__block_ram_1__ram1024x18_bram_DOA_0__UNCONNECTED; + wire NLW_com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_queue_ram_ram_row_0__block_ram_2__ram1024x18_bram_DOPA_1__UNCONNECTED; + wire NLW_com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_queue_ram_ram_row_0__block_ram_2__ram1024x18_bram_DOPA_0__UNCONNECTED; + wire NLW_com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_queue_ram_ram_row_0__block_ram_2__ram1024x18_bram_DOA_15__UNCONNECTED; + wire NLW_com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_queue_ram_ram_row_0__block_ram_2__ram1024x18_bram_DOA_14__UNCONNECTED; + wire NLW_com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_queue_ram_ram_row_0__block_ram_2__ram1024x18_bram_DOA_13__UNCONNECTED; + wire NLW_com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_queue_ram_ram_row_0__block_ram_2__ram1024x18_bram_DOA_12__UNCONNECTED; + wire NLW_com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_queue_ram_ram_row_0__block_ram_2__ram1024x18_bram_DOA_11__UNCONNECTED; + wire NLW_com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_queue_ram_ram_row_0__block_ram_2__ram1024x18_bram_DOA_10__UNCONNECTED; + wire NLW_com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_queue_ram_ram_row_0__block_ram_2__ram1024x18_bram_DOA_9__UNCONNECTED; + wire NLW_com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_queue_ram_ram_row_0__block_ram_2__ram1024x18_bram_DOA_8__UNCONNECTED; + wire NLW_com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_queue_ram_ram_row_0__block_ram_2__ram1024x18_bram_DOA_7__UNCONNECTED; + wire NLW_com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_queue_ram_ram_row_0__block_ram_2__ram1024x18_bram_DOA_6__UNCONNECTED; + wire NLW_com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_queue_ram_ram_row_0__block_ram_2__ram1024x18_bram_DOA_5__UNCONNECTED; + wire NLW_com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_queue_ram_ram_row_0__block_ram_2__ram1024x18_bram_DOA_4__UNCONNECTED; + wire NLW_com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_queue_ram_ram_row_0__block_ram_2__ram1024x18_bram_DOA_3__UNCONNECTED; + wire NLW_com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_queue_ram_ram_row_0__block_ram_2__ram1024x18_bram_DOA_2__UNCONNECTED; + wire NLW_com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_queue_ram_ram_row_0__block_ram_2__ram1024x18_bram_DOA_1__UNCONNECTED; + wire NLW_com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_queue_ram_ram_row_0__block_ram_2__ram1024x18_bram_DOA_0__UNCONNECTED; + wire NLW_com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_queue_ram_ram_row_0__block_ram_3__ram1024x18_bram_DOPA_1__UNCONNECTED; + wire NLW_com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_queue_ram_ram_row_0__block_ram_3__ram1024x18_bram_DOPA_0__UNCONNECTED; + wire NLW_com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_queue_ram_ram_row_0__block_ram_3__ram1024x18_bram_DOPB_1__UNCONNECTED; + wire NLW_com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_queue_ram_ram_row_0__block_ram_3__ram1024x18_bram_DOPB_0__UNCONNECTED; + wire NLW_com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_queue_ram_ram_row_0__block_ram_3__ram1024x18_bram_DOA_15__UNCONNECTED; + wire NLW_com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_queue_ram_ram_row_0__block_ram_3__ram1024x18_bram_DOA_14__UNCONNECTED; + wire NLW_com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_queue_ram_ram_row_0__block_ram_3__ram1024x18_bram_DOA_13__UNCONNECTED; + wire NLW_com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_queue_ram_ram_row_0__block_ram_3__ram1024x18_bram_DOA_12__UNCONNECTED; + wire NLW_com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_queue_ram_ram_row_0__block_ram_3__ram1024x18_bram_DOA_11__UNCONNECTED; + wire NLW_com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_queue_ram_ram_row_0__block_ram_3__ram1024x18_bram_DOA_10__UNCONNECTED; + wire NLW_com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_queue_ram_ram_row_0__block_ram_3__ram1024x18_bram_DOA_9__UNCONNECTED; + wire NLW_com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_queue_ram_ram_row_0__block_ram_3__ram1024x18_bram_DOA_8__UNCONNECTED; + wire NLW_com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_queue_ram_ram_row_0__block_ram_3__ram1024x18_bram_DOA_7__UNCONNECTED; + wire NLW_com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_queue_ram_ram_row_0__block_ram_3__ram1024x18_bram_DOA_6__UNCONNECTED; + wire NLW_com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_queue_ram_ram_row_0__block_ram_3__ram1024x18_bram_DOA_5__UNCONNECTED; + wire NLW_com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_queue_ram_ram_row_0__block_ram_3__ram1024x18_bram_DOA_4__UNCONNECTED; + wire NLW_com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_queue_ram_ram_row_0__block_ram_3__ram1024x18_bram_DOA_3__UNCONNECTED; + wire NLW_com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_queue_ram_ram_row_0__block_ram_3__ram1024x18_bram_DOA_2__UNCONNECTED; + wire NLW_com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_queue_ram_ram_row_0__block_ram_3__ram1024x18_bram_DOA_1__UNCONNECTED; + wire NLW_com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_queue_ram_ram_row_0__block_ram_3__ram1024x18_bram_DOA_0__UNCONNECTED; + wire NLW_com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_queue_ram_ram_row_0__block_ram_3__ram1024x18_bram_DOB_15__UNCONNECTED; + wire NLW_com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_queue_ram_ram_row_0__block_ram_3__ram1024x18_bram_DOB_14__UNCONNECTED; + wire NLW_com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_srlrow_4__srlcol_8__srlinst_Q15_UNCONNECTED; + wire NLW_com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_srlrow_4__srlcol_5__srlinst_Q15_UNCONNECTED; + wire NLW_com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_srlrow_4__srlcol_6__srlinst_Q15_UNCONNECTED; + wire NLW_com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_srlrow_4__srlcol_7__srlinst_Q15_UNCONNECTED; + wire NLW_com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_srlrow_4__srlcol_4__srlinst_Q15_UNCONNECTED; + wire NLW_com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_srlrow_4__srlcol_0__srlinst_Q15_UNCONNECTED; + wire NLW_com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_srlrow_4__srlcol_1__srlinst_Q15_UNCONNECTED; + wire NLW_com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_srlrow_4__srlcol_3__srlinst_Q15_UNCONNECTED; + wire NLW_com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_srlrow_4__srlcol_2__srlinst_Q15_UNCONNECTED; + wire NLW_com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_srlrow_1__srlcol_9__srlinst_Q15_UNCONNECTED; + wire NLW_com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_srlrow_1__srlcol_10__srlinst_Q15_UNCONNECTED; + wire NLW_com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_srlrow_1__srlcol_11__srlinst_Q15_UNCONNECTED; + wire NLW_com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_srlrow_1__srlcol_30__srlinst_Q15_UNCONNECTED; + wire NLW_com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_srlrow_1__srlcol_13__srlinst_Q15_UNCONNECTED; + wire NLW_com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_srlrow_1__srlcol_14__srlinst_Q15_UNCONNECTED; + wire NLW_com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_srlrow_1__srlcol_16__srlinst_Q15_UNCONNECTED; + wire NLW_com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_srlrow_1__srlcol_17__srlinst_Q15_UNCONNECTED; + wire NLW_com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_srlrow_1__srlcol_18__srlinst_Q15_UNCONNECTED; + wire NLW_com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_srlrow_1__srlcol_19__srlinst_Q15_UNCONNECTED; + wire NLW_com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_srlrow_1__srlcol_20__srlinst_Q15_UNCONNECTED; + wire NLW_com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_srlrow_1__srlcol_22__srlinst_Q15_UNCONNECTED; + wire NLW_com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_srlrow_1__srlcol_61__srlinst_Q15_UNCONNECTED; + wire NLW_com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_srlrow_1__srlcol_57__srlinst_Q15_UNCONNECTED; + wire NLW_com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_srlrow_1__srlcol_23__srlinst_Q15_UNCONNECTED; + wire NLW_com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_srlrow_1__srlcol_24__srlinst_Q15_UNCONNECTED; + wire NLW_com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_srlrow_1__srlcol_25__srlinst_Q15_UNCONNECTED; + wire NLW_com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_srlrow_1__srlcol_26__srlinst_Q15_UNCONNECTED; + wire NLW_com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_srlrow_1__srlcol_27__srlinst_Q15_UNCONNECTED; + wire NLW_com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_srlrow_1__srlcol_28__srlinst_Q15_UNCONNECTED; + wire NLW_com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_srlrow_1__srlcol_67__srlinst_Q15_UNCONNECTED; + wire NLW_com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_srlrow_1__srlcol_63__srlinst_Q15_UNCONNECTED; + wire NLW_com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_srlrow_1__srlcol_29__srlinst_Q15_UNCONNECTED; + wire NLW_com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_srlrow_1__srlcol_21__srlinst_Q15_UNCONNECTED; + wire NLW_com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_srlrow_1__srlcol_31__srlinst_Q15_UNCONNECTED; + wire NLW_com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_srlrow_1__srlcol_32__srlinst_Q15_UNCONNECTED; + wire NLW_com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_srlrow_1__srlcol_33__srlinst_Q15_UNCONNECTED; + wire NLW_com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_srlrow_1__srlcol_34__srlinst_Q15_UNCONNECTED; + wire NLW_com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_srlrow_1__srlcol_35__srlinst_Q15_UNCONNECTED; + wire NLW_com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_srlrow_1__srlcol_36__srlinst_Q15_UNCONNECTED; + wire NLW_com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_srlrow_1__srlcol_37__srlinst_Q15_UNCONNECTED; + wire NLW_com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_srlrow_1__srlcol_38__srlinst_Q15_UNCONNECTED; + wire NLW_com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_srlrow_1__srlcol_39__srlinst_Q15_UNCONNECTED; + wire NLW_com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_srlrow_1__srlcol_40__srlinst_Q15_UNCONNECTED; + wire NLW_com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_srlrow_1__srlcol_0__srlinst_Q15_UNCONNECTED; + wire NLW_com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_srlrow_1__srlcol_41__srlinst_Q15_UNCONNECTED; + wire NLW_com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_srlrow_1__srlcol_1__srlinst_Q15_UNCONNECTED; + wire NLW_com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_srlrow_1__srlcol_42__srlinst_Q15_UNCONNECTED; + wire NLW_com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_srlrow_1__srlcol_2__srlinst_Q15_UNCONNECTED; + wire NLW_com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_srlrow_1__srlcol_43__srlinst_Q15_UNCONNECTED; + wire NLW_com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_srlrow_1__srlcol_3__srlinst_Q15_UNCONNECTED; + wire NLW_com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_srlrow_1__srlcol_44__srlinst_Q15_UNCONNECTED; + wire NLW_com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_srlrow_1__srlcol_4__srlinst_Q15_UNCONNECTED; + wire NLW_com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_srlrow_1__srlcol_45__srlinst_Q15_UNCONNECTED; + wire NLW_com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_srlrow_1__srlcol_5__srlinst_Q15_UNCONNECTED; + wire NLW_com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_srlrow_1__srlcol_46__srlinst_Q15_UNCONNECTED; + wire NLW_com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_srlrow_1__srlcol_6__srlinst_Q15_UNCONNECTED; + wire NLW_com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_srlrow_1__srlcol_7__srlinst_Q15_UNCONNECTED; + wire NLW_com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_srlrow_1__srlcol_12__srlinst_Q15_UNCONNECTED; + wire NLW_com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_srlrow_1__srlcol_49__srlinst_Q15_UNCONNECTED; + wire NLW_com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_srlrow_1__srlcol_15__srlinst_Q15_UNCONNECTED; + wire NLW_com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_srlrow_1__srlcol_50__srlinst_Q15_UNCONNECTED; + wire NLW_com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_srlrow_1__srlcol_64__srlinst_Q15_UNCONNECTED; + wire NLW_com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_srlrow_1__srlcol_51__srlinst_Q15_UNCONNECTED; + wire NLW_com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_srlrow_1__srlcol_65__srlinst_Q15_UNCONNECTED; + wire NLW_com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_srlrow_1__srlcol_52__srlinst_Q15_UNCONNECTED; + wire NLW_com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_srlrow_1__srlcol_48__srlinst_Q15_UNCONNECTED; + wire NLW_com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_srlrow_1__srlcol_8__srlinst_Q15_UNCONNECTED; + wire NLW_com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_srlrow_1__srlcol_53__srlinst_Q15_UNCONNECTED; + wire NLW_com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_srlrow_1__srlcol_58__srlinst_Q15_UNCONNECTED; + wire NLW_com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_srlrow_1__srlcol_54__srlinst_Q15_UNCONNECTED; + wire NLW_com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_srlrow_1__srlcol_60__srlinst_Q15_UNCONNECTED; + wire NLW_com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_srlrow_1__srlcol_59__srlinst_Q15_UNCONNECTED; + wire NLW_com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_srlrow_1__srlcol_55__srlinst_Q15_UNCONNECTED; + wire NLW_com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_srlrow_1__srlcol_47__srlinst_Q15_UNCONNECTED; + wire NLW_com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_srlrow_1__srlcol_56__srlinst_Q15_UNCONNECTED; + wire NLW_com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_srlrow_1__srlcol_62__srlinst_Q15_UNCONNECTED; + wire NLW_com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_queue_aux_queue_srlrow_0__srlcol_0__srlinst_Q15_UNCONNECTED; + wire NLW_com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_queue_aux_queue_srlrow_0__srlcol_3__srlinst_Q15_UNCONNECTED; + wire NLW_com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_queue_aux_queue_srlrow_0__srlcol_2__srlinst_Q15_UNCONNECTED; + wire NLW_com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_queue_aux_queue_srlrow_0__srlcol_1__srlinst_Q15_UNCONNECTED; + wire NLW_com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_queue_aux_queue_srlrow_0__srlcol_4__srlinst_Q15_UNCONNECTED; + wire NLW_com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_queue_aux_queue_srlrow_0__srlcol_7__srlinst_Q15_UNCONNECTED; + wire NLW_com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_queue_aux_queue_srlrow_0__srlcol_6__srlinst_Q15_UNCONNECTED; + wire NLW_com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_queue_aux_queue_srlrow_0__srlcol_5__srlinst_Q15_UNCONNECTED; + wire NLW_com_cmm_u_cmm_errman_cmt_hdr_buf_lutram_data_I_1_SPO_UNCONNECTED; + wire NLW_com_cmm_u_cmm_errman_cmt_hdr_buf_lutram_data_I_2_SPO_UNCONNECTED; + wire NLW_com_cmm_u_cmm_errman_cmt_hdr_buf_lutram_data_I_3_SPO_UNCONNECTED; + wire NLW_com_cmm_u_cmm_errman_cmt_hdr_buf_lutram_data_I_4_SPO_UNCONNECTED; + wire NLW_com_cmm_u_cmm_errman_cmt_hdr_buf_lutram_data_I_5_SPO_UNCONNECTED; + wire NLW_com_cmm_u_cmm_errman_cmt_hdr_buf_lutram_data_I_6_SPO_UNCONNECTED; + wire NLW_com_cmm_u_cmm_errman_cmt_hdr_buf_lutram_data_I_7_SPO_UNCONNECTED; + wire NLW_com_cmm_u_cmm_errman_cmt_hdr_buf_lutram_data_I_8_SPO_UNCONNECTED; + wire NLW_com_cmm_u_cmm_errman_cmt_hdr_buf_lutram_data_I_9_SPO_UNCONNECTED; + wire NLW_com_cmm_u_cmm_errman_cmt_hdr_buf_lutram_data_I_10_SPO_UNCONNECTED; + wire NLW_com_cmm_u_cmm_errman_cmt_hdr_buf_lutram_data_I_11_SPO_UNCONNECTED; + wire NLW_com_cmm_u_cmm_errman_cmt_hdr_buf_lutram_data_I_12_SPO_UNCONNECTED; + wire NLW_com_cmm_u_cmm_errman_cmt_hdr_buf_lutram_data_I_13_SPO_UNCONNECTED; + wire NLW_com_cmm_u_cmm_errman_cmt_hdr_buf_lutram_data_I_14_SPO_UNCONNECTED; + wire NLW_com_cmm_u_cmm_errman_cmt_hdr_buf_lutram_data_I_15_SPO_UNCONNECTED; + wire NLW_com_cmm_u_cmm_errman_cmt_hdr_buf_lutram_data_I_16_SPO_UNCONNECTED; + wire NLW_com_cmm_u_cmm_errman_cmt_hdr_buf_lutram_data_I_17_SPO_UNCONNECTED; + wire NLW_com_cmm_u_cmm_errman_cmt_hdr_buf_lutram_data_I_18_SPO_UNCONNECTED; + wire NLW_com_cmm_u_cmm_errman_cmt_hdr_buf_lutram_data_I_19_SPO_UNCONNECTED; + wire NLW_com_cmm_u_cmm_errman_cmt_hdr_buf_lutram_data_I_20_SPO_UNCONNECTED; + wire NLW_com_cmm_u_cmm_errman_cmt_hdr_buf_lutram_data_I_21_SPO_UNCONNECTED; + wire NLW_com_cmm_u_cmm_errman_cmt_hdr_buf_lutram_data_I_22_SPO_UNCONNECTED; + wire NLW_com_cmm_u_cmm_errman_cmt_hdr_buf_lutram_data_I_23_SPO_UNCONNECTED; + wire NLW_com_cmm_u_cmm_errman_cmt_hdr_buf_lutram_data_I_24_SPO_UNCONNECTED; + wire NLW_com_cmm_u_cmm_errman_cmt_hdr_buf_lutram_data_I_25_SPO_UNCONNECTED; + wire NLW_com_cmm_u_cmm_errman_cmt_hdr_buf_lutram_data_I_26_SPO_UNCONNECTED; + wire NLW_com_cmm_u_cmm_errman_cmt_hdr_buf_lutram_data_I_27_SPO_UNCONNECTED; + wire NLW_com_cmm_u_cmm_errman_cmt_hdr_buf_lutram_data_I_28_SPO_UNCONNECTED; + wire NLW_com_cmm_u_cmm_errman_cmt_hdr_buf_lutram_data_I_29_SPO_UNCONNECTED; + wire NLW_com_cmm_u_cmm_errman_cmt_hdr_buf_lutram_data_I_30_SPO_UNCONNECTED; + wire NLW_com_cmm_u_cmm_errman_cmt_hdr_buf_lutram_data_I_31_SPO_UNCONNECTED; + wire NLW_com_cmm_u_cmm_errman_cmt_hdr_buf_lutram_data_I_32_SPO_UNCONNECTED; + wire NLW_com_cmm_u_cmm_errman_cmt_hdr_buf_lutram_data_I_33_SPO_UNCONNECTED; + wire NLW_com_cmm_u_cmm_errman_cmt_hdr_buf_lutram_data_I_34_SPO_UNCONNECTED; + wire NLW_com_cmm_u_cmm_errman_cmt_hdr_buf_lutram_data_I_35_SPO_UNCONNECTED; + wire NLW_com_cmm_u_cmm_errman_cmt_hdr_buf_lutram_data_I_36_SPO_UNCONNECTED; + wire NLW_com_cmm_u_cmm_errman_cmt_hdr_buf_lutram_data_I_37_SPO_UNCONNECTED; + wire NLW_com_cmm_u_cmm_errman_cmt_hdr_buf_lutram_data_I_38_SPO_UNCONNECTED; + wire NLW_com_cmm_u_cmm_errman_cmt_hdr_buf_lutram_data_I_39_SPO_UNCONNECTED; + wire NLW_com_cmm_u_cmm_errman_cmt_hdr_buf_lutram_data_I_40_SPO_UNCONNECTED; + wire NLW_com_cmm_u_cmm_errman_cmt_hdr_buf_lutram_data_I_41_SPO_UNCONNECTED; + wire NLW_com_cmm_u_cmm_errman_cmt_hdr_buf_lutram_data_I_42_SPO_UNCONNECTED; + wire NLW_com_cmm_u_cmm_errman_cmt_hdr_buf_lutram_data_I_43_SPO_UNCONNECTED; + wire NLW_com_cmm_u_cmm_errman_cmt_hdr_buf_lutram_data_I_44_SPO_UNCONNECTED; + wire NLW_com_cmm_u_cmm_errman_cmt_hdr_buf_lutram_data_I_45_SPO_UNCONNECTED; + wire NLW_com_cmm_u_cmm_errman_cmt_hdr_buf_lutram_data_I_46_SPO_UNCONNECTED; + wire NLW_com_cmm_u_cmm_errman_cmt_hdr_buf_lutram_data_I_47_SPO_UNCONNECTED; + wire NLW_com_cmm_u_cmm_errman_cmt_hdr_buf_lutram_data_I_48_SPO_UNCONNECTED; + wire NLW_com_cmm_u_cmm_errman_cmt_hdr_buf_lutram_data_I_49_SPO_UNCONNECTED; + wire NLW_com_cmm_u_cmm_errman_cmt_hdr_buf_lutram_data_I_50_SPO_UNCONNECTED; + wire NLW_com_cmm_u_cmm_errman_cfg_hdr_buf_lutram_data_I_1_SPO_UNCONNECTED; + wire NLW_com_cmm_u_cmm_errman_cfg_hdr_buf_lutram_data_I_2_SPO_UNCONNECTED; + wire NLW_com_cmm_u_cmm_errman_cfg_hdr_buf_lutram_data_I_3_SPO_UNCONNECTED; + wire NLW_com_cmm_u_cmm_errman_cfg_hdr_buf_lutram_data_I_4_SPO_UNCONNECTED; + wire NLW_com_cmm_u_cmm_errman_cfg_hdr_buf_lutram_data_I_5_SPO_UNCONNECTED; + wire NLW_com_cmm_u_cmm_errman_cfg_hdr_buf_lutram_data_I_6_SPO_UNCONNECTED; + wire NLW_com_cmm_u_cmm_errman_cfg_hdr_buf_lutram_data_I_7_SPO_UNCONNECTED; + wire NLW_com_cmm_u_cmm_errman_cfg_hdr_buf_lutram_data_I_8_SPO_UNCONNECTED; + wire NLW_com_cmm_u_cmm_errman_cfg_hdr_buf_lutram_data_I_9_SPO_UNCONNECTED; + wire NLW_com_cmm_u_cmm_errman_cfg_hdr_buf_lutram_data_I_10_SPO_UNCONNECTED; + wire NLW_com_cmm_u_cmm_errman_cfg_hdr_buf_lutram_data_I_11_SPO_UNCONNECTED; + wire NLW_com_cmm_u_cmm_errman_cfg_hdr_buf_lutram_data_I_12_SPO_UNCONNECTED; + wire NLW_com_cmm_u_cmm_errman_cfg_hdr_buf_lutram_data_I_13_SPO_UNCONNECTED; + wire NLW_com_cmm_u_cmm_errman_cfg_hdr_buf_lutram_data_I_14_SPO_UNCONNECTED; + wire NLW_com_cmm_u_cmm_errman_cfg_hdr_buf_lutram_data_I_15_SPO_UNCONNECTED; + wire NLW_com_cmm_u_cmm_errman_cfg_hdr_buf_lutram_data_I_16_SPO_UNCONNECTED; + wire NLW_com_cmm_u_cmm_errman_cfg_hdr_buf_lutram_data_I_17_SPO_UNCONNECTED; + wire NLW_com_cmm_u_cmm_errman_cfg_hdr_buf_lutram_data_I_18_SPO_UNCONNECTED; + wire NLW_com_cmm_u_cmm_errman_cfg_hdr_buf_lutram_data_I_19_SPO_UNCONNECTED; + wire NLW_com_cmm_u_cmm_errman_cfg_hdr_buf_lutram_data_I_20_SPO_UNCONNECTED; + wire NLW_com_cmm_u_cmm_errman_cfg_hdr_buf_lutram_data_I_21_SPO_UNCONNECTED; + wire NLW_com_cmm_u_cmm_errman_cfg_hdr_buf_lutram_data_I_22_SPO_UNCONNECTED; + wire NLW_com_cmm_u_cmm_errman_cfg_hdr_buf_lutram_data_I_23_SPO_UNCONNECTED; + wire NLW_com_cmm_u_cmm_errman_cfg_hdr_buf_lutram_data_I_24_SPO_UNCONNECTED; + wire NLW_com_cmm_u_cmm_errman_cfg_hdr_buf_lutram_data_I_25_SPO_UNCONNECTED; + wire NLW_com_cmm_u_cmm_errman_cfg_hdr_buf_lutram_data_I_26_SPO_UNCONNECTED; + wire NLW_com_cmm_u_cmm_errman_cfg_hdr_buf_lutram_data_I_27_SPO_UNCONNECTED; + wire NLW_com_cmm_u_cmm_errman_cfg_hdr_buf_lutram_data_I_28_SPO_UNCONNECTED; + wire NLW_com_cmm_u_cmm_errman_cfg_hdr_buf_lutram_data_I_29_SPO_UNCONNECTED; + wire NLW_com_cmm_u_cmm_errman_cfg_hdr_buf_lutram_data_I_30_SPO_UNCONNECTED; + wire NLW_com_cmm_u_cmm_errman_cfg_hdr_buf_lutram_data_I_31_SPO_UNCONNECTED; + wire NLW_com_cmm_u_cmm_errman_cfg_hdr_buf_lutram_data_I_32_SPO_UNCONNECTED; + wire NLW_com_cmm_u_cmm_errman_cfg_hdr_buf_lutram_data_I_33_SPO_UNCONNECTED; + wire NLW_com_cmm_u_cmm_errman_cfg_hdr_buf_lutram_data_I_34_SPO_UNCONNECTED; + wire NLW_com_cmm_u_cmm_errman_cfg_hdr_buf_lutram_data_I_35_SPO_UNCONNECTED; + wire NLW_com_cmm_u_cmm_errman_cfg_hdr_buf_lutram_data_I_36_SPO_UNCONNECTED; + wire NLW_com_cmm_u_cmm_errman_cfg_hdr_buf_lutram_data_I_37_SPO_UNCONNECTED; + wire NLW_com_cmm_u_cmm_errman_cfg_hdr_buf_lutram_data_I_38_SPO_UNCONNECTED; + wire NLW_com_cmm_u_cmm_errman_cfg_hdr_buf_lutram_data_I_39_SPO_UNCONNECTED; + wire NLW_com_cmm_u_cmm_errman_cfg_hdr_buf_lutram_data_I_40_SPO_UNCONNECTED; + wire NLW_com_cmm_u_cmm_errman_cfg_hdr_buf_lutram_data_I_41_SPO_UNCONNECTED; + wire NLW_com_cmm_u_cmm_errman_cfg_hdr_buf_lutram_data_I_42_SPO_UNCONNECTED; + wire NLW_com_cmm_u_cmm_errman_cfg_hdr_buf_lutram_data_I_43_SPO_UNCONNECTED; + wire NLW_com_cmm_u_cmm_errman_cfg_hdr_buf_lutram_data_I_44_SPO_UNCONNECTED; + wire NLW_com_cmm_u_cmm_errman_cfg_hdr_buf_lutram_data_I_45_SPO_UNCONNECTED; + wire NLW_com_cmm_u_cmm_errman_cfg_hdr_buf_lutram_data_I_46_SPO_UNCONNECTED; + wire NLW_com_cmm_u_cmm_errman_cfg_hdr_buf_lutram_data_I_47_SPO_UNCONNECTED; + wire NLW_com_cmm_u_cmm_errman_cfg_hdr_buf_lutram_data_I_48_SPO_UNCONNECTED; + wire NLW_com_cmm_u_cmm_errman_cfg_hdr_buf_lutram_data_I_49_SPO_UNCONNECTED; + wire NLW_com_cmm_u_cmm_errman_cfg_hdr_buf_lutram_data_I_50_SPO_UNCONNECTED; + wire [0 : 0] pci_exp_txp_5053; + wire [0 : 0] pci_exp_txn_5054; + wire [0 : 0] pci_exp_rxp_5055; + wire [0 : 0] pci_exp_rxn_5056; + wire [63 : 0] trn_td_5057; + wire [7 : 0] trn_trem_n_5058; + wire [4 : 0] NlwRenamedSig_OI_trn_tbuf_av; + wire [63 : 0] NlwRenamedSig_OI_trn_rd; + wire [3 : 3] NlwRenamedSignal_trn_rrem_n; + wire [15 : 15] NlwRenamedSignal_cfg_lcommand; + wire [6 : 0] trn_rbar_hit_n_5059; + wire [7 : 0] trn_rfc_nph_av_5060; + wire [11 : 0] trn_rfc_npd_av_5061; + wire [7 : 0] trn_rfc_ph_av_5062; + wire [11 : 0] trn_rfc_pd_av_5063; + wire [6 : 0] trn_rfc_cplh_av_5064; + wire [7 : 7] NlwRenamedSig_OI_trn_rfc_cplh_av; + wire [10 : 0] trn_rfc_cpld_av_5065; + wire [11 : 11] NlwRenamedSig_OI_trn_rfc_cpld_av; + wire [31 : 0] cfg_do_5066; + wire [31 : 0] cfg_di_5067; + wire [3 : 0] cfg_byte_en_n_5068; + wire [9 : 0] cfg_dwaddr_5069; + wire [47 : 0] cfg_err_tlp_cpl_header_5070; + wire [1 : 0] cfg_pcie_link_state_n_5071; + wire [7 : 0] NlwRenamedSig_OI_cfg_bus_number; + wire [4 : 0] NlwRenamedSig_OI_cfg_device_number; + wire [14 : 0] NlwRenamedSig_OI_cfg_dcommand; + wire [1023 : 0] cfg_cfg_5072; + wire [0 : 0] com_llm_llm_rx_top_llm_rx_dllp_crc_rx_dllp_d; + wire [0 : 0] plm_sym_reg_count; + wire [0 : 0] com_llm_llm_tx_top_llmx08_tx_tlp_komp_rem_pipe_DOUT; + wire [3 : 3] com_llm_llm_tx_top_llmx08_tx_tlp_komp_rem_pipe; + wire [0 : 0] com_llm_llm_tx_top_llmx08_tx_tlp_komp_eof_n_pipe_DOUT; + wire [4 : 4] com_llm_llm_tx_top_llmx08_tx_tlp_komp_eof_n_pipe; + wire [6 : 0] com_lnk_rd; + wire [31 : 0] com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crc32_d64_feedback; + wire [31 : 0] com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q; + wire [63 : 0] data_in_q; + wire [0 : 0] plm_tsi0_reg_dec1_DOUT; + wire [4 : 1] plm_tsi0_reg_dec1; + wire [0 : 0] plm_tsi0_reg_dec8_DOUT; + wire [0 : 0] plm_tsi0_reg_dec8_0_DOUT; + wire [0 : 0] plm_tsi0_reg_dec7_0_DOUT; + wire [0 : 0] plm_tsi0_reg_dec7_DOUT; + wire [0 : 0] plm_tsi0_reg_dec5_DOUT; + wire [12 : 12] plm_tsi0_reg_dec5; + wire [0 : 0] plm_tsi0_reg_dec6_DOUT; + wire [5 : 5] plm_tsi0_reg_dec6; + wire [0 : 0] plm_tsi0_reg_dec1_2_DOUT; + wire [0 : 0] plm_tsi0_reg_dec1_1_DOUT; + wire [0 : 0] plm_tsi0_reg_dec1_0_DOUT; + wire [7 : 4] plm_dfm_deframe1_qwfsm_nxt_state; + wire [7 : 7] plm_dfm_deframe1_qwfsm_nxt_state_1; + wire [4 : 0] plm_sym_sym_gen_next_addr; + wire [17 : 17] plm_sym_sym_gen_reg_rom_out_27; + wire [4 : 4] plm_fsm_rl_counter3_loadable_tx_counter_reg_tx_count_6; + wire [7 : 0] plm_rx0_lane_num; + wire [0 : 0] com_llm_llm_rx_top_llm_rx_tlp_crc_rx_data_q; + wire [1 : 0] plm_dfm_deframe1_dword_sdpstp; + wire [1 : 0] plm_dfm_deframe1_dword_edbedg; + wire [2 : 2] com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_num; + wire [0 : 0] com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_num_2_q; + wire [63 : 0] phy_td; + wire [63 : 0] phy_rd; + wire [1 : 0] plm_frm0_is_k; + wire [7 : 0] plm_reg_tx_link_num; + wire [15 : 0] plm_frm0_char; + wire [0 : 0] plm_link_ctrl; + wire [2 : 0] plm_send_command; + wire [1 : 1] plm_sent_status; + wire [7 : 0] plm_rx0_link_num; + wire [15 : 0] plm_tx0_raw_char; + wire [1 : 0] plm_tx0_raw_char_pass; + wire [1 : 0] plm_tx0_raw_char_is_k; + wire [15 : 0] plm_rx0_raw_dat; + wire [1 : 0] plm_rx0_des_com; + wire [1 : 1] plm_rx0_des_t1n; + wire [1 : 1] plm_rx0_des_t1p; + wire [1 : 1] plm_rx0_des_t2n; + wire [1 : 1] plm_rx0_des_t2p; + wire [1 : 0] plm_rx0_des_sym; + wire [15 : 0] plm_rx0_des_dat; + wire [1 : 0] plm_rx0_des_bad; + wire [1 : 0] plm_rx0_des_pad; + wire [1 : 0] plm_rx0_des_sdp; + wire [1 : 0] plm_rx0_des_skp; + wire [1 : 0] plm_rx0_des_stp; + wire [1 : 0] plm_rx0_des_edb; + wire [1 : 0] plm_rx0_des_edg; + wire [1 : 0] plm_rx0_des_fts; + wire [1 : 0] plm_rx0_des_idl; + wire [0 : 0] plm_reg_t1n_4; + wire [0 : 0] plm_reg_t1p_4; + wire [0 : 0] plm_reg_t2n_4; + wire [0 : 0] plm_reg_t2p_4; + wire [15 : 0] plm_tx0_data; + wire [1 : 0] plm_tx0_char_is_k; + wire [15 : 0] plm_rx0_data; + wire [1 : 0] plm_rx0_not_in_table; + wire [1 : 0] plm_rx0_char_is_k; + wire [1 : 1] plm_v4f_mgt_for_v1_4_cal_inst1_reset_r; + wire [0 : 0] plm_v4f_mgt_for_v1_4_cal_inst0_reset_r; + wire [15 : 0] plm_v4f_mgt_gt1_di; + wire [5 : 1] plm_v4f_mgt_gt1_daddr; + wire [15 : 0] plm_v4f_mgt_gt1_do; + wire [1 : 1] plm_v4f_mgt_loopback1; + wire [15 : 0] plm_v4f_mgt_gt0_di; + wire [5 : 1] plm_v4f_mgt_gt0_daddr; + wire [15 : 0] plm_v4f_mgt_gt0_do; + wire [13 : 1] plm_v4f_mgt_reg_rst_cnt_cry; + wire [1 : 0] plm_v4f_mgt_RXNOTINTABLE_0; + wire [0 : 0] plm_v4f_mgt_un1_reg_plm_rst_n_2_0_a2_2_1; + wire [0 : 0] plm_v4f_mgt_un1_reg_plm_rst_n_2_0_a2_2; + wire [0 : 0] plm_v4f_mgt_un1_reg_plm_rst_n_2_0_1; + wire [18 : 18] plm_v4f_mgt_reg_tee_dlyline; + wire [0 : 0] plm_v4f_mgt_reg_tee_dlyline_DOUT; + wire [0 : 0] plm_v4f_mgt_reg_phase3_0_DOUT; + wire [14 : 0] plm_v4f_mgt_reg_rst_cnt_s; + wire [0 : 0] plm_v4f_mgt_reg_dcm_cnt_i; + wire [3 : 0] plm_v4f_mgt_reg_dcm_cnt; + wire [3 : 0] plm_v4f_mgt_reg_pma_cnt; + wire [0 : 0] plm_v4f_mgt_reg_pma_cnt_i; + wire [0 : 0] plm_v4f_mgt_un1_reg_plm_rst_n_2_i_i; + wire [0 : 0] plm_v4f_mgt_un1_reg_plm_rst_n_2_i; + wire [0 : 0] plm_v4f_mgt_reg_tee_dlyline_tmp_d_array_1; + wire [0 : 0] plm_v4f_mgt_reg_tee_dlyline_tmp_array_1; + wire [0 : 0] plm_v4f_mgt_reg_phase3_0_tmp_d_array_0; + wire [14 : 0] plm_v4f_mgt_reg_rst_cnt; + wire [14 : 0] plm_v4f_mgt_reg_rst_cnt_qxu; + wire [3 : 3] plm_v4f_mgt_lstate_support; + wire [1 : 0] plm_v4f_mgt_rx_disp_err; + wire [1 : 0] plm_v4f_mgt_rx_run_disp; + wire [15 : 0] plm_v4f_mgt_gt11_by1_COMBUSOUT; + wire [15 : 0] plm_v4f_mgt_gt11_by1_COMBUSOUT_BLK2; + wire [1 : 1] plm_v4f_mgt_for_v1_4_cal_inst0_sd_wr_wreg_9_i_i_m2; + wire [7 : 7] plm_v4f_mgt_for_v1_4_cal_inst0_sd_next_state_0_i_a2_0_a3; + wire [15 : 0] plm_v4f_mgt_for_v1_4_cal_inst0_sd_wr_wreg; + wire [3 : 3] plm_v4f_mgt_for_v1_4_cal_inst0_cb_state_4; + wire [3 : 1] plm_v4f_mgt_for_v1_4_cal_inst0_cb_state; + wire [15 : 0] plm_v4f_mgt_for_v1_4_cal_inst0_gt_do_r_4_i_m2_0_a3; + wire [3 : 2] plm_v4f_mgt_for_v1_4_cal_inst0_cb_state_i; + wire [1 : 1] plm_v4f_mgt_for_v1_4_cal_inst0_GT_DADDR_5_i_i_a3; + wire [1 : 1] plm_v4f_mgt_for_v1_4_cal_inst0_cb_state_4_i_o2_0; + wire [12 : 12] plm_v4f_mgt_for_v1_4_cal_inst1_sd_wr_wreg_9_0_0_a3_0; + wire [0 : 0] plm_v4f_mgt_for_v1_4_cal_inst1_sd_next_state; + wire [15 : 0] plm_v4f_mgt_for_v1_4_cal_inst1_sd_wr_wreg; + wire [3 : 3] plm_v4f_mgt_for_v1_4_cal_inst1_cb_state_4_i_i_a3; + wire [3 : 1] plm_v4f_mgt_for_v1_4_cal_inst1_cb_state; + wire [15 : 0] plm_v4f_mgt_for_v1_4_cal_inst1_gt_do_r_4; + wire [3 : 2] plm_v4f_mgt_for_v1_4_cal_inst1_cb_state_i; + wire [1 : 1] plm_v4f_mgt_for_v1_4_cal_inst1_GT_DADDR_5_i_i_a3_0; + wire [1 : 1] plm_v4f_mgt_for_v1_4_cal_inst1_cb_state_4_i_0_o2_0; + wire [1 : 1] plm_des0_reg_bad_3_i_a7_2_0; + wire [0 : 0] plm_des0_reg_bad_4_i_a7_2_0; + wire [7 : 0] plm_des0_reg_rx_des_dat_14_0_bm; + wire [7 : 0] plm_des0_reg_rx_des_dat_14_0_am; + wire [1 : 1] plm_des0_reg_bad_3_i_1; + wire [0 : 0] plm_des0_reg_bad_4_i_1; + wire [1 : 1] plm_des0_reg_bad_3_i_2; + wire [0 : 0] plm_des0_reg_bad_4_i_2; + wire [1 : 1] plm_des0_reg_skp_3_0_a7_1_0; + wire [0 : 0] plm_des0_reg_sdp_4_0_a7_1_0_0; + wire [1 : 1] plm_des0_reg_stp_3_0_a7_1_0_0; + wire [0 : 0] plm_des0_reg_pad_4_0_a7_1_0_0; + wire [1 : 1] plm_des0_reg_idl_3_2; + wire [0 : 0] plm_des0_reg_idl_4_2; + wire [0 : 0] plm_des0_reg_idl_4_1; + wire [0 : 0] plm_des0_reg_edg_4_0_a7_1_0_0; + wire [1 : 1] plm_des0_reg_idl_3_1; + wire [1 : 1] plm_des0_reg_edg_3_0_a7_1_0_0; + wire [1 : 1] plm_des0_reg_t2p_3_1_0; + wire [1 : 1] plm_des0_reg_t2n_3_0_a7_2_0; + wire [0 : 0] plm_des0_reg_t1p_4_1; + wire [0 : 0] plm_des0_reg_t1p_4_0_a7_2_0; + wire [1 : 1] plm_des0_reg_t2p_3_0_a7_2_0; + wire [1 : 1] plm_des0_reg_t2n_3_1_0; + wire [0 : 0] plm_des0_reg_t1n_4_1; + wire [0 : 0] plm_des0_reg_t1n_4_0_a7_2_0; + wire [15 : 1] plm_des0_one_adv2; + wire [15 : 15] plm_des0_reg_lfsr_two_12_iv_i_0_a2; + wire [12 : 12] plm_des0_reg_lfsr_two_12_0_iv_0_o2; + wire [9 : 9] plm_des0_reg_lfsr_two_12_iv_0_0_o4; + wire [9 : 9] plm_des0_reg_lfsr_two_12_iv_0_0_a4_1; + wire [7 : 0] plm_des0_reg_rx_des_dat_14; + wire [0 : 0] plm_des0_reg_edb_4; + wire [1 : 0] plm_des0_reg_edb; + wire [1 : 1] plm_des0_reg_com_3; + wire [0 : 0] plm_des0_reg_com_4; + wire [1 : 0] plm_des0_reg_bad; + wire [1 : 1] plm_des0_reg_stp_3; + wire [1 : 0] plm_des0_reg_stp; + wire [0 : 0] plm_des0_reg_stp_4; + wire [1 : 1] plm_des0_reg_skp_3; + wire [1 : 0] plm_des0_reg_skp; + wire [0 : 0] plm_des0_reg_skp_4; + wire [1 : 1] plm_des0_reg_sdp_3; + wire [1 : 0] plm_des0_reg_sdp; + wire [0 : 0] plm_des0_reg_sdp_4; + wire [1 : 1] plm_des0_reg_pad_3; + wire [1 : 0] plm_des0_reg_pad; + wire [0 : 0] plm_des0_reg_pad_4; + wire [1 : 1] plm_des0_reg_idl_3; + wire [1 : 0] plm_des0_reg_idl; + wire [0 : 0] plm_des0_reg_idl_4; + wire [1 : 1] plm_des0_reg_fts_3; + wire [1 : 0] plm_des0_reg_fts; + wire [0 : 0] plm_des0_reg_fts_4; + wire [1 : 1] plm_des0_reg_edg_3; + wire [1 : 0] plm_des0_reg_edg; + wire [0 : 0] plm_des0_reg_edg_4; + wire [1 : 1] plm_des0_reg_edb_3; + wire [1 : 0] plm_des0_reg_com; + wire [1 : 1] plm_des0_reg_sym_3; + wire [1 : 0] plm_des0_reg_sym; + wire [0 : 0] plm_des0_reg_sym_4; + wire [1 : 1] plm_des0_reg_t2p_3; + wire [1 : 1] plm_des0_reg_t2p; + wire [1 : 1] plm_des0_reg_t2n_3; + wire [1 : 1] plm_des0_reg_t2n; + wire [1 : 1] plm_des0_reg_t1p_3; + wire [1 : 1] plm_des0_reg_t1p; + wire [1 : 1] plm_des0_reg_t1n_3; + wire [1 : 1] plm_des0_reg_t1n; + wire [1 : 0] plm_des0_reg_nitbl; + wire [15 : 0] plm_des0_reg_data; + wire [15 : 0] plm_des0_reg_dat; + wire [1 : 0] plm_des0_reg_spesh; + wire [1 : 0] plm_des0_reg_kkk; + wire [0 : 0] plm_scr0_reg_com_4_0_a2_1_4; + wire [1 : 1] plm_scr0_reg_com_3_0_a2_1_4; + wire [9 : 9] plm_scr0_one_adv2_1_0; + wire [1 : 1] plm_scr0_reg_com_3_1; + wire [0 : 0] plm_scr0_reg_com_4_1; + wire [7 : 6] plm_scr0_reg_lfsr_one_12_iv_i_a2_0; + wire [14 : 14] plm_scr0_reg_lfsr_two_12_iv_i_0; + wire [1 : 1] plm_scr0_reg_skp_3; + wire [1 : 0] plm_scr0_reg_skp; + wire [0 : 0] plm_scr0_reg_skp_4; + wire [1 : 1] plm_scr0_reg_com_3; + wire [1 : 0] plm_scr0_reg_com; + wire [0 : 0] plm_scr0_reg_com_4; + wire [1 : 0] plm_scr0_reg_dis; + wire [15 : 8] plm_scr0_reg_tx_data_6; + wire [1 : 0] plm_scr0_reg_raw_char_pass; + wire [15 : 0] plm_scr0_reg_raw_char; + wire [15 : 0] plm_scr0_reg_dat; + wire [1 : 0] plm_scr0_reg_raw_char_is_k; + wire [1 : 0] plm_scr0_reg_kkk; + wire [1 : 0] plm_scr0_reg_lfsr_one_12; + wire [6 : 6] plm_tsi0_reg_dec9; + wire [3 : 0] plm_tsi0_reg_ts2_timer; + wire [3 : 0] plm_tsi0_reg_ts1_timer; + wire [15 : 0] plm_tsi0_reg_dly8; + wire [15 : 0] plm_tsi0_do; + wire [15 : 0] plm_tsi0_reg_dly7; + wire [11 : 8] plm_tsi0_reg_dec1_5073; + wire [7 : 0] plm_tsi0_reg_dly9; + wire [12 : 12] plm_tsi0_reg_dec6_5074; + wire [7 : 0] plm_tsi0_reg_lane_num_3; + wire [7 : 0] plm_tsi0_reg_link_num_3; + wire [0 : 0] plm_tsi0_reg_dec7_tmp_d_array_0; + wire [0 : 0] plm_tsi0_reg_dec5_tmp_d_array_0; + wire [0 : 0] plm_tsi0_reg_dec6_tmp_d_array_0; + wire [0 : 0] plm_tsi0_reg_dec8_tmp_d_array_0; + wire [3 : 0] plm_tsi0_reg_ts2_timer_5; + wire [3 : 0] plm_tsi0_reg_ts1_timer_5; + wire [1 : 0] plm_dfm_preh_sdpstp; + wire [1 : 0] plm_dfm_preh_edbedg; + wire [1 : 0] plm_dfm_prel_edbedg; + wire [1 : 0] plm_dfm_prel_sdpstp; + wire [31 : 0] plm_dfm_by1_preh_out; + wire [31 : 0] plm_dfm_by1_prel_out; + wire [31 : 0] plm_dfm_deframe1_dword_out; + wire [2 : 2] plm_dfm_deframe1_reg_push_0_i; + wire [1 : 0] plm_dfm_deframe1_reg_any_bad_6_0_a2_0_a2_0_a2_4; + wire [15 : 0] plm_dfm_deframe1_reg_dat_6; + wire [1 : 0] plm_dfm_deframe1_reg_any_end; + wire [1 : 0] plm_dfm_deframe1_reg_stp_5; + wire [1 : 0] plm_dfm_deframe1_reg_sdp_5; + wire [1 : 0] plm_dfm_deframe1_reg_edg_5; + wire [1 : 0] plm_dfm_deframe1_reg_edb_5; + wire [1 : 0] plm_dfm_deframe1_reg_any_sym; + wire [15 : 0] plm_dfm_deframe1_reg_dat; + wire [15 : 0] plm_dfm_deframe1_reg_delay_dat; + wire [1 : 0] plm_dfm_deframe1_reg_stp; + wire [1 : 0] plm_dfm_deframe1_reg_delay_stp; + wire [1 : 0] plm_dfm_deframe1_reg_sdp; + wire [1 : 0] plm_dfm_deframe1_reg_delay_sdp; + wire [1 : 0] plm_dfm_deframe1_reg_edg; + wire [1 : 0] plm_dfm_deframe1_reg_delay_edg; + wire [1 : 0] plm_dfm_deframe1_reg_edb; + wire [1 : 0] plm_dfm_deframe1_reg_delay_edb; + wire [1 : 0] plm_dfm_deframe1_reg_any_bad; + wire [1 : 0] plm_dfm_deframe1_reg_any_sta; + wire [1 : 1] plm_dfm_deframe1_dwfsm_ns_fsm_substate_i_i_a3; + wire [0 : 0] plm_dfm_deframe1_dwfsm_ns_fsm_substate_i_i_1; + wire [1 : 0] plm_dfm_deframe1_dwfsm_reg_fsm_substate; + wire [1 : 0] plm_dfm_deframe1_dwfsm_reg_fsm_last_substate; + wire [3 : 0] plm_dfm_deframe1_dwbuf_reg_wp3_4; + wire [3 : 0] plm_dfm_deframe1_dwbuf_reg_wp3; + wire [3 : 0] plm_dfm_deframe1_dwbuf_reg_wp0_4; + wire [3 : 0] plm_dfm_deframe1_dwbuf_reg_wp0; + wire [3 : 0] plm_dfm_deframe1_dwbuf_reg_rp_4; + wire [3 : 0] plm_dfm_deframe1_dwbuf_reg_rp; + wire [3 : 0] plm_dfm_deframe1_dwbuf_reg_cnt; + wire [3 : 0] plm_dfm_deframe1_dwbuf_reg_wp2_4; + wire [3 : 0] plm_dfm_deframe1_dwbuf_reg_wp2; + wire [3 : 0] plm_dfm_deframe1_dwbuf_reg_wp1_4; + wire [3 : 0] plm_dfm_deframe1_dwbuf_reg_wp1; + wire [1 : 0] plm_dfm_deframe1_dwbuf_dpo_edbedg; + wire [31 : 0] plm_dfm_deframe1_dwbuf_dpo_out; + wire [1 : 0] plm_dfm_deframe1_dwbuf_dpo_sdpstp; + wire [1 : 1] plm_dfm_deframe1_qwfsm_reg_by1_preh_edbedg_cnst; + wire [1 : 0] plm_dfm_deframe1_qwfsm_reg_by1_preh_sdpstp_6; + wire [31 : 8] plm_dfm_deframe1_qwfsm_reg_by1_preh_out_6; + wire [1 : 0] plm_dfm_deframe1_qwfsm_reg_by1_preh_edbedg_8; + wire [1 : 0] plm_dfm_deframe1_qwfsm_nxt_state_5075; + wire [5 : 2] plm_dfm_deframe1_qwfsm_reg_state; + wire [1 : 0] plm_dfm_deframe1_qwfsm_nxt_state_i_1; + wire [2 : 0] plm_sym_reg_sym_gen_sel; + wire [2 : 2] plm_sym_reg_sym_gen_sel_1; + wire [0 : 0] plm_sym_un1_reg_tx0_raw_char_pass_f1_0; + wire [0 : 0] plm_sym_reg_tx0_raw_char_8_i_i_0_1; + wire [1 : 0] plm_sym_sym_pass; + wire [1 : 0] plm_sym_sym_is_k; + wire [9 : 9] plm_sym_reg_tx0_raw_char_8_0_0_0_0; + wire [2 : 0] plm_sym_sym_bypass; + wire [7 : 7] plm_sym_reg_tx0_raw_char_8_3_i_i_0; + wire [1 : 1] plm_sym_reg_tx0_raw_char_is_k_8_i_0_0_0; + wire [4 : 4] plm_sym_sent_status; + wire [3 : 0] plm_sym_reg_outstanding_ccs; + wire [11 : 1] plm_sym_reg_count_5076; + wire [25 : 25] plm_sym_sym_gen_reg_rom_out_27_0_0; + wire [5 : 0] plm_sym_sym_gen_reg_rom_out; + wire [27 : 27] plm_sym_sym_gen_reg_rom_out_27_0_a3; + wire [63 : 0] plm_frm_reg_d0_td; + wire [63 : 0] plm_frm_reg_d1_td; + wire [63 : 0] plm_frm_reg_d2_td; + wire [1 : 0] plm_frm_by1_frm0_is_k; + wire [7 : 0] plm_frm_frame1_reg_by1_frm0_char_2_0_bm; + wire [7 : 0] plm_frm_frame1_reg_by1_frm0_char_2_0_am; + wire [1 : 0] plm_frm_frame1_by1_frm0_is_k_3_0_bm; + wire [1 : 0] plm_frm_frame1_by1_frm0_is_k_3_0_am; + wire [14 : 14] plm_frm_frame1_reg_by1_frm0_char_2_bm; + wire [14 : 14] plm_frm_frame1_reg_by1_frm0_char_2_am; + wire [9 : 9] plm_frm_frame1_reg_by1_frm0_char_1_bm; + wire [9 : 9] plm_frm_frame1_reg_by1_frm0_char_1_am; + wire [1 : 0] plm_frm_frame1_reg_wd_sel_5; + wire [1 : 0] plm_frm_frame1_reg_wd_sel; + wire [10 : 10] plm_fsm_reg_tx_count_6_0; + wire [3 : 3] plm_fsm_reg_state_141_0_0_0_2_iv_i_0_o3_1; + wire [3 : 3] plm_fsm_reg_state_141_0_0_0_2_iv_i_0_a3_1_1; + wire [0 : 0] plm_fsm_reg_state_141_0_0_0_1_iv_4; + wire [3 : 3] plm_fsm_reg_state_141_0_0_0_2_iv_i_0_o3_3; + wire [18 : 18] plm_fsm_reg_state_141_0_0_0_0_0; + wire [0 : 0] plm_fsm_reg_state_141_0_0_0_1_iv_6; + wire [0 : 0] plm_fsm_reg_state_141_0_0_0_1_iv_2; + wire [0 : 0] plm_fsm_reg_state_141_0_0_0_1_iv_11; + wire [0 : 0] plm_fsm_reg_state_141_0_0_0_1_iv_10; + wire [8 : 8] plm_fsm_reg_state_141_0_0_0_1_iv_0_0_0_1; + wire [8 : 8] plm_fsm_reg_state_141_0_0_0_1_iv_0_0_0_o3_1; + wire [7 : 7] plm_fsm_reg_state_141_0_0_0_1_iv_i_0_0_0; + wire [3 : 3] plm_fsm_reg_state_141_0_0_0_2_iv_i_0_4; + wire [3 : 3] plm_fsm_reg_state_141_0_0_0_2_iv_i_0_2; + wire [3 : 3] plm_fsm_reg_state_141_0_0_0_2_iv_i_0_0; + wire [0 : 0] plm_fsm_reg_state_141_0_0_0_1_iv_13; + wire [15 : 15] plm_fsm_reg_state_141_0_0_0_0_iv_i_0_0_a4_0_0; + wire [10 : 10] plm_fsm_reg_state_141_0_0_0_0_iv_i_0_a4_0_0; + wire [9 : 9] plm_fsm_reg_state_141_0_0_0_1_iv_i_i_i_0; + wire [0 : 0] plm_fsm_reg_state_141_0_0_0_1_iv_19; + wire [0 : 0] plm_fsm_reg_state_141_0_0_0_1_iv_19_1; + wire [0 : 0] plm_fsm_reg_state_141_0_0_0_1_iv_15; + wire [0 : 0] plm_fsm_reg_state_141_0_0_0_1_iv_3; + wire [0 : 0] plm_fsm_reg_state_141_0_0_0_1_iv_14; + wire [0 : 0] plm_fsm_reg_state_141_0_0_0_1_iv_14_1; + wire [0 : 0] plm_fsm_reg_state_141_0_0_0_1_iv_9; + wire [8 : 0] plm_fsm_reg_rx0_old; + wire [8 : 0] plm_fsm_reg_xl_rx0_old; + wire [7 : 0] plm_fsm_reg_tx_link_num_14; + wire [21 : 0] plm_fsm_dq_timer_reg_count_cry; + wire [22 : 0] plm_fsm_dq_timer_reg_count_s; + wire [22 : 0] plm_fsm_dq_timer_reg_count_qxu; + wire [22 : 0] plm_fsm_dq_timer_reg_count; + wire [21 : 0] plm_fsm_pa_timer_reg_count_cry; + wire [22 : 0] plm_fsm_pa_timer_reg_count_s; + wire [22 : 0] plm_fsm_pa_timer_reg_count_qxu; + wire [22 : 0] plm_fsm_pa_timer_reg_count; + wire [6 : 0] plm_fsm_pa_counter0_reg_rx_count_cry; + wire [10 : 0] plm_fsm_pa_counter0_reg_tx_count_cry; + wire [11 : 0] plm_fsm_pa_counter0_reg_tx_count_s; + wire [7 : 0] plm_fsm_pa_counter0_reg_rx_count_s; + wire [7 : 0] plm_fsm_pa_counter0_reg_rx_count_qxu; + wire [7 : 0] plm_fsm_pa_counter0_reg_rx_count; + wire [11 : 0] plm_fsm_pa_counter0_reg_tx_count_qxu; + wire [11 : 0] plm_fsm_pa_counter0_reg_tx_count; + wire [10 : 0] plm_fsm_pa_counter1_reg_tx_count_cry; + wire [11 : 0] plm_fsm_pa_counter1_reg_tx_count_s; + wire [3 : 3] plm_fsm_pa_counter1_reg_rx_count; + wire [11 : 0] plm_fsm_pa_counter1_reg_tx_count_qxu; + wire [11 : 0] plm_fsm_pa_counter1_reg_tx_count; + wire [10 : 0] plm_fsm_pa_counter2_reg_tx_count_cry; + wire [11 : 0] plm_fsm_pa_counter2_reg_tx_count_s; + wire [3 : 3] plm_fsm_pa_counter2_reg_rx_count; + wire [11 : 0] plm_fsm_pa_counter2_reg_tx_count_qxu; + wire [11 : 0] plm_fsm_pa_counter2_reg_tx_count; + wire [10 : 0] plm_fsm_pa_counter3_reg_tx_count_cry; + wire [11 : 0] plm_fsm_pa_counter3_reg_tx_count_s; + wire [3 : 3] plm_fsm_pa_counter3_reg_rx_count; + wire [11 : 0] plm_fsm_pa_counter3_reg_tx_count_qxu; + wire [11 : 0] plm_fsm_pa_counter3_reg_tx_count; + wire [21 : 0] plm_fsm_pc_timer_reg_count_cry; + wire [22 : 0] plm_fsm_pc_timer_reg_count_s; + wire [22 : 0] plm_fsm_pc_timer_reg_count_qxu; + wire [22 : 0] plm_fsm_pc_timer_reg_count; + wire [6 : 0] plm_fsm_pc_counter0_reg_rx_count_cry; + wire [6 : 0] plm_fsm_pc_counter0_reg_tx_count_cry; + wire [7 : 0] plm_fsm_pc_counter0_reg_tx_count_s; + wire [7 : 0] plm_fsm_pc_counter0_reg_rx_count_s; + wire [7 : 0] plm_fsm_pc_counter0_reg_rx_count_qxu; + wire [7 : 0] plm_fsm_pc_counter0_reg_rx_count; + wire [7 : 0] plm_fsm_pc_counter0_reg_tx_count_qxu; + wire [7 : 0] plm_fsm_pc_counter0_reg_tx_count; + wire [6 : 0] plm_fsm_pc_counter1_reg_tx_count_cry; + wire [7 : 0] plm_fsm_pc_counter1_reg_tx_count_s; + wire [3 : 3] plm_fsm_pc_counter1_reg_rx_count; + wire [7 : 0] plm_fsm_pc_counter1_reg_tx_count_qxu; + wire [7 : 0] plm_fsm_pc_counter1_reg_tx_count; + wire [6 : 0] plm_fsm_pc_counter2_reg_tx_count_cry; + wire [7 : 0] plm_fsm_pc_counter2_reg_tx_count_s; + wire [3 : 3] plm_fsm_pc_counter2_reg_rx_count; + wire [7 : 0] plm_fsm_pc_counter2_reg_tx_count_qxu; + wire [7 : 0] plm_fsm_pc_counter2_reg_tx_count; + wire [6 : 0] plm_fsm_pc_counter3_reg_tx_count_cry; + wire [7 : 0] plm_fsm_pc_counter3_reg_tx_count_s; + wire [3 : 3] plm_fsm_pc_counter3_reg_rx_count; + wire [7 : 0] plm_fsm_pc_counter3_reg_tx_count_qxu; + wire [7 : 0] plm_fsm_pc_counter3_reg_tx_count; + wire [21 : 0] plm_fsm_cls_timer_reg_count_cry; + wire [22 : 0] plm_fsm_cls_timer_reg_count_s; + wire [22 : 0] plm_fsm_cls_timer_reg_count_qxu; + wire [22 : 0] plm_fsm_cls_timer_reg_count; + wire [21 : 0] plm_fsm_cla_timer_reg_count_cry; + wire [21 : 18] plm_fsm_cla_timer_count; + wire [22 : 0] plm_fsm_cla_timer_reg_count_s; + wire [22 : 0] plm_fsm_cla_timer_reg_count_qxu; + wire [22 : 0] plm_fsm_cla_timer_reg_count; + wire [21 : 0] plm_fsm_clw_timer_reg_count_cry; + wire [22 : 0] plm_fsm_clw_timer_reg_count_s; + wire [22 : 0] plm_fsm_clw_timer_reg_count_qxu; + wire [22 : 0] plm_fsm_clw_timer_reg_count; + wire [21 : 0] plm_fsm_cc_timer_reg_count_cry; + wire [22 : 0] plm_fsm_cc_timer_reg_count_s; + wire [22 : 0] plm_fsm_cc_timer_reg_count_qxu; + wire [22 : 0] plm_fsm_cc_timer_reg_count; + wire [6 : 0] plm_fsm_cc_counter0_reg_rx_count_cry; + wire [6 : 0] plm_fsm_cc_counter0_reg_tx_count_cry; + wire [7 : 0] plm_fsm_cc_counter0_reg_tx_count_s; + wire [7 : 0] plm_fsm_cc_counter0_reg_rx_count_s; + wire [7 : 0] plm_fsm_cc_counter0_reg_rx_count_qxu; + wire [7 : 0] plm_fsm_cc_counter0_reg_rx_count; + wire [7 : 0] plm_fsm_cc_counter0_reg_tx_count_qxu; + wire [7 : 0] plm_fsm_cc_counter0_reg_tx_count; + wire [21 : 0] plm_fsm_ci_timer_reg_count_cry; + wire [20 : 18] plm_fsm_ci_timer_count; + wire [22 : 0] plm_fsm_ci_timer_reg_count_s; + wire [22 : 0] plm_fsm_ci_timer_reg_count_qxu; + wire [22 : 0] plm_fsm_ci_timer_reg_count; + wire [6 : 0] plm_fsm_ci_counter0_reg_rx_count_cry; + wire [6 : 0] plm_fsm_ci_counter0_reg_tx_count_cry; + wire [7 : 0] plm_fsm_ci_counter0_reg_tx_count_s; + wire [7 : 0] plm_fsm_ci_counter0_reg_rx_count_s; + wire [7 : 0] plm_fsm_ci_counter0_reg_rx_count_qxu; + wire [7 : 0] plm_fsm_ci_counter0_reg_rx_count; + wire [7 : 0] plm_fsm_ci_counter0_reg_tx_count_qxu; + wire [7 : 0] plm_fsm_ci_counter0_reg_tx_count; + wire [6 : 0] plm_fsm_ci_counter1_reg_tx_count_cry; + wire [7 : 0] plm_fsm_ci_counter1_reg_tx_count_s; + wire [2 : 2] plm_fsm_ci_counter1_reg_rx_count; + wire [7 : 0] plm_fsm_ci_counter1_reg_tx_count_qxu; + wire [7 : 0] plm_fsm_ci_counter1_reg_tx_count; + wire [6 : 0] plm_fsm_ci_counter2_reg_tx_count_cry; + wire [7 : 0] plm_fsm_ci_counter2_reg_tx_count_s; + wire [2 : 2] plm_fsm_ci_counter2_reg_rx_count; + wire [7 : 0] plm_fsm_ci_counter2_reg_tx_count_qxu; + wire [7 : 0] plm_fsm_ci_counter2_reg_tx_count; + wire [6 : 0] plm_fsm_ci_counter3_reg_tx_count_cry; + wire [7 : 0] plm_fsm_ci_counter3_reg_tx_count_s; + wire [2 : 2] plm_fsm_ci_counter3_reg_rx_count; + wire [7 : 0] plm_fsm_ci_counter3_reg_tx_count_qxu; + wire [7 : 0] plm_fsm_ci_counter3_reg_tx_count; + wire [21 : 0] plm_fsm_rl_timer_reg_count_cry; + wire [22 : 0] plm_fsm_rl_timer_reg_count_s; + wire [22 : 0] plm_fsm_rl_timer_reg_count_qxu; + wire [22 : 0] plm_fsm_rl_timer_reg_count; + wire [6 : 0] plm_fsm_rl_counterx_reg_rx_count_cry; + wire [10 : 0] plm_fsm_rl_counterx_reg_tx_count_cry; + wire [11 : 0] plm_fsm_rl_counterx_reg_tx_count_s; + wire [7 : 0] plm_fsm_rl_counterx_reg_rx_count_s; + wire [7 : 0] plm_fsm_rl_counterx_reg_rx_count_qxu; + wire [7 : 0] plm_fsm_rl_counterx_reg_rx_count; + wire [11 : 0] plm_fsm_rl_counterx_reg_tx_count_qxu; + wire [11 : 0] plm_fsm_rl_counterx_reg_tx_count; + wire [6 : 0] plm_fsm_rl_counter0_reg_rx_count_cry; + wire [7 : 0] plm_fsm_rl_counter0_reg_rx_count_s; + wire [7 : 0] plm_fsm_rl_counter0_reg_rx_count_qxu; + wire [7 : 0] plm_fsm_rl_counter0_reg_rx_count; + wire [3 : 3] plm_fsm_rl_counter1_reg_rx_count; + wire [3 : 3] plm_fsm_rl_counter2_reg_rx_count; + wire [3 : 3] plm_fsm_rl_counter3_reg_rx_count; + wire [21 : 0] plm_fsm_rc_timer_reg_count_cry; + wire [22 : 0] plm_fsm_rc_timer_reg_count_s; + wire [22 : 0] plm_fsm_rc_timer_reg_count_qxu; + wire [22 : 0] plm_fsm_rc_timer_reg_count; + wire [6 : 0] plm_fsm_rc_counter_ts1_0_reg_rx_count_cry; + wire [6 : 0] plm_fsm_rc_counter_ts1_0_reg_tx_count_cry; + wire [7 : 0] plm_fsm_rc_counter_ts1_0_reg_tx_count_s; + wire [7 : 0] plm_fsm_rc_counter_ts1_0_reg_rx_count_s; + wire [7 : 0] plm_fsm_rc_counter_ts1_0_reg_rx_count_qxu; + wire [7 : 0] plm_fsm_rc_counter_ts1_0_reg_rx_count; + wire [7 : 0] plm_fsm_rc_counter_ts1_0_reg_tx_count_qxu; + wire [7 : 0] plm_fsm_rc_counter_ts1_0_reg_tx_count; + wire [6 : 0] plm_fsm_rc_counter_ts2_0_reg_rx_count_cry; + wire [6 : 0] plm_fsm_rc_counter_ts2_0_reg_tx_count_cry; + wire [7 : 0] plm_fsm_rc_counter_ts2_0_reg_tx_count_s; + wire [7 : 0] plm_fsm_rc_counter_ts2_0_reg_rx_count_s; + wire [7 : 0] plm_fsm_rc_counter_ts2_0_reg_rx_count_qxu; + wire [7 : 0] plm_fsm_rc_counter_ts2_0_reg_rx_count; + wire [7 : 0] plm_fsm_rc_counter_ts2_0_reg_tx_count_qxu; + wire [7 : 0] plm_fsm_rc_counter_ts2_0_reg_tx_count; + wire [21 : 0] plm_fsm_ri_timer_reg_count_cry; + wire [22 : 0] plm_fsm_ri_timer_reg_count_s; + wire [22 : 0] plm_fsm_ri_timer_reg_count_qxu; + wire [22 : 0] plm_fsm_ri_timer_reg_count; + wire [6 : 0] plm_fsm_ri_counter0_reg_rx_count_cry; + wire [6 : 0] plm_fsm_ri_counter0_reg_tx_count_cry; + wire [7 : 0] plm_fsm_ri_counter0_reg_tx_count_s; + wire [7 : 0] plm_fsm_ri_counter0_reg_rx_count_s; + wire [7 : 0] plm_fsm_ri_counter0_reg_rx_count_qxu; + wire [7 : 0] plm_fsm_ri_counter0_reg_rx_count; + wire [7 : 0] plm_fsm_ri_counter0_reg_tx_count_qxu; + wire [7 : 0] plm_fsm_ri_counter0_reg_tx_count; + wire [6 : 0] plm_fsm_ri_counter1_reg_tx_count_cry; + wire [7 : 0] plm_fsm_ri_counter1_reg_tx_count_s; + wire [2 : 2] plm_fsm_ri_counter1_reg_rx_count; + wire [7 : 0] plm_fsm_ri_counter1_reg_tx_count_qxu; + wire [7 : 0] plm_fsm_ri_counter1_reg_tx_count; + wire [6 : 0] plm_fsm_ri_counter2_reg_tx_count_cry; + wire [7 : 0] plm_fsm_ri_counter2_reg_tx_count_s; + wire [2 : 2] plm_fsm_ri_counter2_reg_rx_count; + wire [7 : 0] plm_fsm_ri_counter2_reg_tx_count_qxu; + wire [7 : 0] plm_fsm_ri_counter2_reg_tx_count; + wire [6 : 0] plm_fsm_ri_counter3_reg_tx_count_cry; + wire [7 : 0] plm_fsm_ri_counter3_reg_tx_count_s; + wire [2 : 2] plm_fsm_ri_counter3_reg_rx_count; + wire [7 : 0] plm_fsm_ri_counter3_reg_tx_count_qxu; + wire [7 : 0] plm_fsm_ri_counter3_reg_tx_count; + wire [21 : 0] plm_fsm_hr_timer_reg_count_cry; + wire [22 : 0] plm_fsm_hr_timer_reg_count_s; + wire [22 : 0] plm_fsm_hr_timer_reg_count_qxu; + wire [22 : 0] plm_fsm_hr_timer_reg_count; + wire [21 : 0] plm_fsm_xl_cls_timer_reg_count_cry; + wire [22 : 0] plm_fsm_xl_cls_timer_reg_count_s; + wire [22 : 0] plm_fsm_xl_cls_timer_reg_count_qxu; + wire [22 : 0] plm_fsm_xl_cls_timer_reg_count; + wire [21 : 0] plm_fsm_xl_cla_timer_reg_count_cry; + wire [22 : 0] plm_fsm_xl_cla_timer_reg_count_s; + wire [22 : 0] plm_fsm_xl_cla_timer_reg_count_qxu; + wire [22 : 0] plm_fsm_xl_cla_timer_reg_count; + wire [21 : 0] plm_fsm_xl_clw_timer_reg_count_cry; + wire [22 : 0] plm_fsm_xl_clw_timer_reg_count_s; + wire [22 : 0] plm_fsm_xl_clw_timer_reg_count_qxu; + wire [22 : 0] plm_fsm_xl_clw_timer_reg_count; + wire [60 : 60] com_cmmt_td_0_i_m2_i_m2_i_m2_i_m3_0; + wire [47 : 0] com_cmmt_err_tlp_hdr; + wire [6 : 0] com_cmmt_rbar_hit; + wire [9 : 0] com_cmmt_rpm_set_slot_pwr_data; + wire [63 : 4] com_cmmt_raddr; + wire [17 : 17] com_st_pm_i; + wire [13 : 13] com_st_pm; + wire [11 : 0] com_lnk_tfc_data; + wire [3 : 0] com_lnk_tfc_type; + wire [7 : 0] com_lnk_tfc_header; + wire [11 : 0] com_lnk_ttrans_seq; + wire [63 : 0] com_lnk_td; + wire [2 : 1] com_link_status; + wire [0 : 0] com_lnk_trem; + wire [63 : 7] com_lnk_rd_5077; + wire [0 : 0] com_lnk_rrem; + wire [2 : 0] com_lnk_rfc_type; + wire [11 : 0] com_lnk_rfc_data; + wire [0 : 0] com_lnk_rfc_vc_n; + wire [7 : 0] com_lnk_rfc_header; + wire [11 : 0] com_lnk_tupdate_seq; + wire [0 : 0] com_lnk_ttrans_seq_i; + wire [2 : 2] com_lat_d; + wire [2 : 2] com_lat_d_i; + wire [11 : 1] com_llm_reg_rx_dllp_tsn_m1; + wire [11 : 0] com_llm_reg_rx_dllp_tsn; + wire [31 : 29] com_llm_rx_dllp; + wire [0 : 0] com_llm_link_vc_rcv; + wire [11 : 0] com_llm_reg_next_rcv_tsn; + wire [14 : 0] com_llm_reg_ack_to_val; + wire [11 : 0] com_llm_reg_tx_dllp_tsn; + wire [63 : 0] com_llm_llm_tx_top_tx_tlp_td; + wire [4 : 4] com_llm_llm_tx_top_rem_pipe; + wire [2 : 2] com_llm_llm_tx_top_arb_state; + wire [1 : 0] com_llm_llm_tx_top_llmx08_tx_tlp_komp_eof_n_pipe_5078; + wire [1 : 1] com_llm_llm_tx_top_llmx08_tx_tlp_komp_crcdatawidth; + wire [51 : 50] com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_d_0_bm; + wire [51 : 50] com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_d_0_am; + wire [2 : 0] com_llm_llm_tx_top_llmx08_tx_tlp_komp_sof_n_pipe; + wire [49 : 40] com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_d_i_0; + wire [31 : 0] com_llm_llm_tx_top_llmx08_tx_tlp_komp_sw_early_crc; + wire [0 : 0] com_llm_llm_tx_top_llmx08_tx_tlp_komp_rem_pipe_5079; + wire [0 : 0] com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_tmp_d_array_0; + wire [0 : 0] com_llm_llm_tx_top_llmx08_tx_tlp_komp_rem_pipe_tmp_d_array_0; + wire [63 : 0] com_llm_llm_tx_top_llmx08_tx_tlp_komp_td_mux_i_m3_i_m3_i_m4_0; + wire [31 : 0] com_llm_llm_tx_top_llmx08_tx_tlp_komp_d32_sw; + wire [15 : 0] com_llm_llm_tx_top_llmx08_tx_tlp_komp_d16_sw; + wire [63 : 0] com_llm_llm_tx_top_llmx08_tx_tlp_komp_bat_td; + wire [23 : 0] com_llm_llm_tx_top_llmx08_tx_tlp_komp_sw_early_crc_i; + wire [23 : 0] com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_crc; + wire [2 : 2] com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crcdatawidth_q; + wire [31 : 0] com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4; + wire [4 : 4] com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_new_c16_1_0; + wire [24 : 24] com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_new_c16_1_2; + wire [31 : 31] com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_new_c32_d16; + wire [2 : 2] com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crcdatawidth_qq; + wire [31 : 0] com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_new_c32_d64; + wire [31 : 0] com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_d64_c; + wire [63 : 0] com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6; + wire [0 : 0] com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_1_1; + wire [6 : 6] com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_3; + wire [8 : 8] com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c48_new_c48_1_2; + wire [14 : 0] com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_latency_timer_s; + wire [13 : 0] com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_latency_timer_cry; + wire [0 : 0] com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_dllp_pre_i_i_i_a2; + wire [2 : 0] com_llm_llm_tx_top_llmx08_tx_dllp_jefe_pm_type_q; + wire [14 : 0] com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_latency_timer_qxu; + wire [14 : 0] com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_latency_timer; + wire [3 : 0] com_llm_llm_tx_top_llmx08_tx_dllp_jefe_llm32_fc_fifo_data_count; + wire [2 : 2] com_llm_llm_tx_top_llmx08_tx_packet_packer_next_arb_state_i_i_o3_0; + wire [1 : 1] com_llm_llm_tx_top_llmx08_tx_packet_packer_next_arb_state_i_i_0_a2_1_0; + wire [31 : 0] com_llm_llm_tx_top_llmx08_tx_packet_packer_prev_td; + wire [3 : 3] com_llm_llm_tx_top_llmx08_tx_packet_packer_new_c32_1_3; + wire [2 : 2] com_llm_llm_tx_top_llmx08_tx_packet_packer_arb_state_i; + wire [23 : 8] com_llm_llm_tx_top_llmx08_tx_packet_packer_current_td; + wire [32 : 32] com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_0_o4; + wire [15 : 15] com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_i_0_i; + wire [7 : 0] com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_i_0; + wire [0 : 0] com_llm_llm_tx_top_llmx08_tx_packet_packer_next_arb_state_0_i_1; + wire [0 : 0] com_llm_llm_tx_top_llmx08_tx_packet_packer_next_arb_state_0_i_o3_0; + wire [22 : 22] com_llm_llm_tx_top_llmx08_tx_packet_packer_current_td_0_i_m4_0_1; + wire [12 : 12] com_llm_llm_tx_top_llmx08_tx_packet_packer_llm_rx_crc16_d32_new_c32_1_i_1; + wire [1 : 1] com_llm_llm_tx_top_llmx08_tx_packet_packer_llm_rx_crc16_d32_new_c32_1_2; + wire [11 : 0] com_llm_llm_rx_top_rx_tlp_tsn; + wire [63 : 0] com_llm_llm_rx_top_rx_rd; + wire [2 : 2] com_llm_llm_rx_top_rx_rrem; + wire [28 : 24] com_llm_llm_rx_top_rx_dllp; + wire [20 : 16] com_llm_llm_rx_top_rx_dllp_d_4_i_m2_i_m3_0; + wire [63 : 0] com_llm_llm_rx_top_llm_rx_demux_phy_rd_q_0_; + wire [6 : 0] com_llm_llm_rx_top_llm_rx_dllp_crc_data_tmp; + wire [11 : 1] com_llm_llm_rx_top_llm_rx_dllp_crc_rx_dllp_d_i; + wire [11 : 1] com_llm_llm_rx_top_llm_rx_dllp_crc_RX_DLLP_LOW_M1_2; + wire [15 : 0] com_llm_llm_rx_top_llm_rx_dllp_crc_crc16_d32_nst; + wire [15 : 0] com_llm_llm_rx_top_llm_rx_dllp_crc_crc16_d32_st; + wire [28 : 28] com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q; + wire [15 : 0] com_llm_llm_rx_top_llm_rx_dllp_crc_crc16_ori; + wire [15 : 0] com_llm_llm_rx_top_llm_rx_dllp_crc_un1_crc16_ok_0; + wire [3 : 3] com_llm_llm_rx_top_llm_rx_dllp_crc_llm_rx_crc16_d32_st_new_c32_1_1_0; + wire [3 : 3] com_llm_llm_rx_top_llm_rx_dllp_crc_llm_rx_crc16_d32_nst_new_c32_1_1_2; + wire [4 : 3] com_llm_llm_rx_top_llm_rx_dllp_crc_llm_rx_crc16_d32_nst_new_c32_1_i_1; + wire [14 : 0] com_llm_llm_rx_top_llm_rx_tlp_crc_data_tmp_0; + wire [14 : 0] com_llm_llm_rx_top_llm_rx_tlp_crc_data_tmp; + wire [63 : 32] com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sh; + wire [31 : 0] com_llm_llm_rx_top_llm_rx_tlp_crc_new_c64; + wire [31 : 0] com_llm_llm_rx_top_llm_rx_tlp_crc_new_c16; + wire [31 : 0] com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d16; + wire [7 : 1] com_llm_llm_rx_top_llm_rx_tlp_crc_rx_data_q_5080; + wire [63 : 0] com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl; + wire [11 : 0] com_llm_llm_rx_top_llm_rx_tlp_crc_rx_tlp_tsn_d; + wire [11 : 0] com_llm_llm_rx_top_llm_rx_tlp_crc_rx_tlp_tsn_dd_5_i_m3_i_m3_0; + wire [11 : 0] com_llm_llm_rx_top_llm_rx_tlp_crc_rx_tlp_tsn_dd; + wire [3 : 3] com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d16_new_c16_1_1_0; + wire [2 : 2] com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_3_1; + wire [12 : 12] com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_1_2; + wire [1 : 1] com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_1_1; + wire [2 : 2] com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_3; + wire [5 : 5] com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_9; + wire [25 : 25] com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_7; + wire [15 : 15] com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_4_1; + wire [28 : 28] com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_5_1; + wire [10 : 10] com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_1_0; + wire [4 : 0] com_llm_llm_rx_top_llm_rx_tlp_sm_data_tmp; + wire [11 : 11] com_llm_llm_rx_top_llm_rx_tlp_sm_tlp_diff_tsn; + wire [0 : 0] com_llm_llm_common_link_status_i; + wire [3 : 3] com_llm_llm_common_val_2; + wire [14 : 0] com_llm_llm_common_reg_replay_to_val; + wire [14 : 9] com_llm_llm_common_reg_replay_to_val_3; + wire [14 : 13] com_llm_llm_common_reg_ack_to_val_3_i_m2_i_m3_0_a4; + wire [10 : 10] com_llm_llm_common_reg_ack_to_val_3_i_m2_0_0_a4; + wire [9 : 9] com_llm_llm_common_reg_ack_to_val_3_i_m2_0_0_a4_0; + wire [1 : 1] com_llm_llm_common_reg_ack_to_val_3_0_i_m2_i_m3_i_m3; + wire [1 : 1] com_llm_llm_common_llm_link_sm_llm_link_main_sm_ns_link_i_i_0_0_0_0; + wire [2 : 2] com_llm_llm_common_llm_link_sm_llm_link_main_sm_ns_link_i_0_0_i_2; + wire [2 : 2] com_llm_llm_common_llm_link_sm_llm_link_main_sm_ns_link_i_0_0_i_2_1; + wire [4 : 4] com_llm_llm_common_llm_link_sm_llm_link_main_sm_link_status; + wire [4 : 0] com_llm_llm_common_llm_common_reg_data_tmp_2; + wire [4 : 0] com_llm_llm_common_llm_common_reg_data_tmp_1; + wire [4 : 0] com_llm_llm_common_llm_common_reg_data_tmp_0; + wire [4 : 0] com_llm_llm_common_llm_common_reg_data_tmp; + wire [11 : 11] com_llm_llm_common_llm_common_reg_result_i_0; + wire [11 : 11] com_llm_llm_common_llm_common_reg_result_i; + wire [11 : 11] com_llm_llm_common_llm_common_reg_ttrans_st_hiwater; + wire [11 : 11] com_llm_llm_common_llm_common_reg_tmp_result; + wire [11 : 1] com_llm_llm_common_llm_common_reg_reg_tx_next_tsn_4; + wire [11 : 0] com_llm_llm_common_llm_common_reg_reg_rx_dllp_tsn_q; + wire [11 : 0] com_llm_llm_common_llm_common_reg_reg_tx_next_tsn; + wire [11 : 0] com_llm_llm_common_llm_common_reg_reg_tx_curr_tsn; + wire [11 : 0] com_llm_llm_common_llm_common_reg_hi_water_mark; + wire [11 : 11] com_llm_llm_common_llm_common_reg_compare_1_result; + wire [11 : 11] com_llm_llm_common_llm_common_reg_compare_2_result; + wire [1 : 1] com_llm_llm_common_llm_common_reg_llm_ack_nak_buf_acknak_state_q_5; + wire [1 : 1] com_llm_llm_common_llm_common_reg_llm_ack_nak_buf_acknak_state_q; + wire [0 : 0] com_llm_llm_common_llm_common_reg_llm_ack_nak_fsm_cs_acknakfsm_5_i_0_0; + wire [1 : 1] com_llm_llm_common_llm_common_reg_llm_ack_nak_fsm_cs_acknakfsm_5; + wire [0 : 0] com_llm_llm_common_llm_common_reg_llm_ack_nak_fsm_acknak_state; + wire [4 : 0] com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_data_tmp_1; + wire [4 : 0] com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_data_tmp_0; + wire [6 : 0] com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_data_tmp; + wire [14 : 0] com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_s; + wire [13 : 1] com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_cry; + wire [1 : 0] com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_num_5081; + wire [0 : 0] com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_num_7_iv_0_m2_0; + wire [14 : 0] com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer; + wire [14 : 0] com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_qxu; + wire [14 : 0] com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_q; + wire [11 : 0] com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_reg_tx_ackd_tsn_q; + wire [10 : 0] com_llm_llm_common_llm_common_reg_llm_next_rcv_tsn_out_cry; + wire [11 : 0] com_llm_llm_common_llm_common_reg_llm_next_rcv_tsn_out_s; + wire [11 : 0] com_llm_llm_common_llm_common_reg_llm_next_rcv_tsn_out_qxu; + wire [0 : 0] com_tlm_u_tlm_tx_queue_state; + wire [11 : 0] com_tlm_u_tlm_tx_am_retry_tsn; + wire [3 : 0] com_tlm_u_tlm_tx_freed_buf; + wire [63 : 0] com_tlm_u_tlm_tx_vc0_d; + wire [3 : 0] com_tlm_u_tlm_tx_ds_buf_num; + wire [3 : 0] com_tlm_u_tlm_tx_vc0_buf_num; + wire [68 : 68] com_tlm_u_tlm_tx_rdata_q_all; + wire [11 : 0] com_tlm_u_tlm_tx_vc0_retry_tsn; + wire [11 : 0] com_tlm_u_tlm_tx_data_src_tsn_cnt_s; + wire [10 : 1] com_tlm_u_tlm_tx_data_src_tsn_cnt_cry; + wire [11 : 0] com_tlm_u_tlm_tx_data_src_lnk_ttrans_seq_o_4_i_m2_0; + wire [11 : 0] com_tlm_u_tlm_tx_data_src_tsn_cnt; + wire [11 : 0] com_tlm_u_tlm_tx_data_src_tsn_cnt_qxu; + wire [4 : 0] com_tlm_u_tlm_tx_ack_mgr_data_tmp_0; + wire [4 : 0] com_tlm_u_tlm_tx_ack_mgr_data_tmp; + wire [11 : 0] com_tlm_u_tlm_tx_ack_mgr_newest_freed_tsn_s; + wire [10 : 1] com_tlm_u_tlm_tx_ack_mgr_newest_freed_tsn_cry; + wire [0 : 0] com_tlm_u_tlm_tx_ack_mgr_un1_fifo_ren_iv_0_a2_0_a4; + wire [8 : 8] com_tlm_u_tlm_tx_ack_mgr_mgr_state_4_0_0_0_a4_0_0; + wire [4 : 4] com_tlm_u_tlm_tx_ack_mgr_mgr_state_4_i_i_0_o3; + wire [0 : 0] com_tlm_u_tlm_tx_ack_mgr_mgr_state_4_iv_0_0_a4_1_0; + wire [0 : 0] com_tlm_u_tlm_tx_ack_mgr_mgr_state_4_iv_0_0_a4_0; + wire [11 : 0] com_tlm_u_tlm_tx_ack_mgr_lnk_rupdate_seq_q; + wire [8 : 8] com_tlm_u_tlm_tx_ack_mgr_mgr_state_4_0_0_0_o3_0; + wire [11 : 0] com_tlm_u_tlm_tx_ack_mgr_newest_freed_tsn_qxu; + wire [11 : 0] com_tlm_u_tlm_tx_ack_mgr_newest_freed_tsn; + wire [11 : 0] com_tlm_u_tlm_tx_ack_mgr_latest_ack_tsn; + wire [11 : 0] com_tlm_u_tlm_tx_ack_mgr_fifo_tsn; + wire [3 : 0] com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_shift_tap; + wire [3 : 0] com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_bkp_data; + wire [3 : 0] com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_raddr_lo; + wire [2 : 0] com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_bkp_raddr_lo_7_i_m2_0; + wire [2 : 0] com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_un1_bkp_raddr_lo_i_m2_0; + wire [3 : 3] com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_bkp_raddr_lo_7_i_i_o3; + wire [3 : 0] com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_raddr_lo_5_i_m2_i_m3_0; + wire [3 : 0] com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_bkp_raddr_lo; + wire [3 : 0] com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_d_o_4_i_m2_i_m3_0; + wire [1 : 0] com_tlm_u_tlm_tx_vc0_cat; + wire [5 : 0] com_tlm_u_tlm_tx_vc0_credits; + wire [11 : 0] com_tlm_u_tlm_tx_vc0_start_retry_tsn; + wire [63 : 0] com_tlm_u_tlm_tx_vc0_trn_d; + wire [3 : 0] com_tlm_u_tlm_tx_vc0_tkn_buf_num; + wire [3 : 0] com_tlm_u_tlm_tx_vc0_start_buf_num; + wire [67 : 67] com_tlm_u_tlm_tx_vc0_rdata_q_all_5; + wire [6 : 0] com_tlm_u_tlm_tx_vc0_buf_pool_raddr_l_s; + wire [5 : 1] com_tlm_u_tlm_tx_vc0_buf_pool_raddr_l_cry; + wire [68 : 0] com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all; + wire [67 : 67] com_tlm_u_tlm_tx_vc0_buf_pool_rdata_q_all; + wire [3 : 0] com_tlm_u_tlm_tx_vc0_buf_pool_raddr_h_0_0; + wire [3 : 0] com_tlm_u_tlm_tx_vc0_buf_pool_waddr_h_0_0; + wire [3 : 0] com_tlm_u_tlm_tx_vc0_buf_pool_waddr_h; + wire [6 : 0] com_tlm_u_tlm_tx_vc0_buf_pool_waddr_l_1; + wire [6 : 0] com_tlm_u_tlm_tx_vc0_buf_pool_waddr_l; + wire [3 : 0] com_tlm_u_tlm_tx_vc0_buf_pool_raddr_h; + wire [11 : 0] com_tlm_u_tlm_tx_vc0_buf_pool_retry_tsn_dd; + wire [6 : 0] com_tlm_u_tlm_tx_vc0_buf_pool_raddr_l; + wire [6 : 0] com_tlm_u_tlm_tx_vc0_buf_pool_raddr_l_qxu; + wire [6 : 0] com_tlm_u_tlm_tx_vc0_trn_len_counter_s; + wire [5 : 0] com_tlm_u_tlm_tx_vc0_trn_len_counter_cry; + wire [32 : 32] com_tlm_u_tlm_tx_vc0_trn_d_o_4_i_i_i_0; + wire [62 : 61] com_tlm_u_tlm_tx_vc0_trn_d_o_4_i_0_0_0; + wire [57 : 57] com_tlm_u_tlm_tx_vc0_trn_d_o_4_i_0_0_a2_1; + wire [12 : 12] com_tlm_u_tlm_tx_vc0_trn_d_o_4_0_0_0_a3; + wire [62 : 62] com_tlm_u_tlm_tx_vc0_trn_usr_d_i; + wire [1 : 0] com_tlm_u_tlm_tx_vc0_trn_pkts_in_trn; + wire [0 : 0] com_tlm_u_tlm_tx_vc0_trn_un1_buf_av_one_1_i_0_0_0_a2; + wire [63 : 0] com_tlm_u_tlm_tx_vc0_trn_usr_d; + wire [6 : 0] com_tlm_u_tlm_tx_vc0_trn_len_counter_qxu; + wire [6 : 0] com_tlm_u_tlm_tx_vc0_trn_len_counter; + wire [0 : 0] com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_usr_cat20_0_a2_0_a2_0_a2_1; + wire [5 : 0] com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_usr_credits_6; + wire [5 : 0] com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_usr_credits; + wire [1 : 0] com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_cat_o_2; + wire [1 : 1] com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_cfg_cat; + wire [5 : 1] com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_credits_o_2; + wire [0 : 0] com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_credits_o_2_i_m2_i_m3_i_m2_i_m3_0; + wire [0 : 0] com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_usr_cat20; + wire [1 : 0] com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_usr_cat; + wire [3 : 0] com_tlm_u_tlm_tx_vc0_token_fifo_fifo_d; + wire [3 : 3] com_tlm_u_tlm_tx_vc0_token_fifo_fifo_d_6_i_o2_i_m2_0; + wire [3 : 0] com_tlm_u_tlm_tx_vc0_token_fifo_token_index; + wire [3 : 0] com_tlm_u_tlm_tx_vc0_token_fifo_t_fifo_raddr_lo; + wire [3 : 0] com_tlm_u_tlm_tx_vc0_token_fifo_t_fifo_shift_tap; + wire [10 : 0] com_tlm_u_tlm_tx_vc0_frm_seq_bq_q; + wire [10 : 0] com_tlm_u_tlm_tx_vc0_frm_seq_bq_d; + wire [10 : 6] com_tlm_u_tlm_tx_vc0_frm_seq_npd_av_i; + wire [10 : 6] com_tlm_u_tlm_tx_vc0_frm_seq_cpld_av_i; + wire [10 : 6] com_tlm_u_tlm_tx_vc0_frm_seq_pd_av_i; + wire [3 : 0] com_tlm_u_tlm_tx_vc0_frm_seq_last_buf_num; + wire [11 : 11] com_tlm_u_tlm_tx_vc0_frm_seq_pd_diff; + wire [1 : 0] com_tlm_u_tlm_tx_vc0_frm_seq_oq_cat_qq; + wire [11 : 11] com_tlm_u_tlm_tx_vc0_frm_seq_npd_diff; + wire [11 : 11] com_tlm_u_tlm_tx_vc0_frm_seq_bnpd_diff; + wire [2 : 0] com_tlm_u_tlm_tx_vc0_frm_seq_sq_cnt; + wire [11 : 11] com_tlm_u_tlm_tx_vc0_frm_seq_cpld_diff; + wire [3 : 0] com_tlm_u_tlm_tx_vc0_frm_seq_sq_q; + wire [11 : 0] com_tlm_u_tlm_tx_vc0_frm_seq_npd_av; + wire [1 : 0] com_tlm_u_tlm_tx_vc0_frm_seq_seq_state; + wire [3 : 1] com_tlm_u_tlm_tx_vc0_frm_seq_queue_state; + wire [12 : 11] com_tlm_u_tlm_tx_vc0_frm_seq_oq_q; + wire [5 : 0] com_tlm_u_tlm_tx_vc0_frm_seq_consumed_credits_4_i_m3_i_m4_i_m3_0; + wire [5 : 0] com_tlm_u_tlm_tx_vc0_frm_seq_consumed_credits; + wire [3 : 0] com_tlm_u_tlm_tx_vc0_frm_seq_sq_d_4_i_m3_i_m4_i_m3_0; + wire [3 : 0] com_tlm_u_tlm_tx_vc0_frm_seq_sq_d; + wire [3 : 0] com_tlm_u_tlm_tx_vc0_frm_seq_start_buf_o_2_i_m2_i_m2_i_m3_0; + wire [3 : 0] com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_raddr_lo; + wire [12 : 0] com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_shift_tap; + wire [12 : 0] com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_d_o_14_0_i_m3_i_m4_i_m3_0; + wire [3 : 0] com_tlm_u_tlm_tx_vc0_frm_seq_bq_fifo_raddr_lo; + wire [10 : 0] com_tlm_u_tlm_tx_vc0_frm_seq_bq_fifo_shift_tap; + wire [3 : 0] com_tlm_u_tlm_tx_vc0_frm_seq_sq_fifo_raddr_lo; + wire [3 : 0] com_tlm_u_tlm_tx_vc0_frm_seq_sq_fifo_shift_tap; + wire [1 : 1] com_tlm_u_tlm_tx_vc0_frm_seq_sq_fifo_un1_ct_o190_0_a2_0_a2_0_a2; + wire [3 : 0] com_tlm_u_tlm_tx_vc0_frm_seq_sq_fifo_d_o_24_0_i_m2_i_m4_0; + wire [7 : 0] com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_PH_s; + wire [6 : 1] com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_PH_cry; + wire [7 : 0] com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_NPH_s; + wire [6 : 1] com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_NPH_cry; + wire [7 : 0] com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_CPLH_s; + wire [6 : 1] com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_CPLH_cry; + wire [11 : 0] com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_cpld_av_o_6; + wire [11 : 0] com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_npd_av_o_6; + wire [11 : 0] com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_pd_av_o_6; + wire [7 : 0] com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_limit_NPH; + wire [7 : 0] com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_limit_PH; + wire [11 : 0] com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_prev_limit_data_q_5_0_0; + wire [7 : 0] com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_limit_CPLH; + wire [7 : 0] com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_prev_limit_header_q_5_0_0; + wire [2 : 0] com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_credits_ok; + wire [11 : 0] com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_av_data_cred_7_i_0_0; + wire [0 : 0] com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_credits_ok_3; + wire [11 : 0] com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_limit_CPLD; + wire [11 : 0] com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_limit_NPD; + wire [11 : 0] com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_limit_PD; + wire [4 : 3] com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_min_data_cred_7; + wire [1 : 0] com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_suspend_cat; + wire [11 : 11] com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_fc_diff_data; + wire [11 : 11] com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_fc_diff_data_q; + wire [7 : 7] com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_fc_diff_header; + wire [7 : 7] com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_fc_diff_header_q; + wire [11 : 0] com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_prev_limit_data_q_5; + wire [1 : 0] com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_cat_q; + wire [7 : 0] com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_prev_limit_header_q_5; + wire [7 : 0] com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_prev_limit_header_q; + wire [11 : 0] com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_prev_limit_data_q; + wire [11 : 0] com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_data_qq; + wire [7 : 0] com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_header_q; + wire [7 : 0] com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_header_qq; + wire [11 : 0] com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_data_q; + wire [10 : 0] com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_CPLD_i; + wire [11 : 0] com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_CPLD; + wire [10 : 0] com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_NPD_i; + wire [11 : 0] com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_NPD; + wire [10 : 0] com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_PD_i; + wire [11 : 0] com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_PD; + wire [7 : 0] com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_PH; + wire [7 : 0] com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_NPH; + wire [7 : 0] com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_CPLH; + wire [7 : 0] com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_CPLH_qxu; + wire [7 : 0] com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_NPH_qxu; + wire [7 : 0] com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_PH_qxu; + wire [10 : 6] com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_pd_av; + wire [10 : 6] com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_cpld_av; + wire [11 : 0] com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_av_data_cred; + wire [5 : 3] com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_min_data_cred; + wire [4 : 0] com_tlm_u_tlm_tx_pm_ctrl_cfg_ct; + wire [63 : 0] com_tlm_u_tlm_rx_ds_d; + wire [6 : 0] com_tlm_u_tlm_rx_ds_bar; + wire [11 : 0] com_tlm_u_tlm_rx_fc_req_npd; + wire [7 : 0] com_tlm_u_tlm_rx_fc_req_nph; + wire [5 : 0] com_tlm_u_tlm_rx_fc_use_data; + wire [11 : 0] com_tlm_u_tlm_rx_fc_req_pd; + wire [7 : 0] com_tlm_u_tlm_rx_fc_req_ph; + wire [0 : 0] com_tlm_u_tlm_rx_vc0_rd_mon_word_ct_8_iv_i_0_0_o4_1; + wire [0 : 0] com_tlm_u_tlm_rx_vc0_rd_mon_word_ct; + wire [0 : 0] com_tlm_u_tlm_rx_vc0_rd_mon_word_ct_8_iv_i_0_0_0; + wire [66 : 64] com_tlm_u_tlm_rx_vc0_fifo_ram_dout; + wire [6 : 0] com_tlm_u_tlm_rx_vc0_fifo_aux_oqr; + wire [7 : 0] com_tlm_u_tlm_rx_vc0_fifo_aux_bqr; + wire [0 : 0] com_tlm_u_tlm_rx_vc0_fifo_un1_data_oqr; + wire [8 : 0] com_tlm_u_tlm_rx_vc0_fifo_aux_in; + wire [8 : 0] com_tlm_u_tlm_rx_vc0_fifo_aux_i_d; + wire [6 : 0] com_tlm_u_tlm_rx_vc0_fifo_trn_rbar_hit; + wire [9 : 0] com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_raddr_s; + wire [8 : 1] com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_raddr_cry; + wire [9 : 0] com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr_s; + wire [8 : 0] com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr_cry; + wire [67 : 67] com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_ram_dout; + wire [9 : 0] com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_vld_ct; + wire [6 : 0] com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un10_vld_ct; + wire [9 : 0] com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr_qxu; + wire [9 : 0] com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr; + wire [6 : 0] com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_pkt_ct; + wire [6 : 0] com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_pkt_ct_m1; + wire [0 : 0] com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un8_pkt_ct_m1_i; + wire [9 : 0] com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr_p1; + wire [9 : 0] com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr_bkp; + wire [9 : 0] com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_raddr; + wire [9 : 0] com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_raddr_qxu; + wire [0 : 0] com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un8_pkt_ct; + wire [44 : 9] com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_shift_in; + wire [44 : 0] com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_shift_tap; + wire [8 : 0] com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_d_o_34_0_1_2; + wire [8 : 0] com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_d_o_34_0_1_1; + wire [8 : 0] com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_d_o_34_0_1_0; + wire [3 : 1] com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_hi_53_0_i_m2_0; + wire [4 : 0] com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_hi; + wire [3 : 0] com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_lo; + wire [7 : 0] com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux; + wire [7 : 0] com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_q; + wire [3 : 0] com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo; + wire [0 : 0] com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_un613_d_o_d; + wire [0 : 0] com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_un597_d_o_d; + wire [0 : 0] com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_un589_d_o_d; + wire [1 : 0] com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_hi_62; + wire [1 : 0] com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_hi; + wire [3 : 0] com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1; + wire [3 : 0] com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_queue_aux_queue_raddr_lo; + wire [7 : 0] com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_queue_aux_queue_shift_tap_m; + wire [7 : 0] com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_queue_aux_queue_shift_tap; + wire [9 : 0] com_tlm_u_tlm_rx_vc0_flow_ctrl_lat_timer_s; + wire [8 : 0] com_tlm_u_tlm_rx_vc0_flow_ctrl_lat_timer_cry; + wire [7 : 7] com_tlm_u_tlm_rx_vc0_flow_ctrl_fc_h_advert_0; + wire [11 : 11] com_tlm_u_tlm_rx_vc0_flow_ctrl_fc_d_advert_0; + wire [7 : 7] com_tlm_u_tlm_rx_vc0_flow_ctrl_fc_h_advert; + wire [11 : 11] com_tlm_u_tlm_rx_vc0_flow_ctrl_fc_d_advert; + wire [9 : 0] com_tlm_u_tlm_rx_vc0_flow_ctrl_lat_timer_qxu; + wire [9 : 0] com_tlm_u_tlm_rx_vc0_flow_ctrl_lat_timer; + wire [1 : 0] com_tlm_u_tlm_rx_vc0_flow_ctrl_lat_prescale; + wire [0 : 0] com_tlm_u_tlm_rx_vc0_flow_ctrl_lat_prescale_i; + wire [7 : 0] com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_h_o_0; + wire [11 : 0] com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_d_o_0; + wire [7 : 0] com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_h_con_s; + wire [6 : 1] com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_h_con_cry; + wire [11 : 0] com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_d_alo; + wire [7 : 0] com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_h_alo; + wire [11 : 0] com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_d_con; + wire [11 : 11] com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_d_advert_1; + wire [7 : 7] com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_h_advert_1; + wire [7 : 0] com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_h_con_qxu; + wire [7 : 0] com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_h_con; + wire [7 : 0] com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_h_o_0; + wire [11 : 0] com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_d_o_0; + wire [7 : 0] com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_h_con_s; + wire [6 : 1] com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_h_con_cry; + wire [11 : 0] com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_d_alo; + wire [7 : 0] com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_h_alo; + wire [11 : 0] com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_d_con; + wire [7 : 0] com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_h_con_qxu; + wire [7 : 0] com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_h_con; + wire [7 : 0] com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_h_con_s; + wire [6 : 1] com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_h_con_cry; + wire [0 : 0] com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_free_h; + wire [0 : 0] com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_free_d; + wire [11 : 0] com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_d_con; + wire [5 : 5] com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_h_o; + wire [11 : 0] com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_req_d_o; + wire [7 : 0] com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_req_h_o; + wire [7 : 0] com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_h_con; + wire [7 : 0] com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_h_con_qxu; + wire [6 : 6] com_tlm_u_tlm_rx_data_snk_cur_fulltype; + wire [2 : 0] com_tlm_u_tlm_rx_data_snk_cur_byte_ct_1dw; + wire [1 : 1] com_tlm_u_tlm_rx_data_snk_sof_q_3; + wire [1 : 1] com_tlm_u_tlm_rx_data_snk_dsc_q_3; + wire [1 : 1] com_tlm_u_tlm_rx_data_snk_eof_nd_q_3; + wire [1 : 0] com_tlm_u_tlm_rx_data_snk_cur_first_be_adj; + wire [0 : 0] com_tlm_u_tlm_rx_data_snk_first_be_missing_0_0; + wire [2 : 1] com_tlm_u_tlm_rx_data_snk_cur_bytes_missing_1; + wire [1 : 0] com_tlm_u_tlm_rx_data_snk_cur_attr; + wire [2 : 0] com_tlm_u_tlm_rx_data_snk_cur_tc; + wire [7 : 0] com_tlm_u_tlm_rx_data_snk_cur_tag; + wire [7 : 0] com_tlm_u_tlm_rx_data_snk_cur_msgcode; + wire [15 : 0] com_tlm_u_tlm_rx_data_snk_cur_req_id; + wire [5 : 0] com_tlm_u_tlm_rx_data_snk_cur_data_credits; + wire [11 : 0] com_tlm_u_tlm_rx_data_snk_cur_byte_ct; + wire [28 : 0] com_tlm_u_tlm_rx_data_snk_cur_cpl_header_fmt; + wire [1 : 0] com_tlm_u_tlm_rx_data_snk_cur_lower_addr_22; + wire [6 : 0] com_tlm_u_tlm_rx_data_snk_cur_lower_addr; + wire [6 : 2] com_tlm_u_tlm_rx_data_snk_lower_addr64_in_q; + wire [6 : 2] com_tlm_u_tlm_rx_data_snk_lower_addr32_in_q; + wire [7 : 5] com_tlm_u_tlm_rx_data_snk_cur_length; + wire [2 : 0] com_tlm_u_tlm_rx_data_snk_cur_bytes_missing; + wire [6 : 0] com_tlm_u_tlm_rx_data_snk_malformed_checks_word_ct_d_i; + wire [6 : 0] com_tlm_u_tlm_rx_data_snk_malformed_checks_word_ct; + wire [4 : 1] com_tlm_u_tlm_rx_data_snk_malformed_checks_cur_fulltype; + wire [2 : 0] com_tlm_u_tlm_rx_data_snk_malformed_checks_msgcode_routing; + wire [7 : 5] com_tlm_u_tlm_rx_data_snk_malformed_checks_max_length; + wire [55 : 55] com_tlm_u_tlm_rx_data_snk_bar_hit_check_raddr_d_i_0_o3; + wire [47 : 4] com_tlm_u_tlm_rx_data_snk_bar_hit_un18_check_raddr_d_0_a2_0_a2; + wire [6 : 0] com_tlm_u_tlm_rx_fc_src_initFC_st; + wire [11 : 0] com_tlm_u_tlm_rx_fc_src_pd; + wire [7 : 0] com_tlm_u_tlm_rx_fc_src_ph; + wire [11 : 0] com_tlm_u_tlm_rx_fc_src_npd; + wire [7 : 0] com_tlm_u_tlm_rx_fc_src_nph; + wire [0 : 0] com_tlm_u_tlm_rx_fc_src_initFC_st_i; + wire [3 : 0] com_cmm_req_arbiter; + wire [26 : 26] com_cmm_st_pm; + wire [49 : 0] com_cmm_data_errmanager; + wire [2 : 0] com_cmm_req_errman; + wire [31 : 0] com_cmm_bar5_reg; + wire [31 : 0] com_cmm_bar4_reg; + wire [31 : 0] com_cmm_bar3_reg; + wire [31 : 0] com_cmm_bar2_reg; + wire [31 : 0] com_cmm_bar1_reg; + wire [1 : 0] com_cmm_pme_pmcsr; + wire [31 : 0] com_cmm_cfg_rd_data; + wire [31 : 0] com_cmm_cfg2tlm_rddata; + wire [15 : 0] com_cmm_msi_data; + wire [27 : 24] com_cmm_cfg_wr_data; + wire [9 : 0] com_cmm_cfg_addr; + wire [1 : 0] com_cmm_attr; + wire [3 : 0] com_cmm_cfg_be; + wire [15 : 0] com_cmm_req_id; + wire [7 : 0] com_cmm_tag; + wire [31 : 0] com_cmm_msi_haddr; + wire [31 : 2] com_cmm_msi_laddr; + wire [0 : 0] com_cmm_msi_control_1; + wire [1 : 0] com_cmm_intr_req_type; + wire [3 : 2] com_cmm_u_cmm_intr_next_state_0_i_a2_0_0; + wire [0 : 0] com_cmm_u_cmm_intr_next_state_i_m3_i_o2; + wire [0 : 0] com_cmm_u_cmm_intr_state_i; + wire [3 : 0] com_cmm_u_cmm_intr_state; + wire [0 : 0] com_cmm_u_cmm_intr_next_state_i_m3_i_m2; + wire [2 : 0] com_cmm_u_rx_pkt_proc_state; + wire [31 : 0] com_cmm_u_rx_pkt_proc_nxt_cfg_wr_data; + wire [2 : 2] com_cmm_u_tx_pkt_proc_next_state_0_i_0_0_0_0; + wire [0 : 0] com_cmm_u_tx_pkt_proc_next_state_0_i_0_0_0_a2_0_1; + wire [1 : 1] com_cmm_u_tx_pkt_proc_state; + wire [2 : 2] com_cmm_u_cfg_ctrl_next_state_0_i_0_0_0_o3; + wire [0 : 0] com_cmm_u_cfg_ctrl_state; + wire [12 : 0] com_cmm_u_cmm_decoder_data_tmp_14; + wire [9 : 1] com_cmm_u_cmm_decoder_data_tmp_15; + wire [14 : 0] com_cmm_u_cmm_decoder_data_tmp_3; + wire [12 : 0] com_cmm_u_cmm_decoder_data_tmp_13; + wire [14 : 0] com_cmm_u_cmm_decoder_data_tmp_2; + wire [12 : 0] com_cmm_u_cmm_decoder_data_tmp_12; + wire [14 : 0] com_cmm_u_cmm_decoder_data_tmp_1; + wire [12 : 0] com_cmm_u_cmm_decoder_data_tmp_11; + wire [14 : 0] com_cmm_u_cmm_decoder_data_tmp_0; + wire [12 : 0] com_cmm_u_cmm_decoder_data_tmp_10; + wire [14 : 0] com_cmm_u_cmm_decoder_data_tmp; + wire [12 : 0] com_cmm_u_cmm_decoder_data_tmp_9; + wire [12 : 0] com_cmm_u_cmm_decoder_data_tmp_8; + wire [12 : 0] com_cmm_u_cmm_decoder_data_tmp_7; + wire [12 : 0] com_cmm_u_cmm_decoder_data_tmp_6; + wire [12 : 0] com_cmm_u_cmm_decoder_data_tmp_5; + wire [12 : 0] com_cmm_u_cmm_decoder_data_tmp_4; + wire [4 : 4] com_cmm_u_cmm_decoder_bar_hit_7_0_a2_0; + wire [3 : 3] com_cmm_u_cmm_decoder_bar_hit_6_0_a2_0; + wire [2 : 2] com_cmm_u_cmm_decoder_bar_hit_5_0_a2_0; + wire [1 : 1] com_cmm_u_cmm_decoder_bar_hit_4_0_a2_0; + wire [31 : 0] com_cmm_u_cmm_cfgspace_low_addr_02_q; + wire [31 : 0] com_cmm_u_cmm_cfgspace_low_addr_00_q; + wire [31 : 0] com_cmm_u_cmm_cfgspace_low_addr_03_q; + wire [31 : 0] com_cmm_u_cmm_cfgspace_low_addr_01_q; + wire [31 : 0] com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_bm; + wire [31 : 0] com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_am; + wire [1 : 0] com_cmm_u_cmm_cfgspace_sel_xencode; + wire [1 : 0] com_cmm_u_cmm_cfgspace_data_scale_5_i_m2_i_m4_i_m3_0_bm; + wire [1 : 0] com_cmm_u_cmm_cfgspace_data_scale_5_i_m2_i_m4_i_m3_0_am; + wire [7 : 0] com_cmm_u_cmm_cfgspace_pme_data_5_i_m2_i_m4_i_m3_0_bm; + wire [7 : 0] com_cmm_u_cmm_cfgspace_pme_data_5_i_m2_i_m4_i_m3_0_am; + wire [1 : 0] com_cmm_u_cmm_cfgspace_data_scale_4_i_m2_i_m4_i_m3_0_bm; + wire [1 : 0] com_cmm_u_cmm_cfgspace_data_scale_4_i_m2_i_m4_i_m3_0_am; + wire [7 : 0] com_cmm_u_cmm_cfgspace_pme_data_4_i_m2_i_m4_i_m3_0_bm; + wire [7 : 0] com_cmm_u_cmm_cfgspace_pme_data_4_i_m2_i_m4_i_m3_0_am; + wire [31 : 0] com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_bm; + wire [31 : 0] com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_am; + wire [14 : 14] com_cmm_u_cmm_cfgspace_low_addr_00_0_0_0_0_0; + wire [11 : 11] com_cmm_u_cmm_cfgspace_low_addr_00_i_0_i_0_0; + wire [0 : 0] com_cmm_u_cmm_cfgspace_pme_pmcsr_21_0_i_o3; + wire [14 : 14] com_cmm_u_cmm_cfgspace_pme_pmcsr_21_1; + wire [3 : 3] com_cmm_u_cmm_cfgspace_bar1_reg_8_1_0_0_0_0; + wire [2 : 0] com_cmm_u_cmm_cfgspace_bar1_reg_8_1_0_0_0; + wire [3 : 3] com_cmm_u_cmm_cfgspace_bar2_reg_8_1_0_0_0_0; + wire [2 : 0] com_cmm_u_cmm_cfgspace_bar2_reg_8_1_0_0_0; + wire [1 : 1] com_cmm_u_cmm_cfgspace_bar4_reg_8_1_0_0_0_0; + wire [3 : 0] com_cmm_u_cmm_cfgspace_bar5_reg_8_1_0_0_0; + wire [3 : 3] com_cmm_u_cmm_cfgspace_x_dcmd_18_i_0_0_0_o3; + wire [31 : 0] com_cmm_u_cmm_cfgspace_decoder_read_data; + wire [27 : 27] com_cmm_u_cmm_cfgspace_low_addr_00_i_0_3; + wire [14 : 14] com_cmm_u_cmm_cfgspace_low_addr_00_0_0_0_0_2; + wire [14 : 14] com_cmm_u_cmm_cfgspace_low_addr_00_0_0_0_0_1; + wire [13 : 13] com_cmm_u_cmm_cfgspace_low_addr_00_0_0_1; + wire [13 : 13] com_cmm_u_cmm_cfgspace_low_addr_00_0_0_0; + wire [12 : 12] com_cmm_u_cmm_cfgspace_low_addr_00_0_0_0_1; + wire [12 : 12] com_cmm_u_cmm_cfgspace_low_addr_00_0_0_0_0; + wire [11 : 11] com_cmm_u_cmm_cfgspace_low_addr_00_i_0_i_0_2; + wire [11 : 11] com_cmm_u_cmm_cfgspace_low_addr_00_i_0_i_0_1; + wire [1 : 1] com_cmm_u_cmm_cfgspace_low_addr_00_i_0_0; + wire [1 : 1] com_cmm_u_cmm_cfgspace_low_addr_00_i_0_o3; + wire [2 : 1] com_cmm_u_cmm_cfgspace_sel_encodex_2; + wire [2 : 0] com_cmm_u_cmm_cfgspace_sel_encodex_1; + wire [2 : 0] com_cmm_u_cmm_cfgspace_sel_encodex; + wire [15 : 8] com_cmm_u_cmm_cfgspace_pme_pmcsr; + wire [14 : 13] com_cmm_u_cmm_cfgspace_pme_pmcsr_21; + wire [3 : 3] com_cmm_u_cmm_cfgspace_bar0_reg; + wire [31 : 0] com_cmm_u_cmm_cfgspace_x_dcap; + wire [0 : 0] com_cmm_u_cmm_cfgspace_x_lcap; + wire [7 : 0] com_cmm_u_cmm_cfgspace_cache_line; + wire [7 : 0] com_cmm_u_cmm_cfgspace_int_line; + wire [3 : 3] com_cmm_u_cmm_cfgspace_low_addr_01_7_0_am_0; + wire [0 : 0] com_cmm_u_cmm_cfgspace_low_addr_00_i_0_0_1; + wire [31 : 0] com_cmm_u_cmm_cfgspace_low_addr_01; + wire [31 : 0] com_cmm_u_cmm_cfgspace_low_addr_03_q_4; + wire [31 : 0] com_cmm_u_cmm_cfgspace_low_addr_02; + wire [0 : 0] com_cmm_u_cmm_errman_cplu_num; + wire [0 : 0] com_cmm_u_cmm_errman_cplt_num; + wire [2 : 0] com_cmm_u_cmm_errman_ftl_num; + wire [2 : 0] com_cmm_u_cmm_errman_ftl_num_i; + wire [2 : 0] com_cmm_u_cmm_errman_cor_num_i; + wire [2 : 0] com_cmm_u_cmm_errman_nfl_num_i; + wire [3 : 0] com_cmm_u_cmm_errman_cnt_ftl; + wire [3 : 0] com_cmm_u_cmm_errman_cnt_cor; + wire [3 : 0] com_cmm_u_cmm_errman_cnt_nfl; + wire [3 : 0] com_cmm_u_cmm_errman_cnt_cplt; + wire [3 : 0] com_cmm_u_cmm_errman_cnt_cplu; + wire [2 : 2] com_cmm_u_cmm_errman_ns_fsm_0_i_0_0_0_a2_1_1; + wire [2 : 0] com_cmm_u_cmm_errman_cor_num_int; + wire [1 : 0] com_cmm_u_cmm_errman_ns_fsm_0_i_0_0_0_0; + wire [0 : 0] com_cmm_u_cmm_errman_ns_fsm_0_i_0_0_0_a2_1; + wire [49 : 0] com_cmm_u_cmm_errman_cmt_rd_hdr; + wire [49 : 0] com_cmm_u_cmm_errman_cfg_rd_hdr; + wire [49 : 0] com_cmm_u_cmm_errman_reg_cfg_wr_hdr; + wire [1 : 0] com_cmm_u_cmm_errman_reg_cfg_rp_4; + wire [1 : 0] com_cmm_u_cmm_errman_reg_cfg_rp; + wire [1 : 0] com_cmm_u_cmm_errman_reg_cmt_rp_4; + wire [1 : 0] com_cmm_u_cmm_errman_reg_cmt_rp; + wire [3 : 0] com_cmm_u_cmm_errman_cs_fsm; + wire [47 : 0] com_cmm_u_cmm_errman_reg_cmt_wr_hdr_5; + wire [48 : 0] com_cmm_u_cmm_errman_reg_cmt_wr_hdr; + wire [1 : 0] com_cmm_u_cmm_errman_reg_cfg_wp_4; + wire [1 : 0] com_cmm_u_cmm_errman_reg_cfg_wp; + wire [1 : 0] com_cmm_u_cmm_errman_reg_cmt_wp_4; + wire [1 : 0] com_cmm_u_cmm_errman_reg_cmt_wp; + wire [2 : 2] com_cmm_u_cmm_errman_cor_num; + wire [2 : 2] com_cmm_u_cmm_errman_nfl_num; + wire [3 : 0] com_cmm_u_cmm_errman_cor_cntr_reg_cnt_6; + wire [3 : 0] com_cmm_u_cmm_errman_cor_cntr_reg_cnt; + wire [4 : 0] com_cmm_u_cmm_errman_nfl_cntr_un14_reg_cnt; + wire [4 : 1] com_cmm_u_cmm_errman_nfl_cntr_un25_reg_cnt; + wire [3 : 0] com_cmm_u_cmm_errman_nfl_cntr_reg_cnt_6_0_i_m2_0_1; + wire [3 : 0] com_cmm_u_cmm_errman_nfl_cntr_reg_cnt; + wire [3 : 0] com_cmm_u_cmm_errman_ftl_cntr_reg_cnt; + wire [2 : 2] com_cmm_u_cmm_errman_cplt_cntr_reg_cnt_6_0_i_m2_0_bm; + wire [2 : 2] com_cmm_u_cmm_errman_cplt_cntr_reg_cnt_6_0_i_m2_0_am; + wire [4 : 4] com_cmm_u_cmm_errman_cplt_cntr_un14_reg_cnt; + wire [3 : 0] com_cmm_u_cmm_errman_cplt_cntr_reg_cnt_6_0_i_m2_0_0; + wire [3 : 0] com_cmm_u_cmm_errman_cplt_cntr_reg_cnt; + wire [2 : 2] com_cmm_u_cmm_errman_cplu_cntr_reg_cnt_6_0_i_m2_0_bm_0; + wire [2 : 2] com_cmm_u_cmm_errman_cplu_cntr_reg_cnt_6_0_i_m2_0_am_0; + wire [4 : 4] com_cmm_u_cmm_errman_cplu_cntr_un14_reg_cnt; + wire [3 : 0] com_cmm_u_cmm_errman_cplu_cntr_reg_cnt_6_0_i_m2_0; + wire [3 : 0] com_cmm_u_cmm_errman_cplu_cntr_reg_cnt; + wire [49 : 0] com_cmm_u_cmm_errman_cmt_hdr_buf_lutram_data; + wire [49 : 0] com_cmm_u_cmm_errman_cfg_hdr_buf_lutram_data; + wire [7 : 0] com_cmm_u_cmm_pm_inactivity_timer_cry; + wire [0 : 0] com_cmm_u_cmm_pm_un936_st_pm_next_m_0_a2_0_a2_0_a2_0_a2_6; + wire [0 : 0] com_cmm_u_cmm_pm_un936_st_pm_next_m_0_a2_0_a2_0_a2_0_a2_9; + wire [0 : 0] com_cmm_u_cmm_pm_un936_st_pm_next_m_0_a2_0_a2_0_a2_0_a2_7; + wire [1 : 1] com_cmm_u_cmm_pm_st_pm_next_0_0_0_iv_0_a2_i_0_0; + wire [1 : 1] com_cmm_u_cmm_pm_st_pm_next_0_0_0_iv_0_a2_i_0_2; + wire [0 : 0] com_cmm_u_cmm_pm_un936_st_pm_next_m_0_a2_0_a2_0_a2_0_a2_12; + wire [8 : 0] com_cmm_u_cmm_pm_inactivity_timer_s; + wire [0 : 0] com_cmm_u_cmm_pm_st_pm_next; + wire [0 : 0] com_cmm_u_cmm_pm_cfg_pcie_link_state; + wire [1 : 1] com_cmm_u_cmm_pm_enable_cmm_tx; + wire [8 : 0] com_cmm_u_cmm_pm_inactivity_timer_qxu; + wire [8 : 0] com_cmm_u_cmm_pm_inactivity_timer; + wire [2 : 0] com_cmm_u_cmm_arbiter_req_errman_d; + wire [0 : 0] com_cmm_u_cmm_arbiter_req_arbiter_6_i_0_i_o3_0; + wire [2 : 2] com_cmm_u_cmm_arbiter_ns_fsm_0_a4_0_0_a2_0_a2_0_a2; + wire [3 : 0] com_cmm_u_cmm_arbiter_cs_fsm; + wire [2 : 2] com_cmm_u_cmm_arbiter_ns_fsm_0_0_0_0_1; + wire [2 : 2] com_cmm_u_cmm_arbiter_req_arbiter_6_i_0_1; + wire [1 : 1] com_cmm_u_cmm_dataproducer_byte_11_17_0_bm; + wire [1 : 1] com_cmm_u_cmm_dataproducer_byte_11_17_0_am; + wire [31 : 2] com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_bm; + wire [31 : 2] com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_am; + wire [2 : 1] com_cmm_u_cmm_dataproducer_req_gnt_code; + wire [6 : 2] com_cmm_u_cmm_dataproducer_byte_11_17_m0; + wire [0 : 0] com_cmm_u_cmm_dataproducer_byte_04_17_i_0_0_0_a2; + wire [0 : 0] com_cmm_u_cmm_dataproducer_byte_11_17_m0_0_a2_i_0_0_o2; + wire [2 : 2] com_cmm_u_cmm_dataproducer_req_gnt_code_8_i_0_0_0_o3; + wire [1 : 0] com_cmm_u_cmm_dataproducer_req_gnt_state; + wire [7 : 6] com_cmm_u_cmm_dataproducer_byte_07_27; + wire [31 : 0] com_cmm_u_cmm_dataproducer_bytes_12_to_15_17; + wire [5 : 5] com_cmm_u_cmm_dataproducer_byte_00_19_i_i_0_0_i_a2; + wire [7 : 0] com_cmm_u_cmm_dataproducer_byte_11_17; + wire [3 : 3] com_cmm_u_cmm_dataproducer_req_gnt_code_8_i_0_0_0_1_0; + wire [3 : 3] com_cmm_u_cmm_dataproducer_req_gnt_code_8_i_0_0_0_1; + wire [0 : 0] com_cmm_u_cmm_dataproducer_pcie_link_state_d; + assign + cfg_byte_en_n_5068[3] = cfg_byte_en_n[3], + cfg_byte_en_n_5068[2] = cfg_byte_en_n[2], + cfg_byte_en_n_5068[1] = cfg_byte_en_n[1], + cfg_byte_en_n_5068[0] = cfg_byte_en_n[0], + trn_rfc_ph_av[7] = trn_rfc_ph_av_5062[7], + trn_rfc_ph_av[6] = trn_rfc_ph_av_5062[6], + trn_rfc_ph_av[5] = trn_rfc_ph_av_5062[5], + trn_rfc_ph_av[4] = trn_rfc_ph_av_5062[4], + trn_rfc_ph_av[3] = trn_rfc_ph_av_5062[3], + trn_rfc_ph_av[2] = trn_rfc_ph_av_5062[2], + trn_rfc_ph_av[1] = trn_rfc_ph_av_5062[1], + trn_rfc_ph_av[0] = trn_rfc_ph_av_5062[0], + trn_rd[63] = NlwRenamedSig_OI_trn_rd[63], + trn_rd[62] = NlwRenamedSig_OI_trn_rd[62], + trn_rd[61] = NlwRenamedSig_OI_trn_rd[61], + trn_rd[60] = NlwRenamedSig_OI_trn_rd[60], + trn_rd[59] = NlwRenamedSig_OI_trn_rd[59], + trn_rd[58] = NlwRenamedSig_OI_trn_rd[58], + trn_rd[57] = NlwRenamedSig_OI_trn_rd[57], + trn_rd[56] = NlwRenamedSig_OI_trn_rd[56], + trn_rd[55] = NlwRenamedSig_OI_trn_rd[55], + trn_rd[54] = NlwRenamedSig_OI_trn_rd[54], + trn_rd[53] = NlwRenamedSig_OI_trn_rd[53], + trn_rd[52] = NlwRenamedSig_OI_trn_rd[52], + trn_rd[51] = NlwRenamedSig_OI_trn_rd[51], + trn_rd[50] = NlwRenamedSig_OI_trn_rd[50], + trn_rd[49] = NlwRenamedSig_OI_trn_rd[49], + trn_rd[48] = NlwRenamedSig_OI_trn_rd[48], + trn_rd[47] = NlwRenamedSig_OI_trn_rd[47], + trn_rd[46] = NlwRenamedSig_OI_trn_rd[46], + trn_rd[45] = NlwRenamedSig_OI_trn_rd[45], + trn_rd[44] = NlwRenamedSig_OI_trn_rd[44], + trn_rd[43] = NlwRenamedSig_OI_trn_rd[43], + trn_rd[42] = NlwRenamedSig_OI_trn_rd[42], + trn_rd[41] = NlwRenamedSig_OI_trn_rd[41], + trn_rd[40] = NlwRenamedSig_OI_trn_rd[40], + trn_rd[39] = NlwRenamedSig_OI_trn_rd[39], + trn_rd[38] = NlwRenamedSig_OI_trn_rd[38], + trn_rd[37] = NlwRenamedSig_OI_trn_rd[37], + trn_rd[36] = NlwRenamedSig_OI_trn_rd[36], + trn_rd[35] = NlwRenamedSig_OI_trn_rd[35], + trn_rd[34] = NlwRenamedSig_OI_trn_rd[34], + trn_rd[33] = NlwRenamedSig_OI_trn_rd[33], + trn_rd[32] = NlwRenamedSig_OI_trn_rd[32], + trn_rd[31] = NlwRenamedSig_OI_trn_rd[31], + trn_rd[30] = NlwRenamedSig_OI_trn_rd[30], + trn_rd[29] = NlwRenamedSig_OI_trn_rd[29], + trn_rd[28] = NlwRenamedSig_OI_trn_rd[28], + trn_rd[27] = NlwRenamedSig_OI_trn_rd[27], + trn_rd[26] = NlwRenamedSig_OI_trn_rd[26], + trn_rd[25] = NlwRenamedSig_OI_trn_rd[25], + trn_rd[24] = NlwRenamedSig_OI_trn_rd[24], + trn_rd[23] = NlwRenamedSig_OI_trn_rd[23], + trn_rd[22] = NlwRenamedSig_OI_trn_rd[22], + trn_rd[21] = NlwRenamedSig_OI_trn_rd[21], + trn_rd[20] = NlwRenamedSig_OI_trn_rd[20], + trn_rd[19] = NlwRenamedSig_OI_trn_rd[19], + trn_rd[18] = NlwRenamedSig_OI_trn_rd[18], + trn_rd[17] = NlwRenamedSig_OI_trn_rd[17], + trn_rd[16] = NlwRenamedSig_OI_trn_rd[16], + trn_rd[15] = NlwRenamedSig_OI_trn_rd[15], + trn_rd[14] = NlwRenamedSig_OI_trn_rd[14], + trn_rd[13] = NlwRenamedSig_OI_trn_rd[13], + trn_rd[12] = NlwRenamedSig_OI_trn_rd[12], + trn_rd[11] = NlwRenamedSig_OI_trn_rd[11], + trn_rd[10] = NlwRenamedSig_OI_trn_rd[10], + trn_rd[9] = NlwRenamedSig_OI_trn_rd[9], + trn_rd[8] = NlwRenamedSig_OI_trn_rd[8], + trn_rd[7] = NlwRenamedSig_OI_trn_rd[7], + trn_rd[6] = NlwRenamedSig_OI_trn_rd[6], + trn_rd[5] = NlwRenamedSig_OI_trn_rd[5], + trn_rd[4] = NlwRenamedSig_OI_trn_rd[4], + trn_rd[3] = NlwRenamedSig_OI_trn_rd[3], + trn_rd[2] = NlwRenamedSig_OI_trn_rd[2], + trn_rd[1] = NlwRenamedSig_OI_trn_rd[1], + trn_rd[0] = NlwRenamedSig_OI_trn_rd[0], + trn_td_5057[63] = trn_td[63], + trn_td_5057[62] = trn_td[62], + trn_td_5057[61] = trn_td[61], + trn_td_5057[60] = trn_td[60], + trn_td_5057[59] = trn_td[59], + trn_td_5057[58] = trn_td[58], + trn_td_5057[57] = trn_td[57], + trn_td_5057[56] = trn_td[56], + trn_td_5057[55] = trn_td[55], + trn_td_5057[54] = trn_td[54], + trn_td_5057[53] = trn_td[53], + trn_td_5057[52] = trn_td[52], + trn_td_5057[51] = trn_td[51], + trn_td_5057[50] = trn_td[50], + trn_td_5057[49] = trn_td[49], + trn_td_5057[48] = trn_td[48], + trn_td_5057[47] = trn_td[47], + trn_td_5057[46] = trn_td[46], + trn_td_5057[45] = trn_td[45], + trn_td_5057[44] = trn_td[44], + trn_td_5057[43] = trn_td[43], + trn_td_5057[42] = trn_td[42], + trn_td_5057[41] = trn_td[41], + trn_td_5057[40] = trn_td[40], + trn_td_5057[39] = trn_td[39], + trn_td_5057[38] = trn_td[38], + trn_td_5057[37] = trn_td[37], + trn_td_5057[36] = trn_td[36], + trn_td_5057[35] = trn_td[35], + trn_td_5057[34] = trn_td[34], + trn_td_5057[33] = trn_td[33], + trn_td_5057[32] = trn_td[32], + trn_td_5057[31] = trn_td[31], + trn_td_5057[30] = trn_td[30], + trn_td_5057[29] = trn_td[29], + trn_td_5057[28] = trn_td[28], + trn_td_5057[27] = trn_td[27], + trn_td_5057[26] = trn_td[26], + trn_td_5057[25] = trn_td[25], + trn_td_5057[24] = trn_td[24], + trn_td_5057[23] = trn_td[23], + trn_td_5057[22] = trn_td[22], + trn_td_5057[21] = trn_td[21], + trn_td_5057[20] = trn_td[20], + trn_td_5057[19] = trn_td[19], + trn_td_5057[18] = trn_td[18], + trn_td_5057[17] = trn_td[17], + trn_td_5057[16] = trn_td[16], + trn_td_5057[15] = trn_td[15], + trn_td_5057[14] = trn_td[14], + trn_td_5057[13] = trn_td[13], + trn_td_5057[12] = trn_td[12], + trn_td_5057[11] = trn_td[11], + trn_td_5057[10] = trn_td[10], + trn_td_5057[9] = trn_td[9], + trn_td_5057[8] = trn_td[8], + trn_td_5057[7] = trn_td[7], + trn_td_5057[6] = trn_td[6], + trn_td_5057[5] = trn_td[5], + trn_td_5057[4] = trn_td[4], + trn_td_5057[3] = trn_td[3], + trn_td_5057[2] = trn_td[2], + trn_td_5057[1] = trn_td[1], + trn_td_5057[0] = trn_td[0], + cfg_err_tlp_cpl_header_5070[47] = cfg_err_tlp_cpl_header[47], + cfg_err_tlp_cpl_header_5070[46] = cfg_err_tlp_cpl_header[46], + cfg_err_tlp_cpl_header_5070[45] = cfg_err_tlp_cpl_header[45], + cfg_err_tlp_cpl_header_5070[44] = cfg_err_tlp_cpl_header[44], + cfg_err_tlp_cpl_header_5070[43] = cfg_err_tlp_cpl_header[43], + cfg_err_tlp_cpl_header_5070[42] = cfg_err_tlp_cpl_header[42], + cfg_err_tlp_cpl_header_5070[41] = cfg_err_tlp_cpl_header[41], + cfg_err_tlp_cpl_header_5070[40] = cfg_err_tlp_cpl_header[40], + cfg_err_tlp_cpl_header_5070[39] = cfg_err_tlp_cpl_header[39], + cfg_err_tlp_cpl_header_5070[38] = cfg_err_tlp_cpl_header[38], + cfg_err_tlp_cpl_header_5070[37] = cfg_err_tlp_cpl_header[37], + cfg_err_tlp_cpl_header_5070[36] = cfg_err_tlp_cpl_header[36], + cfg_err_tlp_cpl_header_5070[35] = cfg_err_tlp_cpl_header[35], + cfg_err_tlp_cpl_header_5070[34] = cfg_err_tlp_cpl_header[34], + cfg_err_tlp_cpl_header_5070[33] = cfg_err_tlp_cpl_header[33], + cfg_err_tlp_cpl_header_5070[32] = cfg_err_tlp_cpl_header[32], + cfg_err_tlp_cpl_header_5070[31] = cfg_err_tlp_cpl_header[31], + cfg_err_tlp_cpl_header_5070[30] = cfg_err_tlp_cpl_header[30], + cfg_err_tlp_cpl_header_5070[29] = cfg_err_tlp_cpl_header[29], + cfg_err_tlp_cpl_header_5070[28] = cfg_err_tlp_cpl_header[28], + cfg_err_tlp_cpl_header_5070[27] = cfg_err_tlp_cpl_header[27], + cfg_err_tlp_cpl_header_5070[26] = cfg_err_tlp_cpl_header[26], + cfg_err_tlp_cpl_header_5070[25] = cfg_err_tlp_cpl_header[25], + cfg_err_tlp_cpl_header_5070[24] = cfg_err_tlp_cpl_header[24], + cfg_err_tlp_cpl_header_5070[23] = cfg_err_tlp_cpl_header[23], + cfg_err_tlp_cpl_header_5070[22] = cfg_err_tlp_cpl_header[22], + cfg_err_tlp_cpl_header_5070[21] = cfg_err_tlp_cpl_header[21], + cfg_err_tlp_cpl_header_5070[20] = cfg_err_tlp_cpl_header[20], + cfg_err_tlp_cpl_header_5070[19] = cfg_err_tlp_cpl_header[19], + cfg_err_tlp_cpl_header_5070[18] = cfg_err_tlp_cpl_header[18], + cfg_err_tlp_cpl_header_5070[17] = cfg_err_tlp_cpl_header[17], + cfg_err_tlp_cpl_header_5070[16] = cfg_err_tlp_cpl_header[16], + cfg_err_tlp_cpl_header_5070[15] = cfg_err_tlp_cpl_header[15], + cfg_err_tlp_cpl_header_5070[14] = cfg_err_tlp_cpl_header[14], + cfg_err_tlp_cpl_header_5070[13] = cfg_err_tlp_cpl_header[13], + cfg_err_tlp_cpl_header_5070[12] = cfg_err_tlp_cpl_header[12], + cfg_err_tlp_cpl_header_5070[11] = cfg_err_tlp_cpl_header[11], + cfg_err_tlp_cpl_header_5070[10] = cfg_err_tlp_cpl_header[10], + cfg_err_tlp_cpl_header_5070[9] = cfg_err_tlp_cpl_header[9], + cfg_err_tlp_cpl_header_5070[8] = cfg_err_tlp_cpl_header[8], + cfg_err_tlp_cpl_header_5070[7] = cfg_err_tlp_cpl_header[7], + cfg_err_tlp_cpl_header_5070[6] = cfg_err_tlp_cpl_header[6], + cfg_err_tlp_cpl_header_5070[5] = cfg_err_tlp_cpl_header[5], + cfg_err_tlp_cpl_header_5070[4] = cfg_err_tlp_cpl_header[4], + cfg_err_tlp_cpl_header_5070[3] = cfg_err_tlp_cpl_header[3], + cfg_err_tlp_cpl_header_5070[2] = cfg_err_tlp_cpl_header[2], + cfg_err_tlp_cpl_header_5070[1] = cfg_err_tlp_cpl_header[1], + cfg_err_tlp_cpl_header_5070[0] = cfg_err_tlp_cpl_header[0], + trn_rbar_hit_n[6] = trn_rbar_hit_n_5059[6], + trn_rbar_hit_n[5] = trn_rbar_hit_n_5059[5], + trn_rbar_hit_n[4] = trn_rbar_hit_n_5059[4], + trn_rbar_hit_n[3] = trn_rbar_hit_n_5059[3], + trn_rbar_hit_n[2] = trn_rbar_hit_n_5059[2], + trn_rbar_hit_n[1] = trn_rbar_hit_n_5059[1], + trn_rbar_hit_n[0] = trn_rbar_hit_n_5059[0], + trn_rfc_cpld_av[11] = NlwRenamedSig_OI_trn_rfc_cpld_av[11], + trn_rfc_cpld_av[10] = trn_rfc_cpld_av_5065[10], + trn_rfc_cpld_av[9] = trn_rfc_cpld_av_5065[9], + trn_rfc_cpld_av[8] = trn_rfc_cpld_av_5065[8], + trn_rfc_cpld_av[7] = trn_rfc_cpld_av_5065[7], + trn_rfc_cpld_av[6] = trn_rfc_cpld_av_5065[6], + trn_rfc_cpld_av[5] = trn_rfc_cpld_av_5065[5], + trn_rfc_cpld_av[4] = trn_rfc_cpld_av_5065[4], + trn_rfc_cpld_av[3] = trn_rfc_cpld_av_5065[3], + trn_rfc_cpld_av[2] = trn_rfc_cpld_av_5065[2], + trn_rfc_cpld_av[1] = trn_rfc_cpld_av_5065[1], + trn_rfc_cpld_av[0] = trn_rfc_cpld_av_5065[0], + cfg_lcommand[15] = NlwRenamedSignal_cfg_lcommand[15], + cfg_lcommand[14] = NlwRenamedSignal_cfg_lcommand[15], + cfg_lcommand[13] = NlwRenamedSignal_cfg_lcommand[15], + cfg_lcommand[12] = NlwRenamedSignal_cfg_lcommand[15], + cfg_lcommand[11] = NlwRenamedSignal_cfg_lcommand[15], + cfg_lcommand[10] = NlwRenamedSignal_cfg_lcommand[15], + cfg_lcommand[9] = NlwRenamedSignal_cfg_lcommand[15], + cfg_lcommand[8] = NlwRenamedSignal_cfg_lcommand[15], + cfg_lcommand[7] = NlwRenamedSig_OI_cfg_lcommand_7_, + cfg_lcommand[6] = NlwRenamedSig_OI_cfg_lcommand_6_, + cfg_lcommand[5] = NlwRenamedSignal_cfg_lcommand[15], + cfg_lcommand[4] = NlwRenamedSignal_cfg_lcommand[15], + cfg_lcommand[3] = NlwRenamedSig_OI_cfg_lcommand_3_, + cfg_lcommand[2] = NlwRenamedSignal_cfg_lcommand[15], + cfg_lcommand[1] = NlwRenamedSig_OI_cfg_lcommand_1_, + cfg_lcommand[0] = NlwRenamedSig_OI_cfg_lcommand_0_, + cfg_dstatus[15] = NlwRenamedSignal_cfg_lcommand[15], + cfg_dstatus[14] = NlwRenamedSignal_cfg_lcommand[15], + cfg_dstatus[13] = NlwRenamedSignal_cfg_lcommand[15], + cfg_dstatus[12] = NlwRenamedSignal_cfg_lcommand[15], + cfg_dstatus[11] = NlwRenamedSignal_cfg_lcommand[15], + cfg_dstatus[10] = NlwRenamedSignal_cfg_lcommand[15], + cfg_dstatus[9] = NlwRenamedSignal_cfg_lcommand[15], + cfg_dstatus[8] = NlwRenamedSignal_cfg_lcommand[15], + cfg_dstatus[7] = NlwRenamedSignal_cfg_lcommand[15], + cfg_dstatus[6] = NlwRenamedSignal_cfg_lcommand[15], + cfg_dstatus[5] = NlwRenamedSig_OI_cfg_dstatus_5_, + cfg_dstatus[4] = NlwRenamedSignal_cfg_lcommand[15], + cfg_dstatus[3] = NlwRenamedSig_OI_cfg_dstatus_3_, + cfg_dstatus[2] = NlwRenamedSig_OI_cfg_dstatus_2_, + cfg_dstatus[1] = NlwRenamedSig_OI_cfg_dstatus_1_, + cfg_dstatus[0] = NlwRenamedSig_OI_cfg_dstatus_0_, + trn_rrem_n[7] = NlwRenamedSignal_cfg_lcommand[15], + trn_rrem_n[6] = NlwRenamedSignal_cfg_lcommand[15], + trn_rrem_n[5] = NlwRenamedSignal_cfg_lcommand[15], + trn_rrem_n[4] = NlwRenamedSignal_cfg_lcommand[15], + trn_rrem_n[3] = NlwRenamedSignal_trn_rrem_n[3], + trn_rrem_n[2] = NlwRenamedSignal_trn_rrem_n[3], + trn_rrem_n[1] = NlwRenamedSignal_trn_rrem_n[3], + trn_rrem_n[0] = NlwRenamedSignal_trn_rrem_n[3], + cfg_status[15] = NlwRenamedSig_OI_cfg_status_15_, + cfg_status[14] = NlwRenamedSig_OI_cfg_status_14_, + cfg_status[13] = NlwRenamedSig_OI_cfg_status_13_, + cfg_status[12] = NlwRenamedSig_OI_cfg_status_12_, + cfg_status[11] = NlwRenamedSig_OI_cfg_status_11_, + cfg_status[10] = NlwRenamedSignal_cfg_lcommand[15], + cfg_status[9] = NlwRenamedSignal_cfg_lcommand[15], + cfg_status[8] = NlwRenamedSig_OI_cfg_status_8_, + cfg_status[7] = NlwRenamedSignal_cfg_lcommand[15], + cfg_status[6] = NlwRenamedSignal_cfg_lcommand[15], + cfg_status[5] = NlwRenamedSignal_cfg_lcommand[15], + cfg_status[4] = NlwRenamedSig_OI_cfg_status_4_, + cfg_status[3] = NlwRenamedSig_OI_cfg_status_3_, + cfg_status[2] = NlwRenamedSignal_cfg_lcommand[15], + cfg_status[1] = NlwRenamedSignal_cfg_lcommand[15], + cfg_status[0] = NlwRenamedSignal_cfg_lcommand[15], + trn_rfc_cplh_av[7] = NlwRenamedSig_OI_trn_rfc_cplh_av[7], + trn_rfc_cplh_av[6] = trn_rfc_cplh_av_5064[6], + trn_rfc_cplh_av[5] = trn_rfc_cplh_av_5064[5], + trn_rfc_cplh_av[4] = trn_rfc_cplh_av_5064[4], + trn_rfc_cplh_av[3] = trn_rfc_cplh_av_5064[3], + trn_rfc_cplh_av[2] = trn_rfc_cplh_av_5064[2], + trn_rfc_cplh_av[1] = trn_rfc_cplh_av_5064[1], + trn_rfc_cplh_av[0] = trn_rfc_cplh_av_5064[0], + cfg_command[15] = NlwRenamedSignal_cfg_lcommand[15], + cfg_command[14] = NlwRenamedSignal_cfg_lcommand[15], + cfg_command[13] = NlwRenamedSignal_cfg_lcommand[15], + cfg_command[12] = NlwRenamedSignal_cfg_lcommand[15], + cfg_command[11] = NlwRenamedSignal_cfg_lcommand[15], + cfg_command[10] = NlwRenamedSig_OI_cfg_command_10_, + cfg_command[9] = NlwRenamedSignal_cfg_lcommand[15], + cfg_command[8] = NlwRenamedSig_OI_cfg_command_8_, + cfg_command[7] = NlwRenamedSignal_cfg_lcommand[15], + cfg_command[6] = NlwRenamedSig_OI_cfg_command_6_, + cfg_command[5] = NlwRenamedSignal_cfg_lcommand[15], + cfg_command[4] = NlwRenamedSignal_cfg_lcommand[15], + cfg_command[3] = NlwRenamedSignal_cfg_lcommand[15], + cfg_command[2] = NlwRenamedSig_OI_cfg_command_2_, + cfg_command[1] = NlwRenamedSig_OI_cfg_command_1_, + cfg_command[0] = NlwRenamedSig_OI_cfg_command_0_, + pci_exp_txn[0] = pci_exp_txn_5054[0], + pci_exp_txp[0] = pci_exp_txp_5053[0], + trn_trem_n_5058[7] = trn_trem_n[7], + trn_trem_n_5058[6] = trn_trem_n[6], + trn_trem_n_5058[5] = trn_trem_n[5], + trn_trem_n_5058[4] = trn_trem_n[4], + trn_trem_n_5058[3] = trn_trem_n[3], + trn_trem_n_5058[2] = trn_trem_n[2], + trn_trem_n_5058[1] = trn_trem_n[1], + trn_trem_n_5058[0] = trn_trem_n[0], + cfg_cfg_5072[1023] = cfg_cfg[1023], + cfg_cfg_5072[1022] = cfg_cfg[1022], + cfg_cfg_5072[1021] = cfg_cfg[1021], + cfg_cfg_5072[1020] = cfg_cfg[1020], + cfg_cfg_5072[1019] = cfg_cfg[1019], + cfg_cfg_5072[1018] = cfg_cfg[1018], + cfg_cfg_5072[1017] = cfg_cfg[1017], + cfg_cfg_5072[1016] = cfg_cfg[1016], + cfg_cfg_5072[1015] = cfg_cfg[1015], + cfg_cfg_5072[1014] = cfg_cfg[1014], + cfg_cfg_5072[1013] = cfg_cfg[1013], + cfg_cfg_5072[1012] = cfg_cfg[1012], + cfg_cfg_5072[1011] = cfg_cfg[1011], + cfg_cfg_5072[1010] = cfg_cfg[1010], + cfg_cfg_5072[1009] = cfg_cfg[1009], + cfg_cfg_5072[1008] = cfg_cfg[1008], + cfg_cfg_5072[1007] = cfg_cfg[1007], + cfg_cfg_5072[1006] = cfg_cfg[1006], + cfg_cfg_5072[1005] = cfg_cfg[1005], + cfg_cfg_5072[1004] = cfg_cfg[1004], + cfg_cfg_5072[1003] = cfg_cfg[1003], + cfg_cfg_5072[1002] = cfg_cfg[1002], + cfg_cfg_5072[1001] = cfg_cfg[1001], + cfg_cfg_5072[1000] = cfg_cfg[1000], + cfg_cfg_5072[999] = cfg_cfg[999], + cfg_cfg_5072[998] = cfg_cfg[998], + cfg_cfg_5072[997] = cfg_cfg[997], + cfg_cfg_5072[996] = cfg_cfg[996], + cfg_cfg_5072[995] = cfg_cfg[995], + cfg_cfg_5072[994] = cfg_cfg[994], + cfg_cfg_5072[993] = cfg_cfg[993], + cfg_cfg_5072[992] = cfg_cfg[992], + cfg_cfg_5072[991] = cfg_cfg[991], + cfg_cfg_5072[990] = cfg_cfg[990], + cfg_cfg_5072[989] = cfg_cfg[989], + cfg_cfg_5072[988] = cfg_cfg[988], + cfg_cfg_5072[987] = cfg_cfg[987], + cfg_cfg_5072[986] = cfg_cfg[986], + cfg_cfg_5072[985] = cfg_cfg[985], + cfg_cfg_5072[984] = cfg_cfg[984], + cfg_cfg_5072[983] = cfg_cfg[983], + cfg_cfg_5072[982] = cfg_cfg[982], + cfg_cfg_5072[981] = cfg_cfg[981], + cfg_cfg_5072[980] = cfg_cfg[980], + cfg_cfg_5072[979] = cfg_cfg[979], + cfg_cfg_5072[978] = cfg_cfg[978], + cfg_cfg_5072[977] = cfg_cfg[977], + cfg_cfg_5072[976] = cfg_cfg[976], + cfg_cfg_5072[975] = cfg_cfg[975], + cfg_cfg_5072[974] = cfg_cfg[974], + cfg_cfg_5072[973] = cfg_cfg[973], + cfg_cfg_5072[972] = cfg_cfg[972], + cfg_cfg_5072[971] = cfg_cfg[971], + cfg_cfg_5072[970] = cfg_cfg[970], + cfg_cfg_5072[969] = cfg_cfg[969], + cfg_cfg_5072[968] = cfg_cfg[968], + cfg_cfg_5072[967] = cfg_cfg[967], + cfg_cfg_5072[966] = cfg_cfg[966], + cfg_cfg_5072[965] = cfg_cfg[965], + cfg_cfg_5072[964] = cfg_cfg[964], + cfg_cfg_5072[963] = cfg_cfg[963], + cfg_cfg_5072[962] = cfg_cfg[962], + cfg_cfg_5072[961] = cfg_cfg[961], + cfg_cfg_5072[960] = cfg_cfg[960], + cfg_cfg_5072[959] = cfg_cfg[959], + cfg_cfg_5072[958] = cfg_cfg[958], + cfg_cfg_5072[957] = cfg_cfg[957], + cfg_cfg_5072[956] = cfg_cfg[956], + cfg_cfg_5072[955] = cfg_cfg[955], + cfg_cfg_5072[954] = cfg_cfg[954], + cfg_cfg_5072[953] = cfg_cfg[953], + cfg_cfg_5072[952] = cfg_cfg[952], + cfg_cfg_5072[951] = cfg_cfg[951], + cfg_cfg_5072[950] = cfg_cfg[950], + cfg_cfg_5072[949] = cfg_cfg[949], + cfg_cfg_5072[948] = cfg_cfg[948], + cfg_cfg_5072[947] = cfg_cfg[947], + cfg_cfg_5072[946] = cfg_cfg[946], + cfg_cfg_5072[945] = cfg_cfg[945], + cfg_cfg_5072[944] = cfg_cfg[944], + cfg_cfg_5072[943] = cfg_cfg[943], + cfg_cfg_5072[942] = cfg_cfg[942], + cfg_cfg_5072[941] = cfg_cfg[941], + cfg_cfg_5072[940] = cfg_cfg[940], + cfg_cfg_5072[939] = cfg_cfg[939], + cfg_cfg_5072[938] = cfg_cfg[938], + cfg_cfg_5072[937] = cfg_cfg[937], + cfg_cfg_5072[936] = cfg_cfg[936], + cfg_cfg_5072[935] = cfg_cfg[935], + cfg_cfg_5072[934] = cfg_cfg[934], + cfg_cfg_5072[933] = cfg_cfg[933], + cfg_cfg_5072[932] = cfg_cfg[932], + cfg_cfg_5072[931] = cfg_cfg[931], + cfg_cfg_5072[930] = cfg_cfg[930], + cfg_cfg_5072[929] = cfg_cfg[929], + cfg_cfg_5072[928] = cfg_cfg[928], + cfg_cfg_5072[927] = cfg_cfg[927], + cfg_cfg_5072[926] = cfg_cfg[926], + cfg_cfg_5072[925] = cfg_cfg[925], + cfg_cfg_5072[924] = cfg_cfg[924], + cfg_cfg_5072[923] = cfg_cfg[923], + cfg_cfg_5072[922] = cfg_cfg[922], + cfg_cfg_5072[921] = cfg_cfg[921], + cfg_cfg_5072[920] = cfg_cfg[920], + cfg_cfg_5072[919] = cfg_cfg[919], + cfg_cfg_5072[918] = cfg_cfg[918], + cfg_cfg_5072[917] = cfg_cfg[917], + cfg_cfg_5072[916] = cfg_cfg[916], + cfg_cfg_5072[915] = cfg_cfg[915], + cfg_cfg_5072[914] = cfg_cfg[914], + cfg_cfg_5072[913] = cfg_cfg[913], + cfg_cfg_5072[912] = cfg_cfg[912], + cfg_cfg_5072[911] = cfg_cfg[911], + cfg_cfg_5072[910] = cfg_cfg[910], + cfg_cfg_5072[909] = cfg_cfg[909], + cfg_cfg_5072[908] = cfg_cfg[908], + cfg_cfg_5072[907] = cfg_cfg[907], + cfg_cfg_5072[906] = cfg_cfg[906], + cfg_cfg_5072[905] = cfg_cfg[905], + cfg_cfg_5072[904] = cfg_cfg[904], + cfg_cfg_5072[903] = cfg_cfg[903], + cfg_cfg_5072[902] = cfg_cfg[902], + cfg_cfg_5072[901] = cfg_cfg[901], + cfg_cfg_5072[900] = cfg_cfg[900], + cfg_cfg_5072[899] = cfg_cfg[899], + cfg_cfg_5072[898] = cfg_cfg[898], + cfg_cfg_5072[897] = cfg_cfg[897], + cfg_cfg_5072[896] = cfg_cfg[896], + cfg_cfg_5072[895] = cfg_cfg[895], + cfg_cfg_5072[894] = cfg_cfg[894], + cfg_cfg_5072[893] = cfg_cfg[893], + cfg_cfg_5072[892] = cfg_cfg[892], + cfg_cfg_5072[891] = cfg_cfg[891], + cfg_cfg_5072[890] = cfg_cfg[890], + cfg_cfg_5072[889] = cfg_cfg[889], + cfg_cfg_5072[888] = cfg_cfg[888], + cfg_cfg_5072[887] = cfg_cfg[887], + cfg_cfg_5072[886] = cfg_cfg[886], + cfg_cfg_5072[885] = cfg_cfg[885], + cfg_cfg_5072[884] = cfg_cfg[884], + cfg_cfg_5072[883] = cfg_cfg[883], + cfg_cfg_5072[882] = cfg_cfg[882], + cfg_cfg_5072[881] = cfg_cfg[881], + cfg_cfg_5072[880] = cfg_cfg[880], + cfg_cfg_5072[879] = cfg_cfg[879], + cfg_cfg_5072[878] = cfg_cfg[878], + cfg_cfg_5072[877] = cfg_cfg[877], + cfg_cfg_5072[876] = cfg_cfg[876], + cfg_cfg_5072[875] = cfg_cfg[875], + cfg_cfg_5072[874] = cfg_cfg[874], + cfg_cfg_5072[873] = cfg_cfg[873], + cfg_cfg_5072[872] = cfg_cfg[872], + cfg_cfg_5072[871] = cfg_cfg[871], + cfg_cfg_5072[870] = cfg_cfg[870], + cfg_cfg_5072[869] = cfg_cfg[869], + cfg_cfg_5072[868] = cfg_cfg[868], + cfg_cfg_5072[867] = cfg_cfg[867], + cfg_cfg_5072[866] = cfg_cfg[866], + cfg_cfg_5072[865] = cfg_cfg[865], + cfg_cfg_5072[864] = cfg_cfg[864], + cfg_cfg_5072[863] = cfg_cfg[863], + cfg_cfg_5072[862] = cfg_cfg[862], + cfg_cfg_5072[861] = cfg_cfg[861], + cfg_cfg_5072[860] = cfg_cfg[860], + cfg_cfg_5072[859] = cfg_cfg[859], + cfg_cfg_5072[858] = cfg_cfg[858], + cfg_cfg_5072[857] = cfg_cfg[857], + cfg_cfg_5072[856] = cfg_cfg[856], + cfg_cfg_5072[855] = cfg_cfg[855], + cfg_cfg_5072[854] = cfg_cfg[854], + cfg_cfg_5072[853] = cfg_cfg[853], + cfg_cfg_5072[852] = cfg_cfg[852], + cfg_cfg_5072[851] = cfg_cfg[851], + cfg_cfg_5072[850] = cfg_cfg[850], + cfg_cfg_5072[849] = cfg_cfg[849], + cfg_cfg_5072[848] = cfg_cfg[848], + cfg_cfg_5072[847] = cfg_cfg[847], + cfg_cfg_5072[846] = cfg_cfg[846], + cfg_cfg_5072[845] = cfg_cfg[845], + cfg_cfg_5072[844] = cfg_cfg[844], + cfg_cfg_5072[843] = cfg_cfg[843], + cfg_cfg_5072[842] = cfg_cfg[842], + cfg_cfg_5072[841] = cfg_cfg[841], + cfg_cfg_5072[840] = cfg_cfg[840], + cfg_cfg_5072[839] = cfg_cfg[839], + cfg_cfg_5072[838] = cfg_cfg[838], + cfg_cfg_5072[837] = cfg_cfg[837], + cfg_cfg_5072[836] = cfg_cfg[836], + cfg_cfg_5072[835] = cfg_cfg[835], + cfg_cfg_5072[834] = cfg_cfg[834], + cfg_cfg_5072[833] = cfg_cfg[833], + cfg_cfg_5072[832] = cfg_cfg[832], + cfg_cfg_5072[831] = cfg_cfg[831], + cfg_cfg_5072[830] = cfg_cfg[830], + cfg_cfg_5072[829] = cfg_cfg[829], + cfg_cfg_5072[828] = cfg_cfg[828], + cfg_cfg_5072[827] = cfg_cfg[827], + cfg_cfg_5072[826] = cfg_cfg[826], + cfg_cfg_5072[825] = cfg_cfg[825], + cfg_cfg_5072[824] = cfg_cfg[824], + cfg_cfg_5072[823] = cfg_cfg[823], + cfg_cfg_5072[822] = cfg_cfg[822], + cfg_cfg_5072[821] = cfg_cfg[821], + cfg_cfg_5072[820] = cfg_cfg[820], + cfg_cfg_5072[819] = cfg_cfg[819], + cfg_cfg_5072[818] = cfg_cfg[818], + cfg_cfg_5072[817] = cfg_cfg[817], + cfg_cfg_5072[816] = cfg_cfg[816], + cfg_cfg_5072[815] = cfg_cfg[815], + cfg_cfg_5072[814] = cfg_cfg[814], + cfg_cfg_5072[813] = cfg_cfg[813], + cfg_cfg_5072[812] = cfg_cfg[812], + cfg_cfg_5072[811] = cfg_cfg[811], + cfg_cfg_5072[810] = cfg_cfg[810], + cfg_cfg_5072[809] = cfg_cfg[809], + cfg_cfg_5072[808] = cfg_cfg[808], + cfg_cfg_5072[807] = cfg_cfg[807], + cfg_cfg_5072[806] = cfg_cfg[806], + cfg_cfg_5072[805] = cfg_cfg[805], + cfg_cfg_5072[804] = cfg_cfg[804], + cfg_cfg_5072[803] = cfg_cfg[803], + cfg_cfg_5072[802] = cfg_cfg[802], + cfg_cfg_5072[801] = cfg_cfg[801], + cfg_cfg_5072[800] = cfg_cfg[800], + cfg_cfg_5072[799] = cfg_cfg[799], + cfg_cfg_5072[798] = cfg_cfg[798], + cfg_cfg_5072[797] = cfg_cfg[797], + cfg_cfg_5072[796] = cfg_cfg[796], + cfg_cfg_5072[795] = cfg_cfg[795], + cfg_cfg_5072[794] = cfg_cfg[794], + cfg_cfg_5072[793] = cfg_cfg[793], + cfg_cfg_5072[792] = cfg_cfg[792], + cfg_cfg_5072[791] = cfg_cfg[791], + cfg_cfg_5072[790] = cfg_cfg[790], + cfg_cfg_5072[789] = cfg_cfg[789], + cfg_cfg_5072[788] = cfg_cfg[788], + cfg_cfg_5072[787] = cfg_cfg[787], + cfg_cfg_5072[786] = cfg_cfg[786], + cfg_cfg_5072[785] = cfg_cfg[785], + cfg_cfg_5072[784] = cfg_cfg[784], + cfg_cfg_5072[783] = cfg_cfg[783], + cfg_cfg_5072[782] = cfg_cfg[782], + cfg_cfg_5072[781] = cfg_cfg[781], + cfg_cfg_5072[780] = cfg_cfg[780], + cfg_cfg_5072[779] = cfg_cfg[779], + cfg_cfg_5072[778] = cfg_cfg[778], + cfg_cfg_5072[777] = cfg_cfg[777], + cfg_cfg_5072[776] = cfg_cfg[776], + cfg_cfg_5072[775] = cfg_cfg[775], + cfg_cfg_5072[774] = cfg_cfg[774], + cfg_cfg_5072[773] = cfg_cfg[773], + cfg_cfg_5072[772] = cfg_cfg[772], + cfg_cfg_5072[771] = cfg_cfg[771], + cfg_cfg_5072[770] = cfg_cfg[770], + cfg_cfg_5072[769] = cfg_cfg[769], + cfg_cfg_5072[768] = cfg_cfg[768], + cfg_cfg_5072[767] = cfg_cfg[767], + cfg_cfg_5072[766] = cfg_cfg[766], + cfg_cfg_5072[765] = cfg_cfg[765], + cfg_cfg_5072[764] = cfg_cfg[764], + cfg_cfg_5072[763] = cfg_cfg[763], + cfg_cfg_5072[762] = cfg_cfg[762], + cfg_cfg_5072[761] = cfg_cfg[761], + cfg_cfg_5072[760] = cfg_cfg[760], + cfg_cfg_5072[759] = cfg_cfg[759], + cfg_cfg_5072[758] = cfg_cfg[758], + cfg_cfg_5072[757] = cfg_cfg[757], + cfg_cfg_5072[756] = cfg_cfg[756], + cfg_cfg_5072[755] = cfg_cfg[755], + cfg_cfg_5072[754] = cfg_cfg[754], + cfg_cfg_5072[753] = cfg_cfg[753], + cfg_cfg_5072[752] = cfg_cfg[752], + cfg_cfg_5072[751] = cfg_cfg[751], + cfg_cfg_5072[750] = cfg_cfg[750], + cfg_cfg_5072[749] = cfg_cfg[749], + cfg_cfg_5072[748] = cfg_cfg[748], + cfg_cfg_5072[747] = cfg_cfg[747], + cfg_cfg_5072[746] = cfg_cfg[746], + cfg_cfg_5072[745] = cfg_cfg[745], + cfg_cfg_5072[744] = cfg_cfg[744], + cfg_cfg_5072[743] = cfg_cfg[743], + cfg_cfg_5072[742] = cfg_cfg[742], + cfg_cfg_5072[741] = cfg_cfg[741], + cfg_cfg_5072[740] = cfg_cfg[740], + cfg_cfg_5072[739] = cfg_cfg[739], + cfg_cfg_5072[738] = cfg_cfg[738], + cfg_cfg_5072[737] = cfg_cfg[737], + cfg_cfg_5072[736] = cfg_cfg[736], + cfg_cfg_5072[735] = cfg_cfg[735], + cfg_cfg_5072[734] = cfg_cfg[734], + cfg_cfg_5072[733] = cfg_cfg[733], + cfg_cfg_5072[732] = cfg_cfg[732], + cfg_cfg_5072[731] = cfg_cfg[731], + cfg_cfg_5072[730] = cfg_cfg[730], + cfg_cfg_5072[729] = cfg_cfg[729], + cfg_cfg_5072[728] = cfg_cfg[728], + cfg_cfg_5072[727] = cfg_cfg[727], + cfg_cfg_5072[726] = cfg_cfg[726], + cfg_cfg_5072[725] = cfg_cfg[725], + cfg_cfg_5072[724] = cfg_cfg[724], + cfg_cfg_5072[723] = cfg_cfg[723], + cfg_cfg_5072[722] = cfg_cfg[722], + cfg_cfg_5072[721] = cfg_cfg[721], + cfg_cfg_5072[720] = cfg_cfg[720], + cfg_cfg_5072[719] = cfg_cfg[719], + cfg_cfg_5072[718] = cfg_cfg[718], + cfg_cfg_5072[717] = cfg_cfg[717], + cfg_cfg_5072[716] = cfg_cfg[716], + cfg_cfg_5072[715] = cfg_cfg[715], + cfg_cfg_5072[714] = cfg_cfg[714], + cfg_cfg_5072[713] = cfg_cfg[713], + cfg_cfg_5072[712] = cfg_cfg[712], + cfg_cfg_5072[711] = cfg_cfg[711], + cfg_cfg_5072[710] = cfg_cfg[710], + cfg_cfg_5072[709] = cfg_cfg[709], + cfg_cfg_5072[708] = cfg_cfg[708], + cfg_cfg_5072[707] = cfg_cfg[707], + cfg_cfg_5072[706] = cfg_cfg[706], + cfg_cfg_5072[705] = cfg_cfg[705], + cfg_cfg_5072[704] = cfg_cfg[704], + cfg_cfg_5072[703] = cfg_cfg[703], + cfg_cfg_5072[702] = cfg_cfg[702], + cfg_cfg_5072[701] = cfg_cfg[701], + cfg_cfg_5072[700] = cfg_cfg[700], + cfg_cfg_5072[699] = cfg_cfg[699], + cfg_cfg_5072[698] = cfg_cfg[698], + cfg_cfg_5072[697] = cfg_cfg[697], + cfg_cfg_5072[696] = cfg_cfg[696], + cfg_cfg_5072[695] = cfg_cfg[695], + cfg_cfg_5072[694] = cfg_cfg[694], + cfg_cfg_5072[693] = cfg_cfg[693], + cfg_cfg_5072[692] = cfg_cfg[692], + cfg_cfg_5072[691] = cfg_cfg[691], + cfg_cfg_5072[690] = cfg_cfg[690], + cfg_cfg_5072[689] = cfg_cfg[689], + cfg_cfg_5072[688] = cfg_cfg[688], + cfg_cfg_5072[687] = cfg_cfg[687], + cfg_cfg_5072[686] = cfg_cfg[686], + cfg_cfg_5072[685] = cfg_cfg[685], + cfg_cfg_5072[684] = cfg_cfg[684], + cfg_cfg_5072[683] = cfg_cfg[683], + cfg_cfg_5072[682] = cfg_cfg[682], + cfg_cfg_5072[681] = cfg_cfg[681], + cfg_cfg_5072[680] = cfg_cfg[680], + cfg_cfg_5072[679] = cfg_cfg[679], + cfg_cfg_5072[678] = cfg_cfg[678], + cfg_cfg_5072[677] = cfg_cfg[677], + cfg_cfg_5072[676] = cfg_cfg[676], + cfg_cfg_5072[675] = cfg_cfg[675], + cfg_cfg_5072[674] = cfg_cfg[674], + cfg_cfg_5072[673] = cfg_cfg[673], + cfg_cfg_5072[672] = cfg_cfg[672], + cfg_cfg_5072[671] = cfg_cfg[671], + cfg_cfg_5072[670] = cfg_cfg[670], + cfg_cfg_5072[669] = cfg_cfg[669], + cfg_cfg_5072[668] = cfg_cfg[668], + cfg_cfg_5072[667] = cfg_cfg[667], + cfg_cfg_5072[666] = cfg_cfg[666], + cfg_cfg_5072[665] = cfg_cfg[665], + cfg_cfg_5072[664] = cfg_cfg[664], + cfg_cfg_5072[663] = cfg_cfg[663], + cfg_cfg_5072[662] = cfg_cfg[662], + cfg_cfg_5072[661] = cfg_cfg[661], + cfg_cfg_5072[660] = cfg_cfg[660], + cfg_cfg_5072[659] = cfg_cfg[659], + cfg_cfg_5072[658] = cfg_cfg[658], + cfg_cfg_5072[657] = cfg_cfg[657], + cfg_cfg_5072[656] = cfg_cfg[656], + cfg_cfg_5072[655] = cfg_cfg[655], + cfg_cfg_5072[654] = cfg_cfg[654], + cfg_cfg_5072[653] = cfg_cfg[653], + cfg_cfg_5072[652] = cfg_cfg[652], + cfg_cfg_5072[651] = cfg_cfg[651], + cfg_cfg_5072[650] = cfg_cfg[650], + cfg_cfg_5072[649] = cfg_cfg[649], + cfg_cfg_5072[648] = cfg_cfg[648], + cfg_cfg_5072[647] = cfg_cfg[647], + cfg_cfg_5072[646] = cfg_cfg[646], + cfg_cfg_5072[645] = cfg_cfg[645], + cfg_cfg_5072[644] = cfg_cfg[644], + cfg_cfg_5072[643] = cfg_cfg[643], + cfg_cfg_5072[642] = cfg_cfg[642], + cfg_cfg_5072[641] = cfg_cfg[641], + cfg_cfg_5072[640] = cfg_cfg[640], + cfg_cfg_5072[639] = cfg_cfg[639], + cfg_cfg_5072[638] = cfg_cfg[638], + cfg_cfg_5072[637] = cfg_cfg[637], + cfg_cfg_5072[636] = cfg_cfg[636], + cfg_cfg_5072[635] = cfg_cfg[635], + cfg_cfg_5072[634] = cfg_cfg[634], + cfg_cfg_5072[633] = cfg_cfg[633], + cfg_cfg_5072[632] = cfg_cfg[632], + cfg_cfg_5072[631] = cfg_cfg[631], + cfg_cfg_5072[630] = cfg_cfg[630], + cfg_cfg_5072[629] = cfg_cfg[629], + cfg_cfg_5072[628] = cfg_cfg[628], + cfg_cfg_5072[627] = cfg_cfg[627], + cfg_cfg_5072[626] = cfg_cfg[626], + cfg_cfg_5072[625] = cfg_cfg[625], + cfg_cfg_5072[624] = cfg_cfg[624], + cfg_cfg_5072[623] = cfg_cfg[623], + cfg_cfg_5072[622] = cfg_cfg[622], + cfg_cfg_5072[621] = cfg_cfg[621], + cfg_cfg_5072[620] = cfg_cfg[620], + cfg_cfg_5072[619] = cfg_cfg[619], + cfg_cfg_5072[618] = cfg_cfg[618], + cfg_cfg_5072[617] = cfg_cfg[617], + cfg_cfg_5072[616] = cfg_cfg[616], + cfg_cfg_5072[615] = cfg_cfg[615], + cfg_cfg_5072[614] = cfg_cfg[614], + cfg_cfg_5072[613] = cfg_cfg[613], + cfg_cfg_5072[612] = cfg_cfg[612], + cfg_cfg_5072[611] = cfg_cfg[611], + cfg_cfg_5072[610] = cfg_cfg[610], + cfg_cfg_5072[609] = cfg_cfg[609], + cfg_cfg_5072[608] = cfg_cfg[608], + cfg_cfg_5072[607] = cfg_cfg[607], + cfg_cfg_5072[606] = cfg_cfg[606], + cfg_cfg_5072[605] = cfg_cfg[605], + cfg_cfg_5072[604] = cfg_cfg[604], + cfg_cfg_5072[603] = cfg_cfg[603], + cfg_cfg_5072[602] = cfg_cfg[602], + cfg_cfg_5072[601] = cfg_cfg[601], + cfg_cfg_5072[600] = cfg_cfg[600], + cfg_cfg_5072[599] = cfg_cfg[599], + cfg_cfg_5072[598] = cfg_cfg[598], + cfg_cfg_5072[597] = cfg_cfg[597], + cfg_cfg_5072[596] = cfg_cfg[596], + cfg_cfg_5072[595] = cfg_cfg[595], + cfg_cfg_5072[594] = cfg_cfg[594], + cfg_cfg_5072[593] = cfg_cfg[593], + cfg_cfg_5072[592] = cfg_cfg[592], + cfg_cfg_5072[591] = cfg_cfg[591], + cfg_cfg_5072[590] = cfg_cfg[590], + cfg_cfg_5072[589] = cfg_cfg[589], + cfg_cfg_5072[588] = cfg_cfg[588], + cfg_cfg_5072[587] = cfg_cfg[587], + cfg_cfg_5072[586] = cfg_cfg[586], + cfg_cfg_5072[585] = cfg_cfg[585], + cfg_cfg_5072[584] = cfg_cfg[584], + cfg_cfg_5072[583] = cfg_cfg[583], + cfg_cfg_5072[582] = cfg_cfg[582], + cfg_cfg_5072[581] = cfg_cfg[581], + cfg_cfg_5072[580] = cfg_cfg[580], + cfg_cfg_5072[579] = cfg_cfg[579], + cfg_cfg_5072[578] = cfg_cfg[578], + cfg_cfg_5072[577] = cfg_cfg[577], + cfg_cfg_5072[576] = cfg_cfg[576], + cfg_cfg_5072[575] = cfg_cfg[575], + cfg_cfg_5072[574] = cfg_cfg[574], + cfg_cfg_5072[573] = cfg_cfg[573], + cfg_cfg_5072[572] = cfg_cfg[572], + cfg_cfg_5072[571] = cfg_cfg[571], + cfg_cfg_5072[570] = cfg_cfg[570], + cfg_cfg_5072[569] = cfg_cfg[569], + cfg_cfg_5072[568] = cfg_cfg[568], + cfg_cfg_5072[567] = cfg_cfg[567], + cfg_cfg_5072[566] = cfg_cfg[566], + cfg_cfg_5072[565] = cfg_cfg[565], + cfg_cfg_5072[564] = cfg_cfg[564], + cfg_cfg_5072[563] = cfg_cfg[563], + cfg_cfg_5072[562] = cfg_cfg[562], + cfg_cfg_5072[561] = cfg_cfg[561], + cfg_cfg_5072[560] = cfg_cfg[560], + cfg_cfg_5072[559] = cfg_cfg[559], + cfg_cfg_5072[558] = cfg_cfg[558], + cfg_cfg_5072[557] = cfg_cfg[557], + cfg_cfg_5072[556] = cfg_cfg[556], + cfg_cfg_5072[555] = cfg_cfg[555], + cfg_cfg_5072[554] = cfg_cfg[554], + cfg_cfg_5072[553] = cfg_cfg[553], + cfg_cfg_5072[552] = cfg_cfg[552], + cfg_cfg_5072[551] = cfg_cfg[551], + cfg_cfg_5072[550] = cfg_cfg[550], + cfg_cfg_5072[549] = cfg_cfg[549], + cfg_cfg_5072[548] = cfg_cfg[548], + cfg_cfg_5072[547] = cfg_cfg[547], + cfg_cfg_5072[546] = cfg_cfg[546], + cfg_cfg_5072[545] = cfg_cfg[545], + cfg_cfg_5072[544] = cfg_cfg[544], + cfg_cfg_5072[543] = cfg_cfg[543], + cfg_cfg_5072[542] = cfg_cfg[542], + cfg_cfg_5072[541] = cfg_cfg[541], + cfg_cfg_5072[540] = cfg_cfg[540], + cfg_cfg_5072[539] = cfg_cfg[539], + cfg_cfg_5072[538] = cfg_cfg[538], + cfg_cfg_5072[537] = cfg_cfg[537], + cfg_cfg_5072[536] = cfg_cfg[536], + cfg_cfg_5072[535] = cfg_cfg[535], + cfg_cfg_5072[534] = cfg_cfg[534], + cfg_cfg_5072[533] = cfg_cfg[533], + cfg_cfg_5072[532] = cfg_cfg[532], + cfg_cfg_5072[531] = cfg_cfg[531], + cfg_cfg_5072[530] = cfg_cfg[530], + cfg_cfg_5072[529] = cfg_cfg[529], + cfg_cfg_5072[528] = cfg_cfg[528], + cfg_cfg_5072[527] = cfg_cfg[527], + cfg_cfg_5072[526] = cfg_cfg[526], + cfg_cfg_5072[525] = cfg_cfg[525], + cfg_cfg_5072[524] = cfg_cfg[524], + cfg_cfg_5072[523] = cfg_cfg[523], + cfg_cfg_5072[522] = cfg_cfg[522], + cfg_cfg_5072[521] = cfg_cfg[521], + cfg_cfg_5072[520] = cfg_cfg[520], + cfg_cfg_5072[519] = cfg_cfg[519], + cfg_cfg_5072[518] = cfg_cfg[518], + cfg_cfg_5072[517] = cfg_cfg[517], + cfg_cfg_5072[516] = cfg_cfg[516], + cfg_cfg_5072[515] = cfg_cfg[515], + cfg_cfg_5072[514] = cfg_cfg[514], + cfg_cfg_5072[513] = cfg_cfg[513], + cfg_cfg_5072[512] = cfg_cfg[512], + cfg_cfg_5072[511] = cfg_cfg[511], + cfg_cfg_5072[510] = cfg_cfg[510], + cfg_cfg_5072[509] = cfg_cfg[509], + cfg_cfg_5072[508] = cfg_cfg[508], + cfg_cfg_5072[507] = cfg_cfg[507], + cfg_cfg_5072[506] = cfg_cfg[506], + cfg_cfg_5072[505] = cfg_cfg[505], + cfg_cfg_5072[504] = cfg_cfg[504], + cfg_cfg_5072[503] = cfg_cfg[503], + cfg_cfg_5072[502] = cfg_cfg[502], + cfg_cfg_5072[501] = cfg_cfg[501], + cfg_cfg_5072[500] = cfg_cfg[500], + cfg_cfg_5072[499] = cfg_cfg[499], + cfg_cfg_5072[498] = cfg_cfg[498], + cfg_cfg_5072[497] = cfg_cfg[497], + cfg_cfg_5072[496] = cfg_cfg[496], + cfg_cfg_5072[495] = cfg_cfg[495], + cfg_cfg_5072[494] = cfg_cfg[494], + cfg_cfg_5072[493] = cfg_cfg[493], + cfg_cfg_5072[492] = cfg_cfg[492], + cfg_cfg_5072[491] = cfg_cfg[491], + cfg_cfg_5072[490] = cfg_cfg[490], + cfg_cfg_5072[489] = cfg_cfg[489], + cfg_cfg_5072[488] = cfg_cfg[488], + cfg_cfg_5072[487] = cfg_cfg[487], + cfg_cfg_5072[486] = cfg_cfg[486], + cfg_cfg_5072[485] = cfg_cfg[485], + cfg_cfg_5072[484] = cfg_cfg[484], + cfg_cfg_5072[483] = cfg_cfg[483], + cfg_cfg_5072[482] = cfg_cfg[482], + cfg_cfg_5072[481] = cfg_cfg[481], + cfg_cfg_5072[480] = cfg_cfg[480], + cfg_cfg_5072[479] = cfg_cfg[479], + cfg_cfg_5072[478] = cfg_cfg[478], + cfg_cfg_5072[477] = cfg_cfg[477], + cfg_cfg_5072[476] = cfg_cfg[476], + cfg_cfg_5072[475] = cfg_cfg[475], + cfg_cfg_5072[474] = cfg_cfg[474], + cfg_cfg_5072[473] = cfg_cfg[473], + cfg_cfg_5072[472] = cfg_cfg[472], + cfg_cfg_5072[471] = cfg_cfg[471], + cfg_cfg_5072[470] = cfg_cfg[470], + cfg_cfg_5072[469] = cfg_cfg[469], + cfg_cfg_5072[468] = cfg_cfg[468], + cfg_cfg_5072[467] = cfg_cfg[467], + cfg_cfg_5072[466] = cfg_cfg[466], + cfg_cfg_5072[465] = cfg_cfg[465], + cfg_cfg_5072[464] = cfg_cfg[464], + cfg_cfg_5072[463] = cfg_cfg[463], + cfg_cfg_5072[462] = cfg_cfg[462], + cfg_cfg_5072[461] = cfg_cfg[461], + cfg_cfg_5072[460] = cfg_cfg[460], + cfg_cfg_5072[459] = cfg_cfg[459], + cfg_cfg_5072[458] = cfg_cfg[458], + cfg_cfg_5072[457] = cfg_cfg[457], + cfg_cfg_5072[456] = cfg_cfg[456], + cfg_cfg_5072[455] = cfg_cfg[455], + cfg_cfg_5072[454] = cfg_cfg[454], + cfg_cfg_5072[453] = cfg_cfg[453], + cfg_cfg_5072[452] = cfg_cfg[452], + cfg_cfg_5072[451] = cfg_cfg[451], + cfg_cfg_5072[450] = cfg_cfg[450], + cfg_cfg_5072[449] = cfg_cfg[449], + cfg_cfg_5072[448] = cfg_cfg[448], + cfg_cfg_5072[447] = cfg_cfg[447], + cfg_cfg_5072[446] = cfg_cfg[446], + cfg_cfg_5072[445] = cfg_cfg[445], + cfg_cfg_5072[444] = cfg_cfg[444], + cfg_cfg_5072[443] = cfg_cfg[443], + cfg_cfg_5072[442] = cfg_cfg[442], + cfg_cfg_5072[441] = cfg_cfg[441], + cfg_cfg_5072[440] = cfg_cfg[440], + cfg_cfg_5072[439] = cfg_cfg[439], + cfg_cfg_5072[438] = cfg_cfg[438], + cfg_cfg_5072[437] = cfg_cfg[437], + cfg_cfg_5072[436] = cfg_cfg[436], + cfg_cfg_5072[435] = cfg_cfg[435], + cfg_cfg_5072[434] = cfg_cfg[434], + cfg_cfg_5072[433] = cfg_cfg[433], + cfg_cfg_5072[432] = cfg_cfg[432], + cfg_cfg_5072[431] = cfg_cfg[431], + cfg_cfg_5072[430] = cfg_cfg[430], + cfg_cfg_5072[429] = cfg_cfg[429], + cfg_cfg_5072[428] = cfg_cfg[428], + cfg_cfg_5072[427] = cfg_cfg[427], + cfg_cfg_5072[426] = cfg_cfg[426], + cfg_cfg_5072[425] = cfg_cfg[425], + cfg_cfg_5072[424] = cfg_cfg[424], + cfg_cfg_5072[423] = cfg_cfg[423], + cfg_cfg_5072[422] = cfg_cfg[422], + cfg_cfg_5072[421] = cfg_cfg[421], + cfg_cfg_5072[420] = cfg_cfg[420], + cfg_cfg_5072[419] = cfg_cfg[419], + cfg_cfg_5072[418] = cfg_cfg[418], + cfg_cfg_5072[417] = cfg_cfg[417], + cfg_cfg_5072[416] = cfg_cfg[416], + cfg_cfg_5072[415] = cfg_cfg[415], + cfg_cfg_5072[414] = cfg_cfg[414], + cfg_cfg_5072[413] = cfg_cfg[413], + cfg_cfg_5072[412] = cfg_cfg[412], + cfg_cfg_5072[411] = cfg_cfg[411], + cfg_cfg_5072[410] = cfg_cfg[410], + cfg_cfg_5072[409] = cfg_cfg[409], + cfg_cfg_5072[408] = cfg_cfg[408], + cfg_cfg_5072[407] = cfg_cfg[407], + cfg_cfg_5072[406] = cfg_cfg[406], + cfg_cfg_5072[405] = cfg_cfg[405], + cfg_cfg_5072[404] = cfg_cfg[404], + cfg_cfg_5072[403] = cfg_cfg[403], + cfg_cfg_5072[402] = cfg_cfg[402], + cfg_cfg_5072[401] = cfg_cfg[401], + cfg_cfg_5072[400] = cfg_cfg[400], + cfg_cfg_5072[399] = cfg_cfg[399], + cfg_cfg_5072[398] = cfg_cfg[398], + cfg_cfg_5072[397] = cfg_cfg[397], + cfg_cfg_5072[396] = cfg_cfg[396], + cfg_cfg_5072[395] = cfg_cfg[395], + cfg_cfg_5072[394] = cfg_cfg[394], + cfg_cfg_5072[393] = cfg_cfg[393], + cfg_cfg_5072[392] = cfg_cfg[392], + cfg_cfg_5072[391] = cfg_cfg[391], + cfg_cfg_5072[390] = cfg_cfg[390], + cfg_cfg_5072[389] = cfg_cfg[389], + cfg_cfg_5072[388] = cfg_cfg[388], + cfg_cfg_5072[387] = cfg_cfg[387], + cfg_cfg_5072[386] = cfg_cfg[386], + cfg_cfg_5072[385] = cfg_cfg[385], + cfg_cfg_5072[384] = cfg_cfg[384], + cfg_cfg_5072[383] = cfg_cfg[383], + cfg_cfg_5072[382] = cfg_cfg[382], + cfg_cfg_5072[381] = cfg_cfg[381], + cfg_cfg_5072[380] = cfg_cfg[380], + cfg_cfg_5072[379] = cfg_cfg[379], + cfg_cfg_5072[378] = cfg_cfg[378], + cfg_cfg_5072[377] = cfg_cfg[377], + cfg_cfg_5072[376] = cfg_cfg[376], + cfg_cfg_5072[375] = cfg_cfg[375], + cfg_cfg_5072[374] = cfg_cfg[374], + cfg_cfg_5072[373] = cfg_cfg[373], + cfg_cfg_5072[372] = cfg_cfg[372], + cfg_cfg_5072[371] = cfg_cfg[371], + cfg_cfg_5072[370] = cfg_cfg[370], + cfg_cfg_5072[369] = cfg_cfg[369], + cfg_cfg_5072[368] = cfg_cfg[368], + cfg_cfg_5072[367] = cfg_cfg[367], + cfg_cfg_5072[366] = cfg_cfg[366], + cfg_cfg_5072[365] = cfg_cfg[365], + cfg_cfg_5072[364] = cfg_cfg[364], + cfg_cfg_5072[363] = cfg_cfg[363], + cfg_cfg_5072[362] = cfg_cfg[362], + cfg_cfg_5072[361] = cfg_cfg[361], + cfg_cfg_5072[360] = cfg_cfg[360], + cfg_cfg_5072[359] = cfg_cfg[359], + cfg_cfg_5072[358] = cfg_cfg[358], + cfg_cfg_5072[357] = cfg_cfg[357], + cfg_cfg_5072[356] = cfg_cfg[356], + cfg_cfg_5072[355] = cfg_cfg[355], + cfg_cfg_5072[354] = cfg_cfg[354], + cfg_cfg_5072[353] = cfg_cfg[353], + cfg_cfg_5072[352] = cfg_cfg[352], + cfg_cfg_5072[351] = cfg_cfg[351], + cfg_cfg_5072[350] = cfg_cfg[350], + cfg_cfg_5072[349] = cfg_cfg[349], + cfg_cfg_5072[348] = cfg_cfg[348], + cfg_cfg_5072[347] = cfg_cfg[347], + cfg_cfg_5072[346] = cfg_cfg[346], + cfg_cfg_5072[345] = cfg_cfg[345], + cfg_cfg_5072[344] = cfg_cfg[344], + cfg_cfg_5072[343] = cfg_cfg[343], + cfg_cfg_5072[342] = cfg_cfg[342], + cfg_cfg_5072[341] = cfg_cfg[341], + cfg_cfg_5072[340] = cfg_cfg[340], + cfg_cfg_5072[339] = cfg_cfg[339], + cfg_cfg_5072[338] = cfg_cfg[338], + cfg_cfg_5072[337] = cfg_cfg[337], + cfg_cfg_5072[336] = cfg_cfg[336], + cfg_cfg_5072[335] = cfg_cfg[335], + cfg_cfg_5072[334] = cfg_cfg[334], + cfg_cfg_5072[333] = cfg_cfg[333], + cfg_cfg_5072[332] = cfg_cfg[332], + cfg_cfg_5072[331] = cfg_cfg[331], + cfg_cfg_5072[330] = cfg_cfg[330], + cfg_cfg_5072[329] = cfg_cfg[329], + cfg_cfg_5072[328] = cfg_cfg[328], + cfg_cfg_5072[327] = cfg_cfg[327], + cfg_cfg_5072[326] = cfg_cfg[326], + cfg_cfg_5072[325] = cfg_cfg[325], + cfg_cfg_5072[324] = cfg_cfg[324], + cfg_cfg_5072[323] = cfg_cfg[323], + cfg_cfg_5072[322] = cfg_cfg[322], + cfg_cfg_5072[321] = cfg_cfg[321], + cfg_cfg_5072[320] = cfg_cfg[320], + cfg_cfg_5072[319] = cfg_cfg[319], + cfg_cfg_5072[318] = cfg_cfg[318], + cfg_cfg_5072[317] = cfg_cfg[317], + cfg_cfg_5072[316] = cfg_cfg[316], + cfg_cfg_5072[315] = cfg_cfg[315], + cfg_cfg_5072[314] = cfg_cfg[314], + cfg_cfg_5072[313] = cfg_cfg[313], + cfg_cfg_5072[312] = cfg_cfg[312], + cfg_cfg_5072[311] = cfg_cfg[311], + cfg_cfg_5072[310] = cfg_cfg[310], + cfg_cfg_5072[309] = cfg_cfg[309], + cfg_cfg_5072[308] = cfg_cfg[308], + cfg_cfg_5072[307] = cfg_cfg[307], + cfg_cfg_5072[306] = cfg_cfg[306], + cfg_cfg_5072[305] = cfg_cfg[305], + cfg_cfg_5072[304] = cfg_cfg[304], + cfg_cfg_5072[303] = cfg_cfg[303], + cfg_cfg_5072[302] = cfg_cfg[302], + cfg_cfg_5072[301] = cfg_cfg[301], + cfg_cfg_5072[300] = cfg_cfg[300], + cfg_cfg_5072[299] = cfg_cfg[299], + cfg_cfg_5072[298] = cfg_cfg[298], + cfg_cfg_5072[297] = cfg_cfg[297], + cfg_cfg_5072[296] = cfg_cfg[296], + cfg_cfg_5072[295] = cfg_cfg[295], + cfg_cfg_5072[294] = cfg_cfg[294], + cfg_cfg_5072[293] = cfg_cfg[293], + cfg_cfg_5072[292] = cfg_cfg[292], + cfg_cfg_5072[291] = cfg_cfg[291], + cfg_cfg_5072[290] = cfg_cfg[290], + cfg_cfg_5072[289] = cfg_cfg[289], + cfg_cfg_5072[288] = cfg_cfg[288], + cfg_cfg_5072[287] = cfg_cfg[287], + cfg_cfg_5072[286] = cfg_cfg[286], + cfg_cfg_5072[285] = cfg_cfg[285], + cfg_cfg_5072[284] = cfg_cfg[284], + cfg_cfg_5072[283] = cfg_cfg[283], + cfg_cfg_5072[282] = cfg_cfg[282], + cfg_cfg_5072[281] = cfg_cfg[281], + cfg_cfg_5072[280] = cfg_cfg[280], + cfg_cfg_5072[279] = cfg_cfg[279], + cfg_cfg_5072[278] = cfg_cfg[278], + cfg_cfg_5072[277] = cfg_cfg[277], + cfg_cfg_5072[276] = cfg_cfg[276], + cfg_cfg_5072[275] = cfg_cfg[275], + cfg_cfg_5072[274] = cfg_cfg[274], + cfg_cfg_5072[273] = cfg_cfg[273], + cfg_cfg_5072[272] = cfg_cfg[272], + cfg_cfg_5072[271] = cfg_cfg[271], + cfg_cfg_5072[270] = cfg_cfg[270], + cfg_cfg_5072[269] = cfg_cfg[269], + cfg_cfg_5072[268] = cfg_cfg[268], + cfg_cfg_5072[267] = cfg_cfg[267], + cfg_cfg_5072[266] = cfg_cfg[266], + cfg_cfg_5072[265] = cfg_cfg[265], + cfg_cfg_5072[264] = cfg_cfg[264], + cfg_cfg_5072[263] = cfg_cfg[263], + cfg_cfg_5072[262] = cfg_cfg[262], + cfg_cfg_5072[261] = cfg_cfg[261], + cfg_cfg_5072[260] = cfg_cfg[260], + cfg_cfg_5072[259] = cfg_cfg[259], + cfg_cfg_5072[258] = cfg_cfg[258], + cfg_cfg_5072[257] = cfg_cfg[257], + cfg_cfg_5072[256] = cfg_cfg[256], + cfg_cfg_5072[255] = cfg_cfg[255], + cfg_cfg_5072[254] = cfg_cfg[254], + cfg_cfg_5072[253] = cfg_cfg[253], + cfg_cfg_5072[252] = cfg_cfg[252], + cfg_cfg_5072[251] = cfg_cfg[251], + cfg_cfg_5072[250] = cfg_cfg[250], + cfg_cfg_5072[249] = cfg_cfg[249], + cfg_cfg_5072[248] = cfg_cfg[248], + cfg_cfg_5072[247] = cfg_cfg[247], + cfg_cfg_5072[246] = cfg_cfg[246], + cfg_cfg_5072[245] = cfg_cfg[245], + cfg_cfg_5072[244] = cfg_cfg[244], + cfg_cfg_5072[243] = cfg_cfg[243], + cfg_cfg_5072[242] = cfg_cfg[242], + cfg_cfg_5072[241] = cfg_cfg[241], + cfg_cfg_5072[240] = cfg_cfg[240], + cfg_cfg_5072[239] = cfg_cfg[239], + cfg_cfg_5072[238] = cfg_cfg[238], + cfg_cfg_5072[237] = cfg_cfg[237], + cfg_cfg_5072[236] = cfg_cfg[236], + cfg_cfg_5072[235] = cfg_cfg[235], + cfg_cfg_5072[234] = cfg_cfg[234], + cfg_cfg_5072[233] = cfg_cfg[233], + cfg_cfg_5072[232] = cfg_cfg[232], + cfg_cfg_5072[231] = cfg_cfg[231], + cfg_cfg_5072[230] = cfg_cfg[230], + cfg_cfg_5072[229] = cfg_cfg[229], + cfg_cfg_5072[228] = cfg_cfg[228], + cfg_cfg_5072[227] = cfg_cfg[227], + cfg_cfg_5072[226] = cfg_cfg[226], + cfg_cfg_5072[225] = cfg_cfg[225], + cfg_cfg_5072[224] = cfg_cfg[224], + cfg_cfg_5072[223] = cfg_cfg[223], + cfg_cfg_5072[222] = cfg_cfg[222], + cfg_cfg_5072[221] = cfg_cfg[221], + cfg_cfg_5072[220] = cfg_cfg[220], + cfg_cfg_5072[219] = cfg_cfg[219], + cfg_cfg_5072[218] = cfg_cfg[218], + cfg_cfg_5072[217] = cfg_cfg[217], + cfg_cfg_5072[216] = cfg_cfg[216], + cfg_cfg_5072[215] = cfg_cfg[215], + cfg_cfg_5072[214] = cfg_cfg[214], + cfg_cfg_5072[213] = cfg_cfg[213], + cfg_cfg_5072[212] = cfg_cfg[212], + cfg_cfg_5072[211] = cfg_cfg[211], + cfg_cfg_5072[210] = cfg_cfg[210], + cfg_cfg_5072[209] = cfg_cfg[209], + cfg_cfg_5072[208] = cfg_cfg[208], + cfg_cfg_5072[207] = cfg_cfg[207], + cfg_cfg_5072[206] = cfg_cfg[206], + cfg_cfg_5072[205] = cfg_cfg[205], + cfg_cfg_5072[204] = cfg_cfg[204], + cfg_cfg_5072[203] = cfg_cfg[203], + cfg_cfg_5072[202] = cfg_cfg[202], + cfg_cfg_5072[201] = cfg_cfg[201], + cfg_cfg_5072[200] = cfg_cfg[200], + cfg_cfg_5072[199] = cfg_cfg[199], + cfg_cfg_5072[198] = cfg_cfg[198], + cfg_cfg_5072[197] = cfg_cfg[197], + cfg_cfg_5072[196] = cfg_cfg[196], + cfg_cfg_5072[195] = cfg_cfg[195], + cfg_cfg_5072[194] = cfg_cfg[194], + cfg_cfg_5072[193] = cfg_cfg[193], + cfg_cfg_5072[192] = cfg_cfg[192], + cfg_cfg_5072[191] = cfg_cfg[191], + cfg_cfg_5072[190] = cfg_cfg[190], + cfg_cfg_5072[189] = cfg_cfg[189], + cfg_cfg_5072[188] = cfg_cfg[188], + cfg_cfg_5072[187] = cfg_cfg[187], + cfg_cfg_5072[186] = cfg_cfg[186], + cfg_cfg_5072[185] = cfg_cfg[185], + cfg_cfg_5072[184] = cfg_cfg[184], + cfg_cfg_5072[183] = cfg_cfg[183], + cfg_cfg_5072[182] = cfg_cfg[182], + cfg_cfg_5072[181] = cfg_cfg[181], + cfg_cfg_5072[180] = cfg_cfg[180], + cfg_cfg_5072[179] = cfg_cfg[179], + cfg_cfg_5072[178] = cfg_cfg[178], + cfg_cfg_5072[177] = cfg_cfg[177], + cfg_cfg_5072[176] = cfg_cfg[176], + cfg_cfg_5072[175] = cfg_cfg[175], + cfg_cfg_5072[174] = cfg_cfg[174], + cfg_cfg_5072[173] = cfg_cfg[173], + cfg_cfg_5072[172] = cfg_cfg[172], + cfg_cfg_5072[171] = cfg_cfg[171], + cfg_cfg_5072[170] = cfg_cfg[170], + cfg_cfg_5072[169] = cfg_cfg[169], + cfg_cfg_5072[168] = cfg_cfg[168], + cfg_cfg_5072[167] = cfg_cfg[167], + cfg_cfg_5072[166] = cfg_cfg[166], + cfg_cfg_5072[165] = cfg_cfg[165], + cfg_cfg_5072[164] = cfg_cfg[164], + cfg_cfg_5072[163] = cfg_cfg[163], + cfg_cfg_5072[162] = cfg_cfg[162], + cfg_cfg_5072[161] = cfg_cfg[161], + cfg_cfg_5072[160] = cfg_cfg[160], + cfg_cfg_5072[159] = cfg_cfg[159], + cfg_cfg_5072[158] = cfg_cfg[158], + cfg_cfg_5072[157] = cfg_cfg[157], + cfg_cfg_5072[156] = cfg_cfg[156], + cfg_cfg_5072[155] = cfg_cfg[155], + cfg_cfg_5072[154] = cfg_cfg[154], + cfg_cfg_5072[153] = cfg_cfg[153], + cfg_cfg_5072[152] = cfg_cfg[152], + cfg_cfg_5072[151] = cfg_cfg[151], + cfg_cfg_5072[150] = cfg_cfg[150], + cfg_cfg_5072[149] = cfg_cfg[149], + cfg_cfg_5072[148] = cfg_cfg[148], + cfg_cfg_5072[147] = cfg_cfg[147], + cfg_cfg_5072[146] = cfg_cfg[146], + cfg_cfg_5072[145] = cfg_cfg[145], + cfg_cfg_5072[144] = cfg_cfg[144], + cfg_cfg_5072[143] = cfg_cfg[143], + cfg_cfg_5072[142] = cfg_cfg[142], + cfg_cfg_5072[141] = cfg_cfg[141], + cfg_cfg_5072[140] = cfg_cfg[140], + cfg_cfg_5072[139] = cfg_cfg[139], + cfg_cfg_5072[138] = cfg_cfg[138], + cfg_cfg_5072[137] = cfg_cfg[137], + cfg_cfg_5072[136] = cfg_cfg[136], + cfg_cfg_5072[135] = cfg_cfg[135], + cfg_cfg_5072[134] = cfg_cfg[134], + cfg_cfg_5072[133] = cfg_cfg[133], + cfg_cfg_5072[132] = cfg_cfg[132], + cfg_cfg_5072[131] = cfg_cfg[131], + cfg_cfg_5072[130] = cfg_cfg[130], + cfg_cfg_5072[129] = cfg_cfg[129], + cfg_cfg_5072[128] = cfg_cfg[128], + cfg_cfg_5072[127] = cfg_cfg[127], + cfg_cfg_5072[126] = cfg_cfg[126], + cfg_cfg_5072[125] = cfg_cfg[125], + cfg_cfg_5072[124] = cfg_cfg[124], + cfg_cfg_5072[123] = cfg_cfg[123], + cfg_cfg_5072[122] = cfg_cfg[122], + cfg_cfg_5072[121] = cfg_cfg[121], + cfg_cfg_5072[120] = cfg_cfg[120], + cfg_cfg_5072[119] = cfg_cfg[119], + cfg_cfg_5072[118] = cfg_cfg[118], + cfg_cfg_5072[117] = cfg_cfg[117], + cfg_cfg_5072[116] = cfg_cfg[116], + cfg_cfg_5072[115] = cfg_cfg[115], + cfg_cfg_5072[114] = cfg_cfg[114], + cfg_cfg_5072[113] = cfg_cfg[113], + cfg_cfg_5072[112] = cfg_cfg[112], + cfg_cfg_5072[111] = cfg_cfg[111], + cfg_cfg_5072[110] = cfg_cfg[110], + cfg_cfg_5072[109] = cfg_cfg[109], + cfg_cfg_5072[108] = cfg_cfg[108], + cfg_cfg_5072[107] = cfg_cfg[107], + cfg_cfg_5072[106] = cfg_cfg[106], + cfg_cfg_5072[105] = cfg_cfg[105], + cfg_cfg_5072[104] = cfg_cfg[104], + cfg_cfg_5072[103] = cfg_cfg[103], + cfg_cfg_5072[102] = cfg_cfg[102], + cfg_cfg_5072[101] = cfg_cfg[101], + cfg_cfg_5072[100] = cfg_cfg[100], + cfg_cfg_5072[99] = cfg_cfg[99], + cfg_cfg_5072[98] = cfg_cfg[98], + cfg_cfg_5072[97] = cfg_cfg[97], + cfg_cfg_5072[96] = cfg_cfg[96], + cfg_cfg_5072[95] = cfg_cfg[95], + cfg_cfg_5072[94] = cfg_cfg[94], + cfg_cfg_5072[93] = cfg_cfg[93], + cfg_cfg_5072[92] = cfg_cfg[92], + cfg_cfg_5072[91] = cfg_cfg[91], + cfg_cfg_5072[90] = cfg_cfg[90], + cfg_cfg_5072[89] = cfg_cfg[89], + cfg_cfg_5072[88] = cfg_cfg[88], + cfg_cfg_5072[87] = cfg_cfg[87], + cfg_cfg_5072[86] = cfg_cfg[86], + cfg_cfg_5072[85] = cfg_cfg[85], + cfg_cfg_5072[84] = cfg_cfg[84], + cfg_cfg_5072[83] = cfg_cfg[83], + cfg_cfg_5072[82] = cfg_cfg[82], + cfg_cfg_5072[81] = cfg_cfg[81], + cfg_cfg_5072[80] = cfg_cfg[80], + cfg_cfg_5072[79] = cfg_cfg[79], + cfg_cfg_5072[78] = cfg_cfg[78], + cfg_cfg_5072[77] = cfg_cfg[77], + cfg_cfg_5072[76] = cfg_cfg[76], + cfg_cfg_5072[75] = cfg_cfg[75], + cfg_cfg_5072[74] = cfg_cfg[74], + cfg_cfg_5072[73] = cfg_cfg[73], + cfg_cfg_5072[72] = cfg_cfg[72], + cfg_cfg_5072[71] = cfg_cfg[71], + cfg_cfg_5072[70] = cfg_cfg[70], + cfg_cfg_5072[69] = cfg_cfg[69], + cfg_cfg_5072[68] = cfg_cfg[68], + cfg_cfg_5072[67] = cfg_cfg[67], + cfg_cfg_5072[66] = cfg_cfg[66], + cfg_cfg_5072[65] = cfg_cfg[65], + cfg_cfg_5072[64] = cfg_cfg[64], + cfg_cfg_5072[63] = cfg_cfg[63], + cfg_cfg_5072[62] = cfg_cfg[62], + cfg_cfg_5072[61] = cfg_cfg[61], + cfg_cfg_5072[60] = cfg_cfg[60], + cfg_cfg_5072[59] = cfg_cfg[59], + cfg_cfg_5072[58] = cfg_cfg[58], + cfg_cfg_5072[57] = cfg_cfg[57], + cfg_cfg_5072[56] = cfg_cfg[56], + cfg_cfg_5072[55] = cfg_cfg[55], + cfg_cfg_5072[54] = cfg_cfg[54], + cfg_cfg_5072[53] = cfg_cfg[53], + cfg_cfg_5072[52] = cfg_cfg[52], + cfg_cfg_5072[51] = cfg_cfg[51], + cfg_cfg_5072[50] = cfg_cfg[50], + cfg_cfg_5072[49] = cfg_cfg[49], + cfg_cfg_5072[48] = cfg_cfg[48], + cfg_cfg_5072[47] = cfg_cfg[47], + cfg_cfg_5072[46] = cfg_cfg[46], + cfg_cfg_5072[45] = cfg_cfg[45], + cfg_cfg_5072[44] = cfg_cfg[44], + cfg_cfg_5072[43] = cfg_cfg[43], + cfg_cfg_5072[42] = cfg_cfg[42], + cfg_cfg_5072[41] = cfg_cfg[41], + cfg_cfg_5072[40] = cfg_cfg[40], + cfg_cfg_5072[39] = cfg_cfg[39], + cfg_cfg_5072[38] = cfg_cfg[38], + cfg_cfg_5072[37] = cfg_cfg[37], + cfg_cfg_5072[36] = cfg_cfg[36], + cfg_cfg_5072[35] = cfg_cfg[35], + cfg_cfg_5072[34] = cfg_cfg[34], + cfg_cfg_5072[33] = cfg_cfg[33], + cfg_cfg_5072[32] = cfg_cfg[32], + cfg_cfg_5072[31] = cfg_cfg[31], + cfg_cfg_5072[30] = cfg_cfg[30], + cfg_cfg_5072[29] = cfg_cfg[29], + cfg_cfg_5072[28] = cfg_cfg[28], + cfg_cfg_5072[27] = cfg_cfg[27], + cfg_cfg_5072[26] = cfg_cfg[26], + cfg_cfg_5072[25] = cfg_cfg[25], + cfg_cfg_5072[24] = cfg_cfg[24], + cfg_cfg_5072[23] = cfg_cfg[23], + cfg_cfg_5072[22] = cfg_cfg[22], + cfg_cfg_5072[21] = cfg_cfg[21], + cfg_cfg_5072[20] = cfg_cfg[20], + cfg_cfg_5072[19] = cfg_cfg[19], + cfg_cfg_5072[18] = cfg_cfg[18], + cfg_cfg_5072[17] = cfg_cfg[17], + cfg_cfg_5072[16] = cfg_cfg[16], + cfg_cfg_5072[15] = cfg_cfg[15], + cfg_cfg_5072[14] = cfg_cfg[14], + cfg_cfg_5072[13] = cfg_cfg[13], + cfg_cfg_5072[12] = cfg_cfg[12], + cfg_cfg_5072[11] = cfg_cfg[11], + cfg_cfg_5072[10] = cfg_cfg[10], + cfg_cfg_5072[9] = cfg_cfg[9], + cfg_cfg_5072[8] = cfg_cfg[8], + cfg_cfg_5072[7] = cfg_cfg[7], + cfg_cfg_5072[6] = cfg_cfg[6], + cfg_cfg_5072[5] = cfg_cfg[5], + cfg_cfg_5072[4] = cfg_cfg[4], + cfg_cfg_5072[3] = cfg_cfg[3], + cfg_cfg_5072[2] = cfg_cfg[2], + cfg_cfg_5072[1] = cfg_cfg[1], + cfg_cfg_5072[0] = cfg_cfg[0], + cfg_di_5067[31] = cfg_di[31], + cfg_di_5067[30] = cfg_di[30], + cfg_di_5067[29] = cfg_di[29], + cfg_di_5067[28] = cfg_di[28], + cfg_di_5067[27] = cfg_di[27], + cfg_di_5067[26] = cfg_di[26], + cfg_di_5067[25] = cfg_di[25], + cfg_di_5067[24] = cfg_di[24], + cfg_di_5067[23] = cfg_di[23], + cfg_di_5067[22] = cfg_di[22], + cfg_di_5067[21] = cfg_di[21], + cfg_di_5067[20] = cfg_di[20], + cfg_di_5067[19] = cfg_di[19], + cfg_di_5067[18] = cfg_di[18], + cfg_di_5067[17] = cfg_di[17], + cfg_di_5067[16] = cfg_di[16], + cfg_di_5067[15] = cfg_di[15], + cfg_di_5067[14] = cfg_di[14], + cfg_di_5067[13] = cfg_di[13], + cfg_di_5067[12] = cfg_di[12], + cfg_di_5067[11] = cfg_di[11], + cfg_di_5067[10] = cfg_di[10], + cfg_di_5067[9] = cfg_di[9], + cfg_di_5067[8] = cfg_di[8], + cfg_di_5067[7] = cfg_di[7], + cfg_di_5067[6] = cfg_di[6], + cfg_di_5067[5] = cfg_di[5], + cfg_di_5067[4] = cfg_di[4], + cfg_di_5067[3] = cfg_di[3], + cfg_di_5067[2] = cfg_di[2], + cfg_di_5067[1] = cfg_di[1], + cfg_di_5067[0] = cfg_di[0], + cfg_do[31] = cfg_do_5066[31], + cfg_do[30] = cfg_do_5066[30], + cfg_do[29] = cfg_do_5066[29], + cfg_do[28] = cfg_do_5066[28], + cfg_do[27] = cfg_do_5066[27], + cfg_do[26] = cfg_do_5066[26], + cfg_do[25] = cfg_do_5066[25], + cfg_do[24] = cfg_do_5066[24], + cfg_do[23] = cfg_do_5066[23], + cfg_do[22] = cfg_do_5066[22], + cfg_do[21] = cfg_do_5066[21], + cfg_do[20] = cfg_do_5066[20], + cfg_do[19] = cfg_do_5066[19], + cfg_do[18] = cfg_do_5066[18], + cfg_do[17] = cfg_do_5066[17], + cfg_do[16] = cfg_do_5066[16], + cfg_do[15] = cfg_do_5066[15], + cfg_do[14] = cfg_do_5066[14], + cfg_do[13] = cfg_do_5066[13], + cfg_do[12] = cfg_do_5066[12], + cfg_do[11] = cfg_do_5066[11], + cfg_do[10] = cfg_do_5066[10], + cfg_do[9] = cfg_do_5066[9], + cfg_do[8] = cfg_do_5066[8], + cfg_do[7] = cfg_do_5066[7], + cfg_do[6] = cfg_do_5066[6], + cfg_do[5] = cfg_do_5066[5], + cfg_do[4] = cfg_do_5066[4], + cfg_do[3] = cfg_do_5066[3], + cfg_do[2] = cfg_do_5066[2], + cfg_do[1] = cfg_do_5066[1], + cfg_do[0] = cfg_do_5066[0], + trn_reset_n = NlwRenamedSig_OI_trn_reset_n, + cfg_bus_number[7] = NlwRenamedSig_OI_cfg_bus_number[7], + cfg_bus_number[6] = NlwRenamedSig_OI_cfg_bus_number[6], + cfg_bus_number[5] = NlwRenamedSig_OI_cfg_bus_number[5], + cfg_bus_number[4] = NlwRenamedSig_OI_cfg_bus_number[4], + cfg_bus_number[3] = NlwRenamedSig_OI_cfg_bus_number[3], + cfg_bus_number[2] = NlwRenamedSig_OI_cfg_bus_number[2], + cfg_bus_number[1] = NlwRenamedSig_OI_cfg_bus_number[1], + cfg_bus_number[0] = NlwRenamedSig_OI_cfg_bus_number[0], + cfg_device_number[4] = NlwRenamedSig_OI_cfg_device_number[4], + cfg_device_number[3] = NlwRenamedSig_OI_cfg_device_number[3], + cfg_device_number[2] = NlwRenamedSig_OI_cfg_device_number[2], + cfg_device_number[1] = NlwRenamedSig_OI_cfg_device_number[1], + cfg_device_number[0] = NlwRenamedSig_OI_cfg_device_number[0], + trn_clk = NlwRenamedSig_OI_trn_clk, + cfg_dwaddr_5069[9] = cfg_dwaddr[9], + cfg_dwaddr_5069[8] = cfg_dwaddr[8], + cfg_dwaddr_5069[7] = cfg_dwaddr[7], + cfg_dwaddr_5069[6] = cfg_dwaddr[6], + cfg_dwaddr_5069[5] = cfg_dwaddr[5], + cfg_dwaddr_5069[4] = cfg_dwaddr[4], + cfg_dwaddr_5069[3] = cfg_dwaddr[3], + cfg_dwaddr_5069[2] = cfg_dwaddr[2], + cfg_dwaddr_5069[1] = cfg_dwaddr[1], + cfg_dwaddr_5069[0] = cfg_dwaddr[0], + trn_lnk_up_n = NlwRenamedSig_OI_trn_lnk_up_n, + trn_rfc_npd_av[11] = trn_rfc_npd_av_5061[11], + trn_rfc_npd_av[10] = trn_rfc_npd_av_5061[10], + trn_rfc_npd_av[9] = trn_rfc_npd_av_5061[9], + trn_rfc_npd_av[8] = trn_rfc_npd_av_5061[8], + trn_rfc_npd_av[7] = trn_rfc_npd_av_5061[7], + trn_rfc_npd_av[6] = trn_rfc_npd_av_5061[6], + trn_rfc_npd_av[5] = trn_rfc_npd_av_5061[5], + trn_rfc_npd_av[4] = trn_rfc_npd_av_5061[4], + trn_rfc_npd_av[3] = trn_rfc_npd_av_5061[3], + trn_rfc_npd_av[2] = trn_rfc_npd_av_5061[2], + trn_rfc_npd_av[1] = trn_rfc_npd_av_5061[1], + trn_rfc_npd_av[0] = trn_rfc_npd_av_5061[0], + cfg_dcommand[15] = NlwRenamedSignal_cfg_lcommand[15], + cfg_dcommand[14] = NlwRenamedSig_OI_cfg_dcommand[14], + cfg_dcommand[13] = NlwRenamedSig_OI_cfg_dcommand[13], + cfg_dcommand[12] = NlwRenamedSig_OI_cfg_dcommand[12], + cfg_dcommand[11] = NlwRenamedSig_OI_cfg_dcommand[11], + cfg_dcommand[10] = NlwRenamedSig_OI_cfg_dcommand[10], + cfg_dcommand[9] = NlwRenamedSig_OI_cfg_dcommand[9], + cfg_dcommand[8] = NlwRenamedSig_OI_cfg_dcommand[8], + cfg_dcommand[7] = NlwRenamedSig_OI_cfg_dcommand[7], + cfg_dcommand[6] = NlwRenamedSig_OI_cfg_dcommand[6], + cfg_dcommand[5] = NlwRenamedSig_OI_cfg_dcommand[5], + cfg_dcommand[4] = NlwRenamedSig_OI_cfg_dcommand[4], + cfg_dcommand[3] = NlwRenamedSig_OI_cfg_dcommand[3], + cfg_dcommand[2] = NlwRenamedSig_OI_cfg_dcommand[2], + cfg_dcommand[1] = NlwRenamedSig_OI_cfg_dcommand[1], + cfg_dcommand[0] = NlwRenamedSig_OI_cfg_dcommand[0], + trn_rfc_nph_av[7] = trn_rfc_nph_av_5060[7], + trn_rfc_nph_av[6] = trn_rfc_nph_av_5060[6], + trn_rfc_nph_av[5] = trn_rfc_nph_av_5060[5], + trn_rfc_nph_av[4] = trn_rfc_nph_av_5060[4], + trn_rfc_nph_av[3] = trn_rfc_nph_av_5060[3], + trn_rfc_nph_av[2] = trn_rfc_nph_av_5060[2], + trn_rfc_nph_av[1] = trn_rfc_nph_av_5060[1], + trn_rfc_nph_av[0] = trn_rfc_nph_av_5060[0], + cfg_pcie_link_state_n[2] = NlwRenamedSig_OI_cfg_status_4_, + cfg_pcie_link_state_n[1] = cfg_pcie_link_state_n_5071[1], + cfg_pcie_link_state_n[0] = cfg_pcie_link_state_n_5071[0], + sys_clkz = sys_clk, + cfg_function_number[2] = NlwRenamedSignal_cfg_lcommand[15], + cfg_function_number[1] = NlwRenamedSignal_cfg_lcommand[15], + cfg_function_number[0] = NlwRenamedSignal_cfg_lcommand[15], + cfg_lstatus[15] = NlwRenamedSignal_cfg_lcommand[15], + cfg_lstatus[14] = NlwRenamedSignal_cfg_lcommand[15], + cfg_lstatus[13] = NlwRenamedSignal_cfg_lcommand[15], + cfg_lstatus[12] = NlwRenamedSig_OI_cfg_lstatus_12_, + cfg_lstatus[11] = NlwRenamedSignal_cfg_lcommand[15], + cfg_lstatus[10] = NlwRenamedSignal_cfg_lcommand[15], + cfg_lstatus[9] = NlwRenamedSignal_cfg_lcommand[15], + cfg_lstatus[8] = NlwRenamedSignal_cfg_lcommand[15], + cfg_lstatus[7] = NlwRenamedSignal_cfg_lcommand[15], + cfg_lstatus[6] = NlwRenamedSignal_cfg_lcommand[15], + cfg_lstatus[5] = NlwRenamedSignal_cfg_lcommand[15], + cfg_lstatus[4] = NlwRenamedSig_OI_cfg_lstatus_4_, + cfg_lstatus[3] = NlwRenamedSignal_cfg_lcommand[15], + cfg_lstatus[2] = NlwRenamedSignal_cfg_lcommand[15], + cfg_lstatus[1] = NlwRenamedSignal_cfg_lcommand[15], + cfg_lstatus[0] = NlwRenamedSig_OI_cfg_lstatus_4_, + pci_exp_rxn_5056[0] = pci_exp_rxn[0], + pci_exp_rxp_5055[0] = pci_exp_rxp[0], + trn_rfc_pd_av[11] = trn_rfc_pd_av_5063[11], + trn_rfc_pd_av[10] = trn_rfc_pd_av_5063[10], + trn_rfc_pd_av[9] = trn_rfc_pd_av_5063[9], + trn_rfc_pd_av[8] = trn_rfc_pd_av_5063[8], + trn_rfc_pd_av[7] = trn_rfc_pd_av_5063[7], + trn_rfc_pd_av[6] = trn_rfc_pd_av_5063[6], + trn_rfc_pd_av[5] = trn_rfc_pd_av_5063[5], + trn_rfc_pd_av[4] = trn_rfc_pd_av_5063[4], + trn_rfc_pd_av[3] = trn_rfc_pd_av_5063[3], + trn_rfc_pd_av[2] = trn_rfc_pd_av_5063[2], + trn_rfc_pd_av[1] = trn_rfc_pd_av_5063[1], + trn_rfc_pd_av[0] = trn_rfc_pd_av_5063[0], + trn_tbuf_av[4] = NlwRenamedSig_OI_trn_tbuf_av[4], + trn_tbuf_av[3] = NlwRenamedSig_OI_trn_tbuf_av[3], + trn_tbuf_av[2] = NlwRenamedSig_OI_trn_tbuf_av[2], + trn_tbuf_av[1] = NlwRenamedSig_OI_trn_tbuf_av[1], + trn_tbuf_av[0] = NlwRenamedSig_OI_trn_tbuf_av[0]; + defparam N_6356_i.INIT = 4'h1; + LUT1 N_6356_i ( + .I0(com_tlm_u_tlm_rx_data_snk_cur_length_0__2), + .O(N_6356_i_3) + ); + defparam N_6357_i.INIT = 4'h1; + LUT1 N_6357_i ( + .I0(com_tlm_u_tlm_rx_data_snk_cur_length_1__4), + .O(N_6357_i_5) + ); + defparam N_6358_i.INIT = 4'h1; + LUT1 N_6358_i ( + .I0(com_tlm_u_tlm_rx_data_snk_cur_length_2__6), + .O(N_6358_i_7) + ); + defparam N_6359_i.INIT = 4'h1; + LUT1 N_6359_i ( + .I0(com_tlm_u_tlm_rx_data_snk_cur_length_3__8), + .O(N_6359_i_9) + ); + defparam N_6360_i.INIT = 4'h1; + LUT1 N_6360_i ( + .I0(com_tlm_u_tlm_rx_data_snk_cur_length_4__10), + .O(N_6360_i_11) + ); + defparam N_6364_i.INIT = 4'h1; + LUT1 N_6364_i ( + .I0(com_tlm_u_tlm_rx_data_snk_cur_length_8__12), + .O(N_6364_i_13) + ); + defparam N_6365_i.INIT = 4'h1; + LUT1 N_6365_i ( + .I0(com_tlm_u_tlm_rx_data_snk_cur_length_9__14), + .O(N_6365_i_15) + ); + defparam I_32353.INIT = 4'h1; + LUT1 I_32353 ( + .I0(cfg_cfg_5072[224]), + .O(cfg_cfg_i_224_) + ); + defparam I_32468.INIT = 4'h1; + LUT1 I_32468 ( + .I0(cfg_cfg_5072[351]), + .O(cfg_cfg_i_351_) + ); + defparam N_57349_i.INIT = 4'h1; + LUT1 N_57349_i ( + .I0(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_dllp_d[0]), + .O(N_57349_i_16) + ); + defparam N_57388_i.INIT = 4'h1; + LUT1 N_57388_i ( + .I0(plm_sym_reg_count[0]), + .O(N_57388_i_17) + ); + defparam G_32475.INIT = 4'hB; + LUT2_L G_32475 ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_rem_pipe_DOUT[0]), + .I1(G_32479_18), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_rem_pipe[3]) + ); + defparam G_32480.INIT = 4'hB; + LUT2_L G_32480 ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_eof_n_pipe_DOUT[0]), + .I1(G_32479_18), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_eof_n_pipe[4]) + ); + defparam m16_i_0.INIT = 16'h5100; + LUT4_L m16_i_0 ( + .I0(N_36576), + .I1(com_lnk_rd[4]), + .I2(m16_i_0_1_19), + .I3(m16_i_0_4_20), + .LO(N_14707_i) + ); + INV I_32559 ( + .I(plm_link_up_2), + .O(plm_link_up_0) + ); + INV I_32558 ( + .I(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_5), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_3) + ); + INV I_32557 ( + .I(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_4), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_2) + ); + INV I_32556 ( + .I(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_3), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_1) + ); + INV I_32555 ( + .I(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_2), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_0) + ); + INV I_32554 ( + .I(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_1), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0) + ); + INV N_24768_i_i ( + .I(N_24768_i), + .O(N_24768_i_i_21) + ); + INV N_37268_i_i ( + .I(N_37268_i), + .O(N_37268_i_i_22) + ); + INV N_18912_i_i ( + .I(N_18912_i), + .O(N_18912_i_i_23) + ); + INV N_38578_i ( + .I(N_38578), + .O(N_38578_i_24) + ); + INV N_38691_i ( + .I(I_5072_0_a2_0_a2_0_a4_25), + .O(N_38691_i_26) + ); + INV N_38692_i ( + .I(I_5137_0_a2_0_a2_0_a4_27), + .O(N_38692_i_28) + ); + INV link_up_i ( + .I(plm_link_up), + .O(plm_link_up_i) + ); + FDC G_32545 ( + .C(mgt_clk), + .D(NlwRenamedSig_OI_cfg_status_4_), + .Q(G_32545_29), + .CLR(plm_rst) + ); + FDC G_32547 ( + .C(mgt_clk), + .D(G_32483_31), + .Q(G_32547_30), + .CLR(plm_rst) + ); + FDC G_32549 ( + .C(mgt_clk), + .D(G_32485_33), + .Q(G_32549_32), + .CLR(plm_rst) + ); + FDC G_32551 ( + .C(mgt_clk), + .D(G_32487_35), + .Q(G_32551_34), + .CLR(plm_rst) + ); + FDC G_32489 ( + .C(mgt_clk), + .D(G_32551_34), + .Q(G_32489_36), + .CLR(plm_rst) + ); + FDC G_32483 ( + .C(mgt_clk), + .D(G_32545_29), + .Q(G_32483_31), + .CLR(plm_rst) + ); + FDC G_32485 ( + .C(mgt_clk), + .D(G_32547_30), + .Q(G_32485_33), + .CLR(plm_rst) + ); + FDC G_32487 ( + .C(mgt_clk), + .D(G_32549_32), + .Q(G_32487_35), + .CLR(plm_rst) + ); + FDRE G_32479 ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_i_38), + .C(NlwRenamedSig_OI_trn_clk), + .D(G_32473_37), + .Q(G_32479_18), + .R(plm_link_up_i) + ); + FDRE G_32473 ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_i_38), + .C(NlwRenamedSig_OI_trn_clk), + .D(G_32477_39), + .Q(G_32473_37), + .R(plm_link_up_i) + ); + FDRE G_32477 ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_i_38), + .C(NlwRenamedSig_OI_trn_clk), + .D(NlwRenamedSig_OI_cfg_status_4_), + .Q(G_32477_39), + .R(plm_link_up_i) + ); + defparam N_18708_i_i.INIT = 8'hBF; + LUT3 N_18708_i_i ( + .I0(plm_fsm_rl_counter0_reg_rx_expired_40), + .I1(plm_fsm_reg_state_13__41), + .I2(N_38240_i), + .O(N_18708_i_i_42) + ); + defparam N_18705_i_i.INIT = 4'hB; + LUT2 N_18705_i_i ( + .I0(plm_fsm_pa_counter0_reg_rx_expired_43), + .I1(N_38420), + .O(N_18705_i_i_44) + ); + defparam G_122.INIT = 8'h96; + LUT3 G_122 ( + .I0(N_27425), + .I1(N_27415), + .I2(N_126_1), + .O(N_126) + ); + defparam G_296.INIT = 8'h96; + LUT3 G_296 ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d64_18__45), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d64_30__46), + .I2(N_10445_1), + .O(N_10438) + ); + defparam G_251.INIT = 8'h96; + LUT3 G_251 ( + .I0(N_27494), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d64_16__47), + .I2(N_10461_1), + .O(N_10395) + ); + defparam G_473.INIT = 8'h96; + LUT3 G_473 ( + .I0(N_10393), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d64_22__48), + .I2(N_10496_1), + .O(N_10615) + ); + defparam G_400.INIT = 8'h96; + LUT3 G_400 ( + .I0(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_39_), + .I1(N_217), + .I2(N_178), + .O(N_10542) + ); + defparam G_302.INIT = 8'h96; + LUT3 G_302 ( + .I0(N_10445_1), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d64_19__49), + .I2(N_27491), + .O(N_10444) + ); + defparam G_300.INIT = 8'h96; + LUT3 G_300 ( + .I0(N_10442_1), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d64_31__50), + .I2(N_27498), + .O(N_10442) + ); + defparam G_386.INIT = 8'h96; + LUT3 G_386 ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crc32_d64_feedback[27]), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crc32_d64_feedback[25]), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crc32_d64_feedback[6]), + .O(N_10528) + ); + defparam G_281.INIT = 8'h96; + LUT3 G_281 ( + .I0(N_10424_1), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crc32_d64_feedback[20]), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crc32_d64_feedback[16]), + .O(N_10423) + ); + defparam G_96.INIT = 8'h96; + LUT3 G_96 ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[24]), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[28]), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[20]), + .O(N_100) + ); + defparam G_102_1.INIT = 8'h56; + LUT3 G_102_1 ( + .I0(N_27429), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_initial_64_51), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d64_3__52), + .O(N_106_1) + ); + defparam G_417_1.INIT = 8'h56; + LUT3 G_417_1 ( + .I0(N_27428), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_initial_64_51), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d64_2__53), + .O(N_10559_1) + ); + defparam G_344_1.INIT = 8'h56; + LUT3 G_344_1 ( + .I0(N_27511), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_initial_64_51), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d64_20__54), + .O(N_10486_1) + ); + defparam G_271.INIT = 8'h96; + LUT3 G_271 ( + .I0(N_10413_1), + .I1(data_in_q[34]), + .I2(data_in_q[0]), + .O(G_271_55) + ); + defparam G_287.INIT = 8'h96; + LUT3 G_287 ( + .I0(data_in_q[46]), + .I1(data_in_q[53]), + .I2(data_in_q[5]), + .O(G_287_56) + ); + defparam G_32495.INIT = 4'h8; + LUT2 G_32495 ( + .I0(plm_tsi0_reg_dec1_DOUT[0]), + .I1(G_32547_30), + .O(plm_tsi0_reg_dec1[1]) + ); + defparam G_32490.INIT = 4'h8; + LUT2 G_32490 ( + .I0(G_32489_36), + .I1(plm_tsi0_reg_dec8_DOUT[0]), + .O(plm_tsi0_reg_dec8_7_) + ); + defparam G_32553.INIT = 4'h8; + LUT2 G_32553 ( + .I0(G_32489_36), + .I1(plm_tsi0_reg_dec8_0_DOUT[0]), + .O(plm_tsi0_reg_dec8_0_) + ); + defparam G_32543.INIT = 4'h8; + LUT2 G_32543 ( + .I0(plm_tsi0_reg_dec7_0_DOUT[0]), + .I1(G_32551_34), + .O(plm_tsi0_reg_dec7_6_) + ); + defparam G_32534.INIT = 4'h8; + LUT2 G_32534 ( + .I0(plm_tsi0_reg_dec7_DOUT[0]), + .I1(G_32551_34), + .O(plm_tsi0_reg_dec7_13_) + ); + defparam G_32525.INIT = 4'h8; + LUT2 G_32525 ( + .I0(plm_tsi0_reg_dec5_DOUT[0]), + .I1(G_32549_32), + .O(plm_tsi0_reg_dec5[12]) + ); + defparam G_32518.INIT = 4'h8; + LUT2 G_32518 ( + .I0(G_32487_35), + .I1(plm_tsi0_reg_dec6_DOUT[0]), + .O(plm_tsi0_reg_dec6[5]) + ); + defparam G_32510.INIT = 4'h8; + LUT2 G_32510 ( + .I0(plm_tsi0_reg_dec1_2_DOUT[0]), + .I1(G_32547_30), + .O(plm_tsi0_reg_dec1[4]) + ); + defparam G_32505.INIT = 4'h8; + LUT2 G_32505 ( + .I0(plm_tsi0_reg_dec1_1_DOUT[0]), + .I1(G_32547_30), + .O(plm_tsi0_reg_dec1[3]) + ); + defparam G_32500.INIT = 4'h8; + LUT2 G_32500 ( + .I0(plm_tsi0_reg_dec1_0_DOUT[0]), + .I1(G_32547_30), + .O(plm_tsi0_reg_dec1[2]) + ); + defparam m16_i_0_1.INIT = 16'h03EE; + LUT4 m16_i_0_1 ( + .I0(com_lnk_rd[1]), + .I1(com_lnk_rd[2]), + .I2(com_lnk_rd[3]), + .I3(com_lnk_rd[6]), + .O(m16_i_0_1_19) + ); + defparam m5_2_i_0.INIT = 4'h4; + LUT2_L m5_2_i_0 ( + .I0(N_36389_i), + .I1(m5_2_i_0_32074_57), + .LO(N_14703_i) + ); + defparam m9_1_i_0.INIT = 16'h54E8; + LUT4_L m9_1_i_0 ( + .I0(com_lnk_rd[0]), + .I1(com_lnk_rd[1]), + .I2(com_lnk_rd[2]), + .I3(com_lnk_rd[3]), + .LO(N_14705_i) + ); + defparam I_32458.INIT = 4'h1; + LUT1_L I_32458 ( + .I0(trn_tsof_n), + .LO(trn_tsof_n_i) + ); + defparam I_32470.INIT = 4'h1; + LUT1_L I_32470 ( + .I0(trn_terrfwd_n), + .LO(trn_terrfwd_n_i) + ); + defparam m4_6.INIT = 4'h4; + LUT2_L m4_6 ( + .I0(N_3543), + .I1(plm_dfm_deframe1_qwfsm_reg_state_1__58), + .LO(plm_dfm_deframe1_qwfsm_nxt_state[4]) + ); + defparam m5_4.INIT = 4'h4; + LUT2_L m5_4 ( + .I0(N_3543), + .I1(plm_dfm_deframe1_qwfsm_reg_state_0__59), + .LO(plm_dfm_deframe1_qwfsm_nxt_state[5]) + ); + defparam m10_3.INIT = 16'hCC80; + LUT4_L m10_3 ( + .I0(N_3546), + .I1(plm_dfm_deframe1_qwfsm_nxt_state_1[7]), + .I2(plm_dfm_deframe1_qwfsm_reg_state_1__58), + .I3(plm_dfm_deframe1_qwfsm_reg_state_7__60), + .LO(plm_dfm_deframe1_qwfsm_nxt_state[6]) + ); + defparam m14_2.INIT = 16'hCC80; + LUT4_L m14_2 ( + .I0(N_3546), + .I1(plm_dfm_deframe1_qwfsm_nxt_state_1[7]), + .I2(plm_dfm_deframe1_qwfsm_reg_state_0__59), + .I3(plm_dfm_deframe1_qwfsm_reg_state_6__61), + .LO(plm_dfm_deframe1_qwfsm_nxt_state[7]) + ); + defparam N_176_i.INIT = 16'h5503; + LUT4_L N_176_i ( + .I0(N_172), + .I1(N_223_i), + .I2(plm_sym_sym_gen_next_addr[3]), + .I3(plm_sym_sym_gen_next_addr[4]), + .LO(N_176_i_62) + ); + defparam m8_0.INIT = 16'h00F4; + LUT4_L m8_0 ( + .I0(N_3004), + .I1(plm_sym_sym_gen_next_addr[1]), + .I2(plm_sym_sym_gen_next_addr[2]), + .I3(plm_sym_sym_gen_next_addr[4]), + .LO(plm_sym_sym_gen_reg_rom_out_27[17]) + ); + defparam N_16_i.INIT = 16'h5F40; + LUT4_L N_16_i ( + .I0(N_224_i), + .I1(plm_sym_sym_gen_next_addr[0]), + .I2(plm_sym_sym_gen_next_addr[1]), + .I3(plm_sym_sym_gen_next_addr[2]), + .LO(N_16_i_63) + ); + defparam loadable_tx_counter_reg_tx_count_6_0_a2_0_a2_0_a2_0_a4_4_.INIT = 4'h2; + LUT2_L loadable_tx_counter_reg_tx_count_6_0_a2_0_a2_0_a2_0_a4_4_ ( + .I0(cfg_cfg_5072[507]), + .I1(plm_fsm_reg_state_13__41), + .LO(plm_fsm_rl_counter3_loadable_tx_counter_reg_tx_count_6[4]) + ); + defparam I_5030_0_a2_0_a2_0_a2.INIT = 4'h8; + LUT2_L I_5030_0_a2_0_a2_0_a2 ( + .I0(cfg_cfg_5072[85]), + .I1(com_cmm_cfg_wr_data_13_), + .LO(I_5030_0_a2_0_a2_0_a2_64) + ); + defparam I_5025_0_a2_0_a2_0_a2.INIT = 4'h8; + LUT2_L I_5025_0_a2_0_a2_0_a2 ( + .I0(cfg_cfg_5072[86]), + .I1(com_cmm_cfg_wr_data_14_), + .LO(I_5025_0_a2_0_a2_0_a2_65) + ); + defparam I_5020_0_a2_0_a2.INIT = 4'h8; + LUT2_L I_5020_0_a2_0_a2 ( + .I0(cfg_cfg_5072[87]), + .I1(com_cmm_cfg_wr_data_15_), + .LO(I_5020_0_a2_0_a2_66) + ); + defparam I_5015_0_a2_0_a2.INIT = 4'h8; + LUT2_L I_5015_0_a2_0_a2 ( + .I0(cfg_cfg_5072[88]), + .I1(com_cmm_cfg_wr_data_0_), + .LO(I_5015_0_a2_0_a2_67) + ); + defparam I_5010_0_a2_0_a2.INIT = 4'h8; + LUT2_L I_5010_0_a2_0_a2 ( + .I0(cfg_cfg_5072[89]), + .I1(com_cmm_cfg_wr_data_1_), + .LO(I_5010_0_a2_0_a2_68) + ); + defparam I_5005_0_a2_0_a2.INIT = 4'h8; + LUT2_L I_5005_0_a2_0_a2 ( + .I0(cfg_cfg_5072[90]), + .I1(com_cmm_cfg_wr_data_2_), + .LO(I_5005_0_a2_0_a2_69) + ); + defparam I_5000_0_a2_0_a2_0_a2.INIT = 4'h8; + LUT2_L I_5000_0_a2_0_a2_0_a2 ( + .I0(cfg_cfg_5072[91]), + .I1(com_cmm_cfg_wr_data_3_), + .LO(I_5000_0_a2_0_a2_0_a2_70) + ); + defparam I_4995_0_a2_0_a2_0_a2.INIT = 4'h8; + LUT2_L I_4995_0_a2_0_a2_0_a2 ( + .I0(cfg_cfg_5072[92]), + .I1(com_cmm_cfg_wr_data_4_), + .LO(I_4995_0_a2_0_a2_0_a2_71) + ); + defparam I_4990_0_a2_0_a2_0_a2.INIT = 4'h8; + LUT2_L I_4990_0_a2_0_a2_0_a2 ( + .I0(cfg_cfg_5072[93]), + .I1(com_cmm_cfg_wr_data_5_), + .LO(I_4990_0_a2_0_a2_0_a2_72) + ); + defparam I_4985_0_a2_0_a2_0_a2.INIT = 4'h8; + LUT2_L I_4985_0_a2_0_a2_0_a2 ( + .I0(cfg_cfg_5072[94]), + .I1(com_cmm_cfg_wr_data_6_), + .LO(I_4985_0_a2_0_a2_0_a2_73) + ); + defparam I_4980_0_a2_0_a2_0_a2.INIT = 4'h8; + LUT2_L I_4980_0_a2_0_a2_0_a2 ( + .I0(cfg_cfg_5072[95]), + .I1(com_cmm_cfg_wr_data_7_), + .LO(I_4980_0_a2_0_a2_0_a2_74) + ); + defparam I_4975_0_a2_0_a2_0_a2_0_a2.INIT = 4'h8; + LUT2_L I_4975_0_a2_0_a2_0_a2_0_a2 ( + .I0(cfg_cfg_5072[70]), + .I1(com_cmm_cfg_wr_data_30_), + .LO(I_4975_0_a2_0_a2_0_a2_0_a2_75) + ); + defparam I_4970_0_a2_0_a2_0_a2_0_a2.INIT = 4'h8; + LUT2_L I_4970_0_a2_0_a2_0_a2_0_a2 ( + .I0(cfg_cfg_5072[71]), + .I1(com_cmm_cfg_wr_data_31_), + .LO(I_4970_0_a2_0_a2_0_a2_0_a2_76) + ); + defparam I_4965_0_a2_0_a2_0_a2.INIT = 4'h8; + LUT2_L I_4965_0_a2_0_a2_0_a2 ( + .I0(cfg_cfg_5072[72]), + .I1(com_cmm_cfg_wr_data_16_), + .LO(I_4965_0_a2_0_a2_0_a2_77) + ); + defparam I_4960_0_a2_0_a2_0_a2.INIT = 4'h8; + LUT2_L I_4960_0_a2_0_a2_0_a2 ( + .I0(cfg_cfg_5072[73]), + .I1(com_cmm_cfg_wr_data_17_), + .LO(I_4960_0_a2_0_a2_0_a2_78) + ); + defparam I_4955_0_a2_0_a2_0_a2.INIT = 4'h8; + LUT2_L I_4955_0_a2_0_a2_0_a2 ( + .I0(cfg_cfg_5072[74]), + .I1(com_cmm_cfg_wr_data_18_), + .LO(I_4955_0_a2_0_a2_0_a2_79) + ); + defparam I_4950_0_a2_0_a2_0_a2.INIT = 4'h8; + LUT2_L I_4950_0_a2_0_a2_0_a2 ( + .I0(cfg_cfg_5072[75]), + .I1(com_cmm_cfg_wr_data_19_), + .LO(I_4950_0_a2_0_a2_0_a2_80) + ); + defparam I_4945_0_a2_0_a2_0_a2_0_a2.INIT = 4'h8; + LUT2_L I_4945_0_a2_0_a2_0_a2_0_a2 ( + .I0(cfg_cfg_5072[76]), + .I1(com_cmm_cfg_wr_data_20_), + .LO(I_4945_0_a2_0_a2_0_a2_0_a2_81) + ); + defparam I_4940_0_a2_0_a2.INIT = 4'h8; + LUT2_L I_4940_0_a2_0_a2 ( + .I0(cfg_cfg_5072[77]), + .I1(com_cmm_cfg_wr_data_21_), + .LO(I_4940_0_a2_0_a2_82) + ); + defparam I_4935_0_a2_0_a2_0_a2.INIT = 4'h8; + LUT2_L I_4935_0_a2_0_a2_0_a2 ( + .I0(cfg_cfg_5072[78]), + .I1(com_cmm_cfg_wr_data_22_), + .LO(I_4935_0_a2_0_a2_0_a2_83) + ); + defparam I_4930_0_a2_0_a2_0_a2.INIT = 4'h8; + LUT2_L I_4930_0_a2_0_a2_0_a2 ( + .I0(cfg_cfg_5072[79]), + .I1(com_cmm_cfg_wr_data_23_), + .LO(I_4930_0_a2_0_a2_0_a2_84) + ); + defparam I_4925_0_a2_0_a2_0_a2.INIT = 4'h8; + LUT2_L I_4925_0_a2_0_a2_0_a2 ( + .I0(cfg_cfg_5072[80]), + .I1(com_cmm_cfg_wr_data_8_), + .LO(I_4925_0_a2_0_a2_0_a2_85) + ); + defparam I_4920_0_a2_0_a2_0_a2.INIT = 4'h8; + LUT2_L I_4920_0_a2_0_a2_0_a2 ( + .I0(cfg_cfg_5072[81]), + .I1(com_cmm_cfg_wr_data_9_), + .LO(I_4920_0_a2_0_a2_0_a2_86) + ); + defparam I_4915_0_a2_0_a2_0_a2_0_a2.INIT = 4'h8; + LUT2_L I_4915_0_a2_0_a2_0_a2_0_a2 ( + .I0(cfg_cfg_5072[82]), + .I1(com_cmm_cfg_wr_data_10_), + .LO(I_4915_0_a2_0_a2_0_a2_0_a2_87) + ); + defparam I_4910_0_a2_0_a2_0_a2.INIT = 4'h8; + LUT2_L I_4910_0_a2_0_a2_0_a2 ( + .I0(cfg_cfg_5072[83]), + .I1(com_cmm_cfg_wr_data_11_), + .LO(I_4910_0_a2_0_a2_0_a2_88) + ); + defparam I_4905_0_a2_0_a2_0_a2_0_a2.INIT = 4'h8; + LUT2_L I_4905_0_a2_0_a2_0_a2_0_a2 ( + .I0(cfg_cfg_5072[84]), + .I1(com_cmm_cfg_wr_data_12_), + .LO(I_4905_0_a2_0_a2_0_a2_0_a2_89) + ); + defparam I_4900_0_a2_0_a2_0_a2_0_a2.INIT = 4'h8; + LUT2_L I_4900_0_a2_0_a2_0_a2_0_a2 ( + .I0(cfg_cfg_5072[68]), + .I1(com_cmm_cfg_wr_data_28_), + .LO(I_4900_0_a2_0_a2_0_a2_0_a2_90) + ); + defparam I_4895_0_a2_0_a2_0_a2_0_a2.INIT = 4'h8; + LUT2_L I_4895_0_a2_0_a2_0_a2_0_a2 ( + .I0(cfg_cfg_5072[69]), + .I1(com_cmm_cfg_wr_data_29_), + .LO(I_4895_0_a2_0_a2_0_a2_0_a2_91) + ); + defparam I_4890_0_a2_0_a2_0_a2_0_a2.INIT = 4'h8; + LUT2_L I_4890_0_a2_0_a2_0_a2_0_a2 ( + .I0(cfg_cfg_5072[246]), + .I1(com_cmm_cfg_wr_data_14_), + .LO(I_4890_0_a2_0_a2_0_a2_0_a2_92) + ); + defparam I_4885_0_a2_0_a2.INIT = 4'h8; + LUT2_L I_4885_0_a2_0_a2 ( + .I0(cfg_cfg_5072[247]), + .I1(com_cmm_cfg_wr_data_15_), + .LO(I_4885_0_a2_0_a2_93) + ); + defparam I_4880_0_a2_0_a2_0_a2.INIT = 4'h8; + LUT2_L I_4880_0_a2_0_a2_0_a2 ( + .I0(cfg_cfg_5072[248]), + .I1(com_cmm_cfg_wr_data_0_), + .LO(I_4880_0_a2_0_a2_0_a2_94) + ); + defparam I_4875_0_a2_0_a2.INIT = 4'h8; + LUT2_L I_4875_0_a2_0_a2 ( + .I0(cfg_cfg_5072[249]), + .I1(com_cmm_cfg_wr_data_1_), + .LO(I_4875_0_a2_0_a2_95) + ); + defparam I_4870_0_a2_0_a2.INIT = 4'h8; + LUT2_L I_4870_0_a2_0_a2 ( + .I0(cfg_cfg_5072[250]), + .I1(com_cmm_cfg_wr_data_2_), + .LO(I_4870_0_a2_0_a2_96) + ); + defparam I_4865_0_a2_0_a2_0_a2.INIT = 4'h8; + LUT2_L I_4865_0_a2_0_a2_0_a2 ( + .I0(cfg_cfg_5072[251]), + .I1(com_cmm_cfg_wr_data_3_), + .LO(I_4865_0_a2_0_a2_0_a2_97) + ); + defparam I_4860_0_a2_0_a2_0_a2.INIT = 4'h8; + LUT2_L I_4860_0_a2_0_a2_0_a2 ( + .I0(cfg_cfg_5072[252]), + .I1(com_cmm_cfg_wr_data_4_), + .LO(I_4860_0_a2_0_a2_0_a2_98) + ); + defparam I_4855_0_a2_0_a2_0_a2.INIT = 4'h8; + LUT2_L I_4855_0_a2_0_a2_0_a2 ( + .I0(cfg_cfg_5072[253]), + .I1(com_cmm_cfg_wr_data_5_), + .LO(I_4855_0_a2_0_a2_0_a2_99) + ); + defparam I_4850_0_a2_0_a2_0_a2.INIT = 4'h8; + LUT2_L I_4850_0_a2_0_a2_0_a2 ( + .I0(cfg_cfg_5072[254]), + .I1(com_cmm_cfg_wr_data_6_), + .LO(I_4850_0_a2_0_a2_0_a2_100) + ); + defparam I_4845_0_a2_0_a2_0_a2.INIT = 4'h8; + LUT2_L I_4845_0_a2_0_a2_0_a2 ( + .I0(cfg_cfg_5072[255]), + .I1(com_cmm_cfg_wr_data_7_), + .LO(I_4845_0_a2_0_a2_0_a2_101) + ); + defparam I_4840_0_a2_0_a2_0_a2_0_a2.INIT = 4'h8; + LUT2_L I_4840_0_a2_0_a2_0_a2_0_a2 ( + .I0(cfg_cfg_5072[231]), + .I1(com_cmm_cfg_wr_data_31_), + .LO(I_4840_0_a2_0_a2_0_a2_0_a2_102) + ); + defparam I_4835_0_a2_0_a2_0_a2.INIT = 4'h8; + LUT2_L I_4835_0_a2_0_a2_0_a2 ( + .I0(cfg_cfg_5072[232]), + .I1(com_cmm_cfg_wr_data_16_), + .LO(I_4835_0_a2_0_a2_0_a2_103) + ); + defparam I_4830_0_a2_0_a2_0_a2.INIT = 4'h8; + LUT2_L I_4830_0_a2_0_a2_0_a2 ( + .I0(cfg_cfg_5072[233]), + .I1(com_cmm_cfg_wr_data_17_), + .LO(I_4830_0_a2_0_a2_0_a2_104) + ); + defparam I_4825_0_a2_0_a2_0_a2.INIT = 4'h8; + LUT2_L I_4825_0_a2_0_a2_0_a2 ( + .I0(cfg_cfg_5072[234]), + .I1(com_cmm_cfg_wr_data_18_), + .LO(I_4825_0_a2_0_a2_0_a2_105) + ); + defparam I_4820_0_a2_0_a2_0_a2.INIT = 4'h8; + LUT2_L I_4820_0_a2_0_a2_0_a2 ( + .I0(cfg_cfg_5072[235]), + .I1(com_cmm_cfg_wr_data_19_), + .LO(I_4820_0_a2_0_a2_0_a2_106) + ); + defparam I_4815_0_a2_0_a2_0_a2_0_a2.INIT = 4'h8; + LUT2_L I_4815_0_a2_0_a2_0_a2_0_a2 ( + .I0(cfg_cfg_5072[236]), + .I1(com_cmm_cfg_wr_data_20_), + .LO(I_4815_0_a2_0_a2_0_a2_0_a2_107) + ); + defparam I_4810_0_a2_0_a2.INIT = 4'h8; + LUT2_L I_4810_0_a2_0_a2 ( + .I0(cfg_cfg_5072[237]), + .I1(com_cmm_cfg_wr_data_21_), + .LO(I_4810_0_a2_0_a2_108) + ); + defparam I_4805_0_a2_0_a2_0_a2.INIT = 4'h8; + LUT2_L I_4805_0_a2_0_a2_0_a2 ( + .I0(cfg_cfg_5072[238]), + .I1(com_cmm_cfg_wr_data_22_), + .LO(I_4805_0_a2_0_a2_0_a2_109) + ); + defparam I_4800_0_a2_0_a2_0_a2.INIT = 4'h8; + LUT2_L I_4800_0_a2_0_a2_0_a2 ( + .I0(cfg_cfg_5072[239]), + .I1(com_cmm_cfg_wr_data_23_), + .LO(I_4800_0_a2_0_a2_0_a2_110) + ); + defparam I_4795_0_a2_0_a2_0_a2_0_a2.INIT = 4'h8; + LUT2_L I_4795_0_a2_0_a2_0_a2_0_a2 ( + .I0(cfg_cfg_5072[240]), + .I1(com_cmm_cfg_wr_data_8_), + .LO(I_4795_0_a2_0_a2_0_a2_0_a2_111) + ); + defparam I_4790_0_a2_0_a2_0_a2_0_a2.INIT = 4'h8; + LUT2_L I_4790_0_a2_0_a2_0_a2_0_a2 ( + .I0(cfg_cfg_5072[241]), + .I1(com_cmm_cfg_wr_data_9_), + .LO(I_4790_0_a2_0_a2_0_a2_0_a2_112) + ); + defparam I_4785_0_a2_0_a2_0_a2_0_a2.INIT = 4'h8; + LUT2_L I_4785_0_a2_0_a2_0_a2_0_a2 ( + .I0(cfg_cfg_5072[242]), + .I1(com_cmm_cfg_wr_data_10_), + .LO(I_4785_0_a2_0_a2_0_a2_0_a2_113) + ); + defparam I_4780_0_a2_0_a2_0_a2_0_a2.INIT = 4'h8; + LUT2_L I_4780_0_a2_0_a2_0_a2_0_a2 ( + .I0(cfg_cfg_5072[243]), + .I1(com_cmm_cfg_wr_data_11_), + .LO(I_4780_0_a2_0_a2_0_a2_0_a2_114) + ); + defparam I_4775_0_a2_0_a2_0_a2_0_a2.INIT = 4'h8; + LUT2_L I_4775_0_a2_0_a2_0_a2_0_a2 ( + .I0(cfg_cfg_5072[244]), + .I1(com_cmm_cfg_wr_data_12_), + .LO(I_4775_0_a2_0_a2_0_a2_0_a2_115) + ); + defparam I_4770_0_a2_0_a2_0_a2_0_a2.INIT = 4'h8; + LUT2_L I_4770_0_a2_0_a2_0_a2_0_a2 ( + .I0(cfg_cfg_5072[245]), + .I1(com_cmm_cfg_wr_data_13_), + .LO(I_4770_0_a2_0_a2_0_a2_0_a2_116) + ); + defparam I_4765_0_a2_0_a2.INIT = 4'h8; + LUT2_L I_4765_0_a2_0_a2 ( + .I0(cfg_cfg_5072[216]), + .I1(com_cmm_cfg_wr_data_0_), + .LO(I_4765_0_a2_0_a2_117) + ); + defparam I_4760_0_a2_0_a2.INIT = 4'h8; + LUT2_L I_4760_0_a2_0_a2 ( + .I0(cfg_cfg_5072[217]), + .I1(com_cmm_cfg_wr_data_1_), + .LO(I_4760_0_a2_0_a2_118) + ); + defparam I_4755_0_a2_0_a2.INIT = 4'h8; + LUT2_L I_4755_0_a2_0_a2 ( + .I0(cfg_cfg_5072[218]), + .I1(com_cmm_cfg_wr_data_2_), + .LO(I_4755_0_a2_0_a2_119) + ); + defparam I_4750_0_a2_0_a2_0_a2.INIT = 4'h8; + LUT2_L I_4750_0_a2_0_a2_0_a2 ( + .I0(cfg_cfg_5072[219]), + .I1(com_cmm_cfg_wr_data_3_), + .LO(I_4750_0_a2_0_a2_0_a2_120) + ); + defparam I_4745_0_a2_0_a2_0_a2.INIT = 4'h8; + LUT2_L I_4745_0_a2_0_a2_0_a2 ( + .I0(cfg_cfg_5072[220]), + .I1(com_cmm_cfg_wr_data_4_), + .LO(I_4745_0_a2_0_a2_0_a2_121) + ); + defparam I_4740_0_a2_0_a2_0_a2.INIT = 4'h8; + LUT2_L I_4740_0_a2_0_a2_0_a2 ( + .I0(cfg_cfg_5072[221]), + .I1(com_cmm_cfg_wr_data_5_), + .LO(I_4740_0_a2_0_a2_0_a2_122) + ); + defparam I_4735_0_a2_0_a2_0_a2.INIT = 4'h8; + LUT2_L I_4735_0_a2_0_a2_0_a2 ( + .I0(cfg_cfg_5072[222]), + .I1(com_cmm_cfg_wr_data_6_), + .LO(I_4735_0_a2_0_a2_0_a2_123) + ); + defparam I_4730_0_a2_0_a2_0_a2.INIT = 4'h8; + LUT2_L I_4730_0_a2_0_a2_0_a2 ( + .I0(cfg_cfg_5072[223]), + .I1(com_cmm_cfg_wr_data_7_), + .LO(I_4730_0_a2_0_a2_0_a2_124) + ); + defparam I_4725_0_a2_0_a2_0_a2_0_a2.INIT = 4'h8; + LUT2_L I_4725_0_a2_0_a2_0_a2_0_a2 ( + .I0(cfg_cfg_5072[228]), + .I1(com_cmm_cfg_wr_data_28_), + .LO(I_4725_0_a2_0_a2_0_a2_0_a2_125) + ); + defparam I_4720_0_a2_0_a2_0_a2_0_a2.INIT = 4'h8; + LUT2_L I_4720_0_a2_0_a2_0_a2_0_a2 ( + .I0(cfg_cfg_5072[229]), + .I1(com_cmm_cfg_wr_data_29_), + .LO(I_4720_0_a2_0_a2_0_a2_0_a2_126) + ); + defparam I_4715_0_a2_0_a2_0_a2_0_a2.INIT = 4'h8; + LUT2_L I_4715_0_a2_0_a2_0_a2_0_a2 ( + .I0(cfg_cfg_5072[230]), + .I1(com_cmm_cfg_wr_data_30_), + .LO(I_4715_0_a2_0_a2_0_a2_0_a2_127) + ); + defparam I_4710_0_a2_0_a2_0_a2.INIT = 4'h8; + LUT2_L I_4710_0_a2_0_a2_0_a2 ( + .I0(cfg_cfg_5072[201]), + .I1(com_cmm_cfg_wr_data_17_), + .LO(I_4710_0_a2_0_a2_0_a2_128) + ); + defparam I_4705_0_a2_0_a2_0_a2.INIT = 4'h8; + LUT2_L I_4705_0_a2_0_a2_0_a2 ( + .I0(cfg_cfg_5072[202]), + .I1(com_cmm_cfg_wr_data_18_), + .LO(I_4705_0_a2_0_a2_0_a2_129) + ); + defparam I_4700_0_a2_0_a2_0_a2.INIT = 4'h8; + LUT2_L I_4700_0_a2_0_a2_0_a2 ( + .I0(cfg_cfg_5072[203]), + .I1(com_cmm_cfg_wr_data_19_), + .LO(I_4700_0_a2_0_a2_0_a2_130) + ); + defparam I_4695_0_a2_0_a2_0_a2_0_a2.INIT = 4'h8; + LUT2_L I_4695_0_a2_0_a2_0_a2_0_a2 ( + .I0(cfg_cfg_5072[204]), + .I1(com_cmm_cfg_wr_data_20_), + .LO(I_4695_0_a2_0_a2_0_a2_0_a2_131) + ); + defparam I_4690_0_a2_0_a2.INIT = 4'h8; + LUT2_L I_4690_0_a2_0_a2 ( + .I0(cfg_cfg_5072[205]), + .I1(com_cmm_cfg_wr_data_21_), + .LO(I_4690_0_a2_0_a2_132) + ); + defparam I_4685_0_a2_0_a2_0_a2.INIT = 4'h8; + LUT2_L I_4685_0_a2_0_a2_0_a2 ( + .I0(cfg_cfg_5072[206]), + .I1(com_cmm_cfg_wr_data_22_), + .LO(I_4685_0_a2_0_a2_0_a2_133) + ); + defparam I_4680_0_a2_0_a2_0_a2.INIT = 4'h8; + LUT2_L I_4680_0_a2_0_a2_0_a2 ( + .I0(cfg_cfg_5072[207]), + .I1(com_cmm_cfg_wr_data_23_), + .LO(I_4680_0_a2_0_a2_0_a2_134) + ); + defparam I_4675_0_a2_0_a2_0_a2.INIT = 4'h8; + LUT2_L I_4675_0_a2_0_a2_0_a2 ( + .I0(cfg_cfg_5072[208]), + .I1(com_cmm_cfg_wr_data_8_), + .LO(I_4675_0_a2_0_a2_0_a2_135) + ); + defparam I_4670_0_a2_0_a2_0_a2.INIT = 4'h8; + LUT2_L I_4670_0_a2_0_a2_0_a2 ( + .I0(cfg_cfg_5072[209]), + .I1(com_cmm_cfg_wr_data_9_), + .LO(I_4670_0_a2_0_a2_0_a2_136) + ); + defparam I_4665_0_a2_0_a2_0_a2_0_a2.INIT = 4'h8; + LUT2_L I_4665_0_a2_0_a2_0_a2_0_a2 ( + .I0(cfg_cfg_5072[210]), + .I1(com_cmm_cfg_wr_data_10_), + .LO(I_4665_0_a2_0_a2_0_a2_0_a2_137) + ); + defparam I_4660_0_a2_0_a2_0_a2.INIT = 4'h8; + LUT2_L I_4660_0_a2_0_a2_0_a2 ( + .I0(cfg_cfg_5072[211]), + .I1(com_cmm_cfg_wr_data_11_), + .LO(I_4660_0_a2_0_a2_0_a2_138) + ); + defparam I_4655_0_a2_0_a2_0_a2_0_a2.INIT = 4'h8; + LUT2_L I_4655_0_a2_0_a2_0_a2_0_a2 ( + .I0(cfg_cfg_5072[212]), + .I1(com_cmm_cfg_wr_data_12_), + .LO(I_4655_0_a2_0_a2_0_a2_0_a2_139) + ); + defparam I_4650_0_a2_0_a2_0_a2.INIT = 4'h8; + LUT2_L I_4650_0_a2_0_a2_0_a2 ( + .I0(cfg_cfg_5072[213]), + .I1(com_cmm_cfg_wr_data_13_), + .LO(I_4650_0_a2_0_a2_0_a2_140) + ); + defparam I_4645_0_a2_0_a2_0_a2.INIT = 4'h8; + LUT2_L I_4645_0_a2_0_a2_0_a2 ( + .I0(cfg_cfg_5072[214]), + .I1(com_cmm_cfg_wr_data_14_), + .LO(I_4645_0_a2_0_a2_0_a2_141) + ); + defparam I_4640_0_a2_0_a2.INIT = 4'h8; + LUT2_L I_4640_0_a2_0_a2 ( + .I0(cfg_cfg_5072[215]), + .I1(com_cmm_cfg_wr_data_15_), + .LO(I_4640_0_a2_0_a2_142) + ); + defparam I_4635_0_a2_0_a2.INIT = 4'h8; + LUT2_L I_4635_0_a2_0_a2 ( + .I0(cfg_cfg_5072[186]), + .I1(com_cmm_cfg_wr_data_2_), + .LO(I_4635_0_a2_0_a2_143) + ); + defparam I_4630_0_a2_0_a2_0_a2.INIT = 4'h8; + LUT2_L I_4630_0_a2_0_a2_0_a2 ( + .I0(cfg_cfg_5072[187]), + .I1(com_cmm_cfg_wr_data_3_), + .LO(I_4630_0_a2_0_a2_0_a2_144) + ); + defparam I_4625_0_a2_0_a2_0_a2.INIT = 4'h8; + LUT2_L I_4625_0_a2_0_a2_0_a2 ( + .I0(cfg_cfg_5072[188]), + .I1(com_cmm_cfg_wr_data_4_), + .LO(I_4625_0_a2_0_a2_0_a2_145) + ); + defparam I_4620_0_a2_0_a2_0_a2.INIT = 4'h8; + LUT2_L I_4620_0_a2_0_a2_0_a2 ( + .I0(cfg_cfg_5072[189]), + .I1(com_cmm_cfg_wr_data_5_), + .LO(I_4620_0_a2_0_a2_0_a2_146) + ); + defparam I_4615_0_a2_0_a2_0_a2.INIT = 4'h8; + LUT2_L I_4615_0_a2_0_a2_0_a2 ( + .I0(cfg_cfg_5072[190]), + .I1(com_cmm_cfg_wr_data_6_), + .LO(I_4615_0_a2_0_a2_0_a2_147) + ); + defparam I_4610_0_a2_0_a2_0_a2.INIT = 4'h8; + LUT2_L I_4610_0_a2_0_a2_0_a2 ( + .I0(cfg_cfg_5072[191]), + .I1(com_cmm_cfg_wr_data_7_), + .LO(I_4610_0_a2_0_a2_0_a2_148) + ); + defparam I_4605_0_a2_0_a2_0_a2_0_a2.INIT = 4'h8; + LUT2_L I_4605_0_a2_0_a2_0_a2_0_a2 ( + .I0(cfg_cfg_5072[196]), + .I1(com_cmm_cfg_wr_data_28_), + .LO(I_4605_0_a2_0_a2_0_a2_0_a2_149) + ); + defparam I_4600_0_a2_0_a2_0_a2_0_a2.INIT = 4'h8; + LUT2_L I_4600_0_a2_0_a2_0_a2_0_a2 ( + .I0(cfg_cfg_5072[197]), + .I1(com_cmm_cfg_wr_data_29_), + .LO(I_4600_0_a2_0_a2_0_a2_0_a2_150) + ); + defparam I_4595_0_a2_0_a2_0_a2_0_a2.INIT = 4'h8; + LUT2_L I_4595_0_a2_0_a2_0_a2_0_a2 ( + .I0(cfg_cfg_5072[198]), + .I1(com_cmm_cfg_wr_data_30_), + .LO(I_4595_0_a2_0_a2_0_a2_0_a2_151) + ); + defparam I_4590_0_a2_0_a2_0_a2_0_a2.INIT = 4'h8; + LUT2_L I_4590_0_a2_0_a2_0_a2_0_a2 ( + .I0(cfg_cfg_5072[199]), + .I1(com_cmm_cfg_wr_data_31_), + .LO(I_4590_0_a2_0_a2_0_a2_0_a2_152) + ); + defparam I_4585_0_a2_0_a2_0_a2.INIT = 4'h8; + LUT2_L I_4585_0_a2_0_a2_0_a2 ( + .I0(cfg_cfg_5072[200]), + .I1(com_cmm_cfg_wr_data_16_), + .LO(I_4585_0_a2_0_a2_0_a2_153) + ); + defparam I_4580_0_a2_0_a2_0_a2.INIT = 4'h8; + LUT2_L I_4580_0_a2_0_a2_0_a2 ( + .I0(cfg_cfg_5072[171]), + .I1(com_cmm_cfg_wr_data_19_), + .LO(I_4580_0_a2_0_a2_0_a2_154) + ); + defparam I_4575_0_a2_0_a2_0_a2_0_a2.INIT = 4'h8; + LUT2_L I_4575_0_a2_0_a2_0_a2_0_a2 ( + .I0(cfg_cfg_5072[172]), + .I1(com_cmm_cfg_wr_data_20_), + .LO(I_4575_0_a2_0_a2_0_a2_0_a2_155) + ); + defparam I_4570_0_a2_0_a2.INIT = 4'h8; + LUT2_L I_4570_0_a2_0_a2 ( + .I0(cfg_cfg_5072[173]), + .I1(com_cmm_cfg_wr_data_21_), + .LO(I_4570_0_a2_0_a2_156) + ); + defparam I_4565_0_a2_0_a2_0_a2.INIT = 4'h8; + LUT2_L I_4565_0_a2_0_a2_0_a2 ( + .I0(cfg_cfg_5072[174]), + .I1(com_cmm_cfg_wr_data_22_), + .LO(I_4565_0_a2_0_a2_0_a2_157) + ); + defparam I_4560_0_a2_0_a2_0_a2.INIT = 4'h8; + LUT2_L I_4560_0_a2_0_a2_0_a2 ( + .I0(cfg_cfg_5072[175]), + .I1(com_cmm_cfg_wr_data_23_), + .LO(I_4560_0_a2_0_a2_0_a2_158) + ); + defparam I_4555_0_a2_0_a2_0_a2.INIT = 4'h8; + LUT2_L I_4555_0_a2_0_a2_0_a2 ( + .I0(cfg_cfg_5072[176]), + .I1(com_cmm_cfg_wr_data_8_), + .LO(I_4555_0_a2_0_a2_0_a2_159) + ); + defparam I_4550_0_a2_0_a2_0_a2.INIT = 4'h8; + LUT2_L I_4550_0_a2_0_a2_0_a2 ( + .I0(cfg_cfg_5072[177]), + .I1(com_cmm_cfg_wr_data_9_), + .LO(I_4550_0_a2_0_a2_0_a2_160) + ); + defparam I_4545_0_a2_0_a2_0_a2_0_a2.INIT = 4'h8; + LUT2_L I_4545_0_a2_0_a2_0_a2_0_a2 ( + .I0(cfg_cfg_5072[178]), + .I1(com_cmm_cfg_wr_data_10_), + .LO(I_4545_0_a2_0_a2_0_a2_0_a2_161) + ); + defparam I_4540_0_a2_0_a2_0_a2.INIT = 4'h8; + LUT2_L I_4540_0_a2_0_a2_0_a2 ( + .I0(cfg_cfg_5072[179]), + .I1(com_cmm_cfg_wr_data_11_), + .LO(I_4540_0_a2_0_a2_0_a2_162) + ); + defparam I_4535_0_a2_0_a2_0_a2_0_a2.INIT = 4'h8; + LUT2_L I_4535_0_a2_0_a2_0_a2_0_a2 ( + .I0(cfg_cfg_5072[180]), + .I1(com_cmm_cfg_wr_data_12_), + .LO(I_4535_0_a2_0_a2_0_a2_0_a2_163) + ); + defparam I_4530_0_a2_0_a2_0_a2.INIT = 4'h8; + LUT2_L I_4530_0_a2_0_a2_0_a2 ( + .I0(cfg_cfg_5072[181]), + .I1(com_cmm_cfg_wr_data_13_), + .LO(I_4530_0_a2_0_a2_0_a2_164) + ); + defparam I_4525_0_a2_0_a2_0_a2.INIT = 4'h8; + LUT2_L I_4525_0_a2_0_a2_0_a2 ( + .I0(cfg_cfg_5072[182]), + .I1(com_cmm_cfg_wr_data_14_), + .LO(I_4525_0_a2_0_a2_0_a2_165) + ); + defparam I_4520_0_a2_0_a2.INIT = 4'h8; + LUT2_L I_4520_0_a2_0_a2 ( + .I0(cfg_cfg_5072[183]), + .I1(com_cmm_cfg_wr_data_15_), + .LO(I_4520_0_a2_0_a2_166) + ); + defparam I_4515_0_a2_0_a2.INIT = 4'h8; + LUT2_L I_4515_0_a2_0_a2 ( + .I0(cfg_cfg_5072[184]), + .I1(com_cmm_cfg_wr_data_0_), + .LO(I_4515_0_a2_0_a2_167) + ); + defparam I_4510_0_a2_0_a2.INIT = 4'h8; + LUT2_L I_4510_0_a2_0_a2 ( + .I0(cfg_cfg_5072[185]), + .I1(com_cmm_cfg_wr_data_1_), + .LO(I_4510_0_a2_0_a2_168) + ); + defparam I_4505_0_a2_0_a2_0_a2.INIT = 4'h8; + LUT2_L I_4505_0_a2_0_a2_0_a2 ( + .I0(cfg_cfg_5072[156]), + .I1(com_cmm_cfg_wr_data_4_), + .LO(I_4505_0_a2_0_a2_0_a2_169) + ); + defparam I_4500_0_a2_0_a2_0_a2.INIT = 4'h8; + LUT2_L I_4500_0_a2_0_a2_0_a2 ( + .I0(cfg_cfg_5072[157]), + .I1(com_cmm_cfg_wr_data_5_), + .LO(I_4500_0_a2_0_a2_0_a2_170) + ); + defparam I_4495_0_a2_0_a2_0_a2.INIT = 4'h8; + LUT2_L I_4495_0_a2_0_a2_0_a2 ( + .I0(cfg_cfg_5072[158]), + .I1(com_cmm_cfg_wr_data_6_), + .LO(I_4495_0_a2_0_a2_0_a2_171) + ); + defparam I_4490_0_a2_0_a2_0_a2.INIT = 4'h8; + LUT2_L I_4490_0_a2_0_a2_0_a2 ( + .I0(cfg_cfg_5072[159]), + .I1(com_cmm_cfg_wr_data_7_), + .LO(I_4490_0_a2_0_a2_0_a2_172) + ); + defparam I_4485_0_a2_0_a2_0_a2_0_a2.INIT = 4'h8; + LUT2_L I_4485_0_a2_0_a2_0_a2_0_a2 ( + .I0(cfg_cfg_5072[164]), + .I1(com_cmm_cfg_wr_data_28_), + .LO(I_4485_0_a2_0_a2_0_a2_0_a2_173) + ); + defparam I_4480_0_a2_0_a2_0_a2_0_a2.INIT = 4'h8; + LUT2_L I_4480_0_a2_0_a2_0_a2_0_a2 ( + .I0(cfg_cfg_5072[165]), + .I1(com_cmm_cfg_wr_data_29_), + .LO(I_4480_0_a2_0_a2_0_a2_0_a2_174) + ); + defparam I_4475_0_a2_0_a2_0_a2_0_a2.INIT = 4'h8; + LUT2_L I_4475_0_a2_0_a2_0_a2_0_a2 ( + .I0(cfg_cfg_5072[166]), + .I1(com_cmm_cfg_wr_data_30_), + .LO(I_4475_0_a2_0_a2_0_a2_0_a2_175) + ); + defparam I_4470_0_a2_0_a2_0_a2_0_a2.INIT = 4'h8; + LUT2_L I_4470_0_a2_0_a2_0_a2_0_a2 ( + .I0(cfg_cfg_5072[167]), + .I1(com_cmm_cfg_wr_data_31_), + .LO(I_4470_0_a2_0_a2_0_a2_0_a2_176) + ); + defparam I_4465_0_a2_0_a2_0_a2.INIT = 4'h8; + LUT2_L I_4465_0_a2_0_a2_0_a2 ( + .I0(cfg_cfg_5072[168]), + .I1(com_cmm_cfg_wr_data_16_), + .LO(I_4465_0_a2_0_a2_0_a2_177) + ); + defparam I_4460_0_a2_0_a2_0_a2.INIT = 4'h8; + LUT2_L I_4460_0_a2_0_a2_0_a2 ( + .I0(cfg_cfg_5072[169]), + .I1(com_cmm_cfg_wr_data_17_), + .LO(I_4460_0_a2_0_a2_0_a2_178) + ); + defparam I_4455_0_a2_0_a2_0_a2.INIT = 4'h8; + LUT2_L I_4455_0_a2_0_a2_0_a2 ( + .I0(cfg_cfg_5072[170]), + .I1(com_cmm_cfg_wr_data_18_), + .LO(I_4455_0_a2_0_a2_0_a2_179) + ); + defparam I_4450_0_a2_0_a2.INIT = 4'h8; + LUT2_L I_4450_0_a2_0_a2 ( + .I0(cfg_cfg_5072[141]), + .I1(com_cmm_cfg_wr_data_21_), + .LO(I_4450_0_a2_0_a2_180) + ); + defparam I_4445_0_a2_0_a2_0_a2.INIT = 4'h8; + LUT2_L I_4445_0_a2_0_a2_0_a2 ( + .I0(cfg_cfg_5072[142]), + .I1(com_cmm_cfg_wr_data_22_), + .LO(I_4445_0_a2_0_a2_0_a2_181) + ); + defparam I_4440_0_a2_0_a2_0_a2.INIT = 4'h8; + LUT2_L I_4440_0_a2_0_a2_0_a2 ( + .I0(cfg_cfg_5072[143]), + .I1(com_cmm_cfg_wr_data_23_), + .LO(I_4440_0_a2_0_a2_0_a2_182) + ); + defparam I_4435_0_a2_0_a2_0_a2.INIT = 4'h8; + LUT2_L I_4435_0_a2_0_a2_0_a2 ( + .I0(cfg_cfg_5072[144]), + .I1(com_cmm_cfg_wr_data_8_), + .LO(I_4435_0_a2_0_a2_0_a2_183) + ); + defparam I_4430_0_a2_0_a2_0_a2.INIT = 4'h8; + LUT2_L I_4430_0_a2_0_a2_0_a2 ( + .I0(cfg_cfg_5072[145]), + .I1(com_cmm_cfg_wr_data_9_), + .LO(I_4430_0_a2_0_a2_0_a2_184) + ); + defparam I_4425_0_a2_0_a2_0_a2_0_a2.INIT = 4'h8; + LUT2_L I_4425_0_a2_0_a2_0_a2_0_a2 ( + .I0(cfg_cfg_5072[146]), + .I1(com_cmm_cfg_wr_data_10_), + .LO(I_4425_0_a2_0_a2_0_a2_0_a2_185) + ); + defparam I_4420_0_a2_0_a2_0_a2.INIT = 4'h8; + LUT2_L I_4420_0_a2_0_a2_0_a2 ( + .I0(cfg_cfg_5072[147]), + .I1(com_cmm_cfg_wr_data_11_), + .LO(I_4420_0_a2_0_a2_0_a2_186) + ); + defparam I_4415_0_a2_0_a2_0_a2_0_a2.INIT = 4'h8; + LUT2_L I_4415_0_a2_0_a2_0_a2_0_a2 ( + .I0(cfg_cfg_5072[148]), + .I1(com_cmm_cfg_wr_data_12_), + .LO(I_4415_0_a2_0_a2_0_a2_0_a2_187) + ); + defparam I_4410_0_a2_0_a2_0_a2.INIT = 4'h8; + LUT2_L I_4410_0_a2_0_a2_0_a2 ( + .I0(cfg_cfg_5072[149]), + .I1(com_cmm_cfg_wr_data_13_), + .LO(I_4410_0_a2_0_a2_0_a2_188) + ); + defparam I_4405_0_a2_0_a2_0_a2.INIT = 4'h8; + LUT2_L I_4405_0_a2_0_a2_0_a2 ( + .I0(cfg_cfg_5072[150]), + .I1(com_cmm_cfg_wr_data_14_), + .LO(I_4405_0_a2_0_a2_0_a2_189) + ); + defparam I_4400_0_a2_0_a2.INIT = 4'h8; + LUT2_L I_4400_0_a2_0_a2 ( + .I0(cfg_cfg_5072[151]), + .I1(com_cmm_cfg_wr_data_15_), + .LO(I_4400_0_a2_0_a2_190) + ); + defparam I_4395_0_a2_0_a2.INIT = 4'h8; + LUT2_L I_4395_0_a2_0_a2 ( + .I0(cfg_cfg_5072[152]), + .I1(com_cmm_cfg_wr_data_0_), + .LO(I_4395_0_a2_0_a2_191) + ); + defparam I_4390_0_a2_0_a2.INIT = 4'h8; + LUT2_L I_4390_0_a2_0_a2 ( + .I0(cfg_cfg_5072[153]), + .I1(com_cmm_cfg_wr_data_1_), + .LO(I_4390_0_a2_0_a2_192) + ); + defparam I_4385_0_a2_0_a2.INIT = 4'h8; + LUT2_L I_4385_0_a2_0_a2 ( + .I0(cfg_cfg_5072[154]), + .I1(com_cmm_cfg_wr_data_2_), + .LO(I_4385_0_a2_0_a2_193) + ); + defparam I_4380_0_a2_0_a2_0_a2.INIT = 4'h8; + LUT2_L I_4380_0_a2_0_a2_0_a2 ( + .I0(cfg_cfg_5072[155]), + .I1(com_cmm_cfg_wr_data_3_), + .LO(I_4380_0_a2_0_a2_0_a2_194) + ); + defparam I_4375_0_a2_0_a2_0_a2.INIT = 4'h8; + LUT2_L I_4375_0_a2_0_a2_0_a2 ( + .I0(cfg_cfg_5072[126]), + .I1(com_cmm_cfg_wr_data_6_), + .LO(I_4375_0_a2_0_a2_0_a2_195) + ); + defparam I_4370_0_a2_0_a2_0_a2.INIT = 4'h8; + LUT2_L I_4370_0_a2_0_a2_0_a2 ( + .I0(cfg_cfg_5072[127]), + .I1(com_cmm_cfg_wr_data_7_), + .LO(I_4370_0_a2_0_a2_0_a2_196) + ); + defparam I_4365_0_a2_0_a2_0_a2_0_a2.INIT = 4'h8; + LUT2_L I_4365_0_a2_0_a2_0_a2_0_a2 ( + .I0(cfg_cfg_5072[132]), + .I1(com_cmm_cfg_wr_data_28_), + .LO(I_4365_0_a2_0_a2_0_a2_0_a2_197) + ); + defparam I_4360_0_a2_0_a2_0_a2_0_a2.INIT = 4'h8; + LUT2_L I_4360_0_a2_0_a2_0_a2_0_a2 ( + .I0(cfg_cfg_5072[133]), + .I1(com_cmm_cfg_wr_data_29_), + .LO(I_4360_0_a2_0_a2_0_a2_0_a2_198) + ); + defparam I_4355_0_a2_0_a2_0_a2_0_a2.INIT = 4'h8; + LUT2_L I_4355_0_a2_0_a2_0_a2_0_a2 ( + .I0(cfg_cfg_5072[134]), + .I1(com_cmm_cfg_wr_data_30_), + .LO(I_4355_0_a2_0_a2_0_a2_0_a2_199) + ); + defparam I_4350_0_a2_0_a2_0_a2_0_a2.INIT = 4'h8; + LUT2_L I_4350_0_a2_0_a2_0_a2_0_a2 ( + .I0(cfg_cfg_5072[135]), + .I1(com_cmm_cfg_wr_data_31_), + .LO(I_4350_0_a2_0_a2_0_a2_0_a2_200) + ); + defparam I_4345_0_a2_0_a2_0_a2.INIT = 4'h8; + LUT2_L I_4345_0_a2_0_a2_0_a2 ( + .I0(cfg_cfg_5072[136]), + .I1(com_cmm_cfg_wr_data_16_), + .LO(I_4345_0_a2_0_a2_0_a2_201) + ); + defparam I_4340_0_a2_0_a2_0_a2.INIT = 4'h8; + LUT2_L I_4340_0_a2_0_a2_0_a2 ( + .I0(cfg_cfg_5072[137]), + .I1(com_cmm_cfg_wr_data_17_), + .LO(I_4340_0_a2_0_a2_0_a2_202) + ); + defparam I_4335_0_a2_0_a2_0_a2.INIT = 4'h8; + LUT2_L I_4335_0_a2_0_a2_0_a2 ( + .I0(cfg_cfg_5072[138]), + .I1(com_cmm_cfg_wr_data_18_), + .LO(I_4335_0_a2_0_a2_0_a2_203) + ); + defparam I_4330_0_a2_0_a2_0_a2.INIT = 4'h8; + LUT2_L I_4330_0_a2_0_a2_0_a2 ( + .I0(cfg_cfg_5072[139]), + .I1(com_cmm_cfg_wr_data_19_), + .LO(I_4330_0_a2_0_a2_0_a2_204) + ); + defparam I_4325_0_a2_0_a2_0_a2_0_a2.INIT = 4'h8; + LUT2_L I_4325_0_a2_0_a2_0_a2_0_a2 ( + .I0(cfg_cfg_5072[140]), + .I1(com_cmm_cfg_wr_data_20_), + .LO(I_4325_0_a2_0_a2_0_a2_0_a2_205) + ); + defparam I_4320_0_a2_0_a2_0_a2.INIT = 4'h8; + LUT2_L I_4320_0_a2_0_a2_0_a2 ( + .I0(cfg_cfg_5072[111]), + .I1(com_cmm_cfg_wr_data_23_), + .LO(I_4320_0_a2_0_a2_0_a2_206) + ); + defparam I_4315_0_a2_0_a2_0_a2.INIT = 4'h8; + LUT2_L I_4315_0_a2_0_a2_0_a2 ( + .I0(cfg_cfg_5072[112]), + .I1(com_cmm_cfg_wr_data_8_), + .LO(I_4315_0_a2_0_a2_0_a2_207) + ); + defparam I_4310_0_a2_0_a2_0_a2.INIT = 4'h8; + LUT2_L I_4310_0_a2_0_a2_0_a2 ( + .I0(cfg_cfg_5072[113]), + .I1(com_cmm_cfg_wr_data_9_), + .LO(I_4310_0_a2_0_a2_0_a2_208) + ); + defparam I_4305_0_a2_0_a2_0_a2_0_a2.INIT = 4'h8; + LUT2_L I_4305_0_a2_0_a2_0_a2_0_a2 ( + .I0(cfg_cfg_5072[114]), + .I1(com_cmm_cfg_wr_data_10_), + .LO(I_4305_0_a2_0_a2_0_a2_0_a2_209) + ); + defparam I_4300_0_a2_0_a2_0_a2.INIT = 4'h8; + LUT2_L I_4300_0_a2_0_a2_0_a2 ( + .I0(cfg_cfg_5072[115]), + .I1(com_cmm_cfg_wr_data_11_), + .LO(I_4300_0_a2_0_a2_0_a2_210) + ); + defparam I_4295_0_a2_0_a2_0_a2_0_a2.INIT = 4'h8; + LUT2_L I_4295_0_a2_0_a2_0_a2_0_a2 ( + .I0(cfg_cfg_5072[116]), + .I1(com_cmm_cfg_wr_data_12_), + .LO(I_4295_0_a2_0_a2_0_a2_0_a2_211) + ); + defparam I_4290_0_a2_0_a2_0_a2.INIT = 4'h8; + LUT2_L I_4290_0_a2_0_a2_0_a2 ( + .I0(cfg_cfg_5072[117]), + .I1(com_cmm_cfg_wr_data_13_), + .LO(I_4290_0_a2_0_a2_0_a2_212) + ); + defparam I_4285_0_a2_0_a2_0_a2.INIT = 4'h8; + LUT2_L I_4285_0_a2_0_a2_0_a2 ( + .I0(cfg_cfg_5072[118]), + .I1(com_cmm_cfg_wr_data_14_), + .LO(I_4285_0_a2_0_a2_0_a2_213) + ); + defparam I_4280_0_a2_0_a2.INIT = 4'h8; + LUT2_L I_4280_0_a2_0_a2 ( + .I0(cfg_cfg_5072[119]), + .I1(com_cmm_cfg_wr_data_15_), + .LO(I_4280_0_a2_0_a2_214) + ); + defparam I_4275_0_a2_0_a2.INIT = 4'h8; + LUT2_L I_4275_0_a2_0_a2 ( + .I0(cfg_cfg_5072[120]), + .I1(com_cmm_cfg_wr_data_0_), + .LO(I_4275_0_a2_0_a2_215) + ); + defparam I_4270_0_a2_0_a2.INIT = 4'h8; + LUT2_L I_4270_0_a2_0_a2 ( + .I0(cfg_cfg_5072[121]), + .I1(com_cmm_cfg_wr_data_1_), + .LO(I_4270_0_a2_0_a2_216) + ); + defparam I_4265_0_a2_0_a2.INIT = 4'h8; + LUT2_L I_4265_0_a2_0_a2 ( + .I0(cfg_cfg_5072[122]), + .I1(com_cmm_cfg_wr_data_2_), + .LO(I_4265_0_a2_0_a2_217) + ); + defparam I_4260_0_a2_0_a2_0_a2.INIT = 4'h8; + LUT2_L I_4260_0_a2_0_a2_0_a2 ( + .I0(cfg_cfg_5072[123]), + .I1(com_cmm_cfg_wr_data_3_), + .LO(I_4260_0_a2_0_a2_0_a2_218) + ); + defparam I_4255_0_a2_0_a2_0_a2.INIT = 4'h8; + LUT2_L I_4255_0_a2_0_a2_0_a2 ( + .I0(cfg_cfg_5072[124]), + .I1(com_cmm_cfg_wr_data_4_), + .LO(I_4255_0_a2_0_a2_0_a2_219) + ); + defparam I_4250_0_a2_0_a2_0_a2.INIT = 4'h8; + LUT2_L I_4250_0_a2_0_a2_0_a2 ( + .I0(cfg_cfg_5072[125]), + .I1(com_cmm_cfg_wr_data_5_), + .LO(I_4250_0_a2_0_a2_0_a2_220) + ); + defparam I_4245_0_a2_0_a2_0_a2_0_a2.INIT = 4'h8; + LUT2_L I_4245_0_a2_0_a2_0_a2_0_a2 ( + .I0(cfg_cfg_5072[100]), + .I1(com_cmm_cfg_wr_data_28_), + .LO(I_4245_0_a2_0_a2_0_a2_0_a2_221) + ); + defparam I_4240_0_a2_0_a2_0_a2_0_a2.INIT = 4'h8; + LUT2_L I_4240_0_a2_0_a2_0_a2_0_a2 ( + .I0(cfg_cfg_5072[101]), + .I1(com_cmm_cfg_wr_data_29_), + .LO(I_4240_0_a2_0_a2_0_a2_0_a2_222) + ); + defparam I_4235_0_a2_0_a2_0_a2_0_a2.INIT = 4'h8; + LUT2_L I_4235_0_a2_0_a2_0_a2_0_a2 ( + .I0(cfg_cfg_5072[102]), + .I1(com_cmm_cfg_wr_data_30_), + .LO(I_4235_0_a2_0_a2_0_a2_0_a2_223) + ); + defparam I_4230_0_a2_0_a2_0_a2_0_a2.INIT = 4'h8; + LUT2_L I_4230_0_a2_0_a2_0_a2_0_a2 ( + .I0(cfg_cfg_5072[103]), + .I1(com_cmm_cfg_wr_data_31_), + .LO(I_4230_0_a2_0_a2_0_a2_0_a2_224) + ); + defparam I_4225_0_a2_0_a2_0_a2.INIT = 4'h8; + LUT2_L I_4225_0_a2_0_a2_0_a2 ( + .I0(cfg_cfg_5072[104]), + .I1(com_cmm_cfg_wr_data_16_), + .LO(I_4225_0_a2_0_a2_0_a2_225) + ); + defparam I_4220_0_a2_0_a2_0_a2.INIT = 4'h8; + LUT2_L I_4220_0_a2_0_a2_0_a2 ( + .I0(cfg_cfg_5072[105]), + .I1(com_cmm_cfg_wr_data_17_), + .LO(I_4220_0_a2_0_a2_0_a2_226) + ); + defparam I_4215_0_a2_0_a2_0_a2.INIT = 4'h8; + LUT2_L I_4215_0_a2_0_a2_0_a2 ( + .I0(cfg_cfg_5072[106]), + .I1(com_cmm_cfg_wr_data_18_), + .LO(I_4215_0_a2_0_a2_0_a2_227) + ); + defparam I_4210_0_a2_0_a2_0_a2.INIT = 4'h8; + LUT2_L I_4210_0_a2_0_a2_0_a2 ( + .I0(cfg_cfg_5072[107]), + .I1(com_cmm_cfg_wr_data_19_), + .LO(I_4210_0_a2_0_a2_0_a2_228) + ); + defparam I_4205_0_a2_0_a2_0_a2_0_a2.INIT = 4'h8; + LUT2_L I_4205_0_a2_0_a2_0_a2_0_a2 ( + .I0(cfg_cfg_5072[108]), + .I1(com_cmm_cfg_wr_data_20_), + .LO(I_4205_0_a2_0_a2_0_a2_0_a2_229) + ); + defparam I_4200_0_a2_0_a2.INIT = 4'h8; + LUT2_L I_4200_0_a2_0_a2 ( + .I0(cfg_cfg_5072[109]), + .I1(com_cmm_cfg_wr_data_21_), + .LO(I_4200_0_a2_0_a2_230) + ); + defparam I_4195_0_a2_0_a2_0_a2.INIT = 4'h8; + LUT2_L I_4195_0_a2_0_a2_0_a2 ( + .I0(cfg_cfg_5072[110]), + .I1(com_cmm_cfg_wr_data_22_), + .LO(I_4195_0_a2_0_a2_0_a2_231) + ); + defparam m4.INIT = 16'h9669; + LUT4_L m4 ( + .I0(N_48877_i), + .I1(com_cmml_protocol_err_n), + .I2(com_tlm_cmmt_err_rbuf_overflow), + .I3(m4_1_232), + .LO(N_5_i) + ); + defparam m12_0_0_0.INIT = 8'hC4; + LUT3_L m12_0_0_0 ( + .I0(N_50488), + .I1(m12_0_0_0_32183_233), + .I2(com_tlm_cmmt_err_tlp_malformed), + .LO(N_13_i) + ); + defparam m14_0_a2_0_a2_0_a2.INIT = 8'h04; + LUT3_L m14_0_a2_0_a2_0_a2 ( + .I0(N_48877_i), + .I1(N_48961_i), + .I2(com_cmml_protocol_err_n), + .LO(com_cmm_u_cmm_errman_wtd_ftl_to_incrdf2) + ); + defparam N_68622_i.INIT = 8'hEC; + LUT3_L N_68622_i ( + .I0(N_49558), + .I1(com_cmm_u_cmm_dataproducer_byte_00_1_sqmuxa_1), + .I2(com_cmm_u_cmm_dataproducer_req_gnt_code_3__234), + .LO(N_68622_i_235) + ); + defparam I_32469.INIT = 4'h1; + LUT1_L I_32469 ( + .I0(cfg_trn_pending_n), + .LO(cfg_trn_pending_n_i) + ); + defparam N_6_i.INIT = 16'h9E69; + LUT4_L N_6_i ( + .I0(com_cmm_u_cmm_errman_wtd_nfl_add_input_five_n_d_236), + .I1(com_cmm_u_cmm_errman_wtd_nfl_add_input_four_n_d_237), + .I2(com_cmm_u_cmm_errman_wtd_nfl_add_input_one_d_238), + .I3(com_cmm_u_cmm_errman_wtd_nfl_add_input_two_n_d_239), + .LO(N_6_i_240) + ); + defparam m9.INIT = 16'h71E7; + LUT4_L m9 ( + .I0(com_cmm_u_cmm_errman_wtd_nfl_add_input_five_n_d_236), + .I1(com_cmm_u_cmm_errman_wtd_nfl_add_input_four_n_d_237), + .I2(com_cmm_u_cmm_errman_wtd_nfl_add_input_one_d_238), + .I3(com_cmm_u_cmm_errman_wtd_nfl_add_input_two_n_d_239), + .LO(com_cmm_u_cmm_errman_wtd_nfl_to_incr_0df1) + ); + defparam m11.INIT = 16'h0010; + LUT4_L m11 ( + .I0(com_cmm_u_cmm_errman_wtd_nfl_add_input_five_n_d_236), + .I1(com_cmm_u_cmm_errman_wtd_nfl_add_input_four_n_d_237), + .I2(com_cmm_u_cmm_errman_wtd_nfl_add_input_one_d_238), + .I3(com_cmm_u_cmm_errman_wtd_nfl_add_input_two_n_d_239), + .LO(com_cmm_u_cmm_errman_wtd_nfl_to_incr_0df2) + ); + defparam N_62724_i.INIT = 16'h533C; + LUT4_L N_62724_i ( + .I0(m7_0_241), + .I1(m3_0_242), + .I2(com_cmm_u_cmm_errman_wtd_cor_add_input_five_n_d_243), + .I3(com_cmm_u_cmm_errman_wtd_cor_add_input_four_n_d_244), + .LO(N_62724_i_245) + ); + defparam m17.INIT = 16'hA335; + LUT4_L m17 ( + .I0(m13_0_246), + .I1(m14_247), + .I2(com_cmm_u_cmm_errman_wtd_cor_add_input_five_n_d_243), + .I3(com_cmm_u_cmm_errman_wtd_cor_add_input_four_n_d_244), + .LO(com_cmm_u_cmm_errman_wtd_cor_to_incr_0df1) + ); + defparam m25.INIT = 16'hCAAC; + LUT4_L m25 ( + .I0(m21_248), + .I1(m22_249), + .I2(com_cmm_u_cmm_errman_wtd_cor_add_input_five_n_d_243), + .I3(com_cmm_u_cmm_errman_wtd_cor_add_input_four_n_d_244), + .LO(com_cmm_u_cmm_errman_wtd_cor_to_incr_0df2) + ); + defparam G_28.INIT = 8'h96; + LUT3 G_28 ( + .I0(N_10582_1), + .I1(N_27442), + .I2(N_27500), + .O(N_32) + ); + defparam m2_0_0.INIT = 8'h07; + LUT3 m2_0_0 ( + .I0(plm_sym_sym_gen_next_addr[0]), + .I1(plm_sym_sym_gen_next_addr[1]), + .I2(plm_sym_sym_gen_next_addr[2]), + .O(N_172) + ); + defparam G_2997.INIT = 4'h4; + LUT2 G_2997 ( + .I0(plm_sym_sym_gen_next_addr[0]), + .I1(plm_sym_sym_gen_next_addr[3]), + .O(N_3004) + ); + defparam I_5066_0_a2_i_0.INIT = 16'h0400; + LUT4 I_5066_0_a2_i_0 ( + .I0(N_38123_i), + .I1(N_38124_i), + .I2(plm_fsm_cc_counter0_reg_rx_expired_250), + .I3(plm_rx0_ts2_c), + .O(N_24768_i) + ); + defparam I_5131_0_a2_0_a2_i.INIT = 16'h0400; + LUT4 I_5131_0_a2_0_a2_i ( + .I0(N_38100_i), + .I1(N_38124_i), + .I2(plm_fsm_rc_counter_ts2_0_reg_rx_expired_251), + .I3(plm_rx0_ts2_c), + .O(N_37268_i) + ); + defparam I_5091_i_0_0.INIT = 8'h08; + LUT3 I_5091_i_0_0 ( + .I0(N_38240_i), + .I1(plm_fsm_reg_state_13__41), + .I2(plm_fsm_rl_counter0_reg_rx_expired_40), + .O(N_18708_i) + ); + defparam G_353.INIT = 16'h6996; + LUT4 G_353 ( + .I0(N_10393), + .I1(N_10448), + .I2(N_27488), + .I3(com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d64_22__48), + .O(N_10495) + ); + defparam I_5112_i_0_0.INIT = 16'h0100; + LUT4 I_5112_i_0_0 ( + .I0(N_38100_i), + .I1(N_38124_i), + .I2(plm_fsm_rc_counter_ts1_0_reg_rx_expired_252), + .I3(plm_rx0_ts1_c), + .O(N_18912_i) + ); + defparam I_5091_i_0_0_o4.INIT = 4'h2; + LUT2 I_5091_i_0_0_o4 ( + .I0(N_38124_i), + .I1(N_38174_i), + .O(N_38240_i) + ); + defparam m12_0_0_0_32183.INIT = 16'hD0B1; + LUT4_L m12_0_0_0_32183 ( + .I0(N_48877_i), + .I1(N_48961_i), + .I2(m12_0_0_0_o3_253), + .I3(com_cmml_protocol_err_n), + .LO(m12_0_0_0_32183_233) + ); + defparam G_346.INIT = 8'h96; + LUT3 G_346 ( + .I0(N_53), + .I1(N_10559_1), + .I2(N_27511), + .O(N_10488) + ); + defparam G_339.INIT = 16'h6996; + LUT4 G_339 ( + .I0(N_14), + .I1(N_10352_1), + .I2(N_27418), + .I3(G_339_32076_254), + .O(N_10481) + ); + defparam G_340.INIT = 16'h6996; + LUT4 G_340 ( + .I0(N_36), + .I1(N_10351), + .I2(N_27411), + .I3(N_27564), + .O(N_10482) + ); + defparam G_338.INIT = 8'h96; + LUT3 G_338 ( + .I0(N_10346), + .I1(N_10480_1), + .I2(N_27564), + .O(N_10480) + ); + defparam G_337.INIT = 8'h96; + LUT3 G_337 ( + .I0(N_64), + .I1(N_10500_1), + .I2(N_27564), + .O(N_10479) + ); + defparam G_432.INIT = 8'h96; + LUT3 G_432 ( + .I0(N_14), + .I1(N_10477), + .I2(N_10574_1), + .O(N_10574) + ); + defparam G_423.INIT = 16'h6996; + LUT4 G_423 ( + .I0(N_10_1), + .I1(N_40), + .I2(N_10347_1), + .I3(N_27419), + .O(N_10565) + ); + defparam G_345.INIT = 16'h9669; + LUT4 G_345 ( + .I0(N_32), + .I1(N_10340), + .I2(N_27511), + .I3(N_27655), + .O(N_10487) + ); + defparam G_427.INIT = 16'h6996; + LUT4 G_427 ( + .I0(N_58_1), + .I1(N_10339), + .I2(N_10486_1), + .I3(N_27427), + .O(N_10569) + ); + defparam G_357.INIT = 16'h6996; + LUT4 G_357 ( + .I0(G_431_0), + .I1(N_19_1), + .I2(N_10340), + .I3(N_27411), + .O(N_10499) + ); + defparam G_368.INIT = 16'h6996; + LUT4 G_368 ( + .I0(G_368_0_255), + .I1(N_41_1), + .I2(N_92_1), + .I3(N_10351), + .O(N_10510) + ); + defparam G_460.INIT = 16'h6996; + LUT4 G_460 ( + .I0(G_460_0_256), + .I1(N_160_1), + .I2(N_10345), + .I3(N_10351), + .O(N_10602) + ); + defparam G_474.INIT = 16'h6996; + LUT4 G_474 ( + .I0(N_36), + .I1(N_52), + .I2(N_159_1), + .I3(N_160_1), + .O(N_10616) + ); + MUXF5 m22 ( + .I0(m22_am_257), + .I1(m22_bm_258), + .O(m22_249), + .S(com_cmm_u_cmm_errman_wtd_cor_add_input_five_n_d_243) + ); + defparam m22_bm.INIT = 16'h0002; + LUT4 m22_bm ( + .I0(com_cmm_u_cmm_errman_wtd_cor_add_input_one_d_259), + .I1(com_cmm_u_cmm_errman_wtd_cor_add_input_six_n_d_260), + .I2(com_cmm_u_cmm_errman_wtd_cor_add_input_three_n_d_261), + .I3(com_cmm_u_cmm_errman_wtd_cor_add_input_two_n_d_262), + .O(m22_bm_258) + ); + defparam m22_am.INIT = 16'hCC5F; + LUT4 m22_am ( + .I0(m10_263), + .I1(m12_264), + .I2(com_cmm_u_cmm_errman_wtd_cor_add_input_six_n_d_260), + .I3(com_cmm_u_cmm_errman_wtd_cor_add_input_three_n_d_261), + .O(m22_am_257) + ); + defparam G_469_0_x4_0_x4.INIT = 16'h6996; + LUT4 G_469_0_x4_0_x4 ( + .I0(N_10453_1), + .I1(N_27376), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d64_16__47), + .I3(com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d64_30__46), + .O(N_27398_i_0) + ); + defparam G_372.INIT = 8'h96; + LUT3 G_372 ( + .I0(N_12), + .I1(N_22), + .I2(N_27407), + .O(N_10514) + ); + defparam G_369.INIT = 8'h69; + LUT3 G_369 ( + .I0(N_30), + .I1(N_32), + .I2(N_27655), + .O(N_10511) + ); + defparam G_358.INIT = 4'h6; + LUT2 G_358 ( + .I0(N_10343), + .I1(N_10500_1), + .O(N_10500) + ); + defparam G_464_i_x4_0_x4.INIT = 16'h9669; + LUT4 G_464_i_x4_0_x4 ( + .I0(G_318_1_0_265), + .I1(N_10554_1), + .I2(N_27488), + .I3(com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d64_16__47), + .O(N_27402_i_0) + ); + defparam G_363.INIT = 8'h96; + LUT3 G_363 ( + .I0(N_3), + .I1(N_10341), + .I2(N_27523), + .O(N_10505) + ); + defparam G_461_0_x4.INIT = 16'h6996; + LUT4 G_461_0_x4 ( + .I0(N_10_1), + .I1(N_10478), + .I2(N_27412), + .I3(N_27507), + .O(N_27391_i_0) + ); + defparam m16_i_0_4.INIT = 16'h8C00; + LUT4_L m16_i_0_4 ( + .I0(N_36400_i), + .I1(N_36431_i), + .I2(com_lnk_rd[6]), + .I3(m16_i_0_0_266), + .LO(m16_i_0_4_20) + ); + defparam G_2996_0_a2_0_a2_0_a2.INIT = 4'h2; + LUT2 G_2996_0_a2_0_a2_0_a2 ( + .I0(N_44884_i), + .I1(com_cmm_rst_267), + .O(G_2996_0_a2_0_a2_0_a2_268) + ); + defparam I_5112_i_0_0_o3.INIT = 4'h8; + LUT2 I_5112_i_0_0_o3 ( + .I0(N_8824), + .I1(N_38113_i), + .O(N_38124_i) + ); + defparam G_368_0.INIT = 4'h9; + LUT2_L G_368_0 ( + .I0(N_38), + .I1(N_27655), + .LO(G_368_0_255) + ); + defparam G_336.INIT = 16'h9669; + LUT4 G_336 ( + .I0(N_51_1), + .I1(N_10574_1), + .I2(N_27564), + .I3(N_27661), + .O(N_10478) + ); + defparam G_341.INIT = 8'h69; + LUT3 G_341 ( + .I0(N_3), + .I1(N_10486_1), + .I2(N_27655), + .O(N_10483) + ); + defparam G_438.INIT = 8'h69; + LUT3 G_438 ( + .I0(N_10343), + .I1(N_27511), + .I2(N_27678), + .O(N_10580) + ); + defparam G_356.INIT = 8'h96; + LUT3 G_356 ( + .I0(N_10394), + .I1(N_10498_1), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d64_22__48), + .O(N_10498) + ); + defparam G_347.INIT = 8'h96; + LUT3 G_347 ( + .I0(N_10344), + .I1(N_27423), + .I2(N_27511), + .O(N_10489) + ); + defparam G_297.INIT = 4'h6; + LUT2 G_297 ( + .I0(N_10439_1), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d64_24__269), + .O(N_10439) + ); + defparam G_306.INIT = 8'h96; + LUT3 G_306 ( + .I0(N_10453_1), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d64_16__47), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d64_29__270), + .O(N_10448) + ); + defparam G_358_1.INIT = 16'h9669; + LUT4 G_358_1 ( + .I0(N_10348_1), + .I1(N_27373), + .I2(N_27405), + .I3(N_27666), + .O(N_10500_1) + ); + defparam G_338_1.INIT = 16'h9669; + LUT4 G_338_1 ( + .I0(N_112_1), + .I1(N_10344), + .I2(N_27423), + .I3(N_27664), + .O(N_10480_1) + ); + defparam G_367.INIT = 16'h6996; + LUT4 G_367 ( + .I0(G_367_0_271), + .I1(N_10554_1), + .I2(N_27491), + .I3(N_27498), + .O(N_10509) + ); + defparam G_475.INIT = 16'h6996; + LUT4 G_475 ( + .I0(N_55), + .I1(N_10582_1), + .I2(N_27373), + .I3(N_27523), + .O(N_10617) + ); + defparam G_408.INIT = 4'h6; + LUT2 G_408 ( + .I0(N_32), + .I1(N_10346), + .O(N_10550) + ); + defparam G_409.INIT = 4'h6; + LUT2 G_409 ( + .I0(N_12), + .I1(N_30), + .O(N_10551) + ); + defparam G_404_0_x4.INIT = 4'h6; + LUT2 G_404_0_x4 ( + .I0(N_3), + .I1(N_27374), + .O(N_27399_i_0) + ); + defparam G_414_0_x4.INIT = 16'h6996; + LUT4 G_414_0_x4 ( + .I0(N_10_1), + .I1(N_27372), + .I2(N_27412), + .I3(N_27507), + .O(N_27401_i_0) + ); + defparam G_468.INIT = 4'h6; + LUT2 G_468 ( + .I0(N_10347), + .I1(N_10610_1), + .O(N_10610) + ); + defparam G_360_1.INIT = 8'h96; + LUT3 G_360_1 ( + .I0(N_26_1), + .I1(N_87_1), + .I2(N_10346), + .O(N_10502_1) + ); + defparam G_449_0_x4.INIT = 4'h6; + LUT2 G_449_0_x4 ( + .I0(N_10341), + .I1(N_27373), + .O(N_27400_i_0) + ); + defparam m5_2_i_0_32074.INIT = 16'hC7B7; + LUT4 m5_2_i_0_32074 ( + .I0(com_lnk_rd[0]), + .I1(com_lnk_rd[1]), + .I2(com_lnk_rd[2]), + .I3(com_lnk_rd[3]), + .O(m5_2_i_0_32074_57) + ); + defparam G_428.INIT = 8'h96; + LUT3 G_428 ( + .I0(G_428_0), + .I1(N_116), + .I2(N_136), + .O(G_428_272) + ); + defparam G_437.INIT = 8'h96; + LUT3 G_437 ( + .I0(N_168), + .I1(N_189), + .I2(data_in_q[15]), + .O(G_437_273) + ); + defparam G_359.INIT = 8'h96; + LUT3 G_359 ( + .I0(N_131), + .I1(G_129_274), + .I2(data_in_q[14]), + .O(G_359_275) + ); + defparam G_373.INIT = 8'h96; + LUT3 G_373 ( + .I0(N_131), + .I1(G_149_276), + .I2(data_in_q[11]), + .O(G_373_277) + ); + defparam G_382.INIT = 8'h96; + LUT3 G_382 ( + .I0(N_10524_1), + .I1(data_in_q[45]), + .I2(data_in_q[48]), + .O(G_382_278) + ); + defparam I_5041_i_0_0.INIT = 4'h2; + LUT2 I_5041_i_0_0 ( + .I0(N_38420), + .I1(plm_fsm_pa_counter0_reg_rx_expired_43), + .O(N_18705_i) + ); + defparam G_463.INIT = 8'h96; + LUT3 G_463 ( + .I0(G_463_2_279), + .I1(N_115), + .I2(N_118), + .O(G_463_280) + ); + defparam G_390.INIT = 16'h6996; + LUT4 G_390 ( + .I0(N_243), + .I1(N_10388), + .I2(com_llm_llm_tx_top_tx_dllp_td_27_), + .I3(com_llm_llm_tx_top_tx_dllp_td_28_), + .O(N_10532) + ); + defparam G_407.INIT = 16'h6996; + LUT4 G_407 ( + .I0(N_10549_1), + .I1(com_llm_llm_tx_top_tx_dllp_td_25_), + .I2(com_llm_llm_tx_top_tx_dllp_td_26_), + .I3(com_llm_llm_tx_top_tx_dllp_td_40_), + .O(N_10549) + ); + defparam G_405.INIT = 8'h96; + LUT3 G_405 ( + .I0(G_405_2_281), + .I1(N_179), + .I2(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_29_), + .O(N_10547) + ); + defparam G_406.INIT = 16'h6996; + LUT4 G_406 ( + .I0(G_406_1_282), + .I1(N_10548_1), + .I2(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_8_), + .I3(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_15_), + .O(N_10548) + ); + defparam m21.INIT = 16'h022B; + LUT4 m21 ( + .I0(com_cmm_u_cmm_errman_wtd_cor_add_input_one_d_259), + .I1(com_cmm_u_cmm_errman_wtd_cor_add_input_six_n_d_260), + .I2(com_cmm_u_cmm_errman_wtd_cor_add_input_three_n_d_261), + .I3(com_cmm_u_cmm_errman_wtd_cor_add_input_two_n_d_262), + .O(m21_248) + ); + defparam m14.INIT = 16'h422B; + LUT4 m14 ( + .I0(com_cmm_u_cmm_errman_wtd_cor_add_input_one_d_259), + .I1(com_cmm_u_cmm_errman_wtd_cor_add_input_six_n_d_260), + .I2(com_cmm_u_cmm_errman_wtd_cor_add_input_three_n_d_261), + .I3(com_cmm_u_cmm_errman_wtd_cor_add_input_two_n_d_262), + .O(m14_247) + ); + defparam m13_0.INIT = 16'h2BBD; + LUT4 m13_0 ( + .I0(com_cmm_u_cmm_errman_wtd_cor_add_input_one_d_259), + .I1(com_cmm_u_cmm_errman_wtd_cor_add_input_six_n_d_260), + .I2(com_cmm_u_cmm_errman_wtd_cor_add_input_three_n_d_261), + .I3(com_cmm_u_cmm_errman_wtd_cor_add_input_two_n_d_262), + .O(m13_0_246) + ); + defparam m7_0.INIT = 16'h2996; + LUT4 m7_0 ( + .I0(com_cmm_u_cmm_errman_wtd_cor_add_input_one_d_259), + .I1(com_cmm_u_cmm_errman_wtd_cor_add_input_six_n_d_260), + .I2(com_cmm_u_cmm_errman_wtd_cor_add_input_three_n_d_261), + .I3(com_cmm_u_cmm_errman_wtd_cor_add_input_two_n_d_262), + .O(m7_0_241) + ); + defparam G_425.INIT = 4'h6; + LUT2 G_425 ( + .I0(N_10543), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crc32_d64_feedback[15]), + .O(N_10567) + ); + defparam G_399.INIT = 8'h96; + LUT3 G_399 ( + .I0(N_219), + .I1(N_10374), + .I2(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_7_), + .O(N_10541) + ); + defparam G_421.INIT = 4'h6; + LUT2 G_421 ( + .I0(N_10563_1), + .I1(com_llm_llm_tx_top_tx_dllp_td_25_), + .O(N_10563) + ); + defparam G_355_0.INIT = 8'h96; + LUT3 G_355_0 ( + .I0(N_27376), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d64_22__48), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d64_26__283), + .O(G_355_0_284) + ); + defparam G_431_1.INIT = 8'h96; + LUT3 G_431_1 ( + .I0(G_431_0), + .I1(N_27406), + .I2(N_27417), + .O(G_431_1_285) + ); + defparam G_339_32076.INIT = 8'h96; + LUT3 G_339_32076 ( + .I0(N_27427), + .I1(N_27563), + .I2(N_27564), + .O(G_339_32076_254) + ); + defparam G_138.INIT = 8'h96; + LUT3 G_138 ( + .I0(N_27372), + .I1(N_27419), + .I2(N_27429), + .O(N_10360) + ); + defparam G_58.INIT = 16'h9669; + LUT4 G_58 ( + .I0(N_27410), + .I1(N_27416), + .I2(N_27421), + .I3(N_27664), + .O(N_62) + ); + defparam G_3.INIT = 16'h9669; + LUT4 G_3 ( + .I0(N_27413), + .I1(N_27507), + .I2(N_27526), + .I3(N_27677), + .O(N_10339) + ); + defparam G_20.INIT = 8'h96; + LUT3 G_20 ( + .I0(N_35_1), + .I1(N_27413), + .I2(N_27502), + .O(N_23) + ); + defparam G_32.INIT = 8'h96; + LUT3 G_32 ( + .I0(N_87_1), + .I1(N_27372), + .I2(N_27426), + .O(N_36) + ); + defparam G_71.INIT = 16'h9669; + LUT4 G_71 ( + .I0(N_27415), + .I1(N_27422), + .I2(N_27504), + .I3(N_27664), + .O(N_75) + ); + defparam G_38.INIT = 16'h9669; + LUT4 G_38 ( + .I0(N_27410), + .I1(N_27499), + .I2(N_27500), + .I3(N_27664), + .O(N_42) + ); + defparam G_74.INIT = 8'h69; + LUT3 G_74 ( + .I0(N_27374), + .I1(N_27418), + .I2(N_27664), + .O(N_78) + ); + defparam G_19.INIT = 8'h96; + LUT3 G_19 ( + .I0(N_58_1), + .I1(N_27422), + .I2(N_27502), + .O(N_22) + ); + defparam G_13.INIT = 16'h6996; + LUT4 G_13 ( + .I0(N_27425), + .I1(N_27503), + .I2(N_27665), + .I3(N_27680), + .O(N_15) + ); + defparam G_12.INIT = 8'h69; + LUT3 G_12 ( + .I0(N_10610_1), + .I1(N_27408), + .I2(N_27680), + .O(N_14) + ); + defparam G_11.INIT = 16'h6996; + LUT4 G_11 ( + .I0(N_27415), + .I1(N_27427), + .I2(N_27654), + .I3(N_27680), + .O(N_10345) + ); + defparam G_9.INIT = 8'h69; + LUT3 G_9 ( + .I0(N_35_1), + .I1(N_27504), + .I2(N_27654), + .O(N_10344) + ); + defparam G_6.INIT = 16'h9996; + LUT4 G_6 ( + .I0(N_140_1), + .I1(N_27414), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d64_28__286), + .I3(com_llm_llm_rx_top_llm_rx_tlp_crc_initial_64_51), + .O(N_10342) + ); + defparam G_5.INIT = 16'hAA96; + LUT4 G_5 ( + .I0(N_10348_1), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d64_15__287), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d64_28__286), + .I3(com_llm_llm_rx_top_llm_rx_tlp_crc_initial_64_51), + .O(N_10341) + ); + defparam G_4.INIT = 16'h6669; + LUT4 G_4 ( + .I0(N_10352_1), + .I1(N_27658), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d64_28__286), + .I3(com_llm_llm_rx_top_llm_rx_tlp_crc_initial_64_51), + .O(N_10340) + ); + defparam G_56.INIT = 8'h69; + LUT3 G_56 ( + .I0(N_10484_1), + .I1(N_27412), + .I2(N_27678), + .O(N_60) + ); + defparam G_55.INIT = 8'h96; + LUT3 G_55 ( + .I0(N_10484_1), + .I1(N_27407), + .I2(N_27421), + .O(N_59) + ); + defparam G_54.INIT = 8'h69; + LUT3 G_54 ( + .I0(N_58_1), + .I1(N_27510), + .I2(N_27665), + .O(N_58) + ); + defparam G_53.INIT = 8'h96; + LUT3 G_53 ( + .I0(N_10559_1), + .I1(N_27419), + .I2(N_27510), + .O(N_57) + ); + defparam G_51.INIT = 8'h96; + LUT3 G_51 ( + .I0(N_92_1), + .I1(N_27412), + .I2(N_27499), + .O(N_55) + ); + defparam G_50.INIT = 8'h96; + LUT3 G_50 ( + .I0(N_10574_1), + .I1(N_27414), + .I2(N_27499), + .O(N_54) + ); + defparam G_49.INIT = 16'h9669; + LUT4 G_49 ( + .I0(N_27424), + .I1(N_27425), + .I2(N_27499), + .I3(N_27671), + .O(N_53) + ); + defparam G_48.INIT = 8'h96; + LUT3 G_48 ( + .I0(N_126_1), + .I1(N_27503), + .I2(N_27563), + .O(N_52) + ); + defparam G_47.INIT = 8'h96; + LUT3 G_47 ( + .I0(N_51_1), + .I1(N_27374), + .I2(N_27409), + .O(N_51) + ); + defparam G_36.INIT = 8'h96; + LUT3 G_36 ( + .I0(N_106_1), + .I1(N_27500), + .I2(N_27524), + .O(N_40) + ); + defparam G_33.INIT = 8'h96; + LUT3 G_33 ( + .I0(N_39_1), + .I1(N_27410), + .I2(N_27426), + .O(N_37) + ); + defparam G_30.INIT = 8'h96; + LUT3 G_30 ( + .I0(N_10484_1), + .I1(N_27411), + .I2(N_27442), + .O(N_34) + ); + defparam G_29.INIT = 8'h96; + LUT3 G_29 ( + .I0(N_51_1), + .I1(N_27408), + .I2(N_27442), + .O(N_10354) + ); + defparam G_26.INIT = 8'h69; + LUT3 G_26 ( + .I0(N_10353_1), + .I1(N_27510), + .I2(N_27658), + .O(N_30) + ); + defparam G_156.INIT = 8'h69; + LUT3 G_156 ( + .I0(N_160_1), + .I1(N_27416), + .I2(N_27671), + .O(N_160) + ); + defparam G_121.INIT = 8'h96; + LUT3 G_121 ( + .I0(N_159_1), + .I1(N_27415), + .I2(N_27417), + .O(N_125) + ); + defparam G_108.INIT = 8'h96; + LUT3 G_108 ( + .I0(N_112_1), + .I1(N_27430), + .I2(N_27501), + .O(N_112) + ); + defparam G_103.INIT = 8'h96; + LUT3 G_103 ( + .I0(N_10610_1), + .I1(N_27421), + .I2(N_27423), + .O(N_107) + ); + defparam G_88.INIT = 8'h96; + LUT3 G_88 ( + .I0(N_92_1), + .I1(N_27405), + .I2(N_27422), + .O(N_92) + ); + defparam G_85.INIT = 8'h69; + LUT3 G_85 ( + .I0(N_90_1), + .I1(N_27418), + .I2(N_27671), + .O(N_89) + ); + defparam G_84.INIT = 8'h96; + LUT3 G_84 ( + .I0(N_10610_1), + .I1(N_27406), + .I2(N_27435), + .O(N_88) + ); + defparam G_75.INIT = 8'h96; + LUT3 G_75 ( + .I0(N_124_1), + .I1(N_27412), + .I2(N_27501), + .O(N_79) + ); + defparam G_70.INIT = 8'h69; + LUT3 G_70 ( + .I0(N_140_1), + .I1(N_27504), + .I2(N_27679), + .O(N_74) + ); + defparam G_60.INIT = 8'h96; + LUT3 G_60 ( + .I0(N_160_1), + .I1(N_27407), + .I2(N_27501), + .O(N_64) + ); + defparam G_57.INIT = 8'h96; + LUT3 G_57 ( + .I0(N_10574_1), + .I1(N_27374), + .I2(N_27410), + .O(N_61) + ); + defparam G_250.INIT = 16'h6996; + LUT4 G_250 ( + .I0(N_27404), + .I1(N_27490), + .I2(N_27494), + .I3(com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d64_18__45), + .O(N_10394) + ); + defparam G_249.INIT = 8'h96; + LUT3 G_249 ( + .I0(N_10456_1), + .I1(N_27494), + .I2(N_27497), + .O(N_10393) + ); + defparam G_385.INIT = 8'h69; + LUT3 G_385 ( + .I0(N_27425), + .I1(N_27524), + .I2(N_27665), + .O(N_10527) + ); + defparam G_297_1.INIT = 4'h6; + LUT2_L G_297_1 ( + .I0(N_10445_1), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d64_30__46), + .LO(N_10439_1) + ); + defparam G_251_1.INIT = 4'h6; + LUT2 G_251_1 ( + .I0(N_10461_1), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d64_16__47), + .O(N_10395_1) + ); + defparam G_10.INIT = 8'h96; + LUT3 G_10 ( + .I0(G_10_1_288), + .I1(N_27654), + .I2(N_27655), + .O(N_12) + ); + defparam G_62.INIT = 16'h6996; + LUT4 G_62 ( + .I0(N_27372), + .I1(N_27407), + .I2(N_27417), + .I3(N_27422), + .O(N_66) + ); + defparam G_145.INIT = 16'h6996; + LUT4 G_145 ( + .I0(N_27409), + .I1(N_27423), + .I2(N_27523), + .I3(N_27524), + .O(N_10367) + ); + defparam m16_i_0_a2.INIT = 16'h6E00; + LUT4 m16_i_0_a2 ( + .I0(com_lnk_rd[0]), + .I1(com_lnk_rd[1]), + .I2(com_lnk_rd[3]), + .I3(com_lnk_rd[4]), + .O(N_36576) + ); + defparam G_413.INIT = 8'h96; + LUT3 G_413 ( + .I0(N_27376), + .I1(N_27404), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d64_26__283), + .O(N_10555) + ); + defparam G_370.INIT = 4'h6; + LUT2 G_370 ( + .I0(N_10512_1), + .I1(N_27488), + .O(N_10512) + ); + defparam G_354.INIT = 4'h6; + LUT2 G_354 ( + .I0(N_10496_1), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d64_22__48), + .O(N_10496) + ); + defparam G_342.INIT = 4'h6; + LUT2 G_342 ( + .I0(N_10484_1), + .I1(N_10486_1), + .O(N_10484) + ); + defparam G_314.INIT = 4'h6; + LUT2 G_314 ( + .I0(N_10456_1), + .I1(N_10461_1), + .O(N_10456) + ); + defparam G_313.INIT = 4'h6; + LUT2 G_313 ( + .I0(N_10456_1), + .I1(N_10496_1), + .O(N_10455) + ); + defparam G_311.INIT = 4'h6; + LUT2 G_311 ( + .I0(G_318_1_0_265), + .I1(N_10453_1), + .O(N_10453) + ); + defparam G_310.INIT = 4'h6; + LUT2 G_310 ( + .I0(N_10512_1), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d64_24__269), + .O(N_10452) + ); + defparam G_308.INIT = 8'h96; + LUT3 G_308 ( + .I0(N_10496_1), + .I1(N_27404), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d64_24__269), + .O(N_10450) + ); + defparam G_307.INIT = 4'h6; + LUT2 G_307 ( + .I0(N_10498_1), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d64_29__270), + .O(N_10449) + ); + defparam G_305.INIT = 4'h6; + LUT2 G_305 ( + .I0(N_10447_1), + .I1(N_10453_1), + .O(N_10447) + ); + defparam G_303.INIT = 4'h6; + LUT2 G_303 ( + .I0(N_10445_1), + .I1(N_10554_1), + .O(N_10445) + ); + defparam G_301.INIT = 8'h96; + LUT3 G_301 ( + .I0(N_27404), + .I1(N_27490), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d64_24__269), + .O(N_10443) + ); + defparam G_299.INIT = 8'h96; + LUT3 G_299 ( + .I0(N_10498_1), + .I1(N_27490), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d64_18__45), + .O(N_10441) + ); + defparam G_136.INIT = 4'h6; + LUT2 G_136 ( + .I0(N_140_1), + .I1(N_27418), + .O(N_140) + ); + defparam G_120.INIT = 4'h6; + LUT2 G_120 ( + .I0(N_124_1), + .I1(N_27409), + .O(N_124) + ); + defparam G_109.INIT = 4'h6; + LUT2 G_109 ( + .I0(N_113_1), + .I1(N_27418), + .O(N_113) + ); + defparam G_104.INIT = 4'h6; + LUT2 G_104 ( + .I0(N_113_1), + .I1(N_27421), + .O(N_108) + ); + defparam G_83.INIT = 4'h6; + LUT2 G_83 ( + .I0(N_87_1), + .I1(N_160_1), + .O(N_87) + ); + defparam G_59.INIT = 8'h96; + LUT3 G_59 ( + .I0(N_87_1), + .I1(N_27406), + .I2(N_27410), + .O(N_63) + ); + defparam G_34.INIT = 4'h6; + LUT2 G_34 ( + .I0(N_39_1), + .I1(N_159_1), + .O(N_38) + ); + defparam G_27.INIT = 8'h69; + LUT3 G_27 ( + .I0(N_10353_1), + .I1(N_27503), + .I2(N_27665), + .O(N_10353) + ); + defparam G_24.INIT = 4'h6; + LUT2 G_24 ( + .I0(N_124_1), + .I1(N_10352_1), + .O(N_10351) + ); + defparam G_15.INIT = 8'h69; + LUT3 G_15 ( + .I0(N_10347_1), + .I1(N_27424), + .I2(N_27671), + .O(N_10347) + ); + defparam G_14.INIT = 4'h6; + LUT2 G_14 ( + .I0(N_10347_1), + .I1(N_10353_1), + .O(N_10346) + ); + defparam G_7.INIT = 4'h6; + LUT2 G_7 ( + .I0(N_10_1), + .I1(N_51_1), + .O(N_10343) + ); + defparam G_335.INIT = 8'h96; + LUT3 G_335 ( + .I0(N_10486_1), + .I1(N_27427), + .I2(N_27564), + .O(N_10477) + ); + defparam G_412.INIT = 4'h6; + LUT2 G_412 ( + .I0(N_10554_1), + .I1(N_27376), + .O(N_10554) + ); + defparam G_87.INIT = 16'h6996; + LUT4 G_87 ( + .I0(N_27503), + .I1(N_27526), + .I2(N_27665), + .I3(N_27677), + .O(N_91) + ); + defparam G_1.INIT = 8'h96; + LUT3 G_1 ( + .I0(N_39_1), + .I1(N_27502), + .I2(N_27507), + .O(N_3) + ); + defparam G_31.INIT = 4'h6; + LUT2 G_31 ( + .I0(N_35_1), + .I1(N_126_1), + .O(N_35) + ); + defparam N_3580_m.INIT = 8'h54; + LUT3 N_3580_m ( + .I0(N_3543), + .I1(plm_dfm_deframe1_qwfsm_reg_state_0__59), + .I2(plm_dfm_deframe1_qwfsm_reg_state_1__58), + .O(N_3580_m_289) + ); + defparam m16_i_0_0.INIT = 16'h0F1C; + LUT4 m16_i_0_0 ( + .I0(com_lnk_rd[3]), + .I1(com_lnk_rd[4]), + .I2(com_lnk_rd[5]), + .I3(com_lnk_rd[6]), + .O(m16_i_0_0_266) + ); + defparam G_411.INIT = 8'h96; + LUT3 G_411 ( + .I0(N_115), + .I1(N_10391_1), + .I2(data_in_q[37]), + .O(G_411_290) + ); + defparam G_375.INIT = 8'h96; + LUT3 G_375 ( + .I0(N_114), + .I1(data_in_q[19]), + .I2(data_in_q[20]), + .O(G_375_291) + ); + defparam G_436.INIT = 8'h96; + LUT3 G_436 ( + .I0(N_117), + .I1(data_in_q[15]), + .I2(data_in_q[27]), + .O(G_436_292) + ); + defparam I_5112_i_0_0_o3_0.INIT = 16'h0008; + LUT4 I_5112_i_0_0_o3_0 ( + .I0(I_5112_i_0_0_o3_0_0_293), + .I1(I_5112_i_0_0_o3_0_4_294), + .I2(plm_rx0_lane_num[5]), + .I3(plm_rx0_lane_num[6]), + .O(N_38113_i) + ); + defparam G_459.INIT = 8'h96; + LUT3 G_459 ( + .I0(N_196), + .I1(com_llm_llm_tx_top_tx_dllp_td_30_), + .I2(com_llm_llm_tx_top_tx_dllp_td_35_), + .O(N_10601) + ); + defparam G_420.INIT = 8'h96; + LUT3 G_420 ( + .I0(N_27424), + .I1(N_27655), + .I2(N_27661), + .O(N_10562) + ); + defparam G_456.INIT = 8'h96; + LUT3 G_456 ( + .I0(N_197), + .I1(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_30_), + .I2(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_35_), + .O(N_10598) + ); + defparam G_455.INIT = 8'h96; + LUT3 G_455 ( + .I0(N_198), + .I1(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_3_), + .I2(com_llm_llm_rx_top_rx_data_62_), + .O(N_10597) + ); + defparam G_378.INIT = 8'h96; + LUT3 G_378 ( + .I0(N_67), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[2]), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[3]), + .O(N_10520) + ); + defparam m12_0_0_0_o3.INIT = 8'hE8; + LUT3 m12_0_0_0_o3 ( + .I0(com_tlm_cmmt_err_flow_control), + .I1(com_tlm_cmmt_err_rbuf_overflow), + .I2(com_tlm_cmmt_err_tlp_malformed), + .O(m12_0_0_0_o3_253) + ); + defparam m4_3_0_i_i_a2_0.INIT = 8'h80; + LUT3 m4_3_0_i_i_a2_0 ( + .I0(N_49663), + .I1(N_50505_1), + .I2(com_cmm_u_cmm_dataproducer_req_gnt_code_0__295), + .O(com_cmm_u_cmm_dataproducer_byte_00_1_sqmuxa_1) + ); + defparam G_435.INIT = 16'h6996; + LUT4 G_435 ( + .I0(G_128_296), + .I1(data_in_q[8]), + .I2(data_in_q[16]), + .I3(data_in_q[41]), + .O(G_435_297) + ); + defparam G_418.INIT = 16'h6996; + LUT4 G_418 ( + .I0(G_418_0_298), + .I1(N_199_1), + .I2(N_10560_1), + .I3(data_in_q[29]), + .O(G_418_299) + ); + defparam G_393.INIT = 16'h6996; + LUT4 G_393 ( + .I0(N_208), + .I1(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_4_), + .I2(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_17_), + .I3(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_18_), + .O(N_10535) + ); + defparam G_395.INIT = 16'h6996; + LUT4 G_395 ( + .I0(N_206), + .I1(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_36_), + .I2(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_49_), + .I3(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_50_), + .O(N_10537) + ); + defparam G_466.INIT = 16'h6996; + LUT4 G_466 ( + .I0(N_203), + .I1(N_216_1), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crc32_d64_feedback[3]), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crc32_d64_feedback[10]), + .O(N_10608) + ); + defparam m3_0.INIT = 16'h9669; + LUT4 m3_0 ( + .I0(com_cmm_u_cmm_errman_wtd_cor_add_input_one_d_259), + .I1(com_cmm_u_cmm_errman_wtd_cor_add_input_six_n_d_260), + .I2(com_cmm_u_cmm_errman_wtd_cor_add_input_three_n_d_261), + .I3(com_cmm_u_cmm_errman_wtd_cor_add_input_two_n_d_262), + .O(m3_0_242) + ); + defparam G_421_1.INIT = 16'h6996; + LUT4 G_421_1 ( + .I0(G_421_1_1), + .I1(com_llm_llm_tx_top_tx_dllp_td_32_), + .I2(com_llm_llm_tx_top_tx_dllp_td_43_), + .I3(com_llm_llm_tx_top_tx_dllp_td_45_), + .O(N_10563_1) + ); + defparam G_381.INIT = 4'h6; + LUT2 G_381 ( + .I0(N_184), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crc32_d64_feedback[23]), + .O(N_10523) + ); + defparam G_401.INIT = 16'h6996; + LUT4 G_401 ( + .I0(N_216_1), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crc32_d64_feedback[10]), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crc32_d64_feedback[16]), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crc32_d64_feedback[28]), + .O(N_10543) + ); + defparam G_424.INIT = 4'h6; + LUT2 G_424 ( + .I0(N_67), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[12]), + .O(N_10566) + ); + defparam G_433.INIT = 4'h6; + LUT2 G_433 ( + .I0(N_181), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crc32_d64_feedback[7]), + .O(N_10575) + ); + defparam G_365_0_x4.INIT = 4'h6; + LUT2 G_365_0_x4 ( + .I0(N_247), + .I1(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_55_), + .O(N_27385_i_0) + ); + defparam G_366_0_x4.INIT = 4'h6; + LUT2 G_366_0_x4 ( + .I0(N_245), + .I1(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_23_), + .O(N_27386_i_0) + ); + defparam G_406_1.INIT = 4'h6; + LUT2 G_406_1 ( + .I0(N_10375), + .I1(com_llm_llm_rx_top_rx_data_61_), + .O(N_10548_1) + ); + defparam G_400_1.INIT = 4'h6; + LUT2 G_400_1 ( + .I0(N_178), + .I1(N_217), + .O(N_10542_1) + ); + defparam G_452.INIT = 4'h6; + LUT2 G_452 ( + .I0(N_174), + .I1(com_llm_llm_tx_top_tx_dllp_td_24_), + .O(N_10594) + ); + defparam G_407_1.INIT = 16'h6996; + LUT4 G_407_1 ( + .I0(com_llm_llm_tx_top_tx_dllp_td_29_), + .I1(com_llm_llm_tx_top_tx_dllp_td_34_), + .I2(com_llm_llm_tx_top_tx_dllp_td_52_), + .I3(com_llm_llm_tx_top_tx_dllp_td_55_), + .O(N_10549_1) + ); + defparam G_380_1.INIT = 4'h6; + LUT2 G_380_1 ( + .I0(N_174), + .I1(N_243), + .O(N_10522_1) + ); + defparam G_380_2.INIT = 16'h6996; + LUT4 G_380_2 ( + .I0(com_llm_llm_tx_top_tx_dllp_td_32_), + .I1(com_llm_llm_tx_top_tx_dllp_td_38_), + .I2(com_llm_llm_tx_top_tx_dllp_td_43_), + .I3(com_llm_llm_tx_top_tx_dllp_td_45_), + .O(N_10522_2) + ); + defparam G_371.INIT = 8'h96; + LUT3 G_371 ( + .I0(N_118), + .I1(data_in_q[7]), + .I2(data_in_q[10]), + .O(G_371_300) + ); + defparam G_376.INIT = 4'h6; + LUT2 G_376 ( + .I0(N_130), + .I1(N_10518_1), + .O(G_376_301) + ); + defparam G_382_1.INIT = 4'h6; + LUT2 G_382_1 ( + .I0(N_129), + .I1(data_in_q[16]), + .O(N_10524_1) + ); + defparam G_465.INIT = 4'h6; + LUT2 G_465 ( + .I0(N_129), + .I1(G_186_302), + .O(G_465_303) + ); + defparam G_410.INIT = 4'h6; + LUT2 G_410 ( + .I0(N_117), + .I1(N_154), + .O(G_410_304) + ); + defparam G_374.INIT = 4'h6; + LUT2 G_374 ( + .I0(G_186_302), + .I1(data_in_q[11]), + .O(G_374_305) + ); + defparam G_361.INIT = 4'h6; + LUT2 G_361 ( + .I0(G_142_306), + .I1(data_in_q[38]), + .O(G_361_307) + ); + defparam G_460_0.INIT = 4'h6; + LUT2 G_460_0 ( + .I0(N_27373), + .I1(N_27429), + .O(G_460_0_256) + ); + defparam G_10_1.INIT = 4'h6; + LUT2_L G_10_1 ( + .I0(N_27417), + .I1(N_27442), + .LO(G_10_1_288) + ); + defparam G_318_1_0.INIT = 16'h5A66; + LUT4 G_318_1_0 ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d64_28__286), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_11_), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_43_), + .I3(com_llm_llm_rx_top_llm_rx_tlp_crc_start_high_latch_q_308), + .O(G_318_1_0_265) + ); + defparam m12.INIT = 8'h2B; + LUT3 m12 ( + .I0(com_cmm_u_cmm_errman_wtd_cor_add_input_one_d_259), + .I1(com_cmm_u_cmm_errman_wtd_cor_add_input_six_n_d_260), + .I2(com_cmm_u_cmm_errman_wtd_cor_add_input_two_n_d_262), + .O(m12_264) + ); + defparam G_357_0.INIT = 16'hA599; + LUT4 G_357_0 ( + .I0(N_27666), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_data_q[0]), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_24_), + .I3(com_llm_llm_rx_top_llm_rx_tlp_crc_start_high_latch_309), + .O(G_431_0) + ); + defparam G_427_0.INIT = 8'h56; + LUT3 G_427_0 ( + .I0(N_27432), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d64_7__310), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_initial_64_51), + .O(N_58_1) + ); + defparam m3_3_0.INIT = 8'h14; + LUT3 m3_3_0 ( + .I0(plm_dfm_deframe1_dword_empty), + .I1(plm_dfm_deframe1_dword_sdpstp[0]), + .I2(plm_dfm_deframe1_dword_sdpstp[1]), + .O(N_3543) + ); + defparam G_419_0_m3_0.INIT = 16'hC355; + LUT4 G_419_0_m3_0 ( + .I0(N_27388_i), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_6_), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_22_), + .I3(com_llm_llm_rx_top_llm_rx_tlp_crc_start_high_latch_309), + .O(N_27619) + ); + defparam G_442_0_m3_0.INIT = 16'hC535; + LUT4 G_442_0_m3_0 ( + .I0(N_27390_i), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_6_), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_start_high_latch_309), + .I3(com_llm_llm_rx_top_rx_data_59_), + .O(N_27618) + ); + defparam G_468_1.INIT = 8'h56; + LUT3 G_468_1 ( + .I0(N_27433), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d64_8__311), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_initial_64_51), + .O(N_10610_1) + ); + defparam G_440_1.INIT = 8'h56; + LUT3 G_440_1 ( + .I0(N_27512), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d64_29__270), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_initial_64_51), + .O(N_10582_1) + ); + defparam G_370_1.INIT = 4'h6; + LUT2 G_370_1 ( + .I0(N_27491), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d64_19__49), + .O(N_10512_1) + ); + defparam G_356_1.INIT = 16'h5A66; + LUT4 G_356_1 ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d64_21__312), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_2_), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_34_), + .I3(com_llm_llm_rx_top_llm_rx_tlp_crc_start_high_latch_q_308), + .O(N_10498_1) + ); + defparam G_320_1.INIT = 4'h6; + LUT2 G_320_1 ( + .I0(N_27498), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d64_31__50), + .O(N_10462_1) + ); + defparam G_319_1.INIT = 16'h5A66; + LUT4 G_319_1 ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d64_26__283), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_13_), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_45_), + .I3(com_llm_llm_rx_top_llm_rx_tlp_crc_start_high_latch_q_308), + .O(N_10461_1) + ); + defparam G_314_1.INIT = 16'h5A66; + LUT4 G_314_1 ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d64_17__313), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_6_), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_38_), + .I3(com_llm_llm_rx_top_llm_rx_tlp_crc_start_high_latch_q_308), + .O(N_10456_1) + ); + defparam G_311_1.INIT = 16'h5A66; + LUT4 G_311_1 ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d64_25__314), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_14_), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_46_), + .I3(com_llm_llm_rx_top_llm_rx_tlp_crc_start_high_latch_q_308), + .O(N_10453_1) + ); + defparam G_305_1.INIT = 4'h6; + LUT2 G_305_1 ( + .I0(N_27497), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d64_29__270), + .O(N_10447_1) + ); + defparam G_303_1.INIT = 16'h5A66; + LUT4 G_303_1 ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d64_23__315), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_0_), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_32_), + .I3(com_llm_llm_rx_top_llm_rx_tlp_crc_start_high_latch_q_308), + .O(N_10445_1) + ); + defparam G_156_1.INIT = 8'h56; + LUT3 G_156_1 ( + .I0(N_27514), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d64_31__50), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_initial_64_51), + .O(N_160_1) + ); + defparam G_155_1.INIT = 8'h56; + LUT3 G_155_1 ( + .I0(N_27438), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d64_13__316), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_initial_64_51), + .O(N_159_1) + ); + defparam G_137_1.INIT = 4'h6; + LUT2 G_137_1 ( + .I0(N_27423), + .I1(N_27501), + .O(N_141_1) + ); + defparam G_136_1.INIT = 8'h56; + LUT3 G_136_1 ( + .I0(N_27430), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d64_5__317), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_initial_64_51), + .O(N_140_1) + ); + defparam G_122_1.INIT = 8'h56; + LUT3 G_122_1 ( + .I0(N_27436), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d64_11__318), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_initial_64_51), + .O(N_126_1) + ); + defparam G_120_1.INIT = 8'h56; + LUT3 G_120_1 ( + .I0(N_27439), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d64_14__319), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_initial_64_51), + .O(N_124_1) + ); + defparam G_109_1.INIT = 4'h6; + LUT2 G_109_1 ( + .I0(N_27408), + .I1(N_27409), + .O(N_113_1) + ); + defparam G_108_1.INIT = 4'h6; + LUT2 G_108_1 ( + .I0(N_27411), + .I1(N_27524), + .O(N_112_1) + ); + defparam G_88_1.INIT = 8'h56; + LUT3 G_88_1 ( + .I0(N_27434), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d64_9__320), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_initial_64_51), + .O(N_92_1) + ); + defparam G_86_1.INIT = 4'h6; + LUT2 G_86_1 ( + .I0(N_27406), + .I1(N_27420), + .O(N_90_1) + ); + defparam G_83_1.INIT = 8'h56; + LUT3 G_83_1 ( + .I0(N_27508), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d64_21__312), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_initial_64_51), + .O(N_87_1) + ); + defparam G_47_1.INIT = 8'h56; + LUT3 G_47_1 ( + .I0(N_27506), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d64_19__49), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_initial_64_51), + .O(N_51_1) + ); + defparam G_37_1.INIT = 4'h6; + LUT2 G_37_1 ( + .I0(N_27500), + .I1(N_27523), + .O(N_41_1) + ); + defparam G_35_1.INIT = 8'h56; + LUT3 G_35_1 ( + .I0(N_27527), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d64_25__314), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_initial_64_51), + .O(N_39_1) + ); + defparam G_31_1.INIT = 8'h56; + LUT3 G_31_1 ( + .I0(N_27509), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d64_22__48), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_initial_64_51), + .O(N_35_1) + ); + defparam G_27_1.INIT = 8'h56; + LUT3 G_27_1 ( + .I0(N_27437), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d64_12__321), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_initial_64_51), + .O(N_10353_1) + ); + defparam G_25_1.INIT = 8'h56; + LUT3 G_25_1 ( + .I0(N_27505), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d64_18__45), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_initial_64_51), + .O(N_10352_1) + ); + defparam G_23_1.INIT = 4'h6; + LUT2 G_23_1 ( + .I0(N_27413), + .I1(N_27563), + .O(N_26_1) + ); + defparam G_17_1.INIT = 4'h6; + LUT2 G_17_1 ( + .I0(N_27435), + .I1(N_27510), + .O(N_19_1) + ); + defparam G_16_1.INIT = 16'h5A66; + LUT4 G_16_1 ( + .I0(N_27426), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_data_q[0]), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_24_), + .I3(com_llm_llm_rx_top_llm_rx_tlp_crc_start_high_latch_309), + .O(N_10348_1) + ); + defparam G_8_1.INIT = 8'h56; + LUT3 G_8_1 ( + .I0(N_27441), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d64_24__269), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_initial_64_51), + .O(N_10_1) + ); + defparam G_15_1.INIT = 8'h56; + LUT3 G_15_1 ( + .I0(N_27513), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d64_30__46), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_initial_64_51), + .O(N_10347_1) + ); + defparam G_342_1.INIT = 8'h56; + LUT3 G_342_1 ( + .I0(N_27431), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d64_6__322), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_initial_64_51), + .O(N_10484_1) + ); + defparam G_354_1.INIT = 16'h5A66; + LUT4 G_354_1 ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d64_20__54), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_3_), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_35_), + .I3(com_llm_llm_rx_top_llm_rx_tlp_crc_start_high_latch_q_308), + .O(N_10496_1) + ); + defparam G_415_0_x4_0_x4.INIT = 16'h5A66; + LUT4 G_415_0_x4_0_x4 ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d64_27__323), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_12_), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_44_), + .I3(com_llm_llm_rx_top_llm_rx_tlp_crc_start_high_latch_q_308), + .O(N_10554_1) + ); + defparam G_432_1.INIT = 8'h56; + LUT3 G_432_1 ( + .I0(N_27525), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d64_0__324), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_initial_64_51), + .O(N_10574_1) + ); + defparam G_300_1.INIT = 16'h5A66; + LUT4 G_300_1 ( + .I0(N_27490), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_13_), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_45_), + .I3(com_llm_llm_rx_top_llm_rx_tlp_crc_start_high_latch_q_308), + .O(N_10442_1) + ); + defparam G_405_2.INIT = 16'h6996; + LUT4 G_405_2 ( + .I0(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_25_), + .I1(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_26_), + .I2(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_40_), + .I3(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_47_), + .O(G_405_2_281) + ); + defparam G_463_2.INIT = 16'h6996; + LUT4 G_463_2 ( + .I0(data_in_q[6]), + .I1(data_in_q[46]), + .I2(data_in_q[54]), + .I3(data_in_q[59]), + .O(G_463_2_279) + ); + defparam I_5112_i_0_0_o3_0_4.INIT = 16'h0001; + LUT4 I_5112_i_0_0_o3_0_4 ( + .I0(plm_rx0_lane_num[0]), + .I1(plm_rx0_lane_num[1]), + .I2(plm_rx0_lane_num[2]), + .I3(plm_rx0_lane_num[7]), + .O(I_5112_i_0_0_o3_0_4_294) + ); + defparam G_286.INIT = 8'h96; + LUT3 G_286 ( + .I0(data_in_q[5]), + .I1(data_in_q[32]), + .I2(data_in_q[35]), + .O(G_286_325) + ); + defparam G_295.INIT = 8'h96; + LUT3 G_295 ( + .I0(data_in_q[15]), + .I1(data_in_q[37]), + .I2(data_in_q[46]), + .O(G_295_326) + ); + defparam G_323.INIT = 8'h96; + LUT3 G_323 ( + .I0(N_10558_1), + .I1(plm_scr0_reg_lfsr_one_1__327), + .I2(plm_scr0_reg_lfsr_one_15__328), + .O(G_323_329) + ); + defparam G_324.INIT = 8'h96; + LUT3 G_324 ( + .I0(plm_scr0_reg_lfsr_one_3__330), + .I1(plm_scr0_reg_lfsr_one_13__331), + .I2(plm_scr0_reg_lfsr_one_15__328), + .O(G_324_332) + ); + defparam G_325.INIT = 8'h96; + LUT3 G_325 ( + .I0(N_10519_1), + .I1(plm_des0_reg_lfsr_one_1__333), + .I2(plm_des0_reg_lfsr_one_15__334), + .O(G_325_335) + ); + defparam G_326.INIT = 8'h96; + LUT3 G_326 ( + .I0(plm_des0_reg_lfsr_one_3__336), + .I1(plm_des0_reg_lfsr_one_13__337), + .I2(plm_des0_reg_lfsr_one_15__334), + .O(G_326_338) + ); + defparam G_327.INIT = 8'h96; + LUT3 G_327 ( + .I0(N_10469_1), + .I1(plm_scr0_reg_lfsr_two_13__339), + .I2(plm_scr0_reg_lfsr_two_15__340), + .O(G_327_341) + ); + defparam G_329.INIT = 16'h6996; + LUT4 G_329 ( + .I0(plm_des0_reg_lfsr_two_0__342), + .I1(plm_des0_reg_lfsr_two_11__343), + .I2(plm_des0_reg_lfsr_two_13__344), + .I3(plm_des0_reg_lfsr_two_15__345), + .O(G_329_346) + ); + defparam G_422.INIT = 8'h96; + LUT3 G_422 ( + .I0(data_in_q[10]), + .I1(data_in_q[32]), + .I2(data_in_q[43]), + .O(G_422_347) + ); + defparam G_195.INIT = 8'h96; + LUT3 G_195 ( + .I0(N_10429_1), + .I1(data_in_q[9]), + .I2(data_in_q[29]), + .O(N_200) + ); + defparam G_196.INIT = 16'h6996; + LUT4 G_196 ( + .I0(data_in_q[1]), + .I1(data_in_q[6]), + .I2(data_in_q[29]), + .I3(data_in_q[42]), + .O(N_201) + ); + defparam G_197.INIT = 8'h96; + LUT3 G_197 ( + .I0(N_202_2), + .I1(data_in_q[34]), + .I2(data_in_q[61]), + .O(N_202) + ); + defparam G_204.INIT = 8'h96; + LUT3 G_204 ( + .I0(N_209_1), + .I1(data_in_q[27]), + .I2(data_in_q[39]), + .O(N_209) + ); + defparam G_205.INIT = 8'h96; + LUT3 G_205 ( + .I0(N_210_1), + .I1(data_in_q[25]), + .I2(data_in_q[48]), + .O(N_210) + ); + defparam G_206.INIT = 8'h96; + LUT3 G_206 ( + .I0(N_211_2), + .I1(data_in_q[9]), + .I2(data_in_q[53]), + .O(N_211) + ); + defparam G_207.INIT = 8'h96; + LUT3 G_207 ( + .I0(data_in_q[1]), + .I1(data_in_q[9]), + .I2(data_in_q[17]), + .O(N_212) + ); + defparam G_228.INIT = 8'h96; + LUT3 G_228 ( + .I0(N_234_1), + .I1(data_in_q[5]), + .I2(data_in_q[47]), + .O(N_234) + ); + defparam G_231.INIT = 8'h96; + LUT3 G_231 ( + .I0(N_10391_1), + .I1(data_in_q[0]), + .I2(data_in_q[24]), + .O(N_237) + ); + defparam G_233.INIT = 8'h96; + LUT3 G_233 ( + .I0(N_10518_1), + .I1(data_in_q[27]), + .I2(data_in_q[40]), + .O(N_239) + ); + defparam G_236.INIT = 16'h6996; + LUT4 G_236 ( + .I0(data_in_q[20]), + .I1(data_in_q[22]), + .I2(data_in_q[33]), + .I3(data_in_q[49]), + .O(N_242) + ); + defparam G_255.INIT = 16'h6996; + LUT4 G_255 ( + .I0(data_in_q[0]), + .I1(data_in_q[4]), + .I2(data_in_q[12]), + .I3(data_in_q[41]), + .O(G_255_348) + ); + defparam G_285.INIT = 8'h96; + LUT3 G_285 ( + .I0(data_in_q[24]), + .I1(data_in_q[48]), + .I2(data_in_q[49]), + .O(G_285_349) + ); + defparam G_157.INIT = 8'h96; + LUT3 G_157 ( + .I0(N_10413_1), + .I1(data_in_q[10]), + .I2(data_in_q[62]), + .O(G_157_350) + ); + defparam G_158.INIT = 8'h96; + LUT3 G_158 ( + .I0(N_211_2), + .I1(data_in_q[43]), + .I2(data_in_q[62]), + .O(N_162) + ); + defparam G_159.INIT = 8'h96; + LUT3 G_159 ( + .I0(N_163_1), + .I1(data_in_q[29]), + .I2(data_in_q[62]), + .O(N_163) + ); + defparam G_161.INIT = 8'h96; + LUT3 G_161 ( + .I0(N_165_1), + .I1(data_in_q[0]), + .I2(data_in_q[39]), + .O(N_165) + ); + defparam G_165.INIT = 8'h96; + LUT3 G_165 ( + .I0(N_202_2), + .I1(data_in_q[19]), + .I2(data_in_q[57]), + .O(N_169) + ); + defparam G_166.INIT = 16'h6996; + LUT4 G_166 ( + .I0(data_in_q[1]), + .I1(data_in_q[43]), + .I2(data_in_q[54]), + .I3(data_in_q[57]), + .O(N_170) + ); + defparam G_168.INIT = 16'h6996; + LUT4 G_168 ( + .I0(data_in_q[2]), + .I1(data_in_q[6]), + .I2(data_in_q[29]), + .I3(data_in_q[43]), + .O(G_168_351) + ); + defparam G_169.INIT = 8'h96; + LUT3 G_169 ( + .I0(N_173_1), + .I1(data_in_q[40]), + .I2(data_in_q[63]), + .O(N_173) + ); + defparam G_185.INIT = 16'h6996; + LUT4 G_185 ( + .I0(data_in_q[7]), + .I1(data_in_q[10]), + .I2(data_in_q[19]), + .I3(data_in_q[31]), + .O(N_190) + ); + defparam G_127.INIT = 16'h6996; + LUT4 G_127 ( + .I0(data_in_q[1]), + .I1(data_in_q[32]), + .I2(data_in_q[43]), + .I3(data_in_q[55]), + .O(N_131) + ); + defparam G_129.INIT = 8'h96; + LUT3 G_129 ( + .I0(N_10357_1), + .I1(data_in_q[48]), + .I2(data_in_q[60]), + .O(G_129_274) + ); + defparam G_131.INIT = 8'h96; + LUT3 G_131 ( + .I0(N_10358_1), + .I1(data_in_q[2]), + .I2(data_in_q[60]), + .O(N_135) + ); + defparam G_132.INIT = 8'h96; + LUT3 G_132 ( + .I0(N_10366_1), + .I1(data_in_q[52]), + .I2(data_in_q[53]), + .O(N_136) + ); + defparam G_133.INIT = 8'h96; + LUT3 G_133 ( + .I0(N_10358_1), + .I1(data_in_q[31]), + .I2(data_in_q[49]), + .O(G_133_352) + ); + defparam G_134.INIT = 8'h96; + LUT3 G_134 ( + .I0(N_10369_1), + .I1(data_in_q[36]), + .I2(data_in_q[52]), + .O(G_134_353) + ); + defparam G_144.INIT = 8'h96; + LUT3 G_144 ( + .I0(N_10366_1), + .I1(data_in_q[8]), + .I2(data_in_q[40]), + .O(G_144_354) + ); + defparam G_149.INIT = 8'h96; + LUT3 G_149 ( + .I0(N_10369_1), + .I1(data_in_q[24]), + .I2(data_in_q[39]), + .O(G_149_276) + ); + defparam G_150.INIT = 8'h96; + LUT3 G_150 ( + .I0(N_155_1), + .I1(data_in_q[13]), + .I2(data_in_q[57]), + .O(N_154) + ); + defparam G_151.INIT = 8'h96; + LUT3 G_151 ( + .I0(N_155_1), + .I1(data_in_q[28]), + .I2(data_in_q[53]), + .O(N_155) + ); + defparam G_113.INIT = 8'h96; + LUT3 G_113 ( + .I0(N_117_1), + .I1(data_in_q[3]), + .I2(data_in_q[50]), + .O(N_117) + ); + defparam G_114.INIT = 16'h6996; + LUT4 G_114 ( + .I0(data_in_q[21]), + .I1(data_in_q[50]), + .I2(data_in_q[61]), + .I3(data_in_q[63]), + .O(N_118) + ); + defparam I_5047_0_a2_0_a2_0_a4.INIT = 8'h40; + LUT3 I_5047_0_a2_0_a2_0_a4 ( + .I0(plm_fsm_pc_counter0_reg_rx_expired_355), + .I1(plm_fsm_reg_state_2__356), + .I2(plm_rx0_ts2_c), + .O(N_38578) + ); + defparam I_5137_0_a2_0_a2_0_a4.INIT = 8'h20; + LUT3 I_5137_0_a2_0_a2_0_a4 ( + .I0(plm_fsm_reg_state_16__357), + .I1(plm_fsm_ri_counter0_reg_rx_expired_358), + .I2(plm_rx0_idl_c), + .O(I_5137_0_a2_0_a2_0_a4_27) + ); + defparam I_5072_0_a2_0_a2_0_a4.INIT = 8'h40; + LUT3 I_5072_0_a2_0_a2_0_a4 ( + .I0(plm_fsm_ci_counter0_reg_rx_expired_359), + .I1(plm_fsm_reg_state_11__360), + .I2(plm_rx0_idl_c), + .O(I_5072_0_a2_0_a2_0_a4_25) + ); + defparam G_260.INIT = 16'h6996; + LUT4 G_260 ( + .I0(com_llm_llm_tx_top_tx_dllp_td_26_), + .I1(com_llm_llm_tx_top_tx_dllp_td_33_), + .I2(com_llm_llm_tx_top_tx_dllp_td_38_), + .I3(com_llm_llm_tx_top_tx_dllp_td_53_), + .O(N_10402) + ); + defparam G_262.INIT = 8'h96; + LUT3 G_262 ( + .I0(com_llm_llm_tx_top_tx_dllp_td_27_), + .I1(com_llm_llm_tx_top_tx_dllp_td_41_), + .I2(com_llm_llm_tx_top_tx_dllp_td_53_), + .O(N_10404) + ); + defparam G_278.INIT = 16'h6996; + LUT4 G_278 ( + .I0(com_llm_llm_tx_top_tx_dllp_td_33_), + .I1(com_llm_llm_tx_top_tx_dllp_td_41_), + .I2(com_llm_llm_tx_top_tx_dllp_td_48_), + .I3(com_llm_llm_tx_top_tx_dllp_td_49_), + .O(N_10420) + ); + defparam G_273.INIT = 8'h96; + LUT3 G_273 ( + .I0(com_llm_llm_tx_top_tx_dllp_td_30_), + .I1(com_llm_llm_tx_top_tx_dllp_td_32_), + .I2(com_llm_llm_tx_top_tx_dllp_td_48_), + .O(N_10415) + ); + defparam G_252.INIT = 8'h96; + LUT3 G_252 ( + .I0(com_llm_llm_tx_top_tx_dllp_td_35_), + .I1(com_llm_llm_tx_top_tx_dllp_td_42_), + .I2(com_llm_llm_tx_top_tx_dllp_td_53_), + .O(N_258) + ); + defparam G_246.INIT = 8'h96; + LUT3 G_246 ( + .I0(com_llm_llm_tx_top_tx_dllp_td_32_), + .I1(com_llm_llm_tx_top_tx_dllp_td_41_), + .I2(com_llm_llm_tx_top_tx_dllp_td_55_), + .O(N_252) + ); + defparam G_237.INIT = 8'h96; + LUT3 G_237 ( + .I0(com_llm_llm_tx_top_tx_dllp_td_24_), + .I1(com_llm_llm_tx_top_tx_dllp_td_34_), + .I2(com_llm_llm_tx_top_tx_dllp_td_40_), + .O(N_243) + ); + defparam G_227.INIT = 8'h96; + LUT3 G_227 ( + .I0(N_10432_1), + .I1(com_llm_llm_tx_top_tx_dllp_td_39_), + .I2(com_llm_llm_tx_top_tx_dllp_td_54_), + .O(N_10388) + ); + defparam G_191.INIT = 8'h96; + LUT3 G_191 ( + .I0(com_llm_llm_tx_top_tx_dllp_td_40_), + .I1(com_llm_llm_tx_top_tx_dllp_td_43_), + .I2(com_llm_llm_tx_top_tx_dllp_td_48_), + .O(N_196) + ); + defparam G_170.INIT = 8'h96; + LUT3 G_170 ( + .I0(com_llm_llm_tx_top_tx_dllp_td_44_), + .I1(com_llm_llm_tx_top_tx_dllp_td_52_), + .I2(com_llm_llm_tx_top_tx_dllp_td_54_), + .O(N_174) + ); + defparam G_264.INIT = 8'h96; + LUT3 G_264 ( + .I0(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_9_), + .I1(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_21_), + .I2(com_llm_llm_rx_top_rx_data_59_), + .O(N_10406) + ); + defparam G_316.INIT = 8'h96; + LUT3 G_316 ( + .I0(N_27394_i_0), + .I1(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_7_), + .I2(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_17_), + .O(N_10458) + ); + defparam G_241.INIT = 8'h96; + LUT3 G_241 ( + .I0(N_247_1), + .I1(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_34_), + .I2(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_40_), + .O(N_247) + ); + defparam G_239.INIT = 16'h6996; + LUT4 G_239 ( + .I0(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_2_), + .I1(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_4_), + .I2(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_8_), + .I3(com_llm_llm_rx_top_rx_data_56_), + .O(N_245) + ); + defparam G_226.INIT = 16'h6996; + LUT4 G_226 ( + .I0(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_1_), + .I1(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_3_), + .I2(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_7_), + .I3(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_22_), + .O(N_10387) + ); + defparam G_225.INIT = 16'h6996; + LUT4 G_225 ( + .I0(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_33_), + .I1(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_35_), + .I2(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_39_), + .I3(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_54_), + .O(N_10386) + ); + defparam G_224.INIT = 16'h6996; + LUT4 G_224 ( + .I0(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_38_), + .I1(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_46_), + .I2(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_50_), + .I3(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_54_), + .O(N_10385) + ); + defparam G_222.INIT = 8'h96; + LUT3 G_222 ( + .I0(N_228_1), + .I1(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_18_), + .I2(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_22_), + .O(N_228) + ); + defparam G_203.INIT = 8'h96; + LUT3 G_203 ( + .I0(N_208_1), + .I1(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_10_), + .I2(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_12_), + .O(N_208) + ); + defparam G_201.INIT = 16'h6996; + LUT4 G_201 ( + .I0(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_42_), + .I1(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_44_), + .I2(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_45_), + .I3(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_53_), + .O(N_206) + ); + defparam G_279.INIT = 16'h6996; + LUT4 G_279 ( + .I0(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_33_), + .I1(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_41_), + .I2(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_48_), + .I3(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_49_), + .O(N_10421) + ); + defparam G_275.INIT = 8'h96; + LUT3 G_275 ( + .I0(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_30_), + .I1(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_32_), + .I2(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_48_), + .O(N_10417) + ); + defparam G_274.INIT = 8'h96; + LUT3 G_274 ( + .I0(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_0_), + .I1(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_16_), + .I2(com_llm_llm_rx_top_rx_data_62_), + .O(N_10416) + ); + defparam G_263.INIT = 8'h96; + LUT3 G_263 ( + .I0(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_27_), + .I1(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_41_), + .I2(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_53_), + .O(N_10405) + ); + defparam G_259.INIT = 8'h96; + LUT3 G_259 ( + .I0(N_10401_1), + .I1(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_1_), + .I2(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_21_), + .O(N_10401) + ); + defparam G_258.INIT = 16'h6996; + LUT4 G_258 ( + .I0(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_26_), + .I1(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_33_), + .I2(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_38_), + .I3(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_53_), + .O(N_10400) + ); + defparam G_244.INIT = 8'h96; + LUT3 G_244 ( + .I0(N_10392_1), + .I1(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_0_), + .I2(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_23_), + .O(N_10392) + ); + defparam G_243.INIT = 8'h96; + LUT3 G_243 ( + .I0(N_249_1), + .I1(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_15_), + .I2(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_23_), + .O(N_249) + ); + defparam G_317.INIT = 8'h96; + LUT3 G_317 ( + .I0(N_27395_i_0), + .I1(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_39_), + .I2(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_49_), + .O(N_10459) + ); + defparam G_289.INIT = 16'h6996; + LUT4 G_289 ( + .I0(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_25_), + .I1(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_33_), + .I2(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_35_), + .I3(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_50_), + .O(N_10431) + ); + defparam G_288.INIT = 16'h6996; + LUT4 G_288 ( + .I0(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_1_), + .I1(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_3_), + .I2(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_18_), + .I3(com_llm_llm_rx_top_rx_data_57_), + .O(N_10430) + ); + defparam G_280.INIT = 8'h96; + LUT3 G_280 ( + .I0(N_10422_1), + .I1(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_1_), + .I2(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_16_), + .O(N_10422) + ); + defparam G_78.INIT = 16'h6996; + LUT4 G_78 ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[7]), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[13]), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[17]), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[27]), + .O(N_82) + ); + defparam G_77.INIT = 8'h96; + LUT3 G_77 ( + .I0(N_81_1), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[17]), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[26]), + .O(N_81) + ); + defparam G_68.INIT = 8'h96; + LUT3 G_68 ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[2]), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[26]), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[31]), + .O(N_72) + ); + defparam G_67.INIT = 16'h6996; + LUT4 G_67 ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[18]), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[21]), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[30]), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[31]), + .O(N_71) + ); + defparam G_66.INIT = 16'h6996; + LUT4 G_66 ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[3]), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[10]), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[13]), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[31]), + .O(N_70) + ); + defparam G_65.INIT = 16'h6996; + LUT4 G_65 ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[6]), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[9]), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[22]), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[31]), + .O(N_69) + ); + defparam G_63.INIT = 16'h6996; + LUT4 G_63 ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[9]), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[15]), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[28]), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[31]), + .O(N_67) + ); + defparam G_45.INIT = 8'h96; + LUT3 G_45 ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[23]), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[26]), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[30]), + .O(N_49) + ); + defparam G_44.INIT = 16'h6996; + LUT4 G_44 ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[4]), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[8]), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[10]), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[23]), + .O(N_48) + ); + defparam G_43.INIT = 16'h6996; + LUT4 G_43 ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[0]), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[10]), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[20]), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[23]), + .O(N_47) + ); + defparam G_41.INIT = 16'h6996; + LUT4 G_41 ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[17]), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[22]), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[23]), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[29]), + .O(N_45) + ); + defparam G_40.INIT = 16'h6996; + LUT4 G_40 ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[19]), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[23]), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[24]), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[31]), + .O(N_44) + ); + defparam G_162.INIT = 8'h96; + LUT3 G_162 ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[5]), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[14]), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[27]), + .O(N_166) + ); + defparam G_135.INIT = 16'h6996; + LUT4 G_135 ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[6]), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[14]), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[28]), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[30]), + .O(N_139) + ); + defparam G_115.INIT = 16'h6996; + LUT4 G_115 ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[6]), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[13]), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[18]), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[26]), + .O(N_119) + ); + defparam G_99.INIT = 16'h6996; + LUT4 G_99 ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[7]), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[16]), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[26]), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[27]), + .O(N_103) + ); + defparam G_94.INIT = 16'h6996; + LUT4 G_94 ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[8]), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[10]), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[11]), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[24]), + .O(N_98) + ); + defparam G_93.INIT = 16'h6996; + LUT4 G_93 ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[4]), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[13]), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[24]), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[25]), + .O(N_97) + ); + defparam G_92.INIT = 8'h96; + LUT3 G_92 ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[16]), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[22]), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[26]), + .O(N_10355) + ); + defparam G_90.INIT = 16'h6996; + LUT4 G_90 ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[6]), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[7]), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[12]), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[22]), + .O(N_94) + ); + defparam G_81.INIT = 16'h6996; + LUT4 G_81 ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[17]), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[20]), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[21]), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[27]), + .O(N_85) + ); + defparam G_79.INIT = 16'h6996; + LUT4 G_79 ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[0]), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[8]), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[11]), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[17]), + .O(N_83) + ); + defparam G_216.INIT = 8'h96; + LUT3 G_216 ( + .I0(N_10408_1), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crc32_d64_feedback[9]), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crc32_d64_feedback[29]), + .O(N_221) + ); + defparam G_215.INIT = 8'h96; + LUT3 G_215 ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crc32_d64_feedback[2]), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crc32_d64_feedback[18]), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crc32_d64_feedback[21]), + .O(N_220) + ); + defparam G_210.INIT = 8'h96; + LUT3 G_210 ( + .I0(N_10418_1), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crc32_d64_feedback[23]), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crc32_d64_feedback[29]), + .O(N_215) + ); + defparam G_199.INIT = 16'h6996; + LUT4 G_199 ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crc32_d64_feedback[13]), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crc32_d64_feedback[20]), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crc32_d64_feedback[24]), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crc32_d64_feedback[28]), + .O(N_204) + ); + defparam G_198.INIT = 16'h6996; + LUT4 G_198 ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crc32_d64_feedback[4]), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crc32_d64_feedback[7]), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crc32_d64_feedback[24]), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crc32_d64_feedback[28]), + .O(N_203) + ); + defparam G_182.INIT = 16'h6996; + LUT4 G_182 ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crc32_d64_feedback[19]), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crc32_d64_feedback[21]), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crc32_d64_feedback[24]), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crc32_d64_feedback[31]), + .O(N_187) + ); + defparam G_181.INIT = 8'h96; + LUT3 G_181 ( + .I0(N_10377_1), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crc32_d64_feedback[9]), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crc32_d64_feedback[23]), + .O(N_10377) + ); + defparam G_180.INIT = 16'h6996; + LUT4 G_180 ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crc32_d64_feedback[3]), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crc32_d64_feedback[19]), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crc32_d64_feedback[20]), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crc32_d64_feedback[21]), + .O(N_185) + ); + defparam G_179.INIT = 8'h96; + LUT3 G_179 ( + .I0(N_10377_1), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crc32_d64_feedback[11]), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crc32_d64_feedback[25]), + .O(N_184) + ); + defparam G_178.INIT = 16'h6996; + LUT4 G_178 ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crc32_d64_feedback[8]), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crc32_d64_feedback[17]), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crc32_d64_feedback[24]), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crc32_d64_feedback[29]), + .O(N_10376) + ); + defparam G_177.INIT = 16'h6996; + LUT4 G_177 ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crc32_d64_feedback[15]), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crc32_d64_feedback[17]), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crc32_d64_feedback[18]), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crc32_d64_feedback[27]), + .O(N_182) + ); + defparam G_384.INIT = 8'h96; + LUT3 G_384 ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crc32_d64_feedback[0]), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crc32_d64_feedback[11]), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crc32_d64_feedback[13]), + .O(N_10526) + ); + defparam G_312.INIT = 8'h96; + LUT3 G_312 ( + .I0(N_10454_1), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crc32_d64_feedback[5]), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crc32_d64_feedback[15]), + .O(N_10454) + ); + defparam G_283.INIT = 8'h96; + LUT3 G_283 ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crc32_d64_feedback[1]), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crc32_d64_feedback[9]), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crc32_d64_feedback[14]), + .O(N_10425) + ); + defparam G_276.INIT = 8'h96; + LUT3 G_276 ( + .I0(N_10418_1), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crc32_d64_feedback[21]), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crc32_d64_feedback[22]), + .O(N_10418) + ); + defparam G_270.INIT = 8'h96; + LUT3 G_270 ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crc32_d64_feedback[5]), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crc32_d64_feedback[28]), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crc32_d64_feedback[31]), + .O(N_10412) + ); + defparam G_267.INIT = 8'h96; + LUT3 G_267 ( + .I0(N_10411_1), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crc32_d64_feedback[12]), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crc32_d64_feedback[26]), + .O(N_10409) + ); + defparam G_266.INIT = 8'h96; + LUT3 G_266 ( + .I0(N_10408_1), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crc32_d64_feedback[28]), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crc32_d64_feedback[30]), + .O(N_10408) + ); + defparam G_265.INIT = 16'h6996; + LUT4 G_265 ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crc32_d64_feedback[1]), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crc32_d64_feedback[5]), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crc32_d64_feedback[26]), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crc32_d64_feedback[30]), + .O(N_10407) + ); + defparam G_261.INIT = 8'h96; + LUT3 G_261 ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crc32_d64_feedback[6]), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crc32_d64_feedback[8]), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crc32_d64_feedback[22]), + .O(N_10403) + ); + defparam m12_0_0_0_o3_0.INIT = 8'h80; + LUT3 m12_0_0_0_o3_0 ( + .I0(com_tlm_cmmt_err_flow_control), + .I1(com_tlm_cmmt_err_rbuf_overflow), + .I2(com_tlm_cmmt_err_tlp_malformed), + .O(N_48961_i) + ); + defparam G_89.INIT = 16'h6996; + LUT4 G_89 ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[15]), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[21]), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[22]), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[28]), + .O(N_93) + ); + defparam G_91.INIT = 8'h96; + LUT3 G_91 ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[18]), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[21]), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[22]), + .O(N_95) + ); + defparam G_364.INIT = 16'h6996; + LUT4 G_364 ( + .I0(data_in_q[21]), + .I1(data_in_q[26]), + .I2(data_in_q[34]), + .I3(data_in_q[50]), + .O(G_364_361) + ); + defparam G_234.INIT = 16'h6996; + LUT4 G_234 ( + .I0(data_in_q[32]), + .I1(data_in_q[37]), + .I2(data_in_q[40]), + .I3(data_in_q[45]), + .O(N_240) + ); + defparam G_189.INIT = 16'h6996; + LUT4 G_189 ( + .I0(data_in_q[7]), + .I1(data_in_q[27]), + .I2(data_in_q[44]), + .I3(data_in_q[63]), + .O(N_194) + ); + defparam G_188.INIT = 16'h6996; + LUT4 G_188 ( + .I0(data_in_q[5]), + .I1(data_in_q[7]), + .I2(data_in_q[21]), + .I3(data_in_q[45]), + .O(G_188_362) + ); + defparam G_186.INIT = 16'h6996; + LUT4 G_186 ( + .I0(data_in_q[16]), + .I1(data_in_q[35]), + .I2(data_in_q[38]), + .I3(data_in_q[59]), + .O(G_186_302) + ); + defparam G_184.INIT = 16'h6996; + LUT4 G_184 ( + .I0(data_in_q[8]), + .I1(data_in_q[11]), + .I2(data_in_q[31]), + .I3(data_in_q[46]), + .O(N_189) + ); + defparam G_167.INIT = 16'h6996; + LUT4 G_167 ( + .I0(data_in_q[2]), + .I1(data_in_q[14]), + .I2(data_in_q[32]), + .I3(data_in_q[39]), + .O(G_167_363) + ); + defparam G_164.INIT = 16'h6996; + LUT4 G_164 ( + .I0(data_in_q[30]), + .I1(data_in_q[44]), + .I2(data_in_q[57]), + .I3(data_in_q[59]), + .O(N_168) + ); + defparam G_160.INIT = 16'h6996; + LUT4 G_160 ( + .I0(data_in_q[3]), + .I1(data_in_q[8]), + .I2(data_in_q[15]), + .I3(data_in_q[33]), + .O(N_164) + ); + defparam G_154.INIT = 16'h6996; + LUT4 G_154 ( + .I0(data_in_q[27]), + .I1(data_in_q[28]), + .I2(data_in_q[30]), + .I3(data_in_q[35]), + .O(N_158) + ); + defparam G_153.INIT = 16'h6996; + LUT4 G_153 ( + .I0(data_in_q[28]), + .I1(data_in_q[40]), + .I2(data_in_q[41]), + .I3(data_in_q[44]), + .O(N_157) + ); + defparam G_143.INIT = 16'h6996; + LUT4 G_143 ( + .I0(data_in_q[13]), + .I1(data_in_q[24]), + .I2(data_in_q[37]), + .I3(data_in_q[51]), + .O(G_143_364) + ); + defparam G_142.INIT = 16'h6996; + LUT4 G_142 ( + .I0(data_in_q[4]), + .I1(data_in_q[12]), + .I2(data_in_q[33]), + .I3(data_in_q[51]), + .O(G_142_306) + ); + defparam G_128.INIT = 16'h6996; + LUT4 G_128 ( + .I0(data_in_q[23]), + .I1(data_in_q[28]), + .I2(data_in_q[52]), + .I3(data_in_q[60]), + .O(G_128_296) + ); + defparam G_126.INIT = 16'h6996; + LUT4 G_126 ( + .I0(data_in_q[4]), + .I1(data_in_q[20]), + .I2(data_in_q[54]), + .I3(data_in_q[55]), + .O(N_130) + ); + defparam G_125.INIT = 16'h6996; + LUT4 G_125 ( + .I0(data_in_q[9]), + .I1(data_in_q[26]), + .I2(data_in_q[31]), + .I3(data_in_q[55]), + .O(N_129) + ); + defparam G_112.INIT = 16'h6996; + LUT4 G_112 ( + .I0(data_in_q[14]), + .I1(data_in_q[56]), + .I2(data_in_q[58]), + .I3(data_in_q[59]), + .O(N_116) + ); + defparam G_111.INIT = 16'h6996; + LUT4 G_111 ( + .I0(data_in_q[2]), + .I1(data_in_q[51]), + .I2(data_in_q[56]), + .I3(data_in_q[57]), + .O(N_115) + ); + defparam G_110.INIT = 16'h6996; + LUT4 G_110 ( + .I0(data_in_q[50]), + .I1(data_in_q[56]), + .I2(data_in_q[60]), + .I3(data_in_q[62]), + .O(N_114) + ); + defparam G_202.INIT = 16'h6996; + LUT4 G_202 ( + .I0(com_llm_llm_tx_top_tx_dllp_td_42_), + .I1(com_llm_llm_tx_top_tx_dllp_td_44_), + .I2(com_llm_llm_tx_top_tx_dllp_td_45_), + .I3(com_llm_llm_tx_top_tx_dllp_td_53_), + .O(N_207) + ); + defparam G_172.INIT = 16'h6996; + LUT4 G_172 ( + .I0(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_12_), + .I1(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_19_), + .I2(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_20_), + .I3(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_22_), + .O(N_10374) + ); + defparam G_173.INIT = 16'h6996; + LUT4 G_173 ( + .I0(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_2_), + .I1(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_5_), + .I2(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_20_), + .I3(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_23_), + .O(N_10375) + ); + defparam G_174.INIT = 16'h6996; + LUT4 G_174 ( + .I0(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_44_), + .I1(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_51_), + .I2(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_52_), + .I3(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_54_), + .O(N_178) + ); + defparam G_175.INIT = 16'h6996; + LUT4 G_175 ( + .I0(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_34_), + .I1(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_37_), + .I2(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_52_), + .I3(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_55_), + .O(N_179) + ); + defparam G_192.INIT = 16'h6996; + LUT4 G_192 ( + .I0(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_40_), + .I1(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_43_), + .I2(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_48_), + .I3(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_51_), + .O(N_197) + ); + defparam G_193.INIT = 16'h6996; + LUT4 G_193 ( + .I0(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_8_), + .I1(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_11_), + .I2(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_16_), + .I3(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_19_), + .O(N_198) + ); + defparam G_212.INIT = 16'h6996; + LUT4 G_212 ( + .I0(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_32_), + .I1(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_43_), + .I2(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_45_), + .I3(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_46_), + .O(N_217) + ); + defparam G_214.INIT = 16'h6996; + LUT4 G_214 ( + .I0(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_0_), + .I1(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_11_), + .I2(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_13_), + .I3(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_14_), + .O(N_219) + ); + defparam G_253.INIT = 16'h6996; + LUT4 G_253 ( + .I0(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_35_), + .I1(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_42_), + .I2(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_50_), + .I3(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_53_), + .O(N_259) + ); + defparam G_254.INIT = 16'h6996; + LUT4 G_254 ( + .I0(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_3_), + .I1(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_10_), + .I2(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_18_), + .I3(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_21_), + .O(N_10396) + ); + defparam G_95.INIT = 16'h6996; + LUT4 G_95 ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[3]), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[9]), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[11]), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[24]), + .O(N_99) + ); + defparam G_106.INIT = 16'h6996; + LUT4 G_106 ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[7]), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[11]), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[20]), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[29]), + .O(N_110) + ); + defparam G_183.INIT = 16'h6996; + LUT4 G_183 ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crc32_d64_feedback[12]), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crc32_d64_feedback[16]), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crc32_d64_feedback[19]), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crc32_d64_feedback[25]), + .O(N_10378) + ); + defparam G_200.INIT = 16'h6996; + LUT4 G_200 ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crc32_d64_feedback[16]), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crc32_d64_feedback[24]), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crc32_d64_feedback[26]), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crc32_d64_feedback[27]), + .O(N_205) + ); + defparam G_208.INIT = 16'h6996; + LUT4 G_208 ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crc32_d64_feedback[1]), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crc32_d64_feedback[8]), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crc32_d64_feedback[20]), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crc32_d64_feedback[27]), + .O(N_213) + ); + defparam G_217.INIT = 16'h6996; + LUT4 G_217 ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crc32_d64_feedback[10]), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crc32_d64_feedback[14]), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crc32_d64_feedback[29]), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crc32_d64_feedback[31]), + .O(N_222) + ); + defparam G_268.INIT = 16'h6996; + LUT4 G_268 ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crc32_d64_feedback[6]), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crc32_d64_feedback[12]), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crc32_d64_feedback[14]), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crc32_d64_feedback[28]), + .O(N_10410) + ); + defparam G_352.INIT = 16'h6996; + LUT4 G_352 ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[2]), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[8]), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[19]), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[25]), + .O(N_10494) + ); + defparam G_448.INIT = 8'h96; + LUT3 G_448 ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crc32_d64_feedback[2]), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crc32_d64_feedback[3]), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crc32_d64_feedback[6]), + .O(N_10590) + ); + defparam G_462.INIT = 8'h96; + LUT3 G_462 ( + .I0(N_102), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[18]), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[30]), + .O(N_10604) + ); + defparam G_291.INIT = 8'h96; + LUT3 G_291 ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crc32_d64_feedback[5]), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crc32_d64_feedback[7]), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crc32_d64_feedback[26]), + .O(N_10433) + ); + defparam G_282.INIT = 8'h96; + LUT3 G_282 ( + .I0(N_10424_1), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crc32_d64_feedback[11]), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crc32_d64_feedback[15]), + .O(N_10424) + ); + defparam G_269.INIT = 8'h96; + LUT3 G_269 ( + .I0(N_10411_1), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crc32_d64_feedback[12]), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crc32_d64_feedback[22]), + .O(N_10411) + ); + defparam G_218.INIT = 8'h96; + LUT3 G_218 ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crc32_d64_feedback[8]), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crc32_d64_feedback[29]), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crc32_d64_feedback[31]), + .O(N_224) + ); + defparam G_176.INIT = 16'h6996; + LUT4 G_176 ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crc32_d64_feedback[12]), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crc32_d64_feedback[17]), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crc32_d64_feedback[22]), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crc32_d64_feedback[27]), + .O(N_181) + ); + defparam G_148.INIT = 8'h96; + LUT3 G_148 ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[1]), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[21]), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[30]), + .O(N_152) + ); + defparam G_147.INIT = 16'h6996; + LUT4 G_147 ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[8]), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[11]), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[14]), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[30]), + .O(N_151) + ); + defparam G_139.INIT = 8'h96; + LUT3 G_139 ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[5]), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[25]), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[29]), + .O(N_10361) + ); + defparam G_107.INIT = 4'h6; + LUT2 G_107 ( + .I0(N_111_1), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[21]), + .O(N_111) + ); + defparam G_105.INIT = 16'h6996; + LUT4 G_105 ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[0]), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[1]), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[4]), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[20]), + .O(N_109) + ); + defparam G_100.INIT = 16'h6996; + LUT4 G_100 ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[16]), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[25]), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[27]), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[28]), + .O(N_104) + ); + defparam G_82.INIT = 8'h96; + LUT3 G_82 ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[17]), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[25]), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[30]), + .O(N_86) + ); + defparam G_80.INIT = 16'h6996; + LUT4 G_80 ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[5]), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[12]), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[17]), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[25]), + .O(N_84) + ); + defparam G_76.INIT = 8'h96; + LUT3 G_76 ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[17]), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[25]), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[29]), + .O(N_80) + ); + defparam G_69.INIT = 8'h96; + LUT3 G_69 ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[24]), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[27]), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[31]), + .O(N_73) + ); + defparam G_64.INIT = 8'h96; + LUT3 G_64 ( + .I0(N_111_1), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[16]), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[31]), + .O(N_68) + ); + defparam G_42.INIT = 16'h6996; + LUT4 G_42 ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[5]), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[8]), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[12]), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[23]), + .O(N_46) + ); + defparam G_39.INIT = 16'h6996; + LUT4 G_39 ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[18]), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[22]), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[23]), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[30]), + .O(N_43) + ); + defparam G_315.INIT = 8'h96; + LUT3 G_315 ( + .I0(N_10457_1), + .I1(com_llm_llm_tx_top_tx_dllp_td_39_), + .I2(com_llm_llm_tx_top_tx_dllp_td_49_), + .O(N_10457) + ); + defparam m6_3.INIT = 8'h04; + LUT3 m6_3 ( + .I0(plm_dfm_deframe1_dword_empty), + .I1(plm_dfm_deframe1_dword_sdpstp[0]), + .I2(plm_dfm_deframe1_dword_sdpstp[1]), + .O(N_3546) + ); + defparam G_235.INIT = 8'h96; + LUT3 G_235 ( + .I0(N_10398_1), + .I1(data_in_q[20]), + .I2(data_in_q[33]), + .O(N_241) + ); + defparam G_377.INIT = 4'h6; + LUT2 G_377 ( + .I0(N_10519_1), + .I1(plm_des0_reg_lfsr_one_12__365), + .O(G_377_366) + ); + defparam G_397.INIT = 8'h96; + LUT3 G_397 ( + .I0(data_in_q[0]), + .I1(data_in_q[12]), + .I2(data_in_q[37]), + .O(G_397_367) + ); + defparam G_434.INIT = 8'h96; + LUT3 G_434 ( + .I0(data_in_q[10]), + .I1(data_in_q[50]), + .I2(data_in_q[63]), + .O(G_434_368) + ); + defparam G_367_0.INIT = 4'h6; + LUT2 G_367_0 ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d64_19__49), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d64_31__50), + .O(G_367_0_271) + ); + defparam G_406_1_0.INIT = 4'h6; + LUT2 G_406_1_0 ( + .I0(com_llm_llm_rx_top_rx_data_57_), + .I1(com_llm_llm_rx_top_rx_data_58_), + .O(G_406_1_282) + ); + defparam G_418_0.INIT = 4'h6; + LUT2 G_418_0 ( + .I0(data_in_q[22]), + .I1(data_in_q[46]), + .O(G_418_0_298) + ); + defparam m4_1.INIT = 4'h6; + LUT2 m4_1 ( + .I0(com_tlm_cmmt_err_flow_control), + .I1(com_tlm_cmmt_err_tlp_malformed), + .O(m4_1_232) + ); + defparam I_5112_i_0_0_o3_0_0.INIT = 4'h1; + LUT2 I_5112_i_0_0_o3_0_0 ( + .I0(plm_rx0_lane_num[3]), + .I1(plm_rx0_lane_num[4]), + .O(I_5112_i_0_0_o3_0_0_293) + ); + defparam m10.INIT = 4'h4; + LUT2 m10 ( + .I0(com_cmm_u_cmm_errman_wtd_cor_add_input_one_d_259), + .I1(com_cmm_u_cmm_errman_wtd_cor_add_input_two_n_d_262), + .O(m10_263) + ); + defparam m12_0_0_0_a3_1.INIT = 4'h1; + LUT2 m12_0_0_0_a3_1 ( + .I0(com_tlm_cmmt_err_flow_control), + .I1(com_tlm_cmmt_err_rbuf_overflow), + .O(N_50488) + ); + defparam m5_2_i_0_o3.INIT = 4'h8; + LUT2 m5_2_i_0_o3 ( + .I0(com_lnk_rd[0]), + .I1(com_lnk_rd[3]), + .O(N_36389_i) + ); + defparam G_97.INIT = 4'h6; + LUT2 G_97 ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[20]), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[24]), + .O(N_101) + ); + defparam G_98.INIT = 4'h6; + LUT2 G_98 ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[16]), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[21]), + .O(N_102) + ); + defparam G_101.INIT = 4'h6; + LUT2 G_101 ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[16]), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_d64_c_q_2__369), + .O(N_105) + ); + defparam G_117.INIT = 4'h6; + LUT2 G_117 ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[18]), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[27]), + .O(N_121) + ); + defparam G_304.INIT = 4'h6; + LUT2 G_304 ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[1]), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[2]), + .O(N_10446) + ); + defparam G_348.INIT = 4'h6; + LUT2 G_348 ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[19]), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[20]), + .O(N_10490) + ); + defparam G_349.INIT = 4'h6; + LUT2 G_349 ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[19]), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[22]), + .O(N_10491) + ); + defparam G_350.INIT = 4'h6; + LUT2 G_350 ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[19]), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[29]), + .O(N_10492) + ); + defparam G_351.INIT = 4'h6; + LUT2 G_351 ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[15]), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[19]), + .O(N_10493) + ); + defparam G_392.INIT = 4'h6; + LUT2 G_392 ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[12]), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[28]), + .O(N_10534) + ); + defparam G_396.INIT = 4'h6; + LUT2 G_396 ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[26]), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_d64_c_q_5__370), + .O(N_10538) + ); + defparam G_402.INIT = 4'h6; + LUT2 G_402 ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crc32_d64_feedback[2]), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crc32_d64_feedback[10]), + .O(N_10544) + ); + defparam G_454.INIT = 4'h6; + LUT2 G_454 ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[2]), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[4]), + .O(N_10596) + ); + defparam G_458.INIT = 4'h6; + LUT2 G_458 ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crc32_d64_feedback[2]), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crc32_d64_feedback[7]), + .O(N_10600) + ); + defparam G_471.INIT = 4'h6; + LUT2 G_471 ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[15]), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[25]), + .O(N_10613) + ); + defparam G_443_1.INIT = 4'h6; + LUT2 G_443_1 ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crc32_d64_feedback[14]), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crc32_d64_feedback[22]), + .O(N_10585_1) + ); + defparam G_386_1.INIT = 4'h6; + LUT2 G_386_1 ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crc32_d64_feedback[6]), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crc32_d64_feedback[25]), + .O(N_10528_1) + ); + defparam G_312_1.INIT = 4'h6; + LUT2 G_312_1 ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crc32_d64_feedback[0]), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crc32_d64_feedback[3]), + .O(N_10454_1) + ); + defparam G_282_1.INIT = 4'h6; + LUT2 G_282_1 ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crc32_d64_feedback[1]), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crc32_d64_feedback[4]), + .O(N_10424_1) + ); + defparam G_281_1.INIT = 4'h6; + LUT2 G_281_1 ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crc32_d64_feedback[16]), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crc32_d64_feedback[20]), + .O(N_10423_1) + ); + defparam G_276_1.INIT = 4'h6; + LUT2 G_276_1 ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crc32_d64_feedback[0]), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crc32_d64_feedback[26]), + .O(N_10418_1) + ); + defparam G_269_1.INIT = 4'h6; + LUT2 G_269_1 ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crc32_d64_feedback[13]), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crc32_d64_feedback[15]), + .O(N_10411_1) + ); + defparam G_266_1.INIT = 4'h6; + LUT2 G_266_1 ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crc32_d64_feedback[20]), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crc32_d64_feedback[25]), + .O(N_10408_1) + ); + defparam G_211_1.INIT = 4'h6; + LUT2 G_211_1 ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crc32_d64_feedback[23]), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crc32_d64_feedback[30]), + .O(N_216_1) + ); + defparam G_181_1.INIT = 4'h6; + LUT2 G_181_1 ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crc32_d64_feedback[18]), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crc32_d64_feedback[19]), + .O(N_10377_1) + ); + defparam G_107_1.INIT = 4'h6; + LUT2 G_107_1 ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[20]), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[28]), + .O(N_111_1) + ); + defparam G_77_1.INIT = 4'h6; + LUT2 G_77_1 ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[16]), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[24]), + .O(N_81_1) + ); + defparam G_419_0_x4_0.INIT = 4'h6; + LUT2_L G_419_0_x4_0 ( + .I0(com_llm_llm_rx_top_rx_data_46_), + .I1(com_llm_llm_rx_top_rx_data_62_), + .LO(N_27388_i) + ); + defparam G_442_0_x4_0.INIT = 4'h6; + LUT2_L G_442_0_x4_0 ( + .I0(com_llm_llm_rx_top_rx_data_27_), + .I1(com_llm_llm_rx_top_rx_data_46_), + .LO(N_27390_i) + ); + defparam G_259_1.INIT = 4'h6; + LUT2 G_259_1 ( + .I0(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_6_), + .I1(com_llm_llm_rx_top_rx_data_58_), + .O(N_10401_1) + ); + defparam G_248_1.INIT = 4'h6; + LUT2 G_248_1 ( + .I0(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_41_), + .I1(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_47_), + .O(N_254_1) + ); + defparam G_247_1.INIT = 4'h6; + LUT2 G_247_1 ( + .I0(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_37_), + .I1(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_42_), + .O(N_253_1) + ); + defparam G_244_1.INIT = 4'h6; + LUT2 G_244_1 ( + .I0(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_9_), + .I1(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_15_), + .O(N_10392_1) + ); + defparam G_243_1.INIT = 4'h6; + LUT2 G_243_1 ( + .I0(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_5_), + .I1(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_10_), + .O(N_249_1) + ); + defparam G_241_1.INIT = 4'h6; + LUT2 G_241_1 ( + .I0(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_24_), + .I1(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_36_), + .O(N_247_1) + ); + defparam G_222_1.INIT = 4'h6; + LUT2 G_222_1 ( + .I0(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_6_), + .I1(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_14_), + .O(N_228_1) + ); + defparam G_203_1.INIT = 4'h6; + LUT2 G_203_1 ( + .I0(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_13_), + .I1(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_21_), + .O(N_208_1) + ); + defparam G_280_1.INIT = 4'h6; + LUT2 G_280_1 ( + .I0(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_9_), + .I1(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_17_), + .O(N_10422_1) + ); + defparam G_472_0_x4_0_x4.INIT = 4'h6; + LUT2 G_472_0_x4_0_x4 ( + .I0(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_27_), + .I1(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_31_), + .O(N_27395_i_0) + ); + defparam G_446_0_x4_0_x4.INIT = 4'h6; + LUT2 G_446_0_x4_0_x4 ( + .I0(com_llm_llm_rx_top_rx_data_59_), + .I1(com_llm_llm_rx_top_rx_data_63_), + .O(N_27394_i_0) + ); + defparam G_315_1.INIT = 4'h6; + LUT2 G_315_1 ( + .I0(com_llm_llm_tx_top_tx_dllp_td_27_), + .I1(com_llm_llm_tx_top_tx_dllp_td_31_), + .O(N_10457_1) + ); + defparam G_290_1.INIT = 4'h6; + LUT2 G_290_1 ( + .I0(com_llm_llm_tx_top_tx_dllp_td_33_), + .I1(com_llm_llm_tx_top_tx_dllp_td_35_), + .O(N_10432_1) + ); + defparam I_5041_i_0_0_o4.INIT = 4'h8; + LUT2 I_5041_i_0_0_o4 ( + .I0(plm_rx0_lane_pad), + .I1(plm_rx0_link_pad), + .O(N_38190_i) + ); + defparam m1_3.INIT = 4'h4; + LUT2 m1_3 ( + .I0(plm_dfm_deframe1_dword_empty), + .I1(plm_dfm_deframe1_dword_sdpstp[1]), + .O(N_3541) + ); + defparam m14_2_1.INIT = 4'h1; + LUT2 m14_2_1 ( + .I0(plm_dfm_deframe1_dword_edbedg[0]), + .I1(plm_dfm_deframe1_dword_edbedg[1]), + .O(plm_dfm_deframe1_qwfsm_nxt_state_1[7]) + ); + defparam G_113_1.INIT = 4'h6; + LUT2 G_113_1 ( + .I0(data_in_q[25]), + .I1(data_in_q[47]), + .O(N_117_1) + ); + defparam G_129_1.INIT = 4'h6; + LUT2 G_129_1 ( + .I0(data_in_q[16]), + .I1(data_in_q[18]), + .O(N_10357_1) + ); + defparam G_133_1.INIT = 4'h6; + LUT2 G_133_1 ( + .I0(data_in_q[18]), + .I1(data_in_q[52]), + .O(N_10358_1) + ); + defparam G_144_1.INIT = 4'h6; + LUT2 G_144_1 ( + .I0(data_in_q[7]), + .I1(data_in_q[51]), + .O(N_10366_1) + ); + defparam G_149_1.INIT = 4'h6; + LUT2 G_149_1 ( + .I0(data_in_q[29]), + .I1(data_in_q[58]), + .O(N_10369_1) + ); + defparam G_151_1.INIT = 4'h6; + LUT2 G_151_1 ( + .I0(data_in_q[6]), + .I1(data_in_q[58]), + .O(N_155_1) + ); + defparam G_159_1.INIT = 4'h6; + LUT2 G_159_1 ( + .I0(data_in_q[21]), + .I1(data_in_q[22]), + .O(N_163_1) + ); + defparam G_161_1.INIT = 4'h6; + LUT2 G_161_1 ( + .I0(data_in_q[3]), + .I1(data_in_q[59]), + .O(N_165_1) + ); + defparam G_169_1.INIT = 4'h6; + LUT2 G_169_1 ( + .I0(data_in_q[2]), + .I1(data_in_q[19]), + .O(N_173_1) + ); + defparam G_194_1.INIT = 4'h6; + LUT2 G_194_1 ( + .I0(data_in_q[8]), + .I1(data_in_q[26]), + .O(N_199_1) + ); + defparam G_197_2.INIT = 4'h6; + LUT2 G_197_2 ( + .I0(data_in_q[44]), + .I1(data_in_q[47]), + .O(N_202_2) + ); + defparam G_204_1.INIT = 4'h6; + LUT2 G_204_1 ( + .I0(data_in_q[36]), + .I1(data_in_q[54]), + .O(N_209_1) + ); + defparam G_205_1.INIT = 4'h6; + LUT2 G_205_1 ( + .I0(data_in_q[9]), + .I1(data_in_q[36]), + .O(N_210_1) + ); + defparam G_206_2.INIT = 4'h6; + LUT2 G_206_2 ( + .I0(data_in_q[24]), + .I1(data_in_q[27]), + .O(N_211_2) + ); + defparam G_228_1.INIT = 4'h6; + LUT2 G_228_1 ( + .I0(data_in_q[1]), + .I1(data_in_q[30]), + .O(N_234_1) + ); + defparam G_232_1.INIT = 4'h6; + LUT2 G_232_1 ( + .I0(data_in_q[17]), + .I1(data_in_q[36]), + .O(N_10391_1) + ); + defparam G_256_1.INIT = 4'h6; + LUT2 G_256_1 ( + .I0(data_in_q[38]), + .I1(data_in_q[45]), + .O(N_10398_1) + ); + defparam G_271_2.INIT = 4'h6; + LUT2 G_271_2 ( + .I0(data_in_q[0]), + .I1(data_in_q[34]), + .O(N_10413_2) + ); + defparam G_271_1.INIT = 4'h6; + LUT2 G_271_1 ( + .I0(data_in_q[22]), + .I1(data_in_q[42]), + .O(N_10413_1) + ); + defparam G_287_1.INIT = 4'h6; + LUT2_L G_287_1 ( + .I0(data_in_q[5]), + .I1(data_in_q[53]), + .LO(N_10429_1) + ); + defparam G_327_1.INIT = 4'h6; + LUT2 G_327_1 ( + .I0(plm_scr0_reg_lfsr_two_0__371), + .I1(plm_scr0_reg_lfsr_two_11__372), + .O(N_10469_1) + ); + defparam G_376_1.INIT = 4'h6; + LUT2 G_376_1 ( + .I0(data_in_q[26]), + .I1(data_in_q[61]), + .O(N_10518_1) + ); + defparam G_377_1.INIT = 4'h6; + LUT2 G_377_1 ( + .I0(plm_des0_reg_lfsr_one_0__373), + .I1(plm_des0_reg_lfsr_one_11__374), + .O(N_10519_1) + ); + defparam G_416_1.INIT = 4'h6; + LUT2 G_416_1 ( + .I0(plm_scr0_reg_lfsr_one_0__375), + .I1(plm_scr0_reg_lfsr_one_11__376), + .O(N_10558_1) + ); + defparam G_418_1.INIT = 4'h6; + LUT2 G_418_1 ( + .I0(data_in_q[4]), + .I1(data_in_q[48]), + .O(N_10560_1) + ); + defparam G_331_0_x4_0_x4.INIT = 4'h6; + LUT2 G_331_0_x4_0_x4 ( + .I0(plm_des0_reg_lfsr_one_3__336), + .I1(plm_des0_reg_lfsr_one_14__377), + .O(N_35131_i_0) + ); + defparam G_330_0_x4_0_x4.INIT = 4'h6; + LUT2 G_330_0_x4_0_x4 ( + .I0(plm_des0_reg_lfsr_two_4__378), + .I1(plm_des0_reg_lfsr_two_15__345), + .O(N_35130_i_0) + ); + defparam G_391_0_x4.INIT = 4'h6; + LUT2 G_391_0_x4 ( + .I0(plm_des0_reg_lfsr_two_1__379), + .I1(plm_des0_reg_lfsr_two_2__380), + .O(N_35117_i_0) + ); + defparam G_451_0_x4.INIT = 4'h6; + LUT2 G_451_0_x4 ( + .I0(plm_scr0_reg_lfsr_two_11__372), + .I1(plm_scr0_reg_lfsr_two_14__381), + .O(N_17488_i_0) + ); + defparam G_328_0_x4.INIT = 4'h6; + LUT2 G_328_0_x4 ( + .I0(plm_scr0_reg_lfsr_two_4__382), + .I1(plm_scr0_reg_lfsr_two_15__340), + .O(N_17486_i_0) + ); + defparam G_467.INIT = 4'h6; + LUT2 G_467 ( + .I0(data_in_q[25]), + .I1(data_in_q[30]), + .O(G_467_383) + ); + defparam G_447.INIT = 4'h6; + LUT2 G_447 ( + .I0(data_in_q[23]), + .I1(data_in_q[35]), + .O(G_447_384) + ); + defparam G_383.INIT = 4'h6; + LUT2 G_383 ( + .I0(data_in_q[19]), + .I1(data_in_q[49]), + .O(G_383_385) + ); + defparam G_362.INIT = 4'h6; + LUT2 G_362 ( + .I0(data_in_q[25]), + .I1(data_in_q[38]), + .O(G_362_386) + ); + defparam G_332.INIT = 4'h6; + LUT2 G_332 ( + .I0(plm_scr0_reg_lfsr_one_3__330), + .I1(plm_scr0_reg_lfsr_one_14__387), + .O(G_332_388) + ); + defparam G_294.INIT = 4'h6; + LUT2 G_294 ( + .I0(data_in_q[17]), + .I1(data_in_q[30]), + .O(G_294_389) + ); + defparam G_293.INIT = 4'h6; + LUT2 G_293 ( + .I0(data_in_q[17]), + .I1(data_in_q[35]), + .O(G_293_390) + ); + defparam G_272.INIT = 4'h6; + LUT2 G_272 ( + .I0(data_in_q[13]), + .I1(data_in_q[42]), + .O(G_272_391) + ); + FDR regcom_cmm_u_cmm_errman_wtd_nfl_reg_cor_num_0_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(NlwRenamedSig_OI_cfg_status_4_), + .Q(com_cmm_u_cmm_pm_dev_power_state_eq_d0), + .R(com_cmm_rst_267) + ); + GND GND_0 ( + .G(NlwRenamedSignal_cfg_lcommand[15]) + ); + VCC VCC_1 ( + .P(NlwRenamedSig_OI_cfg_status_4_) + ); + VCC plm_VCC ( + .P(plm_VCC_392) + ); + GND plm_GND ( + .G(plm_GND_393) + ); + defparam plm_N_38584_i.INIT = 4'hE; + LUT2_L plm_N_38584_i ( + .I0(cfg_cfg_5072[510]), + .I1(plm_noscramble), + .LO(plm_N_38584_i_394) + ); + defparam plm_N_50789_i.INIT = 4'hE; + LUT2_L plm_N_50789_i ( + .I0(plm_phy_rbad_dfrm_h), + .I1(plm_phy_rbad_dfrm_l), + .LO(N_50789_i) + ); + defparam plm_un1_tstall_n_0_a2.INIT = 16'h0001; + LUT4_L plm_un1_tstall_n_0_a2 ( + .I0(plm_raw_tstall), + .I1(plm_reg_raw_tstall_d1_397), + .I2(plm_reg_raw_tstall_d2_396), + .I3(plm_reg_raw_tstall_d3_395), + .LO(plm_un1_tstall_n_0_a2_398) + ); + FDC plm_reg_raw_tstall_d3 ( + .C(mgt_clk), + .D(plm_reg_raw_tstall_d2_396), + .Q(plm_reg_raw_tstall_d3_395), + .CLR(plm_rst) + ); + FDC plm_reg_raw_tstall_d2 ( + .C(mgt_clk), + .D(plm_reg_raw_tstall_d1_397), + .Q(plm_reg_raw_tstall_d2_396), + .CLR(plm_rst) + ); + FDC plm_reg_raw_tstall_d1 ( + .C(mgt_clk), + .D(plm_raw_tstall), + .Q(plm_reg_raw_tstall_d1_397), + .CLR(plm_rst) + ); + FDPE plm_reg_phy_tstall_n ( + .PRE(plm_rst), + .CE(plm_phy_cke_3_399), + .C(mgt_clk), + .D(plm_un1_tstall_n_0_a2_398), + .Q(plm_phy_tstall_n) + ); + INV plm_phy_tstall_n_i ( + .I(plm_phy_tstall_n), + .O(phy_tstall_n_i) + ); + INV plm_trn_reset_n_i ( + .I(NlwRenamedSig_OI_trn_reset_n), + .O(trn_reset_n_i) + ); + BUF plm_phy_cke_0 ( + .I(plm_phy_cke), + .O(plm_phy_cke_0_402) + ); + BUF plm_phy_cke_1 ( + .I(plm_phy_cke), + .O(plm_phy_cke_1_401) + ); + BUF plm_phy_cke_2 ( + .I(plm_phy_cke), + .O(plm_phy_cke_2_400) + ); + BUF plm_phy_cke_3 ( + .I(plm_phy_cke), + .O(plm_phy_cke_3_399) + ); + VCC plm_v4f_mgt_VCC ( + .P(plm_v4f_mgt_pipe_phystatus) + ); + GND plm_v4f_mgt_GND ( + .G(plm_v4f_mgt_lstate_support[3]) + ); + BUFG plm_v4f_mgt_special_bufg ( + .I(sys_clkz), + .O(plm_v4f_mgt_special_clk) + ); + defparam plm_v4f_mgt_dcm.CLKDV_DIVIDE = 4.0; + defparam plm_v4f_mgt_dcm.CLKIN_DIVIDE_BY_2 = "TRUE"; + defparam plm_v4f_mgt_dcm.CLKIN_PERIOD = 4.0; + defparam plm_v4f_mgt_dcm.DCM_AUTOCALIBRATION = "FALSE"; + DCM_ADV plm_v4f_mgt_dcm ( + .CLK90(NLW_plm_v4f_mgt_dcm_CLK90_UNCONNECTED), + .CLKFX(NLW_plm_v4f_mgt_dcm_CLKFX_UNCONNECTED), + .CLKIN(sys_clkz), + .LOCKED(plm_v4f_mgt_dcm_lock), + .CLK2X(NLW_plm_v4f_mgt_dcm_CLK2X_UNCONNECTED), + .DWE(plm_v4f_mgt_lstate_support[3]), + .PSCLK(plm_v4f_mgt_lstate_support[3]), + .DCLK(plm_v4f_mgt_lstate_support[3]), + .PSDONE(NLW_plm_v4f_mgt_dcm_PSDONE_UNCONNECTED), + .PSINCDEC(plm_v4f_mgt_lstate_support[3]), + .PSEN(plm_v4f_mgt_lstate_support[3]), + .CLK0(plm_v4f_mgt_dcm_clk0), + .CLKFX180(NLW_plm_v4f_mgt_dcm_CLKFX180_UNCONNECTED), + .DEN(plm_v4f_mgt_lstate_support[3]), + .CLK180(NLW_plm_v4f_mgt_dcm_CLK180_UNCONNECTED), + .CLK2X180(NLW_plm_v4f_mgt_dcm_CLK2X180_UNCONNECTED), + .RST(plm_v4f_mgt_reg_dcm_439), + .CLK270(NLW_plm_v4f_mgt_dcm_CLK270_UNCONNECTED), + .CLKFB(mgt_clk), + .DRDY(NLW_plm_v4f_mgt_dcm_DRDY_UNCONNECTED), + .CLKDV(plm_v4f_mgt_dcm_clkd), + .DADDR({plm_v4f_mgt_lstate_support[3], plm_v4f_mgt_lstate_support[3], plm_v4f_mgt_lstate_support[3], plm_v4f_mgt_lstate_support[3], +plm_v4f_mgt_lstate_support[3], plm_v4f_mgt_lstate_support[3], plm_v4f_mgt_lstate_support[3]}), + .DI({plm_v4f_mgt_lstate_support[3], plm_v4f_mgt_lstate_support[3], plm_v4f_mgt_lstate_support[3], plm_v4f_mgt_lstate_support[3], +plm_v4f_mgt_lstate_support[3], plm_v4f_mgt_lstate_support[3], plm_v4f_mgt_lstate_support[3], plm_v4f_mgt_lstate_support[3], +plm_v4f_mgt_lstate_support[3], plm_v4f_mgt_lstate_support[3], plm_v4f_mgt_lstate_support[3], plm_v4f_mgt_lstate_support[3], +plm_v4f_mgt_lstate_support[3], plm_v4f_mgt_lstate_support[3], plm_v4f_mgt_lstate_support[3], plm_v4f_mgt_lstate_support[3]}), + .DO({NLW_plm_v4f_mgt_dcm_DO_15__UNCONNECTED, NLW_plm_v4f_mgt_dcm_DO_14__UNCONNECTED, NLW_plm_v4f_mgt_dcm_DO_13__UNCONNECTED, +NLW_plm_v4f_mgt_dcm_DO_12__UNCONNECTED, NLW_plm_v4f_mgt_dcm_DO_11__UNCONNECTED, NLW_plm_v4f_mgt_dcm_DO_10__UNCONNECTED, +NLW_plm_v4f_mgt_dcm_DO_9__UNCONNECTED, NLW_plm_v4f_mgt_dcm_DO_8__UNCONNECTED, NLW_plm_v4f_mgt_dcm_DO_7__UNCONNECTED, +NLW_plm_v4f_mgt_dcm_DO_6__UNCONNECTED, NLW_plm_v4f_mgt_dcm_DO_5__UNCONNECTED, NLW_plm_v4f_mgt_dcm_DO_4__UNCONNECTED, +NLW_plm_v4f_mgt_dcm_DO_3__UNCONNECTED, NLW_plm_v4f_mgt_dcm_DO_2__UNCONNECTED, NLW_plm_v4f_mgt_dcm_DO_1__UNCONNECTED, +NLW_plm_v4f_mgt_dcm_DO_0__UNCONNECTED}) + ); + BUFG plm_v4f_mgt_phy_bufg ( + .I(plm_v4f_mgt_dcm_clkd), + .O(NlwRenamedSig_OI_trn_clk) + ); + BUFG plm_v4f_mgt_mgt_bufg ( + .I(plm_v4f_mgt_dcm_clk0), + .O(mgt_clk) + ); + FD plm_v4f_mgt_SYNC0 ( + .C(mgt_clk), + .D(plm_v4f_mgt_rx_sigdet_n_async), + .Q(plm_v4f_mgt_rx_sigdet_n_temp) + ); + FD plm_v4f_mgt_SYNC1 ( + .C(mgt_clk), + .D(plm_v4f_mgt_rx_sigdet_n_temp), + .Q(plm_v4f_mgt_rx_enter_elecidle) + ); + MUXCY_L plm_v4f_mgt_reg_rst_cnt_cry_1_ ( + .CI(plm_v4f_mgt_reg_rst_cnt[0]), + .DI(plm_v4f_mgt_lstate_support[3]), + .LO(plm_v4f_mgt_reg_rst_cnt_cry[1]), + .S(plm_v4f_mgt_reg_rst_cnt_qxu[1]) + ); + XORCY plm_v4f_mgt_reg_rst_cnt_s_1_ ( + .CI(plm_v4f_mgt_reg_rst_cnt[0]), + .LI(plm_v4f_mgt_reg_rst_cnt_qxu[1]), + .O(plm_v4f_mgt_reg_rst_cnt_s[1]) + ); + MUXCY_L plm_v4f_mgt_reg_rst_cnt_cry_2_ ( + .CI(plm_v4f_mgt_reg_rst_cnt_cry[1]), + .DI(plm_v4f_mgt_lstate_support[3]), + .LO(plm_v4f_mgt_reg_rst_cnt_cry[2]), + .S(plm_v4f_mgt_reg_rst_cnt_qxu[2]) + ); + XORCY plm_v4f_mgt_reg_rst_cnt_s_2_ ( + .CI(plm_v4f_mgt_reg_rst_cnt_cry[1]), + .LI(plm_v4f_mgt_reg_rst_cnt_qxu[2]), + .O(plm_v4f_mgt_reg_rst_cnt_s[2]) + ); + MUXCY_L plm_v4f_mgt_reg_rst_cnt_cry_3_ ( + .CI(plm_v4f_mgt_reg_rst_cnt_cry[2]), + .DI(plm_v4f_mgt_lstate_support[3]), + .LO(plm_v4f_mgt_reg_rst_cnt_cry[3]), + .S(plm_v4f_mgt_reg_rst_cnt_qxu[3]) + ); + XORCY plm_v4f_mgt_reg_rst_cnt_s_3_ ( + .CI(plm_v4f_mgt_reg_rst_cnt_cry[2]), + .LI(plm_v4f_mgt_reg_rst_cnt_qxu[3]), + .O(plm_v4f_mgt_reg_rst_cnt_s[3]) + ); + MUXCY_L plm_v4f_mgt_reg_rst_cnt_cry_4_ ( + .CI(plm_v4f_mgt_reg_rst_cnt_cry[3]), + .DI(plm_v4f_mgt_lstate_support[3]), + .LO(plm_v4f_mgt_reg_rst_cnt_cry[4]), + .S(plm_v4f_mgt_reg_rst_cnt_qxu[4]) + ); + XORCY plm_v4f_mgt_reg_rst_cnt_s_4_ ( + .CI(plm_v4f_mgt_reg_rst_cnt_cry[3]), + .LI(plm_v4f_mgt_reg_rst_cnt_qxu[4]), + .O(plm_v4f_mgt_reg_rst_cnt_s[4]) + ); + MUXCY_L plm_v4f_mgt_reg_rst_cnt_cry_5_ ( + .CI(plm_v4f_mgt_reg_rst_cnt_cry[4]), + .DI(plm_v4f_mgt_lstate_support[3]), + .LO(plm_v4f_mgt_reg_rst_cnt_cry[5]), + .S(plm_v4f_mgt_reg_rst_cnt_qxu[5]) + ); + XORCY plm_v4f_mgt_reg_rst_cnt_s_5_ ( + .CI(plm_v4f_mgt_reg_rst_cnt_cry[4]), + .LI(plm_v4f_mgt_reg_rst_cnt_qxu[5]), + .O(plm_v4f_mgt_reg_rst_cnt_s[5]) + ); + MUXCY_L plm_v4f_mgt_reg_rst_cnt_cry_6_ ( + .CI(plm_v4f_mgt_reg_rst_cnt_cry[5]), + .DI(plm_v4f_mgt_lstate_support[3]), + .LO(plm_v4f_mgt_reg_rst_cnt_cry[6]), + .S(plm_v4f_mgt_reg_rst_cnt_qxu[6]) + ); + XORCY plm_v4f_mgt_reg_rst_cnt_s_6_ ( + .CI(plm_v4f_mgt_reg_rst_cnt_cry[5]), + .LI(plm_v4f_mgt_reg_rst_cnt_qxu[6]), + .O(plm_v4f_mgt_reg_rst_cnt_s[6]) + ); + MUXCY_L plm_v4f_mgt_reg_rst_cnt_cry_7_ ( + .CI(plm_v4f_mgt_reg_rst_cnt_cry[6]), + .DI(plm_v4f_mgt_lstate_support[3]), + .LO(plm_v4f_mgt_reg_rst_cnt_cry[7]), + .S(plm_v4f_mgt_reg_rst_cnt_qxu[7]) + ); + XORCY plm_v4f_mgt_reg_rst_cnt_s_7_ ( + .CI(plm_v4f_mgt_reg_rst_cnt_cry[6]), + .LI(plm_v4f_mgt_reg_rst_cnt_qxu[7]), + .O(plm_v4f_mgt_reg_rst_cnt_s[7]) + ); + MUXCY_L plm_v4f_mgt_reg_rst_cnt_cry_8_ ( + .CI(plm_v4f_mgt_reg_rst_cnt_cry[7]), + .DI(plm_v4f_mgt_lstate_support[3]), + .LO(plm_v4f_mgt_reg_rst_cnt_cry[8]), + .S(plm_v4f_mgt_reg_rst_cnt_qxu[8]) + ); + XORCY plm_v4f_mgt_reg_rst_cnt_s_8_ ( + .CI(plm_v4f_mgt_reg_rst_cnt_cry[7]), + .LI(plm_v4f_mgt_reg_rst_cnt_qxu[8]), + .O(plm_v4f_mgt_reg_rst_cnt_s[8]) + ); + MUXCY_L plm_v4f_mgt_reg_rst_cnt_cry_9_ ( + .CI(plm_v4f_mgt_reg_rst_cnt_cry[8]), + .DI(plm_v4f_mgt_lstate_support[3]), + .LO(plm_v4f_mgt_reg_rst_cnt_cry[9]), + .S(plm_v4f_mgt_reg_rst_cnt_qxu[9]) + ); + XORCY plm_v4f_mgt_reg_rst_cnt_s_9_ ( + .CI(plm_v4f_mgt_reg_rst_cnt_cry[8]), + .LI(plm_v4f_mgt_reg_rst_cnt_qxu[9]), + .O(plm_v4f_mgt_reg_rst_cnt_s[9]) + ); + MUXCY_L plm_v4f_mgt_reg_rst_cnt_cry_10_ ( + .CI(plm_v4f_mgt_reg_rst_cnt_cry[9]), + .DI(plm_v4f_mgt_lstate_support[3]), + .LO(plm_v4f_mgt_reg_rst_cnt_cry[10]), + .S(plm_v4f_mgt_reg_rst_cnt_qxu[10]) + ); + XORCY plm_v4f_mgt_reg_rst_cnt_s_10_ ( + .CI(plm_v4f_mgt_reg_rst_cnt_cry[9]), + .LI(plm_v4f_mgt_reg_rst_cnt_qxu[10]), + .O(plm_v4f_mgt_reg_rst_cnt_s[10]) + ); + MUXCY_L plm_v4f_mgt_reg_rst_cnt_cry_11_ ( + .CI(plm_v4f_mgt_reg_rst_cnt_cry[10]), + .DI(plm_v4f_mgt_lstate_support[3]), + .LO(plm_v4f_mgt_reg_rst_cnt_cry[11]), + .S(plm_v4f_mgt_reg_rst_cnt_qxu[11]) + ); + XORCY plm_v4f_mgt_reg_rst_cnt_s_11_ ( + .CI(plm_v4f_mgt_reg_rst_cnt_cry[10]), + .LI(plm_v4f_mgt_reg_rst_cnt_qxu[11]), + .O(plm_v4f_mgt_reg_rst_cnt_s[11]) + ); + MUXCY_L plm_v4f_mgt_reg_rst_cnt_cry_12_ ( + .CI(plm_v4f_mgt_reg_rst_cnt_cry[11]), + .DI(plm_v4f_mgt_lstate_support[3]), + .LO(plm_v4f_mgt_reg_rst_cnt_cry[12]), + .S(plm_v4f_mgt_reg_rst_cnt_qxu[12]) + ); + XORCY plm_v4f_mgt_reg_rst_cnt_s_12_ ( + .CI(plm_v4f_mgt_reg_rst_cnt_cry[11]), + .LI(plm_v4f_mgt_reg_rst_cnt_qxu[12]), + .O(plm_v4f_mgt_reg_rst_cnt_s[12]) + ); + MUXCY_L plm_v4f_mgt_reg_rst_cnt_cry_13_ ( + .CI(plm_v4f_mgt_reg_rst_cnt_cry[12]), + .DI(plm_v4f_mgt_lstate_support[3]), + .LO(plm_v4f_mgt_reg_rst_cnt_cry[13]), + .S(plm_v4f_mgt_reg_rst_cnt_qxu[13]) + ); + XORCY plm_v4f_mgt_reg_rst_cnt_s_13_ ( + .CI(plm_v4f_mgt_reg_rst_cnt_cry[12]), + .LI(plm_v4f_mgt_reg_rst_cnt_qxu[13]), + .O(plm_v4f_mgt_reg_rst_cnt_s[13]) + ); + XORCY plm_v4f_mgt_reg_rst_cnt_s_14_ ( + .CI(plm_v4f_mgt_reg_rst_cnt_cry[13]), + .LI(plm_v4f_mgt_reg_rst_cnt_qxu[14]), + .O(plm_v4f_mgt_reg_rst_cnt_s[14]) + ); + defparam plm_v4f_mgt_un1_reg_plm_rst_n_2_0_o3_0_.INIT = 4'h8; + LUT2 plm_v4f_mgt_un1_reg_plm_rst_n_2_0_o3_0_ ( + .I0(plm_v4f_mgt_reg_rst_cnt[13]), + .I1(plm_v4f_mgt_reg_rst_cnt[14]), + .O(plm_v4f_mgt_N_394_i) + ); + defparam plm_v4f_mgt_un1_reg_plm_rst_n_2_0_o3_0_0_.INIT = 4'h8; + LUT2 plm_v4f_mgt_un1_reg_plm_rst_n_2_0_o3_0_0_ ( + .I0(plm_v4f_mgt_reg_rst_cnt[3]), + .I1(plm_v4f_mgt_reg_rst_cnt[4]), + .O(plm_v4f_mgt_N_406_i) + ); + defparam plm_v4f_mgt_for_v1_4_N_435_i.INIT = 4'hD; + LUT2 plm_v4f_mgt_for_v1_4_N_435_i ( + .I0(plm_v4f_mgt_dcm_lock), + .I1(cfg_cfg_5072[511]), + .O(plm_v4f_mgt_N_435_i) + ); + defparam plm_v4f_mgt_reset_delay_reg_tx_sync_5_i_o2.INIT = 8'h01; + LUT3 plm_v4f_mgt_reset_delay_reg_tx_sync_5_i_o2 ( + .I0(plm_v4f_mgt_reg_rst_cnt[10]), + .I1(plm_v4f_mgt_reg_rst_cnt[11]), + .I2(plm_v4f_mgt_reg_rst_cnt[12]), + .O(plm_v4f_mgt_N_404_i) + ); + defparam plm_v4f_mgt_sys_init_n_i.INIT = 4'h7; + LUT2 plm_v4f_mgt_sys_init_n_i ( + .I0(plm_v4f_mgt_dcm_lock), + .I1(plm_v4f_mgt_pma_txlock0), + .O(plm_v4f_mgt_sys_init_n_i_430) + ); + defparam plm_v4f_mgt_reset_delay_reg_tx_pcs_init_5_i_a3_0_0.INIT = 8'h80; + LUT3 plm_v4f_mgt_reset_delay_reg_tx_pcs_init_5_i_a3_0_0 ( + .I0(plm_v4f_mgt_reg_rst_cnt[0]), + .I1(plm_v4f_mgt_reg_rst_cnt[1]), + .I2(plm_v4f_mgt_reg_rst_cnt[2]), + .O(plm_v4f_mgt_reset_delay_reg_tx_sync_5_i_a2_1_0) + ); + defparam plm_v4f_mgt_dcm_delay_reg_dcm9.INIT = 16'h8000; + LUT4 plm_v4f_mgt_dcm_delay_reg_dcm9 ( + .I0(plm_v4f_mgt_reg_dcm_cnt[0]), + .I1(plm_v4f_mgt_reg_dcm_cnt[1]), + .I2(plm_v4f_mgt_reg_dcm_cnt[2]), + .I3(plm_v4f_mgt_reg_dcm_cnt[3]), + .O(plm_v4f_mgt_dcm_delay_reg_dcm9_438) + ); + defparam plm_v4f_mgt_pma_delay_reg_pma9.INIT = 16'h8000; + LUT4 plm_v4f_mgt_pma_delay_reg_pma9 ( + .I0(plm_v4f_mgt_reg_pma_cnt[0]), + .I1(plm_v4f_mgt_reg_pma_cnt[1]), + .I2(plm_v4f_mgt_reg_pma_cnt[2]), + .I3(plm_v4f_mgt_reg_pma_cnt[3]), + .O(plm_v4f_mgt_pma_delay_reg_pma9_440) + ); + defparam plm_v4f_mgt_un1_reg_plm_rst_n_2_0_o3_1_0_.INIT = 16'h0001; + LUT4 plm_v4f_mgt_un1_reg_plm_rst_n_2_0_o3_1_0_ ( + .I0(plm_v4f_mgt_reg_rst_cnt[5]), + .I1(plm_v4f_mgt_reg_rst_cnt[6]), + .I2(plm_v4f_mgt_reg_rst_cnt[7]), + .I3(plm_v4f_mgt_reg_rst_cnt[8]), + .O(plm_v4f_mgt_N_397_i) + ); + defparam plm_v4f_mgt_un1_reg_plm_rst_n_2_0_a2_2_1_0_.INIT = 8'h01; + LUT3 plm_v4f_mgt_un1_reg_plm_rst_n_2_0_a2_2_1_0_ ( + .I0(plm_v4f_mgt_reg_rst_cnt[9]), + .I1(plm_v4f_mgt_reg_rst_cnt[11]), + .I2(plm_v4f_mgt_reg_rst_cnt[12]), + .O(plm_v4f_mgt_un1_reg_plm_rst_n_2_0_a2_2_1[0]) + ); + defparam plm_v4f_mgt_N_422_i.INIT = 4'hD; + LUT2 plm_v4f_mgt_N_422_i ( + .I0(plm_v4f_mgt_pma_rxlock0), + .I1(plm_v4f_mgt_RXNOTINTABLE_0[1]), + .O(plm_rx0_not_in_table[0]) + ); + defparam plm_v4f_mgt_N_421_i.INIT = 4'hD; + LUT2 plm_v4f_mgt_N_421_i ( + .I0(plm_v4f_mgt_pma_rxlock0), + .I1(plm_v4f_mgt_RXNOTINTABLE_0[0]), + .O(plm_rx0_not_in_table[1]) + ); + defparam plm_v4f_mgt_un1_reg_plm_rst_n_2_0_a2_1_0_0_.INIT = 4'h2; + LUT2 plm_v4f_mgt_un1_reg_plm_rst_n_2_0_a2_1_0_0_ ( + .I0(plm_v4f_mgt_N_404_i), + .I1(plm_v4f_mgt_reg_rst_cnt[9]), + .O(plm_v4f_mgt_N_413_1) + ); + defparam plm_v4f_mgt_un1_reg_plm_rst_n_2_0_o3_2_0_.INIT = 8'h02; + LUT3 plm_v4f_mgt_un1_reg_plm_rst_n_2_0_o3_2_0_ ( + .I0(plm_v4f_mgt_N_397_i), + .I1(plm_v4f_mgt_reg_rst_cnt[13]), + .I2(plm_v4f_mgt_reg_rst_cnt[14]), + .O(plm_v4f_mgt_N_399_i) + ); + defparam plm_v4f_mgt_reset_delay_reg_tx_sync_5_i_a2_1_1.INIT = 16'h8000; + LUT4 plm_v4f_mgt_reset_delay_reg_tx_sync_5_i_a2_1_1 ( + .I0(plm_v4f_mgt_N_406_i), + .I1(plm_v4f_mgt_reg_rst_cnt[5]), + .I2(plm_v4f_mgt_reg_rst_cnt[6]), + .I3(plm_v4f_mgt_reg_rst_cnt[7]), + .O(plm_v4f_mgt_N_419_1) + ); + defparam plm_v4f_mgt_reset_delay_reg_tx_pcs_init_5_i_m3.INIT = 16'h5F33; + LUT4_L plm_v4f_mgt_reset_delay_reg_tx_pcs_init_5_i_m3 ( + .I0(plm_v4f_mgt_N_394_i), + .I1(plm_v4f_mgt_reg_rst_cnt[3]), + .I2(plm_v4f_mgt_reg_rst_cnt[8]), + .I3(plm_v4f_mgt_reg_rst_cnt[9]), + .LO(plm_v4f_mgt_reg_tx_pcs_init_5_i_m3) + ); + defparam plm_v4f_mgt_reset_delay_reg_tx_sync_5_i_m2.INIT = 16'hCC5F; + LUT4_L plm_v4f_mgt_reset_delay_reg_tx_sync_5_i_m2 ( + .I0(plm_v4f_mgt_N_394_i), + .I1(plm_v4f_mgt_reg_rst_cnt[3]), + .I2(plm_v4f_mgt_reg_rst_cnt[8]), + .I3(cfg_cfg_5072[507]), + .LO(plm_v4f_mgt_reg_tx_sync_5_i_m2) + ); + defparam plm_v4f_mgt_un1_reg_plm_rst_n_2_0_a2_2_0_.INIT = 16'h0200; + LUT4_L plm_v4f_mgt_un1_reg_plm_rst_n_2_0_a2_2_0_ ( + .I0(plm_v4f_mgt_N_397_i), + .I1(plm_v4f_mgt_reg_rst_cnt[4]), + .I2(cfg_cfg_5072[507]), + .I3(plm_v4f_mgt_un1_reg_plm_rst_n_2_0_a2_2_1[0]), + .LO(plm_v4f_mgt_un1_reg_plm_rst_n_2_0_a2_2[0]) + ); + defparam plm_v4f_mgt_reset_delay_reg_tx_sync_5_i_0.INIT = 16'h1055; + LUT4_L plm_v4f_mgt_reset_delay_reg_tx_sync_5_i_0 ( + .I0(plm_v4f_mgt_reg_tx_sync_5_i_m2), + .I1(plm_v4f_mgt_reg_rst_cnt[1]), + .I2(plm_v4f_mgt_reg_rst_cnt[2]), + .I3(cfg_cfg_5072[507]), + .LO(plm_v4f_mgt_reset_delay_reg_tx_sync_5_i_0_403) + ); + defparam plm_v4f_mgt_reset_delay_reg_tx_pcs_init_5_i_o2_1.INIT = 16'h0440; + LUT4_L plm_v4f_mgt_reset_delay_reg_tx_pcs_init_5_i_o2_1 ( + .I0(plm_v4f_mgt_reg_tx_pcs_init_5_i_m3), + .I1(plm_v4f_mgt_N_404_i), + .I2(plm_v4f_mgt_reg_rst_cnt[9]), + .I3(cfg_cfg_5072[507]), + .LO(plm_v4f_mgt_reset_delay_reg_tx_pcs_init_5_i_o2_1_404) + ); + defparam plm_v4f_mgt_un1_reg_plm_rst_n_2_0_1_0_.INIT = 16'h0F02; + LUT4_L plm_v4f_mgt_un1_reg_plm_rst_n_2_0_1_0_ ( + .I0(plm_v4f_mgt_N_394_i), + .I1(plm_v4f_mgt_N_404_i), + .I2(plm_v4f_mgt_un1_reg_plm_rst_n_2_0_a2_2[0]), + .I3(cfg_cfg_5072[507]), + .LO(plm_v4f_mgt_un1_reg_plm_rst_n_2_0_1[0]) + ); + defparam plm_v4f_mgt_un1_reg_plm_rst_n_2_0_0_.INIT = 16'hDF00; + LUT4 plm_v4f_mgt_un1_reg_plm_rst_n_2_0_0_ ( + .I0(plm_v4f_mgt_N_399_i), + .I1(plm_v4f_mgt_N_406_i), + .I2(plm_v4f_mgt_N_413_1), + .I3(plm_v4f_mgt_un1_reg_plm_rst_n_2_0_1[0]), + .O(plm_v4f_mgt_un1_reg_plm_rst_n_2_i[0]) + ); + defparam plm_v4f_mgt_reset_delay_reg_tx_sync_5_i_2.INIT = 16'h20A0; + LUT4_L plm_v4f_mgt_reset_delay_reg_tx_sync_5_i_2 ( + .I0(plm_v4f_mgt_N_413_1), + .I1(plm_v4f_mgt_N_419_1), + .I2(plm_v4f_mgt_reset_delay_reg_tx_sync_5_i_0_403), + .I3(plm_v4f_mgt_reset_delay_reg_tx_sync_5_i_a2_1_0), + .LO(plm_v4f_mgt_reset_delay_reg_tx_sync_5_i_2_406) + ); + defparam plm_v4f_mgt_reset_delay_reg_tx_pcs_init_5_i_o2_2.INIT = 16'h40F0; + LUT4_L plm_v4f_mgt_reset_delay_reg_tx_pcs_init_5_i_o2_2 ( + .I0(plm_v4f_mgt_N_419_1), + .I1(plm_v4f_mgt_reg_rst_cnt[9]), + .I2(plm_v4f_mgt_reset_delay_reg_tx_pcs_init_5_i_o2_1_404), + .I3(plm_v4f_mgt_reset_delay_reg_tx_sync_5_i_a2_1_0), + .LO(plm_v4f_mgt_reset_delay_reg_tx_pcs_init_5_i_o2_2_405) + ); + defparam plm_v4f_mgt_reset_delay_reg_tx_pcs_init_5_i_o2.INIT = 16'hF200; + LUT4 plm_v4f_mgt_reset_delay_reg_tx_pcs_init_5_i_o2 ( + .I0(plm_v4f_mgt_N_399_i), + .I1(plm_v4f_mgt_reg_rst_cnt[4]), + .I2(plm_v4f_mgt_reg_rst_cnt[9]), + .I3(plm_v4f_mgt_reset_delay_reg_tx_pcs_init_5_i_o2_2_405), + .O(plm_v4f_mgt_N_411_i) + ); + defparam plm_v4f_mgt_reset_delay_reg_tx_sync_5_i.INIT = 16'h20F0; + LUT4_L plm_v4f_mgt_reset_delay_reg_tx_sync_5_i ( + .I0(plm_v4f_mgt_N_399_i), + .I1(plm_v4f_mgt_reg_rst_cnt[4]), + .I2(plm_v4f_mgt_reset_delay_reg_tx_sync_5_i_2_406), + .I3(cfg_cfg_5072[507]), + .LO(plm_v4f_mgt_N_388_i) + ); + defparam plm_v4f_mgt_reg_phy_clk_toggle_i.INIT = 4'h1; + LUT1_L plm_v4f_mgt_reg_phy_clk_toggle_i ( + .I0(plm_v4f_mgt_reg_phy_clk_toggle_429), + .LO(plm_v4f_mgt_reg_phy_clk_toggle_i_428) + ); + defparam plm_v4f_mgt_reset_delay_N_420_i.INIT = 4'hB; + LUT2_L plm_v4f_mgt_reset_delay_N_420_i ( + .I0(plm_v4f_mgt_N_411_i), + .I1(plm_v4f_mgt_pma_rxlock0), + .LO(plm_v4f_mgt_N_420_i) + ); + defparam plm_v4f_mgt_reg_dcm_cnt_i_0_.INIT = 4'h1; + LUT1_L plm_v4f_mgt_reg_dcm_cnt_i_0_ ( + .I0(plm_v4f_mgt_reg_dcm_cnt[0]), + .LO(plm_v4f_mgt_reg_dcm_cnt_i[0]) + ); + defparam plm_v4f_mgt_un3_reg_pma_cnt_axbxc3.INIT = 16'h7F80; + LUT4_L plm_v4f_mgt_un3_reg_pma_cnt_axbxc3 ( + .I0(plm_v4f_mgt_reg_pma_cnt[0]), + .I1(plm_v4f_mgt_reg_pma_cnt[1]), + .I2(plm_v4f_mgt_reg_pma_cnt[2]), + .I3(plm_v4f_mgt_reg_pma_cnt[3]), + .LO(plm_v4f_mgt_un3_reg_pma_cnt_axbxc3_432) + ); + defparam plm_v4f_mgt_un3_reg_pma_cnt_axbxc2.INIT = 8'h78; + LUT3_L plm_v4f_mgt_un3_reg_pma_cnt_axbxc2 ( + .I0(plm_v4f_mgt_reg_pma_cnt[0]), + .I1(plm_v4f_mgt_reg_pma_cnt[1]), + .I2(plm_v4f_mgt_reg_pma_cnt[2]), + .LO(plm_v4f_mgt_un3_reg_pma_cnt_axbxc2_433) + ); + defparam plm_v4f_mgt_un3_reg_pma_cnt_axbxc1.INIT = 4'h6; + LUT2_L plm_v4f_mgt_un3_reg_pma_cnt_axbxc1 ( + .I0(plm_v4f_mgt_reg_pma_cnt[0]), + .I1(plm_v4f_mgt_reg_pma_cnt[1]), + .LO(plm_v4f_mgt_un3_reg_pma_cnt_axbxc1_434) + ); + defparam plm_v4f_mgt_reg_pma_cnt_i_0_.INIT = 4'h1; + LUT1_L plm_v4f_mgt_reg_pma_cnt_i_0_ ( + .I0(plm_v4f_mgt_reg_pma_cnt[0]), + .LO(plm_v4f_mgt_reg_pma_cnt_i[0]) + ); + defparam plm_v4f_mgt_un3_reg_dcm_cnt_axbxc3.INIT = 16'h7F80; + LUT4_L plm_v4f_mgt_un3_reg_dcm_cnt_axbxc3 ( + .I0(plm_v4f_mgt_reg_dcm_cnt[0]), + .I1(plm_v4f_mgt_reg_dcm_cnt[1]), + .I2(plm_v4f_mgt_reg_dcm_cnt[2]), + .I3(plm_v4f_mgt_reg_dcm_cnt[3]), + .LO(plm_v4f_mgt_un3_reg_dcm_cnt_axbxc3_435) + ); + defparam plm_v4f_mgt_un3_reg_dcm_cnt_axbxc2.INIT = 8'h78; + LUT3_L plm_v4f_mgt_un3_reg_dcm_cnt_axbxc2 ( + .I0(plm_v4f_mgt_reg_dcm_cnt[0]), + .I1(plm_v4f_mgt_reg_dcm_cnt[1]), + .I2(plm_v4f_mgt_reg_dcm_cnt[2]), + .LO(plm_v4f_mgt_un3_reg_dcm_cnt_axbxc2_436) + ); + defparam plm_v4f_mgt_un3_reg_dcm_cnt_axbxc1.INIT = 4'h6; + LUT2_L plm_v4f_mgt_un3_reg_dcm_cnt_axbxc1 ( + .I0(plm_v4f_mgt_reg_dcm_cnt[0]), + .I1(plm_v4f_mgt_reg_dcm_cnt[1]), + .LO(plm_v4f_mgt_un3_reg_dcm_cnt_axbxc1_437) + ); + defparam plm_v4f_mgt_delta_detect_reg_phase1_3.INIT = 4'h6; + LUT2_L plm_v4f_mgt_delta_detect_reg_phase1_3 ( + .I0(plm_v4f_mgt_reg_mgt_clk_sample_425), + .I1(plm_v4f_mgt_reg_phy_clk_toggle_429), + .LO(plm_v4f_mgt_delta_detect_reg_phase1_3_445) + ); + defparam plm_v4f_mgt_G_322.INIT = 4'h8; + LUT2 plm_v4f_mgt_G_322 ( + .I0(plm_v4f_mgt_reg_phase3_0_DOUT[0]), + .I1(plm_v4f_mgt_G_326_420), + .O(plm_phy_cke) + ); + defparam plm_v4f_mgt_G_343.INIT = 4'hE; + LUT2 plm_v4f_mgt_G_343 ( + .I0(plm_v4f_mgt_N_1151_i_443), + .I1(plm_v4f_mgt_reg_tee_dlyline_DOUT[0]), + .O(plm_v4f_mgt_reg_tee_dlyline[18]) + ); + FDC plm_v4f_mgt_G_320 ( + .C(mgt_clk), + .D(plm_v4f_mgt_G_324_421), + .Q(plm_v4f_mgt_G_320_419), + .CLR(plm_rst) + ); + FDC plm_v4f_mgt_G_339 ( + .C(mgt_clk), + .D(plm_v4f_mgt_G_338_407), + .Q(plm_v4f_mgt_G_339_423), + .CLR(plm_rst) + ); + FDC plm_v4f_mgt_G_338 ( + .C(mgt_clk), + .D(plm_v4f_mgt_G_337_408), + .Q(plm_v4f_mgt_G_338_407), + .CLR(plm_rst) + ); + FDC plm_v4f_mgt_G_337 ( + .C(mgt_clk), + .D(plm_v4f_mgt_G_336_409), + .Q(plm_v4f_mgt_G_337_408), + .CLR(plm_rst) + ); + FDC plm_v4f_mgt_G_336 ( + .C(mgt_clk), + .D(plm_v4f_mgt_G_335_410), + .Q(plm_v4f_mgt_G_336_409), + .CLR(plm_rst) + ); + FDC plm_v4f_mgt_G_335 ( + .C(mgt_clk), + .D(plm_v4f_mgt_G_334_411), + .Q(plm_v4f_mgt_G_335_410), + .CLR(plm_rst) + ); + FDC plm_v4f_mgt_G_334 ( + .C(mgt_clk), + .D(plm_v4f_mgt_G_333_412), + .Q(plm_v4f_mgt_G_334_411), + .CLR(plm_rst) + ); + FDC plm_v4f_mgt_G_333 ( + .C(mgt_clk), + .D(plm_v4f_mgt_G_332_413), + .Q(plm_v4f_mgt_G_333_412), + .CLR(plm_rst) + ); + FDC plm_v4f_mgt_G_332 ( + .C(mgt_clk), + .D(plm_v4f_mgt_G_331_414), + .Q(plm_v4f_mgt_G_332_413), + .CLR(plm_rst) + ); + FDC plm_v4f_mgt_G_331 ( + .C(mgt_clk), + .D(plm_v4f_mgt_G_330_415), + .Q(plm_v4f_mgt_G_331_414), + .CLR(plm_rst) + ); + FDC plm_v4f_mgt_G_330 ( + .C(mgt_clk), + .D(plm_v4f_mgt_G_329_416), + .Q(plm_v4f_mgt_G_330_415), + .CLR(plm_rst) + ); + FDC plm_v4f_mgt_G_329 ( + .C(mgt_clk), + .D(plm_v4f_mgt_G_328_417), + .Q(plm_v4f_mgt_G_329_416), + .CLR(plm_rst) + ); + FDC plm_v4f_mgt_G_328 ( + .C(mgt_clk), + .D(plm_v4f_mgt_G_327_418), + .Q(plm_v4f_mgt_G_328_417), + .CLR(plm_rst) + ); + FDC plm_v4f_mgt_G_327 ( + .C(mgt_clk), + .D(plm_v4f_mgt_G_326_420), + .Q(plm_v4f_mgt_G_327_418), + .CLR(plm_rst) + ); + FDC plm_v4f_mgt_G_326 ( + .C(mgt_clk), + .D(plm_v4f_mgt_G_320_419), + .Q(plm_v4f_mgt_G_326_420), + .CLR(plm_rst) + ); + FDC plm_v4f_mgt_G_324 ( + .C(mgt_clk), + .D(plm_v4f_mgt_pipe_phystatus), + .Q(plm_v4f_mgt_G_324_421), + .CLR(plm_rst) + ); + FDC plm_v4f_mgt_G_342 ( + .C(mgt_clk), + .D(plm_v4f_mgt_G_341_422), + .Q(plm_v4f_mgt_G_342_444), + .CLR(plm_rst) + ); + FDC plm_v4f_mgt_G_341 ( + .C(mgt_clk), + .D(plm_v4f_mgt_G_340_424), + .Q(plm_v4f_mgt_G_341_422), + .CLR(plm_rst) + ); + FDC plm_v4f_mgt_G_340 ( + .C(mgt_clk), + .D(plm_v4f_mgt_G_339_423), + .Q(plm_v4f_mgt_G_340_424), + .CLR(plm_rst) + ); + FD plm_v4f_mgt_reg_tee_dlyline_DOUT_0_ ( + .C(mgt_clk), + .D(plm_v4f_mgt_reg_tee_dlyline_tmp_d_array_1[0]), + .Q(plm_v4f_mgt_reg_tee_dlyline_DOUT[0]) + ); + FD plm_v4f_mgt_reg_phase3_0_DOUT_0_ ( + .C(mgt_clk), + .D(plm_v4f_mgt_reg_phase3_0_tmp_d_array_0[0]), + .Q(plm_v4f_mgt_reg_phase3_0_DOUT[0]) + ); + FDCE plm_v4f_mgt_reg_rst_cnt_14_ ( + .CE(plm_v4f_mgt_un1_reg_plm_rst_n_2_i_i[0]), + .C(mgt_clk), + .D(plm_v4f_mgt_reg_rst_cnt_s[14]), + .Q(plm_v4f_mgt_reg_rst_cnt[14]), + .CLR(plm_v4f_mgt_sys_init_n_i_430) + ); + FDCE plm_v4f_mgt_reg_rst_cnt_13_ ( + .CE(plm_v4f_mgt_un1_reg_plm_rst_n_2_i_i[0]), + .C(mgt_clk), + .D(plm_v4f_mgt_reg_rst_cnt_s[13]), + .Q(plm_v4f_mgt_reg_rst_cnt[13]), + .CLR(plm_v4f_mgt_sys_init_n_i_430) + ); + FDCE plm_v4f_mgt_reg_rst_cnt_12_ ( + .CE(plm_v4f_mgt_un1_reg_plm_rst_n_2_i_i[0]), + .C(mgt_clk), + .D(plm_v4f_mgt_reg_rst_cnt_s[12]), + .Q(plm_v4f_mgt_reg_rst_cnt[12]), + .CLR(plm_v4f_mgt_sys_init_n_i_430) + ); + FDCE plm_v4f_mgt_reg_rst_cnt_11_ ( + .CE(plm_v4f_mgt_un1_reg_plm_rst_n_2_i_i[0]), + .C(mgt_clk), + .D(plm_v4f_mgt_reg_rst_cnt_s[11]), + .Q(plm_v4f_mgt_reg_rst_cnt[11]), + .CLR(plm_v4f_mgt_sys_init_n_i_430) + ); + FDCE plm_v4f_mgt_reg_rst_cnt_10_ ( + .CE(plm_v4f_mgt_un1_reg_plm_rst_n_2_i_i[0]), + .C(mgt_clk), + .D(plm_v4f_mgt_reg_rst_cnt_s[10]), + .Q(plm_v4f_mgt_reg_rst_cnt[10]), + .CLR(plm_v4f_mgt_sys_init_n_i_430) + ); + FDCE plm_v4f_mgt_reg_rst_cnt_9_ ( + .CE(plm_v4f_mgt_un1_reg_plm_rst_n_2_i_i[0]), + .C(mgt_clk), + .D(plm_v4f_mgt_reg_rst_cnt_s[9]), + .Q(plm_v4f_mgt_reg_rst_cnt[9]), + .CLR(plm_v4f_mgt_sys_init_n_i_430) + ); + FDCE plm_v4f_mgt_reg_rst_cnt_8_ ( + .CE(plm_v4f_mgt_un1_reg_plm_rst_n_2_i_i[0]), + .C(mgt_clk), + .D(plm_v4f_mgt_reg_rst_cnt_s[8]), + .Q(plm_v4f_mgt_reg_rst_cnt[8]), + .CLR(plm_v4f_mgt_sys_init_n_i_430) + ); + FDCE plm_v4f_mgt_reg_rst_cnt_7_ ( + .CE(plm_v4f_mgt_un1_reg_plm_rst_n_2_i_i[0]), + .C(mgt_clk), + .D(plm_v4f_mgt_reg_rst_cnt_s[7]), + .Q(plm_v4f_mgt_reg_rst_cnt[7]), + .CLR(plm_v4f_mgt_sys_init_n_i_430) + ); + FDCE plm_v4f_mgt_reg_rst_cnt_6_ ( + .CE(plm_v4f_mgt_un1_reg_plm_rst_n_2_i_i[0]), + .C(mgt_clk), + .D(plm_v4f_mgt_reg_rst_cnt_s[6]), + .Q(plm_v4f_mgt_reg_rst_cnt[6]), + .CLR(plm_v4f_mgt_sys_init_n_i_430) + ); + FDCE plm_v4f_mgt_reg_rst_cnt_5_ ( + .CE(plm_v4f_mgt_un1_reg_plm_rst_n_2_i_i[0]), + .C(mgt_clk), + .D(plm_v4f_mgt_reg_rst_cnt_s[5]), + .Q(plm_v4f_mgt_reg_rst_cnt[5]), + .CLR(plm_v4f_mgt_sys_init_n_i_430) + ); + FDCE plm_v4f_mgt_reg_rst_cnt_4_ ( + .CE(plm_v4f_mgt_un1_reg_plm_rst_n_2_i_i[0]), + .C(mgt_clk), + .D(plm_v4f_mgt_reg_rst_cnt_s[4]), + .Q(plm_v4f_mgt_reg_rst_cnt[4]), + .CLR(plm_v4f_mgt_sys_init_n_i_430) + ); + FDCE plm_v4f_mgt_reg_rst_cnt_3_ ( + .CE(plm_v4f_mgt_un1_reg_plm_rst_n_2_i_i[0]), + .C(mgt_clk), + .D(plm_v4f_mgt_reg_rst_cnt_s[3]), + .Q(plm_v4f_mgt_reg_rst_cnt[3]), + .CLR(plm_v4f_mgt_sys_init_n_i_430) + ); + FDCE plm_v4f_mgt_reg_rst_cnt_2_ ( + .CE(plm_v4f_mgt_un1_reg_plm_rst_n_2_i_i[0]), + .C(mgt_clk), + .D(plm_v4f_mgt_reg_rst_cnt_s[2]), + .Q(plm_v4f_mgt_reg_rst_cnt[2]), + .CLR(plm_v4f_mgt_sys_init_n_i_430) + ); + FDCE plm_v4f_mgt_reg_rst_cnt_1_ ( + .CE(plm_v4f_mgt_un1_reg_plm_rst_n_2_i_i[0]), + .C(mgt_clk), + .D(plm_v4f_mgt_reg_rst_cnt_s[1]), + .Q(plm_v4f_mgt_reg_rst_cnt[1]), + .CLR(plm_v4f_mgt_sys_init_n_i_430) + ); + FDCE plm_v4f_mgt_reg_rst_cnt_0_ ( + .CE(plm_v4f_mgt_un1_reg_plm_rst_n_2_i_i[0]), + .C(mgt_clk), + .D(plm_v4f_mgt_reg_rst_cnt_s[0]), + .Q(plm_v4f_mgt_reg_rst_cnt[0]), + .CLR(plm_v4f_mgt_sys_init_n_i_430) + ); + FDC plm_v4f_mgt_reg_mgt_clk_sample ( + .C(mgt_clk), + .D(plm_v4f_mgt_reg_phy_clk_toggle_429), + .Q(plm_v4f_mgt_reg_mgt_clk_sample_425), + .CLR(plm_rst) + ); + FDC plm_v4f_mgt_reg_tx_sync ( + .C(mgt_clk), + .D(plm_v4f_mgt_N_388_i), + .Q(plm_v4f_mgt_reg_tx_sync_426), + .CLR(plm_v4f_mgt_sys_init_n_i_430) + ); + FDC plm_v4f_mgt_reg_tx_pcs_init ( + .C(mgt_clk), + .D(plm_v4f_mgt_N_411_i), + .Q(plm_v4f_mgt_reg_tx_pcs_init_427), + .CLR(plm_v4f_mgt_sys_init_n_i_430) + ); + FDC plm_v4f_mgt_reg_phy_clk_toggle ( + .C(NlwRenamedSig_OI_trn_clk), + .D(plm_v4f_mgt_reg_phy_clk_toggle_i_428), + .Q(plm_v4f_mgt_reg_phy_clk_toggle_429), + .CLR(plm_rst) + ); + FDC plm_v4f_mgt_reg_plm_rst_n ( + .C(mgt_clk), + .D(plm_v4f_mgt_un1_reg_plm_rst_n_2_i[0]), + .Q(NlwRenamedSig_OI_trn_reset_n), + .CLR(plm_v4f_mgt_sys_init_n_i_430) + ); + FDP plm_v4f_mgt_reg_plm_rst ( + .PRE(plm_v4f_mgt_sys_init_n_i_430), + .C(mgt_clk), + .D(plm_v4f_mgt_un1_reg_plm_rst_n_2_i_i[0]), + .Q(plm_rst) + ); + FDC plm_v4f_mgt_reg_rx_pcs_init ( + .C(mgt_clk), + .D(plm_v4f_mgt_N_420_i), + .Q(plm_v4f_mgt_reg_rx_pcs_init_431), + .CLR(plm_v4f_mgt_sys_init_n_i_430) + ); + FDC plm_v4f_mgt_reg_dcm_cnt_0_ ( + .C(plm_v4f_mgt_special_clk), + .D(plm_v4f_mgt_reg_dcm_cnt_i[0]), + .Q(plm_v4f_mgt_reg_dcm_cnt[0]), + .CLR(plm_v4f_mgt_sys_rst_n_i) + ); + FDC plm_v4f_mgt_reg_pma_cnt_3_ ( + .C(plm_v4f_mgt_special_clk), + .D(plm_v4f_mgt_un3_reg_pma_cnt_axbxc3_432), + .Q(plm_v4f_mgt_reg_pma_cnt[3]), + .CLR(plm_v4f_mgt_dcm_lock_i_442) + ); + FDC plm_v4f_mgt_reg_pma_cnt_2_ ( + .C(plm_v4f_mgt_special_clk), + .D(plm_v4f_mgt_un3_reg_pma_cnt_axbxc2_433), + .Q(plm_v4f_mgt_reg_pma_cnt[2]), + .CLR(plm_v4f_mgt_dcm_lock_i_442) + ); + FDC plm_v4f_mgt_reg_pma_cnt_1_ ( + .C(plm_v4f_mgt_special_clk), + .D(plm_v4f_mgt_un3_reg_pma_cnt_axbxc1_434), + .Q(plm_v4f_mgt_reg_pma_cnt[1]), + .CLR(plm_v4f_mgt_dcm_lock_i_442) + ); + FDC plm_v4f_mgt_reg_pma_cnt_0_ ( + .C(plm_v4f_mgt_special_clk), + .D(plm_v4f_mgt_reg_pma_cnt_i[0]), + .Q(plm_v4f_mgt_reg_pma_cnt[0]), + .CLR(plm_v4f_mgt_dcm_lock_i_442) + ); + FDC plm_v4f_mgt_reg_dcm_cnt_3_ ( + .C(plm_v4f_mgt_special_clk), + .D(plm_v4f_mgt_un3_reg_dcm_cnt_axbxc3_435), + .Q(plm_v4f_mgt_reg_dcm_cnt[3]), + .CLR(plm_v4f_mgt_sys_rst_n_i) + ); + FDC plm_v4f_mgt_reg_dcm_cnt_2_ ( + .C(plm_v4f_mgt_special_clk), + .D(plm_v4f_mgt_un3_reg_dcm_cnt_axbxc2_436), + .Q(plm_v4f_mgt_reg_dcm_cnt[2]), + .CLR(plm_v4f_mgt_sys_rst_n_i) + ); + FDC plm_v4f_mgt_reg_dcm_cnt_1_ ( + .C(plm_v4f_mgt_special_clk), + .D(plm_v4f_mgt_un3_reg_dcm_cnt_axbxc1_437), + .Q(plm_v4f_mgt_reg_dcm_cnt[1]), + .CLR(plm_v4f_mgt_sys_rst_n_i) + ); + FDPE plm_v4f_mgt_reg_dcm ( + .PRE(plm_v4f_mgt_sys_rst_n_i), + .CE(plm_v4f_mgt_dcm_delay_reg_dcm9_438), + .C(plm_v4f_mgt_special_clk), + .D(plm_v4f_mgt_lstate_support[3]), + .Q(plm_v4f_mgt_reg_dcm_439) + ); + FDPE plm_v4f_mgt_reg_pma ( + .PRE(plm_v4f_mgt_dcm_lock_i_442), + .CE(plm_v4f_mgt_pma_delay_reg_pma9_440), + .C(plm_v4f_mgt_special_clk), + .D(plm_v4f_mgt_lstate_support[3]), + .Q(plm_v4f_mgt_reg_pma_441) + ); + INV plm_v4f_mgt_dcm_lock_i ( + .I(plm_v4f_mgt_dcm_lock), + .O(plm_v4f_mgt_dcm_lock_i_442) + ); + INV plm_v4f_mgt_I_317 ( + .I(sys_reset_n), + .O(plm_v4f_mgt_sys_rst_n_i) + ); + INV plm_v4f_mgt_un1_reg_plm_rst_n_2_i_i_0_ ( + .I(plm_v4f_mgt_un1_reg_plm_rst_n_2_i[0]), + .O(plm_v4f_mgt_un1_reg_plm_rst_n_2_i_i[0]) + ); + INV plm_v4f_mgt_N_1151_i ( + .I(plm_v4f_mgt_G_342_444), + .O(plm_v4f_mgt_N_1151_i_443) + ); + SRLC16 plm_v4f_mgt_reg_tee_dlyline_I_2 ( + .D(plm_v4f_mgt_reg_tee_dlyline_tmp_array_1[0]), + .Q(plm_v4f_mgt_reg_tee_dlyline_tmp_d_array_1[0]), + .CLK(mgt_clk), + .Q15(NLW_plm_v4f_mgt_reg_tee_dlyline_I_2_Q15_UNCONNECTED), + .A0(plm_v4f_mgt_pipe_phystatus), + .A1(plm_v4f_mgt_lstate_support[3]), + .A2(plm_v4f_mgt_lstate_support[3]), + .A3(plm_v4f_mgt_lstate_support[3]) + ); + SRLC16 plm_v4f_mgt_reg_tee_dlyline_I_1 ( + .D(plm_tx0_txinhibit), + .Q(NLW_plm_v4f_mgt_reg_tee_dlyline_I_1_Q_UNCONNECTED), + .CLK(mgt_clk), + .Q15(plm_v4f_mgt_reg_tee_dlyline_tmp_array_1[0]), + .A0(plm_v4f_mgt_pipe_phystatus), + .A1(plm_v4f_mgt_pipe_phystatus), + .A2(plm_v4f_mgt_pipe_phystatus), + .A3(plm_v4f_mgt_pipe_phystatus) + ); + SRL16 plm_v4f_mgt_reg_phase3_0_I_1 ( + .D(plm_v4f_mgt_delta_detect_reg_phase1_3_445), + .Q(plm_v4f_mgt_reg_phase3_0_tmp_d_array_0[0]), + .CLK(mgt_clk), + .A0(plm_v4f_mgt_pipe_phystatus), + .A1(plm_v4f_mgt_lstate_support[3]), + .A2(plm_v4f_mgt_lstate_support[3]), + .A3(plm_v4f_mgt_lstate_support[3]) + ); + defparam plm_v4f_mgt_reg_rst_cnt_qxu_0_0_.INIT = 4'h2; + LUT1_L plm_v4f_mgt_reg_rst_cnt_qxu_0_0_ ( + .I0(plm_v4f_mgt_reg_rst_cnt[0]), + .LO(plm_v4f_mgt_reg_rst_cnt_qxu[0]) + ); + defparam plm_v4f_mgt_reg_rst_cnt_s_0_.INIT = 4'h1; + LUT1_L plm_v4f_mgt_reg_rst_cnt_s_0_ ( + .I0(plm_v4f_mgt_reg_rst_cnt_qxu[0]), + .LO(plm_v4f_mgt_reg_rst_cnt_s[0]) + ); + defparam plm_v4f_mgt_reg_rst_cnt_qxu_0_1_.INIT = 4'h2; + LUT1_L plm_v4f_mgt_reg_rst_cnt_qxu_0_1_ ( + .I0(plm_v4f_mgt_reg_rst_cnt[1]), + .LO(plm_v4f_mgt_reg_rst_cnt_qxu[1]) + ); + defparam plm_v4f_mgt_reg_rst_cnt_qxu_0_2_.INIT = 4'h2; + LUT1_L plm_v4f_mgt_reg_rst_cnt_qxu_0_2_ ( + .I0(plm_v4f_mgt_reg_rst_cnt[2]), + .LO(plm_v4f_mgt_reg_rst_cnt_qxu[2]) + ); + defparam plm_v4f_mgt_reg_rst_cnt_qxu_0_3_.INIT = 4'h2; + LUT1_L plm_v4f_mgt_reg_rst_cnt_qxu_0_3_ ( + .I0(plm_v4f_mgt_reg_rst_cnt[3]), + .LO(plm_v4f_mgt_reg_rst_cnt_qxu[3]) + ); + defparam plm_v4f_mgt_reg_rst_cnt_qxu_0_4_.INIT = 4'h2; + LUT1_L plm_v4f_mgt_reg_rst_cnt_qxu_0_4_ ( + .I0(plm_v4f_mgt_reg_rst_cnt[4]), + .LO(plm_v4f_mgt_reg_rst_cnt_qxu[4]) + ); + defparam plm_v4f_mgt_reg_rst_cnt_qxu_0_5_.INIT = 4'h2; + LUT1_L plm_v4f_mgt_reg_rst_cnt_qxu_0_5_ ( + .I0(plm_v4f_mgt_reg_rst_cnt[5]), + .LO(plm_v4f_mgt_reg_rst_cnt_qxu[5]) + ); + defparam plm_v4f_mgt_reg_rst_cnt_qxu_0_6_.INIT = 4'h2; + LUT1_L plm_v4f_mgt_reg_rst_cnt_qxu_0_6_ ( + .I0(plm_v4f_mgt_reg_rst_cnt[6]), + .LO(plm_v4f_mgt_reg_rst_cnt_qxu[6]) + ); + defparam plm_v4f_mgt_reg_rst_cnt_qxu_0_7_.INIT = 4'h2; + LUT1_L plm_v4f_mgt_reg_rst_cnt_qxu_0_7_ ( + .I0(plm_v4f_mgt_reg_rst_cnt[7]), + .LO(plm_v4f_mgt_reg_rst_cnt_qxu[7]) + ); + defparam plm_v4f_mgt_reg_rst_cnt_qxu_0_8_.INIT = 4'h2; + LUT1_L plm_v4f_mgt_reg_rst_cnt_qxu_0_8_ ( + .I0(plm_v4f_mgt_reg_rst_cnt[8]), + .LO(plm_v4f_mgt_reg_rst_cnt_qxu[8]) + ); + defparam plm_v4f_mgt_reg_rst_cnt_qxu_0_9_.INIT = 4'h2; + LUT1_L plm_v4f_mgt_reg_rst_cnt_qxu_0_9_ ( + .I0(plm_v4f_mgt_reg_rst_cnt[9]), + .LO(plm_v4f_mgt_reg_rst_cnt_qxu[9]) + ); + defparam plm_v4f_mgt_reg_rst_cnt_qxu_0_10_.INIT = 4'h2; + LUT1_L plm_v4f_mgt_reg_rst_cnt_qxu_0_10_ ( + .I0(plm_v4f_mgt_reg_rst_cnt[10]), + .LO(plm_v4f_mgt_reg_rst_cnt_qxu[10]) + ); + defparam plm_v4f_mgt_reg_rst_cnt_qxu_0_11_.INIT = 4'h2; + LUT1_L plm_v4f_mgt_reg_rst_cnt_qxu_0_11_ ( + .I0(plm_v4f_mgt_reg_rst_cnt[11]), + .LO(plm_v4f_mgt_reg_rst_cnt_qxu[11]) + ); + defparam plm_v4f_mgt_reg_rst_cnt_qxu_0_12_.INIT = 4'h2; + LUT1_L plm_v4f_mgt_reg_rst_cnt_qxu_0_12_ ( + .I0(plm_v4f_mgt_reg_rst_cnt[12]), + .LO(plm_v4f_mgt_reg_rst_cnt_qxu[12]) + ); + defparam plm_v4f_mgt_reg_rst_cnt_qxu_0_13_.INIT = 4'h2; + LUT1_L plm_v4f_mgt_reg_rst_cnt_qxu_0_13_ ( + .I0(plm_v4f_mgt_reg_rst_cnt[13]), + .LO(plm_v4f_mgt_reg_rst_cnt_qxu[13]) + ); + defparam plm_v4f_mgt_reg_rst_cnt_qxu_0_14_.INIT = 4'h2; + LUT1_L plm_v4f_mgt_reg_rst_cnt_qxu_0_14_ ( + .I0(plm_v4f_mgt_reg_rst_cnt[14]), + .LO(plm_v4f_mgt_reg_rst_cnt_qxu[14]) + ); + VCC plm_v4f_mgt_gt11_by1_VCC ( + .P(plm_v4f_mgt_gt11_by1_VCC_446) + ); + GND plm_v4f_mgt_gt11_by1_GND ( + .G(plm_v4f_mgt_gt11_by1_GND_447) + ); + defparam plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST.MCOMMA_32B_VALUE = 32'h00000283; + defparam plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST.PCOMMA_32B_VALUE = 32'h0000017C; + defparam plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST.RXCTRL1 = 12'h200; + defparam plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST.RXCPSEL = "FALSE"; + defparam plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST.RXDIGRX = "FALSE"; + defparam plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST.RXLOOPFILT = 4'b1111; + defparam plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST.RXPLLNDIVSEL = 20; + defparam plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST.RXOUTDIV2SEL = 4; + defparam plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST.TXPD = "FALSE"; + defparam plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST.TXDAT_TAP_DAC = 5'b01010; + defparam plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST.TXPOST_TAP_DAC = 5'b00000; + defparam plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST.TXPOST_TAP_PD = "FALSE"; + defparam plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST.TXDAT_PRDRV_DAC = 3'b111; + defparam plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST.TXPOST_PRDRV_DAC = 3'b111; + defparam plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST.TXSLEWRATE = "TRUE"; + defparam plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST.TXASYNCDIVIDE = 2'b01; + defparam plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST.TXTERMTRIM = 4'b1100; + defparam plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST.TXAREFBIASSEL = "TRUE"; + defparam plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST.TXHIGHSIGNALEN = "TRUE"; + defparam plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST.TXCLKMODE = 4'b0100; + defparam plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST.TXPRE_TAP_DAC = 5'b00000; + defparam plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST.TXPRE_TAP_PD = "TRUE"; + defparam plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST.TXPRE_PRDRV_DAC = 3'b111; + defparam plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST.TXCTRL1 = 12'h200; + defparam plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST.TXCPSEL = "FALSE"; + defparam plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST.TXLOOPFILT = 4'b0101; + defparam plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST.TXPLLNDIVSEL = 20; + defparam plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST.TXOUTDIV2SEL = 4; + defparam plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST.RXEQ = 64'h4000000000000000; + defparam plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST.RXPD = "FALSE"; + defparam plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST.RXDIGRESET = "FALSE"; + defparam plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST.RXLKADJ = 5'b00000; + defparam plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST.RXDCCOUPLE = "FALSE"; + defparam plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST.RXCDRLOS = 6'b001100; + defparam plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST.RXAFEEQ = 9'b000000111; + defparam plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST.RXRCPADJ = 3'b010; + defparam plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST.RXLB = "FALSE"; + defparam plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST.RXCLKMODE = 6'b000011; + defparam plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST.RXASYNCDIVIDE = 2'b01; + defparam plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST.PMA_BIT_SLIP = "FALSE"; + defparam plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST.PMACOREPWRENABLE = "TRUE"; + defparam plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST.PMACLKENABLE = "TRUE"; + defparam plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST.TXPHASESEL = "FALSE"; + defparam plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST.BANDGAPSEL = "FALSE"; + defparam plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST.TXABPMACLKSEL = "REFCLK1"; + defparam plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST.RXPMACLKSEL = "REFCLK1"; + defparam plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST.RXRECCLK1_USE_SYNC = "FALSE"; + defparam plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST.TXOUTCLK1_USE_SYNC = "FALSE"; + defparam plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST.TXCLK0_FORCE_PMACLK = "TRUE"; + defparam plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST.RXCLK0_FORCE_PMACLK = "TRUE"; + defparam plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST.TX_CLOCK_DIVIDER = 2'b01; + defparam plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST.RX_CLOCK_DIVIDER = 2'b01; + defparam plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST.TXCRCENABLE = "TRUE"; + defparam plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST.TXCRCINITVAL = 32'hFFFFFFFF; + defparam plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST.TXCRCSAMECLOCK = "TRUE"; + defparam plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST.TXCRCINVERTGEN = "FALSE"; + defparam plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST.TXCRCCLOCKDOUBLE = "FALSE"; + defparam plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST.RXCRCINITVAL = 32'hFFFFFFFF; + defparam plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST.RXCRCENABLE = "TRUE"; + defparam plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST.RXCRCSAMECLOCK = "TRUE"; + defparam plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST.RXCRCINVERTGEN = "FALSE"; + defparam plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST.RXCRCCLOCKDOUBLE = "FALSE"; + defparam plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST.VCODAC_INIT = 10'b0000000000; + defparam plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST.SLOWDOWN_CAL = 2'b00; + defparam plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST.LOOPCAL_WAIT = 2'b00; + defparam plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST.FDET_HYS_CAL = 3'b010; + defparam plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST.FDET_LCK_CAL = 3'b101; + defparam plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST.FDET_HYS_SEL = 3'b001; + defparam plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST.FDET_LCK_SEL = 3'b111; + defparam plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST.VCO_CTRL_ENABLE = "TRUE"; + defparam plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST.CYCLE_LIMIT_SEL = 2'b00; + defparam plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST.RXVCODAC_INIT = 10'b0000000000; + defparam plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST.RXSLOWDOWN_CAL = 2'b00; + defparam plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST.RXLOOPCAL_WAIT = 2'b00; + defparam plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST.RXFDET_HYS_CAL = 3'b010; + defparam plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST.RXFDET_LCK_CAL = 3'b101; + defparam plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST.RXFDET_HYS_SEL = 3'b001; + defparam plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST.RXFDET_LCK_SEL = 3'b100; + defparam plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST.RXVCO_CTRL_ENABLE = "TRUE"; + defparam plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST.RXCYCLE_LIMIT_SEL = 2'b00; + defparam plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST.RXFDCAL_CLOCK_DIVIDE = "NONE"; + defparam plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST.TXFDCAL_CLOCK_DIVIDE = "NONE"; + defparam plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST.BIASRESSEL = "FALSE"; + defparam plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST.RXPDDTST = "TRUE"; + defparam plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST.RXCMADJ = 2'b01; + defparam plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST.RXBY_32 = "FALSE"; + defparam plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST.REPEATER = "FALSE"; + defparam plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST.ENABLE_DCDR = "FALSE"; + defparam plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST.SAMPLE_8X = "FALSE"; + defparam plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST.DCDR_FILTER = 3'b010; + defparam plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST.RXUSRDIVISOR = 1; + defparam plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST.COMMA_10B_MASK = 12'h3FF; + defparam plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST.PCOMMA_DETECT = "TRUE"; + defparam plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST.MCOMMA_DETECT = "TRUE"; + defparam plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST.DEC_VALID_COMMA_ONLY = "TRUE"; + defparam plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST.DEC_PCOMMA_DETECT = "TRUE"; + defparam plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST.DEC_MCOMMA_DETECT = "TRUE"; + defparam plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST.ALIGN_COMMA_WORD = 1; + defparam plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST.CLK_COR_8B10B_DE = "TRUE"; + defparam plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST.CLK_CORRECT_USE = "TRUE"; + defparam plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST.CLK_COR_SEQ_LEN = 4; + defparam plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST.CLK_COR_SEQ_DROP = "FALSE"; + defparam plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST.CLK_COR_SEQ_2_USE = "FALSE"; + defparam plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST.CLK_COR_MAX_LAT = 44; + defparam plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST.CLK_COR_SEQ_2_MASK = 4'b1110; + defparam plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST.CLK_COR_SEQ_2_4 = 11'b00000000000; + defparam plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST.CLK_COR_SEQ_2_3 = 11'b00000000000; + defparam plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST.CLK_COR_SEQ_2_2 = 11'b00000000000; + defparam plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST.CLK_COR_SEQ_2_1 = 11'b00000000000; + defparam plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST.RXDATA_SEL = 2'b00; + defparam plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST.TXDATA_SEL = 2'b00; + defparam plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST.CLK_COR_MIN_LAT = 36; + defparam plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST.PCS_BIT_SLIP = "FALSE"; + defparam plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST.DIGRX_FWDCLK = 2'b00; + defparam plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST.DIGRX_SYNC_MODE = "FALSE"; + defparam plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST.CLK_COR_SEQ_1_MASK = 4'b0000; + defparam plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST.CLK_COR_SEQ_1_4 = 11'b00100011100; + defparam plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST.CLK_COR_SEQ_1_3 = 11'b00100011100; + defparam plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST.CLK_COR_SEQ_1_2 = 11'b00100011100; + defparam plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST.CLK_COR_SEQ_1_1 = 11'b00110111100; + defparam plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST.CCCB_ARBITRATOR_DISABLE = "FALSE"; + defparam plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST.OPPOSITE_SELECT = "FALSE"; + defparam plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST.POWER_ENABLE = "TRUE"; + defparam plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST.CHAN_BOND_SEQ_2_MASK = 4'b0000; + defparam plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST.CHAN_BOND_SEQ_2_4 = 11'b00000000000; + defparam plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST.CHAN_BOND_SEQ_2_3 = 11'b00000000000; + defparam plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST.CHAN_BOND_SEQ_2_2 = 11'b00000000000; + defparam plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST.CHAN_BOND_SEQ_2_1 = 11'b00000000000; + defparam plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST.TX_BUFFER_USE = "TRUE"; + defparam plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST.RX_BUFFER_USE = "TRUE"; + defparam plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST.CHAN_BOND_SEQ_LEN = 4; + defparam plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST.CHAN_BOND_SEQ_2_USE = "FALSE"; + defparam plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST.CHAN_BOND_ONE_SHOT = "FALSE"; + defparam plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST.CHAN_BOND_MODE = "NONE"; + defparam plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST.CHAN_BOND_LIMIT = 6; + defparam plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST.CHAN_BOND_SEQ_1_MASK = 4'b0000; + defparam plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST.CHAN_BOND_SEQ_1_4 = 11'b00110111100; + defparam plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST.CHAN_BOND_SEQ_1_3 = 11'b00001000101; + defparam plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST.CHAN_BOND_SEQ_1_2 = 11'b00001000101; + defparam plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST.CHAN_BOND_SEQ_1_1 = 11'b00001000101; + defparam plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST.GT11_MODE = "A"; + GT11 plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST ( + .RXCRCPD(plm_v4f_mgt_gt11_by1_VCC_446), + .RXBUFERR(NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST_RXBUFERR_UNCONNECTED), + .TXSYNC(plm_v4f_mgt_reg_tx_sync_426), + .POWERDOWN(plm_v4f_mgt_gt11_by1_GND_447), + .TXUSRCLK2(mgt_clk), + .ENPCOMMAALIGN(plm_v4f_mgt_gt11_by1_VCC_446), + .RXPOLARITY(plm_rx0_polarity), + .ENMCOMMAALIGN(plm_v4f_mgt_gt11_by1_VCC_446), + .TXBUFERR(NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST_TXBUFERR_UNCONNECTED), + .TXCRCPD(plm_v4f_mgt_gt11_by1_VCC_446), + .RXSIGDET(plm_v4f_mgt_rx_sigdet_n_async), + .TXCLKSTABLE(plm_v4f_mgt_gt11_by1_VCC_446), + .RXUSRCLK2(mgt_clk), + .TXPOLARITY(plm_v4f_mgt_gt11_by1_GND_447), + .DWE(plm_v4f_mgt_gt0_dwe), + .RXREALIGN(NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST_RXREALIGN_UNCONNECTED), + .TXGEARBOX64B66BUSE(plm_v4f_mgt_gt11_by1_GND_447), + .RXCYCLELIMIT(NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST_RXCYCLELIMIT_UNCONNECTED), + .RXRESET(plm_v4f_mgt_reg_rx_pcs_init_431), + .TXCYCLELIMIT(NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST_TXCYCLELIMIT_UNCONNECTED), + .TXCALFAIL(NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST_TXCALFAIL_UNCONNECTED), + .RXUSRCLK(mgt_clk), + .RXDEC64B66BUSE(plm_v4f_mgt_gt11_by1_GND_447), + .RXPCSHCLKOUT(NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST_RXPCSHCLKOUT_UNCONNECTED), + .TXPCSHCLKOUT(NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST_TXPCSHCLKOUT_UNCONNECTED), + .RXCOMMADETUSE(plm_v4f_mgt_gt11_by1_VCC_446), + .DCLK(NlwRenamedSig_OI_trn_clk), + .TXCRCINIT(plm_v4f_mgt_gt11_by1_GND_447), + .TXUSRCLK(mgt_clk), + .RXCALFAIL(NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST_RXCALFAIL_UNCONNECTED), + .RXPMARESET(plm_v4f_mgt_reg_pma_441), + .RX1N(pci_exp_rxn_5056[0]), + .RX1P(pci_exp_rxp_5055[0]), + .TXRESET(plm_v4f_mgt_reg_tx_pcs_init_427), + .RXSLIDE(plm_v4f_mgt_gt11_by1_GND_447), + .TXPMARESET(plm_v4f_mgt_reg_pma_441), + .TXCRCINTCLK(plm_v4f_mgt_gt11_by1_GND_447), + .RXCRCINIT(plm_v4f_mgt_gt11_by1_GND_447), + .RXDEC8B10BUSE(plm_v4f_mgt_gt11_by1_VCC_446), + .RXCLKSTABLE(plm_v4f_mgt_gt11_by1_VCC_446), + .RXLOCK(plm_v4f_mgt_pma_rxlock0), + .TXCRCDATAVALID(plm_v4f_mgt_gt11_by1_GND_447), + .GREFCLK(NlwRenamedSig_OI_trn_clk), + .ENCHANSYNC(plm_v4f_mgt_gt11_by1_GND_447), + .DEN(plm_v4f_mgt_gt0_den), + .RXMCLK(NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST_RXMCLK_UNCONNECTED), + .RXCOMMADET(NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST_RXCOMMADET_UNCONNECTED), + .TXOUTCLK1(NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST_TXOUTCLK1_UNCONNECTED), + .TXOUTCLK2(NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST_TXOUTCLK2_UNCONNECTED), + .RXCRCRESET(plm_v4f_mgt_gt11_by1_VCC_446), + .RXCRCCLK(plm_v4f_mgt_gt11_by1_GND_447), + .TXENC64B66BUSE(plm_v4f_mgt_gt11_by1_GND_447), + .TXINHIBIT(plm_v4f_mgt_gt11_by1_GND_447), + .RXRECCLK1(NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST_RXRECCLK1_UNCONNECTED), + .RXRECCLK2(NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST_RXRECCLK2_UNCONNECTED), + .TXLOCK(plm_v4f_mgt_pma_txlock0), + .TXCRCRESET(plm_v4f_mgt_gt11_by1_VCC_446), + .RXDESCRAM64B66BUSE(plm_v4f_mgt_gt11_by1_GND_447), + .RXBLOCKSYNC64B66BUSE(plm_v4f_mgt_gt11_by1_GND_447), + .RXIGNOREBTF(plm_v4f_mgt_gt11_by1_GND_447), + .TXCRCCLK(plm_v4f_mgt_gt11_by1_GND_447), + .RXCRCDATAVALID(plm_v4f_mgt_gt11_by1_GND_447), + .TXSCRAM64B66BUSE(plm_v4f_mgt_gt11_by1_GND_447), + .RXCRCINTCLK(plm_v4f_mgt_gt11_by1_GND_447), + .RXSYNC(plm_v4f_mgt_gt11_by1_GND_447), + .DRDY(plm_v4f_mgt_gt0_drdy), + .TXENC8B10BUSE(plm_v4f_mgt_gt11_by1_VCC_446), + .REFCLK1(sys_clkz), + .TXENOOB(plm_v4f_mgt_reg_tee_dlyline[18]), + .REFCLK2(plm_v4f_mgt_gt11_by1_GND_447), + .TX1N(pci_exp_txn_5054[0]), + .TX1P(pci_exp_txp_5053[0]), + .RXSTATUS({NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST_RXSTATUS_5__UNCONNECTED, +NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST_RXSTATUS_4__UNCONNECTED, NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST_RXSTATUS_3__UNCONNECTED, +NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST_RXSTATUS_2__UNCONNECTED, NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST_RXSTATUS_1__UNCONNECTED, +NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST_RXSTATUS_0__UNCONNECTED}), + .RXNOTINTABLE({NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST_RXNOTINTABLE_7__UNCONNECTED, +NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST_RXNOTINTABLE_6__UNCONNECTED, NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST_RXNOTINTABLE_5__UNCONNECTED, +NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST_RXNOTINTABLE_4__UNCONNECTED, NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST_RXNOTINTABLE_3__UNCONNECTED, +NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST_RXNOTINTABLE_2__UNCONNECTED, plm_v4f_mgt_RXNOTINTABLE_0[1], plm_v4f_mgt_RXNOTINTABLE_0[0]}), + .DADDR({plm_v4f_mgt_gt11_by1_GND_447, plm_v4f_mgt_gt11_by1_VCC_446, plm_v4f_mgt_gt0_daddr[5], plm_v4f_mgt_gt0_daddr[4], plm_v4f_mgt_gt0_daddr[3], +plm_v4f_mgt_gt0_daddr[2], plm_v4f_mgt_gt0_daddr[1], plm_v4f_mgt_gt0_daddr[4]}), + .TXDATAWIDTH({plm_v4f_mgt_gt11_by1_GND_447, plm_v4f_mgt_gt11_by1_VCC_446}), + .RXCRCOUT({NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST_RXCRCOUT_31__UNCONNECTED, +NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST_RXCRCOUT_30__UNCONNECTED, NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST_RXCRCOUT_29__UNCONNECTED, +NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST_RXCRCOUT_28__UNCONNECTED, NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST_RXCRCOUT_27__UNCONNECTED, +NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST_RXCRCOUT_26__UNCONNECTED, NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST_RXCRCOUT_25__UNCONNECTED, +NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST_RXCRCOUT_24__UNCONNECTED, NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST_RXCRCOUT_23__UNCONNECTED, +NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST_RXCRCOUT_22__UNCONNECTED, NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST_RXCRCOUT_21__UNCONNECTED, +NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST_RXCRCOUT_20__UNCONNECTED, NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST_RXCRCOUT_19__UNCONNECTED, +NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST_RXCRCOUT_18__UNCONNECTED, NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST_RXCRCOUT_17__UNCONNECTED, +NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST_RXCRCOUT_16__UNCONNECTED, NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST_RXCRCOUT_15__UNCONNECTED, +NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST_RXCRCOUT_14__UNCONNECTED, NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST_RXCRCOUT_13__UNCONNECTED, +NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST_RXCRCOUT_12__UNCONNECTED, NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST_RXCRCOUT_11__UNCONNECTED, +NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST_RXCRCOUT_10__UNCONNECTED, NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST_RXCRCOUT_9__UNCONNECTED, +NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST_RXCRCOUT_8__UNCONNECTED, NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST_RXCRCOUT_7__UNCONNECTED, +NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST_RXCRCOUT_6__UNCONNECTED, NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST_RXCRCOUT_5__UNCONNECTED, +NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST_RXCRCOUT_4__UNCONNECTED, NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST_RXCRCOUT_3__UNCONNECTED, +NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST_RXCRCOUT_2__UNCONNECTED, NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST_RXCRCOUT_1__UNCONNECTED, +NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST_RXCRCOUT_0__UNCONNECTED}), + .TXINTDATAWIDTH({plm_v4f_mgt_gt11_by1_VCC_446, plm_v4f_mgt_gt11_by1_VCC_446}), + .DI({plm_v4f_mgt_gt0_do[15], plm_v4f_mgt_gt0_do[14], plm_v4f_mgt_gt0_do[13], plm_v4f_mgt_gt0_do[12], plm_v4f_mgt_gt0_do[11], +plm_v4f_mgt_gt0_do[10], plm_v4f_mgt_gt0_do[9], plm_v4f_mgt_gt0_do[8], plm_v4f_mgt_gt0_do[7], plm_v4f_mgt_gt0_do[6], plm_v4f_mgt_gt0_do[5], +plm_v4f_mgt_gt0_do[4], plm_v4f_mgt_gt0_do[3], plm_v4f_mgt_gt0_do[2], plm_v4f_mgt_gt0_do[1], plm_v4f_mgt_gt0_do[0]}), + .DO({plm_v4f_mgt_gt0_di[15], plm_v4f_mgt_gt0_di[14], plm_v4f_mgt_gt0_di[13], plm_v4f_mgt_gt0_di[12], plm_v4f_mgt_gt0_di[11], +plm_v4f_mgt_gt0_di[10], plm_v4f_mgt_gt0_di[9], plm_v4f_mgt_gt0_di[8], plm_v4f_mgt_gt0_di[7], plm_v4f_mgt_gt0_di[6], plm_v4f_mgt_gt0_di[5], +plm_v4f_mgt_gt0_di[4], plm_v4f_mgt_gt0_di[3], plm_v4f_mgt_gt0_di[2], plm_v4f_mgt_gt0_di[1], plm_v4f_mgt_gt0_di[0]}), + .TXCRCOUT({NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST_TXCRCOUT_31__UNCONNECTED, +NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST_TXCRCOUT_30__UNCONNECTED, NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST_TXCRCOUT_29__UNCONNECTED, +NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST_TXCRCOUT_28__UNCONNECTED, NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST_TXCRCOUT_27__UNCONNECTED, +NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST_TXCRCOUT_26__UNCONNECTED, NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST_TXCRCOUT_25__UNCONNECTED, +NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST_TXCRCOUT_24__UNCONNECTED, NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST_TXCRCOUT_23__UNCONNECTED, +NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST_TXCRCOUT_22__UNCONNECTED, NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST_TXCRCOUT_21__UNCONNECTED, +NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST_TXCRCOUT_20__UNCONNECTED, NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST_TXCRCOUT_19__UNCONNECTED, +NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST_TXCRCOUT_18__UNCONNECTED, NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST_TXCRCOUT_17__UNCONNECTED, +NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST_TXCRCOUT_16__UNCONNECTED, NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST_TXCRCOUT_15__UNCONNECTED, +NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST_TXCRCOUT_14__UNCONNECTED, NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST_TXCRCOUT_13__UNCONNECTED, +NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST_TXCRCOUT_12__UNCONNECTED, NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST_TXCRCOUT_11__UNCONNECTED, +NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST_TXCRCOUT_10__UNCONNECTED, NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST_TXCRCOUT_9__UNCONNECTED, +NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST_TXCRCOUT_8__UNCONNECTED, NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST_TXCRCOUT_7__UNCONNECTED, +NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST_TXCRCOUT_6__UNCONNECTED, NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST_TXCRCOUT_5__UNCONNECTED, +NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST_TXCRCOUT_4__UNCONNECTED, NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST_TXCRCOUT_3__UNCONNECTED, +NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST_TXCRCOUT_2__UNCONNECTED, NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST_TXCRCOUT_1__UNCONNECTED, +NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST_TXCRCOUT_0__UNCONNECTED}), + .COMBUSIN({plm_v4f_mgt_gt11_by1_COMBUSOUT_BLK2[15], plm_v4f_mgt_gt11_by1_COMBUSOUT_BLK2[14], plm_v4f_mgt_gt11_by1_COMBUSOUT_BLK2[13], +plm_v4f_mgt_gt11_by1_COMBUSOUT_BLK2[12], plm_v4f_mgt_gt11_by1_COMBUSOUT_BLK2[11], plm_v4f_mgt_gt11_by1_COMBUSOUT_BLK2[10], +plm_v4f_mgt_gt11_by1_COMBUSOUT_BLK2[9], plm_v4f_mgt_gt11_by1_COMBUSOUT_BLK2[8], plm_v4f_mgt_gt11_by1_COMBUSOUT_BLK2[7], +plm_v4f_mgt_gt11_by1_COMBUSOUT_BLK2[6], plm_v4f_mgt_gt11_by1_COMBUSOUT_BLK2[5], plm_v4f_mgt_gt11_by1_COMBUSOUT_BLK2[4], +plm_v4f_mgt_gt11_by1_COMBUSOUT_BLK2[3], plm_v4f_mgt_gt11_by1_COMBUSOUT_BLK2[2], plm_v4f_mgt_gt11_by1_COMBUSOUT_BLK2[1], +plm_v4f_mgt_gt11_by1_COMBUSOUT_BLK2[0]}), + .COMBUSOUT({plm_v4f_mgt_gt11_by1_COMBUSOUT[15], plm_v4f_mgt_gt11_by1_COMBUSOUT[14], plm_v4f_mgt_gt11_by1_COMBUSOUT[13], +plm_v4f_mgt_gt11_by1_COMBUSOUT[12], plm_v4f_mgt_gt11_by1_COMBUSOUT[11], plm_v4f_mgt_gt11_by1_COMBUSOUT[10], plm_v4f_mgt_gt11_by1_COMBUSOUT[9], +plm_v4f_mgt_gt11_by1_COMBUSOUT[8], plm_v4f_mgt_gt11_by1_COMBUSOUT[7], plm_v4f_mgt_gt11_by1_COMBUSOUT[6], plm_v4f_mgt_gt11_by1_COMBUSOUT[5], +plm_v4f_mgt_gt11_by1_COMBUSOUT[4], plm_v4f_mgt_gt11_by1_COMBUSOUT[3], plm_v4f_mgt_gt11_by1_COMBUSOUT[2], plm_v4f_mgt_gt11_by1_COMBUSOUT[1], +plm_v4f_mgt_gt11_by1_COMBUSOUT[0]}), + .RXDATA({NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST_RXDATA_63__UNCONNECTED, NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST_RXDATA_62__UNCONNECTED, +NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST_RXDATA_61__UNCONNECTED, NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST_RXDATA_60__UNCONNECTED, +NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST_RXDATA_59__UNCONNECTED, NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST_RXDATA_58__UNCONNECTED, +NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST_RXDATA_57__UNCONNECTED, NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST_RXDATA_56__UNCONNECTED, +NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST_RXDATA_55__UNCONNECTED, NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST_RXDATA_54__UNCONNECTED, +NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST_RXDATA_53__UNCONNECTED, NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST_RXDATA_52__UNCONNECTED, +NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST_RXDATA_51__UNCONNECTED, NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST_RXDATA_50__UNCONNECTED, +NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST_RXDATA_49__UNCONNECTED, NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST_RXDATA_48__UNCONNECTED, +NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST_RXDATA_47__UNCONNECTED, NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST_RXDATA_46__UNCONNECTED, +NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST_RXDATA_45__UNCONNECTED, NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST_RXDATA_44__UNCONNECTED, +NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST_RXDATA_43__UNCONNECTED, NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST_RXDATA_42__UNCONNECTED, +NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST_RXDATA_41__UNCONNECTED, NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST_RXDATA_40__UNCONNECTED, +NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST_RXDATA_39__UNCONNECTED, NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST_RXDATA_38__UNCONNECTED, +NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST_RXDATA_37__UNCONNECTED, NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST_RXDATA_36__UNCONNECTED, +NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST_RXDATA_35__UNCONNECTED, NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST_RXDATA_34__UNCONNECTED, +NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST_RXDATA_33__UNCONNECTED, NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST_RXDATA_32__UNCONNECTED, +NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST_RXDATA_31__UNCONNECTED, NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST_RXDATA_30__UNCONNECTED, +NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST_RXDATA_29__UNCONNECTED, NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST_RXDATA_28__UNCONNECTED, +NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST_RXDATA_27__UNCONNECTED, NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST_RXDATA_26__UNCONNECTED, +NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST_RXDATA_25__UNCONNECTED, NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST_RXDATA_24__UNCONNECTED, +NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST_RXDATA_23__UNCONNECTED, NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST_RXDATA_22__UNCONNECTED, +NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST_RXDATA_21__UNCONNECTED, NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST_RXDATA_20__UNCONNECTED, +NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST_RXDATA_19__UNCONNECTED, NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST_RXDATA_18__UNCONNECTED, +NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST_RXDATA_17__UNCONNECTED, NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST_RXDATA_16__UNCONNECTED, +plm_rx0_data[7], plm_rx0_data[6], plm_rx0_data[5], plm_rx0_data[4], plm_rx0_data[3], plm_rx0_data[2], plm_rx0_data[1], plm_rx0_data[0], +plm_rx0_data[15], plm_rx0_data[14], plm_rx0_data[13], plm_rx0_data[12], plm_rx0_data[11], plm_rx0_data[10], plm_rx0_data[9], plm_rx0_data[8]}), + .TXRUNDISP({NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST_TXRUNDISP_7__UNCONNECTED, +NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST_TXRUNDISP_6__UNCONNECTED, NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST_TXRUNDISP_5__UNCONNECTED, +NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST_TXRUNDISP_4__UNCONNECTED, NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST_TXRUNDISP_3__UNCONNECTED, +NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST_TXRUNDISP_2__UNCONNECTED, NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST_TXRUNDISP_1__UNCONNECTED, +NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST_TXRUNDISP_0__UNCONNECTED}), + .RXINTDATAWIDTH({plm_v4f_mgt_gt11_by1_VCC_446, plm_v4f_mgt_gt11_by1_VCC_446}), + .RXDATAWIDTH({plm_v4f_mgt_gt11_by1_GND_447, plm_v4f_mgt_gt11_by1_VCC_446}), + .RXLOSSOFSYNC({NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST_RXLOSSOFSYNC_1__UNCONNECTED, +NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST_RXLOSSOFSYNC_0__UNCONNECTED}), + .RXRUNDISP({NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST_RXRUNDISP_7__UNCONNECTED, +NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST_RXRUNDISP_6__UNCONNECTED, NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST_RXRUNDISP_5__UNCONNECTED, +NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST_RXRUNDISP_4__UNCONNECTED, NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST_RXRUNDISP_3__UNCONNECTED, +NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST_RXRUNDISP_2__UNCONNECTED, plm_v4f_mgt_rx_run_disp[0], plm_v4f_mgt_rx_run_disp[1]}), + .TXDATA({plm_v4f_mgt_gt11_by1_GND_447, plm_v4f_mgt_gt11_by1_GND_447, plm_v4f_mgt_gt11_by1_GND_447, plm_v4f_mgt_gt11_by1_GND_447, +plm_v4f_mgt_gt11_by1_GND_447, plm_v4f_mgt_gt11_by1_GND_447, plm_v4f_mgt_gt11_by1_GND_447, plm_v4f_mgt_gt11_by1_GND_447, plm_v4f_mgt_gt11_by1_GND_447, +plm_v4f_mgt_gt11_by1_GND_447, plm_v4f_mgt_gt11_by1_GND_447, plm_v4f_mgt_gt11_by1_GND_447, plm_v4f_mgt_gt11_by1_GND_447, plm_v4f_mgt_gt11_by1_GND_447, +plm_v4f_mgt_gt11_by1_GND_447, plm_v4f_mgt_gt11_by1_GND_447, plm_v4f_mgt_gt11_by1_GND_447, plm_v4f_mgt_gt11_by1_GND_447, plm_v4f_mgt_gt11_by1_GND_447, +plm_v4f_mgt_gt11_by1_GND_447, plm_v4f_mgt_gt11_by1_GND_447, plm_v4f_mgt_gt11_by1_GND_447, plm_v4f_mgt_gt11_by1_GND_447, plm_v4f_mgt_gt11_by1_GND_447, +plm_v4f_mgt_gt11_by1_GND_447, plm_v4f_mgt_gt11_by1_GND_447, plm_v4f_mgt_gt11_by1_GND_447, plm_v4f_mgt_gt11_by1_GND_447, plm_v4f_mgt_gt11_by1_GND_447, +plm_v4f_mgt_gt11_by1_GND_447, plm_v4f_mgt_gt11_by1_GND_447, plm_v4f_mgt_gt11_by1_GND_447, plm_v4f_mgt_gt11_by1_GND_447, plm_v4f_mgt_gt11_by1_GND_447, +plm_v4f_mgt_gt11_by1_GND_447, plm_v4f_mgt_gt11_by1_GND_447, plm_v4f_mgt_gt11_by1_GND_447, plm_v4f_mgt_gt11_by1_GND_447, plm_v4f_mgt_gt11_by1_GND_447, +plm_v4f_mgt_gt11_by1_GND_447, plm_v4f_mgt_gt11_by1_GND_447, plm_v4f_mgt_gt11_by1_GND_447, plm_v4f_mgt_gt11_by1_GND_447, plm_v4f_mgt_gt11_by1_GND_447, +plm_v4f_mgt_gt11_by1_GND_447, plm_v4f_mgt_gt11_by1_GND_447, plm_v4f_mgt_gt11_by1_GND_447, plm_v4f_mgt_gt11_by1_GND_447, plm_tx0_data[7], +plm_tx0_data[6], plm_tx0_data[5], plm_tx0_data[4], plm_tx0_data[3], plm_tx0_data[2], plm_tx0_data[1], plm_tx0_data[0], plm_tx0_data[15], +plm_tx0_data[14], plm_tx0_data[13], plm_tx0_data[12], plm_tx0_data[11], plm_tx0_data[10], plm_tx0_data[9], plm_tx0_data[8]}), + .TXCHARDISPVAL({plm_v4f_mgt_gt11_by1_GND_447, plm_v4f_mgt_gt11_by1_GND_447, plm_v4f_mgt_gt11_by1_GND_447, plm_v4f_mgt_gt11_by1_GND_447, +plm_v4f_mgt_gt11_by1_GND_447, plm_v4f_mgt_gt11_by1_GND_447, plm_GND_393, plm_GND_393}), + .LOOPBACK({plm_v4f_mgt_gt11_by1_GND_447, plm_v4f_mgt_gt11_by1_GND_447}), + .CHBONDI({plm_v4f_mgt_gt11_by1_GND_447, plm_v4f_mgt_gt11_by1_GND_447, plm_v4f_mgt_gt11_by1_GND_447, plm_v4f_mgt_gt11_by1_GND_447, +plm_v4f_mgt_gt11_by1_GND_447}), + .TXCRCDATAWIDTH({plm_v4f_mgt_gt11_by1_GND_447, plm_v4f_mgt_gt11_by1_GND_447, plm_v4f_mgt_gt11_by1_GND_447}), + .CHBONDO({NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST_CHBONDO_4__UNCONNECTED, NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST_CHBONDO_3__UNCONNECTED, +NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST_CHBONDO_2__UNCONNECTED, NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST_CHBONDO_1__UNCONNECTED, +NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST_CHBONDO_0__UNCONNECTED}), + .TXCHARISK({plm_v4f_mgt_gt11_by1_GND_447, plm_v4f_mgt_gt11_by1_GND_447, plm_v4f_mgt_gt11_by1_GND_447, plm_v4f_mgt_gt11_by1_GND_447, +plm_v4f_mgt_gt11_by1_GND_447, plm_v4f_mgt_gt11_by1_GND_447, plm_tx0_char_is_k[0], plm_tx0_char_is_k[1]}), + .TXBYPASS8B10B({plm_v4f_mgt_gt11_by1_GND_447, plm_v4f_mgt_gt11_by1_GND_447, plm_v4f_mgt_gt11_by1_GND_447, plm_v4f_mgt_gt11_by1_GND_447, +plm_v4f_mgt_gt11_by1_GND_447, plm_v4f_mgt_gt11_by1_GND_447, plm_v4f_mgt_gt11_by1_GND_447, plm_v4f_mgt_gt11_by1_GND_447}), + .RXCRCIN({plm_v4f_mgt_gt11_by1_GND_447, plm_v4f_mgt_gt11_by1_GND_447, plm_v4f_mgt_gt11_by1_GND_447, plm_v4f_mgt_gt11_by1_GND_447, +plm_v4f_mgt_gt11_by1_GND_447, plm_v4f_mgt_gt11_by1_GND_447, plm_v4f_mgt_gt11_by1_GND_447, plm_v4f_mgt_gt11_by1_GND_447, plm_v4f_mgt_gt11_by1_GND_447, +plm_v4f_mgt_gt11_by1_GND_447, plm_v4f_mgt_gt11_by1_GND_447, plm_v4f_mgt_gt11_by1_GND_447, plm_v4f_mgt_gt11_by1_GND_447, plm_v4f_mgt_gt11_by1_GND_447, +plm_v4f_mgt_gt11_by1_GND_447, plm_v4f_mgt_gt11_by1_GND_447, plm_v4f_mgt_gt11_by1_GND_447, plm_v4f_mgt_gt11_by1_GND_447, plm_v4f_mgt_gt11_by1_GND_447, +plm_v4f_mgt_gt11_by1_GND_447, plm_v4f_mgt_gt11_by1_GND_447, plm_v4f_mgt_gt11_by1_GND_447, plm_v4f_mgt_gt11_by1_GND_447, plm_v4f_mgt_gt11_by1_GND_447, +plm_v4f_mgt_gt11_by1_GND_447, plm_v4f_mgt_gt11_by1_GND_447, plm_v4f_mgt_gt11_by1_GND_447, plm_v4f_mgt_gt11_by1_GND_447, plm_v4f_mgt_gt11_by1_GND_447, +plm_v4f_mgt_gt11_by1_GND_447, plm_v4f_mgt_gt11_by1_GND_447, plm_v4f_mgt_gt11_by1_GND_447, plm_v4f_mgt_gt11_by1_GND_447, plm_v4f_mgt_gt11_by1_GND_447, +plm_v4f_mgt_gt11_by1_GND_447, plm_v4f_mgt_gt11_by1_GND_447, plm_v4f_mgt_gt11_by1_GND_447, plm_v4f_mgt_gt11_by1_GND_447, plm_v4f_mgt_gt11_by1_GND_447, +plm_v4f_mgt_gt11_by1_GND_447, plm_v4f_mgt_gt11_by1_GND_447, plm_v4f_mgt_gt11_by1_GND_447, plm_v4f_mgt_gt11_by1_GND_447, plm_v4f_mgt_gt11_by1_GND_447, +plm_v4f_mgt_gt11_by1_GND_447, plm_v4f_mgt_gt11_by1_GND_447, plm_v4f_mgt_gt11_by1_GND_447, plm_v4f_mgt_gt11_by1_GND_447, plm_v4f_mgt_gt11_by1_GND_447, +plm_v4f_mgt_gt11_by1_GND_447, plm_v4f_mgt_gt11_by1_GND_447, plm_v4f_mgt_gt11_by1_GND_447, plm_v4f_mgt_gt11_by1_GND_447, plm_v4f_mgt_gt11_by1_GND_447, +plm_v4f_mgt_gt11_by1_GND_447, plm_v4f_mgt_gt11_by1_GND_447, plm_v4f_mgt_gt11_by1_GND_447, plm_v4f_mgt_gt11_by1_GND_447, plm_v4f_mgt_gt11_by1_GND_447, +plm_v4f_mgt_gt11_by1_GND_447, plm_v4f_mgt_gt11_by1_GND_447, plm_v4f_mgt_gt11_by1_GND_447, plm_v4f_mgt_gt11_by1_GND_447, plm_v4f_mgt_gt11_by1_GND_447}) +, + .RXCHARISK({NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST_RXCHARISK_7__UNCONNECTED, +NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST_RXCHARISK_6__UNCONNECTED, NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST_RXCHARISK_5__UNCONNECTED, +NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST_RXCHARISK_4__UNCONNECTED, NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST_RXCHARISK_3__UNCONNECTED, +NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST_RXCHARISK_2__UNCONNECTED, plm_rx0_char_is_k[0], plm_rx0_char_is_k[1]}), + .TXCHARDISPMODE({plm_v4f_mgt_gt11_by1_GND_447, plm_v4f_mgt_gt11_by1_GND_447, plm_v4f_mgt_gt11_by1_GND_447, plm_v4f_mgt_gt11_by1_GND_447, +plm_v4f_mgt_gt11_by1_GND_447, plm_v4f_mgt_gt11_by1_GND_447, plm_GND_393, plm_GND_393}), + .RXCRCDATAWIDTH({plm_v4f_mgt_gt11_by1_GND_447, plm_v4f_mgt_gt11_by1_GND_447, plm_v4f_mgt_gt11_by1_GND_447}), + .RXDISPERR({NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST_RXDISPERR_7__UNCONNECTED, +NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST_RXDISPERR_6__UNCONNECTED, NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST_RXDISPERR_5__UNCONNECTED, +NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST_RXDISPERR_4__UNCONNECTED, NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST_RXDISPERR_3__UNCONNECTED, +NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST_RXDISPERR_2__UNCONNECTED, plm_v4f_mgt_rx_disp_err[0], plm_v4f_mgt_rx_disp_err[1]}), + .RXCHARISCOMMA({NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST_RXCHARISCOMMA_7__UNCONNECTED, +NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST_RXCHARISCOMMA_6__UNCONNECTED, NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST_RXCHARISCOMMA_5__UNCONNECTED, +NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST_RXCHARISCOMMA_4__UNCONNECTED, NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST_RXCHARISCOMMA_3__UNCONNECTED, +NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST_RXCHARISCOMMA_2__UNCONNECTED, NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST_RXCHARISCOMMA_1__UNCONNECTED, +NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST_RXCHARISCOMMA_0__UNCONNECTED}), + .TXCRCIN({plm_v4f_mgt_gt11_by1_GND_447, plm_v4f_mgt_gt11_by1_GND_447, plm_v4f_mgt_gt11_by1_GND_447, plm_v4f_mgt_gt11_by1_GND_447, +plm_v4f_mgt_gt11_by1_GND_447, plm_v4f_mgt_gt11_by1_GND_447, plm_v4f_mgt_gt11_by1_GND_447, plm_v4f_mgt_gt11_by1_GND_447, plm_v4f_mgt_gt11_by1_GND_447, +plm_v4f_mgt_gt11_by1_GND_447, plm_v4f_mgt_gt11_by1_GND_447, plm_v4f_mgt_gt11_by1_GND_447, plm_v4f_mgt_gt11_by1_GND_447, plm_v4f_mgt_gt11_by1_GND_447, +plm_v4f_mgt_gt11_by1_GND_447, plm_v4f_mgt_gt11_by1_GND_447, plm_v4f_mgt_gt11_by1_GND_447, plm_v4f_mgt_gt11_by1_GND_447, plm_v4f_mgt_gt11_by1_GND_447, +plm_v4f_mgt_gt11_by1_GND_447, plm_v4f_mgt_gt11_by1_GND_447, plm_v4f_mgt_gt11_by1_GND_447, plm_v4f_mgt_gt11_by1_GND_447, plm_v4f_mgt_gt11_by1_GND_447, +plm_v4f_mgt_gt11_by1_GND_447, plm_v4f_mgt_gt11_by1_GND_447, plm_v4f_mgt_gt11_by1_GND_447, plm_v4f_mgt_gt11_by1_GND_447, plm_v4f_mgt_gt11_by1_GND_447, +plm_v4f_mgt_gt11_by1_GND_447, plm_v4f_mgt_gt11_by1_GND_447, plm_v4f_mgt_gt11_by1_GND_447, plm_v4f_mgt_gt11_by1_GND_447, plm_v4f_mgt_gt11_by1_GND_447, +plm_v4f_mgt_gt11_by1_GND_447, plm_v4f_mgt_gt11_by1_GND_447, plm_v4f_mgt_gt11_by1_GND_447, plm_v4f_mgt_gt11_by1_GND_447, plm_v4f_mgt_gt11_by1_GND_447, +plm_v4f_mgt_gt11_by1_GND_447, plm_v4f_mgt_gt11_by1_GND_447, plm_v4f_mgt_gt11_by1_GND_447, plm_v4f_mgt_gt11_by1_GND_447, plm_v4f_mgt_gt11_by1_GND_447, +plm_v4f_mgt_gt11_by1_GND_447, plm_v4f_mgt_gt11_by1_GND_447, plm_v4f_mgt_gt11_by1_GND_447, plm_v4f_mgt_gt11_by1_GND_447, plm_v4f_mgt_gt11_by1_GND_447, +plm_v4f_mgt_gt11_by1_GND_447, plm_v4f_mgt_gt11_by1_GND_447, plm_v4f_mgt_gt11_by1_GND_447, plm_v4f_mgt_gt11_by1_GND_447, plm_v4f_mgt_gt11_by1_GND_447, +plm_v4f_mgt_gt11_by1_GND_447, plm_v4f_mgt_gt11_by1_GND_447, plm_v4f_mgt_gt11_by1_GND_447, plm_v4f_mgt_gt11_by1_GND_447, plm_v4f_mgt_gt11_by1_GND_447, +plm_v4f_mgt_gt11_by1_GND_447, plm_v4f_mgt_gt11_by1_GND_447, plm_v4f_mgt_gt11_by1_GND_447, plm_v4f_mgt_gt11_by1_GND_447, plm_v4f_mgt_gt11_by1_GND_447}) +, + .TXKERR({NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST_TXKERR_7__UNCONNECTED, NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST_TXKERR_6__UNCONNECTED, +NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST_TXKERR_5__UNCONNECTED, NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST_TXKERR_4__UNCONNECTED, +NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST_TXKERR_3__UNCONNECTED, NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST_TXKERR_2__UNCONNECTED, +NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST_TXKERR_1__UNCONNECTED, NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST_TXKERR_0__UNCONNECTED}) + ); + defparam plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2.MCOMMA_32B_VALUE = 32'h00000283; + defparam plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2.PCOMMA_32B_VALUE = 32'h0000017C; + defparam plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2.RXCTRL1 = 12'h200; + defparam plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2.RXCPSEL = "FALSE"; + defparam plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2.RXDIGRX = "FALSE"; + defparam plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2.RXLOOPFILT = 4'b1111; + defparam plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2.RXPLLNDIVSEL = 20; + defparam plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2.RXOUTDIV2SEL = 4; + defparam plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2.TXPD = "FALSE"; + defparam plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2.TXDAT_TAP_DAC = 5'b01010; + defparam plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2.TXPOST_TAP_DAC = 5'b00000; + defparam plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2.TXPOST_TAP_PD = "FALSE"; + defparam plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2.TXDAT_PRDRV_DAC = 3'b111; + defparam plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2.TXPOST_PRDRV_DAC = 3'b111; + defparam plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2.TXSLEWRATE = "TRUE"; + defparam plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2.TXASYNCDIVIDE = 2'b01; + defparam plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2.TXTERMTRIM = 4'b1100; + defparam plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2.TXAREFBIASSEL = "TRUE"; + defparam plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2.TXHIGHSIGNALEN = "TRUE"; + defparam plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2.TXCLKMODE = 4'b0100; + defparam plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2.TXPRE_TAP_DAC = 5'b00000; + defparam plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2.TXPRE_TAP_PD = "TRUE"; + defparam plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2.TXPRE_PRDRV_DAC = 3'b111; + defparam plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2.TXCTRL1 = 12'h200; + defparam plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2.TXCPSEL = "FALSE"; + defparam plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2.TXLOOPFILT = 4'b0101; + defparam plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2.TXPLLNDIVSEL = 20; + defparam plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2.TXOUTDIV2SEL = 4; + defparam plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2.RXEQ = 64'h4000000000000000; + defparam plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2.RXPD = "FALSE"; + defparam plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2.RXDIGRESET = "FALSE"; + defparam plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2.RXLKADJ = 5'b00000; + defparam plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2.RXDCCOUPLE = "FALSE"; + defparam plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2.RXCDRLOS = 6'b001100; + defparam plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2.RXAFEEQ = 9'b000000111; + defparam plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2.RXRCPADJ = 3'b010; + defparam plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2.RXLB = "FALSE"; + defparam plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2.RXCLKMODE = 6'b000011; + defparam plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2.RXASYNCDIVIDE = 2'b01; + defparam plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2.PMA_BIT_SLIP = "FALSE"; + defparam plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2.PMACOREPWRENABLE = "TRUE"; + defparam plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2.PMACLKENABLE = "TRUE"; + defparam plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2.TXPHASESEL = "FALSE"; + defparam plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2.BANDGAPSEL = "FALSE"; + defparam plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2.TXABPMACLKSEL = "REFCLK1"; + defparam plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2.RXPMACLKSEL = "REFCLK1"; + defparam plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2.RXRECCLK1_USE_SYNC = "FALSE"; + defparam plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2.TXOUTCLK1_USE_SYNC = "FALSE"; + defparam plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2.TXCLK0_FORCE_PMACLK = "TRUE"; + defparam plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2.RXCLK0_FORCE_PMACLK = "TRUE"; + defparam plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2.TX_CLOCK_DIVIDER = 2'b01; + defparam plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2.RX_CLOCK_DIVIDER = 2'b01; + defparam plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2.TXCRCENABLE = "TRUE"; + defparam plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2.TXCRCINITVAL = 32'hFFFFFFFF; + defparam plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2.TXCRCSAMECLOCK = "TRUE"; + defparam plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2.TXCRCINVERTGEN = "FALSE"; + defparam plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2.TXCRCCLOCKDOUBLE = "FALSE"; + defparam plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2.RXCRCINITVAL = 32'hFFFFFFFF; + defparam plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2.RXCRCENABLE = "TRUE"; + defparam plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2.RXCRCSAMECLOCK = "TRUE"; + defparam plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2.RXCRCINVERTGEN = "FALSE"; + defparam plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2.RXCRCCLOCKDOUBLE = "FALSE"; + defparam plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2.VCODAC_INIT = 10'b0000000000; + defparam plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2.SLOWDOWN_CAL = 2'b00; + defparam plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2.LOOPCAL_WAIT = 2'b00; + defparam plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2.FDET_HYS_CAL = 3'b010; + defparam plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2.FDET_LCK_CAL = 3'b101; + defparam plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2.FDET_HYS_SEL = 3'b001; + defparam plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2.FDET_LCK_SEL = 3'b111; + defparam plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2.VCO_CTRL_ENABLE = "TRUE"; + defparam plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2.CYCLE_LIMIT_SEL = 2'b00; + defparam plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2.RXVCODAC_INIT = 10'b0000000000; + defparam plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2.RXSLOWDOWN_CAL = 2'b00; + defparam plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2.RXLOOPCAL_WAIT = 2'b00; + defparam plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2.RXFDET_HYS_CAL = 3'b010; + defparam plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2.RXFDET_LCK_CAL = 3'b101; + defparam plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2.RXFDET_HYS_SEL = 3'b001; + defparam plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2.RXFDET_LCK_SEL = 3'b100; + defparam plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2.RXVCO_CTRL_ENABLE = "TRUE"; + defparam plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2.RXCYCLE_LIMIT_SEL = 2'b00; + defparam plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2.RXFDCAL_CLOCK_DIVIDE = "NONE"; + defparam plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2.TXFDCAL_CLOCK_DIVIDE = "NONE"; + defparam plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2.BIASRESSEL = "FALSE"; + defparam plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2.RXPDDTST = "TRUE"; + defparam plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2.RXCMADJ = 2'b01; + defparam plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2.RXBY_32 = "FALSE"; + defparam plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2.REPEATER = "FALSE"; + defparam plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2.ENABLE_DCDR = "FALSE"; + defparam plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2.SAMPLE_8X = "FALSE"; + defparam plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2.DCDR_FILTER = 3'b010; + defparam plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2.RXUSRDIVISOR = 1; + defparam plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2.COMMA_10B_MASK = 12'h3FF; + defparam plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2.PCOMMA_DETECT = "TRUE"; + defparam plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2.MCOMMA_DETECT = "TRUE"; + defparam plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2.DEC_VALID_COMMA_ONLY = "TRUE"; + defparam plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2.DEC_PCOMMA_DETECT = "TRUE"; + defparam plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2.DEC_MCOMMA_DETECT = "TRUE"; + defparam plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2.ALIGN_COMMA_WORD = 1; + defparam plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2.CLK_COR_8B10B_DE = "TRUE"; + defparam plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2.CLK_CORRECT_USE = "TRUE"; + defparam plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2.CLK_COR_SEQ_LEN = 4; + defparam plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2.CLK_COR_SEQ_DROP = "FALSE"; + defparam plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2.CLK_COR_SEQ_2_USE = "FALSE"; + defparam plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2.CLK_COR_MAX_LAT = 44; + defparam plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2.CLK_COR_SEQ_2_MASK = 4'b1110; + defparam plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2.CLK_COR_SEQ_2_4 = 11'b00000000000; + defparam plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2.CLK_COR_SEQ_2_3 = 11'b00000000000; + defparam plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2.CLK_COR_SEQ_2_2 = 11'b00000000000; + defparam plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2.CLK_COR_SEQ_2_1 = 11'b00000000000; + defparam plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2.RXDATA_SEL = 2'b00; + defparam plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2.TXDATA_SEL = 2'b00; + defparam plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2.CLK_COR_MIN_LAT = 36; + defparam plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2.PCS_BIT_SLIP = "FALSE"; + defparam plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2.DIGRX_FWDCLK = 2'b00; + defparam plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2.DIGRX_SYNC_MODE = "FALSE"; + defparam plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2.CLK_COR_SEQ_1_MASK = 4'b0000; + defparam plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2.CLK_COR_SEQ_1_4 = 11'b00100011100; + defparam plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2.CLK_COR_SEQ_1_3 = 11'b00100011100; + defparam plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2.CLK_COR_SEQ_1_2 = 11'b00100011100; + defparam plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2.CLK_COR_SEQ_1_1 = 11'b00110111100; + defparam plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2.CCCB_ARBITRATOR_DISABLE = "FALSE"; + defparam plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2.OPPOSITE_SELECT = "FALSE"; + defparam plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2.POWER_ENABLE = "TRUE"; + defparam plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2.CHAN_BOND_SEQ_2_MASK = 4'b0000; + defparam plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2.CHAN_BOND_SEQ_2_4 = 11'b00000000000; + defparam plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2.CHAN_BOND_SEQ_2_3 = 11'b00000000000; + defparam plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2.CHAN_BOND_SEQ_2_2 = 11'b00000000000; + defparam plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2.CHAN_BOND_SEQ_2_1 = 11'b00000000000; + defparam plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2.TX_BUFFER_USE = "TRUE"; + defparam plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2.RX_BUFFER_USE = "TRUE"; + defparam plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2.CHAN_BOND_SEQ_LEN = 4; + defparam plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2.CHAN_BOND_SEQ_2_USE = "FALSE"; + defparam plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2.CHAN_BOND_ONE_SHOT = "FALSE"; + defparam plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2.CHAN_BOND_MODE = "NONE"; + defparam plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2.CHAN_BOND_LIMIT = 6; + defparam plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2.CHAN_BOND_SEQ_1_MASK = 4'b0000; + defparam plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2.CHAN_BOND_SEQ_1_4 = 11'b00110111100; + defparam plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2.CHAN_BOND_SEQ_1_3 = 11'b00001000101; + defparam plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2.CHAN_BOND_SEQ_1_2 = 11'b00001000101; + defparam plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2.CHAN_BOND_SEQ_1_1 = 11'b00001000101; + defparam plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2.GT11_MODE = "B"; + GT11 plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2 ( + .RXCRCPD(plm_v4f_mgt_gt11_by1_VCC_446), + .RXBUFERR(NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2_RXBUFERR_UNCONNECTED), + .TXSYNC(plm_v4f_mgt_reg_tx_sync_426), + .POWERDOWN(plm_v4f_mgt_gt11_by1_GND_447), + .TXUSRCLK2(mgt_clk), + .ENPCOMMAALIGN(plm_v4f_mgt_gt11_by1_VCC_446), + .RXPOLARITY(plm_v4f_mgt_gt11_by1_GND_447), + .ENMCOMMAALIGN(plm_v4f_mgt_gt11_by1_VCC_446), + .TXBUFERR(NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2_TXBUFERR_UNCONNECTED), + .TXCRCPD(plm_v4f_mgt_gt11_by1_VCC_446), + .RXSIGDET(NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2_RXSIGDET_UNCONNECTED), + .TXCLKSTABLE(plm_v4f_mgt_gt11_by1_VCC_446), + .RXUSRCLK2(mgt_clk), + .TXPOLARITY(plm_v4f_mgt_gt11_by1_GND_447), + .DWE(plm_v4f_mgt_gt1_dwe), + .RXREALIGN(NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2_RXREALIGN_UNCONNECTED), + .TXGEARBOX64B66BUSE(plm_v4f_mgt_gt11_by1_GND_447), + .RXCYCLELIMIT(NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2_RXCYCLELIMIT_UNCONNECTED), + .RXRESET(plm_v4f_mgt_reg_rx_pcs_init_431), + .TXCYCLELIMIT(NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2_TXCYCLELIMIT_UNCONNECTED), + .TXCALFAIL(NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2_TXCALFAIL_UNCONNECTED), + .RXUSRCLK(mgt_clk), + .RXDEC64B66BUSE(plm_v4f_mgt_gt11_by1_GND_447), + .RXPCSHCLKOUT(NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2_RXPCSHCLKOUT_UNCONNECTED), + .TXPCSHCLKOUT(NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2_TXPCSHCLKOUT_UNCONNECTED), + .RXCOMMADETUSE(plm_v4f_mgt_gt11_by1_VCC_446), + .DCLK(NlwRenamedSig_OI_trn_clk), + .TXCRCINIT(plm_v4f_mgt_gt11_by1_GND_447), + .TXUSRCLK(mgt_clk), + .RXCALFAIL(NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2_RXCALFAIL_UNCONNECTED), + .RXPMARESET(plm_v4f_mgt_reg_pma_441), + .RX1N(plm_v4f_mgt_gt11_by1_GND_447), + .RX1P(plm_v4f_mgt_gt11_by1_GND_447), + .TXRESET(plm_v4f_mgt_reg_tx_pcs_init_427), + .RXSLIDE(plm_v4f_mgt_gt11_by1_GND_447), + .TXPMARESET(plm_v4f_mgt_reg_pma_441), + .TXCRCINTCLK(plm_v4f_mgt_gt11_by1_GND_447), + .RXCRCINIT(plm_v4f_mgt_gt11_by1_GND_447), + .RXDEC8B10BUSE(plm_v4f_mgt_gt11_by1_VCC_446), + .RXCLKSTABLE(plm_v4f_mgt_gt11_by1_VCC_446), + .RXLOCK(NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2_RXLOCK_UNCONNECTED), + .TXCRCDATAVALID(plm_v4f_mgt_gt11_by1_GND_447), + .GREFCLK(NlwRenamedSig_OI_trn_clk), + .ENCHANSYNC(plm_v4f_mgt_gt11_by1_GND_447), + .DEN(plm_v4f_mgt_gt1_den), + .RXMCLK(NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2_RXMCLK_UNCONNECTED), + .RXCOMMADET(NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2_RXCOMMADET_UNCONNECTED), + .TXOUTCLK1(NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2_TXOUTCLK1_UNCONNECTED), + .TXOUTCLK2(NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2_TXOUTCLK2_UNCONNECTED), + .RXCRCRESET(plm_v4f_mgt_gt11_by1_VCC_446), + .RXCRCCLK(plm_v4f_mgt_gt11_by1_GND_447), + .TXENC64B66BUSE(plm_v4f_mgt_gt11_by1_GND_447), + .TXINHIBIT(plm_v4f_mgt_gt11_by1_GND_447), + .RXRECCLK1(NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2_RXRECCLK1_UNCONNECTED), + .RXRECCLK2(NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2_RXRECCLK2_UNCONNECTED), + .TXLOCK(NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2_TXLOCK_UNCONNECTED), + .TXCRCRESET(plm_v4f_mgt_gt11_by1_VCC_446), + .RXDESCRAM64B66BUSE(plm_v4f_mgt_gt11_by1_GND_447), + .RXBLOCKSYNC64B66BUSE(plm_v4f_mgt_gt11_by1_GND_447), + .RXIGNOREBTF(plm_v4f_mgt_gt11_by1_GND_447), + .TXCRCCLK(plm_v4f_mgt_gt11_by1_GND_447), + .RXCRCDATAVALID(plm_v4f_mgt_gt11_by1_GND_447), + .TXSCRAM64B66BUSE(plm_v4f_mgt_gt11_by1_GND_447), + .RXCRCINTCLK(plm_v4f_mgt_gt11_by1_GND_447), + .RXSYNC(plm_v4f_mgt_gt11_by1_GND_447), + .DRDY(plm_v4f_mgt_gt1_drdy), + .TXENC8B10BUSE(plm_v4f_mgt_gt11_by1_VCC_446), + .REFCLK1(sys_clkz), + .TXENOOB(plm_v4f_mgt_gt11_by1_VCC_446), + .REFCLK2(plm_v4f_mgt_gt11_by1_GND_447), + .TX1N(NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2_TX1N_UNCONNECTED), + .TX1P(NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2_TX1P_UNCONNECTED), + .RXSTATUS({NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2_RXSTATUS_5__UNCONNECTED, +NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2_RXSTATUS_4__UNCONNECTED, NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2_RXSTATUS_3__UNCONNECTED, +NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2_RXSTATUS_2__UNCONNECTED, NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2_RXSTATUS_1__UNCONNECTED, +NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2_RXSTATUS_0__UNCONNECTED}), + .RXNOTINTABLE({NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2_RXNOTINTABLE_7__UNCONNECTED, +NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2_RXNOTINTABLE_6__UNCONNECTED, NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2_RXNOTINTABLE_5__UNCONNECTED, +NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2_RXNOTINTABLE_4__UNCONNECTED, NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2_RXNOTINTABLE_3__UNCONNECTED, +NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2_RXNOTINTABLE_2__UNCONNECTED, NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2_RXNOTINTABLE_1__UNCONNECTED, +NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2_RXNOTINTABLE_0__UNCONNECTED}), + .DADDR({plm_v4f_mgt_gt11_by1_GND_447, plm_v4f_mgt_gt11_by1_VCC_446, plm_v4f_mgt_gt1_daddr[5], plm_v4f_mgt_gt1_daddr[4], plm_v4f_mgt_gt1_daddr[3], +plm_v4f_mgt_gt1_daddr[2], plm_v4f_mgt_gt1_daddr[1], plm_v4f_mgt_gt1_daddr[4]}), + .TXDATAWIDTH({plm_v4f_mgt_gt11_by1_GND_447, plm_v4f_mgt_gt11_by1_VCC_446}), + .RXCRCOUT({NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2_RXCRCOUT_31__UNCONNECTED, +NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2_RXCRCOUT_30__UNCONNECTED, NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2_RXCRCOUT_29__UNCONNECTED, +NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2_RXCRCOUT_28__UNCONNECTED, NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2_RXCRCOUT_27__UNCONNECTED, +NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2_RXCRCOUT_26__UNCONNECTED, NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2_RXCRCOUT_25__UNCONNECTED, +NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2_RXCRCOUT_24__UNCONNECTED, NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2_RXCRCOUT_23__UNCONNECTED, +NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2_RXCRCOUT_22__UNCONNECTED, NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2_RXCRCOUT_21__UNCONNECTED, +NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2_RXCRCOUT_20__UNCONNECTED, NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2_RXCRCOUT_19__UNCONNECTED, +NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2_RXCRCOUT_18__UNCONNECTED, NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2_RXCRCOUT_17__UNCONNECTED, +NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2_RXCRCOUT_16__UNCONNECTED, NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2_RXCRCOUT_15__UNCONNECTED, +NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2_RXCRCOUT_14__UNCONNECTED, NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2_RXCRCOUT_13__UNCONNECTED, +NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2_RXCRCOUT_12__UNCONNECTED, NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2_RXCRCOUT_11__UNCONNECTED, +NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2_RXCRCOUT_10__UNCONNECTED, NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2_RXCRCOUT_9__UNCONNECTED, +NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2_RXCRCOUT_8__UNCONNECTED, NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2_RXCRCOUT_7__UNCONNECTED, +NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2_RXCRCOUT_6__UNCONNECTED, NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2_RXCRCOUT_5__UNCONNECTED, +NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2_RXCRCOUT_4__UNCONNECTED, NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2_RXCRCOUT_3__UNCONNECTED, +NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2_RXCRCOUT_2__UNCONNECTED, NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2_RXCRCOUT_1__UNCONNECTED, +NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2_RXCRCOUT_0__UNCONNECTED}), + .TXINTDATAWIDTH({plm_v4f_mgt_gt11_by1_VCC_446, plm_v4f_mgt_gt11_by1_VCC_446}), + .DI({plm_v4f_mgt_gt1_do[15], plm_v4f_mgt_gt1_do[14], plm_v4f_mgt_gt1_do[13], plm_v4f_mgt_gt1_do[12], plm_v4f_mgt_gt1_do[11], +plm_v4f_mgt_gt1_do[10], plm_v4f_mgt_gt1_do[9], plm_v4f_mgt_gt1_do[8], plm_v4f_mgt_gt1_do[7], plm_v4f_mgt_gt1_do[6], plm_v4f_mgt_gt1_do[5], +plm_v4f_mgt_gt1_do[4], plm_v4f_mgt_gt1_do[3], plm_v4f_mgt_gt1_do[2], plm_v4f_mgt_gt1_do[1], plm_v4f_mgt_gt1_do[0]}), + .DO({plm_v4f_mgt_gt1_di[15], plm_v4f_mgt_gt1_di[14], plm_v4f_mgt_gt1_di[13], plm_v4f_mgt_gt1_di[12], plm_v4f_mgt_gt1_di[11], +plm_v4f_mgt_gt1_di[10], plm_v4f_mgt_gt1_di[9], plm_v4f_mgt_gt1_di[8], plm_v4f_mgt_gt1_di[7], plm_v4f_mgt_gt1_di[6], plm_v4f_mgt_gt1_di[5], +plm_v4f_mgt_gt1_di[4], plm_v4f_mgt_gt1_di[3], plm_v4f_mgt_gt1_di[2], plm_v4f_mgt_gt1_di[1], plm_v4f_mgt_gt1_di[0]}), + .TXCRCOUT({NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2_TXCRCOUT_31__UNCONNECTED, +NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2_TXCRCOUT_30__UNCONNECTED, NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2_TXCRCOUT_29__UNCONNECTED, +NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2_TXCRCOUT_28__UNCONNECTED, NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2_TXCRCOUT_27__UNCONNECTED, +NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2_TXCRCOUT_26__UNCONNECTED, NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2_TXCRCOUT_25__UNCONNECTED, +NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2_TXCRCOUT_24__UNCONNECTED, NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2_TXCRCOUT_23__UNCONNECTED, +NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2_TXCRCOUT_22__UNCONNECTED, NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2_TXCRCOUT_21__UNCONNECTED, +NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2_TXCRCOUT_20__UNCONNECTED, NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2_TXCRCOUT_19__UNCONNECTED, +NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2_TXCRCOUT_18__UNCONNECTED, NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2_TXCRCOUT_17__UNCONNECTED, +NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2_TXCRCOUT_16__UNCONNECTED, NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2_TXCRCOUT_15__UNCONNECTED, +NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2_TXCRCOUT_14__UNCONNECTED, NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2_TXCRCOUT_13__UNCONNECTED, +NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2_TXCRCOUT_12__UNCONNECTED, NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2_TXCRCOUT_11__UNCONNECTED, +NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2_TXCRCOUT_10__UNCONNECTED, NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2_TXCRCOUT_9__UNCONNECTED, +NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2_TXCRCOUT_8__UNCONNECTED, NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2_TXCRCOUT_7__UNCONNECTED, +NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2_TXCRCOUT_6__UNCONNECTED, NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2_TXCRCOUT_5__UNCONNECTED, +NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2_TXCRCOUT_4__UNCONNECTED, NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2_TXCRCOUT_3__UNCONNECTED, +NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2_TXCRCOUT_2__UNCONNECTED, NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2_TXCRCOUT_1__UNCONNECTED, +NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2_TXCRCOUT_0__UNCONNECTED}), + .COMBUSIN({plm_v4f_mgt_gt11_by1_COMBUSOUT[15], plm_v4f_mgt_gt11_by1_COMBUSOUT[14], plm_v4f_mgt_gt11_by1_COMBUSOUT[13], +plm_v4f_mgt_gt11_by1_COMBUSOUT[12], plm_v4f_mgt_gt11_by1_COMBUSOUT[11], plm_v4f_mgt_gt11_by1_COMBUSOUT[10], plm_v4f_mgt_gt11_by1_COMBUSOUT[9], +plm_v4f_mgt_gt11_by1_COMBUSOUT[8], plm_v4f_mgt_gt11_by1_COMBUSOUT[7], plm_v4f_mgt_gt11_by1_COMBUSOUT[6], plm_v4f_mgt_gt11_by1_COMBUSOUT[5], +plm_v4f_mgt_gt11_by1_COMBUSOUT[4], plm_v4f_mgt_gt11_by1_COMBUSOUT[3], plm_v4f_mgt_gt11_by1_COMBUSOUT[2], plm_v4f_mgt_gt11_by1_COMBUSOUT[1], +plm_v4f_mgt_gt11_by1_COMBUSOUT[0]}), + .COMBUSOUT({plm_v4f_mgt_gt11_by1_COMBUSOUT_BLK2[15], plm_v4f_mgt_gt11_by1_COMBUSOUT_BLK2[14], plm_v4f_mgt_gt11_by1_COMBUSOUT_BLK2[13], +plm_v4f_mgt_gt11_by1_COMBUSOUT_BLK2[12], plm_v4f_mgt_gt11_by1_COMBUSOUT_BLK2[11], plm_v4f_mgt_gt11_by1_COMBUSOUT_BLK2[10], +plm_v4f_mgt_gt11_by1_COMBUSOUT_BLK2[9], plm_v4f_mgt_gt11_by1_COMBUSOUT_BLK2[8], plm_v4f_mgt_gt11_by1_COMBUSOUT_BLK2[7], +plm_v4f_mgt_gt11_by1_COMBUSOUT_BLK2[6], plm_v4f_mgt_gt11_by1_COMBUSOUT_BLK2[5], plm_v4f_mgt_gt11_by1_COMBUSOUT_BLK2[4], +plm_v4f_mgt_gt11_by1_COMBUSOUT_BLK2[3], plm_v4f_mgt_gt11_by1_COMBUSOUT_BLK2[2], plm_v4f_mgt_gt11_by1_COMBUSOUT_BLK2[1], +plm_v4f_mgt_gt11_by1_COMBUSOUT_BLK2[0]}), + .RXDATA({NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2_RXDATA_63__UNCONNECTED, NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2_RXDATA_62__UNCONNECTED +, NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2_RXDATA_61__UNCONNECTED, NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2_RXDATA_60__UNCONNECTED, +NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2_RXDATA_59__UNCONNECTED, NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2_RXDATA_58__UNCONNECTED, +NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2_RXDATA_57__UNCONNECTED, NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2_RXDATA_56__UNCONNECTED, +NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2_RXDATA_55__UNCONNECTED, NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2_RXDATA_54__UNCONNECTED, +NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2_RXDATA_53__UNCONNECTED, NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2_RXDATA_52__UNCONNECTED, +NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2_RXDATA_51__UNCONNECTED, NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2_RXDATA_50__UNCONNECTED, +NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2_RXDATA_49__UNCONNECTED, NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2_RXDATA_48__UNCONNECTED, +NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2_RXDATA_47__UNCONNECTED, NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2_RXDATA_46__UNCONNECTED, +NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2_RXDATA_45__UNCONNECTED, NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2_RXDATA_44__UNCONNECTED, +NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2_RXDATA_43__UNCONNECTED, NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2_RXDATA_42__UNCONNECTED, +NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2_RXDATA_41__UNCONNECTED, NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2_RXDATA_40__UNCONNECTED, +NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2_RXDATA_39__UNCONNECTED, NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2_RXDATA_38__UNCONNECTED, +NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2_RXDATA_37__UNCONNECTED, NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2_RXDATA_36__UNCONNECTED, +NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2_RXDATA_35__UNCONNECTED, NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2_RXDATA_34__UNCONNECTED, +NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2_RXDATA_33__UNCONNECTED, NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2_RXDATA_32__UNCONNECTED, +NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2_RXDATA_31__UNCONNECTED, NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2_RXDATA_30__UNCONNECTED, +NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2_RXDATA_29__UNCONNECTED, NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2_RXDATA_28__UNCONNECTED, +NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2_RXDATA_27__UNCONNECTED, NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2_RXDATA_26__UNCONNECTED, +NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2_RXDATA_25__UNCONNECTED, NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2_RXDATA_24__UNCONNECTED, +NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2_RXDATA_23__UNCONNECTED, NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2_RXDATA_22__UNCONNECTED, +NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2_RXDATA_21__UNCONNECTED, NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2_RXDATA_20__UNCONNECTED, +NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2_RXDATA_19__UNCONNECTED, NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2_RXDATA_18__UNCONNECTED, +NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2_RXDATA_17__UNCONNECTED, NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2_RXDATA_16__UNCONNECTED, +NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2_RXDATA_15__UNCONNECTED, NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2_RXDATA_14__UNCONNECTED, +NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2_RXDATA_13__UNCONNECTED, NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2_RXDATA_12__UNCONNECTED, +NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2_RXDATA_11__UNCONNECTED, NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2_RXDATA_10__UNCONNECTED, +NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2_RXDATA_9__UNCONNECTED, NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2_RXDATA_8__UNCONNECTED, +NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2_RXDATA_7__UNCONNECTED, NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2_RXDATA_6__UNCONNECTED, +NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2_RXDATA_5__UNCONNECTED, NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2_RXDATA_4__UNCONNECTED, +NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2_RXDATA_3__UNCONNECTED, NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2_RXDATA_2__UNCONNECTED, +NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2_RXDATA_1__UNCONNECTED, NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2_RXDATA_0__UNCONNECTED}), + .TXRUNDISP({NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2_TXRUNDISP_7__UNCONNECTED, +NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2_TXRUNDISP_6__UNCONNECTED, NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2_TXRUNDISP_5__UNCONNECTED, +NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2_TXRUNDISP_4__UNCONNECTED, NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2_TXRUNDISP_3__UNCONNECTED, +NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2_TXRUNDISP_2__UNCONNECTED, NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2_TXRUNDISP_1__UNCONNECTED, +NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2_TXRUNDISP_0__UNCONNECTED}), + .RXINTDATAWIDTH({plm_v4f_mgt_gt11_by1_VCC_446, plm_v4f_mgt_gt11_by1_VCC_446}), + .RXDATAWIDTH({plm_v4f_mgt_gt11_by1_GND_447, plm_v4f_mgt_gt11_by1_VCC_446}), + .RXLOSSOFSYNC({NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2_RXLOSSOFSYNC_1__UNCONNECTED, +NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2_RXLOSSOFSYNC_0__UNCONNECTED}), + .RXRUNDISP({NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2_RXRUNDISP_7__UNCONNECTED, +NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2_RXRUNDISP_6__UNCONNECTED, NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2_RXRUNDISP_5__UNCONNECTED, +NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2_RXRUNDISP_4__UNCONNECTED, NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2_RXRUNDISP_3__UNCONNECTED, +NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2_RXRUNDISP_2__UNCONNECTED, NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2_RXRUNDISP_1__UNCONNECTED, +NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2_RXRUNDISP_0__UNCONNECTED}), + .TXDATA({plm_v4f_mgt_gt11_by1_GND_447, plm_v4f_mgt_gt11_by1_GND_447, plm_v4f_mgt_gt11_by1_GND_447, plm_v4f_mgt_gt11_by1_GND_447, +plm_v4f_mgt_gt11_by1_GND_447, plm_v4f_mgt_gt11_by1_GND_447, plm_v4f_mgt_gt11_by1_GND_447, plm_v4f_mgt_gt11_by1_GND_447, plm_v4f_mgt_gt11_by1_GND_447, +plm_v4f_mgt_gt11_by1_GND_447, plm_v4f_mgt_gt11_by1_GND_447, plm_v4f_mgt_gt11_by1_GND_447, plm_v4f_mgt_gt11_by1_GND_447, plm_v4f_mgt_gt11_by1_GND_447, +plm_v4f_mgt_gt11_by1_GND_447, plm_v4f_mgt_gt11_by1_GND_447, plm_v4f_mgt_gt11_by1_GND_447, plm_v4f_mgt_gt11_by1_GND_447, plm_v4f_mgt_gt11_by1_GND_447, +plm_v4f_mgt_gt11_by1_GND_447, plm_v4f_mgt_gt11_by1_GND_447, plm_v4f_mgt_gt11_by1_GND_447, plm_v4f_mgt_gt11_by1_GND_447, plm_v4f_mgt_gt11_by1_GND_447, +plm_v4f_mgt_gt11_by1_GND_447, plm_v4f_mgt_gt11_by1_GND_447, plm_v4f_mgt_gt11_by1_GND_447, plm_v4f_mgt_gt11_by1_GND_447, plm_v4f_mgt_gt11_by1_GND_447, +plm_v4f_mgt_gt11_by1_GND_447, plm_v4f_mgt_gt11_by1_GND_447, plm_v4f_mgt_gt11_by1_GND_447, plm_v4f_mgt_gt11_by1_GND_447, plm_v4f_mgt_gt11_by1_GND_447, +plm_v4f_mgt_gt11_by1_GND_447, plm_v4f_mgt_gt11_by1_GND_447, plm_v4f_mgt_gt11_by1_GND_447, plm_v4f_mgt_gt11_by1_GND_447, plm_v4f_mgt_gt11_by1_GND_447, +plm_v4f_mgt_gt11_by1_GND_447, plm_v4f_mgt_gt11_by1_GND_447, plm_v4f_mgt_gt11_by1_GND_447, plm_v4f_mgt_gt11_by1_GND_447, plm_v4f_mgt_gt11_by1_GND_447, +plm_v4f_mgt_gt11_by1_GND_447, plm_v4f_mgt_gt11_by1_GND_447, plm_v4f_mgt_gt11_by1_GND_447, plm_v4f_mgt_gt11_by1_GND_447, plm_v4f_mgt_gt11_by1_GND_447, +plm_v4f_mgt_gt11_by1_GND_447, plm_v4f_mgt_gt11_by1_GND_447, plm_v4f_mgt_gt11_by1_GND_447, plm_v4f_mgt_gt11_by1_GND_447, plm_v4f_mgt_gt11_by1_GND_447, +plm_v4f_mgt_gt11_by1_GND_447, plm_v4f_mgt_gt11_by1_GND_447, plm_v4f_mgt_gt11_by1_GND_447, plm_v4f_mgt_gt11_by1_GND_447, plm_v4f_mgt_gt11_by1_GND_447, +plm_v4f_mgt_gt11_by1_GND_447, plm_v4f_mgt_gt11_by1_GND_447, plm_v4f_mgt_gt11_by1_GND_447, plm_v4f_mgt_gt11_by1_GND_447, plm_v4f_mgt_gt11_by1_GND_447}) +, + .TXCHARDISPVAL({plm_v4f_mgt_gt11_by1_GND_447, plm_v4f_mgt_gt11_by1_GND_447, plm_v4f_mgt_gt11_by1_GND_447, plm_v4f_mgt_gt11_by1_GND_447, +plm_v4f_mgt_gt11_by1_GND_447, plm_v4f_mgt_gt11_by1_GND_447, plm_v4f_mgt_gt11_by1_GND_447, plm_v4f_mgt_gt11_by1_GND_447}), + .LOOPBACK({plm_v4f_mgt_loopback1[1], plm_v4f_mgt_loopback1[1]}), + .CHBONDI({plm_v4f_mgt_gt11_by1_GND_447, plm_v4f_mgt_gt11_by1_GND_447, plm_v4f_mgt_gt11_by1_GND_447, plm_v4f_mgt_gt11_by1_GND_447, +plm_v4f_mgt_gt11_by1_GND_447}), + .TXCRCDATAWIDTH({plm_v4f_mgt_gt11_by1_GND_447, plm_v4f_mgt_gt11_by1_GND_447, plm_v4f_mgt_gt11_by1_GND_447}), + .CHBONDO({NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2_CHBONDO_4__UNCONNECTED, NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2_CHBONDO_3__UNCONNECTED +, NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2_CHBONDO_2__UNCONNECTED, NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2_CHBONDO_1__UNCONNECTED, +NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2_CHBONDO_0__UNCONNECTED}), + .TXCHARISK({plm_v4f_mgt_gt11_by1_GND_447, plm_v4f_mgt_gt11_by1_GND_447, plm_v4f_mgt_gt11_by1_GND_447, plm_v4f_mgt_gt11_by1_GND_447, +plm_v4f_mgt_gt11_by1_GND_447, plm_v4f_mgt_gt11_by1_GND_447, plm_v4f_mgt_gt11_by1_GND_447, plm_v4f_mgt_gt11_by1_GND_447}), + .TXBYPASS8B10B({plm_v4f_mgt_gt11_by1_GND_447, plm_v4f_mgt_gt11_by1_GND_447, plm_v4f_mgt_gt11_by1_GND_447, plm_v4f_mgt_gt11_by1_GND_447, +plm_v4f_mgt_gt11_by1_GND_447, plm_v4f_mgt_gt11_by1_GND_447, plm_v4f_mgt_gt11_by1_GND_447, plm_v4f_mgt_gt11_by1_GND_447}), + .RXCRCIN({plm_v4f_mgt_gt11_by1_GND_447, plm_v4f_mgt_gt11_by1_GND_447, plm_v4f_mgt_gt11_by1_GND_447, plm_v4f_mgt_gt11_by1_GND_447, +plm_v4f_mgt_gt11_by1_GND_447, plm_v4f_mgt_gt11_by1_GND_447, plm_v4f_mgt_gt11_by1_GND_447, plm_v4f_mgt_gt11_by1_GND_447, plm_v4f_mgt_gt11_by1_GND_447, +plm_v4f_mgt_gt11_by1_GND_447, plm_v4f_mgt_gt11_by1_GND_447, plm_v4f_mgt_gt11_by1_GND_447, plm_v4f_mgt_gt11_by1_GND_447, plm_v4f_mgt_gt11_by1_GND_447, +plm_v4f_mgt_gt11_by1_GND_447, plm_v4f_mgt_gt11_by1_GND_447, plm_v4f_mgt_gt11_by1_GND_447, plm_v4f_mgt_gt11_by1_GND_447, plm_v4f_mgt_gt11_by1_GND_447, +plm_v4f_mgt_gt11_by1_GND_447, plm_v4f_mgt_gt11_by1_GND_447, plm_v4f_mgt_gt11_by1_GND_447, plm_v4f_mgt_gt11_by1_GND_447, plm_v4f_mgt_gt11_by1_GND_447, +plm_v4f_mgt_gt11_by1_GND_447, plm_v4f_mgt_gt11_by1_GND_447, plm_v4f_mgt_gt11_by1_GND_447, plm_v4f_mgt_gt11_by1_GND_447, plm_v4f_mgt_gt11_by1_GND_447, +plm_v4f_mgt_gt11_by1_GND_447, plm_v4f_mgt_gt11_by1_GND_447, plm_v4f_mgt_gt11_by1_GND_447, plm_v4f_mgt_gt11_by1_GND_447, plm_v4f_mgt_gt11_by1_GND_447, +plm_v4f_mgt_gt11_by1_GND_447, plm_v4f_mgt_gt11_by1_GND_447, plm_v4f_mgt_gt11_by1_GND_447, plm_v4f_mgt_gt11_by1_GND_447, plm_v4f_mgt_gt11_by1_GND_447, +plm_v4f_mgt_gt11_by1_GND_447, plm_v4f_mgt_gt11_by1_GND_447, plm_v4f_mgt_gt11_by1_GND_447, plm_v4f_mgt_gt11_by1_GND_447, plm_v4f_mgt_gt11_by1_GND_447, +plm_v4f_mgt_gt11_by1_GND_447, plm_v4f_mgt_gt11_by1_GND_447, plm_v4f_mgt_gt11_by1_GND_447, plm_v4f_mgt_gt11_by1_GND_447, plm_v4f_mgt_gt11_by1_GND_447, +plm_v4f_mgt_gt11_by1_GND_447, plm_v4f_mgt_gt11_by1_GND_447, plm_v4f_mgt_gt11_by1_GND_447, plm_v4f_mgt_gt11_by1_GND_447, plm_v4f_mgt_gt11_by1_GND_447, +plm_v4f_mgt_gt11_by1_GND_447, plm_v4f_mgt_gt11_by1_GND_447, plm_v4f_mgt_gt11_by1_GND_447, plm_v4f_mgt_gt11_by1_GND_447, plm_v4f_mgt_gt11_by1_GND_447, +plm_v4f_mgt_gt11_by1_GND_447, plm_v4f_mgt_gt11_by1_GND_447, plm_v4f_mgt_gt11_by1_GND_447, plm_v4f_mgt_gt11_by1_GND_447, plm_v4f_mgt_gt11_by1_GND_447}) +, + .RXCHARISK({NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2_RXCHARISK_7__UNCONNECTED, +NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2_RXCHARISK_6__UNCONNECTED, NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2_RXCHARISK_5__UNCONNECTED, +NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2_RXCHARISK_4__UNCONNECTED, NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2_RXCHARISK_3__UNCONNECTED, +NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2_RXCHARISK_2__UNCONNECTED, NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2_RXCHARISK_1__UNCONNECTED, +NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2_RXCHARISK_0__UNCONNECTED}), + .TXCHARDISPMODE({plm_v4f_mgt_gt11_by1_GND_447, plm_v4f_mgt_gt11_by1_GND_447, plm_v4f_mgt_gt11_by1_GND_447, plm_v4f_mgt_gt11_by1_GND_447, +plm_v4f_mgt_gt11_by1_GND_447, plm_v4f_mgt_gt11_by1_GND_447, plm_v4f_mgt_gt11_by1_GND_447, plm_v4f_mgt_gt11_by1_GND_447}), + .RXCRCDATAWIDTH({plm_v4f_mgt_gt11_by1_GND_447, plm_v4f_mgt_gt11_by1_GND_447, plm_v4f_mgt_gt11_by1_GND_447}), + .RXDISPERR({NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2_RXDISPERR_7__UNCONNECTED, +NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2_RXDISPERR_6__UNCONNECTED, NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2_RXDISPERR_5__UNCONNECTED, +NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2_RXDISPERR_4__UNCONNECTED, NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2_RXDISPERR_3__UNCONNECTED, +NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2_RXDISPERR_2__UNCONNECTED, NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2_RXDISPERR_1__UNCONNECTED, +NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2_RXDISPERR_0__UNCONNECTED}), + .RXCHARISCOMMA({NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2_RXCHARISCOMMA_7__UNCONNECTED, +NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2_RXCHARISCOMMA_6__UNCONNECTED, NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2_RXCHARISCOMMA_5__UNCONNECTED, +NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2_RXCHARISCOMMA_4__UNCONNECTED, NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2_RXCHARISCOMMA_3__UNCONNECTED, +NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2_RXCHARISCOMMA_2__UNCONNECTED, NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2_RXCHARISCOMMA_1__UNCONNECTED, +NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2_RXCHARISCOMMA_0__UNCONNECTED}), + .TXCRCIN({plm_v4f_mgt_gt11_by1_GND_447, plm_v4f_mgt_gt11_by1_GND_447, plm_v4f_mgt_gt11_by1_GND_447, plm_v4f_mgt_gt11_by1_GND_447, +plm_v4f_mgt_gt11_by1_GND_447, plm_v4f_mgt_gt11_by1_GND_447, plm_v4f_mgt_gt11_by1_GND_447, plm_v4f_mgt_gt11_by1_GND_447, plm_v4f_mgt_gt11_by1_GND_447, +plm_v4f_mgt_gt11_by1_GND_447, plm_v4f_mgt_gt11_by1_GND_447, plm_v4f_mgt_gt11_by1_GND_447, plm_v4f_mgt_gt11_by1_GND_447, plm_v4f_mgt_gt11_by1_GND_447, +plm_v4f_mgt_gt11_by1_GND_447, plm_v4f_mgt_gt11_by1_GND_447, plm_v4f_mgt_gt11_by1_GND_447, plm_v4f_mgt_gt11_by1_GND_447, plm_v4f_mgt_gt11_by1_GND_447, +plm_v4f_mgt_gt11_by1_GND_447, plm_v4f_mgt_gt11_by1_GND_447, plm_v4f_mgt_gt11_by1_GND_447, plm_v4f_mgt_gt11_by1_GND_447, plm_v4f_mgt_gt11_by1_GND_447, +plm_v4f_mgt_gt11_by1_GND_447, plm_v4f_mgt_gt11_by1_GND_447, plm_v4f_mgt_gt11_by1_GND_447, plm_v4f_mgt_gt11_by1_GND_447, plm_v4f_mgt_gt11_by1_GND_447, +plm_v4f_mgt_gt11_by1_GND_447, plm_v4f_mgt_gt11_by1_GND_447, plm_v4f_mgt_gt11_by1_GND_447, plm_v4f_mgt_gt11_by1_GND_447, plm_v4f_mgt_gt11_by1_GND_447, +plm_v4f_mgt_gt11_by1_GND_447, plm_v4f_mgt_gt11_by1_GND_447, plm_v4f_mgt_gt11_by1_GND_447, plm_v4f_mgt_gt11_by1_GND_447, plm_v4f_mgt_gt11_by1_GND_447, +plm_v4f_mgt_gt11_by1_GND_447, plm_v4f_mgt_gt11_by1_GND_447, plm_v4f_mgt_gt11_by1_GND_447, plm_v4f_mgt_gt11_by1_GND_447, plm_v4f_mgt_gt11_by1_GND_447, +plm_v4f_mgt_gt11_by1_GND_447, plm_v4f_mgt_gt11_by1_GND_447, plm_v4f_mgt_gt11_by1_GND_447, plm_v4f_mgt_gt11_by1_GND_447, plm_v4f_mgt_gt11_by1_GND_447, +plm_v4f_mgt_gt11_by1_GND_447, plm_v4f_mgt_gt11_by1_GND_447, plm_v4f_mgt_gt11_by1_GND_447, plm_v4f_mgt_gt11_by1_GND_447, plm_v4f_mgt_gt11_by1_GND_447, +plm_v4f_mgt_gt11_by1_GND_447, plm_v4f_mgt_gt11_by1_GND_447, plm_v4f_mgt_gt11_by1_GND_447, plm_v4f_mgt_gt11_by1_GND_447, plm_v4f_mgt_gt11_by1_GND_447, +plm_v4f_mgt_gt11_by1_GND_447, plm_v4f_mgt_gt11_by1_GND_447, plm_v4f_mgt_gt11_by1_GND_447, plm_v4f_mgt_gt11_by1_GND_447, plm_v4f_mgt_gt11_by1_GND_447}) +, + .TXKERR({NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2_TXKERR_7__UNCONNECTED, NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2_TXKERR_6__UNCONNECTED, +NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2_TXKERR_5__UNCONNECTED, NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2_TXKERR_4__UNCONNECTED, +NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2_TXKERR_3__UNCONNECTED, NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2_TXKERR_2__UNCONNECTED, +NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2_TXKERR_1__UNCONNECTED, NLW_plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST2_TXKERR_0__UNCONNECTED}) + ); + GND plm_v4f_mgt_for_v1_4_cal_inst0_GND ( + .G(plm_v4f_mgt_for_v1_4_cal_inst0_GND_481) + ); + FDS plm_v4f_mgt_for_v1_4_cal_inst0_drp_state_0_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(plm_v4f_mgt_for_v1_4_cal_inst0_N_1051_i_475), + .Q(plm_v4f_mgt_for_v1_4_cal_inst0_drp_state_0__477), + .S(plm_v4f_mgt_for_v1_4_cal_inst0_reset_r[0]) + ); + FDR plm_v4f_mgt_for_v1_4_cal_inst0_drp_state_1_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(plm_v4f_mgt_for_v1_4_cal_inst0_N_576_i), + .Q(plm_v4f_mgt_for_v1_4_cal_inst0_drp_state_1__472), + .R(plm_v4f_mgt_for_v1_4_cal_inst0_reset_r[0]) + ); + FDR plm_v4f_mgt_for_v1_4_cal_inst0_drp_state_2_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(plm_v4f_mgt_for_v1_4_cal_inst0_drp_next_state_0_sqmuxa_1), + .Q(plm_v4f_mgt_gt0_dwe), + .R(plm_v4f_mgt_for_v1_4_cal_inst0_reset_r[0]) + ); + FDR plm_v4f_mgt_for_v1_4_cal_inst0_drp_state_3_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(plm_v4f_mgt_for_v1_4_cal_inst0_N_1020_i_470), + .Q(plm_v4f_mgt_for_v1_4_cal_inst0_drp_state_3__471), + .R(plm_v4f_mgt_for_v1_4_cal_inst0_reset_r[0]) + ); + FDR plm_v4f_mgt_for_v1_4_cal_inst0_drp_state_4_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(plm_v4f_mgt_for_v1_4_cal_inst0_drp_next_state_0_sqmuxa), + .Q(plm_v4f_mgt_for_v1_4_cal_inst0_drp_state_4__476), + .R(plm_v4f_mgt_for_v1_4_cal_inst0_reset_r[0]) + ); + FDR plm_v4f_mgt_for_v1_4_cal_inst0_sd_state_3_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(plm_v4f_mgt_for_v1_4_cal_inst0_N_683_i), + .Q(plm_v4f_mgt_for_v1_4_cal_inst0_sd_state_3__468), + .R(plm_v4f_mgt_for_v1_4_cal_inst0_reset_r[0]) + ); + FDR plm_v4f_mgt_for_v1_4_cal_inst0_sd_state_5_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(plm_v4f_mgt_for_v1_4_cal_inst0_sd_next_state_0_sqmuxa_1), + .Q(plm_v4f_mgt_for_v1_4_cal_inst0_sd_state_5__466), + .R(plm_v4f_mgt_for_v1_4_cal_inst0_reset_r[0]) + ); + FDR plm_v4f_mgt_for_v1_4_cal_inst0_sd_state_6_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(plm_v4f_mgt_for_v1_4_cal_inst0_N_682_i_464), + .Q(plm_v4f_mgt_for_v1_4_cal_inst0_sd_state_6__465), + .R(plm_v4f_mgt_for_v1_4_cal_inst0_reset_r[0]) + ); + FDR plm_v4f_mgt_for_v1_4_cal_inst0_sd_state_7_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(plm_v4f_mgt_for_v1_4_cal_inst0_sd_next_state_0_i_a2_0_a3[7]), + .Q(plm_v4f_mgt_for_v1_4_cal_inst0_sd_state_7__463), + .R(plm_v4f_mgt_for_v1_4_cal_inst0_reset_r[0]) + ); + FDR plm_v4f_mgt_for_v1_4_cal_inst0_sd_state_8_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(plm_v4f_mgt_for_v1_4_cal_inst0_N_1048_i_461), + .Q(plm_v4f_mgt_for_v1_4_cal_inst0_sd_state_8__462), + .R(plm_v4f_mgt_for_v1_4_cal_inst0_reset_r[0]) + ); + FDR plm_v4f_mgt_for_v1_4_cal_inst0_sd_state_9_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(plm_v4f_mgt_for_v1_4_cal_inst0_sd_next_state_0_sqmuxa_2), + .Q(plm_v4f_mgt_for_v1_4_cal_inst0_sd_state_9__460), + .R(plm_v4f_mgt_for_v1_4_cal_inst0_reset_r[0]) + ); + FDR plm_v4f_mgt_for_v1_4_cal_inst0_sd_state_10_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(plm_v4f_mgt_for_v1_4_cal_inst0_N_680_i_458), + .Q(plm_v4f_mgt_for_v1_4_cal_inst0_sd_state_10__459), + .R(plm_v4f_mgt_for_v1_4_cal_inst0_reset_r[0]) + ); + FDR plm_v4f_mgt_for_v1_4_cal_inst0_sd_state_12_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(plm_v4f_mgt_for_v1_4_cal_inst0_sd_next_state_0_sqmuxa_3), + .Q(plm_v4f_mgt_for_v1_4_cal_inst0_sd_state_12__456), + .R(plm_v4f_mgt_for_v1_4_cal_inst0_reset_r[0]) + ); + FDR plm_v4f_mgt_for_v1_4_cal_inst0_sd_state_13_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(plm_v4f_mgt_for_v1_4_cal_inst0_N_1047_i_454), + .Q(plm_v4f_mgt_for_v1_4_cal_inst0_sd_state_13__455), + .R(plm_v4f_mgt_for_v1_4_cal_inst0_reset_r[0]) + ); + FDR plm_v4f_mgt_for_v1_4_cal_inst0_GT_DEN ( + .C(NlwRenamedSig_OI_trn_clk), + .D(plm_v4f_mgt_for_v1_4_cal_inst0_N_578_i), + .Q(plm_v4f_mgt_gt0_den), + .R(plm_v4f_mgt_for_v1_4_cal_inst0_reset_r[0]) + ); + FDR plm_v4f_mgt_for_v1_4_cal_inst0_sd_write ( + .C(NlwRenamedSig_OI_trn_clk), + .D(plm_v4f_mgt_for_v1_4_cal_inst0_N_744_i_453), + .Q(plm_v4f_mgt_for_v1_4_cal_inst0_sd_write_473), + .R(plm_v4f_mgt_for_v1_4_cal_inst0_N_746_i_449) + ); + FDR plm_v4f_mgt_for_v1_4_cal_inst0_sd_read ( + .C(NlwRenamedSig_OI_trn_clk), + .D(plm_v4f_mgt_for_v1_4_cal_inst0_N_745_i_452), + .Q(plm_v4f_mgt_for_v1_4_cal_inst0_sd_read_474), + .R(plm_v4f_mgt_for_v1_4_cal_inst0_N_746_i_449) + ); + FDR plm_v4f_mgt_for_v1_4_cal_inst0_sd_req ( + .C(NlwRenamedSig_OI_trn_clk), + .D(plm_v4f_mgt_for_v1_4_cal_inst0_N_729_i_451), + .Q(plm_v4f_mgt_for_v1_4_cal_inst0_sd_req_448), + .R(plm_v4f_mgt_for_v1_4_cal_inst0_N_746_i_449) + ); + FDRE plm_v4f_mgt_for_v1_4_cal_inst0_sd_state_11_ ( + .CE(plm_v4f_mgt_for_v1_4_cal_inst0_sd_drp_done_469), + .C(NlwRenamedSig_OI_trn_clk), + .D(plm_v4f_mgt_for_v1_4_cal_inst0_sd_state_10__459), + .Q(plm_v4f_mgt_for_v1_4_cal_inst0_sd_state_11__457), + .R(plm_v4f_mgt_for_v1_4_cal_inst0_reset_r[0]) + ); + FDRE plm_v4f_mgt_for_v1_4_cal_inst0_sd_state_4_ ( + .CE(plm_v4f_mgt_for_v1_4_cal_inst0_sd_drp_done_469), + .C(NlwRenamedSig_OI_trn_clk), + .D(plm_v4f_mgt_for_v1_4_cal_inst0_sd_state_3__468), + .Q(plm_v4f_mgt_for_v1_4_cal_inst0_sd_state_4__467), + .R(plm_v4f_mgt_for_v1_4_cal_inst0_reset_r[0]) + ); + FDSE plm_v4f_mgt_for_v1_4_cal_inst0_sd_state_0_ ( + .CE(plm_v4f_mgt_for_v1_4_cal_inst0_sd_state_13__455), + .C(NlwRenamedSig_OI_trn_clk), + .D(plm_v4f_mgt_for_v1_4_cal_inst0_sd_drp_done_469), + .Q(plm_v4f_mgt_for_v1_4_cal_inst0_sd_state_0__450), + .S(plm_v4f_mgt_for_v1_4_cal_inst0_reset_r[0]) + ); + FDR plm_v4f_mgt_for_v1_4_cal_inst0_sd_drp_done ( + .C(NlwRenamedSig_OI_trn_clk), + .D(plm_v4f_mgt_gt0_drdy), + .Q(plm_v4f_mgt_for_v1_4_cal_inst0_sd_drp_done_469), + .R(plm_v4f_mgt_for_v1_4_cal_inst0_cb_state_i[2]) + ); + defparam plm_v4f_mgt_for_v1_4_cal_inst0_cb_state_4_i_o2_1_.INIT = 4'h8; + LUT2 plm_v4f_mgt_for_v1_4_cal_inst0_cb_state_4_i_o2_1_ ( + .I0(plm_v4f_mgt_for_v1_4_cal_inst0_cb_state[1]), + .I1(plm_v4f_mgt_for_v1_4_cal_inst0_sd_req_448), + .O(plm_v4f_mgt_for_v1_4_cal_inst0_N_800_i) + ); + defparam plm_v4f_mgt_for_v1_4_cal_inst0_sd_write_3_0_a2_0_o3.INIT = 4'h1; + LUT2 plm_v4f_mgt_for_v1_4_cal_inst0_sd_write_3_0_a2_0_o3 ( + .I0(plm_v4f_mgt_for_v1_4_cal_inst0_sd_state_6__465), + .I1(plm_v4f_mgt_for_v1_4_cal_inst0_sd_state_10__459), + .O(plm_v4f_mgt_for_v1_4_cal_inst0_N_669_i) + ); + defparam plm_v4f_mgt_for_v1_4_cal_inst0_cb_state_4_i_o2_0_1_.INIT = 4'h1; + LUT2 plm_v4f_mgt_for_v1_4_cal_inst0_cb_state_4_i_o2_0_1_ ( + .I0(plm_v4f_mgt_for_v1_4_cal_inst0_cb_state[2]), + .I1(plm_v4f_mgt_for_v1_4_cal_inst0_cb_state[3]), + .O(plm_v4f_mgt_for_v1_4_cal_inst0_cb_state_4_i_o2_0[1]) + ); + defparam plm_v4f_mgt_for_v1_4_cal_inst0_N_746_i.INIT = 4'hE; + LUT2 plm_v4f_mgt_for_v1_4_cal_inst0_N_746_i ( + .I0(plm_v4f_mgt_for_v1_4_cal_inst0_sd_drp_done_469), + .I1(plm_v4f_mgt_for_v1_4_cal_inst0_sd_state_0__450), + .O(plm_v4f_mgt_for_v1_4_cal_inst0_N_746_i_449) + ); + defparam plm_v4f_mgt_for_v1_4_cal_inst0_sd_wr_wreg_9_0_0_o2_12_.INIT = 8'h80; + LUT3 plm_v4f_mgt_for_v1_4_cal_inst0_sd_wr_wreg_9_0_0_o2_12_ ( + .I0(plm_v4f_mgt_for_v1_4_cal_inst0_cb_state[2]), + .I1(plm_v4f_mgt_for_v1_4_cal_inst0_sd_read_474), + .I2(plm_v4f_mgt_gt0_drdy), + .O(plm_v4f_mgt_for_v1_4_cal_inst0_N_660_i) + ); + defparam plm_v4f_mgt_for_v1_4_cal_inst0_GT_DADDR_5_i_0_o2_5_.INIT = 8'h02; + LUT3 plm_v4f_mgt_for_v1_4_cal_inst0_GT_DADDR_5_i_0_o2_5_ ( + .I0(plm_v4f_mgt_for_v1_4_cal_inst0_N_669_i), + .I1(plm_v4f_mgt_for_v1_4_cal_inst0_sd_state_4__467), + .I2(plm_v4f_mgt_for_v1_4_cal_inst0_sd_state_8__462), + .O(plm_v4f_mgt_for_v1_4_cal_inst0_N_670_i) + ); + defparam plm_v4f_mgt_for_v1_4_cal_inst0_GT_DEN_3_i_a2.INIT = 16'h1113; + LUT4 plm_v4f_mgt_for_v1_4_cal_inst0_GT_DEN_3_i_a2 ( + .I0(plm_v4f_mgt_for_v1_4_cal_inst0_cb_state[2]), + .I1(plm_v4f_mgt_for_v1_4_cal_inst0_cb_state[3]), + .I2(plm_v4f_mgt_for_v1_4_cal_inst0_sd_read_474), + .I3(plm_v4f_mgt_for_v1_4_cal_inst0_sd_write_473), + .O(plm_v4f_mgt_for_v1_4_cal_inst0_GT_DEN_3_i_a2_478) + ); + defparam plm_v4f_mgt_for_v1_4_cal_inst0_N_356_i_0.INIT = 4'h1; + LUT2 plm_v4f_mgt_for_v1_4_cal_inst0_N_356_i_0 ( + .I0(plm_v4f_mgt_for_v1_4_cal_inst0_N_670_i), + .I1(plm_v4f_mgt_for_v1_4_cal_inst0_cb_state[3]), + .O(plm_v4f_mgt_for_v1_4_cal_inst0_N_356_i_i) + ); + defparam plm_v4f_mgt_for_v1_4_cal_inst0_sd_wr_wreg_9_i_i_m2_1_.INIT = 8'h1B; + LUT3_L plm_v4f_mgt_for_v1_4_cal_inst0_sd_wr_wreg_9_i_i_m2_1_ ( + .I0(plm_v4f_mgt_for_v1_4_cal_inst0_N_660_i), + .I1(plm_v4f_mgt_for_v1_4_cal_inst0_sd_state_5__466), + .I2(plm_v4f_mgt_gt0_di[1]), + .LO(plm_v4f_mgt_for_v1_4_cal_inst0_sd_wr_wreg_9_i_i_m2[1]) + ); + defparam plm_v4f_mgt_for_v1_4_cal_inst0_N_1050_i.INIT = 16'h3733; + LUT4_L plm_v4f_mgt_for_v1_4_cal_inst0_N_1050_i ( + .I0(plm_v4f_mgt_for_v1_4_cal_inst0_N_660_i), + .I1(plm_v4f_mgt_for_v1_4_cal_inst0_sd_wr_wreg_9_i_i_m2[1]), + .I2(plm_v4f_mgt_for_v1_4_cal_inst0_sd_state_9__460), + .I3(plm_v4f_mgt_for_v1_4_cal_inst0_sd_wr_wreg[1]), + .LO(plm_v4f_mgt_for_v1_4_cal_inst0_N_1050_i_480) + ); + defparam plm_v4f_mgt_for_v1_4_cal_inst0_cb_state_4_0_a3_3_.INIT = 8'h02; + LUT3_L plm_v4f_mgt_for_v1_4_cal_inst0_cb_state_4_0_a3_3_ ( + .I0(plm_v4f_mgt_for_v1_4_cal_inst0_cb_state[3]), + .I1(plm_v4f_mgt_for_v1_4_cal_inst0_gt_drdy_r_479), + .I2(plm_v4f_mgt_for_v1_4_cal_inst0_reset_r[0]), + .LO(plm_v4f_mgt_for_v1_4_cal_inst0_cb_state_4[3]) + ); + defparam plm_v4f_mgt_for_v1_4_cal_inst0_cb_state_4_i_2_.INIT = 16'h00AE; + LUT4_L plm_v4f_mgt_for_v1_4_cal_inst0_cb_state_4_i_2_ ( + .I0(plm_v4f_mgt_for_v1_4_cal_inst0_N_800_i), + .I1(plm_v4f_mgt_for_v1_4_cal_inst0_cb_state[2]), + .I2(plm_v4f_mgt_for_v1_4_cal_inst0_gt_drdy_r_479), + .I3(plm_v4f_mgt_for_v1_4_cal_inst0_reset_r[0]), + .LO(plm_v4f_mgt_for_v1_4_cal_inst0_N_583_i) + ); + defparam plm_v4f_mgt_for_v1_4_cal_inst0_cb_state_4_i_1_.INIT = 16'h0054; + LUT4_L plm_v4f_mgt_for_v1_4_cal_inst0_cb_state_4_i_1_ ( + .I0(plm_v4f_mgt_for_v1_4_cal_inst0_N_800_i), + .I1(plm_v4f_mgt_for_v1_4_cal_inst0_cb_state_4_i_o2_0[1]), + .I2(plm_v4f_mgt_for_v1_4_cal_inst0_gt_drdy_r_479), + .I3(plm_v4f_mgt_for_v1_4_cal_inst0_reset_r[0]), + .LO(plm_v4f_mgt_for_v1_4_cal_inst0_N_581_i) + ); + defparam plm_v4f_mgt_for_v1_4_cal_inst0_N_1053_i.INIT = 16'hBA10; + LUT4_L plm_v4f_mgt_for_v1_4_cal_inst0_N_1053_i ( + .I0(plm_v4f_mgt_for_v1_4_cal_inst0_N_660_i), + .I1(plm_v4f_mgt_for_v1_4_cal_inst0_sd_state_12__456), + .I2(plm_v4f_mgt_for_v1_4_cal_inst0_sd_wr_wreg[12]), + .I3(plm_v4f_mgt_gt0_di[12]), + .LO(plm_v4f_mgt_for_v1_4_cal_inst0_N_1053_i_482) + ); + defparam plm_v4f_mgt_for_v1_4_cal_inst0_gt_do_r_4_i_m2_0_a3_15_.INIT = 4'h8; + LUT2_L plm_v4f_mgt_for_v1_4_cal_inst0_gt_do_r_4_i_m2_0_a3_15_ ( + .I0(plm_v4f_mgt_for_v1_4_cal_inst0_cb_state[2]), + .I1(plm_v4f_mgt_for_v1_4_cal_inst0_sd_wr_wreg[15]), + .LO(plm_v4f_mgt_for_v1_4_cal_inst0_gt_do_r_4_i_m2_0_a3[15]) + ); + defparam plm_v4f_mgt_for_v1_4_cal_inst0_gt_do_r_4_i_m2_0_a3_14_.INIT = 4'h8; + LUT2_L plm_v4f_mgt_for_v1_4_cal_inst0_gt_do_r_4_i_m2_0_a3_14_ ( + .I0(plm_v4f_mgt_for_v1_4_cal_inst0_cb_state[2]), + .I1(plm_v4f_mgt_for_v1_4_cal_inst0_sd_wr_wreg[14]), + .LO(plm_v4f_mgt_for_v1_4_cal_inst0_gt_do_r_4_i_m2_0_a3[14]) + ); + defparam plm_v4f_mgt_for_v1_4_cal_inst0_gt_do_r_4_i_m2_0_a3_13_.INIT = 4'h8; + LUT2_L plm_v4f_mgt_for_v1_4_cal_inst0_gt_do_r_4_i_m2_0_a3_13_ ( + .I0(plm_v4f_mgt_for_v1_4_cal_inst0_cb_state[2]), + .I1(plm_v4f_mgt_for_v1_4_cal_inst0_sd_wr_wreg[13]), + .LO(plm_v4f_mgt_for_v1_4_cal_inst0_gt_do_r_4_i_m2_0_a3[13]) + ); + defparam plm_v4f_mgt_for_v1_4_cal_inst0_gt_do_r_4_i_m2_0_a3_12_.INIT = 4'h8; + LUT2_L plm_v4f_mgt_for_v1_4_cal_inst0_gt_do_r_4_i_m2_0_a3_12_ ( + .I0(plm_v4f_mgt_for_v1_4_cal_inst0_cb_state[2]), + .I1(plm_v4f_mgt_for_v1_4_cal_inst0_sd_wr_wreg[12]), + .LO(plm_v4f_mgt_for_v1_4_cal_inst0_gt_do_r_4_i_m2_0_a3[12]) + ); + defparam plm_v4f_mgt_for_v1_4_cal_inst0_gt_do_r_4_i_m2_0_a3_11_.INIT = 4'h8; + LUT2_L plm_v4f_mgt_for_v1_4_cal_inst0_gt_do_r_4_i_m2_0_a3_11_ ( + .I0(plm_v4f_mgt_for_v1_4_cal_inst0_cb_state[2]), + .I1(plm_v4f_mgt_for_v1_4_cal_inst0_sd_wr_wreg[11]), + .LO(plm_v4f_mgt_for_v1_4_cal_inst0_gt_do_r_4_i_m2_0_a3[11]) + ); + defparam plm_v4f_mgt_for_v1_4_cal_inst0_gt_do_r_4_i_m2_0_a3_10_.INIT = 4'h8; + LUT2_L plm_v4f_mgt_for_v1_4_cal_inst0_gt_do_r_4_i_m2_0_a3_10_ ( + .I0(plm_v4f_mgt_for_v1_4_cal_inst0_cb_state[2]), + .I1(plm_v4f_mgt_for_v1_4_cal_inst0_sd_wr_wreg[10]), + .LO(plm_v4f_mgt_for_v1_4_cal_inst0_gt_do_r_4_i_m2_0_a3[10]) + ); + defparam plm_v4f_mgt_for_v1_4_cal_inst0_gt_do_r_4_i_m2_0_a3_9_.INIT = 4'h8; + LUT2_L plm_v4f_mgt_for_v1_4_cal_inst0_gt_do_r_4_i_m2_0_a3_9_ ( + .I0(plm_v4f_mgt_for_v1_4_cal_inst0_cb_state[2]), + .I1(plm_v4f_mgt_for_v1_4_cal_inst0_sd_wr_wreg[9]), + .LO(plm_v4f_mgt_for_v1_4_cal_inst0_gt_do_r_4_i_m2_0_a3[9]) + ); + defparam plm_v4f_mgt_for_v1_4_cal_inst0_gt_do_r_4_i_m2_0_a3_8_.INIT = 4'h8; + LUT2_L plm_v4f_mgt_for_v1_4_cal_inst0_gt_do_r_4_i_m2_0_a3_8_ ( + .I0(plm_v4f_mgt_for_v1_4_cal_inst0_cb_state[2]), + .I1(plm_v4f_mgt_for_v1_4_cal_inst0_sd_wr_wreg[8]), + .LO(plm_v4f_mgt_for_v1_4_cal_inst0_gt_do_r_4_i_m2_0_a3[8]) + ); + defparam plm_v4f_mgt_for_v1_4_cal_inst0_gt_do_r_4_i_m2_0_a3_7_.INIT = 4'h8; + LUT2_L plm_v4f_mgt_for_v1_4_cal_inst0_gt_do_r_4_i_m2_0_a3_7_ ( + .I0(plm_v4f_mgt_for_v1_4_cal_inst0_cb_state[2]), + .I1(plm_v4f_mgt_for_v1_4_cal_inst0_sd_wr_wreg[7]), + .LO(plm_v4f_mgt_for_v1_4_cal_inst0_gt_do_r_4_i_m2_0_a3[7]) + ); + defparam plm_v4f_mgt_for_v1_4_cal_inst0_gt_do_r_4_i_m2_0_a3_6_.INIT = 4'h8; + LUT2_L plm_v4f_mgt_for_v1_4_cal_inst0_gt_do_r_4_i_m2_0_a3_6_ ( + .I0(plm_v4f_mgt_for_v1_4_cal_inst0_cb_state[2]), + .I1(plm_v4f_mgt_for_v1_4_cal_inst0_sd_wr_wreg[6]), + .LO(plm_v4f_mgt_for_v1_4_cal_inst0_gt_do_r_4_i_m2_0_a3[6]) + ); + defparam plm_v4f_mgt_for_v1_4_cal_inst0_gt_do_r_4_i_m2_0_a3_5_.INIT = 4'h8; + LUT2_L plm_v4f_mgt_for_v1_4_cal_inst0_gt_do_r_4_i_m2_0_a3_5_ ( + .I0(plm_v4f_mgt_for_v1_4_cal_inst0_cb_state[2]), + .I1(plm_v4f_mgt_for_v1_4_cal_inst0_sd_wr_wreg[5]), + .LO(plm_v4f_mgt_for_v1_4_cal_inst0_gt_do_r_4_i_m2_0_a3[5]) + ); + defparam plm_v4f_mgt_for_v1_4_cal_inst0_gt_do_r_4_i_m2_0_a3_4_.INIT = 4'h8; + LUT2_L plm_v4f_mgt_for_v1_4_cal_inst0_gt_do_r_4_i_m2_0_a3_4_ ( + .I0(plm_v4f_mgt_for_v1_4_cal_inst0_cb_state[2]), + .I1(plm_v4f_mgt_for_v1_4_cal_inst0_sd_wr_wreg[4]), + .LO(plm_v4f_mgt_for_v1_4_cal_inst0_gt_do_r_4_i_m2_0_a3[4]) + ); + defparam plm_v4f_mgt_for_v1_4_cal_inst0_gt_do_r_4_i_m2_0_a3_3_.INIT = 4'h8; + LUT2_L plm_v4f_mgt_for_v1_4_cal_inst0_gt_do_r_4_i_m2_0_a3_3_ ( + .I0(plm_v4f_mgt_for_v1_4_cal_inst0_cb_state[2]), + .I1(plm_v4f_mgt_for_v1_4_cal_inst0_sd_wr_wreg[3]), + .LO(plm_v4f_mgt_for_v1_4_cal_inst0_gt_do_r_4_i_m2_0_a3[3]) + ); + defparam plm_v4f_mgt_for_v1_4_cal_inst0_gt_do_r_4_i_m2_0_a3_2_.INIT = 4'h8; + LUT2_L plm_v4f_mgt_for_v1_4_cal_inst0_gt_do_r_4_i_m2_0_a3_2_ ( + .I0(plm_v4f_mgt_for_v1_4_cal_inst0_cb_state[2]), + .I1(plm_v4f_mgt_for_v1_4_cal_inst0_sd_wr_wreg[2]), + .LO(plm_v4f_mgt_for_v1_4_cal_inst0_gt_do_r_4_i_m2_0_a3[2]) + ); + defparam plm_v4f_mgt_for_v1_4_cal_inst0_gt_do_r_4_i_m2_0_a3_1_.INIT = 4'h8; + LUT2_L plm_v4f_mgt_for_v1_4_cal_inst0_gt_do_r_4_i_m2_0_a3_1_ ( + .I0(plm_v4f_mgt_for_v1_4_cal_inst0_cb_state[2]), + .I1(plm_v4f_mgt_for_v1_4_cal_inst0_sd_wr_wreg[1]), + .LO(plm_v4f_mgt_for_v1_4_cal_inst0_gt_do_r_4_i_m2_0_a3[1]) + ); + defparam plm_v4f_mgt_for_v1_4_cal_inst0_gt_do_r_4_i_m2_0_a3_0_.INIT = 4'h8; + LUT2_L plm_v4f_mgt_for_v1_4_cal_inst0_gt_do_r_4_i_m2_0_a3_0_ ( + .I0(plm_v4f_mgt_for_v1_4_cal_inst0_cb_state[2]), + .I1(plm_v4f_mgt_for_v1_4_cal_inst0_sd_wr_wreg[0]), + .LO(plm_v4f_mgt_for_v1_4_cal_inst0_gt_do_r_4_i_m2_0_a3[0]) + ); + defparam plm_v4f_mgt_for_v1_4_cal_inst0_N_729_i.INIT = 4'hE; + LUT2_L plm_v4f_mgt_for_v1_4_cal_inst0_N_729_i ( + .I0(plm_v4f_mgt_for_v1_4_cal_inst0_sd_read_474), + .I1(plm_v4f_mgt_for_v1_4_cal_inst0_sd_write_473), + .LO(plm_v4f_mgt_for_v1_4_cal_inst0_N_729_i_451) + ); + defparam plm_v4f_mgt_for_v1_4_cal_inst0_N_745_i.INIT = 8'hFE; + LUT3_L plm_v4f_mgt_for_v1_4_cal_inst0_N_745_i ( + .I0(plm_v4f_mgt_for_v1_4_cal_inst0_sd_state_4__467), + .I1(plm_v4f_mgt_for_v1_4_cal_inst0_sd_state_8__462), + .I2(plm_v4f_mgt_for_v1_4_cal_inst0_sd_state_11__457), + .LO(plm_v4f_mgt_for_v1_4_cal_inst0_N_745_i_452) + ); + defparam plm_v4f_mgt_for_v1_4_cal_inst0_N_744_i.INIT = 8'hFD; + LUT3_L plm_v4f_mgt_for_v1_4_cal_inst0_N_744_i ( + .I0(plm_v4f_mgt_for_v1_4_cal_inst0_N_669_i), + .I1(plm_v4f_mgt_for_v1_4_cal_inst0_sd_state_3__468), + .I2(plm_v4f_mgt_for_v1_4_cal_inst0_sd_state_13__455), + .LO(plm_v4f_mgt_for_v1_4_cal_inst0_N_744_i_453) + ); + defparam plm_v4f_mgt_for_v1_4_cal_inst0_GT_DEN_3_i.INIT = 4'h4; + LUT2_L plm_v4f_mgt_for_v1_4_cal_inst0_GT_DEN_3_i ( + .I0(plm_v4f_mgt_for_v1_4_cal_inst0_GT_DEN_3_i_a2_478), + .I1(plm_v4f_mgt_for_v1_4_cal_inst0_drp_state_0__477), + .LO(plm_v4f_mgt_for_v1_4_cal_inst0_N_578_i) + ); + defparam plm_v4f_mgt_for_v1_4_cal_inst0_GT_DADDR_5_i_0_5_.INIT = 4'h2; + LUT2_L plm_v4f_mgt_for_v1_4_cal_inst0_GT_DADDR_5_i_0_5_ ( + .I0(plm_v4f_mgt_for_v1_4_cal_inst0_N_356_i_i), + .I1(cfg_cfg_5072[509]), + .LO(plm_v4f_mgt_for_v1_4_cal_inst0_N_297_i) + ); + defparam plm_v4f_mgt_for_v1_4_cal_inst0_cb_state_i_3_.INIT = 4'h1; + LUT1_L plm_v4f_mgt_for_v1_4_cal_inst0_cb_state_i_3_ ( + .I0(plm_v4f_mgt_for_v1_4_cal_inst0_cb_state[3]), + .LO(plm_v4f_mgt_for_v1_4_cal_inst0_cb_state_i[3]) + ); + defparam plm_v4f_mgt_for_v1_4_cal_inst0_GT_DADDR_5_i_0_2_.INIT = 8'h23; + LUT3_L plm_v4f_mgt_for_v1_4_cal_inst0_GT_DADDR_5_i_0_2_ ( + .I0(plm_v4f_mgt_for_v1_4_cal_inst0_N_670_i), + .I1(plm_v4f_mgt_for_v1_4_cal_inst0_cb_state[3]), + .I2(cfg_cfg_5072[509]), + .LO(plm_v4f_mgt_for_v1_4_cal_inst0_N_293_i) + ); + defparam plm_v4f_mgt_for_v1_4_cal_inst0_GT_DADDR_5_i_i_a3_1_.INIT = 8'h20; + LUT3_L plm_v4f_mgt_for_v1_4_cal_inst0_GT_DADDR_5_i_i_a3_1_ ( + .I0(plm_v4f_mgt_for_v1_4_cal_inst0_N_670_i), + .I1(plm_v4f_mgt_for_v1_4_cal_inst0_cb_state[3]), + .I2(cfg_cfg_5072[509]), + .LO(plm_v4f_mgt_for_v1_4_cal_inst0_GT_DADDR_5_i_i_a3[1]) + ); + defparam plm_v4f_mgt_for_v1_4_cal_inst0_N_1047_i.INIT = 8'hDC; + LUT3_L plm_v4f_mgt_for_v1_4_cal_inst0_N_1047_i ( + .I0(plm_v4f_mgt_for_v1_4_cal_inst0_sd_drp_done_469), + .I1(plm_v4f_mgt_for_v1_4_cal_inst0_sd_state_12__456), + .I2(plm_v4f_mgt_for_v1_4_cal_inst0_sd_state_13__455), + .LO(plm_v4f_mgt_for_v1_4_cal_inst0_N_1047_i_454) + ); + defparam plm_v4f_mgt_for_v1_4_cal_inst0_sd_next_state_0_sqmuxa_3_0_a2_0_a3.INIT = 4'h8; + LUT2_L plm_v4f_mgt_for_v1_4_cal_inst0_sd_next_state_0_sqmuxa_3_0_a2_0_a3 ( + .I0(plm_v4f_mgt_for_v1_4_cal_inst0_sd_drp_done_469), + .I1(plm_v4f_mgt_for_v1_4_cal_inst0_sd_state_11__457), + .LO(plm_v4f_mgt_for_v1_4_cal_inst0_sd_next_state_0_sqmuxa_3) + ); + defparam plm_v4f_mgt_for_v1_4_cal_inst0_N_680_i.INIT = 8'h5C; + LUT3_L plm_v4f_mgt_for_v1_4_cal_inst0_N_680_i ( + .I0(plm_v4f_mgt_for_v1_4_cal_inst0_sd_drp_done_469), + .I1(plm_v4f_mgt_for_v1_4_cal_inst0_sd_state_9__460), + .I2(plm_v4f_mgt_for_v1_4_cal_inst0_sd_state_10__459), + .LO(plm_v4f_mgt_for_v1_4_cal_inst0_N_680_i_458) + ); + defparam plm_v4f_mgt_for_v1_4_cal_inst0_sd_next_state_0_sqmuxa_2_0_a2_0_a3.INIT = 4'h8; + LUT2_L plm_v4f_mgt_for_v1_4_cal_inst0_sd_next_state_0_sqmuxa_2_0_a2_0_a3 ( + .I0(plm_v4f_mgt_for_v1_4_cal_inst0_sd_drp_done_469), + .I1(plm_v4f_mgt_for_v1_4_cal_inst0_sd_state_8__462), + .LO(plm_v4f_mgt_for_v1_4_cal_inst0_sd_next_state_0_sqmuxa_2) + ); + defparam plm_v4f_mgt_for_v1_4_cal_inst0_N_1048_i.INIT = 8'hDC; + LUT3_L plm_v4f_mgt_for_v1_4_cal_inst0_N_1048_i ( + .I0(plm_v4f_mgt_for_v1_4_cal_inst0_sd_drp_done_469), + .I1(plm_v4f_mgt_for_v1_4_cal_inst0_sd_state_7__463), + .I2(plm_v4f_mgt_for_v1_4_cal_inst0_sd_state_8__462), + .LO(plm_v4f_mgt_for_v1_4_cal_inst0_N_1048_i_461) + ); + defparam plm_v4f_mgt_for_v1_4_cal_inst0_sd_next_state_0_i_a2_0_a3_7_.INIT = 4'h8; + LUT2_L plm_v4f_mgt_for_v1_4_cal_inst0_sd_next_state_0_i_a2_0_a3_7_ ( + .I0(plm_v4f_mgt_for_v1_4_cal_inst0_sd_drp_done_469), + .I1(plm_v4f_mgt_for_v1_4_cal_inst0_sd_state_6__465), + .LO(plm_v4f_mgt_for_v1_4_cal_inst0_sd_next_state_0_i_a2_0_a3[7]) + ); + defparam plm_v4f_mgt_for_v1_4_cal_inst0_N_682_i.INIT = 8'h5C; + LUT3_L plm_v4f_mgt_for_v1_4_cal_inst0_N_682_i ( + .I0(plm_v4f_mgt_for_v1_4_cal_inst0_sd_drp_done_469), + .I1(plm_v4f_mgt_for_v1_4_cal_inst0_sd_state_5__466), + .I2(plm_v4f_mgt_for_v1_4_cal_inst0_sd_state_6__465), + .LO(plm_v4f_mgt_for_v1_4_cal_inst0_N_682_i_464) + ); + defparam plm_v4f_mgt_for_v1_4_cal_inst0_sd_next_state_0_sqmuxa_1_0_a2_0_a3.INIT = 4'h8; + LUT2_L plm_v4f_mgt_for_v1_4_cal_inst0_sd_next_state_0_sqmuxa_1_0_a2_0_a3 ( + .I0(plm_v4f_mgt_for_v1_4_cal_inst0_sd_drp_done_469), + .I1(plm_v4f_mgt_for_v1_4_cal_inst0_sd_state_4__467), + .LO(plm_v4f_mgt_for_v1_4_cal_inst0_sd_next_state_0_sqmuxa_1) + ); + defparam plm_v4f_mgt_for_v1_4_cal_inst0_sd_next_state_0_m4_i_m2_i_m2_3_.INIT = 4'h4; + LUT2_L plm_v4f_mgt_for_v1_4_cal_inst0_sd_next_state_0_m4_i_m2_i_m2_3_ ( + .I0(plm_v4f_mgt_for_v1_4_cal_inst0_sd_drp_done_469), + .I1(plm_v4f_mgt_for_v1_4_cal_inst0_sd_state_3__468), + .LO(plm_v4f_mgt_for_v1_4_cal_inst0_N_683_i) + ); + defparam plm_v4f_mgt_for_v1_4_cal_inst0_drp_next_state_0_sqmuxa_0_a3.INIT = 4'h8; + LUT2_L plm_v4f_mgt_for_v1_4_cal_inst0_drp_next_state_0_sqmuxa_0_a3 ( + .I0(plm_v4f_mgt_for_v1_4_cal_inst0_drp_state_3__471), + .I1(plm_v4f_mgt_for_v1_4_cal_inst0_gt_drdy_r_479), + .LO(plm_v4f_mgt_for_v1_4_cal_inst0_drp_next_state_0_sqmuxa) + ); + defparam plm_v4f_mgt_for_v1_4_cal_inst0_N_1020_i.INIT = 16'hFFAE; + LUT4_L plm_v4f_mgt_for_v1_4_cal_inst0_N_1020_i ( + .I0(plm_v4f_mgt_for_v1_4_cal_inst0_drp_state_1__472), + .I1(plm_v4f_mgt_for_v1_4_cal_inst0_drp_state_3__471), + .I2(plm_v4f_mgt_for_v1_4_cal_inst0_gt_drdy_r_479), + .I3(plm_v4f_mgt_gt0_dwe), + .LO(plm_v4f_mgt_for_v1_4_cal_inst0_N_1020_i_470) + ); + defparam plm_v4f_mgt_for_v1_4_cal_inst0_drp_next_state_0_sqmuxa_1_0_a3.INIT = 8'h80; + LUT3_L plm_v4f_mgt_for_v1_4_cal_inst0_drp_next_state_0_sqmuxa_1_0_a3 ( + .I0(plm_v4f_mgt_for_v1_4_cal_inst0_cb_state[2]), + .I1(plm_v4f_mgt_for_v1_4_cal_inst0_drp_state_0__477), + .I2(plm_v4f_mgt_for_v1_4_cal_inst0_sd_write_473), + .LO(plm_v4f_mgt_for_v1_4_cal_inst0_drp_next_state_0_sqmuxa_1) + ); + defparam plm_v4f_mgt_for_v1_4_cal_inst0_drp_next_state_1_sqmuxa_1_i.INIT = 16'hE0C0; + LUT4_L plm_v4f_mgt_for_v1_4_cal_inst0_drp_next_state_1_sqmuxa_1_i ( + .I0(plm_v4f_mgt_for_v1_4_cal_inst0_cb_state[2]), + .I1(plm_v4f_mgt_for_v1_4_cal_inst0_cb_state[3]), + .I2(plm_v4f_mgt_for_v1_4_cal_inst0_drp_state_0__477), + .I3(plm_v4f_mgt_for_v1_4_cal_inst0_sd_read_474), + .LO(plm_v4f_mgt_for_v1_4_cal_inst0_N_576_i) + ); + defparam plm_v4f_mgt_for_v1_4_cal_inst0_N_1051_i.INIT = 8'hF8; + LUT3_L plm_v4f_mgt_for_v1_4_cal_inst0_N_1051_i ( + .I0(plm_v4f_mgt_for_v1_4_cal_inst0_GT_DEN_3_i_a2_478), + .I1(plm_v4f_mgt_for_v1_4_cal_inst0_drp_state_0__477), + .I2(plm_v4f_mgt_for_v1_4_cal_inst0_drp_state_4__476), + .LO(plm_v4f_mgt_for_v1_4_cal_inst0_N_1051_i_475) + ); + FD plm_v4f_mgt_for_v1_4_cal_inst0_gt_drdy_r ( + .C(NlwRenamedSig_OI_trn_clk), + .D(plm_v4f_mgt_gt0_drdy), + .Q(plm_v4f_mgt_for_v1_4_cal_inst0_gt_drdy_r_479) + ); + FDE plm_v4f_mgt_for_v1_4_cal_inst0_sd_wr_wreg_9_ ( + .CE(plm_v4f_mgt_for_v1_4_cal_inst0_N_660_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(plm_v4f_mgt_gt0_di[9]), + .Q(plm_v4f_mgt_for_v1_4_cal_inst0_sd_wr_wreg[9]) + ); + FDE plm_v4f_mgt_for_v1_4_cal_inst0_sd_wr_wreg_8_ ( + .CE(plm_v4f_mgt_for_v1_4_cal_inst0_N_660_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(plm_v4f_mgt_gt0_di[8]), + .Q(plm_v4f_mgt_for_v1_4_cal_inst0_sd_wr_wreg[8]) + ); + FDE plm_v4f_mgt_for_v1_4_cal_inst0_sd_wr_wreg_7_ ( + .CE(plm_v4f_mgt_for_v1_4_cal_inst0_N_660_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(plm_v4f_mgt_gt0_di[7]), + .Q(plm_v4f_mgt_for_v1_4_cal_inst0_sd_wr_wreg[7]) + ); + FDE plm_v4f_mgt_for_v1_4_cal_inst0_sd_wr_wreg_6_ ( + .CE(plm_v4f_mgt_for_v1_4_cal_inst0_N_660_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(plm_v4f_mgt_gt0_di[6]), + .Q(plm_v4f_mgt_for_v1_4_cal_inst0_sd_wr_wreg[6]) + ); + FDE plm_v4f_mgt_for_v1_4_cal_inst0_sd_wr_wreg_5_ ( + .CE(plm_v4f_mgt_for_v1_4_cal_inst0_N_660_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(plm_v4f_mgt_gt0_di[5]), + .Q(plm_v4f_mgt_for_v1_4_cal_inst0_sd_wr_wreg[5]) + ); + FDE plm_v4f_mgt_for_v1_4_cal_inst0_sd_wr_wreg_4_ ( + .CE(plm_v4f_mgt_for_v1_4_cal_inst0_N_660_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(plm_v4f_mgt_gt0_di[4]), + .Q(plm_v4f_mgt_for_v1_4_cal_inst0_sd_wr_wreg[4]) + ); + FDE plm_v4f_mgt_for_v1_4_cal_inst0_sd_wr_wreg_3_ ( + .CE(plm_v4f_mgt_for_v1_4_cal_inst0_N_660_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(plm_v4f_mgt_gt0_di[3]), + .Q(plm_v4f_mgt_for_v1_4_cal_inst0_sd_wr_wreg[3]) + ); + FDE plm_v4f_mgt_for_v1_4_cal_inst0_sd_wr_wreg_2_ ( + .CE(plm_v4f_mgt_for_v1_4_cal_inst0_N_660_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(plm_v4f_mgt_gt0_di[2]), + .Q(plm_v4f_mgt_for_v1_4_cal_inst0_sd_wr_wreg[2]) + ); + FD plm_v4f_mgt_for_v1_4_cal_inst0_sd_wr_wreg_1_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(plm_v4f_mgt_for_v1_4_cal_inst0_N_1050_i_480), + .Q(plm_v4f_mgt_for_v1_4_cal_inst0_sd_wr_wreg[1]) + ); + FDE plm_v4f_mgt_for_v1_4_cal_inst0_sd_wr_wreg_0_ ( + .CE(plm_v4f_mgt_for_v1_4_cal_inst0_N_660_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(plm_v4f_mgt_gt0_di[0]), + .Q(plm_v4f_mgt_for_v1_4_cal_inst0_sd_wr_wreg[0]) + ); + FDP plm_v4f_mgt_for_v1_4_cal_inst0_reset_r_1_ ( + .PRE(plm_v4f_mgt_N_435_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(plm_v4f_mgt_for_v1_4_cal_inst0_GND_481), + .Q(plm_v4f_mgt_for_v1_4_cal_inst1_reset_r[1]) + ); + FD plm_v4f_mgt_for_v1_4_cal_inst0_cb_state_3_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(plm_v4f_mgt_for_v1_4_cal_inst0_cb_state_4[3]), + .Q(plm_v4f_mgt_for_v1_4_cal_inst0_cb_state[3]) + ); + FD plm_v4f_mgt_for_v1_4_cal_inst0_cb_state_2_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(plm_v4f_mgt_for_v1_4_cal_inst0_N_583_i), + .Q(plm_v4f_mgt_for_v1_4_cal_inst0_cb_state[2]) + ); + FD plm_v4f_mgt_for_v1_4_cal_inst0_cb_state_1_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(plm_v4f_mgt_for_v1_4_cal_inst0_N_581_i), + .Q(plm_v4f_mgt_for_v1_4_cal_inst0_cb_state[1]) + ); + FDE plm_v4f_mgt_for_v1_4_cal_inst0_sd_wr_wreg_15_ ( + .CE(plm_v4f_mgt_for_v1_4_cal_inst0_N_660_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(plm_v4f_mgt_gt0_di[15]), + .Q(plm_v4f_mgt_for_v1_4_cal_inst0_sd_wr_wreg[15]) + ); + FDE plm_v4f_mgt_for_v1_4_cal_inst0_sd_wr_wreg_14_ ( + .CE(plm_v4f_mgt_for_v1_4_cal_inst0_N_660_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(plm_v4f_mgt_gt0_di[14]), + .Q(plm_v4f_mgt_for_v1_4_cal_inst0_sd_wr_wreg[14]) + ); + FDE plm_v4f_mgt_for_v1_4_cal_inst0_sd_wr_wreg_13_ ( + .CE(plm_v4f_mgt_for_v1_4_cal_inst0_N_660_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(plm_v4f_mgt_gt0_di[13]), + .Q(plm_v4f_mgt_for_v1_4_cal_inst0_sd_wr_wreg[13]) + ); + FD plm_v4f_mgt_for_v1_4_cal_inst0_sd_wr_wreg_12_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(plm_v4f_mgt_for_v1_4_cal_inst0_N_1053_i_482), + .Q(plm_v4f_mgt_for_v1_4_cal_inst0_sd_wr_wreg[12]) + ); + FDE plm_v4f_mgt_for_v1_4_cal_inst0_sd_wr_wreg_11_ ( + .CE(plm_v4f_mgt_for_v1_4_cal_inst0_N_660_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(plm_v4f_mgt_gt0_di[11]), + .Q(plm_v4f_mgt_for_v1_4_cal_inst0_sd_wr_wreg[11]) + ); + FDE plm_v4f_mgt_for_v1_4_cal_inst0_sd_wr_wreg_10_ ( + .CE(plm_v4f_mgt_for_v1_4_cal_inst0_N_660_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(plm_v4f_mgt_gt0_di[10]), + .Q(plm_v4f_mgt_for_v1_4_cal_inst0_sd_wr_wreg[10]) + ); + FDE plm_v4f_mgt_for_v1_4_cal_inst0_gt_do_r_15_ ( + .CE(plm_v4f_mgt_for_v1_4_cal_inst0_N_1031_i_483), + .C(NlwRenamedSig_OI_trn_clk), + .D(plm_v4f_mgt_for_v1_4_cal_inst0_gt_do_r_4_i_m2_0_a3[15]), + .Q(plm_v4f_mgt_gt0_do[15]) + ); + FDE plm_v4f_mgt_for_v1_4_cal_inst0_gt_do_r_14_ ( + .CE(plm_v4f_mgt_for_v1_4_cal_inst0_N_1031_i_483), + .C(NlwRenamedSig_OI_trn_clk), + .D(plm_v4f_mgt_for_v1_4_cal_inst0_gt_do_r_4_i_m2_0_a3[14]), + .Q(plm_v4f_mgt_gt0_do[14]) + ); + FDE plm_v4f_mgt_for_v1_4_cal_inst0_gt_do_r_13_ ( + .CE(plm_v4f_mgt_for_v1_4_cal_inst0_N_1031_i_483), + .C(NlwRenamedSig_OI_trn_clk), + .D(plm_v4f_mgt_for_v1_4_cal_inst0_gt_do_r_4_i_m2_0_a3[13]), + .Q(plm_v4f_mgt_gt0_do[13]) + ); + FDE plm_v4f_mgt_for_v1_4_cal_inst0_gt_do_r_12_ ( + .CE(plm_v4f_mgt_for_v1_4_cal_inst0_N_1031_i_483), + .C(NlwRenamedSig_OI_trn_clk), + .D(plm_v4f_mgt_for_v1_4_cal_inst0_gt_do_r_4_i_m2_0_a3[12]), + .Q(plm_v4f_mgt_gt0_do[12]) + ); + FDE plm_v4f_mgt_for_v1_4_cal_inst0_gt_do_r_11_ ( + .CE(plm_v4f_mgt_for_v1_4_cal_inst0_N_1031_i_483), + .C(NlwRenamedSig_OI_trn_clk), + .D(plm_v4f_mgt_for_v1_4_cal_inst0_gt_do_r_4_i_m2_0_a3[11]), + .Q(plm_v4f_mgt_gt0_do[11]) + ); + FDE plm_v4f_mgt_for_v1_4_cal_inst0_gt_do_r_10_ ( + .CE(plm_v4f_mgt_for_v1_4_cal_inst0_N_1031_i_483), + .C(NlwRenamedSig_OI_trn_clk), + .D(plm_v4f_mgt_for_v1_4_cal_inst0_gt_do_r_4_i_m2_0_a3[10]), + .Q(plm_v4f_mgt_gt0_do[10]) + ); + FDE plm_v4f_mgt_for_v1_4_cal_inst0_gt_do_r_9_ ( + .CE(plm_v4f_mgt_for_v1_4_cal_inst0_N_1031_i_483), + .C(NlwRenamedSig_OI_trn_clk), + .D(plm_v4f_mgt_for_v1_4_cal_inst0_gt_do_r_4_i_m2_0_a3[9]), + .Q(plm_v4f_mgt_gt0_do[9]) + ); + FDE plm_v4f_mgt_for_v1_4_cal_inst0_gt_do_r_8_ ( + .CE(plm_v4f_mgt_for_v1_4_cal_inst0_N_1031_i_483), + .C(NlwRenamedSig_OI_trn_clk), + .D(plm_v4f_mgt_for_v1_4_cal_inst0_gt_do_r_4_i_m2_0_a3[8]), + .Q(plm_v4f_mgt_gt0_do[8]) + ); + FDE plm_v4f_mgt_for_v1_4_cal_inst0_gt_do_r_7_ ( + .CE(plm_v4f_mgt_for_v1_4_cal_inst0_N_1031_i_483), + .C(NlwRenamedSig_OI_trn_clk), + .D(plm_v4f_mgt_for_v1_4_cal_inst0_gt_do_r_4_i_m2_0_a3[7]), + .Q(plm_v4f_mgt_gt0_do[7]) + ); + FDE plm_v4f_mgt_for_v1_4_cal_inst0_gt_do_r_6_ ( + .CE(plm_v4f_mgt_for_v1_4_cal_inst0_N_1031_i_483), + .C(NlwRenamedSig_OI_trn_clk), + .D(plm_v4f_mgt_for_v1_4_cal_inst0_gt_do_r_4_i_m2_0_a3[6]), + .Q(plm_v4f_mgt_gt0_do[6]) + ); + FDE plm_v4f_mgt_for_v1_4_cal_inst0_gt_do_r_5_ ( + .CE(plm_v4f_mgt_for_v1_4_cal_inst0_N_1031_i_483), + .C(NlwRenamedSig_OI_trn_clk), + .D(plm_v4f_mgt_for_v1_4_cal_inst0_gt_do_r_4_i_m2_0_a3[5]), + .Q(plm_v4f_mgt_gt0_do[5]) + ); + FDE plm_v4f_mgt_for_v1_4_cal_inst0_gt_do_r_4_ ( + .CE(plm_v4f_mgt_for_v1_4_cal_inst0_N_1031_i_483), + .C(NlwRenamedSig_OI_trn_clk), + .D(plm_v4f_mgt_for_v1_4_cal_inst0_gt_do_r_4_i_m2_0_a3[4]), + .Q(plm_v4f_mgt_gt0_do[4]) + ); + FDE plm_v4f_mgt_for_v1_4_cal_inst0_gt_do_r_3_ ( + .CE(plm_v4f_mgt_for_v1_4_cal_inst0_N_1031_i_483), + .C(NlwRenamedSig_OI_trn_clk), + .D(plm_v4f_mgt_for_v1_4_cal_inst0_gt_do_r_4_i_m2_0_a3[3]), + .Q(plm_v4f_mgt_gt0_do[3]) + ); + FDE plm_v4f_mgt_for_v1_4_cal_inst0_gt_do_r_2_ ( + .CE(plm_v4f_mgt_for_v1_4_cal_inst0_N_1031_i_483), + .C(NlwRenamedSig_OI_trn_clk), + .D(plm_v4f_mgt_for_v1_4_cal_inst0_gt_do_r_4_i_m2_0_a3[2]), + .Q(plm_v4f_mgt_gt0_do[2]) + ); + FDE plm_v4f_mgt_for_v1_4_cal_inst0_gt_do_r_1_ ( + .CE(plm_v4f_mgt_for_v1_4_cal_inst0_N_1031_i_483), + .C(NlwRenamedSig_OI_trn_clk), + .D(plm_v4f_mgt_for_v1_4_cal_inst0_gt_do_r_4_i_m2_0_a3[1]), + .Q(plm_v4f_mgt_gt0_do[1]) + ); + FDE plm_v4f_mgt_for_v1_4_cal_inst0_gt_do_r_0_ ( + .CE(plm_v4f_mgt_for_v1_4_cal_inst0_N_1031_i_483), + .C(NlwRenamedSig_OI_trn_clk), + .D(plm_v4f_mgt_for_v1_4_cal_inst0_gt_do_r_4_i_m2_0_a3[0]), + .Q(plm_v4f_mgt_gt0_do[0]) + ); + FDE plm_v4f_mgt_for_v1_4_cal_inst0_GT_DADDR_1_5_ ( + .CE(plm_v4f_mgt_for_v1_4_cal_inst0_N_1031_i_483), + .C(NlwRenamedSig_OI_trn_clk), + .D(plm_v4f_mgt_for_v1_4_cal_inst0_N_297_i), + .Q(plm_v4f_mgt_gt0_daddr[5]) + ); + FDE plm_v4f_mgt_for_v1_4_cal_inst0_GT_DADDR_1_3_ ( + .CE(plm_v4f_mgt_for_v1_4_cal_inst0_N_1031_i_483), + .C(NlwRenamedSig_OI_trn_clk), + .D(plm_v4f_mgt_for_v1_4_cal_inst0_cb_state_i[3]), + .Q(plm_v4f_mgt_gt0_daddr[3]) + ); + FDE plm_v4f_mgt_for_v1_4_cal_inst0_GT_DADDR_1_2_ ( + .CE(plm_v4f_mgt_for_v1_4_cal_inst0_N_1031_i_483), + .C(NlwRenamedSig_OI_trn_clk), + .D(plm_v4f_mgt_for_v1_4_cal_inst0_N_293_i), + .Q(plm_v4f_mgt_gt0_daddr[2]) + ); + FDE plm_v4f_mgt_for_v1_4_cal_inst0_GT_DADDR_1_1_ ( + .CE(plm_v4f_mgt_for_v1_4_cal_inst0_N_1031_i_483), + .C(NlwRenamedSig_OI_trn_clk), + .D(plm_v4f_mgt_for_v1_4_cal_inst0_GT_DADDR_5_i_i_a3[1]), + .Q(plm_v4f_mgt_gt0_daddr[1]) + ); + FDE plm_v4f_mgt_for_v1_4_cal_inst0_GT_DADDR_1_0_ ( + .CE(plm_v4f_mgt_for_v1_4_cal_inst0_N_1031_i_483), + .C(NlwRenamedSig_OI_trn_clk), + .D(plm_v4f_mgt_for_v1_4_cal_inst0_N_356_i_i), + .Q(plm_v4f_mgt_gt0_daddr[4]) + ); + INV plm_v4f_mgt_for_v1_4_cal_inst0_cb_state_i_2_ ( + .I(plm_v4f_mgt_for_v1_4_cal_inst0_cb_state[2]), + .O(plm_v4f_mgt_for_v1_4_cal_inst0_cb_state_i[2]) + ); + INV plm_v4f_mgt_for_v1_4_cal_inst0_N_1031_i ( + .I(plm_v4f_mgt_for_v1_4_cal_inst0_cb_state_4_i_o2_0[1]), + .O(plm_v4f_mgt_for_v1_4_cal_inst0_N_1031_i_483) + ); + VCC plm_v4f_mgt_for_v1_4_cal_inst1_VCC ( + .P(plm_v4f_mgt_for_v1_4_cal_inst1_VCC_484) + ); + GND plm_v4f_mgt_for_v1_4_cal_inst1_GND ( + .G(plm_v4f_mgt_for_v1_4_cal_inst1_GND_485) + ); + FDS plm_v4f_mgt_for_v1_4_cal_inst1_drp_state_0_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(plm_v4f_mgt_for_v1_4_cal_inst1_N_1058_i_513), + .Q(plm_v4f_mgt_for_v1_4_cal_inst1_drp_state_0__515), + .S(plm_v4f_mgt_for_v1_4_cal_inst0_reset_r[0]) + ); + FDR plm_v4f_mgt_for_v1_4_cal_inst1_drp_state_1_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(plm_v4f_mgt_for_v1_4_cal_inst1_N_282_i), + .Q(plm_v4f_mgt_for_v1_4_cal_inst1_drp_state_1__509), + .R(plm_v4f_mgt_for_v1_4_cal_inst0_reset_r[0]) + ); + FDR plm_v4f_mgt_for_v1_4_cal_inst1_drp_state_2_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(plm_v4f_mgt_for_v1_4_cal_inst1_drp_next_state_0_sqmuxa_1_i_i_a3_510), + .Q(plm_v4f_mgt_gt1_dwe), + .R(plm_v4f_mgt_for_v1_4_cal_inst0_reset_r[0]) + ); + FDR plm_v4f_mgt_for_v1_4_cal_inst1_drp_state_3_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(plm_v4f_mgt_for_v1_4_cal_inst1_N_1022_i_507), + .Q(plm_v4f_mgt_for_v1_4_cal_inst1_drp_state_3__508), + .R(plm_v4f_mgt_for_v1_4_cal_inst0_reset_r[0]) + ); + FDR plm_v4f_mgt_for_v1_4_cal_inst1_drp_state_4_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(plm_v4f_mgt_for_v1_4_cal_inst1_drp_next_state_0_sqmuxa), + .Q(plm_v4f_mgt_for_v1_4_cal_inst1_drp_state_4__514), + .R(plm_v4f_mgt_for_v1_4_cal_inst0_reset_r[0]) + ); + FDS plm_v4f_mgt_for_v1_4_cal_inst1_sd_state_0_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(plm_v4f_mgt_for_v1_4_cal_inst1_sd_next_state[0]), + .Q(plm_v4f_mgt_for_v1_4_cal_inst1_sd_state_0__504), + .S(plm_v4f_mgt_for_v1_4_cal_inst0_reset_r[0]) + ); + FDR plm_v4f_mgt_for_v1_4_cal_inst1_sd_state_1_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(plm_v4f_mgt_for_v1_4_cal_inst1_N_1057_i_502), + .Q(plm_v4f_mgt_for_v1_4_cal_inst1_sd_state_1__503), + .R(plm_v4f_mgt_for_v1_4_cal_inst0_reset_r[0]) + ); + FDR plm_v4f_mgt_for_v1_4_cal_inst1_sd_state_2_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(plm_v4f_mgt_for_v1_4_cal_inst1_sd_next_state_0_sqmuxa), + .Q(plm_v4f_mgt_for_v1_4_cal_inst1_sd_state_2__501), + .R(plm_v4f_mgt_for_v1_4_cal_inst0_reset_r[0]) + ); + FDR plm_v4f_mgt_for_v1_4_cal_inst1_sd_state_3_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(plm_v4f_mgt_for_v1_4_cal_inst1_N_674_i_499), + .Q(plm_v4f_mgt_for_v1_4_cal_inst1_sd_state_3__500), + .R(plm_v4f_mgt_for_v1_4_cal_inst0_reset_r[0]) + ); + FDR plm_v4f_mgt_for_v1_4_cal_inst1_sd_state_5_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(plm_v4f_mgt_for_v1_4_cal_inst1_sd_next_state_0_sqmuxa_1), + .Q(plm_v4f_mgt_for_v1_4_cal_inst1_sd_state_5__497), + .R(plm_v4f_mgt_for_v1_4_cal_inst0_reset_r[0]) + ); + FDR plm_v4f_mgt_for_v1_4_cal_inst1_sd_state_6_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(plm_v4f_mgt_for_v1_4_cal_inst1_N_676_i_495), + .Q(plm_v4f_mgt_for_v1_4_cal_inst1_sd_state_6__496), + .R(plm_v4f_mgt_for_v1_4_cal_inst0_reset_r[0]) + ); + FDR plm_v4f_mgt_for_v1_4_cal_inst1_sd_state_10_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(plm_v4f_mgt_for_v1_4_cal_inst1_N_677_i), + .Q(plm_v4f_mgt_for_v1_4_cal_inst1_sd_state_10__494), + .R(plm_v4f_mgt_for_v1_4_cal_inst0_reset_r[0]) + ); + FDR plm_v4f_mgt_for_v1_4_cal_inst1_sd_state_12_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(plm_v4f_mgt_for_v1_4_cal_inst1_sd_next_state_0_sqmuxa_3), + .Q(plm_v4f_mgt_for_v1_4_cal_inst1_sd_state_12__492), + .R(plm_v4f_mgt_for_v1_4_cal_inst0_reset_r[0]) + ); + FDR plm_v4f_mgt_for_v1_4_cal_inst1_sd_state_13_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(plm_v4f_mgt_for_v1_4_cal_inst1_N_1056_i_491), + .Q(plm_v4f_mgt_for_v1_4_cal_inst1_sd_state_13__505), + .R(plm_v4f_mgt_for_v1_4_cal_inst0_reset_r[0]) + ); + FDR plm_v4f_mgt_for_v1_4_cal_inst1_GT_DEN ( + .C(NlwRenamedSig_OI_trn_clk), + .D(plm_v4f_mgt_for_v1_4_cal_inst1_N_284_i), + .Q(plm_v4f_mgt_gt1_den), + .R(plm_v4f_mgt_for_v1_4_cal_inst0_reset_r[0]) + ); + FDR plm_v4f_mgt_for_v1_4_cal_inst1_sd_write ( + .C(NlwRenamedSig_OI_trn_clk), + .D(plm_v4f_mgt_for_v1_4_cal_inst1_N_715_i_490), + .Q(plm_v4f_mgt_for_v1_4_cal_inst1_sd_write_511), + .R(plm_v4f_mgt_for_v1_4_cal_inst1_N_718_i_487) + ); + FDR plm_v4f_mgt_for_v1_4_cal_inst1_sd_read ( + .C(NlwRenamedSig_OI_trn_clk), + .D(plm_v4f_mgt_for_v1_4_cal_inst1_N_716_i_489), + .Q(plm_v4f_mgt_for_v1_4_cal_inst1_sd_read_512), + .R(plm_v4f_mgt_for_v1_4_cal_inst1_N_718_i_487) + ); + FDR plm_v4f_mgt_for_v1_4_cal_inst1_sd_req ( + .C(NlwRenamedSig_OI_trn_clk), + .D(plm_v4f_mgt_for_v1_4_cal_inst1_N_717_i_488), + .Q(plm_v4f_mgt_for_v1_4_cal_inst1_sd_req_486), + .R(plm_v4f_mgt_for_v1_4_cal_inst1_N_718_i_487) + ); + FDRS plm_v4f_mgt_for_v1_4_cal_inst1_GT_LOOPBACK_1_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(plm_v4f_mgt_for_v1_4_cal_inst1_GND_485), + .Q(plm_v4f_mgt_loopback1[1]), + .R(plm_v4f_mgt_for_v1_4_cal_inst0_reset_r[0]), + .S(plm_v4f_mgt_for_v1_4_cal_inst1_VCC_484) + ); + FDRE plm_v4f_mgt_for_v1_4_cal_inst1_sd_state_11_ ( + .CE(plm_v4f_mgt_for_v1_4_cal_inst1_sd_drp_done_506), + .C(NlwRenamedSig_OI_trn_clk), + .D(plm_v4f_mgt_for_v1_4_cal_inst1_sd_state_10__494), + .Q(plm_v4f_mgt_for_v1_4_cal_inst1_sd_state_11__493), + .R(plm_v4f_mgt_for_v1_4_cal_inst0_reset_r[0]) + ); + FDRE plm_v4f_mgt_for_v1_4_cal_inst1_sd_state_4_ ( + .CE(plm_v4f_mgt_for_v1_4_cal_inst1_sd_drp_done_506), + .C(NlwRenamedSig_OI_trn_clk), + .D(plm_v4f_mgt_for_v1_4_cal_inst1_sd_state_3__500), + .Q(plm_v4f_mgt_for_v1_4_cal_inst1_sd_state_4__498), + .R(plm_v4f_mgt_for_v1_4_cal_inst0_reset_r[0]) + ); + FDR plm_v4f_mgt_for_v1_4_cal_inst1_sd_drp_done ( + .C(NlwRenamedSig_OI_trn_clk), + .D(plm_v4f_mgt_gt1_drdy), + .Q(plm_v4f_mgt_for_v1_4_cal_inst1_sd_drp_done_506), + .R(plm_v4f_mgt_for_v1_4_cal_inst1_cb_state_i[2]) + ); + defparam plm_v4f_mgt_for_v1_4_cal_inst1_cb_state_4_i_0_o2_1_.INIT = 4'h8; + LUT2 plm_v4f_mgt_for_v1_4_cal_inst1_cb_state_4_i_0_o2_1_ ( + .I0(plm_v4f_mgt_for_v1_4_cal_inst1_cb_state[1]), + .I1(plm_v4f_mgt_for_v1_4_cal_inst1_sd_req_486), + .O(plm_v4f_mgt_for_v1_4_cal_inst1_N_799_i) + ); + defparam plm_v4f_mgt_for_v1_4_cal_inst1_cb_state_4_i_0_o2_0_1_.INIT = 4'h1; + LUT2 plm_v4f_mgt_for_v1_4_cal_inst1_cb_state_4_i_0_o2_0_1_ ( + .I0(plm_v4f_mgt_for_v1_4_cal_inst1_cb_state[2]), + .I1(plm_v4f_mgt_for_v1_4_cal_inst1_cb_state[3]), + .O(plm_v4f_mgt_for_v1_4_cal_inst1_cb_state_4_i_0_o2_0[1]) + ); + defparam plm_v4f_mgt_for_v1_4_cal_inst1_sd_wr_wreg_9_0_0_a3_0_0_12_.INIT = 4'h4; + LUT2 plm_v4f_mgt_for_v1_4_cal_inst1_sd_wr_wreg_9_0_0_a3_0_0_12_ ( + .I0(plm_v4f_mgt_for_v1_4_cal_inst1_sd_state_12__492), + .I1(plm_v4f_mgt_for_v1_4_cal_inst1_sd_wr_wreg[12]), + .O(plm_v4f_mgt_for_v1_4_cal_inst1_sd_wr_wreg_9_0_0_a3_0[12]) + ); + defparam plm_v4f_mgt_for_v1_4_cal_inst1_N_718_i.INIT = 4'hE; + LUT2 plm_v4f_mgt_for_v1_4_cal_inst1_N_718_i ( + .I0(plm_v4f_mgt_for_v1_4_cal_inst1_sd_drp_done_506), + .I1(plm_v4f_mgt_for_v1_4_cal_inst1_sd_state_0__504), + .O(plm_v4f_mgt_for_v1_4_cal_inst1_N_718_i_487) + ); + defparam plm_v4f_mgt_for_v1_4_cal_inst1_sd_wr_wreg_9_0_0_o2_12_.INIT = 8'h80; + LUT3 plm_v4f_mgt_for_v1_4_cal_inst1_sd_wr_wreg_9_0_0_o2_12_ ( + .I0(plm_v4f_mgt_for_v1_4_cal_inst1_cb_state[2]), + .I1(plm_v4f_mgt_for_v1_4_cal_inst1_sd_read_512), + .I2(plm_v4f_mgt_gt1_drdy), + .O(plm_v4f_mgt_for_v1_4_cal_inst1_N_661_i) + ); + defparam plm_v4f_mgt_for_v1_4_cal_inst1_GT_DADDR_5_i_0_o2_5_.INIT = 8'h01; + LUT3 plm_v4f_mgt_for_v1_4_cal_inst1_GT_DADDR_5_i_0_o2_5_ ( + .I0(plm_v4f_mgt_for_v1_4_cal_inst1_sd_state_4__498), + .I1(plm_v4f_mgt_for_v1_4_cal_inst1_sd_state_6__496), + .I2(plm_v4f_mgt_for_v1_4_cal_inst1_sd_state_10__494), + .O(plm_v4f_mgt_for_v1_4_cal_inst1_N_671_i) + ); + defparam plm_v4f_mgt_for_v1_4_cal_inst1_GT_DEN_3_i_0_a2.INIT = 16'h1113; + LUT4 plm_v4f_mgt_for_v1_4_cal_inst1_GT_DEN_3_i_0_a2 ( + .I0(plm_v4f_mgt_for_v1_4_cal_inst1_cb_state[2]), + .I1(plm_v4f_mgt_for_v1_4_cal_inst1_cb_state[3]), + .I2(plm_v4f_mgt_for_v1_4_cal_inst1_sd_read_512), + .I3(plm_v4f_mgt_for_v1_4_cal_inst1_sd_write_511), + .O(plm_v4f_mgt_for_v1_4_cal_inst1_GT_DEN_3_i_0_a2_516) + ); + defparam plm_v4f_mgt_for_v1_4_cal_inst1_N_391_i_0.INIT = 4'h1; + LUT2 plm_v4f_mgt_for_v1_4_cal_inst1_N_391_i_0 ( + .I0(plm_v4f_mgt_for_v1_4_cal_inst1_N_671_i), + .I1(plm_v4f_mgt_for_v1_4_cal_inst1_cb_state[3]), + .O(plm_v4f_mgt_for_v1_4_cal_inst1_N_391_i_i) + ); + defparam plm_v4f_mgt_for_v1_4_cal_inst1_N_1061_i.INIT = 16'hFE54; + LUT4_L plm_v4f_mgt_for_v1_4_cal_inst1_N_1061_i ( + .I0(plm_v4f_mgt_for_v1_4_cal_inst1_N_661_i), + .I1(plm_v4f_mgt_for_v1_4_cal_inst1_sd_state_5__497), + .I2(plm_v4f_mgt_for_v1_4_cal_inst1_sd_wr_wreg[1]), + .I3(plm_v4f_mgt_gt1_di[1]), + .LO(plm_v4f_mgt_for_v1_4_cal_inst1_N_1061_i_518) + ); + defparam plm_v4f_mgt_for_v1_4_cal_inst1_cb_state_4_i_i_a3_3_.INIT = 8'h04; + LUT3_L plm_v4f_mgt_for_v1_4_cal_inst1_cb_state_4_i_i_a3_3_ ( + .I0(plm_v4f_mgt_for_v1_4_cal_inst0_reset_r[0]), + .I1(plm_v4f_mgt_for_v1_4_cal_inst1_cb_state[3]), + .I2(plm_v4f_mgt_for_v1_4_cal_inst1_gt_drdy_r_517), + .LO(plm_v4f_mgt_for_v1_4_cal_inst1_cb_state_4_i_i_a3[3]) + ); + defparam plm_v4f_mgt_for_v1_4_cal_inst1_cb_state_4_i_0_2_.INIT = 16'h2232; + LUT4_L plm_v4f_mgt_for_v1_4_cal_inst1_cb_state_4_i_0_2_ ( + .I0(plm_v4f_mgt_for_v1_4_cal_inst1_N_799_i), + .I1(plm_v4f_mgt_for_v1_4_cal_inst0_reset_r[0]), + .I2(plm_v4f_mgt_for_v1_4_cal_inst1_cb_state[2]), + .I3(plm_v4f_mgt_for_v1_4_cal_inst1_gt_drdy_r_517), + .LO(plm_v4f_mgt_for_v1_4_cal_inst1_N_291_i) + ); + defparam plm_v4f_mgt_for_v1_4_cal_inst1_cb_state_4_i_0_1_.INIT = 16'h0504; + LUT4_L plm_v4f_mgt_for_v1_4_cal_inst1_cb_state_4_i_0_1_ ( + .I0(plm_v4f_mgt_for_v1_4_cal_inst1_N_799_i), + .I1(plm_v4f_mgt_for_v1_4_cal_inst1_cb_state_4_i_0_o2_0[1]), + .I2(plm_v4f_mgt_for_v1_4_cal_inst0_reset_r[0]), + .I3(plm_v4f_mgt_for_v1_4_cal_inst1_gt_drdy_r_517), + .LO(plm_v4f_mgt_for_v1_4_cal_inst1_N_289_i) + ); + defparam plm_v4f_mgt_for_v1_4_cal_inst1_N_1064_i.INIT = 16'hBA10; + LUT4_L plm_v4f_mgt_for_v1_4_cal_inst1_N_1064_i ( + .I0(plm_v4f_mgt_for_v1_4_cal_inst1_N_661_i), + .I1(plm_v4f_mgt_for_v1_4_cal_inst1_sd_state_2__501), + .I2(plm_v4f_mgt_for_v1_4_cal_inst1_sd_wr_wreg_9_0_0_a3_0[12]), + .I3(plm_v4f_mgt_gt1_di[12]), + .LO(plm_v4f_mgt_for_v1_4_cal_inst1_N_1064_i_519) + ); + defparam plm_v4f_mgt_for_v1_4_cal_inst1_gt_do_r_4_i_m2_0_a3_15_.INIT = 4'h8; + LUT2_L plm_v4f_mgt_for_v1_4_cal_inst1_gt_do_r_4_i_m2_0_a3_15_ ( + .I0(plm_v4f_mgt_for_v1_4_cal_inst1_cb_state[2]), + .I1(plm_v4f_mgt_for_v1_4_cal_inst1_sd_wr_wreg[15]), + .LO(plm_v4f_mgt_for_v1_4_cal_inst1_gt_do_r_4[15]) + ); + defparam plm_v4f_mgt_for_v1_4_cal_inst1_gt_do_r_4_i_m2_0_a3_14_.INIT = 4'h8; + LUT2_L plm_v4f_mgt_for_v1_4_cal_inst1_gt_do_r_4_i_m2_0_a3_14_ ( + .I0(plm_v4f_mgt_for_v1_4_cal_inst1_cb_state[2]), + .I1(plm_v4f_mgt_for_v1_4_cal_inst1_sd_wr_wreg[14]), + .LO(plm_v4f_mgt_for_v1_4_cal_inst1_gt_do_r_4[14]) + ); + defparam plm_v4f_mgt_for_v1_4_cal_inst1_gt_do_r_4_i_m2_0_a3_13_.INIT = 4'h8; + LUT2_L plm_v4f_mgt_for_v1_4_cal_inst1_gt_do_r_4_i_m2_0_a3_13_ ( + .I0(plm_v4f_mgt_for_v1_4_cal_inst1_cb_state[2]), + .I1(plm_v4f_mgt_for_v1_4_cal_inst1_sd_wr_wreg[13]), + .LO(plm_v4f_mgt_for_v1_4_cal_inst1_gt_do_r_4[13]) + ); + defparam plm_v4f_mgt_for_v1_4_cal_inst1_gt_do_r_4_i_m2_0_a3_12_.INIT = 4'h8; + LUT2_L plm_v4f_mgt_for_v1_4_cal_inst1_gt_do_r_4_i_m2_0_a3_12_ ( + .I0(plm_v4f_mgt_for_v1_4_cal_inst1_cb_state[2]), + .I1(plm_v4f_mgt_for_v1_4_cal_inst1_sd_wr_wreg[12]), + .LO(plm_v4f_mgt_for_v1_4_cal_inst1_gt_do_r_4[12]) + ); + defparam plm_v4f_mgt_for_v1_4_cal_inst1_gt_do_r_4_i_m2_0_a3_11_.INIT = 4'h8; + LUT2_L plm_v4f_mgt_for_v1_4_cal_inst1_gt_do_r_4_i_m2_0_a3_11_ ( + .I0(plm_v4f_mgt_for_v1_4_cal_inst1_cb_state[2]), + .I1(plm_v4f_mgt_for_v1_4_cal_inst1_sd_wr_wreg[11]), + .LO(plm_v4f_mgt_for_v1_4_cal_inst1_gt_do_r_4[11]) + ); + defparam plm_v4f_mgt_for_v1_4_cal_inst1_gt_do_r_4_i_m2_0_a3_10_.INIT = 4'h8; + LUT2_L plm_v4f_mgt_for_v1_4_cal_inst1_gt_do_r_4_i_m2_0_a3_10_ ( + .I0(plm_v4f_mgt_for_v1_4_cal_inst1_cb_state[2]), + .I1(plm_v4f_mgt_for_v1_4_cal_inst1_sd_wr_wreg[10]), + .LO(plm_v4f_mgt_for_v1_4_cal_inst1_gt_do_r_4[10]) + ); + defparam plm_v4f_mgt_for_v1_4_cal_inst1_gt_do_r_4_i_m2_0_a3_9_.INIT = 4'h8; + LUT2_L plm_v4f_mgt_for_v1_4_cal_inst1_gt_do_r_4_i_m2_0_a3_9_ ( + .I0(plm_v4f_mgt_for_v1_4_cal_inst1_cb_state[2]), + .I1(plm_v4f_mgt_for_v1_4_cal_inst1_sd_wr_wreg[9]), + .LO(plm_v4f_mgt_for_v1_4_cal_inst1_gt_do_r_4[9]) + ); + defparam plm_v4f_mgt_for_v1_4_cal_inst1_gt_do_r_4_i_m2_0_a3_8_.INIT = 4'h8; + LUT2_L plm_v4f_mgt_for_v1_4_cal_inst1_gt_do_r_4_i_m2_0_a3_8_ ( + .I0(plm_v4f_mgt_for_v1_4_cal_inst1_cb_state[2]), + .I1(plm_v4f_mgt_for_v1_4_cal_inst1_sd_wr_wreg[8]), + .LO(plm_v4f_mgt_for_v1_4_cal_inst1_gt_do_r_4[8]) + ); + defparam plm_v4f_mgt_for_v1_4_cal_inst1_gt_do_r_4_i_m2_0_a3_7_.INIT = 4'h8; + LUT2_L plm_v4f_mgt_for_v1_4_cal_inst1_gt_do_r_4_i_m2_0_a3_7_ ( + .I0(plm_v4f_mgt_for_v1_4_cal_inst1_cb_state[2]), + .I1(plm_v4f_mgt_for_v1_4_cal_inst1_sd_wr_wreg[7]), + .LO(plm_v4f_mgt_for_v1_4_cal_inst1_gt_do_r_4[7]) + ); + defparam plm_v4f_mgt_for_v1_4_cal_inst1_gt_do_r_4_i_m2_0_a3_6_.INIT = 4'h8; + LUT2_L plm_v4f_mgt_for_v1_4_cal_inst1_gt_do_r_4_i_m2_0_a3_6_ ( + .I0(plm_v4f_mgt_for_v1_4_cal_inst1_cb_state[2]), + .I1(plm_v4f_mgt_for_v1_4_cal_inst1_sd_wr_wreg[6]), + .LO(plm_v4f_mgt_for_v1_4_cal_inst1_gt_do_r_4[6]) + ); + defparam plm_v4f_mgt_for_v1_4_cal_inst1_gt_do_r_4_i_m2_0_a3_5_.INIT = 4'h8; + LUT2_L plm_v4f_mgt_for_v1_4_cal_inst1_gt_do_r_4_i_m2_0_a3_5_ ( + .I0(plm_v4f_mgt_for_v1_4_cal_inst1_cb_state[2]), + .I1(plm_v4f_mgt_for_v1_4_cal_inst1_sd_wr_wreg[5]), + .LO(plm_v4f_mgt_for_v1_4_cal_inst1_gt_do_r_4[5]) + ); + defparam plm_v4f_mgt_for_v1_4_cal_inst1_gt_do_r_4_i_m2_0_a3_4_.INIT = 4'h8; + LUT2_L plm_v4f_mgt_for_v1_4_cal_inst1_gt_do_r_4_i_m2_0_a3_4_ ( + .I0(plm_v4f_mgt_for_v1_4_cal_inst1_cb_state[2]), + .I1(plm_v4f_mgt_for_v1_4_cal_inst1_sd_wr_wreg[4]), + .LO(plm_v4f_mgt_for_v1_4_cal_inst1_gt_do_r_4[4]) + ); + defparam plm_v4f_mgt_for_v1_4_cal_inst1_gt_do_r_4_i_m2_0_a3_3_.INIT = 4'h8; + LUT2_L plm_v4f_mgt_for_v1_4_cal_inst1_gt_do_r_4_i_m2_0_a3_3_ ( + .I0(plm_v4f_mgt_for_v1_4_cal_inst1_cb_state[2]), + .I1(plm_v4f_mgt_for_v1_4_cal_inst1_sd_wr_wreg[3]), + .LO(plm_v4f_mgt_for_v1_4_cal_inst1_gt_do_r_4[3]) + ); + defparam plm_v4f_mgt_for_v1_4_cal_inst1_gt_do_r_4_i_m2_0_a3_2_.INIT = 4'h8; + LUT2_L plm_v4f_mgt_for_v1_4_cal_inst1_gt_do_r_4_i_m2_0_a3_2_ ( + .I0(plm_v4f_mgt_for_v1_4_cal_inst1_cb_state[2]), + .I1(plm_v4f_mgt_for_v1_4_cal_inst1_sd_wr_wreg[2]), + .LO(plm_v4f_mgt_for_v1_4_cal_inst1_gt_do_r_4[2]) + ); + defparam plm_v4f_mgt_for_v1_4_cal_inst1_gt_do_r_4_i_m2_0_a3_1_.INIT = 4'h8; + LUT2_L plm_v4f_mgt_for_v1_4_cal_inst1_gt_do_r_4_i_m2_0_a3_1_ ( + .I0(plm_v4f_mgt_for_v1_4_cal_inst1_cb_state[2]), + .I1(plm_v4f_mgt_for_v1_4_cal_inst1_sd_wr_wreg[1]), + .LO(plm_v4f_mgt_for_v1_4_cal_inst1_gt_do_r_4[1]) + ); + defparam plm_v4f_mgt_for_v1_4_cal_inst1_gt_do_r_4_i_m2_0_a3_0_.INIT = 4'h8; + LUT2_L plm_v4f_mgt_for_v1_4_cal_inst1_gt_do_r_4_i_m2_0_a3_0_ ( + .I0(plm_v4f_mgt_for_v1_4_cal_inst1_cb_state[2]), + .I1(plm_v4f_mgt_for_v1_4_cal_inst1_sd_wr_wreg[0]), + .LO(plm_v4f_mgt_for_v1_4_cal_inst1_gt_do_r_4[0]) + ); + defparam plm_v4f_mgt_for_v1_4_cal_inst1_N_717_i.INIT = 4'hE; + LUT2_L plm_v4f_mgt_for_v1_4_cal_inst1_N_717_i ( + .I0(plm_v4f_mgt_for_v1_4_cal_inst1_sd_read_512), + .I1(plm_v4f_mgt_for_v1_4_cal_inst1_sd_write_511), + .LO(plm_v4f_mgt_for_v1_4_cal_inst1_N_717_i_488) + ); + defparam plm_v4f_mgt_for_v1_4_cal_inst1_N_716_i.INIT = 8'hFE; + LUT3_L plm_v4f_mgt_for_v1_4_cal_inst1_N_716_i ( + .I0(plm_v4f_mgt_for_v1_4_cal_inst1_sd_state_1__503), + .I1(plm_v4f_mgt_for_v1_4_cal_inst1_sd_state_4__498), + .I2(plm_v4f_mgt_for_v1_4_cal_inst1_sd_state_11__493), + .LO(plm_v4f_mgt_for_v1_4_cal_inst1_N_716_i_489) + ); + defparam plm_v4f_mgt_for_v1_4_cal_inst1_N_715_i.INIT = 16'hFFFE; + LUT4_L plm_v4f_mgt_for_v1_4_cal_inst1_N_715_i ( + .I0(plm_v4f_mgt_for_v1_4_cal_inst1_sd_state_3__500), + .I1(plm_v4f_mgt_for_v1_4_cal_inst1_sd_state_6__496), + .I2(plm_v4f_mgt_for_v1_4_cal_inst1_sd_state_10__494), + .I3(plm_v4f_mgt_for_v1_4_cal_inst1_sd_state_13__505), + .LO(plm_v4f_mgt_for_v1_4_cal_inst1_N_715_i_490) + ); + defparam plm_v4f_mgt_for_v1_4_cal_inst1_GT_DEN_3_i_0.INIT = 4'h4; + LUT2_L plm_v4f_mgt_for_v1_4_cal_inst1_GT_DEN_3_i_0 ( + .I0(plm_v4f_mgt_for_v1_4_cal_inst1_GT_DEN_3_i_0_a2_516), + .I1(plm_v4f_mgt_for_v1_4_cal_inst1_drp_state_0__515), + .LO(plm_v4f_mgt_for_v1_4_cal_inst1_N_284_i) + ); + defparam plm_v4f_mgt_for_v1_4_cal_inst1_GT_DADDR_5_i_0_5_.INIT = 4'h8; + LUT2_L plm_v4f_mgt_for_v1_4_cal_inst1_GT_DADDR_5_i_0_5_ ( + .I0(plm_v4f_mgt_for_v1_4_cal_inst1_N_391_i_i), + .I1(cfg_cfg_5072[509]), + .LO(plm_v4f_mgt_for_v1_4_cal_inst1_N_313_i) + ); + defparam plm_v4f_mgt_for_v1_4_cal_inst1_cb_state_i_3_.INIT = 4'h1; + LUT1_L plm_v4f_mgt_for_v1_4_cal_inst1_cb_state_i_3_ ( + .I0(plm_v4f_mgt_for_v1_4_cal_inst1_cb_state[3]), + .LO(plm_v4f_mgt_for_v1_4_cal_inst1_cb_state_i[3]) + ); + defparam plm_v4f_mgt_for_v1_4_cal_inst1_GT_DADDR_5_i_0_2_.INIT = 8'h32; + LUT3_L plm_v4f_mgt_for_v1_4_cal_inst1_GT_DADDR_5_i_0_2_ ( + .I0(plm_v4f_mgt_for_v1_4_cal_inst1_N_671_i), + .I1(plm_v4f_mgt_for_v1_4_cal_inst1_cb_state[3]), + .I2(cfg_cfg_5072[509]), + .LO(plm_v4f_mgt_for_v1_4_cal_inst1_N_309_i) + ); + defparam plm_v4f_mgt_for_v1_4_cal_inst1_GT_DADDR_5_i_i_a3_1_.INIT = 8'h02; + LUT3_L plm_v4f_mgt_for_v1_4_cal_inst1_GT_DADDR_5_i_i_a3_1_ ( + .I0(plm_v4f_mgt_for_v1_4_cal_inst1_N_671_i), + .I1(plm_v4f_mgt_for_v1_4_cal_inst1_cb_state[3]), + .I2(cfg_cfg_5072[509]), + .LO(plm_v4f_mgt_for_v1_4_cal_inst1_GT_DADDR_5_i_i_a3_0[1]) + ); + defparam plm_v4f_mgt_for_v1_4_cal_inst1_N_1056_i.INIT = 8'hDC; + LUT3_L plm_v4f_mgt_for_v1_4_cal_inst1_N_1056_i ( + .I0(plm_v4f_mgt_for_v1_4_cal_inst1_sd_drp_done_506), + .I1(plm_v4f_mgt_for_v1_4_cal_inst1_sd_state_12__492), + .I2(plm_v4f_mgt_for_v1_4_cal_inst1_sd_state_13__505), + .LO(plm_v4f_mgt_for_v1_4_cal_inst1_N_1056_i_491) + ); + defparam plm_v4f_mgt_for_v1_4_cal_inst1_sd_next_state_0_sqmuxa_3_0_a2_0_a3.INIT = 4'h8; + LUT2_L plm_v4f_mgt_for_v1_4_cal_inst1_sd_next_state_0_sqmuxa_3_0_a2_0_a3 ( + .I0(plm_v4f_mgt_for_v1_4_cal_inst1_sd_drp_done_506), + .I1(plm_v4f_mgt_for_v1_4_cal_inst1_sd_state_11__493), + .LO(plm_v4f_mgt_for_v1_4_cal_inst1_sd_next_state_0_sqmuxa_3) + ); + defparam plm_v4f_mgt_for_v1_4_cal_inst1_sd_next_state_0_0_m4_i_m2_i_m2_10_.INIT = 4'h4; + LUT2_L plm_v4f_mgt_for_v1_4_cal_inst1_sd_next_state_0_0_m4_i_m2_i_m2_10_ ( + .I0(plm_v4f_mgt_for_v1_4_cal_inst1_sd_drp_done_506), + .I1(plm_v4f_mgt_for_v1_4_cal_inst1_sd_state_10__494), + .LO(plm_v4f_mgt_for_v1_4_cal_inst1_N_677_i) + ); + defparam plm_v4f_mgt_for_v1_4_cal_inst1_N_676_i.INIT = 8'h5C; + LUT3_L plm_v4f_mgt_for_v1_4_cal_inst1_N_676_i ( + .I0(plm_v4f_mgt_for_v1_4_cal_inst1_sd_drp_done_506), + .I1(plm_v4f_mgt_for_v1_4_cal_inst1_sd_state_5__497), + .I2(plm_v4f_mgt_for_v1_4_cal_inst1_sd_state_6__496), + .LO(plm_v4f_mgt_for_v1_4_cal_inst1_N_676_i_495) + ); + defparam plm_v4f_mgt_for_v1_4_cal_inst1_sd_next_state_0_sqmuxa_1_0_a2_0_a3.INIT = 4'h8; + LUT2_L plm_v4f_mgt_for_v1_4_cal_inst1_sd_next_state_0_sqmuxa_1_0_a2_0_a3 ( + .I0(plm_v4f_mgt_for_v1_4_cal_inst1_sd_drp_done_506), + .I1(plm_v4f_mgt_for_v1_4_cal_inst1_sd_state_4__498), + .LO(plm_v4f_mgt_for_v1_4_cal_inst1_sd_next_state_0_sqmuxa_1) + ); + defparam plm_v4f_mgt_for_v1_4_cal_inst1_N_674_i.INIT = 8'h5C; + LUT3_L plm_v4f_mgt_for_v1_4_cal_inst1_N_674_i ( + .I0(plm_v4f_mgt_for_v1_4_cal_inst1_sd_drp_done_506), + .I1(plm_v4f_mgt_for_v1_4_cal_inst1_sd_state_2__501), + .I2(plm_v4f_mgt_for_v1_4_cal_inst1_sd_state_3__500), + .LO(plm_v4f_mgt_for_v1_4_cal_inst1_N_674_i_499) + ); + defparam plm_v4f_mgt_for_v1_4_cal_inst1_sd_next_state_0_sqmuxa_0_a2_0_a3.INIT = 4'h8; + LUT2_L plm_v4f_mgt_for_v1_4_cal_inst1_sd_next_state_0_sqmuxa_0_a2_0_a3 ( + .I0(plm_v4f_mgt_for_v1_4_cal_inst1_sd_drp_done_506), + .I1(plm_v4f_mgt_for_v1_4_cal_inst1_sd_state_1__503), + .LO(plm_v4f_mgt_for_v1_4_cal_inst1_sd_next_state_0_sqmuxa) + ); + defparam plm_v4f_mgt_for_v1_4_cal_inst1_N_1057_i.INIT = 8'hDC; + LUT3_L plm_v4f_mgt_for_v1_4_cal_inst1_N_1057_i ( + .I0(plm_v4f_mgt_for_v1_4_cal_inst1_sd_drp_done_506), + .I1(plm_v4f_mgt_for_v1_4_cal_inst1_sd_state_0__504), + .I2(plm_v4f_mgt_for_v1_4_cal_inst1_sd_state_1__503), + .LO(plm_v4f_mgt_for_v1_4_cal_inst1_N_1057_i_502) + ); + defparam plm_v4f_mgt_for_v1_4_cal_inst1_sd_next_state_0_0_a3_0_a2_0_a3_0_.INIT = 4'h8; + LUT2_L plm_v4f_mgt_for_v1_4_cal_inst1_sd_next_state_0_0_a3_0_a2_0_a3_0_ ( + .I0(plm_v4f_mgt_for_v1_4_cal_inst1_sd_drp_done_506), + .I1(plm_v4f_mgt_for_v1_4_cal_inst1_sd_state_13__505), + .LO(plm_v4f_mgt_for_v1_4_cal_inst1_sd_next_state[0]) + ); + defparam plm_v4f_mgt_for_v1_4_cal_inst1_drp_next_state_0_sqmuxa_0_a2_0_a3.INIT = 4'h8; + LUT2_L plm_v4f_mgt_for_v1_4_cal_inst1_drp_next_state_0_sqmuxa_0_a2_0_a3 ( + .I0(plm_v4f_mgt_for_v1_4_cal_inst1_drp_state_3__508), + .I1(plm_v4f_mgt_for_v1_4_cal_inst1_gt_drdy_r_517), + .LO(plm_v4f_mgt_for_v1_4_cal_inst1_drp_next_state_0_sqmuxa) + ); + defparam plm_v4f_mgt_for_v1_4_cal_inst1_N_1022_i.INIT = 16'hFFAE; + LUT4_L plm_v4f_mgt_for_v1_4_cal_inst1_N_1022_i ( + .I0(plm_v4f_mgt_for_v1_4_cal_inst1_drp_state_1__509), + .I1(plm_v4f_mgt_for_v1_4_cal_inst1_drp_state_3__508), + .I2(plm_v4f_mgt_for_v1_4_cal_inst1_gt_drdy_r_517), + .I3(plm_v4f_mgt_gt1_dwe), + .LO(plm_v4f_mgt_for_v1_4_cal_inst1_N_1022_i_507) + ); + defparam plm_v4f_mgt_for_v1_4_cal_inst1_drp_next_state_0_sqmuxa_1_i_i_a3.INIT = 8'h80; + LUT3_L plm_v4f_mgt_for_v1_4_cal_inst1_drp_next_state_0_sqmuxa_1_i_i_a3 ( + .I0(plm_v4f_mgt_for_v1_4_cal_inst1_cb_state[2]), + .I1(plm_v4f_mgt_for_v1_4_cal_inst1_drp_state_0__515), + .I2(plm_v4f_mgt_for_v1_4_cal_inst1_sd_write_511), + .LO(plm_v4f_mgt_for_v1_4_cal_inst1_drp_next_state_0_sqmuxa_1_i_i_a3_510) + ); + defparam plm_v4f_mgt_for_v1_4_cal_inst1_drp_next_state_1_sqmuxa_1_i_0.INIT = 16'hE0C0; + LUT4_L plm_v4f_mgt_for_v1_4_cal_inst1_drp_next_state_1_sqmuxa_1_i_0 ( + .I0(plm_v4f_mgt_for_v1_4_cal_inst1_cb_state[2]), + .I1(plm_v4f_mgt_for_v1_4_cal_inst1_cb_state[3]), + .I2(plm_v4f_mgt_for_v1_4_cal_inst1_drp_state_0__515), + .I3(plm_v4f_mgt_for_v1_4_cal_inst1_sd_read_512), + .LO(plm_v4f_mgt_for_v1_4_cal_inst1_N_282_i) + ); + defparam plm_v4f_mgt_for_v1_4_cal_inst1_N_1058_i.INIT = 8'hF8; + LUT3_L plm_v4f_mgt_for_v1_4_cal_inst1_N_1058_i ( + .I0(plm_v4f_mgt_for_v1_4_cal_inst1_GT_DEN_3_i_0_a2_516), + .I1(plm_v4f_mgt_for_v1_4_cal_inst1_drp_state_0__515), + .I2(plm_v4f_mgt_for_v1_4_cal_inst1_drp_state_4__514), + .LO(plm_v4f_mgt_for_v1_4_cal_inst1_N_1058_i_513) + ); + FD plm_v4f_mgt_for_v1_4_cal_inst1_gt_drdy_r ( + .C(NlwRenamedSig_OI_trn_clk), + .D(plm_v4f_mgt_gt1_drdy), + .Q(plm_v4f_mgt_for_v1_4_cal_inst1_gt_drdy_r_517) + ); + FDE plm_v4f_mgt_for_v1_4_cal_inst1_sd_wr_wreg_8_ ( + .CE(plm_v4f_mgt_for_v1_4_cal_inst1_N_661_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(plm_v4f_mgt_gt1_di[8]), + .Q(plm_v4f_mgt_for_v1_4_cal_inst1_sd_wr_wreg[8]) + ); + FDE plm_v4f_mgt_for_v1_4_cal_inst1_sd_wr_wreg_7_ ( + .CE(plm_v4f_mgt_for_v1_4_cal_inst1_N_661_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(plm_v4f_mgt_gt1_di[7]), + .Q(plm_v4f_mgt_for_v1_4_cal_inst1_sd_wr_wreg[7]) + ); + FDE plm_v4f_mgt_for_v1_4_cal_inst1_sd_wr_wreg_6_ ( + .CE(plm_v4f_mgt_for_v1_4_cal_inst1_N_661_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(plm_v4f_mgt_gt1_di[6]), + .Q(plm_v4f_mgt_for_v1_4_cal_inst1_sd_wr_wreg[6]) + ); + FDE plm_v4f_mgt_for_v1_4_cal_inst1_sd_wr_wreg_5_ ( + .CE(plm_v4f_mgt_for_v1_4_cal_inst1_N_661_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(plm_v4f_mgt_gt1_di[5]), + .Q(plm_v4f_mgt_for_v1_4_cal_inst1_sd_wr_wreg[5]) + ); + FDE plm_v4f_mgt_for_v1_4_cal_inst1_sd_wr_wreg_4_ ( + .CE(plm_v4f_mgt_for_v1_4_cal_inst1_N_661_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(plm_v4f_mgt_gt1_di[4]), + .Q(plm_v4f_mgt_for_v1_4_cal_inst1_sd_wr_wreg[4]) + ); + FDE plm_v4f_mgt_for_v1_4_cal_inst1_sd_wr_wreg_3_ ( + .CE(plm_v4f_mgt_for_v1_4_cal_inst1_N_661_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(plm_v4f_mgt_gt1_di[3]), + .Q(plm_v4f_mgt_for_v1_4_cal_inst1_sd_wr_wreg[3]) + ); + FDE plm_v4f_mgt_for_v1_4_cal_inst1_sd_wr_wreg_2_ ( + .CE(plm_v4f_mgt_for_v1_4_cal_inst1_N_661_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(plm_v4f_mgt_gt1_di[2]), + .Q(plm_v4f_mgt_for_v1_4_cal_inst1_sd_wr_wreg[2]) + ); + FD plm_v4f_mgt_for_v1_4_cal_inst1_sd_wr_wreg_1_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(plm_v4f_mgt_for_v1_4_cal_inst1_N_1061_i_518), + .Q(plm_v4f_mgt_for_v1_4_cal_inst1_sd_wr_wreg[1]) + ); + FDE plm_v4f_mgt_for_v1_4_cal_inst1_sd_wr_wreg_0_ ( + .CE(plm_v4f_mgt_for_v1_4_cal_inst1_N_661_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(plm_v4f_mgt_gt1_di[0]), + .Q(plm_v4f_mgt_for_v1_4_cal_inst1_sd_wr_wreg[0]) + ); + FDP plm_v4f_mgt_for_v1_4_cal_inst1_reset_r_0_ ( + .PRE(plm_v4f_mgt_N_435_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(plm_v4f_mgt_for_v1_4_cal_inst1_reset_r[1]), + .Q(plm_v4f_mgt_for_v1_4_cal_inst0_reset_r[0]) + ); + FD plm_v4f_mgt_for_v1_4_cal_inst1_cb_state_3_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(plm_v4f_mgt_for_v1_4_cal_inst1_cb_state_4_i_i_a3[3]), + .Q(plm_v4f_mgt_for_v1_4_cal_inst1_cb_state[3]) + ); + FD plm_v4f_mgt_for_v1_4_cal_inst1_cb_state_2_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(plm_v4f_mgt_for_v1_4_cal_inst1_N_291_i), + .Q(plm_v4f_mgt_for_v1_4_cal_inst1_cb_state[2]) + ); + FD plm_v4f_mgt_for_v1_4_cal_inst1_cb_state_1_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(plm_v4f_mgt_for_v1_4_cal_inst1_N_289_i), + .Q(plm_v4f_mgt_for_v1_4_cal_inst1_cb_state[1]) + ); + FDE plm_v4f_mgt_for_v1_4_cal_inst1_sd_wr_wreg_15_ ( + .CE(plm_v4f_mgt_for_v1_4_cal_inst1_N_661_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(plm_v4f_mgt_gt1_di[15]), + .Q(plm_v4f_mgt_for_v1_4_cal_inst1_sd_wr_wreg[15]) + ); + FDE plm_v4f_mgt_for_v1_4_cal_inst1_sd_wr_wreg_14_ ( + .CE(plm_v4f_mgt_for_v1_4_cal_inst1_N_661_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(plm_v4f_mgt_gt1_di[14]), + .Q(plm_v4f_mgt_for_v1_4_cal_inst1_sd_wr_wreg[14]) + ); + FDE plm_v4f_mgt_for_v1_4_cal_inst1_sd_wr_wreg_13_ ( + .CE(plm_v4f_mgt_for_v1_4_cal_inst1_N_661_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(plm_v4f_mgt_gt1_di[13]), + .Q(plm_v4f_mgt_for_v1_4_cal_inst1_sd_wr_wreg[13]) + ); + FD plm_v4f_mgt_for_v1_4_cal_inst1_sd_wr_wreg_12_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(plm_v4f_mgt_for_v1_4_cal_inst1_N_1064_i_519), + .Q(plm_v4f_mgt_for_v1_4_cal_inst1_sd_wr_wreg[12]) + ); + FDE plm_v4f_mgt_for_v1_4_cal_inst1_sd_wr_wreg_11_ ( + .CE(plm_v4f_mgt_for_v1_4_cal_inst1_N_661_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(plm_v4f_mgt_gt1_di[11]), + .Q(plm_v4f_mgt_for_v1_4_cal_inst1_sd_wr_wreg[11]) + ); + FDE plm_v4f_mgt_for_v1_4_cal_inst1_sd_wr_wreg_10_ ( + .CE(plm_v4f_mgt_for_v1_4_cal_inst1_N_661_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(plm_v4f_mgt_gt1_di[10]), + .Q(plm_v4f_mgt_for_v1_4_cal_inst1_sd_wr_wreg[10]) + ); + FDE plm_v4f_mgt_for_v1_4_cal_inst1_sd_wr_wreg_9_ ( + .CE(plm_v4f_mgt_for_v1_4_cal_inst1_N_661_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(plm_v4f_mgt_gt1_di[9]), + .Q(plm_v4f_mgt_for_v1_4_cal_inst1_sd_wr_wreg[9]) + ); + FDE plm_v4f_mgt_for_v1_4_cal_inst1_gt_do_r_15_ ( + .CE(plm_v4f_mgt_for_v1_4_cal_inst1_N_1030_i_520), + .C(NlwRenamedSig_OI_trn_clk), + .D(plm_v4f_mgt_for_v1_4_cal_inst1_gt_do_r_4[15]), + .Q(plm_v4f_mgt_gt1_do[15]) + ); + FDE plm_v4f_mgt_for_v1_4_cal_inst1_gt_do_r_14_ ( + .CE(plm_v4f_mgt_for_v1_4_cal_inst1_N_1030_i_520), + .C(NlwRenamedSig_OI_trn_clk), + .D(plm_v4f_mgt_for_v1_4_cal_inst1_gt_do_r_4[14]), + .Q(plm_v4f_mgt_gt1_do[14]) + ); + FDE plm_v4f_mgt_for_v1_4_cal_inst1_gt_do_r_13_ ( + .CE(plm_v4f_mgt_for_v1_4_cal_inst1_N_1030_i_520), + .C(NlwRenamedSig_OI_trn_clk), + .D(plm_v4f_mgt_for_v1_4_cal_inst1_gt_do_r_4[13]), + .Q(plm_v4f_mgt_gt1_do[13]) + ); + FDE plm_v4f_mgt_for_v1_4_cal_inst1_gt_do_r_12_ ( + .CE(plm_v4f_mgt_for_v1_4_cal_inst1_N_1030_i_520), + .C(NlwRenamedSig_OI_trn_clk), + .D(plm_v4f_mgt_for_v1_4_cal_inst1_gt_do_r_4[12]), + .Q(plm_v4f_mgt_gt1_do[12]) + ); + FDE plm_v4f_mgt_for_v1_4_cal_inst1_gt_do_r_11_ ( + .CE(plm_v4f_mgt_for_v1_4_cal_inst1_N_1030_i_520), + .C(NlwRenamedSig_OI_trn_clk), + .D(plm_v4f_mgt_for_v1_4_cal_inst1_gt_do_r_4[11]), + .Q(plm_v4f_mgt_gt1_do[11]) + ); + FDE plm_v4f_mgt_for_v1_4_cal_inst1_gt_do_r_10_ ( + .CE(plm_v4f_mgt_for_v1_4_cal_inst1_N_1030_i_520), + .C(NlwRenamedSig_OI_trn_clk), + .D(plm_v4f_mgt_for_v1_4_cal_inst1_gt_do_r_4[10]), + .Q(plm_v4f_mgt_gt1_do[10]) + ); + FDE plm_v4f_mgt_for_v1_4_cal_inst1_gt_do_r_9_ ( + .CE(plm_v4f_mgt_for_v1_4_cal_inst1_N_1030_i_520), + .C(NlwRenamedSig_OI_trn_clk), + .D(plm_v4f_mgt_for_v1_4_cal_inst1_gt_do_r_4[9]), + .Q(plm_v4f_mgt_gt1_do[9]) + ); + FDE plm_v4f_mgt_for_v1_4_cal_inst1_gt_do_r_8_ ( + .CE(plm_v4f_mgt_for_v1_4_cal_inst1_N_1030_i_520), + .C(NlwRenamedSig_OI_trn_clk), + .D(plm_v4f_mgt_for_v1_4_cal_inst1_gt_do_r_4[8]), + .Q(plm_v4f_mgt_gt1_do[8]) + ); + FDE plm_v4f_mgt_for_v1_4_cal_inst1_gt_do_r_7_ ( + .CE(plm_v4f_mgt_for_v1_4_cal_inst1_N_1030_i_520), + .C(NlwRenamedSig_OI_trn_clk), + .D(plm_v4f_mgt_for_v1_4_cal_inst1_gt_do_r_4[7]), + .Q(plm_v4f_mgt_gt1_do[7]) + ); + FDE plm_v4f_mgt_for_v1_4_cal_inst1_gt_do_r_6_ ( + .CE(plm_v4f_mgt_for_v1_4_cal_inst1_N_1030_i_520), + .C(NlwRenamedSig_OI_trn_clk), + .D(plm_v4f_mgt_for_v1_4_cal_inst1_gt_do_r_4[6]), + .Q(plm_v4f_mgt_gt1_do[6]) + ); + FDE plm_v4f_mgt_for_v1_4_cal_inst1_gt_do_r_5_ ( + .CE(plm_v4f_mgt_for_v1_4_cal_inst1_N_1030_i_520), + .C(NlwRenamedSig_OI_trn_clk), + .D(plm_v4f_mgt_for_v1_4_cal_inst1_gt_do_r_4[5]), + .Q(plm_v4f_mgt_gt1_do[5]) + ); + FDE plm_v4f_mgt_for_v1_4_cal_inst1_gt_do_r_4_ ( + .CE(plm_v4f_mgt_for_v1_4_cal_inst1_N_1030_i_520), + .C(NlwRenamedSig_OI_trn_clk), + .D(plm_v4f_mgt_for_v1_4_cal_inst1_gt_do_r_4[4]), + .Q(plm_v4f_mgt_gt1_do[4]) + ); + FDE plm_v4f_mgt_for_v1_4_cal_inst1_gt_do_r_3_ ( + .CE(plm_v4f_mgt_for_v1_4_cal_inst1_N_1030_i_520), + .C(NlwRenamedSig_OI_trn_clk), + .D(plm_v4f_mgt_for_v1_4_cal_inst1_gt_do_r_4[3]), + .Q(plm_v4f_mgt_gt1_do[3]) + ); + FDE plm_v4f_mgt_for_v1_4_cal_inst1_gt_do_r_2_ ( + .CE(plm_v4f_mgt_for_v1_4_cal_inst1_N_1030_i_520), + .C(NlwRenamedSig_OI_trn_clk), + .D(plm_v4f_mgt_for_v1_4_cal_inst1_gt_do_r_4[2]), + .Q(plm_v4f_mgt_gt1_do[2]) + ); + FDE plm_v4f_mgt_for_v1_4_cal_inst1_gt_do_r_1_ ( + .CE(plm_v4f_mgt_for_v1_4_cal_inst1_N_1030_i_520), + .C(NlwRenamedSig_OI_trn_clk), + .D(plm_v4f_mgt_for_v1_4_cal_inst1_gt_do_r_4[1]), + .Q(plm_v4f_mgt_gt1_do[1]) + ); + FDE plm_v4f_mgt_for_v1_4_cal_inst1_gt_do_r_0_ ( + .CE(plm_v4f_mgt_for_v1_4_cal_inst1_N_1030_i_520), + .C(NlwRenamedSig_OI_trn_clk), + .D(plm_v4f_mgt_for_v1_4_cal_inst1_gt_do_r_4[0]), + .Q(plm_v4f_mgt_gt1_do[0]) + ); + FDE plm_v4f_mgt_for_v1_4_cal_inst1_GT_DADDR_1_5_ ( + .CE(plm_v4f_mgt_for_v1_4_cal_inst1_N_1030_i_520), + .C(NlwRenamedSig_OI_trn_clk), + .D(plm_v4f_mgt_for_v1_4_cal_inst1_N_313_i), + .Q(plm_v4f_mgt_gt1_daddr[5]) + ); + FDE plm_v4f_mgt_for_v1_4_cal_inst1_GT_DADDR_1_3_ ( + .CE(plm_v4f_mgt_for_v1_4_cal_inst1_N_1030_i_520), + .C(NlwRenamedSig_OI_trn_clk), + .D(plm_v4f_mgt_for_v1_4_cal_inst1_cb_state_i[3]), + .Q(plm_v4f_mgt_gt1_daddr[3]) + ); + FDE plm_v4f_mgt_for_v1_4_cal_inst1_GT_DADDR_1_2_ ( + .CE(plm_v4f_mgt_for_v1_4_cal_inst1_N_1030_i_520), + .C(NlwRenamedSig_OI_trn_clk), + .D(plm_v4f_mgt_for_v1_4_cal_inst1_N_309_i), + .Q(plm_v4f_mgt_gt1_daddr[2]) + ); + FDE plm_v4f_mgt_for_v1_4_cal_inst1_GT_DADDR_1_1_ ( + .CE(plm_v4f_mgt_for_v1_4_cal_inst1_N_1030_i_520), + .C(NlwRenamedSig_OI_trn_clk), + .D(plm_v4f_mgt_for_v1_4_cal_inst1_GT_DADDR_5_i_i_a3_0[1]), + .Q(plm_v4f_mgt_gt1_daddr[1]) + ); + FDE plm_v4f_mgt_for_v1_4_cal_inst1_GT_DADDR_1_0_ ( + .CE(plm_v4f_mgt_for_v1_4_cal_inst1_N_1030_i_520), + .C(NlwRenamedSig_OI_trn_clk), + .D(plm_v4f_mgt_for_v1_4_cal_inst1_N_391_i_i), + .Q(plm_v4f_mgt_gt1_daddr[4]) + ); + INV plm_v4f_mgt_for_v1_4_cal_inst1_cb_state_i_2_ ( + .I(plm_v4f_mgt_for_v1_4_cal_inst1_cb_state[2]), + .O(plm_v4f_mgt_for_v1_4_cal_inst1_cb_state_i[2]) + ); + INV plm_v4f_mgt_for_v1_4_cal_inst1_N_1030_i ( + .I(plm_v4f_mgt_for_v1_4_cal_inst1_cb_state_4_i_0_o2_0[1]), + .O(plm_v4f_mgt_for_v1_4_cal_inst1_N_1030_i_520) + ); + defparam plm_des0_input_decoder_reg_sym_3_0_a7_1_.INIT = 4'h1; + LUT2 plm_des0_input_decoder_reg_sym_3_0_a7_1_ ( + .I0(plm_des0_reg_nitbl[1]), + .I1(plm_des0_reg_spesh[1]), + .O(plm_des0_reg_sym_3[1]) + ); + defparam plm_des0_input_decoder_reg_sym_4_0_a7_0_.INIT = 4'h1; + LUT2 plm_des0_input_decoder_reg_sym_4_0_a7_0_ ( + .I0(plm_des0_reg_nitbl[0]), + .I1(plm_des0_reg_spesh[0]), + .O(plm_des0_reg_sym_4[0]) + ); + defparam plm_des0_descram_reg_rx_des_dat_14_sn_m1_0_a2_0_a3_0_a2.INIT = 4'h1; + LUT2 plm_des0_descram_reg_rx_des_dat_14_sn_m1_0_a2_0_a3_0_a2 ( + .I0(plm_des0_reg_dis_539), + .I1(plm_des0_reg_kkk[0]), + .O(plm_des0_m1_0_a2_0_a3_0_a2) + ); + defparam plm_des0_lfsrs_reg_lfsr_one_12_0_iv_i_i_o4_0_.INIT = 4'h1; + LUT2 plm_des0_lfsrs_reg_lfsr_one_12_0_iv_i_i_o4_0_ ( + .I0(plm_des0_reg_skp[0]), + .I1(plm_des0_reg_skp[1]), + .O(plm_des0_N_35105_i) + ); + defparam plm_des0_descram_reg_rx_des_dat_7_i_x2_0_o4_0_8_.INIT = 4'h1; + LUT2 plm_des0_descram_reg_rx_des_dat_7_i_x2_0_o4_0_8_ ( + .I0(plm_des0_reg_dis_539), + .I1(plm_des0_reg_kkk[1]), + .O(plm_des0_N_35107_i) + ); + defparam plm_des0_lfsrs_reg_lfsr_two_12_0_iv_0_o2_12_.INIT = 4'h1; + LUT2 plm_des0_lfsrs_reg_lfsr_two_12_0_iv_0_o2_12_ ( + .I0(plm_des0_reg_com[0]), + .I1(plm_des0_reg_com[1]), + .O(plm_des0_reg_lfsr_two_12_0_iv_0_o2[12]) + ); + defparam plm_des0_one_adv2_1_15_.INIT = 4'h6; + LUT2 plm_des0_one_adv2_1_15_ ( + .I0(plm_des0_reg_lfsr_one_10__540), + .I1(plm_des0_reg_lfsr_one_11__374), + .O(plm_des0_one_adv2_1_15__521) + ); + defparam plm_des0_one_adv2_1_13_.INIT = 4'h6; + LUT2 plm_des0_one_adv2_1_13_ ( + .I0(plm_des0_reg_lfsr_one_8__542), + .I1(plm_des0_reg_lfsr_one_9__541), + .O(plm_des0_one_adv2_1_13__522) + ); + defparam plm_des0_one_adv2_1_9_.INIT = 4'h6; + LUT2 plm_des0_one_adv2_1_9_ ( + .I0(plm_des0_reg_lfsr_one_4__546), + .I1(plm_des0_reg_lfsr_one_5__545), + .O(plm_des0_one_adv2_1_9__529) + ); + defparam plm_des0_one_adv2_1_6_.INIT = 4'h6; + LUT2 plm_des0_one_adv2_1_6_ ( + .I0(plm_des0_reg_lfsr_one_1__333), + .I1(plm_des0_reg_lfsr_one_12__365), + .O(plm_des0_one_adv2_1_6__527) + ); + defparam plm_des0_one_adv2_1_5_.INIT = 4'h6; + LUT2 plm_des0_one_adv2_1_5_ ( + .I0(plm_des0_reg_lfsr_one_2__547), + .I1(plm_des0_reg_lfsr_one_13__337), + .O(plm_des0_one_adv2_1_5__528) + ); + defparam plm_des0_two_adv2_1_14_.INIT = 4'h6; + LUT2 plm_des0_two_adv2_1_14_ ( + .I0(plm_des0_reg_lfsr_two_9__551), + .I1(plm_des0_reg_lfsr_two_10__550), + .O(plm_des0_two_adv2_1_14__523) + ); + defparam plm_des0_two_adv2_1_12_.INIT = 4'h6; + LUT2 plm_des0_two_adv2_1_12_ ( + .I0(plm_des0_reg_lfsr_two_7__553), + .I1(plm_des0_reg_lfsr_two_8__552), + .O(plm_des0_two_adv2_1_12__524) + ); + defparam plm_des0_two_adv2_1_10_.INIT = 4'h6; + LUT2 plm_des0_two_adv2_1_10_ ( + .I0(plm_des0_reg_lfsr_two_5__555), + .I1(plm_des0_reg_lfsr_two_6__554), + .O(plm_des0_two_adv2_1_10__530) + ); + defparam plm_des0_two_adv2_1_7_.INIT = 4'h6; + LUT2 plm_des0_two_adv2_1_7_ ( + .I0(plm_des0_reg_lfsr_two_2__380), + .I1(plm_des0_reg_lfsr_two_13__344), + .O(plm_des0_two_adv2_1_7__526) + ); + defparam plm_des0_two_adv2_1_1_.INIT = 4'h6; + LUT2 plm_des0_two_adv2_1_1_ ( + .I0(plm_des0_reg_lfsr_two_12__549), + .I1(plm_des0_reg_lfsr_two_13__344), + .O(plm_des0_two_adv2_1_1__525) + ); + defparam plm_des0_input_decoder_reg_bad_4_i_a7_2_0_0_.INIT = 4'h4; + LUT2_L plm_des0_input_decoder_reg_bad_4_i_a7_2_0_0_ ( + .I0(plm_des0_reg_data[5]), + .I1(plm_des0_reg_data[7]), + .LO(plm_des0_reg_bad_4_i_a7_2_0[0]) + ); + defparam plm_des0_input_decoder_reg_bad_3_i_a7_2_0_1_.INIT = 4'h4; + LUT2_L plm_des0_input_decoder_reg_bad_3_i_a7_2_0_1_ ( + .I0(plm_des0_reg_data[13]), + .I1(plm_des0_reg_data[15]), + .LO(plm_des0_reg_bad_3_i_a7_2_0[1]) + ); + defparam plm_des0_lfsrs_reg_lfsr_one32_i.INIT = 4'h7; + LUT2 plm_des0_lfsrs_reg_lfsr_one32_i ( + .I0(plm_des0_reg_skp[0]), + .I1(plm_des0_reg_skp[1]), + .O(plm_des0_reg_lfsr_one32_i) + ); + defparam plm_des0_input_decoder_reg_bad_3_i_x2_1_.INIT = 16'h7888; + LUT4 plm_des0_input_decoder_reg_bad_3_i_x2_1_ ( + .I0(plm_des0_reg_data[8]), + .I1(plm_des0_reg_data[9]), + .I2(plm_des0_reg_data[10]), + .I3(plm_des0_reg_data[11]), + .O(plm_des0_N_11969_i) + ); + defparam plm_des0_input_decoder_reg_bad_3_i_x2_0_1_.INIT = 16'hE111; + LUT4 plm_des0_input_decoder_reg_bad_3_i_x2_0_1_ ( + .I0(plm_des0_reg_data[8]), + .I1(plm_des0_reg_data[9]), + .I2(plm_des0_reg_data[14]), + .I3(plm_des0_reg_data[15]), + .O(plm_des0_N_11970_i) + ); + defparam plm_des0_input_decoder_reg_bad_4_i_x2_0_.INIT = 16'h7888; + LUT4 plm_des0_input_decoder_reg_bad_4_i_x2_0_ ( + .I0(plm_des0_reg_data[0]), + .I1(plm_des0_reg_data[1]), + .I2(plm_des0_reg_data[2]), + .I3(plm_des0_reg_data[3]), + .O(plm_des0_N_12016_i) + ); + defparam plm_des0_input_decoder_reg_bad_4_i_x2_0_0_.INIT = 16'hE111; + LUT4 plm_des0_input_decoder_reg_bad_4_i_x2_0_0_ ( + .I0(plm_des0_reg_data[0]), + .I1(plm_des0_reg_data[1]), + .I2(plm_des0_reg_data[6]), + .I3(plm_des0_reg_data[7]), + .O(plm_des0_N_12017_i) + ); + defparam plm_des0_input_decoder_reg_idl_4_0_a7_2_0_.INIT = 16'h1000; + LUT4 plm_des0_input_decoder_reg_idl_4_0_a7_2_0_ ( + .I0(plm_des0_reg_data[0]), + .I1(plm_des0_reg_data[1]), + .I2(plm_des0_reg_data[2]), + .I3(plm_des0_reg_data[3]), + .O(plm_des0_reg_idl_4_2[0]) + ); + defparam plm_des0_input_decoder_reg_idl_3_0_a7_2_1_.INIT = 16'h1000; + LUT4 plm_des0_input_decoder_reg_idl_3_0_a7_2_1_ ( + .I0(plm_des0_reg_data[8]), + .I1(plm_des0_reg_data[9]), + .I2(plm_des0_reg_data[10]), + .I3(plm_des0_reg_data[11]), + .O(plm_des0_reg_idl_3_2[1]) + ); + defparam plm_des0_lfsrs_reg_lfsr_two_12_iv_0_0_o4_9_.INIT = 8'h23; + LUT3 plm_des0_lfsrs_reg_lfsr_two_12_iv_0_0_o4_9_ ( + .I0(plm_des0_reg_com[1]), + .I1(plm_des0_reg_skp[0]), + .I2(plm_des0_reg_skp[1]), + .O(plm_des0_reg_lfsr_two_12_iv_0_0_o4[9]) + ); + defparam plm_des0_lfsrs_reg_lfsr_two_12_iv_0_0_o2_9_.INIT = 8'h15; + LUT3 plm_des0_lfsrs_reg_lfsr_two_12_iv_0_0_o2_9_ ( + .I0(plm_des0_reg_com[0]), + .I1(plm_des0_reg_com[1]), + .I2(plm_des0_reg_skp[0]), + .O(plm_des0_N_35106_i) + ); + defparam plm_des0_two_adv2_1_6_.INIT = 8'h96; + LUT3 plm_des0_two_adv2_1_6_ ( + .I0(plm_des0_reg_lfsr_two_3__556), + .I1(plm_des0_reg_lfsr_two_12__549), + .I2(plm_des0_reg_lfsr_two_14__548), + .O(plm_des0_two_adv2_1_6__532) + ); + defparam plm_des0_two_adv2_15_.INIT = 16'h6996; + LUT4 plm_des0_two_adv2_15_ ( + .I0(plm_des0_reg_lfsr_two_10__550), + .I1(plm_des0_reg_lfsr_two_11__343), + .I2(plm_des0_reg_lfsr_two_12__549), + .I3(plm_des0_reg_lfsr_two_15__345), + .O(plm_des0_two_adv2_15__534) + ); + defparam plm_des0_one_adv2_2_.INIT = 8'h96; + LUT3 plm_des0_one_adv2_2_ ( + .I0(plm_des0_one_adv2_1_5__528), + .I1(plm_des0_reg_lfsr_one_14__377), + .I2(plm_des0_reg_lfsr_one_15__334), + .O(plm_des0_one_adv2[2]) + ); + defparam plm_des0_one_adv2_1_.INIT = 8'h96; + LUT3 plm_des0_one_adv2_1_ ( + .I0(plm_des0_one_adv2_1_6__527), + .I1(plm_des0_reg_lfsr_one_13__337), + .I2(plm_des0_reg_lfsr_one_14__377), + .O(plm_des0_one_adv2[1]) + ); + defparam plm_des0_two_adv2_12_.INIT = 8'h96; + LUT3 plm_des0_two_adv2_12_ ( + .I0(plm_des0_reg_lfsr_two_9__551), + .I1(plm_des0_reg_lfsr_two_12__549), + .I2(plm_des0_two_adv2_1_12__524), + .O(plm_des0_two_adv2_12__535) + ); + defparam plm_des0_two_adv2_10_.INIT = 8'h96; + LUT3 plm_des0_two_adv2_10_ ( + .I0(plm_des0_reg_lfsr_two_7__553), + .I1(plm_des0_reg_lfsr_two_10__550), + .I2(plm_des0_two_adv2_1_10__530), + .O(plm_des0_two_adv2_10__536) + ); + defparam plm_des0_one_adv2_15_.INIT = 8'h96; + LUT3 plm_des0_one_adv2_15_ ( + .I0(plm_des0_one_adv2_1_15__521), + .I1(plm_des0_reg_lfsr_one_12__365), + .I2(plm_des0_reg_lfsr_one_15__334), + .O(plm_des0_one_adv2[15]) + ); + defparam plm_des0_one_adv2_14_.INIT = 8'h96; + LUT3 plm_des0_one_adv2_14_ ( + .I0(plm_des0_one_adv2_1_15__521), + .I1(plm_des0_reg_lfsr_one_9__541), + .I2(plm_des0_reg_lfsr_one_14__377), + .O(plm_des0_one_adv2[14]) + ); + defparam plm_des0_one_adv2_13_.INIT = 8'h96; + LUT3 plm_des0_one_adv2_13_ ( + .I0(plm_des0_one_adv2_1_13__522), + .I1(plm_des0_reg_lfsr_one_10__540), + .I2(plm_des0_reg_lfsr_one_13__337), + .O(plm_des0_one_adv2[13]) + ); + defparam plm_des0_one_adv2_12_.INIT = 8'h96; + LUT3 plm_des0_one_adv2_12_ ( + .I0(plm_des0_one_adv2_1_13__522), + .I1(plm_des0_reg_lfsr_one_7__543), + .I2(plm_des0_reg_lfsr_one_12__365), + .O(plm_des0_one_adv2[12]) + ); + defparam plm_des0_one_adv2_11_.INIT = 16'h6996; + LUT4 plm_des0_one_adv2_11_ ( + .I0(plm_des0_reg_lfsr_one_6__544), + .I1(plm_des0_reg_lfsr_one_7__543), + .I2(plm_des0_reg_lfsr_one_8__542), + .I3(plm_des0_reg_lfsr_one_11__374), + .O(plm_des0_one_adv2[11]) + ); + defparam plm_des0_one_adv2_10_.INIT = 16'h6996; + LUT4 plm_des0_one_adv2_10_ ( + .I0(plm_des0_reg_lfsr_one_5__545), + .I1(plm_des0_reg_lfsr_one_6__544), + .I2(plm_des0_reg_lfsr_one_7__543), + .I3(plm_des0_reg_lfsr_one_10__540), + .O(plm_des0_one_adv2[10]) + ); + defparam plm_des0_input_decoder_reg_t1n_4_0_a7_1_0_0_.INIT = 16'h0800; + LUT4 plm_des0_input_decoder_reg_t1n_4_0_a7_1_0_0_ ( + .I0(plm_des0_reg_data[4]), + .I1(plm_des0_reg_data[5]), + .I2(plm_des0_reg_data[6]), + .I3(plm_des0_reg_data[7]), + .O(plm_des0_reg_t1n_4_1[0]) + ); + defparam plm_des0_input_decoder_reg_t1p_4_0_a7_1_0_0_.INIT = 16'h0010; + LUT4 plm_des0_input_decoder_reg_t1p_4_0_a7_1_0_0_ ( + .I0(plm_des0_reg_data[4]), + .I1(plm_des0_reg_data[5]), + .I2(plm_des0_reg_data[6]), + .I3(plm_des0_reg_data[7]), + .O(plm_des0_reg_t1p_4_1[0]) + ); + defparam plm_des0_input_decoder_reg_t2n_3_0_a7_1_0_1_.INIT = 16'h0800; + LUT4 plm_des0_input_decoder_reg_t2n_3_0_a7_1_0_1_ ( + .I0(plm_des0_reg_data[12]), + .I1(plm_des0_reg_data[13]), + .I2(plm_des0_reg_data[14]), + .I3(plm_des0_reg_data[15]), + .O(plm_des0_reg_t2n_3_1_0[1]) + ); + defparam plm_des0_input_decoder_reg_t2p_3_0_a7_1_0_1_.INIT = 16'h0010; + LUT4 plm_des0_input_decoder_reg_t2p_3_0_a7_1_0_1_ ( + .I0(plm_des0_reg_data[12]), + .I1(plm_des0_reg_data[13]), + .I2(plm_des0_reg_data[14]), + .I3(plm_des0_reg_data[15]), + .O(plm_des0_reg_t2p_3_1_0[1]) + ); + defparam plm_des0_two_adv2_1_8_.INIT = 8'h96; + LUT3 plm_des0_two_adv2_1_8_ ( + .I0(plm_des0_reg_lfsr_two_4__378), + .I1(plm_des0_reg_lfsr_two_5__555), + .I2(plm_des0_reg_lfsr_two_8__552), + .O(plm_des0_two_adv2_1_8__531) + ); + defparam plm_des0_input_decoder_reg_t1n_4_0_a7_2_0_0_.INIT = 16'h0020; + LUT4 plm_des0_input_decoder_reg_t1n_4_0_a7_2_0_0_ ( + .I0(plm_des0_reg_data[0]), + .I1(plm_des0_reg_data[1]), + .I2(plm_des0_reg_data[2]), + .I3(plm_des0_reg_data[3]), + .O(plm_des0_reg_t1n_4_0_a7_2_0[0]) + ); + defparam plm_des0_input_decoder_reg_t2n_3_0_a7_2_0_1_.INIT = 16'h0400; + LUT4 plm_des0_input_decoder_reg_t2n_3_0_a7_2_0_1_ ( + .I0(plm_des0_reg_data[8]), + .I1(plm_des0_reg_data[9]), + .I2(plm_des0_reg_data[10]), + .I3(plm_des0_reg_data[11]), + .O(plm_des0_reg_t2n_3_0_a7_2_0[1]) + ); + defparam plm_des0_input_decoder_reg_t2p_3_0_a7_2_0_1_.INIT = 16'h0020; + LUT4 plm_des0_input_decoder_reg_t2p_3_0_a7_2_0_1_ ( + .I0(plm_des0_reg_data[8]), + .I1(plm_des0_reg_data[9]), + .I2(plm_des0_reg_data[10]), + .I3(plm_des0_reg_data[11]), + .O(plm_des0_reg_t2p_3_0_a7_2_0[1]) + ); + defparam plm_des0_input_decoder_reg_t1p_4_0_a7_2_0_0_.INIT = 16'h0400; + LUT4 plm_des0_input_decoder_reg_t1p_4_0_a7_2_0_0_ ( + .I0(plm_des0_reg_data[0]), + .I1(plm_des0_reg_data[1]), + .I2(plm_des0_reg_data[2]), + .I3(plm_des0_reg_data[3]), + .O(plm_des0_reg_t1p_4_0_a7_2_0[0]) + ); + defparam plm_des0_two_adv2_1_4_.INIT = 16'h6996; + LUT4 plm_des0_two_adv2_1_4_ ( + .I0(plm_des0_reg_lfsr_two_0__342), + .I1(plm_des0_reg_lfsr_two_1__379), + .I2(plm_des0_reg_lfsr_two_11__343), + .I3(plm_des0_reg_lfsr_two_14__548), + .O(plm_des0_two_adv2_1_4__533) + ); + defparam plm_des0_input_decoder_reg_stp_3_0_a7_1_0_0_1_.INIT = 16'h8000; + LUT4 plm_des0_input_decoder_reg_stp_3_0_a7_1_0_0_1_ ( + .I0(plm_des0_reg_data[8]), + .I1(plm_des0_reg_data[9]), + .I2(plm_des0_reg_data[14]), + .I3(plm_des0_reg_data[15]), + .O(plm_des0_reg_stp_3_0_a7_1_0_0[1]) + ); + defparam plm_des0_input_decoder_reg_edg_4_0_a7_1_0_0_0_.INIT = 16'h8000; + LUT4 plm_des0_input_decoder_reg_edg_4_0_a7_1_0_0_0_ ( + .I0(plm_des0_reg_data[2]), + .I1(plm_des0_reg_data[3]), + .I2(plm_des0_reg_data[6]), + .I3(plm_des0_reg_data[7]), + .O(plm_des0_reg_edg_4_0_a7_1_0_0[0]) + ); + defparam plm_des0_input_decoder_reg_pad_4_0_a7_1_0_0_0_.INIT = 16'h8000; + LUT4 plm_des0_input_decoder_reg_pad_4_0_a7_1_0_0_0_ ( + .I0(plm_des0_reg_data[0]), + .I1(plm_des0_reg_data[1]), + .I2(plm_des0_reg_data[6]), + .I3(plm_des0_reg_data[7]), + .O(plm_des0_reg_pad_4_0_a7_1_0_0[0]) + ); + defparam plm_des0_input_decoder_reg_edg_3_0_a7_1_0_0_1_.INIT = 16'h8000; + LUT4 plm_des0_input_decoder_reg_edg_3_0_a7_1_0_0_1_ ( + .I0(plm_des0_reg_data[10]), + .I1(plm_des0_reg_data[11]), + .I2(plm_des0_reg_data[14]), + .I3(plm_des0_reg_data[15]), + .O(plm_des0_reg_edg_3_0_a7_1_0_0[1]) + ); + defparam plm_des0_input_decoder_reg_idl_4_0_a7_1_0_.INIT = 16'h0800; + LUT4 plm_des0_input_decoder_reg_idl_4_0_a7_1_0_ ( + .I0(plm_des0_reg_data[4]), + .I1(plm_des0_reg_data[5]), + .I2(plm_des0_reg_nitbl[0]), + .I3(plm_des0_reg_spesh[0]), + .O(plm_des0_reg_idl_4_1[0]) + ); + defparam plm_des0_input_decoder_reg_idl_3_0_a7_1_1_.INIT = 16'h0800; + LUT4 plm_des0_input_decoder_reg_idl_3_0_a7_1_1_ ( + .I0(plm_des0_reg_data[12]), + .I1(plm_des0_reg_data[13]), + .I2(plm_des0_reg_nitbl[1]), + .I3(plm_des0_reg_spesh[1]), + .O(plm_des0_reg_idl_3_1[1]) + ); + defparam plm_des0_lfsrs_reg_lfsr_two_12_iv_i_0_a2_15_.INIT = 4'h4; + LUT2_L plm_des0_lfsrs_reg_lfsr_two_12_iv_i_0_a2_15_ ( + .I0(plm_des0_reg_lfsr_two_12_iv_0_0_o4[9]), + .I1(plm_des0_one_adv2[15]), + .LO(plm_des0_reg_lfsr_two_12_iv_i_0_a2[15]) + ); + defparam plm_des0_lfsrs_reg_lfsr_two_12_iv_i_0_a2_0_14_.INIT = 16'h8228; + LUT4 plm_des0_lfsrs_reg_lfsr_two_12_iv_i_0_a2_0_14_ ( + .I0(plm_des0_reg_lfsr_two_12_iv_0_0_a4_1[9]), + .I1(plm_des0_reg_lfsr_two_11__343), + .I2(plm_des0_reg_lfsr_two_14__548), + .I3(plm_des0_two_adv2_1_14__523), + .O(plm_des0_reg_lfsr_two_12_iv_i_0_a2_0_14_) + ); + defparam plm_des0_lfsrs_reg_lfsr_two_12_iv_i_0_a2_0_13_.INIT = 16'h8228; + LUT4 plm_des0_lfsrs_reg_lfsr_two_12_iv_i_0_a2_0_13_ ( + .I0(plm_des0_reg_lfsr_two_12_iv_0_0_a4_1[9]), + .I1(plm_des0_reg_lfsr_two_8__552), + .I2(plm_des0_reg_lfsr_two_13__344), + .I3(plm_des0_two_adv2_1_14__523), + .O(plm_des0_reg_lfsr_two_12_iv_i_0_a2_0_13_) + ); + defparam plm_des0_lfsrs_reg_lfsr_two_12_iv_i_0_a2_0_11_.INIT = 16'h8228; + LUT4_L plm_des0_lfsrs_reg_lfsr_two_12_iv_i_0_a2_0_11_ ( + .I0(plm_des0_reg_lfsr_two_12_iv_0_0_a4_1[9]), + .I1(plm_des0_reg_lfsr_two_6__554), + .I2(plm_des0_reg_lfsr_two_11__343), + .I3(plm_des0_two_adv2_1_12__524), + .LO(plm_des0_reg_lfsr_two_12_iv_i_0_a2_0_11_) + ); + defparam plm_des0_lfsrs_reg_lfsr_two_12_iv_i_0_a2_0_2_.INIT = 16'h8228; + LUT4 plm_des0_lfsrs_reg_lfsr_two_12_iv_i_0_a2_0_2_ ( + .I0(plm_des0_reg_lfsr_two_12_iv_0_0_a4_1[9]), + .I1(plm_des0_reg_lfsr_two_14__548), + .I2(plm_des0_reg_lfsr_two_15__345), + .I3(plm_des0_two_adv2_1_7__526), + .O(plm_des0_reg_lfsr_two_12_iv_i_0_a2_0_2_) + ); + defparam plm_des0_lfsrs_reg_lfsr_two_12_iv_i_0_a2_0_1_.INIT = 16'h8228; + LUT4 plm_des0_lfsrs_reg_lfsr_two_12_iv_i_0_a2_0_1_ ( + .I0(plm_des0_reg_lfsr_two_12_iv_0_0_a4_1[9]), + .I1(plm_des0_reg_lfsr_two_1__379), + .I2(plm_des0_reg_lfsr_two_14__548), + .I3(plm_des0_two_adv2_1_1__525), + .O(plm_des0_reg_lfsr_two_12_iv_i_0_a2_0_1_) + ); + defparam plm_des0_lfsrs_reg_lfsr_two_12_iv_i_0_a2_0_0_.INIT = 16'h8228; + LUT4 plm_des0_lfsrs_reg_lfsr_two_12_iv_i_0_a2_0_0_ ( + .I0(plm_des0_reg_lfsr_two_12_iv_0_0_a4_1[9]), + .I1(plm_des0_reg_lfsr_two_0__342), + .I2(plm_des0_reg_lfsr_two_11__343), + .I3(plm_des0_two_adv2_1_1__525), + .O(plm_des0_reg_lfsr_two_12_iv_i_0_a2_0_0_) + ); + defparam plm_des0_lfsrs_reg_lfsr_one_12_iv_i_0_a2_0_12_.INIT = 4'h8; + LUT2_L plm_des0_lfsrs_reg_lfsr_one_12_iv_i_0_a2_0_12_ ( + .I0(plm_des0_reg_lfsr_two_12_iv_0_0_a4_1[9]), + .I1(plm_des0_one_adv2[12]), + .LO(plm_des0_reg_lfsr_one_12_iv_i_0_a2_0_12_) + ); + defparam plm_des0_lfsrs_reg_lfsr_one_12_iv_i_0_a2_0_10_.INIT = 4'h8; + LUT2_L plm_des0_lfsrs_reg_lfsr_one_12_iv_i_0_a2_0_10_ ( + .I0(plm_des0_reg_lfsr_two_12_iv_0_0_a4_1[9]), + .I1(plm_des0_one_adv2[10]), + .LO(plm_des0_reg_lfsr_one_12_iv_i_0_a2_0_10_) + ); + defparam plm_des0_lfsrs_reg_lfsr_one_12_iv_i_0_a2_9_.INIT = 4'h4; + LUT2 plm_des0_lfsrs_reg_lfsr_one_12_iv_i_0_a2_9_ ( + .I0(plm_des0_reg_lfsr_two_12_iv_0_0_o4[9]), + .I1(plm_des0_reg_lfsr_two_9__551), + .O(plm_des0_reg_lfsr_one_12_iv_i_0_a2_9_) + ); + defparam plm_des0_lfsrs_reg_lfsr_one_12_iv_i_0_a2_8_.INIT = 4'h4; + LUT2 plm_des0_lfsrs_reg_lfsr_one_12_iv_i_0_a2_8_ ( + .I0(plm_des0_reg_lfsr_two_12_iv_0_0_o4[9]), + .I1(plm_des0_reg_lfsr_two_8__552), + .O(plm_des0_reg_lfsr_one_12_iv_i_0_a2_8_) + ); + defparam plm_des0_lfsrs_reg_lfsr_one_12_iv_i_0_a2_3_.INIT = 4'h4; + LUT2 plm_des0_lfsrs_reg_lfsr_one_12_iv_i_0_a2_3_ ( + .I0(plm_des0_reg_lfsr_two_12_iv_0_0_o4[9]), + .I1(plm_des0_reg_lfsr_two_3__556), + .O(plm_des0_reg_lfsr_one_12_iv_i_0_a2_3_) + ); + defparam plm_des0_lfsrs_reg_lfsr_one_12_0_iv_i_i_x4_0_.INIT = 4'h6; + LUT2 plm_des0_lfsrs_reg_lfsr_one_12_0_iv_i_i_x4_0_ ( + .I0(G_377_366), + .I1(plm_des0_reg_lfsr_one_13__337), + .O(plm_des0_N_35110_i_0) + ); + defparam plm_des0_descram_N_68296_i.INIT = 8'h57; + LUT3 plm_des0_descram_N_68296_i ( + .I0(plm_des0_m1_0_a2_0_a3_0_a2), + .I1(plm_des0_reg_com[1]), + .I2(plm_des0_reg_skp[1]), + .O(plm_des0_N_68296_i) + ); + defparam plm_des0_two_adv2_7_.INIT = 16'h6996; + LUT4 plm_des0_two_adv2_7_ ( + .I0(N_35130_i_0), + .I1(plm_des0_reg_lfsr_two_3__556), + .I2(plm_des0_reg_lfsr_two_7__553), + .I3(plm_des0_two_adv2_1_7__526), + .O(plm_des0_two_adv2_7__537) + ); + defparam plm_des0_one_adv2_6_.INIT = 16'h6996; + LUT4 plm_des0_one_adv2_6_ ( + .I0(N_35131_i_0), + .I1(plm_des0_one_adv2_1_6__527), + .I2(plm_des0_reg_lfsr_one_2__547), + .I3(plm_des0_reg_lfsr_one_6__544), + .O(plm_des0_one_adv2[6]) + ); + defparam plm_des0_one_adv2_7_.INIT = 16'h6996; + LUT4 plm_des0_one_adv2_7_ ( + .I0(G_326_338), + .I1(plm_des0_reg_lfsr_one_2__547), + .I2(plm_des0_reg_lfsr_one_4__546), + .I3(plm_des0_reg_lfsr_one_7__543), + .O(plm_des0_one_adv2[7]) + ); + defparam plm_des0_one_adv2_9_.INIT = 16'h6996; + LUT4 plm_des0_one_adv2_9_ ( + .I0(plm_des0_one_adv2_1_9__529), + .I1(plm_des0_reg_lfsr_one_6__544), + .I2(plm_des0_reg_lfsr_one_9__541), + .I3(plm_des0_reg_lfsr_one_15__334), + .O(plm_des0_one_adv2[9]) + ); + defparam plm_des0_two_adv2_6_.INIT = 8'h96; + LUT3 plm_des0_two_adv2_6_ ( + .I0(N_35117_i_0), + .I1(plm_des0_reg_lfsr_two_6__554), + .I2(plm_des0_two_adv2_1_6__532), + .O(plm_des0_two_adv2_6__538) + ); + defparam plm_des0_one_adv2_5_.INIT = 8'h96; + LUT3 plm_des0_one_adv2_5_ ( + .I0(G_325_335), + .I1(plm_des0_one_adv2_1_5__528), + .I2(plm_des0_reg_lfsr_one_5__545), + .O(plm_des0_one_adv2[5]) + ); + defparam plm_des0_one_adv2_4_.INIT = 8'h96; + LUT3 plm_des0_one_adv2_4_ ( + .I0(G_325_335), + .I1(plm_des0_reg_lfsr_one_4__546), + .I2(plm_des0_reg_lfsr_one_14__377), + .O(plm_des0_one_adv2[4]) + ); + defparam plm_des0_one_adv2_8_.INIT = 8'h96; + LUT3 plm_des0_one_adv2_8_ ( + .I0(N_35131_i_0), + .I1(plm_des0_one_adv2_1_9__529), + .I2(plm_des0_reg_lfsr_one_8__542), + .O(plm_des0_one_adv2[8]) + ); + defparam plm_des0_input_decoder_reg_skp_3_0_a7_1_0_1_.INIT = 16'h0200; + LUT4 plm_des0_input_decoder_reg_skp_3_0_a7_1_0_1_ ( + .I0(plm_des0_reg_data[12]), + .I1(plm_des0_reg_data[13]), + .I2(plm_des0_reg_nitbl[1]), + .I3(plm_des0_reg_spesh[1]), + .O(plm_des0_reg_skp_3_0_a7_1_0[1]) + ); + defparam plm_des0_input_decoder_reg_sdp_4_0_a7_1_0_0_0_.INIT = 16'h0200; + LUT4 plm_des0_input_decoder_reg_sdp_4_0_a7_1_0_0_0_ ( + .I0(plm_des0_reg_data[4]), + .I1(plm_des0_reg_data[5]), + .I2(plm_des0_reg_nitbl[0]), + .I3(plm_des0_reg_spesh[0]), + .O(plm_des0_reg_sdp_4_0_a7_1_0_0[0]) + ); + defparam plm_des0_input_decoder_reg_bad_3_i_1_1_.INIT = 16'h54FF; + LUT4_L plm_des0_input_decoder_reg_bad_3_i_1_1_ ( + .I0(plm_des0_reg_bad_3_i_a7_2_0[1]), + .I1(plm_des0_reg_data[10]), + .I2(plm_des0_reg_data[11]), + .I3(plm_des0_reg_spesh[1]), + .LO(plm_des0_reg_bad_3_i_1[1]) + ); + defparam plm_des0_input_decoder_reg_bad_4_i_1_0_.INIT = 16'h54FF; + LUT4_L plm_des0_input_decoder_reg_bad_4_i_1_0_ ( + .I0(plm_des0_reg_bad_4_i_a7_2_0[0]), + .I1(plm_des0_reg_data[2]), + .I2(plm_des0_reg_data[3]), + .I3(plm_des0_reg_spesh[0]), + .LO(plm_des0_reg_bad_4_i_1[0]) + ); + defparam plm_des0_lfsrs_reg_lfsr_two_12_iv_0_0_a2_0_9_.INIT = 16'h4884; + LUT4 plm_des0_lfsrs_reg_lfsr_two_12_iv_0_0_a2_0_9_ ( + .I0(N_35130_i_0), + .I1(plm_des0_reg_lfsr_two_12_iv_0_0_a4_1[9]), + .I2(plm_des0_reg_lfsr_two_9__551), + .I3(plm_des0_two_adv2_1_10__530), + .O(plm_des0_reg_lfsr_two_12_iv_0_0_a2_0_9_) + ); + defparam plm_des0_lfsrs_reg_lfsr_two_12_iv_0_0_a2_0_8_.INIT = 16'h2882; + LUT4 plm_des0_lfsrs_reg_lfsr_two_12_iv_0_0_a2_0_8_ ( + .I0(plm_des0_reg_lfsr_two_12_iv_0_0_a4_1[9]), + .I1(plm_des0_reg_lfsr_two_3__556), + .I2(plm_des0_reg_lfsr_two_14__548), + .I3(plm_des0_two_adv2_1_8__531), + .O(plm_des0_reg_lfsr_two_12_iv_0_0_a2_0_8_) + ); + defparam plm_des0_lfsrs_reg_lfsr_two_12_iv_0_0_a2_0_5_.INIT = 16'h6090; + LUT4 plm_des0_lfsrs_reg_lfsr_two_12_iv_0_0_a2_0_5_ ( + .I0(G_329_346), + .I1(N_35117_i_0), + .I2(plm_des0_reg_lfsr_two_12_iv_0_0_a4_1[9]), + .I3(plm_des0_reg_lfsr_two_5__555), + .O(plm_des0_reg_lfsr_two_12_iv_0_0_a2_0_5_) + ); + defparam plm_des0_lfsrs_reg_lfsr_two_12_iv_0_0_a2_0_3_.INIT = 8'h84; + LUT3 plm_des0_lfsrs_reg_lfsr_two_12_iv_0_0_a2_0_3_ ( + .I0(G_329_346), + .I1(plm_des0_reg_lfsr_two_12_iv_0_0_a4_1[9]), + .I2(plm_des0_two_adv2_1_6__532), + .O(plm_des0_reg_lfsr_two_12_iv_0_0_a2_0_3_) + ); + defparam plm_des0_lfsrs_reg_lfsr_two_12_iv_i_0_a2_0_4_.INIT = 8'h48; + LUT3 plm_des0_lfsrs_reg_lfsr_two_12_iv_i_0_a2_0_4_ ( + .I0(N_35130_i_0), + .I1(plm_des0_reg_lfsr_two_12_iv_0_0_a4_1[9]), + .I2(plm_des0_two_adv2_1_4__533), + .O(plm_des0_reg_lfsr_two_12_iv_i_0_a2_0_4_) + ); + defparam plm_des0_lfsrs_reg_lfsr_one_12_iv_i_0_a2_0_7_.INIT = 4'h8; + LUT2_L plm_des0_lfsrs_reg_lfsr_one_12_iv_i_0_a2_0_7_ ( + .I0(plm_des0_reg_lfsr_two_12_iv_0_0_a4_1[9]), + .I1(plm_des0_one_adv2[7]), + .LO(plm_des0_reg_lfsr_one_12_iv_i_0_a2_0_7_) + ); + defparam plm_des0_lfsrs_reg_lfsr_one_12_iv_i_0_a2_0_6_.INIT = 4'h8; + LUT2_L plm_des0_lfsrs_reg_lfsr_one_12_iv_i_0_a2_0_6_ ( + .I0(plm_des0_reg_lfsr_two_12_iv_0_0_a4_1[9]), + .I1(plm_des0_one_adv2[6]), + .LO(plm_des0_reg_lfsr_one_12_iv_i_0_a2_0_6_) + ); + defparam plm_des0_lfsrs_reg_lfsr_one_12_iv_i_0_a2_0_5_.INIT = 4'h8; + LUT2_L plm_des0_lfsrs_reg_lfsr_one_12_iv_i_0_a2_0_5_ ( + .I0(plm_des0_reg_lfsr_two_12_iv_0_0_a4_1[9]), + .I1(plm_des0_one_adv2[5]), + .LO(plm_des0_reg_lfsr_one_12_iv_i_0_a2_0_5_) + ); + defparam plm_des0_descram_reg_rx_des_dat_14_0_am_7_.INIT = 8'h65; + LUT3 plm_des0_descram_reg_rx_des_dat_14_0_am_7_ ( + .I0(plm_des0_reg_dat[7]), + .I1(plm_des0_reg_lfsr_one_8__542), + .I2(plm_des0_reg_skp[1]), + .O(plm_des0_reg_rx_des_dat_14_0_am[7]) + ); + defparam plm_des0_descram_reg_rx_des_dat_14_0_bm_7_.INIT = 8'h6C; + LUT3 plm_des0_descram_reg_rx_des_dat_14_0_bm_7_ ( + .I0(plm_des0_m1_0_a2_0_a3_0_a2), + .I1(plm_des0_reg_dat[7]), + .I2(plm_des0_reg_lfsr_two_8__552), + .O(plm_des0_reg_rx_des_dat_14_0_bm[7]) + ); + MUXF5 plm_des0_descram_reg_rx_des_dat_14_0_7_ ( + .I0(plm_des0_reg_rx_des_dat_14_0_am[7]), + .I1(plm_des0_reg_rx_des_dat_14_0_bm[7]), + .O(plm_des0_reg_rx_des_dat_14[7]), + .S(plm_des0_N_68296_i) + ); + defparam plm_des0_descram_reg_rx_des_dat_14_0_am_6_.INIT = 8'h65; + LUT3 plm_des0_descram_reg_rx_des_dat_14_0_am_6_ ( + .I0(plm_des0_reg_dat[6]), + .I1(plm_des0_reg_lfsr_one_9__541), + .I2(plm_des0_reg_skp[1]), + .O(plm_des0_reg_rx_des_dat_14_0_am[6]) + ); + defparam plm_des0_descram_reg_rx_des_dat_14_0_bm_6_.INIT = 8'h6C; + LUT3 plm_des0_descram_reg_rx_des_dat_14_0_bm_6_ ( + .I0(plm_des0_m1_0_a2_0_a3_0_a2), + .I1(plm_des0_reg_dat[6]), + .I2(plm_des0_reg_lfsr_two_9__551), + .O(plm_des0_reg_rx_des_dat_14_0_bm[6]) + ); + MUXF5 plm_des0_descram_reg_rx_des_dat_14_0_6_ ( + .I0(plm_des0_reg_rx_des_dat_14_0_am[6]), + .I1(plm_des0_reg_rx_des_dat_14_0_bm[6]), + .O(plm_des0_reg_rx_des_dat_14[6]), + .S(plm_des0_N_68296_i) + ); + defparam plm_des0_descram_reg_rx_des_dat_14_0_am_5_.INIT = 8'h65; + LUT3 plm_des0_descram_reg_rx_des_dat_14_0_am_5_ ( + .I0(plm_des0_reg_dat[5]), + .I1(plm_des0_reg_lfsr_one_10__540), + .I2(plm_des0_reg_skp[1]), + .O(plm_des0_reg_rx_des_dat_14_0_am[5]) + ); + defparam plm_des0_descram_reg_rx_des_dat_14_0_bm_5_.INIT = 8'h6C; + LUT3 plm_des0_descram_reg_rx_des_dat_14_0_bm_5_ ( + .I0(plm_des0_m1_0_a2_0_a3_0_a2), + .I1(plm_des0_reg_dat[5]), + .I2(plm_des0_reg_lfsr_two_10__550), + .O(plm_des0_reg_rx_des_dat_14_0_bm[5]) + ); + MUXF5 plm_des0_descram_reg_rx_des_dat_14_0_5_ ( + .I0(plm_des0_reg_rx_des_dat_14_0_am[5]), + .I1(plm_des0_reg_rx_des_dat_14_0_bm[5]), + .O(plm_des0_reg_rx_des_dat_14[5]), + .S(plm_des0_N_68296_i) + ); + defparam plm_des0_descram_reg_rx_des_dat_14_0_am_4_.INIT = 8'h65; + LUT3 plm_des0_descram_reg_rx_des_dat_14_0_am_4_ ( + .I0(plm_des0_reg_dat[4]), + .I1(plm_des0_reg_lfsr_one_11__374), + .I2(plm_des0_reg_skp[1]), + .O(plm_des0_reg_rx_des_dat_14_0_am[4]) + ); + defparam plm_des0_descram_reg_rx_des_dat_14_0_bm_4_.INIT = 8'h6C; + LUT3 plm_des0_descram_reg_rx_des_dat_14_0_bm_4_ ( + .I0(plm_des0_m1_0_a2_0_a3_0_a2), + .I1(plm_des0_reg_dat[4]), + .I2(plm_des0_reg_lfsr_two_11__343), + .O(plm_des0_reg_rx_des_dat_14_0_bm[4]) + ); + MUXF5 plm_des0_descram_reg_rx_des_dat_14_0_4_ ( + .I0(plm_des0_reg_rx_des_dat_14_0_am[4]), + .I1(plm_des0_reg_rx_des_dat_14_0_bm[4]), + .O(plm_des0_reg_rx_des_dat_14[4]), + .S(plm_des0_N_68296_i) + ); + defparam plm_des0_descram_reg_rx_des_dat_14_0_am_3_.INIT = 8'h65; + LUT3 plm_des0_descram_reg_rx_des_dat_14_0_am_3_ ( + .I0(plm_des0_reg_dat[3]), + .I1(plm_des0_reg_lfsr_one_12__365), + .I2(plm_des0_reg_skp[1]), + .O(plm_des0_reg_rx_des_dat_14_0_am[3]) + ); + defparam plm_des0_descram_reg_rx_des_dat_14_0_bm_3_.INIT = 8'h6C; + LUT3 plm_des0_descram_reg_rx_des_dat_14_0_bm_3_ ( + .I0(plm_des0_m1_0_a2_0_a3_0_a2), + .I1(plm_des0_reg_dat[3]), + .I2(plm_des0_reg_lfsr_two_12__549), + .O(plm_des0_reg_rx_des_dat_14_0_bm[3]) + ); + MUXF5 plm_des0_descram_reg_rx_des_dat_14_0_3_ ( + .I0(plm_des0_reg_rx_des_dat_14_0_am[3]), + .I1(plm_des0_reg_rx_des_dat_14_0_bm[3]), + .O(plm_des0_reg_rx_des_dat_14[3]), + .S(plm_des0_N_68296_i) + ); + defparam plm_des0_descram_reg_rx_des_dat_14_0_am_2_.INIT = 8'h65; + LUT3 plm_des0_descram_reg_rx_des_dat_14_0_am_2_ ( + .I0(plm_des0_reg_dat[2]), + .I1(plm_des0_reg_lfsr_one_13__337), + .I2(plm_des0_reg_skp[1]), + .O(plm_des0_reg_rx_des_dat_14_0_am[2]) + ); + defparam plm_des0_descram_reg_rx_des_dat_14_0_bm_2_.INIT = 8'h6C; + LUT3 plm_des0_descram_reg_rx_des_dat_14_0_bm_2_ ( + .I0(plm_des0_m1_0_a2_0_a3_0_a2), + .I1(plm_des0_reg_dat[2]), + .I2(plm_des0_reg_lfsr_two_13__344), + .O(plm_des0_reg_rx_des_dat_14_0_bm[2]) + ); + MUXF5 plm_des0_descram_reg_rx_des_dat_14_0_2_ ( + .I0(plm_des0_reg_rx_des_dat_14_0_am[2]), + .I1(plm_des0_reg_rx_des_dat_14_0_bm[2]), + .O(plm_des0_reg_rx_des_dat_14[2]), + .S(plm_des0_N_68296_i) + ); + defparam plm_des0_descram_reg_rx_des_dat_14_0_am_1_.INIT = 8'h65; + LUT3 plm_des0_descram_reg_rx_des_dat_14_0_am_1_ ( + .I0(plm_des0_reg_dat[1]), + .I1(plm_des0_reg_lfsr_one_14__377), + .I2(plm_des0_reg_skp[1]), + .O(plm_des0_reg_rx_des_dat_14_0_am[1]) + ); + defparam plm_des0_descram_reg_rx_des_dat_14_0_bm_1_.INIT = 8'h6C; + LUT3 plm_des0_descram_reg_rx_des_dat_14_0_bm_1_ ( + .I0(plm_des0_m1_0_a2_0_a3_0_a2), + .I1(plm_des0_reg_dat[1]), + .I2(plm_des0_reg_lfsr_two_14__548), + .O(plm_des0_reg_rx_des_dat_14_0_bm[1]) + ); + MUXF5 plm_des0_descram_reg_rx_des_dat_14_0_1_ ( + .I0(plm_des0_reg_rx_des_dat_14_0_am[1]), + .I1(plm_des0_reg_rx_des_dat_14_0_bm[1]), + .O(plm_des0_reg_rx_des_dat_14[1]), + .S(plm_des0_N_68296_i) + ); + defparam plm_des0_descram_reg_rx_des_dat_14_0_am_0_.INIT = 8'h65; + LUT3 plm_des0_descram_reg_rx_des_dat_14_0_am_0_ ( + .I0(plm_des0_reg_dat[0]), + .I1(plm_des0_reg_lfsr_one_15__334), + .I2(plm_des0_reg_skp[1]), + .O(plm_des0_reg_rx_des_dat_14_0_am[0]) + ); + defparam plm_des0_descram_reg_rx_des_dat_14_0_bm_0_.INIT = 8'h6C; + LUT3 plm_des0_descram_reg_rx_des_dat_14_0_bm_0_ ( + .I0(plm_des0_m1_0_a2_0_a3_0_a2), + .I1(plm_des0_reg_dat[0]), + .I2(plm_des0_reg_lfsr_two_15__345), + .O(plm_des0_reg_rx_des_dat_14_0_bm[0]) + ); + MUXF5 plm_des0_descram_reg_rx_des_dat_14_0_0_ ( + .I0(plm_des0_reg_rx_des_dat_14_0_am[0]), + .I1(plm_des0_reg_rx_des_dat_14_0_bm[0]), + .O(plm_des0_reg_rx_des_dat_14[0]), + .S(plm_des0_N_68296_i) + ); + defparam plm_des0_one_adv2_3_.INIT = 8'h96; + LUT3 plm_des0_one_adv2_3_ ( + .I0(G_326_338), + .I1(G_377_366), + .I2(plm_des0_reg_lfsr_one_14__377), + .O(plm_des0_one_adv2[3]) + ); + defparam plm_des0_input_decoder_reg_bad_3_i_2_1_.INIT = 16'h080A; + LUT4_L plm_des0_input_decoder_reg_bad_3_i_2_1_ ( + .I0(plm_des0_reg_bad_3_i_1[1]), + .I1(plm_des0_reg_data[12]), + .I2(plm_des0_reg_nitbl[1]), + .I3(plm_des0_reg_spesh[1]), + .LO(plm_des0_reg_bad_3_i_2[1]) + ); + defparam plm_des0_input_decoder_reg_bad_4_i_2_0_.INIT = 16'h080A; + LUT4_L plm_des0_input_decoder_reg_bad_4_i_2_0_ ( + .I0(plm_des0_reg_bad_4_i_1[0]), + .I1(plm_des0_reg_data[4]), + .I2(plm_des0_reg_nitbl[0]), + .I3(plm_des0_reg_spesh[0]), + .LO(plm_des0_reg_bad_4_i_2[0]) + ); + defparam plm_des0_input_decoder_reg_edb_4_0_a7_0_.INIT = 16'h0800; + LUT4_L plm_des0_input_decoder_reg_edb_4_0_a7_0_ ( + .I0(plm_des0_reg_edg_4_0_a7_1_0_0[0]), + .I1(plm_des0_reg_idl_4_1[0]), + .I2(plm_des0_reg_data[0]), + .I3(plm_des0_reg_data[1]), + .LO(plm_des0_reg_edb_4[0]) + ); + defparam plm_des0_input_decoder_reg_com_3_0_a7_1_.INIT = 16'h0800; + LUT4_L plm_des0_input_decoder_reg_com_3_0_a7_1_ ( + .I0(plm_des0_reg_idl_3_1[1]), + .I1(plm_des0_reg_idl_3_2[1]), + .I2(plm_des0_reg_data[14]), + .I3(plm_des0_reg_data[15]), + .LO(plm_des0_reg_com_3[1]) + ); + defparam plm_des0_input_decoder_reg_com_4_0_a7_0_.INIT = 16'h0800; + LUT4_L plm_des0_input_decoder_reg_com_4_0_a7_0_ ( + .I0(plm_des0_reg_idl_4_1[0]), + .I1(plm_des0_reg_idl_4_2[0]), + .I2(plm_des0_reg_data[6]), + .I3(plm_des0_reg_data[7]), + .LO(plm_des0_reg_com_4[0]) + ); + defparam plm_des0_input_decoder_N_67774_i.INIT = 16'h7F0F; + LUT4_L plm_des0_input_decoder_N_67774_i ( + .I0(plm_des0_N_11969_i), + .I1(plm_des0_N_11970_i), + .I2(plm_des0_reg_bad_3_i_2[1]), + .I3(plm_des0_reg_spesh[1]), + .LO(plm_des0_N_67774_i) + ); + defparam plm_des0_input_decoder_N_67773_i.INIT = 16'h7F0F; + LUT4_L plm_des0_input_decoder_N_67773_i ( + .I0(plm_des0_N_12016_i), + .I1(plm_des0_N_12017_i), + .I2(plm_des0_reg_bad_4_i_2[0]), + .I3(plm_des0_reg_spesh[0]), + .LO(plm_des0_N_67773_i) + ); + defparam plm_des0_descram_N_35147_i_0_i.INIT = 8'h6C; + LUT3_L plm_des0_descram_N_35147_i_0_i ( + .I0(plm_des0_N_35107_i), + .I1(plm_des0_reg_dat[15]), + .I2(plm_des0_reg_lfsr_one_8__542), + .LO(plm_des0_N_35147_i_0_i) + ); + defparam plm_des0_descram_N_35145_i_0_i.INIT = 8'h6C; + LUT3_L plm_des0_descram_N_35145_i_0_i ( + .I0(plm_des0_N_35107_i), + .I1(plm_des0_reg_dat[14]), + .I2(plm_des0_reg_lfsr_one_9__541), + .LO(plm_des0_N_35145_i_0_i) + ); + defparam plm_des0_descram_N_35143_i_0_i.INIT = 8'h6C; + LUT3_L plm_des0_descram_N_35143_i_0_i ( + .I0(plm_des0_N_35107_i), + .I1(plm_des0_reg_dat[13]), + .I2(plm_des0_reg_lfsr_one_10__540), + .LO(plm_des0_N_35143_i_0_i) + ); + defparam plm_des0_descram_N_35141_i_0_i.INIT = 8'h6C; + LUT3_L plm_des0_descram_N_35141_i_0_i ( + .I0(plm_des0_N_35107_i), + .I1(plm_des0_reg_dat[12]), + .I2(plm_des0_reg_lfsr_one_11__374), + .LO(plm_des0_N_35141_i_0_i) + ); + defparam plm_des0_descram_N_35139_i_0_i.INIT = 8'h6C; + LUT3_L plm_des0_descram_N_35139_i_0_i ( + .I0(plm_des0_N_35107_i), + .I1(plm_des0_reg_dat[11]), + .I2(plm_des0_reg_lfsr_one_12__365), + .LO(plm_des0_N_35139_i_0_i) + ); + defparam plm_des0_descram_N_35137_i_0_i.INIT = 8'h6C; + LUT3_L plm_des0_descram_N_35137_i_0_i ( + .I0(plm_des0_N_35107_i), + .I1(plm_des0_reg_dat[10]), + .I2(plm_des0_reg_lfsr_one_13__337), + .LO(plm_des0_N_35137_i_0_i) + ); + defparam plm_des0_descram_N_35135_i_0_i.INIT = 8'h6C; + LUT3_L plm_des0_descram_N_35135_i_0_i ( + .I0(plm_des0_N_35107_i), + .I1(plm_des0_reg_dat[9]), + .I2(plm_des0_reg_lfsr_one_14__377), + .LO(plm_des0_N_35135_i_0_i) + ); + defparam plm_des0_descram_N_35133_i_0_i.INIT = 8'h6C; + LUT3_L plm_des0_descram_N_35133_i_0_i ( + .I0(plm_des0_N_35107_i), + .I1(plm_des0_reg_dat[8]), + .I2(plm_des0_reg_lfsr_one_15__334), + .LO(plm_des0_N_35133_i_0_i) + ); + defparam plm_des0_input_decoder_reg_stp_3_0_a7_1_.INIT = 16'h0800; + LUT4_L plm_des0_input_decoder_reg_stp_3_0_a7_1_ ( + .I0(plm_des0_reg_idl_3_1[1]), + .I1(plm_des0_reg_stp_3_0_a7_1_0_0[1]), + .I2(plm_des0_reg_data[10]), + .I3(plm_des0_reg_data[11]), + .LO(plm_des0_reg_stp_3[1]) + ); + defparam plm_des0_input_decoder_reg_stp_4_0_a7_0_.INIT = 16'h0800; + LUT4_L plm_des0_input_decoder_reg_stp_4_0_a7_0_ ( + .I0(plm_des0_reg_idl_4_1[0]), + .I1(plm_des0_reg_pad_4_0_a7_1_0_0[0]), + .I2(plm_des0_reg_data[2]), + .I3(plm_des0_reg_data[3]), + .LO(plm_des0_reg_stp_4[0]) + ); + defparam plm_des0_input_decoder_reg_skp_3_0_a7_1_.INIT = 16'h0008; + LUT4_L plm_des0_input_decoder_reg_skp_3_0_a7_1_ ( + .I0(plm_des0_reg_idl_3_2[1]), + .I1(plm_des0_reg_skp_3_0_a7_1_0[1]), + .I2(plm_des0_reg_data[14]), + .I3(plm_des0_reg_data[15]), + .LO(plm_des0_reg_skp_3[1]) + ); + defparam plm_des0_input_decoder_reg_skp_4_0_a7_0_.INIT = 16'h0008; + LUT4_L plm_des0_input_decoder_reg_skp_4_0_a7_0_ ( + .I0(plm_des0_reg_idl_4_2[0]), + .I1(plm_des0_reg_sdp_4_0_a7_1_0_0[0]), + .I2(plm_des0_reg_data[6]), + .I3(plm_des0_reg_data[7]), + .LO(plm_des0_reg_skp_4[0]) + ); + defparam plm_des0_input_decoder_reg_sdp_3_0_a7_1_.INIT = 16'h0080; + LUT4_L plm_des0_input_decoder_reg_sdp_3_0_a7_1_ ( + .I0(plm_des0_reg_idl_3_2[1]), + .I1(plm_des0_reg_skp_3_0_a7_1_0[1]), + .I2(plm_des0_reg_data[14]), + .I3(plm_des0_reg_data[15]), + .LO(plm_des0_reg_sdp_3[1]) + ); + defparam plm_des0_input_decoder_reg_sdp_4_0_a7_0_.INIT = 16'h0080; + LUT4_L plm_des0_input_decoder_reg_sdp_4_0_a7_0_ ( + .I0(plm_des0_reg_idl_4_2[0]), + .I1(plm_des0_reg_sdp_4_0_a7_1_0_0[0]), + .I2(plm_des0_reg_data[6]), + .I3(plm_des0_reg_data[7]), + .LO(plm_des0_reg_sdp_4[0]) + ); + defparam plm_des0_input_decoder_reg_pad_3_0_a7_1_.INIT = 16'h0080; + LUT4_L plm_des0_input_decoder_reg_pad_3_0_a7_1_ ( + .I0(plm_des0_reg_idl_3_1[1]), + .I1(plm_des0_reg_stp_3_0_a7_1_0_0[1]), + .I2(plm_des0_reg_data[10]), + .I3(plm_des0_reg_data[11]), + .LO(plm_des0_reg_pad_3[1]) + ); + defparam plm_des0_input_decoder_reg_pad_4_0_a7_0_.INIT = 16'h0080; + LUT4_L plm_des0_input_decoder_reg_pad_4_0_a7_0_ ( + .I0(plm_des0_reg_idl_4_1[0]), + .I1(plm_des0_reg_pad_4_0_a7_1_0_0[0]), + .I2(plm_des0_reg_data[2]), + .I3(plm_des0_reg_data[3]), + .LO(plm_des0_reg_pad_4[0]) + ); + defparam plm_des0_input_decoder_reg_idl_3_0_a7_1_.INIT = 16'h0080; + LUT4_L plm_des0_input_decoder_reg_idl_3_0_a7_1_ ( + .I0(plm_des0_reg_idl_3_1[1]), + .I1(plm_des0_reg_idl_3_2[1]), + .I2(plm_des0_reg_data[14]), + .I3(plm_des0_reg_data[15]), + .LO(plm_des0_reg_idl_3[1]) + ); + defparam plm_des0_input_decoder_reg_idl_4_0_a7_0_.INIT = 16'h0080; + LUT4_L plm_des0_input_decoder_reg_idl_4_0_a7_0_ ( + .I0(plm_des0_reg_idl_4_1[0]), + .I1(plm_des0_reg_idl_4_2[0]), + .I2(plm_des0_reg_data[6]), + .I3(plm_des0_reg_data[7]), + .LO(plm_des0_reg_idl_4[0]) + ); + defparam plm_des0_input_decoder_reg_fts_3_0_a7_1_.INIT = 16'h0008; + LUT4_L plm_des0_input_decoder_reg_fts_3_0_a7_1_ ( + .I0(plm_des0_reg_idl_3_1[1]), + .I1(plm_des0_reg_idl_3_2[1]), + .I2(plm_des0_reg_data[14]), + .I3(plm_des0_reg_data[15]), + .LO(plm_des0_reg_fts_3[1]) + ); + defparam plm_des0_input_decoder_reg_fts_4_0_a7_0_.INIT = 16'h0008; + LUT4_L plm_des0_input_decoder_reg_fts_4_0_a7_0_ ( + .I0(plm_des0_reg_idl_4_1[0]), + .I1(plm_des0_reg_idl_4_2[0]), + .I2(plm_des0_reg_data[6]), + .I3(plm_des0_reg_data[7]), + .LO(plm_des0_reg_fts_4[0]) + ); + defparam plm_des0_input_decoder_reg_edg_3_0_a7_1_.INIT = 16'h0080; + LUT4_L plm_des0_input_decoder_reg_edg_3_0_a7_1_ ( + .I0(plm_des0_reg_edg_3_0_a7_1_0_0[1]), + .I1(plm_des0_reg_idl_3_1[1]), + .I2(plm_des0_reg_data[8]), + .I3(plm_des0_reg_data[9]), + .LO(plm_des0_reg_edg_3[1]) + ); + defparam plm_des0_input_decoder_reg_edg_4_0_a7_0_.INIT = 16'h0080; + LUT4_L plm_des0_input_decoder_reg_edg_4_0_a7_0_ ( + .I0(plm_des0_reg_edg_4_0_a7_1_0_0[0]), + .I1(plm_des0_reg_idl_4_1[0]), + .I2(plm_des0_reg_data[0]), + .I3(plm_des0_reg_data[1]), + .LO(plm_des0_reg_edg_4[0]) + ); + defparam plm_des0_input_decoder_reg_edb_3_0_a7_1_.INIT = 16'h0800; + LUT4_L plm_des0_input_decoder_reg_edb_3_0_a7_1_ ( + .I0(plm_des0_reg_edg_3_0_a7_1_0_0[1]), + .I1(plm_des0_reg_idl_3_1[1]), + .I2(plm_des0_reg_data[8]), + .I3(plm_des0_reg_data[9]), + .LO(plm_des0_reg_edb_3[1]) + ); + defparam plm_des0_input_decoder_reg_t2p_3_0_a7_1_.INIT = 8'h80; + LUT3_L plm_des0_input_decoder_reg_t2p_3_0_a7_1_ ( + .I0(plm_des0_reg_sym_3[1]), + .I1(plm_des0_reg_t2p_3_0_a7_2_0[1]), + .I2(plm_des0_reg_t2p_3_1_0[1]), + .LO(plm_des0_reg_t2p_3[1]) + ); + defparam plm_des0_input_decoder_reg_t2p_4_0_a7_0_.INIT = 8'h80; + LUT3_L plm_des0_input_decoder_reg_t2p_4_0_a7_0_ ( + .I0(plm_des0_reg_sym_4[0]), + .I1(plm_des0_reg_t1n_4_0_a7_2_0[0]), + .I2(plm_des0_reg_t1p_4_1[0]), + .LO(plm_reg_t2p_4[0]) + ); + defparam plm_des0_input_decoder_reg_t2n_3_0_a7_1_.INIT = 8'h80; + LUT3_L plm_des0_input_decoder_reg_t2n_3_0_a7_1_ ( + .I0(plm_des0_reg_sym_3[1]), + .I1(plm_des0_reg_t2n_3_0_a7_2_0[1]), + .I2(plm_des0_reg_t2n_3_1_0[1]), + .LO(plm_des0_reg_t2n_3[1]) + ); + defparam plm_des0_input_decoder_reg_t2n_4_0_a7_0_.INIT = 8'h80; + LUT3_L plm_des0_input_decoder_reg_t2n_4_0_a7_0_ ( + .I0(plm_des0_reg_sym_4[0]), + .I1(plm_des0_reg_t1n_4_1[0]), + .I2(plm_des0_reg_t1p_4_0_a7_2_0[0]), + .LO(plm_reg_t2n_4[0]) + ); + defparam plm_des0_input_decoder_reg_t1p_3_0_a7_1_.INIT = 8'h80; + LUT3_L plm_des0_input_decoder_reg_t1p_3_0_a7_1_ ( + .I0(plm_des0_reg_sym_3[1]), + .I1(plm_des0_reg_t2n_3_0_a7_2_0[1]), + .I2(plm_des0_reg_t2p_3_1_0[1]), + .LO(plm_des0_reg_t1p_3[1]) + ); + defparam plm_des0_input_decoder_reg_t1p_4_0_a7_0_.INIT = 8'h80; + LUT3_L plm_des0_input_decoder_reg_t1p_4_0_a7_0_ ( + .I0(plm_des0_reg_sym_4[0]), + .I1(plm_des0_reg_t1p_4_0_a7_2_0[0]), + .I2(plm_des0_reg_t1p_4_1[0]), + .LO(plm_reg_t1p_4[0]) + ); + defparam plm_des0_input_decoder_reg_t1n_3_0_a7_1_.INIT = 8'h80; + LUT3_L plm_des0_input_decoder_reg_t1n_3_0_a7_1_ ( + .I0(plm_des0_reg_sym_3[1]), + .I1(plm_des0_reg_t2n_3_1_0[1]), + .I2(plm_des0_reg_t2p_3_0_a7_2_0[1]), + .LO(plm_des0_reg_t1n_3[1]) + ); + defparam plm_des0_input_decoder_reg_t1n_4_0_a7_0_.INIT = 8'h80; + LUT3_L plm_des0_input_decoder_reg_t1n_4_0_a7_0_ ( + .I0(plm_des0_reg_sym_4[0]), + .I1(plm_des0_reg_t1n_4_0_a7_2_0[0]), + .I2(plm_des0_reg_t1n_4_1[0]), + .LO(plm_reg_t1n_4[0]) + ); + defparam plm_des0_lfsrs_N_69382_i.INIT = 16'hF7B3; + LUT4_L plm_des0_lfsrs_N_69382_i ( + .I0(plm_des0_N_35105_i), + .I1(plm_des0_reg_lfsr_two_12_0_iv_0_o2[12]), + .I2(plm_des0_one_adv2[15]), + .I3(plm_des0_reg_lfsr_two_15__345), + .LO(plm_des0_N_69382_i) + ); + defparam plm_des0_lfsrs_N_69381_i.INIT = 16'hF7B3; + LUT4_L plm_des0_lfsrs_N_69381_i ( + .I0(plm_des0_N_35105_i), + .I1(plm_des0_reg_lfsr_two_12_0_iv_0_o2[12]), + .I2(plm_des0_one_adv2[14]), + .I3(plm_des0_reg_lfsr_two_14__548), + .LO(plm_des0_N_69381_i) + ); + defparam plm_des0_lfsrs_N_69380_i.INIT = 16'hF7B3; + LUT4_L plm_des0_lfsrs_N_69380_i ( + .I0(plm_des0_N_35105_i), + .I1(plm_des0_reg_lfsr_two_12_0_iv_0_o2[12]), + .I2(plm_des0_one_adv2[13]), + .I3(plm_des0_reg_lfsr_two_13__344), + .LO(plm_des0_N_69380_i) + ); + defparam plm_des0_lfsrs_N_67782_i.INIT = 16'hDFDD; + LUT4_L plm_des0_lfsrs_N_67782_i ( + .I0(plm_des0_N_35106_i), + .I1(plm_des0_reg_lfsr_one_12_iv_i_0_a2_0_12_), + .I2(plm_des0_reg_lfsr_two_12_iv_0_0_o4[9]), + .I3(plm_des0_reg_lfsr_two_12__549), + .LO(plm_des0_N_67782_i) + ); + defparam plm_des0_lfsrs_N_69379_i.INIT = 16'hF7B3; + LUT4_L plm_des0_lfsrs_N_69379_i ( + .I0(plm_des0_N_35105_i), + .I1(plm_des0_reg_lfsr_two_12_0_iv_0_o2[12]), + .I2(plm_des0_one_adv2[11]), + .I3(plm_des0_reg_lfsr_two_11__343), + .LO(plm_des0_N_69379_i) + ); + defparam plm_des0_lfsrs_N_67781_i.INIT = 16'hDFDD; + LUT4_L plm_des0_lfsrs_N_67781_i ( + .I0(plm_des0_N_35106_i), + .I1(plm_des0_reg_lfsr_one_12_iv_i_0_a2_0_10_), + .I2(plm_des0_reg_lfsr_two_12_iv_0_0_o4[9]), + .I3(plm_des0_reg_lfsr_two_10__550), + .LO(plm_des0_N_67781_i) + ); + defparam plm_des0_lfsrs_N_67780_i.INIT = 16'hFDDD; + LUT4_L plm_des0_lfsrs_N_67780_i ( + .I0(plm_des0_N_35106_i), + .I1(plm_des0_reg_lfsr_one_12_iv_i_0_a2_9_), + .I2(plm_des0_reg_lfsr_two_12_iv_0_0_a4_1[9]), + .I3(plm_des0_one_adv2[9]), + .LO(plm_des0_N_67780_i) + ); + defparam plm_des0_lfsrs_N_67779_i.INIT = 16'hFDDD; + LUT4_L plm_des0_lfsrs_N_67779_i ( + .I0(plm_des0_N_35106_i), + .I1(plm_des0_reg_lfsr_one_12_iv_i_0_a2_8_), + .I2(plm_des0_reg_lfsr_two_12_iv_0_0_a4_1[9]), + .I3(plm_des0_one_adv2[8]), + .LO(plm_des0_N_67779_i) + ); + defparam plm_des0_lfsrs_N_67778_i.INIT = 16'hDFDD; + LUT4_L plm_des0_lfsrs_N_67778_i ( + .I0(plm_des0_N_35106_i), + .I1(plm_des0_reg_lfsr_one_12_iv_i_0_a2_0_7_), + .I2(plm_des0_reg_lfsr_two_12_iv_0_0_o4[9]), + .I3(plm_des0_reg_lfsr_two_7__553), + .LO(plm_des0_N_67778_i) + ); + defparam plm_des0_lfsrs_N_67777_i.INIT = 16'hDFDD; + LUT4_L plm_des0_lfsrs_N_67777_i ( + .I0(plm_des0_N_35106_i), + .I1(plm_des0_reg_lfsr_one_12_iv_i_0_a2_0_6_), + .I2(plm_des0_reg_lfsr_two_12_iv_0_0_o4[9]), + .I3(plm_des0_reg_lfsr_two_6__554), + .LO(plm_des0_N_67777_i) + ); + defparam plm_des0_lfsrs_N_67776_i.INIT = 16'hDFDD; + LUT4_L plm_des0_lfsrs_N_67776_i ( + .I0(plm_des0_N_35106_i), + .I1(plm_des0_reg_lfsr_one_12_iv_i_0_a2_0_5_), + .I2(plm_des0_reg_lfsr_two_12_iv_0_0_o4[9]), + .I3(plm_des0_reg_lfsr_two_5__555), + .LO(plm_des0_N_67776_i) + ); + defparam plm_des0_lfsrs_N_69378_i.INIT = 16'hF7B3; + LUT4_L plm_des0_lfsrs_N_69378_i ( + .I0(plm_des0_N_35105_i), + .I1(plm_des0_reg_lfsr_two_12_0_iv_0_o2[12]), + .I2(plm_des0_one_adv2[4]), + .I3(plm_des0_reg_lfsr_two_4__378), + .LO(plm_des0_N_69378_i) + ); + defparam plm_des0_lfsrs_N_67775_i.INIT = 16'hFDDD; + LUT4_L plm_des0_lfsrs_N_67775_i ( + .I0(plm_des0_N_35106_i), + .I1(plm_des0_reg_lfsr_one_12_iv_i_0_a2_3_), + .I2(plm_des0_reg_lfsr_two_12_iv_0_0_a4_1[9]), + .I3(plm_des0_one_adv2[3]), + .LO(plm_des0_N_67775_i) + ); + defparam plm_des0_lfsrs_N_69377_i.INIT = 16'hF7B3; + LUT4_L plm_des0_lfsrs_N_69377_i ( + .I0(plm_des0_N_35105_i), + .I1(plm_des0_reg_lfsr_two_12_0_iv_0_o2[12]), + .I2(plm_des0_one_adv2[2]), + .I3(plm_des0_reg_lfsr_two_2__380), + .LO(plm_des0_N_69377_i) + ); + defparam plm_des0_lfsrs_N_69376_i.INIT = 16'hF7B3; + LUT4_L plm_des0_lfsrs_N_69376_i ( + .I0(plm_des0_N_35105_i), + .I1(plm_des0_reg_lfsr_two_12_0_iv_0_o2[12]), + .I2(plm_des0_one_adv2[1]), + .I3(plm_des0_reg_lfsr_two_1__379), + .LO(plm_des0_N_69376_i) + ); + defparam plm_des0_lfsrs_N_69375_i.INIT = 16'hDF8F; + LUT4_L plm_des0_lfsrs_N_69375_i ( + .I0(plm_des0_N_35105_i), + .I1(plm_des0_N_35110_i_0), + .I2(plm_des0_reg_lfsr_two_12_0_iv_0_o2[12]), + .I3(plm_des0_reg_lfsr_two_0__342), + .LO(plm_des0_N_69375_i) + ); + defparam plm_des0_lfsrs_N_67790_i.INIT = 16'hFDDD; + LUT4_L plm_des0_lfsrs_N_67790_i ( + .I0(plm_des0_N_35106_i), + .I1(plm_des0_reg_lfsr_two_12_iv_i_0_a2[15]), + .I2(plm_des0_reg_lfsr_two_12_iv_0_0_a4_1[9]), + .I3(plm_des0_two_adv2_15__534), + .LO(plm_des0_N_67790_i) + ); + defparam plm_des0_lfsrs_N_67789_i.INIT = 16'hDFDD; + LUT4_L plm_des0_lfsrs_N_67789_i ( + .I0(plm_des0_N_35106_i), + .I1(plm_des0_reg_lfsr_two_12_iv_i_0_a2_0_14_), + .I2(plm_des0_reg_lfsr_two_12_iv_0_0_o4[9]), + .I3(plm_des0_one_adv2[14]), + .LO(plm_des0_N_67789_i) + ); + defparam plm_des0_lfsrs_N_67788_i.INIT = 16'hDFDD; + LUT4_L plm_des0_lfsrs_N_67788_i ( + .I0(plm_des0_N_35106_i), + .I1(plm_des0_reg_lfsr_two_12_iv_i_0_a2_0_13_), + .I2(plm_des0_reg_lfsr_two_12_iv_0_0_o4[9]), + .I3(plm_des0_one_adv2[13]), + .LO(plm_des0_N_67788_i) + ); + defparam plm_des0_lfsrs_reg_lfsr_two_12_0_iv_0_12_.INIT = 16'hC840; + LUT4_L plm_des0_lfsrs_reg_lfsr_two_12_0_iv_0_12_ ( + .I0(plm_des0_N_35105_i), + .I1(plm_des0_reg_lfsr_two_12_0_iv_0_o2[12]), + .I2(plm_des0_one_adv2[12]), + .I3(plm_des0_two_adv2_12__535), + .LO(plm_des0_N_8718_i) + ); + defparam plm_des0_lfsrs_N_67787_i.INIT = 16'hDFDD; + LUT4_L plm_des0_lfsrs_N_67787_i ( + .I0(plm_des0_N_35106_i), + .I1(plm_des0_reg_lfsr_two_12_iv_i_0_a2_0_11_), + .I2(plm_des0_reg_lfsr_two_12_iv_0_0_o4[9]), + .I3(plm_des0_one_adv2[11]), + .LO(plm_des0_N_67787_i) + ); + defparam plm_des0_lfsrs_reg_lfsr_two_12_0_iv_0_10_.INIT = 16'hC840; + LUT4_L plm_des0_lfsrs_reg_lfsr_two_12_0_iv_0_10_ ( + .I0(plm_des0_N_35105_i), + .I1(plm_des0_reg_lfsr_two_12_0_iv_0_o2[12]), + .I2(plm_des0_one_adv2[10]), + .I3(plm_des0_two_adv2_10__536), + .LO(plm_des0_N_8720_i) + ); + defparam plm_des0_lfsrs_reg_lfsr_two_12_iv_0_0_9_.INIT = 16'h2220; + LUT4_L plm_des0_lfsrs_reg_lfsr_two_12_iv_0_0_9_ ( + .I0(plm_des0_N_35106_i), + .I1(plm_des0_reg_lfsr_two_12_iv_0_0_a2_0_9_), + .I2(plm_des0_reg_lfsr_two_12_iv_0_0_o4[9]), + .I3(plm_des0_one_adv2[9]), + .LO(plm_des0_N_8721_i) + ); + defparam plm_des0_lfsrs_reg_lfsr_two_12_iv_0_0_8_.INIT = 16'h2220; + LUT4_L plm_des0_lfsrs_reg_lfsr_two_12_iv_0_0_8_ ( + .I0(plm_des0_N_35106_i), + .I1(plm_des0_reg_lfsr_two_12_iv_0_0_a2_0_8_), + .I2(plm_des0_reg_lfsr_two_12_iv_0_0_o4[9]), + .I3(plm_des0_one_adv2[8]), + .LO(plm_des0_N_8722_i) + ); + defparam plm_des0_lfsrs_reg_lfsr_two_12_0_iv_0_7_.INIT = 16'hC840; + LUT4_L plm_des0_lfsrs_reg_lfsr_two_12_0_iv_0_7_ ( + .I0(plm_des0_N_35105_i), + .I1(plm_des0_reg_lfsr_two_12_0_iv_0_o2[12]), + .I2(plm_des0_one_adv2[7]), + .I3(plm_des0_two_adv2_7__537), + .LO(plm_des0_N_8723_i) + ); + defparam plm_des0_lfsrs_reg_lfsr_two_12_0_iv_0_6_.INIT = 16'hC840; + LUT4_L plm_des0_lfsrs_reg_lfsr_two_12_0_iv_0_6_ ( + .I0(plm_des0_N_35105_i), + .I1(plm_des0_reg_lfsr_two_12_0_iv_0_o2[12]), + .I2(plm_des0_one_adv2[6]), + .I3(plm_des0_two_adv2_6__538), + .LO(plm_des0_N_8724_i) + ); + defparam plm_des0_lfsrs_reg_lfsr_two_12_iv_0_0_5_.INIT = 16'h2220; + LUT4_L plm_des0_lfsrs_reg_lfsr_two_12_iv_0_0_5_ ( + .I0(plm_des0_N_35106_i), + .I1(plm_des0_reg_lfsr_two_12_iv_0_0_a2_0_5_), + .I2(plm_des0_reg_lfsr_two_12_iv_0_0_o4[9]), + .I3(plm_des0_one_adv2[5]), + .LO(plm_des0_N_8725_i) + ); + defparam plm_des0_lfsrs_N_67786_i.INIT = 16'hDFDD; + LUT4_L plm_des0_lfsrs_N_67786_i ( + .I0(plm_des0_N_35106_i), + .I1(plm_des0_reg_lfsr_two_12_iv_i_0_a2_0_4_), + .I2(plm_des0_reg_lfsr_two_12_iv_0_0_o4[9]), + .I3(plm_des0_one_adv2[4]), + .LO(plm_des0_N_67786_i) + ); + defparam plm_des0_lfsrs_reg_lfsr_two_12_iv_0_0_3_.INIT = 16'h2220; + LUT4_L plm_des0_lfsrs_reg_lfsr_two_12_iv_0_0_3_ ( + .I0(plm_des0_N_35106_i), + .I1(plm_des0_reg_lfsr_two_12_iv_0_0_a2_0_3_), + .I2(plm_des0_reg_lfsr_two_12_iv_0_0_o4[9]), + .I3(plm_des0_one_adv2[3]), + .LO(plm_des0_N_8727_i) + ); + defparam plm_des0_lfsrs_N_67785_i.INIT = 16'hDFDD; + LUT4_L plm_des0_lfsrs_N_67785_i ( + .I0(plm_des0_N_35106_i), + .I1(plm_des0_reg_lfsr_two_12_iv_i_0_a2_0_2_), + .I2(plm_des0_reg_lfsr_two_12_iv_0_0_o4[9]), + .I3(plm_des0_one_adv2[2]), + .LO(plm_des0_N_67785_i) + ); + defparam plm_des0_lfsrs_N_67784_i.INIT = 16'hDFDD; + LUT4_L plm_des0_lfsrs_N_67784_i ( + .I0(plm_des0_N_35106_i), + .I1(plm_des0_reg_lfsr_two_12_iv_i_0_a2_0_1_), + .I2(plm_des0_reg_lfsr_two_12_iv_0_0_o4[9]), + .I3(plm_des0_one_adv2[1]), + .LO(plm_des0_N_67784_i) + ); + defparam plm_des0_lfsrs_N_67783_i.INIT = 16'hF5FD; + LUT4_L plm_des0_lfsrs_N_67783_i ( + .I0(plm_des0_N_35106_i), + .I1(plm_des0_N_35110_i_0), + .I2(plm_des0_reg_lfsr_two_12_iv_i_0_a2_0_0_), + .I3(plm_des0_reg_lfsr_two_12_iv_0_0_o4[9]), + .LO(plm_des0_N_67783_i) + ); + defparam plm_des0_lfsrs_reg_lfsr_two_12_iv_0_0_a4_1_9_.INIT = 8'h01; + LUT3 plm_des0_lfsrs_reg_lfsr_two_12_iv_0_0_a4_1_9_ ( + .I0(plm_des0_reg_com[1]), + .I1(plm_des0_reg_skp[1]), + .I2(plm_des0_reg_skp[0]), + .O(plm_des0_reg_lfsr_two_12_iv_0_0_a4_1[9]) + ); + FDC plm_des0_reg_dis ( + .C(mgt_clk), + .D(plm_reg_disdes), + .Q(plm_des0_reg_dis_539), + .CLR(plm_rst) + ); + FDC plm_des0_reg_rx_des_pad_0_ ( + .C(mgt_clk), + .D(plm_des0_reg_pad[0]), + .Q(plm_rx0_des_pad[0]), + .CLR(plm_rst) + ); + FDC plm_des0_reg_rx_des_idl_1_ ( + .C(mgt_clk), + .D(plm_des0_reg_idl[1]), + .Q(plm_rx0_des_idl[1]), + .CLR(plm_rst) + ); + FDC plm_des0_reg_rx_des_idl_0_ ( + .C(mgt_clk), + .D(plm_des0_reg_idl[0]), + .Q(plm_rx0_des_idl[0]), + .CLR(plm_rst) + ); + FDC plm_des0_reg_rx_des_fts_1_ ( + .C(mgt_clk), + .D(plm_des0_reg_fts[1]), + .Q(plm_rx0_des_fts[1]), + .CLR(plm_rst) + ); + FDC plm_des0_reg_rx_des_fts_0_ ( + .C(mgt_clk), + .D(plm_des0_reg_fts[0]), + .Q(plm_rx0_des_fts[0]), + .CLR(plm_rst) + ); + FDC plm_des0_reg_rx_des_edg_1_ ( + .C(mgt_clk), + .D(plm_des0_reg_edg[1]), + .Q(plm_rx0_des_edg[1]), + .CLR(plm_rst) + ); + FDC plm_des0_reg_rx_des_edg_0_ ( + .C(mgt_clk), + .D(plm_des0_reg_edg[0]), + .Q(plm_rx0_des_edg[0]), + .CLR(plm_rst) + ); + FDC plm_des0_reg_rx_des_edb_1_ ( + .C(mgt_clk), + .D(plm_des0_reg_edb[1]), + .Q(plm_rx0_des_edb[1]), + .CLR(plm_rst) + ); + FDC plm_des0_reg_rx_des_edb_0_ ( + .C(mgt_clk), + .D(plm_des0_reg_edb[0]), + .Q(plm_rx0_des_edb[0]), + .CLR(plm_rst) + ); + FDC plm_des0_reg_rx_des_dat_7_ ( + .C(mgt_clk), + .D(plm_des0_reg_rx_des_dat_14[7]), + .Q(plm_rx0_des_dat[7]), + .CLR(plm_rst) + ); + FDC plm_des0_reg_rx_des_dat_6_ ( + .C(mgt_clk), + .D(plm_des0_reg_rx_des_dat_14[6]), + .Q(plm_rx0_des_dat[6]), + .CLR(plm_rst) + ); + FDC plm_des0_reg_rx_des_dat_5_ ( + .C(mgt_clk), + .D(plm_des0_reg_rx_des_dat_14[5]), + .Q(plm_rx0_des_dat[5]), + .CLR(plm_rst) + ); + FDC plm_des0_reg_rx_des_dat_4_ ( + .C(mgt_clk), + .D(plm_des0_reg_rx_des_dat_14[4]), + .Q(plm_rx0_des_dat[4]), + .CLR(plm_rst) + ); + FDC plm_des0_reg_rx_des_dat_3_ ( + .C(mgt_clk), + .D(plm_des0_reg_rx_des_dat_14[3]), + .Q(plm_rx0_des_dat[3]), + .CLR(plm_rst) + ); + FDC plm_des0_reg_rx_des_dat_2_ ( + .C(mgt_clk), + .D(plm_des0_reg_rx_des_dat_14[2]), + .Q(plm_rx0_des_dat[2]), + .CLR(plm_rst) + ); + FDC plm_des0_reg_rx_des_dat_1_ ( + .C(mgt_clk), + .D(plm_des0_reg_rx_des_dat_14[1]), + .Q(plm_rx0_des_dat[1]), + .CLR(plm_rst) + ); + FDC plm_des0_reg_rx_des_dat_0_ ( + .C(mgt_clk), + .D(plm_des0_reg_rx_des_dat_14[0]), + .Q(plm_rx0_des_dat[0]), + .CLR(plm_rst) + ); + FDC plm_des0_reg_rx_des_stp_1_ ( + .C(mgt_clk), + .D(plm_des0_reg_stp[1]), + .Q(plm_rx0_des_stp[1]), + .CLR(plm_rst) + ); + FDC plm_des0_reg_rx_des_stp_0_ ( + .C(mgt_clk), + .D(plm_des0_reg_stp[0]), + .Q(plm_rx0_des_stp[0]), + .CLR(plm_rst) + ); + FDC plm_des0_reg_rx_des_skp_1_ ( + .C(mgt_clk), + .D(plm_des0_reg_skp[1]), + .Q(plm_rx0_des_skp[1]), + .CLR(plm_rst) + ); + FDC plm_des0_reg_rx_des_skp_0_ ( + .C(mgt_clk), + .D(plm_des0_reg_skp[0]), + .Q(plm_rx0_des_skp[0]), + .CLR(plm_rst) + ); + FDC plm_des0_reg_rx_des_sdp_1_ ( + .C(mgt_clk), + .D(plm_des0_reg_sdp[1]), + .Q(plm_rx0_des_sdp[1]), + .CLR(plm_rst) + ); + FDC plm_des0_reg_rx_des_sdp_0_ ( + .C(mgt_clk), + .D(plm_des0_reg_sdp[0]), + .Q(plm_rx0_des_sdp[0]), + .CLR(plm_rst) + ); + FDC plm_des0_reg_rx_des_pad_1_ ( + .C(mgt_clk), + .D(plm_des0_reg_pad[1]), + .Q(plm_rx0_des_pad[1]), + .CLR(plm_rst) + ); + FDC plm_des0_reg_edb_0_ ( + .C(mgt_clk), + .D(plm_des0_reg_edb_4[0]), + .Q(plm_des0_reg_edb[0]), + .CLR(plm_rst) + ); + FDC plm_des0_reg_com_1_ ( + .C(mgt_clk), + .D(plm_des0_reg_com_3[1]), + .Q(plm_des0_reg_com[1]), + .CLR(plm_rst) + ); + FDC plm_des0_reg_com_0_ ( + .C(mgt_clk), + .D(plm_des0_reg_com_4[0]), + .Q(plm_des0_reg_com[0]), + .CLR(plm_rst) + ); + FDC plm_des0_reg_rx_des_bad_1_ ( + .C(mgt_clk), + .D(plm_des0_reg_bad[1]), + .Q(plm_rx0_des_bad[1]), + .CLR(plm_rst) + ); + FDC plm_des0_reg_rx_des_bad_0_ ( + .C(mgt_clk), + .D(plm_des0_reg_bad[0]), + .Q(plm_rx0_des_bad[0]), + .CLR(plm_rst) + ); + FDC plm_des0_reg_bad_1_ ( + .C(mgt_clk), + .D(plm_des0_N_67774_i), + .Q(plm_des0_reg_bad[1]), + .CLR(plm_rst) + ); + FDC plm_des0_reg_bad_0_ ( + .C(mgt_clk), + .D(plm_des0_N_67773_i), + .Q(plm_des0_reg_bad[0]), + .CLR(plm_rst) + ); + FDC plm_des0_reg_rx_des_dat_15_ ( + .C(mgt_clk), + .D(plm_des0_N_35147_i_0_i), + .Q(plm_rx0_des_dat[15]), + .CLR(plm_rst) + ); + FDC plm_des0_reg_rx_des_dat_14_ ( + .C(mgt_clk), + .D(plm_des0_N_35145_i_0_i), + .Q(plm_rx0_des_dat[14]), + .CLR(plm_rst) + ); + FDC plm_des0_reg_rx_des_dat_13_ ( + .C(mgt_clk), + .D(plm_des0_N_35143_i_0_i), + .Q(plm_rx0_des_dat[13]), + .CLR(plm_rst) + ); + FDC plm_des0_reg_rx_des_dat_12_ ( + .C(mgt_clk), + .D(plm_des0_N_35141_i_0_i), + .Q(plm_rx0_des_dat[12]), + .CLR(plm_rst) + ); + FDC plm_des0_reg_rx_des_dat_11_ ( + .C(mgt_clk), + .D(plm_des0_N_35139_i_0_i), + .Q(plm_rx0_des_dat[11]), + .CLR(plm_rst) + ); + FDC plm_des0_reg_rx_des_dat_10_ ( + .C(mgt_clk), + .D(plm_des0_N_35137_i_0_i), + .Q(plm_rx0_des_dat[10]), + .CLR(plm_rst) + ); + FDC plm_des0_reg_rx_des_dat_9_ ( + .C(mgt_clk), + .D(plm_des0_N_35135_i_0_i), + .Q(plm_rx0_des_dat[9]), + .CLR(plm_rst) + ); + FDC plm_des0_reg_rx_des_dat_8_ ( + .C(mgt_clk), + .D(plm_des0_N_35133_i_0_i), + .Q(plm_rx0_des_dat[8]), + .CLR(plm_rst) + ); + FDC plm_des0_reg_stp_1_ ( + .C(mgt_clk), + .D(plm_des0_reg_stp_3[1]), + .Q(plm_des0_reg_stp[1]), + .CLR(plm_rst) + ); + FDC plm_des0_reg_stp_0_ ( + .C(mgt_clk), + .D(plm_des0_reg_stp_4[0]), + .Q(plm_des0_reg_stp[0]), + .CLR(plm_rst) + ); + FDC plm_des0_reg_skp_1_ ( + .C(mgt_clk), + .D(plm_des0_reg_skp_3[1]), + .Q(plm_des0_reg_skp[1]), + .CLR(plm_rst) + ); + FDC plm_des0_reg_skp_0_ ( + .C(mgt_clk), + .D(plm_des0_reg_skp_4[0]), + .Q(plm_des0_reg_skp[0]), + .CLR(plm_rst) + ); + FDC plm_des0_reg_sdp_1_ ( + .C(mgt_clk), + .D(plm_des0_reg_sdp_3[1]), + .Q(plm_des0_reg_sdp[1]), + .CLR(plm_rst) + ); + FDC plm_des0_reg_sdp_0_ ( + .C(mgt_clk), + .D(plm_des0_reg_sdp_4[0]), + .Q(plm_des0_reg_sdp[0]), + .CLR(plm_rst) + ); + FDC plm_des0_reg_pad_1_ ( + .C(mgt_clk), + .D(plm_des0_reg_pad_3[1]), + .Q(plm_des0_reg_pad[1]), + .CLR(plm_rst) + ); + FDC plm_des0_reg_pad_0_ ( + .C(mgt_clk), + .D(plm_des0_reg_pad_4[0]), + .Q(plm_des0_reg_pad[0]), + .CLR(plm_rst) + ); + FDC plm_des0_reg_idl_1_ ( + .C(mgt_clk), + .D(plm_des0_reg_idl_3[1]), + .Q(plm_des0_reg_idl[1]), + .CLR(plm_rst) + ); + FDC plm_des0_reg_idl_0_ ( + .C(mgt_clk), + .D(plm_des0_reg_idl_4[0]), + .Q(plm_des0_reg_idl[0]), + .CLR(plm_rst) + ); + FDC plm_des0_reg_fts_1_ ( + .C(mgt_clk), + .D(plm_des0_reg_fts_3[1]), + .Q(plm_des0_reg_fts[1]), + .CLR(plm_rst) + ); + FDC plm_des0_reg_fts_0_ ( + .C(mgt_clk), + .D(plm_des0_reg_fts_4[0]), + .Q(plm_des0_reg_fts[0]), + .CLR(plm_rst) + ); + FDC plm_des0_reg_edg_1_ ( + .C(mgt_clk), + .D(plm_des0_reg_edg_3[1]), + .Q(plm_des0_reg_edg[1]), + .CLR(plm_rst) + ); + FDC plm_des0_reg_edg_0_ ( + .C(mgt_clk), + .D(plm_des0_reg_edg_4[0]), + .Q(plm_des0_reg_edg[0]), + .CLR(plm_rst) + ); + FDC plm_des0_reg_edb_1_ ( + .C(mgt_clk), + .D(plm_des0_reg_edb_3[1]), + .Q(plm_des0_reg_edb[1]), + .CLR(plm_rst) + ); + FDC plm_des0_reg_rx_des_sym_1_ ( + .C(mgt_clk), + .D(plm_des0_reg_sym[1]), + .Q(plm_rx0_des_sym[1]), + .CLR(plm_rst) + ); + FDC plm_des0_reg_rx_des_sym_0_ ( + .C(mgt_clk), + .D(plm_des0_reg_sym[0]), + .Q(plm_rx0_des_sym[0]), + .CLR(plm_rst) + ); + FDC plm_des0_reg_rx_des_t2p_1_ ( + .C(mgt_clk), + .D(plm_des0_reg_t2p[1]), + .Q(plm_rx0_des_t2p[1]), + .CLR(plm_rst) + ); + FDC plm_des0_reg_rx_des_t2n_1_ ( + .C(mgt_clk), + .D(plm_des0_reg_t2n[1]), + .Q(plm_rx0_des_t2n[1]), + .CLR(plm_rst) + ); + FDC plm_des0_reg_rx_des_t1p_1_ ( + .C(mgt_clk), + .D(plm_des0_reg_t1p[1]), + .Q(plm_rx0_des_t1p[1]), + .CLR(plm_rst) + ); + FDC plm_des0_reg_rx_des_t1n_1_ ( + .C(mgt_clk), + .D(plm_des0_reg_t1n[1]), + .Q(plm_rx0_des_t1n[1]), + .CLR(plm_rst) + ); + FDC plm_des0_reg_rx_des_com_1_ ( + .C(mgt_clk), + .D(plm_des0_reg_com[1]), + .Q(plm_rx0_des_com[1]), + .CLR(plm_rst) + ); + FDC plm_des0_reg_rx_des_com_0_ ( + .C(mgt_clk), + .D(plm_des0_reg_com[0]), + .Q(plm_rx0_des_com[0]), + .CLR(plm_rst) + ); + FDC plm_des0_reg_sym_1_ ( + .C(mgt_clk), + .D(plm_des0_reg_sym_3[1]), + .Q(plm_des0_reg_sym[1]), + .CLR(plm_rst) + ); + FDC plm_des0_reg_sym_0_ ( + .C(mgt_clk), + .D(plm_des0_reg_sym_4[0]), + .Q(plm_des0_reg_sym[0]), + .CLR(plm_rst) + ); + FDC plm_des0_reg_t2p_1_ ( + .C(mgt_clk), + .D(plm_des0_reg_t2p_3[1]), + .Q(plm_des0_reg_t2p[1]), + .CLR(plm_rst) + ); + FDC plm_des0_reg_t2n_1_ ( + .C(mgt_clk), + .D(plm_des0_reg_t2n_3[1]), + .Q(plm_des0_reg_t2n[1]), + .CLR(plm_rst) + ); + FDC plm_des0_reg_t1p_1_ ( + .C(mgt_clk), + .D(plm_des0_reg_t1p_3[1]), + .Q(plm_des0_reg_t1p[1]), + .CLR(plm_rst) + ); + FDC plm_des0_reg_t1n_1_ ( + .C(mgt_clk), + .D(plm_des0_reg_t1n_3[1]), + .Q(plm_des0_reg_t1n[1]), + .CLR(plm_rst) + ); + FDC plm_des0_reg_rx_raw_dat_14_ ( + .C(mgt_clk), + .D(plm_des0_reg_dat[14]), + .Q(plm_rx0_raw_dat[14]), + .CLR(plm_rst) + ); + FDC plm_des0_reg_rx_raw_dat_13_ ( + .C(mgt_clk), + .D(plm_des0_reg_dat[13]), + .Q(plm_rx0_raw_dat[13]), + .CLR(plm_rst) + ); + FDC plm_des0_reg_rx_raw_dat_12_ ( + .C(mgt_clk), + .D(plm_des0_reg_dat[12]), + .Q(plm_rx0_raw_dat[12]), + .CLR(plm_rst) + ); + FDC plm_des0_reg_rx_raw_dat_11_ ( + .C(mgt_clk), + .D(plm_des0_reg_dat[11]), + .Q(plm_rx0_raw_dat[11]), + .CLR(plm_rst) + ); + FDC plm_des0_reg_rx_raw_dat_10_ ( + .C(mgt_clk), + .D(plm_des0_reg_dat[10]), + .Q(plm_rx0_raw_dat[10]), + .CLR(plm_rst) + ); + FDC plm_des0_reg_rx_raw_dat_9_ ( + .C(mgt_clk), + .D(plm_des0_reg_dat[9]), + .Q(plm_rx0_raw_dat[9]), + .CLR(plm_rst) + ); + FDC plm_des0_reg_rx_raw_dat_8_ ( + .C(mgt_clk), + .D(plm_des0_reg_dat[8]), + .Q(plm_rx0_raw_dat[8]), + .CLR(plm_rst) + ); + FDC plm_des0_reg_rx_raw_dat_7_ ( + .C(mgt_clk), + .D(plm_des0_reg_dat[7]), + .Q(plm_rx0_raw_dat[7]), + .CLR(plm_rst) + ); + FDC plm_des0_reg_rx_raw_dat_6_ ( + .C(mgt_clk), + .D(plm_des0_reg_dat[6]), + .Q(plm_rx0_raw_dat[6]), + .CLR(plm_rst) + ); + FDC plm_des0_reg_rx_raw_dat_5_ ( + .C(mgt_clk), + .D(plm_des0_reg_dat[5]), + .Q(plm_rx0_raw_dat[5]), + .CLR(plm_rst) + ); + FDC plm_des0_reg_rx_raw_dat_4_ ( + .C(mgt_clk), + .D(plm_des0_reg_dat[4]), + .Q(plm_rx0_raw_dat[4]), + .CLR(plm_rst) + ); + FDC plm_des0_reg_rx_raw_dat_3_ ( + .C(mgt_clk), + .D(plm_des0_reg_dat[3]), + .Q(plm_rx0_raw_dat[3]), + .CLR(plm_rst) + ); + FDC plm_des0_reg_rx_raw_dat_2_ ( + .C(mgt_clk), + .D(plm_des0_reg_dat[2]), + .Q(plm_rx0_raw_dat[2]), + .CLR(plm_rst) + ); + FDC plm_des0_reg_rx_raw_dat_1_ ( + .C(mgt_clk), + .D(plm_des0_reg_dat[1]), + .Q(plm_rx0_raw_dat[1]), + .CLR(plm_rst) + ); + FDC plm_des0_reg_rx_raw_dat_0_ ( + .C(mgt_clk), + .D(plm_des0_reg_dat[0]), + .Q(plm_rx0_raw_dat[0]), + .CLR(plm_rst) + ); + FDC plm_des0_reg_data_9_ ( + .C(mgt_clk), + .D(plm_rx0_data[9]), + .Q(plm_des0_reg_data[9]), + .CLR(plm_rst) + ); + FDC plm_des0_reg_data_8_ ( + .C(mgt_clk), + .D(plm_rx0_data[8]), + .Q(plm_des0_reg_data[8]), + .CLR(plm_rst) + ); + FDC plm_des0_reg_data_7_ ( + .C(mgt_clk), + .D(plm_rx0_data[7]), + .Q(plm_des0_reg_data[7]), + .CLR(plm_rst) + ); + FDC plm_des0_reg_data_6_ ( + .C(mgt_clk), + .D(plm_rx0_data[6]), + .Q(plm_des0_reg_data[6]), + .CLR(plm_rst) + ); + FDC plm_des0_reg_data_5_ ( + .C(mgt_clk), + .D(plm_rx0_data[5]), + .Q(plm_des0_reg_data[5]), + .CLR(plm_rst) + ); + FDC plm_des0_reg_data_4_ ( + .C(mgt_clk), + .D(plm_rx0_data[4]), + .Q(plm_des0_reg_data[4]), + .CLR(plm_rst) + ); + FDC plm_des0_reg_data_3_ ( + .C(mgt_clk), + .D(plm_rx0_data[3]), + .Q(plm_des0_reg_data[3]), + .CLR(plm_rst) + ); + FDC plm_des0_reg_data_2_ ( + .C(mgt_clk), + .D(plm_rx0_data[2]), + .Q(plm_des0_reg_data[2]), + .CLR(plm_rst) + ); + FDC plm_des0_reg_data_1_ ( + .C(mgt_clk), + .D(plm_rx0_data[1]), + .Q(plm_des0_reg_data[1]), + .CLR(plm_rst) + ); + FDC plm_des0_reg_data_0_ ( + .C(mgt_clk), + .D(plm_rx0_data[0]), + .Q(plm_des0_reg_data[0]), + .CLR(plm_rst) + ); + FDC plm_des0_reg_spesh_1_ ( + .C(mgt_clk), + .D(plm_rx0_char_is_k[1]), + .Q(plm_des0_reg_spesh[1]), + .CLR(plm_rst) + ); + FDC plm_des0_reg_spesh_0_ ( + .C(mgt_clk), + .D(plm_rx0_char_is_k[0]), + .Q(plm_des0_reg_spesh[0]), + .CLR(plm_rst) + ); + FDC plm_des0_reg_nitbl_1_ ( + .C(mgt_clk), + .D(plm_rx0_not_in_table[1]), + .Q(plm_des0_reg_nitbl[1]), + .CLR(plm_rst) + ); + FDC plm_des0_reg_nitbl_0_ ( + .C(mgt_clk), + .D(plm_rx0_not_in_table[0]), + .Q(plm_des0_reg_nitbl[0]), + .CLR(plm_rst) + ); + FDC plm_des0_reg_rx_raw_dat_15_ ( + .C(mgt_clk), + .D(plm_des0_reg_dat[15]), + .Q(plm_rx0_raw_dat[15]), + .CLR(plm_rst) + ); + FDC plm_des0_reg_dat_6_ ( + .C(mgt_clk), + .D(plm_des0_reg_data[6]), + .Q(plm_des0_reg_dat[6]), + .CLR(plm_rst) + ); + FDC plm_des0_reg_dat_5_ ( + .C(mgt_clk), + .D(plm_des0_reg_data[5]), + .Q(plm_des0_reg_dat[5]), + .CLR(plm_rst) + ); + FDC plm_des0_reg_dat_4_ ( + .C(mgt_clk), + .D(plm_des0_reg_data[4]), + .Q(plm_des0_reg_dat[4]), + .CLR(plm_rst) + ); + FDC plm_des0_reg_dat_3_ ( + .C(mgt_clk), + .D(plm_des0_reg_data[3]), + .Q(plm_des0_reg_dat[3]), + .CLR(plm_rst) + ); + FDC plm_des0_reg_dat_2_ ( + .C(mgt_clk), + .D(plm_des0_reg_data[2]), + .Q(plm_des0_reg_dat[2]), + .CLR(plm_rst) + ); + FDC plm_des0_reg_dat_1_ ( + .C(mgt_clk), + .D(plm_des0_reg_data[1]), + .Q(plm_des0_reg_dat[1]), + .CLR(plm_rst) + ); + FDC plm_des0_reg_dat_0_ ( + .C(mgt_clk), + .D(plm_des0_reg_data[0]), + .Q(plm_des0_reg_dat[0]), + .CLR(plm_rst) + ); + FDC plm_des0_reg_kkk_1_ ( + .C(mgt_clk), + .D(plm_des0_reg_spesh[1]), + .Q(plm_des0_reg_kkk[1]), + .CLR(plm_rst) + ); + FDC plm_des0_reg_kkk_0_ ( + .C(mgt_clk), + .D(plm_des0_reg_spesh[0]), + .Q(plm_des0_reg_kkk[0]), + .CLR(plm_rst) + ); + FDC plm_des0_reg_data_15_ ( + .C(mgt_clk), + .D(plm_rx0_data[15]), + .Q(plm_des0_reg_data[15]), + .CLR(plm_rst) + ); + FDC plm_des0_reg_data_14_ ( + .C(mgt_clk), + .D(plm_rx0_data[14]), + .Q(plm_des0_reg_data[14]), + .CLR(plm_rst) + ); + FDC plm_des0_reg_data_13_ ( + .C(mgt_clk), + .D(plm_rx0_data[13]), + .Q(plm_des0_reg_data[13]), + .CLR(plm_rst) + ); + FDC plm_des0_reg_data_12_ ( + .C(mgt_clk), + .D(plm_rx0_data[12]), + .Q(plm_des0_reg_data[12]), + .CLR(plm_rst) + ); + FDC plm_des0_reg_data_11_ ( + .C(mgt_clk), + .D(plm_rx0_data[11]), + .Q(plm_des0_reg_data[11]), + .CLR(plm_rst) + ); + FDC plm_des0_reg_data_10_ ( + .C(mgt_clk), + .D(plm_rx0_data[10]), + .Q(plm_des0_reg_data[10]), + .CLR(plm_rst) + ); + FDC plm_des0_reg_dat_15_ ( + .C(mgt_clk), + .D(plm_des0_reg_data[15]), + .Q(plm_des0_reg_dat[15]), + .CLR(plm_rst) + ); + FDC plm_des0_reg_dat_14_ ( + .C(mgt_clk), + .D(plm_des0_reg_data[14]), + .Q(plm_des0_reg_dat[14]), + .CLR(plm_rst) + ); + FDC plm_des0_reg_dat_13_ ( + .C(mgt_clk), + .D(plm_des0_reg_data[13]), + .Q(plm_des0_reg_dat[13]), + .CLR(plm_rst) + ); + FDC plm_des0_reg_dat_12_ ( + .C(mgt_clk), + .D(plm_des0_reg_data[12]), + .Q(plm_des0_reg_dat[12]), + .CLR(plm_rst) + ); + FDC plm_des0_reg_dat_11_ ( + .C(mgt_clk), + .D(plm_des0_reg_data[11]), + .Q(plm_des0_reg_dat[11]), + .CLR(plm_rst) + ); + FDC plm_des0_reg_dat_10_ ( + .C(mgt_clk), + .D(plm_des0_reg_data[10]), + .Q(plm_des0_reg_dat[10]), + .CLR(plm_rst) + ); + FDC plm_des0_reg_dat_9_ ( + .C(mgt_clk), + .D(plm_des0_reg_data[9]), + .Q(plm_des0_reg_dat[9]), + .CLR(plm_rst) + ); + FDC plm_des0_reg_dat_8_ ( + .C(mgt_clk), + .D(plm_des0_reg_data[8]), + .Q(plm_des0_reg_dat[8]), + .CLR(plm_rst) + ); + FDC plm_des0_reg_dat_7_ ( + .C(mgt_clk), + .D(plm_des0_reg_data[7]), + .Q(plm_des0_reg_dat[7]), + .CLR(plm_rst) + ); + FDPE plm_des0_reg_lfsr_one_15_ ( + .PRE(plm_rst), + .CE(plm_des0_reg_lfsr_one32_i), + .C(mgt_clk), + .D(plm_des0_N_69382_i), + .Q(plm_des0_reg_lfsr_one_15__334) + ); + FDPE plm_des0_reg_lfsr_one_14_ ( + .PRE(plm_rst), + .CE(plm_des0_reg_lfsr_one32_i), + .C(mgt_clk), + .D(plm_des0_N_69381_i), + .Q(plm_des0_reg_lfsr_one_14__377) + ); + FDPE plm_des0_reg_lfsr_one_13_ ( + .PRE(plm_rst), + .CE(plm_des0_reg_lfsr_one32_i), + .C(mgt_clk), + .D(plm_des0_N_69380_i), + .Q(plm_des0_reg_lfsr_one_13__337) + ); + FDPE plm_des0_reg_lfsr_one_12_ ( + .PRE(plm_rst), + .CE(plm_des0_reg_lfsr_one32_i), + .C(mgt_clk), + .D(plm_des0_N_67782_i), + .Q(plm_des0_reg_lfsr_one_12__365) + ); + FDPE plm_des0_reg_lfsr_one_11_ ( + .PRE(plm_rst), + .CE(plm_des0_reg_lfsr_one32_i), + .C(mgt_clk), + .D(plm_des0_N_69379_i), + .Q(plm_des0_reg_lfsr_one_11__374) + ); + FDPE plm_des0_reg_lfsr_one_10_ ( + .PRE(plm_rst), + .CE(plm_des0_reg_lfsr_one32_i), + .C(mgt_clk), + .D(plm_des0_N_67781_i), + .Q(plm_des0_reg_lfsr_one_10__540) + ); + FDPE plm_des0_reg_lfsr_one_9_ ( + .PRE(plm_rst), + .CE(plm_des0_reg_lfsr_one32_i), + .C(mgt_clk), + .D(plm_des0_N_67780_i), + .Q(plm_des0_reg_lfsr_one_9__541) + ); + FDPE plm_des0_reg_lfsr_one_8_ ( + .PRE(plm_rst), + .CE(plm_des0_reg_lfsr_one32_i), + .C(mgt_clk), + .D(plm_des0_N_67779_i), + .Q(plm_des0_reg_lfsr_one_8__542) + ); + FDPE plm_des0_reg_lfsr_one_7_ ( + .PRE(plm_rst), + .CE(plm_des0_reg_lfsr_one32_i), + .C(mgt_clk), + .D(plm_des0_N_67778_i), + .Q(plm_des0_reg_lfsr_one_7__543) + ); + FDPE plm_des0_reg_lfsr_one_6_ ( + .PRE(plm_rst), + .CE(plm_des0_reg_lfsr_one32_i), + .C(mgt_clk), + .D(plm_des0_N_67777_i), + .Q(plm_des0_reg_lfsr_one_6__544) + ); + FDPE plm_des0_reg_lfsr_one_5_ ( + .PRE(plm_rst), + .CE(plm_des0_reg_lfsr_one32_i), + .C(mgt_clk), + .D(plm_des0_N_67776_i), + .Q(plm_des0_reg_lfsr_one_5__545) + ); + FDPE plm_des0_reg_lfsr_one_4_ ( + .PRE(plm_rst), + .CE(plm_des0_reg_lfsr_one32_i), + .C(mgt_clk), + .D(plm_des0_N_69378_i), + .Q(plm_des0_reg_lfsr_one_4__546) + ); + FDPE plm_des0_reg_lfsr_one_3_ ( + .PRE(plm_rst), + .CE(plm_des0_reg_lfsr_one32_i), + .C(mgt_clk), + .D(plm_des0_N_67775_i), + .Q(plm_des0_reg_lfsr_one_3__336) + ); + FDPE plm_des0_reg_lfsr_one_2_ ( + .PRE(plm_rst), + .CE(plm_des0_reg_lfsr_one32_i), + .C(mgt_clk), + .D(plm_des0_N_69377_i), + .Q(plm_des0_reg_lfsr_one_2__547) + ); + FDPE plm_des0_reg_lfsr_one_1_ ( + .PRE(plm_rst), + .CE(plm_des0_reg_lfsr_one32_i), + .C(mgt_clk), + .D(plm_des0_N_69376_i), + .Q(plm_des0_reg_lfsr_one_1__333) + ); + FDPE plm_des0_reg_lfsr_one_0_ ( + .PRE(plm_rst), + .CE(plm_des0_reg_lfsr_one32_i), + .C(mgt_clk), + .D(plm_des0_N_69375_i), + .Q(plm_des0_reg_lfsr_one_0__373) + ); + FDPE plm_des0_reg_lfsr_two_15_ ( + .PRE(plm_rst), + .CE(plm_des0_reg_lfsr_one32_i), + .C(mgt_clk), + .D(plm_des0_N_67790_i), + .Q(plm_des0_reg_lfsr_two_15__345) + ); + FDPE plm_des0_reg_lfsr_two_14_ ( + .PRE(plm_rst), + .CE(plm_des0_reg_lfsr_one32_i), + .C(mgt_clk), + .D(plm_des0_N_67789_i), + .Q(plm_des0_reg_lfsr_two_14__548) + ); + FDPE plm_des0_reg_lfsr_two_13_ ( + .PRE(plm_rst), + .CE(plm_des0_reg_lfsr_one32_i), + .C(mgt_clk), + .D(plm_des0_N_67788_i), + .Q(plm_des0_reg_lfsr_two_13__344) + ); + FDCE plm_des0_reg_lfsr_two_12_ ( + .CE(plm_des0_reg_lfsr_one32_i), + .C(mgt_clk), + .D(plm_des0_N_8718_i), + .Q(plm_des0_reg_lfsr_two_12__549), + .CLR(plm_rst) + ); + FDPE plm_des0_reg_lfsr_two_11_ ( + .PRE(plm_rst), + .CE(plm_des0_reg_lfsr_one32_i), + .C(mgt_clk), + .D(plm_des0_N_67787_i), + .Q(plm_des0_reg_lfsr_two_11__343) + ); + FDCE plm_des0_reg_lfsr_two_10_ ( + .CE(plm_des0_reg_lfsr_one32_i), + .C(mgt_clk), + .D(plm_des0_N_8720_i), + .Q(plm_des0_reg_lfsr_two_10__550), + .CLR(plm_rst) + ); + FDCE plm_des0_reg_lfsr_two_9_ ( + .CE(plm_des0_reg_lfsr_one32_i), + .C(mgt_clk), + .D(plm_des0_N_8721_i), + .Q(plm_des0_reg_lfsr_two_9__551), + .CLR(plm_rst) + ); + FDCE plm_des0_reg_lfsr_two_8_ ( + .CE(plm_des0_reg_lfsr_one32_i), + .C(mgt_clk), + .D(plm_des0_N_8722_i), + .Q(plm_des0_reg_lfsr_two_8__552), + .CLR(plm_rst) + ); + FDCE plm_des0_reg_lfsr_two_7_ ( + .CE(plm_des0_reg_lfsr_one32_i), + .C(mgt_clk), + .D(plm_des0_N_8723_i), + .Q(plm_des0_reg_lfsr_two_7__553), + .CLR(plm_rst) + ); + FDCE plm_des0_reg_lfsr_two_6_ ( + .CE(plm_des0_reg_lfsr_one32_i), + .C(mgt_clk), + .D(plm_des0_N_8724_i), + .Q(plm_des0_reg_lfsr_two_6__554), + .CLR(plm_rst) + ); + FDCE plm_des0_reg_lfsr_two_5_ ( + .CE(plm_des0_reg_lfsr_one32_i), + .C(mgt_clk), + .D(plm_des0_N_8725_i), + .Q(plm_des0_reg_lfsr_two_5__555), + .CLR(plm_rst) + ); + FDPE plm_des0_reg_lfsr_two_4_ ( + .PRE(plm_rst), + .CE(plm_des0_reg_lfsr_one32_i), + .C(mgt_clk), + .D(plm_des0_N_67786_i), + .Q(plm_des0_reg_lfsr_two_4__378) + ); + FDCE plm_des0_reg_lfsr_two_3_ ( + .CE(plm_des0_reg_lfsr_one32_i), + .C(mgt_clk), + .D(plm_des0_N_8727_i), + .Q(plm_des0_reg_lfsr_two_3__556), + .CLR(plm_rst) + ); + FDPE plm_des0_reg_lfsr_two_2_ ( + .PRE(plm_rst), + .CE(plm_des0_reg_lfsr_one32_i), + .C(mgt_clk), + .D(plm_des0_N_67785_i), + .Q(plm_des0_reg_lfsr_two_2__380) + ); + FDPE plm_des0_reg_lfsr_two_1_ ( + .PRE(plm_rst), + .CE(plm_des0_reg_lfsr_one32_i), + .C(mgt_clk), + .D(plm_des0_N_67784_i), + .Q(plm_des0_reg_lfsr_two_1__379) + ); + FDPE plm_des0_reg_lfsr_two_0_ ( + .PRE(plm_rst), + .CE(plm_des0_reg_lfsr_one32_i), + .C(mgt_clk), + .D(plm_des0_N_67783_i), + .Q(plm_des0_reg_lfsr_two_0__342) + ); + defparam plm_scr0_scram_reg_tx_data_12_sn_m2.INIT = 4'h1; + LUT2 plm_scr0_scram_reg_tx_data_12_sn_m2 ( + .I0(plm_scr0_reg_dis[0]), + .I1(plm_scr0_reg_skp[1]), + .O(plm_scr0_reg_tx_data_12_sn_m2) + ); + defparam plm_scr0_one_adv2_1_13_.INIT = 4'h6; + LUT2 plm_scr0_one_adv2_1_13_ ( + .I0(plm_scr0_reg_lfsr_one_8__593), + .I1(plm_scr0_reg_lfsr_one_9__592), + .O(plm_scr0_one_adv2_1_13__557) + ); + defparam plm_scr0_one_adv2_1_11_.INIT = 4'h6; + LUT2 plm_scr0_one_adv2_1_11_ ( + .I0(plm_scr0_reg_lfsr_one_6__595), + .I1(plm_scr0_reg_lfsr_one_7__594), + .O(plm_scr0_one_adv2_1_11__558) + ); + defparam plm_scr0_one_adv2_1_6_.INIT = 4'h6; + LUT2 plm_scr0_one_adv2_1_6_ ( + .I0(plm_scr0_reg_lfsr_one_1__327), + .I1(plm_scr0_reg_lfsr_one_12__590), + .O(plm_scr0_one_adv2_1_6__563) + ); + defparam plm_scr0_one_adv2_1_5_.INIT = 4'h6; + LUT2 plm_scr0_one_adv2_1_5_ ( + .I0(plm_scr0_reg_lfsr_one_2__598), + .I1(plm_scr0_reg_lfsr_one_13__331), + .O(plm_scr0_one_adv2_1_5__567) + ); + defparam plm_scr0_two_adv2_1_14_.INIT = 4'h6; + LUT2 plm_scr0_two_adv2_1_14_ ( + .I0(plm_scr0_reg_lfsr_two_9__601), + .I1(plm_scr0_reg_lfsr_two_10__600), + .O(plm_scr0_two_adv2_1_14__570) + ); + defparam plm_scr0_two_adv2_1_12_.INIT = 4'h6; + LUT2 plm_scr0_two_adv2_1_12_ ( + .I0(plm_scr0_reg_lfsr_two_7__603), + .I1(plm_scr0_reg_lfsr_two_8__602), + .O(plm_scr0_two_adv2_1_12__560) + ); + defparam plm_scr0_two_adv2_1_7_.INIT = 4'h6; + LUT2 plm_scr0_two_adv2_1_7_ ( + .I0(plm_scr0_reg_lfsr_two_2__607), + .I1(plm_scr0_reg_lfsr_two_13__339), + .O(plm_scr0_two_adv2_1_7__562) + ); + defparam plm_scr0_two_adv2_1_1_.INIT = 4'h6; + LUT2 plm_scr0_two_adv2_1_1_ ( + .I0(plm_scr0_reg_lfsr_two_12__599), + .I1(plm_scr0_reg_lfsr_two_13__339), + .O(plm_scr0_two_adv2_1_1__561) + ); + defparam plm_scr0_two_adv2_0_15_.INIT = 4'h6; + LUT2 plm_scr0_two_adv2_0_15_ ( + .I0(plm_scr0_reg_lfsr_two_10__600), + .I1(plm_scr0_reg_lfsr_two_15__340), + .O(plm_scr0_two_adv2_0_15__559) + ); + defparam plm_scr0_two_adv2_0_4_.INIT = 4'h6; + LUT2 plm_scr0_two_adv2_0_4_ ( + .I0(plm_scr0_reg_lfsr_two_0__371), + .I1(plm_scr0_reg_lfsr_two_1__608), + .O(plm_scr0_two_adv2_0_4__565) + ); + defparam plm_scr0_lfsrs_reg_lfsr_one32_i.INIT = 4'h7; + LUT2 plm_scr0_lfsrs_reg_lfsr_one32_i ( + .I0(plm_scr0_reg_skp[0]), + .I1(plm_scr0_reg_skp[1]), + .O(plm_scr0_reg_lfsr_one32_i) + ); + defparam plm_scr0_lfsrs_reg_lfsr_one29.INIT = 16'h0001; + LUT4 plm_scr0_lfsrs_reg_lfsr_one29 ( + .I0(plm_scr0_reg_com[0]), + .I1(plm_scr0_reg_com[1]), + .I2(plm_scr0_reg_skp[0]), + .I3(plm_scr0_reg_skp[1]), + .O(plm_scr0_reg_lfsr_one29) + ); + defparam plm_scr0_un1_reg_com_1.INIT = 16'h1110; + LUT4 plm_scr0_un1_reg_com_1 ( + .I0(plm_scr0_reg_com[0]), + .I1(plm_scr0_reg_com[1]), + .I2(plm_scr0_reg_skp[0]), + .I3(plm_scr0_reg_skp[1]), + .O(plm_scr0_un1_reg_com_1_588) + ); + defparam plm_scr0_lfsrs_reg_lfsr_two_12_iv_i_o2_15_.INIT = 8'h15; + LUT3 plm_scr0_lfsrs_reg_lfsr_two_12_iv_i_o2_15_ ( + .I0(plm_scr0_reg_com[0]), + .I1(plm_scr0_reg_com[1]), + .I2(plm_scr0_reg_skp[0]), + .O(plm_scr0_N_17481_i) + ); + defparam plm_scr0_two_adv2_1_6_.INIT = 8'h96; + LUT3 plm_scr0_two_adv2_1_6_ ( + .I0(plm_scr0_reg_lfsr_two_3__606), + .I1(plm_scr0_reg_lfsr_two_12__599), + .I2(plm_scr0_reg_lfsr_two_14__381), + .O(plm_scr0_two_adv2_1_6__566) + ); + defparam plm_scr0_one_adv2_2_.INIT = 8'h96; + LUT3 plm_scr0_one_adv2_2_ ( + .I0(plm_scr0_one_adv2_1_5__567), + .I1(plm_scr0_reg_lfsr_one_14__387), + .I2(plm_scr0_reg_lfsr_one_15__328), + .O(plm_scr0_one_adv2_2__586) + ); + defparam plm_scr0_one_adv2_1_.INIT = 8'h96; + LUT3 plm_scr0_one_adv2_1_ ( + .I0(plm_scr0_one_adv2_1_6__563), + .I1(plm_scr0_reg_lfsr_one_13__331), + .I2(plm_scr0_reg_lfsr_one_14__387), + .O(plm_scr0_one_adv2_1__587) + ); + defparam plm_scr0_two_adv2_12_.INIT = 8'h96; + LUT3 plm_scr0_two_adv2_12_ ( + .I0(plm_scr0_reg_lfsr_two_9__601), + .I1(plm_scr0_reg_lfsr_two_12__599), + .I2(plm_scr0_two_adv2_1_12__560), + .O(plm_scr0_two_adv2_12__572) + ); + defparam plm_scr0_two_adv2_10_.INIT = 16'h6996; + LUT4 plm_scr0_two_adv2_10_ ( + .I0(plm_scr0_reg_lfsr_two_5__605), + .I1(plm_scr0_reg_lfsr_two_6__604), + .I2(plm_scr0_reg_lfsr_two_7__603), + .I3(plm_scr0_reg_lfsr_two_10__600), + .O(plm_scr0_two_adv2_10__575) + ); + defparam plm_scr0_one_adv2_15_.INIT = 16'h6996; + LUT4 plm_scr0_one_adv2_15_ ( + .I0(plm_scr0_reg_lfsr_one_10__591), + .I1(plm_scr0_reg_lfsr_one_11__376), + .I2(plm_scr0_reg_lfsr_one_12__590), + .I3(plm_scr0_reg_lfsr_one_15__328), + .O(plm_scr0_one_adv2_15__569) + ); + defparam plm_scr0_one_adv2_14_.INIT = 16'h6996; + LUT4 plm_scr0_one_adv2_14_ ( + .I0(plm_scr0_reg_lfsr_one_9__592), + .I1(plm_scr0_reg_lfsr_one_10__591), + .I2(plm_scr0_reg_lfsr_one_11__376), + .I3(plm_scr0_reg_lfsr_one_14__387), + .O(plm_scr0_one_adv2_14__568) + ); + defparam plm_scr0_one_adv2_13_.INIT = 8'h96; + LUT3 plm_scr0_one_adv2_13_ ( + .I0(plm_scr0_one_adv2_1_13__557), + .I1(plm_scr0_reg_lfsr_one_10__591), + .I2(plm_scr0_reg_lfsr_one_13__331), + .O(plm_scr0_one_adv2_13__571) + ); + defparam plm_scr0_one_adv2_12_.INIT = 8'h96; + LUT3 plm_scr0_one_adv2_12_ ( + .I0(plm_scr0_one_adv2_1_13__557), + .I1(plm_scr0_reg_lfsr_one_7__594), + .I2(plm_scr0_reg_lfsr_one_12__590), + .O(plm_scr0_one_adv2_12__573) + ); + defparam plm_scr0_one_adv2_11_.INIT = 8'h96; + LUT3 plm_scr0_one_adv2_11_ ( + .I0(plm_scr0_one_adv2_1_11__558), + .I1(plm_scr0_reg_lfsr_one_8__593), + .I2(plm_scr0_reg_lfsr_one_11__376), + .O(plm_scr0_one_adv2_11__574) + ); + defparam plm_scr0_one_adv2_10_.INIT = 8'h96; + LUT3 plm_scr0_one_adv2_10_ ( + .I0(plm_scr0_one_adv2_1_11__558), + .I1(plm_scr0_reg_lfsr_one_5__596), + .I2(plm_scr0_reg_lfsr_one_10__591), + .O(plm_scr0_one_adv2_10__576) + ); + defparam plm_scr0_lfsrs_reg_lfsr_two_12_iv_i_a2_9_.INIT = 8'h04; + LUT3 plm_scr0_lfsrs_reg_lfsr_two_12_iv_i_a2_9_ ( + .I0(plm_scr0_reg_com[0]), + .I1(plm_scr0_reg_com[1]), + .I2(plm_scr0_reg_skp[0]), + .O(plm_scr0_reg_lfsr_two_12_iv_i_a2_9_) + ); + defparam plm_scr0_input_decoder_reg_com_4_0_a2_1_4_0_.INIT = 16'h0080; + LUT4_L plm_scr0_input_decoder_reg_com_4_0_a2_1_4_0_ ( + .I0(plm_scr0_reg_raw_char[2]), + .I1(plm_scr0_reg_raw_char[3]), + .I2(plm_scr0_reg_raw_char[4]), + .I3(plm_scr0_reg_raw_char[6]), + .LO(plm_scr0_reg_com_4_0_a2_1_4[0]) + ); + defparam plm_scr0_input_decoder_reg_com_3_0_a2_1_4_1_.INIT = 16'h0080; + LUT4_L plm_scr0_input_decoder_reg_com_3_0_a2_1_4_1_ ( + .I0(plm_scr0_reg_raw_char[10]), + .I1(plm_scr0_reg_raw_char[11]), + .I2(plm_scr0_reg_raw_char[12]), + .I3(plm_scr0_reg_raw_char[14]), + .LO(plm_scr0_reg_com_3_0_a2_1_4[1]) + ); + defparam plm_scr0_two_adv2_1_8_.INIT = 8'h96; + LUT3 plm_scr0_two_adv2_1_8_ ( + .I0(plm_scr0_reg_lfsr_two_4__382), + .I1(plm_scr0_reg_lfsr_two_5__605), + .I2(plm_scr0_reg_lfsr_two_8__602), + .O(plm_scr0_two_adv2_1_8__564) + ); + defparam plm_scr0_one_adv2_1_0_9_.INIT = 8'h96; + LUT3 plm_scr0_one_adv2_1_0_9_ ( + .I0(plm_scr0_reg_lfsr_one_6__595), + .I1(plm_scr0_reg_lfsr_one_9__592), + .I2(plm_scr0_reg_lfsr_one_15__328), + .O(plm_scr0_one_adv2_1_0[9]) + ); + defparam plm_scr0_one_adv2_0_.INIT = 8'h96; + LUT3 plm_scr0_one_adv2_0_ ( + .I0(N_10558_1), + .I1(plm_scr0_reg_lfsr_one_12__590), + .I2(plm_scr0_reg_lfsr_one_13__331), + .O(plm_scr0_one_adv2_0__589) + ); + defparam plm_scr0_lfsrs_reg_lfsr_two_12_iv_i_a2_0_15_.INIT = 16'h8228; + LUT4_L plm_scr0_lfsrs_reg_lfsr_two_12_iv_i_a2_0_15_ ( + .I0(plm_scr0_reg_lfsr_one29), + .I1(plm_scr0_reg_lfsr_two_11__372), + .I2(plm_scr0_reg_lfsr_two_12__599), + .I3(plm_scr0_two_adv2_0_15__559), + .LO(plm_scr0_reg_lfsr_two_12_iv_i_a2_0_15_) + ); + defparam plm_scr0_lfsrs_reg_lfsr_two_12_iv_i_a2_0_13_.INIT = 16'h8228; + LUT4 plm_scr0_lfsrs_reg_lfsr_two_12_iv_i_a2_0_13_ ( + .I0(plm_scr0_reg_lfsr_one29), + .I1(plm_scr0_reg_lfsr_two_8__602), + .I2(plm_scr0_reg_lfsr_two_13__339), + .I3(plm_scr0_two_adv2_1_14__570), + .O(plm_scr0_reg_lfsr_two_12_iv_i_a2_0_13_) + ); + defparam plm_scr0_lfsrs_reg_lfsr_two_12_iv_i_a2_11_.INIT = 16'h8228; + LUT4 plm_scr0_lfsrs_reg_lfsr_two_12_iv_i_a2_11_ ( + .I0(plm_scr0_reg_lfsr_one29), + .I1(plm_scr0_reg_lfsr_two_6__604), + .I2(plm_scr0_reg_lfsr_two_11__372), + .I3(plm_scr0_two_adv2_1_12__560), + .O(plm_scr0_reg_lfsr_two_12_iv_i_a2_11_) + ); + defparam plm_scr0_lfsrs_reg_lfsr_two_12_iv_i_a2_0_2_.INIT = 16'h8228; + LUT4 plm_scr0_lfsrs_reg_lfsr_two_12_iv_i_a2_0_2_ ( + .I0(plm_scr0_reg_lfsr_one29), + .I1(plm_scr0_reg_lfsr_two_14__381), + .I2(plm_scr0_reg_lfsr_two_15__340), + .I3(plm_scr0_two_adv2_1_7__562), + .O(plm_scr0_reg_lfsr_two_12_iv_i_a2_0_2_) + ); + defparam plm_scr0_lfsrs_reg_lfsr_two_12_iv_i_a2_1_.INIT = 16'h8228; + LUT4 plm_scr0_lfsrs_reg_lfsr_two_12_iv_i_a2_1_ ( + .I0(plm_scr0_reg_lfsr_one29), + .I1(plm_scr0_reg_lfsr_two_1__608), + .I2(plm_scr0_reg_lfsr_two_14__381), + .I3(plm_scr0_two_adv2_1_1__561), + .O(plm_scr0_reg_lfsr_two_12_iv_i_a2_1_) + ); + defparam plm_scr0_lfsrs_reg_lfsr_two_12_iv_i_a2_0_.INIT = 8'h48; + LUT3 plm_scr0_lfsrs_reg_lfsr_two_12_iv_i_a2_0_ ( + .I0(N_10469_1), + .I1(plm_scr0_reg_lfsr_one29), + .I2(plm_scr0_two_adv2_1_1__561), + .O(plm_scr0_reg_lfsr_two_12_iv_i_a2_0_) + ); + defparam plm_scr0_lfsrs_reg_lfsr_one_12_iv_i_a2_12_.INIT = 4'h8; + LUT2_L plm_scr0_lfsrs_reg_lfsr_one_12_iv_i_a2_12_ ( + .I0(plm_scr0_reg_lfsr_one29), + .I1(plm_scr0_one_adv2_12__573), + .LO(plm_scr0_reg_lfsr_one_12_iv_i_a2_12_) + ); + defparam plm_scr0_lfsrs_reg_lfsr_one_12_iv_i_a2_10_.INIT = 4'h8; + LUT2_L plm_scr0_lfsrs_reg_lfsr_one_12_iv_i_a2_10_ ( + .I0(plm_scr0_reg_lfsr_one29), + .I1(plm_scr0_one_adv2_10__576), + .LO(plm_scr0_reg_lfsr_one_12_iv_i_a2_10_) + ); + defparam plm_scr0_lfsrs_reg_lfsr_one_12_iv_i_a2_0_7_.INIT = 4'h8; + LUT2 plm_scr0_lfsrs_reg_lfsr_one_12_iv_i_a2_0_7_ ( + .I0(plm_scr0_reg_lfsr_two_7__603), + .I1(plm_scr0_un1_reg_com_1_588), + .O(plm_scr0_reg_lfsr_one_12_iv_i_a2_0[7]) + ); + defparam plm_scr0_lfsrs_reg_lfsr_one_12_iv_i_a2_3_.INIT = 4'h8; + LUT2 plm_scr0_lfsrs_reg_lfsr_one_12_iv_i_a2_3_ ( + .I0(plm_scr0_reg_lfsr_two_3__606), + .I1(plm_scr0_un1_reg_com_1_588), + .O(plm_scr0_reg_lfsr_one_12_iv_i_a2_3_) + ); + defparam plm_scr0_two_adv2_7_.INIT = 16'h6996; + LUT4 plm_scr0_two_adv2_7_ ( + .I0(N_17486_i_0), + .I1(plm_scr0_reg_lfsr_two_3__606), + .I2(plm_scr0_reg_lfsr_two_7__603), + .I3(plm_scr0_two_adv2_1_7__562), + .O(plm_scr0_two_adv2_7__579) + ); + defparam plm_scr0_one_adv2_6_.INIT = 16'h6996; + LUT4 plm_scr0_one_adv2_6_ ( + .I0(G_332_388), + .I1(plm_scr0_one_adv2_1_6__563), + .I2(plm_scr0_reg_lfsr_one_2__598), + .I3(plm_scr0_reg_lfsr_one_6__595), + .O(plm_scr0_one_adv2_6__582) + ); + defparam plm_scr0_one_adv2_7_.INIT = 16'h6996; + LUT4 plm_scr0_one_adv2_7_ ( + .I0(G_324_332), + .I1(plm_scr0_reg_lfsr_one_2__598), + .I2(plm_scr0_reg_lfsr_one_4__597), + .I3(plm_scr0_reg_lfsr_one_7__594), + .O(plm_scr0_one_adv2_7__580) + ); + defparam plm_scr0_one_adv2_4_.INIT = 8'h96; + LUT3 plm_scr0_one_adv2_4_ ( + .I0(G_323_329), + .I1(plm_scr0_reg_lfsr_one_4__597), + .I2(plm_scr0_reg_lfsr_one_14__387), + .O(plm_scr0_one_adv2_4__584) + ); + defparam plm_scr0_two_adv2_9_.INIT = 16'h6996; + LUT4 plm_scr0_two_adv2_9_ ( + .I0(N_17486_i_0), + .I1(plm_scr0_reg_lfsr_two_5__605), + .I2(plm_scr0_reg_lfsr_two_6__604), + .I3(plm_scr0_reg_lfsr_two_9__601), + .O(plm_scr0_two_adv2_9__577) + ); + defparam plm_scr0_two_adv2_6_.INIT = 16'h6996; + LUT4 plm_scr0_two_adv2_6_ ( + .I0(plm_scr0_reg_lfsr_two_1__608), + .I1(plm_scr0_reg_lfsr_two_2__607), + .I2(plm_scr0_reg_lfsr_two_6__604), + .I3(plm_scr0_two_adv2_1_6__566), + .O(plm_scr0_two_adv2_6__581) + ); + defparam plm_scr0_two_adv2_5_.INIT = 16'h6996; + LUT4 plm_scr0_two_adv2_5_ ( + .I0(G_327_341), + .I1(plm_scr0_reg_lfsr_two_1__608), + .I2(plm_scr0_reg_lfsr_two_2__607), + .I3(plm_scr0_reg_lfsr_two_5__605), + .O(plm_scr0_two_adv2_5__583) + ); + defparam plm_scr0_one_adv2_8_.INIT = 16'h6996; + LUT4 plm_scr0_one_adv2_8_ ( + .I0(G_332_388), + .I1(plm_scr0_reg_lfsr_one_4__597), + .I2(plm_scr0_reg_lfsr_one_5__596), + .I3(plm_scr0_reg_lfsr_one_8__593), + .O(plm_scr0_one_adv2_8__578) + ); + defparam plm_scr0_input_decoder_reg_com_4_0_a2_1_0_.INIT = 16'h0200; + LUT4 plm_scr0_input_decoder_reg_com_4_0_a2_1_0_ ( + .I0(plm_scr0_reg_com_4_0_a2_1_4[0]), + .I1(plm_scr0_reg_raw_char[0]), + .I2(plm_scr0_reg_raw_char[1]), + .I3(plm_scr0_reg_raw_char_is_k[0]), + .O(plm_scr0_reg_com_4_1[0]) + ); + defparam plm_scr0_input_decoder_reg_com_3_0_a2_1_1_.INIT = 16'h0200; + LUT4 plm_scr0_input_decoder_reg_com_3_0_a2_1_1_ ( + .I0(plm_scr0_reg_com_3_0_a2_1_4[1]), + .I1(plm_scr0_reg_raw_char[8]), + .I2(plm_scr0_reg_raw_char[9]), + .I3(plm_scr0_reg_raw_char_is_k[1]), + .O(plm_scr0_reg_com_3_1[1]) + ); + defparam plm_scr0_scram_reg_tx_data_12_2_m3_0_am_4_.INIT = 8'h65; + LUT3 plm_scr0_scram_reg_tx_data_12_2_m3_0_am_4_ ( + .I0(plm_scr0_reg_dat[4]), + .I1(plm_scr0_reg_dis[0]), + .I2(plm_scr0_reg_lfsr_one_11__376), + .O(plm_scr0_reg_tx_data_12_2_m3_0_am_4_) + ); + defparam plm_scr0_scram_reg_tx_data_12_2_m3_0_bm_4_.INIT = 8'hC9; + LUT3 plm_scr0_scram_reg_tx_data_12_2_m3_0_bm_4_ ( + .I0(plm_scr0_reg_com[1]), + .I1(plm_scr0_reg_dat[4]), + .I2(plm_scr0_reg_lfsr_two_11__372), + .O(plm_scr0_reg_tx_data_12_2_m3_0_bm_4_) + ); + MUXF5 plm_scr0_scram_reg_tx_data_12_2_m3_0_4_ ( + .I0(plm_scr0_reg_tx_data_12_2_m3_0_am_4_), + .I1(plm_scr0_reg_tx_data_12_2_m3_0_bm_4_), + .O(plm_scr0_reg_tx_data_12_2_m3_0_4_), + .S(plm_scr0_reg_tx_data_12_sn_m2) + ); + defparam plm_scr0_scram_reg_tx_data_12_2_m3_0_am_1_.INIT = 8'h65; + LUT3 plm_scr0_scram_reg_tx_data_12_2_m3_0_am_1_ ( + .I0(plm_scr0_reg_dat[1]), + .I1(plm_scr0_reg_dis[0]), + .I2(plm_scr0_reg_lfsr_one_14__387), + .O(plm_scr0_reg_tx_data_12_2_m3_0_am_1_) + ); + defparam plm_scr0_scram_reg_tx_data_12_2_m3_0_bm_1_.INIT = 8'hC9; + LUT3 plm_scr0_scram_reg_tx_data_12_2_m3_0_bm_1_ ( + .I0(plm_scr0_reg_com[1]), + .I1(plm_scr0_reg_dat[1]), + .I2(plm_scr0_reg_lfsr_two_14__381), + .O(plm_scr0_reg_tx_data_12_2_m3_0_bm_1_) + ); + MUXF5 plm_scr0_scram_reg_tx_data_12_2_m3_0_1_ ( + .I0(plm_scr0_reg_tx_data_12_2_m3_0_am_1_), + .I1(plm_scr0_reg_tx_data_12_2_m3_0_bm_1_), + .O(plm_scr0_reg_tx_data_12_2_m3_0_1_), + .S(plm_scr0_reg_tx_data_12_sn_m2) + ); + defparam plm_scr0_lfsrs_reg_lfsr_two_12_iv_i_a2_0_9_.INIT = 16'h9600; + LUT4 plm_scr0_lfsrs_reg_lfsr_two_12_iv_i_a2_0_9_ ( + .I0(plm_scr0_one_adv2_1_0[9]), + .I1(plm_scr0_reg_lfsr_one_4__597), + .I2(plm_scr0_reg_lfsr_one_5__596), + .I3(plm_scr0_un1_reg_com_1_588), + .O(plm_scr0_reg_lfsr_two_12_iv_i_a2_0_9_) + ); + defparam plm_scr0_lfsrs_reg_lfsr_two_12_iv_i_a2_0_8_.INIT = 16'h8228; + LUT4 plm_scr0_lfsrs_reg_lfsr_two_12_iv_i_a2_0_8_ ( + .I0(plm_scr0_reg_lfsr_one29), + .I1(plm_scr0_reg_lfsr_two_3__606), + .I2(plm_scr0_reg_lfsr_two_14__381), + .I3(plm_scr0_two_adv2_1_8__564), + .O(plm_scr0_reg_lfsr_two_12_iv_i_a2_0_8_) + ); + defparam plm_scr0_lfsrs_reg_lfsr_two_12_iv_i_a2_5_.INIT = 16'h9600; + LUT4 plm_scr0_lfsrs_reg_lfsr_two_12_iv_i_a2_5_ ( + .I0(G_323_329), + .I1(plm_scr0_one_adv2_1_5__567), + .I2(plm_scr0_reg_lfsr_one_5__596), + .I3(plm_scr0_un1_reg_com_1_588), + .O(plm_scr0_reg_lfsr_two_12_iv_i_a2_5_) + ); + defparam plm_scr0_lfsrs_reg_lfsr_two_12_iv_i_a2_0_4_.INIT = 16'h9060; + LUT4 plm_scr0_lfsrs_reg_lfsr_two_12_iv_i_a2_0_4_ ( + .I0(N_17486_i_0), + .I1(N_17488_i_0), + .I2(plm_scr0_reg_lfsr_one29), + .I3(plm_scr0_two_adv2_0_4__565), + .O(plm_scr0_reg_lfsr_two_12_iv_i_a2_0_4_) + ); + defparam plm_scr0_lfsrs_reg_lfsr_two_12_iv_i_a2_0_3_.INIT = 8'h48; + LUT3_L plm_scr0_lfsrs_reg_lfsr_two_12_iv_i_a2_0_3_ ( + .I0(G_327_341), + .I1(plm_scr0_reg_lfsr_one29), + .I2(plm_scr0_two_adv2_1_6__566), + .LO(plm_scr0_reg_lfsr_two_12_iv_i_a2_0_3_) + ); + defparam plm_scr0_lfsrs_reg_lfsr_one_12_iv_i_a2_9_.INIT = 16'h8228; + LUT4_L plm_scr0_lfsrs_reg_lfsr_one_12_iv_i_a2_9_ ( + .I0(plm_scr0_reg_lfsr_one29), + .I1(plm_scr0_one_adv2_1_0[9]), + .I2(plm_scr0_reg_lfsr_one_4__597), + .I3(plm_scr0_reg_lfsr_one_5__596), + .LO(plm_scr0_reg_lfsr_one_12_iv_i_a2_9_) + ); + defparam plm_scr0_lfsrs_reg_lfsr_one_12_iv_i_a2_8_.INIT = 4'h8; + LUT2_L plm_scr0_lfsrs_reg_lfsr_one_12_iv_i_a2_8_ ( + .I0(plm_scr0_reg_lfsr_one29), + .I1(plm_scr0_one_adv2_8__578), + .LO(plm_scr0_reg_lfsr_one_12_iv_i_a2_8_) + ); + defparam plm_scr0_lfsrs_reg_lfsr_one_12_iv_i_a2_0_6_.INIT = 4'h8; + LUT2_L plm_scr0_lfsrs_reg_lfsr_one_12_iv_i_a2_0_6_ ( + .I0(plm_scr0_reg_lfsr_one29), + .I1(plm_scr0_one_adv2_6__582), + .LO(plm_scr0_reg_lfsr_one_12_iv_i_a2_0[6]) + ); + defparam plm_scr0_lfsrs_reg_lfsr_one_12_iv_i_a2_5_.INIT = 16'h8448; + LUT4_L plm_scr0_lfsrs_reg_lfsr_one_12_iv_i_a2_5_ ( + .I0(G_323_329), + .I1(plm_scr0_reg_lfsr_one29), + .I2(plm_scr0_one_adv2_1_5__567), + .I3(plm_scr0_reg_lfsr_one_5__596), + .LO(plm_scr0_reg_lfsr_one_12_iv_i_a2_5_) + ); + defparam plm_scr0_scram_reg_tx_data_12_2_am_7_.INIT = 8'h9A; + LUT3 plm_scr0_scram_reg_tx_data_12_2_am_7_ ( + .I0(plm_scr0_reg_dat[7]), + .I1(plm_scr0_reg_dis[0]), + .I2(plm_scr0_reg_lfsr_one_8__593), + .O(plm_scr0_reg_tx_data_12_2_am_7_) + ); + defparam plm_scr0_scram_reg_tx_data_12_2_bm_7_.INIT = 8'h36; + LUT3 plm_scr0_scram_reg_tx_data_12_2_bm_7_ ( + .I0(plm_scr0_reg_com[1]), + .I1(plm_scr0_reg_dat[7]), + .I2(plm_scr0_reg_lfsr_two_8__602), + .O(plm_scr0_reg_tx_data_12_2_bm_7_) + ); + MUXF5 plm_scr0_scram_reg_tx_data_12_2_7_ ( + .I0(plm_scr0_reg_tx_data_12_2_am_7_), + .I1(plm_scr0_reg_tx_data_12_2_bm_7_), + .O(plm_scr0_reg_tx_data_12_7_), + .S(plm_scr0_reg_tx_data_12_sn_m2) + ); + defparam plm_scr0_scram_reg_tx_data_12_2_am_6_.INIT = 8'h9A; + LUT3 plm_scr0_scram_reg_tx_data_12_2_am_6_ ( + .I0(plm_scr0_reg_dat[6]), + .I1(plm_scr0_reg_dis[0]), + .I2(plm_scr0_reg_lfsr_one_9__592), + .O(plm_scr0_reg_tx_data_12_2_am_6_) + ); + defparam plm_scr0_scram_reg_tx_data_12_2_bm_6_.INIT = 8'h36; + LUT3 plm_scr0_scram_reg_tx_data_12_2_bm_6_ ( + .I0(plm_scr0_reg_com[1]), + .I1(plm_scr0_reg_dat[6]), + .I2(plm_scr0_reg_lfsr_two_9__601), + .O(plm_scr0_reg_tx_data_12_2_bm_6_) + ); + MUXF5 plm_scr0_scram_reg_tx_data_12_2_6_ ( + .I0(plm_scr0_reg_tx_data_12_2_am_6_), + .I1(plm_scr0_reg_tx_data_12_2_bm_6_), + .O(plm_scr0_reg_tx_data_12_6_), + .S(plm_scr0_reg_tx_data_12_sn_m2) + ); + defparam plm_scr0_scram_reg_tx_data_12_2_am_5_.INIT = 8'h9A; + LUT3 plm_scr0_scram_reg_tx_data_12_2_am_5_ ( + .I0(plm_scr0_reg_dat[5]), + .I1(plm_scr0_reg_dis[0]), + .I2(plm_scr0_reg_lfsr_one_10__591), + .O(plm_scr0_reg_tx_data_12_2_am_5_) + ); + defparam plm_scr0_scram_reg_tx_data_12_2_bm_5_.INIT = 8'h36; + LUT3 plm_scr0_scram_reg_tx_data_12_2_bm_5_ ( + .I0(plm_scr0_reg_com[1]), + .I1(plm_scr0_reg_dat[5]), + .I2(plm_scr0_reg_lfsr_two_10__600), + .O(plm_scr0_reg_tx_data_12_2_bm_5_) + ); + MUXF5 plm_scr0_scram_reg_tx_data_12_2_5_ ( + .I0(plm_scr0_reg_tx_data_12_2_am_5_), + .I1(plm_scr0_reg_tx_data_12_2_bm_5_), + .O(plm_scr0_reg_tx_data_12_5_), + .S(plm_scr0_reg_tx_data_12_sn_m2) + ); + defparam plm_scr0_scram_reg_tx_data_12_2_am_3_.INIT = 8'h9A; + LUT3 plm_scr0_scram_reg_tx_data_12_2_am_3_ ( + .I0(plm_scr0_reg_dat[3]), + .I1(plm_scr0_reg_dis[0]), + .I2(plm_scr0_reg_lfsr_one_12__590), + .O(plm_scr0_reg_tx_data_12_2_am_3_) + ); + defparam plm_scr0_scram_reg_tx_data_12_2_bm_3_.INIT = 8'h36; + LUT3 plm_scr0_scram_reg_tx_data_12_2_bm_3_ ( + .I0(plm_scr0_reg_com[1]), + .I1(plm_scr0_reg_dat[3]), + .I2(plm_scr0_reg_lfsr_two_12__599), + .O(plm_scr0_reg_tx_data_12_2_bm_3_) + ); + MUXF5 plm_scr0_scram_reg_tx_data_12_2_3_ ( + .I0(plm_scr0_reg_tx_data_12_2_am_3_), + .I1(plm_scr0_reg_tx_data_12_2_bm_3_), + .O(plm_scr0_reg_tx_data_12_3_), + .S(plm_scr0_reg_tx_data_12_sn_m2) + ); + defparam plm_scr0_scram_reg_tx_data_12_2_am_2_.INIT = 8'h9A; + LUT3 plm_scr0_scram_reg_tx_data_12_2_am_2_ ( + .I0(plm_scr0_reg_dat[2]), + .I1(plm_scr0_reg_dis[0]), + .I2(plm_scr0_reg_lfsr_one_13__331), + .O(plm_scr0_reg_tx_data_12_2_am_2_) + ); + defparam plm_scr0_scram_reg_tx_data_12_2_bm_2_.INIT = 8'h36; + LUT3 plm_scr0_scram_reg_tx_data_12_2_bm_2_ ( + .I0(plm_scr0_reg_com[1]), + .I1(plm_scr0_reg_dat[2]), + .I2(plm_scr0_reg_lfsr_two_13__339), + .O(plm_scr0_reg_tx_data_12_2_bm_2_) + ); + MUXF5 plm_scr0_scram_reg_tx_data_12_2_2_ ( + .I0(plm_scr0_reg_tx_data_12_2_am_2_), + .I1(plm_scr0_reg_tx_data_12_2_bm_2_), + .O(plm_scr0_reg_tx_data_12_2_), + .S(plm_scr0_reg_tx_data_12_sn_m2) + ); + defparam plm_scr0_scram_reg_tx_data_12_2_am_0_.INIT = 8'h9A; + LUT3 plm_scr0_scram_reg_tx_data_12_2_am_0_ ( + .I0(plm_scr0_reg_dat[0]), + .I1(plm_scr0_reg_dis[0]), + .I2(plm_scr0_reg_lfsr_one_15__328), + .O(plm_scr0_reg_tx_data_12_2_am_0_) + ); + defparam plm_scr0_scram_reg_tx_data_12_2_bm_0_.INIT = 8'h36; + LUT3 plm_scr0_scram_reg_tx_data_12_2_bm_0_ ( + .I0(plm_scr0_reg_com[1]), + .I1(plm_scr0_reg_dat[0]), + .I2(plm_scr0_reg_lfsr_two_15__340), + .O(plm_scr0_reg_tx_data_12_2_bm_0_) + ); + MUXF5 plm_scr0_scram_reg_tx_data_12_2_0_ ( + .I0(plm_scr0_reg_tx_data_12_2_am_0_), + .I1(plm_scr0_reg_tx_data_12_2_bm_0_), + .O(plm_scr0_reg_tx_data_12_0_), + .S(plm_scr0_reg_tx_data_12_sn_m2) + ); + defparam plm_scr0_one_adv2_3_.INIT = 16'h6996; + LUT4 plm_scr0_one_adv2_3_ ( + .I0(G_324_332), + .I1(N_10558_1), + .I2(plm_scr0_reg_lfsr_one_12__590), + .I3(plm_scr0_reg_lfsr_one_14__387), + .O(plm_scr0_one_adv2_3__585) + ); + defparam plm_scr0_lfsrs_reg_lfsr_two_12_iv_i_0_14_.INIT = 8'h2A; + LUT3_L plm_scr0_lfsrs_reg_lfsr_two_12_iv_i_0_14_ ( + .I0(plm_scr0_N_17481_i), + .I1(plm_scr0_one_adv2_14__568), + .I2(plm_scr0_un1_reg_com_1_588), + .LO(plm_scr0_reg_lfsr_two_12_iv_i_0[14]) + ); + defparam plm_scr0_scram_N_17494_i.INIT = 4'h1; + LUT1_L plm_scr0_scram_N_17494_i ( + .I0(plm_scr0_reg_tx_data_12_2_m3_0_4_), + .LO(plm_scr0_N_17494_i) + ); + defparam plm_scr0_scram_N_17493_i.INIT = 4'h1; + LUT1_L plm_scr0_scram_N_17493_i ( + .I0(plm_scr0_reg_tx_data_12_2_m3_0_1_), + .LO(plm_scr0_N_17493_i) + ); + defparam plm_scr0_input_decoder_reg_skp_3_0_a2_1_.INIT = 8'h02; + LUT3_L plm_scr0_input_decoder_reg_skp_3_0_a2_1_ ( + .I0(plm_scr0_reg_com_3_1[1]), + .I1(plm_scr0_reg_raw_char[13]), + .I2(plm_scr0_reg_raw_char[15]), + .LO(plm_scr0_reg_skp_3[1]) + ); + defparam plm_scr0_input_decoder_reg_skp_4_0_a2_0_.INIT = 8'h02; + LUT3_L plm_scr0_input_decoder_reg_skp_4_0_a2_0_ ( + .I0(plm_scr0_reg_com_4_1[0]), + .I1(plm_scr0_reg_raw_char[5]), + .I2(plm_scr0_reg_raw_char[7]), + .LO(plm_scr0_reg_skp_4[0]) + ); + defparam plm_scr0_input_decoder_reg_com_3_0_a2_1_.INIT = 8'h80; + LUT3_L plm_scr0_input_decoder_reg_com_3_0_a2_1_ ( + .I0(plm_scr0_reg_com_3_1[1]), + .I1(plm_scr0_reg_raw_char[13]), + .I2(plm_scr0_reg_raw_char[15]), + .LO(plm_scr0_reg_com_3[1]) + ); + defparam plm_scr0_input_decoder_reg_com_4_0_a2_0_.INIT = 8'h80; + LUT3_L plm_scr0_input_decoder_reg_com_4_0_a2_0_ ( + .I0(plm_scr0_reg_com_4_1[0]), + .I1(plm_scr0_reg_raw_char[5]), + .I2(plm_scr0_reg_raw_char[7]), + .LO(plm_scr0_reg_com_4[0]) + ); + defparam plm_scr0_input_decoder_N_12053_i.INIT = 8'hFE; + LUT3_L plm_scr0_input_decoder_N_12053_i ( + .I0(plm_reg_disdes), + .I1(plm_scr0_reg_raw_char_is_k[1]), + .I2(plm_scr0_reg_raw_char_pass[1]), + .LO(plm_scr0_N_12053_i) + ); + defparam plm_scr0_input_decoder_N_12052_i.INIT = 8'hFE; + LUT3_L plm_scr0_input_decoder_N_12052_i ( + .I0(plm_reg_disdes), + .I1(plm_scr0_reg_raw_char_is_k[0]), + .I2(plm_scr0_reg_raw_char_pass[0]), + .LO(plm_scr0_N_12052_i) + ); + defparam plm_scr0_scram_reg_tx_data_6_0_15_.INIT = 8'h9A; + LUT3_L plm_scr0_scram_reg_tx_data_6_0_15_ ( + .I0(plm_scr0_reg_dat[15]), + .I1(plm_scr0_reg_dis[1]), + .I2(plm_scr0_reg_lfsr_one_8__593), + .LO(plm_scr0_reg_tx_data_6[15]) + ); + defparam plm_scr0_scram_reg_tx_data_6_0_14_.INIT = 8'h9A; + LUT3_L plm_scr0_scram_reg_tx_data_6_0_14_ ( + .I0(plm_scr0_reg_dat[14]), + .I1(plm_scr0_reg_dis[1]), + .I2(plm_scr0_reg_lfsr_one_9__592), + .LO(plm_scr0_reg_tx_data_6[14]) + ); + defparam plm_scr0_scram_reg_tx_data_6_0_13_.INIT = 8'h9A; + LUT3_L plm_scr0_scram_reg_tx_data_6_0_13_ ( + .I0(plm_scr0_reg_dat[13]), + .I1(plm_scr0_reg_dis[1]), + .I2(plm_scr0_reg_lfsr_one_10__591), + .LO(plm_scr0_reg_tx_data_6[13]) + ); + defparam plm_scr0_scram_reg_tx_data_6_0_12_.INIT = 8'h9A; + LUT3_L plm_scr0_scram_reg_tx_data_6_0_12_ ( + .I0(plm_scr0_reg_dat[12]), + .I1(plm_scr0_reg_dis[1]), + .I2(plm_scr0_reg_lfsr_one_11__376), + .LO(plm_scr0_reg_tx_data_6[12]) + ); + defparam plm_scr0_scram_reg_tx_data_6_0_11_.INIT = 8'h9A; + LUT3_L plm_scr0_scram_reg_tx_data_6_0_11_ ( + .I0(plm_scr0_reg_dat[11]), + .I1(plm_scr0_reg_dis[1]), + .I2(plm_scr0_reg_lfsr_one_12__590), + .LO(plm_scr0_reg_tx_data_6[11]) + ); + defparam plm_scr0_scram_reg_tx_data_6_0_10_.INIT = 8'h9A; + LUT3_L plm_scr0_scram_reg_tx_data_6_0_10_ ( + .I0(plm_scr0_reg_dat[10]), + .I1(plm_scr0_reg_dis[1]), + .I2(plm_scr0_reg_lfsr_one_13__331), + .LO(plm_scr0_reg_tx_data_6[10]) + ); + defparam plm_scr0_scram_reg_tx_data_6_0_9_.INIT = 8'h9A; + LUT3_L plm_scr0_scram_reg_tx_data_6_0_9_ ( + .I0(plm_scr0_reg_dat[9]), + .I1(plm_scr0_reg_dis[1]), + .I2(plm_scr0_reg_lfsr_one_14__387), + .LO(plm_scr0_reg_tx_data_6[9]) + ); + defparam plm_scr0_scram_reg_tx_data_6_0_8_.INIT = 8'h9A; + LUT3_L plm_scr0_scram_reg_tx_data_6_0_8_ ( + .I0(plm_scr0_reg_dat[8]), + .I1(plm_scr0_reg_dis[1]), + .I2(plm_scr0_reg_lfsr_one_15__328), + .LO(plm_scr0_reg_tx_data_6[8]) + ); + defparam plm_scr0_lfsrs_reg_lfsr_one_12_0_iv_i_15_.INIT = 16'hD0DD; + LUT4_L plm_scr0_lfsrs_reg_lfsr_one_12_0_iv_i_15_ ( + .I0(plm_scr0_reg_lfsr_one29), + .I1(plm_scr0_one_adv2_15__569), + .I2(plm_scr0_reg_lfsr_two_15__340), + .I3(plm_scr0_un1_reg_com_1_588), + .LO(plm_scr0_N_17450_i) + ); + defparam plm_scr0_lfsrs_reg_lfsr_one_12_0_iv_i_14_.INIT = 16'hD0DD; + LUT4_L plm_scr0_lfsrs_reg_lfsr_one_12_0_iv_i_14_ ( + .I0(plm_scr0_reg_lfsr_one29), + .I1(plm_scr0_one_adv2_14__568), + .I2(plm_scr0_reg_lfsr_two_14__381), + .I3(plm_scr0_un1_reg_com_1_588), + .LO(plm_scr0_N_17452_i) + ); + defparam plm_scr0_lfsrs_reg_lfsr_one_12_0_iv_i_13_.INIT = 16'hD0DD; + LUT4_L plm_scr0_lfsrs_reg_lfsr_one_12_0_iv_i_13_ ( + .I0(plm_scr0_reg_lfsr_one29), + .I1(plm_scr0_one_adv2_13__571), + .I2(plm_scr0_reg_lfsr_two_13__339), + .I3(plm_scr0_un1_reg_com_1_588), + .LO(plm_scr0_N_17454_i) + ); + defparam plm_scr0_lfsrs_N_67804_i.INIT = 16'hFDDD; + LUT4_L plm_scr0_lfsrs_N_67804_i ( + .I0(plm_scr0_N_17481_i), + .I1(plm_scr0_reg_lfsr_one_12_iv_i_a2_12_), + .I2(plm_scr0_reg_lfsr_two_12__599), + .I3(plm_scr0_un1_reg_com_1_588), + .LO(plm_scr0_N_67804_i) + ); + defparam plm_scr0_lfsrs_reg_lfsr_one_12_0_iv_i_11_.INIT = 16'hD0DD; + LUT4_L plm_scr0_lfsrs_reg_lfsr_one_12_0_iv_i_11_ ( + .I0(plm_scr0_reg_lfsr_one29), + .I1(plm_scr0_one_adv2_11__574), + .I2(plm_scr0_reg_lfsr_two_11__372), + .I3(plm_scr0_un1_reg_com_1_588), + .LO(plm_scr0_N_17458_i) + ); + defparam plm_scr0_lfsrs_N_67803_i.INIT = 16'hFDDD; + LUT4_L plm_scr0_lfsrs_N_67803_i ( + .I0(plm_scr0_N_17481_i), + .I1(plm_scr0_reg_lfsr_one_12_iv_i_a2_10_), + .I2(plm_scr0_reg_lfsr_two_10__600), + .I3(plm_scr0_un1_reg_com_1_588), + .LO(plm_scr0_N_67803_i) + ); + defparam plm_scr0_lfsrs_N_67802_i.INIT = 16'hFDDD; + LUT4_L plm_scr0_lfsrs_N_67802_i ( + .I0(plm_scr0_N_17481_i), + .I1(plm_scr0_reg_lfsr_one_12_iv_i_a2_9_), + .I2(plm_scr0_reg_lfsr_two_9__601), + .I3(plm_scr0_un1_reg_com_1_588), + .LO(plm_scr0_N_67802_i) + ); + defparam plm_scr0_lfsrs_N_67801_i.INIT = 16'hFDDD; + LUT4_L plm_scr0_lfsrs_N_67801_i ( + .I0(plm_scr0_N_17481_i), + .I1(plm_scr0_reg_lfsr_one_12_iv_i_a2_8_), + .I2(plm_scr0_reg_lfsr_two_8__602), + .I3(plm_scr0_un1_reg_com_1_588), + .LO(plm_scr0_N_67801_i) + ); + defparam plm_scr0_lfsrs_N_67800_i.INIT = 16'hFDDD; + LUT4_L plm_scr0_lfsrs_N_67800_i ( + .I0(plm_scr0_N_17481_i), + .I1(plm_scr0_reg_lfsr_one_12_iv_i_a2_0[7]), + .I2(plm_scr0_reg_lfsr_one29), + .I3(plm_scr0_one_adv2_7__580), + .LO(plm_scr0_N_67800_i) + ); + defparam plm_scr0_lfsrs_N_67799_i.INIT = 16'hFDDD; + LUT4_L plm_scr0_lfsrs_N_67799_i ( + .I0(plm_scr0_N_17481_i), + .I1(plm_scr0_reg_lfsr_one_12_iv_i_a2_0[6]), + .I2(plm_scr0_reg_lfsr_two_6__604), + .I3(plm_scr0_un1_reg_com_1_588), + .LO(plm_scr0_N_67799_i) + ); + defparam plm_scr0_lfsrs_N_67798_i.INIT = 16'hFDDD; + LUT4_L plm_scr0_lfsrs_N_67798_i ( + .I0(plm_scr0_N_17481_i), + .I1(plm_scr0_reg_lfsr_one_12_iv_i_a2_5_), + .I2(plm_scr0_reg_lfsr_two_5__605), + .I3(plm_scr0_un1_reg_com_1_588), + .LO(plm_scr0_N_67798_i) + ); + defparam plm_scr0_lfsrs_reg_lfsr_one_12_0_iv_i_4_.INIT = 16'hD0DD; + LUT4_L plm_scr0_lfsrs_reg_lfsr_one_12_0_iv_i_4_ ( + .I0(plm_scr0_reg_lfsr_one29), + .I1(plm_scr0_one_adv2_4__584), + .I2(plm_scr0_reg_lfsr_two_4__382), + .I3(plm_scr0_un1_reg_com_1_588), + .LO(plm_scr0_N_17472_i) + ); + defparam plm_scr0_lfsrs_N_67797_i.INIT = 16'hFDDD; + LUT4_L plm_scr0_lfsrs_N_67797_i ( + .I0(plm_scr0_N_17481_i), + .I1(plm_scr0_reg_lfsr_one_12_iv_i_a2_3_), + .I2(plm_scr0_reg_lfsr_one29), + .I3(plm_scr0_one_adv2_3__585), + .LO(plm_scr0_N_67797_i) + ); + defparam plm_scr0_lfsrs_reg_lfsr_one_12_0_iv_i_2_.INIT = 16'hD0DD; + LUT4_L plm_scr0_lfsrs_reg_lfsr_one_12_0_iv_i_2_ ( + .I0(plm_scr0_reg_lfsr_one29), + .I1(plm_scr0_one_adv2_2__586), + .I2(plm_scr0_reg_lfsr_two_2__607), + .I3(plm_scr0_un1_reg_com_1_588), + .LO(plm_scr0_N_17476_i) + ); + defparam plm_scr0_lfsrs_reg_lfsr_one_12_0_iv_1_.INIT = 16'hD0DD; + LUT4_L plm_scr0_lfsrs_reg_lfsr_one_12_0_iv_1_ ( + .I0(plm_scr0_reg_lfsr_one29), + .I1(plm_scr0_one_adv2_1__587), + .I2(plm_scr0_reg_lfsr_two_1__608), + .I3(plm_scr0_un1_reg_com_1_588), + .LO(plm_scr0_reg_lfsr_one_12[1]) + ); + defparam plm_scr0_lfsrs_reg_lfsr_one_12_0_iv_0_.INIT = 16'hD0DD; + LUT4_L plm_scr0_lfsrs_reg_lfsr_one_12_0_iv_0_ ( + .I0(plm_scr0_reg_lfsr_one29), + .I1(plm_scr0_one_adv2_0__589), + .I2(plm_scr0_reg_lfsr_two_0__371), + .I3(plm_scr0_un1_reg_com_1_588), + .LO(plm_scr0_reg_lfsr_one_12[0]) + ); + defparam plm_scr0_lfsrs_N_67816_i.INIT = 16'hFDDD; + LUT4_L plm_scr0_lfsrs_N_67816_i ( + .I0(plm_scr0_N_17481_i), + .I1(plm_scr0_reg_lfsr_two_12_iv_i_a2_0_15_), + .I2(plm_scr0_one_adv2_15__569), + .I3(plm_scr0_un1_reg_com_1_588), + .LO(plm_scr0_N_67816_i) + ); + defparam plm_scr0_lfsrs_N_67815_i.INIT = 16'h4F8F; + LUT4_L plm_scr0_lfsrs_N_67815_i ( + .I0(N_17488_i_0), + .I1(plm_scr0_reg_lfsr_one29), + .I2(plm_scr0_reg_lfsr_two_12_iv_i_0[14]), + .I3(plm_scr0_two_adv2_1_14__570), + .LO(plm_scr0_N_67815_i) + ); + defparam plm_scr0_lfsrs_N_67814_i.INIT = 16'hFDDD; + LUT4_L plm_scr0_lfsrs_N_67814_i ( + .I0(plm_scr0_N_17481_i), + .I1(plm_scr0_reg_lfsr_two_12_iv_i_a2_0_13_), + .I2(plm_scr0_one_adv2_13__571), + .I3(plm_scr0_un1_reg_com_1_588), + .LO(plm_scr0_N_67814_i) + ); + defparam plm_scr0_lfsrs_N_69424_i.INIT = 16'hECA0; + LUT4_L plm_scr0_lfsrs_N_69424_i ( + .I0(plm_scr0_reg_lfsr_one29), + .I1(plm_scr0_one_adv2_12__573), + .I2(plm_scr0_two_adv2_12__572), + .I3(plm_scr0_un1_reg_com_1_588), + .LO(plm_scr0_N_69424_i) + ); + defparam plm_scr0_lfsrs_N_67813_i.INIT = 16'hFDDD; + LUT4_L plm_scr0_lfsrs_N_67813_i ( + .I0(plm_scr0_N_17481_i), + .I1(plm_scr0_reg_lfsr_two_12_iv_i_a2_11_), + .I2(plm_scr0_one_adv2_11__574), + .I3(plm_scr0_un1_reg_com_1_588), + .LO(plm_scr0_N_67813_i) + ); + defparam plm_scr0_lfsrs_N_69423_i.INIT = 16'hECA0; + LUT4_L plm_scr0_lfsrs_N_69423_i ( + .I0(plm_scr0_reg_lfsr_one29), + .I1(plm_scr0_one_adv2_10__576), + .I2(plm_scr0_two_adv2_10__575), + .I3(plm_scr0_un1_reg_com_1_588), + .LO(plm_scr0_N_69423_i) + ); + defparam plm_scr0_lfsrs_N_67812_i.INIT = 16'hFEEE; + LUT4_L plm_scr0_lfsrs_N_67812_i ( + .I0(plm_scr0_reg_lfsr_two_12_iv_i_a2_9_), + .I1(plm_scr0_reg_lfsr_two_12_iv_i_a2_0_9_), + .I2(plm_scr0_reg_lfsr_one29), + .I3(plm_scr0_two_adv2_9__577), + .LO(plm_scr0_N_67812_i) + ); + defparam plm_scr0_lfsrs_N_67811_i.INIT = 16'hFEEE; + LUT4_L plm_scr0_lfsrs_N_67811_i ( + .I0(plm_scr0_reg_lfsr_two_12_iv_i_a2_9_), + .I1(plm_scr0_reg_lfsr_two_12_iv_i_a2_0_8_), + .I2(plm_scr0_one_adv2_8__578), + .I3(plm_scr0_un1_reg_com_1_588), + .LO(plm_scr0_N_67811_i) + ); + defparam plm_scr0_lfsrs_N_69422_i.INIT = 16'hECA0; + LUT4_L plm_scr0_lfsrs_N_69422_i ( + .I0(plm_scr0_reg_lfsr_one29), + .I1(plm_scr0_one_adv2_7__580), + .I2(plm_scr0_two_adv2_7__579), + .I3(plm_scr0_un1_reg_com_1_588), + .LO(plm_scr0_N_69422_i) + ); + defparam plm_scr0_lfsrs_N_8756_i.INIT = 16'hECA0; + LUT4_L plm_scr0_lfsrs_N_8756_i ( + .I0(plm_scr0_reg_lfsr_one29), + .I1(plm_scr0_one_adv2_6__582), + .I2(plm_scr0_two_adv2_6__581), + .I3(plm_scr0_un1_reg_com_1_588), + .LO(plm_scr0_N_8756_i) + ); + defparam plm_scr0_lfsrs_N_67810_i.INIT = 16'hFEEE; + LUT4_L plm_scr0_lfsrs_N_67810_i ( + .I0(plm_scr0_reg_lfsr_two_12_iv_i_a2_9_), + .I1(plm_scr0_reg_lfsr_two_12_iv_i_a2_5_), + .I2(plm_scr0_reg_lfsr_one29), + .I3(plm_scr0_two_adv2_5__583), + .LO(plm_scr0_N_67810_i) + ); + defparam plm_scr0_lfsrs_N_67809_i.INIT = 16'hFDDD; + LUT4_L plm_scr0_lfsrs_N_67809_i ( + .I0(plm_scr0_N_17481_i), + .I1(plm_scr0_reg_lfsr_two_12_iv_i_a2_0_4_), + .I2(plm_scr0_one_adv2_4__584), + .I3(plm_scr0_un1_reg_com_1_588), + .LO(plm_scr0_N_67809_i) + ); + defparam plm_scr0_lfsrs_N_67808_i.INIT = 16'hFEEE; + LUT4_L plm_scr0_lfsrs_N_67808_i ( + .I0(plm_scr0_reg_lfsr_two_12_iv_i_a2_9_), + .I1(plm_scr0_reg_lfsr_two_12_iv_i_a2_0_3_), + .I2(plm_scr0_one_adv2_3__585), + .I3(plm_scr0_un1_reg_com_1_588), + .LO(plm_scr0_N_67808_i) + ); + defparam plm_scr0_lfsrs_N_67807_i.INIT = 16'hFDDD; + LUT4_L plm_scr0_lfsrs_N_67807_i ( + .I0(plm_scr0_N_17481_i), + .I1(plm_scr0_reg_lfsr_two_12_iv_i_a2_0_2_), + .I2(plm_scr0_one_adv2_2__586), + .I3(plm_scr0_un1_reg_com_1_588), + .LO(plm_scr0_N_67807_i) + ); + defparam plm_scr0_lfsrs_N_67806_i.INIT = 16'hFDDD; + LUT4_L plm_scr0_lfsrs_N_67806_i ( + .I0(plm_scr0_N_17481_i), + .I1(plm_scr0_reg_lfsr_two_12_iv_i_a2_1_), + .I2(plm_scr0_one_adv2_1__587), + .I3(plm_scr0_un1_reg_com_1_588), + .LO(plm_scr0_N_67806_i) + ); + defparam plm_scr0_lfsrs_N_67805_i.INIT = 16'hFDDD; + LUT4_L plm_scr0_lfsrs_N_67805_i ( + .I0(plm_scr0_N_17481_i), + .I1(plm_scr0_reg_lfsr_two_12_iv_i_a2_0_), + .I2(plm_scr0_one_adv2_0__589), + .I3(plm_scr0_un1_reg_com_1_588), + .LO(plm_scr0_N_67805_i) + ); + FDC plm_scr0_reg_disable_scr ( + .C(mgt_clk), + .D(plm_N_38584_i_394), + .Q(plm_reg_disdes), + .CLR(plm_rst) + ); + FDC plm_scr0_reg_tx_data_6_ ( + .C(mgt_clk), + .D(plm_scr0_reg_tx_data_12_6_), + .Q(plm_tx0_data[6]), + .CLR(plm_rst) + ); + FDC plm_scr0_reg_tx_data_5_ ( + .C(mgt_clk), + .D(plm_scr0_reg_tx_data_12_5_), + .Q(plm_tx0_data[5]), + .CLR(plm_rst) + ); + FDC plm_scr0_reg_tx_data_4_ ( + .C(mgt_clk), + .D(plm_scr0_N_17494_i), + .Q(plm_tx0_data[4]), + .CLR(plm_rst) + ); + FDC plm_scr0_reg_tx_data_3_ ( + .C(mgt_clk), + .D(plm_scr0_reg_tx_data_12_3_), + .Q(plm_tx0_data[3]), + .CLR(plm_rst) + ); + FDC plm_scr0_reg_tx_data_2_ ( + .C(mgt_clk), + .D(plm_scr0_reg_tx_data_12_2_), + .Q(plm_tx0_data[2]), + .CLR(plm_rst) + ); + FDC plm_scr0_reg_tx_data_1_ ( + .C(mgt_clk), + .D(plm_scr0_N_17493_i), + .Q(plm_tx0_data[1]), + .CLR(plm_rst) + ); + FDC plm_scr0_reg_tx_data_0_ ( + .C(mgt_clk), + .D(plm_scr0_reg_tx_data_12_0_), + .Q(plm_tx0_data[0]), + .CLR(plm_rst) + ); + FDC plm_scr0_reg_skp_1_ ( + .C(mgt_clk), + .D(plm_scr0_reg_skp_3[1]), + .Q(plm_scr0_reg_skp[1]), + .CLR(plm_rst) + ); + FDC plm_scr0_reg_skp_0_ ( + .C(mgt_clk), + .D(plm_scr0_reg_skp_4[0]), + .Q(plm_scr0_reg_skp[0]), + .CLR(plm_rst) + ); + FDC plm_scr0_reg_com_1_ ( + .C(mgt_clk), + .D(plm_scr0_reg_com_3[1]), + .Q(plm_scr0_reg_com[1]), + .CLR(plm_rst) + ); + FDC plm_scr0_reg_com_0_ ( + .C(mgt_clk), + .D(plm_scr0_reg_com_4[0]), + .Q(plm_scr0_reg_com[0]), + .CLR(plm_rst) + ); + FDC plm_scr0_reg_raw_char_is_k_1_ ( + .C(mgt_clk), + .D(plm_tx0_raw_char_is_k[1]), + .Q(plm_scr0_reg_raw_char_is_k[1]), + .CLR(plm_rst) + ); + FDC plm_scr0_reg_raw_char_is_k_0_ ( + .C(mgt_clk), + .D(plm_tx0_raw_char_is_k[0]), + .Q(plm_scr0_reg_raw_char_is_k[0]), + .CLR(plm_rst) + ); + FDC plm_scr0_reg_dis_1_ ( + .C(mgt_clk), + .D(plm_scr0_N_12053_i), + .Q(plm_scr0_reg_dis[1]), + .CLR(plm_rst) + ); + FDC plm_scr0_reg_dis_0_ ( + .C(mgt_clk), + .D(plm_scr0_N_12052_i), + .Q(plm_scr0_reg_dis[0]), + .CLR(plm_rst) + ); + FDC plm_scr0_reg_tx_char_is_k_1_ ( + .C(mgt_clk), + .D(plm_scr0_reg_kkk[1]), + .Q(plm_tx0_char_is_k[1]), + .CLR(plm_rst) + ); + FDC plm_scr0_reg_tx_char_is_k_0_ ( + .C(mgt_clk), + .D(plm_scr0_reg_kkk[0]), + .Q(plm_tx0_char_is_k[0]), + .CLR(plm_rst) + ); + FDC plm_scr0_reg_tx_data_15_ ( + .C(mgt_clk), + .D(plm_scr0_reg_tx_data_6[15]), + .Q(plm_tx0_data[15]), + .CLR(plm_rst) + ); + FDC plm_scr0_reg_tx_data_14_ ( + .C(mgt_clk), + .D(plm_scr0_reg_tx_data_6[14]), + .Q(plm_tx0_data[14]), + .CLR(plm_rst) + ); + FDC plm_scr0_reg_tx_data_13_ ( + .C(mgt_clk), + .D(plm_scr0_reg_tx_data_6[13]), + .Q(plm_tx0_data[13]), + .CLR(plm_rst) + ); + FDC plm_scr0_reg_tx_data_12_ ( + .C(mgt_clk), + .D(plm_scr0_reg_tx_data_6[12]), + .Q(plm_tx0_data[12]), + .CLR(plm_rst) + ); + FDC plm_scr0_reg_tx_data_11_ ( + .C(mgt_clk), + .D(plm_scr0_reg_tx_data_6[11]), + .Q(plm_tx0_data[11]), + .CLR(plm_rst) + ); + FDC plm_scr0_reg_tx_data_10_ ( + .C(mgt_clk), + .D(plm_scr0_reg_tx_data_6[10]), + .Q(plm_tx0_data[10]), + .CLR(plm_rst) + ); + FDC plm_scr0_reg_tx_data_9_ ( + .C(mgt_clk), + .D(plm_scr0_reg_tx_data_6[9]), + .Q(plm_tx0_data[9]), + .CLR(plm_rst) + ); + FDC plm_scr0_reg_tx_data_8_ ( + .C(mgt_clk), + .D(plm_scr0_reg_tx_data_6[8]), + .Q(plm_tx0_data[8]), + .CLR(plm_rst) + ); + FDC plm_scr0_reg_tx_data_7_ ( + .C(mgt_clk), + .D(plm_scr0_reg_tx_data_12_7_), + .Q(plm_tx0_data[7]), + .CLR(plm_rst) + ); + FDC plm_scr0_reg_raw_char_12_ ( + .C(mgt_clk), + .D(plm_tx0_raw_char[12]), + .Q(plm_scr0_reg_raw_char[12]), + .CLR(plm_rst) + ); + FDC plm_scr0_reg_raw_char_11_ ( + .C(mgt_clk), + .D(plm_tx0_raw_char[11]), + .Q(plm_scr0_reg_raw_char[11]), + .CLR(plm_rst) + ); + FDC plm_scr0_reg_raw_char_10_ ( + .C(mgt_clk), + .D(plm_tx0_raw_char[10]), + .Q(plm_scr0_reg_raw_char[10]), + .CLR(plm_rst) + ); + FDC plm_scr0_reg_raw_char_9_ ( + .C(mgt_clk), + .D(plm_tx0_raw_char[9]), + .Q(plm_scr0_reg_raw_char[9]), + .CLR(plm_rst) + ); + FDC plm_scr0_reg_raw_char_8_ ( + .C(mgt_clk), + .D(plm_tx0_raw_char[8]), + .Q(plm_scr0_reg_raw_char[8]), + .CLR(plm_rst) + ); + FDC plm_scr0_reg_raw_char_7_ ( + .C(mgt_clk), + .D(plm_tx0_raw_char[7]), + .Q(plm_scr0_reg_raw_char[7]), + .CLR(plm_rst) + ); + FDC plm_scr0_reg_raw_char_6_ ( + .C(mgt_clk), + .D(plm_tx0_raw_char[6]), + .Q(plm_scr0_reg_raw_char[6]), + .CLR(plm_rst) + ); + FDC plm_scr0_reg_raw_char_5_ ( + .C(mgt_clk), + .D(plm_tx0_raw_char[5]), + .Q(plm_scr0_reg_raw_char[5]), + .CLR(plm_rst) + ); + FDC plm_scr0_reg_raw_char_4_ ( + .C(mgt_clk), + .D(plm_tx0_raw_char[4]), + .Q(plm_scr0_reg_raw_char[4]), + .CLR(plm_rst) + ); + FDC plm_scr0_reg_raw_char_3_ ( + .C(mgt_clk), + .D(plm_tx0_raw_char[3]), + .Q(plm_scr0_reg_raw_char[3]), + .CLR(plm_rst) + ); + FDC plm_scr0_reg_raw_char_2_ ( + .C(mgt_clk), + .D(plm_tx0_raw_char[2]), + .Q(plm_scr0_reg_raw_char[2]), + .CLR(plm_rst) + ); + FDC plm_scr0_reg_raw_char_1_ ( + .C(mgt_clk), + .D(plm_tx0_raw_char[1]), + .Q(plm_scr0_reg_raw_char[1]), + .CLR(plm_rst) + ); + FDC plm_scr0_reg_raw_char_0_ ( + .C(mgt_clk), + .D(plm_tx0_raw_char[0]), + .Q(plm_scr0_reg_raw_char[0]), + .CLR(plm_rst) + ); + FDC plm_scr0_reg_raw_char_pass_1_ ( + .C(mgt_clk), + .D(plm_tx0_raw_char_pass[1]), + .Q(plm_scr0_reg_raw_char_pass[1]), + .CLR(plm_rst) + ); + FDC plm_scr0_reg_raw_char_pass_0_ ( + .C(mgt_clk), + .D(plm_tx0_raw_char_pass[0]), + .Q(plm_scr0_reg_raw_char_pass[0]), + .CLR(plm_rst) + ); + FDC plm_scr0_reg_dat_9_ ( + .C(mgt_clk), + .D(plm_scr0_reg_raw_char[9]), + .Q(plm_scr0_reg_dat[9]), + .CLR(plm_rst) + ); + FDC plm_scr0_reg_dat_8_ ( + .C(mgt_clk), + .D(plm_scr0_reg_raw_char[8]), + .Q(plm_scr0_reg_dat[8]), + .CLR(plm_rst) + ); + FDC plm_scr0_reg_dat_7_ ( + .C(mgt_clk), + .D(plm_scr0_reg_raw_char[7]), + .Q(plm_scr0_reg_dat[7]), + .CLR(plm_rst) + ); + FDC plm_scr0_reg_dat_6_ ( + .C(mgt_clk), + .D(plm_scr0_reg_raw_char[6]), + .Q(plm_scr0_reg_dat[6]), + .CLR(plm_rst) + ); + FDC plm_scr0_reg_dat_5_ ( + .C(mgt_clk), + .D(plm_scr0_reg_raw_char[5]), + .Q(plm_scr0_reg_dat[5]), + .CLR(plm_rst) + ); + FDC plm_scr0_reg_dat_4_ ( + .C(mgt_clk), + .D(plm_scr0_reg_raw_char[4]), + .Q(plm_scr0_reg_dat[4]), + .CLR(plm_rst) + ); + FDC plm_scr0_reg_dat_3_ ( + .C(mgt_clk), + .D(plm_scr0_reg_raw_char[3]), + .Q(plm_scr0_reg_dat[3]), + .CLR(plm_rst) + ); + FDC plm_scr0_reg_dat_2_ ( + .C(mgt_clk), + .D(plm_scr0_reg_raw_char[2]), + .Q(plm_scr0_reg_dat[2]), + .CLR(plm_rst) + ); + FDC plm_scr0_reg_dat_1_ ( + .C(mgt_clk), + .D(plm_scr0_reg_raw_char[1]), + .Q(plm_scr0_reg_dat[1]), + .CLR(plm_rst) + ); + FDC plm_scr0_reg_dat_0_ ( + .C(mgt_clk), + .D(plm_scr0_reg_raw_char[0]), + .Q(plm_scr0_reg_dat[0]), + .CLR(plm_rst) + ); + FDC plm_scr0_reg_kkk_1_ ( + .C(mgt_clk), + .D(plm_scr0_reg_raw_char_is_k[1]), + .Q(plm_scr0_reg_kkk[1]), + .CLR(plm_rst) + ); + FDC plm_scr0_reg_kkk_0_ ( + .C(mgt_clk), + .D(plm_scr0_reg_raw_char_is_k[0]), + .Q(plm_scr0_reg_kkk[0]), + .CLR(plm_rst) + ); + FDC plm_scr0_reg_raw_char_15_ ( + .C(mgt_clk), + .D(plm_tx0_raw_char[15]), + .Q(plm_scr0_reg_raw_char[15]), + .CLR(plm_rst) + ); + FDC plm_scr0_reg_raw_char_14_ ( + .C(mgt_clk), + .D(plm_tx0_raw_char[14]), + .Q(plm_scr0_reg_raw_char[14]), + .CLR(plm_rst) + ); + FDC plm_scr0_reg_raw_char_13_ ( + .C(mgt_clk), + .D(plm_tx0_raw_char[13]), + .Q(plm_scr0_reg_raw_char[13]), + .CLR(plm_rst) + ); + FDC plm_scr0_reg_dat_15_ ( + .C(mgt_clk), + .D(plm_scr0_reg_raw_char[15]), + .Q(plm_scr0_reg_dat[15]), + .CLR(plm_rst) + ); + FDC plm_scr0_reg_dat_14_ ( + .C(mgt_clk), + .D(plm_scr0_reg_raw_char[14]), + .Q(plm_scr0_reg_dat[14]), + .CLR(plm_rst) + ); + FDC plm_scr0_reg_dat_13_ ( + .C(mgt_clk), + .D(plm_scr0_reg_raw_char[13]), + .Q(plm_scr0_reg_dat[13]), + .CLR(plm_rst) + ); + FDC plm_scr0_reg_dat_12_ ( + .C(mgt_clk), + .D(plm_scr0_reg_raw_char[12]), + .Q(plm_scr0_reg_dat[12]), + .CLR(plm_rst) + ); + FDC plm_scr0_reg_dat_11_ ( + .C(mgt_clk), + .D(plm_scr0_reg_raw_char[11]), + .Q(plm_scr0_reg_dat[11]), + .CLR(plm_rst) + ); + FDC plm_scr0_reg_dat_10_ ( + .C(mgt_clk), + .D(plm_scr0_reg_raw_char[10]), + .Q(plm_scr0_reg_dat[10]), + .CLR(plm_rst) + ); + FDPE plm_scr0_reg_lfsr_one_15_ ( + .PRE(plm_rst), + .CE(plm_scr0_reg_lfsr_one32_i), + .C(mgt_clk), + .D(plm_scr0_N_17450_i), + .Q(plm_scr0_reg_lfsr_one_15__328) + ); + FDPE plm_scr0_reg_lfsr_one_14_ ( + .PRE(plm_rst), + .CE(plm_scr0_reg_lfsr_one32_i), + .C(mgt_clk), + .D(plm_scr0_N_17452_i), + .Q(plm_scr0_reg_lfsr_one_14__387) + ); + FDPE plm_scr0_reg_lfsr_one_13_ ( + .PRE(plm_rst), + .CE(plm_scr0_reg_lfsr_one32_i), + .C(mgt_clk), + .D(plm_scr0_N_17454_i), + .Q(plm_scr0_reg_lfsr_one_13__331) + ); + FDPE plm_scr0_reg_lfsr_one_12_ ( + .PRE(plm_rst), + .CE(plm_scr0_reg_lfsr_one32_i), + .C(mgt_clk), + .D(plm_scr0_N_67804_i), + .Q(plm_scr0_reg_lfsr_one_12__590) + ); + FDPE plm_scr0_reg_lfsr_one_11_ ( + .PRE(plm_rst), + .CE(plm_scr0_reg_lfsr_one32_i), + .C(mgt_clk), + .D(plm_scr0_N_17458_i), + .Q(plm_scr0_reg_lfsr_one_11__376) + ); + FDPE plm_scr0_reg_lfsr_one_10_ ( + .PRE(plm_rst), + .CE(plm_scr0_reg_lfsr_one32_i), + .C(mgt_clk), + .D(plm_scr0_N_67803_i), + .Q(plm_scr0_reg_lfsr_one_10__591) + ); + FDPE plm_scr0_reg_lfsr_one_9_ ( + .PRE(plm_rst), + .CE(plm_scr0_reg_lfsr_one32_i), + .C(mgt_clk), + .D(plm_scr0_N_67802_i), + .Q(plm_scr0_reg_lfsr_one_9__592) + ); + FDPE plm_scr0_reg_lfsr_one_8_ ( + .PRE(plm_rst), + .CE(plm_scr0_reg_lfsr_one32_i), + .C(mgt_clk), + .D(plm_scr0_N_67801_i), + .Q(plm_scr0_reg_lfsr_one_8__593) + ); + FDPE plm_scr0_reg_lfsr_one_7_ ( + .PRE(plm_rst), + .CE(plm_scr0_reg_lfsr_one32_i), + .C(mgt_clk), + .D(plm_scr0_N_67800_i), + .Q(plm_scr0_reg_lfsr_one_7__594) + ); + FDPE plm_scr0_reg_lfsr_one_6_ ( + .PRE(plm_rst), + .CE(plm_scr0_reg_lfsr_one32_i), + .C(mgt_clk), + .D(plm_scr0_N_67799_i), + .Q(plm_scr0_reg_lfsr_one_6__595) + ); + FDPE plm_scr0_reg_lfsr_one_5_ ( + .PRE(plm_rst), + .CE(plm_scr0_reg_lfsr_one32_i), + .C(mgt_clk), + .D(plm_scr0_N_67798_i), + .Q(plm_scr0_reg_lfsr_one_5__596) + ); + FDPE plm_scr0_reg_lfsr_one_4_ ( + .PRE(plm_rst), + .CE(plm_scr0_reg_lfsr_one32_i), + .C(mgt_clk), + .D(plm_scr0_N_17472_i), + .Q(plm_scr0_reg_lfsr_one_4__597) + ); + FDPE plm_scr0_reg_lfsr_one_3_ ( + .PRE(plm_rst), + .CE(plm_scr0_reg_lfsr_one32_i), + .C(mgt_clk), + .D(plm_scr0_N_67797_i), + .Q(plm_scr0_reg_lfsr_one_3__330) + ); + FDPE plm_scr0_reg_lfsr_one_2_ ( + .PRE(plm_rst), + .CE(plm_scr0_reg_lfsr_one32_i), + .C(mgt_clk), + .D(plm_scr0_N_17476_i), + .Q(plm_scr0_reg_lfsr_one_2__598) + ); + FDPE plm_scr0_reg_lfsr_one_1_ ( + .PRE(plm_rst), + .CE(plm_scr0_reg_lfsr_one32_i), + .C(mgt_clk), + .D(plm_scr0_reg_lfsr_one_12[1]), + .Q(plm_scr0_reg_lfsr_one_1__327) + ); + FDPE plm_scr0_reg_lfsr_one_0_ ( + .PRE(plm_rst), + .CE(plm_scr0_reg_lfsr_one32_i), + .C(mgt_clk), + .D(plm_scr0_reg_lfsr_one_12[0]), + .Q(plm_scr0_reg_lfsr_one_0__375) + ); + FDPE plm_scr0_reg_lfsr_two_15_ ( + .PRE(plm_rst), + .CE(plm_scr0_reg_lfsr_one32_i), + .C(mgt_clk), + .D(plm_scr0_N_67816_i), + .Q(plm_scr0_reg_lfsr_two_15__340) + ); + FDPE plm_scr0_reg_lfsr_two_14_ ( + .PRE(plm_rst), + .CE(plm_scr0_reg_lfsr_one32_i), + .C(mgt_clk), + .D(plm_scr0_N_67815_i), + .Q(plm_scr0_reg_lfsr_two_14__381) + ); + FDPE plm_scr0_reg_lfsr_two_13_ ( + .PRE(plm_rst), + .CE(plm_scr0_reg_lfsr_one32_i), + .C(mgt_clk), + .D(plm_scr0_N_67814_i), + .Q(plm_scr0_reg_lfsr_two_13__339) + ); + FDCE plm_scr0_reg_lfsr_two_12_ ( + .CE(plm_scr0_reg_lfsr_one32_i), + .C(mgt_clk), + .D(plm_scr0_N_69424_i), + .Q(plm_scr0_reg_lfsr_two_12__599), + .CLR(plm_rst) + ); + FDPE plm_scr0_reg_lfsr_two_11_ ( + .PRE(plm_rst), + .CE(plm_scr0_reg_lfsr_one32_i), + .C(mgt_clk), + .D(plm_scr0_N_67813_i), + .Q(plm_scr0_reg_lfsr_two_11__372) + ); + FDCE plm_scr0_reg_lfsr_two_10_ ( + .CE(plm_scr0_reg_lfsr_one32_i), + .C(mgt_clk), + .D(plm_scr0_N_69423_i), + .Q(plm_scr0_reg_lfsr_two_10__600), + .CLR(plm_rst) + ); + FDCE plm_scr0_reg_lfsr_two_9_ ( + .CE(plm_scr0_reg_lfsr_one32_i), + .C(mgt_clk), + .D(plm_scr0_N_67812_i), + .Q(plm_scr0_reg_lfsr_two_9__601), + .CLR(plm_rst) + ); + FDCE plm_scr0_reg_lfsr_two_8_ ( + .CE(plm_scr0_reg_lfsr_one32_i), + .C(mgt_clk), + .D(plm_scr0_N_67811_i), + .Q(plm_scr0_reg_lfsr_two_8__602), + .CLR(plm_rst) + ); + FDCE plm_scr0_reg_lfsr_two_7_ ( + .CE(plm_scr0_reg_lfsr_one32_i), + .C(mgt_clk), + .D(plm_scr0_N_69422_i), + .Q(plm_scr0_reg_lfsr_two_7__603), + .CLR(plm_rst) + ); + FDCE plm_scr0_reg_lfsr_two_6_ ( + .CE(plm_scr0_reg_lfsr_one32_i), + .C(mgt_clk), + .D(plm_scr0_N_8756_i), + .Q(plm_scr0_reg_lfsr_two_6__604), + .CLR(plm_rst) + ); + FDCE plm_scr0_reg_lfsr_two_5_ ( + .CE(plm_scr0_reg_lfsr_one32_i), + .C(mgt_clk), + .D(plm_scr0_N_67810_i), + .Q(plm_scr0_reg_lfsr_two_5__605), + .CLR(plm_rst) + ); + FDPE plm_scr0_reg_lfsr_two_4_ ( + .PRE(plm_rst), + .CE(plm_scr0_reg_lfsr_one32_i), + .C(mgt_clk), + .D(plm_scr0_N_67809_i), + .Q(plm_scr0_reg_lfsr_two_4__382) + ); + FDCE plm_scr0_reg_lfsr_two_3_ ( + .CE(plm_scr0_reg_lfsr_one32_i), + .C(mgt_clk), + .D(plm_scr0_N_67808_i), + .Q(plm_scr0_reg_lfsr_two_3__606), + .CLR(plm_rst) + ); + FDPE plm_scr0_reg_lfsr_two_2_ ( + .PRE(plm_rst), + .CE(plm_scr0_reg_lfsr_one32_i), + .C(mgt_clk), + .D(plm_scr0_N_67807_i), + .Q(plm_scr0_reg_lfsr_two_2__607) + ); + FDPE plm_scr0_reg_lfsr_two_1_ ( + .PRE(plm_rst), + .CE(plm_scr0_reg_lfsr_one32_i), + .C(mgt_clk), + .D(plm_scr0_N_67806_i), + .Q(plm_scr0_reg_lfsr_two_1__608) + ); + FDPE plm_scr0_reg_lfsr_two_0_ ( + .PRE(plm_rst), + .CE(plm_scr0_reg_lfsr_one32_i), + .C(mgt_clk), + .D(plm_scr0_N_67805_i), + .Q(plm_scr0_reg_lfsr_two_0__371) + ); + VCC plm_tsi0_VCC ( + .P(plm_tsi0_VCC_681) + ); + GND plm_tsi0_GND ( + .G(plm_tsi0_GND_682) + ); + SRL16 plm_tsi0_D00 ( + .D(plm_rx0_raw_dat[0]), + .Q(plm_tsi0_do[0]), + .CLK(mgt_clk), + .A0(plm_tsi0_VCC_681), + .A1(plm_tsi0_GND_682), + .A2(plm_tsi0_VCC_681), + .A3(plm_tsi0_GND_682) + ); + SRL16 plm_tsi0_D01 ( + .D(plm_rx0_raw_dat[1]), + .Q(plm_tsi0_do[1]), + .CLK(mgt_clk), + .A0(plm_tsi0_VCC_681), + .A1(plm_tsi0_GND_682), + .A2(plm_tsi0_VCC_681), + .A3(plm_tsi0_GND_682) + ); + SRL16 plm_tsi0_D02 ( + .D(plm_rx0_raw_dat[2]), + .Q(plm_tsi0_do[2]), + .CLK(mgt_clk), + .A0(plm_tsi0_VCC_681), + .A1(plm_tsi0_GND_682), + .A2(plm_tsi0_VCC_681), + .A3(plm_tsi0_GND_682) + ); + SRL16 plm_tsi0_D03 ( + .D(plm_rx0_raw_dat[3]), + .Q(plm_tsi0_do[3]), + .CLK(mgt_clk), + .A0(plm_tsi0_VCC_681), + .A1(plm_tsi0_GND_682), + .A2(plm_tsi0_VCC_681), + .A3(plm_tsi0_GND_682) + ); + SRL16 plm_tsi0_D04 ( + .D(plm_rx0_raw_dat[4]), + .Q(plm_tsi0_do[4]), + .CLK(mgt_clk), + .A0(plm_tsi0_VCC_681), + .A1(plm_tsi0_GND_682), + .A2(plm_tsi0_VCC_681), + .A3(plm_tsi0_GND_682) + ); + SRL16 plm_tsi0_D05 ( + .D(plm_rx0_raw_dat[5]), + .Q(plm_tsi0_do[5]), + .CLK(mgt_clk), + .A0(plm_tsi0_VCC_681), + .A1(plm_tsi0_GND_682), + .A2(plm_tsi0_VCC_681), + .A3(plm_tsi0_GND_682) + ); + SRL16 plm_tsi0_D06 ( + .D(plm_rx0_raw_dat[6]), + .Q(plm_tsi0_do[6]), + .CLK(mgt_clk), + .A0(plm_tsi0_VCC_681), + .A1(plm_tsi0_GND_682), + .A2(plm_tsi0_VCC_681), + .A3(plm_tsi0_GND_682) + ); + SRL16 plm_tsi0_D07 ( + .D(plm_rx0_raw_dat[7]), + .Q(plm_tsi0_do[7]), + .CLK(mgt_clk), + .A0(plm_tsi0_VCC_681), + .A1(plm_tsi0_GND_682), + .A2(plm_tsi0_VCC_681), + .A3(plm_tsi0_GND_682) + ); + SRL16 plm_tsi0_D08 ( + .D(plm_rx0_raw_dat[8]), + .Q(plm_tsi0_do[8]), + .CLK(mgt_clk), + .A0(plm_tsi0_VCC_681), + .A1(plm_tsi0_GND_682), + .A2(plm_tsi0_VCC_681), + .A3(plm_tsi0_GND_682) + ); + SRL16 plm_tsi0_D09 ( + .D(plm_rx0_raw_dat[9]), + .Q(plm_tsi0_do[9]), + .CLK(mgt_clk), + .A0(plm_tsi0_VCC_681), + .A1(plm_tsi0_GND_682), + .A2(plm_tsi0_VCC_681), + .A3(plm_tsi0_GND_682) + ); + SRL16 plm_tsi0_D10 ( + .D(plm_rx0_raw_dat[10]), + .Q(plm_tsi0_do[10]), + .CLK(mgt_clk), + .A0(plm_tsi0_VCC_681), + .A1(plm_tsi0_GND_682), + .A2(plm_tsi0_VCC_681), + .A3(plm_tsi0_GND_682) + ); + SRL16 plm_tsi0_D11 ( + .D(plm_rx0_raw_dat[11]), + .Q(plm_tsi0_do[11]), + .CLK(mgt_clk), + .A0(plm_tsi0_VCC_681), + .A1(plm_tsi0_GND_682), + .A2(plm_tsi0_VCC_681), + .A3(plm_tsi0_GND_682) + ); + SRL16 plm_tsi0_D12 ( + .D(plm_rx0_raw_dat[12]), + .Q(plm_tsi0_do[12]), + .CLK(mgt_clk), + .A0(plm_tsi0_VCC_681), + .A1(plm_tsi0_GND_682), + .A2(plm_tsi0_VCC_681), + .A3(plm_tsi0_GND_682) + ); + SRL16 plm_tsi0_D13 ( + .D(plm_rx0_raw_dat[13]), + .Q(plm_tsi0_do[13]), + .CLK(mgt_clk), + .A0(plm_tsi0_VCC_681), + .A1(plm_tsi0_GND_682), + .A2(plm_tsi0_VCC_681), + .A3(plm_tsi0_GND_682) + ); + SRL16 plm_tsi0_D14 ( + .D(plm_rx0_raw_dat[14]), + .Q(plm_tsi0_do[14]), + .CLK(mgt_clk), + .A0(plm_tsi0_VCC_681), + .A1(plm_tsi0_GND_682), + .A2(plm_tsi0_VCC_681), + .A3(plm_tsi0_GND_682) + ); + SRL16 plm_tsi0_D15 ( + .D(plm_rx0_raw_dat[15]), + .Q(plm_tsi0_do[15]), + .CLK(mgt_clk), + .A0(plm_tsi0_VCC_681), + .A1(plm_tsi0_GND_682), + .A2(plm_tsi0_VCC_681), + .A3(plm_tsi0_GND_682) + ); + defparam plm_tsi0_un2_com_data_jog0.INIT = 4'h1; + LUT2 plm_tsi0_un2_com_data_jog0 ( + .I0(plm_tsi0_reg_dec8_5__662), + .I1(plm_tsi0_reg_dec8_6__660), + .O(plm_tsi0_un2_com_data_jog0_609) + ); + defparam plm_tsi0_un2_recent_ts1.INIT = 16'h0001; + LUT4 plm_tsi0_un2_recent_ts1 ( + .I0(plm_tsi0_reg_ts1_timer[0]), + .I1(plm_tsi0_reg_ts1_timer[1]), + .I2(plm_tsi0_reg_ts1_timer[2]), + .I3(plm_tsi0_reg_ts1_timer[3]), + .O(plm_tsi0_un2_recent_ts1_634) + ); + defparam plm_tsi0_un2_recent_ts2.INIT = 16'h0001; + LUT4 plm_tsi0_un2_recent_ts2 ( + .I0(plm_tsi0_reg_ts2_timer[0]), + .I1(plm_tsi0_reg_ts2_timer[1]), + .I2(plm_tsi0_reg_ts2_timer[2]), + .I3(plm_tsi0_reg_ts2_timer[3]), + .O(plm_tsi0_un2_recent_ts2_637) + ); + defparam plm_tsi0_com_data_jog0_2.INIT = 16'h8880; + LUT4 plm_tsi0_com_data_jog0_2 ( + .I0(plm_tsi0_reg_dec6[5]), + .I1(plm_tsi0_reg_dec6_5074[12]), + .I2(plm_tsi0_reg_dec7_12__655), + .I3(plm_tsi0_reg_dec7_13_), + .O(plm_tsi0_com_data_jog1_2) + ); + defparam plm_tsi0_ts1_inv1_jog1_1_4.INIT = 8'h80; + LUT3_L plm_tsi0_ts1_inv1_jog1_1_4 ( + .I0(plm_tsi0_reg_dec1[2]), + .I1(plm_tsi0_reg_dec1_5073[9]), + .I2(plm_tsi0_reg_dec2_2__644), + .LO(plm_tsi0_ts1_inv1_jog1_1_4_618) + ); + defparam plm_tsi0_ts1_inv1_jog1_1_5.INIT = 16'h8000; + LUT4 plm_tsi0_ts1_inv1_jog1_1_5 ( + .I0(plm_tsi0_reg_dec2_9__652), + .I1(plm_tsi0_reg_dec3_2__675), + .I2(plm_tsi0_reg_dec3_9__667), + .I3(plm_tsi0_reg_dec4_2__676), + .O(plm_tsi0_ts1_inv1_jog1_1_5_617) + ); + defparam plm_tsi0_ts2_inv0_jog0_1_4.INIT = 8'h80; + LUT3_L plm_tsi0_ts2_inv0_jog0_1_4 ( + .I0(plm_tsi0_reg_dec1[3]), + .I1(plm_tsi0_reg_dec1_5073[10]), + .I2(plm_tsi0_reg_dec2_3__643), + .LO(plm_tsi0_ts2_inv0_jog0_1_4_612) + ); + defparam plm_tsi0_ts2_inv0_jog0_1_5.INIT = 16'h8000; + LUT4 plm_tsi0_ts2_inv0_jog0_1_5 ( + .I0(plm_tsi0_reg_dec2_10__651), + .I1(plm_tsi0_reg_dec3_3__673), + .I2(plm_tsi0_reg_dec3_10__665), + .I3(plm_tsi0_reg_dec4_3__674), + .O(plm_tsi0_ts2_inv0_jog0_1_5_611) + ); + defparam plm_tsi0_ts2_inv1_jog0_1_4.INIT = 8'h80; + LUT3_L plm_tsi0_ts2_inv1_jog0_1_4 ( + .I0(plm_tsi0_reg_dec1[4]), + .I1(plm_tsi0_reg_dec1_5073[11]), + .I2(plm_tsi0_reg_dec2_4__654), + .LO(plm_tsi0_ts2_inv1_jog0_1_4_614) + ); + defparam plm_tsi0_ts2_inv1_jog0_1_5.INIT = 16'h8000; + LUT4 plm_tsi0_ts2_inv1_jog0_1_5 ( + .I0(plm_tsi0_reg_dec2_11__650), + .I1(plm_tsi0_reg_dec3_4__671), + .I2(plm_tsi0_reg_dec3_11__663), + .I3(plm_tsi0_reg_dec4_4__672), + .O(plm_tsi0_ts2_inv1_jog0_1_5_613) + ); + defparam plm_tsi0_ts1_inv0_jog1_1_4.INIT = 8'h80; + LUT3_L plm_tsi0_ts1_inv0_jog1_1_4 ( + .I0(plm_tsi0_reg_dec1[1]), + .I1(plm_tsi0_reg_dec1_5073[8]), + .I2(plm_tsi0_reg_dec2_1__645), + .LO(plm_tsi0_ts1_inv0_jog1_1_4_616) + ); + defparam plm_tsi0_ts1_inv0_jog1_1_5.INIT = 16'h8000; + LUT4 plm_tsi0_ts1_inv0_jog1_1_5 ( + .I0(plm_tsi0_reg_dec2_8__653), + .I1(plm_tsi0_reg_dec3_1__677), + .I2(plm_tsi0_reg_dec3_8__669), + .I3(plm_tsi0_reg_dec4_1__678), + .O(plm_tsi0_ts1_inv0_jog1_1_5_615) + ); + defparam plm_tsi0_idle_pair_0_a2_0_a2_0_a4_9.INIT = 16'h0001; + LUT4 plm_tsi0_idle_pair_0_a2_0_a2_0_a4_9 ( + .I0(plm_rx0_des_dat[0]), + .I1(plm_rx0_des_dat[1]), + .I2(plm_rx0_des_dat[6]), + .I3(plm_rx0_des_dat[7]), + .O(plm_tsi0_idle_pair_0_a2_0_a2_0_a4_9_623) + ); + defparam plm_tsi0_idle_pair_0_a2_0_a2_0_a4_10.INIT = 16'h0001; + LUT4 plm_tsi0_idle_pair_0_a2_0_a2_0_a4_10 ( + .I0(plm_rx0_des_dat[4]), + .I1(plm_rx0_des_dat[5]), + .I2(plm_rx0_des_dat[12]), + .I3(plm_rx0_des_dat[13]), + .O(plm_tsi0_idle_pair_0_a2_0_a2_0_a4_10_622) + ); + defparam plm_tsi0_idle_pair_0_a2_0_a2_0_a4_11.INIT = 16'h0001; + LUT4 plm_tsi0_idle_pair_0_a2_0_a2_0_a4_11 ( + .I0(plm_rx0_des_dat[2]), + .I1(plm_rx0_des_dat[3]), + .I2(plm_rx0_des_dat[10]), + .I3(plm_rx0_des_dat[11]), + .O(plm_tsi0_idle_pair_0_a2_0_a2_0_a4_11_621) + ); + defparam plm_tsi0_idle_pair_0_a2_0_a2_0_a4_12.INIT = 16'h0001; + LUT4_L plm_tsi0_idle_pair_0_a2_0_a2_0_a4_12 ( + .I0(plm_rx0_des_dat[8]), + .I1(plm_rx0_des_dat[9]), + .I2(plm_rx0_des_dat[14]), + .I3(plm_rx0_des_dat[15]), + .LO(plm_tsi0_idle_pair_0_a2_0_a2_0_a4_12_610) + ); + defparam plm_tsi0_com_data_jog1_1.INIT = 16'hA800; + LUT4 plm_tsi0_com_data_jog1_1 ( + .I0(plm_tsi0_reg_dec5[12]), + .I1(plm_tsi0_reg_dec7_5__661), + .I2(plm_tsi0_reg_dec7_6_), + .I3(plm_tsi0_reg_dec8_0_), + .O(plm_tsi0_com_data_jog1_1_619) + ); + defparam plm_tsi0_com_data_jog0.INIT = 16'h4000; + LUT4 plm_tsi0_com_data_jog0 ( + .I0(plm_tsi0_un2_com_data_jog0_609), + .I1(plm_tsi0_com_data_jog1_2), + .I2(plm_tsi0_reg_dec7_5__661), + .I3(plm_tsi0_reg_dec8_7_), + .O(plm_tsi0_com_data_jog0_628) + ); + defparam plm_tsi0_idle_pair_0_a2_0_a2_0_a4_13.INIT = 8'h80; + LUT3_L plm_tsi0_idle_pair_0_a2_0_a2_0_a4_13 ( + .I0(plm_rx0_des_sym[0]), + .I1(plm_rx0_des_sym[1]), + .I2(plm_tsi0_idle_pair_0_a2_0_a2_0_a4_12_610), + .LO(plm_tsi0_idle_pair_0_a2_0_a2_0_a4_13_620) + ); + defparam plm_tsi0_reg_ts1_timer_0_sqmuxa.INIT = 8'h01; + LUT3 plm_tsi0_reg_ts1_timer_0_sqmuxa ( + .I0(plm_tsi0_un2_recent_ts1_634), + .I1(plm_rx_clear_cs), + .I2(plm_tsi0_reg_capture_ts1_641), + .O(plm_tsi0_reg_ts1_timer_0_sqmuxa_635) + ); + defparam plm_tsi0_reg_ts2_timer_0_sqmuxa.INIT = 8'h01; + LUT3 plm_tsi0_reg_ts2_timer_0_sqmuxa ( + .I0(plm_tsi0_un2_recent_ts2_637), + .I1(plm_rx_clear_cs), + .I2(plm_tsi0_reg_capture_ts2_640), + .O(plm_tsi0_reg_ts2_timer_0_sqmuxa_638) + ); + defparam plm_tsi0_ts2_inv0_jog0_1.INIT = 16'h8000; + LUT4 plm_tsi0_ts2_inv0_jog0_1 ( + .I0(plm_tsi0_reg_dec4_10__666), + .I1(plm_tsi0_reg_dec5_3__647), + .I2(plm_tsi0_ts2_inv0_jog0_1_4_612), + .I3(plm_tsi0_ts2_inv0_jog0_1_5_611), + .O(plm_tsi0_ts2_inv0_jog0_1_627) + ); + defparam plm_tsi0_ts2_inv1_jog0_1.INIT = 16'h8000; + LUT4 plm_tsi0_ts2_inv1_jog0_1 ( + .I0(plm_tsi0_reg_dec4_11__664), + .I1(plm_tsi0_reg_dec5_4__646), + .I2(plm_tsi0_ts2_inv1_jog0_1_4_614), + .I3(plm_tsi0_ts2_inv1_jog0_1_5_613), + .O(plm_tsi0_ts2_inv1_jog0_1_625) + ); + defparam plm_tsi0_ts1_inv0_jog1_1.INIT = 16'h8000; + LUT4 plm_tsi0_ts1_inv0_jog1_1 ( + .I0(plm_tsi0_reg_dec4_8__670), + .I1(plm_tsi0_reg_dec5_1__649), + .I2(plm_tsi0_ts1_inv0_jog1_1_4_616), + .I3(plm_tsi0_ts1_inv0_jog1_1_5_615), + .O(plm_tsi0_ts1_inv0_jog1_1_626) + ); + defparam plm_tsi0_ts1_inv1_jog1_1.INIT = 16'h8000; + LUT4 plm_tsi0_ts1_inv1_jog1_1 ( + .I0(plm_tsi0_reg_dec4_9__668), + .I1(plm_tsi0_reg_dec5_2__648), + .I2(plm_tsi0_ts1_inv1_jog1_1_4_618), + .I3(plm_tsi0_ts1_inv1_jog1_1_5_617), + .O(plm_tsi0_ts1_inv1_jog1_1_624) + ); + defparam plm_tsi0_un7_reg_ts1_timer_axbxc3.INIT = 16'hFE01; + LUT4 plm_tsi0_un7_reg_ts1_timer_axbxc3 ( + .I0(plm_tsi0_reg_ts1_timer[0]), + .I1(plm_tsi0_reg_ts1_timer[1]), + .I2(plm_tsi0_reg_ts1_timer[2]), + .I3(plm_tsi0_reg_ts1_timer[3]), + .O(plm_tsi0_un7_reg_ts1_timer_axbxc3_633) + ); + defparam plm_tsi0_un7_reg_ts2_timer_axbxc3.INIT = 16'hFE01; + LUT4 plm_tsi0_un7_reg_ts2_timer_axbxc3 ( + .I0(plm_tsi0_reg_ts2_timer[0]), + .I1(plm_tsi0_reg_ts2_timer[1]), + .I2(plm_tsi0_reg_ts2_timer[2]), + .I3(plm_tsi0_reg_ts2_timer[3]), + .O(plm_tsi0_un7_reg_ts2_timer_axbxc3_636) + ); + defparam plm_tsi0_ts2_inv0_jog1.INIT = 16'h8000; + LUT4 plm_tsi0_ts2_inv0_jog1 ( + .I0(plm_rx0_des_t2p[1]), + .I1(plm_tsi0_com_data_jog1_1_619), + .I2(plm_tsi0_com_data_jog1_2), + .I3(plm_tsi0_ts2_inv0_jog0_1_627), + .O(plm_tsi0_ts2_inv0_jog1_630) + ); + defparam plm_tsi0_ts2_inv1_jog1.INIT = 16'h8000; + LUT4 plm_tsi0_ts2_inv1_jog1 ( + .I0(plm_rx0_des_t2n[1]), + .I1(plm_tsi0_com_data_jog1_1_619), + .I2(plm_tsi0_com_data_jog1_2), + .I3(plm_tsi0_ts2_inv1_jog0_1_625), + .O(plm_tsi0_ts2_inv1_jog1_629) + ); + defparam plm_tsi0_ts1_inv0_jog1.INIT = 16'h8000; + LUT4 plm_tsi0_ts1_inv0_jog1 ( + .I0(plm_rx0_des_t1p[1]), + .I1(plm_tsi0_com_data_jog1_1_619), + .I2(plm_tsi0_com_data_jog1_2), + .I3(plm_tsi0_ts1_inv0_jog1_1_626), + .O(plm_tsi0_ts1_inv0_jog1_632) + ); + defparam plm_tsi0_ts1_inv1_jog1.INIT = 16'h8000; + LUT4 plm_tsi0_ts1_inv1_jog1 ( + .I0(plm_rx0_des_t1n[1]), + .I1(plm_tsi0_com_data_jog1_1_619), + .I2(plm_tsi0_com_data_jog1_2), + .I3(plm_tsi0_ts1_inv1_jog1_1_624), + .O(plm_tsi0_ts1_inv1_jog1_631) + ); + defparam plm_tsi0_idle_pair_0_a2_0_a2_0_a4.INIT = 16'h8000; + LUT4 plm_tsi0_idle_pair_0_a2_0_a2_0_a4 ( + .I0(plm_tsi0_idle_pair_0_a2_0_a2_0_a4_9_623), + .I1(plm_tsi0_idle_pair_0_a2_0_a2_0_a4_10_622), + .I2(plm_tsi0_idle_pair_0_a2_0_a2_0_a4_11_621), + .I3(plm_tsi0_idle_pair_0_a2_0_a2_0_a4_13_620), + .O(plm_tsi0_idle_pair) + ); + defparam plm_tsi0_what_it_is_reg_capture_inv_3_5594.INIT = 16'h070F; + LUT4 plm_tsi0_what_it_is_reg_capture_inv_3_5594 ( + .I0(plm_tsi0_com_data_jog0_628), + .I1(plm_tsi0_reg_dec5_9__658), + .I2(plm_tsi0_ts1_inv1_jog1_631), + .I3(plm_tsi0_ts1_inv1_jog1_1_624), + .O(plm_tsi0_reg_capture_inv_3_5594) + ); + defparam plm_tsi0_what_it_is_reg_capture_inv_3_5595.INIT = 16'h007F; + LUT4 plm_tsi0_what_it_is_reg_capture_inv_3_5595 ( + .I0(plm_tsi0_com_data_jog0_628), + .I1(plm_tsi0_reg_dec5_11__656), + .I2(plm_tsi0_ts2_inv1_jog0_1_625), + .I3(plm_tsi0_ts2_inv1_jog1_629), + .O(plm_tsi0_reg_capture_inv_3_5595) + ); + defparam plm_tsi0_what_it_is_reg_capture_ts1_3_0.INIT = 16'h070F; + LUT4 plm_tsi0_what_it_is_reg_capture_ts1_3_0 ( + .I0(plm_tsi0_com_data_jog0_628), + .I1(plm_tsi0_reg_dec5_8__659), + .I2(plm_tsi0_ts1_inv0_jog1_632), + .I3(plm_tsi0_ts1_inv0_jog1_1_626), + .O(plm_tsi0_reg_capture_ts1_3_0) + ); + defparam plm_tsi0_what_it_is_reg_capture_ts2_3_0.INIT = 16'h007F; + LUT4 plm_tsi0_what_it_is_reg_capture_ts2_3_0 ( + .I0(plm_tsi0_com_data_jog0_628), + .I1(plm_tsi0_reg_dec5_10__657), + .I2(plm_tsi0_ts2_inv0_jog0_1_627), + .I3(plm_tsi0_ts2_inv0_jog1_630), + .O(plm_tsi0_reg_capture_ts2_3_0) + ); + defparam plm_tsi0_event_regs_reg_ts2_c_3.INIT = 8'h10; + LUT3_L plm_tsi0_event_regs_reg_ts2_c_3 ( + .I0(plm_tsi0_un2_recent_ts2_637), + .I1(plm_rx_clear_cs), + .I2(plm_tsi0_reg_capture_ts2_640), + .LO(plm_tsi0_reg_ts2_c_3) + ); + defparam plm_tsi0_event_regs_reg_ts1_c_3.INIT = 8'h10; + LUT3_L plm_tsi0_event_regs_reg_ts1_c_3 ( + .I0(plm_tsi0_un2_recent_ts1_634), + .I1(plm_rx_clear_cs), + .I2(plm_tsi0_reg_capture_ts1_641), + .LO(plm_tsi0_reg_ts1_c_3) + ); + defparam plm_tsi0_what_it_is_N_9992_i.INIT = 16'h7FFF; + LUT4_L plm_tsi0_what_it_is_N_9992_i ( + .I0(plm_tsi0_reg_capture_inv_3_5594), + .I1(plm_tsi0_reg_capture_inv_3_5595), + .I2(plm_tsi0_reg_capture_ts1_3_0), + .I3(plm_tsi0_reg_capture_ts2_3_0), + .LO(plm_tsi0_N_9992_i) + ); + defparam plm_tsi0_what_it_is_N_9993_i.INIT = 4'h7; + LUT2_L plm_tsi0_what_it_is_N_9993_i ( + .I0(plm_tsi0_reg_capture_inv_3_5595), + .I1(plm_tsi0_reg_capture_ts2_3_0), + .LO(plm_tsi0_N_9993_i) + ); + defparam plm_tsi0_what_it_is_N_9994_i.INIT = 4'h7; + LUT2_L plm_tsi0_what_it_is_N_9994_i ( + .I0(plm_tsi0_reg_capture_inv_3_5594), + .I1(plm_tsi0_reg_capture_ts1_3_0), + .LO(plm_tsi0_N_9994_i) + ); + defparam plm_tsi0_what_it_is_N_9996_i.INIT = 16'hFFFE; + LUT4_L plm_tsi0_what_it_is_N_9996_i ( + .I0(plm_tsi0_ts1_inv0_jog1_632), + .I1(plm_tsi0_ts1_inv1_jog1_631), + .I2(plm_tsi0_ts2_inv0_jog1_630), + .I3(plm_tsi0_ts2_inv1_jog1_629), + .LO(plm_tsi0_N_9996_i) + ); + defparam plm_tsi0_what_it_is_N_9995_i.INIT = 4'h7; + LUT2_L plm_tsi0_what_it_is_N_9995_i ( + .I0(plm_tsi0_reg_capture_inv_3_5594), + .I1(plm_tsi0_reg_capture_inv_3_5595), + .LO(plm_tsi0_N_9995_i) + ); + defparam plm_tsi0_idle_hands_reg_rx_idl_c_3_0_a2_0_a2_0_a4.INIT = 4'h8; + LUT2_L plm_tsi0_idle_hands_reg_rx_idl_c_3_0_a2_0_a2_0_a4 ( + .I0(plm_reg_rx_idl_1), + .I1(plm_tsi0_idle_pair), + .LO(plm_tsi0_reg_rx_idl_c_3) + ); + defparam plm_tsi0_event_regs_reg_ts2_timer_5_0_.INIT = 4'h4; + LUT2_L plm_tsi0_event_regs_reg_ts2_timer_5_0_ ( + .I0(plm_tsi0_reg_ts2_timer[0]), + .I1(plm_tsi0_reg_ts2_timer_0_sqmuxa_638), + .LO(plm_tsi0_reg_ts2_timer_5[0]) + ); + defparam plm_tsi0_event_regs_reg_ts1_timer_5_f0_3_.INIT = 16'hF1F0; + LUT4_L plm_tsi0_event_regs_reg_ts1_timer_5_f0_3_ ( + .I0(plm_tsi0_un2_recent_ts1_634), + .I1(plm_rx_clear_cs), + .I2(plm_tsi0_reg_capture_ts1_641), + .I3(plm_tsi0_un7_reg_ts1_timer_axbxc3_633), + .LO(plm_tsi0_reg_ts1_timer_5[3]) + ); + defparam plm_tsi0_event_regs_reg_ts1_timer_5_2_.INIT = 16'hE100; + LUT4_L plm_tsi0_event_regs_reg_ts1_timer_5_2_ ( + .I0(plm_tsi0_reg_ts1_timer[0]), + .I1(plm_tsi0_reg_ts1_timer[1]), + .I2(plm_tsi0_reg_ts1_timer[2]), + .I3(plm_tsi0_reg_ts1_timer_0_sqmuxa_635), + .LO(plm_tsi0_reg_ts1_timer_5[2]) + ); + defparam plm_tsi0_event_regs_reg_ts1_timer_5_1_.INIT = 8'h90; + LUT3_L plm_tsi0_event_regs_reg_ts1_timer_5_1_ ( + .I0(plm_tsi0_reg_ts1_timer[0]), + .I1(plm_tsi0_reg_ts1_timer[1]), + .I2(plm_tsi0_reg_ts1_timer_0_sqmuxa_635), + .LO(plm_tsi0_reg_ts1_timer_5[1]) + ); + defparam plm_tsi0_event_regs_reg_ts1_timer_5_0_.INIT = 4'h4; + LUT2_L plm_tsi0_event_regs_reg_ts1_timer_5_0_ ( + .I0(plm_tsi0_reg_ts1_timer[0]), + .I1(plm_tsi0_reg_ts1_timer_0_sqmuxa_635), + .LO(plm_tsi0_reg_ts1_timer_5[0]) + ); + defparam plm_tsi0_event_regs_reg_ts2_timer_5_f0_3_.INIT = 16'hF1F0; + LUT4_L plm_tsi0_event_regs_reg_ts2_timer_5_f0_3_ ( + .I0(plm_tsi0_un2_recent_ts2_637), + .I1(plm_rx_clear_cs), + .I2(plm_tsi0_reg_capture_ts2_640), + .I3(plm_tsi0_un7_reg_ts2_timer_axbxc3_636), + .LO(plm_tsi0_reg_ts2_timer_5[3]) + ); + defparam plm_tsi0_event_regs_reg_ts2_timer_5_2_.INIT = 16'hE100; + LUT4_L plm_tsi0_event_regs_reg_ts2_timer_5_2_ ( + .I0(plm_tsi0_reg_ts2_timer[0]), + .I1(plm_tsi0_reg_ts2_timer[1]), + .I2(plm_tsi0_reg_ts2_timer[2]), + .I3(plm_tsi0_reg_ts2_timer_0_sqmuxa_638), + .LO(plm_tsi0_reg_ts2_timer_5[2]) + ); + defparam plm_tsi0_event_regs_reg_ts2_timer_5_1_.INIT = 8'h90; + LUT3_L plm_tsi0_event_regs_reg_ts2_timer_5_1_ ( + .I0(plm_tsi0_reg_ts2_timer[0]), + .I1(plm_tsi0_reg_ts2_timer[1]), + .I2(plm_tsi0_reg_ts2_timer_0_sqmuxa_638), + .LO(plm_tsi0_reg_ts2_timer_5[1]) + ); + defparam plm_tsi0_holding_regs_reg_lane_pad_3_0.INIT = 8'hD8; + LUT3_L plm_tsi0_holding_regs_reg_lane_pad_3_0 ( + .I0(plm_tsi0_reg_capture_jog_642), + .I1(plm_tsi0_reg_dec8_6__660), + .I2(plm_tsi0_reg_dec8_13__639), + .LO(plm_tsi0_reg_lane_pad_3) + ); + defparam plm_tsi0_holding_regs_reg_link_pad_3_0.INIT = 8'hD8; + LUT3_L plm_tsi0_holding_regs_reg_link_pad_3_0 ( + .I0(plm_tsi0_reg_capture_jog_642), + .I1(plm_tsi0_reg_dec8_13__639), + .I2(plm_tsi0_reg_dec9[6]), + .LO(plm_tsi0_reg_link_pad_3) + ); + defparam plm_tsi0_holding_regs_reg_lane_num_3_7_.INIT = 16'h596A; + LUT4_L plm_tsi0_holding_regs_reg_lane_num_3_7_ ( + .I0(plm_tsi0_reg_capture_inv_679), + .I1(plm_tsi0_reg_capture_jog_642), + .I2(plm_tsi0_reg_dly8[7]), + .I3(plm_tsi0_reg_dly8[15]), + .LO(plm_tsi0_reg_lane_num_3[7]) + ); + defparam plm_tsi0_holding_regs_reg_lane_num_3_6_.INIT = 16'h596A; + LUT4_L plm_tsi0_holding_regs_reg_lane_num_3_6_ ( + .I0(plm_tsi0_reg_capture_inv_679), + .I1(plm_tsi0_reg_capture_jog_642), + .I2(plm_tsi0_reg_dly8[6]), + .I3(plm_tsi0_reg_dly8[14]), + .LO(plm_tsi0_reg_lane_num_3[6]) + ); + defparam plm_tsi0_holding_regs_reg_lane_num_3_5_.INIT = 16'h596A; + LUT4_L plm_tsi0_holding_regs_reg_lane_num_3_5_ ( + .I0(plm_tsi0_reg_capture_inv_679), + .I1(plm_tsi0_reg_capture_jog_642), + .I2(plm_tsi0_reg_dly8[5]), + .I3(plm_tsi0_reg_dly8[13]), + .LO(plm_tsi0_reg_lane_num_3[5]) + ); + defparam plm_tsi0_holding_regs_reg_lane_num_3_4_.INIT = 16'h596A; + LUT4_L plm_tsi0_holding_regs_reg_lane_num_3_4_ ( + .I0(plm_tsi0_reg_capture_inv_679), + .I1(plm_tsi0_reg_capture_jog_642), + .I2(plm_tsi0_reg_dly8[4]), + .I3(plm_tsi0_reg_dly8[12]), + .LO(plm_tsi0_reg_lane_num_3[4]) + ); + defparam plm_tsi0_holding_regs_reg_lane_num_3_3_.INIT = 16'h596A; + LUT4_L plm_tsi0_holding_regs_reg_lane_num_3_3_ ( + .I0(plm_tsi0_reg_capture_inv_679), + .I1(plm_tsi0_reg_capture_jog_642), + .I2(plm_tsi0_reg_dly8[3]), + .I3(plm_tsi0_reg_dly8[11]), + .LO(plm_tsi0_reg_lane_num_3[3]) + ); + defparam plm_tsi0_holding_regs_reg_lane_num_3_2_.INIT = 16'h596A; + LUT4_L plm_tsi0_holding_regs_reg_lane_num_3_2_ ( + .I0(plm_tsi0_reg_capture_inv_679), + .I1(plm_tsi0_reg_capture_jog_642), + .I2(plm_tsi0_reg_dly8[2]), + .I3(plm_tsi0_reg_dly8[10]), + .LO(plm_tsi0_reg_lane_num_3[2]) + ); + defparam plm_tsi0_holding_regs_reg_lane_num_3_1_.INIT = 16'h596A; + LUT4_L plm_tsi0_holding_regs_reg_lane_num_3_1_ ( + .I0(plm_tsi0_reg_capture_inv_679), + .I1(plm_tsi0_reg_capture_jog_642), + .I2(plm_tsi0_reg_dly8[1]), + .I3(plm_tsi0_reg_dly8[9]), + .LO(plm_tsi0_reg_lane_num_3[1]) + ); + defparam plm_tsi0_holding_regs_reg_lane_num_3_0_.INIT = 16'h596A; + LUT4_L plm_tsi0_holding_regs_reg_lane_num_3_0_ ( + .I0(plm_tsi0_reg_capture_inv_679), + .I1(plm_tsi0_reg_capture_jog_642), + .I2(plm_tsi0_reg_dly8[0]), + .I3(plm_tsi0_reg_dly8[8]), + .LO(plm_tsi0_reg_lane_num_3[0]) + ); + defparam plm_tsi0_holding_regs_reg_link_num_3_7_.INIT = 16'h596A; + LUT4_L plm_tsi0_holding_regs_reg_link_num_3_7_ ( + .I0(plm_tsi0_reg_capture_inv_679), + .I1(plm_tsi0_reg_capture_jog_642), + .I2(plm_tsi0_reg_dly8[15]), + .I3(plm_tsi0_reg_dly9[7]), + .LO(plm_tsi0_reg_link_num_3[7]) + ); + defparam plm_tsi0_holding_regs_reg_link_num_3_6_.INIT = 16'h596A; + LUT4_L plm_tsi0_holding_regs_reg_link_num_3_6_ ( + .I0(plm_tsi0_reg_capture_inv_679), + .I1(plm_tsi0_reg_capture_jog_642), + .I2(plm_tsi0_reg_dly8[14]), + .I3(plm_tsi0_reg_dly9[6]), + .LO(plm_tsi0_reg_link_num_3[6]) + ); + defparam plm_tsi0_holding_regs_reg_link_num_3_5_.INIT = 16'h596A; + LUT4_L plm_tsi0_holding_regs_reg_link_num_3_5_ ( + .I0(plm_tsi0_reg_capture_inv_679), + .I1(plm_tsi0_reg_capture_jog_642), + .I2(plm_tsi0_reg_dly8[13]), + .I3(plm_tsi0_reg_dly9[5]), + .LO(plm_tsi0_reg_link_num_3[5]) + ); + defparam plm_tsi0_holding_regs_reg_link_num_3_4_.INIT = 16'h596A; + LUT4_L plm_tsi0_holding_regs_reg_link_num_3_4_ ( + .I0(plm_tsi0_reg_capture_inv_679), + .I1(plm_tsi0_reg_capture_jog_642), + .I2(plm_tsi0_reg_dly8[12]), + .I3(plm_tsi0_reg_dly9[4]), + .LO(plm_tsi0_reg_link_num_3[4]) + ); + defparam plm_tsi0_holding_regs_reg_link_num_3_3_.INIT = 16'h596A; + LUT4_L plm_tsi0_holding_regs_reg_link_num_3_3_ ( + .I0(plm_tsi0_reg_capture_inv_679), + .I1(plm_tsi0_reg_capture_jog_642), + .I2(plm_tsi0_reg_dly8[11]), + .I3(plm_tsi0_reg_dly9[3]), + .LO(plm_tsi0_reg_link_num_3[3]) + ); + defparam plm_tsi0_holding_regs_reg_link_num_3_2_.INIT = 16'h596A; + LUT4_L plm_tsi0_holding_regs_reg_link_num_3_2_ ( + .I0(plm_tsi0_reg_capture_inv_679), + .I1(plm_tsi0_reg_capture_jog_642), + .I2(plm_tsi0_reg_dly8[10]), + .I3(plm_tsi0_reg_dly9[2]), + .LO(plm_tsi0_reg_link_num_3[2]) + ); + defparam plm_tsi0_holding_regs_reg_link_num_3_1_.INIT = 16'h596A; + LUT4_L plm_tsi0_holding_regs_reg_link_num_3_1_ ( + .I0(plm_tsi0_reg_capture_inv_679), + .I1(plm_tsi0_reg_capture_jog_642), + .I2(plm_tsi0_reg_dly8[9]), + .I3(plm_tsi0_reg_dly9[1]), + .LO(plm_tsi0_reg_link_num_3[1]) + ); + defparam plm_tsi0_holding_regs_reg_link_num_3_0_.INIT = 16'h596A; + LUT4_L plm_tsi0_holding_regs_reg_link_num_3_0_ ( + .I0(plm_tsi0_reg_capture_inv_679), + .I1(plm_tsi0_reg_capture_jog_642), + .I2(plm_tsi0_reg_dly8[8]), + .I3(plm_tsi0_reg_dly9[0]), + .LO(plm_tsi0_reg_link_num_3[0]) + ); + defparam plm_tsi0_holding_regs_reg_linkctrl_3_3_.INIT = 16'h636C; + LUT4_L plm_tsi0_holding_regs_reg_linkctrl_3_3_ ( + .I0(plm_tsi0_do[11]), + .I1(plm_tsi0_reg_capture_inv_679), + .I2(plm_tsi0_reg_capture_jog_642), + .I3(plm_tsi0_reg_dly7[3]), + .LO(plm_tsi0_reg_linkctrl_3_3_) + ); + defparam plm_tsi0_holding_regs_reg_linkctrl_3_0_.INIT = 16'h636C; + LUT4_L plm_tsi0_holding_regs_reg_linkctrl_3_0_ ( + .I0(plm_tsi0_do[8]), + .I1(plm_tsi0_reg_capture_inv_679), + .I2(plm_tsi0_reg_capture_jog_642), + .I3(plm_tsi0_reg_dly7[0]), + .LO(plm_tsi0_reg_linkctrl_3_0_) + ); + FD plm_tsi0_reg_dec8_0_DOUT_0_ ( + .C(mgt_clk), + .D(plm_tsi0_reg_dec8_0_N_6), + .Q(plm_tsi0_reg_dec8_0_DOUT[0]) + ); + FD plm_tsi0_reg_dec7_0_DOUT_0_ ( + .C(mgt_clk), + .D(plm_tsi0_reg_dec7_0_N_6), + .Q(plm_tsi0_reg_dec7_0_DOUT[0]) + ); + FD plm_tsi0_reg_dec7_DOUT_0_ ( + .C(mgt_clk), + .D(plm_tsi0_reg_dec7_tmp_d_array_0[0]), + .Q(plm_tsi0_reg_dec7_DOUT[0]) + ); + FD plm_tsi0_reg_dec5_DOUT_0_ ( + .C(mgt_clk), + .D(plm_tsi0_reg_dec5_tmp_d_array_0[0]), + .Q(plm_tsi0_reg_dec5_DOUT[0]) + ); + FD plm_tsi0_reg_dec6_DOUT_0_ ( + .C(mgt_clk), + .D(plm_tsi0_reg_dec6_tmp_d_array_0[0]), + .Q(plm_tsi0_reg_dec6_DOUT[0]) + ); + FD plm_tsi0_reg_dec1_2_DOUT_0_ ( + .C(mgt_clk), + .D(plm_tsi0_reg_dec1_2_N_6), + .Q(plm_tsi0_reg_dec1_2_DOUT[0]) + ); + FD plm_tsi0_reg_dec1_1_DOUT_0_ ( + .C(mgt_clk), + .D(plm_tsi0_reg_dec1_1_N_6), + .Q(plm_tsi0_reg_dec1_1_DOUT[0]) + ); + FD plm_tsi0_reg_dec1_0_DOUT_0_ ( + .C(mgt_clk), + .D(plm_tsi0_reg_dec1_0_N_6), + .Q(plm_tsi0_reg_dec1_0_DOUT[0]) + ); + FD plm_tsi0_reg_dec1_DOUT_0_ ( + .C(mgt_clk), + .D(plm_tsi0_reg_dec1_N_6), + .Q(plm_tsi0_reg_dec1_DOUT[0]) + ); + FD plm_tsi0_reg_dec8_DOUT_0_ ( + .C(mgt_clk), + .D(plm_tsi0_reg_dec8_tmp_d_array_0[0]), + .Q(plm_tsi0_reg_dec8_DOUT[0]) + ); + FDC plm_tsi0_reg_dec8_13_ ( + .C(mgt_clk), + .D(plm_tsi0_reg_dec7_13_), + .Q(plm_tsi0_reg_dec8_13__639), + .CLR(plm_rst) + ); + FDC plm_tsi0_reg_dec9_6_ ( + .C(mgt_clk), + .D(plm_tsi0_reg_dec8_6__660), + .Q(plm_tsi0_reg_dec9[6]), + .CLR(plm_rst) + ); + FDC plm_tsi0_reg_rx_idl_1 ( + .C(mgt_clk), + .D(plm_tsi0_idle_pair), + .Q(plm_reg_rx_idl_1), + .CLR(plm_rst) + ); + FDC plm_tsi0_reg_ts2_c ( + .C(mgt_clk), + .D(plm_tsi0_reg_ts2_c_3), + .Q(plm_rx0_ts2_c), + .CLR(plm_rst) + ); + FDC plm_tsi0_reg_ts1_c ( + .C(mgt_clk), + .D(plm_tsi0_reg_ts1_c_3), + .Q(plm_rx0_ts1_c), + .CLR(plm_rst) + ); + FDC plm_tsi0_reg_ts2_1 ( + .C(mgt_clk), + .D(plm_tsi0_reg_capture_ts2_640), + .Q(plm_reg_ts2_1), + .CLR(plm_rst) + ); + FDC plm_tsi0_reg_ts1_1 ( + .C(mgt_clk), + .D(plm_tsi0_reg_capture_ts1_641), + .Q(plm_reg_ts1_1), + .CLR(plm_rst) + ); + FDC plm_tsi0_reg_capture_now ( + .C(mgt_clk), + .D(plm_tsi0_N_9992_i), + .Q(plm_tsi0_reg_capture_now_680), + .CLR(plm_rst) + ); + FDC plm_tsi0_reg_capture_ts2 ( + .C(mgt_clk), + .D(plm_tsi0_N_9993_i), + .Q(plm_tsi0_reg_capture_ts2_640), + .CLR(plm_rst) + ); + FDC plm_tsi0_reg_capture_ts1 ( + .C(mgt_clk), + .D(plm_tsi0_N_9994_i), + .Q(plm_tsi0_reg_capture_ts1_641), + .CLR(plm_rst) + ); + FDC plm_tsi0_reg_capture_jog ( + .C(mgt_clk), + .D(plm_tsi0_N_9996_i), + .Q(plm_tsi0_reg_capture_jog_642), + .CLR(plm_rst) + ); + FDC plm_tsi0_reg_capture_inv ( + .C(mgt_clk), + .D(plm_tsi0_N_9995_i), + .Q(plm_tsi0_reg_capture_inv_679), + .CLR(plm_rst) + ); + FDC plm_tsi0_reg_rx_idl_c ( + .C(mgt_clk), + .D(plm_tsi0_reg_rx_idl_c_3), + .Q(plm_rx0_idl_c), + .CLR(plm_rst) + ); + FDC plm_tsi0_reg_ts2_timer_0_ ( + .C(mgt_clk), + .D(plm_tsi0_reg_ts2_timer_5[0]), + .Q(plm_tsi0_reg_ts2_timer[0]), + .CLR(plm_rst) + ); + FDC plm_tsi0_reg_ts1_timer_3_ ( + .C(mgt_clk), + .D(plm_tsi0_reg_ts1_timer_5[3]), + .Q(plm_tsi0_reg_ts1_timer[3]), + .CLR(plm_rst) + ); + FDC plm_tsi0_reg_ts1_timer_2_ ( + .C(mgt_clk), + .D(plm_tsi0_reg_ts1_timer_5[2]), + .Q(plm_tsi0_reg_ts1_timer[2]), + .CLR(plm_rst) + ); + FDC plm_tsi0_reg_ts1_timer_1_ ( + .C(mgt_clk), + .D(plm_tsi0_reg_ts1_timer_5[1]), + .Q(plm_tsi0_reg_ts1_timer[1]), + .CLR(plm_rst) + ); + FDC plm_tsi0_reg_ts1_timer_0_ ( + .C(mgt_clk), + .D(plm_tsi0_reg_ts1_timer_5[0]), + .Q(plm_tsi0_reg_ts1_timer[0]), + .CLR(plm_rst) + ); + FDC plm_tsi0_reg_ts2_timer_3_ ( + .C(mgt_clk), + .D(plm_tsi0_reg_ts2_timer_5[3]), + .Q(plm_tsi0_reg_ts2_timer[3]), + .CLR(plm_rst) + ); + FDC plm_tsi0_reg_ts2_timer_2_ ( + .C(mgt_clk), + .D(plm_tsi0_reg_ts2_timer_5[2]), + .Q(plm_tsi0_reg_ts2_timer[2]), + .CLR(plm_rst) + ); + FDC plm_tsi0_reg_ts2_timer_1_ ( + .C(mgt_clk), + .D(plm_tsi0_reg_ts2_timer_5[1]), + .Q(plm_tsi0_reg_ts2_timer[1]), + .CLR(plm_rst) + ); + FDC plm_tsi0_reg_dly8_8_ ( + .C(mgt_clk), + .D(plm_tsi0_reg_dly7[8]), + .Q(plm_tsi0_reg_dly8[8]), + .CLR(plm_rst) + ); + FDC plm_tsi0_reg_dly8_7_ ( + .C(mgt_clk), + .D(plm_tsi0_reg_dly7[7]), + .Q(plm_tsi0_reg_dly8[7]), + .CLR(plm_rst) + ); + FDC plm_tsi0_reg_dly8_6_ ( + .C(mgt_clk), + .D(plm_tsi0_reg_dly7[6]), + .Q(plm_tsi0_reg_dly8[6]), + .CLR(plm_rst) + ); + FDC plm_tsi0_reg_dly8_5_ ( + .C(mgt_clk), + .D(plm_tsi0_reg_dly7[5]), + .Q(plm_tsi0_reg_dly8[5]), + .CLR(plm_rst) + ); + FDC plm_tsi0_reg_dly8_4_ ( + .C(mgt_clk), + .D(plm_tsi0_reg_dly7[4]), + .Q(plm_tsi0_reg_dly8[4]), + .CLR(plm_rst) + ); + FDC plm_tsi0_reg_dly8_3_ ( + .C(mgt_clk), + .D(plm_tsi0_reg_dly7[3]), + .Q(plm_tsi0_reg_dly8[3]), + .CLR(plm_rst) + ); + FDC plm_tsi0_reg_dly8_2_ ( + .C(mgt_clk), + .D(plm_tsi0_reg_dly7[2]), + .Q(plm_tsi0_reg_dly8[2]), + .CLR(plm_rst) + ); + FDC plm_tsi0_reg_dly8_1_ ( + .C(mgt_clk), + .D(plm_tsi0_reg_dly7[1]), + .Q(plm_tsi0_reg_dly8[1]), + .CLR(plm_rst) + ); + FDC plm_tsi0_reg_dly8_0_ ( + .C(mgt_clk), + .D(plm_tsi0_reg_dly7[0]), + .Q(plm_tsi0_reg_dly8[0]), + .CLR(plm_rst) + ); + FDC plm_tsi0_reg_dec2_4_ ( + .C(mgt_clk), + .D(plm_tsi0_reg_dec1[4]), + .Q(plm_tsi0_reg_dec2_4__654), + .CLR(plm_rst) + ); + FDC plm_tsi0_reg_dec2_3_ ( + .C(mgt_clk), + .D(plm_tsi0_reg_dec1[3]), + .Q(plm_tsi0_reg_dec2_3__643), + .CLR(plm_rst) + ); + FDC plm_tsi0_reg_dec2_2_ ( + .C(mgt_clk), + .D(plm_tsi0_reg_dec1[2]), + .Q(plm_tsi0_reg_dec2_2__644), + .CLR(plm_rst) + ); + FDC plm_tsi0_reg_dec2_1_ ( + .C(mgt_clk), + .D(plm_tsi0_reg_dec1[1]), + .Q(plm_tsi0_reg_dec2_1__645), + .CLR(plm_rst) + ); + FDC plm_tsi0_reg_dly8_15_ ( + .C(mgt_clk), + .D(plm_tsi0_reg_dly7[15]), + .Q(plm_tsi0_reg_dly8[15]), + .CLR(plm_rst) + ); + FDC plm_tsi0_reg_dly8_14_ ( + .C(mgt_clk), + .D(plm_tsi0_reg_dly7[14]), + .Q(plm_tsi0_reg_dly8[14]), + .CLR(plm_rst) + ); + FDC plm_tsi0_reg_dly8_13_ ( + .C(mgt_clk), + .D(plm_tsi0_reg_dly7[13]), + .Q(plm_tsi0_reg_dly8[13]), + .CLR(plm_rst) + ); + FDC plm_tsi0_reg_dly8_12_ ( + .C(mgt_clk), + .D(plm_tsi0_reg_dly7[12]), + .Q(plm_tsi0_reg_dly8[12]), + .CLR(plm_rst) + ); + FDC plm_tsi0_reg_dly8_11_ ( + .C(mgt_clk), + .D(plm_tsi0_reg_dly7[11]), + .Q(plm_tsi0_reg_dly8[11]), + .CLR(plm_rst) + ); + FDC plm_tsi0_reg_dly8_10_ ( + .C(mgt_clk), + .D(plm_tsi0_reg_dly7[10]), + .Q(plm_tsi0_reg_dly8[10]), + .CLR(plm_rst) + ); + FDC plm_tsi0_reg_dly8_9_ ( + .C(mgt_clk), + .D(plm_tsi0_reg_dly7[9]), + .Q(plm_tsi0_reg_dly8[9]), + .CLR(plm_rst) + ); + FDC plm_tsi0_reg_dec3_3_ ( + .C(mgt_clk), + .D(plm_tsi0_reg_dec2_3__643), + .Q(plm_tsi0_reg_dec3_3__673), + .CLR(plm_rst) + ); + FDC plm_tsi0_reg_dec3_2_ ( + .C(mgt_clk), + .D(plm_tsi0_reg_dec2_2__644), + .Q(plm_tsi0_reg_dec3_2__675), + .CLR(plm_rst) + ); + FDC plm_tsi0_reg_dec3_1_ ( + .C(mgt_clk), + .D(plm_tsi0_reg_dec2_1__645), + .Q(plm_tsi0_reg_dec3_1__677), + .CLR(plm_rst) + ); + FDC plm_tsi0_reg_dec7_5_ ( + .C(mgt_clk), + .D(plm_tsi0_reg_dec6[5]), + .Q(plm_tsi0_reg_dec7_5__661), + .CLR(plm_rst) + ); + FDC plm_tsi0_reg_dec2_11_ ( + .C(mgt_clk), + .D(plm_tsi0_reg_dec1_5073[11]), + .Q(plm_tsi0_reg_dec2_11__650), + .CLR(plm_rst) + ); + FDC plm_tsi0_reg_dec2_10_ ( + .C(mgt_clk), + .D(plm_tsi0_reg_dec1_5073[10]), + .Q(plm_tsi0_reg_dec2_10__651), + .CLR(plm_rst) + ); + FDC plm_tsi0_reg_dec2_9_ ( + .C(mgt_clk), + .D(plm_tsi0_reg_dec1_5073[9]), + .Q(plm_tsi0_reg_dec2_9__652), + .CLR(plm_rst) + ); + FDC plm_tsi0_reg_dec2_8_ ( + .C(mgt_clk), + .D(plm_tsi0_reg_dec1_5073[8]), + .Q(plm_tsi0_reg_dec2_8__653), + .CLR(plm_rst) + ); + FDC plm_tsi0_reg_dec5_4_ ( + .C(mgt_clk), + .D(plm_tsi0_reg_dec4_4__672), + .Q(plm_tsi0_reg_dec5_4__646), + .CLR(plm_rst) + ); + FDC plm_tsi0_reg_dec5_3_ ( + .C(mgt_clk), + .D(plm_tsi0_reg_dec4_3__674), + .Q(plm_tsi0_reg_dec5_3__647), + .CLR(plm_rst) + ); + FDC plm_tsi0_reg_dec5_2_ ( + .C(mgt_clk), + .D(plm_tsi0_reg_dec4_2__676), + .Q(plm_tsi0_reg_dec5_2__648), + .CLR(plm_rst) + ); + FDC plm_tsi0_reg_dec5_1_ ( + .C(mgt_clk), + .D(plm_tsi0_reg_dec4_1__678), + .Q(plm_tsi0_reg_dec5_1__649), + .CLR(plm_rst) + ); + FDC plm_tsi0_reg_dec3_11_ ( + .C(mgt_clk), + .D(plm_tsi0_reg_dec2_11__650), + .Q(plm_tsi0_reg_dec3_11__663), + .CLR(plm_rst) + ); + FDC plm_tsi0_reg_dec3_10_ ( + .C(mgt_clk), + .D(plm_tsi0_reg_dec2_10__651), + .Q(plm_tsi0_reg_dec3_10__665), + .CLR(plm_rst) + ); + FDC plm_tsi0_reg_dec3_9_ ( + .C(mgt_clk), + .D(plm_tsi0_reg_dec2_9__652), + .Q(plm_tsi0_reg_dec3_9__667), + .CLR(plm_rst) + ); + FDC plm_tsi0_reg_dec3_8_ ( + .C(mgt_clk), + .D(plm_tsi0_reg_dec2_8__653), + .Q(plm_tsi0_reg_dec3_8__669), + .CLR(plm_rst) + ); + FDC plm_tsi0_reg_dec3_4_ ( + .C(mgt_clk), + .D(plm_tsi0_reg_dec2_4__654), + .Q(plm_tsi0_reg_dec3_4__671), + .CLR(plm_rst) + ); + FDC plm_tsi0_reg_dly7_3_ ( + .C(mgt_clk), + .D(plm_tsi0_do[3]), + .Q(plm_tsi0_reg_dly7[3]), + .CLR(plm_rst) + ); + FDC plm_tsi0_reg_dly7_2_ ( + .C(mgt_clk), + .D(plm_tsi0_do[2]), + .Q(plm_tsi0_reg_dly7[2]), + .CLR(plm_rst) + ); + FDC plm_tsi0_reg_dly7_1_ ( + .C(mgt_clk), + .D(plm_tsi0_do[1]), + .Q(plm_tsi0_reg_dly7[1]), + .CLR(plm_rst) + ); + FDC plm_tsi0_reg_dly7_0_ ( + .C(mgt_clk), + .D(plm_tsi0_do[0]), + .Q(plm_tsi0_reg_dly7[0]), + .CLR(plm_rst) + ); + FDC plm_tsi0_reg_dec7_12_ ( + .C(mgt_clk), + .D(plm_tsi0_reg_dec6_5074[12]), + .Q(plm_tsi0_reg_dec7_12__655), + .CLR(plm_rst) + ); + FDC plm_tsi0_reg_dec5_11_ ( + .C(mgt_clk), + .D(plm_tsi0_reg_dec4_11__664), + .Q(plm_tsi0_reg_dec5_11__656), + .CLR(plm_rst) + ); + FDC plm_tsi0_reg_dec5_10_ ( + .C(mgt_clk), + .D(plm_tsi0_reg_dec4_10__666), + .Q(plm_tsi0_reg_dec5_10__657), + .CLR(plm_rst) + ); + FDC plm_tsi0_reg_dec5_9_ ( + .C(mgt_clk), + .D(plm_tsi0_reg_dec4_9__668), + .Q(plm_tsi0_reg_dec5_9__658), + .CLR(plm_rst) + ); + FDC plm_tsi0_reg_dec5_8_ ( + .C(mgt_clk), + .D(plm_tsi0_reg_dec4_8__670), + .Q(plm_tsi0_reg_dec5_8__659), + .CLR(plm_rst) + ); + FDC plm_tsi0_reg_dly7_15_ ( + .C(mgt_clk), + .D(plm_tsi0_do[15]), + .Q(plm_tsi0_reg_dly7[15]), + .CLR(plm_rst) + ); + FDC plm_tsi0_reg_dly7_14_ ( + .C(mgt_clk), + .D(plm_tsi0_do[14]), + .Q(plm_tsi0_reg_dly7[14]), + .CLR(plm_rst) + ); + FDC plm_tsi0_reg_dly7_13_ ( + .C(mgt_clk), + .D(plm_tsi0_do[13]), + .Q(plm_tsi0_reg_dly7[13]), + .CLR(plm_rst) + ); + FDC plm_tsi0_reg_dly7_12_ ( + .C(mgt_clk), + .D(plm_tsi0_do[12]), + .Q(plm_tsi0_reg_dly7[12]), + .CLR(plm_rst) + ); + FDC plm_tsi0_reg_dly7_11_ ( + .C(mgt_clk), + .D(plm_tsi0_do[11]), + .Q(plm_tsi0_reg_dly7[11]), + .CLR(plm_rst) + ); + FDC plm_tsi0_reg_dly7_10_ ( + .C(mgt_clk), + .D(plm_tsi0_do[10]), + .Q(plm_tsi0_reg_dly7[10]), + .CLR(plm_rst) + ); + FDC plm_tsi0_reg_dly7_9_ ( + .C(mgt_clk), + .D(plm_tsi0_do[9]), + .Q(plm_tsi0_reg_dly7[9]), + .CLR(plm_rst) + ); + FDC plm_tsi0_reg_dly7_8_ ( + .C(mgt_clk), + .D(plm_tsi0_do[8]), + .Q(plm_tsi0_reg_dly7[8]), + .CLR(plm_rst) + ); + FDC plm_tsi0_reg_dly7_7_ ( + .C(mgt_clk), + .D(plm_tsi0_do[7]), + .Q(plm_tsi0_reg_dly7[7]), + .CLR(plm_rst) + ); + FDC plm_tsi0_reg_dly7_6_ ( + .C(mgt_clk), + .D(plm_tsi0_do[6]), + .Q(plm_tsi0_reg_dly7[6]), + .CLR(plm_rst) + ); + FDC plm_tsi0_reg_dly7_5_ ( + .C(mgt_clk), + .D(plm_tsi0_do[5]), + .Q(plm_tsi0_reg_dly7[5]), + .CLR(plm_rst) + ); + FDC plm_tsi0_reg_dly7_4_ ( + .C(mgt_clk), + .D(plm_tsi0_do[4]), + .Q(plm_tsi0_reg_dly7[4]), + .CLR(plm_rst) + ); + FDC plm_tsi0_reg_dec1_11_ ( + .C(mgt_clk), + .D(plm_rx0_des_t2n[1]), + .Q(plm_tsi0_reg_dec1_5073[11]), + .CLR(plm_rst) + ); + FDC plm_tsi0_reg_dec1_10_ ( + .C(mgt_clk), + .D(plm_rx0_des_t2p[1]), + .Q(plm_tsi0_reg_dec1_5073[10]), + .CLR(plm_rst) + ); + FDC plm_tsi0_reg_dec1_9_ ( + .C(mgt_clk), + .D(plm_rx0_des_t1n[1]), + .Q(plm_tsi0_reg_dec1_5073[9]), + .CLR(plm_rst) + ); + FDC plm_tsi0_reg_dec1_8_ ( + .C(mgt_clk), + .D(plm_rx0_des_t1p[1]), + .Q(plm_tsi0_reg_dec1_5073[8]), + .CLR(plm_rst) + ); + FDC plm_tsi0_reg_dec8_6_ ( + .C(mgt_clk), + .D(plm_tsi0_reg_dec7_6_), + .Q(plm_tsi0_reg_dec8_6__660), + .CLR(plm_rst) + ); + FDC plm_tsi0_reg_dec8_5_ ( + .C(mgt_clk), + .D(plm_tsi0_reg_dec7_5__661), + .Q(plm_tsi0_reg_dec8_5__662), + .CLR(plm_rst) + ); + FDC plm_tsi0_reg_dec4_11_ ( + .C(mgt_clk), + .D(plm_tsi0_reg_dec3_11__663), + .Q(plm_tsi0_reg_dec4_11__664), + .CLR(plm_rst) + ); + FDC plm_tsi0_reg_dec4_10_ ( + .C(mgt_clk), + .D(plm_tsi0_reg_dec3_10__665), + .Q(plm_tsi0_reg_dec4_10__666), + .CLR(plm_rst) + ); + FDC plm_tsi0_reg_dec4_9_ ( + .C(mgt_clk), + .D(plm_tsi0_reg_dec3_9__667), + .Q(plm_tsi0_reg_dec4_9__668), + .CLR(plm_rst) + ); + FDC plm_tsi0_reg_dec4_8_ ( + .C(mgt_clk), + .D(plm_tsi0_reg_dec3_8__669), + .Q(plm_tsi0_reg_dec4_8__670), + .CLR(plm_rst) + ); + FDC plm_tsi0_reg_dec4_4_ ( + .C(mgt_clk), + .D(plm_tsi0_reg_dec3_4__671), + .Q(plm_tsi0_reg_dec4_4__672), + .CLR(plm_rst) + ); + FDC plm_tsi0_reg_dec4_3_ ( + .C(mgt_clk), + .D(plm_tsi0_reg_dec3_3__673), + .Q(plm_tsi0_reg_dec4_3__674), + .CLR(plm_rst) + ); + FDC plm_tsi0_reg_dec4_2_ ( + .C(mgt_clk), + .D(plm_tsi0_reg_dec3_2__675), + .Q(plm_tsi0_reg_dec4_2__676), + .CLR(plm_rst) + ); + FDC plm_tsi0_reg_dec4_1_ ( + .C(mgt_clk), + .D(plm_tsi0_reg_dec3_1__677), + .Q(plm_tsi0_reg_dec4_1__678), + .CLR(plm_rst) + ); + FDC plm_tsi0_reg_dly9_7_ ( + .C(mgt_clk), + .D(plm_tsi0_reg_dly8[7]), + .Q(plm_tsi0_reg_dly9[7]), + .CLR(plm_rst) + ); + FDC plm_tsi0_reg_dly9_6_ ( + .C(mgt_clk), + .D(plm_tsi0_reg_dly8[6]), + .Q(plm_tsi0_reg_dly9[6]), + .CLR(plm_rst) + ); + FDC plm_tsi0_reg_dly9_5_ ( + .C(mgt_clk), + .D(plm_tsi0_reg_dly8[5]), + .Q(plm_tsi0_reg_dly9[5]), + .CLR(plm_rst) + ); + FDC plm_tsi0_reg_dly9_4_ ( + .C(mgt_clk), + .D(plm_tsi0_reg_dly8[4]), + .Q(plm_tsi0_reg_dly9[4]), + .CLR(plm_rst) + ); + FDC plm_tsi0_reg_dly9_3_ ( + .C(mgt_clk), + .D(plm_tsi0_reg_dly8[3]), + .Q(plm_tsi0_reg_dly9[3]), + .CLR(plm_rst) + ); + FDC plm_tsi0_reg_dly9_2_ ( + .C(mgt_clk), + .D(plm_tsi0_reg_dly8[2]), + .Q(plm_tsi0_reg_dly9[2]), + .CLR(plm_rst) + ); + FDC plm_tsi0_reg_dly9_1_ ( + .C(mgt_clk), + .D(plm_tsi0_reg_dly8[1]), + .Q(plm_tsi0_reg_dly9[1]), + .CLR(plm_rst) + ); + FDC plm_tsi0_reg_dly9_0_ ( + .C(mgt_clk), + .D(plm_tsi0_reg_dly8[0]), + .Q(plm_tsi0_reg_dly9[0]), + .CLR(plm_rst) + ); + FDC plm_tsi0_reg_dec6_12_ ( + .C(mgt_clk), + .D(plm_tsi0_reg_dec5[12]), + .Q(plm_tsi0_reg_dec6_5074[12]), + .CLR(plm_rst) + ); + FDCE plm_tsi0_reg_inverted ( + .CE(plm_tsi0_reg_capture_now_680), + .C(mgt_clk), + .D(plm_tsi0_reg_capture_inv_679), + .Q(plm_rx0_inverted), + .CLR(plm_rst) + ); + FDCE plm_tsi0_reg_lane_pad ( + .CE(plm_tsi0_reg_capture_now_680), + .C(mgt_clk), + .D(plm_tsi0_reg_lane_pad_3), + .Q(plm_rx0_lane_pad), + .CLR(plm_rst) + ); + FDCE plm_tsi0_reg_link_pad ( + .CE(plm_tsi0_reg_capture_now_680), + .C(mgt_clk), + .D(plm_tsi0_reg_link_pad_3), + .Q(plm_rx0_link_pad), + .CLR(plm_rst) + ); + FDCE plm_tsi0_reg_lane_num_7_ ( + .CE(plm_tsi0_reg_capture_now_680), + .C(mgt_clk), + .D(plm_tsi0_reg_lane_num_3[7]), + .Q(plm_rx0_lane_num[7]), + .CLR(plm_rst) + ); + FDCE plm_tsi0_reg_lane_num_6_ ( + .CE(plm_tsi0_reg_capture_now_680), + .C(mgt_clk), + .D(plm_tsi0_reg_lane_num_3[6]), + .Q(plm_rx0_lane_num[6]), + .CLR(plm_rst) + ); + FDCE plm_tsi0_reg_lane_num_5_ ( + .CE(plm_tsi0_reg_capture_now_680), + .C(mgt_clk), + .D(plm_tsi0_reg_lane_num_3[5]), + .Q(plm_rx0_lane_num[5]), + .CLR(plm_rst) + ); + FDCE plm_tsi0_reg_lane_num_4_ ( + .CE(plm_tsi0_reg_capture_now_680), + .C(mgt_clk), + .D(plm_tsi0_reg_lane_num_3[4]), + .Q(plm_rx0_lane_num[4]), + .CLR(plm_rst) + ); + FDCE plm_tsi0_reg_lane_num_3_ ( + .CE(plm_tsi0_reg_capture_now_680), + .C(mgt_clk), + .D(plm_tsi0_reg_lane_num_3[3]), + .Q(plm_rx0_lane_num[3]), + .CLR(plm_rst) + ); + FDCE plm_tsi0_reg_lane_num_2_ ( + .CE(plm_tsi0_reg_capture_now_680), + .C(mgt_clk), + .D(plm_tsi0_reg_lane_num_3[2]), + .Q(plm_rx0_lane_num[2]), + .CLR(plm_rst) + ); + FDCE plm_tsi0_reg_lane_num_1_ ( + .CE(plm_tsi0_reg_capture_now_680), + .C(mgt_clk), + .D(plm_tsi0_reg_lane_num_3[1]), + .Q(plm_rx0_lane_num[1]), + .CLR(plm_rst) + ); + FDCE plm_tsi0_reg_lane_num_0_ ( + .CE(plm_tsi0_reg_capture_now_680), + .C(mgt_clk), + .D(plm_tsi0_reg_lane_num_3[0]), + .Q(plm_rx0_lane_num[0]), + .CLR(plm_rst) + ); + FDCE plm_tsi0_reg_link_num_7_ ( + .CE(plm_tsi0_reg_capture_now_680), + .C(mgt_clk), + .D(plm_tsi0_reg_link_num_3[7]), + .Q(plm_rx0_link_num[7]), + .CLR(plm_rst) + ); + FDCE plm_tsi0_reg_link_num_6_ ( + .CE(plm_tsi0_reg_capture_now_680), + .C(mgt_clk), + .D(plm_tsi0_reg_link_num_3[6]), + .Q(plm_rx0_link_num[6]), + .CLR(plm_rst) + ); + FDCE plm_tsi0_reg_link_num_5_ ( + .CE(plm_tsi0_reg_capture_now_680), + .C(mgt_clk), + .D(plm_tsi0_reg_link_num_3[5]), + .Q(plm_rx0_link_num[5]), + .CLR(plm_rst) + ); + FDCE plm_tsi0_reg_link_num_4_ ( + .CE(plm_tsi0_reg_capture_now_680), + .C(mgt_clk), + .D(plm_tsi0_reg_link_num_3[4]), + .Q(plm_rx0_link_num[4]), + .CLR(plm_rst) + ); + FDCE plm_tsi0_reg_link_num_3_ ( + .CE(plm_tsi0_reg_capture_now_680), + .C(mgt_clk), + .D(plm_tsi0_reg_link_num_3[3]), + .Q(plm_rx0_link_num[3]), + .CLR(plm_rst) + ); + FDCE plm_tsi0_reg_link_num_2_ ( + .CE(plm_tsi0_reg_capture_now_680), + .C(mgt_clk), + .D(plm_tsi0_reg_link_num_3[2]), + .Q(plm_rx0_link_num[2]), + .CLR(plm_rst) + ); + FDCE plm_tsi0_reg_link_num_1_ ( + .CE(plm_tsi0_reg_capture_now_680), + .C(mgt_clk), + .D(plm_tsi0_reg_link_num_3[1]), + .Q(plm_rx0_link_num[1]), + .CLR(plm_rst) + ); + FDCE plm_tsi0_reg_link_num_0_ ( + .CE(plm_tsi0_reg_capture_now_680), + .C(mgt_clk), + .D(plm_tsi0_reg_link_num_3[0]), + .Q(plm_rx0_link_num[0]), + .CLR(plm_rst) + ); + FDCE plm_tsi0_reg_linkctrl_3_ ( + .CE(plm_tsi0_reg_capture_now_680), + .C(mgt_clk), + .D(plm_tsi0_reg_linkctrl_3_3_), + .Q(plm_rx0_linkctrl_3_), + .CLR(plm_rst) + ); + FDCE plm_tsi0_reg_linkctrl_0_ ( + .CE(plm_tsi0_reg_capture_now_680), + .C(mgt_clk), + .D(plm_tsi0_reg_linkctrl_3_0_), + .Q(plm_rx0_linkctrl_0_), + .CLR(plm_rst) + ); + SRL16 plm_tsi0_reg_dec8_0_I_1 ( + .D(plm_rx0_des_com[0]), + .Q(plm_tsi0_reg_dec8_0_N_6), + .CLK(mgt_clk), + .A0(plm_tsi0_GND_682), + .A1(plm_tsi0_VCC_681), + .A2(plm_tsi0_VCC_681), + .A3(plm_tsi0_GND_682) + ); + SRL16 plm_tsi0_reg_dec7_0_I_1 ( + .D(plm_rx0_des_pad[0]), + .Q(plm_tsi0_reg_dec7_0_N_6), + .CLK(mgt_clk), + .A0(plm_tsi0_VCC_681), + .A1(plm_tsi0_GND_682), + .A2(plm_tsi0_VCC_681), + .A3(plm_tsi0_GND_682) + ); + SRL16 plm_tsi0_reg_dec7_I_1 ( + .D(plm_rx0_des_pad[1]), + .Q(plm_tsi0_reg_dec7_tmp_d_array_0[0]), + .CLK(mgt_clk), + .A0(plm_tsi0_VCC_681), + .A1(plm_tsi0_GND_682), + .A2(plm_tsi0_VCC_681), + .A3(plm_tsi0_GND_682) + ); + SRL16 plm_tsi0_reg_dec5_I_1 ( + .D(plm_rx0_des_sym[1]), + .Q(plm_tsi0_reg_dec5_tmp_d_array_0[0]), + .CLK(mgt_clk), + .A0(plm_tsi0_VCC_681), + .A1(plm_tsi0_VCC_681), + .A2(plm_tsi0_GND_682), + .A3(plm_tsi0_GND_682) + ); + SRL16 plm_tsi0_reg_dec6_I_1 ( + .D(plm_rx0_des_sym[0]), + .Q(plm_tsi0_reg_dec6_tmp_d_array_0[0]), + .CLK(mgt_clk), + .A0(plm_tsi0_GND_682), + .A1(plm_tsi0_GND_682), + .A2(plm_tsi0_VCC_681), + .A3(plm_tsi0_GND_682) + ); + SRL16 plm_tsi0_reg_dec1_2_I_1 ( + .D(plm_reg_t2n_4[0]), + .Q(plm_tsi0_reg_dec1_2_N_6), + .CLK(mgt_clk), + .A0(plm_tsi0_VCC_681), + .A1(plm_tsi0_GND_682), + .A2(plm_tsi0_GND_682), + .A3(plm_tsi0_GND_682) + ); + SRL16 plm_tsi0_reg_dec1_1_I_1 ( + .D(plm_reg_t2p_4[0]), + .Q(plm_tsi0_reg_dec1_1_N_6), + .CLK(mgt_clk), + .A0(plm_tsi0_VCC_681), + .A1(plm_tsi0_GND_682), + .A2(plm_tsi0_GND_682), + .A3(plm_tsi0_GND_682) + ); + SRL16 plm_tsi0_reg_dec1_0_I_1 ( + .D(plm_reg_t1n_4[0]), + .Q(plm_tsi0_reg_dec1_0_N_6), + .CLK(mgt_clk), + .A0(plm_tsi0_VCC_681), + .A1(plm_tsi0_GND_682), + .A2(plm_tsi0_GND_682), + .A3(plm_tsi0_GND_682) + ); + SRL16 plm_tsi0_reg_dec1_I_1 ( + .D(plm_reg_t1p_4[0]), + .Q(plm_tsi0_reg_dec1_N_6), + .CLK(mgt_clk), + .A0(plm_tsi0_VCC_681), + .A1(plm_tsi0_GND_682), + .A2(plm_tsi0_GND_682), + .A3(plm_tsi0_GND_682) + ); + SRL16 plm_tsi0_reg_dec8_I_1 ( + .D(plm_rx0_des_com[1]), + .Q(plm_tsi0_reg_dec8_tmp_d_array_0[0]), + .CLK(mgt_clk), + .A0(plm_tsi0_GND_682), + .A1(plm_tsi0_VCC_681), + .A2(plm_tsi0_VCC_681), + .A3(plm_tsi0_GND_682) + ); + defparam plm_dfm_N_8801_i_0_m2_0.INIT = 8'h8D; + LUT3 plm_dfm_N_8801_i_0_m2_0 ( + .I0(phy_rctrl_l), + .I1(plm_dfm_preh_sdpstp[0]), + .I2(plm_dfm_preh_sdpstp[1]), + .O(plm_dfm_N_8801_i_0_m2_0_683) + ); + defparam plm_dfm_not_my_prob_after_this_reg_phy_rframe_h_3.INIT = 8'h96; + LUT3_L plm_dfm_not_my_prob_after_this_reg_phy_rframe_h_3 ( + .I0(phy_rframe_h), + .I1(plm_dfm_preh_sdpstp[0]), + .I2(plm_dfm_preh_sdpstp[1]), + .LO(plm_dfm_reg_phy_rframe_h_3) + ); + defparam plm_dfm_not_my_prob_after_this_reg_phy_rframe_l_3.INIT = 8'h96; + LUT3_L plm_dfm_not_my_prob_after_this_reg_phy_rframe_l_3 ( + .I0(phy_rframe_l), + .I1(plm_dfm_prel_sdpstp[0]), + .I2(plm_dfm_prel_sdpstp[1]), + .LO(plm_dfm_reg_phy_rframe_l_3) + ); + defparam plm_dfm_not_my_prob_after_this_reg_phy_rbad_dfrm_h_3_0_a2.INIT = 4'h4; + LUT2_L plm_dfm_not_my_prob_after_this_reg_phy_rbad_dfrm_h_3_0_a2 ( + .I0(plm_dfm_preh_edbedg[0]), + .I1(plm_dfm_preh_edbedg[1]), + .LO(plm_dfm_reg_phy_rbad_dfrm_h_3) + ); + defparam plm_dfm_not_my_prob_after_this_reg_phy_rbad_dfrm_l_3_0_a2.INIT = 4'h4; + LUT2_L plm_dfm_not_my_prob_after_this_reg_phy_rbad_dfrm_l_3_0_a2 ( + .I0(plm_dfm_prel_edbedg[0]), + .I1(plm_dfm_prel_edbedg[1]), + .LO(plm_dfm_reg_phy_rbad_dfrm_l_3) + ); + defparam plm_dfm_not_my_prob_after_this_un4_reg_phy_ferr_h_n_i.INIT = 4'h7; + LUT2_L plm_dfm_not_my_prob_after_this_un4_reg_phy_ferr_h_n_i ( + .I0(plm_dfm_preh_edbedg[0]), + .I1(plm_dfm_preh_edbedg[1]), + .LO(plm_dfm_un4_reg_phy_ferr_h_n_i) + ); + defparam plm_dfm_not_my_prob_after_this_un4_reg_phy_ferr_l_n_i.INIT = 4'h7; + LUT2_L plm_dfm_not_my_prob_after_this_un4_reg_phy_ferr_l_n_i ( + .I0(plm_dfm_prel_edbedg[0]), + .I1(plm_dfm_prel_edbedg[1]), + .LO(plm_dfm_un4_reg_phy_ferr_l_n_i) + ); + defparam plm_dfm_N_17411_i.INIT = 4'h1; + LUT1_L plm_dfm_N_17411_i ( + .I0(plm_dfm_N_8801_i_0_m2_0_683), + .LO(plm_dfm_N_17411_i_684) + ); + defparam plm_dfm_ns_phy_rctrl_l_iv_0_m2_0.INIT = 8'hB1; + LUT3_L plm_dfm_ns_phy_rctrl_l_iv_0_m2_0 ( + .I0(plm_dfm_N_8801_i_0_m2_0_683), + .I1(plm_dfm_prel_sdpstp[0]), + .I2(plm_dfm_prel_sdpstp[1]), + .LO(plm_dfm_ns_phy_rctrl_l_iv_0_m2_0_685) + ); + FDC plm_dfm_reg_phy_rerr ( + .C(mgt_clk), + .D(plm_dfm_by1_prec_rcverr), + .Q(cmmp_receiver_err), + .CLR(plm_rst) + ); + FDPE plm_dfm_reg_phy_rd_63_ ( + .PRE(plm_rst), + .CE(plm_phy_cke_1_401), + .C(mgt_clk), + .D(plm_dfm_by1_preh_out[31]), + .Q(phy_rd[63]) + ); + FDPE plm_dfm_reg_phy_rd_62_ ( + .PRE(plm_rst), + .CE(plm_phy_cke_1_401), + .C(mgt_clk), + .D(plm_dfm_by1_preh_out[30]), + .Q(phy_rd[62]) + ); + FDPE plm_dfm_reg_phy_rd_61_ ( + .PRE(plm_rst), + .CE(plm_phy_cke_1_401), + .C(mgt_clk), + .D(plm_dfm_by1_preh_out[29]), + .Q(phy_rd[61]) + ); + FDPE plm_dfm_reg_phy_rd_60_ ( + .PRE(plm_rst), + .CE(plm_phy_cke_1_401), + .C(mgt_clk), + .D(plm_dfm_by1_preh_out[28]), + .Q(phy_rd[60]) + ); + FDPE plm_dfm_reg_phy_rd_59_ ( + .PRE(plm_rst), + .CE(plm_phy_cke_1_401), + .C(mgt_clk), + .D(plm_dfm_by1_preh_out[27]), + .Q(phy_rd[59]) + ); + FDPE plm_dfm_reg_phy_rd_58_ ( + .PRE(plm_rst), + .CE(plm_phy_cke_1_401), + .C(mgt_clk), + .D(plm_dfm_by1_preh_out[26]), + .Q(phy_rd[58]) + ); + FDPE plm_dfm_reg_phy_rd_57_ ( + .PRE(plm_rst), + .CE(plm_phy_cke_1_401), + .C(mgt_clk), + .D(plm_dfm_by1_preh_out[25]), + .Q(phy_rd[57]) + ); + FDPE plm_dfm_reg_phy_rd_56_ ( + .PRE(plm_rst), + .CE(plm_phy_cke_1_401), + .C(mgt_clk), + .D(plm_dfm_by1_preh_out[24]), + .Q(phy_rd[56]) + ); + FDCE plm_dfm_reg_phy_rd_55_ ( + .CE(plm_phy_cke_1_401), + .C(mgt_clk), + .D(plm_dfm_by1_preh_out[23]), + .Q(phy_rd[55]), + .CLR(plm_rst) + ); + FDCE plm_dfm_reg_phy_rd_54_ ( + .CE(plm_phy_cke_1_401), + .C(mgt_clk), + .D(plm_dfm_by1_preh_out[22]), + .Q(phy_rd[54]), + .CLR(plm_rst) + ); + FDCE plm_dfm_reg_phy_rd_53_ ( + .CE(plm_phy_cke_1_401), + .C(mgt_clk), + .D(plm_dfm_by1_preh_out[21]), + .Q(phy_rd[53]), + .CLR(plm_rst) + ); + FDCE plm_dfm_reg_phy_rd_52_ ( + .CE(plm_phy_cke_1_401), + .C(mgt_clk), + .D(plm_dfm_by1_preh_out[20]), + .Q(phy_rd[52]), + .CLR(plm_rst) + ); + FDCE plm_dfm_reg_phy_rd_51_ ( + .CE(plm_phy_cke_1_401), + .C(mgt_clk), + .D(plm_dfm_by1_preh_out[19]), + .Q(phy_rd[51]), + .CLR(plm_rst) + ); + FDCE plm_dfm_reg_phy_rd_50_ ( + .CE(plm_phy_cke_1_401), + .C(mgt_clk), + .D(plm_dfm_by1_preh_out[18]), + .Q(phy_rd[50]), + .CLR(plm_rst) + ); + FDCE plm_dfm_reg_phy_rd_49_ ( + .CE(plm_phy_cke_1_401), + .C(mgt_clk), + .D(plm_dfm_by1_preh_out[17]), + .Q(phy_rd[49]), + .CLR(plm_rst) + ); + FDCE plm_dfm_reg_phy_rd_48_ ( + .CE(plm_phy_cke_1_401), + .C(mgt_clk), + .D(plm_dfm_by1_preh_out[16]), + .Q(phy_rd[48]), + .CLR(plm_rst) + ); + FDCE plm_dfm_reg_phy_rd_47_ ( + .CE(plm_phy_cke_1_401), + .C(mgt_clk), + .D(plm_dfm_by1_preh_out[15]), + .Q(phy_rd[47]), + .CLR(plm_rst) + ); + FDCE plm_dfm_reg_phy_rd_46_ ( + .CE(plm_phy_cke_1_401), + .C(mgt_clk), + .D(plm_dfm_by1_preh_out[14]), + .Q(phy_rd[46]), + .CLR(plm_rst) + ); + FDCE plm_dfm_reg_phy_rd_45_ ( + .CE(plm_phy_cke_1_401), + .C(mgt_clk), + .D(plm_dfm_by1_preh_out[13]), + .Q(phy_rd[45]), + .CLR(plm_rst) + ); + FDCE plm_dfm_reg_phy_rd_44_ ( + .CE(plm_phy_cke_1_401), + .C(mgt_clk), + .D(plm_dfm_by1_preh_out[12]), + .Q(phy_rd[44]), + .CLR(plm_rst) + ); + FDCE plm_dfm_reg_phy_rd_43_ ( + .CE(plm_phy_cke_1_401), + .C(mgt_clk), + .D(plm_dfm_by1_preh_out[11]), + .Q(phy_rd[43]), + .CLR(plm_rst) + ); + FDCE plm_dfm_reg_phy_rd_42_ ( + .CE(plm_phy_cke_1_401), + .C(mgt_clk), + .D(plm_dfm_by1_preh_out[10]), + .Q(phy_rd[42]), + .CLR(plm_rst) + ); + FDCE plm_dfm_reg_phy_rd_41_ ( + .CE(plm_phy_cke_1_401), + .C(mgt_clk), + .D(plm_dfm_by1_preh_out[9]), + .Q(phy_rd[41]), + .CLR(plm_rst) + ); + FDCE plm_dfm_reg_phy_rd_40_ ( + .CE(plm_phy_cke_1_401), + .C(mgt_clk), + .D(plm_dfm_by1_preh_out[8]), + .Q(phy_rd[40]), + .CLR(plm_rst) + ); + FDCE plm_dfm_reg_phy_rd_39_ ( + .CE(plm_phy_cke_1_401), + .C(mgt_clk), + .D(plm_dfm_by1_preh_out[7]), + .Q(phy_rd[39]), + .CLR(plm_rst) + ); + FDCE plm_dfm_reg_phy_rd_38_ ( + .CE(plm_phy_cke_1_401), + .C(mgt_clk), + .D(plm_dfm_by1_preh_out[6]), + .Q(phy_rd[38]), + .CLR(plm_rst) + ); + FDCE plm_dfm_reg_phy_rd_37_ ( + .CE(plm_phy_cke_1_401), + .C(mgt_clk), + .D(plm_dfm_by1_preh_out[5]), + .Q(phy_rd[37]), + .CLR(plm_rst) + ); + FDCE plm_dfm_reg_phy_rd_36_ ( + .CE(plm_phy_cke_1_401), + .C(mgt_clk), + .D(plm_dfm_by1_preh_out[4]), + .Q(phy_rd[36]), + .CLR(plm_rst) + ); + FDCE plm_dfm_reg_phy_rd_35_ ( + .CE(plm_phy_cke_1_401), + .C(mgt_clk), + .D(plm_dfm_by1_preh_out[3]), + .Q(phy_rd[35]), + .CLR(plm_rst) + ); + FDCE plm_dfm_reg_phy_rd_34_ ( + .CE(plm_phy_cke_1_401), + .C(mgt_clk), + .D(plm_dfm_by1_preh_out[2]), + .Q(phy_rd[34]), + .CLR(plm_rst) + ); + FDCE plm_dfm_reg_phy_rd_33_ ( + .CE(plm_phy_cke_0_402), + .C(mgt_clk), + .D(plm_dfm_by1_preh_out[1]), + .Q(phy_rd[33]), + .CLR(plm_rst) + ); + FDCE plm_dfm_reg_phy_rd_32_ ( + .CE(plm_phy_cke_0_402), + .C(mgt_clk), + .D(plm_dfm_by1_preh_out[0]), + .Q(phy_rd[32]), + .CLR(plm_rst) + ); + FDCE plm_dfm_reg_phy_rd_31_ ( + .CE(plm_phy_cke_0_402), + .C(mgt_clk), + .D(plm_dfm_by1_prel_out[31]), + .Q(phy_rd[31]), + .CLR(plm_rst) + ); + FDCE plm_dfm_reg_phy_rd_30_ ( + .CE(plm_phy_cke_0_402), + .C(mgt_clk), + .D(plm_dfm_by1_prel_out[30]), + .Q(phy_rd[30]), + .CLR(plm_rst) + ); + FDCE plm_dfm_reg_phy_rd_29_ ( + .CE(plm_phy_cke_0_402), + .C(mgt_clk), + .D(plm_dfm_by1_prel_out[29]), + .Q(phy_rd[29]), + .CLR(plm_rst) + ); + FDCE plm_dfm_reg_phy_rd_28_ ( + .CE(plm_phy_cke_0_402), + .C(mgt_clk), + .D(plm_dfm_by1_prel_out[28]), + .Q(phy_rd[28]), + .CLR(plm_rst) + ); + FDCE plm_dfm_reg_phy_rd_27_ ( + .CE(plm_phy_cke_0_402), + .C(mgt_clk), + .D(plm_dfm_by1_prel_out[27]), + .Q(phy_rd[27]), + .CLR(plm_rst) + ); + FDCE plm_dfm_reg_phy_rd_26_ ( + .CE(plm_phy_cke_0_402), + .C(mgt_clk), + .D(plm_dfm_by1_prel_out[26]), + .Q(phy_rd[26]), + .CLR(plm_rst) + ); + FDCE plm_dfm_reg_phy_rd_25_ ( + .CE(plm_phy_cke_0_402), + .C(mgt_clk), + .D(plm_dfm_by1_prel_out[25]), + .Q(phy_rd[25]), + .CLR(plm_rst) + ); + FDCE plm_dfm_reg_phy_rd_24_ ( + .CE(plm_phy_cke_0_402), + .C(mgt_clk), + .D(plm_dfm_by1_prel_out[24]), + .Q(phy_rd[24]), + .CLR(plm_rst) + ); + FDCE plm_dfm_reg_phy_rd_23_ ( + .CE(plm_phy_cke_0_402), + .C(mgt_clk), + .D(plm_dfm_by1_prel_out[23]), + .Q(phy_rd[23]), + .CLR(plm_rst) + ); + FDCE plm_dfm_reg_phy_rd_22_ ( + .CE(plm_phy_cke_0_402), + .C(mgt_clk), + .D(plm_dfm_by1_prel_out[22]), + .Q(phy_rd[22]), + .CLR(plm_rst) + ); + FDCE plm_dfm_reg_phy_rd_21_ ( + .CE(plm_phy_cke_0_402), + .C(mgt_clk), + .D(plm_dfm_by1_prel_out[21]), + .Q(phy_rd[21]), + .CLR(plm_rst) + ); + FDCE plm_dfm_reg_phy_rd_20_ ( + .CE(plm_phy_cke_0_402), + .C(mgt_clk), + .D(plm_dfm_by1_prel_out[20]), + .Q(phy_rd[20]), + .CLR(plm_rst) + ); + FDCE plm_dfm_reg_phy_rd_19_ ( + .CE(plm_phy_cke_0_402), + .C(mgt_clk), + .D(plm_dfm_by1_prel_out[19]), + .Q(phy_rd[19]), + .CLR(plm_rst) + ); + FDCE plm_dfm_reg_phy_rd_18_ ( + .CE(plm_phy_cke_0_402), + .C(mgt_clk), + .D(plm_dfm_by1_prel_out[18]), + .Q(phy_rd[18]), + .CLR(plm_rst) + ); + FDCE plm_dfm_reg_phy_rd_17_ ( + .CE(plm_phy_cke_0_402), + .C(mgt_clk), + .D(plm_dfm_by1_prel_out[17]), + .Q(phy_rd[17]), + .CLR(plm_rst) + ); + FDCE plm_dfm_reg_phy_rd_16_ ( + .CE(plm_phy_cke_0_402), + .C(mgt_clk), + .D(plm_dfm_by1_prel_out[16]), + .Q(phy_rd[16]), + .CLR(plm_rst) + ); + FDCE plm_dfm_reg_phy_rd_15_ ( + .CE(plm_phy_cke_0_402), + .C(mgt_clk), + .D(plm_dfm_by1_prel_out[15]), + .Q(phy_rd[15]), + .CLR(plm_rst) + ); + FDCE plm_dfm_reg_phy_rd_14_ ( + .CE(plm_phy_cke_0_402), + .C(mgt_clk), + .D(plm_dfm_by1_prel_out[14]), + .Q(phy_rd[14]), + .CLR(plm_rst) + ); + FDCE plm_dfm_reg_phy_rd_13_ ( + .CE(plm_phy_cke_0_402), + .C(mgt_clk), + .D(plm_dfm_by1_prel_out[13]), + .Q(phy_rd[13]), + .CLR(plm_rst) + ); + FDCE plm_dfm_reg_phy_rd_12_ ( + .CE(plm_phy_cke_0_402), + .C(mgt_clk), + .D(plm_dfm_by1_prel_out[12]), + .Q(phy_rd[12]), + .CLR(plm_rst) + ); + FDCE plm_dfm_reg_phy_rd_11_ ( + .CE(plm_phy_cke_0_402), + .C(mgt_clk), + .D(plm_dfm_by1_prel_out[11]), + .Q(phy_rd[11]), + .CLR(plm_rst) + ); + FDCE plm_dfm_reg_phy_rd_10_ ( + .CE(plm_phy_cke_0_402), + .C(mgt_clk), + .D(plm_dfm_by1_prel_out[10]), + .Q(phy_rd[10]), + .CLR(plm_rst) + ); + FDCE plm_dfm_reg_phy_rd_9_ ( + .CE(plm_phy_cke_0_402), + .C(mgt_clk), + .D(plm_dfm_by1_prel_out[9]), + .Q(phy_rd[9]), + .CLR(plm_rst) + ); + FDCE plm_dfm_reg_phy_rd_8_ ( + .CE(plm_phy_cke_0_402), + .C(mgt_clk), + .D(plm_dfm_by1_prel_out[8]), + .Q(phy_rd[8]), + .CLR(plm_rst) + ); + FDPE plm_dfm_reg_phy_rd_7_ ( + .PRE(plm_rst), + .CE(plm_phy_cke_0_402), + .C(mgt_clk), + .D(plm_dfm_by1_prel_out[7]), + .Q(phy_rd[7]) + ); + FDPE plm_dfm_reg_phy_rd_6_ ( + .PRE(plm_rst), + .CE(plm_phy_cke_0_402), + .C(mgt_clk), + .D(plm_dfm_by1_prel_out[6]), + .Q(phy_rd[6]) + ); + FDPE plm_dfm_reg_phy_rd_5_ ( + .PRE(plm_rst), + .CE(plm_phy_cke_0_402), + .C(mgt_clk), + .D(plm_dfm_by1_prel_out[5]), + .Q(phy_rd[5]) + ); + FDPE plm_dfm_reg_phy_rd_4_ ( + .PRE(plm_rst), + .CE(plm_phy_cke_0_402), + .C(mgt_clk), + .D(plm_dfm_by1_prel_out[4]), + .Q(phy_rd[4]) + ); + FDPE plm_dfm_reg_phy_rd_3_ ( + .PRE(plm_rst), + .CE(plm_phy_cke_0_402), + .C(mgt_clk), + .D(plm_dfm_by1_prel_out[3]), + .Q(phy_rd[3]) + ); + FDPE plm_dfm_reg_phy_rd_2_ ( + .PRE(plm_rst), + .CE(plm_phy_cke_0_402), + .C(mgt_clk), + .D(plm_dfm_by1_prel_out[2]), + .Q(phy_rd[2]) + ); + FDPE plm_dfm_reg_phy_rd_1_ ( + .PRE(plm_rst), + .CE(plm_phy_cke_0_402), + .C(mgt_clk), + .D(plm_dfm_by1_prel_out[1]), + .Q(phy_rd[1]) + ); + FDPE plm_dfm_reg_phy_rd_0_ ( + .PRE(plm_rst), + .CE(plm_phy_cke_0_402), + .C(mgt_clk), + .D(plm_dfm_by1_prel_out[0]), + .Q(phy_rd[0]) + ); + FDCE plm_dfm_reg_phy_rframe_h ( + .CE(plm_phy_cke_1_401), + .C(mgt_clk), + .D(plm_dfm_reg_phy_rframe_h_3), + .Q(phy_rframe_h), + .CLR(plm_rst) + ); + FDCE plm_dfm_reg_phy_rframe_l ( + .CE(plm_phy_cke_1_401), + .C(mgt_clk), + .D(plm_dfm_reg_phy_rframe_l_3), + .Q(phy_rframe_l), + .CLR(plm_rst) + ); + FDCE plm_dfm_reg_phy_rbad_dfrm_h ( + .CE(plm_phy_cke_0_402), + .C(mgt_clk), + .D(plm_dfm_reg_phy_rbad_dfrm_h_3), + .Q(plm_phy_rbad_dfrm_h), + .CLR(plm_rst) + ); + FDCE plm_dfm_reg_phy_rbad_dfrm_l ( + .CE(plm_phy_cke_0_402), + .C(mgt_clk), + .D(plm_dfm_reg_phy_rbad_dfrm_l_3), + .Q(plm_phy_rbad_dfrm_l), + .CLR(plm_rst) + ); + FDPE plm_dfm_reg_phy_ferr_h_n ( + .PRE(plm_rst), + .CE(plm_phy_cke_0_402), + .C(mgt_clk), + .D(plm_dfm_un4_reg_phy_ferr_h_n_i), + .Q(phy_rferr_h_n) + ); + FDPE plm_dfm_reg_phy_ferr_l_n ( + .PRE(plm_rst), + .CE(plm_phy_cke_0_402), + .C(mgt_clk), + .D(plm_dfm_un4_reg_phy_ferr_l_n_i), + .Q(phy_rferr_l_n) + ); + FDPE plm_dfm_reg_phy_rctrl_h ( + .PRE(plm_rst), + .CE(plm_phy_cke_0_402), + .C(mgt_clk), + .D(plm_dfm_N_17411_i_684), + .Q(phy_rctrl_h) + ); + FDPE plm_dfm_reg_phy_rctrl_l ( + .PRE(plm_rst), + .CE(plm_phy_cke_0_402), + .C(mgt_clk), + .D(plm_dfm_ns_phy_rctrl_l_iv_0_m2_0_685), + .Q(phy_rctrl_l) + ); + defparam plm_dfm_deframe1_filter_reg_any_sym_5_0_a2_0_a2_0_a3_0_a3_0_.INIT = 4'h8; + LUT2 plm_dfm_deframe1_filter_reg_any_sym_5_0_a2_0_a2_0_a3_0_a3_0_ ( + .I0(plm_link_l0), + .I1(plm_rx0_des_sym[0]), + .O(plm_dfm_deframe1_reg_dat_1_sqmuxa_1) + ); + defparam plm_dfm_deframe1_filter_reg_any_sym_5_0_a2_0_a2_0_a3_0_a3_1_.INIT = 4'h8; + LUT2 plm_dfm_deframe1_filter_reg_any_sym_5_0_a2_0_a2_0_a3_0_a3_1_ ( + .I0(plm_link_l0), + .I1(plm_rx0_des_sym[1]), + .O(plm_dfm_deframe1_reg_dat_1_sqmuxa) + ); + defparam plm_dfm_deframe1_det_d0_0_a2_0_a2_0_a2.INIT = 4'h1; + LUT2 plm_dfm_deframe1_det_d0_0_a2_0_a2_0_a2 ( + .I0(plm_rx0_des_bad[0]), + .I1(plm_rx0_des_bad[1]), + .O(plm_dfm_deframe1_det_d0_i) + ); + defparam plm_dfm_deframe1_filter_reg_any_bad_6_0_a2_0_a2_0_a2_4_1_.INIT = 16'h0001; + LUT4_L plm_dfm_deframe1_filter_reg_any_bad_6_0_a2_0_a2_0_a2_4_1_ ( + .I0(plm_rx0_des_bad[1]), + .I1(plm_rx0_des_com[1]), + .I2(plm_rx0_des_fts[1]), + .I3(plm_rx0_des_pad[1]), + .LO(plm_dfm_deframe1_reg_any_bad_6_0_a2_0_a2_0_a2_4[1]) + ); + defparam plm_dfm_deframe1_filter_reg_any_bad_6_0_a2_0_a2_0_a2_4_0_.INIT = 16'h0001; + LUT4_L plm_dfm_deframe1_filter_reg_any_bad_6_0_a2_0_a2_0_a2_4_0_ ( + .I0(plm_rx0_des_bad[0]), + .I1(plm_rx0_des_com[0]), + .I2(plm_rx0_des_fts[0]), + .I3(plm_rx0_des_pad[0]), + .LO(plm_dfm_deframe1_reg_any_bad_6_0_a2_0_a2_0_a2_4[0]) + ); + defparam plm_dfm_deframe1_reg_dat_6_0_a2_0_a2_0_a4_12_.INIT = 4'h8; + LUT2_L plm_dfm_deframe1_reg_dat_6_0_a2_0_a2_0_a4_12_ ( + .I0(plm_dfm_deframe1_reg_dat_1_sqmuxa), + .I1(plm_rx0_des_dat[12]), + .LO(plm_dfm_deframe1_reg_dat_6[12]) + ); + defparam plm_dfm_deframe1_reg_dat_6_0_a2_0_a2_0_a4_11_.INIT = 4'h8; + LUT2_L plm_dfm_deframe1_reg_dat_6_0_a2_0_a2_0_a4_11_ ( + .I0(plm_dfm_deframe1_reg_dat_1_sqmuxa), + .I1(plm_rx0_des_dat[11]), + .LO(plm_dfm_deframe1_reg_dat_6[11]) + ); + defparam plm_dfm_deframe1_reg_dat_6_0_a2_0_a2_0_a4_10_.INIT = 4'h8; + LUT2_L plm_dfm_deframe1_reg_dat_6_0_a2_0_a2_0_a4_10_ ( + .I0(plm_dfm_deframe1_reg_dat_1_sqmuxa), + .I1(plm_rx0_des_dat[10]), + .LO(plm_dfm_deframe1_reg_dat_6[10]) + ); + defparam plm_dfm_deframe1_reg_dat_6_0_a2_0_a2_0_a4_9_.INIT = 4'h8; + LUT2_L plm_dfm_deframe1_reg_dat_6_0_a2_0_a2_0_a4_9_ ( + .I0(plm_dfm_deframe1_reg_dat_1_sqmuxa), + .I1(plm_rx0_des_dat[9]), + .LO(plm_dfm_deframe1_reg_dat_6[9]) + ); + defparam plm_dfm_deframe1_reg_dat_6_0_a2_0_a2_0_a4_8_.INIT = 4'h8; + LUT2_L plm_dfm_deframe1_reg_dat_6_0_a2_0_a2_0_a4_8_ ( + .I0(plm_dfm_deframe1_reg_dat_1_sqmuxa), + .I1(plm_rx0_des_dat[8]), + .LO(plm_dfm_deframe1_reg_dat_6[8]) + ); + defparam plm_dfm_deframe1_reg_dat_6_0_a2_0_a2_0_a4_7_.INIT = 4'h8; + LUT2_L plm_dfm_deframe1_reg_dat_6_0_a2_0_a2_0_a4_7_ ( + .I0(plm_dfm_deframe1_reg_dat_1_sqmuxa_1), + .I1(plm_rx0_des_dat[7]), + .LO(plm_dfm_deframe1_reg_dat_6[7]) + ); + defparam plm_dfm_deframe1_reg_dat_6_0_a2_0_a2_0_a4_6_.INIT = 4'h8; + LUT2_L plm_dfm_deframe1_reg_dat_6_0_a2_0_a2_0_a4_6_ ( + .I0(plm_dfm_deframe1_reg_dat_1_sqmuxa_1), + .I1(plm_rx0_des_dat[6]), + .LO(plm_dfm_deframe1_reg_dat_6[6]) + ); + defparam plm_dfm_deframe1_reg_dat_6_0_a2_0_a2_0_a4_5_.INIT = 4'h8; + LUT2_L plm_dfm_deframe1_reg_dat_6_0_a2_0_a2_0_a4_5_ ( + .I0(plm_dfm_deframe1_reg_dat_1_sqmuxa_1), + .I1(plm_rx0_des_dat[5]), + .LO(plm_dfm_deframe1_reg_dat_6[5]) + ); + defparam plm_dfm_deframe1_reg_dat_6_0_a2_0_a2_0_a4_4_.INIT = 4'h8; + LUT2_L plm_dfm_deframe1_reg_dat_6_0_a2_0_a2_0_a4_4_ ( + .I0(plm_dfm_deframe1_reg_dat_1_sqmuxa_1), + .I1(plm_rx0_des_dat[4]), + .LO(plm_dfm_deframe1_reg_dat_6[4]) + ); + defparam plm_dfm_deframe1_reg_dat_6_0_a2_0_a2_0_a4_3_.INIT = 4'h8; + LUT2_L plm_dfm_deframe1_reg_dat_6_0_a2_0_a2_0_a4_3_ ( + .I0(plm_dfm_deframe1_reg_dat_1_sqmuxa_1), + .I1(plm_rx0_des_dat[3]), + .LO(plm_dfm_deframe1_reg_dat_6[3]) + ); + defparam plm_dfm_deframe1_reg_dat_6_0_a2_0_a2_0_a4_2_.INIT = 4'h8; + LUT2_L plm_dfm_deframe1_reg_dat_6_0_a2_0_a2_0_a4_2_ ( + .I0(plm_dfm_deframe1_reg_dat_1_sqmuxa_1), + .I1(plm_rx0_des_dat[2]), + .LO(plm_dfm_deframe1_reg_dat_6[2]) + ); + defparam plm_dfm_deframe1_reg_dat_6_0_a2_0_a2_0_a4_1_.INIT = 4'h8; + LUT2_L plm_dfm_deframe1_reg_dat_6_0_a2_0_a2_0_a4_1_ ( + .I0(plm_dfm_deframe1_reg_dat_1_sqmuxa_1), + .I1(plm_rx0_des_dat[1]), + .LO(plm_dfm_deframe1_reg_dat_6[1]) + ); + defparam plm_dfm_deframe1_reg_dat_6_0_a2_0_a2_0_a4_0_.INIT = 4'h8; + LUT2_L plm_dfm_deframe1_reg_dat_6_0_a2_0_a2_0_a4_0_ ( + .I0(plm_dfm_deframe1_reg_dat_1_sqmuxa_1), + .I1(plm_rx0_des_dat[0]), + .LO(plm_dfm_deframe1_reg_dat_6[0]) + ); + defparam plm_dfm_deframe1_filter_reg_any_end_6_i_0_0_1_.INIT = 8'hA8; + LUT3_L plm_dfm_deframe1_filter_reg_any_end_6_i_0_0_1_ ( + .I0(plm_link_l0), + .I1(plm_rx0_des_edb[1]), + .I2(plm_rx0_des_edg[1]), + .LO(plm_dfm_deframe1_N_13549_i) + ); + defparam plm_dfm_deframe1_filter_reg_any_end_6_i_0_0_0_.INIT = 8'hA8; + LUT3_L plm_dfm_deframe1_filter_reg_any_end_6_i_0_0_0_ ( + .I0(plm_link_l0), + .I1(plm_rx0_des_edb[0]), + .I2(plm_rx0_des_edg[0]), + .LO(plm_dfm_deframe1_N_13547_i) + ); + defparam plm_dfm_deframe1_filter_reg_stp_5_0_a2_0_a2_0_a4_1_.INIT = 4'h8; + LUT2_L plm_dfm_deframe1_filter_reg_stp_5_0_a2_0_a2_0_a4_1_ ( + .I0(plm_link_l0), + .I1(plm_rx0_des_stp[1]), + .LO(plm_dfm_deframe1_reg_stp_5[1]) + ); + defparam plm_dfm_deframe1_filter_reg_stp_5_0_a2_0_a2_0_a4_0_.INIT = 4'h8; + LUT2_L plm_dfm_deframe1_filter_reg_stp_5_0_a2_0_a2_0_a4_0_ ( + .I0(plm_link_l0), + .I1(plm_rx0_des_stp[0]), + .LO(plm_dfm_deframe1_reg_stp_5[0]) + ); + defparam plm_dfm_deframe1_filter_reg_sdp_5_0_a2_0_a2_0_a4_1_.INIT = 4'h8; + LUT2_L plm_dfm_deframe1_filter_reg_sdp_5_0_a2_0_a2_0_a4_1_ ( + .I0(plm_link_l0), + .I1(plm_rx0_des_sdp[1]), + .LO(plm_dfm_deframe1_reg_sdp_5[1]) + ); + defparam plm_dfm_deframe1_filter_reg_sdp_5_0_a2_0_a2_0_a4_0_.INIT = 4'h8; + LUT2_L plm_dfm_deframe1_filter_reg_sdp_5_0_a2_0_a2_0_a4_0_ ( + .I0(plm_link_l0), + .I1(plm_rx0_des_sdp[0]), + .LO(plm_dfm_deframe1_reg_sdp_5[0]) + ); + defparam plm_dfm_deframe1_filter_reg_edg_5_0_a2_0_a2_0_a4_1_.INIT = 4'h8; + LUT2_L plm_dfm_deframe1_filter_reg_edg_5_0_a2_0_a2_0_a4_1_ ( + .I0(plm_link_l0), + .I1(plm_rx0_des_edg[1]), + .LO(plm_dfm_deframe1_reg_edg_5[1]) + ); + defparam plm_dfm_deframe1_filter_reg_edg_5_0_a2_0_a2_0_a4_0_.INIT = 4'h8; + LUT2_L plm_dfm_deframe1_filter_reg_edg_5_0_a2_0_a2_0_a4_0_ ( + .I0(plm_link_l0), + .I1(plm_rx0_des_edg[0]), + .LO(plm_dfm_deframe1_reg_edg_5[0]) + ); + defparam plm_dfm_deframe1_filter_reg_edb_5_0_a2_0_a2_0_a4_1_.INIT = 4'h8; + LUT2_L plm_dfm_deframe1_filter_reg_edb_5_0_a2_0_a2_0_a4_1_ ( + .I0(plm_link_l0), + .I1(plm_rx0_des_edb[1]), + .LO(plm_dfm_deframe1_reg_edb_5[1]) + ); + defparam plm_dfm_deframe1_filter_reg_edb_5_0_a2_0_a2_0_a4_0_.INIT = 4'h8; + LUT2_L plm_dfm_deframe1_filter_reg_edb_5_0_a2_0_a2_0_a4_0_ ( + .I0(plm_link_l0), + .I1(plm_rx0_des_edb[0]), + .LO(plm_dfm_deframe1_reg_edb_5[0]) + ); + defparam plm_dfm_deframe1_reg_dat_6_0_a2_0_a2_0_a4_15_.INIT = 4'h8; + LUT2_L plm_dfm_deframe1_reg_dat_6_0_a2_0_a2_0_a4_15_ ( + .I0(plm_dfm_deframe1_reg_dat_1_sqmuxa), + .I1(plm_rx0_des_dat[15]), + .LO(plm_dfm_deframe1_reg_dat_6[15]) + ); + defparam plm_dfm_deframe1_reg_dat_6_0_a2_0_a2_0_a4_14_.INIT = 4'h8; + LUT2_L plm_dfm_deframe1_reg_dat_6_0_a2_0_a2_0_a4_14_ ( + .I0(plm_dfm_deframe1_reg_dat_1_sqmuxa), + .I1(plm_rx0_des_dat[14]), + .LO(plm_dfm_deframe1_reg_dat_6[14]) + ); + defparam plm_dfm_deframe1_reg_dat_6_0_a2_0_a2_0_a4_13_.INIT = 4'h8; + LUT2_L plm_dfm_deframe1_reg_dat_6_0_a2_0_a2_0_a4_13_ ( + .I0(plm_dfm_deframe1_reg_dat_1_sqmuxa), + .I1(plm_rx0_des_dat[13]), + .LO(plm_dfm_deframe1_reg_dat_6[13]) + ); + defparam plm_dfm_deframe1_filter_N_42622_i.INIT = 16'hFFF7; + LUT4_L plm_dfm_deframe1_filter_N_42622_i ( + .I0(plm_dfm_deframe1_reg_any_bad_6_0_a2_0_a2_0_a2_4[1]), + .I1(plm_link_l0), + .I2(plm_rx0_des_idl[1]), + .I3(plm_rx0_des_skp[1]), + .LO(plm_dfm_deframe1_N_42622_i) + ); + defparam plm_dfm_deframe1_filter_N_42621_i.INIT = 16'hFFF7; + LUT4_L plm_dfm_deframe1_filter_N_42621_i ( + .I0(plm_dfm_deframe1_reg_any_bad_6_0_a2_0_a2_0_a2_4[0]), + .I1(plm_link_l0), + .I2(plm_rx0_des_idl[0]), + .I3(plm_rx0_des_skp[0]), + .LO(plm_dfm_deframe1_N_42621_i) + ); + defparam plm_dfm_deframe1_filter_reg_any_sta_6_i_0_0_1_.INIT = 8'hA8; + LUT3_L plm_dfm_deframe1_filter_reg_any_sta_6_i_0_0_1_ ( + .I0(plm_link_l0), + .I1(plm_rx0_des_sdp[1]), + .I2(plm_rx0_des_stp[1]), + .LO(plm_dfm_deframe1_N_13553_i) + ); + defparam plm_dfm_deframe1_filter_reg_any_sta_6_i_0_0_0_.INIT = 8'hA8; + LUT3_L plm_dfm_deframe1_filter_reg_any_sta_6_i_0_0_0_ ( + .I0(plm_link_l0), + .I1(plm_rx0_des_sdp[0]), + .I2(plm_rx0_des_stp[0]), + .LO(plm_dfm_deframe1_N_13551_i) + ); + defparam plm_dfm_deframe1_detect_and_stretch_N_42623_i.INIT = 16'hFFFD; + LUT4_L plm_dfm_deframe1_detect_and_stretch_N_42623_i ( + .I0(plm_dfm_deframe1_det_d0_i), + .I1(plm_dfm_deframe1_reg_det_d1_686), + .I2(plm_dfm_deframe1_reg_det_d2_687), + .I3(plm_dfm_deframe1_reg_det_d3_688), + .LO(plm_dfm_deframe1_N_42623_i) + ); + FDC plm_dfm_deframe1_reg_det_d2 ( + .C(mgt_clk), + .D(plm_dfm_deframe1_reg_det_d1_686), + .Q(plm_dfm_deframe1_reg_det_d2_687), + .CLR(plm_rst) + ); + FDC plm_dfm_deframe1_reg_det_d1 ( + .C(mgt_clk), + .D(plm_dfm_deframe1_det_d0_i_i_689), + .Q(plm_dfm_deframe1_reg_det_d1_686), + .CLR(plm_rst) + ); + FDC plm_dfm_deframe1_reg_det_d3 ( + .C(mgt_clk), + .D(plm_dfm_deframe1_reg_det_d2_687), + .Q(plm_dfm_deframe1_reg_det_d3_688), + .CLR(plm_rst) + ); + FDC plm_dfm_deframe1_reg_dat_12_ ( + .C(mgt_clk), + .D(plm_dfm_deframe1_reg_dat_6[12]), + .Q(plm_dfm_deframe1_reg_dat[12]), + .CLR(plm_rst) + ); + FDC plm_dfm_deframe1_reg_dat_11_ ( + .C(mgt_clk), + .D(plm_dfm_deframe1_reg_dat_6[11]), + .Q(plm_dfm_deframe1_reg_dat[11]), + .CLR(plm_rst) + ); + FDC plm_dfm_deframe1_reg_dat_10_ ( + .C(mgt_clk), + .D(plm_dfm_deframe1_reg_dat_6[10]), + .Q(plm_dfm_deframe1_reg_dat[10]), + .CLR(plm_rst) + ); + FDC plm_dfm_deframe1_reg_dat_9_ ( + .C(mgt_clk), + .D(plm_dfm_deframe1_reg_dat_6[9]), + .Q(plm_dfm_deframe1_reg_dat[9]), + .CLR(plm_rst) + ); + FDC plm_dfm_deframe1_reg_dat_8_ ( + .C(mgt_clk), + .D(plm_dfm_deframe1_reg_dat_6[8]), + .Q(plm_dfm_deframe1_reg_dat[8]), + .CLR(plm_rst) + ); + FDC plm_dfm_deframe1_reg_dat_7_ ( + .C(mgt_clk), + .D(plm_dfm_deframe1_reg_dat_6[7]), + .Q(plm_dfm_deframe1_reg_dat[7]), + .CLR(plm_rst) + ); + FDC plm_dfm_deframe1_reg_dat_6_ ( + .C(mgt_clk), + .D(plm_dfm_deframe1_reg_dat_6[6]), + .Q(plm_dfm_deframe1_reg_dat[6]), + .CLR(plm_rst) + ); + FDC plm_dfm_deframe1_reg_dat_5_ ( + .C(mgt_clk), + .D(plm_dfm_deframe1_reg_dat_6[5]), + .Q(plm_dfm_deframe1_reg_dat[5]), + .CLR(plm_rst) + ); + FDC plm_dfm_deframe1_reg_dat_4_ ( + .C(mgt_clk), + .D(plm_dfm_deframe1_reg_dat_6[4]), + .Q(plm_dfm_deframe1_reg_dat[4]), + .CLR(plm_rst) + ); + FDC plm_dfm_deframe1_reg_dat_3_ ( + .C(mgt_clk), + .D(plm_dfm_deframe1_reg_dat_6[3]), + .Q(plm_dfm_deframe1_reg_dat[3]), + .CLR(plm_rst) + ); + FDC plm_dfm_deframe1_reg_dat_2_ ( + .C(mgt_clk), + .D(plm_dfm_deframe1_reg_dat_6[2]), + .Q(plm_dfm_deframe1_reg_dat[2]), + .CLR(plm_rst) + ); + FDC plm_dfm_deframe1_reg_dat_1_ ( + .C(mgt_clk), + .D(plm_dfm_deframe1_reg_dat_6[1]), + .Q(plm_dfm_deframe1_reg_dat[1]), + .CLR(plm_rst) + ); + FDC plm_dfm_deframe1_reg_dat_0_ ( + .C(mgt_clk), + .D(plm_dfm_deframe1_reg_dat_6[0]), + .Q(plm_dfm_deframe1_reg_dat[0]), + .CLR(plm_rst) + ); + FDC plm_dfm_deframe1_reg_any_end_1_ ( + .C(mgt_clk), + .D(plm_dfm_deframe1_N_13549_i), + .Q(plm_dfm_deframe1_reg_any_end[1]), + .CLR(plm_rst) + ); + FDC plm_dfm_deframe1_reg_any_end_0_ ( + .C(mgt_clk), + .D(plm_dfm_deframe1_N_13547_i), + .Q(plm_dfm_deframe1_reg_any_end[0]), + .CLR(plm_rst) + ); + FDC plm_dfm_deframe1_reg_stp_1_ ( + .C(mgt_clk), + .D(plm_dfm_deframe1_reg_stp_5[1]), + .Q(plm_dfm_deframe1_reg_stp[1]), + .CLR(plm_rst) + ); + FDC plm_dfm_deframe1_reg_stp_0_ ( + .C(mgt_clk), + .D(plm_dfm_deframe1_reg_stp_5[0]), + .Q(plm_dfm_deframe1_reg_stp[0]), + .CLR(plm_rst) + ); + FDC plm_dfm_deframe1_reg_sdp_1_ ( + .C(mgt_clk), + .D(plm_dfm_deframe1_reg_sdp_5[1]), + .Q(plm_dfm_deframe1_reg_sdp[1]), + .CLR(plm_rst) + ); + FDC plm_dfm_deframe1_reg_sdp_0_ ( + .C(mgt_clk), + .D(plm_dfm_deframe1_reg_sdp_5[0]), + .Q(plm_dfm_deframe1_reg_sdp[0]), + .CLR(plm_rst) + ); + FDC plm_dfm_deframe1_reg_edg_1_ ( + .C(mgt_clk), + .D(plm_dfm_deframe1_reg_edg_5[1]), + .Q(plm_dfm_deframe1_reg_edg[1]), + .CLR(plm_rst) + ); + FDC plm_dfm_deframe1_reg_edg_0_ ( + .C(mgt_clk), + .D(plm_dfm_deframe1_reg_edg_5[0]), + .Q(plm_dfm_deframe1_reg_edg[0]), + .CLR(plm_rst) + ); + FDC plm_dfm_deframe1_reg_edb_1_ ( + .C(mgt_clk), + .D(plm_dfm_deframe1_reg_edb_5[1]), + .Q(plm_dfm_deframe1_reg_edb[1]), + .CLR(plm_rst) + ); + FDC plm_dfm_deframe1_reg_edb_0_ ( + .C(mgt_clk), + .D(plm_dfm_deframe1_reg_edb_5[0]), + .Q(plm_dfm_deframe1_reg_edb[0]), + .CLR(plm_rst) + ); + FDC plm_dfm_deframe1_reg_any_sym_1_ ( + .C(mgt_clk), + .D(plm_dfm_deframe1_reg_dat_1_sqmuxa), + .Q(plm_dfm_deframe1_reg_any_sym[1]), + .CLR(plm_rst) + ); + FDC plm_dfm_deframe1_reg_any_sym_0_ ( + .C(mgt_clk), + .D(plm_dfm_deframe1_reg_dat_1_sqmuxa_1), + .Q(plm_dfm_deframe1_reg_any_sym[0]), + .CLR(plm_rst) + ); + FDC plm_dfm_deframe1_reg_dat_15_ ( + .C(mgt_clk), + .D(plm_dfm_deframe1_reg_dat_6[15]), + .Q(plm_dfm_deframe1_reg_dat[15]), + .CLR(plm_rst) + ); + FDC plm_dfm_deframe1_reg_dat_14_ ( + .C(mgt_clk), + .D(plm_dfm_deframe1_reg_dat_6[14]), + .Q(plm_dfm_deframe1_reg_dat[14]), + .CLR(plm_rst) + ); + FDC plm_dfm_deframe1_reg_dat_13_ ( + .C(mgt_clk), + .D(plm_dfm_deframe1_reg_dat_6[13]), + .Q(plm_dfm_deframe1_reg_dat[13]), + .CLR(plm_rst) + ); + FDC plm_dfm_deframe1_reg_delay_dat_2_ ( + .C(mgt_clk), + .D(plm_dfm_deframe1_reg_dat[2]), + .Q(plm_dfm_deframe1_reg_delay_dat[2]), + .CLR(plm_rst) + ); + FDC plm_dfm_deframe1_reg_delay_dat_1_ ( + .C(mgt_clk), + .D(plm_dfm_deframe1_reg_dat[1]), + .Q(plm_dfm_deframe1_reg_delay_dat[1]), + .CLR(plm_rst) + ); + FDC plm_dfm_deframe1_reg_delay_dat_0_ ( + .C(mgt_clk), + .D(plm_dfm_deframe1_reg_dat[0]), + .Q(plm_dfm_deframe1_reg_delay_dat[0]), + .CLR(plm_rst) + ); + FDC plm_dfm_deframe1_reg_delay_stp_1_ ( + .C(mgt_clk), + .D(plm_dfm_deframe1_reg_stp[1]), + .Q(plm_dfm_deframe1_reg_delay_stp[1]), + .CLR(plm_rst) + ); + FDC plm_dfm_deframe1_reg_delay_stp_0_ ( + .C(mgt_clk), + .D(plm_dfm_deframe1_reg_stp[0]), + .Q(plm_dfm_deframe1_reg_delay_stp[0]), + .CLR(plm_rst) + ); + FDC plm_dfm_deframe1_reg_delay_sdp_1_ ( + .C(mgt_clk), + .D(plm_dfm_deframe1_reg_sdp[1]), + .Q(plm_dfm_deframe1_reg_delay_sdp[1]), + .CLR(plm_rst) + ); + FDC plm_dfm_deframe1_reg_delay_sdp_0_ ( + .C(mgt_clk), + .D(plm_dfm_deframe1_reg_sdp[0]), + .Q(plm_dfm_deframe1_reg_delay_sdp[0]), + .CLR(plm_rst) + ); + FDC plm_dfm_deframe1_reg_delay_edg_1_ ( + .C(mgt_clk), + .D(plm_dfm_deframe1_reg_edg[1]), + .Q(plm_dfm_deframe1_reg_delay_edg[1]), + .CLR(plm_rst) + ); + FDC plm_dfm_deframe1_reg_delay_edg_0_ ( + .C(mgt_clk), + .D(plm_dfm_deframe1_reg_edg[0]), + .Q(plm_dfm_deframe1_reg_delay_edg[0]), + .CLR(plm_rst) + ); + FDC plm_dfm_deframe1_reg_delay_edb_1_ ( + .C(mgt_clk), + .D(plm_dfm_deframe1_reg_edb[1]), + .Q(plm_dfm_deframe1_reg_delay_edb[1]), + .CLR(plm_rst) + ); + FDC plm_dfm_deframe1_reg_delay_edb_0_ ( + .C(mgt_clk), + .D(plm_dfm_deframe1_reg_edb[0]), + .Q(plm_dfm_deframe1_reg_delay_edb[0]), + .CLR(plm_rst) + ); + FDP plm_dfm_deframe1_reg_any_bad_1_ ( + .PRE(plm_rst), + .C(mgt_clk), + .D(plm_dfm_deframe1_N_42622_i), + .Q(plm_dfm_deframe1_reg_any_bad[1]) + ); + FDP plm_dfm_deframe1_reg_any_bad_0_ ( + .PRE(plm_rst), + .C(mgt_clk), + .D(plm_dfm_deframe1_N_42621_i), + .Q(plm_dfm_deframe1_reg_any_bad[0]) + ); + FDC plm_dfm_deframe1_reg_any_sta_1_ ( + .C(mgt_clk), + .D(plm_dfm_deframe1_N_13553_i), + .Q(plm_dfm_deframe1_reg_any_sta[1]), + .CLR(plm_rst) + ); + FDC plm_dfm_deframe1_reg_any_sta_0_ ( + .C(mgt_clk), + .D(plm_dfm_deframe1_N_13551_i), + .Q(plm_dfm_deframe1_reg_any_sta[0]), + .CLR(plm_rst) + ); + FDC plm_dfm_deframe1_reg_delay_dat_15_ ( + .C(mgt_clk), + .D(plm_dfm_deframe1_reg_dat[15]), + .Q(plm_dfm_deframe1_reg_delay_dat[15]), + .CLR(plm_rst) + ); + FDC plm_dfm_deframe1_reg_delay_dat_14_ ( + .C(mgt_clk), + .D(plm_dfm_deframe1_reg_dat[14]), + .Q(plm_dfm_deframe1_reg_delay_dat[14]), + .CLR(plm_rst) + ); + FDC plm_dfm_deframe1_reg_delay_dat_13_ ( + .C(mgt_clk), + .D(plm_dfm_deframe1_reg_dat[13]), + .Q(plm_dfm_deframe1_reg_delay_dat[13]), + .CLR(plm_rst) + ); + FDC plm_dfm_deframe1_reg_delay_dat_12_ ( + .C(mgt_clk), + .D(plm_dfm_deframe1_reg_dat[12]), + .Q(plm_dfm_deframe1_reg_delay_dat[12]), + .CLR(plm_rst) + ); + FDC plm_dfm_deframe1_reg_delay_dat_11_ ( + .C(mgt_clk), + .D(plm_dfm_deframe1_reg_dat[11]), + .Q(plm_dfm_deframe1_reg_delay_dat[11]), + .CLR(plm_rst) + ); + FDC plm_dfm_deframe1_reg_delay_dat_10_ ( + .C(mgt_clk), + .D(plm_dfm_deframe1_reg_dat[10]), + .Q(plm_dfm_deframe1_reg_delay_dat[10]), + .CLR(plm_rst) + ); + FDC plm_dfm_deframe1_reg_delay_dat_9_ ( + .C(mgt_clk), + .D(plm_dfm_deframe1_reg_dat[9]), + .Q(plm_dfm_deframe1_reg_delay_dat[9]), + .CLR(plm_rst) + ); + FDC plm_dfm_deframe1_reg_delay_dat_8_ ( + .C(mgt_clk), + .D(plm_dfm_deframe1_reg_dat[8]), + .Q(plm_dfm_deframe1_reg_delay_dat[8]), + .CLR(plm_rst) + ); + FDC plm_dfm_deframe1_reg_delay_dat_7_ ( + .C(mgt_clk), + .D(plm_dfm_deframe1_reg_dat[7]), + .Q(plm_dfm_deframe1_reg_delay_dat[7]), + .CLR(plm_rst) + ); + FDC plm_dfm_deframe1_reg_delay_dat_6_ ( + .C(mgt_clk), + .D(plm_dfm_deframe1_reg_dat[6]), + .Q(plm_dfm_deframe1_reg_delay_dat[6]), + .CLR(plm_rst) + ); + FDC plm_dfm_deframe1_reg_delay_dat_5_ ( + .C(mgt_clk), + .D(plm_dfm_deframe1_reg_dat[5]), + .Q(plm_dfm_deframe1_reg_delay_dat[5]), + .CLR(plm_rst) + ); + FDC plm_dfm_deframe1_reg_delay_dat_4_ ( + .C(mgt_clk), + .D(plm_dfm_deframe1_reg_dat[4]), + .Q(plm_dfm_deframe1_reg_delay_dat[4]), + .CLR(plm_rst) + ); + FDC plm_dfm_deframe1_reg_delay_dat_3_ ( + .C(mgt_clk), + .D(plm_dfm_deframe1_reg_dat[3]), + .Q(plm_dfm_deframe1_reg_delay_dat[3]), + .CLR(plm_rst) + ); + FDCE plm_dfm_deframe1_reg_by1_prec_rcverr ( + .CE(plm_phy_cke_0_402), + .C(mgt_clk), + .D(plm_dfm_deframe1_N_42623_i), + .Q(plm_dfm_by1_prec_rcverr), + .CLR(plm_rst) + ); + defparam plm_dfm_deframe1_det_d0_i_i.INIT = 4'hE; + LUT2_L plm_dfm_deframe1_det_d0_i_i ( + .I0(plm_rx0_des_bad[1]), + .I1(plm_rx0_des_bad[0]), + .LO(plm_dfm_deframe1_det_d0_i_i_689) + ); + defparam plm_dfm_deframe1_dwfsm_reg_push_0_a4_0_a3_1_.INIT = 4'h4; + LUT2 plm_dfm_deframe1_dwfsm_reg_push_0_a4_0_a3_1_ ( + .I0(plm_dfm_deframe1_dwfsm_reg_fsm_last_substate[1]), + .I1(plm_dfm_deframe1_dwfsm_reg_fsm_substate[1]), + .O(plm_dfm_deframe1_push1) + ); + defparam plm_dfm_deframe1_dwfsm_ns_fsm_substate_i_i_a3_1_1_.INIT = 4'h1; + LUT2 plm_dfm_deframe1_dwfsm_ns_fsm_substate_i_i_a3_1_1_ ( + .I0(plm_dfm_deframe1_reg_any_bad[0]), + .I1(plm_dfm_deframe1_reg_any_end[0]), + .O(plm_dfm_deframe1_dwfsm_N_18673_1) + ); + defparam plm_dfm_deframe1_dwfsm_valid_on_third_symbol_reg_ferr_40_i_i_a3_1_0.INIT = 4'h8; + LUT2_L plm_dfm_deframe1_dwfsm_valid_on_third_symbol_reg_ferr_40_i_i_a3_1_0 ( + .I0(plm_dfm_deframe1_reg_any_end[0]), + .I1(plm_dfm_deframe1_reg_any_sym[1]), + .LO(plm_dfm_deframe1_dwfsm_reg_ferr_40_i_i_a3_1_0) + ); + defparam plm_dfm_deframe1_dwfsm_ns_fsm_framing_iv_i_i_a3_1.INIT = 8'h08; + LUT3_L plm_dfm_deframe1_dwfsm_ns_fsm_framing_iv_i_i_a3_1 ( + .I0(plm_dfm_deframe1_dwfsm_reg_fsm_errored_699), + .I1(plm_dfm_deframe1_dwfsm_reg_fsm_framing_698), + .I2(plm_dfm_deframe1_dwfsm_reg_fsm_substate[1]), + .LO(plm_dfm_deframe1_dwfsm_ns_fsm_framing_iv_i_i_a3_1_690) + ); + defparam plm_dfm_deframe1_dwfsm_reg_push_i_i_3_.INIT = 16'h008C; + LUT4 plm_dfm_deframe1_dwfsm_reg_push_i_i_3_ ( + .I0(plm_dfm_deframe1_dwfsm_reg_fsm_last_substate[0]), + .I1(plm_dfm_deframe1_dwfsm_reg_fsm_last_substate[1]), + .I2(plm_dfm_deframe1_dwfsm_reg_fsm_substate[0]), + .I3(plm_dfm_deframe1_dwfsm_reg_fsm_substate[1]), + .O(plm_dfm_deframe1_N_18645_i) + ); + defparam plm_dfm_deframe1_dwfsm_ns_fsm_framing_iv_i_i_a3_0_1.INIT = 8'h01; + LUT3 plm_dfm_deframe1_dwfsm_ns_fsm_framing_iv_i_i_a3_0_1 ( + .I0(plm_dfm_deframe1_reg_any_bad[1]), + .I1(plm_dfm_deframe1_reg_any_end[1]), + .I2(plm_dfm_deframe1_reg_any_sym[1]), + .O(plm_dfm_deframe1_dwfsm_N_18662_1) + ); + defparam plm_dfm_deframe1_dwfsm_reg_push_i_i_0_.INIT = 16'h1190; + LUT4 plm_dfm_deframe1_dwfsm_reg_push_i_i_0_ ( + .I0(plm_dfm_deframe1_dwfsm_reg_fsm_last_substate[0]), + .I1(plm_dfm_deframe1_dwfsm_reg_fsm_last_substate[1]), + .I2(plm_dfm_deframe1_dwfsm_reg_fsm_substate[0]), + .I3(plm_dfm_deframe1_dwfsm_reg_fsm_substate[1]), + .O(plm_dfm_deframe1_N_18643_i) + ); + defparam plm_dfm_deframe1_dwfsm_ns_fsm_errored_iv_0_0.INIT = 16'h3704; + LUT4_L plm_dfm_deframe1_dwfsm_ns_fsm_errored_iv_0_0 ( + .I0(plm_dfm_deframe1_dwfsm_reg_fsm_errored_699), + .I1(plm_dfm_deframe1_dwfsm_reg_fsm_framing_698), + .I2(plm_dfm_deframe1_dwfsm_reg_fsm_substate[1]), + .I3(plm_dfm_deframe1_reg_any_sta[1]), + .LO(plm_dfm_deframe1_dwfsm_ns_fsm_errored_iv_0_0_691) + ); + defparam plm_dfm_deframe1_dwfsm_reg_push_0_i_2_.INIT = 16'h0FFB; + LUT4 plm_dfm_deframe1_dwfsm_reg_push_0_i_2_ ( + .I0(plm_dfm_deframe1_dwfsm_reg_fsm_last_substate[0]), + .I1(plm_dfm_deframe1_dwfsm_reg_fsm_last_substate[1]), + .I2(plm_dfm_deframe1_dwfsm_reg_fsm_substate[0]), + .I3(plm_dfm_deframe1_dwfsm_reg_fsm_substate[1]), + .O(plm_dfm_deframe1_reg_push_0_i[2]) + ); + defparam plm_dfm_deframe1_dwfsm_ns_fsm_framing_iv_i_i_o4.INIT = 16'h5111; + LUT4 plm_dfm_deframe1_dwfsm_ns_fsm_framing_iv_i_i_o4 ( + .I0(plm_dfm_deframe1_dwfsm_reg_fsm_errored_699), + .I1(plm_dfm_deframe1_dwfsm_reg_fsm_substate[1]), + .I2(plm_dfm_deframe1_reg_any_sym[0]), + .I3(plm_dfm_deframe1_reg_any_sym[1]), + .O(plm_dfm_deframe1_dwfsm_ns_fsm_framing_iv_i_i_o4_697) + ); + defparam plm_dfm_deframe1_dwfsm_ns_fsm_framing_iv_i_i_a3_3.INIT = 16'h0002; + LUT4 plm_dfm_deframe1_dwfsm_ns_fsm_framing_iv_i_i_a3_3 ( + .I0(plm_dfm_deframe1_dwfsm_N_18673_1), + .I1(plm_dfm_deframe1_dwfsm_reg_fsm_framing_698), + .I2(plm_dfm_deframe1_reg_any_sta[0]), + .I3(plm_dfm_deframe1_reg_any_sym[0]), + .O(plm_dfm_deframe1_dwfsm_ns_fsm_framing_iv_i_i_a3_3_693) + ); + defparam plm_dfm_deframe1_dwfsm_ns_fsm_substate_i_i_a3_1_.INIT = 16'h0008; + LUT4_L plm_dfm_deframe1_dwfsm_ns_fsm_substate_i_i_a3_1_ ( + .I0(plm_dfm_deframe1_dwfsm_N_18673_1), + .I1(plm_dfm_deframe1_dwfsm_reg_fsm_substate[1]), + .I2(plm_dfm_deframe1_reg_any_sta[0]), + .I3(plm_dfm_deframe1_reg_any_sym[0]), + .LO(plm_dfm_deframe1_dwfsm_ns_fsm_substate_i_i_a3[1]) + ); + defparam plm_dfm_deframe1_dwfsm_ns_fsm_framing_iv_i_i_a3_0.INIT = 16'h00A2; + LUT4 plm_dfm_deframe1_dwfsm_ns_fsm_framing_iv_i_i_a3_0 ( + .I0(plm_dfm_deframe1_dwfsm_N_18662_1), + .I1(plm_dfm_deframe1_dwfsm_reg_fsm_framing_698), + .I2(plm_dfm_deframe1_dwfsm_reg_fsm_substate[1]), + .I3(plm_dfm_deframe1_reg_any_sta[1]), + .O(plm_dfm_deframe1_dwfsm_ns_fsm_framing_iv_i_i_a3_0_694) + ); + defparam plm_dfm_deframe1_dwfsm_valid_on_third_symbol_reg_ferr_40_i_i_0.INIT = 16'hABEF; + LUT4_L plm_dfm_deframe1_dwfsm_valid_on_third_symbol_reg_ferr_40_i_i_0 ( + .I0(plm_dfm_deframe1_dwfsm_reg_fsm_errored_699), + .I1(plm_dfm_deframe1_dwfsm_reg_fsm_substate[0]), + .I2(plm_dfm_deframe1_dwfsm_reg_ferr_40_i_i_a3_1_0), + .I3(plm_dfm_deframe1_reg_any_end[1]), + .LO(plm_dfm_deframe1_dwfsm_reg_ferr_40_i_i_0) + ); + defparam plm_dfm_deframe1_dwfsm_ns_fsm_framing_iv_i_i_0.INIT = 16'h5554; + LUT4 plm_dfm_deframe1_dwfsm_ns_fsm_framing_iv_i_i_0 ( + .I0(plm_dfm_deframe1_dwfsm_ns_fsm_framing_iv_i_i_a3_1_690), + .I1(plm_dfm_deframe1_dwfsm_reg_fsm_framing_698), + .I2(plm_dfm_deframe1_reg_any_sta[0]), + .I3(plm_dfm_deframe1_reg_any_sta[1]), + .O(plm_dfm_deframe1_dwfsm_ns_fsm_framing_iv_i_i_0_692) + ); + defparam plm_dfm_deframe1_dwfsm_ns_fsm_errored_iv_0_1.INIT = 16'h2AAA; + LUT4_L plm_dfm_deframe1_dwfsm_ns_fsm_errored_iv_0_1 ( + .I0(plm_dfm_deframe1_dwfsm_ns_fsm_errored_iv_0_0_691), + .I1(plm_dfm_deframe1_dwfsm_reg_fsm_framing_698), + .I2(plm_dfm_deframe1_reg_any_sym[0]), + .I3(plm_dfm_deframe1_reg_any_sym[1]), + .LO(plm_dfm_deframe1_dwfsm_ns_fsm_errored_iv_0_1_696) + ); + defparam plm_dfm_deframe1_dwfsm_ns_fsm_framing_iv_i_i_a3.INIT = 16'h0444; + LUT4_L plm_dfm_deframe1_dwfsm_ns_fsm_framing_iv_i_i_a3 ( + .I0(plm_dfm_deframe1_dwfsm_ns_fsm_framing_iv_i_i_o4_697), + .I1(plm_dfm_deframe1_dwfsm_reg_fsm_framing_698), + .I2(plm_dfm_deframe1_dwfsm_reg_fsm_substate[0]), + .I3(plm_dfm_deframe1_reg_any_sta[0]), + .LO(plm_dfm_deframe1_dwfsm_ns_fsm_framing_iv_i_i_a3_695) + ); + defparam plm_dfm_deframe1_dwfsm_ns_fsm_substate_i_i_1_0_.INIT = 16'hD1C0; + LUT4_L plm_dfm_deframe1_dwfsm_ns_fsm_substate_i_i_1_0_ ( + .I0(plm_dfm_deframe1_dwfsm_N_18662_1), + .I1(plm_dfm_deframe1_dwfsm_reg_fsm_framing_698), + .I2(plm_dfm_deframe1_dwfsm_reg_fsm_substate[0]), + .I3(plm_dfm_deframe1_reg_any_sta[0]), + .LO(plm_dfm_deframe1_dwfsm_ns_fsm_substate_i_i_1[0]) + ); + defparam plm_dfm_deframe1_dwfsm_ns_fsm_framing_iv_i_i.INIT = 16'h0100; + LUT4_L plm_dfm_deframe1_dwfsm_ns_fsm_framing_iv_i_i ( + .I0(plm_dfm_deframe1_dwfsm_ns_fsm_framing_iv_i_i_a3_695), + .I1(plm_dfm_deframe1_dwfsm_ns_fsm_framing_iv_i_i_a3_0_694), + .I2(plm_dfm_deframe1_dwfsm_ns_fsm_framing_iv_i_i_a3_3_693), + .I3(plm_dfm_deframe1_dwfsm_ns_fsm_framing_iv_i_i_0_692), + .LO(plm_dfm_deframe1_dwfsm_N_18633_i) + ); + defparam plm_dfm_deframe1_dwfsm_ns_fsm_errored_iv_0.INIT = 16'hCCC4; + LUT4_L plm_dfm_deframe1_dwfsm_ns_fsm_errored_iv_0 ( + .I0(plm_dfm_deframe1_dwfsm_N_18673_1), + .I1(plm_dfm_deframe1_dwfsm_ns_fsm_errored_iv_0_1_696), + .I2(plm_dfm_deframe1_dwfsm_reg_fsm_framing_698), + .I3(plm_dfm_deframe1_reg_any_sta[0]), + .LO(plm_dfm_deframe1_dwfsm_N_8660_i) + ); + defparam plm_dfm_deframe1_dwfsm_valid_on_third_symbol_reg_ferr_40_i_i.INIT = 16'h8CCC; + LUT4_L plm_dfm_deframe1_dwfsm_valid_on_third_symbol_reg_ferr_40_i_i ( + .I0(plm_dfm_deframe1_dwfsm_reg_fsm_errored_699), + .I1(plm_dfm_deframe1_dwfsm_reg_ferr_40_i_i_0), + .I2(plm_dfm_deframe1_reg_any_sym[0]), + .I3(plm_dfm_deframe1_reg_any_sym[1]), + .LO(plm_dfm_deframe1_dwfsm_N_18637_i) + ); + defparam plm_dfm_deframe1_dwfsm_corkscrew_select_reg_high60_0_a3.INIT = 8'h80; + LUT3_L plm_dfm_deframe1_dwfsm_corkscrew_select_reg_high60_0_a3 ( + .I0(plm_dfm_deframe1_dwfsm_reg_fsm_framing_698), + .I1(plm_dfm_deframe1_dwfsm_reg_fsm_substate[0]), + .I2(plm_dfm_deframe1_dwfsm_reg_fsm_substate[1]), + .LO(plm_dfm_deframe1_dwfsm_reg_high60) + ); + defparam plm_dfm_deframe1_dwfsm_corkscrew_select_reg_high59_0_a3.INIT = 8'h20; + LUT3_L plm_dfm_deframe1_dwfsm_corkscrew_select_reg_high59_0_a3 ( + .I0(plm_dfm_deframe1_dwfsm_reg_fsm_framing_698), + .I1(plm_dfm_deframe1_dwfsm_reg_fsm_substate[0]), + .I2(plm_dfm_deframe1_dwfsm_reg_fsm_substate[1]), + .LO(plm_dfm_deframe1_dwfsm_reg_high59) + ); + defparam plm_dfm_deframe1_dwfsm_corkscrew_select_reg_high58_0_a3.INIT = 8'h08; + LUT3_L plm_dfm_deframe1_dwfsm_corkscrew_select_reg_high58_0_a3 ( + .I0(plm_dfm_deframe1_dwfsm_reg_fsm_framing_698), + .I1(plm_dfm_deframe1_dwfsm_reg_fsm_substate[0]), + .I2(plm_dfm_deframe1_dwfsm_reg_fsm_substate[1]), + .LO(plm_dfm_deframe1_dwfsm_reg_high58) + ); + defparam plm_dfm_deframe1_dwfsm_reg_high_12_iv_0_0_.INIT = 16'h5702; + LUT4_L plm_dfm_deframe1_dwfsm_reg_high_12_iv_0_0_ ( + .I0(plm_dfm_deframe1_dwfsm_reg_fsm_framing_698), + .I1(plm_dfm_deframe1_dwfsm_reg_fsm_substate[0]), + .I2(plm_dfm_deframe1_dwfsm_reg_fsm_substate[1]), + .I3(plm_dfm_deframe1_reg_any_sta[1]), + .LO(plm_dfm_deframe1_dwfsm_N_8781_i) + ); + defparam plm_dfm_deframe1_dwfsm_ns_fsm_substate_i_i_1_.INIT = 16'h1504; + LUT4_L plm_dfm_deframe1_dwfsm_ns_fsm_substate_i_i_1_ ( + .I0(plm_dfm_deframe1_dwfsm_ns_fsm_substate_i_i_a3[1]), + .I1(plm_dfm_deframe1_dwfsm_reg_fsm_framing_698), + .I2(plm_dfm_deframe1_dwfsm_reg_fsm_substate[1]), + .I3(plm_dfm_deframe1_reg_any_sta[1]), + .LO(plm_dfm_deframe1_dwfsm_N_18639_i) + ); + defparam plm_dfm_deframe1_dwfsm_ns_fsm_substate_i_i_0_.INIT = 8'hC8; + LUT3_L plm_dfm_deframe1_dwfsm_ns_fsm_substate_i_i_0_ ( + .I0(plm_dfm_deframe1_dwfsm_ns_fsm_framing_iv_i_i_o4_697), + .I1(plm_dfm_deframe1_dwfsm_ns_fsm_substate_i_i_1[0]), + .I2(plm_dfm_deframe1_reg_any_sta[0]), + .LO(plm_dfm_deframe1_dwfsm_N_18641_i) + ); + FDC plm_dfm_deframe1_dwfsm_reg_fsm_framing ( + .C(mgt_clk), + .D(plm_dfm_deframe1_dwfsm_N_18633_i), + .Q(plm_dfm_deframe1_dwfsm_reg_fsm_framing_698), + .CLR(plm_rst) + ); + FDC plm_dfm_deframe1_dwfsm_reg_fsm_errored ( + .C(mgt_clk), + .D(plm_dfm_deframe1_dwfsm_N_8660_i), + .Q(plm_dfm_deframe1_dwfsm_reg_fsm_errored_699), + .CLR(plm_rst) + ); + FDC plm_dfm_deframe1_dwfsm_reg_ferr ( + .C(mgt_clk), + .D(plm_dfm_deframe1_dwfsm_N_18637_i), + .Q(plm_dfm_deframe1_ferr), + .CLR(plm_rst) + ); + FDC plm_dfm_deframe1_dwfsm_reg_high_3_ ( + .C(mgt_clk), + .D(plm_dfm_deframe1_dwfsm_reg_high60), + .Q(plm_dfm_deframe1_high3), + .CLR(plm_rst) + ); + FDC plm_dfm_deframe1_dwfsm_reg_high_2_ ( + .C(mgt_clk), + .D(plm_dfm_deframe1_dwfsm_reg_high59), + .Q(plm_dfm_deframe1_high2), + .CLR(plm_rst) + ); + FDC plm_dfm_deframe1_dwfsm_reg_high_1_ ( + .C(mgt_clk), + .D(plm_dfm_deframe1_dwfsm_reg_high58), + .Q(plm_dfm_deframe1_high1), + .CLR(plm_rst) + ); + FDC plm_dfm_deframe1_dwfsm_reg_high_0_ ( + .C(mgt_clk), + .D(plm_dfm_deframe1_dwfsm_N_8781_i), + .Q(plm_dfm_deframe1_high0), + .CLR(plm_rst) + ); + FDC plm_dfm_deframe1_dwfsm_reg_fsm_substate_1_ ( + .C(mgt_clk), + .D(plm_dfm_deframe1_dwfsm_N_18639_i), + .Q(plm_dfm_deframe1_dwfsm_reg_fsm_substate[1]), + .CLR(plm_rst) + ); + FDC plm_dfm_deframe1_dwfsm_reg_fsm_substate_0_ ( + .C(mgt_clk), + .D(plm_dfm_deframe1_dwfsm_N_18641_i), + .Q(plm_dfm_deframe1_dwfsm_reg_fsm_substate[0]), + .CLR(plm_rst) + ); + FDC plm_dfm_deframe1_dwfsm_reg_fsm_last_substate_1_ ( + .C(mgt_clk), + .D(plm_dfm_deframe1_dwfsm_reg_fsm_substate[1]), + .Q(plm_dfm_deframe1_dwfsm_reg_fsm_last_substate[1]), + .CLR(plm_rst) + ); + FDC plm_dfm_deframe1_dwfsm_reg_fsm_last_substate_0_ ( + .C(mgt_clk), + .D(plm_dfm_deframe1_dwfsm_reg_fsm_substate[0]), + .Q(plm_dfm_deframe1_dwfsm_reg_fsm_last_substate[0]), + .CLR(plm_rst) + ); + INV plm_dfm_deframe1_dwfsm_N_69404_i ( + .I(plm_dfm_deframe1_reg_push_0_i[2]), + .O(plm_dfm_deframe1_N_69404_i) + ); + GND plm_dfm_deframe1_dwbuf_GND ( + .G(plm_dfm_deframe1_dwbuf_GND_700) + ); + RAM16X1D plm_dfm_deframe1_dwbuf_L0S0 ( + .DPO(plm_dfm_deframe1_dwbuf_dpo_sdpstp[0]), + .WCLK(mgt_clk), + .D(plm_dfm_deframe1_dwbuf_N_51073), + .A0(plm_dfm_deframe1_dwbuf_reg_wp0[0]), + .A1(plm_dfm_deframe1_dwbuf_reg_wp0[1]), + .A2(plm_dfm_deframe1_dwbuf_reg_wp0[2]), + .A3(plm_dfm_deframe1_dwbuf_reg_wp0[3]), + .DPRA0(plm_dfm_deframe1_dwbuf_reg_rp[0]), + .DPRA1(plm_dfm_deframe1_dwbuf_reg_rp[1]), + .DPRA2(plm_dfm_deframe1_dwbuf_reg_rp[2]), + .DPRA3(plm_dfm_deframe1_dwbuf_reg_rp[3]), + .SPO(NLW_plm_dfm_deframe1_dwbuf_L0S0_SPO_UNCONNECTED), + .WE(plm_dfm_deframe1_N_18643_i) + ); + RAM16X1D plm_dfm_deframe1_dwbuf_L0S1 ( + .DPO(plm_dfm_deframe1_dwbuf_dpo_sdpstp[1]), + .WCLK(mgt_clk), + .D(plm_dfm_deframe1_dwbuf_N_51074), + .A0(plm_dfm_deframe1_dwbuf_reg_wp0[0]), + .A1(plm_dfm_deframe1_dwbuf_reg_wp0[1]), + .A2(plm_dfm_deframe1_dwbuf_reg_wp0[2]), + .A3(plm_dfm_deframe1_dwbuf_reg_wp0[3]), + .DPRA0(plm_dfm_deframe1_dwbuf_reg_rp[0]), + .DPRA1(plm_dfm_deframe1_dwbuf_reg_rp[1]), + .DPRA2(plm_dfm_deframe1_dwbuf_reg_rp[2]), + .DPRA3(plm_dfm_deframe1_dwbuf_reg_rp[3]), + .SPO(NLW_plm_dfm_deframe1_dwbuf_L0S1_SPO_UNCONNECTED), + .WE(plm_dfm_deframe1_N_18643_i) + ); + RAM16X1D plm_dfm_deframe1_dwbuf_L0B0 ( + .DPO(plm_dfm_deframe1_dwbuf_dpo_out[24]), + .WCLK(mgt_clk), + .D(plm_dfm_deframe1_dwbuf_N_22446), + .A0(plm_dfm_deframe1_dwbuf_reg_wp0[0]), + .A1(plm_dfm_deframe1_dwbuf_reg_wp0[1]), + .A2(plm_dfm_deframe1_dwbuf_reg_wp0[2]), + .A3(plm_dfm_deframe1_dwbuf_reg_wp0[3]), + .DPRA0(plm_dfm_deframe1_dwbuf_reg_rp[0]), + .DPRA1(plm_dfm_deframe1_dwbuf_reg_rp[1]), + .DPRA2(plm_dfm_deframe1_dwbuf_reg_rp[2]), + .DPRA3(plm_dfm_deframe1_dwbuf_reg_rp[3]), + .SPO(NLW_plm_dfm_deframe1_dwbuf_L0B0_SPO_UNCONNECTED), + .WE(plm_dfm_deframe1_N_18643_i) + ); + RAM16X1D plm_dfm_deframe1_dwbuf_L0B1 ( + .DPO(plm_dfm_deframe1_dwbuf_dpo_out[25]), + .WCLK(mgt_clk), + .D(plm_dfm_deframe1_dwbuf_N_22447), + .A0(plm_dfm_deframe1_dwbuf_reg_wp0[0]), + .A1(plm_dfm_deframe1_dwbuf_reg_wp0[1]), + .A2(plm_dfm_deframe1_dwbuf_reg_wp0[2]), + .A3(plm_dfm_deframe1_dwbuf_reg_wp0[3]), + .DPRA0(plm_dfm_deframe1_dwbuf_reg_rp[0]), + .DPRA1(plm_dfm_deframe1_dwbuf_reg_rp[1]), + .DPRA2(plm_dfm_deframe1_dwbuf_reg_rp[2]), + .DPRA3(plm_dfm_deframe1_dwbuf_reg_rp[3]), + .SPO(NLW_plm_dfm_deframe1_dwbuf_L0B1_SPO_UNCONNECTED), + .WE(plm_dfm_deframe1_N_18643_i) + ); + RAM16X1D plm_dfm_deframe1_dwbuf_L0B2 ( + .DPO(plm_dfm_deframe1_dwbuf_dpo_out[26]), + .WCLK(mgt_clk), + .D(plm_dfm_deframe1_dwbuf_N_22448), + .A0(plm_dfm_deframe1_dwbuf_reg_wp0[0]), + .A1(plm_dfm_deframe1_dwbuf_reg_wp0[1]), + .A2(plm_dfm_deframe1_dwbuf_reg_wp0[2]), + .A3(plm_dfm_deframe1_dwbuf_reg_wp0[3]), + .DPRA0(plm_dfm_deframe1_dwbuf_reg_rp[0]), + .DPRA1(plm_dfm_deframe1_dwbuf_reg_rp[1]), + .DPRA2(plm_dfm_deframe1_dwbuf_reg_rp[2]), + .DPRA3(plm_dfm_deframe1_dwbuf_reg_rp[3]), + .SPO(NLW_plm_dfm_deframe1_dwbuf_L0B2_SPO_UNCONNECTED), + .WE(plm_dfm_deframe1_N_18643_i) + ); + RAM16X1D plm_dfm_deframe1_dwbuf_L0B3 ( + .DPO(plm_dfm_deframe1_dwbuf_dpo_out[27]), + .WCLK(mgt_clk), + .D(plm_dfm_deframe1_dwbuf_N_22449), + .A0(plm_dfm_deframe1_dwbuf_reg_wp0[0]), + .A1(plm_dfm_deframe1_dwbuf_reg_wp0[1]), + .A2(plm_dfm_deframe1_dwbuf_reg_wp0[2]), + .A3(plm_dfm_deframe1_dwbuf_reg_wp0[3]), + .DPRA0(plm_dfm_deframe1_dwbuf_reg_rp[0]), + .DPRA1(plm_dfm_deframe1_dwbuf_reg_rp[1]), + .DPRA2(plm_dfm_deframe1_dwbuf_reg_rp[2]), + .DPRA3(plm_dfm_deframe1_dwbuf_reg_rp[3]), + .SPO(NLW_plm_dfm_deframe1_dwbuf_L0B3_SPO_UNCONNECTED), + .WE(plm_dfm_deframe1_N_18643_i) + ); + RAM16X1D plm_dfm_deframe1_dwbuf_L0B4 ( + .DPO(plm_dfm_deframe1_dwbuf_dpo_out[28]), + .WCLK(mgt_clk), + .D(plm_dfm_deframe1_dwbuf_N_22450), + .A0(plm_dfm_deframe1_dwbuf_reg_wp0[0]), + .A1(plm_dfm_deframe1_dwbuf_reg_wp0[1]), + .A2(plm_dfm_deframe1_dwbuf_reg_wp0[2]), + .A3(plm_dfm_deframe1_dwbuf_reg_wp0[3]), + .DPRA0(plm_dfm_deframe1_dwbuf_reg_rp[0]), + .DPRA1(plm_dfm_deframe1_dwbuf_reg_rp[1]), + .DPRA2(plm_dfm_deframe1_dwbuf_reg_rp[2]), + .DPRA3(plm_dfm_deframe1_dwbuf_reg_rp[3]), + .SPO(NLW_plm_dfm_deframe1_dwbuf_L0B4_SPO_UNCONNECTED), + .WE(plm_dfm_deframe1_N_18643_i) + ); + RAM16X1D plm_dfm_deframe1_dwbuf_L0B5 ( + .DPO(plm_dfm_deframe1_dwbuf_dpo_out[29]), + .WCLK(mgt_clk), + .D(plm_dfm_deframe1_dwbuf_N_22451), + .A0(plm_dfm_deframe1_dwbuf_reg_wp0[0]), + .A1(plm_dfm_deframe1_dwbuf_reg_wp0[1]), + .A2(plm_dfm_deframe1_dwbuf_reg_wp0[2]), + .A3(plm_dfm_deframe1_dwbuf_reg_wp0[3]), + .DPRA0(plm_dfm_deframe1_dwbuf_reg_rp[0]), + .DPRA1(plm_dfm_deframe1_dwbuf_reg_rp[1]), + .DPRA2(plm_dfm_deframe1_dwbuf_reg_rp[2]), + .DPRA3(plm_dfm_deframe1_dwbuf_reg_rp[3]), + .SPO(NLW_plm_dfm_deframe1_dwbuf_L0B5_SPO_UNCONNECTED), + .WE(plm_dfm_deframe1_N_18643_i) + ); + RAM16X1D plm_dfm_deframe1_dwbuf_L0B6 ( + .DPO(plm_dfm_deframe1_dwbuf_dpo_out[30]), + .WCLK(mgt_clk), + .D(plm_dfm_deframe1_dwbuf_N_22452), + .A0(plm_dfm_deframe1_dwbuf_reg_wp0[0]), + .A1(plm_dfm_deframe1_dwbuf_reg_wp0[1]), + .A2(plm_dfm_deframe1_dwbuf_reg_wp0[2]), + .A3(plm_dfm_deframe1_dwbuf_reg_wp0[3]), + .DPRA0(plm_dfm_deframe1_dwbuf_reg_rp[0]), + .DPRA1(plm_dfm_deframe1_dwbuf_reg_rp[1]), + .DPRA2(plm_dfm_deframe1_dwbuf_reg_rp[2]), + .DPRA3(plm_dfm_deframe1_dwbuf_reg_rp[3]), + .SPO(NLW_plm_dfm_deframe1_dwbuf_L0B6_SPO_UNCONNECTED), + .WE(plm_dfm_deframe1_N_18643_i) + ); + RAM16X1D plm_dfm_deframe1_dwbuf_L0B7 ( + .DPO(plm_dfm_deframe1_dwbuf_dpo_out[31]), + .WCLK(mgt_clk), + .D(plm_dfm_deframe1_dwbuf_N_22453), + .A0(plm_dfm_deframe1_dwbuf_reg_wp0[0]), + .A1(plm_dfm_deframe1_dwbuf_reg_wp0[1]), + .A2(plm_dfm_deframe1_dwbuf_reg_wp0[2]), + .A3(plm_dfm_deframe1_dwbuf_reg_wp0[3]), + .DPRA0(plm_dfm_deframe1_dwbuf_reg_rp[0]), + .DPRA1(plm_dfm_deframe1_dwbuf_reg_rp[1]), + .DPRA2(plm_dfm_deframe1_dwbuf_reg_rp[2]), + .DPRA3(plm_dfm_deframe1_dwbuf_reg_rp[3]), + .SPO(NLW_plm_dfm_deframe1_dwbuf_L0B7_SPO_UNCONNECTED), + .WE(plm_dfm_deframe1_N_18643_i) + ); + RAM16X1D plm_dfm_deframe1_dwbuf_L1B0 ( + .DPO(plm_dfm_deframe1_dwbuf_dpo_out[16]), + .WCLK(mgt_clk), + .D(plm_dfm_deframe1_dwbuf_N_22454), + .A0(plm_dfm_deframe1_dwbuf_reg_wp1[0]), + .A1(plm_dfm_deframe1_dwbuf_reg_wp1[1]), + .A2(plm_dfm_deframe1_dwbuf_reg_wp1[2]), + .A3(plm_dfm_deframe1_dwbuf_reg_wp1[3]), + .DPRA0(plm_dfm_deframe1_dwbuf_reg_rp[0]), + .DPRA1(plm_dfm_deframe1_dwbuf_reg_rp[1]), + .DPRA2(plm_dfm_deframe1_dwbuf_reg_rp[2]), + .DPRA3(plm_dfm_deframe1_dwbuf_reg_rp[3]), + .SPO(NLW_plm_dfm_deframe1_dwbuf_L1B0_SPO_UNCONNECTED), + .WE(plm_dfm_deframe1_push1) + ); + RAM16X1D plm_dfm_deframe1_dwbuf_L1B1 ( + .DPO(plm_dfm_deframe1_dwbuf_dpo_out[17]), + .WCLK(mgt_clk), + .D(plm_dfm_deframe1_dwbuf_N_22455), + .A0(plm_dfm_deframe1_dwbuf_reg_wp1[0]), + .A1(plm_dfm_deframe1_dwbuf_reg_wp1[1]), + .A2(plm_dfm_deframe1_dwbuf_reg_wp1[2]), + .A3(plm_dfm_deframe1_dwbuf_reg_wp1[3]), + .DPRA0(plm_dfm_deframe1_dwbuf_reg_rp[0]), + .DPRA1(plm_dfm_deframe1_dwbuf_reg_rp[1]), + .DPRA2(plm_dfm_deframe1_dwbuf_reg_rp[2]), + .DPRA3(plm_dfm_deframe1_dwbuf_reg_rp[3]), + .SPO(NLW_plm_dfm_deframe1_dwbuf_L1B1_SPO_UNCONNECTED), + .WE(plm_dfm_deframe1_push1) + ); + RAM16X1D plm_dfm_deframe1_dwbuf_L1B2 ( + .DPO(plm_dfm_deframe1_dwbuf_dpo_out[18]), + .WCLK(mgt_clk), + .D(plm_dfm_deframe1_dwbuf_N_22456), + .A0(plm_dfm_deframe1_dwbuf_reg_wp1[0]), + .A1(plm_dfm_deframe1_dwbuf_reg_wp1[1]), + .A2(plm_dfm_deframe1_dwbuf_reg_wp1[2]), + .A3(plm_dfm_deframe1_dwbuf_reg_wp1[3]), + .DPRA0(plm_dfm_deframe1_dwbuf_reg_rp[0]), + .DPRA1(plm_dfm_deframe1_dwbuf_reg_rp[1]), + .DPRA2(plm_dfm_deframe1_dwbuf_reg_rp[2]), + .DPRA3(plm_dfm_deframe1_dwbuf_reg_rp[3]), + .SPO(NLW_plm_dfm_deframe1_dwbuf_L1B2_SPO_UNCONNECTED), + .WE(plm_dfm_deframe1_push1) + ); + RAM16X1D plm_dfm_deframe1_dwbuf_L1B3 ( + .DPO(plm_dfm_deframe1_dwbuf_dpo_out[19]), + .WCLK(mgt_clk), + .D(plm_dfm_deframe1_dwbuf_N_22457), + .A0(plm_dfm_deframe1_dwbuf_reg_wp1[0]), + .A1(plm_dfm_deframe1_dwbuf_reg_wp1[1]), + .A2(plm_dfm_deframe1_dwbuf_reg_wp1[2]), + .A3(plm_dfm_deframe1_dwbuf_reg_wp1[3]), + .DPRA0(plm_dfm_deframe1_dwbuf_reg_rp[0]), + .DPRA1(plm_dfm_deframe1_dwbuf_reg_rp[1]), + .DPRA2(plm_dfm_deframe1_dwbuf_reg_rp[2]), + .DPRA3(plm_dfm_deframe1_dwbuf_reg_rp[3]), + .SPO(NLW_plm_dfm_deframe1_dwbuf_L1B3_SPO_UNCONNECTED), + .WE(plm_dfm_deframe1_push1) + ); + RAM16X1D plm_dfm_deframe1_dwbuf_L1B4 ( + .DPO(plm_dfm_deframe1_dwbuf_dpo_out[20]), + .WCLK(mgt_clk), + .D(plm_dfm_deframe1_dwbuf_N_22458), + .A0(plm_dfm_deframe1_dwbuf_reg_wp1[0]), + .A1(plm_dfm_deframe1_dwbuf_reg_wp1[1]), + .A2(plm_dfm_deframe1_dwbuf_reg_wp1[2]), + .A3(plm_dfm_deframe1_dwbuf_reg_wp1[3]), + .DPRA0(plm_dfm_deframe1_dwbuf_reg_rp[0]), + .DPRA1(plm_dfm_deframe1_dwbuf_reg_rp[1]), + .DPRA2(plm_dfm_deframe1_dwbuf_reg_rp[2]), + .DPRA3(plm_dfm_deframe1_dwbuf_reg_rp[3]), + .SPO(NLW_plm_dfm_deframe1_dwbuf_L1B4_SPO_UNCONNECTED), + .WE(plm_dfm_deframe1_push1) + ); + RAM16X1D plm_dfm_deframe1_dwbuf_L1B5 ( + .DPO(plm_dfm_deframe1_dwbuf_dpo_out[21]), + .WCLK(mgt_clk), + .D(plm_dfm_deframe1_dwbuf_N_22459), + .A0(plm_dfm_deframe1_dwbuf_reg_wp1[0]), + .A1(plm_dfm_deframe1_dwbuf_reg_wp1[1]), + .A2(plm_dfm_deframe1_dwbuf_reg_wp1[2]), + .A3(plm_dfm_deframe1_dwbuf_reg_wp1[3]), + .DPRA0(plm_dfm_deframe1_dwbuf_reg_rp[0]), + .DPRA1(plm_dfm_deframe1_dwbuf_reg_rp[1]), + .DPRA2(plm_dfm_deframe1_dwbuf_reg_rp[2]), + .DPRA3(plm_dfm_deframe1_dwbuf_reg_rp[3]), + .SPO(NLW_plm_dfm_deframe1_dwbuf_L1B5_SPO_UNCONNECTED), + .WE(plm_dfm_deframe1_push1) + ); + RAM16X1D plm_dfm_deframe1_dwbuf_L1B6 ( + .DPO(plm_dfm_deframe1_dwbuf_dpo_out[22]), + .WCLK(mgt_clk), + .D(plm_dfm_deframe1_dwbuf_N_22460), + .A0(plm_dfm_deframe1_dwbuf_reg_wp1[0]), + .A1(plm_dfm_deframe1_dwbuf_reg_wp1[1]), + .A2(plm_dfm_deframe1_dwbuf_reg_wp1[2]), + .A3(plm_dfm_deframe1_dwbuf_reg_wp1[3]), + .DPRA0(plm_dfm_deframe1_dwbuf_reg_rp[0]), + .DPRA1(plm_dfm_deframe1_dwbuf_reg_rp[1]), + .DPRA2(plm_dfm_deframe1_dwbuf_reg_rp[2]), + .DPRA3(plm_dfm_deframe1_dwbuf_reg_rp[3]), + .SPO(NLW_plm_dfm_deframe1_dwbuf_L1B6_SPO_UNCONNECTED), + .WE(plm_dfm_deframe1_push1) + ); + RAM16X1D plm_dfm_deframe1_dwbuf_L1B7 ( + .DPO(plm_dfm_deframe1_dwbuf_dpo_out[23]), + .WCLK(mgt_clk), + .D(plm_dfm_deframe1_dwbuf_N_22461), + .A0(plm_dfm_deframe1_dwbuf_reg_wp1[0]), + .A1(plm_dfm_deframe1_dwbuf_reg_wp1[1]), + .A2(plm_dfm_deframe1_dwbuf_reg_wp1[2]), + .A3(plm_dfm_deframe1_dwbuf_reg_wp1[3]), + .DPRA0(plm_dfm_deframe1_dwbuf_reg_rp[0]), + .DPRA1(plm_dfm_deframe1_dwbuf_reg_rp[1]), + .DPRA2(plm_dfm_deframe1_dwbuf_reg_rp[2]), + .DPRA3(plm_dfm_deframe1_dwbuf_reg_rp[3]), + .SPO(NLW_plm_dfm_deframe1_dwbuf_L1B7_SPO_UNCONNECTED), + .WE(plm_dfm_deframe1_push1) + ); + RAM16X1D plm_dfm_deframe1_dwbuf_L2B0 ( + .DPO(plm_dfm_deframe1_dwbuf_dpo_out[8]), + .WCLK(mgt_clk), + .D(plm_dfm_deframe1_dwbuf_N_22462), + .A0(plm_dfm_deframe1_dwbuf_reg_wp2[0]), + .A1(plm_dfm_deframe1_dwbuf_reg_wp2[1]), + .A2(plm_dfm_deframe1_dwbuf_reg_wp2[2]), + .A3(plm_dfm_deframe1_dwbuf_reg_wp2[3]), + .DPRA0(plm_dfm_deframe1_dwbuf_reg_rp[0]), + .DPRA1(plm_dfm_deframe1_dwbuf_reg_rp[1]), + .DPRA2(plm_dfm_deframe1_dwbuf_reg_rp[2]), + .DPRA3(plm_dfm_deframe1_dwbuf_reg_rp[3]), + .SPO(NLW_plm_dfm_deframe1_dwbuf_L2B0_SPO_UNCONNECTED), + .WE(plm_dfm_deframe1_N_69404_i) + ); + RAM16X1D plm_dfm_deframe1_dwbuf_L2B1 ( + .DPO(plm_dfm_deframe1_dwbuf_dpo_out[9]), + .WCLK(mgt_clk), + .D(plm_dfm_deframe1_dwbuf_N_22463), + .A0(plm_dfm_deframe1_dwbuf_reg_wp2[0]), + .A1(plm_dfm_deframe1_dwbuf_reg_wp2[1]), + .A2(plm_dfm_deframe1_dwbuf_reg_wp2[2]), + .A3(plm_dfm_deframe1_dwbuf_reg_wp2[3]), + .DPRA0(plm_dfm_deframe1_dwbuf_reg_rp[0]), + .DPRA1(plm_dfm_deframe1_dwbuf_reg_rp[1]), + .DPRA2(plm_dfm_deframe1_dwbuf_reg_rp[2]), + .DPRA3(plm_dfm_deframe1_dwbuf_reg_rp[3]), + .SPO(NLW_plm_dfm_deframe1_dwbuf_L2B1_SPO_UNCONNECTED), + .WE(plm_dfm_deframe1_N_69404_i) + ); + RAM16X1D plm_dfm_deframe1_dwbuf_L2B2 ( + .DPO(plm_dfm_deframe1_dwbuf_dpo_out[10]), + .WCLK(mgt_clk), + .D(plm_dfm_deframe1_dwbuf_N_22464), + .A0(plm_dfm_deframe1_dwbuf_reg_wp2[0]), + .A1(plm_dfm_deframe1_dwbuf_reg_wp2[1]), + .A2(plm_dfm_deframe1_dwbuf_reg_wp2[2]), + .A3(plm_dfm_deframe1_dwbuf_reg_wp2[3]), + .DPRA0(plm_dfm_deframe1_dwbuf_reg_rp[0]), + .DPRA1(plm_dfm_deframe1_dwbuf_reg_rp[1]), + .DPRA2(plm_dfm_deframe1_dwbuf_reg_rp[2]), + .DPRA3(plm_dfm_deframe1_dwbuf_reg_rp[3]), + .SPO(NLW_plm_dfm_deframe1_dwbuf_L2B2_SPO_UNCONNECTED), + .WE(plm_dfm_deframe1_N_69404_i) + ); + RAM16X1D plm_dfm_deframe1_dwbuf_L2B3 ( + .DPO(plm_dfm_deframe1_dwbuf_dpo_out[11]), + .WCLK(mgt_clk), + .D(plm_dfm_deframe1_dwbuf_N_22465), + .A0(plm_dfm_deframe1_dwbuf_reg_wp2[0]), + .A1(plm_dfm_deframe1_dwbuf_reg_wp2[1]), + .A2(plm_dfm_deframe1_dwbuf_reg_wp2[2]), + .A3(plm_dfm_deframe1_dwbuf_reg_wp2[3]), + .DPRA0(plm_dfm_deframe1_dwbuf_reg_rp[0]), + .DPRA1(plm_dfm_deframe1_dwbuf_reg_rp[1]), + .DPRA2(plm_dfm_deframe1_dwbuf_reg_rp[2]), + .DPRA3(plm_dfm_deframe1_dwbuf_reg_rp[3]), + .SPO(NLW_plm_dfm_deframe1_dwbuf_L2B3_SPO_UNCONNECTED), + .WE(plm_dfm_deframe1_N_69404_i) + ); + RAM16X1D plm_dfm_deframe1_dwbuf_L2B4 ( + .DPO(plm_dfm_deframe1_dwbuf_dpo_out[12]), + .WCLK(mgt_clk), + .D(plm_dfm_deframe1_dwbuf_N_22466), + .A0(plm_dfm_deframe1_dwbuf_reg_wp2[0]), + .A1(plm_dfm_deframe1_dwbuf_reg_wp2[1]), + .A2(plm_dfm_deframe1_dwbuf_reg_wp2[2]), + .A3(plm_dfm_deframe1_dwbuf_reg_wp2[3]), + .DPRA0(plm_dfm_deframe1_dwbuf_reg_rp[0]), + .DPRA1(plm_dfm_deframe1_dwbuf_reg_rp[1]), + .DPRA2(plm_dfm_deframe1_dwbuf_reg_rp[2]), + .DPRA3(plm_dfm_deframe1_dwbuf_reg_rp[3]), + .SPO(NLW_plm_dfm_deframe1_dwbuf_L2B4_SPO_UNCONNECTED), + .WE(plm_dfm_deframe1_N_69404_i) + ); + RAM16X1D plm_dfm_deframe1_dwbuf_L2B5 ( + .DPO(plm_dfm_deframe1_dwbuf_dpo_out[13]), + .WCLK(mgt_clk), + .D(plm_dfm_deframe1_dwbuf_N_22467), + .A0(plm_dfm_deframe1_dwbuf_reg_wp2[0]), + .A1(plm_dfm_deframe1_dwbuf_reg_wp2[1]), + .A2(plm_dfm_deframe1_dwbuf_reg_wp2[2]), + .A3(plm_dfm_deframe1_dwbuf_reg_wp2[3]), + .DPRA0(plm_dfm_deframe1_dwbuf_reg_rp[0]), + .DPRA1(plm_dfm_deframe1_dwbuf_reg_rp[1]), + .DPRA2(plm_dfm_deframe1_dwbuf_reg_rp[2]), + .DPRA3(plm_dfm_deframe1_dwbuf_reg_rp[3]), + .SPO(NLW_plm_dfm_deframe1_dwbuf_L2B5_SPO_UNCONNECTED), + .WE(plm_dfm_deframe1_N_69404_i) + ); + RAM16X1D plm_dfm_deframe1_dwbuf_L2B6 ( + .DPO(plm_dfm_deframe1_dwbuf_dpo_out[14]), + .WCLK(mgt_clk), + .D(plm_dfm_deframe1_dwbuf_N_22468), + .A0(plm_dfm_deframe1_dwbuf_reg_wp2[0]), + .A1(plm_dfm_deframe1_dwbuf_reg_wp2[1]), + .A2(plm_dfm_deframe1_dwbuf_reg_wp2[2]), + .A3(plm_dfm_deframe1_dwbuf_reg_wp2[3]), + .DPRA0(plm_dfm_deframe1_dwbuf_reg_rp[0]), + .DPRA1(plm_dfm_deframe1_dwbuf_reg_rp[1]), + .DPRA2(plm_dfm_deframe1_dwbuf_reg_rp[2]), + .DPRA3(plm_dfm_deframe1_dwbuf_reg_rp[3]), + .SPO(NLW_plm_dfm_deframe1_dwbuf_L2B6_SPO_UNCONNECTED), + .WE(plm_dfm_deframe1_N_69404_i) + ); + RAM16X1D plm_dfm_deframe1_dwbuf_L2B7 ( + .DPO(plm_dfm_deframe1_dwbuf_dpo_out[15]), + .WCLK(mgt_clk), + .D(plm_dfm_deframe1_dwbuf_N_22469), + .A0(plm_dfm_deframe1_dwbuf_reg_wp2[0]), + .A1(plm_dfm_deframe1_dwbuf_reg_wp2[1]), + .A2(plm_dfm_deframe1_dwbuf_reg_wp2[2]), + .A3(plm_dfm_deframe1_dwbuf_reg_wp2[3]), + .DPRA0(plm_dfm_deframe1_dwbuf_reg_rp[0]), + .DPRA1(plm_dfm_deframe1_dwbuf_reg_rp[1]), + .DPRA2(plm_dfm_deframe1_dwbuf_reg_rp[2]), + .DPRA3(plm_dfm_deframe1_dwbuf_reg_rp[3]), + .SPO(NLW_plm_dfm_deframe1_dwbuf_L2B7_SPO_UNCONNECTED), + .WE(plm_dfm_deframe1_N_69404_i) + ); + RAM16X1D plm_dfm_deframe1_dwbuf_L3B0 ( + .DPO(plm_dfm_deframe1_dwbuf_dpo_out[0]), + .WCLK(mgt_clk), + .D(plm_dfm_deframe1_dwbuf_N_22470), + .A0(plm_dfm_deframe1_dwbuf_reg_wp3[0]), + .A1(plm_dfm_deframe1_dwbuf_reg_wp3[1]), + .A2(plm_dfm_deframe1_dwbuf_reg_wp3[2]), + .A3(plm_dfm_deframe1_dwbuf_reg_wp3[3]), + .DPRA0(plm_dfm_deframe1_dwbuf_reg_rp[0]), + .DPRA1(plm_dfm_deframe1_dwbuf_reg_rp[1]), + .DPRA2(plm_dfm_deframe1_dwbuf_reg_rp[2]), + .DPRA3(plm_dfm_deframe1_dwbuf_reg_rp[3]), + .SPO(NLW_plm_dfm_deframe1_dwbuf_L3B0_SPO_UNCONNECTED), + .WE(plm_dfm_deframe1_N_18645_i) + ); + RAM16X1D plm_dfm_deframe1_dwbuf_L3B1 ( + .DPO(plm_dfm_deframe1_dwbuf_dpo_out[1]), + .WCLK(mgt_clk), + .D(plm_dfm_deframe1_dwbuf_N_22471), + .A0(plm_dfm_deframe1_dwbuf_reg_wp3[0]), + .A1(plm_dfm_deframe1_dwbuf_reg_wp3[1]), + .A2(plm_dfm_deframe1_dwbuf_reg_wp3[2]), + .A3(plm_dfm_deframe1_dwbuf_reg_wp3[3]), + .DPRA0(plm_dfm_deframe1_dwbuf_reg_rp[0]), + .DPRA1(plm_dfm_deframe1_dwbuf_reg_rp[1]), + .DPRA2(plm_dfm_deframe1_dwbuf_reg_rp[2]), + .DPRA3(plm_dfm_deframe1_dwbuf_reg_rp[3]), + .SPO(NLW_plm_dfm_deframe1_dwbuf_L3B1_SPO_UNCONNECTED), + .WE(plm_dfm_deframe1_N_18645_i) + ); + RAM16X1D plm_dfm_deframe1_dwbuf_L3B2 ( + .DPO(plm_dfm_deframe1_dwbuf_dpo_out[2]), + .WCLK(mgt_clk), + .D(plm_dfm_deframe1_dwbuf_N_22472), + .A0(plm_dfm_deframe1_dwbuf_reg_wp3[0]), + .A1(plm_dfm_deframe1_dwbuf_reg_wp3[1]), + .A2(plm_dfm_deframe1_dwbuf_reg_wp3[2]), + .A3(plm_dfm_deframe1_dwbuf_reg_wp3[3]), + .DPRA0(plm_dfm_deframe1_dwbuf_reg_rp[0]), + .DPRA1(plm_dfm_deframe1_dwbuf_reg_rp[1]), + .DPRA2(plm_dfm_deframe1_dwbuf_reg_rp[2]), + .DPRA3(plm_dfm_deframe1_dwbuf_reg_rp[3]), + .SPO(NLW_plm_dfm_deframe1_dwbuf_L3B2_SPO_UNCONNECTED), + .WE(plm_dfm_deframe1_N_18645_i) + ); + RAM16X1D plm_dfm_deframe1_dwbuf_L3B3 ( + .DPO(plm_dfm_deframe1_dwbuf_dpo_out[3]), + .WCLK(mgt_clk), + .D(plm_dfm_deframe1_dwbuf_N_22473), + .A0(plm_dfm_deframe1_dwbuf_reg_wp3[0]), + .A1(plm_dfm_deframe1_dwbuf_reg_wp3[1]), + .A2(plm_dfm_deframe1_dwbuf_reg_wp3[2]), + .A3(plm_dfm_deframe1_dwbuf_reg_wp3[3]), + .DPRA0(plm_dfm_deframe1_dwbuf_reg_rp[0]), + .DPRA1(plm_dfm_deframe1_dwbuf_reg_rp[1]), + .DPRA2(plm_dfm_deframe1_dwbuf_reg_rp[2]), + .DPRA3(plm_dfm_deframe1_dwbuf_reg_rp[3]), + .SPO(NLW_plm_dfm_deframe1_dwbuf_L3B3_SPO_UNCONNECTED), + .WE(plm_dfm_deframe1_N_18645_i) + ); + RAM16X1D plm_dfm_deframe1_dwbuf_L3B4 ( + .DPO(plm_dfm_deframe1_dwbuf_dpo_out[4]), + .WCLK(mgt_clk), + .D(plm_dfm_deframe1_dwbuf_N_22474), + .A0(plm_dfm_deframe1_dwbuf_reg_wp3[0]), + .A1(plm_dfm_deframe1_dwbuf_reg_wp3[1]), + .A2(plm_dfm_deframe1_dwbuf_reg_wp3[2]), + .A3(plm_dfm_deframe1_dwbuf_reg_wp3[3]), + .DPRA0(plm_dfm_deframe1_dwbuf_reg_rp[0]), + .DPRA1(plm_dfm_deframe1_dwbuf_reg_rp[1]), + .DPRA2(plm_dfm_deframe1_dwbuf_reg_rp[2]), + .DPRA3(plm_dfm_deframe1_dwbuf_reg_rp[3]), + .SPO(NLW_plm_dfm_deframe1_dwbuf_L3B4_SPO_UNCONNECTED), + .WE(plm_dfm_deframe1_N_18645_i) + ); + RAM16X1D plm_dfm_deframe1_dwbuf_L3B5 ( + .DPO(plm_dfm_deframe1_dwbuf_dpo_out[5]), + .WCLK(mgt_clk), + .D(plm_dfm_deframe1_dwbuf_N_22475), + .A0(plm_dfm_deframe1_dwbuf_reg_wp3[0]), + .A1(plm_dfm_deframe1_dwbuf_reg_wp3[1]), + .A2(plm_dfm_deframe1_dwbuf_reg_wp3[2]), + .A3(plm_dfm_deframe1_dwbuf_reg_wp3[3]), + .DPRA0(plm_dfm_deframe1_dwbuf_reg_rp[0]), + .DPRA1(plm_dfm_deframe1_dwbuf_reg_rp[1]), + .DPRA2(plm_dfm_deframe1_dwbuf_reg_rp[2]), + .DPRA3(plm_dfm_deframe1_dwbuf_reg_rp[3]), + .SPO(NLW_plm_dfm_deframe1_dwbuf_L3B5_SPO_UNCONNECTED), + .WE(plm_dfm_deframe1_N_18645_i) + ); + RAM16X1D plm_dfm_deframe1_dwbuf_L3B6 ( + .DPO(plm_dfm_deframe1_dwbuf_dpo_out[6]), + .WCLK(mgt_clk), + .D(plm_dfm_deframe1_dwbuf_N_22476), + .A0(plm_dfm_deframe1_dwbuf_reg_wp3[0]), + .A1(plm_dfm_deframe1_dwbuf_reg_wp3[1]), + .A2(plm_dfm_deframe1_dwbuf_reg_wp3[2]), + .A3(plm_dfm_deframe1_dwbuf_reg_wp3[3]), + .DPRA0(plm_dfm_deframe1_dwbuf_reg_rp[0]), + .DPRA1(plm_dfm_deframe1_dwbuf_reg_rp[1]), + .DPRA2(plm_dfm_deframe1_dwbuf_reg_rp[2]), + .DPRA3(plm_dfm_deframe1_dwbuf_reg_rp[3]), + .SPO(NLW_plm_dfm_deframe1_dwbuf_L3B6_SPO_UNCONNECTED), + .WE(plm_dfm_deframe1_N_18645_i) + ); + RAM16X1D plm_dfm_deframe1_dwbuf_L3B7 ( + .DPO(plm_dfm_deframe1_dwbuf_dpo_out[7]), + .WCLK(mgt_clk), + .D(plm_dfm_deframe1_dwbuf_N_22477), + .A0(plm_dfm_deframe1_dwbuf_reg_wp3[0]), + .A1(plm_dfm_deframe1_dwbuf_reg_wp3[1]), + .A2(plm_dfm_deframe1_dwbuf_reg_wp3[2]), + .A3(plm_dfm_deframe1_dwbuf_reg_wp3[3]), + .DPRA0(plm_dfm_deframe1_dwbuf_reg_rp[0]), + .DPRA1(plm_dfm_deframe1_dwbuf_reg_rp[1]), + .DPRA2(plm_dfm_deframe1_dwbuf_reg_rp[2]), + .DPRA3(plm_dfm_deframe1_dwbuf_reg_rp[3]), + .SPO(NLW_plm_dfm_deframe1_dwbuf_L3B7_SPO_UNCONNECTED), + .WE(plm_dfm_deframe1_N_18645_i) + ); + RAM16X1D plm_dfm_deframe1_dwbuf_L3S0 ( + .DPO(plm_dfm_deframe1_dwbuf_dpo_edbedg[0]), + .WCLK(mgt_clk), + .D(plm_dfm_deframe1_dwbuf_N_69361_i_707), + .A0(plm_dfm_deframe1_dwbuf_reg_wp3[0]), + .A1(plm_dfm_deframe1_dwbuf_reg_wp3[1]), + .A2(plm_dfm_deframe1_dwbuf_reg_wp3[2]), + .A3(plm_dfm_deframe1_dwbuf_reg_wp3[3]), + .DPRA0(plm_dfm_deframe1_dwbuf_reg_rp[0]), + .DPRA1(plm_dfm_deframe1_dwbuf_reg_rp[1]), + .DPRA2(plm_dfm_deframe1_dwbuf_reg_rp[2]), + .DPRA3(plm_dfm_deframe1_dwbuf_reg_rp[3]), + .SPO(NLW_plm_dfm_deframe1_dwbuf_L3S0_SPO_UNCONNECTED), + .WE(plm_dfm_deframe1_N_18645_i) + ); + RAM16X1D plm_dfm_deframe1_dwbuf_L3S1 ( + .DPO(plm_dfm_deframe1_dwbuf_dpo_edbedg[1]), + .WCLK(mgt_clk), + .D(plm_dfm_deframe1_dwbuf_N_69360_i_708), + .A0(plm_dfm_deframe1_dwbuf_reg_wp3[0]), + .A1(plm_dfm_deframe1_dwbuf_reg_wp3[1]), + .A2(plm_dfm_deframe1_dwbuf_reg_wp3[2]), + .A3(plm_dfm_deframe1_dwbuf_reg_wp3[3]), + .DPRA0(plm_dfm_deframe1_dwbuf_reg_rp[0]), + .DPRA1(plm_dfm_deframe1_dwbuf_reg_rp[1]), + .DPRA2(plm_dfm_deframe1_dwbuf_reg_rp[2]), + .DPRA3(plm_dfm_deframe1_dwbuf_reg_rp[3]), + .SPO(NLW_plm_dfm_deframe1_dwbuf_L3S1_SPO_UNCONNECTED), + .WE(plm_dfm_deframe1_N_18645_i) + ); + defparam plm_dfm_deframe1_dwbuf_pointers_reg_wp0_4_p4.INIT = 16'h8000; + LUT4_L plm_dfm_deframe1_dwbuf_pointers_reg_wp0_4_p4 ( + .I0(plm_dfm_deframe1_N_18643_i), + .I1(plm_dfm_deframe1_dwbuf_reg_wp0[0]), + .I2(plm_dfm_deframe1_dwbuf_reg_wp0[1]), + .I3(plm_dfm_deframe1_dwbuf_reg_wp0[2]), + .LO(plm_dfm_deframe1_dwbuf_reg_wp0_4_p4) + ); + defparam plm_dfm_deframe1_dwbuf_pointers_reg_wp1_4_p4.INIT = 16'h8000; + LUT4_L plm_dfm_deframe1_dwbuf_pointers_reg_wp1_4_p4 ( + .I0(plm_dfm_deframe1_dwbuf_reg_wp1[0]), + .I1(plm_dfm_deframe1_dwbuf_reg_wp1[1]), + .I2(plm_dfm_deframe1_dwbuf_reg_wp1[2]), + .I3(plm_dfm_deframe1_push1), + .LO(plm_dfm_deframe1_dwbuf_reg_wp1_4_p4) + ); + defparam plm_dfm_deframe1_dwbuf_pointers_reg_wp2_4_p4.INIT = 16'h4000; + LUT4_L plm_dfm_deframe1_dwbuf_pointers_reg_wp2_4_p4 ( + .I0(plm_dfm_deframe1_reg_push_0_i[2]), + .I1(plm_dfm_deframe1_dwbuf_reg_wp2[0]), + .I2(plm_dfm_deframe1_dwbuf_reg_wp2[1]), + .I3(plm_dfm_deframe1_dwbuf_reg_wp2[2]), + .LO(plm_dfm_deframe1_dwbuf_reg_wp2_4_p4) + ); + defparam plm_dfm_deframe1_dwbuf_pointers_reg_wp3_4_p4.INIT = 16'h8000; + LUT4_L plm_dfm_deframe1_dwbuf_pointers_reg_wp3_4_p4 ( + .I0(plm_dfm_deframe1_N_18645_i), + .I1(plm_dfm_deframe1_dwbuf_reg_wp3[0]), + .I2(plm_dfm_deframe1_dwbuf_reg_wp3[1]), + .I3(plm_dfm_deframe1_dwbuf_reg_wp3[2]), + .LO(plm_dfm_deframe1_dwbuf_reg_wp3_4_p4) + ); + defparam plm_dfm_deframe1_dwbuf_pointers_reg_rp_4_p4.INIT = 16'h8000; + LUT4_L plm_dfm_deframe1_dwbuf_pointers_reg_rp_4_p4 ( + .I0(plm_dfm_deframe1_dwbuf_reg_rp[0]), + .I1(plm_dfm_deframe1_dwbuf_reg_rp[1]), + .I2(plm_dfm_deframe1_dwbuf_reg_rp[2]), + .I3(plm_dfm_deframe1_dword_pop), + .LO(plm_dfm_deframe1_dwbuf_reg_rp_4_p4) + ); + MULT_AND plm_dfm_deframe1_dwbuf_un1_reg_cnt_1_cry_0 ( + .I0(plm_dfm_deframe1_dwbuf_reg_empty19_i), + .I1(plm_dfm_deframe1_dwbuf_reg_empty22_i), + .LO(plm_dfm_deframe1_dwbuf_un1_reg_cnt_1_cry_0_0_701) + ); + MUXCY_L plm_dfm_deframe1_dwbuf_un1_reg_cnt_1_cry_0_0 ( + .CI(plm_dfm_deframe1_dwbuf_GND_700), + .DI(plm_dfm_deframe1_dwbuf_un1_reg_cnt_1_cry_0_0_701), + .LO(plm_dfm_deframe1_dwbuf_un1_reg_cnt_1_cry_0_703), + .S(plm_dfm_deframe1_dwbuf_un1_reg_cnt_1_axb_0_714) + ); + MULT_AND plm_dfm_deframe1_dwbuf_un1_reg_cnt_1_cry_1 ( + .I0(plm_dfm_deframe1_dword_pop), + .I1(plm_dfm_deframe1_dwbuf_reg_empty22_i), + .LO(plm_dfm_deframe1_dwbuf_un1_reg_cnt_1_cry_1_0_702) + ); + MUXCY_L plm_dfm_deframe1_dwbuf_un1_reg_cnt_1_cry_1_0 ( + .CI(plm_dfm_deframe1_dwbuf_un1_reg_cnt_1_cry_0_703), + .DI(plm_dfm_deframe1_dwbuf_un1_reg_cnt_1_cry_1_0_702), + .LO(plm_dfm_deframe1_dwbuf_un1_reg_cnt_1_cry_1_705), + .S(plm_dfm_deframe1_dwbuf_un1_reg_cnt_1_axb_1_710) + ); + XORCY plm_dfm_deframe1_dwbuf_un1_reg_cnt_1_s_1 ( + .CI(plm_dfm_deframe1_dwbuf_un1_reg_cnt_1_cry_0_703), + .LI(plm_dfm_deframe1_dwbuf_un1_reg_cnt_1_axb_1_710), + .O(plm_dfm_deframe1_dwbuf_un1_reg_cnt_1_s_1_713) + ); + MULT_AND plm_dfm_deframe1_dwbuf_un1_reg_cnt_1_cry_2 ( + .I0(plm_dfm_deframe1_dword_pop), + .I1(plm_dfm_deframe1_dwbuf_reg_empty22_i), + .LO(plm_dfm_deframe1_dwbuf_un1_reg_cnt_1_cry_2_0_704) + ); + MUXCY_L plm_dfm_deframe1_dwbuf_un1_reg_cnt_1_cry_2_0 ( + .CI(plm_dfm_deframe1_dwbuf_un1_reg_cnt_1_cry_1_705), + .DI(plm_dfm_deframe1_dwbuf_un1_reg_cnt_1_cry_2_0_704), + .LO(plm_dfm_deframe1_dwbuf_un1_reg_cnt_1_cry_2_706), + .S(plm_dfm_deframe1_dwbuf_un1_reg_cnt_1_axb_2_709) + ); + XORCY plm_dfm_deframe1_dwbuf_un1_reg_cnt_1_s_2 ( + .CI(plm_dfm_deframe1_dwbuf_un1_reg_cnt_1_cry_1_705), + .LI(plm_dfm_deframe1_dwbuf_un1_reg_cnt_1_axb_2_709), + .O(plm_dfm_deframe1_dwbuf_un1_reg_cnt_1_s_2_712) + ); + XORCY plm_dfm_deframe1_dwbuf_un1_reg_cnt_1_s_3 ( + .CI(plm_dfm_deframe1_dwbuf_un1_reg_cnt_1_cry_2_706), + .LI(plm_dfm_deframe1_dwbuf_un1_reg_cnt_1_axb_3_717), + .O(plm_dfm_deframe1_dwbuf_un1_reg_cnt_1_s_3_711) + ); + defparam plm_dfm_deframe1_dwbuf_pointers_reg_empty_5_0.INIT = 4'h1; + LUT2_L plm_dfm_deframe1_dwbuf_pointers_reg_empty_5_0 ( + .I0(plm_dfm_deframe1_dwbuf_reg_cnt[2]), + .I1(plm_dfm_deframe1_dwbuf_reg_cnt[3]), + .LO(plm_dfm_deframe1_dwbuf_reg_empty_5_0) + ); + defparam plm_dfm_deframe1_dwbuf_wd_l0_i_m4_0_0_.INIT = 8'hE4; + LUT3 plm_dfm_deframe1_dwbuf_wd_l0_i_m4_0_0_ ( + .I0(plm_dfm_deframe1_high0), + .I1(plm_dfm_deframe1_reg_delay_dat[0]), + .I2(plm_dfm_deframe1_reg_delay_dat[8]), + .O(plm_dfm_deframe1_dwbuf_N_22446) + ); + defparam plm_dfm_deframe1_dwbuf_wd_l0_i_m4_0_1_.INIT = 8'hE4; + LUT3 plm_dfm_deframe1_dwbuf_wd_l0_i_m4_0_1_ ( + .I0(plm_dfm_deframe1_high0), + .I1(plm_dfm_deframe1_reg_delay_dat[1]), + .I2(plm_dfm_deframe1_reg_delay_dat[9]), + .O(plm_dfm_deframe1_dwbuf_N_22447) + ); + defparam plm_dfm_deframe1_dwbuf_wd_l0_i_m4_0_2_.INIT = 8'hE4; + LUT3 plm_dfm_deframe1_dwbuf_wd_l0_i_m4_0_2_ ( + .I0(plm_dfm_deframe1_high0), + .I1(plm_dfm_deframe1_reg_delay_dat[2]), + .I2(plm_dfm_deframe1_reg_delay_dat[10]), + .O(plm_dfm_deframe1_dwbuf_N_22448) + ); + defparam plm_dfm_deframe1_dwbuf_wd_l0_i_m4_0_3_.INIT = 8'hE4; + LUT3 plm_dfm_deframe1_dwbuf_wd_l0_i_m4_0_3_ ( + .I0(plm_dfm_deframe1_high0), + .I1(plm_dfm_deframe1_reg_delay_dat[3]), + .I2(plm_dfm_deframe1_reg_delay_dat[11]), + .O(plm_dfm_deframe1_dwbuf_N_22449) + ); + defparam plm_dfm_deframe1_dwbuf_wd_l0_i_m4_0_4_.INIT = 8'hE4; + LUT3 plm_dfm_deframe1_dwbuf_wd_l0_i_m4_0_4_ ( + .I0(plm_dfm_deframe1_high0), + .I1(plm_dfm_deframe1_reg_delay_dat[4]), + .I2(plm_dfm_deframe1_reg_delay_dat[12]), + .O(plm_dfm_deframe1_dwbuf_N_22450) + ); + defparam plm_dfm_deframe1_dwbuf_wd_l0_i_m4_0_5_.INIT = 8'hE4; + LUT3 plm_dfm_deframe1_dwbuf_wd_l0_i_m4_0_5_ ( + .I0(plm_dfm_deframe1_high0), + .I1(plm_dfm_deframe1_reg_delay_dat[5]), + .I2(plm_dfm_deframe1_reg_delay_dat[13]), + .O(plm_dfm_deframe1_dwbuf_N_22451) + ); + defparam plm_dfm_deframe1_dwbuf_wd_l0_i_m4_0_6_.INIT = 8'hE4; + LUT3 plm_dfm_deframe1_dwbuf_wd_l0_i_m4_0_6_ ( + .I0(plm_dfm_deframe1_high0), + .I1(plm_dfm_deframe1_reg_delay_dat[6]), + .I2(plm_dfm_deframe1_reg_delay_dat[14]), + .O(plm_dfm_deframe1_dwbuf_N_22452) + ); + defparam plm_dfm_deframe1_dwbuf_wd_l0_i_m4_0_7_.INIT = 8'hE4; + LUT3 plm_dfm_deframe1_dwbuf_wd_l0_i_m4_0_7_ ( + .I0(plm_dfm_deframe1_high0), + .I1(plm_dfm_deframe1_reg_delay_dat[7]), + .I2(plm_dfm_deframe1_reg_delay_dat[15]), + .O(plm_dfm_deframe1_dwbuf_N_22453) + ); + defparam plm_dfm_deframe1_dwbuf_wd_l1_i_m4_0_4_.INIT = 8'hE4; + LUT3 plm_dfm_deframe1_dwbuf_wd_l1_i_m4_0_4_ ( + .I0(plm_dfm_deframe1_high1), + .I1(plm_dfm_deframe1_reg_delay_dat[4]), + .I2(plm_dfm_deframe1_reg_delay_dat[12]), + .O(plm_dfm_deframe1_dwbuf_N_22458) + ); + defparam plm_dfm_deframe1_dwbuf_wd_l2_i_m4_0_0_.INIT = 8'hE4; + LUT3 plm_dfm_deframe1_dwbuf_wd_l2_i_m4_0_0_ ( + .I0(plm_dfm_deframe1_high2), + .I1(plm_dfm_deframe1_reg_delay_dat[0]), + .I2(plm_dfm_deframe1_reg_delay_dat[8]), + .O(plm_dfm_deframe1_dwbuf_N_22462) + ); + defparam plm_dfm_deframe1_dwbuf_wd_l2_i_m4_0_1_.INIT = 8'hE4; + LUT3 plm_dfm_deframe1_dwbuf_wd_l2_i_m4_0_1_ ( + .I0(plm_dfm_deframe1_high2), + .I1(plm_dfm_deframe1_reg_delay_dat[1]), + .I2(plm_dfm_deframe1_reg_delay_dat[9]), + .O(plm_dfm_deframe1_dwbuf_N_22463) + ); + defparam plm_dfm_deframe1_dwbuf_wd_l2_i_m4_0_2_.INIT = 8'hE4; + LUT3 plm_dfm_deframe1_dwbuf_wd_l2_i_m4_0_2_ ( + .I0(plm_dfm_deframe1_high2), + .I1(plm_dfm_deframe1_reg_delay_dat[2]), + .I2(plm_dfm_deframe1_reg_delay_dat[10]), + .O(plm_dfm_deframe1_dwbuf_N_22464) + ); + defparam plm_dfm_deframe1_dwbuf_wd_l2_i_m4_0_3_.INIT = 8'hE4; + LUT3 plm_dfm_deframe1_dwbuf_wd_l2_i_m4_0_3_ ( + .I0(plm_dfm_deframe1_high2), + .I1(plm_dfm_deframe1_reg_delay_dat[3]), + .I2(plm_dfm_deframe1_reg_delay_dat[11]), + .O(plm_dfm_deframe1_dwbuf_N_22465) + ); + defparam plm_dfm_deframe1_dwbuf_wd_l2_i_m4_0_4_.INIT = 8'hE4; + LUT3 plm_dfm_deframe1_dwbuf_wd_l2_i_m4_0_4_ ( + .I0(plm_dfm_deframe1_high2), + .I1(plm_dfm_deframe1_reg_delay_dat[4]), + .I2(plm_dfm_deframe1_reg_delay_dat[12]), + .O(plm_dfm_deframe1_dwbuf_N_22466) + ); + defparam plm_dfm_deframe1_dwbuf_wd_l2_i_m4_0_5_.INIT = 8'hE4; + LUT3 plm_dfm_deframe1_dwbuf_wd_l2_i_m4_0_5_ ( + .I0(plm_dfm_deframe1_high2), + .I1(plm_dfm_deframe1_reg_delay_dat[5]), + .I2(plm_dfm_deframe1_reg_delay_dat[13]), + .O(plm_dfm_deframe1_dwbuf_N_22467) + ); + defparam plm_dfm_deframe1_dwbuf_wd_l3_i_m4_0_3_.INIT = 8'hE4; + LUT3 plm_dfm_deframe1_dwbuf_wd_l3_i_m4_0_3_ ( + .I0(plm_dfm_deframe1_high3), + .I1(plm_dfm_deframe1_reg_delay_dat[3]), + .I2(plm_dfm_deframe1_reg_delay_dat[11]), + .O(plm_dfm_deframe1_dwbuf_N_22473) + ); + defparam plm_dfm_deframe1_dwbuf_wd_l3_i_m4_0_4_.INIT = 8'hE4; + LUT3 plm_dfm_deframe1_dwbuf_wd_l3_i_m4_0_4_ ( + .I0(plm_dfm_deframe1_high3), + .I1(plm_dfm_deframe1_reg_delay_dat[4]), + .I2(plm_dfm_deframe1_reg_delay_dat[12]), + .O(plm_dfm_deframe1_dwbuf_N_22474) + ); + defparam plm_dfm_deframe1_dwbuf_wd_s0_i_m4_0_0_.INIT = 8'hE4; + LUT3 plm_dfm_deframe1_dwbuf_wd_s0_i_m4_0_0_ ( + .I0(plm_dfm_deframe1_high0), + .I1(plm_dfm_deframe1_reg_delay_stp[0]), + .I2(plm_dfm_deframe1_reg_delay_stp[1]), + .O(plm_dfm_deframe1_dwbuf_N_51073) + ); + defparam plm_dfm_deframe1_dwbuf_wd_s0_i_m4_0_1_.INIT = 8'hE4; + LUT3 plm_dfm_deframe1_dwbuf_wd_s0_i_m4_0_1_ ( + .I0(plm_dfm_deframe1_high0), + .I1(plm_dfm_deframe1_reg_delay_sdp[0]), + .I2(plm_dfm_deframe1_reg_delay_sdp[1]), + .O(plm_dfm_deframe1_dwbuf_N_51074) + ); + defparam plm_dfm_deframe1_dwbuf_wd_l3_i_m4_0_7_.INIT = 8'hE4; + LUT3 plm_dfm_deframe1_dwbuf_wd_l3_i_m4_0_7_ ( + .I0(plm_dfm_deframe1_high3), + .I1(plm_dfm_deframe1_reg_delay_dat[7]), + .I2(plm_dfm_deframe1_reg_delay_dat[15]), + .O(plm_dfm_deframe1_dwbuf_N_22477) + ); + defparam plm_dfm_deframe1_dwbuf_wd_l3_i_m4_0_6_.INIT = 8'hE4; + LUT3 plm_dfm_deframe1_dwbuf_wd_l3_i_m4_0_6_ ( + .I0(plm_dfm_deframe1_high3), + .I1(plm_dfm_deframe1_reg_delay_dat[6]), + .I2(plm_dfm_deframe1_reg_delay_dat[14]), + .O(plm_dfm_deframe1_dwbuf_N_22476) + ); + defparam plm_dfm_deframe1_dwbuf_wd_l3_i_m4_0_5_.INIT = 8'hE4; + LUT3 plm_dfm_deframe1_dwbuf_wd_l3_i_m4_0_5_ ( + .I0(plm_dfm_deframe1_high3), + .I1(plm_dfm_deframe1_reg_delay_dat[5]), + .I2(plm_dfm_deframe1_reg_delay_dat[13]), + .O(plm_dfm_deframe1_dwbuf_N_22475) + ); + defparam plm_dfm_deframe1_dwbuf_wd_l3_i_m4_0_2_.INIT = 8'hE4; + LUT3 plm_dfm_deframe1_dwbuf_wd_l3_i_m4_0_2_ ( + .I0(plm_dfm_deframe1_high3), + .I1(plm_dfm_deframe1_reg_delay_dat[2]), + .I2(plm_dfm_deframe1_reg_delay_dat[10]), + .O(plm_dfm_deframe1_dwbuf_N_22472) + ); + defparam plm_dfm_deframe1_dwbuf_wd_l3_i_m4_0_1_.INIT = 8'hE4; + LUT3 plm_dfm_deframe1_dwbuf_wd_l3_i_m4_0_1_ ( + .I0(plm_dfm_deframe1_high3), + .I1(plm_dfm_deframe1_reg_delay_dat[1]), + .I2(plm_dfm_deframe1_reg_delay_dat[9]), + .O(plm_dfm_deframe1_dwbuf_N_22471) + ); + defparam plm_dfm_deframe1_dwbuf_wd_l3_i_m4_0_0_.INIT = 8'hE4; + LUT3 plm_dfm_deframe1_dwbuf_wd_l3_i_m4_0_0_ ( + .I0(plm_dfm_deframe1_high3), + .I1(plm_dfm_deframe1_reg_delay_dat[0]), + .I2(plm_dfm_deframe1_reg_delay_dat[8]), + .O(plm_dfm_deframe1_dwbuf_N_22470) + ); + defparam plm_dfm_deframe1_dwbuf_wd_l2_i_m4_0_7_.INIT = 8'hE4; + LUT3 plm_dfm_deframe1_dwbuf_wd_l2_i_m4_0_7_ ( + .I0(plm_dfm_deframe1_high2), + .I1(plm_dfm_deframe1_reg_delay_dat[7]), + .I2(plm_dfm_deframe1_reg_delay_dat[15]), + .O(plm_dfm_deframe1_dwbuf_N_22469) + ); + defparam plm_dfm_deframe1_dwbuf_wd_l2_i_m4_0_6_.INIT = 8'hE4; + LUT3 plm_dfm_deframe1_dwbuf_wd_l2_i_m4_0_6_ ( + .I0(plm_dfm_deframe1_high2), + .I1(plm_dfm_deframe1_reg_delay_dat[6]), + .I2(plm_dfm_deframe1_reg_delay_dat[14]), + .O(plm_dfm_deframe1_dwbuf_N_22468) + ); + defparam plm_dfm_deframe1_dwbuf_wd_l1_i_m4_0_7_.INIT = 8'hE4; + LUT3 plm_dfm_deframe1_dwbuf_wd_l1_i_m4_0_7_ ( + .I0(plm_dfm_deframe1_high1), + .I1(plm_dfm_deframe1_reg_delay_dat[7]), + .I2(plm_dfm_deframe1_reg_delay_dat[15]), + .O(plm_dfm_deframe1_dwbuf_N_22461) + ); + defparam plm_dfm_deframe1_dwbuf_wd_l1_i_m4_0_6_.INIT = 8'hE4; + LUT3 plm_dfm_deframe1_dwbuf_wd_l1_i_m4_0_6_ ( + .I0(plm_dfm_deframe1_high1), + .I1(plm_dfm_deframe1_reg_delay_dat[6]), + .I2(plm_dfm_deframe1_reg_delay_dat[14]), + .O(plm_dfm_deframe1_dwbuf_N_22460) + ); + defparam plm_dfm_deframe1_dwbuf_wd_l1_i_m4_0_5_.INIT = 8'hE4; + LUT3 plm_dfm_deframe1_dwbuf_wd_l1_i_m4_0_5_ ( + .I0(plm_dfm_deframe1_high1), + .I1(plm_dfm_deframe1_reg_delay_dat[5]), + .I2(plm_dfm_deframe1_reg_delay_dat[13]), + .O(plm_dfm_deframe1_dwbuf_N_22459) + ); + defparam plm_dfm_deframe1_dwbuf_wd_l1_i_m4_0_3_.INIT = 8'hE4; + LUT3 plm_dfm_deframe1_dwbuf_wd_l1_i_m4_0_3_ ( + .I0(plm_dfm_deframe1_high1), + .I1(plm_dfm_deframe1_reg_delay_dat[3]), + .I2(plm_dfm_deframe1_reg_delay_dat[11]), + .O(plm_dfm_deframe1_dwbuf_N_22457) + ); + defparam plm_dfm_deframe1_dwbuf_wd_l1_i_m4_0_2_.INIT = 8'hE4; + LUT3 plm_dfm_deframe1_dwbuf_wd_l1_i_m4_0_2_ ( + .I0(plm_dfm_deframe1_high1), + .I1(plm_dfm_deframe1_reg_delay_dat[2]), + .I2(plm_dfm_deframe1_reg_delay_dat[10]), + .O(plm_dfm_deframe1_dwbuf_N_22456) + ); + defparam plm_dfm_deframe1_dwbuf_wd_l1_i_m4_0_1_.INIT = 8'hE4; + LUT3 plm_dfm_deframe1_dwbuf_wd_l1_i_m4_0_1_ ( + .I0(plm_dfm_deframe1_high1), + .I1(plm_dfm_deframe1_reg_delay_dat[1]), + .I2(plm_dfm_deframe1_reg_delay_dat[9]), + .O(plm_dfm_deframe1_dwbuf_N_22455) + ); + defparam plm_dfm_deframe1_dwbuf_wd_l1_i_m4_0_0_.INIT = 8'hE4; + LUT3 plm_dfm_deframe1_dwbuf_wd_l1_i_m4_0_0_ ( + .I0(plm_dfm_deframe1_high1), + .I1(plm_dfm_deframe1_reg_delay_dat[0]), + .I2(plm_dfm_deframe1_reg_delay_dat[8]), + .O(plm_dfm_deframe1_dwbuf_N_22454) + ); + defparam plm_dfm_deframe1_dwbuf_un1_reg_cnt_1_axb_0.INIT = 8'h78; + LUT3 plm_dfm_deframe1_dwbuf_un1_reg_cnt_1_axb_0 ( + .I0(plm_dfm_deframe1_dwbuf_reg_empty19_i), + .I1(plm_dfm_deframe1_dwbuf_reg_empty22_i), + .I2(plm_dfm_deframe1_dwbuf_reg_cnt[0]), + .O(plm_dfm_deframe1_dwbuf_un1_reg_cnt_1_axb_0_714) + ); + defparam plm_dfm_deframe1_dwbuf_N_69361_i.INIT = 16'hFEBA; + LUT4 plm_dfm_deframe1_dwbuf_N_69361_i ( + .I0(plm_dfm_deframe1_ferr), + .I1(plm_dfm_deframe1_high3), + .I2(plm_dfm_deframe1_reg_delay_edg[0]), + .I3(plm_dfm_deframe1_reg_delay_edg[1]), + .O(plm_dfm_deframe1_dwbuf_N_69361_i_707) + ); + defparam plm_dfm_deframe1_dwbuf_N_69360_i.INIT = 16'hFEBA; + LUT4 plm_dfm_deframe1_dwbuf_N_69360_i ( + .I0(plm_dfm_deframe1_ferr), + .I1(plm_dfm_deframe1_high3), + .I2(plm_dfm_deframe1_reg_delay_edb[0]), + .I3(plm_dfm_deframe1_reg_delay_edb[1]), + .O(plm_dfm_deframe1_dwbuf_N_69360_i_708) + ); + defparam plm_dfm_deframe1_dwbuf_pointers_reg_empty_8_0_am.INIT = 8'h08; + LUT3 plm_dfm_deframe1_dwbuf_pointers_reg_empty_8_0_am ( + .I0(plm_dfm_deframe1_dwbuf_reg_empty_5_0), + .I1(plm_dfm_deframe1_dwbuf_reg_cnt[0]), + .I2(plm_dfm_deframe1_dwbuf_reg_cnt[1]), + .O(plm_dfm_deframe1_dwbuf_reg_empty_8_0_am) + ); + defparam plm_dfm_deframe1_dwbuf_pointers_reg_empty_8_0_bm.INIT = 16'h8000; + LUT4 plm_dfm_deframe1_dwbuf_pointers_reg_empty_8_0_bm ( + .I0(plm_dfm_deframe1_dwbuf_reg_cnt[0]), + .I1(plm_dfm_deframe1_dwbuf_reg_cnt[1]), + .I2(plm_dfm_deframe1_dwbuf_reg_cnt[2]), + .I3(plm_dfm_deframe1_dwbuf_reg_cnt[3]), + .O(plm_dfm_deframe1_dwbuf_reg_empty_8_0_bm) + ); + MUXF5 plm_dfm_deframe1_dwbuf_pointers_reg_empty_8_0 ( + .I0(plm_dfm_deframe1_dwbuf_reg_empty_8_0_am), + .I1(plm_dfm_deframe1_dwbuf_reg_empty_8_0_bm), + .O(plm_dfm_deframe1_dwbuf_reg_empty_8), + .S(plm_dfm_deframe1_N_18645_i) + ); + defparam plm_dfm_deframe1_dwbuf_pointers_reg_empty19_i.INIT = 4'hE; + LUT2 plm_dfm_deframe1_dwbuf_pointers_reg_empty19_i ( + .I0(plm_dfm_deframe1_N_18645_i), + .I1(plm_dfm_deframe1_dword_pop), + .O(plm_dfm_deframe1_dwbuf_reg_empty19_i) + ); + defparam plm_dfm_deframe1_dwbuf_pointers_reg_empty22_i.INIT = 4'h7; + LUT2 plm_dfm_deframe1_dwbuf_pointers_reg_empty22_i ( + .I0(plm_dfm_deframe1_N_18645_i), + .I1(plm_dfm_deframe1_dword_pop), + .O(plm_dfm_deframe1_dwbuf_reg_empty22_i) + ); + defparam plm_dfm_deframe1_dwbuf_pointers_reg_wp3_4_axbxc1.INIT = 8'h78; + LUT3_L plm_dfm_deframe1_dwbuf_pointers_reg_wp3_4_axbxc1 ( + .I0(plm_dfm_deframe1_N_18645_i), + .I1(plm_dfm_deframe1_dwbuf_reg_wp3[0]), + .I2(plm_dfm_deframe1_dwbuf_reg_wp3[1]), + .LO(plm_dfm_deframe1_dwbuf_reg_wp3_4[1]) + ); + defparam plm_dfm_deframe1_dwbuf_pointers_reg_wp3_4_axbxc0.INIT = 4'h6; + LUT2_L plm_dfm_deframe1_dwbuf_pointers_reg_wp3_4_axbxc0 ( + .I0(plm_dfm_deframe1_N_18645_i), + .I1(plm_dfm_deframe1_dwbuf_reg_wp3[0]), + .LO(plm_dfm_deframe1_dwbuf_reg_wp3_4[0]) + ); + defparam plm_dfm_deframe1_dwbuf_pointers_reg_wp0_4_axbxc0.INIT = 4'h6; + LUT2_L plm_dfm_deframe1_dwbuf_pointers_reg_wp0_4_axbxc0 ( + .I0(plm_dfm_deframe1_N_18643_i), + .I1(plm_dfm_deframe1_dwbuf_reg_wp0[0]), + .LO(plm_dfm_deframe1_dwbuf_reg_wp0_4[0]) + ); + defparam plm_dfm_deframe1_dwbuf_pointers_reg_rp_4_axbxc3.INIT = 4'h6; + LUT2_L plm_dfm_deframe1_dwbuf_pointers_reg_rp_4_axbxc3 ( + .I0(plm_dfm_deframe1_dwbuf_reg_rp_4_p4), + .I1(plm_dfm_deframe1_dwbuf_reg_rp[3]), + .LO(plm_dfm_deframe1_dwbuf_reg_rp_4[3]) + ); + defparam plm_dfm_deframe1_dwbuf_pointers_reg_rp_4_axbxc2.INIT = 16'h78F0; + LUT4_L plm_dfm_deframe1_dwbuf_pointers_reg_rp_4_axbxc2 ( + .I0(plm_dfm_deframe1_dwbuf_reg_rp[0]), + .I1(plm_dfm_deframe1_dwbuf_reg_rp[1]), + .I2(plm_dfm_deframe1_dwbuf_reg_rp[2]), + .I3(plm_dfm_deframe1_dword_pop), + .LO(plm_dfm_deframe1_dwbuf_reg_rp_4[2]) + ); + defparam plm_dfm_deframe1_dwbuf_pointers_reg_rp_4_axbxc1.INIT = 8'h6C; + LUT3_L plm_dfm_deframe1_dwbuf_pointers_reg_rp_4_axbxc1 ( + .I0(plm_dfm_deframe1_dwbuf_reg_rp[0]), + .I1(plm_dfm_deframe1_dwbuf_reg_rp[1]), + .I2(plm_dfm_deframe1_dword_pop), + .LO(plm_dfm_deframe1_dwbuf_reg_rp_4[1]) + ); + defparam plm_dfm_deframe1_dwbuf_pointers_reg_rp_4_axbxc0.INIT = 4'h6; + LUT2_L plm_dfm_deframe1_dwbuf_pointers_reg_rp_4_axbxc0 ( + .I0(plm_dfm_deframe1_dwbuf_reg_rp[0]), + .I1(plm_dfm_deframe1_dword_pop), + .LO(plm_dfm_deframe1_dwbuf_reg_rp_4[0]) + ); + defparam plm_dfm_deframe1_dwbuf_un1_reg_cnt_1_axb_2.INIT = 8'h6C; + LUT3_L plm_dfm_deframe1_dwbuf_un1_reg_cnt_1_axb_2 ( + .I0(plm_dfm_deframe1_dwbuf_reg_empty22_i), + .I1(plm_dfm_deframe1_dwbuf_reg_cnt[2]), + .I2(plm_dfm_deframe1_dword_pop), + .LO(plm_dfm_deframe1_dwbuf_un1_reg_cnt_1_axb_2_709) + ); + defparam plm_dfm_deframe1_dwbuf_un1_reg_cnt_1_axb_1.INIT = 8'h6C; + LUT3_L plm_dfm_deframe1_dwbuf_un1_reg_cnt_1_axb_1 ( + .I0(plm_dfm_deframe1_dwbuf_reg_empty22_i), + .I1(plm_dfm_deframe1_dwbuf_reg_cnt[1]), + .I2(plm_dfm_deframe1_dword_pop), + .LO(plm_dfm_deframe1_dwbuf_un1_reg_cnt_1_axb_1_710) + ); + defparam plm_dfm_deframe1_dwbuf_pointers_reg_wp3_4_axbxc3.INIT = 4'h6; + LUT2_L plm_dfm_deframe1_dwbuf_pointers_reg_wp3_4_axbxc3 ( + .I0(plm_dfm_deframe1_dwbuf_reg_wp3_4_p4), + .I1(plm_dfm_deframe1_dwbuf_reg_wp3[3]), + .LO(plm_dfm_deframe1_dwbuf_reg_wp3_4[3]) + ); + defparam plm_dfm_deframe1_dwbuf_pointers_reg_wp3_4_axbxc2.INIT = 16'h7F80; + LUT4_L plm_dfm_deframe1_dwbuf_pointers_reg_wp3_4_axbxc2 ( + .I0(plm_dfm_deframe1_N_18645_i), + .I1(plm_dfm_deframe1_dwbuf_reg_wp3[0]), + .I2(plm_dfm_deframe1_dwbuf_reg_wp3[1]), + .I3(plm_dfm_deframe1_dwbuf_reg_wp3[2]), + .LO(plm_dfm_deframe1_dwbuf_reg_wp3_4[2]) + ); + defparam plm_dfm_deframe1_dwbuf_pointers_reg_wp2_4_axbxc3.INIT = 4'h6; + LUT2_L plm_dfm_deframe1_dwbuf_pointers_reg_wp2_4_axbxc3 ( + .I0(plm_dfm_deframe1_dwbuf_reg_wp2_4_p4), + .I1(plm_dfm_deframe1_dwbuf_reg_wp2[3]), + .LO(plm_dfm_deframe1_dwbuf_reg_wp2_4[3]) + ); + defparam plm_dfm_deframe1_dwbuf_pointers_reg_wp2_4_axbxc2.INIT = 16'hBF40; + LUT4_L plm_dfm_deframe1_dwbuf_pointers_reg_wp2_4_axbxc2 ( + .I0(plm_dfm_deframe1_reg_push_0_i[2]), + .I1(plm_dfm_deframe1_dwbuf_reg_wp2[0]), + .I2(plm_dfm_deframe1_dwbuf_reg_wp2[1]), + .I3(plm_dfm_deframe1_dwbuf_reg_wp2[2]), + .LO(plm_dfm_deframe1_dwbuf_reg_wp2_4[2]) + ); + defparam plm_dfm_deframe1_dwbuf_pointers_reg_wp2_4_axbxc1.INIT = 8'hB4; + LUT3_L plm_dfm_deframe1_dwbuf_pointers_reg_wp2_4_axbxc1 ( + .I0(plm_dfm_deframe1_reg_push_0_i[2]), + .I1(plm_dfm_deframe1_dwbuf_reg_wp2[0]), + .I2(plm_dfm_deframe1_dwbuf_reg_wp2[1]), + .LO(plm_dfm_deframe1_dwbuf_reg_wp2_4[1]) + ); + defparam plm_dfm_deframe1_dwbuf_pointers_reg_wp2_4_axbxc0.INIT = 4'h9; + LUT2_L plm_dfm_deframe1_dwbuf_pointers_reg_wp2_4_axbxc0 ( + .I0(plm_dfm_deframe1_reg_push_0_i[2]), + .I1(plm_dfm_deframe1_dwbuf_reg_wp2[0]), + .LO(plm_dfm_deframe1_dwbuf_reg_wp2_4[0]) + ); + defparam plm_dfm_deframe1_dwbuf_pointers_reg_wp1_4_axbxc3.INIT = 4'h6; + LUT2_L plm_dfm_deframe1_dwbuf_pointers_reg_wp1_4_axbxc3 ( + .I0(plm_dfm_deframe1_dwbuf_reg_wp1_4_p4), + .I1(plm_dfm_deframe1_dwbuf_reg_wp1[3]), + .LO(plm_dfm_deframe1_dwbuf_reg_wp1_4[3]) + ); + defparam plm_dfm_deframe1_dwbuf_pointers_reg_wp1_4_axbxc2.INIT = 16'h78F0; + LUT4_L plm_dfm_deframe1_dwbuf_pointers_reg_wp1_4_axbxc2 ( + .I0(plm_dfm_deframe1_dwbuf_reg_wp1[0]), + .I1(plm_dfm_deframe1_dwbuf_reg_wp1[1]), + .I2(plm_dfm_deframe1_dwbuf_reg_wp1[2]), + .I3(plm_dfm_deframe1_push1), + .LO(plm_dfm_deframe1_dwbuf_reg_wp1_4[2]) + ); + defparam plm_dfm_deframe1_dwbuf_pointers_reg_wp1_4_axbxc1.INIT = 8'h6C; + LUT3_L plm_dfm_deframe1_dwbuf_pointers_reg_wp1_4_axbxc1 ( + .I0(plm_dfm_deframe1_dwbuf_reg_wp1[0]), + .I1(plm_dfm_deframe1_dwbuf_reg_wp1[1]), + .I2(plm_dfm_deframe1_push1), + .LO(plm_dfm_deframe1_dwbuf_reg_wp1_4[1]) + ); + defparam plm_dfm_deframe1_dwbuf_pointers_reg_wp1_4_axbxc0.INIT = 4'h6; + LUT2_L plm_dfm_deframe1_dwbuf_pointers_reg_wp1_4_axbxc0 ( + .I0(plm_dfm_deframe1_dwbuf_reg_wp1[0]), + .I1(plm_dfm_deframe1_push1), + .LO(plm_dfm_deframe1_dwbuf_reg_wp1_4[0]) + ); + defparam plm_dfm_deframe1_dwbuf_pointers_reg_wp0_4_axbxc3.INIT = 4'h6; + LUT2_L plm_dfm_deframe1_dwbuf_pointers_reg_wp0_4_axbxc3 ( + .I0(plm_dfm_deframe1_dwbuf_reg_wp0_4_p4), + .I1(plm_dfm_deframe1_dwbuf_reg_wp0[3]), + .LO(plm_dfm_deframe1_dwbuf_reg_wp0_4[3]) + ); + defparam plm_dfm_deframe1_dwbuf_pointers_reg_wp0_4_axbxc2.INIT = 16'h7F80; + LUT4_L plm_dfm_deframe1_dwbuf_pointers_reg_wp0_4_axbxc2 ( + .I0(plm_dfm_deframe1_N_18643_i), + .I1(plm_dfm_deframe1_dwbuf_reg_wp0[0]), + .I2(plm_dfm_deframe1_dwbuf_reg_wp0[1]), + .I3(plm_dfm_deframe1_dwbuf_reg_wp0[2]), + .LO(plm_dfm_deframe1_dwbuf_reg_wp0_4[2]) + ); + defparam plm_dfm_deframe1_dwbuf_pointers_reg_wp0_4_axbxc1.INIT = 8'h78; + LUT3_L plm_dfm_deframe1_dwbuf_pointers_reg_wp0_4_axbxc1 ( + .I0(plm_dfm_deframe1_N_18643_i), + .I1(plm_dfm_deframe1_dwbuf_reg_wp0[0]), + .I2(plm_dfm_deframe1_dwbuf_reg_wp0[1]), + .LO(plm_dfm_deframe1_dwbuf_reg_wp0_4[1]) + ); + defparam plm_dfm_deframe1_dwbuf_un1_reg_empty19.INIT = 8'hA8; + LUT3 plm_dfm_deframe1_dwbuf_un1_reg_empty19 ( + .I0(plm_dfm_deframe1_dwbuf_reg_empty22_i), + .I1(plm_dfm_deframe1_dword_pop), + .I2(plm_dfm_deframe1_N_18645_i), + .O(plm_dfm_deframe1_dwbuf_un1_reg_empty19_715) + ); + FDP plm_dfm_deframe1_dwbuf_reg_opt_empty ( + .PRE(plm_rst), + .C(mgt_clk), + .D(plm_dfm_deframe1_dwbuf_reg_empty_716), + .Q(plm_dfm_deframe1_dword_empty) + ); + FDC plm_dfm_deframe1_dwbuf_reg_wp3_1_ ( + .C(mgt_clk), + .D(plm_dfm_deframe1_dwbuf_reg_wp3_4[1]), + .Q(plm_dfm_deframe1_dwbuf_reg_wp3[1]), + .CLR(plm_rst) + ); + FDC plm_dfm_deframe1_dwbuf_reg_wp3_0_ ( + .C(mgt_clk), + .D(plm_dfm_deframe1_dwbuf_reg_wp3_4[0]), + .Q(plm_dfm_deframe1_dwbuf_reg_wp3[0]), + .CLR(plm_rst) + ); + FDC plm_dfm_deframe1_dwbuf_reg_wp0_0_ ( + .C(mgt_clk), + .D(plm_dfm_deframe1_dwbuf_reg_wp0_4[0]), + .Q(plm_dfm_deframe1_dwbuf_reg_wp0[0]), + .CLR(plm_rst) + ); + FDC plm_dfm_deframe1_dwbuf_reg_rp_3_ ( + .C(mgt_clk), + .D(plm_dfm_deframe1_dwbuf_reg_rp_4[3]), + .Q(plm_dfm_deframe1_dwbuf_reg_rp[3]), + .CLR(plm_rst) + ); + FDC plm_dfm_deframe1_dwbuf_reg_rp_2_ ( + .C(mgt_clk), + .D(plm_dfm_deframe1_dwbuf_reg_rp_4[2]), + .Q(plm_dfm_deframe1_dwbuf_reg_rp[2]), + .CLR(plm_rst) + ); + FDC plm_dfm_deframe1_dwbuf_reg_rp_1_ ( + .C(mgt_clk), + .D(plm_dfm_deframe1_dwbuf_reg_rp_4[1]), + .Q(plm_dfm_deframe1_dwbuf_reg_rp[1]), + .CLR(plm_rst) + ); + FDC plm_dfm_deframe1_dwbuf_reg_rp_0_ ( + .C(mgt_clk), + .D(plm_dfm_deframe1_dwbuf_reg_rp_4[0]), + .Q(plm_dfm_deframe1_dwbuf_reg_rp[0]), + .CLR(plm_rst) + ); + FDC plm_dfm_deframe1_dwbuf_reg_cnt_3_ ( + .C(mgt_clk), + .D(plm_dfm_deframe1_dwbuf_un1_reg_cnt_1_s_3_711), + .Q(plm_dfm_deframe1_dwbuf_reg_cnt[3]), + .CLR(plm_rst) + ); + FDC plm_dfm_deframe1_dwbuf_reg_cnt_2_ ( + .C(mgt_clk), + .D(plm_dfm_deframe1_dwbuf_un1_reg_cnt_1_s_2_712), + .Q(plm_dfm_deframe1_dwbuf_reg_cnt[2]), + .CLR(plm_rst) + ); + FDC plm_dfm_deframe1_dwbuf_reg_cnt_1_ ( + .C(mgt_clk), + .D(plm_dfm_deframe1_dwbuf_un1_reg_cnt_1_s_1_713), + .Q(plm_dfm_deframe1_dwbuf_reg_cnt[1]), + .CLR(plm_rst) + ); + FDC plm_dfm_deframe1_dwbuf_reg_cnt_0_ ( + .C(mgt_clk), + .D(plm_dfm_deframe1_dwbuf_un1_reg_cnt_1_axb_0_714), + .Q(plm_dfm_deframe1_dwbuf_reg_cnt[0]), + .CLR(plm_rst) + ); + FDC plm_dfm_deframe1_dwbuf_reg_wp3_3_ ( + .C(mgt_clk), + .D(plm_dfm_deframe1_dwbuf_reg_wp3_4[3]), + .Q(plm_dfm_deframe1_dwbuf_reg_wp3[3]), + .CLR(plm_rst) + ); + FDC plm_dfm_deframe1_dwbuf_reg_wp3_2_ ( + .C(mgt_clk), + .D(plm_dfm_deframe1_dwbuf_reg_wp3_4[2]), + .Q(plm_dfm_deframe1_dwbuf_reg_wp3[2]), + .CLR(plm_rst) + ); + FDC plm_dfm_deframe1_dwbuf_reg_wp2_3_ ( + .C(mgt_clk), + .D(plm_dfm_deframe1_dwbuf_reg_wp2_4[3]), + .Q(plm_dfm_deframe1_dwbuf_reg_wp2[3]), + .CLR(plm_rst) + ); + FDC plm_dfm_deframe1_dwbuf_reg_wp2_2_ ( + .C(mgt_clk), + .D(plm_dfm_deframe1_dwbuf_reg_wp2_4[2]), + .Q(plm_dfm_deframe1_dwbuf_reg_wp2[2]), + .CLR(plm_rst) + ); + FDC plm_dfm_deframe1_dwbuf_reg_wp2_1_ ( + .C(mgt_clk), + .D(plm_dfm_deframe1_dwbuf_reg_wp2_4[1]), + .Q(plm_dfm_deframe1_dwbuf_reg_wp2[1]), + .CLR(plm_rst) + ); + FDC plm_dfm_deframe1_dwbuf_reg_wp2_0_ ( + .C(mgt_clk), + .D(plm_dfm_deframe1_dwbuf_reg_wp2_4[0]), + .Q(plm_dfm_deframe1_dwbuf_reg_wp2[0]), + .CLR(plm_rst) + ); + FDC plm_dfm_deframe1_dwbuf_reg_wp1_3_ ( + .C(mgt_clk), + .D(plm_dfm_deframe1_dwbuf_reg_wp1_4[3]), + .Q(plm_dfm_deframe1_dwbuf_reg_wp1[3]), + .CLR(plm_rst) + ); + FDC plm_dfm_deframe1_dwbuf_reg_wp1_2_ ( + .C(mgt_clk), + .D(plm_dfm_deframe1_dwbuf_reg_wp1_4[2]), + .Q(plm_dfm_deframe1_dwbuf_reg_wp1[2]), + .CLR(plm_rst) + ); + FDC plm_dfm_deframe1_dwbuf_reg_wp1_1_ ( + .C(mgt_clk), + .D(plm_dfm_deframe1_dwbuf_reg_wp1_4[1]), + .Q(plm_dfm_deframe1_dwbuf_reg_wp1[1]), + .CLR(plm_rst) + ); + FDC plm_dfm_deframe1_dwbuf_reg_wp1_0_ ( + .C(mgt_clk), + .D(plm_dfm_deframe1_dwbuf_reg_wp1_4[0]), + .Q(plm_dfm_deframe1_dwbuf_reg_wp1[0]), + .CLR(plm_rst) + ); + FDC plm_dfm_deframe1_dwbuf_reg_wp0_3_ ( + .C(mgt_clk), + .D(plm_dfm_deframe1_dwbuf_reg_wp0_4[3]), + .Q(plm_dfm_deframe1_dwbuf_reg_wp0[3]), + .CLR(plm_rst) + ); + FDC plm_dfm_deframe1_dwbuf_reg_wp0_2_ ( + .C(mgt_clk), + .D(plm_dfm_deframe1_dwbuf_reg_wp0_4[2]), + .Q(plm_dfm_deframe1_dwbuf_reg_wp0[2]), + .CLR(plm_rst) + ); + FDC plm_dfm_deframe1_dwbuf_reg_wp0_1_ ( + .C(mgt_clk), + .D(plm_dfm_deframe1_dwbuf_reg_wp0_4[1]), + .Q(plm_dfm_deframe1_dwbuf_reg_wp0[1]), + .CLR(plm_rst) + ); + FDC plm_dfm_deframe1_dwbuf_reg_opt_edbedg_1_ ( + .C(mgt_clk), + .D(plm_dfm_deframe1_dwbuf_dpo_edbedg[1]), + .Q(plm_dfm_deframe1_dword_edbedg[1]), + .CLR(plm_rst) + ); + FDC plm_dfm_deframe1_dwbuf_reg_opt_edbedg_0_ ( + .C(mgt_clk), + .D(plm_dfm_deframe1_dwbuf_dpo_edbedg[0]), + .Q(plm_dfm_deframe1_dword_edbedg[0]), + .CLR(plm_rst) + ); + FDC plm_dfm_deframe1_dwbuf_reg_opt_out_12_ ( + .C(mgt_clk), + .D(plm_dfm_deframe1_dwbuf_dpo_out[12]), + .Q(plm_dfm_deframe1_dword_out[12]), + .CLR(plm_rst) + ); + FDC plm_dfm_deframe1_dwbuf_reg_opt_out_11_ ( + .C(mgt_clk), + .D(plm_dfm_deframe1_dwbuf_dpo_out[11]), + .Q(plm_dfm_deframe1_dword_out[11]), + .CLR(plm_rst) + ); + FDC plm_dfm_deframe1_dwbuf_reg_opt_out_10_ ( + .C(mgt_clk), + .D(plm_dfm_deframe1_dwbuf_dpo_out[10]), + .Q(plm_dfm_deframe1_dword_out[10]), + .CLR(plm_rst) + ); + FDC plm_dfm_deframe1_dwbuf_reg_opt_out_9_ ( + .C(mgt_clk), + .D(plm_dfm_deframe1_dwbuf_dpo_out[9]), + .Q(plm_dfm_deframe1_dword_out[9]), + .CLR(plm_rst) + ); + FDC plm_dfm_deframe1_dwbuf_reg_opt_out_8_ ( + .C(mgt_clk), + .D(plm_dfm_deframe1_dwbuf_dpo_out[8]), + .Q(plm_dfm_deframe1_dword_out[8]), + .CLR(plm_rst) + ); + FDC plm_dfm_deframe1_dwbuf_reg_opt_out_7_ ( + .C(mgt_clk), + .D(plm_dfm_deframe1_dwbuf_dpo_out[7]), + .Q(plm_dfm_deframe1_dword_out[7]), + .CLR(plm_rst) + ); + FDC plm_dfm_deframe1_dwbuf_reg_opt_out_6_ ( + .C(mgt_clk), + .D(plm_dfm_deframe1_dwbuf_dpo_out[6]), + .Q(plm_dfm_deframe1_dword_out[6]), + .CLR(plm_rst) + ); + FDC plm_dfm_deframe1_dwbuf_reg_opt_out_5_ ( + .C(mgt_clk), + .D(plm_dfm_deframe1_dwbuf_dpo_out[5]), + .Q(plm_dfm_deframe1_dword_out[5]), + .CLR(plm_rst) + ); + FDC plm_dfm_deframe1_dwbuf_reg_opt_out_4_ ( + .C(mgt_clk), + .D(plm_dfm_deframe1_dwbuf_dpo_out[4]), + .Q(plm_dfm_deframe1_dword_out[4]), + .CLR(plm_rst) + ); + FDC plm_dfm_deframe1_dwbuf_reg_opt_out_3_ ( + .C(mgt_clk), + .D(plm_dfm_deframe1_dwbuf_dpo_out[3]), + .Q(plm_dfm_deframe1_dword_out[3]), + .CLR(plm_rst) + ); + FDC plm_dfm_deframe1_dwbuf_reg_opt_out_2_ ( + .C(mgt_clk), + .D(plm_dfm_deframe1_dwbuf_dpo_out[2]), + .Q(plm_dfm_deframe1_dword_out[2]), + .CLR(plm_rst) + ); + FDC plm_dfm_deframe1_dwbuf_reg_opt_out_1_ ( + .C(mgt_clk), + .D(plm_dfm_deframe1_dwbuf_dpo_out[1]), + .Q(plm_dfm_deframe1_dword_out[1]), + .CLR(plm_rst) + ); + FDC plm_dfm_deframe1_dwbuf_reg_opt_out_0_ ( + .C(mgt_clk), + .D(plm_dfm_deframe1_dwbuf_dpo_out[0]), + .Q(plm_dfm_deframe1_dword_out[0]), + .CLR(plm_rst) + ); + FDC plm_dfm_deframe1_dwbuf_reg_opt_sdpstp_1_ ( + .C(mgt_clk), + .D(plm_dfm_deframe1_dwbuf_dpo_sdpstp[1]), + .Q(plm_dfm_deframe1_dword_sdpstp[1]), + .CLR(plm_rst) + ); + FDC plm_dfm_deframe1_dwbuf_reg_opt_sdpstp_0_ ( + .C(mgt_clk), + .D(plm_dfm_deframe1_dwbuf_dpo_sdpstp[0]), + .Q(plm_dfm_deframe1_dword_sdpstp[0]), + .CLR(plm_rst) + ); + FDC plm_dfm_deframe1_dwbuf_reg_opt_out_27_ ( + .C(mgt_clk), + .D(plm_dfm_deframe1_dwbuf_dpo_out[27]), + .Q(plm_dfm_deframe1_dword_out[27]), + .CLR(plm_rst) + ); + FDC plm_dfm_deframe1_dwbuf_reg_opt_out_26_ ( + .C(mgt_clk), + .D(plm_dfm_deframe1_dwbuf_dpo_out[26]), + .Q(plm_dfm_deframe1_dword_out[26]), + .CLR(plm_rst) + ); + FDC plm_dfm_deframe1_dwbuf_reg_opt_out_25_ ( + .C(mgt_clk), + .D(plm_dfm_deframe1_dwbuf_dpo_out[25]), + .Q(plm_dfm_deframe1_dword_out[25]), + .CLR(plm_rst) + ); + FDC plm_dfm_deframe1_dwbuf_reg_opt_out_24_ ( + .C(mgt_clk), + .D(plm_dfm_deframe1_dwbuf_dpo_out[24]), + .Q(plm_dfm_deframe1_dword_out[24]), + .CLR(plm_rst) + ); + FDC plm_dfm_deframe1_dwbuf_reg_opt_out_23_ ( + .C(mgt_clk), + .D(plm_dfm_deframe1_dwbuf_dpo_out[23]), + .Q(plm_dfm_deframe1_dword_out[23]), + .CLR(plm_rst) + ); + FDC plm_dfm_deframe1_dwbuf_reg_opt_out_22_ ( + .C(mgt_clk), + .D(plm_dfm_deframe1_dwbuf_dpo_out[22]), + .Q(plm_dfm_deframe1_dword_out[22]), + .CLR(plm_rst) + ); + FDC plm_dfm_deframe1_dwbuf_reg_opt_out_21_ ( + .C(mgt_clk), + .D(plm_dfm_deframe1_dwbuf_dpo_out[21]), + .Q(plm_dfm_deframe1_dword_out[21]), + .CLR(plm_rst) + ); + FDC plm_dfm_deframe1_dwbuf_reg_opt_out_20_ ( + .C(mgt_clk), + .D(plm_dfm_deframe1_dwbuf_dpo_out[20]), + .Q(plm_dfm_deframe1_dword_out[20]), + .CLR(plm_rst) + ); + FDC plm_dfm_deframe1_dwbuf_reg_opt_out_19_ ( + .C(mgt_clk), + .D(plm_dfm_deframe1_dwbuf_dpo_out[19]), + .Q(plm_dfm_deframe1_dword_out[19]), + .CLR(plm_rst) + ); + FDC plm_dfm_deframe1_dwbuf_reg_opt_out_18_ ( + .C(mgt_clk), + .D(plm_dfm_deframe1_dwbuf_dpo_out[18]), + .Q(plm_dfm_deframe1_dword_out[18]), + .CLR(plm_rst) + ); + FDC plm_dfm_deframe1_dwbuf_reg_opt_out_17_ ( + .C(mgt_clk), + .D(plm_dfm_deframe1_dwbuf_dpo_out[17]), + .Q(plm_dfm_deframe1_dword_out[17]), + .CLR(plm_rst) + ); + FDC plm_dfm_deframe1_dwbuf_reg_opt_out_16_ ( + .C(mgt_clk), + .D(plm_dfm_deframe1_dwbuf_dpo_out[16]), + .Q(plm_dfm_deframe1_dword_out[16]), + .CLR(plm_rst) + ); + FDC plm_dfm_deframe1_dwbuf_reg_opt_out_15_ ( + .C(mgt_clk), + .D(plm_dfm_deframe1_dwbuf_dpo_out[15]), + .Q(plm_dfm_deframe1_dword_out[15]), + .CLR(plm_rst) + ); + FDC plm_dfm_deframe1_dwbuf_reg_opt_out_14_ ( + .C(mgt_clk), + .D(plm_dfm_deframe1_dwbuf_dpo_out[14]), + .Q(plm_dfm_deframe1_dword_out[14]), + .CLR(plm_rst) + ); + FDC plm_dfm_deframe1_dwbuf_reg_opt_out_13_ ( + .C(mgt_clk), + .D(plm_dfm_deframe1_dwbuf_dpo_out[13]), + .Q(plm_dfm_deframe1_dword_out[13]), + .CLR(plm_rst) + ); + FDC plm_dfm_deframe1_dwbuf_reg_opt_out_31_ ( + .C(mgt_clk), + .D(plm_dfm_deframe1_dwbuf_dpo_out[31]), + .Q(plm_dfm_deframe1_dword_out[31]), + .CLR(plm_rst) + ); + FDC plm_dfm_deframe1_dwbuf_reg_opt_out_30_ ( + .C(mgt_clk), + .D(plm_dfm_deframe1_dwbuf_dpo_out[30]), + .Q(plm_dfm_deframe1_dword_out[30]), + .CLR(plm_rst) + ); + FDC plm_dfm_deframe1_dwbuf_reg_opt_out_29_ ( + .C(mgt_clk), + .D(plm_dfm_deframe1_dwbuf_dpo_out[29]), + .Q(plm_dfm_deframe1_dword_out[29]), + .CLR(plm_rst) + ); + FDC plm_dfm_deframe1_dwbuf_reg_opt_out_28_ ( + .C(mgt_clk), + .D(plm_dfm_deframe1_dwbuf_dpo_out[28]), + .Q(plm_dfm_deframe1_dword_out[28]), + .CLR(plm_rst) + ); + FDPE plm_dfm_deframe1_dwbuf_reg_empty ( + .PRE(plm_rst), + .CE(plm_dfm_deframe1_dwbuf_un1_reg_empty19_715), + .C(mgt_clk), + .D(plm_dfm_deframe1_dwbuf_reg_empty_8), + .Q(plm_dfm_deframe1_dwbuf_reg_empty_716) + ); + defparam plm_dfm_deframe1_dwbuf_un1_reg_cnt_1_axb_3.INIT = 8'hC6; + LUT3_L plm_dfm_deframe1_dwbuf_un1_reg_cnt_1_axb_3 ( + .I0(plm_dfm_deframe1_dword_pop), + .I1(plm_dfm_deframe1_dwbuf_reg_cnt[3]), + .I2(plm_dfm_deframe1_N_18645_i), + .LO(plm_dfm_deframe1_dwbuf_un1_reg_cnt_1_axb_3_717) + ); + defparam plm_dfm_deframe1_qwfsm_reg_by1_preh_out16.INIT = 4'h1; + LUT2 plm_dfm_deframe1_qwfsm_reg_by1_preh_out16 ( + .I0(plm_dfm_deframe1_qwfsm_reg_state[4]), + .I1(plm_dfm_deframe1_qwfsm_reg_state[5]), + .O(plm_dfm_deframe1_qwfsm_reg_by1_preh_out16_720) + ); + defparam plm_dfm_deframe1_qwfsm_qwfsm_vector_N_9986_i.INIT = 4'hE; + LUT2 plm_dfm_deframe1_qwfsm_qwfsm_vector_N_9986_i ( + .I0(plm_dfm_deframe1_qwfsm_reg_phi1_724), + .I1(plm_phy_cke_0_402), + .O(plm_dfm_deframe1_qwfsm_N_9986_i) + ); + defparam plm_dfm_deframe1_qwfsm_reg_by1_prel_edbedg_1_sqmuxa.INIT = 8'h54; + LUT3 plm_dfm_deframe1_qwfsm_reg_by1_prel_edbedg_1_sqmuxa ( + .I0(plm_dfm_deframe1_dword_edbedg[0]), + .I1(plm_dfm_deframe1_qwfsm_reg_state[2]), + .I2(plm_dfm_deframe1_qwfsm_reg_state[3]), + .O(plm_dfm_deframe1_qwfsm_reg_by1_preh_edbedg_cnst[1]) + ); + defparam plm_dfm_deframe1_qwfsm_pop_iv_0.INIT = 16'hCCC5; + LUT4 plm_dfm_deframe1_qwfsm_pop_iv_0 ( + .I0(plm_dfm_deframe1_qwfsm_reg_by1_preh_out16_720), + .I1(plm_dfm_deframe1_dword_empty), + .I2(plm_dfm_deframe1_qwfsm_reg_state_0__59), + .I3(plm_dfm_deframe1_qwfsm_reg_state_1__58), + .O(plm_dfm_deframe1_qwfsm_pop_iv_0_719) + ); + defparam plm_dfm_deframe1_qwfsm_pop_iv_1.INIT = 16'hEFFE; + LUT4 plm_dfm_deframe1_qwfsm_pop_iv_1 ( + .I0(plm_dfm_deframe1_qwfsm_reg_by1_preh_out16_720), + .I1(plm_dfm_deframe1_dword_empty), + .I2(plm_dfm_deframe1_dword_sdpstp[0]), + .I3(plm_dfm_deframe1_dword_sdpstp[1]), + .O(plm_dfm_deframe1_qwfsm_pop_iv_1_718) + ); + defparam plm_dfm_deframe1_qwfsm_prerelease_reg_by1_preh_sdpstp_6_iv_1_.INIT = 8'hC8; + LUT3 plm_dfm_deframe1_qwfsm_prerelease_reg_by1_preh_sdpstp_6_iv_1_ ( + .I0(N_3580_m_289), + .I1(plm_dfm_deframe1_qwfsm_reg_by1_preh_out16_720), + .I2(plm_dfm_deframe1_dword_sdpstp[1]), + .O(plm_dfm_deframe1_qwfsm_reg_by1_preh_sdpstp_6[1]) + ); + defparam plm_dfm_deframe1_qwfsm_prerelease_reg_by1_preh_out_6_8_.INIT = 8'h40; + LUT3 plm_dfm_deframe1_qwfsm_prerelease_reg_by1_preh_out_6_8_ ( + .I0(N_3580_m_289), + .I1(plm_dfm_deframe1_qwfsm_reg_by1_preh_out16_720), + .I2(plm_dfm_deframe1_dword_out[8]), + .O(plm_dfm_deframe1_qwfsm_reg_by1_preh_out_6[8]) + ); + defparam plm_dfm_deframe1_qwfsm_prerelease_reg_by1_preh_out_6_9_.INIT = 8'h40; + LUT3 plm_dfm_deframe1_qwfsm_prerelease_reg_by1_preh_out_6_9_ ( + .I0(N_3580_m_289), + .I1(plm_dfm_deframe1_qwfsm_reg_by1_preh_out16_720), + .I2(plm_dfm_deframe1_dword_out[9]), + .O(plm_dfm_deframe1_qwfsm_reg_by1_preh_out_6[9]) + ); + defparam plm_dfm_deframe1_qwfsm_prerelease_reg_by1_preh_out_6_10_.INIT = 8'h40; + LUT3 plm_dfm_deframe1_qwfsm_prerelease_reg_by1_preh_out_6_10_ ( + .I0(N_3580_m_289), + .I1(plm_dfm_deframe1_qwfsm_reg_by1_preh_out16_720), + .I2(plm_dfm_deframe1_dword_out[10]), + .O(plm_dfm_deframe1_qwfsm_reg_by1_preh_out_6[10]) + ); + defparam plm_dfm_deframe1_qwfsm_prerelease_reg_by1_preh_out_6_11_.INIT = 8'h40; + LUT3 plm_dfm_deframe1_qwfsm_prerelease_reg_by1_preh_out_6_11_ ( + .I0(N_3580_m_289), + .I1(plm_dfm_deframe1_qwfsm_reg_by1_preh_out16_720), + .I2(plm_dfm_deframe1_dword_out[11]), + .O(plm_dfm_deframe1_qwfsm_reg_by1_preh_out_6[11]) + ); + defparam plm_dfm_deframe1_qwfsm_prerelease_reg_by1_preh_out_6_12_.INIT = 8'h40; + LUT3 plm_dfm_deframe1_qwfsm_prerelease_reg_by1_preh_out_6_12_ ( + .I0(N_3580_m_289), + .I1(plm_dfm_deframe1_qwfsm_reg_by1_preh_out16_720), + .I2(plm_dfm_deframe1_dword_out[12]), + .O(plm_dfm_deframe1_qwfsm_reg_by1_preh_out_6[12]) + ); + defparam plm_dfm_deframe1_qwfsm_prerelease_reg_by1_preh_out_6_13_.INIT = 8'h40; + LUT3 plm_dfm_deframe1_qwfsm_prerelease_reg_by1_preh_out_6_13_ ( + .I0(N_3580_m_289), + .I1(plm_dfm_deframe1_qwfsm_reg_by1_preh_out16_720), + .I2(plm_dfm_deframe1_dword_out[13]), + .O(plm_dfm_deframe1_qwfsm_reg_by1_preh_out_6[13]) + ); + defparam plm_dfm_deframe1_qwfsm_prerelease_reg_by1_preh_out_6_14_.INIT = 8'h40; + LUT3 plm_dfm_deframe1_qwfsm_prerelease_reg_by1_preh_out_6_14_ ( + .I0(N_3580_m_289), + .I1(plm_dfm_deframe1_qwfsm_reg_by1_preh_out16_720), + .I2(plm_dfm_deframe1_dword_out[14]), + .O(plm_dfm_deframe1_qwfsm_reg_by1_preh_out_6[14]) + ); + defparam plm_dfm_deframe1_qwfsm_prerelease_reg_by1_preh_out_6_15_.INIT = 8'h40; + LUT3 plm_dfm_deframe1_qwfsm_prerelease_reg_by1_preh_out_6_15_ ( + .I0(N_3580_m_289), + .I1(plm_dfm_deframe1_qwfsm_reg_by1_preh_out16_720), + .I2(plm_dfm_deframe1_dword_out[15]), + .O(plm_dfm_deframe1_qwfsm_reg_by1_preh_out_6[15]) + ); + defparam plm_dfm_deframe1_qwfsm_prerelease_reg_by1_preh_out_6_16_.INIT = 8'h40; + LUT3 plm_dfm_deframe1_qwfsm_prerelease_reg_by1_preh_out_6_16_ ( + .I0(N_3580_m_289), + .I1(plm_dfm_deframe1_qwfsm_reg_by1_preh_out16_720), + .I2(plm_dfm_deframe1_dword_out[16]), + .O(plm_dfm_deframe1_qwfsm_reg_by1_preh_out_6[16]) + ); + defparam plm_dfm_deframe1_qwfsm_prerelease_reg_by1_preh_out_6_17_.INIT = 8'h40; + LUT3 plm_dfm_deframe1_qwfsm_prerelease_reg_by1_preh_out_6_17_ ( + .I0(N_3580_m_289), + .I1(plm_dfm_deframe1_qwfsm_reg_by1_preh_out16_720), + .I2(plm_dfm_deframe1_dword_out[17]), + .O(plm_dfm_deframe1_qwfsm_reg_by1_preh_out_6[17]) + ); + defparam plm_dfm_deframe1_qwfsm_prerelease_reg_by1_preh_out_6_18_.INIT = 8'h40; + LUT3 plm_dfm_deframe1_qwfsm_prerelease_reg_by1_preh_out_6_18_ ( + .I0(N_3580_m_289), + .I1(plm_dfm_deframe1_qwfsm_reg_by1_preh_out16_720), + .I2(plm_dfm_deframe1_dword_out[18]), + .O(plm_dfm_deframe1_qwfsm_reg_by1_preh_out_6[18]) + ); + defparam plm_dfm_deframe1_qwfsm_prerelease_reg_by1_preh_out_6_19_.INIT = 8'h40; + LUT3 plm_dfm_deframe1_qwfsm_prerelease_reg_by1_preh_out_6_19_ ( + .I0(N_3580_m_289), + .I1(plm_dfm_deframe1_qwfsm_reg_by1_preh_out16_720), + .I2(plm_dfm_deframe1_dword_out[19]), + .O(plm_dfm_deframe1_qwfsm_reg_by1_preh_out_6[19]) + ); + defparam plm_dfm_deframe1_qwfsm_prerelease_reg_by1_preh_out_6_20_.INIT = 8'h40; + LUT3 plm_dfm_deframe1_qwfsm_prerelease_reg_by1_preh_out_6_20_ ( + .I0(N_3580_m_289), + .I1(plm_dfm_deframe1_qwfsm_reg_by1_preh_out16_720), + .I2(plm_dfm_deframe1_dword_out[20]), + .O(plm_dfm_deframe1_qwfsm_reg_by1_preh_out_6[20]) + ); + defparam plm_dfm_deframe1_qwfsm_prerelease_reg_by1_preh_out_6_21_.INIT = 8'h40; + LUT3 plm_dfm_deframe1_qwfsm_prerelease_reg_by1_preh_out_6_21_ ( + .I0(N_3580_m_289), + .I1(plm_dfm_deframe1_qwfsm_reg_by1_preh_out16_720), + .I2(plm_dfm_deframe1_dword_out[21]), + .O(plm_dfm_deframe1_qwfsm_reg_by1_preh_out_6[21]) + ); + defparam plm_dfm_deframe1_qwfsm_prerelease_reg_by1_preh_out_6_22_.INIT = 8'h40; + LUT3 plm_dfm_deframe1_qwfsm_prerelease_reg_by1_preh_out_6_22_ ( + .I0(N_3580_m_289), + .I1(plm_dfm_deframe1_qwfsm_reg_by1_preh_out16_720), + .I2(plm_dfm_deframe1_dword_out[22]), + .O(plm_dfm_deframe1_qwfsm_reg_by1_preh_out_6[22]) + ); + defparam plm_dfm_deframe1_qwfsm_prerelease_reg_by1_preh_out_6_23_.INIT = 8'h40; + LUT3 plm_dfm_deframe1_qwfsm_prerelease_reg_by1_preh_out_6_23_ ( + .I0(N_3580_m_289), + .I1(plm_dfm_deframe1_qwfsm_reg_by1_preh_out16_720), + .I2(plm_dfm_deframe1_dword_out[23]), + .O(plm_dfm_deframe1_qwfsm_reg_by1_preh_out_6[23]) + ); + defparam plm_dfm_deframe1_qwfsm_prerelease_reg_by1_preh_sdpstp_6_0_.INIT = 8'h40; + LUT3 plm_dfm_deframe1_qwfsm_prerelease_reg_by1_preh_sdpstp_6_0_ ( + .I0(N_3580_m_289), + .I1(plm_dfm_deframe1_qwfsm_reg_by1_preh_out16_720), + .I2(plm_dfm_deframe1_dword_sdpstp[0]), + .O(plm_dfm_deframe1_qwfsm_reg_by1_preh_sdpstp_6[0]) + ); + defparam plm_dfm_deframe1_qwfsm_dword_pop.INIT = 16'h7770; + LUT4 plm_dfm_deframe1_qwfsm_dword_pop ( + .I0(plm_dfm_deframe1_qwfsm_pop_iv_0_719), + .I1(plm_dfm_deframe1_qwfsm_pop_iv_1_718), + .I2(plm_dfm_deframe1_qwfsm_reg_phi1_724), + .I3(plm_phy_cke_0_402), + .O(plm_dfm_deframe1_dword_pop) + ); + defparam plm_dfm_deframe1_qwfsm_prerelease_reg_by1_preh_out_6_iv_24_.INIT = 8'hC8; + LUT3 plm_dfm_deframe1_qwfsm_prerelease_reg_by1_preh_out_6_iv_24_ ( + .I0(N_3580_m_289), + .I1(plm_dfm_deframe1_qwfsm_reg_by1_preh_out16_720), + .I2(plm_dfm_deframe1_dword_out[24]), + .O(plm_dfm_deframe1_qwfsm_reg_by1_preh_out_6[24]) + ); + defparam plm_dfm_deframe1_qwfsm_prerelease_reg_by1_preh_out_6_iv_25_.INIT = 8'hC8; + LUT3 plm_dfm_deframe1_qwfsm_prerelease_reg_by1_preh_out_6_iv_25_ ( + .I0(N_3580_m_289), + .I1(plm_dfm_deframe1_qwfsm_reg_by1_preh_out16_720), + .I2(plm_dfm_deframe1_dword_out[25]), + .O(plm_dfm_deframe1_qwfsm_reg_by1_preh_out_6[25]) + ); + defparam plm_dfm_deframe1_qwfsm_prerelease_reg_by1_preh_out_6_iv_26_.INIT = 8'hC8; + LUT3 plm_dfm_deframe1_qwfsm_prerelease_reg_by1_preh_out_6_iv_26_ ( + .I0(N_3580_m_289), + .I1(plm_dfm_deframe1_qwfsm_reg_by1_preh_out16_720), + .I2(plm_dfm_deframe1_dword_out[26]), + .O(plm_dfm_deframe1_qwfsm_reg_by1_preh_out_6[26]) + ); + defparam plm_dfm_deframe1_qwfsm_prerelease_reg_by1_preh_out_6_iv_27_.INIT = 8'hC8; + LUT3 plm_dfm_deframe1_qwfsm_prerelease_reg_by1_preh_out_6_iv_27_ ( + .I0(N_3580_m_289), + .I1(plm_dfm_deframe1_qwfsm_reg_by1_preh_out16_720), + .I2(plm_dfm_deframe1_dword_out[27]), + .O(plm_dfm_deframe1_qwfsm_reg_by1_preh_out_6[27]) + ); + defparam plm_dfm_deframe1_qwfsm_prerelease_reg_by1_preh_out_6_iv_28_.INIT = 8'hC8; + LUT3 plm_dfm_deframe1_qwfsm_prerelease_reg_by1_preh_out_6_iv_28_ ( + .I0(N_3580_m_289), + .I1(plm_dfm_deframe1_qwfsm_reg_by1_preh_out16_720), + .I2(plm_dfm_deframe1_dword_out[28]), + .O(plm_dfm_deframe1_qwfsm_reg_by1_preh_out_6[28]) + ); + defparam plm_dfm_deframe1_qwfsm_prerelease_reg_by1_preh_out_6_iv_29_.INIT = 8'hC8; + LUT3 plm_dfm_deframe1_qwfsm_prerelease_reg_by1_preh_out_6_iv_29_ ( + .I0(N_3580_m_289), + .I1(plm_dfm_deframe1_qwfsm_reg_by1_preh_out16_720), + .I2(plm_dfm_deframe1_dword_out[29]), + .O(plm_dfm_deframe1_qwfsm_reg_by1_preh_out_6[29]) + ); + defparam plm_dfm_deframe1_qwfsm_prerelease_reg_by1_preh_out_6_iv_30_.INIT = 8'hC8; + LUT3 plm_dfm_deframe1_qwfsm_prerelease_reg_by1_preh_out_6_iv_30_ ( + .I0(N_3580_m_289), + .I1(plm_dfm_deframe1_qwfsm_reg_by1_preh_out16_720), + .I2(plm_dfm_deframe1_dword_out[30]), + .O(plm_dfm_deframe1_qwfsm_reg_by1_preh_out_6[30]) + ); + defparam plm_dfm_deframe1_qwfsm_prerelease_reg_by1_preh_out_6_iv_31_.INIT = 8'hC8; + LUT3 plm_dfm_deframe1_qwfsm_prerelease_reg_by1_preh_out_6_iv_31_ ( + .I0(N_3580_m_289), + .I1(plm_dfm_deframe1_qwfsm_reg_by1_preh_out16_720), + .I2(plm_dfm_deframe1_dword_out[31]), + .O(plm_dfm_deframe1_qwfsm_reg_by1_preh_out_6[31]) + ); + defparam plm_dfm_deframe1_qwfsm_prerelease_reg_by1_preh_edbedg_8_0_0_.INIT = 16'h7773; + LUT4 plm_dfm_deframe1_qwfsm_prerelease_reg_by1_preh_edbedg_8_0_0_ ( + .I0(N_3580_m_289), + .I1(plm_dfm_deframe1_qwfsm_reg_by1_preh_out16_720), + .I2(plm_dfm_deframe1_dword_edbedg[0]), + .I3(plm_dfm_deframe1_qwfsm_reg_by1_preh_edbedg_cnst[1]), + .O(plm_dfm_deframe1_qwfsm_reg_by1_preh_edbedg_8[0]) + ); + defparam plm_dfm_deframe1_qwfsm_prerelease_reg_by1_preh_edbedg_8_0_1_.INIT = 16'hFF40; + LUT4 plm_dfm_deframe1_qwfsm_prerelease_reg_by1_preh_edbedg_8_0_1_ ( + .I0(N_3580_m_289), + .I1(plm_dfm_deframe1_qwfsm_reg_by1_preh_out16_720), + .I2(plm_dfm_deframe1_dword_edbedg[1]), + .I3(plm_dfm_deframe1_qwfsm_reg_by1_preh_edbedg_cnst[1]), + .O(plm_dfm_deframe1_qwfsm_reg_by1_preh_edbedg_8[1]) + ); + defparam plm_dfm_deframe1_qwfsm_prerelease_N_8799_i.INIT = 8'h73; + LUT3 plm_dfm_deframe1_qwfsm_prerelease_N_8799_i ( + .I0(N_3580_m_289), + .I1(plm_dfm_deframe1_qwfsm_reg_by1_preh_out16_720), + .I2(plm_dfm_deframe1_dword_out[0]), + .O(plm_dfm_deframe1_qwfsm_N_8799_i) + ); + defparam plm_dfm_deframe1_qwfsm_prerelease_N_8798_i.INIT = 8'h73; + LUT3 plm_dfm_deframe1_qwfsm_prerelease_N_8798_i ( + .I0(N_3580_m_289), + .I1(plm_dfm_deframe1_qwfsm_reg_by1_preh_out16_720), + .I2(plm_dfm_deframe1_dword_out[1]), + .O(plm_dfm_deframe1_qwfsm_N_8798_i) + ); + defparam plm_dfm_deframe1_qwfsm_prerelease_N_8797_i.INIT = 8'h73; + LUT3 plm_dfm_deframe1_qwfsm_prerelease_N_8797_i ( + .I0(N_3580_m_289), + .I1(plm_dfm_deframe1_qwfsm_reg_by1_preh_out16_720), + .I2(plm_dfm_deframe1_dword_out[2]), + .O(plm_dfm_deframe1_qwfsm_N_8797_i) + ); + defparam plm_dfm_deframe1_qwfsm_prerelease_N_8796_i.INIT = 8'h73; + LUT3 plm_dfm_deframe1_qwfsm_prerelease_N_8796_i ( + .I0(N_3580_m_289), + .I1(plm_dfm_deframe1_qwfsm_reg_by1_preh_out16_720), + .I2(plm_dfm_deframe1_dword_out[3]), + .O(plm_dfm_deframe1_qwfsm_N_8796_i) + ); + defparam plm_dfm_deframe1_qwfsm_prerelease_N_8795_i.INIT = 8'h73; + LUT3 plm_dfm_deframe1_qwfsm_prerelease_N_8795_i ( + .I0(N_3580_m_289), + .I1(plm_dfm_deframe1_qwfsm_reg_by1_preh_out16_720), + .I2(plm_dfm_deframe1_dword_out[4]), + .O(plm_dfm_deframe1_qwfsm_N_8795_i) + ); + defparam plm_dfm_deframe1_qwfsm_prerelease_N_8794_i.INIT = 8'h73; + LUT3 plm_dfm_deframe1_qwfsm_prerelease_N_8794_i ( + .I0(N_3580_m_289), + .I1(plm_dfm_deframe1_qwfsm_reg_by1_preh_out16_720), + .I2(plm_dfm_deframe1_dword_out[5]), + .O(plm_dfm_deframe1_qwfsm_N_8794_i) + ); + defparam plm_dfm_deframe1_qwfsm_prerelease_N_8793_i.INIT = 8'h73; + LUT3 plm_dfm_deframe1_qwfsm_prerelease_N_8793_i ( + .I0(N_3580_m_289), + .I1(plm_dfm_deframe1_qwfsm_reg_by1_preh_out16_720), + .I2(plm_dfm_deframe1_dword_out[6]), + .O(plm_dfm_deframe1_qwfsm_N_8793_i) + ); + defparam plm_dfm_deframe1_qwfsm_prerelease_N_8792_i.INIT = 8'h73; + LUT3 plm_dfm_deframe1_qwfsm_prerelease_N_8792_i ( + .I0(N_3580_m_289), + .I1(plm_dfm_deframe1_qwfsm_reg_by1_preh_out16_720), + .I2(plm_dfm_deframe1_dword_out[7]), + .O(plm_dfm_deframe1_qwfsm_N_8792_i) + ); + defparam plm_dfm_deframe1_qwfsm_nxt_state_6_sqmuxa_1.INIT = 16'h2000; + LUT4_L plm_dfm_deframe1_qwfsm_nxt_state_6_sqmuxa_1 ( + .I0(N_3541), + .I1(plm_dfm_deframe1_dword_sdpstp[0]), + .I2(plm_dfm_deframe1_qwfsm_nxt_state_1[7]), + .I3(plm_dfm_deframe1_qwfsm_reg_state_0__59), + .LO(plm_dfm_deframe1_qwfsm_nxt_state_6_sqmuxa_1_722) + ); + defparam plm_dfm_deframe1_qwfsm_nxt_state_6_sqmuxa.INIT = 16'h2000; + LUT4_L plm_dfm_deframe1_qwfsm_nxt_state_6_sqmuxa ( + .I0(N_3541), + .I1(plm_dfm_deframe1_dword_sdpstp[0]), + .I2(plm_dfm_deframe1_qwfsm_nxt_state_1[7]), + .I3(plm_dfm_deframe1_qwfsm_reg_state_1__58), + .LO(plm_dfm_deframe1_qwfsm_nxt_state_6_sqmuxa_723) + ); + defparam plm_dfm_deframe1_qwfsm_nxt_state_i_1_0_.INIT = 8'h07; + LUT3_L plm_dfm_deframe1_qwfsm_nxt_state_i_1_0_ ( + .I0(N_3543), + .I1(plm_dfm_deframe1_qwfsm_reg_state_1__58), + .I2(plm_dfm_deframe1_qwfsm_reg_state_7__60), + .LO(plm_dfm_deframe1_qwfsm_nxt_state_i_1[0]) + ); + defparam plm_dfm_deframe1_qwfsm_nxt_state_i_1_1_.INIT = 8'h07; + LUT3_L plm_dfm_deframe1_qwfsm_nxt_state_i_1_1_ ( + .I0(N_3543), + .I1(plm_dfm_deframe1_qwfsm_reg_state_0__59), + .I2(plm_dfm_deframe1_qwfsm_reg_state_6__61), + .LO(plm_dfm_deframe1_qwfsm_nxt_state_i_1[1]) + ); + FDC plm_dfm_deframe1_qwfsm_reg_phi1 ( + .C(mgt_clk), + .D(plm_dfm_deframe1_qwfsm_reg_phi0_721), + .Q(plm_dfm_deframe1_qwfsm_reg_phi1_724), + .CLR(plm_rst) + ); + FDC plm_dfm_deframe1_qwfsm_reg_phi0 ( + .C(mgt_clk), + .D(plm_phy_cke_0_402), + .Q(plm_dfm_deframe1_qwfsm_reg_phi0_721), + .CLR(plm_rst) + ); + FDCE plm_dfm_deframe1_qwfsm_reg_state_7_ ( + .CE(plm_dfm_deframe1_qwfsm_N_9986_i), + .C(mgt_clk), + .D(plm_dfm_deframe1_qwfsm_nxt_state[7]), + .Q(plm_dfm_deframe1_qwfsm_reg_state_7__60), + .CLR(plm_rst) + ); + FDCE plm_dfm_deframe1_qwfsm_reg_state_6_ ( + .CE(plm_dfm_deframe1_qwfsm_N_9986_i), + .C(mgt_clk), + .D(plm_dfm_deframe1_qwfsm_nxt_state[6]), + .Q(plm_dfm_deframe1_qwfsm_reg_state_6__61), + .CLR(plm_rst) + ); + FDCE plm_dfm_deframe1_qwfsm_reg_state_5_ ( + .CE(plm_dfm_deframe1_qwfsm_N_9986_i), + .C(mgt_clk), + .D(plm_dfm_deframe1_qwfsm_nxt_state[5]), + .Q(plm_dfm_deframe1_qwfsm_reg_state[5]), + .CLR(plm_rst) + ); + FDCE plm_dfm_deframe1_qwfsm_reg_state_4_ ( + .CE(plm_dfm_deframe1_qwfsm_N_9986_i), + .C(mgt_clk), + .D(plm_dfm_deframe1_qwfsm_nxt_state[4]), + .Q(plm_dfm_deframe1_qwfsm_reg_state[4]), + .CLR(plm_rst) + ); + FDCE plm_dfm_deframe1_qwfsm_reg_state_3_ ( + .CE(plm_dfm_deframe1_qwfsm_N_9986_i), + .C(mgt_clk), + .D(plm_dfm_deframe1_qwfsm_nxt_state_6_sqmuxa_1_722), + .Q(plm_dfm_deframe1_qwfsm_reg_state[3]), + .CLR(plm_rst) + ); + FDCE plm_dfm_deframe1_qwfsm_reg_state_2_ ( + .CE(plm_dfm_deframe1_qwfsm_N_9986_i), + .C(mgt_clk), + .D(plm_dfm_deframe1_qwfsm_nxt_state_6_sqmuxa_723), + .Q(plm_dfm_deframe1_qwfsm_reg_state[2]), + .CLR(plm_rst) + ); + FDCE plm_dfm_deframe1_qwfsm_reg_state_1_ ( + .CE(plm_dfm_deframe1_qwfsm_N_9986_i), + .C(mgt_clk), + .D(plm_dfm_deframe1_qwfsm_nxt_state_5075[1]), + .Q(plm_dfm_deframe1_qwfsm_reg_state_1__58), + .CLR(plm_rst) + ); + FDPE plm_dfm_deframe1_qwfsm_reg_state_0_ ( + .PRE(plm_rst), + .CE(plm_dfm_deframe1_qwfsm_N_9986_i), + .C(mgt_clk), + .D(plm_dfm_deframe1_qwfsm_nxt_state_5075[0]), + .Q(plm_dfm_deframe1_qwfsm_reg_state_0__59) + ); + FDCE plm_dfm_deframe1_qwfsm_reg_by1_prel_sdpstp_1_ ( + .CE(plm_dfm_deframe1_qwfsm_reg_phi1_724), + .C(mgt_clk), + .D(plm_dfm_deframe1_qwfsm_reg_by1_preh_sdpstp_6[1]), + .Q(plm_dfm_prel_sdpstp[1]), + .CLR(plm_rst) + ); + FDCE plm_dfm_deframe1_qwfsm_reg_by1_prel_sdpstp_0_ ( + .CE(plm_dfm_deframe1_qwfsm_reg_phi1_724), + .C(mgt_clk), + .D(plm_dfm_deframe1_qwfsm_reg_by1_preh_sdpstp_6[0]), + .Q(plm_dfm_prel_sdpstp[0]), + .CLR(plm_rst) + ); + FDPE plm_dfm_deframe1_qwfsm_reg_by1_preh_sdpstp_1_ ( + .PRE(plm_rst), + .CE(plm_phy_cke_0_402), + .C(mgt_clk), + .D(plm_dfm_deframe1_qwfsm_reg_by1_preh_sdpstp_6[1]), + .Q(plm_dfm_preh_sdpstp[1]) + ); + FDCE plm_dfm_deframe1_qwfsm_reg_by1_preh_sdpstp_0_ ( + .CE(plm_phy_cke_0_402), + .C(mgt_clk), + .D(plm_dfm_deframe1_qwfsm_reg_by1_preh_sdpstp_6[0]), + .Q(plm_dfm_preh_sdpstp[0]), + .CLR(plm_rst) + ); + FDPE plm_dfm_deframe1_qwfsm_reg_by1_preh_out_31_ ( + .PRE(plm_rst), + .CE(plm_phy_cke_0_402), + .C(mgt_clk), + .D(plm_dfm_deframe1_qwfsm_reg_by1_preh_out_6[31]), + .Q(plm_dfm_by1_preh_out[31]) + ); + FDPE plm_dfm_deframe1_qwfsm_reg_by1_preh_out_30_ ( + .PRE(plm_rst), + .CE(plm_phy_cke_0_402), + .C(mgt_clk), + .D(plm_dfm_deframe1_qwfsm_reg_by1_preh_out_6[30]), + .Q(plm_dfm_by1_preh_out[30]) + ); + FDPE plm_dfm_deframe1_qwfsm_reg_by1_preh_out_29_ ( + .PRE(plm_rst), + .CE(plm_phy_cke_0_402), + .C(mgt_clk), + .D(plm_dfm_deframe1_qwfsm_reg_by1_preh_out_6[29]), + .Q(plm_dfm_by1_preh_out[29]) + ); + FDPE plm_dfm_deframe1_qwfsm_reg_by1_preh_out_28_ ( + .PRE(plm_rst), + .CE(plm_phy_cke_0_402), + .C(mgt_clk), + .D(plm_dfm_deframe1_qwfsm_reg_by1_preh_out_6[28]), + .Q(plm_dfm_by1_preh_out[28]) + ); + FDPE plm_dfm_deframe1_qwfsm_reg_by1_preh_out_27_ ( + .PRE(plm_rst), + .CE(plm_phy_cke_0_402), + .C(mgt_clk), + .D(plm_dfm_deframe1_qwfsm_reg_by1_preh_out_6[27]), + .Q(plm_dfm_by1_preh_out[27]) + ); + FDPE plm_dfm_deframe1_qwfsm_reg_by1_preh_out_26_ ( + .PRE(plm_rst), + .CE(plm_phy_cke_0_402), + .C(mgt_clk), + .D(plm_dfm_deframe1_qwfsm_reg_by1_preh_out_6[26]), + .Q(plm_dfm_by1_preh_out[26]) + ); + FDPE plm_dfm_deframe1_qwfsm_reg_by1_preh_out_25_ ( + .PRE(plm_rst), + .CE(plm_phy_cke_0_402), + .C(mgt_clk), + .D(plm_dfm_deframe1_qwfsm_reg_by1_preh_out_6[25]), + .Q(plm_dfm_by1_preh_out[25]) + ); + FDPE plm_dfm_deframe1_qwfsm_reg_by1_preh_out_24_ ( + .PRE(plm_rst), + .CE(plm_phy_cke_0_402), + .C(mgt_clk), + .D(plm_dfm_deframe1_qwfsm_reg_by1_preh_out_6[24]), + .Q(plm_dfm_by1_preh_out[24]) + ); + FDCE plm_dfm_deframe1_qwfsm_reg_by1_preh_out_23_ ( + .CE(plm_phy_cke_0_402), + .C(mgt_clk), + .D(plm_dfm_deframe1_qwfsm_reg_by1_preh_out_6[23]), + .Q(plm_dfm_by1_preh_out[23]), + .CLR(plm_rst) + ); + FDCE plm_dfm_deframe1_qwfsm_reg_by1_preh_out_22_ ( + .CE(plm_phy_cke_0_402), + .C(mgt_clk), + .D(plm_dfm_deframe1_qwfsm_reg_by1_preh_out_6[22]), + .Q(plm_dfm_by1_preh_out[22]), + .CLR(plm_rst) + ); + FDCE plm_dfm_deframe1_qwfsm_reg_by1_preh_out_21_ ( + .CE(plm_phy_cke_0_402), + .C(mgt_clk), + .D(plm_dfm_deframe1_qwfsm_reg_by1_preh_out_6[21]), + .Q(plm_dfm_by1_preh_out[21]), + .CLR(plm_rst) + ); + FDCE plm_dfm_deframe1_qwfsm_reg_by1_preh_out_20_ ( + .CE(plm_phy_cke_0_402), + .C(mgt_clk), + .D(plm_dfm_deframe1_qwfsm_reg_by1_preh_out_6[20]), + .Q(plm_dfm_by1_preh_out[20]), + .CLR(plm_rst) + ); + FDCE plm_dfm_deframe1_qwfsm_reg_by1_preh_out_19_ ( + .CE(plm_phy_cke_0_402), + .C(mgt_clk), + .D(plm_dfm_deframe1_qwfsm_reg_by1_preh_out_6[19]), + .Q(plm_dfm_by1_preh_out[19]), + .CLR(plm_rst) + ); + FDCE plm_dfm_deframe1_qwfsm_reg_by1_preh_out_18_ ( + .CE(plm_phy_cke_0_402), + .C(mgt_clk), + .D(plm_dfm_deframe1_qwfsm_reg_by1_preh_out_6[18]), + .Q(plm_dfm_by1_preh_out[18]), + .CLR(plm_rst) + ); + FDCE plm_dfm_deframe1_qwfsm_reg_by1_preh_out_17_ ( + .CE(plm_phy_cke_0_402), + .C(mgt_clk), + .D(plm_dfm_deframe1_qwfsm_reg_by1_preh_out_6[17]), + .Q(plm_dfm_by1_preh_out[17]), + .CLR(plm_rst) + ); + FDCE plm_dfm_deframe1_qwfsm_reg_by1_preh_out_16_ ( + .CE(plm_phy_cke_0_402), + .C(mgt_clk), + .D(plm_dfm_deframe1_qwfsm_reg_by1_preh_out_6[16]), + .Q(plm_dfm_by1_preh_out[16]), + .CLR(plm_rst) + ); + FDCE plm_dfm_deframe1_qwfsm_reg_by1_preh_out_15_ ( + .CE(plm_phy_cke_0_402), + .C(mgt_clk), + .D(plm_dfm_deframe1_qwfsm_reg_by1_preh_out_6[15]), + .Q(plm_dfm_by1_preh_out[15]), + .CLR(plm_rst) + ); + FDCE plm_dfm_deframe1_qwfsm_reg_by1_preh_out_14_ ( + .CE(plm_phy_cke_0_402), + .C(mgt_clk), + .D(plm_dfm_deframe1_qwfsm_reg_by1_preh_out_6[14]), + .Q(plm_dfm_by1_preh_out[14]), + .CLR(plm_rst) + ); + FDCE plm_dfm_deframe1_qwfsm_reg_by1_preh_out_13_ ( + .CE(plm_phy_cke_0_402), + .C(mgt_clk), + .D(plm_dfm_deframe1_qwfsm_reg_by1_preh_out_6[13]), + .Q(plm_dfm_by1_preh_out[13]), + .CLR(plm_rst) + ); + FDCE plm_dfm_deframe1_qwfsm_reg_by1_preh_out_12_ ( + .CE(plm_phy_cke_0_402), + .C(mgt_clk), + .D(plm_dfm_deframe1_qwfsm_reg_by1_preh_out_6[12]), + .Q(plm_dfm_by1_preh_out[12]), + .CLR(plm_rst) + ); + FDCE plm_dfm_deframe1_qwfsm_reg_by1_preh_out_11_ ( + .CE(plm_phy_cke_0_402), + .C(mgt_clk), + .D(plm_dfm_deframe1_qwfsm_reg_by1_preh_out_6[11]), + .Q(plm_dfm_by1_preh_out[11]), + .CLR(plm_rst) + ); + FDCE plm_dfm_deframe1_qwfsm_reg_by1_preh_out_10_ ( + .CE(plm_phy_cke_0_402), + .C(mgt_clk), + .D(plm_dfm_deframe1_qwfsm_reg_by1_preh_out_6[10]), + .Q(plm_dfm_by1_preh_out[10]), + .CLR(plm_rst) + ); + FDCE plm_dfm_deframe1_qwfsm_reg_by1_preh_out_9_ ( + .CE(plm_phy_cke_0_402), + .C(mgt_clk), + .D(plm_dfm_deframe1_qwfsm_reg_by1_preh_out_6[9]), + .Q(plm_dfm_by1_preh_out[9]), + .CLR(plm_rst) + ); + FDCE plm_dfm_deframe1_qwfsm_reg_by1_preh_out_8_ ( + .CE(plm_phy_cke_0_402), + .C(mgt_clk), + .D(plm_dfm_deframe1_qwfsm_reg_by1_preh_out_6[8]), + .Q(plm_dfm_by1_preh_out[8]), + .CLR(plm_rst) + ); + FDCE plm_dfm_deframe1_qwfsm_reg_by1_preh_out_7_ ( + .CE(plm_phy_cke_0_402), + .C(mgt_clk), + .D(plm_dfm_deframe1_qwfsm_N_8792_i), + .Q(plm_dfm_by1_preh_out[7]), + .CLR(plm_rst) + ); + FDCE plm_dfm_deframe1_qwfsm_reg_by1_preh_out_6_ ( + .CE(plm_phy_cke_0_402), + .C(mgt_clk), + .D(plm_dfm_deframe1_qwfsm_N_8793_i), + .Q(plm_dfm_by1_preh_out[6]), + .CLR(plm_rst) + ); + FDCE plm_dfm_deframe1_qwfsm_reg_by1_preh_out_5_ ( + .CE(plm_phy_cke_0_402), + .C(mgt_clk), + .D(plm_dfm_deframe1_qwfsm_N_8794_i), + .Q(plm_dfm_by1_preh_out[5]), + .CLR(plm_rst) + ); + FDCE plm_dfm_deframe1_qwfsm_reg_by1_preh_out_4_ ( + .CE(plm_phy_cke_0_402), + .C(mgt_clk), + .D(plm_dfm_deframe1_qwfsm_N_8795_i), + .Q(plm_dfm_by1_preh_out[4]), + .CLR(plm_rst) + ); + FDCE plm_dfm_deframe1_qwfsm_reg_by1_preh_out_3_ ( + .CE(plm_phy_cke_0_402), + .C(mgt_clk), + .D(plm_dfm_deframe1_qwfsm_N_8796_i), + .Q(plm_dfm_by1_preh_out[3]), + .CLR(plm_rst) + ); + FDCE plm_dfm_deframe1_qwfsm_reg_by1_preh_out_2_ ( + .CE(plm_phy_cke_0_402), + .C(mgt_clk), + .D(plm_dfm_deframe1_qwfsm_N_8797_i), + .Q(plm_dfm_by1_preh_out[2]), + .CLR(plm_rst) + ); + FDCE plm_dfm_deframe1_qwfsm_reg_by1_preh_out_1_ ( + .CE(plm_phy_cke_0_402), + .C(mgt_clk), + .D(plm_dfm_deframe1_qwfsm_N_8798_i), + .Q(plm_dfm_by1_preh_out[1]), + .CLR(plm_rst) + ); + FDCE plm_dfm_deframe1_qwfsm_reg_by1_preh_out_0_ ( + .CE(plm_phy_cke_0_402), + .C(mgt_clk), + .D(plm_dfm_deframe1_qwfsm_N_8799_i), + .Q(plm_dfm_by1_preh_out[0]), + .CLR(plm_rst) + ); + FDCE plm_dfm_deframe1_qwfsm_reg_by1_prel_out_31_ ( + .CE(plm_dfm_deframe1_qwfsm_reg_phi1_724), + .C(mgt_clk), + .D(plm_dfm_deframe1_qwfsm_reg_by1_preh_out_6[31]), + .Q(plm_dfm_by1_prel_out[31]), + .CLR(plm_rst) + ); + FDCE plm_dfm_deframe1_qwfsm_reg_by1_prel_out_30_ ( + .CE(plm_dfm_deframe1_qwfsm_reg_phi1_724), + .C(mgt_clk), + .D(plm_dfm_deframe1_qwfsm_reg_by1_preh_out_6[30]), + .Q(plm_dfm_by1_prel_out[30]), + .CLR(plm_rst) + ); + FDCE plm_dfm_deframe1_qwfsm_reg_by1_prel_out_29_ ( + .CE(plm_dfm_deframe1_qwfsm_reg_phi1_724), + .C(mgt_clk), + .D(plm_dfm_deframe1_qwfsm_reg_by1_preh_out_6[29]), + .Q(plm_dfm_by1_prel_out[29]), + .CLR(plm_rst) + ); + FDCE plm_dfm_deframe1_qwfsm_reg_by1_prel_out_28_ ( + .CE(plm_dfm_deframe1_qwfsm_reg_phi1_724), + .C(mgt_clk), + .D(plm_dfm_deframe1_qwfsm_reg_by1_preh_out_6[28]), + .Q(plm_dfm_by1_prel_out[28]), + .CLR(plm_rst) + ); + FDCE plm_dfm_deframe1_qwfsm_reg_by1_prel_out_27_ ( + .CE(plm_dfm_deframe1_qwfsm_reg_phi1_724), + .C(mgt_clk), + .D(plm_dfm_deframe1_qwfsm_reg_by1_preh_out_6[27]), + .Q(plm_dfm_by1_prel_out[27]), + .CLR(plm_rst) + ); + FDCE plm_dfm_deframe1_qwfsm_reg_by1_prel_out_26_ ( + .CE(plm_dfm_deframe1_qwfsm_reg_phi1_724), + .C(mgt_clk), + .D(plm_dfm_deframe1_qwfsm_reg_by1_preh_out_6[26]), + .Q(plm_dfm_by1_prel_out[26]), + .CLR(plm_rst) + ); + FDCE plm_dfm_deframe1_qwfsm_reg_by1_prel_out_25_ ( + .CE(plm_dfm_deframe1_qwfsm_reg_phi1_724), + .C(mgt_clk), + .D(plm_dfm_deframe1_qwfsm_reg_by1_preh_out_6[25]), + .Q(plm_dfm_by1_prel_out[25]), + .CLR(plm_rst) + ); + FDCE plm_dfm_deframe1_qwfsm_reg_by1_prel_out_24_ ( + .CE(plm_dfm_deframe1_qwfsm_reg_phi1_724), + .C(mgt_clk), + .D(plm_dfm_deframe1_qwfsm_reg_by1_preh_out_6[24]), + .Q(plm_dfm_by1_prel_out[24]), + .CLR(plm_rst) + ); + FDCE plm_dfm_deframe1_qwfsm_reg_by1_prel_out_23_ ( + .CE(plm_dfm_deframe1_qwfsm_reg_phi1_724), + .C(mgt_clk), + .D(plm_dfm_deframe1_qwfsm_reg_by1_preh_out_6[23]), + .Q(plm_dfm_by1_prel_out[23]), + .CLR(plm_rst) + ); + FDCE plm_dfm_deframe1_qwfsm_reg_by1_prel_out_22_ ( + .CE(plm_dfm_deframe1_qwfsm_reg_phi1_724), + .C(mgt_clk), + .D(plm_dfm_deframe1_qwfsm_reg_by1_preh_out_6[22]), + .Q(plm_dfm_by1_prel_out[22]), + .CLR(plm_rst) + ); + FDCE plm_dfm_deframe1_qwfsm_reg_by1_prel_out_21_ ( + .CE(plm_dfm_deframe1_qwfsm_reg_phi1_724), + .C(mgt_clk), + .D(plm_dfm_deframe1_qwfsm_reg_by1_preh_out_6[21]), + .Q(plm_dfm_by1_prel_out[21]), + .CLR(plm_rst) + ); + FDCE plm_dfm_deframe1_qwfsm_reg_by1_prel_out_20_ ( + .CE(plm_dfm_deframe1_qwfsm_reg_phi1_724), + .C(mgt_clk), + .D(plm_dfm_deframe1_qwfsm_reg_by1_preh_out_6[20]), + .Q(plm_dfm_by1_prel_out[20]), + .CLR(plm_rst) + ); + FDCE plm_dfm_deframe1_qwfsm_reg_by1_prel_out_19_ ( + .CE(plm_dfm_deframe1_qwfsm_reg_phi1_724), + .C(mgt_clk), + .D(plm_dfm_deframe1_qwfsm_reg_by1_preh_out_6[19]), + .Q(plm_dfm_by1_prel_out[19]), + .CLR(plm_rst) + ); + FDCE plm_dfm_deframe1_qwfsm_reg_by1_prel_out_18_ ( + .CE(plm_dfm_deframe1_qwfsm_reg_phi1_724), + .C(mgt_clk), + .D(plm_dfm_deframe1_qwfsm_reg_by1_preh_out_6[18]), + .Q(plm_dfm_by1_prel_out[18]), + .CLR(plm_rst) + ); + FDCE plm_dfm_deframe1_qwfsm_reg_by1_prel_out_17_ ( + .CE(plm_dfm_deframe1_qwfsm_reg_phi1_724), + .C(mgt_clk), + .D(plm_dfm_deframe1_qwfsm_reg_by1_preh_out_6[17]), + .Q(plm_dfm_by1_prel_out[17]), + .CLR(plm_rst) + ); + FDCE plm_dfm_deframe1_qwfsm_reg_by1_prel_out_16_ ( + .CE(plm_dfm_deframe1_qwfsm_reg_phi1_724), + .C(mgt_clk), + .D(plm_dfm_deframe1_qwfsm_reg_by1_preh_out_6[16]), + .Q(plm_dfm_by1_prel_out[16]), + .CLR(plm_rst) + ); + FDCE plm_dfm_deframe1_qwfsm_reg_by1_prel_out_15_ ( + .CE(plm_dfm_deframe1_qwfsm_reg_phi1_724), + .C(mgt_clk), + .D(plm_dfm_deframe1_qwfsm_reg_by1_preh_out_6[15]), + .Q(plm_dfm_by1_prel_out[15]), + .CLR(plm_rst) + ); + FDCE plm_dfm_deframe1_qwfsm_reg_by1_prel_out_14_ ( + .CE(plm_dfm_deframe1_qwfsm_reg_phi1_724), + .C(mgt_clk), + .D(plm_dfm_deframe1_qwfsm_reg_by1_preh_out_6[14]), + .Q(plm_dfm_by1_prel_out[14]), + .CLR(plm_rst) + ); + FDCE plm_dfm_deframe1_qwfsm_reg_by1_prel_out_13_ ( + .CE(plm_dfm_deframe1_qwfsm_reg_phi1_724), + .C(mgt_clk), + .D(plm_dfm_deframe1_qwfsm_reg_by1_preh_out_6[13]), + .Q(plm_dfm_by1_prel_out[13]), + .CLR(plm_rst) + ); + FDCE plm_dfm_deframe1_qwfsm_reg_by1_prel_out_12_ ( + .CE(plm_dfm_deframe1_qwfsm_reg_phi1_724), + .C(mgt_clk), + .D(plm_dfm_deframe1_qwfsm_reg_by1_preh_out_6[12]), + .Q(plm_dfm_by1_prel_out[12]), + .CLR(plm_rst) + ); + FDCE plm_dfm_deframe1_qwfsm_reg_by1_prel_out_11_ ( + .CE(plm_dfm_deframe1_qwfsm_reg_phi1_724), + .C(mgt_clk), + .D(plm_dfm_deframe1_qwfsm_reg_by1_preh_out_6[11]), + .Q(plm_dfm_by1_prel_out[11]), + .CLR(plm_rst) + ); + FDCE plm_dfm_deframe1_qwfsm_reg_by1_prel_out_10_ ( + .CE(plm_dfm_deframe1_qwfsm_reg_phi1_724), + .C(mgt_clk), + .D(plm_dfm_deframe1_qwfsm_reg_by1_preh_out_6[10]), + .Q(plm_dfm_by1_prel_out[10]), + .CLR(plm_rst) + ); + FDCE plm_dfm_deframe1_qwfsm_reg_by1_prel_out_9_ ( + .CE(plm_dfm_deframe1_qwfsm_reg_phi1_724), + .C(mgt_clk), + .D(plm_dfm_deframe1_qwfsm_reg_by1_preh_out_6[9]), + .Q(plm_dfm_by1_prel_out[9]), + .CLR(plm_rst) + ); + FDCE plm_dfm_deframe1_qwfsm_reg_by1_prel_out_8_ ( + .CE(plm_dfm_deframe1_qwfsm_reg_phi1_724), + .C(mgt_clk), + .D(plm_dfm_deframe1_qwfsm_reg_by1_preh_out_6[8]), + .Q(plm_dfm_by1_prel_out[8]), + .CLR(plm_rst) + ); + FDPE plm_dfm_deframe1_qwfsm_reg_by1_prel_out_7_ ( + .PRE(plm_rst), + .CE(plm_dfm_deframe1_qwfsm_reg_phi1_724), + .C(mgt_clk), + .D(plm_dfm_deframe1_qwfsm_N_8792_i), + .Q(plm_dfm_by1_prel_out[7]) + ); + FDPE plm_dfm_deframe1_qwfsm_reg_by1_prel_out_6_ ( + .PRE(plm_rst), + .CE(plm_dfm_deframe1_qwfsm_reg_phi1_724), + .C(mgt_clk), + .D(plm_dfm_deframe1_qwfsm_N_8793_i), + .Q(plm_dfm_by1_prel_out[6]) + ); + FDPE plm_dfm_deframe1_qwfsm_reg_by1_prel_out_5_ ( + .PRE(plm_rst), + .CE(plm_dfm_deframe1_qwfsm_reg_phi1_724), + .C(mgt_clk), + .D(plm_dfm_deframe1_qwfsm_N_8794_i), + .Q(plm_dfm_by1_prel_out[5]) + ); + FDPE plm_dfm_deframe1_qwfsm_reg_by1_prel_out_4_ ( + .PRE(plm_rst), + .CE(plm_dfm_deframe1_qwfsm_reg_phi1_724), + .C(mgt_clk), + .D(plm_dfm_deframe1_qwfsm_N_8795_i), + .Q(plm_dfm_by1_prel_out[4]) + ); + FDPE plm_dfm_deframe1_qwfsm_reg_by1_prel_out_3_ ( + .PRE(plm_rst), + .CE(plm_dfm_deframe1_qwfsm_reg_phi1_724), + .C(mgt_clk), + .D(plm_dfm_deframe1_qwfsm_N_8796_i), + .Q(plm_dfm_by1_prel_out[3]) + ); + FDPE plm_dfm_deframe1_qwfsm_reg_by1_prel_out_2_ ( + .PRE(plm_rst), + .CE(plm_dfm_deframe1_qwfsm_reg_phi1_724), + .C(mgt_clk), + .D(plm_dfm_deframe1_qwfsm_N_8797_i), + .Q(plm_dfm_by1_prel_out[2]) + ); + FDPE plm_dfm_deframe1_qwfsm_reg_by1_prel_out_1_ ( + .PRE(plm_rst), + .CE(plm_dfm_deframe1_qwfsm_reg_phi1_724), + .C(mgt_clk), + .D(plm_dfm_deframe1_qwfsm_N_8798_i), + .Q(plm_dfm_by1_prel_out[1]) + ); + FDPE plm_dfm_deframe1_qwfsm_reg_by1_prel_out_0_ ( + .PRE(plm_rst), + .CE(plm_dfm_deframe1_qwfsm_reg_phi1_724), + .C(mgt_clk), + .D(plm_dfm_deframe1_qwfsm_N_8799_i), + .Q(plm_dfm_by1_prel_out[0]) + ); + FDCE plm_dfm_deframe1_qwfsm_reg_by1_preh_edbedg_1_ ( + .CE(plm_phy_cke_0_402), + .C(mgt_clk), + .D(plm_dfm_deframe1_qwfsm_reg_by1_preh_edbedg_8[1]), + .Q(plm_dfm_preh_edbedg[1]), + .CLR(plm_rst) + ); + FDCE plm_dfm_deframe1_qwfsm_reg_by1_preh_edbedg_0_ ( + .CE(plm_phy_cke_0_402), + .C(mgt_clk), + .D(plm_dfm_deframe1_qwfsm_reg_by1_preh_edbedg_8[0]), + .Q(plm_dfm_preh_edbedg[0]), + .CLR(plm_rst) + ); + FDCE plm_dfm_deframe1_qwfsm_reg_by1_prel_edbedg_1_ ( + .CE(plm_dfm_deframe1_qwfsm_reg_phi1_724), + .C(mgt_clk), + .D(plm_dfm_deframe1_qwfsm_reg_by1_preh_edbedg_8[1]), + .Q(plm_dfm_prel_edbedg[1]), + .CLR(plm_rst) + ); + FDPE plm_dfm_deframe1_qwfsm_reg_by1_prel_edbedg_0_ ( + .PRE(plm_rst), + .CE(plm_dfm_deframe1_qwfsm_reg_phi1_724), + .C(mgt_clk), + .D(plm_dfm_deframe1_qwfsm_reg_by1_preh_edbedg_8[0]), + .Q(plm_dfm_prel_edbedg[0]) + ); + defparam plm_dfm_deframe1_qwfsm_nxt_state_i_0_.INIT = 16'hFFF1; + LUT4_L plm_dfm_deframe1_qwfsm_nxt_state_i_0_ ( + .I0(plm_dfm_deframe1_qwfsm_nxt_state_1[7]), + .I1(plm_dfm_deframe1_qwfsm_nxt_state_i_1[0]), + .I2(plm_dfm_deframe1_qwfsm_reg_state[3]), + .I3(plm_dfm_deframe1_qwfsm_reg_state[5]), + .LO(plm_dfm_deframe1_qwfsm_nxt_state_5075[0]) + ); + defparam plm_dfm_deframe1_qwfsm_nxt_state_i_1_.INIT = 16'hFFF1; + LUT4_L plm_dfm_deframe1_qwfsm_nxt_state_i_1_ ( + .I0(plm_dfm_deframe1_qwfsm_nxt_state_1[7]), + .I1(plm_dfm_deframe1_qwfsm_nxt_state_i_1[1]), + .I2(plm_dfm_deframe1_qwfsm_reg_state[2]), + .I3(plm_dfm_deframe1_qwfsm_reg_state[4]), + .LO(plm_dfm_deframe1_qwfsm_nxt_state_5075[1]) + ); + VCC plm_sym_VCC ( + .P(plm_sym_VCC_734) + ); + GND plm_sym_GND ( + .G(plm_sym_GND_737) + ); + MUXCY_L plm_sym_un6_reg_count_cry_0 ( + .CI(plm_sym_GND_737), + .DI(plm_sym_VCC_734), + .LO(plm_sym_un6_reg_count_cry_0_725), + .S(N_57388_i_17) + ); + MUXCY_L plm_sym_un6_reg_count_cry_1 ( + .CI(plm_sym_un6_reg_count_cry_0_725), + .DI(plm_sym_VCC_734), + .LO(plm_sym_un6_reg_count_cry_1_726), + .S(plm_sym_un6_reg_count_s_1_sf_785) + ); + XORCY plm_sym_un6_reg_count_s_1 ( + .CI(plm_sym_un6_reg_count_cry_0_725), + .LI(plm_sym_un6_reg_count_s_1_sf_785), + .O(plm_sym_un6_reg_count_s_1_747) + ); + MUXCY_L plm_sym_un6_reg_count_cry_2 ( + .CI(plm_sym_un6_reg_count_cry_1_726), + .DI(plm_sym_VCC_734), + .LO(plm_sym_un6_reg_count_cry_2_727), + .S(plm_sym_un6_reg_count_s_2_sf_784) + ); + XORCY plm_sym_un6_reg_count_s_2 ( + .CI(plm_sym_un6_reg_count_cry_1_726), + .LI(plm_sym_un6_reg_count_s_2_sf_784), + .O(plm_sym_un6_reg_count_s_2_746) + ); + MUXCY_L plm_sym_un6_reg_count_cry_3 ( + .CI(plm_sym_un6_reg_count_cry_2_727), + .DI(plm_sym_VCC_734), + .LO(plm_sym_un6_reg_count_cry_3_728), + .S(plm_sym_un6_reg_count_s_3_sf_783) + ); + XORCY plm_sym_un6_reg_count_s_3 ( + .CI(plm_sym_un6_reg_count_cry_2_727), + .LI(plm_sym_un6_reg_count_s_3_sf_783), + .O(plm_sym_un6_reg_count_s_3_745) + ); + MUXCY_L plm_sym_un6_reg_count_cry_4 ( + .CI(plm_sym_un6_reg_count_cry_3_728), + .DI(plm_sym_VCC_734), + .LO(plm_sym_un6_reg_count_cry_4_729), + .S(plm_sym_un6_reg_count_s_4_sf_782) + ); + XORCY plm_sym_un6_reg_count_s_4 ( + .CI(plm_sym_un6_reg_count_cry_3_728), + .LI(plm_sym_un6_reg_count_s_4_sf_782), + .O(plm_sym_un6_reg_count_s_4_759) + ); + MUXCY_L plm_sym_un6_reg_count_cry_5 ( + .CI(plm_sym_un6_reg_count_cry_4_729), + .DI(plm_sym_VCC_734), + .LO(plm_sym_un6_reg_count_cry_5_730), + .S(plm_sym_un6_reg_count_s_5_sf_781) + ); + XORCY plm_sym_un6_reg_count_s_5 ( + .CI(plm_sym_un6_reg_count_cry_4_729), + .LI(plm_sym_un6_reg_count_s_5_sf_781), + .O(plm_sym_un6_reg_count_s_5_758) + ); + MUXCY_L plm_sym_un6_reg_count_cry_6 ( + .CI(plm_sym_un6_reg_count_cry_5_730), + .DI(plm_sym_VCC_734), + .LO(plm_sym_un6_reg_count_cry_6_731), + .S(plm_sym_un6_reg_count_s_6_sf_780) + ); + XORCY plm_sym_un6_reg_count_s_6 ( + .CI(plm_sym_un6_reg_count_cry_5_730), + .LI(plm_sym_un6_reg_count_s_6_sf_780), + .O(plm_sym_un6_reg_count_s_6_757) + ); + MUXCY_L plm_sym_un6_reg_count_cry_7 ( + .CI(plm_sym_un6_reg_count_cry_6_731), + .DI(plm_sym_VCC_734), + .LO(plm_sym_un6_reg_count_cry_7_732), + .S(plm_sym_un6_reg_count_s_7_sf_779) + ); + XORCY plm_sym_un6_reg_count_s_7 ( + .CI(plm_sym_un6_reg_count_cry_6_731), + .LI(plm_sym_un6_reg_count_s_7_sf_779), + .O(plm_sym_un6_reg_count_s_7_756) + ); + MUXCY_L plm_sym_un6_reg_count_cry_8 ( + .CI(plm_sym_un6_reg_count_cry_7_732), + .DI(plm_sym_VCC_734), + .LO(plm_sym_un6_reg_count_cry_8_733), + .S(plm_sym_un6_reg_count_s_8_sf_755) + ); + XORCY plm_sym_un6_reg_count_s_8 ( + .CI(plm_sym_un6_reg_count_cry_7_732), + .LI(plm_sym_un6_reg_count_s_8_sf_755), + .O(plm_sym_un6_reg_count_s_8_773) + ); + MUXCY_L plm_sym_un6_reg_count_cry_9 ( + .CI(plm_sym_un6_reg_count_cry_8_733), + .DI(plm_sym_VCC_734), + .LO(plm_sym_un6_reg_count_cry_9_735), + .S(plm_sym_un6_reg_count_s_9_sf_754) + ); + XORCY plm_sym_un6_reg_count_s_9 ( + .CI(plm_sym_un6_reg_count_cry_8_733), + .LI(plm_sym_un6_reg_count_s_9_sf_754), + .O(plm_sym_un6_reg_count_s_9_772) + ); + MUXCY_L plm_sym_un6_reg_count_cry_10 ( + .CI(plm_sym_un6_reg_count_cry_9_735), + .DI(plm_sym_VCC_734), + .LO(plm_sym_un6_reg_count_cry_10_736), + .S(plm_sym_un6_reg_count_s_10_sf_778) + ); + XORCY plm_sym_un6_reg_count_s_10 ( + .CI(plm_sym_un6_reg_count_cry_9_735), + .LI(plm_sym_un6_reg_count_s_10_sf_778), + .O(plm_sym_un6_reg_count_s_10_753) + ); + XORCY plm_sym_un6_reg_count_s_11 ( + .CI(plm_sym_un6_reg_count_cry_10_736), + .LI(plm_sym_un6_reg_count_s_11_sf_741), + .O(plm_sym_un6_reg_count_s_11_752) + ); + MUXCY_L plm_sym_un1_reg_outstanding_ccs_1_cry_0 ( + .CI(plm_sym_GND_737), + .DI(plm_sym_reg_outstanding_ccs[0]), + .LO(plm_sym_un1_reg_outstanding_ccs_1_cry_0_738), + .S(plm_sym_un1_reg_outstanding_ccs_1_axb_0_769) + ); + MUXCY_L plm_sym_un1_reg_outstanding_ccs_1_cry_1 ( + .CI(plm_sym_un1_reg_outstanding_ccs_1_cry_0_738), + .DI(plm_sym_reg_outstanding_ccs[1]), + .LO(plm_sym_un1_reg_outstanding_ccs_1_cry_1_739), + .S(plm_sym_un1_reg_outstanding_ccs_1_axb_1_750) + ); + XORCY plm_sym_un1_reg_outstanding_ccs_1_s_1 ( + .CI(plm_sym_un1_reg_outstanding_ccs_1_cry_0_738), + .LI(plm_sym_un1_reg_outstanding_ccs_1_axb_1_750), + .O(plm_sym_un1_reg_outstanding_ccs_1_s_1_768) + ); + MUXCY_L plm_sym_un1_reg_outstanding_ccs_1_cry_2 ( + .CI(plm_sym_un1_reg_outstanding_ccs_1_cry_1_739), + .DI(plm_sym_reg_outstanding_ccs[2]), + .LO(plm_sym_un1_reg_outstanding_ccs_1_cry_2_740), + .S(plm_sym_un1_reg_outstanding_ccs_1_axb_2_749) + ); + XORCY plm_sym_un1_reg_outstanding_ccs_1_s_2 ( + .CI(plm_sym_un1_reg_outstanding_ccs_1_cry_1_739), + .LI(plm_sym_un1_reg_outstanding_ccs_1_axb_2_749), + .O(plm_sym_un1_reg_outstanding_ccs_1_s_2_767) + ); + XORCY plm_sym_un1_reg_outstanding_ccs_1_s_3 ( + .CI(plm_sym_un1_reg_outstanding_ccs_1_cry_2_740), + .LI(plm_sym_un1_reg_outstanding_ccs_1_axb_3_748), + .O(plm_sym_un1_reg_outstanding_ccs_1_s_3_766) + ); + defparam plm_sym_reg_sym_gen_sel_15_i_x3_0_.INIT = 4'h6; + LUT2 plm_sym_reg_sym_gen_sel_15_i_x3_0_ ( + .I0(plm_send_command[1]), + .I1(plm_send_command[2]), + .O(plm_sym_N_3502_i) + ); + defparam plm_sym_reg_sym_gen_sel_15_i_o3_1_.INIT = 4'h8; + LUT2 plm_sym_reg_sym_gen_sel_15_i_o3_1_ ( + .I0(plm_send_command[0]), + .I1(plm_send_command[2]), + .O(plm_sym_N_8917) + ); + defparam plm_sym_frm_dispatched_ccs.INIT = 4'h2; + LUT2 plm_sym_frm_dispatched_ccs ( + .I0(plm_frm_atomic), + .I1(plm_sym_reg_frm_atomic_760), + .O(plm_sym_frm_dispatched_ccs_751) + ); + defparam plm_sym_lane0_bypass_reg_tx0_raw_char_pass_8_0_iv_i_0_0_a3_0_.INIT = 4'h2; + LUT2 plm_sym_lane0_bypass_reg_tx0_raw_char_pass_8_0_iv_i_0_0_a3_0_ ( + .I0(plm_sym_sym_bypass[0]), + .I1(plm_tx0_link_pad), + .O(plm_sym_N_39041) + ); + defparam plm_sym_lane0_bypass_reg_tx0_raw_char_8_0_0_0_a3_9_.INIT = 4'h1; + LUT2 plm_sym_lane0_bypass_reg_tx0_raw_char_8_0_0_0_a3_9_ ( + .I0(plm_sym_sym_bypass[0]), + .I1(plm_sym_sym_bypass[1]), + .O(plm_sym_N_39030) + ); + defparam plm_sym_lane0_bypass_reg_tx0_raw_char_8_3_0_0_a4_6_.INIT = 4'h8; + LUT2 plm_sym_lane0_bypass_reg_tx0_raw_char_8_3_0_0_a4_6_ ( + .I0(plm_sym_sym_bypass[0]), + .I1(plm_sym_sym_bypass[1]), + .O(plm_sym_N_38399) + ); + defparam plm_sym_un6_reg_count_s_11_sf.INIT = 4'h1; + LUT1 plm_sym_un6_reg_count_s_11_sf ( + .I0(plm_sym_reg_count_5076[11]), + .O(plm_sym_un6_reg_count_s_11_sf_741) + ); + defparam plm_sym_lane0_bypass_reg_tx0_raw_char_8_i_0_0_m3_0_0_8_.INIT = 8'hB8; + LUT3_L plm_sym_lane0_bypass_reg_tx0_raw_char_8_i_0_0_m3_0_0_8_ ( + .I0(plm_frm0_char[8]), + .I1(plm_sym_sym_bypass[2]), + .I2(plm_sym_sym_symbol_8_), + .LO(plm_sym_N_38246) + ); + defparam plm_sym_lane0_bypass_reg_tx0_raw_char_8_1_i_m2_i_m3_i_m3_0_3_.INIT = 8'hB8; + LUT3_L plm_sym_lane0_bypass_reg_tx0_raw_char_8_1_i_m2_i_m3_i_m3_0_3_ ( + .I0(plm_frm0_char[3]), + .I1(plm_sym_sym_bypass[2]), + .I2(plm_sym_sym_symbol_3_), + .LO(plm_sym_N_51410) + ); + defparam plm_sym_lane0_bypass_reg_tx0_raw_char_8_1_i_m2_i_m3_i_m3_0_11_.INIT = 8'hB8; + LUT3_L plm_sym_lane0_bypass_reg_tx0_raw_char_8_1_i_m2_i_m3_i_m3_0_11_ ( + .I0(plm_frm0_char[11]), + .I1(plm_sym_sym_bypass[2]), + .I2(plm_sym_sym_symbol_11_), + .LO(plm_sym_N_51414) + ); + defparam plm_sym_lane0_bypass_reg_tx0_raw_char_8_1_i_m2_i_m3_i_m3_0_14_.INIT = 8'hB8; + LUT3_L plm_sym_lane0_bypass_reg_tx0_raw_char_8_1_i_m2_i_m3_i_m3_0_14_ ( + .I0(plm_frm0_char[14]), + .I1(plm_sym_sym_bypass[2]), + .I2(plm_sym_sym_symbol_14_), + .LO(plm_sym_N_51416) + ); + defparam plm_sym_lane0_bypass_reg_tx0_raw_char_8_1_i_m2_i_m3_i_m3_0_15_.INIT = 8'hB8; + LUT3 plm_sym_lane0_bypass_reg_tx0_raw_char_8_1_i_m2_i_m3_i_m3_0_15_ ( + .I0(plm_frm0_char[15]), + .I1(plm_sym_sym_bypass[2]), + .I2(plm_sym_sym_symbol_15_), + .O(plm_sym_N_51417) + ); + defparam plm_sym_lane0_bypass_reg_tx0_raw_char_8_1_i_m2_i_m3_i_m3_0_13_.INIT = 8'hB8; + LUT3 plm_sym_lane0_bypass_reg_tx0_raw_char_8_1_i_m2_i_m3_i_m3_0_13_ ( + .I0(plm_frm0_char[13]), + .I1(plm_sym_sym_bypass[2]), + .I2(plm_sym_sym_symbol_13_), + .O(plm_sym_N_51415) + ); + defparam plm_sym_lane0_bypass_reg_tx0_raw_char_8_1_i_m2_i_m3_i_m3_0_10_.INIT = 8'hB8; + LUT3 plm_sym_lane0_bypass_reg_tx0_raw_char_8_1_i_m2_i_m3_i_m3_0_10_ ( + .I0(plm_frm0_char[10]), + .I1(plm_sym_sym_bypass[2]), + .I2(plm_sym_sym_symbol_10_), + .O(plm_sym_N_51413) + ); + defparam plm_sym_lane0_bypass_reg_tx0_raw_char_is_k_8_i_0_0_a4_1_.INIT = 8'h8C; + LUT3 plm_sym_lane0_bypass_reg_tx0_raw_char_is_k_8_i_0_0_a4_1_ ( + .I0(plm_sym_sym_bypass[0]), + .I1(plm_sym_sym_bypass[1]), + .I2(plm_tx0_lane_pad), + .O(plm_sym_N_38489) + ); + defparam plm_sym_un3_frm_clkcmp.INIT = 16'h0001; + LUT4 plm_sym_un3_frm_clkcmp ( + .I0(plm_sym_reg_outstanding_ccs[0]), + .I1(plm_sym_reg_outstanding_ccs[1]), + .I2(plm_sym_reg_outstanding_ccs[2]), + .I3(plm_sym_reg_outstanding_ccs[3]), + .O(plm_un3_frm_clkcmp) + ); + defparam plm_sym_reg_sym_gen_sel_15_i_a3_0_2_.INIT = 8'h02; + LUT3 plm_sym_reg_sym_gen_sel_15_i_a3_0_2_ ( + .I0(plm_send_command[0]), + .I1(plm_send_command[1]), + .I2(plm_send_command[2]), + .O(plm_N_3508) + ); + defparam plm_sym_insert_ccs_6.INIT = 16'h0001; + LUT4_L plm_sym_insert_ccs_6 ( + .I0(plm_sym_reg_count[0]), + .I1(plm_sym_reg_count_5076[8]), + .I2(plm_sym_reg_count_5076[9]), + .I3(plm_sym_reg_count_5076[11]), + .LO(plm_sym_insert_ccs_6_744) + ); + defparam plm_sym_insert_ccs_7.INIT = 16'h0001; + LUT4 plm_sym_insert_ccs_7 ( + .I0(plm_sym_reg_count_5076[1]), + .I1(plm_sym_reg_count_5076[2]), + .I2(plm_sym_reg_count_5076[3]), + .I3(plm_sym_reg_count_5076[10]), + .O(plm_sym_insert_ccs_7_743) + ); + defparam plm_sym_insert_ccs_8.INIT = 16'h0001; + LUT4 plm_sym_insert_ccs_8 ( + .I0(plm_sym_reg_count_5076[4]), + .I1(plm_sym_reg_count_5076[5]), + .I2(plm_sym_reg_count_5076[6]), + .I3(plm_sym_reg_count_5076[7]), + .O(plm_sym_insert_ccs_8_742) + ); + defparam plm_sym_lane0_bypass_reg_tx0_raw_char_8_3_0_0_a4_2_.INIT = 16'h202A; + LUT4_L plm_sym_lane0_bypass_reg_tx0_raw_char_8_3_0_0_a4_2_ ( + .I0(plm_sym_N_39030), + .I1(plm_frm0_char[2]), + .I2(plm_sym_sym_bypass[2]), + .I3(plm_sym_sym_symbol_2_), + .LO(plm_sym_N_38407) + ); + defparam plm_sym_lane0_bypass_reg_tx0_raw_char_8_3_0_0_a4_5_.INIT = 16'h202A; + LUT4_L plm_sym_lane0_bypass_reg_tx0_raw_char_8_3_0_0_a4_5_ ( + .I0(plm_sym_N_39030), + .I1(plm_frm0_char[5]), + .I2(plm_sym_sym_bypass[2]), + .I3(plm_sym_sym_symbol_5_), + .LO(plm_sym_N_38402) + ); + defparam plm_sym_lane0_bypass_reg_tx0_raw_char_8_3_0_0_a4_0_6_.INIT = 16'h202A; + LUT4_L plm_sym_lane0_bypass_reg_tx0_raw_char_8_3_0_0_a4_0_6_ ( + .I0(plm_sym_N_39030), + .I1(plm_frm0_char[6]), + .I2(plm_sym_sym_bypass[2]), + .I3(plm_sym_sym_symbol_6_), + .LO(plm_sym_N_38400) + ); + defparam plm_sym_lane0_bypass_reg_tx0_raw_char_8_0_0_0_a4_1_9_.INIT = 8'h80; + LUT3_L plm_sym_lane0_bypass_reg_tx0_raw_char_8_0_0_0_a4_1_9_ ( + .I0(plm_sym_N_39030), + .I1(plm_frm0_char[9]), + .I2(plm_sym_sym_bypass[2]), + .LO(plm_sym_N_38395) + ); + defparam plm_sym_lane0_bypass_reg_tx0_raw_char_8_3_0_0_a4_1_4_.INIT = 8'h20; + LUT3_L plm_sym_lane0_bypass_reg_tx0_raw_char_8_3_0_0_a4_1_4_ ( + .I0(plm_sym_N_39030), + .I1(plm_frm0_char[4]), + .I2(plm_sym_sym_bypass[2]), + .LO(plm_sym_N_38406) + ); + defparam plm_sym_lane0_bypass_reg_tx0_raw_char_8_3_0_0_a4_1_1_.INIT = 8'h20; + LUT3_L plm_sym_lane0_bypass_reg_tx0_raw_char_8_3_0_0_a4_1_1_ ( + .I0(plm_sym_N_39030), + .I1(plm_frm0_char[1]), + .I2(plm_sym_sym_bypass[2]), + .LO(plm_sym_N_38411) + ); + defparam plm_sym_lane0_bypass_reg_tx0_raw_char_8_i_i_0_a4_0_0_.INIT = 8'h02; + LUT3 plm_sym_lane0_bypass_reg_tx0_raw_char_8_i_i_0_a4_0_0_ ( + .I0(plm_sym_N_39041), + .I1(plm_sym_sym_bypass[1]), + .I2(plm_reg_tx_link_num[0]), + .O(plm_sym_N_38514) + ); + defparam plm_sym_lane0_bypass_reg_tx0_raw_char_is_k_8_i_0_0_0_32080.INIT = 16'h54FF; + LUT4_L plm_sym_lane0_bypass_reg_tx0_raw_char_is_k_8_i_0_0_0_32080 ( + .I0(plm_sym_N_39041), + .I1(plm_frm0_is_k[0]), + .I2(plm_sym_sym_bypass[0]), + .I3(plm_sym_sym_bypass[2]), + .LO(plm_sym_reg_tx0_raw_char_is_k_8_i_0_0_0_32080) + ); + defparam plm_sym_lane0_bypass_reg_tx0_raw_char_8_3_i_i_0_7_.INIT = 8'h51; + LUT3_L plm_sym_lane0_bypass_reg_tx0_raw_char_8_3_i_i_0_7_ ( + .I0(plm_sym_N_38399), + .I1(plm_sym_N_39041), + .I2(plm_reg_tx_link_num[7]), + .LO(plm_sym_reg_tx0_raw_char_8_3_i_i_0[7]) + ); + defparam plm_sym_lane0_bypass_reg_tx0_raw_char_is_k_8_i_0_0_0_1_.INIT = 16'h5554; + LUT4_L plm_sym_lane0_bypass_reg_tx0_raw_char_is_k_8_i_0_0_0_1_ ( + .I0(plm_sym_N_38489), + .I1(plm_sym_sym_bypass[1]), + .I2(plm_sym_sym_bypass[2]), + .I3(plm_sym_sym_is_k[1]), + .LO(plm_sym_reg_tx0_raw_char_is_k_8_i_0_0_0[1]) + ); + defparam plm_sym_lane0_bypass_reg_tx0_raw_char_8_i_0_0_0_3_.INIT = 16'h30F5; + LUT4_L plm_sym_lane0_bypass_reg_tx0_raw_char_8_i_0_0_0_3_ ( + .I0(plm_sym_N_51410), + .I1(cfg_cfg_5072[510]), + .I2(plm_sym_sym_bypass[0]), + .I3(plm_sym_sym_bypass[1]), + .LO(plm_sym_reg_tx0_raw_char_8_i_0_0_0_3_) + ); + defparam plm_sym_reg_sym_gen_sel_1_2_.INIT = 8'h45; + LUT3 plm_sym_reg_sym_gen_sel_1_2_ ( + .I0(plm_frm_atomic), + .I1(plm_send_command[2]), + .I2(plm_un3_frm_clkcmp), + .O(plm_sym_reg_sym_gen_sel_1[2]) + ); + defparam plm_sym_reg_sym_gen_sel_1_.INIT = 16'h3020; + LUT4 plm_sym_reg_sym_gen_sel_1_ ( + .I0(plm_sym_N_8917), + .I1(plm_frm_atomic), + .I2(plm_send_command[1]), + .I3(plm_un3_frm_clkcmp), + .O(plm_sym_reg_sym_gen_sel[1]) + ); + defparam plm_sym_insert_ccs.INIT = 8'h80; + LUT3 plm_sym_insert_ccs ( + .I0(plm_sym_insert_ccs_6_744), + .I1(plm_sym_insert_ccs_7_743), + .I2(plm_sym_insert_ccs_8_742), + .O(plm_sym_insert_ccs_761) + ); + defparam plm_sym_lane0_bypass_reg_tx0_raw_char_8_i_i_0_1_0_.INIT = 16'hDFD5; + LUT4_L plm_sym_lane0_bypass_reg_tx0_raw_char_8_i_i_0_1_0_ ( + .I0(plm_sym_N_39030), + .I1(plm_frm0_char[0]), + .I2(plm_sym_sym_bypass[2]), + .I3(plm_sym_sym_symbol_8_), + .LO(plm_sym_reg_tx0_raw_char_8_i_i_0_1[0]) + ); + defparam plm_sym_lane0_bypass_reg_tx0_raw_char_8_i_0_0_0_12_.INIT = 16'h5155; + LUT4_L plm_sym_lane0_bypass_reg_tx0_raw_char_8_i_0_0_0_12_ ( + .I0(plm_sym_N_38489), + .I1(plm_sym_N_39030), + .I2(plm_frm0_char[12]), + .I3(plm_sym_sym_bypass[2]), + .LO(plm_sym_reg_tx0_raw_char_8_i_0_0_0_12_) + ); + defparam plm_sym_lane0_bypass_reg_tx0_raw_char_8_3_0_0_1_4_.INIT = 16'h1101; + LUT4_L plm_sym_lane0_bypass_reg_tx0_raw_char_8_3_0_0_1_4_ ( + .I0(plm_sym_N_38399), + .I1(plm_sym_N_38406), + .I2(plm_sym_N_39041), + .I3(plm_reg_tx_link_num[4]), + .LO(plm_sym_reg_tx0_raw_char_8_3_0_0_1_4_) + ); + defparam plm_sym_lane0_bypass_reg_tx0_raw_char_8_3_0_0_1_1_.INIT = 16'h1101; + LUT4_L plm_sym_lane0_bypass_reg_tx0_raw_char_8_3_0_0_1_1_ ( + .I0(plm_sym_N_38399), + .I1(plm_sym_N_38411), + .I2(plm_sym_N_39041), + .I3(plm_reg_tx_link_num[1]), + .LO(plm_sym_reg_tx0_raw_char_8_3_0_0_1_1_) + ); + defparam plm_sym_lane0_bypass_reg_tx0_raw_char_8_0_0_0_0_9_.INIT = 16'h0515; + LUT4_L plm_sym_lane0_bypass_reg_tx0_raw_char_8_0_0_0_0_9_ ( + .I0(plm_sym_N_38395), + .I1(plm_sym_sym_bypass[0]), + .I2(plm_sym_sym_bypass[1]), + .I3(plm_tx0_lane_pad), + .LO(plm_sym_reg_tx0_raw_char_8_0_0_0_0[9]) + ); + defparam plm_sym_reg_sym_gen_sel_0_.INIT = 16'h0323; + LUT4 plm_sym_reg_sym_gen_sel_0_ ( + .I0(plm_sym_N_3502_i), + .I1(plm_frm_atomic), + .I2(plm_send_command[0]), + .I3(plm_un3_frm_clkcmp), + .O(plm_sym_reg_sym_gen_sel[0]) + ); + defparam plm_sym_reg_sym_gen_sel_2_.INIT = 4'h4; + LUT2 plm_sym_reg_sym_gen_sel_2_ ( + .I0(plm_N_3508), + .I1(plm_sym_reg_sym_gen_sel_1[2]), + .O(plm_sym_reg_sym_gen_sel[2]) + ); + defparam plm_sym_un1_reg_tx0_raw_char_pass_f1_1_0_.INIT = 8'hF9; + LUT3 plm_sym_un1_reg_tx0_raw_char_pass_f1_1_0_ ( + .I0(plm_sym_sent_status[4]), + .I1(plm_sym_frm_dispatched_ccs_751), + .I2(plm_sym_insert_ccs_761), + .O(plm_sym_N_8657_1) + ); + defparam plm_sym_un1_reg_tx0_raw_char_pass_f1_0_0_.INIT = 8'h6F; + LUT3 plm_sym_un1_reg_tx0_raw_char_pass_f1_0_0_ ( + .I0(plm_sym_sent_status[4]), + .I1(plm_sym_frm_dispatched_ccs_751), + .I2(plm_sym_insert_ccs_761), + .O(plm_sym_un1_reg_tx0_raw_char_pass_f1_0[0]) + ); + defparam plm_sym_un1_reg_outstanding_ccs_1_axb_0.INIT = 8'h93; + LUT3 plm_sym_un1_reg_outstanding_ccs_1_axb_0 ( + .I0(plm_sym_N_8657_1), + .I1(plm_sym_reg_outstanding_ccs[0]), + .I2(plm_sym_un1_reg_tx0_raw_char_pass_f1_0[0]), + .O(plm_sym_un1_reg_outstanding_ccs_1_axb_0_769) + ); + defparam plm_sym_lane0_bypass_reg_tx0_raw_char_8_3_0_0_4_.INIT = 16'hCCC4; + LUT4_L plm_sym_lane0_bypass_reg_tx0_raw_char_8_3_0_0_4_ ( + .I0(plm_sym_N_39030), + .I1(plm_sym_reg_tx0_raw_char_8_3_0_0_1_4_), + .I2(plm_sym_sym_bypass[2]), + .I3(plm_sym_sym_is_k[0]), + .LO(plm_sym_N_8702_i) + ); + defparam plm_sym_lane0_bypass_N_67888_i.INIT = 16'h3B33; + LUT4_L plm_sym_lane0_bypass_N_67888_i ( + .I0(plm_sym_N_39041), + .I1(plm_sym_reg_tx0_raw_char_8_i_0_0_0_3_), + .I2(plm_sym_sym_bypass[1]), + .I3(plm_reg_tx_link_num[3]), + .LO(plm_sym_N_67888_i) + ); + defparam plm_sym_lane0_bypass_reg_tx0_raw_char_8_3_0_0_2_.INIT = 16'h1101; + LUT4_L plm_sym_lane0_bypass_reg_tx0_raw_char_8_3_0_0_2_ ( + .I0(plm_sym_N_38399), + .I1(plm_sym_N_38407), + .I2(plm_sym_N_39041), + .I3(plm_reg_tx_link_num[2]), + .LO(plm_sym_N_8704_i) + ); + defparam plm_sym_lane0_bypass_reg_tx0_raw_char_8_3_0_0_1_.INIT = 16'hCCC4; + LUT4_L plm_sym_lane0_bypass_reg_tx0_raw_char_8_3_0_0_1_ ( + .I0(plm_sym_N_39030), + .I1(plm_sym_reg_tx0_raw_char_8_3_0_0_1_1_), + .I2(plm_sym_sym_bypass[2]), + .I3(plm_sym_sym_symbol_1_), + .LO(plm_sym_N_8705_i) + ); + defparam plm_sym_lane0_bypass_reg_tx0_raw_char_8_i_i_0_0_.INIT = 16'h3100; + LUT4_L plm_sym_lane0_bypass_reg_tx0_raw_char_8_i_i_0_0_ ( + .I0(plm_sym_N_38399), + .I1(plm_sym_N_38514), + .I2(plm_link_ctrl[0]), + .I3(plm_sym_reg_tx0_raw_char_8_i_i_0_1[0]), + .LO(plm_sym_N_24851_i) + ); + defparam plm_sym_lane0_bypass_N_69257_i.INIT = 8'hBA; + LUT3_L plm_sym_lane0_bypass_N_69257_i ( + .I0(plm_sym_N_38489), + .I1(plm_sym_sym_bypass[2]), + .I2(plm_sym_sym_pass[1]), + .LO(plm_sym_N_69257_i) + ); + defparam plm_sym_lane0_bypass_N_67887_i.INIT = 16'hEFEE; + LUT4_L plm_sym_lane0_bypass_N_67887_i ( + .I0(plm_sym_N_39041), + .I1(plm_sym_sym_bypass[1]), + .I2(plm_sym_sym_bypass[2]), + .I3(plm_sym_sym_pass[0]), + .LO(plm_sym_N_67887_i) + ); + defparam plm_sym_reg_count_5_3_.INIT = 4'h4; + LUT2_L plm_sym_reg_count_5_3_ ( + .I0(plm_sym_insert_ccs_761), + .I1(plm_sym_un6_reg_count_s_3_745), + .LO(plm_sym_reg_count_5_3__762) + ); + defparam plm_sym_reg_count_5_2_.INIT = 4'h4; + LUT2_L plm_sym_reg_count_5_2_ ( + .I0(plm_sym_insert_ccs_761), + .I1(plm_sym_un6_reg_count_s_2_746), + .LO(plm_sym_reg_count_5_2__763) + ); + defparam plm_sym_reg_count_5_1_.INIT = 4'h4; + LUT2_L plm_sym_reg_count_5_1_ ( + .I0(plm_sym_insert_ccs_761), + .I1(plm_sym_un6_reg_count_s_1_747), + .LO(plm_sym_reg_count_5_1__764) + ); + defparam plm_sym_reg_count_5_0_.INIT = 4'h1; + LUT2_L plm_sym_reg_count_5_0_ ( + .I0(plm_sym_insert_ccs_761), + .I1(plm_sym_reg_count[0]), + .LO(plm_sym_reg_count_5_0__765) + ); + defparam plm_sym_lane0_bypass_reg_tx0_raw_char_8_i_0_0_15_.INIT = 8'h51; + LUT3_L plm_sym_lane0_bypass_reg_tx0_raw_char_8_i_0_0_15_ ( + .I0(plm_sym_N_38489), + .I1(plm_sym_N_39030), + .I2(plm_sym_N_51417), + .LO(plm_sym_N_20556_i) + ); + defparam plm_sym_lane0_bypass_reg_tx0_raw_char_8_i_0_0_14_.INIT = 16'h3202; + LUT4_L plm_sym_lane0_bypass_reg_tx0_raw_char_8_i_0_0_14_ ( + .I0(plm_sym_N_51416), + .I1(plm_sym_sym_bypass[0]), + .I2(plm_sym_sym_bypass[1]), + .I3(plm_tx0_lane_pad), + .LO(plm_sym_N_20554_i) + ); + defparam plm_sym_lane0_bypass_reg_tx0_raw_char_8_i_0_0_13_.INIT = 8'h51; + LUT3_L plm_sym_lane0_bypass_reg_tx0_raw_char_8_i_0_0_13_ ( + .I0(plm_sym_N_38489), + .I1(plm_sym_N_39030), + .I2(plm_sym_N_51415), + .LO(plm_sym_N_20552_i) + ); + defparam plm_sym_lane0_bypass_reg_tx0_raw_char_8_i_0_0_12_.INIT = 16'hCCC4; + LUT4_L plm_sym_lane0_bypass_reg_tx0_raw_char_8_i_0_0_12_ ( + .I0(plm_sym_N_39030), + .I1(plm_sym_reg_tx0_raw_char_8_i_0_0_0_12_), + .I2(plm_sym_sym_bypass[2]), + .I3(plm_sym_sym_is_k[1]), + .LO(plm_sym_N_20550_i) + ); + defparam plm_sym_lane0_bypass_reg_tx0_raw_char_8_i_0_0_11_.INIT = 8'h0E; + LUT3_L plm_sym_lane0_bypass_reg_tx0_raw_char_8_i_0_0_11_ ( + .I0(plm_sym_N_51414), + .I1(plm_sym_sym_bypass[0]), + .I2(plm_sym_sym_bypass[1]), + .LO(plm_sym_N_20548_i) + ); + defparam plm_sym_lane0_bypass_reg_tx0_raw_char_8_i_0_0_10_.INIT = 8'h51; + LUT3_L plm_sym_lane0_bypass_reg_tx0_raw_char_8_i_0_0_10_ ( + .I0(plm_sym_N_38489), + .I1(plm_sym_N_39030), + .I2(plm_sym_N_51413), + .LO(plm_sym_N_20546_i) + ); + defparam plm_sym_lane0_bypass_N_67875_i.INIT = 16'h3B33; + LUT4_L plm_sym_lane0_bypass_N_67875_i ( + .I0(plm_sym_N_39030), + .I1(plm_sym_reg_tx0_raw_char_8_0_0_0_0[9]), + .I2(plm_sym_sym_bypass[2]), + .I3(plm_sym_sym_symbol_1_), + .LO(plm_sym_N_67875_i) + ); + defparam plm_sym_lane0_bypass_reg_tx0_raw_char_8_i_0_0_8_.INIT = 16'h3202; + LUT4_L plm_sym_lane0_bypass_reg_tx0_raw_char_8_i_0_0_8_ ( + .I0(plm_sym_N_38246), + .I1(plm_sym_sym_bypass[0]), + .I2(plm_sym_sym_bypass[1]), + .I3(plm_tx0_lane_pad), + .LO(plm_sym_N_20543_i) + ); + defparam plm_sym_lane0_bypass_reg_tx0_raw_char_8_3_i_i_7_.INIT = 16'hD050; + LUT4_L plm_sym_lane0_bypass_reg_tx0_raw_char_8_3_i_i_7_ ( + .I0(plm_sym_N_39030), + .I1(plm_frm0_char[7]), + .I2(plm_sym_reg_tx0_raw_char_8_3_i_i_0[7]), + .I3(plm_sym_sym_bypass[2]), + .LO(plm_sym_N_37114_i) + ); + defparam plm_sym_lane0_bypass_reg_tx0_raw_char_8_3_0_0_6_.INIT = 16'h1101; + LUT4_L plm_sym_lane0_bypass_reg_tx0_raw_char_8_3_0_0_6_ ( + .I0(plm_sym_N_38399), + .I1(plm_sym_N_38400), + .I2(plm_sym_N_39041), + .I3(plm_reg_tx_link_num[6]), + .LO(plm_sym_N_8700_i) + ); + defparam plm_sym_lane0_bypass_reg_tx0_raw_char_8_3_0_0_5_.INIT = 16'h1101; + LUT4_L plm_sym_lane0_bypass_reg_tx0_raw_char_8_3_0_0_5_ ( + .I0(plm_sym_N_38399), + .I1(plm_sym_N_38402), + .I2(plm_sym_N_39041), + .I3(plm_reg_tx_link_num[5]), + .LO(plm_sym_N_8701_i) + ); + defparam plm_sym_lane0_bypass_reg_tx0_raw_char_is_k_8_i_0_0_1_.INIT = 16'hD0F0; + LUT4_L plm_sym_lane0_bypass_reg_tx0_raw_char_is_k_8_i_0_0_1_ ( + .I0(plm_sym_N_39030), + .I1(plm_frm0_is_k[1]), + .I2(plm_sym_reg_tx0_raw_char_is_k_8_i_0_0_0[1]), + .I3(plm_sym_sym_bypass[2]), + .LO(plm_sym_N_20541_i) + ); + defparam plm_sym_lane0_bypass_reg_tx0_raw_char_is_k_8_i_0_0_0_.INIT = 16'h2220; + LUT4_L plm_sym_lane0_bypass_reg_tx0_raw_char_is_k_8_i_0_0_0_ ( + .I0(plm_sym_reg_tx0_raw_char_is_k_8_i_0_0_0_32080), + .I1(plm_sym_sym_bypass[1]), + .I2(plm_sym_sym_bypass[2]), + .I3(plm_sym_sym_is_k[0]), + .LO(plm_sym_N_20539_i) + ); + defparam plm_sym_un1_reg_outstanding_ccs_1_axb_3.INIT = 16'h718E; + LUT4_L plm_sym_un1_reg_outstanding_ccs_1_axb_3 ( + .I0(plm_sym_sent_status[4]), + .I1(plm_sym_frm_dispatched_ccs_751), + .I2(plm_sym_insert_ccs_761), + .I3(plm_sym_reg_outstanding_ccs[3]), + .LO(plm_sym_un1_reg_outstanding_ccs_1_axb_3_748) + ); + defparam plm_sym_un1_reg_outstanding_ccs_1_axb_2.INIT = 16'h718E; + LUT4_L plm_sym_un1_reg_outstanding_ccs_1_axb_2 ( + .I0(plm_sym_sent_status[4]), + .I1(plm_sym_frm_dispatched_ccs_751), + .I2(plm_sym_insert_ccs_761), + .I3(plm_sym_reg_outstanding_ccs[2]), + .LO(plm_sym_un1_reg_outstanding_ccs_1_axb_2_749) + ); + defparam plm_sym_un1_reg_outstanding_ccs_1_axb_1.INIT = 16'h718E; + LUT4_L plm_sym_un1_reg_outstanding_ccs_1_axb_1 ( + .I0(plm_sym_sent_status[4]), + .I1(plm_sym_frm_dispatched_ccs_751), + .I2(plm_sym_insert_ccs_761), + .I3(plm_sym_reg_outstanding_ccs[1]), + .LO(plm_sym_un1_reg_outstanding_ccs_1_axb_1_750) + ); + defparam plm_sym_reg_count_5_11_.INIT = 4'h4; + LUT2_L plm_sym_reg_count_5_11_ ( + .I0(plm_sym_insert_ccs_761), + .I1(plm_sym_un6_reg_count_s_11_752), + .LO(plm_sym_reg_count_5_11__770) + ); + defparam plm_sym_reg_count_5_10_.INIT = 4'h4; + LUT2_L plm_sym_reg_count_5_10_ ( + .I0(plm_sym_insert_ccs_761), + .I1(plm_sym_un6_reg_count_s_10_753), + .LO(plm_sym_reg_count_5_10__771) + ); + defparam plm_sym_un6_reg_count_s_9_sf.INIT = 4'h1; + LUT1_L plm_sym_un6_reg_count_s_9_sf ( + .I0(plm_sym_reg_count_5076[9]), + .LO(plm_sym_un6_reg_count_s_9_sf_754) + ); + defparam plm_sym_un6_reg_count_s_8_sf.INIT = 4'h1; + LUT1_L plm_sym_un6_reg_count_s_8_sf ( + .I0(plm_sym_reg_count_5076[8]), + .LO(plm_sym_un6_reg_count_s_8_sf_755) + ); + defparam plm_sym_reg_count_5_7_.INIT = 4'h4; + LUT2_L plm_sym_reg_count_5_7_ ( + .I0(plm_sym_insert_ccs_761), + .I1(plm_sym_un6_reg_count_s_7_756), + .LO(plm_sym_reg_count_5_7__774) + ); + defparam plm_sym_reg_count_5_6_.INIT = 4'h4; + LUT2_L plm_sym_reg_count_5_6_ ( + .I0(plm_sym_insert_ccs_761), + .I1(plm_sym_un6_reg_count_s_6_757), + .LO(plm_sym_reg_count_5_6__775) + ); + defparam plm_sym_reg_count_5_5_.INIT = 4'h4; + LUT2_L plm_sym_reg_count_5_5_ ( + .I0(plm_sym_insert_ccs_761), + .I1(plm_sym_un6_reg_count_s_5_758), + .LO(plm_sym_reg_count_5_5__776) + ); + defparam plm_sym_reg_count_5_4_.INIT = 4'h4; + LUT2_L plm_sym_reg_count_5_4_ ( + .I0(plm_sym_insert_ccs_761), + .I1(plm_sym_un6_reg_count_s_4_759), + .LO(plm_sym_reg_count_5_4__777) + ); + FDC plm_sym_reg_frm_atomic ( + .C(mgt_clk), + .D(plm_frm_atomic), + .Q(plm_sym_reg_frm_atomic_760), + .CLR(plm_rst) + ); + FDC plm_sym_reg_raw_tstall ( + .C(mgt_clk), + .D(plm_sym_insert_ccs_761), + .Q(plm_raw_tstall), + .CLR(plm_rst) + ); + FDC plm_sym_reg_tx0_raw_char_4_ ( + .C(mgt_clk), + .D(plm_sym_N_8702_i), + .Q(plm_tx0_raw_char[4]), + .CLR(plm_rst) + ); + FDC plm_sym_reg_tx0_raw_char_3_ ( + .C(mgt_clk), + .D(plm_sym_N_67888_i), + .Q(plm_tx0_raw_char[3]), + .CLR(plm_rst) + ); + FDC plm_sym_reg_tx0_raw_char_2_ ( + .C(mgt_clk), + .D(plm_sym_N_8704_i), + .Q(plm_tx0_raw_char[2]), + .CLR(plm_rst) + ); + FDC plm_sym_reg_tx0_raw_char_1_ ( + .C(mgt_clk), + .D(plm_sym_N_8705_i), + .Q(plm_tx0_raw_char[1]), + .CLR(plm_rst) + ); + FDC plm_sym_reg_tx0_raw_char_0_ ( + .C(mgt_clk), + .D(plm_sym_N_24851_i), + .Q(plm_tx0_raw_char[0]), + .CLR(plm_rst) + ); + FDC plm_sym_reg_tx0_raw_char_pass_1_ ( + .C(mgt_clk), + .D(plm_sym_N_69257_i), + .Q(plm_tx0_raw_char_pass[1]), + .CLR(plm_rst) + ); + FDC plm_sym_reg_tx0_raw_char_pass_0_ ( + .C(mgt_clk), + .D(plm_sym_N_67887_i), + .Q(plm_tx0_raw_char_pass[0]), + .CLR(plm_rst) + ); + FDC plm_sym_reg_count_3_ ( + .C(mgt_clk), + .D(plm_sym_reg_count_5_3__762), + .Q(plm_sym_reg_count_5076[3]), + .CLR(plm_rst) + ); + FDC plm_sym_reg_count_2_ ( + .C(mgt_clk), + .D(plm_sym_reg_count_5_2__763), + .Q(plm_sym_reg_count_5076[2]), + .CLR(plm_rst) + ); + FDC plm_sym_reg_count_1_ ( + .C(mgt_clk), + .D(plm_sym_reg_count_5_1__764), + .Q(plm_sym_reg_count_5076[1]), + .CLR(plm_rst) + ); + FDC plm_sym_reg_count_0_ ( + .C(mgt_clk), + .D(plm_sym_reg_count_5_0__765), + .Q(plm_sym_reg_count[0]), + .CLR(plm_rst) + ); + FDC plm_sym_reg_tx0_raw_char_15_ ( + .C(mgt_clk), + .D(plm_sym_N_20556_i), + .Q(plm_tx0_raw_char[15]), + .CLR(plm_rst) + ); + FDC plm_sym_reg_tx0_raw_char_14_ ( + .C(mgt_clk), + .D(plm_sym_N_20554_i), + .Q(plm_tx0_raw_char[14]), + .CLR(plm_rst) + ); + FDC plm_sym_reg_tx0_raw_char_13_ ( + .C(mgt_clk), + .D(plm_sym_N_20552_i), + .Q(plm_tx0_raw_char[13]), + .CLR(plm_rst) + ); + FDC plm_sym_reg_tx0_raw_char_12_ ( + .C(mgt_clk), + .D(plm_sym_N_20550_i), + .Q(plm_tx0_raw_char[12]), + .CLR(plm_rst) + ); + FDC plm_sym_reg_tx0_raw_char_11_ ( + .C(mgt_clk), + .D(plm_sym_N_20548_i), + .Q(plm_tx0_raw_char[11]), + .CLR(plm_rst) + ); + FDC plm_sym_reg_tx0_raw_char_10_ ( + .C(mgt_clk), + .D(plm_sym_N_20546_i), + .Q(plm_tx0_raw_char[10]), + .CLR(plm_rst) + ); + FDC plm_sym_reg_tx0_raw_char_9_ ( + .C(mgt_clk), + .D(plm_sym_N_67875_i), + .Q(plm_tx0_raw_char[9]), + .CLR(plm_rst) + ); + FDC plm_sym_reg_tx0_raw_char_8_ ( + .C(mgt_clk), + .D(plm_sym_N_20543_i), + .Q(plm_tx0_raw_char[8]), + .CLR(plm_rst) + ); + FDC plm_sym_reg_tx0_raw_char_7_ ( + .C(mgt_clk), + .D(plm_sym_N_37114_i), + .Q(plm_tx0_raw_char[7]), + .CLR(plm_rst) + ); + FDC plm_sym_reg_tx0_raw_char_6_ ( + .C(mgt_clk), + .D(plm_sym_N_8700_i), + .Q(plm_tx0_raw_char[6]), + .CLR(plm_rst) + ); + FDC plm_sym_reg_tx0_raw_char_5_ ( + .C(mgt_clk), + .D(plm_sym_N_8701_i), + .Q(plm_tx0_raw_char[5]), + .CLR(plm_rst) + ); + FDC plm_sym_reg_tx0_raw_char_is_k_1_ ( + .C(mgt_clk), + .D(plm_sym_N_20541_i), + .Q(plm_tx0_raw_char_is_k[1]), + .CLR(plm_rst) + ); + FDC plm_sym_reg_tx0_raw_char_is_k_0_ ( + .C(mgt_clk), + .D(plm_sym_N_20539_i), + .Q(plm_tx0_raw_char_is_k[0]), + .CLR(plm_rst) + ); + FDC plm_sym_reg_outstanding_ccs_3_ ( + .C(mgt_clk), + .D(plm_sym_un1_reg_outstanding_ccs_1_s_3_766), + .Q(plm_sym_reg_outstanding_ccs[3]), + .CLR(plm_rst) + ); + FDC plm_sym_reg_outstanding_ccs_2_ ( + .C(mgt_clk), + .D(plm_sym_un1_reg_outstanding_ccs_1_s_2_767), + .Q(plm_sym_reg_outstanding_ccs[2]), + .CLR(plm_rst) + ); + FDC plm_sym_reg_outstanding_ccs_1_ ( + .C(mgt_clk), + .D(plm_sym_un1_reg_outstanding_ccs_1_s_1_768), + .Q(plm_sym_reg_outstanding_ccs[1]), + .CLR(plm_rst) + ); + FDC plm_sym_reg_outstanding_ccs_0_ ( + .C(mgt_clk), + .D(plm_sym_un1_reg_outstanding_ccs_1_axb_0_769), + .Q(plm_sym_reg_outstanding_ccs[0]), + .CLR(plm_rst) + ); + FDC plm_sym_reg_count_11_ ( + .C(mgt_clk), + .D(plm_sym_reg_count_5_11__770), + .Q(plm_sym_reg_count_5076[11]), + .CLR(plm_rst) + ); + FDC plm_sym_reg_count_10_ ( + .C(mgt_clk), + .D(plm_sym_reg_count_5_10__771), + .Q(plm_sym_reg_count_5076[10]), + .CLR(plm_rst) + ); + FDP plm_sym_reg_count_9_ ( + .PRE(plm_rst), + .C(mgt_clk), + .D(plm_sym_un6_reg_count_s_9_772), + .Q(plm_sym_reg_count_5076[9]) + ); + FDP plm_sym_reg_count_8_ ( + .PRE(plm_rst), + .C(mgt_clk), + .D(plm_sym_un6_reg_count_s_8_773), + .Q(plm_sym_reg_count_5076[8]) + ); + FDC plm_sym_reg_count_7_ ( + .C(mgt_clk), + .D(plm_sym_reg_count_5_7__774), + .Q(plm_sym_reg_count_5076[7]), + .CLR(plm_rst) + ); + FDC plm_sym_reg_count_6_ ( + .C(mgt_clk), + .D(plm_sym_reg_count_5_6__775), + .Q(plm_sym_reg_count_5076[6]), + .CLR(plm_rst) + ); + FDC plm_sym_reg_count_5_ ( + .C(mgt_clk), + .D(plm_sym_reg_count_5_5__776), + .Q(plm_sym_reg_count_5076[5]), + .CLR(plm_rst) + ); + FDC plm_sym_reg_count_4_ ( + .C(mgt_clk), + .D(plm_sym_reg_count_5_4__777), + .Q(plm_sym_reg_count_5076[4]), + .CLR(plm_rst) + ); + defparam plm_sym_un6_reg_count_s_10_sf.INIT = 4'h1; + LUT1 plm_sym_un6_reg_count_s_10_sf ( + .I0(plm_sym_reg_count_5076[10]), + .O(plm_sym_un6_reg_count_s_10_sf_778) + ); + defparam plm_sym_un6_reg_count_s_7_sf.INIT = 4'h1; + LUT1 plm_sym_un6_reg_count_s_7_sf ( + .I0(plm_sym_reg_count_5076[7]), + .O(plm_sym_un6_reg_count_s_7_sf_779) + ); + defparam plm_sym_un6_reg_count_s_6_sf.INIT = 4'h1; + LUT1 plm_sym_un6_reg_count_s_6_sf ( + .I0(plm_sym_reg_count_5076[6]), + .O(plm_sym_un6_reg_count_s_6_sf_780) + ); + defparam plm_sym_un6_reg_count_s_5_sf.INIT = 4'h1; + LUT1 plm_sym_un6_reg_count_s_5_sf ( + .I0(plm_sym_reg_count_5076[5]), + .O(plm_sym_un6_reg_count_s_5_sf_781) + ); + defparam plm_sym_un6_reg_count_s_4_sf.INIT = 4'h1; + LUT1 plm_sym_un6_reg_count_s_4_sf ( + .I0(plm_sym_reg_count_5076[4]), + .O(plm_sym_un6_reg_count_s_4_sf_782) + ); + defparam plm_sym_un6_reg_count_s_3_sf.INIT = 4'h1; + LUT1 plm_sym_un6_reg_count_s_3_sf ( + .I0(plm_sym_reg_count_5076[3]), + .O(plm_sym_un6_reg_count_s_3_sf_783) + ); + defparam plm_sym_un6_reg_count_s_2_sf.INIT = 4'h1; + LUT1 plm_sym_un6_reg_count_s_2_sf ( + .I0(plm_sym_reg_count_5076[2]), + .O(plm_sym_un6_reg_count_s_2_sf_784) + ); + defparam plm_sym_un6_reg_count_s_1_sf.INIT = 4'h1; + LUT1 plm_sym_un6_reg_count_s_1_sf ( + .I0(plm_sym_reg_count_5076[1]), + .O(plm_sym_un6_reg_count_s_1_sf_785) + ); + defparam plm_sym_sym_gen_next_addr_cnst_i_x2_2_.INIT = 4'h9; + LUT2 plm_sym_sym_gen_next_addr_cnst_i_x2_2_ ( + .I0(plm_sym_reg_sym_gen_sel[0]), + .I1(plm_sym_reg_sym_gen_sel[1]), + .O(plm_sym_sym_gen_N_3524_i) + ); + defparam plm_sym_sym_gen_next_addr_0_4_.INIT = 16'h88F0; + LUT4 plm_sym_sym_gen_next_addr_0_4_ ( + .I0(plm_sym_reg_sym_gen_sel[1]), + .I1(plm_sym_reg_sym_gen_sel_1[2]), + .I2(plm_sym_sym_gen_reg_rom_out[4]), + .I3(plm_sym_sym_gen_reg_rom_out[5]), + .O(plm_sym_sym_gen_next_addr[4]) + ); + defparam plm_sym_sym_gen_next_addr_0_3_.INIT = 16'h44F0; + LUT4 plm_sym_sym_gen_next_addr_0_3_ ( + .I0(plm_sym_reg_sym_gen_sel[0]), + .I1(plm_sym_reg_sym_gen_sel[2]), + .I2(plm_sym_sym_gen_reg_rom_out[3]), + .I3(plm_sym_sym_gen_reg_rom_out[5]), + .O(plm_sym_sym_gen_next_addr[3]) + ); + defparam plm_sym_sym_gen_reg_rom_out_27_i_o2_8_.INIT = 4'h1; + LUT2 plm_sym_sym_gen_reg_rom_out_27_i_o2_8_ ( + .I0(plm_sym_sym_gen_next_addr[3]), + .I1(plm_sym_sym_gen_next_addr[4]), + .O(N_224_i) + ); + defparam plm_sym_sym_gen_next_addr_0_0_.INIT = 16'h22F0; + LUT4 plm_sym_sym_gen_next_addr_0_0_ ( + .I0(plm_sym_sym_gen_N_3531), + .I1(plm_sym_reg_sym_gen_sel[0]), + .I2(plm_sym_sym_gen_reg_rom_out[0]), + .I3(plm_sym_sym_gen_reg_rom_out[5]), + .O(plm_sym_sym_gen_next_addr[0]) + ); + defparam plm_sym_sym_gen_next_addr_0_1_.INIT = 16'h88F0; + LUT4 plm_sym_sym_gen_next_addr_0_1_ ( + .I0(plm_sym_sym_gen_N_3523_i), + .I1(plm_sym_reg_sym_gen_sel[0]), + .I2(plm_sym_sym_gen_reg_rom_out[1]), + .I3(plm_sym_sym_gen_reg_rom_out[5]), + .O(plm_sym_sym_gen_next_addr[1]) + ); + defparam plm_sym_sym_gen_next_addr_0_2_.INIT = 16'h11F0; + LUT4 plm_sym_sym_gen_next_addr_0_2_ ( + .I0(plm_sym_sym_gen_N_3524_i), + .I1(plm_sym_sym_gen_N_3531), + .I2(plm_sym_sym_gen_reg_rom_out[2]), + .I3(plm_sym_sym_gen_reg_rom_out[5]), + .O(plm_sym_sym_gen_next_addr[2]) + ); + defparam plm_sym_sym_gen_reg_rom_out_27_0_o2_6_.INIT = 4'h1; + LUT2 plm_sym_sym_gen_reg_rom_out_27_0_o2_6_ ( + .I0(plm_sym_sym_gen_next_addr[1]), + .I1(plm_sym_sym_gen_next_addr[2]), + .O(N_223_i) + ); + defparam plm_sym_sym_gen_reg_rom_out_27_i_a2_2_.INIT = 4'h8; + LUT2 plm_sym_sym_gen_reg_rom_out_27_i_a2_2_ ( + .I0(plm_sym_sym_gen_next_addr[2]), + .I1(plm_sym_sym_gen_reg_rom_out[1]), + .O(plm_sym_sym_gen_N_236) + ); + defparam plm_sym_sym_gen_reg_rom_out_27_i_o3_30_.INIT = 4'h1; + LUT2 plm_sym_sym_gen_reg_rom_out_27_i_o3_30_ ( + .I0(plm_sym_sym_gen_next_addr[0]), + .I1(plm_sym_sym_gen_next_addr[2]), + .O(plm_sym_sym_gen_N_133_i) + ); + defparam plm_sym_sym_gen_reg_rom_out_27_i_a2_28_.INIT = 4'h2; + LUT2 plm_sym_sym_gen_reg_rom_out_27_i_a2_28_ ( + .I0(N_224_i), + .I1(plm_sym_sym_gen_next_addr[0]), + .O(plm_sym_sym_gen_N_161) + ); + defparam plm_sym_sym_gen_reg_rom_out_27_0_a3_27_.INIT = 8'h28; + LUT3 plm_sym_sym_gen_reg_rom_out_27_0_a3_27_ ( + .I0(N_224_i), + .I1(plm_sym_sym_gen_next_addr[1]), + .I2(plm_sym_sym_gen_next_addr[2]), + .O(plm_sym_sym_gen_reg_rom_out_27_0_a3[27]) + ); + defparam plm_sym_sym_gen_reg_rom_out_27_0_a3_0_26_.INIT = 8'h02; + LUT3 plm_sym_sym_gen_reg_rom_out_27_0_a3_0_26_ ( + .I0(N_223_i), + .I1(N_224_i), + .I2(plm_sym_sym_gen_next_addr[0]), + .O(plm_sym_sym_gen_N_148) + ); + defparam plm_sym_sym_gen_reg_rom_out_27_i_m3_0_24_.INIT = 16'hD8DA; + LUT4_L plm_sym_sym_gen_reg_rom_out_27_i_m3_0_24_ ( + .I0(N_223_i), + .I1(plm_sym_sym_gen_next_addr[0]), + .I2(plm_sym_sym_gen_next_addr[3]), + .I3(plm_sym_sym_gen_next_addr[4]), + .LO(plm_sym_sym_gen_N_138) + ); + defparam plm_sym_sym_gen_reg_rom_out_27_0_0_25_.INIT = 8'h53; + LUT3 plm_sym_sym_gen_reg_rom_out_27_0_0_25_ ( + .I0(N_224_i), + .I1(N_3004), + .I2(plm_sym_sym_gen_next_addr[1]), + .O(plm_sym_sym_gen_reg_rom_out_27_0_0[25]) + ); + defparam plm_sym_sym_gen_address_table_next_addr39.INIT = 8'h80; + LUT3_L plm_sym_sym_gen_address_table_next_addr39 ( + .I0(plm_sym_sym_gen_N_3531), + .I1(plm_sym_reg_sym_gen_sel[0]), + .I2(plm_sym_sym_gen_reg_rom_out[5]), + .LO(plm_sym_sym_gen_next_addr39) + ); + defparam plm_sym_sym_gen_reg_rom_out_27_i_22_.INIT = 4'h4; + LUT2_L plm_sym_sym_gen_reg_rom_out_27_i_22_ ( + .I0(N_172), + .I1(plm_sym_sym_gen_next_addr[4]), + .LO(plm_sym_sym_gen_reg_rom_out_27_22_) + ); + defparam plm_sym_sym_gen_reg_rom_out_27_i_9_.INIT = 4'h1; + LUT2_L plm_sym_sym_gen_reg_rom_out_27_i_9_ ( + .I0(plm_sym_sym_gen_N_148), + .I1(N_224_i), + .LO(plm_sym_sym_gen_reg_rom_out_27_9_) + ); + defparam plm_sym_sym_gen_N_224_i_i.INIT = 4'h1; + LUT1_L plm_sym_sym_gen_N_224_i_i ( + .I0(N_224_i), + .LO(plm_sym_sym_gen_N_224_i_i_786) + ); + defparam plm_sym_sym_gen_N_9357_i.INIT = 16'hFC88; + LUT4_L plm_sym_sym_gen_N_9357_i ( + .I0(N_223_i), + .I1(N_224_i), + .I2(plm_sym_sym_gen_N_236), + .I3(plm_sym_sym_gen_next_addr[0]), + .LO(plm_sym_sym_gen_N_9357_i_787) + ); + defparam plm_sym_sym_gen_reg_rom_out_27_i_4_.INIT = 8'h70; + LUT3_L plm_sym_sym_gen_reg_rom_out_27_i_4_ ( + .I0(plm_sym_sym_gen_N_236), + .I1(plm_sym_sym_gen_next_addr[0]), + .I2(plm_sym_sym_gen_next_addr[4]), + .LO(plm_sym_sym_gen_reg_rom_out_27_4_) + ); + defparam plm_sym_sym_gen_reg_rom_out_27_i_3_.INIT = 8'h70; + LUT3_L plm_sym_sym_gen_reg_rom_out_27_i_3_ ( + .I0(plm_sym_sym_gen_N_236), + .I1(plm_sym_sym_gen_next_addr[0]), + .I2(plm_sym_sym_gen_next_addr[3]), + .LO(plm_sym_sym_gen_reg_rom_out_27_3_) + ); + defparam plm_sym_sym_gen_reg_rom_out_27_i_2_.INIT = 16'h0155; + LUT4_L plm_sym_sym_gen_reg_rom_out_27_i_2_ ( + .I0(N_172), + .I1(N_224_i), + .I2(plm_sym_sym_gen_N_236), + .I3(plm_sym_sym_gen_next_addr[0]), + .LO(plm_sym_sym_gen_reg_rom_out_27_2_) + ); + defparam plm_sym_sym_gen_reg_rom_out_27_i_1_.INIT = 8'h34; + LUT3_L plm_sym_sym_gen_reg_rom_out_27_i_1_ ( + .I0(N_224_i), + .I1(plm_sym_sym_gen_next_addr[0]), + .I2(plm_sym_sym_gen_next_addr[1]), + .LO(plm_sym_sym_gen_reg_rom_out_27_1_) + ); + defparam plm_sym_sym_gen_reg_rom_out_27_i_0_.INIT = 8'h07; + LUT3_L plm_sym_sym_gen_reg_rom_out_27_i_0_ ( + .I0(N_223_i), + .I1(N_224_i), + .I2(plm_sym_sym_gen_next_addr[0]), + .LO(plm_sym_sym_gen_reg_rom_out_27_0_) + ); + defparam plm_sym_sym_gen_address_table_next_addr45.INIT = 16'h8000; + LUT4_L plm_sym_sym_gen_address_table_next_addr45 ( + .I0(plm_sym_reg_sym_gen_sel[0]), + .I1(plm_sym_reg_sym_gen_sel[1]), + .I2(plm_sym_reg_sym_gen_sel_1[2]), + .I3(plm_sym_sym_gen_reg_rom_out[5]), + .LO(plm_sym_sym_gen_next_addr45) + ); + defparam plm_sym_sym_gen_address_table_next_addr44.INIT = 16'h1000; + LUT4_L plm_sym_sym_gen_address_table_next_addr44 ( + .I0(plm_sym_reg_sym_gen_sel[0]), + .I1(plm_sym_reg_sym_gen_sel[1]), + .I2(plm_sym_reg_sym_gen_sel[2]), + .I3(plm_sym_sym_gen_reg_rom_out[5]), + .LO(plm_sym_sym_gen_next_addr44) + ); + defparam plm_sym_sym_gen_address_table_next_addr43.INIT = 16'h2000; + LUT4_L plm_sym_sym_gen_address_table_next_addr43 ( + .I0(plm_sym_reg_sym_gen_sel[0]), + .I1(plm_sym_reg_sym_gen_sel[1]), + .I2(plm_sym_reg_sym_gen_sel[2]), + .I3(plm_sym_sym_gen_reg_rom_out[5]), + .LO(plm_sym_sym_gen_next_addr43) + ); + defparam plm_sym_sym_gen_address_table_next_addr40.INIT = 8'h20; + LUT3_L plm_sym_sym_gen_address_table_next_addr40 ( + .I0(plm_sym_sym_gen_N_3531), + .I1(plm_sym_reg_sym_gen_sel[0]), + .I2(plm_sym_sym_gen_reg_rom_out[5]), + .LO(plm_sym_sym_gen_next_addr40) + ); + defparam plm_sym_sym_gen_reg_rom_out_27_i_30_.INIT = 4'h2; + LUT2_L plm_sym_sym_gen_reg_rom_out_27_i_30_ ( + .I0(plm_sym_sym_gen_N_133_i), + .I1(N_224_i), + .LO(plm_sym_sym_gen_reg_rom_out_27_30_) + ); + defparam plm_sym_sym_gen_reg_rom_out_27_0_a3_29_.INIT = 8'h06; + LUT3_L plm_sym_sym_gen_reg_rom_out_27_0_a3_29_ ( + .I0(N_223_i), + .I1(N_224_i), + .I2(plm_sym_sym_gen_next_addr[0]), + .LO(plm_sym_sym_gen_reg_rom_out_27_29_) + ); + defparam plm_sym_sym_gen_reg_rom_out_27_i_28_.INIT = 16'h1151; + LUT4_L plm_sym_sym_gen_reg_rom_out_27_i_28_ ( + .I0(N_172), + .I1(N_224_i), + .I2(plm_sym_sym_gen_next_addr[0]), + .I3(plm_sym_sym_gen_next_addr[1]), + .LO(plm_sym_sym_gen_reg_rom_out_27_28_) + ); + defparam plm_sym_sym_gen_N_9369_i.INIT = 16'hFEEE; + LUT4_L plm_sym_sym_gen_N_9369_i ( + .I0(plm_sym_sym_gen_N_148), + .I1(plm_sym_sym_gen_reg_rom_out_27_0_a3[27]), + .I2(plm_sym_sym_gen_N_161), + .I3(plm_sym_sym_gen_next_addr[1]), + .LO(plm_sym_sym_gen_N_9369_i_788) + ); + defparam plm_sym_sym_gen_N_9370_i.INIT = 4'hE; + LUT2_L plm_sym_sym_gen_N_9370_i ( + .I0(plm_sym_sym_gen_N_148), + .I1(plm_sym_sym_gen_reg_rom_out_27_6_), + .LO(plm_sym_sym_gen_N_9370_i_789) + ); + defparam plm_sym_sym_gen_N_9371_i.INIT = 16'hA3FF; + LUT4_L plm_sym_sym_gen_N_9371_i ( + .I0(plm_sym_sym_gen_N_148), + .I1(N_172), + .I2(plm_sym_sym_gen_next_addr[4]), + .I3(plm_sym_sym_gen_reg_rom_out_27_0_0[25]), + .LO(plm_sym_sym_gen_N_9371_i_790) + ); + defparam plm_sym_sym_gen_reg_rom_out_27_i_24_.INIT = 16'h1333; + LUT4_L plm_sym_sym_gen_reg_rom_out_27_i_24_ ( + .I0(plm_sym_sym_gen_N_133_i), + .I1(plm_sym_sym_gen_N_138), + .I2(plm_sym_sym_gen_next_addr[1]), + .I3(plm_sym_sym_gen_next_addr[4]), + .LO(plm_sym_sym_gen_reg_rom_out_27_24_) + ); + defparam plm_sym_sym_gen_reg_rom_out_27_0_a3_23_.INIT = 4'h4; + LUT2_L plm_sym_sym_gen_reg_rom_out_27_0_a3_23_ ( + .I0(N_172), + .I1(plm_sym_sym_gen_next_addr[3]), + .LO(plm_sym_sym_gen_reg_rom_out_27_23_) + ); + defparam plm_sym_sym_gen_reg_rom_out_27_i_32_.INIT = 4'h4; + LUT2_L plm_sym_sym_gen_reg_rom_out_27_i_32_ ( + .I0(plm_sym_sym_gen_N_161), + .I1(N_172), + .LO(plm_sym_sym_gen_reg_rom_out_27_32_) + ); + defparam plm_sym_sym_gen_reg_rom_out_27_0_a3_31_.INIT = 16'h0014; + LUT4_L plm_sym_sym_gen_reg_rom_out_27_0_a3_31_ ( + .I0(N_224_i), + .I1(plm_sym_sym_gen_next_addr[0]), + .I2(plm_sym_sym_gen_next_addr[1]), + .I3(plm_sym_sym_gen_next_addr[2]), + .LO(plm_sym_sym_gen_reg_rom_out_27_31_) + ); + defparam plm_sym_sym_gen_next_addr_cnst_i_a2_2_.INIT = 8'h51; + LUT3 plm_sym_sym_gen_next_addr_cnst_i_a2_2_ ( + .I0(plm_sym_reg_sym_gen_sel[1]), + .I1(plm_sym_reg_sym_gen_sel_1[2]), + .I2(plm_N_3508), + .O(plm_sym_sym_gen_N_3531) + ); + defparam plm_sym_sym_gen_next_addr_cnst_i_x2_1_.INIT = 8'hA6; + LUT3_L plm_sym_sym_gen_next_addr_cnst_i_x2_1_ ( + .I0(plm_sym_reg_sym_gen_sel[1]), + .I1(plm_sym_reg_sym_gen_sel_1[2]), + .I2(plm_N_3508), + .LO(plm_sym_sym_gen_N_3523_i) + ); + defparam plm_sym_sym_gen_reg_rom_out_27_0_a3_6_.INIT = 8'h01; + LUT3 plm_sym_sym_gen_reg_rom_out_27_0_a3_6_ ( + .I0(N_223_i), + .I1(plm_sym_sym_gen_next_addr[4]), + .I2(plm_sym_sym_gen_next_addr[3]), + .O(plm_sym_sym_gen_reg_rom_out_27_6_) + ); + FDC plm_sym_sym_gen_reg_sym_sent_0_ ( + .C(mgt_clk), + .D(plm_sym_sym_gen_next_addr39), + .Q(plm_reg_sym_sent_0_), + .CLR(plm_rst) + ); + FDC plm_sym_sym_gen_reg_rom_out_14_ ( + .C(mgt_clk), + .D(plm_sym_sym_gen_reg_rom_out_27_22_), + .Q(plm_sym_sym_symbol_8_), + .CLR(plm_rst) + ); + FDC plm_sym_sym_gen_reg_rom_out_9_ ( + .C(mgt_clk), + .D(plm_sym_sym_gen_reg_rom_out_27_9_), + .Q(plm_sym_sym_pass[1]), + .CLR(plm_rst) + ); + FDC plm_sym_sym_gen_reg_rom_out_8_ ( + .C(mgt_clk), + .D(plm_sym_sym_gen_N_224_i_i_786), + .Q(plm_sym_sym_pass[0]), + .CLR(plm_rst) + ); + FDC plm_sym_sym_gen_reg_rom_out_6_ ( + .C(mgt_clk), + .D(plm_sym_sym_gen_reg_rom_out_27_6_), + .Q(plm_sym_sym_is_k[0]), + .CLR(plm_rst) + ); + FDC plm_sym_sym_gen_reg_rom_out_5_ ( + .C(mgt_clk), + .D(plm_sym_sym_gen_N_9357_i_787), + .Q(plm_sym_sym_gen_reg_rom_out[5]), + .CLR(plm_rst) + ); + FDC plm_sym_sym_gen_reg_rom_out_4_ ( + .C(mgt_clk), + .D(plm_sym_sym_gen_reg_rom_out_27_4_), + .Q(plm_sym_sym_gen_reg_rom_out[4]), + .CLR(plm_rst) + ); + FDC plm_sym_sym_gen_reg_rom_out_3_ ( + .C(mgt_clk), + .D(plm_sym_sym_gen_reg_rom_out_27_3_), + .Q(plm_sym_sym_gen_reg_rom_out[3]), + .CLR(plm_rst) + ); + FDC plm_sym_sym_gen_reg_rom_out_2_ ( + .C(mgt_clk), + .D(plm_sym_sym_gen_reg_rom_out_27_2_), + .Q(plm_sym_sym_gen_reg_rom_out[2]), + .CLR(plm_rst) + ); + FDC plm_sym_sym_gen_reg_rom_out_1_ ( + .C(mgt_clk), + .D(plm_sym_sym_gen_reg_rom_out_27_1_), + .Q(plm_sym_sym_gen_reg_rom_out[1]), + .CLR(plm_rst) + ); + FDC plm_sym_sym_gen_reg_rom_out_0_ ( + .C(mgt_clk), + .D(plm_sym_sym_gen_reg_rom_out_27_0_), + .Q(plm_sym_sym_gen_reg_rom_out[0]), + .CLR(plm_rst) + ); + FDC plm_sym_sym_gen_reg_sym_sent_6_ ( + .C(mgt_clk), + .D(plm_sym_sym_gen_next_addr45), + .Q(plm_reg_sym_sent_6_), + .CLR(plm_rst) + ); + FDC plm_sym_sym_gen_reg_sym_sent_5_ ( + .C(mgt_clk), + .D(plm_sym_sym_gen_next_addr44), + .Q(plm_reg_sym_sent_5_), + .CLR(plm_rst) + ); + FDC plm_sym_sym_gen_reg_sym_sent_4_ ( + .C(mgt_clk), + .D(plm_sym_sym_gen_next_addr43), + .Q(plm_sym_sent_status[4]), + .CLR(plm_rst) + ); + FDC plm_sym_sym_gen_reg_sym_sent_1_ ( + .C(mgt_clk), + .D(plm_sym_sym_gen_next_addr40), + .Q(plm_sent_status[1]), + .CLR(plm_rst) + ); + FDC plm_sym_sym_gen_reg_rom_out_30_ ( + .C(mgt_clk), + .D(plm_sym_sym_gen_reg_rom_out_27_30_), + .Q(plm_sym_sym_bypass[0]), + .CLR(plm_rst) + ); + FDC plm_sym_sym_gen_reg_rom_out_29_ ( + .C(mgt_clk), + .D(plm_sym_sym_gen_reg_rom_out_27_29_), + .Q(plm_sym_sym_symbol_15_), + .CLR(plm_rst) + ); + FDC plm_sym_sym_gen_reg_rom_out_28_ ( + .C(mgt_clk), + .D(plm_sym_sym_gen_reg_rom_out_27_28_), + .Q(plm_sym_sym_symbol_14_), + .CLR(plm_rst) + ); + FDC plm_sym_sym_gen_reg_rom_out_27_ ( + .C(mgt_clk), + .D(plm_sym_sym_gen_N_9369_i_788), + .Q(plm_sym_sym_symbol_13_), + .CLR(plm_rst) + ); + FDC plm_sym_sym_gen_reg_rom_out_26_ ( + .C(mgt_clk), + .D(plm_sym_sym_gen_N_9370_i_789), + .Q(plm_sym_sym_is_k[1]), + .CLR(plm_rst) + ); + FDC plm_sym_sym_gen_reg_rom_out_25_ ( + .C(mgt_clk), + .D(plm_sym_sym_gen_N_9371_i_790), + .Q(plm_sym_sym_symbol_11_), + .CLR(plm_rst) + ); + FDC plm_sym_sym_gen_reg_rom_out_24_ ( + .C(mgt_clk), + .D(plm_sym_sym_gen_reg_rom_out_27_24_), + .Q(plm_sym_sym_symbol_10_), + .CLR(plm_rst) + ); + FDC plm_sym_sym_gen_reg_rom_out_23_ ( + .C(mgt_clk), + .D(plm_sym_sym_gen_reg_rom_out_27_23_), + .Q(plm_sym_sym_symbol_1_), + .CLR(plm_rst) + ); + FDC plm_sym_sym_gen_reg_rom_out_20_ ( + .C(mgt_clk), + .D(N_16_i_63), + .Q(plm_sym_sym_symbol_6_), + .CLR(plm_rst) + ); + FDC plm_sym_sym_gen_reg_rom_out_19_ ( + .C(mgt_clk), + .D(plm_sym_sym_gen_reg_rom_out_27_0_a3[27]), + .Q(plm_sym_sym_symbol_5_), + .CLR(plm_rst) + ); + FDC plm_sym_sym_gen_reg_rom_out_17_ ( + .C(mgt_clk), + .D(plm_sym_sym_gen_reg_rom_out_27[17]), + .Q(plm_sym_sym_symbol_3_), + .CLR(plm_rst) + ); + FDC plm_sym_sym_gen_reg_rom_out_16_ ( + .C(mgt_clk), + .D(N_176_i_62), + .Q(plm_sym_sym_symbol_2_), + .CLR(plm_rst) + ); + FDC plm_sym_sym_gen_reg_rom_out_32_ ( + .C(mgt_clk), + .D(plm_sym_sym_gen_reg_rom_out_27_32_), + .Q(plm_sym_sym_bypass[2]), + .CLR(plm_rst) + ); + FDC plm_sym_sym_gen_reg_rom_out_31_ ( + .C(mgt_clk), + .D(plm_sym_sym_gen_reg_rom_out_27_31_), + .Q(plm_sym_sym_bypass[1]), + .CLR(plm_rst) + ); + defparam plm_frm_d1_start_h.INIT = 4'h6; + LUT2 plm_frm_d1_start_h ( + .I0(plm_frm_reg_d1_tframe_h_804), + .I1(plm_frm_reg_d2_tframe_h_805), + .O(plm_frm_d1_start_h_795) + ); + defparam plm_frm_d1_end_h.INIT = 4'h6; + LUT2 plm_frm_d1_end_h ( + .I0(plm_frm_reg_d1_tframe_l_806), + .I1(plm_frm_reg_d2_tframe_l_807), + .O(plm_frm_d1_end_h_796) + ); + defparam plm_frm_d1_end_l.INIT = 4'h6; + LUT2 plm_frm_d1_end_l ( + .I0(plm_frm_reg_d0_tframe_h_802), + .I1(plm_frm_reg_d1_tframe_h_804), + .O(plm_frm_d1_end_l_797) + ); + defparam plm_frm_delay_one_reg_d1_idleflag_lh_3_0.INIT = 4'h8; + LUT2 plm_frm_delay_one_reg_d1_idleflag_lh_3_0 ( + .I0(plm_frm_reg_d0_td[30]), + .I1(plm_frm_reg_d0_td[31]), + .O(plm_frm_reg_d1_idleflag_lh_3_0) + ); + defparam plm_frm_delay_one_reg_d1_idleflag_ll_3_0.INIT = 4'h8; + LUT2 plm_frm_delay_one_reg_d1_idleflag_ll_3_0 ( + .I0(plm_frm_reg_d0_td[6]), + .I1(plm_frm_reg_d0_td[7]), + .O(plm_frm_reg_d1_idleflag_ll_3_0) + ); + defparam plm_frm_delay_one_reg_d1_idleflag_hh_3_0.INIT = 4'h8; + LUT2 plm_frm_delay_one_reg_d1_idleflag_hh_3_0 ( + .I0(plm_frm_reg_d0_td[62]), + .I1(plm_frm_reg_d0_td[63]), + .O(plm_frm_reg_d1_idleflag_hh_3_0) + ); + defparam plm_frm_delay_one_reg_d1_idleflag_hl_3_0.INIT = 4'h8; + LUT2 plm_frm_delay_one_reg_d1_idleflag_hl_3_0 ( + .I0(plm_frm_reg_d0_td[38]), + .I1(plm_frm_reg_d0_td[39]), + .O(plm_frm_reg_d1_idleflag_hl_3_0) + ); + defparam plm_frm_un1_d1_idle_l.INIT = 8'h80; + LUT3_L plm_frm_un1_d1_idle_l ( + .I0(plm_frm_d1_end_h_796), + .I1(plm_frm_reg_d1_idleflag_lh_810), + .I2(plm_frm_reg_d1_tctrl_l_801), + .LO(plm_frm_un1_d1_idle_l_794) + ); + defparam plm_frm_un1_d1_idle_h.INIT = 8'h80; + LUT3_L plm_frm_un1_d1_idle_h ( + .I0(plm_frm_d1_start_h_795), + .I1(plm_frm_reg_d1_idleflag_hh_808), + .I2(plm_frm_reg_d1_tctrl_h_799), + .LO(plm_frm_un1_d1_idle_h_793) + ); + defparam plm_frm_delay_one_reg_d1_idleflag_lh_3_4.INIT = 16'h8000; + LUT4 plm_frm_delay_one_reg_d1_idleflag_lh_3_4 ( + .I0(plm_frm_reg_d0_td[24]), + .I1(plm_frm_reg_d0_td[25]), + .I2(plm_frm_reg_d0_td[26]), + .I3(plm_frm_reg_d0_td[27]), + .O(plm_frm_reg_d1_idleflag_lh_3_4) + ); + defparam plm_frm_delay_one_reg_d1_idleflag_ll_3_4.INIT = 16'h8000; + LUT4 plm_frm_delay_one_reg_d1_idleflag_ll_3_4 ( + .I0(plm_frm_reg_d0_td[0]), + .I1(plm_frm_reg_d0_td[1]), + .I2(plm_frm_reg_d0_td[2]), + .I3(plm_frm_reg_d0_td[3]), + .O(plm_frm_reg_d1_idleflag_ll_3_4) + ); + defparam plm_frm_delay_one_reg_d1_idleflag_hh_3_4.INIT = 16'h8000; + LUT4 plm_frm_delay_one_reg_d1_idleflag_hh_3_4 ( + .I0(plm_frm_reg_d0_td[56]), + .I1(plm_frm_reg_d0_td[57]), + .I2(plm_frm_reg_d0_td[58]), + .I3(plm_frm_reg_d0_td[59]), + .O(plm_frm_reg_d1_idleflag_hh_3_4) + ); + defparam plm_frm_delay_one_reg_d1_idleflag_hl_3_4.INIT = 16'h8000; + LUT4 plm_frm_delay_one_reg_d1_idleflag_hl_3_4 ( + .I0(plm_frm_reg_d0_td[32]), + .I1(plm_frm_reg_d0_td[33]), + .I2(plm_frm_reg_d0_td[34]), + .I3(plm_frm_reg_d0_td[35]), + .O(plm_frm_reg_d1_idleflag_hl_3_4) + ); + defparam plm_frm_reg_d2_charisk_1_sqmuxa_3.INIT = 8'h02; + LUT3 plm_frm_reg_d2_charisk_1_sqmuxa_3 ( + .I0(plm_frm_d1_end_h_796), + .I1(plm_frm_d1_end_l_797), + .I2(plm_frm_reg_d1_idleflag_lh_810), + .O(plm_frm_reg_d2_charisk_1_sqmuxa_3_822) + ); + defparam plm_frm_reg_d2_charisk_1_sqmuxa_2.INIT = 8'h04; + LUT3 plm_frm_reg_d2_charisk_1_sqmuxa_2 ( + .I0(plm_frm_d1_end_h_796), + .I1(plm_frm_d1_end_l_797), + .I2(plm_frm_reg_d1_idleflag_ll_811), + .O(plm_frm_reg_d2_charisk_1_sqmuxa_2_816) + ); + defparam plm_frm_reg_d2_charisk_1_sqmuxa_1.INIT = 8'h04; + LUT3 plm_frm_reg_d2_charisk_1_sqmuxa_1 ( + .I0(plm_frm_d1_end_h_796), + .I1(plm_frm_d1_start_h_795), + .I2(plm_frm_reg_d1_idleflag_hh_808), + .O(plm_frm_reg_d2_charisk_1_sqmuxa_1_818) + ); + defparam plm_frm_reg_d2_charisk_1_sqmuxa.INIT = 8'h02; + LUT3 plm_frm_reg_d2_charisk_1_sqmuxa ( + .I0(plm_frm_d1_end_h_796), + .I1(plm_frm_d1_start_h_795), + .I2(plm_frm_reg_d1_idleflag_hl_809), + .O(plm_frm_reg_d2_charisk_1_sqmuxa_820) + ); + defparam plm_frm_delay_two_b_reg_d2_td_24_31_.INIT = 4'h1; + LUT2 plm_frm_delay_two_b_reg_d2_td_24_31_ ( + .I0(plm_frm_reg_d2_charisk69), + .I1(plm_frm_reg_d2_charisk_1_sqmuxa_2_816), + .O(plm_frm_N_8807) + ); + defparam plm_frm_un1_reg_d2_td_0_sqmuxa_1.INIT = 16'h9BDF; + LUT4 plm_frm_un1_reg_d2_td_0_sqmuxa_1 ( + .I0(plm_frm_d1_end_h_796), + .I1(plm_frm_d1_end_l_797), + .I2(plm_frm_reg_d1_idleflag_lh_810), + .I3(plm_frm_reg_d1_idleflag_ll_811), + .O(plm_frm_un1_reg_d2_td_0_sqmuxa_1_i) + ); + defparam plm_frm_delay_two_b_reg_d2_td_13_63_.INIT = 4'h1; + LUT2 plm_frm_delay_two_b_reg_d2_td_13_63_ ( + .I0(plm_frm_reg_d2_charisk37), + .I1(plm_frm_reg_d2_charisk_1_sqmuxa_820), + .O(plm_frm_reg_d2_td_13_63_) + ); + defparam plm_frm_un1_reg_d2_td_0_sqmuxa.INIT = 16'h9DBF; + LUT4 plm_frm_un1_reg_d2_td_0_sqmuxa ( + .I0(plm_frm_d1_end_h_796), + .I1(plm_frm_d1_start_h_795), + .I2(plm_frm_reg_d1_idleflag_hh_808), + .I3(plm_frm_reg_d1_idleflag_hl_809), + .O(plm_frm_un1_reg_d2_td_0_sqmuxa_i) + ); + defparam plm_frm_by1_opportunity_l.INIT = 16'h0080; + LUT4 plm_frm_by1_opportunity_l ( + .I0(plm_N_3508), + .I1(plm_frm_reg_d2_idle_l_815), + .I2(plm_sent_status[1]), + .I3(plm_un3_frm_clkcmp), + .O(plm_frm_by1_opportunity_l_791) + ); + defparam plm_frm_by1_opportunity_h.INIT = 16'h0080; + LUT4 plm_frm_by1_opportunity_h ( + .I0(plm_N_3508), + .I1(plm_frm_reg_d2_idle_h_813), + .I2(plm_sent_status[1]), + .I3(plm_un3_frm_clkcmp), + .O(plm_frm_by1_opportunity_h_792) + ); + defparam plm_frm_delay_one_reg_d1_idleflag_hh_3.INIT = 16'h8000; + LUT4_L plm_frm_delay_one_reg_d1_idleflag_hh_3 ( + .I0(plm_frm_reg_d1_idleflag_hh_3_0), + .I1(plm_frm_reg_d1_idleflag_hh_3_4), + .I2(plm_frm_reg_d0_td[60]), + .I3(plm_frm_reg_d0_td[61]), + .LO(plm_frm_reg_d1_idleflag_hh_3) + ); + defparam plm_frm_delay_one_reg_d1_idleflag_hl_3.INIT = 16'h8000; + LUT4_L plm_frm_delay_one_reg_d1_idleflag_hl_3 ( + .I0(plm_frm_reg_d1_idleflag_hl_3_0), + .I1(plm_frm_reg_d1_idleflag_hl_3_4), + .I2(plm_frm_reg_d0_td[36]), + .I3(plm_frm_reg_d0_td[37]), + .LO(plm_frm_reg_d1_idleflag_hl_3) + ); + defparam plm_frm_delay_one_reg_d1_idleflag_lh_3.INIT = 16'h8000; + LUT4_L plm_frm_delay_one_reg_d1_idleflag_lh_3 ( + .I0(plm_frm_reg_d1_idleflag_lh_3_0), + .I1(plm_frm_reg_d1_idleflag_lh_3_4), + .I2(plm_frm_reg_d0_td[28]), + .I3(plm_frm_reg_d0_td[29]), + .LO(plm_frm_reg_d1_idleflag_lh_3) + ); + defparam plm_frm_delay_one_reg_d1_idleflag_ll_3.INIT = 16'h8000; + LUT4_L plm_frm_delay_one_reg_d1_idleflag_ll_3 ( + .I0(plm_frm_reg_d1_idleflag_ll_3_0), + .I1(plm_frm_reg_d1_idleflag_ll_3_4), + .I2(plm_frm_reg_d0_td[4]), + .I3(plm_frm_reg_d0_td[5]), + .LO(plm_frm_reg_d1_idleflag_ll_3) + ); + defparam plm_frm_N_9970_i.INIT = 16'hFF80; + LUT4_L plm_frm_N_9970_i ( + .I0(plm_frm_d1_end_h_796), + .I1(plm_frm_reg_d1_idleflag_hl_809), + .I2(plm_frm_reg_d1_tctrl_h_799), + .I3(plm_frm_un1_d1_idle_h_793), + .LO(plm_frm_N_9970_i_812) + ); + defparam plm_frm_N_9969_i.INIT = 16'hFF80; + LUT4_L plm_frm_N_9969_i ( + .I0(plm_frm_d1_end_l_797), + .I1(plm_frm_reg_d1_idleflag_ll_811), + .I2(plm_frm_reg_d1_tctrl_l_801), + .I3(plm_frm_un1_d1_idle_l_794), + .LO(plm_frm_N_9969_i_814) + ); + defparam plm_frm_delay_two_b_N_8815_i.INIT = 16'h7350; + LUT4_L plm_frm_delay_two_b_N_8815_i ( + .I0(plm_frm_reg_d2_td_13_63_), + .I1(plm_frm_reg_d1_tctrl_l_801), + .I2(plm_frm_reg_d1_td[63]), + .I3(plm_frm_reg_d2_charisk_1_sqmuxa_1_818), + .LO(plm_frm_N_8815_i) + ); + defparam plm_frm_delay_two_b_reg_d2_td_13_1_f0_62_.INIT = 16'hF400; + LUT4_L plm_frm_delay_two_b_reg_d2_td_13_1_f0_62_ ( + .I0(plm_frm_d1_end_h_796), + .I1(plm_frm_d1_start_h_795), + .I2(plm_frm_reg_d1_td[62]), + .I3(plm_frm_un1_reg_d2_td_0_sqmuxa_i), + .LO(plm_frm_reg_d2_td_13_62_) + ); + defparam plm_frm_delay_two_b_N_8817_i.INIT = 16'h7350; + LUT4_L plm_frm_delay_two_b_N_8817_i ( + .I0(plm_frm_reg_d2_td_13_63_), + .I1(plm_frm_reg_d1_tctrl_l_801), + .I2(plm_frm_reg_d1_td[61]), + .I3(plm_frm_reg_d2_charisk_1_sqmuxa_1_818), + .LO(plm_frm_N_8817_i) + ); + defparam plm_frm_delay_two_b_reg_d2_td_13_1_f0_60_.INIT = 16'hF400; + LUT4_L plm_frm_delay_two_b_reg_d2_td_13_1_f0_60_ ( + .I0(plm_frm_d1_end_h_796), + .I1(plm_frm_d1_start_h_795), + .I2(plm_frm_reg_d1_td[60]), + .I3(plm_frm_un1_reg_d2_td_0_sqmuxa_i), + .LO(plm_frm_reg_d2_td_13_60_) + ); + defparam plm_frm_delay_two_b_reg_d2_td_13_1_f0_59_.INIT = 16'hF400; + LUT4_L plm_frm_delay_two_b_reg_d2_td_13_1_f0_59_ ( + .I0(plm_frm_d1_end_h_796), + .I1(plm_frm_d1_start_h_795), + .I2(plm_frm_reg_d1_td[59]), + .I3(plm_frm_un1_reg_d2_td_0_sqmuxa_i), + .LO(plm_frm_reg_d2_td_13_59_) + ); + defparam plm_frm_delay_two_b_N_8818_i.INIT = 16'hDC50; + LUT4_L plm_frm_delay_two_b_N_8818_i ( + .I0(plm_frm_reg_d2_td_13_63_), + .I1(plm_frm_reg_d1_tctrl_l_801), + .I2(plm_frm_reg_d1_td[58]), + .I3(plm_frm_reg_d2_charisk_1_sqmuxa_1_818), + .LO(plm_frm_N_8818_i) + ); + defparam plm_frm_delay_two_b_N_8819_i.INIT = 16'h7350; + LUT4_L plm_frm_delay_two_b_N_8819_i ( + .I0(plm_frm_reg_d2_td_13_63_), + .I1(plm_frm_reg_d1_tctrl_l_801), + .I2(plm_frm_reg_d1_td[57]), + .I3(plm_frm_reg_d2_charisk_1_sqmuxa_1_818), + .LO(plm_frm_N_8819_i) + ); + defparam plm_frm_delay_two_b_N_8820_i.INIT = 16'h7350; + LUT4_L plm_frm_delay_two_b_N_8820_i ( + .I0(plm_frm_reg_d2_td_13_63_), + .I1(plm_frm_reg_d1_tctrl_l_801), + .I2(plm_frm_reg_d1_td[56]), + .I3(plm_frm_reg_d2_charisk_1_sqmuxa_1_818), + .LO(plm_frm_N_8820_i) + ); + defparam plm_frm_delay_two_b_reg_d2_td_13_55_.INIT = 4'h8; + LUT2_L plm_frm_delay_two_b_reg_d2_td_13_55_ ( + .I0(plm_frm_reg_d1_td[55]), + .I1(plm_frm_un1_reg_d2_td_0_sqmuxa_i), + .LO(plm_frm_reg_d2_td_13_55_) + ); + defparam plm_frm_delay_two_b_reg_d2_td_13_54_.INIT = 4'h8; + LUT2_L plm_frm_delay_two_b_reg_d2_td_13_54_ ( + .I0(plm_frm_reg_d1_td[54]), + .I1(plm_frm_un1_reg_d2_td_0_sqmuxa_i), + .LO(plm_frm_reg_d2_td_13_54_) + ); + defparam plm_frm_delay_two_b_reg_d2_td_13_53_.INIT = 4'h8; + LUT2_L plm_frm_delay_two_b_reg_d2_td_13_53_ ( + .I0(plm_frm_reg_d1_td[53]), + .I1(plm_frm_un1_reg_d2_td_0_sqmuxa_i), + .LO(plm_frm_reg_d2_td_13_53_) + ); + defparam plm_frm_delay_two_b_reg_d2_td_13_52_.INIT = 4'h8; + LUT2_L plm_frm_delay_two_b_reg_d2_td_13_52_ ( + .I0(plm_frm_reg_d1_td[52]), + .I1(plm_frm_un1_reg_d2_td_0_sqmuxa_i), + .LO(plm_frm_reg_d2_td_13_52_) + ); + defparam plm_frm_delay_two_b_reg_d2_td_13_51_.INIT = 4'h8; + LUT2_L plm_frm_delay_two_b_reg_d2_td_13_51_ ( + .I0(plm_frm_reg_d1_td[51]), + .I1(plm_frm_un1_reg_d2_td_0_sqmuxa_i), + .LO(plm_frm_reg_d2_td_13_51_) + ); + defparam plm_frm_delay_two_b_reg_d2_td_13_50_.INIT = 4'h8; + LUT2_L plm_frm_delay_two_b_reg_d2_td_13_50_ ( + .I0(plm_frm_reg_d1_td[50]), + .I1(plm_frm_un1_reg_d2_td_0_sqmuxa_i), + .LO(plm_frm_reg_d2_td_13_50_) + ); + defparam plm_frm_delay_two_b_reg_d2_td_13_49_.INIT = 4'h8; + LUT2_L plm_frm_delay_two_b_reg_d2_td_13_49_ ( + .I0(plm_frm_reg_d1_td[49]), + .I1(plm_frm_un1_reg_d2_td_0_sqmuxa_i), + .LO(plm_frm_reg_d2_td_13_49_) + ); + defparam plm_frm_delay_two_b_reg_d2_td_13_48_.INIT = 4'h8; + LUT2_L plm_frm_delay_two_b_reg_d2_td_13_48_ ( + .I0(plm_frm_reg_d1_td[48]), + .I1(plm_frm_un1_reg_d2_td_0_sqmuxa_i), + .LO(plm_frm_reg_d2_td_13_48_) + ); + defparam plm_frm_delay_two_b_reg_d2_td_13_47_.INIT = 4'h8; + LUT2_L plm_frm_delay_two_b_reg_d2_td_13_47_ ( + .I0(plm_frm_reg_d1_td[47]), + .I1(plm_frm_un1_reg_d2_td_0_sqmuxa_i), + .LO(plm_frm_reg_d2_td_13_47_) + ); + defparam plm_frm_delay_two_b_reg_d2_td_13_46_.INIT = 4'h8; + LUT2_L plm_frm_delay_two_b_reg_d2_td_13_46_ ( + .I0(plm_frm_reg_d1_td[46]), + .I1(plm_frm_un1_reg_d2_td_0_sqmuxa_i), + .LO(plm_frm_reg_d2_td_13_46_) + ); + defparam plm_frm_delay_two_b_reg_d2_td_13_45_.INIT = 4'h8; + LUT2_L plm_frm_delay_two_b_reg_d2_td_13_45_ ( + .I0(plm_frm_reg_d1_td[45]), + .I1(plm_frm_un1_reg_d2_td_0_sqmuxa_i), + .LO(plm_frm_reg_d2_td_13_45_) + ); + defparam plm_frm_delay_two_b_reg_d2_td_13_44_.INIT = 4'h8; + LUT2_L plm_frm_delay_two_b_reg_d2_td_13_44_ ( + .I0(plm_frm_reg_d1_td[44]), + .I1(plm_frm_un1_reg_d2_td_0_sqmuxa_i), + .LO(plm_frm_reg_d2_td_13_44_) + ); + defparam plm_frm_delay_two_b_reg_d2_td_13_43_.INIT = 4'h8; + LUT2_L plm_frm_delay_two_b_reg_d2_td_13_43_ ( + .I0(plm_frm_reg_d1_td[43]), + .I1(plm_frm_un1_reg_d2_td_0_sqmuxa_i), + .LO(plm_frm_reg_d2_td_13_43_) + ); + defparam plm_frm_delay_two_b_reg_d2_td_13_42_.INIT = 4'h8; + LUT2_L plm_frm_delay_two_b_reg_d2_td_13_42_ ( + .I0(plm_frm_reg_d1_td[42]), + .I1(plm_frm_un1_reg_d2_td_0_sqmuxa_i), + .LO(plm_frm_reg_d2_td_13_42_) + ); + defparam plm_frm_delay_two_b_reg_d2_td_13_41_.INIT = 4'h8; + LUT2_L plm_frm_delay_two_b_reg_d2_td_13_41_ ( + .I0(plm_frm_reg_d1_td[41]), + .I1(plm_frm_un1_reg_d2_td_0_sqmuxa_i), + .LO(plm_frm_reg_d2_td_13_41_) + ); + defparam plm_frm_delay_two_b_reg_d2_td_13_40_.INIT = 4'h8; + LUT2_L plm_frm_delay_two_b_reg_d2_td_13_40_ ( + .I0(plm_frm_reg_d1_td[40]), + .I1(plm_frm_un1_reg_d2_td_0_sqmuxa_i), + .LO(plm_frm_reg_d2_td_13_40_) + ); + defparam plm_frm_delay_two_b_reg_d2_td_13_1_f0_39_.INIT = 16'hF200; + LUT4_L plm_frm_delay_two_b_reg_d2_td_13_1_f0_39_ ( + .I0(plm_frm_d1_end_h_796), + .I1(plm_frm_d1_start_h_795), + .I2(plm_frm_reg_d1_td[39]), + .I3(plm_frm_un1_reg_d2_td_0_sqmuxa_i), + .LO(plm_frm_reg_d2_td_13_39_) + ); + defparam plm_frm_delay_two_b_reg_d2_td_13_1_f0_38_.INIT = 16'hF200; + LUT4_L plm_frm_delay_two_b_reg_d2_td_13_1_f0_38_ ( + .I0(plm_frm_d1_end_h_796), + .I1(plm_frm_d1_start_h_795), + .I2(plm_frm_reg_d1_td[38]), + .I3(plm_frm_un1_reg_d2_td_0_sqmuxa_i), + .LO(plm_frm_reg_d2_td_13_38_) + ); + defparam plm_frm_delay_two_b_reg_d2_td_13_1_f0_37_.INIT = 16'hF200; + LUT4_L plm_frm_delay_two_b_reg_d2_td_13_1_f0_37_ ( + .I0(plm_frm_d1_end_h_796), + .I1(plm_frm_d1_start_h_795), + .I2(plm_frm_reg_d1_td[37]), + .I3(plm_frm_un1_reg_d2_td_0_sqmuxa_i), + .LO(plm_frm_reg_d2_td_13_37_) + ); + defparam plm_frm_delay_two_b_reg_d2_td_13_1_f0_36_.INIT = 16'hF200; + LUT4_L plm_frm_delay_two_b_reg_d2_td_13_1_f0_36_ ( + .I0(plm_frm_d1_end_h_796), + .I1(plm_frm_d1_start_h_795), + .I2(plm_frm_reg_d1_td[36]), + .I3(plm_frm_un1_reg_d2_td_0_sqmuxa_i), + .LO(plm_frm_reg_d2_td_13_36_) + ); + defparam plm_frm_delay_two_b_reg_d2_td_13_1_f0_35_.INIT = 16'hF200; + LUT4_L plm_frm_delay_two_b_reg_d2_td_13_1_f0_35_ ( + .I0(plm_frm_d1_end_h_796), + .I1(plm_frm_d1_start_h_795), + .I2(plm_frm_reg_d1_td[35]), + .I3(plm_frm_un1_reg_d2_td_0_sqmuxa_i), + .LO(plm_frm_reg_d2_td_13_35_) + ); + defparam plm_frm_delay_two_b_reg_d2_td_13_1_f0_34_.INIT = 16'hF200; + LUT4_L plm_frm_delay_two_b_reg_d2_td_13_1_f0_34_ ( + .I0(plm_frm_d1_end_h_796), + .I1(plm_frm_d1_start_h_795), + .I2(plm_frm_reg_d1_td[34]), + .I3(plm_frm_un1_reg_d2_td_0_sqmuxa_i), + .LO(plm_frm_reg_d2_td_13_34_) + ); + defparam plm_frm_reg_d1_td_m_33_.INIT = 8'hC8; + LUT3_L plm_frm_reg_d1_td_m_33_ ( + .I0(plm_frm_reg_d2_charisk37), + .I1(plm_frm_reg_d1_td[33]), + .I2(plm_frm_reg_d2_charisk_1_sqmuxa_1_818), + .LO(plm_frm_N_8821_i_0) + ); + defparam plm_frm_delay_two_b_N_8823_i.INIT = 16'hFCF8; + LUT4_L plm_frm_delay_two_b_N_8823_i ( + .I0(plm_frm_reg_d2_charisk37), + .I1(plm_frm_reg_d1_td[32]), + .I2(plm_frm_reg_d2_charisk_1_sqmuxa_820), + .I3(plm_frm_reg_d2_charisk_1_sqmuxa_1_818), + .LO(plm_frm_N_8823_i) + ); + defparam plm_frm_delay_two_b_N_8806_i.INIT = 16'h7350; + LUT4_L plm_frm_delay_two_b_N_8806_i ( + .I0(plm_frm_N_8807), + .I1(plm_frm_reg_d1_tctrl_l_801), + .I2(plm_frm_reg_d1_td[31]), + .I3(plm_frm_reg_d2_charisk_1_sqmuxa_3_822), + .LO(plm_frm_N_8806_i) + ); + defparam plm_frm_delay_two_b_reg_d2_td_24_1_f0_30_.INIT = 16'hF200; + LUT4_L plm_frm_delay_two_b_reg_d2_td_24_1_f0_30_ ( + .I0(plm_frm_d1_end_h_796), + .I1(plm_frm_d1_end_l_797), + .I2(plm_frm_reg_d1_td[30]), + .I3(plm_frm_un1_reg_d2_td_0_sqmuxa_1_i), + .LO(plm_frm_reg_d2_td_24_30_) + ); + defparam plm_frm_delay_two_b_N_8808_i.INIT = 16'h7350; + LUT4_L plm_frm_delay_two_b_N_8808_i ( + .I0(plm_frm_N_8807), + .I1(plm_frm_reg_d1_tctrl_l_801), + .I2(plm_frm_reg_d1_td[29]), + .I3(plm_frm_reg_d2_charisk_1_sqmuxa_3_822), + .LO(plm_frm_N_8808_i) + ); + defparam plm_frm_delay_two_b_reg_d2_td_24_1_f0_28_.INIT = 16'hF200; + LUT4_L plm_frm_delay_two_b_reg_d2_td_24_1_f0_28_ ( + .I0(plm_frm_d1_end_h_796), + .I1(plm_frm_d1_end_l_797), + .I2(plm_frm_reg_d1_td[28]), + .I3(plm_frm_un1_reg_d2_td_0_sqmuxa_1_i), + .LO(plm_frm_reg_d2_td_24_28_) + ); + defparam plm_frm_delay_two_b_reg_d2_td_24_1_f0_27_.INIT = 16'hF200; + LUT4_L plm_frm_delay_two_b_reg_d2_td_24_1_f0_27_ ( + .I0(plm_frm_d1_end_h_796), + .I1(plm_frm_d1_end_l_797), + .I2(plm_frm_reg_d1_td[27]), + .I3(plm_frm_un1_reg_d2_td_0_sqmuxa_1_i), + .LO(plm_frm_reg_d2_td_24_27_) + ); + defparam plm_frm_delay_two_b_N_8809_i.INIT = 16'hDC50; + LUT4_L plm_frm_delay_two_b_N_8809_i ( + .I0(plm_frm_N_8807), + .I1(plm_frm_reg_d1_tctrl_l_801), + .I2(plm_frm_reg_d1_td[26]), + .I3(plm_frm_reg_d2_charisk_1_sqmuxa_3_822), + .LO(plm_frm_N_8809_i) + ); + defparam plm_frm_delay_two_b_N_8810_i.INIT = 16'h7350; + LUT4_L plm_frm_delay_two_b_N_8810_i ( + .I0(plm_frm_N_8807), + .I1(plm_frm_reg_d1_tctrl_l_801), + .I2(plm_frm_reg_d1_td[25]), + .I3(plm_frm_reg_d2_charisk_1_sqmuxa_3_822), + .LO(plm_frm_N_8810_i) + ); + defparam plm_frm_delay_two_b_N_8811_i.INIT = 16'h7350; + LUT4_L plm_frm_delay_two_b_N_8811_i ( + .I0(plm_frm_N_8807), + .I1(plm_frm_reg_d1_tctrl_l_801), + .I2(plm_frm_reg_d1_td[24]), + .I3(plm_frm_reg_d2_charisk_1_sqmuxa_3_822), + .LO(plm_frm_N_8811_i) + ); + defparam plm_frm_delay_two_b_reg_d2_td_24_23_.INIT = 4'h8; + LUT2_L plm_frm_delay_two_b_reg_d2_td_24_23_ ( + .I0(plm_frm_reg_d1_td[23]), + .I1(plm_frm_un1_reg_d2_td_0_sqmuxa_1_i), + .LO(plm_frm_reg_d2_td_24_23_) + ); + defparam plm_frm_delay_two_b_reg_d2_td_24_22_.INIT = 4'h8; + LUT2_L plm_frm_delay_two_b_reg_d2_td_24_22_ ( + .I0(plm_frm_reg_d1_td[22]), + .I1(plm_frm_un1_reg_d2_td_0_sqmuxa_1_i), + .LO(plm_frm_reg_d2_td_24_22_) + ); + defparam plm_frm_delay_two_b_reg_d2_td_24_21_.INIT = 4'h8; + LUT2_L plm_frm_delay_two_b_reg_d2_td_24_21_ ( + .I0(plm_frm_reg_d1_td[21]), + .I1(plm_frm_un1_reg_d2_td_0_sqmuxa_1_i), + .LO(plm_frm_reg_d2_td_24_21_) + ); + defparam plm_frm_delay_two_b_reg_d2_td_24_20_.INIT = 4'h8; + LUT2_L plm_frm_delay_two_b_reg_d2_td_24_20_ ( + .I0(plm_frm_reg_d1_td[20]), + .I1(plm_frm_un1_reg_d2_td_0_sqmuxa_1_i), + .LO(plm_frm_reg_d2_td_24_20_) + ); + defparam plm_frm_delay_two_b_reg_d2_td_24_19_.INIT = 4'h8; + LUT2_L plm_frm_delay_two_b_reg_d2_td_24_19_ ( + .I0(plm_frm_reg_d1_td[19]), + .I1(plm_frm_un1_reg_d2_td_0_sqmuxa_1_i), + .LO(plm_frm_reg_d2_td_24_19_) + ); + defparam plm_frm_delay_two_b_reg_d2_td_24_18_.INIT = 4'h8; + LUT2_L plm_frm_delay_two_b_reg_d2_td_24_18_ ( + .I0(plm_frm_reg_d1_td[18]), + .I1(plm_frm_un1_reg_d2_td_0_sqmuxa_1_i), + .LO(plm_frm_reg_d2_td_24_18_) + ); + defparam plm_frm_delay_two_b_reg_d2_td_24_17_.INIT = 4'h8; + LUT2_L plm_frm_delay_two_b_reg_d2_td_24_17_ ( + .I0(plm_frm_reg_d1_td[17]), + .I1(plm_frm_un1_reg_d2_td_0_sqmuxa_1_i), + .LO(plm_frm_reg_d2_td_24_17_) + ); + defparam plm_frm_delay_two_b_reg_d2_td_24_16_.INIT = 4'h8; + LUT2_L plm_frm_delay_two_b_reg_d2_td_24_16_ ( + .I0(plm_frm_reg_d1_td[16]), + .I1(plm_frm_un1_reg_d2_td_0_sqmuxa_1_i), + .LO(plm_frm_reg_d2_td_24_16_) + ); + defparam plm_frm_delay_two_b_reg_d2_td_24_15_.INIT = 4'h8; + LUT2_L plm_frm_delay_two_b_reg_d2_td_24_15_ ( + .I0(plm_frm_reg_d1_td[15]), + .I1(plm_frm_un1_reg_d2_td_0_sqmuxa_1_i), + .LO(plm_frm_reg_d2_td_24_15_) + ); + defparam plm_frm_delay_two_b_reg_d2_td_24_14_.INIT = 4'h8; + LUT2_L plm_frm_delay_two_b_reg_d2_td_24_14_ ( + .I0(plm_frm_reg_d1_td[14]), + .I1(plm_frm_un1_reg_d2_td_0_sqmuxa_1_i), + .LO(plm_frm_reg_d2_td_24_14_) + ); + defparam plm_frm_delay_two_b_reg_d2_td_24_13_.INIT = 4'h8; + LUT2_L plm_frm_delay_two_b_reg_d2_td_24_13_ ( + .I0(plm_frm_reg_d1_td[13]), + .I1(plm_frm_un1_reg_d2_td_0_sqmuxa_1_i), + .LO(plm_frm_reg_d2_td_24_13_) + ); + defparam plm_frm_delay_two_b_reg_d2_td_24_12_.INIT = 4'h8; + LUT2_L plm_frm_delay_two_b_reg_d2_td_24_12_ ( + .I0(plm_frm_reg_d1_td[12]), + .I1(plm_frm_un1_reg_d2_td_0_sqmuxa_1_i), + .LO(plm_frm_reg_d2_td_24_12_) + ); + defparam plm_frm_delay_two_b_reg_d2_td_24_11_.INIT = 4'h8; + LUT2_L plm_frm_delay_two_b_reg_d2_td_24_11_ ( + .I0(plm_frm_reg_d1_td[11]), + .I1(plm_frm_un1_reg_d2_td_0_sqmuxa_1_i), + .LO(plm_frm_reg_d2_td_24_11_) + ); + defparam plm_frm_delay_two_b_reg_d2_td_24_10_.INIT = 4'h8; + LUT2_L plm_frm_delay_two_b_reg_d2_td_24_10_ ( + .I0(plm_frm_reg_d1_td[10]), + .I1(plm_frm_un1_reg_d2_td_0_sqmuxa_1_i), + .LO(plm_frm_reg_d2_td_24_10_) + ); + defparam plm_frm_delay_two_b_reg_d2_td_24_9_.INIT = 4'h8; + LUT2_L plm_frm_delay_two_b_reg_d2_td_24_9_ ( + .I0(plm_frm_reg_d1_td[9]), + .I1(plm_frm_un1_reg_d2_td_0_sqmuxa_1_i), + .LO(plm_frm_reg_d2_td_24_9_) + ); + defparam plm_frm_delay_two_b_reg_d2_td_24_8_.INIT = 4'h8; + LUT2_L plm_frm_delay_two_b_reg_d2_td_24_8_ ( + .I0(plm_frm_reg_d1_td[8]), + .I1(plm_frm_un1_reg_d2_td_0_sqmuxa_1_i), + .LO(plm_frm_reg_d2_td_24_8_) + ); + defparam plm_frm_delay_two_b_reg_d2_td_24_1_f0_7_.INIT = 16'hF400; + LUT4_L plm_frm_delay_two_b_reg_d2_td_24_1_f0_7_ ( + .I0(plm_frm_d1_end_h_796), + .I1(plm_frm_d1_end_l_797), + .I2(plm_frm_reg_d1_td[7]), + .I3(plm_frm_un1_reg_d2_td_0_sqmuxa_1_i), + .LO(plm_frm_reg_d2_td_24_7_) + ); + defparam plm_frm_delay_two_b_reg_d2_td_24_1_f0_6_.INIT = 16'hF400; + LUT4_L plm_frm_delay_two_b_reg_d2_td_24_1_f0_6_ ( + .I0(plm_frm_d1_end_h_796), + .I1(plm_frm_d1_end_l_797), + .I2(plm_frm_reg_d1_td[6]), + .I3(plm_frm_un1_reg_d2_td_0_sqmuxa_1_i), + .LO(plm_frm_reg_d2_td_24_6_) + ); + defparam plm_frm_delay_two_b_reg_d2_td_24_1_f0_5_.INIT = 16'hF400; + LUT4_L plm_frm_delay_two_b_reg_d2_td_24_1_f0_5_ ( + .I0(plm_frm_d1_end_h_796), + .I1(plm_frm_d1_end_l_797), + .I2(plm_frm_reg_d1_td[5]), + .I3(plm_frm_un1_reg_d2_td_0_sqmuxa_1_i), + .LO(plm_frm_reg_d2_td_24_5_) + ); + defparam plm_frm_delay_two_b_reg_d2_td_24_1_f0_4_.INIT = 16'hF400; + LUT4_L plm_frm_delay_two_b_reg_d2_td_24_1_f0_4_ ( + .I0(plm_frm_d1_end_h_796), + .I1(plm_frm_d1_end_l_797), + .I2(plm_frm_reg_d1_td[4]), + .I3(plm_frm_un1_reg_d2_td_0_sqmuxa_1_i), + .LO(plm_frm_reg_d2_td_24_4_) + ); + defparam plm_frm_delay_two_b_reg_d2_td_24_1_f0_3_.INIT = 16'hF400; + LUT4_L plm_frm_delay_two_b_reg_d2_td_24_1_f0_3_ ( + .I0(plm_frm_d1_end_h_796), + .I1(plm_frm_d1_end_l_797), + .I2(plm_frm_reg_d1_td[3]), + .I3(plm_frm_un1_reg_d2_td_0_sqmuxa_1_i), + .LO(plm_frm_reg_d2_td_24_3_) + ); + defparam plm_frm_delay_two_b_reg_d2_td_24_1_f0_2_.INIT = 16'hF400; + LUT4_L plm_frm_delay_two_b_reg_d2_td_24_1_f0_2_ ( + .I0(plm_frm_d1_end_h_796), + .I1(plm_frm_d1_end_l_797), + .I2(plm_frm_reg_d1_td[2]), + .I3(plm_frm_un1_reg_d2_td_0_sqmuxa_1_i), + .LO(plm_frm_reg_d2_td_24_2_) + ); + defparam plm_frm_reg_d1_td_m_1_.INIT = 8'hC8; + LUT3_L plm_frm_reg_d1_td_m_1_ ( + .I0(plm_frm_reg_d2_charisk69), + .I1(plm_frm_reg_d1_td[1]), + .I2(plm_frm_reg_d2_charisk_1_sqmuxa_3_822), + .LO(plm_frm_N_8812_i_0) + ); + defparam plm_frm_delay_two_b_N_8814_i.INIT = 16'hFCF8; + LUT4_L plm_frm_delay_two_b_N_8814_i ( + .I0(plm_frm_reg_d2_charisk69), + .I1(plm_frm_reg_d1_td[0]), + .I2(plm_frm_reg_d2_charisk_1_sqmuxa_2_816), + .I3(plm_frm_reg_d2_charisk_1_sqmuxa_3_822), + .LO(plm_frm_N_8814_i) + ); + defparam plm_frm_delay_two_b_reg_d2_charisk37.INIT = 8'h41; + LUT3 plm_frm_delay_two_b_reg_d2_charisk37 ( + .I0(plm_frm_d1_end_h_796), + .I1(plm_frm_reg_d2_tframe_h_805), + .I2(plm_frm_reg_d1_tframe_h_804), + .O(plm_frm_reg_d2_charisk37) + ); + defparam plm_frm_delay_two_b_reg_d2_charisk69.INIT = 8'h41; + LUT3 plm_frm_delay_two_b_reg_d2_charisk69 ( + .I0(plm_frm_d1_end_l_797), + .I1(plm_frm_reg_d2_tframe_l_807), + .I2(plm_frm_reg_d1_tframe_l_806), + .O(plm_frm_reg_d2_charisk69) + ); + FDC plm_frm_reg_frm_atomic ( + .C(mgt_clk), + .D(plm_frm_by1_frm_atomic), + .Q(plm_frm_atomic), + .CLR(plm_rst) + ); + FDC plm_frm_reg_frm0_char_9_ ( + .C(mgt_clk), + .D(plm_frm_by1_frm0_char_9_), + .Q(plm_frm0_char[9]), + .CLR(plm_rst) + ); + FDC plm_frm_reg_frm0_char_8_ ( + .C(mgt_clk), + .D(plm_frm_by1_frm0_char_8_), + .Q(plm_frm0_char[8]), + .CLR(plm_rst) + ); + FDC plm_frm_reg_frm0_char_7_ ( + .C(mgt_clk), + .D(plm_frm_by1_frm0_char_7_), + .Q(plm_frm0_char[7]), + .CLR(plm_rst) + ); + FDC plm_frm_reg_frm0_char_6_ ( + .C(mgt_clk), + .D(plm_frm_by1_frm0_char_6_), + .Q(plm_frm0_char[6]), + .CLR(plm_rst) + ); + FDC plm_frm_reg_frm0_char_5_ ( + .C(mgt_clk), + .D(plm_frm_by1_frm0_char_5_), + .Q(plm_frm0_char[5]), + .CLR(plm_rst) + ); + FDC plm_frm_reg_frm0_char_4_ ( + .C(mgt_clk), + .D(plm_frm_N_8665_i), + .Q(plm_frm0_char[4]), + .CLR(plm_rst) + ); + FDC plm_frm_reg_frm0_char_3_ ( + .C(mgt_clk), + .D(plm_frm_N_8666_i), + .Q(plm_frm0_char[3]), + .CLR(plm_rst) + ); + FDC plm_frm_reg_frm0_char_2_ ( + .C(mgt_clk), + .D(plm_frm_N_8667_i), + .Q(plm_frm0_char[2]), + .CLR(plm_rst) + ); + FDC plm_frm_reg_frm0_char_1_ ( + .C(mgt_clk), + .D(plm_frm_by1_frm0_char_1_), + .Q(plm_frm0_char[1]), + .CLR(plm_rst) + ); + FDC plm_frm_reg_frm0_char_0_ ( + .C(mgt_clk), + .D(plm_frm_by1_frm0_char_0_), + .Q(plm_frm0_char[0]), + .CLR(plm_rst) + ); + FDC plm_frm_reg_frm0_is_k_1_ ( + .C(mgt_clk), + .D(plm_frm_by1_frm0_is_k[1]), + .Q(plm_frm0_is_k[1]), + .CLR(plm_rst) + ); + FDC plm_frm_reg_frm0_is_k_0_ ( + .C(mgt_clk), + .D(plm_frm_by1_frm0_is_k[0]), + .Q(plm_frm0_is_k[0]), + .CLR(plm_rst) + ); + FDC plm_frm_reg_frm0_char_15_ ( + .C(mgt_clk), + .D(plm_frm_by1_frm0_char_15_), + .Q(plm_frm0_char[15]), + .CLR(plm_rst) + ); + FDC plm_frm_reg_frm0_char_14_ ( + .C(mgt_clk), + .D(plm_frm_by1_frm0_char_14_), + .Q(plm_frm0_char[14]), + .CLR(plm_rst) + ); + FDC plm_frm_reg_frm0_char_13_ ( + .C(mgt_clk), + .D(plm_frm_by1_frm0_char_13_), + .Q(plm_frm0_char[13]), + .CLR(plm_rst) + ); + FDC plm_frm_reg_frm0_char_12_ ( + .C(mgt_clk), + .D(plm_frm_by1_frm0_char_12_), + .Q(plm_frm0_char[12]), + .CLR(plm_rst) + ); + FDC plm_frm_reg_frm0_char_11_ ( + .C(mgt_clk), + .D(plm_frm_by1_frm0_char_11_), + .Q(plm_frm0_char[11]), + .CLR(plm_rst) + ); + FDC plm_frm_reg_frm0_char_10_ ( + .C(mgt_clk), + .D(plm_frm_by1_frm0_char_10_), + .Q(plm_frm0_char[10]), + .CLR(plm_rst) + ); + FDCE plm_frm_reg_d0_tctrl_h ( + .CE(plm_phy_cke_1_401), + .C(mgt_clk), + .D(phy_tctrl_h), + .Q(plm_frm_reg_d0_tctrl_h_798), + .CLR(plm_rst) + ); + FDCE plm_frm_reg_d0_tctrl_l ( + .CE(plm_phy_cke_1_401), + .C(mgt_clk), + .D(phy_tctrl_l), + .Q(plm_frm_reg_d0_tctrl_l_800), + .CLR(plm_rst) + ); + FDCE plm_frm_reg_d0_tframe_h ( + .CE(plm_phy_cke_2_400), + .C(mgt_clk), + .D(phy_tframe_h), + .Q(plm_frm_reg_d0_tframe_h_802), + .CLR(plm_rst) + ); + FDCE plm_frm_reg_d0_tframe_l ( + .CE(plm_phy_cke_2_400), + .C(mgt_clk), + .D(phy_tframe_l), + .Q(plm_frm_reg_d0_tframe_l_803), + .CLR(plm_rst) + ); + FDCE plm_frm_reg_d0_td_63_ ( + .CE(plm_phy_cke_2_400), + .C(mgt_clk), + .D(phy_td[63]), + .Q(plm_frm_reg_d0_td[63]), + .CLR(plm_rst) + ); + FDCE plm_frm_reg_d0_td_62_ ( + .CE(plm_phy_cke_2_400), + .C(mgt_clk), + .D(phy_td[62]), + .Q(plm_frm_reg_d0_td[62]), + .CLR(plm_rst) + ); + FDCE plm_frm_reg_d0_td_61_ ( + .CE(plm_phy_cke_2_400), + .C(mgt_clk), + .D(phy_td[61]), + .Q(plm_frm_reg_d0_td[61]), + .CLR(plm_rst) + ); + FDCE plm_frm_reg_d0_td_60_ ( + .CE(plm_phy_cke_2_400), + .C(mgt_clk), + .D(phy_td[60]), + .Q(plm_frm_reg_d0_td[60]), + .CLR(plm_rst) + ); + FDCE plm_frm_reg_d0_td_59_ ( + .CE(plm_phy_cke_2_400), + .C(mgt_clk), + .D(phy_td[59]), + .Q(plm_frm_reg_d0_td[59]), + .CLR(plm_rst) + ); + FDCE plm_frm_reg_d0_td_58_ ( + .CE(plm_phy_cke_2_400), + .C(mgt_clk), + .D(phy_td[58]), + .Q(plm_frm_reg_d0_td[58]), + .CLR(plm_rst) + ); + FDCE plm_frm_reg_d0_td_57_ ( + .CE(plm_phy_cke_2_400), + .C(mgt_clk), + .D(phy_td[57]), + .Q(plm_frm_reg_d0_td[57]), + .CLR(plm_rst) + ); + FDCE plm_frm_reg_d0_td_56_ ( + .CE(plm_phy_cke_2_400), + .C(mgt_clk), + .D(phy_td[56]), + .Q(plm_frm_reg_d0_td[56]), + .CLR(plm_rst) + ); + FDCE plm_frm_reg_d0_td_55_ ( + .CE(plm_phy_cke_2_400), + .C(mgt_clk), + .D(phy_td[55]), + .Q(plm_frm_reg_d0_td[55]), + .CLR(plm_rst) + ); + FDCE plm_frm_reg_d0_td_54_ ( + .CE(plm_phy_cke_2_400), + .C(mgt_clk), + .D(phy_td[54]), + .Q(plm_frm_reg_d0_td[54]), + .CLR(plm_rst) + ); + FDCE plm_frm_reg_d0_td_53_ ( + .CE(plm_phy_cke_2_400), + .C(mgt_clk), + .D(phy_td[53]), + .Q(plm_frm_reg_d0_td[53]), + .CLR(plm_rst) + ); + FDCE plm_frm_reg_d0_td_52_ ( + .CE(plm_phy_cke_2_400), + .C(mgt_clk), + .D(phy_td[52]), + .Q(plm_frm_reg_d0_td[52]), + .CLR(plm_rst) + ); + FDCE plm_frm_reg_d0_td_51_ ( + .CE(plm_phy_cke_2_400), + .C(mgt_clk), + .D(phy_td[51]), + .Q(plm_frm_reg_d0_td[51]), + .CLR(plm_rst) + ); + FDCE plm_frm_reg_d0_td_50_ ( + .CE(plm_phy_cke_2_400), + .C(mgt_clk), + .D(phy_td[50]), + .Q(plm_frm_reg_d0_td[50]), + .CLR(plm_rst) + ); + FDCE plm_frm_reg_d0_td_49_ ( + .CE(plm_phy_cke_2_400), + .C(mgt_clk), + .D(phy_td[49]), + .Q(plm_frm_reg_d0_td[49]), + .CLR(plm_rst) + ); + FDCE plm_frm_reg_d0_td_48_ ( + .CE(plm_phy_cke_2_400), + .C(mgt_clk), + .D(phy_td[48]), + .Q(plm_frm_reg_d0_td[48]), + .CLR(plm_rst) + ); + FDCE plm_frm_reg_d0_td_47_ ( + .CE(plm_phy_cke_1_401), + .C(mgt_clk), + .D(phy_td[47]), + .Q(plm_frm_reg_d0_td[47]), + .CLR(plm_rst) + ); + FDCE plm_frm_reg_d0_td_46_ ( + .CE(plm_phy_cke_1_401), + .C(mgt_clk), + .D(phy_td[46]), + .Q(plm_frm_reg_d0_td[46]), + .CLR(plm_rst) + ); + FDCE plm_frm_reg_d0_td_45_ ( + .CE(plm_phy_cke_1_401), + .C(mgt_clk), + .D(phy_td[45]), + .Q(plm_frm_reg_d0_td[45]), + .CLR(plm_rst) + ); + FDCE plm_frm_reg_d0_td_44_ ( + .CE(plm_phy_cke_1_401), + .C(mgt_clk), + .D(phy_td[44]), + .Q(plm_frm_reg_d0_td[44]), + .CLR(plm_rst) + ); + FDCE plm_frm_reg_d0_td_43_ ( + .CE(plm_phy_cke_1_401), + .C(mgt_clk), + .D(phy_td[43]), + .Q(plm_frm_reg_d0_td[43]), + .CLR(plm_rst) + ); + FDCE plm_frm_reg_d0_td_42_ ( + .CE(plm_phy_cke_1_401), + .C(mgt_clk), + .D(phy_td[42]), + .Q(plm_frm_reg_d0_td[42]), + .CLR(plm_rst) + ); + FDCE plm_frm_reg_d0_td_41_ ( + .CE(plm_phy_cke_1_401), + .C(mgt_clk), + .D(phy_td[41]), + .Q(plm_frm_reg_d0_td[41]), + .CLR(plm_rst) + ); + FDCE plm_frm_reg_d0_td_40_ ( + .CE(plm_phy_cke_1_401), + .C(mgt_clk), + .D(phy_td[40]), + .Q(plm_frm_reg_d0_td[40]), + .CLR(plm_rst) + ); + FDCE plm_frm_reg_d0_td_39_ ( + .CE(plm_phy_cke_1_401), + .C(mgt_clk), + .D(phy_td[39]), + .Q(plm_frm_reg_d0_td[39]), + .CLR(plm_rst) + ); + FDCE plm_frm_reg_d0_td_38_ ( + .CE(plm_phy_cke_1_401), + .C(mgt_clk), + .D(phy_td[38]), + .Q(plm_frm_reg_d0_td[38]), + .CLR(plm_rst) + ); + FDCE plm_frm_reg_d0_td_37_ ( + .CE(plm_phy_cke_1_401), + .C(mgt_clk), + .D(phy_td[37]), + .Q(plm_frm_reg_d0_td[37]), + .CLR(plm_rst) + ); + FDCE plm_frm_reg_d0_td_36_ ( + .CE(plm_phy_cke_1_401), + .C(mgt_clk), + .D(phy_td[36]), + .Q(plm_frm_reg_d0_td[36]), + .CLR(plm_rst) + ); + FDCE plm_frm_reg_d0_td_35_ ( + .CE(plm_phy_cke_1_401), + .C(mgt_clk), + .D(phy_td[35]), + .Q(plm_frm_reg_d0_td[35]), + .CLR(plm_rst) + ); + FDCE plm_frm_reg_d0_td_34_ ( + .CE(plm_phy_cke_1_401), + .C(mgt_clk), + .D(phy_td[34]), + .Q(plm_frm_reg_d0_td[34]), + .CLR(plm_rst) + ); + FDCE plm_frm_reg_d0_td_33_ ( + .CE(plm_phy_cke_1_401), + .C(mgt_clk), + .D(phy_td[33]), + .Q(plm_frm_reg_d0_td[33]), + .CLR(plm_rst) + ); + FDCE plm_frm_reg_d0_td_32_ ( + .CE(plm_phy_cke_1_401), + .C(mgt_clk), + .D(phy_td[32]), + .Q(plm_frm_reg_d0_td[32]), + .CLR(plm_rst) + ); + FDCE plm_frm_reg_d0_td_31_ ( + .CE(plm_phy_cke_1_401), + .C(mgt_clk), + .D(phy_td[31]), + .Q(plm_frm_reg_d0_td[31]), + .CLR(plm_rst) + ); + FDCE plm_frm_reg_d0_td_30_ ( + .CE(plm_phy_cke_1_401), + .C(mgt_clk), + .D(phy_td[30]), + .Q(plm_frm_reg_d0_td[30]), + .CLR(plm_rst) + ); + FDCE plm_frm_reg_d0_td_29_ ( + .CE(plm_phy_cke_1_401), + .C(mgt_clk), + .D(phy_td[29]), + .Q(plm_frm_reg_d0_td[29]), + .CLR(plm_rst) + ); + FDCE plm_frm_reg_d0_td_28_ ( + .CE(plm_phy_cke_1_401), + .C(mgt_clk), + .D(phy_td[28]), + .Q(plm_frm_reg_d0_td[28]), + .CLR(plm_rst) + ); + FDCE plm_frm_reg_d0_td_27_ ( + .CE(plm_phy_cke_1_401), + .C(mgt_clk), + .D(phy_td[27]), + .Q(plm_frm_reg_d0_td[27]), + .CLR(plm_rst) + ); + FDCE plm_frm_reg_d0_td_26_ ( + .CE(plm_phy_cke_1_401), + .C(mgt_clk), + .D(phy_td[26]), + .Q(plm_frm_reg_d0_td[26]), + .CLR(plm_rst) + ); + FDCE plm_frm_reg_d0_td_25_ ( + .CE(plm_phy_cke_1_401), + .C(mgt_clk), + .D(phy_td[25]), + .Q(plm_frm_reg_d0_td[25]), + .CLR(plm_rst) + ); + FDCE plm_frm_reg_d0_td_24_ ( + .CE(plm_phy_cke_1_401), + .C(mgt_clk), + .D(phy_td[24]), + .Q(plm_frm_reg_d0_td[24]), + .CLR(plm_rst) + ); + FDCE plm_frm_reg_d0_td_23_ ( + .CE(plm_phy_cke_1_401), + .C(mgt_clk), + .D(phy_td[23]), + .Q(plm_frm_reg_d0_td[23]), + .CLR(plm_rst) + ); + FDCE plm_frm_reg_d0_td_22_ ( + .CE(plm_phy_cke_1_401), + .C(mgt_clk), + .D(phy_td[22]), + .Q(plm_frm_reg_d0_td[22]), + .CLR(plm_rst) + ); + FDCE plm_frm_reg_d0_td_21_ ( + .CE(plm_phy_cke_1_401), + .C(mgt_clk), + .D(phy_td[21]), + .Q(plm_frm_reg_d0_td[21]), + .CLR(plm_rst) + ); + FDCE plm_frm_reg_d0_td_20_ ( + .CE(plm_phy_cke_1_401), + .C(mgt_clk), + .D(phy_td[20]), + .Q(plm_frm_reg_d0_td[20]), + .CLR(plm_rst) + ); + FDCE plm_frm_reg_d0_td_19_ ( + .CE(plm_phy_cke_1_401), + .C(mgt_clk), + .D(phy_td[19]), + .Q(plm_frm_reg_d0_td[19]), + .CLR(plm_rst) + ); + FDCE plm_frm_reg_d0_td_18_ ( + .CE(plm_phy_cke_1_401), + .C(mgt_clk), + .D(phy_td[18]), + .Q(plm_frm_reg_d0_td[18]), + .CLR(plm_rst) + ); + FDCE plm_frm_reg_d0_td_17_ ( + .CE(plm_phy_cke_1_401), + .C(mgt_clk), + .D(phy_td[17]), + .Q(plm_frm_reg_d0_td[17]), + .CLR(plm_rst) + ); + FDCE plm_frm_reg_d0_td_16_ ( + .CE(plm_phy_cke_1_401), + .C(mgt_clk), + .D(phy_td[16]), + .Q(plm_frm_reg_d0_td[16]), + .CLR(plm_rst) + ); + FDCE plm_frm_reg_d0_td_15_ ( + .CE(plm_phy_cke_1_401), + .C(mgt_clk), + .D(phy_td[15]), + .Q(plm_frm_reg_d0_td[15]), + .CLR(plm_rst) + ); + FDCE plm_frm_reg_d0_td_14_ ( + .CE(plm_phy_cke_1_401), + .C(mgt_clk), + .D(phy_td[14]), + .Q(plm_frm_reg_d0_td[14]), + .CLR(plm_rst) + ); + FDCE plm_frm_reg_d0_td_13_ ( + .CE(plm_phy_cke_1_401), + .C(mgt_clk), + .D(phy_td[13]), + .Q(plm_frm_reg_d0_td[13]), + .CLR(plm_rst) + ); + FDCE plm_frm_reg_d0_td_12_ ( + .CE(plm_phy_cke_1_401), + .C(mgt_clk), + .D(phy_td[12]), + .Q(plm_frm_reg_d0_td[12]), + .CLR(plm_rst) + ); + FDCE plm_frm_reg_d0_td_11_ ( + .CE(plm_phy_cke_1_401), + .C(mgt_clk), + .D(phy_td[11]), + .Q(plm_frm_reg_d0_td[11]), + .CLR(plm_rst) + ); + FDCE plm_frm_reg_d0_td_10_ ( + .CE(plm_phy_cke_1_401), + .C(mgt_clk), + .D(phy_td[10]), + .Q(plm_frm_reg_d0_td[10]), + .CLR(plm_rst) + ); + FDCE plm_frm_reg_d0_td_9_ ( + .CE(plm_phy_cke_1_401), + .C(mgt_clk), + .D(phy_td[9]), + .Q(plm_frm_reg_d0_td[9]), + .CLR(plm_rst) + ); + FDCE plm_frm_reg_d0_td_8_ ( + .CE(plm_phy_cke_1_401), + .C(mgt_clk), + .D(phy_td[8]), + .Q(plm_frm_reg_d0_td[8]), + .CLR(plm_rst) + ); + FDCE plm_frm_reg_d0_td_7_ ( + .CE(plm_phy_cke_1_401), + .C(mgt_clk), + .D(phy_td[7]), + .Q(plm_frm_reg_d0_td[7]), + .CLR(plm_rst) + ); + FDCE plm_frm_reg_d0_td_6_ ( + .CE(plm_phy_cke_1_401), + .C(mgt_clk), + .D(phy_td[6]), + .Q(plm_frm_reg_d0_td[6]), + .CLR(plm_rst) + ); + FDCE plm_frm_reg_d0_td_5_ ( + .CE(plm_phy_cke_1_401), + .C(mgt_clk), + .D(phy_td[5]), + .Q(plm_frm_reg_d0_td[5]), + .CLR(plm_rst) + ); + FDCE plm_frm_reg_d0_td_4_ ( + .CE(plm_phy_cke_1_401), + .C(mgt_clk), + .D(phy_td[4]), + .Q(plm_frm_reg_d0_td[4]), + .CLR(plm_rst) + ); + FDCE plm_frm_reg_d0_td_3_ ( + .CE(plm_phy_cke_1_401), + .C(mgt_clk), + .D(phy_td[3]), + .Q(plm_frm_reg_d0_td[3]), + .CLR(plm_rst) + ); + FDCE plm_frm_reg_d0_td_2_ ( + .CE(plm_phy_cke_1_401), + .C(mgt_clk), + .D(phy_td[2]), + .Q(plm_frm_reg_d0_td[2]), + .CLR(plm_rst) + ); + FDCE plm_frm_reg_d0_td_1_ ( + .CE(plm_phy_cke_1_401), + .C(mgt_clk), + .D(phy_td[1]), + .Q(plm_frm_reg_d0_td[1]), + .CLR(plm_rst) + ); + FDCE plm_frm_reg_d0_td_0_ ( + .CE(plm_phy_cke_1_401), + .C(mgt_clk), + .D(phy_td[0]), + .Q(plm_frm_reg_d0_td[0]), + .CLR(plm_rst) + ); + FDCE plm_frm_reg_d1_tctrl_h ( + .CE(plm_phy_cke_2_400), + .C(mgt_clk), + .D(plm_frm_reg_d0_tctrl_h_798), + .Q(plm_frm_reg_d1_tctrl_h_799), + .CLR(plm_rst) + ); + FDCE plm_frm_reg_d1_tctrl_l ( + .CE(plm_phy_cke_2_400), + .C(mgt_clk), + .D(plm_frm_reg_d0_tctrl_l_800), + .Q(plm_frm_reg_d1_tctrl_l_801), + .CLR(plm_rst) + ); + FDCE plm_frm_reg_d1_tframe_h ( + .CE(plm_phy_cke_3_399), + .C(mgt_clk), + .D(plm_frm_reg_d0_tframe_h_802), + .Q(plm_frm_reg_d1_tframe_h_804), + .CLR(plm_rst) + ); + FDCE plm_frm_reg_d1_tframe_l ( + .CE(plm_phy_cke_3_399), + .C(mgt_clk), + .D(plm_frm_reg_d0_tframe_l_803), + .Q(plm_frm_reg_d1_tframe_l_806), + .CLR(plm_rst) + ); + FDCE plm_frm_reg_d1_td_63_ ( + .CE(plm_phy_cke_3_399), + .C(mgt_clk), + .D(plm_frm_reg_d0_td[63]), + .Q(plm_frm_reg_d1_td[63]), + .CLR(plm_rst) + ); + FDCE plm_frm_reg_d1_td_62_ ( + .CE(plm_phy_cke_3_399), + .C(mgt_clk), + .D(plm_frm_reg_d0_td[62]), + .Q(plm_frm_reg_d1_td[62]), + .CLR(plm_rst) + ); + FDCE plm_frm_reg_d1_td_61_ ( + .CE(plm_phy_cke_3_399), + .C(mgt_clk), + .D(plm_frm_reg_d0_td[61]), + .Q(plm_frm_reg_d1_td[61]), + .CLR(plm_rst) + ); + FDCE plm_frm_reg_d1_td_60_ ( + .CE(plm_phy_cke_3_399), + .C(mgt_clk), + .D(plm_frm_reg_d0_td[60]), + .Q(plm_frm_reg_d1_td[60]), + .CLR(plm_rst) + ); + FDCE plm_frm_reg_d1_td_59_ ( + .CE(plm_phy_cke_3_399), + .C(mgt_clk), + .D(plm_frm_reg_d0_td[59]), + .Q(plm_frm_reg_d1_td[59]), + .CLR(plm_rst) + ); + FDCE plm_frm_reg_d1_td_58_ ( + .CE(plm_phy_cke_3_399), + .C(mgt_clk), + .D(plm_frm_reg_d0_td[58]), + .Q(plm_frm_reg_d1_td[58]), + .CLR(plm_rst) + ); + FDCE plm_frm_reg_d1_td_57_ ( + .CE(plm_phy_cke_2_400), + .C(mgt_clk), + .D(plm_frm_reg_d0_td[57]), + .Q(plm_frm_reg_d1_td[57]), + .CLR(plm_rst) + ); + FDCE plm_frm_reg_d1_td_56_ ( + .CE(plm_phy_cke_2_400), + .C(mgt_clk), + .D(plm_frm_reg_d0_td[56]), + .Q(plm_frm_reg_d1_td[56]), + .CLR(plm_rst) + ); + FDCE plm_frm_reg_d1_td_55_ ( + .CE(plm_phy_cke_2_400), + .C(mgt_clk), + .D(plm_frm_reg_d0_td[55]), + .Q(plm_frm_reg_d1_td[55]), + .CLR(plm_rst) + ); + FDCE plm_frm_reg_d1_td_54_ ( + .CE(plm_phy_cke_2_400), + .C(mgt_clk), + .D(plm_frm_reg_d0_td[54]), + .Q(plm_frm_reg_d1_td[54]), + .CLR(plm_rst) + ); + FDCE plm_frm_reg_d1_td_53_ ( + .CE(plm_phy_cke_2_400), + .C(mgt_clk), + .D(plm_frm_reg_d0_td[53]), + .Q(plm_frm_reg_d1_td[53]), + .CLR(plm_rst) + ); + FDCE plm_frm_reg_d1_td_52_ ( + .CE(plm_phy_cke_2_400), + .C(mgt_clk), + .D(plm_frm_reg_d0_td[52]), + .Q(plm_frm_reg_d1_td[52]), + .CLR(plm_rst) + ); + FDCE plm_frm_reg_d1_td_51_ ( + .CE(plm_phy_cke_2_400), + .C(mgt_clk), + .D(plm_frm_reg_d0_td[51]), + .Q(plm_frm_reg_d1_td[51]), + .CLR(plm_rst) + ); + FDCE plm_frm_reg_d1_td_50_ ( + .CE(plm_phy_cke_2_400), + .C(mgt_clk), + .D(plm_frm_reg_d0_td[50]), + .Q(plm_frm_reg_d1_td[50]), + .CLR(plm_rst) + ); + FDCE plm_frm_reg_d1_td_49_ ( + .CE(plm_phy_cke_2_400), + .C(mgt_clk), + .D(plm_frm_reg_d0_td[49]), + .Q(plm_frm_reg_d1_td[49]), + .CLR(plm_rst) + ); + FDCE plm_frm_reg_d1_td_48_ ( + .CE(plm_phy_cke_2_400), + .C(mgt_clk), + .D(plm_frm_reg_d0_td[48]), + .Q(plm_frm_reg_d1_td[48]), + .CLR(plm_rst) + ); + FDCE plm_frm_reg_d1_td_47_ ( + .CE(plm_phy_cke_2_400), + .C(mgt_clk), + .D(plm_frm_reg_d0_td[47]), + .Q(plm_frm_reg_d1_td[47]), + .CLR(plm_rst) + ); + FDCE plm_frm_reg_d1_td_46_ ( + .CE(plm_phy_cke_2_400), + .C(mgt_clk), + .D(plm_frm_reg_d0_td[46]), + .Q(plm_frm_reg_d1_td[46]), + .CLR(plm_rst) + ); + FDCE plm_frm_reg_d1_td_45_ ( + .CE(plm_phy_cke_2_400), + .C(mgt_clk), + .D(plm_frm_reg_d0_td[45]), + .Q(plm_frm_reg_d1_td[45]), + .CLR(plm_rst) + ); + FDCE plm_frm_reg_d1_td_44_ ( + .CE(plm_phy_cke_2_400), + .C(mgt_clk), + .D(plm_frm_reg_d0_td[44]), + .Q(plm_frm_reg_d1_td[44]), + .CLR(plm_rst) + ); + FDCE plm_frm_reg_d1_td_43_ ( + .CE(plm_phy_cke_2_400), + .C(mgt_clk), + .D(plm_frm_reg_d0_td[43]), + .Q(plm_frm_reg_d1_td[43]), + .CLR(plm_rst) + ); + FDCE plm_frm_reg_d1_td_42_ ( + .CE(plm_phy_cke_2_400), + .C(mgt_clk), + .D(plm_frm_reg_d0_td[42]), + .Q(plm_frm_reg_d1_td[42]), + .CLR(plm_rst) + ); + FDCE plm_frm_reg_d1_td_41_ ( + .CE(plm_phy_cke_2_400), + .C(mgt_clk), + .D(plm_frm_reg_d0_td[41]), + .Q(plm_frm_reg_d1_td[41]), + .CLR(plm_rst) + ); + FDCE plm_frm_reg_d1_td_40_ ( + .CE(plm_phy_cke_2_400), + .C(mgt_clk), + .D(plm_frm_reg_d0_td[40]), + .Q(plm_frm_reg_d1_td[40]), + .CLR(plm_rst) + ); + FDCE plm_frm_reg_d1_td_39_ ( + .CE(plm_phy_cke_2_400), + .C(mgt_clk), + .D(plm_frm_reg_d0_td[39]), + .Q(plm_frm_reg_d1_td[39]), + .CLR(plm_rst) + ); + FDCE plm_frm_reg_d1_td_38_ ( + .CE(plm_phy_cke_2_400), + .C(mgt_clk), + .D(plm_frm_reg_d0_td[38]), + .Q(plm_frm_reg_d1_td[38]), + .CLR(plm_rst) + ); + FDCE plm_frm_reg_d1_td_37_ ( + .CE(plm_phy_cke_2_400), + .C(mgt_clk), + .D(plm_frm_reg_d0_td[37]), + .Q(plm_frm_reg_d1_td[37]), + .CLR(plm_rst) + ); + FDCE plm_frm_reg_d1_td_36_ ( + .CE(plm_phy_cke_2_400), + .C(mgt_clk), + .D(plm_frm_reg_d0_td[36]), + .Q(plm_frm_reg_d1_td[36]), + .CLR(plm_rst) + ); + FDCE plm_frm_reg_d1_td_35_ ( + .CE(plm_phy_cke_2_400), + .C(mgt_clk), + .D(plm_frm_reg_d0_td[35]), + .Q(plm_frm_reg_d1_td[35]), + .CLR(plm_rst) + ); + FDCE plm_frm_reg_d1_td_34_ ( + .CE(plm_phy_cke_2_400), + .C(mgt_clk), + .D(plm_frm_reg_d0_td[34]), + .Q(plm_frm_reg_d1_td[34]), + .CLR(plm_rst) + ); + FDCE plm_frm_reg_d1_td_33_ ( + .CE(plm_phy_cke_2_400), + .C(mgt_clk), + .D(plm_frm_reg_d0_td[33]), + .Q(plm_frm_reg_d1_td[33]), + .CLR(plm_rst) + ); + FDCE plm_frm_reg_d1_td_32_ ( + .CE(plm_phy_cke_2_400), + .C(mgt_clk), + .D(plm_frm_reg_d0_td[32]), + .Q(plm_frm_reg_d1_td[32]), + .CLR(plm_rst) + ); + FDCE plm_frm_reg_d1_td_31_ ( + .CE(plm_phy_cke_2_400), + .C(mgt_clk), + .D(plm_frm_reg_d0_td[31]), + .Q(plm_frm_reg_d1_td[31]), + .CLR(plm_rst) + ); + FDCE plm_frm_reg_d1_td_30_ ( + .CE(plm_phy_cke_2_400), + .C(mgt_clk), + .D(plm_frm_reg_d0_td[30]), + .Q(plm_frm_reg_d1_td[30]), + .CLR(plm_rst) + ); + FDCE plm_frm_reg_d1_td_29_ ( + .CE(plm_phy_cke_2_400), + .C(mgt_clk), + .D(plm_frm_reg_d0_td[29]), + .Q(plm_frm_reg_d1_td[29]), + .CLR(plm_rst) + ); + FDCE plm_frm_reg_d1_td_28_ ( + .CE(plm_phy_cke_2_400), + .C(mgt_clk), + .D(plm_frm_reg_d0_td[28]), + .Q(plm_frm_reg_d1_td[28]), + .CLR(plm_rst) + ); + FDCE plm_frm_reg_d1_td_27_ ( + .CE(plm_phy_cke_2_400), + .C(mgt_clk), + .D(plm_frm_reg_d0_td[27]), + .Q(plm_frm_reg_d1_td[27]), + .CLR(plm_rst) + ); + FDCE plm_frm_reg_d1_td_26_ ( + .CE(plm_phy_cke_2_400), + .C(mgt_clk), + .D(plm_frm_reg_d0_td[26]), + .Q(plm_frm_reg_d1_td[26]), + .CLR(plm_rst) + ); + FDCE plm_frm_reg_d1_td_25_ ( + .CE(plm_phy_cke_2_400), + .C(mgt_clk), + .D(plm_frm_reg_d0_td[25]), + .Q(plm_frm_reg_d1_td[25]), + .CLR(plm_rst) + ); + FDCE plm_frm_reg_d1_td_24_ ( + .CE(plm_phy_cke_2_400), + .C(mgt_clk), + .D(plm_frm_reg_d0_td[24]), + .Q(plm_frm_reg_d1_td[24]), + .CLR(plm_rst) + ); + FDCE plm_frm_reg_d1_td_23_ ( + .CE(plm_phy_cke_2_400), + .C(mgt_clk), + .D(plm_frm_reg_d0_td[23]), + .Q(plm_frm_reg_d1_td[23]), + .CLR(plm_rst) + ); + FDCE plm_frm_reg_d1_td_22_ ( + .CE(plm_phy_cke_2_400), + .C(mgt_clk), + .D(plm_frm_reg_d0_td[22]), + .Q(plm_frm_reg_d1_td[22]), + .CLR(plm_rst) + ); + FDCE plm_frm_reg_d1_td_21_ ( + .CE(plm_phy_cke_2_400), + .C(mgt_clk), + .D(plm_frm_reg_d0_td[21]), + .Q(plm_frm_reg_d1_td[21]), + .CLR(plm_rst) + ); + FDCE plm_frm_reg_d1_td_20_ ( + .CE(plm_phy_cke_2_400), + .C(mgt_clk), + .D(plm_frm_reg_d0_td[20]), + .Q(plm_frm_reg_d1_td[20]), + .CLR(plm_rst) + ); + FDCE plm_frm_reg_d1_td_19_ ( + .CE(plm_phy_cke_2_400), + .C(mgt_clk), + .D(plm_frm_reg_d0_td[19]), + .Q(plm_frm_reg_d1_td[19]), + .CLR(plm_rst) + ); + FDCE plm_frm_reg_d1_td_18_ ( + .CE(plm_phy_cke_2_400), + .C(mgt_clk), + .D(plm_frm_reg_d0_td[18]), + .Q(plm_frm_reg_d1_td[18]), + .CLR(plm_rst) + ); + FDCE plm_frm_reg_d1_td_17_ ( + .CE(plm_phy_cke_2_400), + .C(mgt_clk), + .D(plm_frm_reg_d0_td[17]), + .Q(plm_frm_reg_d1_td[17]), + .CLR(plm_rst) + ); + FDCE plm_frm_reg_d1_td_16_ ( + .CE(plm_phy_cke_2_400), + .C(mgt_clk), + .D(plm_frm_reg_d0_td[16]), + .Q(plm_frm_reg_d1_td[16]), + .CLR(plm_rst) + ); + FDCE plm_frm_reg_d1_td_15_ ( + .CE(plm_phy_cke_2_400), + .C(mgt_clk), + .D(plm_frm_reg_d0_td[15]), + .Q(plm_frm_reg_d1_td[15]), + .CLR(plm_rst) + ); + FDCE plm_frm_reg_d1_td_14_ ( + .CE(plm_phy_cke_2_400), + .C(mgt_clk), + .D(plm_frm_reg_d0_td[14]), + .Q(plm_frm_reg_d1_td[14]), + .CLR(plm_rst) + ); + FDCE plm_frm_reg_d1_td_13_ ( + .CE(plm_phy_cke_2_400), + .C(mgt_clk), + .D(plm_frm_reg_d0_td[13]), + .Q(plm_frm_reg_d1_td[13]), + .CLR(plm_rst) + ); + FDCE plm_frm_reg_d1_td_12_ ( + .CE(plm_phy_cke_2_400), + .C(mgt_clk), + .D(plm_frm_reg_d0_td[12]), + .Q(plm_frm_reg_d1_td[12]), + .CLR(plm_rst) + ); + FDCE plm_frm_reg_d1_td_11_ ( + .CE(plm_phy_cke_2_400), + .C(mgt_clk), + .D(plm_frm_reg_d0_td[11]), + .Q(plm_frm_reg_d1_td[11]), + .CLR(plm_rst) + ); + FDCE plm_frm_reg_d1_td_10_ ( + .CE(plm_phy_cke_2_400), + .C(mgt_clk), + .D(plm_frm_reg_d0_td[10]), + .Q(plm_frm_reg_d1_td[10]), + .CLR(plm_rst) + ); + FDCE plm_frm_reg_d1_td_9_ ( + .CE(plm_phy_cke_2_400), + .C(mgt_clk), + .D(plm_frm_reg_d0_td[9]), + .Q(plm_frm_reg_d1_td[9]), + .CLR(plm_rst) + ); + FDCE plm_frm_reg_d1_td_8_ ( + .CE(plm_phy_cke_2_400), + .C(mgt_clk), + .D(plm_frm_reg_d0_td[8]), + .Q(plm_frm_reg_d1_td[8]), + .CLR(plm_rst) + ); + FDCE plm_frm_reg_d1_td_7_ ( + .CE(plm_phy_cke_2_400), + .C(mgt_clk), + .D(plm_frm_reg_d0_td[7]), + .Q(plm_frm_reg_d1_td[7]), + .CLR(plm_rst) + ); + FDCE plm_frm_reg_d1_td_6_ ( + .CE(plm_phy_cke_2_400), + .C(mgt_clk), + .D(plm_frm_reg_d0_td[6]), + .Q(plm_frm_reg_d1_td[6]), + .CLR(plm_rst) + ); + FDCE plm_frm_reg_d1_td_5_ ( + .CE(plm_phy_cke_2_400), + .C(mgt_clk), + .D(plm_frm_reg_d0_td[5]), + .Q(plm_frm_reg_d1_td[5]), + .CLR(plm_rst) + ); + FDCE plm_frm_reg_d1_td_4_ ( + .CE(plm_phy_cke_2_400), + .C(mgt_clk), + .D(plm_frm_reg_d0_td[4]), + .Q(plm_frm_reg_d1_td[4]), + .CLR(plm_rst) + ); + FDCE plm_frm_reg_d1_td_3_ ( + .CE(plm_phy_cke_2_400), + .C(mgt_clk), + .D(plm_frm_reg_d0_td[3]), + .Q(plm_frm_reg_d1_td[3]), + .CLR(plm_rst) + ); + FDCE plm_frm_reg_d1_td_2_ ( + .CE(plm_phy_cke_2_400), + .C(mgt_clk), + .D(plm_frm_reg_d0_td[2]), + .Q(plm_frm_reg_d1_td[2]), + .CLR(plm_rst) + ); + FDCE plm_frm_reg_d1_td_1_ ( + .CE(plm_phy_cke_2_400), + .C(mgt_clk), + .D(plm_frm_reg_d0_td[1]), + .Q(plm_frm_reg_d1_td[1]), + .CLR(plm_rst) + ); + FDCE plm_frm_reg_d1_td_0_ ( + .CE(plm_phy_cke_2_400), + .C(mgt_clk), + .D(plm_frm_reg_d0_td[0]), + .Q(plm_frm_reg_d1_td[0]), + .CLR(plm_rst) + ); + FDCE plm_frm_reg_d2_tframe_h ( + .CE(plm_phy_cke_3_399), + .C(mgt_clk), + .D(plm_frm_reg_d1_tframe_h_804), + .Q(plm_frm_reg_d2_tframe_h_805), + .CLR(plm_rst) + ); + FDCE plm_frm_reg_d2_tframe_l ( + .CE(plm_phy_cke_3_399), + .C(mgt_clk), + .D(plm_frm_reg_d1_tframe_l_806), + .Q(plm_frm_reg_d2_tframe_l_807), + .CLR(plm_rst) + ); + FDCE plm_frm_reg_d1_idleflag_hh ( + .CE(plm_phy_cke_2_400), + .C(mgt_clk), + .D(plm_frm_reg_d1_idleflag_hh_3), + .Q(plm_frm_reg_d1_idleflag_hh_808), + .CLR(plm_rst) + ); + FDCE plm_frm_reg_d1_idleflag_hl ( + .CE(plm_phy_cke_2_400), + .C(mgt_clk), + .D(plm_frm_reg_d1_idleflag_hl_3), + .Q(plm_frm_reg_d1_idleflag_hl_809), + .CLR(plm_rst) + ); + FDCE plm_frm_reg_d1_idleflag_lh ( + .CE(plm_phy_cke_2_400), + .C(mgt_clk), + .D(plm_frm_reg_d1_idleflag_lh_3), + .Q(plm_frm_reg_d1_idleflag_lh_810), + .CLR(plm_rst) + ); + FDCE plm_frm_reg_d1_idleflag_ll ( + .CE(plm_phy_cke_2_400), + .C(mgt_clk), + .D(plm_frm_reg_d1_idleflag_ll_3), + .Q(plm_frm_reg_d1_idleflag_ll_811), + .CLR(plm_rst) + ); + FDCE plm_frm_reg_d2_idle_h ( + .CE(plm_phy_cke_3_399), + .C(mgt_clk), + .D(plm_frm_N_9970_i_812), + .Q(plm_frm_reg_d2_idle_h_813), + .CLR(plm_rst) + ); + FDCE plm_frm_reg_d2_idle_l ( + .CE(plm_phy_cke_3_399), + .C(mgt_clk), + .D(plm_frm_N_9969_i_814), + .Q(plm_frm_reg_d2_idle_l_815), + .CLR(plm_rst) + ); + FDCE plm_frm_reg_d2_charisk_0_ ( + .CE(plm_phy_cke_3_399), + .C(mgt_clk), + .D(plm_frm_reg_d2_charisk_1_sqmuxa_2_816), + .Q(plm_frm_reg_d2_charisk_0__817), + .CLR(plm_rst) + ); + FDCE plm_frm_reg_d2_charisk_7_ ( + .CE(plm_phy_cke_3_399), + .C(mgt_clk), + .D(plm_frm_reg_d2_charisk_1_sqmuxa_1_818), + .Q(plm_frm_reg_d2_charisk_7__819), + .CLR(plm_rst) + ); + FDCE plm_frm_reg_d2_charisk_4_ ( + .CE(plm_phy_cke_3_399), + .C(mgt_clk), + .D(plm_frm_reg_d2_charisk_1_sqmuxa_820), + .Q(plm_frm_reg_d2_charisk_4__821), + .CLR(plm_rst) + ); + FDCE plm_frm_reg_d2_charisk_3_ ( + .CE(plm_phy_cke_3_399), + .C(mgt_clk), + .D(plm_frm_reg_d2_charisk_1_sqmuxa_3_822), + .Q(plm_frm_reg_d2_charisk_3__823), + .CLR(plm_rst) + ); + FDCE plm_frm_reg_d2_td_63_ ( + .CE(plm_phy_cke_3_399), + .C(mgt_clk), + .D(plm_frm_N_8815_i), + .Q(plm_frm_reg_d2_td[63]), + .CLR(plm_rst) + ); + FDCE plm_frm_reg_d2_td_62_ ( + .CE(plm_phy_cke_3_399), + .C(mgt_clk), + .D(plm_frm_reg_d2_td_13_62_), + .Q(plm_frm_reg_d2_td[62]), + .CLR(plm_rst) + ); + FDCE plm_frm_reg_d2_td_61_ ( + .CE(plm_phy_cke_3_399), + .C(mgt_clk), + .D(plm_frm_N_8817_i), + .Q(plm_frm_reg_d2_td[61]), + .CLR(plm_rst) + ); + FDCE plm_frm_reg_d2_td_60_ ( + .CE(plm_phy_cke_3_399), + .C(mgt_clk), + .D(plm_frm_reg_d2_td_13_60_), + .Q(plm_frm_reg_d2_td[60]), + .CLR(plm_rst) + ); + FDCE plm_frm_reg_d2_td_59_ ( + .CE(plm_phy_cke_3_399), + .C(mgt_clk), + .D(plm_frm_reg_d2_td_13_59_), + .Q(plm_frm_reg_d2_td[59]), + .CLR(plm_rst) + ); + FDCE plm_frm_reg_d2_td_58_ ( + .CE(plm_phy_cke_3_399), + .C(mgt_clk), + .D(plm_frm_N_8818_i), + .Q(plm_frm_reg_d2_td[58]), + .CLR(plm_rst) + ); + FDCE plm_frm_reg_d2_td_57_ ( + .CE(plm_phy_cke_3_399), + .C(mgt_clk), + .D(plm_frm_N_8819_i), + .Q(plm_frm_reg_d2_td[57]), + .CLR(plm_rst) + ); + FDCE plm_frm_reg_d2_td_56_ ( + .CE(plm_phy_cke_3_399), + .C(mgt_clk), + .D(plm_frm_N_8820_i), + .Q(plm_frm_reg_d2_td[56]), + .CLR(plm_rst) + ); + FDCE plm_frm_reg_d2_td_55_ ( + .CE(plm_phy_cke_3_399), + .C(mgt_clk), + .D(plm_frm_reg_d2_td_13_55_), + .Q(plm_frm_reg_d2_td[55]), + .CLR(plm_rst) + ); + FDCE plm_frm_reg_d2_td_54_ ( + .CE(plm_phy_cke_3_399), + .C(mgt_clk), + .D(plm_frm_reg_d2_td_13_54_), + .Q(plm_frm_reg_d2_td[54]), + .CLR(plm_rst) + ); + FDCE plm_frm_reg_d2_td_53_ ( + .CE(plm_phy_cke_3_399), + .C(mgt_clk), + .D(plm_frm_reg_d2_td_13_53_), + .Q(plm_frm_reg_d2_td[53]), + .CLR(plm_rst) + ); + FDCE plm_frm_reg_d2_td_52_ ( + .CE(plm_phy_cke_3_399), + .C(mgt_clk), + .D(plm_frm_reg_d2_td_13_52_), + .Q(plm_frm_reg_d2_td[52]), + .CLR(plm_rst) + ); + FDCE plm_frm_reg_d2_td_51_ ( + .CE(plm_phy_cke_3_399), + .C(mgt_clk), + .D(plm_frm_reg_d2_td_13_51_), + .Q(plm_frm_reg_d2_td[51]), + .CLR(plm_rst) + ); + FDCE plm_frm_reg_d2_td_50_ ( + .CE(plm_phy_cke_3_399), + .C(mgt_clk), + .D(plm_frm_reg_d2_td_13_50_), + .Q(plm_frm_reg_d2_td[50]), + .CLR(plm_rst) + ); + FDCE plm_frm_reg_d2_td_49_ ( + .CE(plm_phy_cke_3_399), + .C(mgt_clk), + .D(plm_frm_reg_d2_td_13_49_), + .Q(plm_frm_reg_d2_td[49]), + .CLR(plm_rst) + ); + FDCE plm_frm_reg_d2_td_48_ ( + .CE(plm_phy_cke_3_399), + .C(mgt_clk), + .D(plm_frm_reg_d2_td_13_48_), + .Q(plm_frm_reg_d2_td[48]), + .CLR(plm_rst) + ); + FDCE plm_frm_reg_d2_td_47_ ( + .CE(plm_phy_cke_3_399), + .C(mgt_clk), + .D(plm_frm_reg_d2_td_13_47_), + .Q(plm_frm_reg_d2_td[47]), + .CLR(plm_rst) + ); + FDCE plm_frm_reg_d2_td_46_ ( + .CE(plm_phy_cke_3_399), + .C(mgt_clk), + .D(plm_frm_reg_d2_td_13_46_), + .Q(plm_frm_reg_d2_td[46]), + .CLR(plm_rst) + ); + FDCE plm_frm_reg_d2_td_45_ ( + .CE(plm_phy_cke_3_399), + .C(mgt_clk), + .D(plm_frm_reg_d2_td_13_45_), + .Q(plm_frm_reg_d2_td[45]), + .CLR(plm_rst) + ); + FDCE plm_frm_reg_d2_td_44_ ( + .CE(plm_phy_cke_3_399), + .C(mgt_clk), + .D(plm_frm_reg_d2_td_13_44_), + .Q(plm_frm_reg_d2_td[44]), + .CLR(plm_rst) + ); + FDCE plm_frm_reg_d2_td_43_ ( + .CE(plm_phy_cke_3_399), + .C(mgt_clk), + .D(plm_frm_reg_d2_td_13_43_), + .Q(plm_frm_reg_d2_td[43]), + .CLR(plm_rst) + ); + FDCE plm_frm_reg_d2_td_42_ ( + .CE(plm_phy_cke_3_399), + .C(mgt_clk), + .D(plm_frm_reg_d2_td_13_42_), + .Q(plm_frm_reg_d2_td[42]), + .CLR(plm_rst) + ); + FDCE plm_frm_reg_d2_td_41_ ( + .CE(plm_phy_cke_3_399), + .C(mgt_clk), + .D(plm_frm_reg_d2_td_13_41_), + .Q(plm_frm_reg_d2_td[41]), + .CLR(plm_rst) + ); + FDCE plm_frm_reg_d2_td_40_ ( + .CE(plm_phy_cke_3_399), + .C(mgt_clk), + .D(plm_frm_reg_d2_td_13_40_), + .Q(plm_frm_reg_d2_td[40]), + .CLR(plm_rst) + ); + FDCE plm_frm_reg_d2_td_39_ ( + .CE(plm_phy_cke_3_399), + .C(mgt_clk), + .D(plm_frm_reg_d2_td_13_39_), + .Q(plm_frm_reg_d2_td[39]), + .CLR(plm_rst) + ); + FDCE plm_frm_reg_d2_td_38_ ( + .CE(plm_phy_cke_3_399), + .C(mgt_clk), + .D(plm_frm_reg_d2_td_13_38_), + .Q(plm_frm_reg_d2_td[38]), + .CLR(plm_rst) + ); + FDCE plm_frm_reg_d2_td_37_ ( + .CE(plm_phy_cke_3_399), + .C(mgt_clk), + .D(plm_frm_reg_d2_td_13_37_), + .Q(plm_frm_reg_d2_td[37]), + .CLR(plm_rst) + ); + FDCE plm_frm_reg_d2_td_36_ ( + .CE(plm_phy_cke_3_399), + .C(mgt_clk), + .D(plm_frm_reg_d2_td_13_36_), + .Q(plm_frm_reg_d2_td[36]), + .CLR(plm_rst) + ); + FDCE plm_frm_reg_d2_td_35_ ( + .CE(plm_phy_cke_3_399), + .C(mgt_clk), + .D(plm_frm_reg_d2_td_13_35_), + .Q(plm_frm_reg_d2_td[35]), + .CLR(plm_rst) + ); + FDCE plm_frm_reg_d2_td_34_ ( + .CE(plm_phy_cke_3_399), + .C(mgt_clk), + .D(plm_frm_reg_d2_td_13_34_), + .Q(plm_frm_reg_d2_td[34]), + .CLR(plm_rst) + ); + FDCE plm_frm_reg_d2_td_33_ ( + .CE(plm_phy_cke_3_399), + .C(mgt_clk), + .D(plm_frm_N_8821_i_0), + .Q(plm_frm_reg_d2_td[33]), + .CLR(plm_rst) + ); + FDCE plm_frm_reg_d2_td_32_ ( + .CE(plm_phy_cke_3_399), + .C(mgt_clk), + .D(plm_frm_N_8823_i), + .Q(plm_frm_reg_d2_td[32]), + .CLR(plm_rst) + ); + FDCE plm_frm_reg_d2_td_31_ ( + .CE(plm_phy_cke_3_399), + .C(mgt_clk), + .D(plm_frm_N_8806_i), + .Q(plm_frm_reg_d2_td[31]), + .CLR(plm_rst) + ); + FDCE plm_frm_reg_d2_td_30_ ( + .CE(plm_phy_cke_3_399), + .C(mgt_clk), + .D(plm_frm_reg_d2_td_24_30_), + .Q(plm_frm_reg_d2_td[30]), + .CLR(plm_rst) + ); + FDCE plm_frm_reg_d2_td_29_ ( + .CE(plm_phy_cke_3_399), + .C(mgt_clk), + .D(plm_frm_N_8808_i), + .Q(plm_frm_reg_d2_td[29]), + .CLR(plm_rst) + ); + FDCE plm_frm_reg_d2_td_28_ ( + .CE(plm_phy_cke_3_399), + .C(mgt_clk), + .D(plm_frm_reg_d2_td_24_28_), + .Q(plm_frm_reg_d2_td[28]), + .CLR(plm_rst) + ); + FDCE plm_frm_reg_d2_td_27_ ( + .CE(plm_phy_cke_3_399), + .C(mgt_clk), + .D(plm_frm_reg_d2_td_24_27_), + .Q(plm_frm_reg_d2_td[27]), + .CLR(plm_rst) + ); + FDCE plm_frm_reg_d2_td_26_ ( + .CE(plm_phy_cke_3_399), + .C(mgt_clk), + .D(plm_frm_N_8809_i), + .Q(plm_frm_reg_d2_td[26]), + .CLR(plm_rst) + ); + FDCE plm_frm_reg_d2_td_25_ ( + .CE(plm_phy_cke_3_399), + .C(mgt_clk), + .D(plm_frm_N_8810_i), + .Q(plm_frm_reg_d2_td[25]), + .CLR(plm_rst) + ); + FDCE plm_frm_reg_d2_td_24_ ( + .CE(plm_phy_cke_3_399), + .C(mgt_clk), + .D(plm_frm_N_8811_i), + .Q(plm_frm_reg_d2_td[24]), + .CLR(plm_rst) + ); + FDCE plm_frm_reg_d2_td_23_ ( + .CE(plm_phy_cke_3_399), + .C(mgt_clk), + .D(plm_frm_reg_d2_td_24_23_), + .Q(plm_frm_reg_d2_td[23]), + .CLR(plm_rst) + ); + FDCE plm_frm_reg_d2_td_22_ ( + .CE(plm_phy_cke_3_399), + .C(mgt_clk), + .D(plm_frm_reg_d2_td_24_22_), + .Q(plm_frm_reg_d2_td[22]), + .CLR(plm_rst) + ); + FDCE plm_frm_reg_d2_td_21_ ( + .CE(plm_phy_cke_3_399), + .C(mgt_clk), + .D(plm_frm_reg_d2_td_24_21_), + .Q(plm_frm_reg_d2_td[21]), + .CLR(plm_rst) + ); + FDCE plm_frm_reg_d2_td_20_ ( + .CE(plm_phy_cke_3_399), + .C(mgt_clk), + .D(plm_frm_reg_d2_td_24_20_), + .Q(plm_frm_reg_d2_td[20]), + .CLR(plm_rst) + ); + FDCE plm_frm_reg_d2_td_19_ ( + .CE(plm_phy_cke_3_399), + .C(mgt_clk), + .D(plm_frm_reg_d2_td_24_19_), + .Q(plm_frm_reg_d2_td[19]), + .CLR(plm_rst) + ); + FDCE plm_frm_reg_d2_td_18_ ( + .CE(plm_phy_cke_3_399), + .C(mgt_clk), + .D(plm_frm_reg_d2_td_24_18_), + .Q(plm_frm_reg_d2_td[18]), + .CLR(plm_rst) + ); + FDCE plm_frm_reg_d2_td_17_ ( + .CE(plm_phy_cke_3_399), + .C(mgt_clk), + .D(plm_frm_reg_d2_td_24_17_), + .Q(plm_frm_reg_d2_td[17]), + .CLR(plm_rst) + ); + FDCE plm_frm_reg_d2_td_16_ ( + .CE(plm_phy_cke_3_399), + .C(mgt_clk), + .D(plm_frm_reg_d2_td_24_16_), + .Q(plm_frm_reg_d2_td[16]), + .CLR(plm_rst) + ); + FDCE plm_frm_reg_d2_td_15_ ( + .CE(plm_phy_cke_3_399), + .C(mgt_clk), + .D(plm_frm_reg_d2_td_24_15_), + .Q(plm_frm_reg_d2_td[15]), + .CLR(plm_rst) + ); + FDCE plm_frm_reg_d2_td_14_ ( + .CE(plm_phy_cke_3_399), + .C(mgt_clk), + .D(plm_frm_reg_d2_td_24_14_), + .Q(plm_frm_reg_d2_td[14]), + .CLR(plm_rst) + ); + FDCE plm_frm_reg_d2_td_13_ ( + .CE(plm_phy_cke_3_399), + .C(mgt_clk), + .D(plm_frm_reg_d2_td_24_13_), + .Q(plm_frm_reg_d2_td[13]), + .CLR(plm_rst) + ); + FDCE plm_frm_reg_d2_td_12_ ( + .CE(plm_phy_cke_3_399), + .C(mgt_clk), + .D(plm_frm_reg_d2_td_24_12_), + .Q(plm_frm_reg_d2_td[12]), + .CLR(plm_rst) + ); + FDCE plm_frm_reg_d2_td_11_ ( + .CE(plm_phy_cke_3_399), + .C(mgt_clk), + .D(plm_frm_reg_d2_td_24_11_), + .Q(plm_frm_reg_d2_td[11]), + .CLR(plm_rst) + ); + FDCE plm_frm_reg_d2_td_10_ ( + .CE(plm_phy_cke_3_399), + .C(mgt_clk), + .D(plm_frm_reg_d2_td_24_10_), + .Q(plm_frm_reg_d2_td[10]), + .CLR(plm_rst) + ); + FDCE plm_frm_reg_d2_td_9_ ( + .CE(plm_phy_cke_3_399), + .C(mgt_clk), + .D(plm_frm_reg_d2_td_24_9_), + .Q(plm_frm_reg_d2_td[9]), + .CLR(plm_rst) + ); + FDCE plm_frm_reg_d2_td_8_ ( + .CE(plm_phy_cke_3_399), + .C(mgt_clk), + .D(plm_frm_reg_d2_td_24_8_), + .Q(plm_frm_reg_d2_td[8]), + .CLR(plm_rst) + ); + FDCE plm_frm_reg_d2_td_7_ ( + .CE(plm_phy_cke_3_399), + .C(mgt_clk), + .D(plm_frm_reg_d2_td_24_7_), + .Q(plm_frm_reg_d2_td[7]), + .CLR(plm_rst) + ); + FDCE plm_frm_reg_d2_td_6_ ( + .CE(plm_phy_cke_3_399), + .C(mgt_clk), + .D(plm_frm_reg_d2_td_24_6_), + .Q(plm_frm_reg_d2_td[6]), + .CLR(plm_rst) + ); + FDCE plm_frm_reg_d2_td_5_ ( + .CE(plm_phy_cke_3_399), + .C(mgt_clk), + .D(plm_frm_reg_d2_td_24_5_), + .Q(plm_frm_reg_d2_td[5]), + .CLR(plm_rst) + ); + FDCE plm_frm_reg_d2_td_4_ ( + .CE(plm_phy_cke_3_399), + .C(mgt_clk), + .D(plm_frm_reg_d2_td_24_4_), + .Q(plm_frm_reg_d2_td[4]), + .CLR(plm_rst) + ); + FDCE plm_frm_reg_d2_td_3_ ( + .CE(plm_phy_cke_3_399), + .C(mgt_clk), + .D(plm_frm_reg_d2_td_24_3_), + .Q(plm_frm_reg_d2_td[3]), + .CLR(plm_rst) + ); + FDCE plm_frm_reg_d2_td_2_ ( + .CE(plm_phy_cke_3_399), + .C(mgt_clk), + .D(plm_frm_reg_d2_td_24_2_), + .Q(plm_frm_reg_d2_td[2]), + .CLR(plm_rst) + ); + FDCE plm_frm_reg_d2_td_1_ ( + .CE(plm_phy_cke_3_399), + .C(mgt_clk), + .D(plm_frm_N_8812_i_0), + .Q(plm_frm_reg_d2_td[1]), + .CLR(plm_rst) + ); + FDCE plm_frm_reg_d2_td_0_ ( + .CE(plm_phy_cke_3_399), + .C(mgt_clk), + .D(plm_frm_N_8814_i), + .Q(plm_frm_reg_d2_td[0]), + .CLR(plm_rst) + ); + defparam plm_frm_frame1_reg_by1_frm0_is_k_5_0_.INIT = 4'h1; + LUT2_L plm_frm_frame1_reg_by1_frm0_is_k_5_0_ ( + .I0(plm_frm_frame1_reg_byp1_843), + .I1(plm_frm_reg_d2_charisk_4__821), + .LO(plm_frm_frame1_N_9974) + ); + defparam plm_frm_frame1_reg_by1_frm0_char_sn_m1_0_a3.INIT = 4'h4; + LUT2 plm_frm_frame1_reg_by1_frm0_char_sn_m1_0_a3 ( + .I0(plm_frm_frame1_reg_byp1_843), + .I1(plm_frm_frame1_reg_wd_sel[0]), + .O(plm_frm_frame1_reg_by1_frm0_char_sn_m1_0_a3_832) + ); + defparam plm_frm_frame1_reg_by1_frm0_char_sn_m4_i_a3.INIT = 8'hE0; + LUT3 plm_frm_frame1_reg_by1_frm0_char_sn_m4_i_a3 ( + .I0(plm_frm_frame1_reg_byp1_843), + .I1(plm_frm_frame1_reg_byp3_842), + .I2(plm_frm_frame1_reg_wd_sel[0]), + .O(plm_frm_frame1_reg_by1_frm0_char_sn_m4_i_a3_837) + ); + defparam plm_frm_frame1_reg_by1_frm0_char_0_0_13_.INIT = 8'hD8; + LUT3 plm_frm_frame1_reg_by1_frm0_char_0_0_13_ ( + .I0(plm_frm_frame1_reg_by1_frm0_char_sn_m1_0_a3_832), + .I1(plm_frm_reg_d2_td[45]), + .I2(plm_frm_reg_d2_td[61]), + .O(plm_frm_frame1_N_6132) + ); + defparam plm_frm_frame1_reg_by1_frm0_char_0_0_15_.INIT = 8'hD8; + LUT3 plm_frm_frame1_reg_by1_frm0_char_0_0_15_ ( + .I0(plm_frm_frame1_reg_by1_frm0_char_sn_m1_0_a3_832), + .I1(plm_frm_reg_d2_td[47]), + .I2(plm_frm_reg_d2_td[63]), + .O(plm_frm_frame1_N_6134) + ); + defparam plm_frm_frame1_reg_by1_frm0_char_2_0_am_6_.INIT = 8'hD8; + LUT3 plm_frm_frame1_reg_by1_frm0_char_2_0_am_6_ ( + .I0(plm_frm_frame1_reg_wd_sel[0]), + .I1(plm_frm_reg_d2_td[38]), + .I2(plm_frm_reg_d2_td[54]), + .O(plm_frm_frame1_reg_by1_frm0_char_2_0_am[6]) + ); + defparam plm_frm_frame1_reg_by1_frm0_char_2_0_bm_6_.INIT = 8'hD8; + LUT3 plm_frm_frame1_reg_by1_frm0_char_2_0_bm_6_ ( + .I0(plm_frm_frame1_reg_wd_sel[0]), + .I1(plm_frm_reg_d2_td[6]), + .I2(plm_frm_reg_d2_td[22]), + .O(plm_frm_frame1_reg_by1_frm0_char_2_0_bm[6]) + ); + MUXF5 plm_frm_frame1_reg_by1_frm0_char_2_0_6_ ( + .I0(plm_frm_frame1_reg_by1_frm0_char_2_0_am[6]), + .I1(plm_frm_frame1_reg_by1_frm0_char_2_0_bm[6]), + .O(plm_frm_frame1_N_6194), + .S(plm_frm_frame1_reg_wd_sel[1]) + ); + defparam plm_frm_frame1_reg_by1_frm0_char_2_0_am_5_.INIT = 8'hD8; + LUT3 plm_frm_frame1_reg_by1_frm0_char_2_0_am_5_ ( + .I0(plm_frm_frame1_reg_wd_sel[0]), + .I1(plm_frm_reg_d2_td[37]), + .I2(plm_frm_reg_d2_td[53]), + .O(plm_frm_frame1_reg_by1_frm0_char_2_0_am[5]) + ); + defparam plm_frm_frame1_reg_by1_frm0_char_2_0_bm_5_.INIT = 8'hD8; + LUT3 plm_frm_frame1_reg_by1_frm0_char_2_0_bm_5_ ( + .I0(plm_frm_frame1_reg_wd_sel[0]), + .I1(plm_frm_reg_d2_td[5]), + .I2(plm_frm_reg_d2_td[21]), + .O(plm_frm_frame1_reg_by1_frm0_char_2_0_bm[5]) + ); + MUXF5 plm_frm_frame1_reg_by1_frm0_char_2_0_5_ ( + .I0(plm_frm_frame1_reg_by1_frm0_char_2_0_am[5]), + .I1(plm_frm_frame1_reg_by1_frm0_char_2_0_bm[5]), + .O(plm_frm_frame1_N_6193), + .S(plm_frm_frame1_reg_wd_sel[1]) + ); + defparam plm_frm_frame1_reg_by1_frm0_char_2_0_am_4_.INIT = 8'hD8; + LUT3 plm_frm_frame1_reg_by1_frm0_char_2_0_am_4_ ( + .I0(plm_frm_frame1_reg_wd_sel[0]), + .I1(plm_frm_reg_d2_td[36]), + .I2(plm_frm_reg_d2_td[52]), + .O(plm_frm_frame1_reg_by1_frm0_char_2_0_am[4]) + ); + defparam plm_frm_frame1_reg_by1_frm0_char_2_0_bm_4_.INIT = 8'hD8; + LUT3 plm_frm_frame1_reg_by1_frm0_char_2_0_bm_4_ ( + .I0(plm_frm_frame1_reg_wd_sel[0]), + .I1(plm_frm_reg_d2_td[4]), + .I2(plm_frm_reg_d2_td[20]), + .O(plm_frm_frame1_reg_by1_frm0_char_2_0_bm[4]) + ); + MUXF5 plm_frm_frame1_reg_by1_frm0_char_2_0_4_ ( + .I0(plm_frm_frame1_reg_by1_frm0_char_2_0_am[4]), + .I1(plm_frm_frame1_reg_by1_frm0_char_2_0_bm[4]), + .O(plm_frm_frame1_N_6192), + .S(plm_frm_frame1_reg_wd_sel[1]) + ); + defparam plm_frm_frame1_reg_by1_frm0_char_2_0_am_3_.INIT = 8'hD8; + LUT3 plm_frm_frame1_reg_by1_frm0_char_2_0_am_3_ ( + .I0(plm_frm_frame1_reg_wd_sel[0]), + .I1(plm_frm_reg_d2_td[35]), + .I2(plm_frm_reg_d2_td[51]), + .O(plm_frm_frame1_reg_by1_frm0_char_2_0_am[3]) + ); + defparam plm_frm_frame1_reg_by1_frm0_char_2_0_bm_3_.INIT = 8'hD8; + LUT3 plm_frm_frame1_reg_by1_frm0_char_2_0_bm_3_ ( + .I0(plm_frm_frame1_reg_wd_sel[0]), + .I1(plm_frm_reg_d2_td[3]), + .I2(plm_frm_reg_d2_td[19]), + .O(plm_frm_frame1_reg_by1_frm0_char_2_0_bm[3]) + ); + MUXF5 plm_frm_frame1_reg_by1_frm0_char_2_0_3_ ( + .I0(plm_frm_frame1_reg_by1_frm0_char_2_0_am[3]), + .I1(plm_frm_frame1_reg_by1_frm0_char_2_0_bm[3]), + .O(plm_frm_frame1_N_6191), + .S(plm_frm_frame1_reg_wd_sel[1]) + ); + defparam plm_frm_frame1_reg_by1_frm0_char_2_0_am_2_.INIT = 8'hD8; + LUT3 plm_frm_frame1_reg_by1_frm0_char_2_0_am_2_ ( + .I0(plm_frm_frame1_reg_wd_sel[0]), + .I1(plm_frm_reg_d2_td[34]), + .I2(plm_frm_reg_d2_td[50]), + .O(plm_frm_frame1_reg_by1_frm0_char_2_0_am[2]) + ); + defparam plm_frm_frame1_reg_by1_frm0_char_2_0_bm_2_.INIT = 8'hD8; + LUT3 plm_frm_frame1_reg_by1_frm0_char_2_0_bm_2_ ( + .I0(plm_frm_frame1_reg_wd_sel[0]), + .I1(plm_frm_reg_d2_td[2]), + .I2(plm_frm_reg_d2_td[18]), + .O(plm_frm_frame1_reg_by1_frm0_char_2_0_bm[2]) + ); + MUXF5 plm_frm_frame1_reg_by1_frm0_char_2_0_2_ ( + .I0(plm_frm_frame1_reg_by1_frm0_char_2_0_am[2]), + .I1(plm_frm_frame1_reg_by1_frm0_char_2_0_bm[2]), + .O(plm_frm_frame1_N_6190), + .S(plm_frm_frame1_reg_wd_sel[1]) + ); + defparam plm_frm_frame1_reg_by1_frm0_char_2_0_am_1_.INIT = 8'hD8; + LUT3 plm_frm_frame1_reg_by1_frm0_char_2_0_am_1_ ( + .I0(plm_frm_frame1_reg_wd_sel[0]), + .I1(plm_frm_reg_d2_td[33]), + .I2(plm_frm_reg_d2_td[49]), + .O(plm_frm_frame1_reg_by1_frm0_char_2_0_am[1]) + ); + defparam plm_frm_frame1_reg_by1_frm0_char_2_0_bm_1_.INIT = 8'hD8; + LUT3 plm_frm_frame1_reg_by1_frm0_char_2_0_bm_1_ ( + .I0(plm_frm_frame1_reg_wd_sel[0]), + .I1(plm_frm_reg_d2_td[1]), + .I2(plm_frm_reg_d2_td[17]), + .O(plm_frm_frame1_reg_by1_frm0_char_2_0_bm[1]) + ); + MUXF5 plm_frm_frame1_reg_by1_frm0_char_2_0_1_ ( + .I0(plm_frm_frame1_reg_by1_frm0_char_2_0_am[1]), + .I1(plm_frm_frame1_reg_by1_frm0_char_2_0_bm[1]), + .O(plm_frm_frame1_N_6189), + .S(plm_frm_frame1_reg_wd_sel[1]) + ); + defparam plm_frm_frame1_reg_by1_frm0_char_2_0_am_0_.INIT = 8'hD8; + LUT3 plm_frm_frame1_reg_by1_frm0_char_2_0_am_0_ ( + .I0(plm_frm_frame1_reg_wd_sel[0]), + .I1(plm_frm_reg_d2_td[32]), + .I2(plm_frm_reg_d2_td[48]), + .O(plm_frm_frame1_reg_by1_frm0_char_2_0_am[0]) + ); + defparam plm_frm_frame1_reg_by1_frm0_char_2_0_bm_0_.INIT = 8'hD8; + LUT3 plm_frm_frame1_reg_by1_frm0_char_2_0_bm_0_ ( + .I0(plm_frm_frame1_reg_wd_sel[0]), + .I1(plm_frm_reg_d2_td[0]), + .I2(plm_frm_reg_d2_td[16]), + .O(plm_frm_frame1_reg_by1_frm0_char_2_0_bm[0]) + ); + MUXF5 plm_frm_frame1_reg_by1_frm0_char_2_0_0_ ( + .I0(plm_frm_frame1_reg_by1_frm0_char_2_0_am[0]), + .I1(plm_frm_frame1_reg_by1_frm0_char_2_0_bm[0]), + .O(plm_frm_frame1_N_6188), + .S(plm_frm_frame1_reg_wd_sel[1]) + ); + defparam plm_frm_frame1_un1_reg_by1_frm0_char_1_sqmuxa_2_0.INIT = 16'h3F5F; + LUT4 plm_frm_frame1_un1_reg_by1_frm0_char_1_sqmuxa_2_0 ( + .I0(plm_frm_frame1_reg_byp1_843), + .I1(plm_frm_frame1_reg_byp3_842), + .I2(plm_frm_frame1_reg_wd_sel[0]), + .I3(plm_frm_frame1_reg_wd_sel[1]), + .O(plm_frm_frame1_un1_reg_by1_frm0_char_1_sqmuxa_2_0_824) + ); + defparam plm_frm_frame1_reg_by1_frm0_char_2_0_am_7_.INIT = 8'hD8; + LUT3 plm_frm_frame1_reg_by1_frm0_char_2_0_am_7_ ( + .I0(plm_frm_frame1_reg_wd_sel[0]), + .I1(plm_frm_reg_d2_td[39]), + .I2(plm_frm_reg_d2_td[55]), + .O(plm_frm_frame1_reg_by1_frm0_char_2_0_am[7]) + ); + defparam plm_frm_frame1_reg_by1_frm0_char_2_0_bm_7_.INIT = 8'hD8; + LUT3 plm_frm_frame1_reg_by1_frm0_char_2_0_bm_7_ ( + .I0(plm_frm_frame1_reg_wd_sel[0]), + .I1(plm_frm_reg_d2_td[7]), + .I2(plm_frm_reg_d2_td[23]), + .O(plm_frm_frame1_reg_by1_frm0_char_2_0_bm[7]) + ); + MUXF5 plm_frm_frame1_reg_by1_frm0_char_2_0_7_ ( + .I0(plm_frm_frame1_reg_by1_frm0_char_2_0_am[7]), + .I1(plm_frm_frame1_reg_by1_frm0_char_2_0_bm[7]), + .O(plm_frm_frame1_N_6195), + .S(plm_frm_frame1_reg_wd_sel[1]) + ); + defparam plm_frm_frame1_reg_by1_frm0_is_k_2_1_.INIT = 4'h1; + LUT2_L plm_frm_frame1_reg_by1_frm0_is_k_2_1_ ( + .I0(plm_frm_by1_opportunity_h_792), + .I1(plm_frm_reg_d2_charisk_7__819), + .LO(plm_frm_frame1_N_9975) + ); + defparam plm_frm_frame1_un1_reg_by1_frm0_char_1_sqmuxa_2_1.INIT = 16'hDF00; + LUT4_L plm_frm_frame1_un1_reg_by1_frm0_char_1_sqmuxa_2_1 ( + .I0(plm_frm_by1_opportunity_l_791), + .I1(plm_frm_frame1_reg_wd_sel[0]), + .I2(plm_frm_frame1_reg_wd_sel[1]), + .I3(plm_frm_frame1_un1_reg_by1_frm0_char_1_sqmuxa_2_0_824), + .LO(plm_frm_frame1_un1_reg_by1_frm0_char_1_sqmuxa_2_1_825) + ); + defparam plm_frm_frame1_reg_by1_frm0_char_sn_m6_i.INIT = 16'h0035; + LUT4 plm_frm_frame1_reg_by1_frm0_char_sn_m6_i ( + .I0(plm_frm_by1_opportunity_h_792), + .I1(plm_frm_frame1_reg_byp1_843), + .I2(plm_frm_frame1_reg_wd_sel[0]), + .I3(plm_frm_frame1_reg_wd_sel[1]), + .O(plm_frm_frame1_reg_by1_frm0_char_sn_m6_i_838) + ); + defparam plm_frm_frame1_reg_by1_frm0_char_sn_m9_i.INIT = 16'h3500; + LUT4 plm_frm_frame1_reg_by1_frm0_char_sn_m9_i ( + .I0(plm_frm_by1_opportunity_l_791), + .I1(plm_frm_frame1_reg_byp3_842), + .I2(plm_frm_frame1_reg_wd_sel[0]), + .I3(plm_frm_frame1_reg_wd_sel[1]), + .O(plm_frm_frame1_reg_by1_frm0_char_sn_m9_i_839) + ); + defparam plm_frm_frame1_by1_frm0_is_k_3_0_am_0_.INIT = 8'hCA; + LUT3 plm_frm_frame1_by1_frm0_is_k_3_0_am_0_ ( + .I0(plm_frm_by1_opportunity_h_792), + .I1(plm_frm_by1_opportunity_l_791), + .I2(plm_frm_frame1_reg_wd_sel[1]), + .O(plm_frm_frame1_by1_frm0_is_k_3_0_am[0]) + ); + defparam plm_frm_frame1_by1_frm0_is_k_3_0_bm_0_.INIT = 16'hF5C5; + LUT4 plm_frm_frame1_by1_frm0_is_k_3_0_bm_0_ ( + .I0(plm_frm_frame1_N_9974), + .I1(plm_frm_frame1_reg_byp3_842), + .I2(plm_frm_frame1_reg_wd_sel[1]), + .I3(plm_frm_reg_d2_charisk_0__817), + .O(plm_frm_frame1_by1_frm0_is_k_3_0_bm[0]) + ); + MUXF5 plm_frm_frame1_by1_frm0_is_k_3_0_0_ ( + .I0(plm_frm_frame1_by1_frm0_is_k_3_0_am[0]), + .I1(plm_frm_frame1_by1_frm0_is_k_3_0_bm[0]), + .O(plm_frm_by1_frm0_is_k[0]), + .S(plm_frm_frame1_reg_wd_sel[0]) + ); + defparam plm_frm_frame1_un1_reg_by1_frm0_char_1_sqmuxa_2.INIT = 16'hFD00; + LUT4 plm_frm_frame1_un1_reg_by1_frm0_char_1_sqmuxa_2 ( + .I0(plm_frm_by1_opportunity_h_792), + .I1(plm_frm_frame1_reg_wd_sel[0]), + .I2(plm_frm_frame1_reg_wd_sel[1]), + .I3(plm_frm_frame1_un1_reg_by1_frm0_char_1_sqmuxa_2_1_825), + .O(plm_frm_frame1_N_9971) + ); + defparam plm_frm_frame1_by1_frm0_is_k_3_0_am_1_.INIT = 16'hF5C5; + LUT4 plm_frm_frame1_by1_frm0_is_k_3_0_am_1_ ( + .I0(plm_frm_frame1_N_9975), + .I1(plm_frm_by1_opportunity_l_791), + .I2(plm_frm_frame1_reg_wd_sel[1]), + .I3(plm_frm_reg_d2_charisk_3__823), + .O(plm_frm_frame1_by1_frm0_is_k_3_0_am[1]) + ); + defparam plm_frm_frame1_by1_frm0_is_k_3_0_bm_1_.INIT = 8'hCA; + LUT3 plm_frm_frame1_by1_frm0_is_k_3_0_bm_1_ ( + .I0(plm_frm_frame1_reg_byp1_843), + .I1(plm_frm_frame1_reg_byp3_842), + .I2(plm_frm_frame1_reg_wd_sel[1]), + .O(plm_frm_frame1_by1_frm0_is_k_3_0_bm[1]) + ); + MUXF5 plm_frm_frame1_by1_frm0_is_k_3_0_1_ ( + .I0(plm_frm_frame1_by1_frm0_is_k_3_0_am[1]), + .I1(plm_frm_frame1_by1_frm0_is_k_3_0_bm[1]), + .O(plm_frm_by1_frm0_is_k[1]), + .S(plm_frm_frame1_reg_wd_sel[0]) + ); + defparam plm_frm_frame1_reg_by1_frm0_char_2_am_14_.INIT = 16'hA280; + LUT4 plm_frm_frame1_reg_by1_frm0_char_2_am_14_ ( + .I0(plm_frm_frame1_reg_by1_frm0_char_sn_m6_i_838), + .I1(plm_frm_frame1_reg_wd_sel[0]), + .I2(plm_frm_reg_d2_td[46]), + .I3(plm_frm_reg_d2_td[62]), + .O(plm_frm_frame1_reg_by1_frm0_char_2_am[14]) + ); + defparam plm_frm_frame1_reg_by1_frm0_char_2_bm_14_.INIT = 8'hD8; + LUT3 plm_frm_frame1_reg_by1_frm0_char_2_bm_14_ ( + .I0(plm_frm_frame1_reg_wd_sel[0]), + .I1(plm_frm_reg_d2_td[14]), + .I2(plm_frm_reg_d2_td[30]), + .O(plm_frm_frame1_reg_by1_frm0_char_2_bm[14]) + ); + MUXF5 plm_frm_frame1_reg_by1_frm0_char_2_14_ ( + .I0(plm_frm_frame1_reg_by1_frm0_char_2_am[14]), + .I1(plm_frm_frame1_reg_by1_frm0_char_2_bm[14]), + .O(plm_frm_by1_frm0_char_14_), + .S(plm_frm_frame1_reg_by1_frm0_char_sn_m9_i_839) + ); + defparam plm_frm_frame1_reg_by1_frm0_char_1_am_9_.INIT = 16'hC480; + LUT4 plm_frm_frame1_reg_by1_frm0_char_1_am_9_ ( + .I0(plm_frm_frame1_reg_by1_frm0_char_sn_m1_0_a3_832), + .I1(plm_frm_frame1_reg_by1_frm0_char_sn_m6_i_838), + .I2(plm_frm_reg_d2_td[41]), + .I3(plm_frm_reg_d2_td[57]), + .O(plm_frm_frame1_reg_by1_frm0_char_1_am[9]) + ); + defparam plm_frm_frame1_reg_by1_frm0_char_1_bm_9_.INIT = 16'hFB40; + LUT4 plm_frm_frame1_reg_by1_frm0_char_1_bm_9_ ( + .I0(plm_frm_frame1_reg_byp3_842), + .I1(plm_frm_frame1_reg_wd_sel[0]), + .I2(plm_frm_reg_d2_td[9]), + .I3(plm_frm_reg_d2_td[25]), + .O(plm_frm_frame1_reg_by1_frm0_char_1_bm[9]) + ); + MUXF5 plm_frm_frame1_reg_by1_frm0_char_1_9_ ( + .I0(plm_frm_frame1_reg_by1_frm0_char_1_am[9]), + .I1(plm_frm_frame1_reg_by1_frm0_char_1_bm[9]), + .O(plm_frm_by1_frm0_char_9_), + .S(plm_frm_frame1_reg_by1_frm0_char_sn_m9_i_839) + ); + defparam plm_frm_frame1_reg_by1_frm0_char_0_am_10_.INIT = 16'hF7B3; + LUT4 plm_frm_frame1_reg_by1_frm0_char_0_am_10_ ( + .I0(plm_frm_frame1_reg_by1_frm0_char_sn_m1_0_a3_832), + .I1(plm_frm_frame1_reg_by1_frm0_char_sn_m6_i_838), + .I2(plm_frm_reg_d2_td[42]), + .I3(plm_frm_reg_d2_td[58]), + .O(plm_frm_frame1_reg_by1_frm0_char_0_am_10__827) + ); + defparam plm_frm_frame1_reg_by1_frm0_char_0_bm_10_.INIT = 16'hFB40; + LUT4 plm_frm_frame1_reg_by1_frm0_char_0_bm_10_ ( + .I0(plm_frm_frame1_reg_byp3_842), + .I1(plm_frm_frame1_reg_wd_sel[0]), + .I2(plm_frm_reg_d2_td[10]), + .I3(plm_frm_reg_d2_td[26]), + .O(plm_frm_frame1_reg_by1_frm0_char_0_bm_10__826) + ); + MUXF5 plm_frm_frame1_reg_by1_frm0_char_0_10_ ( + .I0(plm_frm_frame1_reg_by1_frm0_char_0_am_10__827), + .I1(plm_frm_frame1_reg_by1_frm0_char_0_bm_10__826), + .O(plm_frm_by1_frm0_char_10_), + .S(plm_frm_frame1_reg_by1_frm0_char_sn_m9_i_839) + ); + defparam plm_frm_frame1_reg_by1_frm0_char_0_am_12_.INIT = 16'hF7B3; + LUT4 plm_frm_frame1_reg_by1_frm0_char_0_am_12_ ( + .I0(plm_frm_frame1_reg_by1_frm0_char_sn_m1_0_a3_832), + .I1(plm_frm_frame1_reg_by1_frm0_char_sn_m6_i_838), + .I2(plm_frm_reg_d2_td[44]), + .I3(plm_frm_reg_d2_td[60]), + .O(plm_frm_frame1_reg_by1_frm0_char_0_am_12__829) + ); + defparam plm_frm_frame1_reg_by1_frm0_char_0_bm_12_.INIT = 16'hFB40; + LUT4 plm_frm_frame1_reg_by1_frm0_char_0_bm_12_ ( + .I0(plm_frm_frame1_reg_byp3_842), + .I1(plm_frm_frame1_reg_wd_sel[0]), + .I2(plm_frm_reg_d2_td[12]), + .I3(plm_frm_reg_d2_td[28]), + .O(plm_frm_frame1_reg_by1_frm0_char_0_bm_12__828) + ); + MUXF5 plm_frm_frame1_reg_by1_frm0_char_0_12_ ( + .I0(plm_frm_frame1_reg_by1_frm0_char_0_am_12__829), + .I1(plm_frm_frame1_reg_by1_frm0_char_0_bm_12__828), + .O(plm_frm_by1_frm0_char_12_), + .S(plm_frm_frame1_reg_by1_frm0_char_sn_m9_i_839) + ); + defparam plm_frm_frame1_reg_by1_frm0_char_0_am_8_.INIT = 16'hC480; + LUT4 plm_frm_frame1_reg_by1_frm0_char_0_am_8_ ( + .I0(plm_frm_frame1_reg_by1_frm0_char_sn_m1_0_a3_832), + .I1(plm_frm_frame1_reg_by1_frm0_char_sn_m6_i_838), + .I2(plm_frm_reg_d2_td[40]), + .I3(plm_frm_reg_d2_td[56]), + .O(plm_frm_frame1_reg_by1_frm0_char_0_am_8__831) + ); + defparam plm_frm_frame1_reg_by1_frm0_char_0_bm_8_.INIT = 16'hFB40; + LUT4 plm_frm_frame1_reg_by1_frm0_char_0_bm_8_ ( + .I0(plm_frm_frame1_reg_byp3_842), + .I1(plm_frm_frame1_reg_wd_sel[0]), + .I2(plm_frm_reg_d2_td[8]), + .I3(plm_frm_reg_d2_td[24]), + .O(plm_frm_frame1_reg_by1_frm0_char_0_bm_8__830) + ); + MUXF5 plm_frm_frame1_reg_by1_frm0_char_0_8_ ( + .I0(plm_frm_frame1_reg_by1_frm0_char_0_am_8__831), + .I1(plm_frm_frame1_reg_by1_frm0_char_0_bm_8__830), + .O(plm_frm_by1_frm0_char_8_), + .S(plm_frm_frame1_reg_by1_frm0_char_sn_m9_i_839) + ); + defparam plm_frm_frame1_reg_by1_frm0_char_0_am_11_.INIT = 16'hF7B3; + LUT4 plm_frm_frame1_reg_by1_frm0_char_0_am_11_ ( + .I0(plm_frm_frame1_reg_by1_frm0_char_sn_m1_0_a3_832), + .I1(plm_frm_frame1_reg_by1_frm0_char_sn_m6_i_838), + .I2(plm_frm_reg_d2_td[43]), + .I3(plm_frm_reg_d2_td[59]), + .O(plm_frm_frame1_reg_by1_frm0_char_0_am_11__834) + ); + defparam plm_frm_frame1_reg_by1_frm0_char_0_bm_11_.INIT = 16'hFB40; + LUT4 plm_frm_frame1_reg_by1_frm0_char_0_bm_11_ ( + .I0(plm_frm_frame1_reg_byp3_842), + .I1(plm_frm_frame1_reg_wd_sel[0]), + .I2(plm_frm_reg_d2_td[11]), + .I3(plm_frm_reg_d2_td[27]), + .O(plm_frm_frame1_reg_by1_frm0_char_0_bm_11__833) + ); + MUXF5 plm_frm_frame1_reg_by1_frm0_char_0_11_ ( + .I0(plm_frm_frame1_reg_by1_frm0_char_0_am_11__834), + .I1(plm_frm_frame1_reg_by1_frm0_char_0_bm_11__833), + .O(plm_frm_by1_frm0_char_11_), + .S(plm_frm_frame1_reg_by1_frm0_char_sn_m9_i_839) + ); + defparam plm_frm_frame1_reg_by1_frm0_char_0_am_13_.INIT = 8'h8B; + LUT3 plm_frm_frame1_reg_by1_frm0_char_0_am_13_ ( + .I0(plm_frm_frame1_N_6132), + .I1(plm_frm_frame1_reg_by1_frm0_char_sn_m6_i_838), + .I2(plm_frm_frame1_reg_by1_frm0_char_sn_m4_i_a3_837), + .O(plm_frm_frame1_reg_by1_frm0_char_0_am_13__836) + ); + defparam plm_frm_frame1_reg_by1_frm0_char_0_bm_13_.INIT = 16'hFB40; + LUT4 plm_frm_frame1_reg_by1_frm0_char_0_bm_13_ ( + .I0(plm_frm_frame1_reg_byp3_842), + .I1(plm_frm_frame1_reg_wd_sel[0]), + .I2(plm_frm_reg_d2_td[13]), + .I3(plm_frm_reg_d2_td[29]), + .O(plm_frm_frame1_reg_by1_frm0_char_0_bm_13__835) + ); + MUXF5 plm_frm_frame1_reg_by1_frm0_char_0_13_ ( + .I0(plm_frm_frame1_reg_by1_frm0_char_0_am_13__836), + .I1(plm_frm_frame1_reg_by1_frm0_char_0_bm_13__835), + .O(plm_frm_by1_frm0_char_13_), + .S(plm_frm_frame1_reg_by1_frm0_char_sn_m9_i_839) + ); + defparam plm_frm_frame1_reg_by1_frm0_char_0_am_15_.INIT = 8'h8B; + LUT3 plm_frm_frame1_reg_by1_frm0_char_0_am_15_ ( + .I0(plm_frm_frame1_N_6134), + .I1(plm_frm_frame1_reg_by1_frm0_char_sn_m6_i_838), + .I2(plm_frm_frame1_reg_by1_frm0_char_sn_m4_i_a3_837), + .O(plm_frm_frame1_reg_by1_frm0_char_0_am_15__841) + ); + defparam plm_frm_frame1_reg_by1_frm0_char_0_bm_15_.INIT = 16'hFB40; + LUT4 plm_frm_frame1_reg_by1_frm0_char_0_bm_15_ ( + .I0(plm_frm_frame1_reg_byp3_842), + .I1(plm_frm_frame1_reg_wd_sel[0]), + .I2(plm_frm_reg_d2_td[15]), + .I3(plm_frm_reg_d2_td[31]), + .O(plm_frm_frame1_reg_by1_frm0_char_0_bm_15__840) + ); + MUXF5 plm_frm_frame1_reg_by1_frm0_char_0_15_ ( + .I0(plm_frm_frame1_reg_by1_frm0_char_0_am_15__841), + .I1(plm_frm_frame1_reg_by1_frm0_char_0_bm_15__840), + .O(plm_frm_by1_frm0_char_15_), + .S(plm_frm_frame1_reg_by1_frm0_char_sn_m9_i_839) + ); + defparam plm_frm_frame1_by1_frm_atomic_u.INIT = 16'h0C0A; + LUT4_L plm_frm_frame1_by1_frm_atomic_u ( + .I0(plm_frm_by1_opportunity_h_792), + .I1(plm_frm_by1_opportunity_l_791), + .I2(plm_frm_frame1_reg_wd_sel[0]), + .I3(plm_frm_frame1_reg_wd_sel[1]), + .LO(plm_frm_by1_frm_atomic) + ); + defparam plm_frm_frame1_reg_by1_frm0_char_7_.INIT = 4'h8; + LUT2_L plm_frm_frame1_reg_by1_frm0_char_7_ ( + .I0(plm_frm_frame1_N_6195), + .I1(plm_frm_frame1_N_9971), + .LO(plm_frm_by1_frm0_char_7_) + ); + defparam plm_frm_frame1_reg_by1_frm0_char_6_.INIT = 4'h8; + LUT2_L plm_frm_frame1_reg_by1_frm0_char_6_ ( + .I0(plm_frm_frame1_N_6194), + .I1(plm_frm_frame1_N_9971), + .LO(plm_frm_by1_frm0_char_6_) + ); + defparam plm_frm_frame1_reg_by1_frm0_char_5_.INIT = 4'h8; + LUT2_L plm_frm_frame1_reg_by1_frm0_char_5_ ( + .I0(plm_frm_frame1_N_6193), + .I1(plm_frm_frame1_N_9971), + .LO(plm_frm_by1_frm0_char_5_) + ); + defparam plm_frm_frame1_N_8665_i.INIT = 4'hB; + LUT2_L plm_frm_frame1_N_8665_i ( + .I0(plm_frm_frame1_N_6192), + .I1(plm_frm_frame1_N_9971), + .LO(plm_frm_N_8665_i) + ); + defparam plm_frm_frame1_N_8666_i.INIT = 4'hB; + LUT2_L plm_frm_frame1_N_8666_i ( + .I0(plm_frm_frame1_N_6191), + .I1(plm_frm_frame1_N_9971), + .LO(plm_frm_N_8666_i) + ); + defparam plm_frm_frame1_N_8667_i.INIT = 4'hB; + LUT2_L plm_frm_frame1_N_8667_i ( + .I0(plm_frm_frame1_N_6190), + .I1(plm_frm_frame1_N_9971), + .LO(plm_frm_N_8667_i) + ); + defparam plm_frm_frame1_reg_by1_frm0_char_1_.INIT = 4'h8; + LUT2_L plm_frm_frame1_reg_by1_frm0_char_1_ ( + .I0(plm_frm_frame1_N_6189), + .I1(plm_frm_frame1_N_9971), + .LO(plm_frm_by1_frm0_char_1_) + ); + defparam plm_frm_frame1_reg_by1_frm0_char_0_.INIT = 4'h8; + LUT2_L plm_frm_frame1_reg_by1_frm0_char_0_ ( + .I0(plm_frm_frame1_N_6188), + .I1(plm_frm_frame1_N_9971), + .LO(plm_frm_by1_frm0_char_0_) + ); + defparam plm_frm_frame1_sel_sequencer_reg_wd_sel_5_1_.INIT = 8'h06; + LUT3_L plm_frm_frame1_sel_sequencer_reg_wd_sel_5_1_ ( + .I0(plm_frm_frame1_reg_wd_sel[0]), + .I1(plm_frm_frame1_reg_wd_sel[1]), + .I2(plm_phy_cke_0_402), + .LO(plm_frm_frame1_reg_wd_sel_5[1]) + ); + defparam plm_frm_frame1_sel_sequencer_reg_wd_sel_5_0_.INIT = 4'h1; + LUT2_L plm_frm_frame1_sel_sequencer_reg_wd_sel_5_0_ ( + .I0(plm_frm_frame1_reg_wd_sel[0]), + .I1(plm_phy_cke_0_402), + .LO(plm_frm_frame1_reg_wd_sel_5[0]) + ); + FDC plm_frm_frame1_reg_byp3 ( + .C(mgt_clk), + .D(plm_frm_by1_opportunity_l_791), + .Q(plm_frm_frame1_reg_byp3_842), + .CLR(plm_rst) + ); + FDC plm_frm_frame1_reg_byp1 ( + .C(mgt_clk), + .D(plm_frm_by1_opportunity_h_792), + .Q(plm_frm_frame1_reg_byp1_843), + .CLR(plm_rst) + ); + FDC plm_frm_frame1_reg_wd_sel_1_ ( + .C(mgt_clk), + .D(plm_frm_frame1_reg_wd_sel_5[1]), + .Q(plm_frm_frame1_reg_wd_sel[1]), + .CLR(plm_rst) + ); + FDC plm_frm_frame1_reg_wd_sel_0_ ( + .C(mgt_clk), + .D(plm_frm_frame1_reg_wd_sel_5[0]), + .Q(plm_frm_frame1_reg_wd_sel[0]), + .CLR(plm_rst) + ); + VCC plm_fsm_VCC ( + .P(plm_fsm_VCC_891) + ); + defparam plm_fsm_fsm_vector_reg_123_link_pad_36_0_a2_i_0_a3_0.INIT = 4'h2; + LUT2 plm_fsm_fsm_vector_reg_123_link_pad_36_0_a2_i_0_a3_0 ( + .I0(plm_fsm_reg_state_8__873), + .I1(plm_rx0_ts2_c), + .O(plm_fsm_N_39029) + ); + defparam plm_fsm_fsm_vector_reg_rx_clear_cs_98_0_0_0_1_iv_i_o3_4_1_0_o3_0.INIT = 4'h8; + LUT2 plm_fsm_fsm_vector_reg_rx_clear_cs_98_0_0_0_1_iv_i_o3_4_1_0_o3_0 ( + .I0(plm_fsm_reg_state_8__873), + .I1(plm_rx0_ts2_c), + .O(plm_fsm_N_38117_i) + ); + defparam plm_fsm_un1_reg_state_15_i_0_o3.INIT = 4'h1; + LUT2 plm_fsm_un1_reg_state_15_i_0_o3 ( + .I0(plm_fsm_reg_state_0__879), + .I1(plm_fsm_reg_state_2__356), + .O(plm_fsm_N_38203_i) + ); + defparam plm_fsm_reg_rx_clear_cs_1_sqmuxa_1_i_i_a2_0_a4_1.INIT = 4'h4; + LUT2 plm_fsm_reg_rx_clear_cs_1_sqmuxa_1_i_i_a2_0_a4_1 ( + .I0(plm_fsm_cc_cntrout0), + .I1(plm_fsm_reg_state_9__910), + .O(plm_fsm_N_38735_1) + ); + defparam plm_fsm_un1_reg_state_22_i_0_0_o4.INIT = 4'h1; + LUT2 plm_fsm_un1_reg_state_22_i_0_0_o4 ( + .I0(plm_fsm_reg_state_9__910), + .I1(plm_fsm_reg_state_10__886), + .O(N_38123_i) + ); + defparam plm_fsm_un1_reg_state_22_i_0_0_o4_1.INIT = 4'h1; + LUT2 plm_fsm_un1_reg_state_22_i_0_0_o4_1 ( + .I0(plm_link_ctrl[0]), + .I1(plm_link_l0), + .O(plm_fsm_N_38241_i) + ); + defparam plm_fsm_fsm_vector_reg_send_command_28_0_a2_0_a2_0_a2_0_o3_2_.INIT = 4'h1; + LUT2 plm_fsm_fsm_vector_reg_send_command_28_0_a2_0_a2_0_a2_0_o3_2_ ( + .I0(plm_fsm_reg_state_11__360), + .I1(plm_fsm_reg_state_16__357), + .O(plm_fsm_N_38173_i) + ); + defparam plm_fsm_fsm_vector_reg_state_141_0_0_0_2_iv_i_0_o3_1_3_.INIT = 4'h8; + LUT2 plm_fsm_fsm_vector_reg_state_141_0_0_0_2_iv_i_0_o3_1_3_ ( + .I0(plm_reg_ts1_1), + .I1(plm_rx0_lane_pad), + .O(plm_fsm_reg_state_141_0_0_0_2_iv_i_0_o3_1[3]) + ); + defparam plm_fsm_fsm_vector_reg_state_141_0_0_0_1_iv_0_0_0_o3_0_8_.INIT = 4'h1; + LUT2 plm_fsm_fsm_vector_reg_state_141_0_0_0_1_iv_0_0_0_o3_0_8_ ( + .I0(plm_tx0_lane_pad), + .I1(plm_tx0_link_pad), + .O(plm_fsm_N_38126_i) + ); + defparam plm_fsm_ci_idle_data_i_o3_i_a4_0.INIT = 4'h8; + LUT2_L plm_fsm_ci_idle_data_i_o3_i_a4_0 ( + .I0(plm_fsm_ci_cntrout1), + .I1(plm_fsm_ci_cntrout3), + .LO(plm_fsm_ci_idle_data_i_o3_i_a4_0_847) + ); + defparam plm_fsm_xl_lanenum_changes_N_38556_i.INIT = 4'hE; + LUT2 plm_fsm_xl_lanenum_changes_N_38556_i ( + .I0(plm_fsm_reg_state_22__881), + .I1(plm_fsm_reg_state_24__887), + .O(plm_fsm_N_38556_i) + ); + defparam plm_fsm_lanenum_changes_N_38583_i.INIT = 4'hE; + LUT2 plm_fsm_lanenum_changes_N_38583_i ( + .I0(plm_fsm_reg_state_6__875), + .I1(plm_fsm_reg_state_8__873), + .O(plm_fsm_N_38583_i) + ); + defparam plm_fsm_fsm_vector_reg_state_141_0_0_0_0_iv_i_0_0_o3_0_15_.INIT = 8'hC4; + LUT3 plm_fsm_fsm_vector_reg_state_141_0_0_0_0_iv_i_0_0_o3_0_15_ ( + .I0(NlwRenamedSig_OI_cfg_lcommand_7_), + .I1(plm_fsm_rl_cntrout0), + .I2(plm_fsm_rl_extdout), + .O(plm_fsm_N_38122_i) + ); + defparam plm_fsm_fsm_vector_reg_state_141_0_0_0_0_iv_i_0_0_a4_0_17_.INIT = 8'h80; + LUT3 plm_fsm_fsm_vector_reg_state_141_0_0_0_0_iv_i_0_0_a4_0_17_ ( + .I0(plm_fsm_reg_state_16__357), + .I1(plm_rx0_linkctrl_0_), + .I2(plm_rx0_ts1_c), + .O(plm_fsm_N_38471) + ); + defparam plm_fsm_reg_rx_clear_cs_2_sqmuxa_i_i_a2_0_a4_1.INIT = 8'h10; + LUT3 plm_fsm_reg_rx_clear_cs_2_sqmuxa_i_i_a2_0_a4_1 ( + .I0(plm_fsm_reg_expired), + .I1(plm_fsm_rc_cntrout_ts2_0), + .I2(plm_fsm_reg_state_14__909), + .O(plm_fsm_N_38733_1) + ); + defparam plm_fsm_fsm_vector_reg_state_141_0_0_0_1_iv_i_0_0_o3_1_16_.INIT = 8'hE0; + LUT3 plm_fsm_fsm_vector_reg_state_141_0_0_0_1_iv_i_0_0_o3_1_16_ ( + .I0(plm_rx0_lane_pad), + .I1(plm_rx0_linkctrl_0_), + .I2(plm_rx0_ts1_c), + .O(plm_fsm_N_38245_i) + ); + defparam plm_fsm_un3_l0_exit_reason_i_o2_0_0_o4.INIT = 8'hA2; + LUT3 plm_fsm_un3_l0_exit_reason_i_o2_0_0_o4 ( + .I0(plm_fsm_N_38095_i), + .I1(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_num[2]), + .I2(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_num_2_q[0]), + .O(plm_fsm_N_38139_i) + ); + defparam plm_fsm_fsm_vector_reg_state_141_0_0_0_0_iv_i_0_o3_4_.INIT = 8'h20; + LUT3 plm_fsm_fsm_vector_reg_state_141_0_0_0_0_iv_i_0_o3_4_ ( + .I0(plm_rx0_lane_pad), + .I1(plm_rx0_link_pad), + .I2(plm_rx0_ts1_c), + .O(plm_fsm_N_38118_i) + ); + defparam plm_fsm_un1_reg_state_14_i_0_0_0.INIT = 8'h2A; + LUT3 plm_fsm_un1_reg_state_14_i_0_0_0 ( + .I0(plm_link_ctrl[0]), + .I1(plm_rx0_linkctrl_0_), + .I2(plm_rx0_ts1_c), + .O(plm_fsm_N_18398_i) + ); + defparam plm_fsm_fsm_vector_reg_state_141_0_0_0_1_iv_0_0_0_a3_2_8_.INIT = 8'h80; + LUT3 plm_fsm_fsm_vector_reg_state_141_0_0_0_1_iv_0_0_0_a3_2_8_ ( + .I0(plm_rx0_lane_pad), + .I1(plm_rx0_link_pad), + .I2(plm_rx0_ts1_c), + .O(plm_fsm_N_39043) + ); + defparam plm_fsm_fsm_vector_reg_state_141_0_0_0_1_iv_i_i_i_a4_1_1_0_9_.INIT = 8'h80; + LUT3 plm_fsm_fsm_vector_reg_state_141_0_0_0_1_iv_i_i_i_a4_1_1_0_9_ ( + .I0(cfg_cfg_5072[505]), + .I1(plm_fsm_pc_cntrout0), + .I2(plm_fsm_reg_state_2__356), + .O(plm_fsm_N_38611_1_0) + ); + defparam plm_fsm_fsm_vector_reg_state67.INIT = 8'h01; + LUT3 plm_fsm_fsm_vector_reg_state67 ( + .I0(plm_fsm_pa_cntrout1), + .I1(plm_fsm_pa_cntrout2), + .I2(plm_fsm_pa_cntrout3), + .O(plm_fsm_N_9824) + ); + defparam plm_fsm_fsm_vector_reg_state_141_0_0_0_0_iv_i_0_a4_0_0_10_.INIT = 8'h80; + LUT3 plm_fsm_fsm_vector_reg_state_141_0_0_0_0_iv_i_0_a4_0_0_10_ ( + .I0(plm_fsm_pc_cntrout1), + .I1(plm_fsm_pc_cntrout2), + .I2(plm_fsm_pc_cntrout3), + .O(plm_fsm_reg_state_141_0_0_0_0_iv_i_0_a4_0_0[10]) + ); + defparam plm_fsm_un1_linklanematch0_NE_0.INIT = 16'h8421; + LUT4 plm_fsm_un1_linklanematch0_NE_0 ( + .I0(plm_rx0_link_num[2]), + .I1(plm_rx0_link_num[3]), + .I2(plm_reg_tx_link_num[2]), + .I3(plm_reg_tx_link_num[3]), + .O(plm_fsm_un1_linklanematch0_NE_0_851) + ); + defparam plm_fsm_un1_linklanematch0_NE_1.INIT = 16'h8421; + LUT4 plm_fsm_un1_linklanematch0_NE_1 ( + .I0(plm_rx0_link_num[4]), + .I1(plm_rx0_link_num[5]), + .I2(plm_reg_tx_link_num[4]), + .I3(plm_reg_tx_link_num[5]), + .O(plm_fsm_un1_linklanematch0_NE_1_850) + ); + defparam plm_fsm_un1_linklanematch0_NE_2.INIT = 16'h8421; + LUT4 plm_fsm_un1_linklanematch0_NE_2 ( + .I0(plm_rx0_link_num[0]), + .I1(plm_rx0_link_num[1]), + .I2(plm_reg_tx_link_num[0]), + .I3(plm_reg_tx_link_num[1]), + .O(plm_fsm_un1_linklanematch0_NE_2_849) + ); + defparam plm_fsm_un1_linklanematch0_NE_3.INIT = 16'h8421; + LUT4 plm_fsm_un1_linklanematch0_NE_3 ( + .I0(plm_rx0_link_num[6]), + .I1(plm_rx0_link_num[7]), + .I2(plm_reg_tx_link_num[6]), + .I3(plm_reg_tx_link_num[7]), + .O(plm_fsm_un1_linklanematch0_NE_3_848) + ); + defparam plm_fsm_un3_xl_clw0_newv_NE_0.INIT = 16'h8421; + LUT4 plm_fsm_un3_xl_clw0_newv_NE_0 ( + .I0(plm_fsm_reg_xl_rx0_old[4]), + .I1(plm_fsm_reg_xl_rx0_old[5]), + .I2(plm_rx0_lane_num[4]), + .I3(plm_rx0_lane_num[5]), + .O(plm_fsm_un3_xl_clw0_newv_NE_0_858) + ); + defparam plm_fsm_un3_xl_clw0_newv_NE_1.INIT = 16'h8421; + LUT4 plm_fsm_un3_xl_clw0_newv_NE_1 ( + .I0(plm_fsm_reg_xl_rx0_old[2]), + .I1(plm_fsm_reg_xl_rx0_old[3]), + .I2(plm_rx0_lane_num[2]), + .I3(plm_rx0_lane_num[3]), + .O(plm_fsm_un3_xl_clw0_newv_NE_1_857) + ); + defparam plm_fsm_un3_xl_clw0_newv_NE_2.INIT = 16'h8421; + LUT4 plm_fsm_un3_xl_clw0_newv_NE_2 ( + .I0(plm_fsm_reg_xl_rx0_old[6]), + .I1(plm_fsm_reg_xl_rx0_old[7]), + .I2(plm_rx0_lane_num[6]), + .I3(plm_rx0_lane_num[7]), + .O(plm_fsm_un3_xl_clw0_newv_NE_2_856) + ); + defparam plm_fsm_un3_xl_clw0_newv_NE_3.INIT = 16'h8421; + LUT4_L plm_fsm_un3_xl_clw0_newv_NE_3 ( + .I0(plm_fsm_reg_xl_rx0_old[0]), + .I1(plm_fsm_reg_xl_rx0_old[1]), + .I2(plm_rx0_lane_num[0]), + .I3(plm_rx0_lane_num[1]), + .LO(plm_fsm_un3_xl_clw0_newv_NE_3_845) + ); + defparam plm_fsm_un3_clw0_newv_NE_0.INIT = 16'h8421; + LUT4 plm_fsm_un3_clw0_newv_NE_0 ( + .I0(plm_fsm_reg_rx0_old[4]), + .I1(plm_fsm_reg_rx0_old[5]), + .I2(plm_rx0_lane_num[4]), + .I3(plm_rx0_lane_num[5]), + .O(plm_fsm_un3_clw0_newv_NE_0_854) + ); + defparam plm_fsm_un3_clw0_newv_NE_1.INIT = 16'h8421; + LUT4 plm_fsm_un3_clw0_newv_NE_1 ( + .I0(plm_fsm_reg_rx0_old[2]), + .I1(plm_fsm_reg_rx0_old[3]), + .I2(plm_rx0_lane_num[2]), + .I3(plm_rx0_lane_num[3]), + .O(plm_fsm_un3_clw0_newv_NE_1_853) + ); + defparam plm_fsm_un3_clw0_newv_NE_2.INIT = 16'h8421; + LUT4 plm_fsm_un3_clw0_newv_NE_2 ( + .I0(plm_fsm_reg_rx0_old[6]), + .I1(plm_fsm_reg_rx0_old[7]), + .I2(plm_rx0_lane_num[6]), + .I3(plm_rx0_lane_num[7]), + .O(plm_fsm_un3_clw0_newv_NE_2_852) + ); + defparam plm_fsm_un3_clw0_newv_NE_3.INIT = 16'h8421; + LUT4_L plm_fsm_un3_clw0_newv_NE_3 ( + .I0(plm_fsm_reg_rx0_old[0]), + .I1(plm_fsm_reg_rx0_old[1]), + .I2(plm_rx0_lane_num[0]), + .I3(plm_rx0_lane_num[1]), + .LO(plm_fsm_un3_clw0_newv_NE_3_846) + ); + defparam plm_fsm_reg_rx_clear_cs_2_sqmuxa_9_0.INIT = 8'h2A; + LUT3 plm_fsm_reg_rx_clear_cs_2_sqmuxa_9_0 ( + .I0(plm_fsm_reg_state_16__357), + .I1(plm_rx0_linkctrl_0_), + .I2(plm_rx0_ts1_c), + .O(plm_fsm_reg_rx_clear_cs_2_sqmuxa_9_0_869) + ); + defparam plm_fsm_fsm_vector_reg_123_link_pad_36_0_a2_i_0_a4_5.INIT = 16'h0001; + LUT4 plm_fsm_fsm_vector_reg_123_link_pad_36_0_a2_i_0_a4_5 ( + .I0(plm_fsm_reg_123_lane_pad_898), + .I1(plm_fsm_reg_123_link_pad_900), + .I2(plm_reg_tx_link_num[2]), + .I3(plm_reg_tx_link_num[6]), + .O(plm_fsm_reg_123_link_pad_36_0_a2_i_0_a4_5) + ); + defparam plm_fsm_fsm_vector_reg_123_link_pad_36_0_a2_i_0_a4_6.INIT = 16'h0001; + LUT4_L plm_fsm_fsm_vector_reg_123_link_pad_36_0_a2_i_0_a4_6 ( + .I0(plm_reg_tx_link_num[1]), + .I1(plm_reg_tx_link_num[3]), + .I2(plm_reg_tx_link_num[4]), + .I3(plm_reg_tx_link_num[5]), + .LO(plm_fsm_reg_123_link_pad_36_0_a2_i_0_a4_6) + ); + defparam plm_fsm_fsm_vector_reg_123_link_pad_36_0_a2_i_0_1_0.INIT = 16'h0001; + LUT4 plm_fsm_fsm_vector_reg_123_link_pad_36_0_a2_i_0_1_0 ( + .I0(plm_fsm_reg_state_18__885), + .I1(plm_fsm_reg_state_19__884), + .I2(plm_fsm_reg_state_20__883), + .I3(plm_fsm_reg_state_21__882), + .O(plm_fsm_reg_123_link_pad_36_0_a2_i_0_1) + ); + defparam plm_fsm_fsm_vector_reg_state_141_0_0_0_1_iv_0_5621_i_0_m3_0.INIT = 8'h7E; + LUT3 plm_fsm_fsm_vector_reg_state_141_0_0_0_1_iv_0_5621_i_0_m3_0 ( + .I0(plm_fsm_pc_cntrout1), + .I1(plm_fsm_pc_cntrout2), + .I2(plm_fsm_pc_cntrout3), + .O(plm_fsm_N_38341) + ); + defparam plm_fsm_reg_state_2_sqmuxa_8_i_0_0_o3_2.INIT = 16'h007F; + LUT4 plm_fsm_reg_state_2_sqmuxa_8_i_0_0_o3_2 ( + .I0(plm_fsm_rl_cntrout1), + .I1(plm_fsm_rl_cntrout2), + .I2(plm_fsm_rl_cntrout3), + .I3(plm_fsm_reg_sel_by1_890), + .O(plm_fsm_N_38114_i) + ); + defparam plm_fsm_fsm_vector_reg_state_141_0_0_0_1_iv_i_0_0_o3_2_16_.INIT = 16'h007F; + LUT4 plm_fsm_fsm_vector_reg_state_141_0_0_0_1_iv_i_0_0_o3_2_16_ ( + .I0(plm_fsm_ri_cntrout1), + .I1(plm_fsm_ri_cntrout2), + .I2(plm_fsm_ri_cntrout3), + .I3(plm_fsm_reg_sel_by1_890), + .O(plm_fsm_N_38132_i) + ); + defparam plm_fsm_fsm_vector_reg_rx_clear_cs_98_0_0_0_1_iv_i_o3_4_1_0_a3_0.INIT = 16'h2000; + LUT4 plm_fsm_fsm_vector_reg_rx_clear_cs_98_0_0_0_1_iv_i_o3_4_1_0_a3_0 ( + .I0(plm_fsm_reg_state_16__357), + .I1(plm_fsm_ri_cntrout0), + .I2(plm_rx0_lane_pad), + .I3(plm_rx0_ts1_c), + .O(plm_fsm_N_38989) + ); + defparam plm_fsm_fsm_vector_reg_state_141_0_0_0_0_iv_i_0_0_a4_0_1_15_.INIT = 4'h8; + LUT2 plm_fsm_fsm_vector_reg_state_141_0_0_0_0_iv_i_0_0_a4_0_1_15_ ( + .I0(plm_fsm_N_38122_i), + .I1(plm_fsm_reg_state_13__41), + .O(plm_fsm_N_38473_1) + ); + defparam plm_fsm_reg_state_1_sqmuxa_2.INIT = 8'h80; + LUT3 plm_fsm_reg_state_1_sqmuxa_2 ( + .I0(plm_reg_ts1_1), + .I1(N_38190_i), + .I2(plm_fsm_reg_state_18__885), + .O(plm_fsm_reg_state_1_sqmuxa_2_865) + ); + defparam plm_fsm_fsm_vector_reg_state_141_0_0_0_2_iv_i_0_a3_4_3_.INIT = 4'h8; + LUT2 plm_fsm_fsm_vector_reg_state_141_0_0_0_2_iv_i_0_a3_4_3_ ( + .I0(plm_fsm_N_38118_i), + .I1(plm_fsm_reg_state_18__885), + .O(plm_fsm_N_39026) + ); + defparam plm_fsm_un1_reg_state_22_i_o2_1_i_a2_0_o3.INIT = 8'h08; + LUT3 plm_fsm_un1_reg_state_22_i_o2_1_i_a2_0_o3 ( + .I0(N_38100_i), + .I1(plm_fsm_N_38173_i), + .I2(plm_fsm_reg_state_13__41), + .O(plm_fsm_N_38236_i) + ); + defparam plm_fsm_fsm_vector_reg_state_141_0_0_0_0_iv_0_i_0_a3_5_.INIT = 4'h8; + LUT2 plm_fsm_fsm_vector_reg_state_141_0_0_0_0_iv_0_i_0_a3_5_ ( + .I0(plm_fsm_N_38118_i), + .I1(plm_fsm_reg_state_4__877), + .O(plm_fsm_N_39047) + ); + defparam plm_fsm_fsm_vector_reg_state_141_0_0_0_2_iv_i_0_a3_5_3_.INIT = 16'h0800; + LUT4 plm_fsm_fsm_vector_reg_state_141_0_0_0_2_iv_i_0_a3_5_3_ ( + .I0(plm_fsm_reg_state_16__357), + .I1(plm_rx0_lane_pad), + .I2(plm_rx0_linkctrl_0_), + .I3(plm_rx0_ts1_c), + .O(plm_fsm_N_38988) + ); + defparam plm_fsm_un1_reg_state_15_i_0_a4_1.INIT = 4'h4; + LUT2 plm_fsm_un1_reg_state_15_i_0_a4_1 ( + .I0(plm_fsm_N_38118_i), + .I1(plm_fsm_reg_state_4__877), + .O(plm_fsm_reg_rx_clear_cs_4_sqmuxa_1_0) + ); + defparam plm_fsm_fsm_vector_reg_state_141_0_0_0_0_iv_i_0_a4_0_4_.INIT = 8'h08; + LUT3 plm_fsm_fsm_vector_reg_state_141_0_0_0_0_iv_i_0_a4_0_4_ ( + .I0(plm_fsm_reg_state_141_0_0_0_2_iv_i_0_o3_1[3]), + .I1(plm_fsm_reg_state_3__878), + .I2(plm_rx0_link_pad), + .O(plm_fsm_N_38598) + ); + defparam plm_fsm_fsm_vector_reg_state_141_0_0_0_0_iv_i_0_0_a4_13_.INIT = 4'h4; + LUT2 plm_fsm_fsm_vector_reg_state_141_0_0_0_0_iv_i_0_0_a4_13_ ( + .I0(plm_fsm_N_38139_i), + .I1(plm_link_l0), + .O(plm_fsm_N_38506) + ); + defparam plm_fsm_un1_reg_state_4_i_i.INIT = 8'hFE; + LUT3 plm_fsm_un1_reg_state_4_i_i ( + .I0(plm_fsm_reg_state_18__885), + .I1(plm_fsm_reg_state_19__884), + .I2(plm_fsm_reg_state_20__883), + .O(plm_fsm_un1_reg_state_4_i_i_844) + ); + defparam plm_fsm_un1_reg_state_15_i_0_2.INIT = 8'h02; + LUT3 plm_fsm_un1_reg_state_15_i_0_2 ( + .I0(plm_fsm_N_38203_i), + .I1(plm_fsm_reg_state_1__903), + .I2(plm_fsm_reg_state_3__878), + .O(plm_fsm_N_67847_2) + ); + defparam plm_fsm_fsm_vector_reg_state_141_0_0_0_1_iv_i_i_i_a4_1_9_.INIT = 16'h0002; + LUT4 plm_fsm_fsm_vector_reg_state_141_0_0_0_1_iv_i_i_i_a4_1_9_ ( + .I0(plm_fsm_N_38611_1_0), + .I1(plm_fsm_pc_cntrout1), + .I2(plm_fsm_pc_cntrout2), + .I3(plm_fsm_pc_cntrout3), + .O(plm_fsm_N_38611) + ); + defparam plm_fsm_un3_xl_clw0_newv_NE_4.INIT = 8'h84; + LUT3_L plm_fsm_un3_xl_clw0_newv_NE_4 ( + .I0(plm_fsm_reg_xl_rx0_old[8]), + .I1(plm_fsm_un3_xl_clw0_newv_NE_3_845), + .I2(plm_rx0_lane_pad), + .LO(plm_fsm_un3_xl_clw0_newv_NE_4_855) + ); + defparam plm_fsm_un3_clw0_newv_NE_4.INIT = 8'h84; + LUT3 plm_fsm_un3_clw0_newv_NE_4 ( + .I0(plm_fsm_reg_rx0_old[8]), + .I1(plm_fsm_un3_clw0_newv_NE_3_846), + .I2(plm_rx0_lane_pad), + .O(plm_fsm_un3_clw0_newv_NE_4_861) + ); + defparam plm_fsm_fsm_vector_reg_state_141_0_0_0_0_iv_i_0_0_a4_0_0_15_.INIT = 16'h0080; + LUT4 plm_fsm_fsm_vector_reg_state_141_0_0_0_0_iv_i_0_0_a4_0_0_15_ ( + .I0(plm_fsm_rl_cntrout1), + .I1(plm_fsm_rl_cntrout2), + .I2(plm_fsm_rl_cntrout3), + .I3(plm_fsm_reg_sel_by1_890), + .O(plm_fsm_reg_state_141_0_0_0_0_iv_i_0_0_a4_0_0[15]) + ); + defparam plm_fsm_fsm_vector_reg_123_link_pad_36_0_a2_i_0_a4_7.INIT = 8'h02; + LUT3 plm_fsm_fsm_vector_reg_123_link_pad_36_0_a2_i_0_a4_7 ( + .I0(plm_fsm_reg_123_link_pad_36_0_a2_i_0_a4_6), + .I1(plm_reg_tx_link_num[0]), + .I2(plm_reg_tx_link_num[7]), + .O(plm_fsm_reg_123_link_pad_36_0_a2_i_0_a4_7) + ); + defparam plm_fsm_fsm_vector_reg_123_link_pad_36_0_a2_i_0_a4_8.INIT = 8'hC8; + LUT3 plm_fsm_fsm_vector_reg_123_link_pad_36_0_a2_i_0_a4_8 ( + .I0(plm_fsm_N_39029), + .I1(plm_fsm_reg_123_link_pad_36_0_a2_i_0_a4_5), + .I2(plm_fsm_reg_state_24__887), + .O(plm_fsm_reg_123_link_pad_36_0_a2_i_0_a4_8) + ); + defparam plm_fsm_un1_reg_state_22_i_0_0_1.INIT = 8'h08; + LUT3 plm_fsm_un1_reg_state_22_i_0_0_1 ( + .I0(N_38123_i), + .I1(plm_fsm_N_38241_i), + .I2(plm_fsm_reg_state_23__880), + .O(plm_fsm_un1_reg_state_22_i_0_0_1_871) + ); + defparam plm_fsm_reg_state_5_sqmuxa_1_i_0_a4.INIT = 4'h4; + LUT2 plm_fsm_reg_state_5_sqmuxa_1_i_0_a4 ( + .I0(plm_fsm_N_38341), + .I1(plm_fsm_pc_cntrout0), + .O(plm_fsm_N_38608) + ); + defparam plm_fsm_fsm_vector_reg_rx_clear_cs_98_0_0_0_1_iv_i_o3_4_1_0_a3_7_1.INIT = 4'h1; + LUT2 plm_fsm_fsm_vector_reg_rx_clear_cs_98_0_0_0_1_iv_i_o3_4_1_0_a3_7_1 ( + .I0(plm_fsm_rc_timeout_1), + .I1(plm_rx0_ts1_c), + .O(plm_fsm_N_38983_1) + ); + defparam plm_fsm_N_38537_i.INIT = 8'hF7; + LUT3 plm_fsm_N_38537_i ( + .I0(N_38123_i), + .I1(plm_fsm_N_38203_i), + .I2(plm_fsm_reg_state_1__903), + .O(plm_fsm_N_38537_i_889) + ); + defparam plm_fsm_N_38559_i.INIT = 16'hFFFD; + LUT4 plm_fsm_N_38559_i ( + .I0(plm_fsm_N_38203_i), + .I1(plm_fsm_reg_state_1__903), + .I2(plm_fsm_reg_state_11__360), + .I3(plm_link_ctrl[0]), + .O(plm_fsm_N_38559_i_888) + ); + defparam plm_fsm_un1_reg_state_22_i_o2_1_i_a2_0_a4.INIT = 4'h8; + LUT2 plm_fsm_un1_reg_state_22_i_o2_1_i_a2_0_a4 ( + .I0(plm_fsm_N_38236_i), + .I1(plm_fsm_N_38241_i), + .O(plm_fsm_un1_reg_state_22_i_o2_1_i_a2_0_a4_893) + ); + defparam plm_fsm_ci_idle_data_i_0_0.INIT = 16'hAA80; + LUT4 plm_fsm_ci_idle_data_i_0_0 ( + .I0(plm_fsm_ci_cntrout0), + .I1(plm_fsm_ci_cntrout2), + .I2(plm_fsm_ci_idle_data_i_o3_i_a4_0_847), + .I3(plm_fsm_reg_sel_by1_890), + .O(plm_fsm_N_23238_i) + ); + defparam plm_fsm_reg_state_2_sqmuxa_8_i_0_0_a4.INIT = 8'h0D; + LUT3 plm_fsm_reg_state_2_sqmuxa_8_i_0_0_a4 ( + .I0(plm_fsm_N_38122_i), + .I1(cfg_cfg_5072[505]), + .I2(plm_fsm_reg_rl_throw_a_bone_895), + .O(plm_fsm_N_38588) + ); + defparam plm_fsm_fsm_vector_reg_rx_clear_cs_98_0_0_0_1_iv_i_0_a3_11.INIT = 8'h51; + LUT3 plm_fsm_fsm_vector_reg_rx_clear_cs_98_0_0_0_1_iv_i_0_a3_11 ( + .I0(plm_fsm_N_38114_i), + .I1(NlwRenamedSig_OI_cfg_lcommand_7_), + .I2(plm_fsm_rl_extdout), + .O(plm_fsm_N_39002) + ); + defparam plm_fsm_reg_state_2_sqmuxa_8_i_0_0_o3_1.INIT = 4'h4; + LUT2 plm_fsm_reg_state_2_sqmuxa_8_i_0_0_o3_1 ( + .I0(plm_fsm_N_38114_i), + .I1(plm_fsm_N_38122_i), + .O(plm_fsm_N_38130_i) + ); + defparam plm_fsm_un1_linklanematch0_NE.INIT = 16'h8000; + LUT4 plm_fsm_un1_linklanematch0_NE ( + .I0(plm_fsm_un1_linklanematch0_NE_0_851), + .I1(plm_fsm_un1_linklanematch0_NE_1_850), + .I2(plm_fsm_un1_linklanematch0_NE_2_849), + .I3(plm_fsm_un1_linklanematch0_NE_3_848), + .O(N_8824) + ); + defparam plm_fsm_fsm_vector_reg_state_141_0_0_0_1_iv_i_0_0_o3_23_.INIT = 8'h80; + LUT3 plm_fsm_fsm_vector_reg_state_141_0_0_0_1_iv_i_0_0_o3_23_ ( + .I0(N_38113_i), + .I1(plm_fsm_reg_123_lane_pad_898), + .I2(plm_fsm_reg_123_link_pad_900), + .O(plm_fsm_N_38164_i) + ); + defparam plm_fsm_reg_state_4_sqmuxa_1_1.INIT = 16'h1300; + LUT4 plm_fsm_reg_state_4_sqmuxa_1_1 ( + .I0(plm_reg_ts1_1), + .I1(plm_fsm_N_38118_i), + .I2(N_38190_i), + .I3(plm_fsm_reg_state_18__885), + .O(plm_fsm_reg_state_4_sqmuxa_1_1_866) + ); + defparam plm_fsm_un3_clw0_newv_NE_6.INIT = 8'h80; + LUT3 plm_fsm_un3_clw0_newv_NE_6 ( + .I0(plm_fsm_un3_clw0_newv_NE_0_854), + .I1(plm_fsm_un3_clw0_newv_NE_1_853), + .I2(plm_fsm_un3_clw0_newv_NE_2_852), + .O(plm_fsm_un3_clw0_newv_NE_6_860) + ); + defparam plm_fsm_fsm_vector_reg_rx_clear_cs_98_0_0_0_1_iv_i_0_o3.INIT = 4'h2; + LUT2_L plm_fsm_fsm_vector_reg_rx_clear_cs_98_0_0_0_1_iv_i_0_o3 ( + .I0(plm_fsm_N_51397), + .I1(plm_fsm_pa_cntrout0), + .LO(plm_fsm_N_38192_i) + ); + defparam plm_fsm_fsm_vector_reg_state_141_0_0_0_i_0_a4_1_.INIT = 16'hFE00; + LUT4 plm_fsm_fsm_vector_reg_state_141_0_0_0_i_0_a4_1_ ( + .I0(plm_fsm_N_51382), + .I1(plm_fsm_N_51449), + .I2(plm_fsm_N_51450), + .I3(plm_fsm_reg_state_0__879), + .O(plm_fsm_N_38599) + ); + defparam plm_fsm_reg_state_2_sqmuxa_8_i_0_0_o3_0.INIT = 4'h4; + LUT2 plm_fsm_reg_state_2_sqmuxa_8_i_0_0_o3_0 ( + .I0(plm_fsm_N_51395), + .I1(plm_fsm_reg_state_13__41), + .O(plm_fsm_N_38189_i) + ); + defparam plm_fsm_fsm_vector_reg_state_141_0_0_0_2_iv_i_0_a4_3_.INIT = 16'hA020; + LUT4 plm_fsm_fsm_vector_reg_state_141_0_0_0_2_iv_i_0_a4_3_ ( + .I0(plm_fsm_N_51384), + .I1(plm_fsm_reg_state_141_0_0_0_2_iv_i_0_o3_1[3]), + .I2(plm_fsm_reg_state_3__878), + .I3(plm_rx0_link_pad), + .O(plm_fsm_N_38593) + ); + defparam plm_fsm_fsm_vector_reg_state86.INIT = 8'h10; + LUT3_L plm_fsm_fsm_vector_reg_state86 ( + .I0(plm_fsm_N_51397), + .I1(plm_fsm_pa_cntrout0), + .I2(plm_fsm_reg_state_1__903), + .LO(plm_fsm_reg_state86) + ); + defparam plm_fsm_fsm_vector_reg_state_141_0_0_0_1_iv_0_0_.INIT = 16'h153F; + LUT4 plm_fsm_fsm_vector_reg_state_141_0_0_0_1_iv_0_0_ ( + .I0(plm_fsm_N_38733_1), + .I1(plm_fsm_N_39029), + .I2(plm_fsm_N_39043), + .I3(plm_fsm_rc_timeout_1), + .O(plm_fsm_reg_state_141_0_0_0_1_iv_0_0_) + ); + defparam plm_fsm_N_9826_i.INIT = 8'hFD; + LUT3 plm_fsm_N_9826_i ( + .I0(plm_fsm_N_67847_2), + .I1(plm_fsm_reg_state_4__877), + .I2(plm_fsm_reg_state_18__885), + .O(plm_fsm_N_9826_i_897) + ); + defparam plm_fsm_un1_reg_state_22_i_0_0_o4_2.INIT = 16'h0002; + LUT4 plm_fsm_un1_reg_state_22_i_0_0_o4_2 ( + .I0(plm_fsm_N_38236_i), + .I1(plm_fsm_reg_state_7__874), + .I2(plm_fsm_reg_state_8__873), + .I3(plm_fsm_reg_state_24__887), + .O(plm_fsm_N_38379_i) + ); + defparam plm_fsm_un1_reg_state_15_i_o3_i_o3_0.INIT = 4'h2; + LUT2 plm_fsm_un1_reg_state_15_i_o3_i_o3_0 ( + .I0(N_8824), + .I1(plm_rx0_link_pad), + .O(plm_fsm_N_38096_i) + ); + defparam plm_fsm_reg_state_2_sqmuxa_3_1.INIT = 4'h4; + LUT2 plm_fsm_reg_state_2_sqmuxa_3_1 ( + .I0(plm_fsm_N_23238_i), + .I1(plm_fsm_reg_state_11__360), + .O(plm_fsm_reg_state_2_sqmuxa_3_1_870) + ); + defparam plm_fsm_fsm_vector_reg_state_141_0_0_0_1_iv_i_0_0_a4_0_0_16_.INIT = 16'h2030; + LUT4 plm_fsm_fsm_vector_reg_state_141_0_0_0_1_iv_i_0_0_a4_0_0_16_ ( + .I0(plm_fsm_N_38132_i), + .I1(plm_fsm_N_38245_i), + .I2(plm_fsm_reg_state_16__357), + .I3(plm_fsm_ri_cntrout0), + .O(plm_fsm_reg_rx_clear_cs_4_sqmuxa_1_0_0) + ); + defparam plm_fsm_fsm_vector_N_26212_i_i.INIT = 4'h8; + LUT2 plm_fsm_fsm_vector_N_26212_i_i ( + .I0(plm_fsm_reg_expired), + .I1(plm_fsm_N_26212_i_i_0), + .O(plm_fsm_N_38060_i) + ); + defparam plm_fsm_un3_xl_clw0_newv_NE.INIT = 16'h8000; + LUT4 plm_fsm_un3_xl_clw0_newv_NE ( + .I0(plm_fsm_un3_xl_clw0_newv_NE_0_858), + .I1(plm_fsm_un3_xl_clw0_newv_NE_1_857), + .I2(plm_fsm_un3_xl_clw0_newv_NE_2_856), + .I3(plm_fsm_un3_xl_clw0_newv_NE_4_855), + .O(plm_fsm_N_8826) + ); + defparam plm_fsm_fsm_vector_reg_state_141_0_0_0_2_iv_i_0_a3_1_1_3_.INIT = 16'h0008; + LUT4 plm_fsm_fsm_vector_reg_state_141_0_0_0_2_iv_i_0_a3_1_1_3_ ( + .I0(plm_fsm_N_38114_i), + .I1(plm_fsm_N_38122_i), + .I2(cfg_cfg_5072[505]), + .I3(plm_fsm_reg_link_mode_892), + .O(plm_fsm_reg_state_141_0_0_0_2_iv_i_0_a3_1_1[3]) + ); + defparam plm_fsm_fsm_vector_reg_rx_clear_cs_98_0_0_0_1_iv_i_o3_4_1_0_a3.INIT = 8'hE0; + LUT3 plm_fsm_fsm_vector_reg_rx_clear_cs_98_0_0_0_1_iv_i_o3_4_1_0_a3 ( + .I0(plm_fsm_N_38608), + .I1(plm_fsm_pc_timeout_1), + .I2(plm_fsm_reg_state_2__356), + .O(plm_fsm_N_39018) + ); + defparam plm_fsm_reg_state_3_sqmuxa_2.INIT = 16'hA020; + LUT4 plm_fsm_reg_state_3_sqmuxa_2 ( + .I0(plm_fsm_N_25635_i), + .I1(plm_fsm_reg_state_141_0_0_0_2_iv_i_0_o3_1[3]), + .I2(plm_fsm_reg_state_3__878), + .I3(plm_rx0_link_pad), + .O(plm_fsm_reg_state_3_sqmuxa_2_859) + ); + defparam plm_fsm_reg_state_2_sqmuxa_2.INIT = 16'h2000; + LUT4 plm_fsm_reg_state_2_sqmuxa_2 ( + .I0(plm_fsm_N_38608), + .I1(cfg_cfg_5072[505]), + .I2(plm_fsm_reg_link_mode_892), + .I3(plm_fsm_reg_state_2__356), + .O(plm_fsm_reg_state_2_sqmuxa_2_867) + ); + defparam plm_fsm_fsm_vector_reg_state_141_0_0_0_2_iv_i_0_a3_0_3_.INIT = 16'h0200; + LUT4 plm_fsm_fsm_vector_reg_state_141_0_0_0_2_iv_i_0_a3_0_3_ ( + .I0(plm_fsm_N_38608), + .I1(cfg_cfg_5072[505]), + .I2(plm_fsm_reg_link_mode_892), + .I3(plm_fsm_reg_state_2__356), + .O(plm_fsm_N_39022) + ); + defparam plm_fsm_fsm_vector_reg_state_141_0_0_0_1_iv_0_32192.INIT = 16'h135F; + LUT4 plm_fsm_fsm_vector_reg_state_141_0_0_0_1_iv_0_32192 ( + .I0(plm_fsm_N_38341), + .I1(plm_fsm_N_39043), + .I2(plm_fsm_pc_timeout), + .I3(plm_fsm_reg_state_24__887), + .O(plm_fsm_reg_state_141_0_0_0_1_iv_0_32192) + ); + defparam plm_fsm_fsm_vector_reg_state_141_0_0_0_1_iv_0_0_0_o3_2_8_.INIT = 8'h2A; + LUT3 plm_fsm_fsm_vector_reg_state_141_0_0_0_1_iv_0_0_0_o3_2_8_ ( + .I0(plm_fsm_reg_state_7__874), + .I1(plm_fsm_un3_clw0_newv_NE_4_861), + .I2(plm_fsm_un3_clw0_newv_NE_6_860), + .O(plm_fsm_N_38201_i) + ); + defparam plm_fsm_fsm_vector_reg_rx_clear_cs_98_0_0_0_1_iv_i_0_a3_2.INIT = 8'hB0; + LUT3 plm_fsm_fsm_vector_reg_rx_clear_cs_98_0_0_0_1_iv_i_0_a3_2 ( + .I0(plm_fsm_N_38130_i), + .I1(plm_fsm_N_51395), + .I2(plm_fsm_reg_state_13__41), + .O(plm_fsm_N_39011) + ); + defparam plm_fsm_fsm_vector_reg_state_141_0_0_0_0_iv_i_0_0_o3_21_.INIT = 4'h8; + LUT2 plm_fsm_fsm_vector_reg_state_141_0_0_0_0_iv_i_0_0_o3_21_ ( + .I0(plm_fsm_N_38096_i), + .I1(plm_fsm_reg_state_141_0_0_0_2_iv_i_0_o3_1[3]), + .O(plm_fsm_N_38196_i) + ); + defparam plm_fsm_fsm_vector_reg_state_141_0_0_0_1_iv_i_0_0_o3_24_.INIT = 4'h8; + LUT2 plm_fsm_fsm_vector_reg_state_141_0_0_0_1_iv_i_0_0_o3_24_ ( + .I0(plm_fsm_N_38096_i), + .I1(plm_fsm_N_38126_i), + .O(plm_fsm_N_38180_i) + ); + defparam plm_fsm_fsm_vector_reg_rx_clear_cs_98_0_0_0_1_iv_i_o3_4_1_0_o3_10.INIT = 16'h2030; + LUT4 plm_fsm_fsm_vector_reg_rx_clear_cs_98_0_0_0_1_iv_i_o3_4_1_0_o3_10 ( + .I0(N_38100_i), + .I1(plm_fsm_N_38469), + .I2(plm_fsm_reg_rx_clear_cs_98_0_0_0_1_iv_i_o3_4_1_0_o3_10_0), + .I3(plm_fsm_rc_timeout_1), + .O(plm_fsm_reg_rx_clear_cs_98_0_0_0_1_iv_i_o3_4_1_0_o3_10) + ); + defparam plm_fsm_fsm_vector_reg_rx_clear_cs_98_0_0_0_1_iv_i_o3_4_1_0_a3_5.INIT = 8'h04; + LUT3 plm_fsm_fsm_vector_reg_rx_clear_cs_98_0_0_0_1_iv_i_o3_4_1_0_a3_5 ( + .I0(plm_fsm_reg_expired), + .I1(plm_fsm_N_38983_1), + .I2(plm_fsm_rc_cntrout_ts2_0), + .O(plm_fsm_N_38981) + ); + defparam plm_fsm_fsm_vector_reg_state_141_0_0_0_2_iv_i_0_o3_3_3_.INIT = 16'h0501; + LUT4 plm_fsm_fsm_vector_reg_state_141_0_0_0_2_iv_i_0_o3_3_3_ ( + .I0(plm_fsm_N_38060_i), + .I1(plm_fsm_N_38988), + .I2(plm_fsm_N_39026), + .I3(plm_fsm_ri_cntrout0), + .O(plm_fsm_reg_state_141_0_0_0_2_iv_i_0_o3_3[3]) + ); + defparam plm_fsm_fsm_vector_reg_state_141_0_0_0_1_iv_0_12_.INIT = 16'h135F; + LUT4_L plm_fsm_fsm_vector_reg_state_141_0_0_0_1_iv_0_12_ ( + .I0(plm_fsm_N_23238_i), + .I1(plm_fsm_N_38139_i), + .I2(plm_fsm_reg_state_11__360), + .I3(plm_link_l0), + .LO(plm_fsm_reg_state_141_0_0_0_1_iv_0_12_) + ); + defparam plm_fsm_fsm_vector_reg_state_141_0_0_0_0_0_18_.INIT = 16'h1505; + LUT4 plm_fsm_fsm_vector_reg_state_141_0_0_0_0_0_18_ ( + .I0(plm_fsm_N_38060_i), + .I1(plm_fsm_N_38132_i), + .I2(plm_fsm_N_38988), + .I3(plm_fsm_ri_cntrout0), + .O(plm_fsm_reg_state_141_0_0_0_0_0[18]) + ); + defparam plm_fsm_fsm_vector_reg_state_141_0_0_0_2_iv_i_0_0_3_.INIT = 16'h0F07; + LUT4 plm_fsm_fsm_vector_reg_state_141_0_0_0_2_iv_i_0_0_3_ ( + .I0(plm_fsm_N_38132_i), + .I1(plm_fsm_N_38988), + .I2(plm_fsm_N_39026), + .I3(plm_fsm_reg_link_mode_892), + .O(plm_fsm_reg_state_141_0_0_0_2_iv_i_0_0[3]) + ); + defparam plm_fsm_fsm_vector_reg_rx_clear_cs_98_0_0_0_1_iv_i_0_o3_9.INIT = 16'h1505; + LUT4 plm_fsm_fsm_vector_reg_rx_clear_cs_98_0_0_0_1_iv_i_0_o3_9 ( + .I0(N_38123_i), + .I1(plm_fsm_N_39033), + .I2(plm_fsm_N_51381), + .I3(plm_fsm_cc_cntrout0), + .O(plm_fsm_N_38137_i) + ); + defparam plm_fsm_fsm_vector_reg_state_141_0_0_0_1_iv_2_32191.INIT = 16'h0EFF; + LUT4_L plm_fsm_fsm_vector_reg_state_141_0_0_0_1_iv_2_32191 ( + .I0(plm_fsm_N_9824), + .I1(plm_fsm_N_51397), + .I2(plm_fsm_pa_cntrout0), + .I3(plm_fsm_reg_state_1__903), + .LO(plm_fsm_reg_state_141_0_0_0_1_iv_2_32191) + ); + defparam plm_fsm_fsm_vector_reg_state_141_0_0_0_1_iv_i_i_i_0_9_.INIT = 8'h15; + LUT3 plm_fsm_fsm_vector_reg_state_141_0_0_0_1_iv_i_i_i_0_9_ ( + .I0(plm_fsm_N_38611), + .I1(plm_fsm_N_38735_1), + .I2(plm_fsm_N_51381), + .O(plm_fsm_reg_state_141_0_0_0_1_iv_i_i_i_0[9]) + ); + defparam plm_fsm_fsm_vector_reg_state_141_0_0_0_1_iv_2_0_.INIT = 16'hA2F3; + LUT4 plm_fsm_fsm_vector_reg_state_141_0_0_0_1_iv_2_0_ ( + .I0(plm_fsm_N_38599), + .I1(plm_fsm_N_38735_1), + .I2(plm_fsm_N_51381), + .I3(plm_fsm_reg_state_0__879), + .O(plm_fsm_reg_state_141_0_0_0_1_iv_2[0]) + ); + defparam plm_fsm_fsm_vector_reg_state_141_0_0_0_1_iv_3_0_.INIT = 16'h51F3; + LUT4_L plm_fsm_fsm_vector_reg_state_141_0_0_0_1_iv_3_0_ ( + .I0(plm_fsm_N_9824), + .I1(plm_fsm_reg_state_10__886), + .I2(plm_fsm_N_51381), + .I3(plm_fsm_reg_state86), + .LO(plm_fsm_reg_state_141_0_0_0_1_iv_3[0]) + ); + defparam plm_fsm_fsm_vector_reg_state_141_0_0_0_1_iv_4_0_.INIT = 16'h008A; + LUT4_L plm_fsm_fsm_vector_reg_state_141_0_0_0_1_iv_4_0_ ( + .I0(plm_fsm_reg_state_141_0_0_0_1_iv_0_0_), + .I1(plm_fsm_pc_cntrout0), + .I2(plm_fsm_pc_timeout), + .I3(plm_fsm_reg_state_3_sqmuxa_2_859), + .LO(plm_fsm_reg_state_141_0_0_0_1_iv_4[0]) + ); + defparam plm_fsm_fsm_vector_reg_rx_clear_cs_98_0_0_0_1_iv_i_o3_4_1_0_o3_8.INIT = 4'h4; + LUT2 plm_fsm_fsm_vector_reg_rx_clear_cs_98_0_0_0_1_iv_i_o3_4_1_0_o3_8 ( + .I0(plm_fsm_N_38471), + .I1(plm_fsm_reg_rx_clear_cs_98_0_0_0_1_iv_i_o3_4_1_0_o3_10), + .O(plm_fsm_N_38238_i) + ); + defparam plm_fsm_fsm_vector_reg_state_141_0_0_0_1_iv_i_0_0_a4_1_0_7_.INIT = 16'h008F; + LUT4 plm_fsm_fsm_vector_reg_state_141_0_0_0_1_iv_i_0_0_a4_1_0_7_ ( + .I0(plm_fsm_un3_clw0_newv_NE_4_861), + .I1(plm_fsm_un3_clw0_newv_NE_6_860), + .I2(plm_rx0_ts1_c), + .I3(plm_rx0_ts2_c), + .O(plm_fsm_N_38465_1) + ); + defparam plm_fsm_fsm_vector_reg_state_141_0_0_0_1_iv_i_0_0_a4_1_23_.INIT = 16'h8000; + LUT4 plm_fsm_fsm_vector_reg_state_141_0_0_0_1_iv_i_0_0_a4_1_23_ ( + .I0(plm_fsm_N_38096_i), + .I1(plm_fsm_reg_state_22__881), + .I2(plm_rx0_lane_pad), + .I3(plm_rx0_ts1_c), + .O(plm_fsm_N_38481) + ); + defparam plm_fsm_fsm_vector_reg_rx_clear_cs_98_0_0_0_1_iv_i_0_a3_12_1.INIT = 4'h8; + LUT2_L plm_fsm_fsm_vector_reg_rx_clear_cs_98_0_0_0_1_iv_i_0_a3_12_1 ( + .I0(plm_fsm_N_38102_i), + .I1(plm_fsm_N_38126_i), + .LO(plm_fsm_N_39050_1) + ); + defparam plm_fsm_reg_state_2_sqmuxa_7_1_i_o2_0_a2_0_o3.INIT = 4'h8; + LUT2 plm_fsm_reg_state_2_sqmuxa_7_1_i_o2_0_a2_0_o3 ( + .I0(plm_reg_ts1_1), + .I1(plm_fsm_N_38102_i), + .O(plm_fsm_N_38197_i) + ); + defparam plm_fsm_fsm_vector_reg_state_141_0_0_0_0_iv_i_0_0_a4_0_21_.INIT = 16'h8000; + LUT4 plm_fsm_fsm_vector_reg_state_141_0_0_0_0_iv_i_0_0_a4_0_21_ ( + .I0(plm_fsm_N_38096_i), + .I1(plm_fsm_reg_state_20__883), + .I2(plm_rx0_lane_pad), + .I3(plm_rx0_ts1_c), + .O(plm_fsm_N_38483) + ); + defparam plm_fsm_fsm_vector_reg_state_141_0_0_0_1_iv_i_0_0_a4_1_24_.INIT = 8'h40; + LUT3 plm_fsm_fsm_vector_reg_state_141_0_0_0_1_iv_i_0_0_a4_1_24_ ( + .I0(plm_fsm_N_8826), + .I1(plm_fsm_reg_state_23__880), + .I2(plm_rx0_ts1_c), + .O(plm_fsm_N_38436) + ); + defparam plm_fsm_reg_state_3_sqmuxa_5_1.INIT = 16'h4CCC; + LUT4 plm_fsm_reg_state_3_sqmuxa_5_1 ( + .I0(plm_fsm_N_38096_i), + .I1(plm_fsm_reg_state_20__883), + .I2(plm_rx0_lane_pad), + .I3(plm_rx0_ts1_c), + .O(plm_fsm_reg_state_3_sqmuxa_5_1_864) + ); + defparam plm_fsm_reg_rx_clear_cs_1_sqmuxa_12_1.INIT = 8'h8C; + LUT3 plm_fsm_reg_rx_clear_cs_1_sqmuxa_12_1 ( + .I0(plm_fsm_N_8826), + .I1(plm_fsm_reg_state_23__880), + .I2(plm_rx0_ts1_c), + .O(plm_fsm_reg_rx_clear_cs_1_sqmuxa_12_1_862) + ); + defparam plm_fsm_un1_reg_state_15_i_0_a4_1_0.INIT = 16'h4CCC; + LUT4 plm_fsm_un1_reg_state_15_i_0_a4_1_0 ( + .I0(plm_fsm_N_38096_i), + .I1(plm_fsm_reg_state_22__881), + .I2(plm_rx0_lane_pad), + .I3(plm_rx0_ts1_c), + .O(plm_fsm_N_38601_1) + ); + defparam plm_fsm_fsm_vector_reg_rx_clear_cs_98_0_0_0_1_iv_i_o3_4_1_0_o3_4.INIT = 16'h0301; + LUT4 plm_fsm_fsm_vector_reg_rx_clear_cs_98_0_0_0_1_iv_i_o3_4_1_0_o3_4 ( + .I0(N_38100_i), + .I1(plm_fsm_N_38981), + .I2(plm_fsm_N_38983), + .I3(plm_rx0_ts1_c), + .O(plm_fsm_N_38061_i) + ); + defparam plm_fsm_fsm_vector_reg_state_141_0_0_0_2_iv_i_0_2_3_.INIT = 8'h13; + LUT3 plm_fsm_fsm_vector_reg_state_141_0_0_0_2_iv_i_0_2_3_ ( + .I0(plm_fsm_N_38189_i), + .I1(plm_fsm_N_39022), + .I2(plm_fsm_reg_state_141_0_0_0_2_iv_i_0_a3_1_1[3]), + .O(plm_fsm_reg_state_141_0_0_0_2_iv_i_0_2[3]) + ); + defparam plm_fsm_fsm_vector_reg_rx_clear_cs_98_0_0_0_1_iv_i_0_o3_2_1.INIT = 16'h3020; + LUT4 plm_fsm_fsm_vector_reg_rx_clear_cs_98_0_0_0_1_iv_i_0_o3_2_1 ( + .I0(N_38123_i), + .I1(plm_fsm_N_38189_i), + .I2(plm_fsm_N_38604_i), + .I3(plm_fsm_N_51381), + .O(plm_fsm_reg_rx_clear_cs_98_0_0_0_1_iv_i_0_o3_2_1) + ); + defparam plm_fsm_fsm_vector_reg_state_141_0_0_0_1_iv_i_0_0_m3_0_24_.INIT = 8'hE2; + LUT3_L plm_fsm_fsm_vector_reg_state_141_0_0_0_1_iv_i_0_0_m3_0_24_ ( + .I0(plm_fsm_N_38180_i), + .I1(plm_rx0_lane_pad), + .I2(plm_rx0_link_pad), + .LO(plm_fsm_N_38371) + ); + defparam plm_fsm_fsm_vector_reg_rx_clear_cs_98_0_0_0_1_iv_i_0_o3_13_1_1.INIT = 8'h10; + LUT3 plm_fsm_fsm_vector_reg_rx_clear_cs_98_0_0_0_1_iv_i_0_o3_13_1_1 ( + .I0(plm_fsm_N_38137_i), + .I1(plm_fsm_reg_state_7__874), + .I2(plm_rx0_ts2_c), + .O(plm_fsm_N_39364_1_i_1) + ); + defparam plm_fsm_fsm_vector_reg_state_141_0_0_0_1_iv_6_0_.INIT = 16'h0777; + LUT4_L plm_fsm_fsm_vector_reg_state_141_0_0_0_1_iv_6_0_ ( + .I0(plm_fsm_ci_timeout), + .I1(plm_fsm_reg_state_2_sqmuxa_3_1_870), + .I2(plm_fsm_reg_state_4_sqmuxa_1_1_866), + .I3(plm_fsm_xl_cls_timeout), + .LO(plm_fsm_reg_state_141_0_0_0_1_iv_6[0]) + ); + defparam plm_fsm_fsm_vector_reg_state_141_0_0_0_1_iv_9_0_.INIT = 16'h40C0; + LUT4_L plm_fsm_fsm_vector_reg_state_141_0_0_0_1_iv_9_0_ ( + .I0(plm_fsm_N_25635_i), + .I1(plm_fsm_reg_state_141_0_0_0_1_iv_0_32192), + .I2(plm_fsm_reg_state_141_0_0_0_1_iv_4[0]), + .I3(plm_fsm_reg_rx_clear_cs_4_sqmuxa_1_0), + .LO(plm_fsm_reg_state_141_0_0_0_1_iv_9[0]) + ); + defparam plm_fsm_fsm_vector_reg_state_141_0_0_0_1_iv_10_0_.INIT = 16'h7077; + LUT4 plm_fsm_fsm_vector_reg_state_141_0_0_0_1_iv_10_0_ ( + .I0(plm_fsm_N_38375_i), + .I1(plm_fsm_N_38588), + .I2(plm_fsm_N_51392), + .I3(plm_fsm_reg_rx_clear_cs_4_sqmuxa_1_0_0), + .O(plm_fsm_reg_state_141_0_0_0_1_iv_10[0]) + ); + defparam plm_fsm_N_69263_i.INIT = 8'h4F; + LUT3 plm_fsm_N_69263_i ( + .I0(plm_fsm_N_38095_i), + .I1(N_38124_i), + .I2(plm_fsm_reg_state_13__41), + .O(plm_fsm_N_69263_i_894) + ); + defparam plm_fsm_fsm_vector_reg_state_141_0_0_0_1_iv_i_0_0_a4_0_7_.INIT = 8'h80; + LUT3 plm_fsm_fsm_vector_reg_state_141_0_0_0_1_iv_i_0_0_a4_0_7_ ( + .I0(plm_fsm_N_38102_i), + .I1(plm_fsm_reg_state_6__875), + .I2(plm_rx0_ts1_c), + .O(plm_fsm_N_38466) + ); + defparam plm_fsm_fsm_vector_reg_state_141_0_0_0_1_iv_i_0_0_a3_7_.INIT = 8'h80; + LUT3 plm_fsm_fsm_vector_reg_state_141_0_0_0_1_iv_i_0_0_a3_7_ ( + .I0(plm_fsm_N_38102_i), + .I1(plm_fsm_N_38126_i), + .I2(plm_rx0_ts1_c), + .O(plm_fsm_N_39051) + ); + defparam plm_fsm_un1_reg_state_18_i_a2_i_0_o4.INIT = 8'h4C; + LUT3 plm_fsm_un1_reg_state_18_i_a2_i_0_o4 ( + .I0(plm_fsm_N_38102_i), + .I1(plm_fsm_reg_state_6__875), + .I2(plm_rx0_ts1_c), + .O(plm_fsm_N_38161_i) + ); + defparam plm_fsm_fsm_vector_reg_rx_clear_cs_98_0_0_0_1_iv_i_o3_4_1_0_a3_9_1.INIT = 4'h8; + LUT2 plm_fsm_fsm_vector_reg_rx_clear_cs_98_0_0_0_1_iv_i_o3_4_1_0_a3_9_1 ( + .I0(plm_fsm_N_38061_i), + .I1(plm_fsm_N_38096_i), + .O(plm_fsm_N_38987_1) + ); + defparam plm_fsm_fsm_vector_reg_state_141_0_0_0_1_iv_i_0_0_a4_23_.INIT = 4'h8; + LUT2 plm_fsm_fsm_vector_reg_state_141_0_0_0_1_iv_i_0_0_a4_23_ ( + .I0(plm_fsm_N_51356), + .I1(plm_fsm_reg_rx_clear_cs_1_sqmuxa_12_1_862), + .O(plm_fsm_N_38479) + ); + defparam plm_fsm_fsm_vector_reg_rx_clear_cs_98_0_0_0_1_iv_i_o3_4_1_0_a3_8.INIT = 8'h08; + LUT3 plm_fsm_fsm_vector_reg_rx_clear_cs_98_0_0_0_1_iv_i_o3_4_1_0_a3_8 ( + .I0(plm_fsm_N_38061_i), + .I1(plm_fsm_reg_state_4__877), + .I2(plm_rx0_link_pad), + .O(plm_fsm_N_38986) + ); + defparam plm_fsm_fsm_vector_reg_state_141_0_0_0_1_iv_0_0_0_a4_8_.INIT = 16'h0800; + LUT4_L plm_fsm_fsm_vector_reg_state_141_0_0_0_1_iv_0_0_0_a4_8_ ( + .I0(plm_fsm_N_38164_i), + .I1(plm_fsm_N_39050_1), + .I2(plm_fsm_reg_state_7__874), + .I3(plm_rx0_ts2_c), + .LO(plm_fsm_N_38416) + ); + defparam plm_fsm_fsm_vector_reg_state_141_0_0_0_2_iv_i_0_4_3_.INIT = 16'hF4FC; + LUT4_L plm_fsm_fsm_vector_reg_state_141_0_0_0_2_iv_i_0_4_3_ ( + .I0(plm_fsm_N_38375_i), + .I1(plm_fsm_reg_state_141_0_0_0_2_iv_i_0_o3_3[3]), + .I2(plm_fsm_reg_link_mode_892), + .I3(plm_fsm_reg_rl_throw_a_bone_895), + .LO(plm_fsm_reg_state_141_0_0_0_2_iv_i_0_4[3]) + ); + defparam plm_fsm_reg_link_mode_m.INIT = 16'h2F00; + LUT4 plm_fsm_reg_link_mode_m ( + .I0(plm_fsm_N_38375_i), + .I1(plm_fsm_N_38588), + .I2(plm_fsm_reg_state_141_0_0_0_0_0[18]), + .I3(plm_fsm_reg_link_mode_892), + .O(plm_fsm_reg_link_mode_m_868) + ); + defparam plm_fsm_fsm_vector_reg_rx_clear_cs_98_0_0_0_1_iv_i_0_a3_14.INIT = 8'h01; + LUT3_L plm_fsm_fsm_vector_reg_rx_clear_cs_98_0_0_0_1_iv_i_0_a3_14 ( + .I0(plm_fsm_N_38061_i), + .I1(plm_fsm_N_38137_i), + .I2(plm_rx0_ts2_c), + .LO(plm_fsm_N_39007) + ); + defparam plm_fsm_fsm_vector_reg_state_141_0_0_0_1_iv_11_0_.INIT = 16'h40C0; + LUT4_L plm_fsm_fsm_vector_reg_state_141_0_0_0_1_iv_11_0_ ( + .I0(plm_fsm_hr_timeout_i_0_0_0_o4), + .I1(plm_fsm_reg_state_141_0_0_0_1_iv_2[0]), + .I2(plm_fsm_reg_state_141_0_0_0_1_iv_6[0]), + .I3(plm_link_ctrl[0]), + .LO(plm_fsm_reg_state_141_0_0_0_1_iv_11[0]) + ); + defparam plm_fsm_fsm_vector_reg_state_141_0_0_0_1_iv_i_i_i_a3_0_9_.INIT = 4'h8; + LUT2 plm_fsm_fsm_vector_reg_state_141_0_0_0_1_iv_i_i_i_a3_0_9_ ( + .I0(plm_fsm_N_39051), + .I1(plm_fsm_reg_state_24__887), + .O(plm_fsm_N_39005) + ); + defparam plm_fsm_un1_reg_state_22_i_0_0_o4_0.INIT = 4'h1; + LUT2 plm_fsm_un1_reg_state_22_i_0_0_o4_0 ( + .I0(plm_fsm_N_38466), + .I1(plm_fsm_N_38481), + .O(plm_fsm_N_38198_i) + ); + defparam plm_fsm_fsm_vector_reg_state_141_0_0_0_1_iv_0_0_0_o3_1_8_.INIT = 4'h1; + LUT2 plm_fsm_fsm_vector_reg_state_141_0_0_0_1_iv_0_0_0_o3_1_8_ ( + .I0(plm_fsm_N_39043), + .I1(plm_fsm_N_39051), + .O(plm_fsm_reg_state_141_0_0_0_1_iv_0_0_0_o3_1[8]) + ); + defparam plm_fsm_reg_state_1_sqmuxa_10.INIT = 8'h10; + LUT3 plm_fsm_reg_state_1_sqmuxa_10 ( + .I0(plm_fsm_N_38197_i), + .I1(plm_fsm_N_51184), + .I2(plm_fsm_reg_state_5__876), + .O(plm_fsm_reg_state_1_sqmuxa_10_872) + ); + defparam plm_fsm_un1_reg_state_19_i_0_0_a3_0.INIT = 16'h0040; + LUT4 plm_fsm_un1_reg_state_19_i_0_0_a3_0 ( + .I0(plm_fsm_N_38117_i), + .I1(plm_fsm_N_38236_i), + .I2(plm_fsm_N_39051), + .I3(plm_fsm_reg_state_7__874), + .O(plm_fsm_N_39017) + ); + defparam plm_fsm_fsm_vector_reg_state_141_0_0_0_1_iv_i_0_0_0_7_.INIT = 16'h1333; + LUT4_L plm_fsm_fsm_vector_reg_state_141_0_0_0_1_iv_i_0_0_0_7_ ( + .I0(plm_fsm_N_38465_1), + .I1(plm_fsm_N_38466), + .I2(plm_fsm_N_51318), + .I3(plm_fsm_reg_state_7__874), + .LO(plm_fsm_reg_state_141_0_0_0_1_iv_i_0_0_0[7]) + ); + defparam plm_fsm_fsm_vector_reg_state_141_0_0_0_1_iv_15_0_.INIT = 16'h0BBB; + LUT4 plm_fsm_fsm_vector_reg_state_141_0_0_0_1_iv_15_0_ ( + .I0(plm_fsm_N_51356), + .I1(plm_fsm_reg_rx_clear_cs_1_sqmuxa_12_1_862), + .I2(plm_fsm_reg_state_3_sqmuxa_5_1_864), + .I3(plm_fsm_xl_cls_timeout), + .O(plm_fsm_reg_state_141_0_0_0_1_iv_15[0]) + ); + defparam plm_fsm_fsm_vector_reg_state_141_0_0_0_1_iv_13_0_.INIT = 4'h8; + LUT2 plm_fsm_fsm_vector_reg_state_141_0_0_0_1_iv_13_0_ ( + .I0(plm_fsm_reg_state_141_0_0_0_1_iv_10[0]), + .I1(plm_fsm_reg_state_141_0_0_0_1_iv_11[0]), + .O(plm_fsm_reg_state_141_0_0_0_1_iv_13[0]) + ); + defparam plm_fsm_fsm_vector_reg_123_lane_pad_35_0_a2.INIT = 16'h007F; + LUT4 plm_fsm_fsm_vector_reg_123_lane_pad_35_0_a2 ( + .I0(plm_fsm_N_39051), + .I1(plm_fsm_reg_123_link_pad_36_0_a2_i_0_a4_7), + .I2(plm_fsm_reg_123_link_pad_36_0_a2_i_0_a4_8), + .I3(plm_fsm_reg_state_10__886), + .O(plm_fsm_reg_123_lane_pad_35) + ); + defparam plm_fsm_un1_reg_state_19_i_0_0_o3.INIT = 4'h1; + LUT2_L plm_fsm_un1_reg_state_19_i_0_0_o3 ( + .I0(plm_fsm_N_38379_i), + .I1(plm_fsm_N_39017), + .LO(plm_fsm_N_38087_i) + ); + defparam plm_fsm_fsm_vector_reg_rx_clear_cs_98_0_0_0_1_iv_i_o3_4_1_0_o3_9.INIT = 8'h2A; + LUT3 plm_fsm_fsm_vector_reg_rx_clear_cs_98_0_0_0_1_iv_i_o3_4_1_0_o3_9 ( + .I0(plm_fsm_N_38238_i), + .I1(plm_fsm_N_38987_1), + .I2(plm_fsm_reg_state_6__875), + .O(plm_fsm_N_39348_i) + ); + defparam plm_fsm_un1_reg_state_15_i_0_1.INIT = 16'hF531; + LUT4 plm_fsm_un1_reg_state_15_i_0_1 ( + .I0(plm_fsm_N_38161_i), + .I1(plm_fsm_N_38601_1), + .I2(plm_fsm_N_51184), + .I3(plm_fsm_N_51352), + .O(plm_fsm_N_67847_1) + ); + defparam plm_fsm_fsm_vector_reg_state_141_0_0_0_1_iv_0_0_0_1_8_.INIT = 16'h5510; + LUT4 plm_fsm_fsm_vector_reg_state_141_0_0_0_1_iv_0_0_0_1_8_ ( + .I0(plm_fsm_N_38416), + .I1(plm_fsm_N_38465_1), + .I2(plm_fsm_reg_state_7__874), + .I3(plm_fsm_reg_state_8__873), + .O(plm_fsm_reg_state_141_0_0_0_1_iv_0_0_0_1[8]) + ); + defparam plm_fsm_fsm_vector_reg_rx_clear_cs_98_0_0_0_1_iv_i_0_o3_3_0.INIT = 16'h2232; + LUT4_L plm_fsm_fsm_vector_reg_rx_clear_cs_98_0_0_0_1_iv_i_0_o3_3_0 ( + .I0(plm_fsm_N_39007), + .I1(plm_fsm_N_39011), + .I2(plm_fsm_N_39364_1_i_1), + .I3(plm_rx0_ts1_c), + .LO(plm_fsm_reg_rx_clear_cs_98_0_0_0_1_iv_i_0_o3_3_0) + ); + defparam plm_fsm_fsm_vector_reg_rx_clear_cs_98_0_0_0_1_iv_i_o3_4_1_0_o3_12.INIT = 8'h70; + LUT3_L plm_fsm_fsm_vector_reg_rx_clear_cs_98_0_0_0_1_iv_i_o3_4_1_0_o3_12 ( + .I0(plm_fsm_N_38061_i), + .I1(plm_fsm_N_38180_i), + .I2(plm_fsm_N_39348_i), + .LO(plm_fsm_reg_rx_clear_cs_98_0_0_0_1_iv_i_o3_4_1_0_o3_12) + ); + defparam plm_fsm_un1_reg_state_18_i_0_0_a4.INIT = 16'h0B00; + LUT4 plm_fsm_un1_reg_state_18_i_0_0_a4 ( + .I0(plm_fsm_N_38161_i), + .I1(plm_fsm_N_38379_i), + .I2(plm_fsm_N_39017), + .I3(plm_fsm_N_51184), + .O(plm_fsm_N_38485) + ); + defparam plm_fsm_un1_reg_state_18_i_0_0_1.INIT = 16'h1050; + LUT4 plm_fsm_un1_reg_state_18_i_0_0_1 ( + .I0(plm_fsm_N_38087_i), + .I1(plm_fsm_N_38164_i), + .I2(plm_fsm_N_38241_i), + .I3(plm_fsm_reg_state_24__887), + .O(plm_fsm_un1_reg_state_18_i_0_0_1_863) + ); + defparam plm_fsm_fsm_vector_reg_rx_clear_cs_98_0_0_0_1_iv_i_o3_4_1_0_o3_6.INIT = 16'h0222; + LUT4 plm_fsm_fsm_vector_reg_rx_clear_cs_98_0_0_0_1_iv_i_o3_4_1_0_o3_6 ( + .I0(plm_fsm_N_38238_i), + .I1(plm_fsm_N_38986), + .I2(plm_fsm_N_38987_1), + .I3(plm_fsm_reg_state_22__881), + .O(plm_fsm_N_39351_i) + ); + defparam plm_fsm_un1_reg_state_19_i_0_0.INIT = 4'h2; + LUT2 plm_fsm_un1_reg_state_19_i_0_0 ( + .I0(plm_fsm_un1_reg_state_18_i_0_0_1_863), + .I1(plm_fsm_reg_state_23__880), + .O(plm_fsm_N_19144_i) + ); + defparam plm_fsm_fsm_vector_reg_rx_clear_cs_98_0_0_0_1_iv_i_0_a3_16.INIT = 16'h2A0A; + LUT4 plm_fsm_fsm_vector_reg_rx_clear_cs_98_0_0_0_1_iv_i_0_a3_16 ( + .I0(plm_fsm_N_38132_i), + .I1(plm_fsm_reg_state_141_0_0_0_1_iv_0_0_0_o3_1[8]), + .I2(plm_fsm_reg_rx_clear_cs_98_0_0_0_1_iv_i_0_o3_20_2), + .I3(plm_fsm_reg_state_24__887), + .O(plm_fsm_N_39034) + ); + defparam plm_fsm_fsm_vector_reg_rx_clear_cs_98_0_0_0_1_iv_i_o3_4_1_0_m3_0_0.INIT = 8'hCA; + LUT3 plm_fsm_fsm_vector_reg_rx_clear_cs_98_0_0_0_1_iv_i_o3_4_1_0_m3_0_0 ( + .I0(plm_fsm_N_39348_i), + .I1(plm_fsm_N_39351_i), + .I2(plm_rx0_lane_pad), + .O(plm_fsm_N_38163) + ); + defparam plm_fsm_fsm_vector_reg_rx_clear_cs_98_0_0_0_1_iv_i_o3_4_1_0_m3_0.INIT = 16'hF044; + LUT4_L plm_fsm_fsm_vector_reg_rx_clear_cs_98_0_0_0_1_iv_i_o3_4_1_0_m3_0 ( + .I0(plm_fsm_N_38180_i), + .I1(plm_fsm_N_39348_i), + .I2(plm_fsm_N_39351_i), + .I3(plm_rx0_lane_pad), + .LO(plm_fsm_N_38336) + ); + defparam plm_fsm_fsm_vector_reg_rx_clear_cs_98_0_0_0_1_iv_i_o3_4_1_0_o3_7.INIT = 16'h5CFC; + LUT4 plm_fsm_fsm_vector_reg_rx_clear_cs_98_0_0_0_1_iv_i_o3_4_1_0_o3_7 ( + .I0(plm_fsm_N_38061_i), + .I1(plm_fsm_reg_rx_clear_cs_98_0_0_0_1_iv_i_o3_4_1_0_o3_12), + .I2(plm_rx0_lane_pad), + .I3(plm_rx0_link_pad), + .O(plm_fsm_reg_rx_clear_cs_98_0_0_0_1_iv_i_o3_4_1_0_o3_7) + ); + defparam plm_fsm_un1_reg_state_18_i_0_0.INIT = 16'h0004; + LUT4 plm_fsm_un1_reg_state_18_i_0_0 ( + .I0(plm_fsm_N_38485), + .I1(plm_fsm_un1_reg_state_18_i_0_0_1_863), + .I2(plm_fsm_reg_state_5__876), + .I3(plm_fsm_reg_state_23__880), + .O(plm_fsm_N_19146_i) + ); + defparam plm_fsm_fsm_vector_reg_rx_clear_cs_98_0_0_0_1_iv_i_0_m3_1.INIT = 8'hC5; + LUT3_L plm_fsm_fsm_vector_reg_rx_clear_cs_98_0_0_0_1_iv_i_0_m3_1 ( + .I0(plm_fsm_N_38163), + .I1(plm_fsm_reg_state_7__874), + .I2(plm_rx0_ts2_c), + .LO(plm_fsm_N_38342) + ); + defparam plm_fsm_fsm_vector_reg_rx_clear_cs_98_0_0_0_1_iv_i_0_a3_17.INIT = 16'h0054; + LUT4 plm_fsm_fsm_vector_reg_rx_clear_cs_98_0_0_0_1_iv_i_0_a3_17 ( + .I0(plm_fsm_reg_rx_clear_cs_98_0_0_0_1_iv_i_o3_4_1_0_o3_7), + .I1(plm_fsm_reg_state_8__873), + .I2(plm_fsm_reg_state_24__887), + .I3(plm_rx0_ts2_c), + .O(plm_fsm_N_38997) + ); + defparam plm_fsm_fsm_vector_reg_rx_clear_cs_98_0_0_0_1_iv_i_o3_4_1_0_a4.INIT = 16'h8808; + LUT4 plm_fsm_fsm_vector_reg_rx_clear_cs_98_0_0_0_1_iv_i_o3_4_1_0_a4 ( + .I0(plm_fsm_N_38117_i), + .I1(plm_fsm_N_38164_i), + .I2(plm_fsm_N_38336), + .I3(plm_fsm_N_38989), + .O(plm_fsm_N_38761) + ); + defparam plm_fsm_fsm_vector_reg_rx_clear_cs_98_0_0_0_1_iv_i_0_o3_17_1.INIT = 16'h0501; + LUT4 plm_fsm_fsm_vector_reg_rx_clear_cs_98_0_0_0_1_iv_i_0_o3_17_1 ( + .I0(plm_fsm_N_38342), + .I1(plm_fsm_N_38989), + .I2(plm_fsm_N_39034), + .I3(plm_rx0_ts2_c), + .O(plm_fsm_reg_rx_clear_cs_98_0_0_0_1_iv_i_0_o3_17_1) + ); + defparam plm_fsm_fsm_vector_reg_rx_clear_cs_98_0_0_0_1_iv_i_0_6.INIT = 8'h45; + LUT3 plm_fsm_fsm_vector_reg_rx_clear_cs_98_0_0_0_1_iv_i_0_6 ( + .I0(plm_fsm_N_38761), + .I1(plm_fsm_reg_rx_clear_cs_98_0_0_0_1_iv_i_o3_4_1_0_o3_7), + .I2(plm_fsm_reg_state_24__887), + .O(plm_fsm_reg_rx_clear_cs_98_0_0_0_1_iv_i_0_6) + ); + defparam plm_fsm_fsm_vector_reg_rx_clear_cs_98_0_0_0_1_iv_i_0_o3_14.INIT = 16'h1300; + LUT4 plm_fsm_fsm_vector_reg_rx_clear_cs_98_0_0_0_1_iv_i_0_o3_14 ( + .I0(plm_fsm_N_38132_i), + .I1(plm_fsm_N_38997), + .I2(plm_fsm_N_39004), + .I3(plm_fsm_reg_rx_clear_cs_98_0_0_0_1_iv_i_0_o3_17_1), + .O(plm_fsm_N_38157_i) + ); + defparam plm_fsm_fsm_vector_reg_rx_clear_cs_98_0_0_0_1_iv_i_0_o3_12.INIT = 8'h10; + LUT3 plm_fsm_fsm_vector_reg_rx_clear_cs_98_0_0_0_1_iv_i_0_o3_12 ( + .I0(plm_fsm_N_38137_i), + .I1(plm_fsm_N_38997), + .I2(plm_fsm_reg_rx_clear_cs_98_0_0_0_1_iv_i_0_o3_17_1), + .O(plm_fsm_N_39361_i) + ); + defparam plm_fsm_fsm_vector_reg_rx_clear_cs_98_0_0_0_1_iv_i_0_a3_0.INIT = 16'hD000; + LUT4_L plm_fsm_fsm_vector_reg_rx_clear_cs_98_0_0_0_1_iv_i_0_a3_0 ( + .I0(plm_fsm_N_38157_i), + .I1(plm_fsm_N_39002), + .I2(plm_fsm_reg_state_13__41), + .I3(plm_fsm_rl_cntrout0), + .LO(plm_fsm_N_39015) + ); + defparam plm_fsm_fsm_vector_reg_rx_clear_cs_98_0_0_0_1_iv_i_0_o3_4_0.INIT = 16'hBF3F; + LUT4_L plm_fsm_fsm_vector_reg_rx_clear_cs_98_0_0_0_1_iv_i_0_o3_4_0 ( + .I0(plm_fsm_N_39002), + .I1(plm_fsm_N_39361_i), + .I2(plm_fsm_N_51395), + .I3(plm_fsm_rl_cntrout0), + .LO(plm_fsm_reg_rx_clear_cs_98_0_0_0_1_iv_i_0_o3_4_0) + ); + defparam plm_fsm_fsm_vector_reg_rx_clear_cs_98_0_0_0_1_iv_i_0_o3_4.INIT = 8'hC4; + LUT3 plm_fsm_fsm_vector_reg_rx_clear_cs_98_0_0_0_1_iv_i_0_o3_4 ( + .I0(plm_fsm_N_39361_i), + .I1(plm_fsm_reg_rx_clear_cs_98_0_0_0_1_iv_i_0_o3_4_0), + .I2(plm_fsm_reg_state_13__41), + .O(plm_fsm_N_38083_i) + ); + defparam plm_fsm_fsm_vector_reg_rx_clear_cs_98_0_0_0_1_iv_i_0_a4_1.INIT = 16'hC4CC; + LUT4 plm_fsm_fsm_vector_reg_rx_clear_cs_98_0_0_0_1_iv_i_0_a4_1 ( + .I0(plm_fsm_N_38157_i), + .I1(plm_fsm_N_38164_i), + .I2(plm_fsm_N_39015), + .I3(plm_fsm_reg_rx_clear_cs_98_0_0_0_1_iv_i_0_o3_2_1), + .O(plm_fsm_N_38591) + ); + defparam plm_fsm_fsm_vector_N_67838_i.INIT = 16'hEFFF; + LUT4_L plm_fsm_fsm_vector_N_67838_i ( + .I0(plm_fsm_N_38083_i), + .I1(plm_fsm_N_38591), + .I2(plm_fsm_reg_rx_clear_cs_98_0_0_0_1_iv_i_0_5), + .I3(plm_fsm_reg_rx_clear_cs_98_0_0_0_1_iv_i_0_6), + .LO(plm_fsm_N_67838_i) + ); + defparam plm_fsm_fsm_vector_reg_state_141_0_0_0_1_iv_0_0_0_8_.INIT = 16'hF0E0; + LUT4_L plm_fsm_fsm_vector_reg_state_141_0_0_0_1_iv_0_0_0_8_ ( + .I0(plm_fsm_N_38201_i), + .I1(plm_fsm_reg_state_141_0_0_0_1_iv_0_0_0_o3_1[8]), + .I2(plm_fsm_reg_state_141_0_0_0_1_iv_0_0_0_1[8]), + .I3(plm_rx0_ts2_c), + .LO(plm_fsm_N_9217_i) + ); + defparam plm_fsm_fsm_vector_N_67825_i.INIT = 8'h8F; + LUT3_L plm_fsm_fsm_vector_N_67825_i ( + .I0(plm_fsm_N_39029), + .I1(plm_fsm_N_39051), + .I2(plm_fsm_reg_state_141_0_0_0_1_iv_i_0_0_0[7]), + .LO(plm_fsm_N_67825_i) + ); + defparam plm_fsm_fsm_vector_N_9344_i.INIT = 16'hECA0; + LUT4_L plm_fsm_fsm_vector_N_9344_i ( + .I0(plm_fsm_N_38161_i), + .I1(plm_fsm_N_38197_i), + .I2(plm_fsm_N_51184), + .I3(plm_fsm_reg_state_5__876), + .LO(plm_fsm_N_9344_i) + ); + defparam plm_fsm_fsm_vector_N_69127_i.INIT = 16'hDCCC; + LUT4_L plm_fsm_fsm_vector_N_69127_i ( + .I0(plm_fsm_N_38197_i), + .I1(plm_fsm_N_39047), + .I2(plm_fsm_N_51184), + .I3(plm_fsm_reg_state_5__876), + .LO(plm_fsm_N_69127_i) + ); + defparam plm_fsm_fsm_vector_N_69128_i.INIT = 8'hEA; + LUT3_L plm_fsm_fsm_vector_N_69128_i ( + .I0(plm_fsm_N_38598), + .I1(plm_fsm_N_51384), + .I2(plm_fsm_reg_rx_clear_cs_4_sqmuxa_1_0), + .LO(plm_fsm_N_69128_i) + ); + defparam plm_fsm_fsm_vector_N_67848_i.INIT = 16'hBFFF; + LUT4_L plm_fsm_fsm_vector_N_67848_i ( + .I0(plm_fsm_N_38593), + .I1(plm_fsm_reg_state_141_0_0_0_2_iv_i_0_0[3]), + .I2(plm_fsm_reg_state_141_0_0_0_2_iv_i_0_2[3]), + .I3(plm_fsm_reg_state_141_0_0_0_2_iv_i_0_4[3]), + .LO(plm_fsm_N_67848_i) + ); + defparam plm_fsm_fsm_vector_N_9214_i.INIT = 16'h3733; + LUT4_L plm_fsm_fsm_vector_N_9214_i ( + .I0(plm_fsm_N_38608), + .I1(plm_fsm_reg_state_141_0_0_0_1_iv_2_32191), + .I2(plm_fsm_pc_timeout_1), + .I3(plm_fsm_reg_state_2__356), + .LO(plm_fsm_N_9214_i) + ); + defparam plm_fsm_fsm_vector_N_69295_i.INIT = 8'hEC; + LUT3_L plm_fsm_fsm_vector_N_69295_i ( + .I0(plm_fsm_N_38192_i), + .I1(plm_fsm_N_38599), + .I2(plm_fsm_reg_state_1__903), + .LO(plm_fsm_N_69295_i) + ); + defparam plm_fsm_fsm_vector_N_9213_i.INIT = 16'h7FFF; + LUT4_L plm_fsm_fsm_vector_N_9213_i ( + .I0(plm_fsm_N_67847_1), + .I1(plm_fsm_reg_state_141_0_0_0_1_iv_13[0]), + .I2(plm_fsm_reg_state_141_0_0_0_1_iv_14[0]), + .I3(plm_fsm_reg_state_141_0_0_0_1_iv_19[0]), + .LO(plm_fsm_N_9213_i) + ); + defparam plm_fsm_fsm_vector_N_67824_i.INIT = 16'hFDFC; + LUT4_L plm_fsm_fsm_vector_N_67824_i ( + .I0(plm_fsm_N_38164_i), + .I1(plm_fsm_N_38479), + .I2(plm_fsm_N_38481), + .I3(plm_fsm_N_39005), + .LO(plm_fsm_N_67824_i) + ); + defparam plm_fsm_fsm_vector_N_9333_i.INIT = 16'hEAC0; + LUT4_L plm_fsm_fsm_vector_N_9333_i ( + .I0(plm_fsm_N_38196_i), + .I1(plm_fsm_N_38601_1), + .I2(plm_fsm_N_51352), + .I3(plm_fsm_reg_state_21__882), + .LO(plm_fsm_N_9333_i) + ); + defparam plm_fsm_fsm_vector_N_69079_i.INIT = 16'hDCCC; + LUT4_L plm_fsm_fsm_vector_N_69079_i ( + .I0(plm_fsm_N_38196_i), + .I1(plm_fsm_N_38483), + .I2(plm_fsm_N_51352), + .I3(plm_fsm_reg_state_21__882), + .LO(plm_fsm_N_69079_i) + ); + defparam plm_fsm_fsm_vector_N_9335_i.INIT = 16'h88F8; + LUT4_L plm_fsm_fsm_vector_N_9335_i ( + .I0(plm_fsm_N_38196_i), + .I1(plm_fsm_reg_state_19__884), + .I2(plm_fsm_reg_state_3_sqmuxa_5_1_864), + .I3(plm_fsm_xl_cls_timeout), + .LO(plm_fsm_N_9335_i) + ); + defparam plm_fsm_fsm_vector_N_9336_i.INIT = 16'hF0F4; + LUT4_L plm_fsm_fsm_vector_N_9336_i ( + .I0(plm_fsm_N_38196_i), + .I1(plm_fsm_reg_state_19__884), + .I2(plm_fsm_reg_state_1_sqmuxa_2_865), + .I3(plm_fsm_xl_cls_timeout), + .LO(plm_fsm_N_9336_i) + ); + defparam plm_fsm_fsm_vector_N_9337_i.INIT = 16'hEEFE; + LUT4_L plm_fsm_fsm_vector_N_9337_i ( + .I0(plm_fsm_reg_link_mode_m_868), + .I1(plm_fsm_reg_state_2_sqmuxa_2_867), + .I2(plm_fsm_reg_state_4_sqmuxa_1_1_866), + .I3(plm_fsm_xl_cls_timeout), + .LO(plm_fsm_N_9337_i) + ); + defparam plm_fsm_fsm_vector_N_69350_i.INIT = 8'hBA; + LUT3_L plm_fsm_fsm_vector_N_69350_i ( + .I0(plm_fsm_N_38471), + .I1(plm_fsm_hr_timeout_i_0_0_0_o4), + .I2(plm_link_ctrl[0]), + .LO(plm_fsm_N_69350_i) + ); + defparam plm_fsm_fsm_vector_N_69076_i.INIT = 8'hEA; + LUT3_L plm_fsm_fsm_vector_N_69076_i ( + .I0(plm_fsm_N_38469), + .I1(plm_fsm_N_51392), + .I2(plm_fsm_reg_rx_clear_cs_4_sqmuxa_1_0_0), + .LO(plm_fsm_N_69076_i) + ); + defparam plm_fsm_fsm_vector_N_69358_i.INIT = 16'hC0EA; + LUT4_L plm_fsm_fsm_vector_N_69358_i ( + .I0(plm_fsm_N_38472_1), + .I1(plm_fsm_N_38473_1), + .I2(plm_fsm_reg_state_141_0_0_0_0_iv_i_0_0_a4_0_0[15]), + .I3(plm_fsm_rc_timeout_1), + .LO(plm_fsm_N_69358_i) + ); + defparam plm_fsm_fsm_vector_N_69077_i.INIT = 16'hAE0C; + LUT4_L plm_fsm_fsm_vector_N_69077_i ( + .I0(plm_fsm_N_38473_1), + .I1(plm_fsm_N_38733_1), + .I2(plm_fsm_rc_timeout_1), + .I3(plm_fsm_reg_sel_by1_890), + .LO(plm_fsm_N_69077_i) + ); + defparam plm_fsm_fsm_vector_N_69304_i.INIT = 16'hDCCC; + LUT4_L plm_fsm_fsm_vector_N_69304_i ( + .I0(plm_fsm_N_38130_i), + .I1(plm_fsm_N_38506), + .I2(plm_fsm_N_51395), + .I3(plm_fsm_reg_state_13__41), + .LO(plm_fsm_N_69304_i) + ); + defparam plm_fsm_fsm_vector_N_9220_i.INIT = 16'h7333; + LUT4_L plm_fsm_fsm_vector_N_9220_i ( + .I0(plm_fsm_N_38132_i), + .I1(plm_fsm_reg_state_141_0_0_0_1_iv_0_12_), + .I2(plm_fsm_reg_rx_clear_cs_2_sqmuxa_9_0_869), + .I3(plm_fsm_ri_cntrout0), + .LO(plm_fsm_N_9220_i) + ); + defparam plm_fsm_fsm_vector_N_9219_i.INIT = 8'h75; + LUT3_L plm_fsm_fsm_vector_N_9219_i ( + .I0(plm_fsm_N_38604_i), + .I1(plm_fsm_ci_timeout), + .I2(plm_fsm_reg_state_2_sqmuxa_3_1_870), + .LO(plm_fsm_N_9219_i) + ); + defparam plm_fsm_fsm_vector_N_69283_i.INIT = 16'hECA0; + LUT4_L plm_fsm_fsm_vector_N_69283_i ( + .I0(plm_fsm_reg_state_10__886), + .I1(plm_fsm_N_38611_1_0), + .I2(plm_fsm_N_51381), + .I3(plm_fsm_reg_state_141_0_0_0_0_iv_i_0_a4_0_0[10]), + .LO(plm_fsm_N_69283_i) + ); + defparam plm_fsm_fsm_vector_N_67832_i.INIT = 16'hA8FF; + LUT4_L plm_fsm_fsm_vector_N_67832_i ( + .I0(plm_fsm_N_38164_i), + .I1(plm_fsm_N_39004), + .I2(plm_fsm_N_39005), + .I3(plm_fsm_reg_state_141_0_0_0_1_iv_i_i_i_0[9]), + .LO(plm_fsm_N_67832_i) + ); + defparam plm_fsm_fsm_vector_reg_send_command_28_0_a2_0_a2_0_a2_0_a4_2_.INIT = 8'h02; + LUT3_L plm_fsm_fsm_vector_reg_send_command_28_0_a2_0_a2_0_a2_0_a4_2_ ( + .I0(plm_fsm_N_38173_i), + .I1(plm_fsm_reg_state_0__879), + .I2(plm_link_l0), + .LO(plm_fsm_reg_send_command_28_2_) + ); + defparam plm_fsm_fsm_vector_N_38531_i.INIT = 8'hF7; + LUT3_L plm_fsm_fsm_vector_N_38531_i ( + .I0(N_38100_i), + .I1(N_38123_i), + .I2(plm_fsm_reg_state_2__356), + .LO(plm_fsm_N_38531_i) + ); + defparam plm_fsm_fsm_vector_reg_send_command_28_0_a2_0_a2_0_a4_0_.INIT = 16'h8000; + LUT4_L plm_fsm_fsm_vector_reg_send_command_28_0_a2_0_a2_0_a4_0_ ( + .I0(N_38100_i), + .I1(N_38123_i), + .I2(plm_fsm_N_38173_i), + .I3(plm_fsm_N_38203_i), + .LO(plm_fsm_reg_send_command_28_0_) + ); + defparam plm_fsm_fsm_vector_N_67881_i.INIT = 16'hDCFC; + LUT4_L plm_fsm_fsm_vector_N_67881_i ( + .I0(plm_fsm_N_38371), + .I1(plm_fsm_N_38436), + .I2(plm_fsm_reg_state_24__887), + .I3(plm_rx0_ts1_c), + .LO(plm_fsm_N_67881_i) + ); + defparam plm_fsm_fsm_vector_reg_noscramble_27.INIT = 16'h5444; + LUT4_L plm_fsm_fsm_vector_reg_noscramble_27 ( + .I0(plm_fsm_N_38604_i), + .I1(cfg_cfg_5072[510]), + .I2(plm_rx0_linkctrl_3_), + .I3(plm_fsm_reg_sel_by1_890), + .LO(plm_fsm_reg_noscramble_27) + ); + defparam plm_fsm_invert_state_reg_rx0_polarity_3.INIT = 4'h6; + LUT2_L plm_fsm_invert_state_reg_rx0_polarity_3 ( + .I0(plm_rx0_inverted), + .I1(plm_rx0_polarity), + .LO(plm_fsm_reg_rx0_polarity_3) + ); + defparam plm_fsm_fsm_vector_reg_tx_link_num_14_0_a2_0_a2_0_a4_7_.INIT = 4'h8; + LUT2_L plm_fsm_fsm_vector_reg_tx_link_num_14_0_a2_0_a2_0_a4_7_ ( + .I0(plm_fsm_N_39047), + .I1(plm_rx0_link_num[7]), + .LO(plm_fsm_reg_tx_link_num_14[7]) + ); + defparam plm_fsm_fsm_vector_reg_tx_link_num_14_0_a2_0_a2_0_a4_6_.INIT = 4'h8; + LUT2_L plm_fsm_fsm_vector_reg_tx_link_num_14_0_a2_0_a2_0_a4_6_ ( + .I0(plm_fsm_N_39047), + .I1(plm_rx0_link_num[6]), + .LO(plm_fsm_reg_tx_link_num_14[6]) + ); + defparam plm_fsm_fsm_vector_reg_tx_link_num_14_0_a2_0_a2_0_a4_5_.INIT = 4'h8; + LUT2_L plm_fsm_fsm_vector_reg_tx_link_num_14_0_a2_0_a2_0_a4_5_ ( + .I0(plm_fsm_N_39047), + .I1(plm_rx0_link_num[5]), + .LO(plm_fsm_reg_tx_link_num_14[5]) + ); + defparam plm_fsm_fsm_vector_reg_tx_link_num_14_0_a2_0_a2_0_a4_4_.INIT = 4'h8; + LUT2_L plm_fsm_fsm_vector_reg_tx_link_num_14_0_a2_0_a2_0_a4_4_ ( + .I0(plm_fsm_N_39047), + .I1(plm_rx0_link_num[4]), + .LO(plm_fsm_reg_tx_link_num_14[4]) + ); + defparam plm_fsm_fsm_vector_reg_tx_link_num_14_0_a2_0_a2_0_a4_3_.INIT = 4'h8; + LUT2_L plm_fsm_fsm_vector_reg_tx_link_num_14_0_a2_0_a2_0_a4_3_ ( + .I0(plm_fsm_N_39047), + .I1(plm_rx0_link_num[3]), + .LO(plm_fsm_reg_tx_link_num_14[3]) + ); + defparam plm_fsm_fsm_vector_reg_tx_link_num_14_0_a2_0_a2_0_a4_2_.INIT = 4'h8; + LUT2_L plm_fsm_fsm_vector_reg_tx_link_num_14_0_a2_0_a2_0_a4_2_ ( + .I0(plm_fsm_N_39047), + .I1(plm_rx0_link_num[2]), + .LO(plm_fsm_reg_tx_link_num_14[2]) + ); + defparam plm_fsm_fsm_vector_reg_tx_link_num_14_0_a2_0_a2_0_a4_1_.INIT = 4'h8; + LUT2_L plm_fsm_fsm_vector_reg_tx_link_num_14_0_a2_0_a2_0_a4_1_ ( + .I0(plm_fsm_N_39047), + .I1(plm_rx0_link_num[1]), + .LO(plm_fsm_reg_tx_link_num_14[1]) + ); + defparam plm_fsm_fsm_vector_reg_tx_link_num_14_0_a2_0_a2_0_a4_0_.INIT = 4'h8; + LUT2_L plm_fsm_fsm_vector_reg_tx_link_num_14_0_a2_0_a2_0_a4_0_ ( + .I0(plm_fsm_N_39047), + .I1(plm_rx0_link_num[0]), + .LO(plm_fsm_reg_tx_link_num_14[0]) + ); + defparam plm_fsm_N_67847_i.INIT = 8'hF7; + LUT3_L plm_fsm_N_67847_i ( + .I0(plm_fsm_N_67847_1), + .I1(plm_fsm_N_67847_2), + .I2(plm_fsm_reg_rx_clear_cs_4_sqmuxa_1_0), + .LO(plm_fsm_N_67847_i_899) + ); + defparam plm_fsm_fsm_vector_reg_123_link_pad_36_0_a2_i_0.INIT = 16'h7000; + LUT4_L plm_fsm_fsm_vector_reg_123_link_pad_36_0_a2_i_0 ( + .I0(plm_fsm_N_38601_1), + .I1(plm_fsm_N_51352), + .I2(plm_fsm_reg_123_lane_pad_35), + .I3(plm_fsm_reg_123_link_pad_36_0_a2_i_0_1), + .LO(plm_fsm_N_24595_i) + ); + defparam plm_fsm_un1_reg_state_22_i_0_0.INIT = 8'h80; + LUT3_L plm_fsm_un1_reg_state_22_i_0_0 ( + .I0(plm_fsm_N_38198_i), + .I1(plm_fsm_N_38379_i), + .I2(plm_fsm_un1_reg_state_22_i_0_0_1_871), + .LO(plm_fsm_N_19142_i) + ); + defparam plm_fsm_N_38550_i.INIT = 4'hD; + LUT2_L plm_fsm_N_38550_i ( + .I0(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_num[2]), + .I1(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_num_2_q[0]), + .LO(N_38550_i) + ); + defparam plm_fsm_fsm_vector_reg_rx_clear_cs_98_0_0_0_1_iv_i_0_5_1.INIT = 8'h10; + LUT3 plm_fsm_fsm_vector_reg_rx_clear_cs_98_0_0_0_1_iv_i_0_5_1 ( + .I0(plm_fsm_N_8826), + .I1(plm_fsm_reg_rx_clear_cs_98_0_0_0_1_iv_i_0_o3_3_0), + .I2(plm_fsm_reg_state_23__880), + .O(plm_fsm_reg_rx_clear_cs_98_0_0_0_1_iv_i_0_5_1) + ); + defparam plm_fsm_fsm_vector_reg_rx_clear_cs_98_0_0_0_1_iv_i_0_5.INIT = 16'h0020; + LUT4 plm_fsm_fsm_vector_reg_rx_clear_cs_98_0_0_0_1_iv_i_0_5 ( + .I0(plm_fsm_N_38163), + .I1(plm_fsm_N_39018), + .I2(plm_fsm_reg_rx_clear_cs_98_0_0_0_1_iv_i_0_2), + .I3(plm_fsm_reg_rx_clear_cs_98_0_0_0_1_iv_i_0_5_1), + .O(plm_fsm_reg_rx_clear_cs_98_0_0_0_1_iv_i_0_5) + ); + defparam plm_fsm_fsm_vector_reg_rx_clear_cs_98_0_0_0_1_iv_i_0_2_1.INIT = 16'h0105; + LUT4 plm_fsm_fsm_vector_reg_rx_clear_cs_98_0_0_0_1_iv_i_0_2_1 ( + .I0(plm_fsm_N_38506), + .I1(plm_fsm_N_38989), + .I2(plm_fsm_reg_state_0__879), + .I3(plm_rx0_ts2_c), + .O(plm_fsm_reg_rx_clear_cs_98_0_0_0_1_iv_i_0_2_1) + ); + defparam plm_fsm_fsm_vector_reg_rx_clear_cs_98_0_0_0_1_iv_i_0_2.INIT = 16'h0700; + LUT4 plm_fsm_fsm_vector_reg_rx_clear_cs_98_0_0_0_1_iv_i_0_2 ( + .I0(plm_fsm_N_38061_i), + .I1(plm_fsm_N_38201_i), + .I2(plm_fsm_N_38590), + .I3(plm_fsm_reg_rx_clear_cs_98_0_0_0_1_iv_i_0_2_1), + .O(plm_fsm_reg_rx_clear_cs_98_0_0_0_1_iv_i_0_2) + ); + defparam plm_fsm_fsm_vector_reg_state_141_0_0_0_1_iv_19_1_0_.INIT = 16'h23AF; + LUT4 plm_fsm_fsm_vector_reg_state_141_0_0_0_1_iv_19_1_0_ ( + .I0(plm_fsm_N_51352), + .I1(plm_fsm_reg_state_19__884), + .I2(plm_fsm_reg_state_21__882), + .I3(plm_fsm_xl_cls_timeout), + .O(plm_fsm_reg_state_141_0_0_0_1_iv_19_1[0]) + ); + defparam plm_fsm_fsm_vector_reg_state_141_0_0_0_1_iv_19_0_.INIT = 16'h00C8; + LUT4 plm_fsm_fsm_vector_reg_state_141_0_0_0_1_iv_19_0_ ( + .I0(plm_fsm_N_38196_i), + .I1(plm_fsm_reg_state_141_0_0_0_1_iv_15[0]), + .I2(plm_fsm_reg_state_141_0_0_0_1_iv_19_1[0]), + .I3(plm_fsm_reg_state_1_sqmuxa_10_872), + .O(plm_fsm_reg_state_141_0_0_0_1_iv_19[0]) + ); + defparam plm_fsm_fsm_vector_reg_rx_clear_cs_98_0_0_0_1_iv_i_0_o3_20_2_1.INIT = 16'h1130; + LUT4 plm_fsm_fsm_vector_reg_rx_clear_cs_98_0_0_0_1_iv_i_0_o3_20_2_1 ( + .I0(plm_fsm_N_38481), + .I1(plm_fsm_N_39047), + .I2(plm_fsm_reg_rx_clear_cs_98_0_0_0_1_iv_i_o3_4_1_0_o3_10), + .I3(plm_rx0_ts2_c), + .O(plm_fsm_reg_rx_clear_cs_98_0_0_0_1_iv_i_0_o3_20_2_1) + ); + defparam plm_fsm_fsm_vector_reg_rx_clear_cs_98_0_0_0_1_iv_i_0_o3_20_2.INIT = 16'h20A0; + LUT4_L plm_fsm_fsm_vector_reg_rx_clear_cs_98_0_0_0_1_iv_i_0_o3_20_2 ( + .I0(plm_fsm_N_38198_i), + .I1(plm_fsm_N_38245_i), + .I2(plm_fsm_reg_rx_clear_cs_98_0_0_0_1_iv_i_0_o3_20_2_1), + .I3(plm_fsm_reg_state_16__357), + .LO(plm_fsm_reg_rx_clear_cs_98_0_0_0_1_iv_i_0_o3_20_2) + ); + defparam plm_fsm_fsm_vector_reg_state_141_0_0_0_1_iv_14_1_0_.INIT = 16'h2F0F; + LUT4 plm_fsm_fsm_vector_reg_state_141_0_0_0_1_iv_14_1_0_ ( + .I0(plm_fsm_N_38465_1), + .I1(plm_fsm_N_51318), + .I2(plm_fsm_reg_state_141_0_0_0_1_iv_3[0]), + .I3(plm_fsm_reg_state_7__874), + .O(plm_fsm_reg_state_141_0_0_0_1_iv_14_1[0]) + ); + defparam plm_fsm_fsm_vector_reg_state_141_0_0_0_1_iv_14_0_.INIT = 16'h040C; + LUT4_L plm_fsm_fsm_vector_reg_state_141_0_0_0_1_iv_14_0_ ( + .I0(plm_fsm_N_38472_1), + .I1(plm_fsm_reg_state_141_0_0_0_1_iv_9[0]), + .I2(plm_fsm_reg_state_141_0_0_0_1_iv_14_1[0]), + .I3(plm_fsm_rc_timeout_1), + .LO(plm_fsm_reg_state_141_0_0_0_1_iv_14[0]) + ); + defparam plm_fsm_fsm_vector_reg_state_141_0_0_0_1_iv_0_0_0_o3_8_.INIT = 8'h10; + LUT3 plm_fsm_fsm_vector_reg_state_141_0_0_0_1_iv_0_0_0_o3_8_ ( + .I0(plm_rx0_lane_pad), + .I1(plm_rx0_link_pad), + .I2(N_8824), + .O(plm_fsm_N_38102_i) + ); + defparam plm_fsm_fsm_vector_reg_rx_clear_cs_98_0_0_0_1_iv_i_0_a4_0.INIT = 8'h8A; + LUT3 plm_fsm_fsm_vector_reg_rx_clear_cs_98_0_0_0_1_iv_i_0_a4_0 ( + .I0(plm_fsm_reg_state_1__903), + .I1(plm_fsm_pa_cntrout0), + .I2(plm_fsm_N_51397), + .O(plm_fsm_N_38590) + ); + defparam plm_fsm_reg_state_2_sqmuxa_8_i_0_0_o4.INIT = 8'h04; + LUT3 plm_fsm_reg_state_2_sqmuxa_8_i_0_0_o4 ( + .I0(plm_fsm_N_38130_i), + .I1(plm_fsm_reg_state_13__41), + .I2(plm_fsm_N_51395), + .O(plm_fsm_N_38375_i) + ); + defparam plm_fsm_fsm_vector_reg_state_141_0_0_0_1_iv_i_i_i_a3_9_.INIT = 8'h80; + LUT3 plm_fsm_fsm_vector_reg_state_141_0_0_0_1_iv_i_i_i_a3_9_ ( + .I0(plm_fsm_N_38117_i), + .I1(plm_fsm_N_38126_i), + .I2(plm_fsm_N_38102_i), + .O(plm_fsm_N_39004) + ); + FDCE plm_fsm_reg_link_up_2 ( + .CE(plm_fsm_N_38559_i_888), + .C(mgt_clk), + .D(plm_fsm_reg_state_11__360), + .Q(plm_link_up_2), + .CLR(plm_rst) + ); + FDCE plm_fsm_reg_link_up_1 ( + .CE(plm_fsm_N_38559_i_888), + .C(mgt_clk), + .D(plm_fsm_reg_state_11__360), + .Q(plm_link_up_1), + .CLR(plm_rst) + ); + FDC plm_fsm_reg_fix_polarity ( + .C(mgt_clk), + .D(plm_fsm_N_38590), + .Q(plm_fsm_reg_fix_polarity_896), + .CLR(plm_rst) + ); + FDP plm_fsm_reg_123_txinhibit ( + .PRE(plm_rst), + .C(mgt_clk), + .D(plm_fsm_reg_state_0__879), + .Q(plm_tx0_txinhibit) + ); + FDP plm_fsm_reg_rx_clear_cs ( + .PRE(plm_rst), + .C(mgt_clk), + .D(plm_fsm_N_67838_i), + .Q(plm_rx_clear_cs) + ); + FDC plm_fsm_reg_state_8_ ( + .C(mgt_clk), + .D(plm_fsm_N_9217_i), + .Q(plm_fsm_reg_state_8__873), + .CLR(plm_rst) + ); + FDC plm_fsm_reg_state_7_ ( + .C(mgt_clk), + .D(plm_fsm_N_67825_i), + .Q(plm_fsm_reg_state_7__874), + .CLR(plm_rst) + ); + FDC plm_fsm_reg_state_6_ ( + .C(mgt_clk), + .D(plm_fsm_N_9344_i), + .Q(plm_fsm_reg_state_6__875), + .CLR(plm_rst) + ); + FDC plm_fsm_reg_state_5_ ( + .C(mgt_clk), + .D(plm_fsm_N_69127_i), + .Q(plm_fsm_reg_state_5__876), + .CLR(plm_rst) + ); + FDC plm_fsm_reg_state_4_ ( + .C(mgt_clk), + .D(plm_fsm_N_69128_i), + .Q(plm_fsm_reg_state_4__877), + .CLR(plm_rst) + ); + FDC plm_fsm_reg_state_3_ ( + .C(mgt_clk), + .D(plm_fsm_N_67848_i), + .Q(plm_fsm_reg_state_3__878), + .CLR(plm_rst) + ); + FDC plm_fsm_reg_state_2_ ( + .C(mgt_clk), + .D(plm_fsm_N_9214_i), + .Q(plm_fsm_reg_state_2__356), + .CLR(plm_rst) + ); + FDC plm_fsm_reg_state_1_ ( + .C(mgt_clk), + .D(plm_fsm_N_69295_i), + .Q(plm_fsm_reg_state_1__903), + .CLR(plm_rst) + ); + FDP plm_fsm_reg_state_0_ ( + .PRE(plm_rst), + .C(mgt_clk), + .D(plm_fsm_N_9213_i), + .Q(plm_fsm_reg_state_0__879) + ); + FDC plm_fsm_reg_state_23_ ( + .C(mgt_clk), + .D(plm_fsm_N_67824_i), + .Q(plm_fsm_reg_state_23__880), + .CLR(plm_rst) + ); + FDC plm_fsm_reg_state_22_ ( + .C(mgt_clk), + .D(plm_fsm_N_9333_i), + .Q(plm_fsm_reg_state_22__881), + .CLR(plm_rst) + ); + FDC plm_fsm_reg_state_21_ ( + .C(mgt_clk), + .D(plm_fsm_N_69079_i), + .Q(plm_fsm_reg_state_21__882), + .CLR(plm_rst) + ); + FDC plm_fsm_reg_state_20_ ( + .C(mgt_clk), + .D(plm_fsm_N_9335_i), + .Q(plm_fsm_reg_state_20__883), + .CLR(plm_rst) + ); + FDC plm_fsm_reg_state_19_ ( + .C(mgt_clk), + .D(plm_fsm_N_9336_i), + .Q(plm_fsm_reg_state_19__884), + .CLR(plm_rst) + ); + FDC plm_fsm_reg_state_18_ ( + .C(mgt_clk), + .D(plm_fsm_N_9337_i), + .Q(plm_fsm_reg_state_18__885), + .CLR(plm_rst) + ); + FDC plm_fsm_reg_state_17_ ( + .C(mgt_clk), + .D(plm_fsm_N_69350_i), + .Q(plm_link_ctrl[0]), + .CLR(plm_rst) + ); + FDC plm_fsm_reg_state_16_ ( + .C(mgt_clk), + .D(plm_fsm_N_69076_i), + .Q(plm_fsm_reg_state_16__357), + .CLR(plm_rst) + ); + FDC plm_fsm_reg_state_15_ ( + .C(mgt_clk), + .D(plm_fsm_N_69358_i), + .Q(plm_fsm_reg_state_15__908), + .CLR(plm_rst) + ); + FDC plm_fsm_reg_state_14_ ( + .C(mgt_clk), + .D(plm_fsm_N_69077_i), + .Q(plm_fsm_reg_state_14__909), + .CLR(plm_rst) + ); + FDC plm_fsm_reg_state_13_ ( + .C(mgt_clk), + .D(plm_fsm_N_69304_i), + .Q(plm_fsm_reg_state_13__41), + .CLR(plm_rst) + ); + FDC plm_fsm_reg_state_12_ ( + .C(mgt_clk), + .D(plm_fsm_N_9220_i), + .Q(plm_link_l0), + .CLR(plm_rst) + ); + FDC plm_fsm_reg_state_11_ ( + .C(mgt_clk), + .D(plm_fsm_N_9219_i), + .Q(plm_fsm_reg_state_11__360), + .CLR(plm_rst) + ); + FDC plm_fsm_reg_state_10_ ( + .C(mgt_clk), + .D(plm_fsm_N_69283_i), + .Q(plm_fsm_reg_state_10__886), + .CLR(plm_rst) + ); + FDC plm_fsm_reg_state_9_ ( + .C(mgt_clk), + .D(plm_fsm_N_67832_i), + .Q(plm_fsm_reg_state_9__910), + .CLR(plm_rst) + ); + FDC plm_fsm_reg_send_command_2_ ( + .C(mgt_clk), + .D(plm_fsm_reg_send_command_28_2_), + .Q(plm_send_command[2]), + .CLR(plm_rst) + ); + FDC plm_fsm_reg_send_command_1_ ( + .C(mgt_clk), + .D(plm_fsm_N_38531_i), + .Q(plm_send_command[1]), + .CLR(plm_rst) + ); + FDC plm_fsm_reg_send_command_0_ ( + .C(mgt_clk), + .D(plm_fsm_reg_send_command_28_0_), + .Q(plm_send_command[0]), + .CLR(plm_rst) + ); + FDC plm_fsm_reg_state_24_ ( + .C(mgt_clk), + .D(plm_fsm_N_67881_i), + .Q(plm_fsm_reg_state_24__887), + .CLR(plm_rst) + ); + FDCE plm_fsm_reg_rx0_old_8_ ( + .CE(plm_fsm_N_38583_i), + .C(mgt_clk), + .D(plm_rx0_lane_pad), + .Q(plm_fsm_reg_rx0_old[8]), + .CLR(plm_rst) + ); + FDCE plm_fsm_reg_rx0_old_7_ ( + .CE(plm_fsm_N_38583_i), + .C(mgt_clk), + .D(plm_rx0_lane_num[7]), + .Q(plm_fsm_reg_rx0_old[7]), + .CLR(plm_rst) + ); + FDCE plm_fsm_reg_rx0_old_6_ ( + .CE(plm_fsm_N_38583_i), + .C(mgt_clk), + .D(plm_rx0_lane_num[6]), + .Q(plm_fsm_reg_rx0_old[6]), + .CLR(plm_rst) + ); + FDCE plm_fsm_reg_rx0_old_5_ ( + .CE(plm_fsm_N_38583_i), + .C(mgt_clk), + .D(plm_rx0_lane_num[5]), + .Q(plm_fsm_reg_rx0_old[5]), + .CLR(plm_rst) + ); + FDCE plm_fsm_reg_rx0_old_4_ ( + .CE(plm_fsm_N_38583_i), + .C(mgt_clk), + .D(plm_rx0_lane_num[4]), + .Q(plm_fsm_reg_rx0_old[4]), + .CLR(plm_rst) + ); + FDCE plm_fsm_reg_rx0_old_3_ ( + .CE(plm_fsm_N_38583_i), + .C(mgt_clk), + .D(plm_rx0_lane_num[3]), + .Q(plm_fsm_reg_rx0_old[3]), + .CLR(plm_rst) + ); + FDCE plm_fsm_reg_rx0_old_2_ ( + .CE(plm_fsm_N_38583_i), + .C(mgt_clk), + .D(plm_rx0_lane_num[2]), + .Q(plm_fsm_reg_rx0_old[2]), + .CLR(plm_rst) + ); + FDCE plm_fsm_reg_rx0_old_1_ ( + .CE(plm_fsm_N_38583_i), + .C(mgt_clk), + .D(plm_rx0_lane_num[1]), + .Q(plm_fsm_reg_rx0_old[1]), + .CLR(plm_rst) + ); + FDCE plm_fsm_reg_rx0_old_0_ ( + .CE(plm_fsm_N_38583_i), + .C(mgt_clk), + .D(plm_rx0_lane_num[0]), + .Q(plm_fsm_reg_rx0_old[0]), + .CLR(plm_rst) + ); + FDCE plm_fsm_reg_xl_rx0_old_8_ ( + .CE(plm_fsm_N_38556_i), + .C(mgt_clk), + .D(plm_rx0_lane_pad), + .Q(plm_fsm_reg_xl_rx0_old[8]), + .CLR(plm_rst) + ); + FDCE plm_fsm_reg_xl_rx0_old_7_ ( + .CE(plm_fsm_N_38556_i), + .C(mgt_clk), + .D(plm_rx0_lane_num[7]), + .Q(plm_fsm_reg_xl_rx0_old[7]), + .CLR(plm_rst) + ); + FDCE plm_fsm_reg_xl_rx0_old_6_ ( + .CE(plm_fsm_N_38556_i), + .C(mgt_clk), + .D(plm_rx0_lane_num[6]), + .Q(plm_fsm_reg_xl_rx0_old[6]), + .CLR(plm_rst) + ); + FDCE plm_fsm_reg_xl_rx0_old_5_ ( + .CE(plm_fsm_N_38556_i), + .C(mgt_clk), + .D(plm_rx0_lane_num[5]), + .Q(plm_fsm_reg_xl_rx0_old[5]), + .CLR(plm_rst) + ); + FDCE plm_fsm_reg_xl_rx0_old_4_ ( + .CE(plm_fsm_N_38556_i), + .C(mgt_clk), + .D(plm_rx0_lane_num[4]), + .Q(plm_fsm_reg_xl_rx0_old[4]), + .CLR(plm_rst) + ); + FDCE plm_fsm_reg_xl_rx0_old_3_ ( + .CE(plm_fsm_N_38556_i), + .C(mgt_clk), + .D(plm_rx0_lane_num[3]), + .Q(plm_fsm_reg_xl_rx0_old[3]), + .CLR(plm_rst) + ); + FDCE plm_fsm_reg_xl_rx0_old_2_ ( + .CE(plm_fsm_N_38556_i), + .C(mgt_clk), + .D(plm_rx0_lane_num[2]), + .Q(plm_fsm_reg_xl_rx0_old[2]), + .CLR(plm_rst) + ); + FDCE plm_fsm_reg_xl_rx0_old_1_ ( + .CE(plm_fsm_N_38556_i), + .C(mgt_clk), + .D(plm_rx0_lane_num[1]), + .Q(plm_fsm_reg_xl_rx0_old[1]), + .CLR(plm_rst) + ); + FDCE plm_fsm_reg_xl_rx0_old_0_ ( + .CE(plm_fsm_N_38556_i), + .C(mgt_clk), + .D(plm_rx0_lane_num[0]), + .Q(plm_fsm_reg_xl_rx0_old[0]), + .CLR(plm_rst) + ); + FDCE plm_fsm_reg_link_up ( + .CE(plm_fsm_N_38559_i_888), + .C(mgt_clk), + .D(plm_fsm_reg_state_11__360), + .Q(plm_link_up), + .CLR(plm_rst) + ); + FDCE plm_fsm_reg_sel_by1 ( + .CE(plm_fsm_N_38537_i_889), + .C(mgt_clk), + .D(plm_fsm_reg_state_9__910), + .Q(plm_fsm_reg_sel_by1_890), + .CLR(plm_rst) + ); + FDC plm_fsm_reg_link_mode ( + .C(mgt_clk), + .D(plm_fsm_VCC_891), + .Q(plm_fsm_reg_link_mode_892), + .CLR(plm_rst) + ); + FDCE plm_fsm_reg_noscramble ( + .CE(plm_fsm_un1_reg_state_22_i_o2_1_i_a2_0_a4_893), + .C(mgt_clk), + .D(plm_fsm_reg_noscramble_27), + .Q(plm_noscramble), + .CLR(plm_rst) + ); + FDCE plm_fsm_reg_rl_throw_a_bone ( + .CE(plm_fsm_N_69263_i_894), + .C(mgt_clk), + .D(plm_fsm_reg_state_13__41), + .Q(plm_fsm_reg_rl_throw_a_bone_895), + .CLR(plm_rst) + ); + FDCE plm_fsm_reg_rx0_polarity ( + .CE(plm_fsm_reg_fix_polarity_896), + .C(mgt_clk), + .D(plm_fsm_reg_rx0_polarity_3), + .Q(plm_rx0_polarity), + .CLR(plm_rst) + ); + FDCE plm_fsm_reg_tx_link_num_7_ ( + .CE(plm_fsm_N_9826_i_897), + .C(mgt_clk), + .D(plm_fsm_reg_tx_link_num_14[7]), + .Q(plm_reg_tx_link_num[7]), + .CLR(plm_rst) + ); + FDCE plm_fsm_reg_tx_link_num_6_ ( + .CE(plm_fsm_N_9826_i_897), + .C(mgt_clk), + .D(plm_fsm_reg_tx_link_num_14[6]), + .Q(plm_reg_tx_link_num[6]), + .CLR(plm_rst) + ); + FDCE plm_fsm_reg_tx_link_num_5_ ( + .CE(plm_fsm_N_9826_i_897), + .C(mgt_clk), + .D(plm_fsm_reg_tx_link_num_14[5]), + .Q(plm_reg_tx_link_num[5]), + .CLR(plm_rst) + ); + FDCE plm_fsm_reg_tx_link_num_4_ ( + .CE(plm_fsm_N_9826_i_897), + .C(mgt_clk), + .D(plm_fsm_reg_tx_link_num_14[4]), + .Q(plm_reg_tx_link_num[4]), + .CLR(plm_rst) + ); + FDCE plm_fsm_reg_tx_link_num_3_ ( + .CE(plm_fsm_N_9826_i_897), + .C(mgt_clk), + .D(plm_fsm_reg_tx_link_num_14[3]), + .Q(plm_reg_tx_link_num[3]), + .CLR(plm_rst) + ); + FDCE plm_fsm_reg_tx_link_num_2_ ( + .CE(plm_fsm_N_9826_i_897), + .C(mgt_clk), + .D(plm_fsm_reg_tx_link_num_14[2]), + .Q(plm_reg_tx_link_num[2]), + .CLR(plm_rst) + ); + FDCE plm_fsm_reg_tx_link_num_1_ ( + .CE(plm_fsm_N_9826_i_897), + .C(mgt_clk), + .D(plm_fsm_reg_tx_link_num_14[1]), + .Q(plm_reg_tx_link_num[1]), + .CLR(plm_rst) + ); + FDCE plm_fsm_reg_tx_link_num_0_ ( + .CE(plm_fsm_N_9826_i_897), + .C(mgt_clk), + .D(plm_fsm_reg_tx_link_num_14[0]), + .Q(plm_reg_tx_link_num[0]), + .CLR(plm_rst) + ); + FDPE plm_fsm_reg_123_lane_pad ( + .PRE(plm_rst), + .CE(plm_fsm_N_19144_i), + .C(mgt_clk), + .D(plm_fsm_reg_123_lane_pad_35), + .Q(plm_fsm_reg_123_lane_pad_898) + ); + FDPE plm_fsm_reg_tx0_link_pad ( + .PRE(plm_rst), + .CE(plm_fsm_N_19146_i), + .C(mgt_clk), + .D(plm_fsm_N_67847_i_899), + .Q(plm_tx0_link_pad) + ); + FDPE plm_fsm_reg_123_link_pad ( + .PRE(plm_rst), + .CE(plm_fsm_N_19146_i), + .C(mgt_clk), + .D(plm_fsm_N_24595_i), + .Q(plm_fsm_reg_123_link_pad_900) + ); + FDPE plm_fsm_reg_tx0_lane_pad ( + .PRE(plm_rst), + .CE(plm_fsm_N_19144_i), + .C(mgt_clk), + .D(plm_fsm_N_19142_i), + .Q(plm_tx0_lane_pad) + ); + INV plm_fsm_reg_state_i_16_ ( + .I(plm_fsm_reg_state_16__357), + .O(plm_fsm_reg_state_i_16__901) + ); + INV plm_fsm_reg_state_i_1_ ( + .I(plm_fsm_reg_state_1__903), + .O(plm_fsm_reg_state_i_1__902) + ); + INV plm_fsm_reg_state_i_13_ ( + .I(plm_fsm_reg_state_13__41), + .O(plm_fsm_reg_state_i_13__904) + ); + INV plm_fsm_reg_state_i_2_ ( + .I(plm_fsm_reg_state_2__356), + .O(plm_fsm_reg_state_i_2__905) + ); + INV plm_fsm_reg_state_i_11_ ( + .I(plm_fsm_reg_state_11__360), + .O(plm_fsm_reg_state_i_11__906) + ); + INV plm_fsm_N_38123_i_i ( + .I(N_38123_i), + .O(plm_fsm_N_38123_i_i_907) + ); + defparam plm_fsm_fsm_vector_reg_state_141_0_0_0_0_iv_i_0_0_a4_1_0_15_.INIT = 4'h8; + LUT2 plm_fsm_fsm_vector_reg_state_141_0_0_0_0_iv_i_0_0_a4_1_0_15_ ( + .I0(plm_fsm_N_38134_i), + .I1(plm_fsm_reg_state_15__908), + .O(plm_fsm_N_38472_1) + ); + defparam plm_fsm_fsm_vector_reg_rx_clear_cs_98_0_0_0_1_iv_i_o3_4_1_0_a3_7_0.INIT = 8'h08; + LUT3 plm_fsm_fsm_vector_reg_rx_clear_cs_98_0_0_0_1_iv_i_o3_4_1_0_a3_7_0 ( + .I0(plm_fsm_N_38134_i), + .I1(plm_fsm_N_38983_1), + .I2(plm_fsm_reg_state_14__909), + .O(plm_fsm_N_38983) + ); + defparam plm_fsm_fsm_vector_reg_state_141_0_0_0_1_iv_i_0_0_a4_0_1_16_.INIT = 4'h8; + LUT2 plm_fsm_fsm_vector_reg_state_141_0_0_0_1_iv_i_0_0_a4_0_1_16_ ( + .I0(plm_fsm_rc_cntrout_ts2_0), + .I1(plm_fsm_reg_state_14__909), + .O(plm_fsm_N_38469) + ); + defparam plm_fsm_fsm_vector_reg_rx_clear_cs_98_0_0_0_1_iv_i_0_o3_7_2_0.INIT = 4'h7; + LUT2 plm_fsm_fsm_vector_reg_rx_clear_cs_98_0_0_0_1_iv_i_0_o3_7_2_0 ( + .I0(plm_fsm_cc_cntrout0), + .I1(plm_fsm_reg_state_9__910), + .O(plm_fsm_N_38604_i) + ); + defparam plm_fsm_fsm_vector_reg_rx_clear_cs_98_0_0_0_1_iv_i_o3_4_1_0_o3_10_0_0.INIT = 8'h57; + LUT3 plm_fsm_fsm_vector_reg_rx_clear_cs_98_0_0_0_1_iv_i_o3_4_1_0_o3_10_0_0 ( + .I0(plm_fsm_reg_expired), + .I1(plm_fsm_reg_state_14__909), + .I2(plm_fsm_reg_state_15__908), + .O(plm_fsm_reg_rx_clear_cs_98_0_0_0_1_iv_i_o3_4_1_0_o3_10_0) + ); + defparam plm_fsm_fsm_vector_N_26212_i_i_0_0.INIT = 8'hF4; + LUT3_L plm_fsm_fsm_vector_N_26212_i_i_0_0 ( + .I0(plm_fsm_rc_cntrout_ts2_0), + .I1(plm_fsm_reg_state_14__909), + .I2(plm_fsm_reg_state_15__908), + .LO(plm_fsm_N_26212_i_i_0) + ); + defparam plm_fsm_reg_rx_clear_cs_2_sqmuxa_5_i_0_0_o4_0.INIT = 4'h1; + LUT1 plm_fsm_reg_rx_clear_cs_2_sqmuxa_5_i_0_0_o4_0 ( + .I0(plm_fsm_reg_expired), + .O(plm_fsm_N_38134_i) + ); + defparam plm_fsm_fsm_vector_reg_rx_clear_cs_98_0_0_0_1_iv_i_0_a3_15_0.INIT = 4'h1; + LUT1 plm_fsm_fsm_vector_reg_rx_clear_cs_98_0_0_0_1_iv_i_0_a3_15_0 ( + .I0(plm_fsm_reg_state_9__910), + .O(plm_fsm_N_39033) + ); + GND plm_fsm_dq_timer_GND ( + .G(plm_fsm_dq_timer_GND_911) + ); + MUXCY_L plm_fsm_dq_timer_reg_count_cry_0_ ( + .CI(plm_fsm_reg_state_0__879), + .DI(plm_fsm_dq_timer_GND_911), + .LO(plm_fsm_dq_timer_reg_count_cry[0]), + .S(plm_fsm_dq_timer_reg_count_qxu[0]) + ); + XORCY plm_fsm_dq_timer_reg_count_s_0_ ( + .CI(plm_fsm_reg_state_0__879), + .LI(plm_fsm_dq_timer_reg_count_qxu[0]), + .O(plm_fsm_dq_timer_reg_count_s[0]) + ); + MUXCY_L plm_fsm_dq_timer_reg_count_cry_1_ ( + .CI(plm_fsm_dq_timer_reg_count_cry[0]), + .DI(plm_fsm_dq_timer_GND_911), + .LO(plm_fsm_dq_timer_reg_count_cry[1]), + .S(plm_fsm_dq_timer_reg_count_qxu[1]) + ); + XORCY plm_fsm_dq_timer_reg_count_s_1_ ( + .CI(plm_fsm_dq_timer_reg_count_cry[0]), + .LI(plm_fsm_dq_timer_reg_count_qxu[1]), + .O(plm_fsm_dq_timer_reg_count_s[1]) + ); + MUXCY_L plm_fsm_dq_timer_reg_count_cry_2_ ( + .CI(plm_fsm_dq_timer_reg_count_cry[1]), + .DI(plm_fsm_dq_timer_GND_911), + .LO(plm_fsm_dq_timer_reg_count_cry[2]), + .S(plm_fsm_dq_timer_reg_count_qxu[2]) + ); + XORCY plm_fsm_dq_timer_reg_count_s_2_ ( + .CI(plm_fsm_dq_timer_reg_count_cry[1]), + .LI(plm_fsm_dq_timer_reg_count_qxu[2]), + .O(plm_fsm_dq_timer_reg_count_s[2]) + ); + MUXCY_L plm_fsm_dq_timer_reg_count_cry_3_ ( + .CI(plm_fsm_dq_timer_reg_count_cry[2]), + .DI(plm_fsm_dq_timer_GND_911), + .LO(plm_fsm_dq_timer_reg_count_cry[3]), + .S(plm_fsm_dq_timer_reg_count_qxu[3]) + ); + XORCY plm_fsm_dq_timer_reg_count_s_3_ ( + .CI(plm_fsm_dq_timer_reg_count_cry[2]), + .LI(plm_fsm_dq_timer_reg_count_qxu[3]), + .O(plm_fsm_dq_timer_reg_count_s[3]) + ); + MUXCY_L plm_fsm_dq_timer_reg_count_cry_4_ ( + .CI(plm_fsm_dq_timer_reg_count_cry[3]), + .DI(plm_fsm_dq_timer_GND_911), + .LO(plm_fsm_dq_timer_reg_count_cry[4]), + .S(plm_fsm_dq_timer_reg_count_qxu[4]) + ); + XORCY plm_fsm_dq_timer_reg_count_s_4_ ( + .CI(plm_fsm_dq_timer_reg_count_cry[3]), + .LI(plm_fsm_dq_timer_reg_count_qxu[4]), + .O(plm_fsm_dq_timer_reg_count_s[4]) + ); + MUXCY_L plm_fsm_dq_timer_reg_count_cry_5_ ( + .CI(plm_fsm_dq_timer_reg_count_cry[4]), + .DI(plm_fsm_dq_timer_GND_911), + .LO(plm_fsm_dq_timer_reg_count_cry[5]), + .S(plm_fsm_dq_timer_reg_count_qxu[5]) + ); + XORCY plm_fsm_dq_timer_reg_count_s_5_ ( + .CI(plm_fsm_dq_timer_reg_count_cry[4]), + .LI(plm_fsm_dq_timer_reg_count_qxu[5]), + .O(plm_fsm_dq_timer_reg_count_s[5]) + ); + MUXCY_L plm_fsm_dq_timer_reg_count_cry_6_ ( + .CI(plm_fsm_dq_timer_reg_count_cry[5]), + .DI(plm_fsm_dq_timer_GND_911), + .LO(plm_fsm_dq_timer_reg_count_cry[6]), + .S(plm_fsm_dq_timer_reg_count_qxu[6]) + ); + XORCY plm_fsm_dq_timer_reg_count_s_6_ ( + .CI(plm_fsm_dq_timer_reg_count_cry[5]), + .LI(plm_fsm_dq_timer_reg_count_qxu[6]), + .O(plm_fsm_dq_timer_reg_count_s[6]) + ); + MUXCY_L plm_fsm_dq_timer_reg_count_cry_7_ ( + .CI(plm_fsm_dq_timer_reg_count_cry[6]), + .DI(plm_fsm_dq_timer_GND_911), + .LO(plm_fsm_dq_timer_reg_count_cry[7]), + .S(plm_fsm_dq_timer_reg_count_qxu[7]) + ); + XORCY plm_fsm_dq_timer_reg_count_s_7_ ( + .CI(plm_fsm_dq_timer_reg_count_cry[6]), + .LI(plm_fsm_dq_timer_reg_count_qxu[7]), + .O(plm_fsm_dq_timer_reg_count_s[7]) + ); + MUXCY_L plm_fsm_dq_timer_reg_count_cry_8_ ( + .CI(plm_fsm_dq_timer_reg_count_cry[7]), + .DI(plm_fsm_dq_timer_GND_911), + .LO(plm_fsm_dq_timer_reg_count_cry[8]), + .S(plm_fsm_dq_timer_reg_count_qxu[8]) + ); + XORCY plm_fsm_dq_timer_reg_count_s_8_ ( + .CI(plm_fsm_dq_timer_reg_count_cry[7]), + .LI(plm_fsm_dq_timer_reg_count_qxu[8]), + .O(plm_fsm_dq_timer_reg_count_s[8]) + ); + MUXCY_L plm_fsm_dq_timer_reg_count_cry_9_ ( + .CI(plm_fsm_dq_timer_reg_count_cry[8]), + .DI(plm_fsm_dq_timer_GND_911), + .LO(plm_fsm_dq_timer_reg_count_cry[9]), + .S(plm_fsm_dq_timer_reg_count_qxu[9]) + ); + XORCY plm_fsm_dq_timer_reg_count_s_9_ ( + .CI(plm_fsm_dq_timer_reg_count_cry[8]), + .LI(plm_fsm_dq_timer_reg_count_qxu[9]), + .O(plm_fsm_dq_timer_reg_count_s[9]) + ); + MUXCY_L plm_fsm_dq_timer_reg_count_cry_10_ ( + .CI(plm_fsm_dq_timer_reg_count_cry[9]), + .DI(plm_fsm_dq_timer_GND_911), + .LO(plm_fsm_dq_timer_reg_count_cry[10]), + .S(plm_fsm_dq_timer_reg_count_qxu[10]) + ); + XORCY plm_fsm_dq_timer_reg_count_s_10_ ( + .CI(plm_fsm_dq_timer_reg_count_cry[9]), + .LI(plm_fsm_dq_timer_reg_count_qxu[10]), + .O(plm_fsm_dq_timer_reg_count_s[10]) + ); + MUXCY_L plm_fsm_dq_timer_reg_count_cry_11_ ( + .CI(plm_fsm_dq_timer_reg_count_cry[10]), + .DI(plm_fsm_dq_timer_GND_911), + .LO(plm_fsm_dq_timer_reg_count_cry[11]), + .S(plm_fsm_dq_timer_reg_count_qxu[11]) + ); + XORCY plm_fsm_dq_timer_reg_count_s_11_ ( + .CI(plm_fsm_dq_timer_reg_count_cry[10]), + .LI(plm_fsm_dq_timer_reg_count_qxu[11]), + .O(plm_fsm_dq_timer_reg_count_s[11]) + ); + MUXCY_L plm_fsm_dq_timer_reg_count_cry_12_ ( + .CI(plm_fsm_dq_timer_reg_count_cry[11]), + .DI(plm_fsm_dq_timer_GND_911), + .LO(plm_fsm_dq_timer_reg_count_cry[12]), + .S(plm_fsm_dq_timer_reg_count_qxu[12]) + ); + XORCY plm_fsm_dq_timer_reg_count_s_12_ ( + .CI(plm_fsm_dq_timer_reg_count_cry[11]), + .LI(plm_fsm_dq_timer_reg_count_qxu[12]), + .O(plm_fsm_dq_timer_reg_count_s[12]) + ); + MUXCY_L plm_fsm_dq_timer_reg_count_cry_13_ ( + .CI(plm_fsm_dq_timer_reg_count_cry[12]), + .DI(plm_fsm_dq_timer_GND_911), + .LO(plm_fsm_dq_timer_reg_count_cry[13]), + .S(plm_fsm_dq_timer_reg_count_qxu[13]) + ); + XORCY plm_fsm_dq_timer_reg_count_s_13_ ( + .CI(plm_fsm_dq_timer_reg_count_cry[12]), + .LI(plm_fsm_dq_timer_reg_count_qxu[13]), + .O(plm_fsm_dq_timer_reg_count_s[13]) + ); + MUXCY_L plm_fsm_dq_timer_reg_count_cry_14_ ( + .CI(plm_fsm_dq_timer_reg_count_cry[13]), + .DI(plm_fsm_dq_timer_GND_911), + .LO(plm_fsm_dq_timer_reg_count_cry[14]), + .S(plm_fsm_dq_timer_reg_count_qxu[14]) + ); + XORCY plm_fsm_dq_timer_reg_count_s_14_ ( + .CI(plm_fsm_dq_timer_reg_count_cry[13]), + .LI(plm_fsm_dq_timer_reg_count_qxu[14]), + .O(plm_fsm_dq_timer_reg_count_s[14]) + ); + MUXCY_L plm_fsm_dq_timer_reg_count_cry_15_ ( + .CI(plm_fsm_dq_timer_reg_count_cry[14]), + .DI(plm_fsm_dq_timer_GND_911), + .LO(plm_fsm_dq_timer_reg_count_cry[15]), + .S(plm_fsm_dq_timer_reg_count_qxu[15]) + ); + XORCY plm_fsm_dq_timer_reg_count_s_15_ ( + .CI(plm_fsm_dq_timer_reg_count_cry[14]), + .LI(plm_fsm_dq_timer_reg_count_qxu[15]), + .O(plm_fsm_dq_timer_reg_count_s[15]) + ); + MUXCY_L plm_fsm_dq_timer_reg_count_cry_16_ ( + .CI(plm_fsm_dq_timer_reg_count_cry[15]), + .DI(plm_fsm_dq_timer_GND_911), + .LO(plm_fsm_dq_timer_reg_count_cry[16]), + .S(plm_fsm_dq_timer_reg_count_qxu[16]) + ); + XORCY plm_fsm_dq_timer_reg_count_s_16_ ( + .CI(plm_fsm_dq_timer_reg_count_cry[15]), + .LI(plm_fsm_dq_timer_reg_count_qxu[16]), + .O(plm_fsm_dq_timer_reg_count_s[16]) + ); + MUXCY_L plm_fsm_dq_timer_reg_count_cry_17_ ( + .CI(plm_fsm_dq_timer_reg_count_cry[16]), + .DI(plm_fsm_dq_timer_GND_911), + .LO(plm_fsm_dq_timer_reg_count_cry[17]), + .S(plm_fsm_dq_timer_reg_count_qxu[17]) + ); + XORCY plm_fsm_dq_timer_reg_count_s_17_ ( + .CI(plm_fsm_dq_timer_reg_count_cry[16]), + .LI(plm_fsm_dq_timer_reg_count_qxu[17]), + .O(plm_fsm_dq_timer_reg_count_s[17]) + ); + MUXCY_L plm_fsm_dq_timer_reg_count_cry_18_ ( + .CI(plm_fsm_dq_timer_reg_count_cry[17]), + .DI(plm_fsm_dq_timer_GND_911), + .LO(plm_fsm_dq_timer_reg_count_cry[18]), + .S(plm_fsm_dq_timer_reg_count_qxu[18]) + ); + XORCY plm_fsm_dq_timer_reg_count_s_18_ ( + .CI(plm_fsm_dq_timer_reg_count_cry[17]), + .LI(plm_fsm_dq_timer_reg_count_qxu[18]), + .O(plm_fsm_dq_timer_reg_count_s[18]) + ); + MUXCY_L plm_fsm_dq_timer_reg_count_cry_19_ ( + .CI(plm_fsm_dq_timer_reg_count_cry[18]), + .DI(plm_fsm_dq_timer_GND_911), + .LO(plm_fsm_dq_timer_reg_count_cry[19]), + .S(plm_fsm_dq_timer_reg_count_qxu[19]) + ); + XORCY plm_fsm_dq_timer_reg_count_s_19_ ( + .CI(plm_fsm_dq_timer_reg_count_cry[18]), + .LI(plm_fsm_dq_timer_reg_count_qxu[19]), + .O(plm_fsm_dq_timer_reg_count_s[19]) + ); + MUXCY_L plm_fsm_dq_timer_reg_count_cry_20_ ( + .CI(plm_fsm_dq_timer_reg_count_cry[19]), + .DI(plm_fsm_dq_timer_GND_911), + .LO(plm_fsm_dq_timer_reg_count_cry[20]), + .S(plm_fsm_dq_timer_reg_count_qxu[20]) + ); + XORCY plm_fsm_dq_timer_reg_count_s_20_ ( + .CI(plm_fsm_dq_timer_reg_count_cry[19]), + .LI(plm_fsm_dq_timer_reg_count_qxu[20]), + .O(plm_fsm_dq_timer_reg_count_s[20]) + ); + MUXCY_L plm_fsm_dq_timer_reg_count_cry_21_ ( + .CI(plm_fsm_dq_timer_reg_count_cry[20]), + .DI(plm_fsm_dq_timer_GND_911), + .LO(plm_fsm_dq_timer_reg_count_cry[21]), + .S(plm_fsm_dq_timer_reg_count_qxu[21]) + ); + XORCY plm_fsm_dq_timer_reg_count_s_21_ ( + .CI(plm_fsm_dq_timer_reg_count_cry[20]), + .LI(plm_fsm_dq_timer_reg_count_qxu[21]), + .O(plm_fsm_dq_timer_reg_count_s[21]) + ); + XORCY plm_fsm_dq_timer_reg_count_s_22_ ( + .CI(plm_fsm_dq_timer_reg_count_cry[21]), + .LI(plm_fsm_dq_timer_reg_count_qxu[22]), + .O(plm_fsm_dq_timer_reg_count_s[22]) + ); + defparam plm_fsm_dq_timer_count_i_m3_i_m3_0_20_.INIT = 8'hD8; + LUT3_L plm_fsm_dq_timer_count_i_m3_i_m3_0_20_ ( + .I0(cfg_cfg_5072[507]), + .I1(plm_fsm_dq_timer_reg_count[12]), + .I2(plm_fsm_dq_timer_reg_count[20]), + .LO(plm_fsm_dq_timer_N_51448) + ); + defparam plm_fsm_dq_timer_count_i_m3_i_m3_0_22_.INIT = 8'hD8; + LUT3 plm_fsm_dq_timer_count_i_m3_i_m3_0_22_ ( + .I0(cfg_cfg_5072[507]), + .I1(plm_fsm_dq_timer_reg_count[14]), + .I2(plm_fsm_dq_timer_reg_count[22]), + .O(plm_fsm_N_51450) + ); + defparam plm_fsm_dq_timer_count_i_m3_i_m3_0_21_.INIT = 8'hD8; + LUT3 plm_fsm_dq_timer_count_i_m3_i_m3_0_21_ ( + .I0(cfg_cfg_5072[507]), + .I1(plm_fsm_dq_timer_reg_count[13]), + .I2(plm_fsm_dq_timer_reg_count[21]), + .O(plm_fsm_N_51449) + ); + defparam plm_fsm_dq_timer_un4_expired_12ms_0_a2_0_a4.INIT = 16'hA280; + LUT4 plm_fsm_dq_timer_un4_expired_12ms_0_a2_0_a4 ( + .I0(plm_fsm_dq_timer_N_51448), + .I1(cfg_cfg_5072[507]), + .I2(plm_fsm_dq_timer_reg_count[11]), + .I3(plm_fsm_dq_timer_reg_count[19]), + .O(plm_fsm_N_51382) + ); + FDC plm_fsm_dq_timer_reg_count_22_ ( + .C(mgt_clk), + .D(plm_fsm_dq_timer_reg_count_s[22]), + .Q(plm_fsm_dq_timer_reg_count[22]), + .CLR(plm_rst) + ); + FDC plm_fsm_dq_timer_reg_count_21_ ( + .C(mgt_clk), + .D(plm_fsm_dq_timer_reg_count_s[21]), + .Q(plm_fsm_dq_timer_reg_count[21]), + .CLR(plm_rst) + ); + FDC plm_fsm_dq_timer_reg_count_20_ ( + .C(mgt_clk), + .D(plm_fsm_dq_timer_reg_count_s[20]), + .Q(plm_fsm_dq_timer_reg_count[20]), + .CLR(plm_rst) + ); + FDC plm_fsm_dq_timer_reg_count_19_ ( + .C(mgt_clk), + .D(plm_fsm_dq_timer_reg_count_s[19]), + .Q(plm_fsm_dq_timer_reg_count[19]), + .CLR(plm_rst) + ); + FDC plm_fsm_dq_timer_reg_count_18_ ( + .C(mgt_clk), + .D(plm_fsm_dq_timer_reg_count_s[18]), + .Q(plm_fsm_dq_timer_reg_count[18]), + .CLR(plm_rst) + ); + FDC plm_fsm_dq_timer_reg_count_17_ ( + .C(mgt_clk), + .D(plm_fsm_dq_timer_reg_count_s[17]), + .Q(plm_fsm_dq_timer_reg_count[17]), + .CLR(plm_rst) + ); + FDC plm_fsm_dq_timer_reg_count_16_ ( + .C(mgt_clk), + .D(plm_fsm_dq_timer_reg_count_s[16]), + .Q(plm_fsm_dq_timer_reg_count[16]), + .CLR(plm_rst) + ); + FDC plm_fsm_dq_timer_reg_count_15_ ( + .C(mgt_clk), + .D(plm_fsm_dq_timer_reg_count_s[15]), + .Q(plm_fsm_dq_timer_reg_count[15]), + .CLR(plm_rst) + ); + FDC plm_fsm_dq_timer_reg_count_14_ ( + .C(mgt_clk), + .D(plm_fsm_dq_timer_reg_count_s[14]), + .Q(plm_fsm_dq_timer_reg_count[14]), + .CLR(plm_rst) + ); + FDC plm_fsm_dq_timer_reg_count_13_ ( + .C(mgt_clk), + .D(plm_fsm_dq_timer_reg_count_s[13]), + .Q(plm_fsm_dq_timer_reg_count[13]), + .CLR(plm_rst) + ); + FDC plm_fsm_dq_timer_reg_count_12_ ( + .C(mgt_clk), + .D(plm_fsm_dq_timer_reg_count_s[12]), + .Q(plm_fsm_dq_timer_reg_count[12]), + .CLR(plm_rst) + ); + FDC plm_fsm_dq_timer_reg_count_11_ ( + .C(mgt_clk), + .D(plm_fsm_dq_timer_reg_count_s[11]), + .Q(plm_fsm_dq_timer_reg_count[11]), + .CLR(plm_rst) + ); + FDC plm_fsm_dq_timer_reg_count_10_ ( + .C(mgt_clk), + .D(plm_fsm_dq_timer_reg_count_s[10]), + .Q(plm_fsm_dq_timer_reg_count[10]), + .CLR(plm_rst) + ); + FDC plm_fsm_dq_timer_reg_count_9_ ( + .C(mgt_clk), + .D(plm_fsm_dq_timer_reg_count_s[9]), + .Q(plm_fsm_dq_timer_reg_count[9]), + .CLR(plm_rst) + ); + FDC plm_fsm_dq_timer_reg_count_8_ ( + .C(mgt_clk), + .D(plm_fsm_dq_timer_reg_count_s[8]), + .Q(plm_fsm_dq_timer_reg_count[8]), + .CLR(plm_rst) + ); + FDC plm_fsm_dq_timer_reg_count_7_ ( + .C(mgt_clk), + .D(plm_fsm_dq_timer_reg_count_s[7]), + .Q(plm_fsm_dq_timer_reg_count[7]), + .CLR(plm_rst) + ); + FDC plm_fsm_dq_timer_reg_count_6_ ( + .C(mgt_clk), + .D(plm_fsm_dq_timer_reg_count_s[6]), + .Q(plm_fsm_dq_timer_reg_count[6]), + .CLR(plm_rst) + ); + FDC plm_fsm_dq_timer_reg_count_5_ ( + .C(mgt_clk), + .D(plm_fsm_dq_timer_reg_count_s[5]), + .Q(plm_fsm_dq_timer_reg_count[5]), + .CLR(plm_rst) + ); + FDC plm_fsm_dq_timer_reg_count_4_ ( + .C(mgt_clk), + .D(plm_fsm_dq_timer_reg_count_s[4]), + .Q(plm_fsm_dq_timer_reg_count[4]), + .CLR(plm_rst) + ); + FDC plm_fsm_dq_timer_reg_count_3_ ( + .C(mgt_clk), + .D(plm_fsm_dq_timer_reg_count_s[3]), + .Q(plm_fsm_dq_timer_reg_count[3]), + .CLR(plm_rst) + ); + FDC plm_fsm_dq_timer_reg_count_2_ ( + .C(mgt_clk), + .D(plm_fsm_dq_timer_reg_count_s[2]), + .Q(plm_fsm_dq_timer_reg_count[2]), + .CLR(plm_rst) + ); + FDC plm_fsm_dq_timer_reg_count_1_ ( + .C(mgt_clk), + .D(plm_fsm_dq_timer_reg_count_s[1]), + .Q(plm_fsm_dq_timer_reg_count[1]), + .CLR(plm_rst) + ); + FDC plm_fsm_dq_timer_reg_count_0_ ( + .C(mgt_clk), + .D(plm_fsm_dq_timer_reg_count_s[0]), + .Q(plm_fsm_dq_timer_reg_count[0]), + .CLR(plm_rst) + ); + defparam plm_fsm_dq_timer_reg_count_qxu_0_0_.INIT = 4'h8; + LUT2_L plm_fsm_dq_timer_reg_count_qxu_0_0_ ( + .I0(plm_fsm_dq_timer_reg_count[0]), + .I1(plm_fsm_reg_state_0__879), + .LO(plm_fsm_dq_timer_reg_count_qxu[0]) + ); + defparam plm_fsm_dq_timer_reg_count_qxu_0_1_.INIT = 4'h8; + LUT2_L plm_fsm_dq_timer_reg_count_qxu_0_1_ ( + .I0(plm_fsm_dq_timer_reg_count[1]), + .I1(plm_fsm_reg_state_0__879), + .LO(plm_fsm_dq_timer_reg_count_qxu[1]) + ); + defparam plm_fsm_dq_timer_reg_count_qxu_0_2_.INIT = 4'h8; + LUT2_L plm_fsm_dq_timer_reg_count_qxu_0_2_ ( + .I0(plm_fsm_dq_timer_reg_count[2]), + .I1(plm_fsm_reg_state_0__879), + .LO(plm_fsm_dq_timer_reg_count_qxu[2]) + ); + defparam plm_fsm_dq_timer_reg_count_qxu_0_3_.INIT = 4'h8; + LUT2_L plm_fsm_dq_timer_reg_count_qxu_0_3_ ( + .I0(plm_fsm_dq_timer_reg_count[3]), + .I1(plm_fsm_reg_state_0__879), + .LO(plm_fsm_dq_timer_reg_count_qxu[3]) + ); + defparam plm_fsm_dq_timer_reg_count_qxu_0_4_.INIT = 4'h8; + LUT2_L plm_fsm_dq_timer_reg_count_qxu_0_4_ ( + .I0(plm_fsm_dq_timer_reg_count[4]), + .I1(plm_fsm_reg_state_0__879), + .LO(plm_fsm_dq_timer_reg_count_qxu[4]) + ); + defparam plm_fsm_dq_timer_reg_count_qxu_0_5_.INIT = 4'h8; + LUT2_L plm_fsm_dq_timer_reg_count_qxu_0_5_ ( + .I0(plm_fsm_dq_timer_reg_count[5]), + .I1(plm_fsm_reg_state_0__879), + .LO(plm_fsm_dq_timer_reg_count_qxu[5]) + ); + defparam plm_fsm_dq_timer_reg_count_qxu_0_6_.INIT = 4'h8; + LUT2_L plm_fsm_dq_timer_reg_count_qxu_0_6_ ( + .I0(plm_fsm_dq_timer_reg_count[6]), + .I1(plm_fsm_reg_state_0__879), + .LO(plm_fsm_dq_timer_reg_count_qxu[6]) + ); + defparam plm_fsm_dq_timer_reg_count_qxu_0_7_.INIT = 4'h8; + LUT2_L plm_fsm_dq_timer_reg_count_qxu_0_7_ ( + .I0(plm_fsm_dq_timer_reg_count[7]), + .I1(plm_fsm_reg_state_0__879), + .LO(plm_fsm_dq_timer_reg_count_qxu[7]) + ); + defparam plm_fsm_dq_timer_reg_count_qxu_0_8_.INIT = 4'h8; + LUT2_L plm_fsm_dq_timer_reg_count_qxu_0_8_ ( + .I0(plm_fsm_dq_timer_reg_count[8]), + .I1(plm_fsm_reg_state_0__879), + .LO(plm_fsm_dq_timer_reg_count_qxu[8]) + ); + defparam plm_fsm_dq_timer_reg_count_qxu_0_9_.INIT = 4'h8; + LUT2_L plm_fsm_dq_timer_reg_count_qxu_0_9_ ( + .I0(plm_fsm_dq_timer_reg_count[9]), + .I1(plm_fsm_reg_state_0__879), + .LO(plm_fsm_dq_timer_reg_count_qxu[9]) + ); + defparam plm_fsm_dq_timer_reg_count_qxu_0_10_.INIT = 4'h8; + LUT2_L plm_fsm_dq_timer_reg_count_qxu_0_10_ ( + .I0(plm_fsm_dq_timer_reg_count[10]), + .I1(plm_fsm_reg_state_0__879), + .LO(plm_fsm_dq_timer_reg_count_qxu[10]) + ); + defparam plm_fsm_dq_timer_reg_count_qxu_0_11_.INIT = 4'h8; + LUT2_L plm_fsm_dq_timer_reg_count_qxu_0_11_ ( + .I0(plm_fsm_dq_timer_reg_count[11]), + .I1(plm_fsm_reg_state_0__879), + .LO(plm_fsm_dq_timer_reg_count_qxu[11]) + ); + defparam plm_fsm_dq_timer_reg_count_qxu_0_12_.INIT = 4'h8; + LUT2_L plm_fsm_dq_timer_reg_count_qxu_0_12_ ( + .I0(plm_fsm_dq_timer_reg_count[12]), + .I1(plm_fsm_reg_state_0__879), + .LO(plm_fsm_dq_timer_reg_count_qxu[12]) + ); + defparam plm_fsm_dq_timer_reg_count_qxu_0_13_.INIT = 4'h8; + LUT2_L plm_fsm_dq_timer_reg_count_qxu_0_13_ ( + .I0(plm_fsm_dq_timer_reg_count[13]), + .I1(plm_fsm_reg_state_0__879), + .LO(plm_fsm_dq_timer_reg_count_qxu[13]) + ); + defparam plm_fsm_dq_timer_reg_count_qxu_0_14_.INIT = 4'h8; + LUT2_L plm_fsm_dq_timer_reg_count_qxu_0_14_ ( + .I0(plm_fsm_dq_timer_reg_count[14]), + .I1(plm_fsm_reg_state_0__879), + .LO(plm_fsm_dq_timer_reg_count_qxu[14]) + ); + defparam plm_fsm_dq_timer_reg_count_qxu_0_15_.INIT = 4'h8; + LUT2_L plm_fsm_dq_timer_reg_count_qxu_0_15_ ( + .I0(plm_fsm_dq_timer_reg_count[15]), + .I1(plm_fsm_reg_state_0__879), + .LO(plm_fsm_dq_timer_reg_count_qxu[15]) + ); + defparam plm_fsm_dq_timer_reg_count_qxu_0_16_.INIT = 4'h8; + LUT2_L plm_fsm_dq_timer_reg_count_qxu_0_16_ ( + .I0(plm_fsm_dq_timer_reg_count[16]), + .I1(plm_fsm_reg_state_0__879), + .LO(plm_fsm_dq_timer_reg_count_qxu[16]) + ); + defparam plm_fsm_dq_timer_reg_count_qxu_0_17_.INIT = 4'h8; + LUT2_L plm_fsm_dq_timer_reg_count_qxu_0_17_ ( + .I0(plm_fsm_dq_timer_reg_count[17]), + .I1(plm_fsm_reg_state_0__879), + .LO(plm_fsm_dq_timer_reg_count_qxu[17]) + ); + defparam plm_fsm_dq_timer_reg_count_qxu_0_18_.INIT = 4'h8; + LUT2_L plm_fsm_dq_timer_reg_count_qxu_0_18_ ( + .I0(plm_fsm_dq_timer_reg_count[18]), + .I1(plm_fsm_reg_state_0__879), + .LO(plm_fsm_dq_timer_reg_count_qxu[18]) + ); + defparam plm_fsm_dq_timer_reg_count_qxu_0_19_.INIT = 4'h8; + LUT2_L plm_fsm_dq_timer_reg_count_qxu_0_19_ ( + .I0(plm_fsm_dq_timer_reg_count[19]), + .I1(plm_fsm_reg_state_0__879), + .LO(plm_fsm_dq_timer_reg_count_qxu[19]) + ); + defparam plm_fsm_dq_timer_reg_count_qxu_0_20_.INIT = 4'h8; + LUT2_L plm_fsm_dq_timer_reg_count_qxu_0_20_ ( + .I0(plm_fsm_dq_timer_reg_count[20]), + .I1(plm_fsm_reg_state_0__879), + .LO(plm_fsm_dq_timer_reg_count_qxu[20]) + ); + defparam plm_fsm_dq_timer_reg_count_qxu_0_21_.INIT = 4'h8; + LUT2_L plm_fsm_dq_timer_reg_count_qxu_0_21_ ( + .I0(plm_fsm_dq_timer_reg_count[21]), + .I1(plm_fsm_reg_state_0__879), + .LO(plm_fsm_dq_timer_reg_count_qxu[21]) + ); + defparam plm_fsm_dq_timer_reg_count_qxu_0_22_.INIT = 4'h8; + LUT2_L plm_fsm_dq_timer_reg_count_qxu_0_22_ ( + .I0(plm_fsm_dq_timer_reg_count[22]), + .I1(plm_fsm_reg_state_0__879), + .LO(plm_fsm_dq_timer_reg_count_qxu[22]) + ); + GND plm_fsm_pa_timer_GND ( + .G(plm_fsm_pa_timer_GND_912) + ); + MUXCY_L plm_fsm_pa_timer_reg_count_cry_0_ ( + .CI(plm_fsm_reg_state_1__903), + .DI(plm_fsm_pa_timer_GND_912), + .LO(plm_fsm_pa_timer_reg_count_cry[0]), + .S(plm_fsm_pa_timer_reg_count_qxu[0]) + ); + XORCY plm_fsm_pa_timer_reg_count_s_0_ ( + .CI(plm_fsm_reg_state_1__903), + .LI(plm_fsm_pa_timer_reg_count_qxu[0]), + .O(plm_fsm_pa_timer_reg_count_s[0]) + ); + MUXCY_L plm_fsm_pa_timer_reg_count_cry_1_ ( + .CI(plm_fsm_pa_timer_reg_count_cry[0]), + .DI(plm_fsm_pa_timer_GND_912), + .LO(plm_fsm_pa_timer_reg_count_cry[1]), + .S(plm_fsm_pa_timer_reg_count_qxu[1]) + ); + XORCY plm_fsm_pa_timer_reg_count_s_1_ ( + .CI(plm_fsm_pa_timer_reg_count_cry[0]), + .LI(plm_fsm_pa_timer_reg_count_qxu[1]), + .O(plm_fsm_pa_timer_reg_count_s[1]) + ); + MUXCY_L plm_fsm_pa_timer_reg_count_cry_2_ ( + .CI(plm_fsm_pa_timer_reg_count_cry[1]), + .DI(plm_fsm_pa_timer_GND_912), + .LO(plm_fsm_pa_timer_reg_count_cry[2]), + .S(plm_fsm_pa_timer_reg_count_qxu[2]) + ); + XORCY plm_fsm_pa_timer_reg_count_s_2_ ( + .CI(plm_fsm_pa_timer_reg_count_cry[1]), + .LI(plm_fsm_pa_timer_reg_count_qxu[2]), + .O(plm_fsm_pa_timer_reg_count_s[2]) + ); + MUXCY_L plm_fsm_pa_timer_reg_count_cry_3_ ( + .CI(plm_fsm_pa_timer_reg_count_cry[2]), + .DI(plm_fsm_pa_timer_GND_912), + .LO(plm_fsm_pa_timer_reg_count_cry[3]), + .S(plm_fsm_pa_timer_reg_count_qxu[3]) + ); + XORCY plm_fsm_pa_timer_reg_count_s_3_ ( + .CI(plm_fsm_pa_timer_reg_count_cry[2]), + .LI(plm_fsm_pa_timer_reg_count_qxu[3]), + .O(plm_fsm_pa_timer_reg_count_s[3]) + ); + MUXCY_L plm_fsm_pa_timer_reg_count_cry_4_ ( + .CI(plm_fsm_pa_timer_reg_count_cry[3]), + .DI(plm_fsm_pa_timer_GND_912), + .LO(plm_fsm_pa_timer_reg_count_cry[4]), + .S(plm_fsm_pa_timer_reg_count_qxu[4]) + ); + XORCY plm_fsm_pa_timer_reg_count_s_4_ ( + .CI(plm_fsm_pa_timer_reg_count_cry[3]), + .LI(plm_fsm_pa_timer_reg_count_qxu[4]), + .O(plm_fsm_pa_timer_reg_count_s[4]) + ); + MUXCY_L plm_fsm_pa_timer_reg_count_cry_5_ ( + .CI(plm_fsm_pa_timer_reg_count_cry[4]), + .DI(plm_fsm_pa_timer_GND_912), + .LO(plm_fsm_pa_timer_reg_count_cry[5]), + .S(plm_fsm_pa_timer_reg_count_qxu[5]) + ); + XORCY plm_fsm_pa_timer_reg_count_s_5_ ( + .CI(plm_fsm_pa_timer_reg_count_cry[4]), + .LI(plm_fsm_pa_timer_reg_count_qxu[5]), + .O(plm_fsm_pa_timer_reg_count_s[5]) + ); + MUXCY_L plm_fsm_pa_timer_reg_count_cry_6_ ( + .CI(plm_fsm_pa_timer_reg_count_cry[5]), + .DI(plm_fsm_pa_timer_GND_912), + .LO(plm_fsm_pa_timer_reg_count_cry[6]), + .S(plm_fsm_pa_timer_reg_count_qxu[6]) + ); + XORCY plm_fsm_pa_timer_reg_count_s_6_ ( + .CI(plm_fsm_pa_timer_reg_count_cry[5]), + .LI(plm_fsm_pa_timer_reg_count_qxu[6]), + .O(plm_fsm_pa_timer_reg_count_s[6]) + ); + MUXCY_L plm_fsm_pa_timer_reg_count_cry_7_ ( + .CI(plm_fsm_pa_timer_reg_count_cry[6]), + .DI(plm_fsm_pa_timer_GND_912), + .LO(plm_fsm_pa_timer_reg_count_cry[7]), + .S(plm_fsm_pa_timer_reg_count_qxu[7]) + ); + XORCY plm_fsm_pa_timer_reg_count_s_7_ ( + .CI(plm_fsm_pa_timer_reg_count_cry[6]), + .LI(plm_fsm_pa_timer_reg_count_qxu[7]), + .O(plm_fsm_pa_timer_reg_count_s[7]) + ); + MUXCY_L plm_fsm_pa_timer_reg_count_cry_8_ ( + .CI(plm_fsm_pa_timer_reg_count_cry[7]), + .DI(plm_fsm_pa_timer_GND_912), + .LO(plm_fsm_pa_timer_reg_count_cry[8]), + .S(plm_fsm_pa_timer_reg_count_qxu[8]) + ); + XORCY plm_fsm_pa_timer_reg_count_s_8_ ( + .CI(plm_fsm_pa_timer_reg_count_cry[7]), + .LI(plm_fsm_pa_timer_reg_count_qxu[8]), + .O(plm_fsm_pa_timer_reg_count_s[8]) + ); + MUXCY_L plm_fsm_pa_timer_reg_count_cry_9_ ( + .CI(plm_fsm_pa_timer_reg_count_cry[8]), + .DI(plm_fsm_pa_timer_GND_912), + .LO(plm_fsm_pa_timer_reg_count_cry[9]), + .S(plm_fsm_pa_timer_reg_count_qxu[9]) + ); + XORCY plm_fsm_pa_timer_reg_count_s_9_ ( + .CI(plm_fsm_pa_timer_reg_count_cry[8]), + .LI(plm_fsm_pa_timer_reg_count_qxu[9]), + .O(plm_fsm_pa_timer_reg_count_s[9]) + ); + MUXCY_L plm_fsm_pa_timer_reg_count_cry_10_ ( + .CI(plm_fsm_pa_timer_reg_count_cry[9]), + .DI(plm_fsm_pa_timer_GND_912), + .LO(plm_fsm_pa_timer_reg_count_cry[10]), + .S(plm_fsm_pa_timer_reg_count_qxu[10]) + ); + XORCY plm_fsm_pa_timer_reg_count_s_10_ ( + .CI(plm_fsm_pa_timer_reg_count_cry[9]), + .LI(plm_fsm_pa_timer_reg_count_qxu[10]), + .O(plm_fsm_pa_timer_reg_count_s[10]) + ); + MUXCY_L plm_fsm_pa_timer_reg_count_cry_11_ ( + .CI(plm_fsm_pa_timer_reg_count_cry[10]), + .DI(plm_fsm_pa_timer_GND_912), + .LO(plm_fsm_pa_timer_reg_count_cry[11]), + .S(plm_fsm_pa_timer_reg_count_qxu[11]) + ); + XORCY plm_fsm_pa_timer_reg_count_s_11_ ( + .CI(plm_fsm_pa_timer_reg_count_cry[10]), + .LI(plm_fsm_pa_timer_reg_count_qxu[11]), + .O(plm_fsm_pa_timer_reg_count_s[11]) + ); + MUXCY_L plm_fsm_pa_timer_reg_count_cry_12_ ( + .CI(plm_fsm_pa_timer_reg_count_cry[11]), + .DI(plm_fsm_pa_timer_GND_912), + .LO(plm_fsm_pa_timer_reg_count_cry[12]), + .S(plm_fsm_pa_timer_reg_count_qxu[12]) + ); + XORCY plm_fsm_pa_timer_reg_count_s_12_ ( + .CI(plm_fsm_pa_timer_reg_count_cry[11]), + .LI(plm_fsm_pa_timer_reg_count_qxu[12]), + .O(plm_fsm_pa_timer_reg_count_s[12]) + ); + MUXCY_L plm_fsm_pa_timer_reg_count_cry_13_ ( + .CI(plm_fsm_pa_timer_reg_count_cry[12]), + .DI(plm_fsm_pa_timer_GND_912), + .LO(plm_fsm_pa_timer_reg_count_cry[13]), + .S(plm_fsm_pa_timer_reg_count_qxu[13]) + ); + XORCY plm_fsm_pa_timer_reg_count_s_13_ ( + .CI(plm_fsm_pa_timer_reg_count_cry[12]), + .LI(plm_fsm_pa_timer_reg_count_qxu[13]), + .O(plm_fsm_pa_timer_reg_count_s[13]) + ); + MUXCY_L plm_fsm_pa_timer_reg_count_cry_14_ ( + .CI(plm_fsm_pa_timer_reg_count_cry[13]), + .DI(plm_fsm_pa_timer_GND_912), + .LO(plm_fsm_pa_timer_reg_count_cry[14]), + .S(plm_fsm_pa_timer_reg_count_qxu[14]) + ); + XORCY plm_fsm_pa_timer_reg_count_s_14_ ( + .CI(plm_fsm_pa_timer_reg_count_cry[13]), + .LI(plm_fsm_pa_timer_reg_count_qxu[14]), + .O(plm_fsm_pa_timer_reg_count_s[14]) + ); + MUXCY_L plm_fsm_pa_timer_reg_count_cry_15_ ( + .CI(plm_fsm_pa_timer_reg_count_cry[14]), + .DI(plm_fsm_pa_timer_GND_912), + .LO(plm_fsm_pa_timer_reg_count_cry[15]), + .S(plm_fsm_pa_timer_reg_count_qxu[15]) + ); + XORCY plm_fsm_pa_timer_reg_count_s_15_ ( + .CI(plm_fsm_pa_timer_reg_count_cry[14]), + .LI(plm_fsm_pa_timer_reg_count_qxu[15]), + .O(plm_fsm_pa_timer_reg_count_s[15]) + ); + MUXCY_L plm_fsm_pa_timer_reg_count_cry_16_ ( + .CI(plm_fsm_pa_timer_reg_count_cry[15]), + .DI(plm_fsm_pa_timer_GND_912), + .LO(plm_fsm_pa_timer_reg_count_cry[16]), + .S(plm_fsm_pa_timer_reg_count_qxu[16]) + ); + XORCY plm_fsm_pa_timer_reg_count_s_16_ ( + .CI(plm_fsm_pa_timer_reg_count_cry[15]), + .LI(plm_fsm_pa_timer_reg_count_qxu[16]), + .O(plm_fsm_pa_timer_reg_count_s[16]) + ); + MUXCY_L plm_fsm_pa_timer_reg_count_cry_17_ ( + .CI(plm_fsm_pa_timer_reg_count_cry[16]), + .DI(plm_fsm_pa_timer_GND_912), + .LO(plm_fsm_pa_timer_reg_count_cry[17]), + .S(plm_fsm_pa_timer_reg_count_qxu[17]) + ); + XORCY plm_fsm_pa_timer_reg_count_s_17_ ( + .CI(plm_fsm_pa_timer_reg_count_cry[16]), + .LI(plm_fsm_pa_timer_reg_count_qxu[17]), + .O(plm_fsm_pa_timer_reg_count_s[17]) + ); + MUXCY_L plm_fsm_pa_timer_reg_count_cry_18_ ( + .CI(plm_fsm_pa_timer_reg_count_cry[17]), + .DI(plm_fsm_pa_timer_GND_912), + .LO(plm_fsm_pa_timer_reg_count_cry[18]), + .S(plm_fsm_pa_timer_reg_count_qxu[18]) + ); + XORCY plm_fsm_pa_timer_reg_count_s_18_ ( + .CI(plm_fsm_pa_timer_reg_count_cry[17]), + .LI(plm_fsm_pa_timer_reg_count_qxu[18]), + .O(plm_fsm_pa_timer_reg_count_s[18]) + ); + MUXCY_L plm_fsm_pa_timer_reg_count_cry_19_ ( + .CI(plm_fsm_pa_timer_reg_count_cry[18]), + .DI(plm_fsm_pa_timer_GND_912), + .LO(plm_fsm_pa_timer_reg_count_cry[19]), + .S(plm_fsm_pa_timer_reg_count_qxu[19]) + ); + XORCY plm_fsm_pa_timer_reg_count_s_19_ ( + .CI(plm_fsm_pa_timer_reg_count_cry[18]), + .LI(plm_fsm_pa_timer_reg_count_qxu[19]), + .O(plm_fsm_pa_timer_reg_count_s[19]) + ); + MUXCY_L plm_fsm_pa_timer_reg_count_cry_20_ ( + .CI(plm_fsm_pa_timer_reg_count_cry[19]), + .DI(plm_fsm_pa_timer_GND_912), + .LO(plm_fsm_pa_timer_reg_count_cry[20]), + .S(plm_fsm_pa_timer_reg_count_qxu[20]) + ); + XORCY plm_fsm_pa_timer_reg_count_s_20_ ( + .CI(plm_fsm_pa_timer_reg_count_cry[19]), + .LI(plm_fsm_pa_timer_reg_count_qxu[20]), + .O(plm_fsm_pa_timer_reg_count_s[20]) + ); + MUXCY_L plm_fsm_pa_timer_reg_count_cry_21_ ( + .CI(plm_fsm_pa_timer_reg_count_cry[20]), + .DI(plm_fsm_pa_timer_GND_912), + .LO(plm_fsm_pa_timer_reg_count_cry[21]), + .S(plm_fsm_pa_timer_reg_count_qxu[21]) + ); + XORCY plm_fsm_pa_timer_reg_count_s_21_ ( + .CI(plm_fsm_pa_timer_reg_count_cry[20]), + .LI(plm_fsm_pa_timer_reg_count_qxu[21]), + .O(plm_fsm_pa_timer_reg_count_s[21]) + ); + XORCY plm_fsm_pa_timer_reg_count_s_22_ ( + .CI(plm_fsm_pa_timer_reg_count_cry[21]), + .LI(plm_fsm_pa_timer_reg_count_qxu[22]), + .O(plm_fsm_pa_timer_reg_count_s[22]) + ); + defparam plm_fsm_pa_timer_count_i_m3_i_m3_0_20_.INIT = 8'hD8; + LUT3_L plm_fsm_pa_timer_count_i_m3_i_m3_0_20_ ( + .I0(cfg_cfg_5072[507]), + .I1(plm_fsm_pa_timer_reg_count[12]), + .I2(plm_fsm_pa_timer_reg_count[20]), + .LO(plm_fsm_pa_timer_N_51451) + ); + defparam plm_fsm_pa_timer_un3_expired_24ms_0_a2_0_a2_0_a4.INIT = 16'hA280; + LUT4_L plm_fsm_pa_timer_un3_expired_24ms_0_a2_0_a2_0_a4 ( + .I0(plm_fsm_pa_timer_N_51451), + .I1(cfg_cfg_5072[507]), + .I2(plm_fsm_pa_timer_reg_count[13]), + .I3(plm_fsm_pa_timer_reg_count[21]), + .LO(plm_fsm_pa_timer_N_51396) + ); + defparam plm_fsm_pa_timer_un1_expired_24ms_0_a2_0_a2_0_a4.INIT = 16'h0415; + LUT4 plm_fsm_pa_timer_un1_expired_24ms_0_a2_0_a2_0_a4 ( + .I0(plm_fsm_pa_timer_N_51396), + .I1(cfg_cfg_5072[507]), + .I2(plm_fsm_pa_timer_reg_count[14]), + .I3(plm_fsm_pa_timer_reg_count[22]), + .O(plm_fsm_N_51397) + ); + FDC plm_fsm_pa_timer_reg_count_22_ ( + .C(mgt_clk), + .D(plm_fsm_pa_timer_reg_count_s[22]), + .Q(plm_fsm_pa_timer_reg_count[22]), + .CLR(plm_rst) + ); + FDC plm_fsm_pa_timer_reg_count_21_ ( + .C(mgt_clk), + .D(plm_fsm_pa_timer_reg_count_s[21]), + .Q(plm_fsm_pa_timer_reg_count[21]), + .CLR(plm_rst) + ); + FDC plm_fsm_pa_timer_reg_count_20_ ( + .C(mgt_clk), + .D(plm_fsm_pa_timer_reg_count_s[20]), + .Q(plm_fsm_pa_timer_reg_count[20]), + .CLR(plm_rst) + ); + FDC plm_fsm_pa_timer_reg_count_19_ ( + .C(mgt_clk), + .D(plm_fsm_pa_timer_reg_count_s[19]), + .Q(plm_fsm_pa_timer_reg_count[19]), + .CLR(plm_rst) + ); + FDC plm_fsm_pa_timer_reg_count_18_ ( + .C(mgt_clk), + .D(plm_fsm_pa_timer_reg_count_s[18]), + .Q(plm_fsm_pa_timer_reg_count[18]), + .CLR(plm_rst) + ); + FDC plm_fsm_pa_timer_reg_count_17_ ( + .C(mgt_clk), + .D(plm_fsm_pa_timer_reg_count_s[17]), + .Q(plm_fsm_pa_timer_reg_count[17]), + .CLR(plm_rst) + ); + FDC plm_fsm_pa_timer_reg_count_16_ ( + .C(mgt_clk), + .D(plm_fsm_pa_timer_reg_count_s[16]), + .Q(plm_fsm_pa_timer_reg_count[16]), + .CLR(plm_rst) + ); + FDC plm_fsm_pa_timer_reg_count_15_ ( + .C(mgt_clk), + .D(plm_fsm_pa_timer_reg_count_s[15]), + .Q(plm_fsm_pa_timer_reg_count[15]), + .CLR(plm_rst) + ); + FDC plm_fsm_pa_timer_reg_count_14_ ( + .C(mgt_clk), + .D(plm_fsm_pa_timer_reg_count_s[14]), + .Q(plm_fsm_pa_timer_reg_count[14]), + .CLR(plm_rst) + ); + FDC plm_fsm_pa_timer_reg_count_13_ ( + .C(mgt_clk), + .D(plm_fsm_pa_timer_reg_count_s[13]), + .Q(plm_fsm_pa_timer_reg_count[13]), + .CLR(plm_rst) + ); + FDC plm_fsm_pa_timer_reg_count_12_ ( + .C(mgt_clk), + .D(plm_fsm_pa_timer_reg_count_s[12]), + .Q(plm_fsm_pa_timer_reg_count[12]), + .CLR(plm_rst) + ); + FDC plm_fsm_pa_timer_reg_count_11_ ( + .C(mgt_clk), + .D(plm_fsm_pa_timer_reg_count_s[11]), + .Q(plm_fsm_pa_timer_reg_count[11]), + .CLR(plm_rst) + ); + FDC plm_fsm_pa_timer_reg_count_10_ ( + .C(mgt_clk), + .D(plm_fsm_pa_timer_reg_count_s[10]), + .Q(plm_fsm_pa_timer_reg_count[10]), + .CLR(plm_rst) + ); + FDC plm_fsm_pa_timer_reg_count_9_ ( + .C(mgt_clk), + .D(plm_fsm_pa_timer_reg_count_s[9]), + .Q(plm_fsm_pa_timer_reg_count[9]), + .CLR(plm_rst) + ); + FDC plm_fsm_pa_timer_reg_count_8_ ( + .C(mgt_clk), + .D(plm_fsm_pa_timer_reg_count_s[8]), + .Q(plm_fsm_pa_timer_reg_count[8]), + .CLR(plm_rst) + ); + FDC plm_fsm_pa_timer_reg_count_7_ ( + .C(mgt_clk), + .D(plm_fsm_pa_timer_reg_count_s[7]), + .Q(plm_fsm_pa_timer_reg_count[7]), + .CLR(plm_rst) + ); + FDC plm_fsm_pa_timer_reg_count_6_ ( + .C(mgt_clk), + .D(plm_fsm_pa_timer_reg_count_s[6]), + .Q(plm_fsm_pa_timer_reg_count[6]), + .CLR(plm_rst) + ); + FDC plm_fsm_pa_timer_reg_count_5_ ( + .C(mgt_clk), + .D(plm_fsm_pa_timer_reg_count_s[5]), + .Q(plm_fsm_pa_timer_reg_count[5]), + .CLR(plm_rst) + ); + FDC plm_fsm_pa_timer_reg_count_4_ ( + .C(mgt_clk), + .D(plm_fsm_pa_timer_reg_count_s[4]), + .Q(plm_fsm_pa_timer_reg_count[4]), + .CLR(plm_rst) + ); + FDC plm_fsm_pa_timer_reg_count_3_ ( + .C(mgt_clk), + .D(plm_fsm_pa_timer_reg_count_s[3]), + .Q(plm_fsm_pa_timer_reg_count[3]), + .CLR(plm_rst) + ); + FDC plm_fsm_pa_timer_reg_count_2_ ( + .C(mgt_clk), + .D(plm_fsm_pa_timer_reg_count_s[2]), + .Q(plm_fsm_pa_timer_reg_count[2]), + .CLR(plm_rst) + ); + FDC plm_fsm_pa_timer_reg_count_1_ ( + .C(mgt_clk), + .D(plm_fsm_pa_timer_reg_count_s[1]), + .Q(plm_fsm_pa_timer_reg_count[1]), + .CLR(plm_rst) + ); + FDC plm_fsm_pa_timer_reg_count_0_ ( + .C(mgt_clk), + .D(plm_fsm_pa_timer_reg_count_s[0]), + .Q(plm_fsm_pa_timer_reg_count[0]), + .CLR(plm_rst) + ); + defparam plm_fsm_pa_timer_reg_count_qxu_0_0_.INIT = 4'h8; + LUT2_L plm_fsm_pa_timer_reg_count_qxu_0_0_ ( + .I0(plm_fsm_pa_timer_reg_count[0]), + .I1(plm_fsm_reg_state_1__903), + .LO(plm_fsm_pa_timer_reg_count_qxu[0]) + ); + defparam plm_fsm_pa_timer_reg_count_qxu_0_1_.INIT = 4'h8; + LUT2_L plm_fsm_pa_timer_reg_count_qxu_0_1_ ( + .I0(plm_fsm_pa_timer_reg_count[1]), + .I1(plm_fsm_reg_state_1__903), + .LO(plm_fsm_pa_timer_reg_count_qxu[1]) + ); + defparam plm_fsm_pa_timer_reg_count_qxu_0_2_.INIT = 4'h8; + LUT2_L plm_fsm_pa_timer_reg_count_qxu_0_2_ ( + .I0(plm_fsm_pa_timer_reg_count[2]), + .I1(plm_fsm_reg_state_1__903), + .LO(plm_fsm_pa_timer_reg_count_qxu[2]) + ); + defparam plm_fsm_pa_timer_reg_count_qxu_0_3_.INIT = 4'h8; + LUT2_L plm_fsm_pa_timer_reg_count_qxu_0_3_ ( + .I0(plm_fsm_pa_timer_reg_count[3]), + .I1(plm_fsm_reg_state_1__903), + .LO(plm_fsm_pa_timer_reg_count_qxu[3]) + ); + defparam plm_fsm_pa_timer_reg_count_qxu_0_4_.INIT = 4'h8; + LUT2_L plm_fsm_pa_timer_reg_count_qxu_0_4_ ( + .I0(plm_fsm_pa_timer_reg_count[4]), + .I1(plm_fsm_reg_state_1__903), + .LO(plm_fsm_pa_timer_reg_count_qxu[4]) + ); + defparam plm_fsm_pa_timer_reg_count_qxu_0_5_.INIT = 4'h8; + LUT2_L plm_fsm_pa_timer_reg_count_qxu_0_5_ ( + .I0(plm_fsm_pa_timer_reg_count[5]), + .I1(plm_fsm_reg_state_1__903), + .LO(plm_fsm_pa_timer_reg_count_qxu[5]) + ); + defparam plm_fsm_pa_timer_reg_count_qxu_0_6_.INIT = 4'h8; + LUT2_L plm_fsm_pa_timer_reg_count_qxu_0_6_ ( + .I0(plm_fsm_pa_timer_reg_count[6]), + .I1(plm_fsm_reg_state_1__903), + .LO(plm_fsm_pa_timer_reg_count_qxu[6]) + ); + defparam plm_fsm_pa_timer_reg_count_qxu_0_7_.INIT = 4'h8; + LUT2_L plm_fsm_pa_timer_reg_count_qxu_0_7_ ( + .I0(plm_fsm_pa_timer_reg_count[7]), + .I1(plm_fsm_reg_state_1__903), + .LO(plm_fsm_pa_timer_reg_count_qxu[7]) + ); + defparam plm_fsm_pa_timer_reg_count_qxu_0_8_.INIT = 4'h8; + LUT2_L plm_fsm_pa_timer_reg_count_qxu_0_8_ ( + .I0(plm_fsm_pa_timer_reg_count[8]), + .I1(plm_fsm_reg_state_1__903), + .LO(plm_fsm_pa_timer_reg_count_qxu[8]) + ); + defparam plm_fsm_pa_timer_reg_count_qxu_0_9_.INIT = 4'h8; + LUT2_L plm_fsm_pa_timer_reg_count_qxu_0_9_ ( + .I0(plm_fsm_pa_timer_reg_count[9]), + .I1(plm_fsm_reg_state_1__903), + .LO(plm_fsm_pa_timer_reg_count_qxu[9]) + ); + defparam plm_fsm_pa_timer_reg_count_qxu_0_10_.INIT = 4'h8; + LUT2_L plm_fsm_pa_timer_reg_count_qxu_0_10_ ( + .I0(plm_fsm_pa_timer_reg_count[10]), + .I1(plm_fsm_reg_state_1__903), + .LO(plm_fsm_pa_timer_reg_count_qxu[10]) + ); + defparam plm_fsm_pa_timer_reg_count_qxu_0_11_.INIT = 4'h8; + LUT2_L plm_fsm_pa_timer_reg_count_qxu_0_11_ ( + .I0(plm_fsm_pa_timer_reg_count[11]), + .I1(plm_fsm_reg_state_1__903), + .LO(plm_fsm_pa_timer_reg_count_qxu[11]) + ); + defparam plm_fsm_pa_timer_reg_count_qxu_0_12_.INIT = 4'h8; + LUT2_L plm_fsm_pa_timer_reg_count_qxu_0_12_ ( + .I0(plm_fsm_pa_timer_reg_count[12]), + .I1(plm_fsm_reg_state_1__903), + .LO(plm_fsm_pa_timer_reg_count_qxu[12]) + ); + defparam plm_fsm_pa_timer_reg_count_qxu_0_13_.INIT = 4'h8; + LUT2_L plm_fsm_pa_timer_reg_count_qxu_0_13_ ( + .I0(plm_fsm_pa_timer_reg_count[13]), + .I1(plm_fsm_reg_state_1__903), + .LO(plm_fsm_pa_timer_reg_count_qxu[13]) + ); + defparam plm_fsm_pa_timer_reg_count_qxu_0_14_.INIT = 4'h8; + LUT2_L plm_fsm_pa_timer_reg_count_qxu_0_14_ ( + .I0(plm_fsm_pa_timer_reg_count[14]), + .I1(plm_fsm_reg_state_1__903), + .LO(plm_fsm_pa_timer_reg_count_qxu[14]) + ); + defparam plm_fsm_pa_timer_reg_count_qxu_0_15_.INIT = 4'h8; + LUT2_L plm_fsm_pa_timer_reg_count_qxu_0_15_ ( + .I0(plm_fsm_pa_timer_reg_count[15]), + .I1(plm_fsm_reg_state_1__903), + .LO(plm_fsm_pa_timer_reg_count_qxu[15]) + ); + defparam plm_fsm_pa_timer_reg_count_qxu_0_16_.INIT = 4'h8; + LUT2_L plm_fsm_pa_timer_reg_count_qxu_0_16_ ( + .I0(plm_fsm_pa_timer_reg_count[16]), + .I1(plm_fsm_reg_state_1__903), + .LO(plm_fsm_pa_timer_reg_count_qxu[16]) + ); + defparam plm_fsm_pa_timer_reg_count_qxu_0_17_.INIT = 4'h8; + LUT2_L plm_fsm_pa_timer_reg_count_qxu_0_17_ ( + .I0(plm_fsm_pa_timer_reg_count[17]), + .I1(plm_fsm_reg_state_1__903), + .LO(plm_fsm_pa_timer_reg_count_qxu[17]) + ); + defparam plm_fsm_pa_timer_reg_count_qxu_0_18_.INIT = 4'h8; + LUT2_L plm_fsm_pa_timer_reg_count_qxu_0_18_ ( + .I0(plm_fsm_pa_timer_reg_count[18]), + .I1(plm_fsm_reg_state_1__903), + .LO(plm_fsm_pa_timer_reg_count_qxu[18]) + ); + defparam plm_fsm_pa_timer_reg_count_qxu_0_19_.INIT = 4'h8; + LUT2_L plm_fsm_pa_timer_reg_count_qxu_0_19_ ( + .I0(plm_fsm_pa_timer_reg_count[19]), + .I1(plm_fsm_reg_state_1__903), + .LO(plm_fsm_pa_timer_reg_count_qxu[19]) + ); + defparam plm_fsm_pa_timer_reg_count_qxu_0_20_.INIT = 4'h8; + LUT2_L plm_fsm_pa_timer_reg_count_qxu_0_20_ ( + .I0(plm_fsm_pa_timer_reg_count[20]), + .I1(plm_fsm_reg_state_1__903), + .LO(plm_fsm_pa_timer_reg_count_qxu[20]) + ); + defparam plm_fsm_pa_timer_reg_count_qxu_0_21_.INIT = 4'h8; + LUT2_L plm_fsm_pa_timer_reg_count_qxu_0_21_ ( + .I0(plm_fsm_pa_timer_reg_count[21]), + .I1(plm_fsm_reg_state_1__903), + .LO(plm_fsm_pa_timer_reg_count_qxu[21]) + ); + defparam plm_fsm_pa_timer_reg_count_qxu_0_22_.INIT = 4'h8; + LUT2_L plm_fsm_pa_timer_reg_count_qxu_0_22_ ( + .I0(plm_fsm_pa_timer_reg_count[22]), + .I1(plm_fsm_reg_state_1__903), + .LO(plm_fsm_pa_timer_reg_count_qxu[22]) + ); + VCC plm_fsm_pa_counter0_VCC ( + .P(plm_fsm_pa_counter0_VCC_913) + ); + MUXCY_L plm_fsm_pa_counter0_reg_rx_count_cry_0_ ( + .CI(N_18705_i_i_44), + .DI(plm_fsm_pa_counter0_VCC_913), + .LO(plm_fsm_pa_counter0_reg_rx_count_cry[0]), + .S(plm_fsm_pa_counter0_reg_rx_count_qxu[0]) + ); + XORCY plm_fsm_pa_counter0_reg_rx_count_s_0_ ( + .CI(N_18705_i_i_44), + .LI(plm_fsm_pa_counter0_reg_rx_count_qxu[0]), + .O(plm_fsm_pa_counter0_reg_rx_count_s[0]) + ); + MUXCY_L plm_fsm_pa_counter0_reg_rx_count_cry_1_ ( + .CI(plm_fsm_pa_counter0_reg_rx_count_cry[0]), + .DI(plm_fsm_pa_counter0_VCC_913), + .LO(plm_fsm_pa_counter0_reg_rx_count_cry[1]), + .S(plm_fsm_pa_counter0_reg_rx_count_qxu[1]) + ); + XORCY plm_fsm_pa_counter0_reg_rx_count_s_1_ ( + .CI(plm_fsm_pa_counter0_reg_rx_count_cry[0]), + .LI(plm_fsm_pa_counter0_reg_rx_count_qxu[1]), + .O(plm_fsm_pa_counter0_reg_rx_count_s[1]) + ); + MUXCY_L plm_fsm_pa_counter0_reg_rx_count_cry_2_ ( + .CI(plm_fsm_pa_counter0_reg_rx_count_cry[1]), + .DI(plm_fsm_pa_counter0_VCC_913), + .LO(plm_fsm_pa_counter0_reg_rx_count_cry[2]), + .S(plm_fsm_pa_counter0_reg_rx_count_qxu[2]) + ); + XORCY plm_fsm_pa_counter0_reg_rx_count_s_2_ ( + .CI(plm_fsm_pa_counter0_reg_rx_count_cry[1]), + .LI(plm_fsm_pa_counter0_reg_rx_count_qxu[2]), + .O(plm_fsm_pa_counter0_reg_rx_count_s[2]) + ); + MUXCY_L plm_fsm_pa_counter0_reg_rx_count_cry_3_ ( + .CI(plm_fsm_pa_counter0_reg_rx_count_cry[2]), + .DI(plm_fsm_pa_counter0_VCC_913), + .LO(plm_fsm_pa_counter0_reg_rx_count_cry[3]), + .S(plm_fsm_pa_counter0_reg_rx_count_qxu[3]) + ); + XORCY plm_fsm_pa_counter0_reg_rx_count_s_3_ ( + .CI(plm_fsm_pa_counter0_reg_rx_count_cry[2]), + .LI(plm_fsm_pa_counter0_reg_rx_count_qxu[3]), + .O(plm_fsm_pa_counter0_reg_rx_count_s[3]) + ); + MUXCY_L plm_fsm_pa_counter0_reg_rx_count_cry_4_ ( + .CI(plm_fsm_pa_counter0_reg_rx_count_cry[3]), + .DI(plm_fsm_pa_counter0_VCC_913), + .LO(plm_fsm_pa_counter0_reg_rx_count_cry[4]), + .S(plm_fsm_pa_counter0_reg_rx_count_qxu[4]) + ); + XORCY plm_fsm_pa_counter0_reg_rx_count_s_4_ ( + .CI(plm_fsm_pa_counter0_reg_rx_count_cry[3]), + .LI(plm_fsm_pa_counter0_reg_rx_count_qxu[4]), + .O(plm_fsm_pa_counter0_reg_rx_count_s[4]) + ); + MUXCY_L plm_fsm_pa_counter0_reg_rx_count_cry_5_ ( + .CI(plm_fsm_pa_counter0_reg_rx_count_cry[4]), + .DI(plm_fsm_pa_counter0_VCC_913), + .LO(plm_fsm_pa_counter0_reg_rx_count_cry[5]), + .S(plm_fsm_pa_counter0_reg_rx_count_qxu[5]) + ); + XORCY plm_fsm_pa_counter0_reg_rx_count_s_5_ ( + .CI(plm_fsm_pa_counter0_reg_rx_count_cry[4]), + .LI(plm_fsm_pa_counter0_reg_rx_count_qxu[5]), + .O(plm_fsm_pa_counter0_reg_rx_count_s[5]) + ); + MUXCY_L plm_fsm_pa_counter0_reg_rx_count_cry_6_ ( + .CI(plm_fsm_pa_counter0_reg_rx_count_cry[5]), + .DI(plm_fsm_pa_counter0_VCC_913), + .LO(plm_fsm_pa_counter0_reg_rx_count_cry[6]), + .S(plm_fsm_pa_counter0_reg_rx_count_qxu[6]) + ); + XORCY plm_fsm_pa_counter0_reg_rx_count_s_6_ ( + .CI(plm_fsm_pa_counter0_reg_rx_count_cry[5]), + .LI(plm_fsm_pa_counter0_reg_rx_count_qxu[6]), + .O(plm_fsm_pa_counter0_reg_rx_count_s[6]) + ); + XORCY plm_fsm_pa_counter0_reg_rx_count_s_7_ ( + .CI(plm_fsm_pa_counter0_reg_rx_count_cry[6]), + .LI(plm_fsm_pa_counter0_reg_rx_count_qxu[7]), + .O(plm_fsm_pa_counter0_reg_rx_count_s[7]) + ); + MUXCY_L plm_fsm_pa_counter0_reg_tx_count_cry_0_ ( + .CI(plm_fsm_pa_counter0_un1_enable_1_i_914), + .DI(plm_fsm_pa_counter0_VCC_913), + .LO(plm_fsm_pa_counter0_reg_tx_count_cry[0]), + .S(plm_fsm_pa_counter0_reg_tx_count_qxu[0]) + ); + XORCY plm_fsm_pa_counter0_reg_tx_count_s_0_ ( + .CI(plm_fsm_pa_counter0_un1_enable_1_i_914), + .LI(plm_fsm_pa_counter0_reg_tx_count_qxu[0]), + .O(plm_fsm_pa_counter0_reg_tx_count_s[0]) + ); + MUXCY_L plm_fsm_pa_counter0_reg_tx_count_cry_1_ ( + .CI(plm_fsm_pa_counter0_reg_tx_count_cry[0]), + .DI(plm_fsm_pa_counter0_VCC_913), + .LO(plm_fsm_pa_counter0_reg_tx_count_cry[1]), + .S(plm_fsm_pa_counter0_reg_tx_count_qxu[1]) + ); + XORCY plm_fsm_pa_counter0_reg_tx_count_s_1_ ( + .CI(plm_fsm_pa_counter0_reg_tx_count_cry[0]), + .LI(plm_fsm_pa_counter0_reg_tx_count_qxu[1]), + .O(plm_fsm_pa_counter0_reg_tx_count_s[1]) + ); + MUXCY_L plm_fsm_pa_counter0_reg_tx_count_cry_2_ ( + .CI(plm_fsm_pa_counter0_reg_tx_count_cry[1]), + .DI(plm_fsm_pa_counter0_VCC_913), + .LO(plm_fsm_pa_counter0_reg_tx_count_cry[2]), + .S(plm_fsm_pa_counter0_reg_tx_count_qxu[2]) + ); + XORCY plm_fsm_pa_counter0_reg_tx_count_s_2_ ( + .CI(plm_fsm_pa_counter0_reg_tx_count_cry[1]), + .LI(plm_fsm_pa_counter0_reg_tx_count_qxu[2]), + .O(plm_fsm_pa_counter0_reg_tx_count_s[2]) + ); + MUXCY_L plm_fsm_pa_counter0_reg_tx_count_cry_3_ ( + .CI(plm_fsm_pa_counter0_reg_tx_count_cry[2]), + .DI(plm_fsm_pa_counter0_VCC_913), + .LO(plm_fsm_pa_counter0_reg_tx_count_cry[3]), + .S(plm_fsm_pa_counter0_reg_tx_count_qxu[3]) + ); + XORCY plm_fsm_pa_counter0_reg_tx_count_s_3_ ( + .CI(plm_fsm_pa_counter0_reg_tx_count_cry[2]), + .LI(plm_fsm_pa_counter0_reg_tx_count_qxu[3]), + .O(plm_fsm_pa_counter0_reg_tx_count_s[3]) + ); + MUXCY_L plm_fsm_pa_counter0_reg_tx_count_cry_4_ ( + .CI(plm_fsm_pa_counter0_reg_tx_count_cry[3]), + .DI(plm_fsm_pa_counter0_VCC_913), + .LO(plm_fsm_pa_counter0_reg_tx_count_cry[4]), + .S(plm_fsm_pa_counter0_reg_tx_count_qxu[4]) + ); + XORCY plm_fsm_pa_counter0_reg_tx_count_s_4_ ( + .CI(plm_fsm_pa_counter0_reg_tx_count_cry[3]), + .LI(plm_fsm_pa_counter0_reg_tx_count_qxu[4]), + .O(plm_fsm_pa_counter0_reg_tx_count_s[4]) + ); + MUXCY_L plm_fsm_pa_counter0_reg_tx_count_cry_5_ ( + .CI(plm_fsm_pa_counter0_reg_tx_count_cry[4]), + .DI(plm_fsm_pa_counter0_VCC_913), + .LO(plm_fsm_pa_counter0_reg_tx_count_cry[5]), + .S(plm_fsm_pa_counter0_reg_tx_count_qxu[5]) + ); + XORCY plm_fsm_pa_counter0_reg_tx_count_s_5_ ( + .CI(plm_fsm_pa_counter0_reg_tx_count_cry[4]), + .LI(plm_fsm_pa_counter0_reg_tx_count_qxu[5]), + .O(plm_fsm_pa_counter0_reg_tx_count_s[5]) + ); + MUXCY_L plm_fsm_pa_counter0_reg_tx_count_cry_6_ ( + .CI(plm_fsm_pa_counter0_reg_tx_count_cry[5]), + .DI(plm_fsm_pa_counter0_VCC_913), + .LO(plm_fsm_pa_counter0_reg_tx_count_cry[6]), + .S(plm_fsm_pa_counter0_reg_tx_count_qxu[6]) + ); + XORCY plm_fsm_pa_counter0_reg_tx_count_s_6_ ( + .CI(plm_fsm_pa_counter0_reg_tx_count_cry[5]), + .LI(plm_fsm_pa_counter0_reg_tx_count_qxu[6]), + .O(plm_fsm_pa_counter0_reg_tx_count_s[6]) + ); + MUXCY_L plm_fsm_pa_counter0_reg_tx_count_cry_7_ ( + .CI(plm_fsm_pa_counter0_reg_tx_count_cry[6]), + .DI(plm_fsm_pa_counter0_VCC_913), + .LO(plm_fsm_pa_counter0_reg_tx_count_cry[7]), + .S(plm_fsm_pa_counter0_reg_tx_count_qxu[7]) + ); + XORCY plm_fsm_pa_counter0_reg_tx_count_s_7_ ( + .CI(plm_fsm_pa_counter0_reg_tx_count_cry[6]), + .LI(plm_fsm_pa_counter0_reg_tx_count_qxu[7]), + .O(plm_fsm_pa_counter0_reg_tx_count_s[7]) + ); + MUXCY_L plm_fsm_pa_counter0_reg_tx_count_cry_8_ ( + .CI(plm_fsm_pa_counter0_reg_tx_count_cry[7]), + .DI(plm_fsm_pa_counter0_VCC_913), + .LO(plm_fsm_pa_counter0_reg_tx_count_cry[8]), + .S(plm_fsm_pa_counter0_reg_tx_count_qxu[8]) + ); + XORCY plm_fsm_pa_counter0_reg_tx_count_s_8_ ( + .CI(plm_fsm_pa_counter0_reg_tx_count_cry[7]), + .LI(plm_fsm_pa_counter0_reg_tx_count_qxu[8]), + .O(plm_fsm_pa_counter0_reg_tx_count_s[8]) + ); + MUXCY_L plm_fsm_pa_counter0_reg_tx_count_cry_9_ ( + .CI(plm_fsm_pa_counter0_reg_tx_count_cry[8]), + .DI(plm_fsm_pa_counter0_VCC_913), + .LO(plm_fsm_pa_counter0_reg_tx_count_cry[9]), + .S(plm_fsm_pa_counter0_reg_tx_count_qxu[9]) + ); + XORCY plm_fsm_pa_counter0_reg_tx_count_s_9_ ( + .CI(plm_fsm_pa_counter0_reg_tx_count_cry[8]), + .LI(plm_fsm_pa_counter0_reg_tx_count_qxu[9]), + .O(plm_fsm_pa_counter0_reg_tx_count_s[9]) + ); + MUXCY_L plm_fsm_pa_counter0_reg_tx_count_cry_10_ ( + .CI(plm_fsm_pa_counter0_reg_tx_count_cry[9]), + .DI(plm_fsm_pa_counter0_VCC_913), + .LO(plm_fsm_pa_counter0_reg_tx_count_cry[10]), + .S(plm_fsm_pa_counter0_reg_tx_count_qxu[10]) + ); + XORCY plm_fsm_pa_counter0_reg_tx_count_s_10_ ( + .CI(plm_fsm_pa_counter0_reg_tx_count_cry[9]), + .LI(plm_fsm_pa_counter0_reg_tx_count_qxu[10]), + .O(plm_fsm_pa_counter0_reg_tx_count_s[10]) + ); + XORCY plm_fsm_pa_counter0_reg_tx_count_s_11_ ( + .CI(plm_fsm_pa_counter0_reg_tx_count_cry[10]), + .LI(plm_fsm_pa_counter0_reg_tx_count_qxu[11]), + .O(plm_fsm_pa_counter0_reg_tx_count_s[11]) + ); + defparam plm_fsm_pa_counter0_un1_enable_2_0_0_o3.INIT = 4'h1; + LUT2 plm_fsm_pa_counter0_un1_enable_2_0_0_o3 ( + .I0(plm_rx0_ts1_c), + .I1(plm_rx0_ts2_c), + .O(N_38174_i) + ); + defparam plm_fsm_pa_counter0_un1_enable_1_0_a2_0_a4.INIT = 4'h4; + LUT2 plm_fsm_pa_counter0_un1_enable_1_0_a2_0_a4 ( + .I0(plm_fsm_pa_counter0_reg_tx_expired_916), + .I1(plm_fsm_reg_state_1__903), + .O(plm_fsm_pa_counter0_un1_enable_1) + ); + defparam plm_fsm_pa_counter0_un1_enable_2_0_0_a4_0.INIT = 4'h8; + LUT2 plm_fsm_pa_counter0_un1_enable_2_0_0_a4_0 ( + .I0(plm_fsm_pa_counter0_reg_rx_expired_43), + .I1(plm_fsm_reg_state_1__903), + .O(plm_fsm_pa_counter0_N_38421) + ); + defparam plm_fsm_pa_counter0_un1_enable_2_0_0_a4_1.INIT = 4'h8; + LUT2 plm_fsm_pa_counter0_un1_enable_2_0_0_a4_1 ( + .I0(plm_fsm_N_38095_i), + .I1(plm_fsm_reg_state_1__903), + .O(plm_fsm_pa_counter0_N_38422) + ); + defparam plm_fsm_pa_counter0_loadable_rx_counter_un1_reg_rx_count_0_a4_4.INIT = 16'h0001; + LUT4 plm_fsm_pa_counter0_loadable_rx_counter_un1_reg_rx_count_0_a4_4 ( + .I0(plm_fsm_pa_counter0_reg_rx_count[0]), + .I1(plm_fsm_pa_counter0_reg_rx_count[1]), + .I2(plm_fsm_pa_counter0_reg_rx_count[2]), + .I3(plm_fsm_pa_counter0_reg_rx_count[3]), + .O(plm_fsm_pa_counter0_un1_reg_rx_count_0_a4_4) + ); + defparam plm_fsm_pa_counter0_loadable_rx_counter_un1_reg_rx_count_0_a4_5.INIT = 16'h0001; + LUT4 plm_fsm_pa_counter0_loadable_rx_counter_un1_reg_rx_count_0_a4_5 ( + .I0(plm_fsm_pa_counter0_reg_rx_count[4]), + .I1(plm_fsm_pa_counter0_reg_rx_count[5]), + .I2(plm_fsm_pa_counter0_reg_rx_count[6]), + .I3(plm_fsm_pa_counter0_reg_rx_count[7]), + .O(plm_fsm_pa_counter0_un1_reg_rx_count_0_a4_5) + ); + defparam plm_fsm_pa_counter0_loadable_tx_counter_un1_reg_tx_count_0_a4_6.INIT = 16'h0001; + LUT4 plm_fsm_pa_counter0_loadable_tx_counter_un1_reg_tx_count_0_a4_6 ( + .I0(plm_fsm_pa_counter0_reg_tx_count[0]), + .I1(plm_fsm_pa_counter0_reg_tx_count[1]), + .I2(plm_fsm_pa_counter0_reg_tx_count[2]), + .I3(plm_fsm_pa_counter0_reg_tx_count[3]), + .O(plm_fsm_pa_counter0_un1_reg_tx_count_0_a4_6) + ); + defparam plm_fsm_pa_counter0_loadable_tx_counter_un1_reg_tx_count_0_a4_7.INIT = 16'h0001; + LUT4 plm_fsm_pa_counter0_loadable_tx_counter_un1_reg_tx_count_0_a4_7 ( + .I0(plm_fsm_pa_counter0_reg_tx_count[4]), + .I1(plm_fsm_pa_counter0_reg_tx_count[5]), + .I2(plm_fsm_pa_counter0_reg_tx_count[6]), + .I3(plm_fsm_pa_counter0_reg_tx_count[7]), + .O(plm_fsm_pa_counter0_un1_reg_tx_count_0_a4_7) + ); + defparam plm_fsm_pa_counter0_loadable_tx_counter_un1_reg_tx_count_0_a4_8.INIT = 16'h0001; + LUT4 plm_fsm_pa_counter0_loadable_tx_counter_un1_reg_tx_count_0_a4_8 ( + .I0(plm_fsm_pa_counter0_reg_tx_count[8]), + .I1(plm_fsm_pa_counter0_reg_tx_count[9]), + .I2(plm_fsm_pa_counter0_reg_tx_count[10]), + .I3(plm_fsm_pa_counter0_reg_tx_count[11]), + .O(plm_fsm_pa_counter0_un1_reg_tx_count_0_a4_8) + ); + defparam plm_fsm_pa_counter0_N_38532_i.INIT = 4'hB; + LUT2 plm_fsm_pa_counter0_N_38532_i ( + .I0(plm_reg_sym_sent_5_), + .I1(plm_fsm_pa_counter0_un1_enable_1), + .O(plm_fsm_pa_counter0_N_38532_i_915) + ); + defparam plm_fsm_pa_counter0_un1_enable_2_0_0_a4.INIT = 8'h40; + LUT3 plm_fsm_pa_counter0_un1_enable_2_0_0_a4 ( + .I0(N_38174_i), + .I1(N_38190_i), + .I2(plm_fsm_reg_state_1__903), + .O(N_38420) + ); + defparam plm_fsm_pa_counter0_loadable_rx_counter_un1_reg_rx_expired_1_i.INIT = 4'hD; + LUT2 plm_fsm_pa_counter0_loadable_rx_counter_un1_reg_rx_expired_1_i ( + .I0(plm_fsm_pa_counter0_N_38422), + .I1(plm_fsm_pa_counter0_reg_rx_expired_43), + .O(plm_fsm_pa_counter0_un1_reg_rx_expired_1_i) + ); + defparam plm_fsm_pa_counter0_un1_enable_2_0_0.INIT = 8'h01; + LUT3 plm_fsm_pa_counter0_un1_enable_2_0_0 ( + .I0(N_38420), + .I1(plm_fsm_pa_counter0_N_38421), + .I2(plm_fsm_pa_counter0_N_38422), + .O(plm_fsm_pa_counter0_N_9959_i) + ); + defparam plm_fsm_pa_counter0_loadable_rx_counter_N_38548_i.INIT = 8'h8F; + LUT3 plm_fsm_pa_counter0_loadable_rx_counter_N_38548_i ( + .I0(plm_fsm_pa_counter0_un1_reg_rx_count_0_a4_4), + .I1(plm_fsm_pa_counter0_un1_reg_rx_count_0_a4_5), + .I2(plm_fsm_reg_state_1__903), + .O(plm_fsm_pa_counter0_N_38548_i) + ); + defparam plm_fsm_pa_counter0_loadable_tx_counter_N_38549_i.INIT = 16'h80FF; + LUT4 plm_fsm_pa_counter0_loadable_tx_counter_N_38549_i ( + .I0(plm_fsm_pa_counter0_un1_reg_tx_count_0_a4_6), + .I1(plm_fsm_pa_counter0_un1_reg_tx_count_0_a4_7), + .I2(plm_fsm_pa_counter0_un1_reg_tx_count_0_a4_8), + .I3(plm_fsm_reg_state_1__903), + .O(plm_fsm_pa_counter0_N_38549_i) + ); + defparam plm_fsm_pa_counter0_flagit_reg_expired_5_0_a2_0_a4.INIT = 4'h8; + LUT2_L plm_fsm_pa_counter0_flagit_reg_expired_5_0_a2_0_a4 ( + .I0(plm_fsm_pa_counter0_N_38421), + .I1(plm_fsm_pa_counter0_reg_tx_expired_916), + .LO(plm_fsm_pa_counter0_reg_expired_5) + ); + defparam plm_fsm_pa_counter0_un1_enable_1_i.INIT = 4'hD; + LUT2 plm_fsm_pa_counter0_un1_enable_1_i ( + .I0(plm_fsm_reg_state_1__903), + .I1(plm_fsm_pa_counter0_reg_tx_expired_916), + .O(plm_fsm_pa_counter0_un1_enable_1_i_914) + ); + FDCE plm_fsm_pa_counter0_reg_tx_count_11_ ( + .CE(plm_fsm_pa_counter0_N_38532_i_915), + .C(mgt_clk), + .D(plm_fsm_pa_counter0_reg_tx_count_s[11]), + .Q(plm_fsm_pa_counter0_reg_tx_count[11]), + .CLR(plm_rst) + ); + FDCE plm_fsm_pa_counter0_reg_tx_count_10_ ( + .CE(plm_fsm_pa_counter0_N_38532_i_915), + .C(mgt_clk), + .D(plm_fsm_pa_counter0_reg_tx_count_s[10]), + .Q(plm_fsm_pa_counter0_reg_tx_count[10]), + .CLR(plm_rst) + ); + FDCE plm_fsm_pa_counter0_reg_tx_count_9_ ( + .CE(plm_fsm_pa_counter0_N_38532_i_915), + .C(mgt_clk), + .D(plm_fsm_pa_counter0_reg_tx_count_s[9]), + .Q(plm_fsm_pa_counter0_reg_tx_count[9]), + .CLR(plm_rst) + ); + FDCE plm_fsm_pa_counter0_reg_tx_count_8_ ( + .CE(plm_fsm_pa_counter0_N_38532_i_915), + .C(mgt_clk), + .D(plm_fsm_pa_counter0_reg_tx_count_s[8]), + .Q(plm_fsm_pa_counter0_reg_tx_count[8]), + .CLR(plm_rst) + ); + FDCE plm_fsm_pa_counter0_reg_tx_count_7_ ( + .CE(plm_fsm_pa_counter0_N_38532_i_915), + .C(mgt_clk), + .D(plm_fsm_pa_counter0_reg_tx_count_s[7]), + .Q(plm_fsm_pa_counter0_reg_tx_count[7]), + .CLR(plm_rst) + ); + FDCE plm_fsm_pa_counter0_reg_tx_count_6_ ( + .CE(plm_fsm_pa_counter0_N_38532_i_915), + .C(mgt_clk), + .D(plm_fsm_pa_counter0_reg_tx_count_s[6]), + .Q(plm_fsm_pa_counter0_reg_tx_count[6]), + .CLR(plm_rst) + ); + FDCE plm_fsm_pa_counter0_reg_tx_count_5_ ( + .CE(plm_fsm_pa_counter0_N_38532_i_915), + .C(mgt_clk), + .D(plm_fsm_pa_counter0_reg_tx_count_s[5]), + .Q(plm_fsm_pa_counter0_reg_tx_count[5]), + .CLR(plm_rst) + ); + FDCE plm_fsm_pa_counter0_reg_tx_count_4_ ( + .CE(plm_fsm_pa_counter0_N_38532_i_915), + .C(mgt_clk), + .D(plm_fsm_pa_counter0_reg_tx_count_s[4]), + .Q(plm_fsm_pa_counter0_reg_tx_count[4]), + .CLR(plm_rst) + ); + FDCE plm_fsm_pa_counter0_reg_tx_count_3_ ( + .CE(plm_fsm_pa_counter0_N_38532_i_915), + .C(mgt_clk), + .D(plm_fsm_pa_counter0_reg_tx_count_s[3]), + .Q(plm_fsm_pa_counter0_reg_tx_count[3]), + .CLR(plm_rst) + ); + FDCE plm_fsm_pa_counter0_reg_tx_count_2_ ( + .CE(plm_fsm_pa_counter0_N_38532_i_915), + .C(mgt_clk), + .D(plm_fsm_pa_counter0_reg_tx_count_s[2]), + .Q(plm_fsm_pa_counter0_reg_tx_count[2]), + .CLR(plm_rst) + ); + FDCE plm_fsm_pa_counter0_reg_tx_count_1_ ( + .CE(plm_fsm_pa_counter0_N_38532_i_915), + .C(mgt_clk), + .D(plm_fsm_pa_counter0_reg_tx_count_s[1]), + .Q(plm_fsm_pa_counter0_reg_tx_count[1]), + .CLR(plm_rst) + ); + FDCE plm_fsm_pa_counter0_reg_tx_count_0_ ( + .CE(plm_fsm_pa_counter0_N_38532_i_915), + .C(mgt_clk), + .D(plm_fsm_pa_counter0_reg_tx_count_s[0]), + .Q(plm_fsm_pa_counter0_reg_tx_count[0]), + .CLR(plm_rst) + ); + FDCE plm_fsm_pa_counter0_reg_rx_count_7_ ( + .CE(plm_fsm_pa_counter0_un1_reg_rx_expired_1_i), + .C(mgt_clk), + .D(plm_fsm_pa_counter0_reg_rx_count_s[7]), + .Q(plm_fsm_pa_counter0_reg_rx_count[7]), + .CLR(plm_rst) + ); + FDCE plm_fsm_pa_counter0_reg_rx_count_6_ ( + .CE(plm_fsm_pa_counter0_un1_reg_rx_expired_1_i), + .C(mgt_clk), + .D(plm_fsm_pa_counter0_reg_rx_count_s[6]), + .Q(plm_fsm_pa_counter0_reg_rx_count[6]), + .CLR(plm_rst) + ); + FDCE plm_fsm_pa_counter0_reg_rx_count_5_ ( + .CE(plm_fsm_pa_counter0_un1_reg_rx_expired_1_i), + .C(mgt_clk), + .D(plm_fsm_pa_counter0_reg_rx_count_s[5]), + .Q(plm_fsm_pa_counter0_reg_rx_count[5]), + .CLR(plm_rst) + ); + FDCE plm_fsm_pa_counter0_reg_rx_count_4_ ( + .CE(plm_fsm_pa_counter0_un1_reg_rx_expired_1_i), + .C(mgt_clk), + .D(plm_fsm_pa_counter0_reg_rx_count_s[4]), + .Q(plm_fsm_pa_counter0_reg_rx_count[4]), + .CLR(plm_rst) + ); + FDCE plm_fsm_pa_counter0_reg_rx_count_3_ ( + .CE(plm_fsm_pa_counter0_un1_reg_rx_expired_1_i), + .C(mgt_clk), + .D(plm_fsm_pa_counter0_reg_rx_count_s[3]), + .Q(plm_fsm_pa_counter0_reg_rx_count[3]), + .CLR(plm_rst) + ); + FDCE plm_fsm_pa_counter0_reg_rx_count_2_ ( + .CE(plm_fsm_pa_counter0_un1_reg_rx_expired_1_i), + .C(mgt_clk), + .D(plm_fsm_pa_counter0_reg_rx_count_s[2]), + .Q(plm_fsm_pa_counter0_reg_rx_count[2]), + .CLR(plm_rst) + ); + FDCE plm_fsm_pa_counter0_reg_rx_count_1_ ( + .CE(plm_fsm_pa_counter0_un1_reg_rx_expired_1_i), + .C(mgt_clk), + .D(plm_fsm_pa_counter0_reg_rx_count_s[1]), + .Q(plm_fsm_pa_counter0_reg_rx_count[1]), + .CLR(plm_rst) + ); + FDCE plm_fsm_pa_counter0_reg_rx_count_0_ ( + .CE(plm_fsm_pa_counter0_un1_reg_rx_expired_1_i), + .C(mgt_clk), + .D(plm_fsm_pa_counter0_reg_rx_count_s[0]), + .Q(plm_fsm_pa_counter0_reg_rx_count[0]), + .CLR(plm_rst) + ); + FDC plm_fsm_pa_counter0_reg_expired ( + .C(mgt_clk), + .D(plm_fsm_pa_counter0_reg_expired_5), + .Q(plm_fsm_pa_cntrout0), + .CLR(plm_rst) + ); + FDCE plm_fsm_pa_counter0_reg_tx_expired ( + .CE(plm_fsm_pa_counter0_N_38549_i), + .C(mgt_clk), + .D(plm_fsm_reg_state_1__903), + .Q(plm_fsm_pa_counter0_reg_tx_expired_916), + .CLR(plm_rst) + ); + FDCE plm_fsm_pa_counter0_reg_rx_expired ( + .CE(plm_fsm_pa_counter0_N_38548_i), + .C(mgt_clk), + .D(plm_fsm_reg_state_1__903), + .Q(plm_fsm_pa_counter0_reg_rx_expired_43), + .CLR(plm_rst) + ); + defparam plm_fsm_pa_counter0_reg_rx_count_qxu_0_0_.INIT = 4'h7; + LUT2_L plm_fsm_pa_counter0_reg_rx_count_qxu_0_0_ ( + .I0(N_18705_i), + .I1(plm_fsm_pa_counter0_reg_rx_count[0]), + .LO(plm_fsm_pa_counter0_reg_rx_count_qxu[0]) + ); + defparam plm_fsm_pa_counter0_reg_rx_count_qxu_0_1_.INIT = 4'h7; + LUT2_L plm_fsm_pa_counter0_reg_rx_count_qxu_0_1_ ( + .I0(N_18705_i), + .I1(plm_fsm_pa_counter0_reg_rx_count[1]), + .LO(plm_fsm_pa_counter0_reg_rx_count_qxu[1]) + ); + defparam plm_fsm_pa_counter0_reg_rx_count_qxu_0_2_.INIT = 4'h7; + LUT2_L plm_fsm_pa_counter0_reg_rx_count_qxu_0_2_ ( + .I0(N_18705_i), + .I1(plm_fsm_pa_counter0_reg_rx_count[2]), + .LO(plm_fsm_pa_counter0_reg_rx_count_qxu[2]) + ); + defparam plm_fsm_pa_counter0_reg_rx_count_qxu_0_3_.INIT = 8'h1D; + LUT3_L plm_fsm_pa_counter0_reg_rx_count_qxu_0_3_ ( + .I0(plm_fsm_pa_counter0_N_9959_i), + .I1(N_18705_i), + .I2(plm_fsm_pa_counter0_reg_rx_count[3]), + .LO(plm_fsm_pa_counter0_reg_rx_count_qxu[3]) + ); + defparam plm_fsm_pa_counter0_reg_rx_count_qxu_0_4_.INIT = 4'h7; + LUT2_L plm_fsm_pa_counter0_reg_rx_count_qxu_0_4_ ( + .I0(N_18705_i), + .I1(plm_fsm_pa_counter0_reg_rx_count[4]), + .LO(plm_fsm_pa_counter0_reg_rx_count_qxu[4]) + ); + defparam plm_fsm_pa_counter0_reg_rx_count_qxu_0_5_.INIT = 4'h7; + LUT2_L plm_fsm_pa_counter0_reg_rx_count_qxu_0_5_ ( + .I0(N_18705_i), + .I1(plm_fsm_pa_counter0_reg_rx_count[5]), + .LO(plm_fsm_pa_counter0_reg_rx_count_qxu[5]) + ); + defparam plm_fsm_pa_counter0_reg_rx_count_qxu_0_6_.INIT = 4'h7; + LUT2_L plm_fsm_pa_counter0_reg_rx_count_qxu_0_6_ ( + .I0(N_18705_i), + .I1(plm_fsm_pa_counter0_reg_rx_count[6]), + .LO(plm_fsm_pa_counter0_reg_rx_count_qxu[6]) + ); + defparam plm_fsm_pa_counter0_reg_rx_count_qxu_0_7_.INIT = 4'h7; + LUT2_L plm_fsm_pa_counter0_reg_rx_count_qxu_0_7_ ( + .I0(N_18705_i), + .I1(plm_fsm_pa_counter0_reg_rx_count[7]), + .LO(plm_fsm_pa_counter0_reg_rx_count_qxu[7]) + ); + defparam plm_fsm_pa_counter0_reg_tx_count_qxu_0_0_.INIT = 4'h7; + LUT2_L plm_fsm_pa_counter0_reg_tx_count_qxu_0_0_ ( + .I0(plm_fsm_pa_counter0_reg_tx_count[0]), + .I1(plm_fsm_pa_counter0_un1_enable_1), + .LO(plm_fsm_pa_counter0_reg_tx_count_qxu[0]) + ); + defparam plm_fsm_pa_counter0_reg_tx_count_qxu_0_1_.INIT = 4'h7; + LUT2_L plm_fsm_pa_counter0_reg_tx_count_qxu_0_1_ ( + .I0(plm_fsm_pa_counter0_reg_tx_count[1]), + .I1(plm_fsm_pa_counter0_un1_enable_1), + .LO(plm_fsm_pa_counter0_reg_tx_count_qxu[1]) + ); + defparam plm_fsm_pa_counter0_reg_tx_count_qxu_0_2_.INIT = 4'h7; + LUT2_L plm_fsm_pa_counter0_reg_tx_count_qxu_0_2_ ( + .I0(plm_fsm_pa_counter0_reg_tx_count[2]), + .I1(plm_fsm_pa_counter0_un1_enable_1), + .LO(plm_fsm_pa_counter0_reg_tx_count_qxu[2]) + ); + defparam plm_fsm_pa_counter0_reg_tx_count_qxu_0_3_.INIT = 4'h7; + LUT2_L plm_fsm_pa_counter0_reg_tx_count_qxu_0_3_ ( + .I0(plm_fsm_pa_counter0_reg_tx_count[3]), + .I1(plm_fsm_pa_counter0_un1_enable_1), + .LO(plm_fsm_pa_counter0_reg_tx_count_qxu[3]) + ); + defparam plm_fsm_pa_counter0_reg_tx_count_qxu_0_4_.INIT = 8'h35; + LUT3_L plm_fsm_pa_counter0_reg_tx_count_qxu_0_4_ ( + .I0(plm_fsm_reg_tx_count_6_4_), + .I1(plm_fsm_pa_counter0_reg_tx_count[4]), + .I2(plm_fsm_pa_counter0_un1_enable_1), + .LO(plm_fsm_pa_counter0_reg_tx_count_qxu[4]) + ); + defparam plm_fsm_pa_counter0_reg_tx_count_qxu_0_5_.INIT = 4'h7; + LUT2_L plm_fsm_pa_counter0_reg_tx_count_qxu_0_5_ ( + .I0(plm_fsm_pa_counter0_reg_tx_count[5]), + .I1(plm_fsm_pa_counter0_un1_enable_1), + .LO(plm_fsm_pa_counter0_reg_tx_count_qxu[5]) + ); + defparam plm_fsm_pa_counter0_reg_tx_count_qxu_0_6_.INIT = 4'h7; + LUT2_L plm_fsm_pa_counter0_reg_tx_count_qxu_0_6_ ( + .I0(plm_fsm_pa_counter0_reg_tx_count[6]), + .I1(plm_fsm_pa_counter0_un1_enable_1), + .LO(plm_fsm_pa_counter0_reg_tx_count_qxu[6]) + ); + defparam plm_fsm_pa_counter0_reg_tx_count_qxu_0_7_.INIT = 4'h7; + LUT2_L plm_fsm_pa_counter0_reg_tx_count_qxu_0_7_ ( + .I0(plm_fsm_pa_counter0_reg_tx_count[7]), + .I1(plm_fsm_pa_counter0_un1_enable_1), + .LO(plm_fsm_pa_counter0_reg_tx_count_qxu[7]) + ); + defparam plm_fsm_pa_counter0_reg_tx_count_qxu_0_8_.INIT = 4'h7; + LUT2_L plm_fsm_pa_counter0_reg_tx_count_qxu_0_8_ ( + .I0(plm_fsm_pa_counter0_reg_tx_count[8]), + .I1(plm_fsm_pa_counter0_un1_enable_1), + .LO(plm_fsm_pa_counter0_reg_tx_count_qxu[8]) + ); + defparam plm_fsm_pa_counter0_reg_tx_count_qxu_0_9_.INIT = 4'h7; + LUT2_L plm_fsm_pa_counter0_reg_tx_count_qxu_0_9_ ( + .I0(plm_fsm_pa_counter0_reg_tx_count[9]), + .I1(plm_fsm_pa_counter0_un1_enable_1), + .LO(plm_fsm_pa_counter0_reg_tx_count_qxu[9]) + ); + defparam plm_fsm_pa_counter0_reg_tx_count_qxu_0_10_.INIT = 8'h35; + LUT3_L plm_fsm_pa_counter0_reg_tx_count_qxu_0_10_ ( + .I0(plm_fsm_reg_tx_count_6_10_), + .I1(plm_fsm_pa_counter0_reg_tx_count[10]), + .I2(plm_fsm_pa_counter0_un1_enable_1), + .LO(plm_fsm_pa_counter0_reg_tx_count_qxu[10]) + ); + defparam plm_fsm_pa_counter0_reg_tx_count_qxu_0_11_.INIT = 4'h7; + LUT2_L plm_fsm_pa_counter0_reg_tx_count_qxu_0_11_ ( + .I0(plm_fsm_pa_counter0_reg_tx_count[11]), + .I1(plm_fsm_pa_counter0_un1_enable_1), + .LO(plm_fsm_pa_counter0_reg_tx_count_qxu[11]) + ); + VCC plm_fsm_pa_counter1_VCC ( + .P(plm_fsm_pa_counter1_VCC_917) + ); + MUXCY_L plm_fsm_pa_counter1_reg_tx_count_cry_0_ ( + .CI(plm_fsm_pa_counter1_un1_enable_1_i_918), + .DI(plm_fsm_pa_counter1_VCC_917), + .LO(plm_fsm_pa_counter1_reg_tx_count_cry[0]), + .S(plm_fsm_pa_counter1_reg_tx_count_qxu[0]) + ); + XORCY plm_fsm_pa_counter1_reg_tx_count_s_0_ ( + .CI(plm_fsm_pa_counter1_un1_enable_1_i_918), + .LI(plm_fsm_pa_counter1_reg_tx_count_qxu[0]), + .O(plm_fsm_pa_counter1_reg_tx_count_s[0]) + ); + MUXCY_L plm_fsm_pa_counter1_reg_tx_count_cry_1_ ( + .CI(plm_fsm_pa_counter1_reg_tx_count_cry[0]), + .DI(plm_fsm_pa_counter1_VCC_917), + .LO(plm_fsm_pa_counter1_reg_tx_count_cry[1]), + .S(plm_fsm_pa_counter1_reg_tx_count_qxu[1]) + ); + XORCY plm_fsm_pa_counter1_reg_tx_count_s_1_ ( + .CI(plm_fsm_pa_counter1_reg_tx_count_cry[0]), + .LI(plm_fsm_pa_counter1_reg_tx_count_qxu[1]), + .O(plm_fsm_pa_counter1_reg_tx_count_s[1]) + ); + MUXCY_L plm_fsm_pa_counter1_reg_tx_count_cry_2_ ( + .CI(plm_fsm_pa_counter1_reg_tx_count_cry[1]), + .DI(plm_fsm_pa_counter1_VCC_917), + .LO(plm_fsm_pa_counter1_reg_tx_count_cry[2]), + .S(plm_fsm_pa_counter1_reg_tx_count_qxu[2]) + ); + XORCY plm_fsm_pa_counter1_reg_tx_count_s_2_ ( + .CI(plm_fsm_pa_counter1_reg_tx_count_cry[1]), + .LI(plm_fsm_pa_counter1_reg_tx_count_qxu[2]), + .O(plm_fsm_pa_counter1_reg_tx_count_s[2]) + ); + MUXCY_L plm_fsm_pa_counter1_reg_tx_count_cry_3_ ( + .CI(plm_fsm_pa_counter1_reg_tx_count_cry[2]), + .DI(plm_fsm_pa_counter1_VCC_917), + .LO(plm_fsm_pa_counter1_reg_tx_count_cry[3]), + .S(plm_fsm_pa_counter1_reg_tx_count_qxu[3]) + ); + XORCY plm_fsm_pa_counter1_reg_tx_count_s_3_ ( + .CI(plm_fsm_pa_counter1_reg_tx_count_cry[2]), + .LI(plm_fsm_pa_counter1_reg_tx_count_qxu[3]), + .O(plm_fsm_pa_counter1_reg_tx_count_s[3]) + ); + MUXCY_L plm_fsm_pa_counter1_reg_tx_count_cry_4_ ( + .CI(plm_fsm_pa_counter1_reg_tx_count_cry[3]), + .DI(plm_fsm_pa_counter1_VCC_917), + .LO(plm_fsm_pa_counter1_reg_tx_count_cry[4]), + .S(plm_fsm_pa_counter1_reg_tx_count_qxu[4]) + ); + XORCY plm_fsm_pa_counter1_reg_tx_count_s_4_ ( + .CI(plm_fsm_pa_counter1_reg_tx_count_cry[3]), + .LI(plm_fsm_pa_counter1_reg_tx_count_qxu[4]), + .O(plm_fsm_pa_counter1_reg_tx_count_s[4]) + ); + MUXCY_L plm_fsm_pa_counter1_reg_tx_count_cry_5_ ( + .CI(plm_fsm_pa_counter1_reg_tx_count_cry[4]), + .DI(plm_fsm_pa_counter1_VCC_917), + .LO(plm_fsm_pa_counter1_reg_tx_count_cry[5]), + .S(plm_fsm_pa_counter1_reg_tx_count_qxu[5]) + ); + XORCY plm_fsm_pa_counter1_reg_tx_count_s_5_ ( + .CI(plm_fsm_pa_counter1_reg_tx_count_cry[4]), + .LI(plm_fsm_pa_counter1_reg_tx_count_qxu[5]), + .O(plm_fsm_pa_counter1_reg_tx_count_s[5]) + ); + MUXCY_L plm_fsm_pa_counter1_reg_tx_count_cry_6_ ( + .CI(plm_fsm_pa_counter1_reg_tx_count_cry[5]), + .DI(plm_fsm_pa_counter1_VCC_917), + .LO(plm_fsm_pa_counter1_reg_tx_count_cry[6]), + .S(plm_fsm_pa_counter1_reg_tx_count_qxu[6]) + ); + XORCY plm_fsm_pa_counter1_reg_tx_count_s_6_ ( + .CI(plm_fsm_pa_counter1_reg_tx_count_cry[5]), + .LI(plm_fsm_pa_counter1_reg_tx_count_qxu[6]), + .O(plm_fsm_pa_counter1_reg_tx_count_s[6]) + ); + MUXCY_L plm_fsm_pa_counter1_reg_tx_count_cry_7_ ( + .CI(plm_fsm_pa_counter1_reg_tx_count_cry[6]), + .DI(plm_fsm_pa_counter1_VCC_917), + .LO(plm_fsm_pa_counter1_reg_tx_count_cry[7]), + .S(plm_fsm_pa_counter1_reg_tx_count_qxu[7]) + ); + XORCY plm_fsm_pa_counter1_reg_tx_count_s_7_ ( + .CI(plm_fsm_pa_counter1_reg_tx_count_cry[6]), + .LI(plm_fsm_pa_counter1_reg_tx_count_qxu[7]), + .O(plm_fsm_pa_counter1_reg_tx_count_s[7]) + ); + MUXCY_L plm_fsm_pa_counter1_reg_tx_count_cry_8_ ( + .CI(plm_fsm_pa_counter1_reg_tx_count_cry[7]), + .DI(plm_fsm_pa_counter1_VCC_917), + .LO(plm_fsm_pa_counter1_reg_tx_count_cry[8]), + .S(plm_fsm_pa_counter1_reg_tx_count_qxu[8]) + ); + XORCY plm_fsm_pa_counter1_reg_tx_count_s_8_ ( + .CI(plm_fsm_pa_counter1_reg_tx_count_cry[7]), + .LI(plm_fsm_pa_counter1_reg_tx_count_qxu[8]), + .O(plm_fsm_pa_counter1_reg_tx_count_s[8]) + ); + MUXCY_L plm_fsm_pa_counter1_reg_tx_count_cry_9_ ( + .CI(plm_fsm_pa_counter1_reg_tx_count_cry[8]), + .DI(plm_fsm_pa_counter1_VCC_917), + .LO(plm_fsm_pa_counter1_reg_tx_count_cry[9]), + .S(plm_fsm_pa_counter1_reg_tx_count_qxu[9]) + ); + XORCY plm_fsm_pa_counter1_reg_tx_count_s_9_ ( + .CI(plm_fsm_pa_counter1_reg_tx_count_cry[8]), + .LI(plm_fsm_pa_counter1_reg_tx_count_qxu[9]), + .O(plm_fsm_pa_counter1_reg_tx_count_s[9]) + ); + MUXCY_L plm_fsm_pa_counter1_reg_tx_count_cry_10_ ( + .CI(plm_fsm_pa_counter1_reg_tx_count_cry[9]), + .DI(plm_fsm_pa_counter1_VCC_917), + .LO(plm_fsm_pa_counter1_reg_tx_count_cry[10]), + .S(plm_fsm_pa_counter1_reg_tx_count_qxu[10]) + ); + XORCY plm_fsm_pa_counter1_reg_tx_count_s_10_ ( + .CI(plm_fsm_pa_counter1_reg_tx_count_cry[9]), + .LI(plm_fsm_pa_counter1_reg_tx_count_qxu[10]), + .O(plm_fsm_pa_counter1_reg_tx_count_s[10]) + ); + XORCY plm_fsm_pa_counter1_reg_tx_count_s_11_ ( + .CI(plm_fsm_pa_counter1_reg_tx_count_cry[10]), + .LI(plm_fsm_pa_counter1_reg_tx_count_qxu[11]), + .O(plm_fsm_pa_counter1_reg_tx_count_s[11]) + ); + defparam plm_fsm_pa_counter1_un1_enable_1_0_a2_0_a4.INIT = 4'h4; + LUT2 plm_fsm_pa_counter1_un1_enable_1_0_a2_0_a4 ( + .I0(plm_fsm_pa_counter1_reg_tx_expired_920), + .I1(plm_fsm_reg_state_1__903), + .O(plm_fsm_pa_counter1_un1_enable_1) + ); + defparam plm_fsm_pa_counter1_loadable_rx_counter_N_38545_i.INIT = 4'h7; + LUT2 plm_fsm_pa_counter1_loadable_rx_counter_N_38545_i ( + .I0(plm_fsm_pa_counter1_reg_rx_count[3]), + .I1(plm_fsm_reg_state_1__903), + .O(plm_fsm_pa_counter1_N_38545_i) + ); + defparam plm_fsm_pa_counter1_loadable_rx_counter_N_38547_i.INIT = 4'hB; + LUT2 plm_fsm_pa_counter1_loadable_rx_counter_N_38547_i ( + .I0(plm_fsm_pa_counter1_reg_rx_expired_921), + .I1(plm_fsm_reg_state_1__903), + .O(plm_fsm_pa_counter1_N_38547_i) + ); + defparam plm_fsm_pa_counter1_loadable_tx_counter_un1_reg_tx_count_0_a4_6.INIT = 16'h0001; + LUT4 plm_fsm_pa_counter1_loadable_tx_counter_un1_reg_tx_count_0_a4_6 ( + .I0(plm_fsm_pa_counter1_reg_tx_count[0]), + .I1(plm_fsm_pa_counter1_reg_tx_count[1]), + .I2(plm_fsm_pa_counter1_reg_tx_count[2]), + .I3(plm_fsm_pa_counter1_reg_tx_count[3]), + .O(plm_fsm_pa_counter1_un1_reg_tx_count_0_a4_6) + ); + defparam plm_fsm_pa_counter1_loadable_tx_counter_un1_reg_tx_count_0_a4_7.INIT = 16'h0001; + LUT4 plm_fsm_pa_counter1_loadable_tx_counter_un1_reg_tx_count_0_a4_7 ( + .I0(plm_fsm_pa_counter1_reg_tx_count[4]), + .I1(plm_fsm_pa_counter1_reg_tx_count[5]), + .I2(plm_fsm_pa_counter1_reg_tx_count[6]), + .I3(plm_fsm_pa_counter1_reg_tx_count[7]), + .O(plm_fsm_pa_counter1_un1_reg_tx_count_0_a4_7) + ); + defparam plm_fsm_pa_counter1_loadable_tx_counter_un1_reg_tx_count_0_a4_8.INIT = 16'h0001; + LUT4 plm_fsm_pa_counter1_loadable_tx_counter_un1_reg_tx_count_0_a4_8 ( + .I0(plm_fsm_pa_counter1_reg_tx_count[8]), + .I1(plm_fsm_pa_counter1_reg_tx_count[9]), + .I2(plm_fsm_pa_counter1_reg_tx_count[10]), + .I3(plm_fsm_pa_counter1_reg_tx_count[11]), + .O(plm_fsm_pa_counter1_un1_reg_tx_count_0_a4_8) + ); + defparam plm_fsm_pa_counter1_N_38533_i.INIT = 4'hB; + LUT2 plm_fsm_pa_counter1_N_38533_i ( + .I0(plm_reg_sym_sent_5_), + .I1(plm_fsm_pa_counter1_un1_enable_1), + .O(plm_fsm_pa_counter1_N_38533_i_919) + ); + defparam plm_fsm_pa_counter1_loadable_tx_counter_N_38546_i.INIT = 16'h80FF; + LUT4 plm_fsm_pa_counter1_loadable_tx_counter_N_38546_i ( + .I0(plm_fsm_pa_counter1_un1_reg_tx_count_0_a4_6), + .I1(plm_fsm_pa_counter1_un1_reg_tx_count_0_a4_7), + .I2(plm_fsm_pa_counter1_un1_reg_tx_count_0_a4_8), + .I3(plm_fsm_reg_state_1__903), + .O(plm_fsm_pa_counter1_N_38546_i) + ); + defparam plm_fsm_pa_counter1_flagit_reg_expired_5_0_a2_0_a4.INIT = 8'h80; + LUT3_L plm_fsm_pa_counter1_flagit_reg_expired_5_0_a2_0_a4 ( + .I0(plm_fsm_pa_counter1_reg_rx_expired_921), + .I1(plm_fsm_pa_counter1_reg_tx_expired_920), + .I2(plm_fsm_reg_state_1__903), + .LO(plm_fsm_pa_counter1_reg_expired_5) + ); + defparam plm_fsm_pa_counter1_un1_enable_1_i.INIT = 4'hD; + LUT2 plm_fsm_pa_counter1_un1_enable_1_i ( + .I0(plm_fsm_reg_state_1__903), + .I1(plm_fsm_pa_counter1_reg_tx_expired_920), + .O(plm_fsm_pa_counter1_un1_enable_1_i_918) + ); + FDCE plm_fsm_pa_counter1_reg_tx_count_11_ ( + .CE(plm_fsm_pa_counter1_N_38533_i_919), + .C(mgt_clk), + .D(plm_fsm_pa_counter1_reg_tx_count_s[11]), + .Q(plm_fsm_pa_counter1_reg_tx_count[11]), + .CLR(plm_rst) + ); + FDCE plm_fsm_pa_counter1_reg_tx_count_10_ ( + .CE(plm_fsm_pa_counter1_N_38533_i_919), + .C(mgt_clk), + .D(plm_fsm_pa_counter1_reg_tx_count_s[10]), + .Q(plm_fsm_pa_counter1_reg_tx_count[10]), + .CLR(plm_rst) + ); + FDCE plm_fsm_pa_counter1_reg_tx_count_9_ ( + .CE(plm_fsm_pa_counter1_N_38533_i_919), + .C(mgt_clk), + .D(plm_fsm_pa_counter1_reg_tx_count_s[9]), + .Q(plm_fsm_pa_counter1_reg_tx_count[9]), + .CLR(plm_rst) + ); + FDCE plm_fsm_pa_counter1_reg_tx_count_8_ ( + .CE(plm_fsm_pa_counter1_N_38533_i_919), + .C(mgt_clk), + .D(plm_fsm_pa_counter1_reg_tx_count_s[8]), + .Q(plm_fsm_pa_counter1_reg_tx_count[8]), + .CLR(plm_rst) + ); + FDCE plm_fsm_pa_counter1_reg_tx_count_7_ ( + .CE(plm_fsm_pa_counter1_N_38533_i_919), + .C(mgt_clk), + .D(plm_fsm_pa_counter1_reg_tx_count_s[7]), + .Q(plm_fsm_pa_counter1_reg_tx_count[7]), + .CLR(plm_rst) + ); + FDCE plm_fsm_pa_counter1_reg_tx_count_6_ ( + .CE(plm_fsm_pa_counter1_N_38533_i_919), + .C(mgt_clk), + .D(plm_fsm_pa_counter1_reg_tx_count_s[6]), + .Q(plm_fsm_pa_counter1_reg_tx_count[6]), + .CLR(plm_rst) + ); + FDCE plm_fsm_pa_counter1_reg_tx_count_5_ ( + .CE(plm_fsm_pa_counter1_N_38533_i_919), + .C(mgt_clk), + .D(plm_fsm_pa_counter1_reg_tx_count_s[5]), + .Q(plm_fsm_pa_counter1_reg_tx_count[5]), + .CLR(plm_rst) + ); + FDCE plm_fsm_pa_counter1_reg_tx_count_4_ ( + .CE(plm_fsm_pa_counter1_N_38533_i_919), + .C(mgt_clk), + .D(plm_fsm_pa_counter1_reg_tx_count_s[4]), + .Q(plm_fsm_pa_counter1_reg_tx_count[4]), + .CLR(plm_rst) + ); + FDCE plm_fsm_pa_counter1_reg_tx_count_3_ ( + .CE(plm_fsm_pa_counter1_N_38533_i_919), + .C(mgt_clk), + .D(plm_fsm_pa_counter1_reg_tx_count_s[3]), + .Q(plm_fsm_pa_counter1_reg_tx_count[3]), + .CLR(plm_rst) + ); + FDCE plm_fsm_pa_counter1_reg_tx_count_2_ ( + .CE(plm_fsm_pa_counter1_N_38533_i_919), + .C(mgt_clk), + .D(plm_fsm_pa_counter1_reg_tx_count_s[2]), + .Q(plm_fsm_pa_counter1_reg_tx_count[2]), + .CLR(plm_rst) + ); + FDCE plm_fsm_pa_counter1_reg_tx_count_1_ ( + .CE(plm_fsm_pa_counter1_N_38533_i_919), + .C(mgt_clk), + .D(plm_fsm_pa_counter1_reg_tx_count_s[1]), + .Q(plm_fsm_pa_counter1_reg_tx_count[1]), + .CLR(plm_rst) + ); + FDCE plm_fsm_pa_counter1_reg_tx_count_0_ ( + .CE(plm_fsm_pa_counter1_N_38533_i_919), + .C(mgt_clk), + .D(plm_fsm_pa_counter1_reg_tx_count_s[0]), + .Q(plm_fsm_pa_counter1_reg_tx_count[0]), + .CLR(plm_rst) + ); + FDC plm_fsm_pa_counter1_reg_expired ( + .C(mgt_clk), + .D(plm_fsm_pa_counter1_reg_expired_5), + .Q(plm_fsm_pa_cntrout1), + .CLR(plm_rst) + ); + FDCE plm_fsm_pa_counter1_reg_rx_count_3_ ( + .CE(plm_fsm_pa_counter1_N_38547_i), + .C(mgt_clk), + .D(plm_fsm_reg_state_i_1__902), + .Q(plm_fsm_pa_counter1_reg_rx_count[3]), + .CLR(plm_rst) + ); + FDCE plm_fsm_pa_counter1_reg_tx_expired ( + .CE(plm_fsm_pa_counter1_N_38546_i), + .C(mgt_clk), + .D(plm_fsm_reg_state_1__903), + .Q(plm_fsm_pa_counter1_reg_tx_expired_920), + .CLR(plm_rst) + ); + FDCE plm_fsm_pa_counter1_reg_rx_expired ( + .CE(plm_fsm_pa_counter1_N_38545_i), + .C(mgt_clk), + .D(plm_fsm_reg_state_1__903), + .Q(plm_fsm_pa_counter1_reg_rx_expired_921), + .CLR(plm_rst) + ); + defparam plm_fsm_pa_counter1_reg_tx_count_qxu_0_0_.INIT = 4'h7; + LUT2_L plm_fsm_pa_counter1_reg_tx_count_qxu_0_0_ ( + .I0(plm_fsm_pa_counter1_reg_tx_count[0]), + .I1(plm_fsm_pa_counter1_un1_enable_1), + .LO(plm_fsm_pa_counter1_reg_tx_count_qxu[0]) + ); + defparam plm_fsm_pa_counter1_reg_tx_count_qxu_0_1_.INIT = 4'h7; + LUT2_L plm_fsm_pa_counter1_reg_tx_count_qxu_0_1_ ( + .I0(plm_fsm_pa_counter1_reg_tx_count[1]), + .I1(plm_fsm_pa_counter1_un1_enable_1), + .LO(plm_fsm_pa_counter1_reg_tx_count_qxu[1]) + ); + defparam plm_fsm_pa_counter1_reg_tx_count_qxu_0_2_.INIT = 4'h7; + LUT2_L plm_fsm_pa_counter1_reg_tx_count_qxu_0_2_ ( + .I0(plm_fsm_pa_counter1_reg_tx_count[2]), + .I1(plm_fsm_pa_counter1_un1_enable_1), + .LO(plm_fsm_pa_counter1_reg_tx_count_qxu[2]) + ); + defparam plm_fsm_pa_counter1_reg_tx_count_qxu_0_3_.INIT = 4'h7; + LUT2_L plm_fsm_pa_counter1_reg_tx_count_qxu_0_3_ ( + .I0(plm_fsm_pa_counter1_reg_tx_count[3]), + .I1(plm_fsm_pa_counter1_un1_enable_1), + .LO(plm_fsm_pa_counter1_reg_tx_count_qxu[3]) + ); + defparam plm_fsm_pa_counter1_reg_tx_count_qxu_0_4_.INIT = 8'h35; + LUT3_L plm_fsm_pa_counter1_reg_tx_count_qxu_0_4_ ( + .I0(plm_fsm_reg_tx_count_6_4_), + .I1(plm_fsm_pa_counter1_reg_tx_count[4]), + .I2(plm_fsm_pa_counter1_un1_enable_1), + .LO(plm_fsm_pa_counter1_reg_tx_count_qxu[4]) + ); + defparam plm_fsm_pa_counter1_reg_tx_count_qxu_0_5_.INIT = 4'h7; + LUT2_L plm_fsm_pa_counter1_reg_tx_count_qxu_0_5_ ( + .I0(plm_fsm_pa_counter1_reg_tx_count[5]), + .I1(plm_fsm_pa_counter1_un1_enable_1), + .LO(plm_fsm_pa_counter1_reg_tx_count_qxu[5]) + ); + defparam plm_fsm_pa_counter1_reg_tx_count_qxu_0_6_.INIT = 4'h7; + LUT2_L plm_fsm_pa_counter1_reg_tx_count_qxu_0_6_ ( + .I0(plm_fsm_pa_counter1_reg_tx_count[6]), + .I1(plm_fsm_pa_counter1_un1_enable_1), + .LO(plm_fsm_pa_counter1_reg_tx_count_qxu[6]) + ); + defparam plm_fsm_pa_counter1_reg_tx_count_qxu_0_7_.INIT = 4'h7; + LUT2_L plm_fsm_pa_counter1_reg_tx_count_qxu_0_7_ ( + .I0(plm_fsm_pa_counter1_reg_tx_count[7]), + .I1(plm_fsm_pa_counter1_un1_enable_1), + .LO(plm_fsm_pa_counter1_reg_tx_count_qxu[7]) + ); + defparam plm_fsm_pa_counter1_reg_tx_count_qxu_0_8_.INIT = 4'h7; + LUT2_L plm_fsm_pa_counter1_reg_tx_count_qxu_0_8_ ( + .I0(plm_fsm_pa_counter1_reg_tx_count[8]), + .I1(plm_fsm_pa_counter1_un1_enable_1), + .LO(plm_fsm_pa_counter1_reg_tx_count_qxu[8]) + ); + defparam plm_fsm_pa_counter1_reg_tx_count_qxu_0_9_.INIT = 4'h7; + LUT2_L plm_fsm_pa_counter1_reg_tx_count_qxu_0_9_ ( + .I0(plm_fsm_pa_counter1_reg_tx_count[9]), + .I1(plm_fsm_pa_counter1_un1_enable_1), + .LO(plm_fsm_pa_counter1_reg_tx_count_qxu[9]) + ); + defparam plm_fsm_pa_counter1_reg_tx_count_qxu_0_10_.INIT = 8'h35; + LUT3_L plm_fsm_pa_counter1_reg_tx_count_qxu_0_10_ ( + .I0(plm_fsm_reg_tx_count_6_10_), + .I1(plm_fsm_pa_counter1_reg_tx_count[10]), + .I2(plm_fsm_pa_counter1_un1_enable_1), + .LO(plm_fsm_pa_counter1_reg_tx_count_qxu[10]) + ); + defparam plm_fsm_pa_counter1_reg_tx_count_qxu_0_11_.INIT = 4'h7; + LUT2_L plm_fsm_pa_counter1_reg_tx_count_qxu_0_11_ ( + .I0(plm_fsm_pa_counter1_reg_tx_count[11]), + .I1(plm_fsm_pa_counter1_un1_enable_1), + .LO(plm_fsm_pa_counter1_reg_tx_count_qxu[11]) + ); + VCC plm_fsm_pa_counter2_VCC ( + .P(plm_fsm_pa_counter2_VCC_922) + ); + MUXCY_L plm_fsm_pa_counter2_reg_tx_count_cry_0_ ( + .CI(plm_fsm_pa_counter2_un1_enable_1_i_923), + .DI(plm_fsm_pa_counter2_VCC_922), + .LO(plm_fsm_pa_counter2_reg_tx_count_cry[0]), + .S(plm_fsm_pa_counter2_reg_tx_count_qxu[0]) + ); + XORCY plm_fsm_pa_counter2_reg_tx_count_s_0_ ( + .CI(plm_fsm_pa_counter2_un1_enable_1_i_923), + .LI(plm_fsm_pa_counter2_reg_tx_count_qxu[0]), + .O(plm_fsm_pa_counter2_reg_tx_count_s[0]) + ); + MUXCY_L plm_fsm_pa_counter2_reg_tx_count_cry_1_ ( + .CI(plm_fsm_pa_counter2_reg_tx_count_cry[0]), + .DI(plm_fsm_pa_counter2_VCC_922), + .LO(plm_fsm_pa_counter2_reg_tx_count_cry[1]), + .S(plm_fsm_pa_counter2_reg_tx_count_qxu[1]) + ); + XORCY plm_fsm_pa_counter2_reg_tx_count_s_1_ ( + .CI(plm_fsm_pa_counter2_reg_tx_count_cry[0]), + .LI(plm_fsm_pa_counter2_reg_tx_count_qxu[1]), + .O(plm_fsm_pa_counter2_reg_tx_count_s[1]) + ); + MUXCY_L plm_fsm_pa_counter2_reg_tx_count_cry_2_ ( + .CI(plm_fsm_pa_counter2_reg_tx_count_cry[1]), + .DI(plm_fsm_pa_counter2_VCC_922), + .LO(plm_fsm_pa_counter2_reg_tx_count_cry[2]), + .S(plm_fsm_pa_counter2_reg_tx_count_qxu[2]) + ); + XORCY plm_fsm_pa_counter2_reg_tx_count_s_2_ ( + .CI(plm_fsm_pa_counter2_reg_tx_count_cry[1]), + .LI(plm_fsm_pa_counter2_reg_tx_count_qxu[2]), + .O(plm_fsm_pa_counter2_reg_tx_count_s[2]) + ); + MUXCY_L plm_fsm_pa_counter2_reg_tx_count_cry_3_ ( + .CI(plm_fsm_pa_counter2_reg_tx_count_cry[2]), + .DI(plm_fsm_pa_counter2_VCC_922), + .LO(plm_fsm_pa_counter2_reg_tx_count_cry[3]), + .S(plm_fsm_pa_counter2_reg_tx_count_qxu[3]) + ); + XORCY plm_fsm_pa_counter2_reg_tx_count_s_3_ ( + .CI(plm_fsm_pa_counter2_reg_tx_count_cry[2]), + .LI(plm_fsm_pa_counter2_reg_tx_count_qxu[3]), + .O(plm_fsm_pa_counter2_reg_tx_count_s[3]) + ); + MUXCY_L plm_fsm_pa_counter2_reg_tx_count_cry_4_ ( + .CI(plm_fsm_pa_counter2_reg_tx_count_cry[3]), + .DI(plm_fsm_pa_counter2_VCC_922), + .LO(plm_fsm_pa_counter2_reg_tx_count_cry[4]), + .S(plm_fsm_pa_counter2_reg_tx_count_qxu[4]) + ); + XORCY plm_fsm_pa_counter2_reg_tx_count_s_4_ ( + .CI(plm_fsm_pa_counter2_reg_tx_count_cry[3]), + .LI(plm_fsm_pa_counter2_reg_tx_count_qxu[4]), + .O(plm_fsm_pa_counter2_reg_tx_count_s[4]) + ); + MUXCY_L plm_fsm_pa_counter2_reg_tx_count_cry_5_ ( + .CI(plm_fsm_pa_counter2_reg_tx_count_cry[4]), + .DI(plm_fsm_pa_counter2_VCC_922), + .LO(plm_fsm_pa_counter2_reg_tx_count_cry[5]), + .S(plm_fsm_pa_counter2_reg_tx_count_qxu[5]) + ); + XORCY plm_fsm_pa_counter2_reg_tx_count_s_5_ ( + .CI(plm_fsm_pa_counter2_reg_tx_count_cry[4]), + .LI(plm_fsm_pa_counter2_reg_tx_count_qxu[5]), + .O(plm_fsm_pa_counter2_reg_tx_count_s[5]) + ); + MUXCY_L plm_fsm_pa_counter2_reg_tx_count_cry_6_ ( + .CI(plm_fsm_pa_counter2_reg_tx_count_cry[5]), + .DI(plm_fsm_pa_counter2_VCC_922), + .LO(plm_fsm_pa_counter2_reg_tx_count_cry[6]), + .S(plm_fsm_pa_counter2_reg_tx_count_qxu[6]) + ); + XORCY plm_fsm_pa_counter2_reg_tx_count_s_6_ ( + .CI(plm_fsm_pa_counter2_reg_tx_count_cry[5]), + .LI(plm_fsm_pa_counter2_reg_tx_count_qxu[6]), + .O(plm_fsm_pa_counter2_reg_tx_count_s[6]) + ); + MUXCY_L plm_fsm_pa_counter2_reg_tx_count_cry_7_ ( + .CI(plm_fsm_pa_counter2_reg_tx_count_cry[6]), + .DI(plm_fsm_pa_counter2_VCC_922), + .LO(plm_fsm_pa_counter2_reg_tx_count_cry[7]), + .S(plm_fsm_pa_counter2_reg_tx_count_qxu[7]) + ); + XORCY plm_fsm_pa_counter2_reg_tx_count_s_7_ ( + .CI(plm_fsm_pa_counter2_reg_tx_count_cry[6]), + .LI(plm_fsm_pa_counter2_reg_tx_count_qxu[7]), + .O(plm_fsm_pa_counter2_reg_tx_count_s[7]) + ); + MUXCY_L plm_fsm_pa_counter2_reg_tx_count_cry_8_ ( + .CI(plm_fsm_pa_counter2_reg_tx_count_cry[7]), + .DI(plm_fsm_pa_counter2_VCC_922), + .LO(plm_fsm_pa_counter2_reg_tx_count_cry[8]), + .S(plm_fsm_pa_counter2_reg_tx_count_qxu[8]) + ); + XORCY plm_fsm_pa_counter2_reg_tx_count_s_8_ ( + .CI(plm_fsm_pa_counter2_reg_tx_count_cry[7]), + .LI(plm_fsm_pa_counter2_reg_tx_count_qxu[8]), + .O(plm_fsm_pa_counter2_reg_tx_count_s[8]) + ); + MUXCY_L plm_fsm_pa_counter2_reg_tx_count_cry_9_ ( + .CI(plm_fsm_pa_counter2_reg_tx_count_cry[8]), + .DI(plm_fsm_pa_counter2_VCC_922), + .LO(plm_fsm_pa_counter2_reg_tx_count_cry[9]), + .S(plm_fsm_pa_counter2_reg_tx_count_qxu[9]) + ); + XORCY plm_fsm_pa_counter2_reg_tx_count_s_9_ ( + .CI(plm_fsm_pa_counter2_reg_tx_count_cry[8]), + .LI(plm_fsm_pa_counter2_reg_tx_count_qxu[9]), + .O(plm_fsm_pa_counter2_reg_tx_count_s[9]) + ); + MUXCY_L plm_fsm_pa_counter2_reg_tx_count_cry_10_ ( + .CI(plm_fsm_pa_counter2_reg_tx_count_cry[9]), + .DI(plm_fsm_pa_counter2_VCC_922), + .LO(plm_fsm_pa_counter2_reg_tx_count_cry[10]), + .S(plm_fsm_pa_counter2_reg_tx_count_qxu[10]) + ); + XORCY plm_fsm_pa_counter2_reg_tx_count_s_10_ ( + .CI(plm_fsm_pa_counter2_reg_tx_count_cry[9]), + .LI(plm_fsm_pa_counter2_reg_tx_count_qxu[10]), + .O(plm_fsm_pa_counter2_reg_tx_count_s[10]) + ); + XORCY plm_fsm_pa_counter2_reg_tx_count_s_11_ ( + .CI(plm_fsm_pa_counter2_reg_tx_count_cry[10]), + .LI(plm_fsm_pa_counter2_reg_tx_count_qxu[11]), + .O(plm_fsm_pa_counter2_reg_tx_count_s[11]) + ); + defparam plm_fsm_pa_counter2_un1_enable_1_0_a2_0_a4.INIT = 4'h4; + LUT2 plm_fsm_pa_counter2_un1_enable_1_0_a2_0_a4 ( + .I0(plm_fsm_pa_counter2_reg_tx_expired_925), + .I1(plm_fsm_reg_state_1__903), + .O(plm_fsm_pa_counter2_un1_enable_1) + ); + defparam plm_fsm_pa_counter2_loadable_rx_counter_N_38542_i.INIT = 4'h7; + LUT2 plm_fsm_pa_counter2_loadable_rx_counter_N_38542_i ( + .I0(plm_fsm_pa_counter2_reg_rx_count[3]), + .I1(plm_fsm_reg_state_1__903), + .O(plm_fsm_pa_counter2_N_38542_i) + ); + defparam plm_fsm_pa_counter2_loadable_rx_counter_N_38544_i.INIT = 4'hB; + LUT2 plm_fsm_pa_counter2_loadable_rx_counter_N_38544_i ( + .I0(plm_fsm_pa_counter2_reg_rx_expired_926), + .I1(plm_fsm_reg_state_1__903), + .O(plm_fsm_pa_counter2_N_38544_i) + ); + defparam plm_fsm_pa_counter2_loadable_tx_counter_un1_reg_tx_count_0_a4_6.INIT = 16'h0001; + LUT4 plm_fsm_pa_counter2_loadable_tx_counter_un1_reg_tx_count_0_a4_6 ( + .I0(plm_fsm_pa_counter2_reg_tx_count[0]), + .I1(plm_fsm_pa_counter2_reg_tx_count[1]), + .I2(plm_fsm_pa_counter2_reg_tx_count[2]), + .I3(plm_fsm_pa_counter2_reg_tx_count[3]), + .O(plm_fsm_pa_counter2_un1_reg_tx_count_0_a4_6) + ); + defparam plm_fsm_pa_counter2_loadable_tx_counter_un1_reg_tx_count_0_a4_7.INIT = 16'h0001; + LUT4 plm_fsm_pa_counter2_loadable_tx_counter_un1_reg_tx_count_0_a4_7 ( + .I0(plm_fsm_pa_counter2_reg_tx_count[4]), + .I1(plm_fsm_pa_counter2_reg_tx_count[5]), + .I2(plm_fsm_pa_counter2_reg_tx_count[6]), + .I3(plm_fsm_pa_counter2_reg_tx_count[7]), + .O(plm_fsm_pa_counter2_un1_reg_tx_count_0_a4_7) + ); + defparam plm_fsm_pa_counter2_loadable_tx_counter_un1_reg_tx_count_0_a4_8.INIT = 16'h0001; + LUT4 plm_fsm_pa_counter2_loadable_tx_counter_un1_reg_tx_count_0_a4_8 ( + .I0(plm_fsm_pa_counter2_reg_tx_count[8]), + .I1(plm_fsm_pa_counter2_reg_tx_count[9]), + .I2(plm_fsm_pa_counter2_reg_tx_count[10]), + .I3(plm_fsm_pa_counter2_reg_tx_count[11]), + .O(plm_fsm_pa_counter2_un1_reg_tx_count_0_a4_8) + ); + defparam plm_fsm_pa_counter2_N_38534_i.INIT = 4'hB; + LUT2 plm_fsm_pa_counter2_N_38534_i ( + .I0(plm_reg_sym_sent_5_), + .I1(plm_fsm_pa_counter2_un1_enable_1), + .O(plm_fsm_pa_counter2_N_38534_i_924) + ); + defparam plm_fsm_pa_counter2_loadable_tx_counter_N_38543_i.INIT = 16'h80FF; + LUT4 plm_fsm_pa_counter2_loadable_tx_counter_N_38543_i ( + .I0(plm_fsm_pa_counter2_un1_reg_tx_count_0_a4_6), + .I1(plm_fsm_pa_counter2_un1_reg_tx_count_0_a4_7), + .I2(plm_fsm_pa_counter2_un1_reg_tx_count_0_a4_8), + .I3(plm_fsm_reg_state_1__903), + .O(plm_fsm_pa_counter2_N_38543_i) + ); + defparam plm_fsm_pa_counter2_flagit_reg_expired_5_0_a2_0_a4.INIT = 8'h80; + LUT3_L plm_fsm_pa_counter2_flagit_reg_expired_5_0_a2_0_a4 ( + .I0(plm_fsm_pa_counter2_reg_rx_expired_926), + .I1(plm_fsm_pa_counter2_reg_tx_expired_925), + .I2(plm_fsm_reg_state_1__903), + .LO(plm_fsm_pa_counter2_reg_expired_5) + ); + defparam plm_fsm_pa_counter2_un1_enable_1_i.INIT = 4'hD; + LUT2 plm_fsm_pa_counter2_un1_enable_1_i ( + .I0(plm_fsm_reg_state_1__903), + .I1(plm_fsm_pa_counter2_reg_tx_expired_925), + .O(plm_fsm_pa_counter2_un1_enable_1_i_923) + ); + FDCE plm_fsm_pa_counter2_reg_tx_count_11_ ( + .CE(plm_fsm_pa_counter2_N_38534_i_924), + .C(mgt_clk), + .D(plm_fsm_pa_counter2_reg_tx_count_s[11]), + .Q(plm_fsm_pa_counter2_reg_tx_count[11]), + .CLR(plm_rst) + ); + FDCE plm_fsm_pa_counter2_reg_tx_count_10_ ( + .CE(plm_fsm_pa_counter2_N_38534_i_924), + .C(mgt_clk), + .D(plm_fsm_pa_counter2_reg_tx_count_s[10]), + .Q(plm_fsm_pa_counter2_reg_tx_count[10]), + .CLR(plm_rst) + ); + FDCE plm_fsm_pa_counter2_reg_tx_count_9_ ( + .CE(plm_fsm_pa_counter2_N_38534_i_924), + .C(mgt_clk), + .D(plm_fsm_pa_counter2_reg_tx_count_s[9]), + .Q(plm_fsm_pa_counter2_reg_tx_count[9]), + .CLR(plm_rst) + ); + FDCE plm_fsm_pa_counter2_reg_tx_count_8_ ( + .CE(plm_fsm_pa_counter2_N_38534_i_924), + .C(mgt_clk), + .D(plm_fsm_pa_counter2_reg_tx_count_s[8]), + .Q(plm_fsm_pa_counter2_reg_tx_count[8]), + .CLR(plm_rst) + ); + FDCE plm_fsm_pa_counter2_reg_tx_count_7_ ( + .CE(plm_fsm_pa_counter2_N_38534_i_924), + .C(mgt_clk), + .D(plm_fsm_pa_counter2_reg_tx_count_s[7]), + .Q(plm_fsm_pa_counter2_reg_tx_count[7]), + .CLR(plm_rst) + ); + FDCE plm_fsm_pa_counter2_reg_tx_count_6_ ( + .CE(plm_fsm_pa_counter2_N_38534_i_924), + .C(mgt_clk), + .D(plm_fsm_pa_counter2_reg_tx_count_s[6]), + .Q(plm_fsm_pa_counter2_reg_tx_count[6]), + .CLR(plm_rst) + ); + FDCE plm_fsm_pa_counter2_reg_tx_count_5_ ( + .CE(plm_fsm_pa_counter2_N_38534_i_924), + .C(mgt_clk), + .D(plm_fsm_pa_counter2_reg_tx_count_s[5]), + .Q(plm_fsm_pa_counter2_reg_tx_count[5]), + .CLR(plm_rst) + ); + FDCE plm_fsm_pa_counter2_reg_tx_count_4_ ( + .CE(plm_fsm_pa_counter2_N_38534_i_924), + .C(mgt_clk), + .D(plm_fsm_pa_counter2_reg_tx_count_s[4]), + .Q(plm_fsm_pa_counter2_reg_tx_count[4]), + .CLR(plm_rst) + ); + FDCE plm_fsm_pa_counter2_reg_tx_count_3_ ( + .CE(plm_fsm_pa_counter2_N_38534_i_924), + .C(mgt_clk), + .D(plm_fsm_pa_counter2_reg_tx_count_s[3]), + .Q(plm_fsm_pa_counter2_reg_tx_count[3]), + .CLR(plm_rst) + ); + FDCE plm_fsm_pa_counter2_reg_tx_count_2_ ( + .CE(plm_fsm_pa_counter2_N_38534_i_924), + .C(mgt_clk), + .D(plm_fsm_pa_counter2_reg_tx_count_s[2]), + .Q(plm_fsm_pa_counter2_reg_tx_count[2]), + .CLR(plm_rst) + ); + FDCE plm_fsm_pa_counter2_reg_tx_count_1_ ( + .CE(plm_fsm_pa_counter2_N_38534_i_924), + .C(mgt_clk), + .D(plm_fsm_pa_counter2_reg_tx_count_s[1]), + .Q(plm_fsm_pa_counter2_reg_tx_count[1]), + .CLR(plm_rst) + ); + FDCE plm_fsm_pa_counter2_reg_tx_count_0_ ( + .CE(plm_fsm_pa_counter2_N_38534_i_924), + .C(mgt_clk), + .D(plm_fsm_pa_counter2_reg_tx_count_s[0]), + .Q(plm_fsm_pa_counter2_reg_tx_count[0]), + .CLR(plm_rst) + ); + FDC plm_fsm_pa_counter2_reg_expired ( + .C(mgt_clk), + .D(plm_fsm_pa_counter2_reg_expired_5), + .Q(plm_fsm_pa_cntrout2), + .CLR(plm_rst) + ); + FDCE plm_fsm_pa_counter2_reg_rx_count_3_ ( + .CE(plm_fsm_pa_counter2_N_38544_i), + .C(mgt_clk), + .D(plm_fsm_reg_state_i_1__902), + .Q(plm_fsm_pa_counter2_reg_rx_count[3]), + .CLR(plm_rst) + ); + FDCE plm_fsm_pa_counter2_reg_tx_expired ( + .CE(plm_fsm_pa_counter2_N_38543_i), + .C(mgt_clk), + .D(plm_fsm_reg_state_1__903), + .Q(plm_fsm_pa_counter2_reg_tx_expired_925), + .CLR(plm_rst) + ); + FDCE plm_fsm_pa_counter2_reg_rx_expired ( + .CE(plm_fsm_pa_counter2_N_38542_i), + .C(mgt_clk), + .D(plm_fsm_reg_state_1__903), + .Q(plm_fsm_pa_counter2_reg_rx_expired_926), + .CLR(plm_rst) + ); + defparam plm_fsm_pa_counter2_reg_tx_count_qxu_0_0_.INIT = 4'h7; + LUT2_L plm_fsm_pa_counter2_reg_tx_count_qxu_0_0_ ( + .I0(plm_fsm_pa_counter2_reg_tx_count[0]), + .I1(plm_fsm_pa_counter2_un1_enable_1), + .LO(plm_fsm_pa_counter2_reg_tx_count_qxu[0]) + ); + defparam plm_fsm_pa_counter2_reg_tx_count_qxu_0_1_.INIT = 4'h7; + LUT2_L plm_fsm_pa_counter2_reg_tx_count_qxu_0_1_ ( + .I0(plm_fsm_pa_counter2_reg_tx_count[1]), + .I1(plm_fsm_pa_counter2_un1_enable_1), + .LO(plm_fsm_pa_counter2_reg_tx_count_qxu[1]) + ); + defparam plm_fsm_pa_counter2_reg_tx_count_qxu_0_2_.INIT = 4'h7; + LUT2_L plm_fsm_pa_counter2_reg_tx_count_qxu_0_2_ ( + .I0(plm_fsm_pa_counter2_reg_tx_count[2]), + .I1(plm_fsm_pa_counter2_un1_enable_1), + .LO(plm_fsm_pa_counter2_reg_tx_count_qxu[2]) + ); + defparam plm_fsm_pa_counter2_reg_tx_count_qxu_0_3_.INIT = 4'h7; + LUT2_L plm_fsm_pa_counter2_reg_tx_count_qxu_0_3_ ( + .I0(plm_fsm_pa_counter2_reg_tx_count[3]), + .I1(plm_fsm_pa_counter2_un1_enable_1), + .LO(plm_fsm_pa_counter2_reg_tx_count_qxu[3]) + ); + defparam plm_fsm_pa_counter2_reg_tx_count_qxu_0_4_.INIT = 8'h35; + LUT3_L plm_fsm_pa_counter2_reg_tx_count_qxu_0_4_ ( + .I0(plm_fsm_reg_tx_count_6_4_), + .I1(plm_fsm_pa_counter2_reg_tx_count[4]), + .I2(plm_fsm_pa_counter2_un1_enable_1), + .LO(plm_fsm_pa_counter2_reg_tx_count_qxu[4]) + ); + defparam plm_fsm_pa_counter2_reg_tx_count_qxu_0_5_.INIT = 4'h7; + LUT2_L plm_fsm_pa_counter2_reg_tx_count_qxu_0_5_ ( + .I0(plm_fsm_pa_counter2_reg_tx_count[5]), + .I1(plm_fsm_pa_counter2_un1_enable_1), + .LO(plm_fsm_pa_counter2_reg_tx_count_qxu[5]) + ); + defparam plm_fsm_pa_counter2_reg_tx_count_qxu_0_6_.INIT = 4'h7; + LUT2_L plm_fsm_pa_counter2_reg_tx_count_qxu_0_6_ ( + .I0(plm_fsm_pa_counter2_reg_tx_count[6]), + .I1(plm_fsm_pa_counter2_un1_enable_1), + .LO(plm_fsm_pa_counter2_reg_tx_count_qxu[6]) + ); + defparam plm_fsm_pa_counter2_reg_tx_count_qxu_0_7_.INIT = 4'h7; + LUT2_L plm_fsm_pa_counter2_reg_tx_count_qxu_0_7_ ( + .I0(plm_fsm_pa_counter2_reg_tx_count[7]), + .I1(plm_fsm_pa_counter2_un1_enable_1), + .LO(plm_fsm_pa_counter2_reg_tx_count_qxu[7]) + ); + defparam plm_fsm_pa_counter2_reg_tx_count_qxu_0_8_.INIT = 4'h7; + LUT2_L plm_fsm_pa_counter2_reg_tx_count_qxu_0_8_ ( + .I0(plm_fsm_pa_counter2_reg_tx_count[8]), + .I1(plm_fsm_pa_counter2_un1_enable_1), + .LO(plm_fsm_pa_counter2_reg_tx_count_qxu[8]) + ); + defparam plm_fsm_pa_counter2_reg_tx_count_qxu_0_9_.INIT = 4'h7; + LUT2_L plm_fsm_pa_counter2_reg_tx_count_qxu_0_9_ ( + .I0(plm_fsm_pa_counter2_reg_tx_count[9]), + .I1(plm_fsm_pa_counter2_un1_enable_1), + .LO(plm_fsm_pa_counter2_reg_tx_count_qxu[9]) + ); + defparam plm_fsm_pa_counter2_reg_tx_count_qxu_0_10_.INIT = 8'h35; + LUT3_L plm_fsm_pa_counter2_reg_tx_count_qxu_0_10_ ( + .I0(plm_fsm_reg_tx_count_6_10_), + .I1(plm_fsm_pa_counter2_reg_tx_count[10]), + .I2(plm_fsm_pa_counter2_un1_enable_1), + .LO(plm_fsm_pa_counter2_reg_tx_count_qxu[10]) + ); + defparam plm_fsm_pa_counter2_reg_tx_count_qxu_0_11_.INIT = 4'h7; + LUT2_L plm_fsm_pa_counter2_reg_tx_count_qxu_0_11_ ( + .I0(plm_fsm_pa_counter2_reg_tx_count[11]), + .I1(plm_fsm_pa_counter2_un1_enable_1), + .LO(plm_fsm_pa_counter2_reg_tx_count_qxu[11]) + ); + VCC plm_fsm_pa_counter3_VCC ( + .P(plm_fsm_pa_counter3_VCC_927) + ); + MUXCY_L plm_fsm_pa_counter3_reg_tx_count_cry_0_ ( + .CI(plm_fsm_pa_counter3_un1_enable_1_i_928), + .DI(plm_fsm_pa_counter3_VCC_927), + .LO(plm_fsm_pa_counter3_reg_tx_count_cry[0]), + .S(plm_fsm_pa_counter3_reg_tx_count_qxu[0]) + ); + XORCY plm_fsm_pa_counter3_reg_tx_count_s_0_ ( + .CI(plm_fsm_pa_counter3_un1_enable_1_i_928), + .LI(plm_fsm_pa_counter3_reg_tx_count_qxu[0]), + .O(plm_fsm_pa_counter3_reg_tx_count_s[0]) + ); + MUXCY_L plm_fsm_pa_counter3_reg_tx_count_cry_1_ ( + .CI(plm_fsm_pa_counter3_reg_tx_count_cry[0]), + .DI(plm_fsm_pa_counter3_VCC_927), + .LO(plm_fsm_pa_counter3_reg_tx_count_cry[1]), + .S(plm_fsm_pa_counter3_reg_tx_count_qxu[1]) + ); + XORCY plm_fsm_pa_counter3_reg_tx_count_s_1_ ( + .CI(plm_fsm_pa_counter3_reg_tx_count_cry[0]), + .LI(plm_fsm_pa_counter3_reg_tx_count_qxu[1]), + .O(plm_fsm_pa_counter3_reg_tx_count_s[1]) + ); + MUXCY_L plm_fsm_pa_counter3_reg_tx_count_cry_2_ ( + .CI(plm_fsm_pa_counter3_reg_tx_count_cry[1]), + .DI(plm_fsm_pa_counter3_VCC_927), + .LO(plm_fsm_pa_counter3_reg_tx_count_cry[2]), + .S(plm_fsm_pa_counter3_reg_tx_count_qxu[2]) + ); + XORCY plm_fsm_pa_counter3_reg_tx_count_s_2_ ( + .CI(plm_fsm_pa_counter3_reg_tx_count_cry[1]), + .LI(plm_fsm_pa_counter3_reg_tx_count_qxu[2]), + .O(plm_fsm_pa_counter3_reg_tx_count_s[2]) + ); + MUXCY_L plm_fsm_pa_counter3_reg_tx_count_cry_3_ ( + .CI(plm_fsm_pa_counter3_reg_tx_count_cry[2]), + .DI(plm_fsm_pa_counter3_VCC_927), + .LO(plm_fsm_pa_counter3_reg_tx_count_cry[3]), + .S(plm_fsm_pa_counter3_reg_tx_count_qxu[3]) + ); + XORCY plm_fsm_pa_counter3_reg_tx_count_s_3_ ( + .CI(plm_fsm_pa_counter3_reg_tx_count_cry[2]), + .LI(plm_fsm_pa_counter3_reg_tx_count_qxu[3]), + .O(plm_fsm_pa_counter3_reg_tx_count_s[3]) + ); + MUXCY_L plm_fsm_pa_counter3_reg_tx_count_cry_4_ ( + .CI(plm_fsm_pa_counter3_reg_tx_count_cry[3]), + .DI(plm_fsm_pa_counter3_VCC_927), + .LO(plm_fsm_pa_counter3_reg_tx_count_cry[4]), + .S(plm_fsm_pa_counter3_reg_tx_count_qxu[4]) + ); + XORCY plm_fsm_pa_counter3_reg_tx_count_s_4_ ( + .CI(plm_fsm_pa_counter3_reg_tx_count_cry[3]), + .LI(plm_fsm_pa_counter3_reg_tx_count_qxu[4]), + .O(plm_fsm_pa_counter3_reg_tx_count_s[4]) + ); + MUXCY_L plm_fsm_pa_counter3_reg_tx_count_cry_5_ ( + .CI(plm_fsm_pa_counter3_reg_tx_count_cry[4]), + .DI(plm_fsm_pa_counter3_VCC_927), + .LO(plm_fsm_pa_counter3_reg_tx_count_cry[5]), + .S(plm_fsm_pa_counter3_reg_tx_count_qxu[5]) + ); + XORCY plm_fsm_pa_counter3_reg_tx_count_s_5_ ( + .CI(plm_fsm_pa_counter3_reg_tx_count_cry[4]), + .LI(plm_fsm_pa_counter3_reg_tx_count_qxu[5]), + .O(plm_fsm_pa_counter3_reg_tx_count_s[5]) + ); + MUXCY_L plm_fsm_pa_counter3_reg_tx_count_cry_6_ ( + .CI(plm_fsm_pa_counter3_reg_tx_count_cry[5]), + .DI(plm_fsm_pa_counter3_VCC_927), + .LO(plm_fsm_pa_counter3_reg_tx_count_cry[6]), + .S(plm_fsm_pa_counter3_reg_tx_count_qxu[6]) + ); + XORCY plm_fsm_pa_counter3_reg_tx_count_s_6_ ( + .CI(plm_fsm_pa_counter3_reg_tx_count_cry[5]), + .LI(plm_fsm_pa_counter3_reg_tx_count_qxu[6]), + .O(plm_fsm_pa_counter3_reg_tx_count_s[6]) + ); + MUXCY_L plm_fsm_pa_counter3_reg_tx_count_cry_7_ ( + .CI(plm_fsm_pa_counter3_reg_tx_count_cry[6]), + .DI(plm_fsm_pa_counter3_VCC_927), + .LO(plm_fsm_pa_counter3_reg_tx_count_cry[7]), + .S(plm_fsm_pa_counter3_reg_tx_count_qxu[7]) + ); + XORCY plm_fsm_pa_counter3_reg_tx_count_s_7_ ( + .CI(plm_fsm_pa_counter3_reg_tx_count_cry[6]), + .LI(plm_fsm_pa_counter3_reg_tx_count_qxu[7]), + .O(plm_fsm_pa_counter3_reg_tx_count_s[7]) + ); + MUXCY_L plm_fsm_pa_counter3_reg_tx_count_cry_8_ ( + .CI(plm_fsm_pa_counter3_reg_tx_count_cry[7]), + .DI(plm_fsm_pa_counter3_VCC_927), + .LO(plm_fsm_pa_counter3_reg_tx_count_cry[8]), + .S(plm_fsm_pa_counter3_reg_tx_count_qxu[8]) + ); + XORCY plm_fsm_pa_counter3_reg_tx_count_s_8_ ( + .CI(plm_fsm_pa_counter3_reg_tx_count_cry[7]), + .LI(plm_fsm_pa_counter3_reg_tx_count_qxu[8]), + .O(plm_fsm_pa_counter3_reg_tx_count_s[8]) + ); + MUXCY_L plm_fsm_pa_counter3_reg_tx_count_cry_9_ ( + .CI(plm_fsm_pa_counter3_reg_tx_count_cry[8]), + .DI(plm_fsm_pa_counter3_VCC_927), + .LO(plm_fsm_pa_counter3_reg_tx_count_cry[9]), + .S(plm_fsm_pa_counter3_reg_tx_count_qxu[9]) + ); + XORCY plm_fsm_pa_counter3_reg_tx_count_s_9_ ( + .CI(plm_fsm_pa_counter3_reg_tx_count_cry[8]), + .LI(plm_fsm_pa_counter3_reg_tx_count_qxu[9]), + .O(plm_fsm_pa_counter3_reg_tx_count_s[9]) + ); + MUXCY_L plm_fsm_pa_counter3_reg_tx_count_cry_10_ ( + .CI(plm_fsm_pa_counter3_reg_tx_count_cry[9]), + .DI(plm_fsm_pa_counter3_VCC_927), + .LO(plm_fsm_pa_counter3_reg_tx_count_cry[10]), + .S(plm_fsm_pa_counter3_reg_tx_count_qxu[10]) + ); + XORCY plm_fsm_pa_counter3_reg_tx_count_s_10_ ( + .CI(plm_fsm_pa_counter3_reg_tx_count_cry[9]), + .LI(plm_fsm_pa_counter3_reg_tx_count_qxu[10]), + .O(plm_fsm_pa_counter3_reg_tx_count_s[10]) + ); + XORCY plm_fsm_pa_counter3_reg_tx_count_s_11_ ( + .CI(plm_fsm_pa_counter3_reg_tx_count_cry[10]), + .LI(plm_fsm_pa_counter3_reg_tx_count_qxu[11]), + .O(plm_fsm_pa_counter3_reg_tx_count_s[11]) + ); + defparam plm_fsm_pa_counter3_loadable_tx_counter_reg_tx_count_6_0_a2_0_a2_0_a4_10_.INIT = 4'h1; + LUT2 plm_fsm_pa_counter3_loadable_tx_counter_reg_tx_count_6_0_a2_0_a2_0_a4_10_ ( + .I0(cfg_cfg_5072[507]), + .I1(plm_fsm_reg_state_1__903), + .O(plm_fsm_reg_tx_count_6_10_) + ); + defparam plm_fsm_pa_counter3_loadable_tx_counter_reg_tx_count_6_0_a2_0_a2_0_a4_4_.INIT = 4'h2; + LUT2 plm_fsm_pa_counter3_loadable_tx_counter_reg_tx_count_6_0_a2_0_a2_0_a4_4_ ( + .I0(cfg_cfg_5072[507]), + .I1(plm_fsm_reg_state_1__903), + .O(plm_fsm_reg_tx_count_6_4_) + ); + defparam plm_fsm_pa_counter3_un1_enable_1_0_a2_0_a4.INIT = 4'h4; + LUT2 plm_fsm_pa_counter3_un1_enable_1_0_a2_0_a4 ( + .I0(plm_fsm_pa_counter3_reg_tx_expired_930), + .I1(plm_fsm_reg_state_1__903), + .O(plm_fsm_pa_counter3_un1_enable_1) + ); + defparam plm_fsm_pa_counter3_loadable_rx_counter_N_38539_i.INIT = 4'h7; + LUT2 plm_fsm_pa_counter3_loadable_rx_counter_N_38539_i ( + .I0(plm_fsm_pa_counter3_reg_rx_count[3]), + .I1(plm_fsm_reg_state_1__903), + .O(plm_fsm_pa_counter3_N_38539_i) + ); + defparam plm_fsm_pa_counter3_loadable_rx_counter_N_38541_i.INIT = 4'hB; + LUT2 plm_fsm_pa_counter3_loadable_rx_counter_N_38541_i ( + .I0(plm_fsm_pa_counter3_reg_rx_expired_931), + .I1(plm_fsm_reg_state_1__903), + .O(plm_fsm_pa_counter3_N_38541_i) + ); + defparam plm_fsm_pa_counter3_loadable_tx_counter_un1_reg_tx_count_0_a4_6.INIT = 16'h0001; + LUT4 plm_fsm_pa_counter3_loadable_tx_counter_un1_reg_tx_count_0_a4_6 ( + .I0(plm_fsm_pa_counter3_reg_tx_count[0]), + .I1(plm_fsm_pa_counter3_reg_tx_count[1]), + .I2(plm_fsm_pa_counter3_reg_tx_count[2]), + .I3(plm_fsm_pa_counter3_reg_tx_count[3]), + .O(plm_fsm_pa_counter3_un1_reg_tx_count_0_a4_6) + ); + defparam plm_fsm_pa_counter3_loadable_tx_counter_un1_reg_tx_count_0_a4_7.INIT = 16'h0001; + LUT4 plm_fsm_pa_counter3_loadable_tx_counter_un1_reg_tx_count_0_a4_7 ( + .I0(plm_fsm_pa_counter3_reg_tx_count[4]), + .I1(plm_fsm_pa_counter3_reg_tx_count[5]), + .I2(plm_fsm_pa_counter3_reg_tx_count[6]), + .I3(plm_fsm_pa_counter3_reg_tx_count[7]), + .O(plm_fsm_pa_counter3_un1_reg_tx_count_0_a4_7) + ); + defparam plm_fsm_pa_counter3_loadable_tx_counter_un1_reg_tx_count_0_a4_8.INIT = 16'h0001; + LUT4 plm_fsm_pa_counter3_loadable_tx_counter_un1_reg_tx_count_0_a4_8 ( + .I0(plm_fsm_pa_counter3_reg_tx_count[8]), + .I1(plm_fsm_pa_counter3_reg_tx_count[9]), + .I2(plm_fsm_pa_counter3_reg_tx_count[10]), + .I3(plm_fsm_pa_counter3_reg_tx_count[11]), + .O(plm_fsm_pa_counter3_un1_reg_tx_count_0_a4_8) + ); + defparam plm_fsm_pa_counter3_N_38535_i.INIT = 4'hB; + LUT2 plm_fsm_pa_counter3_N_38535_i ( + .I0(plm_reg_sym_sent_5_), + .I1(plm_fsm_pa_counter3_un1_enable_1), + .O(plm_fsm_pa_counter3_N_38535_i_929) + ); + defparam plm_fsm_pa_counter3_loadable_tx_counter_N_38540_i.INIT = 16'h80FF; + LUT4 plm_fsm_pa_counter3_loadable_tx_counter_N_38540_i ( + .I0(plm_fsm_pa_counter3_un1_reg_tx_count_0_a4_6), + .I1(plm_fsm_pa_counter3_un1_reg_tx_count_0_a4_7), + .I2(plm_fsm_pa_counter3_un1_reg_tx_count_0_a4_8), + .I3(plm_fsm_reg_state_1__903), + .O(plm_fsm_pa_counter3_N_38540_i) + ); + defparam plm_fsm_pa_counter3_flagit_reg_expired_5_0_a2_0_a4.INIT = 8'h80; + LUT3_L plm_fsm_pa_counter3_flagit_reg_expired_5_0_a2_0_a4 ( + .I0(plm_fsm_pa_counter3_reg_rx_expired_931), + .I1(plm_fsm_pa_counter3_reg_tx_expired_930), + .I2(plm_fsm_reg_state_1__903), + .LO(plm_fsm_pa_counter3_reg_expired_5) + ); + defparam plm_fsm_pa_counter3_un1_enable_1_i.INIT = 4'hD; + LUT2 plm_fsm_pa_counter3_un1_enable_1_i ( + .I0(plm_fsm_reg_state_1__903), + .I1(plm_fsm_pa_counter3_reg_tx_expired_930), + .O(plm_fsm_pa_counter3_un1_enable_1_i_928) + ); + FDCE plm_fsm_pa_counter3_reg_tx_count_11_ ( + .CE(plm_fsm_pa_counter3_N_38535_i_929), + .C(mgt_clk), + .D(plm_fsm_pa_counter3_reg_tx_count_s[11]), + .Q(plm_fsm_pa_counter3_reg_tx_count[11]), + .CLR(plm_rst) + ); + FDCE plm_fsm_pa_counter3_reg_tx_count_10_ ( + .CE(plm_fsm_pa_counter3_N_38535_i_929), + .C(mgt_clk), + .D(plm_fsm_pa_counter3_reg_tx_count_s[10]), + .Q(plm_fsm_pa_counter3_reg_tx_count[10]), + .CLR(plm_rst) + ); + FDCE plm_fsm_pa_counter3_reg_tx_count_9_ ( + .CE(plm_fsm_pa_counter3_N_38535_i_929), + .C(mgt_clk), + .D(plm_fsm_pa_counter3_reg_tx_count_s[9]), + .Q(plm_fsm_pa_counter3_reg_tx_count[9]), + .CLR(plm_rst) + ); + FDCE plm_fsm_pa_counter3_reg_tx_count_8_ ( + .CE(plm_fsm_pa_counter3_N_38535_i_929), + .C(mgt_clk), + .D(plm_fsm_pa_counter3_reg_tx_count_s[8]), + .Q(plm_fsm_pa_counter3_reg_tx_count[8]), + .CLR(plm_rst) + ); + FDCE plm_fsm_pa_counter3_reg_tx_count_7_ ( + .CE(plm_fsm_pa_counter3_N_38535_i_929), + .C(mgt_clk), + .D(plm_fsm_pa_counter3_reg_tx_count_s[7]), + .Q(plm_fsm_pa_counter3_reg_tx_count[7]), + .CLR(plm_rst) + ); + FDCE plm_fsm_pa_counter3_reg_tx_count_6_ ( + .CE(plm_fsm_pa_counter3_N_38535_i_929), + .C(mgt_clk), + .D(plm_fsm_pa_counter3_reg_tx_count_s[6]), + .Q(plm_fsm_pa_counter3_reg_tx_count[6]), + .CLR(plm_rst) + ); + FDCE plm_fsm_pa_counter3_reg_tx_count_5_ ( + .CE(plm_fsm_pa_counter3_N_38535_i_929), + .C(mgt_clk), + .D(plm_fsm_pa_counter3_reg_tx_count_s[5]), + .Q(plm_fsm_pa_counter3_reg_tx_count[5]), + .CLR(plm_rst) + ); + FDCE plm_fsm_pa_counter3_reg_tx_count_4_ ( + .CE(plm_fsm_pa_counter3_N_38535_i_929), + .C(mgt_clk), + .D(plm_fsm_pa_counter3_reg_tx_count_s[4]), + .Q(plm_fsm_pa_counter3_reg_tx_count[4]), + .CLR(plm_rst) + ); + FDCE plm_fsm_pa_counter3_reg_tx_count_3_ ( + .CE(plm_fsm_pa_counter3_N_38535_i_929), + .C(mgt_clk), + .D(plm_fsm_pa_counter3_reg_tx_count_s[3]), + .Q(plm_fsm_pa_counter3_reg_tx_count[3]), + .CLR(plm_rst) + ); + FDCE plm_fsm_pa_counter3_reg_tx_count_2_ ( + .CE(plm_fsm_pa_counter3_N_38535_i_929), + .C(mgt_clk), + .D(plm_fsm_pa_counter3_reg_tx_count_s[2]), + .Q(plm_fsm_pa_counter3_reg_tx_count[2]), + .CLR(plm_rst) + ); + FDCE plm_fsm_pa_counter3_reg_tx_count_1_ ( + .CE(plm_fsm_pa_counter3_N_38535_i_929), + .C(mgt_clk), + .D(plm_fsm_pa_counter3_reg_tx_count_s[1]), + .Q(plm_fsm_pa_counter3_reg_tx_count[1]), + .CLR(plm_rst) + ); + FDCE plm_fsm_pa_counter3_reg_tx_count_0_ ( + .CE(plm_fsm_pa_counter3_N_38535_i_929), + .C(mgt_clk), + .D(plm_fsm_pa_counter3_reg_tx_count_s[0]), + .Q(plm_fsm_pa_counter3_reg_tx_count[0]), + .CLR(plm_rst) + ); + FDC plm_fsm_pa_counter3_reg_expired ( + .C(mgt_clk), + .D(plm_fsm_pa_counter3_reg_expired_5), + .Q(plm_fsm_pa_cntrout3), + .CLR(plm_rst) + ); + FDCE plm_fsm_pa_counter3_reg_rx_count_3_ ( + .CE(plm_fsm_pa_counter3_N_38541_i), + .C(mgt_clk), + .D(plm_fsm_reg_state_i_1__902), + .Q(plm_fsm_pa_counter3_reg_rx_count[3]), + .CLR(plm_rst) + ); + FDCE plm_fsm_pa_counter3_reg_tx_expired ( + .CE(plm_fsm_pa_counter3_N_38540_i), + .C(mgt_clk), + .D(plm_fsm_reg_state_1__903), + .Q(plm_fsm_pa_counter3_reg_tx_expired_930), + .CLR(plm_rst) + ); + FDCE plm_fsm_pa_counter3_reg_rx_expired ( + .CE(plm_fsm_pa_counter3_N_38539_i), + .C(mgt_clk), + .D(plm_fsm_reg_state_1__903), + .Q(plm_fsm_pa_counter3_reg_rx_expired_931), + .CLR(plm_rst) + ); + defparam plm_fsm_pa_counter3_reg_tx_count_qxu_0_0_.INIT = 4'h7; + LUT2_L plm_fsm_pa_counter3_reg_tx_count_qxu_0_0_ ( + .I0(plm_fsm_pa_counter3_reg_tx_count[0]), + .I1(plm_fsm_pa_counter3_un1_enable_1), + .LO(plm_fsm_pa_counter3_reg_tx_count_qxu[0]) + ); + defparam plm_fsm_pa_counter3_reg_tx_count_qxu_0_1_.INIT = 4'h7; + LUT2_L plm_fsm_pa_counter3_reg_tx_count_qxu_0_1_ ( + .I0(plm_fsm_pa_counter3_reg_tx_count[1]), + .I1(plm_fsm_pa_counter3_un1_enable_1), + .LO(plm_fsm_pa_counter3_reg_tx_count_qxu[1]) + ); + defparam plm_fsm_pa_counter3_reg_tx_count_qxu_0_2_.INIT = 4'h7; + LUT2_L plm_fsm_pa_counter3_reg_tx_count_qxu_0_2_ ( + .I0(plm_fsm_pa_counter3_reg_tx_count[2]), + .I1(plm_fsm_pa_counter3_un1_enable_1), + .LO(plm_fsm_pa_counter3_reg_tx_count_qxu[2]) + ); + defparam plm_fsm_pa_counter3_reg_tx_count_qxu_0_3_.INIT = 4'h7; + LUT2_L plm_fsm_pa_counter3_reg_tx_count_qxu_0_3_ ( + .I0(plm_fsm_pa_counter3_reg_tx_count[3]), + .I1(plm_fsm_pa_counter3_un1_enable_1), + .LO(plm_fsm_pa_counter3_reg_tx_count_qxu[3]) + ); + defparam plm_fsm_pa_counter3_reg_tx_count_qxu_0_4_.INIT = 8'h35; + LUT3_L plm_fsm_pa_counter3_reg_tx_count_qxu_0_4_ ( + .I0(plm_fsm_reg_tx_count_6_4_), + .I1(plm_fsm_pa_counter3_reg_tx_count[4]), + .I2(plm_fsm_pa_counter3_un1_enable_1), + .LO(plm_fsm_pa_counter3_reg_tx_count_qxu[4]) + ); + defparam plm_fsm_pa_counter3_reg_tx_count_qxu_0_5_.INIT = 4'h7; + LUT2_L plm_fsm_pa_counter3_reg_tx_count_qxu_0_5_ ( + .I0(plm_fsm_pa_counter3_reg_tx_count[5]), + .I1(plm_fsm_pa_counter3_un1_enable_1), + .LO(plm_fsm_pa_counter3_reg_tx_count_qxu[5]) + ); + defparam plm_fsm_pa_counter3_reg_tx_count_qxu_0_6_.INIT = 4'h7; + LUT2_L plm_fsm_pa_counter3_reg_tx_count_qxu_0_6_ ( + .I0(plm_fsm_pa_counter3_reg_tx_count[6]), + .I1(plm_fsm_pa_counter3_un1_enable_1), + .LO(plm_fsm_pa_counter3_reg_tx_count_qxu[6]) + ); + defparam plm_fsm_pa_counter3_reg_tx_count_qxu_0_7_.INIT = 4'h7; + LUT2_L plm_fsm_pa_counter3_reg_tx_count_qxu_0_7_ ( + .I0(plm_fsm_pa_counter3_reg_tx_count[7]), + .I1(plm_fsm_pa_counter3_un1_enable_1), + .LO(plm_fsm_pa_counter3_reg_tx_count_qxu[7]) + ); + defparam plm_fsm_pa_counter3_reg_tx_count_qxu_0_8_.INIT = 4'h7; + LUT2_L plm_fsm_pa_counter3_reg_tx_count_qxu_0_8_ ( + .I0(plm_fsm_pa_counter3_reg_tx_count[8]), + .I1(plm_fsm_pa_counter3_un1_enable_1), + .LO(plm_fsm_pa_counter3_reg_tx_count_qxu[8]) + ); + defparam plm_fsm_pa_counter3_reg_tx_count_qxu_0_9_.INIT = 4'h7; + LUT2_L plm_fsm_pa_counter3_reg_tx_count_qxu_0_9_ ( + .I0(plm_fsm_pa_counter3_reg_tx_count[9]), + .I1(plm_fsm_pa_counter3_un1_enable_1), + .LO(plm_fsm_pa_counter3_reg_tx_count_qxu[9]) + ); + defparam plm_fsm_pa_counter3_reg_tx_count_qxu_0_10_.INIT = 8'h35; + LUT3_L plm_fsm_pa_counter3_reg_tx_count_qxu_0_10_ ( + .I0(plm_fsm_reg_tx_count_6_10_), + .I1(plm_fsm_pa_counter3_reg_tx_count[10]), + .I2(plm_fsm_pa_counter3_un1_enable_1), + .LO(plm_fsm_pa_counter3_reg_tx_count_qxu[10]) + ); + defparam plm_fsm_pa_counter3_reg_tx_count_qxu_0_11_.INIT = 4'h7; + LUT2_L plm_fsm_pa_counter3_reg_tx_count_qxu_0_11_ ( + .I0(plm_fsm_pa_counter3_reg_tx_count[11]), + .I1(plm_fsm_pa_counter3_un1_enable_1), + .LO(plm_fsm_pa_counter3_reg_tx_count_qxu[11]) + ); + GND plm_fsm_pc_timer_GND ( + .G(plm_fsm_pc_timer_GND_932) + ); + MUXCY_L plm_fsm_pc_timer_reg_count_cry_0_ ( + .CI(plm_fsm_reg_state_2__356), + .DI(plm_fsm_pc_timer_GND_932), + .LO(plm_fsm_pc_timer_reg_count_cry[0]), + .S(plm_fsm_pc_timer_reg_count_qxu[0]) + ); + XORCY plm_fsm_pc_timer_reg_count_s_0_ ( + .CI(plm_fsm_reg_state_2__356), + .LI(plm_fsm_pc_timer_reg_count_qxu[0]), + .O(plm_fsm_pc_timer_reg_count_s[0]) + ); + MUXCY_L plm_fsm_pc_timer_reg_count_cry_1_ ( + .CI(plm_fsm_pc_timer_reg_count_cry[0]), + .DI(plm_fsm_pc_timer_GND_932), + .LO(plm_fsm_pc_timer_reg_count_cry[1]), + .S(plm_fsm_pc_timer_reg_count_qxu[1]) + ); + XORCY plm_fsm_pc_timer_reg_count_s_1_ ( + .CI(plm_fsm_pc_timer_reg_count_cry[0]), + .LI(plm_fsm_pc_timer_reg_count_qxu[1]), + .O(plm_fsm_pc_timer_reg_count_s[1]) + ); + MUXCY_L plm_fsm_pc_timer_reg_count_cry_2_ ( + .CI(plm_fsm_pc_timer_reg_count_cry[1]), + .DI(plm_fsm_pc_timer_GND_932), + .LO(plm_fsm_pc_timer_reg_count_cry[2]), + .S(plm_fsm_pc_timer_reg_count_qxu[2]) + ); + XORCY plm_fsm_pc_timer_reg_count_s_2_ ( + .CI(plm_fsm_pc_timer_reg_count_cry[1]), + .LI(plm_fsm_pc_timer_reg_count_qxu[2]), + .O(plm_fsm_pc_timer_reg_count_s[2]) + ); + MUXCY_L plm_fsm_pc_timer_reg_count_cry_3_ ( + .CI(plm_fsm_pc_timer_reg_count_cry[2]), + .DI(plm_fsm_pc_timer_GND_932), + .LO(plm_fsm_pc_timer_reg_count_cry[3]), + .S(plm_fsm_pc_timer_reg_count_qxu[3]) + ); + XORCY plm_fsm_pc_timer_reg_count_s_3_ ( + .CI(plm_fsm_pc_timer_reg_count_cry[2]), + .LI(plm_fsm_pc_timer_reg_count_qxu[3]), + .O(plm_fsm_pc_timer_reg_count_s[3]) + ); + MUXCY_L plm_fsm_pc_timer_reg_count_cry_4_ ( + .CI(plm_fsm_pc_timer_reg_count_cry[3]), + .DI(plm_fsm_pc_timer_GND_932), + .LO(plm_fsm_pc_timer_reg_count_cry[4]), + .S(plm_fsm_pc_timer_reg_count_qxu[4]) + ); + XORCY plm_fsm_pc_timer_reg_count_s_4_ ( + .CI(plm_fsm_pc_timer_reg_count_cry[3]), + .LI(plm_fsm_pc_timer_reg_count_qxu[4]), + .O(plm_fsm_pc_timer_reg_count_s[4]) + ); + MUXCY_L plm_fsm_pc_timer_reg_count_cry_5_ ( + .CI(plm_fsm_pc_timer_reg_count_cry[4]), + .DI(plm_fsm_pc_timer_GND_932), + .LO(plm_fsm_pc_timer_reg_count_cry[5]), + .S(plm_fsm_pc_timer_reg_count_qxu[5]) + ); + XORCY plm_fsm_pc_timer_reg_count_s_5_ ( + .CI(plm_fsm_pc_timer_reg_count_cry[4]), + .LI(plm_fsm_pc_timer_reg_count_qxu[5]), + .O(plm_fsm_pc_timer_reg_count_s[5]) + ); + MUXCY_L plm_fsm_pc_timer_reg_count_cry_6_ ( + .CI(plm_fsm_pc_timer_reg_count_cry[5]), + .DI(plm_fsm_pc_timer_GND_932), + .LO(plm_fsm_pc_timer_reg_count_cry[6]), + .S(plm_fsm_pc_timer_reg_count_qxu[6]) + ); + XORCY plm_fsm_pc_timer_reg_count_s_6_ ( + .CI(plm_fsm_pc_timer_reg_count_cry[5]), + .LI(plm_fsm_pc_timer_reg_count_qxu[6]), + .O(plm_fsm_pc_timer_reg_count_s[6]) + ); + MUXCY_L plm_fsm_pc_timer_reg_count_cry_7_ ( + .CI(plm_fsm_pc_timer_reg_count_cry[6]), + .DI(plm_fsm_pc_timer_GND_932), + .LO(plm_fsm_pc_timer_reg_count_cry[7]), + .S(plm_fsm_pc_timer_reg_count_qxu[7]) + ); + XORCY plm_fsm_pc_timer_reg_count_s_7_ ( + .CI(plm_fsm_pc_timer_reg_count_cry[6]), + .LI(plm_fsm_pc_timer_reg_count_qxu[7]), + .O(plm_fsm_pc_timer_reg_count_s[7]) + ); + MUXCY_L plm_fsm_pc_timer_reg_count_cry_8_ ( + .CI(plm_fsm_pc_timer_reg_count_cry[7]), + .DI(plm_fsm_pc_timer_GND_932), + .LO(plm_fsm_pc_timer_reg_count_cry[8]), + .S(plm_fsm_pc_timer_reg_count_qxu[8]) + ); + XORCY plm_fsm_pc_timer_reg_count_s_8_ ( + .CI(plm_fsm_pc_timer_reg_count_cry[7]), + .LI(plm_fsm_pc_timer_reg_count_qxu[8]), + .O(plm_fsm_pc_timer_reg_count_s[8]) + ); + MUXCY_L plm_fsm_pc_timer_reg_count_cry_9_ ( + .CI(plm_fsm_pc_timer_reg_count_cry[8]), + .DI(plm_fsm_pc_timer_GND_932), + .LO(plm_fsm_pc_timer_reg_count_cry[9]), + .S(plm_fsm_pc_timer_reg_count_qxu[9]) + ); + XORCY plm_fsm_pc_timer_reg_count_s_9_ ( + .CI(plm_fsm_pc_timer_reg_count_cry[8]), + .LI(plm_fsm_pc_timer_reg_count_qxu[9]), + .O(plm_fsm_pc_timer_reg_count_s[9]) + ); + MUXCY_L plm_fsm_pc_timer_reg_count_cry_10_ ( + .CI(plm_fsm_pc_timer_reg_count_cry[9]), + .DI(plm_fsm_pc_timer_GND_932), + .LO(plm_fsm_pc_timer_reg_count_cry[10]), + .S(plm_fsm_pc_timer_reg_count_qxu[10]) + ); + XORCY plm_fsm_pc_timer_reg_count_s_10_ ( + .CI(plm_fsm_pc_timer_reg_count_cry[9]), + .LI(plm_fsm_pc_timer_reg_count_qxu[10]), + .O(plm_fsm_pc_timer_reg_count_s[10]) + ); + MUXCY_L plm_fsm_pc_timer_reg_count_cry_11_ ( + .CI(plm_fsm_pc_timer_reg_count_cry[10]), + .DI(plm_fsm_pc_timer_GND_932), + .LO(plm_fsm_pc_timer_reg_count_cry[11]), + .S(plm_fsm_pc_timer_reg_count_qxu[11]) + ); + XORCY plm_fsm_pc_timer_reg_count_s_11_ ( + .CI(plm_fsm_pc_timer_reg_count_cry[10]), + .LI(plm_fsm_pc_timer_reg_count_qxu[11]), + .O(plm_fsm_pc_timer_reg_count_s[11]) + ); + MUXCY_L plm_fsm_pc_timer_reg_count_cry_12_ ( + .CI(plm_fsm_pc_timer_reg_count_cry[11]), + .DI(plm_fsm_pc_timer_GND_932), + .LO(plm_fsm_pc_timer_reg_count_cry[12]), + .S(plm_fsm_pc_timer_reg_count_qxu[12]) + ); + XORCY plm_fsm_pc_timer_reg_count_s_12_ ( + .CI(plm_fsm_pc_timer_reg_count_cry[11]), + .LI(plm_fsm_pc_timer_reg_count_qxu[12]), + .O(plm_fsm_pc_timer_reg_count_s[12]) + ); + MUXCY_L plm_fsm_pc_timer_reg_count_cry_13_ ( + .CI(plm_fsm_pc_timer_reg_count_cry[12]), + .DI(plm_fsm_pc_timer_GND_932), + .LO(plm_fsm_pc_timer_reg_count_cry[13]), + .S(plm_fsm_pc_timer_reg_count_qxu[13]) + ); + XORCY plm_fsm_pc_timer_reg_count_s_13_ ( + .CI(plm_fsm_pc_timer_reg_count_cry[12]), + .LI(plm_fsm_pc_timer_reg_count_qxu[13]), + .O(plm_fsm_pc_timer_reg_count_s[13]) + ); + MUXCY_L plm_fsm_pc_timer_reg_count_cry_14_ ( + .CI(plm_fsm_pc_timer_reg_count_cry[13]), + .DI(plm_fsm_pc_timer_GND_932), + .LO(plm_fsm_pc_timer_reg_count_cry[14]), + .S(plm_fsm_pc_timer_reg_count_qxu[14]) + ); + XORCY plm_fsm_pc_timer_reg_count_s_14_ ( + .CI(plm_fsm_pc_timer_reg_count_cry[13]), + .LI(plm_fsm_pc_timer_reg_count_qxu[14]), + .O(plm_fsm_pc_timer_reg_count_s[14]) + ); + MUXCY_L plm_fsm_pc_timer_reg_count_cry_15_ ( + .CI(plm_fsm_pc_timer_reg_count_cry[14]), + .DI(plm_fsm_pc_timer_GND_932), + .LO(plm_fsm_pc_timer_reg_count_cry[15]), + .S(plm_fsm_pc_timer_reg_count_qxu[15]) + ); + XORCY plm_fsm_pc_timer_reg_count_s_15_ ( + .CI(plm_fsm_pc_timer_reg_count_cry[14]), + .LI(plm_fsm_pc_timer_reg_count_qxu[15]), + .O(plm_fsm_pc_timer_reg_count_s[15]) + ); + MUXCY_L plm_fsm_pc_timer_reg_count_cry_16_ ( + .CI(plm_fsm_pc_timer_reg_count_cry[15]), + .DI(plm_fsm_pc_timer_GND_932), + .LO(plm_fsm_pc_timer_reg_count_cry[16]), + .S(plm_fsm_pc_timer_reg_count_qxu[16]) + ); + XORCY plm_fsm_pc_timer_reg_count_s_16_ ( + .CI(plm_fsm_pc_timer_reg_count_cry[15]), + .LI(plm_fsm_pc_timer_reg_count_qxu[16]), + .O(plm_fsm_pc_timer_reg_count_s[16]) + ); + MUXCY_L plm_fsm_pc_timer_reg_count_cry_17_ ( + .CI(plm_fsm_pc_timer_reg_count_cry[16]), + .DI(plm_fsm_pc_timer_GND_932), + .LO(plm_fsm_pc_timer_reg_count_cry[17]), + .S(plm_fsm_pc_timer_reg_count_qxu[17]) + ); + XORCY plm_fsm_pc_timer_reg_count_s_17_ ( + .CI(plm_fsm_pc_timer_reg_count_cry[16]), + .LI(plm_fsm_pc_timer_reg_count_qxu[17]), + .O(plm_fsm_pc_timer_reg_count_s[17]) + ); + MUXCY_L plm_fsm_pc_timer_reg_count_cry_18_ ( + .CI(plm_fsm_pc_timer_reg_count_cry[17]), + .DI(plm_fsm_pc_timer_GND_932), + .LO(plm_fsm_pc_timer_reg_count_cry[18]), + .S(plm_fsm_pc_timer_reg_count_qxu[18]) + ); + XORCY plm_fsm_pc_timer_reg_count_s_18_ ( + .CI(plm_fsm_pc_timer_reg_count_cry[17]), + .LI(plm_fsm_pc_timer_reg_count_qxu[18]), + .O(plm_fsm_pc_timer_reg_count_s[18]) + ); + MUXCY_L plm_fsm_pc_timer_reg_count_cry_19_ ( + .CI(plm_fsm_pc_timer_reg_count_cry[18]), + .DI(plm_fsm_pc_timer_GND_932), + .LO(plm_fsm_pc_timer_reg_count_cry[19]), + .S(plm_fsm_pc_timer_reg_count_qxu[19]) + ); + XORCY plm_fsm_pc_timer_reg_count_s_19_ ( + .CI(plm_fsm_pc_timer_reg_count_cry[18]), + .LI(plm_fsm_pc_timer_reg_count_qxu[19]), + .O(plm_fsm_pc_timer_reg_count_s[19]) + ); + MUXCY_L plm_fsm_pc_timer_reg_count_cry_20_ ( + .CI(plm_fsm_pc_timer_reg_count_cry[19]), + .DI(plm_fsm_pc_timer_GND_932), + .LO(plm_fsm_pc_timer_reg_count_cry[20]), + .S(plm_fsm_pc_timer_reg_count_qxu[20]) + ); + XORCY plm_fsm_pc_timer_reg_count_s_20_ ( + .CI(plm_fsm_pc_timer_reg_count_cry[19]), + .LI(plm_fsm_pc_timer_reg_count_qxu[20]), + .O(plm_fsm_pc_timer_reg_count_s[20]) + ); + MUXCY_L plm_fsm_pc_timer_reg_count_cry_21_ ( + .CI(plm_fsm_pc_timer_reg_count_cry[20]), + .DI(plm_fsm_pc_timer_GND_932), + .LO(plm_fsm_pc_timer_reg_count_cry[21]), + .S(plm_fsm_pc_timer_reg_count_qxu[21]) + ); + XORCY plm_fsm_pc_timer_reg_count_s_21_ ( + .CI(plm_fsm_pc_timer_reg_count_cry[20]), + .LI(plm_fsm_pc_timer_reg_count_qxu[21]), + .O(plm_fsm_pc_timer_reg_count_s[21]) + ); + XORCY plm_fsm_pc_timer_reg_count_s_22_ ( + .CI(plm_fsm_pc_timer_reg_count_cry[21]), + .LI(plm_fsm_pc_timer_reg_count_qxu[22]), + .O(plm_fsm_pc_timer_reg_count_s[22]) + ); + defparam plm_fsm_pc_timer_count_i_m3_i_m3_0_21_.INIT = 8'hD8; + LUT3_L plm_fsm_pc_timer_count_i_m3_i_m3_0_21_ ( + .I0(cfg_cfg_5072[507]), + .I1(plm_fsm_pc_timer_reg_count[13]), + .I2(plm_fsm_pc_timer_reg_count[21]), + .LO(plm_fsm_pc_timer_N_51446) + ); + defparam plm_fsm_pc_timer_expired_1_0_a2_0_a4.INIT = 16'hA280; + LUT4 plm_fsm_pc_timer_expired_1_0_a2_0_a4 ( + .I0(plm_fsm_pc_timer_N_51446), + .I1(cfg_cfg_5072[507]), + .I2(plm_fsm_pc_timer_reg_count[14]), + .I3(plm_fsm_pc_timer_reg_count[22]), + .O(plm_fsm_pc_timeout_1) + ); + defparam plm_fsm_pc_timer_expired_0_a3_0_a3.INIT = 4'h8; + LUT2 plm_fsm_pc_timer_expired_0_a3_0_a3 ( + .I0(plm_fsm_pc_timeout_1), + .I1(plm_fsm_reg_state_2__356), + .O(plm_fsm_pc_timeout) + ); + FDC plm_fsm_pc_timer_reg_count_22_ ( + .C(mgt_clk), + .D(plm_fsm_pc_timer_reg_count_s[22]), + .Q(plm_fsm_pc_timer_reg_count[22]), + .CLR(plm_rst) + ); + FDC plm_fsm_pc_timer_reg_count_21_ ( + .C(mgt_clk), + .D(plm_fsm_pc_timer_reg_count_s[21]), + .Q(plm_fsm_pc_timer_reg_count[21]), + .CLR(plm_rst) + ); + FDC plm_fsm_pc_timer_reg_count_20_ ( + .C(mgt_clk), + .D(plm_fsm_pc_timer_reg_count_s[20]), + .Q(plm_fsm_pc_timer_reg_count[20]), + .CLR(plm_rst) + ); + FDC plm_fsm_pc_timer_reg_count_19_ ( + .C(mgt_clk), + .D(plm_fsm_pc_timer_reg_count_s[19]), + .Q(plm_fsm_pc_timer_reg_count[19]), + .CLR(plm_rst) + ); + FDC plm_fsm_pc_timer_reg_count_18_ ( + .C(mgt_clk), + .D(plm_fsm_pc_timer_reg_count_s[18]), + .Q(plm_fsm_pc_timer_reg_count[18]), + .CLR(plm_rst) + ); + FDC plm_fsm_pc_timer_reg_count_17_ ( + .C(mgt_clk), + .D(plm_fsm_pc_timer_reg_count_s[17]), + .Q(plm_fsm_pc_timer_reg_count[17]), + .CLR(plm_rst) + ); + FDC plm_fsm_pc_timer_reg_count_16_ ( + .C(mgt_clk), + .D(plm_fsm_pc_timer_reg_count_s[16]), + .Q(plm_fsm_pc_timer_reg_count[16]), + .CLR(plm_rst) + ); + FDC plm_fsm_pc_timer_reg_count_15_ ( + .C(mgt_clk), + .D(plm_fsm_pc_timer_reg_count_s[15]), + .Q(plm_fsm_pc_timer_reg_count[15]), + .CLR(plm_rst) + ); + FDC plm_fsm_pc_timer_reg_count_14_ ( + .C(mgt_clk), + .D(plm_fsm_pc_timer_reg_count_s[14]), + .Q(plm_fsm_pc_timer_reg_count[14]), + .CLR(plm_rst) + ); + FDC plm_fsm_pc_timer_reg_count_13_ ( + .C(mgt_clk), + .D(plm_fsm_pc_timer_reg_count_s[13]), + .Q(plm_fsm_pc_timer_reg_count[13]), + .CLR(plm_rst) + ); + FDC plm_fsm_pc_timer_reg_count_12_ ( + .C(mgt_clk), + .D(plm_fsm_pc_timer_reg_count_s[12]), + .Q(plm_fsm_pc_timer_reg_count[12]), + .CLR(plm_rst) + ); + FDC plm_fsm_pc_timer_reg_count_11_ ( + .C(mgt_clk), + .D(plm_fsm_pc_timer_reg_count_s[11]), + .Q(plm_fsm_pc_timer_reg_count[11]), + .CLR(plm_rst) + ); + FDC plm_fsm_pc_timer_reg_count_10_ ( + .C(mgt_clk), + .D(plm_fsm_pc_timer_reg_count_s[10]), + .Q(plm_fsm_pc_timer_reg_count[10]), + .CLR(plm_rst) + ); + FDC plm_fsm_pc_timer_reg_count_9_ ( + .C(mgt_clk), + .D(plm_fsm_pc_timer_reg_count_s[9]), + .Q(plm_fsm_pc_timer_reg_count[9]), + .CLR(plm_rst) + ); + FDC plm_fsm_pc_timer_reg_count_8_ ( + .C(mgt_clk), + .D(plm_fsm_pc_timer_reg_count_s[8]), + .Q(plm_fsm_pc_timer_reg_count[8]), + .CLR(plm_rst) + ); + FDC plm_fsm_pc_timer_reg_count_7_ ( + .C(mgt_clk), + .D(plm_fsm_pc_timer_reg_count_s[7]), + .Q(plm_fsm_pc_timer_reg_count[7]), + .CLR(plm_rst) + ); + FDC plm_fsm_pc_timer_reg_count_6_ ( + .C(mgt_clk), + .D(plm_fsm_pc_timer_reg_count_s[6]), + .Q(plm_fsm_pc_timer_reg_count[6]), + .CLR(plm_rst) + ); + FDC plm_fsm_pc_timer_reg_count_5_ ( + .C(mgt_clk), + .D(plm_fsm_pc_timer_reg_count_s[5]), + .Q(plm_fsm_pc_timer_reg_count[5]), + .CLR(plm_rst) + ); + FDC plm_fsm_pc_timer_reg_count_4_ ( + .C(mgt_clk), + .D(plm_fsm_pc_timer_reg_count_s[4]), + .Q(plm_fsm_pc_timer_reg_count[4]), + .CLR(plm_rst) + ); + FDC plm_fsm_pc_timer_reg_count_3_ ( + .C(mgt_clk), + .D(plm_fsm_pc_timer_reg_count_s[3]), + .Q(plm_fsm_pc_timer_reg_count[3]), + .CLR(plm_rst) + ); + FDC plm_fsm_pc_timer_reg_count_2_ ( + .C(mgt_clk), + .D(plm_fsm_pc_timer_reg_count_s[2]), + .Q(plm_fsm_pc_timer_reg_count[2]), + .CLR(plm_rst) + ); + FDC plm_fsm_pc_timer_reg_count_1_ ( + .C(mgt_clk), + .D(plm_fsm_pc_timer_reg_count_s[1]), + .Q(plm_fsm_pc_timer_reg_count[1]), + .CLR(plm_rst) + ); + FDC plm_fsm_pc_timer_reg_count_0_ ( + .C(mgt_clk), + .D(plm_fsm_pc_timer_reg_count_s[0]), + .Q(plm_fsm_pc_timer_reg_count[0]), + .CLR(plm_rst) + ); + defparam plm_fsm_pc_timer_reg_count_qxu_0_0_.INIT = 4'h8; + LUT2_L plm_fsm_pc_timer_reg_count_qxu_0_0_ ( + .I0(plm_fsm_pc_timer_reg_count[0]), + .I1(plm_fsm_reg_state_2__356), + .LO(plm_fsm_pc_timer_reg_count_qxu[0]) + ); + defparam plm_fsm_pc_timer_reg_count_qxu_0_1_.INIT = 4'h8; + LUT2_L plm_fsm_pc_timer_reg_count_qxu_0_1_ ( + .I0(plm_fsm_pc_timer_reg_count[1]), + .I1(plm_fsm_reg_state_2__356), + .LO(plm_fsm_pc_timer_reg_count_qxu[1]) + ); + defparam plm_fsm_pc_timer_reg_count_qxu_0_2_.INIT = 4'h8; + LUT2_L plm_fsm_pc_timer_reg_count_qxu_0_2_ ( + .I0(plm_fsm_pc_timer_reg_count[2]), + .I1(plm_fsm_reg_state_2__356), + .LO(plm_fsm_pc_timer_reg_count_qxu[2]) + ); + defparam plm_fsm_pc_timer_reg_count_qxu_0_3_.INIT = 4'h8; + LUT2_L plm_fsm_pc_timer_reg_count_qxu_0_3_ ( + .I0(plm_fsm_pc_timer_reg_count[3]), + .I1(plm_fsm_reg_state_2__356), + .LO(plm_fsm_pc_timer_reg_count_qxu[3]) + ); + defparam plm_fsm_pc_timer_reg_count_qxu_0_4_.INIT = 4'h8; + LUT2_L plm_fsm_pc_timer_reg_count_qxu_0_4_ ( + .I0(plm_fsm_pc_timer_reg_count[4]), + .I1(plm_fsm_reg_state_2__356), + .LO(plm_fsm_pc_timer_reg_count_qxu[4]) + ); + defparam plm_fsm_pc_timer_reg_count_qxu_0_5_.INIT = 4'h8; + LUT2_L plm_fsm_pc_timer_reg_count_qxu_0_5_ ( + .I0(plm_fsm_pc_timer_reg_count[5]), + .I1(plm_fsm_reg_state_2__356), + .LO(plm_fsm_pc_timer_reg_count_qxu[5]) + ); + defparam plm_fsm_pc_timer_reg_count_qxu_0_6_.INIT = 4'h8; + LUT2_L plm_fsm_pc_timer_reg_count_qxu_0_6_ ( + .I0(plm_fsm_pc_timer_reg_count[6]), + .I1(plm_fsm_reg_state_2__356), + .LO(plm_fsm_pc_timer_reg_count_qxu[6]) + ); + defparam plm_fsm_pc_timer_reg_count_qxu_0_7_.INIT = 4'h8; + LUT2_L plm_fsm_pc_timer_reg_count_qxu_0_7_ ( + .I0(plm_fsm_pc_timer_reg_count[7]), + .I1(plm_fsm_reg_state_2__356), + .LO(plm_fsm_pc_timer_reg_count_qxu[7]) + ); + defparam plm_fsm_pc_timer_reg_count_qxu_0_8_.INIT = 4'h8; + LUT2_L plm_fsm_pc_timer_reg_count_qxu_0_8_ ( + .I0(plm_fsm_pc_timer_reg_count[8]), + .I1(plm_fsm_reg_state_2__356), + .LO(plm_fsm_pc_timer_reg_count_qxu[8]) + ); + defparam plm_fsm_pc_timer_reg_count_qxu_0_9_.INIT = 4'h8; + LUT2_L plm_fsm_pc_timer_reg_count_qxu_0_9_ ( + .I0(plm_fsm_pc_timer_reg_count[9]), + .I1(plm_fsm_reg_state_2__356), + .LO(plm_fsm_pc_timer_reg_count_qxu[9]) + ); + defparam plm_fsm_pc_timer_reg_count_qxu_0_10_.INIT = 4'h8; + LUT2_L plm_fsm_pc_timer_reg_count_qxu_0_10_ ( + .I0(plm_fsm_pc_timer_reg_count[10]), + .I1(plm_fsm_reg_state_2__356), + .LO(plm_fsm_pc_timer_reg_count_qxu[10]) + ); + defparam plm_fsm_pc_timer_reg_count_qxu_0_11_.INIT = 4'h8; + LUT2_L plm_fsm_pc_timer_reg_count_qxu_0_11_ ( + .I0(plm_fsm_pc_timer_reg_count[11]), + .I1(plm_fsm_reg_state_2__356), + .LO(plm_fsm_pc_timer_reg_count_qxu[11]) + ); + defparam plm_fsm_pc_timer_reg_count_qxu_0_12_.INIT = 4'h8; + LUT2_L plm_fsm_pc_timer_reg_count_qxu_0_12_ ( + .I0(plm_fsm_pc_timer_reg_count[12]), + .I1(plm_fsm_reg_state_2__356), + .LO(plm_fsm_pc_timer_reg_count_qxu[12]) + ); + defparam plm_fsm_pc_timer_reg_count_qxu_0_13_.INIT = 4'h8; + LUT2_L plm_fsm_pc_timer_reg_count_qxu_0_13_ ( + .I0(plm_fsm_pc_timer_reg_count[13]), + .I1(plm_fsm_reg_state_2__356), + .LO(plm_fsm_pc_timer_reg_count_qxu[13]) + ); + defparam plm_fsm_pc_timer_reg_count_qxu_0_14_.INIT = 4'h8; + LUT2_L plm_fsm_pc_timer_reg_count_qxu_0_14_ ( + .I0(plm_fsm_pc_timer_reg_count[14]), + .I1(plm_fsm_reg_state_2__356), + .LO(plm_fsm_pc_timer_reg_count_qxu[14]) + ); + defparam plm_fsm_pc_timer_reg_count_qxu_0_15_.INIT = 4'h8; + LUT2_L plm_fsm_pc_timer_reg_count_qxu_0_15_ ( + .I0(plm_fsm_pc_timer_reg_count[15]), + .I1(plm_fsm_reg_state_2__356), + .LO(plm_fsm_pc_timer_reg_count_qxu[15]) + ); + defparam plm_fsm_pc_timer_reg_count_qxu_0_16_.INIT = 4'h8; + LUT2_L plm_fsm_pc_timer_reg_count_qxu_0_16_ ( + .I0(plm_fsm_pc_timer_reg_count[16]), + .I1(plm_fsm_reg_state_2__356), + .LO(plm_fsm_pc_timer_reg_count_qxu[16]) + ); + defparam plm_fsm_pc_timer_reg_count_qxu_0_17_.INIT = 4'h8; + LUT2_L plm_fsm_pc_timer_reg_count_qxu_0_17_ ( + .I0(plm_fsm_pc_timer_reg_count[17]), + .I1(plm_fsm_reg_state_2__356), + .LO(plm_fsm_pc_timer_reg_count_qxu[17]) + ); + defparam plm_fsm_pc_timer_reg_count_qxu_0_18_.INIT = 4'h8; + LUT2_L plm_fsm_pc_timer_reg_count_qxu_0_18_ ( + .I0(plm_fsm_pc_timer_reg_count[18]), + .I1(plm_fsm_reg_state_2__356), + .LO(plm_fsm_pc_timer_reg_count_qxu[18]) + ); + defparam plm_fsm_pc_timer_reg_count_qxu_0_19_.INIT = 4'h8; + LUT2_L plm_fsm_pc_timer_reg_count_qxu_0_19_ ( + .I0(plm_fsm_pc_timer_reg_count[19]), + .I1(plm_fsm_reg_state_2__356), + .LO(plm_fsm_pc_timer_reg_count_qxu[19]) + ); + defparam plm_fsm_pc_timer_reg_count_qxu_0_20_.INIT = 4'h8; + LUT2_L plm_fsm_pc_timer_reg_count_qxu_0_20_ ( + .I0(plm_fsm_pc_timer_reg_count[20]), + .I1(plm_fsm_reg_state_2__356), + .LO(plm_fsm_pc_timer_reg_count_qxu[20]) + ); + defparam plm_fsm_pc_timer_reg_count_qxu_0_21_.INIT = 4'h8; + LUT2_L plm_fsm_pc_timer_reg_count_qxu_0_21_ ( + .I0(plm_fsm_pc_timer_reg_count[21]), + .I1(plm_fsm_reg_state_2__356), + .LO(plm_fsm_pc_timer_reg_count_qxu[21]) + ); + defparam plm_fsm_pc_timer_reg_count_qxu_0_22_.INIT = 4'h8; + LUT2_L plm_fsm_pc_timer_reg_count_qxu_0_22_ ( + .I0(plm_fsm_pc_timer_reg_count[22]), + .I1(plm_fsm_reg_state_2__356), + .LO(plm_fsm_pc_timer_reg_count_qxu[22]) + ); + VCC plm_fsm_pc_counter0_VCC ( + .P(plm_fsm_pc_counter0_VCC_933) + ); + MUXCY_L plm_fsm_pc_counter0_reg_rx_count_cry_0_ ( + .CI(N_38578_i_24), + .DI(plm_fsm_pc_counter0_VCC_933), + .LO(plm_fsm_pc_counter0_reg_rx_count_cry[0]), + .S(plm_fsm_pc_counter0_reg_rx_count_qxu[0]) + ); + XORCY plm_fsm_pc_counter0_reg_rx_count_s_0_ ( + .CI(N_38578_i_24), + .LI(plm_fsm_pc_counter0_reg_rx_count_qxu[0]), + .O(plm_fsm_pc_counter0_reg_rx_count_s[0]) + ); + MUXCY_L plm_fsm_pc_counter0_reg_rx_count_cry_1_ ( + .CI(plm_fsm_pc_counter0_reg_rx_count_cry[0]), + .DI(plm_fsm_pc_counter0_VCC_933), + .LO(plm_fsm_pc_counter0_reg_rx_count_cry[1]), + .S(plm_fsm_pc_counter0_reg_rx_count_qxu[1]) + ); + XORCY plm_fsm_pc_counter0_reg_rx_count_s_1_ ( + .CI(plm_fsm_pc_counter0_reg_rx_count_cry[0]), + .LI(plm_fsm_pc_counter0_reg_rx_count_qxu[1]), + .O(plm_fsm_pc_counter0_reg_rx_count_s[1]) + ); + MUXCY_L plm_fsm_pc_counter0_reg_rx_count_cry_2_ ( + .CI(plm_fsm_pc_counter0_reg_rx_count_cry[1]), + .DI(plm_fsm_pc_counter0_VCC_933), + .LO(plm_fsm_pc_counter0_reg_rx_count_cry[2]), + .S(plm_fsm_pc_counter0_reg_rx_count_qxu[2]) + ); + XORCY plm_fsm_pc_counter0_reg_rx_count_s_2_ ( + .CI(plm_fsm_pc_counter0_reg_rx_count_cry[1]), + .LI(plm_fsm_pc_counter0_reg_rx_count_qxu[2]), + .O(plm_fsm_pc_counter0_reg_rx_count_s[2]) + ); + MUXCY_L plm_fsm_pc_counter0_reg_rx_count_cry_3_ ( + .CI(plm_fsm_pc_counter0_reg_rx_count_cry[2]), + .DI(plm_fsm_pc_counter0_VCC_933), + .LO(plm_fsm_pc_counter0_reg_rx_count_cry[3]), + .S(plm_fsm_pc_counter0_reg_rx_count_qxu[3]) + ); + XORCY plm_fsm_pc_counter0_reg_rx_count_s_3_ ( + .CI(plm_fsm_pc_counter0_reg_rx_count_cry[2]), + .LI(plm_fsm_pc_counter0_reg_rx_count_qxu[3]), + .O(plm_fsm_pc_counter0_reg_rx_count_s[3]) + ); + MUXCY_L plm_fsm_pc_counter0_reg_rx_count_cry_4_ ( + .CI(plm_fsm_pc_counter0_reg_rx_count_cry[3]), + .DI(plm_fsm_pc_counter0_VCC_933), + .LO(plm_fsm_pc_counter0_reg_rx_count_cry[4]), + .S(plm_fsm_pc_counter0_reg_rx_count_qxu[4]) + ); + XORCY plm_fsm_pc_counter0_reg_rx_count_s_4_ ( + .CI(plm_fsm_pc_counter0_reg_rx_count_cry[3]), + .LI(plm_fsm_pc_counter0_reg_rx_count_qxu[4]), + .O(plm_fsm_pc_counter0_reg_rx_count_s[4]) + ); + MUXCY_L plm_fsm_pc_counter0_reg_rx_count_cry_5_ ( + .CI(plm_fsm_pc_counter0_reg_rx_count_cry[4]), + .DI(plm_fsm_pc_counter0_VCC_933), + .LO(plm_fsm_pc_counter0_reg_rx_count_cry[5]), + .S(plm_fsm_pc_counter0_reg_rx_count_qxu[5]) + ); + XORCY plm_fsm_pc_counter0_reg_rx_count_s_5_ ( + .CI(plm_fsm_pc_counter0_reg_rx_count_cry[4]), + .LI(plm_fsm_pc_counter0_reg_rx_count_qxu[5]), + .O(plm_fsm_pc_counter0_reg_rx_count_s[5]) + ); + MUXCY_L plm_fsm_pc_counter0_reg_rx_count_cry_6_ ( + .CI(plm_fsm_pc_counter0_reg_rx_count_cry[5]), + .DI(plm_fsm_pc_counter0_VCC_933), + .LO(plm_fsm_pc_counter0_reg_rx_count_cry[6]), + .S(plm_fsm_pc_counter0_reg_rx_count_qxu[6]) + ); + XORCY plm_fsm_pc_counter0_reg_rx_count_s_6_ ( + .CI(plm_fsm_pc_counter0_reg_rx_count_cry[5]), + .LI(plm_fsm_pc_counter0_reg_rx_count_qxu[6]), + .O(plm_fsm_pc_counter0_reg_rx_count_s[6]) + ); + XORCY plm_fsm_pc_counter0_reg_rx_count_s_7_ ( + .CI(plm_fsm_pc_counter0_reg_rx_count_cry[6]), + .LI(plm_fsm_pc_counter0_reg_rx_count_qxu[7]), + .O(plm_fsm_pc_counter0_reg_rx_count_s[7]) + ); + MUXCY_L plm_fsm_pc_counter0_reg_tx_count_cry_0_ ( + .CI(plm_fsm_pc_counter0_un1_enable_1_i_938), + .DI(plm_fsm_pc_counter0_VCC_933), + .LO(plm_fsm_pc_counter0_reg_tx_count_cry[0]), + .S(plm_fsm_pc_counter0_reg_tx_count_qxu[0]) + ); + XORCY plm_fsm_pc_counter0_reg_tx_count_s_0_ ( + .CI(plm_fsm_pc_counter0_un1_enable_1_i_938), + .LI(plm_fsm_pc_counter0_reg_tx_count_qxu[0]), + .O(plm_fsm_pc_counter0_reg_tx_count_s[0]) + ); + MUXCY_L plm_fsm_pc_counter0_reg_tx_count_cry_1_ ( + .CI(plm_fsm_pc_counter0_reg_tx_count_cry[0]), + .DI(plm_fsm_pc_counter0_VCC_933), + .LO(plm_fsm_pc_counter0_reg_tx_count_cry[1]), + .S(plm_fsm_pc_counter0_reg_tx_count_qxu[1]) + ); + XORCY plm_fsm_pc_counter0_reg_tx_count_s_1_ ( + .CI(plm_fsm_pc_counter0_reg_tx_count_cry[0]), + .LI(plm_fsm_pc_counter0_reg_tx_count_qxu[1]), + .O(plm_fsm_pc_counter0_reg_tx_count_s[1]) + ); + MUXCY_L plm_fsm_pc_counter0_reg_tx_count_cry_2_ ( + .CI(plm_fsm_pc_counter0_reg_tx_count_cry[1]), + .DI(plm_fsm_pc_counter0_VCC_933), + .LO(plm_fsm_pc_counter0_reg_tx_count_cry[2]), + .S(plm_fsm_pc_counter0_reg_tx_count_qxu[2]) + ); + XORCY plm_fsm_pc_counter0_reg_tx_count_s_2_ ( + .CI(plm_fsm_pc_counter0_reg_tx_count_cry[1]), + .LI(plm_fsm_pc_counter0_reg_tx_count_qxu[2]), + .O(plm_fsm_pc_counter0_reg_tx_count_s[2]) + ); + MUXCY_L plm_fsm_pc_counter0_reg_tx_count_cry_3_ ( + .CI(plm_fsm_pc_counter0_reg_tx_count_cry[2]), + .DI(plm_fsm_pc_counter0_VCC_933), + .LO(plm_fsm_pc_counter0_reg_tx_count_cry[3]), + .S(plm_fsm_pc_counter0_reg_tx_count_qxu[3]) + ); + XORCY plm_fsm_pc_counter0_reg_tx_count_s_3_ ( + .CI(plm_fsm_pc_counter0_reg_tx_count_cry[2]), + .LI(plm_fsm_pc_counter0_reg_tx_count_qxu[3]), + .O(plm_fsm_pc_counter0_reg_tx_count_s[3]) + ); + MUXCY_L plm_fsm_pc_counter0_reg_tx_count_cry_4_ ( + .CI(plm_fsm_pc_counter0_reg_tx_count_cry[3]), + .DI(plm_fsm_pc_counter0_VCC_933), + .LO(plm_fsm_pc_counter0_reg_tx_count_cry[4]), + .S(plm_fsm_pc_counter0_reg_tx_count_qxu[4]) + ); + XORCY plm_fsm_pc_counter0_reg_tx_count_s_4_ ( + .CI(plm_fsm_pc_counter0_reg_tx_count_cry[3]), + .LI(plm_fsm_pc_counter0_reg_tx_count_qxu[4]), + .O(plm_fsm_pc_counter0_reg_tx_count_s[4]) + ); + MUXCY_L plm_fsm_pc_counter0_reg_tx_count_cry_5_ ( + .CI(plm_fsm_pc_counter0_reg_tx_count_cry[4]), + .DI(plm_fsm_pc_counter0_VCC_933), + .LO(plm_fsm_pc_counter0_reg_tx_count_cry[5]), + .S(plm_fsm_pc_counter0_reg_tx_count_qxu[5]) + ); + XORCY plm_fsm_pc_counter0_reg_tx_count_s_5_ ( + .CI(plm_fsm_pc_counter0_reg_tx_count_cry[4]), + .LI(plm_fsm_pc_counter0_reg_tx_count_qxu[5]), + .O(plm_fsm_pc_counter0_reg_tx_count_s[5]) + ); + MUXCY_L plm_fsm_pc_counter0_reg_tx_count_cry_6_ ( + .CI(plm_fsm_pc_counter0_reg_tx_count_cry[5]), + .DI(plm_fsm_pc_counter0_VCC_933), + .LO(plm_fsm_pc_counter0_reg_tx_count_cry[6]), + .S(plm_fsm_pc_counter0_reg_tx_count_qxu[6]) + ); + XORCY plm_fsm_pc_counter0_reg_tx_count_s_6_ ( + .CI(plm_fsm_pc_counter0_reg_tx_count_cry[5]), + .LI(plm_fsm_pc_counter0_reg_tx_count_qxu[6]), + .O(plm_fsm_pc_counter0_reg_tx_count_s[6]) + ); + XORCY plm_fsm_pc_counter0_reg_tx_count_s_7_ ( + .CI(plm_fsm_pc_counter0_reg_tx_count_cry[6]), + .LI(plm_fsm_pc_counter0_reg_tx_count_qxu[7]), + .O(plm_fsm_pc_counter0_reg_tx_count_s[7]) + ); + defparam plm_fsm_pc_counter0_loadable_tx_counter_reg_tx_count17_0_a2_0_a2_0_a4.INIT = 4'h8; + LUT2 plm_fsm_pc_counter0_loadable_tx_counter_reg_tx_count17_0_a2_0_a2_0_a4 ( + .I0(plm_fsm_pc_counter0_reg_oneshot_935), + .I1(plm_fsm_reg_state_2__356), + .O(plm_fsm_pc_counter0_un1_reg_tx_count17) + ); + defparam plm_fsm_pc_counter0_oneshot_monitor_un1_enable_0_a2_0_a2_0_a4.INIT = 4'h4; + LUT2 plm_fsm_pc_counter0_oneshot_monitor_un1_enable_0_a2_0_a2_0_a4 ( + .I0(plm_reg_ts2_1), + .I1(plm_fsm_reg_state_2__356), + .O(plm_fsm_pc_counter0_un1_enable_0_a2_0_a2_0_a4_0) + ); + defparam plm_fsm_pc_counter0_loadable_rx_counter_un1_reg_rx_count_0_a2_4.INIT = 16'h0001; + LUT4 plm_fsm_pc_counter0_loadable_rx_counter_un1_reg_rx_count_0_a2_4 ( + .I0(plm_fsm_pc_counter0_reg_rx_count[0]), + .I1(plm_fsm_pc_counter0_reg_rx_count[1]), + .I2(plm_fsm_pc_counter0_reg_rx_count[2]), + .I3(plm_fsm_pc_counter0_reg_rx_count[3]), + .O(plm_fsm_pc_counter0_un1_reg_rx_count_0_a2_4) + ); + defparam plm_fsm_pc_counter0_loadable_rx_counter_un1_reg_rx_count_0_a2_5.INIT = 16'h0001; + LUT4 plm_fsm_pc_counter0_loadable_rx_counter_un1_reg_rx_count_0_a2_5 ( + .I0(plm_fsm_pc_counter0_reg_rx_count[4]), + .I1(plm_fsm_pc_counter0_reg_rx_count[5]), + .I2(plm_fsm_pc_counter0_reg_rx_count[6]), + .I3(plm_fsm_pc_counter0_reg_rx_count[7]), + .O(plm_fsm_pc_counter0_un1_reg_rx_count_0_a2_5) + ); + defparam plm_fsm_pc_counter0_loadable_tx_counter_un1_reg_tx_count_0_a2_4.INIT = 16'h0001; + LUT4 plm_fsm_pc_counter0_loadable_tx_counter_un1_reg_tx_count_0_a2_4 ( + .I0(plm_fsm_pc_counter0_reg_tx_count[0]), + .I1(plm_fsm_pc_counter0_reg_tx_count[1]), + .I2(plm_fsm_pc_counter0_reg_tx_count[2]), + .I3(plm_fsm_pc_counter0_reg_tx_count[3]), + .O(plm_fsm_pc_counter0_un1_reg_tx_count_0_a2_4) + ); + defparam plm_fsm_pc_counter0_loadable_tx_counter_un1_reg_tx_count_0_a2_5.INIT = 16'h0001; + LUT4 plm_fsm_pc_counter0_loadable_tx_counter_un1_reg_tx_count_0_a2_5 ( + .I0(plm_fsm_pc_counter0_reg_tx_count[4]), + .I1(plm_fsm_pc_counter0_reg_tx_count[5]), + .I2(plm_fsm_pc_counter0_reg_tx_count[6]), + .I3(plm_fsm_pc_counter0_reg_tx_count[7]), + .O(plm_fsm_pc_counter0_un1_reg_tx_count_0_a2_5) + ); + defparam plm_fsm_pc_counter0_loadable_rx_counter_un1_rx_ts1_i.INIT = 4'hD; + LUT2 plm_fsm_pc_counter0_loadable_rx_counter_un1_rx_ts1_i ( + .I0(plm_fsm_pc_counter0_un1_enable_0_a2_0_a2_0_a4_0), + .I1(plm_fsm_pc_counter0_reg_rx_expired_355), + .O(plm_fsm_pc_counter0_un1_rx_ts1_i) + ); + defparam plm_fsm_pc_counter0_N_69324_i.INIT = 16'h0F2F; + LUT4 plm_fsm_pc_counter0_N_69324_i ( + .I0(plm_reg_ts2_1), + .I1(plm_fsm_pc_counter0_reg_rx_expired_355), + .I2(plm_fsm_reg_state_2__356), + .I3(plm_rx0_ts2_c), + .O(plm_fsm_pc_counter0_N_69324_i_939) + ); + defparam plm_fsm_pc_counter0_N_38554_i.INIT = 4'hB; + LUT2 plm_fsm_pc_counter0_N_38554_i ( + .I0(plm_reg_sym_sent_6_), + .I1(plm_fsm_pc_counter0_un1_enable_1), + .O(plm_fsm_pc_counter0_N_38554_i_934) + ); + defparam plm_fsm_pc_counter0_un1_enable_2_i.INIT = 8'h8F; + LUT3 plm_fsm_pc_counter0_un1_enable_2_i ( + .I0(plm_fsm_pc_counter0_un1_reg_tx_count_0_a2_4), + .I1(plm_fsm_pc_counter0_un1_reg_tx_count_0_a2_5), + .I2(plm_fsm_pc_counter0_un1_reg_tx_count17), + .O(plm_fsm_pc_counter0_un1_enable_2_i_936) + ); + defparam plm_fsm_pc_counter0_loadable_rx_counter_N_38706_i.INIT = 8'h8F; + LUT3 plm_fsm_pc_counter0_loadable_rx_counter_N_38706_i ( + .I0(plm_fsm_pc_counter0_un1_reg_rx_count_0_a2_4), + .I1(plm_fsm_pc_counter0_un1_reg_rx_count_0_a2_5), + .I2(plm_fsm_reg_state_2__356), + .O(plm_fsm_pc_counter0_N_38706_i) + ); + defparam plm_fsm_pc_counter0_flagit_reg_expired_5_0_a2_0_a2_0_a4.INIT = 8'h80; + LUT3_L plm_fsm_pc_counter0_flagit_reg_expired_5_0_a2_0_a2_0_a4 ( + .I0(plm_fsm_pc_counter0_reg_rx_expired_355), + .I1(plm_fsm_pc_counter0_reg_tx_expired_937), + .I2(plm_fsm_reg_state_2__356), + .LO(plm_fsm_pc_counter0_reg_expired_5) + ); + defparam plm_fsm_pc_counter0_un1_enable_1_0_a2_0_a2_0_a4.INIT = 8'h40; + LUT3 plm_fsm_pc_counter0_un1_enable_1_0_a2_0_a2_0_a4 ( + .I0(plm_fsm_pc_counter0_reg_tx_expired_937), + .I1(plm_fsm_reg_state_2__356), + .I2(plm_fsm_pc_counter0_reg_oneshot_935), + .O(plm_fsm_pc_counter0_un1_enable_1) + ); + FDCE plm_fsm_pc_counter0_reg_tx_count_7_ ( + .CE(plm_fsm_pc_counter0_N_38554_i_934), + .C(mgt_clk), + .D(plm_fsm_pc_counter0_reg_tx_count_s[7]), + .Q(plm_fsm_pc_counter0_reg_tx_count[7]), + .CLR(plm_rst) + ); + FDCE plm_fsm_pc_counter0_reg_tx_count_6_ ( + .CE(plm_fsm_pc_counter0_N_38554_i_934), + .C(mgt_clk), + .D(plm_fsm_pc_counter0_reg_tx_count_s[6]), + .Q(plm_fsm_pc_counter0_reg_tx_count[6]), + .CLR(plm_rst) + ); + FDCE plm_fsm_pc_counter0_reg_tx_count_5_ ( + .CE(plm_fsm_pc_counter0_N_38554_i_934), + .C(mgt_clk), + .D(plm_fsm_pc_counter0_reg_tx_count_s[5]), + .Q(plm_fsm_pc_counter0_reg_tx_count[5]), + .CLR(plm_rst) + ); + FDPE plm_fsm_pc_counter0_reg_tx_count_4_ ( + .PRE(plm_rst), + .CE(plm_fsm_pc_counter0_N_38554_i_934), + .C(mgt_clk), + .D(plm_fsm_pc_counter0_reg_tx_count_s[4]), + .Q(plm_fsm_pc_counter0_reg_tx_count[4]) + ); + FDCE plm_fsm_pc_counter0_reg_tx_count_3_ ( + .CE(plm_fsm_pc_counter0_N_38554_i_934), + .C(mgt_clk), + .D(plm_fsm_pc_counter0_reg_tx_count_s[3]), + .Q(plm_fsm_pc_counter0_reg_tx_count[3]), + .CLR(plm_rst) + ); + FDCE plm_fsm_pc_counter0_reg_tx_count_2_ ( + .CE(plm_fsm_pc_counter0_N_38554_i_934), + .C(mgt_clk), + .D(plm_fsm_pc_counter0_reg_tx_count_s[2]), + .Q(plm_fsm_pc_counter0_reg_tx_count[2]), + .CLR(plm_rst) + ); + FDCE plm_fsm_pc_counter0_reg_tx_count_1_ ( + .CE(plm_fsm_pc_counter0_N_38554_i_934), + .C(mgt_clk), + .D(plm_fsm_pc_counter0_reg_tx_count_s[1]), + .Q(plm_fsm_pc_counter0_reg_tx_count[1]), + .CLR(plm_rst) + ); + FDCE plm_fsm_pc_counter0_reg_tx_count_0_ ( + .CE(plm_fsm_pc_counter0_N_38554_i_934), + .C(mgt_clk), + .D(plm_fsm_pc_counter0_reg_tx_count_s[0]), + .Q(plm_fsm_pc_counter0_reg_tx_count[0]), + .CLR(plm_rst) + ); + FDCE plm_fsm_pc_counter0_reg_rx_count_7_ ( + .CE(plm_fsm_pc_counter0_un1_rx_ts1_i), + .C(mgt_clk), + .D(plm_fsm_pc_counter0_reg_rx_count_s[7]), + .Q(plm_fsm_pc_counter0_reg_rx_count[7]), + .CLR(plm_rst) + ); + FDCE plm_fsm_pc_counter0_reg_rx_count_6_ ( + .CE(plm_fsm_pc_counter0_un1_rx_ts1_i), + .C(mgt_clk), + .D(plm_fsm_pc_counter0_reg_rx_count_s[6]), + .Q(plm_fsm_pc_counter0_reg_rx_count[6]), + .CLR(plm_rst) + ); + FDCE plm_fsm_pc_counter0_reg_rx_count_5_ ( + .CE(plm_fsm_pc_counter0_un1_rx_ts1_i), + .C(mgt_clk), + .D(plm_fsm_pc_counter0_reg_rx_count_s[5]), + .Q(plm_fsm_pc_counter0_reg_rx_count[5]), + .CLR(plm_rst) + ); + FDCE plm_fsm_pc_counter0_reg_rx_count_4_ ( + .CE(plm_fsm_pc_counter0_un1_rx_ts1_i), + .C(mgt_clk), + .D(plm_fsm_pc_counter0_reg_rx_count_s[4]), + .Q(plm_fsm_pc_counter0_reg_rx_count[4]), + .CLR(plm_rst) + ); + FDPE plm_fsm_pc_counter0_reg_rx_count_3_ ( + .PRE(plm_rst), + .CE(plm_fsm_pc_counter0_un1_rx_ts1_i), + .C(mgt_clk), + .D(plm_fsm_pc_counter0_reg_rx_count_s[3]), + .Q(plm_fsm_pc_counter0_reg_rx_count[3]) + ); + FDCE plm_fsm_pc_counter0_reg_rx_count_2_ ( + .CE(plm_fsm_pc_counter0_un1_rx_ts1_i), + .C(mgt_clk), + .D(plm_fsm_pc_counter0_reg_rx_count_s[2]), + .Q(plm_fsm_pc_counter0_reg_rx_count[2]), + .CLR(plm_rst) + ); + FDCE plm_fsm_pc_counter0_reg_rx_count_1_ ( + .CE(plm_fsm_pc_counter0_un1_rx_ts1_i), + .C(mgt_clk), + .D(plm_fsm_pc_counter0_reg_rx_count_s[1]), + .Q(plm_fsm_pc_counter0_reg_rx_count[1]), + .CLR(plm_rst) + ); + FDCE plm_fsm_pc_counter0_reg_rx_count_0_ ( + .CE(plm_fsm_pc_counter0_un1_rx_ts1_i), + .C(mgt_clk), + .D(plm_fsm_pc_counter0_reg_rx_count_s[0]), + .Q(plm_fsm_pc_counter0_reg_rx_count[0]), + .CLR(plm_rst) + ); + FDC plm_fsm_pc_counter0_reg_expired ( + .C(mgt_clk), + .D(plm_fsm_pc_counter0_reg_expired_5), + .Q(plm_fsm_pc_cntrout0), + .CLR(plm_rst) + ); + FDCE plm_fsm_pc_counter0_reg_oneshot ( + .CE(plm_fsm_pc_counter0_N_38576_i), + .C(mgt_clk), + .D(plm_fsm_reg_state_2__356), + .Q(plm_fsm_pc_counter0_reg_oneshot_935), + .CLR(plm_rst) + ); + FDCE plm_fsm_pc_counter0_reg_rx_expired ( + .CE(plm_fsm_pc_counter0_N_38706_i), + .C(mgt_clk), + .D(plm_fsm_reg_state_2__356), + .Q(plm_fsm_pc_counter0_reg_rx_expired_355), + .CLR(plm_rst) + ); + FDCE plm_fsm_pc_counter0_reg_tx_expired ( + .CE(plm_fsm_pc_counter0_un1_enable_2_i_936), + .C(mgt_clk), + .D(plm_fsm_pc_counter0_un1_reg_tx_count17), + .Q(plm_fsm_pc_counter0_reg_tx_expired_937), + .CLR(plm_rst) + ); + INV plm_fsm_pc_counter0_oneshot_monitor_N_38576_i ( + .I(plm_fsm_pc_counter0_un1_enable_0_a2_0_a2_0_a4_0), + .O(plm_fsm_pc_counter0_N_38576_i) + ); + INV plm_fsm_pc_counter0_un1_enable_1_i ( + .I(plm_fsm_pc_counter0_un1_enable_1), + .O(plm_fsm_pc_counter0_un1_enable_1_i_938) + ); + defparam plm_fsm_pc_counter0_reg_rx_count_qxu_0_0_.INIT = 4'h7; + LUT2_L plm_fsm_pc_counter0_reg_rx_count_qxu_0_0_ ( + .I0(N_38578), + .I1(plm_fsm_pc_counter0_reg_rx_count[0]), + .LO(plm_fsm_pc_counter0_reg_rx_count_qxu[0]) + ); + defparam plm_fsm_pc_counter0_reg_rx_count_qxu_0_1_.INIT = 4'h7; + LUT2_L plm_fsm_pc_counter0_reg_rx_count_qxu_0_1_ ( + .I0(N_38578), + .I1(plm_fsm_pc_counter0_reg_rx_count[1]), + .LO(plm_fsm_pc_counter0_reg_rx_count_qxu[1]) + ); + defparam plm_fsm_pc_counter0_reg_rx_count_qxu_0_2_.INIT = 4'h7; + LUT2_L plm_fsm_pc_counter0_reg_rx_count_qxu_0_2_ ( + .I0(N_38578), + .I1(plm_fsm_pc_counter0_reg_rx_count[2]), + .LO(plm_fsm_pc_counter0_reg_rx_count_qxu[2]) + ); + defparam plm_fsm_pc_counter0_reg_rx_count_qxu_0_3_.INIT = 8'h1B; + LUT3_L plm_fsm_pc_counter0_reg_rx_count_qxu_0_3_ ( + .I0(N_38578), + .I1(plm_fsm_pc_counter0_N_69324_i_939), + .I2(plm_fsm_pc_counter0_reg_rx_count[3]), + .LO(plm_fsm_pc_counter0_reg_rx_count_qxu[3]) + ); + defparam plm_fsm_pc_counter0_reg_rx_count_qxu_0_4_.INIT = 4'h7; + LUT2_L plm_fsm_pc_counter0_reg_rx_count_qxu_0_4_ ( + .I0(N_38578), + .I1(plm_fsm_pc_counter0_reg_rx_count[4]), + .LO(plm_fsm_pc_counter0_reg_rx_count_qxu[4]) + ); + defparam plm_fsm_pc_counter0_reg_rx_count_qxu_0_5_.INIT = 4'h7; + LUT2_L plm_fsm_pc_counter0_reg_rx_count_qxu_0_5_ ( + .I0(N_38578), + .I1(plm_fsm_pc_counter0_reg_rx_count[5]), + .LO(plm_fsm_pc_counter0_reg_rx_count_qxu[5]) + ); + defparam plm_fsm_pc_counter0_reg_rx_count_qxu_0_6_.INIT = 4'h7; + LUT2_L plm_fsm_pc_counter0_reg_rx_count_qxu_0_6_ ( + .I0(N_38578), + .I1(plm_fsm_pc_counter0_reg_rx_count[6]), + .LO(plm_fsm_pc_counter0_reg_rx_count_qxu[6]) + ); + defparam plm_fsm_pc_counter0_reg_rx_count_qxu_0_7_.INIT = 4'h7; + LUT2_L plm_fsm_pc_counter0_reg_rx_count_qxu_0_7_ ( + .I0(N_38578), + .I1(plm_fsm_pc_counter0_reg_rx_count[7]), + .LO(plm_fsm_pc_counter0_reg_rx_count_qxu[7]) + ); + defparam plm_fsm_pc_counter0_reg_tx_count_qxu_0_0_.INIT = 4'h7; + LUT2_L plm_fsm_pc_counter0_reg_tx_count_qxu_0_0_ ( + .I0(plm_fsm_pc_counter0_reg_tx_count[0]), + .I1(plm_fsm_pc_counter0_un1_enable_1), + .LO(plm_fsm_pc_counter0_reg_tx_count_qxu[0]) + ); + defparam plm_fsm_pc_counter0_reg_tx_count_qxu_0_1_.INIT = 4'h7; + LUT2_L plm_fsm_pc_counter0_reg_tx_count_qxu_0_1_ ( + .I0(plm_fsm_pc_counter0_reg_tx_count[1]), + .I1(plm_fsm_pc_counter0_un1_enable_1), + .LO(plm_fsm_pc_counter0_reg_tx_count_qxu[1]) + ); + defparam plm_fsm_pc_counter0_reg_tx_count_qxu_0_2_.INIT = 4'h7; + LUT2_L plm_fsm_pc_counter0_reg_tx_count_qxu_0_2_ ( + .I0(plm_fsm_pc_counter0_reg_tx_count[2]), + .I1(plm_fsm_pc_counter0_un1_enable_1), + .LO(plm_fsm_pc_counter0_reg_tx_count_qxu[2]) + ); + defparam plm_fsm_pc_counter0_reg_tx_count_qxu_0_3_.INIT = 4'h7; + LUT2_L plm_fsm_pc_counter0_reg_tx_count_qxu_0_3_ ( + .I0(plm_fsm_pc_counter0_reg_tx_count[3]), + .I1(plm_fsm_pc_counter0_un1_enable_1), + .LO(plm_fsm_pc_counter0_reg_tx_count_qxu[3]) + ); + defparam plm_fsm_pc_counter0_reg_tx_count_qxu_0_4_.INIT = 8'h74; + LUT3_L plm_fsm_pc_counter0_reg_tx_count_qxu_0_4_ ( + .I0(plm_fsm_pc_counter0_reg_tx_count[4]), + .I1(plm_fsm_pc_counter0_un1_enable_1), + .I2(plm_fsm_pc_counter0_un1_reg_tx_count17), + .LO(plm_fsm_pc_counter0_reg_tx_count_qxu[4]) + ); + defparam plm_fsm_pc_counter0_reg_tx_count_qxu_0_5_.INIT = 4'h7; + LUT2_L plm_fsm_pc_counter0_reg_tx_count_qxu_0_5_ ( + .I0(plm_fsm_pc_counter0_reg_tx_count[5]), + .I1(plm_fsm_pc_counter0_un1_enable_1), + .LO(plm_fsm_pc_counter0_reg_tx_count_qxu[5]) + ); + defparam plm_fsm_pc_counter0_reg_tx_count_qxu_0_6_.INIT = 4'h7; + LUT2_L plm_fsm_pc_counter0_reg_tx_count_qxu_0_6_ ( + .I0(plm_fsm_pc_counter0_reg_tx_count[6]), + .I1(plm_fsm_pc_counter0_un1_enable_1), + .LO(plm_fsm_pc_counter0_reg_tx_count_qxu[6]) + ); + defparam plm_fsm_pc_counter0_reg_tx_count_qxu_0_7_.INIT = 4'h7; + LUT2_L plm_fsm_pc_counter0_reg_tx_count_qxu_0_7_ ( + .I0(plm_fsm_pc_counter0_reg_tx_count[7]), + .I1(plm_fsm_pc_counter0_un1_enable_1), + .LO(plm_fsm_pc_counter0_reg_tx_count_qxu[7]) + ); + VCC plm_fsm_pc_counter1_VCC ( + .P(plm_fsm_pc_counter1_VCC_940) + ); + MUXCY_L plm_fsm_pc_counter1_reg_tx_count_cry_0_ ( + .CI(plm_fsm_pc_counter1_un1_enable_1_i_941), + .DI(plm_fsm_pc_counter1_VCC_940), + .LO(plm_fsm_pc_counter1_reg_tx_count_cry[0]), + .S(plm_fsm_pc_counter1_reg_tx_count_qxu[0]) + ); + XORCY plm_fsm_pc_counter1_reg_tx_count_s_0_ ( + .CI(plm_fsm_pc_counter1_un1_enable_1_i_941), + .LI(plm_fsm_pc_counter1_reg_tx_count_qxu[0]), + .O(plm_fsm_pc_counter1_reg_tx_count_s[0]) + ); + MUXCY_L plm_fsm_pc_counter1_reg_tx_count_cry_1_ ( + .CI(plm_fsm_pc_counter1_reg_tx_count_cry[0]), + .DI(plm_fsm_pc_counter1_VCC_940), + .LO(plm_fsm_pc_counter1_reg_tx_count_cry[1]), + .S(plm_fsm_pc_counter1_reg_tx_count_qxu[1]) + ); + XORCY plm_fsm_pc_counter1_reg_tx_count_s_1_ ( + .CI(plm_fsm_pc_counter1_reg_tx_count_cry[0]), + .LI(plm_fsm_pc_counter1_reg_tx_count_qxu[1]), + .O(plm_fsm_pc_counter1_reg_tx_count_s[1]) + ); + MUXCY_L plm_fsm_pc_counter1_reg_tx_count_cry_2_ ( + .CI(plm_fsm_pc_counter1_reg_tx_count_cry[1]), + .DI(plm_fsm_pc_counter1_VCC_940), + .LO(plm_fsm_pc_counter1_reg_tx_count_cry[2]), + .S(plm_fsm_pc_counter1_reg_tx_count_qxu[2]) + ); + XORCY plm_fsm_pc_counter1_reg_tx_count_s_2_ ( + .CI(plm_fsm_pc_counter1_reg_tx_count_cry[1]), + .LI(plm_fsm_pc_counter1_reg_tx_count_qxu[2]), + .O(plm_fsm_pc_counter1_reg_tx_count_s[2]) + ); + MUXCY_L plm_fsm_pc_counter1_reg_tx_count_cry_3_ ( + .CI(plm_fsm_pc_counter1_reg_tx_count_cry[2]), + .DI(plm_fsm_pc_counter1_VCC_940), + .LO(plm_fsm_pc_counter1_reg_tx_count_cry[3]), + .S(plm_fsm_pc_counter1_reg_tx_count_qxu[3]) + ); + XORCY plm_fsm_pc_counter1_reg_tx_count_s_3_ ( + .CI(plm_fsm_pc_counter1_reg_tx_count_cry[2]), + .LI(plm_fsm_pc_counter1_reg_tx_count_qxu[3]), + .O(plm_fsm_pc_counter1_reg_tx_count_s[3]) + ); + MUXCY_L plm_fsm_pc_counter1_reg_tx_count_cry_4_ ( + .CI(plm_fsm_pc_counter1_reg_tx_count_cry[3]), + .DI(plm_fsm_pc_counter1_VCC_940), + .LO(plm_fsm_pc_counter1_reg_tx_count_cry[4]), + .S(plm_fsm_pc_counter1_reg_tx_count_qxu[4]) + ); + XORCY plm_fsm_pc_counter1_reg_tx_count_s_4_ ( + .CI(plm_fsm_pc_counter1_reg_tx_count_cry[3]), + .LI(plm_fsm_pc_counter1_reg_tx_count_qxu[4]), + .O(plm_fsm_pc_counter1_reg_tx_count_s[4]) + ); + MUXCY_L plm_fsm_pc_counter1_reg_tx_count_cry_5_ ( + .CI(plm_fsm_pc_counter1_reg_tx_count_cry[4]), + .DI(plm_fsm_pc_counter1_VCC_940), + .LO(plm_fsm_pc_counter1_reg_tx_count_cry[5]), + .S(plm_fsm_pc_counter1_reg_tx_count_qxu[5]) + ); + XORCY plm_fsm_pc_counter1_reg_tx_count_s_5_ ( + .CI(plm_fsm_pc_counter1_reg_tx_count_cry[4]), + .LI(plm_fsm_pc_counter1_reg_tx_count_qxu[5]), + .O(plm_fsm_pc_counter1_reg_tx_count_s[5]) + ); + MUXCY_L plm_fsm_pc_counter1_reg_tx_count_cry_6_ ( + .CI(plm_fsm_pc_counter1_reg_tx_count_cry[5]), + .DI(plm_fsm_pc_counter1_VCC_940), + .LO(plm_fsm_pc_counter1_reg_tx_count_cry[6]), + .S(plm_fsm_pc_counter1_reg_tx_count_qxu[6]) + ); + XORCY plm_fsm_pc_counter1_reg_tx_count_s_6_ ( + .CI(plm_fsm_pc_counter1_reg_tx_count_cry[5]), + .LI(plm_fsm_pc_counter1_reg_tx_count_qxu[6]), + .O(plm_fsm_pc_counter1_reg_tx_count_s[6]) + ); + XORCY plm_fsm_pc_counter1_reg_tx_count_s_7_ ( + .CI(plm_fsm_pc_counter1_reg_tx_count_cry[6]), + .LI(plm_fsm_pc_counter1_reg_tx_count_qxu[7]), + .O(plm_fsm_pc_counter1_reg_tx_count_s[7]) + ); + defparam plm_fsm_pc_counter1_loadable_rx_counter_N_38705_i.INIT = 4'h7; + LUT2 plm_fsm_pc_counter1_loadable_rx_counter_N_38705_i ( + .I0(plm_fsm_pc_counter1_reg_rx_count[3]), + .I1(plm_fsm_reg_state_2__356), + .O(plm_fsm_pc_counter1_N_38705_i) + ); + defparam plm_fsm_pc_counter1_loadable_rx_counter_N_38538_i.INIT = 4'hB; + LUT2 plm_fsm_pc_counter1_loadable_rx_counter_N_38538_i ( + .I0(plm_fsm_pc_counter1_reg_rx_expired_943), + .I1(plm_fsm_reg_state_2__356), + .O(plm_fsm_pc_counter1_N_38538_i) + ); + defparam plm_fsm_pc_counter1_loadable_tx_counter_un1_reg_tx_count_0_a2_0_a4_4.INIT = 16'h0001; + LUT4 plm_fsm_pc_counter1_loadable_tx_counter_un1_reg_tx_count_0_a2_0_a4_4 ( + .I0(plm_fsm_pc_counter1_reg_tx_count[0]), + .I1(plm_fsm_pc_counter1_reg_tx_count[1]), + .I2(plm_fsm_pc_counter1_reg_tx_count[2]), + .I3(plm_fsm_pc_counter1_reg_tx_count[3]), + .O(plm_fsm_pc_counter1_un1_reg_tx_count_0_a2_0_a4_4) + ); + defparam plm_fsm_pc_counter1_loadable_tx_counter_un1_reg_tx_count_0_a2_0_a4_5.INIT = 16'h0001; + LUT4 plm_fsm_pc_counter1_loadable_tx_counter_un1_reg_tx_count_0_a2_0_a4_5 ( + .I0(plm_fsm_pc_counter1_reg_tx_count[4]), + .I1(plm_fsm_pc_counter1_reg_tx_count[5]), + .I2(plm_fsm_pc_counter1_reg_tx_count[6]), + .I3(plm_fsm_pc_counter1_reg_tx_count[7]), + .O(plm_fsm_pc_counter1_un1_reg_tx_count_0_a2_0_a4_5) + ); + defparam plm_fsm_pc_counter1_N_38555_i.INIT = 4'hB; + LUT2 plm_fsm_pc_counter1_N_38555_i ( + .I0(plm_reg_sym_sent_6_), + .I1(plm_fsm_pc_counter1_un1_enable_1), + .O(plm_fsm_pc_counter1_N_38555_i_942) + ); + defparam plm_fsm_pc_counter1_un1_enable_2_i.INIT = 8'h8F; + LUT3 plm_fsm_pc_counter1_un1_enable_2_i ( + .I0(plm_fsm_pc_counter1_un1_reg_tx_count_0_a2_0_a4_4), + .I1(plm_fsm_pc_counter1_un1_reg_tx_count_0_a2_0_a4_5), + .I2(plm_fsm_un1_reg_tx_count17), + .O(plm_fsm_pc_counter1_un1_enable_2_i_944) + ); + defparam plm_fsm_pc_counter1_flagit_reg_expired_5_0_a2_0_a4.INIT = 8'h80; + LUT3_L plm_fsm_pc_counter1_flagit_reg_expired_5_0_a2_0_a4 ( + .I0(plm_fsm_pc_counter1_reg_rx_expired_943), + .I1(plm_fsm_pc_counter1_reg_tx_expired_945), + .I2(plm_fsm_reg_state_2__356), + .LO(plm_fsm_pc_counter1_reg_expired_5) + ); + defparam plm_fsm_pc_counter1_un1_enable_1_0_a2_0_a2_0_a4.INIT = 8'h40; + LUT3 plm_fsm_pc_counter1_un1_enable_1_0_a2_0_a2_0_a4 ( + .I0(plm_fsm_pc_counter1_reg_tx_expired_945), + .I1(plm_fsm_reg_state_2__356), + .I2(plm_fsm_reg_oneshot), + .O(plm_fsm_pc_counter1_un1_enable_1) + ); + defparam plm_fsm_pc_counter1_un1_enable_1_i.INIT = 8'hF7; + LUT3 plm_fsm_pc_counter1_un1_enable_1_i ( + .I0(plm_fsm_reg_oneshot), + .I1(plm_fsm_reg_state_2__356), + .I2(plm_fsm_pc_counter1_reg_tx_expired_945), + .O(plm_fsm_pc_counter1_un1_enable_1_i_941) + ); + FDCE plm_fsm_pc_counter1_reg_tx_count_7_ ( + .CE(plm_fsm_pc_counter1_N_38555_i_942), + .C(mgt_clk), + .D(plm_fsm_pc_counter1_reg_tx_count_s[7]), + .Q(plm_fsm_pc_counter1_reg_tx_count[7]), + .CLR(plm_rst) + ); + FDCE plm_fsm_pc_counter1_reg_tx_count_6_ ( + .CE(plm_fsm_pc_counter1_N_38555_i_942), + .C(mgt_clk), + .D(plm_fsm_pc_counter1_reg_tx_count_s[6]), + .Q(plm_fsm_pc_counter1_reg_tx_count[6]), + .CLR(plm_rst) + ); + FDCE plm_fsm_pc_counter1_reg_tx_count_5_ ( + .CE(plm_fsm_pc_counter1_N_38555_i_942), + .C(mgt_clk), + .D(plm_fsm_pc_counter1_reg_tx_count_s[5]), + .Q(plm_fsm_pc_counter1_reg_tx_count[5]), + .CLR(plm_rst) + ); + FDPE plm_fsm_pc_counter1_reg_tx_count_4_ ( + .PRE(plm_rst), + .CE(plm_fsm_pc_counter1_N_38555_i_942), + .C(mgt_clk), + .D(plm_fsm_pc_counter1_reg_tx_count_s[4]), + .Q(plm_fsm_pc_counter1_reg_tx_count[4]) + ); + FDCE plm_fsm_pc_counter1_reg_tx_count_3_ ( + .CE(plm_fsm_pc_counter1_N_38555_i_942), + .C(mgt_clk), + .D(plm_fsm_pc_counter1_reg_tx_count_s[3]), + .Q(plm_fsm_pc_counter1_reg_tx_count[3]), + .CLR(plm_rst) + ); + FDCE plm_fsm_pc_counter1_reg_tx_count_2_ ( + .CE(plm_fsm_pc_counter1_N_38555_i_942), + .C(mgt_clk), + .D(plm_fsm_pc_counter1_reg_tx_count_s[2]), + .Q(plm_fsm_pc_counter1_reg_tx_count[2]), + .CLR(plm_rst) + ); + FDCE plm_fsm_pc_counter1_reg_tx_count_1_ ( + .CE(plm_fsm_pc_counter1_N_38555_i_942), + .C(mgt_clk), + .D(plm_fsm_pc_counter1_reg_tx_count_s[1]), + .Q(plm_fsm_pc_counter1_reg_tx_count[1]), + .CLR(plm_rst) + ); + FDCE plm_fsm_pc_counter1_reg_tx_count_0_ ( + .CE(plm_fsm_pc_counter1_N_38555_i_942), + .C(mgt_clk), + .D(plm_fsm_pc_counter1_reg_tx_count_s[0]), + .Q(plm_fsm_pc_counter1_reg_tx_count[0]), + .CLR(plm_rst) + ); + FDC plm_fsm_pc_counter1_reg_expired ( + .C(mgt_clk), + .D(plm_fsm_pc_counter1_reg_expired_5), + .Q(plm_fsm_pc_cntrout1), + .CLR(plm_rst) + ); + FDPE plm_fsm_pc_counter1_reg_rx_count_3_ ( + .PRE(plm_rst), + .CE(plm_fsm_pc_counter1_N_38538_i), + .C(mgt_clk), + .D(plm_fsm_reg_state_i_2__905), + .Q(plm_fsm_pc_counter1_reg_rx_count[3]) + ); + FDCE plm_fsm_pc_counter1_reg_rx_expired ( + .CE(plm_fsm_pc_counter1_N_38705_i), + .C(mgt_clk), + .D(plm_fsm_reg_state_2__356), + .Q(plm_fsm_pc_counter1_reg_rx_expired_943), + .CLR(plm_rst) + ); + FDCE plm_fsm_pc_counter1_reg_tx_expired ( + .CE(plm_fsm_pc_counter1_un1_enable_2_i_944), + .C(mgt_clk), + .D(plm_fsm_un1_reg_tx_count17), + .Q(plm_fsm_pc_counter1_reg_tx_expired_945), + .CLR(plm_rst) + ); + defparam plm_fsm_pc_counter1_reg_tx_count_qxu_0_0_.INIT = 4'h7; + LUT2_L plm_fsm_pc_counter1_reg_tx_count_qxu_0_0_ ( + .I0(plm_fsm_pc_counter1_reg_tx_count[0]), + .I1(plm_fsm_pc_counter1_un1_enable_1), + .LO(plm_fsm_pc_counter1_reg_tx_count_qxu[0]) + ); + defparam plm_fsm_pc_counter1_reg_tx_count_qxu_0_1_.INIT = 4'h7; + LUT2_L plm_fsm_pc_counter1_reg_tx_count_qxu_0_1_ ( + .I0(plm_fsm_pc_counter1_reg_tx_count[1]), + .I1(plm_fsm_pc_counter1_un1_enable_1), + .LO(plm_fsm_pc_counter1_reg_tx_count_qxu[1]) + ); + defparam plm_fsm_pc_counter1_reg_tx_count_qxu_0_2_.INIT = 4'h7; + LUT2_L plm_fsm_pc_counter1_reg_tx_count_qxu_0_2_ ( + .I0(plm_fsm_pc_counter1_reg_tx_count[2]), + .I1(plm_fsm_pc_counter1_un1_enable_1), + .LO(plm_fsm_pc_counter1_reg_tx_count_qxu[2]) + ); + defparam plm_fsm_pc_counter1_reg_tx_count_qxu_0_3_.INIT = 4'h7; + LUT2_L plm_fsm_pc_counter1_reg_tx_count_qxu_0_3_ ( + .I0(plm_fsm_pc_counter1_reg_tx_count[3]), + .I1(plm_fsm_pc_counter1_un1_enable_1), + .LO(plm_fsm_pc_counter1_reg_tx_count_qxu[3]) + ); + defparam plm_fsm_pc_counter1_reg_tx_count_qxu_0_4_.INIT = 8'h74; + LUT3_L plm_fsm_pc_counter1_reg_tx_count_qxu_0_4_ ( + .I0(plm_fsm_pc_counter1_reg_tx_count[4]), + .I1(plm_fsm_pc_counter1_un1_enable_1), + .I2(plm_fsm_un1_reg_tx_count17), + .LO(plm_fsm_pc_counter1_reg_tx_count_qxu[4]) + ); + defparam plm_fsm_pc_counter1_reg_tx_count_qxu_0_5_.INIT = 4'h7; + LUT2_L plm_fsm_pc_counter1_reg_tx_count_qxu_0_5_ ( + .I0(plm_fsm_pc_counter1_reg_tx_count[5]), + .I1(plm_fsm_pc_counter1_un1_enable_1), + .LO(plm_fsm_pc_counter1_reg_tx_count_qxu[5]) + ); + defparam plm_fsm_pc_counter1_reg_tx_count_qxu_0_6_.INIT = 4'h7; + LUT2_L plm_fsm_pc_counter1_reg_tx_count_qxu_0_6_ ( + .I0(plm_fsm_pc_counter1_reg_tx_count[6]), + .I1(plm_fsm_pc_counter1_un1_enable_1), + .LO(plm_fsm_pc_counter1_reg_tx_count_qxu[6]) + ); + defparam plm_fsm_pc_counter1_reg_tx_count_qxu_0_7_.INIT = 4'h7; + LUT2_L plm_fsm_pc_counter1_reg_tx_count_qxu_0_7_ ( + .I0(plm_fsm_pc_counter1_reg_tx_count[7]), + .I1(plm_fsm_pc_counter1_un1_enable_1), + .LO(plm_fsm_pc_counter1_reg_tx_count_qxu[7]) + ); + VCC plm_fsm_pc_counter2_VCC ( + .P(plm_fsm_pc_counter2_VCC_946) + ); + MUXCY_L plm_fsm_pc_counter2_reg_tx_count_cry_0_ ( + .CI(plm_fsm_pc_counter2_un1_enable_1_i_947), + .DI(plm_fsm_pc_counter2_VCC_946), + .LO(plm_fsm_pc_counter2_reg_tx_count_cry[0]), + .S(plm_fsm_pc_counter2_reg_tx_count_qxu[0]) + ); + XORCY plm_fsm_pc_counter2_reg_tx_count_s_0_ ( + .CI(plm_fsm_pc_counter2_un1_enable_1_i_947), + .LI(plm_fsm_pc_counter2_reg_tx_count_qxu[0]), + .O(plm_fsm_pc_counter2_reg_tx_count_s[0]) + ); + MUXCY_L plm_fsm_pc_counter2_reg_tx_count_cry_1_ ( + .CI(plm_fsm_pc_counter2_reg_tx_count_cry[0]), + .DI(plm_fsm_pc_counter2_VCC_946), + .LO(plm_fsm_pc_counter2_reg_tx_count_cry[1]), + .S(plm_fsm_pc_counter2_reg_tx_count_qxu[1]) + ); + XORCY plm_fsm_pc_counter2_reg_tx_count_s_1_ ( + .CI(plm_fsm_pc_counter2_reg_tx_count_cry[0]), + .LI(plm_fsm_pc_counter2_reg_tx_count_qxu[1]), + .O(plm_fsm_pc_counter2_reg_tx_count_s[1]) + ); + MUXCY_L plm_fsm_pc_counter2_reg_tx_count_cry_2_ ( + .CI(plm_fsm_pc_counter2_reg_tx_count_cry[1]), + .DI(plm_fsm_pc_counter2_VCC_946), + .LO(plm_fsm_pc_counter2_reg_tx_count_cry[2]), + .S(plm_fsm_pc_counter2_reg_tx_count_qxu[2]) + ); + XORCY plm_fsm_pc_counter2_reg_tx_count_s_2_ ( + .CI(plm_fsm_pc_counter2_reg_tx_count_cry[1]), + .LI(plm_fsm_pc_counter2_reg_tx_count_qxu[2]), + .O(plm_fsm_pc_counter2_reg_tx_count_s[2]) + ); + MUXCY_L plm_fsm_pc_counter2_reg_tx_count_cry_3_ ( + .CI(plm_fsm_pc_counter2_reg_tx_count_cry[2]), + .DI(plm_fsm_pc_counter2_VCC_946), + .LO(plm_fsm_pc_counter2_reg_tx_count_cry[3]), + .S(plm_fsm_pc_counter2_reg_tx_count_qxu[3]) + ); + XORCY plm_fsm_pc_counter2_reg_tx_count_s_3_ ( + .CI(plm_fsm_pc_counter2_reg_tx_count_cry[2]), + .LI(plm_fsm_pc_counter2_reg_tx_count_qxu[3]), + .O(plm_fsm_pc_counter2_reg_tx_count_s[3]) + ); + MUXCY_L plm_fsm_pc_counter2_reg_tx_count_cry_4_ ( + .CI(plm_fsm_pc_counter2_reg_tx_count_cry[3]), + .DI(plm_fsm_pc_counter2_VCC_946), + .LO(plm_fsm_pc_counter2_reg_tx_count_cry[4]), + .S(plm_fsm_pc_counter2_reg_tx_count_qxu[4]) + ); + XORCY plm_fsm_pc_counter2_reg_tx_count_s_4_ ( + .CI(plm_fsm_pc_counter2_reg_tx_count_cry[3]), + .LI(plm_fsm_pc_counter2_reg_tx_count_qxu[4]), + .O(plm_fsm_pc_counter2_reg_tx_count_s[4]) + ); + MUXCY_L plm_fsm_pc_counter2_reg_tx_count_cry_5_ ( + .CI(plm_fsm_pc_counter2_reg_tx_count_cry[4]), + .DI(plm_fsm_pc_counter2_VCC_946), + .LO(plm_fsm_pc_counter2_reg_tx_count_cry[5]), + .S(plm_fsm_pc_counter2_reg_tx_count_qxu[5]) + ); + XORCY plm_fsm_pc_counter2_reg_tx_count_s_5_ ( + .CI(plm_fsm_pc_counter2_reg_tx_count_cry[4]), + .LI(plm_fsm_pc_counter2_reg_tx_count_qxu[5]), + .O(plm_fsm_pc_counter2_reg_tx_count_s[5]) + ); + MUXCY_L plm_fsm_pc_counter2_reg_tx_count_cry_6_ ( + .CI(plm_fsm_pc_counter2_reg_tx_count_cry[5]), + .DI(plm_fsm_pc_counter2_VCC_946), + .LO(plm_fsm_pc_counter2_reg_tx_count_cry[6]), + .S(plm_fsm_pc_counter2_reg_tx_count_qxu[6]) + ); + XORCY plm_fsm_pc_counter2_reg_tx_count_s_6_ ( + .CI(plm_fsm_pc_counter2_reg_tx_count_cry[5]), + .LI(plm_fsm_pc_counter2_reg_tx_count_qxu[6]), + .O(plm_fsm_pc_counter2_reg_tx_count_s[6]) + ); + XORCY plm_fsm_pc_counter2_reg_tx_count_s_7_ ( + .CI(plm_fsm_pc_counter2_reg_tx_count_cry[6]), + .LI(plm_fsm_pc_counter2_reg_tx_count_qxu[7]), + .O(plm_fsm_pc_counter2_reg_tx_count_s[7]) + ); + defparam plm_fsm_pc_counter2_loadable_rx_counter_N_38703_i.INIT = 4'h7; + LUT2 plm_fsm_pc_counter2_loadable_rx_counter_N_38703_i ( + .I0(plm_fsm_pc_counter2_reg_rx_count[3]), + .I1(plm_fsm_reg_state_2__356), + .O(plm_fsm_pc_counter2_N_38703_i) + ); + defparam plm_fsm_pc_counter2_loadable_rx_counter_N_38704_i.INIT = 4'hB; + LUT2 plm_fsm_pc_counter2_loadable_rx_counter_N_38704_i ( + .I0(plm_fsm_pc_counter2_reg_rx_expired_949), + .I1(plm_fsm_reg_state_2__356), + .O(plm_fsm_pc_counter2_N_38704_i) + ); + defparam plm_fsm_pc_counter2_loadable_tx_counter_un1_reg_tx_count_0_a2_0_a4_4.INIT = 16'h0001; + LUT4 plm_fsm_pc_counter2_loadable_tx_counter_un1_reg_tx_count_0_a2_0_a4_4 ( + .I0(plm_fsm_pc_counter2_reg_tx_count[0]), + .I1(plm_fsm_pc_counter2_reg_tx_count[1]), + .I2(plm_fsm_pc_counter2_reg_tx_count[2]), + .I3(plm_fsm_pc_counter2_reg_tx_count[3]), + .O(plm_fsm_pc_counter2_un1_reg_tx_count_0_a2_0_a4_4) + ); + defparam plm_fsm_pc_counter2_loadable_tx_counter_un1_reg_tx_count_0_a2_0_a4_5.INIT = 16'h0001; + LUT4 plm_fsm_pc_counter2_loadable_tx_counter_un1_reg_tx_count_0_a2_0_a4_5 ( + .I0(plm_fsm_pc_counter2_reg_tx_count[4]), + .I1(plm_fsm_pc_counter2_reg_tx_count[5]), + .I2(plm_fsm_pc_counter2_reg_tx_count[6]), + .I3(plm_fsm_pc_counter2_reg_tx_count[7]), + .O(plm_fsm_pc_counter2_un1_reg_tx_count_0_a2_0_a4_5) + ); + defparam plm_fsm_pc_counter2_N_38628_i.INIT = 4'hB; + LUT2 plm_fsm_pc_counter2_N_38628_i ( + .I0(plm_reg_sym_sent_6_), + .I1(plm_fsm_pc_counter2_un1_enable_1), + .O(plm_fsm_pc_counter2_N_38628_i_948) + ); + defparam plm_fsm_pc_counter2_un1_enable_2_i.INIT = 8'h8F; + LUT3 plm_fsm_pc_counter2_un1_enable_2_i ( + .I0(plm_fsm_pc_counter2_un1_reg_tx_count_0_a2_0_a4_4), + .I1(plm_fsm_pc_counter2_un1_reg_tx_count_0_a2_0_a4_5), + .I2(plm_fsm_un1_reg_tx_count17), + .O(plm_fsm_pc_counter2_un1_enable_2_i_950) + ); + defparam plm_fsm_pc_counter2_flagit_reg_expired_5_0_a2_0_a2_0_a4.INIT = 8'h80; + LUT3_L plm_fsm_pc_counter2_flagit_reg_expired_5_0_a2_0_a2_0_a4 ( + .I0(plm_fsm_pc_counter2_reg_rx_expired_949), + .I1(plm_fsm_pc_counter2_reg_tx_expired_951), + .I2(plm_fsm_reg_state_2__356), + .LO(plm_fsm_pc_counter2_reg_expired_5) + ); + defparam plm_fsm_pc_counter2_un1_enable_1_0_a2_0_a2_0_a4.INIT = 8'h40; + LUT3 plm_fsm_pc_counter2_un1_enable_1_0_a2_0_a2_0_a4 ( + .I0(plm_fsm_pc_counter2_reg_tx_expired_951), + .I1(plm_fsm_reg_state_2__356), + .I2(plm_fsm_reg_oneshot), + .O(plm_fsm_pc_counter2_un1_enable_1) + ); + defparam plm_fsm_pc_counter2_un1_enable_1_i.INIT = 8'hF7; + LUT3 plm_fsm_pc_counter2_un1_enable_1_i ( + .I0(plm_fsm_reg_oneshot), + .I1(plm_fsm_reg_state_2__356), + .I2(plm_fsm_pc_counter2_reg_tx_expired_951), + .O(plm_fsm_pc_counter2_un1_enable_1_i_947) + ); + FDCE plm_fsm_pc_counter2_reg_tx_count_7_ ( + .CE(plm_fsm_pc_counter2_N_38628_i_948), + .C(mgt_clk), + .D(plm_fsm_pc_counter2_reg_tx_count_s[7]), + .Q(plm_fsm_pc_counter2_reg_tx_count[7]), + .CLR(plm_rst) + ); + FDCE plm_fsm_pc_counter2_reg_tx_count_6_ ( + .CE(plm_fsm_pc_counter2_N_38628_i_948), + .C(mgt_clk), + .D(plm_fsm_pc_counter2_reg_tx_count_s[6]), + .Q(plm_fsm_pc_counter2_reg_tx_count[6]), + .CLR(plm_rst) + ); + FDCE plm_fsm_pc_counter2_reg_tx_count_5_ ( + .CE(plm_fsm_pc_counter2_N_38628_i_948), + .C(mgt_clk), + .D(plm_fsm_pc_counter2_reg_tx_count_s[5]), + .Q(plm_fsm_pc_counter2_reg_tx_count[5]), + .CLR(plm_rst) + ); + FDPE plm_fsm_pc_counter2_reg_tx_count_4_ ( + .PRE(plm_rst), + .CE(plm_fsm_pc_counter2_N_38628_i_948), + .C(mgt_clk), + .D(plm_fsm_pc_counter2_reg_tx_count_s[4]), + .Q(plm_fsm_pc_counter2_reg_tx_count[4]) + ); + FDCE plm_fsm_pc_counter2_reg_tx_count_3_ ( + .CE(plm_fsm_pc_counter2_N_38628_i_948), + .C(mgt_clk), + .D(plm_fsm_pc_counter2_reg_tx_count_s[3]), + .Q(plm_fsm_pc_counter2_reg_tx_count[3]), + .CLR(plm_rst) + ); + FDCE plm_fsm_pc_counter2_reg_tx_count_2_ ( + .CE(plm_fsm_pc_counter2_N_38628_i_948), + .C(mgt_clk), + .D(plm_fsm_pc_counter2_reg_tx_count_s[2]), + .Q(plm_fsm_pc_counter2_reg_tx_count[2]), + .CLR(plm_rst) + ); + FDCE plm_fsm_pc_counter2_reg_tx_count_1_ ( + .CE(plm_fsm_pc_counter2_N_38628_i_948), + .C(mgt_clk), + .D(plm_fsm_pc_counter2_reg_tx_count_s[1]), + .Q(plm_fsm_pc_counter2_reg_tx_count[1]), + .CLR(plm_rst) + ); + FDCE plm_fsm_pc_counter2_reg_tx_count_0_ ( + .CE(plm_fsm_pc_counter2_N_38628_i_948), + .C(mgt_clk), + .D(plm_fsm_pc_counter2_reg_tx_count_s[0]), + .Q(plm_fsm_pc_counter2_reg_tx_count[0]), + .CLR(plm_rst) + ); + FDC plm_fsm_pc_counter2_reg_expired ( + .C(mgt_clk), + .D(plm_fsm_pc_counter2_reg_expired_5), + .Q(plm_fsm_pc_cntrout2), + .CLR(plm_rst) + ); + FDPE plm_fsm_pc_counter2_reg_rx_count_3_ ( + .PRE(plm_rst), + .CE(plm_fsm_pc_counter2_N_38704_i), + .C(mgt_clk), + .D(plm_fsm_reg_state_i_2__905), + .Q(plm_fsm_pc_counter2_reg_rx_count[3]) + ); + FDCE plm_fsm_pc_counter2_reg_rx_expired ( + .CE(plm_fsm_pc_counter2_N_38703_i), + .C(mgt_clk), + .D(plm_fsm_reg_state_2__356), + .Q(plm_fsm_pc_counter2_reg_rx_expired_949), + .CLR(plm_rst) + ); + FDCE plm_fsm_pc_counter2_reg_tx_expired ( + .CE(plm_fsm_pc_counter2_un1_enable_2_i_950), + .C(mgt_clk), + .D(plm_fsm_un1_reg_tx_count17), + .Q(plm_fsm_pc_counter2_reg_tx_expired_951), + .CLR(plm_rst) + ); + defparam plm_fsm_pc_counter2_reg_tx_count_qxu_0_0_.INIT = 4'h7; + LUT2_L plm_fsm_pc_counter2_reg_tx_count_qxu_0_0_ ( + .I0(plm_fsm_pc_counter2_reg_tx_count[0]), + .I1(plm_fsm_pc_counter2_un1_enable_1), + .LO(plm_fsm_pc_counter2_reg_tx_count_qxu[0]) + ); + defparam plm_fsm_pc_counter2_reg_tx_count_qxu_0_1_.INIT = 4'h7; + LUT2_L plm_fsm_pc_counter2_reg_tx_count_qxu_0_1_ ( + .I0(plm_fsm_pc_counter2_reg_tx_count[1]), + .I1(plm_fsm_pc_counter2_un1_enable_1), + .LO(plm_fsm_pc_counter2_reg_tx_count_qxu[1]) + ); + defparam plm_fsm_pc_counter2_reg_tx_count_qxu_0_2_.INIT = 4'h7; + LUT2_L plm_fsm_pc_counter2_reg_tx_count_qxu_0_2_ ( + .I0(plm_fsm_pc_counter2_reg_tx_count[2]), + .I1(plm_fsm_pc_counter2_un1_enable_1), + .LO(plm_fsm_pc_counter2_reg_tx_count_qxu[2]) + ); + defparam plm_fsm_pc_counter2_reg_tx_count_qxu_0_3_.INIT = 4'h7; + LUT2_L plm_fsm_pc_counter2_reg_tx_count_qxu_0_3_ ( + .I0(plm_fsm_pc_counter2_reg_tx_count[3]), + .I1(plm_fsm_pc_counter2_un1_enable_1), + .LO(plm_fsm_pc_counter2_reg_tx_count_qxu[3]) + ); + defparam plm_fsm_pc_counter2_reg_tx_count_qxu_0_4_.INIT = 8'h74; + LUT3_L plm_fsm_pc_counter2_reg_tx_count_qxu_0_4_ ( + .I0(plm_fsm_pc_counter2_reg_tx_count[4]), + .I1(plm_fsm_pc_counter2_un1_enable_1), + .I2(plm_fsm_un1_reg_tx_count17), + .LO(plm_fsm_pc_counter2_reg_tx_count_qxu[4]) + ); + defparam plm_fsm_pc_counter2_reg_tx_count_qxu_0_5_.INIT = 4'h7; + LUT2_L plm_fsm_pc_counter2_reg_tx_count_qxu_0_5_ ( + .I0(plm_fsm_pc_counter2_reg_tx_count[5]), + .I1(plm_fsm_pc_counter2_un1_enable_1), + .LO(plm_fsm_pc_counter2_reg_tx_count_qxu[5]) + ); + defparam plm_fsm_pc_counter2_reg_tx_count_qxu_0_6_.INIT = 4'h7; + LUT2_L plm_fsm_pc_counter2_reg_tx_count_qxu_0_6_ ( + .I0(plm_fsm_pc_counter2_reg_tx_count[6]), + .I1(plm_fsm_pc_counter2_un1_enable_1), + .LO(plm_fsm_pc_counter2_reg_tx_count_qxu[6]) + ); + defparam plm_fsm_pc_counter2_reg_tx_count_qxu_0_7_.INIT = 4'h7; + LUT2_L plm_fsm_pc_counter2_reg_tx_count_qxu_0_7_ ( + .I0(plm_fsm_pc_counter2_reg_tx_count[7]), + .I1(plm_fsm_pc_counter2_un1_enable_1), + .LO(plm_fsm_pc_counter2_reg_tx_count_qxu[7]) + ); + VCC plm_fsm_pc_counter3_VCC ( + .P(plm_fsm_pc_counter3_VCC_952) + ); + MUXCY_L plm_fsm_pc_counter3_reg_tx_count_cry_0_ ( + .CI(plm_fsm_pc_counter3_un1_enable_1_i_953), + .DI(plm_fsm_pc_counter3_VCC_952), + .LO(plm_fsm_pc_counter3_reg_tx_count_cry[0]), + .S(plm_fsm_pc_counter3_reg_tx_count_qxu[0]) + ); + XORCY plm_fsm_pc_counter3_reg_tx_count_s_0_ ( + .CI(plm_fsm_pc_counter3_un1_enable_1_i_953), + .LI(plm_fsm_pc_counter3_reg_tx_count_qxu[0]), + .O(plm_fsm_pc_counter3_reg_tx_count_s[0]) + ); + MUXCY_L plm_fsm_pc_counter3_reg_tx_count_cry_1_ ( + .CI(plm_fsm_pc_counter3_reg_tx_count_cry[0]), + .DI(plm_fsm_pc_counter3_VCC_952), + .LO(plm_fsm_pc_counter3_reg_tx_count_cry[1]), + .S(plm_fsm_pc_counter3_reg_tx_count_qxu[1]) + ); + XORCY plm_fsm_pc_counter3_reg_tx_count_s_1_ ( + .CI(plm_fsm_pc_counter3_reg_tx_count_cry[0]), + .LI(plm_fsm_pc_counter3_reg_tx_count_qxu[1]), + .O(plm_fsm_pc_counter3_reg_tx_count_s[1]) + ); + MUXCY_L plm_fsm_pc_counter3_reg_tx_count_cry_2_ ( + .CI(plm_fsm_pc_counter3_reg_tx_count_cry[1]), + .DI(plm_fsm_pc_counter3_VCC_952), + .LO(plm_fsm_pc_counter3_reg_tx_count_cry[2]), + .S(plm_fsm_pc_counter3_reg_tx_count_qxu[2]) + ); + XORCY plm_fsm_pc_counter3_reg_tx_count_s_2_ ( + .CI(plm_fsm_pc_counter3_reg_tx_count_cry[1]), + .LI(plm_fsm_pc_counter3_reg_tx_count_qxu[2]), + .O(plm_fsm_pc_counter3_reg_tx_count_s[2]) + ); + MUXCY_L plm_fsm_pc_counter3_reg_tx_count_cry_3_ ( + .CI(plm_fsm_pc_counter3_reg_tx_count_cry[2]), + .DI(plm_fsm_pc_counter3_VCC_952), + .LO(plm_fsm_pc_counter3_reg_tx_count_cry[3]), + .S(plm_fsm_pc_counter3_reg_tx_count_qxu[3]) + ); + XORCY plm_fsm_pc_counter3_reg_tx_count_s_3_ ( + .CI(plm_fsm_pc_counter3_reg_tx_count_cry[2]), + .LI(plm_fsm_pc_counter3_reg_tx_count_qxu[3]), + .O(plm_fsm_pc_counter3_reg_tx_count_s[3]) + ); + MUXCY_L plm_fsm_pc_counter3_reg_tx_count_cry_4_ ( + .CI(plm_fsm_pc_counter3_reg_tx_count_cry[3]), + .DI(plm_fsm_pc_counter3_VCC_952), + .LO(plm_fsm_pc_counter3_reg_tx_count_cry[4]), + .S(plm_fsm_pc_counter3_reg_tx_count_qxu[4]) + ); + XORCY plm_fsm_pc_counter3_reg_tx_count_s_4_ ( + .CI(plm_fsm_pc_counter3_reg_tx_count_cry[3]), + .LI(plm_fsm_pc_counter3_reg_tx_count_qxu[4]), + .O(plm_fsm_pc_counter3_reg_tx_count_s[4]) + ); + MUXCY_L plm_fsm_pc_counter3_reg_tx_count_cry_5_ ( + .CI(plm_fsm_pc_counter3_reg_tx_count_cry[4]), + .DI(plm_fsm_pc_counter3_VCC_952), + .LO(plm_fsm_pc_counter3_reg_tx_count_cry[5]), + .S(plm_fsm_pc_counter3_reg_tx_count_qxu[5]) + ); + XORCY plm_fsm_pc_counter3_reg_tx_count_s_5_ ( + .CI(plm_fsm_pc_counter3_reg_tx_count_cry[4]), + .LI(plm_fsm_pc_counter3_reg_tx_count_qxu[5]), + .O(plm_fsm_pc_counter3_reg_tx_count_s[5]) + ); + MUXCY_L plm_fsm_pc_counter3_reg_tx_count_cry_6_ ( + .CI(plm_fsm_pc_counter3_reg_tx_count_cry[5]), + .DI(plm_fsm_pc_counter3_VCC_952), + .LO(plm_fsm_pc_counter3_reg_tx_count_cry[6]), + .S(plm_fsm_pc_counter3_reg_tx_count_qxu[6]) + ); + XORCY plm_fsm_pc_counter3_reg_tx_count_s_6_ ( + .CI(plm_fsm_pc_counter3_reg_tx_count_cry[5]), + .LI(plm_fsm_pc_counter3_reg_tx_count_qxu[6]), + .O(plm_fsm_pc_counter3_reg_tx_count_s[6]) + ); + XORCY plm_fsm_pc_counter3_reg_tx_count_s_7_ ( + .CI(plm_fsm_pc_counter3_reg_tx_count_cry[6]), + .LI(plm_fsm_pc_counter3_reg_tx_count_qxu[7]), + .O(plm_fsm_pc_counter3_reg_tx_count_s[7]) + ); + defparam plm_fsm_pc_counter3_loadable_tx_counter_reg_tx_count17_0_a3_0_a2_0_a3_0_a3.INIT = 4'h8; + LUT2 plm_fsm_pc_counter3_loadable_tx_counter_reg_tx_count17_0_a3_0_a2_0_a3_0_a3 ( + .I0(plm_fsm_reg_oneshot), + .I1(plm_fsm_reg_state_2__356), + .O(plm_fsm_un1_reg_tx_count17) + ); + defparam plm_fsm_pc_counter3_loadable_rx_counter_N_38619_i.INIT = 4'h7; + LUT2 plm_fsm_pc_counter3_loadable_rx_counter_N_38619_i ( + .I0(plm_fsm_pc_counter3_reg_rx_count[3]), + .I1(plm_fsm_reg_state_2__356), + .O(plm_fsm_pc_counter3_N_38619_i) + ); + defparam plm_fsm_pc_counter3_loadable_rx_counter_N_38630_i.INIT = 4'hB; + LUT2 plm_fsm_pc_counter3_loadable_rx_counter_N_38630_i ( + .I0(plm_fsm_pc_counter3_reg_rx_expired_955), + .I1(plm_fsm_reg_state_2__356), + .O(plm_fsm_pc_counter3_N_38630_i) + ); + defparam plm_fsm_pc_counter3_loadable_tx_counter_un1_reg_tx_count_0_a2_0_a4_4.INIT = 16'h0001; + LUT4 plm_fsm_pc_counter3_loadable_tx_counter_un1_reg_tx_count_0_a2_0_a4_4 ( + .I0(plm_fsm_pc_counter3_reg_tx_count[0]), + .I1(plm_fsm_pc_counter3_reg_tx_count[1]), + .I2(plm_fsm_pc_counter3_reg_tx_count[2]), + .I3(plm_fsm_pc_counter3_reg_tx_count[3]), + .O(plm_fsm_pc_counter3_un1_reg_tx_count_0_a2_0_a4_4) + ); + defparam plm_fsm_pc_counter3_loadable_tx_counter_un1_reg_tx_count_0_a2_0_a4_5.INIT = 16'h0001; + LUT4 plm_fsm_pc_counter3_loadable_tx_counter_un1_reg_tx_count_0_a2_0_a4_5 ( + .I0(plm_fsm_pc_counter3_reg_tx_count[4]), + .I1(plm_fsm_pc_counter3_reg_tx_count[5]), + .I2(plm_fsm_pc_counter3_reg_tx_count[6]), + .I3(plm_fsm_pc_counter3_reg_tx_count[7]), + .O(plm_fsm_pc_counter3_un1_reg_tx_count_0_a2_0_a4_5) + ); + defparam plm_fsm_pc_counter3_N_38629_i.INIT = 4'hB; + LUT2 plm_fsm_pc_counter3_N_38629_i ( + .I0(plm_reg_sym_sent_6_), + .I1(plm_fsm_pc_counter3_un1_enable_1), + .O(plm_fsm_pc_counter3_N_38629_i_954) + ); + defparam plm_fsm_pc_counter3_un1_enable_2_i.INIT = 8'h8F; + LUT3 plm_fsm_pc_counter3_un1_enable_2_i ( + .I0(plm_fsm_pc_counter3_un1_reg_tx_count_0_a2_0_a4_4), + .I1(plm_fsm_pc_counter3_un1_reg_tx_count_0_a2_0_a4_5), + .I2(plm_fsm_un1_reg_tx_count17), + .O(plm_fsm_pc_counter3_un1_enable_2_i_956) + ); + defparam plm_fsm_pc_counter3_flagit_reg_expired_5_0_a2_0_a2_0_a4.INIT = 8'h80; + LUT3_L plm_fsm_pc_counter3_flagit_reg_expired_5_0_a2_0_a2_0_a4 ( + .I0(plm_fsm_pc_counter3_reg_rx_expired_955), + .I1(plm_fsm_pc_counter3_reg_tx_expired_957), + .I2(plm_fsm_reg_state_2__356), + .LO(plm_fsm_pc_counter3_reg_expired_5) + ); + defparam plm_fsm_pc_counter3_un1_enable_1_0_a2_0_a2_0_a4.INIT = 8'h40; + LUT3 plm_fsm_pc_counter3_un1_enable_1_0_a2_0_a2_0_a4 ( + .I0(plm_fsm_pc_counter3_reg_tx_expired_957), + .I1(plm_fsm_reg_state_2__356), + .I2(plm_fsm_reg_oneshot), + .O(plm_fsm_pc_counter3_un1_enable_1) + ); + defparam plm_fsm_pc_counter3_un1_enable_1_i.INIT = 8'hF7; + LUT3 plm_fsm_pc_counter3_un1_enable_1_i ( + .I0(plm_fsm_reg_oneshot), + .I1(plm_fsm_reg_state_2__356), + .I2(plm_fsm_pc_counter3_reg_tx_expired_957), + .O(plm_fsm_pc_counter3_un1_enable_1_i_953) + ); + FDCE plm_fsm_pc_counter3_reg_tx_count_7_ ( + .CE(plm_fsm_pc_counter3_N_38629_i_954), + .C(mgt_clk), + .D(plm_fsm_pc_counter3_reg_tx_count_s[7]), + .Q(plm_fsm_pc_counter3_reg_tx_count[7]), + .CLR(plm_rst) + ); + FDCE plm_fsm_pc_counter3_reg_tx_count_6_ ( + .CE(plm_fsm_pc_counter3_N_38629_i_954), + .C(mgt_clk), + .D(plm_fsm_pc_counter3_reg_tx_count_s[6]), + .Q(plm_fsm_pc_counter3_reg_tx_count[6]), + .CLR(plm_rst) + ); + FDCE plm_fsm_pc_counter3_reg_tx_count_5_ ( + .CE(plm_fsm_pc_counter3_N_38629_i_954), + .C(mgt_clk), + .D(plm_fsm_pc_counter3_reg_tx_count_s[5]), + .Q(plm_fsm_pc_counter3_reg_tx_count[5]), + .CLR(plm_rst) + ); + FDPE plm_fsm_pc_counter3_reg_tx_count_4_ ( + .PRE(plm_rst), + .CE(plm_fsm_pc_counter3_N_38629_i_954), + .C(mgt_clk), + .D(plm_fsm_pc_counter3_reg_tx_count_s[4]), + .Q(plm_fsm_pc_counter3_reg_tx_count[4]) + ); + FDCE plm_fsm_pc_counter3_reg_tx_count_3_ ( + .CE(plm_fsm_pc_counter3_N_38629_i_954), + .C(mgt_clk), + .D(plm_fsm_pc_counter3_reg_tx_count_s[3]), + .Q(plm_fsm_pc_counter3_reg_tx_count[3]), + .CLR(plm_rst) + ); + FDCE plm_fsm_pc_counter3_reg_tx_count_2_ ( + .CE(plm_fsm_pc_counter3_N_38629_i_954), + .C(mgt_clk), + .D(plm_fsm_pc_counter3_reg_tx_count_s[2]), + .Q(plm_fsm_pc_counter3_reg_tx_count[2]), + .CLR(plm_rst) + ); + FDCE plm_fsm_pc_counter3_reg_tx_count_1_ ( + .CE(plm_fsm_pc_counter3_N_38629_i_954), + .C(mgt_clk), + .D(plm_fsm_pc_counter3_reg_tx_count_s[1]), + .Q(plm_fsm_pc_counter3_reg_tx_count[1]), + .CLR(plm_rst) + ); + FDCE plm_fsm_pc_counter3_reg_tx_count_0_ ( + .CE(plm_fsm_pc_counter3_N_38629_i_954), + .C(mgt_clk), + .D(plm_fsm_pc_counter3_reg_tx_count_s[0]), + .Q(plm_fsm_pc_counter3_reg_tx_count[0]), + .CLR(plm_rst) + ); + FDC plm_fsm_pc_counter3_reg_expired ( + .C(mgt_clk), + .D(plm_fsm_pc_counter3_reg_expired_5), + .Q(plm_fsm_pc_cntrout3), + .CLR(plm_rst) + ); + FDPE plm_fsm_pc_counter3_reg_rx_count_3_ ( + .PRE(plm_rst), + .CE(plm_fsm_pc_counter3_N_38630_i), + .C(mgt_clk), + .D(plm_fsm_reg_state_i_2__905), + .Q(plm_fsm_pc_counter3_reg_rx_count[3]) + ); + FDCE plm_fsm_pc_counter3_reg_oneshot ( + .CE(plm_fsm_reg_state_i_2__905), + .C(mgt_clk), + .D(plm_fsm_reg_state_2__356), + .Q(plm_fsm_reg_oneshot), + .CLR(plm_rst) + ); + FDCE plm_fsm_pc_counter3_reg_rx_expired ( + .CE(plm_fsm_pc_counter3_N_38619_i), + .C(mgt_clk), + .D(plm_fsm_reg_state_2__356), + .Q(plm_fsm_pc_counter3_reg_rx_expired_955), + .CLR(plm_rst) + ); + FDCE plm_fsm_pc_counter3_reg_tx_expired ( + .CE(plm_fsm_pc_counter3_un1_enable_2_i_956), + .C(mgt_clk), + .D(plm_fsm_un1_reg_tx_count17), + .Q(plm_fsm_pc_counter3_reg_tx_expired_957), + .CLR(plm_rst) + ); + defparam plm_fsm_pc_counter3_reg_tx_count_qxu_0_0_.INIT = 4'h7; + LUT2_L plm_fsm_pc_counter3_reg_tx_count_qxu_0_0_ ( + .I0(plm_fsm_pc_counter3_reg_tx_count[0]), + .I1(plm_fsm_pc_counter3_un1_enable_1), + .LO(plm_fsm_pc_counter3_reg_tx_count_qxu[0]) + ); + defparam plm_fsm_pc_counter3_reg_tx_count_qxu_0_1_.INIT = 4'h7; + LUT2_L plm_fsm_pc_counter3_reg_tx_count_qxu_0_1_ ( + .I0(plm_fsm_pc_counter3_reg_tx_count[1]), + .I1(plm_fsm_pc_counter3_un1_enable_1), + .LO(plm_fsm_pc_counter3_reg_tx_count_qxu[1]) + ); + defparam plm_fsm_pc_counter3_reg_tx_count_qxu_0_2_.INIT = 4'h7; + LUT2_L plm_fsm_pc_counter3_reg_tx_count_qxu_0_2_ ( + .I0(plm_fsm_pc_counter3_reg_tx_count[2]), + .I1(plm_fsm_pc_counter3_un1_enable_1), + .LO(plm_fsm_pc_counter3_reg_tx_count_qxu[2]) + ); + defparam plm_fsm_pc_counter3_reg_tx_count_qxu_0_3_.INIT = 4'h7; + LUT2_L plm_fsm_pc_counter3_reg_tx_count_qxu_0_3_ ( + .I0(plm_fsm_pc_counter3_reg_tx_count[3]), + .I1(plm_fsm_pc_counter3_un1_enable_1), + .LO(plm_fsm_pc_counter3_reg_tx_count_qxu[3]) + ); + defparam plm_fsm_pc_counter3_reg_tx_count_qxu_0_4_.INIT = 8'h74; + LUT3_L plm_fsm_pc_counter3_reg_tx_count_qxu_0_4_ ( + .I0(plm_fsm_pc_counter3_reg_tx_count[4]), + .I1(plm_fsm_pc_counter3_un1_enable_1), + .I2(plm_fsm_un1_reg_tx_count17), + .LO(plm_fsm_pc_counter3_reg_tx_count_qxu[4]) + ); + defparam plm_fsm_pc_counter3_reg_tx_count_qxu_0_5_.INIT = 4'h7; + LUT2_L plm_fsm_pc_counter3_reg_tx_count_qxu_0_5_ ( + .I0(plm_fsm_pc_counter3_reg_tx_count[5]), + .I1(plm_fsm_pc_counter3_un1_enable_1), + .LO(plm_fsm_pc_counter3_reg_tx_count_qxu[5]) + ); + defparam plm_fsm_pc_counter3_reg_tx_count_qxu_0_6_.INIT = 4'h7; + LUT2_L plm_fsm_pc_counter3_reg_tx_count_qxu_0_6_ ( + .I0(plm_fsm_pc_counter3_reg_tx_count[6]), + .I1(plm_fsm_pc_counter3_un1_enable_1), + .LO(plm_fsm_pc_counter3_reg_tx_count_qxu[6]) + ); + defparam plm_fsm_pc_counter3_reg_tx_count_qxu_0_7_.INIT = 4'h7; + LUT2_L plm_fsm_pc_counter3_reg_tx_count_qxu_0_7_ ( + .I0(plm_fsm_pc_counter3_reg_tx_count[7]), + .I1(plm_fsm_pc_counter3_un1_enable_1), + .LO(plm_fsm_pc_counter3_reg_tx_count_qxu[7]) + ); + GND plm_fsm_cls_timer_GND ( + .G(plm_fsm_cls_timer_GND_958) + ); + MUXCY_L plm_fsm_cls_timer_reg_count_cry_0_ ( + .CI(plm_fsm_cls_timer_un1_reg_state_i_i_959), + .DI(plm_fsm_cls_timer_GND_958), + .LO(plm_fsm_cls_timer_reg_count_cry[0]), + .S(plm_fsm_cls_timer_reg_count_qxu[0]) + ); + XORCY plm_fsm_cls_timer_reg_count_s_0_ ( + .CI(plm_fsm_cls_timer_un1_reg_state_i_i_959), + .LI(plm_fsm_cls_timer_reg_count_qxu[0]), + .O(plm_fsm_cls_timer_reg_count_s[0]) + ); + MUXCY_L plm_fsm_cls_timer_reg_count_cry_1_ ( + .CI(plm_fsm_cls_timer_reg_count_cry[0]), + .DI(plm_fsm_cls_timer_GND_958), + .LO(plm_fsm_cls_timer_reg_count_cry[1]), + .S(plm_fsm_cls_timer_reg_count_qxu[1]) + ); + XORCY plm_fsm_cls_timer_reg_count_s_1_ ( + .CI(plm_fsm_cls_timer_reg_count_cry[0]), + .LI(plm_fsm_cls_timer_reg_count_qxu[1]), + .O(plm_fsm_cls_timer_reg_count_s[1]) + ); + MUXCY_L plm_fsm_cls_timer_reg_count_cry_2_ ( + .CI(plm_fsm_cls_timer_reg_count_cry[1]), + .DI(plm_fsm_cls_timer_GND_958), + .LO(plm_fsm_cls_timer_reg_count_cry[2]), + .S(plm_fsm_cls_timer_reg_count_qxu[2]) + ); + XORCY plm_fsm_cls_timer_reg_count_s_2_ ( + .CI(plm_fsm_cls_timer_reg_count_cry[1]), + .LI(plm_fsm_cls_timer_reg_count_qxu[2]), + .O(plm_fsm_cls_timer_reg_count_s[2]) + ); + MUXCY_L plm_fsm_cls_timer_reg_count_cry_3_ ( + .CI(plm_fsm_cls_timer_reg_count_cry[2]), + .DI(plm_fsm_cls_timer_GND_958), + .LO(plm_fsm_cls_timer_reg_count_cry[3]), + .S(plm_fsm_cls_timer_reg_count_qxu[3]) + ); + XORCY plm_fsm_cls_timer_reg_count_s_3_ ( + .CI(plm_fsm_cls_timer_reg_count_cry[2]), + .LI(plm_fsm_cls_timer_reg_count_qxu[3]), + .O(plm_fsm_cls_timer_reg_count_s[3]) + ); + MUXCY_L plm_fsm_cls_timer_reg_count_cry_4_ ( + .CI(plm_fsm_cls_timer_reg_count_cry[3]), + .DI(plm_fsm_cls_timer_GND_958), + .LO(plm_fsm_cls_timer_reg_count_cry[4]), + .S(plm_fsm_cls_timer_reg_count_qxu[4]) + ); + XORCY plm_fsm_cls_timer_reg_count_s_4_ ( + .CI(plm_fsm_cls_timer_reg_count_cry[3]), + .LI(plm_fsm_cls_timer_reg_count_qxu[4]), + .O(plm_fsm_cls_timer_reg_count_s[4]) + ); + MUXCY_L plm_fsm_cls_timer_reg_count_cry_5_ ( + .CI(plm_fsm_cls_timer_reg_count_cry[4]), + .DI(plm_fsm_cls_timer_GND_958), + .LO(plm_fsm_cls_timer_reg_count_cry[5]), + .S(plm_fsm_cls_timer_reg_count_qxu[5]) + ); + XORCY plm_fsm_cls_timer_reg_count_s_5_ ( + .CI(plm_fsm_cls_timer_reg_count_cry[4]), + .LI(plm_fsm_cls_timer_reg_count_qxu[5]), + .O(plm_fsm_cls_timer_reg_count_s[5]) + ); + MUXCY_L plm_fsm_cls_timer_reg_count_cry_6_ ( + .CI(plm_fsm_cls_timer_reg_count_cry[5]), + .DI(plm_fsm_cls_timer_GND_958), + .LO(plm_fsm_cls_timer_reg_count_cry[6]), + .S(plm_fsm_cls_timer_reg_count_qxu[6]) + ); + XORCY plm_fsm_cls_timer_reg_count_s_6_ ( + .CI(plm_fsm_cls_timer_reg_count_cry[5]), + .LI(plm_fsm_cls_timer_reg_count_qxu[6]), + .O(plm_fsm_cls_timer_reg_count_s[6]) + ); + MUXCY_L plm_fsm_cls_timer_reg_count_cry_7_ ( + .CI(plm_fsm_cls_timer_reg_count_cry[6]), + .DI(plm_fsm_cls_timer_GND_958), + .LO(plm_fsm_cls_timer_reg_count_cry[7]), + .S(plm_fsm_cls_timer_reg_count_qxu[7]) + ); + XORCY plm_fsm_cls_timer_reg_count_s_7_ ( + .CI(plm_fsm_cls_timer_reg_count_cry[6]), + .LI(plm_fsm_cls_timer_reg_count_qxu[7]), + .O(plm_fsm_cls_timer_reg_count_s[7]) + ); + MUXCY_L plm_fsm_cls_timer_reg_count_cry_8_ ( + .CI(plm_fsm_cls_timer_reg_count_cry[7]), + .DI(plm_fsm_cls_timer_GND_958), + .LO(plm_fsm_cls_timer_reg_count_cry[8]), + .S(plm_fsm_cls_timer_reg_count_qxu[8]) + ); + XORCY plm_fsm_cls_timer_reg_count_s_8_ ( + .CI(plm_fsm_cls_timer_reg_count_cry[7]), + .LI(plm_fsm_cls_timer_reg_count_qxu[8]), + .O(plm_fsm_cls_timer_reg_count_s[8]) + ); + MUXCY_L plm_fsm_cls_timer_reg_count_cry_9_ ( + .CI(plm_fsm_cls_timer_reg_count_cry[8]), + .DI(plm_fsm_cls_timer_GND_958), + .LO(plm_fsm_cls_timer_reg_count_cry[9]), + .S(plm_fsm_cls_timer_reg_count_qxu[9]) + ); + XORCY plm_fsm_cls_timer_reg_count_s_9_ ( + .CI(plm_fsm_cls_timer_reg_count_cry[8]), + .LI(plm_fsm_cls_timer_reg_count_qxu[9]), + .O(plm_fsm_cls_timer_reg_count_s[9]) + ); + MUXCY_L plm_fsm_cls_timer_reg_count_cry_10_ ( + .CI(plm_fsm_cls_timer_reg_count_cry[9]), + .DI(plm_fsm_cls_timer_GND_958), + .LO(plm_fsm_cls_timer_reg_count_cry[10]), + .S(plm_fsm_cls_timer_reg_count_qxu[10]) + ); + XORCY plm_fsm_cls_timer_reg_count_s_10_ ( + .CI(plm_fsm_cls_timer_reg_count_cry[9]), + .LI(plm_fsm_cls_timer_reg_count_qxu[10]), + .O(plm_fsm_cls_timer_reg_count_s[10]) + ); + MUXCY_L plm_fsm_cls_timer_reg_count_cry_11_ ( + .CI(plm_fsm_cls_timer_reg_count_cry[10]), + .DI(plm_fsm_cls_timer_GND_958), + .LO(plm_fsm_cls_timer_reg_count_cry[11]), + .S(plm_fsm_cls_timer_reg_count_qxu[11]) + ); + XORCY plm_fsm_cls_timer_reg_count_s_11_ ( + .CI(plm_fsm_cls_timer_reg_count_cry[10]), + .LI(plm_fsm_cls_timer_reg_count_qxu[11]), + .O(plm_fsm_cls_timer_reg_count_s[11]) + ); + MUXCY_L plm_fsm_cls_timer_reg_count_cry_12_ ( + .CI(plm_fsm_cls_timer_reg_count_cry[11]), + .DI(plm_fsm_cls_timer_GND_958), + .LO(plm_fsm_cls_timer_reg_count_cry[12]), + .S(plm_fsm_cls_timer_reg_count_qxu[12]) + ); + XORCY plm_fsm_cls_timer_reg_count_s_12_ ( + .CI(plm_fsm_cls_timer_reg_count_cry[11]), + .LI(plm_fsm_cls_timer_reg_count_qxu[12]), + .O(plm_fsm_cls_timer_reg_count_s[12]) + ); + MUXCY_L plm_fsm_cls_timer_reg_count_cry_13_ ( + .CI(plm_fsm_cls_timer_reg_count_cry[12]), + .DI(plm_fsm_cls_timer_GND_958), + .LO(plm_fsm_cls_timer_reg_count_cry[13]), + .S(plm_fsm_cls_timer_reg_count_qxu[13]) + ); + XORCY plm_fsm_cls_timer_reg_count_s_13_ ( + .CI(plm_fsm_cls_timer_reg_count_cry[12]), + .LI(plm_fsm_cls_timer_reg_count_qxu[13]), + .O(plm_fsm_cls_timer_reg_count_s[13]) + ); + MUXCY_L plm_fsm_cls_timer_reg_count_cry_14_ ( + .CI(plm_fsm_cls_timer_reg_count_cry[13]), + .DI(plm_fsm_cls_timer_GND_958), + .LO(plm_fsm_cls_timer_reg_count_cry[14]), + .S(plm_fsm_cls_timer_reg_count_qxu[14]) + ); + XORCY plm_fsm_cls_timer_reg_count_s_14_ ( + .CI(plm_fsm_cls_timer_reg_count_cry[13]), + .LI(plm_fsm_cls_timer_reg_count_qxu[14]), + .O(plm_fsm_cls_timer_reg_count_s[14]) + ); + MUXCY_L plm_fsm_cls_timer_reg_count_cry_15_ ( + .CI(plm_fsm_cls_timer_reg_count_cry[14]), + .DI(plm_fsm_cls_timer_GND_958), + .LO(plm_fsm_cls_timer_reg_count_cry[15]), + .S(plm_fsm_cls_timer_reg_count_qxu[15]) + ); + XORCY plm_fsm_cls_timer_reg_count_s_15_ ( + .CI(plm_fsm_cls_timer_reg_count_cry[14]), + .LI(plm_fsm_cls_timer_reg_count_qxu[15]), + .O(plm_fsm_cls_timer_reg_count_s[15]) + ); + MUXCY_L plm_fsm_cls_timer_reg_count_cry_16_ ( + .CI(plm_fsm_cls_timer_reg_count_cry[15]), + .DI(plm_fsm_cls_timer_GND_958), + .LO(plm_fsm_cls_timer_reg_count_cry[16]), + .S(plm_fsm_cls_timer_reg_count_qxu[16]) + ); + XORCY plm_fsm_cls_timer_reg_count_s_16_ ( + .CI(plm_fsm_cls_timer_reg_count_cry[15]), + .LI(plm_fsm_cls_timer_reg_count_qxu[16]), + .O(plm_fsm_cls_timer_reg_count_s[16]) + ); + MUXCY_L plm_fsm_cls_timer_reg_count_cry_17_ ( + .CI(plm_fsm_cls_timer_reg_count_cry[16]), + .DI(plm_fsm_cls_timer_GND_958), + .LO(plm_fsm_cls_timer_reg_count_cry[17]), + .S(plm_fsm_cls_timer_reg_count_qxu[17]) + ); + XORCY plm_fsm_cls_timer_reg_count_s_17_ ( + .CI(plm_fsm_cls_timer_reg_count_cry[16]), + .LI(plm_fsm_cls_timer_reg_count_qxu[17]), + .O(plm_fsm_cls_timer_reg_count_s[17]) + ); + MUXCY_L plm_fsm_cls_timer_reg_count_cry_18_ ( + .CI(plm_fsm_cls_timer_reg_count_cry[17]), + .DI(plm_fsm_cls_timer_GND_958), + .LO(plm_fsm_cls_timer_reg_count_cry[18]), + .S(plm_fsm_cls_timer_reg_count_qxu[18]) + ); + XORCY plm_fsm_cls_timer_reg_count_s_18_ ( + .CI(plm_fsm_cls_timer_reg_count_cry[17]), + .LI(plm_fsm_cls_timer_reg_count_qxu[18]), + .O(plm_fsm_cls_timer_reg_count_s[18]) + ); + MUXCY_L plm_fsm_cls_timer_reg_count_cry_19_ ( + .CI(plm_fsm_cls_timer_reg_count_cry[18]), + .DI(plm_fsm_cls_timer_GND_958), + .LO(plm_fsm_cls_timer_reg_count_cry[19]), + .S(plm_fsm_cls_timer_reg_count_qxu[19]) + ); + XORCY plm_fsm_cls_timer_reg_count_s_19_ ( + .CI(plm_fsm_cls_timer_reg_count_cry[18]), + .LI(plm_fsm_cls_timer_reg_count_qxu[19]), + .O(plm_fsm_cls_timer_reg_count_s[19]) + ); + MUXCY_L plm_fsm_cls_timer_reg_count_cry_20_ ( + .CI(plm_fsm_cls_timer_reg_count_cry[19]), + .DI(plm_fsm_cls_timer_GND_958), + .LO(plm_fsm_cls_timer_reg_count_cry[20]), + .S(plm_fsm_cls_timer_reg_count_qxu[20]) + ); + XORCY plm_fsm_cls_timer_reg_count_s_20_ ( + .CI(plm_fsm_cls_timer_reg_count_cry[19]), + .LI(plm_fsm_cls_timer_reg_count_qxu[20]), + .O(plm_fsm_cls_timer_reg_count_s[20]) + ); + MUXCY_L plm_fsm_cls_timer_reg_count_cry_21_ ( + .CI(plm_fsm_cls_timer_reg_count_cry[20]), + .DI(plm_fsm_cls_timer_GND_958), + .LO(plm_fsm_cls_timer_reg_count_cry[21]), + .S(plm_fsm_cls_timer_reg_count_qxu[21]) + ); + XORCY plm_fsm_cls_timer_reg_count_s_21_ ( + .CI(plm_fsm_cls_timer_reg_count_cry[20]), + .LI(plm_fsm_cls_timer_reg_count_qxu[21]), + .O(plm_fsm_cls_timer_reg_count_s[21]) + ); + XORCY plm_fsm_cls_timer_reg_count_s_22_ ( + .CI(plm_fsm_cls_timer_reg_count_cry[21]), + .LI(plm_fsm_cls_timer_reg_count_qxu[22]), + .O(plm_fsm_cls_timer_reg_count_s[22]) + ); + defparam plm_fsm_cls_timer_count_i_m3_i_m3_i_m3_0_20_.INIT = 8'hD8; + LUT3_L plm_fsm_cls_timer_count_i_m3_i_m3_i_m3_0_20_ ( + .I0(cfg_cfg_5072[507]), + .I1(plm_fsm_cls_timer_reg_count[12]), + .I2(plm_fsm_cls_timer_reg_count[20]), + .LO(plm_fsm_cls_timer_N_51461) + ); + defparam plm_fsm_cls_timer_un1_reg_state_i_i.INIT = 4'hE; + LUT2 plm_fsm_cls_timer_un1_reg_state_i_i ( + .I0(plm_fsm_reg_state_3__878), + .I1(plm_fsm_reg_state_4__877), + .O(plm_fsm_cls_timer_un1_reg_state_i_i_959) + ); + defparam plm_fsm_cls_timer_un3_expired_24ms_0_a2_0_a4.INIT = 16'hA280; + LUT4_L plm_fsm_cls_timer_un3_expired_24ms_0_a2_0_a4 ( + .I0(plm_fsm_cls_timer_N_51461), + .I1(cfg_cfg_5072[507]), + .I2(plm_fsm_cls_timer_reg_count[13]), + .I3(plm_fsm_cls_timer_reg_count[21]), + .LO(plm_fsm_cls_timer_N_51383) + ); + defparam plm_fsm_cls_timer_un1_expired_24ms_0_a2_0_a4.INIT = 16'h0415; + LUT4 plm_fsm_cls_timer_un1_expired_24ms_0_a2_0_a4 ( + .I0(plm_fsm_cls_timer_N_51383), + .I1(cfg_cfg_5072[507]), + .I2(plm_fsm_cls_timer_reg_count[14]), + .I3(plm_fsm_cls_timer_reg_count[22]), + .O(plm_fsm_N_51384) + ); + defparam plm_fsm_cls_timer_expired_i_0.INIT = 8'h54; + LUT3 plm_fsm_cls_timer_expired_i_0 ( + .I0(plm_fsm_N_51384), + .I1(plm_fsm_reg_state_3__878), + .I2(plm_fsm_reg_state_4__877), + .O(plm_fsm_N_25635_i) + ); + FDC plm_fsm_cls_timer_reg_count_22_ ( + .C(mgt_clk), + .D(plm_fsm_cls_timer_reg_count_s[22]), + .Q(plm_fsm_cls_timer_reg_count[22]), + .CLR(plm_rst) + ); + FDC plm_fsm_cls_timer_reg_count_21_ ( + .C(mgt_clk), + .D(plm_fsm_cls_timer_reg_count_s[21]), + .Q(plm_fsm_cls_timer_reg_count[21]), + .CLR(plm_rst) + ); + FDC plm_fsm_cls_timer_reg_count_20_ ( + .C(mgt_clk), + .D(plm_fsm_cls_timer_reg_count_s[20]), + .Q(plm_fsm_cls_timer_reg_count[20]), + .CLR(plm_rst) + ); + FDC plm_fsm_cls_timer_reg_count_19_ ( + .C(mgt_clk), + .D(plm_fsm_cls_timer_reg_count_s[19]), + .Q(plm_fsm_cls_timer_reg_count[19]), + .CLR(plm_rst) + ); + FDC plm_fsm_cls_timer_reg_count_18_ ( + .C(mgt_clk), + .D(plm_fsm_cls_timer_reg_count_s[18]), + .Q(plm_fsm_cls_timer_reg_count[18]), + .CLR(plm_rst) + ); + FDC plm_fsm_cls_timer_reg_count_17_ ( + .C(mgt_clk), + .D(plm_fsm_cls_timer_reg_count_s[17]), + .Q(plm_fsm_cls_timer_reg_count[17]), + .CLR(plm_rst) + ); + FDC plm_fsm_cls_timer_reg_count_16_ ( + .C(mgt_clk), + .D(plm_fsm_cls_timer_reg_count_s[16]), + .Q(plm_fsm_cls_timer_reg_count[16]), + .CLR(plm_rst) + ); + FDC plm_fsm_cls_timer_reg_count_15_ ( + .C(mgt_clk), + .D(plm_fsm_cls_timer_reg_count_s[15]), + .Q(plm_fsm_cls_timer_reg_count[15]), + .CLR(plm_rst) + ); + FDC plm_fsm_cls_timer_reg_count_14_ ( + .C(mgt_clk), + .D(plm_fsm_cls_timer_reg_count_s[14]), + .Q(plm_fsm_cls_timer_reg_count[14]), + .CLR(plm_rst) + ); + FDC plm_fsm_cls_timer_reg_count_13_ ( + .C(mgt_clk), + .D(plm_fsm_cls_timer_reg_count_s[13]), + .Q(plm_fsm_cls_timer_reg_count[13]), + .CLR(plm_rst) + ); + FDC plm_fsm_cls_timer_reg_count_12_ ( + .C(mgt_clk), + .D(plm_fsm_cls_timer_reg_count_s[12]), + .Q(plm_fsm_cls_timer_reg_count[12]), + .CLR(plm_rst) + ); + FDC plm_fsm_cls_timer_reg_count_11_ ( + .C(mgt_clk), + .D(plm_fsm_cls_timer_reg_count_s[11]), + .Q(plm_fsm_cls_timer_reg_count[11]), + .CLR(plm_rst) + ); + FDC plm_fsm_cls_timer_reg_count_10_ ( + .C(mgt_clk), + .D(plm_fsm_cls_timer_reg_count_s[10]), + .Q(plm_fsm_cls_timer_reg_count[10]), + .CLR(plm_rst) + ); + FDC plm_fsm_cls_timer_reg_count_9_ ( + .C(mgt_clk), + .D(plm_fsm_cls_timer_reg_count_s[9]), + .Q(plm_fsm_cls_timer_reg_count[9]), + .CLR(plm_rst) + ); + FDC plm_fsm_cls_timer_reg_count_8_ ( + .C(mgt_clk), + .D(plm_fsm_cls_timer_reg_count_s[8]), + .Q(plm_fsm_cls_timer_reg_count[8]), + .CLR(plm_rst) + ); + FDC plm_fsm_cls_timer_reg_count_7_ ( + .C(mgt_clk), + .D(plm_fsm_cls_timer_reg_count_s[7]), + .Q(plm_fsm_cls_timer_reg_count[7]), + .CLR(plm_rst) + ); + FDC plm_fsm_cls_timer_reg_count_6_ ( + .C(mgt_clk), + .D(plm_fsm_cls_timer_reg_count_s[6]), + .Q(plm_fsm_cls_timer_reg_count[6]), + .CLR(plm_rst) + ); + FDC plm_fsm_cls_timer_reg_count_5_ ( + .C(mgt_clk), + .D(plm_fsm_cls_timer_reg_count_s[5]), + .Q(plm_fsm_cls_timer_reg_count[5]), + .CLR(plm_rst) + ); + FDC plm_fsm_cls_timer_reg_count_4_ ( + .C(mgt_clk), + .D(plm_fsm_cls_timer_reg_count_s[4]), + .Q(plm_fsm_cls_timer_reg_count[4]), + .CLR(plm_rst) + ); + FDC plm_fsm_cls_timer_reg_count_3_ ( + .C(mgt_clk), + .D(plm_fsm_cls_timer_reg_count_s[3]), + .Q(plm_fsm_cls_timer_reg_count[3]), + .CLR(plm_rst) + ); + FDC plm_fsm_cls_timer_reg_count_2_ ( + .C(mgt_clk), + .D(plm_fsm_cls_timer_reg_count_s[2]), + .Q(plm_fsm_cls_timer_reg_count[2]), + .CLR(plm_rst) + ); + FDC plm_fsm_cls_timer_reg_count_1_ ( + .C(mgt_clk), + .D(plm_fsm_cls_timer_reg_count_s[1]), + .Q(plm_fsm_cls_timer_reg_count[1]), + .CLR(plm_rst) + ); + FDC plm_fsm_cls_timer_reg_count_0_ ( + .C(mgt_clk), + .D(plm_fsm_cls_timer_reg_count_s[0]), + .Q(plm_fsm_cls_timer_reg_count[0]), + .CLR(plm_rst) + ); + defparam plm_fsm_cls_timer_reg_count_qxu_0_0_.INIT = 4'h8; + LUT2_L plm_fsm_cls_timer_reg_count_qxu_0_0_ ( + .I0(plm_fsm_cls_timer_reg_count[0]), + .I1(plm_fsm_cls_timer_un1_reg_state_i_i_959), + .LO(plm_fsm_cls_timer_reg_count_qxu[0]) + ); + defparam plm_fsm_cls_timer_reg_count_qxu_0_1_.INIT = 4'h8; + LUT2_L plm_fsm_cls_timer_reg_count_qxu_0_1_ ( + .I0(plm_fsm_cls_timer_reg_count[1]), + .I1(plm_fsm_cls_timer_un1_reg_state_i_i_959), + .LO(plm_fsm_cls_timer_reg_count_qxu[1]) + ); + defparam plm_fsm_cls_timer_reg_count_qxu_0_2_.INIT = 4'h8; + LUT2_L plm_fsm_cls_timer_reg_count_qxu_0_2_ ( + .I0(plm_fsm_cls_timer_reg_count[2]), + .I1(plm_fsm_cls_timer_un1_reg_state_i_i_959), + .LO(plm_fsm_cls_timer_reg_count_qxu[2]) + ); + defparam plm_fsm_cls_timer_reg_count_qxu_0_3_.INIT = 4'h8; + LUT2_L plm_fsm_cls_timer_reg_count_qxu_0_3_ ( + .I0(plm_fsm_cls_timer_reg_count[3]), + .I1(plm_fsm_cls_timer_un1_reg_state_i_i_959), + .LO(plm_fsm_cls_timer_reg_count_qxu[3]) + ); + defparam plm_fsm_cls_timer_reg_count_qxu_0_4_.INIT = 4'h8; + LUT2_L plm_fsm_cls_timer_reg_count_qxu_0_4_ ( + .I0(plm_fsm_cls_timer_reg_count[4]), + .I1(plm_fsm_cls_timer_un1_reg_state_i_i_959), + .LO(plm_fsm_cls_timer_reg_count_qxu[4]) + ); + defparam plm_fsm_cls_timer_reg_count_qxu_0_5_.INIT = 4'h8; + LUT2_L plm_fsm_cls_timer_reg_count_qxu_0_5_ ( + .I0(plm_fsm_cls_timer_reg_count[5]), + .I1(plm_fsm_cls_timer_un1_reg_state_i_i_959), + .LO(plm_fsm_cls_timer_reg_count_qxu[5]) + ); + defparam plm_fsm_cls_timer_reg_count_qxu_0_6_.INIT = 4'h8; + LUT2_L plm_fsm_cls_timer_reg_count_qxu_0_6_ ( + .I0(plm_fsm_cls_timer_reg_count[6]), + .I1(plm_fsm_cls_timer_un1_reg_state_i_i_959), + .LO(plm_fsm_cls_timer_reg_count_qxu[6]) + ); + defparam plm_fsm_cls_timer_reg_count_qxu_0_7_.INIT = 4'h8; + LUT2_L plm_fsm_cls_timer_reg_count_qxu_0_7_ ( + .I0(plm_fsm_cls_timer_reg_count[7]), + .I1(plm_fsm_cls_timer_un1_reg_state_i_i_959), + .LO(plm_fsm_cls_timer_reg_count_qxu[7]) + ); + defparam plm_fsm_cls_timer_reg_count_qxu_0_8_.INIT = 4'h8; + LUT2_L plm_fsm_cls_timer_reg_count_qxu_0_8_ ( + .I0(plm_fsm_cls_timer_reg_count[8]), + .I1(plm_fsm_cls_timer_un1_reg_state_i_i_959), + .LO(plm_fsm_cls_timer_reg_count_qxu[8]) + ); + defparam plm_fsm_cls_timer_reg_count_qxu_0_9_.INIT = 4'h8; + LUT2_L plm_fsm_cls_timer_reg_count_qxu_0_9_ ( + .I0(plm_fsm_cls_timer_reg_count[9]), + .I1(plm_fsm_cls_timer_un1_reg_state_i_i_959), + .LO(plm_fsm_cls_timer_reg_count_qxu[9]) + ); + defparam plm_fsm_cls_timer_reg_count_qxu_0_10_.INIT = 4'h8; + LUT2_L plm_fsm_cls_timer_reg_count_qxu_0_10_ ( + .I0(plm_fsm_cls_timer_reg_count[10]), + .I1(plm_fsm_cls_timer_un1_reg_state_i_i_959), + .LO(plm_fsm_cls_timer_reg_count_qxu[10]) + ); + defparam plm_fsm_cls_timer_reg_count_qxu_0_11_.INIT = 4'h8; + LUT2_L plm_fsm_cls_timer_reg_count_qxu_0_11_ ( + .I0(plm_fsm_cls_timer_reg_count[11]), + .I1(plm_fsm_cls_timer_un1_reg_state_i_i_959), + .LO(plm_fsm_cls_timer_reg_count_qxu[11]) + ); + defparam plm_fsm_cls_timer_reg_count_qxu_0_12_.INIT = 4'h8; + LUT2_L plm_fsm_cls_timer_reg_count_qxu_0_12_ ( + .I0(plm_fsm_cls_timer_reg_count[12]), + .I1(plm_fsm_cls_timer_un1_reg_state_i_i_959), + .LO(plm_fsm_cls_timer_reg_count_qxu[12]) + ); + defparam plm_fsm_cls_timer_reg_count_qxu_0_13_.INIT = 4'h8; + LUT2_L plm_fsm_cls_timer_reg_count_qxu_0_13_ ( + .I0(plm_fsm_cls_timer_reg_count[13]), + .I1(plm_fsm_cls_timer_un1_reg_state_i_i_959), + .LO(plm_fsm_cls_timer_reg_count_qxu[13]) + ); + defparam plm_fsm_cls_timer_reg_count_qxu_0_14_.INIT = 4'h8; + LUT2_L plm_fsm_cls_timer_reg_count_qxu_0_14_ ( + .I0(plm_fsm_cls_timer_reg_count[14]), + .I1(plm_fsm_cls_timer_un1_reg_state_i_i_959), + .LO(plm_fsm_cls_timer_reg_count_qxu[14]) + ); + defparam plm_fsm_cls_timer_reg_count_qxu_0_15_.INIT = 4'h8; + LUT2_L plm_fsm_cls_timer_reg_count_qxu_0_15_ ( + .I0(plm_fsm_cls_timer_reg_count[15]), + .I1(plm_fsm_cls_timer_un1_reg_state_i_i_959), + .LO(plm_fsm_cls_timer_reg_count_qxu[15]) + ); + defparam plm_fsm_cls_timer_reg_count_qxu_0_16_.INIT = 4'h8; + LUT2_L plm_fsm_cls_timer_reg_count_qxu_0_16_ ( + .I0(plm_fsm_cls_timer_reg_count[16]), + .I1(plm_fsm_cls_timer_un1_reg_state_i_i_959), + .LO(plm_fsm_cls_timer_reg_count_qxu[16]) + ); + defparam plm_fsm_cls_timer_reg_count_qxu_0_17_.INIT = 4'h8; + LUT2_L plm_fsm_cls_timer_reg_count_qxu_0_17_ ( + .I0(plm_fsm_cls_timer_reg_count[17]), + .I1(plm_fsm_cls_timer_un1_reg_state_i_i_959), + .LO(plm_fsm_cls_timer_reg_count_qxu[17]) + ); + defparam plm_fsm_cls_timer_reg_count_qxu_0_18_.INIT = 4'h8; + LUT2_L plm_fsm_cls_timer_reg_count_qxu_0_18_ ( + .I0(plm_fsm_cls_timer_reg_count[18]), + .I1(plm_fsm_cls_timer_un1_reg_state_i_i_959), + .LO(plm_fsm_cls_timer_reg_count_qxu[18]) + ); + defparam plm_fsm_cls_timer_reg_count_qxu_0_19_.INIT = 4'h8; + LUT2_L plm_fsm_cls_timer_reg_count_qxu_0_19_ ( + .I0(plm_fsm_cls_timer_reg_count[19]), + .I1(plm_fsm_cls_timer_un1_reg_state_i_i_959), + .LO(plm_fsm_cls_timer_reg_count_qxu[19]) + ); + defparam plm_fsm_cls_timer_reg_count_qxu_0_20_.INIT = 4'h8; + LUT2_L plm_fsm_cls_timer_reg_count_qxu_0_20_ ( + .I0(plm_fsm_cls_timer_reg_count[20]), + .I1(plm_fsm_cls_timer_un1_reg_state_i_i_959), + .LO(plm_fsm_cls_timer_reg_count_qxu[20]) + ); + defparam plm_fsm_cls_timer_reg_count_qxu_0_21_.INIT = 4'h8; + LUT2_L plm_fsm_cls_timer_reg_count_qxu_0_21_ ( + .I0(plm_fsm_cls_timer_reg_count[21]), + .I1(plm_fsm_cls_timer_un1_reg_state_i_i_959), + .LO(plm_fsm_cls_timer_reg_count_qxu[21]) + ); + defparam plm_fsm_cls_timer_reg_count_qxu_0_22_.INIT = 4'h8; + LUT2_L plm_fsm_cls_timer_reg_count_qxu_0_22_ ( + .I0(plm_fsm_cls_timer_reg_count[22]), + .I1(plm_fsm_cls_timer_un1_reg_state_i_i_959), + .LO(plm_fsm_cls_timer_reg_count_qxu[22]) + ); + GND plm_fsm_cla_timer_GND ( + .G(plm_fsm_cla_timer_GND_960) + ); + MUXCY_L plm_fsm_cla_timer_reg_count_cry_0_ ( + .CI(plm_fsm_cla_timer_un1_reg_state_1_i_i_962), + .DI(plm_fsm_cla_timer_GND_960), + .LO(plm_fsm_cla_timer_reg_count_cry[0]), + .S(plm_fsm_cla_timer_reg_count_qxu[0]) + ); + XORCY plm_fsm_cla_timer_reg_count_s_0_ ( + .CI(plm_fsm_cla_timer_un1_reg_state_1_i_i_962), + .LI(plm_fsm_cla_timer_reg_count_qxu[0]), + .O(plm_fsm_cla_timer_reg_count_s[0]) + ); + MUXCY_L plm_fsm_cla_timer_reg_count_cry_1_ ( + .CI(plm_fsm_cla_timer_reg_count_cry[0]), + .DI(plm_fsm_cla_timer_GND_960), + .LO(plm_fsm_cla_timer_reg_count_cry[1]), + .S(plm_fsm_cla_timer_reg_count_qxu[1]) + ); + XORCY plm_fsm_cla_timer_reg_count_s_1_ ( + .CI(plm_fsm_cla_timer_reg_count_cry[0]), + .LI(plm_fsm_cla_timer_reg_count_qxu[1]), + .O(plm_fsm_cla_timer_reg_count_s[1]) + ); + MUXCY_L plm_fsm_cla_timer_reg_count_cry_2_ ( + .CI(plm_fsm_cla_timer_reg_count_cry[1]), + .DI(plm_fsm_cla_timer_GND_960), + .LO(plm_fsm_cla_timer_reg_count_cry[2]), + .S(plm_fsm_cla_timer_reg_count_qxu[2]) + ); + XORCY plm_fsm_cla_timer_reg_count_s_2_ ( + .CI(plm_fsm_cla_timer_reg_count_cry[1]), + .LI(plm_fsm_cla_timer_reg_count_qxu[2]), + .O(plm_fsm_cla_timer_reg_count_s[2]) + ); + MUXCY_L plm_fsm_cla_timer_reg_count_cry_3_ ( + .CI(plm_fsm_cla_timer_reg_count_cry[2]), + .DI(plm_fsm_cla_timer_GND_960), + .LO(plm_fsm_cla_timer_reg_count_cry[3]), + .S(plm_fsm_cla_timer_reg_count_qxu[3]) + ); + XORCY plm_fsm_cla_timer_reg_count_s_3_ ( + .CI(plm_fsm_cla_timer_reg_count_cry[2]), + .LI(plm_fsm_cla_timer_reg_count_qxu[3]), + .O(plm_fsm_cla_timer_reg_count_s[3]) + ); + MUXCY_L plm_fsm_cla_timer_reg_count_cry_4_ ( + .CI(plm_fsm_cla_timer_reg_count_cry[3]), + .DI(plm_fsm_cla_timer_GND_960), + .LO(plm_fsm_cla_timer_reg_count_cry[4]), + .S(plm_fsm_cla_timer_reg_count_qxu[4]) + ); + XORCY plm_fsm_cla_timer_reg_count_s_4_ ( + .CI(plm_fsm_cla_timer_reg_count_cry[3]), + .LI(plm_fsm_cla_timer_reg_count_qxu[4]), + .O(plm_fsm_cla_timer_reg_count_s[4]) + ); + MUXCY_L plm_fsm_cla_timer_reg_count_cry_5_ ( + .CI(plm_fsm_cla_timer_reg_count_cry[4]), + .DI(plm_fsm_cla_timer_GND_960), + .LO(plm_fsm_cla_timer_reg_count_cry[5]), + .S(plm_fsm_cla_timer_reg_count_qxu[5]) + ); + XORCY plm_fsm_cla_timer_reg_count_s_5_ ( + .CI(plm_fsm_cla_timer_reg_count_cry[4]), + .LI(plm_fsm_cla_timer_reg_count_qxu[5]), + .O(plm_fsm_cla_timer_reg_count_s[5]) + ); + MUXCY_L plm_fsm_cla_timer_reg_count_cry_6_ ( + .CI(plm_fsm_cla_timer_reg_count_cry[5]), + .DI(plm_fsm_cla_timer_GND_960), + .LO(plm_fsm_cla_timer_reg_count_cry[6]), + .S(plm_fsm_cla_timer_reg_count_qxu[6]) + ); + XORCY plm_fsm_cla_timer_reg_count_s_6_ ( + .CI(plm_fsm_cla_timer_reg_count_cry[5]), + .LI(plm_fsm_cla_timer_reg_count_qxu[6]), + .O(plm_fsm_cla_timer_reg_count_s[6]) + ); + MUXCY_L plm_fsm_cla_timer_reg_count_cry_7_ ( + .CI(plm_fsm_cla_timer_reg_count_cry[6]), + .DI(plm_fsm_cla_timer_GND_960), + .LO(plm_fsm_cla_timer_reg_count_cry[7]), + .S(plm_fsm_cla_timer_reg_count_qxu[7]) + ); + XORCY plm_fsm_cla_timer_reg_count_s_7_ ( + .CI(plm_fsm_cla_timer_reg_count_cry[6]), + .LI(plm_fsm_cla_timer_reg_count_qxu[7]), + .O(plm_fsm_cla_timer_reg_count_s[7]) + ); + MUXCY_L plm_fsm_cla_timer_reg_count_cry_8_ ( + .CI(plm_fsm_cla_timer_reg_count_cry[7]), + .DI(plm_fsm_cla_timer_GND_960), + .LO(plm_fsm_cla_timer_reg_count_cry[8]), + .S(plm_fsm_cla_timer_reg_count_qxu[8]) + ); + XORCY plm_fsm_cla_timer_reg_count_s_8_ ( + .CI(plm_fsm_cla_timer_reg_count_cry[7]), + .LI(plm_fsm_cla_timer_reg_count_qxu[8]), + .O(plm_fsm_cla_timer_reg_count_s[8]) + ); + MUXCY_L plm_fsm_cla_timer_reg_count_cry_9_ ( + .CI(plm_fsm_cla_timer_reg_count_cry[8]), + .DI(plm_fsm_cla_timer_GND_960), + .LO(plm_fsm_cla_timer_reg_count_cry[9]), + .S(plm_fsm_cla_timer_reg_count_qxu[9]) + ); + XORCY plm_fsm_cla_timer_reg_count_s_9_ ( + .CI(plm_fsm_cla_timer_reg_count_cry[8]), + .LI(plm_fsm_cla_timer_reg_count_qxu[9]), + .O(plm_fsm_cla_timer_reg_count_s[9]) + ); + MUXCY_L plm_fsm_cla_timer_reg_count_cry_10_ ( + .CI(plm_fsm_cla_timer_reg_count_cry[9]), + .DI(plm_fsm_cla_timer_GND_960), + .LO(plm_fsm_cla_timer_reg_count_cry[10]), + .S(plm_fsm_cla_timer_reg_count_qxu[10]) + ); + XORCY plm_fsm_cla_timer_reg_count_s_10_ ( + .CI(plm_fsm_cla_timer_reg_count_cry[9]), + .LI(plm_fsm_cla_timer_reg_count_qxu[10]), + .O(plm_fsm_cla_timer_reg_count_s[10]) + ); + MUXCY_L plm_fsm_cla_timer_reg_count_cry_11_ ( + .CI(plm_fsm_cla_timer_reg_count_cry[10]), + .DI(plm_fsm_cla_timer_GND_960), + .LO(plm_fsm_cla_timer_reg_count_cry[11]), + .S(plm_fsm_cla_timer_reg_count_qxu[11]) + ); + XORCY plm_fsm_cla_timer_reg_count_s_11_ ( + .CI(plm_fsm_cla_timer_reg_count_cry[10]), + .LI(plm_fsm_cla_timer_reg_count_qxu[11]), + .O(plm_fsm_cla_timer_reg_count_s[11]) + ); + MUXCY_L plm_fsm_cla_timer_reg_count_cry_12_ ( + .CI(plm_fsm_cla_timer_reg_count_cry[11]), + .DI(plm_fsm_cla_timer_GND_960), + .LO(plm_fsm_cla_timer_reg_count_cry[12]), + .S(plm_fsm_cla_timer_reg_count_qxu[12]) + ); + XORCY plm_fsm_cla_timer_reg_count_s_12_ ( + .CI(plm_fsm_cla_timer_reg_count_cry[11]), + .LI(plm_fsm_cla_timer_reg_count_qxu[12]), + .O(plm_fsm_cla_timer_reg_count_s[12]) + ); + MUXCY_L plm_fsm_cla_timer_reg_count_cry_13_ ( + .CI(plm_fsm_cla_timer_reg_count_cry[12]), + .DI(plm_fsm_cla_timer_GND_960), + .LO(plm_fsm_cla_timer_reg_count_cry[13]), + .S(plm_fsm_cla_timer_reg_count_qxu[13]) + ); + XORCY plm_fsm_cla_timer_reg_count_s_13_ ( + .CI(plm_fsm_cla_timer_reg_count_cry[12]), + .LI(plm_fsm_cla_timer_reg_count_qxu[13]), + .O(plm_fsm_cla_timer_reg_count_s[13]) + ); + MUXCY_L plm_fsm_cla_timer_reg_count_cry_14_ ( + .CI(plm_fsm_cla_timer_reg_count_cry[13]), + .DI(plm_fsm_cla_timer_GND_960), + .LO(plm_fsm_cla_timer_reg_count_cry[14]), + .S(plm_fsm_cla_timer_reg_count_qxu[14]) + ); + XORCY plm_fsm_cla_timer_reg_count_s_14_ ( + .CI(plm_fsm_cla_timer_reg_count_cry[13]), + .LI(plm_fsm_cla_timer_reg_count_qxu[14]), + .O(plm_fsm_cla_timer_reg_count_s[14]) + ); + MUXCY_L plm_fsm_cla_timer_reg_count_cry_15_ ( + .CI(plm_fsm_cla_timer_reg_count_cry[14]), + .DI(plm_fsm_cla_timer_GND_960), + .LO(plm_fsm_cla_timer_reg_count_cry[15]), + .S(plm_fsm_cla_timer_reg_count_qxu[15]) + ); + XORCY plm_fsm_cla_timer_reg_count_s_15_ ( + .CI(plm_fsm_cla_timer_reg_count_cry[14]), + .LI(plm_fsm_cla_timer_reg_count_qxu[15]), + .O(plm_fsm_cla_timer_reg_count_s[15]) + ); + MUXCY_L plm_fsm_cla_timer_reg_count_cry_16_ ( + .CI(plm_fsm_cla_timer_reg_count_cry[15]), + .DI(plm_fsm_cla_timer_GND_960), + .LO(plm_fsm_cla_timer_reg_count_cry[16]), + .S(plm_fsm_cla_timer_reg_count_qxu[16]) + ); + XORCY plm_fsm_cla_timer_reg_count_s_16_ ( + .CI(plm_fsm_cla_timer_reg_count_cry[15]), + .LI(plm_fsm_cla_timer_reg_count_qxu[16]), + .O(plm_fsm_cla_timer_reg_count_s[16]) + ); + MUXCY_L plm_fsm_cla_timer_reg_count_cry_17_ ( + .CI(plm_fsm_cla_timer_reg_count_cry[16]), + .DI(plm_fsm_cla_timer_GND_960), + .LO(plm_fsm_cla_timer_reg_count_cry[17]), + .S(plm_fsm_cla_timer_reg_count_qxu[17]) + ); + XORCY plm_fsm_cla_timer_reg_count_s_17_ ( + .CI(plm_fsm_cla_timer_reg_count_cry[16]), + .LI(plm_fsm_cla_timer_reg_count_qxu[17]), + .O(plm_fsm_cla_timer_reg_count_s[17]) + ); + MUXCY_L plm_fsm_cla_timer_reg_count_cry_18_ ( + .CI(plm_fsm_cla_timer_reg_count_cry[17]), + .DI(plm_fsm_cla_timer_GND_960), + .LO(plm_fsm_cla_timer_reg_count_cry[18]), + .S(plm_fsm_cla_timer_reg_count_qxu[18]) + ); + XORCY plm_fsm_cla_timer_reg_count_s_18_ ( + .CI(plm_fsm_cla_timer_reg_count_cry[17]), + .LI(plm_fsm_cla_timer_reg_count_qxu[18]), + .O(plm_fsm_cla_timer_reg_count_s[18]) + ); + MUXCY_L plm_fsm_cla_timer_reg_count_cry_19_ ( + .CI(plm_fsm_cla_timer_reg_count_cry[18]), + .DI(plm_fsm_cla_timer_GND_960), + .LO(plm_fsm_cla_timer_reg_count_cry[19]), + .S(plm_fsm_cla_timer_reg_count_qxu[19]) + ); + XORCY plm_fsm_cla_timer_reg_count_s_19_ ( + .CI(plm_fsm_cla_timer_reg_count_cry[18]), + .LI(plm_fsm_cla_timer_reg_count_qxu[19]), + .O(plm_fsm_cla_timer_reg_count_s[19]) + ); + MUXCY_L plm_fsm_cla_timer_reg_count_cry_20_ ( + .CI(plm_fsm_cla_timer_reg_count_cry[19]), + .DI(plm_fsm_cla_timer_GND_960), + .LO(plm_fsm_cla_timer_reg_count_cry[20]), + .S(plm_fsm_cla_timer_reg_count_qxu[20]) + ); + XORCY plm_fsm_cla_timer_reg_count_s_20_ ( + .CI(plm_fsm_cla_timer_reg_count_cry[19]), + .LI(plm_fsm_cla_timer_reg_count_qxu[20]), + .O(plm_fsm_cla_timer_reg_count_s[20]) + ); + MUXCY_L plm_fsm_cla_timer_reg_count_cry_21_ ( + .CI(plm_fsm_cla_timer_reg_count_cry[20]), + .DI(plm_fsm_cla_timer_GND_960), + .LO(plm_fsm_cla_timer_reg_count_cry[21]), + .S(plm_fsm_cla_timer_reg_count_qxu[21]) + ); + XORCY plm_fsm_cla_timer_reg_count_s_21_ ( + .CI(plm_fsm_cla_timer_reg_count_cry[20]), + .LI(plm_fsm_cla_timer_reg_count_qxu[21]), + .O(plm_fsm_cla_timer_reg_count_s[21]) + ); + XORCY plm_fsm_cla_timer_reg_count_s_22_ ( + .CI(plm_fsm_cla_timer_reg_count_cry[21]), + .LI(plm_fsm_cla_timer_reg_count_qxu[22]), + .O(plm_fsm_cla_timer_reg_count_s[22]) + ); + defparam plm_fsm_cla_timer_count_0_18_.INIT = 8'hD8; + LUT3 plm_fsm_cla_timer_count_0_18_ ( + .I0(cfg_cfg_5072[507]), + .I1(plm_fsm_cla_timer_reg_count[10]), + .I2(plm_fsm_cla_timer_reg_count[18]), + .O(plm_fsm_cla_timer_count[18]) + ); + defparam plm_fsm_cla_timer_count_0_19_.INIT = 8'hD8; + LUT3_L plm_fsm_cla_timer_count_0_19_ ( + .I0(cfg_cfg_5072[507]), + .I1(plm_fsm_cla_timer_reg_count[11]), + .I2(plm_fsm_cla_timer_reg_count[19]), + .LO(plm_fsm_cla_timer_count[19]) + ); + defparam plm_fsm_cla_timer_count_0_20_.INIT = 8'hD8; + LUT3 plm_fsm_cla_timer_count_0_20_ ( + .I0(cfg_cfg_5072[507]), + .I1(plm_fsm_cla_timer_reg_count[12]), + .I2(plm_fsm_cla_timer_reg_count[20]), + .O(plm_fsm_cla_timer_count[20]) + ); + defparam plm_fsm_cla_timer_count_0_21_.INIT = 8'hD8; + LUT3 plm_fsm_cla_timer_count_0_21_ ( + .I0(cfg_cfg_5072[507]), + .I1(plm_fsm_cla_timer_reg_count[13]), + .I2(plm_fsm_cla_timer_reg_count[21]), + .O(plm_fsm_cla_timer_count[21]) + ); + defparam plm_fsm_cla_timer_un1_reg_state_1_i_i.INIT = 4'hE; + LUT2 plm_fsm_cla_timer_un1_reg_state_1_i_i ( + .I0(plm_fsm_reg_state_5__876), + .I1(plm_fsm_reg_state_6__875), + .O(plm_fsm_cla_timer_un1_reg_state_1_i_i_962) + ); + defparam plm_fsm_cla_timer_un1_expired_2ms_0_a2_0_a2_0.INIT = 16'h0213; + LUT4_L plm_fsm_cla_timer_un1_expired_2ms_0_a2_0_a2_0 ( + .I0(cfg_cfg_5072[507]), + .I1(plm_fsm_cla_timer_count[19]), + .I2(plm_fsm_cla_timer_reg_count[14]), + .I3(plm_fsm_cla_timer_reg_count[22]), + .LO(plm_fsm_cla_timer_un1_expired_2ms_0_a2_0_a2_0_961) + ); + defparam plm_fsm_cla_timer_un1_expired_2ms_0_a2_0_a2.INIT = 16'h0100; + LUT4 plm_fsm_cla_timer_un1_expired_2ms_0_a2_0_a2 ( + .I0(plm_fsm_cla_timer_count[18]), + .I1(plm_fsm_cla_timer_count[20]), + .I2(plm_fsm_cla_timer_count[21]), + .I3(plm_fsm_cla_timer_un1_expired_2ms_0_a2_0_a2_0_961), + .O(plm_fsm_N_51184) + ); + FDC plm_fsm_cla_timer_reg_count_22_ ( + .C(mgt_clk), + .D(plm_fsm_cla_timer_reg_count_s[22]), + .Q(plm_fsm_cla_timer_reg_count[22]), + .CLR(plm_rst) + ); + FDC plm_fsm_cla_timer_reg_count_21_ ( + .C(mgt_clk), + .D(plm_fsm_cla_timer_reg_count_s[21]), + .Q(plm_fsm_cla_timer_reg_count[21]), + .CLR(plm_rst) + ); + FDC plm_fsm_cla_timer_reg_count_20_ ( + .C(mgt_clk), + .D(plm_fsm_cla_timer_reg_count_s[20]), + .Q(plm_fsm_cla_timer_reg_count[20]), + .CLR(plm_rst) + ); + FDC plm_fsm_cla_timer_reg_count_19_ ( + .C(mgt_clk), + .D(plm_fsm_cla_timer_reg_count_s[19]), + .Q(plm_fsm_cla_timer_reg_count[19]), + .CLR(plm_rst) + ); + FDC plm_fsm_cla_timer_reg_count_18_ ( + .C(mgt_clk), + .D(plm_fsm_cla_timer_reg_count_s[18]), + .Q(plm_fsm_cla_timer_reg_count[18]), + .CLR(plm_rst) + ); + FDC plm_fsm_cla_timer_reg_count_17_ ( + .C(mgt_clk), + .D(plm_fsm_cla_timer_reg_count_s[17]), + .Q(plm_fsm_cla_timer_reg_count[17]), + .CLR(plm_rst) + ); + FDC plm_fsm_cla_timer_reg_count_16_ ( + .C(mgt_clk), + .D(plm_fsm_cla_timer_reg_count_s[16]), + .Q(plm_fsm_cla_timer_reg_count[16]), + .CLR(plm_rst) + ); + FDC plm_fsm_cla_timer_reg_count_15_ ( + .C(mgt_clk), + .D(plm_fsm_cla_timer_reg_count_s[15]), + .Q(plm_fsm_cla_timer_reg_count[15]), + .CLR(plm_rst) + ); + FDC plm_fsm_cla_timer_reg_count_14_ ( + .C(mgt_clk), + .D(plm_fsm_cla_timer_reg_count_s[14]), + .Q(plm_fsm_cla_timer_reg_count[14]), + .CLR(plm_rst) + ); + FDC plm_fsm_cla_timer_reg_count_13_ ( + .C(mgt_clk), + .D(plm_fsm_cla_timer_reg_count_s[13]), + .Q(plm_fsm_cla_timer_reg_count[13]), + .CLR(plm_rst) + ); + FDC plm_fsm_cla_timer_reg_count_12_ ( + .C(mgt_clk), + .D(plm_fsm_cla_timer_reg_count_s[12]), + .Q(plm_fsm_cla_timer_reg_count[12]), + .CLR(plm_rst) + ); + FDC plm_fsm_cla_timer_reg_count_11_ ( + .C(mgt_clk), + .D(plm_fsm_cla_timer_reg_count_s[11]), + .Q(plm_fsm_cla_timer_reg_count[11]), + .CLR(plm_rst) + ); + FDC plm_fsm_cla_timer_reg_count_10_ ( + .C(mgt_clk), + .D(plm_fsm_cla_timer_reg_count_s[10]), + .Q(plm_fsm_cla_timer_reg_count[10]), + .CLR(plm_rst) + ); + FDC plm_fsm_cla_timer_reg_count_9_ ( + .C(mgt_clk), + .D(plm_fsm_cla_timer_reg_count_s[9]), + .Q(plm_fsm_cla_timer_reg_count[9]), + .CLR(plm_rst) + ); + FDC plm_fsm_cla_timer_reg_count_8_ ( + .C(mgt_clk), + .D(plm_fsm_cla_timer_reg_count_s[8]), + .Q(plm_fsm_cla_timer_reg_count[8]), + .CLR(plm_rst) + ); + FDC plm_fsm_cla_timer_reg_count_7_ ( + .C(mgt_clk), + .D(plm_fsm_cla_timer_reg_count_s[7]), + .Q(plm_fsm_cla_timer_reg_count[7]), + .CLR(plm_rst) + ); + FDC plm_fsm_cla_timer_reg_count_6_ ( + .C(mgt_clk), + .D(plm_fsm_cla_timer_reg_count_s[6]), + .Q(plm_fsm_cla_timer_reg_count[6]), + .CLR(plm_rst) + ); + FDC plm_fsm_cla_timer_reg_count_5_ ( + .C(mgt_clk), + .D(plm_fsm_cla_timer_reg_count_s[5]), + .Q(plm_fsm_cla_timer_reg_count[5]), + .CLR(plm_rst) + ); + FDC plm_fsm_cla_timer_reg_count_4_ ( + .C(mgt_clk), + .D(plm_fsm_cla_timer_reg_count_s[4]), + .Q(plm_fsm_cla_timer_reg_count[4]), + .CLR(plm_rst) + ); + FDC plm_fsm_cla_timer_reg_count_3_ ( + .C(mgt_clk), + .D(plm_fsm_cla_timer_reg_count_s[3]), + .Q(plm_fsm_cla_timer_reg_count[3]), + .CLR(plm_rst) + ); + FDC plm_fsm_cla_timer_reg_count_2_ ( + .C(mgt_clk), + .D(plm_fsm_cla_timer_reg_count_s[2]), + .Q(plm_fsm_cla_timer_reg_count[2]), + .CLR(plm_rst) + ); + FDC plm_fsm_cla_timer_reg_count_1_ ( + .C(mgt_clk), + .D(plm_fsm_cla_timer_reg_count_s[1]), + .Q(plm_fsm_cla_timer_reg_count[1]), + .CLR(plm_rst) + ); + FDC plm_fsm_cla_timer_reg_count_0_ ( + .C(mgt_clk), + .D(plm_fsm_cla_timer_reg_count_s[0]), + .Q(plm_fsm_cla_timer_reg_count[0]), + .CLR(plm_rst) + ); + defparam plm_fsm_cla_timer_reg_count_qxu_0_0_.INIT = 4'h8; + LUT2_L plm_fsm_cla_timer_reg_count_qxu_0_0_ ( + .I0(plm_fsm_cla_timer_reg_count[0]), + .I1(plm_fsm_cla_timer_un1_reg_state_1_i_i_962), + .LO(plm_fsm_cla_timer_reg_count_qxu[0]) + ); + defparam plm_fsm_cla_timer_reg_count_qxu_0_1_.INIT = 4'h8; + LUT2_L plm_fsm_cla_timer_reg_count_qxu_0_1_ ( + .I0(plm_fsm_cla_timer_reg_count[1]), + .I1(plm_fsm_cla_timer_un1_reg_state_1_i_i_962), + .LO(plm_fsm_cla_timer_reg_count_qxu[1]) + ); + defparam plm_fsm_cla_timer_reg_count_qxu_0_2_.INIT = 4'h8; + LUT2_L plm_fsm_cla_timer_reg_count_qxu_0_2_ ( + .I0(plm_fsm_cla_timer_reg_count[2]), + .I1(plm_fsm_cla_timer_un1_reg_state_1_i_i_962), + .LO(plm_fsm_cla_timer_reg_count_qxu[2]) + ); + defparam plm_fsm_cla_timer_reg_count_qxu_0_3_.INIT = 4'h8; + LUT2_L plm_fsm_cla_timer_reg_count_qxu_0_3_ ( + .I0(plm_fsm_cla_timer_reg_count[3]), + .I1(plm_fsm_cla_timer_un1_reg_state_1_i_i_962), + .LO(plm_fsm_cla_timer_reg_count_qxu[3]) + ); + defparam plm_fsm_cla_timer_reg_count_qxu_0_4_.INIT = 4'h8; + LUT2_L plm_fsm_cla_timer_reg_count_qxu_0_4_ ( + .I0(plm_fsm_cla_timer_reg_count[4]), + .I1(plm_fsm_cla_timer_un1_reg_state_1_i_i_962), + .LO(plm_fsm_cla_timer_reg_count_qxu[4]) + ); + defparam plm_fsm_cla_timer_reg_count_qxu_0_5_.INIT = 4'h8; + LUT2_L plm_fsm_cla_timer_reg_count_qxu_0_5_ ( + .I0(plm_fsm_cla_timer_reg_count[5]), + .I1(plm_fsm_cla_timer_un1_reg_state_1_i_i_962), + .LO(plm_fsm_cla_timer_reg_count_qxu[5]) + ); + defparam plm_fsm_cla_timer_reg_count_qxu_0_6_.INIT = 4'h8; + LUT2_L plm_fsm_cla_timer_reg_count_qxu_0_6_ ( + .I0(plm_fsm_cla_timer_reg_count[6]), + .I1(plm_fsm_cla_timer_un1_reg_state_1_i_i_962), + .LO(plm_fsm_cla_timer_reg_count_qxu[6]) + ); + defparam plm_fsm_cla_timer_reg_count_qxu_0_7_.INIT = 4'h8; + LUT2_L plm_fsm_cla_timer_reg_count_qxu_0_7_ ( + .I0(plm_fsm_cla_timer_reg_count[7]), + .I1(plm_fsm_cla_timer_un1_reg_state_1_i_i_962), + .LO(plm_fsm_cla_timer_reg_count_qxu[7]) + ); + defparam plm_fsm_cla_timer_reg_count_qxu_0_8_.INIT = 4'h8; + LUT2_L plm_fsm_cla_timer_reg_count_qxu_0_8_ ( + .I0(plm_fsm_cla_timer_reg_count[8]), + .I1(plm_fsm_cla_timer_un1_reg_state_1_i_i_962), + .LO(plm_fsm_cla_timer_reg_count_qxu[8]) + ); + defparam plm_fsm_cla_timer_reg_count_qxu_0_9_.INIT = 4'h8; + LUT2_L plm_fsm_cla_timer_reg_count_qxu_0_9_ ( + .I0(plm_fsm_cla_timer_reg_count[9]), + .I1(plm_fsm_cla_timer_un1_reg_state_1_i_i_962), + .LO(plm_fsm_cla_timer_reg_count_qxu[9]) + ); + defparam plm_fsm_cla_timer_reg_count_qxu_0_10_.INIT = 4'h8; + LUT2_L plm_fsm_cla_timer_reg_count_qxu_0_10_ ( + .I0(plm_fsm_cla_timer_reg_count[10]), + .I1(plm_fsm_cla_timer_un1_reg_state_1_i_i_962), + .LO(plm_fsm_cla_timer_reg_count_qxu[10]) + ); + defparam plm_fsm_cla_timer_reg_count_qxu_0_11_.INIT = 4'h8; + LUT2_L plm_fsm_cla_timer_reg_count_qxu_0_11_ ( + .I0(plm_fsm_cla_timer_reg_count[11]), + .I1(plm_fsm_cla_timer_un1_reg_state_1_i_i_962), + .LO(plm_fsm_cla_timer_reg_count_qxu[11]) + ); + defparam plm_fsm_cla_timer_reg_count_qxu_0_12_.INIT = 4'h8; + LUT2_L plm_fsm_cla_timer_reg_count_qxu_0_12_ ( + .I0(plm_fsm_cla_timer_reg_count[12]), + .I1(plm_fsm_cla_timer_un1_reg_state_1_i_i_962), + .LO(plm_fsm_cla_timer_reg_count_qxu[12]) + ); + defparam plm_fsm_cla_timer_reg_count_qxu_0_13_.INIT = 4'h8; + LUT2_L plm_fsm_cla_timer_reg_count_qxu_0_13_ ( + .I0(plm_fsm_cla_timer_reg_count[13]), + .I1(plm_fsm_cla_timer_un1_reg_state_1_i_i_962), + .LO(plm_fsm_cla_timer_reg_count_qxu[13]) + ); + defparam plm_fsm_cla_timer_reg_count_qxu_0_14_.INIT = 4'h8; + LUT2_L plm_fsm_cla_timer_reg_count_qxu_0_14_ ( + .I0(plm_fsm_cla_timer_reg_count[14]), + .I1(plm_fsm_cla_timer_un1_reg_state_1_i_i_962), + .LO(plm_fsm_cla_timer_reg_count_qxu[14]) + ); + defparam plm_fsm_cla_timer_reg_count_qxu_0_15_.INIT = 4'h8; + LUT2_L plm_fsm_cla_timer_reg_count_qxu_0_15_ ( + .I0(plm_fsm_cla_timer_reg_count[15]), + .I1(plm_fsm_cla_timer_un1_reg_state_1_i_i_962), + .LO(plm_fsm_cla_timer_reg_count_qxu[15]) + ); + defparam plm_fsm_cla_timer_reg_count_qxu_0_16_.INIT = 4'h8; + LUT2_L plm_fsm_cla_timer_reg_count_qxu_0_16_ ( + .I0(plm_fsm_cla_timer_reg_count[16]), + .I1(plm_fsm_cla_timer_un1_reg_state_1_i_i_962), + .LO(plm_fsm_cla_timer_reg_count_qxu[16]) + ); + defparam plm_fsm_cla_timer_reg_count_qxu_0_17_.INIT = 4'h8; + LUT2_L plm_fsm_cla_timer_reg_count_qxu_0_17_ ( + .I0(plm_fsm_cla_timer_reg_count[17]), + .I1(plm_fsm_cla_timer_un1_reg_state_1_i_i_962), + .LO(plm_fsm_cla_timer_reg_count_qxu[17]) + ); + defparam plm_fsm_cla_timer_reg_count_qxu_0_18_.INIT = 4'h8; + LUT2_L plm_fsm_cla_timer_reg_count_qxu_0_18_ ( + .I0(plm_fsm_cla_timer_reg_count[18]), + .I1(plm_fsm_cla_timer_un1_reg_state_1_i_i_962), + .LO(plm_fsm_cla_timer_reg_count_qxu[18]) + ); + defparam plm_fsm_cla_timer_reg_count_qxu_0_19_.INIT = 4'h8; + LUT2_L plm_fsm_cla_timer_reg_count_qxu_0_19_ ( + .I0(plm_fsm_cla_timer_reg_count[19]), + .I1(plm_fsm_cla_timer_un1_reg_state_1_i_i_962), + .LO(plm_fsm_cla_timer_reg_count_qxu[19]) + ); + defparam plm_fsm_cla_timer_reg_count_qxu_0_20_.INIT = 4'h8; + LUT2_L plm_fsm_cla_timer_reg_count_qxu_0_20_ ( + .I0(plm_fsm_cla_timer_reg_count[20]), + .I1(plm_fsm_cla_timer_un1_reg_state_1_i_i_962), + .LO(plm_fsm_cla_timer_reg_count_qxu[20]) + ); + defparam plm_fsm_cla_timer_reg_count_qxu_0_21_.INIT = 4'h8; + LUT2_L plm_fsm_cla_timer_reg_count_qxu_0_21_ ( + .I0(plm_fsm_cla_timer_reg_count[21]), + .I1(plm_fsm_cla_timer_un1_reg_state_1_i_i_962), + .LO(plm_fsm_cla_timer_reg_count_qxu[21]) + ); + defparam plm_fsm_cla_timer_reg_count_qxu_0_22_.INIT = 4'h8; + LUT2_L plm_fsm_cla_timer_reg_count_qxu_0_22_ ( + .I0(plm_fsm_cla_timer_reg_count[22]), + .I1(plm_fsm_cla_timer_un1_reg_state_1_i_i_962), + .LO(plm_fsm_cla_timer_reg_count_qxu[22]) + ); + GND plm_fsm_clw_timer_GND ( + .G(plm_fsm_clw_timer_GND_963) + ); + MUXCY_L plm_fsm_clw_timer_reg_count_cry_0_ ( + .CI(plm_fsm_reg_state_7__874), + .DI(plm_fsm_clw_timer_GND_963), + .LO(plm_fsm_clw_timer_reg_count_cry[0]), + .S(plm_fsm_clw_timer_reg_count_qxu[0]) + ); + XORCY plm_fsm_clw_timer_reg_count_s_0_ ( + .CI(plm_fsm_reg_state_7__874), + .LI(plm_fsm_clw_timer_reg_count_qxu[0]), + .O(plm_fsm_clw_timer_reg_count_s[0]) + ); + MUXCY_L plm_fsm_clw_timer_reg_count_cry_1_ ( + .CI(plm_fsm_clw_timer_reg_count_cry[0]), + .DI(plm_fsm_clw_timer_GND_963), + .LO(plm_fsm_clw_timer_reg_count_cry[1]), + .S(plm_fsm_clw_timer_reg_count_qxu[1]) + ); + XORCY plm_fsm_clw_timer_reg_count_s_1_ ( + .CI(plm_fsm_clw_timer_reg_count_cry[0]), + .LI(plm_fsm_clw_timer_reg_count_qxu[1]), + .O(plm_fsm_clw_timer_reg_count_s[1]) + ); + MUXCY_L plm_fsm_clw_timer_reg_count_cry_2_ ( + .CI(plm_fsm_clw_timer_reg_count_cry[1]), + .DI(plm_fsm_clw_timer_GND_963), + .LO(plm_fsm_clw_timer_reg_count_cry[2]), + .S(plm_fsm_clw_timer_reg_count_qxu[2]) + ); + XORCY plm_fsm_clw_timer_reg_count_s_2_ ( + .CI(plm_fsm_clw_timer_reg_count_cry[1]), + .LI(plm_fsm_clw_timer_reg_count_qxu[2]), + .O(plm_fsm_clw_timer_reg_count_s[2]) + ); + MUXCY_L plm_fsm_clw_timer_reg_count_cry_3_ ( + .CI(plm_fsm_clw_timer_reg_count_cry[2]), + .DI(plm_fsm_clw_timer_GND_963), + .LO(plm_fsm_clw_timer_reg_count_cry[3]), + .S(plm_fsm_clw_timer_reg_count_qxu[3]) + ); + XORCY plm_fsm_clw_timer_reg_count_s_3_ ( + .CI(plm_fsm_clw_timer_reg_count_cry[2]), + .LI(plm_fsm_clw_timer_reg_count_qxu[3]), + .O(plm_fsm_clw_timer_reg_count_s[3]) + ); + MUXCY_L plm_fsm_clw_timer_reg_count_cry_4_ ( + .CI(plm_fsm_clw_timer_reg_count_cry[3]), + .DI(plm_fsm_clw_timer_GND_963), + .LO(plm_fsm_clw_timer_reg_count_cry[4]), + .S(plm_fsm_clw_timer_reg_count_qxu[4]) + ); + XORCY plm_fsm_clw_timer_reg_count_s_4_ ( + .CI(plm_fsm_clw_timer_reg_count_cry[3]), + .LI(plm_fsm_clw_timer_reg_count_qxu[4]), + .O(plm_fsm_clw_timer_reg_count_s[4]) + ); + MUXCY_L plm_fsm_clw_timer_reg_count_cry_5_ ( + .CI(plm_fsm_clw_timer_reg_count_cry[4]), + .DI(plm_fsm_clw_timer_GND_963), + .LO(plm_fsm_clw_timer_reg_count_cry[5]), + .S(plm_fsm_clw_timer_reg_count_qxu[5]) + ); + XORCY plm_fsm_clw_timer_reg_count_s_5_ ( + .CI(plm_fsm_clw_timer_reg_count_cry[4]), + .LI(plm_fsm_clw_timer_reg_count_qxu[5]), + .O(plm_fsm_clw_timer_reg_count_s[5]) + ); + MUXCY_L plm_fsm_clw_timer_reg_count_cry_6_ ( + .CI(plm_fsm_clw_timer_reg_count_cry[5]), + .DI(plm_fsm_clw_timer_GND_963), + .LO(plm_fsm_clw_timer_reg_count_cry[6]), + .S(plm_fsm_clw_timer_reg_count_qxu[6]) + ); + XORCY plm_fsm_clw_timer_reg_count_s_6_ ( + .CI(plm_fsm_clw_timer_reg_count_cry[5]), + .LI(plm_fsm_clw_timer_reg_count_qxu[6]), + .O(plm_fsm_clw_timer_reg_count_s[6]) + ); + MUXCY_L plm_fsm_clw_timer_reg_count_cry_7_ ( + .CI(plm_fsm_clw_timer_reg_count_cry[6]), + .DI(plm_fsm_clw_timer_GND_963), + .LO(plm_fsm_clw_timer_reg_count_cry[7]), + .S(plm_fsm_clw_timer_reg_count_qxu[7]) + ); + XORCY plm_fsm_clw_timer_reg_count_s_7_ ( + .CI(plm_fsm_clw_timer_reg_count_cry[6]), + .LI(plm_fsm_clw_timer_reg_count_qxu[7]), + .O(plm_fsm_clw_timer_reg_count_s[7]) + ); + MUXCY_L plm_fsm_clw_timer_reg_count_cry_8_ ( + .CI(plm_fsm_clw_timer_reg_count_cry[7]), + .DI(plm_fsm_clw_timer_GND_963), + .LO(plm_fsm_clw_timer_reg_count_cry[8]), + .S(plm_fsm_clw_timer_reg_count_qxu[8]) + ); + XORCY plm_fsm_clw_timer_reg_count_s_8_ ( + .CI(plm_fsm_clw_timer_reg_count_cry[7]), + .LI(plm_fsm_clw_timer_reg_count_qxu[8]), + .O(plm_fsm_clw_timer_reg_count_s[8]) + ); + MUXCY_L plm_fsm_clw_timer_reg_count_cry_9_ ( + .CI(plm_fsm_clw_timer_reg_count_cry[8]), + .DI(plm_fsm_clw_timer_GND_963), + .LO(plm_fsm_clw_timer_reg_count_cry[9]), + .S(plm_fsm_clw_timer_reg_count_qxu[9]) + ); + XORCY plm_fsm_clw_timer_reg_count_s_9_ ( + .CI(plm_fsm_clw_timer_reg_count_cry[8]), + .LI(plm_fsm_clw_timer_reg_count_qxu[9]), + .O(plm_fsm_clw_timer_reg_count_s[9]) + ); + MUXCY_L plm_fsm_clw_timer_reg_count_cry_10_ ( + .CI(plm_fsm_clw_timer_reg_count_cry[9]), + .DI(plm_fsm_clw_timer_GND_963), + .LO(plm_fsm_clw_timer_reg_count_cry[10]), + .S(plm_fsm_clw_timer_reg_count_qxu[10]) + ); + XORCY plm_fsm_clw_timer_reg_count_s_10_ ( + .CI(plm_fsm_clw_timer_reg_count_cry[9]), + .LI(plm_fsm_clw_timer_reg_count_qxu[10]), + .O(plm_fsm_clw_timer_reg_count_s[10]) + ); + MUXCY_L plm_fsm_clw_timer_reg_count_cry_11_ ( + .CI(plm_fsm_clw_timer_reg_count_cry[10]), + .DI(plm_fsm_clw_timer_GND_963), + .LO(plm_fsm_clw_timer_reg_count_cry[11]), + .S(plm_fsm_clw_timer_reg_count_qxu[11]) + ); + XORCY plm_fsm_clw_timer_reg_count_s_11_ ( + .CI(plm_fsm_clw_timer_reg_count_cry[10]), + .LI(plm_fsm_clw_timer_reg_count_qxu[11]), + .O(plm_fsm_clw_timer_reg_count_s[11]) + ); + MUXCY_L plm_fsm_clw_timer_reg_count_cry_12_ ( + .CI(plm_fsm_clw_timer_reg_count_cry[11]), + .DI(plm_fsm_clw_timer_GND_963), + .LO(plm_fsm_clw_timer_reg_count_cry[12]), + .S(plm_fsm_clw_timer_reg_count_qxu[12]) + ); + XORCY plm_fsm_clw_timer_reg_count_s_12_ ( + .CI(plm_fsm_clw_timer_reg_count_cry[11]), + .LI(plm_fsm_clw_timer_reg_count_qxu[12]), + .O(plm_fsm_clw_timer_reg_count_s[12]) + ); + MUXCY_L plm_fsm_clw_timer_reg_count_cry_13_ ( + .CI(plm_fsm_clw_timer_reg_count_cry[12]), + .DI(plm_fsm_clw_timer_GND_963), + .LO(plm_fsm_clw_timer_reg_count_cry[13]), + .S(plm_fsm_clw_timer_reg_count_qxu[13]) + ); + XORCY plm_fsm_clw_timer_reg_count_s_13_ ( + .CI(plm_fsm_clw_timer_reg_count_cry[12]), + .LI(plm_fsm_clw_timer_reg_count_qxu[13]), + .O(plm_fsm_clw_timer_reg_count_s[13]) + ); + MUXCY_L plm_fsm_clw_timer_reg_count_cry_14_ ( + .CI(plm_fsm_clw_timer_reg_count_cry[13]), + .DI(plm_fsm_clw_timer_GND_963), + .LO(plm_fsm_clw_timer_reg_count_cry[14]), + .S(plm_fsm_clw_timer_reg_count_qxu[14]) + ); + XORCY plm_fsm_clw_timer_reg_count_s_14_ ( + .CI(plm_fsm_clw_timer_reg_count_cry[13]), + .LI(plm_fsm_clw_timer_reg_count_qxu[14]), + .O(plm_fsm_clw_timer_reg_count_s[14]) + ); + MUXCY_L plm_fsm_clw_timer_reg_count_cry_15_ ( + .CI(plm_fsm_clw_timer_reg_count_cry[14]), + .DI(plm_fsm_clw_timer_GND_963), + .LO(plm_fsm_clw_timer_reg_count_cry[15]), + .S(plm_fsm_clw_timer_reg_count_qxu[15]) + ); + XORCY plm_fsm_clw_timer_reg_count_s_15_ ( + .CI(plm_fsm_clw_timer_reg_count_cry[14]), + .LI(plm_fsm_clw_timer_reg_count_qxu[15]), + .O(plm_fsm_clw_timer_reg_count_s[15]) + ); + MUXCY_L plm_fsm_clw_timer_reg_count_cry_16_ ( + .CI(plm_fsm_clw_timer_reg_count_cry[15]), + .DI(plm_fsm_clw_timer_GND_963), + .LO(plm_fsm_clw_timer_reg_count_cry[16]), + .S(plm_fsm_clw_timer_reg_count_qxu[16]) + ); + XORCY plm_fsm_clw_timer_reg_count_s_16_ ( + .CI(plm_fsm_clw_timer_reg_count_cry[15]), + .LI(plm_fsm_clw_timer_reg_count_qxu[16]), + .O(plm_fsm_clw_timer_reg_count_s[16]) + ); + MUXCY_L plm_fsm_clw_timer_reg_count_cry_17_ ( + .CI(plm_fsm_clw_timer_reg_count_cry[16]), + .DI(plm_fsm_clw_timer_GND_963), + .LO(plm_fsm_clw_timer_reg_count_cry[17]), + .S(plm_fsm_clw_timer_reg_count_qxu[17]) + ); + XORCY plm_fsm_clw_timer_reg_count_s_17_ ( + .CI(plm_fsm_clw_timer_reg_count_cry[16]), + .LI(plm_fsm_clw_timer_reg_count_qxu[17]), + .O(plm_fsm_clw_timer_reg_count_s[17]) + ); + MUXCY_L plm_fsm_clw_timer_reg_count_cry_18_ ( + .CI(plm_fsm_clw_timer_reg_count_cry[17]), + .DI(plm_fsm_clw_timer_GND_963), + .LO(plm_fsm_clw_timer_reg_count_cry[18]), + .S(plm_fsm_clw_timer_reg_count_qxu[18]) + ); + XORCY plm_fsm_clw_timer_reg_count_s_18_ ( + .CI(plm_fsm_clw_timer_reg_count_cry[17]), + .LI(plm_fsm_clw_timer_reg_count_qxu[18]), + .O(plm_fsm_clw_timer_reg_count_s[18]) + ); + MUXCY_L plm_fsm_clw_timer_reg_count_cry_19_ ( + .CI(plm_fsm_clw_timer_reg_count_cry[18]), + .DI(plm_fsm_clw_timer_GND_963), + .LO(plm_fsm_clw_timer_reg_count_cry[19]), + .S(plm_fsm_clw_timer_reg_count_qxu[19]) + ); + XORCY plm_fsm_clw_timer_reg_count_s_19_ ( + .CI(plm_fsm_clw_timer_reg_count_cry[18]), + .LI(plm_fsm_clw_timer_reg_count_qxu[19]), + .O(plm_fsm_clw_timer_reg_count_s[19]) + ); + MUXCY_L plm_fsm_clw_timer_reg_count_cry_20_ ( + .CI(plm_fsm_clw_timer_reg_count_cry[19]), + .DI(plm_fsm_clw_timer_GND_963), + .LO(plm_fsm_clw_timer_reg_count_cry[20]), + .S(plm_fsm_clw_timer_reg_count_qxu[20]) + ); + XORCY plm_fsm_clw_timer_reg_count_s_20_ ( + .CI(plm_fsm_clw_timer_reg_count_cry[19]), + .LI(plm_fsm_clw_timer_reg_count_qxu[20]), + .O(plm_fsm_clw_timer_reg_count_s[20]) + ); + MUXCY_L plm_fsm_clw_timer_reg_count_cry_21_ ( + .CI(plm_fsm_clw_timer_reg_count_cry[20]), + .DI(plm_fsm_clw_timer_GND_963), + .LO(plm_fsm_clw_timer_reg_count_cry[21]), + .S(plm_fsm_clw_timer_reg_count_qxu[21]) + ); + XORCY plm_fsm_clw_timer_reg_count_s_21_ ( + .CI(plm_fsm_clw_timer_reg_count_cry[20]), + .LI(plm_fsm_clw_timer_reg_count_qxu[21]), + .O(plm_fsm_clw_timer_reg_count_s[21]) + ); + XORCY plm_fsm_clw_timer_reg_count_s_22_ ( + .CI(plm_fsm_clw_timer_reg_count_cry[21]), + .LI(plm_fsm_clw_timer_reg_count_qxu[22]), + .O(plm_fsm_clw_timer_reg_count_s[22]) + ); + defparam plm_fsm_clw_timer_count_i_m3_i_m3_i_m3_0_21_.INIT = 8'hD8; + LUT3 plm_fsm_clw_timer_count_i_m3_i_m3_i_m3_0_21_ ( + .I0(cfg_cfg_5072[507]), + .I1(plm_fsm_clw_timer_reg_count[13]), + .I2(plm_fsm_clw_timer_reg_count[21]), + .O(plm_fsm_clw_timer_N_51457) + ); + defparam plm_fsm_clw_timer_count_i_m3_i_m3_i_m3_0_20_.INIT = 8'hD8; + LUT3 plm_fsm_clw_timer_count_i_m3_i_m3_i_m3_0_20_ ( + .I0(cfg_cfg_5072[507]), + .I1(plm_fsm_clw_timer_reg_count[12]), + .I2(plm_fsm_clw_timer_reg_count[20]), + .O(plm_fsm_clw_timer_N_51456) + ); + defparam plm_fsm_clw_timer_count_i_m3_i_m3_i_m3_0_19_.INIT = 8'hD8; + LUT3_L plm_fsm_clw_timer_count_i_m3_i_m3_i_m3_0_19_ ( + .I0(cfg_cfg_5072[507]), + .I1(plm_fsm_clw_timer_reg_count[11]), + .I2(plm_fsm_clw_timer_reg_count[19]), + .LO(plm_fsm_clw_timer_N_51455) + ); + defparam plm_fsm_clw_timer_count_i_m3_i_m3_i_m3_0_18_.INIT = 8'hD8; + LUT3 plm_fsm_clw_timer_count_i_m3_i_m3_i_m3_0_18_ ( + .I0(cfg_cfg_5072[507]), + .I1(plm_fsm_clw_timer_reg_count[10]), + .I2(plm_fsm_clw_timer_reg_count[18]), + .O(plm_fsm_clw_timer_N_51454) + ); + defparam plm_fsm_clw_timer_un1_expired_2ms_0_a2_0_a4_0.INIT = 16'h0415; + LUT4_L plm_fsm_clw_timer_un1_expired_2ms_0_a2_0_a4_0 ( + .I0(plm_fsm_clw_timer_N_51455), + .I1(cfg_cfg_5072[507]), + .I2(plm_fsm_clw_timer_reg_count[14]), + .I3(plm_fsm_clw_timer_reg_count[22]), + .LO(plm_fsm_clw_timer_un1_expired_2ms_0_a2_0_a4_0_964) + ); + defparam plm_fsm_clw_timer_un1_expired_2ms_0_a2_0_a4.INIT = 16'h0100; + LUT4 plm_fsm_clw_timer_un1_expired_2ms_0_a2_0_a4 ( + .I0(plm_fsm_clw_timer_N_51454), + .I1(plm_fsm_clw_timer_N_51456), + .I2(plm_fsm_clw_timer_N_51457), + .I3(plm_fsm_clw_timer_un1_expired_2ms_0_a2_0_a4_0_964), + .O(plm_fsm_N_51318) + ); + FDC plm_fsm_clw_timer_reg_count_22_ ( + .C(mgt_clk), + .D(plm_fsm_clw_timer_reg_count_s[22]), + .Q(plm_fsm_clw_timer_reg_count[22]), + .CLR(plm_rst) + ); + FDC plm_fsm_clw_timer_reg_count_21_ ( + .C(mgt_clk), + .D(plm_fsm_clw_timer_reg_count_s[21]), + .Q(plm_fsm_clw_timer_reg_count[21]), + .CLR(plm_rst) + ); + FDC plm_fsm_clw_timer_reg_count_20_ ( + .C(mgt_clk), + .D(plm_fsm_clw_timer_reg_count_s[20]), + .Q(plm_fsm_clw_timer_reg_count[20]), + .CLR(plm_rst) + ); + FDC plm_fsm_clw_timer_reg_count_19_ ( + .C(mgt_clk), + .D(plm_fsm_clw_timer_reg_count_s[19]), + .Q(plm_fsm_clw_timer_reg_count[19]), + .CLR(plm_rst) + ); + FDC plm_fsm_clw_timer_reg_count_18_ ( + .C(mgt_clk), + .D(plm_fsm_clw_timer_reg_count_s[18]), + .Q(plm_fsm_clw_timer_reg_count[18]), + .CLR(plm_rst) + ); + FDC plm_fsm_clw_timer_reg_count_17_ ( + .C(mgt_clk), + .D(plm_fsm_clw_timer_reg_count_s[17]), + .Q(plm_fsm_clw_timer_reg_count[17]), + .CLR(plm_rst) + ); + FDC plm_fsm_clw_timer_reg_count_16_ ( + .C(mgt_clk), + .D(plm_fsm_clw_timer_reg_count_s[16]), + .Q(plm_fsm_clw_timer_reg_count[16]), + .CLR(plm_rst) + ); + FDC plm_fsm_clw_timer_reg_count_15_ ( + .C(mgt_clk), + .D(plm_fsm_clw_timer_reg_count_s[15]), + .Q(plm_fsm_clw_timer_reg_count[15]), + .CLR(plm_rst) + ); + FDC plm_fsm_clw_timer_reg_count_14_ ( + .C(mgt_clk), + .D(plm_fsm_clw_timer_reg_count_s[14]), + .Q(plm_fsm_clw_timer_reg_count[14]), + .CLR(plm_rst) + ); + FDC plm_fsm_clw_timer_reg_count_13_ ( + .C(mgt_clk), + .D(plm_fsm_clw_timer_reg_count_s[13]), + .Q(plm_fsm_clw_timer_reg_count[13]), + .CLR(plm_rst) + ); + FDC plm_fsm_clw_timer_reg_count_12_ ( + .C(mgt_clk), + .D(plm_fsm_clw_timer_reg_count_s[12]), + .Q(plm_fsm_clw_timer_reg_count[12]), + .CLR(plm_rst) + ); + FDC plm_fsm_clw_timer_reg_count_11_ ( + .C(mgt_clk), + .D(plm_fsm_clw_timer_reg_count_s[11]), + .Q(plm_fsm_clw_timer_reg_count[11]), + .CLR(plm_rst) + ); + FDC plm_fsm_clw_timer_reg_count_10_ ( + .C(mgt_clk), + .D(plm_fsm_clw_timer_reg_count_s[10]), + .Q(plm_fsm_clw_timer_reg_count[10]), + .CLR(plm_rst) + ); + FDC plm_fsm_clw_timer_reg_count_9_ ( + .C(mgt_clk), + .D(plm_fsm_clw_timer_reg_count_s[9]), + .Q(plm_fsm_clw_timer_reg_count[9]), + .CLR(plm_rst) + ); + FDC plm_fsm_clw_timer_reg_count_8_ ( + .C(mgt_clk), + .D(plm_fsm_clw_timer_reg_count_s[8]), + .Q(plm_fsm_clw_timer_reg_count[8]), + .CLR(plm_rst) + ); + FDC plm_fsm_clw_timer_reg_count_7_ ( + .C(mgt_clk), + .D(plm_fsm_clw_timer_reg_count_s[7]), + .Q(plm_fsm_clw_timer_reg_count[7]), + .CLR(plm_rst) + ); + FDC plm_fsm_clw_timer_reg_count_6_ ( + .C(mgt_clk), + .D(plm_fsm_clw_timer_reg_count_s[6]), + .Q(plm_fsm_clw_timer_reg_count[6]), + .CLR(plm_rst) + ); + FDC plm_fsm_clw_timer_reg_count_5_ ( + .C(mgt_clk), + .D(plm_fsm_clw_timer_reg_count_s[5]), + .Q(plm_fsm_clw_timer_reg_count[5]), + .CLR(plm_rst) + ); + FDC plm_fsm_clw_timer_reg_count_4_ ( + .C(mgt_clk), + .D(plm_fsm_clw_timer_reg_count_s[4]), + .Q(plm_fsm_clw_timer_reg_count[4]), + .CLR(plm_rst) + ); + FDC plm_fsm_clw_timer_reg_count_3_ ( + .C(mgt_clk), + .D(plm_fsm_clw_timer_reg_count_s[3]), + .Q(plm_fsm_clw_timer_reg_count[3]), + .CLR(plm_rst) + ); + FDC plm_fsm_clw_timer_reg_count_2_ ( + .C(mgt_clk), + .D(plm_fsm_clw_timer_reg_count_s[2]), + .Q(plm_fsm_clw_timer_reg_count[2]), + .CLR(plm_rst) + ); + FDC plm_fsm_clw_timer_reg_count_1_ ( + .C(mgt_clk), + .D(plm_fsm_clw_timer_reg_count_s[1]), + .Q(plm_fsm_clw_timer_reg_count[1]), + .CLR(plm_rst) + ); + FDC plm_fsm_clw_timer_reg_count_0_ ( + .C(mgt_clk), + .D(plm_fsm_clw_timer_reg_count_s[0]), + .Q(plm_fsm_clw_timer_reg_count[0]), + .CLR(plm_rst) + ); + defparam plm_fsm_clw_timer_reg_count_qxu_0_0_.INIT = 4'h8; + LUT2_L plm_fsm_clw_timer_reg_count_qxu_0_0_ ( + .I0(plm_fsm_clw_timer_reg_count[0]), + .I1(plm_fsm_reg_state_7__874), + .LO(plm_fsm_clw_timer_reg_count_qxu[0]) + ); + defparam plm_fsm_clw_timer_reg_count_qxu_0_1_.INIT = 4'h8; + LUT2_L plm_fsm_clw_timer_reg_count_qxu_0_1_ ( + .I0(plm_fsm_clw_timer_reg_count[1]), + .I1(plm_fsm_reg_state_7__874), + .LO(plm_fsm_clw_timer_reg_count_qxu[1]) + ); + defparam plm_fsm_clw_timer_reg_count_qxu_0_2_.INIT = 4'h8; + LUT2_L plm_fsm_clw_timer_reg_count_qxu_0_2_ ( + .I0(plm_fsm_clw_timer_reg_count[2]), + .I1(plm_fsm_reg_state_7__874), + .LO(plm_fsm_clw_timer_reg_count_qxu[2]) + ); + defparam plm_fsm_clw_timer_reg_count_qxu_0_3_.INIT = 4'h8; + LUT2_L plm_fsm_clw_timer_reg_count_qxu_0_3_ ( + .I0(plm_fsm_clw_timer_reg_count[3]), + .I1(plm_fsm_reg_state_7__874), + .LO(plm_fsm_clw_timer_reg_count_qxu[3]) + ); + defparam plm_fsm_clw_timer_reg_count_qxu_0_4_.INIT = 4'h8; + LUT2_L plm_fsm_clw_timer_reg_count_qxu_0_4_ ( + .I0(plm_fsm_clw_timer_reg_count[4]), + .I1(plm_fsm_reg_state_7__874), + .LO(plm_fsm_clw_timer_reg_count_qxu[4]) + ); + defparam plm_fsm_clw_timer_reg_count_qxu_0_5_.INIT = 4'h8; + LUT2_L plm_fsm_clw_timer_reg_count_qxu_0_5_ ( + .I0(plm_fsm_clw_timer_reg_count[5]), + .I1(plm_fsm_reg_state_7__874), + .LO(plm_fsm_clw_timer_reg_count_qxu[5]) + ); + defparam plm_fsm_clw_timer_reg_count_qxu_0_6_.INIT = 4'h8; + LUT2_L plm_fsm_clw_timer_reg_count_qxu_0_6_ ( + .I0(plm_fsm_clw_timer_reg_count[6]), + .I1(plm_fsm_reg_state_7__874), + .LO(plm_fsm_clw_timer_reg_count_qxu[6]) + ); + defparam plm_fsm_clw_timer_reg_count_qxu_0_7_.INIT = 4'h8; + LUT2_L plm_fsm_clw_timer_reg_count_qxu_0_7_ ( + .I0(plm_fsm_clw_timer_reg_count[7]), + .I1(plm_fsm_reg_state_7__874), + .LO(plm_fsm_clw_timer_reg_count_qxu[7]) + ); + defparam plm_fsm_clw_timer_reg_count_qxu_0_8_.INIT = 4'h8; + LUT2_L plm_fsm_clw_timer_reg_count_qxu_0_8_ ( + .I0(plm_fsm_clw_timer_reg_count[8]), + .I1(plm_fsm_reg_state_7__874), + .LO(plm_fsm_clw_timer_reg_count_qxu[8]) + ); + defparam plm_fsm_clw_timer_reg_count_qxu_0_9_.INIT = 4'h8; + LUT2_L plm_fsm_clw_timer_reg_count_qxu_0_9_ ( + .I0(plm_fsm_clw_timer_reg_count[9]), + .I1(plm_fsm_reg_state_7__874), + .LO(plm_fsm_clw_timer_reg_count_qxu[9]) + ); + defparam plm_fsm_clw_timer_reg_count_qxu_0_10_.INIT = 4'h8; + LUT2_L plm_fsm_clw_timer_reg_count_qxu_0_10_ ( + .I0(plm_fsm_clw_timer_reg_count[10]), + .I1(plm_fsm_reg_state_7__874), + .LO(plm_fsm_clw_timer_reg_count_qxu[10]) + ); + defparam plm_fsm_clw_timer_reg_count_qxu_0_11_.INIT = 4'h8; + LUT2_L plm_fsm_clw_timer_reg_count_qxu_0_11_ ( + .I0(plm_fsm_clw_timer_reg_count[11]), + .I1(plm_fsm_reg_state_7__874), + .LO(plm_fsm_clw_timer_reg_count_qxu[11]) + ); + defparam plm_fsm_clw_timer_reg_count_qxu_0_12_.INIT = 4'h8; + LUT2_L plm_fsm_clw_timer_reg_count_qxu_0_12_ ( + .I0(plm_fsm_clw_timer_reg_count[12]), + .I1(plm_fsm_reg_state_7__874), + .LO(plm_fsm_clw_timer_reg_count_qxu[12]) + ); + defparam plm_fsm_clw_timer_reg_count_qxu_0_13_.INIT = 4'h8; + LUT2_L plm_fsm_clw_timer_reg_count_qxu_0_13_ ( + .I0(plm_fsm_clw_timer_reg_count[13]), + .I1(plm_fsm_reg_state_7__874), + .LO(plm_fsm_clw_timer_reg_count_qxu[13]) + ); + defparam plm_fsm_clw_timer_reg_count_qxu_0_14_.INIT = 4'h8; + LUT2_L plm_fsm_clw_timer_reg_count_qxu_0_14_ ( + .I0(plm_fsm_clw_timer_reg_count[14]), + .I1(plm_fsm_reg_state_7__874), + .LO(plm_fsm_clw_timer_reg_count_qxu[14]) + ); + defparam plm_fsm_clw_timer_reg_count_qxu_0_15_.INIT = 4'h8; + LUT2_L plm_fsm_clw_timer_reg_count_qxu_0_15_ ( + .I0(plm_fsm_clw_timer_reg_count[15]), + .I1(plm_fsm_reg_state_7__874), + .LO(plm_fsm_clw_timer_reg_count_qxu[15]) + ); + defparam plm_fsm_clw_timer_reg_count_qxu_0_16_.INIT = 4'h8; + LUT2_L plm_fsm_clw_timer_reg_count_qxu_0_16_ ( + .I0(plm_fsm_clw_timer_reg_count[16]), + .I1(plm_fsm_reg_state_7__874), + .LO(plm_fsm_clw_timer_reg_count_qxu[16]) + ); + defparam plm_fsm_clw_timer_reg_count_qxu_0_17_.INIT = 4'h8; + LUT2_L plm_fsm_clw_timer_reg_count_qxu_0_17_ ( + .I0(plm_fsm_clw_timer_reg_count[17]), + .I1(plm_fsm_reg_state_7__874), + .LO(plm_fsm_clw_timer_reg_count_qxu[17]) + ); + defparam plm_fsm_clw_timer_reg_count_qxu_0_18_.INIT = 4'h8; + LUT2_L plm_fsm_clw_timer_reg_count_qxu_0_18_ ( + .I0(plm_fsm_clw_timer_reg_count[18]), + .I1(plm_fsm_reg_state_7__874), + .LO(plm_fsm_clw_timer_reg_count_qxu[18]) + ); + defparam plm_fsm_clw_timer_reg_count_qxu_0_19_.INIT = 4'h8; + LUT2_L plm_fsm_clw_timer_reg_count_qxu_0_19_ ( + .I0(plm_fsm_clw_timer_reg_count[19]), + .I1(plm_fsm_reg_state_7__874), + .LO(plm_fsm_clw_timer_reg_count_qxu[19]) + ); + defparam plm_fsm_clw_timer_reg_count_qxu_0_20_.INIT = 4'h8; + LUT2_L plm_fsm_clw_timer_reg_count_qxu_0_20_ ( + .I0(plm_fsm_clw_timer_reg_count[20]), + .I1(plm_fsm_reg_state_7__874), + .LO(plm_fsm_clw_timer_reg_count_qxu[20]) + ); + defparam plm_fsm_clw_timer_reg_count_qxu_0_21_.INIT = 4'h8; + LUT2_L plm_fsm_clw_timer_reg_count_qxu_0_21_ ( + .I0(plm_fsm_clw_timer_reg_count[21]), + .I1(plm_fsm_reg_state_7__874), + .LO(plm_fsm_clw_timer_reg_count_qxu[21]) + ); + defparam plm_fsm_clw_timer_reg_count_qxu_0_22_.INIT = 4'h8; + LUT2_L plm_fsm_clw_timer_reg_count_qxu_0_22_ ( + .I0(plm_fsm_clw_timer_reg_count[22]), + .I1(plm_fsm_reg_state_7__874), + .LO(plm_fsm_clw_timer_reg_count_qxu[22]) + ); + GND plm_fsm_cc_timer_GND ( + .G(plm_fsm_cc_timer_GND_965) + ); + MUXCY_L plm_fsm_cc_timer_reg_count_cry_0_ ( + .CI(plm_fsm_N_38123_i_i_907), + .DI(plm_fsm_cc_timer_GND_965), + .LO(plm_fsm_cc_timer_reg_count_cry[0]), + .S(plm_fsm_cc_timer_reg_count_qxu[0]) + ); + XORCY plm_fsm_cc_timer_reg_count_s_0_ ( + .CI(plm_fsm_N_38123_i_i_907), + .LI(plm_fsm_cc_timer_reg_count_qxu[0]), + .O(plm_fsm_cc_timer_reg_count_s[0]) + ); + MUXCY_L plm_fsm_cc_timer_reg_count_cry_1_ ( + .CI(plm_fsm_cc_timer_reg_count_cry[0]), + .DI(plm_fsm_cc_timer_GND_965), + .LO(plm_fsm_cc_timer_reg_count_cry[1]), + .S(plm_fsm_cc_timer_reg_count_qxu[1]) + ); + XORCY plm_fsm_cc_timer_reg_count_s_1_ ( + .CI(plm_fsm_cc_timer_reg_count_cry[0]), + .LI(plm_fsm_cc_timer_reg_count_qxu[1]), + .O(plm_fsm_cc_timer_reg_count_s[1]) + ); + MUXCY_L plm_fsm_cc_timer_reg_count_cry_2_ ( + .CI(plm_fsm_cc_timer_reg_count_cry[1]), + .DI(plm_fsm_cc_timer_GND_965), + .LO(plm_fsm_cc_timer_reg_count_cry[2]), + .S(plm_fsm_cc_timer_reg_count_qxu[2]) + ); + XORCY plm_fsm_cc_timer_reg_count_s_2_ ( + .CI(plm_fsm_cc_timer_reg_count_cry[1]), + .LI(plm_fsm_cc_timer_reg_count_qxu[2]), + .O(plm_fsm_cc_timer_reg_count_s[2]) + ); + MUXCY_L plm_fsm_cc_timer_reg_count_cry_3_ ( + .CI(plm_fsm_cc_timer_reg_count_cry[2]), + .DI(plm_fsm_cc_timer_GND_965), + .LO(plm_fsm_cc_timer_reg_count_cry[3]), + .S(plm_fsm_cc_timer_reg_count_qxu[3]) + ); + XORCY plm_fsm_cc_timer_reg_count_s_3_ ( + .CI(plm_fsm_cc_timer_reg_count_cry[2]), + .LI(plm_fsm_cc_timer_reg_count_qxu[3]), + .O(plm_fsm_cc_timer_reg_count_s[3]) + ); + MUXCY_L plm_fsm_cc_timer_reg_count_cry_4_ ( + .CI(plm_fsm_cc_timer_reg_count_cry[3]), + .DI(plm_fsm_cc_timer_GND_965), + .LO(plm_fsm_cc_timer_reg_count_cry[4]), + .S(plm_fsm_cc_timer_reg_count_qxu[4]) + ); + XORCY plm_fsm_cc_timer_reg_count_s_4_ ( + .CI(plm_fsm_cc_timer_reg_count_cry[3]), + .LI(plm_fsm_cc_timer_reg_count_qxu[4]), + .O(plm_fsm_cc_timer_reg_count_s[4]) + ); + MUXCY_L plm_fsm_cc_timer_reg_count_cry_5_ ( + .CI(plm_fsm_cc_timer_reg_count_cry[4]), + .DI(plm_fsm_cc_timer_GND_965), + .LO(plm_fsm_cc_timer_reg_count_cry[5]), + .S(plm_fsm_cc_timer_reg_count_qxu[5]) + ); + XORCY plm_fsm_cc_timer_reg_count_s_5_ ( + .CI(plm_fsm_cc_timer_reg_count_cry[4]), + .LI(plm_fsm_cc_timer_reg_count_qxu[5]), + .O(plm_fsm_cc_timer_reg_count_s[5]) + ); + MUXCY_L plm_fsm_cc_timer_reg_count_cry_6_ ( + .CI(plm_fsm_cc_timer_reg_count_cry[5]), + .DI(plm_fsm_cc_timer_GND_965), + .LO(plm_fsm_cc_timer_reg_count_cry[6]), + .S(plm_fsm_cc_timer_reg_count_qxu[6]) + ); + XORCY plm_fsm_cc_timer_reg_count_s_6_ ( + .CI(plm_fsm_cc_timer_reg_count_cry[5]), + .LI(plm_fsm_cc_timer_reg_count_qxu[6]), + .O(plm_fsm_cc_timer_reg_count_s[6]) + ); + MUXCY_L plm_fsm_cc_timer_reg_count_cry_7_ ( + .CI(plm_fsm_cc_timer_reg_count_cry[6]), + .DI(plm_fsm_cc_timer_GND_965), + .LO(plm_fsm_cc_timer_reg_count_cry[7]), + .S(plm_fsm_cc_timer_reg_count_qxu[7]) + ); + XORCY plm_fsm_cc_timer_reg_count_s_7_ ( + .CI(plm_fsm_cc_timer_reg_count_cry[6]), + .LI(plm_fsm_cc_timer_reg_count_qxu[7]), + .O(plm_fsm_cc_timer_reg_count_s[7]) + ); + MUXCY_L plm_fsm_cc_timer_reg_count_cry_8_ ( + .CI(plm_fsm_cc_timer_reg_count_cry[7]), + .DI(plm_fsm_cc_timer_GND_965), + .LO(plm_fsm_cc_timer_reg_count_cry[8]), + .S(plm_fsm_cc_timer_reg_count_qxu[8]) + ); + XORCY plm_fsm_cc_timer_reg_count_s_8_ ( + .CI(plm_fsm_cc_timer_reg_count_cry[7]), + .LI(plm_fsm_cc_timer_reg_count_qxu[8]), + .O(plm_fsm_cc_timer_reg_count_s[8]) + ); + MUXCY_L plm_fsm_cc_timer_reg_count_cry_9_ ( + .CI(plm_fsm_cc_timer_reg_count_cry[8]), + .DI(plm_fsm_cc_timer_GND_965), + .LO(plm_fsm_cc_timer_reg_count_cry[9]), + .S(plm_fsm_cc_timer_reg_count_qxu[9]) + ); + XORCY plm_fsm_cc_timer_reg_count_s_9_ ( + .CI(plm_fsm_cc_timer_reg_count_cry[8]), + .LI(plm_fsm_cc_timer_reg_count_qxu[9]), + .O(plm_fsm_cc_timer_reg_count_s[9]) + ); + MUXCY_L plm_fsm_cc_timer_reg_count_cry_10_ ( + .CI(plm_fsm_cc_timer_reg_count_cry[9]), + .DI(plm_fsm_cc_timer_GND_965), + .LO(plm_fsm_cc_timer_reg_count_cry[10]), + .S(plm_fsm_cc_timer_reg_count_qxu[10]) + ); + XORCY plm_fsm_cc_timer_reg_count_s_10_ ( + .CI(plm_fsm_cc_timer_reg_count_cry[9]), + .LI(plm_fsm_cc_timer_reg_count_qxu[10]), + .O(plm_fsm_cc_timer_reg_count_s[10]) + ); + MUXCY_L plm_fsm_cc_timer_reg_count_cry_11_ ( + .CI(plm_fsm_cc_timer_reg_count_cry[10]), + .DI(plm_fsm_cc_timer_GND_965), + .LO(plm_fsm_cc_timer_reg_count_cry[11]), + .S(plm_fsm_cc_timer_reg_count_qxu[11]) + ); + XORCY plm_fsm_cc_timer_reg_count_s_11_ ( + .CI(plm_fsm_cc_timer_reg_count_cry[10]), + .LI(plm_fsm_cc_timer_reg_count_qxu[11]), + .O(plm_fsm_cc_timer_reg_count_s[11]) + ); + MUXCY_L plm_fsm_cc_timer_reg_count_cry_12_ ( + .CI(plm_fsm_cc_timer_reg_count_cry[11]), + .DI(plm_fsm_cc_timer_GND_965), + .LO(plm_fsm_cc_timer_reg_count_cry[12]), + .S(plm_fsm_cc_timer_reg_count_qxu[12]) + ); + XORCY plm_fsm_cc_timer_reg_count_s_12_ ( + .CI(plm_fsm_cc_timer_reg_count_cry[11]), + .LI(plm_fsm_cc_timer_reg_count_qxu[12]), + .O(plm_fsm_cc_timer_reg_count_s[12]) + ); + MUXCY_L plm_fsm_cc_timer_reg_count_cry_13_ ( + .CI(plm_fsm_cc_timer_reg_count_cry[12]), + .DI(plm_fsm_cc_timer_GND_965), + .LO(plm_fsm_cc_timer_reg_count_cry[13]), + .S(plm_fsm_cc_timer_reg_count_qxu[13]) + ); + XORCY plm_fsm_cc_timer_reg_count_s_13_ ( + .CI(plm_fsm_cc_timer_reg_count_cry[12]), + .LI(plm_fsm_cc_timer_reg_count_qxu[13]), + .O(plm_fsm_cc_timer_reg_count_s[13]) + ); + MUXCY_L plm_fsm_cc_timer_reg_count_cry_14_ ( + .CI(plm_fsm_cc_timer_reg_count_cry[13]), + .DI(plm_fsm_cc_timer_GND_965), + .LO(plm_fsm_cc_timer_reg_count_cry[14]), + .S(plm_fsm_cc_timer_reg_count_qxu[14]) + ); + XORCY plm_fsm_cc_timer_reg_count_s_14_ ( + .CI(plm_fsm_cc_timer_reg_count_cry[13]), + .LI(plm_fsm_cc_timer_reg_count_qxu[14]), + .O(plm_fsm_cc_timer_reg_count_s[14]) + ); + MUXCY_L plm_fsm_cc_timer_reg_count_cry_15_ ( + .CI(plm_fsm_cc_timer_reg_count_cry[14]), + .DI(plm_fsm_cc_timer_GND_965), + .LO(plm_fsm_cc_timer_reg_count_cry[15]), + .S(plm_fsm_cc_timer_reg_count_qxu[15]) + ); + XORCY plm_fsm_cc_timer_reg_count_s_15_ ( + .CI(plm_fsm_cc_timer_reg_count_cry[14]), + .LI(plm_fsm_cc_timer_reg_count_qxu[15]), + .O(plm_fsm_cc_timer_reg_count_s[15]) + ); + MUXCY_L plm_fsm_cc_timer_reg_count_cry_16_ ( + .CI(plm_fsm_cc_timer_reg_count_cry[15]), + .DI(plm_fsm_cc_timer_GND_965), + .LO(plm_fsm_cc_timer_reg_count_cry[16]), + .S(plm_fsm_cc_timer_reg_count_qxu[16]) + ); + XORCY plm_fsm_cc_timer_reg_count_s_16_ ( + .CI(plm_fsm_cc_timer_reg_count_cry[15]), + .LI(plm_fsm_cc_timer_reg_count_qxu[16]), + .O(plm_fsm_cc_timer_reg_count_s[16]) + ); + MUXCY_L plm_fsm_cc_timer_reg_count_cry_17_ ( + .CI(plm_fsm_cc_timer_reg_count_cry[16]), + .DI(plm_fsm_cc_timer_GND_965), + .LO(plm_fsm_cc_timer_reg_count_cry[17]), + .S(plm_fsm_cc_timer_reg_count_qxu[17]) + ); + XORCY plm_fsm_cc_timer_reg_count_s_17_ ( + .CI(plm_fsm_cc_timer_reg_count_cry[16]), + .LI(plm_fsm_cc_timer_reg_count_qxu[17]), + .O(plm_fsm_cc_timer_reg_count_s[17]) + ); + MUXCY_L plm_fsm_cc_timer_reg_count_cry_18_ ( + .CI(plm_fsm_cc_timer_reg_count_cry[17]), + .DI(plm_fsm_cc_timer_GND_965), + .LO(plm_fsm_cc_timer_reg_count_cry[18]), + .S(plm_fsm_cc_timer_reg_count_qxu[18]) + ); + XORCY plm_fsm_cc_timer_reg_count_s_18_ ( + .CI(plm_fsm_cc_timer_reg_count_cry[17]), + .LI(plm_fsm_cc_timer_reg_count_qxu[18]), + .O(plm_fsm_cc_timer_reg_count_s[18]) + ); + MUXCY_L plm_fsm_cc_timer_reg_count_cry_19_ ( + .CI(plm_fsm_cc_timer_reg_count_cry[18]), + .DI(plm_fsm_cc_timer_GND_965), + .LO(plm_fsm_cc_timer_reg_count_cry[19]), + .S(plm_fsm_cc_timer_reg_count_qxu[19]) + ); + XORCY plm_fsm_cc_timer_reg_count_s_19_ ( + .CI(plm_fsm_cc_timer_reg_count_cry[18]), + .LI(plm_fsm_cc_timer_reg_count_qxu[19]), + .O(plm_fsm_cc_timer_reg_count_s[19]) + ); + MUXCY_L plm_fsm_cc_timer_reg_count_cry_20_ ( + .CI(plm_fsm_cc_timer_reg_count_cry[19]), + .DI(plm_fsm_cc_timer_GND_965), + .LO(plm_fsm_cc_timer_reg_count_cry[20]), + .S(plm_fsm_cc_timer_reg_count_qxu[20]) + ); + XORCY plm_fsm_cc_timer_reg_count_s_20_ ( + .CI(plm_fsm_cc_timer_reg_count_cry[19]), + .LI(plm_fsm_cc_timer_reg_count_qxu[20]), + .O(plm_fsm_cc_timer_reg_count_s[20]) + ); + MUXCY_L plm_fsm_cc_timer_reg_count_cry_21_ ( + .CI(plm_fsm_cc_timer_reg_count_cry[20]), + .DI(plm_fsm_cc_timer_GND_965), + .LO(plm_fsm_cc_timer_reg_count_cry[21]), + .S(plm_fsm_cc_timer_reg_count_qxu[21]) + ); + XORCY plm_fsm_cc_timer_reg_count_s_21_ ( + .CI(plm_fsm_cc_timer_reg_count_cry[20]), + .LI(plm_fsm_cc_timer_reg_count_qxu[21]), + .O(plm_fsm_cc_timer_reg_count_s[21]) + ); + XORCY plm_fsm_cc_timer_reg_count_s_22_ ( + .CI(plm_fsm_cc_timer_reg_count_cry[21]), + .LI(plm_fsm_cc_timer_reg_count_qxu[22]), + .O(plm_fsm_cc_timer_reg_count_s[22]) + ); + defparam plm_fsm_cc_timer_count_0_18_.INIT = 8'hD8; + LUT3 plm_fsm_cc_timer_count_0_18_ ( + .I0(cfg_cfg_5072[507]), + .I1(plm_fsm_cc_timer_reg_count[10]), + .I2(plm_fsm_cc_timer_reg_count[18]), + .O(plm_fsm_cc_timer_count_18_) + ); + defparam plm_fsm_cc_timer_count_0_20_.INIT = 8'hD8; + LUT3 plm_fsm_cc_timer_count_0_20_ ( + .I0(cfg_cfg_5072[507]), + .I1(plm_fsm_cc_timer_reg_count[12]), + .I2(plm_fsm_cc_timer_reg_count[20]), + .O(plm_fsm_cc_timer_count_20_) + ); + defparam plm_fsm_cc_timer_count_i_m3_i_m3_i_m3_0_21_.INIT = 8'hD8; + LUT3 plm_fsm_cc_timer_count_i_m3_i_m3_i_m3_0_21_ ( + .I0(cfg_cfg_5072[507]), + .I1(plm_fsm_cc_timer_reg_count[13]), + .I2(plm_fsm_cc_timer_reg_count[21]), + .O(plm_fsm_cc_timer_N_51459) + ); + defparam plm_fsm_cc_timer_count_i_m3_i_m3_i_m3_0_22_.INIT = 8'hD8; + LUT3_L plm_fsm_cc_timer_count_i_m3_i_m3_i_m3_0_22_ ( + .I0(cfg_cfg_5072[507]), + .I1(plm_fsm_cc_timer_reg_count[14]), + .I2(plm_fsm_cc_timer_reg_count[22]), + .LO(plm_fsm_cc_timer_N_51460) + ); + defparam plm_fsm_cc_timer_un1_expired_2ms_0_a2_0_a4_0.INIT = 16'h0415; + LUT4_L plm_fsm_cc_timer_un1_expired_2ms_0_a2_0_a4_0 ( + .I0(plm_fsm_cc_timer_N_51460), + .I1(cfg_cfg_5072[507]), + .I2(plm_fsm_cc_timer_reg_count[11]), + .I3(plm_fsm_cc_timer_reg_count[19]), + .LO(plm_fsm_cc_timer_un1_expired_2ms_0_a2_0_a4_0_966) + ); + defparam plm_fsm_cc_timer_un1_expired_2ms_0_a2_0_a4.INIT = 16'h0100; + LUT4 plm_fsm_cc_timer_un1_expired_2ms_0_a2_0_a4 ( + .I0(plm_fsm_cc_timer_N_51459), + .I1(plm_fsm_cc_timer_count_18_), + .I2(plm_fsm_cc_timer_count_20_), + .I3(plm_fsm_cc_timer_un1_expired_2ms_0_a2_0_a4_0_966), + .O(plm_fsm_N_51381) + ); + FDC plm_fsm_cc_timer_reg_count_22_ ( + .C(mgt_clk), + .D(plm_fsm_cc_timer_reg_count_s[22]), + .Q(plm_fsm_cc_timer_reg_count[22]), + .CLR(plm_rst) + ); + FDC plm_fsm_cc_timer_reg_count_21_ ( + .C(mgt_clk), + .D(plm_fsm_cc_timer_reg_count_s[21]), + .Q(plm_fsm_cc_timer_reg_count[21]), + .CLR(plm_rst) + ); + FDC plm_fsm_cc_timer_reg_count_20_ ( + .C(mgt_clk), + .D(plm_fsm_cc_timer_reg_count_s[20]), + .Q(plm_fsm_cc_timer_reg_count[20]), + .CLR(plm_rst) + ); + FDC plm_fsm_cc_timer_reg_count_19_ ( + .C(mgt_clk), + .D(plm_fsm_cc_timer_reg_count_s[19]), + .Q(plm_fsm_cc_timer_reg_count[19]), + .CLR(plm_rst) + ); + FDC plm_fsm_cc_timer_reg_count_18_ ( + .C(mgt_clk), + .D(plm_fsm_cc_timer_reg_count_s[18]), + .Q(plm_fsm_cc_timer_reg_count[18]), + .CLR(plm_rst) + ); + FDC plm_fsm_cc_timer_reg_count_17_ ( + .C(mgt_clk), + .D(plm_fsm_cc_timer_reg_count_s[17]), + .Q(plm_fsm_cc_timer_reg_count[17]), + .CLR(plm_rst) + ); + FDC plm_fsm_cc_timer_reg_count_16_ ( + .C(mgt_clk), + .D(plm_fsm_cc_timer_reg_count_s[16]), + .Q(plm_fsm_cc_timer_reg_count[16]), + .CLR(plm_rst) + ); + FDC plm_fsm_cc_timer_reg_count_15_ ( + .C(mgt_clk), + .D(plm_fsm_cc_timer_reg_count_s[15]), + .Q(plm_fsm_cc_timer_reg_count[15]), + .CLR(plm_rst) + ); + FDC plm_fsm_cc_timer_reg_count_14_ ( + .C(mgt_clk), + .D(plm_fsm_cc_timer_reg_count_s[14]), + .Q(plm_fsm_cc_timer_reg_count[14]), + .CLR(plm_rst) + ); + FDC plm_fsm_cc_timer_reg_count_13_ ( + .C(mgt_clk), + .D(plm_fsm_cc_timer_reg_count_s[13]), + .Q(plm_fsm_cc_timer_reg_count[13]), + .CLR(plm_rst) + ); + FDC plm_fsm_cc_timer_reg_count_12_ ( + .C(mgt_clk), + .D(plm_fsm_cc_timer_reg_count_s[12]), + .Q(plm_fsm_cc_timer_reg_count[12]), + .CLR(plm_rst) + ); + FDC plm_fsm_cc_timer_reg_count_11_ ( + .C(mgt_clk), + .D(plm_fsm_cc_timer_reg_count_s[11]), + .Q(plm_fsm_cc_timer_reg_count[11]), + .CLR(plm_rst) + ); + FDC plm_fsm_cc_timer_reg_count_10_ ( + .C(mgt_clk), + .D(plm_fsm_cc_timer_reg_count_s[10]), + .Q(plm_fsm_cc_timer_reg_count[10]), + .CLR(plm_rst) + ); + FDC plm_fsm_cc_timer_reg_count_9_ ( + .C(mgt_clk), + .D(plm_fsm_cc_timer_reg_count_s[9]), + .Q(plm_fsm_cc_timer_reg_count[9]), + .CLR(plm_rst) + ); + FDC plm_fsm_cc_timer_reg_count_8_ ( + .C(mgt_clk), + .D(plm_fsm_cc_timer_reg_count_s[8]), + .Q(plm_fsm_cc_timer_reg_count[8]), + .CLR(plm_rst) + ); + FDC plm_fsm_cc_timer_reg_count_7_ ( + .C(mgt_clk), + .D(plm_fsm_cc_timer_reg_count_s[7]), + .Q(plm_fsm_cc_timer_reg_count[7]), + .CLR(plm_rst) + ); + FDC plm_fsm_cc_timer_reg_count_6_ ( + .C(mgt_clk), + .D(plm_fsm_cc_timer_reg_count_s[6]), + .Q(plm_fsm_cc_timer_reg_count[6]), + .CLR(plm_rst) + ); + FDC plm_fsm_cc_timer_reg_count_5_ ( + .C(mgt_clk), + .D(plm_fsm_cc_timer_reg_count_s[5]), + .Q(plm_fsm_cc_timer_reg_count[5]), + .CLR(plm_rst) + ); + FDC plm_fsm_cc_timer_reg_count_4_ ( + .C(mgt_clk), + .D(plm_fsm_cc_timer_reg_count_s[4]), + .Q(plm_fsm_cc_timer_reg_count[4]), + .CLR(plm_rst) + ); + FDC plm_fsm_cc_timer_reg_count_3_ ( + .C(mgt_clk), + .D(plm_fsm_cc_timer_reg_count_s[3]), + .Q(plm_fsm_cc_timer_reg_count[3]), + .CLR(plm_rst) + ); + FDC plm_fsm_cc_timer_reg_count_2_ ( + .C(mgt_clk), + .D(plm_fsm_cc_timer_reg_count_s[2]), + .Q(plm_fsm_cc_timer_reg_count[2]), + .CLR(plm_rst) + ); + FDC plm_fsm_cc_timer_reg_count_1_ ( + .C(mgt_clk), + .D(plm_fsm_cc_timer_reg_count_s[1]), + .Q(plm_fsm_cc_timer_reg_count[1]), + .CLR(plm_rst) + ); + FDC plm_fsm_cc_timer_reg_count_0_ ( + .C(mgt_clk), + .D(plm_fsm_cc_timer_reg_count_s[0]), + .Q(plm_fsm_cc_timer_reg_count[0]), + .CLR(plm_rst) + ); + defparam plm_fsm_cc_timer_reg_count_qxu_0_0_.INIT = 4'h4; + LUT2_L plm_fsm_cc_timer_reg_count_qxu_0_0_ ( + .I0(N_38123_i), + .I1(plm_fsm_cc_timer_reg_count[0]), + .LO(plm_fsm_cc_timer_reg_count_qxu[0]) + ); + defparam plm_fsm_cc_timer_reg_count_qxu_0_1_.INIT = 4'h4; + LUT2_L plm_fsm_cc_timer_reg_count_qxu_0_1_ ( + .I0(N_38123_i), + .I1(plm_fsm_cc_timer_reg_count[1]), + .LO(plm_fsm_cc_timer_reg_count_qxu[1]) + ); + defparam plm_fsm_cc_timer_reg_count_qxu_0_2_.INIT = 4'h4; + LUT2_L plm_fsm_cc_timer_reg_count_qxu_0_2_ ( + .I0(N_38123_i), + .I1(plm_fsm_cc_timer_reg_count[2]), + .LO(plm_fsm_cc_timer_reg_count_qxu[2]) + ); + defparam plm_fsm_cc_timer_reg_count_qxu_0_3_.INIT = 4'h4; + LUT2_L plm_fsm_cc_timer_reg_count_qxu_0_3_ ( + .I0(N_38123_i), + .I1(plm_fsm_cc_timer_reg_count[3]), + .LO(plm_fsm_cc_timer_reg_count_qxu[3]) + ); + defparam plm_fsm_cc_timer_reg_count_qxu_0_4_.INIT = 4'h4; + LUT2_L plm_fsm_cc_timer_reg_count_qxu_0_4_ ( + .I0(N_38123_i), + .I1(plm_fsm_cc_timer_reg_count[4]), + .LO(plm_fsm_cc_timer_reg_count_qxu[4]) + ); + defparam plm_fsm_cc_timer_reg_count_qxu_0_5_.INIT = 4'h4; + LUT2_L plm_fsm_cc_timer_reg_count_qxu_0_5_ ( + .I0(N_38123_i), + .I1(plm_fsm_cc_timer_reg_count[5]), + .LO(plm_fsm_cc_timer_reg_count_qxu[5]) + ); + defparam plm_fsm_cc_timer_reg_count_qxu_0_6_.INIT = 4'h4; + LUT2_L plm_fsm_cc_timer_reg_count_qxu_0_6_ ( + .I0(N_38123_i), + .I1(plm_fsm_cc_timer_reg_count[6]), + .LO(plm_fsm_cc_timer_reg_count_qxu[6]) + ); + defparam plm_fsm_cc_timer_reg_count_qxu_0_7_.INIT = 4'h4; + LUT2_L plm_fsm_cc_timer_reg_count_qxu_0_7_ ( + .I0(N_38123_i), + .I1(plm_fsm_cc_timer_reg_count[7]), + .LO(plm_fsm_cc_timer_reg_count_qxu[7]) + ); + defparam plm_fsm_cc_timer_reg_count_qxu_0_8_.INIT = 4'h4; + LUT2_L plm_fsm_cc_timer_reg_count_qxu_0_8_ ( + .I0(N_38123_i), + .I1(plm_fsm_cc_timer_reg_count[8]), + .LO(plm_fsm_cc_timer_reg_count_qxu[8]) + ); + defparam plm_fsm_cc_timer_reg_count_qxu_0_9_.INIT = 4'h4; + LUT2_L plm_fsm_cc_timer_reg_count_qxu_0_9_ ( + .I0(N_38123_i), + .I1(plm_fsm_cc_timer_reg_count[9]), + .LO(plm_fsm_cc_timer_reg_count_qxu[9]) + ); + defparam plm_fsm_cc_timer_reg_count_qxu_0_10_.INIT = 4'h4; + LUT2_L plm_fsm_cc_timer_reg_count_qxu_0_10_ ( + .I0(N_38123_i), + .I1(plm_fsm_cc_timer_reg_count[10]), + .LO(plm_fsm_cc_timer_reg_count_qxu[10]) + ); + defparam plm_fsm_cc_timer_reg_count_qxu_0_11_.INIT = 4'h4; + LUT2_L plm_fsm_cc_timer_reg_count_qxu_0_11_ ( + .I0(N_38123_i), + .I1(plm_fsm_cc_timer_reg_count[11]), + .LO(plm_fsm_cc_timer_reg_count_qxu[11]) + ); + defparam plm_fsm_cc_timer_reg_count_qxu_0_12_.INIT = 4'h4; + LUT2_L plm_fsm_cc_timer_reg_count_qxu_0_12_ ( + .I0(N_38123_i), + .I1(plm_fsm_cc_timer_reg_count[12]), + .LO(plm_fsm_cc_timer_reg_count_qxu[12]) + ); + defparam plm_fsm_cc_timer_reg_count_qxu_0_13_.INIT = 4'h4; + LUT2_L plm_fsm_cc_timer_reg_count_qxu_0_13_ ( + .I0(N_38123_i), + .I1(plm_fsm_cc_timer_reg_count[13]), + .LO(plm_fsm_cc_timer_reg_count_qxu[13]) + ); + defparam plm_fsm_cc_timer_reg_count_qxu_0_14_.INIT = 4'h4; + LUT2_L plm_fsm_cc_timer_reg_count_qxu_0_14_ ( + .I0(N_38123_i), + .I1(plm_fsm_cc_timer_reg_count[14]), + .LO(plm_fsm_cc_timer_reg_count_qxu[14]) + ); + defparam plm_fsm_cc_timer_reg_count_qxu_0_15_.INIT = 4'h4; + LUT2_L plm_fsm_cc_timer_reg_count_qxu_0_15_ ( + .I0(N_38123_i), + .I1(plm_fsm_cc_timer_reg_count[15]), + .LO(plm_fsm_cc_timer_reg_count_qxu[15]) + ); + defparam plm_fsm_cc_timer_reg_count_qxu_0_16_.INIT = 4'h4; + LUT2_L plm_fsm_cc_timer_reg_count_qxu_0_16_ ( + .I0(N_38123_i), + .I1(plm_fsm_cc_timer_reg_count[16]), + .LO(plm_fsm_cc_timer_reg_count_qxu[16]) + ); + defparam plm_fsm_cc_timer_reg_count_qxu_0_17_.INIT = 4'h4; + LUT2_L plm_fsm_cc_timer_reg_count_qxu_0_17_ ( + .I0(N_38123_i), + .I1(plm_fsm_cc_timer_reg_count[17]), + .LO(plm_fsm_cc_timer_reg_count_qxu[17]) + ); + defparam plm_fsm_cc_timer_reg_count_qxu_0_18_.INIT = 4'h4; + LUT2_L plm_fsm_cc_timer_reg_count_qxu_0_18_ ( + .I0(N_38123_i), + .I1(plm_fsm_cc_timer_reg_count[18]), + .LO(plm_fsm_cc_timer_reg_count_qxu[18]) + ); + defparam plm_fsm_cc_timer_reg_count_qxu_0_19_.INIT = 4'h4; + LUT2_L plm_fsm_cc_timer_reg_count_qxu_0_19_ ( + .I0(N_38123_i), + .I1(plm_fsm_cc_timer_reg_count[19]), + .LO(plm_fsm_cc_timer_reg_count_qxu[19]) + ); + defparam plm_fsm_cc_timer_reg_count_qxu_0_20_.INIT = 4'h4; + LUT2_L plm_fsm_cc_timer_reg_count_qxu_0_20_ ( + .I0(N_38123_i), + .I1(plm_fsm_cc_timer_reg_count[20]), + .LO(plm_fsm_cc_timer_reg_count_qxu[20]) + ); + defparam plm_fsm_cc_timer_reg_count_qxu_0_21_.INIT = 4'h4; + LUT2_L plm_fsm_cc_timer_reg_count_qxu_0_21_ ( + .I0(N_38123_i), + .I1(plm_fsm_cc_timer_reg_count[21]), + .LO(plm_fsm_cc_timer_reg_count_qxu[21]) + ); + defparam plm_fsm_cc_timer_reg_count_qxu_0_22_.INIT = 4'h4; + LUT2_L plm_fsm_cc_timer_reg_count_qxu_0_22_ ( + .I0(N_38123_i), + .I1(plm_fsm_cc_timer_reg_count[22]), + .LO(plm_fsm_cc_timer_reg_count_qxu[22]) + ); + VCC plm_fsm_cc_counter0_VCC ( + .P(plm_fsm_cc_counter0_VCC_967) + ); + MUXCY_L plm_fsm_cc_counter0_reg_rx_count_cry_0_ ( + .CI(N_24768_i_i_21), + .DI(plm_fsm_cc_counter0_VCC_967), + .LO(plm_fsm_cc_counter0_reg_rx_count_cry[0]), + .S(plm_fsm_cc_counter0_reg_rx_count_qxu[0]) + ); + XORCY plm_fsm_cc_counter0_reg_rx_count_s_0_ ( + .CI(N_24768_i_i_21), + .LI(plm_fsm_cc_counter0_reg_rx_count_qxu[0]), + .O(plm_fsm_cc_counter0_reg_rx_count_s[0]) + ); + MUXCY_L plm_fsm_cc_counter0_reg_rx_count_cry_1_ ( + .CI(plm_fsm_cc_counter0_reg_rx_count_cry[0]), + .DI(plm_fsm_cc_counter0_VCC_967), + .LO(plm_fsm_cc_counter0_reg_rx_count_cry[1]), + .S(plm_fsm_cc_counter0_reg_rx_count_qxu[1]) + ); + XORCY plm_fsm_cc_counter0_reg_rx_count_s_1_ ( + .CI(plm_fsm_cc_counter0_reg_rx_count_cry[0]), + .LI(plm_fsm_cc_counter0_reg_rx_count_qxu[1]), + .O(plm_fsm_cc_counter0_reg_rx_count_s[1]) + ); + MUXCY_L plm_fsm_cc_counter0_reg_rx_count_cry_2_ ( + .CI(plm_fsm_cc_counter0_reg_rx_count_cry[1]), + .DI(plm_fsm_cc_counter0_VCC_967), + .LO(plm_fsm_cc_counter0_reg_rx_count_cry[2]), + .S(plm_fsm_cc_counter0_reg_rx_count_qxu[2]) + ); + XORCY plm_fsm_cc_counter0_reg_rx_count_s_2_ ( + .CI(plm_fsm_cc_counter0_reg_rx_count_cry[1]), + .LI(plm_fsm_cc_counter0_reg_rx_count_qxu[2]), + .O(plm_fsm_cc_counter0_reg_rx_count_s[2]) + ); + MUXCY_L plm_fsm_cc_counter0_reg_rx_count_cry_3_ ( + .CI(plm_fsm_cc_counter0_reg_rx_count_cry[2]), + .DI(plm_fsm_cc_counter0_VCC_967), + .LO(plm_fsm_cc_counter0_reg_rx_count_cry[3]), + .S(plm_fsm_cc_counter0_reg_rx_count_qxu[3]) + ); + XORCY plm_fsm_cc_counter0_reg_rx_count_s_3_ ( + .CI(plm_fsm_cc_counter0_reg_rx_count_cry[2]), + .LI(plm_fsm_cc_counter0_reg_rx_count_qxu[3]), + .O(plm_fsm_cc_counter0_reg_rx_count_s[3]) + ); + MUXCY_L plm_fsm_cc_counter0_reg_rx_count_cry_4_ ( + .CI(plm_fsm_cc_counter0_reg_rx_count_cry[3]), + .DI(plm_fsm_cc_counter0_VCC_967), + .LO(plm_fsm_cc_counter0_reg_rx_count_cry[4]), + .S(plm_fsm_cc_counter0_reg_rx_count_qxu[4]) + ); + XORCY plm_fsm_cc_counter0_reg_rx_count_s_4_ ( + .CI(plm_fsm_cc_counter0_reg_rx_count_cry[3]), + .LI(plm_fsm_cc_counter0_reg_rx_count_qxu[4]), + .O(plm_fsm_cc_counter0_reg_rx_count_s[4]) + ); + MUXCY_L plm_fsm_cc_counter0_reg_rx_count_cry_5_ ( + .CI(plm_fsm_cc_counter0_reg_rx_count_cry[4]), + .DI(plm_fsm_cc_counter0_VCC_967), + .LO(plm_fsm_cc_counter0_reg_rx_count_cry[5]), + .S(plm_fsm_cc_counter0_reg_rx_count_qxu[5]) + ); + XORCY plm_fsm_cc_counter0_reg_rx_count_s_5_ ( + .CI(plm_fsm_cc_counter0_reg_rx_count_cry[4]), + .LI(plm_fsm_cc_counter0_reg_rx_count_qxu[5]), + .O(plm_fsm_cc_counter0_reg_rx_count_s[5]) + ); + MUXCY_L plm_fsm_cc_counter0_reg_rx_count_cry_6_ ( + .CI(plm_fsm_cc_counter0_reg_rx_count_cry[5]), + .DI(plm_fsm_cc_counter0_VCC_967), + .LO(plm_fsm_cc_counter0_reg_rx_count_cry[6]), + .S(plm_fsm_cc_counter0_reg_rx_count_qxu[6]) + ); + XORCY plm_fsm_cc_counter0_reg_rx_count_s_6_ ( + .CI(plm_fsm_cc_counter0_reg_rx_count_cry[5]), + .LI(plm_fsm_cc_counter0_reg_rx_count_qxu[6]), + .O(plm_fsm_cc_counter0_reg_rx_count_s[6]) + ); + XORCY plm_fsm_cc_counter0_reg_rx_count_s_7_ ( + .CI(plm_fsm_cc_counter0_reg_rx_count_cry[6]), + .LI(plm_fsm_cc_counter0_reg_rx_count_qxu[7]), + .O(plm_fsm_cc_counter0_reg_rx_count_s[7]) + ); + MUXCY_L plm_fsm_cc_counter0_reg_tx_count_cry_0_ ( + .CI(plm_fsm_cc_counter0_N_24684_i_i_968), + .DI(plm_fsm_cc_counter0_VCC_967), + .LO(plm_fsm_cc_counter0_reg_tx_count_cry[0]), + .S(plm_fsm_cc_counter0_reg_tx_count_qxu[0]) + ); + XORCY plm_fsm_cc_counter0_reg_tx_count_s_0_ ( + .CI(plm_fsm_cc_counter0_N_24684_i_i_968), + .LI(plm_fsm_cc_counter0_reg_tx_count_qxu[0]), + .O(plm_fsm_cc_counter0_reg_tx_count_s[0]) + ); + MUXCY_L plm_fsm_cc_counter0_reg_tx_count_cry_1_ ( + .CI(plm_fsm_cc_counter0_reg_tx_count_cry[0]), + .DI(plm_fsm_cc_counter0_VCC_967), + .LO(plm_fsm_cc_counter0_reg_tx_count_cry[1]), + .S(plm_fsm_cc_counter0_reg_tx_count_qxu[1]) + ); + XORCY plm_fsm_cc_counter0_reg_tx_count_s_1_ ( + .CI(plm_fsm_cc_counter0_reg_tx_count_cry[0]), + .LI(plm_fsm_cc_counter0_reg_tx_count_qxu[1]), + .O(plm_fsm_cc_counter0_reg_tx_count_s[1]) + ); + MUXCY_L plm_fsm_cc_counter0_reg_tx_count_cry_2_ ( + .CI(plm_fsm_cc_counter0_reg_tx_count_cry[1]), + .DI(plm_fsm_cc_counter0_VCC_967), + .LO(plm_fsm_cc_counter0_reg_tx_count_cry[2]), + .S(plm_fsm_cc_counter0_reg_tx_count_qxu[2]) + ); + XORCY plm_fsm_cc_counter0_reg_tx_count_s_2_ ( + .CI(plm_fsm_cc_counter0_reg_tx_count_cry[1]), + .LI(plm_fsm_cc_counter0_reg_tx_count_qxu[2]), + .O(plm_fsm_cc_counter0_reg_tx_count_s[2]) + ); + MUXCY_L plm_fsm_cc_counter0_reg_tx_count_cry_3_ ( + .CI(plm_fsm_cc_counter0_reg_tx_count_cry[2]), + .DI(plm_fsm_cc_counter0_VCC_967), + .LO(plm_fsm_cc_counter0_reg_tx_count_cry[3]), + .S(plm_fsm_cc_counter0_reg_tx_count_qxu[3]) + ); + XORCY plm_fsm_cc_counter0_reg_tx_count_s_3_ ( + .CI(plm_fsm_cc_counter0_reg_tx_count_cry[2]), + .LI(plm_fsm_cc_counter0_reg_tx_count_qxu[3]), + .O(plm_fsm_cc_counter0_reg_tx_count_s[3]) + ); + MUXCY_L plm_fsm_cc_counter0_reg_tx_count_cry_4_ ( + .CI(plm_fsm_cc_counter0_reg_tx_count_cry[3]), + .DI(plm_fsm_cc_counter0_VCC_967), + .LO(plm_fsm_cc_counter0_reg_tx_count_cry[4]), + .S(plm_fsm_cc_counter0_reg_tx_count_qxu[4]) + ); + XORCY plm_fsm_cc_counter0_reg_tx_count_s_4_ ( + .CI(plm_fsm_cc_counter0_reg_tx_count_cry[3]), + .LI(plm_fsm_cc_counter0_reg_tx_count_qxu[4]), + .O(plm_fsm_cc_counter0_reg_tx_count_s[4]) + ); + MUXCY_L plm_fsm_cc_counter0_reg_tx_count_cry_5_ ( + .CI(plm_fsm_cc_counter0_reg_tx_count_cry[4]), + .DI(plm_fsm_cc_counter0_VCC_967), + .LO(plm_fsm_cc_counter0_reg_tx_count_cry[5]), + .S(plm_fsm_cc_counter0_reg_tx_count_qxu[5]) + ); + XORCY plm_fsm_cc_counter0_reg_tx_count_s_5_ ( + .CI(plm_fsm_cc_counter0_reg_tx_count_cry[4]), + .LI(plm_fsm_cc_counter0_reg_tx_count_qxu[5]), + .O(plm_fsm_cc_counter0_reg_tx_count_s[5]) + ); + MUXCY_L plm_fsm_cc_counter0_reg_tx_count_cry_6_ ( + .CI(plm_fsm_cc_counter0_reg_tx_count_cry[5]), + .DI(plm_fsm_cc_counter0_VCC_967), + .LO(plm_fsm_cc_counter0_reg_tx_count_cry[6]), + .S(plm_fsm_cc_counter0_reg_tx_count_qxu[6]) + ); + XORCY plm_fsm_cc_counter0_reg_tx_count_s_6_ ( + .CI(plm_fsm_cc_counter0_reg_tx_count_cry[5]), + .LI(plm_fsm_cc_counter0_reg_tx_count_qxu[6]), + .O(plm_fsm_cc_counter0_reg_tx_count_s[6]) + ); + XORCY plm_fsm_cc_counter0_reg_tx_count_s_7_ ( + .CI(plm_fsm_cc_counter0_reg_tx_count_cry[6]), + .LI(plm_fsm_cc_counter0_reg_tx_count_qxu[7]), + .O(plm_fsm_cc_counter0_reg_tx_count_s[7]) + ); + defparam plm_fsm_cc_counter0_un1_enable_1_0_a2_i_0_o4.INIT = 4'h4; + LUT2 plm_fsm_cc_counter0_un1_enable_1_0_a2_i_0_o4 ( + .I0(N_38123_i), + .I1(plm_fsm_cc_counter0_reg_oneshot_970), + .O(plm_fsm_cc_counter0_N_38368_i) + ); + defparam plm_fsm_cc_counter0_loadable_rx_counter_un1_reg_rx_count_0_a4_4.INIT = 16'h0001; + LUT4 plm_fsm_cc_counter0_loadable_rx_counter_un1_reg_rx_count_0_a4_4 ( + .I0(plm_fsm_cc_counter0_reg_rx_count[0]), + .I1(plm_fsm_cc_counter0_reg_rx_count[1]), + .I2(plm_fsm_cc_counter0_reg_rx_count[2]), + .I3(plm_fsm_cc_counter0_reg_rx_count[3]), + .O(plm_fsm_cc_counter0_un1_reg_rx_count_0_a4_4) + ); + defparam plm_fsm_cc_counter0_loadable_rx_counter_un1_reg_rx_count_0_a4_5.INIT = 16'h0001; + LUT4 plm_fsm_cc_counter0_loadable_rx_counter_un1_reg_rx_count_0_a4_5 ( + .I0(plm_fsm_cc_counter0_reg_rx_count[4]), + .I1(plm_fsm_cc_counter0_reg_rx_count[5]), + .I2(plm_fsm_cc_counter0_reg_rx_count[6]), + .I3(plm_fsm_cc_counter0_reg_rx_count[7]), + .O(plm_fsm_cc_counter0_un1_reg_rx_count_0_a4_5) + ); + defparam plm_fsm_cc_counter0_loadable_tx_counter_un1_reg_tx_count_0_a2_0_a4_4.INIT = 16'h0001; + LUT4 plm_fsm_cc_counter0_loadable_tx_counter_un1_reg_tx_count_0_a2_0_a4_4 ( + .I0(plm_fsm_cc_counter0_reg_tx_count[0]), + .I1(plm_fsm_cc_counter0_reg_tx_count[1]), + .I2(plm_fsm_cc_counter0_reg_tx_count[2]), + .I3(plm_fsm_cc_counter0_reg_tx_count[3]), + .O(plm_fsm_cc_counter0_un1_reg_tx_count_0_a2_0_a4_4) + ); + defparam plm_fsm_cc_counter0_loadable_tx_counter_un1_reg_tx_count_0_a2_0_a4_5.INIT = 16'h0001; + LUT4 plm_fsm_cc_counter0_loadable_tx_counter_un1_reg_tx_count_0_a2_0_a4_5 ( + .I0(plm_fsm_cc_counter0_reg_tx_count[4]), + .I1(plm_fsm_cc_counter0_reg_tx_count[5]), + .I2(plm_fsm_cc_counter0_reg_tx_count[6]), + .I3(plm_fsm_cc_counter0_reg_tx_count[7]), + .O(plm_fsm_cc_counter0_un1_reg_tx_count_0_a2_0_a4_5) + ); + defparam plm_fsm_cc_counter0_oneshot_monitor_N_24639_i_i.INIT = 4'hE; + LUT2 plm_fsm_cc_counter0_oneshot_monitor_N_24639_i_i ( + .I0(plm_reg_ts2_1), + .I1(N_38123_i), + .O(plm_fsm_cc_counter0_N_24639_i_i) + ); + defparam plm_fsm_cc_counter0_un1_enable_1_0_a2_i_0.INIT = 4'h2; + LUT2 plm_fsm_cc_counter0_un1_enable_1_0_a2_i_0 ( + .I0(plm_fsm_cc_counter0_N_38368_i), + .I1(plm_fsm_cc_counter0_reg_tx_expired_972), + .O(plm_fsm_cc_counter0_N_24684_i) + ); + defparam plm_fsm_cc_counter0_loadable_rx_counter_N_69225_i.INIT = 8'hFE; + LUT3 plm_fsm_cc_counter0_loadable_rx_counter_N_69225_i ( + .I0(plm_reg_ts2_1), + .I1(N_38123_i), + .I2(plm_fsm_cc_counter0_reg_rx_expired_250), + .O(plm_fsm_cc_counter0_N_69225_i) + ); + defparam plm_fsm_cc_counter0_N_69088_i.INIT = 8'hD5; + LUT3 plm_fsm_cc_counter0_N_69088_i ( + .I0(plm_fsm_cc_counter0_N_38368_i), + .I1(plm_fsm_cc_counter0_un1_reg_tx_count_0_a2_0_a4_4), + .I2(plm_fsm_cc_counter0_un1_reg_tx_count_0_a2_0_a4_5), + .O(plm_fsm_cc_counter0_N_69088_i_971) + ); + defparam plm_fsm_cc_counter0_loadable_rx_counter_N_69253_i.INIT = 8'hEA; + LUT3 plm_fsm_cc_counter0_loadable_rx_counter_N_69253_i ( + .I0(N_38123_i), + .I1(plm_fsm_cc_counter0_un1_reg_rx_count_0_a4_4), + .I2(plm_fsm_cc_counter0_un1_reg_rx_count_0_a4_5), + .O(plm_fsm_cc_counter0_N_69253_i) + ); + defparam plm_fsm_cc_counter0_N_69226_i.INIT = 4'hB; + LUT2 plm_fsm_cc_counter0_N_69226_i ( + .I0(plm_reg_sym_sent_6_), + .I1(plm_fsm_cc_counter0_N_24684_i), + .O(plm_fsm_cc_counter0_N_69226_i_969) + ); + defparam plm_fsm_cc_counter0_un1_enable_4_i_0_a4_1.INIT = 8'h2A; + LUT3 plm_fsm_cc_counter0_un1_enable_4_i_0_a4_1 ( + .I0(plm_reg_ts2_1), + .I1(N_38124_i), + .I2(plm_rx0_ts2_c), + .O(plm_fsm_N_38512_1) + ); + defparam plm_fsm_cc_counter0_N_69086_i.INIT = 8'hAE; + LUT3_L plm_fsm_cc_counter0_N_69086_i ( + .I0(N_38123_i), + .I1(plm_fsm_N_38512_1), + .I2(plm_fsm_cc_counter0_reg_rx_expired_250), + .LO(plm_fsm_cc_counter0_N_69086_i_973) + ); + defparam plm_fsm_cc_counter0_flagit_reg_expired_5_i_0.INIT = 8'h40; + LUT3_L plm_fsm_cc_counter0_flagit_reg_expired_5_i_0 ( + .I0(N_38123_i), + .I1(plm_fsm_cc_counter0_reg_rx_expired_250), + .I2(plm_fsm_cc_counter0_reg_tx_expired_972), + .LO(plm_fsm_cc_counter0_N_24582_i) + ); + defparam plm_fsm_cc_counter0_N_24684_i_i.INIT = 4'hB; + LUT2 plm_fsm_cc_counter0_N_24684_i_i ( + .I0(plm_fsm_cc_counter0_reg_tx_expired_972), + .I1(plm_fsm_cc_counter0_N_38368_i), + .O(plm_fsm_cc_counter0_N_24684_i_i_968) + ); + FDCE plm_fsm_cc_counter0_reg_tx_count_7_ ( + .CE(plm_fsm_cc_counter0_N_69226_i_969), + .C(mgt_clk), + .D(plm_fsm_cc_counter0_reg_tx_count_s[7]), + .Q(plm_fsm_cc_counter0_reg_tx_count[7]), + .CLR(plm_rst) + ); + FDCE plm_fsm_cc_counter0_reg_tx_count_6_ ( + .CE(plm_fsm_cc_counter0_N_69226_i_969), + .C(mgt_clk), + .D(plm_fsm_cc_counter0_reg_tx_count_s[6]), + .Q(plm_fsm_cc_counter0_reg_tx_count[6]), + .CLR(plm_rst) + ); + FDCE plm_fsm_cc_counter0_reg_tx_count_5_ ( + .CE(plm_fsm_cc_counter0_N_69226_i_969), + .C(mgt_clk), + .D(plm_fsm_cc_counter0_reg_tx_count_s[5]), + .Q(plm_fsm_cc_counter0_reg_tx_count[5]), + .CLR(plm_rst) + ); + FDPE plm_fsm_cc_counter0_reg_tx_count_4_ ( + .PRE(plm_rst), + .CE(plm_fsm_cc_counter0_N_69226_i_969), + .C(mgt_clk), + .D(plm_fsm_cc_counter0_reg_tx_count_s[4]), + .Q(plm_fsm_cc_counter0_reg_tx_count[4]) + ); + FDCE plm_fsm_cc_counter0_reg_tx_count_3_ ( + .CE(plm_fsm_cc_counter0_N_69226_i_969), + .C(mgt_clk), + .D(plm_fsm_cc_counter0_reg_tx_count_s[3]), + .Q(plm_fsm_cc_counter0_reg_tx_count[3]), + .CLR(plm_rst) + ); + FDCE plm_fsm_cc_counter0_reg_tx_count_2_ ( + .CE(plm_fsm_cc_counter0_N_69226_i_969), + .C(mgt_clk), + .D(plm_fsm_cc_counter0_reg_tx_count_s[2]), + .Q(plm_fsm_cc_counter0_reg_tx_count[2]), + .CLR(plm_rst) + ); + FDCE plm_fsm_cc_counter0_reg_tx_count_1_ ( + .CE(plm_fsm_cc_counter0_N_69226_i_969), + .C(mgt_clk), + .D(plm_fsm_cc_counter0_reg_tx_count_s[1]), + .Q(plm_fsm_cc_counter0_reg_tx_count[1]), + .CLR(plm_rst) + ); + FDCE plm_fsm_cc_counter0_reg_tx_count_0_ ( + .CE(plm_fsm_cc_counter0_N_69226_i_969), + .C(mgt_clk), + .D(plm_fsm_cc_counter0_reg_tx_count_s[0]), + .Q(plm_fsm_cc_counter0_reg_tx_count[0]), + .CLR(plm_rst) + ); + FDCE plm_fsm_cc_counter0_reg_rx_count_7_ ( + .CE(plm_fsm_cc_counter0_N_69225_i), + .C(mgt_clk), + .D(plm_fsm_cc_counter0_reg_rx_count_s[7]), + .Q(plm_fsm_cc_counter0_reg_rx_count[7]), + .CLR(plm_rst) + ); + FDCE plm_fsm_cc_counter0_reg_rx_count_6_ ( + .CE(plm_fsm_cc_counter0_N_69225_i), + .C(mgt_clk), + .D(plm_fsm_cc_counter0_reg_rx_count_s[6]), + .Q(plm_fsm_cc_counter0_reg_rx_count[6]), + .CLR(plm_rst) + ); + FDCE plm_fsm_cc_counter0_reg_rx_count_5_ ( + .CE(plm_fsm_cc_counter0_N_69225_i), + .C(mgt_clk), + .D(plm_fsm_cc_counter0_reg_rx_count_s[5]), + .Q(plm_fsm_cc_counter0_reg_rx_count[5]), + .CLR(plm_rst) + ); + FDCE plm_fsm_cc_counter0_reg_rx_count_4_ ( + .CE(plm_fsm_cc_counter0_N_69225_i), + .C(mgt_clk), + .D(plm_fsm_cc_counter0_reg_rx_count_s[4]), + .Q(plm_fsm_cc_counter0_reg_rx_count[4]), + .CLR(plm_rst) + ); + FDPE plm_fsm_cc_counter0_reg_rx_count_3_ ( + .PRE(plm_rst), + .CE(plm_fsm_cc_counter0_N_69225_i), + .C(mgt_clk), + .D(plm_fsm_cc_counter0_reg_rx_count_s[3]), + .Q(plm_fsm_cc_counter0_reg_rx_count[3]) + ); + FDCE plm_fsm_cc_counter0_reg_rx_count_2_ ( + .CE(plm_fsm_cc_counter0_N_69225_i), + .C(mgt_clk), + .D(plm_fsm_cc_counter0_reg_rx_count_s[2]), + .Q(plm_fsm_cc_counter0_reg_rx_count[2]), + .CLR(plm_rst) + ); + FDCE plm_fsm_cc_counter0_reg_rx_count_1_ ( + .CE(plm_fsm_cc_counter0_N_69225_i), + .C(mgt_clk), + .D(plm_fsm_cc_counter0_reg_rx_count_s[1]), + .Q(plm_fsm_cc_counter0_reg_rx_count[1]), + .CLR(plm_rst) + ); + FDCE plm_fsm_cc_counter0_reg_rx_count_0_ ( + .CE(plm_fsm_cc_counter0_N_69225_i), + .C(mgt_clk), + .D(plm_fsm_cc_counter0_reg_rx_count_s[0]), + .Q(plm_fsm_cc_counter0_reg_rx_count[0]), + .CLR(plm_rst) + ); + FDC plm_fsm_cc_counter0_reg_expired ( + .C(mgt_clk), + .D(plm_fsm_cc_counter0_N_24582_i), + .Q(plm_fsm_cc_cntrout0), + .CLR(plm_rst) + ); + FDCE plm_fsm_cc_counter0_reg_oneshot ( + .CE(plm_fsm_cc_counter0_N_24639_i_i), + .C(mgt_clk), + .D(plm_fsm_N_38123_i_i_907), + .Q(plm_fsm_cc_counter0_reg_oneshot_970), + .CLR(plm_rst) + ); + FDCE plm_fsm_cc_counter0_reg_rx_expired ( + .CE(plm_fsm_cc_counter0_N_69253_i), + .C(mgt_clk), + .D(plm_fsm_N_38123_i_i_907), + .Q(plm_fsm_cc_counter0_reg_rx_expired_250), + .CLR(plm_rst) + ); + FDCE plm_fsm_cc_counter0_reg_tx_expired ( + .CE(plm_fsm_cc_counter0_N_69088_i_971), + .C(mgt_clk), + .D(plm_fsm_cc_counter0_N_38368_i), + .Q(plm_fsm_cc_counter0_reg_tx_expired_972), + .CLR(plm_rst) + ); + defparam plm_fsm_cc_counter0_reg_rx_count_qxu_0_0_.INIT = 4'h7; + LUT2_L plm_fsm_cc_counter0_reg_rx_count_qxu_0_0_ ( + .I0(N_24768_i), + .I1(plm_fsm_cc_counter0_reg_rx_count[0]), + .LO(plm_fsm_cc_counter0_reg_rx_count_qxu[0]) + ); + defparam plm_fsm_cc_counter0_reg_rx_count_qxu_0_1_.INIT = 4'h7; + LUT2_L plm_fsm_cc_counter0_reg_rx_count_qxu_0_1_ ( + .I0(N_24768_i), + .I1(plm_fsm_cc_counter0_reg_rx_count[1]), + .LO(plm_fsm_cc_counter0_reg_rx_count_qxu[1]) + ); + defparam plm_fsm_cc_counter0_reg_rx_count_qxu_0_2_.INIT = 4'h7; + LUT2_L plm_fsm_cc_counter0_reg_rx_count_qxu_0_2_ ( + .I0(N_24768_i), + .I1(plm_fsm_cc_counter0_reg_rx_count[2]), + .LO(plm_fsm_cc_counter0_reg_rx_count_qxu[2]) + ); + defparam plm_fsm_cc_counter0_reg_rx_count_qxu_0_3_.INIT = 8'h1B; + LUT3_L plm_fsm_cc_counter0_reg_rx_count_qxu_0_3_ ( + .I0(N_24768_i), + .I1(plm_fsm_cc_counter0_N_69086_i_973), + .I2(plm_fsm_cc_counter0_reg_rx_count[3]), + .LO(plm_fsm_cc_counter0_reg_rx_count_qxu[3]) + ); + defparam plm_fsm_cc_counter0_reg_rx_count_qxu_0_4_.INIT = 4'h7; + LUT2_L plm_fsm_cc_counter0_reg_rx_count_qxu_0_4_ ( + .I0(N_24768_i), + .I1(plm_fsm_cc_counter0_reg_rx_count[4]), + .LO(plm_fsm_cc_counter0_reg_rx_count_qxu[4]) + ); + defparam plm_fsm_cc_counter0_reg_rx_count_qxu_0_5_.INIT = 4'h7; + LUT2_L plm_fsm_cc_counter0_reg_rx_count_qxu_0_5_ ( + .I0(N_24768_i), + .I1(plm_fsm_cc_counter0_reg_rx_count[5]), + .LO(plm_fsm_cc_counter0_reg_rx_count_qxu[5]) + ); + defparam plm_fsm_cc_counter0_reg_rx_count_qxu_0_6_.INIT = 4'h7; + LUT2_L plm_fsm_cc_counter0_reg_rx_count_qxu_0_6_ ( + .I0(N_24768_i), + .I1(plm_fsm_cc_counter0_reg_rx_count[6]), + .LO(plm_fsm_cc_counter0_reg_rx_count_qxu[6]) + ); + defparam plm_fsm_cc_counter0_reg_rx_count_qxu_0_7_.INIT = 4'h7; + LUT2_L plm_fsm_cc_counter0_reg_rx_count_qxu_0_7_ ( + .I0(N_24768_i), + .I1(plm_fsm_cc_counter0_reg_rx_count[7]), + .LO(plm_fsm_cc_counter0_reg_rx_count_qxu[7]) + ); + defparam plm_fsm_cc_counter0_reg_tx_count_qxu_0_0_.INIT = 4'h7; + LUT2_L plm_fsm_cc_counter0_reg_tx_count_qxu_0_0_ ( + .I0(plm_fsm_cc_counter0_N_24684_i), + .I1(plm_fsm_cc_counter0_reg_tx_count[0]), + .LO(plm_fsm_cc_counter0_reg_tx_count_qxu[0]) + ); + defparam plm_fsm_cc_counter0_reg_tx_count_qxu_0_1_.INIT = 4'h7; + LUT2_L plm_fsm_cc_counter0_reg_tx_count_qxu_0_1_ ( + .I0(plm_fsm_cc_counter0_N_24684_i), + .I1(plm_fsm_cc_counter0_reg_tx_count[1]), + .LO(plm_fsm_cc_counter0_reg_tx_count_qxu[1]) + ); + defparam plm_fsm_cc_counter0_reg_tx_count_qxu_0_2_.INIT = 4'h7; + LUT2_L plm_fsm_cc_counter0_reg_tx_count_qxu_0_2_ ( + .I0(plm_fsm_cc_counter0_N_24684_i), + .I1(plm_fsm_cc_counter0_reg_tx_count[2]), + .LO(plm_fsm_cc_counter0_reg_tx_count_qxu[2]) + ); + defparam plm_fsm_cc_counter0_reg_tx_count_qxu_0_3_.INIT = 4'h7; + LUT2_L plm_fsm_cc_counter0_reg_tx_count_qxu_0_3_ ( + .I0(plm_fsm_cc_counter0_N_24684_i), + .I1(plm_fsm_cc_counter0_reg_tx_count[3]), + .LO(plm_fsm_cc_counter0_reg_tx_count_qxu[3]) + ); + defparam plm_fsm_cc_counter0_reg_tx_count_qxu_0_4_.INIT = 8'h4E; + LUT3_L plm_fsm_cc_counter0_reg_tx_count_qxu_0_4_ ( + .I0(plm_fsm_cc_counter0_N_24684_i), + .I1(plm_fsm_cc_counter0_N_38368_i), + .I2(plm_fsm_cc_counter0_reg_tx_count[4]), + .LO(plm_fsm_cc_counter0_reg_tx_count_qxu[4]) + ); + defparam plm_fsm_cc_counter0_reg_tx_count_qxu_0_5_.INIT = 4'h7; + LUT2_L plm_fsm_cc_counter0_reg_tx_count_qxu_0_5_ ( + .I0(plm_fsm_cc_counter0_N_24684_i), + .I1(plm_fsm_cc_counter0_reg_tx_count[5]), + .LO(plm_fsm_cc_counter0_reg_tx_count_qxu[5]) + ); + defparam plm_fsm_cc_counter0_reg_tx_count_qxu_0_6_.INIT = 4'h7; + LUT2_L plm_fsm_cc_counter0_reg_tx_count_qxu_0_6_ ( + .I0(plm_fsm_cc_counter0_N_24684_i), + .I1(plm_fsm_cc_counter0_reg_tx_count[6]), + .LO(plm_fsm_cc_counter0_reg_tx_count_qxu[6]) + ); + defparam plm_fsm_cc_counter0_reg_tx_count_qxu_0_7_.INIT = 4'h7; + LUT2_L plm_fsm_cc_counter0_reg_tx_count_qxu_0_7_ ( + .I0(plm_fsm_cc_counter0_N_24684_i), + .I1(plm_fsm_cc_counter0_reg_tx_count[7]), + .LO(plm_fsm_cc_counter0_reg_tx_count_qxu[7]) + ); + GND plm_fsm_ci_timer_GND ( + .G(plm_fsm_ci_timer_GND_974) + ); + MUXCY_L plm_fsm_ci_timer_reg_count_cry_0_ ( + .CI(plm_fsm_reg_state_11__360), + .DI(plm_fsm_ci_timer_GND_974), + .LO(plm_fsm_ci_timer_reg_count_cry[0]), + .S(plm_fsm_ci_timer_reg_count_qxu[0]) + ); + XORCY plm_fsm_ci_timer_reg_count_s_0_ ( + .CI(plm_fsm_reg_state_11__360), + .LI(plm_fsm_ci_timer_reg_count_qxu[0]), + .O(plm_fsm_ci_timer_reg_count_s[0]) + ); + MUXCY_L plm_fsm_ci_timer_reg_count_cry_1_ ( + .CI(plm_fsm_ci_timer_reg_count_cry[0]), + .DI(plm_fsm_ci_timer_GND_974), + .LO(plm_fsm_ci_timer_reg_count_cry[1]), + .S(plm_fsm_ci_timer_reg_count_qxu[1]) + ); + XORCY plm_fsm_ci_timer_reg_count_s_1_ ( + .CI(plm_fsm_ci_timer_reg_count_cry[0]), + .LI(plm_fsm_ci_timer_reg_count_qxu[1]), + .O(plm_fsm_ci_timer_reg_count_s[1]) + ); + MUXCY_L plm_fsm_ci_timer_reg_count_cry_2_ ( + .CI(plm_fsm_ci_timer_reg_count_cry[1]), + .DI(plm_fsm_ci_timer_GND_974), + .LO(plm_fsm_ci_timer_reg_count_cry[2]), + .S(plm_fsm_ci_timer_reg_count_qxu[2]) + ); + XORCY plm_fsm_ci_timer_reg_count_s_2_ ( + .CI(plm_fsm_ci_timer_reg_count_cry[1]), + .LI(plm_fsm_ci_timer_reg_count_qxu[2]), + .O(plm_fsm_ci_timer_reg_count_s[2]) + ); + MUXCY_L plm_fsm_ci_timer_reg_count_cry_3_ ( + .CI(plm_fsm_ci_timer_reg_count_cry[2]), + .DI(plm_fsm_ci_timer_GND_974), + .LO(plm_fsm_ci_timer_reg_count_cry[3]), + .S(plm_fsm_ci_timer_reg_count_qxu[3]) + ); + XORCY plm_fsm_ci_timer_reg_count_s_3_ ( + .CI(plm_fsm_ci_timer_reg_count_cry[2]), + .LI(plm_fsm_ci_timer_reg_count_qxu[3]), + .O(plm_fsm_ci_timer_reg_count_s[3]) + ); + MUXCY_L plm_fsm_ci_timer_reg_count_cry_4_ ( + .CI(plm_fsm_ci_timer_reg_count_cry[3]), + .DI(plm_fsm_ci_timer_GND_974), + .LO(plm_fsm_ci_timer_reg_count_cry[4]), + .S(plm_fsm_ci_timer_reg_count_qxu[4]) + ); + XORCY plm_fsm_ci_timer_reg_count_s_4_ ( + .CI(plm_fsm_ci_timer_reg_count_cry[3]), + .LI(plm_fsm_ci_timer_reg_count_qxu[4]), + .O(plm_fsm_ci_timer_reg_count_s[4]) + ); + MUXCY_L plm_fsm_ci_timer_reg_count_cry_5_ ( + .CI(plm_fsm_ci_timer_reg_count_cry[4]), + .DI(plm_fsm_ci_timer_GND_974), + .LO(plm_fsm_ci_timer_reg_count_cry[5]), + .S(plm_fsm_ci_timer_reg_count_qxu[5]) + ); + XORCY plm_fsm_ci_timer_reg_count_s_5_ ( + .CI(plm_fsm_ci_timer_reg_count_cry[4]), + .LI(plm_fsm_ci_timer_reg_count_qxu[5]), + .O(plm_fsm_ci_timer_reg_count_s[5]) + ); + MUXCY_L plm_fsm_ci_timer_reg_count_cry_6_ ( + .CI(plm_fsm_ci_timer_reg_count_cry[5]), + .DI(plm_fsm_ci_timer_GND_974), + .LO(plm_fsm_ci_timer_reg_count_cry[6]), + .S(plm_fsm_ci_timer_reg_count_qxu[6]) + ); + XORCY plm_fsm_ci_timer_reg_count_s_6_ ( + .CI(plm_fsm_ci_timer_reg_count_cry[5]), + .LI(plm_fsm_ci_timer_reg_count_qxu[6]), + .O(plm_fsm_ci_timer_reg_count_s[6]) + ); + MUXCY_L plm_fsm_ci_timer_reg_count_cry_7_ ( + .CI(plm_fsm_ci_timer_reg_count_cry[6]), + .DI(plm_fsm_ci_timer_GND_974), + .LO(plm_fsm_ci_timer_reg_count_cry[7]), + .S(plm_fsm_ci_timer_reg_count_qxu[7]) + ); + XORCY plm_fsm_ci_timer_reg_count_s_7_ ( + .CI(plm_fsm_ci_timer_reg_count_cry[6]), + .LI(plm_fsm_ci_timer_reg_count_qxu[7]), + .O(plm_fsm_ci_timer_reg_count_s[7]) + ); + MUXCY_L plm_fsm_ci_timer_reg_count_cry_8_ ( + .CI(plm_fsm_ci_timer_reg_count_cry[7]), + .DI(plm_fsm_ci_timer_GND_974), + .LO(plm_fsm_ci_timer_reg_count_cry[8]), + .S(plm_fsm_ci_timer_reg_count_qxu[8]) + ); + XORCY plm_fsm_ci_timer_reg_count_s_8_ ( + .CI(plm_fsm_ci_timer_reg_count_cry[7]), + .LI(plm_fsm_ci_timer_reg_count_qxu[8]), + .O(plm_fsm_ci_timer_reg_count_s[8]) + ); + MUXCY_L plm_fsm_ci_timer_reg_count_cry_9_ ( + .CI(plm_fsm_ci_timer_reg_count_cry[8]), + .DI(plm_fsm_ci_timer_GND_974), + .LO(plm_fsm_ci_timer_reg_count_cry[9]), + .S(plm_fsm_ci_timer_reg_count_qxu[9]) + ); + XORCY plm_fsm_ci_timer_reg_count_s_9_ ( + .CI(plm_fsm_ci_timer_reg_count_cry[8]), + .LI(plm_fsm_ci_timer_reg_count_qxu[9]), + .O(plm_fsm_ci_timer_reg_count_s[9]) + ); + MUXCY_L plm_fsm_ci_timer_reg_count_cry_10_ ( + .CI(plm_fsm_ci_timer_reg_count_cry[9]), + .DI(plm_fsm_ci_timer_GND_974), + .LO(plm_fsm_ci_timer_reg_count_cry[10]), + .S(plm_fsm_ci_timer_reg_count_qxu[10]) + ); + XORCY plm_fsm_ci_timer_reg_count_s_10_ ( + .CI(plm_fsm_ci_timer_reg_count_cry[9]), + .LI(plm_fsm_ci_timer_reg_count_qxu[10]), + .O(plm_fsm_ci_timer_reg_count_s[10]) + ); + MUXCY_L plm_fsm_ci_timer_reg_count_cry_11_ ( + .CI(plm_fsm_ci_timer_reg_count_cry[10]), + .DI(plm_fsm_ci_timer_GND_974), + .LO(plm_fsm_ci_timer_reg_count_cry[11]), + .S(plm_fsm_ci_timer_reg_count_qxu[11]) + ); + XORCY plm_fsm_ci_timer_reg_count_s_11_ ( + .CI(plm_fsm_ci_timer_reg_count_cry[10]), + .LI(plm_fsm_ci_timer_reg_count_qxu[11]), + .O(plm_fsm_ci_timer_reg_count_s[11]) + ); + MUXCY_L plm_fsm_ci_timer_reg_count_cry_12_ ( + .CI(plm_fsm_ci_timer_reg_count_cry[11]), + .DI(plm_fsm_ci_timer_GND_974), + .LO(plm_fsm_ci_timer_reg_count_cry[12]), + .S(plm_fsm_ci_timer_reg_count_qxu[12]) + ); + XORCY plm_fsm_ci_timer_reg_count_s_12_ ( + .CI(plm_fsm_ci_timer_reg_count_cry[11]), + .LI(plm_fsm_ci_timer_reg_count_qxu[12]), + .O(plm_fsm_ci_timer_reg_count_s[12]) + ); + MUXCY_L plm_fsm_ci_timer_reg_count_cry_13_ ( + .CI(plm_fsm_ci_timer_reg_count_cry[12]), + .DI(plm_fsm_ci_timer_GND_974), + .LO(plm_fsm_ci_timer_reg_count_cry[13]), + .S(plm_fsm_ci_timer_reg_count_qxu[13]) + ); + XORCY plm_fsm_ci_timer_reg_count_s_13_ ( + .CI(plm_fsm_ci_timer_reg_count_cry[12]), + .LI(plm_fsm_ci_timer_reg_count_qxu[13]), + .O(plm_fsm_ci_timer_reg_count_s[13]) + ); + MUXCY_L plm_fsm_ci_timer_reg_count_cry_14_ ( + .CI(plm_fsm_ci_timer_reg_count_cry[13]), + .DI(plm_fsm_ci_timer_GND_974), + .LO(plm_fsm_ci_timer_reg_count_cry[14]), + .S(plm_fsm_ci_timer_reg_count_qxu[14]) + ); + XORCY plm_fsm_ci_timer_reg_count_s_14_ ( + .CI(plm_fsm_ci_timer_reg_count_cry[13]), + .LI(plm_fsm_ci_timer_reg_count_qxu[14]), + .O(plm_fsm_ci_timer_reg_count_s[14]) + ); + MUXCY_L plm_fsm_ci_timer_reg_count_cry_15_ ( + .CI(plm_fsm_ci_timer_reg_count_cry[14]), + .DI(plm_fsm_ci_timer_GND_974), + .LO(plm_fsm_ci_timer_reg_count_cry[15]), + .S(plm_fsm_ci_timer_reg_count_qxu[15]) + ); + XORCY plm_fsm_ci_timer_reg_count_s_15_ ( + .CI(plm_fsm_ci_timer_reg_count_cry[14]), + .LI(plm_fsm_ci_timer_reg_count_qxu[15]), + .O(plm_fsm_ci_timer_reg_count_s[15]) + ); + MUXCY_L plm_fsm_ci_timer_reg_count_cry_16_ ( + .CI(plm_fsm_ci_timer_reg_count_cry[15]), + .DI(plm_fsm_ci_timer_GND_974), + .LO(plm_fsm_ci_timer_reg_count_cry[16]), + .S(plm_fsm_ci_timer_reg_count_qxu[16]) + ); + XORCY plm_fsm_ci_timer_reg_count_s_16_ ( + .CI(plm_fsm_ci_timer_reg_count_cry[15]), + .LI(plm_fsm_ci_timer_reg_count_qxu[16]), + .O(plm_fsm_ci_timer_reg_count_s[16]) + ); + MUXCY_L plm_fsm_ci_timer_reg_count_cry_17_ ( + .CI(plm_fsm_ci_timer_reg_count_cry[16]), + .DI(plm_fsm_ci_timer_GND_974), + .LO(plm_fsm_ci_timer_reg_count_cry[17]), + .S(plm_fsm_ci_timer_reg_count_qxu[17]) + ); + XORCY plm_fsm_ci_timer_reg_count_s_17_ ( + .CI(plm_fsm_ci_timer_reg_count_cry[16]), + .LI(plm_fsm_ci_timer_reg_count_qxu[17]), + .O(plm_fsm_ci_timer_reg_count_s[17]) + ); + MUXCY_L plm_fsm_ci_timer_reg_count_cry_18_ ( + .CI(plm_fsm_ci_timer_reg_count_cry[17]), + .DI(plm_fsm_ci_timer_GND_974), + .LO(plm_fsm_ci_timer_reg_count_cry[18]), + .S(plm_fsm_ci_timer_reg_count_qxu[18]) + ); + XORCY plm_fsm_ci_timer_reg_count_s_18_ ( + .CI(plm_fsm_ci_timer_reg_count_cry[17]), + .LI(plm_fsm_ci_timer_reg_count_qxu[18]), + .O(plm_fsm_ci_timer_reg_count_s[18]) + ); + MUXCY_L plm_fsm_ci_timer_reg_count_cry_19_ ( + .CI(plm_fsm_ci_timer_reg_count_cry[18]), + .DI(plm_fsm_ci_timer_GND_974), + .LO(plm_fsm_ci_timer_reg_count_cry[19]), + .S(plm_fsm_ci_timer_reg_count_qxu[19]) + ); + XORCY plm_fsm_ci_timer_reg_count_s_19_ ( + .CI(plm_fsm_ci_timer_reg_count_cry[18]), + .LI(plm_fsm_ci_timer_reg_count_qxu[19]), + .O(plm_fsm_ci_timer_reg_count_s[19]) + ); + MUXCY_L plm_fsm_ci_timer_reg_count_cry_20_ ( + .CI(plm_fsm_ci_timer_reg_count_cry[19]), + .DI(plm_fsm_ci_timer_GND_974), + .LO(plm_fsm_ci_timer_reg_count_cry[20]), + .S(plm_fsm_ci_timer_reg_count_qxu[20]) + ); + XORCY plm_fsm_ci_timer_reg_count_s_20_ ( + .CI(plm_fsm_ci_timer_reg_count_cry[19]), + .LI(plm_fsm_ci_timer_reg_count_qxu[20]), + .O(plm_fsm_ci_timer_reg_count_s[20]) + ); + MUXCY_L plm_fsm_ci_timer_reg_count_cry_21_ ( + .CI(plm_fsm_ci_timer_reg_count_cry[20]), + .DI(plm_fsm_ci_timer_GND_974), + .LO(plm_fsm_ci_timer_reg_count_cry[21]), + .S(plm_fsm_ci_timer_reg_count_qxu[21]) + ); + XORCY plm_fsm_ci_timer_reg_count_s_21_ ( + .CI(plm_fsm_ci_timer_reg_count_cry[20]), + .LI(plm_fsm_ci_timer_reg_count_qxu[21]), + .O(plm_fsm_ci_timer_reg_count_s[21]) + ); + XORCY plm_fsm_ci_timer_reg_count_s_22_ ( + .CI(plm_fsm_ci_timer_reg_count_cry[21]), + .LI(plm_fsm_ci_timer_reg_count_qxu[22]), + .O(plm_fsm_ci_timer_reg_count_s[22]) + ); + defparam plm_fsm_ci_timer_count_0_18_.INIT = 8'hD8; + LUT3_L plm_fsm_ci_timer_count_0_18_ ( + .I0(cfg_cfg_5072[507]), + .I1(plm_fsm_ci_timer_reg_count[10]), + .I2(plm_fsm_ci_timer_reg_count[18]), + .LO(plm_fsm_ci_timer_count[18]) + ); + defparam plm_fsm_ci_timer_count_0_20_.INIT = 8'hD8; + LUT3_L plm_fsm_ci_timer_count_0_20_ ( + .I0(cfg_cfg_5072[507]), + .I1(plm_fsm_ci_timer_reg_count[12]), + .I2(plm_fsm_ci_timer_reg_count[20]), + .LO(plm_fsm_ci_timer_count[20]) + ); + defparam plm_fsm_ci_timer_count_0_19_.INIT = 8'hD8; + LUT3 plm_fsm_ci_timer_count_0_19_ ( + .I0(cfg_cfg_5072[507]), + .I1(plm_fsm_ci_timer_reg_count[11]), + .I2(plm_fsm_ci_timer_reg_count[19]), + .O(plm_fsm_ci_timer_count[19]) + ); + defparam plm_fsm_ci_timer_un1_expired_2ms_0.INIT = 16'h0213; + LUT4 plm_fsm_ci_timer_un1_expired_2ms_0 ( + .I0(cfg_cfg_5072[507]), + .I1(plm_fsm_ci_timer_count[18]), + .I2(plm_fsm_ci_timer_reg_count[14]), + .I3(plm_fsm_ci_timer_reg_count[22]), + .O(plm_fsm_ci_timer_un1_expired_2ms_0_976) + ); + defparam plm_fsm_ci_timer_un1_expired_2ms_1.INIT = 16'h0213; + LUT4 plm_fsm_ci_timer_un1_expired_2ms_1 ( + .I0(cfg_cfg_5072[507]), + .I1(plm_fsm_ci_timer_count[20]), + .I2(plm_fsm_ci_timer_reg_count[13]), + .I3(plm_fsm_ci_timer_reg_count[21]), + .O(plm_fsm_ci_timer_un1_expired_2ms_1_975) + ); + defparam plm_fsm_ci_timer_expired.INIT = 16'hBF00; + LUT4 plm_fsm_ci_timer_expired ( + .I0(plm_fsm_ci_timer_count[19]), + .I1(plm_fsm_ci_timer_un1_expired_2ms_0_976), + .I2(plm_fsm_ci_timer_un1_expired_2ms_1_975), + .I3(plm_fsm_reg_state_11__360), + .O(plm_fsm_ci_timeout) + ); + FDC plm_fsm_ci_timer_reg_count_22_ ( + .C(mgt_clk), + .D(plm_fsm_ci_timer_reg_count_s[22]), + .Q(plm_fsm_ci_timer_reg_count[22]), + .CLR(plm_rst) + ); + FDC plm_fsm_ci_timer_reg_count_21_ ( + .C(mgt_clk), + .D(plm_fsm_ci_timer_reg_count_s[21]), + .Q(plm_fsm_ci_timer_reg_count[21]), + .CLR(plm_rst) + ); + FDC plm_fsm_ci_timer_reg_count_20_ ( + .C(mgt_clk), + .D(plm_fsm_ci_timer_reg_count_s[20]), + .Q(plm_fsm_ci_timer_reg_count[20]), + .CLR(plm_rst) + ); + FDC plm_fsm_ci_timer_reg_count_19_ ( + .C(mgt_clk), + .D(plm_fsm_ci_timer_reg_count_s[19]), + .Q(plm_fsm_ci_timer_reg_count[19]), + .CLR(plm_rst) + ); + FDC plm_fsm_ci_timer_reg_count_18_ ( + .C(mgt_clk), + .D(plm_fsm_ci_timer_reg_count_s[18]), + .Q(plm_fsm_ci_timer_reg_count[18]), + .CLR(plm_rst) + ); + FDC plm_fsm_ci_timer_reg_count_17_ ( + .C(mgt_clk), + .D(plm_fsm_ci_timer_reg_count_s[17]), + .Q(plm_fsm_ci_timer_reg_count[17]), + .CLR(plm_rst) + ); + FDC plm_fsm_ci_timer_reg_count_16_ ( + .C(mgt_clk), + .D(plm_fsm_ci_timer_reg_count_s[16]), + .Q(plm_fsm_ci_timer_reg_count[16]), + .CLR(plm_rst) + ); + FDC plm_fsm_ci_timer_reg_count_15_ ( + .C(mgt_clk), + .D(plm_fsm_ci_timer_reg_count_s[15]), + .Q(plm_fsm_ci_timer_reg_count[15]), + .CLR(plm_rst) + ); + FDC plm_fsm_ci_timer_reg_count_14_ ( + .C(mgt_clk), + .D(plm_fsm_ci_timer_reg_count_s[14]), + .Q(plm_fsm_ci_timer_reg_count[14]), + .CLR(plm_rst) + ); + FDC plm_fsm_ci_timer_reg_count_13_ ( + .C(mgt_clk), + .D(plm_fsm_ci_timer_reg_count_s[13]), + .Q(plm_fsm_ci_timer_reg_count[13]), + .CLR(plm_rst) + ); + FDC plm_fsm_ci_timer_reg_count_12_ ( + .C(mgt_clk), + .D(plm_fsm_ci_timer_reg_count_s[12]), + .Q(plm_fsm_ci_timer_reg_count[12]), + .CLR(plm_rst) + ); + FDC plm_fsm_ci_timer_reg_count_11_ ( + .C(mgt_clk), + .D(plm_fsm_ci_timer_reg_count_s[11]), + .Q(plm_fsm_ci_timer_reg_count[11]), + .CLR(plm_rst) + ); + FDC plm_fsm_ci_timer_reg_count_10_ ( + .C(mgt_clk), + .D(plm_fsm_ci_timer_reg_count_s[10]), + .Q(plm_fsm_ci_timer_reg_count[10]), + .CLR(plm_rst) + ); + FDC plm_fsm_ci_timer_reg_count_9_ ( + .C(mgt_clk), + .D(plm_fsm_ci_timer_reg_count_s[9]), + .Q(plm_fsm_ci_timer_reg_count[9]), + .CLR(plm_rst) + ); + FDC plm_fsm_ci_timer_reg_count_8_ ( + .C(mgt_clk), + .D(plm_fsm_ci_timer_reg_count_s[8]), + .Q(plm_fsm_ci_timer_reg_count[8]), + .CLR(plm_rst) + ); + FDC plm_fsm_ci_timer_reg_count_7_ ( + .C(mgt_clk), + .D(plm_fsm_ci_timer_reg_count_s[7]), + .Q(plm_fsm_ci_timer_reg_count[7]), + .CLR(plm_rst) + ); + FDC plm_fsm_ci_timer_reg_count_6_ ( + .C(mgt_clk), + .D(plm_fsm_ci_timer_reg_count_s[6]), + .Q(plm_fsm_ci_timer_reg_count[6]), + .CLR(plm_rst) + ); + FDC plm_fsm_ci_timer_reg_count_5_ ( + .C(mgt_clk), + .D(plm_fsm_ci_timer_reg_count_s[5]), + .Q(plm_fsm_ci_timer_reg_count[5]), + .CLR(plm_rst) + ); + FDC plm_fsm_ci_timer_reg_count_4_ ( + .C(mgt_clk), + .D(plm_fsm_ci_timer_reg_count_s[4]), + .Q(plm_fsm_ci_timer_reg_count[4]), + .CLR(plm_rst) + ); + FDC plm_fsm_ci_timer_reg_count_3_ ( + .C(mgt_clk), + .D(plm_fsm_ci_timer_reg_count_s[3]), + .Q(plm_fsm_ci_timer_reg_count[3]), + .CLR(plm_rst) + ); + FDC plm_fsm_ci_timer_reg_count_2_ ( + .C(mgt_clk), + .D(plm_fsm_ci_timer_reg_count_s[2]), + .Q(plm_fsm_ci_timer_reg_count[2]), + .CLR(plm_rst) + ); + FDC plm_fsm_ci_timer_reg_count_1_ ( + .C(mgt_clk), + .D(plm_fsm_ci_timer_reg_count_s[1]), + .Q(plm_fsm_ci_timer_reg_count[1]), + .CLR(plm_rst) + ); + FDC plm_fsm_ci_timer_reg_count_0_ ( + .C(mgt_clk), + .D(plm_fsm_ci_timer_reg_count_s[0]), + .Q(plm_fsm_ci_timer_reg_count[0]), + .CLR(plm_rst) + ); + defparam plm_fsm_ci_timer_reg_count_qxu_0_0_.INIT = 4'h8; + LUT2_L plm_fsm_ci_timer_reg_count_qxu_0_0_ ( + .I0(plm_fsm_ci_timer_reg_count[0]), + .I1(plm_fsm_reg_state_11__360), + .LO(plm_fsm_ci_timer_reg_count_qxu[0]) + ); + defparam plm_fsm_ci_timer_reg_count_qxu_0_1_.INIT = 4'h8; + LUT2_L plm_fsm_ci_timer_reg_count_qxu_0_1_ ( + .I0(plm_fsm_ci_timer_reg_count[1]), + .I1(plm_fsm_reg_state_11__360), + .LO(plm_fsm_ci_timer_reg_count_qxu[1]) + ); + defparam plm_fsm_ci_timer_reg_count_qxu_0_2_.INIT = 4'h8; + LUT2_L plm_fsm_ci_timer_reg_count_qxu_0_2_ ( + .I0(plm_fsm_ci_timer_reg_count[2]), + .I1(plm_fsm_reg_state_11__360), + .LO(plm_fsm_ci_timer_reg_count_qxu[2]) + ); + defparam plm_fsm_ci_timer_reg_count_qxu_0_3_.INIT = 4'h8; + LUT2_L plm_fsm_ci_timer_reg_count_qxu_0_3_ ( + .I0(plm_fsm_ci_timer_reg_count[3]), + .I1(plm_fsm_reg_state_11__360), + .LO(plm_fsm_ci_timer_reg_count_qxu[3]) + ); + defparam plm_fsm_ci_timer_reg_count_qxu_0_4_.INIT = 4'h8; + LUT2_L plm_fsm_ci_timer_reg_count_qxu_0_4_ ( + .I0(plm_fsm_ci_timer_reg_count[4]), + .I1(plm_fsm_reg_state_11__360), + .LO(plm_fsm_ci_timer_reg_count_qxu[4]) + ); + defparam plm_fsm_ci_timer_reg_count_qxu_0_5_.INIT = 4'h8; + LUT2_L plm_fsm_ci_timer_reg_count_qxu_0_5_ ( + .I0(plm_fsm_ci_timer_reg_count[5]), + .I1(plm_fsm_reg_state_11__360), + .LO(plm_fsm_ci_timer_reg_count_qxu[5]) + ); + defparam plm_fsm_ci_timer_reg_count_qxu_0_6_.INIT = 4'h8; + LUT2_L plm_fsm_ci_timer_reg_count_qxu_0_6_ ( + .I0(plm_fsm_ci_timer_reg_count[6]), + .I1(plm_fsm_reg_state_11__360), + .LO(plm_fsm_ci_timer_reg_count_qxu[6]) + ); + defparam plm_fsm_ci_timer_reg_count_qxu_0_7_.INIT = 4'h8; + LUT2_L plm_fsm_ci_timer_reg_count_qxu_0_7_ ( + .I0(plm_fsm_ci_timer_reg_count[7]), + .I1(plm_fsm_reg_state_11__360), + .LO(plm_fsm_ci_timer_reg_count_qxu[7]) + ); + defparam plm_fsm_ci_timer_reg_count_qxu_0_8_.INIT = 4'h8; + LUT2_L plm_fsm_ci_timer_reg_count_qxu_0_8_ ( + .I0(plm_fsm_ci_timer_reg_count[8]), + .I1(plm_fsm_reg_state_11__360), + .LO(plm_fsm_ci_timer_reg_count_qxu[8]) + ); + defparam plm_fsm_ci_timer_reg_count_qxu_0_9_.INIT = 4'h8; + LUT2_L plm_fsm_ci_timer_reg_count_qxu_0_9_ ( + .I0(plm_fsm_ci_timer_reg_count[9]), + .I1(plm_fsm_reg_state_11__360), + .LO(plm_fsm_ci_timer_reg_count_qxu[9]) + ); + defparam plm_fsm_ci_timer_reg_count_qxu_0_10_.INIT = 4'h8; + LUT2_L plm_fsm_ci_timer_reg_count_qxu_0_10_ ( + .I0(plm_fsm_ci_timer_reg_count[10]), + .I1(plm_fsm_reg_state_11__360), + .LO(plm_fsm_ci_timer_reg_count_qxu[10]) + ); + defparam plm_fsm_ci_timer_reg_count_qxu_0_11_.INIT = 4'h8; + LUT2_L plm_fsm_ci_timer_reg_count_qxu_0_11_ ( + .I0(plm_fsm_ci_timer_reg_count[11]), + .I1(plm_fsm_reg_state_11__360), + .LO(plm_fsm_ci_timer_reg_count_qxu[11]) + ); + defparam plm_fsm_ci_timer_reg_count_qxu_0_12_.INIT = 4'h8; + LUT2_L plm_fsm_ci_timer_reg_count_qxu_0_12_ ( + .I0(plm_fsm_ci_timer_reg_count[12]), + .I1(plm_fsm_reg_state_11__360), + .LO(plm_fsm_ci_timer_reg_count_qxu[12]) + ); + defparam plm_fsm_ci_timer_reg_count_qxu_0_13_.INIT = 4'h8; + LUT2_L plm_fsm_ci_timer_reg_count_qxu_0_13_ ( + .I0(plm_fsm_ci_timer_reg_count[13]), + .I1(plm_fsm_reg_state_11__360), + .LO(plm_fsm_ci_timer_reg_count_qxu[13]) + ); + defparam plm_fsm_ci_timer_reg_count_qxu_0_14_.INIT = 4'h8; + LUT2_L plm_fsm_ci_timer_reg_count_qxu_0_14_ ( + .I0(plm_fsm_ci_timer_reg_count[14]), + .I1(plm_fsm_reg_state_11__360), + .LO(plm_fsm_ci_timer_reg_count_qxu[14]) + ); + defparam plm_fsm_ci_timer_reg_count_qxu_0_15_.INIT = 4'h8; + LUT2_L plm_fsm_ci_timer_reg_count_qxu_0_15_ ( + .I0(plm_fsm_ci_timer_reg_count[15]), + .I1(plm_fsm_reg_state_11__360), + .LO(plm_fsm_ci_timer_reg_count_qxu[15]) + ); + defparam plm_fsm_ci_timer_reg_count_qxu_0_16_.INIT = 4'h8; + LUT2_L plm_fsm_ci_timer_reg_count_qxu_0_16_ ( + .I0(plm_fsm_ci_timer_reg_count[16]), + .I1(plm_fsm_reg_state_11__360), + .LO(plm_fsm_ci_timer_reg_count_qxu[16]) + ); + defparam plm_fsm_ci_timer_reg_count_qxu_0_17_.INIT = 4'h8; + LUT2_L plm_fsm_ci_timer_reg_count_qxu_0_17_ ( + .I0(plm_fsm_ci_timer_reg_count[17]), + .I1(plm_fsm_reg_state_11__360), + .LO(plm_fsm_ci_timer_reg_count_qxu[17]) + ); + defparam plm_fsm_ci_timer_reg_count_qxu_0_18_.INIT = 4'h8; + LUT2_L plm_fsm_ci_timer_reg_count_qxu_0_18_ ( + .I0(plm_fsm_ci_timer_reg_count[18]), + .I1(plm_fsm_reg_state_11__360), + .LO(plm_fsm_ci_timer_reg_count_qxu[18]) + ); + defparam plm_fsm_ci_timer_reg_count_qxu_0_19_.INIT = 4'h8; + LUT2_L plm_fsm_ci_timer_reg_count_qxu_0_19_ ( + .I0(plm_fsm_ci_timer_reg_count[19]), + .I1(plm_fsm_reg_state_11__360), + .LO(plm_fsm_ci_timer_reg_count_qxu[19]) + ); + defparam plm_fsm_ci_timer_reg_count_qxu_0_20_.INIT = 4'h8; + LUT2_L plm_fsm_ci_timer_reg_count_qxu_0_20_ ( + .I0(plm_fsm_ci_timer_reg_count[20]), + .I1(plm_fsm_reg_state_11__360), + .LO(plm_fsm_ci_timer_reg_count_qxu[20]) + ); + defparam plm_fsm_ci_timer_reg_count_qxu_0_21_.INIT = 4'h8; + LUT2_L plm_fsm_ci_timer_reg_count_qxu_0_21_ ( + .I0(plm_fsm_ci_timer_reg_count[21]), + .I1(plm_fsm_reg_state_11__360), + .LO(plm_fsm_ci_timer_reg_count_qxu[21]) + ); + defparam plm_fsm_ci_timer_reg_count_qxu_0_22_.INIT = 4'h8; + LUT2_L plm_fsm_ci_timer_reg_count_qxu_0_22_ ( + .I0(plm_fsm_ci_timer_reg_count[22]), + .I1(plm_fsm_reg_state_11__360), + .LO(plm_fsm_ci_timer_reg_count_qxu[22]) + ); + VCC plm_fsm_ci_counter0_VCC ( + .P(plm_fsm_ci_counter0_VCC_977) + ); + MUXCY_L plm_fsm_ci_counter0_reg_rx_count_cry_0_ ( + .CI(N_38691_i_26), + .DI(plm_fsm_ci_counter0_VCC_977), + .LO(plm_fsm_ci_counter0_reg_rx_count_cry[0]), + .S(plm_fsm_ci_counter0_reg_rx_count_qxu[0]) + ); + XORCY plm_fsm_ci_counter0_reg_rx_count_s_0_ ( + .CI(N_38691_i_26), + .LI(plm_fsm_ci_counter0_reg_rx_count_qxu[0]), + .O(plm_fsm_ci_counter0_reg_rx_count_s[0]) + ); + MUXCY_L plm_fsm_ci_counter0_reg_rx_count_cry_1_ ( + .CI(plm_fsm_ci_counter0_reg_rx_count_cry[0]), + .DI(plm_fsm_ci_counter0_VCC_977), + .LO(plm_fsm_ci_counter0_reg_rx_count_cry[1]), + .S(plm_fsm_ci_counter0_reg_rx_count_qxu[1]) + ); + XORCY plm_fsm_ci_counter0_reg_rx_count_s_1_ ( + .CI(plm_fsm_ci_counter0_reg_rx_count_cry[0]), + .LI(plm_fsm_ci_counter0_reg_rx_count_qxu[1]), + .O(plm_fsm_ci_counter0_reg_rx_count_s[1]) + ); + MUXCY_L plm_fsm_ci_counter0_reg_rx_count_cry_2_ ( + .CI(plm_fsm_ci_counter0_reg_rx_count_cry[1]), + .DI(plm_fsm_ci_counter0_VCC_977), + .LO(plm_fsm_ci_counter0_reg_rx_count_cry[2]), + .S(plm_fsm_ci_counter0_reg_rx_count_qxu[2]) + ); + XORCY plm_fsm_ci_counter0_reg_rx_count_s_2_ ( + .CI(plm_fsm_ci_counter0_reg_rx_count_cry[1]), + .LI(plm_fsm_ci_counter0_reg_rx_count_qxu[2]), + .O(plm_fsm_ci_counter0_reg_rx_count_s[2]) + ); + MUXCY_L plm_fsm_ci_counter0_reg_rx_count_cry_3_ ( + .CI(plm_fsm_ci_counter0_reg_rx_count_cry[2]), + .DI(plm_fsm_ci_counter0_VCC_977), + .LO(plm_fsm_ci_counter0_reg_rx_count_cry[3]), + .S(plm_fsm_ci_counter0_reg_rx_count_qxu[3]) + ); + XORCY plm_fsm_ci_counter0_reg_rx_count_s_3_ ( + .CI(plm_fsm_ci_counter0_reg_rx_count_cry[2]), + .LI(plm_fsm_ci_counter0_reg_rx_count_qxu[3]), + .O(plm_fsm_ci_counter0_reg_rx_count_s[3]) + ); + MUXCY_L plm_fsm_ci_counter0_reg_rx_count_cry_4_ ( + .CI(plm_fsm_ci_counter0_reg_rx_count_cry[3]), + .DI(plm_fsm_ci_counter0_VCC_977), + .LO(plm_fsm_ci_counter0_reg_rx_count_cry[4]), + .S(plm_fsm_ci_counter0_reg_rx_count_qxu[4]) + ); + XORCY plm_fsm_ci_counter0_reg_rx_count_s_4_ ( + .CI(plm_fsm_ci_counter0_reg_rx_count_cry[3]), + .LI(plm_fsm_ci_counter0_reg_rx_count_qxu[4]), + .O(plm_fsm_ci_counter0_reg_rx_count_s[4]) + ); + MUXCY_L plm_fsm_ci_counter0_reg_rx_count_cry_5_ ( + .CI(plm_fsm_ci_counter0_reg_rx_count_cry[4]), + .DI(plm_fsm_ci_counter0_VCC_977), + .LO(plm_fsm_ci_counter0_reg_rx_count_cry[5]), + .S(plm_fsm_ci_counter0_reg_rx_count_qxu[5]) + ); + XORCY plm_fsm_ci_counter0_reg_rx_count_s_5_ ( + .CI(plm_fsm_ci_counter0_reg_rx_count_cry[4]), + .LI(plm_fsm_ci_counter0_reg_rx_count_qxu[5]), + .O(plm_fsm_ci_counter0_reg_rx_count_s[5]) + ); + MUXCY_L plm_fsm_ci_counter0_reg_rx_count_cry_6_ ( + .CI(plm_fsm_ci_counter0_reg_rx_count_cry[5]), + .DI(plm_fsm_ci_counter0_VCC_977), + .LO(plm_fsm_ci_counter0_reg_rx_count_cry[6]), + .S(plm_fsm_ci_counter0_reg_rx_count_qxu[6]) + ); + XORCY plm_fsm_ci_counter0_reg_rx_count_s_6_ ( + .CI(plm_fsm_ci_counter0_reg_rx_count_cry[5]), + .LI(plm_fsm_ci_counter0_reg_rx_count_qxu[6]), + .O(plm_fsm_ci_counter0_reg_rx_count_s[6]) + ); + XORCY plm_fsm_ci_counter0_reg_rx_count_s_7_ ( + .CI(plm_fsm_ci_counter0_reg_rx_count_cry[6]), + .LI(plm_fsm_ci_counter0_reg_rx_count_qxu[7]), + .O(plm_fsm_ci_counter0_reg_rx_count_s[7]) + ); + MUXCY_L plm_fsm_ci_counter0_reg_tx_count_cry_0_ ( + .CI(plm_fsm_ci_counter0_N_38659_i_982), + .DI(plm_fsm_ci_counter0_VCC_977), + .LO(plm_fsm_ci_counter0_reg_tx_count_cry[0]), + .S(plm_fsm_ci_counter0_reg_tx_count_qxu[0]) + ); + XORCY plm_fsm_ci_counter0_reg_tx_count_s_0_ ( + .CI(plm_fsm_ci_counter0_N_38659_i_982), + .LI(plm_fsm_ci_counter0_reg_tx_count_qxu[0]), + .O(plm_fsm_ci_counter0_reg_tx_count_s[0]) + ); + MUXCY_L plm_fsm_ci_counter0_reg_tx_count_cry_1_ ( + .CI(plm_fsm_ci_counter0_reg_tx_count_cry[0]), + .DI(plm_fsm_ci_counter0_VCC_977), + .LO(plm_fsm_ci_counter0_reg_tx_count_cry[1]), + .S(plm_fsm_ci_counter0_reg_tx_count_qxu[1]) + ); + XORCY plm_fsm_ci_counter0_reg_tx_count_s_1_ ( + .CI(plm_fsm_ci_counter0_reg_tx_count_cry[0]), + .LI(plm_fsm_ci_counter0_reg_tx_count_qxu[1]), + .O(plm_fsm_ci_counter0_reg_tx_count_s[1]) + ); + MUXCY_L plm_fsm_ci_counter0_reg_tx_count_cry_2_ ( + .CI(plm_fsm_ci_counter0_reg_tx_count_cry[1]), + .DI(plm_fsm_ci_counter0_VCC_977), + .LO(plm_fsm_ci_counter0_reg_tx_count_cry[2]), + .S(plm_fsm_ci_counter0_reg_tx_count_qxu[2]) + ); + XORCY plm_fsm_ci_counter0_reg_tx_count_s_2_ ( + .CI(plm_fsm_ci_counter0_reg_tx_count_cry[1]), + .LI(plm_fsm_ci_counter0_reg_tx_count_qxu[2]), + .O(plm_fsm_ci_counter0_reg_tx_count_s[2]) + ); + MUXCY_L plm_fsm_ci_counter0_reg_tx_count_cry_3_ ( + .CI(plm_fsm_ci_counter0_reg_tx_count_cry[2]), + .DI(plm_fsm_ci_counter0_VCC_977), + .LO(plm_fsm_ci_counter0_reg_tx_count_cry[3]), + .S(plm_fsm_ci_counter0_reg_tx_count_qxu[3]) + ); + XORCY plm_fsm_ci_counter0_reg_tx_count_s_3_ ( + .CI(plm_fsm_ci_counter0_reg_tx_count_cry[2]), + .LI(plm_fsm_ci_counter0_reg_tx_count_qxu[3]), + .O(plm_fsm_ci_counter0_reg_tx_count_s[3]) + ); + MUXCY_L plm_fsm_ci_counter0_reg_tx_count_cry_4_ ( + .CI(plm_fsm_ci_counter0_reg_tx_count_cry[3]), + .DI(plm_fsm_ci_counter0_VCC_977), + .LO(plm_fsm_ci_counter0_reg_tx_count_cry[4]), + .S(plm_fsm_ci_counter0_reg_tx_count_qxu[4]) + ); + XORCY plm_fsm_ci_counter0_reg_tx_count_s_4_ ( + .CI(plm_fsm_ci_counter0_reg_tx_count_cry[3]), + .LI(plm_fsm_ci_counter0_reg_tx_count_qxu[4]), + .O(plm_fsm_ci_counter0_reg_tx_count_s[4]) + ); + MUXCY_L plm_fsm_ci_counter0_reg_tx_count_cry_5_ ( + .CI(plm_fsm_ci_counter0_reg_tx_count_cry[4]), + .DI(plm_fsm_ci_counter0_VCC_977), + .LO(plm_fsm_ci_counter0_reg_tx_count_cry[5]), + .S(plm_fsm_ci_counter0_reg_tx_count_qxu[5]) + ); + XORCY plm_fsm_ci_counter0_reg_tx_count_s_5_ ( + .CI(plm_fsm_ci_counter0_reg_tx_count_cry[4]), + .LI(plm_fsm_ci_counter0_reg_tx_count_qxu[5]), + .O(plm_fsm_ci_counter0_reg_tx_count_s[5]) + ); + MUXCY_L plm_fsm_ci_counter0_reg_tx_count_cry_6_ ( + .CI(plm_fsm_ci_counter0_reg_tx_count_cry[5]), + .DI(plm_fsm_ci_counter0_VCC_977), + .LO(plm_fsm_ci_counter0_reg_tx_count_cry[6]), + .S(plm_fsm_ci_counter0_reg_tx_count_qxu[6]) + ); + XORCY plm_fsm_ci_counter0_reg_tx_count_s_6_ ( + .CI(plm_fsm_ci_counter0_reg_tx_count_cry[5]), + .LI(plm_fsm_ci_counter0_reg_tx_count_qxu[6]), + .O(plm_fsm_ci_counter0_reg_tx_count_s[6]) + ); + XORCY plm_fsm_ci_counter0_reg_tx_count_s_7_ ( + .CI(plm_fsm_ci_counter0_reg_tx_count_cry[6]), + .LI(plm_fsm_ci_counter0_reg_tx_count_qxu[7]), + .O(plm_fsm_ci_counter0_reg_tx_count_s[7]) + ); + defparam plm_fsm_ci_counter0_loadable_tx_counter_reg_tx_count17_0_a2_0_a2_0_a2_0_a4.INIT = 4'h8; + LUT2 plm_fsm_ci_counter0_loadable_tx_counter_reg_tx_count17_0_a2_0_a2_0_a2_0_a4 ( + .I0(plm_fsm_ci_counter0_reg_oneshot_979), + .I1(plm_fsm_reg_state_11__360), + .O(plm_fsm_ci_counter0_reg_tx_count17_0_a2_0_a2_0_a2_0_a4) + ); + defparam plm_fsm_ci_counter0_oneshot_monitor_N_38699_i.INIT = 4'hB; + LUT2 plm_fsm_ci_counter0_oneshot_monitor_N_38699_i ( + .I0(plm_reg_rx_idl_1), + .I1(plm_fsm_reg_state_11__360), + .O(plm_fsm_ci_counter0_N_38699_i) + ); + defparam plm_fsm_ci_counter0_loadable_tx_counter_un1_reg_tx_count_0_a2_4.INIT = 16'h0001; + LUT4 plm_fsm_ci_counter0_loadable_tx_counter_un1_reg_tx_count_0_a2_4 ( + .I0(plm_fsm_ci_counter0_reg_tx_count[0]), + .I1(plm_fsm_ci_counter0_reg_tx_count[1]), + .I2(plm_fsm_ci_counter0_reg_tx_count[2]), + .I3(plm_fsm_ci_counter0_reg_tx_count[3]), + .O(plm_fsm_ci_counter0_un1_reg_tx_count_0_a2_4) + ); + defparam plm_fsm_ci_counter0_loadable_tx_counter_un1_reg_tx_count_0_a2_5.INIT = 16'h0001; + LUT4 plm_fsm_ci_counter0_loadable_tx_counter_un1_reg_tx_count_0_a2_5 ( + .I0(plm_fsm_ci_counter0_reg_tx_count[4]), + .I1(plm_fsm_ci_counter0_reg_tx_count[5]), + .I2(plm_fsm_ci_counter0_reg_tx_count[6]), + .I3(plm_fsm_ci_counter0_reg_tx_count[7]), + .O(plm_fsm_ci_counter0_un1_reg_tx_count_0_a2_5) + ); + defparam plm_fsm_ci_counter0_loadable_rx_counter_un1_reg_rx_count_4.INIT = 16'h0001; + LUT4 plm_fsm_ci_counter0_loadable_rx_counter_un1_reg_rx_count_4 ( + .I0(plm_fsm_ci_counter0_reg_rx_count[0]), + .I1(plm_fsm_ci_counter0_reg_rx_count[1]), + .I2(plm_fsm_ci_counter0_reg_rx_count[2]), + .I3(plm_fsm_ci_counter0_reg_rx_count[3]), + .O(plm_fsm_ci_counter0_un1_reg_rx_count_4) + ); + defparam plm_fsm_ci_counter0_loadable_rx_counter_un1_reg_rx_count_5.INIT = 16'h0001; + LUT4 plm_fsm_ci_counter0_loadable_rx_counter_un1_reg_rx_count_5 ( + .I0(plm_fsm_ci_counter0_reg_rx_count[4]), + .I1(plm_fsm_ci_counter0_reg_rx_count[5]), + .I2(plm_fsm_ci_counter0_reg_rx_count[6]), + .I3(plm_fsm_ci_counter0_reg_rx_count[7]), + .O(plm_fsm_ci_counter0_un1_reg_rx_count_5) + ); + defparam plm_fsm_ci_counter0_loadable_rx_counter_N_38698_i.INIT = 8'hEF; + LUT3 plm_fsm_ci_counter0_loadable_rx_counter_N_38698_i ( + .I0(plm_reg_rx_idl_1), + .I1(plm_fsm_ci_counter0_reg_rx_expired_359), + .I2(plm_fsm_reg_state_11__360), + .O(plm_fsm_ci_counter0_N_38698_i) + ); + defparam plm_fsm_ci_counter0_N_69074_i.INIT = 8'h2F; + LUT3_L plm_fsm_ci_counter0_N_69074_i ( + .I0(plm_fsm_N_38476_1), + .I1(plm_fsm_ci_counter0_reg_rx_expired_359), + .I2(plm_fsm_reg_state_11__360), + .LO(plm_fsm_ci_counter0_N_69074_i_983) + ); + defparam plm_fsm_ci_counter0_N_38660_i.INIT = 4'hB; + LUT2 plm_fsm_ci_counter0_N_38660_i ( + .I0(plm_reg_sym_sent_0_), + .I1(plm_fsm_ci_counter0_un1_enable_1_0_a2_0_a2_0_a4_984), + .O(plm_fsm_ci_counter0_N_38660_i_978) + ); + defparam plm_fsm_ci_counter0_N_38719_i.INIT = 8'hD5; + LUT3 plm_fsm_ci_counter0_N_38719_i ( + .I0(plm_fsm_ci_counter0_reg_tx_count17_0_a2_0_a2_0_a2_0_a4), + .I1(plm_fsm_ci_counter0_un1_reg_tx_count_0_a2_4), + .I2(plm_fsm_ci_counter0_un1_reg_tx_count_0_a2_5), + .O(plm_fsm_ci_counter0_N_38719_i_980) + ); + defparam plm_fsm_ci_counter0_loadable_rx_counter_N_9912_i.INIT = 8'h8F; + LUT3 plm_fsm_ci_counter0_loadable_rx_counter_N_9912_i ( + .I0(plm_fsm_ci_counter0_un1_reg_rx_count_4), + .I1(plm_fsm_ci_counter0_un1_reg_rx_count_5), + .I2(plm_fsm_reg_state_11__360), + .O(plm_fsm_ci_counter0_N_9912_i) + ); + defparam plm_fsm_ci_counter0_flagit_reg_expired_5_0_a2_0_a2_0_a4.INIT = 8'h80; + LUT3_L plm_fsm_ci_counter0_flagit_reg_expired_5_0_a2_0_a2_0_a4 ( + .I0(plm_fsm_ci_counter0_reg_rx_expired_359), + .I1(plm_fsm_ci_counter0_reg_tx_expired_981), + .I2(plm_fsm_reg_state_11__360), + .LO(plm_fsm_ci_counter0_reg_expired_5) + ); + defparam plm_fsm_ci_counter0_un1_enable_1_0_a2_0_a2_0_a4.INIT = 8'h40; + LUT3 plm_fsm_ci_counter0_un1_enable_1_0_a2_0_a2_0_a4 ( + .I0(plm_fsm_ci_counter0_reg_tx_expired_981), + .I1(plm_fsm_reg_state_11__360), + .I2(plm_fsm_ci_counter0_reg_oneshot_979), + .O(plm_fsm_ci_counter0_un1_enable_1_0_a2_0_a2_0_a4_984) + ); + FDCE plm_fsm_ci_counter0_reg_tx_count_7_ ( + .CE(plm_fsm_ci_counter0_N_38660_i_978), + .C(mgt_clk), + .D(plm_fsm_ci_counter0_reg_tx_count_s[7]), + .Q(plm_fsm_ci_counter0_reg_tx_count[7]), + .CLR(plm_rst) + ); + FDCE plm_fsm_ci_counter0_reg_tx_count_6_ ( + .CE(plm_fsm_ci_counter0_N_38660_i_978), + .C(mgt_clk), + .D(plm_fsm_ci_counter0_reg_tx_count_s[6]), + .Q(plm_fsm_ci_counter0_reg_tx_count[6]), + .CLR(plm_rst) + ); + FDCE plm_fsm_ci_counter0_reg_tx_count_5_ ( + .CE(plm_fsm_ci_counter0_N_38660_i_978), + .C(mgt_clk), + .D(plm_fsm_ci_counter0_reg_tx_count_s[5]), + .Q(plm_fsm_ci_counter0_reg_tx_count[5]), + .CLR(plm_rst) + ); + FDCE plm_fsm_ci_counter0_reg_tx_count_4_ ( + .CE(plm_fsm_ci_counter0_N_38660_i_978), + .C(mgt_clk), + .D(plm_fsm_ci_counter0_reg_tx_count_s[4]), + .Q(plm_fsm_ci_counter0_reg_tx_count[4]), + .CLR(plm_rst) + ); + FDPE plm_fsm_ci_counter0_reg_tx_count_3_ ( + .PRE(plm_rst), + .CE(plm_fsm_ci_counter0_N_38660_i_978), + .C(mgt_clk), + .D(plm_fsm_ci_counter0_reg_tx_count_s[3]), + .Q(plm_fsm_ci_counter0_reg_tx_count[3]) + ); + FDCE plm_fsm_ci_counter0_reg_tx_count_2_ ( + .CE(plm_fsm_ci_counter0_N_38660_i_978), + .C(mgt_clk), + .D(plm_fsm_ci_counter0_reg_tx_count_s[2]), + .Q(plm_fsm_ci_counter0_reg_tx_count[2]), + .CLR(plm_rst) + ); + FDCE plm_fsm_ci_counter0_reg_tx_count_1_ ( + .CE(plm_fsm_ci_counter0_N_38660_i_978), + .C(mgt_clk), + .D(plm_fsm_ci_counter0_reg_tx_count_s[1]), + .Q(plm_fsm_ci_counter0_reg_tx_count[1]), + .CLR(plm_rst) + ); + FDCE plm_fsm_ci_counter0_reg_tx_count_0_ ( + .CE(plm_fsm_ci_counter0_N_38660_i_978), + .C(mgt_clk), + .D(plm_fsm_ci_counter0_reg_tx_count_s[0]), + .Q(plm_fsm_ci_counter0_reg_tx_count[0]), + .CLR(plm_rst) + ); + FDCE plm_fsm_ci_counter0_reg_rx_count_7_ ( + .CE(plm_fsm_ci_counter0_N_38698_i), + .C(mgt_clk), + .D(plm_fsm_ci_counter0_reg_rx_count_s[7]), + .Q(plm_fsm_ci_counter0_reg_rx_count[7]), + .CLR(plm_rst) + ); + FDCE plm_fsm_ci_counter0_reg_rx_count_6_ ( + .CE(plm_fsm_ci_counter0_N_38698_i), + .C(mgt_clk), + .D(plm_fsm_ci_counter0_reg_rx_count_s[6]), + .Q(plm_fsm_ci_counter0_reg_rx_count[6]), + .CLR(plm_rst) + ); + FDCE plm_fsm_ci_counter0_reg_rx_count_5_ ( + .CE(plm_fsm_ci_counter0_N_38698_i), + .C(mgt_clk), + .D(plm_fsm_ci_counter0_reg_rx_count_s[5]), + .Q(plm_fsm_ci_counter0_reg_rx_count[5]), + .CLR(plm_rst) + ); + FDCE plm_fsm_ci_counter0_reg_rx_count_4_ ( + .CE(plm_fsm_ci_counter0_N_38698_i), + .C(mgt_clk), + .D(plm_fsm_ci_counter0_reg_rx_count_s[4]), + .Q(plm_fsm_ci_counter0_reg_rx_count[4]), + .CLR(plm_rst) + ); + FDCE plm_fsm_ci_counter0_reg_rx_count_3_ ( + .CE(plm_fsm_ci_counter0_N_38698_i), + .C(mgt_clk), + .D(plm_fsm_ci_counter0_reg_rx_count_s[3]), + .Q(plm_fsm_ci_counter0_reg_rx_count[3]), + .CLR(plm_rst) + ); + FDPE plm_fsm_ci_counter0_reg_rx_count_2_ ( + .PRE(plm_rst), + .CE(plm_fsm_ci_counter0_N_38698_i), + .C(mgt_clk), + .D(plm_fsm_ci_counter0_reg_rx_count_s[2]), + .Q(plm_fsm_ci_counter0_reg_rx_count[2]) + ); + FDCE plm_fsm_ci_counter0_reg_rx_count_1_ ( + .CE(plm_fsm_ci_counter0_N_38698_i), + .C(mgt_clk), + .D(plm_fsm_ci_counter0_reg_rx_count_s[1]), + .Q(plm_fsm_ci_counter0_reg_rx_count[1]), + .CLR(plm_rst) + ); + FDCE plm_fsm_ci_counter0_reg_rx_count_0_ ( + .CE(plm_fsm_ci_counter0_N_38698_i), + .C(mgt_clk), + .D(plm_fsm_ci_counter0_reg_rx_count_s[0]), + .Q(plm_fsm_ci_counter0_reg_rx_count[0]), + .CLR(plm_rst) + ); + FDC plm_fsm_ci_counter0_reg_expired ( + .C(mgt_clk), + .D(plm_fsm_ci_counter0_reg_expired_5), + .Q(plm_fsm_ci_cntrout0), + .CLR(plm_rst) + ); + FDCE plm_fsm_ci_counter0_reg_oneshot ( + .CE(plm_fsm_ci_counter0_N_38699_i), + .C(mgt_clk), + .D(plm_fsm_reg_state_11__360), + .Q(plm_fsm_ci_counter0_reg_oneshot_979), + .CLR(plm_rst) + ); + FDCE plm_fsm_ci_counter0_reg_rx_expired ( + .CE(plm_fsm_ci_counter0_N_9912_i), + .C(mgt_clk), + .D(plm_fsm_reg_state_11__360), + .Q(plm_fsm_ci_counter0_reg_rx_expired_359), + .CLR(plm_rst) + ); + FDCE plm_fsm_ci_counter0_reg_tx_expired ( + .CE(plm_fsm_ci_counter0_N_38719_i_980), + .C(mgt_clk), + .D(plm_fsm_ci_counter0_reg_tx_count17_0_a2_0_a2_0_a2_0_a4), + .Q(plm_fsm_ci_counter0_reg_tx_expired_981), + .CLR(plm_rst) + ); + INV plm_fsm_ci_counter0_N_38659_i ( + .I(plm_fsm_ci_counter0_un1_enable_1_0_a2_0_a2_0_a4_984), + .O(plm_fsm_ci_counter0_N_38659_i_982) + ); + defparam plm_fsm_ci_counter0_reg_rx_count_qxu_0_0_.INIT = 4'h7; + LUT2_L plm_fsm_ci_counter0_reg_rx_count_qxu_0_0_ ( + .I0(I_5072_0_a2_0_a2_0_a4_25), + .I1(plm_fsm_ci_counter0_reg_rx_count[0]), + .LO(plm_fsm_ci_counter0_reg_rx_count_qxu[0]) + ); + defparam plm_fsm_ci_counter0_reg_rx_count_qxu_0_1_.INIT = 4'h7; + LUT2_L plm_fsm_ci_counter0_reg_rx_count_qxu_0_1_ ( + .I0(I_5072_0_a2_0_a2_0_a4_25), + .I1(plm_fsm_ci_counter0_reg_rx_count[1]), + .LO(plm_fsm_ci_counter0_reg_rx_count_qxu[1]) + ); + defparam plm_fsm_ci_counter0_reg_rx_count_qxu_0_2_.INIT = 8'h1B; + LUT3_L plm_fsm_ci_counter0_reg_rx_count_qxu_0_2_ ( + .I0(I_5072_0_a2_0_a2_0_a4_25), + .I1(plm_fsm_ci_counter0_N_69074_i_983), + .I2(plm_fsm_ci_counter0_reg_rx_count[2]), + .LO(plm_fsm_ci_counter0_reg_rx_count_qxu[2]) + ); + defparam plm_fsm_ci_counter0_reg_rx_count_qxu_0_3_.INIT = 4'h7; + LUT2_L plm_fsm_ci_counter0_reg_rx_count_qxu_0_3_ ( + .I0(I_5072_0_a2_0_a2_0_a4_25), + .I1(plm_fsm_ci_counter0_reg_rx_count[3]), + .LO(plm_fsm_ci_counter0_reg_rx_count_qxu[3]) + ); + defparam plm_fsm_ci_counter0_reg_rx_count_qxu_0_4_.INIT = 4'h7; + LUT2_L plm_fsm_ci_counter0_reg_rx_count_qxu_0_4_ ( + .I0(I_5072_0_a2_0_a2_0_a4_25), + .I1(plm_fsm_ci_counter0_reg_rx_count[4]), + .LO(plm_fsm_ci_counter0_reg_rx_count_qxu[4]) + ); + defparam plm_fsm_ci_counter0_reg_rx_count_qxu_0_5_.INIT = 4'h7; + LUT2_L plm_fsm_ci_counter0_reg_rx_count_qxu_0_5_ ( + .I0(I_5072_0_a2_0_a2_0_a4_25), + .I1(plm_fsm_ci_counter0_reg_rx_count[5]), + .LO(plm_fsm_ci_counter0_reg_rx_count_qxu[5]) + ); + defparam plm_fsm_ci_counter0_reg_rx_count_qxu_0_6_.INIT = 4'h7; + LUT2_L plm_fsm_ci_counter0_reg_rx_count_qxu_0_6_ ( + .I0(I_5072_0_a2_0_a2_0_a4_25), + .I1(plm_fsm_ci_counter0_reg_rx_count[6]), + .LO(plm_fsm_ci_counter0_reg_rx_count_qxu[6]) + ); + defparam plm_fsm_ci_counter0_reg_rx_count_qxu_0_7_.INIT = 4'h7; + LUT2_L plm_fsm_ci_counter0_reg_rx_count_qxu_0_7_ ( + .I0(I_5072_0_a2_0_a2_0_a4_25), + .I1(plm_fsm_ci_counter0_reg_rx_count[7]), + .LO(plm_fsm_ci_counter0_reg_rx_count_qxu[7]) + ); + defparam plm_fsm_ci_counter0_reg_tx_count_qxu_0_0_.INIT = 4'h7; + LUT2_L plm_fsm_ci_counter0_reg_tx_count_qxu_0_0_ ( + .I0(plm_fsm_ci_counter0_un1_enable_1_0_a2_0_a2_0_a4_984), + .I1(plm_fsm_ci_counter0_reg_tx_count[0]), + .LO(plm_fsm_ci_counter0_reg_tx_count_qxu[0]) + ); + defparam plm_fsm_ci_counter0_reg_tx_count_qxu_0_1_.INIT = 4'h7; + LUT2_L plm_fsm_ci_counter0_reg_tx_count_qxu_0_1_ ( + .I0(plm_fsm_ci_counter0_un1_enable_1_0_a2_0_a2_0_a4_984), + .I1(plm_fsm_ci_counter0_reg_tx_count[1]), + .LO(plm_fsm_ci_counter0_reg_tx_count_qxu[1]) + ); + defparam plm_fsm_ci_counter0_reg_tx_count_qxu_0_2_.INIT = 4'h7; + LUT2_L plm_fsm_ci_counter0_reg_tx_count_qxu_0_2_ ( + .I0(plm_fsm_ci_counter0_un1_enable_1_0_a2_0_a2_0_a4_984), + .I1(plm_fsm_ci_counter0_reg_tx_count[2]), + .LO(plm_fsm_ci_counter0_reg_tx_count_qxu[2]) + ); + defparam plm_fsm_ci_counter0_reg_tx_count_qxu_0_3_.INIT = 8'h4E; + LUT3_L plm_fsm_ci_counter0_reg_tx_count_qxu_0_3_ ( + .I0(plm_fsm_ci_counter0_un1_enable_1_0_a2_0_a2_0_a4_984), + .I1(plm_fsm_ci_counter0_reg_tx_count17_0_a2_0_a2_0_a2_0_a4), + .I2(plm_fsm_ci_counter0_reg_tx_count[3]), + .LO(plm_fsm_ci_counter0_reg_tx_count_qxu[3]) + ); + defparam plm_fsm_ci_counter0_reg_tx_count_qxu_0_4_.INIT = 4'h7; + LUT2_L plm_fsm_ci_counter0_reg_tx_count_qxu_0_4_ ( + .I0(plm_fsm_ci_counter0_un1_enable_1_0_a2_0_a2_0_a4_984), + .I1(plm_fsm_ci_counter0_reg_tx_count[4]), + .LO(plm_fsm_ci_counter0_reg_tx_count_qxu[4]) + ); + defparam plm_fsm_ci_counter0_reg_tx_count_qxu_0_5_.INIT = 4'h7; + LUT2_L plm_fsm_ci_counter0_reg_tx_count_qxu_0_5_ ( + .I0(plm_fsm_ci_counter0_un1_enable_1_0_a2_0_a2_0_a4_984), + .I1(plm_fsm_ci_counter0_reg_tx_count[5]), + .LO(plm_fsm_ci_counter0_reg_tx_count_qxu[5]) + ); + defparam plm_fsm_ci_counter0_reg_tx_count_qxu_0_6_.INIT = 4'h7; + LUT2_L plm_fsm_ci_counter0_reg_tx_count_qxu_0_6_ ( + .I0(plm_fsm_ci_counter0_un1_enable_1_0_a2_0_a2_0_a4_984), + .I1(plm_fsm_ci_counter0_reg_tx_count[6]), + .LO(plm_fsm_ci_counter0_reg_tx_count_qxu[6]) + ); + defparam plm_fsm_ci_counter0_reg_tx_count_qxu_0_7_.INIT = 4'h7; + LUT2_L plm_fsm_ci_counter0_reg_tx_count_qxu_0_7_ ( + .I0(plm_fsm_ci_counter0_un1_enable_1_0_a2_0_a2_0_a4_984), + .I1(plm_fsm_ci_counter0_reg_tx_count[7]), + .LO(plm_fsm_ci_counter0_reg_tx_count_qxu[7]) + ); + VCC plm_fsm_ci_counter1_VCC ( + .P(plm_fsm_ci_counter1_VCC_985) + ); + MUXCY_L plm_fsm_ci_counter1_reg_tx_count_cry_0_ ( + .CI(plm_fsm_ci_counter1_un1_enable_1_i_990), + .DI(plm_fsm_ci_counter1_VCC_985), + .LO(plm_fsm_ci_counter1_reg_tx_count_cry[0]), + .S(plm_fsm_ci_counter1_reg_tx_count_qxu[0]) + ); + XORCY plm_fsm_ci_counter1_reg_tx_count_s_0_ ( + .CI(plm_fsm_ci_counter1_un1_enable_1_i_990), + .LI(plm_fsm_ci_counter1_reg_tx_count_qxu[0]), + .O(plm_fsm_ci_counter1_reg_tx_count_s[0]) + ); + MUXCY_L plm_fsm_ci_counter1_reg_tx_count_cry_1_ ( + .CI(plm_fsm_ci_counter1_reg_tx_count_cry[0]), + .DI(plm_fsm_ci_counter1_VCC_985), + .LO(plm_fsm_ci_counter1_reg_tx_count_cry[1]), + .S(plm_fsm_ci_counter1_reg_tx_count_qxu[1]) + ); + XORCY plm_fsm_ci_counter1_reg_tx_count_s_1_ ( + .CI(plm_fsm_ci_counter1_reg_tx_count_cry[0]), + .LI(plm_fsm_ci_counter1_reg_tx_count_qxu[1]), + .O(plm_fsm_ci_counter1_reg_tx_count_s[1]) + ); + MUXCY_L plm_fsm_ci_counter1_reg_tx_count_cry_2_ ( + .CI(plm_fsm_ci_counter1_reg_tx_count_cry[1]), + .DI(plm_fsm_ci_counter1_VCC_985), + .LO(plm_fsm_ci_counter1_reg_tx_count_cry[2]), + .S(plm_fsm_ci_counter1_reg_tx_count_qxu[2]) + ); + XORCY plm_fsm_ci_counter1_reg_tx_count_s_2_ ( + .CI(plm_fsm_ci_counter1_reg_tx_count_cry[1]), + .LI(plm_fsm_ci_counter1_reg_tx_count_qxu[2]), + .O(plm_fsm_ci_counter1_reg_tx_count_s[2]) + ); + MUXCY_L plm_fsm_ci_counter1_reg_tx_count_cry_3_ ( + .CI(plm_fsm_ci_counter1_reg_tx_count_cry[2]), + .DI(plm_fsm_ci_counter1_VCC_985), + .LO(plm_fsm_ci_counter1_reg_tx_count_cry[3]), + .S(plm_fsm_ci_counter1_reg_tx_count_qxu[3]) + ); + XORCY plm_fsm_ci_counter1_reg_tx_count_s_3_ ( + .CI(plm_fsm_ci_counter1_reg_tx_count_cry[2]), + .LI(plm_fsm_ci_counter1_reg_tx_count_qxu[3]), + .O(plm_fsm_ci_counter1_reg_tx_count_s[3]) + ); + MUXCY_L plm_fsm_ci_counter1_reg_tx_count_cry_4_ ( + .CI(plm_fsm_ci_counter1_reg_tx_count_cry[3]), + .DI(plm_fsm_ci_counter1_VCC_985), + .LO(plm_fsm_ci_counter1_reg_tx_count_cry[4]), + .S(plm_fsm_ci_counter1_reg_tx_count_qxu[4]) + ); + XORCY plm_fsm_ci_counter1_reg_tx_count_s_4_ ( + .CI(plm_fsm_ci_counter1_reg_tx_count_cry[3]), + .LI(plm_fsm_ci_counter1_reg_tx_count_qxu[4]), + .O(plm_fsm_ci_counter1_reg_tx_count_s[4]) + ); + MUXCY_L plm_fsm_ci_counter1_reg_tx_count_cry_5_ ( + .CI(plm_fsm_ci_counter1_reg_tx_count_cry[4]), + .DI(plm_fsm_ci_counter1_VCC_985), + .LO(plm_fsm_ci_counter1_reg_tx_count_cry[5]), + .S(plm_fsm_ci_counter1_reg_tx_count_qxu[5]) + ); + XORCY plm_fsm_ci_counter1_reg_tx_count_s_5_ ( + .CI(plm_fsm_ci_counter1_reg_tx_count_cry[4]), + .LI(plm_fsm_ci_counter1_reg_tx_count_qxu[5]), + .O(plm_fsm_ci_counter1_reg_tx_count_s[5]) + ); + MUXCY_L plm_fsm_ci_counter1_reg_tx_count_cry_6_ ( + .CI(plm_fsm_ci_counter1_reg_tx_count_cry[5]), + .DI(plm_fsm_ci_counter1_VCC_985), + .LO(plm_fsm_ci_counter1_reg_tx_count_cry[6]), + .S(plm_fsm_ci_counter1_reg_tx_count_qxu[6]) + ); + XORCY plm_fsm_ci_counter1_reg_tx_count_s_6_ ( + .CI(plm_fsm_ci_counter1_reg_tx_count_cry[5]), + .LI(plm_fsm_ci_counter1_reg_tx_count_qxu[6]), + .O(plm_fsm_ci_counter1_reg_tx_count_s[6]) + ); + XORCY plm_fsm_ci_counter1_reg_tx_count_s_7_ ( + .CI(plm_fsm_ci_counter1_reg_tx_count_cry[6]), + .LI(plm_fsm_ci_counter1_reg_tx_count_qxu[7]), + .O(plm_fsm_ci_counter1_reg_tx_count_s[7]) + ); + defparam plm_fsm_ci_counter1_loadable_rx_counter_N_9908_i.INIT = 4'h7; + LUT2 plm_fsm_ci_counter1_loadable_rx_counter_N_9908_i ( + .I0(plm_fsm_ci_counter1_reg_rx_count[2]), + .I1(plm_fsm_reg_state_11__360), + .O(plm_fsm_ci_counter1_N_9908_i) + ); + defparam plm_fsm_ci_counter1_loadable_rx_counter_N_38671_i.INIT = 4'hB; + LUT2 plm_fsm_ci_counter1_loadable_rx_counter_N_38671_i ( + .I0(plm_fsm_ci_counter1_reg_rx_expired_987), + .I1(plm_fsm_reg_state_11__360), + .O(plm_fsm_ci_counter1_N_38671_i) + ); + defparam plm_fsm_ci_counter1_loadable_tx_counter_un1_reg_tx_count_0_a2_0_a4_4.INIT = 16'h0001; + LUT4 plm_fsm_ci_counter1_loadable_tx_counter_un1_reg_tx_count_0_a2_0_a4_4 ( + .I0(plm_fsm_ci_counter1_reg_tx_count[0]), + .I1(plm_fsm_ci_counter1_reg_tx_count[1]), + .I2(plm_fsm_ci_counter1_reg_tx_count[2]), + .I3(plm_fsm_ci_counter1_reg_tx_count[3]), + .O(plm_fsm_ci_counter1_un1_reg_tx_count_0_a2_0_a4_4) + ); + defparam plm_fsm_ci_counter1_loadable_tx_counter_un1_reg_tx_count_0_a2_0_a4_5.INIT = 16'h0001; + LUT4 plm_fsm_ci_counter1_loadable_tx_counter_un1_reg_tx_count_0_a2_0_a4_5 ( + .I0(plm_fsm_ci_counter1_reg_tx_count[4]), + .I1(plm_fsm_ci_counter1_reg_tx_count[5]), + .I2(plm_fsm_ci_counter1_reg_tx_count[6]), + .I3(plm_fsm_ci_counter1_reg_tx_count[7]), + .O(plm_fsm_ci_counter1_un1_reg_tx_count_0_a2_0_a4_5) + ); + defparam plm_fsm_ci_counter1_N_38661_i.INIT = 4'hB; + LUT2 plm_fsm_ci_counter1_N_38661_i ( + .I0(plm_reg_sym_sent_0_), + .I1(plm_fsm_ci_counter1_un1_enable_1), + .O(plm_fsm_ci_counter1_N_38661_i_986) + ); + defparam plm_fsm_ci_counter1_un1_enable_2_i.INIT = 8'h8F; + LUT3 plm_fsm_ci_counter1_un1_enable_2_i ( + .I0(plm_fsm_ci_counter1_un1_reg_tx_count_0_a2_0_a4_4), + .I1(plm_fsm_ci_counter1_un1_reg_tx_count_0_a2_0_a4_5), + .I2(plm_fsm_un1_reg_tx_count17_0), + .O(plm_fsm_ci_counter1_un1_enable_2_i_988) + ); + defparam plm_fsm_ci_counter1_flagit_reg_expired_5_0_a2_0_a2_0_a4.INIT = 8'h80; + LUT3_L plm_fsm_ci_counter1_flagit_reg_expired_5_0_a2_0_a2_0_a4 ( + .I0(plm_fsm_ci_counter1_reg_rx_expired_987), + .I1(plm_fsm_ci_counter1_reg_tx_expired_989), + .I2(plm_fsm_reg_state_11__360), + .LO(plm_fsm_ci_counter1_reg_expired_5) + ); + defparam plm_fsm_ci_counter1_un1_enable_1_0_a2_0_a2_0_a4.INIT = 8'h40; + LUT3 plm_fsm_ci_counter1_un1_enable_1_0_a2_0_a2_0_a4 ( + .I0(plm_fsm_ci_counter1_reg_tx_expired_989), + .I1(plm_fsm_reg_state_11__360), + .I2(plm_fsm_reg_oneshot_0), + .O(plm_fsm_ci_counter1_un1_enable_1) + ); + FDCE plm_fsm_ci_counter1_reg_tx_count_7_ ( + .CE(plm_fsm_ci_counter1_N_38661_i_986), + .C(mgt_clk), + .D(plm_fsm_ci_counter1_reg_tx_count_s[7]), + .Q(plm_fsm_ci_counter1_reg_tx_count[7]), + .CLR(plm_rst) + ); + FDCE plm_fsm_ci_counter1_reg_tx_count_6_ ( + .CE(plm_fsm_ci_counter1_N_38661_i_986), + .C(mgt_clk), + .D(plm_fsm_ci_counter1_reg_tx_count_s[6]), + .Q(plm_fsm_ci_counter1_reg_tx_count[6]), + .CLR(plm_rst) + ); + FDCE plm_fsm_ci_counter1_reg_tx_count_5_ ( + .CE(plm_fsm_ci_counter1_N_38661_i_986), + .C(mgt_clk), + .D(plm_fsm_ci_counter1_reg_tx_count_s[5]), + .Q(plm_fsm_ci_counter1_reg_tx_count[5]), + .CLR(plm_rst) + ); + FDCE plm_fsm_ci_counter1_reg_tx_count_4_ ( + .CE(plm_fsm_ci_counter1_N_38661_i_986), + .C(mgt_clk), + .D(plm_fsm_ci_counter1_reg_tx_count_s[4]), + .Q(plm_fsm_ci_counter1_reg_tx_count[4]), + .CLR(plm_rst) + ); + FDPE plm_fsm_ci_counter1_reg_tx_count_3_ ( + .PRE(plm_rst), + .CE(plm_fsm_ci_counter1_N_38661_i_986), + .C(mgt_clk), + .D(plm_fsm_ci_counter1_reg_tx_count_s[3]), + .Q(plm_fsm_ci_counter1_reg_tx_count[3]) + ); + FDCE plm_fsm_ci_counter1_reg_tx_count_2_ ( + .CE(plm_fsm_ci_counter1_N_38661_i_986), + .C(mgt_clk), + .D(plm_fsm_ci_counter1_reg_tx_count_s[2]), + .Q(plm_fsm_ci_counter1_reg_tx_count[2]), + .CLR(plm_rst) + ); + FDCE plm_fsm_ci_counter1_reg_tx_count_1_ ( + .CE(plm_fsm_ci_counter1_N_38661_i_986), + .C(mgt_clk), + .D(plm_fsm_ci_counter1_reg_tx_count_s[1]), + .Q(plm_fsm_ci_counter1_reg_tx_count[1]), + .CLR(plm_rst) + ); + FDCE plm_fsm_ci_counter1_reg_tx_count_0_ ( + .CE(plm_fsm_ci_counter1_N_38661_i_986), + .C(mgt_clk), + .D(plm_fsm_ci_counter1_reg_tx_count_s[0]), + .Q(plm_fsm_ci_counter1_reg_tx_count[0]), + .CLR(plm_rst) + ); + FDC plm_fsm_ci_counter1_reg_expired ( + .C(mgt_clk), + .D(plm_fsm_ci_counter1_reg_expired_5), + .Q(plm_fsm_ci_cntrout1), + .CLR(plm_rst) + ); + FDPE plm_fsm_ci_counter1_reg_rx_count_2_ ( + .PRE(plm_rst), + .CE(plm_fsm_ci_counter1_N_38671_i), + .C(mgt_clk), + .D(plm_fsm_reg_state_i_11__906), + .Q(plm_fsm_ci_counter1_reg_rx_count[2]) + ); + FDCE plm_fsm_ci_counter1_reg_rx_expired ( + .CE(plm_fsm_ci_counter1_N_9908_i), + .C(mgt_clk), + .D(plm_fsm_reg_state_11__360), + .Q(plm_fsm_ci_counter1_reg_rx_expired_987), + .CLR(plm_rst) + ); + FDCE plm_fsm_ci_counter1_reg_tx_expired ( + .CE(plm_fsm_ci_counter1_un1_enable_2_i_988), + .C(mgt_clk), + .D(plm_fsm_un1_reg_tx_count17_0), + .Q(plm_fsm_ci_counter1_reg_tx_expired_989), + .CLR(plm_rst) + ); + INV plm_fsm_ci_counter1_un1_enable_1_i ( + .I(plm_fsm_ci_counter1_un1_enable_1), + .O(plm_fsm_ci_counter1_un1_enable_1_i_990) + ); + defparam plm_fsm_ci_counter1_reg_tx_count_qxu_0_0_.INIT = 4'h7; + LUT2_L plm_fsm_ci_counter1_reg_tx_count_qxu_0_0_ ( + .I0(plm_fsm_ci_counter1_reg_tx_count[0]), + .I1(plm_fsm_ci_counter1_un1_enable_1), + .LO(plm_fsm_ci_counter1_reg_tx_count_qxu[0]) + ); + defparam plm_fsm_ci_counter1_reg_tx_count_qxu_0_1_.INIT = 4'h7; + LUT2_L plm_fsm_ci_counter1_reg_tx_count_qxu_0_1_ ( + .I0(plm_fsm_ci_counter1_reg_tx_count[1]), + .I1(plm_fsm_ci_counter1_un1_enable_1), + .LO(plm_fsm_ci_counter1_reg_tx_count_qxu[1]) + ); + defparam plm_fsm_ci_counter1_reg_tx_count_qxu_0_2_.INIT = 4'h7; + LUT2_L plm_fsm_ci_counter1_reg_tx_count_qxu_0_2_ ( + .I0(plm_fsm_ci_counter1_reg_tx_count[2]), + .I1(plm_fsm_ci_counter1_un1_enable_1), + .LO(plm_fsm_ci_counter1_reg_tx_count_qxu[2]) + ); + defparam plm_fsm_ci_counter1_reg_tx_count_qxu_0_3_.INIT = 8'h74; + LUT3_L plm_fsm_ci_counter1_reg_tx_count_qxu_0_3_ ( + .I0(plm_fsm_ci_counter1_reg_tx_count[3]), + .I1(plm_fsm_ci_counter1_un1_enable_1), + .I2(plm_fsm_un1_reg_tx_count17_0), + .LO(plm_fsm_ci_counter1_reg_tx_count_qxu[3]) + ); + defparam plm_fsm_ci_counter1_reg_tx_count_qxu_0_4_.INIT = 4'h7; + LUT2_L plm_fsm_ci_counter1_reg_tx_count_qxu_0_4_ ( + .I0(plm_fsm_ci_counter1_reg_tx_count[4]), + .I1(plm_fsm_ci_counter1_un1_enable_1), + .LO(plm_fsm_ci_counter1_reg_tx_count_qxu[4]) + ); + defparam plm_fsm_ci_counter1_reg_tx_count_qxu_0_5_.INIT = 4'h7; + LUT2_L plm_fsm_ci_counter1_reg_tx_count_qxu_0_5_ ( + .I0(plm_fsm_ci_counter1_reg_tx_count[5]), + .I1(plm_fsm_ci_counter1_un1_enable_1), + .LO(plm_fsm_ci_counter1_reg_tx_count_qxu[5]) + ); + defparam plm_fsm_ci_counter1_reg_tx_count_qxu_0_6_.INIT = 4'h7; + LUT2_L plm_fsm_ci_counter1_reg_tx_count_qxu_0_6_ ( + .I0(plm_fsm_ci_counter1_reg_tx_count[6]), + .I1(plm_fsm_ci_counter1_un1_enable_1), + .LO(plm_fsm_ci_counter1_reg_tx_count_qxu[6]) + ); + defparam plm_fsm_ci_counter1_reg_tx_count_qxu_0_7_.INIT = 4'h7; + LUT2_L plm_fsm_ci_counter1_reg_tx_count_qxu_0_7_ ( + .I0(plm_fsm_ci_counter1_reg_tx_count[7]), + .I1(plm_fsm_ci_counter1_un1_enable_1), + .LO(plm_fsm_ci_counter1_reg_tx_count_qxu[7]) + ); + VCC plm_fsm_ci_counter2_VCC ( + .P(plm_fsm_ci_counter2_VCC_991) + ); + MUXCY_L plm_fsm_ci_counter2_reg_tx_count_cry_0_ ( + .CI(plm_fsm_ci_counter2_un1_enable_1_i_996), + .DI(plm_fsm_ci_counter2_VCC_991), + .LO(plm_fsm_ci_counter2_reg_tx_count_cry[0]), + .S(plm_fsm_ci_counter2_reg_tx_count_qxu[0]) + ); + XORCY plm_fsm_ci_counter2_reg_tx_count_s_0_ ( + .CI(plm_fsm_ci_counter2_un1_enable_1_i_996), + .LI(plm_fsm_ci_counter2_reg_tx_count_qxu[0]), + .O(plm_fsm_ci_counter2_reg_tx_count_s[0]) + ); + MUXCY_L plm_fsm_ci_counter2_reg_tx_count_cry_1_ ( + .CI(plm_fsm_ci_counter2_reg_tx_count_cry[0]), + .DI(plm_fsm_ci_counter2_VCC_991), + .LO(plm_fsm_ci_counter2_reg_tx_count_cry[1]), + .S(plm_fsm_ci_counter2_reg_tx_count_qxu[1]) + ); + XORCY plm_fsm_ci_counter2_reg_tx_count_s_1_ ( + .CI(plm_fsm_ci_counter2_reg_tx_count_cry[0]), + .LI(plm_fsm_ci_counter2_reg_tx_count_qxu[1]), + .O(plm_fsm_ci_counter2_reg_tx_count_s[1]) + ); + MUXCY_L plm_fsm_ci_counter2_reg_tx_count_cry_2_ ( + .CI(plm_fsm_ci_counter2_reg_tx_count_cry[1]), + .DI(plm_fsm_ci_counter2_VCC_991), + .LO(plm_fsm_ci_counter2_reg_tx_count_cry[2]), + .S(plm_fsm_ci_counter2_reg_tx_count_qxu[2]) + ); + XORCY plm_fsm_ci_counter2_reg_tx_count_s_2_ ( + .CI(plm_fsm_ci_counter2_reg_tx_count_cry[1]), + .LI(plm_fsm_ci_counter2_reg_tx_count_qxu[2]), + .O(plm_fsm_ci_counter2_reg_tx_count_s[2]) + ); + MUXCY_L plm_fsm_ci_counter2_reg_tx_count_cry_3_ ( + .CI(plm_fsm_ci_counter2_reg_tx_count_cry[2]), + .DI(plm_fsm_ci_counter2_VCC_991), + .LO(plm_fsm_ci_counter2_reg_tx_count_cry[3]), + .S(plm_fsm_ci_counter2_reg_tx_count_qxu[3]) + ); + XORCY plm_fsm_ci_counter2_reg_tx_count_s_3_ ( + .CI(plm_fsm_ci_counter2_reg_tx_count_cry[2]), + .LI(plm_fsm_ci_counter2_reg_tx_count_qxu[3]), + .O(plm_fsm_ci_counter2_reg_tx_count_s[3]) + ); + MUXCY_L plm_fsm_ci_counter2_reg_tx_count_cry_4_ ( + .CI(plm_fsm_ci_counter2_reg_tx_count_cry[3]), + .DI(plm_fsm_ci_counter2_VCC_991), + .LO(plm_fsm_ci_counter2_reg_tx_count_cry[4]), + .S(plm_fsm_ci_counter2_reg_tx_count_qxu[4]) + ); + XORCY plm_fsm_ci_counter2_reg_tx_count_s_4_ ( + .CI(plm_fsm_ci_counter2_reg_tx_count_cry[3]), + .LI(plm_fsm_ci_counter2_reg_tx_count_qxu[4]), + .O(plm_fsm_ci_counter2_reg_tx_count_s[4]) + ); + MUXCY_L plm_fsm_ci_counter2_reg_tx_count_cry_5_ ( + .CI(plm_fsm_ci_counter2_reg_tx_count_cry[4]), + .DI(plm_fsm_ci_counter2_VCC_991), + .LO(plm_fsm_ci_counter2_reg_tx_count_cry[5]), + .S(plm_fsm_ci_counter2_reg_tx_count_qxu[5]) + ); + XORCY plm_fsm_ci_counter2_reg_tx_count_s_5_ ( + .CI(plm_fsm_ci_counter2_reg_tx_count_cry[4]), + .LI(plm_fsm_ci_counter2_reg_tx_count_qxu[5]), + .O(plm_fsm_ci_counter2_reg_tx_count_s[5]) + ); + MUXCY_L plm_fsm_ci_counter2_reg_tx_count_cry_6_ ( + .CI(plm_fsm_ci_counter2_reg_tx_count_cry[5]), + .DI(plm_fsm_ci_counter2_VCC_991), + .LO(plm_fsm_ci_counter2_reg_tx_count_cry[6]), + .S(plm_fsm_ci_counter2_reg_tx_count_qxu[6]) + ); + XORCY plm_fsm_ci_counter2_reg_tx_count_s_6_ ( + .CI(plm_fsm_ci_counter2_reg_tx_count_cry[5]), + .LI(plm_fsm_ci_counter2_reg_tx_count_qxu[6]), + .O(plm_fsm_ci_counter2_reg_tx_count_s[6]) + ); + XORCY plm_fsm_ci_counter2_reg_tx_count_s_7_ ( + .CI(plm_fsm_ci_counter2_reg_tx_count_cry[6]), + .LI(plm_fsm_ci_counter2_reg_tx_count_qxu[7]), + .O(plm_fsm_ci_counter2_reg_tx_count_s[7]) + ); + defparam plm_fsm_ci_counter2_loadable_rx_counter_N_38697_i.INIT = 4'h7; + LUT2 plm_fsm_ci_counter2_loadable_rx_counter_N_38697_i ( + .I0(plm_fsm_ci_counter2_reg_rx_count[2]), + .I1(plm_fsm_reg_state_11__360), + .O(plm_fsm_ci_counter2_N_38697_i) + ); + defparam plm_fsm_ci_counter2_loadable_rx_counter_N_38721_i.INIT = 4'hB; + LUT2 plm_fsm_ci_counter2_loadable_rx_counter_N_38721_i ( + .I0(plm_fsm_ci_counter2_reg_rx_expired_993), + .I1(plm_fsm_reg_state_11__360), + .O(plm_fsm_ci_counter2_N_38721_i) + ); + defparam plm_fsm_ci_counter2_loadable_tx_counter_un1_reg_tx_count_0_a2_0_a4_4.INIT = 16'h0001; + LUT4 plm_fsm_ci_counter2_loadable_tx_counter_un1_reg_tx_count_0_a2_0_a4_4 ( + .I0(plm_fsm_ci_counter2_reg_tx_count[0]), + .I1(plm_fsm_ci_counter2_reg_tx_count[1]), + .I2(plm_fsm_ci_counter2_reg_tx_count[2]), + .I3(plm_fsm_ci_counter2_reg_tx_count[3]), + .O(plm_fsm_ci_counter2_un1_reg_tx_count_0_a2_0_a4_4) + ); + defparam plm_fsm_ci_counter2_loadable_tx_counter_un1_reg_tx_count_0_a2_0_a4_5.INIT = 16'h0001; + LUT4 plm_fsm_ci_counter2_loadable_tx_counter_un1_reg_tx_count_0_a2_0_a4_5 ( + .I0(plm_fsm_ci_counter2_reg_tx_count[4]), + .I1(plm_fsm_ci_counter2_reg_tx_count[5]), + .I2(plm_fsm_ci_counter2_reg_tx_count[6]), + .I3(plm_fsm_ci_counter2_reg_tx_count[7]), + .O(plm_fsm_ci_counter2_un1_reg_tx_count_0_a2_0_a4_5) + ); + defparam plm_fsm_ci_counter2_N_38662_i.INIT = 4'hB; + LUT2 plm_fsm_ci_counter2_N_38662_i ( + .I0(plm_reg_sym_sent_0_), + .I1(plm_fsm_ci_counter2_un1_enable_1), + .O(plm_fsm_ci_counter2_N_38662_i_992) + ); + defparam plm_fsm_ci_counter2_un1_enable_2_i.INIT = 8'h8F; + LUT3 plm_fsm_ci_counter2_un1_enable_2_i ( + .I0(plm_fsm_ci_counter2_un1_reg_tx_count_0_a2_0_a4_4), + .I1(plm_fsm_ci_counter2_un1_reg_tx_count_0_a2_0_a4_5), + .I2(plm_fsm_un1_reg_tx_count17_0), + .O(plm_fsm_ci_counter2_un1_enable_2_i_994) + ); + defparam plm_fsm_ci_counter2_flagit_reg_expired_5_0_a2_0_a2_0_a4.INIT = 8'h80; + LUT3_L plm_fsm_ci_counter2_flagit_reg_expired_5_0_a2_0_a2_0_a4 ( + .I0(plm_fsm_ci_counter2_reg_rx_expired_993), + .I1(plm_fsm_ci_counter2_reg_tx_expired_995), + .I2(plm_fsm_reg_state_11__360), + .LO(plm_fsm_ci_counter2_reg_expired_5) + ); + defparam plm_fsm_ci_counter2_un1_enable_1_0_a2_0_a2_0_a4.INIT = 8'h40; + LUT3 plm_fsm_ci_counter2_un1_enable_1_0_a2_0_a2_0_a4 ( + .I0(plm_fsm_ci_counter2_reg_tx_expired_995), + .I1(plm_fsm_reg_state_11__360), + .I2(plm_fsm_reg_oneshot_0), + .O(plm_fsm_ci_counter2_un1_enable_1) + ); + FDCE plm_fsm_ci_counter2_reg_tx_count_7_ ( + .CE(plm_fsm_ci_counter2_N_38662_i_992), + .C(mgt_clk), + .D(plm_fsm_ci_counter2_reg_tx_count_s[7]), + .Q(plm_fsm_ci_counter2_reg_tx_count[7]), + .CLR(plm_rst) + ); + FDCE plm_fsm_ci_counter2_reg_tx_count_6_ ( + .CE(plm_fsm_ci_counter2_N_38662_i_992), + .C(mgt_clk), + .D(plm_fsm_ci_counter2_reg_tx_count_s[6]), + .Q(plm_fsm_ci_counter2_reg_tx_count[6]), + .CLR(plm_rst) + ); + FDCE plm_fsm_ci_counter2_reg_tx_count_5_ ( + .CE(plm_fsm_ci_counter2_N_38662_i_992), + .C(mgt_clk), + .D(plm_fsm_ci_counter2_reg_tx_count_s[5]), + .Q(plm_fsm_ci_counter2_reg_tx_count[5]), + .CLR(plm_rst) + ); + FDCE plm_fsm_ci_counter2_reg_tx_count_4_ ( + .CE(plm_fsm_ci_counter2_N_38662_i_992), + .C(mgt_clk), + .D(plm_fsm_ci_counter2_reg_tx_count_s[4]), + .Q(plm_fsm_ci_counter2_reg_tx_count[4]), + .CLR(plm_rst) + ); + FDPE plm_fsm_ci_counter2_reg_tx_count_3_ ( + .PRE(plm_rst), + .CE(plm_fsm_ci_counter2_N_38662_i_992), + .C(mgt_clk), + .D(plm_fsm_ci_counter2_reg_tx_count_s[3]), + .Q(plm_fsm_ci_counter2_reg_tx_count[3]) + ); + FDCE plm_fsm_ci_counter2_reg_tx_count_2_ ( + .CE(plm_fsm_ci_counter2_N_38662_i_992), + .C(mgt_clk), + .D(plm_fsm_ci_counter2_reg_tx_count_s[2]), + .Q(plm_fsm_ci_counter2_reg_tx_count[2]), + .CLR(plm_rst) + ); + FDCE plm_fsm_ci_counter2_reg_tx_count_1_ ( + .CE(plm_fsm_ci_counter2_N_38662_i_992), + .C(mgt_clk), + .D(plm_fsm_ci_counter2_reg_tx_count_s[1]), + .Q(plm_fsm_ci_counter2_reg_tx_count[1]), + .CLR(plm_rst) + ); + FDCE plm_fsm_ci_counter2_reg_tx_count_0_ ( + .CE(plm_fsm_ci_counter2_N_38662_i_992), + .C(mgt_clk), + .D(plm_fsm_ci_counter2_reg_tx_count_s[0]), + .Q(plm_fsm_ci_counter2_reg_tx_count[0]), + .CLR(plm_rst) + ); + FDC plm_fsm_ci_counter2_reg_expired ( + .C(mgt_clk), + .D(plm_fsm_ci_counter2_reg_expired_5), + .Q(plm_fsm_ci_cntrout2), + .CLR(plm_rst) + ); + FDPE plm_fsm_ci_counter2_reg_rx_count_2_ ( + .PRE(plm_rst), + .CE(plm_fsm_ci_counter2_N_38721_i), + .C(mgt_clk), + .D(plm_fsm_reg_state_i_11__906), + .Q(plm_fsm_ci_counter2_reg_rx_count[2]) + ); + FDCE plm_fsm_ci_counter2_reg_rx_expired ( + .CE(plm_fsm_ci_counter2_N_38697_i), + .C(mgt_clk), + .D(plm_fsm_reg_state_11__360), + .Q(plm_fsm_ci_counter2_reg_rx_expired_993), + .CLR(plm_rst) + ); + FDCE plm_fsm_ci_counter2_reg_tx_expired ( + .CE(plm_fsm_ci_counter2_un1_enable_2_i_994), + .C(mgt_clk), + .D(plm_fsm_un1_reg_tx_count17_0), + .Q(plm_fsm_ci_counter2_reg_tx_expired_995), + .CLR(plm_rst) + ); + INV plm_fsm_ci_counter2_un1_enable_1_i ( + .I(plm_fsm_ci_counter2_un1_enable_1), + .O(plm_fsm_ci_counter2_un1_enable_1_i_996) + ); + defparam plm_fsm_ci_counter2_reg_tx_count_qxu_0_0_.INIT = 4'h7; + LUT2_L plm_fsm_ci_counter2_reg_tx_count_qxu_0_0_ ( + .I0(plm_fsm_ci_counter2_reg_tx_count[0]), + .I1(plm_fsm_ci_counter2_un1_enable_1), + .LO(plm_fsm_ci_counter2_reg_tx_count_qxu[0]) + ); + defparam plm_fsm_ci_counter2_reg_tx_count_qxu_0_1_.INIT = 4'h7; + LUT2_L plm_fsm_ci_counter2_reg_tx_count_qxu_0_1_ ( + .I0(plm_fsm_ci_counter2_reg_tx_count[1]), + .I1(plm_fsm_ci_counter2_un1_enable_1), + .LO(plm_fsm_ci_counter2_reg_tx_count_qxu[1]) + ); + defparam plm_fsm_ci_counter2_reg_tx_count_qxu_0_2_.INIT = 4'h7; + LUT2_L plm_fsm_ci_counter2_reg_tx_count_qxu_0_2_ ( + .I0(plm_fsm_ci_counter2_reg_tx_count[2]), + .I1(plm_fsm_ci_counter2_un1_enable_1), + .LO(plm_fsm_ci_counter2_reg_tx_count_qxu[2]) + ); + defparam plm_fsm_ci_counter2_reg_tx_count_qxu_0_3_.INIT = 8'h74; + LUT3_L plm_fsm_ci_counter2_reg_tx_count_qxu_0_3_ ( + .I0(plm_fsm_ci_counter2_reg_tx_count[3]), + .I1(plm_fsm_ci_counter2_un1_enable_1), + .I2(plm_fsm_un1_reg_tx_count17_0), + .LO(plm_fsm_ci_counter2_reg_tx_count_qxu[3]) + ); + defparam plm_fsm_ci_counter2_reg_tx_count_qxu_0_4_.INIT = 4'h7; + LUT2_L plm_fsm_ci_counter2_reg_tx_count_qxu_0_4_ ( + .I0(plm_fsm_ci_counter2_reg_tx_count[4]), + .I1(plm_fsm_ci_counter2_un1_enable_1), + .LO(plm_fsm_ci_counter2_reg_tx_count_qxu[4]) + ); + defparam plm_fsm_ci_counter2_reg_tx_count_qxu_0_5_.INIT = 4'h7; + LUT2_L plm_fsm_ci_counter2_reg_tx_count_qxu_0_5_ ( + .I0(plm_fsm_ci_counter2_reg_tx_count[5]), + .I1(plm_fsm_ci_counter2_un1_enable_1), + .LO(plm_fsm_ci_counter2_reg_tx_count_qxu[5]) + ); + defparam plm_fsm_ci_counter2_reg_tx_count_qxu_0_6_.INIT = 4'h7; + LUT2_L plm_fsm_ci_counter2_reg_tx_count_qxu_0_6_ ( + .I0(plm_fsm_ci_counter2_reg_tx_count[6]), + .I1(plm_fsm_ci_counter2_un1_enable_1), + .LO(plm_fsm_ci_counter2_reg_tx_count_qxu[6]) + ); + defparam plm_fsm_ci_counter2_reg_tx_count_qxu_0_7_.INIT = 4'h7; + LUT2_L plm_fsm_ci_counter2_reg_tx_count_qxu_0_7_ ( + .I0(plm_fsm_ci_counter2_reg_tx_count[7]), + .I1(plm_fsm_ci_counter2_un1_enable_1), + .LO(plm_fsm_ci_counter2_reg_tx_count_qxu[7]) + ); + VCC plm_fsm_ci_counter3_VCC ( + .P(plm_fsm_ci_counter3_VCC_997) + ); + MUXCY_L plm_fsm_ci_counter3_reg_tx_count_cry_0_ ( + .CI(plm_fsm_ci_counter3_un1_enable_1_i_1002), + .DI(plm_fsm_ci_counter3_VCC_997), + .LO(plm_fsm_ci_counter3_reg_tx_count_cry[0]), + .S(plm_fsm_ci_counter3_reg_tx_count_qxu[0]) + ); + XORCY plm_fsm_ci_counter3_reg_tx_count_s_0_ ( + .CI(plm_fsm_ci_counter3_un1_enable_1_i_1002), + .LI(plm_fsm_ci_counter3_reg_tx_count_qxu[0]), + .O(plm_fsm_ci_counter3_reg_tx_count_s[0]) + ); + MUXCY_L plm_fsm_ci_counter3_reg_tx_count_cry_1_ ( + .CI(plm_fsm_ci_counter3_reg_tx_count_cry[0]), + .DI(plm_fsm_ci_counter3_VCC_997), + .LO(plm_fsm_ci_counter3_reg_tx_count_cry[1]), + .S(plm_fsm_ci_counter3_reg_tx_count_qxu[1]) + ); + XORCY plm_fsm_ci_counter3_reg_tx_count_s_1_ ( + .CI(plm_fsm_ci_counter3_reg_tx_count_cry[0]), + .LI(plm_fsm_ci_counter3_reg_tx_count_qxu[1]), + .O(plm_fsm_ci_counter3_reg_tx_count_s[1]) + ); + MUXCY_L plm_fsm_ci_counter3_reg_tx_count_cry_2_ ( + .CI(plm_fsm_ci_counter3_reg_tx_count_cry[1]), + .DI(plm_fsm_ci_counter3_VCC_997), + .LO(plm_fsm_ci_counter3_reg_tx_count_cry[2]), + .S(plm_fsm_ci_counter3_reg_tx_count_qxu[2]) + ); + XORCY plm_fsm_ci_counter3_reg_tx_count_s_2_ ( + .CI(plm_fsm_ci_counter3_reg_tx_count_cry[1]), + .LI(plm_fsm_ci_counter3_reg_tx_count_qxu[2]), + .O(plm_fsm_ci_counter3_reg_tx_count_s[2]) + ); + MUXCY_L plm_fsm_ci_counter3_reg_tx_count_cry_3_ ( + .CI(plm_fsm_ci_counter3_reg_tx_count_cry[2]), + .DI(plm_fsm_ci_counter3_VCC_997), + .LO(plm_fsm_ci_counter3_reg_tx_count_cry[3]), + .S(plm_fsm_ci_counter3_reg_tx_count_qxu[3]) + ); + XORCY plm_fsm_ci_counter3_reg_tx_count_s_3_ ( + .CI(plm_fsm_ci_counter3_reg_tx_count_cry[2]), + .LI(plm_fsm_ci_counter3_reg_tx_count_qxu[3]), + .O(plm_fsm_ci_counter3_reg_tx_count_s[3]) + ); + MUXCY_L plm_fsm_ci_counter3_reg_tx_count_cry_4_ ( + .CI(plm_fsm_ci_counter3_reg_tx_count_cry[3]), + .DI(plm_fsm_ci_counter3_VCC_997), + .LO(plm_fsm_ci_counter3_reg_tx_count_cry[4]), + .S(plm_fsm_ci_counter3_reg_tx_count_qxu[4]) + ); + XORCY plm_fsm_ci_counter3_reg_tx_count_s_4_ ( + .CI(plm_fsm_ci_counter3_reg_tx_count_cry[3]), + .LI(plm_fsm_ci_counter3_reg_tx_count_qxu[4]), + .O(plm_fsm_ci_counter3_reg_tx_count_s[4]) + ); + MUXCY_L plm_fsm_ci_counter3_reg_tx_count_cry_5_ ( + .CI(plm_fsm_ci_counter3_reg_tx_count_cry[4]), + .DI(plm_fsm_ci_counter3_VCC_997), + .LO(plm_fsm_ci_counter3_reg_tx_count_cry[5]), + .S(plm_fsm_ci_counter3_reg_tx_count_qxu[5]) + ); + XORCY plm_fsm_ci_counter3_reg_tx_count_s_5_ ( + .CI(plm_fsm_ci_counter3_reg_tx_count_cry[4]), + .LI(plm_fsm_ci_counter3_reg_tx_count_qxu[5]), + .O(plm_fsm_ci_counter3_reg_tx_count_s[5]) + ); + MUXCY_L plm_fsm_ci_counter3_reg_tx_count_cry_6_ ( + .CI(plm_fsm_ci_counter3_reg_tx_count_cry[5]), + .DI(plm_fsm_ci_counter3_VCC_997), + .LO(plm_fsm_ci_counter3_reg_tx_count_cry[6]), + .S(plm_fsm_ci_counter3_reg_tx_count_qxu[6]) + ); + XORCY plm_fsm_ci_counter3_reg_tx_count_s_6_ ( + .CI(plm_fsm_ci_counter3_reg_tx_count_cry[5]), + .LI(plm_fsm_ci_counter3_reg_tx_count_qxu[6]), + .O(plm_fsm_ci_counter3_reg_tx_count_s[6]) + ); + XORCY plm_fsm_ci_counter3_reg_tx_count_s_7_ ( + .CI(plm_fsm_ci_counter3_reg_tx_count_cry[6]), + .LI(plm_fsm_ci_counter3_reg_tx_count_qxu[7]), + .O(plm_fsm_ci_counter3_reg_tx_count_s[7]) + ); + defparam plm_fsm_ci_counter3_loadable_tx_counter_reg_tx_count17_0_a2_0_a3_0_a3.INIT = 4'h8; + LUT2 plm_fsm_ci_counter3_loadable_tx_counter_reg_tx_count17_0_a2_0_a3_0_a3 ( + .I0(plm_fsm_reg_oneshot_0), + .I1(plm_fsm_reg_state_11__360), + .O(plm_fsm_un1_reg_tx_count17_0) + ); + defparam plm_fsm_ci_counter3_loadable_rx_counter_N_38696_i.INIT = 4'h7; + LUT2 plm_fsm_ci_counter3_loadable_rx_counter_N_38696_i ( + .I0(plm_fsm_ci_counter3_reg_rx_count[2]), + .I1(plm_fsm_reg_state_11__360), + .O(plm_fsm_ci_counter3_N_38696_i) + ); + defparam plm_fsm_ci_counter3_loadable_rx_counter_N_38720_i.INIT = 4'hB; + LUT2 plm_fsm_ci_counter3_loadable_rx_counter_N_38720_i ( + .I0(plm_fsm_ci_counter3_reg_rx_expired_999), + .I1(plm_fsm_reg_state_11__360), + .O(plm_fsm_ci_counter3_N_38720_i) + ); + defparam plm_fsm_ci_counter3_loadable_tx_counter_un1_reg_tx_count_0_a2_4.INIT = 16'h0001; + LUT4 plm_fsm_ci_counter3_loadable_tx_counter_un1_reg_tx_count_0_a2_4 ( + .I0(plm_fsm_ci_counter3_reg_tx_count[0]), + .I1(plm_fsm_ci_counter3_reg_tx_count[1]), + .I2(plm_fsm_ci_counter3_reg_tx_count[2]), + .I3(plm_fsm_ci_counter3_reg_tx_count[3]), + .O(plm_fsm_ci_counter3_un1_reg_tx_count_0_a2_4) + ); + defparam plm_fsm_ci_counter3_loadable_tx_counter_un1_reg_tx_count_0_a2_5.INIT = 16'h0001; + LUT4 plm_fsm_ci_counter3_loadable_tx_counter_un1_reg_tx_count_0_a2_5 ( + .I0(plm_fsm_ci_counter3_reg_tx_count[4]), + .I1(plm_fsm_ci_counter3_reg_tx_count[5]), + .I2(plm_fsm_ci_counter3_reg_tx_count[6]), + .I3(plm_fsm_ci_counter3_reg_tx_count[7]), + .O(plm_fsm_ci_counter3_un1_reg_tx_count_0_a2_5) + ); + defparam plm_fsm_ci_counter3_N_38663_i.INIT = 4'hB; + LUT2 plm_fsm_ci_counter3_N_38663_i ( + .I0(plm_reg_sym_sent_0_), + .I1(plm_fsm_ci_counter3_un1_enable_1), + .O(plm_fsm_ci_counter3_N_38663_i_998) + ); + defparam plm_fsm_ci_counter3_un1_enable_2_i.INIT = 8'h8F; + LUT3 plm_fsm_ci_counter3_un1_enable_2_i ( + .I0(plm_fsm_ci_counter3_un1_reg_tx_count_0_a2_4), + .I1(plm_fsm_ci_counter3_un1_reg_tx_count_0_a2_5), + .I2(plm_fsm_un1_reg_tx_count17_0), + .O(plm_fsm_ci_counter3_un1_enable_2_i_1000) + ); + defparam plm_fsm_ci_counter3_flagit_reg_expired_5_0_a2_0_a2_0_a4.INIT = 8'h80; + LUT3_L plm_fsm_ci_counter3_flagit_reg_expired_5_0_a2_0_a2_0_a4 ( + .I0(plm_fsm_ci_counter3_reg_rx_expired_999), + .I1(plm_fsm_ci_counter3_reg_tx_expired_1001), + .I2(plm_fsm_reg_state_11__360), + .LO(plm_fsm_ci_counter3_reg_expired_5) + ); + defparam plm_fsm_ci_counter3_un1_enable_1_0_a2_0_a2_0_a4.INIT = 8'h40; + LUT3 plm_fsm_ci_counter3_un1_enable_1_0_a2_0_a2_0_a4 ( + .I0(plm_fsm_ci_counter3_reg_tx_expired_1001), + .I1(plm_fsm_reg_state_11__360), + .I2(plm_fsm_reg_oneshot_0), + .O(plm_fsm_ci_counter3_un1_enable_1) + ); + FDCE plm_fsm_ci_counter3_reg_tx_count_7_ ( + .CE(plm_fsm_ci_counter3_N_38663_i_998), + .C(mgt_clk), + .D(plm_fsm_ci_counter3_reg_tx_count_s[7]), + .Q(plm_fsm_ci_counter3_reg_tx_count[7]), + .CLR(plm_rst) + ); + FDCE plm_fsm_ci_counter3_reg_tx_count_6_ ( + .CE(plm_fsm_ci_counter3_N_38663_i_998), + .C(mgt_clk), + .D(plm_fsm_ci_counter3_reg_tx_count_s[6]), + .Q(plm_fsm_ci_counter3_reg_tx_count[6]), + .CLR(plm_rst) + ); + FDCE plm_fsm_ci_counter3_reg_tx_count_5_ ( + .CE(plm_fsm_ci_counter3_N_38663_i_998), + .C(mgt_clk), + .D(plm_fsm_ci_counter3_reg_tx_count_s[5]), + .Q(plm_fsm_ci_counter3_reg_tx_count[5]), + .CLR(plm_rst) + ); + FDCE plm_fsm_ci_counter3_reg_tx_count_4_ ( + .CE(plm_fsm_ci_counter3_N_38663_i_998), + .C(mgt_clk), + .D(plm_fsm_ci_counter3_reg_tx_count_s[4]), + .Q(plm_fsm_ci_counter3_reg_tx_count[4]), + .CLR(plm_rst) + ); + FDPE plm_fsm_ci_counter3_reg_tx_count_3_ ( + .PRE(plm_rst), + .CE(plm_fsm_ci_counter3_N_38663_i_998), + .C(mgt_clk), + .D(plm_fsm_ci_counter3_reg_tx_count_s[3]), + .Q(plm_fsm_ci_counter3_reg_tx_count[3]) + ); + FDCE plm_fsm_ci_counter3_reg_tx_count_2_ ( + .CE(plm_fsm_ci_counter3_N_38663_i_998), + .C(mgt_clk), + .D(plm_fsm_ci_counter3_reg_tx_count_s[2]), + .Q(plm_fsm_ci_counter3_reg_tx_count[2]), + .CLR(plm_rst) + ); + FDCE plm_fsm_ci_counter3_reg_tx_count_1_ ( + .CE(plm_fsm_ci_counter3_N_38663_i_998), + .C(mgt_clk), + .D(plm_fsm_ci_counter3_reg_tx_count_s[1]), + .Q(plm_fsm_ci_counter3_reg_tx_count[1]), + .CLR(plm_rst) + ); + FDCE plm_fsm_ci_counter3_reg_tx_count_0_ ( + .CE(plm_fsm_ci_counter3_N_38663_i_998), + .C(mgt_clk), + .D(plm_fsm_ci_counter3_reg_tx_count_s[0]), + .Q(plm_fsm_ci_counter3_reg_tx_count[0]), + .CLR(plm_rst) + ); + FDC plm_fsm_ci_counter3_reg_expired ( + .C(mgt_clk), + .D(plm_fsm_ci_counter3_reg_expired_5), + .Q(plm_fsm_ci_cntrout3), + .CLR(plm_rst) + ); + FDPE plm_fsm_ci_counter3_reg_rx_count_2_ ( + .PRE(plm_rst), + .CE(plm_fsm_ci_counter3_N_38720_i), + .C(mgt_clk), + .D(plm_fsm_reg_state_i_11__906), + .Q(plm_fsm_ci_counter3_reg_rx_count[2]) + ); + FDCE plm_fsm_ci_counter3_reg_oneshot ( + .CE(plm_fsm_reg_state_i_11__906), + .C(mgt_clk), + .D(plm_fsm_reg_state_11__360), + .Q(plm_fsm_reg_oneshot_0), + .CLR(plm_rst) + ); + FDCE plm_fsm_ci_counter3_reg_rx_expired ( + .CE(plm_fsm_ci_counter3_N_38696_i), + .C(mgt_clk), + .D(plm_fsm_reg_state_11__360), + .Q(plm_fsm_ci_counter3_reg_rx_expired_999), + .CLR(plm_rst) + ); + FDCE plm_fsm_ci_counter3_reg_tx_expired ( + .CE(plm_fsm_ci_counter3_un1_enable_2_i_1000), + .C(mgt_clk), + .D(plm_fsm_un1_reg_tx_count17_0), + .Q(plm_fsm_ci_counter3_reg_tx_expired_1001), + .CLR(plm_rst) + ); + INV plm_fsm_ci_counter3_un1_enable_1_i ( + .I(plm_fsm_ci_counter3_un1_enable_1), + .O(plm_fsm_ci_counter3_un1_enable_1_i_1002) + ); + defparam plm_fsm_ci_counter3_reg_tx_count_qxu_0_0_.INIT = 4'h7; + LUT2_L plm_fsm_ci_counter3_reg_tx_count_qxu_0_0_ ( + .I0(plm_fsm_ci_counter3_reg_tx_count[0]), + .I1(plm_fsm_ci_counter3_un1_enable_1), + .LO(plm_fsm_ci_counter3_reg_tx_count_qxu[0]) + ); + defparam plm_fsm_ci_counter3_reg_tx_count_qxu_0_1_.INIT = 4'h7; + LUT2_L plm_fsm_ci_counter3_reg_tx_count_qxu_0_1_ ( + .I0(plm_fsm_ci_counter3_reg_tx_count[1]), + .I1(plm_fsm_ci_counter3_un1_enable_1), + .LO(plm_fsm_ci_counter3_reg_tx_count_qxu[1]) + ); + defparam plm_fsm_ci_counter3_reg_tx_count_qxu_0_2_.INIT = 4'h7; + LUT2_L plm_fsm_ci_counter3_reg_tx_count_qxu_0_2_ ( + .I0(plm_fsm_ci_counter3_reg_tx_count[2]), + .I1(plm_fsm_ci_counter3_un1_enable_1), + .LO(plm_fsm_ci_counter3_reg_tx_count_qxu[2]) + ); + defparam plm_fsm_ci_counter3_reg_tx_count_qxu_0_3_.INIT = 8'h74; + LUT3_L plm_fsm_ci_counter3_reg_tx_count_qxu_0_3_ ( + .I0(plm_fsm_ci_counter3_reg_tx_count[3]), + .I1(plm_fsm_ci_counter3_un1_enable_1), + .I2(plm_fsm_un1_reg_tx_count17_0), + .LO(plm_fsm_ci_counter3_reg_tx_count_qxu[3]) + ); + defparam plm_fsm_ci_counter3_reg_tx_count_qxu_0_4_.INIT = 4'h7; + LUT2_L plm_fsm_ci_counter3_reg_tx_count_qxu_0_4_ ( + .I0(plm_fsm_ci_counter3_reg_tx_count[4]), + .I1(plm_fsm_ci_counter3_un1_enable_1), + .LO(plm_fsm_ci_counter3_reg_tx_count_qxu[4]) + ); + defparam plm_fsm_ci_counter3_reg_tx_count_qxu_0_5_.INIT = 4'h7; + LUT2_L plm_fsm_ci_counter3_reg_tx_count_qxu_0_5_ ( + .I0(plm_fsm_ci_counter3_reg_tx_count[5]), + .I1(plm_fsm_ci_counter3_un1_enable_1), + .LO(plm_fsm_ci_counter3_reg_tx_count_qxu[5]) + ); + defparam plm_fsm_ci_counter3_reg_tx_count_qxu_0_6_.INIT = 4'h7; + LUT2_L plm_fsm_ci_counter3_reg_tx_count_qxu_0_6_ ( + .I0(plm_fsm_ci_counter3_reg_tx_count[6]), + .I1(plm_fsm_ci_counter3_un1_enable_1), + .LO(plm_fsm_ci_counter3_reg_tx_count_qxu[6]) + ); + defparam plm_fsm_ci_counter3_reg_tx_count_qxu_0_7_.INIT = 4'h7; + LUT2_L plm_fsm_ci_counter3_reg_tx_count_qxu_0_7_ ( + .I0(plm_fsm_ci_counter3_reg_tx_count[7]), + .I1(plm_fsm_ci_counter3_un1_enable_1), + .LO(plm_fsm_ci_counter3_reg_tx_count_qxu[7]) + ); + GND plm_fsm_rl_timer_GND ( + .G(plm_fsm_rl_timer_GND_1003) + ); + MUXCY_L plm_fsm_rl_timer_reg_count_cry_0_ ( + .CI(plm_fsm_reg_state_13__41), + .DI(plm_fsm_rl_timer_GND_1003), + .LO(plm_fsm_rl_timer_reg_count_cry[0]), + .S(plm_fsm_rl_timer_reg_count_qxu[0]) + ); + XORCY plm_fsm_rl_timer_reg_count_s_0_ ( + .CI(plm_fsm_reg_state_13__41), + .LI(plm_fsm_rl_timer_reg_count_qxu[0]), + .O(plm_fsm_rl_timer_reg_count_s[0]) + ); + MUXCY_L plm_fsm_rl_timer_reg_count_cry_1_ ( + .CI(plm_fsm_rl_timer_reg_count_cry[0]), + .DI(plm_fsm_rl_timer_GND_1003), + .LO(plm_fsm_rl_timer_reg_count_cry[1]), + .S(plm_fsm_rl_timer_reg_count_qxu[1]) + ); + XORCY plm_fsm_rl_timer_reg_count_s_1_ ( + .CI(plm_fsm_rl_timer_reg_count_cry[0]), + .LI(plm_fsm_rl_timer_reg_count_qxu[1]), + .O(plm_fsm_rl_timer_reg_count_s[1]) + ); + MUXCY_L plm_fsm_rl_timer_reg_count_cry_2_ ( + .CI(plm_fsm_rl_timer_reg_count_cry[1]), + .DI(plm_fsm_rl_timer_GND_1003), + .LO(plm_fsm_rl_timer_reg_count_cry[2]), + .S(plm_fsm_rl_timer_reg_count_qxu[2]) + ); + XORCY plm_fsm_rl_timer_reg_count_s_2_ ( + .CI(plm_fsm_rl_timer_reg_count_cry[1]), + .LI(plm_fsm_rl_timer_reg_count_qxu[2]), + .O(plm_fsm_rl_timer_reg_count_s[2]) + ); + MUXCY_L plm_fsm_rl_timer_reg_count_cry_3_ ( + .CI(plm_fsm_rl_timer_reg_count_cry[2]), + .DI(plm_fsm_rl_timer_GND_1003), + .LO(plm_fsm_rl_timer_reg_count_cry[3]), + .S(plm_fsm_rl_timer_reg_count_qxu[3]) + ); + XORCY plm_fsm_rl_timer_reg_count_s_3_ ( + .CI(plm_fsm_rl_timer_reg_count_cry[2]), + .LI(plm_fsm_rl_timer_reg_count_qxu[3]), + .O(plm_fsm_rl_timer_reg_count_s[3]) + ); + MUXCY_L plm_fsm_rl_timer_reg_count_cry_4_ ( + .CI(plm_fsm_rl_timer_reg_count_cry[3]), + .DI(plm_fsm_rl_timer_GND_1003), + .LO(plm_fsm_rl_timer_reg_count_cry[4]), + .S(plm_fsm_rl_timer_reg_count_qxu[4]) + ); + XORCY plm_fsm_rl_timer_reg_count_s_4_ ( + .CI(plm_fsm_rl_timer_reg_count_cry[3]), + .LI(plm_fsm_rl_timer_reg_count_qxu[4]), + .O(plm_fsm_rl_timer_reg_count_s[4]) + ); + MUXCY_L plm_fsm_rl_timer_reg_count_cry_5_ ( + .CI(plm_fsm_rl_timer_reg_count_cry[4]), + .DI(plm_fsm_rl_timer_GND_1003), + .LO(plm_fsm_rl_timer_reg_count_cry[5]), + .S(plm_fsm_rl_timer_reg_count_qxu[5]) + ); + XORCY plm_fsm_rl_timer_reg_count_s_5_ ( + .CI(plm_fsm_rl_timer_reg_count_cry[4]), + .LI(plm_fsm_rl_timer_reg_count_qxu[5]), + .O(plm_fsm_rl_timer_reg_count_s[5]) + ); + MUXCY_L plm_fsm_rl_timer_reg_count_cry_6_ ( + .CI(plm_fsm_rl_timer_reg_count_cry[5]), + .DI(plm_fsm_rl_timer_GND_1003), + .LO(plm_fsm_rl_timer_reg_count_cry[6]), + .S(plm_fsm_rl_timer_reg_count_qxu[6]) + ); + XORCY plm_fsm_rl_timer_reg_count_s_6_ ( + .CI(plm_fsm_rl_timer_reg_count_cry[5]), + .LI(plm_fsm_rl_timer_reg_count_qxu[6]), + .O(plm_fsm_rl_timer_reg_count_s[6]) + ); + MUXCY_L plm_fsm_rl_timer_reg_count_cry_7_ ( + .CI(plm_fsm_rl_timer_reg_count_cry[6]), + .DI(plm_fsm_rl_timer_GND_1003), + .LO(plm_fsm_rl_timer_reg_count_cry[7]), + .S(plm_fsm_rl_timer_reg_count_qxu[7]) + ); + XORCY plm_fsm_rl_timer_reg_count_s_7_ ( + .CI(plm_fsm_rl_timer_reg_count_cry[6]), + .LI(plm_fsm_rl_timer_reg_count_qxu[7]), + .O(plm_fsm_rl_timer_reg_count_s[7]) + ); + MUXCY_L plm_fsm_rl_timer_reg_count_cry_8_ ( + .CI(plm_fsm_rl_timer_reg_count_cry[7]), + .DI(plm_fsm_rl_timer_GND_1003), + .LO(plm_fsm_rl_timer_reg_count_cry[8]), + .S(plm_fsm_rl_timer_reg_count_qxu[8]) + ); + XORCY plm_fsm_rl_timer_reg_count_s_8_ ( + .CI(plm_fsm_rl_timer_reg_count_cry[7]), + .LI(plm_fsm_rl_timer_reg_count_qxu[8]), + .O(plm_fsm_rl_timer_reg_count_s[8]) + ); + MUXCY_L plm_fsm_rl_timer_reg_count_cry_9_ ( + .CI(plm_fsm_rl_timer_reg_count_cry[8]), + .DI(plm_fsm_rl_timer_GND_1003), + .LO(plm_fsm_rl_timer_reg_count_cry[9]), + .S(plm_fsm_rl_timer_reg_count_qxu[9]) + ); + XORCY plm_fsm_rl_timer_reg_count_s_9_ ( + .CI(plm_fsm_rl_timer_reg_count_cry[8]), + .LI(plm_fsm_rl_timer_reg_count_qxu[9]), + .O(plm_fsm_rl_timer_reg_count_s[9]) + ); + MUXCY_L plm_fsm_rl_timer_reg_count_cry_10_ ( + .CI(plm_fsm_rl_timer_reg_count_cry[9]), + .DI(plm_fsm_rl_timer_GND_1003), + .LO(plm_fsm_rl_timer_reg_count_cry[10]), + .S(plm_fsm_rl_timer_reg_count_qxu[10]) + ); + XORCY plm_fsm_rl_timer_reg_count_s_10_ ( + .CI(plm_fsm_rl_timer_reg_count_cry[9]), + .LI(plm_fsm_rl_timer_reg_count_qxu[10]), + .O(plm_fsm_rl_timer_reg_count_s[10]) + ); + MUXCY_L plm_fsm_rl_timer_reg_count_cry_11_ ( + .CI(plm_fsm_rl_timer_reg_count_cry[10]), + .DI(plm_fsm_rl_timer_GND_1003), + .LO(plm_fsm_rl_timer_reg_count_cry[11]), + .S(plm_fsm_rl_timer_reg_count_qxu[11]) + ); + XORCY plm_fsm_rl_timer_reg_count_s_11_ ( + .CI(plm_fsm_rl_timer_reg_count_cry[10]), + .LI(plm_fsm_rl_timer_reg_count_qxu[11]), + .O(plm_fsm_rl_timer_reg_count_s[11]) + ); + MUXCY_L plm_fsm_rl_timer_reg_count_cry_12_ ( + .CI(plm_fsm_rl_timer_reg_count_cry[11]), + .DI(plm_fsm_rl_timer_GND_1003), + .LO(plm_fsm_rl_timer_reg_count_cry[12]), + .S(plm_fsm_rl_timer_reg_count_qxu[12]) + ); + XORCY plm_fsm_rl_timer_reg_count_s_12_ ( + .CI(plm_fsm_rl_timer_reg_count_cry[11]), + .LI(plm_fsm_rl_timer_reg_count_qxu[12]), + .O(plm_fsm_rl_timer_reg_count_s[12]) + ); + MUXCY_L plm_fsm_rl_timer_reg_count_cry_13_ ( + .CI(plm_fsm_rl_timer_reg_count_cry[12]), + .DI(plm_fsm_rl_timer_GND_1003), + .LO(plm_fsm_rl_timer_reg_count_cry[13]), + .S(plm_fsm_rl_timer_reg_count_qxu[13]) + ); + XORCY plm_fsm_rl_timer_reg_count_s_13_ ( + .CI(plm_fsm_rl_timer_reg_count_cry[12]), + .LI(plm_fsm_rl_timer_reg_count_qxu[13]), + .O(plm_fsm_rl_timer_reg_count_s[13]) + ); + MUXCY_L plm_fsm_rl_timer_reg_count_cry_14_ ( + .CI(plm_fsm_rl_timer_reg_count_cry[13]), + .DI(plm_fsm_rl_timer_GND_1003), + .LO(plm_fsm_rl_timer_reg_count_cry[14]), + .S(plm_fsm_rl_timer_reg_count_qxu[14]) + ); + XORCY plm_fsm_rl_timer_reg_count_s_14_ ( + .CI(plm_fsm_rl_timer_reg_count_cry[13]), + .LI(plm_fsm_rl_timer_reg_count_qxu[14]), + .O(plm_fsm_rl_timer_reg_count_s[14]) + ); + MUXCY_L plm_fsm_rl_timer_reg_count_cry_15_ ( + .CI(plm_fsm_rl_timer_reg_count_cry[14]), + .DI(plm_fsm_rl_timer_GND_1003), + .LO(plm_fsm_rl_timer_reg_count_cry[15]), + .S(plm_fsm_rl_timer_reg_count_qxu[15]) + ); + XORCY plm_fsm_rl_timer_reg_count_s_15_ ( + .CI(plm_fsm_rl_timer_reg_count_cry[14]), + .LI(plm_fsm_rl_timer_reg_count_qxu[15]), + .O(plm_fsm_rl_timer_reg_count_s[15]) + ); + MUXCY_L plm_fsm_rl_timer_reg_count_cry_16_ ( + .CI(plm_fsm_rl_timer_reg_count_cry[15]), + .DI(plm_fsm_rl_timer_GND_1003), + .LO(plm_fsm_rl_timer_reg_count_cry[16]), + .S(plm_fsm_rl_timer_reg_count_qxu[16]) + ); + XORCY plm_fsm_rl_timer_reg_count_s_16_ ( + .CI(plm_fsm_rl_timer_reg_count_cry[15]), + .LI(plm_fsm_rl_timer_reg_count_qxu[16]), + .O(plm_fsm_rl_timer_reg_count_s[16]) + ); + MUXCY_L plm_fsm_rl_timer_reg_count_cry_17_ ( + .CI(plm_fsm_rl_timer_reg_count_cry[16]), + .DI(plm_fsm_rl_timer_GND_1003), + .LO(plm_fsm_rl_timer_reg_count_cry[17]), + .S(plm_fsm_rl_timer_reg_count_qxu[17]) + ); + XORCY plm_fsm_rl_timer_reg_count_s_17_ ( + .CI(plm_fsm_rl_timer_reg_count_cry[16]), + .LI(plm_fsm_rl_timer_reg_count_qxu[17]), + .O(plm_fsm_rl_timer_reg_count_s[17]) + ); + MUXCY_L plm_fsm_rl_timer_reg_count_cry_18_ ( + .CI(plm_fsm_rl_timer_reg_count_cry[17]), + .DI(plm_fsm_rl_timer_GND_1003), + .LO(plm_fsm_rl_timer_reg_count_cry[18]), + .S(plm_fsm_rl_timer_reg_count_qxu[18]) + ); + XORCY plm_fsm_rl_timer_reg_count_s_18_ ( + .CI(plm_fsm_rl_timer_reg_count_cry[17]), + .LI(plm_fsm_rl_timer_reg_count_qxu[18]), + .O(plm_fsm_rl_timer_reg_count_s[18]) + ); + MUXCY_L plm_fsm_rl_timer_reg_count_cry_19_ ( + .CI(plm_fsm_rl_timer_reg_count_cry[18]), + .DI(plm_fsm_rl_timer_GND_1003), + .LO(plm_fsm_rl_timer_reg_count_cry[19]), + .S(plm_fsm_rl_timer_reg_count_qxu[19]) + ); + XORCY plm_fsm_rl_timer_reg_count_s_19_ ( + .CI(plm_fsm_rl_timer_reg_count_cry[18]), + .LI(plm_fsm_rl_timer_reg_count_qxu[19]), + .O(plm_fsm_rl_timer_reg_count_s[19]) + ); + MUXCY_L plm_fsm_rl_timer_reg_count_cry_20_ ( + .CI(plm_fsm_rl_timer_reg_count_cry[19]), + .DI(plm_fsm_rl_timer_GND_1003), + .LO(plm_fsm_rl_timer_reg_count_cry[20]), + .S(plm_fsm_rl_timer_reg_count_qxu[20]) + ); + XORCY plm_fsm_rl_timer_reg_count_s_20_ ( + .CI(plm_fsm_rl_timer_reg_count_cry[19]), + .LI(plm_fsm_rl_timer_reg_count_qxu[20]), + .O(plm_fsm_rl_timer_reg_count_s[20]) + ); + MUXCY_L plm_fsm_rl_timer_reg_count_cry_21_ ( + .CI(plm_fsm_rl_timer_reg_count_cry[20]), + .DI(plm_fsm_rl_timer_GND_1003), + .LO(plm_fsm_rl_timer_reg_count_cry[21]), + .S(plm_fsm_rl_timer_reg_count_qxu[21]) + ); + XORCY plm_fsm_rl_timer_reg_count_s_21_ ( + .CI(plm_fsm_rl_timer_reg_count_cry[20]), + .LI(plm_fsm_rl_timer_reg_count_qxu[21]), + .O(plm_fsm_rl_timer_reg_count_s[21]) + ); + XORCY plm_fsm_rl_timer_reg_count_s_22_ ( + .CI(plm_fsm_rl_timer_reg_count_cry[21]), + .LI(plm_fsm_rl_timer_reg_count_qxu[22]), + .O(plm_fsm_rl_timer_reg_count_s[22]) + ); + defparam plm_fsm_rl_timer_count_i_m3_i_m3_0_20_.INIT = 8'hD8; + LUT3_L plm_fsm_rl_timer_count_i_m3_i_m3_0_20_ ( + .I0(cfg_cfg_5072[507]), + .I1(plm_fsm_rl_timer_reg_count[12]), + .I2(plm_fsm_rl_timer_reg_count[20]), + .LO(plm_fsm_rl_timer_N_51443) + ); + defparam plm_fsm_rl_timer_un3_expired_24ms_0_a2_0_a2_0_a4.INIT = 16'hA280; + LUT4_L plm_fsm_rl_timer_un3_expired_24ms_0_a2_0_a2_0_a4 ( + .I0(plm_fsm_rl_timer_N_51443), + .I1(cfg_cfg_5072[507]), + .I2(plm_fsm_rl_timer_reg_count[13]), + .I3(plm_fsm_rl_timer_reg_count[21]), + .LO(plm_fsm_rl_timer_N_51394) + ); + defparam plm_fsm_rl_timer_un1_expired_24ms_0_a2_0_a2_0_a4.INIT = 16'h0415; + LUT4 plm_fsm_rl_timer_un1_expired_24ms_0_a2_0_a2_0_a4 ( + .I0(plm_fsm_rl_timer_N_51394), + .I1(cfg_cfg_5072[507]), + .I2(plm_fsm_rl_timer_reg_count[14]), + .I3(plm_fsm_rl_timer_reg_count[22]), + .O(plm_fsm_N_51395) + ); + FDC plm_fsm_rl_timer_reg_count_22_ ( + .C(mgt_clk), + .D(plm_fsm_rl_timer_reg_count_s[22]), + .Q(plm_fsm_rl_timer_reg_count[22]), + .CLR(plm_rst) + ); + FDC plm_fsm_rl_timer_reg_count_21_ ( + .C(mgt_clk), + .D(plm_fsm_rl_timer_reg_count_s[21]), + .Q(plm_fsm_rl_timer_reg_count[21]), + .CLR(plm_rst) + ); + FDC plm_fsm_rl_timer_reg_count_20_ ( + .C(mgt_clk), + .D(plm_fsm_rl_timer_reg_count_s[20]), + .Q(plm_fsm_rl_timer_reg_count[20]), + .CLR(plm_rst) + ); + FDC plm_fsm_rl_timer_reg_count_19_ ( + .C(mgt_clk), + .D(plm_fsm_rl_timer_reg_count_s[19]), + .Q(plm_fsm_rl_timer_reg_count[19]), + .CLR(plm_rst) + ); + FDC plm_fsm_rl_timer_reg_count_18_ ( + .C(mgt_clk), + .D(plm_fsm_rl_timer_reg_count_s[18]), + .Q(plm_fsm_rl_timer_reg_count[18]), + .CLR(plm_rst) + ); + FDC plm_fsm_rl_timer_reg_count_17_ ( + .C(mgt_clk), + .D(plm_fsm_rl_timer_reg_count_s[17]), + .Q(plm_fsm_rl_timer_reg_count[17]), + .CLR(plm_rst) + ); + FDC plm_fsm_rl_timer_reg_count_16_ ( + .C(mgt_clk), + .D(plm_fsm_rl_timer_reg_count_s[16]), + .Q(plm_fsm_rl_timer_reg_count[16]), + .CLR(plm_rst) + ); + FDC plm_fsm_rl_timer_reg_count_15_ ( + .C(mgt_clk), + .D(plm_fsm_rl_timer_reg_count_s[15]), + .Q(plm_fsm_rl_timer_reg_count[15]), + .CLR(plm_rst) + ); + FDC plm_fsm_rl_timer_reg_count_14_ ( + .C(mgt_clk), + .D(plm_fsm_rl_timer_reg_count_s[14]), + .Q(plm_fsm_rl_timer_reg_count[14]), + .CLR(plm_rst) + ); + FDC plm_fsm_rl_timer_reg_count_13_ ( + .C(mgt_clk), + .D(plm_fsm_rl_timer_reg_count_s[13]), + .Q(plm_fsm_rl_timer_reg_count[13]), + .CLR(plm_rst) + ); + FDC plm_fsm_rl_timer_reg_count_12_ ( + .C(mgt_clk), + .D(plm_fsm_rl_timer_reg_count_s[12]), + .Q(plm_fsm_rl_timer_reg_count[12]), + .CLR(plm_rst) + ); + FDC plm_fsm_rl_timer_reg_count_11_ ( + .C(mgt_clk), + .D(plm_fsm_rl_timer_reg_count_s[11]), + .Q(plm_fsm_rl_timer_reg_count[11]), + .CLR(plm_rst) + ); + FDC plm_fsm_rl_timer_reg_count_10_ ( + .C(mgt_clk), + .D(plm_fsm_rl_timer_reg_count_s[10]), + .Q(plm_fsm_rl_timer_reg_count[10]), + .CLR(plm_rst) + ); + FDC plm_fsm_rl_timer_reg_count_9_ ( + .C(mgt_clk), + .D(plm_fsm_rl_timer_reg_count_s[9]), + .Q(plm_fsm_rl_timer_reg_count[9]), + .CLR(plm_rst) + ); + FDC plm_fsm_rl_timer_reg_count_8_ ( + .C(mgt_clk), + .D(plm_fsm_rl_timer_reg_count_s[8]), + .Q(plm_fsm_rl_timer_reg_count[8]), + .CLR(plm_rst) + ); + FDC plm_fsm_rl_timer_reg_count_7_ ( + .C(mgt_clk), + .D(plm_fsm_rl_timer_reg_count_s[7]), + .Q(plm_fsm_rl_timer_reg_count[7]), + .CLR(plm_rst) + ); + FDC plm_fsm_rl_timer_reg_count_6_ ( + .C(mgt_clk), + .D(plm_fsm_rl_timer_reg_count_s[6]), + .Q(plm_fsm_rl_timer_reg_count[6]), + .CLR(plm_rst) + ); + FDC plm_fsm_rl_timer_reg_count_5_ ( + .C(mgt_clk), + .D(plm_fsm_rl_timer_reg_count_s[5]), + .Q(plm_fsm_rl_timer_reg_count[5]), + .CLR(plm_rst) + ); + FDC plm_fsm_rl_timer_reg_count_4_ ( + .C(mgt_clk), + .D(plm_fsm_rl_timer_reg_count_s[4]), + .Q(plm_fsm_rl_timer_reg_count[4]), + .CLR(plm_rst) + ); + FDC plm_fsm_rl_timer_reg_count_3_ ( + .C(mgt_clk), + .D(plm_fsm_rl_timer_reg_count_s[3]), + .Q(plm_fsm_rl_timer_reg_count[3]), + .CLR(plm_rst) + ); + FDC plm_fsm_rl_timer_reg_count_2_ ( + .C(mgt_clk), + .D(plm_fsm_rl_timer_reg_count_s[2]), + .Q(plm_fsm_rl_timer_reg_count[2]), + .CLR(plm_rst) + ); + FDC plm_fsm_rl_timer_reg_count_1_ ( + .C(mgt_clk), + .D(plm_fsm_rl_timer_reg_count_s[1]), + .Q(plm_fsm_rl_timer_reg_count[1]), + .CLR(plm_rst) + ); + FDC plm_fsm_rl_timer_reg_count_0_ ( + .C(mgt_clk), + .D(plm_fsm_rl_timer_reg_count_s[0]), + .Q(plm_fsm_rl_timer_reg_count[0]), + .CLR(plm_rst) + ); + defparam plm_fsm_rl_timer_reg_count_qxu_0_0_.INIT = 4'h8; + LUT2_L plm_fsm_rl_timer_reg_count_qxu_0_0_ ( + .I0(plm_fsm_reg_state_13__41), + .I1(plm_fsm_rl_timer_reg_count[0]), + .LO(plm_fsm_rl_timer_reg_count_qxu[0]) + ); + defparam plm_fsm_rl_timer_reg_count_qxu_0_1_.INIT = 4'h8; + LUT2_L plm_fsm_rl_timer_reg_count_qxu_0_1_ ( + .I0(plm_fsm_reg_state_13__41), + .I1(plm_fsm_rl_timer_reg_count[1]), + .LO(plm_fsm_rl_timer_reg_count_qxu[1]) + ); + defparam plm_fsm_rl_timer_reg_count_qxu_0_2_.INIT = 4'h8; + LUT2_L plm_fsm_rl_timer_reg_count_qxu_0_2_ ( + .I0(plm_fsm_reg_state_13__41), + .I1(plm_fsm_rl_timer_reg_count[2]), + .LO(plm_fsm_rl_timer_reg_count_qxu[2]) + ); + defparam plm_fsm_rl_timer_reg_count_qxu_0_3_.INIT = 4'h8; + LUT2_L plm_fsm_rl_timer_reg_count_qxu_0_3_ ( + .I0(plm_fsm_reg_state_13__41), + .I1(plm_fsm_rl_timer_reg_count[3]), + .LO(plm_fsm_rl_timer_reg_count_qxu[3]) + ); + defparam plm_fsm_rl_timer_reg_count_qxu_0_4_.INIT = 4'h8; + LUT2_L plm_fsm_rl_timer_reg_count_qxu_0_4_ ( + .I0(plm_fsm_reg_state_13__41), + .I1(plm_fsm_rl_timer_reg_count[4]), + .LO(plm_fsm_rl_timer_reg_count_qxu[4]) + ); + defparam plm_fsm_rl_timer_reg_count_qxu_0_5_.INIT = 4'h8; + LUT2_L plm_fsm_rl_timer_reg_count_qxu_0_5_ ( + .I0(plm_fsm_reg_state_13__41), + .I1(plm_fsm_rl_timer_reg_count[5]), + .LO(plm_fsm_rl_timer_reg_count_qxu[5]) + ); + defparam plm_fsm_rl_timer_reg_count_qxu_0_6_.INIT = 4'h8; + LUT2_L plm_fsm_rl_timer_reg_count_qxu_0_6_ ( + .I0(plm_fsm_reg_state_13__41), + .I1(plm_fsm_rl_timer_reg_count[6]), + .LO(plm_fsm_rl_timer_reg_count_qxu[6]) + ); + defparam plm_fsm_rl_timer_reg_count_qxu_0_7_.INIT = 4'h8; + LUT2_L plm_fsm_rl_timer_reg_count_qxu_0_7_ ( + .I0(plm_fsm_reg_state_13__41), + .I1(plm_fsm_rl_timer_reg_count[7]), + .LO(plm_fsm_rl_timer_reg_count_qxu[7]) + ); + defparam plm_fsm_rl_timer_reg_count_qxu_0_8_.INIT = 4'h8; + LUT2_L plm_fsm_rl_timer_reg_count_qxu_0_8_ ( + .I0(plm_fsm_reg_state_13__41), + .I1(plm_fsm_rl_timer_reg_count[8]), + .LO(plm_fsm_rl_timer_reg_count_qxu[8]) + ); + defparam plm_fsm_rl_timer_reg_count_qxu_0_9_.INIT = 4'h8; + LUT2_L plm_fsm_rl_timer_reg_count_qxu_0_9_ ( + .I0(plm_fsm_reg_state_13__41), + .I1(plm_fsm_rl_timer_reg_count[9]), + .LO(plm_fsm_rl_timer_reg_count_qxu[9]) + ); + defparam plm_fsm_rl_timer_reg_count_qxu_0_10_.INIT = 4'h8; + LUT2_L plm_fsm_rl_timer_reg_count_qxu_0_10_ ( + .I0(plm_fsm_reg_state_13__41), + .I1(plm_fsm_rl_timer_reg_count[10]), + .LO(plm_fsm_rl_timer_reg_count_qxu[10]) + ); + defparam plm_fsm_rl_timer_reg_count_qxu_0_11_.INIT = 4'h8; + LUT2_L plm_fsm_rl_timer_reg_count_qxu_0_11_ ( + .I0(plm_fsm_reg_state_13__41), + .I1(plm_fsm_rl_timer_reg_count[11]), + .LO(plm_fsm_rl_timer_reg_count_qxu[11]) + ); + defparam plm_fsm_rl_timer_reg_count_qxu_0_12_.INIT = 4'h8; + LUT2_L plm_fsm_rl_timer_reg_count_qxu_0_12_ ( + .I0(plm_fsm_reg_state_13__41), + .I1(plm_fsm_rl_timer_reg_count[12]), + .LO(plm_fsm_rl_timer_reg_count_qxu[12]) + ); + defparam plm_fsm_rl_timer_reg_count_qxu_0_13_.INIT = 4'h8; + LUT2_L plm_fsm_rl_timer_reg_count_qxu_0_13_ ( + .I0(plm_fsm_reg_state_13__41), + .I1(plm_fsm_rl_timer_reg_count[13]), + .LO(plm_fsm_rl_timer_reg_count_qxu[13]) + ); + defparam plm_fsm_rl_timer_reg_count_qxu_0_14_.INIT = 4'h8; + LUT2_L plm_fsm_rl_timer_reg_count_qxu_0_14_ ( + .I0(plm_fsm_reg_state_13__41), + .I1(plm_fsm_rl_timer_reg_count[14]), + .LO(plm_fsm_rl_timer_reg_count_qxu[14]) + ); + defparam plm_fsm_rl_timer_reg_count_qxu_0_15_.INIT = 4'h8; + LUT2_L plm_fsm_rl_timer_reg_count_qxu_0_15_ ( + .I0(plm_fsm_reg_state_13__41), + .I1(plm_fsm_rl_timer_reg_count[15]), + .LO(plm_fsm_rl_timer_reg_count_qxu[15]) + ); + defparam plm_fsm_rl_timer_reg_count_qxu_0_16_.INIT = 4'h8; + LUT2_L plm_fsm_rl_timer_reg_count_qxu_0_16_ ( + .I0(plm_fsm_reg_state_13__41), + .I1(plm_fsm_rl_timer_reg_count[16]), + .LO(plm_fsm_rl_timer_reg_count_qxu[16]) + ); + defparam plm_fsm_rl_timer_reg_count_qxu_0_17_.INIT = 4'h8; + LUT2_L plm_fsm_rl_timer_reg_count_qxu_0_17_ ( + .I0(plm_fsm_reg_state_13__41), + .I1(plm_fsm_rl_timer_reg_count[17]), + .LO(plm_fsm_rl_timer_reg_count_qxu[17]) + ); + defparam plm_fsm_rl_timer_reg_count_qxu_0_18_.INIT = 4'h8; + LUT2_L plm_fsm_rl_timer_reg_count_qxu_0_18_ ( + .I0(plm_fsm_reg_state_13__41), + .I1(plm_fsm_rl_timer_reg_count[18]), + .LO(plm_fsm_rl_timer_reg_count_qxu[18]) + ); + defparam plm_fsm_rl_timer_reg_count_qxu_0_19_.INIT = 4'h8; + LUT2_L plm_fsm_rl_timer_reg_count_qxu_0_19_ ( + .I0(plm_fsm_reg_state_13__41), + .I1(plm_fsm_rl_timer_reg_count[19]), + .LO(plm_fsm_rl_timer_reg_count_qxu[19]) + ); + defparam plm_fsm_rl_timer_reg_count_qxu_0_20_.INIT = 4'h8; + LUT2_L plm_fsm_rl_timer_reg_count_qxu_0_20_ ( + .I0(plm_fsm_reg_state_13__41), + .I1(plm_fsm_rl_timer_reg_count[20]), + .LO(plm_fsm_rl_timer_reg_count_qxu[20]) + ); + defparam plm_fsm_rl_timer_reg_count_qxu_0_21_.INIT = 4'h8; + LUT2_L plm_fsm_rl_timer_reg_count_qxu_0_21_ ( + .I0(plm_fsm_reg_state_13__41), + .I1(plm_fsm_rl_timer_reg_count[21]), + .LO(plm_fsm_rl_timer_reg_count_qxu[21]) + ); + defparam plm_fsm_rl_timer_reg_count_qxu_0_22_.INIT = 4'h8; + LUT2_L plm_fsm_rl_timer_reg_count_qxu_0_22_ ( + .I0(plm_fsm_reg_state_13__41), + .I1(plm_fsm_rl_timer_reg_count[22]), + .LO(plm_fsm_rl_timer_reg_count_qxu[22]) + ); + VCC plm_fsm_rl_counterx_VCC ( + .P(plm_fsm_rl_counterx_VCC_1004) + ); + MUXCY_L plm_fsm_rl_counterx_reg_rx_count_cry_0_ ( + .CI(plm_fsm_rl_counterx_N_38586_i), + .DI(plm_fsm_rl_counterx_VCC_1004), + .LO(plm_fsm_rl_counterx_reg_rx_count_cry[0]), + .S(plm_fsm_rl_counterx_reg_rx_count_qxu[0]) + ); + XORCY plm_fsm_rl_counterx_reg_rx_count_s_0_ ( + .CI(plm_fsm_rl_counterx_N_38586_i), + .LI(plm_fsm_rl_counterx_reg_rx_count_qxu[0]), + .O(plm_fsm_rl_counterx_reg_rx_count_s[0]) + ); + MUXCY_L plm_fsm_rl_counterx_reg_rx_count_cry_1_ ( + .CI(plm_fsm_rl_counterx_reg_rx_count_cry[0]), + .DI(plm_fsm_rl_counterx_VCC_1004), + .LO(plm_fsm_rl_counterx_reg_rx_count_cry[1]), + .S(plm_fsm_rl_counterx_reg_rx_count_qxu[1]) + ); + XORCY plm_fsm_rl_counterx_reg_rx_count_s_1_ ( + .CI(plm_fsm_rl_counterx_reg_rx_count_cry[0]), + .LI(plm_fsm_rl_counterx_reg_rx_count_qxu[1]), + .O(plm_fsm_rl_counterx_reg_rx_count_s[1]) + ); + MUXCY_L plm_fsm_rl_counterx_reg_rx_count_cry_2_ ( + .CI(plm_fsm_rl_counterx_reg_rx_count_cry[1]), + .DI(plm_fsm_rl_counterx_VCC_1004), + .LO(plm_fsm_rl_counterx_reg_rx_count_cry[2]), + .S(plm_fsm_rl_counterx_reg_rx_count_qxu[2]) + ); + XORCY plm_fsm_rl_counterx_reg_rx_count_s_2_ ( + .CI(plm_fsm_rl_counterx_reg_rx_count_cry[1]), + .LI(plm_fsm_rl_counterx_reg_rx_count_qxu[2]), + .O(plm_fsm_rl_counterx_reg_rx_count_s[2]) + ); + MUXCY_L plm_fsm_rl_counterx_reg_rx_count_cry_3_ ( + .CI(plm_fsm_rl_counterx_reg_rx_count_cry[2]), + .DI(plm_fsm_rl_counterx_VCC_1004), + .LO(plm_fsm_rl_counterx_reg_rx_count_cry[3]), + .S(plm_fsm_rl_counterx_reg_rx_count_qxu[3]) + ); + XORCY plm_fsm_rl_counterx_reg_rx_count_s_3_ ( + .CI(plm_fsm_rl_counterx_reg_rx_count_cry[2]), + .LI(plm_fsm_rl_counterx_reg_rx_count_qxu[3]), + .O(plm_fsm_rl_counterx_reg_rx_count_s[3]) + ); + MUXCY_L plm_fsm_rl_counterx_reg_rx_count_cry_4_ ( + .CI(plm_fsm_rl_counterx_reg_rx_count_cry[3]), + .DI(plm_fsm_rl_counterx_VCC_1004), + .LO(plm_fsm_rl_counterx_reg_rx_count_cry[4]), + .S(plm_fsm_rl_counterx_reg_rx_count_qxu[4]) + ); + XORCY plm_fsm_rl_counterx_reg_rx_count_s_4_ ( + .CI(plm_fsm_rl_counterx_reg_rx_count_cry[3]), + .LI(plm_fsm_rl_counterx_reg_rx_count_qxu[4]), + .O(plm_fsm_rl_counterx_reg_rx_count_s[4]) + ); + MUXCY_L plm_fsm_rl_counterx_reg_rx_count_cry_5_ ( + .CI(plm_fsm_rl_counterx_reg_rx_count_cry[4]), + .DI(plm_fsm_rl_counterx_VCC_1004), + .LO(plm_fsm_rl_counterx_reg_rx_count_cry[5]), + .S(plm_fsm_rl_counterx_reg_rx_count_qxu[5]) + ); + XORCY plm_fsm_rl_counterx_reg_rx_count_s_5_ ( + .CI(plm_fsm_rl_counterx_reg_rx_count_cry[4]), + .LI(plm_fsm_rl_counterx_reg_rx_count_qxu[5]), + .O(plm_fsm_rl_counterx_reg_rx_count_s[5]) + ); + MUXCY_L plm_fsm_rl_counterx_reg_rx_count_cry_6_ ( + .CI(plm_fsm_rl_counterx_reg_rx_count_cry[5]), + .DI(plm_fsm_rl_counterx_VCC_1004), + .LO(plm_fsm_rl_counterx_reg_rx_count_cry[6]), + .S(plm_fsm_rl_counterx_reg_rx_count_qxu[6]) + ); + XORCY plm_fsm_rl_counterx_reg_rx_count_s_6_ ( + .CI(plm_fsm_rl_counterx_reg_rx_count_cry[5]), + .LI(plm_fsm_rl_counterx_reg_rx_count_qxu[6]), + .O(plm_fsm_rl_counterx_reg_rx_count_s[6]) + ); + XORCY plm_fsm_rl_counterx_reg_rx_count_s_7_ ( + .CI(plm_fsm_rl_counterx_reg_rx_count_cry[6]), + .LI(plm_fsm_rl_counterx_reg_rx_count_qxu[7]), + .O(plm_fsm_rl_counterx_reg_rx_count_s[7]) + ); + MUXCY_L plm_fsm_rl_counterx_reg_tx_count_cry_0_ ( + .CI(plm_fsm_rl_counterx_un1_enable_1_i_1008), + .DI(plm_fsm_rl_counterx_VCC_1004), + .LO(plm_fsm_rl_counterx_reg_tx_count_cry[0]), + .S(plm_fsm_rl_counterx_reg_tx_count_qxu[0]) + ); + XORCY plm_fsm_rl_counterx_reg_tx_count_s_0_ ( + .CI(plm_fsm_rl_counterx_un1_enable_1_i_1008), + .LI(plm_fsm_rl_counterx_reg_tx_count_qxu[0]), + .O(plm_fsm_rl_counterx_reg_tx_count_s[0]) + ); + MUXCY_L plm_fsm_rl_counterx_reg_tx_count_cry_1_ ( + .CI(plm_fsm_rl_counterx_reg_tx_count_cry[0]), + .DI(plm_fsm_rl_counterx_VCC_1004), + .LO(plm_fsm_rl_counterx_reg_tx_count_cry[1]), + .S(plm_fsm_rl_counterx_reg_tx_count_qxu[1]) + ); + XORCY plm_fsm_rl_counterx_reg_tx_count_s_1_ ( + .CI(plm_fsm_rl_counterx_reg_tx_count_cry[0]), + .LI(plm_fsm_rl_counterx_reg_tx_count_qxu[1]), + .O(plm_fsm_rl_counterx_reg_tx_count_s[1]) + ); + MUXCY_L plm_fsm_rl_counterx_reg_tx_count_cry_2_ ( + .CI(plm_fsm_rl_counterx_reg_tx_count_cry[1]), + .DI(plm_fsm_rl_counterx_VCC_1004), + .LO(plm_fsm_rl_counterx_reg_tx_count_cry[2]), + .S(plm_fsm_rl_counterx_reg_tx_count_qxu[2]) + ); + XORCY plm_fsm_rl_counterx_reg_tx_count_s_2_ ( + .CI(plm_fsm_rl_counterx_reg_tx_count_cry[1]), + .LI(plm_fsm_rl_counterx_reg_tx_count_qxu[2]), + .O(plm_fsm_rl_counterx_reg_tx_count_s[2]) + ); + MUXCY_L plm_fsm_rl_counterx_reg_tx_count_cry_3_ ( + .CI(plm_fsm_rl_counterx_reg_tx_count_cry[2]), + .DI(plm_fsm_rl_counterx_VCC_1004), + .LO(plm_fsm_rl_counterx_reg_tx_count_cry[3]), + .S(plm_fsm_rl_counterx_reg_tx_count_qxu[3]) + ); + XORCY plm_fsm_rl_counterx_reg_tx_count_s_3_ ( + .CI(plm_fsm_rl_counterx_reg_tx_count_cry[2]), + .LI(plm_fsm_rl_counterx_reg_tx_count_qxu[3]), + .O(plm_fsm_rl_counterx_reg_tx_count_s[3]) + ); + MUXCY_L plm_fsm_rl_counterx_reg_tx_count_cry_4_ ( + .CI(plm_fsm_rl_counterx_reg_tx_count_cry[3]), + .DI(plm_fsm_rl_counterx_VCC_1004), + .LO(plm_fsm_rl_counterx_reg_tx_count_cry[4]), + .S(plm_fsm_rl_counterx_reg_tx_count_qxu[4]) + ); + XORCY plm_fsm_rl_counterx_reg_tx_count_s_4_ ( + .CI(plm_fsm_rl_counterx_reg_tx_count_cry[3]), + .LI(plm_fsm_rl_counterx_reg_tx_count_qxu[4]), + .O(plm_fsm_rl_counterx_reg_tx_count_s[4]) + ); + MUXCY_L plm_fsm_rl_counterx_reg_tx_count_cry_5_ ( + .CI(plm_fsm_rl_counterx_reg_tx_count_cry[4]), + .DI(plm_fsm_rl_counterx_VCC_1004), + .LO(plm_fsm_rl_counterx_reg_tx_count_cry[5]), + .S(plm_fsm_rl_counterx_reg_tx_count_qxu[5]) + ); + XORCY plm_fsm_rl_counterx_reg_tx_count_s_5_ ( + .CI(plm_fsm_rl_counterx_reg_tx_count_cry[4]), + .LI(plm_fsm_rl_counterx_reg_tx_count_qxu[5]), + .O(plm_fsm_rl_counterx_reg_tx_count_s[5]) + ); + MUXCY_L plm_fsm_rl_counterx_reg_tx_count_cry_6_ ( + .CI(plm_fsm_rl_counterx_reg_tx_count_cry[5]), + .DI(plm_fsm_rl_counterx_VCC_1004), + .LO(plm_fsm_rl_counterx_reg_tx_count_cry[6]), + .S(plm_fsm_rl_counterx_reg_tx_count_qxu[6]) + ); + XORCY plm_fsm_rl_counterx_reg_tx_count_s_6_ ( + .CI(plm_fsm_rl_counterx_reg_tx_count_cry[5]), + .LI(plm_fsm_rl_counterx_reg_tx_count_qxu[6]), + .O(plm_fsm_rl_counterx_reg_tx_count_s[6]) + ); + MUXCY_L plm_fsm_rl_counterx_reg_tx_count_cry_7_ ( + .CI(plm_fsm_rl_counterx_reg_tx_count_cry[6]), + .DI(plm_fsm_rl_counterx_VCC_1004), + .LO(plm_fsm_rl_counterx_reg_tx_count_cry[7]), + .S(plm_fsm_rl_counterx_reg_tx_count_qxu[7]) + ); + XORCY plm_fsm_rl_counterx_reg_tx_count_s_7_ ( + .CI(plm_fsm_rl_counterx_reg_tx_count_cry[6]), + .LI(plm_fsm_rl_counterx_reg_tx_count_qxu[7]), + .O(plm_fsm_rl_counterx_reg_tx_count_s[7]) + ); + MUXCY_L plm_fsm_rl_counterx_reg_tx_count_cry_8_ ( + .CI(plm_fsm_rl_counterx_reg_tx_count_cry[7]), + .DI(plm_fsm_rl_counterx_VCC_1004), + .LO(plm_fsm_rl_counterx_reg_tx_count_cry[8]), + .S(plm_fsm_rl_counterx_reg_tx_count_qxu[8]) + ); + XORCY plm_fsm_rl_counterx_reg_tx_count_s_8_ ( + .CI(plm_fsm_rl_counterx_reg_tx_count_cry[7]), + .LI(plm_fsm_rl_counterx_reg_tx_count_qxu[8]), + .O(plm_fsm_rl_counterx_reg_tx_count_s[8]) + ); + MUXCY_L plm_fsm_rl_counterx_reg_tx_count_cry_9_ ( + .CI(plm_fsm_rl_counterx_reg_tx_count_cry[8]), + .DI(plm_fsm_rl_counterx_VCC_1004), + .LO(plm_fsm_rl_counterx_reg_tx_count_cry[9]), + .S(plm_fsm_rl_counterx_reg_tx_count_qxu[9]) + ); + XORCY plm_fsm_rl_counterx_reg_tx_count_s_9_ ( + .CI(plm_fsm_rl_counterx_reg_tx_count_cry[8]), + .LI(plm_fsm_rl_counterx_reg_tx_count_qxu[9]), + .O(plm_fsm_rl_counterx_reg_tx_count_s[9]) + ); + MUXCY_L plm_fsm_rl_counterx_reg_tx_count_cry_10_ ( + .CI(plm_fsm_rl_counterx_reg_tx_count_cry[9]), + .DI(plm_fsm_rl_counterx_VCC_1004), + .LO(plm_fsm_rl_counterx_reg_tx_count_cry[10]), + .S(plm_fsm_rl_counterx_reg_tx_count_qxu[10]) + ); + XORCY plm_fsm_rl_counterx_reg_tx_count_s_10_ ( + .CI(plm_fsm_rl_counterx_reg_tx_count_cry[9]), + .LI(plm_fsm_rl_counterx_reg_tx_count_qxu[10]), + .O(plm_fsm_rl_counterx_reg_tx_count_s[10]) + ); + XORCY plm_fsm_rl_counterx_reg_tx_count_s_11_ ( + .CI(plm_fsm_rl_counterx_reg_tx_count_cry[10]), + .LI(plm_fsm_rl_counterx_reg_tx_count_qxu[11]), + .O(plm_fsm_rl_counterx_reg_tx_count_s[11]) + ); + defparam plm_fsm_rl_counterx_un1_enable_1_0_a2_0_a4.INIT = 4'h2; + LUT2 plm_fsm_rl_counterx_un1_enable_1_0_a2_0_a4 ( + .I0(plm_fsm_reg_state_13__41), + .I1(plm_fsm_rl_counterx_reg_tx_expired_1006), + .O(plm_fsm_rl_counterx_un1_enable_1) + ); + defparam plm_fsm_rl_counterx_loadable_rx_counter_un1_reg_rx_expired_0_a2_0_a2_0_a4.INIT = 4'h2; + LUT2 plm_fsm_rl_counterx_loadable_rx_counter_un1_reg_rx_expired_0_a2_0_a2_0_a4 ( + .I0(plm_fsm_reg_state_13__41), + .I1(plm_fsm_rl_counterx_reg_rx_expired_1007), + .O(plm_fsm_rl_counterx_un1_reg_rx_expired_0_a2_0_a2_0_a4) + ); + defparam plm_fsm_rl_counterx_loadable_rx_counter_un1_reg_rx_count_0_a2_4.INIT = 16'h0001; + LUT4 plm_fsm_rl_counterx_loadable_rx_counter_un1_reg_rx_count_0_a2_4 ( + .I0(plm_fsm_rl_counterx_reg_rx_count[0]), + .I1(plm_fsm_rl_counterx_reg_rx_count[1]), + .I2(plm_fsm_rl_counterx_reg_rx_count[2]), + .I3(plm_fsm_rl_counterx_reg_rx_count[3]), + .O(plm_fsm_rl_counterx_un1_reg_rx_count_0_a2_4) + ); + defparam plm_fsm_rl_counterx_loadable_rx_counter_un1_reg_rx_count_0_a2_5.INIT = 16'h0001; + LUT4 plm_fsm_rl_counterx_loadable_rx_counter_un1_reg_rx_count_0_a2_5 ( + .I0(plm_fsm_rl_counterx_reg_rx_count[4]), + .I1(plm_fsm_rl_counterx_reg_rx_count[5]), + .I2(plm_fsm_rl_counterx_reg_rx_count[6]), + .I3(plm_fsm_rl_counterx_reg_rx_count[7]), + .O(plm_fsm_rl_counterx_un1_reg_rx_count_0_a2_5) + ); + defparam plm_fsm_rl_counterx_loadable_tx_counter_un1_reg_tx_count_6.INIT = 16'h0001; + LUT4 plm_fsm_rl_counterx_loadable_tx_counter_un1_reg_tx_count_6 ( + .I0(plm_fsm_rl_counterx_reg_tx_count[0]), + .I1(plm_fsm_rl_counterx_reg_tx_count[1]), + .I2(plm_fsm_rl_counterx_reg_tx_count[2]), + .I3(plm_fsm_rl_counterx_reg_tx_count[3]), + .O(plm_fsm_rl_counterx_un1_reg_tx_count_6) + ); + defparam plm_fsm_rl_counterx_loadable_tx_counter_un1_reg_tx_count_7.INIT = 16'h0001; + LUT4 plm_fsm_rl_counterx_loadable_tx_counter_un1_reg_tx_count_7 ( + .I0(plm_fsm_rl_counterx_reg_tx_count[4]), + .I1(plm_fsm_rl_counterx_reg_tx_count[5]), + .I2(plm_fsm_rl_counterx_reg_tx_count[6]), + .I3(plm_fsm_rl_counterx_reg_tx_count[7]), + .O(plm_fsm_rl_counterx_un1_reg_tx_count_7) + ); + defparam plm_fsm_rl_counterx_loadable_tx_counter_un1_reg_tx_count_8.INIT = 16'h0001; + LUT4 plm_fsm_rl_counterx_loadable_tx_counter_un1_reg_tx_count_8 ( + .I0(plm_fsm_rl_counterx_reg_tx_count[8]), + .I1(plm_fsm_rl_counterx_reg_tx_count[9]), + .I2(plm_fsm_rl_counterx_reg_tx_count[10]), + .I3(plm_fsm_rl_counterx_reg_tx_count[11]), + .O(plm_fsm_rl_counterx_un1_reg_tx_count_8) + ); + defparam plm_fsm_rl_counterx_N_38536_i.INIT = 4'hB; + LUT2 plm_fsm_rl_counterx_N_38536_i ( + .I0(plm_reg_sym_sent_5_), + .I1(plm_fsm_rl_counterx_un1_enable_1), + .O(plm_fsm_rl_counterx_N_38536_i_1005) + ); + defparam plm_fsm_rl_counterx_loadable_rx_counter_N_38565_i.INIT = 8'hD5; + LUT3 plm_fsm_rl_counterx_loadable_rx_counter_N_38565_i ( + .I0(plm_fsm_reg_state_13__41), + .I1(plm_fsm_rl_counterx_un1_reg_rx_count_0_a2_4), + .I2(plm_fsm_rl_counterx_un1_reg_rx_count_0_a2_5), + .O(plm_fsm_rl_counterx_N_38565_i) + ); + defparam plm_fsm_rl_counterx_loadable_tx_counter_N_9900_i.INIT = 16'hD555; + LUT4 plm_fsm_rl_counterx_loadable_tx_counter_N_9900_i ( + .I0(plm_fsm_reg_state_13__41), + .I1(plm_fsm_rl_counterx_un1_reg_tx_count_6), + .I2(plm_fsm_rl_counterx_un1_reg_tx_count_7), + .I3(plm_fsm_rl_counterx_un1_reg_tx_count_8), + .O(plm_fsm_rl_counterx_N_9900_i) + ); + defparam plm_fsm_rl_counterx_flagit_reg_expired_5_0_a2_0_a2_0_a4.INIT = 8'h80; + LUT3_L plm_fsm_rl_counterx_flagit_reg_expired_5_0_a2_0_a2_0_a4 ( + .I0(plm_fsm_reg_state_13__41), + .I1(plm_fsm_rl_counterx_reg_rx_expired_1007), + .I2(plm_fsm_rl_counterx_reg_tx_expired_1006), + .LO(plm_fsm_rl_counterx_reg_expired_5) + ); + FDCE plm_fsm_rl_counterx_reg_tx_count_11_ ( + .CE(plm_fsm_rl_counterx_N_38536_i_1005), + .C(mgt_clk), + .D(plm_fsm_rl_counterx_reg_tx_count_s[11]), + .Q(plm_fsm_rl_counterx_reg_tx_count[11]), + .CLR(plm_rst) + ); + FDCE plm_fsm_rl_counterx_reg_tx_count_10_ ( + .CE(plm_fsm_rl_counterx_N_38536_i_1005), + .C(mgt_clk), + .D(plm_fsm_rl_counterx_reg_tx_count_s[10]), + .Q(plm_fsm_rl_counterx_reg_tx_count[10]), + .CLR(plm_rst) + ); + FDCE plm_fsm_rl_counterx_reg_tx_count_9_ ( + .CE(plm_fsm_rl_counterx_N_38536_i_1005), + .C(mgt_clk), + .D(plm_fsm_rl_counterx_reg_tx_count_s[9]), + .Q(plm_fsm_rl_counterx_reg_tx_count[9]), + .CLR(plm_rst) + ); + FDCE plm_fsm_rl_counterx_reg_tx_count_8_ ( + .CE(plm_fsm_rl_counterx_N_38536_i_1005), + .C(mgt_clk), + .D(plm_fsm_rl_counterx_reg_tx_count_s[8]), + .Q(plm_fsm_rl_counterx_reg_tx_count[8]), + .CLR(plm_rst) + ); + FDCE plm_fsm_rl_counterx_reg_tx_count_7_ ( + .CE(plm_fsm_rl_counterx_N_38536_i_1005), + .C(mgt_clk), + .D(plm_fsm_rl_counterx_reg_tx_count_s[7]), + .Q(plm_fsm_rl_counterx_reg_tx_count[7]), + .CLR(plm_rst) + ); + FDCE plm_fsm_rl_counterx_reg_tx_count_6_ ( + .CE(plm_fsm_rl_counterx_N_38536_i_1005), + .C(mgt_clk), + .D(plm_fsm_rl_counterx_reg_tx_count_s[6]), + .Q(plm_fsm_rl_counterx_reg_tx_count[6]), + .CLR(plm_rst) + ); + FDCE plm_fsm_rl_counterx_reg_tx_count_5_ ( + .CE(plm_fsm_rl_counterx_N_38536_i_1005), + .C(mgt_clk), + .D(plm_fsm_rl_counterx_reg_tx_count_s[5]), + .Q(plm_fsm_rl_counterx_reg_tx_count[5]), + .CLR(plm_rst) + ); + FDCE plm_fsm_rl_counterx_reg_tx_count_4_ ( + .CE(plm_fsm_rl_counterx_N_38536_i_1005), + .C(mgt_clk), + .D(plm_fsm_rl_counterx_reg_tx_count_s[4]), + .Q(plm_fsm_rl_counterx_reg_tx_count[4]), + .CLR(plm_rst) + ); + FDCE plm_fsm_rl_counterx_reg_tx_count_3_ ( + .CE(plm_fsm_rl_counterx_N_38536_i_1005), + .C(mgt_clk), + .D(plm_fsm_rl_counterx_reg_tx_count_s[3]), + .Q(plm_fsm_rl_counterx_reg_tx_count[3]), + .CLR(plm_rst) + ); + FDCE plm_fsm_rl_counterx_reg_tx_count_2_ ( + .CE(plm_fsm_rl_counterx_N_38536_i_1005), + .C(mgt_clk), + .D(plm_fsm_rl_counterx_reg_tx_count_s[2]), + .Q(plm_fsm_rl_counterx_reg_tx_count[2]), + .CLR(plm_rst) + ); + FDCE plm_fsm_rl_counterx_reg_tx_count_1_ ( + .CE(plm_fsm_rl_counterx_N_38536_i_1005), + .C(mgt_clk), + .D(plm_fsm_rl_counterx_reg_tx_count_s[1]), + .Q(plm_fsm_rl_counterx_reg_tx_count[1]), + .CLR(plm_rst) + ); + FDCE plm_fsm_rl_counterx_reg_tx_count_0_ ( + .CE(plm_fsm_rl_counterx_N_38536_i_1005), + .C(mgt_clk), + .D(plm_fsm_rl_counterx_reg_tx_count_s[0]), + .Q(plm_fsm_rl_counterx_reg_tx_count[0]), + .CLR(plm_rst) + ); + FDC plm_fsm_rl_counterx_reg_rx_count_7_ ( + .C(mgt_clk), + .D(plm_fsm_rl_counterx_reg_rx_count_s[7]), + .Q(plm_fsm_rl_counterx_reg_rx_count[7]), + .CLR(plm_rst) + ); + FDC plm_fsm_rl_counterx_reg_rx_count_6_ ( + .C(mgt_clk), + .D(plm_fsm_rl_counterx_reg_rx_count_s[6]), + .Q(plm_fsm_rl_counterx_reg_rx_count[6]), + .CLR(plm_rst) + ); + FDC plm_fsm_rl_counterx_reg_rx_count_5_ ( + .C(mgt_clk), + .D(plm_fsm_rl_counterx_reg_rx_count_s[5]), + .Q(plm_fsm_rl_counterx_reg_rx_count[5]), + .CLR(plm_rst) + ); + FDC plm_fsm_rl_counterx_reg_rx_count_4_ ( + .C(mgt_clk), + .D(plm_fsm_rl_counterx_reg_rx_count_s[4]), + .Q(plm_fsm_rl_counterx_reg_rx_count[4]), + .CLR(plm_rst) + ); + FDC plm_fsm_rl_counterx_reg_rx_count_3_ ( + .C(mgt_clk), + .D(plm_fsm_rl_counterx_reg_rx_count_s[3]), + .Q(plm_fsm_rl_counterx_reg_rx_count[3]), + .CLR(plm_rst) + ); + FDC plm_fsm_rl_counterx_reg_rx_count_2_ ( + .C(mgt_clk), + .D(plm_fsm_rl_counterx_reg_rx_count_s[2]), + .Q(plm_fsm_rl_counterx_reg_rx_count[2]), + .CLR(plm_rst) + ); + FDC plm_fsm_rl_counterx_reg_rx_count_1_ ( + .C(mgt_clk), + .D(plm_fsm_rl_counterx_reg_rx_count_s[1]), + .Q(plm_fsm_rl_counterx_reg_rx_count[1]), + .CLR(plm_rst) + ); + FDC plm_fsm_rl_counterx_reg_rx_count_0_ ( + .C(mgt_clk), + .D(plm_fsm_rl_counterx_reg_rx_count_s[0]), + .Q(plm_fsm_rl_counterx_reg_rx_count[0]), + .CLR(plm_rst) + ); + FDC plm_fsm_rl_counterx_reg_expired ( + .C(mgt_clk), + .D(plm_fsm_rl_counterx_reg_expired_5), + .Q(plm_fsm_rl_extdout), + .CLR(plm_rst) + ); + FDCE plm_fsm_rl_counterx_reg_tx_expired ( + .CE(plm_fsm_rl_counterx_N_9900_i), + .C(mgt_clk), + .D(plm_fsm_reg_state_13__41), + .Q(plm_fsm_rl_counterx_reg_tx_expired_1006), + .CLR(plm_rst) + ); + FDCE plm_fsm_rl_counterx_reg_rx_expired ( + .CE(plm_fsm_rl_counterx_N_38565_i), + .C(mgt_clk), + .D(plm_fsm_reg_state_13__41), + .Q(plm_fsm_rl_counterx_reg_rx_expired_1007), + .CLR(plm_rst) + ); + INV plm_fsm_rl_counterx_loadable_rx_counter_N_38586_i ( + .I(plm_fsm_rl_counterx_un1_reg_rx_expired_0_a2_0_a2_0_a4), + .O(plm_fsm_rl_counterx_N_38586_i) + ); + INV plm_fsm_rl_counterx_un1_enable_1_i ( + .I(plm_fsm_rl_counterx_un1_enable_1), + .O(plm_fsm_rl_counterx_un1_enable_1_i_1008) + ); + defparam plm_fsm_rl_counterx_reg_rx_count_qxu_0_0_.INIT = 4'h7; + LUT2_L plm_fsm_rl_counterx_reg_rx_count_qxu_0_0_ ( + .I0(plm_fsm_rl_counterx_un1_reg_rx_expired_0_a2_0_a2_0_a4), + .I1(plm_fsm_rl_counterx_reg_rx_count[0]), + .LO(plm_fsm_rl_counterx_reg_rx_count_qxu[0]) + ); + defparam plm_fsm_rl_counterx_reg_rx_count_qxu_0_1_.INIT = 4'h7; + LUT2_L plm_fsm_rl_counterx_reg_rx_count_qxu_0_1_ ( + .I0(plm_fsm_rl_counterx_un1_reg_rx_expired_0_a2_0_a2_0_a4), + .I1(plm_fsm_rl_counterx_reg_rx_count[1]), + .LO(plm_fsm_rl_counterx_reg_rx_count_qxu[1]) + ); + defparam plm_fsm_rl_counterx_reg_rx_count_qxu_0_2_.INIT = 4'h7; + LUT2_L plm_fsm_rl_counterx_reg_rx_count_qxu_0_2_ ( + .I0(plm_fsm_rl_counterx_un1_reg_rx_expired_0_a2_0_a2_0_a4), + .I1(plm_fsm_rl_counterx_reg_rx_count[2]), + .LO(plm_fsm_rl_counterx_reg_rx_count_qxu[2]) + ); + defparam plm_fsm_rl_counterx_reg_rx_count_qxu_0_3_.INIT = 8'h4E; + LUT3_L plm_fsm_rl_counterx_reg_rx_count_qxu_0_3_ ( + .I0(plm_fsm_rl_counterx_un1_reg_rx_expired_0_a2_0_a2_0_a4), + .I1(plm_fsm_reg_state_13__41), + .I2(plm_fsm_rl_counterx_reg_rx_count[3]), + .LO(plm_fsm_rl_counterx_reg_rx_count_qxu[3]) + ); + defparam plm_fsm_rl_counterx_reg_rx_count_qxu_0_4_.INIT = 4'h7; + LUT2_L plm_fsm_rl_counterx_reg_rx_count_qxu_0_4_ ( + .I0(plm_fsm_rl_counterx_un1_reg_rx_expired_0_a2_0_a2_0_a4), + .I1(plm_fsm_rl_counterx_reg_rx_count[4]), + .LO(plm_fsm_rl_counterx_reg_rx_count_qxu[4]) + ); + defparam plm_fsm_rl_counterx_reg_rx_count_qxu_0_5_.INIT = 4'h7; + LUT2_L plm_fsm_rl_counterx_reg_rx_count_qxu_0_5_ ( + .I0(plm_fsm_rl_counterx_un1_reg_rx_expired_0_a2_0_a2_0_a4), + .I1(plm_fsm_rl_counterx_reg_rx_count[5]), + .LO(plm_fsm_rl_counterx_reg_rx_count_qxu[5]) + ); + defparam plm_fsm_rl_counterx_reg_rx_count_qxu_0_6_.INIT = 4'h7; + LUT2_L plm_fsm_rl_counterx_reg_rx_count_qxu_0_6_ ( + .I0(plm_fsm_rl_counterx_un1_reg_rx_expired_0_a2_0_a2_0_a4), + .I1(plm_fsm_rl_counterx_reg_rx_count[6]), + .LO(plm_fsm_rl_counterx_reg_rx_count_qxu[6]) + ); + defparam plm_fsm_rl_counterx_reg_rx_count_qxu_0_7_.INIT = 4'h7; + LUT2_L plm_fsm_rl_counterx_reg_rx_count_qxu_0_7_ ( + .I0(plm_fsm_rl_counterx_un1_reg_rx_expired_0_a2_0_a2_0_a4), + .I1(plm_fsm_rl_counterx_reg_rx_count[7]), + .LO(plm_fsm_rl_counterx_reg_rx_count_qxu[7]) + ); + defparam plm_fsm_rl_counterx_reg_tx_count_qxu_0_0_.INIT = 4'h7; + LUT2_L plm_fsm_rl_counterx_reg_tx_count_qxu_0_0_ ( + .I0(plm_fsm_rl_counterx_reg_tx_count[0]), + .I1(plm_fsm_rl_counterx_un1_enable_1), + .LO(plm_fsm_rl_counterx_reg_tx_count_qxu[0]) + ); + defparam plm_fsm_rl_counterx_reg_tx_count_qxu_0_1_.INIT = 4'h7; + LUT2_L plm_fsm_rl_counterx_reg_tx_count_qxu_0_1_ ( + .I0(plm_fsm_rl_counterx_reg_tx_count[1]), + .I1(plm_fsm_rl_counterx_un1_enable_1), + .LO(plm_fsm_rl_counterx_reg_tx_count_qxu[1]) + ); + defparam plm_fsm_rl_counterx_reg_tx_count_qxu_0_2_.INIT = 4'h7; + LUT2_L plm_fsm_rl_counterx_reg_tx_count_qxu_0_2_ ( + .I0(plm_fsm_rl_counterx_reg_tx_count[2]), + .I1(plm_fsm_rl_counterx_un1_enable_1), + .LO(plm_fsm_rl_counterx_reg_tx_count_qxu[2]) + ); + defparam plm_fsm_rl_counterx_reg_tx_count_qxu_0_3_.INIT = 4'h7; + LUT2_L plm_fsm_rl_counterx_reg_tx_count_qxu_0_3_ ( + .I0(plm_fsm_rl_counterx_reg_tx_count[3]), + .I1(plm_fsm_rl_counterx_un1_enable_1), + .LO(plm_fsm_rl_counterx_reg_tx_count_qxu[3]) + ); + defparam plm_fsm_rl_counterx_reg_tx_count_qxu_0_4_.INIT = 4'h7; + LUT2_L plm_fsm_rl_counterx_reg_tx_count_qxu_0_4_ ( + .I0(plm_fsm_rl_counterx_reg_tx_count[4]), + .I1(plm_fsm_rl_counterx_un1_enable_1), + .LO(plm_fsm_rl_counterx_reg_tx_count_qxu[4]) + ); + defparam plm_fsm_rl_counterx_reg_tx_count_qxu_0_5_.INIT = 4'h7; + LUT2_L plm_fsm_rl_counterx_reg_tx_count_qxu_0_5_ ( + .I0(plm_fsm_rl_counterx_reg_tx_count[5]), + .I1(plm_fsm_rl_counterx_un1_enable_1), + .LO(plm_fsm_rl_counterx_reg_tx_count_qxu[5]) + ); + defparam plm_fsm_rl_counterx_reg_tx_count_qxu_0_6_.INIT = 4'h7; + LUT2_L plm_fsm_rl_counterx_reg_tx_count_qxu_0_6_ ( + .I0(plm_fsm_rl_counterx_reg_tx_count[6]), + .I1(plm_fsm_rl_counterx_un1_enable_1), + .LO(plm_fsm_rl_counterx_reg_tx_count_qxu[6]) + ); + defparam plm_fsm_rl_counterx_reg_tx_count_qxu_0_7_.INIT = 4'h7; + LUT2_L plm_fsm_rl_counterx_reg_tx_count_qxu_0_7_ ( + .I0(plm_fsm_rl_counterx_reg_tx_count[7]), + .I1(plm_fsm_rl_counterx_un1_enable_1), + .LO(plm_fsm_rl_counterx_reg_tx_count_qxu[7]) + ); + defparam plm_fsm_rl_counterx_reg_tx_count_qxu_0_8_.INIT = 4'h7; + LUT2_L plm_fsm_rl_counterx_reg_tx_count_qxu_0_8_ ( + .I0(plm_fsm_rl_counterx_reg_tx_count[8]), + .I1(plm_fsm_rl_counterx_un1_enable_1), + .LO(plm_fsm_rl_counterx_reg_tx_count_qxu[8]) + ); + defparam plm_fsm_rl_counterx_reg_tx_count_qxu_0_9_.INIT = 4'h7; + LUT2_L plm_fsm_rl_counterx_reg_tx_count_qxu_0_9_ ( + .I0(plm_fsm_rl_counterx_reg_tx_count[9]), + .I1(plm_fsm_rl_counterx_un1_enable_1), + .LO(plm_fsm_rl_counterx_reg_tx_count_qxu[9]) + ); + defparam plm_fsm_rl_counterx_reg_tx_count_qxu_0_10_.INIT = 8'h3A; + LUT3_L plm_fsm_rl_counterx_reg_tx_count_qxu_0_10_ ( + .I0(plm_fsm_reg_state_13__41), + .I1(plm_fsm_rl_counterx_reg_tx_count[10]), + .I2(plm_fsm_rl_counterx_un1_enable_1), + .LO(plm_fsm_rl_counterx_reg_tx_count_qxu[10]) + ); + defparam plm_fsm_rl_counterx_reg_tx_count_qxu_0_11_.INIT = 4'h7; + LUT2_L plm_fsm_rl_counterx_reg_tx_count_qxu_0_11_ ( + .I0(plm_fsm_rl_counterx_reg_tx_count[11]), + .I1(plm_fsm_rl_counterx_un1_enable_1), + .LO(plm_fsm_rl_counterx_reg_tx_count_qxu[11]) + ); + VCC plm_fsm_rl_counter0_VCC ( + .P(plm_fsm_rl_counter0_VCC_1009) + ); + MUXCY_L plm_fsm_rl_counter0_reg_rx_count_cry_0_ ( + .CI(N_18708_i_i_42), + .DI(plm_fsm_rl_counter0_VCC_1009), + .LO(plm_fsm_rl_counter0_reg_rx_count_cry[0]), + .S(plm_fsm_rl_counter0_reg_rx_count_qxu[0]) + ); + XORCY plm_fsm_rl_counter0_reg_rx_count_s_0_ ( + .CI(N_18708_i_i_42), + .LI(plm_fsm_rl_counter0_reg_rx_count_qxu[0]), + .O(plm_fsm_rl_counter0_reg_rx_count_s[0]) + ); + MUXCY_L plm_fsm_rl_counter0_reg_rx_count_cry_1_ ( + .CI(plm_fsm_rl_counter0_reg_rx_count_cry[0]), + .DI(plm_fsm_rl_counter0_VCC_1009), + .LO(plm_fsm_rl_counter0_reg_rx_count_cry[1]), + .S(plm_fsm_rl_counter0_reg_rx_count_qxu[1]) + ); + XORCY plm_fsm_rl_counter0_reg_rx_count_s_1_ ( + .CI(plm_fsm_rl_counter0_reg_rx_count_cry[0]), + .LI(plm_fsm_rl_counter0_reg_rx_count_qxu[1]), + .O(plm_fsm_rl_counter0_reg_rx_count_s[1]) + ); + MUXCY_L plm_fsm_rl_counter0_reg_rx_count_cry_2_ ( + .CI(plm_fsm_rl_counter0_reg_rx_count_cry[1]), + .DI(plm_fsm_rl_counter0_VCC_1009), + .LO(plm_fsm_rl_counter0_reg_rx_count_cry[2]), + .S(plm_fsm_rl_counter0_reg_rx_count_qxu[2]) + ); + XORCY plm_fsm_rl_counter0_reg_rx_count_s_2_ ( + .CI(plm_fsm_rl_counter0_reg_rx_count_cry[1]), + .LI(plm_fsm_rl_counter0_reg_rx_count_qxu[2]), + .O(plm_fsm_rl_counter0_reg_rx_count_s[2]) + ); + MUXCY_L plm_fsm_rl_counter0_reg_rx_count_cry_3_ ( + .CI(plm_fsm_rl_counter0_reg_rx_count_cry[2]), + .DI(plm_fsm_rl_counter0_VCC_1009), + .LO(plm_fsm_rl_counter0_reg_rx_count_cry[3]), + .S(plm_fsm_rl_counter0_reg_rx_count_qxu[3]) + ); + XORCY plm_fsm_rl_counter0_reg_rx_count_s_3_ ( + .CI(plm_fsm_rl_counter0_reg_rx_count_cry[2]), + .LI(plm_fsm_rl_counter0_reg_rx_count_qxu[3]), + .O(plm_fsm_rl_counter0_reg_rx_count_s[3]) + ); + MUXCY_L plm_fsm_rl_counter0_reg_rx_count_cry_4_ ( + .CI(plm_fsm_rl_counter0_reg_rx_count_cry[3]), + .DI(plm_fsm_rl_counter0_VCC_1009), + .LO(plm_fsm_rl_counter0_reg_rx_count_cry[4]), + .S(plm_fsm_rl_counter0_reg_rx_count_qxu[4]) + ); + XORCY plm_fsm_rl_counter0_reg_rx_count_s_4_ ( + .CI(plm_fsm_rl_counter0_reg_rx_count_cry[3]), + .LI(plm_fsm_rl_counter0_reg_rx_count_qxu[4]), + .O(plm_fsm_rl_counter0_reg_rx_count_s[4]) + ); + MUXCY_L plm_fsm_rl_counter0_reg_rx_count_cry_5_ ( + .CI(plm_fsm_rl_counter0_reg_rx_count_cry[4]), + .DI(plm_fsm_rl_counter0_VCC_1009), + .LO(plm_fsm_rl_counter0_reg_rx_count_cry[5]), + .S(plm_fsm_rl_counter0_reg_rx_count_qxu[5]) + ); + XORCY plm_fsm_rl_counter0_reg_rx_count_s_5_ ( + .CI(plm_fsm_rl_counter0_reg_rx_count_cry[4]), + .LI(plm_fsm_rl_counter0_reg_rx_count_qxu[5]), + .O(plm_fsm_rl_counter0_reg_rx_count_s[5]) + ); + MUXCY_L plm_fsm_rl_counter0_reg_rx_count_cry_6_ ( + .CI(plm_fsm_rl_counter0_reg_rx_count_cry[5]), + .DI(plm_fsm_rl_counter0_VCC_1009), + .LO(plm_fsm_rl_counter0_reg_rx_count_cry[6]), + .S(plm_fsm_rl_counter0_reg_rx_count_qxu[6]) + ); + XORCY plm_fsm_rl_counter0_reg_rx_count_s_6_ ( + .CI(plm_fsm_rl_counter0_reg_rx_count_cry[5]), + .LI(plm_fsm_rl_counter0_reg_rx_count_qxu[6]), + .O(plm_fsm_rl_counter0_reg_rx_count_s[6]) + ); + XORCY plm_fsm_rl_counter0_reg_rx_count_s_7_ ( + .CI(plm_fsm_rl_counter0_reg_rx_count_cry[6]), + .LI(plm_fsm_rl_counter0_reg_rx_count_qxu[7]), + .O(plm_fsm_rl_counter0_reg_rx_count_s[7]) + ); + defparam plm_fsm_rl_counter0_flagit_reg_expired_5_0_a2_0_a2_0_a4_1.INIT = 4'h8; + LUT2 plm_fsm_rl_counter0_flagit_reg_expired_5_0_a2_0_a2_0_a4_1 ( + .I0(plm_fsm_reg_state_13__41), + .I1(plm_fsm_reg_tx_expired), + .O(plm_fsm_reg_expired_5_1) + ); + defparam plm_fsm_rl_counter0_un1_enable_2_0_0_i_o3.INIT = 4'h1; + LUT2 plm_fsm_rl_counter0_un1_enable_2_0_0_i_o3 ( + .I0(plm_reg_ts2_1), + .I1(plm_reg_ts1_1), + .O(plm_fsm_N_38095_i) + ); + defparam plm_fsm_rl_counter0_loadable_rx_counter_un1_reg_rx_count_0_a2_4.INIT = 16'h0001; + LUT4 plm_fsm_rl_counter0_loadable_rx_counter_un1_reg_rx_count_0_a2_4 ( + .I0(plm_fsm_rl_counter0_reg_rx_count[0]), + .I1(plm_fsm_rl_counter0_reg_rx_count[1]), + .I2(plm_fsm_rl_counter0_reg_rx_count[2]), + .I3(plm_fsm_rl_counter0_reg_rx_count[3]), + .O(plm_fsm_rl_counter0_un1_reg_rx_count_0_a2_4) + ); + defparam plm_fsm_rl_counter0_loadable_rx_counter_un1_reg_rx_count_0_a2_5.INIT = 16'h0001; + LUT4 plm_fsm_rl_counter0_loadable_rx_counter_un1_reg_rx_count_0_a2_5 ( + .I0(plm_fsm_rl_counter0_reg_rx_count[4]), + .I1(plm_fsm_rl_counter0_reg_rx_count[5]), + .I2(plm_fsm_rl_counter0_reg_rx_count[6]), + .I3(plm_fsm_rl_counter0_reg_rx_count[7]), + .O(plm_fsm_rl_counter0_un1_reg_rx_count_0_a2_5) + ); + defparam plm_fsm_rl_counter0_loadable_tx_counter_N_38564_i.INIT = 8'h57; + LUT3 plm_fsm_rl_counter0_loadable_tx_counter_N_38564_i ( + .I0(plm_fsm_reg_state_13__41), + .I1(plm_fsm_reg_tx_count_4_), + .I2(plm_fsm_reg_tx_count_10_), + .O(plm_fsm_N_38564_i) + ); + defparam plm_fsm_rl_counter0_loadable_rx_counter_un1_reg_rx_expired_1_i.INIT = 8'hF7; + LUT3 plm_fsm_rl_counter0_loadable_rx_counter_un1_reg_rx_expired_1_i ( + .I0(plm_fsm_N_38095_i), + .I1(plm_fsm_reg_state_13__41), + .I2(plm_fsm_rl_counter0_reg_rx_expired_40), + .O(plm_fsm_rl_counter0_un1_reg_rx_expired_1_i) + ); + defparam plm_fsm_rl_counter0_loadable_rx_counter_N_38563_i.INIT = 8'hD5; + LUT3 plm_fsm_rl_counter0_loadable_rx_counter_N_38563_i ( + .I0(plm_fsm_reg_state_13__41), + .I1(plm_fsm_rl_counter0_un1_reg_rx_count_0_a2_4), + .I2(plm_fsm_rl_counter0_un1_reg_rx_count_0_a2_5), + .O(plm_fsm_rl_counter0_N_38563_i) + ); + defparam plm_fsm_rl_counter0_N_69264_i.INIT = 16'h0F1F; + LUT4 plm_fsm_rl_counter0_N_69264_i ( + .I0(plm_fsm_N_38095_i), + .I1(N_38240_i), + .I2(plm_fsm_reg_state_13__41), + .I3(plm_fsm_rl_counter0_reg_rx_expired_40), + .O(plm_fsm_rl_counter0_N_69264_i_1010) + ); + defparam plm_fsm_rl_counter0_flagit_reg_expired_5_0_a2_0_a2_0_a4.INIT = 4'h8; + LUT2_L plm_fsm_rl_counter0_flagit_reg_expired_5_0_a2_0_a2_0_a4 ( + .I0(plm_fsm_reg_expired_5_1), + .I1(plm_fsm_rl_counter0_reg_rx_expired_40), + .LO(plm_fsm_rl_counter0_reg_expired_5) + ); + defparam plm_fsm_rl_counter0_loadable_tx_counter_reg_tx_count_6_0_a2_10_.INIT = 4'h1; + LUT2_L plm_fsm_rl_counter0_loadable_tx_counter_reg_tx_count_6_0_a2_10_ ( + .I0(cfg_cfg_5072[507]), + .I1(plm_fsm_reg_state_13__41), + .LO(plm_fsm_reg_tx_count_6_0[10]) + ); + FDCE plm_fsm_rl_counter0_reg_rx_count_7_ ( + .CE(plm_fsm_rl_counter0_un1_reg_rx_expired_1_i), + .C(mgt_clk), + .D(plm_fsm_rl_counter0_reg_rx_count_s[7]), + .Q(plm_fsm_rl_counter0_reg_rx_count[7]), + .CLR(plm_rst) + ); + FDCE plm_fsm_rl_counter0_reg_rx_count_6_ ( + .CE(plm_fsm_rl_counter0_un1_reg_rx_expired_1_i), + .C(mgt_clk), + .D(plm_fsm_rl_counter0_reg_rx_count_s[6]), + .Q(plm_fsm_rl_counter0_reg_rx_count[6]), + .CLR(plm_rst) + ); + FDCE plm_fsm_rl_counter0_reg_rx_count_5_ ( + .CE(plm_fsm_rl_counter0_un1_reg_rx_expired_1_i), + .C(mgt_clk), + .D(plm_fsm_rl_counter0_reg_rx_count_s[5]), + .Q(plm_fsm_rl_counter0_reg_rx_count[5]), + .CLR(plm_rst) + ); + FDCE plm_fsm_rl_counter0_reg_rx_count_4_ ( + .CE(plm_fsm_rl_counter0_un1_reg_rx_expired_1_i), + .C(mgt_clk), + .D(plm_fsm_rl_counter0_reg_rx_count_s[4]), + .Q(plm_fsm_rl_counter0_reg_rx_count[4]), + .CLR(plm_rst) + ); + FDCE plm_fsm_rl_counter0_reg_rx_count_3_ ( + .CE(plm_fsm_rl_counter0_un1_reg_rx_expired_1_i), + .C(mgt_clk), + .D(plm_fsm_rl_counter0_reg_rx_count_s[3]), + .Q(plm_fsm_rl_counter0_reg_rx_count[3]), + .CLR(plm_rst) + ); + FDCE plm_fsm_rl_counter0_reg_rx_count_2_ ( + .CE(plm_fsm_rl_counter0_un1_reg_rx_expired_1_i), + .C(mgt_clk), + .D(plm_fsm_rl_counter0_reg_rx_count_s[2]), + .Q(plm_fsm_rl_counter0_reg_rx_count[2]), + .CLR(plm_rst) + ); + FDCE plm_fsm_rl_counter0_reg_rx_count_1_ ( + .CE(plm_fsm_rl_counter0_un1_reg_rx_expired_1_i), + .C(mgt_clk), + .D(plm_fsm_rl_counter0_reg_rx_count_s[1]), + .Q(plm_fsm_rl_counter0_reg_rx_count[1]), + .CLR(plm_rst) + ); + FDCE plm_fsm_rl_counter0_reg_rx_count_0_ ( + .CE(plm_fsm_rl_counter0_un1_reg_rx_expired_1_i), + .C(mgt_clk), + .D(plm_fsm_rl_counter0_reg_rx_count_s[0]), + .Q(plm_fsm_rl_counter0_reg_rx_count[0]), + .CLR(plm_rst) + ); + FDC plm_fsm_rl_counter0_reg_expired ( + .C(mgt_clk), + .D(plm_fsm_rl_counter0_reg_expired_5), + .Q(plm_fsm_rl_cntrout0), + .CLR(plm_rst) + ); + FDCE plm_fsm_rl_counter0_reg_rx_expired ( + .CE(plm_fsm_rl_counter0_N_38563_i), + .C(mgt_clk), + .D(plm_fsm_reg_state_13__41), + .Q(plm_fsm_rl_counter0_reg_rx_expired_40), + .CLR(plm_rst) + ); + defparam plm_fsm_rl_counter0_reg_rx_count_qxu_0_0_.INIT = 4'h7; + LUT2_L plm_fsm_rl_counter0_reg_rx_count_qxu_0_0_ ( + .I0(N_18708_i), + .I1(plm_fsm_rl_counter0_reg_rx_count[0]), + .LO(plm_fsm_rl_counter0_reg_rx_count_qxu[0]) + ); + defparam plm_fsm_rl_counter0_reg_rx_count_qxu_0_1_.INIT = 4'h7; + LUT2_L plm_fsm_rl_counter0_reg_rx_count_qxu_0_1_ ( + .I0(N_18708_i), + .I1(plm_fsm_rl_counter0_reg_rx_count[1]), + .LO(plm_fsm_rl_counter0_reg_rx_count_qxu[1]) + ); + defparam plm_fsm_rl_counter0_reg_rx_count_qxu_0_2_.INIT = 4'h7; + LUT2_L plm_fsm_rl_counter0_reg_rx_count_qxu_0_2_ ( + .I0(N_18708_i), + .I1(plm_fsm_rl_counter0_reg_rx_count[2]), + .LO(plm_fsm_rl_counter0_reg_rx_count_qxu[2]) + ); + defparam plm_fsm_rl_counter0_reg_rx_count_qxu_0_3_.INIT = 8'h1B; + LUT3_L plm_fsm_rl_counter0_reg_rx_count_qxu_0_3_ ( + .I0(N_18708_i), + .I1(plm_fsm_rl_counter0_N_69264_i_1010), + .I2(plm_fsm_rl_counter0_reg_rx_count[3]), + .LO(plm_fsm_rl_counter0_reg_rx_count_qxu[3]) + ); + defparam plm_fsm_rl_counter0_reg_rx_count_qxu_0_4_.INIT = 4'h7; + LUT2_L plm_fsm_rl_counter0_reg_rx_count_qxu_0_4_ ( + .I0(N_18708_i), + .I1(plm_fsm_rl_counter0_reg_rx_count[4]), + .LO(plm_fsm_rl_counter0_reg_rx_count_qxu[4]) + ); + defparam plm_fsm_rl_counter0_reg_rx_count_qxu_0_5_.INIT = 4'h7; + LUT2_L plm_fsm_rl_counter0_reg_rx_count_qxu_0_5_ ( + .I0(N_18708_i), + .I1(plm_fsm_rl_counter0_reg_rx_count[5]), + .LO(plm_fsm_rl_counter0_reg_rx_count_qxu[5]) + ); + defparam plm_fsm_rl_counter0_reg_rx_count_qxu_0_6_.INIT = 4'h7; + LUT2_L plm_fsm_rl_counter0_reg_rx_count_qxu_0_6_ ( + .I0(N_18708_i), + .I1(plm_fsm_rl_counter0_reg_rx_count[6]), + .LO(plm_fsm_rl_counter0_reg_rx_count_qxu[6]) + ); + defparam plm_fsm_rl_counter0_reg_rx_count_qxu_0_7_.INIT = 4'h7; + LUT2_L plm_fsm_rl_counter0_reg_rx_count_qxu_0_7_ ( + .I0(N_18708_i), + .I1(plm_fsm_rl_counter0_reg_rx_count[7]), + .LO(plm_fsm_rl_counter0_reg_rx_count_qxu[7]) + ); + defparam plm_fsm_rl_counter1_loadable_rx_counter_N_38562_i.INIT = 4'h7; + LUT2 plm_fsm_rl_counter1_loadable_rx_counter_N_38562_i ( + .I0(plm_fsm_reg_state_13__41), + .I1(plm_fsm_rl_counter1_reg_rx_count[3]), + .O(plm_fsm_rl_counter1_N_38562_i) + ); + defparam plm_fsm_rl_counter1_loadable_rx_counter_N_38573_i.INIT = 4'hD; + LUT2 plm_fsm_rl_counter1_loadable_rx_counter_N_38573_i ( + .I0(plm_fsm_reg_state_13__41), + .I1(plm_fsm_rl_counter1_reg_rx_expired_1011), + .O(plm_fsm_rl_counter1_N_38573_i) + ); + defparam plm_fsm_rl_counter1_flagit_reg_expired_5_0_a2_0_a2_0_a4.INIT = 4'h8; + LUT2_L plm_fsm_rl_counter1_flagit_reg_expired_5_0_a2_0_a2_0_a4 ( + .I0(plm_fsm_reg_expired_5_1), + .I1(plm_fsm_rl_counter1_reg_rx_expired_1011), + .LO(plm_fsm_rl_counter1_reg_expired_5) + ); + FDC plm_fsm_rl_counter1_reg_expired ( + .C(mgt_clk), + .D(plm_fsm_rl_counter1_reg_expired_5), + .Q(plm_fsm_rl_cntrout1), + .CLR(plm_rst) + ); + FDCE plm_fsm_rl_counter1_reg_rx_count_3_ ( + .CE(plm_fsm_rl_counter1_N_38573_i), + .C(mgt_clk), + .D(plm_fsm_reg_state_i_13__904), + .Q(plm_fsm_rl_counter1_reg_rx_count[3]), + .CLR(plm_rst) + ); + FDCE plm_fsm_rl_counter1_reg_rx_expired ( + .CE(plm_fsm_rl_counter1_N_38562_i), + .C(mgt_clk), + .D(plm_fsm_reg_state_13__41), + .Q(plm_fsm_rl_counter1_reg_rx_expired_1011), + .CLR(plm_rst) + ); + defparam plm_fsm_rl_counter2_loadable_rx_counter_N_38561_i.INIT = 4'h7; + LUT2 plm_fsm_rl_counter2_loadable_rx_counter_N_38561_i ( + .I0(plm_fsm_reg_state_13__41), + .I1(plm_fsm_rl_counter2_reg_rx_count[3]), + .O(plm_fsm_rl_counter2_N_38561_i) + ); + defparam plm_fsm_rl_counter2_loadable_rx_counter_N_38572_i.INIT = 4'hD; + LUT2 plm_fsm_rl_counter2_loadable_rx_counter_N_38572_i ( + .I0(plm_fsm_reg_state_13__41), + .I1(plm_fsm_rl_counter2_reg_rx_expired_1012), + .O(plm_fsm_rl_counter2_N_38572_i) + ); + defparam plm_fsm_rl_counter2_flagit_reg_expired_5_0_a2_0_a2_0_a4.INIT = 4'h8; + LUT2_L plm_fsm_rl_counter2_flagit_reg_expired_5_0_a2_0_a2_0_a4 ( + .I0(plm_fsm_reg_expired_5_1), + .I1(plm_fsm_rl_counter2_reg_rx_expired_1012), + .LO(plm_fsm_rl_counter2_reg_expired_5) + ); + FDC plm_fsm_rl_counter2_reg_expired ( + .C(mgt_clk), + .D(plm_fsm_rl_counter2_reg_expired_5), + .Q(plm_fsm_rl_cntrout2), + .CLR(plm_rst) + ); + FDCE plm_fsm_rl_counter2_reg_rx_count_3_ ( + .CE(plm_fsm_rl_counter2_N_38572_i), + .C(mgt_clk), + .D(plm_fsm_reg_state_i_13__904), + .Q(plm_fsm_rl_counter2_reg_rx_count[3]), + .CLR(plm_rst) + ); + FDCE plm_fsm_rl_counter2_reg_rx_expired ( + .CE(plm_fsm_rl_counter2_N_38561_i), + .C(mgt_clk), + .D(plm_fsm_reg_state_13__41), + .Q(plm_fsm_rl_counter2_reg_rx_expired_1012), + .CLR(plm_rst) + ); + defparam plm_fsm_rl_counter3_loadable_rx_counter_N_38560_i.INIT = 4'h7; + LUT2 plm_fsm_rl_counter3_loadable_rx_counter_N_38560_i ( + .I0(plm_fsm_reg_state_13__41), + .I1(plm_fsm_rl_counter3_reg_rx_count[3]), + .O(plm_fsm_rl_counter3_N_38560_i) + ); + defparam plm_fsm_rl_counter3_loadable_rx_counter_N_38571_i.INIT = 4'hD; + LUT2 plm_fsm_rl_counter3_loadable_rx_counter_N_38571_i ( + .I0(plm_fsm_reg_state_13__41), + .I1(plm_fsm_rl_counter3_reg_rx_expired_1013), + .O(plm_fsm_rl_counter3_N_38571_i) + ); + defparam plm_fsm_rl_counter3_flagit_reg_expired_5_0_a2_0_a2_0_a4.INIT = 4'h8; + LUT2_L plm_fsm_rl_counter3_flagit_reg_expired_5_0_a2_0_a2_0_a4 ( + .I0(plm_fsm_reg_expired_5_1), + .I1(plm_fsm_rl_counter3_reg_rx_expired_1013), + .LO(plm_fsm_rl_counter3_reg_expired_5) + ); + FDC plm_fsm_rl_counter3_reg_expired ( + .C(mgt_clk), + .D(plm_fsm_rl_counter3_reg_expired_5), + .Q(plm_fsm_rl_cntrout3), + .CLR(plm_rst) + ); + FDCE plm_fsm_rl_counter3_reg_rx_count_3_ ( + .CE(plm_fsm_rl_counter3_N_38571_i), + .C(mgt_clk), + .D(plm_fsm_reg_state_i_13__904), + .Q(plm_fsm_rl_counter3_reg_rx_count[3]), + .CLR(plm_rst) + ); + FDC plm_fsm_rl_counter3_reg_tx_count_10_ ( + .C(mgt_clk), + .D(plm_fsm_reg_tx_count_6_0[10]), + .Q(plm_fsm_reg_tx_count_10_), + .CLR(plm_rst) + ); + FDC plm_fsm_rl_counter3_reg_tx_count_4_ ( + .C(mgt_clk), + .D(plm_fsm_rl_counter3_loadable_tx_counter_reg_tx_count_6[4]), + .Q(plm_fsm_reg_tx_count_4_), + .CLR(plm_rst) + ); + FDCE plm_fsm_rl_counter3_reg_tx_expired ( + .CE(plm_fsm_N_38564_i), + .C(mgt_clk), + .D(plm_fsm_reg_state_13__41), + .Q(plm_fsm_reg_tx_expired), + .CLR(plm_rst) + ); + FDCE plm_fsm_rl_counter3_reg_rx_expired ( + .CE(plm_fsm_rl_counter3_N_38560_i), + .C(mgt_clk), + .D(plm_fsm_reg_state_13__41), + .Q(plm_fsm_rl_counter3_reg_rx_expired_1013), + .CLR(plm_rst) + ); + GND plm_fsm_rc_timer_GND ( + .G(plm_fsm_rc_timer_GND_1014) + ); + MUXCY_L plm_fsm_rc_timer_reg_count_cry_0_ ( + .CI(plm_fsm_N_38100_i_i), + .DI(plm_fsm_rc_timer_GND_1014), + .LO(plm_fsm_rc_timer_reg_count_cry[0]), + .S(plm_fsm_rc_timer_reg_count_qxu[0]) + ); + XORCY plm_fsm_rc_timer_reg_count_s_0_ ( + .CI(plm_fsm_N_38100_i_i), + .LI(plm_fsm_rc_timer_reg_count_qxu[0]), + .O(plm_fsm_rc_timer_reg_count_s[0]) + ); + MUXCY_L plm_fsm_rc_timer_reg_count_cry_1_ ( + .CI(plm_fsm_rc_timer_reg_count_cry[0]), + .DI(plm_fsm_rc_timer_GND_1014), + .LO(plm_fsm_rc_timer_reg_count_cry[1]), + .S(plm_fsm_rc_timer_reg_count_qxu[1]) + ); + XORCY plm_fsm_rc_timer_reg_count_s_1_ ( + .CI(plm_fsm_rc_timer_reg_count_cry[0]), + .LI(plm_fsm_rc_timer_reg_count_qxu[1]), + .O(plm_fsm_rc_timer_reg_count_s[1]) + ); + MUXCY_L plm_fsm_rc_timer_reg_count_cry_2_ ( + .CI(plm_fsm_rc_timer_reg_count_cry[1]), + .DI(plm_fsm_rc_timer_GND_1014), + .LO(plm_fsm_rc_timer_reg_count_cry[2]), + .S(plm_fsm_rc_timer_reg_count_qxu[2]) + ); + XORCY plm_fsm_rc_timer_reg_count_s_2_ ( + .CI(plm_fsm_rc_timer_reg_count_cry[1]), + .LI(plm_fsm_rc_timer_reg_count_qxu[2]), + .O(plm_fsm_rc_timer_reg_count_s[2]) + ); + MUXCY_L plm_fsm_rc_timer_reg_count_cry_3_ ( + .CI(plm_fsm_rc_timer_reg_count_cry[2]), + .DI(plm_fsm_rc_timer_GND_1014), + .LO(plm_fsm_rc_timer_reg_count_cry[3]), + .S(plm_fsm_rc_timer_reg_count_qxu[3]) + ); + XORCY plm_fsm_rc_timer_reg_count_s_3_ ( + .CI(plm_fsm_rc_timer_reg_count_cry[2]), + .LI(plm_fsm_rc_timer_reg_count_qxu[3]), + .O(plm_fsm_rc_timer_reg_count_s[3]) + ); + MUXCY_L plm_fsm_rc_timer_reg_count_cry_4_ ( + .CI(plm_fsm_rc_timer_reg_count_cry[3]), + .DI(plm_fsm_rc_timer_GND_1014), + .LO(plm_fsm_rc_timer_reg_count_cry[4]), + .S(plm_fsm_rc_timer_reg_count_qxu[4]) + ); + XORCY plm_fsm_rc_timer_reg_count_s_4_ ( + .CI(plm_fsm_rc_timer_reg_count_cry[3]), + .LI(plm_fsm_rc_timer_reg_count_qxu[4]), + .O(plm_fsm_rc_timer_reg_count_s[4]) + ); + MUXCY_L plm_fsm_rc_timer_reg_count_cry_5_ ( + .CI(plm_fsm_rc_timer_reg_count_cry[4]), + .DI(plm_fsm_rc_timer_GND_1014), + .LO(plm_fsm_rc_timer_reg_count_cry[5]), + .S(plm_fsm_rc_timer_reg_count_qxu[5]) + ); + XORCY plm_fsm_rc_timer_reg_count_s_5_ ( + .CI(plm_fsm_rc_timer_reg_count_cry[4]), + .LI(plm_fsm_rc_timer_reg_count_qxu[5]), + .O(plm_fsm_rc_timer_reg_count_s[5]) + ); + MUXCY_L plm_fsm_rc_timer_reg_count_cry_6_ ( + .CI(plm_fsm_rc_timer_reg_count_cry[5]), + .DI(plm_fsm_rc_timer_GND_1014), + .LO(plm_fsm_rc_timer_reg_count_cry[6]), + .S(plm_fsm_rc_timer_reg_count_qxu[6]) + ); + XORCY plm_fsm_rc_timer_reg_count_s_6_ ( + .CI(plm_fsm_rc_timer_reg_count_cry[5]), + .LI(plm_fsm_rc_timer_reg_count_qxu[6]), + .O(plm_fsm_rc_timer_reg_count_s[6]) + ); + MUXCY_L plm_fsm_rc_timer_reg_count_cry_7_ ( + .CI(plm_fsm_rc_timer_reg_count_cry[6]), + .DI(plm_fsm_rc_timer_GND_1014), + .LO(plm_fsm_rc_timer_reg_count_cry[7]), + .S(plm_fsm_rc_timer_reg_count_qxu[7]) + ); + XORCY plm_fsm_rc_timer_reg_count_s_7_ ( + .CI(plm_fsm_rc_timer_reg_count_cry[6]), + .LI(plm_fsm_rc_timer_reg_count_qxu[7]), + .O(plm_fsm_rc_timer_reg_count_s[7]) + ); + MUXCY_L plm_fsm_rc_timer_reg_count_cry_8_ ( + .CI(plm_fsm_rc_timer_reg_count_cry[7]), + .DI(plm_fsm_rc_timer_GND_1014), + .LO(plm_fsm_rc_timer_reg_count_cry[8]), + .S(plm_fsm_rc_timer_reg_count_qxu[8]) + ); + XORCY plm_fsm_rc_timer_reg_count_s_8_ ( + .CI(plm_fsm_rc_timer_reg_count_cry[7]), + .LI(plm_fsm_rc_timer_reg_count_qxu[8]), + .O(plm_fsm_rc_timer_reg_count_s[8]) + ); + MUXCY_L plm_fsm_rc_timer_reg_count_cry_9_ ( + .CI(plm_fsm_rc_timer_reg_count_cry[8]), + .DI(plm_fsm_rc_timer_GND_1014), + .LO(plm_fsm_rc_timer_reg_count_cry[9]), + .S(plm_fsm_rc_timer_reg_count_qxu[9]) + ); + XORCY plm_fsm_rc_timer_reg_count_s_9_ ( + .CI(plm_fsm_rc_timer_reg_count_cry[8]), + .LI(plm_fsm_rc_timer_reg_count_qxu[9]), + .O(plm_fsm_rc_timer_reg_count_s[9]) + ); + MUXCY_L plm_fsm_rc_timer_reg_count_cry_10_ ( + .CI(plm_fsm_rc_timer_reg_count_cry[9]), + .DI(plm_fsm_rc_timer_GND_1014), + .LO(plm_fsm_rc_timer_reg_count_cry[10]), + .S(plm_fsm_rc_timer_reg_count_qxu[10]) + ); + XORCY plm_fsm_rc_timer_reg_count_s_10_ ( + .CI(plm_fsm_rc_timer_reg_count_cry[9]), + .LI(plm_fsm_rc_timer_reg_count_qxu[10]), + .O(plm_fsm_rc_timer_reg_count_s[10]) + ); + MUXCY_L plm_fsm_rc_timer_reg_count_cry_11_ ( + .CI(plm_fsm_rc_timer_reg_count_cry[10]), + .DI(plm_fsm_rc_timer_GND_1014), + .LO(plm_fsm_rc_timer_reg_count_cry[11]), + .S(plm_fsm_rc_timer_reg_count_qxu[11]) + ); + XORCY plm_fsm_rc_timer_reg_count_s_11_ ( + .CI(plm_fsm_rc_timer_reg_count_cry[10]), + .LI(plm_fsm_rc_timer_reg_count_qxu[11]), + .O(plm_fsm_rc_timer_reg_count_s[11]) + ); + MUXCY_L plm_fsm_rc_timer_reg_count_cry_12_ ( + .CI(plm_fsm_rc_timer_reg_count_cry[11]), + .DI(plm_fsm_rc_timer_GND_1014), + .LO(plm_fsm_rc_timer_reg_count_cry[12]), + .S(plm_fsm_rc_timer_reg_count_qxu[12]) + ); + XORCY plm_fsm_rc_timer_reg_count_s_12_ ( + .CI(plm_fsm_rc_timer_reg_count_cry[11]), + .LI(plm_fsm_rc_timer_reg_count_qxu[12]), + .O(plm_fsm_rc_timer_reg_count_s[12]) + ); + MUXCY_L plm_fsm_rc_timer_reg_count_cry_13_ ( + .CI(plm_fsm_rc_timer_reg_count_cry[12]), + .DI(plm_fsm_rc_timer_GND_1014), + .LO(plm_fsm_rc_timer_reg_count_cry[13]), + .S(plm_fsm_rc_timer_reg_count_qxu[13]) + ); + XORCY plm_fsm_rc_timer_reg_count_s_13_ ( + .CI(plm_fsm_rc_timer_reg_count_cry[12]), + .LI(plm_fsm_rc_timer_reg_count_qxu[13]), + .O(plm_fsm_rc_timer_reg_count_s[13]) + ); + MUXCY_L plm_fsm_rc_timer_reg_count_cry_14_ ( + .CI(plm_fsm_rc_timer_reg_count_cry[13]), + .DI(plm_fsm_rc_timer_GND_1014), + .LO(plm_fsm_rc_timer_reg_count_cry[14]), + .S(plm_fsm_rc_timer_reg_count_qxu[14]) + ); + XORCY plm_fsm_rc_timer_reg_count_s_14_ ( + .CI(plm_fsm_rc_timer_reg_count_cry[13]), + .LI(plm_fsm_rc_timer_reg_count_qxu[14]), + .O(plm_fsm_rc_timer_reg_count_s[14]) + ); + MUXCY_L plm_fsm_rc_timer_reg_count_cry_15_ ( + .CI(plm_fsm_rc_timer_reg_count_cry[14]), + .DI(plm_fsm_rc_timer_GND_1014), + .LO(plm_fsm_rc_timer_reg_count_cry[15]), + .S(plm_fsm_rc_timer_reg_count_qxu[15]) + ); + XORCY plm_fsm_rc_timer_reg_count_s_15_ ( + .CI(plm_fsm_rc_timer_reg_count_cry[14]), + .LI(plm_fsm_rc_timer_reg_count_qxu[15]), + .O(plm_fsm_rc_timer_reg_count_s[15]) + ); + MUXCY_L plm_fsm_rc_timer_reg_count_cry_16_ ( + .CI(plm_fsm_rc_timer_reg_count_cry[15]), + .DI(plm_fsm_rc_timer_GND_1014), + .LO(plm_fsm_rc_timer_reg_count_cry[16]), + .S(plm_fsm_rc_timer_reg_count_qxu[16]) + ); + XORCY plm_fsm_rc_timer_reg_count_s_16_ ( + .CI(plm_fsm_rc_timer_reg_count_cry[15]), + .LI(plm_fsm_rc_timer_reg_count_qxu[16]), + .O(plm_fsm_rc_timer_reg_count_s[16]) + ); + MUXCY_L plm_fsm_rc_timer_reg_count_cry_17_ ( + .CI(plm_fsm_rc_timer_reg_count_cry[16]), + .DI(plm_fsm_rc_timer_GND_1014), + .LO(plm_fsm_rc_timer_reg_count_cry[17]), + .S(plm_fsm_rc_timer_reg_count_qxu[17]) + ); + XORCY plm_fsm_rc_timer_reg_count_s_17_ ( + .CI(plm_fsm_rc_timer_reg_count_cry[16]), + .LI(plm_fsm_rc_timer_reg_count_qxu[17]), + .O(plm_fsm_rc_timer_reg_count_s[17]) + ); + MUXCY_L plm_fsm_rc_timer_reg_count_cry_18_ ( + .CI(plm_fsm_rc_timer_reg_count_cry[17]), + .DI(plm_fsm_rc_timer_GND_1014), + .LO(plm_fsm_rc_timer_reg_count_cry[18]), + .S(plm_fsm_rc_timer_reg_count_qxu[18]) + ); + XORCY plm_fsm_rc_timer_reg_count_s_18_ ( + .CI(plm_fsm_rc_timer_reg_count_cry[17]), + .LI(plm_fsm_rc_timer_reg_count_qxu[18]), + .O(plm_fsm_rc_timer_reg_count_s[18]) + ); + MUXCY_L plm_fsm_rc_timer_reg_count_cry_19_ ( + .CI(plm_fsm_rc_timer_reg_count_cry[18]), + .DI(plm_fsm_rc_timer_GND_1014), + .LO(plm_fsm_rc_timer_reg_count_cry[19]), + .S(plm_fsm_rc_timer_reg_count_qxu[19]) + ); + XORCY plm_fsm_rc_timer_reg_count_s_19_ ( + .CI(plm_fsm_rc_timer_reg_count_cry[18]), + .LI(plm_fsm_rc_timer_reg_count_qxu[19]), + .O(plm_fsm_rc_timer_reg_count_s[19]) + ); + MUXCY_L plm_fsm_rc_timer_reg_count_cry_20_ ( + .CI(plm_fsm_rc_timer_reg_count_cry[19]), + .DI(plm_fsm_rc_timer_GND_1014), + .LO(plm_fsm_rc_timer_reg_count_cry[20]), + .S(plm_fsm_rc_timer_reg_count_qxu[20]) + ); + XORCY plm_fsm_rc_timer_reg_count_s_20_ ( + .CI(plm_fsm_rc_timer_reg_count_cry[19]), + .LI(plm_fsm_rc_timer_reg_count_qxu[20]), + .O(plm_fsm_rc_timer_reg_count_s[20]) + ); + MUXCY_L plm_fsm_rc_timer_reg_count_cry_21_ ( + .CI(plm_fsm_rc_timer_reg_count_cry[20]), + .DI(plm_fsm_rc_timer_GND_1014), + .LO(plm_fsm_rc_timer_reg_count_cry[21]), + .S(plm_fsm_rc_timer_reg_count_qxu[21]) + ); + XORCY plm_fsm_rc_timer_reg_count_s_21_ ( + .CI(plm_fsm_rc_timer_reg_count_cry[20]), + .LI(plm_fsm_rc_timer_reg_count_qxu[21]), + .O(plm_fsm_rc_timer_reg_count_s[21]) + ); + XORCY plm_fsm_rc_timer_reg_count_s_22_ ( + .CI(plm_fsm_rc_timer_reg_count_cry[21]), + .LI(plm_fsm_rc_timer_reg_count_qxu[22]), + .O(plm_fsm_rc_timer_reg_count_s[22]) + ); + defparam plm_fsm_rc_timer_count_i_m3_i_m3_0_21_.INIT = 8'hD8; + LUT3_L plm_fsm_rc_timer_count_i_m3_i_m3_0_21_ ( + .I0(cfg_cfg_5072[507]), + .I1(plm_fsm_rc_timer_reg_count[13]), + .I2(plm_fsm_rc_timer_reg_count[21]), + .LO(plm_fsm_rc_timer_N_51441) + ); + defparam plm_fsm_rc_timer_expired_1_0_a2_0_a2_0_a2_0_a4.INIT = 16'hA280; + LUT4 plm_fsm_rc_timer_expired_1_0_a2_0_a2_0_a2_0_a4 ( + .I0(plm_fsm_rc_timer_N_51441), + .I1(cfg_cfg_5072[507]), + .I2(plm_fsm_rc_timer_reg_count[14]), + .I3(plm_fsm_rc_timer_reg_count[22]), + .O(plm_fsm_rc_timeout_1) + ); + FDC plm_fsm_rc_timer_reg_count_22_ ( + .C(mgt_clk), + .D(plm_fsm_rc_timer_reg_count_s[22]), + .Q(plm_fsm_rc_timer_reg_count[22]), + .CLR(plm_rst) + ); + FDC plm_fsm_rc_timer_reg_count_21_ ( + .C(mgt_clk), + .D(plm_fsm_rc_timer_reg_count_s[21]), + .Q(plm_fsm_rc_timer_reg_count[21]), + .CLR(plm_rst) + ); + FDC plm_fsm_rc_timer_reg_count_20_ ( + .C(mgt_clk), + .D(plm_fsm_rc_timer_reg_count_s[20]), + .Q(plm_fsm_rc_timer_reg_count[20]), + .CLR(plm_rst) + ); + FDC plm_fsm_rc_timer_reg_count_19_ ( + .C(mgt_clk), + .D(plm_fsm_rc_timer_reg_count_s[19]), + .Q(plm_fsm_rc_timer_reg_count[19]), + .CLR(plm_rst) + ); + FDC plm_fsm_rc_timer_reg_count_18_ ( + .C(mgt_clk), + .D(plm_fsm_rc_timer_reg_count_s[18]), + .Q(plm_fsm_rc_timer_reg_count[18]), + .CLR(plm_rst) + ); + FDC plm_fsm_rc_timer_reg_count_17_ ( + .C(mgt_clk), + .D(plm_fsm_rc_timer_reg_count_s[17]), + .Q(plm_fsm_rc_timer_reg_count[17]), + .CLR(plm_rst) + ); + FDC plm_fsm_rc_timer_reg_count_16_ ( + .C(mgt_clk), + .D(plm_fsm_rc_timer_reg_count_s[16]), + .Q(plm_fsm_rc_timer_reg_count[16]), + .CLR(plm_rst) + ); + FDC plm_fsm_rc_timer_reg_count_15_ ( + .C(mgt_clk), + .D(plm_fsm_rc_timer_reg_count_s[15]), + .Q(plm_fsm_rc_timer_reg_count[15]), + .CLR(plm_rst) + ); + FDC plm_fsm_rc_timer_reg_count_14_ ( + .C(mgt_clk), + .D(plm_fsm_rc_timer_reg_count_s[14]), + .Q(plm_fsm_rc_timer_reg_count[14]), + .CLR(plm_rst) + ); + FDC plm_fsm_rc_timer_reg_count_13_ ( + .C(mgt_clk), + .D(plm_fsm_rc_timer_reg_count_s[13]), + .Q(plm_fsm_rc_timer_reg_count[13]), + .CLR(plm_rst) + ); + FDC plm_fsm_rc_timer_reg_count_12_ ( + .C(mgt_clk), + .D(plm_fsm_rc_timer_reg_count_s[12]), + .Q(plm_fsm_rc_timer_reg_count[12]), + .CLR(plm_rst) + ); + FDC plm_fsm_rc_timer_reg_count_11_ ( + .C(mgt_clk), + .D(plm_fsm_rc_timer_reg_count_s[11]), + .Q(plm_fsm_rc_timer_reg_count[11]), + .CLR(plm_rst) + ); + FDC plm_fsm_rc_timer_reg_count_10_ ( + .C(mgt_clk), + .D(plm_fsm_rc_timer_reg_count_s[10]), + .Q(plm_fsm_rc_timer_reg_count[10]), + .CLR(plm_rst) + ); + FDC plm_fsm_rc_timer_reg_count_9_ ( + .C(mgt_clk), + .D(plm_fsm_rc_timer_reg_count_s[9]), + .Q(plm_fsm_rc_timer_reg_count[9]), + .CLR(plm_rst) + ); + FDC plm_fsm_rc_timer_reg_count_8_ ( + .C(mgt_clk), + .D(plm_fsm_rc_timer_reg_count_s[8]), + .Q(plm_fsm_rc_timer_reg_count[8]), + .CLR(plm_rst) + ); + FDC plm_fsm_rc_timer_reg_count_7_ ( + .C(mgt_clk), + .D(plm_fsm_rc_timer_reg_count_s[7]), + .Q(plm_fsm_rc_timer_reg_count[7]), + .CLR(plm_rst) + ); + FDC plm_fsm_rc_timer_reg_count_6_ ( + .C(mgt_clk), + .D(plm_fsm_rc_timer_reg_count_s[6]), + .Q(plm_fsm_rc_timer_reg_count[6]), + .CLR(plm_rst) + ); + FDC plm_fsm_rc_timer_reg_count_5_ ( + .C(mgt_clk), + .D(plm_fsm_rc_timer_reg_count_s[5]), + .Q(plm_fsm_rc_timer_reg_count[5]), + .CLR(plm_rst) + ); + FDC plm_fsm_rc_timer_reg_count_4_ ( + .C(mgt_clk), + .D(plm_fsm_rc_timer_reg_count_s[4]), + .Q(plm_fsm_rc_timer_reg_count[4]), + .CLR(plm_rst) + ); + FDC plm_fsm_rc_timer_reg_count_3_ ( + .C(mgt_clk), + .D(plm_fsm_rc_timer_reg_count_s[3]), + .Q(plm_fsm_rc_timer_reg_count[3]), + .CLR(plm_rst) + ); + FDC plm_fsm_rc_timer_reg_count_2_ ( + .C(mgt_clk), + .D(plm_fsm_rc_timer_reg_count_s[2]), + .Q(plm_fsm_rc_timer_reg_count[2]), + .CLR(plm_rst) + ); + FDC plm_fsm_rc_timer_reg_count_1_ ( + .C(mgt_clk), + .D(plm_fsm_rc_timer_reg_count_s[1]), + .Q(plm_fsm_rc_timer_reg_count[1]), + .CLR(plm_rst) + ); + FDC plm_fsm_rc_timer_reg_count_0_ ( + .C(mgt_clk), + .D(plm_fsm_rc_timer_reg_count_s[0]), + .Q(plm_fsm_rc_timer_reg_count[0]), + .CLR(plm_rst) + ); + defparam plm_fsm_rc_timer_reg_count_qxu_0_0_.INIT = 4'h4; + LUT2_L plm_fsm_rc_timer_reg_count_qxu_0_0_ ( + .I0(N_38100_i), + .I1(plm_fsm_rc_timer_reg_count[0]), + .LO(plm_fsm_rc_timer_reg_count_qxu[0]) + ); + defparam plm_fsm_rc_timer_reg_count_qxu_0_1_.INIT = 4'h4; + LUT2_L plm_fsm_rc_timer_reg_count_qxu_0_1_ ( + .I0(N_38100_i), + .I1(plm_fsm_rc_timer_reg_count[1]), + .LO(plm_fsm_rc_timer_reg_count_qxu[1]) + ); + defparam plm_fsm_rc_timer_reg_count_qxu_0_2_.INIT = 4'h4; + LUT2_L plm_fsm_rc_timer_reg_count_qxu_0_2_ ( + .I0(N_38100_i), + .I1(plm_fsm_rc_timer_reg_count[2]), + .LO(plm_fsm_rc_timer_reg_count_qxu[2]) + ); + defparam plm_fsm_rc_timer_reg_count_qxu_0_3_.INIT = 4'h4; + LUT2_L plm_fsm_rc_timer_reg_count_qxu_0_3_ ( + .I0(N_38100_i), + .I1(plm_fsm_rc_timer_reg_count[3]), + .LO(plm_fsm_rc_timer_reg_count_qxu[3]) + ); + defparam plm_fsm_rc_timer_reg_count_qxu_0_4_.INIT = 4'h4; + LUT2_L plm_fsm_rc_timer_reg_count_qxu_0_4_ ( + .I0(N_38100_i), + .I1(plm_fsm_rc_timer_reg_count[4]), + .LO(plm_fsm_rc_timer_reg_count_qxu[4]) + ); + defparam plm_fsm_rc_timer_reg_count_qxu_0_5_.INIT = 4'h4; + LUT2_L plm_fsm_rc_timer_reg_count_qxu_0_5_ ( + .I0(N_38100_i), + .I1(plm_fsm_rc_timer_reg_count[5]), + .LO(plm_fsm_rc_timer_reg_count_qxu[5]) + ); + defparam plm_fsm_rc_timer_reg_count_qxu_0_6_.INIT = 4'h4; + LUT2_L plm_fsm_rc_timer_reg_count_qxu_0_6_ ( + .I0(N_38100_i), + .I1(plm_fsm_rc_timer_reg_count[6]), + .LO(plm_fsm_rc_timer_reg_count_qxu[6]) + ); + defparam plm_fsm_rc_timer_reg_count_qxu_0_7_.INIT = 4'h4; + LUT2_L plm_fsm_rc_timer_reg_count_qxu_0_7_ ( + .I0(N_38100_i), + .I1(plm_fsm_rc_timer_reg_count[7]), + .LO(plm_fsm_rc_timer_reg_count_qxu[7]) + ); + defparam plm_fsm_rc_timer_reg_count_qxu_0_8_.INIT = 4'h4; + LUT2_L plm_fsm_rc_timer_reg_count_qxu_0_8_ ( + .I0(N_38100_i), + .I1(plm_fsm_rc_timer_reg_count[8]), + .LO(plm_fsm_rc_timer_reg_count_qxu[8]) + ); + defparam plm_fsm_rc_timer_reg_count_qxu_0_9_.INIT = 4'h4; + LUT2_L plm_fsm_rc_timer_reg_count_qxu_0_9_ ( + .I0(N_38100_i), + .I1(plm_fsm_rc_timer_reg_count[9]), + .LO(plm_fsm_rc_timer_reg_count_qxu[9]) + ); + defparam plm_fsm_rc_timer_reg_count_qxu_0_10_.INIT = 4'h4; + LUT2_L plm_fsm_rc_timer_reg_count_qxu_0_10_ ( + .I0(N_38100_i), + .I1(plm_fsm_rc_timer_reg_count[10]), + .LO(plm_fsm_rc_timer_reg_count_qxu[10]) + ); + defparam plm_fsm_rc_timer_reg_count_qxu_0_11_.INIT = 4'h4; + LUT2_L plm_fsm_rc_timer_reg_count_qxu_0_11_ ( + .I0(N_38100_i), + .I1(plm_fsm_rc_timer_reg_count[11]), + .LO(plm_fsm_rc_timer_reg_count_qxu[11]) + ); + defparam plm_fsm_rc_timer_reg_count_qxu_0_12_.INIT = 4'h4; + LUT2_L plm_fsm_rc_timer_reg_count_qxu_0_12_ ( + .I0(N_38100_i), + .I1(plm_fsm_rc_timer_reg_count[12]), + .LO(plm_fsm_rc_timer_reg_count_qxu[12]) + ); + defparam plm_fsm_rc_timer_reg_count_qxu_0_13_.INIT = 4'h4; + LUT2_L plm_fsm_rc_timer_reg_count_qxu_0_13_ ( + .I0(N_38100_i), + .I1(plm_fsm_rc_timer_reg_count[13]), + .LO(plm_fsm_rc_timer_reg_count_qxu[13]) + ); + defparam plm_fsm_rc_timer_reg_count_qxu_0_14_.INIT = 4'h4; + LUT2_L plm_fsm_rc_timer_reg_count_qxu_0_14_ ( + .I0(N_38100_i), + .I1(plm_fsm_rc_timer_reg_count[14]), + .LO(plm_fsm_rc_timer_reg_count_qxu[14]) + ); + defparam plm_fsm_rc_timer_reg_count_qxu_0_15_.INIT = 4'h4; + LUT2_L plm_fsm_rc_timer_reg_count_qxu_0_15_ ( + .I0(N_38100_i), + .I1(plm_fsm_rc_timer_reg_count[15]), + .LO(plm_fsm_rc_timer_reg_count_qxu[15]) + ); + defparam plm_fsm_rc_timer_reg_count_qxu_0_16_.INIT = 4'h4; + LUT2_L plm_fsm_rc_timer_reg_count_qxu_0_16_ ( + .I0(N_38100_i), + .I1(plm_fsm_rc_timer_reg_count[16]), + .LO(plm_fsm_rc_timer_reg_count_qxu[16]) + ); + defparam plm_fsm_rc_timer_reg_count_qxu_0_17_.INIT = 4'h4; + LUT2_L plm_fsm_rc_timer_reg_count_qxu_0_17_ ( + .I0(N_38100_i), + .I1(plm_fsm_rc_timer_reg_count[17]), + .LO(plm_fsm_rc_timer_reg_count_qxu[17]) + ); + defparam plm_fsm_rc_timer_reg_count_qxu_0_18_.INIT = 4'h4; + LUT2_L plm_fsm_rc_timer_reg_count_qxu_0_18_ ( + .I0(N_38100_i), + .I1(plm_fsm_rc_timer_reg_count[18]), + .LO(plm_fsm_rc_timer_reg_count_qxu[18]) + ); + defparam plm_fsm_rc_timer_reg_count_qxu_0_19_.INIT = 4'h4; + LUT2_L plm_fsm_rc_timer_reg_count_qxu_0_19_ ( + .I0(N_38100_i), + .I1(plm_fsm_rc_timer_reg_count[19]), + .LO(plm_fsm_rc_timer_reg_count_qxu[19]) + ); + defparam plm_fsm_rc_timer_reg_count_qxu_0_20_.INIT = 4'h4; + LUT2_L plm_fsm_rc_timer_reg_count_qxu_0_20_ ( + .I0(N_38100_i), + .I1(plm_fsm_rc_timer_reg_count[20]), + .LO(plm_fsm_rc_timer_reg_count_qxu[20]) + ); + defparam plm_fsm_rc_timer_reg_count_qxu_0_21_.INIT = 4'h4; + LUT2_L plm_fsm_rc_timer_reg_count_qxu_0_21_ ( + .I0(N_38100_i), + .I1(plm_fsm_rc_timer_reg_count[21]), + .LO(plm_fsm_rc_timer_reg_count_qxu[21]) + ); + defparam plm_fsm_rc_timer_reg_count_qxu_0_22_.INIT = 4'h4; + LUT2_L plm_fsm_rc_timer_reg_count_qxu_0_22_ ( + .I0(N_38100_i), + .I1(plm_fsm_rc_timer_reg_count[22]), + .LO(plm_fsm_rc_timer_reg_count_qxu[22]) + ); + VCC plm_fsm_rc_counter_ts1_0_VCC ( + .P(plm_fsm_rc_counter_ts1_0_VCC_1015) + ); + MUXCY_L plm_fsm_rc_counter_ts1_0_reg_rx_count_cry_0_ ( + .CI(N_18912_i_i_23), + .DI(plm_fsm_rc_counter_ts1_0_VCC_1015), + .LO(plm_fsm_rc_counter_ts1_0_reg_rx_count_cry[0]), + .S(plm_fsm_rc_counter_ts1_0_reg_rx_count_qxu[0]) + ); + XORCY plm_fsm_rc_counter_ts1_0_reg_rx_count_s_0_ ( + .CI(N_18912_i_i_23), + .LI(plm_fsm_rc_counter_ts1_0_reg_rx_count_qxu[0]), + .O(plm_fsm_rc_counter_ts1_0_reg_rx_count_s[0]) + ); + MUXCY_L plm_fsm_rc_counter_ts1_0_reg_rx_count_cry_1_ ( + .CI(plm_fsm_rc_counter_ts1_0_reg_rx_count_cry[0]), + .DI(plm_fsm_rc_counter_ts1_0_VCC_1015), + .LO(plm_fsm_rc_counter_ts1_0_reg_rx_count_cry[1]), + .S(plm_fsm_rc_counter_ts1_0_reg_rx_count_qxu[1]) + ); + XORCY plm_fsm_rc_counter_ts1_0_reg_rx_count_s_1_ ( + .CI(plm_fsm_rc_counter_ts1_0_reg_rx_count_cry[0]), + .LI(plm_fsm_rc_counter_ts1_0_reg_rx_count_qxu[1]), + .O(plm_fsm_rc_counter_ts1_0_reg_rx_count_s[1]) + ); + MUXCY_L plm_fsm_rc_counter_ts1_0_reg_rx_count_cry_2_ ( + .CI(plm_fsm_rc_counter_ts1_0_reg_rx_count_cry[1]), + .DI(plm_fsm_rc_counter_ts1_0_VCC_1015), + .LO(plm_fsm_rc_counter_ts1_0_reg_rx_count_cry[2]), + .S(plm_fsm_rc_counter_ts1_0_reg_rx_count_qxu[2]) + ); + XORCY plm_fsm_rc_counter_ts1_0_reg_rx_count_s_2_ ( + .CI(plm_fsm_rc_counter_ts1_0_reg_rx_count_cry[1]), + .LI(plm_fsm_rc_counter_ts1_0_reg_rx_count_qxu[2]), + .O(plm_fsm_rc_counter_ts1_0_reg_rx_count_s[2]) + ); + MUXCY_L plm_fsm_rc_counter_ts1_0_reg_rx_count_cry_3_ ( + .CI(plm_fsm_rc_counter_ts1_0_reg_rx_count_cry[2]), + .DI(plm_fsm_rc_counter_ts1_0_VCC_1015), + .LO(plm_fsm_rc_counter_ts1_0_reg_rx_count_cry[3]), + .S(plm_fsm_rc_counter_ts1_0_reg_rx_count_qxu[3]) + ); + XORCY plm_fsm_rc_counter_ts1_0_reg_rx_count_s_3_ ( + .CI(plm_fsm_rc_counter_ts1_0_reg_rx_count_cry[2]), + .LI(plm_fsm_rc_counter_ts1_0_reg_rx_count_qxu[3]), + .O(plm_fsm_rc_counter_ts1_0_reg_rx_count_s[3]) + ); + MUXCY_L plm_fsm_rc_counter_ts1_0_reg_rx_count_cry_4_ ( + .CI(plm_fsm_rc_counter_ts1_0_reg_rx_count_cry[3]), + .DI(plm_fsm_rc_counter_ts1_0_VCC_1015), + .LO(plm_fsm_rc_counter_ts1_0_reg_rx_count_cry[4]), + .S(plm_fsm_rc_counter_ts1_0_reg_rx_count_qxu[4]) + ); + XORCY plm_fsm_rc_counter_ts1_0_reg_rx_count_s_4_ ( + .CI(plm_fsm_rc_counter_ts1_0_reg_rx_count_cry[3]), + .LI(plm_fsm_rc_counter_ts1_0_reg_rx_count_qxu[4]), + .O(plm_fsm_rc_counter_ts1_0_reg_rx_count_s[4]) + ); + MUXCY_L plm_fsm_rc_counter_ts1_0_reg_rx_count_cry_5_ ( + .CI(plm_fsm_rc_counter_ts1_0_reg_rx_count_cry[4]), + .DI(plm_fsm_rc_counter_ts1_0_VCC_1015), + .LO(plm_fsm_rc_counter_ts1_0_reg_rx_count_cry[5]), + .S(plm_fsm_rc_counter_ts1_0_reg_rx_count_qxu[5]) + ); + XORCY plm_fsm_rc_counter_ts1_0_reg_rx_count_s_5_ ( + .CI(plm_fsm_rc_counter_ts1_0_reg_rx_count_cry[4]), + .LI(plm_fsm_rc_counter_ts1_0_reg_rx_count_qxu[5]), + .O(plm_fsm_rc_counter_ts1_0_reg_rx_count_s[5]) + ); + MUXCY_L plm_fsm_rc_counter_ts1_0_reg_rx_count_cry_6_ ( + .CI(plm_fsm_rc_counter_ts1_0_reg_rx_count_cry[5]), + .DI(plm_fsm_rc_counter_ts1_0_VCC_1015), + .LO(plm_fsm_rc_counter_ts1_0_reg_rx_count_cry[6]), + .S(plm_fsm_rc_counter_ts1_0_reg_rx_count_qxu[6]) + ); + XORCY plm_fsm_rc_counter_ts1_0_reg_rx_count_s_6_ ( + .CI(plm_fsm_rc_counter_ts1_0_reg_rx_count_cry[5]), + .LI(plm_fsm_rc_counter_ts1_0_reg_rx_count_qxu[6]), + .O(plm_fsm_rc_counter_ts1_0_reg_rx_count_s[6]) + ); + XORCY plm_fsm_rc_counter_ts1_0_reg_rx_count_s_7_ ( + .CI(plm_fsm_rc_counter_ts1_0_reg_rx_count_cry[6]), + .LI(plm_fsm_rc_counter_ts1_0_reg_rx_count_qxu[7]), + .O(plm_fsm_rc_counter_ts1_0_reg_rx_count_s[7]) + ); + MUXCY_L plm_fsm_rc_counter_ts1_0_reg_tx_count_cry_0_ ( + .CI(plm_fsm_rc_counter_ts1_0_N_37210_i_i_1016), + .DI(plm_fsm_rc_counter_ts1_0_VCC_1015), + .LO(plm_fsm_rc_counter_ts1_0_reg_tx_count_cry[0]), + .S(plm_fsm_rc_counter_ts1_0_reg_tx_count_qxu[0]) + ); + XORCY plm_fsm_rc_counter_ts1_0_reg_tx_count_s_0_ ( + .CI(plm_fsm_rc_counter_ts1_0_N_37210_i_i_1016), + .LI(plm_fsm_rc_counter_ts1_0_reg_tx_count_qxu[0]), + .O(plm_fsm_rc_counter_ts1_0_reg_tx_count_s[0]) + ); + MUXCY_L plm_fsm_rc_counter_ts1_0_reg_tx_count_cry_1_ ( + .CI(plm_fsm_rc_counter_ts1_0_reg_tx_count_cry[0]), + .DI(plm_fsm_rc_counter_ts1_0_VCC_1015), + .LO(plm_fsm_rc_counter_ts1_0_reg_tx_count_cry[1]), + .S(plm_fsm_rc_counter_ts1_0_reg_tx_count_qxu[1]) + ); + XORCY plm_fsm_rc_counter_ts1_0_reg_tx_count_s_1_ ( + .CI(plm_fsm_rc_counter_ts1_0_reg_tx_count_cry[0]), + .LI(plm_fsm_rc_counter_ts1_0_reg_tx_count_qxu[1]), + .O(plm_fsm_rc_counter_ts1_0_reg_tx_count_s[1]) + ); + MUXCY_L plm_fsm_rc_counter_ts1_0_reg_tx_count_cry_2_ ( + .CI(plm_fsm_rc_counter_ts1_0_reg_tx_count_cry[1]), + .DI(plm_fsm_rc_counter_ts1_0_VCC_1015), + .LO(plm_fsm_rc_counter_ts1_0_reg_tx_count_cry[2]), + .S(plm_fsm_rc_counter_ts1_0_reg_tx_count_qxu[2]) + ); + XORCY plm_fsm_rc_counter_ts1_0_reg_tx_count_s_2_ ( + .CI(plm_fsm_rc_counter_ts1_0_reg_tx_count_cry[1]), + .LI(plm_fsm_rc_counter_ts1_0_reg_tx_count_qxu[2]), + .O(plm_fsm_rc_counter_ts1_0_reg_tx_count_s[2]) + ); + MUXCY_L plm_fsm_rc_counter_ts1_0_reg_tx_count_cry_3_ ( + .CI(plm_fsm_rc_counter_ts1_0_reg_tx_count_cry[2]), + .DI(plm_fsm_rc_counter_ts1_0_VCC_1015), + .LO(plm_fsm_rc_counter_ts1_0_reg_tx_count_cry[3]), + .S(plm_fsm_rc_counter_ts1_0_reg_tx_count_qxu[3]) + ); + XORCY plm_fsm_rc_counter_ts1_0_reg_tx_count_s_3_ ( + .CI(plm_fsm_rc_counter_ts1_0_reg_tx_count_cry[2]), + .LI(plm_fsm_rc_counter_ts1_0_reg_tx_count_qxu[3]), + .O(plm_fsm_rc_counter_ts1_0_reg_tx_count_s[3]) + ); + MUXCY_L plm_fsm_rc_counter_ts1_0_reg_tx_count_cry_4_ ( + .CI(plm_fsm_rc_counter_ts1_0_reg_tx_count_cry[3]), + .DI(plm_fsm_rc_counter_ts1_0_VCC_1015), + .LO(plm_fsm_rc_counter_ts1_0_reg_tx_count_cry[4]), + .S(plm_fsm_rc_counter_ts1_0_reg_tx_count_qxu[4]) + ); + XORCY plm_fsm_rc_counter_ts1_0_reg_tx_count_s_4_ ( + .CI(plm_fsm_rc_counter_ts1_0_reg_tx_count_cry[3]), + .LI(plm_fsm_rc_counter_ts1_0_reg_tx_count_qxu[4]), + .O(plm_fsm_rc_counter_ts1_0_reg_tx_count_s[4]) + ); + MUXCY_L plm_fsm_rc_counter_ts1_0_reg_tx_count_cry_5_ ( + .CI(plm_fsm_rc_counter_ts1_0_reg_tx_count_cry[4]), + .DI(plm_fsm_rc_counter_ts1_0_VCC_1015), + .LO(plm_fsm_rc_counter_ts1_0_reg_tx_count_cry[5]), + .S(plm_fsm_rc_counter_ts1_0_reg_tx_count_qxu[5]) + ); + XORCY plm_fsm_rc_counter_ts1_0_reg_tx_count_s_5_ ( + .CI(plm_fsm_rc_counter_ts1_0_reg_tx_count_cry[4]), + .LI(plm_fsm_rc_counter_ts1_0_reg_tx_count_qxu[5]), + .O(plm_fsm_rc_counter_ts1_0_reg_tx_count_s[5]) + ); + MUXCY_L plm_fsm_rc_counter_ts1_0_reg_tx_count_cry_6_ ( + .CI(plm_fsm_rc_counter_ts1_0_reg_tx_count_cry[5]), + .DI(plm_fsm_rc_counter_ts1_0_VCC_1015), + .LO(plm_fsm_rc_counter_ts1_0_reg_tx_count_cry[6]), + .S(plm_fsm_rc_counter_ts1_0_reg_tx_count_qxu[6]) + ); + XORCY plm_fsm_rc_counter_ts1_0_reg_tx_count_s_6_ ( + .CI(plm_fsm_rc_counter_ts1_0_reg_tx_count_cry[5]), + .LI(plm_fsm_rc_counter_ts1_0_reg_tx_count_qxu[6]), + .O(plm_fsm_rc_counter_ts1_0_reg_tx_count_s[6]) + ); + XORCY plm_fsm_rc_counter_ts1_0_reg_tx_count_s_7_ ( + .CI(plm_fsm_rc_counter_ts1_0_reg_tx_count_cry[6]), + .LI(plm_fsm_rc_counter_ts1_0_reg_tx_count_qxu[7]), + .O(plm_fsm_rc_counter_ts1_0_reg_tx_count_s[7]) + ); + defparam plm_fsm_rc_counter_ts1_0_un1_enable_4_i_0_0_a4_0_1.INIT = 4'h2; + LUT2 plm_fsm_rc_counter_ts1_0_un1_enable_4_i_0_0_a4_0_1 ( + .I0(plm_reg_ts1_1), + .I1(plm_fsm_rc_counter_ts1_0_reg_rx_expired_252), + .O(plm_fsm_rc_counter_ts1_0_N_38438_1) + ); + defparam plm_fsm_rc_counter_ts1_0_un1_enable_1_0_a2_0_a2_i_o4.INIT = 4'h4; + LUT2 plm_fsm_rc_counter_ts1_0_un1_enable_1_0_a2_0_a2_i_o4 ( + .I0(N_38100_i), + .I1(plm_fsm_rc_counter_ts1_0_reg_oneshot_1018), + .O(plm_fsm_rc_counter_ts1_0_N_38369_i) + ); + defparam plm_fsm_rc_counter_ts1_0_loadable_tx_counter_un1_reg_tx_count_0_a2_4.INIT = 16'h0001; + LUT4 plm_fsm_rc_counter_ts1_0_loadable_tx_counter_un1_reg_tx_count_0_a2_4 ( + .I0(plm_fsm_rc_counter_ts1_0_reg_tx_count[0]), + .I1(plm_fsm_rc_counter_ts1_0_reg_tx_count[1]), + .I2(plm_fsm_rc_counter_ts1_0_reg_tx_count[2]), + .I3(plm_fsm_rc_counter_ts1_0_reg_tx_count[3]), + .O(plm_fsm_rc_counter_ts1_0_un1_reg_tx_count_0_a2_4) + ); + defparam plm_fsm_rc_counter_ts1_0_loadable_tx_counter_un1_reg_tx_count_0_a2_5.INIT = 16'h0001; + LUT4 plm_fsm_rc_counter_ts1_0_loadable_tx_counter_un1_reg_tx_count_0_a2_5 ( + .I0(plm_fsm_rc_counter_ts1_0_reg_tx_count[4]), + .I1(plm_fsm_rc_counter_ts1_0_reg_tx_count[5]), + .I2(plm_fsm_rc_counter_ts1_0_reg_tx_count[6]), + .I3(plm_fsm_rc_counter_ts1_0_reg_tx_count[7]), + .O(plm_fsm_rc_counter_ts1_0_un1_reg_tx_count_0_a2_5) + ); + defparam plm_fsm_rc_counter_ts1_0_loadable_rx_counter_un1_reg_rx_count_0_a2_4.INIT = 16'h0001; + LUT4 plm_fsm_rc_counter_ts1_0_loadable_rx_counter_un1_reg_rx_count_0_a2_4 ( + .I0(plm_fsm_rc_counter_ts1_0_reg_rx_count[0]), + .I1(plm_fsm_rc_counter_ts1_0_reg_rx_count[1]), + .I2(plm_fsm_rc_counter_ts1_0_reg_rx_count[2]), + .I3(plm_fsm_rc_counter_ts1_0_reg_rx_count[3]), + .O(plm_fsm_rc_counter_ts1_0_un1_reg_rx_count_0_a2_4) + ); + defparam plm_fsm_rc_counter_ts1_0_loadable_rx_counter_un1_reg_rx_count_0_a2_5.INIT = 16'h0001; + LUT4 plm_fsm_rc_counter_ts1_0_loadable_rx_counter_un1_reg_rx_count_0_a2_5 ( + .I0(plm_fsm_rc_counter_ts1_0_reg_rx_count[4]), + .I1(plm_fsm_rc_counter_ts1_0_reg_rx_count[5]), + .I2(plm_fsm_rc_counter_ts1_0_reg_rx_count[6]), + .I3(plm_fsm_rc_counter_ts1_0_reg_rx_count[7]), + .O(plm_fsm_rc_counter_ts1_0_un1_reg_rx_count_0_a2_5) + ); + defparam plm_fsm_rc_counter_ts1_0_oneshot_monitor_N_69125_i.INIT = 4'hE; + LUT2 plm_fsm_rc_counter_ts1_0_oneshot_monitor_N_69125_i ( + .I0(plm_reg_ts1_1), + .I1(N_38100_i), + .O(plm_fsm_rc_counter_ts1_0_N_69125_i) + ); + defparam plm_fsm_rc_counter_ts1_0_un1_enable_1_0_a2_0_a2_i.INIT = 4'h2; + LUT2 plm_fsm_rc_counter_ts1_0_un1_enable_1_0_a2_0_a2_i ( + .I0(plm_fsm_rc_counter_ts1_0_N_38369_i), + .I1(plm_fsm_rc_counter_ts1_0_reg_tx_expired_1020), + .O(plm_fsm_rc_counter_ts1_0_N_37210_i) + ); + defparam plm_fsm_rc_counter_ts1_0_loadable_rx_counter_N_69223_i.INIT = 8'hFE; + LUT3 plm_fsm_rc_counter_ts1_0_loadable_rx_counter_N_69223_i ( + .I0(plm_reg_ts1_1), + .I1(N_38100_i), + .I2(plm_fsm_rc_counter_ts1_0_reg_rx_expired_252), + .O(plm_fsm_rc_counter_ts1_0_N_69223_i) + ); + defparam plm_fsm_rc_counter_ts1_0_N_69101_i.INIT = 8'hD5; + LUT3 plm_fsm_rc_counter_ts1_0_N_69101_i ( + .I0(plm_fsm_rc_counter_ts1_0_N_38369_i), + .I1(plm_fsm_rc_counter_ts1_0_un1_reg_tx_count_0_a2_4), + .I2(plm_fsm_rc_counter_ts1_0_un1_reg_tx_count_0_a2_5), + .O(plm_fsm_rc_counter_ts1_0_N_69101_i_1019) + ); + defparam plm_fsm_rc_counter_ts1_0_loadable_rx_counter_N_69114_i.INIT = 8'hEA; + LUT3 plm_fsm_rc_counter_ts1_0_loadable_rx_counter_N_69114_i ( + .I0(N_38100_i), + .I1(plm_fsm_rc_counter_ts1_0_un1_reg_rx_count_0_a2_4), + .I2(plm_fsm_rc_counter_ts1_0_un1_reg_rx_count_0_a2_5), + .O(plm_fsm_rc_counter_ts1_0_N_69114_i) + ); + defparam plm_fsm_rc_counter_ts1_0_N_69277_i.INIT = 4'hB; + LUT2 plm_fsm_rc_counter_ts1_0_N_69277_i ( + .I0(plm_reg_sym_sent_6_), + .I1(plm_fsm_rc_counter_ts1_0_N_37210_i), + .O(plm_fsm_rc_counter_ts1_0_N_69277_i_1017) + ); + defparam plm_fsm_rc_counter_ts1_0_N_67861_i.INIT = 16'hEAFA; + LUT4 plm_fsm_rc_counter_ts1_0_N_67861_i ( + .I0(N_38100_i), + .I1(N_38124_i), + .I2(plm_fsm_rc_counter_ts1_0_N_38438_1), + .I3(plm_rx0_ts1_c), + .O(plm_fsm_rc_counter_ts1_0_N_67861_i_1021) + ); + defparam plm_fsm_rc_counter_ts1_0_flagit_reg_expired_5_0_a2_0_a2_i.INIT = 8'h40; + LUT3_L plm_fsm_rc_counter_ts1_0_flagit_reg_expired_5_0_a2_0_a2_i ( + .I0(N_38100_i), + .I1(plm_fsm_rc_counter_ts1_0_reg_rx_expired_252), + .I2(plm_fsm_rc_counter_ts1_0_reg_tx_expired_1020), + .LO(plm_fsm_rc_counter_ts1_0_N_37299_i) + ); + defparam plm_fsm_rc_counter_ts1_0_N_37210_i_i.INIT = 4'hB; + LUT2 plm_fsm_rc_counter_ts1_0_N_37210_i_i ( + .I0(plm_fsm_rc_counter_ts1_0_reg_tx_expired_1020), + .I1(plm_fsm_rc_counter_ts1_0_N_38369_i), + .O(plm_fsm_rc_counter_ts1_0_N_37210_i_i_1016) + ); + FDCE plm_fsm_rc_counter_ts1_0_reg_tx_count_7_ ( + .CE(plm_fsm_rc_counter_ts1_0_N_69277_i_1017), + .C(mgt_clk), + .D(plm_fsm_rc_counter_ts1_0_reg_tx_count_s[7]), + .Q(plm_fsm_rc_counter_ts1_0_reg_tx_count[7]), + .CLR(plm_rst) + ); + FDCE plm_fsm_rc_counter_ts1_0_reg_tx_count_6_ ( + .CE(plm_fsm_rc_counter_ts1_0_N_69277_i_1017), + .C(mgt_clk), + .D(plm_fsm_rc_counter_ts1_0_reg_tx_count_s[6]), + .Q(plm_fsm_rc_counter_ts1_0_reg_tx_count[6]), + .CLR(plm_rst) + ); + FDCE plm_fsm_rc_counter_ts1_0_reg_tx_count_5_ ( + .CE(plm_fsm_rc_counter_ts1_0_N_69277_i_1017), + .C(mgt_clk), + .D(plm_fsm_rc_counter_ts1_0_reg_tx_count_s[5]), + .Q(plm_fsm_rc_counter_ts1_0_reg_tx_count[5]), + .CLR(plm_rst) + ); + FDPE plm_fsm_rc_counter_ts1_0_reg_tx_count_4_ ( + .PRE(plm_rst), + .CE(plm_fsm_rc_counter_ts1_0_N_69277_i_1017), + .C(mgt_clk), + .D(plm_fsm_rc_counter_ts1_0_reg_tx_count_s[4]), + .Q(plm_fsm_rc_counter_ts1_0_reg_tx_count[4]) + ); + FDCE plm_fsm_rc_counter_ts1_0_reg_tx_count_3_ ( + .CE(plm_fsm_rc_counter_ts1_0_N_69277_i_1017), + .C(mgt_clk), + .D(plm_fsm_rc_counter_ts1_0_reg_tx_count_s[3]), + .Q(plm_fsm_rc_counter_ts1_0_reg_tx_count[3]), + .CLR(plm_rst) + ); + FDCE plm_fsm_rc_counter_ts1_0_reg_tx_count_2_ ( + .CE(plm_fsm_rc_counter_ts1_0_N_69277_i_1017), + .C(mgt_clk), + .D(plm_fsm_rc_counter_ts1_0_reg_tx_count_s[2]), + .Q(plm_fsm_rc_counter_ts1_0_reg_tx_count[2]), + .CLR(plm_rst) + ); + FDCE plm_fsm_rc_counter_ts1_0_reg_tx_count_1_ ( + .CE(plm_fsm_rc_counter_ts1_0_N_69277_i_1017), + .C(mgt_clk), + .D(plm_fsm_rc_counter_ts1_0_reg_tx_count_s[1]), + .Q(plm_fsm_rc_counter_ts1_0_reg_tx_count[1]), + .CLR(plm_rst) + ); + FDCE plm_fsm_rc_counter_ts1_0_reg_tx_count_0_ ( + .CE(plm_fsm_rc_counter_ts1_0_N_69277_i_1017), + .C(mgt_clk), + .D(plm_fsm_rc_counter_ts1_0_reg_tx_count_s[0]), + .Q(plm_fsm_rc_counter_ts1_0_reg_tx_count[0]), + .CLR(plm_rst) + ); + FDCE plm_fsm_rc_counter_ts1_0_reg_rx_count_7_ ( + .CE(plm_fsm_rc_counter_ts1_0_N_69223_i), + .C(mgt_clk), + .D(plm_fsm_rc_counter_ts1_0_reg_rx_count_s[7]), + .Q(plm_fsm_rc_counter_ts1_0_reg_rx_count[7]), + .CLR(plm_rst) + ); + FDCE plm_fsm_rc_counter_ts1_0_reg_rx_count_6_ ( + .CE(plm_fsm_rc_counter_ts1_0_N_69223_i), + .C(mgt_clk), + .D(plm_fsm_rc_counter_ts1_0_reg_rx_count_s[6]), + .Q(plm_fsm_rc_counter_ts1_0_reg_rx_count[6]), + .CLR(plm_rst) + ); + FDCE plm_fsm_rc_counter_ts1_0_reg_rx_count_5_ ( + .CE(plm_fsm_rc_counter_ts1_0_N_69223_i), + .C(mgt_clk), + .D(plm_fsm_rc_counter_ts1_0_reg_rx_count_s[5]), + .Q(plm_fsm_rc_counter_ts1_0_reg_rx_count[5]), + .CLR(plm_rst) + ); + FDCE plm_fsm_rc_counter_ts1_0_reg_rx_count_4_ ( + .CE(plm_fsm_rc_counter_ts1_0_N_69223_i), + .C(mgt_clk), + .D(plm_fsm_rc_counter_ts1_0_reg_rx_count_s[4]), + .Q(plm_fsm_rc_counter_ts1_0_reg_rx_count[4]), + .CLR(plm_rst) + ); + FDPE plm_fsm_rc_counter_ts1_0_reg_rx_count_3_ ( + .PRE(plm_rst), + .CE(plm_fsm_rc_counter_ts1_0_N_69223_i), + .C(mgt_clk), + .D(plm_fsm_rc_counter_ts1_0_reg_rx_count_s[3]), + .Q(plm_fsm_rc_counter_ts1_0_reg_rx_count[3]) + ); + FDCE plm_fsm_rc_counter_ts1_0_reg_rx_count_2_ ( + .CE(plm_fsm_rc_counter_ts1_0_N_69223_i), + .C(mgt_clk), + .D(plm_fsm_rc_counter_ts1_0_reg_rx_count_s[2]), + .Q(plm_fsm_rc_counter_ts1_0_reg_rx_count[2]), + .CLR(plm_rst) + ); + FDCE plm_fsm_rc_counter_ts1_0_reg_rx_count_1_ ( + .CE(plm_fsm_rc_counter_ts1_0_N_69223_i), + .C(mgt_clk), + .D(plm_fsm_rc_counter_ts1_0_reg_rx_count_s[1]), + .Q(plm_fsm_rc_counter_ts1_0_reg_rx_count[1]), + .CLR(plm_rst) + ); + FDCE plm_fsm_rc_counter_ts1_0_reg_rx_count_0_ ( + .CE(plm_fsm_rc_counter_ts1_0_N_69223_i), + .C(mgt_clk), + .D(plm_fsm_rc_counter_ts1_0_reg_rx_count_s[0]), + .Q(plm_fsm_rc_counter_ts1_0_reg_rx_count[0]), + .CLR(plm_rst) + ); + FDC plm_fsm_rc_counter_ts1_0_reg_expired ( + .C(mgt_clk), + .D(plm_fsm_rc_counter_ts1_0_N_37299_i), + .Q(plm_fsm_reg_expired), + .CLR(plm_rst) + ); + FDCE plm_fsm_rc_counter_ts1_0_reg_oneshot ( + .CE(plm_fsm_rc_counter_ts1_0_N_69125_i), + .C(mgt_clk), + .D(plm_fsm_N_38100_i_i), + .Q(plm_fsm_rc_counter_ts1_0_reg_oneshot_1018), + .CLR(plm_rst) + ); + FDCE plm_fsm_rc_counter_ts1_0_reg_rx_expired ( + .CE(plm_fsm_rc_counter_ts1_0_N_69114_i), + .C(mgt_clk), + .D(plm_fsm_N_38100_i_i), + .Q(plm_fsm_rc_counter_ts1_0_reg_rx_expired_252), + .CLR(plm_rst) + ); + FDCE plm_fsm_rc_counter_ts1_0_reg_tx_expired ( + .CE(plm_fsm_rc_counter_ts1_0_N_69101_i_1019), + .C(mgt_clk), + .D(plm_fsm_rc_counter_ts1_0_N_38369_i), + .Q(plm_fsm_rc_counter_ts1_0_reg_tx_expired_1020), + .CLR(plm_rst) + ); + defparam plm_fsm_rc_counter_ts1_0_reg_rx_count_qxu_0_0_.INIT = 4'h7; + LUT2_L plm_fsm_rc_counter_ts1_0_reg_rx_count_qxu_0_0_ ( + .I0(N_18912_i), + .I1(plm_fsm_rc_counter_ts1_0_reg_rx_count[0]), + .LO(plm_fsm_rc_counter_ts1_0_reg_rx_count_qxu[0]) + ); + defparam plm_fsm_rc_counter_ts1_0_reg_rx_count_qxu_0_1_.INIT = 4'h7; + LUT2_L plm_fsm_rc_counter_ts1_0_reg_rx_count_qxu_0_1_ ( + .I0(N_18912_i), + .I1(plm_fsm_rc_counter_ts1_0_reg_rx_count[1]), + .LO(plm_fsm_rc_counter_ts1_0_reg_rx_count_qxu[1]) + ); + defparam plm_fsm_rc_counter_ts1_0_reg_rx_count_qxu_0_2_.INIT = 4'h7; + LUT2_L plm_fsm_rc_counter_ts1_0_reg_rx_count_qxu_0_2_ ( + .I0(N_18912_i), + .I1(plm_fsm_rc_counter_ts1_0_reg_rx_count[2]), + .LO(plm_fsm_rc_counter_ts1_0_reg_rx_count_qxu[2]) + ); + defparam plm_fsm_rc_counter_ts1_0_reg_rx_count_qxu_0_3_.INIT = 8'h1B; + LUT3_L plm_fsm_rc_counter_ts1_0_reg_rx_count_qxu_0_3_ ( + .I0(N_18912_i), + .I1(plm_fsm_rc_counter_ts1_0_N_67861_i_1021), + .I2(plm_fsm_rc_counter_ts1_0_reg_rx_count[3]), + .LO(plm_fsm_rc_counter_ts1_0_reg_rx_count_qxu[3]) + ); + defparam plm_fsm_rc_counter_ts1_0_reg_rx_count_qxu_0_4_.INIT = 4'h7; + LUT2_L plm_fsm_rc_counter_ts1_0_reg_rx_count_qxu_0_4_ ( + .I0(N_18912_i), + .I1(plm_fsm_rc_counter_ts1_0_reg_rx_count[4]), + .LO(plm_fsm_rc_counter_ts1_0_reg_rx_count_qxu[4]) + ); + defparam plm_fsm_rc_counter_ts1_0_reg_rx_count_qxu_0_5_.INIT = 4'h7; + LUT2_L plm_fsm_rc_counter_ts1_0_reg_rx_count_qxu_0_5_ ( + .I0(N_18912_i), + .I1(plm_fsm_rc_counter_ts1_0_reg_rx_count[5]), + .LO(plm_fsm_rc_counter_ts1_0_reg_rx_count_qxu[5]) + ); + defparam plm_fsm_rc_counter_ts1_0_reg_rx_count_qxu_0_6_.INIT = 4'h7; + LUT2_L plm_fsm_rc_counter_ts1_0_reg_rx_count_qxu_0_6_ ( + .I0(N_18912_i), + .I1(plm_fsm_rc_counter_ts1_0_reg_rx_count[6]), + .LO(plm_fsm_rc_counter_ts1_0_reg_rx_count_qxu[6]) + ); + defparam plm_fsm_rc_counter_ts1_0_reg_rx_count_qxu_0_7_.INIT = 4'h7; + LUT2_L plm_fsm_rc_counter_ts1_0_reg_rx_count_qxu_0_7_ ( + .I0(N_18912_i), + .I1(plm_fsm_rc_counter_ts1_0_reg_rx_count[7]), + .LO(plm_fsm_rc_counter_ts1_0_reg_rx_count_qxu[7]) + ); + defparam plm_fsm_rc_counter_ts1_0_reg_tx_count_qxu_0_0_.INIT = 4'h7; + LUT2_L plm_fsm_rc_counter_ts1_0_reg_tx_count_qxu_0_0_ ( + .I0(plm_fsm_rc_counter_ts1_0_N_37210_i), + .I1(plm_fsm_rc_counter_ts1_0_reg_tx_count[0]), + .LO(plm_fsm_rc_counter_ts1_0_reg_tx_count_qxu[0]) + ); + defparam plm_fsm_rc_counter_ts1_0_reg_tx_count_qxu_0_1_.INIT = 4'h7; + LUT2_L plm_fsm_rc_counter_ts1_0_reg_tx_count_qxu_0_1_ ( + .I0(plm_fsm_rc_counter_ts1_0_N_37210_i), + .I1(plm_fsm_rc_counter_ts1_0_reg_tx_count[1]), + .LO(plm_fsm_rc_counter_ts1_0_reg_tx_count_qxu[1]) + ); + defparam plm_fsm_rc_counter_ts1_0_reg_tx_count_qxu_0_2_.INIT = 4'h7; + LUT2_L plm_fsm_rc_counter_ts1_0_reg_tx_count_qxu_0_2_ ( + .I0(plm_fsm_rc_counter_ts1_0_N_37210_i), + .I1(plm_fsm_rc_counter_ts1_0_reg_tx_count[2]), + .LO(plm_fsm_rc_counter_ts1_0_reg_tx_count_qxu[2]) + ); + defparam plm_fsm_rc_counter_ts1_0_reg_tx_count_qxu_0_3_.INIT = 4'h7; + LUT2_L plm_fsm_rc_counter_ts1_0_reg_tx_count_qxu_0_3_ ( + .I0(plm_fsm_rc_counter_ts1_0_N_37210_i), + .I1(plm_fsm_rc_counter_ts1_0_reg_tx_count[3]), + .LO(plm_fsm_rc_counter_ts1_0_reg_tx_count_qxu[3]) + ); + defparam plm_fsm_rc_counter_ts1_0_reg_tx_count_qxu_0_4_.INIT = 8'h4E; + LUT3_L plm_fsm_rc_counter_ts1_0_reg_tx_count_qxu_0_4_ ( + .I0(plm_fsm_rc_counter_ts1_0_N_37210_i), + .I1(plm_fsm_rc_counter_ts1_0_N_38369_i), + .I2(plm_fsm_rc_counter_ts1_0_reg_tx_count[4]), + .LO(plm_fsm_rc_counter_ts1_0_reg_tx_count_qxu[4]) + ); + defparam plm_fsm_rc_counter_ts1_0_reg_tx_count_qxu_0_5_.INIT = 4'h7; + LUT2_L plm_fsm_rc_counter_ts1_0_reg_tx_count_qxu_0_5_ ( + .I0(plm_fsm_rc_counter_ts1_0_N_37210_i), + .I1(plm_fsm_rc_counter_ts1_0_reg_tx_count[5]), + .LO(plm_fsm_rc_counter_ts1_0_reg_tx_count_qxu[5]) + ); + defparam plm_fsm_rc_counter_ts1_0_reg_tx_count_qxu_0_6_.INIT = 4'h7; + LUT2_L plm_fsm_rc_counter_ts1_0_reg_tx_count_qxu_0_6_ ( + .I0(plm_fsm_rc_counter_ts1_0_N_37210_i), + .I1(plm_fsm_rc_counter_ts1_0_reg_tx_count[6]), + .LO(plm_fsm_rc_counter_ts1_0_reg_tx_count_qxu[6]) + ); + defparam plm_fsm_rc_counter_ts1_0_reg_tx_count_qxu_0_7_.INIT = 4'h7; + LUT2_L plm_fsm_rc_counter_ts1_0_reg_tx_count_qxu_0_7_ ( + .I0(plm_fsm_rc_counter_ts1_0_N_37210_i), + .I1(plm_fsm_rc_counter_ts1_0_reg_tx_count[7]), + .LO(plm_fsm_rc_counter_ts1_0_reg_tx_count_qxu[7]) + ); + VCC plm_fsm_rc_counter_ts2_0_VCC ( + .P(plm_fsm_rc_counter_ts2_0_VCC_1022) + ); + MUXCY_L plm_fsm_rc_counter_ts2_0_reg_rx_count_cry_0_ ( + .CI(N_37268_i_i_22), + .DI(plm_fsm_rc_counter_ts2_0_VCC_1022), + .LO(plm_fsm_rc_counter_ts2_0_reg_rx_count_cry[0]), + .S(plm_fsm_rc_counter_ts2_0_reg_rx_count_qxu[0]) + ); + XORCY plm_fsm_rc_counter_ts2_0_reg_rx_count_s_0_ ( + .CI(N_37268_i_i_22), + .LI(plm_fsm_rc_counter_ts2_0_reg_rx_count_qxu[0]), + .O(plm_fsm_rc_counter_ts2_0_reg_rx_count_s[0]) + ); + MUXCY_L plm_fsm_rc_counter_ts2_0_reg_rx_count_cry_1_ ( + .CI(plm_fsm_rc_counter_ts2_0_reg_rx_count_cry[0]), + .DI(plm_fsm_rc_counter_ts2_0_VCC_1022), + .LO(plm_fsm_rc_counter_ts2_0_reg_rx_count_cry[1]), + .S(plm_fsm_rc_counter_ts2_0_reg_rx_count_qxu[1]) + ); + XORCY plm_fsm_rc_counter_ts2_0_reg_rx_count_s_1_ ( + .CI(plm_fsm_rc_counter_ts2_0_reg_rx_count_cry[0]), + .LI(plm_fsm_rc_counter_ts2_0_reg_rx_count_qxu[1]), + .O(plm_fsm_rc_counter_ts2_0_reg_rx_count_s[1]) + ); + MUXCY_L plm_fsm_rc_counter_ts2_0_reg_rx_count_cry_2_ ( + .CI(plm_fsm_rc_counter_ts2_0_reg_rx_count_cry[1]), + .DI(plm_fsm_rc_counter_ts2_0_VCC_1022), + .LO(plm_fsm_rc_counter_ts2_0_reg_rx_count_cry[2]), + .S(plm_fsm_rc_counter_ts2_0_reg_rx_count_qxu[2]) + ); + XORCY plm_fsm_rc_counter_ts2_0_reg_rx_count_s_2_ ( + .CI(plm_fsm_rc_counter_ts2_0_reg_rx_count_cry[1]), + .LI(plm_fsm_rc_counter_ts2_0_reg_rx_count_qxu[2]), + .O(plm_fsm_rc_counter_ts2_0_reg_rx_count_s[2]) + ); + MUXCY_L plm_fsm_rc_counter_ts2_0_reg_rx_count_cry_3_ ( + .CI(plm_fsm_rc_counter_ts2_0_reg_rx_count_cry[2]), + .DI(plm_fsm_rc_counter_ts2_0_VCC_1022), + .LO(plm_fsm_rc_counter_ts2_0_reg_rx_count_cry[3]), + .S(plm_fsm_rc_counter_ts2_0_reg_rx_count_qxu[3]) + ); + XORCY plm_fsm_rc_counter_ts2_0_reg_rx_count_s_3_ ( + .CI(plm_fsm_rc_counter_ts2_0_reg_rx_count_cry[2]), + .LI(plm_fsm_rc_counter_ts2_0_reg_rx_count_qxu[3]), + .O(plm_fsm_rc_counter_ts2_0_reg_rx_count_s[3]) + ); + MUXCY_L plm_fsm_rc_counter_ts2_0_reg_rx_count_cry_4_ ( + .CI(plm_fsm_rc_counter_ts2_0_reg_rx_count_cry[3]), + .DI(plm_fsm_rc_counter_ts2_0_VCC_1022), + .LO(plm_fsm_rc_counter_ts2_0_reg_rx_count_cry[4]), + .S(plm_fsm_rc_counter_ts2_0_reg_rx_count_qxu[4]) + ); + XORCY plm_fsm_rc_counter_ts2_0_reg_rx_count_s_4_ ( + .CI(plm_fsm_rc_counter_ts2_0_reg_rx_count_cry[3]), + .LI(plm_fsm_rc_counter_ts2_0_reg_rx_count_qxu[4]), + .O(plm_fsm_rc_counter_ts2_0_reg_rx_count_s[4]) + ); + MUXCY_L plm_fsm_rc_counter_ts2_0_reg_rx_count_cry_5_ ( + .CI(plm_fsm_rc_counter_ts2_0_reg_rx_count_cry[4]), + .DI(plm_fsm_rc_counter_ts2_0_VCC_1022), + .LO(plm_fsm_rc_counter_ts2_0_reg_rx_count_cry[5]), + .S(plm_fsm_rc_counter_ts2_0_reg_rx_count_qxu[5]) + ); + XORCY plm_fsm_rc_counter_ts2_0_reg_rx_count_s_5_ ( + .CI(plm_fsm_rc_counter_ts2_0_reg_rx_count_cry[4]), + .LI(plm_fsm_rc_counter_ts2_0_reg_rx_count_qxu[5]), + .O(plm_fsm_rc_counter_ts2_0_reg_rx_count_s[5]) + ); + MUXCY_L plm_fsm_rc_counter_ts2_0_reg_rx_count_cry_6_ ( + .CI(plm_fsm_rc_counter_ts2_0_reg_rx_count_cry[5]), + .DI(plm_fsm_rc_counter_ts2_0_VCC_1022), + .LO(plm_fsm_rc_counter_ts2_0_reg_rx_count_cry[6]), + .S(plm_fsm_rc_counter_ts2_0_reg_rx_count_qxu[6]) + ); + XORCY plm_fsm_rc_counter_ts2_0_reg_rx_count_s_6_ ( + .CI(plm_fsm_rc_counter_ts2_0_reg_rx_count_cry[5]), + .LI(plm_fsm_rc_counter_ts2_0_reg_rx_count_qxu[6]), + .O(plm_fsm_rc_counter_ts2_0_reg_rx_count_s[6]) + ); + XORCY plm_fsm_rc_counter_ts2_0_reg_rx_count_s_7_ ( + .CI(plm_fsm_rc_counter_ts2_0_reg_rx_count_cry[6]), + .LI(plm_fsm_rc_counter_ts2_0_reg_rx_count_qxu[7]), + .O(plm_fsm_rc_counter_ts2_0_reg_rx_count_s[7]) + ); + MUXCY_L plm_fsm_rc_counter_ts2_0_reg_tx_count_cry_0_ ( + .CI(plm_fsm_rc_counter_ts2_0_N_37194_i_i_1023), + .DI(plm_fsm_rc_counter_ts2_0_VCC_1022), + .LO(plm_fsm_rc_counter_ts2_0_reg_tx_count_cry[0]), + .S(plm_fsm_rc_counter_ts2_0_reg_tx_count_qxu[0]) + ); + XORCY plm_fsm_rc_counter_ts2_0_reg_tx_count_s_0_ ( + .CI(plm_fsm_rc_counter_ts2_0_N_37194_i_i_1023), + .LI(plm_fsm_rc_counter_ts2_0_reg_tx_count_qxu[0]), + .O(plm_fsm_rc_counter_ts2_0_reg_tx_count_s[0]) + ); + MUXCY_L plm_fsm_rc_counter_ts2_0_reg_tx_count_cry_1_ ( + .CI(plm_fsm_rc_counter_ts2_0_reg_tx_count_cry[0]), + .DI(plm_fsm_rc_counter_ts2_0_VCC_1022), + .LO(plm_fsm_rc_counter_ts2_0_reg_tx_count_cry[1]), + .S(plm_fsm_rc_counter_ts2_0_reg_tx_count_qxu[1]) + ); + XORCY plm_fsm_rc_counter_ts2_0_reg_tx_count_s_1_ ( + .CI(plm_fsm_rc_counter_ts2_0_reg_tx_count_cry[0]), + .LI(plm_fsm_rc_counter_ts2_0_reg_tx_count_qxu[1]), + .O(plm_fsm_rc_counter_ts2_0_reg_tx_count_s[1]) + ); + MUXCY_L plm_fsm_rc_counter_ts2_0_reg_tx_count_cry_2_ ( + .CI(plm_fsm_rc_counter_ts2_0_reg_tx_count_cry[1]), + .DI(plm_fsm_rc_counter_ts2_0_VCC_1022), + .LO(plm_fsm_rc_counter_ts2_0_reg_tx_count_cry[2]), + .S(plm_fsm_rc_counter_ts2_0_reg_tx_count_qxu[2]) + ); + XORCY plm_fsm_rc_counter_ts2_0_reg_tx_count_s_2_ ( + .CI(plm_fsm_rc_counter_ts2_0_reg_tx_count_cry[1]), + .LI(plm_fsm_rc_counter_ts2_0_reg_tx_count_qxu[2]), + .O(plm_fsm_rc_counter_ts2_0_reg_tx_count_s[2]) + ); + MUXCY_L plm_fsm_rc_counter_ts2_0_reg_tx_count_cry_3_ ( + .CI(plm_fsm_rc_counter_ts2_0_reg_tx_count_cry[2]), + .DI(plm_fsm_rc_counter_ts2_0_VCC_1022), + .LO(plm_fsm_rc_counter_ts2_0_reg_tx_count_cry[3]), + .S(plm_fsm_rc_counter_ts2_0_reg_tx_count_qxu[3]) + ); + XORCY plm_fsm_rc_counter_ts2_0_reg_tx_count_s_3_ ( + .CI(plm_fsm_rc_counter_ts2_0_reg_tx_count_cry[2]), + .LI(plm_fsm_rc_counter_ts2_0_reg_tx_count_qxu[3]), + .O(plm_fsm_rc_counter_ts2_0_reg_tx_count_s[3]) + ); + MUXCY_L plm_fsm_rc_counter_ts2_0_reg_tx_count_cry_4_ ( + .CI(plm_fsm_rc_counter_ts2_0_reg_tx_count_cry[3]), + .DI(plm_fsm_rc_counter_ts2_0_VCC_1022), + .LO(plm_fsm_rc_counter_ts2_0_reg_tx_count_cry[4]), + .S(plm_fsm_rc_counter_ts2_0_reg_tx_count_qxu[4]) + ); + XORCY plm_fsm_rc_counter_ts2_0_reg_tx_count_s_4_ ( + .CI(plm_fsm_rc_counter_ts2_0_reg_tx_count_cry[3]), + .LI(plm_fsm_rc_counter_ts2_0_reg_tx_count_qxu[4]), + .O(plm_fsm_rc_counter_ts2_0_reg_tx_count_s[4]) + ); + MUXCY_L plm_fsm_rc_counter_ts2_0_reg_tx_count_cry_5_ ( + .CI(plm_fsm_rc_counter_ts2_0_reg_tx_count_cry[4]), + .DI(plm_fsm_rc_counter_ts2_0_VCC_1022), + .LO(plm_fsm_rc_counter_ts2_0_reg_tx_count_cry[5]), + .S(plm_fsm_rc_counter_ts2_0_reg_tx_count_qxu[5]) + ); + XORCY plm_fsm_rc_counter_ts2_0_reg_tx_count_s_5_ ( + .CI(plm_fsm_rc_counter_ts2_0_reg_tx_count_cry[4]), + .LI(plm_fsm_rc_counter_ts2_0_reg_tx_count_qxu[5]), + .O(plm_fsm_rc_counter_ts2_0_reg_tx_count_s[5]) + ); + MUXCY_L plm_fsm_rc_counter_ts2_0_reg_tx_count_cry_6_ ( + .CI(plm_fsm_rc_counter_ts2_0_reg_tx_count_cry[5]), + .DI(plm_fsm_rc_counter_ts2_0_VCC_1022), + .LO(plm_fsm_rc_counter_ts2_0_reg_tx_count_cry[6]), + .S(plm_fsm_rc_counter_ts2_0_reg_tx_count_qxu[6]) + ); + XORCY plm_fsm_rc_counter_ts2_0_reg_tx_count_s_6_ ( + .CI(plm_fsm_rc_counter_ts2_0_reg_tx_count_cry[5]), + .LI(plm_fsm_rc_counter_ts2_0_reg_tx_count_qxu[6]), + .O(plm_fsm_rc_counter_ts2_0_reg_tx_count_s[6]) + ); + XORCY plm_fsm_rc_counter_ts2_0_reg_tx_count_s_7_ ( + .CI(plm_fsm_rc_counter_ts2_0_reg_tx_count_cry[6]), + .LI(plm_fsm_rc_counter_ts2_0_reg_tx_count_qxu[7]), + .O(plm_fsm_rc_counter_ts2_0_reg_tx_count_s[7]) + ); + defparam plm_fsm_rc_counter_ts2_0_un1_enable_4_0_0_i_o3.INIT = 4'h1; + LUT2 plm_fsm_rc_counter_ts2_0_un1_enable_4_0_0_i_o3 ( + .I0(plm_fsm_reg_state_14__909), + .I1(plm_fsm_reg_state_15__908), + .O(N_38100_i) + ); + defparam plm_fsm_rc_counter_ts2_0_un1_enable_1_0_a2_0_a2_i_o4.INIT = 4'h4; + LUT2 plm_fsm_rc_counter_ts2_0_un1_enable_1_0_a2_0_a2_i_o4 ( + .I0(N_38100_i), + .I1(plm_fsm_rc_counter_ts2_0_reg_oneshot_1025), + .O(plm_fsm_rc_counter_ts2_0_N_38370_i) + ); + defparam plm_fsm_rc_counter_ts2_0_loadable_rx_counter_un1_reg_rx_count_0_a2_4.INIT = 16'h0001; + LUT4 plm_fsm_rc_counter_ts2_0_loadable_rx_counter_un1_reg_rx_count_0_a2_4 ( + .I0(plm_fsm_rc_counter_ts2_0_reg_rx_count[0]), + .I1(plm_fsm_rc_counter_ts2_0_reg_rx_count[1]), + .I2(plm_fsm_rc_counter_ts2_0_reg_rx_count[2]), + .I3(plm_fsm_rc_counter_ts2_0_reg_rx_count[3]), + .O(plm_fsm_rc_counter_ts2_0_un1_reg_rx_count_0_a2_4) + ); + defparam plm_fsm_rc_counter_ts2_0_loadable_rx_counter_un1_reg_rx_count_0_a2_5.INIT = 16'h0001; + LUT4 plm_fsm_rc_counter_ts2_0_loadable_rx_counter_un1_reg_rx_count_0_a2_5 ( + .I0(plm_fsm_rc_counter_ts2_0_reg_rx_count[4]), + .I1(plm_fsm_rc_counter_ts2_0_reg_rx_count[5]), + .I2(plm_fsm_rc_counter_ts2_0_reg_rx_count[6]), + .I3(plm_fsm_rc_counter_ts2_0_reg_rx_count[7]), + .O(plm_fsm_rc_counter_ts2_0_un1_reg_rx_count_0_a2_5) + ); + defparam plm_fsm_rc_counter_ts2_0_loadable_tx_counter_un1_reg_tx_count_0_a2_4.INIT = 16'h0001; + LUT4 plm_fsm_rc_counter_ts2_0_loadable_tx_counter_un1_reg_tx_count_0_a2_4 ( + .I0(plm_fsm_rc_counter_ts2_0_reg_tx_count[0]), + .I1(plm_fsm_rc_counter_ts2_0_reg_tx_count[1]), + .I2(plm_fsm_rc_counter_ts2_0_reg_tx_count[2]), + .I3(plm_fsm_rc_counter_ts2_0_reg_tx_count[3]), + .O(plm_fsm_rc_counter_ts2_0_un1_reg_tx_count_0_a2_4) + ); + defparam plm_fsm_rc_counter_ts2_0_loadable_tx_counter_un1_reg_tx_count_0_a2_5.INIT = 16'h0001; + LUT4 plm_fsm_rc_counter_ts2_0_loadable_tx_counter_un1_reg_tx_count_0_a2_5 ( + .I0(plm_fsm_rc_counter_ts2_0_reg_tx_count[4]), + .I1(plm_fsm_rc_counter_ts2_0_reg_tx_count[5]), + .I2(plm_fsm_rc_counter_ts2_0_reg_tx_count[6]), + .I3(plm_fsm_rc_counter_ts2_0_reg_tx_count[7]), + .O(plm_fsm_rc_counter_ts2_0_un1_reg_tx_count_0_a2_5) + ); + defparam plm_fsm_rc_counter_ts2_0_oneshot_monitor_N_69115_i.INIT = 4'hE; + LUT2 plm_fsm_rc_counter_ts2_0_oneshot_monitor_N_69115_i ( + .I0(plm_reg_ts2_1), + .I1(N_38100_i), + .O(plm_fsm_rc_counter_ts2_0_N_69115_i) + ); + defparam plm_fsm_rc_counter_ts2_0_un1_enable_1_0_a2_0_a2_i.INIT = 4'h2; + LUT2 plm_fsm_rc_counter_ts2_0_un1_enable_1_0_a2_0_a2_i ( + .I0(plm_fsm_rc_counter_ts2_0_N_38370_i), + .I1(plm_fsm_rc_counter_ts2_0_reg_tx_expired_1027), + .O(plm_fsm_rc_counter_ts2_0_N_37194_i) + ); + defparam plm_fsm_rc_counter_ts2_0_loadable_rx_counter_N_69224_i.INIT = 8'hFE; + LUT3 plm_fsm_rc_counter_ts2_0_loadable_rx_counter_N_69224_i ( + .I0(plm_reg_ts2_1), + .I1(N_38100_i), + .I2(plm_fsm_rc_counter_ts2_0_reg_rx_expired_251), + .O(plm_fsm_rc_counter_ts2_0_N_69224_i) + ); + defparam plm_fsm_rc_counter_ts2_0_N_69096_i.INIT = 8'hD5; + LUT3 plm_fsm_rc_counter_ts2_0_N_69096_i ( + .I0(plm_fsm_rc_counter_ts2_0_N_38370_i), + .I1(plm_fsm_rc_counter_ts2_0_un1_reg_tx_count_0_a2_4), + .I2(plm_fsm_rc_counter_ts2_0_un1_reg_tx_count_0_a2_5), + .O(plm_fsm_rc_counter_ts2_0_N_69096_i_1026) + ); + defparam plm_fsm_rc_counter_ts2_0_loadable_rx_counter_N_69111_i.INIT = 8'hEA; + LUT3 plm_fsm_rc_counter_ts2_0_loadable_rx_counter_N_69111_i ( + .I0(N_38100_i), + .I1(plm_fsm_rc_counter_ts2_0_un1_reg_rx_count_0_a2_4), + .I2(plm_fsm_rc_counter_ts2_0_un1_reg_rx_count_0_a2_5), + .O(plm_fsm_rc_counter_ts2_0_N_69111_i) + ); + defparam plm_fsm_rc_counter_ts2_0_N_69278_i.INIT = 4'hB; + LUT2 plm_fsm_rc_counter_ts2_0_N_69278_i ( + .I0(plm_reg_sym_sent_6_), + .I1(plm_fsm_rc_counter_ts2_0_N_37194_i), + .O(plm_fsm_rc_counter_ts2_0_N_69278_i_1024) + ); + defparam plm_fsm_rc_counter_ts2_0_N_69064_i.INIT = 8'hAE; + LUT3_L plm_fsm_rc_counter_ts2_0_N_69064_i ( + .I0(N_38100_i), + .I1(plm_fsm_N_38512_1), + .I2(plm_fsm_rc_counter_ts2_0_reg_rx_expired_251), + .LO(plm_fsm_rc_counter_ts2_0_N_69064_i_1028) + ); + defparam plm_fsm_rc_counter_ts2_0_flagit_reg_expired_5_0_a2_0_a2_i.INIT = 8'h40; + LUT3_L plm_fsm_rc_counter_ts2_0_flagit_reg_expired_5_0_a2_0_a2_i ( + .I0(N_38100_i), + .I1(plm_fsm_rc_counter_ts2_0_reg_rx_expired_251), + .I2(plm_fsm_rc_counter_ts2_0_reg_tx_expired_1027), + .LO(plm_fsm_rc_counter_ts2_0_N_37196_i) + ); + defparam plm_fsm_rc_counter_ts2_0_N_37194_i_i.INIT = 4'hB; + LUT2 plm_fsm_rc_counter_ts2_0_N_37194_i_i ( + .I0(plm_fsm_rc_counter_ts2_0_reg_tx_expired_1027), + .I1(plm_fsm_rc_counter_ts2_0_N_38370_i), + .O(plm_fsm_rc_counter_ts2_0_N_37194_i_i_1023) + ); + FDCE plm_fsm_rc_counter_ts2_0_reg_tx_count_7_ ( + .CE(plm_fsm_rc_counter_ts2_0_N_69278_i_1024), + .C(mgt_clk), + .D(plm_fsm_rc_counter_ts2_0_reg_tx_count_s[7]), + .Q(plm_fsm_rc_counter_ts2_0_reg_tx_count[7]), + .CLR(plm_rst) + ); + FDCE plm_fsm_rc_counter_ts2_0_reg_tx_count_6_ ( + .CE(plm_fsm_rc_counter_ts2_0_N_69278_i_1024), + .C(mgt_clk), + .D(plm_fsm_rc_counter_ts2_0_reg_tx_count_s[6]), + .Q(plm_fsm_rc_counter_ts2_0_reg_tx_count[6]), + .CLR(plm_rst) + ); + FDCE plm_fsm_rc_counter_ts2_0_reg_tx_count_5_ ( + .CE(plm_fsm_rc_counter_ts2_0_N_69278_i_1024), + .C(mgt_clk), + .D(plm_fsm_rc_counter_ts2_0_reg_tx_count_s[5]), + .Q(plm_fsm_rc_counter_ts2_0_reg_tx_count[5]), + .CLR(plm_rst) + ); + FDPE plm_fsm_rc_counter_ts2_0_reg_tx_count_4_ ( + .PRE(plm_rst), + .CE(plm_fsm_rc_counter_ts2_0_N_69278_i_1024), + .C(mgt_clk), + .D(plm_fsm_rc_counter_ts2_0_reg_tx_count_s[4]), + .Q(plm_fsm_rc_counter_ts2_0_reg_tx_count[4]) + ); + FDCE plm_fsm_rc_counter_ts2_0_reg_tx_count_3_ ( + .CE(plm_fsm_rc_counter_ts2_0_N_69278_i_1024), + .C(mgt_clk), + .D(plm_fsm_rc_counter_ts2_0_reg_tx_count_s[3]), + .Q(plm_fsm_rc_counter_ts2_0_reg_tx_count[3]), + .CLR(plm_rst) + ); + FDCE plm_fsm_rc_counter_ts2_0_reg_tx_count_2_ ( + .CE(plm_fsm_rc_counter_ts2_0_N_69278_i_1024), + .C(mgt_clk), + .D(plm_fsm_rc_counter_ts2_0_reg_tx_count_s[2]), + .Q(plm_fsm_rc_counter_ts2_0_reg_tx_count[2]), + .CLR(plm_rst) + ); + FDCE plm_fsm_rc_counter_ts2_0_reg_tx_count_1_ ( + .CE(plm_fsm_rc_counter_ts2_0_N_69278_i_1024), + .C(mgt_clk), + .D(plm_fsm_rc_counter_ts2_0_reg_tx_count_s[1]), + .Q(plm_fsm_rc_counter_ts2_0_reg_tx_count[1]), + .CLR(plm_rst) + ); + FDCE plm_fsm_rc_counter_ts2_0_reg_tx_count_0_ ( + .CE(plm_fsm_rc_counter_ts2_0_N_69278_i_1024), + .C(mgt_clk), + .D(plm_fsm_rc_counter_ts2_0_reg_tx_count_s[0]), + .Q(plm_fsm_rc_counter_ts2_0_reg_tx_count[0]), + .CLR(plm_rst) + ); + FDCE plm_fsm_rc_counter_ts2_0_reg_rx_count_7_ ( + .CE(plm_fsm_rc_counter_ts2_0_N_69224_i), + .C(mgt_clk), + .D(plm_fsm_rc_counter_ts2_0_reg_rx_count_s[7]), + .Q(plm_fsm_rc_counter_ts2_0_reg_rx_count[7]), + .CLR(plm_rst) + ); + FDCE plm_fsm_rc_counter_ts2_0_reg_rx_count_6_ ( + .CE(plm_fsm_rc_counter_ts2_0_N_69224_i), + .C(mgt_clk), + .D(plm_fsm_rc_counter_ts2_0_reg_rx_count_s[6]), + .Q(plm_fsm_rc_counter_ts2_0_reg_rx_count[6]), + .CLR(plm_rst) + ); + FDCE plm_fsm_rc_counter_ts2_0_reg_rx_count_5_ ( + .CE(plm_fsm_rc_counter_ts2_0_N_69224_i), + .C(mgt_clk), + .D(plm_fsm_rc_counter_ts2_0_reg_rx_count_s[5]), + .Q(plm_fsm_rc_counter_ts2_0_reg_rx_count[5]), + .CLR(plm_rst) + ); + FDCE plm_fsm_rc_counter_ts2_0_reg_rx_count_4_ ( + .CE(plm_fsm_rc_counter_ts2_0_N_69224_i), + .C(mgt_clk), + .D(plm_fsm_rc_counter_ts2_0_reg_rx_count_s[4]), + .Q(plm_fsm_rc_counter_ts2_0_reg_rx_count[4]), + .CLR(plm_rst) + ); + FDPE plm_fsm_rc_counter_ts2_0_reg_rx_count_3_ ( + .PRE(plm_rst), + .CE(plm_fsm_rc_counter_ts2_0_N_69224_i), + .C(mgt_clk), + .D(plm_fsm_rc_counter_ts2_0_reg_rx_count_s[3]), + .Q(plm_fsm_rc_counter_ts2_0_reg_rx_count[3]) + ); + FDCE plm_fsm_rc_counter_ts2_0_reg_rx_count_2_ ( + .CE(plm_fsm_rc_counter_ts2_0_N_69224_i), + .C(mgt_clk), + .D(plm_fsm_rc_counter_ts2_0_reg_rx_count_s[2]), + .Q(plm_fsm_rc_counter_ts2_0_reg_rx_count[2]), + .CLR(plm_rst) + ); + FDCE plm_fsm_rc_counter_ts2_0_reg_rx_count_1_ ( + .CE(plm_fsm_rc_counter_ts2_0_N_69224_i), + .C(mgt_clk), + .D(plm_fsm_rc_counter_ts2_0_reg_rx_count_s[1]), + .Q(plm_fsm_rc_counter_ts2_0_reg_rx_count[1]), + .CLR(plm_rst) + ); + FDCE plm_fsm_rc_counter_ts2_0_reg_rx_count_0_ ( + .CE(plm_fsm_rc_counter_ts2_0_N_69224_i), + .C(mgt_clk), + .D(plm_fsm_rc_counter_ts2_0_reg_rx_count_s[0]), + .Q(plm_fsm_rc_counter_ts2_0_reg_rx_count[0]), + .CLR(plm_rst) + ); + FDC plm_fsm_rc_counter_ts2_0_reg_expired ( + .C(mgt_clk), + .D(plm_fsm_rc_counter_ts2_0_N_37196_i), + .Q(plm_fsm_rc_cntrout_ts2_0), + .CLR(plm_rst) + ); + FDCE plm_fsm_rc_counter_ts2_0_reg_oneshot ( + .CE(plm_fsm_rc_counter_ts2_0_N_69115_i), + .C(mgt_clk), + .D(plm_fsm_N_38100_i_i), + .Q(plm_fsm_rc_counter_ts2_0_reg_oneshot_1025), + .CLR(plm_rst) + ); + FDCE plm_fsm_rc_counter_ts2_0_reg_rx_expired ( + .CE(plm_fsm_rc_counter_ts2_0_N_69111_i), + .C(mgt_clk), + .D(plm_fsm_N_38100_i_i), + .Q(plm_fsm_rc_counter_ts2_0_reg_rx_expired_251), + .CLR(plm_rst) + ); + FDCE plm_fsm_rc_counter_ts2_0_reg_tx_expired ( + .CE(plm_fsm_rc_counter_ts2_0_N_69096_i_1026), + .C(mgt_clk), + .D(plm_fsm_rc_counter_ts2_0_N_38370_i), + .Q(plm_fsm_rc_counter_ts2_0_reg_tx_expired_1027), + .CLR(plm_rst) + ); + INV plm_fsm_rc_counter_ts2_0_N_38100_i_i ( + .I(N_38100_i), + .O(plm_fsm_N_38100_i_i) + ); + defparam plm_fsm_rc_counter_ts2_0_reg_rx_count_qxu_0_0_.INIT = 4'h7; + LUT2_L plm_fsm_rc_counter_ts2_0_reg_rx_count_qxu_0_0_ ( + .I0(N_37268_i), + .I1(plm_fsm_rc_counter_ts2_0_reg_rx_count[0]), + .LO(plm_fsm_rc_counter_ts2_0_reg_rx_count_qxu[0]) + ); + defparam plm_fsm_rc_counter_ts2_0_reg_rx_count_qxu_0_1_.INIT = 4'h7; + LUT2_L plm_fsm_rc_counter_ts2_0_reg_rx_count_qxu_0_1_ ( + .I0(N_37268_i), + .I1(plm_fsm_rc_counter_ts2_0_reg_rx_count[1]), + .LO(plm_fsm_rc_counter_ts2_0_reg_rx_count_qxu[1]) + ); + defparam plm_fsm_rc_counter_ts2_0_reg_rx_count_qxu_0_2_.INIT = 4'h7; + LUT2_L plm_fsm_rc_counter_ts2_0_reg_rx_count_qxu_0_2_ ( + .I0(N_37268_i), + .I1(plm_fsm_rc_counter_ts2_0_reg_rx_count[2]), + .LO(plm_fsm_rc_counter_ts2_0_reg_rx_count_qxu[2]) + ); + defparam plm_fsm_rc_counter_ts2_0_reg_rx_count_qxu_0_3_.INIT = 8'h1B; + LUT3_L plm_fsm_rc_counter_ts2_0_reg_rx_count_qxu_0_3_ ( + .I0(N_37268_i), + .I1(plm_fsm_rc_counter_ts2_0_N_69064_i_1028), + .I2(plm_fsm_rc_counter_ts2_0_reg_rx_count[3]), + .LO(plm_fsm_rc_counter_ts2_0_reg_rx_count_qxu[3]) + ); + defparam plm_fsm_rc_counter_ts2_0_reg_rx_count_qxu_0_4_.INIT = 4'h7; + LUT2_L plm_fsm_rc_counter_ts2_0_reg_rx_count_qxu_0_4_ ( + .I0(N_37268_i), + .I1(plm_fsm_rc_counter_ts2_0_reg_rx_count[4]), + .LO(plm_fsm_rc_counter_ts2_0_reg_rx_count_qxu[4]) + ); + defparam plm_fsm_rc_counter_ts2_0_reg_rx_count_qxu_0_5_.INIT = 4'h7; + LUT2_L plm_fsm_rc_counter_ts2_0_reg_rx_count_qxu_0_5_ ( + .I0(N_37268_i), + .I1(plm_fsm_rc_counter_ts2_0_reg_rx_count[5]), + .LO(plm_fsm_rc_counter_ts2_0_reg_rx_count_qxu[5]) + ); + defparam plm_fsm_rc_counter_ts2_0_reg_rx_count_qxu_0_6_.INIT = 4'h7; + LUT2_L plm_fsm_rc_counter_ts2_0_reg_rx_count_qxu_0_6_ ( + .I0(N_37268_i), + .I1(plm_fsm_rc_counter_ts2_0_reg_rx_count[6]), + .LO(plm_fsm_rc_counter_ts2_0_reg_rx_count_qxu[6]) + ); + defparam plm_fsm_rc_counter_ts2_0_reg_rx_count_qxu_0_7_.INIT = 4'h7; + LUT2_L plm_fsm_rc_counter_ts2_0_reg_rx_count_qxu_0_7_ ( + .I0(N_37268_i), + .I1(plm_fsm_rc_counter_ts2_0_reg_rx_count[7]), + .LO(plm_fsm_rc_counter_ts2_0_reg_rx_count_qxu[7]) + ); + defparam plm_fsm_rc_counter_ts2_0_reg_tx_count_qxu_0_0_.INIT = 4'h7; + LUT2_L plm_fsm_rc_counter_ts2_0_reg_tx_count_qxu_0_0_ ( + .I0(plm_fsm_rc_counter_ts2_0_N_37194_i), + .I1(plm_fsm_rc_counter_ts2_0_reg_tx_count[0]), + .LO(plm_fsm_rc_counter_ts2_0_reg_tx_count_qxu[0]) + ); + defparam plm_fsm_rc_counter_ts2_0_reg_tx_count_qxu_0_1_.INIT = 4'h7; + LUT2_L plm_fsm_rc_counter_ts2_0_reg_tx_count_qxu_0_1_ ( + .I0(plm_fsm_rc_counter_ts2_0_N_37194_i), + .I1(plm_fsm_rc_counter_ts2_0_reg_tx_count[1]), + .LO(plm_fsm_rc_counter_ts2_0_reg_tx_count_qxu[1]) + ); + defparam plm_fsm_rc_counter_ts2_0_reg_tx_count_qxu_0_2_.INIT = 4'h7; + LUT2_L plm_fsm_rc_counter_ts2_0_reg_tx_count_qxu_0_2_ ( + .I0(plm_fsm_rc_counter_ts2_0_N_37194_i), + .I1(plm_fsm_rc_counter_ts2_0_reg_tx_count[2]), + .LO(plm_fsm_rc_counter_ts2_0_reg_tx_count_qxu[2]) + ); + defparam plm_fsm_rc_counter_ts2_0_reg_tx_count_qxu_0_3_.INIT = 4'h7; + LUT2_L plm_fsm_rc_counter_ts2_0_reg_tx_count_qxu_0_3_ ( + .I0(plm_fsm_rc_counter_ts2_0_N_37194_i), + .I1(plm_fsm_rc_counter_ts2_0_reg_tx_count[3]), + .LO(plm_fsm_rc_counter_ts2_0_reg_tx_count_qxu[3]) + ); + defparam plm_fsm_rc_counter_ts2_0_reg_tx_count_qxu_0_4_.INIT = 8'h4E; + LUT3_L plm_fsm_rc_counter_ts2_0_reg_tx_count_qxu_0_4_ ( + .I0(plm_fsm_rc_counter_ts2_0_N_37194_i), + .I1(plm_fsm_rc_counter_ts2_0_N_38370_i), + .I2(plm_fsm_rc_counter_ts2_0_reg_tx_count[4]), + .LO(plm_fsm_rc_counter_ts2_0_reg_tx_count_qxu[4]) + ); + defparam plm_fsm_rc_counter_ts2_0_reg_tx_count_qxu_0_5_.INIT = 4'h7; + LUT2_L plm_fsm_rc_counter_ts2_0_reg_tx_count_qxu_0_5_ ( + .I0(plm_fsm_rc_counter_ts2_0_N_37194_i), + .I1(plm_fsm_rc_counter_ts2_0_reg_tx_count[5]), + .LO(plm_fsm_rc_counter_ts2_0_reg_tx_count_qxu[5]) + ); + defparam plm_fsm_rc_counter_ts2_0_reg_tx_count_qxu_0_6_.INIT = 4'h7; + LUT2_L plm_fsm_rc_counter_ts2_0_reg_tx_count_qxu_0_6_ ( + .I0(plm_fsm_rc_counter_ts2_0_N_37194_i), + .I1(plm_fsm_rc_counter_ts2_0_reg_tx_count[6]), + .LO(plm_fsm_rc_counter_ts2_0_reg_tx_count_qxu[6]) + ); + defparam plm_fsm_rc_counter_ts2_0_reg_tx_count_qxu_0_7_.INIT = 4'h7; + LUT2_L plm_fsm_rc_counter_ts2_0_reg_tx_count_qxu_0_7_ ( + .I0(plm_fsm_rc_counter_ts2_0_N_37194_i), + .I1(plm_fsm_rc_counter_ts2_0_reg_tx_count[7]), + .LO(plm_fsm_rc_counter_ts2_0_reg_tx_count_qxu[7]) + ); + GND plm_fsm_ri_timer_GND ( + .G(plm_fsm_ri_timer_GND_1029) + ); + MUXCY_L plm_fsm_ri_timer_reg_count_cry_0_ ( + .CI(plm_fsm_reg_state_16__357), + .DI(plm_fsm_ri_timer_GND_1029), + .LO(plm_fsm_ri_timer_reg_count_cry[0]), + .S(plm_fsm_ri_timer_reg_count_qxu[0]) + ); + XORCY plm_fsm_ri_timer_reg_count_s_0_ ( + .CI(plm_fsm_reg_state_16__357), + .LI(plm_fsm_ri_timer_reg_count_qxu[0]), + .O(plm_fsm_ri_timer_reg_count_s[0]) + ); + MUXCY_L plm_fsm_ri_timer_reg_count_cry_1_ ( + .CI(plm_fsm_ri_timer_reg_count_cry[0]), + .DI(plm_fsm_ri_timer_GND_1029), + .LO(plm_fsm_ri_timer_reg_count_cry[1]), + .S(plm_fsm_ri_timer_reg_count_qxu[1]) + ); + XORCY plm_fsm_ri_timer_reg_count_s_1_ ( + .CI(plm_fsm_ri_timer_reg_count_cry[0]), + .LI(plm_fsm_ri_timer_reg_count_qxu[1]), + .O(plm_fsm_ri_timer_reg_count_s[1]) + ); + MUXCY_L plm_fsm_ri_timer_reg_count_cry_2_ ( + .CI(plm_fsm_ri_timer_reg_count_cry[1]), + .DI(plm_fsm_ri_timer_GND_1029), + .LO(plm_fsm_ri_timer_reg_count_cry[2]), + .S(plm_fsm_ri_timer_reg_count_qxu[2]) + ); + XORCY plm_fsm_ri_timer_reg_count_s_2_ ( + .CI(plm_fsm_ri_timer_reg_count_cry[1]), + .LI(plm_fsm_ri_timer_reg_count_qxu[2]), + .O(plm_fsm_ri_timer_reg_count_s[2]) + ); + MUXCY_L plm_fsm_ri_timer_reg_count_cry_3_ ( + .CI(plm_fsm_ri_timer_reg_count_cry[2]), + .DI(plm_fsm_ri_timer_GND_1029), + .LO(plm_fsm_ri_timer_reg_count_cry[3]), + .S(plm_fsm_ri_timer_reg_count_qxu[3]) + ); + XORCY plm_fsm_ri_timer_reg_count_s_3_ ( + .CI(plm_fsm_ri_timer_reg_count_cry[2]), + .LI(plm_fsm_ri_timer_reg_count_qxu[3]), + .O(plm_fsm_ri_timer_reg_count_s[3]) + ); + MUXCY_L plm_fsm_ri_timer_reg_count_cry_4_ ( + .CI(plm_fsm_ri_timer_reg_count_cry[3]), + .DI(plm_fsm_ri_timer_GND_1029), + .LO(plm_fsm_ri_timer_reg_count_cry[4]), + .S(plm_fsm_ri_timer_reg_count_qxu[4]) + ); + XORCY plm_fsm_ri_timer_reg_count_s_4_ ( + .CI(plm_fsm_ri_timer_reg_count_cry[3]), + .LI(plm_fsm_ri_timer_reg_count_qxu[4]), + .O(plm_fsm_ri_timer_reg_count_s[4]) + ); + MUXCY_L plm_fsm_ri_timer_reg_count_cry_5_ ( + .CI(plm_fsm_ri_timer_reg_count_cry[4]), + .DI(plm_fsm_ri_timer_GND_1029), + .LO(plm_fsm_ri_timer_reg_count_cry[5]), + .S(plm_fsm_ri_timer_reg_count_qxu[5]) + ); + XORCY plm_fsm_ri_timer_reg_count_s_5_ ( + .CI(plm_fsm_ri_timer_reg_count_cry[4]), + .LI(plm_fsm_ri_timer_reg_count_qxu[5]), + .O(plm_fsm_ri_timer_reg_count_s[5]) + ); + MUXCY_L plm_fsm_ri_timer_reg_count_cry_6_ ( + .CI(plm_fsm_ri_timer_reg_count_cry[5]), + .DI(plm_fsm_ri_timer_GND_1029), + .LO(plm_fsm_ri_timer_reg_count_cry[6]), + .S(plm_fsm_ri_timer_reg_count_qxu[6]) + ); + XORCY plm_fsm_ri_timer_reg_count_s_6_ ( + .CI(plm_fsm_ri_timer_reg_count_cry[5]), + .LI(plm_fsm_ri_timer_reg_count_qxu[6]), + .O(plm_fsm_ri_timer_reg_count_s[6]) + ); + MUXCY_L plm_fsm_ri_timer_reg_count_cry_7_ ( + .CI(plm_fsm_ri_timer_reg_count_cry[6]), + .DI(plm_fsm_ri_timer_GND_1029), + .LO(plm_fsm_ri_timer_reg_count_cry[7]), + .S(plm_fsm_ri_timer_reg_count_qxu[7]) + ); + XORCY plm_fsm_ri_timer_reg_count_s_7_ ( + .CI(plm_fsm_ri_timer_reg_count_cry[6]), + .LI(plm_fsm_ri_timer_reg_count_qxu[7]), + .O(plm_fsm_ri_timer_reg_count_s[7]) + ); + MUXCY_L plm_fsm_ri_timer_reg_count_cry_8_ ( + .CI(plm_fsm_ri_timer_reg_count_cry[7]), + .DI(plm_fsm_ri_timer_GND_1029), + .LO(plm_fsm_ri_timer_reg_count_cry[8]), + .S(plm_fsm_ri_timer_reg_count_qxu[8]) + ); + XORCY plm_fsm_ri_timer_reg_count_s_8_ ( + .CI(plm_fsm_ri_timer_reg_count_cry[7]), + .LI(plm_fsm_ri_timer_reg_count_qxu[8]), + .O(plm_fsm_ri_timer_reg_count_s[8]) + ); + MUXCY_L plm_fsm_ri_timer_reg_count_cry_9_ ( + .CI(plm_fsm_ri_timer_reg_count_cry[8]), + .DI(plm_fsm_ri_timer_GND_1029), + .LO(plm_fsm_ri_timer_reg_count_cry[9]), + .S(plm_fsm_ri_timer_reg_count_qxu[9]) + ); + XORCY plm_fsm_ri_timer_reg_count_s_9_ ( + .CI(plm_fsm_ri_timer_reg_count_cry[8]), + .LI(plm_fsm_ri_timer_reg_count_qxu[9]), + .O(plm_fsm_ri_timer_reg_count_s[9]) + ); + MUXCY_L plm_fsm_ri_timer_reg_count_cry_10_ ( + .CI(plm_fsm_ri_timer_reg_count_cry[9]), + .DI(plm_fsm_ri_timer_GND_1029), + .LO(plm_fsm_ri_timer_reg_count_cry[10]), + .S(plm_fsm_ri_timer_reg_count_qxu[10]) + ); + XORCY plm_fsm_ri_timer_reg_count_s_10_ ( + .CI(plm_fsm_ri_timer_reg_count_cry[9]), + .LI(plm_fsm_ri_timer_reg_count_qxu[10]), + .O(plm_fsm_ri_timer_reg_count_s[10]) + ); + MUXCY_L plm_fsm_ri_timer_reg_count_cry_11_ ( + .CI(plm_fsm_ri_timer_reg_count_cry[10]), + .DI(plm_fsm_ri_timer_GND_1029), + .LO(plm_fsm_ri_timer_reg_count_cry[11]), + .S(plm_fsm_ri_timer_reg_count_qxu[11]) + ); + XORCY plm_fsm_ri_timer_reg_count_s_11_ ( + .CI(plm_fsm_ri_timer_reg_count_cry[10]), + .LI(plm_fsm_ri_timer_reg_count_qxu[11]), + .O(plm_fsm_ri_timer_reg_count_s[11]) + ); + MUXCY_L plm_fsm_ri_timer_reg_count_cry_12_ ( + .CI(plm_fsm_ri_timer_reg_count_cry[11]), + .DI(plm_fsm_ri_timer_GND_1029), + .LO(plm_fsm_ri_timer_reg_count_cry[12]), + .S(plm_fsm_ri_timer_reg_count_qxu[12]) + ); + XORCY plm_fsm_ri_timer_reg_count_s_12_ ( + .CI(plm_fsm_ri_timer_reg_count_cry[11]), + .LI(plm_fsm_ri_timer_reg_count_qxu[12]), + .O(plm_fsm_ri_timer_reg_count_s[12]) + ); + MUXCY_L plm_fsm_ri_timer_reg_count_cry_13_ ( + .CI(plm_fsm_ri_timer_reg_count_cry[12]), + .DI(plm_fsm_ri_timer_GND_1029), + .LO(plm_fsm_ri_timer_reg_count_cry[13]), + .S(plm_fsm_ri_timer_reg_count_qxu[13]) + ); + XORCY plm_fsm_ri_timer_reg_count_s_13_ ( + .CI(plm_fsm_ri_timer_reg_count_cry[12]), + .LI(plm_fsm_ri_timer_reg_count_qxu[13]), + .O(plm_fsm_ri_timer_reg_count_s[13]) + ); + MUXCY_L plm_fsm_ri_timer_reg_count_cry_14_ ( + .CI(plm_fsm_ri_timer_reg_count_cry[13]), + .DI(plm_fsm_ri_timer_GND_1029), + .LO(plm_fsm_ri_timer_reg_count_cry[14]), + .S(plm_fsm_ri_timer_reg_count_qxu[14]) + ); + XORCY plm_fsm_ri_timer_reg_count_s_14_ ( + .CI(plm_fsm_ri_timer_reg_count_cry[13]), + .LI(plm_fsm_ri_timer_reg_count_qxu[14]), + .O(plm_fsm_ri_timer_reg_count_s[14]) + ); + MUXCY_L plm_fsm_ri_timer_reg_count_cry_15_ ( + .CI(plm_fsm_ri_timer_reg_count_cry[14]), + .DI(plm_fsm_ri_timer_GND_1029), + .LO(plm_fsm_ri_timer_reg_count_cry[15]), + .S(plm_fsm_ri_timer_reg_count_qxu[15]) + ); + XORCY plm_fsm_ri_timer_reg_count_s_15_ ( + .CI(plm_fsm_ri_timer_reg_count_cry[14]), + .LI(plm_fsm_ri_timer_reg_count_qxu[15]), + .O(plm_fsm_ri_timer_reg_count_s[15]) + ); + MUXCY_L plm_fsm_ri_timer_reg_count_cry_16_ ( + .CI(plm_fsm_ri_timer_reg_count_cry[15]), + .DI(plm_fsm_ri_timer_GND_1029), + .LO(plm_fsm_ri_timer_reg_count_cry[16]), + .S(plm_fsm_ri_timer_reg_count_qxu[16]) + ); + XORCY plm_fsm_ri_timer_reg_count_s_16_ ( + .CI(plm_fsm_ri_timer_reg_count_cry[15]), + .LI(plm_fsm_ri_timer_reg_count_qxu[16]), + .O(plm_fsm_ri_timer_reg_count_s[16]) + ); + MUXCY_L plm_fsm_ri_timer_reg_count_cry_17_ ( + .CI(plm_fsm_ri_timer_reg_count_cry[16]), + .DI(plm_fsm_ri_timer_GND_1029), + .LO(plm_fsm_ri_timer_reg_count_cry[17]), + .S(plm_fsm_ri_timer_reg_count_qxu[17]) + ); + XORCY plm_fsm_ri_timer_reg_count_s_17_ ( + .CI(plm_fsm_ri_timer_reg_count_cry[16]), + .LI(plm_fsm_ri_timer_reg_count_qxu[17]), + .O(plm_fsm_ri_timer_reg_count_s[17]) + ); + MUXCY_L plm_fsm_ri_timer_reg_count_cry_18_ ( + .CI(plm_fsm_ri_timer_reg_count_cry[17]), + .DI(plm_fsm_ri_timer_GND_1029), + .LO(plm_fsm_ri_timer_reg_count_cry[18]), + .S(plm_fsm_ri_timer_reg_count_qxu[18]) + ); + XORCY plm_fsm_ri_timer_reg_count_s_18_ ( + .CI(plm_fsm_ri_timer_reg_count_cry[17]), + .LI(plm_fsm_ri_timer_reg_count_qxu[18]), + .O(plm_fsm_ri_timer_reg_count_s[18]) + ); + MUXCY_L plm_fsm_ri_timer_reg_count_cry_19_ ( + .CI(plm_fsm_ri_timer_reg_count_cry[18]), + .DI(plm_fsm_ri_timer_GND_1029), + .LO(plm_fsm_ri_timer_reg_count_cry[19]), + .S(plm_fsm_ri_timer_reg_count_qxu[19]) + ); + XORCY plm_fsm_ri_timer_reg_count_s_19_ ( + .CI(plm_fsm_ri_timer_reg_count_cry[18]), + .LI(plm_fsm_ri_timer_reg_count_qxu[19]), + .O(plm_fsm_ri_timer_reg_count_s[19]) + ); + MUXCY_L plm_fsm_ri_timer_reg_count_cry_20_ ( + .CI(plm_fsm_ri_timer_reg_count_cry[19]), + .DI(plm_fsm_ri_timer_GND_1029), + .LO(plm_fsm_ri_timer_reg_count_cry[20]), + .S(plm_fsm_ri_timer_reg_count_qxu[20]) + ); + XORCY plm_fsm_ri_timer_reg_count_s_20_ ( + .CI(plm_fsm_ri_timer_reg_count_cry[19]), + .LI(plm_fsm_ri_timer_reg_count_qxu[20]), + .O(plm_fsm_ri_timer_reg_count_s[20]) + ); + MUXCY_L plm_fsm_ri_timer_reg_count_cry_21_ ( + .CI(plm_fsm_ri_timer_reg_count_cry[20]), + .DI(plm_fsm_ri_timer_GND_1029), + .LO(plm_fsm_ri_timer_reg_count_cry[21]), + .S(plm_fsm_ri_timer_reg_count_qxu[21]) + ); + XORCY plm_fsm_ri_timer_reg_count_s_21_ ( + .CI(plm_fsm_ri_timer_reg_count_cry[20]), + .LI(plm_fsm_ri_timer_reg_count_qxu[21]), + .O(plm_fsm_ri_timer_reg_count_s[21]) + ); + XORCY plm_fsm_ri_timer_reg_count_s_22_ ( + .CI(plm_fsm_ri_timer_reg_count_cry[21]), + .LI(plm_fsm_ri_timer_reg_count_qxu[22]), + .O(plm_fsm_ri_timer_reg_count_s[22]) + ); + defparam plm_fsm_ri_timer_count_i_m3_i_m3_0_18_.INIT = 8'hD8; + LUT3 plm_fsm_ri_timer_count_i_m3_i_m3_0_18_ ( + .I0(cfg_cfg_5072[507]), + .I1(plm_fsm_ri_timer_reg_count[10]), + .I2(plm_fsm_ri_timer_reg_count[18]), + .O(plm_fsm_ri_timer_N_51436) + ); + defparam plm_fsm_ri_timer_count_i_m3_i_m3_0_19_.INIT = 8'hD8; + LUT3_L plm_fsm_ri_timer_count_i_m3_i_m3_0_19_ ( + .I0(cfg_cfg_5072[507]), + .I1(plm_fsm_ri_timer_reg_count[11]), + .I2(plm_fsm_ri_timer_reg_count[19]), + .LO(plm_fsm_ri_timer_N_51437) + ); + defparam plm_fsm_ri_timer_count_i_m3_i_m3_0_20_.INIT = 8'hD8; + LUT3 plm_fsm_ri_timer_count_i_m3_i_m3_0_20_ ( + .I0(cfg_cfg_5072[507]), + .I1(plm_fsm_ri_timer_reg_count[12]), + .I2(plm_fsm_ri_timer_reg_count[20]), + .O(plm_fsm_ri_timer_N_51438) + ); + defparam plm_fsm_ri_timer_count_i_m3_i_m3_0_21_.INIT = 8'hD8; + LUT3 plm_fsm_ri_timer_count_i_m3_i_m3_0_21_ ( + .I0(cfg_cfg_5072[507]), + .I1(plm_fsm_ri_timer_reg_count[13]), + .I2(plm_fsm_ri_timer_reg_count[21]), + .O(plm_fsm_ri_timer_N_51439) + ); + defparam plm_fsm_ri_timer_un1_expired_2ms_0_a2_0_a4_0.INIT = 16'h0415; + LUT4_L plm_fsm_ri_timer_un1_expired_2ms_0_a2_0_a4_0 ( + .I0(plm_fsm_ri_timer_N_51437), + .I1(cfg_cfg_5072[507]), + .I2(plm_fsm_ri_timer_reg_count[14]), + .I3(plm_fsm_ri_timer_reg_count[22]), + .LO(plm_fsm_ri_timer_un1_expired_2ms_0_a2_0_a4_0_1030) + ); + defparam plm_fsm_ri_timer_un1_expired_2ms_0_a2_0_a4.INIT = 16'h0100; + LUT4 plm_fsm_ri_timer_un1_expired_2ms_0_a2_0_a4 ( + .I0(plm_fsm_ri_timer_N_51436), + .I1(plm_fsm_ri_timer_N_51438), + .I2(plm_fsm_ri_timer_N_51439), + .I3(plm_fsm_ri_timer_un1_expired_2ms_0_a2_0_a4_0_1030), + .O(plm_fsm_N_51392) + ); + FDC plm_fsm_ri_timer_reg_count_22_ ( + .C(mgt_clk), + .D(plm_fsm_ri_timer_reg_count_s[22]), + .Q(plm_fsm_ri_timer_reg_count[22]), + .CLR(plm_rst) + ); + FDC plm_fsm_ri_timer_reg_count_21_ ( + .C(mgt_clk), + .D(plm_fsm_ri_timer_reg_count_s[21]), + .Q(plm_fsm_ri_timer_reg_count[21]), + .CLR(plm_rst) + ); + FDC plm_fsm_ri_timer_reg_count_20_ ( + .C(mgt_clk), + .D(plm_fsm_ri_timer_reg_count_s[20]), + .Q(plm_fsm_ri_timer_reg_count[20]), + .CLR(plm_rst) + ); + FDC plm_fsm_ri_timer_reg_count_19_ ( + .C(mgt_clk), + .D(plm_fsm_ri_timer_reg_count_s[19]), + .Q(plm_fsm_ri_timer_reg_count[19]), + .CLR(plm_rst) + ); + FDC plm_fsm_ri_timer_reg_count_18_ ( + .C(mgt_clk), + .D(plm_fsm_ri_timer_reg_count_s[18]), + .Q(plm_fsm_ri_timer_reg_count[18]), + .CLR(plm_rst) + ); + FDC plm_fsm_ri_timer_reg_count_17_ ( + .C(mgt_clk), + .D(plm_fsm_ri_timer_reg_count_s[17]), + .Q(plm_fsm_ri_timer_reg_count[17]), + .CLR(plm_rst) + ); + FDC plm_fsm_ri_timer_reg_count_16_ ( + .C(mgt_clk), + .D(plm_fsm_ri_timer_reg_count_s[16]), + .Q(plm_fsm_ri_timer_reg_count[16]), + .CLR(plm_rst) + ); + FDC plm_fsm_ri_timer_reg_count_15_ ( + .C(mgt_clk), + .D(plm_fsm_ri_timer_reg_count_s[15]), + .Q(plm_fsm_ri_timer_reg_count[15]), + .CLR(plm_rst) + ); + FDC plm_fsm_ri_timer_reg_count_14_ ( + .C(mgt_clk), + .D(plm_fsm_ri_timer_reg_count_s[14]), + .Q(plm_fsm_ri_timer_reg_count[14]), + .CLR(plm_rst) + ); + FDC plm_fsm_ri_timer_reg_count_13_ ( + .C(mgt_clk), + .D(plm_fsm_ri_timer_reg_count_s[13]), + .Q(plm_fsm_ri_timer_reg_count[13]), + .CLR(plm_rst) + ); + FDC plm_fsm_ri_timer_reg_count_12_ ( + .C(mgt_clk), + .D(plm_fsm_ri_timer_reg_count_s[12]), + .Q(plm_fsm_ri_timer_reg_count[12]), + .CLR(plm_rst) + ); + FDC plm_fsm_ri_timer_reg_count_11_ ( + .C(mgt_clk), + .D(plm_fsm_ri_timer_reg_count_s[11]), + .Q(plm_fsm_ri_timer_reg_count[11]), + .CLR(plm_rst) + ); + FDC plm_fsm_ri_timer_reg_count_10_ ( + .C(mgt_clk), + .D(plm_fsm_ri_timer_reg_count_s[10]), + .Q(plm_fsm_ri_timer_reg_count[10]), + .CLR(plm_rst) + ); + FDC plm_fsm_ri_timer_reg_count_9_ ( + .C(mgt_clk), + .D(plm_fsm_ri_timer_reg_count_s[9]), + .Q(plm_fsm_ri_timer_reg_count[9]), + .CLR(plm_rst) + ); + FDC plm_fsm_ri_timer_reg_count_8_ ( + .C(mgt_clk), + .D(plm_fsm_ri_timer_reg_count_s[8]), + .Q(plm_fsm_ri_timer_reg_count[8]), + .CLR(plm_rst) + ); + FDC plm_fsm_ri_timer_reg_count_7_ ( + .C(mgt_clk), + .D(plm_fsm_ri_timer_reg_count_s[7]), + .Q(plm_fsm_ri_timer_reg_count[7]), + .CLR(plm_rst) + ); + FDC plm_fsm_ri_timer_reg_count_6_ ( + .C(mgt_clk), + .D(plm_fsm_ri_timer_reg_count_s[6]), + .Q(plm_fsm_ri_timer_reg_count[6]), + .CLR(plm_rst) + ); + FDC plm_fsm_ri_timer_reg_count_5_ ( + .C(mgt_clk), + .D(plm_fsm_ri_timer_reg_count_s[5]), + .Q(plm_fsm_ri_timer_reg_count[5]), + .CLR(plm_rst) + ); + FDC plm_fsm_ri_timer_reg_count_4_ ( + .C(mgt_clk), + .D(plm_fsm_ri_timer_reg_count_s[4]), + .Q(plm_fsm_ri_timer_reg_count[4]), + .CLR(plm_rst) + ); + FDC plm_fsm_ri_timer_reg_count_3_ ( + .C(mgt_clk), + .D(plm_fsm_ri_timer_reg_count_s[3]), + .Q(plm_fsm_ri_timer_reg_count[3]), + .CLR(plm_rst) + ); + FDC plm_fsm_ri_timer_reg_count_2_ ( + .C(mgt_clk), + .D(plm_fsm_ri_timer_reg_count_s[2]), + .Q(plm_fsm_ri_timer_reg_count[2]), + .CLR(plm_rst) + ); + FDC plm_fsm_ri_timer_reg_count_1_ ( + .C(mgt_clk), + .D(plm_fsm_ri_timer_reg_count_s[1]), + .Q(plm_fsm_ri_timer_reg_count[1]), + .CLR(plm_rst) + ); + FDC plm_fsm_ri_timer_reg_count_0_ ( + .C(mgt_clk), + .D(plm_fsm_ri_timer_reg_count_s[0]), + .Q(plm_fsm_ri_timer_reg_count[0]), + .CLR(plm_rst) + ); + defparam plm_fsm_ri_timer_reg_count_qxu_0_0_.INIT = 4'h8; + LUT2_L plm_fsm_ri_timer_reg_count_qxu_0_0_ ( + .I0(plm_fsm_reg_state_16__357), + .I1(plm_fsm_ri_timer_reg_count[0]), + .LO(plm_fsm_ri_timer_reg_count_qxu[0]) + ); + defparam plm_fsm_ri_timer_reg_count_qxu_0_1_.INIT = 4'h8; + LUT2_L plm_fsm_ri_timer_reg_count_qxu_0_1_ ( + .I0(plm_fsm_reg_state_16__357), + .I1(plm_fsm_ri_timer_reg_count[1]), + .LO(plm_fsm_ri_timer_reg_count_qxu[1]) + ); + defparam plm_fsm_ri_timer_reg_count_qxu_0_2_.INIT = 4'h8; + LUT2_L plm_fsm_ri_timer_reg_count_qxu_0_2_ ( + .I0(plm_fsm_reg_state_16__357), + .I1(plm_fsm_ri_timer_reg_count[2]), + .LO(plm_fsm_ri_timer_reg_count_qxu[2]) + ); + defparam plm_fsm_ri_timer_reg_count_qxu_0_3_.INIT = 4'h8; + LUT2_L plm_fsm_ri_timer_reg_count_qxu_0_3_ ( + .I0(plm_fsm_reg_state_16__357), + .I1(plm_fsm_ri_timer_reg_count[3]), + .LO(plm_fsm_ri_timer_reg_count_qxu[3]) + ); + defparam plm_fsm_ri_timer_reg_count_qxu_0_4_.INIT = 4'h8; + LUT2_L plm_fsm_ri_timer_reg_count_qxu_0_4_ ( + .I0(plm_fsm_reg_state_16__357), + .I1(plm_fsm_ri_timer_reg_count[4]), + .LO(plm_fsm_ri_timer_reg_count_qxu[4]) + ); + defparam plm_fsm_ri_timer_reg_count_qxu_0_5_.INIT = 4'h8; + LUT2_L plm_fsm_ri_timer_reg_count_qxu_0_5_ ( + .I0(plm_fsm_reg_state_16__357), + .I1(plm_fsm_ri_timer_reg_count[5]), + .LO(plm_fsm_ri_timer_reg_count_qxu[5]) + ); + defparam plm_fsm_ri_timer_reg_count_qxu_0_6_.INIT = 4'h8; + LUT2_L plm_fsm_ri_timer_reg_count_qxu_0_6_ ( + .I0(plm_fsm_reg_state_16__357), + .I1(plm_fsm_ri_timer_reg_count[6]), + .LO(plm_fsm_ri_timer_reg_count_qxu[6]) + ); + defparam plm_fsm_ri_timer_reg_count_qxu_0_7_.INIT = 4'h8; + LUT2_L plm_fsm_ri_timer_reg_count_qxu_0_7_ ( + .I0(plm_fsm_reg_state_16__357), + .I1(plm_fsm_ri_timer_reg_count[7]), + .LO(plm_fsm_ri_timer_reg_count_qxu[7]) + ); + defparam plm_fsm_ri_timer_reg_count_qxu_0_8_.INIT = 4'h8; + LUT2_L plm_fsm_ri_timer_reg_count_qxu_0_8_ ( + .I0(plm_fsm_reg_state_16__357), + .I1(plm_fsm_ri_timer_reg_count[8]), + .LO(plm_fsm_ri_timer_reg_count_qxu[8]) + ); + defparam plm_fsm_ri_timer_reg_count_qxu_0_9_.INIT = 4'h8; + LUT2_L plm_fsm_ri_timer_reg_count_qxu_0_9_ ( + .I0(plm_fsm_reg_state_16__357), + .I1(plm_fsm_ri_timer_reg_count[9]), + .LO(plm_fsm_ri_timer_reg_count_qxu[9]) + ); + defparam plm_fsm_ri_timer_reg_count_qxu_0_10_.INIT = 4'h8; + LUT2_L plm_fsm_ri_timer_reg_count_qxu_0_10_ ( + .I0(plm_fsm_reg_state_16__357), + .I1(plm_fsm_ri_timer_reg_count[10]), + .LO(plm_fsm_ri_timer_reg_count_qxu[10]) + ); + defparam plm_fsm_ri_timer_reg_count_qxu_0_11_.INIT = 4'h8; + LUT2_L plm_fsm_ri_timer_reg_count_qxu_0_11_ ( + .I0(plm_fsm_reg_state_16__357), + .I1(plm_fsm_ri_timer_reg_count[11]), + .LO(plm_fsm_ri_timer_reg_count_qxu[11]) + ); + defparam plm_fsm_ri_timer_reg_count_qxu_0_12_.INIT = 4'h8; + LUT2_L plm_fsm_ri_timer_reg_count_qxu_0_12_ ( + .I0(plm_fsm_reg_state_16__357), + .I1(plm_fsm_ri_timer_reg_count[12]), + .LO(plm_fsm_ri_timer_reg_count_qxu[12]) + ); + defparam plm_fsm_ri_timer_reg_count_qxu_0_13_.INIT = 4'h8; + LUT2_L plm_fsm_ri_timer_reg_count_qxu_0_13_ ( + .I0(plm_fsm_reg_state_16__357), + .I1(plm_fsm_ri_timer_reg_count[13]), + .LO(plm_fsm_ri_timer_reg_count_qxu[13]) + ); + defparam plm_fsm_ri_timer_reg_count_qxu_0_14_.INIT = 4'h8; + LUT2_L plm_fsm_ri_timer_reg_count_qxu_0_14_ ( + .I0(plm_fsm_reg_state_16__357), + .I1(plm_fsm_ri_timer_reg_count[14]), + .LO(plm_fsm_ri_timer_reg_count_qxu[14]) + ); + defparam plm_fsm_ri_timer_reg_count_qxu_0_15_.INIT = 4'h8; + LUT2_L plm_fsm_ri_timer_reg_count_qxu_0_15_ ( + .I0(plm_fsm_reg_state_16__357), + .I1(plm_fsm_ri_timer_reg_count[15]), + .LO(plm_fsm_ri_timer_reg_count_qxu[15]) + ); + defparam plm_fsm_ri_timer_reg_count_qxu_0_16_.INIT = 4'h8; + LUT2_L plm_fsm_ri_timer_reg_count_qxu_0_16_ ( + .I0(plm_fsm_reg_state_16__357), + .I1(plm_fsm_ri_timer_reg_count[16]), + .LO(plm_fsm_ri_timer_reg_count_qxu[16]) + ); + defparam plm_fsm_ri_timer_reg_count_qxu_0_17_.INIT = 4'h8; + LUT2_L plm_fsm_ri_timer_reg_count_qxu_0_17_ ( + .I0(plm_fsm_reg_state_16__357), + .I1(plm_fsm_ri_timer_reg_count[17]), + .LO(plm_fsm_ri_timer_reg_count_qxu[17]) + ); + defparam plm_fsm_ri_timer_reg_count_qxu_0_18_.INIT = 4'h8; + LUT2_L plm_fsm_ri_timer_reg_count_qxu_0_18_ ( + .I0(plm_fsm_reg_state_16__357), + .I1(plm_fsm_ri_timer_reg_count[18]), + .LO(plm_fsm_ri_timer_reg_count_qxu[18]) + ); + defparam plm_fsm_ri_timer_reg_count_qxu_0_19_.INIT = 4'h8; + LUT2_L plm_fsm_ri_timer_reg_count_qxu_0_19_ ( + .I0(plm_fsm_reg_state_16__357), + .I1(plm_fsm_ri_timer_reg_count[19]), + .LO(plm_fsm_ri_timer_reg_count_qxu[19]) + ); + defparam plm_fsm_ri_timer_reg_count_qxu_0_20_.INIT = 4'h8; + LUT2_L plm_fsm_ri_timer_reg_count_qxu_0_20_ ( + .I0(plm_fsm_reg_state_16__357), + .I1(plm_fsm_ri_timer_reg_count[20]), + .LO(plm_fsm_ri_timer_reg_count_qxu[20]) + ); + defparam plm_fsm_ri_timer_reg_count_qxu_0_21_.INIT = 4'h8; + LUT2_L plm_fsm_ri_timer_reg_count_qxu_0_21_ ( + .I0(plm_fsm_reg_state_16__357), + .I1(plm_fsm_ri_timer_reg_count[21]), + .LO(plm_fsm_ri_timer_reg_count_qxu[21]) + ); + defparam plm_fsm_ri_timer_reg_count_qxu_0_22_.INIT = 4'h8; + LUT2_L plm_fsm_ri_timer_reg_count_qxu_0_22_ ( + .I0(plm_fsm_reg_state_16__357), + .I1(plm_fsm_ri_timer_reg_count[22]), + .LO(plm_fsm_ri_timer_reg_count_qxu[22]) + ); + VCC plm_fsm_ri_counter0_VCC ( + .P(plm_fsm_ri_counter0_VCC_1031) + ); + MUXCY_L plm_fsm_ri_counter0_reg_rx_count_cry_0_ ( + .CI(N_38692_i_28), + .DI(plm_fsm_ri_counter0_VCC_1031), + .LO(plm_fsm_ri_counter0_reg_rx_count_cry[0]), + .S(plm_fsm_ri_counter0_reg_rx_count_qxu[0]) + ); + XORCY plm_fsm_ri_counter0_reg_rx_count_s_0_ ( + .CI(N_38692_i_28), + .LI(plm_fsm_ri_counter0_reg_rx_count_qxu[0]), + .O(plm_fsm_ri_counter0_reg_rx_count_s[0]) + ); + MUXCY_L plm_fsm_ri_counter0_reg_rx_count_cry_1_ ( + .CI(plm_fsm_ri_counter0_reg_rx_count_cry[0]), + .DI(plm_fsm_ri_counter0_VCC_1031), + .LO(plm_fsm_ri_counter0_reg_rx_count_cry[1]), + .S(plm_fsm_ri_counter0_reg_rx_count_qxu[1]) + ); + XORCY plm_fsm_ri_counter0_reg_rx_count_s_1_ ( + .CI(plm_fsm_ri_counter0_reg_rx_count_cry[0]), + .LI(plm_fsm_ri_counter0_reg_rx_count_qxu[1]), + .O(plm_fsm_ri_counter0_reg_rx_count_s[1]) + ); + MUXCY_L plm_fsm_ri_counter0_reg_rx_count_cry_2_ ( + .CI(plm_fsm_ri_counter0_reg_rx_count_cry[1]), + .DI(plm_fsm_ri_counter0_VCC_1031), + .LO(plm_fsm_ri_counter0_reg_rx_count_cry[2]), + .S(plm_fsm_ri_counter0_reg_rx_count_qxu[2]) + ); + XORCY plm_fsm_ri_counter0_reg_rx_count_s_2_ ( + .CI(plm_fsm_ri_counter0_reg_rx_count_cry[1]), + .LI(plm_fsm_ri_counter0_reg_rx_count_qxu[2]), + .O(plm_fsm_ri_counter0_reg_rx_count_s[2]) + ); + MUXCY_L plm_fsm_ri_counter0_reg_rx_count_cry_3_ ( + .CI(plm_fsm_ri_counter0_reg_rx_count_cry[2]), + .DI(plm_fsm_ri_counter0_VCC_1031), + .LO(plm_fsm_ri_counter0_reg_rx_count_cry[3]), + .S(plm_fsm_ri_counter0_reg_rx_count_qxu[3]) + ); + XORCY plm_fsm_ri_counter0_reg_rx_count_s_3_ ( + .CI(plm_fsm_ri_counter0_reg_rx_count_cry[2]), + .LI(plm_fsm_ri_counter0_reg_rx_count_qxu[3]), + .O(plm_fsm_ri_counter0_reg_rx_count_s[3]) + ); + MUXCY_L plm_fsm_ri_counter0_reg_rx_count_cry_4_ ( + .CI(plm_fsm_ri_counter0_reg_rx_count_cry[3]), + .DI(plm_fsm_ri_counter0_VCC_1031), + .LO(plm_fsm_ri_counter0_reg_rx_count_cry[4]), + .S(plm_fsm_ri_counter0_reg_rx_count_qxu[4]) + ); + XORCY plm_fsm_ri_counter0_reg_rx_count_s_4_ ( + .CI(plm_fsm_ri_counter0_reg_rx_count_cry[3]), + .LI(plm_fsm_ri_counter0_reg_rx_count_qxu[4]), + .O(plm_fsm_ri_counter0_reg_rx_count_s[4]) + ); + MUXCY_L plm_fsm_ri_counter0_reg_rx_count_cry_5_ ( + .CI(plm_fsm_ri_counter0_reg_rx_count_cry[4]), + .DI(plm_fsm_ri_counter0_VCC_1031), + .LO(plm_fsm_ri_counter0_reg_rx_count_cry[5]), + .S(plm_fsm_ri_counter0_reg_rx_count_qxu[5]) + ); + XORCY plm_fsm_ri_counter0_reg_rx_count_s_5_ ( + .CI(plm_fsm_ri_counter0_reg_rx_count_cry[4]), + .LI(plm_fsm_ri_counter0_reg_rx_count_qxu[5]), + .O(plm_fsm_ri_counter0_reg_rx_count_s[5]) + ); + MUXCY_L plm_fsm_ri_counter0_reg_rx_count_cry_6_ ( + .CI(plm_fsm_ri_counter0_reg_rx_count_cry[5]), + .DI(plm_fsm_ri_counter0_VCC_1031), + .LO(plm_fsm_ri_counter0_reg_rx_count_cry[6]), + .S(plm_fsm_ri_counter0_reg_rx_count_qxu[6]) + ); + XORCY plm_fsm_ri_counter0_reg_rx_count_s_6_ ( + .CI(plm_fsm_ri_counter0_reg_rx_count_cry[5]), + .LI(plm_fsm_ri_counter0_reg_rx_count_qxu[6]), + .O(plm_fsm_ri_counter0_reg_rx_count_s[6]) + ); + XORCY plm_fsm_ri_counter0_reg_rx_count_s_7_ ( + .CI(plm_fsm_ri_counter0_reg_rx_count_cry[6]), + .LI(plm_fsm_ri_counter0_reg_rx_count_qxu[7]), + .O(plm_fsm_ri_counter0_reg_rx_count_s[7]) + ); + MUXCY_L plm_fsm_ri_counter0_reg_tx_count_cry_0_ ( + .CI(plm_fsm_ri_counter0_N_38649_i_1032), + .DI(plm_fsm_ri_counter0_VCC_1031), + .LO(plm_fsm_ri_counter0_reg_tx_count_cry[0]), + .S(plm_fsm_ri_counter0_reg_tx_count_qxu[0]) + ); + XORCY plm_fsm_ri_counter0_reg_tx_count_s_0_ ( + .CI(plm_fsm_ri_counter0_N_38649_i_1032), + .LI(plm_fsm_ri_counter0_reg_tx_count_qxu[0]), + .O(plm_fsm_ri_counter0_reg_tx_count_s[0]) + ); + MUXCY_L plm_fsm_ri_counter0_reg_tx_count_cry_1_ ( + .CI(plm_fsm_ri_counter0_reg_tx_count_cry[0]), + .DI(plm_fsm_ri_counter0_VCC_1031), + .LO(plm_fsm_ri_counter0_reg_tx_count_cry[1]), + .S(plm_fsm_ri_counter0_reg_tx_count_qxu[1]) + ); + XORCY plm_fsm_ri_counter0_reg_tx_count_s_1_ ( + .CI(plm_fsm_ri_counter0_reg_tx_count_cry[0]), + .LI(plm_fsm_ri_counter0_reg_tx_count_qxu[1]), + .O(plm_fsm_ri_counter0_reg_tx_count_s[1]) + ); + MUXCY_L plm_fsm_ri_counter0_reg_tx_count_cry_2_ ( + .CI(plm_fsm_ri_counter0_reg_tx_count_cry[1]), + .DI(plm_fsm_ri_counter0_VCC_1031), + .LO(plm_fsm_ri_counter0_reg_tx_count_cry[2]), + .S(plm_fsm_ri_counter0_reg_tx_count_qxu[2]) + ); + XORCY plm_fsm_ri_counter0_reg_tx_count_s_2_ ( + .CI(plm_fsm_ri_counter0_reg_tx_count_cry[1]), + .LI(plm_fsm_ri_counter0_reg_tx_count_qxu[2]), + .O(plm_fsm_ri_counter0_reg_tx_count_s[2]) + ); + MUXCY_L plm_fsm_ri_counter0_reg_tx_count_cry_3_ ( + .CI(plm_fsm_ri_counter0_reg_tx_count_cry[2]), + .DI(plm_fsm_ri_counter0_VCC_1031), + .LO(plm_fsm_ri_counter0_reg_tx_count_cry[3]), + .S(plm_fsm_ri_counter0_reg_tx_count_qxu[3]) + ); + XORCY plm_fsm_ri_counter0_reg_tx_count_s_3_ ( + .CI(plm_fsm_ri_counter0_reg_tx_count_cry[2]), + .LI(plm_fsm_ri_counter0_reg_tx_count_qxu[3]), + .O(plm_fsm_ri_counter0_reg_tx_count_s[3]) + ); + MUXCY_L plm_fsm_ri_counter0_reg_tx_count_cry_4_ ( + .CI(plm_fsm_ri_counter0_reg_tx_count_cry[3]), + .DI(plm_fsm_ri_counter0_VCC_1031), + .LO(plm_fsm_ri_counter0_reg_tx_count_cry[4]), + .S(plm_fsm_ri_counter0_reg_tx_count_qxu[4]) + ); + XORCY plm_fsm_ri_counter0_reg_tx_count_s_4_ ( + .CI(plm_fsm_ri_counter0_reg_tx_count_cry[3]), + .LI(plm_fsm_ri_counter0_reg_tx_count_qxu[4]), + .O(plm_fsm_ri_counter0_reg_tx_count_s[4]) + ); + MUXCY_L plm_fsm_ri_counter0_reg_tx_count_cry_5_ ( + .CI(plm_fsm_ri_counter0_reg_tx_count_cry[4]), + .DI(plm_fsm_ri_counter0_VCC_1031), + .LO(plm_fsm_ri_counter0_reg_tx_count_cry[5]), + .S(plm_fsm_ri_counter0_reg_tx_count_qxu[5]) + ); + XORCY plm_fsm_ri_counter0_reg_tx_count_s_5_ ( + .CI(plm_fsm_ri_counter0_reg_tx_count_cry[4]), + .LI(plm_fsm_ri_counter0_reg_tx_count_qxu[5]), + .O(plm_fsm_ri_counter0_reg_tx_count_s[5]) + ); + MUXCY_L plm_fsm_ri_counter0_reg_tx_count_cry_6_ ( + .CI(plm_fsm_ri_counter0_reg_tx_count_cry[5]), + .DI(plm_fsm_ri_counter0_VCC_1031), + .LO(plm_fsm_ri_counter0_reg_tx_count_cry[6]), + .S(plm_fsm_ri_counter0_reg_tx_count_qxu[6]) + ); + XORCY plm_fsm_ri_counter0_reg_tx_count_s_6_ ( + .CI(plm_fsm_ri_counter0_reg_tx_count_cry[5]), + .LI(plm_fsm_ri_counter0_reg_tx_count_qxu[6]), + .O(plm_fsm_ri_counter0_reg_tx_count_s[6]) + ); + XORCY plm_fsm_ri_counter0_reg_tx_count_s_7_ ( + .CI(plm_fsm_ri_counter0_reg_tx_count_cry[6]), + .LI(plm_fsm_ri_counter0_reg_tx_count_qxu[7]), + .O(plm_fsm_ri_counter0_reg_tx_count_s[7]) + ); + defparam plm_fsm_ri_counter0_un1_enable_4_i_0_0_a4_1.INIT = 4'h2; + LUT2 plm_fsm_ri_counter0_un1_enable_4_i_0_0_a4_1 ( + .I0(plm_reg_rx_idl_1), + .I1(plm_rx0_idl_c), + .O(plm_fsm_N_38476_1) + ); + defparam plm_fsm_ri_counter0_oneshot_monitor_un1_enable_0_a2_0_a2_0_a4.INIT = 4'h4; + LUT2 plm_fsm_ri_counter0_oneshot_monitor_un1_enable_0_a2_0_a2_0_a4 ( + .I0(plm_reg_rx_idl_1), + .I1(plm_fsm_reg_state_16__357), + .O(plm_fsm_ri_counter0_un1_enable_0_a2_0_a2_0_a4) + ); + defparam plm_fsm_ri_counter0_loadable_tx_counter_reg_tx_count17_0_a2_0_a2_0_a4.INIT = 4'h8; + LUT2 plm_fsm_ri_counter0_loadable_tx_counter_reg_tx_count17_0_a2_0_a2_0_a4 ( + .I0(plm_fsm_reg_state_16__357), + .I1(plm_fsm_ri_counter0_reg_oneshot_1034), + .O(plm_fsm_ri_counter0_reg_tx_count17_0_a2_0_a2_0_a4) + ); + defparam plm_fsm_ri_counter0_un1_enable_1_0_a2_0_a2_0_a4.INIT = 4'h2; + LUT2 plm_fsm_ri_counter0_un1_enable_1_0_a2_0_a2_0_a4 ( + .I0(plm_fsm_ri_counter0_reg_tx_count17_0_a2_0_a2_0_a4), + .I1(plm_fsm_ri_counter0_reg_tx_expired_1036), + .O(plm_fsm_ri_counter0_un1_enable_1_0_a2_0_a2_0_a4_0) + ); + defparam plm_fsm_ri_counter0_loadable_tx_counter_un1_reg_tx_count_0_a2_0_a4_4.INIT = 16'h0001; + LUT4 plm_fsm_ri_counter0_loadable_tx_counter_un1_reg_tx_count_0_a2_0_a4_4 ( + .I0(plm_fsm_ri_counter0_reg_tx_count[0]), + .I1(plm_fsm_ri_counter0_reg_tx_count[1]), + .I2(plm_fsm_ri_counter0_reg_tx_count[2]), + .I3(plm_fsm_ri_counter0_reg_tx_count[3]), + .O(plm_fsm_ri_counter0_un1_reg_tx_count_0_a2_0_a4_4) + ); + defparam plm_fsm_ri_counter0_loadable_tx_counter_un1_reg_tx_count_0_a2_0_a4_5.INIT = 16'h0001; + LUT4 plm_fsm_ri_counter0_loadable_tx_counter_un1_reg_tx_count_0_a2_0_a4_5 ( + .I0(plm_fsm_ri_counter0_reg_tx_count[4]), + .I1(plm_fsm_ri_counter0_reg_tx_count[5]), + .I2(plm_fsm_ri_counter0_reg_tx_count[6]), + .I3(plm_fsm_ri_counter0_reg_tx_count[7]), + .O(plm_fsm_ri_counter0_un1_reg_tx_count_0_a2_0_a4_5) + ); + defparam plm_fsm_ri_counter0_loadable_rx_counter_un1_reg_rx_count_4.INIT = 16'h0001; + LUT4 plm_fsm_ri_counter0_loadable_rx_counter_un1_reg_rx_count_4 ( + .I0(plm_fsm_ri_counter0_reg_rx_count[0]), + .I1(plm_fsm_ri_counter0_reg_rx_count[1]), + .I2(plm_fsm_ri_counter0_reg_rx_count[2]), + .I3(plm_fsm_ri_counter0_reg_rx_count[3]), + .O(plm_fsm_ri_counter0_un1_reg_rx_count_4) + ); + defparam plm_fsm_ri_counter0_loadable_rx_counter_un1_reg_rx_count_5.INIT = 16'h0001; + LUT4 plm_fsm_ri_counter0_loadable_rx_counter_un1_reg_rx_count_5 ( + .I0(plm_fsm_ri_counter0_reg_rx_count[4]), + .I1(plm_fsm_ri_counter0_reg_rx_count[5]), + .I2(plm_fsm_ri_counter0_reg_rx_count[6]), + .I3(plm_fsm_ri_counter0_reg_rx_count[7]), + .O(plm_fsm_ri_counter0_un1_reg_rx_count_5) + ); + defparam plm_fsm_ri_counter0_N_69078_i.INIT = 8'h3B; + LUT3_L plm_fsm_ri_counter0_N_69078_i ( + .I0(plm_fsm_N_38476_1), + .I1(plm_fsm_reg_state_16__357), + .I2(plm_fsm_ri_counter0_reg_rx_expired_358), + .LO(plm_fsm_ri_counter0_N_69078_i_1037) + ); + defparam plm_fsm_ri_counter0_N_38664_i.INIT = 4'hB; + LUT2 plm_fsm_ri_counter0_N_38664_i ( + .I0(plm_reg_sym_sent_0_), + .I1(plm_fsm_ri_counter0_un1_enable_1_0_a2_0_a2_0_a4_0), + .O(plm_fsm_ri_counter0_N_38664_i_1033) + ); + defparam plm_fsm_ri_counter0_N_38651_i.INIT = 8'hD5; + LUT3 plm_fsm_ri_counter0_N_38651_i ( + .I0(plm_fsm_ri_counter0_reg_tx_count17_0_a2_0_a2_0_a4), + .I1(plm_fsm_ri_counter0_un1_reg_tx_count_0_a2_0_a4_4), + .I2(plm_fsm_ri_counter0_un1_reg_tx_count_0_a2_0_a4_5), + .O(plm_fsm_ri_counter0_N_38651_i_1035) + ); + defparam plm_fsm_ri_counter0_loadable_rx_counter_N_9853_i.INIT = 8'hD5; + LUT3 plm_fsm_ri_counter0_loadable_rx_counter_N_9853_i ( + .I0(plm_fsm_reg_state_16__357), + .I1(plm_fsm_ri_counter0_un1_reg_rx_count_4), + .I2(plm_fsm_ri_counter0_un1_reg_rx_count_5), + .O(plm_fsm_ri_counter0_N_9853_i) + ); + defparam plm_fsm_ri_counter0_flagit_reg_expired_5_0_a2_0_a2_0_a4.INIT = 8'h80; + LUT3_L plm_fsm_ri_counter0_flagit_reg_expired_5_0_a2_0_a2_0_a4 ( + .I0(plm_fsm_reg_state_16__357), + .I1(plm_fsm_ri_counter0_reg_rx_expired_358), + .I2(plm_fsm_ri_counter0_reg_tx_expired_1036), + .LO(plm_fsm_ri_counter0_reg_expired_5) + ); + defparam plm_fsm_ri_counter0_loadable_rx_counter_N_38694_i.INIT = 8'hFB; + LUT3 plm_fsm_ri_counter0_loadable_rx_counter_N_38694_i ( + .I0(plm_fsm_ri_counter0_reg_rx_expired_358), + .I1(plm_fsm_reg_state_16__357), + .I2(plm_reg_rx_idl_1), + .O(plm_fsm_ri_counter0_N_38694_i) + ); + defparam plm_fsm_ri_counter0_N_38649_i.INIT = 4'hB; + LUT2 plm_fsm_ri_counter0_N_38649_i ( + .I0(plm_fsm_ri_counter0_reg_tx_expired_1036), + .I1(plm_fsm_ri_counter0_reg_tx_count17_0_a2_0_a2_0_a4), + .O(plm_fsm_ri_counter0_N_38649_i_1032) + ); + FDCE plm_fsm_ri_counter0_reg_tx_count_7_ ( + .CE(plm_fsm_ri_counter0_N_38664_i_1033), + .C(mgt_clk), + .D(plm_fsm_ri_counter0_reg_tx_count_s[7]), + .Q(plm_fsm_ri_counter0_reg_tx_count[7]), + .CLR(plm_rst) + ); + FDCE plm_fsm_ri_counter0_reg_tx_count_6_ ( + .CE(plm_fsm_ri_counter0_N_38664_i_1033), + .C(mgt_clk), + .D(plm_fsm_ri_counter0_reg_tx_count_s[6]), + .Q(plm_fsm_ri_counter0_reg_tx_count[6]), + .CLR(plm_rst) + ); + FDCE plm_fsm_ri_counter0_reg_tx_count_5_ ( + .CE(plm_fsm_ri_counter0_N_38664_i_1033), + .C(mgt_clk), + .D(plm_fsm_ri_counter0_reg_tx_count_s[5]), + .Q(plm_fsm_ri_counter0_reg_tx_count[5]), + .CLR(plm_rst) + ); + FDCE plm_fsm_ri_counter0_reg_tx_count_4_ ( + .CE(plm_fsm_ri_counter0_N_38664_i_1033), + .C(mgt_clk), + .D(plm_fsm_ri_counter0_reg_tx_count_s[4]), + .Q(plm_fsm_ri_counter0_reg_tx_count[4]), + .CLR(plm_rst) + ); + FDPE plm_fsm_ri_counter0_reg_tx_count_3_ ( + .PRE(plm_rst), + .CE(plm_fsm_ri_counter0_N_38664_i_1033), + .C(mgt_clk), + .D(plm_fsm_ri_counter0_reg_tx_count_s[3]), + .Q(plm_fsm_ri_counter0_reg_tx_count[3]) + ); + FDCE plm_fsm_ri_counter0_reg_tx_count_2_ ( + .CE(plm_fsm_ri_counter0_N_38664_i_1033), + .C(mgt_clk), + .D(plm_fsm_ri_counter0_reg_tx_count_s[2]), + .Q(plm_fsm_ri_counter0_reg_tx_count[2]), + .CLR(plm_rst) + ); + FDCE plm_fsm_ri_counter0_reg_tx_count_1_ ( + .CE(plm_fsm_ri_counter0_N_38664_i_1033), + .C(mgt_clk), + .D(plm_fsm_ri_counter0_reg_tx_count_s[1]), + .Q(plm_fsm_ri_counter0_reg_tx_count[1]), + .CLR(plm_rst) + ); + FDCE plm_fsm_ri_counter0_reg_tx_count_0_ ( + .CE(plm_fsm_ri_counter0_N_38664_i_1033), + .C(mgt_clk), + .D(plm_fsm_ri_counter0_reg_tx_count_s[0]), + .Q(plm_fsm_ri_counter0_reg_tx_count[0]), + .CLR(plm_rst) + ); + FDCE plm_fsm_ri_counter0_reg_rx_count_7_ ( + .CE(plm_fsm_ri_counter0_N_38694_i), + .C(mgt_clk), + .D(plm_fsm_ri_counter0_reg_rx_count_s[7]), + .Q(plm_fsm_ri_counter0_reg_rx_count[7]), + .CLR(plm_rst) + ); + FDCE plm_fsm_ri_counter0_reg_rx_count_6_ ( + .CE(plm_fsm_ri_counter0_N_38694_i), + .C(mgt_clk), + .D(plm_fsm_ri_counter0_reg_rx_count_s[6]), + .Q(plm_fsm_ri_counter0_reg_rx_count[6]), + .CLR(plm_rst) + ); + FDCE plm_fsm_ri_counter0_reg_rx_count_5_ ( + .CE(plm_fsm_ri_counter0_N_38694_i), + .C(mgt_clk), + .D(plm_fsm_ri_counter0_reg_rx_count_s[5]), + .Q(plm_fsm_ri_counter0_reg_rx_count[5]), + .CLR(plm_rst) + ); + FDCE plm_fsm_ri_counter0_reg_rx_count_4_ ( + .CE(plm_fsm_ri_counter0_N_38694_i), + .C(mgt_clk), + .D(plm_fsm_ri_counter0_reg_rx_count_s[4]), + .Q(plm_fsm_ri_counter0_reg_rx_count[4]), + .CLR(plm_rst) + ); + FDCE plm_fsm_ri_counter0_reg_rx_count_3_ ( + .CE(plm_fsm_ri_counter0_N_38694_i), + .C(mgt_clk), + .D(plm_fsm_ri_counter0_reg_rx_count_s[3]), + .Q(plm_fsm_ri_counter0_reg_rx_count[3]), + .CLR(plm_rst) + ); + FDPE plm_fsm_ri_counter0_reg_rx_count_2_ ( + .PRE(plm_rst), + .CE(plm_fsm_ri_counter0_N_38694_i), + .C(mgt_clk), + .D(plm_fsm_ri_counter0_reg_rx_count_s[2]), + .Q(plm_fsm_ri_counter0_reg_rx_count[2]) + ); + FDCE plm_fsm_ri_counter0_reg_rx_count_1_ ( + .CE(plm_fsm_ri_counter0_N_38694_i), + .C(mgt_clk), + .D(plm_fsm_ri_counter0_reg_rx_count_s[1]), + .Q(plm_fsm_ri_counter0_reg_rx_count[1]), + .CLR(plm_rst) + ); + FDCE plm_fsm_ri_counter0_reg_rx_count_0_ ( + .CE(plm_fsm_ri_counter0_N_38694_i), + .C(mgt_clk), + .D(plm_fsm_ri_counter0_reg_rx_count_s[0]), + .Q(plm_fsm_ri_counter0_reg_rx_count[0]), + .CLR(plm_rst) + ); + FDC plm_fsm_ri_counter0_reg_expired ( + .C(mgt_clk), + .D(plm_fsm_ri_counter0_reg_expired_5), + .Q(plm_fsm_ri_cntrout0), + .CLR(plm_rst) + ); + FDCE plm_fsm_ri_counter0_reg_oneshot ( + .CE(plm_fsm_ri_counter0_N_38695_i), + .C(mgt_clk), + .D(plm_fsm_reg_state_16__357), + .Q(plm_fsm_ri_counter0_reg_oneshot_1034), + .CLR(plm_rst) + ); + FDCE plm_fsm_ri_counter0_reg_rx_expired ( + .CE(plm_fsm_ri_counter0_N_9853_i), + .C(mgt_clk), + .D(plm_fsm_reg_state_16__357), + .Q(plm_fsm_ri_counter0_reg_rx_expired_358), + .CLR(plm_rst) + ); + FDCE plm_fsm_ri_counter0_reg_tx_expired ( + .CE(plm_fsm_ri_counter0_N_38651_i_1035), + .C(mgt_clk), + .D(plm_fsm_ri_counter0_reg_tx_count17_0_a2_0_a2_0_a4), + .Q(plm_fsm_ri_counter0_reg_tx_expired_1036), + .CLR(plm_rst) + ); + INV plm_fsm_ri_counter0_oneshot_monitor_N_38695_i ( + .I(plm_fsm_ri_counter0_un1_enable_0_a2_0_a2_0_a4), + .O(plm_fsm_ri_counter0_N_38695_i) + ); + defparam plm_fsm_ri_counter0_reg_rx_count_qxu_0_0_.INIT = 4'h7; + LUT2_L plm_fsm_ri_counter0_reg_rx_count_qxu_0_0_ ( + .I0(I_5137_0_a2_0_a2_0_a4_27), + .I1(plm_fsm_ri_counter0_reg_rx_count[0]), + .LO(plm_fsm_ri_counter0_reg_rx_count_qxu[0]) + ); + defparam plm_fsm_ri_counter0_reg_rx_count_qxu_0_1_.INIT = 4'h7; + LUT2_L plm_fsm_ri_counter0_reg_rx_count_qxu_0_1_ ( + .I0(I_5137_0_a2_0_a2_0_a4_27), + .I1(plm_fsm_ri_counter0_reg_rx_count[1]), + .LO(plm_fsm_ri_counter0_reg_rx_count_qxu[1]) + ); + defparam plm_fsm_ri_counter0_reg_rx_count_qxu_0_2_.INIT = 8'h1B; + LUT3_L plm_fsm_ri_counter0_reg_rx_count_qxu_0_2_ ( + .I0(I_5137_0_a2_0_a2_0_a4_27), + .I1(plm_fsm_ri_counter0_N_69078_i_1037), + .I2(plm_fsm_ri_counter0_reg_rx_count[2]), + .LO(plm_fsm_ri_counter0_reg_rx_count_qxu[2]) + ); + defparam plm_fsm_ri_counter0_reg_rx_count_qxu_0_3_.INIT = 4'h7; + LUT2_L plm_fsm_ri_counter0_reg_rx_count_qxu_0_3_ ( + .I0(I_5137_0_a2_0_a2_0_a4_27), + .I1(plm_fsm_ri_counter0_reg_rx_count[3]), + .LO(plm_fsm_ri_counter0_reg_rx_count_qxu[3]) + ); + defparam plm_fsm_ri_counter0_reg_rx_count_qxu_0_4_.INIT = 4'h7; + LUT2_L plm_fsm_ri_counter0_reg_rx_count_qxu_0_4_ ( + .I0(I_5137_0_a2_0_a2_0_a4_27), + .I1(plm_fsm_ri_counter0_reg_rx_count[4]), + .LO(plm_fsm_ri_counter0_reg_rx_count_qxu[4]) + ); + defparam plm_fsm_ri_counter0_reg_rx_count_qxu_0_5_.INIT = 4'h7; + LUT2_L plm_fsm_ri_counter0_reg_rx_count_qxu_0_5_ ( + .I0(I_5137_0_a2_0_a2_0_a4_27), + .I1(plm_fsm_ri_counter0_reg_rx_count[5]), + .LO(plm_fsm_ri_counter0_reg_rx_count_qxu[5]) + ); + defparam plm_fsm_ri_counter0_reg_rx_count_qxu_0_6_.INIT = 4'h7; + LUT2_L plm_fsm_ri_counter0_reg_rx_count_qxu_0_6_ ( + .I0(I_5137_0_a2_0_a2_0_a4_27), + .I1(plm_fsm_ri_counter0_reg_rx_count[6]), + .LO(plm_fsm_ri_counter0_reg_rx_count_qxu[6]) + ); + defparam plm_fsm_ri_counter0_reg_rx_count_qxu_0_7_.INIT = 4'h7; + LUT2_L plm_fsm_ri_counter0_reg_rx_count_qxu_0_7_ ( + .I0(I_5137_0_a2_0_a2_0_a4_27), + .I1(plm_fsm_ri_counter0_reg_rx_count[7]), + .LO(plm_fsm_ri_counter0_reg_rx_count_qxu[7]) + ); + defparam plm_fsm_ri_counter0_reg_tx_count_qxu_0_0_.INIT = 4'h7; + LUT2_L plm_fsm_ri_counter0_reg_tx_count_qxu_0_0_ ( + .I0(plm_fsm_ri_counter0_un1_enable_1_0_a2_0_a2_0_a4_0), + .I1(plm_fsm_ri_counter0_reg_tx_count[0]), + .LO(plm_fsm_ri_counter0_reg_tx_count_qxu[0]) + ); + defparam plm_fsm_ri_counter0_reg_tx_count_qxu_0_1_.INIT = 4'h7; + LUT2_L plm_fsm_ri_counter0_reg_tx_count_qxu_0_1_ ( + .I0(plm_fsm_ri_counter0_un1_enable_1_0_a2_0_a2_0_a4_0), + .I1(plm_fsm_ri_counter0_reg_tx_count[1]), + .LO(plm_fsm_ri_counter0_reg_tx_count_qxu[1]) + ); + defparam plm_fsm_ri_counter0_reg_tx_count_qxu_0_2_.INIT = 4'h7; + LUT2_L plm_fsm_ri_counter0_reg_tx_count_qxu_0_2_ ( + .I0(plm_fsm_ri_counter0_un1_enable_1_0_a2_0_a2_0_a4_0), + .I1(plm_fsm_ri_counter0_reg_tx_count[2]), + .LO(plm_fsm_ri_counter0_reg_tx_count_qxu[2]) + ); + defparam plm_fsm_ri_counter0_reg_tx_count_qxu_0_3_.INIT = 8'h4E; + LUT3_L plm_fsm_ri_counter0_reg_tx_count_qxu_0_3_ ( + .I0(plm_fsm_ri_counter0_un1_enable_1_0_a2_0_a2_0_a4_0), + .I1(plm_fsm_ri_counter0_reg_tx_count17_0_a2_0_a2_0_a4), + .I2(plm_fsm_ri_counter0_reg_tx_count[3]), + .LO(plm_fsm_ri_counter0_reg_tx_count_qxu[3]) + ); + defparam plm_fsm_ri_counter0_reg_tx_count_qxu_0_4_.INIT = 4'h7; + LUT2_L plm_fsm_ri_counter0_reg_tx_count_qxu_0_4_ ( + .I0(plm_fsm_ri_counter0_un1_enable_1_0_a2_0_a2_0_a4_0), + .I1(plm_fsm_ri_counter0_reg_tx_count[4]), + .LO(plm_fsm_ri_counter0_reg_tx_count_qxu[4]) + ); + defparam plm_fsm_ri_counter0_reg_tx_count_qxu_0_5_.INIT = 4'h7; + LUT2_L plm_fsm_ri_counter0_reg_tx_count_qxu_0_5_ ( + .I0(plm_fsm_ri_counter0_un1_enable_1_0_a2_0_a2_0_a4_0), + .I1(plm_fsm_ri_counter0_reg_tx_count[5]), + .LO(plm_fsm_ri_counter0_reg_tx_count_qxu[5]) + ); + defparam plm_fsm_ri_counter0_reg_tx_count_qxu_0_6_.INIT = 4'h7; + LUT2_L plm_fsm_ri_counter0_reg_tx_count_qxu_0_6_ ( + .I0(plm_fsm_ri_counter0_un1_enable_1_0_a2_0_a2_0_a4_0), + .I1(plm_fsm_ri_counter0_reg_tx_count[6]), + .LO(plm_fsm_ri_counter0_reg_tx_count_qxu[6]) + ); + defparam plm_fsm_ri_counter0_reg_tx_count_qxu_0_7_.INIT = 4'h7; + LUT2_L plm_fsm_ri_counter0_reg_tx_count_qxu_0_7_ ( + .I0(plm_fsm_ri_counter0_un1_enable_1_0_a2_0_a2_0_a4_0), + .I1(plm_fsm_ri_counter0_reg_tx_count[7]), + .LO(plm_fsm_ri_counter0_reg_tx_count_qxu[7]) + ); + VCC plm_fsm_ri_counter1_VCC ( + .P(plm_fsm_ri_counter1_VCC_1038) + ); + MUXCY_L plm_fsm_ri_counter1_reg_tx_count_cry_0_ ( + .CI(plm_fsm_ri_counter1_un1_enable_1_i_1039), + .DI(plm_fsm_ri_counter1_VCC_1038), + .LO(plm_fsm_ri_counter1_reg_tx_count_cry[0]), + .S(plm_fsm_ri_counter1_reg_tx_count_qxu[0]) + ); + XORCY plm_fsm_ri_counter1_reg_tx_count_s_0_ ( + .CI(plm_fsm_ri_counter1_un1_enable_1_i_1039), + .LI(plm_fsm_ri_counter1_reg_tx_count_qxu[0]), + .O(plm_fsm_ri_counter1_reg_tx_count_s[0]) + ); + MUXCY_L plm_fsm_ri_counter1_reg_tx_count_cry_1_ ( + .CI(plm_fsm_ri_counter1_reg_tx_count_cry[0]), + .DI(plm_fsm_ri_counter1_VCC_1038), + .LO(plm_fsm_ri_counter1_reg_tx_count_cry[1]), + .S(plm_fsm_ri_counter1_reg_tx_count_qxu[1]) + ); + XORCY plm_fsm_ri_counter1_reg_tx_count_s_1_ ( + .CI(plm_fsm_ri_counter1_reg_tx_count_cry[0]), + .LI(plm_fsm_ri_counter1_reg_tx_count_qxu[1]), + .O(plm_fsm_ri_counter1_reg_tx_count_s[1]) + ); + MUXCY_L plm_fsm_ri_counter1_reg_tx_count_cry_2_ ( + .CI(plm_fsm_ri_counter1_reg_tx_count_cry[1]), + .DI(plm_fsm_ri_counter1_VCC_1038), + .LO(plm_fsm_ri_counter1_reg_tx_count_cry[2]), + .S(plm_fsm_ri_counter1_reg_tx_count_qxu[2]) + ); + XORCY plm_fsm_ri_counter1_reg_tx_count_s_2_ ( + .CI(plm_fsm_ri_counter1_reg_tx_count_cry[1]), + .LI(plm_fsm_ri_counter1_reg_tx_count_qxu[2]), + .O(plm_fsm_ri_counter1_reg_tx_count_s[2]) + ); + MUXCY_L plm_fsm_ri_counter1_reg_tx_count_cry_3_ ( + .CI(plm_fsm_ri_counter1_reg_tx_count_cry[2]), + .DI(plm_fsm_ri_counter1_VCC_1038), + .LO(plm_fsm_ri_counter1_reg_tx_count_cry[3]), + .S(plm_fsm_ri_counter1_reg_tx_count_qxu[3]) + ); + XORCY plm_fsm_ri_counter1_reg_tx_count_s_3_ ( + .CI(plm_fsm_ri_counter1_reg_tx_count_cry[2]), + .LI(plm_fsm_ri_counter1_reg_tx_count_qxu[3]), + .O(plm_fsm_ri_counter1_reg_tx_count_s[3]) + ); + MUXCY_L plm_fsm_ri_counter1_reg_tx_count_cry_4_ ( + .CI(plm_fsm_ri_counter1_reg_tx_count_cry[3]), + .DI(plm_fsm_ri_counter1_VCC_1038), + .LO(plm_fsm_ri_counter1_reg_tx_count_cry[4]), + .S(plm_fsm_ri_counter1_reg_tx_count_qxu[4]) + ); + XORCY plm_fsm_ri_counter1_reg_tx_count_s_4_ ( + .CI(plm_fsm_ri_counter1_reg_tx_count_cry[3]), + .LI(plm_fsm_ri_counter1_reg_tx_count_qxu[4]), + .O(plm_fsm_ri_counter1_reg_tx_count_s[4]) + ); + MUXCY_L plm_fsm_ri_counter1_reg_tx_count_cry_5_ ( + .CI(plm_fsm_ri_counter1_reg_tx_count_cry[4]), + .DI(plm_fsm_ri_counter1_VCC_1038), + .LO(plm_fsm_ri_counter1_reg_tx_count_cry[5]), + .S(plm_fsm_ri_counter1_reg_tx_count_qxu[5]) + ); + XORCY plm_fsm_ri_counter1_reg_tx_count_s_5_ ( + .CI(plm_fsm_ri_counter1_reg_tx_count_cry[4]), + .LI(plm_fsm_ri_counter1_reg_tx_count_qxu[5]), + .O(plm_fsm_ri_counter1_reg_tx_count_s[5]) + ); + MUXCY_L plm_fsm_ri_counter1_reg_tx_count_cry_6_ ( + .CI(plm_fsm_ri_counter1_reg_tx_count_cry[5]), + .DI(plm_fsm_ri_counter1_VCC_1038), + .LO(plm_fsm_ri_counter1_reg_tx_count_cry[6]), + .S(plm_fsm_ri_counter1_reg_tx_count_qxu[6]) + ); + XORCY plm_fsm_ri_counter1_reg_tx_count_s_6_ ( + .CI(plm_fsm_ri_counter1_reg_tx_count_cry[5]), + .LI(plm_fsm_ri_counter1_reg_tx_count_qxu[6]), + .O(plm_fsm_ri_counter1_reg_tx_count_s[6]) + ); + XORCY plm_fsm_ri_counter1_reg_tx_count_s_7_ ( + .CI(plm_fsm_ri_counter1_reg_tx_count_cry[6]), + .LI(plm_fsm_ri_counter1_reg_tx_count_qxu[7]), + .O(plm_fsm_ri_counter1_reg_tx_count_s[7]) + ); + defparam plm_fsm_ri_counter1_loadable_rx_counter_N_9849_i.INIT = 4'h7; + LUT2 plm_fsm_ri_counter1_loadable_rx_counter_N_9849_i ( + .I0(plm_fsm_reg_state_16__357), + .I1(plm_fsm_ri_counter1_reg_rx_count[2]), + .O(plm_fsm_ri_counter1_N_9849_i) + ); + defparam plm_fsm_ri_counter1_loadable_rx_counter_N_38670_i.INIT = 4'hD; + LUT2 plm_fsm_ri_counter1_loadable_rx_counter_N_38670_i ( + .I0(plm_fsm_reg_state_16__357), + .I1(plm_fsm_ri_counter1_reg_rx_expired_1041), + .O(plm_fsm_ri_counter1_N_38670_i) + ); + defparam plm_fsm_ri_counter1_un1_enable_1_0_a2_0_a2_0_a4.INIT = 4'h4; + LUT2 plm_fsm_ri_counter1_un1_enable_1_0_a2_0_a2_0_a4 ( + .I0(plm_fsm_ri_counter1_reg_tx_expired_1043), + .I1(plm_fsm_un1_reg_tx_count17_1), + .O(plm_fsm_ri_counter1_un1_enable_1) + ); + defparam plm_fsm_ri_counter1_loadable_tx_counter_un1_reg_tx_count_0_a2_4.INIT = 16'h0001; + LUT4 plm_fsm_ri_counter1_loadable_tx_counter_un1_reg_tx_count_0_a2_4 ( + .I0(plm_fsm_ri_counter1_reg_tx_count[0]), + .I1(plm_fsm_ri_counter1_reg_tx_count[1]), + .I2(plm_fsm_ri_counter1_reg_tx_count[2]), + .I3(plm_fsm_ri_counter1_reg_tx_count[3]), + .O(plm_fsm_ri_counter1_un1_reg_tx_count_0_a2_4) + ); + defparam plm_fsm_ri_counter1_loadable_tx_counter_un1_reg_tx_count_0_a2_5.INIT = 16'h0001; + LUT4 plm_fsm_ri_counter1_loadable_tx_counter_un1_reg_tx_count_0_a2_5 ( + .I0(plm_fsm_ri_counter1_reg_tx_count[4]), + .I1(plm_fsm_ri_counter1_reg_tx_count[5]), + .I2(plm_fsm_ri_counter1_reg_tx_count[6]), + .I3(plm_fsm_ri_counter1_reg_tx_count[7]), + .O(plm_fsm_ri_counter1_un1_reg_tx_count_0_a2_5) + ); + defparam plm_fsm_ri_counter1_un1_enable_2_i.INIT = 8'h8F; + LUT3 plm_fsm_ri_counter1_un1_enable_2_i ( + .I0(plm_fsm_ri_counter1_un1_reg_tx_count_0_a2_4), + .I1(plm_fsm_ri_counter1_un1_reg_tx_count_0_a2_5), + .I2(plm_fsm_un1_reg_tx_count17_1), + .O(plm_fsm_ri_counter1_un1_enable_2_i_1042) + ); + defparam plm_fsm_ri_counter1_flagit_reg_expired_5_0_a2_0_a2_0_a4.INIT = 8'h80; + LUT3_L plm_fsm_ri_counter1_flagit_reg_expired_5_0_a2_0_a2_0_a4 ( + .I0(plm_fsm_reg_state_16__357), + .I1(plm_fsm_ri_counter1_reg_rx_expired_1041), + .I2(plm_fsm_ri_counter1_reg_tx_expired_1043), + .LO(plm_fsm_ri_counter1_reg_expired_5) + ); + defparam plm_fsm_ri_counter1_N_38665_i.INIT = 8'hFB; + LUT3 plm_fsm_ri_counter1_N_38665_i ( + .I0(plm_reg_sym_sent_0_), + .I1(plm_fsm_un1_reg_tx_count17_1), + .I2(plm_fsm_ri_counter1_reg_tx_expired_1043), + .O(plm_fsm_ri_counter1_N_38665_i_1040) + ); + defparam plm_fsm_ri_counter1_un1_enable_1_i.INIT = 4'hD; + LUT2 plm_fsm_ri_counter1_un1_enable_1_i ( + .I0(plm_fsm_un1_reg_tx_count17_1), + .I1(plm_fsm_ri_counter1_reg_tx_expired_1043), + .O(plm_fsm_ri_counter1_un1_enable_1_i_1039) + ); + FDCE plm_fsm_ri_counter1_reg_tx_count_7_ ( + .CE(plm_fsm_ri_counter1_N_38665_i_1040), + .C(mgt_clk), + .D(plm_fsm_ri_counter1_reg_tx_count_s[7]), + .Q(plm_fsm_ri_counter1_reg_tx_count[7]), + .CLR(plm_rst) + ); + FDCE plm_fsm_ri_counter1_reg_tx_count_6_ ( + .CE(plm_fsm_ri_counter1_N_38665_i_1040), + .C(mgt_clk), + .D(plm_fsm_ri_counter1_reg_tx_count_s[6]), + .Q(plm_fsm_ri_counter1_reg_tx_count[6]), + .CLR(plm_rst) + ); + FDCE plm_fsm_ri_counter1_reg_tx_count_5_ ( + .CE(plm_fsm_ri_counter1_N_38665_i_1040), + .C(mgt_clk), + .D(plm_fsm_ri_counter1_reg_tx_count_s[5]), + .Q(plm_fsm_ri_counter1_reg_tx_count[5]), + .CLR(plm_rst) + ); + FDCE plm_fsm_ri_counter1_reg_tx_count_4_ ( + .CE(plm_fsm_ri_counter1_N_38665_i_1040), + .C(mgt_clk), + .D(plm_fsm_ri_counter1_reg_tx_count_s[4]), + .Q(plm_fsm_ri_counter1_reg_tx_count[4]), + .CLR(plm_rst) + ); + FDPE plm_fsm_ri_counter1_reg_tx_count_3_ ( + .PRE(plm_rst), + .CE(plm_fsm_ri_counter1_N_38665_i_1040), + .C(mgt_clk), + .D(plm_fsm_ri_counter1_reg_tx_count_s[3]), + .Q(plm_fsm_ri_counter1_reg_tx_count[3]) + ); + FDCE plm_fsm_ri_counter1_reg_tx_count_2_ ( + .CE(plm_fsm_ri_counter1_N_38665_i_1040), + .C(mgt_clk), + .D(plm_fsm_ri_counter1_reg_tx_count_s[2]), + .Q(plm_fsm_ri_counter1_reg_tx_count[2]), + .CLR(plm_rst) + ); + FDCE plm_fsm_ri_counter1_reg_tx_count_1_ ( + .CE(plm_fsm_ri_counter1_N_38665_i_1040), + .C(mgt_clk), + .D(plm_fsm_ri_counter1_reg_tx_count_s[1]), + .Q(plm_fsm_ri_counter1_reg_tx_count[1]), + .CLR(plm_rst) + ); + FDCE plm_fsm_ri_counter1_reg_tx_count_0_ ( + .CE(plm_fsm_ri_counter1_N_38665_i_1040), + .C(mgt_clk), + .D(plm_fsm_ri_counter1_reg_tx_count_s[0]), + .Q(plm_fsm_ri_counter1_reg_tx_count[0]), + .CLR(plm_rst) + ); + FDC plm_fsm_ri_counter1_reg_expired ( + .C(mgt_clk), + .D(plm_fsm_ri_counter1_reg_expired_5), + .Q(plm_fsm_ri_cntrout1), + .CLR(plm_rst) + ); + FDPE plm_fsm_ri_counter1_reg_rx_count_2_ ( + .PRE(plm_rst), + .CE(plm_fsm_ri_counter1_N_38670_i), + .C(mgt_clk), + .D(plm_fsm_reg_state_i_16__901), + .Q(plm_fsm_ri_counter1_reg_rx_count[2]) + ); + FDCE plm_fsm_ri_counter1_reg_rx_expired ( + .CE(plm_fsm_ri_counter1_N_9849_i), + .C(mgt_clk), + .D(plm_fsm_reg_state_16__357), + .Q(plm_fsm_ri_counter1_reg_rx_expired_1041), + .CLR(plm_rst) + ); + FDCE plm_fsm_ri_counter1_reg_tx_expired ( + .CE(plm_fsm_ri_counter1_un1_enable_2_i_1042), + .C(mgt_clk), + .D(plm_fsm_un1_reg_tx_count17_1), + .Q(plm_fsm_ri_counter1_reg_tx_expired_1043), + .CLR(plm_rst) + ); + defparam plm_fsm_ri_counter1_reg_tx_count_qxu_0_0_.INIT = 4'h7; + LUT2_L plm_fsm_ri_counter1_reg_tx_count_qxu_0_0_ ( + .I0(plm_fsm_ri_counter1_reg_tx_count[0]), + .I1(plm_fsm_ri_counter1_un1_enable_1), + .LO(plm_fsm_ri_counter1_reg_tx_count_qxu[0]) + ); + defparam plm_fsm_ri_counter1_reg_tx_count_qxu_0_1_.INIT = 4'h7; + LUT2_L plm_fsm_ri_counter1_reg_tx_count_qxu_0_1_ ( + .I0(plm_fsm_ri_counter1_reg_tx_count[1]), + .I1(plm_fsm_ri_counter1_un1_enable_1), + .LO(plm_fsm_ri_counter1_reg_tx_count_qxu[1]) + ); + defparam plm_fsm_ri_counter1_reg_tx_count_qxu_0_2_.INIT = 4'h7; + LUT2_L plm_fsm_ri_counter1_reg_tx_count_qxu_0_2_ ( + .I0(plm_fsm_ri_counter1_reg_tx_count[2]), + .I1(plm_fsm_ri_counter1_un1_enable_1), + .LO(plm_fsm_ri_counter1_reg_tx_count_qxu[2]) + ); + defparam plm_fsm_ri_counter1_reg_tx_count_qxu_0_3_.INIT = 8'h74; + LUT3_L plm_fsm_ri_counter1_reg_tx_count_qxu_0_3_ ( + .I0(plm_fsm_ri_counter1_reg_tx_count[3]), + .I1(plm_fsm_ri_counter1_un1_enable_1), + .I2(plm_fsm_un1_reg_tx_count17_1), + .LO(plm_fsm_ri_counter1_reg_tx_count_qxu[3]) + ); + defparam plm_fsm_ri_counter1_reg_tx_count_qxu_0_4_.INIT = 4'h7; + LUT2_L plm_fsm_ri_counter1_reg_tx_count_qxu_0_4_ ( + .I0(plm_fsm_ri_counter1_reg_tx_count[4]), + .I1(plm_fsm_ri_counter1_un1_enable_1), + .LO(plm_fsm_ri_counter1_reg_tx_count_qxu[4]) + ); + defparam plm_fsm_ri_counter1_reg_tx_count_qxu_0_5_.INIT = 4'h7; + LUT2_L plm_fsm_ri_counter1_reg_tx_count_qxu_0_5_ ( + .I0(plm_fsm_ri_counter1_reg_tx_count[5]), + .I1(plm_fsm_ri_counter1_un1_enable_1), + .LO(plm_fsm_ri_counter1_reg_tx_count_qxu[5]) + ); + defparam plm_fsm_ri_counter1_reg_tx_count_qxu_0_6_.INIT = 4'h7; + LUT2_L plm_fsm_ri_counter1_reg_tx_count_qxu_0_6_ ( + .I0(plm_fsm_ri_counter1_reg_tx_count[6]), + .I1(plm_fsm_ri_counter1_un1_enable_1), + .LO(plm_fsm_ri_counter1_reg_tx_count_qxu[6]) + ); + defparam plm_fsm_ri_counter1_reg_tx_count_qxu_0_7_.INIT = 4'h7; + LUT2_L plm_fsm_ri_counter1_reg_tx_count_qxu_0_7_ ( + .I0(plm_fsm_ri_counter1_reg_tx_count[7]), + .I1(plm_fsm_ri_counter1_un1_enable_1), + .LO(plm_fsm_ri_counter1_reg_tx_count_qxu[7]) + ); + VCC plm_fsm_ri_counter2_VCC ( + .P(plm_fsm_ri_counter2_VCC_1044) + ); + MUXCY_L plm_fsm_ri_counter2_reg_tx_count_cry_0_ ( + .CI(plm_fsm_ri_counter2_un1_enable_1_i_1045), + .DI(plm_fsm_ri_counter2_VCC_1044), + .LO(plm_fsm_ri_counter2_reg_tx_count_cry[0]), + .S(plm_fsm_ri_counter2_reg_tx_count_qxu[0]) + ); + XORCY plm_fsm_ri_counter2_reg_tx_count_s_0_ ( + .CI(plm_fsm_ri_counter2_un1_enable_1_i_1045), + .LI(plm_fsm_ri_counter2_reg_tx_count_qxu[0]), + .O(plm_fsm_ri_counter2_reg_tx_count_s[0]) + ); + MUXCY_L plm_fsm_ri_counter2_reg_tx_count_cry_1_ ( + .CI(plm_fsm_ri_counter2_reg_tx_count_cry[0]), + .DI(plm_fsm_ri_counter2_VCC_1044), + .LO(plm_fsm_ri_counter2_reg_tx_count_cry[1]), + .S(plm_fsm_ri_counter2_reg_tx_count_qxu[1]) + ); + XORCY plm_fsm_ri_counter2_reg_tx_count_s_1_ ( + .CI(plm_fsm_ri_counter2_reg_tx_count_cry[0]), + .LI(plm_fsm_ri_counter2_reg_tx_count_qxu[1]), + .O(plm_fsm_ri_counter2_reg_tx_count_s[1]) + ); + MUXCY_L plm_fsm_ri_counter2_reg_tx_count_cry_2_ ( + .CI(plm_fsm_ri_counter2_reg_tx_count_cry[1]), + .DI(plm_fsm_ri_counter2_VCC_1044), + .LO(plm_fsm_ri_counter2_reg_tx_count_cry[2]), + .S(plm_fsm_ri_counter2_reg_tx_count_qxu[2]) + ); + XORCY plm_fsm_ri_counter2_reg_tx_count_s_2_ ( + .CI(plm_fsm_ri_counter2_reg_tx_count_cry[1]), + .LI(plm_fsm_ri_counter2_reg_tx_count_qxu[2]), + .O(plm_fsm_ri_counter2_reg_tx_count_s[2]) + ); + MUXCY_L plm_fsm_ri_counter2_reg_tx_count_cry_3_ ( + .CI(plm_fsm_ri_counter2_reg_tx_count_cry[2]), + .DI(plm_fsm_ri_counter2_VCC_1044), + .LO(plm_fsm_ri_counter2_reg_tx_count_cry[3]), + .S(plm_fsm_ri_counter2_reg_tx_count_qxu[3]) + ); + XORCY plm_fsm_ri_counter2_reg_tx_count_s_3_ ( + .CI(plm_fsm_ri_counter2_reg_tx_count_cry[2]), + .LI(plm_fsm_ri_counter2_reg_tx_count_qxu[3]), + .O(plm_fsm_ri_counter2_reg_tx_count_s[3]) + ); + MUXCY_L plm_fsm_ri_counter2_reg_tx_count_cry_4_ ( + .CI(plm_fsm_ri_counter2_reg_tx_count_cry[3]), + .DI(plm_fsm_ri_counter2_VCC_1044), + .LO(plm_fsm_ri_counter2_reg_tx_count_cry[4]), + .S(plm_fsm_ri_counter2_reg_tx_count_qxu[4]) + ); + XORCY plm_fsm_ri_counter2_reg_tx_count_s_4_ ( + .CI(plm_fsm_ri_counter2_reg_tx_count_cry[3]), + .LI(plm_fsm_ri_counter2_reg_tx_count_qxu[4]), + .O(plm_fsm_ri_counter2_reg_tx_count_s[4]) + ); + MUXCY_L plm_fsm_ri_counter2_reg_tx_count_cry_5_ ( + .CI(plm_fsm_ri_counter2_reg_tx_count_cry[4]), + .DI(plm_fsm_ri_counter2_VCC_1044), + .LO(plm_fsm_ri_counter2_reg_tx_count_cry[5]), + .S(plm_fsm_ri_counter2_reg_tx_count_qxu[5]) + ); + XORCY plm_fsm_ri_counter2_reg_tx_count_s_5_ ( + .CI(plm_fsm_ri_counter2_reg_tx_count_cry[4]), + .LI(plm_fsm_ri_counter2_reg_tx_count_qxu[5]), + .O(plm_fsm_ri_counter2_reg_tx_count_s[5]) + ); + MUXCY_L plm_fsm_ri_counter2_reg_tx_count_cry_6_ ( + .CI(plm_fsm_ri_counter2_reg_tx_count_cry[5]), + .DI(plm_fsm_ri_counter2_VCC_1044), + .LO(plm_fsm_ri_counter2_reg_tx_count_cry[6]), + .S(plm_fsm_ri_counter2_reg_tx_count_qxu[6]) + ); + XORCY plm_fsm_ri_counter2_reg_tx_count_s_6_ ( + .CI(plm_fsm_ri_counter2_reg_tx_count_cry[5]), + .LI(plm_fsm_ri_counter2_reg_tx_count_qxu[6]), + .O(plm_fsm_ri_counter2_reg_tx_count_s[6]) + ); + XORCY plm_fsm_ri_counter2_reg_tx_count_s_7_ ( + .CI(plm_fsm_ri_counter2_reg_tx_count_cry[6]), + .LI(plm_fsm_ri_counter2_reg_tx_count_qxu[7]), + .O(plm_fsm_ri_counter2_reg_tx_count_s[7]) + ); + defparam plm_fsm_ri_counter2_loadable_rx_counter_N_9847_i.INIT = 4'h7; + LUT2 plm_fsm_ri_counter2_loadable_rx_counter_N_9847_i ( + .I0(plm_fsm_reg_state_16__357), + .I1(plm_fsm_ri_counter2_reg_rx_count[2]), + .O(plm_fsm_ri_counter2_N_9847_i) + ); + defparam plm_fsm_ri_counter2_loadable_rx_counter_N_38669_i.INIT = 4'hD; + LUT2 plm_fsm_ri_counter2_loadable_rx_counter_N_38669_i ( + .I0(plm_fsm_reg_state_16__357), + .I1(plm_fsm_ri_counter2_reg_rx_expired_1047), + .O(plm_fsm_ri_counter2_N_38669_i) + ); + defparam plm_fsm_ri_counter2_un1_enable_1_0_a2_0_a2_0_a4.INIT = 4'h4; + LUT2 plm_fsm_ri_counter2_un1_enable_1_0_a2_0_a2_0_a4 ( + .I0(plm_fsm_ri_counter2_reg_tx_expired_1049), + .I1(plm_fsm_un1_reg_tx_count17_1), + .O(plm_fsm_ri_counter2_un1_enable_1) + ); + defparam plm_fsm_ri_counter2_loadable_tx_counter_un1_reg_tx_count_4.INIT = 16'h0001; + LUT4 plm_fsm_ri_counter2_loadable_tx_counter_un1_reg_tx_count_4 ( + .I0(plm_fsm_ri_counter2_reg_tx_count[0]), + .I1(plm_fsm_ri_counter2_reg_tx_count[1]), + .I2(plm_fsm_ri_counter2_reg_tx_count[2]), + .I3(plm_fsm_ri_counter2_reg_tx_count[3]), + .O(plm_fsm_ri_counter2_un1_reg_tx_count_4) + ); + defparam plm_fsm_ri_counter2_loadable_tx_counter_un1_reg_tx_count_5.INIT = 16'h0001; + LUT4 plm_fsm_ri_counter2_loadable_tx_counter_un1_reg_tx_count_5 ( + .I0(plm_fsm_ri_counter2_reg_tx_count[4]), + .I1(plm_fsm_ri_counter2_reg_tx_count[5]), + .I2(plm_fsm_ri_counter2_reg_tx_count[6]), + .I3(plm_fsm_ri_counter2_reg_tx_count[7]), + .O(plm_fsm_ri_counter2_un1_reg_tx_count_5) + ); + defparam plm_fsm_ri_counter2_un1_enable_2_i.INIT = 8'h8F; + LUT3 plm_fsm_ri_counter2_un1_enable_2_i ( + .I0(plm_fsm_ri_counter2_un1_reg_tx_count_4), + .I1(plm_fsm_ri_counter2_un1_reg_tx_count_5), + .I2(plm_fsm_un1_reg_tx_count17_1), + .O(plm_fsm_ri_counter2_un1_enable_2_i_1048) + ); + defparam plm_fsm_ri_counter2_flagit_reg_expired_5_0_a2_0_a2_0_a4.INIT = 8'h80; + LUT3_L plm_fsm_ri_counter2_flagit_reg_expired_5_0_a2_0_a2_0_a4 ( + .I0(plm_fsm_reg_state_16__357), + .I1(plm_fsm_ri_counter2_reg_rx_expired_1047), + .I2(plm_fsm_ri_counter2_reg_tx_expired_1049), + .LO(plm_fsm_ri_counter2_reg_expired_5) + ); + defparam plm_fsm_ri_counter2_N_38666_i.INIT = 8'hFB; + LUT3 plm_fsm_ri_counter2_N_38666_i ( + .I0(plm_reg_sym_sent_0_), + .I1(plm_fsm_un1_reg_tx_count17_1), + .I2(plm_fsm_ri_counter2_reg_tx_expired_1049), + .O(plm_fsm_ri_counter2_N_38666_i_1046) + ); + defparam plm_fsm_ri_counter2_un1_enable_1_i.INIT = 4'hD; + LUT2 plm_fsm_ri_counter2_un1_enable_1_i ( + .I0(plm_fsm_un1_reg_tx_count17_1), + .I1(plm_fsm_ri_counter2_reg_tx_expired_1049), + .O(plm_fsm_ri_counter2_un1_enable_1_i_1045) + ); + FDCE plm_fsm_ri_counter2_reg_tx_count_7_ ( + .CE(plm_fsm_ri_counter2_N_38666_i_1046), + .C(mgt_clk), + .D(plm_fsm_ri_counter2_reg_tx_count_s[7]), + .Q(plm_fsm_ri_counter2_reg_tx_count[7]), + .CLR(plm_rst) + ); + FDCE plm_fsm_ri_counter2_reg_tx_count_6_ ( + .CE(plm_fsm_ri_counter2_N_38666_i_1046), + .C(mgt_clk), + .D(plm_fsm_ri_counter2_reg_tx_count_s[6]), + .Q(plm_fsm_ri_counter2_reg_tx_count[6]), + .CLR(plm_rst) + ); + FDCE plm_fsm_ri_counter2_reg_tx_count_5_ ( + .CE(plm_fsm_ri_counter2_N_38666_i_1046), + .C(mgt_clk), + .D(plm_fsm_ri_counter2_reg_tx_count_s[5]), + .Q(plm_fsm_ri_counter2_reg_tx_count[5]), + .CLR(plm_rst) + ); + FDCE plm_fsm_ri_counter2_reg_tx_count_4_ ( + .CE(plm_fsm_ri_counter2_N_38666_i_1046), + .C(mgt_clk), + .D(plm_fsm_ri_counter2_reg_tx_count_s[4]), + .Q(plm_fsm_ri_counter2_reg_tx_count[4]), + .CLR(plm_rst) + ); + FDPE plm_fsm_ri_counter2_reg_tx_count_3_ ( + .PRE(plm_rst), + .CE(plm_fsm_ri_counter2_N_38666_i_1046), + .C(mgt_clk), + .D(plm_fsm_ri_counter2_reg_tx_count_s[3]), + .Q(plm_fsm_ri_counter2_reg_tx_count[3]) + ); + FDCE plm_fsm_ri_counter2_reg_tx_count_2_ ( + .CE(plm_fsm_ri_counter2_N_38666_i_1046), + .C(mgt_clk), + .D(plm_fsm_ri_counter2_reg_tx_count_s[2]), + .Q(plm_fsm_ri_counter2_reg_tx_count[2]), + .CLR(plm_rst) + ); + FDCE plm_fsm_ri_counter2_reg_tx_count_1_ ( + .CE(plm_fsm_ri_counter2_N_38666_i_1046), + .C(mgt_clk), + .D(plm_fsm_ri_counter2_reg_tx_count_s[1]), + .Q(plm_fsm_ri_counter2_reg_tx_count[1]), + .CLR(plm_rst) + ); + FDCE plm_fsm_ri_counter2_reg_tx_count_0_ ( + .CE(plm_fsm_ri_counter2_N_38666_i_1046), + .C(mgt_clk), + .D(plm_fsm_ri_counter2_reg_tx_count_s[0]), + .Q(plm_fsm_ri_counter2_reg_tx_count[0]), + .CLR(plm_rst) + ); + FDC plm_fsm_ri_counter2_reg_expired ( + .C(mgt_clk), + .D(plm_fsm_ri_counter2_reg_expired_5), + .Q(plm_fsm_ri_cntrout2), + .CLR(plm_rst) + ); + FDPE plm_fsm_ri_counter2_reg_rx_count_2_ ( + .PRE(plm_rst), + .CE(plm_fsm_ri_counter2_N_38669_i), + .C(mgt_clk), + .D(plm_fsm_reg_state_i_16__901), + .Q(plm_fsm_ri_counter2_reg_rx_count[2]) + ); + FDCE plm_fsm_ri_counter2_reg_rx_expired ( + .CE(plm_fsm_ri_counter2_N_9847_i), + .C(mgt_clk), + .D(plm_fsm_reg_state_16__357), + .Q(plm_fsm_ri_counter2_reg_rx_expired_1047), + .CLR(plm_rst) + ); + FDCE plm_fsm_ri_counter2_reg_tx_expired ( + .CE(plm_fsm_ri_counter2_un1_enable_2_i_1048), + .C(mgt_clk), + .D(plm_fsm_un1_reg_tx_count17_1), + .Q(plm_fsm_ri_counter2_reg_tx_expired_1049), + .CLR(plm_rst) + ); + defparam plm_fsm_ri_counter2_reg_tx_count_qxu_0_0_.INIT = 4'h7; + LUT2_L plm_fsm_ri_counter2_reg_tx_count_qxu_0_0_ ( + .I0(plm_fsm_ri_counter2_reg_tx_count[0]), + .I1(plm_fsm_ri_counter2_un1_enable_1), + .LO(plm_fsm_ri_counter2_reg_tx_count_qxu[0]) + ); + defparam plm_fsm_ri_counter2_reg_tx_count_qxu_0_1_.INIT = 4'h7; + LUT2_L plm_fsm_ri_counter2_reg_tx_count_qxu_0_1_ ( + .I0(plm_fsm_ri_counter2_reg_tx_count[1]), + .I1(plm_fsm_ri_counter2_un1_enable_1), + .LO(plm_fsm_ri_counter2_reg_tx_count_qxu[1]) + ); + defparam plm_fsm_ri_counter2_reg_tx_count_qxu_0_2_.INIT = 4'h7; + LUT2_L plm_fsm_ri_counter2_reg_tx_count_qxu_0_2_ ( + .I0(plm_fsm_ri_counter2_reg_tx_count[2]), + .I1(plm_fsm_ri_counter2_un1_enable_1), + .LO(plm_fsm_ri_counter2_reg_tx_count_qxu[2]) + ); + defparam plm_fsm_ri_counter2_reg_tx_count_qxu_0_3_.INIT = 8'h74; + LUT3_L plm_fsm_ri_counter2_reg_tx_count_qxu_0_3_ ( + .I0(plm_fsm_ri_counter2_reg_tx_count[3]), + .I1(plm_fsm_ri_counter2_un1_enable_1), + .I2(plm_fsm_un1_reg_tx_count17_1), + .LO(plm_fsm_ri_counter2_reg_tx_count_qxu[3]) + ); + defparam plm_fsm_ri_counter2_reg_tx_count_qxu_0_4_.INIT = 4'h7; + LUT2_L plm_fsm_ri_counter2_reg_tx_count_qxu_0_4_ ( + .I0(plm_fsm_ri_counter2_reg_tx_count[4]), + .I1(plm_fsm_ri_counter2_un1_enable_1), + .LO(plm_fsm_ri_counter2_reg_tx_count_qxu[4]) + ); + defparam plm_fsm_ri_counter2_reg_tx_count_qxu_0_5_.INIT = 4'h7; + LUT2_L plm_fsm_ri_counter2_reg_tx_count_qxu_0_5_ ( + .I0(plm_fsm_ri_counter2_reg_tx_count[5]), + .I1(plm_fsm_ri_counter2_un1_enable_1), + .LO(plm_fsm_ri_counter2_reg_tx_count_qxu[5]) + ); + defparam plm_fsm_ri_counter2_reg_tx_count_qxu_0_6_.INIT = 4'h7; + LUT2_L plm_fsm_ri_counter2_reg_tx_count_qxu_0_6_ ( + .I0(plm_fsm_ri_counter2_reg_tx_count[6]), + .I1(plm_fsm_ri_counter2_un1_enable_1), + .LO(plm_fsm_ri_counter2_reg_tx_count_qxu[6]) + ); + defparam plm_fsm_ri_counter2_reg_tx_count_qxu_0_7_.INIT = 4'h7; + LUT2_L plm_fsm_ri_counter2_reg_tx_count_qxu_0_7_ ( + .I0(plm_fsm_ri_counter2_reg_tx_count[7]), + .I1(plm_fsm_ri_counter2_un1_enable_1), + .LO(plm_fsm_ri_counter2_reg_tx_count_qxu[7]) + ); + VCC plm_fsm_ri_counter3_VCC ( + .P(plm_fsm_ri_counter3_VCC_1050) + ); + MUXCY_L plm_fsm_ri_counter3_reg_tx_count_cry_0_ ( + .CI(plm_fsm_ri_counter3_un1_enable_1_i_1051), + .DI(plm_fsm_ri_counter3_VCC_1050), + .LO(plm_fsm_ri_counter3_reg_tx_count_cry[0]), + .S(plm_fsm_ri_counter3_reg_tx_count_qxu[0]) + ); + XORCY plm_fsm_ri_counter3_reg_tx_count_s_0_ ( + .CI(plm_fsm_ri_counter3_un1_enable_1_i_1051), + .LI(plm_fsm_ri_counter3_reg_tx_count_qxu[0]), + .O(plm_fsm_ri_counter3_reg_tx_count_s[0]) + ); + MUXCY_L plm_fsm_ri_counter3_reg_tx_count_cry_1_ ( + .CI(plm_fsm_ri_counter3_reg_tx_count_cry[0]), + .DI(plm_fsm_ri_counter3_VCC_1050), + .LO(plm_fsm_ri_counter3_reg_tx_count_cry[1]), + .S(plm_fsm_ri_counter3_reg_tx_count_qxu[1]) + ); + XORCY plm_fsm_ri_counter3_reg_tx_count_s_1_ ( + .CI(plm_fsm_ri_counter3_reg_tx_count_cry[0]), + .LI(plm_fsm_ri_counter3_reg_tx_count_qxu[1]), + .O(plm_fsm_ri_counter3_reg_tx_count_s[1]) + ); + MUXCY_L plm_fsm_ri_counter3_reg_tx_count_cry_2_ ( + .CI(plm_fsm_ri_counter3_reg_tx_count_cry[1]), + .DI(plm_fsm_ri_counter3_VCC_1050), + .LO(plm_fsm_ri_counter3_reg_tx_count_cry[2]), + .S(plm_fsm_ri_counter3_reg_tx_count_qxu[2]) + ); + XORCY plm_fsm_ri_counter3_reg_tx_count_s_2_ ( + .CI(plm_fsm_ri_counter3_reg_tx_count_cry[1]), + .LI(plm_fsm_ri_counter3_reg_tx_count_qxu[2]), + .O(plm_fsm_ri_counter3_reg_tx_count_s[2]) + ); + MUXCY_L plm_fsm_ri_counter3_reg_tx_count_cry_3_ ( + .CI(plm_fsm_ri_counter3_reg_tx_count_cry[2]), + .DI(plm_fsm_ri_counter3_VCC_1050), + .LO(plm_fsm_ri_counter3_reg_tx_count_cry[3]), + .S(plm_fsm_ri_counter3_reg_tx_count_qxu[3]) + ); + XORCY plm_fsm_ri_counter3_reg_tx_count_s_3_ ( + .CI(plm_fsm_ri_counter3_reg_tx_count_cry[2]), + .LI(plm_fsm_ri_counter3_reg_tx_count_qxu[3]), + .O(plm_fsm_ri_counter3_reg_tx_count_s[3]) + ); + MUXCY_L plm_fsm_ri_counter3_reg_tx_count_cry_4_ ( + .CI(plm_fsm_ri_counter3_reg_tx_count_cry[3]), + .DI(plm_fsm_ri_counter3_VCC_1050), + .LO(plm_fsm_ri_counter3_reg_tx_count_cry[4]), + .S(plm_fsm_ri_counter3_reg_tx_count_qxu[4]) + ); + XORCY plm_fsm_ri_counter3_reg_tx_count_s_4_ ( + .CI(plm_fsm_ri_counter3_reg_tx_count_cry[3]), + .LI(plm_fsm_ri_counter3_reg_tx_count_qxu[4]), + .O(plm_fsm_ri_counter3_reg_tx_count_s[4]) + ); + MUXCY_L plm_fsm_ri_counter3_reg_tx_count_cry_5_ ( + .CI(plm_fsm_ri_counter3_reg_tx_count_cry[4]), + .DI(plm_fsm_ri_counter3_VCC_1050), + .LO(plm_fsm_ri_counter3_reg_tx_count_cry[5]), + .S(plm_fsm_ri_counter3_reg_tx_count_qxu[5]) + ); + XORCY plm_fsm_ri_counter3_reg_tx_count_s_5_ ( + .CI(plm_fsm_ri_counter3_reg_tx_count_cry[4]), + .LI(plm_fsm_ri_counter3_reg_tx_count_qxu[5]), + .O(plm_fsm_ri_counter3_reg_tx_count_s[5]) + ); + MUXCY_L plm_fsm_ri_counter3_reg_tx_count_cry_6_ ( + .CI(plm_fsm_ri_counter3_reg_tx_count_cry[5]), + .DI(plm_fsm_ri_counter3_VCC_1050), + .LO(plm_fsm_ri_counter3_reg_tx_count_cry[6]), + .S(plm_fsm_ri_counter3_reg_tx_count_qxu[6]) + ); + XORCY plm_fsm_ri_counter3_reg_tx_count_s_6_ ( + .CI(plm_fsm_ri_counter3_reg_tx_count_cry[5]), + .LI(plm_fsm_ri_counter3_reg_tx_count_qxu[6]), + .O(plm_fsm_ri_counter3_reg_tx_count_s[6]) + ); + XORCY plm_fsm_ri_counter3_reg_tx_count_s_7_ ( + .CI(plm_fsm_ri_counter3_reg_tx_count_cry[6]), + .LI(plm_fsm_ri_counter3_reg_tx_count_qxu[7]), + .O(plm_fsm_ri_counter3_reg_tx_count_s[7]) + ); + defparam plm_fsm_ri_counter3_loadable_tx_counter_reg_tx_count17_0_a2_0_a3_0_a3.INIT = 4'h8; + LUT2 plm_fsm_ri_counter3_loadable_tx_counter_reg_tx_count17_0_a2_0_a3_0_a3 ( + .I0(plm_fsm_reg_state_16__357), + .I1(plm_fsm_ri_counter3_reg_oneshot_1053), + .O(plm_fsm_un1_reg_tx_count17_1) + ); + defparam plm_fsm_ri_counter3_loadable_rx_counter_N_38693_i.INIT = 4'h7; + LUT2 plm_fsm_ri_counter3_loadable_rx_counter_N_38693_i ( + .I0(plm_fsm_reg_state_16__357), + .I1(plm_fsm_ri_counter3_reg_rx_count[2]), + .O(plm_fsm_ri_counter3_N_38693_i) + ); + defparam plm_fsm_ri_counter3_loadable_rx_counter_N_38668_i.INIT = 4'hD; + LUT2 plm_fsm_ri_counter3_loadable_rx_counter_N_38668_i ( + .I0(plm_fsm_reg_state_16__357), + .I1(plm_fsm_ri_counter3_reg_rx_expired_1054), + .O(plm_fsm_ri_counter3_N_38668_i) + ); + defparam plm_fsm_ri_counter3_un1_enable_1_0_a2_0_a2_0_a4.INIT = 4'h4; + LUT2 plm_fsm_ri_counter3_un1_enable_1_0_a2_0_a2_0_a4 ( + .I0(plm_fsm_ri_counter3_reg_tx_expired_1056), + .I1(plm_fsm_un1_reg_tx_count17_1), + .O(plm_fsm_ri_counter3_un1_enable_1) + ); + defparam plm_fsm_ri_counter3_loadable_tx_counter_un1_reg_tx_count_0_a2_0_a4_4.INIT = 16'h0001; + LUT4 plm_fsm_ri_counter3_loadable_tx_counter_un1_reg_tx_count_0_a2_0_a4_4 ( + .I0(plm_fsm_ri_counter3_reg_tx_count[0]), + .I1(plm_fsm_ri_counter3_reg_tx_count[1]), + .I2(plm_fsm_ri_counter3_reg_tx_count[2]), + .I3(plm_fsm_ri_counter3_reg_tx_count[3]), + .O(plm_fsm_ri_counter3_un1_reg_tx_count_0_a2_0_a4_4) + ); + defparam plm_fsm_ri_counter3_loadable_tx_counter_un1_reg_tx_count_0_a2_0_a4_5.INIT = 16'h0001; + LUT4 plm_fsm_ri_counter3_loadable_tx_counter_un1_reg_tx_count_0_a2_0_a4_5 ( + .I0(plm_fsm_ri_counter3_reg_tx_count[4]), + .I1(plm_fsm_ri_counter3_reg_tx_count[5]), + .I2(plm_fsm_ri_counter3_reg_tx_count[6]), + .I3(plm_fsm_ri_counter3_reg_tx_count[7]), + .O(plm_fsm_ri_counter3_un1_reg_tx_count_0_a2_0_a4_5) + ); + defparam plm_fsm_ri_counter3_un1_enable_2_i.INIT = 8'h8F; + LUT3 plm_fsm_ri_counter3_un1_enable_2_i ( + .I0(plm_fsm_ri_counter3_un1_reg_tx_count_0_a2_0_a4_4), + .I1(plm_fsm_ri_counter3_un1_reg_tx_count_0_a2_0_a4_5), + .I2(plm_fsm_un1_reg_tx_count17_1), + .O(plm_fsm_ri_counter3_un1_enable_2_i_1055) + ); + defparam plm_fsm_ri_counter3_flagit_reg_expired_5_0_a2_0_a2_0_a4.INIT = 8'h80; + LUT3_L plm_fsm_ri_counter3_flagit_reg_expired_5_0_a2_0_a2_0_a4 ( + .I0(plm_fsm_reg_state_16__357), + .I1(plm_fsm_ri_counter3_reg_rx_expired_1054), + .I2(plm_fsm_ri_counter3_reg_tx_expired_1056), + .LO(plm_fsm_ri_counter3_reg_expired_5) + ); + defparam plm_fsm_ri_counter3_N_38667_i.INIT = 8'hFB; + LUT3 plm_fsm_ri_counter3_N_38667_i ( + .I0(plm_reg_sym_sent_0_), + .I1(plm_fsm_un1_reg_tx_count17_1), + .I2(plm_fsm_ri_counter3_reg_tx_expired_1056), + .O(plm_fsm_ri_counter3_N_38667_i_1052) + ); + defparam plm_fsm_ri_counter3_un1_enable_1_i.INIT = 4'hD; + LUT2 plm_fsm_ri_counter3_un1_enable_1_i ( + .I0(plm_fsm_un1_reg_tx_count17_1), + .I1(plm_fsm_ri_counter3_reg_tx_expired_1056), + .O(plm_fsm_ri_counter3_un1_enable_1_i_1051) + ); + FDCE plm_fsm_ri_counter3_reg_tx_count_7_ ( + .CE(plm_fsm_ri_counter3_N_38667_i_1052), + .C(mgt_clk), + .D(plm_fsm_ri_counter3_reg_tx_count_s[7]), + .Q(plm_fsm_ri_counter3_reg_tx_count[7]), + .CLR(plm_rst) + ); + FDCE plm_fsm_ri_counter3_reg_tx_count_6_ ( + .CE(plm_fsm_ri_counter3_N_38667_i_1052), + .C(mgt_clk), + .D(plm_fsm_ri_counter3_reg_tx_count_s[6]), + .Q(plm_fsm_ri_counter3_reg_tx_count[6]), + .CLR(plm_rst) + ); + FDCE plm_fsm_ri_counter3_reg_tx_count_5_ ( + .CE(plm_fsm_ri_counter3_N_38667_i_1052), + .C(mgt_clk), + .D(plm_fsm_ri_counter3_reg_tx_count_s[5]), + .Q(plm_fsm_ri_counter3_reg_tx_count[5]), + .CLR(plm_rst) + ); + FDCE plm_fsm_ri_counter3_reg_tx_count_4_ ( + .CE(plm_fsm_ri_counter3_N_38667_i_1052), + .C(mgt_clk), + .D(plm_fsm_ri_counter3_reg_tx_count_s[4]), + .Q(plm_fsm_ri_counter3_reg_tx_count[4]), + .CLR(plm_rst) + ); + FDPE plm_fsm_ri_counter3_reg_tx_count_3_ ( + .PRE(plm_rst), + .CE(plm_fsm_ri_counter3_N_38667_i_1052), + .C(mgt_clk), + .D(plm_fsm_ri_counter3_reg_tx_count_s[3]), + .Q(plm_fsm_ri_counter3_reg_tx_count[3]) + ); + FDCE plm_fsm_ri_counter3_reg_tx_count_2_ ( + .CE(plm_fsm_ri_counter3_N_38667_i_1052), + .C(mgt_clk), + .D(plm_fsm_ri_counter3_reg_tx_count_s[2]), + .Q(plm_fsm_ri_counter3_reg_tx_count[2]), + .CLR(plm_rst) + ); + FDCE plm_fsm_ri_counter3_reg_tx_count_1_ ( + .CE(plm_fsm_ri_counter3_N_38667_i_1052), + .C(mgt_clk), + .D(plm_fsm_ri_counter3_reg_tx_count_s[1]), + .Q(plm_fsm_ri_counter3_reg_tx_count[1]), + .CLR(plm_rst) + ); + FDCE plm_fsm_ri_counter3_reg_tx_count_0_ ( + .CE(plm_fsm_ri_counter3_N_38667_i_1052), + .C(mgt_clk), + .D(plm_fsm_ri_counter3_reg_tx_count_s[0]), + .Q(plm_fsm_ri_counter3_reg_tx_count[0]), + .CLR(plm_rst) + ); + FDC plm_fsm_ri_counter3_reg_expired ( + .C(mgt_clk), + .D(plm_fsm_ri_counter3_reg_expired_5), + .Q(plm_fsm_ri_cntrout3), + .CLR(plm_rst) + ); + FDPE plm_fsm_ri_counter3_reg_rx_count_2_ ( + .PRE(plm_rst), + .CE(plm_fsm_ri_counter3_N_38668_i), + .C(mgt_clk), + .D(plm_fsm_reg_state_i_16__901), + .Q(plm_fsm_ri_counter3_reg_rx_count[2]) + ); + FDCE plm_fsm_ri_counter3_reg_oneshot ( + .CE(plm_fsm_reg_state_i_16__901), + .C(mgt_clk), + .D(plm_fsm_reg_state_16__357), + .Q(plm_fsm_ri_counter3_reg_oneshot_1053), + .CLR(plm_rst) + ); + FDCE plm_fsm_ri_counter3_reg_rx_expired ( + .CE(plm_fsm_ri_counter3_N_38693_i), + .C(mgt_clk), + .D(plm_fsm_reg_state_16__357), + .Q(plm_fsm_ri_counter3_reg_rx_expired_1054), + .CLR(plm_rst) + ); + FDCE plm_fsm_ri_counter3_reg_tx_expired ( + .CE(plm_fsm_ri_counter3_un1_enable_2_i_1055), + .C(mgt_clk), + .D(plm_fsm_un1_reg_tx_count17_1), + .Q(plm_fsm_ri_counter3_reg_tx_expired_1056), + .CLR(plm_rst) + ); + defparam plm_fsm_ri_counter3_reg_tx_count_qxu_0_0_.INIT = 4'h7; + LUT2_L plm_fsm_ri_counter3_reg_tx_count_qxu_0_0_ ( + .I0(plm_fsm_ri_counter3_reg_tx_count[0]), + .I1(plm_fsm_ri_counter3_un1_enable_1), + .LO(plm_fsm_ri_counter3_reg_tx_count_qxu[0]) + ); + defparam plm_fsm_ri_counter3_reg_tx_count_qxu_0_1_.INIT = 4'h7; + LUT2_L plm_fsm_ri_counter3_reg_tx_count_qxu_0_1_ ( + .I0(plm_fsm_ri_counter3_reg_tx_count[1]), + .I1(plm_fsm_ri_counter3_un1_enable_1), + .LO(plm_fsm_ri_counter3_reg_tx_count_qxu[1]) + ); + defparam plm_fsm_ri_counter3_reg_tx_count_qxu_0_2_.INIT = 4'h7; + LUT2_L plm_fsm_ri_counter3_reg_tx_count_qxu_0_2_ ( + .I0(plm_fsm_ri_counter3_reg_tx_count[2]), + .I1(plm_fsm_ri_counter3_un1_enable_1), + .LO(plm_fsm_ri_counter3_reg_tx_count_qxu[2]) + ); + defparam plm_fsm_ri_counter3_reg_tx_count_qxu_0_3_.INIT = 8'h74; + LUT3_L plm_fsm_ri_counter3_reg_tx_count_qxu_0_3_ ( + .I0(plm_fsm_ri_counter3_reg_tx_count[3]), + .I1(plm_fsm_ri_counter3_un1_enable_1), + .I2(plm_fsm_un1_reg_tx_count17_1), + .LO(plm_fsm_ri_counter3_reg_tx_count_qxu[3]) + ); + defparam plm_fsm_ri_counter3_reg_tx_count_qxu_0_4_.INIT = 4'h7; + LUT2_L plm_fsm_ri_counter3_reg_tx_count_qxu_0_4_ ( + .I0(plm_fsm_ri_counter3_reg_tx_count[4]), + .I1(plm_fsm_ri_counter3_un1_enable_1), + .LO(plm_fsm_ri_counter3_reg_tx_count_qxu[4]) + ); + defparam plm_fsm_ri_counter3_reg_tx_count_qxu_0_5_.INIT = 4'h7; + LUT2_L plm_fsm_ri_counter3_reg_tx_count_qxu_0_5_ ( + .I0(plm_fsm_ri_counter3_reg_tx_count[5]), + .I1(plm_fsm_ri_counter3_un1_enable_1), + .LO(plm_fsm_ri_counter3_reg_tx_count_qxu[5]) + ); + defparam plm_fsm_ri_counter3_reg_tx_count_qxu_0_6_.INIT = 4'h7; + LUT2_L plm_fsm_ri_counter3_reg_tx_count_qxu_0_6_ ( + .I0(plm_fsm_ri_counter3_reg_tx_count[6]), + .I1(plm_fsm_ri_counter3_un1_enable_1), + .LO(plm_fsm_ri_counter3_reg_tx_count_qxu[6]) + ); + defparam plm_fsm_ri_counter3_reg_tx_count_qxu_0_7_.INIT = 4'h7; + LUT2_L plm_fsm_ri_counter3_reg_tx_count_qxu_0_7_ ( + .I0(plm_fsm_ri_counter3_reg_tx_count[7]), + .I1(plm_fsm_ri_counter3_un1_enable_1), + .LO(plm_fsm_ri_counter3_reg_tx_count_qxu[7]) + ); + GND plm_fsm_hr_timer_GND ( + .G(plm_fsm_hr_timer_GND_1057) + ); + MUXCY_L plm_fsm_hr_timer_reg_count_cry_0_ ( + .CI(plm_fsm_N_18398_i), + .DI(plm_fsm_hr_timer_GND_1057), + .LO(plm_fsm_hr_timer_reg_count_cry[0]), + .S(plm_fsm_hr_timer_reg_count_qxu[0]) + ); + XORCY plm_fsm_hr_timer_reg_count_s_0_ ( + .CI(plm_fsm_N_18398_i), + .LI(plm_fsm_hr_timer_reg_count_qxu[0]), + .O(plm_fsm_hr_timer_reg_count_s[0]) + ); + MUXCY_L plm_fsm_hr_timer_reg_count_cry_1_ ( + .CI(plm_fsm_hr_timer_reg_count_cry[0]), + .DI(plm_fsm_hr_timer_GND_1057), + .LO(plm_fsm_hr_timer_reg_count_cry[1]), + .S(plm_fsm_hr_timer_reg_count_qxu[1]) + ); + XORCY plm_fsm_hr_timer_reg_count_s_1_ ( + .CI(plm_fsm_hr_timer_reg_count_cry[0]), + .LI(plm_fsm_hr_timer_reg_count_qxu[1]), + .O(plm_fsm_hr_timer_reg_count_s[1]) + ); + MUXCY_L plm_fsm_hr_timer_reg_count_cry_2_ ( + .CI(plm_fsm_hr_timer_reg_count_cry[1]), + .DI(plm_fsm_hr_timer_GND_1057), + .LO(plm_fsm_hr_timer_reg_count_cry[2]), + .S(plm_fsm_hr_timer_reg_count_qxu[2]) + ); + XORCY plm_fsm_hr_timer_reg_count_s_2_ ( + .CI(plm_fsm_hr_timer_reg_count_cry[1]), + .LI(plm_fsm_hr_timer_reg_count_qxu[2]), + .O(plm_fsm_hr_timer_reg_count_s[2]) + ); + MUXCY_L plm_fsm_hr_timer_reg_count_cry_3_ ( + .CI(plm_fsm_hr_timer_reg_count_cry[2]), + .DI(plm_fsm_hr_timer_GND_1057), + .LO(plm_fsm_hr_timer_reg_count_cry[3]), + .S(plm_fsm_hr_timer_reg_count_qxu[3]) + ); + XORCY plm_fsm_hr_timer_reg_count_s_3_ ( + .CI(plm_fsm_hr_timer_reg_count_cry[2]), + .LI(plm_fsm_hr_timer_reg_count_qxu[3]), + .O(plm_fsm_hr_timer_reg_count_s[3]) + ); + MUXCY_L plm_fsm_hr_timer_reg_count_cry_4_ ( + .CI(plm_fsm_hr_timer_reg_count_cry[3]), + .DI(plm_fsm_hr_timer_GND_1057), + .LO(plm_fsm_hr_timer_reg_count_cry[4]), + .S(plm_fsm_hr_timer_reg_count_qxu[4]) + ); + XORCY plm_fsm_hr_timer_reg_count_s_4_ ( + .CI(plm_fsm_hr_timer_reg_count_cry[3]), + .LI(plm_fsm_hr_timer_reg_count_qxu[4]), + .O(plm_fsm_hr_timer_reg_count_s[4]) + ); + MUXCY_L plm_fsm_hr_timer_reg_count_cry_5_ ( + .CI(plm_fsm_hr_timer_reg_count_cry[4]), + .DI(plm_fsm_hr_timer_GND_1057), + .LO(plm_fsm_hr_timer_reg_count_cry[5]), + .S(plm_fsm_hr_timer_reg_count_qxu[5]) + ); + XORCY plm_fsm_hr_timer_reg_count_s_5_ ( + .CI(plm_fsm_hr_timer_reg_count_cry[4]), + .LI(plm_fsm_hr_timer_reg_count_qxu[5]), + .O(plm_fsm_hr_timer_reg_count_s[5]) + ); + MUXCY_L plm_fsm_hr_timer_reg_count_cry_6_ ( + .CI(plm_fsm_hr_timer_reg_count_cry[5]), + .DI(plm_fsm_hr_timer_GND_1057), + .LO(plm_fsm_hr_timer_reg_count_cry[6]), + .S(plm_fsm_hr_timer_reg_count_qxu[6]) + ); + XORCY plm_fsm_hr_timer_reg_count_s_6_ ( + .CI(plm_fsm_hr_timer_reg_count_cry[5]), + .LI(plm_fsm_hr_timer_reg_count_qxu[6]), + .O(plm_fsm_hr_timer_reg_count_s[6]) + ); + MUXCY_L plm_fsm_hr_timer_reg_count_cry_7_ ( + .CI(plm_fsm_hr_timer_reg_count_cry[6]), + .DI(plm_fsm_hr_timer_GND_1057), + .LO(plm_fsm_hr_timer_reg_count_cry[7]), + .S(plm_fsm_hr_timer_reg_count_qxu[7]) + ); + XORCY plm_fsm_hr_timer_reg_count_s_7_ ( + .CI(plm_fsm_hr_timer_reg_count_cry[6]), + .LI(plm_fsm_hr_timer_reg_count_qxu[7]), + .O(plm_fsm_hr_timer_reg_count_s[7]) + ); + MUXCY_L plm_fsm_hr_timer_reg_count_cry_8_ ( + .CI(plm_fsm_hr_timer_reg_count_cry[7]), + .DI(plm_fsm_hr_timer_GND_1057), + .LO(plm_fsm_hr_timer_reg_count_cry[8]), + .S(plm_fsm_hr_timer_reg_count_qxu[8]) + ); + XORCY plm_fsm_hr_timer_reg_count_s_8_ ( + .CI(plm_fsm_hr_timer_reg_count_cry[7]), + .LI(plm_fsm_hr_timer_reg_count_qxu[8]), + .O(plm_fsm_hr_timer_reg_count_s[8]) + ); + MUXCY_L plm_fsm_hr_timer_reg_count_cry_9_ ( + .CI(plm_fsm_hr_timer_reg_count_cry[8]), + .DI(plm_fsm_hr_timer_GND_1057), + .LO(plm_fsm_hr_timer_reg_count_cry[9]), + .S(plm_fsm_hr_timer_reg_count_qxu[9]) + ); + XORCY plm_fsm_hr_timer_reg_count_s_9_ ( + .CI(plm_fsm_hr_timer_reg_count_cry[8]), + .LI(plm_fsm_hr_timer_reg_count_qxu[9]), + .O(plm_fsm_hr_timer_reg_count_s[9]) + ); + MUXCY_L plm_fsm_hr_timer_reg_count_cry_10_ ( + .CI(plm_fsm_hr_timer_reg_count_cry[9]), + .DI(plm_fsm_hr_timer_GND_1057), + .LO(plm_fsm_hr_timer_reg_count_cry[10]), + .S(plm_fsm_hr_timer_reg_count_qxu[10]) + ); + XORCY plm_fsm_hr_timer_reg_count_s_10_ ( + .CI(plm_fsm_hr_timer_reg_count_cry[9]), + .LI(plm_fsm_hr_timer_reg_count_qxu[10]), + .O(plm_fsm_hr_timer_reg_count_s[10]) + ); + MUXCY_L plm_fsm_hr_timer_reg_count_cry_11_ ( + .CI(plm_fsm_hr_timer_reg_count_cry[10]), + .DI(plm_fsm_hr_timer_GND_1057), + .LO(plm_fsm_hr_timer_reg_count_cry[11]), + .S(plm_fsm_hr_timer_reg_count_qxu[11]) + ); + XORCY plm_fsm_hr_timer_reg_count_s_11_ ( + .CI(plm_fsm_hr_timer_reg_count_cry[10]), + .LI(plm_fsm_hr_timer_reg_count_qxu[11]), + .O(plm_fsm_hr_timer_reg_count_s[11]) + ); + MUXCY_L plm_fsm_hr_timer_reg_count_cry_12_ ( + .CI(plm_fsm_hr_timer_reg_count_cry[11]), + .DI(plm_fsm_hr_timer_GND_1057), + .LO(plm_fsm_hr_timer_reg_count_cry[12]), + .S(plm_fsm_hr_timer_reg_count_qxu[12]) + ); + XORCY plm_fsm_hr_timer_reg_count_s_12_ ( + .CI(plm_fsm_hr_timer_reg_count_cry[11]), + .LI(plm_fsm_hr_timer_reg_count_qxu[12]), + .O(plm_fsm_hr_timer_reg_count_s[12]) + ); + MUXCY_L plm_fsm_hr_timer_reg_count_cry_13_ ( + .CI(plm_fsm_hr_timer_reg_count_cry[12]), + .DI(plm_fsm_hr_timer_GND_1057), + .LO(plm_fsm_hr_timer_reg_count_cry[13]), + .S(plm_fsm_hr_timer_reg_count_qxu[13]) + ); + XORCY plm_fsm_hr_timer_reg_count_s_13_ ( + .CI(plm_fsm_hr_timer_reg_count_cry[12]), + .LI(plm_fsm_hr_timer_reg_count_qxu[13]), + .O(plm_fsm_hr_timer_reg_count_s[13]) + ); + MUXCY_L plm_fsm_hr_timer_reg_count_cry_14_ ( + .CI(plm_fsm_hr_timer_reg_count_cry[13]), + .DI(plm_fsm_hr_timer_GND_1057), + .LO(plm_fsm_hr_timer_reg_count_cry[14]), + .S(plm_fsm_hr_timer_reg_count_qxu[14]) + ); + XORCY plm_fsm_hr_timer_reg_count_s_14_ ( + .CI(plm_fsm_hr_timer_reg_count_cry[13]), + .LI(plm_fsm_hr_timer_reg_count_qxu[14]), + .O(plm_fsm_hr_timer_reg_count_s[14]) + ); + MUXCY_L plm_fsm_hr_timer_reg_count_cry_15_ ( + .CI(plm_fsm_hr_timer_reg_count_cry[14]), + .DI(plm_fsm_hr_timer_GND_1057), + .LO(plm_fsm_hr_timer_reg_count_cry[15]), + .S(plm_fsm_hr_timer_reg_count_qxu[15]) + ); + XORCY plm_fsm_hr_timer_reg_count_s_15_ ( + .CI(plm_fsm_hr_timer_reg_count_cry[14]), + .LI(plm_fsm_hr_timer_reg_count_qxu[15]), + .O(plm_fsm_hr_timer_reg_count_s[15]) + ); + MUXCY_L plm_fsm_hr_timer_reg_count_cry_16_ ( + .CI(plm_fsm_hr_timer_reg_count_cry[15]), + .DI(plm_fsm_hr_timer_GND_1057), + .LO(plm_fsm_hr_timer_reg_count_cry[16]), + .S(plm_fsm_hr_timer_reg_count_qxu[16]) + ); + XORCY plm_fsm_hr_timer_reg_count_s_16_ ( + .CI(plm_fsm_hr_timer_reg_count_cry[15]), + .LI(plm_fsm_hr_timer_reg_count_qxu[16]), + .O(plm_fsm_hr_timer_reg_count_s[16]) + ); + MUXCY_L plm_fsm_hr_timer_reg_count_cry_17_ ( + .CI(plm_fsm_hr_timer_reg_count_cry[16]), + .DI(plm_fsm_hr_timer_GND_1057), + .LO(plm_fsm_hr_timer_reg_count_cry[17]), + .S(plm_fsm_hr_timer_reg_count_qxu[17]) + ); + XORCY plm_fsm_hr_timer_reg_count_s_17_ ( + .CI(plm_fsm_hr_timer_reg_count_cry[16]), + .LI(plm_fsm_hr_timer_reg_count_qxu[17]), + .O(plm_fsm_hr_timer_reg_count_s[17]) + ); + MUXCY_L plm_fsm_hr_timer_reg_count_cry_18_ ( + .CI(plm_fsm_hr_timer_reg_count_cry[17]), + .DI(plm_fsm_hr_timer_GND_1057), + .LO(plm_fsm_hr_timer_reg_count_cry[18]), + .S(plm_fsm_hr_timer_reg_count_qxu[18]) + ); + XORCY plm_fsm_hr_timer_reg_count_s_18_ ( + .CI(plm_fsm_hr_timer_reg_count_cry[17]), + .LI(plm_fsm_hr_timer_reg_count_qxu[18]), + .O(plm_fsm_hr_timer_reg_count_s[18]) + ); + MUXCY_L plm_fsm_hr_timer_reg_count_cry_19_ ( + .CI(plm_fsm_hr_timer_reg_count_cry[18]), + .DI(plm_fsm_hr_timer_GND_1057), + .LO(plm_fsm_hr_timer_reg_count_cry[19]), + .S(plm_fsm_hr_timer_reg_count_qxu[19]) + ); + XORCY plm_fsm_hr_timer_reg_count_s_19_ ( + .CI(plm_fsm_hr_timer_reg_count_cry[18]), + .LI(plm_fsm_hr_timer_reg_count_qxu[19]), + .O(plm_fsm_hr_timer_reg_count_s[19]) + ); + MUXCY_L plm_fsm_hr_timer_reg_count_cry_20_ ( + .CI(plm_fsm_hr_timer_reg_count_cry[19]), + .DI(plm_fsm_hr_timer_GND_1057), + .LO(plm_fsm_hr_timer_reg_count_cry[20]), + .S(plm_fsm_hr_timer_reg_count_qxu[20]) + ); + XORCY plm_fsm_hr_timer_reg_count_s_20_ ( + .CI(plm_fsm_hr_timer_reg_count_cry[19]), + .LI(plm_fsm_hr_timer_reg_count_qxu[20]), + .O(plm_fsm_hr_timer_reg_count_s[20]) + ); + MUXCY_L plm_fsm_hr_timer_reg_count_cry_21_ ( + .CI(plm_fsm_hr_timer_reg_count_cry[20]), + .DI(plm_fsm_hr_timer_GND_1057), + .LO(plm_fsm_hr_timer_reg_count_cry[21]), + .S(plm_fsm_hr_timer_reg_count_qxu[21]) + ); + XORCY plm_fsm_hr_timer_reg_count_s_21_ ( + .CI(plm_fsm_hr_timer_reg_count_cry[20]), + .LI(plm_fsm_hr_timer_reg_count_qxu[21]), + .O(plm_fsm_hr_timer_reg_count_s[21]) + ); + XORCY plm_fsm_hr_timer_reg_count_s_22_ ( + .CI(plm_fsm_hr_timer_reg_count_cry[21]), + .LI(plm_fsm_hr_timer_reg_count_qxu[22]), + .O(plm_fsm_hr_timer_reg_count_s[22]) + ); + defparam plm_fsm_hr_timer_count_i_m3_i_m3_0_20_.INIT = 8'hD8; + LUT3_L plm_fsm_hr_timer_count_i_m3_i_m3_0_20_ ( + .I0(cfg_cfg_5072[507]), + .I1(plm_fsm_hr_timer_reg_count[12]), + .I2(plm_fsm_hr_timer_reg_count[20]), + .LO(plm_fsm_hr_timer_N_51420) + ); + defparam plm_fsm_hr_timer_count_i_m3_i_m3_0_19_.INIT = 8'hD8; + LUT3_L plm_fsm_hr_timer_count_i_m3_i_m3_0_19_ ( + .I0(cfg_cfg_5072[507]), + .I1(plm_fsm_hr_timer_reg_count[11]), + .I2(plm_fsm_hr_timer_reg_count[19]), + .LO(plm_fsm_hr_timer_N_51419) + ); + defparam plm_fsm_hr_timer_un1_expired_2ms_0_a2_0_a2_0_a4_0.INIT = 16'h0415; + LUT4 plm_fsm_hr_timer_un1_expired_2ms_0_a2_0_a2_0_a4_0 ( + .I0(plm_fsm_hr_timer_N_51419), + .I1(cfg_cfg_5072[507]), + .I2(plm_fsm_hr_timer_reg_count[14]), + .I3(plm_fsm_hr_timer_reg_count[22]), + .O(plm_fsm_hr_timer_un1_expired_2ms_0_a2_0_a2_0_a4_0_1060) + ); + defparam plm_fsm_hr_timer_un1_expired_2ms_0_a2_0_a2_0_a4_1.INIT = 16'h0415; + LUT4_L plm_fsm_hr_timer_un1_expired_2ms_0_a2_0_a2_0_a4_1 ( + .I0(plm_fsm_hr_timer_N_51420), + .I1(cfg_cfg_5072[507]), + .I2(plm_fsm_hr_timer_reg_count[13]), + .I3(plm_fsm_hr_timer_reg_count[21]), + .LO(plm_fsm_hr_timer_un1_expired_2ms_0_a2_0_a2_0_a4_1_1058) + ); + defparam plm_fsm_hr_timer_un1_expired_2ms_0_a2_0_a2_0_a4_2.INIT = 16'h2700; + LUT4_L plm_fsm_hr_timer_un1_expired_2ms_0_a2_0_a2_0_a4_2 ( + .I0(cfg_cfg_5072[507]), + .I1(plm_fsm_hr_timer_reg_count[10]), + .I2(plm_fsm_hr_timer_reg_count[18]), + .I3(plm_fsm_hr_timer_un1_expired_2ms_0_a2_0_a2_0_a4_1_1058), + .LO(plm_fsm_hr_timer_un1_expired_2ms_0_a2_0_a2_0_a4_2_1059) + ); + defparam plm_fsm_hr_timer_hr_timeout_i_0_0_0_o4.INIT = 16'h0777; + LUT4 plm_fsm_hr_timer_hr_timeout_i_0_0_0_o4 ( + .I0(plm_fsm_hr_timer_un1_expired_2ms_0_a2_0_a2_0_a4_0_1060), + .I1(plm_fsm_hr_timer_un1_expired_2ms_0_a2_0_a2_0_a4_2_1059), + .I2(plm_rx0_linkctrl_0_), + .I3(plm_rx0_ts1_c), + .O(plm_fsm_hr_timeout_i_0_0_0_o4) + ); + FDC plm_fsm_hr_timer_reg_count_22_ ( + .C(mgt_clk), + .D(plm_fsm_hr_timer_reg_count_s[22]), + .Q(plm_fsm_hr_timer_reg_count[22]), + .CLR(plm_rst) + ); + FDC plm_fsm_hr_timer_reg_count_21_ ( + .C(mgt_clk), + .D(plm_fsm_hr_timer_reg_count_s[21]), + .Q(plm_fsm_hr_timer_reg_count[21]), + .CLR(plm_rst) + ); + FDC plm_fsm_hr_timer_reg_count_20_ ( + .C(mgt_clk), + .D(plm_fsm_hr_timer_reg_count_s[20]), + .Q(plm_fsm_hr_timer_reg_count[20]), + .CLR(plm_rst) + ); + FDC plm_fsm_hr_timer_reg_count_19_ ( + .C(mgt_clk), + .D(plm_fsm_hr_timer_reg_count_s[19]), + .Q(plm_fsm_hr_timer_reg_count[19]), + .CLR(plm_rst) + ); + FDC plm_fsm_hr_timer_reg_count_18_ ( + .C(mgt_clk), + .D(plm_fsm_hr_timer_reg_count_s[18]), + .Q(plm_fsm_hr_timer_reg_count[18]), + .CLR(plm_rst) + ); + FDC plm_fsm_hr_timer_reg_count_17_ ( + .C(mgt_clk), + .D(plm_fsm_hr_timer_reg_count_s[17]), + .Q(plm_fsm_hr_timer_reg_count[17]), + .CLR(plm_rst) + ); + FDC plm_fsm_hr_timer_reg_count_16_ ( + .C(mgt_clk), + .D(plm_fsm_hr_timer_reg_count_s[16]), + .Q(plm_fsm_hr_timer_reg_count[16]), + .CLR(plm_rst) + ); + FDC plm_fsm_hr_timer_reg_count_15_ ( + .C(mgt_clk), + .D(plm_fsm_hr_timer_reg_count_s[15]), + .Q(plm_fsm_hr_timer_reg_count[15]), + .CLR(plm_rst) + ); + FDC plm_fsm_hr_timer_reg_count_14_ ( + .C(mgt_clk), + .D(plm_fsm_hr_timer_reg_count_s[14]), + .Q(plm_fsm_hr_timer_reg_count[14]), + .CLR(plm_rst) + ); + FDC plm_fsm_hr_timer_reg_count_13_ ( + .C(mgt_clk), + .D(plm_fsm_hr_timer_reg_count_s[13]), + .Q(plm_fsm_hr_timer_reg_count[13]), + .CLR(plm_rst) + ); + FDC plm_fsm_hr_timer_reg_count_12_ ( + .C(mgt_clk), + .D(plm_fsm_hr_timer_reg_count_s[12]), + .Q(plm_fsm_hr_timer_reg_count[12]), + .CLR(plm_rst) + ); + FDC plm_fsm_hr_timer_reg_count_11_ ( + .C(mgt_clk), + .D(plm_fsm_hr_timer_reg_count_s[11]), + .Q(plm_fsm_hr_timer_reg_count[11]), + .CLR(plm_rst) + ); + FDC plm_fsm_hr_timer_reg_count_10_ ( + .C(mgt_clk), + .D(plm_fsm_hr_timer_reg_count_s[10]), + .Q(plm_fsm_hr_timer_reg_count[10]), + .CLR(plm_rst) + ); + FDC plm_fsm_hr_timer_reg_count_9_ ( + .C(mgt_clk), + .D(plm_fsm_hr_timer_reg_count_s[9]), + .Q(plm_fsm_hr_timer_reg_count[9]), + .CLR(plm_rst) + ); + FDC plm_fsm_hr_timer_reg_count_8_ ( + .C(mgt_clk), + .D(plm_fsm_hr_timer_reg_count_s[8]), + .Q(plm_fsm_hr_timer_reg_count[8]), + .CLR(plm_rst) + ); + FDC plm_fsm_hr_timer_reg_count_7_ ( + .C(mgt_clk), + .D(plm_fsm_hr_timer_reg_count_s[7]), + .Q(plm_fsm_hr_timer_reg_count[7]), + .CLR(plm_rst) + ); + FDC plm_fsm_hr_timer_reg_count_6_ ( + .C(mgt_clk), + .D(plm_fsm_hr_timer_reg_count_s[6]), + .Q(plm_fsm_hr_timer_reg_count[6]), + .CLR(plm_rst) + ); + FDC plm_fsm_hr_timer_reg_count_5_ ( + .C(mgt_clk), + .D(plm_fsm_hr_timer_reg_count_s[5]), + .Q(plm_fsm_hr_timer_reg_count[5]), + .CLR(plm_rst) + ); + FDC plm_fsm_hr_timer_reg_count_4_ ( + .C(mgt_clk), + .D(plm_fsm_hr_timer_reg_count_s[4]), + .Q(plm_fsm_hr_timer_reg_count[4]), + .CLR(plm_rst) + ); + FDC plm_fsm_hr_timer_reg_count_3_ ( + .C(mgt_clk), + .D(plm_fsm_hr_timer_reg_count_s[3]), + .Q(plm_fsm_hr_timer_reg_count[3]), + .CLR(plm_rst) + ); + FDC plm_fsm_hr_timer_reg_count_2_ ( + .C(mgt_clk), + .D(plm_fsm_hr_timer_reg_count_s[2]), + .Q(plm_fsm_hr_timer_reg_count[2]), + .CLR(plm_rst) + ); + FDC plm_fsm_hr_timer_reg_count_1_ ( + .C(mgt_clk), + .D(plm_fsm_hr_timer_reg_count_s[1]), + .Q(plm_fsm_hr_timer_reg_count[1]), + .CLR(plm_rst) + ); + FDC plm_fsm_hr_timer_reg_count_0_ ( + .C(mgt_clk), + .D(plm_fsm_hr_timer_reg_count_s[0]), + .Q(plm_fsm_hr_timer_reg_count[0]), + .CLR(plm_rst) + ); + defparam plm_fsm_hr_timer_reg_count_qxu_0_0_.INIT = 4'h8; + LUT2_L plm_fsm_hr_timer_reg_count_qxu_0_0_ ( + .I0(plm_fsm_N_18398_i), + .I1(plm_fsm_hr_timer_reg_count[0]), + .LO(plm_fsm_hr_timer_reg_count_qxu[0]) + ); + defparam plm_fsm_hr_timer_reg_count_qxu_0_1_.INIT = 4'h8; + LUT2_L plm_fsm_hr_timer_reg_count_qxu_0_1_ ( + .I0(plm_fsm_N_18398_i), + .I1(plm_fsm_hr_timer_reg_count[1]), + .LO(plm_fsm_hr_timer_reg_count_qxu[1]) + ); + defparam plm_fsm_hr_timer_reg_count_qxu_0_2_.INIT = 4'h8; + LUT2_L plm_fsm_hr_timer_reg_count_qxu_0_2_ ( + .I0(plm_fsm_N_18398_i), + .I1(plm_fsm_hr_timer_reg_count[2]), + .LO(plm_fsm_hr_timer_reg_count_qxu[2]) + ); + defparam plm_fsm_hr_timer_reg_count_qxu_0_3_.INIT = 4'h8; + LUT2_L plm_fsm_hr_timer_reg_count_qxu_0_3_ ( + .I0(plm_fsm_N_18398_i), + .I1(plm_fsm_hr_timer_reg_count[3]), + .LO(plm_fsm_hr_timer_reg_count_qxu[3]) + ); + defparam plm_fsm_hr_timer_reg_count_qxu_0_4_.INIT = 4'h8; + LUT2_L plm_fsm_hr_timer_reg_count_qxu_0_4_ ( + .I0(plm_fsm_N_18398_i), + .I1(plm_fsm_hr_timer_reg_count[4]), + .LO(plm_fsm_hr_timer_reg_count_qxu[4]) + ); + defparam plm_fsm_hr_timer_reg_count_qxu_0_5_.INIT = 4'h8; + LUT2_L plm_fsm_hr_timer_reg_count_qxu_0_5_ ( + .I0(plm_fsm_N_18398_i), + .I1(plm_fsm_hr_timer_reg_count[5]), + .LO(plm_fsm_hr_timer_reg_count_qxu[5]) + ); + defparam plm_fsm_hr_timer_reg_count_qxu_0_6_.INIT = 4'h8; + LUT2_L plm_fsm_hr_timer_reg_count_qxu_0_6_ ( + .I0(plm_fsm_N_18398_i), + .I1(plm_fsm_hr_timer_reg_count[6]), + .LO(plm_fsm_hr_timer_reg_count_qxu[6]) + ); + defparam plm_fsm_hr_timer_reg_count_qxu_0_7_.INIT = 4'h8; + LUT2_L plm_fsm_hr_timer_reg_count_qxu_0_7_ ( + .I0(plm_fsm_N_18398_i), + .I1(plm_fsm_hr_timer_reg_count[7]), + .LO(plm_fsm_hr_timer_reg_count_qxu[7]) + ); + defparam plm_fsm_hr_timer_reg_count_qxu_0_8_.INIT = 4'h8; + LUT2_L plm_fsm_hr_timer_reg_count_qxu_0_8_ ( + .I0(plm_fsm_N_18398_i), + .I1(plm_fsm_hr_timer_reg_count[8]), + .LO(plm_fsm_hr_timer_reg_count_qxu[8]) + ); + defparam plm_fsm_hr_timer_reg_count_qxu_0_9_.INIT = 4'h8; + LUT2_L plm_fsm_hr_timer_reg_count_qxu_0_9_ ( + .I0(plm_fsm_N_18398_i), + .I1(plm_fsm_hr_timer_reg_count[9]), + .LO(plm_fsm_hr_timer_reg_count_qxu[9]) + ); + defparam plm_fsm_hr_timer_reg_count_qxu_0_10_.INIT = 4'h8; + LUT2_L plm_fsm_hr_timer_reg_count_qxu_0_10_ ( + .I0(plm_fsm_N_18398_i), + .I1(plm_fsm_hr_timer_reg_count[10]), + .LO(plm_fsm_hr_timer_reg_count_qxu[10]) + ); + defparam plm_fsm_hr_timer_reg_count_qxu_0_11_.INIT = 4'h8; + LUT2_L plm_fsm_hr_timer_reg_count_qxu_0_11_ ( + .I0(plm_fsm_N_18398_i), + .I1(plm_fsm_hr_timer_reg_count[11]), + .LO(plm_fsm_hr_timer_reg_count_qxu[11]) + ); + defparam plm_fsm_hr_timer_reg_count_qxu_0_12_.INIT = 4'h8; + LUT2_L plm_fsm_hr_timer_reg_count_qxu_0_12_ ( + .I0(plm_fsm_N_18398_i), + .I1(plm_fsm_hr_timer_reg_count[12]), + .LO(plm_fsm_hr_timer_reg_count_qxu[12]) + ); + defparam plm_fsm_hr_timer_reg_count_qxu_0_13_.INIT = 4'h8; + LUT2_L plm_fsm_hr_timer_reg_count_qxu_0_13_ ( + .I0(plm_fsm_N_18398_i), + .I1(plm_fsm_hr_timer_reg_count[13]), + .LO(plm_fsm_hr_timer_reg_count_qxu[13]) + ); + defparam plm_fsm_hr_timer_reg_count_qxu_0_14_.INIT = 4'h8; + LUT2_L plm_fsm_hr_timer_reg_count_qxu_0_14_ ( + .I0(plm_fsm_N_18398_i), + .I1(plm_fsm_hr_timer_reg_count[14]), + .LO(plm_fsm_hr_timer_reg_count_qxu[14]) + ); + defparam plm_fsm_hr_timer_reg_count_qxu_0_15_.INIT = 4'h8; + LUT2_L plm_fsm_hr_timer_reg_count_qxu_0_15_ ( + .I0(plm_fsm_N_18398_i), + .I1(plm_fsm_hr_timer_reg_count[15]), + .LO(plm_fsm_hr_timer_reg_count_qxu[15]) + ); + defparam plm_fsm_hr_timer_reg_count_qxu_0_16_.INIT = 4'h8; + LUT2_L plm_fsm_hr_timer_reg_count_qxu_0_16_ ( + .I0(plm_fsm_N_18398_i), + .I1(plm_fsm_hr_timer_reg_count[16]), + .LO(plm_fsm_hr_timer_reg_count_qxu[16]) + ); + defparam plm_fsm_hr_timer_reg_count_qxu_0_17_.INIT = 4'h8; + LUT2_L plm_fsm_hr_timer_reg_count_qxu_0_17_ ( + .I0(plm_fsm_N_18398_i), + .I1(plm_fsm_hr_timer_reg_count[17]), + .LO(plm_fsm_hr_timer_reg_count_qxu[17]) + ); + defparam plm_fsm_hr_timer_reg_count_qxu_0_18_.INIT = 4'h8; + LUT2_L plm_fsm_hr_timer_reg_count_qxu_0_18_ ( + .I0(plm_fsm_N_18398_i), + .I1(plm_fsm_hr_timer_reg_count[18]), + .LO(plm_fsm_hr_timer_reg_count_qxu[18]) + ); + defparam plm_fsm_hr_timer_reg_count_qxu_0_19_.INIT = 4'h8; + LUT2_L plm_fsm_hr_timer_reg_count_qxu_0_19_ ( + .I0(plm_fsm_N_18398_i), + .I1(plm_fsm_hr_timer_reg_count[19]), + .LO(plm_fsm_hr_timer_reg_count_qxu[19]) + ); + defparam plm_fsm_hr_timer_reg_count_qxu_0_20_.INIT = 4'h8; + LUT2_L plm_fsm_hr_timer_reg_count_qxu_0_20_ ( + .I0(plm_fsm_N_18398_i), + .I1(plm_fsm_hr_timer_reg_count[20]), + .LO(plm_fsm_hr_timer_reg_count_qxu[20]) + ); + defparam plm_fsm_hr_timer_reg_count_qxu_0_21_.INIT = 4'h8; + LUT2_L plm_fsm_hr_timer_reg_count_qxu_0_21_ ( + .I0(plm_fsm_N_18398_i), + .I1(plm_fsm_hr_timer_reg_count[21]), + .LO(plm_fsm_hr_timer_reg_count_qxu[21]) + ); + defparam plm_fsm_hr_timer_reg_count_qxu_0_22_.INIT = 4'h8; + LUT2_L plm_fsm_hr_timer_reg_count_qxu_0_22_ ( + .I0(plm_fsm_N_18398_i), + .I1(plm_fsm_hr_timer_reg_count[22]), + .LO(plm_fsm_hr_timer_reg_count_qxu[22]) + ); + GND plm_fsm_xl_cls_timer_GND ( + .G(plm_fsm_xl_cls_timer_GND_1061) + ); + MUXCY_L plm_fsm_xl_cls_timer_reg_count_cry_0_ ( + .CI(plm_fsm_un1_reg_state_4_i_i_844), + .DI(plm_fsm_xl_cls_timer_GND_1061), + .LO(plm_fsm_xl_cls_timer_reg_count_cry[0]), + .S(plm_fsm_xl_cls_timer_reg_count_qxu[0]) + ); + XORCY plm_fsm_xl_cls_timer_reg_count_s_0_ ( + .CI(plm_fsm_un1_reg_state_4_i_i_844), + .LI(plm_fsm_xl_cls_timer_reg_count_qxu[0]), + .O(plm_fsm_xl_cls_timer_reg_count_s[0]) + ); + MUXCY_L plm_fsm_xl_cls_timer_reg_count_cry_1_ ( + .CI(plm_fsm_xl_cls_timer_reg_count_cry[0]), + .DI(plm_fsm_xl_cls_timer_GND_1061), + .LO(plm_fsm_xl_cls_timer_reg_count_cry[1]), + .S(plm_fsm_xl_cls_timer_reg_count_qxu[1]) + ); + XORCY plm_fsm_xl_cls_timer_reg_count_s_1_ ( + .CI(plm_fsm_xl_cls_timer_reg_count_cry[0]), + .LI(plm_fsm_xl_cls_timer_reg_count_qxu[1]), + .O(plm_fsm_xl_cls_timer_reg_count_s[1]) + ); + MUXCY_L plm_fsm_xl_cls_timer_reg_count_cry_2_ ( + .CI(plm_fsm_xl_cls_timer_reg_count_cry[1]), + .DI(plm_fsm_xl_cls_timer_GND_1061), + .LO(plm_fsm_xl_cls_timer_reg_count_cry[2]), + .S(plm_fsm_xl_cls_timer_reg_count_qxu[2]) + ); + XORCY plm_fsm_xl_cls_timer_reg_count_s_2_ ( + .CI(plm_fsm_xl_cls_timer_reg_count_cry[1]), + .LI(plm_fsm_xl_cls_timer_reg_count_qxu[2]), + .O(plm_fsm_xl_cls_timer_reg_count_s[2]) + ); + MUXCY_L plm_fsm_xl_cls_timer_reg_count_cry_3_ ( + .CI(plm_fsm_xl_cls_timer_reg_count_cry[2]), + .DI(plm_fsm_xl_cls_timer_GND_1061), + .LO(plm_fsm_xl_cls_timer_reg_count_cry[3]), + .S(plm_fsm_xl_cls_timer_reg_count_qxu[3]) + ); + XORCY plm_fsm_xl_cls_timer_reg_count_s_3_ ( + .CI(plm_fsm_xl_cls_timer_reg_count_cry[2]), + .LI(plm_fsm_xl_cls_timer_reg_count_qxu[3]), + .O(plm_fsm_xl_cls_timer_reg_count_s[3]) + ); + MUXCY_L plm_fsm_xl_cls_timer_reg_count_cry_4_ ( + .CI(plm_fsm_xl_cls_timer_reg_count_cry[3]), + .DI(plm_fsm_xl_cls_timer_GND_1061), + .LO(plm_fsm_xl_cls_timer_reg_count_cry[4]), + .S(plm_fsm_xl_cls_timer_reg_count_qxu[4]) + ); + XORCY plm_fsm_xl_cls_timer_reg_count_s_4_ ( + .CI(plm_fsm_xl_cls_timer_reg_count_cry[3]), + .LI(plm_fsm_xl_cls_timer_reg_count_qxu[4]), + .O(plm_fsm_xl_cls_timer_reg_count_s[4]) + ); + MUXCY_L plm_fsm_xl_cls_timer_reg_count_cry_5_ ( + .CI(plm_fsm_xl_cls_timer_reg_count_cry[4]), + .DI(plm_fsm_xl_cls_timer_GND_1061), + .LO(plm_fsm_xl_cls_timer_reg_count_cry[5]), + .S(plm_fsm_xl_cls_timer_reg_count_qxu[5]) + ); + XORCY plm_fsm_xl_cls_timer_reg_count_s_5_ ( + .CI(plm_fsm_xl_cls_timer_reg_count_cry[4]), + .LI(plm_fsm_xl_cls_timer_reg_count_qxu[5]), + .O(plm_fsm_xl_cls_timer_reg_count_s[5]) + ); + MUXCY_L plm_fsm_xl_cls_timer_reg_count_cry_6_ ( + .CI(plm_fsm_xl_cls_timer_reg_count_cry[5]), + .DI(plm_fsm_xl_cls_timer_GND_1061), + .LO(plm_fsm_xl_cls_timer_reg_count_cry[6]), + .S(plm_fsm_xl_cls_timer_reg_count_qxu[6]) + ); + XORCY plm_fsm_xl_cls_timer_reg_count_s_6_ ( + .CI(plm_fsm_xl_cls_timer_reg_count_cry[5]), + .LI(plm_fsm_xl_cls_timer_reg_count_qxu[6]), + .O(plm_fsm_xl_cls_timer_reg_count_s[6]) + ); + MUXCY_L plm_fsm_xl_cls_timer_reg_count_cry_7_ ( + .CI(plm_fsm_xl_cls_timer_reg_count_cry[6]), + .DI(plm_fsm_xl_cls_timer_GND_1061), + .LO(plm_fsm_xl_cls_timer_reg_count_cry[7]), + .S(plm_fsm_xl_cls_timer_reg_count_qxu[7]) + ); + XORCY plm_fsm_xl_cls_timer_reg_count_s_7_ ( + .CI(plm_fsm_xl_cls_timer_reg_count_cry[6]), + .LI(plm_fsm_xl_cls_timer_reg_count_qxu[7]), + .O(plm_fsm_xl_cls_timer_reg_count_s[7]) + ); + MUXCY_L plm_fsm_xl_cls_timer_reg_count_cry_8_ ( + .CI(plm_fsm_xl_cls_timer_reg_count_cry[7]), + .DI(plm_fsm_xl_cls_timer_GND_1061), + .LO(plm_fsm_xl_cls_timer_reg_count_cry[8]), + .S(plm_fsm_xl_cls_timer_reg_count_qxu[8]) + ); + XORCY plm_fsm_xl_cls_timer_reg_count_s_8_ ( + .CI(plm_fsm_xl_cls_timer_reg_count_cry[7]), + .LI(plm_fsm_xl_cls_timer_reg_count_qxu[8]), + .O(plm_fsm_xl_cls_timer_reg_count_s[8]) + ); + MUXCY_L plm_fsm_xl_cls_timer_reg_count_cry_9_ ( + .CI(plm_fsm_xl_cls_timer_reg_count_cry[8]), + .DI(plm_fsm_xl_cls_timer_GND_1061), + .LO(plm_fsm_xl_cls_timer_reg_count_cry[9]), + .S(plm_fsm_xl_cls_timer_reg_count_qxu[9]) + ); + XORCY plm_fsm_xl_cls_timer_reg_count_s_9_ ( + .CI(plm_fsm_xl_cls_timer_reg_count_cry[8]), + .LI(plm_fsm_xl_cls_timer_reg_count_qxu[9]), + .O(plm_fsm_xl_cls_timer_reg_count_s[9]) + ); + MUXCY_L plm_fsm_xl_cls_timer_reg_count_cry_10_ ( + .CI(plm_fsm_xl_cls_timer_reg_count_cry[9]), + .DI(plm_fsm_xl_cls_timer_GND_1061), + .LO(plm_fsm_xl_cls_timer_reg_count_cry[10]), + .S(plm_fsm_xl_cls_timer_reg_count_qxu[10]) + ); + XORCY plm_fsm_xl_cls_timer_reg_count_s_10_ ( + .CI(plm_fsm_xl_cls_timer_reg_count_cry[9]), + .LI(plm_fsm_xl_cls_timer_reg_count_qxu[10]), + .O(plm_fsm_xl_cls_timer_reg_count_s[10]) + ); + MUXCY_L plm_fsm_xl_cls_timer_reg_count_cry_11_ ( + .CI(plm_fsm_xl_cls_timer_reg_count_cry[10]), + .DI(plm_fsm_xl_cls_timer_GND_1061), + .LO(plm_fsm_xl_cls_timer_reg_count_cry[11]), + .S(plm_fsm_xl_cls_timer_reg_count_qxu[11]) + ); + XORCY plm_fsm_xl_cls_timer_reg_count_s_11_ ( + .CI(plm_fsm_xl_cls_timer_reg_count_cry[10]), + .LI(plm_fsm_xl_cls_timer_reg_count_qxu[11]), + .O(plm_fsm_xl_cls_timer_reg_count_s[11]) + ); + MUXCY_L plm_fsm_xl_cls_timer_reg_count_cry_12_ ( + .CI(plm_fsm_xl_cls_timer_reg_count_cry[11]), + .DI(plm_fsm_xl_cls_timer_GND_1061), + .LO(plm_fsm_xl_cls_timer_reg_count_cry[12]), + .S(plm_fsm_xl_cls_timer_reg_count_qxu[12]) + ); + XORCY plm_fsm_xl_cls_timer_reg_count_s_12_ ( + .CI(plm_fsm_xl_cls_timer_reg_count_cry[11]), + .LI(plm_fsm_xl_cls_timer_reg_count_qxu[12]), + .O(plm_fsm_xl_cls_timer_reg_count_s[12]) + ); + MUXCY_L plm_fsm_xl_cls_timer_reg_count_cry_13_ ( + .CI(plm_fsm_xl_cls_timer_reg_count_cry[12]), + .DI(plm_fsm_xl_cls_timer_GND_1061), + .LO(plm_fsm_xl_cls_timer_reg_count_cry[13]), + .S(plm_fsm_xl_cls_timer_reg_count_qxu[13]) + ); + XORCY plm_fsm_xl_cls_timer_reg_count_s_13_ ( + .CI(plm_fsm_xl_cls_timer_reg_count_cry[12]), + .LI(plm_fsm_xl_cls_timer_reg_count_qxu[13]), + .O(plm_fsm_xl_cls_timer_reg_count_s[13]) + ); + MUXCY_L plm_fsm_xl_cls_timer_reg_count_cry_14_ ( + .CI(plm_fsm_xl_cls_timer_reg_count_cry[13]), + .DI(plm_fsm_xl_cls_timer_GND_1061), + .LO(plm_fsm_xl_cls_timer_reg_count_cry[14]), + .S(plm_fsm_xl_cls_timer_reg_count_qxu[14]) + ); + XORCY plm_fsm_xl_cls_timer_reg_count_s_14_ ( + .CI(plm_fsm_xl_cls_timer_reg_count_cry[13]), + .LI(plm_fsm_xl_cls_timer_reg_count_qxu[14]), + .O(plm_fsm_xl_cls_timer_reg_count_s[14]) + ); + MUXCY_L plm_fsm_xl_cls_timer_reg_count_cry_15_ ( + .CI(plm_fsm_xl_cls_timer_reg_count_cry[14]), + .DI(plm_fsm_xl_cls_timer_GND_1061), + .LO(plm_fsm_xl_cls_timer_reg_count_cry[15]), + .S(plm_fsm_xl_cls_timer_reg_count_qxu[15]) + ); + XORCY plm_fsm_xl_cls_timer_reg_count_s_15_ ( + .CI(plm_fsm_xl_cls_timer_reg_count_cry[14]), + .LI(plm_fsm_xl_cls_timer_reg_count_qxu[15]), + .O(plm_fsm_xl_cls_timer_reg_count_s[15]) + ); + MUXCY_L plm_fsm_xl_cls_timer_reg_count_cry_16_ ( + .CI(plm_fsm_xl_cls_timer_reg_count_cry[15]), + .DI(plm_fsm_xl_cls_timer_GND_1061), + .LO(plm_fsm_xl_cls_timer_reg_count_cry[16]), + .S(plm_fsm_xl_cls_timer_reg_count_qxu[16]) + ); + XORCY plm_fsm_xl_cls_timer_reg_count_s_16_ ( + .CI(plm_fsm_xl_cls_timer_reg_count_cry[15]), + .LI(plm_fsm_xl_cls_timer_reg_count_qxu[16]), + .O(plm_fsm_xl_cls_timer_reg_count_s[16]) + ); + MUXCY_L plm_fsm_xl_cls_timer_reg_count_cry_17_ ( + .CI(plm_fsm_xl_cls_timer_reg_count_cry[16]), + .DI(plm_fsm_xl_cls_timer_GND_1061), + .LO(plm_fsm_xl_cls_timer_reg_count_cry[17]), + .S(plm_fsm_xl_cls_timer_reg_count_qxu[17]) + ); + XORCY plm_fsm_xl_cls_timer_reg_count_s_17_ ( + .CI(plm_fsm_xl_cls_timer_reg_count_cry[16]), + .LI(plm_fsm_xl_cls_timer_reg_count_qxu[17]), + .O(plm_fsm_xl_cls_timer_reg_count_s[17]) + ); + MUXCY_L plm_fsm_xl_cls_timer_reg_count_cry_18_ ( + .CI(plm_fsm_xl_cls_timer_reg_count_cry[17]), + .DI(plm_fsm_xl_cls_timer_GND_1061), + .LO(plm_fsm_xl_cls_timer_reg_count_cry[18]), + .S(plm_fsm_xl_cls_timer_reg_count_qxu[18]) + ); + XORCY plm_fsm_xl_cls_timer_reg_count_s_18_ ( + .CI(plm_fsm_xl_cls_timer_reg_count_cry[17]), + .LI(plm_fsm_xl_cls_timer_reg_count_qxu[18]), + .O(plm_fsm_xl_cls_timer_reg_count_s[18]) + ); + MUXCY_L plm_fsm_xl_cls_timer_reg_count_cry_19_ ( + .CI(plm_fsm_xl_cls_timer_reg_count_cry[18]), + .DI(plm_fsm_xl_cls_timer_GND_1061), + .LO(plm_fsm_xl_cls_timer_reg_count_cry[19]), + .S(plm_fsm_xl_cls_timer_reg_count_qxu[19]) + ); + XORCY plm_fsm_xl_cls_timer_reg_count_s_19_ ( + .CI(plm_fsm_xl_cls_timer_reg_count_cry[18]), + .LI(plm_fsm_xl_cls_timer_reg_count_qxu[19]), + .O(plm_fsm_xl_cls_timer_reg_count_s[19]) + ); + MUXCY_L plm_fsm_xl_cls_timer_reg_count_cry_20_ ( + .CI(plm_fsm_xl_cls_timer_reg_count_cry[19]), + .DI(plm_fsm_xl_cls_timer_GND_1061), + .LO(plm_fsm_xl_cls_timer_reg_count_cry[20]), + .S(plm_fsm_xl_cls_timer_reg_count_qxu[20]) + ); + XORCY plm_fsm_xl_cls_timer_reg_count_s_20_ ( + .CI(plm_fsm_xl_cls_timer_reg_count_cry[19]), + .LI(plm_fsm_xl_cls_timer_reg_count_qxu[20]), + .O(plm_fsm_xl_cls_timer_reg_count_s[20]) + ); + MUXCY_L plm_fsm_xl_cls_timer_reg_count_cry_21_ ( + .CI(plm_fsm_xl_cls_timer_reg_count_cry[20]), + .DI(plm_fsm_xl_cls_timer_GND_1061), + .LO(plm_fsm_xl_cls_timer_reg_count_cry[21]), + .S(plm_fsm_xl_cls_timer_reg_count_qxu[21]) + ); + XORCY plm_fsm_xl_cls_timer_reg_count_s_21_ ( + .CI(plm_fsm_xl_cls_timer_reg_count_cry[20]), + .LI(plm_fsm_xl_cls_timer_reg_count_qxu[21]), + .O(plm_fsm_xl_cls_timer_reg_count_s[21]) + ); + XORCY plm_fsm_xl_cls_timer_reg_count_s_22_ ( + .CI(plm_fsm_xl_cls_timer_reg_count_cry[21]), + .LI(plm_fsm_xl_cls_timer_reg_count_qxu[22]), + .O(plm_fsm_xl_cls_timer_reg_count_s[22]) + ); + defparam plm_fsm_xl_cls_timer_count_i_m3_i_m3_0_20_.INIT = 8'hD8; + LUT3_L plm_fsm_xl_cls_timer_count_i_m3_i_m3_0_20_ ( + .I0(cfg_cfg_5072[507]), + .I1(plm_fsm_xl_cls_timer_reg_count[12]), + .I2(plm_fsm_xl_cls_timer_reg_count[20]), + .LO(plm_fsm_xl_cls_timer_N_51423) + ); + defparam plm_fsm_xl_cls_timer_un3_expired_24ms.INIT = 16'hA280; + LUT4_L plm_fsm_xl_cls_timer_un3_expired_24ms ( + .I0(plm_fsm_xl_cls_timer_N_51423), + .I1(cfg_cfg_5072[507]), + .I2(plm_fsm_xl_cls_timer_reg_count[13]), + .I3(plm_fsm_xl_cls_timer_reg_count[21]), + .LO(plm_fsm_xl_cls_timer_N_12156) + ); + defparam plm_fsm_xl_cls_timer_un1_expired_24ms.INIT = 16'h0415; + LUT4_L plm_fsm_xl_cls_timer_un1_expired_24ms ( + .I0(plm_fsm_xl_cls_timer_N_12156), + .I1(cfg_cfg_5072[507]), + .I2(plm_fsm_xl_cls_timer_reg_count[14]), + .I3(plm_fsm_xl_cls_timer_reg_count[22]), + .LO(plm_fsm_xl_cls_timer_N_12157) + ); + defparam plm_fsm_xl_cls_timer_expired.INIT = 16'h5554; + LUT4 plm_fsm_xl_cls_timer_expired ( + .I0(plm_fsm_xl_cls_timer_N_12157), + .I1(plm_fsm_reg_state_18__885), + .I2(plm_fsm_reg_state_19__884), + .I3(plm_fsm_reg_state_20__883), + .O(plm_fsm_xl_cls_timeout) + ); + FDC plm_fsm_xl_cls_timer_reg_count_22_ ( + .C(mgt_clk), + .D(plm_fsm_xl_cls_timer_reg_count_s[22]), + .Q(plm_fsm_xl_cls_timer_reg_count[22]), + .CLR(plm_rst) + ); + FDC plm_fsm_xl_cls_timer_reg_count_21_ ( + .C(mgt_clk), + .D(plm_fsm_xl_cls_timer_reg_count_s[21]), + .Q(plm_fsm_xl_cls_timer_reg_count[21]), + .CLR(plm_rst) + ); + FDC plm_fsm_xl_cls_timer_reg_count_20_ ( + .C(mgt_clk), + .D(plm_fsm_xl_cls_timer_reg_count_s[20]), + .Q(plm_fsm_xl_cls_timer_reg_count[20]), + .CLR(plm_rst) + ); + FDC plm_fsm_xl_cls_timer_reg_count_19_ ( + .C(mgt_clk), + .D(plm_fsm_xl_cls_timer_reg_count_s[19]), + .Q(plm_fsm_xl_cls_timer_reg_count[19]), + .CLR(plm_rst) + ); + FDC plm_fsm_xl_cls_timer_reg_count_18_ ( + .C(mgt_clk), + .D(plm_fsm_xl_cls_timer_reg_count_s[18]), + .Q(plm_fsm_xl_cls_timer_reg_count[18]), + .CLR(plm_rst) + ); + FDC plm_fsm_xl_cls_timer_reg_count_17_ ( + .C(mgt_clk), + .D(plm_fsm_xl_cls_timer_reg_count_s[17]), + .Q(plm_fsm_xl_cls_timer_reg_count[17]), + .CLR(plm_rst) + ); + FDC plm_fsm_xl_cls_timer_reg_count_16_ ( + .C(mgt_clk), + .D(plm_fsm_xl_cls_timer_reg_count_s[16]), + .Q(plm_fsm_xl_cls_timer_reg_count[16]), + .CLR(plm_rst) + ); + FDC plm_fsm_xl_cls_timer_reg_count_15_ ( + .C(mgt_clk), + .D(plm_fsm_xl_cls_timer_reg_count_s[15]), + .Q(plm_fsm_xl_cls_timer_reg_count[15]), + .CLR(plm_rst) + ); + FDC plm_fsm_xl_cls_timer_reg_count_14_ ( + .C(mgt_clk), + .D(plm_fsm_xl_cls_timer_reg_count_s[14]), + .Q(plm_fsm_xl_cls_timer_reg_count[14]), + .CLR(plm_rst) + ); + FDC plm_fsm_xl_cls_timer_reg_count_13_ ( + .C(mgt_clk), + .D(plm_fsm_xl_cls_timer_reg_count_s[13]), + .Q(plm_fsm_xl_cls_timer_reg_count[13]), + .CLR(plm_rst) + ); + FDC plm_fsm_xl_cls_timer_reg_count_12_ ( + .C(mgt_clk), + .D(plm_fsm_xl_cls_timer_reg_count_s[12]), + .Q(plm_fsm_xl_cls_timer_reg_count[12]), + .CLR(plm_rst) + ); + FDC plm_fsm_xl_cls_timer_reg_count_11_ ( + .C(mgt_clk), + .D(plm_fsm_xl_cls_timer_reg_count_s[11]), + .Q(plm_fsm_xl_cls_timer_reg_count[11]), + .CLR(plm_rst) + ); + FDC plm_fsm_xl_cls_timer_reg_count_10_ ( + .C(mgt_clk), + .D(plm_fsm_xl_cls_timer_reg_count_s[10]), + .Q(plm_fsm_xl_cls_timer_reg_count[10]), + .CLR(plm_rst) + ); + FDC plm_fsm_xl_cls_timer_reg_count_9_ ( + .C(mgt_clk), + .D(plm_fsm_xl_cls_timer_reg_count_s[9]), + .Q(plm_fsm_xl_cls_timer_reg_count[9]), + .CLR(plm_rst) + ); + FDC plm_fsm_xl_cls_timer_reg_count_8_ ( + .C(mgt_clk), + .D(plm_fsm_xl_cls_timer_reg_count_s[8]), + .Q(plm_fsm_xl_cls_timer_reg_count[8]), + .CLR(plm_rst) + ); + FDC plm_fsm_xl_cls_timer_reg_count_7_ ( + .C(mgt_clk), + .D(plm_fsm_xl_cls_timer_reg_count_s[7]), + .Q(plm_fsm_xl_cls_timer_reg_count[7]), + .CLR(plm_rst) + ); + FDC plm_fsm_xl_cls_timer_reg_count_6_ ( + .C(mgt_clk), + .D(plm_fsm_xl_cls_timer_reg_count_s[6]), + .Q(plm_fsm_xl_cls_timer_reg_count[6]), + .CLR(plm_rst) + ); + FDC plm_fsm_xl_cls_timer_reg_count_5_ ( + .C(mgt_clk), + .D(plm_fsm_xl_cls_timer_reg_count_s[5]), + .Q(plm_fsm_xl_cls_timer_reg_count[5]), + .CLR(plm_rst) + ); + FDC plm_fsm_xl_cls_timer_reg_count_4_ ( + .C(mgt_clk), + .D(plm_fsm_xl_cls_timer_reg_count_s[4]), + .Q(plm_fsm_xl_cls_timer_reg_count[4]), + .CLR(plm_rst) + ); + FDC plm_fsm_xl_cls_timer_reg_count_3_ ( + .C(mgt_clk), + .D(plm_fsm_xl_cls_timer_reg_count_s[3]), + .Q(plm_fsm_xl_cls_timer_reg_count[3]), + .CLR(plm_rst) + ); + FDC plm_fsm_xl_cls_timer_reg_count_2_ ( + .C(mgt_clk), + .D(plm_fsm_xl_cls_timer_reg_count_s[2]), + .Q(plm_fsm_xl_cls_timer_reg_count[2]), + .CLR(plm_rst) + ); + FDC plm_fsm_xl_cls_timer_reg_count_1_ ( + .C(mgt_clk), + .D(plm_fsm_xl_cls_timer_reg_count_s[1]), + .Q(plm_fsm_xl_cls_timer_reg_count[1]), + .CLR(plm_rst) + ); + FDC plm_fsm_xl_cls_timer_reg_count_0_ ( + .C(mgt_clk), + .D(plm_fsm_xl_cls_timer_reg_count_s[0]), + .Q(plm_fsm_xl_cls_timer_reg_count[0]), + .CLR(plm_rst) + ); + defparam plm_fsm_xl_cls_timer_reg_count_qxu_0_0_.INIT = 4'h8; + LUT2_L plm_fsm_xl_cls_timer_reg_count_qxu_0_0_ ( + .I0(plm_fsm_un1_reg_state_4_i_i_844), + .I1(plm_fsm_xl_cls_timer_reg_count[0]), + .LO(plm_fsm_xl_cls_timer_reg_count_qxu[0]) + ); + defparam plm_fsm_xl_cls_timer_reg_count_qxu_0_1_.INIT = 4'h8; + LUT2_L plm_fsm_xl_cls_timer_reg_count_qxu_0_1_ ( + .I0(plm_fsm_un1_reg_state_4_i_i_844), + .I1(plm_fsm_xl_cls_timer_reg_count[1]), + .LO(plm_fsm_xl_cls_timer_reg_count_qxu[1]) + ); + defparam plm_fsm_xl_cls_timer_reg_count_qxu_0_2_.INIT = 4'h8; + LUT2_L plm_fsm_xl_cls_timer_reg_count_qxu_0_2_ ( + .I0(plm_fsm_un1_reg_state_4_i_i_844), + .I1(plm_fsm_xl_cls_timer_reg_count[2]), + .LO(plm_fsm_xl_cls_timer_reg_count_qxu[2]) + ); + defparam plm_fsm_xl_cls_timer_reg_count_qxu_0_3_.INIT = 4'h8; + LUT2_L plm_fsm_xl_cls_timer_reg_count_qxu_0_3_ ( + .I0(plm_fsm_un1_reg_state_4_i_i_844), + .I1(plm_fsm_xl_cls_timer_reg_count[3]), + .LO(plm_fsm_xl_cls_timer_reg_count_qxu[3]) + ); + defparam plm_fsm_xl_cls_timer_reg_count_qxu_0_4_.INIT = 4'h8; + LUT2_L plm_fsm_xl_cls_timer_reg_count_qxu_0_4_ ( + .I0(plm_fsm_un1_reg_state_4_i_i_844), + .I1(plm_fsm_xl_cls_timer_reg_count[4]), + .LO(plm_fsm_xl_cls_timer_reg_count_qxu[4]) + ); + defparam plm_fsm_xl_cls_timer_reg_count_qxu_0_5_.INIT = 4'h8; + LUT2_L plm_fsm_xl_cls_timer_reg_count_qxu_0_5_ ( + .I0(plm_fsm_un1_reg_state_4_i_i_844), + .I1(plm_fsm_xl_cls_timer_reg_count[5]), + .LO(plm_fsm_xl_cls_timer_reg_count_qxu[5]) + ); + defparam plm_fsm_xl_cls_timer_reg_count_qxu_0_6_.INIT = 4'h8; + LUT2_L plm_fsm_xl_cls_timer_reg_count_qxu_0_6_ ( + .I0(plm_fsm_un1_reg_state_4_i_i_844), + .I1(plm_fsm_xl_cls_timer_reg_count[6]), + .LO(plm_fsm_xl_cls_timer_reg_count_qxu[6]) + ); + defparam plm_fsm_xl_cls_timer_reg_count_qxu_0_7_.INIT = 4'h8; + LUT2_L plm_fsm_xl_cls_timer_reg_count_qxu_0_7_ ( + .I0(plm_fsm_un1_reg_state_4_i_i_844), + .I1(plm_fsm_xl_cls_timer_reg_count[7]), + .LO(plm_fsm_xl_cls_timer_reg_count_qxu[7]) + ); + defparam plm_fsm_xl_cls_timer_reg_count_qxu_0_8_.INIT = 4'h8; + LUT2_L plm_fsm_xl_cls_timer_reg_count_qxu_0_8_ ( + .I0(plm_fsm_un1_reg_state_4_i_i_844), + .I1(plm_fsm_xl_cls_timer_reg_count[8]), + .LO(plm_fsm_xl_cls_timer_reg_count_qxu[8]) + ); + defparam plm_fsm_xl_cls_timer_reg_count_qxu_0_9_.INIT = 4'h8; + LUT2_L plm_fsm_xl_cls_timer_reg_count_qxu_0_9_ ( + .I0(plm_fsm_un1_reg_state_4_i_i_844), + .I1(plm_fsm_xl_cls_timer_reg_count[9]), + .LO(plm_fsm_xl_cls_timer_reg_count_qxu[9]) + ); + defparam plm_fsm_xl_cls_timer_reg_count_qxu_0_10_.INIT = 4'h8; + LUT2_L plm_fsm_xl_cls_timer_reg_count_qxu_0_10_ ( + .I0(plm_fsm_un1_reg_state_4_i_i_844), + .I1(plm_fsm_xl_cls_timer_reg_count[10]), + .LO(plm_fsm_xl_cls_timer_reg_count_qxu[10]) + ); + defparam plm_fsm_xl_cls_timer_reg_count_qxu_0_11_.INIT = 4'h8; + LUT2_L plm_fsm_xl_cls_timer_reg_count_qxu_0_11_ ( + .I0(plm_fsm_un1_reg_state_4_i_i_844), + .I1(plm_fsm_xl_cls_timer_reg_count[11]), + .LO(plm_fsm_xl_cls_timer_reg_count_qxu[11]) + ); + defparam plm_fsm_xl_cls_timer_reg_count_qxu_0_12_.INIT = 4'h8; + LUT2_L plm_fsm_xl_cls_timer_reg_count_qxu_0_12_ ( + .I0(plm_fsm_un1_reg_state_4_i_i_844), + .I1(plm_fsm_xl_cls_timer_reg_count[12]), + .LO(plm_fsm_xl_cls_timer_reg_count_qxu[12]) + ); + defparam plm_fsm_xl_cls_timer_reg_count_qxu_0_13_.INIT = 4'h8; + LUT2_L plm_fsm_xl_cls_timer_reg_count_qxu_0_13_ ( + .I0(plm_fsm_un1_reg_state_4_i_i_844), + .I1(plm_fsm_xl_cls_timer_reg_count[13]), + .LO(plm_fsm_xl_cls_timer_reg_count_qxu[13]) + ); + defparam plm_fsm_xl_cls_timer_reg_count_qxu_0_14_.INIT = 4'h8; + LUT2_L plm_fsm_xl_cls_timer_reg_count_qxu_0_14_ ( + .I0(plm_fsm_un1_reg_state_4_i_i_844), + .I1(plm_fsm_xl_cls_timer_reg_count[14]), + .LO(plm_fsm_xl_cls_timer_reg_count_qxu[14]) + ); + defparam plm_fsm_xl_cls_timer_reg_count_qxu_0_15_.INIT = 4'h8; + LUT2_L plm_fsm_xl_cls_timer_reg_count_qxu_0_15_ ( + .I0(plm_fsm_un1_reg_state_4_i_i_844), + .I1(plm_fsm_xl_cls_timer_reg_count[15]), + .LO(plm_fsm_xl_cls_timer_reg_count_qxu[15]) + ); + defparam plm_fsm_xl_cls_timer_reg_count_qxu_0_16_.INIT = 4'h8; + LUT2_L plm_fsm_xl_cls_timer_reg_count_qxu_0_16_ ( + .I0(plm_fsm_un1_reg_state_4_i_i_844), + .I1(plm_fsm_xl_cls_timer_reg_count[16]), + .LO(plm_fsm_xl_cls_timer_reg_count_qxu[16]) + ); + defparam plm_fsm_xl_cls_timer_reg_count_qxu_0_17_.INIT = 4'h8; + LUT2_L plm_fsm_xl_cls_timer_reg_count_qxu_0_17_ ( + .I0(plm_fsm_un1_reg_state_4_i_i_844), + .I1(plm_fsm_xl_cls_timer_reg_count[17]), + .LO(plm_fsm_xl_cls_timer_reg_count_qxu[17]) + ); + defparam plm_fsm_xl_cls_timer_reg_count_qxu_0_18_.INIT = 4'h8; + LUT2_L plm_fsm_xl_cls_timer_reg_count_qxu_0_18_ ( + .I0(plm_fsm_un1_reg_state_4_i_i_844), + .I1(plm_fsm_xl_cls_timer_reg_count[18]), + .LO(plm_fsm_xl_cls_timer_reg_count_qxu[18]) + ); + defparam plm_fsm_xl_cls_timer_reg_count_qxu_0_19_.INIT = 4'h8; + LUT2_L plm_fsm_xl_cls_timer_reg_count_qxu_0_19_ ( + .I0(plm_fsm_un1_reg_state_4_i_i_844), + .I1(plm_fsm_xl_cls_timer_reg_count[19]), + .LO(plm_fsm_xl_cls_timer_reg_count_qxu[19]) + ); + defparam plm_fsm_xl_cls_timer_reg_count_qxu_0_20_.INIT = 4'h8; + LUT2_L plm_fsm_xl_cls_timer_reg_count_qxu_0_20_ ( + .I0(plm_fsm_un1_reg_state_4_i_i_844), + .I1(plm_fsm_xl_cls_timer_reg_count[20]), + .LO(plm_fsm_xl_cls_timer_reg_count_qxu[20]) + ); + defparam plm_fsm_xl_cls_timer_reg_count_qxu_0_21_.INIT = 4'h8; + LUT2_L plm_fsm_xl_cls_timer_reg_count_qxu_0_21_ ( + .I0(plm_fsm_un1_reg_state_4_i_i_844), + .I1(plm_fsm_xl_cls_timer_reg_count[21]), + .LO(plm_fsm_xl_cls_timer_reg_count_qxu[21]) + ); + defparam plm_fsm_xl_cls_timer_reg_count_qxu_0_22_.INIT = 4'h8; + LUT2_L plm_fsm_xl_cls_timer_reg_count_qxu_0_22_ ( + .I0(plm_fsm_un1_reg_state_4_i_i_844), + .I1(plm_fsm_xl_cls_timer_reg_count[22]), + .LO(plm_fsm_xl_cls_timer_reg_count_qxu[22]) + ); + GND plm_fsm_xl_cla_timer_GND ( + .G(plm_fsm_xl_cla_timer_GND_1062) + ); + MUXCY_L plm_fsm_xl_cla_timer_reg_count_cry_0_ ( + .CI(plm_fsm_xl_cla_timer_un1_reg_state_5_i_i_1064), + .DI(plm_fsm_xl_cla_timer_GND_1062), + .LO(plm_fsm_xl_cla_timer_reg_count_cry[0]), + .S(plm_fsm_xl_cla_timer_reg_count_qxu[0]) + ); + XORCY plm_fsm_xl_cla_timer_reg_count_s_0_ ( + .CI(plm_fsm_xl_cla_timer_un1_reg_state_5_i_i_1064), + .LI(plm_fsm_xl_cla_timer_reg_count_qxu[0]), + .O(plm_fsm_xl_cla_timer_reg_count_s[0]) + ); + MUXCY_L plm_fsm_xl_cla_timer_reg_count_cry_1_ ( + .CI(plm_fsm_xl_cla_timer_reg_count_cry[0]), + .DI(plm_fsm_xl_cla_timer_GND_1062), + .LO(plm_fsm_xl_cla_timer_reg_count_cry[1]), + .S(plm_fsm_xl_cla_timer_reg_count_qxu[1]) + ); + XORCY plm_fsm_xl_cla_timer_reg_count_s_1_ ( + .CI(plm_fsm_xl_cla_timer_reg_count_cry[0]), + .LI(plm_fsm_xl_cla_timer_reg_count_qxu[1]), + .O(plm_fsm_xl_cla_timer_reg_count_s[1]) + ); + MUXCY_L plm_fsm_xl_cla_timer_reg_count_cry_2_ ( + .CI(plm_fsm_xl_cla_timer_reg_count_cry[1]), + .DI(plm_fsm_xl_cla_timer_GND_1062), + .LO(plm_fsm_xl_cla_timer_reg_count_cry[2]), + .S(plm_fsm_xl_cla_timer_reg_count_qxu[2]) + ); + XORCY plm_fsm_xl_cla_timer_reg_count_s_2_ ( + .CI(plm_fsm_xl_cla_timer_reg_count_cry[1]), + .LI(plm_fsm_xl_cla_timer_reg_count_qxu[2]), + .O(plm_fsm_xl_cla_timer_reg_count_s[2]) + ); + MUXCY_L plm_fsm_xl_cla_timer_reg_count_cry_3_ ( + .CI(plm_fsm_xl_cla_timer_reg_count_cry[2]), + .DI(plm_fsm_xl_cla_timer_GND_1062), + .LO(plm_fsm_xl_cla_timer_reg_count_cry[3]), + .S(plm_fsm_xl_cla_timer_reg_count_qxu[3]) + ); + XORCY plm_fsm_xl_cla_timer_reg_count_s_3_ ( + .CI(plm_fsm_xl_cla_timer_reg_count_cry[2]), + .LI(plm_fsm_xl_cla_timer_reg_count_qxu[3]), + .O(plm_fsm_xl_cla_timer_reg_count_s[3]) + ); + MUXCY_L plm_fsm_xl_cla_timer_reg_count_cry_4_ ( + .CI(plm_fsm_xl_cla_timer_reg_count_cry[3]), + .DI(plm_fsm_xl_cla_timer_GND_1062), + .LO(plm_fsm_xl_cla_timer_reg_count_cry[4]), + .S(plm_fsm_xl_cla_timer_reg_count_qxu[4]) + ); + XORCY plm_fsm_xl_cla_timer_reg_count_s_4_ ( + .CI(plm_fsm_xl_cla_timer_reg_count_cry[3]), + .LI(plm_fsm_xl_cla_timer_reg_count_qxu[4]), + .O(plm_fsm_xl_cla_timer_reg_count_s[4]) + ); + MUXCY_L plm_fsm_xl_cla_timer_reg_count_cry_5_ ( + .CI(plm_fsm_xl_cla_timer_reg_count_cry[4]), + .DI(plm_fsm_xl_cla_timer_GND_1062), + .LO(plm_fsm_xl_cla_timer_reg_count_cry[5]), + .S(plm_fsm_xl_cla_timer_reg_count_qxu[5]) + ); + XORCY plm_fsm_xl_cla_timer_reg_count_s_5_ ( + .CI(plm_fsm_xl_cla_timer_reg_count_cry[4]), + .LI(plm_fsm_xl_cla_timer_reg_count_qxu[5]), + .O(plm_fsm_xl_cla_timer_reg_count_s[5]) + ); + MUXCY_L plm_fsm_xl_cla_timer_reg_count_cry_6_ ( + .CI(plm_fsm_xl_cla_timer_reg_count_cry[5]), + .DI(plm_fsm_xl_cla_timer_GND_1062), + .LO(plm_fsm_xl_cla_timer_reg_count_cry[6]), + .S(plm_fsm_xl_cla_timer_reg_count_qxu[6]) + ); + XORCY plm_fsm_xl_cla_timer_reg_count_s_6_ ( + .CI(plm_fsm_xl_cla_timer_reg_count_cry[5]), + .LI(plm_fsm_xl_cla_timer_reg_count_qxu[6]), + .O(plm_fsm_xl_cla_timer_reg_count_s[6]) + ); + MUXCY_L plm_fsm_xl_cla_timer_reg_count_cry_7_ ( + .CI(plm_fsm_xl_cla_timer_reg_count_cry[6]), + .DI(plm_fsm_xl_cla_timer_GND_1062), + .LO(plm_fsm_xl_cla_timer_reg_count_cry[7]), + .S(plm_fsm_xl_cla_timer_reg_count_qxu[7]) + ); + XORCY plm_fsm_xl_cla_timer_reg_count_s_7_ ( + .CI(plm_fsm_xl_cla_timer_reg_count_cry[6]), + .LI(plm_fsm_xl_cla_timer_reg_count_qxu[7]), + .O(plm_fsm_xl_cla_timer_reg_count_s[7]) + ); + MUXCY_L plm_fsm_xl_cla_timer_reg_count_cry_8_ ( + .CI(plm_fsm_xl_cla_timer_reg_count_cry[7]), + .DI(plm_fsm_xl_cla_timer_GND_1062), + .LO(plm_fsm_xl_cla_timer_reg_count_cry[8]), + .S(plm_fsm_xl_cla_timer_reg_count_qxu[8]) + ); + XORCY plm_fsm_xl_cla_timer_reg_count_s_8_ ( + .CI(plm_fsm_xl_cla_timer_reg_count_cry[7]), + .LI(plm_fsm_xl_cla_timer_reg_count_qxu[8]), + .O(plm_fsm_xl_cla_timer_reg_count_s[8]) + ); + MUXCY_L plm_fsm_xl_cla_timer_reg_count_cry_9_ ( + .CI(plm_fsm_xl_cla_timer_reg_count_cry[8]), + .DI(plm_fsm_xl_cla_timer_GND_1062), + .LO(plm_fsm_xl_cla_timer_reg_count_cry[9]), + .S(plm_fsm_xl_cla_timer_reg_count_qxu[9]) + ); + XORCY plm_fsm_xl_cla_timer_reg_count_s_9_ ( + .CI(plm_fsm_xl_cla_timer_reg_count_cry[8]), + .LI(plm_fsm_xl_cla_timer_reg_count_qxu[9]), + .O(plm_fsm_xl_cla_timer_reg_count_s[9]) + ); + MUXCY_L plm_fsm_xl_cla_timer_reg_count_cry_10_ ( + .CI(plm_fsm_xl_cla_timer_reg_count_cry[9]), + .DI(plm_fsm_xl_cla_timer_GND_1062), + .LO(plm_fsm_xl_cla_timer_reg_count_cry[10]), + .S(plm_fsm_xl_cla_timer_reg_count_qxu[10]) + ); + XORCY plm_fsm_xl_cla_timer_reg_count_s_10_ ( + .CI(plm_fsm_xl_cla_timer_reg_count_cry[9]), + .LI(plm_fsm_xl_cla_timer_reg_count_qxu[10]), + .O(plm_fsm_xl_cla_timer_reg_count_s[10]) + ); + MUXCY_L plm_fsm_xl_cla_timer_reg_count_cry_11_ ( + .CI(plm_fsm_xl_cla_timer_reg_count_cry[10]), + .DI(plm_fsm_xl_cla_timer_GND_1062), + .LO(plm_fsm_xl_cla_timer_reg_count_cry[11]), + .S(plm_fsm_xl_cla_timer_reg_count_qxu[11]) + ); + XORCY plm_fsm_xl_cla_timer_reg_count_s_11_ ( + .CI(plm_fsm_xl_cla_timer_reg_count_cry[10]), + .LI(plm_fsm_xl_cla_timer_reg_count_qxu[11]), + .O(plm_fsm_xl_cla_timer_reg_count_s[11]) + ); + MUXCY_L plm_fsm_xl_cla_timer_reg_count_cry_12_ ( + .CI(plm_fsm_xl_cla_timer_reg_count_cry[11]), + .DI(plm_fsm_xl_cla_timer_GND_1062), + .LO(plm_fsm_xl_cla_timer_reg_count_cry[12]), + .S(plm_fsm_xl_cla_timer_reg_count_qxu[12]) + ); + XORCY plm_fsm_xl_cla_timer_reg_count_s_12_ ( + .CI(plm_fsm_xl_cla_timer_reg_count_cry[11]), + .LI(plm_fsm_xl_cla_timer_reg_count_qxu[12]), + .O(plm_fsm_xl_cla_timer_reg_count_s[12]) + ); + MUXCY_L plm_fsm_xl_cla_timer_reg_count_cry_13_ ( + .CI(plm_fsm_xl_cla_timer_reg_count_cry[12]), + .DI(plm_fsm_xl_cla_timer_GND_1062), + .LO(plm_fsm_xl_cla_timer_reg_count_cry[13]), + .S(plm_fsm_xl_cla_timer_reg_count_qxu[13]) + ); + XORCY plm_fsm_xl_cla_timer_reg_count_s_13_ ( + .CI(plm_fsm_xl_cla_timer_reg_count_cry[12]), + .LI(plm_fsm_xl_cla_timer_reg_count_qxu[13]), + .O(plm_fsm_xl_cla_timer_reg_count_s[13]) + ); + MUXCY_L plm_fsm_xl_cla_timer_reg_count_cry_14_ ( + .CI(plm_fsm_xl_cla_timer_reg_count_cry[13]), + .DI(plm_fsm_xl_cla_timer_GND_1062), + .LO(plm_fsm_xl_cla_timer_reg_count_cry[14]), + .S(plm_fsm_xl_cla_timer_reg_count_qxu[14]) + ); + XORCY plm_fsm_xl_cla_timer_reg_count_s_14_ ( + .CI(plm_fsm_xl_cla_timer_reg_count_cry[13]), + .LI(plm_fsm_xl_cla_timer_reg_count_qxu[14]), + .O(plm_fsm_xl_cla_timer_reg_count_s[14]) + ); + MUXCY_L plm_fsm_xl_cla_timer_reg_count_cry_15_ ( + .CI(plm_fsm_xl_cla_timer_reg_count_cry[14]), + .DI(plm_fsm_xl_cla_timer_GND_1062), + .LO(plm_fsm_xl_cla_timer_reg_count_cry[15]), + .S(plm_fsm_xl_cla_timer_reg_count_qxu[15]) + ); + XORCY plm_fsm_xl_cla_timer_reg_count_s_15_ ( + .CI(plm_fsm_xl_cla_timer_reg_count_cry[14]), + .LI(plm_fsm_xl_cla_timer_reg_count_qxu[15]), + .O(plm_fsm_xl_cla_timer_reg_count_s[15]) + ); + MUXCY_L plm_fsm_xl_cla_timer_reg_count_cry_16_ ( + .CI(plm_fsm_xl_cla_timer_reg_count_cry[15]), + .DI(plm_fsm_xl_cla_timer_GND_1062), + .LO(plm_fsm_xl_cla_timer_reg_count_cry[16]), + .S(plm_fsm_xl_cla_timer_reg_count_qxu[16]) + ); + XORCY plm_fsm_xl_cla_timer_reg_count_s_16_ ( + .CI(plm_fsm_xl_cla_timer_reg_count_cry[15]), + .LI(plm_fsm_xl_cla_timer_reg_count_qxu[16]), + .O(plm_fsm_xl_cla_timer_reg_count_s[16]) + ); + MUXCY_L plm_fsm_xl_cla_timer_reg_count_cry_17_ ( + .CI(plm_fsm_xl_cla_timer_reg_count_cry[16]), + .DI(plm_fsm_xl_cla_timer_GND_1062), + .LO(plm_fsm_xl_cla_timer_reg_count_cry[17]), + .S(plm_fsm_xl_cla_timer_reg_count_qxu[17]) + ); + XORCY plm_fsm_xl_cla_timer_reg_count_s_17_ ( + .CI(plm_fsm_xl_cla_timer_reg_count_cry[16]), + .LI(plm_fsm_xl_cla_timer_reg_count_qxu[17]), + .O(plm_fsm_xl_cla_timer_reg_count_s[17]) + ); + MUXCY_L plm_fsm_xl_cla_timer_reg_count_cry_18_ ( + .CI(plm_fsm_xl_cla_timer_reg_count_cry[17]), + .DI(plm_fsm_xl_cla_timer_GND_1062), + .LO(plm_fsm_xl_cla_timer_reg_count_cry[18]), + .S(plm_fsm_xl_cla_timer_reg_count_qxu[18]) + ); + XORCY plm_fsm_xl_cla_timer_reg_count_s_18_ ( + .CI(plm_fsm_xl_cla_timer_reg_count_cry[17]), + .LI(plm_fsm_xl_cla_timer_reg_count_qxu[18]), + .O(plm_fsm_xl_cla_timer_reg_count_s[18]) + ); + MUXCY_L plm_fsm_xl_cla_timer_reg_count_cry_19_ ( + .CI(plm_fsm_xl_cla_timer_reg_count_cry[18]), + .DI(plm_fsm_xl_cla_timer_GND_1062), + .LO(plm_fsm_xl_cla_timer_reg_count_cry[19]), + .S(plm_fsm_xl_cla_timer_reg_count_qxu[19]) + ); + XORCY plm_fsm_xl_cla_timer_reg_count_s_19_ ( + .CI(plm_fsm_xl_cla_timer_reg_count_cry[18]), + .LI(plm_fsm_xl_cla_timer_reg_count_qxu[19]), + .O(plm_fsm_xl_cla_timer_reg_count_s[19]) + ); + MUXCY_L plm_fsm_xl_cla_timer_reg_count_cry_20_ ( + .CI(plm_fsm_xl_cla_timer_reg_count_cry[19]), + .DI(plm_fsm_xl_cla_timer_GND_1062), + .LO(plm_fsm_xl_cla_timer_reg_count_cry[20]), + .S(plm_fsm_xl_cla_timer_reg_count_qxu[20]) + ); + XORCY plm_fsm_xl_cla_timer_reg_count_s_20_ ( + .CI(plm_fsm_xl_cla_timer_reg_count_cry[19]), + .LI(plm_fsm_xl_cla_timer_reg_count_qxu[20]), + .O(plm_fsm_xl_cla_timer_reg_count_s[20]) + ); + MUXCY_L plm_fsm_xl_cla_timer_reg_count_cry_21_ ( + .CI(plm_fsm_xl_cla_timer_reg_count_cry[20]), + .DI(plm_fsm_xl_cla_timer_GND_1062), + .LO(plm_fsm_xl_cla_timer_reg_count_cry[21]), + .S(plm_fsm_xl_cla_timer_reg_count_qxu[21]) + ); + XORCY plm_fsm_xl_cla_timer_reg_count_s_21_ ( + .CI(plm_fsm_xl_cla_timer_reg_count_cry[20]), + .LI(plm_fsm_xl_cla_timer_reg_count_qxu[21]), + .O(plm_fsm_xl_cla_timer_reg_count_s[21]) + ); + XORCY plm_fsm_xl_cla_timer_reg_count_s_22_ ( + .CI(plm_fsm_xl_cla_timer_reg_count_cry[21]), + .LI(plm_fsm_xl_cla_timer_reg_count_qxu[22]), + .O(plm_fsm_xl_cla_timer_reg_count_s[22]) + ); + defparam plm_fsm_xl_cla_timer_count_i_m3_i_m3_0_21_.INIT = 8'hD8; + LUT3 plm_fsm_xl_cla_timer_count_i_m3_i_m3_0_21_ ( + .I0(cfg_cfg_5072[507]), + .I1(plm_fsm_xl_cla_timer_reg_count[13]), + .I2(plm_fsm_xl_cla_timer_reg_count[21]), + .O(plm_fsm_xl_cla_timer_N_51429) + ); + defparam plm_fsm_xl_cla_timer_count_i_m3_i_m3_0_20_.INIT = 8'hD8; + LUT3 plm_fsm_xl_cla_timer_count_i_m3_i_m3_0_20_ ( + .I0(cfg_cfg_5072[507]), + .I1(plm_fsm_xl_cla_timer_reg_count[12]), + .I2(plm_fsm_xl_cla_timer_reg_count[20]), + .O(plm_fsm_xl_cla_timer_N_51428) + ); + defparam plm_fsm_xl_cla_timer_count_i_m3_i_m3_0_19_.INIT = 8'hD8; + LUT3_L plm_fsm_xl_cla_timer_count_i_m3_i_m3_0_19_ ( + .I0(cfg_cfg_5072[507]), + .I1(plm_fsm_xl_cla_timer_reg_count[11]), + .I2(plm_fsm_xl_cla_timer_reg_count[19]), + .LO(plm_fsm_xl_cla_timer_N_51427) + ); + defparam plm_fsm_xl_cla_timer_count_i_m3_i_m3_0_18_.INIT = 8'hD8; + LUT3 plm_fsm_xl_cla_timer_count_i_m3_i_m3_0_18_ ( + .I0(cfg_cfg_5072[507]), + .I1(plm_fsm_xl_cla_timer_reg_count[10]), + .I2(plm_fsm_xl_cla_timer_reg_count[18]), + .O(plm_fsm_xl_cla_timer_N_51426) + ); + defparam plm_fsm_xl_cla_timer_un1_reg_state_5_i_i.INIT = 4'hE; + LUT2 plm_fsm_xl_cla_timer_un1_reg_state_5_i_i ( + .I0(plm_fsm_reg_state_21__882), + .I1(plm_fsm_reg_state_22__881), + .O(plm_fsm_xl_cla_timer_un1_reg_state_5_i_i_1064) + ); + defparam plm_fsm_xl_cla_timer_un1_expired_2ms_0_a2_0_a4_0.INIT = 16'h0415; + LUT4_L plm_fsm_xl_cla_timer_un1_expired_2ms_0_a2_0_a4_0 ( + .I0(plm_fsm_xl_cla_timer_N_51427), + .I1(cfg_cfg_5072[507]), + .I2(plm_fsm_xl_cla_timer_reg_count[14]), + .I3(plm_fsm_xl_cla_timer_reg_count[22]), + .LO(plm_fsm_xl_cla_timer_un1_expired_2ms_0_a2_0_a4_0_1063) + ); + defparam plm_fsm_xl_cla_timer_un1_expired_2ms_0_a2_0_a4.INIT = 16'h0100; + LUT4 plm_fsm_xl_cla_timer_un1_expired_2ms_0_a2_0_a4 ( + .I0(plm_fsm_xl_cla_timer_N_51426), + .I1(plm_fsm_xl_cla_timer_N_51428), + .I2(plm_fsm_xl_cla_timer_N_51429), + .I3(plm_fsm_xl_cla_timer_un1_expired_2ms_0_a2_0_a4_0_1063), + .O(plm_fsm_N_51352) + ); + FDC plm_fsm_xl_cla_timer_reg_count_22_ ( + .C(mgt_clk), + .D(plm_fsm_xl_cla_timer_reg_count_s[22]), + .Q(plm_fsm_xl_cla_timer_reg_count[22]), + .CLR(plm_rst) + ); + FDC plm_fsm_xl_cla_timer_reg_count_21_ ( + .C(mgt_clk), + .D(plm_fsm_xl_cla_timer_reg_count_s[21]), + .Q(plm_fsm_xl_cla_timer_reg_count[21]), + .CLR(plm_rst) + ); + FDC plm_fsm_xl_cla_timer_reg_count_20_ ( + .C(mgt_clk), + .D(plm_fsm_xl_cla_timer_reg_count_s[20]), + .Q(plm_fsm_xl_cla_timer_reg_count[20]), + .CLR(plm_rst) + ); + FDC plm_fsm_xl_cla_timer_reg_count_19_ ( + .C(mgt_clk), + .D(plm_fsm_xl_cla_timer_reg_count_s[19]), + .Q(plm_fsm_xl_cla_timer_reg_count[19]), + .CLR(plm_rst) + ); + FDC plm_fsm_xl_cla_timer_reg_count_18_ ( + .C(mgt_clk), + .D(plm_fsm_xl_cla_timer_reg_count_s[18]), + .Q(plm_fsm_xl_cla_timer_reg_count[18]), + .CLR(plm_rst) + ); + FDC plm_fsm_xl_cla_timer_reg_count_17_ ( + .C(mgt_clk), + .D(plm_fsm_xl_cla_timer_reg_count_s[17]), + .Q(plm_fsm_xl_cla_timer_reg_count[17]), + .CLR(plm_rst) + ); + FDC plm_fsm_xl_cla_timer_reg_count_16_ ( + .C(mgt_clk), + .D(plm_fsm_xl_cla_timer_reg_count_s[16]), + .Q(plm_fsm_xl_cla_timer_reg_count[16]), + .CLR(plm_rst) + ); + FDC plm_fsm_xl_cla_timer_reg_count_15_ ( + .C(mgt_clk), + .D(plm_fsm_xl_cla_timer_reg_count_s[15]), + .Q(plm_fsm_xl_cla_timer_reg_count[15]), + .CLR(plm_rst) + ); + FDC plm_fsm_xl_cla_timer_reg_count_14_ ( + .C(mgt_clk), + .D(plm_fsm_xl_cla_timer_reg_count_s[14]), + .Q(plm_fsm_xl_cla_timer_reg_count[14]), + .CLR(plm_rst) + ); + FDC plm_fsm_xl_cla_timer_reg_count_13_ ( + .C(mgt_clk), + .D(plm_fsm_xl_cla_timer_reg_count_s[13]), + .Q(plm_fsm_xl_cla_timer_reg_count[13]), + .CLR(plm_rst) + ); + FDC plm_fsm_xl_cla_timer_reg_count_12_ ( + .C(mgt_clk), + .D(plm_fsm_xl_cla_timer_reg_count_s[12]), + .Q(plm_fsm_xl_cla_timer_reg_count[12]), + .CLR(plm_rst) + ); + FDC plm_fsm_xl_cla_timer_reg_count_11_ ( + .C(mgt_clk), + .D(plm_fsm_xl_cla_timer_reg_count_s[11]), + .Q(plm_fsm_xl_cla_timer_reg_count[11]), + .CLR(plm_rst) + ); + FDC plm_fsm_xl_cla_timer_reg_count_10_ ( + .C(mgt_clk), + .D(plm_fsm_xl_cla_timer_reg_count_s[10]), + .Q(plm_fsm_xl_cla_timer_reg_count[10]), + .CLR(plm_rst) + ); + FDC plm_fsm_xl_cla_timer_reg_count_9_ ( + .C(mgt_clk), + .D(plm_fsm_xl_cla_timer_reg_count_s[9]), + .Q(plm_fsm_xl_cla_timer_reg_count[9]), + .CLR(plm_rst) + ); + FDC plm_fsm_xl_cla_timer_reg_count_8_ ( + .C(mgt_clk), + .D(plm_fsm_xl_cla_timer_reg_count_s[8]), + .Q(plm_fsm_xl_cla_timer_reg_count[8]), + .CLR(plm_rst) + ); + FDC plm_fsm_xl_cla_timer_reg_count_7_ ( + .C(mgt_clk), + .D(plm_fsm_xl_cla_timer_reg_count_s[7]), + .Q(plm_fsm_xl_cla_timer_reg_count[7]), + .CLR(plm_rst) + ); + FDC plm_fsm_xl_cla_timer_reg_count_6_ ( + .C(mgt_clk), + .D(plm_fsm_xl_cla_timer_reg_count_s[6]), + .Q(plm_fsm_xl_cla_timer_reg_count[6]), + .CLR(plm_rst) + ); + FDC plm_fsm_xl_cla_timer_reg_count_5_ ( + .C(mgt_clk), + .D(plm_fsm_xl_cla_timer_reg_count_s[5]), + .Q(plm_fsm_xl_cla_timer_reg_count[5]), + .CLR(plm_rst) + ); + FDC plm_fsm_xl_cla_timer_reg_count_4_ ( + .C(mgt_clk), + .D(plm_fsm_xl_cla_timer_reg_count_s[4]), + .Q(plm_fsm_xl_cla_timer_reg_count[4]), + .CLR(plm_rst) + ); + FDC plm_fsm_xl_cla_timer_reg_count_3_ ( + .C(mgt_clk), + .D(plm_fsm_xl_cla_timer_reg_count_s[3]), + .Q(plm_fsm_xl_cla_timer_reg_count[3]), + .CLR(plm_rst) + ); + FDC plm_fsm_xl_cla_timer_reg_count_2_ ( + .C(mgt_clk), + .D(plm_fsm_xl_cla_timer_reg_count_s[2]), + .Q(plm_fsm_xl_cla_timer_reg_count[2]), + .CLR(plm_rst) + ); + FDC plm_fsm_xl_cla_timer_reg_count_1_ ( + .C(mgt_clk), + .D(plm_fsm_xl_cla_timer_reg_count_s[1]), + .Q(plm_fsm_xl_cla_timer_reg_count[1]), + .CLR(plm_rst) + ); + FDC plm_fsm_xl_cla_timer_reg_count_0_ ( + .C(mgt_clk), + .D(plm_fsm_xl_cla_timer_reg_count_s[0]), + .Q(plm_fsm_xl_cla_timer_reg_count[0]), + .CLR(plm_rst) + ); + defparam plm_fsm_xl_cla_timer_reg_count_qxu_0_0_.INIT = 4'h8; + LUT2_L plm_fsm_xl_cla_timer_reg_count_qxu_0_0_ ( + .I0(plm_fsm_xl_cla_timer_un1_reg_state_5_i_i_1064), + .I1(plm_fsm_xl_cla_timer_reg_count[0]), + .LO(plm_fsm_xl_cla_timer_reg_count_qxu[0]) + ); + defparam plm_fsm_xl_cla_timer_reg_count_qxu_0_1_.INIT = 4'h8; + LUT2_L plm_fsm_xl_cla_timer_reg_count_qxu_0_1_ ( + .I0(plm_fsm_xl_cla_timer_un1_reg_state_5_i_i_1064), + .I1(plm_fsm_xl_cla_timer_reg_count[1]), + .LO(plm_fsm_xl_cla_timer_reg_count_qxu[1]) + ); + defparam plm_fsm_xl_cla_timer_reg_count_qxu_0_2_.INIT = 4'h8; + LUT2_L plm_fsm_xl_cla_timer_reg_count_qxu_0_2_ ( + .I0(plm_fsm_xl_cla_timer_un1_reg_state_5_i_i_1064), + .I1(plm_fsm_xl_cla_timer_reg_count[2]), + .LO(plm_fsm_xl_cla_timer_reg_count_qxu[2]) + ); + defparam plm_fsm_xl_cla_timer_reg_count_qxu_0_3_.INIT = 4'h8; + LUT2_L plm_fsm_xl_cla_timer_reg_count_qxu_0_3_ ( + .I0(plm_fsm_xl_cla_timer_un1_reg_state_5_i_i_1064), + .I1(plm_fsm_xl_cla_timer_reg_count[3]), + .LO(plm_fsm_xl_cla_timer_reg_count_qxu[3]) + ); + defparam plm_fsm_xl_cla_timer_reg_count_qxu_0_4_.INIT = 4'h8; + LUT2_L plm_fsm_xl_cla_timer_reg_count_qxu_0_4_ ( + .I0(plm_fsm_xl_cla_timer_un1_reg_state_5_i_i_1064), + .I1(plm_fsm_xl_cla_timer_reg_count[4]), + .LO(plm_fsm_xl_cla_timer_reg_count_qxu[4]) + ); + defparam plm_fsm_xl_cla_timer_reg_count_qxu_0_5_.INIT = 4'h8; + LUT2_L plm_fsm_xl_cla_timer_reg_count_qxu_0_5_ ( + .I0(plm_fsm_xl_cla_timer_un1_reg_state_5_i_i_1064), + .I1(plm_fsm_xl_cla_timer_reg_count[5]), + .LO(plm_fsm_xl_cla_timer_reg_count_qxu[5]) + ); + defparam plm_fsm_xl_cla_timer_reg_count_qxu_0_6_.INIT = 4'h8; + LUT2_L plm_fsm_xl_cla_timer_reg_count_qxu_0_6_ ( + .I0(plm_fsm_xl_cla_timer_un1_reg_state_5_i_i_1064), + .I1(plm_fsm_xl_cla_timer_reg_count[6]), + .LO(plm_fsm_xl_cla_timer_reg_count_qxu[6]) + ); + defparam plm_fsm_xl_cla_timer_reg_count_qxu_0_7_.INIT = 4'h8; + LUT2_L plm_fsm_xl_cla_timer_reg_count_qxu_0_7_ ( + .I0(plm_fsm_xl_cla_timer_un1_reg_state_5_i_i_1064), + .I1(plm_fsm_xl_cla_timer_reg_count[7]), + .LO(plm_fsm_xl_cla_timer_reg_count_qxu[7]) + ); + defparam plm_fsm_xl_cla_timer_reg_count_qxu_0_8_.INIT = 4'h8; + LUT2_L plm_fsm_xl_cla_timer_reg_count_qxu_0_8_ ( + .I0(plm_fsm_xl_cla_timer_un1_reg_state_5_i_i_1064), + .I1(plm_fsm_xl_cla_timer_reg_count[8]), + .LO(plm_fsm_xl_cla_timer_reg_count_qxu[8]) + ); + defparam plm_fsm_xl_cla_timer_reg_count_qxu_0_9_.INIT = 4'h8; + LUT2_L plm_fsm_xl_cla_timer_reg_count_qxu_0_9_ ( + .I0(plm_fsm_xl_cla_timer_un1_reg_state_5_i_i_1064), + .I1(plm_fsm_xl_cla_timer_reg_count[9]), + .LO(plm_fsm_xl_cla_timer_reg_count_qxu[9]) + ); + defparam plm_fsm_xl_cla_timer_reg_count_qxu_0_10_.INIT = 4'h8; + LUT2_L plm_fsm_xl_cla_timer_reg_count_qxu_0_10_ ( + .I0(plm_fsm_xl_cla_timer_un1_reg_state_5_i_i_1064), + .I1(plm_fsm_xl_cla_timer_reg_count[10]), + .LO(plm_fsm_xl_cla_timer_reg_count_qxu[10]) + ); + defparam plm_fsm_xl_cla_timer_reg_count_qxu_0_11_.INIT = 4'h8; + LUT2_L plm_fsm_xl_cla_timer_reg_count_qxu_0_11_ ( + .I0(plm_fsm_xl_cla_timer_un1_reg_state_5_i_i_1064), + .I1(plm_fsm_xl_cla_timer_reg_count[11]), + .LO(plm_fsm_xl_cla_timer_reg_count_qxu[11]) + ); + defparam plm_fsm_xl_cla_timer_reg_count_qxu_0_12_.INIT = 4'h8; + LUT2_L plm_fsm_xl_cla_timer_reg_count_qxu_0_12_ ( + .I0(plm_fsm_xl_cla_timer_un1_reg_state_5_i_i_1064), + .I1(plm_fsm_xl_cla_timer_reg_count[12]), + .LO(plm_fsm_xl_cla_timer_reg_count_qxu[12]) + ); + defparam plm_fsm_xl_cla_timer_reg_count_qxu_0_13_.INIT = 4'h8; + LUT2_L plm_fsm_xl_cla_timer_reg_count_qxu_0_13_ ( + .I0(plm_fsm_xl_cla_timer_un1_reg_state_5_i_i_1064), + .I1(plm_fsm_xl_cla_timer_reg_count[13]), + .LO(plm_fsm_xl_cla_timer_reg_count_qxu[13]) + ); + defparam plm_fsm_xl_cla_timer_reg_count_qxu_0_14_.INIT = 4'h8; + LUT2_L plm_fsm_xl_cla_timer_reg_count_qxu_0_14_ ( + .I0(plm_fsm_xl_cla_timer_un1_reg_state_5_i_i_1064), + .I1(plm_fsm_xl_cla_timer_reg_count[14]), + .LO(plm_fsm_xl_cla_timer_reg_count_qxu[14]) + ); + defparam plm_fsm_xl_cla_timer_reg_count_qxu_0_15_.INIT = 4'h8; + LUT2_L plm_fsm_xl_cla_timer_reg_count_qxu_0_15_ ( + .I0(plm_fsm_xl_cla_timer_un1_reg_state_5_i_i_1064), + .I1(plm_fsm_xl_cla_timer_reg_count[15]), + .LO(plm_fsm_xl_cla_timer_reg_count_qxu[15]) + ); + defparam plm_fsm_xl_cla_timer_reg_count_qxu_0_16_.INIT = 4'h8; + LUT2_L plm_fsm_xl_cla_timer_reg_count_qxu_0_16_ ( + .I0(plm_fsm_xl_cla_timer_un1_reg_state_5_i_i_1064), + .I1(plm_fsm_xl_cla_timer_reg_count[16]), + .LO(plm_fsm_xl_cla_timer_reg_count_qxu[16]) + ); + defparam plm_fsm_xl_cla_timer_reg_count_qxu_0_17_.INIT = 4'h8; + LUT2_L plm_fsm_xl_cla_timer_reg_count_qxu_0_17_ ( + .I0(plm_fsm_xl_cla_timer_un1_reg_state_5_i_i_1064), + .I1(plm_fsm_xl_cla_timer_reg_count[17]), + .LO(plm_fsm_xl_cla_timer_reg_count_qxu[17]) + ); + defparam plm_fsm_xl_cla_timer_reg_count_qxu_0_18_.INIT = 4'h8; + LUT2_L plm_fsm_xl_cla_timer_reg_count_qxu_0_18_ ( + .I0(plm_fsm_xl_cla_timer_un1_reg_state_5_i_i_1064), + .I1(plm_fsm_xl_cla_timer_reg_count[18]), + .LO(plm_fsm_xl_cla_timer_reg_count_qxu[18]) + ); + defparam plm_fsm_xl_cla_timer_reg_count_qxu_0_19_.INIT = 4'h8; + LUT2_L plm_fsm_xl_cla_timer_reg_count_qxu_0_19_ ( + .I0(plm_fsm_xl_cla_timer_un1_reg_state_5_i_i_1064), + .I1(plm_fsm_xl_cla_timer_reg_count[19]), + .LO(plm_fsm_xl_cla_timer_reg_count_qxu[19]) + ); + defparam plm_fsm_xl_cla_timer_reg_count_qxu_0_20_.INIT = 4'h8; + LUT2_L plm_fsm_xl_cla_timer_reg_count_qxu_0_20_ ( + .I0(plm_fsm_xl_cla_timer_un1_reg_state_5_i_i_1064), + .I1(plm_fsm_xl_cla_timer_reg_count[20]), + .LO(plm_fsm_xl_cla_timer_reg_count_qxu[20]) + ); + defparam plm_fsm_xl_cla_timer_reg_count_qxu_0_21_.INIT = 4'h8; + LUT2_L plm_fsm_xl_cla_timer_reg_count_qxu_0_21_ ( + .I0(plm_fsm_xl_cla_timer_un1_reg_state_5_i_i_1064), + .I1(plm_fsm_xl_cla_timer_reg_count[21]), + .LO(plm_fsm_xl_cla_timer_reg_count_qxu[21]) + ); + defparam plm_fsm_xl_cla_timer_reg_count_qxu_0_22_.INIT = 4'h8; + LUT2_L plm_fsm_xl_cla_timer_reg_count_qxu_0_22_ ( + .I0(plm_fsm_xl_cla_timer_un1_reg_state_5_i_i_1064), + .I1(plm_fsm_xl_cla_timer_reg_count[22]), + .LO(plm_fsm_xl_cla_timer_reg_count_qxu[22]) + ); + GND plm_fsm_xl_clw_timer_GND ( + .G(plm_fsm_xl_clw_timer_GND_1065) + ); + MUXCY_L plm_fsm_xl_clw_timer_reg_count_cry_0_ ( + .CI(plm_fsm_reg_state_23__880), + .DI(plm_fsm_xl_clw_timer_GND_1065), + .LO(plm_fsm_xl_clw_timer_reg_count_cry[0]), + .S(plm_fsm_xl_clw_timer_reg_count_qxu[0]) + ); + XORCY plm_fsm_xl_clw_timer_reg_count_s_0_ ( + .CI(plm_fsm_reg_state_23__880), + .LI(plm_fsm_xl_clw_timer_reg_count_qxu[0]), + .O(plm_fsm_xl_clw_timer_reg_count_s[0]) + ); + MUXCY_L plm_fsm_xl_clw_timer_reg_count_cry_1_ ( + .CI(plm_fsm_xl_clw_timer_reg_count_cry[0]), + .DI(plm_fsm_xl_clw_timer_GND_1065), + .LO(plm_fsm_xl_clw_timer_reg_count_cry[1]), + .S(plm_fsm_xl_clw_timer_reg_count_qxu[1]) + ); + XORCY plm_fsm_xl_clw_timer_reg_count_s_1_ ( + .CI(plm_fsm_xl_clw_timer_reg_count_cry[0]), + .LI(plm_fsm_xl_clw_timer_reg_count_qxu[1]), + .O(plm_fsm_xl_clw_timer_reg_count_s[1]) + ); + MUXCY_L plm_fsm_xl_clw_timer_reg_count_cry_2_ ( + .CI(plm_fsm_xl_clw_timer_reg_count_cry[1]), + .DI(plm_fsm_xl_clw_timer_GND_1065), + .LO(plm_fsm_xl_clw_timer_reg_count_cry[2]), + .S(plm_fsm_xl_clw_timer_reg_count_qxu[2]) + ); + XORCY plm_fsm_xl_clw_timer_reg_count_s_2_ ( + .CI(plm_fsm_xl_clw_timer_reg_count_cry[1]), + .LI(plm_fsm_xl_clw_timer_reg_count_qxu[2]), + .O(plm_fsm_xl_clw_timer_reg_count_s[2]) + ); + MUXCY_L plm_fsm_xl_clw_timer_reg_count_cry_3_ ( + .CI(plm_fsm_xl_clw_timer_reg_count_cry[2]), + .DI(plm_fsm_xl_clw_timer_GND_1065), + .LO(plm_fsm_xl_clw_timer_reg_count_cry[3]), + .S(plm_fsm_xl_clw_timer_reg_count_qxu[3]) + ); + XORCY plm_fsm_xl_clw_timer_reg_count_s_3_ ( + .CI(plm_fsm_xl_clw_timer_reg_count_cry[2]), + .LI(plm_fsm_xl_clw_timer_reg_count_qxu[3]), + .O(plm_fsm_xl_clw_timer_reg_count_s[3]) + ); + MUXCY_L plm_fsm_xl_clw_timer_reg_count_cry_4_ ( + .CI(plm_fsm_xl_clw_timer_reg_count_cry[3]), + .DI(plm_fsm_xl_clw_timer_GND_1065), + .LO(plm_fsm_xl_clw_timer_reg_count_cry[4]), + .S(plm_fsm_xl_clw_timer_reg_count_qxu[4]) + ); + XORCY plm_fsm_xl_clw_timer_reg_count_s_4_ ( + .CI(plm_fsm_xl_clw_timer_reg_count_cry[3]), + .LI(plm_fsm_xl_clw_timer_reg_count_qxu[4]), + .O(plm_fsm_xl_clw_timer_reg_count_s[4]) + ); + MUXCY_L plm_fsm_xl_clw_timer_reg_count_cry_5_ ( + .CI(plm_fsm_xl_clw_timer_reg_count_cry[4]), + .DI(plm_fsm_xl_clw_timer_GND_1065), + .LO(plm_fsm_xl_clw_timer_reg_count_cry[5]), + .S(plm_fsm_xl_clw_timer_reg_count_qxu[5]) + ); + XORCY plm_fsm_xl_clw_timer_reg_count_s_5_ ( + .CI(plm_fsm_xl_clw_timer_reg_count_cry[4]), + .LI(plm_fsm_xl_clw_timer_reg_count_qxu[5]), + .O(plm_fsm_xl_clw_timer_reg_count_s[5]) + ); + MUXCY_L plm_fsm_xl_clw_timer_reg_count_cry_6_ ( + .CI(plm_fsm_xl_clw_timer_reg_count_cry[5]), + .DI(plm_fsm_xl_clw_timer_GND_1065), + .LO(plm_fsm_xl_clw_timer_reg_count_cry[6]), + .S(plm_fsm_xl_clw_timer_reg_count_qxu[6]) + ); + XORCY plm_fsm_xl_clw_timer_reg_count_s_6_ ( + .CI(plm_fsm_xl_clw_timer_reg_count_cry[5]), + .LI(plm_fsm_xl_clw_timer_reg_count_qxu[6]), + .O(plm_fsm_xl_clw_timer_reg_count_s[6]) + ); + MUXCY_L plm_fsm_xl_clw_timer_reg_count_cry_7_ ( + .CI(plm_fsm_xl_clw_timer_reg_count_cry[6]), + .DI(plm_fsm_xl_clw_timer_GND_1065), + .LO(plm_fsm_xl_clw_timer_reg_count_cry[7]), + .S(plm_fsm_xl_clw_timer_reg_count_qxu[7]) + ); + XORCY plm_fsm_xl_clw_timer_reg_count_s_7_ ( + .CI(plm_fsm_xl_clw_timer_reg_count_cry[6]), + .LI(plm_fsm_xl_clw_timer_reg_count_qxu[7]), + .O(plm_fsm_xl_clw_timer_reg_count_s[7]) + ); + MUXCY_L plm_fsm_xl_clw_timer_reg_count_cry_8_ ( + .CI(plm_fsm_xl_clw_timer_reg_count_cry[7]), + .DI(plm_fsm_xl_clw_timer_GND_1065), + .LO(plm_fsm_xl_clw_timer_reg_count_cry[8]), + .S(plm_fsm_xl_clw_timer_reg_count_qxu[8]) + ); + XORCY plm_fsm_xl_clw_timer_reg_count_s_8_ ( + .CI(plm_fsm_xl_clw_timer_reg_count_cry[7]), + .LI(plm_fsm_xl_clw_timer_reg_count_qxu[8]), + .O(plm_fsm_xl_clw_timer_reg_count_s[8]) + ); + MUXCY_L plm_fsm_xl_clw_timer_reg_count_cry_9_ ( + .CI(plm_fsm_xl_clw_timer_reg_count_cry[8]), + .DI(plm_fsm_xl_clw_timer_GND_1065), + .LO(plm_fsm_xl_clw_timer_reg_count_cry[9]), + .S(plm_fsm_xl_clw_timer_reg_count_qxu[9]) + ); + XORCY plm_fsm_xl_clw_timer_reg_count_s_9_ ( + .CI(plm_fsm_xl_clw_timer_reg_count_cry[8]), + .LI(plm_fsm_xl_clw_timer_reg_count_qxu[9]), + .O(plm_fsm_xl_clw_timer_reg_count_s[9]) + ); + MUXCY_L plm_fsm_xl_clw_timer_reg_count_cry_10_ ( + .CI(plm_fsm_xl_clw_timer_reg_count_cry[9]), + .DI(plm_fsm_xl_clw_timer_GND_1065), + .LO(plm_fsm_xl_clw_timer_reg_count_cry[10]), + .S(plm_fsm_xl_clw_timer_reg_count_qxu[10]) + ); + XORCY plm_fsm_xl_clw_timer_reg_count_s_10_ ( + .CI(plm_fsm_xl_clw_timer_reg_count_cry[9]), + .LI(plm_fsm_xl_clw_timer_reg_count_qxu[10]), + .O(plm_fsm_xl_clw_timer_reg_count_s[10]) + ); + MUXCY_L plm_fsm_xl_clw_timer_reg_count_cry_11_ ( + .CI(plm_fsm_xl_clw_timer_reg_count_cry[10]), + .DI(plm_fsm_xl_clw_timer_GND_1065), + .LO(plm_fsm_xl_clw_timer_reg_count_cry[11]), + .S(plm_fsm_xl_clw_timer_reg_count_qxu[11]) + ); + XORCY plm_fsm_xl_clw_timer_reg_count_s_11_ ( + .CI(plm_fsm_xl_clw_timer_reg_count_cry[10]), + .LI(plm_fsm_xl_clw_timer_reg_count_qxu[11]), + .O(plm_fsm_xl_clw_timer_reg_count_s[11]) + ); + MUXCY_L plm_fsm_xl_clw_timer_reg_count_cry_12_ ( + .CI(plm_fsm_xl_clw_timer_reg_count_cry[11]), + .DI(plm_fsm_xl_clw_timer_GND_1065), + .LO(plm_fsm_xl_clw_timer_reg_count_cry[12]), + .S(plm_fsm_xl_clw_timer_reg_count_qxu[12]) + ); + XORCY plm_fsm_xl_clw_timer_reg_count_s_12_ ( + .CI(plm_fsm_xl_clw_timer_reg_count_cry[11]), + .LI(plm_fsm_xl_clw_timer_reg_count_qxu[12]), + .O(plm_fsm_xl_clw_timer_reg_count_s[12]) + ); + MUXCY_L plm_fsm_xl_clw_timer_reg_count_cry_13_ ( + .CI(plm_fsm_xl_clw_timer_reg_count_cry[12]), + .DI(plm_fsm_xl_clw_timer_GND_1065), + .LO(plm_fsm_xl_clw_timer_reg_count_cry[13]), + .S(plm_fsm_xl_clw_timer_reg_count_qxu[13]) + ); + XORCY plm_fsm_xl_clw_timer_reg_count_s_13_ ( + .CI(plm_fsm_xl_clw_timer_reg_count_cry[12]), + .LI(plm_fsm_xl_clw_timer_reg_count_qxu[13]), + .O(plm_fsm_xl_clw_timer_reg_count_s[13]) + ); + MUXCY_L plm_fsm_xl_clw_timer_reg_count_cry_14_ ( + .CI(plm_fsm_xl_clw_timer_reg_count_cry[13]), + .DI(plm_fsm_xl_clw_timer_GND_1065), + .LO(plm_fsm_xl_clw_timer_reg_count_cry[14]), + .S(plm_fsm_xl_clw_timer_reg_count_qxu[14]) + ); + XORCY plm_fsm_xl_clw_timer_reg_count_s_14_ ( + .CI(plm_fsm_xl_clw_timer_reg_count_cry[13]), + .LI(plm_fsm_xl_clw_timer_reg_count_qxu[14]), + .O(plm_fsm_xl_clw_timer_reg_count_s[14]) + ); + MUXCY_L plm_fsm_xl_clw_timer_reg_count_cry_15_ ( + .CI(plm_fsm_xl_clw_timer_reg_count_cry[14]), + .DI(plm_fsm_xl_clw_timer_GND_1065), + .LO(plm_fsm_xl_clw_timer_reg_count_cry[15]), + .S(plm_fsm_xl_clw_timer_reg_count_qxu[15]) + ); + XORCY plm_fsm_xl_clw_timer_reg_count_s_15_ ( + .CI(plm_fsm_xl_clw_timer_reg_count_cry[14]), + .LI(plm_fsm_xl_clw_timer_reg_count_qxu[15]), + .O(plm_fsm_xl_clw_timer_reg_count_s[15]) + ); + MUXCY_L plm_fsm_xl_clw_timer_reg_count_cry_16_ ( + .CI(plm_fsm_xl_clw_timer_reg_count_cry[15]), + .DI(plm_fsm_xl_clw_timer_GND_1065), + .LO(plm_fsm_xl_clw_timer_reg_count_cry[16]), + .S(plm_fsm_xl_clw_timer_reg_count_qxu[16]) + ); + XORCY plm_fsm_xl_clw_timer_reg_count_s_16_ ( + .CI(plm_fsm_xl_clw_timer_reg_count_cry[15]), + .LI(plm_fsm_xl_clw_timer_reg_count_qxu[16]), + .O(plm_fsm_xl_clw_timer_reg_count_s[16]) + ); + MUXCY_L plm_fsm_xl_clw_timer_reg_count_cry_17_ ( + .CI(plm_fsm_xl_clw_timer_reg_count_cry[16]), + .DI(plm_fsm_xl_clw_timer_GND_1065), + .LO(plm_fsm_xl_clw_timer_reg_count_cry[17]), + .S(plm_fsm_xl_clw_timer_reg_count_qxu[17]) + ); + XORCY plm_fsm_xl_clw_timer_reg_count_s_17_ ( + .CI(plm_fsm_xl_clw_timer_reg_count_cry[16]), + .LI(plm_fsm_xl_clw_timer_reg_count_qxu[17]), + .O(plm_fsm_xl_clw_timer_reg_count_s[17]) + ); + MUXCY_L plm_fsm_xl_clw_timer_reg_count_cry_18_ ( + .CI(plm_fsm_xl_clw_timer_reg_count_cry[17]), + .DI(plm_fsm_xl_clw_timer_GND_1065), + .LO(plm_fsm_xl_clw_timer_reg_count_cry[18]), + .S(plm_fsm_xl_clw_timer_reg_count_qxu[18]) + ); + XORCY plm_fsm_xl_clw_timer_reg_count_s_18_ ( + .CI(plm_fsm_xl_clw_timer_reg_count_cry[17]), + .LI(plm_fsm_xl_clw_timer_reg_count_qxu[18]), + .O(plm_fsm_xl_clw_timer_reg_count_s[18]) + ); + MUXCY_L plm_fsm_xl_clw_timer_reg_count_cry_19_ ( + .CI(plm_fsm_xl_clw_timer_reg_count_cry[18]), + .DI(plm_fsm_xl_clw_timer_GND_1065), + .LO(plm_fsm_xl_clw_timer_reg_count_cry[19]), + .S(plm_fsm_xl_clw_timer_reg_count_qxu[19]) + ); + XORCY plm_fsm_xl_clw_timer_reg_count_s_19_ ( + .CI(plm_fsm_xl_clw_timer_reg_count_cry[18]), + .LI(plm_fsm_xl_clw_timer_reg_count_qxu[19]), + .O(plm_fsm_xl_clw_timer_reg_count_s[19]) + ); + MUXCY_L plm_fsm_xl_clw_timer_reg_count_cry_20_ ( + .CI(plm_fsm_xl_clw_timer_reg_count_cry[19]), + .DI(plm_fsm_xl_clw_timer_GND_1065), + .LO(plm_fsm_xl_clw_timer_reg_count_cry[20]), + .S(plm_fsm_xl_clw_timer_reg_count_qxu[20]) + ); + XORCY plm_fsm_xl_clw_timer_reg_count_s_20_ ( + .CI(plm_fsm_xl_clw_timer_reg_count_cry[19]), + .LI(plm_fsm_xl_clw_timer_reg_count_qxu[20]), + .O(plm_fsm_xl_clw_timer_reg_count_s[20]) + ); + MUXCY_L plm_fsm_xl_clw_timer_reg_count_cry_21_ ( + .CI(plm_fsm_xl_clw_timer_reg_count_cry[20]), + .DI(plm_fsm_xl_clw_timer_GND_1065), + .LO(plm_fsm_xl_clw_timer_reg_count_cry[21]), + .S(plm_fsm_xl_clw_timer_reg_count_qxu[21]) + ); + XORCY plm_fsm_xl_clw_timer_reg_count_s_21_ ( + .CI(plm_fsm_xl_clw_timer_reg_count_cry[20]), + .LI(plm_fsm_xl_clw_timer_reg_count_qxu[21]), + .O(plm_fsm_xl_clw_timer_reg_count_s[21]) + ); + XORCY plm_fsm_xl_clw_timer_reg_count_s_22_ ( + .CI(plm_fsm_xl_clw_timer_reg_count_cry[21]), + .LI(plm_fsm_xl_clw_timer_reg_count_qxu[22]), + .O(plm_fsm_xl_clw_timer_reg_count_s[22]) + ); + defparam plm_fsm_xl_clw_timer_count_i_m3_i_m3_0_18_.INIT = 8'hD8; + LUT3 plm_fsm_xl_clw_timer_count_i_m3_i_m3_0_18_ ( + .I0(cfg_cfg_5072[507]), + .I1(plm_fsm_xl_clw_timer_reg_count[10]), + .I2(plm_fsm_xl_clw_timer_reg_count[18]), + .O(plm_fsm_xl_clw_timer_N_51431) + ); + defparam plm_fsm_xl_clw_timer_count_i_m3_i_m3_0_19_.INIT = 8'hD8; + LUT3_L plm_fsm_xl_clw_timer_count_i_m3_i_m3_0_19_ ( + .I0(cfg_cfg_5072[507]), + .I1(plm_fsm_xl_clw_timer_reg_count[11]), + .I2(plm_fsm_xl_clw_timer_reg_count[19]), + .LO(plm_fsm_xl_clw_timer_N_51432) + ); + defparam plm_fsm_xl_clw_timer_count_i_m3_i_m3_0_20_.INIT = 8'hD8; + LUT3 plm_fsm_xl_clw_timer_count_i_m3_i_m3_0_20_ ( + .I0(cfg_cfg_5072[507]), + .I1(plm_fsm_xl_clw_timer_reg_count[12]), + .I2(plm_fsm_xl_clw_timer_reg_count[20]), + .O(plm_fsm_xl_clw_timer_N_51433) + ); + defparam plm_fsm_xl_clw_timer_count_i_m3_i_m3_0_21_.INIT = 8'hD8; + LUT3 plm_fsm_xl_clw_timer_count_i_m3_i_m3_0_21_ ( + .I0(cfg_cfg_5072[507]), + .I1(plm_fsm_xl_clw_timer_reg_count[13]), + .I2(plm_fsm_xl_clw_timer_reg_count[21]), + .O(plm_fsm_xl_clw_timer_N_51434) + ); + defparam plm_fsm_xl_clw_timer_un1_expired_2ms_0_a2_0_a4_0.INIT = 16'h0415; + LUT4_L plm_fsm_xl_clw_timer_un1_expired_2ms_0_a2_0_a4_0 ( + .I0(plm_fsm_xl_clw_timer_N_51432), + .I1(cfg_cfg_5072[507]), + .I2(plm_fsm_xl_clw_timer_reg_count[14]), + .I3(plm_fsm_xl_clw_timer_reg_count[22]), + .LO(plm_fsm_xl_clw_timer_un1_expired_2ms_0_a2_0_a4_0_1066) + ); + defparam plm_fsm_xl_clw_timer_un1_expired_2ms_0_a2_0_a4.INIT = 16'h0100; + LUT4 plm_fsm_xl_clw_timer_un1_expired_2ms_0_a2_0_a4 ( + .I0(plm_fsm_xl_clw_timer_N_51431), + .I1(plm_fsm_xl_clw_timer_N_51433), + .I2(plm_fsm_xl_clw_timer_N_51434), + .I3(plm_fsm_xl_clw_timer_un1_expired_2ms_0_a2_0_a4_0_1066), + .O(plm_fsm_N_51356) + ); + FDC plm_fsm_xl_clw_timer_reg_count_22_ ( + .C(mgt_clk), + .D(plm_fsm_xl_clw_timer_reg_count_s[22]), + .Q(plm_fsm_xl_clw_timer_reg_count[22]), + .CLR(plm_rst) + ); + FDC plm_fsm_xl_clw_timer_reg_count_21_ ( + .C(mgt_clk), + .D(plm_fsm_xl_clw_timer_reg_count_s[21]), + .Q(plm_fsm_xl_clw_timer_reg_count[21]), + .CLR(plm_rst) + ); + FDC plm_fsm_xl_clw_timer_reg_count_20_ ( + .C(mgt_clk), + .D(plm_fsm_xl_clw_timer_reg_count_s[20]), + .Q(plm_fsm_xl_clw_timer_reg_count[20]), + .CLR(plm_rst) + ); + FDC plm_fsm_xl_clw_timer_reg_count_19_ ( + .C(mgt_clk), + .D(plm_fsm_xl_clw_timer_reg_count_s[19]), + .Q(plm_fsm_xl_clw_timer_reg_count[19]), + .CLR(plm_rst) + ); + FDC plm_fsm_xl_clw_timer_reg_count_18_ ( + .C(mgt_clk), + .D(plm_fsm_xl_clw_timer_reg_count_s[18]), + .Q(plm_fsm_xl_clw_timer_reg_count[18]), + .CLR(plm_rst) + ); + FDC plm_fsm_xl_clw_timer_reg_count_17_ ( + .C(mgt_clk), + .D(plm_fsm_xl_clw_timer_reg_count_s[17]), + .Q(plm_fsm_xl_clw_timer_reg_count[17]), + .CLR(plm_rst) + ); + FDC plm_fsm_xl_clw_timer_reg_count_16_ ( + .C(mgt_clk), + .D(plm_fsm_xl_clw_timer_reg_count_s[16]), + .Q(plm_fsm_xl_clw_timer_reg_count[16]), + .CLR(plm_rst) + ); + FDC plm_fsm_xl_clw_timer_reg_count_15_ ( + .C(mgt_clk), + .D(plm_fsm_xl_clw_timer_reg_count_s[15]), + .Q(plm_fsm_xl_clw_timer_reg_count[15]), + .CLR(plm_rst) + ); + FDC plm_fsm_xl_clw_timer_reg_count_14_ ( + .C(mgt_clk), + .D(plm_fsm_xl_clw_timer_reg_count_s[14]), + .Q(plm_fsm_xl_clw_timer_reg_count[14]), + .CLR(plm_rst) + ); + FDC plm_fsm_xl_clw_timer_reg_count_13_ ( + .C(mgt_clk), + .D(plm_fsm_xl_clw_timer_reg_count_s[13]), + .Q(plm_fsm_xl_clw_timer_reg_count[13]), + .CLR(plm_rst) + ); + FDC plm_fsm_xl_clw_timer_reg_count_12_ ( + .C(mgt_clk), + .D(plm_fsm_xl_clw_timer_reg_count_s[12]), + .Q(plm_fsm_xl_clw_timer_reg_count[12]), + .CLR(plm_rst) + ); + FDC plm_fsm_xl_clw_timer_reg_count_11_ ( + .C(mgt_clk), + .D(plm_fsm_xl_clw_timer_reg_count_s[11]), + .Q(plm_fsm_xl_clw_timer_reg_count[11]), + .CLR(plm_rst) + ); + FDC plm_fsm_xl_clw_timer_reg_count_10_ ( + .C(mgt_clk), + .D(plm_fsm_xl_clw_timer_reg_count_s[10]), + .Q(plm_fsm_xl_clw_timer_reg_count[10]), + .CLR(plm_rst) + ); + FDC plm_fsm_xl_clw_timer_reg_count_9_ ( + .C(mgt_clk), + .D(plm_fsm_xl_clw_timer_reg_count_s[9]), + .Q(plm_fsm_xl_clw_timer_reg_count[9]), + .CLR(plm_rst) + ); + FDC plm_fsm_xl_clw_timer_reg_count_8_ ( + .C(mgt_clk), + .D(plm_fsm_xl_clw_timer_reg_count_s[8]), + .Q(plm_fsm_xl_clw_timer_reg_count[8]), + .CLR(plm_rst) + ); + FDC plm_fsm_xl_clw_timer_reg_count_7_ ( + .C(mgt_clk), + .D(plm_fsm_xl_clw_timer_reg_count_s[7]), + .Q(plm_fsm_xl_clw_timer_reg_count[7]), + .CLR(plm_rst) + ); + FDC plm_fsm_xl_clw_timer_reg_count_6_ ( + .C(mgt_clk), + .D(plm_fsm_xl_clw_timer_reg_count_s[6]), + .Q(plm_fsm_xl_clw_timer_reg_count[6]), + .CLR(plm_rst) + ); + FDC plm_fsm_xl_clw_timer_reg_count_5_ ( + .C(mgt_clk), + .D(plm_fsm_xl_clw_timer_reg_count_s[5]), + .Q(plm_fsm_xl_clw_timer_reg_count[5]), + .CLR(plm_rst) + ); + FDC plm_fsm_xl_clw_timer_reg_count_4_ ( + .C(mgt_clk), + .D(plm_fsm_xl_clw_timer_reg_count_s[4]), + .Q(plm_fsm_xl_clw_timer_reg_count[4]), + .CLR(plm_rst) + ); + FDC plm_fsm_xl_clw_timer_reg_count_3_ ( + .C(mgt_clk), + .D(plm_fsm_xl_clw_timer_reg_count_s[3]), + .Q(plm_fsm_xl_clw_timer_reg_count[3]), + .CLR(plm_rst) + ); + FDC plm_fsm_xl_clw_timer_reg_count_2_ ( + .C(mgt_clk), + .D(plm_fsm_xl_clw_timer_reg_count_s[2]), + .Q(plm_fsm_xl_clw_timer_reg_count[2]), + .CLR(plm_rst) + ); + FDC plm_fsm_xl_clw_timer_reg_count_1_ ( + .C(mgt_clk), + .D(plm_fsm_xl_clw_timer_reg_count_s[1]), + .Q(plm_fsm_xl_clw_timer_reg_count[1]), + .CLR(plm_rst) + ); + FDC plm_fsm_xl_clw_timer_reg_count_0_ ( + .C(mgt_clk), + .D(plm_fsm_xl_clw_timer_reg_count_s[0]), + .Q(plm_fsm_xl_clw_timer_reg_count[0]), + .CLR(plm_rst) + ); + defparam plm_fsm_xl_clw_timer_reg_count_qxu_0_0_.INIT = 4'h8; + LUT2_L plm_fsm_xl_clw_timer_reg_count_qxu_0_0_ ( + .I0(plm_fsm_reg_state_23__880), + .I1(plm_fsm_xl_clw_timer_reg_count[0]), + .LO(plm_fsm_xl_clw_timer_reg_count_qxu[0]) + ); + defparam plm_fsm_xl_clw_timer_reg_count_qxu_0_1_.INIT = 4'h8; + LUT2_L plm_fsm_xl_clw_timer_reg_count_qxu_0_1_ ( + .I0(plm_fsm_reg_state_23__880), + .I1(plm_fsm_xl_clw_timer_reg_count[1]), + .LO(plm_fsm_xl_clw_timer_reg_count_qxu[1]) + ); + defparam plm_fsm_xl_clw_timer_reg_count_qxu_0_2_.INIT = 4'h8; + LUT2_L plm_fsm_xl_clw_timer_reg_count_qxu_0_2_ ( + .I0(plm_fsm_reg_state_23__880), + .I1(plm_fsm_xl_clw_timer_reg_count[2]), + .LO(plm_fsm_xl_clw_timer_reg_count_qxu[2]) + ); + defparam plm_fsm_xl_clw_timer_reg_count_qxu_0_3_.INIT = 4'h8; + LUT2_L plm_fsm_xl_clw_timer_reg_count_qxu_0_3_ ( + .I0(plm_fsm_reg_state_23__880), + .I1(plm_fsm_xl_clw_timer_reg_count[3]), + .LO(plm_fsm_xl_clw_timer_reg_count_qxu[3]) + ); + defparam plm_fsm_xl_clw_timer_reg_count_qxu_0_4_.INIT = 4'h8; + LUT2_L plm_fsm_xl_clw_timer_reg_count_qxu_0_4_ ( + .I0(plm_fsm_reg_state_23__880), + .I1(plm_fsm_xl_clw_timer_reg_count[4]), + .LO(plm_fsm_xl_clw_timer_reg_count_qxu[4]) + ); + defparam plm_fsm_xl_clw_timer_reg_count_qxu_0_5_.INIT = 4'h8; + LUT2_L plm_fsm_xl_clw_timer_reg_count_qxu_0_5_ ( + .I0(plm_fsm_reg_state_23__880), + .I1(plm_fsm_xl_clw_timer_reg_count[5]), + .LO(plm_fsm_xl_clw_timer_reg_count_qxu[5]) + ); + defparam plm_fsm_xl_clw_timer_reg_count_qxu_0_6_.INIT = 4'h8; + LUT2_L plm_fsm_xl_clw_timer_reg_count_qxu_0_6_ ( + .I0(plm_fsm_reg_state_23__880), + .I1(plm_fsm_xl_clw_timer_reg_count[6]), + .LO(plm_fsm_xl_clw_timer_reg_count_qxu[6]) + ); + defparam plm_fsm_xl_clw_timer_reg_count_qxu_0_7_.INIT = 4'h8; + LUT2_L plm_fsm_xl_clw_timer_reg_count_qxu_0_7_ ( + .I0(plm_fsm_reg_state_23__880), + .I1(plm_fsm_xl_clw_timer_reg_count[7]), + .LO(plm_fsm_xl_clw_timer_reg_count_qxu[7]) + ); + defparam plm_fsm_xl_clw_timer_reg_count_qxu_0_8_.INIT = 4'h8; + LUT2_L plm_fsm_xl_clw_timer_reg_count_qxu_0_8_ ( + .I0(plm_fsm_reg_state_23__880), + .I1(plm_fsm_xl_clw_timer_reg_count[8]), + .LO(plm_fsm_xl_clw_timer_reg_count_qxu[8]) + ); + defparam plm_fsm_xl_clw_timer_reg_count_qxu_0_9_.INIT = 4'h8; + LUT2_L plm_fsm_xl_clw_timer_reg_count_qxu_0_9_ ( + .I0(plm_fsm_reg_state_23__880), + .I1(plm_fsm_xl_clw_timer_reg_count[9]), + .LO(plm_fsm_xl_clw_timer_reg_count_qxu[9]) + ); + defparam plm_fsm_xl_clw_timer_reg_count_qxu_0_10_.INIT = 4'h8; + LUT2_L plm_fsm_xl_clw_timer_reg_count_qxu_0_10_ ( + .I0(plm_fsm_reg_state_23__880), + .I1(plm_fsm_xl_clw_timer_reg_count[10]), + .LO(plm_fsm_xl_clw_timer_reg_count_qxu[10]) + ); + defparam plm_fsm_xl_clw_timer_reg_count_qxu_0_11_.INIT = 4'h8; + LUT2_L plm_fsm_xl_clw_timer_reg_count_qxu_0_11_ ( + .I0(plm_fsm_reg_state_23__880), + .I1(plm_fsm_xl_clw_timer_reg_count[11]), + .LO(plm_fsm_xl_clw_timer_reg_count_qxu[11]) + ); + defparam plm_fsm_xl_clw_timer_reg_count_qxu_0_12_.INIT = 4'h8; + LUT2_L plm_fsm_xl_clw_timer_reg_count_qxu_0_12_ ( + .I0(plm_fsm_reg_state_23__880), + .I1(plm_fsm_xl_clw_timer_reg_count[12]), + .LO(plm_fsm_xl_clw_timer_reg_count_qxu[12]) + ); + defparam plm_fsm_xl_clw_timer_reg_count_qxu_0_13_.INIT = 4'h8; + LUT2_L plm_fsm_xl_clw_timer_reg_count_qxu_0_13_ ( + .I0(plm_fsm_reg_state_23__880), + .I1(plm_fsm_xl_clw_timer_reg_count[13]), + .LO(plm_fsm_xl_clw_timer_reg_count_qxu[13]) + ); + defparam plm_fsm_xl_clw_timer_reg_count_qxu_0_14_.INIT = 4'h8; + LUT2_L plm_fsm_xl_clw_timer_reg_count_qxu_0_14_ ( + .I0(plm_fsm_reg_state_23__880), + .I1(plm_fsm_xl_clw_timer_reg_count[14]), + .LO(plm_fsm_xl_clw_timer_reg_count_qxu[14]) + ); + defparam plm_fsm_xl_clw_timer_reg_count_qxu_0_15_.INIT = 4'h8; + LUT2_L plm_fsm_xl_clw_timer_reg_count_qxu_0_15_ ( + .I0(plm_fsm_reg_state_23__880), + .I1(plm_fsm_xl_clw_timer_reg_count[15]), + .LO(plm_fsm_xl_clw_timer_reg_count_qxu[15]) + ); + defparam plm_fsm_xl_clw_timer_reg_count_qxu_0_16_.INIT = 4'h8; + LUT2_L plm_fsm_xl_clw_timer_reg_count_qxu_0_16_ ( + .I0(plm_fsm_reg_state_23__880), + .I1(plm_fsm_xl_clw_timer_reg_count[16]), + .LO(plm_fsm_xl_clw_timer_reg_count_qxu[16]) + ); + defparam plm_fsm_xl_clw_timer_reg_count_qxu_0_17_.INIT = 4'h8; + LUT2_L plm_fsm_xl_clw_timer_reg_count_qxu_0_17_ ( + .I0(plm_fsm_reg_state_23__880), + .I1(plm_fsm_xl_clw_timer_reg_count[17]), + .LO(plm_fsm_xl_clw_timer_reg_count_qxu[17]) + ); + defparam plm_fsm_xl_clw_timer_reg_count_qxu_0_18_.INIT = 4'h8; + LUT2_L plm_fsm_xl_clw_timer_reg_count_qxu_0_18_ ( + .I0(plm_fsm_reg_state_23__880), + .I1(plm_fsm_xl_clw_timer_reg_count[18]), + .LO(plm_fsm_xl_clw_timer_reg_count_qxu[18]) + ); + defparam plm_fsm_xl_clw_timer_reg_count_qxu_0_19_.INIT = 4'h8; + LUT2_L plm_fsm_xl_clw_timer_reg_count_qxu_0_19_ ( + .I0(plm_fsm_reg_state_23__880), + .I1(plm_fsm_xl_clw_timer_reg_count[19]), + .LO(plm_fsm_xl_clw_timer_reg_count_qxu[19]) + ); + defparam plm_fsm_xl_clw_timer_reg_count_qxu_0_20_.INIT = 4'h8; + LUT2_L plm_fsm_xl_clw_timer_reg_count_qxu_0_20_ ( + .I0(plm_fsm_reg_state_23__880), + .I1(plm_fsm_xl_clw_timer_reg_count[20]), + .LO(plm_fsm_xl_clw_timer_reg_count_qxu[20]) + ); + defparam plm_fsm_xl_clw_timer_reg_count_qxu_0_21_.INIT = 4'h8; + LUT2_L plm_fsm_xl_clw_timer_reg_count_qxu_0_21_ ( + .I0(plm_fsm_reg_state_23__880), + .I1(plm_fsm_xl_clw_timer_reg_count[21]), + .LO(plm_fsm_xl_clw_timer_reg_count_qxu[21]) + ); + defparam plm_fsm_xl_clw_timer_reg_count_qxu_0_22_.INIT = 4'h8; + LUT2_L plm_fsm_xl_clw_timer_reg_count_qxu_0_22_ ( + .I0(plm_fsm_reg_state_23__880), + .I1(plm_fsm_xl_clw_timer_reg_count[22]), + .LO(plm_fsm_xl_clw_timer_reg_count_qxu[22]) + ); + FDP com_llm_cmml_protocol_err_n ( + .PRE(plm_link_up_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_rx_dllp_range_err_n), + .Q(com_cmml_protocol_err_n) + ); + FDR com_llm_llm_tx_top_cmml_suspend_ok ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_cmml_suspend_ok_4_i_i_a2_1067), + .Q(com_cmml_suspend_ok), + .R(plm_link_up_i) + ); + defparam com_llm_llm_tx_top_cmml_suspend_ok_4_i_i_a2.INIT = 16'hD050; + LUT4_L com_llm_llm_tx_top_cmml_suspend_ok_4_i_i_a2 ( + .I0(com_cmml_suspend_now_n), + .I1(com_llm_llm_tx_top_reg_tx_djefe_idle), + .I2(com_llm_llm_tx_top_reg_tx_pp_idle), + .I3(com_llm_llm_tx_top_reg_tx_tkomp_idle), + .LO(com_llm_llm_tx_top_cmml_suspend_ok_4_i_i_a2_1067) + ); + VCC com_llm_llm_tx_top_llmx08_tx_tlp_komp_VCC ( + .P(com_llm_llm_tx_top_llmx08_tx_tlp_komp_VCC_1078) + ); + GND com_llm_llm_tx_top_llmx08_tx_tlp_komp_GND ( + .G(com_llm_llm_tx_top_llmx08_tx_tlp_komp_GND_1077) + ); + FDS com_llm_llm_tx_top_llmx08_tx_tlp_komp_lnk_tdst_rdy_n ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_N_68157_i_1076), + .Q(com_lnk_tdst_rdy_n), + .S(plm_link_up_i) + ); + FDSE com_llm_llm_tx_top_llmx08_tx_tlp_komp_reg_tx_tkomp_idle ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_N_17379_i_1071), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_reg_tx_tkomp_idle_5), + .Q(com_llm_llm_tx_top_reg_tx_tkomp_idle), + .S(plm_link_up_i) + ); + FDSE com_llm_llm_tx_top_llmx08_tx_tlp_komp_sof_n_pipe_0_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_0), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_N_42045_i_i_1075), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_sof_n_pipe[0]), + .S(plm_link_up_i) + ); + FDSE com_llm_llm_tx_top_llmx08_tx_tlp_komp_sof_n_pipe_1_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_0), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_sof_n_pipe[0]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_sof_n_pipe[1]), + .S(plm_link_up_i) + ); + FDSE com_llm_llm_tx_top_llmx08_tx_tlp_komp_sof_n_pipe_2_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_0), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_sof_n_pipe[1]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_sof_n_pipe[2]), + .S(plm_link_up_i) + ); + FDSE com_llm_llm_tx_top_llmx08_tx_tlp_komp_sof_n_pipe_3_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_0), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_sof_n_pipe[2]), + .Q(com_llm_llm_tx_top_tx_tlp_sof_pre_n), + .S(plm_link_up_i) + ); + FDSE com_llm_llm_tx_top_llmx08_tx_tlp_komp_sof_n_pipe_4_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_0), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_tx_tlp_sof_pre_n), + .Q(com_llm_llm_tx_top_tx_tlp_sof_n), + .S(plm_link_up_i) + ); + FDSE com_llm_llm_tx_top_llmx08_tx_tlp_komp_rem_pipe_0_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_0), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_N_69201_i_1072), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_rem_pipe_5079[0]), + .S(plm_link_up_i) + ); + FDSE com_llm_llm_tx_top_llmx08_tx_tlp_komp_rem_pipe_4_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_0), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_rem_pipe[3]), + .Q(com_llm_llm_tx_top_rem_pipe[4]), + .S(plm_link_up_i) + ); + FDSE com_llm_llm_tx_top_llmx08_tx_tlp_komp_rem_pipe_5_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_0), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_rem_pipe[4]), + .Q(com_llm_llm_tx_top_tx_tlp_vld_l_n_i), + .S(plm_link_up_i) + ); + FDSE com_llm_llm_tx_top_llmx08_tx_tlp_komp_eof_n_pipe_0_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_0), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_N_48931_i), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_eof_n_pipe_5078[0]), + .S(plm_link_up_i) + ); + FDSE com_llm_llm_tx_top_llmx08_tx_tlp_komp_eof_n_pipe_1_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_0), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_eof_n_pipe_5078[0]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_eof_n_pipe_5078[1]), + .S(plm_link_up_i) + ); + FDSE com_llm_llm_tx_top_llmx08_tx_tlp_komp_eof_n_pipe_5_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_0), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_eof_n_pipe[4]), + .Q(com_llm_llm_tx_top_tx_tlp_eof_n), + .S(plm_link_up_i) + ); + FDRSE com_llm_llm_tx_top_llmx08_tx_tlp_komp_holy_stashed_data ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_0), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_GND_1077), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_holy_stashed_data_1073), + .R(plm_link_up_i), + .S(com_llm_llm_tx_top_llmx08_tx_tlp_komp_un1_tx_pipe_full_0_a2_1069) + ); + FDSE com_llm_llm_tx_top_llmx08_tx_tlp_komp_bat_sof_n ( + .CE(com_lnk_tdst_rdy_n_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_lnk_tsof_i), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_bat_sof_n_1068), + .S(plm_link_up_i) + ); + FDSE com_llm_llm_tx_top_llmx08_tx_tlp_komp_bat_rem ( + .CE(com_lnk_tdst_rdy_n_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_lnk_trem[0]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_bat_rem_1074), + .S(plm_link_up_i) + ); + FDSE com_llm_llm_tx_top_llmx08_tx_tlp_komp_bat_eof_n ( + .CE(com_lnk_tdst_rdy_n_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_lnk_teof_i), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_bat_eof_n_1070), + .S(plm_link_up_i) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_bat_sof_n7_0_a2.INIT = 4'h4; + LUT2 com_llm_llm_tx_top_llmx08_tx_tlp_komp_bat_sof_n7_0_a2 ( + .I0(com_lnk_tdst_rdy_n), + .I1(plm_link_up_1), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_bat_sof_n7) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_crcdatawidth_0_a2_1_.INIT = 4'h8; + LUT2 com_llm_llm_tx_top_llmx08_tx_tlp_komp_crcdatawidth_0_a2_1_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_eof_n_pipe_5078[1]), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_rem_pipe_5079[0]), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_crcdatawidth[1]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_lnk_td_pre_swap_62_.INIT = 4'h8; + LUT2 com_llm_llm_tx_top_llmx08_tx_tlp_komp_lnk_td_pre_swap_62_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_d16_sw[9]), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_sof_n_pipe[0]), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_d64_sw_57_) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_lnk_td_pre_swap_0_48_.INIT = 8'hB8; + LUT3 com_llm_llm_tx_top_llmx08_tx_tlp_komp_lnk_td_pre_swap_0_48_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_d16_sw[7]), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_sof_n_pipe[0]), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tsn_pipe_0__1106), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_d64_sw_55_) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_lnk_td_pre_swap_0_49_.INIT = 8'hB8; + LUT3 com_llm_llm_tx_top_llmx08_tx_tlp_komp_lnk_td_pre_swap_0_49_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_d16_sw[6]), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_sof_n_pipe[0]), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tsn_pipe_1__1105), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_d64_sw_54_) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_lnk_td_pre_swap_0_50_.INIT = 8'hB8; + LUT3 com_llm_llm_tx_top_llmx08_tx_tlp_komp_lnk_td_pre_swap_0_50_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_d16_sw[5]), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_sof_n_pipe[0]), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tsn_pipe_2__1104), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_d64_sw_53_) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_lnk_td_pre_swap_0_51_.INIT = 8'hB8; + LUT3 com_llm_llm_tx_top_llmx08_tx_tlp_komp_lnk_td_pre_swap_0_51_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_d16_sw[4]), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_sof_n_pipe[0]), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tsn_pipe_3__1103), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_d64_sw_52_) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_lnk_td_pre_swap_0_52_.INIT = 8'hB8; + LUT3 com_llm_llm_tx_top_llmx08_tx_tlp_komp_lnk_td_pre_swap_0_52_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_d16_sw[3]), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_sof_n_pipe[0]), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tsn_pipe_4__1102), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_d64_sw_51_) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_lnk_td_pre_swap_0_53_.INIT = 8'hB8; + LUT3 com_llm_llm_tx_top_llmx08_tx_tlp_komp_lnk_td_pre_swap_0_53_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_d16_sw[2]), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_sof_n_pipe[0]), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tsn_pipe_5__1101), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_d64_sw_50_) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_lnk_td_pre_swap_0_54_.INIT = 8'hB8; + LUT3 com_llm_llm_tx_top_llmx08_tx_tlp_komp_lnk_td_pre_swap_0_54_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_d16_sw[1]), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_sof_n_pipe[0]), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tsn_pipe_6__1100), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_d64_sw_49_) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_lnk_td_pre_swap_0_55_.INIT = 8'hB8; + LUT3 com_llm_llm_tx_top_llmx08_tx_tlp_komp_lnk_td_pre_swap_0_55_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_d16_sw[0]), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_sof_n_pipe[0]), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tsn_pipe_7__1099), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_d64_sw_48_) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_lnk_td_pre_swap_0_56_.INIT = 8'hB8; + LUT3 com_llm_llm_tx_top_llmx08_tx_tlp_komp_lnk_td_pre_swap_0_56_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_d16_sw[15]), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_sof_n_pipe[0]), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tsn_pipe_8__1098), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_d64_sw_63_) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_lnk_td_pre_swap_0_57_.INIT = 8'hB8; + LUT3 com_llm_llm_tx_top_llmx08_tx_tlp_komp_lnk_td_pre_swap_0_57_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_d16_sw[14]), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_sof_n_pipe[0]), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tsn_pipe_9__1097), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_d64_sw_62_) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_lnk_td_pre_swap_0_58_.INIT = 8'hB8; + LUT3 com_llm_llm_tx_top_llmx08_tx_tlp_komp_lnk_td_pre_swap_0_58_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_d16_sw[13]), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_sof_n_pipe[0]), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tsn_pipe_10__1096), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_d64_sw_61_) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_lnk_td_pre_swap_0_59_.INIT = 8'hB8; + LUT3 com_llm_llm_tx_top_llmx08_tx_tlp_komp_lnk_td_pre_swap_0_59_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_d16_sw[12]), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_sof_n_pipe[0]), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tsn_pipe_11__1095), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_d64_sw_60_) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_d_i_a4_1_a2_40_.INIT = 4'h8; + LUT2 com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_d_i_a4_1_a2_40_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_N_41721_i), + .I1(com_llm_llm_tx_top_tx_tlp_sof_pre_n), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_N_42609) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_lnk_tdst_rdy_n_d_i_0_0_a2_0.INIT = 8'h10; + LUT3 com_llm_llm_tx_top_llmx08_tx_tlp_komp_lnk_tdst_rdy_n_d_i_0_0_a2_0 ( + .I0(com_llm_llm_tx_top_arb_state[2]), + .I1(com_llm_llm_tx_top_tx_tlp_sof_n), + .I2(com_llm_llm_tx_top_tx_tlp_vld_l_n_i), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_crcint_0_a2_i_0_o2.INIT = 16'h4744; + LUT4 com_llm_llm_tx_top_llmx08_tx_tlp_komp_crcint_0_a2_i_0_o2 ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_bat_sof_n_1068), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_holy_stashed_data_1073), + .I2(com_lnk_tdst_rdy_n), + .I3(com_lnk_tsof), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_N_42045_i) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_un1_tx_pipe_full_0_a2.INIT = 4'h2; + LUT2 com_llm_llm_tx_top_llmx08_tx_tlp_komp_un1_tx_pipe_full_0_a2 ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full), + .I1(com_lnk_tdst_rdy_n), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_un1_tx_pipe_full_0_a2_1069) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_lnk_tdst_rdy_n_d_i_0_0_0_o2.INIT = 16'hB8BB; + LUT4 com_llm_llm_tx_top_llmx08_tx_tlp_komp_lnk_tdst_rdy_n_d_i_0_0_0_o2 ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_bat_eof_n_1070), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_holy_stashed_data_1073), + .I2(com_lnk_tdst_rdy_n), + .I3(com_lnk_teof), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_N_48931_i) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_d_0_am_50_.INIT = 8'hAC; + LUT3 com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_d_0_am_50_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_266_), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tsn_pipe_46_), + .I2(com_llm_llm_tx_top_tx_tlp_sof_pre_n), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_d_0_am[50]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_d_0_bm_50_.INIT = 8'hB8; + LUT3 com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_d_0_bm_50_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_266_), + .I1(com_llm_llm_tx_top_rem_pipe[4]), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_crc[10]), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_d_0_bm[50]) + ); + MUXF5 com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_d_0_50_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_d_0_am[50]), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_d_0_bm[50]), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_d_50_), + .S(com_llm_llm_tx_top_llmx08_tx_tlp_komp_N_42608) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_d_0_am_51_.INIT = 8'hAC; + LUT3 com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_d_0_am_51_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_267_), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tsn_pipe_47_), + .I2(com_llm_llm_tx_top_tx_tlp_sof_pre_n), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_d_0_am[51]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_d_0_bm_51_.INIT = 8'hB8; + LUT3 com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_d_0_bm_51_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_267_), + .I1(com_llm_llm_tx_top_rem_pipe[4]), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_crc[11]), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_d_0_bm[51]) + ); + MUXF5 com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_d_0_51_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_d_0_am[51]), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_d_0_bm[51]), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_d_51_), + .S(com_llm_llm_tx_top_llmx08_tx_tlp_komp_N_42608) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_reg_tx_tkomp_idle_5_0_a2.INIT = 16'h8000; + LUT4 com_llm_llm_tx_top_llmx08_tx_tlp_komp_reg_tx_tkomp_idle_5_0_a2 ( + .I0(com_llm_llm_tx_top_N_41766_i), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_sof_n_pipe[0]), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_sof_n_pipe[1]), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_sof_n_pipe[2]), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_reg_tx_tkomp_idle_5) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_d_i_0_46_.INIT = 16'hEEF0; + LUT4 com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_d_i_0_46_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_N_41721_i), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_262_), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tsn_pipe_42_), + .I3(com_llm_llm_tx_top_tx_tlp_sof_pre_n), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_d_i_0[46]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_d_i_0_41_.INIT = 16'hEEF0; + LUT4 com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_d_i_0_41_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_N_41721_i), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_257_), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tsn_pipe_37_), + .I3(com_llm_llm_tx_top_tx_tlp_sof_pre_n), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_d_i_0[41]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_d_i_0_49_.INIT = 16'hEEF0; + LUT4 com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_d_i_0_49_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_N_41721_i), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_265_), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tsn_pipe_45_), + .I3(com_llm_llm_tx_top_tx_tlp_sof_pre_n), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_d_i_0[49]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_d_i_0_42_.INIT = 16'hEEF0; + LUT4 com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_d_i_0_42_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_N_41721_i), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_258_), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tsn_pipe_38_), + .I3(com_llm_llm_tx_top_tx_tlp_sof_pre_n), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_d_i_0[42]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_d_i_0_48_.INIT = 16'hEEF0; + LUT4 com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_d_i_0_48_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_N_41721_i), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_264_), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tsn_pipe_44_), + .I3(com_llm_llm_tx_top_tx_tlp_sof_pre_n), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_d_i_0[48]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_d_i_0_47_.INIT = 16'hEEF0; + LUT4 com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_d_i_0_47_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_N_41721_i), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_263_), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tsn_pipe_43_), + .I3(com_llm_llm_tx_top_tx_tlp_sof_pre_n), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_d_i_0[47]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_d_i_0_43_.INIT = 16'hEEF0; + LUT4 com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_d_i_0_43_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_N_41721_i), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_259_), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tsn_pipe_39_), + .I3(com_llm_llm_tx_top_tx_tlp_sof_pre_n), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_d_i_0[43]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_d_i_0_40_.INIT = 16'hEEF0; + LUT4 com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_d_i_0_40_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_N_41721_i), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_256_), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tsn_pipe_36_), + .I3(com_llm_llm_tx_top_tx_tlp_sof_pre_n), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_d_i_0[40]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_d_i_0_44_.INIT = 16'hEEF0; + LUT4 com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_d_i_0_44_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_N_41721_i), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_260_), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tsn_pipe_40_), + .I3(com_llm_llm_tx_top_tx_tlp_sof_pre_n), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_d_i_0[44]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_d_i_0_45_.INIT = 16'hEEF0; + LUT4 com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_d_i_0_45_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_N_41721_i), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_261_), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tsn_pipe_41_), + .I3(com_llm_llm_tx_top_tx_tlp_sof_pre_n), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_d_i_0[45]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_N_17379_i.INIT = 4'h7; + LUT2 com_llm_llm_tx_top_llmx08_tx_tlp_komp_N_17379_i ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_reg_tx_tkomp_idle_5), + .I1(com_llm_llm_tx_top_tx_tlp_eof_n), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_N_17379_i_1071) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_td_mux_i_m3_i_m3_i_m4_0_6_.INIT = 8'hB8; + LUT3_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_td_mux_i_m3_i_m3_i_m4_0_6_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_bat_td[6]), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_holy_stashed_data_1073), + .I2(com_lnk_td[6]), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_td_mux_i_m3_i_m3_i_m4_0[6]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_td_mux_i_m3_i_m3_i_m4_0_5_.INIT = 8'hB8; + LUT3_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_td_mux_i_m3_i_m3_i_m4_0_5_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_bat_td[5]), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_holy_stashed_data_1073), + .I2(com_lnk_td[5]), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_td_mux_i_m3_i_m3_i_m4_0[5]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_td_mux_i_m3_i_m3_i_m4_0_4_.INIT = 8'hB8; + LUT3_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_td_mux_i_m3_i_m3_i_m4_0_4_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_bat_td[4]), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_holy_stashed_data_1073), + .I2(com_lnk_td[4]), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_td_mux_i_m3_i_m3_i_m4_0[4]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_td_mux_i_m3_i_m3_i_m4_0_3_.INIT = 8'hB8; + LUT3_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_td_mux_i_m3_i_m3_i_m4_0_3_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_bat_td[3]), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_holy_stashed_data_1073), + .I2(com_lnk_td[3]), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_td_mux_i_m3_i_m3_i_m4_0[3]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_td_mux_i_m3_i_m3_i_m4_0_2_.INIT = 8'hB8; + LUT3_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_td_mux_i_m3_i_m3_i_m4_0_2_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_bat_td[2]), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_holy_stashed_data_1073), + .I2(com_lnk_td[2]), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_td_mux_i_m3_i_m3_i_m4_0[2]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_td_mux_i_m3_i_m3_i_m4_0_1_.INIT = 8'hB8; + LUT3_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_td_mux_i_m3_i_m3_i_m4_0_1_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_bat_td[1]), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_holy_stashed_data_1073), + .I2(com_lnk_td[1]), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_td_mux_i_m3_i_m3_i_m4_0[1]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_td_mux_i_m3_i_m3_i_m4_0_0_.INIT = 8'hB8; + LUT3_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_td_mux_i_m3_i_m3_i_m4_0_0_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_bat_td[0]), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_holy_stashed_data_1073), + .I2(com_lnk_td[0]), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_td_mux_i_m3_i_m3_i_m4_0[0]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_td_mux_i_m3_i_m3_i_m4_0_21_.INIT = 8'hB8; + LUT3_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_td_mux_i_m3_i_m3_i_m4_0_21_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_bat_td[21]), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_holy_stashed_data_1073), + .I2(com_lnk_td[21]), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_td_mux_i_m3_i_m3_i_m4_0[21]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_td_mux_i_m3_i_m3_i_m4_0_20_.INIT = 8'hB8; + LUT3_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_td_mux_i_m3_i_m3_i_m4_0_20_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_bat_td[20]), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_holy_stashed_data_1073), + .I2(com_lnk_td[20]), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_td_mux_i_m3_i_m3_i_m4_0[20]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_td_mux_i_m3_i_m3_i_m4_0_19_.INIT = 8'hB8; + LUT3_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_td_mux_i_m3_i_m3_i_m4_0_19_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_bat_td[19]), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_holy_stashed_data_1073), + .I2(com_lnk_td[19]), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_td_mux_i_m3_i_m3_i_m4_0[19]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_td_mux_i_m3_i_m3_i_m4_0_18_.INIT = 8'hB8; + LUT3_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_td_mux_i_m3_i_m3_i_m4_0_18_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_bat_td[18]), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_holy_stashed_data_1073), + .I2(com_lnk_td[18]), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_td_mux_i_m3_i_m3_i_m4_0[18]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_td_mux_i_m3_i_m3_i_m4_0_17_.INIT = 8'hB8; + LUT3_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_td_mux_i_m3_i_m3_i_m4_0_17_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_bat_td[17]), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_holy_stashed_data_1073), + .I2(com_lnk_td[17]), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_td_mux_i_m3_i_m3_i_m4_0[17]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_td_mux_i_m3_i_m3_i_m4_0_16_.INIT = 8'hB8; + LUT3_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_td_mux_i_m3_i_m3_i_m4_0_16_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_bat_td[16]), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_holy_stashed_data_1073), + .I2(com_lnk_td[16]), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_td_mux_i_m3_i_m3_i_m4_0[16]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_td_mux_i_m3_i_m3_i_m4_0_15_.INIT = 8'hB8; + LUT3_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_td_mux_i_m3_i_m3_i_m4_0_15_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_bat_td[15]), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_holy_stashed_data_1073), + .I2(com_lnk_td[15]), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_td_mux_i_m3_i_m3_i_m4_0[15]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_td_mux_i_m3_i_m3_i_m4_0_14_.INIT = 8'hB8; + LUT3_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_td_mux_i_m3_i_m3_i_m4_0_14_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_bat_td[14]), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_holy_stashed_data_1073), + .I2(com_lnk_td[14]), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_td_mux_i_m3_i_m3_i_m4_0[14]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_td_mux_i_m3_i_m3_i_m4_0_13_.INIT = 8'hB8; + LUT3_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_td_mux_i_m3_i_m3_i_m4_0_13_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_bat_td[13]), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_holy_stashed_data_1073), + .I2(com_lnk_td[13]), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_td_mux_i_m3_i_m3_i_m4_0[13]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_td_mux_i_m3_i_m3_i_m4_0_12_.INIT = 8'hB8; + LUT3_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_td_mux_i_m3_i_m3_i_m4_0_12_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_bat_td[12]), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_holy_stashed_data_1073), + .I2(com_lnk_td[12]), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_td_mux_i_m3_i_m3_i_m4_0[12]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_td_mux_i_m3_i_m3_i_m4_0_11_.INIT = 8'hB8; + LUT3_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_td_mux_i_m3_i_m3_i_m4_0_11_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_bat_td[11]), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_holy_stashed_data_1073), + .I2(com_lnk_td[11]), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_td_mux_i_m3_i_m3_i_m4_0[11]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_td_mux_i_m3_i_m3_i_m4_0_10_.INIT = 8'hB8; + LUT3_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_td_mux_i_m3_i_m3_i_m4_0_10_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_bat_td[10]), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_holy_stashed_data_1073), + .I2(com_lnk_td[10]), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_td_mux_i_m3_i_m3_i_m4_0[10]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_td_mux_i_m3_i_m3_i_m4_0_9_.INIT = 8'hB8; + LUT3_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_td_mux_i_m3_i_m3_i_m4_0_9_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_bat_td[9]), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_holy_stashed_data_1073), + .I2(com_lnk_td[9]), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_td_mux_i_m3_i_m3_i_m4_0[9]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_td_mux_i_m3_i_m3_i_m4_0_8_.INIT = 8'hB8; + LUT3_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_td_mux_i_m3_i_m3_i_m4_0_8_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_bat_td[8]), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_holy_stashed_data_1073), + .I2(com_lnk_td[8]), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_td_mux_i_m3_i_m3_i_m4_0[8]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_td_mux_i_m3_i_m3_i_m4_0_7_.INIT = 8'hB8; + LUT3_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_td_mux_i_m3_i_m3_i_m4_0_7_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_bat_td[7]), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_holy_stashed_data_1073), + .I2(com_lnk_td[7]), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_td_mux_i_m3_i_m3_i_m4_0[7]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_td_mux_i_m3_i_m3_i_m4_0_36_.INIT = 8'hB8; + LUT3_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_td_mux_i_m3_i_m3_i_m4_0_36_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_bat_td[36]), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_holy_stashed_data_1073), + .I2(com_lnk_td[36]), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_td_mux_i_m3_i_m3_i_m4_0[36]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_td_mux_i_m3_i_m3_i_m4_0_35_.INIT = 8'hB8; + LUT3_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_td_mux_i_m3_i_m3_i_m4_0_35_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_bat_td[35]), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_holy_stashed_data_1073), + .I2(com_lnk_td[35]), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_td_mux_i_m3_i_m3_i_m4_0[35]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_td_mux_i_m3_i_m3_i_m4_0_34_.INIT = 8'hB8; + LUT3_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_td_mux_i_m3_i_m3_i_m4_0_34_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_bat_td[34]), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_holy_stashed_data_1073), + .I2(com_lnk_td[34]), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_td_mux_i_m3_i_m3_i_m4_0[34]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_td_mux_i_m3_i_m3_i_m4_0_33_.INIT = 8'hB8; + LUT3_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_td_mux_i_m3_i_m3_i_m4_0_33_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_bat_td[33]), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_holy_stashed_data_1073), + .I2(com_lnk_td[33]), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_td_mux_i_m3_i_m3_i_m4_0[33]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_td_mux_i_m3_i_m3_i_m4_0_32_.INIT = 8'hB8; + LUT3_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_td_mux_i_m3_i_m3_i_m4_0_32_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_bat_td[32]), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_holy_stashed_data_1073), + .I2(com_lnk_td[32]), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_td_mux_i_m3_i_m3_i_m4_0[32]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_td_mux_i_m3_i_m3_i_m4_0_31_.INIT = 8'hB8; + LUT3_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_td_mux_i_m3_i_m3_i_m4_0_31_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_bat_td[31]), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_holy_stashed_data_1073), + .I2(com_lnk_td[31]), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_td_mux_i_m3_i_m3_i_m4_0[31]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_td_mux_i_m3_i_m3_i_m4_0_30_.INIT = 8'hB8; + LUT3_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_td_mux_i_m3_i_m3_i_m4_0_30_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_bat_td[30]), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_holy_stashed_data_1073), + .I2(com_lnk_td[30]), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_td_mux_i_m3_i_m3_i_m4_0[30]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_td_mux_i_m3_i_m3_i_m4_0_29_.INIT = 8'hB8; + LUT3_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_td_mux_i_m3_i_m3_i_m4_0_29_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_bat_td[29]), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_holy_stashed_data_1073), + .I2(com_lnk_td[29]), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_td_mux_i_m3_i_m3_i_m4_0[29]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_td_mux_i_m3_i_m3_i_m4_0_28_.INIT = 8'hB8; + LUT3_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_td_mux_i_m3_i_m3_i_m4_0_28_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_bat_td[28]), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_holy_stashed_data_1073), + .I2(com_lnk_td[28]), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_td_mux_i_m3_i_m3_i_m4_0[28]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_td_mux_i_m3_i_m3_i_m4_0_27_.INIT = 8'hB8; + LUT3_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_td_mux_i_m3_i_m3_i_m4_0_27_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_bat_td[27]), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_holy_stashed_data_1073), + .I2(com_lnk_td[27]), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_td_mux_i_m3_i_m3_i_m4_0[27]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_td_mux_i_m3_i_m3_i_m4_0_26_.INIT = 8'hB8; + LUT3_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_td_mux_i_m3_i_m3_i_m4_0_26_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_bat_td[26]), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_holy_stashed_data_1073), + .I2(com_lnk_td[26]), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_td_mux_i_m3_i_m3_i_m4_0[26]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_td_mux_i_m3_i_m3_i_m4_0_25_.INIT = 8'hB8; + LUT3_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_td_mux_i_m3_i_m3_i_m4_0_25_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_bat_td[25]), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_holy_stashed_data_1073), + .I2(com_lnk_td[25]), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_td_mux_i_m3_i_m3_i_m4_0[25]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_td_mux_i_m3_i_m3_i_m4_0_24_.INIT = 8'hB8; + LUT3_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_td_mux_i_m3_i_m3_i_m4_0_24_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_bat_td[24]), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_holy_stashed_data_1073), + .I2(com_lnk_td[24]), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_td_mux_i_m3_i_m3_i_m4_0[24]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_td_mux_i_m3_i_m3_i_m4_0_23_.INIT = 8'hB8; + LUT3_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_td_mux_i_m3_i_m3_i_m4_0_23_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_bat_td[23]), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_holy_stashed_data_1073), + .I2(com_lnk_td[23]), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_td_mux_i_m3_i_m3_i_m4_0[23]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_td_mux_i_m3_i_m3_i_m4_0_22_.INIT = 8'hB8; + LUT3_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_td_mux_i_m3_i_m3_i_m4_0_22_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_bat_td[22]), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_holy_stashed_data_1073), + .I2(com_lnk_td[22]), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_td_mux_i_m3_i_m3_i_m4_0[22]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_td_mux_i_m3_i_m3_i_m4_0_51_.INIT = 8'hB8; + LUT3_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_td_mux_i_m3_i_m3_i_m4_0_51_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_bat_td[51]), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_holy_stashed_data_1073), + .I2(com_lnk_td[51]), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_td_mux_i_m3_i_m3_i_m4_0[51]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_td_mux_i_m3_i_m3_i_m4_0_50_.INIT = 8'hB8; + LUT3_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_td_mux_i_m3_i_m3_i_m4_0_50_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_bat_td[50]), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_holy_stashed_data_1073), + .I2(com_lnk_td[50]), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_td_mux_i_m3_i_m3_i_m4_0[50]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_td_mux_i_m3_i_m3_i_m4_0_49_.INIT = 8'hB8; + LUT3_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_td_mux_i_m3_i_m3_i_m4_0_49_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_bat_td[49]), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_holy_stashed_data_1073), + .I2(com_lnk_td[49]), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_td_mux_i_m3_i_m3_i_m4_0[49]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_td_mux_i_m3_i_m3_i_m4_0_48_.INIT = 8'hB8; + LUT3_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_td_mux_i_m3_i_m3_i_m4_0_48_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_bat_td[48]), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_holy_stashed_data_1073), + .I2(com_lnk_td[48]), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_td_mux_i_m3_i_m3_i_m4_0[48]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_td_mux_i_m3_i_m3_i_m4_0_47_.INIT = 8'hB8; + LUT3_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_td_mux_i_m3_i_m3_i_m4_0_47_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_bat_td[47]), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_holy_stashed_data_1073), + .I2(com_lnk_td[47]), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_td_mux_i_m3_i_m3_i_m4_0[47]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_td_mux_i_m3_i_m3_i_m4_0_46_.INIT = 8'hB8; + LUT3_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_td_mux_i_m3_i_m3_i_m4_0_46_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_bat_td[46]), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_holy_stashed_data_1073), + .I2(com_lnk_td[46]), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_td_mux_i_m3_i_m3_i_m4_0[46]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_td_mux_i_m3_i_m3_i_m4_0_45_.INIT = 8'hB8; + LUT3_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_td_mux_i_m3_i_m3_i_m4_0_45_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_bat_td[45]), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_holy_stashed_data_1073), + .I2(com_lnk_td[45]), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_td_mux_i_m3_i_m3_i_m4_0[45]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_td_mux_i_m3_i_m3_i_m4_0_44_.INIT = 8'hB8; + LUT3_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_td_mux_i_m3_i_m3_i_m4_0_44_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_bat_td[44]), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_holy_stashed_data_1073), + .I2(com_lnk_td[44]), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_td_mux_i_m3_i_m3_i_m4_0[44]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_td_mux_i_m3_i_m3_i_m4_0_43_.INIT = 8'hB8; + LUT3_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_td_mux_i_m3_i_m3_i_m4_0_43_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_bat_td[43]), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_holy_stashed_data_1073), + .I2(com_lnk_td[43]), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_td_mux_i_m3_i_m3_i_m4_0[43]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_td_mux_i_m3_i_m3_i_m4_0_42_.INIT = 8'hB8; + LUT3_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_td_mux_i_m3_i_m3_i_m4_0_42_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_bat_td[42]), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_holy_stashed_data_1073), + .I2(com_lnk_td[42]), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_td_mux_i_m3_i_m3_i_m4_0[42]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_td_mux_i_m3_i_m3_i_m4_0_41_.INIT = 8'hB8; + LUT3_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_td_mux_i_m3_i_m3_i_m4_0_41_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_bat_td[41]), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_holy_stashed_data_1073), + .I2(com_lnk_td[41]), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_td_mux_i_m3_i_m3_i_m4_0[41]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_td_mux_i_m3_i_m3_i_m4_0_40_.INIT = 8'hB8; + LUT3_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_td_mux_i_m3_i_m3_i_m4_0_40_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_bat_td[40]), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_holy_stashed_data_1073), + .I2(com_lnk_td[40]), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_td_mux_i_m3_i_m3_i_m4_0[40]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_td_mux_i_m3_i_m3_i_m4_0_39_.INIT = 8'hB8; + LUT3_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_td_mux_i_m3_i_m3_i_m4_0_39_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_bat_td[39]), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_holy_stashed_data_1073), + .I2(com_lnk_td[39]), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_td_mux_i_m3_i_m3_i_m4_0[39]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_td_mux_i_m3_i_m3_i_m4_0_38_.INIT = 8'hB8; + LUT3_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_td_mux_i_m3_i_m3_i_m4_0_38_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_bat_td[38]), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_holy_stashed_data_1073), + .I2(com_lnk_td[38]), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_td_mux_i_m3_i_m3_i_m4_0[38]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_td_mux_i_m3_i_m3_i_m4_0_37_.INIT = 8'hB8; + LUT3_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_td_mux_i_m3_i_m3_i_m4_0_37_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_bat_td[37]), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_holy_stashed_data_1073), + .I2(com_lnk_td[37]), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_td_mux_i_m3_i_m3_i_m4_0[37]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_td_mux_i_m3_i_m3_i_m4_0_63_.INIT = 8'hB8; + LUT3_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_td_mux_i_m3_i_m3_i_m4_0_63_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_bat_td[63]), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_holy_stashed_data_1073), + .I2(com_lnk_td[63]), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_td_mux_i_m3_i_m3_i_m4_0[63]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_td_mux_i_m3_i_m3_i_m4_0_62_.INIT = 8'hB8; + LUT3_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_td_mux_i_m3_i_m3_i_m4_0_62_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_bat_td[62]), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_holy_stashed_data_1073), + .I2(com_lnk_td[62]), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_td_mux_i_m3_i_m3_i_m4_0[62]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_td_mux_i_m3_i_m3_i_m4_0_61_.INIT = 8'hB8; + LUT3_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_td_mux_i_m3_i_m3_i_m4_0_61_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_bat_td[61]), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_holy_stashed_data_1073), + .I2(com_lnk_td[61]), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_td_mux_i_m3_i_m3_i_m4_0[61]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_td_mux_i_m3_i_m3_i_m4_0_60_.INIT = 8'hB8; + LUT3_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_td_mux_i_m3_i_m3_i_m4_0_60_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_bat_td[60]), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_holy_stashed_data_1073), + .I2(com_lnk_td[60]), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_td_mux_i_m3_i_m3_i_m4_0[60]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_td_mux_i_m3_i_m3_i_m4_0_59_.INIT = 8'hB8; + LUT3_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_td_mux_i_m3_i_m3_i_m4_0_59_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_bat_td[59]), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_holy_stashed_data_1073), + .I2(com_lnk_td[59]), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_td_mux_i_m3_i_m3_i_m4_0[59]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_td_mux_i_m3_i_m3_i_m4_0_58_.INIT = 8'hB8; + LUT3_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_td_mux_i_m3_i_m3_i_m4_0_58_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_bat_td[58]), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_holy_stashed_data_1073), + .I2(com_lnk_td[58]), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_td_mux_i_m3_i_m3_i_m4_0[58]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_td_mux_i_m3_i_m3_i_m4_0_57_.INIT = 8'hB8; + LUT3_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_td_mux_i_m3_i_m3_i_m4_0_57_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_bat_td[57]), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_holy_stashed_data_1073), + .I2(com_lnk_td[57]), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_td_mux_i_m3_i_m3_i_m4_0[57]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_td_mux_i_m3_i_m3_i_m4_0_56_.INIT = 8'hB8; + LUT3_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_td_mux_i_m3_i_m3_i_m4_0_56_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_bat_td[56]), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_holy_stashed_data_1073), + .I2(com_lnk_td[56]), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_td_mux_i_m3_i_m3_i_m4_0[56]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_td_mux_i_m3_i_m3_i_m4_0_55_.INIT = 8'hB8; + LUT3_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_td_mux_i_m3_i_m3_i_m4_0_55_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_bat_td[55]), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_holy_stashed_data_1073), + .I2(com_lnk_td[55]), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_td_mux_i_m3_i_m3_i_m4_0[55]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_td_mux_i_m3_i_m3_i_m4_0_54_.INIT = 8'hB8; + LUT3_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_td_mux_i_m3_i_m3_i_m4_0_54_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_bat_td[54]), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_holy_stashed_data_1073), + .I2(com_lnk_td[54]), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_td_mux_i_m3_i_m3_i_m4_0[54]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_td_mux_i_m3_i_m3_i_m4_0_53_.INIT = 8'hB8; + LUT3_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_td_mux_i_m3_i_m3_i_m4_0_53_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_bat_td[53]), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_holy_stashed_data_1073), + .I2(com_lnk_td[53]), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_td_mux_i_m3_i_m3_i_m4_0[53]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_td_mux_i_m3_i_m3_i_m4_0_52_.INIT = 8'hB8; + LUT3_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_td_mux_i_m3_i_m3_i_m4_0_52_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_bat_td[52]), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_holy_stashed_data_1073), + .I2(com_lnk_td[52]), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_td_mux_i_m3_i_m3_i_m4_0[52]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_crcint_0_a2_i_0.INIT = 4'h2; + LUT2_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_crcint_0_a2_i_0 ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_N_42045_i), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_N_30689_i) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_N_69201_i.INIT = 16'hBBB8; + LUT4_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_N_69201_i ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_bat_rem_1074), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_holy_stashed_data_1073), + .I2(com_lnk_tdst_rdy_n), + .I3(com_lnk_trem[0]), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_N_69201_i_1072) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_N_42045_i_i.INIT = 4'h1; + LUT1_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_N_42045_i_i ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_N_42045_i), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_N_42045_i_i_1075) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_N_68157_i.INIT = 16'hFF57; + LUT4_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_N_68157_i ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_N_48931_i), + .I1(com_link_status[2]), + .I2(com_llm_link_status_3_), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_N_68157_i_1076) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_d_i_63_.INIT = 16'hE400; + LUT4_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_d_i_63_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_N_41721_i), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_279_), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_crc[23]), + .I3(com_llm_llm_tx_top_tx_tlp_sof_pre_n), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_N_40550_i) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_d_i_62_.INIT = 16'hE400; + LUT4_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_d_i_62_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_N_41721_i), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_278_), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_crc[22]), + .I3(com_llm_llm_tx_top_tx_tlp_sof_pre_n), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_N_40548_i) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_d_i_0_61_.INIT = 16'hE400; + LUT4_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_d_i_0_61_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_N_41721_i), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_277_), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_crc[21]), + .I3(com_llm_llm_tx_top_tx_tlp_sof_pre_n), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_N_21250_i) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_d_i_0_60_.INIT = 16'hE400; + LUT4_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_d_i_0_60_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_N_41721_i), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_276_), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_crc[20]), + .I3(com_llm_llm_tx_top_tx_tlp_sof_pre_n), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_N_21248_i) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_d_i_0_59_.INIT = 16'hE400; + LUT4_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_d_i_0_59_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_N_41721_i), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_275_), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_crc[19]), + .I3(com_llm_llm_tx_top_tx_tlp_sof_pre_n), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_N_21246_i) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_d_i_0_58_.INIT = 16'hE400; + LUT4_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_d_i_0_58_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_N_41721_i), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_274_), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_crc[18]), + .I3(com_llm_llm_tx_top_tx_tlp_sof_pre_n), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_N_21244_i) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_d_i_0_57_.INIT = 16'hE400; + LUT4_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_d_i_0_57_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_N_41721_i), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_273_), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_crc[17]), + .I3(com_llm_llm_tx_top_tx_tlp_sof_pre_n), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_N_21242_i) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_d_i_0_56_.INIT = 16'hE400; + LUT4_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_d_i_0_56_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_N_41721_i), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_272_), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_crc[16]), + .I3(com_llm_llm_tx_top_tx_tlp_sof_pre_n), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_N_21240_i) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_d_i_0_55_.INIT = 16'hE400; + LUT4_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_d_i_0_55_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_N_41721_i), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_271_), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_crc[15]), + .I3(com_llm_llm_tx_top_tx_tlp_sof_pre_n), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_N_21238_i) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_d_i_0_54_.INIT = 16'hE400; + LUT4_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_d_i_0_54_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_N_41721_i), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_270_), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_crc[14]), + .I3(com_llm_llm_tx_top_tx_tlp_sof_pre_n), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_N_21236_i) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_d_i_0_53_.INIT = 16'hE400; + LUT4_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_d_i_0_53_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_N_41721_i), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_269_), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_crc[13]), + .I3(com_llm_llm_tx_top_tx_tlp_sof_pre_n), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_N_21234_i) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_d_i_0_52_.INIT = 16'hE400; + LUT4_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_d_i_0_52_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_N_41721_i), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_268_), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_crc[12]), + .I3(com_llm_llm_tx_top_tx_tlp_sof_pre_n), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_N_21232_i) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_d_i_49_.INIT = 8'hD0; + LUT3_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_d_i_49_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_N_42609), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_crc[9]), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_d_i_0[49]), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_N_21230_i) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_d_i_48_.INIT = 8'hD0; + LUT3_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_d_i_48_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_N_42609), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_crc[8]), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_d_i_0[48]), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_N_21228_i) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_d_i_47_.INIT = 8'hD0; + LUT3_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_d_i_47_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_N_42609), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_crc[7]), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_d_i_0[47]), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_N_21226_i) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_d_i_46_.INIT = 8'hD0; + LUT3_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_d_i_46_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_N_42609), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_crc[6]), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_d_i_0[46]), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_N_21224_i) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_d_i_45_.INIT = 8'hD0; + LUT3_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_d_i_45_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_N_42609), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_crc[5]), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_d_i_0[45]), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_N_21222_i) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_d_i_44_.INIT = 8'hD0; + LUT3_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_d_i_44_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_N_42609), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_crc[4]), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_d_i_0[44]), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_N_21220_i) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_d_i_43_.INIT = 8'hD0; + LUT3_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_d_i_43_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_N_42609), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_crc[3]), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_d_i_0[43]), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_N_21218_i) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_d_i_42_.INIT = 8'hD0; + LUT3_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_d_i_42_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_N_42609), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_crc[2]), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_d_i_0[42]), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_N_21216_i) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_d_i_41_.INIT = 8'hD0; + LUT3_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_d_i_41_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_N_42609), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_crc[1]), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_d_i_0[41]), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_N_21214_i) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_d_i_40_.INIT = 8'hD0; + LUT3_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_d_i_40_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_N_42609), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_crc[0]), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_d_i_0[40]), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_N_21212_i) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_d_0_39_.INIT = 16'h44E4; + LUT4_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_d_0_39_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_N_42608), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_255_), + .I2(com_llm_llm_tx_top_rem_pipe[4]), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_sw_early_crc[31]), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_d_39_) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_d_0_38_.INIT = 16'h44E4; + LUT4_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_d_0_38_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_N_42608), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_254_), + .I2(com_llm_llm_tx_top_rem_pipe[4]), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_sw_early_crc[30]), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_d_38_) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_d_0_37_.INIT = 16'h44E4; + LUT4_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_d_0_37_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_N_42608), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_253_), + .I2(com_llm_llm_tx_top_rem_pipe[4]), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_sw_early_crc[29]), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_d_37_) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_d_0_36_.INIT = 16'h44E4; + LUT4_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_d_0_36_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_N_42608), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_252_), + .I2(com_llm_llm_tx_top_rem_pipe[4]), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_sw_early_crc[28]), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_d_36_) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_d_0_35_.INIT = 16'h44E4; + LUT4_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_d_0_35_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_N_42608), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_251_), + .I2(com_llm_llm_tx_top_rem_pipe[4]), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_sw_early_crc[27]), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_d_35_) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_d_0_34_.INIT = 16'h44E4; + LUT4_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_d_0_34_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_N_42608), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_250_), + .I2(com_llm_llm_tx_top_rem_pipe[4]), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_sw_early_crc[26]), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_d_34_) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_d_0_33_.INIT = 16'h44E4; + LUT4_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_d_0_33_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_N_42608), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_249_), + .I2(com_llm_llm_tx_top_rem_pipe[4]), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_sw_early_crc[25]), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_d_33_) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_d_0_32_.INIT = 16'h44E4; + LUT4_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_d_0_32_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_N_42608), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_248_), + .I2(com_llm_llm_tx_top_rem_pipe[4]), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_sw_early_crc[24]), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_d_32_) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_d_0_31_.INIT = 16'h44E4; + LUT4_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_d_0_31_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_N_42608), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_247_), + .I2(com_llm_llm_tx_top_rem_pipe[4]), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_sw_early_crc[23]), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_d_31_) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_d_0_30_.INIT = 16'h44E4; + LUT4_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_d_0_30_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_N_42608), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_246_), + .I2(com_llm_llm_tx_top_rem_pipe[4]), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_sw_early_crc[22]), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_d_30_) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_d_0_29_.INIT = 16'h44E4; + LUT4_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_d_0_29_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_N_42608), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_245_), + .I2(com_llm_llm_tx_top_rem_pipe[4]), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_sw_early_crc[21]), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_d_29_) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_d_0_28_.INIT = 16'h44E4; + LUT4_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_d_0_28_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_N_42608), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_244_), + .I2(com_llm_llm_tx_top_rem_pipe[4]), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_sw_early_crc[20]), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_d_28_) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_d_0_27_.INIT = 16'h44E4; + LUT4_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_d_0_27_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_N_42608), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_243_), + .I2(com_llm_llm_tx_top_rem_pipe[4]), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_sw_early_crc[19]), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_d_27_) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_d_0_26_.INIT = 16'h44E4; + LUT4_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_d_0_26_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_N_42608), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_242_), + .I2(com_llm_llm_tx_top_rem_pipe[4]), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_sw_early_crc[18]), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_d_26_) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_d_0_25_.INIT = 16'h44E4; + LUT4_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_d_0_25_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_N_42608), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_241_), + .I2(com_llm_llm_tx_top_rem_pipe[4]), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_sw_early_crc[17]), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_d_25_) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_d_0_24_.INIT = 16'h44E4; + LUT4_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_d_0_24_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_N_42608), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_240_), + .I2(com_llm_llm_tx_top_rem_pipe[4]), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_sw_early_crc[16]), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_d_24_) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_d_0_23_.INIT = 16'h44E4; + LUT4_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_d_0_23_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_N_42608), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_239_), + .I2(com_llm_llm_tx_top_rem_pipe[4]), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_sw_early_crc[15]), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_d_23_) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_d_0_22_.INIT = 16'h44E4; + LUT4_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_d_0_22_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_N_42608), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_238_), + .I2(com_llm_llm_tx_top_rem_pipe[4]), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_sw_early_crc[14]), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_d_22_) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_d_0_21_.INIT = 16'h44E4; + LUT4_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_d_0_21_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_N_42608), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_237_), + .I2(com_llm_llm_tx_top_rem_pipe[4]), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_sw_early_crc[13]), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_d_21_) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_d_0_20_.INIT = 16'h44E4; + LUT4_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_d_0_20_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_N_42608), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_236_), + .I2(com_llm_llm_tx_top_rem_pipe[4]), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_sw_early_crc[12]), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_d_20_) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_d_0_19_.INIT = 16'h44E4; + LUT4_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_d_0_19_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_N_42608), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_235_), + .I2(com_llm_llm_tx_top_rem_pipe[4]), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_sw_early_crc[11]), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_d_19_) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_d_0_18_.INIT = 16'h44E4; + LUT4_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_d_0_18_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_N_42608), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_234_), + .I2(com_llm_llm_tx_top_rem_pipe[4]), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_sw_early_crc[10]), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_d_18_) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_d_0_17_.INIT = 16'h44E4; + LUT4_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_d_0_17_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_N_42608), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_233_), + .I2(com_llm_llm_tx_top_rem_pipe[4]), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_sw_early_crc[9]), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_d_17_) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_d_0_16_.INIT = 16'h44E4; + LUT4_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_d_0_16_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_N_42608), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_232_), + .I2(com_llm_llm_tx_top_rem_pipe[4]), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_sw_early_crc[8]), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_d_16_) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_d_0_15_.INIT = 16'h44E4; + LUT4_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_d_0_15_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_N_42608), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_231_), + .I2(com_llm_llm_tx_top_rem_pipe[4]), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_sw_early_crc[7]), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_d_15_) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_d_0_14_.INIT = 16'h44E4; + LUT4_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_d_0_14_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_N_42608), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_230_), + .I2(com_llm_llm_tx_top_rem_pipe[4]), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_sw_early_crc[6]), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_d_14_) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_d_0_13_.INIT = 16'h44E4; + LUT4_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_d_0_13_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_N_42608), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_229_), + .I2(com_llm_llm_tx_top_rem_pipe[4]), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_sw_early_crc[5]), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_d_13_) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_d_0_12_.INIT = 16'h44E4; + LUT4_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_d_0_12_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_N_42608), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_228_), + .I2(com_llm_llm_tx_top_rem_pipe[4]), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_sw_early_crc[4]), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_d_12_) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_d_0_11_.INIT = 16'h44E4; + LUT4_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_d_0_11_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_N_42608), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_227_), + .I2(com_llm_llm_tx_top_rem_pipe[4]), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_sw_early_crc[3]), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_d_11_) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_d_0_10_.INIT = 16'h44E4; + LUT4_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_d_0_10_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_N_42608), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_226_), + .I2(com_llm_llm_tx_top_rem_pipe[4]), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_sw_early_crc[2]), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_d_10_) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_d_0_9_.INIT = 16'h44E4; + LUT4_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_d_0_9_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_N_42608), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_225_), + .I2(com_llm_llm_tx_top_rem_pipe[4]), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_sw_early_crc[1]), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_d_9_) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_d_0_8_.INIT = 16'h44E4; + LUT4_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_d_0_8_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_N_42608), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_224_), + .I2(com_llm_llm_tx_top_rem_pipe[4]), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_sw_early_crc[0]), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_d_8_) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_d_7_.INIT = 16'h1054; + LUT4_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_d_7_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_N_42608), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_N_51674), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_223_), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_sw_early_crc[31]), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_d_7__1107) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_d_6_.INIT = 16'h1054; + LUT4_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_d_6_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_N_42608), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_N_51674), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_222_), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_sw_early_crc[30]), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_d_6__1108) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_d_5_.INIT = 16'h1054; + LUT4_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_d_5_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_N_42608), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_N_51674), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_221_), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_sw_early_crc[29]), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_d_5__1109) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_d_4_.INIT = 16'h1054; + LUT4_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_d_4_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_N_42608), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_N_51674), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_220_), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_sw_early_crc[28]), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_d_4__1110) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_d_3_.INIT = 16'h1054; + LUT4_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_d_3_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_N_42608), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_N_51674), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_219_), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_sw_early_crc[27]), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_d_3__1111) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_d_2_.INIT = 16'h1054; + LUT4_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_d_2_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_N_42608), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_N_51674), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_218_), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_sw_early_crc[26]), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_d_2__1112) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_d_1_.INIT = 16'h1054; + LUT4_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_d_1_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_N_42608), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_N_51674), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_217_), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_sw_early_crc[25]), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_d_1__1113) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_d_0_.INIT = 16'h1054; + LUT4_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_d_0_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_N_42608), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_N_51674), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_216_), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_sw_early_crc[24]), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_d_0__1114) + ); + SRL16E com_llm_llm_tx_top_llmx08_tx_tlp_komp_rem_pipe_I_1 ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_i_38), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_rem_pipe_5079[0]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_rem_pipe_tmp_d_array_0[0]), + .CLK(NlwRenamedSig_OI_trn_clk), + .A0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_VCC_1078), + .A1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_GND_1077), + .A2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_GND_1077), + .A3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_GND_1077) + ); + SRL16E com_llm_llm_tx_top_llmx08_tx_tlp_komp_eof_n_pipe_I_1 ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_i_38), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_eof_n_pipe_5078[1]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_eof_n_pipe_N_6), + .CLK(NlwRenamedSig_OI_trn_clk), + .A0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_VCC_1078), + .A1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_GND_1077), + .A2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_GND_1077), + .A3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_GND_1077) + ); + SRL16E com_llm_llm_tx_top_llmx08_tx_tlp_komp_tsn_pipe_I_1 ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_i_38), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tsn_pipe_0__1106), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tsn_pipe_N_6), + .CLK(NlwRenamedSig_OI_trn_clk), + .A0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_VCC_1078), + .A1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_GND_1077), + .A2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_GND_1077), + .A3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_GND_1077) + ); + SRL16E com_llm_llm_tx_top_llmx08_tx_tlp_komp_tsn_pipe_0_I_1 ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_i_38), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tsn_pipe_1__1105), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tsn_pipe_0_N_6), + .CLK(NlwRenamedSig_OI_trn_clk), + .A0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_VCC_1078), + .A1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_GND_1077), + .A2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_GND_1077), + .A3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_GND_1077) + ); + SRL16E com_llm_llm_tx_top_llmx08_tx_tlp_komp_tsn_pipe_1_I_1 ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_i_38), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tsn_pipe_2__1104), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tsn_pipe_1_N_6), + .CLK(NlwRenamedSig_OI_trn_clk), + .A0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_VCC_1078), + .A1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_GND_1077), + .A2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_GND_1077), + .A3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_GND_1077) + ); + SRL16E com_llm_llm_tx_top_llmx08_tx_tlp_komp_tsn_pipe_2_I_1 ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_i_38), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tsn_pipe_3__1103), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tsn_pipe_2_N_6), + .CLK(NlwRenamedSig_OI_trn_clk), + .A0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_VCC_1078), + .A1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_GND_1077), + .A2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_GND_1077), + .A3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_GND_1077) + ); + SRL16E com_llm_llm_tx_top_llmx08_tx_tlp_komp_tsn_pipe_3_I_1 ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_i_38), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tsn_pipe_4__1102), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tsn_pipe_3_N_6), + .CLK(NlwRenamedSig_OI_trn_clk), + .A0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_VCC_1078), + .A1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_GND_1077), + .A2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_GND_1077), + .A3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_GND_1077) + ); + SRL16E com_llm_llm_tx_top_llmx08_tx_tlp_komp_tsn_pipe_4_I_1 ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_i_38), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tsn_pipe_5__1101), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tsn_pipe_4_N_6), + .CLK(NlwRenamedSig_OI_trn_clk), + .A0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_VCC_1078), + .A1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_GND_1077), + .A2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_GND_1077), + .A3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_GND_1077) + ); + SRL16E com_llm_llm_tx_top_llmx08_tx_tlp_komp_tsn_pipe_5_I_1 ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_i_38), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tsn_pipe_6__1100), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tsn_pipe_5_N_6), + .CLK(NlwRenamedSig_OI_trn_clk), + .A0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_VCC_1078), + .A1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_GND_1077), + .A2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_GND_1077), + .A3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_GND_1077) + ); + SRL16E com_llm_llm_tx_top_llmx08_tx_tlp_komp_tsn_pipe_6_I_1 ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_i_38), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tsn_pipe_7__1099), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tsn_pipe_6_N_6), + .CLK(NlwRenamedSig_OI_trn_clk), + .A0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_VCC_1078), + .A1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_GND_1077), + .A2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_GND_1077), + .A3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_GND_1077) + ); + SRL16E com_llm_llm_tx_top_llmx08_tx_tlp_komp_tsn_pipe_7_I_1 ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_i_38), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tsn_pipe_8__1098), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tsn_pipe_7_N_6), + .CLK(NlwRenamedSig_OI_trn_clk), + .A0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_VCC_1078), + .A1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_GND_1077), + .A2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_GND_1077), + .A3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_GND_1077) + ); + SRL16E com_llm_llm_tx_top_llmx08_tx_tlp_komp_tsn_pipe_8_I_1 ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_i_38), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tsn_pipe_9__1097), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tsn_pipe_8_N_6), + .CLK(NlwRenamedSig_OI_trn_clk), + .A0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_VCC_1078), + .A1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_GND_1077), + .A2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_GND_1077), + .A3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_GND_1077) + ); + SRL16E com_llm_llm_tx_top_llmx08_tx_tlp_komp_tsn_pipe_9_I_1 ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_i_38), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tsn_pipe_10__1096), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tsn_pipe_9_N_6), + .CLK(NlwRenamedSig_OI_trn_clk), + .A0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_VCC_1078), + .A1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_GND_1077), + .A2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_GND_1077), + .A3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_GND_1077) + ); + SRL16E com_llm_llm_tx_top_llmx08_tx_tlp_komp_tsn_pipe_10_I_1 ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_i_38), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tsn_pipe_11__1095), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tsn_pipe_10_N_6), + .CLK(NlwRenamedSig_OI_trn_clk), + .A0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_VCC_1078), + .A1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_GND_1077), + .A2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_GND_1077), + .A3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_GND_1077) + ); + SRL16E com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_I_1 ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_i_38), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_d32_sw[2]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_tmp_d_array_0[0]), + .CLK(NlwRenamedSig_OI_trn_clk), + .A0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_GND_1077), + .A1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_VCC_1078), + .A2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_GND_1077), + .A3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_GND_1077) + ); + SRL16E com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_0_I_1 ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_i_38), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_d32_sw[1]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_0_N_6), + .CLK(NlwRenamedSig_OI_trn_clk), + .A0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_GND_1077), + .A1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_VCC_1078), + .A2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_GND_1077), + .A3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_GND_1077) + ); + SRL16E com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_1_I_1 ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_i_38), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_d32_sw[0]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_1_N_6), + .CLK(NlwRenamedSig_OI_trn_clk), + .A0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_GND_1077), + .A1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_VCC_1078), + .A2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_GND_1077), + .A3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_GND_1077) + ); + SRL16E com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_2_I_1 ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_i_38), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_d16_sw[1]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_2_N_6), + .CLK(NlwRenamedSig_OI_trn_clk), + .A0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_VCC_1078), + .A1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_GND_1077), + .A2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_GND_1077), + .A3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_GND_1077) + ); + SRL16E com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_3_I_1 ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_i_38), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_d16_sw[0]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_3_N_6), + .CLK(NlwRenamedSig_OI_trn_clk), + .A0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_VCC_1078), + .A1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_GND_1077), + .A2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_GND_1077), + .A3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_GND_1077) + ); + SRL16E com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_4_I_1 ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_i_38), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_d16_sw[15]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_4_N_6), + .CLK(NlwRenamedSig_OI_trn_clk), + .A0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_VCC_1078), + .A1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_GND_1077), + .A2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_GND_1077), + .A3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_GND_1077) + ); + SRL16E com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_5_I_1 ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_i_38), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_d16_sw[14]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_5_N_6), + .CLK(NlwRenamedSig_OI_trn_clk), + .A0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_VCC_1078), + .A1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_GND_1077), + .A2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_GND_1077), + .A3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_GND_1077) + ); + SRL16E com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_6_I_1 ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_i_38), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_d16_sw[13]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_6_N_6), + .CLK(NlwRenamedSig_OI_trn_clk), + .A0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_VCC_1078), + .A1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_GND_1077), + .A2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_GND_1077), + .A3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_GND_1077) + ); + SRL16E com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_7_I_1 ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_i_38), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_d16_sw[12]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_7_N_6), + .CLK(NlwRenamedSig_OI_trn_clk), + .A0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_VCC_1078), + .A1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_GND_1077), + .A2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_GND_1077), + .A3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_GND_1077) + ); + SRL16E com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_8_I_1 ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_i_38), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_d16_sw[11]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_8_N_6), + .CLK(NlwRenamedSig_OI_trn_clk), + .A0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_VCC_1078), + .A1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_GND_1077), + .A2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_GND_1077), + .A3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_GND_1077) + ); + SRL16E com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_9_I_1 ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_i_38), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_d16_sw[10]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_9_N_6), + .CLK(NlwRenamedSig_OI_trn_clk), + .A0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_VCC_1078), + .A1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_GND_1077), + .A2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_GND_1077), + .A3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_GND_1077) + ); + SRL16E com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_10_I_1 ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_i_38), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_d16_sw[9]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_10_N_6), + .CLK(NlwRenamedSig_OI_trn_clk), + .A0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_VCC_1078), + .A1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_GND_1077), + .A2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_GND_1077), + .A3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_GND_1077) + ); + SRL16E com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_11_I_1 ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_i_38), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_d16_sw[8]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_11_N_6), + .CLK(NlwRenamedSig_OI_trn_clk), + .A0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_VCC_1078), + .A1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_GND_1077), + .A2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_GND_1077), + .A3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_GND_1077) + ); + SRL16E com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_12_I_1 ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_i_38), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_d32_sw[7]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_12_N_6), + .CLK(NlwRenamedSig_OI_trn_clk), + .A0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_GND_1077), + .A1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_VCC_1078), + .A2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_GND_1077), + .A3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_GND_1077) + ); + SRL16E com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_13_I_1 ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_i_38), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_d32_sw[6]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_13_N_6), + .CLK(NlwRenamedSig_OI_trn_clk), + .A0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_GND_1077), + .A1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_VCC_1078), + .A2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_GND_1077), + .A3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_GND_1077) + ); + SRL16E com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_14_I_1 ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_i_38), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_d32_sw[5]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_14_N_6), + .CLK(NlwRenamedSig_OI_trn_clk), + .A0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_GND_1077), + .A1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_VCC_1078), + .A2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_GND_1077), + .A3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_GND_1077) + ); + SRL16E com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_15_I_1 ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_i_38), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_d32_sw[4]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_15_N_6), + .CLK(NlwRenamedSig_OI_trn_clk), + .A0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_GND_1077), + .A1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_VCC_1078), + .A2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_GND_1077), + .A3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_GND_1077) + ); + SRL16E com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_16_I_1 ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_i_38), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_d32_sw[3]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_16_N_6), + .CLK(NlwRenamedSig_OI_trn_clk), + .A0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_GND_1077), + .A1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_VCC_1078), + .A2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_GND_1077), + .A3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_GND_1077) + ); + SRL16E com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_17_I_1 ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_i_38), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_d64_sw_32_), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_17_N_6), + .CLK(NlwRenamedSig_OI_trn_clk), + .A0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_VCC_1078), + .A1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_GND_1077), + .A2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_GND_1077), + .A3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_GND_1077) + ); + SRL16E com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_18_I_1 ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_i_38), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_d64_sw_47_), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_18_N_6), + .CLK(NlwRenamedSig_OI_trn_clk), + .A0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_VCC_1078), + .A1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_GND_1077), + .A2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_GND_1077), + .A3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_GND_1077) + ); + SRL16E com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_19_I_1 ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_i_38), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_d64_sw_46_), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_19_N_6), + .CLK(NlwRenamedSig_OI_trn_clk), + .A0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_VCC_1078), + .A1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_GND_1077), + .A2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_GND_1077), + .A3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_GND_1077) + ); + SRL16E com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_20_I_1 ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_i_38), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_d64_sw_45_), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_20_N_6), + .CLK(NlwRenamedSig_OI_trn_clk), + .A0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_VCC_1078), + .A1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_GND_1077), + .A2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_GND_1077), + .A3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_GND_1077) + ); + SRL16E com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_21_I_1 ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_i_38), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_d64_sw_44_), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_21_N_6), + .CLK(NlwRenamedSig_OI_trn_clk), + .A0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_VCC_1078), + .A1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_GND_1077), + .A2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_GND_1077), + .A3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_GND_1077) + ); + SRL16E com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_22_I_1 ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_i_38), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_d64_sw_43_), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_22_N_6), + .CLK(NlwRenamedSig_OI_trn_clk), + .A0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_VCC_1078), + .A1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_GND_1077), + .A2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_GND_1077), + .A3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_GND_1077) + ); + SRL16E com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_23_I_1 ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_i_38), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_d64_sw_42_), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_23_N_6), + .CLK(NlwRenamedSig_OI_trn_clk), + .A0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_VCC_1078), + .A1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_GND_1077), + .A2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_GND_1077), + .A3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_GND_1077) + ); + SRL16E com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_24_I_1 ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_i_38), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_d64_sw_41_), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_24_N_6), + .CLK(NlwRenamedSig_OI_trn_clk), + .A0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_VCC_1078), + .A1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_GND_1077), + .A2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_GND_1077), + .A3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_GND_1077) + ); + SRL16E com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_25_I_1 ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_i_38), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_d64_sw_40_), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_25_N_6), + .CLK(NlwRenamedSig_OI_trn_clk), + .A0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_VCC_1078), + .A1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_GND_1077), + .A2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_GND_1077), + .A3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_GND_1077) + ); + SRL16E com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_26_I_1 ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_i_38), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_d16_sw[7]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_26_N_6), + .CLK(NlwRenamedSig_OI_trn_clk), + .A0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_VCC_1078), + .A1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_GND_1077), + .A2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_GND_1077), + .A3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_GND_1077) + ); + SRL16E com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_27_I_1 ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_i_38), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_d16_sw[6]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_27_N_6), + .CLK(NlwRenamedSig_OI_trn_clk), + .A0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_VCC_1078), + .A1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_GND_1077), + .A2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_GND_1077), + .A3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_GND_1077) + ); + SRL16E com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_28_I_1 ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_d16_sw[5]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_28_N_6), + .CLK(NlwRenamedSig_OI_trn_clk), + .A0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_VCC_1078), + .A1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_GND_1077), + .A2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_GND_1077), + .A3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_GND_1077) + ); + SRL16E com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_29_I_1 ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_d16_sw[4]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_29_N_6), + .CLK(NlwRenamedSig_OI_trn_clk), + .A0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_VCC_1078), + .A1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_GND_1077), + .A2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_GND_1077), + .A3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_GND_1077) + ); + SRL16E com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_30_I_1 ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_d16_sw[3]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_30_N_6), + .CLK(NlwRenamedSig_OI_trn_clk), + .A0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_VCC_1078), + .A1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_GND_1077), + .A2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_GND_1077), + .A3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_GND_1077) + ); + SRL16E com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_31_I_1 ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_d16_sw[2]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_31_N_6), + .CLK(NlwRenamedSig_OI_trn_clk), + .A0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_VCC_1078), + .A1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_GND_1077), + .A2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_GND_1077), + .A3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_GND_1077) + ); + SRL16E com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_32_I_1 ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_d32_sw[31]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_32_N_6), + .CLK(NlwRenamedSig_OI_trn_clk), + .A0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_VCC_1078), + .A1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_GND_1077), + .A2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_GND_1077), + .A3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_GND_1077) + ); + SRL16E com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_33_I_1 ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_d32_sw[30]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_33_N_6), + .CLK(NlwRenamedSig_OI_trn_clk), + .A0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_VCC_1078), + .A1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_GND_1077), + .A2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_GND_1077), + .A3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_GND_1077) + ); + SRL16E com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_34_I_1 ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_d32_sw[29]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_34_N_6), + .CLK(NlwRenamedSig_OI_trn_clk), + .A0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_VCC_1078), + .A1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_GND_1077), + .A2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_GND_1077), + .A3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_GND_1077) + ); + SRL16E com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_35_I_1 ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_d32_sw[28]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_35_N_6), + .CLK(NlwRenamedSig_OI_trn_clk), + .A0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_VCC_1078), + .A1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_GND_1077), + .A2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_GND_1077), + .A3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_GND_1077) + ); + SRL16E com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_36_I_1 ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_d32_sw[27]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_36_N_6), + .CLK(NlwRenamedSig_OI_trn_clk), + .A0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_VCC_1078), + .A1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_GND_1077), + .A2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_GND_1077), + .A3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_GND_1077) + ); + SRL16E com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_37_I_1 ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_d32_sw[26]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_37_N_6), + .CLK(NlwRenamedSig_OI_trn_clk), + .A0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_VCC_1078), + .A1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_GND_1077), + .A2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_GND_1077), + .A3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_GND_1077) + ); + SRL16E com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_38_I_1 ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_d32_sw[25]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_38_N_6), + .CLK(NlwRenamedSig_OI_trn_clk), + .A0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_VCC_1078), + .A1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_GND_1077), + .A2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_GND_1077), + .A3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_GND_1077) + ); + SRL16E com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_39_I_1 ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_d32_sw[24]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_39_N_6), + .CLK(NlwRenamedSig_OI_trn_clk), + .A0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_VCC_1078), + .A1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_GND_1077), + .A2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_GND_1077), + .A3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_GND_1077) + ); + SRL16E com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_40_I_1 ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_d64_sw_39_), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_40_N_6), + .CLK(NlwRenamedSig_OI_trn_clk), + .A0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_VCC_1078), + .A1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_GND_1077), + .A2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_GND_1077), + .A3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_GND_1077) + ); + SRL16E com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_41_I_1 ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_d64_sw_38_), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_41_N_6), + .CLK(NlwRenamedSig_OI_trn_clk), + .A0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_VCC_1078), + .A1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_GND_1077), + .A2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_GND_1077), + .A3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_GND_1077) + ); + SRL16E com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_42_I_1 ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_d64_sw_37_), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_42_N_6), + .CLK(NlwRenamedSig_OI_trn_clk), + .A0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_VCC_1078), + .A1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_GND_1077), + .A2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_GND_1077), + .A3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_GND_1077) + ); + SRL16E com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_43_I_1 ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_d64_sw_36_), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_43_N_6), + .CLK(NlwRenamedSig_OI_trn_clk), + .A0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_VCC_1078), + .A1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_GND_1077), + .A2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_GND_1077), + .A3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_GND_1077) + ); + SRL16E com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_44_I_1 ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_d64_sw_35_), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_44_N_6), + .CLK(NlwRenamedSig_OI_trn_clk), + .A0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_VCC_1078), + .A1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_GND_1077), + .A2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_GND_1077), + .A3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_GND_1077) + ); + SRL16E com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_45_I_1 ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_d64_sw_34_), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_45_N_6), + .CLK(NlwRenamedSig_OI_trn_clk), + .A0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_VCC_1078), + .A1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_GND_1077), + .A2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_GND_1077), + .A3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_GND_1077) + ); + SRL16E com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_46_I_1 ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_d64_sw_33_), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_46_N_6), + .CLK(NlwRenamedSig_OI_trn_clk), + .A0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_VCC_1078), + .A1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_GND_1077), + .A2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_GND_1077), + .A3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_GND_1077) + ); + SRL16E com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_47_I_1 ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_d32_sw[14]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_47_N_6), + .CLK(NlwRenamedSig_OI_trn_clk), + .A0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_VCC_1078), + .A1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_GND_1077), + .A2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_GND_1077), + .A3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_GND_1077) + ); + SRL16E com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_48_I_1 ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_d32_sw[13]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_48_N_6), + .CLK(NlwRenamedSig_OI_trn_clk), + .A0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_VCC_1078), + .A1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_GND_1077), + .A2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_GND_1077), + .A3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_GND_1077) + ); + SRL16E com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_49_I_1 ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_d32_sw[12]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_49_N_6), + .CLK(NlwRenamedSig_OI_trn_clk), + .A0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_VCC_1078), + .A1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_GND_1077), + .A2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_GND_1077), + .A3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_GND_1077) + ); + SRL16E com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_50_I_1 ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_d32_sw[11]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_50_N_6), + .CLK(NlwRenamedSig_OI_trn_clk), + .A0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_VCC_1078), + .A1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_GND_1077), + .A2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_GND_1077), + .A3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_GND_1077) + ); + SRL16E com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_51_I_1 ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_d32_sw[10]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_51_N_6), + .CLK(NlwRenamedSig_OI_trn_clk), + .A0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_VCC_1078), + .A1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_GND_1077), + .A2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_GND_1077), + .A3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_GND_1077) + ); + SRL16E com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_52_I_1 ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_d32_sw[9]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_52_N_6), + .CLK(NlwRenamedSig_OI_trn_clk), + .A0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_VCC_1078), + .A1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_GND_1077), + .A2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_GND_1077), + .A3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_GND_1077) + ); + SRL16E com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_53_I_1 ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_d32_sw[8]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_53_N_6), + .CLK(NlwRenamedSig_OI_trn_clk), + .A0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_VCC_1078), + .A1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_GND_1077), + .A2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_GND_1077), + .A3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_GND_1077) + ); + SRL16E com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_54_I_1 ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_d32_sw[23]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_54_N_6), + .CLK(NlwRenamedSig_OI_trn_clk), + .A0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_VCC_1078), + .A1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_GND_1077), + .A2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_GND_1077), + .A3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_GND_1077) + ); + SRL16E com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_55_I_1 ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_d32_sw[22]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_55_N_6), + .CLK(NlwRenamedSig_OI_trn_clk), + .A0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_VCC_1078), + .A1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_GND_1077), + .A2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_GND_1077), + .A3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_GND_1077) + ); + SRL16E com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_56_I_1 ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_d32_sw[21]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_56_N_6), + .CLK(NlwRenamedSig_OI_trn_clk), + .A0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_VCC_1078), + .A1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_GND_1077), + .A2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_GND_1077), + .A3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_GND_1077) + ); + SRL16E com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_57_I_1 ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_d32_sw[20]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_57_N_6), + .CLK(NlwRenamedSig_OI_trn_clk), + .A0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_VCC_1078), + .A1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_GND_1077), + .A2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_GND_1077), + .A3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_GND_1077) + ); + SRL16E com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_58_I_1 ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_d32_sw[19]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_58_N_6), + .CLK(NlwRenamedSig_OI_trn_clk), + .A0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_VCC_1078), + .A1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_GND_1077), + .A2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_GND_1077), + .A3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_GND_1077) + ); + SRL16E com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_59_I_1 ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_d32_sw[18]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_59_N_6), + .CLK(NlwRenamedSig_OI_trn_clk), + .A0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_VCC_1078), + .A1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_GND_1077), + .A2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_GND_1077), + .A3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_GND_1077) + ); + SRL16E com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_60_I_1 ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_d32_sw[17]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_60_N_6), + .CLK(NlwRenamedSig_OI_trn_clk), + .A0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_VCC_1078), + .A1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_GND_1077), + .A2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_GND_1077), + .A3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_GND_1077) + ); + SRL16E com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_61_I_1 ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_d32_sw[16]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_61_N_6), + .CLK(NlwRenamedSig_OI_trn_clk), + .A0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_VCC_1078), + .A1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_GND_1077), + .A2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_GND_1077), + .A3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_GND_1077) + ); + SRL16E com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_62_I_1 ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_d32_sw[15]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_62_N_6), + .CLK(NlwRenamedSig_OI_trn_clk), + .A0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_VCC_1078), + .A1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_GND_1077), + .A2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_GND_1077), + .A3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_GND_1077) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_lnk_tdst_rdy_n_d_i_0_0_a2_0_1.INIT = 8'h10; + LUT3 com_llm_llm_tx_top_llmx08_tx_tlp_komp_lnk_tdst_rdy_n_d_i_0_0_a2_0_1 ( + .I0(com_llm_llm_tx_top_arb_state[2]), + .I1(com_llm_llm_tx_top_tx_tlp_sof_n), + .I2(com_llm_llm_tx_top_tx_tlp_vld_l_n_i), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_1) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_lnk_tdst_rdy_n_d_i_0_0_a2_0_2.INIT = 8'h10; + LUT3 com_llm_llm_tx_top_llmx08_tx_tlp_komp_lnk_tdst_rdy_n_d_i_0_0_a2_0_2 ( + .I0(com_llm_llm_tx_top_arb_state[2]), + .I1(com_llm_llm_tx_top_tx_tlp_sof_n), + .I2(com_llm_llm_tx_top_tx_tlp_vld_l_n_i), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_2) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_lnk_tdst_rdy_n_d_i_0_0_a2_0_3.INIT = 8'h10; + LUT3 com_llm_llm_tx_top_llmx08_tx_tlp_komp_lnk_tdst_rdy_n_d_i_0_0_a2_0_3 ( + .I0(com_llm_llm_tx_top_arb_state[2]), + .I1(com_llm_llm_tx_top_tx_tlp_sof_n), + .I2(com_llm_llm_tx_top_tx_tlp_vld_l_n_i), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_3) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_lnk_tdst_rdy_n_d_i_0_0_a2_0_4.INIT = 8'h10; + LUT3 com_llm_llm_tx_top_llmx08_tx_tlp_komp_lnk_tdst_rdy_n_d_i_0_0_a2_0_4 ( + .I0(com_llm_llm_tx_top_arb_state[2]), + .I1(com_llm_llm_tx_top_tx_tlp_sof_n), + .I2(com_llm_llm_tx_top_tx_tlp_vld_l_n_i), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_4) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_lnk_tdst_rdy_n_d_i_0_0_a2_0_5.INIT = 8'h10; + LUT3 com_llm_llm_tx_top_llmx08_tx_tlp_komp_lnk_tdst_rdy_n_d_i_0_0_a2_0_5 ( + .I0(com_llm_llm_tx_top_arb_state[2]), + .I1(com_llm_llm_tx_top_tx_tlp_sof_n), + .I2(com_llm_llm_tx_top_tx_tlp_vld_l_n_i), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_5) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_d_1_e_7_.INIT = 8'h08; + LUT3 com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_d_1_e_7_ ( + .I0(com_llm_llm_tx_top_tx_tlp_sof_pre_n), + .I1(G_32479_18), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_rem_pipe_DOUT[0]), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_N_51674) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_d_i_a4_0_i_o4_40_.INIT = 8'h04; + LUT3 com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_d_i_a4_0_i_o4_40_ ( + .I0(com_llm_llm_tx_top_rem_pipe[4]), + .I1(G_32479_18), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_eof_n_pipe_DOUT[0]), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_N_41721_i) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_d_sn_m3_0_a2_0_a2.INIT = 8'h08; + LUT3 com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_d_sn_m3_0_a2_0_a2 ( + .I0(com_llm_llm_tx_top_tx_tlp_sof_pre_n), + .I1(G_32479_18), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_eof_n_pipe_DOUT[0]), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_N_42608) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_62_DOUT_0_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_62_N_6), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_216_) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_61_DOUT_0_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_61_N_6), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_231_) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_60_DOUT_0_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_60_N_6), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_230_) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_59_DOUT_0_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_59_N_6), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_229_) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_58_DOUT_0_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_58_N_6), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_228_) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_57_DOUT_0_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_57_N_6), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_227_) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_56_DOUT_0_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_56_N_6), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_226_) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_55_DOUT_0_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_55_N_6), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_225_) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_54_DOUT_0_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_54_N_6), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_224_) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_53_DOUT_0_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_53_N_6), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_223_) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_52_DOUT_0_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_52_N_6), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_222_) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_51_DOUT_0_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_51_N_6), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_221_) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_50_DOUT_0_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_50_N_6), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_220_) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_49_DOUT_0_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_49_N_6), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_219_) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_48_DOUT_0_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_48_N_6), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_218_) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_47_DOUT_0_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_47_N_6), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_217_) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_46_DOUT_0_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_46_N_6), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_246_) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_45_DOUT_0_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_45_N_6), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_245_) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_44_DOUT_0_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_44_N_6), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_244_) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_43_DOUT_0_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_43_N_6), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_243_) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_42_DOUT_0_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_42_N_6), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_242_) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_41_DOUT_0_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_41_N_6), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_241_) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_40_DOUT_0_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_40_N_6), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_240_) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_39_DOUT_0_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_39_N_6), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_239_) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_38_DOUT_0_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_38_N_6), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_238_) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_37_DOUT_0_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_37_N_6), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_237_) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_36_DOUT_0_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_36_N_6), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_236_) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_35_DOUT_0_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_35_N_6), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_235_) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_34_DOUT_0_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_34_N_6), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_234_) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_33_DOUT_0_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_33_N_6), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_233_) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_32_DOUT_0_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_32_N_6), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_232_) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_31_DOUT_0_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_31_N_6), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_261_) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_30_DOUT_0_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_30_N_6), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_260_) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_29_DOUT_0_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_29_N_6), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_259_) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_28_DOUT_0_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_28_N_6), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_258_) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_27_DOUT_0_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_i_38), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_27_N_6), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_257_) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_26_DOUT_0_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_i_38), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_26_N_6), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_256_) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_25_DOUT_0_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_i_38), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_25_N_6), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_255_) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_24_DOUT_0_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_i_38), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_24_N_6), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_254_) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_23_DOUT_0_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_i_38), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_23_N_6), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_253_) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_22_DOUT_0_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_i_38), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_22_N_6), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_252_) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_21_DOUT_0_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_i_38), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_21_N_6), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_251_) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_20_DOUT_0_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_i_38), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_20_N_6), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_250_) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_19_DOUT_0_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_i_38), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_19_N_6), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_249_) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_18_DOUT_0_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_i_38), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_18_N_6), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_248_) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_17_DOUT_0_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_i_38), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_17_N_6), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_247_) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_16_DOUT_0_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_i_38), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_16_N_6), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_276_) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_15_DOUT_0_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_i_38), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_15_N_6), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_275_) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_14_DOUT_0_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_i_38), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_14_N_6), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_274_) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_13_DOUT_0_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_i_38), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_13_N_6), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_273_) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_12_DOUT_0_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_i_38), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_12_N_6), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_272_) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_11_DOUT_0_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_i_38), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_11_N_6), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_271_) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_10_DOUT_0_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_i_38), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_10_N_6), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_270_) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_9_DOUT_0_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_i_38), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_9_N_6), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_269_) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_8_DOUT_0_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_i_38), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_8_N_6), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_268_) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_7_DOUT_0_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_i_38), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_7_N_6), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_267_) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_6_DOUT_0_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_i_38), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_6_N_6), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_266_) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_5_DOUT_0_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_i_38), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_5_N_6), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_265_) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_4_DOUT_0_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_i_38), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_4_N_6), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_264_) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_3_DOUT_0_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_i_38), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_3_N_6), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_263_) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_2_DOUT_0_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_i_38), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_2_N_6), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_262_) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_1_DOUT_0_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_i_38), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_1_N_6), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_279_) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_0_DOUT_0_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_i_38), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_0_N_6), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_278_) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_DOUT_0_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_i_38), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_tmp_d_array_0[0]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_277_) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_tsn_pipe_10_DOUT_0_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_i_38), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tsn_pipe_10_N_6), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tsn_pipe_47_) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_tsn_pipe_9_DOUT_0_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_i_38), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tsn_pipe_9_N_6), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tsn_pipe_46_) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_tsn_pipe_8_DOUT_0_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_i_38), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tsn_pipe_8_N_6), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tsn_pipe_45_) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_tsn_pipe_7_DOUT_0_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_i_38), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tsn_pipe_7_N_6), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tsn_pipe_44_) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_tsn_pipe_6_DOUT_0_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_i_38), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tsn_pipe_6_N_6), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tsn_pipe_43_) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_tsn_pipe_5_DOUT_0_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_i_38), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tsn_pipe_5_N_6), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tsn_pipe_42_) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_tsn_pipe_4_DOUT_0_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_i_38), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tsn_pipe_4_N_6), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tsn_pipe_41_) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_tsn_pipe_3_DOUT_0_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_i_38), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tsn_pipe_3_N_6), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tsn_pipe_40_) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_tsn_pipe_2_DOUT_0_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_i_38), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tsn_pipe_2_N_6), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tsn_pipe_39_) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_tsn_pipe_1_DOUT_0_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_i_38), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tsn_pipe_1_N_6), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tsn_pipe_38_) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_tsn_pipe_0_DOUT_0_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_i_38), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tsn_pipe_0_N_6), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tsn_pipe_37_) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_tsn_pipe_DOUT_0_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_i_38), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tsn_pipe_N_6), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tsn_pipe_36_) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_eof_n_pipe_DOUT_0_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_i_38), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_eof_n_pipe_N_6), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_eof_n_pipe_DOUT[0]) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_rem_pipe_DOUT_0_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_i_38), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_rem_pipe_tmp_d_array_0[0]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_rem_pipe_DOUT[0]) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_6_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_3), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_td_mux_i_m3_i_m3_i_m4_0[6]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_6__1091) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_5_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_3), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_td_mux_i_m3_i_m3_i_m4_0[5]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_5__1092) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_4_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_3), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_td_mux_i_m3_i_m3_i_m4_0[4]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_4__1093) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_3_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_3), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_td_mux_i_m3_i_m3_i_m4_0[3]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_3__1094) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_2_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_3), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_td_mux_i_m3_i_m3_i_m4_0[2]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_2__1079) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_1_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_3), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_td_mux_i_m3_i_m3_i_m4_0[1]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_1__1080) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_0_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_3), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_td_mux_i_m3_i_m3_i_m4_0[0]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_0__1081) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_21_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_3), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_td_mux_i_m3_i_m3_i_m4_0[21]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_d32_sw[2]) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_20_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_3), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_td_mux_i_m3_i_m3_i_m4_0[20]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_d32_sw[3]) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_19_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_3), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_td_mux_i_m3_i_m3_i_m4_0[19]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_d32_sw[4]) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_18_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_3), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_td_mux_i_m3_i_m3_i_m4_0[18]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_d32_sw[5]) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_17_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_3), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_td_mux_i_m3_i_m3_i_m4_0[17]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_d32_sw[6]) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_16_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_3), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_td_mux_i_m3_i_m3_i_m4_0[16]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_d32_sw[7]) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_15_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_3), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_td_mux_i_m3_i_m3_i_m4_0[15]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_15__1082) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_14_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_3), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_td_mux_i_m3_i_m3_i_m4_0[14]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_14__1083) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_13_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_3), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_td_mux_i_m3_i_m3_i_m4_0[13]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_13__1084) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_12_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_3), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_td_mux_i_m3_i_m3_i_m4_0[12]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_12__1085) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_11_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_3), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_td_mux_i_m3_i_m3_i_m4_0[11]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_11__1086) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_10_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_3), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_td_mux_i_m3_i_m3_i_m4_0[10]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_10__1087) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_9_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_3), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_td_mux_i_m3_i_m3_i_m4_0[9]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_9__1088) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_8_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_3), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_td_mux_i_m3_i_m3_i_m4_0[8]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_8__1089) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_7_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_3), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_td_mux_i_m3_i_m3_i_m4_0[7]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_7__1090) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_36_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_3), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_td_mux_i_m3_i_m3_i_m4_0[36]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_d32_sw[19]) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_35_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_3), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_td_mux_i_m3_i_m3_i_m4_0[35]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_d32_sw[20]) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_34_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_3), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_td_mux_i_m3_i_m3_i_m4_0[34]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_d32_sw[21]) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_33_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_3), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_td_mux_i_m3_i_m3_i_m4_0[33]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_d32_sw[22]) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_32_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_3), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_td_mux_i_m3_i_m3_i_m4_0[32]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_d32_sw[23]) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_31_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_3), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_td_mux_i_m3_i_m3_i_m4_0[31]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_d32_sw[8]) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_30_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_3), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_td_mux_i_m3_i_m3_i_m4_0[30]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_d32_sw[9]) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_29_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_3), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_td_mux_i_m3_i_m3_i_m4_0[29]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_d32_sw[10]) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_28_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_3), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_td_mux_i_m3_i_m3_i_m4_0[28]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_d32_sw[11]) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_27_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_3), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_td_mux_i_m3_i_m3_i_m4_0[27]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_d32_sw[12]) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_26_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_3), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_td_mux_i_m3_i_m3_i_m4_0[26]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_d32_sw[13]) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_25_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_3), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_td_mux_i_m3_i_m3_i_m4_0[25]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_d32_sw[14]) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_24_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_3), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_td_mux_i_m3_i_m3_i_m4_0[24]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_d32_sw[15]) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_23_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_3), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_td_mux_i_m3_i_m3_i_m4_0[23]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_d32_sw[0]) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_22_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_3), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_td_mux_i_m3_i_m3_i_m4_0[22]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_d32_sw[1]) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_51_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_3), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_td_mux_i_m3_i_m3_i_m4_0[51]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_d64_sw_36_) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_50_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_3), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_td_mux_i_m3_i_m3_i_m4_0[50]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_d64_sw_37_) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_49_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_3), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_td_mux_i_m3_i_m3_i_m4_0[49]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_d64_sw_38_) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_48_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_3), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_td_mux_i_m3_i_m3_i_m4_0[48]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_d64_sw_39_) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_47_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_3), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_td_mux_i_m3_i_m3_i_m4_0[47]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_d32_sw[24]) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_46_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_3), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_td_mux_i_m3_i_m3_i_m4_0[46]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_d32_sw[25]) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_45_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_3), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_td_mux_i_m3_i_m3_i_m4_0[45]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_d32_sw[26]) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_44_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_3), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_td_mux_i_m3_i_m3_i_m4_0[44]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_d32_sw[27]) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_43_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_3), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_td_mux_i_m3_i_m3_i_m4_0[43]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_d32_sw[28]) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_42_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_3), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_td_mux_i_m3_i_m3_i_m4_0[42]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_d32_sw[29]) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_41_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_3), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_td_mux_i_m3_i_m3_i_m4_0[41]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_d32_sw[30]) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_40_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_3), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_td_mux_i_m3_i_m3_i_m4_0[40]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_d32_sw[31]) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_39_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_3), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_td_mux_i_m3_i_m3_i_m4_0[39]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_d32_sw[16]) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_38_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_3), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_td_mux_i_m3_i_m3_i_m4_0[38]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_d32_sw[17]) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_37_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_3), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_td_mux_i_m3_i_m3_i_m4_0[37]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_d32_sw[18]) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_66_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_3), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_2__1079), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_d16_sw[5]) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_65_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_3), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_1__1080), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_d16_sw[6]) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_64_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_3), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_0__1081), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_d16_sw[7]) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_63_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_3), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_td_mux_i_m3_i_m3_i_m4_0[63]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_d64_sw_40_) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_62_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_3), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_td_mux_i_m3_i_m3_i_m4_0[62]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_d64_sw_41_) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_61_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_3), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_td_mux_i_m3_i_m3_i_m4_0[61]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_d64_sw_42_) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_60_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_3), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_td_mux_i_m3_i_m3_i_m4_0[60]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_d64_sw_43_) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_59_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_3), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_td_mux_i_m3_i_m3_i_m4_0[59]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_d64_sw_44_) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_58_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_3), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_td_mux_i_m3_i_m3_i_m4_0[58]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_d64_sw_45_) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_57_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_3), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_td_mux_i_m3_i_m3_i_m4_0[57]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_d64_sw_46_) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_56_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_3), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_td_mux_i_m3_i_m3_i_m4_0[56]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_d64_sw_47_) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_55_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_3), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_td_mux_i_m3_i_m3_i_m4_0[55]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_d64_sw_32_) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_54_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_3), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_td_mux_i_m3_i_m3_i_m4_0[54]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_d64_sw_33_) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_53_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_3), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_td_mux_i_m3_i_m3_i_m4_0[53]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_d64_sw_34_) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_52_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_3), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_td_mux_i_m3_i_m3_i_m4_0[52]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_d64_sw_35_) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_79_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_3), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_15__1082), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_d16_sw[8]) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_78_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_3), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_14__1083), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_d16_sw[9]) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_77_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_3), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_13__1084), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_d16_sw[10]) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_76_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_3), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_12__1085), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_d16_sw[11]) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_75_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_3), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_11__1086), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_d16_sw[12]) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_74_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_3), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_10__1087), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_d16_sw[13]) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_73_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_3), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_9__1088), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_d16_sw[14]) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_72_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_3), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_8__1089), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_d16_sw[15]) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_71_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_3), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_7__1090), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_d16_sw[0]) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_70_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_3), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_6__1091), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_d16_sw[1]) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_69_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_3), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_5__1092), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_d16_sw[2]) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_68_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_3), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_4__1093), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_d16_sw[3]) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_67_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_3), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_3__1094), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_d16_sw[4]) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_bat_td_63_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_bat_sof_n7), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_lnk_td[63]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_bat_td[63]) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_bat_td_62_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_bat_sof_n7), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_lnk_td[62]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_bat_td[62]) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_bat_td_61_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_bat_sof_n7), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_lnk_td[61]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_bat_td[61]) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_bat_td_60_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_bat_sof_n7), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_lnk_td[60]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_bat_td[60]) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_bat_td_59_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_bat_sof_n7), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_lnk_td[59]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_bat_td[59]) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_bat_td_58_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_bat_sof_n7), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_lnk_td[58]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_bat_td[58]) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_bat_td_57_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_bat_sof_n7), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_lnk_td[57]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_bat_td[57]) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_bat_td_56_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_bat_sof_n7), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_lnk_td[56]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_bat_td[56]) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_bat_td_55_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_bat_sof_n7), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_lnk_td[55]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_bat_td[55]) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_bat_td_54_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_bat_sof_n7), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_lnk_td[54]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_bat_td[54]) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_bat_td_53_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_bat_sof_n7), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_lnk_td[53]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_bat_td[53]) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_bat_td_52_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_bat_sof_n7), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_lnk_td[52]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_bat_td[52]) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_bat_td_51_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_bat_sof_n7), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_lnk_td[51]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_bat_td[51]) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_bat_td_50_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_bat_sof_n7), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_lnk_td[50]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_bat_td[50]) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_bat_td_49_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_bat_sof_n7), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_lnk_td[49]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_bat_td[49]) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_bat_td_48_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_bat_sof_n7), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_lnk_td[48]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_bat_td[48]) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_bat_td_47_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_bat_sof_n7), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_lnk_td[47]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_bat_td[47]) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_bat_td_46_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_bat_sof_n7), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_lnk_td[46]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_bat_td[46]) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_bat_td_45_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_bat_sof_n7), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_lnk_td[45]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_bat_td[45]) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_bat_td_44_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_bat_sof_n7), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_lnk_td[44]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_bat_td[44]) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_bat_td_43_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_bat_sof_n7), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_lnk_td[43]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_bat_td[43]) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_bat_td_42_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_bat_sof_n7), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_lnk_td[42]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_bat_td[42]) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_bat_td_41_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_bat_sof_n7), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_lnk_td[41]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_bat_td[41]) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_bat_td_40_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_bat_sof_n7), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_lnk_td[40]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_bat_td[40]) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_bat_td_39_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_bat_sof_n7), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_lnk_td[39]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_bat_td[39]) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_bat_td_38_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_bat_sof_n7), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_lnk_td[38]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_bat_td[38]) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_bat_td_37_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_bat_sof_n7), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_lnk_td[37]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_bat_td[37]) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_bat_td_36_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_bat_sof_n7), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_lnk_td[36]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_bat_td[36]) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_bat_td_35_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_bat_sof_n7), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_lnk_td[35]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_bat_td[35]) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_bat_td_34_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_bat_sof_n7), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_lnk_td[34]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_bat_td[34]) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_bat_td_33_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_bat_sof_n7), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_lnk_td[33]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_bat_td[33]) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_bat_td_32_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_bat_sof_n7), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_lnk_td[32]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_bat_td[32]) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_bat_td_31_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_bat_sof_n7), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_lnk_td[31]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_bat_td[31]) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_bat_td_30_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_bat_sof_n7), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_lnk_td[30]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_bat_td[30]) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_bat_td_29_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_bat_sof_n7), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_lnk_td[29]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_bat_td[29]) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_bat_td_28_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_bat_sof_n7), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_lnk_td[28]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_bat_td[28]) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_bat_td_27_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_bat_sof_n7), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_lnk_td[27]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_bat_td[27]) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_bat_td_26_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_bat_sof_n7), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_lnk_td[26]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_bat_td[26]) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_bat_td_25_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_bat_sof_n7), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_lnk_td[25]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_bat_td[25]) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_bat_td_24_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_bat_sof_n7), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_lnk_td[24]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_bat_td[24]) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_bat_td_23_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_bat_sof_n7), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_lnk_td[23]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_bat_td[23]) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_bat_td_22_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_bat_sof_n7), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_lnk_td[22]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_bat_td[22]) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_bat_td_21_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_bat_sof_n7), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_lnk_td[21]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_bat_td[21]) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_bat_td_20_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_bat_sof_n7), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_lnk_td[20]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_bat_td[20]) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_bat_td_19_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_bat_sof_n7), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_lnk_td[19]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_bat_td[19]) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_bat_td_18_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_bat_sof_n7), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_lnk_td[18]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_bat_td[18]) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_bat_td_17_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_bat_sof_n7), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_lnk_td[17]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_bat_td[17]) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_bat_td_16_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_bat_sof_n7), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_lnk_td[16]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_bat_td[16]) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_bat_td_15_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_bat_sof_n7), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_lnk_td[15]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_bat_td[15]) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_bat_td_14_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_bat_sof_n7), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_lnk_td[14]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_bat_td[14]) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_bat_td_13_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_bat_sof_n7), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_lnk_td[13]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_bat_td[13]) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_bat_td_12_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_bat_sof_n7), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_lnk_td[12]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_bat_td[12]) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_bat_td_11_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_bat_sof_n7), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_lnk_td[11]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_bat_td[11]) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_bat_td_10_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_bat_sof_n7), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_lnk_td[10]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_bat_td[10]) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_bat_td_9_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_bat_sof_n7), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_lnk_td[9]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_bat_td[9]) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_bat_td_8_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_bat_sof_n7), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_lnk_td[8]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_bat_td[8]) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_bat_td_7_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_bat_sof_n7), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_lnk_td[7]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_bat_td[7]) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_bat_td_6_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_bat_sof_n7), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_lnk_td[6]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_bat_td[6]) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_bat_td_5_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_bat_sof_n7), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_lnk_td[5]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_bat_td[5]) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_bat_td_4_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_bat_sof_n7), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_lnk_td[4]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_bat_td[4]) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_bat_td_3_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_bat_sof_n7), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_lnk_td[3]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_bat_td[3]) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_bat_td_2_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_bat_sof_n7), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_lnk_td[2]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_bat_td[2]) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_bat_td_1_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_bat_sof_n7), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_lnk_td[1]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_bat_td[1]) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_bat_td_0_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_bat_sof_n7), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_lnk_td[0]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_bat_td[0]) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_tsn_pipe_11_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_0), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_lnk_ttrans_seq[11]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tsn_pipe_11__1095) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_tsn_pipe_10_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_0), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_lnk_ttrans_seq[10]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tsn_pipe_10__1096) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_tsn_pipe_9_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_0), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_lnk_ttrans_seq[9]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tsn_pipe_9__1097) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_tsn_pipe_8_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_0), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_lnk_ttrans_seq[8]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tsn_pipe_8__1098) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_tsn_pipe_7_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_0), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_lnk_ttrans_seq[7]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tsn_pipe_7__1099) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_tsn_pipe_6_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_0), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_lnk_ttrans_seq[6]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tsn_pipe_6__1100) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_tsn_pipe_5_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_0), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_lnk_ttrans_seq[5]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tsn_pipe_5__1101) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_tsn_pipe_4_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_0), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_lnk_ttrans_seq[4]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tsn_pipe_4__1102) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_tsn_pipe_3_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_0), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_lnk_ttrans_seq[3]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tsn_pipe_3__1103) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_tsn_pipe_2_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_0), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_lnk_ttrans_seq[2]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tsn_pipe_2__1104) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_tsn_pipe_1_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_0), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_lnk_ttrans_seq[1]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tsn_pipe_1__1105) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_tsn_pipe_0_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_0), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_lnk_ttrans_seq[0]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tsn_pipe_0__1106) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_crc_23_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_0), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_sw_early_crc_i[23]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_crc[23]) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_crc_22_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_0), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_sw_early_crc_i[22]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_crc[22]) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_crc_21_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_0), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_sw_early_crc_i[21]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_crc[21]) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_crc_20_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_0), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_sw_early_crc_i[20]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_crc[20]) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_crc_19_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_0), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_sw_early_crc_i[19]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_crc[19]) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_crc_18_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_0), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_sw_early_crc_i[18]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_crc[18]) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_crc_17_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_0), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_sw_early_crc_i[17]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_crc[17]) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_crc_16_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_0), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_sw_early_crc_i[16]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_crc[16]) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_crc_15_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_0), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_sw_early_crc_i[15]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_crc[15]) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_crc_14_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_0), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_sw_early_crc_i[14]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_crc[14]) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_crc_13_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_0), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_sw_early_crc_i[13]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_crc[13]) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_crc_12_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_0), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_sw_early_crc_i[12]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_crc[12]) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_crc_11_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_0), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_sw_early_crc_i[11]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_crc[11]) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_crc_10_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_0), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_sw_early_crc_i[10]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_crc[10]) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_crc_9_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_0), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_sw_early_crc_i[9]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_crc[9]) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_crc_8_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_0), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_sw_early_crc_i[8]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_crc[8]) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_crc_7_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_0), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_sw_early_crc_i[7]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_crc[7]) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_crc_6_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_0), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_sw_early_crc_i[6]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_crc[6]) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_crc_5_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_0), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_sw_early_crc_i[5]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_crc[5]) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_crc_4_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_0), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_sw_early_crc_i[4]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_crc[4]) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_crc_3_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_0), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_sw_early_crc_i[3]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_crc[3]) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_crc_2_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_0), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_sw_early_crc_i[2]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_crc[2]) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_crc_1_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_0), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_sw_early_crc_i[1]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_crc[1]) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_crc_0_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_0), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_sw_early_crc_i[0]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_crc[0]) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_63_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_0), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_N_40550_i), + .Q(com_llm_llm_tx_top_tx_tlp_td[63]) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_62_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_0), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_N_40548_i), + .Q(com_llm_llm_tx_top_tx_tlp_td[62]) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_61_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_0), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_N_21250_i), + .Q(com_llm_llm_tx_top_tx_tlp_td[61]) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_60_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_0), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_N_21248_i), + .Q(com_llm_llm_tx_top_tx_tlp_td[60]) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_59_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_0), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_N_21246_i), + .Q(com_llm_llm_tx_top_tx_tlp_td[59]) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_58_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_0), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_N_21244_i), + .Q(com_llm_llm_tx_top_tx_tlp_td[58]) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_57_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_0), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_N_21242_i), + .Q(com_llm_llm_tx_top_tx_tlp_td[57]) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_56_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_0), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_N_21240_i), + .Q(com_llm_llm_tx_top_tx_tlp_td[56]) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_55_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_0), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_N_21238_i), + .Q(com_llm_llm_tx_top_tx_tlp_td[55]) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_54_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_0), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_N_21236_i), + .Q(com_llm_llm_tx_top_tx_tlp_td[54]) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_53_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_0), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_N_21234_i), + .Q(com_llm_llm_tx_top_tx_tlp_td[53]) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_52_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_0), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_N_21232_i), + .Q(com_llm_llm_tx_top_tx_tlp_td[52]) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_51_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_0), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_d_51_), + .Q(com_llm_llm_tx_top_tx_tlp_td[51]) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_50_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_0), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_d_50_), + .Q(com_llm_llm_tx_top_tx_tlp_td[50]) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_49_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_0), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_N_21230_i), + .Q(com_llm_llm_tx_top_tx_tlp_td[49]) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_48_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_0), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_N_21228_i), + .Q(com_llm_llm_tx_top_tx_tlp_td[48]) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_47_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_0), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_N_21226_i), + .Q(com_llm_llm_tx_top_tx_tlp_td[47]) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_46_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_0), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_N_21224_i), + .Q(com_llm_llm_tx_top_tx_tlp_td[46]) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_45_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_0), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_N_21222_i), + .Q(com_llm_llm_tx_top_tx_tlp_td[45]) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_44_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_0), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_N_21220_i), + .Q(com_llm_llm_tx_top_tx_tlp_td[44]) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_43_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_0), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_N_21218_i), + .Q(com_llm_llm_tx_top_tx_tlp_td[43]) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_42_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_0), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_N_21216_i), + .Q(com_llm_llm_tx_top_tx_tlp_td[42]) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_41_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_0), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_N_21214_i), + .Q(com_llm_llm_tx_top_tx_tlp_td[41]) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_40_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_0), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_N_21212_i), + .Q(com_llm_llm_tx_top_tx_tlp_td[40]) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_39_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_0), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_d_39_), + .Q(com_llm_llm_tx_top_tx_tlp_td[39]) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_38_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_0), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_d_38_), + .Q(com_llm_llm_tx_top_tx_tlp_td[38]) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_37_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_0), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_d_37_), + .Q(com_llm_llm_tx_top_tx_tlp_td[37]) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_36_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_0), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_d_36_), + .Q(com_llm_llm_tx_top_tx_tlp_td[36]) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_35_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_0), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_d_35_), + .Q(com_llm_llm_tx_top_tx_tlp_td[35]) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_34_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_0), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_d_34_), + .Q(com_llm_llm_tx_top_tx_tlp_td[34]) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_33_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_0), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_d_33_), + .Q(com_llm_llm_tx_top_tx_tlp_td[33]) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_32_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_0), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_d_32_), + .Q(com_llm_llm_tx_top_tx_tlp_td[32]) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_31_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_0), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_d_31_), + .Q(com_llm_llm_tx_top_tx_tlp_td[31]) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_30_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_0), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_d_30_), + .Q(com_llm_llm_tx_top_tx_tlp_td[30]) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_29_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_0), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_d_29_), + .Q(com_llm_llm_tx_top_tx_tlp_td[29]) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_28_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_0), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_d_28_), + .Q(com_llm_llm_tx_top_tx_tlp_td[28]) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_27_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_0), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_d_27_), + .Q(com_llm_llm_tx_top_tx_tlp_td[27]) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_26_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_0), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_d_26_), + .Q(com_llm_llm_tx_top_tx_tlp_td[26]) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_25_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_0), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_d_25_), + .Q(com_llm_llm_tx_top_tx_tlp_td[25]) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_24_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_0), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_d_24_), + .Q(com_llm_llm_tx_top_tx_tlp_td[24]) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_23_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_0), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_d_23_), + .Q(com_llm_llm_tx_top_tx_tlp_td[23]) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_22_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_0), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_d_22_), + .Q(com_llm_llm_tx_top_tx_tlp_td[22]) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_21_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_d_21_), + .Q(com_llm_llm_tx_top_tx_tlp_td[21]) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_20_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_d_20_), + .Q(com_llm_llm_tx_top_tx_tlp_td[20]) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_19_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_d_19_), + .Q(com_llm_llm_tx_top_tx_tlp_td[19]) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_18_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_d_18_), + .Q(com_llm_llm_tx_top_tx_tlp_td[18]) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_17_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_d_17_), + .Q(com_llm_llm_tx_top_tx_tlp_td[17]) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_16_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_d_16_), + .Q(com_llm_llm_tx_top_tx_tlp_td[16]) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_15_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_d_15_), + .Q(com_llm_llm_tx_top_tx_tlp_td[15]) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_14_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_d_14_), + .Q(com_llm_llm_tx_top_tx_tlp_td[14]) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_13_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_d_13_), + .Q(com_llm_llm_tx_top_tx_tlp_td[13]) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_12_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_d_12_), + .Q(com_llm_llm_tx_top_tx_tlp_td[12]) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_11_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_d_11_), + .Q(com_llm_llm_tx_top_tx_tlp_td[11]) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_10_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_d_10_), + .Q(com_llm_llm_tx_top_tx_tlp_td[10]) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_9_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_d_9_), + .Q(com_llm_llm_tx_top_tx_tlp_td[9]) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_8_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_d_8_), + .Q(com_llm_llm_tx_top_tx_tlp_td[8]) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_7_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_d_7__1107), + .Q(com_llm_llm_tx_top_tx_tlp_td[7]) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_6_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_d_6__1108), + .Q(com_llm_llm_tx_top_tx_tlp_td[6]) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_5_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_d_5__1109), + .Q(com_llm_llm_tx_top_tx_tlp_td[5]) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_4_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_d_4__1110), + .Q(com_llm_llm_tx_top_tx_tlp_td[4]) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_3_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_d_3__1111), + .Q(com_llm_llm_tx_top_tx_tlp_td[3]) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_2_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_d_2__1112), + .Q(com_llm_llm_tx_top_tx_tlp_td[2]) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_1_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_d_1__1113), + .Q(com_llm_llm_tx_top_tx_tlp_td[1]) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_0_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_d_0__1114), + .Q(com_llm_llm_tx_top_tx_tlp_td[0]) + ); + INV com_llm_llm_tx_top_llmx08_tx_tlp_komp_lnk_tdst_rdy_n_i ( + .I(com_lnk_tdst_rdy_n), + .O(com_lnk_tdst_rdy_n_i) + ); + INV com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_i ( + .I(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_i_38) + ); + FDSE com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crc32_d64_feedback_0_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_1), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_22321_i_1204), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crc32_d64_feedback[0]), + .S(plm_link_up_i) + ); + FDSE com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crc32_d64_feedback_1_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_1), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_22320_i_1203), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crc32_d64_feedback[1]), + .S(plm_link_up_i) + ); + FDSE com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crc32_d64_feedback_2_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_1), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_22319_i_1202), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crc32_d64_feedback[2]), + .S(plm_link_up_i) + ); + FDSE com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crc32_d64_feedback_3_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_1), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_22318_i_1201), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crc32_d64_feedback[3]), + .S(plm_link_up_i) + ); + FDSE com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crc32_d64_feedback_4_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_1), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_22317_i_1200), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crc32_d64_feedback[4]), + .S(plm_link_up_i) + ); + FDSE com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crc32_d64_feedback_5_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_1), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_22316_i_1199), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crc32_d64_feedback[5]), + .S(plm_link_up_i) + ); + FDSE com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crc32_d64_feedback_6_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_1), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_22347_i_1198), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crc32_d64_feedback[6]), + .S(plm_link_up_i) + ); + FDSE com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crc32_d64_feedback_7_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_1), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_22346_i_1197), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crc32_d64_feedback[7]), + .S(plm_link_up_i) + ); + FDSE com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crc32_d64_feedback_8_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_1), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_22345_i_1196), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crc32_d64_feedback[8]), + .S(plm_link_up_i) + ); + FDSE com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crc32_d64_feedback_9_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_1), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_22344_i_1195), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crc32_d64_feedback[9]), + .S(plm_link_up_i) + ); + FDSE com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crc32_d64_feedback_10_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_1), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_22343_i_1194), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crc32_d64_feedback[10]), + .S(plm_link_up_i) + ); + FDSE com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crc32_d64_feedback_11_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_1), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_22342_i_1193), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crc32_d64_feedback[11]), + .S(plm_link_up_i) + ); + FDSE com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crc32_d64_feedback_12_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_1), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_22341_i_1192), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crc32_d64_feedback[12]), + .S(plm_link_up_i) + ); + FDSE com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crc32_d64_feedback_13_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_1), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_22340_i_1191), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crc32_d64_feedback[13]), + .S(plm_link_up_i) + ); + FDSE com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crc32_d64_feedback_14_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_1), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_22339_i_1190), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crc32_d64_feedback[14]), + .S(plm_link_up_i) + ); + FDSE com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crc32_d64_feedback_15_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_1), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_22338_i_1189), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crc32_d64_feedback[15]), + .S(plm_link_up_i) + ); + FDSE com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crc32_d64_feedback_16_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_1), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_22337_i_1188), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crc32_d64_feedback[16]), + .S(plm_link_up_i) + ); + FDSE com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crc32_d64_feedback_17_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_1), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_22336_i_1187), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crc32_d64_feedback[17]), + .S(plm_link_up_i) + ); + FDSE com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crc32_d64_feedback_18_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_1), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_22335_i_1186), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crc32_d64_feedback[18]), + .S(plm_link_up_i) + ); + FDSE com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crc32_d64_feedback_19_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_1), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_22315_i_1185), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crc32_d64_feedback[19]), + .S(plm_link_up_i) + ); + FDSE com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crc32_d64_feedback_20_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_1), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_22314_i_1184), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crc32_d64_feedback[20]), + .S(plm_link_up_i) + ); + FDSE com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crc32_d64_feedback_21_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_1), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_22313_i_1183), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crc32_d64_feedback[21]), + .S(plm_link_up_i) + ); + FDSE com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crc32_d64_feedback_22_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_1), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_22312_i_1182), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crc32_d64_feedback[22]), + .S(plm_link_up_i) + ); + FDSE com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crc32_d64_feedback_23_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_1), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_22311_i_1181), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crc32_d64_feedback[23]), + .S(plm_link_up_i) + ); + FDSE com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crc32_d64_feedback_24_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_1), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_22310_i_1180), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crc32_d64_feedback[24]), + .S(plm_link_up_i) + ); + FDSE com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crc32_d64_feedback_25_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_1), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_22309_i_1179), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crc32_d64_feedback[25]), + .S(plm_link_up_i) + ); + FDSE com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crc32_d64_feedback_26_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_1), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_22308_i_1178), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crc32_d64_feedback[26]), + .S(plm_link_up_i) + ); + FDSE com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crc32_d64_feedback_27_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_1), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_22307_i_1177), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crc32_d64_feedback[27]), + .S(plm_link_up_i) + ); + FDSE com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crc32_d64_feedback_28_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_1), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_22306_i_1176), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crc32_d64_feedback[28]), + .S(plm_link_up_i) + ); + FDSE com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crc32_d64_feedback_29_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_1), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_22305_i_1175), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crc32_d64_feedback[29]), + .S(plm_link_up_i) + ); + FDSE com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crc32_d64_feedback_30_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_2), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_22304_i_1174), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crc32_d64_feedback[30]), + .S(plm_link_up_i) + ); + FDSE com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crc32_d64_feedback_31_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_2), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_22303_i_1173), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crc32_d64_feedback[31]), + .S(plm_link_up_i) + ); + FDSE com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_0_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_2), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4[0]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_sw_early_crc[7]), + .S(plm_link_up_i) + ); + FDSE com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_1_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_2), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4[1]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_sw_early_crc[6]), + .S(plm_link_up_i) + ); + FDSE com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_2_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_2), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4[2]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_sw_early_crc[5]), + .S(plm_link_up_i) + ); + FDSE com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_3_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_2), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4[3]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_sw_early_crc[4]), + .S(plm_link_up_i) + ); + FDSE com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_2), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4[4]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_sw_early_crc[3]), + .S(plm_link_up_i) + ); + FDSE com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_5_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_2), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4[5]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_sw_early_crc[2]), + .S(plm_link_up_i) + ); + FDSE com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_6_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_2), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4[6]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_sw_early_crc[1]), + .S(plm_link_up_i) + ); + FDSE com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_7_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_2), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4[7]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_sw_early_crc[0]), + .S(plm_link_up_i) + ); + FDSE com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_8_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_2), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4[8]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_sw_early_crc[15]), + .S(plm_link_up_i) + ); + FDSE com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_9_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_2), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4[9]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_sw_early_crc[14]), + .S(plm_link_up_i) + ); + FDSE com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_10_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_2), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4[10]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_sw_early_crc[13]), + .S(plm_link_up_i) + ); + FDSE com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_11_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_2), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4[11]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_sw_early_crc[12]), + .S(plm_link_up_i) + ); + FDSE com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_12_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_2), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4[12]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_sw_early_crc[11]), + .S(plm_link_up_i) + ); + FDSE com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_13_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_2), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4[13]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_sw_early_crc[10]), + .S(plm_link_up_i) + ); + FDSE com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_14_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_2), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4[14]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_sw_early_crc[9]), + .S(plm_link_up_i) + ); + FDSE com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_15_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_2), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4[15]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_sw_early_crc[8]), + .S(plm_link_up_i) + ); + FDSE com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_16_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_2), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4[16]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_sw_early_crc[23]), + .S(plm_link_up_i) + ); + FDSE com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_17_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_2), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4[17]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_sw_early_crc[22]), + .S(plm_link_up_i) + ); + FDSE com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_18_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_2), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4[18]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_sw_early_crc[21]), + .S(plm_link_up_i) + ); + FDSE com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_19_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_2), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4[19]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_sw_early_crc[20]), + .S(plm_link_up_i) + ); + FDSE com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_20_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_2), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4[20]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_sw_early_crc[19]), + .S(plm_link_up_i) + ); + FDSE com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_21_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_2), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4[21]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_sw_early_crc[18]), + .S(plm_link_up_i) + ); + FDSE com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_22_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_2), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4[22]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_sw_early_crc[17]), + .S(plm_link_up_i) + ); + FDSE com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_23_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_2), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4[23]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_sw_early_crc[16]), + .S(plm_link_up_i) + ); + FDSE com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_24_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_2), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4[24]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_sw_early_crc[31]), + .S(plm_link_up_i) + ); + FDSE com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_25_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_2), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4[25]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_sw_early_crc[30]), + .S(plm_link_up_i) + ); + FDSE com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_26_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_2), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4[26]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_sw_early_crc[29]), + .S(plm_link_up_i) + ); + FDSE com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_27_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_2), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4[27]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_sw_early_crc[28]), + .S(plm_link_up_i) + ); + FDSE com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_28_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_2), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4[28]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_sw_early_crc[27]), + .S(plm_link_up_i) + ); + FDSE com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_29_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_2), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4[29]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_sw_early_crc[26]), + .S(plm_link_up_i) + ); + FDSE com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_30_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_2), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4[30]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_sw_early_crc[25]), + .S(plm_link_up_i) + ); + FDSE com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_31_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_2), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4[31]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_sw_early_crc[24]), + .S(plm_link_up_i) + ); + FDRE com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crcdatawidth_qq_2_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_2), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crcdatawidth_q[2]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crcdatawidth_qq[2]), + .R(plm_link_up_i) + ); + FDRE com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crcint_qq ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_2), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mgt_tx_crcint), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crcint_qq_1205), + .R(plm_link_up_i) + ); + FDSE com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q_0_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_2), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_new_c32_d64[0]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[0]), + .S(plm_link_up_i) + ); + FDSE com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q_1_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_2), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_new_c32_d64[1]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[1]), + .S(plm_link_up_i) + ); + FDSE com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q_2_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_2), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_new_c32_d64[2]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[2]), + .S(plm_link_up_i) + ); + FDSE com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q_3_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_2), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_new_c32_d64[3]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[3]), + .S(plm_link_up_i) + ); + FDSE com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q_4_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_2), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_new_c32_d64[4]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[4]), + .S(plm_link_up_i) + ); + FDSE com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q_5_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_2), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_new_c32_d64[5]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[5]), + .S(plm_link_up_i) + ); + FDSE com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q_6_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_2), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_new_c32_d64[6]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[6]), + .S(plm_link_up_i) + ); + FDSE com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q_7_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_2), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_new_c32_d64[7]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[7]), + .S(plm_link_up_i) + ); + FDSE com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q_8_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_2), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_new_c32_d64[8]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[8]), + .S(plm_link_up_i) + ); + FDSE com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q_9_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_2), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_new_c32_d64[9]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[9]), + .S(plm_link_up_i) + ); + FDSE com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q_10_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_2), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_new_c32_d64[10]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[10]), + .S(plm_link_up_i) + ); + FDSE com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q_11_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_2), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_new_c32_d64[11]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[11]), + .S(plm_link_up_i) + ); + FDSE com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q_12_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_2), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_new_c32_d64[12]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[12]), + .S(plm_link_up_i) + ); + FDSE com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q_13_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_2), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_new_c32_d64[13]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[13]), + .S(plm_link_up_i) + ); + FDSE com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q_14_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_2), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_new_c32_d64[14]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[14]), + .S(plm_link_up_i) + ); + FDSE com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q_15_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_2), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_new_c32_d64[15]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[15]), + .S(plm_link_up_i) + ); + FDSE com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q_16_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_2), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_new_c32_d64[16]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[16]), + .S(plm_link_up_i) + ); + FDSE com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q_17_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_2), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_new_c32_d64[17]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[17]), + .S(plm_link_up_i) + ); + FDSE com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q_18_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_2), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_new_c32_d64[18]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[18]), + .S(plm_link_up_i) + ); + FDSE com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q_19_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_2), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_new_c32_d64[19]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[19]), + .S(plm_link_up_i) + ); + FDSE com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q_20_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_2), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_new_c32_d64[20]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[20]), + .S(plm_link_up_i) + ); + FDSE com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q_21_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_2), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_new_c32_d64[21]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[21]), + .S(plm_link_up_i) + ); + FDSE com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q_22_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_2), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_new_c32_d64[22]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[22]), + .S(plm_link_up_i) + ); + FDSE com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q_23_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_2), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_new_c32_d64[23]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[23]), + .S(plm_link_up_i) + ); + FDSE com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q_24_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_2), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_new_c32_d64[24]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[24]), + .S(plm_link_up_i) + ); + FDSE com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q_25_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_2), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_new_c32_d64[25]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[25]), + .S(plm_link_up_i) + ); + FDSE com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q_26_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_2), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_new_c32_d64[26]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[26]), + .S(plm_link_up_i) + ); + FDSE com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q_27_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_2), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_new_c32_d64[27]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[27]), + .S(plm_link_up_i) + ); + FDSE com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q_28_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_2), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_new_c32_d64[28]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[28]), + .S(plm_link_up_i) + ); + FDSE com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q_29_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_2), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_new_c32_d64[29]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[29]), + .S(plm_link_up_i) + ); + FDSE com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q_30_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_2), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_new_c32_d64[30]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[30]), + .S(plm_link_up_i) + ); + FDSE com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q_31_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_2), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_new_c32_d64[31]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[31]), + .S(plm_link_up_i) + ); + FDRE com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crcint_q ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_2), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_N_30689_i), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mgt_tx_crcint), + .R(plm_link_up_i) + ); + FDRE com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crcdatawidth_q_2_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_2), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_eof_n_pipe_5078[1]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crcdatawidth_q[2]), + .R(plm_link_up_i) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_0_0_0_.INIT = 8'hAC; + LUT3_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_0_0_0_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_d32_sw[0]), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_d32_sw[16]), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_rem_pipe_5079[0]), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_5966) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_0_0_1_.INIT = 8'hAC; + LUT3_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_0_0_1_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_d32_sw[1]), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_d32_sw[17]), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_rem_pipe_5079[0]), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_5967) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_0_0_2_.INIT = 8'hAC; + LUT3_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_0_0_2_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_d32_sw[2]), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_d32_sw[18]), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_rem_pipe_5079[0]), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_5968) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_0_0_3_.INIT = 8'hAC; + LUT3_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_0_0_3_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_d32_sw[3]), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_d32_sw[19]), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_rem_pipe_5079[0]), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_5969) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_0_0_4_.INIT = 8'hAC; + LUT3_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_0_0_4_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_d32_sw[4]), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_d32_sw[20]), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_rem_pipe_5079[0]), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_5970) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_0_0_5_.INIT = 8'hAC; + LUT3_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_0_0_5_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_d32_sw[5]), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_d32_sw[21]), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_rem_pipe_5079[0]), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_5971) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_0_0_6_.INIT = 8'hAC; + LUT3_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_0_0_6_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_d32_sw[6]), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_d32_sw[22]), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_rem_pipe_5079[0]), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_5972) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_0_0_7_.INIT = 8'hAC; + LUT3_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_0_0_7_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_d32_sw[7]), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_d32_sw[23]), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_rem_pipe_5079[0]), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_5973) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_0_0_8_.INIT = 8'hAC; + LUT3_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_0_0_8_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_d32_sw[8]), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_d32_sw[24]), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_rem_pipe_5079[0]), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_5974) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_0_0_9_.INIT = 8'hAC; + LUT3_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_0_0_9_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_d32_sw[9]), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_d32_sw[25]), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_rem_pipe_5079[0]), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_5975) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_0_0_10_.INIT = 8'hAC; + LUT3_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_0_0_10_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_d32_sw[10]), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_d32_sw[26]), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_rem_pipe_5079[0]), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_5976) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_0_0_11_.INIT = 8'hAC; + LUT3_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_0_0_11_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_d32_sw[11]), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_d32_sw[27]), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_rem_pipe_5079[0]), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_5977) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_0_0_12_.INIT = 8'hAC; + LUT3_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_0_0_12_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_d32_sw[12]), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_d32_sw[28]), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_rem_pipe_5079[0]), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_5978) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_0_0_13_.INIT = 8'hAC; + LUT3_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_0_0_13_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_d32_sw[13]), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_d32_sw[29]), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_rem_pipe_5079[0]), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_5979) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_0_0_14_.INIT = 8'hAC; + LUT3_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_0_0_14_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_d32_sw[14]), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_d32_sw[30]), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_rem_pipe_5079[0]), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_5980) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_0_0_15_.INIT = 8'hAC; + LUT3_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_0_0_15_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_d32_sw[15]), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_d32_sw[31]), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_rem_pipe_5079[0]), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_5981) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_0_0_16_.INIT = 8'hAC; + LUT3_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_0_0_16_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_d32_sw[16]), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_d64_sw_32_), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_rem_pipe_5079[0]), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_5982) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_0_0_17_.INIT = 8'hAC; + LUT3_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_0_0_17_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_d32_sw[17]), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_d64_sw_33_), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_rem_pipe_5079[0]), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_5983) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_0_0_18_.INIT = 8'hAC; + LUT3_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_0_0_18_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_d32_sw[18]), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_d64_sw_34_), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_rem_pipe_5079[0]), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_5984) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_0_0_19_.INIT = 8'hAC; + LUT3_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_0_0_19_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_d32_sw[19]), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_d64_sw_35_), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_rem_pipe_5079[0]), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_5985) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_0_0_20_.INIT = 8'hAC; + LUT3_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_0_0_20_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_d32_sw[20]), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_d64_sw_36_), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_rem_pipe_5079[0]), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_5986) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_0_0_21_.INIT = 8'hAC; + LUT3_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_0_0_21_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_d32_sw[21]), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_d64_sw_37_), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_rem_pipe_5079[0]), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_5987) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_0_0_22_.INIT = 8'hAC; + LUT3_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_0_0_22_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_d32_sw[22]), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_d64_sw_38_), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_rem_pipe_5079[0]), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_5988) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_0_0_23_.INIT = 8'hAC; + LUT3_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_0_0_23_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_d32_sw[23]), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_d64_sw_39_), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_rem_pipe_5079[0]), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_5989) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_0_0_24_.INIT = 8'hAC; + LUT3_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_0_0_24_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_d32_sw[24]), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_d64_sw_40_), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_rem_pipe_5079[0]), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_5990) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_0_0_25_.INIT = 8'hAC; + LUT3_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_0_0_25_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_d32_sw[25]), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_d64_sw_41_), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_rem_pipe_5079[0]), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_5991) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_0_0_26_.INIT = 8'hAC; + LUT3_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_0_0_26_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_d32_sw[26]), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_d64_sw_42_), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_rem_pipe_5079[0]), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_5992) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_0_0_27_.INIT = 8'hAC; + LUT3_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_0_0_27_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_d32_sw[27]), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_d64_sw_43_), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_rem_pipe_5079[0]), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_5993) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_0_0_28_.INIT = 8'hAC; + LUT3_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_0_0_28_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_d32_sw[28]), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_d64_sw_44_), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_rem_pipe_5079[0]), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_5994) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_0_0_29_.INIT = 8'hAC; + LUT3_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_0_0_29_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_d32_sw[29]), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_d64_sw_45_), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_rem_pipe_5079[0]), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_5995) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_0_0_30_.INIT = 8'hAC; + LUT3_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_0_0_30_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_d32_sw[30]), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_d64_sw_46_), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_rem_pipe_5079[0]), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_5996) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_0_0_31_.INIT = 8'hAC; + LUT3_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_0_0_31_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_d32_sw[31]), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_d64_sw_47_), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_rem_pipe_5079[0]), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_5997) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_0_0_40_.INIT = 16'hCAC0; + LUT4_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_0_0_40_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_d16_sw[8]), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_d64_sw_40_), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_rem_pipe_5079[0]), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_sof_n_pipe[0]), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_6006) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_0_0_41_.INIT = 8'hAC; + LUT3_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_0_0_41_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_d64_sw_41_), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_d64_sw_57_), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_rem_pipe_5079[0]), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_6007) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_0_0_42_.INIT = 16'hCAC0; + LUT4_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_0_0_42_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_d16_sw[10]), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_d64_sw_42_), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_rem_pipe_5079[0]), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_sof_n_pipe[0]), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_6008) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_0_0_43_.INIT = 16'hCAC0; + LUT4_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_0_0_43_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_d16_sw[11]), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_d64_sw_43_), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_rem_pipe_5079[0]), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_sof_n_pipe[0]), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_6009) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_0_0_32_.INIT = 8'hAC; + LUT3_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_0_0_32_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_d64_sw_32_), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_d64_sw_48_), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_rem_pipe_5079[0]), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_5998) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_0_0_33_.INIT = 8'hAC; + LUT3_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_0_0_33_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_d64_sw_33_), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_d64_sw_49_), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_rem_pipe_5079[0]), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_5999) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_0_0_34_.INIT = 8'hAC; + LUT3_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_0_0_34_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_d64_sw_34_), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_d64_sw_50_), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_rem_pipe_5079[0]), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_6000) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_0_0_35_.INIT = 8'hAC; + LUT3_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_0_0_35_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_d64_sw_35_), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_d64_sw_51_), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_rem_pipe_5079[0]), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_6001) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_0_0_36_.INIT = 8'hAC; + LUT3_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_0_0_36_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_d64_sw_36_), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_d64_sw_52_), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_rem_pipe_5079[0]), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_6002) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_0_0_37_.INIT = 8'hAC; + LUT3_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_0_0_37_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_d64_sw_37_), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_d64_sw_53_), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_rem_pipe_5079[0]), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_6003) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_0_0_38_.INIT = 8'hAC; + LUT3_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_0_0_38_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_d64_sw_38_), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_d64_sw_54_), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_rem_pipe_5079[0]), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_6004) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_0_0_39_.INIT = 8'hAC; + LUT3_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_0_0_39_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_d64_sw_39_), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_d64_sw_55_), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_rem_pipe_5079[0]), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_6005) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_0_0_44_.INIT = 8'hAC; + LUT3_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_0_0_44_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_d64_sw_44_), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_d64_sw_60_), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_rem_pipe_5079[0]), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_6010) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_0_0_45_.INIT = 8'hAC; + LUT3_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_0_0_45_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_d64_sw_45_), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_d64_sw_61_), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_rem_pipe_5079[0]), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_6011) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_0_0_46_.INIT = 8'hAC; + LUT3_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_0_0_46_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_d64_sw_46_), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_d64_sw_62_), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_rem_pipe_5079[0]), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_6012) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_0_0_47_.INIT = 8'hAC; + LUT3_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_0_0_47_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_d64_sw_47_), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_d64_sw_63_), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_rem_pipe_5079[0]), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_6013) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_am_1_.INIT = 8'h96; + LUT3 com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_am_1_ ( + .I0(N_45), + .I1(N_104), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_d64_c_q_1__1238), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_am_1__1116) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_bm_1_.INIT = 16'h6996; + LUT4 com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_bm_1_ ( + .I0(N_71), + .I1(N_83), + .I2(N_10491), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_new_c48_1_1_1_), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_bm_1__1115) + ); + MUXF5 com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_1_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_am_1__1116), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_bm_1__1115), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4[1]), + .S(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crcdatawidth_qq[2]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_am_6_.INIT = 16'h6996; + LUT4 com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_am_6_ ( + .I0(N_43), + .I1(N_85), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[24]), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_d64_c_q_6__1235), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_am_6__1118) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_bm_6_.INIT = 16'h6996; + LUT4 com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_bm_6_ ( + .I0(N_69), + .I1(N_97), + .I2(N_166), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_new_c48_1_1_6_), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_bm_6__1117) + ); + MUXF5 com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_6_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_am_6__1118), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_bm_6__1117), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4[6]), + .S(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crcdatawidth_qq[2]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_am_10_.INIT = 16'h6996; + LUT4 com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_am_10_ ( + .I0(N_10492), + .I1(N_10604), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[25]), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_d64_c_q_10__1231), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_am_10__1120) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_bm_10_.INIT = 16'h6996; + LUT4 com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_bm_10_ ( + .I0(N_47), + .I1(N_81), + .I2(N_10493), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_new_c48_1_1_10_), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_bm_10__1119) + ); + MUXF5 com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_10_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_am_10__1120), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_bm_10__1119), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4[10]), + .S(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crcdatawidth_qq[2]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_am_12_.INIT = 16'h6996; + LUT4 com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_am_12_ ( + .I0(N_68), + .I1(N_80), + .I2(N_95), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_d64_c_q_12__1229), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_am_12__1122) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_bm_12_.INIT = 16'h6996; + LUT4 com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_bm_12_ ( + .I0(N_10613), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_d64_c_q_12__1229), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_new_c48_1_2_12_), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_new_c32_d48_1_12_), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_bm_12__1121) + ); + MUXF5 com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_12_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_am_12__1122), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_bm_12__1121), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4[12]), + .S(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crcdatawidth_qq[2]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_am_13_.INIT = 8'h96; + LUT3 com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_am_13_ ( + .I0(N_43), + .I1(N_10492), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_new_c16_1_1_13_), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_am_13__1123) + ); + MUXF5 com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_13_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_am_13__1123), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_bm_13__1208), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4[13]), + .S(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crcdatawidth_qq[2]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_bm_14_.INIT = 16'h6996; + LUT4 com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_bm_14_ ( + .I0(N_82), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[28]), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_new_c48_1_0_14_), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_new_c48_1_2_14_), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_bm_14__1124) + ); + MUXF5 com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_14_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_am_14__1172), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_bm_14__1124), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4[14]), + .S(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crcdatawidth_qq[2]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_am_15_.INIT = 16'h6996; + LUT4 com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_am_15_ ( + .I0(N_44), + .I1(N_111), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[25]), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_d64_c_q_15__1226), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_am_15__1126) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_bm_15_.INIT = 8'h96; + LUT3 com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_bm_15_ ( + .I0(N_10596), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_new_c48_1_1_15_), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_new_c48_1_3_15_), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_bm_15__1125) + ); + MUXF5 com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_15_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_am_15__1126), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_bm_15__1125), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4[15]), + .S(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crcdatawidth_qq[2]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_am_16_.INIT = 8'h96; + LUT3 com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_am_16_ ( + .I0(N_102), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[0]), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_new_c16_1_1_16_), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_am_16__1127) + ); + MUXF5 com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_16_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_am_16__1127), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_bm_16__1206), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4[16]), + .S(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crcdatawidth_qq[2]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_am_17_.INIT = 16'h6996; + LUT4 com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_am_17_ ( + .I0(N_80), + .I1(N_152), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[22]), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_d64_c_q_17__1224), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_am_17__1129) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_bm_17_.INIT = 16'h6996; + LUT4 com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_bm_17_ ( + .I0(N_69), + .I1(N_110), + .I2(N_10596), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_new_c48_1_2_17_), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_bm_17__1128) + ); + MUXF5 com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_17_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_am_17__1129), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_bm_17__1128), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4[17]), + .S(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crcdatawidth_qq[2]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_am_18_.INIT = 8'h96; + LUT3 com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_am_18_ ( + .I0(N_43), + .I1(N_72), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_d64_c_q_18__1223), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_am_18__1131) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_bm_18_.INIT = 16'h6996; + LUT4 com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_bm_18_ ( + .I0(N_46), + .I1(N_10604), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[3]), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_new_c48_1_1_18_), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_bm_18__1130) + ); + MUXF5 com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_18_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_am_18__1131), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_bm_18__1130), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4[18]), + .S(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crcdatawidth_qq[2]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_am_19_.INIT = 16'h6996; + LUT4 com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_am_19_ ( + .I0(N_44), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[3]), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[27]), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_d64_c_q_19__1222), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_am_19__1133) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_bm_19_.INIT = 16'h6996; + LUT4 com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_bm_19_ ( + .I0(N_69), + .I1(N_81_1), + .I2(N_83), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_new_c48_1_1_19_), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_bm_19__1132) + ); + MUXF5 com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_19_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_am_19__1133), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_bm_19__1132), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4[19]), + .S(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crcdatawidth_qq[2]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_am_20_.INIT = 16'h6996; + LUT4 com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_am_20_ ( + .I0(N_100), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[4]), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[25]), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_d64_c_q_20__1221), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_am_20__1135) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_bm_20_.INIT = 16'h6996; + LUT4 com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_bm_20_ ( + .I0(N_47), + .I1(N_84), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_new_c48_1_2_20_), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_new_c32_d16_1_25_), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_bm_20__1134) + ); + MUXF5 com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_20_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_am_20__1135), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_bm_20__1134), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4[20]), + .S(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crcdatawidth_qq[2]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_am_21_.INIT = 16'h6996; + LUT4 com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_am_21_ ( + .I0(N_10361), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[21]), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[26]), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_d64_c_q_21__1220), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_am_21__1137) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_bm_21_.INIT = 16'h6996; + LUT4 com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_bm_21_ ( + .I0(N_98), + .I1(N_119), + .I2(N_10493), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_new_c48_1_1_21_), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_bm_21__1136) + ); + MUXF5 com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_21_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_am_21__1137), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_bm_21__1136), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4[21]), + .S(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crcdatawidth_qq[2]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_am_27_.INIT = 16'h6996; + LUT4 com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_am_27_ ( + .I0(N_85), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[11]), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[23]), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_d64_c_q_27__1214), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_am_27__1139) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_bm_27_.INIT = 16'h6996; + LUT4 com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_bm_27_ ( + .I0(N_48), + .I1(N_99), + .I2(N_103), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_new_c48_1_2_27_), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_bm_27__1138) + ); + MUXF5 com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_27_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_am_27__1139), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_bm_27__1138), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4[27]), + .S(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crcdatawidth_qq[2]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_am_28_.INIT = 16'h6996; + LUT4 com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_am_28_ ( + .I0(N_95), + .I1(N_10534), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[24]), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_d64_c_q_28__1213), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_am_28__1141) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_bm_28_.INIT = 16'h6996; + LUT4 com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_bm_28_ ( + .I0(N_84), + .I1(N_98), + .I2(N_139), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_new_c48_1_2_28_), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_bm_28__1140) + ); + MUXF5 com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_28_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_am_28__1141), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_bm_28__1140), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4[28]), + .S(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crcdatawidth_qq[2]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_am_30_.INIT = 16'h6996; + LUT4 com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_am_30_ ( + .I0(N_49), + .I1(N_101), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[14]), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_d64_c_q_30__1211), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_am_30__1143) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_bm_30_.INIT = 16'h6996; + LUT4 com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_bm_30_ ( + .I0(N_103), + .I1(N_151), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_new_c48_1_0_30_), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_new_c48_1_1_30_), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_bm_30__1142) + ); + MUXF5 com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_30_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_am_30__1143), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_bm_30__1142), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4[30]), + .S(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crcdatawidth_qq[2]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_am_0_.INIT = 16'h6996; + LUT4 com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_am_0_ ( + .I0(N_10355), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[25]), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[28]), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_d64_c_q_0__1239), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_am_0__1145) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_bm_0_.INIT = 16'h6996; + LUT4 com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_bm_0_ ( + .I0(N_102), + .I1(N_10566), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[0]), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_new_c48_1_2_0_), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_bm_0__1144) + ); + MUXF5 com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_0_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_am_0__1145), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_bm_0__1144), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4[0]), + .S(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crcdatawidth_qq[2]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_am_2_.INIT = 16'h6996; + LUT4 com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_am_2_ ( + .I0(N_43), + .I1(N_80), + .I2(N_105), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[24]), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_am_2__1147) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_bm_2_.INIT = 8'h96; + LUT3 com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_bm_2_ ( + .I0(N_47), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_new_c48_1_1_2_), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_new_c32_d48_1_2_), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_bm_2__1146) + ); + MUXF5 com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_2_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_am_2__1147), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_bm_2__1146), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4[2]), + .S(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crcdatawidth_qq[2]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_am_3_.INIT = 8'h96; + LUT3 com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_am_3_ ( + .I0(N_86), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_d64_c_q_3__1237), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_new_c32_d16_1_3_), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_am_3__1149) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_bm_3_.INIT = 16'h6996; + LUT4 com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_bm_3_ ( + .I0(N_45), + .I1(N_99), + .I2(N_102), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_new_c48_1_2_3_), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_bm_3__1148) + ); + MUXF5 com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_3_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_am_3__1149), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_bm_3__1148), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4[3]), + .S(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crcdatawidth_qq[2]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_am_4_.INIT = 16'h6996; + LUT4 com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_am_4_ ( + .I0(N_68), + .I1(N_121), + .I2(N_10491), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_new_c16_1_0[4]), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_am_4__1151) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_bm_4_.INIT = 16'h6996; + LUT4 com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_bm_4_ ( + .I0(N_45), + .I1(N_97), + .I2(N_10520), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_new_c48_1_1_4_), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_bm_4__1150) + ); + MUXF5 com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_4_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_am_4__1151), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_bm_4__1150), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4[4]), + .S(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crcdatawidth_qq[2]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_am_5_.INIT = 16'h6996; + LUT4 com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_am_5_ ( + .I0(N_45), + .I1(N_102), + .I2(N_10490), + .I3(N_10538), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_am_5__1153) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_bm_5_.INIT = 16'h6996; + LUT4 com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_bm_5_ ( + .I0(N_46), + .I1(N_97), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[3]), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_new_c48_1_1_5_), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_bm_5__1152) + ); + MUXF5 com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_5_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_am_5__1153), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_bm_5__1152), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4[5]), + .S(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crcdatawidth_qq[2]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_am_7_.INIT = 8'h96; + LUT3 com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_am_7_ ( + .I0(N_102), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_d64_c_q_7__1234), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_new_c32_d16_1_3_), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_am_7__1155) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_bm_7_.INIT = 16'h6996; + LUT4 com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_bm_7_ ( + .I0(N_46), + .I1(N_103), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_new_c48_1_1_7_), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_new_c48_1_3_7_), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_bm_7__1154) + ); + MUXF5 com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_7_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_am_7__1155), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_bm_7__1154), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4[7]), + .S(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crcdatawidth_qq[2]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_am_9_.INIT = 16'h6996; + LUT4 com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_am_9_ ( + .I0(N_80), + .I1(N_111), + .I2(N_121), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_d64_c_q_9__1232), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_am_9__1157) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_bm_9_.INIT = 16'h6996; + LUT4 com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_bm_9_ ( + .I0(N_43), + .I1(N_68), + .I2(N_82), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_new_c48_1_0_9_), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_bm_9__1156) + ); + MUXF5 com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_9_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_am_9__1157), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_bm_9__1156), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4[9]), + .S(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crcdatawidth_qq[2]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_am_11_.INIT = 16'h6996; + LUT4 com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_am_11_ ( + .I0(N_68), + .I1(N_86), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[19]), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_d64_c_q_11__1230), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_am_11__1159) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_bm_11_.INIT = 16'h6996; + LUT4 com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_bm_11_ ( + .I0(N_67), + .I1(N_80), + .I2(N_98), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_new_c48_1_1_11_), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_bm_11__1158) + ); + MUXF5 com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_11_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_am_11__1159), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_bm_11__1158), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4[11]), + .S(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crcdatawidth_qq[2]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_am_22_.INIT = 16'h6996; + LUT4 com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_am_22_ ( + .I0(N_104), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[6]), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[30]), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_d64_c_q_22__1219), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_am_22__1161) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_bm_22_.INIT = 16'h6996; + LUT4 com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_bm_22_ ( + .I0(N_70), + .I1(N_110), + .I2(N_10494), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_new_c48_1_3_22_), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_bm_22__1160) + ); + MUXF5 com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_22_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_am_22__1161), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_bm_22__1160), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4[22]), + .S(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crcdatawidth_qq[2]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_am_23_.INIT = 8'h96; + LUT3 com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_am_23_ ( + .I0(N_80), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[22]), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_new_c16_1_1_23_), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_am_23__1163) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_bm_23_.INIT = 16'h6996; + LUT4 com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_bm_23_ ( + .I0(N_43), + .I1(N_109), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[11]), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_new_c48_1_2_23_), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_bm_23__1162) + ); + MUXF5 com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_23_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_am_23__1163), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_bm_23__1162), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4[23]), + .S(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crcdatawidth_qq[2]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_am_24_.INIT = 4'h6; + LUT2 com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_am_24_ ( + .I0(N_49), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_new_c16_1_2[24]), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_am_24__1165) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_bm_24_.INIT = 16'h6996; + LUT4 com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_bm_24_ ( + .I0(N_109), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[11]), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_new_c48_1_2_24_), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_new_c48_1_3_24_), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_bm_24__1164) + ); + MUXF5 com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_24_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_am_24__1165), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_bm_24__1164), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4[24]), + .S(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crcdatawidth_qq[2]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_am_25_.INIT = 16'h6996; + LUT4 com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_am_25_ ( + .I0(N_73), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[19]), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_d64_c_q_25__1216), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_new_c32_d16_1_25_), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_am_25__1167) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_bm_25_.INIT = 16'h6996; + LUT4 com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_bm_25_ ( + .I0(N_84), + .I1(N_101), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_new_c48_1_1_25_), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_new_c32_d48_1_2_), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_bm_25__1166) + ); + MUXF5 com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_25_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_am_25__1167), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_bm_25__1166), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4[25]), + .S(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crcdatawidth_qq[2]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_am_26_.INIT = 16'h6996; + LUT4 com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_am_26_ ( + .I0(N_10355), + .I1(N_10490), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[10]), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_d64_c_q_26__1215), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_am_26__1169) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_bm_26_.INIT = 16'h6996; + LUT4 com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_bm_26_ ( + .I0(N_48), + .I1(N_94), + .I2(N_10520), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_new_c48_1_1_26_), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_bm_26__1168) + ); + MUXF5 com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_26_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_am_26__1169), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_bm_26__1168), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4[26]), + .S(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crcdatawidth_qq[2]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_am_29_.INIT = 16'h6996; + LUT4 com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_am_29_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[13]), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[25]), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[29]), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_new_c16_1_1_29_), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_am_29__1171) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_bm_29_.INIT = 8'h96; + LUT3 com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_bm_29_ ( + .I0(N_119), + .I1(N_10566), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_new_c48_1_2_29_), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_bm_29__1170) + ); + MUXF5 com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_29_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_am_29__1171), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_bm_29__1170), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4[29]), + .S(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crcdatawidth_qq[2]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_am_14_.INIT = 16'h6996; + LUT4 com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_am_14_ ( + .I0(N_43), + .I1(N_73), + .I2(N_10490), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_d64_c_q_14__1227), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_am_14__1172) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_31_.INIT = 16'h7B48; + LUT4_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_31_ ( + .I0(N_10566), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crcdatawidth_qq[2]), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_new_c48_1_2_31_), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_new_c32_d16[31]), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4[31]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_8_.INIT = 16'h1BE4; + LUT4_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_8_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crcdatawidth_qq[2]), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_new_c16_1_1_8_), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_new_c48_1_3_8_), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_new_c32_d16_1_8_), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4[8]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_22303_i.INIT = 4'hE; + LUT2_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_22303_i ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crcint_qq_1205), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_new_c32_d64[31]), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_22303_i_1173) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_22304_i.INIT = 4'hE; + LUT2_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_22304_i ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crcint_qq_1205), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_new_c32_d64[30]), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_22304_i_1174) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_22305_i.INIT = 4'hE; + LUT2_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_22305_i ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crcint_qq_1205), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_new_c32_d64[29]), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_22305_i_1175) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_22306_i.INIT = 4'hE; + LUT2_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_22306_i ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crcint_qq_1205), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_new_c32_d64[28]), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_22306_i_1176) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_22307_i.INIT = 4'hE; + LUT2_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_22307_i ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crcint_qq_1205), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_new_c32_d64[27]), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_22307_i_1177) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_22308_i.INIT = 4'hE; + LUT2_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_22308_i ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crcint_qq_1205), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_new_c32_d64[26]), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_22308_i_1178) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_22309_i.INIT = 4'hE; + LUT2_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_22309_i ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crcint_qq_1205), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_new_c32_d64[25]), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_22309_i_1179) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_22310_i.INIT = 4'hE; + LUT2_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_22310_i ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crcint_qq_1205), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_new_c32_d64[24]), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_22310_i_1180) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_22311_i.INIT = 4'hE; + LUT2_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_22311_i ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crcint_qq_1205), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_new_c32_d64[23]), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_22311_i_1181) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_22312_i.INIT = 4'hE; + LUT2_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_22312_i ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crcint_qq_1205), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_new_c32_d64[22]), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_22312_i_1182) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_22313_i.INIT = 4'hE; + LUT2_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_22313_i ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crcint_qq_1205), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_new_c32_d64[21]), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_22313_i_1183) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_22314_i.INIT = 4'hE; + LUT2_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_22314_i ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crcint_qq_1205), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_new_c32_d64[20]), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_22314_i_1184) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_22315_i.INIT = 4'hE; + LUT2_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_22315_i ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crcint_qq_1205), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_new_c32_d64[19]), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_22315_i_1185) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_22335_i.INIT = 4'hE; + LUT2_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_22335_i ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crcint_qq_1205), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_new_c32_d64[18]), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_22335_i_1186) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_22336_i.INIT = 4'hE; + LUT2_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_22336_i ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crcint_qq_1205), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_new_c32_d64[17]), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_22336_i_1187) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_22337_i.INIT = 4'hE; + LUT2_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_22337_i ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crcint_qq_1205), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_new_c32_d64[16]), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_22337_i_1188) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_22338_i.INIT = 4'hE; + LUT2_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_22338_i ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crcint_qq_1205), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_new_c32_d64[15]), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_22338_i_1189) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_22339_i.INIT = 4'hE; + LUT2_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_22339_i ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crcint_qq_1205), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_new_c32_d64[14]), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_22339_i_1190) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_22340_i.INIT = 4'hE; + LUT2_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_22340_i ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crcint_qq_1205), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_new_c32_d64[13]), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_22340_i_1191) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_22341_i.INIT = 4'hE; + LUT2_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_22341_i ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crcint_qq_1205), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_new_c32_d64[12]), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_22341_i_1192) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_22342_i.INIT = 4'hE; + LUT2_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_22342_i ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crcint_qq_1205), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_new_c32_d64[11]), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_22342_i_1193) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_22343_i.INIT = 4'hE; + LUT2_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_22343_i ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crcint_qq_1205), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_new_c32_d64[10]), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_22343_i_1194) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_22344_i.INIT = 4'hE; + LUT2_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_22344_i ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crcint_qq_1205), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_new_c32_d64[9]), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_22344_i_1195) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_22345_i.INIT = 4'hE; + LUT2_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_22345_i ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crcint_qq_1205), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_new_c32_d64[8]), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_22345_i_1196) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_22346_i.INIT = 4'hE; + LUT2_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_22346_i ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crcint_qq_1205), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_new_c32_d64[7]), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_22346_i_1197) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_22347_i.INIT = 4'hE; + LUT2_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_22347_i ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crcint_qq_1205), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_new_c32_d64[6]), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_22347_i_1198) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_22316_i.INIT = 4'hE; + LUT2_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_22316_i ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crcint_qq_1205), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_new_c32_d64[5]), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_22316_i_1199) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_22317_i.INIT = 4'hE; + LUT2_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_22317_i ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crcint_qq_1205), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_new_c32_d64[4]), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_22317_i_1200) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_22318_i.INIT = 4'hE; + LUT2_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_22318_i ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crcint_qq_1205), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_new_c32_d64[3]), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_22318_i_1201) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_22319_i.INIT = 4'hE; + LUT2_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_22319_i ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crcint_qq_1205), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_new_c32_d64[2]), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_22319_i_1202) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_22320_i.INIT = 4'hE; + LUT2_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_22320_i ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crcint_qq_1205), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_new_c32_d64[1]), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_22320_i_1203) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_22321_i.INIT = 4'hE; + LUT2_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_22321_i ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crcint_qq_1205), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_new_c32_d64[0]), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_22321_i_1204) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_0_63_.INIT = 8'hD8; + LUT3_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_0_63_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_crcdatawidth[1]), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_d64_sw_63_), + .I2(com_reset_i_q), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6[63]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_0_62_.INIT = 8'hD8; + LUT3_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_0_62_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_crcdatawidth[1]), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_d64_sw_62_), + .I2(com_reset_i_q), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6[62]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_0_61_.INIT = 8'hD8; + LUT3_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_0_61_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_crcdatawidth[1]), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_d64_sw_61_), + .I2(com_reset_i_q), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6[61]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_0_60_.INIT = 8'hD8; + LUT3_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_0_60_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_crcdatawidth[1]), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_d64_sw_60_), + .I2(com_reset_i_q), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6[60]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_0_59_.INIT = 16'hD580; + LUT4_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_0_59_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_crcdatawidth[1]), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_d16_sw[11]), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_sof_n_pipe[0]), + .I3(com_reset_i_q), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6[59]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_0_58_.INIT = 16'hD580; + LUT4_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_0_58_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_crcdatawidth[1]), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_d16_sw[10]), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_sof_n_pipe[0]), + .I3(com_reset_i_q), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6[58]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_0_57_.INIT = 8'hD8; + LUT3_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_0_57_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_crcdatawidth[1]), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_d64_sw_57_), + .I2(com_reset_i_q), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6[57]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_0_56_.INIT = 16'hD580; + LUT4_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_0_56_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_crcdatawidth[1]), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_d16_sw[8]), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_sof_n_pipe[0]), + .I3(com_reset_i_q), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6[56]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_0_55_.INIT = 8'hD8; + LUT3_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_0_55_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_crcdatawidth[1]), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_d64_sw_55_), + .I2(com_reset_i_q), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6[55]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_0_54_.INIT = 8'hD8; + LUT3_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_0_54_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_crcdatawidth[1]), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_d64_sw_54_), + .I2(com_reset_i_q), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6[54]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_0_53_.INIT = 8'hD8; + LUT3_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_0_53_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_crcdatawidth[1]), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_d64_sw_53_), + .I2(com_reset_i_q), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6[53]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_0_52_.INIT = 8'hD8; + LUT3_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_0_52_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_crcdatawidth[1]), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_d64_sw_52_), + .I2(com_reset_i_q), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6[52]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_0_51_.INIT = 8'hD8; + LUT3_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_0_51_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_crcdatawidth[1]), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_d64_sw_51_), + .I2(com_reset_i_q), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6[51]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_0_50_.INIT = 8'hD8; + LUT3_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_0_50_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_crcdatawidth[1]), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_d64_sw_50_), + .I2(com_reset_i_q), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6[50]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_0_49_.INIT = 8'hD8; + LUT3_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_0_49_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_crcdatawidth[1]), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_d64_sw_49_), + .I2(com_reset_i_q), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6[49]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_0_48_.INIT = 8'hD8; + LUT3_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_0_48_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_crcdatawidth[1]), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_d64_sw_48_), + .I2(com_reset_i_q), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6[48]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_0_47_.INIT = 8'hB8; + LUT3_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_0_47_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_6013), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_eof_n_pipe_5078[1]), + .I2(com_reset_i_q), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6[47]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_0_46_.INIT = 8'hB8; + LUT3_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_0_46_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_6012), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_eof_n_pipe_5078[1]), + .I2(com_reset_i_q), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6[46]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_0_45_.INIT = 8'hB8; + LUT3_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_0_45_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_6011), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_eof_n_pipe_5078[1]), + .I2(com_reset_i_q), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6[45]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_0_44_.INIT = 8'hB8; + LUT3_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_0_44_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_6010), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_eof_n_pipe_5078[1]), + .I2(com_reset_i_q), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6[44]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_0_43_.INIT = 8'hB8; + LUT3_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_0_43_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_6009), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_eof_n_pipe_5078[1]), + .I2(com_reset_i_q), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6[43]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_0_42_.INIT = 8'hB8; + LUT3_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_0_42_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_6008), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_eof_n_pipe_5078[1]), + .I2(com_reset_i_q), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6[42]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_0_41_.INIT = 8'hB8; + LUT3_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_0_41_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_6007), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_eof_n_pipe_5078[1]), + .I2(com_reset_i_q), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6[41]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_0_40_.INIT = 8'hB8; + LUT3_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_0_40_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_6006), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_eof_n_pipe_5078[1]), + .I2(com_reset_i_q), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6[40]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_0_39_.INIT = 8'hB8; + LUT3_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_0_39_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_6005), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_eof_n_pipe_5078[1]), + .I2(com_reset_i_q), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6[39]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_0_38_.INIT = 8'hB8; + LUT3_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_0_38_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_6004), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_eof_n_pipe_5078[1]), + .I2(com_reset_i_q), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6[38]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_0_37_.INIT = 8'hB8; + LUT3_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_0_37_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_6003), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_eof_n_pipe_5078[1]), + .I2(com_reset_i_q), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6[37]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_0_36_.INIT = 8'hB8; + LUT3_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_0_36_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_6002), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_eof_n_pipe_5078[1]), + .I2(com_reset_i_q), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6[36]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_0_35_.INIT = 8'hB8; + LUT3_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_0_35_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_6001), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_eof_n_pipe_5078[1]), + .I2(com_reset_i_q), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6[35]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_0_34_.INIT = 8'hB8; + LUT3_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_0_34_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_6000), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_eof_n_pipe_5078[1]), + .I2(com_reset_i_q), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6[34]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_0_33_.INIT = 8'hB8; + LUT3_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_0_33_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_5999), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_eof_n_pipe_5078[1]), + .I2(com_reset_i_q), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6[33]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_0_32_.INIT = 8'hB8; + LUT3_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_0_32_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_5998), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_eof_n_pipe_5078[1]), + .I2(com_reset_i_q), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6[32]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_0_31_.INIT = 8'hB8; + LUT3_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_0_31_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_5997), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_eof_n_pipe_5078[1]), + .I2(com_reset_i_q), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6[31]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_0_30_.INIT = 8'hB8; + LUT3_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_0_30_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_5996), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_eof_n_pipe_5078[1]), + .I2(com_reset_i_q), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6[30]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_0_29_.INIT = 8'hB8; + LUT3_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_0_29_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_5995), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_eof_n_pipe_5078[1]), + .I2(com_reset_i_q), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6[29]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_0_28_.INIT = 8'hB8; + LUT3_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_0_28_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_5994), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_eof_n_pipe_5078[1]), + .I2(com_reset_i_q), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6[28]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_0_27_.INIT = 8'hB8; + LUT3_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_0_27_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_5993), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_eof_n_pipe_5078[1]), + .I2(com_reset_i_q), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6[27]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_0_26_.INIT = 8'hB8; + LUT3_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_0_26_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_5992), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_eof_n_pipe_5078[1]), + .I2(com_reset_i_q), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6[26]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_0_25_.INIT = 8'hB8; + LUT3_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_0_25_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_5991), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_eof_n_pipe_5078[1]), + .I2(com_reset_i_q), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6[25]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_0_24_.INIT = 8'hB8; + LUT3_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_0_24_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_5990), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_eof_n_pipe_5078[1]), + .I2(com_reset_i_q), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6[24]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_0_23_.INIT = 8'hB8; + LUT3_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_0_23_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_5989), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_eof_n_pipe_5078[1]), + .I2(com_reset_i_q), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6[23]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_0_22_.INIT = 8'hB8; + LUT3_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_0_22_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_5988), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_eof_n_pipe_5078[1]), + .I2(com_reset_i_q), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6[22]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_0_21_.INIT = 8'hB8; + LUT3_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_0_21_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_5987), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_eof_n_pipe_5078[1]), + .I2(com_reset_i_q), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6[21]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_0_20_.INIT = 8'hB8; + LUT3_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_0_20_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_5986), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_eof_n_pipe_5078[1]), + .I2(com_reset_i_q), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6[20]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_0_19_.INIT = 8'hB8; + LUT3_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_0_19_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_5985), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_eof_n_pipe_5078[1]), + .I2(com_reset_i_q), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6[19]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_0_18_.INIT = 8'hB8; + LUT3_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_0_18_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_5984), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_eof_n_pipe_5078[1]), + .I2(com_reset_i_q), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6[18]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_0_17_.INIT = 8'hB8; + LUT3_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_0_17_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_5983), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_eof_n_pipe_5078[1]), + .I2(com_reset_i_q), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6[17]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_0_16_.INIT = 8'hB8; + LUT3_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_0_16_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_5982), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_eof_n_pipe_5078[1]), + .I2(com_reset_i_q), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6[16]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_0_15_.INIT = 8'hAC; + LUT3_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_0_15_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_5981), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_d16_sw[15]), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_eof_n_pipe_5078[1]), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6[15]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_0_14_.INIT = 8'hAC; + LUT3_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_0_14_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_5980), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_d16_sw[14]), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_eof_n_pipe_5078[1]), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6[14]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_0_13_.INIT = 8'hAC; + LUT3_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_0_13_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_5979), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_d16_sw[13]), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_eof_n_pipe_5078[1]), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6[13]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_0_12_.INIT = 8'hAC; + LUT3_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_0_12_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_5978), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_d16_sw[12]), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_eof_n_pipe_5078[1]), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6[12]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_0_11_.INIT = 8'hAC; + LUT3_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_0_11_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_5977), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_d16_sw[11]), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_eof_n_pipe_5078[1]), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6[11]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_0_10_.INIT = 8'hAC; + LUT3_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_0_10_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_5976), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_d16_sw[10]), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_eof_n_pipe_5078[1]), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6[10]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_0_9_.INIT = 8'hAC; + LUT3_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_0_9_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_5975), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_d16_sw[9]), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_eof_n_pipe_5078[1]), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6[9]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_0_8_.INIT = 8'hAC; + LUT3_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_0_8_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_5974), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_d16_sw[8]), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_eof_n_pipe_5078[1]), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6[8]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_0_7_.INIT = 8'hAC; + LUT3_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_0_7_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_5973), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_d16_sw[7]), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_eof_n_pipe_5078[1]), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6[7]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_0_6_.INIT = 8'hAC; + LUT3_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_0_6_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_5972), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_d16_sw[6]), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_eof_n_pipe_5078[1]), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6[6]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_0_5_.INIT = 8'hAC; + LUT3_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_0_5_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_5971), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_d16_sw[5]), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_eof_n_pipe_5078[1]), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6[5]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_0_4_.INIT = 8'hAC; + LUT3_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_0_4_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_5970), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_d16_sw[4]), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_eof_n_pipe_5078[1]), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6[4]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_0_3_.INIT = 8'hAC; + LUT3_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_0_3_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_5969), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_d16_sw[3]), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_eof_n_pipe_5078[1]), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6[3]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_0_2_.INIT = 8'hAC; + LUT3_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_0_2_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_5968), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_d16_sw[2]), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_eof_n_pipe_5078[1]), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6[2]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_0_1_.INIT = 8'hAC; + LUT3_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_0_1_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_5967), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_d16_sw[1]), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_eof_n_pipe_5078[1]), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6[1]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_0_0_.INIT = 8'hAC; + LUT3_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_0_0_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_5966), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_d16_sw[0]), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_eof_n_pipe_5078[1]), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6[0]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_sw_early_crc_i_23_.INIT = 4'h1; + LUT1_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_sw_early_crc_i_23_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_sw_early_crc[23]), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_sw_early_crc_i[23]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_sw_early_crc_i_22_.INIT = 4'h1; + LUT1_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_sw_early_crc_i_22_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_sw_early_crc[22]), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_sw_early_crc_i[22]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_sw_early_crc_i_21_.INIT = 4'h1; + LUT1_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_sw_early_crc_i_21_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_sw_early_crc[21]), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_sw_early_crc_i[21]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_sw_early_crc_i_20_.INIT = 4'h1; + LUT1_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_sw_early_crc_i_20_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_sw_early_crc[20]), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_sw_early_crc_i[20]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_sw_early_crc_i_19_.INIT = 4'h1; + LUT1_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_sw_early_crc_i_19_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_sw_early_crc[19]), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_sw_early_crc_i[19]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_sw_early_crc_i_18_.INIT = 4'h1; + LUT1_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_sw_early_crc_i_18_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_sw_early_crc[18]), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_sw_early_crc_i[18]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_sw_early_crc_i_17_.INIT = 4'h1; + LUT1_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_sw_early_crc_i_17_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_sw_early_crc[17]), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_sw_early_crc_i[17]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_sw_early_crc_i_16_.INIT = 4'h1; + LUT1_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_sw_early_crc_i_16_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_sw_early_crc[16]), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_sw_early_crc_i[16]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_sw_early_crc_i_15_.INIT = 4'h1; + LUT1_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_sw_early_crc_i_15_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_sw_early_crc[15]), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_sw_early_crc_i[15]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_sw_early_crc_i_14_.INIT = 4'h1; + LUT1_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_sw_early_crc_i_14_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_sw_early_crc[14]), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_sw_early_crc_i[14]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_sw_early_crc_i_13_.INIT = 4'h1; + LUT1_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_sw_early_crc_i_13_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_sw_early_crc[13]), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_sw_early_crc_i[13]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_sw_early_crc_i_12_.INIT = 4'h1; + LUT1_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_sw_early_crc_i_12_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_sw_early_crc[12]), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_sw_early_crc_i[12]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_sw_early_crc_i_11_.INIT = 4'h1; + LUT1_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_sw_early_crc_i_11_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_sw_early_crc[11]), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_sw_early_crc_i[11]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_sw_early_crc_i_10_.INIT = 4'h1; + LUT1_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_sw_early_crc_i_10_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_sw_early_crc[10]), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_sw_early_crc_i[10]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_sw_early_crc_i_9_.INIT = 4'h1; + LUT1_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_sw_early_crc_i_9_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_sw_early_crc[9]), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_sw_early_crc_i[9]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_sw_early_crc_i_8_.INIT = 4'h1; + LUT1_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_sw_early_crc_i_8_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_sw_early_crc[8]), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_sw_early_crc_i[8]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_sw_early_crc_i_7_.INIT = 4'h1; + LUT1_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_sw_early_crc_i_7_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_sw_early_crc[7]), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_sw_early_crc_i[7]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_sw_early_crc_i_6_.INIT = 4'h1; + LUT1_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_sw_early_crc_i_6_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_sw_early_crc[6]), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_sw_early_crc_i[6]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_sw_early_crc_i_5_.INIT = 4'h1; + LUT1_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_sw_early_crc_i_5_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_sw_early_crc[5]), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_sw_early_crc_i[5]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_sw_early_crc_i_4_.INIT = 4'h1; + LUT1_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_sw_early_crc_i_4_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_sw_early_crc[4]), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_sw_early_crc_i[4]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_sw_early_crc_i_3_.INIT = 4'h1; + LUT1_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_sw_early_crc_i_3_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_sw_early_crc[3]), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_sw_early_crc_i[3]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_sw_early_crc_i_2_.INIT = 4'h1; + LUT1_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_sw_early_crc_i_2_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_sw_early_crc[2]), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_sw_early_crc_i[2]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_sw_early_crc_i_1_.INIT = 4'h1; + LUT1_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_sw_early_crc_i_1_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_sw_early_crc[1]), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_sw_early_crc_i[1]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_sw_early_crc_i_0_.INIT = 4'h1; + LUT1_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_sw_early_crc_i_0_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_sw_early_crc[0]), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_sw_early_crc_i[0]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_bm_1_16_.INIT = 16'h6996; + LUT4_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_bm_1_16_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[8]), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[19]), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_d64_c_q_16__1225), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_new_c32_d48_1_12_), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_bm_1_16__1207) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_bm_16_.INIT = 16'h6996; + LUT4 com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_bm_16_ ( + .I0(N_70), + .I1(N_102), + .I2(N_139), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_bm_1_16__1207), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_bm_16__1206) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_bm_1_13_.INIT = 16'h6996; + LUT4 com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_bm_1_13_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[0]), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[6]), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[15]), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_d64_c_q_13__1228), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_bm_1_13__1209) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_bm_13_.INIT = 16'h6996; + LUT4 com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_bm_13_ ( + .I0(N_72), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[9]), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_new_c48_1_2_13_), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_bm_1_13__1209), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_bm_13__1208) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_d64_c_q_31_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_3), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_d64_c[31]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_d64_c_q_31__1210) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_d64_c_q_30_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_3), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_d64_c[30]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_d64_c_q_30__1211) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_d64_c_q_29_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_3), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_d64_c[29]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_d64_c_q_29__1212) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_d64_c_q_28_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_3), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_d64_c[28]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_d64_c_q_28__1213) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_d64_c_q_27_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_3), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_d64_c[27]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_d64_c_q_27__1214) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_d64_c_q_26_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_3), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_d64_c[26]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_d64_c_q_26__1215) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_d64_c_q_25_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_3), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_d64_c[25]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_d64_c_q_25__1216) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_d64_c_q_24_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_3), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_d64_c[24]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_d64_c_q_24__1217) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_d64_c_q_23_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_3), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_d64_c[23]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_d64_c_q_23__1218) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_d64_c_q_22_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_3), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_d64_c[22]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_d64_c_q_22__1219) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_d64_c_q_21_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_3), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_d64_c[21]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_d64_c_q_21__1220) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_d64_c_q_20_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_2), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_d64_c[20]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_d64_c_q_20__1221) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_d64_c_q_19_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_2), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_d64_c[19]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_d64_c_q_19__1222) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_d64_c_q_18_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_2), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_d64_c[18]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_d64_c_q_18__1223) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_d64_c_q_17_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_2), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_d64_c[17]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_d64_c_q_17__1224) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_d64_c_q_16_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_2), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_d64_c[16]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_d64_c_q_16__1225) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_d64_c_q_15_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_2), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_d64_c[15]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_d64_c_q_15__1226) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_d64_c_q_14_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_2), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_d64_c[14]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_d64_c_q_14__1227) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_d64_c_q_13_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_2), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_d64_c[13]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_d64_c_q_13__1228) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_d64_c_q_12_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_2), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_d64_c[12]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_d64_c_q_12__1229) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_d64_c_q_11_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_2), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_d64_c[11]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_d64_c_q_11__1230) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_d64_c_q_10_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_2), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_d64_c[10]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_d64_c_q_10__1231) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_d64_c_q_9_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_2), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_d64_c[9]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_d64_c_q_9__1232) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_d64_c_q_8_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_2), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_d64_c[8]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_d64_c_q_8__1233) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_d64_c_q_7_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_2), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_d64_c[7]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_d64_c_q_7__1234) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_d64_c_q_6_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_2), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_d64_c[6]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_d64_c_q_6__1235) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_d64_c_q_5_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_2), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_d64_c[5]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_d64_c_q_5__370) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_d64_c_q_4_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_2), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_d64_c[4]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_d64_c_q_4__1236) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_d64_c_q_3_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_2), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_d64_c[3]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_d64_c_q_3__1237) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_d64_c_q_2_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_2), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_d64_c[2]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_d64_c_q_2__369) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_d64_c_q_1_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_2), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_d64_c[1]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_d64_c_q_1__1238) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_d64_c_q_0_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_2), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_d64_c[0]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_d64_c_q_0__1239) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_63_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_1), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6[63]), + .Q(data_in_q[63]) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_62_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_1), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6[62]), + .Q(data_in_q[62]) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_61_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_1), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6[61]), + .Q(data_in_q[61]) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_60_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_1), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6[60]), + .Q(data_in_q[60]) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_59_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_1), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6[59]), + .Q(data_in_q[59]) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_58_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_1), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6[58]), + .Q(data_in_q[58]) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_57_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_1), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6[57]), + .Q(data_in_q[57]) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_56_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_1), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6[56]), + .Q(data_in_q[56]) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_55_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_1), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6[55]), + .Q(data_in_q[55]) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_54_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_1), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6[54]), + .Q(data_in_q[54]) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_53_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_1), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6[53]), + .Q(data_in_q[53]) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_52_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_1), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6[52]), + .Q(data_in_q[52]) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_51_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_1), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6[51]), + .Q(data_in_q[51]) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_50_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_1), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6[50]), + .Q(data_in_q[50]) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_49_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_1), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6[49]), + .Q(data_in_q[49]) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_48_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_1), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6[48]), + .Q(data_in_q[48]) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_47_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_1), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6[47]), + .Q(data_in_q[47]) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_46_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_1), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6[46]), + .Q(data_in_q[46]) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_45_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_1), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6[45]), + .Q(data_in_q[45]) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_44_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_1), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6[44]), + .Q(data_in_q[44]) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_43_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_1), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6[43]), + .Q(data_in_q[43]) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_42_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_1), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6[42]), + .Q(data_in_q[42]) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_41_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_1), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6[41]), + .Q(data_in_q[41]) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_40_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_1), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6[40]), + .Q(data_in_q[40]) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_39_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_1), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6[39]), + .Q(data_in_q[39]) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_38_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_1), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6[38]), + .Q(data_in_q[38]) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_37_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_1), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6[37]), + .Q(data_in_q[37]) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_36_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_1), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6[36]), + .Q(data_in_q[36]) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_35_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_1), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6[35]), + .Q(data_in_q[35]) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_34_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_1), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6[34]), + .Q(data_in_q[34]) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_33_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_1), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6[33]), + .Q(data_in_q[33]) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_32_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_1), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6[32]), + .Q(data_in_q[32]) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_31_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_1), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6[31]), + .Q(data_in_q[31]) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_30_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_1), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6[30]), + .Q(data_in_q[30]) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_29_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_1), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6[29]), + .Q(data_in_q[29]) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_28_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_1), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6[28]), + .Q(data_in_q[28]) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_27_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_1), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6[27]), + .Q(data_in_q[27]) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_26_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_1), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6[26]), + .Q(data_in_q[26]) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_25_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_1), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6[25]), + .Q(data_in_q[25]) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_24_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_1), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6[24]), + .Q(data_in_q[24]) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_23_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_1), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6[23]), + .Q(data_in_q[23]) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_22_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_1), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6[22]), + .Q(data_in_q[22]) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_21_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_1), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6[21]), + .Q(data_in_q[21]) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_20_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_1), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6[20]), + .Q(data_in_q[20]) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_19_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_1), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6[19]), + .Q(data_in_q[19]) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_18_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_1), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6[18]), + .Q(data_in_q[18]) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_17_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_1), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6[17]), + .Q(data_in_q[17]) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_16_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_1), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6[16]), + .Q(data_in_q[16]) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_15_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_1), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6[15]), + .Q(data_in_q[15]) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_14_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_1), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6[14]), + .Q(data_in_q[14]) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_13_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_1), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6[13]), + .Q(data_in_q[13]) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_12_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_1), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6[12]), + .Q(data_in_q[12]) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_11_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_1), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6[11]), + .Q(data_in_q[11]) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_10_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_1), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6[10]), + .Q(data_in_q[10]) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_9_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_1), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6[9]), + .Q(data_in_q[9]) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_8_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_1), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6[8]), + .Q(data_in_q[8]) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_7_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_1), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6[7]), + .Q(data_in_q[7]) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_1), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6[6]), + .Q(data_in_q[6]) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_5_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_1), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6[5]), + .Q(data_in_q[5]) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_4_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_1), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6[4]), + .Q(data_in_q[4]) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_3_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_1), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6[3]), + .Q(data_in_q[3]) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_2_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_1), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6[2]), + .Q(data_in_q[2]) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_1_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_0), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6[1]), + .Q(data_in_q[1]) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_0_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_0), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6[0]), + .Q(data_in_q[0]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_3_6_.INIT = 4'h6; + LUT2 com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_3_6_ ( + .I0(data_in_q[25]), + .I1(data_in_q[42]), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_3[6]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_1_23_.INIT = 4'h6; + LUT2 com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_1_23_ ( + .I0(data_in_q[15]), + .I1(data_in_q[17]), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_23__1243) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_2_26_.INIT = 4'h6; + LUT2 com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_2_26_ ( + .I0(data_in_q[6]), + .I1(data_in_q[18]), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_2_26_) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_2_29_.INIT = 4'h6; + LUT2 com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_2_29_ ( + .I0(data_in_q[42]), + .I1(data_in_q[45]), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_2_29_) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_0_27_.INIT = 4'h6; + LUT2 com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_0_27_ ( + .I0(data_in_q[23]), + .I1(data_in_q[63]), + .O(G_428_0) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_1_1_0_.INIT = 4'h6; + LUT2_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_1_1_0_ ( + .I0(data_in_q[32]), + .I1(data_in_q[54]), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_1_1[0]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_0_20_.INIT = 4'h6; + LUT2 com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_0_20_ ( + .I0(data_in_q[39]), + .I1(data_in_q[55]), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_0_20__1241) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_0_31_.INIT = 4'h6; + LUT2 com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_0_31_ ( + .I0(data_in_q[33]), + .I1(data_in_q[49]), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_0_31__1242) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_1_24_.INIT = 4'h6; + LUT2 com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_1_24_ ( + .I0(data_in_q[39]), + .I1(data_in_q[40]), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_1_24__1240) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_0_13_.INIT = 4'h6; + LUT2 com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_0_13_ ( + .I0(data_in_q[5]), + .I1(data_in_q[28]), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_0_13__1249) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_0_28_.INIT = 4'h6; + LUT2 com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_0_28_ ( + .I0(data_in_q[5]), + .I1(data_in_q[12]), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_0_28__1250) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_2_2_.INIT = 16'h6996; + LUT4 com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_2_2_ ( + .I0(data_in_q[8]), + .I1(data_in_q[18]), + .I2(data_in_q[37]), + .I3(data_in_q[44]), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_2_2__1244) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_2_25_.INIT = 16'h6996; + LUT4 com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_2_25_ ( + .I0(data_in_q[19]), + .I1(data_in_q[38]), + .I2(data_in_q[58]), + .I3(data_in_q[61]), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_2_25__1245) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_1_16_.INIT = 8'h96; + LUT3 com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_1_16_ ( + .I0(data_in_q[0]), + .I1(data_in_q[21]), + .I2(data_in_q[56]), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_1_16__1275) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_0_4_.INIT = 4'h6; + LUT2 com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_0_4_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_2_26_), + .I1(data_in_q[48]), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_0_4__1247) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_2_17_.INIT = 16'h6996; + LUT4 com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_2_17_ ( + .I0(data_in_q[14]), + .I1(data_in_q[22]), + .I2(data_in_q[23]), + .I3(data_in_q[27]), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_2_17__1273) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_1_27_.INIT = 4'h6; + LUT2 com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_1_27_ ( + .I0(G_428_0), + .I1(N_10560_1), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_1_27__1248) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_1_13_.INIT = 4'h6; + LUT2 com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_1_13_ ( + .I0(G_157_350), + .I1(data_in_q[31]), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_13__1280) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_1_15_.INIT = 4'h6; + LUT2 com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_1_15_ ( + .I0(G_188_362), + .I1(data_in_q[49]), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_15__1277) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_1_17_.INIT = 4'h6; + LUT2 com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_1_17_ ( + .I0(N_234), + .I1(G_133_352), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_17__1282) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_1_26_.INIT = 4'h6; + LUT2 com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_1_26_ ( + .I0(G_128_296), + .I1(data_in_q[41]), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_26__1260) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_1_29_.INIT = 4'h6; + LUT2 com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_1_29_ ( + .I0(N_129), + .I1(data_in_q[34]), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_29__1256) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_2_6_.INIT = 16'h6996; + LUT4 com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_2_6_ ( + .I0(N_10398_1), + .I1(data_in_q[11]), + .I2(data_in_q[14]), + .I3(data_in_q[41]), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_2_6_) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_2_1_.INIT = 16'h6996; + LUT4 com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_2_1_ ( + .I0(N_10413_2), + .I1(data_in_q[46]), + .I2(data_in_q[47]), + .I3(data_in_q[49]), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_2_1_) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_1_0_.INIT = 16'h6996; + LUT4 com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_1_0_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_1_1[0]), + .I1(data_in_q[24]), + .I2(data_in_q[29]), + .I3(data_in_q[60]), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_0__1302) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_1_14_.INIT = 8'h96; + LUT3 com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_1_14_ ( + .I0(N_164), + .I1(data_in_q[11]), + .I2(data_in_q[48]), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_14__1304) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_3_18_.INIT = 4'h6; + LUT2 com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_3_18_ ( + .I0(N_190), + .I1(G_285_349), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_3_18__1271) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_1_3_.INIT = 8'h96; + LUT3 com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_1_3_ ( + .I0(N_212), + .I1(G_362_386), + .I2(data_in_q[53]), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_1_3__1297) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_2_21_.INIT = 16'h6996; + LUT4 com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_2_21_ ( + .I0(G_143_364), + .I1(G_293_390), + .I2(data_in_q[34]), + .I3(data_in_q[56]), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_2_21__1267) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_4_21_.INIT = 4'h6; + LUT2_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_4_21_ ( + .I0(N_239), + .I1(G_133_352), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_4_21__1266) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_1_8_.INIT = 8'h96; + LUT3 com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_1_8_ ( + .I0(N_165_1), + .I1(N_189), + .I2(G_293_390), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_1_8__1289) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_2_15_.INIT = 16'h6996; + LUT4 com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_2_15_ ( + .I0(N_10357_1), + .I1(data_in_q[12]), + .I2(data_in_q[34]), + .I3(data_in_q[52]), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_2_15__1251) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_2_10_.INIT = 16'h6996; + LUT4 com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_2_10_ ( + .I0(G_272_391), + .I1(G_286_325), + .I2(data_in_q[14]), + .I3(data_in_q[28]), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_2_10__1252) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_1_0_6_.INIT = 8'h96; + LUT3_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_1_0_6_ ( + .I0(N_163_1), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_3[6]), + .I2(data_in_q[52]), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_1_6_) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_0_5_.INIT = 4'h6; + LUT2 com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_0_5_ ( + .I0(G_143_364), + .I1(G_383_385), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_0_5__1294) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_2_0_26_.INIT = 4'h6; + LUT2_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_2_0_26_ ( + .I0(N_165), + .I1(N_169), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_2_26__1246) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_2_14_.INIT = 16'h6996; + LUT4 com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_2_14_ ( + .I0(G_383_385), + .I1(data_in_q[17]), + .I2(data_in_q[32]), + .I3(data_in_q[44]), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_2_14__1278) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_0_19_.INIT = 4'h6; + LUT2 com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_0_19_ ( + .I0(N_242), + .I1(G_144_354), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_0_19__1269) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_4_17_.INIT = 4'h6; + LUT2 com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_4_17_ ( + .I0(N_154), + .I1(N_241), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_4_17__1272) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_2_30_.INIT = 16'h6996; + LUT4 com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_2_30_ ( + .I0(G_422_347), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_2_29_), + .I2(data_in_q[24]), + .I3(data_in_q[61]), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_2_30__1254) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_3_24_.INIT = 16'h6996; + LUT4 com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_3_24_ ( + .I0(N_158), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_1_24__1240), + .I2(data_in_q[20]), + .I3(data_in_q[47]), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_3_24__1262) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_2_9_.INIT = 16'h6996; + LUT4 com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_2_9_ ( + .I0(N_210_1), + .I1(G_447_384), + .I2(data_in_q[13]), + .I3(data_in_q[41]), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_2_9__1287) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_2_11_.INIT = 4'h6; + LUT2 com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_2_11_ ( + .I0(N_170), + .I1(N_237), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_2_11__1284) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_1_12_.INIT = 8'h96; + LUT3 com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_1_12_ ( + .I0(G_255_348), + .I1(G_272_391), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_23__1243), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_1_12__1281) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_4_18_.INIT = 16'h6996; + LUT4_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_4_18_ ( + .I0(N_155), + .I1(G_364_361), + .I2(data_in_q[23]), + .I3(data_in_q[59]), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_4_18__1270) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_6_3_.INIT = 16'h6996; + LUT4_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_6_3_ ( + .I0(N_116), + .I1(N_135), + .I2(N_190), + .I3(N_209), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_6_3__1296) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_4_20_.INIT = 16'h6996; + LUT4_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_4_20_ ( + .I0(N_210), + .I1(G_294_389), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_0_20__1241), + .I3(data_in_q[61]), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_4_20__1268) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_4_31_.INIT = 16'h6996; + LUT4_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_4_31_ ( + .I0(N_117_1), + .I1(N_162), + .I2(N_209_1), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_0_31__1242), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_4_31__1253) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_5_8_.INIT = 16'h6996; + LUT4 com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_5_8_ ( + .I0(N_170), + .I1(N_240), + .I2(G_128_296), + .I3(G_434_368), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_5_8__1288) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_3_23_.INIT = 16'h6996; + LUT4_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_3_23_ ( + .I0(N_201), + .I1(G_465_303), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_23__1243), + .I3(data_in_q[13]), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_3_23__1263) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_6_2_.INIT = 16'h6996; + LUT4_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_6_2_ ( + .I0(N_234_1), + .I1(N_237), + .I2(G_167_363), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_2_2__1244), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_6_2__1298) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_5_25_.INIT = 8'h96; + LUT3_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_5_25_ ( + .I0(N_157), + .I1(G_411_290), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_2_25__1245), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_5_25__1261) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_4_22_.INIT = 16'h6996; + LUT4 com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_4_22_ ( + .I0(G_129_274), + .I1(G_447_384), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_2_6_), + .I3(data_in_q[61]), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_4_22__1265) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_5_22_.INIT = 8'h96; + LUT3_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_5_22_ ( + .I0(G_134_353), + .I1(G_397_367), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_29__1256), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_5_22__1264) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_2_2_1_.INIT = 8'h96; + LUT3_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_2_2_1_ ( + .I0(N_194), + .I1(N_212), + .I2(G_374_305), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_2_1__1300) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_3_1_.INIT = 16'h6996; + LUT4 com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_3_1_ ( + .I0(N_114), + .I1(G_143_364), + .I2(data_in_q[12]), + .I3(data_in_q[33]), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_3_1__1299) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_5_16_.INIT = 16'h6996; + LUT4_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_5_16_ ( + .I0(N_169), + .I1(G_143_364), + .I2(G_286_325), + .I3(data_in_q[12]), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_5_16__1274) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_4_5_.INIT = 16'h6996; + LUT4 com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_4_5_ ( + .I0(N_130), + .I1(N_157), + .I2(N_201), + .I3(G_287_56), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_4_5__1293) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_3_26_.INIT = 16'h6996; + LUT4_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_3_26_ ( + .I0(G_285_349), + .I1(G_362_386), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_2_26_), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_2_26__1246), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_3_26__1259) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_3_4_.INIT = 16'h6996; + LUT4_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_3_4_ ( + .I0(N_173), + .I1(N_241), + .I2(G_255_348), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_0_4__1247), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_3_4__1295) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_2_0_29_.INIT = 16'h6996; + LUT4 com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_2_0_29_ ( + .I0(N_163), + .I1(N_194), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_2_29_), + .I3(data_in_q[51]), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_2_29__1255) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_3_7_.INIT = 16'h6996; + LUT4 com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_3_7_ ( + .I0(G_188_362), + .I1(G_295_326), + .I2(G_422_347), + .I3(data_in_q[54]), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_3_7__1291) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_4_7_.INIT = 8'h96; + LUT3_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_4_7_ ( + .I0(N_115), + .I1(G_271_55), + .I2(G_435_297), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_4_7__1290) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_3_27_.INIT = 16'h6996; + LUT4 com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_3_27_ ( + .I0(N_239), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_3[6]), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_1_27__1248), + .I3(data_in_q[53]), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_3_27__1258) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_5_9_.INIT = 8'h96; + LUT3 com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_5_9_ ( + .I0(N_135), + .I1(G_287_56), + .I2(G_361_307), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_5_9__1286) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_3_11_.INIT = 16'h6996; + LUT4 com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_3_11_ ( + .I0(N_116), + .I1(N_157), + .I2(G_142_306), + .I3(data_in_q[20]), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_3_11__1283) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_3_0_.INIT = 16'h6996; + LUT4 com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_3_0_ ( + .I0(N_202), + .I1(G_397_367), + .I2(G_434_368), + .I3(G_467_383), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_3_0__1301) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_3_13_.INIT = 16'h6996; + LUT4 com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_3_13_ ( + .I0(N_136), + .I1(N_173_1), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_0_13__1249), + .I3(data_in_q[54]), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_3_13__1279) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_4_28_.INIT = 16'h6996; + LUT4_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_4_28_ ( + .I0(N_162), + .I1(N_199_1), + .I2(G_467_383), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_0_28__1250), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_4_28__1257) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_6_15_.INIT = 16'h6996; + LUT4_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_6_15_ ( + .I0(N_114), + .I1(N_130), + .I2(N_211), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_2_15__1251), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_6_15__1276) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_6_10_.INIT = 16'h6996; + LUT4_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_6_10_ ( + .I0(N_114), + .I1(N_165), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_2_10__1252), + .I3(data_in_q[33]), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_6_10__1285) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_5_6_.INIT = 16'h6996; + LUT4_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_5_6_ ( + .I0(N_114), + .I1(N_130), + .I2(G_168_351), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_1_6_), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_5_6__1292) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_31_.INIT = 16'h6996; + LUT4_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_31_ ( + .I0(N_200), + .I1(G_128_296), + .I2(G_437_273), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_4_31__1253), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_d64_c[31]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_30_.INIT = 16'h6996; + LUT4_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_30_ ( + .I0(N_158), + .I1(G_418_299), + .I2(G_428_272), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_2_30__1254), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_d64_c[30]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_29_.INIT = 16'h6996; + LUT4_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_29_ ( + .I0(G_410_304), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_26__1260), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_29__1256), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_2_29__1255), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_d64_c[29]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_28_.INIT = 16'h6996; + LUT4_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_28_ ( + .I0(N_157), + .I1(N_242), + .I2(G_463_280), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_4_28__1257), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_d64_c[28]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_27_.INIT = 16'h6996; + LUT4_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_27_ ( + .I0(G_373_277), + .I1(G_375_291), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_15__1277), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_3_27__1258), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_d64_c[27]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_26_.INIT = 16'h6996; + LUT4_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_26_ ( + .I0(G_376_301), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_13__1280), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_26__1260), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_3_26__1259), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_d64_c[26]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_25_.INIT = 16'h6996; + LUT4_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_25_ ( + .I0(N_163), + .I1(G_133_352), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_14__1304), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_5_25__1261), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_d64_c[25]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_24_.INIT = 16'h6996; + LUT4_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_24_ ( + .I0(G_359_275), + .I1(G_371_300), + .I2(G_411_290), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_3_24__1262), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_d64_c[24]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_23_.INIT = 16'h6996; + LUT4_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_23_ ( + .I0(N_209), + .I1(G_375_291), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_2_1_), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_3_23__1263), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_d64_c[23]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_22_.INIT = 16'h6996; + LUT4_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_22_ ( + .I0(N_162), + .I1(N_169), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_4_22__1265), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_5_22__1264), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_d64_c[22]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_21_.INIT = 16'h6996; + LUT4_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_21_ ( + .I0(N_200), + .I1(G_157_350), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_2_21__1267), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_4_21__1266), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_d64_c[21]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_20_.INIT = 16'h6996; + LUT4_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_20_ ( + .I0(G_142_306), + .I1(G_364_361), + .I2(G_435_297), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_4_20__1268), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_d64_c[20]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_19_.INIT = 16'h6996; + LUT4_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_19_ ( + .I0(G_374_305), + .I1(G_436_292), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_0__1302), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_0_19__1269), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_d64_c[19]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_18_.INIT = 16'h6996; + LUT4_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_18_ ( + .I0(G_167_363), + .I1(G_295_326), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_3_18__1271), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_4_18__1270), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_d64_c[18]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_17_.INIT = 16'h6996; + LUT4_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_17_ ( + .I0(N_210), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_17__1282), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_2_17__1273), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_4_17__1272), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_d64_c[17]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_16_.INIT = 16'h6996; + LUT4_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_16_ ( + .I0(G_294_389), + .I1(G_418_299), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_1_16__1275), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_5_16__1274), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_d64_c[16]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_15_.INIT = 16'h6996; + LUT4_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_15_ ( + .I0(N_164), + .I1(N_168), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_15__1277), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_6_15__1276), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_d64_c[15]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_14_.INIT = 16'h6996; + LUT4_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_14_ ( + .I0(G_168_351), + .I1(G_428_272), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_2_14__1278), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_4_14__1303), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_d64_c[14]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_13_.INIT = 16'h6996; + LUT4_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_13_ ( + .I0(G_359_275), + .I1(G_410_304), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_13__1280), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_3_13__1279), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_d64_c[13]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_12_.INIT = 16'h6996; + LUT4_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_12_ ( + .I0(N_211), + .I1(G_463_280), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_17__1282), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_1_12__1281), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_d64_c[12]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_11_.INIT = 16'h6996; + LUT4_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_11_ ( + .I0(G_382_278), + .I1(G_436_292), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_2_11__1284), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_3_11__1283), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_d64_c[11]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_10_.INIT = 16'h6996; + LUT4_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_10_ ( + .I0(N_173), + .I1(G_134_353), + .I2(N_10524_1), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_6_10__1285), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_d64_c[10]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_9_.INIT = 16'h6996; + LUT4_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_9_ ( + .I0(N_202), + .I1(G_373_277), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_2_9__1287), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_5_9__1286), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_d64_c[9]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_8_.INIT = 16'h6996; + LUT4_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_8_ ( + .I0(G_271_55), + .I1(G_361_307), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_1_8__1289), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_5_8__1288), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_d64_c[8]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_7_.INIT = 16'h6996; + LUT4_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_7_ ( + .I0(N_117), + .I1(G_149_276), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_3_7__1291), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_4_7__1290), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_d64_c[7]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_6_.INIT = 16'h6996; + LUT4_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_6_ ( + .I0(N_234), + .I1(G_144_354), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_2_6_), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_5_6__1292), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_d64_c[6]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_5_.INIT = 16'h6996; + LUT4_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_5_ ( + .I0(N_165), + .I1(G_371_300), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_0_5__1294), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_4_5__1293), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_d64_c[5]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_4_.INIT = 16'h6996; + LUT4_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_4_ ( + .I0(N_117), + .I1(G_149_276), + .I2(G_437_273), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_3_4__1295), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_d64_c[4]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_3_.INIT = 16'h6996; + LUT4_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_3_ ( + .I0(N_164), + .I1(N_240), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_1_3__1297), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_6_3__1296), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_d64_c[3]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_2_.INIT = 16'h6996; + LUT4_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_2_ ( + .I0(N_136), + .I1(N_154), + .I2(G_465_303), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_6_2__1298), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_d64_c[2]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_1_.INIT = 16'h6996; + LUT4_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_1_ ( + .I0(N_155), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_2_1_), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_2_1__1300), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_3_1__1299), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_d64_c[1]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_0_.INIT = 16'h6996; + LUT4_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_0_ ( + .I0(N_155), + .I1(G_382_278), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_0__1302), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_3_0__1301), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_d64_c[0]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_4_14_.INIT = 8'h96; + LUT3 com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_4_14_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_14__1304), + .I1(N_10518_1), + .I2(N_130), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_4_14__1303) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c16_new_c16_1_1_25_.INIT = 4'h6; + LUT2 com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c16_new_c16_1_1_25_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[9]), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[18]), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_new_c32_d16_1_25_) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c16_new_c16_1_0_4_.INIT = 4'h6; + LUT2 com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c16_new_c16_1_0_4_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[24]), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_d64_c_q_4__1236), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_new_c16_1_0[4]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c16_new_c16_1_2_24_.INIT = 16'h6996; + LUT4 com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c16_new_c16_1_2_24_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[8]), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[17]), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[18]), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_d64_c_q_24__1217), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_new_c16_1_2[24]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c16_new_c16_1_1_29_.INIT = 8'h96; + LUT3_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c16_new_c16_1_1_29_ ( + .I0(N_10491), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[23]), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_d64_c_q_29__1212), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_new_c16_1_1_29_) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c16_new_c16_1_1_13_.INIT = 16'h6996; + LUT4 com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c16_new_c16_1_1_13_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[17]), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[21]), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[26]), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_d64_c_q_13__1228), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_new_c16_1_1_13_) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c16_new_c16_1_1_0_8_.INIT = 8'h96; + LUT3 com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c16_new_c16_1_1_0_8_ ( + .I0(N_10490), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[27]), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[28]), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_new_c16_1_1_8_) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c16_new_c16_1_1_23_.INIT = 16'h6996; + LUT4 com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c16_new_c16_1_1_23_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[7]), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[16]), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[31]), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_d64_c_q_23__1218), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_new_c16_1_1_23_) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c16_new_c16_1_1_8_.INIT = 4'h6; + LUT2_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c16_new_c16_1_1_8_ ( + .I0(N_81), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_d64_c_q_8__1233), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_new_c32_d16_1_8_) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c16_new_c16_1_1_3_.INIT = 8'h96; + LUT3 com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c16_new_c16_1_1_3_ ( + .I0(N_44), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[18]), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[26]), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_new_c32_d16_1_3_) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c16_new_c16_1_31_.INIT = 16'h6996; + LUT4 com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c16_new_c16_1_31_ ( + .I0(N_73), + .I1(N_10613), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[21]), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_d64_c_q_31__1210), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_new_c32_d16[31]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c16_new_c16_1_1_0_16_.INIT = 8'h96; + LUT3_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c16_new_c16_1_1_0_16_ ( + .I0(N_100), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[29]), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_d64_c_q_16__1225), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_new_c16_1_1_16_) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c48_new_c48_1_1_12_.INIT = 4'h6; + LUT2 com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c48_new_c48_1_1_12_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[1]), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[5]), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_new_c32_d48_1_12_) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c48_new_c48_1_0_14_.INIT = 4'h6; + LUT2 com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c48_new_c48_1_0_14_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[10]), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_d64_c_q_14__1227), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_new_c48_1_0_14_) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c48_new_c48_1_2_13_.INIT = 16'h6996; + LUT4 com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c48_new_c48_1_2_13_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[3]), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[12]), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[16]), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[27]), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_new_c48_1_2_13_) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c48_new_c48_1_2_14_.INIT = 16'h6996; + LUT4 com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c48_new_c48_1_2_14_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[1]), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[3]), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[4]), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[16]), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_new_c48_1_2_14_) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c48_new_c48_1_2_17_.INIT = 16'h6996; + LUT4 com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c48_new_c48_1_2_17_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[14]), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[15]), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[17]), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_d64_c_q_17__1224), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_new_c48_1_2_17_) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c48_new_c48_1_1_15_.INIT = 8'h96; + LUT3 com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c48_new_c48_1_1_15_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[5]), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[28]), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_d64_c_q_15__1226), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_new_c48_1_1_15_) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c48_new_c48_1_2_27_.INIT = 16'h6996; + LUT4 com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c48_new_c48_1_2_27_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[5]), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[13]), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[29]), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_d64_c_q_27__1214), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_new_c48_1_2_27_) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c48_new_c48_1_1_10_.INIT = 16'h6996; + LUT4 com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c48_new_c48_1_1_10_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[3]), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[12]), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[13]), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_d64_c_q_10__1231), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_new_c48_1_1_10_) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c48_new_c48_1_1_21_.INIT = 8'h96; + LUT3_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c48_new_c48_1_1_21_ ( + .I0(N_10446), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[21]), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_d64_c_q_21__1220), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_new_c48_1_1_21_) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c48_new_c48_1_1_6_.INIT = 8'h96; + LUT3 com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c48_new_c48_1_1_6_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[26]), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[29]), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_d64_c_q_6__1235), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_new_c48_1_1_6_) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c48_new_c48_1_2_20_.INIT = 16'h6996; + LUT4 com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c48_new_c48_1_2_20_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[1]), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[7]), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[14]), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_d64_c_q_20__1221), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_new_c48_1_2_20_) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c48_new_c48_1_1_1_.INIT = 8'h96; + LUT3_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c48_new_c48_1_1_1_ ( + .I0(N_10534), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[1]), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_d64_c_q_1__1238), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_new_c48_1_1_1_) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c48_new_c48_1_0_30_.INIT = 8'h96; + LUT3 com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c48_new_c48_1_0_30_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[6]), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[12]), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_d64_c_q_30__1211), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_new_c48_1_0_30_) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c48_new_c48_1_1_30_.INIT = 8'h96; + LUT3_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c48_new_c48_1_1_30_ ( + .I0(N_10492), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[10]), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[13]), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_new_c48_1_1_30_) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c48_new_c48_1_1_19_.INIT = 16'h6996; + LUT4 com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c48_new_c48_1_1_19_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[4]), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[13]), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[19]), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_d64_c_q_19__1222), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_new_c48_1_1_19_) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c48_new_c48_1_2_28_.INIT = 16'h6996; + LUT4 com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c48_new_c48_1_2_28_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[4]), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[9]), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[27]), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_d64_c_q_28__1213), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_new_c48_1_2_28_) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c48_new_c48_1_1_7_.INIT = 16'h6996; + LUT4 com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c48_new_c48_1_1_7_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[0]), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[6]), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[9]), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_d64_c_q_7__1234), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_new_c48_1_1_7_) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c48_new_c48_1_1_0_18_.INIT = 16'h6996; + LUT4 com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c48_new_c48_1_1_0_18_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[7]), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[10]), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[15]), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_d64_c_q_18__1223), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_new_c48_1_1_18_) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c48_new_c48_1_1_25_.INIT = 16'h6996; + LUT4 com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c48_new_c48_1_1_25_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[3]), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[6]), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[13]), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_d64_c_q_25__1216), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_new_c48_1_1_25_) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c48_new_c48_1_1_26_.INIT = 8'h96; + LUT3 com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c48_new_c48_1_1_26_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[25]), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[26]), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_d64_c_q_26__1215), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_new_c48_1_1_26_) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c48_new_c48_1_1_4_.INIT = 16'h6996; + LUT4 com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c48_new_c48_1_1_4_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[8]), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[14]), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[30]), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_d64_c_q_4__1236), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_new_c48_1_1_4_) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c48_new_c48_1_1_0_.INIT = 16'h6996; + LUT4_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c48_new_c48_1_1_0_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[8]), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[10]), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[13]), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_d64_c_q_0__1239), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c48_new_c48_1_1_0__1305) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c48_new_c48_1_1_29_.INIT = 16'h6996; + LUT4 com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c48_new_c48_1_1_29_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[7]), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[10]), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[11]), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_d64_c_q_29__1212), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c48_new_c48_1_1_29__1306) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c48_new_c48_1_3_15_.INIT = 16'h6996; + LUT4_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c48_new_c48_1_3_15_ ( + .I0(N_83), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[14]), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[18]), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[29]), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_new_c48_1_3_15_) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c48_new_c48_1_2_12_.INIT = 4'h6; + LUT2_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c48_new_c48_1_2_12_ ( + .I0(N_72), + .I1(N_151), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_new_c48_1_2_12_) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c48_new_c48_1_3_22_.INIT = 16'h6996; + LUT4_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c48_new_c48_1_3_22_ ( + .I0(N_93), + .I1(N_121), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[0]), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_d64_c_q_22__1219), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_new_c48_1_3_22_) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c48_new_c48_1_0_9_.INIT = 4'h6; + LUT2 com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c48_new_c48_1_0_9_ ( + .I0(N_10494), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_d64_c_q_9__1232), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_new_c48_1_0_9_) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c48_new_c48_1_3_7_.INIT = 16'h6996; + LUT4_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c48_new_c48_1_3_7_ ( + .I0(N_71), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[13]), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[25]), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[29]), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_new_c48_1_3_7_) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c48_new_c48_1_1_11_.INIT = 16'h6996; + LUT4_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c48_new_c48_1_1_11_ ( + .I0(N_109), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[12]), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[27]), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_d64_c_q_11__1230), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_new_c48_1_1_11_) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c48_new_c48_1_1_0_5_.INIT = 16'h6996; + LUT4_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c48_new_c48_1_1_0_5_ ( + .I0(N_10538), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[21]), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[28]), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[30]), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_new_c48_1_1_5_) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c48_new_c48_1_2_24_.INIT = 16'h6996; + LUT4_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c48_new_c48_1_2_24_ ( + .I0(N_102), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[2]), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[12]), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_d64_c_q_24__1217), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_new_c48_1_2_24_) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c48_new_c48_1_3_24_.INIT = 4'h6; + LUT2 com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c48_new_c48_1_3_24_ ( + .I0(N_44), + .I1(N_166), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_new_c48_1_3_24_) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c48_new_c48_1_2_23_.INIT = 16'h6996; + LUT4_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c48_new_c48_1_2_23_ ( + .I0(N_70), + .I1(N_10493), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[26]), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_d64_c_q_23__1218), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_new_c48_1_2_23_) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c48_new_c48_1_1_0_2_.INIT = 16'h6996; + LUT4 com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c48_new_c48_1_1_0_2_ ( + .I0(N_105), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[8]), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[14]), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[19]), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_new_c48_1_1_2_) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c48_new_c48_1_2_8_.INIT = 4'h6; + LUT2_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c48_new_c48_1_2_8_ ( + .I0(N_94), + .I1(N_152), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c48_new_c48_1_2[8]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c48_new_c48_1_2_3_.INIT = 16'h6996; + LUT4_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c48_new_c48_1_2_3_ ( + .I0(N_10446), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[15]), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[20]), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_d64_c_q_3__1237), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_new_c48_1_2_3_) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c48_new_c48_1_2_0_.INIT = 16'h6996; + LUT4 com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c48_new_c48_1_2_0_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[14]), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[18]), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[29]), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c48_new_c48_1_1_0__1305), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_new_c48_1_2_0_) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c48_new_c48_1_2_29_.INIT = 4'h6; + LUT2 com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c48_new_c48_1_2_29_ ( + .I0(N_10361), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c48_new_c48_1_1_29__1306), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_new_c48_1_2_29_) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c48_new_c48_1_3_8_.INIT = 16'h6996; + LUT4 com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c48_new_c48_1_3_8_ ( + .I0(N_121), + .I1(N_10492), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[15]), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c48_new_c48_1_2[8]), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_new_c48_1_3_8_) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c48_new_c48_1_2_31_.INIT = 16'h6996; + LUT4 com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c48_new_c48_1_2_31_ ( + .I0(N_82), + .I1(N_151), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[20]), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_d64_c_q_31__1210), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_new_c48_1_2_31_) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c48_new_c48_1_1_2_.INIT = 8'h96; + LUT3 com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c48_new_c48_1_1_2_ ( + .I0(N_93), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[2]), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[1]), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_new_c32_d48_1_2_) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c64_new_c64_1_0_16_.INIT = 4'h6; + LUT2 com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c64_new_c64_1_0_16_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crc32_d64_feedback[24]), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_d64_c_q_16__1225), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c64_new_c64_1_0_16__1309) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c64_new_c64_1_0_25_.INIT = 4'h6; + LUT2_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c64_new_c64_1_0_25_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crc32_d64_feedback[4]), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_d64_c_q_25__1216), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c64_new_c64_1_0_25__1307) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c64_new_c64_1_0_26_.INIT = 4'h6; + LUT2 com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c64_new_c64_1_0_26_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crc32_d64_feedback[6]), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_d64_c_q_26__1215), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c64_new_c64_1_0_26__1337) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c64_new_c64_1_0_13_.INIT = 4'h6; + LUT2 com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c64_new_c64_1_0_13_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crc32_d64_feedback[20]), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_d64_c_q_13__1228), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c64_new_c64_1_0_13__1330) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c64_new_c64_1_1_4_.INIT = 8'h96; + LUT3 com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c64_new_c64_1_1_4_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crc32_d64_feedback[7]), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crc32_d64_feedback[18]), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crc32_d64_feedback[31]), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c64_new_c32_d64_1_4_) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c64_new_c64_1_1_17_.INIT = 8'h96; + LUT3 com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c64_new_c64_1_1_17_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crc32_d64_feedback[17]), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crc32_d64_feedback[26]), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_d64_c_q_17__1224), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c64_new_c64_1_1_17__1310) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c64_new_c64_1_2_19_.INIT = 16'h6996; + LUT4 com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c64_new_c64_1_2_19_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crc32_d64_feedback[1]), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crc32_d64_feedback[19]), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crc32_d64_feedback[28]), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_d64_c_q_19__1222), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c64_new_c64_1_2_19__1311) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c64_new_c64_1_1_21_.INIT = 8'h96; + LUT3 com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c64_new_c64_1_1_21_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crc32_d64_feedback[5]), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crc32_d64_feedback[30]), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_d64_c_q_21__1220), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c64_new_c64_1_1_21__1313) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c64_new_c64_1_1_20_.INIT = 8'h96; + LUT3 com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c64_new_c64_1_1_20_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crc32_d64_feedback[28]), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crc32_d64_feedback[29]), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_d64_c_q_20__1221), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c64_new_c64_1_1_20__1312) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c64_new_c64_1_1_29_.INIT = 8'h96; + LUT3 com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c64_new_c64_1_1_29_ ( + .I0(N_10544), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crc32_d64_feedback[31]), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_d64_c_q_29__1212), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c64_new_c64_1_1_29__1315) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c64_new_c64_1_1_31_.INIT = 8'h96; + LUT3 com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c64_new_c64_1_1_31_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crc32_d64_feedback[14]), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crc32_d64_feedback[21]), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_d64_c_q_31__1210), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c64_new_c64_1_1_31__1314) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c64_new_c64_1_2_22_.INIT = 16'h6996; + LUT4 com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c64_new_c64_1_2_22_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crc32_d64_feedback[4]), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crc32_d64_feedback[5]), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crc32_d64_feedback[11]), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_d64_c_q_22__1219), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c64_new_c64_1_2_22__1308) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c64_new_c64_1_0_23_.INIT = 8'h96; + LUT3 com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c64_new_c64_1_0_23_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crc32_d64_feedback[2]), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crc32_d64_feedback[6]), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_d64_c_q_23__1218), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c64_new_c64_1_0_23__1334) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c64_new_c64_1_1_0_6_.INIT = 16'h6996; + LUT4 com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c64_new_c64_1_1_0_6_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crc32_d64_feedback[10]), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crc32_d64_feedback[11]), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crc32_d64_feedback[15]), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_d64_c_q_6__1235), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c64_new_c64_1_1_6__1323) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c64_new_c64_1_2_2_.INIT = 16'h6996; + LUT4 com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c64_new_c64_1_2_2_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crc32_d64_feedback[4]), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crc32_d64_feedback[12]), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crc32_d64_feedback[23]), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_d64_c_q_2__369), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c64_new_c64_1_2_2__1316) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c64_new_c64_1_1_18_.INIT = 16'h6996; + LUT4 com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c64_new_c64_1_1_18_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crc32_d64_feedback[14]), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crc32_d64_feedback[17]), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crc32_d64_feedback[27]), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_d64_c_q_18__1223), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c64_new_c64_1_1_18__1317) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c64_new_c64_1_1_10_.INIT = 8'h96; + LUT3 com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c64_new_c64_1_1_10_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crc32_d64_feedback[18]), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crc32_d64_feedback[31]), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_d64_c_q_10__1231), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c64_new_c64_1_1_10__1327) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c64_new_c64_1_2_7_.INIT = 16'h6996; + LUT4 com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c64_new_c64_1_2_7_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crc32_d64_feedback[2]), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crc32_d64_feedback[9]), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crc32_d64_feedback[15]), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_d64_c_q_7__1234), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c64_new_c64_1_2_7__1324) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c64_new_c64_1_2_5_.INIT = 16'h6996; + LUT4 com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c64_new_c64_1_2_5_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crc32_d64_feedback[5]), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crc32_d64_feedback[8]), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crc32_d64_feedback[21]), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_d64_c_q_5__370), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c64_new_c64_1_2_5__1322) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c64_new_c64_1_1_0_14_.INIT = 8'h96; + LUT3 com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c64_new_c64_1_1_0_14_ ( + .I0(N_10423_1), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crc32_d64_feedback[11]), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_d64_c_q_14__1227), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c64_new_c64_1_1_14__1331) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c64_new_c64_1_1_15_.INIT = 8'h96; + LUT3 com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c64_new_c64_1_1_15_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crc32_d64_feedback[23]), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crc32_d64_feedback[25]), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_d64_c_q_15__1226), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c64_new_c64_1_1_15__1332) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c64_new_c64_1_1_14_.INIT = 4'h6; + LUT2 com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c64_new_c64_1_1_14_ ( + .I0(N_181), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crc32_d64_feedback[1]), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c64_new_c32_d64_1_14_) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c64_new_c64_1_1_6_.INIT = 4'h6; + LUT2 com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c64_new_c64_1_1_6_ ( + .I0(N_204), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crc32_d64_feedback[30]), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c64_new_c32_d64_1_6_) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c64_new_c64_1_1_2_.INIT = 4'h6; + LUT2 com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c64_new_c64_1_1_2_ ( + .I0(N_10433), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crc32_d64_feedback[0]), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c64_new_c32_d64_1_2_) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c64_new_c64_1_1_7_.INIT = 16'h6996; + LUT4 com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c64_new_c64_1_1_7_ ( + .I0(N_184), + .I1(N_10585_1), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crc32_d64_feedback[0]), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crc32_d64_feedback[10]), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c64_new_c32_d64_1_7_) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c64_new_c64_1_1_30_.INIT = 4'h6; + LUT2_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c64_new_c64_1_1_30_ ( + .I0(N_205), + .I1(N_222), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c64_new_c64_1_1_30__1340) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c64_new_c64_1_3_25_.INIT = 16'h6996; + LUT4_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c64_new_c64_1_3_25_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crc32_d64_feedback[6]), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crc32_d64_feedback[9]), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crc32_d64_feedback[20]), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c64_new_c64_1_0_25__1307), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c64_new_c64_1_3_25__1336) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c64_new_c64_1_2_4_.INIT = 16'h6996; + LUT4 com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c64_new_c64_1_2_4_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crc32_d64_feedback[8]), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crc32_d64_feedback[16]), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_d64_c_q_4__1236), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c64_new_c32_d64_1_4_), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c64_new_c64_1_2_4__1321) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c64_new_c64_1_2_1_.INIT = 16'h6996; + LUT4_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c64_new_c64_1_2_1_ ( + .I0(N_10410), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crc32_d64_feedback[2]), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crc32_d64_feedback[3]), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_d64_c_q_1__1238), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c64_new_c64_1_2_1__1319) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c64_new_c64_1_2_9_.INIT = 16'h6996; + LUT4 com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c64_new_c64_1_2_9_ ( + .I0(N_10410), + .I1(N_10600), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crc32_d64_feedback[9]), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_d64_c_q_9__1232), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c64_new_c64_1_2_9__1326) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c64_new_c64_1_2_28_.INIT = 16'h6996; + LUT4 com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c64_new_c64_1_2_28_ ( + .I0(N_10425), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crc32_d64_feedback[24]), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crc32_d64_feedback[30]), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_d64_c_q_28__1213), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c64_new_c64_1_2_28__1339) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c64_new_c64_1_3_22_.INIT = 16'h6996; + LUT4 com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c64_new_c64_1_3_22_ ( + .I0(N_216_1), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crc32_d64_feedback[16]), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crc32_d64_feedback[28]), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c64_new_c64_1_2_22__1308), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c64_new_c64_1_3_22__1333) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c64_new_c64_1_2_3_.INIT = 16'h6996; + LUT4_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c64_new_c64_1_2_3_ ( + .I0(N_10418), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crc32_d64_feedback[5]), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crc32_d64_feedback[6]), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_d64_c_q_3__1237), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c64_new_c64_1_2_3__1320) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c64_new_c64_1_2_27_.INIT = 16'h6996; + LUT4 com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c64_new_c64_1_2_27_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crc32_d64_feedback[21]), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crc32_d64_feedback[26]), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_d64_c_q_27__1214), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c64_new_c32_d64_1_4_), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c64_new_c64_1_2_27__1338) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c64_new_c64_1_1_12_.INIT = 8'h96; + LUT3 com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c64_new_c64_1_1_12_ ( + .I0(N_187), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crc32_d64_feedback[10]), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_d64_c_q_12__1229), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c64_new_c64_1_1_12__1329) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c64_new_c64_1_1_24_.INIT = 8'h96; + LUT3 com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c64_new_c64_1_1_24_ ( + .I0(N_10454), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crc32_d64_feedback[16]), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_d64_c_q_24__1217), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c64_new_c64_1_1_24__1335) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c64_new_c64_1_2_11_.INIT = 16'h6996; + LUT4 com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c64_new_c64_1_2_11_ ( + .I0(N_10424_1), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crc32_d64_feedback[8]), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crc32_d64_feedback[9]), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_d64_c_q_11__1230), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c64_new_c64_1_2_11__1328) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c64_new_c64_1_16_.INIT = 16'h6996; + LUT4 com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c64_new_c64_1_16_ ( + .I0(N_10378), + .I1(N_10454), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crc32_d64_feedback[14]), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c64_new_c64_1_0_16__1309), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_new_c32_d64[16]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c64_new_c64_1_17_.INIT = 16'h6996; + LUT4 com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c64_new_c64_1_17_ ( + .I0(N_10411_1), + .I1(N_10423), + .I2(N_10528_1), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c64_new_c64_1_1_17__1310), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_new_c32_d64[17]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c64_new_c64_1_19_.INIT = 16'h6996; + LUT4 com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c64_new_c64_1_19_ ( + .I0(N_182), + .I1(N_10403), + .I2(N_10454_1), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c64_new_c64_1_2_19__1311), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_new_c32_d64[19]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c64_new_c64_1_20_.INIT = 16'h6996; + LUT4 com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c64_new_c64_1_20_ ( + .I0(N_10377), + .I1(N_10423), + .I2(N_10600), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c64_new_c64_1_1_20__1312), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_new_c32_d64[20]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c64_new_c64_1_21_.INIT = 16'h6996; + LUT4 com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c64_new_c64_1_21_ ( + .I0(N_185), + .I1(N_10376), + .I2(N_10544), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c64_new_c64_1_1_21__1313), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_new_c32_d64[21]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c64_new_c64_1_31_.INIT = 16'h6996; + LUT4 com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c64_new_c64_1_31_ ( + .I0(N_181), + .I1(N_10408), + .I2(N_10424), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c64_new_c64_1_1_31__1314), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_new_c32_d64[31]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c64_new_c64_1_29_.INIT = 16'h6996; + LUT4 com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c64_new_c64_1_29_ ( + .I0(N_10377), + .I1(N_10408), + .I2(N_10409), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c64_new_c64_1_1_29__1315), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_new_c32_d64[29]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c64_new_c64_1_2_0_.INIT = 16'h6996; + LUT4 com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c64_new_c64_1_2_0_ ( + .I0(N_220), + .I1(N_10412), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crc32_d64_feedback[16]), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_d64_c_q_0__1239), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c64_new_c64_1_2_0__1318) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c64_new_c64_1_1_8_.INIT = 8'h96; + LUT3 com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c64_new_c64_1_1_8_ ( + .I0(N_10412), + .I1(N_10590), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_d64_c_q_8__1233), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c64_new_c64_1_1_8__1325) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c64_new_c64_1_2_.INIT = 16'h6996; + LUT4 com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c64_new_c64_1_2_ ( + .I0(N_185), + .I1(N_10528), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c64_new_c64_1_2_2__1316), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c64_new_c32_d64_1_2_), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_new_c32_d64[2]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c64_new_c64_1_18_.INIT = 16'h6996; + LUT4 com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c64_new_c64_1_18_ ( + .I0(N_220), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crc32_d64_feedback[16]), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c64_new_c64_1_1_18__1317), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c64_new_c32_d64_1_2_), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_new_c32_d64[18]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c64_new_c64_1_0_.INIT = 8'h96; + LUT3 com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c64_new_c64_1_0_ ( + .I0(N_215), + .I1(N_10411), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c64_new_c64_1_2_0__1318), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_new_c32_d64[0]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c64_new_c64_1_1_.INIT = 16'h6996; + LUT4 com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c64_new_c64_1_1_ ( + .I0(N_182), + .I1(N_187), + .I2(N_10407), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c64_new_c64_1_2_1__1319), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_new_c32_d64[1]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c64_new_c64_1_3_.INIT = 16'h6996; + LUT4 com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c64_new_c64_1_3_ ( + .I0(N_203), + .I1(N_213), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crc32_d64_feedback[13]), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c64_new_c64_1_2_3__1320), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_new_c32_d64[3]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c64_new_c64_1_4_.INIT = 16'h6996; + LUT4 com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c64_new_c64_1_4_ ( + .I0(N_10409), + .I1(N_10425), + .I2(N_10528), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c64_new_c64_1_2_4__1321), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_new_c32_d64[4]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c64_new_c64_1_5_.INIT = 16'h6996; + LUT4 com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c64_new_c64_1_5_ ( + .I0(N_222), + .I1(N_10377), + .I2(N_10575), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c64_new_c64_1_2_5__1322), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_new_c32_d64[5]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c64_new_c64_1_6_.INIT = 16'h6996; + LUT4 com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c64_new_c64_1_6_ ( + .I0(N_10377), + .I1(N_10403), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c64_new_c64_1_1_6__1323), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c64_new_c32_d64_1_6_), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_new_c32_d64[6]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c64_new_c64_1_7_.INIT = 16'h6996; + LUT4 com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c64_new_c64_1_7_ ( + .I0(N_204), + .I1(N_10433), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c64_new_c64_1_2_7__1324), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c64_new_c32_d64_1_7_), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_new_c32_d64[7]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c64_new_c64_1_8_.INIT = 16'h6996; + LUT4 com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c64_new_c64_1_8_ ( + .I0(N_213), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crc32_d64_feedback[13]), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c64_new_c64_1_1_8__1325), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c64_new_c32_d64_1_7_), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_new_c32_d64[8]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c64_new_c64_1_9_.INIT = 16'h6996; + LUT4 com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c64_new_c64_1_9_ ( + .I0(N_185), + .I1(N_215), + .I2(N_10424), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c64_new_c64_1_2_9__1326), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_new_c32_d64[9]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c64_new_c64_1_10_.INIT = 16'h6996; + LUT4 com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c64_new_c64_1_10_ ( + .I0(N_213), + .I1(N_10418_1), + .I2(N_10608), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c64_new_c64_1_1_10__1327), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_new_c32_d64[10]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c64_new_c64_1_11_.INIT = 16'h6996; + LUT4 com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c64_new_c64_1_11_ ( + .I0(N_205), + .I1(N_10411), + .I2(N_10523), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c64_new_c64_1_2_11__1328), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_new_c32_d64[11]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c64_new_c64_1_12_.INIT = 16'h6996; + LUT4 com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c64_new_c64_1_12_ ( + .I0(N_182), + .I1(N_221), + .I2(N_10585_1), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c64_new_c64_1_1_12__1329), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_new_c32_d64[12]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c64_new_c64_1_13_.INIT = 16'h6996; + LUT4 com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c64_new_c64_1_13_ ( + .I0(N_184), + .I1(N_10418), + .I2(N_10567), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c64_new_c64_1_0_13__1330), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_new_c32_d64[13]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c64_new_c64_1_14_.INIT = 16'h6996; + LUT4 com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c64_new_c64_1_14_ ( + .I0(N_187), + .I1(N_215), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c64_new_c64_1_1_14__1331), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c64_new_c32_d64_1_14_), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_new_c32_d64[14]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c64_new_c64_1_15_.INIT = 16'h6996; + LUT4 com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c64_new_c64_1_15_ ( + .I0(N_220), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c64_new_c64_1_1_15__1332), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c64_new_c32_d64_1_6_), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c64_new_c32_d64_1_14_), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_new_c32_d64[15]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c64_new_c64_1_22_.INIT = 16'h6996; + LUT4 com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c64_new_c64_1_22_ ( + .I0(N_221), + .I1(N_10409), + .I2(N_10590), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c64_new_c64_1_3_22__1333), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_new_c32_d64[22]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c64_new_c64_1_23_.INIT = 16'h6996; + LUT4 com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c64_new_c64_1_23_ ( + .I0(N_182), + .I1(N_10585_1), + .I2(N_10608), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c64_new_c64_1_0_23__1334), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_new_c32_d64[23]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c64_new_c64_1_24_.INIT = 16'h6996; + LUT4 com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c64_new_c64_1_24_ ( + .I0(N_203), + .I1(N_224), + .I2(N_10523), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c64_new_c64_1_1_24__1335), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_new_c32_d64[24]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c64_new_c64_1_25_.INIT = 16'h6996; + LUT4 com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c64_new_c64_1_25_ ( + .I0(N_10376), + .I1(N_10378), + .I2(N_10407), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c64_new_c64_1_3_25__1336), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_new_c32_d64[25]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c64_new_c64_1_26_.INIT = 16'h6996; + LUT4 com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c64_new_c64_1_26_ ( + .I0(N_221), + .I1(N_10567), + .I2(N_10575), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c64_new_c64_1_0_26__1337), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_new_c32_d64[26]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c64_new_c64_1_27_.INIT = 16'h6996; + LUT4 com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c64_new_c64_1_27_ ( + .I0(N_10376), + .I1(N_10526), + .I2(N_10543), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c64_new_c64_1_2_27__1338), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_new_c32_d64[27]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c64_new_c64_1_28_.INIT = 16'h6996; + LUT4 com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c64_new_c64_1_28_ ( + .I0(N_181), + .I1(N_184), + .I2(N_224), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c64_new_c64_1_2_28__1339), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_new_c32_d64[28]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c64_new_c64_1_30_.INIT = 16'h6996; + LUT4 com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c64_new_c64_1_30_ ( + .I0(N_185), + .I1(N_10526), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_d64_c_q_30__1211), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c64_new_c64_1_1_30__1340), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_new_c32_d64[30]) + ); + GND com_llm_llm_tx_top_llmx08_tx_dllp_jefe_GND ( + .G(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_GND_1341) + ); + FDR com_llm_llm_tx_top_llmx08_tx_dllp_jefe_an_next_q_or_tx_fc_valid_q ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_N_67930_i_1364), + .Q(com_llm_llm_tx_top_tx_dllp_tx_next_pre), + .R(plm_link_up_i) + ); + FDRE com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_dllp_tx_next ( + .CE(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_N_42781_i_1343), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_N_12579_i), + .Q(com_llm_llm_tx_top_tx_dllp_tx_next), + .R(plm_link_up_i) + ); + FDRE com_llm_llm_tx_top_llmx08_tx_dllp_jefe_an_vld_q ( + .CE(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_N_67829_i_1349), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_N_30913_i_i_i_1361), + .Q(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_an_vld_q_1366), + .R(plm_link_up_i) + ); + FDR com_llm_llm_tx_top_llmx08_tx_dllp_jefe_an_next_q ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_an_next_q_5), + .Q(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_an_next_q_1363), + .R(plm_link_up_i) + ); + FDRE com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_expired_lbits ( + .CE(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_expired_lbits_1_sqmuxa_i_1350), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_N_69205_i_1394), + .Q(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_expired_lbits_1344), + .R(plm_link_up_i) + ); + FDRE com_llm_llm_tx_top_llmx08_tx_dllp_jefe_crc_an_vld_q ( + .CE(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_N_42781_i_1343), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_N_12555_i), + .Q(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_crc_an_vld_q_1342), + .R(plm_link_up_i) + ); + FDRE com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_expired_hbits ( + .CE(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_expired_hbits_1_sqmuxa_i_1354), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_N_69205_i_1394), + .Q(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_expired_hbits_1345), + .R(plm_link_up_i) + ); + FDRE com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_fc_valid_q ( + .CE(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_N_41762_i_i_1395), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_fc_queue_empty_i), + .Q(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_fc_valid_q_1367), + .R(plm_link_up_i) + ); + FDS com_llm_llm_tx_top_llmx08_tx_dllp_jefe_reg_tx_djefe_idle ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_reg_tx_djefe_idle_3), + .Q(com_llm_llm_tx_top_reg_tx_djefe_idle), + .S(plm_link_up_i) + ); + FDSE com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_dllp_vld_n ( + .CE(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_N_42781_i_1343), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_N_68886_i_1359), + .Q(com_llm_llm_tx_top_tx_dllp_vld_n), + .S(plm_link_up_i) + ); + MUXCY_L com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_latency_timer_cry_0_ ( + .CI(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_N_69205_i_1394), + .DI(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_GND_1341), + .LO(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_latency_timer_cry[0]), + .S(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_latency_timer_qxu[0]) + ); + XORCY com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_latency_timer_s_0_ ( + .CI(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_N_69205_i_1394), + .LI(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_latency_timer_qxu[0]), + .O(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_latency_timer_s[0]) + ); + FDR com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_latency_timer_0_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_latency_timer_s[0]), + .Q(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_latency_timer[0]), + .R(plm_link_up_i) + ); + MUXCY_L com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_latency_timer_cry_1_ ( + .CI(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_latency_timer_cry[0]), + .DI(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_GND_1341), + .LO(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_latency_timer_cry[1]), + .S(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_latency_timer_qxu[1]) + ); + XORCY com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_latency_timer_s_1_ ( + .CI(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_latency_timer_cry[0]), + .LI(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_latency_timer_qxu[1]), + .O(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_latency_timer_s[1]) + ); + FDR com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_latency_timer_1_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_latency_timer_s[1]), + .Q(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_latency_timer[1]), + .R(plm_link_up_i) + ); + MUXCY_L com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_latency_timer_cry_2_ ( + .CI(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_latency_timer_cry[1]), + .DI(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_GND_1341), + .LO(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_latency_timer_cry[2]), + .S(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_latency_timer_qxu[2]) + ); + XORCY com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_latency_timer_s_2_ ( + .CI(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_latency_timer_cry[1]), + .LI(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_latency_timer_qxu[2]), + .O(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_latency_timer_s[2]) + ); + FDR com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_latency_timer_2_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_latency_timer_s[2]), + .Q(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_latency_timer[2]), + .R(plm_link_up_i) + ); + MUXCY_L com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_latency_timer_cry_3_ ( + .CI(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_latency_timer_cry[2]), + .DI(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_GND_1341), + .LO(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_latency_timer_cry[3]), + .S(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_latency_timer_qxu[3]) + ); + XORCY com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_latency_timer_s_3_ ( + .CI(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_latency_timer_cry[2]), + .LI(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_latency_timer_qxu[3]), + .O(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_latency_timer_s[3]) + ); + FDR com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_latency_timer_3_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_latency_timer_s[3]), + .Q(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_latency_timer[3]), + .R(plm_link_up_i) + ); + MUXCY_L com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_latency_timer_cry_4_ ( + .CI(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_latency_timer_cry[3]), + .DI(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_GND_1341), + .LO(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_latency_timer_cry[4]), + .S(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_latency_timer_qxu[4]) + ); + XORCY com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_latency_timer_s_4_ ( + .CI(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_latency_timer_cry[3]), + .LI(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_latency_timer_qxu[4]), + .O(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_latency_timer_s[4]) + ); + FDR com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_latency_timer_4_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_latency_timer_s[4]), + .Q(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_latency_timer[4]), + .R(plm_link_up_i) + ); + MUXCY_L com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_latency_timer_cry_5_ ( + .CI(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_latency_timer_cry[4]), + .DI(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_GND_1341), + .LO(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_latency_timer_cry[5]), + .S(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_latency_timer_qxu[5]) + ); + XORCY com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_latency_timer_s_5_ ( + .CI(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_latency_timer_cry[4]), + .LI(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_latency_timer_qxu[5]), + .O(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_latency_timer_s[5]) + ); + FDR com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_latency_timer_5_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_latency_timer_s[5]), + .Q(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_latency_timer[5]), + .R(plm_link_up_i) + ); + MUXCY_L com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_latency_timer_cry_6_ ( + .CI(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_latency_timer_cry[5]), + .DI(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_GND_1341), + .LO(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_latency_timer_cry[6]), + .S(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_latency_timer_qxu[6]) + ); + XORCY com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_latency_timer_s_6_ ( + .CI(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_latency_timer_cry[5]), + .LI(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_latency_timer_qxu[6]), + .O(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_latency_timer_s[6]) + ); + FDR com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_latency_timer_6_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_latency_timer_s[6]), + .Q(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_latency_timer[6]), + .R(plm_link_up_i) + ); + MUXCY_L com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_latency_timer_cry_7_ ( + .CI(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_latency_timer_cry[6]), + .DI(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_GND_1341), + .LO(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_latency_timer_cry[7]), + .S(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_latency_timer_qxu[7]) + ); + XORCY com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_latency_timer_s_7_ ( + .CI(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_latency_timer_cry[6]), + .LI(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_latency_timer_qxu[7]), + .O(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_latency_timer_s[7]) + ); + FDR com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_latency_timer_7_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_latency_timer_s[7]), + .Q(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_latency_timer[7]), + .R(plm_link_up_i) + ); + MUXCY_L com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_latency_timer_cry_8_ ( + .CI(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_latency_timer_cry[7]), + .DI(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_GND_1341), + .LO(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_latency_timer_cry[8]), + .S(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_latency_timer_qxu[8]) + ); + XORCY com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_latency_timer_s_8_ ( + .CI(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_latency_timer_cry[7]), + .LI(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_latency_timer_qxu[8]), + .O(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_latency_timer_s[8]) + ); + FDR com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_latency_timer_8_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_latency_timer_s[8]), + .Q(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_latency_timer[8]), + .R(plm_link_up_i) + ); + MUXCY_L com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_latency_timer_cry_9_ ( + .CI(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_latency_timer_cry[8]), + .DI(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_GND_1341), + .LO(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_latency_timer_cry[9]), + .S(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_latency_timer_qxu[9]) + ); + XORCY com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_latency_timer_s_9_ ( + .CI(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_latency_timer_cry[8]), + .LI(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_latency_timer_qxu[9]), + .O(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_latency_timer_s[9]) + ); + FDR com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_latency_timer_9_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_latency_timer_s[9]), + .Q(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_latency_timer[9]), + .R(plm_link_up_i) + ); + MUXCY_L com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_latency_timer_cry_10_ ( + .CI(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_latency_timer_cry[9]), + .DI(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_GND_1341), + .LO(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_latency_timer_cry[10]), + .S(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_latency_timer_qxu[10]) + ); + XORCY com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_latency_timer_s_10_ ( + .CI(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_latency_timer_cry[9]), + .LI(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_latency_timer_qxu[10]), + .O(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_latency_timer_s[10]) + ); + FDR com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_latency_timer_10_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_latency_timer_s[10]), + .Q(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_latency_timer[10]), + .R(plm_link_up_i) + ); + MUXCY_L com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_latency_timer_cry_11_ ( + .CI(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_latency_timer_cry[10]), + .DI(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_GND_1341), + .LO(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_latency_timer_cry[11]), + .S(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_latency_timer_qxu[11]) + ); + XORCY com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_latency_timer_s_11_ ( + .CI(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_latency_timer_cry[10]), + .LI(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_latency_timer_qxu[11]), + .O(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_latency_timer_s[11]) + ); + FDR com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_latency_timer_11_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_latency_timer_s[11]), + .Q(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_latency_timer[11]), + .R(plm_link_up_i) + ); + MUXCY_L com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_latency_timer_cry_12_ ( + .CI(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_latency_timer_cry[11]), + .DI(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_GND_1341), + .LO(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_latency_timer_cry[12]), + .S(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_latency_timer_qxu[12]) + ); + XORCY com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_latency_timer_s_12_ ( + .CI(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_latency_timer_cry[11]), + .LI(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_latency_timer_qxu[12]), + .O(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_latency_timer_s[12]) + ); + FDR com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_latency_timer_12_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_latency_timer_s[12]), + .Q(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_latency_timer[12]), + .R(plm_link_up_i) + ); + MUXCY_L com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_latency_timer_cry_13_ ( + .CI(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_latency_timer_cry[12]), + .DI(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_GND_1341), + .LO(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_latency_timer_cry[13]), + .S(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_latency_timer_qxu[13]) + ); + XORCY com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_latency_timer_s_13_ ( + .CI(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_latency_timer_cry[12]), + .LI(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_latency_timer_qxu[13]), + .O(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_latency_timer_s[13]) + ); + FDR com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_latency_timer_13_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_latency_timer_s[13]), + .Q(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_latency_timer[13]), + .R(plm_link_up_i) + ); + XORCY com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_latency_timer_s_14_ ( + .CI(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_latency_timer_cry[13]), + .LI(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_latency_timer_qxu[14]), + .O(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_latency_timer_s[14]) + ); + FDR com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_latency_timer_14_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_latency_timer_s[14]), + .Q(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_latency_timer[14]), + .R(plm_link_up_i) + ); + FDS com_llm_llm_tx_top_llmx08_tx_dllp_jefe_pm_type_q_2_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_N_42763), + .Q(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_pm_type_q[2]), + .S(plm_link_up_i) + ); + FDS com_llm_llm_tx_top_llmx08_tx_dllp_jefe_lnk_tfc_sent_n ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_N_68242_i_1358), + .Q(com_lnk_tfc_sent_n), + .S(com_llm_link_status_0_) + ); + defparam com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_dllp_tx_next_1_sqmuxa_i_0_0_0_o2.INIT = 4'h4; + LUT2 com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_dllp_tx_next_1_sqmuxa_i_0_0_0_o2 ( + .I0(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_an_next_q_1363), + .I1(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_fc_valid_q_1367), + .O(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_N_41717_i) + ); + defparam com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_dllp_pre_i_i_i_a2_0_.INIT = 4'h1; + LUT2 com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_dllp_pre_i_i_i_a2_0_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_an_vld_q_1366), + .I1(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_fc_valid_q_1367), + .O(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_dllp_pre_i_i_i_a2[0]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_expired_lbits12_0.INIT = 4'h6; + LUT2 com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_expired_lbits12_0 ( + .I0(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_latency_timer[0]), + .I1(com_llm_reg_ack_to_val[0]), + .O(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_expired_lbits12_0_1347) + ); + defparam com_llm_llm_tx_top_llmx08_tx_dllp_jefe_un1_an_vld_q_1_i_0_0_0_o4.INIT = 4'h1; + LUT2 com_llm_llm_tx_top_llmx08_tx_dllp_jefe_un1_an_vld_q_1_i_0_0_0_o4 ( + .I0(com_llm_llm_tx_top_tx_dllp_accepted), + .I1(com_llm_llm_tx_top_tx_dllp_vld_n), + .O(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_N_41728_i) + ); + defparam com_llm_llm_tx_top_llmx08_tx_dllp_jefe_un1_an_vld_q_1_i_0_0_0_1_0.INIT = 4'h1; + LUT2 com_llm_llm_tx_top_llmx08_tx_dllp_jefe_un1_an_vld_q_1_i_0_0_0_1_0 ( + .I0(com_llm_reg_tx_dllp_dup_vld), + .I1(com_llm_reg_tx_dllp_nak_vld), + .O(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_N_67829_1) + ); + defparam com_llm_llm_tx_top_llmx08_tx_dllp_jefe_an_next_q_or_tx_fc_valid_q_7_u_0_0_0_o4.INIT = 8'h54; + LUT3 com_llm_llm_tx_top_llmx08_tx_dllp_jefe_an_next_q_or_tx_fc_valid_q_7_u_0_0_0_o4 ( + .I0(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_N_41728_i), + .I1(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_an_next_q_1363), + .I2(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_an_vld_q_1366), + .O(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_N_41722_i) + ); + defparam com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_latency_timer17_i_o2_0_0_o2.INIT = 8'h51; + LUT3 com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_latency_timer17_i_o2_0_0_o2 ( + .I0(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_an_vld_q_1366), + .I1(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_crc_an_vld_q_1342), + .I2(com_llm_llm_tx_top_tx_dllp_accepted), + .O(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_latency_timer17_i_o2_0_0_o2_1396) + ); + defparam com_llm_llm_tx_top_llmx08_tx_dllp_jefe_pm_type_q_4_0_a2_i_a2_2_.INIT = 4'h2; + LUT2 com_llm_llm_tx_top_llmx08_tx_dllp_jefe_pm_type_q_4_0_a2_i_a2_2_ ( + .I0(com_N_41769_i), + .I1(com_st_pm[13]), + .O(com_N_42763) + ); + defparam com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_expired_lbits12_NE_0.INIT = 16'h8421; + LUT4 com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_expired_lbits12_NE_0 ( + .I0(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_latency_timer[6]), + .I1(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_latency_timer[7]), + .I2(com_llm_reg_ack_to_val[6]), + .I3(com_llm_reg_ack_to_val[7]), + .O(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_expired_lbits12_NE_0_1353) + ); + defparam com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_expired_lbits12_NE_1.INIT = 16'h8421; + LUT4 com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_expired_lbits12_NE_1 ( + .I0(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_latency_timer[4]), + .I1(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_latency_timer[5]), + .I2(com_llm_reg_ack_to_val[4]), + .I3(com_llm_reg_ack_to_val[5]), + .O(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_expired_lbits12_NE_1_1352) + ); + defparam com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_expired_lbits12_NE_2.INIT = 16'h8421; + LUT4 com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_expired_lbits12_NE_2 ( + .I0(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_latency_timer[2]), + .I1(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_latency_timer[3]), + .I2(com_llm_reg_ack_to_val[2]), + .I3(com_llm_reg_ack_to_val[3]), + .O(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_expired_lbits12_NE_2_1346) + ); + defparam com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_expired_hbits12_NE_0.INIT = 16'h8421; + LUT4 com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_expired_hbits12_NE_0 ( + .I0(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_latency_timer[13]), + .I1(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_latency_timer[14]), + .I2(com_llm_reg_ack_to_val[13]), + .I3(com_llm_reg_ack_to_val[14]), + .O(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_expired_hbits12_NE_0_1357) + ); + defparam com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_expired_hbits12_NE_1.INIT = 16'h8421; + LUT4 com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_expired_hbits12_NE_1 ( + .I0(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_latency_timer[11]), + .I1(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_latency_timer[12]), + .I2(com_llm_reg_ack_to_val[11]), + .I3(com_llm_reg_ack_to_val[12]), + .O(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_expired_hbits12_NE_1_1356) + ); + defparam com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_expired_hbits12_NE_2.INIT = 16'h8421; + LUT4_L com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_expired_hbits12_NE_2 ( + .I0(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_latency_timer[8]), + .I1(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_latency_timer[10]), + .I2(com_llm_reg_ack_to_val[8]), + .I3(com_llm_reg_ack_to_val[10]), + .LO(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_expired_hbits12_NE_2_1348) + ); + defparam com_llm_llm_tx_top_llmx08_tx_dllp_jefe_N_42781_i.INIT = 8'hDF; + LUT3 com_llm_llm_tx_top_llmx08_tx_dllp_jefe_N_42781_i ( + .I0(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_N_41728_i), + .I1(com_llm_link_status_0_), + .I2(plm_link_up_1), + .O(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_N_42781_i_1343) + ); + defparam com_llm_llm_tx_top_llmx08_tx_dllp_jefe_an_next_q_or_tx_fc_valid_q_7_u_0_0_0_o4_0.INIT = 8'hE0; + LUT3 com_llm_llm_tx_top_llmx08_tx_dllp_jefe_an_next_q_or_tx_fc_valid_q_7_u_0_0_0_o4_0 ( + .I0(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_N_41728_i), + .I1(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_an_next_q_1363), + .I2(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_fc_valid_q_1367), + .O(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_N_41762_i) + ); + defparam com_llm_llm_tx_top_llmx08_tx_dllp_jefe_un1_an_vld_q_1_i_0_0_0_1.INIT = 16'hBBAB; + LUT4 com_llm_llm_tx_top_llmx08_tx_dllp_jefe_un1_an_vld_q_1_i_0_0_0_1 ( + .I0(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_N_41728_i), + .I1(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_an_next_q_1363), + .I2(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_an_vld_q_1366), + .I3(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_fc_valid_q_1367), + .O(com_llm_N_38737_1_i) + ); + defparam com_llm_llm_tx_top_llmx08_tx_dllp_jefe_an_next_q_or_tx_fc_valid_q_7_u_0_0_0_o4_1.INIT = 16'h2AAA; + LUT4 com_llm_llm_tx_top_llmx08_tx_dllp_jefe_an_next_q_or_tx_fc_valid_q_7_u_0_0_0_o4_1 ( + .I0(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_N_67829_1), + .I1(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_expired_hbits_1345), + .I2(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_expired_lbits_1344), + .I3(com_llm_reg_tx_dllp_ack_vld), + .O(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_an_next_q_or_tx_fc_valid_q_7_u_0_0_0_o4_1_1360) + ); + defparam com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_expired_lbits12_NE_4.INIT = 16'h4004; + LUT4 com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_expired_lbits12_NE_4 ( + .I0(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_expired_lbits12_0_1347), + .I1(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_expired_lbits12_NE_2_1346), + .I2(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_latency_timer[1]), + .I3(com_llm_reg_ack_to_val[1]), + .O(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_expired_lbits12_NE_4_1351) + ); + defparam com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_expired_hbits12_NE_3.INIT = 8'h82; + LUT3 com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_expired_hbits12_NE_3 ( + .I0(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_expired_hbits12_NE_2_1348), + .I1(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_latency_timer[9]), + .I2(com_llm_reg_ack_to_val[9]), + .O(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_expired_hbits12_NE_3_1355) + ); + defparam com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_dllp_tx_next_9_f0_i_0_0_0.INIT = 16'h5540; + LUT4 com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_dllp_tx_next_9_f0_i_0_0_0 ( + .I0(com_llm_link_status_0_), + .I1(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_an_next_q_1363), + .I2(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_an_vld_q_1366), + .I3(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_fc_valid_q_1367), + .O(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_dllp_tx_next_9_f0_i_0_0_0_1362) + ); + defparam com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_fc_valid_q8_i_0_0.INIT = 4'h4; + LUT2 com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_fc_valid_q8_i_0_0 ( + .I0(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_N_41762_i), + .I1(plm_link_up_1), + .O(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_N_12558_i) + ); + defparam com_llm_llm_tx_top_llmx08_tx_dllp_jefe_N_67829_i.INIT = 8'hF7; + LUT3 com_llm_llm_tx_top_llmx08_tx_dllp_jefe_N_67829_i ( + .I0(com_llm_N_38737_1_i), + .I1(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_N_67829_1), + .I2(com_llm_reg_tx_dllp_ack_vld), + .O(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_N_67829_i_1349) + ); + defparam com_llm_llm_tx_top_llmx08_tx_dllp_jefe_an_next_q_or_tx_fc_valid_q_7_u_0_0_0_1.INIT = 8'hCE; + LUT3_L com_llm_llm_tx_top_llmx08_tx_dllp_jefe_an_next_q_or_tx_fc_valid_q_7_u_0_0_0_1 ( + .I0(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_N_41722_i), + .I1(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_an_next_q_or_tx_fc_valid_q_7_u_0_0_0_o4_1_1360), + .I2(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_fc_valid_q_1367), + .LO(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_an_next_q_or_tx_fc_valid_q_7_u_0_0_0_1_1365) + ); + defparam com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_expired_lbits_1_sqmuxa_i.INIT = 16'hEAAA; + LUT4 com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_expired_lbits_1_sqmuxa_i ( + .I0(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_latency_timer17_i_o2_0_0_o2_1396), + .I1(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_expired_lbits12_NE_0_1353), + .I2(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_expired_lbits12_NE_1_1352), + .I3(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_expired_lbits12_NE_4_1351), + .O(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_expired_lbits_1_sqmuxa_i_1350) + ); + defparam com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_expired_hbits_1_sqmuxa_i.INIT = 16'hEAAA; + LUT4 com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_expired_hbits_1_sqmuxa_i ( + .I0(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_latency_timer17_i_o2_0_0_o2_1396), + .I1(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_expired_hbits12_NE_0_1357), + .I2(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_expired_hbits12_NE_1_1356), + .I3(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_expired_hbits12_NE_3_1355), + .O(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_expired_hbits_1_sqmuxa_i_1354) + ); + defparam com_llm_llm_tx_top_llmx08_tx_dllp_jefe_N_68242_i.INIT = 8'hDF; + LUT3_L com_llm_llm_tx_top_llmx08_tx_dllp_jefe_N_68242_i ( + .I0(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_N_41717_i), + .I1(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_N_41728_i), + .I2(plm_link_up_1), + .LO(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_N_68242_i_1358) + ); + defparam com_llm_llm_tx_top_llmx08_tx_dllp_jefe_pm_type_d24_0_a2_0_a2.INIT = 4'h8; + LUT2_L com_llm_llm_tx_top_llmx08_tx_dllp_jefe_pm_type_d24_0_a2_0_a2 ( + .I0(com_N_41769_i), + .I1(com_st_pm[13]), + .LO(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_pm_type_d24) + ); + defparam com_llm_llm_tx_top_llmx08_tx_dllp_jefe_N_68886_i.INIT = 4'hE; + LUT2_L com_llm_llm_tx_top_llmx08_tx_dllp_jefe_N_68886_i ( + .I0(com_llm_link_status_0_), + .I1(com_llm_llm_tx_top_tx_dllp_vld_pre_n), + .LO(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_N_68886_i_1359) + ); + defparam com_llm_llm_tx_top_llmx08_tx_dllp_jefe_reg_tx_djefe_idle_3_0_a2_0_a2.INIT = 8'h80; + LUT3_L com_llm_llm_tx_top_llmx08_tx_dllp_jefe_reg_tx_djefe_idle_3_0_a2_0_a2 ( + .I0(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_dllp_pre_i_i_i_a2[0]), + .I1(com_N_42763), + .I2(com_llm_llm_tx_top_tx_dllp_vld_n), + .LO(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_reg_tx_djefe_idle_3) + ); + defparam com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_dllp_tx_next_0_sqmuxa_i_0_0.INIT = 16'h0400; + LUT4_L com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_dllp_tx_next_0_sqmuxa_i_0_0 ( + .I0(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_N_41717_i), + .I1(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_N_41722_i), + .I2(com_llm_link_status_0_), + .I3(plm_link_up_2), + .LO(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_N_12555_i) + ); + defparam com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_dllp_pre_0_a2_0_a2_0_a2_31_.INIT = 4'h8; + LUT2_L com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_dllp_pre_0_a2_0_a2_0_a2_31_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_N_41717_i), + .I1(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_fc_data_q_31__1368), + .LO(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_dllp_pre_31_) + ); + defparam com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_dllp_pre_0_a2_0_a2_0_a2_30_.INIT = 4'h8; + LUT2_L com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_dllp_pre_0_a2_0_a2_0_a2_30_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_N_41717_i), + .I1(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_fc_data_q_30__1369), + .LO(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_dllp_pre_30_) + ); + defparam com_llm_llm_tx_top_llmx08_tx_dllp_jefe_N_68927_i.INIT = 8'hEC; + LUT3_L com_llm_llm_tx_top_llmx08_tx_dllp_jefe_N_68927_i ( + .I0(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_N_41717_i), + .I1(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_dllp_pre_i_i_i_a2[0]), + .I2(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_fc_data_q_29__1370), + .LO(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_N_68927_i_1392) + ); + defparam com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_dllp_pre_i_i_i_28_.INIT = 16'h3120; + LUT4_L com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_dllp_pre_i_i_i_28_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_N_41717_i), + .I1(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_dllp_pre_i_i_i_a2[0]), + .I2(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_fc_data_q_28__1371), + .I3(com_llm_reg_tx_dllp_nak_vld), + .LO(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_N_41003_i) + ); + defparam com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_dllp_pre_i_0_0_25_.INIT = 8'h04; + LUT3_L com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_dllp_pre_i_0_0_25_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_an_vld_q_1366), + .I1(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_pm_type_q[1]), + .I2(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_fc_valid_q_1367), + .LO(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_N_12613_i) + ); + defparam com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_dllp_pre_i_0_0_24_.INIT = 8'h04; + LUT3_L com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_dllp_pre_i_0_0_24_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_an_vld_q_1366), + .I1(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_pm_type_q[0]), + .I2(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_fc_valid_q_1367), + .LO(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_N_12611_i) + ); + defparam com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_dllp_pre_0_a2_0_a2_0_a2_21_.INIT = 4'h8; + LUT2_L com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_dllp_pre_0_a2_0_a2_0_a2_21_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_N_41717_i), + .I1(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_fc_data_q_21__1372), + .LO(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_dllp_pre_21_) + ); + defparam com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_dllp_pre_0_a2_0_a2_0_a2_20_.INIT = 4'h8; + LUT2_L com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_dllp_pre_0_a2_0_a2_0_a2_20_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_N_41717_i), + .I1(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_fc_data_q_20__1373), + .LO(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_dllp_pre_20_) + ); + defparam com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_dllp_pre_0_a2_0_a2_0_a2_19_.INIT = 4'h8; + LUT2_L com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_dllp_pre_0_a2_0_a2_0_a2_19_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_N_41717_i), + .I1(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_fc_data_q_19__1374), + .LO(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_dllp_pre_19_) + ); + defparam com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_dllp_pre_0_a2_0_a2_0_a2_18_.INIT = 4'h8; + LUT2_L com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_dllp_pre_0_a2_0_a2_0_a2_18_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_N_41717_i), + .I1(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_fc_data_q_18__1375), + .LO(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_dllp_pre_18_) + ); + defparam com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_dllp_pre_0_a2_0_a2_0_a2_17_.INIT = 4'h8; + LUT2_L com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_dllp_pre_0_a2_0_a2_0_a2_17_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_N_41717_i), + .I1(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_fc_data_q_17__1376), + .LO(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_dllp_pre_17_) + ); + defparam com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_dllp_pre_0_a2_0_a2_0_a2_16_.INIT = 4'h8; + LUT2_L com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_dllp_pre_0_a2_0_a2_0_a2_16_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_N_41717_i), + .I1(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_fc_data_q_16__1377), + .LO(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_dllp_pre_16_) + ); + defparam com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_dllp_pre_0_a2_0_a2_0_a2_15_.INIT = 4'h8; + LUT2_L com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_dllp_pre_0_a2_0_a2_0_a2_15_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_N_41717_i), + .I1(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_fc_data_q_15__1378), + .LO(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_dllp_pre_15_) + ); + defparam com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_dllp_pre_0_a2_0_a2_0_a2_14_.INIT = 4'h8; + LUT2_L com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_dllp_pre_0_a2_0_a2_0_a2_14_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_N_41717_i), + .I1(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_fc_data_q_14__1379), + .LO(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_dllp_pre_14_) + ); + defparam com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_dllp_pre_i_i_i_11_.INIT = 16'h3120; + LUT4_L com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_dllp_pre_i_i_i_11_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_N_41717_i), + .I1(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_dllp_pre_i_i_i_a2[0]), + .I2(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_fc_data_q_11__1380), + .I3(com_llm_reg_tx_dllp_tsn[11]), + .LO(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_N_41001_i) + ); + defparam com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_dllp_pre_i_i_i_10_.INIT = 16'h3120; + LUT4_L com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_dllp_pre_i_i_i_10_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_N_41717_i), + .I1(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_dllp_pre_i_i_i_a2[0]), + .I2(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_fc_data_q_10__1381), + .I3(com_llm_reg_tx_dllp_tsn[10]), + .LO(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_N_40999_i) + ); + defparam com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_dllp_pre_i_i_i_9_.INIT = 16'h3120; + LUT4_L com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_dllp_pre_i_i_i_9_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_N_41717_i), + .I1(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_dllp_pre_i_i_i_a2[0]), + .I2(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_fc_data_q_9__1382), + .I3(com_llm_reg_tx_dllp_tsn[9]), + .LO(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_N_40997_i) + ); + defparam com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_dllp_pre_i_i_i_8_.INIT = 16'h3120; + LUT4_L com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_dllp_pre_i_i_i_8_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_N_41717_i), + .I1(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_dllp_pre_i_i_i_a2[0]), + .I2(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_fc_data_q_8__1383), + .I3(com_llm_reg_tx_dllp_tsn[8]), + .LO(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_N_40995_i) + ); + defparam com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_dllp_pre_i_i_i_7_.INIT = 16'h3120; + LUT4_L com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_dllp_pre_i_i_i_7_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_N_41717_i), + .I1(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_dllp_pre_i_i_i_a2[0]), + .I2(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_fc_data_q_7__1384), + .I3(com_llm_reg_tx_dllp_tsn[7]), + .LO(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_N_40993_i) + ); + defparam com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_dllp_pre_i_i_i_6_.INIT = 16'h3120; + LUT4_L com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_dllp_pre_i_i_i_6_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_N_41717_i), + .I1(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_dllp_pre_i_i_i_a2[0]), + .I2(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_fc_data_q_6__1385), + .I3(com_llm_reg_tx_dllp_tsn[6]), + .LO(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_N_40991_i) + ); + defparam com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_dllp_pre_i_i_i_5_.INIT = 16'h3120; + LUT4_L com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_dllp_pre_i_i_i_5_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_N_41717_i), + .I1(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_dllp_pre_i_i_i_a2[0]), + .I2(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_fc_data_q_5__1386), + .I3(com_llm_reg_tx_dllp_tsn[5]), + .LO(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_N_40989_i) + ); + defparam com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_dllp_pre_i_i_i_4_.INIT = 16'h3120; + LUT4_L com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_dllp_pre_i_i_i_4_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_N_41717_i), + .I1(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_dllp_pre_i_i_i_a2[0]), + .I2(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_fc_data_q_4__1387), + .I3(com_llm_reg_tx_dllp_tsn[4]), + .LO(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_N_40987_i) + ); + defparam com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_dllp_pre_i_i_i_3_.INIT = 16'h3120; + LUT4_L com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_dllp_pre_i_i_i_3_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_N_41717_i), + .I1(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_dllp_pre_i_i_i_a2[0]), + .I2(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_fc_data_q_3__1388), + .I3(com_llm_reg_tx_dllp_tsn[3]), + .LO(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_N_40985_i) + ); + defparam com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_dllp_pre_i_i_i_2_.INIT = 16'h3120; + LUT4_L com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_dllp_pre_i_i_i_2_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_N_41717_i), + .I1(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_dllp_pre_i_i_i_a2[0]), + .I2(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_fc_data_q_2__1389), + .I3(com_llm_reg_tx_dllp_tsn[2]), + .LO(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_N_40983_i) + ); + defparam com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_dllp_pre_i_i_i_1_.INIT = 16'h3120; + LUT4_L com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_dllp_pre_i_i_i_1_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_N_41717_i), + .I1(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_dllp_pre_i_i_i_a2[0]), + .I2(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_fc_data_q_1__1390), + .I3(com_llm_reg_tx_dllp_tsn[1]), + .LO(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_N_40981_i) + ); + defparam com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_dllp_pre_i_i_i_0_.INIT = 16'h3120; + LUT4_L com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_dllp_pre_i_i_i_0_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_N_41717_i), + .I1(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_dllp_pre_i_i_i_a2[0]), + .I2(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_fc_data_q_0__1391), + .I3(com_llm_reg_tx_dllp_tsn[0]), + .LO(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_N_40979_i) + ); + defparam com_llm_llm_tx_top_llmx08_tx_dllp_jefe_an_next_q_5_0_a2_0_a2_0_a2.INIT = 8'h0B; + LUT3_L com_llm_llm_tx_top_llmx08_tx_dllp_jefe_an_next_q_5_0_a2_0_a2_0_a2 ( + .I0(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_N_41717_i), + .I1(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_N_41722_i), + .I2(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_an_next_q_or_tx_fc_valid_q_7_u_0_0_0_o4_1_1360), + .LO(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_an_next_q_5) + ); + defparam com_llm_llm_tx_top_llmx08_tx_dllp_jefe_N_30913_i_i_i.INIT = 4'hB; + LUT2_L com_llm_llm_tx_top_llmx08_tx_dllp_jefe_N_30913_i_i_i ( + .I0(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_N_41717_i), + .I1(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_N_41722_i), + .LO(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_N_30913_i_i_i_1361) + ); + defparam com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_dllp_tx_next_9_f0_i_0_0.INIT = 16'hD0C0; + LUT4_L com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_dllp_tx_next_9_f0_i_0_0 ( + .I0(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_N_41728_i), + .I1(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_an_next_q_1363), + .I2(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_dllp_tx_next_9_f0_i_0_0_0_1362), + .I3(plm_link_up_2), + .LO(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_N_12579_i) + ); + defparam com_llm_llm_tx_top_llmx08_tx_dllp_jefe_N_67930_i.INIT = 8'hBF; + LUT3_L com_llm_llm_tx_top_llmx08_tx_dllp_jefe_N_67930_i ( + .I0(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_N_41762_i), + .I1(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_an_next_q_or_tx_fc_valid_q_7_u_0_0_0_1_1365), + .I2(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_fc_queue_empty), + .LO(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_N_67930_i_1364) + ); + defparam com_llm_llm_tx_top_llmx08_tx_dllp_jefe_un1_tx_dllp_vld_pre_n_0_a2_0_a2_0_a2.INIT = 8'h02; + LUT3 com_llm_llm_tx_top_llmx08_tx_dllp_jefe_un1_tx_dllp_vld_pre_n_0_a2_0_a2_0_a2 ( + .I0(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_pm_type_q[2]), + .I1(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_fc_valid_q_1367), + .I2(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_an_vld_q_1366), + .O(com_llm_llm_tx_top_tx_dllp_vld_pre_n) + ); + FD com_llm_llm_tx_top_llmx08_tx_dllp_jefe_pm_type_q_1_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_pm_type_d24), + .Q(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_pm_type_q[1]) + ); + FD com_llm_llm_tx_top_llmx08_tx_dllp_jefe_pm_type_q_0_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_st_pm_i[17]), + .Q(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_pm_type_q[0]) + ); + FDE com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_fc_data_q_31_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_N_12558_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_fc_dout_31_), + .Q(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_fc_data_q_31__1368) + ); + FDE com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_fc_data_q_30_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_N_12558_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_fc_dout_30_), + .Q(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_fc_data_q_30__1369) + ); + FDE com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_fc_data_q_29_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_N_12558_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_fc_dout_29_), + .Q(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_fc_data_q_29__1370) + ); + FDE com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_fc_data_q_28_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_N_12558_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_fc_dout_28_), + .Q(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_fc_data_q_28__1371) + ); + FDE com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_fc_data_q_21_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_N_12558_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_fc_dout_21_), + .Q(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_fc_data_q_21__1372) + ); + FDE com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_fc_data_q_20_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_N_12558_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_fc_dout_20_), + .Q(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_fc_data_q_20__1373) + ); + FDE com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_fc_data_q_19_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_N_12558_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_fc_dout_19_), + .Q(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_fc_data_q_19__1374) + ); + FDE com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_fc_data_q_18_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_N_12558_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_fc_dout_18_), + .Q(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_fc_data_q_18__1375) + ); + FDE com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_fc_data_q_17_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_N_12558_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_fc_dout_17_), + .Q(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_fc_data_q_17__1376) + ); + FDE com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_fc_data_q_16_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_N_12558_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_fc_dout_16_), + .Q(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_fc_data_q_16__1377) + ); + FDE com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_fc_data_q_15_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_N_12558_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_fc_dout_15_), + .Q(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_fc_data_q_15__1378) + ); + FDE com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_fc_data_q_14_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_N_12558_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_fc_dout_14_), + .Q(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_fc_data_q_14__1379) + ); + FDE com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_fc_data_q_11_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_N_12558_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_fc_dout_11_), + .Q(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_fc_data_q_11__1380) + ); + FDE com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_fc_data_q_10_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_N_12558_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_fc_dout_10_), + .Q(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_fc_data_q_10__1381) + ); + FDE com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_fc_data_q_9_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_N_12558_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_fc_dout_9_), + .Q(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_fc_data_q_9__1382) + ); + FDE com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_fc_data_q_8_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_N_12558_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_fc_dout_8_), + .Q(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_fc_data_q_8__1383) + ); + FDE com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_fc_data_q_7_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_N_12558_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_fc_dout_7_), + .Q(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_fc_data_q_7__1384) + ); + FDE com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_fc_data_q_6_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_N_12558_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_fc_dout_6_), + .Q(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_fc_data_q_6__1385) + ); + FDE com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_fc_data_q_5_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_N_12558_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_fc_dout_5_), + .Q(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_fc_data_q_5__1386) + ); + FDE com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_fc_data_q_4_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_N_12558_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_fc_dout_4_), + .Q(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_fc_data_q_4__1387) + ); + FDE com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_fc_data_q_3_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_N_12558_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_fc_dout_3_), + .Q(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_fc_data_q_3__1388) + ); + FDE com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_fc_data_q_2_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_N_12558_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_fc_dout_2_), + .Q(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_fc_data_q_2__1389) + ); + FDE com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_fc_data_q_1_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_N_12558_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_fc_dout_1_), + .Q(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_fc_data_q_1__1390) + ); + FDE com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_fc_data_q_0_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_N_12558_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_fc_dout_0_), + .Q(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_fc_data_q_0__1391) + ); + FDE com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_dllp_td_1_55_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_N_41728_i_i_1393), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_dllp_pre_31_), + .Q(com_llm_llm_tx_top_tx_dllp_td_55_) + ); + FDE com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_dllp_td_1_54_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_N_41728_i_i_1393), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_dllp_pre_30_), + .Q(com_llm_llm_tx_top_tx_dllp_td_54_) + ); + FDE com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_dllp_td_1_53_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_N_41728_i_i_1393), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_N_68927_i_1392), + .Q(com_llm_llm_tx_top_tx_dllp_td_53_) + ); + FDE com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_dllp_td_1_52_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_N_41728_i_i_1393), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_N_41003_i), + .Q(com_llm_llm_tx_top_tx_dllp_td_52_) + ); + FDE com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_dllp_td_1_49_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_N_41728_i_i_1393), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_N_12613_i), + .Q(com_llm_llm_tx_top_tx_dllp_td_49_) + ); + FDE com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_dllp_td_1_48_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_N_41728_i_i_1393), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_N_12611_i), + .Q(com_llm_llm_tx_top_tx_dllp_td_48_) + ); + FDE com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_dllp_td_1_45_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_N_41728_i_i_1393), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_dllp_pre_21_), + .Q(com_llm_llm_tx_top_tx_dllp_td_45_) + ); + FDE com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_dllp_td_1_44_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_N_41728_i_i_1393), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_dllp_pre_20_), + .Q(com_llm_llm_tx_top_tx_dllp_td_44_) + ); + FDE com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_dllp_td_1_43_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_N_41728_i_i_1393), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_dllp_pre_19_), + .Q(com_llm_llm_tx_top_tx_dllp_td_43_) + ); + FDE com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_dllp_td_1_42_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_N_41728_i_i_1393), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_dllp_pre_18_), + .Q(com_llm_llm_tx_top_tx_dllp_td_42_) + ); + FDE com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_dllp_td_1_41_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_N_41728_i_i_1393), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_dllp_pre_17_), + .Q(com_llm_llm_tx_top_tx_dllp_td_41_) + ); + FDE com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_dllp_td_1_40_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_N_41728_i_i_1393), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_dllp_pre_16_), + .Q(com_llm_llm_tx_top_tx_dllp_td_40_) + ); + FDE com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_dllp_td_1_39_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_N_41728_i_i_1393), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_dllp_pre_15_), + .Q(com_llm_llm_tx_top_tx_dllp_td_39_) + ); + FDE com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_dllp_td_1_38_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_N_41728_i_i_1393), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_dllp_pre_14_), + .Q(com_llm_llm_tx_top_tx_dllp_td_38_) + ); + FDE com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_dllp_td_1_35_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_N_41728_i_i_1393), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_N_41001_i), + .Q(com_llm_llm_tx_top_tx_dllp_td_35_) + ); + FDE com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_dllp_td_1_34_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_N_41728_i_i_1393), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_N_40999_i), + .Q(com_llm_llm_tx_top_tx_dllp_td_34_) + ); + FDE com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_dllp_td_1_33_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_N_41728_i_i_1393), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_N_40997_i), + .Q(com_llm_llm_tx_top_tx_dllp_td_33_) + ); + FDE com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_dllp_td_1_32_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_N_41728_i_i_1393), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_N_40995_i), + .Q(com_llm_llm_tx_top_tx_dllp_td_32_) + ); + FDE com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_dllp_td_1_31_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_N_41728_i_i_1393), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_N_40993_i), + .Q(com_llm_llm_tx_top_tx_dllp_td_31_) + ); + FDE com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_dllp_td_1_30_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_N_41728_i_i_1393), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_N_40991_i), + .Q(com_llm_llm_tx_top_tx_dllp_td_30_) + ); + FDE com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_dllp_td_1_29_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_N_41728_i_i_1393), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_N_40989_i), + .Q(com_llm_llm_tx_top_tx_dllp_td_29_) + ); + FDE com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_dllp_td_1_28_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_N_41728_i_i_1393), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_N_40987_i), + .Q(com_llm_llm_tx_top_tx_dllp_td_28_) + ); + FDE com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_dllp_td_1_27_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_N_41728_i_i_1393), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_N_40985_i), + .Q(com_llm_llm_tx_top_tx_dllp_td_27_) + ); + FDE com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_dllp_td_1_26_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_N_41728_i_i_1393), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_N_40983_i), + .Q(com_llm_llm_tx_top_tx_dllp_td_26_) + ); + FDE com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_dllp_td_1_25_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_N_41728_i_i_1393), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_N_40981_i), + .Q(com_llm_llm_tx_top_tx_dllp_td_25_) + ); + FDE com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_dllp_td_1_24_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_N_41728_i_i_1393), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_N_40979_i), + .Q(com_llm_llm_tx_top_tx_dllp_td_24_) + ); + INV com_llm_llm_tx_top_llmx08_tx_dllp_jefe_N_41728_i_i ( + .I(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_N_41728_i), + .O(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_N_41728_i_i_1393) + ); + INV com_llm_llm_tx_top_llmx08_tx_dllp_jefe_N_69205_i ( + .I(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_latency_timer17_i_o2_0_0_o2_1396), + .O(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_N_69205_i_1394) + ); + INV com_llm_llm_tx_top_llmx08_tx_dllp_jefe_N_41762_i_i ( + .I(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_N_41762_i), + .O(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_N_41762_i_i_1395) + ); + defparam com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_latency_timer_qxu_0_14_.INIT = 4'h4; + LUT2_L com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_latency_timer_qxu_0_14_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_latency_timer17_i_o2_0_0_o2_1396), + .I1(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_latency_timer[14]), + .LO(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_latency_timer_qxu[14]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_latency_timer_qxu_0_13_.INIT = 4'h4; + LUT2_L com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_latency_timer_qxu_0_13_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_latency_timer17_i_o2_0_0_o2_1396), + .I1(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_latency_timer[13]), + .LO(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_latency_timer_qxu[13]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_latency_timer_qxu_0_12_.INIT = 4'h4; + LUT2_L com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_latency_timer_qxu_0_12_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_latency_timer17_i_o2_0_0_o2_1396), + .I1(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_latency_timer[12]), + .LO(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_latency_timer_qxu[12]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_latency_timer_qxu_0_11_.INIT = 4'h4; + LUT2_L com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_latency_timer_qxu_0_11_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_latency_timer17_i_o2_0_0_o2_1396), + .I1(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_latency_timer[11]), + .LO(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_latency_timer_qxu[11]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_latency_timer_qxu_0_10_.INIT = 4'h4; + LUT2_L com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_latency_timer_qxu_0_10_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_latency_timer17_i_o2_0_0_o2_1396), + .I1(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_latency_timer[10]), + .LO(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_latency_timer_qxu[10]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_latency_timer_qxu_0_9_.INIT = 4'h4; + LUT2_L com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_latency_timer_qxu_0_9_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_latency_timer17_i_o2_0_0_o2_1396), + .I1(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_latency_timer[9]), + .LO(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_latency_timer_qxu[9]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_latency_timer_qxu_0_8_.INIT = 4'h4; + LUT2_L com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_latency_timer_qxu_0_8_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_latency_timer17_i_o2_0_0_o2_1396), + .I1(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_latency_timer[8]), + .LO(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_latency_timer_qxu[8]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_latency_timer_qxu_0_7_.INIT = 4'h4; + LUT2_L com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_latency_timer_qxu_0_7_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_latency_timer17_i_o2_0_0_o2_1396), + .I1(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_latency_timer[7]), + .LO(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_latency_timer_qxu[7]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_latency_timer_qxu_0_6_.INIT = 4'h4; + LUT2_L com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_latency_timer_qxu_0_6_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_latency_timer17_i_o2_0_0_o2_1396), + .I1(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_latency_timer[6]), + .LO(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_latency_timer_qxu[6]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_latency_timer_qxu_0_5_.INIT = 4'h4; + LUT2_L com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_latency_timer_qxu_0_5_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_latency_timer17_i_o2_0_0_o2_1396), + .I1(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_latency_timer[5]), + .LO(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_latency_timer_qxu[5]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_latency_timer_qxu_0_4_.INIT = 4'h4; + LUT2_L com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_latency_timer_qxu_0_4_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_latency_timer17_i_o2_0_0_o2_1396), + .I1(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_latency_timer[4]), + .LO(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_latency_timer_qxu[4]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_latency_timer_qxu_0_3_.INIT = 4'h4; + LUT2_L com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_latency_timer_qxu_0_3_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_latency_timer17_i_o2_0_0_o2_1396), + .I1(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_latency_timer[3]), + .LO(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_latency_timer_qxu[3]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_latency_timer_qxu_0_2_.INIT = 4'h4; + LUT2_L com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_latency_timer_qxu_0_2_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_latency_timer17_i_o2_0_0_o2_1396), + .I1(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_latency_timer[2]), + .LO(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_latency_timer_qxu[2]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_latency_timer_qxu_0_1_.INIT = 4'h4; + LUT2_L com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_latency_timer_qxu_0_1_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_latency_timer17_i_o2_0_0_o2_1396), + .I1(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_latency_timer[1]), + .LO(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_latency_timer_qxu[1]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_latency_timer_qxu_0_0_.INIT = 4'h4; + LUT2_L com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_latency_timer_qxu_0_0_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_latency_timer17_i_o2_0_0_o2_1396), + .I1(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_latency_timer[0]), + .LO(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_latency_timer_qxu[0]) + ); + GND com_llm_llm_tx_top_llmx08_tx_dllp_jefe_llm32_fc_fifo_GND ( + .G(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_llm32_fc_fifo_GND_1397) + ); + FDR com_llm_llm_tx_top_llmx08_tx_dllp_jefe_llm32_fc_fifo_data_count_0_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_llm32_fc_fifo_un1_data_count_3_axb_0_1404), + .Q(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_llm32_fc_fifo_data_count[0]), + .R(plm_link_up_i) + ); + FDR com_llm_llm_tx_top_llmx08_tx_dllp_jefe_llm32_fc_fifo_data_count_1_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_llm32_fc_fifo_un1_data_count_3_s_1_1398), + .Q(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_llm32_fc_fifo_data_count[1]), + .R(plm_link_up_i) + ); + FDR com_llm_llm_tx_top_llmx08_tx_dllp_jefe_llm32_fc_fifo_data_count_2_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_llm32_fc_fifo_un1_data_count_3_s_2_1400), + .Q(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_llm32_fc_fifo_data_count[2]), + .R(plm_link_up_i) + ); + FDR com_llm_llm_tx_top_llmx08_tx_dllp_jefe_llm32_fc_fifo_data_count_3_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_llm32_fc_fifo_un1_data_count_3_s_3_1402), + .Q(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_llm32_fc_fifo_data_count[3]), + .R(plm_link_up_i) + ); + FDSE com_llm_llm_tx_top_llmx08_tx_dllp_jefe_llm32_fc_fifo_empty ( + .CE(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_llm32_fc_fifo_N_68899_i_1405), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_N_51187_i), + .Q(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_fc_queue_empty), + .S(plm_link_up_i) + ); + FDRE com_llm_llm_tx_top_llmx08_tx_dllp_jefe_llm32_fc_fifo_full ( + .CE(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_llm32_fc_fifo_un1_rd_en_4_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_N_41762_i), + .Q(com_lnk_tfc_dst_rdy_n), + .R(plm_link_up_i) + ); + MUXCY_L com_llm_llm_tx_top_llmx08_tx_dllp_jefe_llm32_fc_fifo_un1_data_count_3_cry_0 ( + .CI(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_llm32_fc_fifo_GND_1397), + .DI(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_llm32_fc_fifo_data_count[0]), + .LO(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_llm32_fc_fifo_un1_data_count_3_cry_0_1399), + .S(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_llm32_fc_fifo_un1_data_count_3_axb_0_1404) + ); + MUXCY_L com_llm_llm_tx_top_llmx08_tx_dllp_jefe_llm32_fc_fifo_un1_data_count_3_cry_1 ( + .CI(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_llm32_fc_fifo_un1_data_count_3_cry_0_1399), + .DI(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_llm32_fc_fifo_data_count[1]), + .LO(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_llm32_fc_fifo_un1_data_count_3_cry_1_1401), + .S(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_llm32_fc_fifo_un1_data_count_3_axb_1_1408) + ); + XORCY com_llm_llm_tx_top_llmx08_tx_dllp_jefe_llm32_fc_fifo_un1_data_count_3_s_1 ( + .CI(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_llm32_fc_fifo_un1_data_count_3_cry_0_1399), + .LI(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_llm32_fc_fifo_un1_data_count_3_axb_1_1408), + .O(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_llm32_fc_fifo_un1_data_count_3_s_1_1398) + ); + MUXCY_L com_llm_llm_tx_top_llmx08_tx_dllp_jefe_llm32_fc_fifo_un1_data_count_3_cry_2 ( + .CI(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_llm32_fc_fifo_un1_data_count_3_cry_1_1401), + .DI(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_llm32_fc_fifo_data_count[2]), + .LO(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_llm32_fc_fifo_un1_data_count_3_cry_2_1403), + .S(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_llm32_fc_fifo_un1_data_count_3_axb_2_1407) + ); + XORCY com_llm_llm_tx_top_llmx08_tx_dllp_jefe_llm32_fc_fifo_un1_data_count_3_s_2 ( + .CI(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_llm32_fc_fifo_un1_data_count_3_cry_1_1401), + .LI(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_llm32_fc_fifo_un1_data_count_3_axb_2_1407), + .O(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_llm32_fc_fifo_un1_data_count_3_s_2_1400) + ); + XORCY com_llm_llm_tx_top_llmx08_tx_dllp_jefe_llm32_fc_fifo_un1_data_count_3_s_3 ( + .CI(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_llm32_fc_fifo_un1_data_count_3_cry_2_1403), + .LI(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_llm32_fc_fifo_un1_data_count_3_axb_3_1406), + .O(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_llm32_fc_fifo_un1_data_count_3_s_3_1402) + ); + defparam com_llm_llm_tx_top_llmx08_tx_dllp_jefe_llm32_fc_fifo_un1_wr_en_5_i_0_0_0_a2_2.INIT = 16'h0001; + LUT4 com_llm_llm_tx_top_llmx08_tx_dllp_jefe_llm32_fc_fifo_un1_wr_en_5_i_0_0_0_a2_2 ( + .I0(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_llm32_fc_fifo_data_count[0]), + .I1(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_llm32_fc_fifo_data_count[1]), + .I2(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_llm32_fc_fifo_data_count[2]), + .I3(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_llm32_fc_fifo_data_count[3]), + .O(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_llm32_fc_fifo_N_42408_2) + ); + defparam com_llm_llm_tx_top_llmx08_tx_dllp_jefe_llm32_fc_fifo_un1_wr_en_7_0_0_0_m2_0_0_.INIT = 16'hE2F3; + LUT4_L com_llm_llm_tx_top_llmx08_tx_dllp_jefe_llm32_fc_fifo_un1_wr_en_7_0_0_0_m2_0_0_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_llm32_fc_fifo_N_42408_2), + .I1(com_un1_lnk_tfc_dst_rdy_i_0_o2_i_a2), + .I2(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_fc_queue_empty), + .I3(plm_link_up_1), + .LO(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_llm32_fc_fifo_N_42051) + ); + defparam com_llm_llm_tx_top_llmx08_tx_dllp_jefe_llm32_fc_fifo_data_count23_i_0_0_0.INIT = 16'h0100; + LUT4 com_llm_llm_tx_top_llmx08_tx_dllp_jefe_llm32_fc_fifo_data_count23_i_0_0_0 ( + .I0(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_N_41762_i), + .I1(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_llm32_fc_fifo_N_42408_2), + .I2(com_un1_lnk_tfc_dst_rdy_i_0_o2_i_a2), + .I3(plm_link_up_1), + .O(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_llm32_fc_fifo_N_12584_i) + ); + defparam com_llm_llm_tx_top_llmx08_tx_dllp_jefe_llm32_fc_fifo_un1_data_count_3_axb_0.INIT = 16'hDE21; + LUT4 com_llm_llm_tx_top_llmx08_tx_dllp_jefe_llm32_fc_fifo_un1_data_count_3_axb_0 ( + .I0(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_N_41762_i), + .I1(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_llm32_fc_fifo_N_42051), + .I2(com_un1_lnk_tfc_dst_rdy_i_0_o2_i_a2), + .I3(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_llm32_fc_fifo_data_count[0]), + .O(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_llm32_fc_fifo_un1_data_count_3_axb_0_1404) + ); + defparam com_llm_llm_tx_top_llmx08_tx_dllp_jefe_llm32_fc_fifo_N_68899_i.INIT = 16'hF404; + LUT4 com_llm_llm_tx_top_llmx08_tx_dllp_jefe_llm32_fc_fifo_N_68899_i ( + .I0(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_N_41762_i), + .I1(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_llm32_fc_fifo_N_42408_2), + .I2(com_un1_lnk_tfc_dst_rdy_i_0_o2_i_a2), + .I3(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_fc_queue_empty), + .O(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_llm32_fc_fifo_N_68899_i_1405) + ); + defparam com_llm_llm_tx_top_llmx08_tx_dllp_jefe_llm32_fc_fifo_un1_data_count_3_axb_3.INIT = 4'h6; + LUT2_L com_llm_llm_tx_top_llmx08_tx_dllp_jefe_llm32_fc_fifo_un1_data_count_3_axb_3 ( + .I0(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_llm32_fc_fifo_N_12584_i), + .I1(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_llm32_fc_fifo_data_count[3]), + .LO(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_llm32_fc_fifo_un1_data_count_3_axb_3_1406) + ); + defparam com_llm_llm_tx_top_llmx08_tx_dllp_jefe_llm32_fc_fifo_un1_data_count_3_axb_2.INIT = 4'h6; + LUT2_L com_llm_llm_tx_top_llmx08_tx_dllp_jefe_llm32_fc_fifo_un1_data_count_3_axb_2 ( + .I0(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_llm32_fc_fifo_N_12584_i), + .I1(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_llm32_fc_fifo_data_count[2]), + .LO(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_llm32_fc_fifo_un1_data_count_3_axb_2_1407) + ); + defparam com_llm_llm_tx_top_llmx08_tx_dllp_jefe_llm32_fc_fifo_un1_data_count_3_axb_1.INIT = 4'h6; + LUT2_L com_llm_llm_tx_top_llmx08_tx_dllp_jefe_llm32_fc_fifo_un1_data_count_3_axb_1 ( + .I0(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_llm32_fc_fifo_N_12584_i), + .I1(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_llm32_fc_fifo_data_count[1]), + .LO(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_llm32_fc_fifo_un1_data_count_3_axb_1_1408) + ); + defparam com_llm_llm_tx_top_llmx08_tx_dllp_jefe_llm32_fc_fifo_tx_fc_queue_empty_i.INIT = 4'h1; + LUT1_L com_llm_llm_tx_top_llmx08_tx_dllp_jefe_llm32_fc_fifo_tx_fc_queue_empty_i ( + .I0(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_fc_queue_empty), + .LO(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_fc_queue_empty_i) + ); + defparam com_llm_llm_tx_top_llmx08_tx_dllp_jefe_llm32_fc_fifo_un1_rd_en_4_0_0_0_1.INIT = 8'h40; + LUT3 com_llm_llm_tx_top_llmx08_tx_dllp_jefe_llm32_fc_fifo_un1_rd_en_4_0_0_0_1 ( + .I0(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_llm32_fc_fifo_data_count[0]), + .I1(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_llm32_fc_fifo_data_count[1]), + .I2(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_llm32_fc_fifo_data_count[3]), + .O(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_llm32_fc_fifo_un1_rd_en_4_0_0_0_1_1409) + ); + defparam com_llm_llm_tx_top_llmx08_tx_dllp_jefe_llm32_fc_fifo_un1_rd_en_4_0_0_0.INIT = 16'h9111; + LUT4 com_llm_llm_tx_top_llmx08_tx_dllp_jefe_llm32_fc_fifo_un1_rd_en_4_0_0_0 ( + .I0(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_N_41762_i), + .I1(com_un1_lnk_tfc_dst_rdy_i_0_o2_i_a2), + .I2(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_llm32_fc_fifo_un1_rd_en_4_0_0_0_1_1409), + .I3(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_llm32_fc_fifo_data_count[2]), + .O(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_llm32_fc_fifo_un1_rd_en_4_i) + ); + SRL16E com_llm_llm_tx_top_llmx08_tx_dllp_jefe_llm32_fc_fifo_llm32_fifo16_srl_regBank_I_1 ( + .CE(com_un1_lnk_tfc_dst_rdy_i_0_o2_i_a2), + .D(com_lnk_tfc_type[2]), + .Q(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_fc_dout_30_), + .CLK(NlwRenamedSig_OI_trn_clk), + .A0(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_llm32_fc_fifo_data_count[0]), + .A1(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_llm32_fc_fifo_data_count[1]), + .A2(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_llm32_fc_fifo_data_count[2]), + .A3(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_llm32_fc_fifo_data_count[3]) + ); + SRL16E com_llm_llm_tx_top_llmx08_tx_dllp_jefe_llm32_fc_fifo_llm32_fifo16_srl_regBank_I_2 ( + .CE(com_un1_lnk_tfc_dst_rdy_i_0_o2_i_a2), + .D(com_lnk_tfc_type[1]), + .Q(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_fc_dout_29_), + .CLK(NlwRenamedSig_OI_trn_clk), + .A0(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_llm32_fc_fifo_data_count[0]), + .A1(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_llm32_fc_fifo_data_count[1]), + .A2(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_llm32_fc_fifo_data_count[2]), + .A3(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_llm32_fc_fifo_data_count[3]) + ); + SRL16E com_llm_llm_tx_top_llmx08_tx_dllp_jefe_llm32_fc_fifo_llm32_fifo16_srl_regBank_I_3 ( + .CE(com_un1_lnk_tfc_dst_rdy_i_0_o2_i_a2), + .D(com_lnk_tfc_header[5]), + .Q(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_fc_dout_19_), + .CLK(NlwRenamedSig_OI_trn_clk), + .A0(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_llm32_fc_fifo_data_count[0]), + .A1(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_llm32_fc_fifo_data_count[1]), + .A2(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_llm32_fc_fifo_data_count[2]), + .A3(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_llm32_fc_fifo_data_count[3]) + ); + SRL16E com_llm_llm_tx_top_llmx08_tx_dllp_jefe_llm32_fc_fifo_llm32_fifo16_srl_regBank_I_4 ( + .CE(com_un1_lnk_tfc_dst_rdy_i_0_o2_i_a2), + .D(com_lnk_tfc_data[8]), + .Q(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_fc_dout_8_), + .CLK(NlwRenamedSig_OI_trn_clk), + .A0(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_llm32_fc_fifo_data_count[0]), + .A1(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_llm32_fc_fifo_data_count[1]), + .A2(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_llm32_fc_fifo_data_count[2]), + .A3(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_llm32_fc_fifo_data_count[3]) + ); + SRL16E com_llm_llm_tx_top_llmx08_tx_dllp_jefe_llm32_fc_fifo_llm32_fifo16_srl_regBank_I_5 ( + .CE(com_un1_lnk_tfc_dst_rdy_i_0_o2_i_a2), + .D(com_lnk_tfc_data[2]), + .Q(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_fc_dout_2_), + .CLK(NlwRenamedSig_OI_trn_clk), + .A0(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_llm32_fc_fifo_data_count[0]), + .A1(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_llm32_fc_fifo_data_count[1]), + .A2(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_llm32_fc_fifo_data_count[2]), + .A3(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_llm32_fc_fifo_data_count[3]) + ); + SRL16E com_llm_llm_tx_top_llmx08_tx_dllp_jefe_llm32_fc_fifo_llm32_fifo16_srl_regBank_I_6 ( + .CE(com_un1_lnk_tfc_dst_rdy_i_0_o2_i_a2), + .D(com_lnk_tfc_data[9]), + .Q(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_fc_dout_9_), + .CLK(NlwRenamedSig_OI_trn_clk), + .A0(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_llm32_fc_fifo_data_count[0]), + .A1(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_llm32_fc_fifo_data_count[1]), + .A2(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_llm32_fc_fifo_data_count[2]), + .A3(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_llm32_fc_fifo_data_count[3]) + ); + SRL16E com_llm_llm_tx_top_llmx08_tx_dllp_jefe_llm32_fc_fifo_llm32_fifo16_srl_regBank_I_7 ( + .CE(com_un1_lnk_tfc_dst_rdy_i_0_o2_i_a2), + .D(com_lnk_tfc_data[6]), + .Q(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_fc_dout_6_), + .CLK(NlwRenamedSig_OI_trn_clk), + .A0(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_llm32_fc_fifo_data_count[0]), + .A1(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_llm32_fc_fifo_data_count[1]), + .A2(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_llm32_fc_fifo_data_count[2]), + .A3(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_llm32_fc_fifo_data_count[3]) + ); + SRL16E com_llm_llm_tx_top_llmx08_tx_dllp_jefe_llm32_fc_fifo_llm32_fifo16_srl_regBank_I_8 ( + .CE(com_un1_lnk_tfc_dst_rdy_i_0_o2_i_a2), + .D(com_lnk_tfc_data[10]), + .Q(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_fc_dout_10_), + .CLK(NlwRenamedSig_OI_trn_clk), + .A0(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_llm32_fc_fifo_data_count[0]), + .A1(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_llm32_fc_fifo_data_count[1]), + .A2(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_llm32_fc_fifo_data_count[2]), + .A3(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_llm32_fc_fifo_data_count[3]) + ); + SRL16E com_llm_llm_tx_top_llmx08_tx_dllp_jefe_llm32_fc_fifo_llm32_fifo16_srl_regBank_I_9 ( + .CE(com_un1_lnk_tfc_dst_rdy_i_0_o2_i_a2), + .D(com_lnk_tfc_data[4]), + .Q(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_fc_dout_4_), + .CLK(NlwRenamedSig_OI_trn_clk), + .A0(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_llm32_fc_fifo_data_count[0]), + .A1(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_llm32_fc_fifo_data_count[1]), + .A2(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_llm32_fc_fifo_data_count[2]), + .A3(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_llm32_fc_fifo_data_count[3]) + ); + SRL16E com_llm_llm_tx_top_llmx08_tx_dllp_jefe_llm32_fc_fifo_llm32_fifo16_srl_regBank_I_10 ( + .CE(com_un1_lnk_tfc_dst_rdy_i_0_o2_i_a2), + .D(com_lnk_tfc_data[11]), + .Q(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_fc_dout_11_), + .CLK(NlwRenamedSig_OI_trn_clk), + .A0(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_llm32_fc_fifo_data_count[0]), + .A1(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_llm32_fc_fifo_data_count[1]), + .A2(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_llm32_fc_fifo_data_count[2]), + .A3(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_llm32_fc_fifo_data_count[3]) + ); + SRL16E com_llm_llm_tx_top_llmx08_tx_dllp_jefe_llm32_fc_fifo_llm32_fifo16_srl_regBank_I_11 ( + .CE(com_un1_lnk_tfc_dst_rdy_i_0_o2_i_a2), + .D(com_lnk_tfc_data[5]), + .Q(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_fc_dout_5_), + .CLK(NlwRenamedSig_OI_trn_clk), + .A0(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_llm32_fc_fifo_data_count[0]), + .A1(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_llm32_fc_fifo_data_count[1]), + .A2(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_llm32_fc_fifo_data_count[2]), + .A3(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_llm32_fc_fifo_data_count[3]) + ); + SRL16E com_llm_llm_tx_top_llmx08_tx_dllp_jefe_llm32_fc_fifo_llm32_fifo16_srl_regBank_I_13 ( + .CE(com_un1_lnk_tfc_dst_rdy_i_0_o2_i_a2), + .D(com_lnk_tfc_type[3]), + .Q(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_fc_dout_31_), + .CLK(NlwRenamedSig_OI_trn_clk), + .A0(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_llm32_fc_fifo_data_count[0]), + .A1(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_llm32_fc_fifo_data_count[1]), + .A2(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_llm32_fc_fifo_data_count[2]), + .A3(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_llm32_fc_fifo_data_count[3]) + ); + SRL16E com_llm_llm_tx_top_llmx08_tx_dllp_jefe_llm32_fc_fifo_llm32_fifo16_srl_regBank_I_15 ( + .CE(com_un1_lnk_tfc_dst_rdy_i_0_o2_i_a2), + .D(com_lnk_tfc_header[6]), + .Q(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_fc_dout_20_), + .CLK(NlwRenamedSig_OI_trn_clk), + .A0(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_llm32_fc_fifo_data_count[0]), + .A1(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_llm32_fc_fifo_data_count[1]), + .A2(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_llm32_fc_fifo_data_count[2]), + .A3(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_llm32_fc_fifo_data_count[3]) + ); + SRL16E com_llm_llm_tx_top_llmx08_tx_dllp_jefe_llm32_fc_fifo_llm32_fifo16_srl_regBank_I_16 ( + .CE(com_un1_lnk_tfc_dst_rdy_i_0_o2_i_a2), + .D(com_lnk_tfc_header[0]), + .Q(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_fc_dout_14_), + .CLK(NlwRenamedSig_OI_trn_clk), + .A0(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_llm32_fc_fifo_data_count[0]), + .A1(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_llm32_fc_fifo_data_count[1]), + .A2(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_llm32_fc_fifo_data_count[2]), + .A3(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_llm32_fc_fifo_data_count[3]) + ); + SRL16E com_llm_llm_tx_top_llmx08_tx_dllp_jefe_llm32_fc_fifo_llm32_fifo16_srl_regBank_I_17 ( + .CE(com_un1_lnk_tfc_dst_rdy_i_0_o2_i_a2), + .D(com_lnk_tfc_header[7]), + .Q(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_fc_dout_21_), + .CLK(NlwRenamedSig_OI_trn_clk), + .A0(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_llm32_fc_fifo_data_count[0]), + .A1(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_llm32_fc_fifo_data_count[1]), + .A2(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_llm32_fc_fifo_data_count[2]), + .A3(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_llm32_fc_fifo_data_count[3]) + ); + SRL16E com_llm_llm_tx_top_llmx08_tx_dllp_jefe_llm32_fc_fifo_llm32_fifo16_srl_regBank_I_18 ( + .CE(com_un1_lnk_tfc_dst_rdy_i_0_o2_i_a2), + .D(com_lnk_tfc_header[1]), + .Q(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_fc_dout_15_), + .CLK(NlwRenamedSig_OI_trn_clk), + .A0(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_llm32_fc_fifo_data_count[0]), + .A1(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_llm32_fc_fifo_data_count[1]), + .A2(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_llm32_fc_fifo_data_count[2]), + .A3(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_llm32_fc_fifo_data_count[3]) + ); + SRL16E com_llm_llm_tx_top_llmx08_tx_dllp_jefe_llm32_fc_fifo_llm32_fifo16_srl_regBank_I_20 ( + .CE(com_un1_lnk_tfc_dst_rdy_i_0_o2_i_a2), + .D(com_lnk_tfc_data[0]), + .Q(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_fc_dout_0_), + .CLK(NlwRenamedSig_OI_trn_clk), + .A0(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_llm32_fc_fifo_data_count[0]), + .A1(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_llm32_fc_fifo_data_count[1]), + .A2(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_llm32_fc_fifo_data_count[2]), + .A3(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_llm32_fc_fifo_data_count[3]) + ); + SRL16E com_llm_llm_tx_top_llmx08_tx_dllp_jefe_llm32_fc_fifo_llm32_fifo16_srl_regBank_I_22 ( + .CE(com_un1_lnk_tfc_dst_rdy_i_0_o2_i_a2), + .D(com_lnk_tfc_header[3]), + .Q(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_fc_dout_17_), + .CLK(NlwRenamedSig_OI_trn_clk), + .A0(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_llm32_fc_fifo_data_count[0]), + .A1(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_llm32_fc_fifo_data_count[1]), + .A2(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_llm32_fc_fifo_data_count[2]), + .A3(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_llm32_fc_fifo_data_count[3]) + ); + SRL16E com_llm_llm_tx_top_llmx08_tx_dllp_jefe_llm32_fc_fifo_llm32_fifo16_srl_regBank_I_24 ( + .CE(com_un1_lnk_tfc_dst_rdy_i_0_o2_i_a2), + .D(com_lnk_tfc_header[4]), + .Q(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_fc_dout_18_), + .CLK(NlwRenamedSig_OI_trn_clk), + .A0(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_llm32_fc_fifo_data_count[0]), + .A1(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_llm32_fc_fifo_data_count[1]), + .A2(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_llm32_fc_fifo_data_count[2]), + .A3(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_llm32_fc_fifo_data_count[3]) + ); + SRL16E com_llm_llm_tx_top_llmx08_tx_dllp_jefe_llm32_fc_fifo_llm32_fifo16_srl_regBank_I_26 ( + .CE(com_un1_lnk_tfc_dst_rdy_i_0_o2_i_a2), + .D(com_lnk_tfc_header[2]), + .Q(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_fc_dout_16_), + .CLK(NlwRenamedSig_OI_trn_clk), + .A0(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_llm32_fc_fifo_data_count[0]), + .A1(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_llm32_fc_fifo_data_count[1]), + .A2(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_llm32_fc_fifo_data_count[2]), + .A3(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_llm32_fc_fifo_data_count[3]) + ); + SRL16E com_llm_llm_tx_top_llmx08_tx_dllp_jefe_llm32_fc_fifo_llm32_fifo16_srl_regBank_I_29 ( + .CE(com_un1_lnk_tfc_dst_rdy_i_0_o2_i_a2), + .D(com_lnk_tfc_type[0]), + .Q(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_fc_dout_28_), + .CLK(NlwRenamedSig_OI_trn_clk), + .A0(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_llm32_fc_fifo_data_count[0]), + .A1(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_llm32_fc_fifo_data_count[1]), + .A2(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_llm32_fc_fifo_data_count[2]), + .A3(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_llm32_fc_fifo_data_count[3]) + ); + SRL16E com_llm_llm_tx_top_llmx08_tx_dllp_jefe_llm32_fc_fifo_llm32_fifo16_srl_regBank_I_30 ( + .CE(com_un1_lnk_tfc_dst_rdy_i_0_o2_i_a2), + .D(com_lnk_tfc_data[3]), + .Q(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_fc_dout_3_), + .CLK(NlwRenamedSig_OI_trn_clk), + .A0(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_llm32_fc_fifo_data_count[0]), + .A1(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_llm32_fc_fifo_data_count[1]), + .A2(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_llm32_fc_fifo_data_count[2]), + .A3(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_llm32_fc_fifo_data_count[3]) + ); + SRL16E com_llm_llm_tx_top_llmx08_tx_dllp_jefe_llm32_fc_fifo_llm32_fifo16_srl_regBank_I_31 ( + .CE(com_un1_lnk_tfc_dst_rdy_i_0_o2_i_a2), + .D(com_lnk_tfc_data[1]), + .Q(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_fc_dout_1_), + .CLK(NlwRenamedSig_OI_trn_clk), + .A0(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_llm32_fc_fifo_data_count[0]), + .A1(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_llm32_fc_fifo_data_count[1]), + .A2(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_llm32_fc_fifo_data_count[2]), + .A3(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_llm32_fc_fifo_data_count[3]) + ); + SRL16E com_llm_llm_tx_top_llmx08_tx_dllp_jefe_llm32_fc_fifo_llm32_fifo16_srl_regBank_I_32 ( + .CE(com_un1_lnk_tfc_dst_rdy_i_0_o2_i_a2), + .D(com_lnk_tfc_data[7]), + .Q(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_fc_dout_7_), + .CLK(NlwRenamedSig_OI_trn_clk), + .A0(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_llm32_fc_fifo_data_count[0]), + .A1(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_llm32_fc_fifo_data_count[1]), + .A2(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_llm32_fc_fifo_data_count[2]), + .A3(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_llm32_fc_fifo_data_count[3]) + ); + FDS com_llm_llm_tx_top_llmx08_tx_packet_packer_arb_state_0_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_68078_i_1489), + .Q(com_llm_llm_tx_top_reg_tx_pp_idle), + .S(plm_link_up_i) + ); + FDR com_llm_llm_tx_top_llmx08_tx_packet_packer_arb_state_1_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_17349_i), + .Q(com_llm_llm_tx_top_tx_dllp_accepted), + .R(plm_link_up_i) + ); + FDR com_llm_llm_tx_top_llmx08_tx_packet_packer_arb_state_2_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_17347_i), + .Q(com_llm_llm_tx_top_arb_state[2]), + .R(plm_link_up_i) + ); + FDS com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_0_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_40392_i), + .Q(phy_td[0]), + .S(plm_link_up_i) + ); + FDS com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_1_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_40394_i), + .Q(phy_td[1]), + .S(plm_link_up_i) + ); + FDS com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_2_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_40396_i), + .Q(phy_td[2]), + .S(plm_link_up_i) + ); + FDS com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_3_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_40398_i), + .Q(phy_td[3]), + .S(plm_link_up_i) + ); + FDS com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_40400_i), + .Q(phy_td[4]), + .S(plm_link_up_i) + ); + FDS com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_5_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_40402_i), + .Q(phy_td[5]), + .S(plm_link_up_i) + ); + FDS com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_6_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_40404_i), + .Q(phy_td[6]), + .S(plm_link_up_i) + ); + FDS com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_7_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_40406_i), + .Q(phy_td[7]), + .S(plm_link_up_i) + ); + FDR com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_8_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_40408_i), + .Q(phy_td[8]), + .R(plm_link_up_i) + ); + FDR com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_9_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_40410_i), + .Q(phy_td[9]), + .R(plm_link_up_i) + ); + FDR com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_10_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_40412_i), + .Q(phy_td[10]), + .R(plm_link_up_i) + ); + FDR com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_11_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_40414_i), + .Q(phy_td[11]), + .R(plm_link_up_i) + ); + FDR com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_12_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_40416_i), + .Q(phy_td[12]), + .R(plm_link_up_i) + ); + FDR com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_13_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_40418_i), + .Q(phy_td[13]), + .R(plm_link_up_i) + ); + FDR com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_14_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_40420_i), + .Q(phy_td[14]), + .R(plm_link_up_i) + ); + FDR com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_15_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_40422_i), + .Q(phy_td[15]), + .R(plm_link_up_i) + ); + FDR com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_16_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_40424_i), + .Q(phy_td[16]), + .R(plm_link_up_i) + ); + FDR com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_17_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_40426_i), + .Q(phy_td[17]), + .R(plm_link_up_i) + ); + FDR com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_18_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_40428_i), + .Q(phy_td[18]), + .R(plm_link_up_i) + ); + FDR com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_19_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_40430_i), + .Q(phy_td[19]), + .R(plm_link_up_i) + ); + FDR com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_20_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_40432_i), + .Q(phy_td[20]), + .R(plm_link_up_i) + ); + FDR com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_21_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_40434_i), + .Q(phy_td[21]), + .R(plm_link_up_i) + ); + FDR com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_22_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_40436_i), + .Q(phy_td[22]), + .R(plm_link_up_i) + ); + FDR com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_23_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_40438_i), + .Q(phy_td[23]), + .R(plm_link_up_i) + ); + FDR com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_24_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_67969_i_1471), + .Q(phy_td[24]), + .R(plm_link_up_i) + ); + FDR com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_25_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_67970_i_1470), + .Q(phy_td[25]), + .R(plm_link_up_i) + ); + FDR com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_26_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_67971_i_1469), + .Q(phy_td[26]), + .R(plm_link_up_i) + ); + FDR com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_27_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_67972_i_1468), + .Q(phy_td[27]), + .R(plm_link_up_i) + ); + FDR com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_28_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_67973_i_1467), + .Q(phy_td[28]), + .R(plm_link_up_i) + ); + FDR com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_29_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_67974_i_1466), + .Q(phy_td[29]), + .R(plm_link_up_i) + ); + FDR com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_30_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_67975_i_1465), + .Q(phy_td[30]), + .R(plm_link_up_i) + ); + FDR com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_31_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_67976_i_1464), + .Q(phy_td[31]), + .R(plm_link_up_i) + ); + FDR com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_32_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_67977_i_1462), + .Q(phy_td[32]), + .R(plm_link_up_i) + ); + FDR com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_33_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_67952_i_1460), + .Q(phy_td[33]), + .R(plm_link_up_i) + ); + FDR com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_34_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_67978_i_1458), + .Q(phy_td[34]), + .R(plm_link_up_i) + ); + FDR com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_35_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_67979_i_1456), + .Q(phy_td[35]), + .R(plm_link_up_i) + ); + FDR com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_36_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_68241_i_1455), + .Q(phy_td[36]), + .R(plm_link_up_i) + ); + FDR com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_37_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_68240_i_1454), + .Q(phy_td[37]), + .R(plm_link_up_i) + ); + FDR com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_38_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_67980_i_1452), + .Q(phy_td[38]), + .R(plm_link_up_i) + ); + FDR com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_39_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_67981_i_1450), + .Q(phy_td[39]), + .R(plm_link_up_i) + ); + FDR com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_40_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_67982_i_1448), + .Q(phy_td[40]), + .R(plm_link_up_i) + ); + FDR com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_41_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_67983_i_1446), + .Q(phy_td[41]), + .R(plm_link_up_i) + ); + FDR com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_42_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_67984_i_1444), + .Q(phy_td[42]), + .R(plm_link_up_i) + ); + FDR com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_43_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_67985_i_1442), + .Q(phy_td[43]), + .R(plm_link_up_i) + ); + FDR com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_44_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_67986_i_1440), + .Q(phy_td[44]), + .R(plm_link_up_i) + ); + FDR com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_45_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_67987_i_1438), + .Q(phy_td[45]), + .R(plm_link_up_i) + ); + FDR com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_46_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_68239_i_1437), + .Q(phy_td[46]), + .R(plm_link_up_i) + ); + FDR com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_47_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_68238_i_1436), + .Q(phy_td[47]), + .R(plm_link_up_i) + ); + FDR com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_48_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_67988_i_1434), + .Q(phy_td[48]), + .R(plm_link_up_i) + ); + FDR com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_49_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_67989_i_1432), + .Q(phy_td[49]), + .R(plm_link_up_i) + ); + FDR com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_50_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_68237_i_1431), + .Q(phy_td[50]), + .R(plm_link_up_i) + ); + FDR com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_51_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_68236_i_1430), + .Q(phy_td[51]), + .R(plm_link_up_i) + ); + FDR com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_52_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_67990_i_1428), + .Q(phy_td[52]), + .R(plm_link_up_i) + ); + FDR com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_53_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_67951_i_1426), + .Q(phy_td[53]), + .R(plm_link_up_i) + ); + FDR com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_54_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_67991_i_1424), + .Q(phy_td[54]), + .R(plm_link_up_i) + ); + FDR com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_55_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_67992_i_1422), + .Q(phy_td[55]), + .R(plm_link_up_i) + ); + FDS com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_56_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_40472_i), + .Q(phy_td[56]), + .S(plm_link_up_i) + ); + FDS com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_57_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_40474_i), + .Q(phy_td[57]), + .S(plm_link_up_i) + ); + FDS com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_58_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_40476_i), + .Q(phy_td[58]), + .S(plm_link_up_i) + ); + FDS com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_59_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_40478_i), + .Q(phy_td[59]), + .S(plm_link_up_i) + ); + FDS com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_60_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_40480_i), + .Q(phy_td[60]), + .S(plm_link_up_i) + ); + FDS com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_61_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_40482_i), + .Q(phy_td[61]), + .S(plm_link_up_i) + ); + FDS com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_62_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_40484_i), + .Q(phy_td[62]), + .S(plm_link_up_i) + ); + FDS com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_63_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_40486_i), + .Q(phy_td[63]), + .S(plm_link_up_i) + ); + FDR com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_tframe_l ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_40390_i), + .Q(phy_tframe_l), + .R(plm_link_up_i) + ); + FDR com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_tframe_h ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_40388_i), + .Q(phy_tframe_h), + .R(plm_link_up_i) + ); + FDS com_llm_llm_tx_top_llmx08_tx_packet_packer_prev_td_0_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_68937_i_1421), + .Q(com_llm_llm_tx_top_llmx08_tx_packet_packer_prev_td[0]), + .S(plm_link_up_i) + ); + FDS com_llm_llm_tx_top_llmx08_tx_packet_packer_prev_td_1_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_68936_i_1420), + .Q(com_llm_llm_tx_top_llmx08_tx_packet_packer_prev_td[1]), + .S(plm_link_up_i) + ); + FDS com_llm_llm_tx_top_llmx08_tx_packet_packer_prev_td_2_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_68935_i_1419), + .Q(com_llm_llm_tx_top_llmx08_tx_packet_packer_prev_td[2]), + .S(plm_link_up_i) + ); + FDS com_llm_llm_tx_top_llmx08_tx_packet_packer_prev_td_3_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_68934_i_1418), + .Q(com_llm_llm_tx_top_llmx08_tx_packet_packer_prev_td[3]), + .S(plm_link_up_i) + ); + FDS com_llm_llm_tx_top_llmx08_tx_packet_packer_prev_td_4_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_68933_i_1417), + .Q(com_llm_llm_tx_top_llmx08_tx_packet_packer_prev_td[4]), + .S(plm_link_up_i) + ); + FDS com_llm_llm_tx_top_llmx08_tx_packet_packer_prev_td_5_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_68932_i_1416), + .Q(com_llm_llm_tx_top_llmx08_tx_packet_packer_prev_td[5]), + .S(plm_link_up_i) + ); + FDS com_llm_llm_tx_top_llmx08_tx_packet_packer_prev_td_6_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_68931_i_1415), + .Q(com_llm_llm_tx_top_llmx08_tx_packet_packer_prev_td[6]), + .S(plm_link_up_i) + ); + FDS com_llm_llm_tx_top_llmx08_tx_packet_packer_prev_td_7_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_68930_i_1414), + .Q(com_llm_llm_tx_top_llmx08_tx_packet_packer_prev_td[7]), + .S(plm_link_up_i) + ); + FDR com_llm_llm_tx_top_llmx08_tx_packet_packer_prev_td_8_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_packet_packer_current_td[8]), + .Q(com_llm_llm_tx_top_llmx08_tx_packet_packer_prev_td[8]), + .R(plm_link_up_i) + ); + FDR com_llm_llm_tx_top_llmx08_tx_packet_packer_prev_td_9_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_packet_packer_current_td[9]), + .Q(com_llm_llm_tx_top_llmx08_tx_packet_packer_prev_td[9]), + .R(plm_link_up_i) + ); + FDR com_llm_llm_tx_top_llmx08_tx_packet_packer_prev_td_10_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_packet_packer_current_td[10]), + .Q(com_llm_llm_tx_top_llmx08_tx_packet_packer_prev_td[10]), + .R(plm_link_up_i) + ); + FDR com_llm_llm_tx_top_llmx08_tx_packet_packer_prev_td_11_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_packet_packer_current_td[11]), + .Q(com_llm_llm_tx_top_llmx08_tx_packet_packer_prev_td[11]), + .R(plm_link_up_i) + ); + FDR com_llm_llm_tx_top_llmx08_tx_packet_packer_prev_td_12_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_packet_packer_current_td[12]), + .Q(com_llm_llm_tx_top_llmx08_tx_packet_packer_prev_td[12]), + .R(plm_link_up_i) + ); + FDR com_llm_llm_tx_top_llmx08_tx_packet_packer_prev_td_13_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_packet_packer_current_td[13]), + .Q(com_llm_llm_tx_top_llmx08_tx_packet_packer_prev_td[13]), + .R(plm_link_up_i) + ); + FDR com_llm_llm_tx_top_llmx08_tx_packet_packer_prev_td_14_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_packet_packer_current_td[14]), + .Q(com_llm_llm_tx_top_llmx08_tx_packet_packer_prev_td[14]), + .R(plm_link_up_i) + ); + FDR com_llm_llm_tx_top_llmx08_tx_packet_packer_prev_td_15_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_packet_packer_current_td[15]), + .Q(com_llm_llm_tx_top_llmx08_tx_packet_packer_prev_td[15]), + .R(plm_link_up_i) + ); + FDR com_llm_llm_tx_top_llmx08_tx_packet_packer_prev_td_16_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_packet_packer_current_td[16]), + .Q(com_llm_llm_tx_top_llmx08_tx_packet_packer_prev_td[16]), + .R(plm_link_up_i) + ); + FDR com_llm_llm_tx_top_llmx08_tx_packet_packer_prev_td_17_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_packet_packer_current_td[17]), + .Q(com_llm_llm_tx_top_llmx08_tx_packet_packer_prev_td[17]), + .R(plm_link_up_i) + ); + FDR com_llm_llm_tx_top_llmx08_tx_packet_packer_prev_td_18_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_packet_packer_current_td[18]), + .Q(com_llm_llm_tx_top_llmx08_tx_packet_packer_prev_td[18]), + .R(plm_link_up_i) + ); + FDR com_llm_llm_tx_top_llmx08_tx_packet_packer_prev_td_19_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_packet_packer_current_td[19]), + .Q(com_llm_llm_tx_top_llmx08_tx_packet_packer_prev_td[19]), + .R(plm_link_up_i) + ); + FDR com_llm_llm_tx_top_llmx08_tx_packet_packer_prev_td_20_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_packet_packer_current_td[20]), + .Q(com_llm_llm_tx_top_llmx08_tx_packet_packer_prev_td[20]), + .R(plm_link_up_i) + ); + FDR com_llm_llm_tx_top_llmx08_tx_packet_packer_prev_td_21_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_packet_packer_current_td[21]), + .Q(com_llm_llm_tx_top_llmx08_tx_packet_packer_prev_td[21]), + .R(plm_link_up_i) + ); + FDR com_llm_llm_tx_top_llmx08_tx_packet_packer_prev_td_22_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_packet_packer_current_td[22]), + .Q(com_llm_llm_tx_top_llmx08_tx_packet_packer_prev_td[22]), + .R(plm_link_up_i) + ); + FDR com_llm_llm_tx_top_llmx08_tx_packet_packer_prev_td_23_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_packet_packer_current_td[23]), + .Q(com_llm_llm_tx_top_llmx08_tx_packet_packer_prev_td[23]), + .R(plm_link_up_i) + ); + FDR com_llm_llm_tx_top_llmx08_tx_packet_packer_prev_td_24_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_40531_i), + .Q(com_llm_llm_tx_top_llmx08_tx_packet_packer_prev_td[24]), + .R(plm_link_up_i) + ); + FDR com_llm_llm_tx_top_llmx08_tx_packet_packer_prev_td_25_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_40533_i), + .Q(com_llm_llm_tx_top_llmx08_tx_packet_packer_prev_td[25]), + .R(plm_link_up_i) + ); + FDR com_llm_llm_tx_top_llmx08_tx_packet_packer_prev_td_26_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_40535_i), + .Q(com_llm_llm_tx_top_llmx08_tx_packet_packer_prev_td[26]), + .R(plm_link_up_i) + ); + FDR com_llm_llm_tx_top_llmx08_tx_packet_packer_prev_td_27_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_40537_i), + .Q(com_llm_llm_tx_top_llmx08_tx_packet_packer_prev_td[27]), + .R(plm_link_up_i) + ); + FDR com_llm_llm_tx_top_llmx08_tx_packet_packer_prev_td_28_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_40539_i), + .Q(com_llm_llm_tx_top_llmx08_tx_packet_packer_prev_td[28]), + .R(plm_link_up_i) + ); + FDR com_llm_llm_tx_top_llmx08_tx_packet_packer_prev_td_29_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_40541_i), + .Q(com_llm_llm_tx_top_llmx08_tx_packet_packer_prev_td[29]), + .R(plm_link_up_i) + ); + FDR com_llm_llm_tx_top_llmx08_tx_packet_packer_prev_td_30_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_40543_i), + .Q(com_llm_llm_tx_top_llmx08_tx_packet_packer_prev_td[30]), + .R(plm_link_up_i) + ); + FDR com_llm_llm_tx_top_llmx08_tx_packet_packer_prev_td_31_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_40545_i), + .Q(com_llm_llm_tx_top_llmx08_tx_packet_packer_prev_td[31]), + .R(plm_link_up_i) + ); + FDS com_llm_llm_tx_top_llmx08_tx_packet_packer_aligned ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_68888_i_1412), + .Q(com_llm_llm_tx_top_llmx08_tx_packet_packer_aligned_1490), + .S(plm_link_up_i) + ); + FDS com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_tctrl_h ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_41842_i_1411), + .Q(phy_tctrl_h), + .S(plm_link_up_i) + ); + FDRSE com_llm_llm_tx_top_llmx08_tx_packet_packer_tx_idle_next ( + .CE(com_llm_llm_tx_top_llmx08_tx_packet_packer_next_arb_state_0_sqmuxa), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmml_suspend_now_n_i), + .Q(com_llm_llm_tx_top_llmx08_tx_packet_packer_tx_idle_next_1486), + .R(plm_link_up_i), + .S(phy_tstall_n_i) + ); + FDR com_llm_llm_tx_top_llmx08_tx_packet_packer_trans_non_aligned ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_41820_i), + .Q(com_llm_llm_tx_top_llmx08_tx_packet_packer_trans_non_aligned_1413), + .R(plm_link_up_i) + ); + FDS com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_tctrl_l ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_packet_packer_arb_state_i[2]), + .Q(phy_tctrl_l), + .S(plm_link_up_i) + ); + defparam com_llm_llm_tx_top_llmx08_tx_packet_packer_next_arb_state_i_i_0_o4_0_1_.INIT = 4'h2; + LUT2 com_llm_llm_tx_top_llmx08_tx_packet_packer_next_arb_state_i_i_0_o4_0_1_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_packet_packer_aligned_1490), + .I1(com_llm_llm_tx_top_rem_pipe[4]), + .O(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_41820_i) + ); + defparam com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_tframe_h_3_i_o4.INIT = 4'h8; + LUT2 com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_tframe_h_3_i_o4 ( + .I0(com_llm_llm_tx_top_arb_state[2]), + .I1(com_llm_llm_tx_top_tx_tlp_sof_n), + .O(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_41774_i) + ); + defparam com_llm_llm_tx_top_llmx08_tx_packet_packer_next_arb_state_i_i_0_o4_1_.INIT = 4'h8; + LUT2 com_llm_llm_tx_top_llmx08_tx_packet_packer_next_arb_state_i_i_0_o4_1_ ( + .I0(com_llm_llm_tx_top_tx_tlp_sof_n), + .I1(com_llm_llm_tx_top_tx_tlp_sof_pre_n), + .O(com_llm_llm_tx_top_N_41766_i) + ); + defparam com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_i_a4_0_.INIT = 4'h4; + LUT2 com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_i_a4_0_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_packet_packer_aligned_1490), + .I1(com_llm_llm_tx_top_reg_tx_pp_idle), + .O(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_43110) + ); + defparam com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_i_a3_1_0_.INIT = 4'h1; + LUT2 com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_i_a3_1_0_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_packet_packer_aligned_1490), + .I1(com_llm_llm_tx_top_arb_state[2]), + .O(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_43106) + ); + defparam com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_i_a3_0_0_.INIT = 4'h4; + LUT2 com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_i_a3_0_0_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_packet_packer_aligned_1490), + .I1(com_llm_llm_tx_top_arb_state[2]), + .O(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_43103) + ); + defparam com_llm_llm_tx_top_llmx08_tx_packet_packer_aligned_4_0_a3.INIT = 4'h1; + LUT2 com_llm_llm_tx_top_llmx08_tx_packet_packer_aligned_4_0_a3 ( + .I0(com_llm_llm_tx_top_llmx08_tx_packet_packer_aligned_1490), + .I1(com_llm_llm_tx_top_llmx08_tx_packet_packer_trans_non_aligned_1413), + .O(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_43102) + ); + defparam com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_i_a3_0_.INIT = 4'h2; + LUT2 com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_i_a3_0_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_packet_packer_aligned_1490), + .I1(com_llm_llm_tx_top_reg_tx_pp_idle), + .O(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_43098) + ); + defparam com_llm_llm_tx_top_llmx08_tx_packet_packer_next_arb_state_0_sqmuxa_0_a2.INIT = 4'h8; + LUT2 com_llm_llm_tx_top_llmx08_tx_packet_packer_next_arb_state_0_sqmuxa_0_a2 ( + .I0(com_llm_llm_tx_top_llmx08_tx_packet_packer_tx_idle_next_1486), + .I1(com_llm_llm_tx_top_reg_tx_pp_idle), + .O(com_llm_llm_tx_top_llmx08_tx_packet_packer_next_arb_state_0_sqmuxa) + ); + defparam com_llm_llm_tx_top_llmx08_tx_packet_packer_next_arb_state_i_i_o3_0_2_.INIT = 4'h1; + LUT2_L com_llm_llm_tx_top_llmx08_tx_packet_packer_next_arb_state_i_i_o3_0_2_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_packet_packer_tx_idle_next_1486), + .I1(com_llm_llm_tx_top_tx_dllp_tx_next_pre), + .LO(com_llm_llm_tx_top_llmx08_tx_packet_packer_next_arb_state_i_i_o3_0[2]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_0_m4_0_31_.INIT = 8'hE4; + LUT3 com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_0_m4_0_31_ ( + .I0(com_llm_llm_tx_top_arb_state[2]), + .I1(com_llm_llm_tx_top_tx_dllp_td_31_), + .I2(com_llm_llm_tx_top_tx_tlp_td[31]), + .O(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_41794) + ); + defparam com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_0_m4_0_30_.INIT = 8'hE4; + LUT3 com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_0_m4_0_30_ ( + .I0(com_llm_llm_tx_top_arb_state[2]), + .I1(com_llm_llm_tx_top_tx_dllp_td_30_), + .I2(com_llm_llm_tx_top_tx_tlp_td[30]), + .O(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_41795) + ); + defparam com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_0_m4_0_29_.INIT = 8'hE4; + LUT3 com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_0_m4_0_29_ ( + .I0(com_llm_llm_tx_top_arb_state[2]), + .I1(com_llm_llm_tx_top_tx_dllp_td_29_), + .I2(com_llm_llm_tx_top_tx_tlp_td[29]), + .O(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_41796) + ); + defparam com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_0_m4_0_28_.INIT = 8'hE4; + LUT3 com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_0_m4_0_28_ ( + .I0(com_llm_llm_tx_top_arb_state[2]), + .I1(com_llm_llm_tx_top_tx_dllp_td_28_), + .I2(com_llm_llm_tx_top_tx_tlp_td[28]), + .O(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_41797) + ); + defparam com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_0_m4_0_27_.INIT = 8'hE4; + LUT3 com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_0_m4_0_27_ ( + .I0(com_llm_llm_tx_top_arb_state[2]), + .I1(com_llm_llm_tx_top_tx_dllp_td_27_), + .I2(com_llm_llm_tx_top_tx_tlp_td[27]), + .O(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_41798) + ); + defparam com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_0_m4_0_26_.INIT = 8'hE4; + LUT3 com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_0_m4_0_26_ ( + .I0(com_llm_llm_tx_top_arb_state[2]), + .I1(com_llm_llm_tx_top_tx_dllp_td_26_), + .I2(com_llm_llm_tx_top_tx_tlp_td[26]), + .O(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_41799) + ); + defparam com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_0_m4_0_24_.INIT = 8'hE4; + LUT3 com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_0_m4_0_24_ ( + .I0(com_llm_llm_tx_top_arb_state[2]), + .I1(com_llm_llm_tx_top_tx_dllp_td_24_), + .I2(com_llm_llm_tx_top_tx_tlp_td[24]), + .O(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_41801) + ); + defparam com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_0_m4_0_25_.INIT = 8'hE4; + LUT3 com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_0_m4_0_25_ ( + .I0(com_llm_llm_tx_top_arb_state[2]), + .I1(com_llm_llm_tx_top_tx_dllp_td_25_), + .I2(com_llm_llm_tx_top_tx_tlp_td[25]), + .O(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_41800) + ); + defparam com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_0_a2_0_31_.INIT = 4'h8; + LUT2_L com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_0_a2_0_31_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_43103), + .I1(com_llm_llm_tx_top_tx_tlp_td[63]), + .LO(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_42210) + ); + defparam com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_0_a2_0_30_.INIT = 4'h8; + LUT2_L com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_0_a2_0_30_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_43103), + .I1(com_llm_llm_tx_top_tx_tlp_td[62]), + .LO(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_42208) + ); + defparam com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_0_a2_0_29_.INIT = 4'h8; + LUT2_L com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_0_a2_0_29_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_43103), + .I1(com_llm_llm_tx_top_tx_tlp_td[61]), + .LO(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_42206) + ); + defparam com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_0_a2_0_28_.INIT = 4'h8; + LUT2_L com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_0_a2_0_28_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_43103), + .I1(com_llm_llm_tx_top_tx_tlp_td[60]), + .LO(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_42204) + ); + defparam com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_0_a2_0_27_.INIT = 4'h8; + LUT2_L com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_0_a2_0_27_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_43103), + .I1(com_llm_llm_tx_top_tx_tlp_td[59]), + .LO(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_42202) + ); + defparam com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_0_a2_0_26_.INIT = 4'h8; + LUT2_L com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_0_a2_0_26_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_43103), + .I1(com_llm_llm_tx_top_tx_tlp_td[58]), + .LO(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_42200) + ); + defparam com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_0_a2_0_25_.INIT = 4'h8; + LUT2_L com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_0_a2_0_25_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_43103), + .I1(com_llm_llm_tx_top_tx_tlp_td[57]), + .LO(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_42198) + ); + defparam com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_0_a2_1_24_.INIT = 4'h8; + LUT2_L com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_0_a2_1_24_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_43103), + .I1(com_llm_llm_tx_top_tx_tlp_td[56]), + .LO(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_42196) + ); + defparam com_llm_llm_tx_top_llmx08_tx_packet_packer_next_arb_state_0_i_o3_0_0_.INIT = 16'h31F5; + LUT4 com_llm_llm_tx_top_llmx08_tx_packet_packer_next_arb_state_0_i_o3_0_0_ ( + .I0(com_llm_llm_tx_top_arb_state[2]), + .I1(com_llm_llm_tx_top_reg_tx_pp_idle), + .I2(com_llm_llm_tx_top_tx_tlp_eof_n), + .I3(com_llm_llm_tx_top_tx_tlp_sof_n), + .O(com_llm_llm_tx_top_llmx08_tx_packet_packer_next_arb_state_0_i_o3_0[0]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_i_0_14_.INIT = 4'h1; + LUT2 com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_i_0_14_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_43106), + .I1(com_llm_llm_tx_top_reg_tx_pp_idle), + .O(com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_i_0_i[15]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_packet_packer_next_arb_state_0_i_o3_0_.INIT = 8'h10; + LUT3 com_llm_llm_tx_top_llmx08_tx_packet_packer_next_arb_state_0_i_o3_0_ ( + .I0(com_llm_llm_tx_top_reg_tx_pp_idle), + .I1(com_llm_llm_tx_top_tx_dllp_accepted), + .I2(com_llm_llm_tx_top_tx_tlp_eof_n), + .O(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_17372_i) + ); + defparam com_llm_llm_tx_top_llmx08_tx_packet_packer_next_arb_state_i_i_0_a2_2_1_.INIT = 16'h0001; + LUT4 com_llm_llm_tx_top_llmx08_tx_packet_packer_next_arb_state_i_i_0_a2_2_1_ ( + .I0(com_llm_llm_tx_top_tx_dllp_tx_next), + .I1(com_llm_llm_tx_top_tx_dllp_tx_next_pre), + .I2(com_llm_llm_tx_top_tx_tlp_eof_n), + .I3(com_llm_llm_tx_top_tx_tlp_sof_pre_n), + .O(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_42596) + ); + defparam com_llm_llm_tx_top_llmx08_tx_packet_packer_next_arb_state_i_i_a2_0_2_.INIT = 16'h1030; + LUT4 com_llm_llm_tx_top_llmx08_tx_packet_packer_next_arb_state_i_i_a2_0_2_ ( + .I0(com_llm_llm_tx_top_arb_state[2]), + .I1(com_llm_llm_tx_top_tx_dllp_accepted), + .I2(com_llm_llm_tx_top_tx_dllp_tx_next), + .I3(com_llm_llm_tx_top_tx_tlp_eof_n), + .O(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_17390) + ); + defparam com_llm_llm_tx_top_llmx08_tx_packet_packer_next_arb_state_i_i_0_a2_1_0_1_.INIT = 8'h01; + LUT3 com_llm_llm_tx_top_llmx08_tx_packet_packer_next_arb_state_i_i_0_a2_1_0_1_ ( + .I0(com_llm_llm_tx_top_arb_state[2]), + .I1(com_llm_llm_tx_top_tx_dllp_tx_next), + .I2(com_llm_llm_tx_top_tx_dllp_tx_next_pre), + .O(com_llm_llm_tx_top_llmx08_tx_packet_packer_next_arb_state_i_i_0_a2_1_0[1]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_i_o2_0_.INIT = 4'h1; + LUT2 com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_i_o2_0_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_43100), + .I1(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_43110), + .O(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_41737_i) + ); + defparam com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_0_o4_32_.INIT = 16'hAF27; + LUT4 com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_0_o4_32_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_packet_packer_aligned_1490), + .I1(com_llm_llm_tx_top_arb_state[2]), + .I2(com_llm_llm_tx_top_llmx08_tx_packet_packer_trans_non_aligned_1413), + .I3(com_llm_llm_tx_top_reg_tx_pp_idle), + .O(com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_0_o4[32]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_packet_packer_next_arb_state_i_i_0_a2_4_1_.INIT = 16'h8000; + LUT4 com_llm_llm_tx_top_llmx08_tx_packet_packer_next_arb_state_i_i_0_a2_4_1_ ( + .I0(com_llm_llm_tx_top_arb_state[2]), + .I1(com_llm_llm_tx_top_tx_dllp_vld_n), + .I2(com_llm_llm_tx_top_tx_dllp_vld_pre_n), + .I3(com_llm_llm_tx_top_tx_tlp_eof_n), + .O(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_42598) + ); + defparam com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_i_12_32081.INIT = 16'hFEBA; + LUT4 com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_i_12_32081 ( + .I0(com_llm_llm_tx_top_llmx08_tx_packet_packer_aligned_1490), + .I1(com_llm_llm_tx_top_arb_state[2]), + .I2(com_llm_llm_tx_top_tx_dllp_td_44_), + .I3(com_llm_llm_tx_top_tx_tlp_td[44]), + .O(com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_i_12_32081_1479) + ); + defparam com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_i_11_32082.INIT = 16'hFEBA; + LUT4 com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_i_11_32082 ( + .I0(com_llm_llm_tx_top_llmx08_tx_packet_packer_aligned_1490), + .I1(com_llm_llm_tx_top_arb_state[2]), + .I2(com_llm_llm_tx_top_tx_dllp_td_43_), + .I3(com_llm_llm_tx_top_tx_tlp_td[43]), + .O(com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_i_11_32082_1480) + ); + defparam com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_i_10_32083.INIT = 16'hFEBA; + LUT4 com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_i_10_32083 ( + .I0(com_llm_llm_tx_top_llmx08_tx_packet_packer_aligned_1490), + .I1(com_llm_llm_tx_top_arb_state[2]), + .I2(com_llm_llm_tx_top_tx_dllp_td_42_), + .I3(com_llm_llm_tx_top_tx_tlp_td[42]), + .O(com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_i_10_32083_1481) + ); + defparam com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_i_8_32084.INIT = 16'hFEBA; + LUT4 com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_i_8_32084 ( + .I0(com_llm_llm_tx_top_llmx08_tx_packet_packer_aligned_1490), + .I1(com_llm_llm_tx_top_arb_state[2]), + .I2(com_llm_llm_tx_top_tx_dllp_td_40_), + .I3(com_llm_llm_tx_top_tx_tlp_td[40]), + .O(com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_i_8_32084_1483) + ); + defparam com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_i_22_32085.INIT = 16'hFEBA; + LUT4 com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_i_22_32085 ( + .I0(com_llm_llm_tx_top_llmx08_tx_packet_packer_aligned_1490), + .I1(com_llm_llm_tx_top_arb_state[2]), + .I2(com_llm_llm_tx_top_tx_dllp_td_54_), + .I3(com_llm_llm_tx_top_tx_tlp_td[54]), + .O(com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_i_22_32085_1473) + ); + defparam com_llm_llm_tx_top_llmx08_tx_packet_packer_next_arb_state_i_i_2_32138.INIT = 16'hE2EA; + LUT4 com_llm_llm_tx_top_llmx08_tx_packet_packer_next_arb_state_i_i_2_32138 ( + .I0(com_llm_llm_tx_top_llmx08_tx_packet_packer_next_arb_state_i_i_o3_0[2]), + .I1(com_llm_llm_tx_top_arb_state[2]), + .I2(com_llm_llm_tx_top_tx_tlp_eof_n), + .I3(com_llm_llm_tx_top_tx_tlp_sof_pre_n), + .O(com_llm_llm_tx_top_llmx08_tx_packet_packer_next_arb_state_i_i_2_32138_1485) + ); + defparam com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_i_16_32150.INIT = 16'hFEBA; + LUT4 com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_i_16_32150 ( + .I0(com_llm_llm_tx_top_llmx08_tx_packet_packer_aligned_1490), + .I1(com_llm_llm_tx_top_arb_state[2]), + .I2(com_llm_llm_tx_top_tx_dllp_td_48_), + .I3(com_llm_llm_tx_top_tx_tlp_td[48]), + .O(com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_i_16_32150_1477) + ); + defparam com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_i_13_32151.INIT = 16'hFEBA; + LUT4 com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_i_13_32151 ( + .I0(com_llm_llm_tx_top_llmx08_tx_packet_packer_aligned_1490), + .I1(com_llm_llm_tx_top_arb_state[2]), + .I2(com_llm_llm_tx_top_tx_dllp_td_45_), + .I3(com_llm_llm_tx_top_tx_tlp_td[45]), + .O(com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_i_13_32151_1478) + ); + defparam com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_i_9_32152.INIT = 16'hFEBA; + LUT4 com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_i_9_32152 ( + .I0(com_llm_llm_tx_top_llmx08_tx_packet_packer_aligned_1490), + .I1(com_llm_llm_tx_top_arb_state[2]), + .I2(com_llm_llm_tx_top_tx_dllp_td_41_), + .I3(com_llm_llm_tx_top_tx_tlp_td[41]), + .O(com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_i_9_32152_1482) + ); + defparam com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_i_23_32153.INIT = 16'hFEBA; + LUT4 com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_i_23_32153 ( + .I0(com_llm_llm_tx_top_llmx08_tx_packet_packer_aligned_1490), + .I1(com_llm_llm_tx_top_arb_state[2]), + .I2(com_llm_llm_tx_top_tx_dllp_td_55_), + .I3(com_llm_llm_tx_top_tx_tlp_td[55]), + .O(com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_i_23_32153_1472) + ); + defparam com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_i_20_32154.INIT = 16'hFEBA; + LUT4 com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_i_20_32154 ( + .I0(com_llm_llm_tx_top_llmx08_tx_packet_packer_aligned_1490), + .I1(com_llm_llm_tx_top_arb_state[2]), + .I2(com_llm_llm_tx_top_tx_dllp_td_52_), + .I3(com_llm_llm_tx_top_tx_tlp_td[52]), + .O(com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_i_20_32154_1475) + ); + defparam com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_i_21_32186.INIT = 16'hFEBA; + LUT4 com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_i_21_32186 ( + .I0(com_llm_llm_tx_top_llmx08_tx_packet_packer_aligned_1490), + .I1(com_llm_llm_tx_top_arb_state[2]), + .I2(com_llm_llm_tx_top_tx_dllp_td_53_), + .I3(com_llm_llm_tx_top_tx_tlp_td[53]), + .O(com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_i_21_32186_1474) + ); + defparam com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_i_17_32187.INIT = 16'hFEBA; + LUT4 com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_i_17_32187 ( + .I0(com_llm_llm_tx_top_llmx08_tx_packet_packer_aligned_1490), + .I1(com_llm_llm_tx_top_arb_state[2]), + .I2(com_llm_llm_tx_top_tx_dllp_td_49_), + .I3(com_llm_llm_tx_top_tx_tlp_td[49]), + .O(com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_i_17_32187_1476) + ); + defparam com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_i_0_6_.INIT = 16'hF351; + LUT4 com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_i_0_6_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_43098), + .I1(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_43106), + .I2(com_llm_llm_tx_top_tx_dllp_td_38_), + .I3(com_llm_llm_tx_top_tx_tlp_td[6]), + .O(com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_i_0[6]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_i_0_0_.INIT = 16'hF351; + LUT4 com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_i_0_0_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_43098), + .I1(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_43106), + .I2(com_llm_llm_tx_top_tx_dllp_td_32_), + .I3(com_llm_llm_tx_top_tx_tlp_td[0]), + .O(com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_i_0[0]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_i_0_2_.INIT = 16'hF351; + LUT4 com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_i_0_2_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_43098), + .I1(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_43106), + .I2(com_llm_llm_tx_top_tx_dllp_td_34_), + .I3(com_llm_llm_tx_top_tx_tlp_td[2]), + .O(com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_i_0[2]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_i_0_3_.INIT = 16'hF351; + LUT4 com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_i_0_3_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_43098), + .I1(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_43106), + .I2(com_llm_llm_tx_top_tx_dllp_td_35_), + .I3(com_llm_llm_tx_top_tx_tlp_td[3]), + .O(com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_i_0[3]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_i_0_1_.INIT = 16'hF351; + LUT4 com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_i_0_1_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_43098), + .I1(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_43106), + .I2(com_llm_llm_tx_top_tx_dllp_td_33_), + .I3(com_llm_llm_tx_top_tx_tlp_td[1]), + .O(com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_i_0[1]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_i_0_7_.INIT = 16'hF351; + LUT4 com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_i_0_7_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_43098), + .I1(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_43106), + .I2(com_llm_llm_tx_top_tx_dllp_td_39_), + .I3(com_llm_llm_tx_top_tx_tlp_td[7]), + .O(com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_i_0[7]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_i_0_4_.INIT = 16'hF531; + LUT4 com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_i_0_4_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_43098), + .I1(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_43103), + .I2(com_llm_llm_tx_top_tx_tlp_td[4]), + .I3(com_llm_llm_tx_top_tx_tlp_td[36]), + .O(com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_i_0[4]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_i_0_5_.INIT = 16'hF531; + LUT4 com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_i_0_5_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_43098), + .I1(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_43103), + .I2(com_llm_llm_tx_top_tx_tlp_td[5]), + .I3(com_llm_llm_tx_top_tx_tlp_td[37]), + .O(com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_i_0[5]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_i_a2_63_.INIT = 4'h1; + LUT2_L com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_i_a2_63_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_0_o4[32]), + .I1(com_llm_llm_tx_top_tx_tlp_td[63]), + .LO(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_42298) + ); + defparam com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_i_a2_62_.INIT = 4'h1; + LUT2_L com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_i_a2_62_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_0_o4[32]), + .I1(com_llm_llm_tx_top_tx_tlp_td[62]), + .LO(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_42296) + ); + defparam com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_i_a2_61_.INIT = 4'h1; + LUT2_L com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_i_a2_61_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_0_o4[32]), + .I1(com_llm_llm_tx_top_tx_tlp_td[61]), + .LO(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_42294) + ); + defparam com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_i_a2_60_.INIT = 4'h1; + LUT2_L com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_i_a2_60_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_0_o4[32]), + .I1(com_llm_llm_tx_top_tx_tlp_td[60]), + .LO(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_42292) + ); + defparam com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_i_a2_59_.INIT = 4'h1; + LUT2_L com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_i_a2_59_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_0_o4[32]), + .I1(com_llm_llm_tx_top_tx_tlp_td[59]), + .LO(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_42290) + ); + defparam com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_i_a2_58_.INIT = 4'h1; + LUT2_L com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_i_a2_58_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_0_o4[32]), + .I1(com_llm_llm_tx_top_tx_tlp_td[58]), + .LO(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_42288) + ); + defparam com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_i_a2_57_.INIT = 4'h1; + LUT2_L com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_i_a2_57_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_0_o4[32]), + .I1(com_llm_llm_tx_top_tx_tlp_td[57]), + .LO(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_42286) + ); + defparam com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_i_a2_56_.INIT = 4'h1; + LUT2_L com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_i_a2_56_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_0_o4[32]), + .I1(com_llm_llm_tx_top_tx_tlp_td[56]), + .LO(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_42283) + ); + defparam com_llm_llm_tx_top_llmx08_tx_packet_packer_next_arb_state_0_i_a2_3_0_.INIT = 16'h1000; + LUT4 com_llm_llm_tx_top_llmx08_tx_packet_packer_next_arb_state_0_i_a2_3_0_ ( + .I0(com_llm_llm_tx_top_tx_dllp_tx_next), + .I1(com_llm_llm_tx_top_tx_dllp_tx_next_pre), + .I2(com_llm_llm_tx_top_tx_dllp_vld_n), + .I3(com_llm_llm_tx_top_tx_dllp_vld_pre_n), + .O(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_17399_3) + ); + defparam com_llm_llm_tx_top_llmx08_tx_packet_packer_next_arb_state_0_i_a2_2_0_.INIT = 16'h0800; + LUT4 com_llm_llm_tx_top_llmx08_tx_packet_packer_next_arb_state_0_i_a2_2_0_ ( + .I0(com_llm_llm_tx_top_N_41766_i), + .I1(com_llm_llm_tx_top_tx_dllp_accepted), + .I2(com_llm_llm_tx_top_tx_dllp_tx_next_pre), + .I3(com_llm_llm_tx_top_tx_dllp_vld_pre_n), + .O(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_17402) + ); + defparam com_llm_llm_tx_top_llmx08_tx_packet_packer_next_arb_state_i_i_2_32140.INIT = 8'h13; + LUT3_L com_llm_llm_tx_top_llmx08_tx_packet_packer_next_arb_state_i_i_2_32140 ( + .I0(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_17372_i), + .I1(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_17390), + .I2(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_41820_i), + .LO(com_llm_llm_tx_top_llmx08_tx_packet_packer_next_arb_state_i_i_2_32140_1484) + ); + defparam com_llm_llm_tx_top_llmx08_tx_packet_packer_next_arb_state_i_i_0_1_32158.INIT = 16'hBBAB; + LUT4_L com_llm_llm_tx_top_llmx08_tx_packet_packer_next_arb_state_i_i_0_1_32158 ( + .I0(com_llm_llm_tx_top_N_41766_i), + .I1(com_llm_llm_tx_top_llmx08_tx_packet_packer_next_arb_state_i_i_0_a2_1_0[1]), + .I2(com_llm_llm_tx_top_tx_dllp_accepted), + .I3(com_llm_llm_tx_top_tx_dllp_tx_next_pre), + .LO(com_llm_llm_tx_top_llmx08_tx_packet_packer_next_arb_state_i_i_0_1_32158_1410) + ); + defparam com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_0_0_40_.INIT = 16'h153F; + LUT4_L com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_0_0_40_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_43100), + .I1(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_43102), + .I2(com_llm_llm_tx_top_llmx08_tx_packet_packer_prev_td[8]), + .I3(com_llm_llm_tx_top_tx_dllp_td_40_), + .LO(com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_0_0_40__1449) + ); + defparam com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_0_0_44_.INIT = 16'h153F; + LUT4_L com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_0_0_44_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_43100), + .I1(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_43102), + .I2(com_llm_llm_tx_top_llmx08_tx_packet_packer_prev_td[12]), + .I3(com_llm_llm_tx_top_tx_dllp_td_44_), + .LO(com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_0_0_44__1441) + ); + defparam com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_0_0_53_.INIT = 16'h153F; + LUT4_L com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_0_0_53_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_43100), + .I1(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_43102), + .I2(com_llm_llm_tx_top_llmx08_tx_packet_packer_prev_td[21]), + .I3(com_llm_llm_tx_top_tx_dllp_td_53_), + .LO(com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_0_0_53__1427) + ); + defparam com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_0_0_32_.INIT = 16'h153F; + LUT4_L com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_0_0_32_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_43100), + .I1(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_43102), + .I2(com_llm_llm_tx_top_llmx08_tx_packet_packer_prev_td[0]), + .I3(com_llm_llm_tx_top_tx_dllp_td_32_), + .LO(com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_0_0_32__1463) + ); + defparam com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_0_0_41_.INIT = 16'h153F; + LUT4_L com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_0_0_41_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_43100), + .I1(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_43102), + .I2(com_llm_llm_tx_top_llmx08_tx_packet_packer_prev_td[9]), + .I3(com_llm_llm_tx_top_tx_dllp_td_41_), + .LO(com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_0_0_41__1447) + ); + defparam com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_0_0_48_.INIT = 16'h153F; + LUT4_L com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_0_0_48_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_43100), + .I1(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_43102), + .I2(com_llm_llm_tx_top_llmx08_tx_packet_packer_prev_td[16]), + .I3(com_llm_llm_tx_top_tx_dllp_td_48_), + .LO(com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_0_0_48__1435) + ); + defparam com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_0_0_49_.INIT = 16'h153F; + LUT4_L com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_0_0_49_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_43100), + .I1(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_43102), + .I2(com_llm_llm_tx_top_llmx08_tx_packet_packer_prev_td[17]), + .I3(com_llm_llm_tx_top_tx_dllp_td_49_), + .LO(com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_0_0_49__1433) + ); + defparam com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_0_0_34_.INIT = 16'h153F; + LUT4_L com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_0_0_34_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_43100), + .I1(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_43102), + .I2(com_llm_llm_tx_top_llmx08_tx_packet_packer_prev_td[2]), + .I3(com_llm_llm_tx_top_tx_dllp_td_34_), + .LO(com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_0_0_34__1459) + ); + defparam com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_0_0_54_.INIT = 16'h153F; + LUT4_L com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_0_0_54_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_43100), + .I1(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_43102), + .I2(com_llm_llm_tx_top_llmx08_tx_packet_packer_prev_td[22]), + .I3(com_llm_llm_tx_top_tx_dllp_td_54_), + .LO(com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_0_0_54__1425) + ); + defparam com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_0_0_52_.INIT = 16'h153F; + LUT4_L com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_0_0_52_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_43100), + .I1(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_43102), + .I2(com_llm_llm_tx_top_llmx08_tx_packet_packer_prev_td[20]), + .I3(com_llm_llm_tx_top_tx_dllp_td_52_), + .LO(com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_0_0_52__1429) + ); + defparam com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_0_0_38_.INIT = 16'h153F; + LUT4_L com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_0_0_38_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_43100), + .I1(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_43102), + .I2(com_llm_llm_tx_top_llmx08_tx_packet_packer_prev_td[6]), + .I3(com_llm_llm_tx_top_tx_dllp_td_38_), + .LO(com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_0_0_38__1453) + ); + defparam com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_0_0_35_.INIT = 16'h153F; + LUT4_L com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_0_0_35_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_43100), + .I1(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_43102), + .I2(com_llm_llm_tx_top_llmx08_tx_packet_packer_prev_td[3]), + .I3(com_llm_llm_tx_top_tx_dllp_td_35_), + .LO(com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_0_0_35__1457) + ); + defparam com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_0_0_45_.INIT = 16'h153F; + LUT4_L com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_0_0_45_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_43100), + .I1(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_43102), + .I2(com_llm_llm_tx_top_llmx08_tx_packet_packer_prev_td[13]), + .I3(com_llm_llm_tx_top_tx_dllp_td_45_), + .LO(com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_0_0_45__1439) + ); + defparam com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_0_0_33_.INIT = 16'h153F; + LUT4_L com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_0_0_33_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_43100), + .I1(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_43102), + .I2(com_llm_llm_tx_top_llmx08_tx_packet_packer_prev_td[1]), + .I3(com_llm_llm_tx_top_tx_dllp_td_33_), + .LO(com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_0_0_33__1461) + ); + defparam com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_0_0_42_.INIT = 16'h153F; + LUT4_L com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_0_0_42_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_43100), + .I1(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_43102), + .I2(com_llm_llm_tx_top_llmx08_tx_packet_packer_prev_td[10]), + .I3(com_llm_llm_tx_top_tx_dllp_td_42_), + .LO(com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_0_0_42__1445) + ); + defparam com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_0_0_39_.INIT = 16'h153F; + LUT4_L com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_0_0_39_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_43100), + .I1(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_43102), + .I2(com_llm_llm_tx_top_llmx08_tx_packet_packer_prev_td[7]), + .I3(com_llm_llm_tx_top_tx_dllp_td_39_), + .LO(com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_0_0_39__1451) + ); + defparam com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_0_0_43_.INIT = 16'h153F; + LUT4_L com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_0_0_43_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_43100), + .I1(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_43102), + .I2(com_llm_llm_tx_top_llmx08_tx_packet_packer_prev_td[11]), + .I3(com_llm_llm_tx_top_tx_dllp_td_43_), + .LO(com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_0_0_43__1443) + ); + defparam com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_0_0_55_.INIT = 16'h153F; + LUT4_L com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_0_0_55_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_43100), + .I1(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_43102), + .I2(com_llm_llm_tx_top_llmx08_tx_packet_packer_prev_td[23]), + .I3(com_llm_llm_tx_top_tx_dllp_td_55_), + .LO(com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_0_0_55__1423) + ); + defparam com_llm_llm_tx_top_llmx08_tx_packet_packer_next_arb_state_0_i_a2_1_0_.INIT = 8'hA8; + LUT3_L com_llm_llm_tx_top_llmx08_tx_packet_packer_next_arb_state_0_i_a2_1_0_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_41820_i), + .I1(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_42598), + .I2(com_llm_llm_tx_top_llmx08_tx_packet_packer_tx_idle_next_1486), + .LO(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_17401) + ); + defparam com_llm_llm_tx_top_llmx08_tx_packet_packer_next_arb_state_i_i_0_1_32157.INIT = 16'h5155; + LUT4_L com_llm_llm_tx_top_llmx08_tx_packet_packer_next_arb_state_i_i_0_1_32157 ( + .I0(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_17399_3), + .I1(com_llm_llm_tx_top_tx_dllp_accepted), + .I2(com_llm_llm_tx_top_tx_dllp_tx_next_pre), + .I3(com_llm_llm_tx_top_tx_dllp_vld_pre_n), + .LO(com_llm_llm_tx_top_llmx08_tx_packet_packer_next_arb_state_i_i_0_1_32157_1488) + ); + defparam com_llm_llm_tx_top_llmx08_tx_packet_packer_current_td_0_i_m4_0_16_.INIT = 16'hED21; + LUT4 com_llm_llm_tx_top_llmx08_tx_packet_packer_current_td_0_i_m4_0_16_ ( + .I0(N_10594), + .I1(com_llm_llm_tx_top_arb_state[2]), + .I2(com_llm_llm_tx_top_llmx08_tx_packet_packer_new_c32_1_2_15_), + .I3(com_llm_llm_tx_top_tx_tlp_td[16]), + .O(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_51495) + ); + defparam com_llm_llm_tx_top_llmx08_tx_packet_packer_next_arb_state_i_i_0_1_32161.INIT = 16'h0D00; + LUT4 com_llm_llm_tx_top_llmx08_tx_packet_packer_next_arb_state_i_i_0_1_32161 ( + .I0(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_17372_i), + .I1(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_41820_i), + .I2(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_42596), + .I3(com_llm_llm_tx_top_llmx08_tx_packet_packer_next_arb_state_i_i_0_1_32158_1410), + .O(com_llm_llm_tx_top_llmx08_tx_packet_packer_next_arb_state_i_i_0_1_32161_1487) + ); + defparam com_llm_llm_tx_top_llmx08_tx_packet_packer_next_arb_state_0_i_1_0_.INIT = 16'h0203; + LUT4_L com_llm_llm_tx_top_llmx08_tx_packet_packer_next_arb_state_0_i_1_0_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_17372_i), + .I1(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_17401), + .I2(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_17402), + .I3(com_llm_llm_tx_top_llmx08_tx_packet_packer_tx_idle_next_1486), + .LO(com_llm_llm_tx_top_llmx08_tx_packet_packer_next_arb_state_0_i_1[0]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_i_a2_19_.INIT = 16'h028A; + LUT4_L com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_i_a2_19_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_packet_packer_aligned_1490), + .I1(com_llm_llm_tx_top_arb_state[2]), + .I2(com_llm_llm_tx_top_llmx08_tx_packet_packer_new_c32_1_i_12_), + .I3(com_llm_llm_tx_top_tx_tlp_td[19]), + .LO(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_42179) + ); + defparam com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_i_a2_18_.INIT = 16'h028A; + LUT4_L com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_i_a2_18_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_packet_packer_aligned_1490), + .I1(com_llm_llm_tx_top_arb_state[2]), + .I2(com_llm_llm_tx_top_llmx08_tx_packet_packer_new_c32_1_i_13_), + .I3(com_llm_llm_tx_top_tx_tlp_td[18]), + .LO(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_42176) + ); + defparam com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_i_a2_15_.INIT = 16'h028A; + LUT4_L com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_i_a2_15_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_packet_packer_aligned_1490), + .I1(com_llm_llm_tx_top_arb_state[2]), + .I2(com_llm_llm_tx_top_llmx08_tx_packet_packer_new_c32_1_i_0_), + .I3(com_llm_llm_tx_top_tx_tlp_td[15]), + .LO(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_42167) + ); + defparam com_llm_llm_tx_top_llmx08_tx_packet_packer_current_td_0_i_m4_0_8_.INIT = 16'hBE14; + LUT4 com_llm_llm_tx_top_llmx08_tx_packet_packer_current_td_0_i_m4_0_8_ ( + .I0(com_llm_llm_tx_top_arb_state[2]), + .I1(com_llm_llm_tx_top_llmx08_tx_packet_packer_new_c32_1_1_7_), + .I2(com_llm_llm_tx_top_llmx08_tx_packet_packer_new_c32_1_2_7_), + .I3(com_llm_llm_tx_top_tx_tlp_td[8]), + .O(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_51487) + ); + defparam com_llm_llm_tx_top_llmx08_tx_packet_packer_current_td_0_i_m4_0_9_.INIT = 16'hED21; + LUT4 com_llm_llm_tx_top_llmx08_tx_packet_packer_current_td_0_i_m4_0_9_ ( + .I0(N_10563), + .I1(com_llm_llm_tx_top_arb_state[2]), + .I2(com_llm_llm_tx_top_llmx08_tx_packet_packer_new_c32_1_1_6_), + .I3(com_llm_llm_tx_top_tx_tlp_td[9]), + .O(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_51488) + ); + defparam com_llm_llm_tx_top_llmx08_tx_packet_packer_current_td_0_i_m4_0_11_.INIT = 16'hDE12; + LUT4 com_llm_llm_tx_top_llmx08_tx_packet_packer_current_td_0_i_m4_0_11_ ( + .I0(N_10532), + .I1(com_llm_llm_tx_top_arb_state[2]), + .I2(com_llm_llm_tx_top_llmx08_tx_packet_packer_new_c32_1_2_4_), + .I3(com_llm_llm_tx_top_tx_tlp_td[11]), + .O(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_51490) + ); + defparam com_llm_llm_tx_top_llmx08_tx_packet_packer_current_td_0_i_m4_0_13_.INIT = 16'hED21; + LUT4 com_llm_llm_tx_top_llmx08_tx_packet_packer_current_td_0_i_m4_0_13_ ( + .I0(N_10549), + .I1(com_llm_llm_tx_top_arb_state[2]), + .I2(com_llm_llm_tx_top_llmx08_tx_packet_packer_new_c32_1_1_2_), + .I3(com_llm_llm_tx_top_tx_tlp_td[13]), + .O(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_51492) + ); + defparam com_llm_llm_tx_top_llmx08_tx_packet_packer_current_td_0_i_m4_0_17_.INIT = 8'hB1; + LUT3 com_llm_llm_tx_top_llmx08_tx_packet_packer_current_td_0_i_m4_0_17_ ( + .I0(com_llm_llm_tx_top_arb_state[2]), + .I1(com_llm_llm_tx_top_llmx08_tx_packet_packer_new_c32_14_), + .I2(com_llm_llm_tx_top_tx_tlp_td[17]), + .O(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_51496) + ); + defparam com_llm_llm_tx_top_llmx08_tx_packet_packer_current_td_0_i_m4_0_20_.INIT = 8'hB1; + LUT3 com_llm_llm_tx_top_llmx08_tx_packet_packer_current_td_0_i_m4_0_20_ ( + .I0(com_llm_llm_tx_top_arb_state[2]), + .I1(com_llm_llm_tx_top_llmx08_tx_packet_packer_new_c32_11_), + .I2(com_llm_llm_tx_top_tx_tlp_td[20]), + .O(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_51499) + ); + defparam com_llm_llm_tx_top_llmx08_tx_packet_packer_current_td_0_i_m4_0_21_.INIT = 8'hB1; + LUT3 com_llm_llm_tx_top_llmx08_tx_packet_packer_current_td_0_i_m4_0_21_ ( + .I0(com_llm_llm_tx_top_arb_state[2]), + .I1(com_llm_llm_tx_top_llmx08_tx_packet_packer_new_c32_10_), + .I2(com_llm_llm_tx_top_tx_tlp_td[21]), + .O(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_51500) + ); + defparam com_llm_llm_tx_top_llmx08_tx_packet_packer_current_td_0_i_m4_0_23_.INIT = 8'hB1; + LUT3 com_llm_llm_tx_top_llmx08_tx_packet_packer_current_td_0_i_m4_0_23_ ( + .I0(com_llm_llm_tx_top_arb_state[2]), + .I1(com_llm_llm_tx_top_llmx08_tx_packet_packer_new_c32_8_), + .I2(com_llm_llm_tx_top_tx_tlp_td[23]), + .O(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_51502) + ); + defparam com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_i_a2_14_.INIT = 16'h20A8; + LUT4_L com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_i_a2_14_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_packet_packer_aligned_1490), + .I1(com_llm_llm_tx_top_arb_state[2]), + .I2(com_llm_llm_tx_top_llmx08_tx_packet_packer_new_c32_1_), + .I3(com_llm_llm_tx_top_tx_tlp_td[14]), + .LO(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_42164) + ); + defparam com_llm_llm_tx_top_llmx08_tx_packet_packer_current_td_0_i_m4_0_10_.INIT = 16'hDE12; + LUT4 com_llm_llm_tx_top_llmx08_tx_packet_packer_current_td_0_i_m4_0_10_ ( + .I0(N_10549), + .I1(com_llm_llm_tx_top_arb_state[2]), + .I2(com_llm_llm_tx_top_llmx08_tx_packet_packer_new_c32_1_2_5_), + .I3(com_llm_llm_tx_top_tx_tlp_td[10]), + .O(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_51489) + ); + defparam com_llm_llm_tx_top_llmx08_tx_packet_packer_current_td_0_i_m4_0_12_.INIT = 16'hDE12; + LUT4 com_llm_llm_tx_top_llmx08_tx_packet_packer_current_td_0_i_m4_0_12_ ( + .I0(N_10563), + .I1(com_llm_llm_tx_top_arb_state[2]), + .I2(com_llm_llm_tx_top_llmx08_tx_packet_packer_new_c32_1_3[3]), + .I3(com_llm_llm_tx_top_tx_tlp_td[12]), + .O(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_51491) + ); + defparam com_llm_llm_tx_top_llmx08_tx_packet_packer_arb_state_i_2_.INIT = 4'h1; + LUT1_L com_llm_llm_tx_top_llmx08_tx_packet_packer_arb_state_i_2_ ( + .I0(com_llm_llm_tx_top_arb_state[2]), + .LO(com_llm_llm_tx_top_llmx08_tx_packet_packer_arb_state_i[2]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_packet_packer_N_41842_i.INIT = 8'h72; + LUT3_L com_llm_llm_tx_top_llmx08_tx_packet_packer_N_41842_i ( + .I0(com_llm_llm_tx_top_llmx08_tx_packet_packer_aligned_1490), + .I1(com_llm_llm_tx_top_arb_state[2]), + .I2(phy_tctrl_l), + .LO(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_41842_i_1411) + ); + defparam com_llm_llm_tx_top_llmx08_tx_packet_packer_N_68888_i.INIT = 16'hA0B1; + LUT4_L com_llm_llm_tx_top_llmx08_tx_packet_packer_N_68888_i ( + .I0(com_llm_llm_tx_top_llmx08_tx_packet_packer_aligned_1490), + .I1(com_llm_llm_tx_top_llmx08_tx_packet_packer_trans_non_aligned_1413), + .I2(com_llm_llm_tx_top_rem_pipe[4]), + .I3(com_llm_llm_tx_top_tx_tlp_vld_l_n_i), + .LO(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_68888_i_1412) + ); + defparam com_llm_llm_tx_top_llmx08_tx_packet_packer_current_td_i_31_.INIT = 4'h2; + LUT2_L com_llm_llm_tx_top_llmx08_tx_packet_packer_current_td_i_31_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_41794), + .I1(com_llm_llm_tx_top_reg_tx_pp_idle), + .LO(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_40545_i) + ); + defparam com_llm_llm_tx_top_llmx08_tx_packet_packer_current_td_i_30_.INIT = 4'h2; + LUT2_L com_llm_llm_tx_top_llmx08_tx_packet_packer_current_td_i_30_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_41795), + .I1(com_llm_llm_tx_top_reg_tx_pp_idle), + .LO(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_40543_i) + ); + defparam com_llm_llm_tx_top_llmx08_tx_packet_packer_current_td_i_29_.INIT = 4'h2; + LUT2_L com_llm_llm_tx_top_llmx08_tx_packet_packer_current_td_i_29_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_41796), + .I1(com_llm_llm_tx_top_reg_tx_pp_idle), + .LO(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_40541_i) + ); + defparam com_llm_llm_tx_top_llmx08_tx_packet_packer_current_td_i_28_.INIT = 4'h2; + LUT2_L com_llm_llm_tx_top_llmx08_tx_packet_packer_current_td_i_28_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_41797), + .I1(com_llm_llm_tx_top_reg_tx_pp_idle), + .LO(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_40539_i) + ); + defparam com_llm_llm_tx_top_llmx08_tx_packet_packer_current_td_i_27_.INIT = 4'h2; + LUT2_L com_llm_llm_tx_top_llmx08_tx_packet_packer_current_td_i_27_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_41798), + .I1(com_llm_llm_tx_top_reg_tx_pp_idle), + .LO(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_40537_i) + ); + defparam com_llm_llm_tx_top_llmx08_tx_packet_packer_current_td_i_26_.INIT = 4'h2; + LUT2_L com_llm_llm_tx_top_llmx08_tx_packet_packer_current_td_i_26_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_41799), + .I1(com_llm_llm_tx_top_reg_tx_pp_idle), + .LO(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_40535_i) + ); + defparam com_llm_llm_tx_top_llmx08_tx_packet_packer_current_td_i_25_.INIT = 4'h2; + LUT2_L com_llm_llm_tx_top_llmx08_tx_packet_packer_current_td_i_25_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_41800), + .I1(com_llm_llm_tx_top_reg_tx_pp_idle), + .LO(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_40533_i) + ); + defparam com_llm_llm_tx_top_llmx08_tx_packet_packer_current_td_i_24_.INIT = 4'h2; + LUT2_L com_llm_llm_tx_top_llmx08_tx_packet_packer_current_td_i_24_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_41801), + .I1(com_llm_llm_tx_top_reg_tx_pp_idle), + .LO(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_40531_i) + ); + defparam com_llm_llm_tx_top_llmx08_tx_packet_packer_current_td_1_a2_23_.INIT = 4'h2; + LUT2_L com_llm_llm_tx_top_llmx08_tx_packet_packer_current_td_1_a2_23_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_51502), + .I1(com_llm_llm_tx_top_reg_tx_pp_idle), + .LO(com_llm_llm_tx_top_llmx08_tx_packet_packer_current_td[23]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_packet_packer_current_td_1_a2_22_.INIT = 4'h2; + LUT2_L com_llm_llm_tx_top_llmx08_tx_packet_packer_current_td_1_a2_22_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_51501), + .I1(com_llm_llm_tx_top_reg_tx_pp_idle), + .LO(com_llm_llm_tx_top_llmx08_tx_packet_packer_current_td[22]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_packet_packer_current_td_1_a2_21_.INIT = 4'h2; + LUT2_L com_llm_llm_tx_top_llmx08_tx_packet_packer_current_td_1_a2_21_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_51500), + .I1(com_llm_llm_tx_top_reg_tx_pp_idle), + .LO(com_llm_llm_tx_top_llmx08_tx_packet_packer_current_td[21]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_packet_packer_current_td_1_a2_20_.INIT = 4'h2; + LUT2_L com_llm_llm_tx_top_llmx08_tx_packet_packer_current_td_1_a2_20_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_51499), + .I1(com_llm_llm_tx_top_reg_tx_pp_idle), + .LO(com_llm_llm_tx_top_llmx08_tx_packet_packer_current_td[20]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_packet_packer_current_td_1_a2_19_.INIT = 16'h0E04; + LUT4_L com_llm_llm_tx_top_llmx08_tx_packet_packer_current_td_1_a2_19_ ( + .I0(com_llm_llm_tx_top_arb_state[2]), + .I1(com_llm_llm_tx_top_llmx08_tx_packet_packer_new_c32_1_i_12_), + .I2(com_llm_llm_tx_top_reg_tx_pp_idle), + .I3(com_llm_llm_tx_top_tx_tlp_td[19]), + .LO(com_llm_llm_tx_top_llmx08_tx_packet_packer_current_td[19]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_packet_packer_current_td_1_a2_18_.INIT = 16'h0E04; + LUT4_L com_llm_llm_tx_top_llmx08_tx_packet_packer_current_td_1_a2_18_ ( + .I0(com_llm_llm_tx_top_arb_state[2]), + .I1(com_llm_llm_tx_top_llmx08_tx_packet_packer_new_c32_1_i_13_), + .I2(com_llm_llm_tx_top_reg_tx_pp_idle), + .I3(com_llm_llm_tx_top_tx_tlp_td[18]), + .LO(com_llm_llm_tx_top_llmx08_tx_packet_packer_current_td[18]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_packet_packer_current_td_1_a2_17_.INIT = 4'h2; + LUT2_L com_llm_llm_tx_top_llmx08_tx_packet_packer_current_td_1_a2_17_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_51496), + .I1(com_llm_llm_tx_top_reg_tx_pp_idle), + .LO(com_llm_llm_tx_top_llmx08_tx_packet_packer_current_td[17]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_packet_packer_current_td_1_a2_16_.INIT = 4'h2; + LUT2_L com_llm_llm_tx_top_llmx08_tx_packet_packer_current_td_1_a2_16_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_51495), + .I1(com_llm_llm_tx_top_reg_tx_pp_idle), + .LO(com_llm_llm_tx_top_llmx08_tx_packet_packer_current_td[16]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_packet_packer_current_td_1_a2_15_.INIT = 16'h0E04; + LUT4_L com_llm_llm_tx_top_llmx08_tx_packet_packer_current_td_1_a2_15_ ( + .I0(com_llm_llm_tx_top_arb_state[2]), + .I1(com_llm_llm_tx_top_llmx08_tx_packet_packer_new_c32_1_i_0_), + .I2(com_llm_llm_tx_top_reg_tx_pp_idle), + .I3(com_llm_llm_tx_top_tx_tlp_td[15]), + .LO(com_llm_llm_tx_top_llmx08_tx_packet_packer_current_td[15]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_packet_packer_current_td_1_a2_14_.INIT = 16'h0B01; + LUT4_L com_llm_llm_tx_top_llmx08_tx_packet_packer_current_td_1_a2_14_ ( + .I0(com_llm_llm_tx_top_arb_state[2]), + .I1(com_llm_llm_tx_top_llmx08_tx_packet_packer_new_c32_1_), + .I2(com_llm_llm_tx_top_reg_tx_pp_idle), + .I3(com_llm_llm_tx_top_tx_tlp_td[14]), + .LO(com_llm_llm_tx_top_llmx08_tx_packet_packer_current_td[14]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_packet_packer_current_td_1_a2_13_.INIT = 4'h2; + LUT2_L com_llm_llm_tx_top_llmx08_tx_packet_packer_current_td_1_a2_13_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_51492), + .I1(com_llm_llm_tx_top_reg_tx_pp_idle), + .LO(com_llm_llm_tx_top_llmx08_tx_packet_packer_current_td[13]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_packet_packer_current_td_1_a2_12_.INIT = 4'h2; + LUT2_L com_llm_llm_tx_top_llmx08_tx_packet_packer_current_td_1_a2_12_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_51491), + .I1(com_llm_llm_tx_top_reg_tx_pp_idle), + .LO(com_llm_llm_tx_top_llmx08_tx_packet_packer_current_td[12]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_packet_packer_current_td_1_a2_11_.INIT = 4'h2; + LUT2_L com_llm_llm_tx_top_llmx08_tx_packet_packer_current_td_1_a2_11_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_51490), + .I1(com_llm_llm_tx_top_reg_tx_pp_idle), + .LO(com_llm_llm_tx_top_llmx08_tx_packet_packer_current_td[11]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_packet_packer_current_td_1_a2_10_.INIT = 4'h2; + LUT2_L com_llm_llm_tx_top_llmx08_tx_packet_packer_current_td_1_a2_10_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_51489), + .I1(com_llm_llm_tx_top_reg_tx_pp_idle), + .LO(com_llm_llm_tx_top_llmx08_tx_packet_packer_current_td[10]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_packet_packer_current_td_1_a2_9_.INIT = 4'h2; + LUT2_L com_llm_llm_tx_top_llmx08_tx_packet_packer_current_td_1_a2_9_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_51488), + .I1(com_llm_llm_tx_top_reg_tx_pp_idle), + .LO(com_llm_llm_tx_top_llmx08_tx_packet_packer_current_td[9]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_packet_packer_current_td_1_a2_8_.INIT = 4'h2; + LUT2_L com_llm_llm_tx_top_llmx08_tx_packet_packer_current_td_1_a2_8_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_51487), + .I1(com_llm_llm_tx_top_reg_tx_pp_idle), + .LO(com_llm_llm_tx_top_llmx08_tx_packet_packer_current_td[8]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_packet_packer_N_68930_i.INIT = 8'hEC; + LUT3_L com_llm_llm_tx_top_llmx08_tx_packet_packer_N_68930_i ( + .I0(com_llm_llm_tx_top_arb_state[2]), + .I1(com_llm_llm_tx_top_reg_tx_pp_idle), + .I2(com_llm_llm_tx_top_tx_tlp_td[7]), + .LO(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_68930_i_1414) + ); + defparam com_llm_llm_tx_top_llmx08_tx_packet_packer_N_68931_i.INIT = 8'hEC; + LUT3_L com_llm_llm_tx_top_llmx08_tx_packet_packer_N_68931_i ( + .I0(com_llm_llm_tx_top_arb_state[2]), + .I1(com_llm_llm_tx_top_reg_tx_pp_idle), + .I2(com_llm_llm_tx_top_tx_tlp_td[6]), + .LO(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_68931_i_1415) + ); + defparam com_llm_llm_tx_top_llmx08_tx_packet_packer_N_68932_i.INIT = 8'hEC; + LUT3_L com_llm_llm_tx_top_llmx08_tx_packet_packer_N_68932_i ( + .I0(com_llm_llm_tx_top_arb_state[2]), + .I1(com_llm_llm_tx_top_reg_tx_pp_idle), + .I2(com_llm_llm_tx_top_tx_tlp_td[5]), + .LO(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_68932_i_1416) + ); + defparam com_llm_llm_tx_top_llmx08_tx_packet_packer_N_68933_i.INIT = 8'hEC; + LUT3_L com_llm_llm_tx_top_llmx08_tx_packet_packer_N_68933_i ( + .I0(com_llm_llm_tx_top_arb_state[2]), + .I1(com_llm_llm_tx_top_reg_tx_pp_idle), + .I2(com_llm_llm_tx_top_tx_tlp_td[4]), + .LO(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_68933_i_1417) + ); + defparam com_llm_llm_tx_top_llmx08_tx_packet_packer_N_68934_i.INIT = 8'hEC; + LUT3_L com_llm_llm_tx_top_llmx08_tx_packet_packer_N_68934_i ( + .I0(com_llm_llm_tx_top_arb_state[2]), + .I1(com_llm_llm_tx_top_reg_tx_pp_idle), + .I2(com_llm_llm_tx_top_tx_tlp_td[3]), + .LO(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_68934_i_1418) + ); + defparam com_llm_llm_tx_top_llmx08_tx_packet_packer_N_68935_i.INIT = 8'hEC; + LUT3_L com_llm_llm_tx_top_llmx08_tx_packet_packer_N_68935_i ( + .I0(com_llm_llm_tx_top_arb_state[2]), + .I1(com_llm_llm_tx_top_reg_tx_pp_idle), + .I2(com_llm_llm_tx_top_tx_tlp_td[2]), + .LO(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_68935_i_1419) + ); + defparam com_llm_llm_tx_top_llmx08_tx_packet_packer_N_68936_i.INIT = 8'hEC; + LUT3_L com_llm_llm_tx_top_llmx08_tx_packet_packer_N_68936_i ( + .I0(com_llm_llm_tx_top_arb_state[2]), + .I1(com_llm_llm_tx_top_reg_tx_pp_idle), + .I2(com_llm_llm_tx_top_tx_tlp_td[1]), + .LO(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_68936_i_1420) + ); + defparam com_llm_llm_tx_top_llmx08_tx_packet_packer_N_68937_i.INIT = 8'hEC; + LUT3_L com_llm_llm_tx_top_llmx08_tx_packet_packer_N_68937_i ( + .I0(com_llm_llm_tx_top_arb_state[2]), + .I1(com_llm_llm_tx_top_reg_tx_pp_idle), + .I2(com_llm_llm_tx_top_tx_tlp_td[0]), + .LO(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_68937_i_1421) + ); + defparam com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_tframe_h_3_i.INIT = 8'hB4; + LUT3_L com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_tframe_h_3_i ( + .I0(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_41774_i), + .I1(com_llm_llm_tx_top_llmx08_tx_packet_packer_aligned_1490), + .I2(phy_tframe_h), + .LO(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_40388_i) + ); + defparam com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_tframe_l_3_i.INIT = 8'hE1; + LUT3_L com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_tframe_l_3_i ( + .I0(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_41774_i), + .I1(com_llm_llm_tx_top_llmx08_tx_packet_packer_aligned_1490), + .I2(phy_tframe_l), + .LO(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_40390_i) + ); + defparam com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_i_63_.INIT = 16'h1101; + LUT4_L com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_i_63_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_42298), + .I1(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_43100), + .I2(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_43102), + .I3(com_llm_llm_tx_top_llmx08_tx_packet_packer_prev_td[31]), + .LO(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_40486_i) + ); + defparam com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_i_62_.INIT = 16'h1101; + LUT4_L com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_i_62_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_42296), + .I1(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_43100), + .I2(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_43102), + .I3(com_llm_llm_tx_top_llmx08_tx_packet_packer_prev_td[30]), + .LO(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_40484_i) + ); + defparam com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_i_61_.INIT = 16'h1101; + LUT4_L com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_i_61_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_42294), + .I1(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_43100), + .I2(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_43102), + .I3(com_llm_llm_tx_top_llmx08_tx_packet_packer_prev_td[29]), + .LO(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_40482_i) + ); + defparam com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_i_60_.INIT = 16'h1101; + LUT4_L com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_i_60_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_42292), + .I1(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_43100), + .I2(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_43102), + .I3(com_llm_llm_tx_top_llmx08_tx_packet_packer_prev_td[28]), + .LO(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_40480_i) + ); + defparam com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_i_59_.INIT = 16'h1101; + LUT4_L com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_i_59_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_42290), + .I1(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_43100), + .I2(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_43102), + .I3(com_llm_llm_tx_top_llmx08_tx_packet_packer_prev_td[27]), + .LO(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_40478_i) + ); + defparam com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_i_58_.INIT = 16'h1101; + LUT4_L com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_i_58_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_42288), + .I1(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_43100), + .I2(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_43102), + .I3(com_llm_llm_tx_top_llmx08_tx_packet_packer_prev_td[26]), + .LO(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_40476_i) + ); + defparam com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_i_57_.INIT = 16'h1101; + LUT4_L com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_i_57_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_42286), + .I1(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_43100), + .I2(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_43102), + .I3(com_llm_llm_tx_top_llmx08_tx_packet_packer_prev_td[25]), + .LO(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_40474_i) + ); + defparam com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_i_56_.INIT = 16'h1101; + LUT4_L com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_i_56_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_42283), + .I1(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_43100), + .I2(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_43102), + .I3(com_llm_llm_tx_top_llmx08_tx_packet_packer_prev_td[24]), + .LO(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_40472_i) + ); + defparam com_llm_llm_tx_top_llmx08_tx_packet_packer_N_67992_i.INIT = 8'h73; + LUT3_L com_llm_llm_tx_top_llmx08_tx_packet_packer_N_67992_i ( + .I0(com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_0_o4[32]), + .I1(com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_0_0_55__1423), + .I2(com_llm_llm_tx_top_tx_tlp_td[55]), + .LO(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_67992_i_1422) + ); + defparam com_llm_llm_tx_top_llmx08_tx_packet_packer_N_67991_i.INIT = 8'h73; + LUT3_L com_llm_llm_tx_top_llmx08_tx_packet_packer_N_67991_i ( + .I0(com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_0_o4[32]), + .I1(com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_0_0_54__1425), + .I2(com_llm_llm_tx_top_tx_tlp_td[54]), + .LO(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_67991_i_1424) + ); + defparam com_llm_llm_tx_top_llmx08_tx_packet_packer_N_67951_i.INIT = 8'h73; + LUT3_L com_llm_llm_tx_top_llmx08_tx_packet_packer_N_67951_i ( + .I0(com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_0_o4[32]), + .I1(com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_0_0_53__1427), + .I2(com_llm_llm_tx_top_tx_tlp_td[53]), + .LO(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_67951_i_1426) + ); + defparam com_llm_llm_tx_top_llmx08_tx_packet_packer_N_67990_i.INIT = 8'h73; + LUT3_L com_llm_llm_tx_top_llmx08_tx_packet_packer_N_67990_i ( + .I0(com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_0_o4[32]), + .I1(com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_0_0_52__1429), + .I2(com_llm_llm_tx_top_tx_tlp_td[52]), + .LO(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_67990_i_1428) + ); + defparam com_llm_llm_tx_top_llmx08_tx_packet_packer_N_68236_i.INIT = 16'hB3A0; + LUT4_L com_llm_llm_tx_top_llmx08_tx_packet_packer_N_68236_i ( + .I0(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_43102), + .I1(com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_0_o4[32]), + .I2(com_llm_llm_tx_top_llmx08_tx_packet_packer_prev_td[19]), + .I3(com_llm_llm_tx_top_tx_tlp_td[51]), + .LO(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_68236_i_1430) + ); + defparam com_llm_llm_tx_top_llmx08_tx_packet_packer_N_68237_i.INIT = 16'hB3A0; + LUT4_L com_llm_llm_tx_top_llmx08_tx_packet_packer_N_68237_i ( + .I0(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_43102), + .I1(com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_0_o4[32]), + .I2(com_llm_llm_tx_top_llmx08_tx_packet_packer_prev_td[18]), + .I3(com_llm_llm_tx_top_tx_tlp_td[50]), + .LO(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_68237_i_1431) + ); + defparam com_llm_llm_tx_top_llmx08_tx_packet_packer_N_67989_i.INIT = 8'h73; + LUT3_L com_llm_llm_tx_top_llmx08_tx_packet_packer_N_67989_i ( + .I0(com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_0_o4[32]), + .I1(com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_0_0_49__1433), + .I2(com_llm_llm_tx_top_tx_tlp_td[49]), + .LO(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_67989_i_1432) + ); + defparam com_llm_llm_tx_top_llmx08_tx_packet_packer_N_67988_i.INIT = 8'h73; + LUT3_L com_llm_llm_tx_top_llmx08_tx_packet_packer_N_67988_i ( + .I0(com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_0_o4[32]), + .I1(com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_0_0_48__1435), + .I2(com_llm_llm_tx_top_tx_tlp_td[48]), + .LO(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_67988_i_1434) + ); + defparam com_llm_llm_tx_top_llmx08_tx_packet_packer_N_68238_i.INIT = 16'hB3A0; + LUT4_L com_llm_llm_tx_top_llmx08_tx_packet_packer_N_68238_i ( + .I0(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_43102), + .I1(com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_0_o4[32]), + .I2(com_llm_llm_tx_top_llmx08_tx_packet_packer_prev_td[15]), + .I3(com_llm_llm_tx_top_tx_tlp_td[47]), + .LO(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_68238_i_1436) + ); + defparam com_llm_llm_tx_top_llmx08_tx_packet_packer_N_68239_i.INIT = 16'hB3A0; + LUT4_L com_llm_llm_tx_top_llmx08_tx_packet_packer_N_68239_i ( + .I0(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_43102), + .I1(com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_0_o4[32]), + .I2(com_llm_llm_tx_top_llmx08_tx_packet_packer_prev_td[14]), + .I3(com_llm_llm_tx_top_tx_tlp_td[46]), + .LO(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_68239_i_1437) + ); + defparam com_llm_llm_tx_top_llmx08_tx_packet_packer_N_67987_i.INIT = 8'h73; + LUT3_L com_llm_llm_tx_top_llmx08_tx_packet_packer_N_67987_i ( + .I0(com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_0_o4[32]), + .I1(com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_0_0_45__1439), + .I2(com_llm_llm_tx_top_tx_tlp_td[45]), + .LO(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_67987_i_1438) + ); + defparam com_llm_llm_tx_top_llmx08_tx_packet_packer_N_67986_i.INIT = 8'h73; + LUT3_L com_llm_llm_tx_top_llmx08_tx_packet_packer_N_67986_i ( + .I0(com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_0_o4[32]), + .I1(com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_0_0_44__1441), + .I2(com_llm_llm_tx_top_tx_tlp_td[44]), + .LO(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_67986_i_1440) + ); + defparam com_llm_llm_tx_top_llmx08_tx_packet_packer_N_67985_i.INIT = 8'h73; + LUT3_L com_llm_llm_tx_top_llmx08_tx_packet_packer_N_67985_i ( + .I0(com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_0_o4[32]), + .I1(com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_0_0_43__1443), + .I2(com_llm_llm_tx_top_tx_tlp_td[43]), + .LO(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_67985_i_1442) + ); + defparam com_llm_llm_tx_top_llmx08_tx_packet_packer_N_67984_i.INIT = 8'h73; + LUT3_L com_llm_llm_tx_top_llmx08_tx_packet_packer_N_67984_i ( + .I0(com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_0_o4[32]), + .I1(com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_0_0_42__1445), + .I2(com_llm_llm_tx_top_tx_tlp_td[42]), + .LO(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_67984_i_1444) + ); + defparam com_llm_llm_tx_top_llmx08_tx_packet_packer_N_67983_i.INIT = 8'h73; + LUT3_L com_llm_llm_tx_top_llmx08_tx_packet_packer_N_67983_i ( + .I0(com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_0_o4[32]), + .I1(com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_0_0_41__1447), + .I2(com_llm_llm_tx_top_tx_tlp_td[41]), + .LO(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_67983_i_1446) + ); + defparam com_llm_llm_tx_top_llmx08_tx_packet_packer_N_67982_i.INIT = 8'h73; + LUT3_L com_llm_llm_tx_top_llmx08_tx_packet_packer_N_67982_i ( + .I0(com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_0_o4[32]), + .I1(com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_0_0_40__1449), + .I2(com_llm_llm_tx_top_tx_tlp_td[40]), + .LO(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_67982_i_1448) + ); + defparam com_llm_llm_tx_top_llmx08_tx_packet_packer_N_67981_i.INIT = 8'h73; + LUT3_L com_llm_llm_tx_top_llmx08_tx_packet_packer_N_67981_i ( + .I0(com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_0_o4[32]), + .I1(com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_0_0_39__1451), + .I2(com_llm_llm_tx_top_tx_tlp_td[39]), + .LO(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_67981_i_1450) + ); + defparam com_llm_llm_tx_top_llmx08_tx_packet_packer_N_67980_i.INIT = 8'h73; + LUT3_L com_llm_llm_tx_top_llmx08_tx_packet_packer_N_67980_i ( + .I0(com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_0_o4[32]), + .I1(com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_0_0_38__1453), + .I2(com_llm_llm_tx_top_tx_tlp_td[38]), + .LO(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_67980_i_1452) + ); + defparam com_llm_llm_tx_top_llmx08_tx_packet_packer_N_68240_i.INIT = 16'hB3A0; + LUT4_L com_llm_llm_tx_top_llmx08_tx_packet_packer_N_68240_i ( + .I0(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_43102), + .I1(com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_0_o4[32]), + .I2(com_llm_llm_tx_top_llmx08_tx_packet_packer_prev_td[5]), + .I3(com_llm_llm_tx_top_tx_tlp_td[37]), + .LO(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_68240_i_1454) + ); + defparam com_llm_llm_tx_top_llmx08_tx_packet_packer_N_68241_i.INIT = 16'hB3A0; + LUT4_L com_llm_llm_tx_top_llmx08_tx_packet_packer_N_68241_i ( + .I0(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_43102), + .I1(com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_0_o4[32]), + .I2(com_llm_llm_tx_top_llmx08_tx_packet_packer_prev_td[4]), + .I3(com_llm_llm_tx_top_tx_tlp_td[36]), + .LO(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_68241_i_1455) + ); + defparam com_llm_llm_tx_top_llmx08_tx_packet_packer_N_67979_i.INIT = 8'h73; + LUT3_L com_llm_llm_tx_top_llmx08_tx_packet_packer_N_67979_i ( + .I0(com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_0_o4[32]), + .I1(com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_0_0_35__1457), + .I2(com_llm_llm_tx_top_tx_tlp_td[35]), + .LO(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_67979_i_1456) + ); + defparam com_llm_llm_tx_top_llmx08_tx_packet_packer_N_67978_i.INIT = 8'h73; + LUT3_L com_llm_llm_tx_top_llmx08_tx_packet_packer_N_67978_i ( + .I0(com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_0_o4[32]), + .I1(com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_0_0_34__1459), + .I2(com_llm_llm_tx_top_tx_tlp_td[34]), + .LO(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_67978_i_1458) + ); + defparam com_llm_llm_tx_top_llmx08_tx_packet_packer_N_67952_i.INIT = 8'h73; + LUT3_L com_llm_llm_tx_top_llmx08_tx_packet_packer_N_67952_i ( + .I0(com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_0_o4[32]), + .I1(com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_0_0_33__1461), + .I2(com_llm_llm_tx_top_tx_tlp_td[33]), + .LO(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_67952_i_1460) + ); + defparam com_llm_llm_tx_top_llmx08_tx_packet_packer_N_67977_i.INIT = 8'h73; + LUT3_L com_llm_llm_tx_top_llmx08_tx_packet_packer_N_67977_i ( + .I0(com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_0_o4[32]), + .I1(com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_0_0_32__1463), + .I2(com_llm_llm_tx_top_tx_tlp_td[32]), + .LO(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_67977_i_1462) + ); + defparam com_llm_llm_tx_top_llmx08_tx_packet_packer_N_67976_i.INIT = 16'hFFEC; + LUT4_L com_llm_llm_tx_top_llmx08_tx_packet_packer_N_67976_i ( + .I0(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_41794), + .I1(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_42210), + .I2(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_43098), + .I3(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_43110), + .LO(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_67976_i_1464) + ); + defparam com_llm_llm_tx_top_llmx08_tx_packet_packer_N_67975_i.INIT = 16'hFFEC; + LUT4_L com_llm_llm_tx_top_llmx08_tx_packet_packer_N_67975_i ( + .I0(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_41795), + .I1(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_42208), + .I2(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_43098), + .I3(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_43110), + .LO(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_67975_i_1465) + ); + defparam com_llm_llm_tx_top_llmx08_tx_packet_packer_N_67974_i.INIT = 16'hFFEC; + LUT4_L com_llm_llm_tx_top_llmx08_tx_packet_packer_N_67974_i ( + .I0(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_41796), + .I1(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_42206), + .I2(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_43098), + .I3(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_43110), + .LO(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_67974_i_1466) + ); + defparam com_llm_llm_tx_top_llmx08_tx_packet_packer_N_67973_i.INIT = 16'hFFEC; + LUT4_L com_llm_llm_tx_top_llmx08_tx_packet_packer_N_67973_i ( + .I0(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_41797), + .I1(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_42204), + .I2(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_43098), + .I3(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_43110), + .LO(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_67973_i_1467) + ); + defparam com_llm_llm_tx_top_llmx08_tx_packet_packer_N_67972_i.INIT = 16'hFFEC; + LUT4_L com_llm_llm_tx_top_llmx08_tx_packet_packer_N_67972_i ( + .I0(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_41798), + .I1(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_42202), + .I2(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_43098), + .I3(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_43110), + .LO(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_67972_i_1468) + ); + defparam com_llm_llm_tx_top_llmx08_tx_packet_packer_N_67971_i.INIT = 16'hFFEC; + LUT4_L com_llm_llm_tx_top_llmx08_tx_packet_packer_N_67971_i ( + .I0(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_41799), + .I1(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_42200), + .I2(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_43098), + .I3(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_43110), + .LO(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_67971_i_1469) + ); + defparam com_llm_llm_tx_top_llmx08_tx_packet_packer_N_67970_i.INIT = 16'hFFEC; + LUT4_L com_llm_llm_tx_top_llmx08_tx_packet_packer_N_67970_i ( + .I0(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_41800), + .I1(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_42198), + .I2(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_43098), + .I3(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_43110), + .LO(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_67970_i_1470) + ); + defparam com_llm_llm_tx_top_llmx08_tx_packet_packer_N_67969_i.INIT = 16'hFFEC; + LUT4_L com_llm_llm_tx_top_llmx08_tx_packet_packer_N_67969_i ( + .I0(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_41801), + .I1(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_42196), + .I2(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_43098), + .I3(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_43110), + .LO(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_67969_i_1471) + ); + defparam com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_i_23_.INIT = 16'h008C; + LUT4_L com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_i_23_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_51502), + .I1(com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_i_23_32153_1472), + .I2(com_llm_llm_tx_top_llmx08_tx_packet_packer_aligned_1490), + .I3(com_llm_llm_tx_top_reg_tx_pp_idle), + .LO(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_40438_i) + ); + defparam com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_i_22_.INIT = 16'h008C; + LUT4_L com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_i_22_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_51501), + .I1(com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_i_22_32085_1473), + .I2(com_llm_llm_tx_top_llmx08_tx_packet_packer_aligned_1490), + .I3(com_llm_llm_tx_top_reg_tx_pp_idle), + .LO(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_40436_i) + ); + defparam com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_i_21_.INIT = 16'h008C; + LUT4_L com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_i_21_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_51500), + .I1(com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_i_21_32186_1474), + .I2(com_llm_llm_tx_top_llmx08_tx_packet_packer_aligned_1490), + .I3(com_llm_llm_tx_top_reg_tx_pp_idle), + .LO(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_40434_i) + ); + defparam com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_i_20_.INIT = 16'h008C; + LUT4_L com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_i_20_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_51499), + .I1(com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_i_20_32154_1475), + .I2(com_llm_llm_tx_top_llmx08_tx_packet_packer_aligned_1490), + .I3(com_llm_llm_tx_top_reg_tx_pp_idle), + .LO(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_40432_i) + ); + defparam com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_i_19_.INIT = 16'h5010; + LUT4_L com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_i_19_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_42179), + .I1(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_43103), + .I2(com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_i_0_i[15]), + .I3(com_llm_llm_tx_top_tx_tlp_td[51]), + .LO(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_40430_i) + ); + defparam com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_i_18_.INIT = 16'h5010; + LUT4_L com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_i_18_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_42176), + .I1(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_43103), + .I2(com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_i_0_i[15]), + .I3(com_llm_llm_tx_top_tx_tlp_td[50]), + .LO(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_40428_i) + ); + defparam com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_i_17_.INIT = 16'h008C; + LUT4_L com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_i_17_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_51496), + .I1(com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_i_17_32187_1476), + .I2(com_llm_llm_tx_top_llmx08_tx_packet_packer_aligned_1490), + .I3(com_llm_llm_tx_top_reg_tx_pp_idle), + .LO(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_40426_i) + ); + defparam com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_i_16_.INIT = 16'h008C; + LUT4_L com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_i_16_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_51495), + .I1(com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_i_16_32150_1477), + .I2(com_llm_llm_tx_top_llmx08_tx_packet_packer_aligned_1490), + .I3(com_llm_llm_tx_top_reg_tx_pp_idle), + .LO(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_40424_i) + ); + defparam com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_i_15_.INIT = 16'h5010; + LUT4_L com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_i_15_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_42167), + .I1(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_43103), + .I2(com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_i_0_i[15]), + .I3(com_llm_llm_tx_top_tx_tlp_td[47]), + .LO(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_40422_i) + ); + defparam com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_i_14_.INIT = 16'h5010; + LUT4_L com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_i_14_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_42164), + .I1(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_43103), + .I2(com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_i_0_i[15]), + .I3(com_llm_llm_tx_top_tx_tlp_td[46]), + .LO(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_40420_i) + ); + defparam com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_i_13_.INIT = 16'h008C; + LUT4_L com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_i_13_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_51492), + .I1(com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_i_13_32151_1478), + .I2(com_llm_llm_tx_top_llmx08_tx_packet_packer_aligned_1490), + .I3(com_llm_llm_tx_top_reg_tx_pp_idle), + .LO(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_40418_i) + ); + defparam com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_i_12_.INIT = 16'h008C; + LUT4_L com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_i_12_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_51491), + .I1(com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_i_12_32081_1479), + .I2(com_llm_llm_tx_top_llmx08_tx_packet_packer_aligned_1490), + .I3(com_llm_llm_tx_top_reg_tx_pp_idle), + .LO(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_40416_i) + ); + defparam com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_i_11_.INIT = 16'h008C; + LUT4_L com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_i_11_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_51490), + .I1(com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_i_11_32082_1480), + .I2(com_llm_llm_tx_top_llmx08_tx_packet_packer_aligned_1490), + .I3(com_llm_llm_tx_top_reg_tx_pp_idle), + .LO(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_40414_i) + ); + defparam com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_i_10_.INIT = 16'h008C; + LUT4_L com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_i_10_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_51489), + .I1(com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_i_10_32083_1481), + .I2(com_llm_llm_tx_top_llmx08_tx_packet_packer_aligned_1490), + .I3(com_llm_llm_tx_top_reg_tx_pp_idle), + .LO(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_40412_i) + ); + defparam com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_i_9_.INIT = 16'h008C; + LUT4_L com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_i_9_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_51488), + .I1(com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_i_9_32152_1482), + .I2(com_llm_llm_tx_top_llmx08_tx_packet_packer_aligned_1490), + .I3(com_llm_llm_tx_top_reg_tx_pp_idle), + .LO(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_40410_i) + ); + defparam com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_i_8_.INIT = 16'h008C; + LUT4_L com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_i_8_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_51487), + .I1(com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_i_8_32084_1483), + .I2(com_llm_llm_tx_top_llmx08_tx_packet_packer_aligned_1490), + .I3(com_llm_llm_tx_top_reg_tx_pp_idle), + .LO(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_40408_i) + ); + defparam com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_i_7_.INIT = 16'hA020; + LUT4_L com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_i_7_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_41737_i), + .I1(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_43103), + .I2(com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_i_0[7]), + .I3(com_llm_llm_tx_top_tx_tlp_td[39]), + .LO(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_40406_i) + ); + defparam com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_i_6_.INIT = 16'hA020; + LUT4_L com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_i_6_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_41737_i), + .I1(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_43103), + .I2(com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_i_0[6]), + .I3(com_llm_llm_tx_top_tx_tlp_td[38]), + .LO(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_40404_i) + ); + defparam com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_i_5_.INIT = 8'h20; + LUT3_L com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_i_5_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_41737_i), + .I1(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_43106), + .I2(com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_i_0[5]), + .LO(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_40402_i) + ); + defparam com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_i_4_.INIT = 8'h20; + LUT3_L com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_i_4_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_41737_i), + .I1(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_43106), + .I2(com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_i_0[4]), + .LO(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_40400_i) + ); + defparam com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_i_3_.INIT = 16'hA020; + LUT4_L com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_i_3_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_41737_i), + .I1(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_43103), + .I2(com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_i_0[3]), + .I3(com_llm_llm_tx_top_tx_tlp_td[35]), + .LO(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_40398_i) + ); + defparam com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_i_2_.INIT = 16'hA020; + LUT4_L com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_i_2_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_41737_i), + .I1(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_43103), + .I2(com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_i_0[2]), + .I3(com_llm_llm_tx_top_tx_tlp_td[34]), + .LO(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_40396_i) + ); + defparam com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_i_1_.INIT = 16'hA020; + LUT4_L com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_i_1_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_41737_i), + .I1(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_43103), + .I2(com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_i_0[1]), + .I3(com_llm_llm_tx_top_tx_tlp_td[33]), + .LO(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_40394_i) + ); + defparam com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_i_0_.INIT = 16'hA020; + LUT4_L com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_i_0_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_41737_i), + .I1(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_43103), + .I2(com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_i_0[0]), + .I3(com_llm_llm_tx_top_tx_tlp_td[32]), + .LO(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_40392_i) + ); + defparam com_llm_llm_tx_top_llmx08_tx_packet_packer_next_arb_state_i_i_2_.INIT = 16'hC040; + LUT4_L com_llm_llm_tx_top_llmx08_tx_packet_packer_next_arb_state_i_i_2_ ( + .I0(com_llm_llm_tx_top_N_41766_i), + .I1(com_llm_llm_tx_top_llmx08_tx_packet_packer_next_arb_state_i_i_2_32138_1485), + .I2(com_llm_llm_tx_top_llmx08_tx_packet_packer_next_arb_state_i_i_2_32140_1484), + .I3(com_llm_llm_tx_top_arb_state[2]), + .LO(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_17347_i) + ); + defparam com_llm_llm_tx_top_llmx08_tx_packet_packer_next_arb_state_i_i_0_1_.INIT = 16'h0040; + LUT4_L com_llm_llm_tx_top_llmx08_tx_packet_packer_next_arb_state_i_i_0_1_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_42598), + .I1(com_llm_llm_tx_top_llmx08_tx_packet_packer_next_arb_state_i_i_0_1_32157_1488), + .I2(com_llm_llm_tx_top_llmx08_tx_packet_packer_next_arb_state_i_i_0_1_32161_1487), + .I3(com_llm_llm_tx_top_llmx08_tx_packet_packer_tx_idle_next_1486), + .LO(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_17349_i) + ); + defparam com_llm_llm_tx_top_llmx08_tx_packet_packer_N_68078_i.INIT = 16'h2F0F; + LUT4_L com_llm_llm_tx_top_llmx08_tx_packet_packer_N_68078_i ( + .I0(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_17399_3), + .I1(com_llm_llm_tx_top_llmx08_tx_packet_packer_next_arb_state_0_i_o3_0[0]), + .I2(com_llm_llm_tx_top_llmx08_tx_packet_packer_next_arb_state_0_i_1[0]), + .I3(com_llm_llm_tx_top_tx_tlp_sof_pre_n), + .LO(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_68078_i_1489) + ); + defparam com_llm_llm_tx_top_llmx08_tx_packet_packer_current_td_0_i_m4_0_1_22_.INIT = 16'h6996; + LUT4_L com_llm_llm_tx_top_llmx08_tx_packet_packer_current_td_0_i_m4_0_1_22_ ( + .I0(N_196), + .I1(N_207), + .I2(N_10432_1), + .I3(com_llm_llm_tx_top_tx_dllp_td_25_), + .LO(com_llm_llm_tx_top_llmx08_tx_packet_packer_current_td_0_i_m4_0_1[22]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_packet_packer_current_td_0_i_m4_0_22_.INIT = 16'hBE14; + LUT4 com_llm_llm_tx_top_llmx08_tx_packet_packer_current_td_0_i_m4_0_22_ ( + .I0(com_llm_llm_tx_top_arb_state[2]), + .I1(com_llm_llm_tx_top_llmx08_tx_packet_packer_current_td_0_i_m4_0_1[22]), + .I2(com_llm_llm_tx_top_llmx08_tx_packet_packer_new_c32_1_1_9_), + .I3(com_llm_llm_tx_top_tx_tlp_td[22]), + .O(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_51501) + ); + defparam com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_0_a3_0_32_.INIT = 8'h10; + LUT3 com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_0_a3_0_32_ ( + .I0(com_llm_llm_tx_top_arb_state[2]), + .I1(com_llm_llm_tx_top_reg_tx_pp_idle), + .I2(com_llm_llm_tx_top_llmx08_tx_packet_packer_aligned_1490), + .O(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_43100) + ); + defparam com_llm_llm_tx_top_llmx08_tx_packet_packer_llm_rx_crc16_d32_new_c32_1_0_10_.INIT = 4'h6; + LUT2 com_llm_llm_tx_top_llmx08_tx_packet_packer_llm_rx_crc16_d32_new_c32_1_0_10_ ( + .I0(com_llm_llm_tx_top_tx_dllp_td_42_), + .I1(com_llm_llm_tx_top_tx_dllp_td_55_), + .O(G_421_1_1) + ); + defparam com_llm_llm_tx_top_llmx08_tx_packet_packer_llm_rx_crc16_d32_new_c32_1_1_12_.INIT = 8'h96; + LUT3 com_llm_llm_tx_top_llmx08_tx_packet_packer_llm_rx_crc16_d32_new_c32_1_1_12_ ( + .I0(com_llm_llm_tx_top_tx_dllp_td_38_), + .I1(com_llm_llm_tx_top_tx_dllp_td_41_), + .I2(com_llm_llm_tx_top_tx_dllp_td_55_), + .O(com_llm_llm_tx_top_llmx08_tx_packet_packer_llm_rx_crc16_d32_new_c32_1_i_1[12]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_packet_packer_llm_rx_crc16_d32_new_c32_1_1_0_.INIT = 8'h96; + LUT3 com_llm_llm_tx_top_llmx08_tx_packet_packer_llm_rx_crc16_d32_new_c32_1_1_0_ ( + .I0(com_llm_llm_tx_top_tx_dllp_td_32_), + .I1(com_llm_llm_tx_top_tx_dllp_td_34_), + .I2(com_llm_llm_tx_top_tx_dllp_td_39_), + .O(com_llm_llm_tx_top_llmx08_tx_packet_packer_llm_rx_crc16_d32_new_c32_1_1_0__1492) + ); + defparam com_llm_llm_tx_top_llmx08_tx_packet_packer_llm_rx_crc16_d32_new_c32_1_0_13_.INIT = 8'h96; + LUT3 com_llm_llm_tx_top_llmx08_tx_packet_packer_llm_rx_crc16_d32_new_c32_1_0_13_ ( + .I0(com_llm_llm_tx_top_tx_dllp_td_26_), + .I1(com_llm_llm_tx_top_tx_dllp_td_45_), + .I2(com_llm_llm_tx_top_tx_dllp_td_53_), + .O(com_llm_llm_tx_top_llmx08_tx_packet_packer_llm_rx_crc16_d32_new_c32_1_0_13__1493) + ); + defparam com_llm_llm_tx_top_llmx08_tx_packet_packer_llm_rx_crc16_d32_new_c32_1_0_9_.INIT = 16'h6996; + LUT4_L com_llm_llm_tx_top_llmx08_tx_packet_packer_llm_rx_crc16_d32_new_c32_1_0_9_ ( + .I0(com_llm_llm_tx_top_tx_dllp_td_38_), + .I1(com_llm_llm_tx_top_tx_dllp_td_39_), + .I2(com_llm_llm_tx_top_tx_dllp_td_41_), + .I3(com_llm_llm_tx_top_tx_dllp_td_49_), + .LO(com_llm_llm_tx_top_llmx08_tx_packet_packer_llm_rx_crc16_d32_new_c32_1_0_9__1491) + ); + defparam com_llm_llm_tx_top_llmx08_tx_packet_packer_llm_rx_crc16_d32_new_c32_1_1_8_.INIT = 16'h6996; + LUT4 com_llm_llm_tx_top_llmx08_tx_packet_packer_llm_rx_crc16_d32_new_c32_1_1_8_ ( + .I0(com_llm_llm_tx_top_tx_dllp_td_26_), + .I1(com_llm_llm_tx_top_tx_dllp_td_39_), + .I2(com_llm_llm_tx_top_tx_dllp_td_41_), + .I3(com_llm_llm_tx_top_tx_dllp_td_49_), + .O(com_llm_llm_tx_top_llmx08_tx_packet_packer_llm_rx_crc16_d32_new_c32_1_1_8__1494) + ); + defparam com_llm_llm_tx_top_llmx08_tx_packet_packer_llm_rx_crc16_d32_new_c32_1_1_3_.INIT = 8'h96; + LUT3 com_llm_llm_tx_top_llmx08_tx_packet_packer_llm_rx_crc16_d32_new_c32_1_1_3_ ( + .I0(com_llm_llm_tx_top_tx_dllp_td_29_), + .I1(com_llm_llm_tx_top_tx_dllp_td_31_), + .I2(com_llm_llm_tx_top_tx_dllp_td_49_), + .O(com_llm_llm_tx_top_llmx08_tx_packet_packer_llm_rx_crc16_d32_new_c32_1_1_3__1496) + ); + defparam com_llm_llm_tx_top_llmx08_tx_packet_packer_llm_rx_crc16_d32_new_c32_1_0_11_.INIT = 4'h6; + LUT2 com_llm_llm_tx_top_llmx08_tx_packet_packer_llm_rx_crc16_d32_new_c32_1_0_11_ ( + .I0(N_196), + .I1(N_252), + .O(com_llm_llm_tx_top_llmx08_tx_packet_packer_llm_rx_crc16_d32_new_c32_1_0_11__1495) + ); + defparam com_llm_llm_tx_top_llmx08_tx_packet_packer_llm_rx_crc16_d32_new_c32_1_1_9_.INIT = 16'h6996; + LUT4 com_llm_llm_tx_top_llmx08_tx_packet_packer_llm_rx_crc16_d32_new_c32_1_1_9_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_packet_packer_llm_rx_crc16_d32_new_c32_1_0_9__1491), + .I1(com_llm_llm_tx_top_tx_dllp_td_34_), + .I2(com_llm_llm_tx_top_tx_dllp_td_52_), + .I3(com_llm_llm_tx_top_tx_dllp_td_55_), + .O(com_llm_llm_tx_top_llmx08_tx_packet_packer_new_c32_1_1_9_) + ); + defparam com_llm_llm_tx_top_llmx08_tx_packet_packer_llm_rx_crc16_d32_new_c32_1_2_15_.INIT = 16'h6996; + LUT4 com_llm_llm_tx_top_llmx08_tx_packet_packer_llm_rx_crc16_d32_new_c32_1_2_15_ ( + .I0(N_10420), + .I1(com_llm_llm_tx_top_tx_dllp_td_28_), + .I2(com_llm_llm_tx_top_tx_dllp_td_35_), + .I3(com_llm_llm_tx_top_tx_dllp_td_43_), + .O(com_llm_llm_tx_top_llmx08_tx_packet_packer_new_c32_1_2_15_) + ); + defparam com_llm_llm_tx_top_llmx08_tx_packet_packer_llm_rx_crc16_d32_new_c32_1_1_2_.INIT = 16'h6996; + LUT4 com_llm_llm_tx_top_llmx08_tx_packet_packer_llm_rx_crc16_d32_new_c32_1_1_2_ ( + .I0(N_10415), + .I1(com_llm_llm_tx_top_tx_dllp_td_38_), + .I2(com_llm_llm_tx_top_tx_dllp_td_42_), + .I3(com_llm_llm_tx_top_tx_dllp_td_54_), + .O(com_llm_llm_tx_top_llmx08_tx_packet_packer_new_c32_1_1_2_) + ); + defparam com_llm_llm_tx_top_llmx08_tx_packet_packer_llm_rx_crc16_d32_new_c32_1_0_.INIT = 16'h6996; + LUT4 com_llm_llm_tx_top_llmx08_tx_packet_packer_llm_rx_crc16_d32_new_c32_1_0_ ( + .I0(N_196), + .I1(N_258), + .I2(N_10457_1), + .I3(com_llm_llm_tx_top_llmx08_tx_packet_packer_llm_rx_crc16_d32_new_c32_1_1_0__1492), + .O(com_llm_llm_tx_top_llmx08_tx_packet_packer_new_c32_1_i_0_) + ); + defparam com_llm_llm_tx_top_llmx08_tx_packet_packer_llm_rx_crc16_d32_new_c32_1_13_.INIT = 16'h6996; + LUT4 com_llm_llm_tx_top_llmx08_tx_packet_packer_llm_rx_crc16_d32_new_c32_1_13_ ( + .I0(N_10601), + .I1(com_llm_llm_tx_top_llmx08_tx_packet_packer_llm_rx_crc16_d32_new_c32_1_0_13__1493), + .I2(com_llm_llm_tx_top_tx_dllp_td_38_), + .I3(com_llm_llm_tx_top_tx_dllp_td_54_), + .O(com_llm_llm_tx_top_llmx08_tx_packet_packer_new_c32_1_i_13_) + ); + defparam com_llm_llm_tx_top_llmx08_tx_packet_packer_llm_rx_crc16_d32_new_c32_1_12_.INIT = 8'h96; + LUT3 com_llm_llm_tx_top_llmx08_tx_packet_packer_llm_rx_crc16_d32_new_c32_1_12_ ( + .I0(N_174), + .I1(N_10457), + .I2(com_llm_llm_tx_top_llmx08_tx_packet_packer_llm_rx_crc16_d32_new_c32_1_i_1[12]), + .O(com_llm_llm_tx_top_llmx08_tx_packet_packer_new_c32_1_i_12_) + ); + defparam com_llm_llm_tx_top_llmx08_tx_packet_packer_llm_rx_crc16_d32_new_c32_1_1_7_.INIT = 16'h6996; + LUT4 com_llm_llm_tx_top_llmx08_tx_packet_packer_llm_rx_crc16_d32_new_c32_1_1_7_ ( + .I0(N_10404), + .I1(N_10432_1), + .I2(com_llm_llm_tx_top_tx_dllp_td_25_), + .I3(com_llm_llm_tx_top_tx_dllp_td_39_), + .O(com_llm_llm_tx_top_llmx08_tx_packet_packer_new_c32_1_1_7_) + ); + defparam com_llm_llm_tx_top_llmx08_tx_packet_packer_llm_rx_crc16_d32_new_c32_1_2_7_.INIT = 4'h6; + LUT2_L com_llm_llm_tx_top_llmx08_tx_packet_packer_llm_rx_crc16_d32_new_c32_1_2_7_ ( + .I0(N_10563_1), + .I1(N_10594), + .LO(com_llm_llm_tx_top_llmx08_tx_packet_packer_new_c32_1_2_7_) + ); + defparam com_llm_llm_tx_top_llmx08_tx_packet_packer_llm_rx_crc16_d32_new_c32_1_2_1_.INIT = 16'h6996; + LUT4_L com_llm_llm_tx_top_llmx08_tx_packet_packer_llm_rx_crc16_d32_new_c32_1_2_1_ ( + .I0(N_252), + .I1(N_10402), + .I2(N_10457), + .I3(com_llm_llm_tx_top_tx_dllp_td_52_), + .LO(com_llm_llm_tx_top_llmx08_tx_packet_packer_llm_rx_crc16_d32_new_c32_1_2[1]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_packet_packer_llm_rx_crc16_d32_new_c32_1_1_6_.INIT = 8'h96; + LUT3 com_llm_llm_tx_top_llmx08_tx_packet_packer_llm_rx_crc16_d32_new_c32_1_1_6_ ( + .I0(N_10402), + .I1(N_10522_1), + .I2(com_llm_llm_tx_top_tx_dllp_td_28_), + .O(com_llm_llm_tx_top_llmx08_tx_packet_packer_new_c32_1_1_6_) + ); + defparam com_llm_llm_tx_top_llmx08_tx_packet_packer_llm_rx_crc16_d32_new_c32_1_2_4_.INIT = 16'h6996; + LUT4 com_llm_llm_tx_top_llmx08_tx_packet_packer_llm_rx_crc16_d32_new_c32_1_2_4_ ( + .I0(N_207), + .I1(N_10415), + .I2(com_llm_llm_tx_top_llmx08_tx_packet_packer_llm_rx_crc16_d32_new_c32_1_i_1[12]), + .I3(com_llm_llm_tx_top_tx_dllp_td_26_), + .O(com_llm_llm_tx_top_llmx08_tx_packet_packer_new_c32_1_2_4_) + ); + defparam com_llm_llm_tx_top_llmx08_tx_packet_packer_llm_rx_crc16_d32_new_c32_1_1_.INIT = 4'h6; + LUT2 com_llm_llm_tx_top_llmx08_tx_packet_packer_llm_rx_crc16_d32_new_c32_1_1_ ( + .I0(N_10601), + .I1(com_llm_llm_tx_top_llmx08_tx_packet_packer_llm_rx_crc16_d32_new_c32_1_2[1]), + .O(com_llm_llm_tx_top_llmx08_tx_packet_packer_new_c32_1_) + ); + defparam com_llm_llm_tx_top_llmx08_tx_packet_packer_llm_rx_crc16_d32_new_c32_1_8_.INIT = 16'h6996; + LUT4_L com_llm_llm_tx_top_llmx08_tx_packet_packer_llm_rx_crc16_d32_new_c32_1_8_ ( + .I0(N_258), + .I1(N_10522_1), + .I2(N_10522_2), + .I3(com_llm_llm_tx_top_llmx08_tx_packet_packer_llm_rx_crc16_d32_new_c32_1_1_8__1494), + .LO(com_llm_llm_tx_top_llmx08_tx_packet_packer_new_c32_8_) + ); + defparam com_llm_llm_tx_top_llmx08_tx_packet_packer_llm_rx_crc16_d32_new_c32_1_11_.INIT = 16'h6996; + LUT4_L com_llm_llm_tx_top_llmx08_tx_packet_packer_llm_rx_crc16_d32_new_c32_1_11_ ( + .I0(N_207), + .I1(N_10388), + .I2(com_llm_llm_tx_top_llmx08_tx_packet_packer_llm_rx_crc16_d32_new_c32_1_0_11__1495), + .I3(com_llm_llm_tx_top_tx_dllp_td_49_), + .LO(com_llm_llm_tx_top_llmx08_tx_packet_packer_new_c32_11_) + ); + defparam com_llm_llm_tx_top_llmx08_tx_packet_packer_llm_rx_crc16_d32_new_c32_1_10_.INIT = 16'h6996; + LUT4_L com_llm_llm_tx_top_llmx08_tx_packet_packer_llm_rx_crc16_d32_new_c32_1_10_ ( + .I0(G_421_1_1), + .I1(N_10420), + .I2(N_10522_1), + .I3(N_10522_2), + .LO(com_llm_llm_tx_top_llmx08_tx_packet_packer_new_c32_10_) + ); + defparam com_llm_llm_tx_top_llmx08_tx_packet_packer_llm_rx_crc16_d32_new_c32_1_14_.INIT = 16'h6996; + LUT4_L com_llm_llm_tx_top_llmx08_tx_packet_packer_llm_rx_crc16_d32_new_c32_1_14_ ( + .I0(N_207), + .I1(N_10549_1), + .I2(com_llm_llm_tx_top_tx_dllp_td_25_), + .I3(com_llm_llm_tx_top_tx_dllp_td_49_), + .LO(com_llm_llm_tx_top_llmx08_tx_packet_packer_new_c32_14_) + ); + defparam com_llm_llm_tx_top_llmx08_tx_packet_packer_llm_rx_crc16_d32_new_c32_1_2_5_.INIT = 16'h6996; + LUT4_L com_llm_llm_tx_top_llmx08_tx_packet_packer_llm_rx_crc16_d32_new_c32_1_2_5_ ( + .I0(N_10388), + .I1(N_10404), + .I2(N_10522_2), + .I3(com_llm_llm_tx_top_tx_dllp_td_44_), + .LO(com_llm_llm_tx_top_llmx08_tx_packet_packer_new_c32_1_2_5_) + ); + defparam com_llm_llm_tx_top_llmx08_tx_packet_packer_llm_rx_crc16_d32_new_c32_1_3_3_.INIT = 16'h6996; + LUT4_L com_llm_llm_tx_top_llmx08_tx_packet_packer_llm_rx_crc16_d32_new_c32_1_3_3_ ( + .I0(N_10532), + .I1(com_llm_llm_tx_top_llmx08_tx_packet_packer_llm_rx_crc16_d32_new_c32_1_1_3__1496), + .I2(com_llm_llm_tx_top_tx_dllp_td_41_), + .I3(com_llm_llm_tx_top_tx_dllp_td_48_), + .LO(com_llm_llm_tx_top_llmx08_tx_packet_packer_new_c32_1_3[3]) + ); + FDS com_llm_llm_rx_top_llm_rx_demux_tlp_eof_n_qq ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_demux_N_67762_i_1545), + .Q(com_llm_llm_rx_top_rx_tlp_eof_n), + .S(plm_link_up_i) + ); + defparam com_llm_llm_rx_top_llm_rx_demux_phy_frame_l_t.INIT = 4'h6; + LUT2 com_llm_llm_rx_top_llm_rx_demux_phy_frame_l_t ( + .I0(com_llm_llm_rx_top_llm_rx_demux_phy_frame_l_q_1513), + .I1(phy_rframe_l), + .O(com_llm_llm_rx_top_llm_rx_demux_phy_frame_l_t_1511) + ); + defparam com_llm_llm_rx_top_llm_rx_demux_phy_frame_h_t.INIT = 4'h6; + LUT2 com_llm_llm_rx_top_llm_rx_demux_phy_frame_h_t ( + .I0(com_llm_llm_rx_top_llm_rx_demux_phy_frame_h_q_1514), + .I1(phy_rframe_h), + .O(com_llm_llm_rx_top_llm_rx_demux_phy_frame_h_t_1512) + ); + defparam com_llm_llm_rx_top_llm_rx_demux_tlp_ferr_n_q_9_u_i_o3.INIT = 4'h1; + LUT2 com_llm_llm_rx_top_llm_rx_demux_tlp_ferr_n_q_9_u_i_o3 ( + .I0(phy_rctrl_h), + .I1(phy_rferr_h_n), + .O(com_llm_llm_rx_top_llm_rx_demux_N_12822_i) + ); + defparam com_llm_llm_rx_top_llm_rx_demux_dllp_vld_h_n_q_11_iv_i_a3_2.INIT = 4'h8; + LUT2 com_llm_llm_rx_top_llm_rx_demux_dllp_vld_h_n_q_11_iv_i_a3_2 ( + .I0(phy_rctrl_l), + .I1(phy_rferr_l_n), + .O(com_llm_llm_rx_top_llm_rx_demux_N_12873_2) + ); + defparam com_llm_llm_rx_top_llm_rx_demux_tlp_ferr_n_q_9_u_i_a2.INIT = 8'h54; + LUT3 com_llm_llm_rx_top_llm_rx_demux_tlp_ferr_n_q_9_u_i_a2 ( + .I0(com_llm_llm_rx_top_llm_rx_demux_N_12822_i), + .I1(phy_rctrl_l), + .I2(phy_rferr_l_n), + .O(com_llm_llm_rx_top_llm_rx_demux_tlp_ferr_n_q_9_u_i_a2_1507) + ); + defparam com_llm_llm_rx_top_llm_rx_demux_un4_idle_on_low_n_4.INIT = 16'h8000; + LUT4 com_llm_llm_rx_top_llm_rx_demux_un4_idle_on_low_n_4 ( + .I0(phy_rd[24]), + .I1(phy_rd[25]), + .I2(phy_rd[26]), + .I3(phy_rd[27]), + .O(com_llm_llm_rx_top_llm_rx_demux_un4_idle_on_low_n_4_1498) + ); + defparam com_llm_llm_rx_top_llm_rx_demux_un4_idle_on_low_n_5.INIT = 16'h8000; + LUT4 com_llm_llm_rx_top_llm_rx_demux_un4_idle_on_low_n_5 ( + .I0(phy_rd[28]), + .I1(phy_rd[29]), + .I2(phy_rd[30]), + .I3(phy_rd[31]), + .O(com_llm_llm_rx_top_llm_rx_demux_un4_idle_on_low_n_5_1497) + ); + defparam com_llm_llm_rx_top_llm_rx_demux_un4_idle_on_high_n_4.INIT = 16'h8000; + LUT4 com_llm_llm_rx_top_llm_rx_demux_un4_idle_on_high_n_4 ( + .I0(phy_rd[32]), + .I1(phy_rd[33]), + .I2(phy_rd[34]), + .I3(phy_rd[35]), + .O(com_llm_llm_rx_top_llm_rx_demux_un4_idle_on_high_n_4_1504) + ); + defparam com_llm_llm_rx_top_llm_rx_demux_un4_idle_on_high_n_5.INIT = 16'h8000; + LUT4 com_llm_llm_rx_top_llm_rx_demux_un4_idle_on_high_n_5 ( + .I0(phy_rd[36]), + .I1(phy_rd[37]), + .I2(phy_rd[38]), + .I3(phy_rd[39]), + .O(com_llm_llm_rx_top_llm_rx_demux_un4_idle_on_high_n_5_1503) + ); + defparam com_llm_llm_rx_top_llm_rx_demux_un10_idle_a_n_4.INIT = 16'h8000; + LUT4 com_llm_llm_rx_top_llm_rx_demux_un10_idle_a_n_4 ( + .I0(phy_rd[0]), + .I1(phy_rd[1]), + .I2(phy_rd[2]), + .I3(phy_rd[3]), + .O(com_llm_llm_rx_top_llm_rx_demux_un10_idle_a_n_4_1500) + ); + defparam com_llm_llm_rx_top_llm_rx_demux_un10_idle_a_n_5.INIT = 16'h8000; + LUT4 com_llm_llm_rx_top_llm_rx_demux_un10_idle_a_n_5 ( + .I0(phy_rd[4]), + .I1(phy_rd[5]), + .I2(phy_rd[6]), + .I3(phy_rd[7]), + .O(com_llm_llm_rx_top_llm_rx_demux_un10_idle_a_n_5_1499) + ); + defparam com_llm_llm_rx_top_llm_rx_demux_un5_idle_a_n_4.INIT = 16'h8000; + LUT4 com_llm_llm_rx_top_llm_rx_demux_un5_idle_a_n_4 ( + .I0(phy_rd[56]), + .I1(phy_rd[57]), + .I2(phy_rd[58]), + .I3(phy_rd[59]), + .O(com_llm_llm_rx_top_llm_rx_demux_un5_idle_a_n_4_1502) + ); + defparam com_llm_llm_rx_top_llm_rx_demux_un5_idle_a_n_5.INIT = 16'h8000; + LUT4 com_llm_llm_rx_top_llm_rx_demux_un5_idle_a_n_5 ( + .I0(phy_rd[60]), + .I1(phy_rd[61]), + .I2(phy_rd[62]), + .I3(phy_rd[63]), + .O(com_llm_llm_rx_top_llm_rx_demux_un5_idle_a_n_5_1501) + ); + defparam com_llm_llm_rx_top_llm_rx_demux_tlp_ferr_n_q_9_u_i_m3_0.INIT = 16'hBBB8; + LUT4 com_llm_llm_rx_top_llm_rx_demux_tlp_ferr_n_q_9_u_i_m3_0 ( + .I0(com_llm_llm_rx_top_llm_rx_demux_phy_frame_h_t_1512), + .I1(com_llm_llm_rx_top_llm_rx_demux_phy_frame_l_t_1511), + .I2(phy_rctrl_h), + .I3(phy_rctrl_l), + .O(com_llm_llm_rx_top_llm_rx_demux_tlp_ferr_n_q_9_u_i_m3_0_1508) + ); + defparam com_llm_llm_rx_top_llm_rx_demux_dllp_vld_l_n_qq_7_i_o2.INIT = 16'hF531; + LUT4 com_llm_llm_rx_top_llm_rx_demux_dllp_vld_l_n_qq_7_i_o2 ( + .I0(com_llm_llm_rx_top_llm_rx_demux_dllp_a_1527), + .I1(com_llm_llm_rx_top_llm_rx_demux_dllp_u_1520), + .I2(com_llm_llm_rx_top_llm_rx_demux_phy_frame_h_t_1512), + .I3(phy_rferr_h_n), + .O(com_llm_llm_rx_top_llm_rx_demux_N_12825_i) + ); + defparam com_llm_llm_rx_top_llm_rx_demux_tlp_ip_flag_5_iv_i_o2.INIT = 16'h5551; + LUT4 com_llm_llm_rx_top_llm_rx_demux_tlp_ip_flag_5_iv_i_o2 ( + .I0(com_llm_llm_rx_top_llm_rx_demux_tlp_unalign_q13_i_a2_1521), + .I1(com_llm_llm_rx_top_llm_rx_demux_phy_frame_h_t_1512), + .I2(phy_rctrl_h), + .I3(phy_rctrl_l), + .O(com_llm_llm_rx_top_llm_rx_demux_N_12826_i) + ); + defparam com_llm_llm_rx_top_llm_rx_demux_tlp_vld_l_n_q_13_0_o2.INIT = 16'h5554; + LUT4 com_llm_llm_rx_top_llm_rx_demux_tlp_vld_l_n_q_13_0_o2 ( + .I0(com_llm_llm_rx_top_llm_rx_demux_N_12820_i), + .I1(com_llm_llm_rx_top_llm_rx_demux_phy_frame_l_t_1511), + .I2(phy_rctrl_h), + .I3(phy_rctrl_l), + .O(com_llm_llm_rx_top_llm_rx_demux_tlp_vld_l_n_q_13_0_o2_1510) + ); + defparam com_llm_llm_rx_top_llm_rx_demux_tlp_eof_n_q18_i_0_1.INIT = 4'h2; + LUT2 com_llm_llm_rx_top_llm_rx_demux_tlp_eof_n_q18_i_0_1 ( + .I0(com_llm_llm_rx_top_llm_rx_demux_N_12821_i), + .I1(phy_rctrl_h), + .O(com_llm_llm_rx_top_llm_rx_demux_N_67772_1) + ); + defparam com_llm_llm_rx_top_llm_rx_demux_N_12838_i.INIT = 4'hD; + LUT2 com_llm_llm_rx_top_llm_rx_demux_N_12838_i ( + .I0(com_llm_llm_rx_top_llm_rx_demux_N_12820_i), + .I1(com_llm_llm_rx_top_llm_rx_demux_dllp_u_1520), + .O(com_llm_llm_rx_top_llm_rx_demux_N_12838_i_1536) + ); + defparam com_llm_llm_rx_top_llm_rx_demux_N_12850_i.INIT = 4'hD; + LUT2 com_llm_llm_rx_top_llm_rx_demux_N_12850_i ( + .I0(com_llm_llm_rx_top_llm_rx_demux_N_12820_i), + .I1(com_llm_llm_rx_top_llm_rx_demux_tlp_ip_flag_1543), + .O(com_llm_llm_rx_top_llm_rx_demux_N_12850_i_1540) + ); + defparam com_llm_llm_rx_top_llm_rx_demux_dllp_sof_n_q_0_sqmuxa_0_a2.INIT = 16'h0888; + LUT4 com_llm_llm_rx_top_llm_rx_demux_dllp_sof_n_q_0_sqmuxa_0_a2 ( + .I0(com_llm_llm_rx_top_llm_rx_demux_N_12873_2), + .I1(com_llm_llm_rx_top_llm_rx_demux_phy_frame_l_t_1511), + .I2(com_llm_llm_rx_top_llm_rx_demux_un4_idle_on_low_n_4_1498), + .I3(com_llm_llm_rx_top_llm_rx_demux_un4_idle_on_low_n_5_1497), + .O(com_llm_llm_rx_top_llm_rx_demux_dllp_sof_n_q_0_sqmuxa) + ); + defparam com_llm_llm_rx_top_llm_rx_demux_dllp_vld_h_n_q_11_iv_i_a3_1_0.INIT = 16'h0777; + LUT4 com_llm_llm_rx_top_llm_rx_demux_dllp_vld_h_n_q_11_iv_i_a3_1_0 ( + .I0(com_llm_llm_rx_top_llm_rx_demux_un5_idle_a_n_4_1502), + .I1(com_llm_llm_rx_top_llm_rx_demux_un5_idle_a_n_5_1501), + .I2(com_llm_llm_rx_top_llm_rx_demux_un10_idle_a_n_4_1500), + .I3(com_llm_llm_rx_top_llm_rx_demux_un10_idle_a_n_5_1499), + .O(com_llm_llm_rx_top_llm_rx_demux_dllp_vld_h_n_q_11_iv_i_a3_1) + ); + defparam com_llm_llm_rx_top_llm_rx_demux_tlp_ferr_n_qq_8_u_i_1.INIT = 16'h1303; + LUT4_L com_llm_llm_rx_top_llm_rx_demux_tlp_ferr_n_qq_8_u_i_1 ( + .I0(com_llm_llm_rx_top_llm_rx_demux_N_12820_i), + .I1(com_llm_llm_rx_top_llm_rx_demux_N_12828_i), + .I2(com_llm_llm_rx_top_llm_rx_demux_tlp_ferr_n_q_1532), + .I3(com_llm_llm_rx_top_llm_rx_demux_tlp_unalign_q_1522), + .LO(com_llm_llm_rx_top_llm_rx_demux_tlp_ferr_n_qq_8_u_i_1_1509) + ); + defparam com_llm_llm_rx_top_llm_rx_demux_dllp_vld_h_n_q_11_iv_i_a3.INIT = 16'h0080; + LUT4 com_llm_llm_rx_top_llm_rx_demux_dllp_vld_h_n_q_11_iv_i_a3 ( + .I0(com_llm_llm_rx_top_llm_rx_demux_N_12873_2), + .I1(com_llm_llm_rx_top_llm_rx_demux_dllp_vld_h_n_q_11_iv_i_a3_1), + .I2(com_llm_llm_rx_top_llm_rx_demux_phy_frame_h_t_1512), + .I3(com_llm_llm_rx_top_llm_rx_demux_phy_frame_l_t_1511), + .O(com_llm_llm_rx_top_llm_rx_demux_dllp_vld_h_n_q_11_iv_i_a3_1505) + ); + defparam com_llm_llm_rx_top_llm_rx_demux_dllp_vld_h_n_q_11_iv_i_o3.INIT = 16'h3111; + LUT4_L com_llm_llm_rx_top_llm_rx_demux_dllp_vld_h_n_q_11_iv_i_o3 ( + .I0(com_llm_llm_rx_top_llm_rx_demux_N_12821_i), + .I1(com_llm_llm_rx_top_llm_rx_demux_dllp_vld_h_n_q_11_iv_i_a3_1505), + .I2(com_llm_llm_rx_top_llm_rx_demux_un4_idle_on_high_n_4_1504), + .I3(com_llm_llm_rx_top_llm_rx_demux_un4_idle_on_high_n_5_1503), + .LO(com_llm_llm_rx_top_llm_rx_demux_dllp_vld_h_n_q_11_iv_i_o3_1506) + ); + defparam com_llm_llm_rx_top_llm_rx_demux_dllp_sof_n_q26_m_1_a2.INIT = 8'h80; + LUT3 com_llm_llm_rx_top_llm_rx_demux_dllp_sof_n_q26_m_1_a2 ( + .I0(com_llm_llm_rx_top_llm_rx_demux_dllp_vld_h_n_q_11_iv_i_a3_1505), + .I1(phy_rctrl_h), + .I2(phy_rferr_h_n), + .O(com_llm_llm_rx_top_llm_rx_demux_dllp_sof_n_q26_m) + ); + defparam com_llm_llm_rx_top_llm_rx_demux_dllp_eof_n_qq_5_i.INIT = 8'h4C; + LUT3_L com_llm_llm_rx_top_llm_rx_demux_dllp_eof_n_qq_5_i ( + .I0(com_llm_llm_rx_top_llm_rx_demux_dllp_a_1527), + .I1(com_llm_llm_rx_top_llm_rx_demux_dllp_eof_n_q_1517), + .I2(com_llm_llm_rx_top_llm_rx_demux_phy_frame_h_t_1512), + .LO(com_llm_llm_rx_top_llm_rx_demux_N_12778_i) + ); + defparam com_llm_llm_rx_top_llm_rx_demux_dllp_eof_n_q13_i.INIT = 8'h7F; + LUT3_L com_llm_llm_rx_top_llm_rx_demux_dllp_eof_n_q13_i ( + .I0(com_llm_llm_rx_top_llm_rx_demux_N_12821_i), + .I1(com_llm_llm_rx_top_llm_rx_demux_dllp_u_1520), + .I2(phy_rferr_h_n), + .LO(com_llm_llm_rx_top_llm_rx_demux_dllp_eof_n_q13_i_1516) + ); + defparam com_llm_llm_rx_top_llm_rx_demux_tlp_align_q13_0_a2.INIT = 16'h0002; + LUT4_L com_llm_llm_rx_top_llm_rx_demux_tlp_align_q13_0_a2 ( + .I0(com_llm_llm_rx_top_llm_rx_demux_phy_frame_h_t_1512), + .I1(com_llm_llm_rx_top_llm_rx_demux_phy_frame_l_t_1511), + .I2(phy_rctrl_h), + .I3(phy_rctrl_l), + .LO(com_llm_llm_rx_top_llm_rx_demux_tlp_align_q13) + ); + defparam com_llm_llm_rx_top_llm_rx_demux_N_69444_i.INIT = 4'hD; + LUT2_L com_llm_llm_rx_top_llm_rx_demux_N_69444_i ( + .I0(com_llm_llm_rx_top_llm_rx_demux_N_12825_i), + .I1(com_llm_llm_rx_top_llm_rx_demux_dllp_vld_h_n_q_1530), + .LO(com_llm_llm_rx_top_llm_rx_demux_N_69444_i_1519) + ); + defparam com_llm_llm_rx_top_llm_rx_demux_N_67772_i.INIT = 16'hF5F7; + LUT4_L com_llm_llm_rx_top_llm_rx_demux_N_67772_i ( + .I0(com_llm_llm_rx_top_llm_rx_demux_N_67772_1), + .I1(com_llm_llm_rx_top_llm_rx_demux_tlp_ip_flag_1543), + .I2(com_llm_llm_rx_top_llm_rx_demux_tlp_unalign_q_1522), + .I3(phy_rctrl_l), + .LO(com_llm_llm_rx_top_llm_rx_demux_N_67772_i_1523) + ); + defparam com_llm_llm_rx_top_llm_rx_demux_N_67819_i.INIT = 16'hF7F3; + LUT4_L com_llm_llm_rx_top_llm_rx_demux_N_67819_i ( + .I0(com_llm_llm_rx_top_llm_rx_demux_N_12821_i), + .I1(com_llm_llm_rx_top_llm_rx_demux_N_12825_i), + .I2(com_llm_llm_rx_top_llm_rx_demux_dllp_sof_n_q_1533), + .I3(com_llm_llm_rx_top_llm_rx_demux_dllp_u_1520), + .LO(com_llm_llm_rx_top_llm_rx_demux_N_67819_i_1524) + ); + defparam com_llm_llm_rx_top_llm_rx_demux_N_69442_i.INIT = 16'hFFDC; + LUT4_L com_llm_llm_rx_top_llm_rx_demux_N_69442_i ( + .I0(com_llm_llm_rx_top_llm_rx_demux_N_12820_i), + .I1(com_llm_llm_rx_top_llm_rx_demux_N_12828_i), + .I2(com_llm_llm_rx_top_llm_rx_demux_tlp_unalign_q_1522), + .I3(com_llm_llm_rx_top_llm_rx_demux_tlp_vld_l_n_q_1541), + .LO(com_llm_llm_rx_top_llm_rx_demux_N_69442_i_1525) + ); + defparam com_llm_llm_rx_top_llm_rx_demux_N_69443_i.INIT = 16'hFDFC; + LUT4_L com_llm_llm_rx_top_llm_rx_demux_N_69443_i ( + .I0(com_llm_llm_rx_top_llm_rx_demux_N_12820_i), + .I1(com_llm_llm_rx_top_llm_rx_demux_N_12828_i), + .I2(com_llm_llm_rx_top_llm_rx_demux_tlp_sof_n_q_1528), + .I3(com_llm_llm_rx_top_llm_rx_demux_tlp_unalign_q_1522), + .LO(com_llm_llm_rx_top_llm_rx_demux_N_69443_i_1526) + ); + defparam com_llm_llm_rx_top_llm_rx_demux_N_12852_i.INIT = 16'hEFFF; + LUT4_L com_llm_llm_rx_top_llm_rx_demux_N_12852_i ( + .I0(com_llm_llm_rx_top_llm_rx_demux_dllp_vld_h_n_q_11_iv_i_o3_1506), + .I1(com_llm_llm_rx_top_llm_rx_demux_long_dllp_u_q_1537), + .I2(phy_rctrl_h), + .I3(phy_rferr_h_n), + .LO(com_llm_llm_rx_top_llm_rx_demux_N_12852_i_1529) + ); + defparam com_llm_llm_rx_top_llm_rx_demux_N_67820_i.INIT = 16'hF0FE; + LUT4_L com_llm_llm_rx_top_llm_rx_demux_N_67820_i ( + .I0(com_llm_llm_rx_top_llm_rx_demux_N_12820_i), + .I1(com_llm_llm_rx_top_llm_rx_demux_tlp_ferr_n_q_9_u_i_m3_0_1508), + .I2(com_llm_llm_rx_top_llm_rx_demux_tlp_ferr_n_q_9_u_i_a2_1507), + .I3(com_llm_llm_rx_top_llm_rx_demux_tlp_ip_flag_1543), + .LO(com_llm_llm_rx_top_llm_rx_demux_N_67820_i_1531) + ); + defparam com_llm_llm_rx_top_llm_rx_demux_dllp_sof_n_q_10_iv_i.INIT = 4'h1; + LUT2_L com_llm_llm_rx_top_llm_rx_demux_dllp_sof_n_q_10_iv_i ( + .I0(com_llm_llm_rx_top_llm_rx_demux_dllp_sof_n_q26_m), + .I1(com_llm_llm_rx_top_llm_rx_demux_dllp_sof_n_q_0_sqmuxa), + .LO(com_llm_llm_rx_top_llm_rx_demux_N_12796_i) + ); + defparam com_llm_llm_rx_top_llm_rx_demux_tlp_vld_h_n_qq_7_f0_i.INIT = 16'h3F2A; + LUT4_L com_llm_llm_rx_top_llm_rx_demux_tlp_vld_h_n_qq_7_f0_i ( + .I0(com_llm_llm_rx_top_llm_rx_demux_N_12828_i), + .I1(com_llm_llm_rx_top_llm_rx_demux_phy_frame_l_t_1511), + .I2(com_llm_llm_rx_top_llm_rx_demux_tlp_unalign_q_1522), + .I3(com_llm_llm_rx_top_llm_rx_demux_tlp_vld_h_n_q_1538), + .LO(com_llm_llm_rx_top_llm_rx_demux_N_12784_i) + ); + defparam com_llm_llm_rx_top_llm_rx_demux_tlp_sof_n_q_and_tlp_ip_flag_6_u_0_a2.INIT = 4'h8; + LUT2_L com_llm_llm_rx_top_llm_rx_demux_tlp_sof_n_q_and_tlp_ip_flag_6_u_0_a2 ( + .I0(com_llm_llm_rx_top_llm_rx_demux_N_12820_i), + .I1(com_llm_llm_rx_top_llm_rx_demux_tlp_sof_n_q_1528), + .LO(com_llm_llm_rx_top_llm_rx_demux_tlp_sof_n_q_and_tlp_ip_flag_6) + ); + defparam com_llm_llm_rx_top_llm_rx_demux_N_67771_i.INIT = 16'h4F0F; + LUT4_L com_llm_llm_rx_top_llm_rx_demux_N_67771_i ( + .I0(com_llm_llm_rx_top_llm_rx_demux_N_12820_i), + .I1(com_llm_llm_rx_top_llm_rx_demux_tlp_ferr_h_n_q_1534), + .I2(com_llm_llm_rx_top_llm_rx_demux_tlp_ferr_n_qq_8_u_i_1_1509), + .I3(com_llm_llm_rx_top_llm_rx_demux_tlp_unalign_q_1522), + .LO(com_llm_llm_rx_top_llm_rx_demux_N_67771_i_1535) + ); + defparam com_llm_llm_rx_top_llm_rx_demux_long_dllp_u_q13_0_a2.INIT = 4'h8; + LUT2_L com_llm_llm_rx_top_llm_rx_demux_long_dllp_u_q13_0_a2 ( + .I0(com_llm_llm_rx_top_llm_rx_demux_N_12820_i), + .I1(com_llm_llm_rx_top_llm_rx_demux_dllp_u_1520), + .LO(com_llm_llm_rx_top_llm_rx_demux_long_dllp_u_q13) + ); + defparam com_llm_llm_rx_top_llm_rx_demux_un1_long_dllp_u_q14_2_i.INIT = 16'hAAA8; + LUT4_L com_llm_llm_rx_top_llm_rx_demux_un1_long_dllp_u_q14_2_i ( + .I0(com_llm_llm_rx_top_llm_rx_demux_tlp_vld_l_n_q_13_0_o2_1510), + .I1(com_llm_llm_rx_top_llm_rx_demux_phy_frame_h_t_1512), + .I2(com_llm_llm_rx_top_llm_rx_demux_tlp_unalign_q_1522), + .I3(phy_rctrl_h), + .LO(com_llm_llm_rx_top_llm_rx_demux_N_12810_i) + ); + defparam com_llm_llm_rx_top_llm_rx_demux_N_69446_i.INIT = 8'hB3; + LUT3_L com_llm_llm_rx_top_llm_rx_demux_N_69446_i ( + .I0(com_llm_llm_rx_top_llm_rx_demux_N_12820_i), + .I1(com_llm_llm_rx_top_llm_rx_demux_N_12826_i), + .I2(com_llm_llm_rx_top_llm_rx_demux_tlp_ip_flag_1543), + .LO(com_llm_llm_rx_top_llm_rx_demux_N_69446_i_1539) + ); + defparam com_llm_llm_rx_top_llm_rx_demux_tlp_vld_l_n_q_13_0.INIT = 8'hC4; + LUT3_L com_llm_llm_rx_top_llm_rx_demux_tlp_vld_l_n_q_13_0 ( + .I0(com_llm_llm_rx_top_llm_rx_demux_tlp_unalign_q13_i_a2_1521), + .I1(com_llm_llm_rx_top_llm_rx_demux_tlp_vld_l_n_q_13_0_o2_1510), + .I2(com_llm_llm_rx_top_llm_rx_demux_tlp_unalign_q_1522), + .LO(com_llm_llm_rx_top_llm_rx_demux_N_9766_i) + ); + defparam com_llm_llm_rx_top_llm_rx_demux_rx_dllp_sof_n_i.INIT = 4'h1; + LUT1_L com_llm_llm_rx_top_llm_rx_demux_rx_dllp_sof_n_i ( + .I0(com_llm_llm_rx_top_rx_dllp_sof_n), + .LO(com_llm_llm_rx_top_rx_dllp_sof_n_i) + ); + defparam com_llm_llm_rx_top_llm_rx_demux_rx_tferr_n_i.INIT = 4'h1; + LUT1_L com_llm_llm_rx_top_llm_rx_demux_rx_tferr_n_i ( + .I0(com_llm_llm_rx_top_llm_rx_demux_rx_tferr_n), + .LO(com_llm_llm_rx_top_rx_tferr_n_i) + ); + defparam com_llm_llm_rx_top_llm_rx_demux_tlp_ferr_h_n_q_9_0_1.INIT = 16'h5551; + LUT4_L com_llm_llm_rx_top_llm_rx_demux_tlp_ferr_h_n_q_9_0_1 ( + .I0(com_llm_llm_rx_top_llm_rx_demux_N_12821_i), + .I1(com_llm_llm_rx_top_llm_rx_demux_phy_frame_h_t_1512), + .I2(com_llm_llm_rx_top_llm_rx_demux_phy_frame_l_t_1511), + .I3(phy_rctrl_l), + .LO(com_llm_llm_rx_top_llm_rx_demux_tlp_ferr_h_n_q_9_0_1_1544) + ); + defparam com_llm_llm_rx_top_llm_rx_demux_N_67762_i_1.INIT = 16'h5775; + LUT4 com_llm_llm_rx_top_llm_rx_demux_N_67762_i_1 ( + .I0(com_llm_llm_rx_top_llm_rx_demux_phy_frame_h_t_1512), + .I1(com_llm_llm_rx_top_llm_rx_demux_phy_frame_l_t_1511), + .I2(phy_rctrl_h), + .I3(phy_rctrl_l), + .O(com_llm_llm_rx_top_llm_rx_demux_N_67762_i_1_1548) + ); + defparam com_llm_llm_rx_top_llm_rx_demux_tlp_unalign_q13_i_a2.INIT = 8'h14; + LUT3 com_llm_llm_rx_top_llm_rx_demux_tlp_unalign_q13_i_a2 ( + .I0(phy_rctrl_l), + .I1(phy_rframe_l), + .I2(com_llm_llm_rx_top_llm_rx_demux_phy_frame_l_q_1513), + .O(com_llm_llm_rx_top_llm_rx_demux_tlp_unalign_q13_i_a2_1521) + ); + defparam com_llm_llm_rx_top_llm_rx_demux_tlp_eof_n_q18_i_0_o2.INIT = 8'h14; + LUT3 com_llm_llm_rx_top_llm_rx_demux_tlp_eof_n_q18_i_0_o2 ( + .I0(com_llm_llm_rx_top_llm_rx_demux_phy_frame_h_t_1512), + .I1(phy_rframe_l), + .I2(com_llm_llm_rx_top_llm_rx_demux_phy_frame_l_q_1513), + .O(com_llm_llm_rx_top_llm_rx_demux_N_12821_i) + ); + defparam com_llm_llm_rx_top_llm_rx_demux_N_9779_i_i_o3.INIT = 8'h41; + LUT3 com_llm_llm_rx_top_llm_rx_demux_N_9779_i_i_o3 ( + .I0(com_llm_llm_rx_top_llm_rx_demux_phy_frame_h_t_1512), + .I1(phy_rframe_l), + .I2(com_llm_llm_rx_top_llm_rx_demux_phy_frame_l_q_1513), + .O(com_llm_llm_rx_top_llm_rx_demux_N_12820_i) + ); + defparam com_llm_llm_rx_top_llm_rx_demux_tlp_vld_h_n_qq_7_f0_i_o3.INIT = 8'h28; + LUT3 com_llm_llm_rx_top_llm_rx_demux_tlp_vld_h_n_qq_7_f0_i_o3 ( + .I0(com_llm_llm_rx_top_llm_rx_demux_tlp_align_q_1518), + .I1(phy_rframe_h), + .I2(com_llm_llm_rx_top_llm_rx_demux_phy_frame_h_q_1514), + .O(com_llm_llm_rx_top_llm_rx_demux_N_12828_i) + ); + FDC com_llm_llm_rx_top_llm_rx_demux_phy_rbad_frm_q ( + .C(NlwRenamedSig_OI_trn_clk), + .D(N_50789_i), + .Q(com_llm_llm_rx_top_llm_rx_demux_phy_rbad_frm_q_1515), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_demux_phy_frame_l_q ( + .C(NlwRenamedSig_OI_trn_clk), + .D(phy_rframe_l), + .Q(com_llm_llm_rx_top_llm_rx_demux_phy_frame_l_q_1513), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_demux_phy_frame_h_q ( + .C(NlwRenamedSig_OI_trn_clk), + .D(phy_rframe_h), + .Q(com_llm_llm_rx_top_llm_rx_demux_phy_frame_h_q_1514), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_demux_phy_rbad_frm_qq ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_demux_phy_rbad_frm_q_1515), + .Q(com_llm_llm_rx_top_rx_tlp_nullified), + .CLR(plm_link_up_i) + ); + FDP com_llm_llm_rx_top_llm_rx_demux_dllp_eof_n_qq ( + .PRE(plm_link_up_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_demux_N_12778_i), + .Q(com_llm_llm_rx_top_rx_dllp_eof_n) + ); + FDP com_llm_llm_rx_top_llm_rx_demux_dllp_eof_n_q ( + .PRE(plm_link_up_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_demux_dllp_eof_n_q13_i_1516), + .Q(com_llm_llm_rx_top_llm_rx_demux_dllp_eof_n_q_1517) + ); + FDC com_llm_llm_rx_top_llm_rx_demux_tlp_align_q ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_demux_tlp_align_q13), + .Q(com_llm_llm_rx_top_llm_rx_demux_tlp_align_q_1518), + .CLR(plm_link_up_i) + ); + FDP com_llm_llm_rx_top_llm_rx_demux_dllp_vld_h_n_qq ( + .PRE(plm_link_up_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_demux_N_69444_i_1519), + .Q(com_llm_llm_rx_top_rx_dllp_vld_h_n) + ); + FDC com_llm_llm_rx_top_llm_rx_demux_dllp_u ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_demux_dllp_sof_n_q_0_sqmuxa), + .Q(com_llm_llm_rx_top_llm_rx_demux_dllp_u_1520), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_demux_tlp_unalign_q ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_demux_tlp_unalign_q13_i_a2_1521), + .Q(com_llm_llm_rx_top_llm_rx_demux_tlp_unalign_q_1522), + .CLR(plm_link_up_i) + ); + FDP com_llm_llm_rx_top_llm_rx_demux_tlp_eof_n_q ( + .PRE(plm_link_up_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_demux_N_67772_i_1523), + .Q(com_llm_llm_rx_top_llm_rx_demux_tlp_eof_n_q_1547) + ); + FDP com_llm_llm_rx_top_llm_rx_demux_dllp_sof_n_qq ( + .PRE(plm_link_up_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_demux_N_67819_i_1524), + .Q(com_llm_llm_rx_top_rx_dllp_sof_n) + ); + FDP com_llm_llm_rx_top_llm_rx_demux_tlp_vld_l_n_qq ( + .PRE(plm_link_up_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_demux_N_69442_i_1525), + .Q(com_llm_llm_rx_top_rx_tlp_vld_l_n) + ); + FDP com_llm_llm_rx_top_llm_rx_demux_tlp_sof_n_qq ( + .PRE(plm_link_up_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_demux_N_69443_i_1526), + .Q(com_llm_llm_rx_top_rx_tlp_sof_n) + ); + FDC com_llm_llm_rx_top_llm_rx_demux_dllp_a ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_demux_dllp_sof_n_q26_m), + .Q(com_llm_llm_rx_top_llm_rx_demux_dllp_a_1527), + .CLR(plm_link_up_i) + ); + FDP com_llm_llm_rx_top_llm_rx_demux_tlp_sof_n_q ( + .PRE(plm_link_up_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_demux_N_12826_i), + .Q(com_llm_llm_rx_top_llm_rx_demux_tlp_sof_n_q_1528) + ); + FDP com_llm_llm_rx_top_llm_rx_demux_dllp_vld_h_n_q ( + .PRE(plm_link_up_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_demux_N_12852_i_1529), + .Q(com_llm_llm_rx_top_llm_rx_demux_dllp_vld_h_n_q_1530) + ); + FDP com_llm_llm_rx_top_llm_rx_demux_tlp_ferr_n_q ( + .PRE(plm_link_up_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_demux_N_67820_i_1531), + .Q(com_llm_llm_rx_top_llm_rx_demux_tlp_ferr_n_q_1532) + ); + FDP com_llm_llm_rx_top_llm_rx_demux_dllp_sof_n_q ( + .PRE(plm_link_up_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_demux_N_12796_i), + .Q(com_llm_llm_rx_top_llm_rx_demux_dllp_sof_n_q_1533) + ); + FDP com_llm_llm_rx_top_llm_rx_demux_tlp_vld_h_n_qq ( + .PRE(plm_link_up_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_demux_N_12784_i), + .Q(com_llm_llm_rx_top_rx_tlp_vld_h_n) + ); + FDP com_llm_llm_rx_top_llm_rx_demux_tlp_ferr_h_n_q ( + .PRE(plm_link_up_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_demux_N_9763_i), + .Q(com_llm_llm_rx_top_llm_rx_demux_tlp_ferr_h_n_q_1534) + ); + FDC com_llm_llm_rx_top_llm_rx_demux_tlp_sof_n_q_and_tlp_ip_flag ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_demux_tlp_sof_n_q_and_tlp_ip_flag_6), + .Q(com_llm_llm_rx_top_llm_rx_demux_tlp_sof_n_q_and_tlp_ip_flag_1546), + .CLR(plm_link_up_i) + ); + FDP com_llm_llm_rx_top_llm_rx_demux_tlp_ferr_n_qq ( + .PRE(plm_link_up_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_demux_N_67771_i_1535), + .Q(com_llm_llm_rx_top_llm_rx_demux_rx_tferr_n) + ); + FD com_llm_llm_rx_top_llm_rx_demux_phy_rd_q_1__8_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_demux_phy_rd_q_0_[8]), + .Q(com_llm_llm_rx_top_rx_data_8_) + ); + FD com_llm_llm_rx_top_llm_rx_demux_phy_rd_q_1__7_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_demux_phy_rd_q_0_[7]), + .Q(com_llm_llm_rx_top_rx_data_7_) + ); + FD com_llm_llm_rx_top_llm_rx_demux_phy_rd_q_1__6_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_demux_phy_rd_q_0_[6]), + .Q(com_llm_llm_rx_top_rx_data_6_) + ); + FD com_llm_llm_rx_top_llm_rx_demux_phy_rd_q_1__5_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_demux_phy_rd_q_0_[5]), + .Q(com_llm_llm_rx_top_rx_data_5_) + ); + FD com_llm_llm_rx_top_llm_rx_demux_phy_rd_q_1__4_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_demux_phy_rd_q_0_[4]), + .Q(com_llm_llm_rx_top_rx_data_4_) + ); + FD com_llm_llm_rx_top_llm_rx_demux_phy_rd_q_1__3_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_demux_phy_rd_q_0_[3]), + .Q(com_llm_llm_rx_top_rx_data_3_) + ); + FD com_llm_llm_rx_top_llm_rx_demux_phy_rd_q_1__2_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_demux_phy_rd_q_0_[2]), + .Q(com_llm_llm_rx_top_rx_data_2_) + ); + FD com_llm_llm_rx_top_llm_rx_demux_phy_rd_q_1__1_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_demux_phy_rd_q_0_[1]), + .Q(com_llm_llm_rx_top_rx_data_1_) + ); + FD com_llm_llm_rx_top_llm_rx_demux_phy_rd_q_1__0_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_demux_phy_rd_q_0_[0]), + .Q(com_llm_llm_rx_top_rx_data_0_) + ); + FD com_llm_llm_rx_top_llm_rx_demux_phy_rd_q_1__23_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_demux_phy_rd_q_0_[23]), + .Q(com_llm_llm_rx_top_rx_data_23_) + ); + FD com_llm_llm_rx_top_llm_rx_demux_phy_rd_q_1__22_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_demux_phy_rd_q_0_[22]), + .Q(com_llm_llm_rx_top_rx_data_22_) + ); + FD com_llm_llm_rx_top_llm_rx_demux_phy_rd_q_1__21_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_demux_phy_rd_q_0_[21]), + .Q(com_llm_llm_rx_top_rx_data_21_) + ); + FD com_llm_llm_rx_top_llm_rx_demux_phy_rd_q_1__20_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_demux_phy_rd_q_0_[20]), + .Q(com_llm_llm_rx_top_rx_data_20_) + ); + FD com_llm_llm_rx_top_llm_rx_demux_phy_rd_q_1__19_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_demux_phy_rd_q_0_[19]), + .Q(com_llm_llm_rx_top_rx_data_19_) + ); + FD com_llm_llm_rx_top_llm_rx_demux_phy_rd_q_1__18_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_demux_phy_rd_q_0_[18]), + .Q(com_llm_llm_rx_top_rx_data_18_) + ); + FD com_llm_llm_rx_top_llm_rx_demux_phy_rd_q_1__17_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_demux_phy_rd_q_0_[17]), + .Q(com_llm_llm_rx_top_rx_data_17_) + ); + FD com_llm_llm_rx_top_llm_rx_demux_phy_rd_q_1__16_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_demux_phy_rd_q_0_[16]), + .Q(com_llm_llm_rx_top_rx_data_16_) + ); + FD com_llm_llm_rx_top_llm_rx_demux_phy_rd_q_1__15_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_demux_phy_rd_q_0_[15]), + .Q(com_llm_llm_rx_top_rx_data_15_) + ); + FD com_llm_llm_rx_top_llm_rx_demux_phy_rd_q_1__14_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_demux_phy_rd_q_0_[14]), + .Q(com_llm_llm_rx_top_rx_data_14_) + ); + FD com_llm_llm_rx_top_llm_rx_demux_phy_rd_q_1__13_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_demux_phy_rd_q_0_[13]), + .Q(com_llm_llm_rx_top_rx_data_13_) + ); + FD com_llm_llm_rx_top_llm_rx_demux_phy_rd_q_1__12_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_demux_phy_rd_q_0_[12]), + .Q(com_llm_llm_rx_top_rx_data_12_) + ); + FD com_llm_llm_rx_top_llm_rx_demux_phy_rd_q_1__11_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_demux_phy_rd_q_0_[11]), + .Q(com_llm_llm_rx_top_rx_data_11_) + ); + FD com_llm_llm_rx_top_llm_rx_demux_phy_rd_q_1__10_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_demux_phy_rd_q_0_[10]), + .Q(com_llm_llm_rx_top_rx_data_10_) + ); + FD com_llm_llm_rx_top_llm_rx_demux_phy_rd_q_1__9_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_demux_phy_rd_q_0_[9]), + .Q(com_llm_llm_rx_top_rx_data_9_) + ); + FD com_llm_llm_rx_top_llm_rx_demux_phy_rd_q_1__38_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_demux_phy_rd_q_0_[38]), + .Q(com_llm_llm_rx_top_rx_data_38_) + ); + FD com_llm_llm_rx_top_llm_rx_demux_phy_rd_q_1__37_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_demux_phy_rd_q_0_[37]), + .Q(com_llm_llm_rx_top_rx_data_37_) + ); + FD com_llm_llm_rx_top_llm_rx_demux_phy_rd_q_1__36_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_demux_phy_rd_q_0_[36]), + .Q(com_llm_llm_rx_top_rx_data_36_) + ); + FD com_llm_llm_rx_top_llm_rx_demux_phy_rd_q_1__35_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_demux_phy_rd_q_0_[35]), + .Q(com_llm_llm_rx_top_rx_data_35_) + ); + FD com_llm_llm_rx_top_llm_rx_demux_phy_rd_q_1__34_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_demux_phy_rd_q_0_[34]), + .Q(com_llm_llm_rx_top_rx_data_34_) + ); + FD com_llm_llm_rx_top_llm_rx_demux_phy_rd_q_1__33_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_demux_phy_rd_q_0_[33]), + .Q(com_llm_llm_rx_top_rx_data_33_) + ); + FD com_llm_llm_rx_top_llm_rx_demux_phy_rd_q_1__32_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_demux_phy_rd_q_0_[32]), + .Q(com_llm_llm_rx_top_rx_data_32_) + ); + FD com_llm_llm_rx_top_llm_rx_demux_phy_rd_q_1__31_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_demux_phy_rd_q_0_[31]), + .Q(com_llm_llm_rx_top_rx_data_31_) + ); + FD com_llm_llm_rx_top_llm_rx_demux_phy_rd_q_1__30_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_demux_phy_rd_q_0_[30]), + .Q(com_llm_llm_rx_top_rx_data_30_) + ); + FD com_llm_llm_rx_top_llm_rx_demux_phy_rd_q_1__29_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_demux_phy_rd_q_0_[29]), + .Q(com_llm_llm_rx_top_rx_data_29_) + ); + FD com_llm_llm_rx_top_llm_rx_demux_phy_rd_q_1__28_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_demux_phy_rd_q_0_[28]), + .Q(com_llm_llm_rx_top_rx_data_28_) + ); + FD com_llm_llm_rx_top_llm_rx_demux_phy_rd_q_1__27_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_demux_phy_rd_q_0_[27]), + .Q(com_llm_llm_rx_top_rx_data_27_) + ); + FD com_llm_llm_rx_top_llm_rx_demux_phy_rd_q_1__26_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_demux_phy_rd_q_0_[26]), + .Q(com_llm_llm_rx_top_rx_data_26_) + ); + FD com_llm_llm_rx_top_llm_rx_demux_phy_rd_q_1__25_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_demux_phy_rd_q_0_[25]), + .Q(com_llm_llm_rx_top_rx_data_25_) + ); + FD com_llm_llm_rx_top_llm_rx_demux_phy_rd_q_1__24_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_demux_phy_rd_q_0_[24]), + .Q(com_llm_llm_rx_top_rx_data_24_) + ); + FD com_llm_llm_rx_top_llm_rx_demux_phy_rd_q_1__53_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_demux_phy_rd_q_0_[53]), + .Q(com_llm_llm_rx_top_rx_data_53_) + ); + FD com_llm_llm_rx_top_llm_rx_demux_phy_rd_q_1__52_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_demux_phy_rd_q_0_[52]), + .Q(com_llm_llm_rx_top_rx_data_52_) + ); + FD com_llm_llm_rx_top_llm_rx_demux_phy_rd_q_1__51_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_demux_phy_rd_q_0_[51]), + .Q(com_llm_llm_rx_top_rx_data_51_) + ); + FD com_llm_llm_rx_top_llm_rx_demux_phy_rd_q_1__50_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_demux_phy_rd_q_0_[50]), + .Q(com_llm_llm_rx_top_rx_data_50_) + ); + FD com_llm_llm_rx_top_llm_rx_demux_phy_rd_q_1__49_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_demux_phy_rd_q_0_[49]), + .Q(com_llm_llm_rx_top_rx_data_49_) + ); + FD com_llm_llm_rx_top_llm_rx_demux_phy_rd_q_1__48_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_demux_phy_rd_q_0_[48]), + .Q(com_llm_llm_rx_top_rx_data_48_) + ); + FD com_llm_llm_rx_top_llm_rx_demux_phy_rd_q_1__47_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_demux_phy_rd_q_0_[47]), + .Q(com_llm_llm_rx_top_rx_data_47_) + ); + FD com_llm_llm_rx_top_llm_rx_demux_phy_rd_q_1__46_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_demux_phy_rd_q_0_[46]), + .Q(com_llm_llm_rx_top_rx_data_46_) + ); + FD com_llm_llm_rx_top_llm_rx_demux_phy_rd_q_1__45_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_demux_phy_rd_q_0_[45]), + .Q(com_llm_llm_rx_top_rx_data_45_) + ); + FD com_llm_llm_rx_top_llm_rx_demux_phy_rd_q_1__44_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_demux_phy_rd_q_0_[44]), + .Q(com_llm_llm_rx_top_rx_data_44_) + ); + FD com_llm_llm_rx_top_llm_rx_demux_phy_rd_q_1__43_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_demux_phy_rd_q_0_[43]), + .Q(com_llm_llm_rx_top_rx_data_43_) + ); + FD com_llm_llm_rx_top_llm_rx_demux_phy_rd_q_1__42_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_demux_phy_rd_q_0_[42]), + .Q(com_llm_llm_rx_top_rx_data_42_) + ); + FD com_llm_llm_rx_top_llm_rx_demux_phy_rd_q_1__41_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_demux_phy_rd_q_0_[41]), + .Q(com_llm_llm_rx_top_rx_data_41_) + ); + FD com_llm_llm_rx_top_llm_rx_demux_phy_rd_q_1__40_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_demux_phy_rd_q_0_[40]), + .Q(com_llm_llm_rx_top_rx_data_40_) + ); + FD com_llm_llm_rx_top_llm_rx_demux_phy_rd_q_1__39_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_demux_phy_rd_q_0_[39]), + .Q(com_llm_llm_rx_top_rx_data_39_) + ); + FD com_llm_llm_rx_top_llm_rx_demux_phy_rd_q_1__63_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_demux_phy_rd_q_0_[63]), + .Q(com_llm_llm_rx_top_rx_data_63_) + ); + FD com_llm_llm_rx_top_llm_rx_demux_phy_rd_q_1__62_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_demux_phy_rd_q_0_[62]), + .Q(com_llm_llm_rx_top_rx_data_62_) + ); + FD com_llm_llm_rx_top_llm_rx_demux_phy_rd_q_1__61_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_demux_phy_rd_q_0_[61]), + .Q(com_llm_llm_rx_top_rx_data_61_) + ); + FD com_llm_llm_rx_top_llm_rx_demux_phy_rd_q_1__60_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_demux_phy_rd_q_0_[60]), + .Q(com_llm_llm_rx_top_rx_data_60_) + ); + FD com_llm_llm_rx_top_llm_rx_demux_phy_rd_q_1__59_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_demux_phy_rd_q_0_[59]), + .Q(com_llm_llm_rx_top_rx_data_59_) + ); + FD com_llm_llm_rx_top_llm_rx_demux_phy_rd_q_1__58_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_demux_phy_rd_q_0_[58]), + .Q(com_llm_llm_rx_top_rx_data_58_) + ); + FD com_llm_llm_rx_top_llm_rx_demux_phy_rd_q_1__57_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_demux_phy_rd_q_0_[57]), + .Q(com_llm_llm_rx_top_rx_data_57_) + ); + FD com_llm_llm_rx_top_llm_rx_demux_phy_rd_q_1__56_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_demux_phy_rd_q_0_[56]), + .Q(com_llm_llm_rx_top_rx_data_56_) + ); + FD com_llm_llm_rx_top_llm_rx_demux_phy_rd_q_1__55_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_demux_phy_rd_q_0_[55]), + .Q(com_llm_llm_rx_top_rx_data_55_) + ); + FD com_llm_llm_rx_top_llm_rx_demux_phy_rd_q_1__54_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_demux_phy_rd_q_0_[54]), + .Q(com_llm_llm_rx_top_rx_data_54_) + ); + FD com_llm_llm_rx_top_llm_rx_demux_phy_rd_q_0__0_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(phy_rd[0]), + .Q(com_llm_llm_rx_top_llm_rx_demux_phy_rd_q_0_[0]) + ); + FD com_llm_llm_rx_top_llm_rx_demux_phy_rd_q_0__15_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(phy_rd[15]), + .Q(com_llm_llm_rx_top_llm_rx_demux_phy_rd_q_0_[15]) + ); + FD com_llm_llm_rx_top_llm_rx_demux_phy_rd_q_0__14_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(phy_rd[14]), + .Q(com_llm_llm_rx_top_llm_rx_demux_phy_rd_q_0_[14]) + ); + FD com_llm_llm_rx_top_llm_rx_demux_phy_rd_q_0__13_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(phy_rd[13]), + .Q(com_llm_llm_rx_top_llm_rx_demux_phy_rd_q_0_[13]) + ); + FD com_llm_llm_rx_top_llm_rx_demux_phy_rd_q_0__12_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(phy_rd[12]), + .Q(com_llm_llm_rx_top_llm_rx_demux_phy_rd_q_0_[12]) + ); + FD com_llm_llm_rx_top_llm_rx_demux_phy_rd_q_0__11_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(phy_rd[11]), + .Q(com_llm_llm_rx_top_llm_rx_demux_phy_rd_q_0_[11]) + ); + FD com_llm_llm_rx_top_llm_rx_demux_phy_rd_q_0__10_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(phy_rd[10]), + .Q(com_llm_llm_rx_top_llm_rx_demux_phy_rd_q_0_[10]) + ); + FD com_llm_llm_rx_top_llm_rx_demux_phy_rd_q_0__9_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(phy_rd[9]), + .Q(com_llm_llm_rx_top_llm_rx_demux_phy_rd_q_0_[9]) + ); + FD com_llm_llm_rx_top_llm_rx_demux_phy_rd_q_0__8_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(phy_rd[8]), + .Q(com_llm_llm_rx_top_llm_rx_demux_phy_rd_q_0_[8]) + ); + FD com_llm_llm_rx_top_llm_rx_demux_phy_rd_q_0__7_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(phy_rd[7]), + .Q(com_llm_llm_rx_top_llm_rx_demux_phy_rd_q_0_[7]) + ); + FD com_llm_llm_rx_top_llm_rx_demux_phy_rd_q_0__6_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(phy_rd[6]), + .Q(com_llm_llm_rx_top_llm_rx_demux_phy_rd_q_0_[6]) + ); + FD com_llm_llm_rx_top_llm_rx_demux_phy_rd_q_0__5_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(phy_rd[5]), + .Q(com_llm_llm_rx_top_llm_rx_demux_phy_rd_q_0_[5]) + ); + FD com_llm_llm_rx_top_llm_rx_demux_phy_rd_q_0__4_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(phy_rd[4]), + .Q(com_llm_llm_rx_top_llm_rx_demux_phy_rd_q_0_[4]) + ); + FD com_llm_llm_rx_top_llm_rx_demux_phy_rd_q_0__3_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(phy_rd[3]), + .Q(com_llm_llm_rx_top_llm_rx_demux_phy_rd_q_0_[3]) + ); + FD com_llm_llm_rx_top_llm_rx_demux_phy_rd_q_0__2_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(phy_rd[2]), + .Q(com_llm_llm_rx_top_llm_rx_demux_phy_rd_q_0_[2]) + ); + FD com_llm_llm_rx_top_llm_rx_demux_phy_rd_q_0__1_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(phy_rd[1]), + .Q(com_llm_llm_rx_top_llm_rx_demux_phy_rd_q_0_[1]) + ); + FD com_llm_llm_rx_top_llm_rx_demux_phy_rd_q_0__30_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(phy_rd[30]), + .Q(com_llm_llm_rx_top_llm_rx_demux_phy_rd_q_0_[30]) + ); + FD com_llm_llm_rx_top_llm_rx_demux_phy_rd_q_0__29_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(phy_rd[29]), + .Q(com_llm_llm_rx_top_llm_rx_demux_phy_rd_q_0_[29]) + ); + FD com_llm_llm_rx_top_llm_rx_demux_phy_rd_q_0__28_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(phy_rd[28]), + .Q(com_llm_llm_rx_top_llm_rx_demux_phy_rd_q_0_[28]) + ); + FD com_llm_llm_rx_top_llm_rx_demux_phy_rd_q_0__27_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(phy_rd[27]), + .Q(com_llm_llm_rx_top_llm_rx_demux_phy_rd_q_0_[27]) + ); + FD com_llm_llm_rx_top_llm_rx_demux_phy_rd_q_0__26_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(phy_rd[26]), + .Q(com_llm_llm_rx_top_llm_rx_demux_phy_rd_q_0_[26]) + ); + FD com_llm_llm_rx_top_llm_rx_demux_phy_rd_q_0__25_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(phy_rd[25]), + .Q(com_llm_llm_rx_top_llm_rx_demux_phy_rd_q_0_[25]) + ); + FD com_llm_llm_rx_top_llm_rx_demux_phy_rd_q_0__24_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(phy_rd[24]), + .Q(com_llm_llm_rx_top_llm_rx_demux_phy_rd_q_0_[24]) + ); + FD com_llm_llm_rx_top_llm_rx_demux_phy_rd_q_0__23_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(phy_rd[23]), + .Q(com_llm_llm_rx_top_llm_rx_demux_phy_rd_q_0_[23]) + ); + FD com_llm_llm_rx_top_llm_rx_demux_phy_rd_q_0__22_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(phy_rd[22]), + .Q(com_llm_llm_rx_top_llm_rx_demux_phy_rd_q_0_[22]) + ); + FD com_llm_llm_rx_top_llm_rx_demux_phy_rd_q_0__21_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(phy_rd[21]), + .Q(com_llm_llm_rx_top_llm_rx_demux_phy_rd_q_0_[21]) + ); + FD com_llm_llm_rx_top_llm_rx_demux_phy_rd_q_0__20_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(phy_rd[20]), + .Q(com_llm_llm_rx_top_llm_rx_demux_phy_rd_q_0_[20]) + ); + FD com_llm_llm_rx_top_llm_rx_demux_phy_rd_q_0__19_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(phy_rd[19]), + .Q(com_llm_llm_rx_top_llm_rx_demux_phy_rd_q_0_[19]) + ); + FD com_llm_llm_rx_top_llm_rx_demux_phy_rd_q_0__18_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(phy_rd[18]), + .Q(com_llm_llm_rx_top_llm_rx_demux_phy_rd_q_0_[18]) + ); + FD com_llm_llm_rx_top_llm_rx_demux_phy_rd_q_0__17_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(phy_rd[17]), + .Q(com_llm_llm_rx_top_llm_rx_demux_phy_rd_q_0_[17]) + ); + FD com_llm_llm_rx_top_llm_rx_demux_phy_rd_q_0__16_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(phy_rd[16]), + .Q(com_llm_llm_rx_top_llm_rx_demux_phy_rd_q_0_[16]) + ); + FD com_llm_llm_rx_top_llm_rx_demux_phy_rd_q_0__45_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(phy_rd[45]), + .Q(com_llm_llm_rx_top_llm_rx_demux_phy_rd_q_0_[45]) + ); + FD com_llm_llm_rx_top_llm_rx_demux_phy_rd_q_0__44_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(phy_rd[44]), + .Q(com_llm_llm_rx_top_llm_rx_demux_phy_rd_q_0_[44]) + ); + FD com_llm_llm_rx_top_llm_rx_demux_phy_rd_q_0__43_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(phy_rd[43]), + .Q(com_llm_llm_rx_top_llm_rx_demux_phy_rd_q_0_[43]) + ); + FD com_llm_llm_rx_top_llm_rx_demux_phy_rd_q_0__42_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(phy_rd[42]), + .Q(com_llm_llm_rx_top_llm_rx_demux_phy_rd_q_0_[42]) + ); + FD com_llm_llm_rx_top_llm_rx_demux_phy_rd_q_0__41_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(phy_rd[41]), + .Q(com_llm_llm_rx_top_llm_rx_demux_phy_rd_q_0_[41]) + ); + FD com_llm_llm_rx_top_llm_rx_demux_phy_rd_q_0__40_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(phy_rd[40]), + .Q(com_llm_llm_rx_top_llm_rx_demux_phy_rd_q_0_[40]) + ); + FD com_llm_llm_rx_top_llm_rx_demux_phy_rd_q_0__39_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(phy_rd[39]), + .Q(com_llm_llm_rx_top_llm_rx_demux_phy_rd_q_0_[39]) + ); + FD com_llm_llm_rx_top_llm_rx_demux_phy_rd_q_0__38_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(phy_rd[38]), + .Q(com_llm_llm_rx_top_llm_rx_demux_phy_rd_q_0_[38]) + ); + FD com_llm_llm_rx_top_llm_rx_demux_phy_rd_q_0__37_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(phy_rd[37]), + .Q(com_llm_llm_rx_top_llm_rx_demux_phy_rd_q_0_[37]) + ); + FD com_llm_llm_rx_top_llm_rx_demux_phy_rd_q_0__36_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(phy_rd[36]), + .Q(com_llm_llm_rx_top_llm_rx_demux_phy_rd_q_0_[36]) + ); + FD com_llm_llm_rx_top_llm_rx_demux_phy_rd_q_0__35_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(phy_rd[35]), + .Q(com_llm_llm_rx_top_llm_rx_demux_phy_rd_q_0_[35]) + ); + FD com_llm_llm_rx_top_llm_rx_demux_phy_rd_q_0__34_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(phy_rd[34]), + .Q(com_llm_llm_rx_top_llm_rx_demux_phy_rd_q_0_[34]) + ); + FD com_llm_llm_rx_top_llm_rx_demux_phy_rd_q_0__33_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(phy_rd[33]), + .Q(com_llm_llm_rx_top_llm_rx_demux_phy_rd_q_0_[33]) + ); + FD com_llm_llm_rx_top_llm_rx_demux_phy_rd_q_0__32_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(phy_rd[32]), + .Q(com_llm_llm_rx_top_llm_rx_demux_phy_rd_q_0_[32]) + ); + FD com_llm_llm_rx_top_llm_rx_demux_phy_rd_q_0__31_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(phy_rd[31]), + .Q(com_llm_llm_rx_top_llm_rx_demux_phy_rd_q_0_[31]) + ); + FD com_llm_llm_rx_top_llm_rx_demux_phy_rd_q_0__60_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(phy_rd[60]), + .Q(com_llm_llm_rx_top_llm_rx_demux_phy_rd_q_0_[60]) + ); + FD com_llm_llm_rx_top_llm_rx_demux_phy_rd_q_0__59_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(phy_rd[59]), + .Q(com_llm_llm_rx_top_llm_rx_demux_phy_rd_q_0_[59]) + ); + FD com_llm_llm_rx_top_llm_rx_demux_phy_rd_q_0__58_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(phy_rd[58]), + .Q(com_llm_llm_rx_top_llm_rx_demux_phy_rd_q_0_[58]) + ); + FD com_llm_llm_rx_top_llm_rx_demux_phy_rd_q_0__57_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(phy_rd[57]), + .Q(com_llm_llm_rx_top_llm_rx_demux_phy_rd_q_0_[57]) + ); + FD com_llm_llm_rx_top_llm_rx_demux_phy_rd_q_0__56_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(phy_rd[56]), + .Q(com_llm_llm_rx_top_llm_rx_demux_phy_rd_q_0_[56]) + ); + FD com_llm_llm_rx_top_llm_rx_demux_phy_rd_q_0__55_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(phy_rd[55]), + .Q(com_llm_llm_rx_top_llm_rx_demux_phy_rd_q_0_[55]) + ); + FD com_llm_llm_rx_top_llm_rx_demux_phy_rd_q_0__54_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(phy_rd[54]), + .Q(com_llm_llm_rx_top_llm_rx_demux_phy_rd_q_0_[54]) + ); + FD com_llm_llm_rx_top_llm_rx_demux_phy_rd_q_0__53_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(phy_rd[53]), + .Q(com_llm_llm_rx_top_llm_rx_demux_phy_rd_q_0_[53]) + ); + FD com_llm_llm_rx_top_llm_rx_demux_phy_rd_q_0__52_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(phy_rd[52]), + .Q(com_llm_llm_rx_top_llm_rx_demux_phy_rd_q_0_[52]) + ); + FD com_llm_llm_rx_top_llm_rx_demux_phy_rd_q_0__51_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(phy_rd[51]), + .Q(com_llm_llm_rx_top_llm_rx_demux_phy_rd_q_0_[51]) + ); + FD com_llm_llm_rx_top_llm_rx_demux_phy_rd_q_0__50_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(phy_rd[50]), + .Q(com_llm_llm_rx_top_llm_rx_demux_phy_rd_q_0_[50]) + ); + FD com_llm_llm_rx_top_llm_rx_demux_phy_rd_q_0__49_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(phy_rd[49]), + .Q(com_llm_llm_rx_top_llm_rx_demux_phy_rd_q_0_[49]) + ); + FD com_llm_llm_rx_top_llm_rx_demux_phy_rd_q_0__48_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(phy_rd[48]), + .Q(com_llm_llm_rx_top_llm_rx_demux_phy_rd_q_0_[48]) + ); + FD com_llm_llm_rx_top_llm_rx_demux_phy_rd_q_0__47_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(phy_rd[47]), + .Q(com_llm_llm_rx_top_llm_rx_demux_phy_rd_q_0_[47]) + ); + FD com_llm_llm_rx_top_llm_rx_demux_phy_rd_q_0__46_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(phy_rd[46]), + .Q(com_llm_llm_rx_top_llm_rx_demux_phy_rd_q_0_[46]) + ); + FD com_llm_llm_rx_top_llm_rx_demux_phy_rd_q_0__63_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(phy_rd[63]), + .Q(com_llm_llm_rx_top_llm_rx_demux_phy_rd_q_0_[63]) + ); + FD com_llm_llm_rx_top_llm_rx_demux_phy_rd_q_0__62_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(phy_rd[62]), + .Q(com_llm_llm_rx_top_llm_rx_demux_phy_rd_q_0_[62]) + ); + FD com_llm_llm_rx_top_llm_rx_demux_phy_rd_q_0__61_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(phy_rd[61]), + .Q(com_llm_llm_rx_top_llm_rx_demux_phy_rd_q_0_[61]) + ); + FDCE com_llm_llm_rx_top_llm_rx_demux_long_dllp_u_q ( + .CE(com_llm_llm_rx_top_llm_rx_demux_N_12838_i_1536), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_demux_long_dllp_u_q13), + .Q(com_llm_llm_rx_top_llm_rx_demux_long_dllp_u_q_1537), + .CLR(plm_link_up_i) + ); + FDPE com_llm_llm_rx_top_llm_rx_demux_tlp_vld_h_n_q ( + .PRE(plm_link_up_i), + .CE(com_llm_llm_rx_top_llm_rx_demux_N_12850_i_1540), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_demux_N_12810_i), + .Q(com_llm_llm_rx_top_llm_rx_demux_tlp_vld_h_n_q_1538) + ); + FDCE com_llm_llm_rx_top_llm_rx_demux_tlp_ip_flag ( + .CE(com_llm_llm_rx_top_llm_rx_demux_N_12820_i_i_1542), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_demux_N_69446_i_1539), + .Q(com_llm_llm_rx_top_llm_rx_demux_tlp_ip_flag_1543), + .CLR(plm_link_up_i) + ); + FDPE com_llm_llm_rx_top_llm_rx_demux_tlp_vld_l_n_q ( + .PRE(plm_link_up_i), + .CE(com_llm_llm_rx_top_llm_rx_demux_N_12850_i_1540), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_demux_N_9766_i), + .Q(com_llm_llm_rx_top_llm_rx_demux_tlp_vld_l_n_q_1541) + ); + INV com_llm_llm_rx_top_llm_rx_demux_rx_tlp_sof_n_i ( + .I(com_llm_llm_rx_top_rx_tlp_sof_n), + .O(com_llm_llm_rx_top_rx_tlp_sof_n_i) + ); + INV com_llm_llm_rx_top_llm_rx_demux_rx_tlp_eof_n_i ( + .I(com_llm_llm_rx_top_rx_tlp_eof_n), + .O(com_llm_llm_rx_top_rx_tlp_eof_n_i) + ); + INV com_llm_llm_rx_top_llm_rx_demux_N_12820_i_i ( + .I(com_llm_llm_rx_top_llm_rx_demux_N_12820_i), + .O(com_llm_llm_rx_top_llm_rx_demux_N_12820_i_i_1542) + ); + defparam com_llm_llm_rx_top_llm_rx_demux_tlp_ferr_h_n_q_9_0.INIT = 16'hDD0D; + LUT4_L com_llm_llm_rx_top_llm_rx_demux_tlp_ferr_h_n_q_9_0 ( + .I0(com_llm_llm_rx_top_llm_rx_demux_N_12822_i), + .I1(com_llm_llm_rx_top_llm_rx_demux_tlp_ferr_h_n_q_9_0_1_1544), + .I2(com_llm_llm_rx_top_llm_rx_demux_tlp_ip_flag_1543), + .I3(phy_rferr_h_n), + .LO(com_llm_llm_rx_top_llm_rx_demux_N_9763_i) + ); + defparam com_llm_llm_rx_top_llm_rx_demux_N_67762_i.INIT = 16'hEAF0; + LUT4_L com_llm_llm_rx_top_llm_rx_demux_N_67762_i ( + .I0(com_llm_llm_rx_top_llm_rx_demux_N_67772_1), + .I1(com_llm_llm_rx_top_llm_rx_demux_N_67762_i_1_1548), + .I2(com_llm_llm_rx_top_llm_rx_demux_tlp_eof_n_q_1547), + .I3(com_llm_llm_rx_top_llm_rx_demux_tlp_sof_n_q_and_tlp_ip_flag_1546), + .LO(com_llm_llm_rx_top_llm_rx_demux_N_67762_i_1545) + ); + VCC com_llm_llm_rx_top_llm_rx_dllp_crc_VCC ( + .P(com_llm_llm_rx_top_llm_rx_dllp_crc_VCC_1558) + ); + GND com_llm_llm_rx_top_llm_rx_dllp_crc_GND ( + .G(com_llm_llm_rx_top_llm_rx_dllp_crc_GND_1561) + ); + MUXCY_L com_llm_llm_rx_top_llm_rx_dllp_crc_crc16_ok_0_I_1 ( + .CI(com_llm_llm_rx_top_llm_rx_dllp_crc_VCC_1558), + .DI(com_llm_llm_rx_top_llm_rx_dllp_crc_GND_1561), + .LO(com_llm_llm_rx_top_llm_rx_dllp_crc_data_tmp[0]), + .S(com_llm_llm_rx_top_llm_rx_dllp_crc_N_59) + ); + MUXCY_L com_llm_llm_rx_top_llm_rx_dllp_crc_crc16_ok_0_I_10 ( + .CI(com_llm_llm_rx_top_llm_rx_dllp_crc_data_tmp[0]), + .DI(com_llm_llm_rx_top_llm_rx_dllp_crc_GND_1561), + .LO(com_llm_llm_rx_top_llm_rx_dllp_crc_data_tmp[1]), + .S(com_llm_llm_rx_top_llm_rx_dllp_crc_N_51) + ); + MUXCY_L com_llm_llm_rx_top_llm_rx_dllp_crc_crc16_ok_0_I_19 ( + .CI(com_llm_llm_rx_top_llm_rx_dllp_crc_data_tmp[1]), + .DI(com_llm_llm_rx_top_llm_rx_dllp_crc_GND_1561), + .LO(com_llm_llm_rx_top_llm_rx_dllp_crc_data_tmp[2]), + .S(com_llm_llm_rx_top_llm_rx_dllp_crc_N_43) + ); + MUXCY_L com_llm_llm_rx_top_llm_rx_dllp_crc_crc16_ok_0_I_28 ( + .CI(com_llm_llm_rx_top_llm_rx_dllp_crc_data_tmp[3]), + .DI(com_llm_llm_rx_top_llm_rx_dllp_crc_GND_1561), + .LO(com_llm_llm_rx_top_llm_rx_dllp_crc_data_tmp[4]), + .S(com_llm_llm_rx_top_llm_rx_dllp_crc_N_35) + ); + MUXCY_L com_llm_llm_rx_top_llm_rx_dllp_crc_crc16_ok_0_I_46 ( + .CI(com_llm_llm_rx_top_llm_rx_dllp_crc_data_tmp[4]), + .DI(com_llm_llm_rx_top_llm_rx_dllp_crc_GND_1561), + .LO(com_llm_llm_rx_top_llm_rx_dllp_crc_data_tmp[5]), + .S(com_llm_llm_rx_top_llm_rx_dllp_crc_N_19) + ); + MUXCY_L com_llm_llm_rx_top_llm_rx_dllp_crc_crc16_ok_0_I_55 ( + .CI(com_llm_llm_rx_top_llm_rx_dllp_crc_data_tmp[5]), + .DI(com_llm_llm_rx_top_llm_rx_dllp_crc_GND_1561), + .LO(com_llm_llm_rx_top_llm_rx_dllp_crc_data_tmp[6]), + .S(com_llm_llm_rx_top_llm_rx_dllp_crc_N_11) + ); + MUXCY_L com_llm_llm_rx_top_llm_rx_dllp_crc_crc16_ok_0_I_64 ( + .CI(com_llm_llm_rx_top_llm_rx_dllp_crc_data_tmp[2]), + .DI(com_llm_llm_rx_top_llm_rx_dllp_crc_GND_1561), + .LO(com_llm_llm_rx_top_llm_rx_dllp_crc_data_tmp[3]), + .S(com_llm_llm_rx_top_llm_rx_dllp_crc_N_3) + ); + MUXCY_L com_llm_llm_rx_top_llm_rx_dllp_crc_RX_DLLP_LOW_M1_2_cry_0 ( + .CI(com_llm_llm_rx_top_llm_rx_dllp_crc_GND_1561), + .DI(com_llm_llm_rx_top_llm_rx_dllp_crc_VCC_1558), + .LO(com_llm_llm_rx_top_llm_rx_dllp_crc_RX_DLLP_LOW_M1_2_cry_0_1549), + .S(N_57349_i_16) + ); + MUXCY_L com_llm_llm_rx_top_llm_rx_dllp_crc_RX_DLLP_LOW_M1_2_cry_1 ( + .CI(com_llm_llm_rx_top_llm_rx_dllp_crc_RX_DLLP_LOW_M1_2_cry_0_1549), + .DI(com_llm_llm_rx_top_llm_rx_dllp_crc_VCC_1558), + .LO(com_llm_llm_rx_top_llm_rx_dllp_crc_RX_DLLP_LOW_M1_2_cry_1_1550), + .S(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_dllp_d_i[1]) + ); + XORCY com_llm_llm_rx_top_llm_rx_dllp_crc_RX_DLLP_LOW_M1_2_s_1 ( + .CI(com_llm_llm_rx_top_llm_rx_dllp_crc_RX_DLLP_LOW_M1_2_cry_0_1549), + .LI(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_dllp_d_i[1]), + .O(com_llm_llm_rx_top_llm_rx_dllp_crc_RX_DLLP_LOW_M1_2[1]) + ); + MUXCY_L com_llm_llm_rx_top_llm_rx_dllp_crc_RX_DLLP_LOW_M1_2_cry_2 ( + .CI(com_llm_llm_rx_top_llm_rx_dllp_crc_RX_DLLP_LOW_M1_2_cry_1_1550), + .DI(com_llm_llm_rx_top_llm_rx_dllp_crc_VCC_1558), + .LO(com_llm_llm_rx_top_llm_rx_dllp_crc_RX_DLLP_LOW_M1_2_cry_2_1551), + .S(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_dllp_d_i[2]) + ); + XORCY com_llm_llm_rx_top_llm_rx_dllp_crc_RX_DLLP_LOW_M1_2_s_2 ( + .CI(com_llm_llm_rx_top_llm_rx_dllp_crc_RX_DLLP_LOW_M1_2_cry_1_1550), + .LI(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_dllp_d_i[2]), + .O(com_llm_llm_rx_top_llm_rx_dllp_crc_RX_DLLP_LOW_M1_2[2]) + ); + MUXCY_L com_llm_llm_rx_top_llm_rx_dllp_crc_RX_DLLP_LOW_M1_2_cry_3 ( + .CI(com_llm_llm_rx_top_llm_rx_dllp_crc_RX_DLLP_LOW_M1_2_cry_2_1551), + .DI(com_llm_llm_rx_top_llm_rx_dllp_crc_VCC_1558), + .LO(com_llm_llm_rx_top_llm_rx_dllp_crc_RX_DLLP_LOW_M1_2_cry_3_1552), + .S(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_dllp_d_i[3]) + ); + XORCY com_llm_llm_rx_top_llm_rx_dllp_crc_RX_DLLP_LOW_M1_2_s_3 ( + .CI(com_llm_llm_rx_top_llm_rx_dllp_crc_RX_DLLP_LOW_M1_2_cry_2_1551), + .LI(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_dllp_d_i[3]), + .O(com_llm_llm_rx_top_llm_rx_dllp_crc_RX_DLLP_LOW_M1_2[3]) + ); + MUXCY_L com_llm_llm_rx_top_llm_rx_dllp_crc_RX_DLLP_LOW_M1_2_cry_4 ( + .CI(com_llm_llm_rx_top_llm_rx_dllp_crc_RX_DLLP_LOW_M1_2_cry_3_1552), + .DI(com_llm_llm_rx_top_llm_rx_dllp_crc_VCC_1558), + .LO(com_llm_llm_rx_top_llm_rx_dllp_crc_RX_DLLP_LOW_M1_2_cry_4_1553), + .S(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_dllp_d_i[4]) + ); + XORCY com_llm_llm_rx_top_llm_rx_dllp_crc_RX_DLLP_LOW_M1_2_s_4 ( + .CI(com_llm_llm_rx_top_llm_rx_dllp_crc_RX_DLLP_LOW_M1_2_cry_3_1552), + .LI(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_dllp_d_i[4]), + .O(com_llm_llm_rx_top_llm_rx_dllp_crc_RX_DLLP_LOW_M1_2[4]) + ); + MUXCY_L com_llm_llm_rx_top_llm_rx_dllp_crc_RX_DLLP_LOW_M1_2_cry_5 ( + .CI(com_llm_llm_rx_top_llm_rx_dllp_crc_RX_DLLP_LOW_M1_2_cry_4_1553), + .DI(com_llm_llm_rx_top_llm_rx_dllp_crc_VCC_1558), + .LO(com_llm_llm_rx_top_llm_rx_dllp_crc_RX_DLLP_LOW_M1_2_cry_5_1554), + .S(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_dllp_d_i[5]) + ); + XORCY com_llm_llm_rx_top_llm_rx_dllp_crc_RX_DLLP_LOW_M1_2_s_5 ( + .CI(com_llm_llm_rx_top_llm_rx_dllp_crc_RX_DLLP_LOW_M1_2_cry_4_1553), + .LI(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_dllp_d_i[5]), + .O(com_llm_llm_rx_top_llm_rx_dllp_crc_RX_DLLP_LOW_M1_2[5]) + ); + MUXCY_L com_llm_llm_rx_top_llm_rx_dllp_crc_RX_DLLP_LOW_M1_2_cry_6 ( + .CI(com_llm_llm_rx_top_llm_rx_dllp_crc_RX_DLLP_LOW_M1_2_cry_5_1554), + .DI(com_llm_llm_rx_top_llm_rx_dllp_crc_VCC_1558), + .LO(com_llm_llm_rx_top_llm_rx_dllp_crc_RX_DLLP_LOW_M1_2_cry_6_1555), + .S(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_dllp_d_i[6]) + ); + XORCY com_llm_llm_rx_top_llm_rx_dllp_crc_RX_DLLP_LOW_M1_2_s_6 ( + .CI(com_llm_llm_rx_top_llm_rx_dllp_crc_RX_DLLP_LOW_M1_2_cry_5_1554), + .LI(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_dllp_d_i[6]), + .O(com_llm_llm_rx_top_llm_rx_dllp_crc_RX_DLLP_LOW_M1_2[6]) + ); + MUXCY_L com_llm_llm_rx_top_llm_rx_dllp_crc_RX_DLLP_LOW_M1_2_cry_7 ( + .CI(com_llm_llm_rx_top_llm_rx_dllp_crc_RX_DLLP_LOW_M1_2_cry_6_1555), + .DI(com_llm_llm_rx_top_llm_rx_dllp_crc_VCC_1558), + .LO(com_llm_llm_rx_top_llm_rx_dllp_crc_RX_DLLP_LOW_M1_2_cry_7_1556), + .S(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_dllp_d_i[7]) + ); + XORCY com_llm_llm_rx_top_llm_rx_dllp_crc_RX_DLLP_LOW_M1_2_s_7 ( + .CI(com_llm_llm_rx_top_llm_rx_dllp_crc_RX_DLLP_LOW_M1_2_cry_6_1555), + .LI(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_dllp_d_i[7]), + .O(com_llm_llm_rx_top_llm_rx_dllp_crc_RX_DLLP_LOW_M1_2[7]) + ); + MUXCY_L com_llm_llm_rx_top_llm_rx_dllp_crc_RX_DLLP_LOW_M1_2_cry_8 ( + .CI(com_llm_llm_rx_top_llm_rx_dllp_crc_RX_DLLP_LOW_M1_2_cry_7_1556), + .DI(com_llm_llm_rx_top_llm_rx_dllp_crc_VCC_1558), + .LO(com_llm_llm_rx_top_llm_rx_dllp_crc_RX_DLLP_LOW_M1_2_cry_8_1557), + .S(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_dllp_d_i[8]) + ); + XORCY com_llm_llm_rx_top_llm_rx_dllp_crc_RX_DLLP_LOW_M1_2_s_8 ( + .CI(com_llm_llm_rx_top_llm_rx_dllp_crc_RX_DLLP_LOW_M1_2_cry_7_1556), + .LI(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_dllp_d_i[8]), + .O(com_llm_llm_rx_top_llm_rx_dllp_crc_RX_DLLP_LOW_M1_2[8]) + ); + MUXCY_L com_llm_llm_rx_top_llm_rx_dllp_crc_RX_DLLP_LOW_M1_2_cry_9 ( + .CI(com_llm_llm_rx_top_llm_rx_dllp_crc_RX_DLLP_LOW_M1_2_cry_8_1557), + .DI(com_llm_llm_rx_top_llm_rx_dllp_crc_VCC_1558), + .LO(com_llm_llm_rx_top_llm_rx_dllp_crc_RX_DLLP_LOW_M1_2_cry_9_1559), + .S(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_dllp_d_i[9]) + ); + XORCY com_llm_llm_rx_top_llm_rx_dllp_crc_RX_DLLP_LOW_M1_2_s_9 ( + .CI(com_llm_llm_rx_top_llm_rx_dllp_crc_RX_DLLP_LOW_M1_2_cry_8_1557), + .LI(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_dllp_d_i[9]), + .O(com_llm_llm_rx_top_llm_rx_dllp_crc_RX_DLLP_LOW_M1_2[9]) + ); + MUXCY_L com_llm_llm_rx_top_llm_rx_dllp_crc_RX_DLLP_LOW_M1_2_cry_10 ( + .CI(com_llm_llm_rx_top_llm_rx_dllp_crc_RX_DLLP_LOW_M1_2_cry_9_1559), + .DI(com_llm_llm_rx_top_llm_rx_dllp_crc_VCC_1558), + .LO(com_llm_llm_rx_top_llm_rx_dllp_crc_RX_DLLP_LOW_M1_2_cry_10_1560), + .S(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_dllp_d_i[10]) + ); + XORCY com_llm_llm_rx_top_llm_rx_dllp_crc_RX_DLLP_LOW_M1_2_s_10 ( + .CI(com_llm_llm_rx_top_llm_rx_dllp_crc_RX_DLLP_LOW_M1_2_cry_9_1559), + .LI(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_dllp_d_i[10]), + .O(com_llm_llm_rx_top_llm_rx_dllp_crc_RX_DLLP_LOW_M1_2[10]) + ); + XORCY com_llm_llm_rx_top_llm_rx_dllp_crc_RX_DLLP_LOW_M1_2_s_11 ( + .CI(com_llm_llm_rx_top_llm_rx_dllp_crc_RX_DLLP_LOW_M1_2_cry_10_1560), + .LI(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_dllp_d_i[11]), + .O(com_llm_llm_rx_top_llm_rx_dllp_crc_RX_DLLP_LOW_M1_2[11]) + ); + defparam com_llm_llm_rx_top_llm_rx_dllp_crc_un1_crc16_ok_0_15_.INIT = 8'hCA; + LUT3 com_llm_llm_rx_top_llm_rx_dllp_crc_un1_crc16_ok_0_15_ ( + .I0(com_llm_llm_rx_top_llm_rx_dllp_crc_crc16_d32_nst[8]), + .I1(com_llm_llm_rx_top_llm_rx_dllp_crc_crc16_d32_st[8]), + .I2(com_llm_llm_rx_top_llm_rx_dllp_crc_fr_straddle_q_1564), + .O(com_llm_llm_rx_top_llm_rx_dllp_crc_un1_crc16_ok_0[15]) + ); + defparam com_llm_llm_rx_top_llm_rx_dllp_crc_un1_crc16_ok_0_14_.INIT = 8'hCA; + LUT3 com_llm_llm_rx_top_llm_rx_dllp_crc_un1_crc16_ok_0_14_ ( + .I0(com_llm_llm_rx_top_llm_rx_dllp_crc_crc16_d32_nst[9]), + .I1(com_llm_llm_rx_top_llm_rx_dllp_crc_crc16_d32_st[9]), + .I2(com_llm_llm_rx_top_llm_rx_dllp_crc_fr_straddle_q_1564), + .O(com_llm_llm_rx_top_llm_rx_dllp_crc_un1_crc16_ok_0[14]) + ); + defparam com_llm_llm_rx_top_llm_rx_dllp_crc_un1_crc16_ok_0_13_.INIT = 8'hCA; + LUT3 com_llm_llm_rx_top_llm_rx_dllp_crc_un1_crc16_ok_0_13_ ( + .I0(com_llm_llm_rx_top_llm_rx_dllp_crc_crc16_d32_nst[10]), + .I1(com_llm_llm_rx_top_llm_rx_dllp_crc_crc16_d32_st[10]), + .I2(com_llm_llm_rx_top_llm_rx_dllp_crc_fr_straddle_q_1564), + .O(com_llm_llm_rx_top_llm_rx_dllp_crc_un1_crc16_ok_0[13]) + ); + defparam com_llm_llm_rx_top_llm_rx_dllp_crc_un1_crc16_ok_0_12_.INIT = 8'hCA; + LUT3 com_llm_llm_rx_top_llm_rx_dllp_crc_un1_crc16_ok_0_12_ ( + .I0(com_llm_llm_rx_top_llm_rx_dllp_crc_crc16_d32_nst[11]), + .I1(com_llm_llm_rx_top_llm_rx_dllp_crc_crc16_d32_st[11]), + .I2(com_llm_llm_rx_top_llm_rx_dllp_crc_fr_straddle_q_1564), + .O(com_llm_llm_rx_top_llm_rx_dllp_crc_un1_crc16_ok_0[12]) + ); + defparam com_llm_llm_rx_top_llm_rx_dllp_crc_un1_crc16_ok_0_11_.INIT = 8'hCA; + LUT3 com_llm_llm_rx_top_llm_rx_dllp_crc_un1_crc16_ok_0_11_ ( + .I0(com_llm_llm_rx_top_llm_rx_dllp_crc_crc16_d32_nst[12]), + .I1(com_llm_llm_rx_top_llm_rx_dllp_crc_crc16_d32_st[12]), + .I2(com_llm_llm_rx_top_llm_rx_dllp_crc_fr_straddle_q_1564), + .O(com_llm_llm_rx_top_llm_rx_dllp_crc_un1_crc16_ok_0[11]) + ); + defparam com_llm_llm_rx_top_llm_rx_dllp_crc_un1_crc16_ok_0_10_.INIT = 8'hCA; + LUT3 com_llm_llm_rx_top_llm_rx_dllp_crc_un1_crc16_ok_0_10_ ( + .I0(com_llm_llm_rx_top_llm_rx_dllp_crc_crc16_d32_nst[13]), + .I1(com_llm_llm_rx_top_llm_rx_dllp_crc_crc16_d32_st[13]), + .I2(com_llm_llm_rx_top_llm_rx_dllp_crc_fr_straddle_q_1564), + .O(com_llm_llm_rx_top_llm_rx_dllp_crc_un1_crc16_ok_0[10]) + ); + defparam com_llm_llm_rx_top_llm_rx_dllp_crc_un1_crc16_ok_0_9_.INIT = 8'hCA; + LUT3 com_llm_llm_rx_top_llm_rx_dllp_crc_un1_crc16_ok_0_9_ ( + .I0(com_llm_llm_rx_top_llm_rx_dllp_crc_crc16_d32_nst[14]), + .I1(com_llm_llm_rx_top_llm_rx_dllp_crc_crc16_d32_st[14]), + .I2(com_llm_llm_rx_top_llm_rx_dllp_crc_fr_straddle_q_1564), + .O(com_llm_llm_rx_top_llm_rx_dllp_crc_un1_crc16_ok_0[9]) + ); + defparam com_llm_llm_rx_top_llm_rx_dllp_crc_un1_crc16_ok_0_8_.INIT = 8'hCA; + LUT3 com_llm_llm_rx_top_llm_rx_dllp_crc_un1_crc16_ok_0_8_ ( + .I0(com_llm_llm_rx_top_llm_rx_dllp_crc_crc16_d32_nst[15]), + .I1(com_llm_llm_rx_top_llm_rx_dllp_crc_crc16_d32_st[15]), + .I2(com_llm_llm_rx_top_llm_rx_dllp_crc_fr_straddle_q_1564), + .O(com_llm_llm_rx_top_llm_rx_dllp_crc_un1_crc16_ok_0[8]) + ); + defparam com_llm_llm_rx_top_llm_rx_dllp_crc_un1_crc16_ok_0_7_.INIT = 8'hCA; + LUT3 com_llm_llm_rx_top_llm_rx_dllp_crc_un1_crc16_ok_0_7_ ( + .I0(com_llm_llm_rx_top_llm_rx_dllp_crc_crc16_d32_nst[0]), + .I1(com_llm_llm_rx_top_llm_rx_dllp_crc_crc16_d32_st[0]), + .I2(com_llm_llm_rx_top_llm_rx_dllp_crc_fr_straddle_q_1564), + .O(com_llm_llm_rx_top_llm_rx_dllp_crc_un1_crc16_ok_0[7]) + ); + defparam com_llm_llm_rx_top_llm_rx_dllp_crc_un1_crc16_ok_0_6_.INIT = 8'hCA; + LUT3 com_llm_llm_rx_top_llm_rx_dllp_crc_un1_crc16_ok_0_6_ ( + .I0(com_llm_llm_rx_top_llm_rx_dllp_crc_crc16_d32_nst[1]), + .I1(com_llm_llm_rx_top_llm_rx_dllp_crc_crc16_d32_st[1]), + .I2(com_llm_llm_rx_top_llm_rx_dllp_crc_fr_straddle_q_1564), + .O(com_llm_llm_rx_top_llm_rx_dllp_crc_un1_crc16_ok_0[6]) + ); + defparam com_llm_llm_rx_top_llm_rx_dllp_crc_un1_crc16_ok_0_5_.INIT = 8'hCA; + LUT3 com_llm_llm_rx_top_llm_rx_dllp_crc_un1_crc16_ok_0_5_ ( + .I0(com_llm_llm_rx_top_llm_rx_dllp_crc_crc16_d32_nst[2]), + .I1(com_llm_llm_rx_top_llm_rx_dllp_crc_crc16_d32_st[2]), + .I2(com_llm_llm_rx_top_llm_rx_dllp_crc_fr_straddle_q_1564), + .O(com_llm_llm_rx_top_llm_rx_dllp_crc_un1_crc16_ok_0[5]) + ); + defparam com_llm_llm_rx_top_llm_rx_dllp_crc_un1_crc16_ok_0_4_.INIT = 8'hCA; + LUT3 com_llm_llm_rx_top_llm_rx_dllp_crc_un1_crc16_ok_0_4_ ( + .I0(com_llm_llm_rx_top_llm_rx_dllp_crc_crc16_d32_nst[3]), + .I1(com_llm_llm_rx_top_llm_rx_dllp_crc_crc16_d32_st[3]), + .I2(com_llm_llm_rx_top_llm_rx_dllp_crc_fr_straddle_q_1564), + .O(com_llm_llm_rx_top_llm_rx_dllp_crc_un1_crc16_ok_0[4]) + ); + defparam com_llm_llm_rx_top_llm_rx_dllp_crc_un1_crc16_ok_0_3_.INIT = 8'hCA; + LUT3 com_llm_llm_rx_top_llm_rx_dllp_crc_un1_crc16_ok_0_3_ ( + .I0(com_llm_llm_rx_top_llm_rx_dllp_crc_crc16_d32_nst[4]), + .I1(com_llm_llm_rx_top_llm_rx_dllp_crc_crc16_d32_st[4]), + .I2(com_llm_llm_rx_top_llm_rx_dllp_crc_fr_straddle_q_1564), + .O(com_llm_llm_rx_top_llm_rx_dllp_crc_un1_crc16_ok_0[3]) + ); + defparam com_llm_llm_rx_top_llm_rx_dllp_crc_un1_crc16_ok_0_2_.INIT = 8'hCA; + LUT3 com_llm_llm_rx_top_llm_rx_dllp_crc_un1_crc16_ok_0_2_ ( + .I0(com_llm_llm_rx_top_llm_rx_dllp_crc_crc16_d32_nst[5]), + .I1(com_llm_llm_rx_top_llm_rx_dllp_crc_crc16_d32_st[5]), + .I2(com_llm_llm_rx_top_llm_rx_dllp_crc_fr_straddle_q_1564), + .O(com_llm_llm_rx_top_llm_rx_dllp_crc_un1_crc16_ok_0[2]) + ); + defparam com_llm_llm_rx_top_llm_rx_dllp_crc_un1_crc16_ok_0_1_.INIT = 8'hCA; + LUT3 com_llm_llm_rx_top_llm_rx_dllp_crc_un1_crc16_ok_0_1_ ( + .I0(com_llm_llm_rx_top_llm_rx_dllp_crc_crc16_d32_nst[6]), + .I1(com_llm_llm_rx_top_llm_rx_dllp_crc_crc16_d32_st[6]), + .I2(com_llm_llm_rx_top_llm_rx_dllp_crc_fr_straddle_q_1564), + .O(com_llm_llm_rx_top_llm_rx_dllp_crc_un1_crc16_ok_0[1]) + ); + defparam com_llm_llm_rx_top_llm_rx_dllp_crc_un1_crc16_ok_0_0_.INIT = 8'hCA; + LUT3 com_llm_llm_rx_top_llm_rx_dllp_crc_un1_crc16_ok_0_0_ ( + .I0(com_llm_llm_rx_top_llm_rx_dllp_crc_crc16_d32_nst[7]), + .I1(com_llm_llm_rx_top_llm_rx_dllp_crc_crc16_d32_st[7]), + .I2(com_llm_llm_rx_top_llm_rx_dllp_crc_fr_straddle_q_1564), + .O(com_llm_llm_rx_top_llm_rx_dllp_crc_un1_crc16_ok_0[0]) + ); + defparam com_llm_llm_rx_top_llm_rx_dllp_crc_N_68799_i.INIT = 16'h0C32; + LUT4 com_llm_llm_rx_top_llm_rx_dllp_crc_N_68799_i ( + .I0(com_llm_llm_rx_top_llm_rx_dllp_crc_fr_straddle_1623), + .I1(com_llm_llm_rx_top_rx_dllp_eof_n), + .I2(com_llm_llm_rx_top_rx_dllp_sof_n), + .I3(com_llm_llm_rx_top_rx_dllp_vld_h_n), + .O(com_llm_llm_rx_top_llm_rx_dllp_crc_N_68799_i_1622) + ); + defparam com_llm_llm_rx_top_llm_rx_dllp_crc_str_dllp_0_a2_0_a2.INIT = 4'h2; + LUT2_L com_llm_llm_rx_top_llm_rx_dllp_crc_str_dllp_0_a2_0_a2 ( + .I0(com_llm_llm_rx_top_llm_rx_dllp_crc_fr_straddle_1623), + .I1(com_llm_llm_rx_top_rx_dllp_eof_n), + .LO(com_llm_llm_rx_top_llm_rx_dllp_crc_str_dllp) + ); + defparam com_llm_llm_rx_top_llm_rx_dllp_crc_reg_dllp_0_a2.INIT = 4'h1; + LUT2_L com_llm_llm_rx_top_llm_rx_dllp_crc_reg_dllp_0_a2 ( + .I0(com_llm_llm_rx_top_llm_rx_dllp_crc_fr_straddle_1623), + .I1(com_llm_llm_rx_top_rx_dllp_eof_n), + .LO(com_llm_llm_rx_top_llm_rx_dllp_crc_reg_dllp) + ); + defparam com_llm_llm_rx_top_llm_rx_dllp_crc_N_23323_i.INIT = 8'hAB; + LUT3_L com_llm_llm_rx_top_llm_rx_dllp_crc_N_23323_i ( + .I0(com_llm_llm_rx_top_llm_rx_dllp_crc_crc16_ok), + .I1(com_llm_llm_rx_top_llm_rx_dllp_crc_reg_dllp_qq_1566), + .I2(com_llm_llm_rx_top_llm_rx_dllp_crc_str_dllp_q_1562), + .LO(com_llm_llm_rx_top_llm_rx_dllp_crc_N_23323_i_1563) + ); + defparam com_llm_llm_rx_top_llm_rx_dllp_crc_RX_DLLP_VLD_5_0_a2.INIT = 8'hA8; + LUT3_L com_llm_llm_rx_top_llm_rx_dllp_crc_RX_DLLP_VLD_5_0_a2 ( + .I0(com_llm_llm_rx_top_llm_rx_dllp_crc_crc16_ok), + .I1(com_llm_llm_rx_top_llm_rx_dllp_crc_reg_dllp_qq_1566), + .I2(com_llm_llm_rx_top_llm_rx_dllp_crc_str_dllp_q_1562), + .LO(com_llm_llm_rx_top_llm_rx_dllp_crc_RX_DLLP_VLD_5) + ); + defparam com_llm_llm_rx_top_llm_rx_dllp_crc_rx_dllp_d_i_8_.INIT = 4'h1; + LUT1_L com_llm_llm_rx_top_llm_rx_dllp_crc_rx_dllp_d_i_8_ ( + .I0(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_dllp_d_8__1614), + .LO(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_dllp_d_i[8]) + ); + defparam com_llm_llm_rx_top_llm_rx_dllp_crc_rx_dllp_d_i_7_.INIT = 4'h1; + LUT1_L com_llm_llm_rx_top_llm_rx_dllp_crc_rx_dllp_d_i_7_ ( + .I0(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_dllp_d_7__1615), + .LO(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_dllp_d_i[7]) + ); + defparam com_llm_llm_rx_top_llm_rx_dllp_crc_rx_dllp_d_i_6_.INIT = 4'h1; + LUT1_L com_llm_llm_rx_top_llm_rx_dllp_crc_rx_dllp_d_i_6_ ( + .I0(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_dllp_d_6__1595), + .LO(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_dllp_d_i[6]) + ); + defparam com_llm_llm_rx_top_llm_rx_dllp_crc_rx_dllp_d_i_5_.INIT = 4'h1; + LUT1_L com_llm_llm_rx_top_llm_rx_dllp_crc_rx_dllp_d_i_5_ ( + .I0(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_dllp_d_5__1596), + .LO(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_dllp_d_i[5]) + ); + defparam com_llm_llm_rx_top_llm_rx_dllp_crc_rx_dllp_d_i_4_.INIT = 4'h1; + LUT1_L com_llm_llm_rx_top_llm_rx_dllp_crc_rx_dllp_d_i_4_ ( + .I0(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_dllp_d_4__1597), + .LO(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_dllp_d_i[4]) + ); + defparam com_llm_llm_rx_top_llm_rx_dllp_crc_rx_dllp_d_i_3_.INIT = 4'h1; + LUT1_L com_llm_llm_rx_top_llm_rx_dllp_crc_rx_dllp_d_i_3_ ( + .I0(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_dllp_d_3__1598), + .LO(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_dllp_d_i[3]) + ); + defparam com_llm_llm_rx_top_llm_rx_dllp_crc_rx_dllp_d_i_2_.INIT = 4'h1; + LUT1_L com_llm_llm_rx_top_llm_rx_dllp_crc_rx_dllp_d_i_2_ ( + .I0(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_dllp_d_2__1599), + .LO(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_dllp_d_i[2]) + ); + defparam com_llm_llm_rx_top_llm_rx_dllp_crc_rx_dllp_d_i_1_.INIT = 4'h1; + LUT1_L com_llm_llm_rx_top_llm_rx_dllp_crc_rx_dllp_d_i_1_ ( + .I0(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_dllp_d_1__1600), + .LO(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_dllp_d_i[1]) + ); + defparam com_llm_llm_rx_top_llm_rx_dllp_crc_rx_dllp_d_i_11_.INIT = 4'h1; + LUT1_L com_llm_llm_rx_top_llm_rx_dllp_crc_rx_dllp_d_i_11_ ( + .I0(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_dllp_d_11__1611), + .LO(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_dllp_d_i[11]) + ); + defparam com_llm_llm_rx_top_llm_rx_dllp_crc_rx_dllp_d_i_10_.INIT = 4'h1; + LUT1_L com_llm_llm_rx_top_llm_rx_dllp_crc_rx_dllp_d_i_10_ ( + .I0(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_dllp_d_10__1612), + .LO(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_dllp_d_i[10]) + ); + defparam com_llm_llm_rx_top_llm_rx_dllp_crc_rx_dllp_d_i_9_.INIT = 4'h1; + LUT1_L com_llm_llm_rx_top_llm_rx_dllp_crc_rx_dllp_d_i_9_ ( + .I0(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_dllp_d_9__1613), + .LO(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_dllp_d_i[9]) + ); + defparam com_llm_llm_rx_top_llm_rx_dllp_crc_crc16_ori_4_i_m2_i_m3_0_3_.INIT = 8'hE4; + LUT3_L com_llm_llm_rx_top_llm_rx_dllp_crc_crc16_ori_4_i_m2_i_m3_0_3_ ( + .I0(com_llm_llm_rx_top_llm_rx_dllp_crc_fr_straddle_1623), + .I1(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_11_), + .I2(com_llm_llm_rx_top_rx_data_43_), + .LO(com_llm_llm_rx_top_llm_rx_dllp_crc_crc16_ori_4_i_m2_i_m3_0_3__1567) + ); + defparam com_llm_llm_rx_top_llm_rx_dllp_crc_crc16_ori_4_i_m2_i_m3_0_2_.INIT = 8'hE4; + LUT3_L com_llm_llm_rx_top_llm_rx_dllp_crc_crc16_ori_4_i_m2_i_m3_0_2_ ( + .I0(com_llm_llm_rx_top_llm_rx_dllp_crc_fr_straddle_1623), + .I1(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_10_), + .I2(com_llm_llm_rx_top_rx_data_42_), + .LO(com_llm_llm_rx_top_llm_rx_dllp_crc_crc16_ori_4_i_m2_i_m3_0_2__1568) + ); + defparam com_llm_llm_rx_top_llm_rx_dllp_crc_crc16_ori_4_i_m2_i_m3_0_1_.INIT = 8'hE4; + LUT3_L com_llm_llm_rx_top_llm_rx_dllp_crc_crc16_ori_4_i_m2_i_m3_0_1_ ( + .I0(com_llm_llm_rx_top_llm_rx_dllp_crc_fr_straddle_1623), + .I1(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_9_), + .I2(com_llm_llm_rx_top_rx_data_41_), + .LO(com_llm_llm_rx_top_llm_rx_dllp_crc_crc16_ori_4_i_m2_i_m3_0_1__1569) + ); + defparam com_llm_llm_rx_top_llm_rx_dllp_crc_crc16_ori_4_i_m2_i_m3_0_0_.INIT = 8'hE4; + LUT3_L com_llm_llm_rx_top_llm_rx_dllp_crc_crc16_ori_4_i_m2_i_m3_0_0_ ( + .I0(com_llm_llm_rx_top_llm_rx_dllp_crc_fr_straddle_1623), + .I1(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_8_), + .I2(com_llm_llm_rx_top_rx_data_40_), + .LO(com_llm_llm_rx_top_llm_rx_dllp_crc_crc16_ori_4_i_m2_i_m3_0_0__1570) + ); + defparam com_llm_llm_rx_top_llm_rx_dllp_crc_crc16_ori_4_i_m3_0_15_.INIT = 8'hE4; + LUT3_L com_llm_llm_rx_top_llm_rx_dllp_crc_crc16_ori_4_i_m3_0_15_ ( + .I0(com_llm_llm_rx_top_llm_rx_dllp_crc_fr_straddle_1623), + .I1(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_23_), + .I2(com_llm_llm_rx_top_rx_data_55_), + .LO(com_llm_llm_rx_top_llm_rx_dllp_crc_crc16_ori_4_i_m3_0_15__1571) + ); + defparam com_llm_llm_rx_top_llm_rx_dllp_crc_crc16_ori_4_i_m2_i_m3_0_14_.INIT = 8'hE4; + LUT3_L com_llm_llm_rx_top_llm_rx_dllp_crc_crc16_ori_4_i_m2_i_m3_0_14_ ( + .I0(com_llm_llm_rx_top_llm_rx_dllp_crc_fr_straddle_1623), + .I1(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_22_), + .I2(com_llm_llm_rx_top_rx_data_54_), + .LO(com_llm_llm_rx_top_llm_rx_dllp_crc_crc16_ori_4_i_m2_i_m3_0_14__1572) + ); + defparam com_llm_llm_rx_top_llm_rx_dllp_crc_crc16_ori_4_i_m2_i_m3_0_13_.INIT = 8'hE4; + LUT3_L com_llm_llm_rx_top_llm_rx_dllp_crc_crc16_ori_4_i_m2_i_m3_0_13_ ( + .I0(com_llm_llm_rx_top_llm_rx_dllp_crc_fr_straddle_1623), + .I1(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_21_), + .I2(com_llm_llm_rx_top_rx_data_53_), + .LO(com_llm_llm_rx_top_llm_rx_dllp_crc_crc16_ori_4_i_m2_i_m3_0_13__1573) + ); + defparam com_llm_llm_rx_top_llm_rx_dllp_crc_crc16_ori_4_i_m2_i_m3_0_12_.INIT = 8'hE4; + LUT3_L com_llm_llm_rx_top_llm_rx_dllp_crc_crc16_ori_4_i_m2_i_m3_0_12_ ( + .I0(com_llm_llm_rx_top_llm_rx_dllp_crc_fr_straddle_1623), + .I1(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_20_), + .I2(com_llm_llm_rx_top_rx_data_52_), + .LO(com_llm_llm_rx_top_llm_rx_dllp_crc_crc16_ori_4_i_m2_i_m3_0_12__1574) + ); + defparam com_llm_llm_rx_top_llm_rx_dllp_crc_crc16_ori_4_i_m3_0_11_.INIT = 8'hE4; + LUT3_L com_llm_llm_rx_top_llm_rx_dllp_crc_crc16_ori_4_i_m3_0_11_ ( + .I0(com_llm_llm_rx_top_llm_rx_dllp_crc_fr_straddle_1623), + .I1(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_19_), + .I2(com_llm_llm_rx_top_rx_data_51_), + .LO(com_llm_llm_rx_top_llm_rx_dllp_crc_crc16_ori_4_i_m3_0_11__1575) + ); + defparam com_llm_llm_rx_top_llm_rx_dllp_crc_crc16_ori_4_i_m3_0_10_.INIT = 8'hE4; + LUT3_L com_llm_llm_rx_top_llm_rx_dllp_crc_crc16_ori_4_i_m3_0_10_ ( + .I0(com_llm_llm_rx_top_llm_rx_dllp_crc_fr_straddle_1623), + .I1(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_18_), + .I2(com_llm_llm_rx_top_rx_data_50_), + .LO(com_llm_llm_rx_top_llm_rx_dllp_crc_crc16_ori_4_i_m3_0_10__1576) + ); + defparam com_llm_llm_rx_top_llm_rx_dllp_crc_crc16_ori_4_i_m3_0_9_.INIT = 8'hE4; + LUT3_L com_llm_llm_rx_top_llm_rx_dllp_crc_crc16_ori_4_i_m3_0_9_ ( + .I0(com_llm_llm_rx_top_llm_rx_dllp_crc_fr_straddle_1623), + .I1(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_17_), + .I2(com_llm_llm_rx_top_rx_data_49_), + .LO(com_llm_llm_rx_top_llm_rx_dllp_crc_crc16_ori_4_i_m3_0_9__1577) + ); + defparam com_llm_llm_rx_top_llm_rx_dllp_crc_crc16_ori_4_i_m3_0_8_.INIT = 8'hE4; + LUT3_L com_llm_llm_rx_top_llm_rx_dllp_crc_crc16_ori_4_i_m3_0_8_ ( + .I0(com_llm_llm_rx_top_llm_rx_dllp_crc_fr_straddle_1623), + .I1(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_16_), + .I2(com_llm_llm_rx_top_rx_data_48_), + .LO(com_llm_llm_rx_top_llm_rx_dllp_crc_crc16_ori_4_i_m3_0_8__1578) + ); + defparam com_llm_llm_rx_top_llm_rx_dllp_crc_crc16_ori_4_i_m3_0_7_.INIT = 8'hE4; + LUT3_L com_llm_llm_rx_top_llm_rx_dllp_crc_crc16_ori_4_i_m3_0_7_ ( + .I0(com_llm_llm_rx_top_llm_rx_dllp_crc_fr_straddle_1623), + .I1(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_15_), + .I2(com_llm_llm_rx_top_rx_data_47_), + .LO(com_llm_llm_rx_top_llm_rx_dllp_crc_crc16_ori_4_i_m3_0_7__1579) + ); + defparam com_llm_llm_rx_top_llm_rx_dllp_crc_crc16_ori_4_i_m3_0_6_.INIT = 8'hE4; + LUT3_L com_llm_llm_rx_top_llm_rx_dllp_crc_crc16_ori_4_i_m3_0_6_ ( + .I0(com_llm_llm_rx_top_llm_rx_dllp_crc_fr_straddle_1623), + .I1(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_14_), + .I2(com_llm_llm_rx_top_rx_data_46_), + .LO(com_llm_llm_rx_top_llm_rx_dllp_crc_crc16_ori_4_i_m3_0_6__1580) + ); + defparam com_llm_llm_rx_top_llm_rx_dllp_crc_crc16_ori_4_i_m3_0_5_.INIT = 8'hE4; + LUT3_L com_llm_llm_rx_top_llm_rx_dllp_crc_crc16_ori_4_i_m3_0_5_ ( + .I0(com_llm_llm_rx_top_llm_rx_dllp_crc_fr_straddle_1623), + .I1(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_13_), + .I2(com_llm_llm_rx_top_rx_data_45_), + .LO(com_llm_llm_rx_top_llm_rx_dllp_crc_crc16_ori_4_i_m3_0_5__1581) + ); + defparam com_llm_llm_rx_top_llm_rx_dllp_crc_crc16_ori_4_i_m2_i_m3_0_4_.INIT = 8'hE4; + LUT3_L com_llm_llm_rx_top_llm_rx_dllp_crc_crc16_ori_4_i_m2_i_m3_0_4_ ( + .I0(com_llm_llm_rx_top_llm_rx_dllp_crc_fr_straddle_1623), + .I1(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_12_), + .I2(com_llm_llm_rx_top_rx_data_44_), + .LO(com_llm_llm_rx_top_llm_rx_dllp_crc_crc16_ori_4_i_m2_i_m3_0_4__1582) + ); + defparam com_llm_llm_rx_top_llm_rx_dllp_crc_rx_dllp_d_4_i_m3_0_4_.INIT = 8'hE4; + LUT3_L com_llm_llm_rx_top_llm_rx_dllp_crc_rx_dllp_d_4_i_m3_0_4_ ( + .I0(com_llm_llm_rx_top_llm_rx_dllp_crc_fr_straddle_1623), + .I1(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q[28]), + .I2(com_llm_llm_rx_top_rx_data_60_), + .LO(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_dllp_d_4_i_m3_0_4__1583) + ); + defparam com_llm_llm_rx_top_llm_rx_dllp_crc_rx_dllp_d_4_i_m2_i_m3_0_3_.INIT = 8'hE4; + LUT3_L com_llm_llm_rx_top_llm_rx_dllp_crc_rx_dllp_d_4_i_m2_i_m3_0_3_ ( + .I0(com_llm_llm_rx_top_llm_rx_dllp_crc_fr_straddle_1623), + .I1(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_27_), + .I2(com_llm_llm_rx_top_rx_data_59_), + .LO(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_dllp_d_4_i_m2_i_m3_0_3__1584) + ); + defparam com_llm_llm_rx_top_llm_rx_dllp_crc_rx_dllp_d_4_i_m3_0_2_.INIT = 8'hE4; + LUT3_L com_llm_llm_rx_top_llm_rx_dllp_crc_rx_dllp_d_4_i_m3_0_2_ ( + .I0(com_llm_llm_rx_top_llm_rx_dllp_crc_fr_straddle_1623), + .I1(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_26_), + .I2(com_llm_llm_rx_top_rx_data_58_), + .LO(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_dllp_d_4_i_m3_0_2__1585) + ); + defparam com_llm_llm_rx_top_llm_rx_dllp_crc_rx_dllp_d_4_i_m3_0_1_.INIT = 8'hE4; + LUT3_L com_llm_llm_rx_top_llm_rx_dllp_crc_rx_dllp_d_4_i_m3_0_1_ ( + .I0(com_llm_llm_rx_top_llm_rx_dllp_crc_fr_straddle_1623), + .I1(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_25_), + .I2(com_llm_llm_rx_top_rx_data_57_), + .LO(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_dllp_d_4_i_m3_0_1__1586) + ); + defparam com_llm_llm_rx_top_llm_rx_dllp_crc_rx_dllp_d_4_i_m3_0_0_.INIT = 8'hE4; + LUT3_L com_llm_llm_rx_top_llm_rx_dllp_crc_rx_dllp_d_4_i_m3_0_0_ ( + .I0(com_llm_llm_rx_top_llm_rx_dllp_crc_fr_straddle_1623), + .I1(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_24_), + .I2(com_llm_llm_rx_top_rx_data_56_), + .LO(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_dllp_d_4_i_m3_0_0__1587) + ); + defparam com_llm_llm_rx_top_llm_rx_dllp_crc_rx_dllp_d_4_i_m3_0_21_.INIT = 8'hD8; + LUT3_L com_llm_llm_rx_top_llm_rx_dllp_crc_rx_dllp_d_4_i_m3_0_21_ ( + .I0(com_llm_llm_rx_top_llm_rx_dllp_crc_fr_straddle_1623), + .I1(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_13_), + .I2(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_45_), + .LO(com_llm_llm_rx_top_rx_dllp_d_4_i_m3_0_21_) + ); + defparam com_llm_llm_rx_top_llm_rx_dllp_crc_rx_dllp_d_4_i_m2_i_m3_0_20_.INIT = 8'hD8; + LUT3_L com_llm_llm_rx_top_llm_rx_dllp_crc_rx_dllp_d_4_i_m2_i_m3_0_20_ ( + .I0(com_llm_llm_rx_top_llm_rx_dllp_crc_fr_straddle_1623), + .I1(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_12_), + .I2(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_44_), + .LO(com_llm_llm_rx_top_rx_dllp_d_4_i_m2_i_m3_0[20]) + ); + defparam com_llm_llm_rx_top_llm_rx_dllp_crc_rx_dllp_d_4_i_m2_i_m3_0_19_.INIT = 8'hD8; + LUT3_L com_llm_llm_rx_top_llm_rx_dllp_crc_rx_dllp_d_4_i_m2_i_m3_0_19_ ( + .I0(com_llm_llm_rx_top_llm_rx_dllp_crc_fr_straddle_1623), + .I1(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_11_), + .I2(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_43_), + .LO(com_llm_llm_rx_top_rx_dllp_d_4_i_m2_i_m3_0[19]) + ); + defparam com_llm_llm_rx_top_llm_rx_dllp_crc_rx_dllp_d_4_i_m2_i_m3_0_18_.INIT = 8'hD8; + LUT3_L com_llm_llm_rx_top_llm_rx_dllp_crc_rx_dllp_d_4_i_m2_i_m3_0_18_ ( + .I0(com_llm_llm_rx_top_llm_rx_dllp_crc_fr_straddle_1623), + .I1(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_10_), + .I2(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_42_), + .LO(com_llm_llm_rx_top_rx_dllp_d_4_i_m2_i_m3_0[18]) + ); + defparam com_llm_llm_rx_top_llm_rx_dllp_crc_rx_dllp_d_4_i_m2_i_m3_0_17_.INIT = 8'hD8; + LUT3_L com_llm_llm_rx_top_llm_rx_dllp_crc_rx_dllp_d_4_i_m2_i_m3_0_17_ ( + .I0(com_llm_llm_rx_top_llm_rx_dllp_crc_fr_straddle_1623), + .I1(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_9_), + .I2(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_41_), + .LO(com_llm_llm_rx_top_rx_dllp_d_4_i_m2_i_m3_0[17]) + ); + defparam com_llm_llm_rx_top_llm_rx_dllp_crc_rx_dllp_d_4_i_m2_i_m3_0_16_.INIT = 8'hD8; + LUT3_L com_llm_llm_rx_top_llm_rx_dllp_crc_rx_dllp_d_4_i_m2_i_m3_0_16_ ( + .I0(com_llm_llm_rx_top_llm_rx_dllp_crc_fr_straddle_1623), + .I1(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_8_), + .I2(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_40_), + .LO(com_llm_llm_rx_top_rx_dllp_d_4_i_m2_i_m3_0[16]) + ); + defparam com_llm_llm_rx_top_llm_rx_dllp_crc_rx_dllp_d_4_i_m3_0_15_.INIT = 8'hD8; + LUT3_L com_llm_llm_rx_top_llm_rx_dllp_crc_rx_dllp_d_4_i_m3_0_15_ ( + .I0(com_llm_llm_rx_top_llm_rx_dllp_crc_fr_straddle_1623), + .I1(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_7_), + .I2(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_39_), + .LO(com_llm_llm_rx_top_rx_dllp_d_4_i_m3_0_15_) + ); + defparam com_llm_llm_rx_top_llm_rx_dllp_crc_rx_dllp_d_4_i_m3_0_14_.INIT = 8'hD8; + LUT3_L com_llm_llm_rx_top_llm_rx_dllp_crc_rx_dllp_d_4_i_m3_0_14_ ( + .I0(com_llm_llm_rx_top_llm_rx_dllp_crc_fr_straddle_1623), + .I1(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_6_), + .I2(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_38_), + .LO(com_llm_llm_rx_top_rx_dllp_d_4_i_m3_0_14_) + ); + defparam com_llm_llm_rx_top_llm_rx_dllp_crc_rx_dllp_d_4_i_m3_0_11_.INIT = 8'hD8; + LUT3_L com_llm_llm_rx_top_llm_rx_dllp_crc_rx_dllp_d_4_i_m3_0_11_ ( + .I0(com_llm_llm_rx_top_llm_rx_dllp_crc_fr_straddle_1623), + .I1(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_3_), + .I2(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_35_), + .LO(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_dllp_d_4_i_m3_0_11__1588) + ); + defparam com_llm_llm_rx_top_llm_rx_dllp_crc_rx_dllp_d_4_i_m3_0_10_.INIT = 8'hD8; + LUT3_L com_llm_llm_rx_top_llm_rx_dllp_crc_rx_dllp_d_4_i_m3_0_10_ ( + .I0(com_llm_llm_rx_top_llm_rx_dllp_crc_fr_straddle_1623), + .I1(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_2_), + .I2(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_34_), + .LO(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_dllp_d_4_i_m3_0_10__1589) + ); + defparam com_llm_llm_rx_top_llm_rx_dllp_crc_rx_dllp_d_4_i_m3_0_9_.INIT = 8'hD8; + LUT3_L com_llm_llm_rx_top_llm_rx_dllp_crc_rx_dllp_d_4_i_m3_0_9_ ( + .I0(com_llm_llm_rx_top_llm_rx_dllp_crc_fr_straddle_1623), + .I1(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_1_), + .I2(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_33_), + .LO(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_dllp_d_4_i_m3_0_9__1590) + ); + defparam com_llm_llm_rx_top_llm_rx_dllp_crc_rx_dllp_d_4_i_m3_0_8_.INIT = 8'hD8; + LUT3_L com_llm_llm_rx_top_llm_rx_dllp_crc_rx_dllp_d_4_i_m3_0_8_ ( + .I0(com_llm_llm_rx_top_llm_rx_dllp_crc_fr_straddle_1623), + .I1(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_0_), + .I2(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_32_), + .LO(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_dllp_d_4_i_m3_0_8__1591) + ); + defparam com_llm_llm_rx_top_llm_rx_dllp_crc_rx_dllp_d_4_i_m2_i_m3_0_7_.INIT = 8'hE4; + LUT3_L com_llm_llm_rx_top_llm_rx_dllp_crc_rx_dllp_d_4_i_m2_i_m3_0_7_ ( + .I0(com_llm_llm_rx_top_llm_rx_dllp_crc_fr_straddle_1623), + .I1(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_31_), + .I2(com_llm_llm_rx_top_rx_data_63_), + .LO(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_dllp_d_4_i_m2_i_m3_0_7__1592) + ); + defparam com_llm_llm_rx_top_llm_rx_dllp_crc_rx_dllp_d_4_i_m3_0_6_.INIT = 8'hE4; + LUT3_L com_llm_llm_rx_top_llm_rx_dllp_crc_rx_dllp_d_4_i_m3_0_6_ ( + .I0(com_llm_llm_rx_top_llm_rx_dllp_crc_fr_straddle_1623), + .I1(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_30_), + .I2(com_llm_llm_rx_top_rx_data_62_), + .LO(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_dllp_d_4_i_m3_0_6__1593) + ); + defparam com_llm_llm_rx_top_llm_rx_dllp_crc_rx_dllp_d_4_i_m3_0_5_.INIT = 8'hE4; + LUT3_L com_llm_llm_rx_top_llm_rx_dllp_crc_rx_dllp_d_4_i_m3_0_5_ ( + .I0(com_llm_llm_rx_top_llm_rx_dllp_crc_fr_straddle_1623), + .I1(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_29_), + .I2(com_llm_llm_rx_top_rx_data_61_), + .LO(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_dllp_d_4_i_m3_0_5__1594) + ); + defparam com_llm_llm_rx_top_llm_rx_dllp_crc_rx_dllp_d_4_i_m3_0_31_.INIT = 8'hD8; + LUT3_L com_llm_llm_rx_top_llm_rx_dllp_crc_rx_dllp_d_4_i_m3_0_31_ ( + .I0(com_llm_llm_rx_top_llm_rx_dllp_crc_fr_straddle_1623), + .I1(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_23_), + .I2(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_55_), + .LO(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_dllp_d_4_i_m3_0_31__1601) + ); + defparam com_llm_llm_rx_top_llm_rx_dllp_crc_rx_dllp_d_4_i_m2_i_m3_0_30_.INIT = 8'hD8; + LUT3_L com_llm_llm_rx_top_llm_rx_dllp_crc_rx_dllp_d_4_i_m2_i_m3_0_30_ ( + .I0(com_llm_llm_rx_top_llm_rx_dllp_crc_fr_straddle_1623), + .I1(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_22_), + .I2(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_54_), + .LO(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_dllp_d_4_i_m2_i_m3_0_30__1602) + ); + defparam com_llm_llm_rx_top_llm_rx_dllp_crc_rx_dllp_d_4_i_m2_i_m3_0_29_.INIT = 8'hD8; + LUT3_L com_llm_llm_rx_top_llm_rx_dllp_crc_rx_dllp_d_4_i_m2_i_m3_0_29_ ( + .I0(com_llm_llm_rx_top_llm_rx_dllp_crc_fr_straddle_1623), + .I1(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_21_), + .I2(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_53_), + .LO(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_dllp_d_4_i_m2_i_m3_0_29__1603) + ); + defparam com_llm_llm_rx_top_llm_rx_dllp_crc_rx_dllp_d_4_i_m2_i_m3_0_28_.INIT = 8'hD8; + LUT3_L com_llm_llm_rx_top_llm_rx_dllp_crc_rx_dllp_d_4_i_m2_i_m3_0_28_ ( + .I0(com_llm_llm_rx_top_llm_rx_dllp_crc_fr_straddle_1623), + .I1(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_20_), + .I2(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_52_), + .LO(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_dllp_d_4_i_m2_i_m3_0_28__1604) + ); + defparam com_llm_llm_rx_top_llm_rx_dllp_crc_rx_dllp_d_4_i_m3_0_27_.INIT = 8'hD8; + LUT3_L com_llm_llm_rx_top_llm_rx_dllp_crc_rx_dllp_d_4_i_m3_0_27_ ( + .I0(com_llm_llm_rx_top_llm_rx_dllp_crc_fr_straddle_1623), + .I1(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_19_), + .I2(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_51_), + .LO(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_dllp_d_4_i_m3_0_27__1605) + ); + defparam com_llm_llm_rx_top_llm_rx_dllp_crc_rx_dllp_d_4_i_m3_0_26_.INIT = 8'hD8; + LUT3_L com_llm_llm_rx_top_llm_rx_dllp_crc_rx_dllp_d_4_i_m3_0_26_ ( + .I0(com_llm_llm_rx_top_llm_rx_dllp_crc_fr_straddle_1623), + .I1(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_18_), + .I2(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_50_), + .LO(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_dllp_d_4_i_m3_0_26__1606) + ); + defparam com_llm_llm_rx_top_llm_rx_dllp_crc_rx_dllp_d_4_i_m3_0_25_.INIT = 8'hD8; + LUT3_L com_llm_llm_rx_top_llm_rx_dllp_crc_rx_dllp_d_4_i_m3_0_25_ ( + .I0(com_llm_llm_rx_top_llm_rx_dllp_crc_fr_straddle_1623), + .I1(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_17_), + .I2(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_49_), + .LO(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_dllp_d_4_i_m3_0_25__1607) + ); + defparam com_llm_llm_rx_top_llm_rx_dllp_crc_rx_dllp_d_4_i_m3_0_24_.INIT = 8'hD8; + LUT3_L com_llm_llm_rx_top_llm_rx_dllp_crc_rx_dllp_d_4_i_m3_0_24_ ( + .I0(com_llm_llm_rx_top_llm_rx_dllp_crc_fr_straddle_1623), + .I1(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_16_), + .I2(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_48_), + .LO(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_dllp_d_4_i_m3_0_24__1608) + ); + MUXCY com_llm_llm_rx_top_llm_rx_dllp_crc_crc16_ok_0_I_37 ( + .CI(com_llm_llm_rx_top_llm_rx_dllp_crc_data_tmp[6]), + .DI(com_llm_llm_rx_top_llm_rx_dllp_crc_GND_1561), + .O(com_llm_llm_rx_top_llm_rx_dllp_crc_crc16_ok), + .S(com_llm_llm_rx_top_llm_rx_dllp_crc_N_27) + ); + FDC com_llm_llm_rx_top_llm_rx_dllp_crc_str_dllp_q ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_dllp_crc_str_dllp), + .Q(com_llm_llm_rx_top_llm_rx_dllp_crc_str_dllp_q_1562), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_dllp_crc_reg_dllp_q ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_dllp_crc_reg_dllp), + .Q(com_llm_llm_rx_top_llm_rx_dllp_crc_reg_dllp_q_1565), + .CLR(plm_link_up_i) + ); + FDP com_llm_llm_rx_top_llm_rx_dllp_crc_RX_DLLP_CRC_ERR_N ( + .PRE(plm_link_up_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_dllp_crc_N_23323_i_1563), + .Q(com_cmml_bad_dllp_err_n) + ); + FDC com_llm_llm_rx_top_llm_rx_dllp_crc_RX_DLLP_VLD ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_dllp_crc_RX_DLLP_VLD_5), + .Q(com_llm_rx_dllp_vld), + .CLR(plm_link_up_i) + ); + FD com_llm_llm_rx_top_llm_rx_dllp_crc_fr_straddle_q ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_dllp_crc_fr_straddle_1623), + .Q(com_llm_llm_rx_top_llm_rx_dllp_crc_fr_straddle_q_1564) + ); + FDC com_llm_llm_rx_top_llm_rx_dllp_crc_reg_dllp_qq ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_dllp_crc_reg_dllp_q_1565), + .Q(com_llm_llm_rx_top_llm_rx_dllp_crc_reg_dllp_qq_1566), + .CLR(plm_link_up_i) + ); + FD com_llm_llm_rx_top_llm_rx_dllp_crc_RX_DLLP_LOW_M1_1_8_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_dllp_crc_RX_DLLP_LOW_M1_2[8]), + .Q(com_llm_reg_rx_dllp_tsn_m1[8]) + ); + FD com_llm_llm_rx_top_llm_rx_dllp_crc_RX_DLLP_LOW_M1_1_7_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_dllp_crc_RX_DLLP_LOW_M1_2[7]), + .Q(com_llm_reg_rx_dllp_tsn_m1[7]) + ); + FD com_llm_llm_rx_top_llm_rx_dllp_crc_RX_DLLP_LOW_M1_1_6_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_dllp_crc_RX_DLLP_LOW_M1_2[6]), + .Q(com_llm_reg_rx_dllp_tsn_m1[6]) + ); + FD com_llm_llm_rx_top_llm_rx_dllp_crc_RX_DLLP_LOW_M1_1_5_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_dllp_crc_RX_DLLP_LOW_M1_2[5]), + .Q(com_llm_reg_rx_dllp_tsn_m1[5]) + ); + FD com_llm_llm_rx_top_llm_rx_dllp_crc_RX_DLLP_LOW_M1_1_4_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_dllp_crc_RX_DLLP_LOW_M1_2[4]), + .Q(com_llm_reg_rx_dllp_tsn_m1[4]) + ); + FD com_llm_llm_rx_top_llm_rx_dllp_crc_RX_DLLP_LOW_M1_1_3_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_dllp_crc_RX_DLLP_LOW_M1_2[3]), + .Q(com_llm_reg_rx_dllp_tsn_m1[3]) + ); + FD com_llm_llm_rx_top_llm_rx_dllp_crc_RX_DLLP_LOW_M1_1_2_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_dllp_crc_RX_DLLP_LOW_M1_2[2]), + .Q(com_llm_reg_rx_dllp_tsn_m1[2]) + ); + FD com_llm_llm_rx_top_llm_rx_dllp_crc_RX_DLLP_LOW_M1_1_1_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_dllp_crc_RX_DLLP_LOW_M1_2[1]), + .Q(com_llm_reg_rx_dllp_tsn_m1[1]) + ); + FD com_llm_llm_rx_top_llm_rx_dllp_crc_RX_DLLP_LOW_M1_1_11_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_dllp_crc_RX_DLLP_LOW_M1_2[11]), + .Q(com_llm_reg_rx_dllp_tsn_m1[11]) + ); + FD com_llm_llm_rx_top_llm_rx_dllp_crc_RX_DLLP_LOW_M1_1_10_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_dllp_crc_RX_DLLP_LOW_M1_2[10]), + .Q(com_llm_reg_rx_dllp_tsn_m1[10]) + ); + FD com_llm_llm_rx_top_llm_rx_dllp_crc_RX_DLLP_LOW_M1_1_9_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_dllp_crc_RX_DLLP_LOW_M1_2[9]), + .Q(com_llm_reg_rx_dllp_tsn_m1[9]) + ); + FD com_llm_llm_rx_top_llm_rx_dllp_crc_crc16_ori_3_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_dllp_crc_crc16_ori_4_i_m2_i_m3_0_3__1567), + .Q(com_llm_llm_rx_top_llm_rx_dllp_crc_crc16_ori[3]) + ); + FD com_llm_llm_rx_top_llm_rx_dllp_crc_crc16_ori_2_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_dllp_crc_crc16_ori_4_i_m2_i_m3_0_2__1568), + .Q(com_llm_llm_rx_top_llm_rx_dllp_crc_crc16_ori[2]) + ); + FD com_llm_llm_rx_top_llm_rx_dllp_crc_crc16_ori_1_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_dllp_crc_crc16_ori_4_i_m2_i_m3_0_1__1569), + .Q(com_llm_llm_rx_top_llm_rx_dllp_crc_crc16_ori[1]) + ); + FD com_llm_llm_rx_top_llm_rx_dllp_crc_crc16_ori_0_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_dllp_crc_crc16_ori_4_i_m2_i_m3_0_0__1570), + .Q(com_llm_llm_rx_top_llm_rx_dllp_crc_crc16_ori[0]) + ); + FD com_llm_llm_rx_top_llm_rx_dllp_crc_crc16_ori_15_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_dllp_crc_crc16_ori_4_i_m3_0_15__1571), + .Q(com_llm_llm_rx_top_llm_rx_dllp_crc_crc16_ori[15]) + ); + FD com_llm_llm_rx_top_llm_rx_dllp_crc_crc16_ori_14_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_dllp_crc_crc16_ori_4_i_m2_i_m3_0_14__1572), + .Q(com_llm_llm_rx_top_llm_rx_dllp_crc_crc16_ori[14]) + ); + FD com_llm_llm_rx_top_llm_rx_dllp_crc_crc16_ori_13_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_dllp_crc_crc16_ori_4_i_m2_i_m3_0_13__1573), + .Q(com_llm_llm_rx_top_llm_rx_dllp_crc_crc16_ori[13]) + ); + FD com_llm_llm_rx_top_llm_rx_dllp_crc_crc16_ori_12_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_dllp_crc_crc16_ori_4_i_m2_i_m3_0_12__1574), + .Q(com_llm_llm_rx_top_llm_rx_dllp_crc_crc16_ori[12]) + ); + FD com_llm_llm_rx_top_llm_rx_dllp_crc_crc16_ori_11_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_dllp_crc_crc16_ori_4_i_m3_0_11__1575), + .Q(com_llm_llm_rx_top_llm_rx_dllp_crc_crc16_ori[11]) + ); + FD com_llm_llm_rx_top_llm_rx_dllp_crc_crc16_ori_10_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_dllp_crc_crc16_ori_4_i_m3_0_10__1576), + .Q(com_llm_llm_rx_top_llm_rx_dllp_crc_crc16_ori[10]) + ); + FD com_llm_llm_rx_top_llm_rx_dllp_crc_crc16_ori_9_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_dllp_crc_crc16_ori_4_i_m3_0_9__1577), + .Q(com_llm_llm_rx_top_llm_rx_dllp_crc_crc16_ori[9]) + ); + FD com_llm_llm_rx_top_llm_rx_dllp_crc_crc16_ori_8_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_dllp_crc_crc16_ori_4_i_m3_0_8__1578), + .Q(com_llm_llm_rx_top_llm_rx_dllp_crc_crc16_ori[8]) + ); + FD com_llm_llm_rx_top_llm_rx_dllp_crc_crc16_ori_7_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_dllp_crc_crc16_ori_4_i_m3_0_7__1579), + .Q(com_llm_llm_rx_top_llm_rx_dllp_crc_crc16_ori[7]) + ); + FD com_llm_llm_rx_top_llm_rx_dllp_crc_crc16_ori_6_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_dllp_crc_crc16_ori_4_i_m3_0_6__1580), + .Q(com_llm_llm_rx_top_llm_rx_dllp_crc_crc16_ori[6]) + ); + FD com_llm_llm_rx_top_llm_rx_dllp_crc_crc16_ori_5_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_dllp_crc_crc16_ori_4_i_m3_0_5__1581), + .Q(com_llm_llm_rx_top_llm_rx_dllp_crc_crc16_ori[5]) + ); + FD com_llm_llm_rx_top_llm_rx_dllp_crc_crc16_ori_4_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_dllp_crc_crc16_ori_4_i_m2_i_m3_0_4__1582), + .Q(com_llm_llm_rx_top_llm_rx_dllp_crc_crc16_ori[4]) + ); + FD com_llm_llm_rx_top_llm_rx_dllp_crc_rx_dllp_d_4_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_dllp_d_4_i_m3_0_4__1583), + .Q(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_dllp_d_4__1597) + ); + FD com_llm_llm_rx_top_llm_rx_dllp_crc_rx_dllp_d_3_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_dllp_d_4_i_m2_i_m3_0_3__1584), + .Q(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_dllp_d_3__1598) + ); + FD com_llm_llm_rx_top_llm_rx_dllp_crc_rx_dllp_d_2_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_dllp_d_4_i_m3_0_2__1585), + .Q(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_dllp_d_2__1599) + ); + FD com_llm_llm_rx_top_llm_rx_dllp_crc_rx_dllp_d_1_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_dllp_d_4_i_m3_0_1__1586), + .Q(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_dllp_d_1__1600) + ); + FD com_llm_llm_rx_top_llm_rx_dllp_crc_rx_dllp_d_0_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_dllp_d_4_i_m3_0_0__1587), + .Q(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_dllp_d[0]) + ); + FD com_llm_llm_rx_top_llm_rx_dllp_crc_rx_dllp_d_11_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_dllp_d_4_i_m3_0_11__1588), + .Q(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_dllp_d_11__1611) + ); + FD com_llm_llm_rx_top_llm_rx_dllp_crc_rx_dllp_d_10_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_dllp_d_4_i_m3_0_10__1589), + .Q(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_dllp_d_10__1612) + ); + FD com_llm_llm_rx_top_llm_rx_dllp_crc_rx_dllp_d_9_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_dllp_d_4_i_m3_0_9__1590), + .Q(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_dllp_d_9__1613) + ); + FD com_llm_llm_rx_top_llm_rx_dllp_crc_rx_dllp_d_8_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_dllp_d_4_i_m3_0_8__1591), + .Q(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_dllp_d_8__1614) + ); + FD com_llm_llm_rx_top_llm_rx_dllp_crc_rx_dllp_d_7_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_dllp_d_4_i_m2_i_m3_0_7__1592), + .Q(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_dllp_d_7__1615) + ); + FD com_llm_llm_rx_top_llm_rx_dllp_crc_rx_dllp_d_6_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_dllp_d_4_i_m3_0_6__1593), + .Q(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_dllp_d_6__1595) + ); + FD com_llm_llm_rx_top_llm_rx_dllp_crc_rx_dllp_d_5_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_dllp_d_4_i_m3_0_5__1594), + .Q(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_dllp_d_5__1596) + ); + FD com_llm_llm_rx_top_llm_rx_dllp_crc_RX_DLLP_6_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_dllp_d_6__1595), + .Q(com_llm_reg_rx_dllp_tsn[6]) + ); + FD com_llm_llm_rx_top_llm_rx_dllp_crc_RX_DLLP_5_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_dllp_d_5__1596), + .Q(com_llm_reg_rx_dllp_tsn[5]) + ); + FD com_llm_llm_rx_top_llm_rx_dllp_crc_RX_DLLP_4_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_dllp_d_4__1597), + .Q(com_llm_reg_rx_dllp_tsn[4]) + ); + FD com_llm_llm_rx_top_llm_rx_dllp_crc_RX_DLLP_3_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_dllp_d_3__1598), + .Q(com_llm_reg_rx_dllp_tsn[3]) + ); + FD com_llm_llm_rx_top_llm_rx_dllp_crc_RX_DLLP_2_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_dllp_d_2__1599), + .Q(com_llm_reg_rx_dllp_tsn[2]) + ); + FD com_llm_llm_rx_top_llm_rx_dllp_crc_RX_DLLP_1_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_dllp_d_1__1600), + .Q(com_llm_reg_rx_dllp_tsn[1]) + ); + FD com_llm_llm_rx_top_llm_rx_dllp_crc_RX_DLLP_0_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_dllp_d[0]), + .Q(com_llm_reg_rx_dllp_tsn[0]) + ); + FD com_llm_llm_rx_top_llm_rx_dllp_crc_rx_dllp_d_31_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_dllp_d_4_i_m3_0_31__1601), + .Q(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_dllp_d_31__1616) + ); + FD com_llm_llm_rx_top_llm_rx_dllp_crc_rx_dllp_d_30_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_dllp_d_4_i_m2_i_m3_0_30__1602), + .Q(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_dllp_d_30__1617) + ); + FD com_llm_llm_rx_top_llm_rx_dllp_crc_rx_dllp_d_29_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_dllp_d_4_i_m2_i_m3_0_29__1603), + .Q(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_dllp_d_29__1618) + ); + FD com_llm_llm_rx_top_llm_rx_dllp_crc_rx_dllp_d_28_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_dllp_d_4_i_m2_i_m3_0_28__1604), + .Q(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_dllp_d_28__1619) + ); + FD com_llm_llm_rx_top_llm_rx_dllp_crc_rx_dllp_d_27_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_dllp_d_4_i_m3_0_27__1605), + .Q(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_dllp_d_27__1620) + ); + FD com_llm_llm_rx_top_llm_rx_dllp_crc_rx_dllp_d_26_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_dllp_d_4_i_m3_0_26__1606), + .Q(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_dllp_d_26__1621) + ); + FD com_llm_llm_rx_top_llm_rx_dllp_crc_rx_dllp_d_25_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_dllp_d_4_i_m3_0_25__1607), + .Q(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_dllp_d_25__1609) + ); + FD com_llm_llm_rx_top_llm_rx_dllp_crc_rx_dllp_d_24_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_dllp_d_4_i_m3_0_24__1608), + .Q(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_dllp_d_24__1610) + ); + FD com_llm_llm_rx_top_llm_rx_dllp_crc_RX_DLLP_25_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_dllp_d_25__1609), + .Q(com_llm_llm_rx_top_rx_dllp[25]) + ); + FD com_llm_llm_rx_top_llm_rx_dllp_crc_RX_DLLP_24_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_dllp_d_24__1610), + .Q(com_llm_llm_rx_top_rx_dllp[24]) + ); + FD com_llm_llm_rx_top_llm_rx_dllp_crc_RX_DLLP_11_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_dllp_d_11__1611), + .Q(com_llm_reg_rx_dllp_tsn[11]) + ); + FD com_llm_llm_rx_top_llm_rx_dllp_crc_RX_DLLP_10_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_dllp_d_10__1612), + .Q(com_llm_reg_rx_dllp_tsn[10]) + ); + FD com_llm_llm_rx_top_llm_rx_dllp_crc_RX_DLLP_9_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_dllp_d_9__1613), + .Q(com_llm_reg_rx_dllp_tsn[9]) + ); + FD com_llm_llm_rx_top_llm_rx_dllp_crc_RX_DLLP_8_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_dllp_d_8__1614), + .Q(com_llm_reg_rx_dllp_tsn[8]) + ); + FD com_llm_llm_rx_top_llm_rx_dllp_crc_RX_DLLP_7_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_dllp_d_7__1615), + .Q(com_llm_reg_rx_dllp_tsn[7]) + ); + FD com_llm_llm_rx_top_llm_rx_dllp_crc_crc16_d32_nst_8_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_dllp_crc_new_c32_nst_i_8_), + .Q(com_llm_llm_rx_top_llm_rx_dllp_crc_crc16_d32_nst[8]) + ); + FD com_llm_llm_rx_top_llm_rx_dllp_crc_crc16_d32_nst_7_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_dllp_crc_new_c32_1_i_0_7_), + .Q(com_llm_llm_rx_top_llm_rx_dllp_crc_crc16_d32_nst[7]) + ); + FD com_llm_llm_rx_top_llm_rx_dllp_crc_crc16_d32_nst_6_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_dllp_crc_new_c32_nst_i_6_), + .Q(com_llm_llm_rx_top_llm_rx_dllp_crc_crc16_d32_nst[6]) + ); + FD com_llm_llm_rx_top_llm_rx_dllp_crc_crc16_d32_nst_5_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_dllp_crc_new_c32_1_i_0_5_), + .Q(com_llm_llm_rx_top_llm_rx_dllp_crc_crc16_d32_nst[5]) + ); + FD com_llm_llm_rx_top_llm_rx_dllp_crc_crc16_d32_nst_4_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_dllp_crc_new_c32_1_i_0_4_), + .Q(com_llm_llm_rx_top_llm_rx_dllp_crc_crc16_d32_nst[4]) + ); + FD com_llm_llm_rx_top_llm_rx_dllp_crc_crc16_d32_nst_3_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_dllp_crc_new_c32_1_i_0_3_), + .Q(com_llm_llm_rx_top_llm_rx_dllp_crc_crc16_d32_nst[3]) + ); + FD com_llm_llm_rx_top_llm_rx_dllp_crc_crc16_d32_nst_2_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_dllp_crc_new_c32_nst_i_2_), + .Q(com_llm_llm_rx_top_llm_rx_dllp_crc_crc16_d32_nst[2]) + ); + FD com_llm_llm_rx_top_llm_rx_dllp_crc_crc16_d32_nst_1_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_dllp_crc_new_c32_nst_i_1_), + .Q(com_llm_llm_rx_top_llm_rx_dllp_crc_crc16_d32_nst[1]) + ); + FD com_llm_llm_rx_top_llm_rx_dllp_crc_crc16_d32_nst_0_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_dllp_crc_new_c32_1_i_0_0_), + .Q(com_llm_llm_rx_top_llm_rx_dllp_crc_crc16_d32_nst[0]) + ); + FD com_llm_llm_rx_top_llm_rx_dllp_crc_RX_DLLP_31_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_dllp_d_31__1616), + .Q(com_llm_rx_dllp[31]) + ); + FD com_llm_llm_rx_top_llm_rx_dllp_crc_RX_DLLP_30_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_dllp_d_30__1617), + .Q(com_llm_rx_dllp[30]) + ); + FD com_llm_llm_rx_top_llm_rx_dllp_crc_RX_DLLP_29_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_dllp_d_29__1618), + .Q(com_llm_rx_dllp[29]) + ); + FD com_llm_llm_rx_top_llm_rx_dllp_crc_RX_DLLP_28_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_dllp_d_28__1619), + .Q(com_llm_llm_rx_top_rx_dllp[28]) + ); + FD com_llm_llm_rx_top_llm_rx_dllp_crc_RX_DLLP_27_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_dllp_d_27__1620), + .Q(com_llm_llm_rx_top_rx_dllp[27]) + ); + FD com_llm_llm_rx_top_llm_rx_dllp_crc_RX_DLLP_26_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_dllp_d_26__1621), + .Q(com_llm_llm_rx_top_rx_dllp[26]) + ); + FD com_llm_llm_rx_top_llm_rx_dllp_crc_crc16_d32_st_7_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_dllp_crc_new_c32_1_i_7_), + .Q(com_llm_llm_rx_top_llm_rx_dllp_crc_crc16_d32_st[7]) + ); + FD com_llm_llm_rx_top_llm_rx_dllp_crc_crc16_d32_st_6_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_dllp_crc_new_c32_st_i_6_), + .Q(com_llm_llm_rx_top_llm_rx_dllp_crc_crc16_d32_st[6]) + ); + FD com_llm_llm_rx_top_llm_rx_dllp_crc_crc16_d32_st_5_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_dllp_crc_new_c32_1_i_5_), + .Q(com_llm_llm_rx_top_llm_rx_dllp_crc_crc16_d32_st[5]) + ); + FD com_llm_llm_rx_top_llm_rx_dllp_crc_crc16_d32_st_4_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_dllp_crc_new_c32_1_i_4_), + .Q(com_llm_llm_rx_top_llm_rx_dllp_crc_crc16_d32_st[4]) + ); + FD com_llm_llm_rx_top_llm_rx_dllp_crc_crc16_d32_st_3_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_dllp_crc_new_c32_1_i_3_), + .Q(com_llm_llm_rx_top_llm_rx_dllp_crc_crc16_d32_st[3]) + ); + FD com_llm_llm_rx_top_llm_rx_dllp_crc_crc16_d32_st_2_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_dllp_crc_new_c32_st_i_2_), + .Q(com_llm_llm_rx_top_llm_rx_dllp_crc_crc16_d32_st[2]) + ); + FD com_llm_llm_rx_top_llm_rx_dllp_crc_crc16_d32_st_1_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_dllp_crc_new_c32_st_i_1_), + .Q(com_llm_llm_rx_top_llm_rx_dllp_crc_crc16_d32_st[1]) + ); + FD com_llm_llm_rx_top_llm_rx_dllp_crc_crc16_d32_st_0_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_dllp_crc_new_c32_1_i_0_), + .Q(com_llm_llm_rx_top_llm_rx_dllp_crc_crc16_d32_st[0]) + ); + FD com_llm_llm_rx_top_llm_rx_dllp_crc_crc16_d32_nst_15_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_dllp_crc_new_c32_nst_i_15_), + .Q(com_llm_llm_rx_top_llm_rx_dllp_crc_crc16_d32_nst[15]) + ); + FD com_llm_llm_rx_top_llm_rx_dllp_crc_crc16_d32_nst_14_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_dllp_crc_new_c32_nst_i_14_), + .Q(com_llm_llm_rx_top_llm_rx_dllp_crc_crc16_d32_nst[14]) + ); + FD com_llm_llm_rx_top_llm_rx_dllp_crc_crc16_d32_nst_13_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_dllp_crc_new_c32_1_i_0_13_), + .Q(com_llm_llm_rx_top_llm_rx_dllp_crc_crc16_d32_nst[13]) + ); + FD com_llm_llm_rx_top_llm_rx_dllp_crc_crc16_d32_nst_12_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_dllp_crc_new_c32_1_i_0_12_), + .Q(com_llm_llm_rx_top_llm_rx_dllp_crc_crc16_d32_nst[12]) + ); + FD com_llm_llm_rx_top_llm_rx_dllp_crc_crc16_d32_nst_11_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_dllp_crc_new_c32_nst_i_11_), + .Q(com_llm_llm_rx_top_llm_rx_dllp_crc_crc16_d32_nst[11]) + ); + FD com_llm_llm_rx_top_llm_rx_dllp_crc_crc16_d32_nst_10_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_dllp_crc_new_c32_nst_i_10_), + .Q(com_llm_llm_rx_top_llm_rx_dllp_crc_crc16_d32_nst[10]) + ); + FD com_llm_llm_rx_top_llm_rx_dllp_crc_crc16_d32_nst_9_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_dllp_crc_new_c32_1_i_0_9_), + .Q(com_llm_llm_rx_top_llm_rx_dllp_crc_crc16_d32_nst[9]) + ); + FD com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_bit_swap_q_6_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_rx_data_1_), + .Q(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_1_) + ); + FD com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_bit_swap_q_5_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_rx_data_2_), + .Q(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_2_) + ); + FD com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_bit_swap_q_4_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_rx_data_3_), + .Q(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_3_) + ); + FD com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_bit_swap_q_3_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_rx_data_4_), + .Q(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_4_) + ); + FD com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_bit_swap_q_2_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_rx_data_5_), + .Q(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_5_) + ); + FD com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_bit_swap_q_1_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_rx_data_6_), + .Q(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_6_) + ); + FD com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_bit_swap_q_0_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_rx_data_7_), + .Q(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_7_) + ); + FD com_llm_llm_rx_top_llm_rx_dllp_crc_crc16_d32_st_15_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_dllp_crc_new_c32_st_i_15_), + .Q(com_llm_llm_rx_top_llm_rx_dllp_crc_crc16_d32_st[15]) + ); + FD com_llm_llm_rx_top_llm_rx_dllp_crc_crc16_d32_st_14_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_dllp_crc_new_c32_st_i_14_), + .Q(com_llm_llm_rx_top_llm_rx_dllp_crc_crc16_d32_st[14]) + ); + FD com_llm_llm_rx_top_llm_rx_dllp_crc_crc16_d32_st_13_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_dllp_crc_new_c32_1_i_13_), + .Q(com_llm_llm_rx_top_llm_rx_dllp_crc_crc16_d32_st[13]) + ); + FD com_llm_llm_rx_top_llm_rx_dllp_crc_crc16_d32_st_12_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_dllp_crc_new_c32_1_i_12_), + .Q(com_llm_llm_rx_top_llm_rx_dllp_crc_crc16_d32_st[12]) + ); + FD com_llm_llm_rx_top_llm_rx_dllp_crc_crc16_d32_st_11_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_dllp_crc_new_c32_st_i_11_), + .Q(com_llm_llm_rx_top_llm_rx_dllp_crc_crc16_d32_st[11]) + ); + FD com_llm_llm_rx_top_llm_rx_dllp_crc_crc16_d32_st_10_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_dllp_crc_new_c32_st_i_10_), + .Q(com_llm_llm_rx_top_llm_rx_dllp_crc_crc16_d32_st[10]) + ); + FD com_llm_llm_rx_top_llm_rx_dllp_crc_crc16_d32_st_9_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_dllp_crc_new_c32_1_i_9_), + .Q(com_llm_llm_rx_top_llm_rx_dllp_crc_crc16_d32_st[9]) + ); + FD com_llm_llm_rx_top_llm_rx_dllp_crc_crc16_d32_st_8_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_dllp_crc_new_c32_st_i_8_), + .Q(com_llm_llm_rx_top_llm_rx_dllp_crc_crc16_d32_st[8]) + ); + FD com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_bit_swap_q_21_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_rx_data_18_), + .Q(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_18_) + ); + FD com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_bit_swap_q_20_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_rx_data_19_), + .Q(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_19_) + ); + FD com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_bit_swap_q_19_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_rx_data_20_), + .Q(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_20_) + ); + FD com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_bit_swap_q_18_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_rx_data_21_), + .Q(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_21_) + ); + FD com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_bit_swap_q_17_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_rx_data_22_), + .Q(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_22_) + ); + FD com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_bit_swap_q_16_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_rx_data_23_), + .Q(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_23_) + ); + FD com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_bit_swap_q_15_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_rx_data_8_), + .Q(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_8_) + ); + FD com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_bit_swap_q_14_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_rx_data_9_), + .Q(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_9_) + ); + FD com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_bit_swap_q_13_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_rx_data_10_), + .Q(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_10_) + ); + FD com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_bit_swap_q_12_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_rx_data_11_), + .Q(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_11_) + ); + FD com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_bit_swap_q_11_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_rx_data_12_), + .Q(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_12_) + ); + FD com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_bit_swap_q_10_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_rx_data_13_), + .Q(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_13_) + ); + FD com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_bit_swap_q_9_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_rx_data_14_), + .Q(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_14_) + ); + FD com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_bit_swap_q_8_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_rx_data_15_), + .Q(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_15_) + ); + FD com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_bit_swap_q_7_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_rx_data_0_), + .Q(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_0_) + ); + FD com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_bit_swap_q_36_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_rx_data_35_), + .Q(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_35_) + ); + FD com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_bit_swap_q_35_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_rx_data_36_), + .Q(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_36_) + ); + FD com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_bit_swap_q_34_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_rx_data_37_), + .Q(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_37_) + ); + FD com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_bit_swap_q_33_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_rx_data_38_), + .Q(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_38_) + ); + FD com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_bit_swap_q_32_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_rx_data_39_), + .Q(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_39_) + ); + FD com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_bit_swap_q_31_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_rx_data_24_), + .Q(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_24_) + ); + FD com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_bit_swap_q_30_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_rx_data_25_), + .Q(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_25_) + ); + FD com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_bit_swap_q_29_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_rx_data_26_), + .Q(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_26_) + ); + FD com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_bit_swap_q_28_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_rx_data_27_), + .Q(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_27_) + ); + FD com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_bit_swap_q_27_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_rx_data_28_), + .Q(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q[28]) + ); + FD com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_bit_swap_q_26_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_rx_data_29_), + .Q(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_29_) + ); + FD com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_bit_swap_q_25_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_rx_data_30_), + .Q(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_30_) + ); + FD com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_bit_swap_q_24_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_rx_data_31_), + .Q(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_31_) + ); + FD com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_bit_swap_q_23_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_rx_data_16_), + .Q(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_16_) + ); + FD com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_bit_swap_q_22_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_rx_data_17_), + .Q(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_17_) + ); + FD com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_bit_swap_q_51_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_rx_data_52_), + .Q(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_52_) + ); + FD com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_bit_swap_q_50_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_rx_data_53_), + .Q(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_53_) + ); + FD com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_bit_swap_q_49_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_rx_data_54_), + .Q(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_54_) + ); + FD com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_bit_swap_q_48_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_rx_data_55_), + .Q(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_55_) + ); + FD com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_bit_swap_q_47_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_rx_data_40_), + .Q(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_40_) + ); + FD com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_bit_swap_q_46_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_rx_data_41_), + .Q(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_41_) + ); + FD com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_bit_swap_q_45_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_rx_data_42_), + .Q(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_42_) + ); + FD com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_bit_swap_q_44_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_rx_data_43_), + .Q(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_43_) + ); + FD com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_bit_swap_q_43_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_rx_data_44_), + .Q(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_44_) + ); + FD com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_bit_swap_q_42_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_rx_data_45_), + .Q(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_45_) + ); + FD com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_bit_swap_q_41_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_rx_data_46_), + .Q(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_46_) + ); + FD com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_bit_swap_q_40_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_rx_data_47_), + .Q(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_47_) + ); + FD com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_bit_swap_q_39_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_rx_data_32_), + .Q(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_32_) + ); + FD com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_bit_swap_q_38_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_rx_data_33_), + .Q(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_33_) + ); + FD com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_bit_swap_q_37_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_rx_data_34_), + .Q(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_34_) + ); + FD com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_bit_swap_q_55_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_rx_data_48_), + .Q(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_48_) + ); + FD com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_bit_swap_q_54_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_rx_data_49_), + .Q(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_49_) + ); + FD com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_bit_swap_q_53_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_rx_data_50_), + .Q(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_50_) + ); + FD com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_bit_swap_q_52_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_rx_data_51_), + .Q(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_51_) + ); + FDCE com_llm_llm_rx_top_llm_rx_dllp_crc_fr_straddle ( + .CE(com_llm_llm_rx_top_llm_rx_dllp_crc_N_68799_i_1622), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_rx_dllp_sof_n_i), + .Q(com_llm_llm_rx_top_llm_rx_dllp_crc_fr_straddle_1623), + .CLR(plm_link_up_i) + ); + defparam com_llm_llm_rx_top_llm_rx_dllp_crc_crc16_ok_0_I_45.INIT = 16'h8421; + LUT4 com_llm_llm_rx_top_llm_rx_dllp_crc_crc16_ok_0_I_45 ( + .I0(com_llm_llm_rx_top_llm_rx_dllp_crc_un1_crc16_ok_0[14]), + .I1(com_llm_llm_rx_top_llm_rx_dllp_crc_un1_crc16_ok_0[15]), + .I2(com_llm_llm_rx_top_llm_rx_dllp_crc_crc16_ori[14]), + .I3(com_llm_llm_rx_top_llm_rx_dllp_crc_crc16_ori[15]), + .O(com_llm_llm_rx_top_llm_rx_dllp_crc_N_27) + ); + defparam com_llm_llm_rx_top_llm_rx_dllp_crc_crc16_ok_0_I_72.INIT = 16'h8421; + LUT4 com_llm_llm_rx_top_llm_rx_dllp_crc_crc16_ok_0_I_72 ( + .I0(com_llm_llm_rx_top_llm_rx_dllp_crc_un1_crc16_ok_0[6]), + .I1(com_llm_llm_rx_top_llm_rx_dllp_crc_un1_crc16_ok_0[7]), + .I2(com_llm_llm_rx_top_llm_rx_dllp_crc_crc16_ori[6]), + .I3(com_llm_llm_rx_top_llm_rx_dllp_crc_crc16_ori[7]), + .O(com_llm_llm_rx_top_llm_rx_dllp_crc_N_3) + ); + defparam com_llm_llm_rx_top_llm_rx_dllp_crc_crc16_ok_0_I_63.INIT = 16'h8421; + LUT4 com_llm_llm_rx_top_llm_rx_dllp_crc_crc16_ok_0_I_63 ( + .I0(com_llm_llm_rx_top_llm_rx_dllp_crc_un1_crc16_ok_0[12]), + .I1(com_llm_llm_rx_top_llm_rx_dllp_crc_un1_crc16_ok_0[13]), + .I2(com_llm_llm_rx_top_llm_rx_dllp_crc_crc16_ori[12]), + .I3(com_llm_llm_rx_top_llm_rx_dllp_crc_crc16_ori[13]), + .O(com_llm_llm_rx_top_llm_rx_dllp_crc_N_11) + ); + defparam com_llm_llm_rx_top_llm_rx_dllp_crc_crc16_ok_0_I_54.INIT = 16'h8421; + LUT4 com_llm_llm_rx_top_llm_rx_dllp_crc_crc16_ok_0_I_54 ( + .I0(com_llm_llm_rx_top_llm_rx_dllp_crc_un1_crc16_ok_0[10]), + .I1(com_llm_llm_rx_top_llm_rx_dllp_crc_un1_crc16_ok_0[11]), + .I2(com_llm_llm_rx_top_llm_rx_dllp_crc_crc16_ori[10]), + .I3(com_llm_llm_rx_top_llm_rx_dllp_crc_crc16_ori[11]), + .O(com_llm_llm_rx_top_llm_rx_dllp_crc_N_19) + ); + defparam com_llm_llm_rx_top_llm_rx_dllp_crc_crc16_ok_0_I_36.INIT = 16'h8421; + LUT4 com_llm_llm_rx_top_llm_rx_dllp_crc_crc16_ok_0_I_36 ( + .I0(com_llm_llm_rx_top_llm_rx_dllp_crc_un1_crc16_ok_0[8]), + .I1(com_llm_llm_rx_top_llm_rx_dllp_crc_un1_crc16_ok_0[9]), + .I2(com_llm_llm_rx_top_llm_rx_dllp_crc_crc16_ori[8]), + .I3(com_llm_llm_rx_top_llm_rx_dllp_crc_crc16_ori[9]), + .O(com_llm_llm_rx_top_llm_rx_dllp_crc_N_35) + ); + defparam com_llm_llm_rx_top_llm_rx_dllp_crc_crc16_ok_0_I_27.INIT = 16'h8421; + LUT4 com_llm_llm_rx_top_llm_rx_dllp_crc_crc16_ok_0_I_27 ( + .I0(com_llm_llm_rx_top_llm_rx_dllp_crc_un1_crc16_ok_0[4]), + .I1(com_llm_llm_rx_top_llm_rx_dllp_crc_un1_crc16_ok_0[5]), + .I2(com_llm_llm_rx_top_llm_rx_dllp_crc_crc16_ori[4]), + .I3(com_llm_llm_rx_top_llm_rx_dllp_crc_crc16_ori[5]), + .O(com_llm_llm_rx_top_llm_rx_dllp_crc_N_43) + ); + defparam com_llm_llm_rx_top_llm_rx_dllp_crc_crc16_ok_0_I_18.INIT = 16'h8421; + LUT4 com_llm_llm_rx_top_llm_rx_dllp_crc_crc16_ok_0_I_18 ( + .I0(com_llm_llm_rx_top_llm_rx_dllp_crc_un1_crc16_ok_0[2]), + .I1(com_llm_llm_rx_top_llm_rx_dllp_crc_un1_crc16_ok_0[3]), + .I2(com_llm_llm_rx_top_llm_rx_dllp_crc_crc16_ori[2]), + .I3(com_llm_llm_rx_top_llm_rx_dllp_crc_crc16_ori[3]), + .O(com_llm_llm_rx_top_llm_rx_dllp_crc_N_51) + ); + defparam com_llm_llm_rx_top_llm_rx_dllp_crc_crc16_ok_0_I_9.INIT = 16'h8421; + LUT4 com_llm_llm_rx_top_llm_rx_dllp_crc_crc16_ok_0_I_9 ( + .I0(com_llm_llm_rx_top_llm_rx_dllp_crc_un1_crc16_ok_0[0]), + .I1(com_llm_llm_rx_top_llm_rx_dllp_crc_un1_crc16_ok_0[1]), + .I2(com_llm_llm_rx_top_llm_rx_dllp_crc_crc16_ori[0]), + .I3(com_llm_llm_rx_top_llm_rx_dllp_crc_crc16_ori[1]), + .O(com_llm_llm_rx_top_llm_rx_dllp_crc_N_59) + ); + defparam com_llm_llm_rx_top_llm_rx_dllp_crc_llm_rx_crc16_d32_st_new_c32_1_0_13_.INIT = 4'h6; + LUT2 com_llm_llm_rx_top_llm_rx_dllp_crc_llm_rx_crc16_d32_st_new_c32_1_0_13_ ( + .I0(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_5_), + .I1(com_llm_llm_rx_top_rx_data_58_), + .O(com_llm_llm_rx_top_llm_rx_dllp_crc_llm_rx_crc16_d32_st_new_c32_1_0_13__1632) + ); + defparam com_llm_llm_rx_top_llm_rx_dllp_crc_llm_rx_crc16_d32_st_new_c32_1_0_0_.INIT = 4'h6; + LUT2 com_llm_llm_rx_top_llm_rx_dllp_crc_llm_rx_crc16_d32_st_new_c32_1_0_0_ ( + .I0(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_0_), + .I1(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_2_), + .O(com_llm_llm_rx_top_llm_rx_dllp_crc_llm_rx_crc16_d32_st_new_c32_1_0_0__1630) + ); + defparam com_llm_llm_rx_top_llm_rx_dllp_crc_llm_rx_crc16_d32_st_new_c32_1_1_0_3_.INIT = 4'h6; + LUT2 com_llm_llm_rx_top_llm_rx_dllp_crc_llm_rx_crc16_d32_st_new_c32_1_1_0_3_ ( + .I0(com_llm_llm_rx_top_rx_data_57_), + .I1(com_llm_llm_rx_top_rx_data_60_), + .O(com_llm_llm_rx_top_llm_rx_dllp_crc_llm_rx_crc16_d32_st_new_c32_1_1_0[3]) + ); + defparam com_llm_llm_rx_top_llm_rx_dllp_crc_llm_rx_crc16_d32_st_new_c32_1_0_2_.INIT = 4'h6; + LUT2 com_llm_llm_rx_top_llm_rx_dllp_crc_llm_rx_crc16_d32_st_new_c32_1_0_2_ ( + .I0(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_10_), + .I1(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_19_), + .O(com_llm_llm_rx_top_llm_rx_dllp_crc_llm_rx_crc16_d32_st_new_c32_1_0_2__1628) + ); + defparam com_llm_llm_rx_top_llm_rx_dllp_crc_llm_rx_crc16_d32_st_new_c32_1_2_15_.INIT = 16'h6996; + LUT4 com_llm_llm_rx_top_llm_rx_dllp_crc_llm_rx_crc16_d32_st_new_c32_1_2_15_ ( + .I0(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_3_), + .I1(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_11_), + .I2(com_llm_llm_rx_top_rx_data_56_), + .I3(com_llm_llm_rx_top_rx_data_60_), + .O(com_llm_llm_rx_top_llm_rx_dllp_crc_llm_rx_crc16_d32_st_new_c32_1_2_15__1631) + ); + defparam com_llm_llm_rx_top_llm_rx_dllp_crc_llm_rx_crc16_d32_st_new_c32_1_1_3_3_.INIT = 8'h96; + LUT3 com_llm_llm_rx_top_llm_rx_dllp_crc_llm_rx_crc16_d32_st_new_c32_1_1_3_3_ ( + .I0(N_10422_1), + .I1(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_16_), + .I2(com_llm_llm_rx_top_rx_data_61_), + .O(com_llm_llm_rx_top_llm_rx_dllp_crc_llm_rx_crc16_d32_st_new_c32_1_1_3__1627) + ); + defparam com_llm_llm_rx_top_llm_rx_dllp_crc_llm_rx_crc16_d32_st_new_c32_1_1_0_.INIT = 4'h6; + LUT2 com_llm_llm_rx_top_llm_rx_dllp_crc_llm_rx_crc16_d32_st_new_c32_1_1_0_ ( + .I0(N_198), + .I1(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_7_), + .O(com_llm_llm_rx_top_llm_rx_dllp_crc_llm_rx_crc16_d32_st_new_c32_1_i_1_0_) + ); + defparam com_llm_llm_rx_top_llm_rx_dllp_crc_llm_rx_crc16_d32_st_new_c32_1_1_4_.INIT = 8'h96; + LUT3 com_llm_llm_rx_top_llm_rx_dllp_crc_llm_rx_crc16_d32_st_new_c32_1_1_4_ ( + .I0(N_208), + .I1(N_228_1), + .I2(N_10392_1), + .O(com_llm_llm_rx_top_llm_rx_dllp_crc_llm_rx_crc16_d32_st_new_c32_1_i_1_4_) + ); + defparam com_llm_llm_rx_top_llm_rx_dllp_crc_llm_rx_crc16_d32_st_new_c32_1_0_12_.INIT = 8'h96; + LUT3 com_llm_llm_rx_top_llm_rx_dllp_crc_llm_rx_crc16_d32_st_new_c32_1_0_12_ ( + .I0(N_228_1), + .I1(N_10392_1), + .I2(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_23_), + .O(com_llm_llm_rx_top_llm_rx_dllp_crc_llm_rx_crc16_d32_st_new_c32_1_0_12__1633) + ); + defparam com_llm_llm_rx_top_llm_rx_dllp_crc_llm_rx_crc16_d32_st_new_c32_1_1_1_.INIT = 4'h6; + LUT2_L com_llm_llm_rx_top_llm_rx_dllp_crc_llm_rx_crc16_d32_st_new_c32_1_1_1_ ( + .I0(N_10392), + .I1(N_10458), + .LO(com_llm_llm_rx_top_llm_rx_dllp_crc_llm_rx_crc16_d32_st_new_c32_1_1_1__1629) + ); + defparam com_llm_llm_rx_top_llm_rx_dllp_crc_llm_rx_crc16_d32_st_new_c32_1_1_11_.INIT = 4'h6; + LUT2 com_llm_llm_rx_top_llm_rx_dllp_crc_llm_rx_crc16_d32_st_new_c32_1_1_11_ ( + .I0(N_10387), + .I1(N_10392), + .O(com_llm_llm_rx_top_llm_rx_dllp_crc_llm_rx_crc16_d32_st_new_c32_1_1_11__1634) + ); + defparam com_llm_llm_rx_top_llm_rx_dllp_crc_llm_rx_crc16_d32_st_new_c32_1_0_9_.INIT = 4'h6; + LUT2 com_llm_llm_rx_top_llm_rx_dllp_crc_llm_rx_crc16_d32_st_new_c32_1_0_9_ ( + .I0(N_10375), + .I1(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_17_), + .O(com_llm_llm_rx_top_llm_rx_dllp_crc_llm_rx_crc16_d32_st_new_c32_1_0_9__1636) + ); + defparam com_llm_llm_rx_top_llm_rx_dllp_crc_llm_rx_crc16_d32_st_new_c32_1_2_10_.INIT = 16'h6996; + LUT4_L com_llm_llm_rx_top_llm_rx_dllp_crc_llm_rx_crc16_d32_st_new_c32_1_2_10_ ( + .I0(N_249_1), + .I1(N_10422), + .I2(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_6_), + .I3(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_18_), + .LO(com_llm_llm_rx_top_llm_rx_dllp_crc_llm_rx_crc16_d32_st_new_c32_1_2_10__1635) + ); + defparam com_llm_llm_rx_top_llm_rx_dllp_crc_llm_rx_crc16_d32_st_new_c32_1_0_7_.INIT = 8'h96; + LUT3 com_llm_llm_rx_top_llm_rx_dllp_crc_llm_rx_crc16_d32_st_new_c32_1_0_7_ ( + .I0(N_10406), + .I1(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_4_), + .I2(com_llm_llm_rx_top_rx_data_56_), + .O(com_llm_llm_rx_top_llm_rx_dllp_crc_llm_rx_crc16_d32_st_new_c32_1_0_7__1624) + ); + defparam com_llm_llm_rx_top_llm_rx_dllp_crc_llm_rx_crc16_d32_st_new_c32_1_2_4_.INIT = 16'h6996; + LUT4 com_llm_llm_rx_top_llm_rx_dllp_crc_llm_rx_crc16_d32_st_new_c32_1_2_4_ ( + .I0(N_10416), + .I1(com_llm_llm_rx_top_rx_data_58_), + .I2(com_llm_llm_rx_top_rx_data_59_), + .I3(com_llm_llm_rx_top_rx_data_60_), + .O(com_llm_llm_rx_top_llm_rx_dllp_crc_llm_rx_crc16_d32_st_new_c32_1_2_4__1626) + ); + defparam com_llm_llm_rx_top_llm_rx_dllp_crc_llm_rx_crc16_d32_st_new_c32_1_2_8_.INIT = 8'h96; + LUT3 com_llm_llm_rx_top_llm_rx_dllp_crc_llm_rx_crc16_d32_st_new_c32_1_2_8_ ( + .I0(N_245), + .I1(N_10401_1), + .I2(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_17_), + .O(com_llm_llm_rx_top_llm_rx_dllp_crc_llm_rx_crc16_d32_st_new_c32_1_2_8__1637) + ); + defparam com_llm_llm_rx_top_llm_rx_dllp_crc_llm_rx_crc16_d32_st_new_c32_1_1_5_.INIT = 8'h96; + LUT3 com_llm_llm_rx_top_llm_rx_dllp_crc_llm_rx_crc16_d32_st_new_c32_1_1_5_ ( + .I0(N_10406), + .I1(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_6_), + .I2(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_12_), + .O(com_llm_llm_rx_top_llm_rx_dllp_crc_llm_rx_crc16_d32_st_new_c32_1_1_5__1625) + ); + defparam com_llm_llm_rx_top_llm_rx_dllp_crc_llm_rx_crc16_d32_st_new_c32_1_1_3_.INIT = 16'h6996; + LUT4 com_llm_llm_rx_top_llm_rx_dllp_crc_llm_rx_crc16_d32_st_new_c32_1_1_3_ ( + .I0(N_219), + .I1(N_245), + .I2(N_249), + .I3(com_llm_llm_rx_top_llm_rx_dllp_crc_llm_rx_crc16_d32_st_new_c32_1_1_0[3]), + .O(com_llm_llm_rx_top_llm_rx_dllp_crc_llm_rx_crc16_d32_st_new_c32_1_i_1_3_) + ); + defparam com_llm_llm_rx_top_llm_rx_dllp_crc_llm_rx_crc16_d32_st_new_c32_1_7_.INIT = 16'h6996; + LUT4_L com_llm_llm_rx_top_llm_rx_dllp_crc_llm_rx_crc16_d32_st_new_c32_1_7_ ( + .I0(N_249), + .I1(N_10430), + .I2(N_10541), + .I3(com_llm_llm_rx_top_llm_rx_dllp_crc_llm_rx_crc16_d32_st_new_c32_1_0_7__1624), + .LO(com_llm_llm_rx_top_llm_rx_dllp_crc_new_c32_1_i_7_) + ); + defparam com_llm_llm_rx_top_llm_rx_dllp_crc_llm_rx_crc16_d32_st_new_c32_st_i_6_.INIT = 8'h69; + LUT3_L com_llm_llm_rx_top_llm_rx_dllp_crc_llm_rx_crc16_d32_st_new_c32_st_i_6_ ( + .I0(N_10374), + .I1(N_10401), + .I2(com_llm_llm_rx_top_llm_rx_dllp_crc_llm_rx_crc16_d32_st_new_c32_1_i_1_3_), + .LO(com_llm_llm_rx_top_llm_rx_dllp_crc_new_c32_st_i_6_) + ); + defparam com_llm_llm_rx_top_llm_rx_dllp_crc_llm_rx_crc16_d32_st_new_c32_1_5_.INIT = 16'h6996; + LUT4_L com_llm_llm_rx_top_llm_rx_dllp_crc_llm_rx_crc16_d32_st_new_c32_1_5_ ( + .I0(N_219), + .I1(N_10387), + .I2(N_10548), + .I3(com_llm_llm_rx_top_llm_rx_dllp_crc_llm_rx_crc16_d32_st_new_c32_1_1_5__1625), + .LO(com_llm_llm_rx_top_llm_rx_dllp_crc_new_c32_1_i_5_) + ); + defparam com_llm_llm_rx_top_llm_rx_dllp_crc_llm_rx_crc16_d32_st_new_c32_1_4_.INIT = 16'h6996; + LUT4_L com_llm_llm_rx_top_llm_rx_dllp_crc_llm_rx_crc16_d32_st_new_c32_1_4_ ( + .I0(N_10387), + .I1(N_27386_i_0), + .I2(com_llm_llm_rx_top_llm_rx_dllp_crc_llm_rx_crc16_d32_st_new_c32_1_2_4__1626), + .I3(com_llm_llm_rx_top_llm_rx_dllp_crc_llm_rx_crc16_d32_st_new_c32_1_i_1_4_), + .LO(com_llm_llm_rx_top_llm_rx_dllp_crc_new_c32_1_i_4_) + ); + defparam com_llm_llm_rx_top_llm_rx_dllp_crc_llm_rx_crc16_d32_st_new_c32_1_3_.INIT = 16'h6996; + LUT4_L com_llm_llm_rx_top_llm_rx_dllp_crc_llm_rx_crc16_d32_st_new_c32_1_3_ ( + .I0(N_10387), + .I1(N_27394_i_0), + .I2(com_llm_llm_rx_top_llm_rx_dllp_crc_llm_rx_crc16_d32_st_new_c32_1_1_3__1627), + .I3(com_llm_llm_rx_top_llm_rx_dllp_crc_llm_rx_crc16_d32_st_new_c32_1_i_1_3_), + .LO(com_llm_llm_rx_top_llm_rx_dllp_crc_new_c32_1_i_3_) + ); + defparam com_llm_llm_rx_top_llm_rx_dllp_crc_llm_rx_crc16_d32_st_new_c32_st_i_2_.INIT = 16'h9669; + LUT4_L com_llm_llm_rx_top_llm_rx_dllp_crc_llm_rx_crc16_d32_st_new_c32_st_i_2_ ( + .I0(N_228), + .I1(N_10416), + .I2(N_10548), + .I3(com_llm_llm_rx_top_llm_rx_dllp_crc_llm_rx_crc16_d32_st_new_c32_1_0_2__1628), + .LO(com_llm_llm_rx_top_llm_rx_dllp_crc_new_c32_st_i_2_) + ); + defparam com_llm_llm_rx_top_llm_rx_dllp_crc_llm_rx_crc16_d32_st_new_c32_st_i_1_.INIT = 16'h9669; + LUT4_L com_llm_llm_rx_top_llm_rx_dllp_crc_llm_rx_crc16_d32_st_new_c32_st_i_1_ ( + .I0(N_10401), + .I1(N_10597), + .I2(com_llm_llm_rx_top_llm_rx_dllp_crc_llm_rx_crc16_d32_st_new_c32_1_1_1__1629), + .I3(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_20_), + .LO(com_llm_llm_rx_top_llm_rx_dllp_crc_new_c32_st_i_1_) + ); + defparam com_llm_llm_rx_top_llm_rx_dllp_crc_llm_rx_crc16_d32_st_new_c32_1_0_.INIT = 16'h6996; + LUT4_L com_llm_llm_rx_top_llm_rx_dllp_crc_llm_rx_crc16_d32_st_new_c32_1_0_ ( + .I0(N_10396), + .I1(N_27394_i_0), + .I2(com_llm_llm_rx_top_llm_rx_dllp_crc_llm_rx_crc16_d32_st_new_c32_1_0_0__1630), + .I3(com_llm_llm_rx_top_llm_rx_dllp_crc_llm_rx_crc16_d32_st_new_c32_1_i_1_0_), + .LO(com_llm_llm_rx_top_llm_rx_dllp_crc_new_c32_1_i_0_) + ); + defparam com_llm_llm_rx_top_llm_rx_dllp_crc_llm_rx_crc16_d32_st_new_c32_st_i_15_.INIT = 16'h9669; + LUT4_L com_llm_llm_rx_top_llm_rx_dllp_crc_llm_rx_crc16_d32_st_new_c32_st_i_15_ ( + .I0(N_10374), + .I1(N_10422), + .I2(com_llm_llm_rx_top_llm_rx_dllp_crc_llm_rx_crc16_d32_st_new_c32_1_2_15__1631), + .I3(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_4_), + .LO(com_llm_llm_rx_top_llm_rx_dllp_crc_new_c32_st_i_15_) + ); + defparam com_llm_llm_rx_top_llm_rx_dllp_crc_llm_rx_crc16_d32_st_new_c32_st_i_14_.INIT = 8'h69; + LUT3_L com_llm_llm_rx_top_llm_rx_dllp_crc_llm_rx_crc16_d32_st_new_c32_st_i_14_ ( + .I0(N_10535), + .I1(N_10548_1), + .I2(com_llm_llm_rx_top_rx_data_57_), + .LO(com_llm_llm_rx_top_llm_rx_dllp_crc_new_c32_st_i_14_) + ); + defparam com_llm_llm_rx_top_llm_rx_dllp_crc_llm_rx_crc16_d32_st_new_c32_1_13_.INIT = 16'h6996; + LUT4_L com_llm_llm_rx_top_llm_rx_dllp_crc_llm_rx_crc16_d32_st_new_c32_1_13_ ( + .I0(N_208_1), + .I1(N_228), + .I2(N_10597), + .I3(com_llm_llm_rx_top_llm_rx_dllp_crc_llm_rx_crc16_d32_st_new_c32_1_0_13__1632), + .LO(com_llm_llm_rx_top_llm_rx_dllp_crc_new_c32_1_i_13_) + ); + defparam com_llm_llm_rx_top_llm_rx_dllp_crc_llm_rx_crc16_d32_st_new_c32_1_12_.INIT = 16'h6996; + LUT4_L com_llm_llm_rx_top_llm_rx_dllp_crc_llm_rx_crc16_d32_st_new_c32_1_12_ ( + .I0(N_10374), + .I1(N_10458), + .I2(com_llm_llm_rx_top_llm_rx_dllp_crc_llm_rx_crc16_d32_st_new_c32_1_0_12__1633), + .I3(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_4_), + .LO(com_llm_llm_rx_top_llm_rx_dllp_crc_new_c32_1_i_12_) + ); + defparam com_llm_llm_rx_top_llm_rx_dllp_crc_llm_rx_crc16_d32_st_new_c32_st_i_11_.INIT = 16'h9669; + LUT4_L com_llm_llm_rx_top_llm_rx_dllp_crc_llm_rx_crc16_d32_st_new_c32_st_i_11_ ( + .I0(N_198), + .I1(N_10535), + .I2(com_llm_llm_rx_top_llm_rx_dllp_crc_llm_rx_crc16_d32_st_new_c32_1_1_11__1634), + .I3(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_5_), + .LO(com_llm_llm_rx_top_llm_rx_dllp_crc_new_c32_st_i_11_) + ); + defparam com_llm_llm_rx_top_llm_rx_dllp_crc_llm_rx_crc16_d32_st_new_c32_st_i_10_.INIT = 16'h9669; + LUT4_L com_llm_llm_rx_top_llm_rx_dllp_crc_llm_rx_crc16_d32_st_new_c32_st_i_10_ ( + .I0(N_219), + .I1(N_10374), + .I2(N_27386_i_0), + .I3(com_llm_llm_rx_top_llm_rx_dllp_crc_llm_rx_crc16_d32_st_new_c32_1_2_10__1635), + .LO(com_llm_llm_rx_top_llm_rx_dllp_crc_new_c32_st_i_10_) + ); + defparam com_llm_llm_rx_top_llm_rx_dllp_crc_llm_rx_crc16_d32_st_new_c32_1_9_.INIT = 16'h6996; + LUT4_L com_llm_llm_rx_top_llm_rx_dllp_crc_llm_rx_crc16_d32_st_new_c32_1_9_ ( + .I0(N_10430), + .I1(com_llm_llm_rx_top_llm_rx_dllp_crc_llm_rx_crc16_d32_st_new_c32_1_0_9__1636), + .I2(com_llm_llm_rx_top_llm_rx_dllp_crc_llm_rx_crc16_d32_st_new_c32_1_i_1_0_), + .I3(com_llm_llm_rx_top_llm_rx_dllp_crc_llm_rx_crc16_d32_st_new_c32_1_i_1_4_), + .LO(com_llm_llm_rx_top_llm_rx_dllp_crc_new_c32_1_i_9_) + ); + defparam com_llm_llm_rx_top_llm_rx_dllp_crc_llm_rx_crc16_d32_st_new_c32_st_i_8_.INIT = 16'h9669; + LUT4_L com_llm_llm_rx_top_llm_rx_dllp_crc_llm_rx_crc16_d32_st_new_c32_st_i_8_ ( + .I0(N_10392_1), + .I1(N_10396), + .I2(N_10541), + .I3(com_llm_llm_rx_top_llm_rx_dllp_crc_llm_rx_crc16_d32_st_new_c32_1_2_8__1637), + .LO(com_llm_llm_rx_top_llm_rx_dllp_crc_new_c32_st_i_8_) + ); + defparam com_llm_llm_rx_top_llm_rx_dllp_crc_llm_rx_crc16_d32_nst_new_c32_1_0_2_.INIT = 4'h6; + LUT2 com_llm_llm_rx_top_llm_rx_dllp_crc_llm_rx_crc16_d32_nst_new_c32_1_0_2_ ( + .I0(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_42_), + .I1(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_51_), + .O(com_llm_llm_rx_top_llm_rx_dllp_crc_llm_rx_crc16_d32_nst_new_c32_1_0_2__1643) + ); + defparam com_llm_llm_rx_top_llm_rx_dllp_crc_llm_rx_crc16_d32_nst_new_c32_1_2_15_.INIT = 16'h6996; + LUT4 com_llm_llm_rx_top_llm_rx_dllp_crc_llm_rx_crc16_d32_nst_new_c32_1_2_15_ ( + .I0(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_24_), + .I1(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q[28]), + .I2(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_35_), + .I3(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_43_), + .O(com_llm_llm_rx_top_llm_rx_dllp_crc_llm_rx_crc16_d32_nst_new_c32_1_2_15__1645) + ); + defparam com_llm_llm_rx_top_llm_rx_dllp_crc_llm_rx_crc16_d32_nst_new_c32_1_1_13_.INIT = 16'h6996; + LUT4 com_llm_llm_rx_top_llm_rx_dllp_crc_llm_rx_crc16_d32_nst_new_c32_1_1_13_ ( + .I0(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_26_), + .I1(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_37_), + .I2(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_45_), + .I3(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_53_), + .O(com_llm_llm_rx_top_llm_rx_dllp_crc_llm_rx_crc16_d32_nst_new_c32_1_1_13__1646) + ); + defparam com_llm_llm_rx_top_llm_rx_dllp_crc_llm_rx_crc16_d32_nst_new_c32_1_1_0_0_.INIT = 8'h96; + LUT3_L com_llm_llm_rx_top_llm_rx_dllp_crc_llm_rx_crc16_d32_nst_new_c32_1_1_0_0_ ( + .I0(N_27395_i_0), + .I1(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_32_), + .I2(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_34_), + .LO(com_llm_llm_rx_top_llm_rx_dllp_crc_llm_rx_crc16_d32_nst_new_c32_1_1_0_) + ); + defparam com_llm_llm_rx_top_llm_rx_dllp_crc_llm_rx_crc16_d32_nst_new_c32_1_1_10_.INIT = 8'h96; + LUT3 com_llm_llm_rx_top_llm_rx_dllp_crc_llm_rx_crc16_d32_nst_new_c32_1_1_10_ ( + .I0(N_253_1), + .I1(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_38_), + .I2(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_50_), + .O(com_llm_llm_rx_top_llm_rx_dllp_crc_llm_rx_crc16_d32_nst_new_c32_1_1_10__1649) + ); + defparam com_llm_llm_rx_top_llm_rx_dllp_crc_llm_rx_crc16_d32_nst_new_c32_1_1_3_3_.INIT = 16'h6996; + LUT4 com_llm_llm_rx_top_llm_rx_dllp_crc_llm_rx_crc16_d32_nst_new_c32_1_1_3_3_ ( + .I0(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_29_), + .I1(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_41_), + .I2(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_48_), + .I3(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_49_), + .O(com_llm_llm_rx_top_llm_rx_dllp_crc_llm_rx_crc16_d32_nst_new_c32_1_1_3__1642) + ); + defparam com_llm_llm_rx_top_llm_rx_dllp_crc_llm_rx_crc16_d32_nst_new_c32_1_1_4_.INIT = 16'h6996; + LUT4 com_llm_llm_rx_top_llm_rx_dllp_crc_llm_rx_crc16_d32_nst_new_c32_1_1_4_ ( + .I0(N_206), + .I1(N_254_1), + .I2(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_38_), + .I3(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_46_), + .O(com_llm_llm_rx_top_llm_rx_dllp_crc_llm_rx_crc16_d32_nst_new_c32_1_i_1[4]) + ); + defparam com_llm_llm_rx_top_llm_rx_dllp_crc_llm_rx_crc16_d32_nst_new_c32_1_0_12_.INIT = 16'h6996; + LUT4 com_llm_llm_rx_top_llm_rx_dllp_crc_llm_rx_crc16_d32_nst_new_c32_1_0_12_ ( + .I0(N_254_1), + .I1(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_38_), + .I2(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_46_), + .I3(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_55_), + .O(com_llm_llm_rx_top_llm_rx_dllp_crc_llm_rx_crc16_d32_nst_new_c32_1_0_12__1647) + ); + defparam com_llm_llm_rx_top_llm_rx_dllp_crc_llm_rx_crc16_d32_nst_new_c32_1_1_2_3_.INIT = 16'h6996; + LUT4_L com_llm_llm_rx_top_llm_rx_dllp_crc_llm_rx_crc16_d32_nst_new_c32_1_1_2_3_ ( + .I0(N_247), + .I1(N_253_1), + .I2(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_47_), + .I3(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_55_), + .LO(com_llm_llm_rx_top_llm_rx_dllp_crc_llm_rx_crc16_d32_nst_new_c32_1_1_2[3]) + ); + defparam com_llm_llm_rx_top_llm_rx_dllp_crc_llm_rx_crc16_d32_nst_new_c32_1_1_1_.INIT = 16'h6996; + LUT4_L com_llm_llm_rx_top_llm_rx_dllp_crc_llm_rx_crc16_d32_nst_new_c32_1_1_1_ ( + .I0(N_254_1), + .I1(N_10459), + .I2(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_32_), + .I3(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_55_), + .LO(com_llm_llm_rx_top_llm_rx_dllp_crc_llm_rx_crc16_d32_nst_new_c32_1_1_1__1644) + ); + defparam com_llm_llm_rx_top_llm_rx_dllp_crc_llm_rx_crc16_d32_nst_new_c32_1_1_11_.INIT = 16'h6996; + LUT4 com_llm_llm_rx_top_llm_rx_dllp_crc_llm_rx_crc16_d32_nst_new_c32_1_1_11_ ( + .I0(N_254_1), + .I1(N_10386), + .I2(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_32_), + .I3(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_55_), + .O(com_llm_llm_rx_top_llm_rx_dllp_crc_llm_rx_crc16_d32_nst_new_c32_1_1_11__1648) + ); + defparam com_llm_llm_rx_top_llm_rx_dllp_crc_llm_rx_crc16_d32_nst_new_c32_1_2_4_.INIT = 16'h6996; + LUT4 com_llm_llm_rx_top_llm_rx_dllp_crc_llm_rx_crc16_d32_nst_new_c32_1_2_4_ ( + .I0(N_10417), + .I1(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_26_), + .I2(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_27_), + .I3(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q[28]), + .O(com_llm_llm_rx_top_llm_rx_dllp_crc_llm_rx_crc16_d32_nst_new_c32_1_2_4__1641) + ); + defparam com_llm_llm_rx_top_llm_rx_dllp_crc_llm_rx_crc16_d32_nst_new_c32_1_1_7_.INIT = 16'h6996; + LUT4 com_llm_llm_rx_top_llm_rx_dllp_crc_llm_rx_crc16_d32_nst_new_c32_1_1_7_ ( + .I0(N_253_1), + .I1(N_10431), + .I2(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_47_), + .I3(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_55_), + .O(com_llm_llm_rx_top_llm_rx_dllp_crc_llm_rx_crc16_d32_nst_new_c32_1_1_7__1639) + ); + defparam com_llm_llm_rx_top_llm_rx_dllp_crc_llm_rx_crc16_d32_nst_new_c32_1_1_8_.INIT = 16'h6996; + LUT4 com_llm_llm_rx_top_llm_rx_dllp_crc_llm_rx_crc16_d32_nst_new_c32_1_1_8_ ( + .I0(N_254_1), + .I1(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_26_), + .I2(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_38_), + .I3(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_49_), + .O(com_llm_llm_rx_top_llm_rx_dllp_crc_llm_rx_crc16_d32_nst_new_c32_1_1_8__1638) + ); + defparam com_llm_llm_rx_top_llm_rx_dllp_crc_llm_rx_crc16_d32_nst_new_c32_1_1_5_.INIT = 8'h96; + LUT3 com_llm_llm_rx_top_llm_rx_dllp_crc_llm_rx_crc16_d32_nst_new_c32_1_1_5_ ( + .I0(N_10405), + .I1(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_38_), + .I2(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_44_), + .O(com_llm_llm_rx_top_llm_rx_dllp_crc_llm_rx_crc16_d32_nst_new_c32_1_1_5__1640) + ); + defparam com_llm_llm_rx_top_llm_rx_dllp_crc_llm_rx_crc16_d32_nst_new_c32_1_1_3_.INIT = 16'h6996; + LUT4 com_llm_llm_rx_top_llm_rx_dllp_crc_llm_rx_crc16_d32_nst_new_c32_1_1_3_ ( + .I0(N_217), + .I1(com_llm_llm_rx_top_llm_rx_dllp_crc_llm_rx_crc16_d32_nst_new_c32_1_1_2[3]), + .I2(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_25_), + .I3(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q[28]), + .O(com_llm_llm_rx_top_llm_rx_dllp_crc_llm_rx_crc16_d32_nst_new_c32_1_i_1[3]) + ); + defparam com_llm_llm_rx_top_llm_rx_dllp_crc_llm_rx_crc16_d32_nst_new_c32_1_1_9_.INIT = 8'h96; + LUT3 com_llm_llm_rx_top_llm_rx_dllp_crc_llm_rx_crc16_d32_nst_new_c32_1_1_9_ ( + .I0(N_179), + .I1(N_10431), + .I2(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_49_), + .O(com_llm_llm_rx_top_llm_rx_dllp_crc_llm_rx_crc16_d32_nst_new_c32_1_1_9__1650) + ); + defparam com_llm_llm_rx_top_llm_rx_dllp_crc_llm_rx_crc16_d32_nst_new_c32_nst_i_8_.INIT = 16'h9669; + LUT4_L com_llm_llm_rx_top_llm_rx_dllp_crc_llm_rx_crc16_d32_nst_new_c32_nst_i_8_ ( + .I0(N_247), + .I1(N_259), + .I2(N_10542), + .I3(com_llm_llm_rx_top_llm_rx_dllp_crc_llm_rx_crc16_d32_nst_new_c32_1_1_8__1638), + .LO(com_llm_llm_rx_top_llm_rx_dllp_crc_new_c32_nst_i_8_) + ); + defparam com_llm_llm_rx_top_llm_rx_dllp_crc_llm_rx_crc16_d32_nst_new_c32_1_7_.INIT = 16'h6996; + LUT4_L com_llm_llm_rx_top_llm_rx_dllp_crc_llm_rx_crc16_d32_nst_new_c32_1_7_ ( + .I0(N_247_1), + .I1(N_10405), + .I2(N_10542), + .I3(com_llm_llm_rx_top_llm_rx_dllp_crc_llm_rx_crc16_d32_nst_new_c32_1_1_7__1639), + .LO(com_llm_llm_rx_top_llm_rx_dllp_crc_new_c32_1_i_0_7_) + ); + defparam com_llm_llm_rx_top_llm_rx_dllp_crc_llm_rx_crc16_d32_nst_new_c32_nst_i_6_.INIT = 8'h69; + LUT3_L com_llm_llm_rx_top_llm_rx_dllp_crc_llm_rx_crc16_d32_nst_new_c32_nst_i_6_ ( + .I0(N_178), + .I1(N_10400), + .I2(com_llm_llm_rx_top_llm_rx_dllp_crc_llm_rx_crc16_d32_nst_new_c32_1_i_1[3]), + .LO(com_llm_llm_rx_top_llm_rx_dllp_crc_new_c32_nst_i_6_) + ); + defparam com_llm_llm_rx_top_llm_rx_dllp_crc_llm_rx_crc16_d32_nst_new_c32_1_5_.INIT = 16'h6996; + LUT4_L com_llm_llm_rx_top_llm_rx_dllp_crc_llm_rx_crc16_d32_nst_new_c32_1_5_ ( + .I0(N_217), + .I1(N_10386), + .I2(N_10547), + .I3(com_llm_llm_rx_top_llm_rx_dllp_crc_llm_rx_crc16_d32_nst_new_c32_1_1_5__1640), + .LO(com_llm_llm_rx_top_llm_rx_dllp_crc_new_c32_1_i_0_5_) + ); + defparam com_llm_llm_rx_top_llm_rx_dllp_crc_llm_rx_crc16_d32_nst_new_c32_1_4_.INIT = 16'h6996; + LUT4_L com_llm_llm_rx_top_llm_rx_dllp_crc_llm_rx_crc16_d32_nst_new_c32_1_4_ ( + .I0(N_10386), + .I1(N_27385_i_0), + .I2(com_llm_llm_rx_top_llm_rx_dllp_crc_llm_rx_crc16_d32_nst_new_c32_1_2_4__1641), + .I3(com_llm_llm_rx_top_llm_rx_dllp_crc_llm_rx_crc16_d32_nst_new_c32_1_i_1[4]), + .LO(com_llm_llm_rx_top_llm_rx_dllp_crc_new_c32_1_i_0_4_) + ); + defparam com_llm_llm_rx_top_llm_rx_dllp_crc_llm_rx_crc16_d32_nst_new_c32_1_3_.INIT = 16'h6996; + LUT4_L com_llm_llm_rx_top_llm_rx_dllp_crc_llm_rx_crc16_d32_nst_new_c32_1_3_ ( + .I0(N_10386), + .I1(N_27395_i_0), + .I2(com_llm_llm_rx_top_llm_rx_dllp_crc_llm_rx_crc16_d32_nst_new_c32_1_1_3__1642), + .I3(com_llm_llm_rx_top_llm_rx_dllp_crc_llm_rx_crc16_d32_nst_new_c32_1_i_1[3]), + .LO(com_llm_llm_rx_top_llm_rx_dllp_crc_new_c32_1_i_0_3_) + ); + defparam com_llm_llm_rx_top_llm_rx_dllp_crc_llm_rx_crc16_d32_nst_new_c32_nst_i_2_.INIT = 16'h9669; + LUT4_L com_llm_llm_rx_top_llm_rx_dllp_crc_llm_rx_crc16_d32_nst_new_c32_nst_i_2_ ( + .I0(N_10385), + .I1(N_10417), + .I2(N_10547), + .I3(com_llm_llm_rx_top_llm_rx_dllp_crc_llm_rx_crc16_d32_nst_new_c32_1_0_2__1643), + .LO(com_llm_llm_rx_top_llm_rx_dllp_crc_new_c32_nst_i_2_) + ); + defparam com_llm_llm_rx_top_llm_rx_dllp_crc_llm_rx_crc16_d32_nst_new_c32_nst_i_1_.INIT = 16'h9669; + LUT4_L com_llm_llm_rx_top_llm_rx_dllp_crc_llm_rx_crc16_d32_nst_new_c32_nst_i_1_ ( + .I0(N_10400), + .I1(N_10598), + .I2(com_llm_llm_rx_top_llm_rx_dllp_crc_llm_rx_crc16_d32_nst_new_c32_1_1_1__1644), + .I3(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_52_), + .LO(com_llm_llm_rx_top_llm_rx_dllp_crc_new_c32_nst_i_1_) + ); + defparam com_llm_llm_rx_top_llm_rx_dllp_crc_llm_rx_crc16_d32_nst_new_c32_1_0_.INIT = 16'h6996; + LUT4_L com_llm_llm_rx_top_llm_rx_dllp_crc_llm_rx_crc16_d32_nst_new_c32_1_0_ ( + .I0(N_197), + .I1(N_259), + .I2(com_llm_llm_rx_top_llm_rx_dllp_crc_llm_rx_crc16_d32_nst_new_c32_1_1_0_), + .I3(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_39_), + .LO(com_llm_llm_rx_top_llm_rx_dllp_crc_new_c32_1_i_0_0_) + ); + defparam com_llm_llm_rx_top_llm_rx_dllp_crc_llm_rx_crc16_d32_nst_new_c32_nst_i_15_.INIT = 16'h9669; + LUT4_L com_llm_llm_rx_top_llm_rx_dllp_crc_llm_rx_crc16_d32_nst_new_c32_nst_i_15_ ( + .I0(N_178), + .I1(N_10421), + .I2(com_llm_llm_rx_top_llm_rx_dllp_crc_llm_rx_crc16_d32_nst_new_c32_1_2_15__1645), + .I3(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_36_), + .LO(com_llm_llm_rx_top_llm_rx_dllp_crc_new_c32_nst_i_15_) + ); + defparam com_llm_llm_rx_top_llm_rx_dllp_crc_llm_rx_crc16_d32_nst_new_c32_nst_i_14_.INIT = 16'h9669; + LUT4_L com_llm_llm_rx_top_llm_rx_dllp_crc_llm_rx_crc16_d32_nst_new_c32_nst_i_14_ ( + .I0(N_179), + .I1(N_10537), + .I2(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_25_), + .I3(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_29_), + .LO(com_llm_llm_rx_top_llm_rx_dllp_crc_new_c32_nst_i_14_) + ); + defparam com_llm_llm_rx_top_llm_rx_dllp_crc_llm_rx_crc16_d32_nst_new_c32_1_13_.INIT = 8'h96; + LUT3_L com_llm_llm_rx_top_llm_rx_dllp_crc_llm_rx_crc16_d32_nst_new_c32_1_13_ ( + .I0(N_10385), + .I1(N_10598), + .I2(com_llm_llm_rx_top_llm_rx_dllp_crc_llm_rx_crc16_d32_nst_new_c32_1_1_13__1646), + .LO(com_llm_llm_rx_top_llm_rx_dllp_crc_new_c32_1_i_0_13_) + ); + defparam com_llm_llm_rx_top_llm_rx_dllp_crc_llm_rx_crc16_d32_nst_new_c32_1_12_.INIT = 16'h6996; + LUT4_L com_llm_llm_rx_top_llm_rx_dllp_crc_llm_rx_crc16_d32_nst_new_c32_1_12_ ( + .I0(N_178), + .I1(N_10459), + .I2(com_llm_llm_rx_top_llm_rx_dllp_crc_llm_rx_crc16_d32_nst_new_c32_1_0_12__1647), + .I3(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_36_), + .LO(com_llm_llm_rx_top_llm_rx_dllp_crc_new_c32_1_i_0_12_) + ); + defparam com_llm_llm_rx_top_llm_rx_dllp_crc_llm_rx_crc16_d32_nst_new_c32_nst_i_11_.INIT = 16'h9669; + LUT4_L com_llm_llm_rx_top_llm_rx_dllp_crc_llm_rx_crc16_d32_nst_new_c32_nst_i_11_ ( + .I0(N_197), + .I1(N_10537), + .I2(com_llm_llm_rx_top_llm_rx_dllp_crc_llm_rx_crc16_d32_nst_new_c32_1_1_11__1648), + .I3(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_37_), + .LO(com_llm_llm_rx_top_llm_rx_dllp_crc_new_c32_nst_i_11_) + ); + defparam com_llm_llm_rx_top_llm_rx_dllp_crc_llm_rx_crc16_d32_nst_new_c32_nst_i_10_.INIT = 16'h9669; + LUT4_L com_llm_llm_rx_top_llm_rx_dllp_crc_llm_rx_crc16_d32_nst_new_c32_nst_i_10_ ( + .I0(N_10421), + .I1(N_10542_1), + .I2(N_27385_i_0), + .I3(com_llm_llm_rx_top_llm_rx_dllp_crc_llm_rx_crc16_d32_nst_new_c32_1_1_10__1649), + .LO(com_llm_llm_rx_top_llm_rx_dllp_crc_new_c32_nst_i_10_) + ); + defparam com_llm_llm_rx_top_llm_rx_dllp_crc_llm_rx_crc16_d32_nst_new_c32_1_9_.INIT = 16'h6996; + LUT4_L com_llm_llm_rx_top_llm_rx_dllp_crc_llm_rx_crc16_d32_nst_new_c32_1_9_ ( + .I0(N_197), + .I1(com_llm_llm_rx_top_llm_rx_dllp_crc_llm_rx_crc16_d32_nst_new_c32_1_1_9__1650), + .I2(com_llm_llm_rx_top_llm_rx_dllp_crc_llm_rx_crc16_d32_nst_new_c32_1_i_1[4]), + .I3(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_39_), + .LO(com_llm_llm_rx_top_llm_rx_dllp_crc_new_c32_1_i_0_9_) + ); + VCC com_llm_llm_rx_top_llm_rx_dllp_decode_VCC ( + .P(com_llm_llm_rx_top_llm_rx_dllp_decode_VCC_1653) + ); + GND com_llm_llm_rx_top_llm_rx_dllp_decode_GND ( + .G(com_llm_llm_rx_top_llm_rx_dllp_decode_GND_1652) + ); + defparam com_llm_llm_rx_top_llm_rx_dllp_decode_lnk_rfc_vc_n_20_u_i_0_0_m4_0_0_.INIT = 8'hB8; + LUT3 com_llm_llm_rx_top_llm_rx_dllp_decode_lnk_rfc_vc_n_20_u_i_0_0_m4_0_0_ ( + .I0(com_link_status[1]), + .I1(com_llm_rx_dllp[30]), + .I2(com_llm_rx_dllp[31]), + .O(com_llm_llm_rx_top_llm_rx_dllp_decode_N_41843) + ); + defparam com_llm_llm_rx_top_llm_rx_dllp_decode_link_update_fc_rcv_3_i_0_0_0_o2.INIT = 8'h70; + LUT3 com_llm_llm_rx_top_llm_rx_dllp_decode_link_update_fc_rcv_3_i_0_0_0_o2 ( + .I0(com_llm_llm_rx_top_rx_dllp[28]), + .I1(com_llm_rx_dllp[29]), + .I2(com_llm_rx_dllp_vld), + .O(com_llm_llm_rx_top_llm_rx_dllp_decode_N_41802_i) + ); + defparam com_llm_llm_rx_top_llm_rx_dllp_decode_link_li1_cpl_rcv_3_0_a2_0_a2_0_a2_1_0.INIT = 8'h40; + LUT3 com_llm_llm_rx_top_llm_rx_dllp_decode_link_li1_cpl_rcv_3_0_a2_0_a2_0_a2_1_0 ( + .I0(com_llm_llm_rx_top_rx_dllp[28]), + .I1(com_llm_rx_dllp[29]), + .I2(com_llm_rx_dllp_vld), + .O(com_llm_llm_rx_top_llm_rx_dllp_decode_link_li1_cpl_rcv_3_1_0) + ); + defparam com_llm_llm_rx_top_llm_rx_dllp_decode_lnk_rfc_vc_n_20_u_i_0_0_o2_0_.INIT = 16'h0001; + LUT4 com_llm_llm_rx_top_llm_rx_dllp_decode_lnk_rfc_vc_n_20_u_i_0_0_o2_0_ ( + .I0(com_llm_llm_rx_top_rx_dllp[24]), + .I1(com_llm_llm_rx_top_rx_dllp[25]), + .I2(com_llm_llm_rx_top_rx_dllp[26]), + .I3(com_llm_llm_rx_top_rx_dllp[27]), + .O(com_llm_N_41810_i) + ); + defparam com_llm_llm_rx_top_llm_rx_dllp_decode_cmml_rpm_ra_3_0_a2_0_a2_0_a2_1_0.INIT = 16'h0002; + LUT4_L com_llm_llm_rx_top_llm_rx_dllp_decode_cmml_rpm_ra_3_0_a2_0_a2_0_a2_1_0 ( + .I0(com_llm_llm_rx_top_llm_rx_dllp_decode_link_li1_cpl_rcv_3_1_0), + .I1(com_llm_llm_rx_top_rx_dllp[24]), + .I2(com_llm_llm_rx_top_rx_dllp[25]), + .I3(com_llm_llm_rx_top_rx_dllp[27]), + .LO(com_llm_llm_rx_top_llm_rx_dllp_decode_cmml_rpm_ra_3_0_a2_0_a2_0_a2_1) + ); + defparam com_llm_llm_rx_top_llm_rx_dllp_decode_link_li2_rcv_3_i_0_0.INIT = 8'h80; + LUT3_L com_llm_llm_rx_top_llm_rx_dllp_decode_link_li2_rcv_3_i_0_0 ( + .I0(com_llm_llm_rx_top_llm_rx_dllp_decode_N_41802_i), + .I1(com_llm_rx_dllp[30]), + .I2(com_llm_rx_dllp[31]), + .LO(com_llm_llm_rx_top_llm_rx_dllp_decode_N_12895_i) + ); + defparam com_llm_llm_rx_top_llm_rx_dllp_decode_link_li1_cpl_rcv_3_0_a2_0_a2_0_a2.INIT = 4'h8; + LUT2_L com_llm_llm_rx_top_llm_rx_dllp_decode_link_li1_cpl_rcv_3_0_a2_0_a2_0_a2 ( + .I0(com_llm_llm_rx_top_llm_rx_dllp_decode_link_li1_cpl_rcv_3_1_0), + .I1(com_llm_rx_dllp[30]), + .LO(com_llm_llm_rx_top_llm_rx_dllp_decode_link_li1_cpl_rcv_3) + ); + defparam com_llm_llm_rx_top_llm_rx_dllp_decode_link_li1_np_rcv_3_0_a2_0_a2_0_a2.INIT = 16'h2000; + LUT4_L com_llm_llm_rx_top_llm_rx_dllp_decode_link_li1_np_rcv_3_0_a2_0_a2_0_a2 ( + .I0(com_llm_llm_rx_top_rx_dllp[28]), + .I1(com_llm_rx_dllp[29]), + .I2(com_llm_rx_dllp[30]), + .I3(com_llm_rx_dllp_vld), + .LO(com_llm_llm_rx_top_llm_rx_dllp_decode_link_li1_np_rcv_3) + ); + defparam com_llm_llm_rx_top_llm_rx_dllp_decode_link_li1_p_rcv_3_0_a2_0_a2_0_a2.INIT = 16'h1000; + LUT4_L com_llm_llm_rx_top_llm_rx_dllp_decode_link_li1_p_rcv_3_0_a2_0_a2_0_a2 ( + .I0(com_llm_llm_rx_top_rx_dllp[28]), + .I1(com_llm_rx_dllp[29]), + .I2(com_llm_rx_dllp[30]), + .I3(com_llm_rx_dllp_vld), + .LO(com_llm_llm_rx_top_llm_rx_dllp_decode_link_li1_p_rcv_3) + ); + defparam com_llm_llm_rx_top_llm_rx_dllp_decode_link_update_fc_rcv_3_i_0_0_0.INIT = 8'h20; + LUT3_L com_llm_llm_rx_top_llm_rx_dllp_decode_link_update_fc_rcv_3_i_0_0_0 ( + .I0(com_llm_llm_rx_top_llm_rx_dllp_decode_N_41802_i), + .I1(com_llm_rx_dllp[30]), + .I2(com_llm_rx_dllp[31]), + .LO(com_llm_llm_rx_top_llm_rx_dllp_decode_N_12890_i) + ); + defparam com_llm_llm_rx_top_llm_rx_dllp_decode_cmml_rpm_ra_3_0_a2_0_a2_0_a2.INIT = 16'h0008; + LUT4_L com_llm_llm_rx_top_llm_rx_dllp_decode_cmml_rpm_ra_3_0_a2_0_a2_0_a2 ( + .I0(com_llm_llm_rx_top_llm_rx_dllp_decode_cmml_rpm_ra_3_0_a2_0_a2_0_a2_1), + .I1(com_llm_llm_rx_top_rx_dllp[26]), + .I2(com_llm_rx_dllp[30]), + .I3(com_llm_rx_dllp[31]), + .LO(com_llm_llm_rx_top_llm_rx_dllp_decode_cmml_rpm_ra_3) + ); + defparam com_llm_llm_rx_top_llm_rx_dllp_decode_reg_rx_dllp_nak_vld_0_a2_0_a2_0_a2.INIT = 8'h80; + LUT3_L com_llm_llm_rx_top_llm_rx_dllp_decode_reg_rx_dllp_nak_vld_0_a2_0_a2_0_a2 ( + .I0(com_llm_N_41810_i), + .I1(com_llm_ANSeqNum_Eq_AckdSeq_5_0_a2_0_a2_0_a2_1_0), + .I2(com_llm_llm_rx_top_rx_dllp[28]), + .LO(com_llm_reg_rx_dllp_nak_vld) + ); + defparam com_llm_llm_rx_top_llm_rx_dllp_decode_reg_rx_dllp_ack_vld_0_a2_0_a2_0_a2.INIT = 8'h08; + LUT3_L com_llm_llm_rx_top_llm_rx_dllp_decode_reg_rx_dllp_ack_vld_0_a2_0_a2_0_a2 ( + .I0(com_llm_N_41810_i), + .I1(com_llm_ANSeqNum_Eq_AckdSeq_5_0_a2_0_a2_0_a2_1_0), + .I2(com_llm_llm_rx_top_rx_dllp[28]), + .LO(com_llm_reg_rx_dllp_ack_vld) + ); + defparam com_llm_llm_rx_top_llm_rx_dllp_decode_N_67905_i.INIT = 8'h7F; + LUT3_L com_llm_llm_rx_top_llm_rx_dllp_decode_N_67905_i ( + .I0(com_llm_llm_rx_top_llm_rx_dllp_decode_N_41802_i), + .I1(com_llm_N_41810_i), + .I2(com_llm_llm_rx_top_llm_rx_dllp_decode_N_41843), + .LO(com_llm_llm_rx_top_llm_rx_dllp_decode_N_67905_i_1651) + ); + FD com_llm_llm_rx_top_llm_rx_dllp_decode_lnk_rfc_header_6_DOUT_0_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_dllp_decode_lnk_rfc_header_6_N_6), + .Q(com_lnk_rfc_header[7]) + ); + FD com_llm_llm_rx_top_llm_rx_dllp_decode_lnk_rfc_header_5_DOUT_0_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_dllp_decode_lnk_rfc_header_5_N_6), + .Q(com_lnk_rfc_header[6]) + ); + FD com_llm_llm_rx_top_llm_rx_dllp_decode_lnk_rfc_header_4_DOUT_0_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_dllp_decode_lnk_rfc_header_4_N_6), + .Q(com_lnk_rfc_header[5]) + ); + FD com_llm_llm_rx_top_llm_rx_dllp_decode_lnk_rfc_header_3_DOUT_0_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_dllp_decode_lnk_rfc_header_3_N_6), + .Q(com_lnk_rfc_header[4]) + ); + FD com_llm_llm_rx_top_llm_rx_dllp_decode_lnk_rfc_header_2_DOUT_0_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_dllp_decode_lnk_rfc_header_2_N_6), + .Q(com_lnk_rfc_header[3]) + ); + FD com_llm_llm_rx_top_llm_rx_dllp_decode_lnk_rfc_header_1_DOUT_0_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_dllp_decode_lnk_rfc_header_1_N_6), + .Q(com_lnk_rfc_header[2]) + ); + FD com_llm_llm_rx_top_llm_rx_dllp_decode_lnk_rfc_header_0_DOUT_0_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_dllp_decode_lnk_rfc_header_0_N_6), + .Q(com_lnk_rfc_header[1]) + ); + FD com_llm_llm_rx_top_llm_rx_dllp_decode_lnk_rfc_header_DOUT_0_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_dllp_decode_lnk_rfc_header_N_6), + .Q(com_lnk_rfc_header[0]) + ); + FDC com_llm_llm_rx_top_llm_rx_dllp_decode_link_li2_rcv ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_dllp_decode_N_12895_i), + .Q(com_llm_link_li2_rcv), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_dllp_decode_link_li1_cpl_rcv ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_dllp_decode_link_li1_cpl_rcv_3), + .Q(com_llm_link_li1_cpl_rcv), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_dllp_decode_link_li1_np_rcv ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_dllp_decode_link_li1_np_rcv_3), + .Q(com_llm_link_li1_np_rcv), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_dllp_decode_link_li1_p_rcv ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_dllp_decode_link_li1_p_rcv_3), + .Q(com_llm_link_li1_p_rcv), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_dllp_decode_link_update_fc_rcv ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_dllp_decode_N_12890_i), + .Q(com_llm_link_update_fc_rcv), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_dllp_decode_cmml_rpm_ra ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_dllp_decode_cmml_rpm_ra_3), + .Q(com_cmml_rpm_ra), + .CLR(plm_link_up_i) + ); + FDP com_llm_llm_rx_top_llm_rx_dllp_decode_lnk_rfc_vc_n_0_ ( + .PRE(plm_link_up_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_dllp_decode_N_67905_i_1651), + .Q(com_lnk_rfc_vc_n[0]) + ); + FDC com_llm_llm_rx_top_llm_rx_dllp_decode_link_vc_rcv_0_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_N_41810_i), + .Q(com_llm_link_vc_rcv[0]), + .CLR(plm_link_up_i) + ); + FD com_llm_llm_rx_top_llm_rx_dllp_decode_lnk_rfc_data_11_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_reg_rx_dllp_tsn[11]), + .Q(com_lnk_rfc_data[11]) + ); + FD com_llm_llm_rx_top_llm_rx_dllp_decode_lnk_rfc_data_10_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_reg_rx_dllp_tsn[10]), + .Q(com_lnk_rfc_data[10]) + ); + FD com_llm_llm_rx_top_llm_rx_dllp_decode_lnk_rfc_data_9_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_reg_rx_dllp_tsn[9]), + .Q(com_lnk_rfc_data[9]) + ); + FD com_llm_llm_rx_top_llm_rx_dllp_decode_lnk_rfc_data_8_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_reg_rx_dllp_tsn[8]), + .Q(com_lnk_rfc_data[8]) + ); + FD com_llm_llm_rx_top_llm_rx_dllp_decode_lnk_rfc_data_7_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_reg_rx_dllp_tsn[7]), + .Q(com_lnk_rfc_data[7]) + ); + FD com_llm_llm_rx_top_llm_rx_dllp_decode_lnk_rfc_data_6_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_reg_rx_dllp_tsn[6]), + .Q(com_lnk_rfc_data[6]) + ); + FD com_llm_llm_rx_top_llm_rx_dllp_decode_lnk_rfc_data_5_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_reg_rx_dllp_tsn[5]), + .Q(com_lnk_rfc_data[5]) + ); + FD com_llm_llm_rx_top_llm_rx_dllp_decode_lnk_rfc_data_4_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_reg_rx_dllp_tsn[4]), + .Q(com_lnk_rfc_data[4]) + ); + FD com_llm_llm_rx_top_llm_rx_dllp_decode_lnk_rfc_data_3_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_reg_rx_dllp_tsn[3]), + .Q(com_lnk_rfc_data[3]) + ); + FD com_llm_llm_rx_top_llm_rx_dllp_decode_lnk_rfc_data_2_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_reg_rx_dllp_tsn[2]), + .Q(com_lnk_rfc_data[2]) + ); + FD com_llm_llm_rx_top_llm_rx_dllp_decode_lnk_rfc_data_1_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_reg_rx_dllp_tsn[1]), + .Q(com_lnk_rfc_data[1]) + ); + FD com_llm_llm_rx_top_llm_rx_dllp_decode_lnk_rfc_data_0_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_reg_rx_dllp_tsn[0]), + .Q(com_lnk_rfc_data[0]) + ); + FD com_llm_llm_rx_top_llm_rx_dllp_decode_lnk_rfc_type_2_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_rx_dllp[30]), + .Q(com_lnk_rfc_type[2]) + ); + FD com_llm_llm_rx_top_llm_rx_dllp_decode_lnk_rfc_type_1_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_rx_dllp[29]), + .Q(com_lnk_rfc_type[1]) + ); + FD com_llm_llm_rx_top_llm_rx_dllp_decode_lnk_rfc_type_0_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_rx_dllp[28]), + .Q(com_lnk_rfc_type[0]) + ); + SRL16 com_llm_llm_rx_top_llm_rx_dllp_decode_lnk_rfc_header_6_I_1 ( + .D(com_llm_llm_rx_top_rx_dllp_d_4_i_m3_0_21_), + .Q(com_llm_llm_rx_top_llm_rx_dllp_decode_lnk_rfc_header_6_N_6), + .CLK(NlwRenamedSig_OI_trn_clk), + .A0(com_llm_llm_rx_top_llm_rx_dllp_decode_VCC_1653), + .A1(com_llm_llm_rx_top_llm_rx_dllp_decode_GND_1652), + .A2(com_llm_llm_rx_top_llm_rx_dllp_decode_GND_1652), + .A3(com_llm_llm_rx_top_llm_rx_dllp_decode_GND_1652) + ); + SRL16 com_llm_llm_rx_top_llm_rx_dllp_decode_lnk_rfc_header_5_I_1 ( + .D(com_llm_llm_rx_top_rx_dllp_d_4_i_m2_i_m3_0[20]), + .Q(com_llm_llm_rx_top_llm_rx_dllp_decode_lnk_rfc_header_5_N_6), + .CLK(NlwRenamedSig_OI_trn_clk), + .A0(com_llm_llm_rx_top_llm_rx_dllp_decode_VCC_1653), + .A1(com_llm_llm_rx_top_llm_rx_dllp_decode_GND_1652), + .A2(com_llm_llm_rx_top_llm_rx_dllp_decode_GND_1652), + .A3(com_llm_llm_rx_top_llm_rx_dllp_decode_GND_1652) + ); + SRL16 com_llm_llm_rx_top_llm_rx_dllp_decode_lnk_rfc_header_4_I_1 ( + .D(com_llm_llm_rx_top_rx_dllp_d_4_i_m2_i_m3_0[19]), + .Q(com_llm_llm_rx_top_llm_rx_dllp_decode_lnk_rfc_header_4_N_6), + .CLK(NlwRenamedSig_OI_trn_clk), + .A0(com_llm_llm_rx_top_llm_rx_dllp_decode_VCC_1653), + .A1(com_llm_llm_rx_top_llm_rx_dllp_decode_GND_1652), + .A2(com_llm_llm_rx_top_llm_rx_dllp_decode_GND_1652), + .A3(com_llm_llm_rx_top_llm_rx_dllp_decode_GND_1652) + ); + SRL16 com_llm_llm_rx_top_llm_rx_dllp_decode_lnk_rfc_header_3_I_1 ( + .D(com_llm_llm_rx_top_rx_dllp_d_4_i_m2_i_m3_0[18]), + .Q(com_llm_llm_rx_top_llm_rx_dllp_decode_lnk_rfc_header_3_N_6), + .CLK(NlwRenamedSig_OI_trn_clk), + .A0(com_llm_llm_rx_top_llm_rx_dllp_decode_VCC_1653), + .A1(com_llm_llm_rx_top_llm_rx_dllp_decode_GND_1652), + .A2(com_llm_llm_rx_top_llm_rx_dllp_decode_GND_1652), + .A3(com_llm_llm_rx_top_llm_rx_dllp_decode_GND_1652) + ); + SRL16 com_llm_llm_rx_top_llm_rx_dllp_decode_lnk_rfc_header_2_I_1 ( + .D(com_llm_llm_rx_top_rx_dllp_d_4_i_m2_i_m3_0[17]), + .Q(com_llm_llm_rx_top_llm_rx_dllp_decode_lnk_rfc_header_2_N_6), + .CLK(NlwRenamedSig_OI_trn_clk), + .A0(com_llm_llm_rx_top_llm_rx_dllp_decode_VCC_1653), + .A1(com_llm_llm_rx_top_llm_rx_dllp_decode_GND_1652), + .A2(com_llm_llm_rx_top_llm_rx_dllp_decode_GND_1652), + .A3(com_llm_llm_rx_top_llm_rx_dllp_decode_GND_1652) + ); + SRL16 com_llm_llm_rx_top_llm_rx_dllp_decode_lnk_rfc_header_1_I_1 ( + .D(com_llm_llm_rx_top_rx_dllp_d_4_i_m2_i_m3_0[16]), + .Q(com_llm_llm_rx_top_llm_rx_dllp_decode_lnk_rfc_header_1_N_6), + .CLK(NlwRenamedSig_OI_trn_clk), + .A0(com_llm_llm_rx_top_llm_rx_dllp_decode_VCC_1653), + .A1(com_llm_llm_rx_top_llm_rx_dllp_decode_GND_1652), + .A2(com_llm_llm_rx_top_llm_rx_dllp_decode_GND_1652), + .A3(com_llm_llm_rx_top_llm_rx_dllp_decode_GND_1652) + ); + SRL16 com_llm_llm_rx_top_llm_rx_dllp_decode_lnk_rfc_header_0_I_1 ( + .D(com_llm_llm_rx_top_rx_dllp_d_4_i_m3_0_15_), + .Q(com_llm_llm_rx_top_llm_rx_dllp_decode_lnk_rfc_header_0_N_6), + .CLK(NlwRenamedSig_OI_trn_clk), + .A0(com_llm_llm_rx_top_llm_rx_dllp_decode_VCC_1653), + .A1(com_llm_llm_rx_top_llm_rx_dllp_decode_GND_1652), + .A2(com_llm_llm_rx_top_llm_rx_dllp_decode_GND_1652), + .A3(com_llm_llm_rx_top_llm_rx_dllp_decode_GND_1652) + ); + SRL16 com_llm_llm_rx_top_llm_rx_dllp_decode_lnk_rfc_header_I_1 ( + .D(com_llm_llm_rx_top_rx_dllp_d_4_i_m3_0_14_), + .Q(com_llm_llm_rx_top_llm_rx_dllp_decode_lnk_rfc_header_N_6), + .CLK(NlwRenamedSig_OI_trn_clk), + .A0(com_llm_llm_rx_top_llm_rx_dllp_decode_VCC_1653), + .A1(com_llm_llm_rx_top_llm_rx_dllp_decode_GND_1652), + .A2(com_llm_llm_rx_top_llm_rx_dllp_decode_GND_1652), + .A3(com_llm_llm_rx_top_llm_rx_dllp_decode_GND_1652) + ); + VCC com_llm_llm_rx_top_llm_rx_tlp_crc_VCC ( + .P(com_llm_llm_rx_top_llm_rx_tlp_crc_VCC_1661) + ); + GND com_llm_llm_rx_top_llm_rx_tlp_crc_GND ( + .G(com_llm_llm_rx_top_llm_rx_tlp_crc_GND_1678) + ); + MUXCY_L com_llm_llm_rx_top_llm_rx_tlp_crc_un3_crc32_com_ok_0_I_1 ( + .CI(com_llm_llm_rx_top_llm_rx_tlp_crc_VCC_1661), + .DI(com_llm_llm_rx_top_llm_rx_tlp_crc_GND_1678), + .LO(com_llm_llm_rx_top_llm_rx_tlp_crc_data_tmp_0[0]), + .S(com_llm_llm_rx_top_llm_rx_tlp_crc_N_123) + ); + MUXCY_L com_llm_llm_rx_top_llm_rx_tlp_crc_un3_crc32_com_ok_0_I_10 ( + .CI(com_llm_llm_rx_top_llm_rx_tlp_crc_data_tmp_0[0]), + .DI(com_llm_llm_rx_top_llm_rx_tlp_crc_GND_1678), + .LO(com_llm_llm_rx_top_llm_rx_tlp_crc_data_tmp_0[1]), + .S(com_llm_llm_rx_top_llm_rx_tlp_crc_N_115) + ); + MUXCY_L com_llm_llm_rx_top_llm_rx_tlp_crc_un3_crc32_com_ok_0_I_19 ( + .CI(com_llm_llm_rx_top_llm_rx_tlp_crc_data_tmp_0[1]), + .DI(com_llm_llm_rx_top_llm_rx_tlp_crc_GND_1678), + .LO(com_llm_llm_rx_top_llm_rx_tlp_crc_data_tmp_0[2]), + .S(com_llm_llm_rx_top_llm_rx_tlp_crc_N_107) + ); + MUXCY_L com_llm_llm_rx_top_llm_rx_tlp_crc_un3_crc32_com_ok_0_I_37 ( + .CI(com_llm_llm_rx_top_llm_rx_tlp_crc_data_tmp_0[10]), + .DI(com_llm_llm_rx_top_llm_rx_tlp_crc_GND_1678), + .LO(com_llm_llm_rx_top_llm_rx_tlp_crc_data_tmp_0[11]), + .S(com_llm_llm_rx_top_llm_rx_tlp_crc_N_91) + ); + MUXCY_L com_llm_llm_rx_top_llm_rx_tlp_crc_un3_crc32_com_ok_0_I_46 ( + .CI(com_llm_llm_rx_top_llm_rx_tlp_crc_data_tmp_0[4]), + .DI(com_llm_llm_rx_top_llm_rx_tlp_crc_GND_1678), + .LO(com_llm_llm_rx_top_llm_rx_tlp_crc_data_tmp_0[5]), + .S(com_llm_llm_rx_top_llm_rx_tlp_crc_N_83) + ); + MUXCY_L com_llm_llm_rx_top_llm_rx_tlp_crc_un3_crc32_com_ok_0_I_55 ( + .CI(com_llm_llm_rx_top_llm_rx_tlp_crc_data_tmp_0[5]), + .DI(com_llm_llm_rx_top_llm_rx_tlp_crc_GND_1678), + .LO(com_llm_llm_rx_top_llm_rx_tlp_crc_data_tmp_0[6]), + .S(com_llm_llm_rx_top_llm_rx_tlp_crc_N_75) + ); + MUXCY_L com_llm_llm_rx_top_llm_rx_tlp_crc_un3_crc32_com_ok_0_I_64 ( + .CI(com_llm_llm_rx_top_llm_rx_tlp_crc_data_tmp_0[11]), + .DI(com_llm_llm_rx_top_llm_rx_tlp_crc_GND_1678), + .LO(com_llm_llm_rx_top_llm_rx_tlp_crc_data_tmp_0[12]), + .S(com_llm_llm_rx_top_llm_rx_tlp_crc_N_67) + ); + MUXCY_L com_llm_llm_rx_top_llm_rx_tlp_crc_un3_crc32_com_ok_0_I_73 ( + .CI(com_llm_llm_rx_top_llm_rx_tlp_crc_data_tmp_0[6]), + .DI(com_llm_llm_rx_top_llm_rx_tlp_crc_GND_1678), + .LO(com_llm_llm_rx_top_llm_rx_tlp_crc_data_tmp_0[7]), + .S(com_llm_llm_rx_top_llm_rx_tlp_crc_N_59) + ); + MUXCY_L com_llm_llm_rx_top_llm_rx_tlp_crc_un3_crc32_com_ok_0_I_82 ( + .CI(com_llm_llm_rx_top_llm_rx_tlp_crc_data_tmp_0[8]), + .DI(com_llm_llm_rx_top_llm_rx_tlp_crc_GND_1678), + .LO(com_llm_llm_rx_top_llm_rx_tlp_crc_data_tmp_0[9]), + .S(com_llm_llm_rx_top_llm_rx_tlp_crc_N_51) + ); + MUXCY_L com_llm_llm_rx_top_llm_rx_tlp_crc_un3_crc32_com_ok_0_I_91 ( + .CI(com_llm_llm_rx_top_llm_rx_tlp_crc_data_tmp_0[9]), + .DI(com_llm_llm_rx_top_llm_rx_tlp_crc_GND_1678), + .LO(com_llm_llm_rx_top_llm_rx_tlp_crc_data_tmp_0[10]), + .S(com_llm_llm_rx_top_llm_rx_tlp_crc_N_43) + ); + MUXCY_L com_llm_llm_rx_top_llm_rx_tlp_crc_un3_crc32_com_ok_0_I_100 ( + .CI(com_llm_llm_rx_top_llm_rx_tlp_crc_data_tmp_0[7]), + .DI(com_llm_llm_rx_top_llm_rx_tlp_crc_GND_1678), + .LO(com_llm_llm_rx_top_llm_rx_tlp_crc_data_tmp_0[8]), + .S(com_llm_llm_rx_top_llm_rx_tlp_crc_N_35) + ); + MUXCY_L com_llm_llm_rx_top_llm_rx_tlp_crc_un3_crc32_com_ok_0_I_109 ( + .CI(com_llm_llm_rx_top_llm_rx_tlp_crc_data_tmp_0[2]), + .DI(com_llm_llm_rx_top_llm_rx_tlp_crc_GND_1678), + .LO(com_llm_llm_rx_top_llm_rx_tlp_crc_data_tmp_0[3]), + .S(com_llm_llm_rx_top_llm_rx_tlp_crc_N_27) + ); + MUXCY_L com_llm_llm_rx_top_llm_rx_tlp_crc_un3_crc32_com_ok_0_I_118 ( + .CI(com_llm_llm_rx_top_llm_rx_tlp_crc_data_tmp_0[12]), + .DI(com_llm_llm_rx_top_llm_rx_tlp_crc_GND_1678), + .LO(com_llm_llm_rx_top_llm_rx_tlp_crc_data_tmp_0[13]), + .S(com_llm_llm_rx_top_llm_rx_tlp_crc_N_19) + ); + MUXCY_L com_llm_llm_rx_top_llm_rx_tlp_crc_un3_crc32_com_ok_0_I_127 ( + .CI(com_llm_llm_rx_top_llm_rx_tlp_crc_data_tmp_0[13]), + .DI(com_llm_llm_rx_top_llm_rx_tlp_crc_GND_1678), + .LO(com_llm_llm_rx_top_llm_rx_tlp_crc_data_tmp[14]), + .S(com_llm_llm_rx_top_llm_rx_tlp_crc_N_11) + ); + MUXCY_L com_llm_llm_rx_top_llm_rx_tlp_crc_un3_crc32_com_ok_0_I_136 ( + .CI(com_llm_llm_rx_top_llm_rx_tlp_crc_data_tmp_0[3]), + .DI(com_llm_llm_rx_top_llm_rx_tlp_crc_GND_1678), + .LO(com_llm_llm_rx_top_llm_rx_tlp_crc_data_tmp_0[4]), + .S(com_llm_llm_rx_top_llm_rx_tlp_crc_N_3) + ); + MUXCY_L com_llm_llm_rx_top_llm_rx_tlp_crc_un4_crc32_com_ok_0_I_1 ( + .CI(com_llm_llm_rx_top_llm_rx_tlp_crc_VCC_1661), + .DI(com_llm_llm_rx_top_llm_rx_tlp_crc_GND_1678), + .LO(com_llm_llm_rx_top_llm_rx_tlp_crc_data_tmp[0]), + .S(com_llm_llm_rx_top_llm_rx_tlp_crc_N_123_0) + ); + MUXCY_L com_llm_llm_rx_top_llm_rx_tlp_crc_un4_crc32_com_ok_0_I_10 ( + .CI(com_llm_llm_rx_top_llm_rx_tlp_crc_data_tmp[0]), + .DI(com_llm_llm_rx_top_llm_rx_tlp_crc_GND_1678), + .LO(com_llm_llm_rx_top_llm_rx_tlp_crc_data_tmp[1]), + .S(com_llm_llm_rx_top_llm_rx_tlp_crc_N_115_0) + ); + MUXCY_L com_llm_llm_rx_top_llm_rx_tlp_crc_un4_crc32_com_ok_0_I_19 ( + .CI(com_llm_llm_rx_top_llm_rx_tlp_crc_data_tmp[1]), + .DI(com_llm_llm_rx_top_llm_rx_tlp_crc_GND_1678), + .LO(com_llm_llm_rx_top_llm_rx_tlp_crc_data_tmp[2]), + .S(com_llm_llm_rx_top_llm_rx_tlp_crc_N_107_0) + ); + MUXCY_L com_llm_llm_rx_top_llm_rx_tlp_crc_un4_crc32_com_ok_0_I_37 ( + .CI(com_llm_llm_rx_top_llm_rx_tlp_crc_data_tmp[10]), + .DI(com_llm_llm_rx_top_llm_rx_tlp_crc_GND_1678), + .LO(com_llm_llm_rx_top_llm_rx_tlp_crc_data_tmp[11]), + .S(com_llm_llm_rx_top_llm_rx_tlp_crc_N_91_0) + ); + MUXCY_L com_llm_llm_rx_top_llm_rx_tlp_crc_un4_crc32_com_ok_0_I_46 ( + .CI(com_llm_llm_rx_top_llm_rx_tlp_crc_data_tmp[4]), + .DI(com_llm_llm_rx_top_llm_rx_tlp_crc_GND_1678), + .LO(com_llm_llm_rx_top_llm_rx_tlp_crc_data_tmp[5]), + .S(com_llm_llm_rx_top_llm_rx_tlp_crc_N_83_0) + ); + MUXCY_L com_llm_llm_rx_top_llm_rx_tlp_crc_un4_crc32_com_ok_0_I_55 ( + .CI(com_llm_llm_rx_top_llm_rx_tlp_crc_data_tmp[5]), + .DI(com_llm_llm_rx_top_llm_rx_tlp_crc_GND_1678), + .LO(com_llm_llm_rx_top_llm_rx_tlp_crc_data_tmp[6]), + .S(com_llm_llm_rx_top_llm_rx_tlp_crc_N_75_0) + ); + MUXCY_L com_llm_llm_rx_top_llm_rx_tlp_crc_un4_crc32_com_ok_0_I_64 ( + .CI(com_llm_llm_rx_top_llm_rx_tlp_crc_data_tmp[11]), + .DI(com_llm_llm_rx_top_llm_rx_tlp_crc_GND_1678), + .LO(com_llm_llm_rx_top_llm_rx_tlp_crc_data_tmp[12]), + .S(com_llm_llm_rx_top_llm_rx_tlp_crc_N_67_0) + ); + MUXCY_L com_llm_llm_rx_top_llm_rx_tlp_crc_un4_crc32_com_ok_0_I_73 ( + .CI(com_llm_llm_rx_top_llm_rx_tlp_crc_data_tmp[6]), + .DI(com_llm_llm_rx_top_llm_rx_tlp_crc_GND_1678), + .LO(com_llm_llm_rx_top_llm_rx_tlp_crc_data_tmp[7]), + .S(com_llm_llm_rx_top_llm_rx_tlp_crc_N_59_0) + ); + MUXCY_L com_llm_llm_rx_top_llm_rx_tlp_crc_un4_crc32_com_ok_0_I_82 ( + .CI(com_llm_llm_rx_top_llm_rx_tlp_crc_data_tmp[8]), + .DI(com_llm_llm_rx_top_llm_rx_tlp_crc_GND_1678), + .LO(com_llm_llm_rx_top_llm_rx_tlp_crc_data_tmp[9]), + .S(com_llm_llm_rx_top_llm_rx_tlp_crc_N_51_0) + ); + MUXCY_L com_llm_llm_rx_top_llm_rx_tlp_crc_un4_crc32_com_ok_0_I_91 ( + .CI(com_llm_llm_rx_top_llm_rx_tlp_crc_data_tmp[9]), + .DI(com_llm_llm_rx_top_llm_rx_tlp_crc_GND_1678), + .LO(com_llm_llm_rx_top_llm_rx_tlp_crc_data_tmp[10]), + .S(com_llm_llm_rx_top_llm_rx_tlp_crc_N_43_0) + ); + MUXCY_L com_llm_llm_rx_top_llm_rx_tlp_crc_un4_crc32_com_ok_0_I_100 ( + .CI(com_llm_llm_rx_top_llm_rx_tlp_crc_data_tmp[7]), + .DI(com_llm_llm_rx_top_llm_rx_tlp_crc_GND_1678), + .LO(com_llm_llm_rx_top_llm_rx_tlp_crc_data_tmp[8]), + .S(com_llm_llm_rx_top_llm_rx_tlp_crc_N_35_0) + ); + MUXCY_L com_llm_llm_rx_top_llm_rx_tlp_crc_un4_crc32_com_ok_0_I_109 ( + .CI(com_llm_llm_rx_top_llm_rx_tlp_crc_data_tmp[2]), + .DI(com_llm_llm_rx_top_llm_rx_tlp_crc_GND_1678), + .LO(com_llm_llm_rx_top_llm_rx_tlp_crc_data_tmp[3]), + .S(com_llm_llm_rx_top_llm_rx_tlp_crc_N_27_0) + ); + MUXCY_L com_llm_llm_rx_top_llm_rx_tlp_crc_un4_crc32_com_ok_0_I_118 ( + .CI(com_llm_llm_rx_top_llm_rx_tlp_crc_data_tmp[12]), + .DI(com_llm_llm_rx_top_llm_rx_tlp_crc_GND_1678), + .LO(com_llm_llm_rx_top_llm_rx_tlp_crc_data_tmp[13]), + .S(com_llm_llm_rx_top_llm_rx_tlp_crc_N_19_0) + ); + MUXCY_L com_llm_llm_rx_top_llm_rx_tlp_crc_un4_crc32_com_ok_0_I_127 ( + .CI(com_llm_llm_rx_top_llm_rx_tlp_crc_data_tmp[13]), + .DI(com_llm_llm_rx_top_llm_rx_tlp_crc_GND_1678), + .LO(com_llm_llm_rx_top_llm_rx_tlp_crc_data_tmp_0[14]), + .S(com_llm_llm_rx_top_llm_rx_tlp_crc_N_11_0) + ); + MUXCY_L com_llm_llm_rx_top_llm_rx_tlp_crc_un4_crc32_com_ok_0_I_136 ( + .CI(com_llm_llm_rx_top_llm_rx_tlp_crc_data_tmp[3]), + .DI(com_llm_llm_rx_top_llm_rx_tlp_crc_GND_1678), + .LO(com_llm_llm_rx_top_llm_rx_tlp_crc_data_tmp[4]), + .S(com_llm_llm_rx_top_llm_rx_tlp_crc_N_3_0) + ); + MUXCY_L com_llm_llm_rx_top_llm_rx_tlp_crc_un6_crc32_res_ok_0 ( + .CI(com_llm_llm_rx_top_llm_rx_tlp_crc_VCC_1661), + .DI(com_llm_llm_rx_top_llm_rx_tlp_crc_GND_1678), + .LO(com_llm_llm_rx_top_llm_rx_tlp_crc_un6_crc32_res_ok_0_1654), + .S(com_llm_llm_rx_top_llm_rx_tlp_crc_un6_crc32_res_ok_0_and) + ); + MUXCY_L com_llm_llm_rx_top_llm_rx_tlp_crc_un6_crc32_res_ok_1 ( + .CI(com_llm_llm_rx_top_llm_rx_tlp_crc_un6_crc32_res_ok_0_1654), + .DI(com_llm_llm_rx_top_llm_rx_tlp_crc_GND_1678), + .LO(com_llm_llm_rx_top_llm_rx_tlp_crc_un6_crc32_res_ok_1_1655), + .S(com_llm_llm_rx_top_llm_rx_tlp_crc_un6_crc32_res_ok_1_and) + ); + MUXCY_L com_llm_llm_rx_top_llm_rx_tlp_crc_un6_crc32_res_ok_2 ( + .CI(com_llm_llm_rx_top_llm_rx_tlp_crc_un6_crc32_res_ok_1_1655), + .DI(com_llm_llm_rx_top_llm_rx_tlp_crc_GND_1678), + .LO(com_llm_llm_rx_top_llm_rx_tlp_crc_un6_crc32_res_ok_2_1656), + .S(com_llm_llm_rx_top_llm_rx_tlp_crc_un6_crc32_res_ok_2_and) + ); + MUXCY_L com_llm_llm_rx_top_llm_rx_tlp_crc_un6_crc32_res_ok_3 ( + .CI(com_llm_llm_rx_top_llm_rx_tlp_crc_un6_crc32_res_ok_2_1656), + .DI(com_llm_llm_rx_top_llm_rx_tlp_crc_GND_1678), + .LO(com_llm_llm_rx_top_llm_rx_tlp_crc_un6_crc32_res_ok_3_1657), + .S(com_llm_llm_rx_top_llm_rx_tlp_crc_un6_crc32_res_ok_3_and) + ); + MUXCY_L com_llm_llm_rx_top_llm_rx_tlp_crc_un6_crc32_res_ok_4 ( + .CI(com_llm_llm_rx_top_llm_rx_tlp_crc_un6_crc32_res_ok_3_1657), + .DI(com_llm_llm_rx_top_llm_rx_tlp_crc_GND_1678), + .LO(com_llm_llm_rx_top_llm_rx_tlp_crc_un6_crc32_res_ok_4_1658), + .S(com_llm_llm_rx_top_llm_rx_tlp_crc_un6_crc32_res_ok_4_and) + ); + MUXCY_L com_llm_llm_rx_top_llm_rx_tlp_crc_un6_crc32_res_ok_5 ( + .CI(com_llm_llm_rx_top_llm_rx_tlp_crc_un6_crc32_res_ok_4_1658), + .DI(com_llm_llm_rx_top_llm_rx_tlp_crc_GND_1678), + .LO(com_llm_llm_rx_top_llm_rx_tlp_crc_un6_crc32_res_ok_5_1659), + .S(com_llm_llm_rx_top_llm_rx_tlp_crc_un6_crc32_res_ok_5_and) + ); + MUXCY_L com_llm_llm_rx_top_llm_rx_tlp_crc_un6_crc32_res_ok_6 ( + .CI(com_llm_llm_rx_top_llm_rx_tlp_crc_un6_crc32_res_ok_5_1659), + .DI(com_llm_llm_rx_top_llm_rx_tlp_crc_GND_1678), + .LO(com_llm_llm_rx_top_llm_rx_tlp_crc_un6_crc32_res_ok_6_1660), + .S(com_llm_llm_rx_top_llm_rx_tlp_crc_un6_crc32_res_ok_6_and) + ); + MUXCY com_llm_llm_rx_top_llm_rx_tlp_crc_un6_crc32_res_ok_7 ( + .CI(com_llm_llm_rx_top_llm_rx_tlp_crc_un6_crc32_res_ok_6_1660), + .DI(com_llm_llm_rx_top_llm_rx_tlp_crc_GND_1678), + .O(com_llm_llm_rx_top_llm_rx_tlp_crc_un6_crc32_res_ok_7_1669), + .S(com_llm_llm_rx_top_llm_rx_tlp_crc_un6_crc32_res_ok_7_and) + ); + MUXCY_L com_llm_llm_rx_top_llm_rx_tlp_crc_un3_crc32_res_ok_0 ( + .CI(com_llm_llm_rx_top_llm_rx_tlp_crc_VCC_1661), + .DI(com_llm_llm_rx_top_llm_rx_tlp_crc_GND_1678), + .LO(com_llm_llm_rx_top_llm_rx_tlp_crc_un3_crc32_res_ok_0_1662), + .S(com_llm_llm_rx_top_llm_rx_tlp_crc_un3_crc32_res_ok_0_and) + ); + MUXCY_L com_llm_llm_rx_top_llm_rx_tlp_crc_un3_crc32_res_ok_1 ( + .CI(com_llm_llm_rx_top_llm_rx_tlp_crc_un3_crc32_res_ok_0_1662), + .DI(com_llm_llm_rx_top_llm_rx_tlp_crc_GND_1678), + .LO(com_llm_llm_rx_top_llm_rx_tlp_crc_un3_crc32_res_ok_1_1663), + .S(com_llm_llm_rx_top_llm_rx_tlp_crc_un3_crc32_res_ok_1_and) + ); + MUXCY_L com_llm_llm_rx_top_llm_rx_tlp_crc_un3_crc32_res_ok_2 ( + .CI(com_llm_llm_rx_top_llm_rx_tlp_crc_un3_crc32_res_ok_1_1663), + .DI(com_llm_llm_rx_top_llm_rx_tlp_crc_GND_1678), + .LO(com_llm_llm_rx_top_llm_rx_tlp_crc_un3_crc32_res_ok_2_1664), + .S(com_llm_llm_rx_top_llm_rx_tlp_crc_un3_crc32_res_ok_2_and) + ); + MUXCY_L com_llm_llm_rx_top_llm_rx_tlp_crc_un3_crc32_res_ok_3 ( + .CI(com_llm_llm_rx_top_llm_rx_tlp_crc_un3_crc32_res_ok_2_1664), + .DI(com_llm_llm_rx_top_llm_rx_tlp_crc_GND_1678), + .LO(com_llm_llm_rx_top_llm_rx_tlp_crc_un3_crc32_res_ok_3_1665), + .S(com_llm_llm_rx_top_llm_rx_tlp_crc_un3_crc32_res_ok_3_and) + ); + MUXCY_L com_llm_llm_rx_top_llm_rx_tlp_crc_un3_crc32_res_ok_4 ( + .CI(com_llm_llm_rx_top_llm_rx_tlp_crc_un3_crc32_res_ok_3_1665), + .DI(com_llm_llm_rx_top_llm_rx_tlp_crc_GND_1678), + .LO(com_llm_llm_rx_top_llm_rx_tlp_crc_un3_crc32_res_ok_4_1666), + .S(com_llm_llm_rx_top_llm_rx_tlp_crc_un3_crc32_res_ok_4_and) + ); + MUXCY_L com_llm_llm_rx_top_llm_rx_tlp_crc_un3_crc32_res_ok_5 ( + .CI(com_llm_llm_rx_top_llm_rx_tlp_crc_un3_crc32_res_ok_4_1666), + .DI(com_llm_llm_rx_top_llm_rx_tlp_crc_GND_1678), + .LO(com_llm_llm_rx_top_llm_rx_tlp_crc_un3_crc32_res_ok_5_1667), + .S(com_llm_llm_rx_top_llm_rx_tlp_crc_un3_crc32_res_ok_5_and) + ); + MUXCY_L com_llm_llm_rx_top_llm_rx_tlp_crc_un3_crc32_res_ok_6 ( + .CI(com_llm_llm_rx_top_llm_rx_tlp_crc_un3_crc32_res_ok_5_1667), + .DI(com_llm_llm_rx_top_llm_rx_tlp_crc_GND_1678), + .LO(com_llm_llm_rx_top_llm_rx_tlp_crc_un3_crc32_res_ok_6_1668), + .S(com_llm_llm_rx_top_llm_rx_tlp_crc_un3_crc32_res_ok_6_and) + ); + MUXCY com_llm_llm_rx_top_llm_rx_tlp_crc_un3_crc32_res_ok_7 ( + .CI(com_llm_llm_rx_top_llm_rx_tlp_crc_un3_crc32_res_ok_6_1668), + .DI(com_llm_llm_rx_top_llm_rx_tlp_crc_GND_1678), + .O(com_llm_llm_rx_top_llm_rx_tlp_crc_un3_crc32_res_ok_7_1670), + .S(com_llm_llm_rx_top_llm_rx_tlp_crc_un3_crc32_res_ok_7_and) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_un3_crc32_res_ok_7_and_0_a2_1.INIT = 4'h1; + LUT2 com_llm_llm_rx_top_llm_rx_tlp_crc_un3_crc32_res_ok_7_and_0_a2_1 ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d16[28]), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d16[29]), + .O(com_llm_llm_rx_top_llm_rx_tlp_crc_un3_crc32_res_ok_7_and_1) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_rx_tlp_eof_nq6_0_0_o3.INIT = 4'h1; + LUT2 com_llm_llm_rx_top_llm_rx_tlp_crc_rx_tlp_eof_nq6_0_0_o3 ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_tlp_in_progress_1783), + .I1(com_llm_llm_rx_top_rx_tlp_sof_n), + .O(com_llm_llm_rx_top_llm_rx_tlp_crc_N_27378_i) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_un1_tlp_in_progress13_i_x4_0_x4.INIT = 4'h6; + LUT2 com_llm_llm_rx_top_llm_rx_tlp_crc_un1_tlp_in_progress13_i_x4_0_x4 ( + .I0(com_llm_llm_rx_top_rx_tlp_eof_n), + .I1(com_llm_llm_rx_top_rx_tlp_sof_n), + .O(com_llm_llm_rx_top_llm_rx_tlp_crc_N_27393_i_0) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_c64_0_a2_0_a2_27_.INIT = 4'h1; + LUT2 com_llm_llm_rx_top_llm_rx_tlp_crc_c64_0_a2_0_a2_27_ ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d64_27__323), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_initial_64_51), + .O(N_27654) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_c64_0_a2_0_a2_23_.INIT = 4'h1; + LUT2 com_llm_llm_rx_top_llm_rx_tlp_crc_c64_0_a2_0_a2_23_ ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d64_23__315), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_initial_64_51), + .O(N_27658) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_c64_0_a2_0_a2_20_.INIT = 4'h1; + LUT2 com_llm_llm_rx_top_llm_rx_tlp_crc_c64_0_a2_0_a2_20_ ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d64_20__54), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_initial_64_51), + .O(N_27661) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_c64_0_a2_0_a2_17_.INIT = 4'h1; + LUT2 com_llm_llm_rx_top_llm_rx_tlp_crc_c64_0_a2_0_a2_17_ ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d64_17__313), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_initial_64_51), + .O(N_27664) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_c64_0_a2_0_a2_16_.INIT = 4'h1; + LUT2 com_llm_llm_rx_top_llm_rx_tlp_crc_c64_0_a2_0_a2_16_ ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d64_16__47), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_initial_64_51), + .O(N_27665) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_c64_0_a2_0_a2_15_.INIT = 4'h1; + LUT2 com_llm_llm_rx_top_llm_rx_tlp_crc_c64_0_a2_0_a2_15_ ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d64_15__287), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_initial_64_51), + .O(N_27666) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_c64_0_a2_0_a2_10_.INIT = 4'h1; + LUT2 com_llm_llm_rx_top_llm_rx_tlp_crc_c64_0_a2_0_a2_10_ ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d64_10__1759), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_initial_64_51), + .O(N_27671) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_c64_0_a2_0_a2_2_.INIT = 4'h1; + LUT2 com_llm_llm_rx_top_llm_rx_tlp_crc_c64_0_a2_0_a2_2_ ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d64_2__53), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_initial_64_51), + .O(N_27679) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_c64_0_a2_0_a2_1_.INIT = 4'h1; + LUT2 com_llm_llm_rx_top_llm_rx_tlp_crc_c64_0_a2_0_a2_1_ ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d64_1__1761), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_initial_64_51), + .O(N_27680) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_un1_RX_RSRC_DSC_N17_0_0_o3.INIT = 4'h1; + LUT2 com_llm_llm_rx_top_llm_rx_tlp_crc_un1_RX_RSRC_DSC_N17_0_0_o3 ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_end_low_latch_1780), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_start_high_latch_qq_1684), + .O(com_llm_llm_rx_top_llm_rx_tlp_crc_N_27369_i) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_c64_0_a2_0_a2_3_.INIT = 4'h1; + LUT2 com_llm_llm_rx_top_llm_rx_tlp_crc_c64_0_a2_0_a2_3_ ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d64_3__52), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_initial_64_51), + .O(N_27678) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_c64_0_a2_0_a2_4_.INIT = 4'h1; + LUT2 com_llm_llm_rx_top_llm_rx_tlp_crc_c64_0_a2_0_a2_4_ ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d64_4__1760), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_initial_64_51), + .O(N_27677) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_c64_0_a2_0_a2_26_.INIT = 4'h1; + LUT2 com_llm_llm_rx_top_llm_rx_tlp_crc_c64_0_a2_0_a2_26_ ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d64_26__283), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_initial_64_51), + .O(N_27655) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_end_low_latch_3_0_a2_0_a2.INIT = 4'h2; + LUT2 com_llm_llm_rx_top_llm_rx_tlp_crc_end_low_latch_3_0_a2_0_a2 ( + .I0(com_llm_llm_rx_top_rx_tlp_sof_n), + .I1(com_llm_llm_rx_top_rx_tlp_vld_l_n), + .O(com_llm_llm_rx_top_llm_rx_tlp_crc_end_low_latch_3) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_RX_TLP_CRC_ERR_N_6_i_0_a2_0_0.INIT = 4'h1; + LUT2 com_llm_llm_rx_top_llm_rx_tlp_crc_RX_TLP_CRC_ERR_N_6_i_0_a2_0_0 ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_aligned_unaligned_1688), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_unaligned_aligned_1687), + .O(com_llm_llm_rx_top_llm_rx_tlp_crc_RX_TLP_CRC_ERR_N_6_i_0_a2_0_0_1672) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_d64_i_m3_0_7_.INIT = 8'hE4; + LUT3 com_llm_llm_rx_top_llm_rx_tlp_crc_d64_i_m3_0_7_ ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_start_high_latch_309), + .I1(com_llm_llm_rx_top_rx_data_24_), + .I2(com_llm_llm_rx_top_rx_data_56_), + .O(N_27372) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_d64_i_m3_0_12_.INIT = 8'hB8; + LUT3 com_llm_llm_rx_top_llm_rx_tlp_crc_d64_i_m3_0_12_ ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_data_q_5080[3]), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_start_high_latch_309), + .I2(com_llm_llm_rx_top_rx_data_35_), + .O(N_27373) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_d64_i_m3_0_21_.INIT = 8'hB8; + LUT3 com_llm_llm_rx_top_llm_rx_tlp_crc_d64_i_m3_0_21_ ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_2_), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_start_high_latch_309), + .I2(com_llm_llm_rx_top_rx_data_42_), + .O(N_27374) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_un1_RX_RSRC_DSC_N17_0_0_m2_0.INIT = 8'hE4; + LUT3 com_llm_llm_rx_top_llm_rx_tlp_crc_un1_RX_RSRC_DSC_N17_0_0_m2_0 ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_dw_3q_1690), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_frame_error_latch_1779), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_frame_error_latch_q_1685), + .O(com_llm_llm_rx_top_llm_rx_tlp_crc_N_27375) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_d16_i_m3_i_m3_0_14_.INIT = 8'hCA; + LUT3 com_llm_llm_rx_top_llm_rx_tlp_crc_d16_i_m3_i_m3_0_14_ ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_9_), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_41_), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_start_high_latch_q_308), + .O(N_27376) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_d16_i_m3_0_8_.INIT = 8'hCA; + LUT3 com_llm_llm_rx_top_llm_rx_tlp_crc_d16_i_m3_0_8_ ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_15_), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_47_), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_start_high_latch_q_308), + .O(N_27404) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_d64_i_m3_0_1_.INIT = 8'hE4; + LUT3 com_llm_llm_rx_top_llm_rx_tlp_crc_d64_i_m3_0_1_ ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_start_high_latch_309), + .I1(com_llm_llm_rx_top_rx_data_30_), + .I2(com_llm_llm_rx_top_rx_data_62_), + .O(N_27406) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_d64_i_m3_0_2_.INIT = 8'hE4; + LUT3 com_llm_llm_rx_top_llm_rx_tlp_crc_d64_i_m3_0_2_ ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_start_high_latch_309), + .I1(com_llm_llm_rx_top_rx_data_29_), + .I2(com_llm_llm_rx_top_rx_data_61_), + .O(N_27407) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_d64_i_m3_0_3_.INIT = 8'hE4; + LUT3 com_llm_llm_rx_top_llm_rx_tlp_crc_d64_i_m3_0_3_ ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_start_high_latch_309), + .I1(com_llm_llm_rx_top_rx_data_28_), + .I2(com_llm_llm_rx_top_rx_data_60_), + .O(N_27408) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_d64_i_m3_0_5_.INIT = 8'hE4; + LUT3 com_llm_llm_rx_top_llm_rx_tlp_crc_d64_i_m3_0_5_ ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_start_high_latch_309), + .I1(com_llm_llm_rx_top_rx_data_26_), + .I2(com_llm_llm_rx_top_rx_data_58_), + .O(N_27410) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_d64_i_m3_0_6_.INIT = 8'hE4; + LUT3 com_llm_llm_rx_top_llm_rx_tlp_crc_d64_i_m3_0_6_ ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_start_high_latch_309), + .I1(com_llm_llm_rx_top_rx_data_25_), + .I2(com_llm_llm_rx_top_rx_data_57_), + .O(N_27411) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_d64_i_m3_0_8_.INIT = 8'hB8; + LUT3 com_llm_llm_rx_top_llm_rx_tlp_crc_d64_i_m3_0_8_ ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_data_q_5080[7]), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_start_high_latch_309), + .I2(com_llm_llm_rx_top_rx_data_39_), + .O(N_27412) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_d64_i_m3_0_9_.INIT = 8'hB8; + LUT3 com_llm_llm_rx_top_llm_rx_tlp_crc_d64_i_m3_0_9_ ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_data_q_5080[6]), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_start_high_latch_309), + .I2(com_llm_llm_rx_top_rx_data_38_), + .O(N_27413) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_d64_i_m3_0_10_.INIT = 8'hB8; + LUT3 com_llm_llm_rx_top_llm_rx_tlp_crc_d64_i_m3_0_10_ ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_data_q_5080[5]), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_start_high_latch_309), + .I2(com_llm_llm_rx_top_rx_data_37_), + .O(N_27414) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_d64_i_m3_0_11_.INIT = 8'hB8; + LUT3 com_llm_llm_rx_top_llm_rx_tlp_crc_d64_i_m3_0_11_ ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_data_q_5080[4]), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_start_high_latch_309), + .I2(com_llm_llm_rx_top_rx_data_36_), + .O(N_27415) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_d64_i_m3_0_13_.INIT = 8'hB8; + LUT3 com_llm_llm_rx_top_llm_rx_tlp_crc_d64_i_m3_0_13_ ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_data_q_5080[2]), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_start_high_latch_309), + .I2(com_llm_llm_rx_top_rx_data_34_), + .O(N_27416) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_d64_i_m3_0_15_.INIT = 8'hB8; + LUT3 com_llm_llm_rx_top_llm_rx_tlp_crc_d64_i_m3_0_15_ ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_data_q[0]), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_start_high_latch_309), + .I2(com_llm_llm_rx_top_rx_data_32_), + .O(N_27418) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_d64_i_m3_0_16_.INIT = 8'hB8; + LUT3 com_llm_llm_rx_top_llm_rx_tlp_crc_d64_i_m3_0_16_ ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_7_), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_start_high_latch_309), + .I2(com_llm_llm_rx_top_rx_data_47_), + .O(N_27419) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_d64_i_m3_0_17_.INIT = 8'hB8; + LUT3 com_llm_llm_rx_top_llm_rx_tlp_crc_d64_i_m3_0_17_ ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_6_), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_start_high_latch_309), + .I2(com_llm_llm_rx_top_rx_data_46_), + .O(N_27420) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_d64_i_m3_0_18_.INIT = 8'hB8; + LUT3 com_llm_llm_rx_top_llm_rx_tlp_crc_d64_i_m3_0_18_ ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_5_), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_start_high_latch_309), + .I2(com_llm_llm_rx_top_rx_data_45_), + .O(N_27421) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_d64_i_m3_0_19_.INIT = 8'hB8; + LUT3 com_llm_llm_rx_top_llm_rx_tlp_crc_d64_i_m3_0_19_ ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_4_), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_start_high_latch_309), + .I2(com_llm_llm_rx_top_rx_data_44_), + .O(N_27422) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_d64_i_m3_0_20_.INIT = 8'hB8; + LUT3 com_llm_llm_rx_top_llm_rx_tlp_crc_d64_i_m3_0_20_ ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_3_), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_start_high_latch_309), + .I2(com_llm_llm_rx_top_rx_data_43_), + .O(N_27423) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_d64_i_m3_0_22_.INIT = 8'hB8; + LUT3 com_llm_llm_rx_top_llm_rx_tlp_crc_d64_i_m3_0_22_ ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_1_), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_start_high_latch_309), + .I2(com_llm_llm_rx_top_rx_data_41_), + .O(N_27424) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_d64_i_m3_0_23_.INIT = 8'hB8; + LUT3 com_llm_llm_rx_top_llm_rx_tlp_crc_d64_i_m3_0_23_ ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_0_), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_start_high_latch_309), + .I2(com_llm_llm_rx_top_rx_data_40_), + .O(N_27425) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_d64_i_m3_0_24_.INIT = 8'hB8; + LUT3 com_llm_llm_rx_top_llm_rx_tlp_crc_d64_i_m3_0_24_ ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_15_), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_start_high_latch_309), + .I2(com_llm_llm_rx_top_rx_data_55_), + .O(N_27426) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_d64_i_m3_0_33_.INIT = 8'hB8; + LUT3 com_llm_llm_rx_top_llm_rx_tlp_crc_d64_i_m3_0_33_ ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_22_), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_start_high_latch_309), + .I2(com_llm_llm_rx_top_rx_data_62_), + .O(N_27427) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_d64_i_m3_0_34_.INIT = 8'hB8; + LUT3 com_llm_llm_rx_top_llm_rx_tlp_crc_d64_i_m3_0_34_ ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_21_), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_start_high_latch_309), + .I2(com_llm_llm_rx_top_rx_data_61_), + .O(N_27428) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_d64_i_m3_0_35_.INIT = 8'hB8; + LUT3 com_llm_llm_rx_top_llm_rx_tlp_crc_d64_i_m3_0_35_ ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_20_), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_start_high_latch_309), + .I2(com_llm_llm_rx_top_rx_data_60_), + .O(N_27429) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_d64_i_m3_0_37_.INIT = 8'hB8; + LUT3 com_llm_llm_rx_top_llm_rx_tlp_crc_d64_i_m3_0_37_ ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_18_), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_start_high_latch_309), + .I2(com_llm_llm_rx_top_rx_data_58_), + .O(N_27430) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_d64_i_m3_0_39_.INIT = 8'hB8; + LUT3_L com_llm_llm_rx_top_llm_rx_tlp_crc_d64_i_m3_0_39_ ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_16_), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_start_high_latch_309), + .I2(com_llm_llm_rx_top_rx_data_56_), + .LO(N_27432) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_d64_i_m3_0_40_.INIT = 8'hCA; + LUT3_L com_llm_llm_rx_top_llm_rx_tlp_crc_d64_i_m3_0_40_ ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_data_q_5080[7]), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_31_), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_start_high_latch_309), + .LO(N_27433) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_d64_i_m3_0_41_.INIT = 8'hCA; + LUT3_L com_llm_llm_rx_top_llm_rx_tlp_crc_d64_i_m3_0_41_ ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_data_q_5080[6]), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_30_), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_start_high_latch_309), + .LO(N_27434) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_d64_i_m3_0_42_.INIT = 8'hCA; + LUT3 com_llm_llm_rx_top_llm_rx_tlp_crc_d64_i_m3_0_42_ ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_data_q_5080[5]), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_29_), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_start_high_latch_309), + .O(N_27435) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_d64_i_m3_0_43_.INIT = 8'hCA; + LUT3_L com_llm_llm_rx_top_llm_rx_tlp_crc_d64_i_m3_0_43_ ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_data_q_5080[4]), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_28_), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_start_high_latch_309), + .LO(N_27436) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_d64_i_m3_0_44_.INIT = 8'hCA; + LUT3_L com_llm_llm_rx_top_llm_rx_tlp_crc_d64_i_m3_0_44_ ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_data_q_5080[3]), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_27_), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_start_high_latch_309), + .LO(N_27437) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_d64_i_m3_0_45_.INIT = 8'hCA; + LUT3_L com_llm_llm_rx_top_llm_rx_tlp_crc_d64_i_m3_0_45_ ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_data_q_5080[2]), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_26_), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_start_high_latch_309), + .LO(N_27438) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_d64_i_m3_0_46_.INIT = 8'hCA; + LUT3_L com_llm_llm_rx_top_llm_rx_tlp_crc_d64_i_m3_0_46_ ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_data_q_5080[1]), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_25_), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_start_high_latch_309), + .LO(N_27439) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_d16_i_m3_i_m3_0_0_.INIT = 8'hCA; + LUT3 com_llm_llm_rx_top_llm_rx_tlp_crc_d16_i_m3_i_m3_0_0_ ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_7_), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_39_), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_start_high_latch_q_308), + .O(N_27488) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_d16_i_m3_i_m3_0_2_.INIT = 8'hCA; + LUT3 com_llm_llm_rx_top_llm_rx_tlp_crc_d16_i_m3_i_m3_0_2_ ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_5_), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_37_), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_start_high_latch_q_308), + .O(N_27490) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_d16_i_m3_i_m3_0_3_.INIT = 8'hCA; + LUT3 com_llm_llm_rx_top_llm_rx_tlp_crc_d16_i_m3_i_m3_0_3_ ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_4_), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_36_), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_start_high_latch_q_308), + .O(N_27491) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_d16_i_m3_i_m3_0_6_.INIT = 8'hCA; + LUT3 com_llm_llm_rx_top_llm_rx_tlp_crc_d16_i_m3_i_m3_0_6_ ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_1_), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_33_), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_start_high_latch_q_308), + .O(N_27494) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_d64_i_m3_i_m3_0_28_.INIT = 8'hB8; + LUT3 com_llm_llm_rx_top_llm_rx_tlp_crc_d64_i_m3_i_m3_0_28_ ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_11_), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_start_high_latch_309), + .I2(com_llm_llm_rx_top_rx_data_51_), + .O(N_27499) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_d64_i_m3_i_m3_0_30_.INIT = 8'hB8; + LUT3 com_llm_llm_rx_top_llm_rx_tlp_crc_d64_i_m3_i_m3_0_30_ ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_9_), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_start_high_latch_309), + .I2(com_llm_llm_rx_top_rx_data_49_), + .O(N_27501) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_d64_i_m3_i_m3_0_48_.INIT = 8'hCA; + LUT3 com_llm_llm_rx_top_llm_rx_tlp_crc_d64_i_m3_i_m3_0_48_ ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_7_), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_39_), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_start_high_latch_309), + .O(N_27503) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_d64_i_m3_i_m3_0_49_.INIT = 8'hCA; + LUT3 com_llm_llm_rx_top_llm_rx_tlp_crc_d64_i_m3_i_m3_0_49_ ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_6_), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_38_), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_start_high_latch_309), + .O(N_27504) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_d64_i_m3_i_m3_0_50_.INIT = 8'hCA; + LUT3_L com_llm_llm_rx_top_llm_rx_tlp_crc_d64_i_m3_i_m3_0_50_ ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_5_), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_37_), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_start_high_latch_309), + .LO(N_27505) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_d64_i_m3_i_m3_0_51_.INIT = 8'hCA; + LUT3_L com_llm_llm_rx_top_llm_rx_tlp_crc_d64_i_m3_i_m3_0_51_ ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_4_), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_36_), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_start_high_latch_309), + .LO(N_27506) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_d64_i_m3_i_m3_0_52_.INIT = 8'hCA; + LUT3 com_llm_llm_rx_top_llm_rx_tlp_crc_d64_i_m3_i_m3_0_52_ ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_3_), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_35_), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_start_high_latch_309), + .O(N_27507) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_d64_i_m3_i_m3_0_53_.INIT = 8'hCA; + LUT3_L com_llm_llm_rx_top_llm_rx_tlp_crc_d64_i_m3_i_m3_0_53_ ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_2_), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_34_), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_start_high_latch_309), + .LO(N_27508) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_d64_i_m3_i_m3_0_54_.INIT = 8'hCA; + LUT3_L com_llm_llm_rx_top_llm_rx_tlp_crc_d64_i_m3_i_m3_0_54_ ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_1_), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_33_), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_start_high_latch_309), + .LO(N_27509) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_d64_i_m3_i_m3_0_55_.INIT = 8'hCA; + LUT3 com_llm_llm_rx_top_llm_rx_tlp_crc_d64_i_m3_i_m3_0_55_ ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_0_), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_32_), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_start_high_latch_309), + .O(N_27510) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_d64_i_m3_i_m3_0_60_.INIT = 8'hCA; + LUT3 com_llm_llm_rx_top_llm_rx_tlp_crc_d64_i_m3_i_m3_0_60_ ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_11_), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_43_), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_start_high_latch_309), + .O(N_27511) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_d64_i_m3_i_m3_0_61_.INIT = 8'hCA; + LUT3_L com_llm_llm_rx_top_llm_rx_tlp_crc_d64_i_m3_i_m3_0_61_ ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_10_), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_42_), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_start_high_latch_309), + .LO(N_27512) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_d64_i_m3_i_m3_0_62_.INIT = 8'hCA; + LUT3_L com_llm_llm_rx_top_llm_rx_tlp_crc_d64_i_m3_i_m3_0_62_ ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_9_), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_41_), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_start_high_latch_309), + .LO(N_27513) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_d64_i_m3_i_m3_0_63_.INIT = 8'hCA; + LUT3_L com_llm_llm_rx_top_llm_rx_tlp_crc_d64_i_m3_i_m3_0_63_ ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_8_), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_40_), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_start_high_latch_309), + .LO(N_27514) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_d64_i_m2_i_m3_0_25_.INIT = 8'hB8; + LUT3 com_llm_llm_rx_top_llm_rx_tlp_crc_d64_i_m2_i_m3_0_25_ ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_14_), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_start_high_latch_309), + .I2(com_llm_llm_rx_top_rx_data_54_), + .O(N_27523) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_d64_i_m2_i_m3_0_57_.INIT = 8'hCA; + LUT3_L com_llm_llm_rx_top_llm_rx_tlp_crc_d64_i_m2_i_m3_0_57_ ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_14_), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_46_), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_start_high_latch_309), + .LO(N_27527) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_d64_i_m2_i_m3_0_27_.INIT = 8'hB8; + LUT3 com_llm_llm_rx_top_llm_rx_tlp_crc_d64_i_m2_i_m3_0_27_ ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_12_), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_start_high_latch_309), + .I2(com_llm_llm_rx_top_rx_data_52_), + .O(N_27563) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_d64_i_m2_i_m3_0_59_.INIT = 8'hCA; + LUT3 com_llm_llm_rx_top_llm_rx_tlp_crc_d64_i_m2_i_m3_0_59_ ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_12_), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_44_), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_start_high_latch_309), + .O(N_27564) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_d64_i_m3_0_14_.INIT = 8'hB8; + LUT3 com_llm_llm_rx_top_llm_rx_tlp_crc_d64_i_m3_0_14_ ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_data_q_5080[1]), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_start_high_latch_309), + .I2(com_llm_llm_rx_top_rx_data_33_), + .O(N_27417) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_d64_i_m3_0_56_.INIT = 8'hCA; + LUT3_L com_llm_llm_rx_top_llm_rx_tlp_crc_d64_i_m3_0_56_ ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_15_), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_47_), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_start_high_latch_309), + .LO(N_27441) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_d64_i_m3_0_38_.INIT = 8'hB8; + LUT3_L com_llm_llm_rx_top_llm_rx_tlp_crc_d64_i_m3_0_38_ ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_17_), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_start_high_latch_309), + .I2(com_llm_llm_rx_top_rx_data_57_), + .LO(N_27431) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_d64_i_m2_i_m3_0_36_.INIT = 8'hB8; + LUT3 com_llm_llm_rx_top_llm_rx_tlp_crc_d64_i_m2_i_m3_0_36_ ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_19_), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_start_high_latch_309), + .I2(com_llm_llm_rx_top_rx_data_59_), + .O(N_27526) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_d64_i_m2_i_m3_0_32_.INIT = 8'hB8; + LUT3_L com_llm_llm_rx_top_llm_rx_tlp_crc_d64_i_m2_i_m3_0_32_ ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_23_), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_start_high_latch_309), + .I2(com_llm_llm_rx_top_rx_data_63_), + .LO(N_27525) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_d64_i_m3_0_4_.INIT = 8'hE4; + LUT3 com_llm_llm_rx_top_llm_rx_tlp_crc_d64_i_m3_0_4_ ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_start_high_latch_309), + .I1(com_llm_llm_rx_top_rx_data_27_), + .I2(com_llm_llm_rx_top_rx_data_59_), + .O(N_27409) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_d64_i_m3_0_0_.INIT = 8'hE4; + LUT3 com_llm_llm_rx_top_llm_rx_tlp_crc_d64_i_m3_0_0_ ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_start_high_latch_309), + .I1(com_llm_llm_rx_top_rx_data_31_), + .I2(com_llm_llm_rx_top_rx_data_63_), + .O(N_27405) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_d64_i_m3_i_m3_0_29_.INIT = 8'hB8; + LUT3 com_llm_llm_rx_top_llm_rx_tlp_crc_d64_i_m3_i_m3_0_29_ ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_10_), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_start_high_latch_309), + .I2(com_llm_llm_rx_top_rx_data_50_), + .O(N_27500) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_d16_i_m3_i_m3_0_13_.INIT = 8'hCA; + LUT3 com_llm_llm_rx_top_llm_rx_tlp_crc_d16_i_m3_i_m3_0_13_ ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_10_), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_42_), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_start_high_latch_q_308), + .O(N_27497) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_d64_i_m2_i_m3_0_26_.INIT = 8'hB8; + LUT3 com_llm_llm_rx_top_llm_rx_tlp_crc_d64_i_m2_i_m3_0_26_ ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_13_), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_start_high_latch_309), + .I2(com_llm_llm_rx_top_rx_data_53_), + .O(N_27524) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_d64_i_m3_0_58_.INIT = 8'hCA; + LUT3 com_llm_llm_rx_top_llm_rx_tlp_crc_d64_i_m3_0_58_ ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_13_), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_45_), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_start_high_latch_309), + .O(N_27442) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_d64_i_m3_i_m3_0_31_.INIT = 8'hB8; + LUT3 com_llm_llm_rx_top_llm_rx_tlp_crc_d64_i_m3_i_m3_0_31_ ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_8_), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_start_high_latch_309), + .I2(com_llm_llm_rx_top_rx_data_48_), + .O(N_27502) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_d16_i_m3_i_m3_0_15_.INIT = 8'hCA; + LUT3 com_llm_llm_rx_top_llm_rx_tlp_crc_d16_i_m3_i_m3_0_15_ ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_8_), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_40_), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_start_high_latch_q_308), + .O(N_27498) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_N_30983_i.INIT = 4'h7; + LUT2 com_llm_llm_rx_top_llm_rx_tlp_crc_N_30983_i ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rsof_nd_1782), + .I1(com_llm_llm_rx_top_rx_reof_n), + .O(com_llm_llm_rx_top_llm_rx_tlp_crc_N_30983_i_1781) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_dw_3_0_a2_0_o4.INIT = 8'h01; + LUT3 com_llm_llm_rx_top_llm_rx_tlp_crc_dw_3_0_a2_0_o4 ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_tlp_sof_nq_1789), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_tlp_vld_l_nq_1682), + .I2(com_llm_llm_rx_top_rx_tlp_vld_h_n), + .O(com_llm_llm_rx_top_llm_rx_tlp_crc_N_27380_i) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_un6_crc32_res_ok_2_and_0_a2_1.INIT = 8'h01; + LUT3 com_llm_llm_rx_top_llm_rx_tlp_crc_un6_crc32_res_ok_2_and_0_a2_1 ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d16[21]), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d16[22]), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d16[23]), + .O(com_llm_llm_rx_top_llm_rx_tlp_crc_un6_crc32_res_ok_2_and_1) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_un6_crc32_res_ok_1_and_0_a2_1.INIT = 8'h01; + LUT3 com_llm_llm_rx_top_llm_rx_tlp_crc_un6_crc32_res_ok_1_and_0_a2_1 ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d16[16]), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d16[17]), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d16[19]), + .O(com_llm_llm_rx_top_llm_rx_tlp_crc_un6_crc32_res_ok_1_and_1) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_un3_crc32_com_ok_0_I_141.INIT = 16'h396C; + LUT4 com_llm_llm_rx_top_llm_rx_tlp_crc_un3_crc32_com_ok_0_I_141 ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_aligned_aligned_1689), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d16[15]), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl[8]), + .I3(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_40_), + .O(com_llm_llm_rx_top_llm_rx_tlp_crc_N_7) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_un3_crc32_com_ok_0_I_140.INIT = 16'h396C; + LUT4 com_llm_llm_rx_top_llm_rx_tlp_crc_un3_crc32_com_ok_0_I_140 ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_aligned_aligned_1689), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d16[14]), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl[9]), + .I3(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_41_), + .O(com_llm_llm_rx_top_llm_rx_tlp_crc_N_6) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_un3_crc32_com_ok_0_I_105.INIT = 16'h396C; + LUT4 com_llm_llm_rx_top_llm_rx_tlp_crc_un3_crc32_com_ok_0_I_105 ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_aligned_aligned_1689), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d16[23]), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl[16]), + .I3(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_48__1770), + .O(com_llm_llm_rx_top_llm_rx_tlp_crc_N_39) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_un3_crc32_com_ok_0_I_32.INIT = 16'h396C; + LUT4 com_llm_llm_rx_top_llm_rx_tlp_crc_un3_crc32_com_ok_0_I_32 ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_aligned_aligned_1689), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d16[24]), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl[31]), + .I3(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_63__1771), + .O(com_llm_llm_rx_top_llm_rx_tlp_crc_N_102) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_un3_crc32_com_ok_0_I_33.INIT = 16'h396C; + LUT4 com_llm_llm_rx_top_llm_rx_tlp_crc_un3_crc32_com_ok_0_I_33 ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_aligned_aligned_1689), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d16[25]), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl[30]), + .I3(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_62__1772), + .O(com_llm_llm_rx_top_llm_rx_tlp_crc_N_103) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_un3_crc32_com_ok_0_I_41.INIT = 16'h396C; + LUT4 com_llm_llm_rx_top_llm_rx_tlp_crc_un3_crc32_com_ok_0_I_41 ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_aligned_aligned_1689), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d16[16]), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl[23]), + .I3(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_55__1763), + .O(com_llm_llm_rx_top_llm_rx_tlp_crc_N_94) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_un3_crc32_com_ok_0_I_42.INIT = 16'h396C; + LUT4 com_llm_llm_rx_top_llm_rx_tlp_crc_un3_crc32_com_ok_0_I_42 ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_aligned_aligned_1689), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d16[17]), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl[22]), + .I3(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_54__1764), + .O(com_llm_llm_rx_top_llm_rx_tlp_crc_N_95) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_un3_crc32_com_ok_0_I_95.INIT = 16'h396C; + LUT4 com_llm_llm_rx_top_llm_rx_tlp_crc_un3_crc32_com_ok_0_I_95 ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_aligned_aligned_1689), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d16[18]), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl[21]), + .I3(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_53__1765), + .O(com_llm_llm_rx_top_llm_rx_tlp_crc_N_46) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_un3_crc32_com_ok_0_I_96.INIT = 16'h396C; + LUT4 com_llm_llm_rx_top_llm_rx_tlp_crc_un3_crc32_com_ok_0_I_96 ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_aligned_aligned_1689), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d16[19]), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl[20]), + .I3(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_52__1766), + .O(com_llm_llm_rx_top_llm_rx_tlp_crc_N_47) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_un3_crc32_com_ok_0_I_59.INIT = 16'h396C; + LUT4 com_llm_llm_rx_top_llm_rx_tlp_crc_un3_crc32_com_ok_0_I_59 ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_aligned_aligned_1689), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d16[10]), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl[13]), + .I3(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_45_), + .O(com_llm_llm_rx_top_llm_rx_tlp_crc_N_78) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_un3_crc32_com_ok_0_I_60.INIT = 16'h396C; + LUT4 com_llm_llm_rx_top_llm_rx_tlp_crc_un3_crc32_com_ok_0_I_60 ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_aligned_aligned_1689), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d16[11]), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl[12]), + .I3(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_44_), + .O(com_llm_llm_rx_top_llm_rx_tlp_crc_N_79) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_un3_crc32_com_ok_0_I_86.INIT = 16'h396C; + LUT4 com_llm_llm_rx_top_llm_rx_tlp_crc_un3_crc32_com_ok_0_I_86 ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_aligned_aligned_1689), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d16[20]), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl[19]), + .I3(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_51__1767), + .O(com_llm_llm_rx_top_llm_rx_tlp_crc_N_54) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_un3_crc32_com_ok_0_I_87.INIT = 16'h396C; + LUT4 com_llm_llm_rx_top_llm_rx_tlp_crc_un3_crc32_com_ok_0_I_87 ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_aligned_aligned_1689), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d16[21]), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl[18]), + .I3(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_50__1768), + .O(com_llm_llm_rx_top_llm_rx_tlp_crc_N_55) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_un3_crc32_com_ok_0_I_104.INIT = 16'h396C; + LUT4 com_llm_llm_rx_top_llm_rx_tlp_crc_un3_crc32_com_ok_0_I_104 ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_aligned_aligned_1689), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d16[22]), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl[17]), + .I3(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_49__1769), + .O(com_llm_llm_rx_top_llm_rx_tlp_crc_N_38) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_un3_crc32_com_ok_0_I_50.INIT = 16'h396C; + LUT4 com_llm_llm_rx_top_llm_rx_tlp_crc_un3_crc32_com_ok_0_I_50 ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_aligned_aligned_1689), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d16[12]), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl[11]), + .I3(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_43_), + .O(com_llm_llm_rx_top_llm_rx_tlp_crc_N_86) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_un3_crc32_com_ok_0_I_51.INIT = 16'h396C; + LUT4 com_llm_llm_rx_top_llm_rx_tlp_crc_un3_crc32_com_ok_0_I_51 ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_aligned_aligned_1689), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d16[13]), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl[10]), + .I3(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_42_), + .O(com_llm_llm_rx_top_llm_rx_tlp_crc_N_87) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_un4_crc32_com_ok_0_I_77.INIT = 16'hC693; + LUT4 com_llm_llm_rx_top_llm_rx_tlp_crc_un4_crc32_com_ok_0_I_77 ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_aligned_aligned_1689), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d16[8]), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl[15]), + .I3(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_47_), + .O(com_llm_llm_rx_top_llm_rx_tlp_crc_N_62) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_un4_crc32_com_ok_0_I_78.INIT = 16'hC693; + LUT4 com_llm_llm_rx_top_llm_rx_tlp_crc_un4_crc32_com_ok_0_I_78 ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_aligned_aligned_1689), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d16[9]), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl[14]), + .I3(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_46_), + .O(com_llm_llm_rx_top_llm_rx_tlp_crc_N_63) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_un3_crc32_com_ok_0_I_68.INIT = 16'h396C; + LUT4 com_llm_llm_rx_top_llm_rx_tlp_crc_un3_crc32_com_ok_0_I_68 ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_aligned_aligned_1689), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d16[30]), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl[25]), + .I3(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_57__1777), + .O(com_llm_llm_rx_top_llm_rx_tlp_crc_N_70) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_un3_crc32_com_ok_0_I_69.INIT = 16'h396C; + LUT4 com_llm_llm_rx_top_llm_rx_tlp_crc_un3_crc32_com_ok_0_I_69 ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_aligned_aligned_1689), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d16[31]), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl[24]), + .I3(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_56__1762), + .O(com_llm_llm_rx_top_llm_rx_tlp_crc_N_71) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_un3_crc32_com_ok_0_I_122.INIT = 16'h396C; + LUT4 com_llm_llm_rx_top_llm_rx_tlp_crc_un3_crc32_com_ok_0_I_122 ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_aligned_aligned_1689), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d16[28]), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl[27]), + .I3(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_59__1775), + .O(com_llm_llm_rx_top_llm_rx_tlp_crc_N_22) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_un3_crc32_com_ok_0_I_123.INIT = 16'h396C; + LUT4 com_llm_llm_rx_top_llm_rx_tlp_crc_un3_crc32_com_ok_0_I_123 ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_aligned_aligned_1689), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d16[29]), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl[26]), + .I3(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_58__1776), + .O(com_llm_llm_rx_top_llm_rx_tlp_crc_N_23) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_un3_crc32_com_ok_0_I_131.INIT = 16'h396C; + LUT4 com_llm_llm_rx_top_llm_rx_tlp_crc_un3_crc32_com_ok_0_I_131 ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_aligned_aligned_1689), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d16[26]), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl[29]), + .I3(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_61__1773), + .O(com_llm_llm_rx_top_llm_rx_tlp_crc_N_14) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_un3_crc32_com_ok_0_I_132.INIT = 16'h396C; + LUT4 com_llm_llm_rx_top_llm_rx_tlp_crc_un3_crc32_com_ok_0_I_132 ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_aligned_aligned_1689), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d16[27]), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl[28]), + .I3(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_60__1774), + .O(com_llm_llm_rx_top_llm_rx_tlp_crc_N_15) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_un3_crc32_com_ok_0_I_5.INIT = 16'h396C; + LUT4 com_llm_llm_rx_top_llm_rx_tlp_crc_un3_crc32_com_ok_0_I_5 ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_aligned_aligned_1689), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d16[6]), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl[1]), + .I3(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_33_), + .O(com_llm_llm_rx_top_llm_rx_tlp_crc_N_126) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_un3_crc32_com_ok_0_I_6.INIT = 16'h396C; + LUT4 com_llm_llm_rx_top_llm_rx_tlp_crc_un3_crc32_com_ok_0_I_6 ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_aligned_aligned_1689), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d16[7]), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl[0]), + .I3(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_32_), + .O(com_llm_llm_rx_top_llm_rx_tlp_crc_N_127) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_un3_crc32_com_ok_0_I_23.INIT = 16'h396C; + LUT4 com_llm_llm_rx_top_llm_rx_tlp_crc_un3_crc32_com_ok_0_I_23 ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_aligned_aligned_1689), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d16[2]), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl[5]), + .I3(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_37_), + .O(com_llm_llm_rx_top_llm_rx_tlp_crc_N_110) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_un3_crc32_com_ok_0_I_24.INIT = 16'h396C; + LUT4 com_llm_llm_rx_top_llm_rx_tlp_crc_un3_crc32_com_ok_0_I_24 ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_aligned_aligned_1689), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d16[3]), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl[4]), + .I3(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_36_), + .O(com_llm_llm_rx_top_llm_rx_tlp_crc_N_111) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_un3_crc32_com_ok_0_I_113.INIT = 16'h396C; + LUT4 com_llm_llm_rx_top_llm_rx_tlp_crc_un3_crc32_com_ok_0_I_113 ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_aligned_aligned_1689), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d16[0]), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl[7]), + .I3(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_39_), + .O(com_llm_llm_rx_top_llm_rx_tlp_crc_N_30) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_un3_crc32_com_ok_0_I_114.INIT = 16'h396C; + LUT4 com_llm_llm_rx_top_llm_rx_tlp_crc_un3_crc32_com_ok_0_I_114 ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_aligned_aligned_1689), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d16[1]), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl[6]), + .I3(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_38_), + .O(com_llm_llm_rx_top_llm_rx_tlp_crc_N_31) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_un3_crc32_com_ok_0_I_14.INIT = 16'h396C; + LUT4 com_llm_llm_rx_top_llm_rx_tlp_crc_un3_crc32_com_ok_0_I_14 ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_aligned_aligned_1689), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d16[4]), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl[3]), + .I3(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_35_), + .O(com_llm_llm_rx_top_llm_rx_tlp_crc_N_118) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_un3_crc32_com_ok_0_I_15.INIT = 16'h396C; + LUT4 com_llm_llm_rx_top_llm_rx_tlp_crc_un3_crc32_com_ok_0_I_15 ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_aligned_aligned_1689), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d16[5]), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl[2]), + .I3(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_34_), + .O(com_llm_llm_rx_top_llm_rx_tlp_crc_N_119) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_un1_RX_RSRC_DSC_N17_0_0_0.INIT = 8'h51; + LUT3 com_llm_llm_rx_top_llm_rx_tlp_crc_un1_RX_RSRC_DSC_N17_0_0_0 ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_N_27375), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rsrc_dsc_nd_1680), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_tlp_nullified_q_1681), + .O(com_llm_llm_rx_top_llm_rx_tlp_crc_un1_RX_RSRC_DSC_N17_0_0_0_1674) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_rx_tlp_sof_nqq6_0_0_o3.INIT = 8'hA2; + LUT3 com_llm_llm_rx_top_llm_rx_tlp_crc_rx_tlp_sof_nqq6_0_0_o3 ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_N_27380_i), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_tlp_eof_nq_1787), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_tlp_vld_h_nq_1683), + .O(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_tlp_sof_nqq6_0_0_o3_1673) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_RX_TLP_CRC_ERR_N_6_i_0_o3.INIT = 8'h02; + LUT3 com_llm_llm_rx_top_llm_rx_tlp_crc_RX_TLP_CRC_ERR_N_6_i_0_o3 ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_N_27369_i), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_dw_3q_1690), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_tlp_eof_nq_1787), + .O(com_llm_llm_rx_top_llm_rx_tlp_crc_RX_TLP_CRC_ERR_N_6_i_0_o3_1676) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_RX_TLP_FERR_N_6_u_i_0_m2_0.INIT = 16'hF2D0; + LUT4 com_llm_llm_rx_top_llm_rx_tlp_crc_RX_TLP_FERR_N_6_u_i_0_m2_0 ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_N_27369_i), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_dw_3q_1690), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_reof_nd_1694), + .I3(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_tlp_eof_nq_1787), + .O(com_llm_llm_rx_top_llm_rx_tlp_crc_RX_REOF_N_5) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_RX_TLP_CRC_ERR_N_6_i_0_m2_0_1.INIT = 16'h193B; + LUT4 com_llm_llm_rx_top_llm_rx_tlp_crc_RX_TLP_CRC_ERR_N_6_i_0_m2_0_1 ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_RX_TLP_CRC_ERR_N_6_i_0_o3_0_1677), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_tlp_nullified_latch_1778), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_un3_crc32_res_ok_7_1670), + .I3(com_llm_llm_rx_top_llm_rx_tlp_crc_un6_crc32_res_ok_7_1669), + .O(com_llm_llm_rx_top_llm_rx_tlp_crc_RX_TLP_CRC_ERR_N_6_i_0_m2_0_1_1671) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_RX_TLP_CRC_ERR_N_6_i_0_m2_0.INIT = 16'h7632; + LUT4 com_llm_llm_rx_top_llm_rx_tlp_crc_RX_TLP_CRC_ERR_N_6_i_0_m2_0 ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_RX_TLP_CRC_ERR_N_6_i_0_o3_0_1677), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_RX_TLP_CRC_ERR_N_6_i_0_m2_0_1_1671), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_I_28), + .I3(com_llm_llm_rx_top_llm_rx_tlp_crc_I_28_0), + .O(com_llm_llm_rx_top_llm_rx_tlp_crc_N_27384) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_RX_TLP_CRC_ERR_N_6_i_0_0.INIT = 16'h5545; + LUT4 com_llm_llm_rx_top_llm_rx_tlp_crc_RX_TLP_CRC_ERR_N_6_i_0_0 ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_N_27375), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_RX_TLP_CRC_ERR_N_6_i_0_o3_1676), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_RX_TLP_CRC_ERR_N_6_i_0_a2_0_0_1672), + .I3(com_llm_llm_rx_top_llm_rx_tlp_crc_aligned_aligned_1689), + .O(com_llm_llm_rx_top_llm_rx_tlp_crc_RX_TLP_CRC_ERR_N_6_i_0_0_1675) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_N_68809_i.INIT = 16'hFFF1; + LUT4 com_llm_llm_rx_top_llm_rx_tlp_crc_N_68809_i ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_N_27378_i), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_tlp_sof_nqq6_0_0_o3_1673), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_end_low_latch_3), + .I3(com_llm_llm_rx_top_rx_tlp_eof_n), + .O(com_llm_llm_rx_top_llm_rx_tlp_crc_N_68809_i_1786) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_N_68796_i.INIT = 16'h0F0D; + LUT4 com_llm_llm_rx_top_llm_rx_tlp_crc_N_68796_i ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_tlp_sof_nqq6_0_0_o3_1673), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_end_low_latch_3), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_tlp_64_q_1686), + .I3(com_llm_llm_rx_top_rx_tlp_eof_n), + .O(com_llm_llm_rx_top_llm_rx_tlp_crc_N_68796_i_1784) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_rx_tlp_nullified_q_i.INIT = 4'h1; + LUT1_L com_llm_llm_rx_top_llm_rx_tlp_crc_rx_tlp_nullified_q_i ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_tlp_nullified_q_1681), + .LO(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_tlp_nullified_q_i_1679) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_tlp_64_0_a2_0_a2.INIT = 4'h2; + LUT2_L com_llm_llm_rx_top_llm_rx_tlp_crc_tlp_64_0_a2_0_a2 ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_N_27378_i), + .I1(com_llm_llm_rx_top_rx_tlp_eof_n), + .LO(com_llm_llm_rx_top_llm_rx_tlp_crc_tlp_64) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_unaligned_aligned_3_0_a2_0_a2.INIT = 4'h2; + LUT2_L com_llm_llm_rx_top_llm_rx_tlp_crc_unaligned_aligned_3_0_a2_0_a2 ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_end_low_latch_1780), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_start_high_latch_q_308), + .LO(com_llm_llm_rx_top_llm_rx_tlp_crc_unaligned_aligned_3) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_aligned_unaligned_3_0_a2_0_a2.INIT = 4'h4; + LUT2_L com_llm_llm_rx_top_llm_rx_tlp_crc_aligned_unaligned_3_0_a2_0_a2 ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_end_low_latch_1780), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_start_high_latch_q_308), + .LO(com_llm_llm_rx_top_llm_rx_tlp_crc_aligned_unaligned_3) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_aligned_aligned_3_0_a2_0_a2.INIT = 4'h8; + LUT2_L com_llm_llm_rx_top_llm_rx_tlp_crc_aligned_aligned_3_0_a2_0_a2 ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_end_low_latch_1780), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_start_high_latch_q_308), + .LO(com_llm_llm_rx_top_llm_rx_tlp_crc_aligned_aligned_3) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_dw_3_0_a2_0_a2.INIT = 8'h02; + LUT3_L com_llm_llm_rx_top_llm_rx_tlp_crc_dw_3_0_a2_0_a2 ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_N_27380_i), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_tlp_vld_h_nq_1683), + .I2(com_llm_llm_rx_top_rx_tlp_eof_n), + .LO(com_llm_llm_rx_top_llm_rx_tlp_crc_dw_3) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_RX_RREM13_i_0.INIT = 8'h41; + LUT3_L com_llm_llm_rx_top_llm_rx_tlp_crc_RX_RREM13_i_0 ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_dw_3q_1690), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_end_low_latch_1780), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_start_high_latch_qq_1684), + .LO(com_llm_llm_rx_top_llm_rx_tlp_crc_N_13155_i) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_N_68081_i.INIT = 16'h73FF; + LUT4_L com_llm_llm_rx_top_llm_rx_tlp_crc_N_68081_i ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_N_27369_i), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_N_27384), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rsrc_dsc_nd_1680), + .I3(com_llm_llm_rx_top_llm_rx_tlp_crc_un1_RX_RSRC_DSC_N17_0_0_0_1674), + .LO(com_llm_llm_rx_top_llm_rx_tlp_crc_N_68081_i_1691) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_N_68082_i.INIT = 16'hBFAF; + LUT4_L com_llm_llm_rx_top_llm_rx_tlp_crc_N_68082_i ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_N_27384), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_RX_TLP_CRC_ERR_N_6_i_0_o3_1676), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_RX_TLP_CRC_ERR_N_6_i_0_0_1675), + .I3(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_reof_nd_1694), + .LO(com_llm_llm_rx_top_llm_rx_tlp_crc_N_68082_i_1692) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_N_68797_i.INIT = 4'hD; + LUT2_L com_llm_llm_rx_top_llm_rx_tlp_crc_N_68797_i ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_N_27375), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_RX_REOF_N_5), + .LO(com_llm_llm_rx_top_llm_rx_tlp_crc_N_68797_i_1693) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m2_i_m3_0_10_.INIT = 8'hCA; + LUT3_L com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m2_i_m3_0_10_ ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl[10]), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl[42]), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_start_high_latch_qq_1684), + .LO(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m2_i_m3_0_10__1695) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m2_i_m3_0_9_.INIT = 8'hCA; + LUT3_L com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m2_i_m3_0_9_ ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl[9]), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl[41]), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_start_high_latch_qq_1684), + .LO(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m2_i_m3_0_9__1696) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m2_i_m3_0_8_.INIT = 8'hCA; + LUT3_L com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m2_i_m3_0_8_ ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl[8]), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl[40]), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_start_high_latch_qq_1684), + .LO(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m2_i_m3_0_8__1697) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m2_i_m3_0_7_.INIT = 8'hCA; + LUT3_L com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m2_i_m3_0_7_ ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl[7]), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl[39]), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_start_high_latch_qq_1684), + .LO(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m2_i_m3_0_7__1698) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m2_i_m3_0_6_.INIT = 8'hCA; + LUT3_L com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m2_i_m3_0_6_ ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl[6]), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl[38]), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_start_high_latch_qq_1684), + .LO(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m2_i_m3_0_6__1699) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m2_i_m3_0_5_.INIT = 8'hCA; + LUT3_L com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m2_i_m3_0_5_ ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl[5]), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl[37]), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_start_high_latch_qq_1684), + .LO(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m2_i_m3_0_5__1700) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m2_i_m3_0_4_.INIT = 8'hCA; + LUT3_L com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m2_i_m3_0_4_ ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl[4]), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl[36]), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_start_high_latch_qq_1684), + .LO(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m2_i_m3_0_4__1701) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m2_i_m3_0_3_.INIT = 8'hCA; + LUT3_L com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m2_i_m3_0_3_ ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl[3]), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl[35]), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_start_high_latch_qq_1684), + .LO(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m2_i_m3_0_3__1702) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m2_i_m3_0_2_.INIT = 8'hCA; + LUT3_L com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m2_i_m3_0_2_ ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl[2]), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl[34]), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_start_high_latch_qq_1684), + .LO(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m2_i_m3_0_2__1703) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m2_i_m3_0_1_.INIT = 8'hCA; + LUT3_L com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m2_i_m3_0_1_ ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl[1]), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl[33]), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_start_high_latch_qq_1684), + .LO(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m2_i_m3_0_1__1704) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m2_i_m3_0_0_.INIT = 8'hCA; + LUT3_L com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m2_i_m3_0_0_ ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl[0]), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl[32]), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_start_high_latch_qq_1684), + .LO(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m2_i_m3_0_0__1705) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m2_i_m3_0_25_.INIT = 8'hCA; + LUT3_L com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m2_i_m3_0_25_ ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl[25]), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl[57]), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_start_high_latch_qq_1684), + .LO(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m2_i_m3_0_25__1706) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m2_i_m3_0_24_.INIT = 8'hCA; + LUT3_L com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m2_i_m3_0_24_ ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl[24]), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl[56]), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_start_high_latch_qq_1684), + .LO(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m2_i_m3_0_24__1707) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m2_i_m3_0_23_.INIT = 8'hCA; + LUT3_L com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m2_i_m3_0_23_ ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl[23]), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl[55]), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_start_high_latch_qq_1684), + .LO(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m2_i_m3_0_23__1708) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m2_i_m3_0_22_.INIT = 8'hCA; + LUT3_L com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m2_i_m3_0_22_ ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl[22]), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl[54]), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_start_high_latch_qq_1684), + .LO(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m2_i_m3_0_22__1709) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m2_i_m3_0_21_.INIT = 8'hCA; + LUT3_L com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m2_i_m3_0_21_ ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl[21]), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl[53]), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_start_high_latch_qq_1684), + .LO(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m2_i_m3_0_21__1710) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m2_i_m3_0_20_.INIT = 8'hCA; + LUT3_L com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m2_i_m3_0_20_ ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl[20]), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl[52]), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_start_high_latch_qq_1684), + .LO(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m2_i_m3_0_20__1711) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m2_i_m3_0_19_.INIT = 8'hCA; + LUT3_L com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m2_i_m3_0_19_ ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl[19]), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl[51]), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_start_high_latch_qq_1684), + .LO(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m2_i_m3_0_19__1712) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m2_i_m3_0_18_.INIT = 8'hCA; + LUT3_L com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m2_i_m3_0_18_ ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl[18]), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl[50]), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_start_high_latch_qq_1684), + .LO(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m2_i_m3_0_18__1713) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m2_i_m3_0_17_.INIT = 8'hCA; + LUT3_L com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m2_i_m3_0_17_ ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl[17]), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl[49]), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_start_high_latch_qq_1684), + .LO(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m2_i_m3_0_17__1714) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m2_i_m3_0_16_.INIT = 8'hCA; + LUT3_L com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m2_i_m3_0_16_ ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl[16]), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl[48]), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_start_high_latch_qq_1684), + .LO(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m2_i_m3_0_16__1715) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m2_i_m3_0_15_.INIT = 8'hCA; + LUT3_L com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m2_i_m3_0_15_ ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl[15]), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl[47]), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_start_high_latch_qq_1684), + .LO(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m2_i_m3_0_15__1716) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m2_i_m3_0_14_.INIT = 8'hCA; + LUT3_L com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m2_i_m3_0_14_ ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl[14]), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl[46]), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_start_high_latch_qq_1684), + .LO(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m2_i_m3_0_14__1717) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m2_i_m3_0_13_.INIT = 8'hCA; + LUT3_L com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m2_i_m3_0_13_ ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl[13]), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl[45]), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_start_high_latch_qq_1684), + .LO(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m2_i_m3_0_13__1718) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m2_i_m3_0_12_.INIT = 8'hCA; + LUT3_L com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m2_i_m3_0_12_ ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl[12]), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl[44]), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_start_high_latch_qq_1684), + .LO(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m2_i_m3_0_12__1719) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m2_i_m3_0_11_.INIT = 8'hCA; + LUT3_L com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m2_i_m3_0_11_ ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl[11]), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl[43]), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_start_high_latch_qq_1684), + .LO(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m2_i_m3_0_11__1720) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m2_i_m3_0_40_.INIT = 8'hAC; + LUT3_L com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m2_i_m3_0_40_ ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sh[40]), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl[40]), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_start_high_latch_qq_1684), + .LO(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m2_i_m3_0_40__1721) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m2_i_m3_0_39_.INIT = 8'hAC; + LUT3_L com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m2_i_m3_0_39_ ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sh[39]), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl[39]), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_start_high_latch_qq_1684), + .LO(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m2_i_m3_0_39__1722) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m2_i_m3_0_38_.INIT = 8'hAC; + LUT3_L com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m2_i_m3_0_38_ ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sh[38]), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl[38]), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_start_high_latch_qq_1684), + .LO(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m2_i_m3_0_38__1723) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m2_i_m3_0_37_.INIT = 8'hAC; + LUT3_L com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m2_i_m3_0_37_ ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sh[37]), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl[37]), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_start_high_latch_qq_1684), + .LO(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m2_i_m3_0_37__1724) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m2_i_m3_0_36_.INIT = 8'hAC; + LUT3_L com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m2_i_m3_0_36_ ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sh[36]), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl[36]), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_start_high_latch_qq_1684), + .LO(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m2_i_m3_0_36__1725) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m2_i_m3_0_35_.INIT = 8'hAC; + LUT3_L com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m2_i_m3_0_35_ ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sh[35]), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl[35]), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_start_high_latch_qq_1684), + .LO(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m2_i_m3_0_35__1726) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m2_i_m3_0_34_.INIT = 8'hAC; + LUT3_L com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m2_i_m3_0_34_ ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sh[34]), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl[34]), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_start_high_latch_qq_1684), + .LO(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m2_i_m3_0_34__1727) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m2_i_m3_0_33_.INIT = 8'hAC; + LUT3_L com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m2_i_m3_0_33_ ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sh[33]), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl[33]), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_start_high_latch_qq_1684), + .LO(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m2_i_m3_0_33__1728) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m2_i_m3_0_32_.INIT = 8'hAC; + LUT3_L com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m2_i_m3_0_32_ ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sh[32]), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl[32]), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_start_high_latch_qq_1684), + .LO(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m2_i_m3_0_32__1729) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m2_i_m3_0_31_.INIT = 8'hCA; + LUT3_L com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m2_i_m3_0_31_ ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl[31]), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl[63]), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_start_high_latch_qq_1684), + .LO(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m2_i_m3_0_31__1730) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m2_i_m3_0_30_.INIT = 8'hCA; + LUT3_L com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m2_i_m3_0_30_ ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl[30]), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl[62]), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_start_high_latch_qq_1684), + .LO(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m2_i_m3_0_30__1731) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m2_i_m3_0_29_.INIT = 8'hCA; + LUT3_L com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m2_i_m3_0_29_ ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl[29]), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl[61]), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_start_high_latch_qq_1684), + .LO(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m2_i_m3_0_29__1732) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m2_i_m3_0_28_.INIT = 8'hCA; + LUT3_L com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m2_i_m3_0_28_ ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl[28]), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl[60]), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_start_high_latch_qq_1684), + .LO(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m2_i_m3_0_28__1733) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m2_i_m3_0_27_.INIT = 8'hCA; + LUT3_L com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m2_i_m3_0_27_ ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl[27]), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl[59]), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_start_high_latch_qq_1684), + .LO(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m2_i_m3_0_27__1734) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m2_i_m3_0_26_.INIT = 8'hCA; + LUT3_L com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m2_i_m3_0_26_ ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl[26]), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl[58]), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_start_high_latch_qq_1684), + .LO(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m2_i_m3_0_26__1735) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m2_i_m3_0_55_.INIT = 8'hAC; + LUT3_L com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m2_i_m3_0_55_ ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sh[55]), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl[55]), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_start_high_latch_qq_1684), + .LO(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m2_i_m3_0_55__1736) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m2_i_m3_0_54_.INIT = 8'hAC; + LUT3_L com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m2_i_m3_0_54_ ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sh[54]), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl[54]), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_start_high_latch_qq_1684), + .LO(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m2_i_m3_0_54__1737) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m2_i_m3_0_53_.INIT = 8'hAC; + LUT3_L com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m2_i_m3_0_53_ ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sh[53]), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl[53]), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_start_high_latch_qq_1684), + .LO(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m2_i_m3_0_53__1738) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m2_i_m3_0_52_.INIT = 8'hAC; + LUT3_L com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m2_i_m3_0_52_ ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sh[52]), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl[52]), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_start_high_latch_qq_1684), + .LO(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m2_i_m3_0_52__1739) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m2_i_m3_0_51_.INIT = 8'hAC; + LUT3_L com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m2_i_m3_0_51_ ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sh[51]), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl[51]), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_start_high_latch_qq_1684), + .LO(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m2_i_m3_0_51__1740) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m2_i_m3_0_50_.INIT = 8'hAC; + LUT3_L com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m2_i_m3_0_50_ ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sh[50]), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl[50]), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_start_high_latch_qq_1684), + .LO(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m2_i_m3_0_50__1741) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m2_i_m3_0_49_.INIT = 8'hAC; + LUT3_L com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m2_i_m3_0_49_ ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sh[49]), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl[49]), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_start_high_latch_qq_1684), + .LO(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m2_i_m3_0_49__1742) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m2_i_m3_0_48_.INIT = 8'hAC; + LUT3_L com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m2_i_m3_0_48_ ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sh[48]), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl[48]), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_start_high_latch_qq_1684), + .LO(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m2_i_m3_0_48__1743) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m3_0_47_.INIT = 8'hAC; + LUT3_L com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m3_0_47_ ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sh[47]), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl[47]), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_start_high_latch_qq_1684), + .LO(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m3_0_47__1744) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m2_i_m3_0_46_.INIT = 8'hAC; + LUT3_L com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m2_i_m3_0_46_ ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sh[46]), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl[46]), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_start_high_latch_qq_1684), + .LO(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m2_i_m3_0_46__1745) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m3_0_45_.INIT = 8'hAC; + LUT3_L com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m3_0_45_ ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sh[45]), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl[45]), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_start_high_latch_qq_1684), + .LO(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m3_0_45__1746) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m2_i_m3_0_44_.INIT = 8'hAC; + LUT3_L com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m2_i_m3_0_44_ ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sh[44]), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl[44]), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_start_high_latch_qq_1684), + .LO(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m2_i_m3_0_44__1747) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m2_i_m3_0_43_.INIT = 8'hAC; + LUT3_L com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m2_i_m3_0_43_ ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sh[43]), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl[43]), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_start_high_latch_qq_1684), + .LO(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m2_i_m3_0_43__1748) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m2_i_m3_0_42_.INIT = 8'hAC; + LUT3_L com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m2_i_m3_0_42_ ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sh[42]), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl[42]), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_start_high_latch_qq_1684), + .LO(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m2_i_m3_0_42__1749) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m2_i_m3_0_41_.INIT = 8'hAC; + LUT3_L com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m2_i_m3_0_41_ ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sh[41]), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl[41]), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_start_high_latch_qq_1684), + .LO(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m2_i_m3_0_41__1750) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m2_i_m3_0_63_.INIT = 8'hAC; + LUT3_L com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m2_i_m3_0_63_ ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sh[63]), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl[63]), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_start_high_latch_qq_1684), + .LO(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m2_i_m3_0_63__1751) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m2_i_m3_0_62_.INIT = 8'hAC; + LUT3_L com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m2_i_m3_0_62_ ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sh[62]), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl[62]), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_start_high_latch_qq_1684), + .LO(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m2_i_m3_0_62__1752) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m2_i_m3_0_61_.INIT = 8'hAC; + LUT3_L com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m2_i_m3_0_61_ ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sh[61]), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl[61]), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_start_high_latch_qq_1684), + .LO(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m2_i_m3_0_61__1753) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m2_i_m3_0_60_.INIT = 8'hAC; + LUT3_L com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m2_i_m3_0_60_ ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sh[60]), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl[60]), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_start_high_latch_qq_1684), + .LO(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m2_i_m3_0_60__1754) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m2_i_m3_0_59_.INIT = 8'hAC; + LUT3_L com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m2_i_m3_0_59_ ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sh[59]), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl[59]), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_start_high_latch_qq_1684), + .LO(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m2_i_m3_0_59__1755) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m2_i_m3_0_58_.INIT = 8'hAC; + LUT3_L com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m2_i_m3_0_58_ ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sh[58]), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl[58]), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_start_high_latch_qq_1684), + .LO(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m2_i_m3_0_58__1756) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m2_i_m3_0_57_.INIT = 8'hAC; + LUT3_L com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m2_i_m3_0_57_ ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sh[57]), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl[57]), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_start_high_latch_qq_1684), + .LO(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m2_i_m3_0_57__1757) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m2_i_m3_0_56_.INIT = 8'hAC; + LUT3_L com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m2_i_m3_0_56_ ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sh[56]), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl[56]), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_start_high_latch_qq_1684), + .LO(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m2_i_m3_0_56__1758) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_start_high_latch_3_0_a2_0_a2.INIT = 4'h2; + LUT2_L com_llm_llm_rx_top_llm_rx_tlp_crc_start_high_latch_3_0_a2_0_a2 ( + .I0(com_llm_llm_rx_top_rx_tlp_eof_n), + .I1(com_llm_llm_rx_top_rx_tlp_vld_h_n), + .LO(com_llm_llm_rx_top_llm_rx_tlp_crc_start_high_latch_3) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_rx_tlp_tsn_dd_5_i_m3_i_m3_0_11_.INIT = 16'hAACA; + LUT4_L com_llm_llm_rx_top_llm_rx_tlp_crc_rx_tlp_tsn_dd_5_i_m3_i_m3_0_11_ ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_11_), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_43_), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_tlp_eof_nq_1787), + .I3(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_tlp_vld_h_nq_1683), + .LO(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_tlp_tsn_dd_5_i_m3_i_m3_0[11]) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_rx_tlp_tsn_dd_5_i_m3_i_m3_0_10_.INIT = 16'hAACA; + LUT4_L com_llm_llm_rx_top_llm_rx_tlp_crc_rx_tlp_tsn_dd_5_i_m3_i_m3_0_10_ ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_10_), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_42_), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_tlp_eof_nq_1787), + .I3(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_tlp_vld_h_nq_1683), + .LO(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_tlp_tsn_dd_5_i_m3_i_m3_0[10]) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_rx_tlp_tsn_dd_5_i_m3_i_m3_0_9_.INIT = 16'hAACA; + LUT4_L com_llm_llm_rx_top_llm_rx_tlp_crc_rx_tlp_tsn_dd_5_i_m3_i_m3_0_9_ ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_9_), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_41_), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_tlp_eof_nq_1787), + .I3(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_tlp_vld_h_nq_1683), + .LO(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_tlp_tsn_dd_5_i_m3_i_m3_0[9]) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_rx_tlp_tsn_dd_5_i_m3_i_m3_0_8_.INIT = 16'hAACA; + LUT4_L com_llm_llm_rx_top_llm_rx_tlp_crc_rx_tlp_tsn_dd_5_i_m3_i_m3_0_8_ ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_8_), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_40_), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_tlp_eof_nq_1787), + .I3(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_tlp_vld_h_nq_1683), + .LO(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_tlp_tsn_dd_5_i_m3_i_m3_0[8]) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_rx_tlp_tsn_dd_5_i_m3_i_m3_0_7_.INIT = 16'hAACA; + LUT4_L com_llm_llm_rx_top_llm_rx_tlp_crc_rx_tlp_tsn_dd_5_i_m3_i_m3_0_7_ ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_7_), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_39_), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_tlp_eof_nq_1787), + .I3(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_tlp_vld_h_nq_1683), + .LO(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_tlp_tsn_dd_5_i_m3_i_m3_0[7]) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_rx_tlp_tsn_dd_5_i_m3_i_m3_0_6_.INIT = 16'hAACA; + LUT4_L com_llm_llm_rx_top_llm_rx_tlp_crc_rx_tlp_tsn_dd_5_i_m3_i_m3_0_6_ ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_6_), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_38_), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_tlp_eof_nq_1787), + .I3(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_tlp_vld_h_nq_1683), + .LO(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_tlp_tsn_dd_5_i_m3_i_m3_0[6]) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_rx_tlp_tsn_dd_5_i_m3_i_m3_0_5_.INIT = 16'hAACA; + LUT4_L com_llm_llm_rx_top_llm_rx_tlp_crc_rx_tlp_tsn_dd_5_i_m3_i_m3_0_5_ ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_5_), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_37_), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_tlp_eof_nq_1787), + .I3(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_tlp_vld_h_nq_1683), + .LO(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_tlp_tsn_dd_5_i_m3_i_m3_0[5]) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_rx_tlp_tsn_dd_5_i_m3_i_m3_0_4_.INIT = 16'hAACA; + LUT4_L com_llm_llm_rx_top_llm_rx_tlp_crc_rx_tlp_tsn_dd_5_i_m3_i_m3_0_4_ ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_4_), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_36_), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_tlp_eof_nq_1787), + .I3(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_tlp_vld_h_nq_1683), + .LO(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_tlp_tsn_dd_5_i_m3_i_m3_0[4]) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_rx_tlp_tsn_dd_5_i_m3_i_m3_0_3_.INIT = 16'hAACA; + LUT4_L com_llm_llm_rx_top_llm_rx_tlp_crc_rx_tlp_tsn_dd_5_i_m3_i_m3_0_3_ ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_3_), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_35_), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_tlp_eof_nq_1787), + .I3(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_tlp_vld_h_nq_1683), + .LO(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_tlp_tsn_dd_5_i_m3_i_m3_0[3]) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_rx_tlp_tsn_dd_5_i_m3_i_m3_0_2_.INIT = 16'hAACA; + LUT4_L com_llm_llm_rx_top_llm_rx_tlp_crc_rx_tlp_tsn_dd_5_i_m3_i_m3_0_2_ ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_2_), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_34_), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_tlp_eof_nq_1787), + .I3(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_tlp_vld_h_nq_1683), + .LO(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_tlp_tsn_dd_5_i_m3_i_m3_0[2]) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_rx_tlp_tsn_dd_5_i_m3_i_m3_0_1_.INIT = 16'hAACA; + LUT4_L com_llm_llm_rx_top_llm_rx_tlp_crc_rx_tlp_tsn_dd_5_i_m3_i_m3_0_1_ ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_1_), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_33_), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_tlp_eof_nq_1787), + .I3(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_tlp_vld_h_nq_1683), + .LO(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_tlp_tsn_dd_5_i_m3_i_m3_0[1]) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_rx_tlp_tsn_dd_5_i_m3_i_m3_0_0_.INIT = 16'hAACA; + LUT4_L com_llm_llm_rx_top_llm_rx_tlp_crc_rx_tlp_tsn_dd_5_i_m3_i_m3_0_0_ ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_0_), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_32_), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_tlp_eof_nq_1787), + .I3(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_tlp_vld_h_nq_1683), + .LO(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_tlp_tsn_dd_5_i_m3_i_m3_0[0]) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_RX_TLP_CRC_ERR_N_6_i_0_o3_0.INIT = 8'h54; + LUT3 com_llm_llm_rx_top_llm_rx_tlp_crc_RX_TLP_CRC_ERR_N_6_i_0_o3_0 ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_aligned_aligned_1689), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_start_high_latch_qq_1684), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_end_low_latch_1780), + .O(com_llm_llm_rx_top_llm_rx_tlp_crc_RX_TLP_CRC_ERR_N_6_i_0_o3_0_1677) + ); + MUXCY com_llm_llm_rx_top_llm_rx_tlp_crc_un4_crc32_com_ok_0_I_28 ( + .CI(com_llm_llm_rx_top_llm_rx_tlp_crc_data_tmp_0[14]), + .DI(com_llm_llm_rx_top_llm_rx_tlp_crc_GND_1678), + .O(com_llm_llm_rx_top_llm_rx_tlp_crc_I_28_0), + .S(com_llm_llm_rx_top_llm_rx_tlp_crc_N_99) + ); + MUXCY com_llm_llm_rx_top_llm_rx_tlp_crc_un3_crc32_com_ok_0_I_28 ( + .CI(com_llm_llm_rx_top_llm_rx_tlp_crc_data_tmp[14]), + .DI(com_llm_llm_rx_top_llm_rx_tlp_crc_GND_1678), + .O(com_llm_llm_rx_top_llm_rx_tlp_crc_I_28), + .S(com_llm_llm_rx_top_llm_rx_tlp_crc_N_99_0) + ); + FDP com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rsrc_dsc_nd ( + .PRE(plm_link_up_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_tlp_nullified_q_i_1679), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rsrc_dsc_nd_1680) + ); + FDP com_llm_llm_rx_top_llm_rx_tlp_crc_RX_RSOF_N ( + .PRE(plm_link_up_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rsof_nd_1782), + .Q(com_llm_llm_rx_top_rx_sof_n) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_rx_tlp_nullified_q ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_rx_tlp_nullified), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_tlp_nullified_q_1681), + .CLR(plm_link_up_i) + ); + FDP com_llm_llm_rx_top_llm_rx_tlp_crc_rx_tlp_vld_l_nq ( + .PRE(plm_link_up_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_rx_tlp_vld_l_n), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_tlp_vld_l_nq_1682) + ); + FDP com_llm_llm_rx_top_llm_rx_tlp_crc_rx_tlp_vld_h_nq ( + .PRE(plm_link_up_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_rx_tlp_vld_h_n), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_tlp_vld_h_nq_1683) + ); + FDP com_llm_llm_rx_top_llm_rx_tlp_crc_rx_tlp_sof_nq ( + .PRE(plm_link_up_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_rx_tlp_sof_n), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_tlp_sof_nq_1789) + ); + FDP com_llm_llm_rx_top_llm_rx_tlp_crc_start_high_latch_qq ( + .PRE(plm_link_up_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_start_high_latch_q_308), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_start_high_latch_qq_1684) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_initial_64 ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_rx_tlp_sof_n_i), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_initial_64_51), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_frame_error_latch_q ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_frame_error_latch_1779), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_frame_error_latch_q_1685), + .CLR(plm_link_up_i) + ); + FDP com_llm_llm_rx_top_llm_rx_tlp_crc_start_high_latch_q ( + .PRE(plm_link_up_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_start_high_latch_309), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_start_high_latch_q_308) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_tlp_64_q ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_tlp_64), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_tlp_64_q_1686), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_unaligned_aligned ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_unaligned_aligned_3), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_unaligned_aligned_1687), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_aligned_unaligned ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_aligned_unaligned_3), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_aligned_unaligned_1688), + .CLR(plm_link_up_i) + ); + FDP com_llm_llm_rx_top_llm_rx_tlp_crc_aligned_aligned ( + .PRE(plm_link_up_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_aligned_aligned_3), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_aligned_aligned_1689) + ); + FDP com_llm_llm_rx_top_llm_rx_tlp_crc_RX_REOF_N ( + .PRE(plm_link_up_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_RX_REOF_N_5), + .Q(com_llm_llm_rx_top_rx_reof_n) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_dw_3q ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_dw_3), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_dw_3q_1690), + .CLR(plm_link_up_i) + ); + FDP com_llm_llm_rx_top_llm_rx_tlp_crc_RX_RREM_1_2_ ( + .PRE(plm_link_up_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_N_13155_i), + .Q(com_llm_llm_rx_top_rx_rrem[2]) + ); + FDP com_llm_llm_rx_top_llm_rx_tlp_crc_RX_RSRC_DSC_N ( + .PRE(plm_link_up_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_N_68081_i_1691), + .Q(com_llm_rx_rsrc_dsc_n) + ); + FDP com_llm_llm_rx_top_llm_rx_tlp_crc_RX_TLP_CRC_ERR_N ( + .PRE(plm_link_up_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_N_68082_i_1692), + .Q(com_llm_llm_rx_top_rx_tlp_crc_err_n) + ); + FDP com_llm_llm_rx_top_llm_rx_tlp_crc_RX_TLP_FERR_N ( + .PRE(plm_link_up_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_N_68797_i_1693), + .Q(com_llm_llm_rx_top_rx_tlp_ferr_n) + ); + FDP com_llm_llm_rx_top_llm_rx_tlp_crc_rx_reof_nd ( + .PRE(plm_link_up_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_tlp_eof_nq_1787), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_reof_nd_1694) + ); + FDP com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rsof_nd ( + .PRE(plm_link_up_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_tlp_sof_nqq_1785), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rsof_nd_1782) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_rx_tlp_tsn_d_7_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_tlp_tsn_dd[7]), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_tlp_tsn_d[7]), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_rx_tlp_tsn_d_6_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_tlp_tsn_dd[6]), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_tlp_tsn_d[6]), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_rx_tlp_tsn_d_5_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_tlp_tsn_dd[5]), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_tlp_tsn_d[5]), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_rx_tlp_tsn_d_4_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_tlp_tsn_dd[4]), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_tlp_tsn_d[4]), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_rx_tlp_tsn_d_3_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_tlp_tsn_dd[3]), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_tlp_tsn_d[3]), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_rx_tlp_tsn_d_2_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_tlp_tsn_dd[2]), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_tlp_tsn_d[2]), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_rx_tlp_tsn_d_1_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_tlp_tsn_dd[1]), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_tlp_tsn_d[1]), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_rx_tlp_tsn_d_0_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_tlp_tsn_dd[0]), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_tlp_tsn_d[0]), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_RX_RD_10_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m2_i_m3_0_10__1695), + .Q(com_llm_llm_rx_top_rx_rd[10]), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_RX_RD_9_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m2_i_m3_0_9__1696), + .Q(com_llm_llm_rx_top_rx_rd[9]), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_RX_RD_8_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m2_i_m3_0_8__1697), + .Q(com_llm_llm_rx_top_rx_rd[8]), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_RX_RD_7_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m2_i_m3_0_7__1698), + .Q(com_llm_llm_rx_top_rx_rd[7]), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_RX_RD_6_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m2_i_m3_0_6__1699), + .Q(com_llm_llm_rx_top_rx_rd[6]), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_RX_RD_5_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m2_i_m3_0_5__1700), + .Q(com_llm_llm_rx_top_rx_rd[5]), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_RX_RD_4_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m2_i_m3_0_4__1701), + .Q(com_llm_llm_rx_top_rx_rd[4]), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_RX_RD_3_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m2_i_m3_0_3__1702), + .Q(com_llm_llm_rx_top_rx_rd[3]), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_RX_RD_2_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m2_i_m3_0_2__1703), + .Q(com_llm_llm_rx_top_rx_rd[2]), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_RX_RD_1_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m2_i_m3_0_1__1704), + .Q(com_llm_llm_rx_top_rx_rd[1]), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_RX_RD_0_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m2_i_m3_0_0__1705), + .Q(com_llm_llm_rx_top_rx_rd[0]), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_rx_tlp_tsn_d_11_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_tlp_tsn_dd[11]), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_tlp_tsn_d[11]), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_rx_tlp_tsn_d_10_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_tlp_tsn_dd[10]), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_tlp_tsn_d[10]), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_rx_tlp_tsn_d_9_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_tlp_tsn_dd[9]), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_tlp_tsn_d[9]), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_rx_tlp_tsn_d_8_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_tlp_tsn_dd[8]), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_tlp_tsn_d[8]), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_RX_RD_25_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m2_i_m3_0_25__1706), + .Q(com_llm_llm_rx_top_rx_rd[25]), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_RX_RD_24_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m2_i_m3_0_24__1707), + .Q(com_llm_llm_rx_top_rx_rd[24]), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_RX_RD_23_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m2_i_m3_0_23__1708), + .Q(com_llm_llm_rx_top_rx_rd[23]), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_RX_RD_22_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m2_i_m3_0_22__1709), + .Q(com_llm_llm_rx_top_rx_rd[22]), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_RX_RD_21_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m2_i_m3_0_21__1710), + .Q(com_llm_llm_rx_top_rx_rd[21]), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_RX_RD_20_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m2_i_m3_0_20__1711), + .Q(com_llm_llm_rx_top_rx_rd[20]), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_RX_RD_19_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m2_i_m3_0_19__1712), + .Q(com_llm_llm_rx_top_rx_rd[19]), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_RX_RD_18_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m2_i_m3_0_18__1713), + .Q(com_llm_llm_rx_top_rx_rd[18]), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_RX_RD_17_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m2_i_m3_0_17__1714), + .Q(com_llm_llm_rx_top_rx_rd[17]), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_RX_RD_16_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m2_i_m3_0_16__1715), + .Q(com_llm_llm_rx_top_rx_rd[16]), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_RX_RD_15_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m2_i_m3_0_15__1716), + .Q(com_llm_llm_rx_top_rx_rd[15]), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_RX_RD_14_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m2_i_m3_0_14__1717), + .Q(com_llm_llm_rx_top_rx_rd[14]), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_RX_RD_13_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m2_i_m3_0_13__1718), + .Q(com_llm_llm_rx_top_rx_rd[13]), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_RX_RD_12_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m2_i_m3_0_12__1719), + .Q(com_llm_llm_rx_top_rx_rd[12]), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_RX_RD_11_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m2_i_m3_0_11__1720), + .Q(com_llm_llm_rx_top_rx_rd[11]), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_RX_RD_40_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m2_i_m3_0_40__1721), + .Q(com_llm_llm_rx_top_rx_rd[40]), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_RX_RD_39_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m2_i_m3_0_39__1722), + .Q(com_llm_llm_rx_top_rx_rd[39]), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_RX_RD_38_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m2_i_m3_0_38__1723), + .Q(com_llm_llm_rx_top_rx_rd[38]), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_RX_RD_37_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m2_i_m3_0_37__1724), + .Q(com_llm_llm_rx_top_rx_rd[37]), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_RX_RD_36_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m2_i_m3_0_36__1725), + .Q(com_llm_llm_rx_top_rx_rd[36]), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_RX_RD_35_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m2_i_m3_0_35__1726), + .Q(com_llm_llm_rx_top_rx_rd[35]), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_RX_RD_34_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m2_i_m3_0_34__1727), + .Q(com_llm_llm_rx_top_rx_rd[34]), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_RX_RD_33_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m2_i_m3_0_33__1728), + .Q(com_llm_llm_rx_top_rx_rd[33]), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_RX_RD_32_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m2_i_m3_0_32__1729), + .Q(com_llm_llm_rx_top_rx_rd[32]), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_RX_RD_31_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m2_i_m3_0_31__1730), + .Q(com_llm_llm_rx_top_rx_rd[31]), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_RX_RD_30_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m2_i_m3_0_30__1731), + .Q(com_llm_llm_rx_top_rx_rd[30]), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_RX_RD_29_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m2_i_m3_0_29__1732), + .Q(com_llm_llm_rx_top_rx_rd[29]), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_RX_RD_28_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m2_i_m3_0_28__1733), + .Q(com_llm_llm_rx_top_rx_rd[28]), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_RX_RD_27_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m2_i_m3_0_27__1734), + .Q(com_llm_llm_rx_top_rx_rd[27]), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_RX_RD_26_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m2_i_m3_0_26__1735), + .Q(com_llm_llm_rx_top_rx_rd[26]), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_RX_RD_55_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m2_i_m3_0_55__1736), + .Q(com_llm_llm_rx_top_rx_rd[55]), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_RX_RD_54_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m2_i_m3_0_54__1737), + .Q(com_llm_llm_rx_top_rx_rd[54]), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_RX_RD_53_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m2_i_m3_0_53__1738), + .Q(com_llm_llm_rx_top_rx_rd[53]), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_RX_RD_52_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m2_i_m3_0_52__1739), + .Q(com_llm_llm_rx_top_rx_rd[52]), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_RX_RD_51_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m2_i_m3_0_51__1740), + .Q(com_llm_llm_rx_top_rx_rd[51]), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_RX_RD_50_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m2_i_m3_0_50__1741), + .Q(com_llm_llm_rx_top_rx_rd[50]), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_RX_RD_49_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m2_i_m3_0_49__1742), + .Q(com_llm_llm_rx_top_rx_rd[49]), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_RX_RD_48_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m2_i_m3_0_48__1743), + .Q(com_llm_llm_rx_top_rx_rd[48]), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_RX_RD_47_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m3_0_47__1744), + .Q(com_llm_llm_rx_top_rx_rd[47]), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_RX_RD_46_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m2_i_m3_0_46__1745), + .Q(com_llm_llm_rx_top_rx_rd[46]), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_RX_RD_45_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m3_0_45__1746), + .Q(com_llm_llm_rx_top_rx_rd[45]), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_RX_RD_44_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m2_i_m3_0_44__1747), + .Q(com_llm_llm_rx_top_rx_rd[44]), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_RX_RD_43_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m2_i_m3_0_43__1748), + .Q(com_llm_llm_rx_top_rx_rd[43]), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_RX_RD_42_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m2_i_m3_0_42__1749), + .Q(com_llm_llm_rx_top_rx_rd[42]), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_RX_RD_41_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m2_i_m3_0_41__1750), + .Q(com_llm_llm_rx_top_rx_rd[41]), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_RX_RD_63_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m2_i_m3_0_63__1751), + .Q(com_llm_llm_rx_top_rx_rd[63]), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_RX_RD_62_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m2_i_m3_0_62__1752), + .Q(com_llm_llm_rx_top_rx_rd[62]), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_RX_RD_61_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m2_i_m3_0_61__1753), + .Q(com_llm_llm_rx_top_rx_rd[61]), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_RX_RD_60_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m2_i_m3_0_60__1754), + .Q(com_llm_llm_rx_top_rx_rd[60]), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_RX_RD_59_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m2_i_m3_0_59__1755), + .Q(com_llm_llm_rx_top_rx_rd[59]), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_RX_RD_58_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m2_i_m3_0_58__1756), + .Q(com_llm_llm_rx_top_rx_rd[58]), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_RX_RD_57_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m2_i_m3_0_57__1757), + .Q(com_llm_llm_rx_top_rx_rd[57]), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_RX_RD_56_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m2_i_m3_0_56__1758), + .Q(com_llm_llm_rx_top_rx_rd[56]), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_62_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_data_q_5080[6]), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_62__1772), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_61_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_data_q_5080[5]), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_61__1773), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_60_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_data_q_5080[4]), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_60__1774), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_59_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_data_q_5080[3]), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_59__1775), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_58_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_data_q_5080[2]), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_58__1776), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_57_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_data_q_5080[1]), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_57__1777), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_56_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_data_q[0]), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_56__1762), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_55_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_rx_data_63_), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_55__1763), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_54_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_rx_data_62_), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_54__1764), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_53_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_rx_data_61_), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_53__1765), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_52_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_rx_data_60_), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_52__1766), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_51_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_rx_data_59_), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_51__1767), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_50_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_rx_data_58_), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_50__1768), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_49_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_rx_data_57_), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_49__1769), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_48_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_rx_data_56_), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_48__1770), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sh_45_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl[13]), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sh[45]), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sh_44_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl[12]), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sh[44]), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sh_43_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl[11]), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sh[43]), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sh_42_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl[10]), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sh[42]), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sh_41_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl[9]), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sh[41]), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sh_40_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl[8]), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sh[40]), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sh_39_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl[7]), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sh[39]), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sh_38_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl[6]), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sh[38]), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sh_37_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl[5]), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sh[37]), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sh_36_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl[4]), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sh[36]), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sh_35_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl[3]), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sh[35]), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sh_34_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl[2]), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sh[34]), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sh_33_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl[1]), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sh[33]), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sh_32_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl[0]), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sh[32]), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_63_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_data_q_5080[7]), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_63__1771), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sh_60_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl[28]), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sh[60]), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sh_59_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl[27]), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sh[59]), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sh_58_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl[26]), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sh[58]), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sh_57_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl[25]), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sh[57]), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sh_56_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl[24]), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sh[56]), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sh_55_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl[23]), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sh[55]), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sh_54_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl[22]), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sh[54]), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sh_53_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl[21]), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sh[53]), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sh_52_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl[20]), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sh[52]), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sh_51_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl[19]), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sh[51]), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sh_50_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl[18]), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sh[50]), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sh_49_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl[17]), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sh[49]), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sh_48_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl[16]), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sh[48]), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sh_47_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl[15]), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sh[47]), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sh_46_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl[14]), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sh[46]), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d64_11_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_new_c64[11]), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d64_11__318), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d64_10_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_new_c64[10]), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d64_10__1759), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d64_9_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_new_c64[9]), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d64_9__320), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d64_8_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_new_c64[8]), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d64_8__311), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d64_7_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_new_c64[7]), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d64_7__310), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d64_6_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_new_c64[6]), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d64_6__322), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d64_5_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_new_c64[5]), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d64_5__317), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d64_4_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_new_c64[4]), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d64_4__1760), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d64_3_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_new_c64[3]), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d64_3__52), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d64_2_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_new_c64[2]), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d64_2__53), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d64_1_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_new_c64[1]), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d64_1__1761), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d64_0_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_new_c64[0]), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d64_0__324), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sh_63_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl[31]), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sh[63]), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sh_62_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl[30]), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sh[62]), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sh_61_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl[29]), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sh[61]), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d64_26_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_new_c64[26]), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d64_26__283), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d64_25_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_new_c64[25]), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d64_25__314), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d64_24_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_new_c64[24]), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d64_24__269), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d64_23_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_new_c64[23]), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d64_23__315), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d64_22_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_new_c64[22]), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d64_22__48), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d64_21_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_new_c64[21]), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d64_21__312), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d64_20_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_new_c64[20]), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d64_20__54), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d64_19_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_new_c64[19]), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d64_19__49), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d64_18_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_new_c64[18]), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d64_18__45), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d64_17_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_new_c64[17]), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d64_17__313), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d64_16_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_new_c64[16]), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d64_16__47), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d64_15_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_new_c64[15]), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d64_15__287), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d64_14_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_new_c64[14]), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d64_14__319), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d64_13_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_new_c64[13]), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d64_13__316), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d64_12_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_new_c64[12]), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d64_12__321), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d16_9_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_new_c16[9]), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d16[9]), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d16_8_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_new_c16[8]), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d16[8]), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d16_7_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_new_c16[7]), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d16[7]), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d16_6_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_new_c16[6]), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d16[6]), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d16_5_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_new_c16[5]), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d16[5]), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d16_4_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_new_c16[4]), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d16[4]), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d16_3_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_new_c16[3]), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d16[3]), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d16_2_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_new_c16[2]), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d16[2]), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d16_1_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_new_c16[1]), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d16[1]), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d16_0_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_new_c16[0]), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d16[0]), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d64_31_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_new_c64[31]), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d64_31__50), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d64_30_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_new_c64[30]), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d64_30__46), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d64_29_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_new_c64[29]), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d64_29__270), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d64_28_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_new_c64[28]), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d64_28__286), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d64_27_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_new_c64[27]), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d64_27__323), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d16_24_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_new_c16[24]), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d16[24]), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d16_23_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_new_c16[23]), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d16[23]), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d16_22_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_new_c16[22]), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d16[22]), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d16_21_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_new_c16[21]), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d16[21]), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d16_20_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_new_c16[20]), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d16[20]), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d16_19_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_new_c16[19]), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d16[19]), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d16_18_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_new_c16[18]), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d16[18]), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d16_17_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_new_c16[17]), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d16[17]), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d16_16_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_new_c16[16]), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d16[16]), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d16_15_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_new_c16[15]), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d16[15]), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d16_14_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_new_c16[14]), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d16[14]), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d16_13_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_new_c16[13]), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d16[13]), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d16_12_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_new_c16[12]), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d16[12]), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d16_11_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_new_c16[11]), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d16[11]), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d16_10_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_new_c16[10]), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d16[10]), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_rx_data_bit_swap_q_15_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_rx_data_8_), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_0_), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_rx_data_bit_swap_q_14_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_rx_data_9_), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_1_), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_rx_data_bit_swap_q_13_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_rx_data_10_), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_2_), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_rx_data_bit_swap_q_12_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_rx_data_11_), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_3_), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_rx_data_bit_swap_q_11_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_rx_data_12_), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_4_), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_rx_data_bit_swap_q_10_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_rx_data_13_), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_5_), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_rx_data_bit_swap_q_9_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_rx_data_14_), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_6_), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_rx_data_bit_swap_q_8_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_rx_data_15_), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_7_), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d16_31_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_new_c16[31]), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d16[31]), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d16_30_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_new_c16[30]), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d16[30]), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d16_29_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_new_c16[29]), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d16[29]), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d16_28_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_new_c16[28]), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d16[28]), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d16_27_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_new_c16[27]), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d16[27]), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d16_26_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_new_c16[26]), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d16[26]), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d16_25_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_new_c16[25]), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d16[25]), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_rx_data_bit_swap_q_30_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_rx_data_25_), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_17_), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_rx_data_bit_swap_q_29_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_rx_data_26_), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_18_), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_rx_data_bit_swap_q_28_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_rx_data_27_), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_19_), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_rx_data_bit_swap_q_27_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_rx_data_28_), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_20_), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_rx_data_bit_swap_q_26_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_rx_data_29_), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_21_), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_rx_data_bit_swap_q_25_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_rx_data_30_), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_22_), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_rx_data_bit_swap_q_24_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_rx_data_31_), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_23_), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_rx_data_bit_swap_q_23_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_rx_data_16_), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_8_), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_rx_data_bit_swap_q_22_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_rx_data_17_), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_9_), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_rx_data_bit_swap_q_21_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_rx_data_18_), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_10_), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_rx_data_bit_swap_q_20_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_rx_data_19_), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_11_), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_rx_data_bit_swap_q_19_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_rx_data_20_), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_12_), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_rx_data_bit_swap_q_18_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_rx_data_21_), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_13_), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_rx_data_bit_swap_q_17_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_rx_data_22_), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_14_), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_rx_data_bit_swap_q_16_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_rx_data_23_), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_15_), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_rx_data_bit_swap_q_45_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_rx_data_42_), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_34_), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_rx_data_bit_swap_q_44_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_rx_data_43_), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_35_), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_rx_data_bit_swap_q_43_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_rx_data_44_), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_36_), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_rx_data_bit_swap_q_42_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_rx_data_45_), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_37_), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_rx_data_bit_swap_q_41_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_rx_data_46_), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_38_), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_rx_data_bit_swap_q_40_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_rx_data_47_), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_39_), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_rx_data_bit_swap_q_39_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_rx_data_32_), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_24_), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_rx_data_bit_swap_q_38_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_rx_data_33_), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_25_), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_rx_data_bit_swap_q_37_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_rx_data_34_), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_26_), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_rx_data_bit_swap_q_36_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_rx_data_35_), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_27_), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_rx_data_bit_swap_q_35_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_rx_data_36_), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_28_), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_rx_data_bit_swap_q_34_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_rx_data_37_), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_29_), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_rx_data_bit_swap_q_33_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_rx_data_38_), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_30_), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_rx_data_bit_swap_q_32_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_rx_data_39_), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_31_), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_rx_data_bit_swap_q_31_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_rx_data_24_), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_16_), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_rx_data_q_4_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_rx_data_4_), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_data_q_5080[4]), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_rx_data_q_3_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_rx_data_3_), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_data_q_5080[3]), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_rx_data_q_2_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_rx_data_2_), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_data_q_5080[2]), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_rx_data_q_1_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_rx_data_1_), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_data_q_5080[1]), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_rx_data_q_0_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_rx_data_0_), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_data_q[0]), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_rx_data_bit_swap_q_55_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_rx_data_48_), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_40_), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_rx_data_bit_swap_q_54_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_rx_data_49_), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_41_), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_rx_data_bit_swap_q_53_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_rx_data_50_), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_42_), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_rx_data_bit_swap_q_52_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_rx_data_51_), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_43_), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_rx_data_bit_swap_q_51_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_rx_data_52_), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_44_), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_rx_data_bit_swap_q_50_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_rx_data_53_), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_45_), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_rx_data_bit_swap_q_49_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_rx_data_54_), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_46_), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_rx_data_bit_swap_q_48_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_rx_data_55_), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_47_), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_rx_data_bit_swap_q_47_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_rx_data_40_), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_32_), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_rx_data_bit_swap_q_46_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_rx_data_41_), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_33_), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_11_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_11_), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl[11]), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_10_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_10_), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl[10]), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_9_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_9_), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl[9]), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_8_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_8_), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl[8]), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_7_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_7_), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl[7]), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_6_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_6_), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl[6]), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_5_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_5_), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl[5]), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_4_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_4_), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl[4]), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_3_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_3_), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl[3]), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_2_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_2_), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl[2]), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_1_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_1_), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl[1]), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_0_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_0_), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl[0]), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_rx_data_q_7_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_rx_data_7_), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_data_q_5080[7]), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_rx_data_q_6_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_rx_data_6_), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_data_q_5080[6]), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_rx_data_q_5_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_rx_data_5_), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_data_q_5080[5]), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_26_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_26_), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl[26]), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_25_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_25_), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl[25]), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_24_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_24_), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl[24]), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_23_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_23_), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl[23]), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_22_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_22_), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl[22]), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_21_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_21_), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl[21]), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_20_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_20_), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl[20]), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_19_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_19_), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl[19]), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_18_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_18_), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl[18]), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_17_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_17_), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl[17]), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_16_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_16_), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl[16]), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_15_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_15_), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl[15]), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_14_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_14_), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl[14]), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_13_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_13_), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl[13]), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_12_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_12_), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl[12]), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_41_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_41_), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl[41]), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_40_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_40_), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl[40]), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_39_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_39_), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl[39]), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_38_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_38_), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl[38]), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_37_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_37_), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl[37]), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_36_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_36_), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl[36]), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_35_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_35_), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl[35]), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_34_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_34_), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl[34]), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_33_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_33_), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl[33]), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_32_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_32_), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl[32]), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_31_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_31_), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl[31]), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_30_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_30_), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl[30]), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_29_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_29_), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl[29]), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_28_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_28_), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl[28]), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_27_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_27_), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl[27]), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_56_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_56__1762), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl[56]), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_55_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_55__1763), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl[55]), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_54_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_54__1764), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl[54]), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_53_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_53__1765), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl[53]), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_52_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_52__1766), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl[52]), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_51_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_51__1767), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl[51]), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_50_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_50__1768), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl[50]), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_49_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_49__1769), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl[49]), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_48_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_48__1770), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl[48]), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_47_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_47_), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl[47]), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_46_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_46_), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl[46]), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_45_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_45_), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl[45]), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_44_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_44_), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl[44]), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_43_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_43_), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl[43]), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_42_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_42_), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl[42]), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_RX_TLP_TSN_7_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_tlp_tsn_d[7]), + .Q(com_llm_llm_rx_top_rx_tlp_tsn[7]), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_RX_TLP_TSN_6_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_tlp_tsn_d[6]), + .Q(com_llm_llm_rx_top_rx_tlp_tsn[6]), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_RX_TLP_TSN_5_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_tlp_tsn_d[5]), + .Q(com_llm_llm_rx_top_rx_tlp_tsn[5]), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_RX_TLP_TSN_4_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_tlp_tsn_d[4]), + .Q(com_llm_llm_rx_top_rx_tlp_tsn[4]), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_RX_TLP_TSN_3_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_tlp_tsn_d[3]), + .Q(com_llm_llm_rx_top_rx_tlp_tsn[3]), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_RX_TLP_TSN_2_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_tlp_tsn_d[2]), + .Q(com_llm_llm_rx_top_rx_tlp_tsn[2]), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_RX_TLP_TSN_1_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_tlp_tsn_d[1]), + .Q(com_llm_llm_rx_top_rx_tlp_tsn[1]), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_RX_TLP_TSN_0_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_tlp_tsn_d[0]), + .Q(com_llm_llm_rx_top_rx_tlp_tsn[0]), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_63_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_63__1771), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl[63]), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_62_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_62__1772), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl[62]), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_61_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_61__1773), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl[61]), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_60_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_60__1774), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl[60]), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_59_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_59__1775), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl[59]), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_58_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_58__1776), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl[58]), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_57_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_57__1777), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl[57]), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_RX_TLP_TSN_11_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_tlp_tsn_d[11]), + .Q(com_llm_llm_rx_top_rx_tlp_tsn[11]), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_RX_TLP_TSN_10_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_tlp_tsn_d[10]), + .Q(com_llm_llm_rx_top_rx_tlp_tsn[10]), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_RX_TLP_TSN_9_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_tlp_tsn_d[9]), + .Q(com_llm_llm_rx_top_rx_tlp_tsn[9]), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_RX_TLP_TSN_8_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_tlp_tsn_d[8]), + .Q(com_llm_llm_rx_top_rx_tlp_tsn[8]), + .CLR(plm_link_up_i) + ); + FDCE com_llm_llm_rx_top_llm_rx_tlp_crc_tlp_nullified_latch ( + .CE(com_llm_llm_rx_top_rx_tlp_eof_n_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_rx_tlp_nullified), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_tlp_nullified_latch_1778), + .CLR(plm_link_up_i) + ); + FDCE com_llm_llm_rx_top_llm_rx_tlp_crc_frame_error_latch ( + .CE(com_llm_llm_rx_top_rx_tlp_eof_n_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_rx_tferr_n_i), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_frame_error_latch_1779), + .CLR(plm_link_up_i) + ); + FDPE com_llm_llm_rx_top_llm_rx_tlp_crc_start_high_latch ( + .PRE(plm_link_up_i), + .CE(com_llm_llm_rx_top_rx_tlp_sof_n_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_start_high_latch_3), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_start_high_latch_309) + ); + FDCE com_llm_llm_rx_top_llm_rx_tlp_crc_end_low_latch ( + .CE(com_llm_llm_rx_top_rx_tlp_eof_n_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_end_low_latch_3), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_end_low_latch_1780), + .CLR(plm_link_up_i) + ); + FDPE com_llm_llm_rx_top_llm_rx_tlp_crc_RX_RSRC_RDY_N ( + .PRE(plm_link_up_i), + .CE(com_llm_llm_rx_top_llm_rx_tlp_crc_N_30983_i_1781), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rsof_nd_1782), + .Q(com_llm_llm_rx_top_rx_rsrc_rdy_n) + ); + FDCE com_llm_llm_rx_top_llm_rx_tlp_crc_tlp_in_progress ( + .CE(com_llm_llm_rx_top_llm_rx_tlp_crc_N_27393_i_0), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_rx_tlp_eof_n), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_tlp_in_progress_1783), + .CLR(plm_link_up_i) + ); + FDCE com_llm_llm_rx_top_llm_rx_tlp_crc_rx_tlp_tsn_dd_11_ ( + .CE(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_tlp_sof_nq_i_1788), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_tlp_tsn_dd_5_i_m3_i_m3_0[11]), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_tlp_tsn_dd[11]), + .CLR(plm_link_up_i) + ); + FDCE com_llm_llm_rx_top_llm_rx_tlp_crc_rx_tlp_tsn_dd_10_ ( + .CE(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_tlp_sof_nq_i_1788), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_tlp_tsn_dd_5_i_m3_i_m3_0[10]), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_tlp_tsn_dd[10]), + .CLR(plm_link_up_i) + ); + FDCE com_llm_llm_rx_top_llm_rx_tlp_crc_rx_tlp_tsn_dd_9_ ( + .CE(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_tlp_sof_nq_i_1788), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_tlp_tsn_dd_5_i_m3_i_m3_0[9]), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_tlp_tsn_dd[9]), + .CLR(plm_link_up_i) + ); + FDCE com_llm_llm_rx_top_llm_rx_tlp_crc_rx_tlp_tsn_dd_8_ ( + .CE(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_tlp_sof_nq_i_1788), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_tlp_tsn_dd_5_i_m3_i_m3_0[8]), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_tlp_tsn_dd[8]), + .CLR(plm_link_up_i) + ); + FDCE com_llm_llm_rx_top_llm_rx_tlp_crc_rx_tlp_tsn_dd_7_ ( + .CE(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_tlp_sof_nq_i_1788), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_tlp_tsn_dd_5_i_m3_i_m3_0[7]), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_tlp_tsn_dd[7]), + .CLR(plm_link_up_i) + ); + FDCE com_llm_llm_rx_top_llm_rx_tlp_crc_rx_tlp_tsn_dd_6_ ( + .CE(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_tlp_sof_nq_i_1788), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_tlp_tsn_dd_5_i_m3_i_m3_0[6]), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_tlp_tsn_dd[6]), + .CLR(plm_link_up_i) + ); + FDCE com_llm_llm_rx_top_llm_rx_tlp_crc_rx_tlp_tsn_dd_5_ ( + .CE(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_tlp_sof_nq_i_1788), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_tlp_tsn_dd_5_i_m3_i_m3_0[5]), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_tlp_tsn_dd[5]), + .CLR(plm_link_up_i) + ); + FDCE com_llm_llm_rx_top_llm_rx_tlp_crc_rx_tlp_tsn_dd_4_ ( + .CE(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_tlp_sof_nq_i_1788), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_tlp_tsn_dd_5_i_m3_i_m3_0[4]), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_tlp_tsn_dd[4]), + .CLR(plm_link_up_i) + ); + FDCE com_llm_llm_rx_top_llm_rx_tlp_crc_rx_tlp_tsn_dd_3_ ( + .CE(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_tlp_sof_nq_i_1788), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_tlp_tsn_dd_5_i_m3_i_m3_0[3]), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_tlp_tsn_dd[3]), + .CLR(plm_link_up_i) + ); + FDCE com_llm_llm_rx_top_llm_rx_tlp_crc_rx_tlp_tsn_dd_2_ ( + .CE(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_tlp_sof_nq_i_1788), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_tlp_tsn_dd_5_i_m3_i_m3_0[2]), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_tlp_tsn_dd[2]), + .CLR(plm_link_up_i) + ); + FDCE com_llm_llm_rx_top_llm_rx_tlp_crc_rx_tlp_tsn_dd_1_ ( + .CE(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_tlp_sof_nq_i_1788), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_tlp_tsn_dd_5_i_m3_i_m3_0[1]), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_tlp_tsn_dd[1]), + .CLR(plm_link_up_i) + ); + FDCE com_llm_llm_rx_top_llm_rx_tlp_crc_rx_tlp_tsn_dd_0_ ( + .CE(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_tlp_sof_nq_i_1788), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_tlp_tsn_dd_5_i_m3_i_m3_0[0]), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_tlp_tsn_dd[0]), + .CLR(plm_link_up_i) + ); + FDPE com_llm_llm_rx_top_llm_rx_tlp_crc_rx_tlp_sof_nqq ( + .PRE(plm_link_up_i), + .CE(com_llm_llm_rx_top_llm_rx_tlp_crc_N_68796_i_1784), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_tlp_sof_nq_1789), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_tlp_sof_nqq_1785) + ); + FDPE com_llm_llm_rx_top_llm_rx_tlp_crc_rx_tlp_eof_nq ( + .PRE(plm_link_up_i), + .CE(com_llm_llm_rx_top_llm_rx_tlp_crc_N_68809_i_1786), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_rx_tlp_eof_n), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_tlp_eof_nq_1787) + ); + INV com_llm_llm_rx_top_llm_rx_tlp_crc_rx_tlp_sof_nq_i ( + .I(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_tlp_sof_nq_1789), + .O(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_tlp_sof_nq_i_1788) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_un3_crc32_com_ok_0_I_36.INIT = 4'h1; + LUT2 com_llm_llm_rx_top_llm_rx_tlp_crc_un3_crc32_com_ok_0_I_36 ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_N_102), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_N_103), + .O(com_llm_llm_rx_top_llm_rx_tlp_crc_N_99_0) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_un4_crc32_com_ok_0_I_36.INIT = 4'h8; + LUT2 com_llm_llm_rx_top_llm_rx_tlp_crc_un4_crc32_com_ok_0_I_36 ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_N_102), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_N_103), + .O(com_llm_llm_rx_top_llm_rx_tlp_crc_N_99) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_un3_crc32_res_ok_7_and_0_a2.INIT = 8'h10; + LUT3 com_llm_llm_rx_top_llm_rx_tlp_crc_un3_crc32_res_ok_7_and_0_a2 ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d16[30]), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d16[31]), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_un3_crc32_res_ok_7_and_1), + .O(com_llm_llm_rx_top_llm_rx_tlp_crc_un3_crc32_res_ok_7_and) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_un3_crc32_res_ok_6_and_0_a2.INIT = 16'h0001; + LUT4 com_llm_llm_rx_top_llm_rx_tlp_crc_un3_crc32_res_ok_6_and_0_a2 ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d16[24]), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d16[25]), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d16[26]), + .I3(com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d16[27]), + .O(com_llm_llm_rx_top_llm_rx_tlp_crc_un3_crc32_res_ok_6_and) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_un3_crc32_res_ok_5_and_0_a2.INIT = 4'h4; + LUT2 com_llm_llm_rx_top_llm_rx_tlp_crc_un3_crc32_res_ok_5_and_0_a2 ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d16[20]), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_un6_crc32_res_ok_2_and_1), + .O(com_llm_llm_rx_top_llm_rx_tlp_crc_un3_crc32_res_ok_5_and) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_un3_crc32_res_ok_4_and_0_a2.INIT = 4'h4; + LUT2 com_llm_llm_rx_top_llm_rx_tlp_crc_un3_crc32_res_ok_4_and_0_a2 ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d16[18]), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_un6_crc32_res_ok_1_and_1), + .O(com_llm_llm_rx_top_llm_rx_tlp_crc_un3_crc32_res_ok_4_and) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_un3_crc32_res_ok_3_and_0_a2.INIT = 16'h0001; + LUT4 com_llm_llm_rx_top_llm_rx_tlp_crc_un3_crc32_res_ok_3_and_0_a2 ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d16[12]), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d16[13]), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d16[14]), + .I3(com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d16[15]), + .O(com_llm_llm_rx_top_llm_rx_tlp_crc_un3_crc32_res_ok_3_and) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_un3_crc32_res_ok_2_and_0_a2.INIT = 16'h0001; + LUT4 com_llm_llm_rx_top_llm_rx_tlp_crc_un3_crc32_res_ok_2_and_0_a2 ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d16[8]), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d16[9]), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d16[10]), + .I3(com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d16[11]), + .O(com_llm_llm_rx_top_llm_rx_tlp_crc_un3_crc32_res_ok_2_and) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_un3_crc32_res_ok_1_and_0_a2.INIT = 16'h0001; + LUT4 com_llm_llm_rx_top_llm_rx_tlp_crc_un3_crc32_res_ok_1_and_0_a2 ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d16[4]), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d16[5]), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d16[6]), + .I3(com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d16[7]), + .O(com_llm_llm_rx_top_llm_rx_tlp_crc_un3_crc32_res_ok_1_and) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_un3_crc32_res_ok_0_and_0_a2.INIT = 16'h0001; + LUT4 com_llm_llm_rx_top_llm_rx_tlp_crc_un3_crc32_res_ok_0_and_0_a2 ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d16[0]), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d16[1]), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d16[2]), + .I3(com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d16[3]), + .O(com_llm_llm_rx_top_llm_rx_tlp_crc_un3_crc32_res_ok_0_and) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_un6_crc32_res_ok_7_and_0_a2.INIT = 16'h8000; + LUT4 com_llm_llm_rx_top_llm_rx_tlp_crc_un6_crc32_res_ok_7_and_0_a2 ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d16[25]), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d16[26]), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d16[30]), + .I3(com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d16[31]), + .O(com_llm_llm_rx_top_llm_rx_tlp_crc_un6_crc32_res_ok_7_and) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_un6_crc32_res_ok_6_and_0_a2.INIT = 16'h8000; + LUT4 com_llm_llm_rx_top_llm_rx_tlp_crc_un6_crc32_res_ok_6_and_0_a2 ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d16[14]), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d16[15]), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d16[18]), + .I3(com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d16[24]), + .O(com_llm_llm_rx_top_llm_rx_tlp_crc_un6_crc32_res_ok_6_and) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_un6_crc32_res_ok_5_and_0_a2.INIT = 16'h8000; + LUT4 com_llm_llm_rx_top_llm_rx_tlp_crc_un6_crc32_res_ok_5_and_0_a2 ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d16[8]), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d16[10]), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d16[11]), + .I3(com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d16[12]), + .O(com_llm_llm_rx_top_llm_rx_tlp_crc_un6_crc32_res_ok_5_and) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_un6_crc32_res_ok_4_and_0_a2.INIT = 16'h8000; + LUT4 com_llm_llm_rx_top_llm_rx_tlp_crc_un6_crc32_res_ok_4_and_0_a2 ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d16[3]), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d16[4]), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d16[5]), + .I3(com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d16[6]), + .O(com_llm_llm_rx_top_llm_rx_tlp_crc_un6_crc32_res_ok_4_and) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_un6_crc32_res_ok_3_and_0_a2.INIT = 8'h80; + LUT3 com_llm_llm_rx_top_llm_rx_tlp_crc_un6_crc32_res_ok_3_and_0_a2 ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d16[0]), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d16[1]), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_un3_crc32_res_ok_7_and_1), + .O(com_llm_llm_rx_top_llm_rx_tlp_crc_un6_crc32_res_ok_3_and) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_un6_crc32_res_ok_2_and_0_a2.INIT = 4'h4; + LUT2 com_llm_llm_rx_top_llm_rx_tlp_crc_un6_crc32_res_ok_2_and_0_a2 ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d16[27]), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_un6_crc32_res_ok_2_and_1), + .O(com_llm_llm_rx_top_llm_rx_tlp_crc_un6_crc32_res_ok_2_and) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_un6_crc32_res_ok_1_and_0_a2.INIT = 4'h4; + LUT2 com_llm_llm_rx_top_llm_rx_tlp_crc_un6_crc32_res_ok_1_and_0_a2 ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d16[20]), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_un6_crc32_res_ok_1_and_1), + .O(com_llm_llm_rx_top_llm_rx_tlp_crc_un6_crc32_res_ok_1_and) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_un6_crc32_res_ok_0_and_0_a2.INIT = 16'h0001; + LUT4 com_llm_llm_rx_top_llm_rx_tlp_crc_un6_crc32_res_ok_0_and_0_a2 ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d16[2]), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d16[7]), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d16[9]), + .I3(com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d16[13]), + .O(com_llm_llm_rx_top_llm_rx_tlp_crc_un6_crc32_res_ok_0_and) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_un4_crc32_com_ok_0_I_144.INIT = 4'h8; + LUT2 com_llm_llm_rx_top_llm_rx_tlp_crc_un4_crc32_com_ok_0_I_144 ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_N_6), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_N_7), + .O(com_llm_llm_rx_top_llm_rx_tlp_crc_N_3_0) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_un4_crc32_com_ok_0_I_135.INIT = 4'h8; + LUT2 com_llm_llm_rx_top_llm_rx_tlp_crc_un4_crc32_com_ok_0_I_135 ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_N_14), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_N_15), + .O(com_llm_llm_rx_top_llm_rx_tlp_crc_N_11_0) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_un4_crc32_com_ok_0_I_126.INIT = 4'h8; + LUT2 com_llm_llm_rx_top_llm_rx_tlp_crc_un4_crc32_com_ok_0_I_126 ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_N_22), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_N_23), + .O(com_llm_llm_rx_top_llm_rx_tlp_crc_N_19_0) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_un4_crc32_com_ok_0_I_117.INIT = 4'h8; + LUT2 com_llm_llm_rx_top_llm_rx_tlp_crc_un4_crc32_com_ok_0_I_117 ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_N_30), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_N_31), + .O(com_llm_llm_rx_top_llm_rx_tlp_crc_N_27_0) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_un4_crc32_com_ok_0_I_108.INIT = 4'h8; + LUT2 com_llm_llm_rx_top_llm_rx_tlp_crc_un4_crc32_com_ok_0_I_108 ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_N_38), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_N_39), + .O(com_llm_llm_rx_top_llm_rx_tlp_crc_N_35_0) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_un4_crc32_com_ok_0_I_99.INIT = 4'h8; + LUT2 com_llm_llm_rx_top_llm_rx_tlp_crc_un4_crc32_com_ok_0_I_99 ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_N_46), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_N_47), + .O(com_llm_llm_rx_top_llm_rx_tlp_crc_N_43_0) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_un4_crc32_com_ok_0_I_90.INIT = 4'h8; + LUT2 com_llm_llm_rx_top_llm_rx_tlp_crc_un4_crc32_com_ok_0_I_90 ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_N_54), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_N_55), + .O(com_llm_llm_rx_top_llm_rx_tlp_crc_N_51_0) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_un4_crc32_com_ok_0_I_81.INIT = 4'h1; + LUT2 com_llm_llm_rx_top_llm_rx_tlp_crc_un4_crc32_com_ok_0_I_81 ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_N_62), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_N_63), + .O(com_llm_llm_rx_top_llm_rx_tlp_crc_N_59_0) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_un4_crc32_com_ok_0_I_72.INIT = 4'h8; + LUT2 com_llm_llm_rx_top_llm_rx_tlp_crc_un4_crc32_com_ok_0_I_72 ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_N_70), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_N_71), + .O(com_llm_llm_rx_top_llm_rx_tlp_crc_N_67_0) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_un4_crc32_com_ok_0_I_63.INIT = 4'h8; + LUT2 com_llm_llm_rx_top_llm_rx_tlp_crc_un4_crc32_com_ok_0_I_63 ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_N_78), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_N_79), + .O(com_llm_llm_rx_top_llm_rx_tlp_crc_N_75_0) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_un4_crc32_com_ok_0_I_54.INIT = 4'h8; + LUT2 com_llm_llm_rx_top_llm_rx_tlp_crc_un4_crc32_com_ok_0_I_54 ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_N_86), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_N_87), + .O(com_llm_llm_rx_top_llm_rx_tlp_crc_N_83_0) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_un4_crc32_com_ok_0_I_45.INIT = 4'h8; + LUT2 com_llm_llm_rx_top_llm_rx_tlp_crc_un4_crc32_com_ok_0_I_45 ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_N_94), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_N_95), + .O(com_llm_llm_rx_top_llm_rx_tlp_crc_N_91_0) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_un4_crc32_com_ok_0_I_27.INIT = 4'h8; + LUT2 com_llm_llm_rx_top_llm_rx_tlp_crc_un4_crc32_com_ok_0_I_27 ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_N_110), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_N_111), + .O(com_llm_llm_rx_top_llm_rx_tlp_crc_N_107_0) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_un4_crc32_com_ok_0_I_18.INIT = 4'h8; + LUT2 com_llm_llm_rx_top_llm_rx_tlp_crc_un4_crc32_com_ok_0_I_18 ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_N_118), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_N_119), + .O(com_llm_llm_rx_top_llm_rx_tlp_crc_N_115_0) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_un4_crc32_com_ok_0_I_9.INIT = 4'h8; + LUT2 com_llm_llm_rx_top_llm_rx_tlp_crc_un4_crc32_com_ok_0_I_9 ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_N_126), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_N_127), + .O(com_llm_llm_rx_top_llm_rx_tlp_crc_N_123_0) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_un3_crc32_com_ok_0_I_144.INIT = 4'h1; + LUT2 com_llm_llm_rx_top_llm_rx_tlp_crc_un3_crc32_com_ok_0_I_144 ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_N_6), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_N_7), + .O(com_llm_llm_rx_top_llm_rx_tlp_crc_N_3) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_un3_crc32_com_ok_0_I_135.INIT = 4'h1; + LUT2 com_llm_llm_rx_top_llm_rx_tlp_crc_un3_crc32_com_ok_0_I_135 ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_N_14), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_N_15), + .O(com_llm_llm_rx_top_llm_rx_tlp_crc_N_11) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_un3_crc32_com_ok_0_I_126.INIT = 4'h1; + LUT2 com_llm_llm_rx_top_llm_rx_tlp_crc_un3_crc32_com_ok_0_I_126 ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_N_22), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_N_23), + .O(com_llm_llm_rx_top_llm_rx_tlp_crc_N_19) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_un3_crc32_com_ok_0_I_117.INIT = 4'h1; + LUT2 com_llm_llm_rx_top_llm_rx_tlp_crc_un3_crc32_com_ok_0_I_117 ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_N_30), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_N_31), + .O(com_llm_llm_rx_top_llm_rx_tlp_crc_N_27) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_un3_crc32_com_ok_0_I_108.INIT = 4'h1; + LUT2 com_llm_llm_rx_top_llm_rx_tlp_crc_un3_crc32_com_ok_0_I_108 ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_N_38), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_N_39), + .O(com_llm_llm_rx_top_llm_rx_tlp_crc_N_35) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_un3_crc32_com_ok_0_I_99.INIT = 4'h1; + LUT2 com_llm_llm_rx_top_llm_rx_tlp_crc_un3_crc32_com_ok_0_I_99 ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_N_46), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_N_47), + .O(com_llm_llm_rx_top_llm_rx_tlp_crc_N_43) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_un3_crc32_com_ok_0_I_90.INIT = 4'h1; + LUT2 com_llm_llm_rx_top_llm_rx_tlp_crc_un3_crc32_com_ok_0_I_90 ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_N_54), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_N_55), + .O(com_llm_llm_rx_top_llm_rx_tlp_crc_N_51) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_un3_crc32_com_ok_0_I_81.INIT = 4'h8; + LUT2 com_llm_llm_rx_top_llm_rx_tlp_crc_un3_crc32_com_ok_0_I_81 ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_N_62), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_N_63), + .O(com_llm_llm_rx_top_llm_rx_tlp_crc_N_59) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_un3_crc32_com_ok_0_I_72.INIT = 4'h1; + LUT2 com_llm_llm_rx_top_llm_rx_tlp_crc_un3_crc32_com_ok_0_I_72 ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_N_70), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_N_71), + .O(com_llm_llm_rx_top_llm_rx_tlp_crc_N_67) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_un3_crc32_com_ok_0_I_63.INIT = 4'h1; + LUT2 com_llm_llm_rx_top_llm_rx_tlp_crc_un3_crc32_com_ok_0_I_63 ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_N_78), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_N_79), + .O(com_llm_llm_rx_top_llm_rx_tlp_crc_N_75) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_un3_crc32_com_ok_0_I_54.INIT = 4'h1; + LUT2 com_llm_llm_rx_top_llm_rx_tlp_crc_un3_crc32_com_ok_0_I_54 ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_N_86), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_N_87), + .O(com_llm_llm_rx_top_llm_rx_tlp_crc_N_83) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_un3_crc32_com_ok_0_I_45.INIT = 4'h1; + LUT2 com_llm_llm_rx_top_llm_rx_tlp_crc_un3_crc32_com_ok_0_I_45 ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_N_94), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_N_95), + .O(com_llm_llm_rx_top_llm_rx_tlp_crc_N_91) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_un3_crc32_com_ok_0_I_27.INIT = 4'h1; + LUT2 com_llm_llm_rx_top_llm_rx_tlp_crc_un3_crc32_com_ok_0_I_27 ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_N_110), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_N_111), + .O(com_llm_llm_rx_top_llm_rx_tlp_crc_N_107) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_un3_crc32_com_ok_0_I_18.INIT = 4'h1; + LUT2 com_llm_llm_rx_top_llm_rx_tlp_crc_un3_crc32_com_ok_0_I_18 ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_N_118), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_N_119), + .O(com_llm_llm_rx_top_llm_rx_tlp_crc_N_115) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_un3_crc32_com_ok_0_I_9.INIT = 4'h1; + LUT2 com_llm_llm_rx_top_llm_rx_tlp_crc_un3_crc32_com_ok_0_I_9 ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_N_126), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_N_127), + .O(com_llm_llm_rx_top_llm_rx_tlp_crc_N_123) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d16_new_c16_1_0_29_.INIT = 4'h6; + LUT2 com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d16_new_c16_1_0_29_ ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d64_13__316), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d64_22__48), + .O(com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d16_new_c16_1_0_29__1803) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d16_new_c16_1_0_30_.INIT = 16'h5A66; + LUT4 com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d16_new_c16_1_0_30_ ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d64_14__319), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_13_), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_45_), + .I3(com_llm_llm_rx_top_llm_rx_tlp_crc_start_high_latch_q_308), + .O(com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d16_new_c16_1_0_30__1802) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d16_new_c16_1_0_9_.INIT = 4'h6; + LUT2 com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d16_new_c16_1_0_9_ ( + .I0(G_318_1_0_265), + .I1(N_10554_1), + .O(com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d16_new_c16_1_0_9__1790) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d16_new_c16_1_2_17_.INIT = 16'h6996; + LUT4 com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d16_new_c16_1_2_17_ ( + .I0(N_10453_1), + .I1(N_27376), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d64_1__1761), + .I3(com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d64_30__46), + .O(com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d16_new_c16_1_2_17__1795) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d16_new_c16_1_1_4_.INIT = 4'h6; + LUT2 com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d16_new_c16_1_1_4_ ( + .I0(N_10394), + .I1(N_10496), + .O(com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d16_new_c16_1_4__1797) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d16_new_c16_1_1_19_.INIT = 16'h6996; + LUT4 com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d16_new_c16_1_1_19_ ( + .I0(N_10444), + .I1(N_10462_1), + .I2(N_27404), + .I3(com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d64_24__269), + .O(com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d16_new_c16_1_19__1793) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d16_new_c16_1_1_11_.INIT = 8'h96; + LUT3 com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d16_new_c16_1_1_11_ ( + .I0(G_318_1_0_265), + .I1(N_10462_1), + .I2(N_27488), + .O(com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d16_new_c16_1_11__1800) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d16_new_c16_1_2_31_.INIT = 16'h6996; + LUT4 com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d16_new_c16_1_2_31_ ( + .I0(N_10453_1), + .I1(N_10498_1), + .I2(N_10554_1), + .I3(com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d64_15__287), + .O(com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d16_new_c16_1_2_31__1801) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d16_new_c16_1_2_22_.INIT = 16'h6996; + LUT4_L com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d16_new_c16_1_2_22_ ( + .I0(G_318_1_0_265), + .I1(N_10554), + .I2(N_27488), + .I3(com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d64_6__322), + .LO(com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d16_new_c16_1_2_22__1792) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d16_new_c16_1_1_18_.INIT = 8'h96; + LUT3_L com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d16_new_c16_1_1_18_ ( + .I0(N_10442), + .I1(N_27494), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d64_2__53), + .LO(com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d16_new_c16_1_1_18__1794) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d16_new_c16_1_1_0_24_.INIT = 8'h96; + LUT3_L com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d16_new_c16_1_1_0_24_ ( + .I0(N_10456), + .I1(N_27490), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d64_8__311), + .LO(com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d16_new_c16_1_1_24_) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d16_new_c16_1_2_16_.INIT = 16'h6996; + LUT4_L com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d16_new_c16_1_2_16_ ( + .I0(G_318_1_0_265), + .I1(N_10449), + .I2(N_27488), + .I3(com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d64_16__47), + .LO(com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d16_new_c16_1_2_16__1796) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d16_new_c16_1_0_14_.INIT = 4'h6; + LUT2 com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d16_new_c16_1_0_14_ ( + .I0(N_10509), + .I1(N_27376), + .O(com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d16_new_c16_1_0_14__1798) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d16_new_c16_1_1_5_.INIT = 8'h96; + LUT3_L com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d16_new_c16_1_1_5_ ( + .I0(N_10444), + .I1(N_10449), + .I2(N_10615), + .LO(com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d16_new_c16_1_1_5__1791) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d16_new_c16_1_2_13_.INIT = 16'h6996; + LUT4_L com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d16_new_c16_1_2_13_ ( + .I0(N_10393), + .I1(N_10442_1), + .I2(N_10449), + .I3(N_10512_1), + .LO(com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d16_new_c16_1_2_13__1799) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d16_new_c16_1_9_.INIT = 16'h6996; + LUT4_L com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d16_new_c16_1_9_ ( + .I0(N_10441), + .I1(N_10447), + .I2(N_10455), + .I3(com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d16_new_c16_1_0_9__1790), + .LO(com_llm_llm_rx_top_llm_rx_tlp_crc_new_c16[9]) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d16_new_c16_1_8_.INIT = 16'h9669; + LUT4_L com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d16_new_c16_1_8_ ( + .I0(N_10450), + .I1(N_10456), + .I2(N_10512_1), + .I3(N_27402_i_0), + .LO(com_llm_llm_rx_top_llm_rx_tlp_crc_new_c16[8]) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d16_new_c16_1_7_.INIT = 16'h6996; + LUT4_L com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d16_new_c16_1_7_ ( + .I0(N_10395_1), + .I1(N_10441), + .I2(N_27488), + .I3(com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d16_new_c16_1_19__1793), + .LO(com_llm_llm_rx_top_llm_rx_tlp_crc_new_c16[7]) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d16_new_c16_1_6_.INIT = 16'h6996; + LUT4_L com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d16_new_c16_1_6_ ( + .I0(N_10439), + .I1(N_10455), + .I2(N_10498), + .I3(N_10554), + .LO(com_llm_llm_rx_top_llm_rx_tlp_crc_new_c16[6]) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d16_new_c16_1_5_.INIT = 8'h96; + LUT3_L com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d16_new_c16_1_5_ ( + .I0(N_10395_1), + .I1(N_27488), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d16_new_c16_1_1_5__1791), + .LO(com_llm_llm_rx_top_llm_rx_tlp_crc_new_c16[5]) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d16_new_c16_1_4_.INIT = 16'h9669; + LUT4_L com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d16_new_c16_1_4_ ( + .I0(N_10452), + .I1(N_10462_1), + .I2(N_27402_i_0), + .I3(com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d16_new_c16_1_4__1797), + .LO(com_llm_llm_rx_top_llm_rx_tlp_crc_new_c16[4]) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d16_new_c16_1_2_.INIT = 16'h6996; + LUT4_L com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d16_new_c16_1_2_ ( + .I0(N_10438), + .I1(N_10443), + .I2(N_10495), + .I3(N_27376), + .LO(com_llm_llm_rx_top_llm_rx_tlp_crc_new_c16[2]) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d16_new_c16_1_1_.INIT = 8'h96; + LUT3_L com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d16_new_c16_1_1_ ( + .I0(G_318_1_0_265), + .I1(N_10445), + .I2(N_10495), + .LO(com_llm_llm_rx_top_llm_rx_tlp_crc_new_c16[1]) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d16_new_c16_1_0_.INIT = 16'h6996; + LUT4_L com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d16_new_c16_1_0_ ( + .I0(N_10395), + .I1(N_10453), + .I2(N_27488), + .I3(com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d64_22__48), + .LO(com_llm_llm_rx_top_llm_rx_tlp_crc_new_c16[0]) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d16_new_c16_1_24_.INIT = 8'h96; + LUT3_L com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d16_new_c16_1_24_ ( + .I0(N_10438), + .I1(N_27376), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d16_new_c16_1_1_24_), + .LO(com_llm_llm_rx_top_llm_rx_tlp_crc_new_c16[24]) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d16_new_c16_1_23_.INIT = 8'h96; + LUT3_L com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d16_new_c16_1_23_ ( + .I0(N_10462_1), + .I1(N_10495), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d64_7__310), + .LO(com_llm_llm_rx_top_llm_rx_tlp_crc_new_c16[23]) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d16_new_c16_1_22_.INIT = 16'h6996; + LUT4_L com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d16_new_c16_1_22_ ( + .I0(N_10453_1), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d64_16__47), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d64_30__46), + .I3(com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d16_new_c16_1_2_22__1792), + .LO(com_llm_llm_rx_top_llm_rx_tlp_crc_new_c16[22]) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d16_new_c16_1_21_.INIT = 16'h6996; + LUT4_L com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d16_new_c16_1_21_ ( + .I0(N_10447), + .I1(N_10461_1), + .I2(N_10498_1), + .I3(com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d64_5__317), + .LO(com_llm_llm_rx_top_llm_rx_tlp_crc_new_c16[21]) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d16_new_c16_1_20_.INIT = 4'h6; + LUT2_L com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d16_new_c16_1_20_ ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d64_4__1760), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d16_new_c16_1_20__1804), + .LO(com_llm_llm_rx_top_llm_rx_tlp_crc_new_c16[20]) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d16_new_c16_1_19_.INIT = 8'h96; + LUT3_L com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d16_new_c16_1_19_ ( + .I0(N_10554_1), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d64_3__52), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d16_new_c16_1_19__1793), + .LO(com_llm_llm_rx_top_llm_rx_tlp_crc_new_c16[19]) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d16_new_c16_1_18_.INIT = 8'h96; + LUT3_L com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d16_new_c16_1_18_ ( + .I0(G_355_0_284), + .I1(N_10438), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d16_new_c16_1_1_18__1794), + .LO(com_llm_llm_rx_top_llm_rx_tlp_crc_new_c16[18]) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d16_new_c16_1_17_.INIT = 16'h6996; + LUT4_L com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d16_new_c16_1_17_ ( + .I0(N_10393), + .I1(N_10449), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d64_22__48), + .I3(com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d16_new_c16_1_2_17__1795), + .LO(com_llm_llm_rx_top_llm_rx_tlp_crc_new_c16[17]) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d16_new_c16_1_16_.INIT = 16'h6996; + LUT4_L com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d16_new_c16_1_16_ ( + .I0(N_10450), + .I1(N_27497), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d64_0__324), + .I3(com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d16_new_c16_1_2_16__1796), + .LO(com_llm_llm_rx_top_llm_rx_tlp_crc_new_c16[16]) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d16_new_c16_1_15_.INIT = 16'h6996; + LUT4_L com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d16_new_c16_1_15_ ( + .I0(N_10444), + .I1(N_10462_1), + .I2(N_10498_1), + .I3(com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d16_new_c16_1_20__1804), + .LO(com_llm_llm_rx_top_llm_rx_tlp_crc_new_c16[15]) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d16_new_c16_1_14_.INIT = 8'h96; + LUT3_L com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d16_new_c16_1_14_ ( + .I0(N_10439), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d16_new_c16_1_0_14__1798), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d16_new_c16_1_4__1797), + .LO(com_llm_llm_rx_top_llm_rx_tlp_crc_new_c16[14]) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d16_new_c16_1_13_.INIT = 8'h96; + LUT3_L com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d16_new_c16_1_13_ ( + .I0(G_355_0_284), + .I1(N_10438), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d16_new_c16_1_2_13__1799), + .LO(com_llm_llm_rx_top_llm_rx_tlp_crc_new_c16[13]) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d16_new_c16_1_12_.INIT = 16'h6996; + LUT4_L com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d16_new_c16_1_12_ ( + .I0(N_10441), + .I1(N_10448), + .I2(N_10615), + .I3(com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d16_new_c16_1_11__1800), + .LO(com_llm_llm_rx_top_llm_rx_tlp_crc_new_c16[12]) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d16_new_c16_1_11_.INIT = 16'h6996; + LUT4_L com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d16_new_c16_1_11_ ( + .I0(N_10455), + .I1(N_10512_1), + .I2(N_27398_i_0), + .I3(com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d16_new_c16_1_11__1800), + .LO(com_llm_llm_rx_top_llm_rx_tlp_crc_new_c16[11]) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d16_new_c16_1_10_.INIT = 16'h6996; + LUT4_L com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d16_new_c16_1_10_ ( + .I0(N_10441), + .I1(N_10447_1), + .I2(N_10512), + .I3(N_27398_i_0), + .LO(com_llm_llm_rx_top_llm_rx_tlp_crc_new_c16[10]) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d16_new_c16_1_31_.INIT = 16'h6996; + LUT4_L com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d16_new_c16_1_31_ ( + .I0(N_10462_1), + .I1(N_27404), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d64_24__269), + .I3(com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d16_new_c16_1_2_31__1801), + .LO(com_llm_llm_rx_top_llm_rx_tlp_crc_new_c16[31]) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d16_new_c16_1_30_.INIT = 16'h6996; + LUT4_L com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d16_new_c16_1_30_ ( + .I0(N_10439), + .I1(N_10496_1), + .I2(N_10555), + .I3(com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d16_new_c16_1_0_30__1802), + .LO(com_llm_llm_rx_top_llm_rx_tlp_crc_new_c16[30]) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d16_new_c16_1_29_.INIT = 16'h6996; + LUT4_L com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d16_new_c16_1_29_ ( + .I0(N_10444), + .I1(N_10447), + .I2(N_27494), + .I3(com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d16_new_c16_1_0_29__1803), + .LO(com_llm_llm_rx_top_llm_rx_tlp_crc_new_c16[29]) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d16_new_c16_1_28_.INIT = 16'h6996; + LUT4_L com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d16_new_c16_1_28_ ( + .I0(G_318_1_0_265), + .I1(N_10498), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d64_12__321), + .I3(com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d64_24__269), + .LO(com_llm_llm_rx_top_llm_rx_tlp_crc_new_c16[28]) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d16_new_c16_1_27_.INIT = 16'h6996; + LUT4_L com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d16_new_c16_1_27_ ( + .I0(N_10445), + .I1(N_10455), + .I2(N_10498_1), + .I3(com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d64_11__318), + .LO(com_llm_llm_rx_top_llm_rx_tlp_crc_new_c16[27]) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d16_new_c16_1_26_.INIT = 16'h6996; + LUT4_L com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d16_new_c16_1_26_ ( + .I0(N_10395), + .I1(N_10496), + .I2(N_10512), + .I3(com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d64_10__1759), + .LO(com_llm_llm_rx_top_llm_rx_tlp_crc_new_c16[26]) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d16_new_c16_1_25_.INIT = 16'h6996; + LUT4_L com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d16_new_c16_1_25_ ( + .I0(N_10443), + .I1(N_10509), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d64_9__320), + .I3(com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d64_18__45), + .LO(com_llm_llm_rx_top_llm_rx_tlp_crc_new_c16[25]) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d16_new_c16_1_1_0_3_.INIT = 8'h69; + LUT3 com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d16_new_c16_1_1_0_3_ ( + .I0(N_10453_1), + .I1(N_10456_1), + .I2(N_10555), + .O(com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d16_new_c16_1_1_0[3]) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d16_new_c16_1_1_20_.INIT = 8'h96; + LUT3 com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d16_new_c16_1_1_20_ ( + .I0(N_10450), + .I1(N_10453_1), + .I2(G_318_1_0_265), + .O(com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d16_new_c16_1_20__1804) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d16_new_c16_1_3_.INIT = 16'h9669; + LUT4_L com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d16_new_c16_1_3_ ( + .I0(N_10438), + .I1(N_10442), + .I2(N_10452), + .I3(com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d16_new_c16_1_1_0[3]), + .LO(com_llm_llm_rx_top_llm_rx_tlp_crc_new_c16[3]) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_1_3_.INIT = 4'h6; + LUT2 com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_1_3_ ( + .I0(N_27418), + .I1(N_27526), + .O(com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_3__1821) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_0_13_.INIT = 4'h6; + LUT2 com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_0_13_ ( + .I0(N_27421), + .I1(N_27523), + .O(com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_0_13__1809) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_0_2_.INIT = 4'h6; + LUT2 com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_0_2_ ( + .I0(N_27412), + .I1(N_27416), + .O(com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_0_2__1832) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_1_23_.INIT = 8'h96; + LUT3 com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_1_23_ ( + .I0(N_27563), + .I1(N_27677), + .I2(N_27679), + .O(com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_1_23__1822) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_14_32043.INIT = 4'h6; + LUT2 com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_14_32043 ( + .I0(N_126_1), + .I1(N_27415), + .O(com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_14_32043_1820) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_1_1_1_.INIT = 8'h96; + LUT3 com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_1_1_1_ ( + .I0(N_27405), + .I1(N_27428), + .I2(N_27564), + .O(com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_1_1[1]) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_3_1_2_.INIT = 16'h9996; + LUT4_L com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_3_1_2_ ( + .I0(N_106_1), + .I1(N_27421), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d64_5__317), + .I3(com_llm_llm_rx_top_llm_rx_tlp_crc_initial_64_51), + .LO(com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_3_1[2]) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_1_21_.INIT = 16'h6996; + LUT4 com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_1_21_ ( + .I0(N_27414), + .I1(N_27426), + .I2(N_27502), + .I3(N_27507), + .O(com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_1_21__1815) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_0_12_.INIT = 4'h6; + LUT2 com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_0_12_ ( + .I0(N_92_1), + .I1(N_27409), + .O(com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_0_12__1816) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_1_29_.INIT = 8'h96; + LUT3 com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_1_29_ ( + .I0(N_27372), + .I1(N_27374), + .I2(N_27524), + .O(com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_1_29__1818) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_1_15_.INIT = 4'h6; + LUT2_L com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_1_15_ ( + .I0(N_57), + .I1(N_10340), + .LO(com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_15__1899) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_1_24_.INIT = 4'h6; + LUT2 com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_1_24_ ( + .I0(N_64), + .I1(N_27374), + .O(com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_24__1817) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_1_22_.INIT = 4'h9; + LUT2 com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_1_22_ ( + .I0(N_92), + .I1(N_27658), + .O(com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_22__1828) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_1_18_.INIT = 4'h6; + LUT2 com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_1_18_ ( + .I0(N_74), + .I1(N_27428), + .O(com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_18__1872) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_1_5_.INIT = 4'h6; + LUT2 com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_1_5_ ( + .I0(N_88), + .I1(N_27408), + .O(com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_5__1840) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_3_2_.INIT = 16'h6996; + LUT4 com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_3_2_ ( + .I0(N_10484_1), + .I1(N_27413), + .I2(N_27526), + .I3(com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_3_1[2]), + .O(com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_3[2]) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_2_2_.INIT = 16'h6996; + LUT4 com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_2_2_ ( + .I0(N_58_1), + .I1(N_27405), + .I2(N_27407), + .I3(N_27419), + .O(com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_2_2_) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_1_26_.INIT = 16'h6996; + LUT4 com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_1_26_ ( + .I0(N_53), + .I1(N_10582_1), + .I2(N_27414), + .I3(N_27435), + .O(com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_26__1903) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_1_2_12_.INIT = 8'h96; + LUT3 com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_1_2_12_ ( + .I0(N_26_1), + .I1(N_62), + .I2(N_87_1), + .O(com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_1_2[12]) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_2_17_.INIT = 16'h6996; + LUT4 com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_2_17_ ( + .I0(N_141_1), + .I1(N_10562), + .I2(N_27427), + .I3(N_27504), + .O(com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_2_17__1805) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_4_17_.INIT = 4'h6; + LUT2_L com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_4_17_ ( + .I0(N_15), + .I1(N_62), + .LO(com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_4_17__1806) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_2_16_.INIT = 16'h9669; + LUT4 com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_2_16_ ( + .I0(N_27416), + .I1(N_27422), + .I2(N_27424), + .I3(N_27618), + .O(com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_2_16__1824) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_3_16_.INIT = 4'h6; + LUT2_L com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_3_16_ ( + .I0(N_61), + .I1(N_79), + .LO(com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_3_16__1823) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_0_24_.INIT = 8'h96; + LUT3 com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_0_24_ ( + .I0(N_10360), + .I1(N_10582_1), + .I2(N_27420), + .O(com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_0_24__1807) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_3_25_.INIT = 4'h6; + LUT2 com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_3_25_ ( + .I0(N_140), + .I1(N_10343), + .O(com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_3_25__1863) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_1_19_.INIT = 16'h9669; + LUT4 com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_1_19_ ( + .I0(N_41_1), + .I1(N_27415), + .I2(N_27424), + .I3(N_27664), + .O(com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_1_19__1877) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_2_19_.INIT = 4'h6; + LUT2 com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_2_19_ ( + .I0(N_60), + .I1(N_10360), + .O(com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_2_19__1876) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_1_11_.INIT = 8'h96; + LUT3 com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_1_11_ ( + .I0(N_92_1), + .I1(N_126_1), + .I2(N_10367), + .O(com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_1_11__1825) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_3_11_.INIT = 16'h6996; + LUT4 com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_3_11_ ( + .I0(N_90_1), + .I1(N_91), + .I2(N_27419), + .I3(N_27499), + .O(com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_3_11__1837) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_2_20_.INIT = 16'h6996; + LUT4 com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_2_20_ ( + .I0(N_51), + .I1(N_27420), + .I2(N_27501), + .I3(N_27524), + .O(com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_2_20__1874) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_3_13_.INIT = 16'h9669; + LUT4_L com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_3_13_ ( + .I0(N_54), + .I1(N_27419), + .I2(N_27503), + .I3(N_27665), + .LO(com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_3_13__1808) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_3_23_.INIT = 16'h6996; + LUT4_L com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_3_23_ ( + .I0(N_22), + .I1(N_10484_1), + .I2(N_27413), + .I3(N_27526), + .LO(com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_3_23__1810) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_1_0_3_.INIT = 16'h6996; + LUT4 com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_1_0_3_ ( + .I0(N_35_1), + .I1(N_159_1), + .I2(N_27523), + .I3(com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_3__1821), + .O(com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_1_3__1827) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_2_3_.INIT = 8'h69; + LUT3_L com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_2_3_ ( + .I0(N_59), + .I1(N_90_1), + .I2(N_27677), + .LO(com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_2_3__1826) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_3_3_.INIT = 8'h96; + LUT3 com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_3_3_ ( + .I0(N_26_1), + .I1(N_87_1), + .I2(N_10342), + .O(com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_3_3__1851) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_1_7_.INIT = 16'h9669; + LUT4_L com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_1_7_ ( + .I0(N_61), + .I1(N_27414), + .I2(N_27435), + .I3(N_27661), + .LO(com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_1_7__1829) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_2_1_.INIT = 16'h6996; + LUT4_L com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_2_1_ ( + .I0(N_74), + .I1(N_90_1), + .I2(N_27419), + .I3(N_27499), + .LO(com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_2_1__1811) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_1_27_.INIT = 8'h96; + LUT3_L com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_1_27_ ( + .I0(N_10_1), + .I1(N_88), + .I2(N_10347_1), + .LO(com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_1_27__1812) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_2_9_.INIT = 8'h96; + LUT3 com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_2_9_ ( + .I0(N_51_1), + .I1(N_124), + .I2(N_10574_1), + .O(com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_2_9__1831) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_3_9_.INIT = 8'h96; + LUT3 com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_3_9_ ( + .I0(N_59), + .I1(N_10559_1), + .I2(N_27416), + .O(com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_3_9__1830) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_2_0_.INIT = 4'h6; + LUT2_L com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_2_0_ ( + .I0(N_54), + .I1(N_112), + .LO(com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_2_0__1813) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_3_0_.INIT = 4'h6; + LUT2 com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_3_0_ ( + .I0(N_57), + .I1(N_10353), + .O(com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_3_0__1860) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_2_2_2_.INIT = 8'h69; + LUT3 com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_2_2_2_ ( + .I0(N_90_1), + .I1(N_112), + .I2(N_27677), + .O(com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_2_2__1854) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_2_30_.INIT = 4'h6; + LUT2_L com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_2_30_ ( + .I0(N_40), + .I1(N_124), + .LO(com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_2_30__1814) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_1_10_.INIT = 16'h6996; + LUT4 com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_1_10_ ( + .I0(N_19_1), + .I1(N_27405), + .I2(N_27410), + .I3(N_27499), + .O(com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_1_10__1897) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_2_5_.INIT = 16'h6996; + LUT4 com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_2_5_ ( + .I0(N_58_1), + .I1(N_140_1), + .I2(N_27414), + .I3(N_27423), + .O(com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_2_5__1847) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_4_29_.INIT = 16'h6996; + LUT4_L com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_4_29_ ( + .I0(N_26_1), + .I1(N_159_1), + .I2(N_10559_1), + .I3(N_27416), + .LO(com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_4_29__1819) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_1_8_.INIT = 8'h69; + LUT3 com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_1_8_ ( + .I0(N_159_1), + .I1(N_27405), + .I2(N_27618), + .O(com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_1_8__1833) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_1_0_6_.INIT = 16'h6996; + LUT4 com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_1_0_6_ ( + .I0(N_51), + .I1(N_27406), + .I2(N_27407), + .I3(N_27410), + .O(com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_1_6__1834) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_2_0_6_.INIT = 4'h6; + LUT2 com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_2_0_6_ ( + .I0(N_35), + .I1(N_125), + .O(com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_2_6_) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_0_18_.INIT = 4'h6; + LUT2 com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_0_18_ ( + .I0(N_10527), + .I1(N_27503), + .O(com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_0_18__1835) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_1_2_.INIT = 4'h6; + LUT2 com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_1_2_ ( + .I0(N_3), + .I1(N_10478), + .O(com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_2__1852) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_1_12_.INIT = 16'h9669; + LUT4 com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_1_12_ ( + .I0(N_10343), + .I1(N_27435), + .I2(N_27661), + .I3(com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_1_2[12]), + .O(com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_12__1886) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_5_17_.INIT = 16'h9669; + LUT4_L com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_5_17_ ( + .I0(G_431_1_285), + .I1(N_27526), + .I2(N_27677), + .I3(com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_2_17__1805), + .LO(com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_5_17__1880) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_6_17_.INIT = 16'h6996; + LUT4 com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_6_17_ ( + .I0(N_26_1), + .I1(N_34), + .I2(N_159_1), + .I3(com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_4_17__1806), + .O(com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_6_17__1879) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_4_24_.INIT = 16'h9669; + LUT4 com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_4_24_ ( + .I0(G_431_1_285), + .I1(N_27526), + .I2(N_27677), + .I3(com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_0_24__1807), + .O(com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_4_24__1866) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_5_24_.INIT = 16'h6996; + LUT4 com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_5_24_ ( + .I0(N_52), + .I1(N_58), + .I2(N_107), + .I3(N_10340), + .O(com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_5_24__1865) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_6_24_.INIT = 16'h6996; + LUT4_L com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_6_24_ ( + .I0(N_39_1), + .I1(N_54), + .I2(N_140_1), + .I3(com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_24__1817), + .LO(com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_6_24__1864) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_5_25_.INIT = 16'h6996; + LUT4 com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_5_25_ ( + .I0(N_14), + .I1(N_55), + .I2(N_59), + .I3(N_75), + .O(com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_5_25__1862) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_5_19_.INIT = 16'h6996; + LUT4_L com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_5_19_ ( + .I0(N_51_1), + .I1(N_10341), + .I2(N_10489), + .I3(N_10574_1), + .LO(com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_5_19__1875) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_5_13_.INIT = 16'h6996; + LUT4_L com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_5_13_ ( + .I0(N_66), + .I1(N_27416), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_0_13__1809), + .I3(com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_3_13__1808), + .LO(com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_5_13__1885) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_6_13_.INIT = 16'h6996; + LUT4 com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_6_13_ ( + .I0(N_35), + .I1(N_63), + .I2(N_10347), + .I3(N_10354), + .O(com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_6_13__1884) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_5_23_.INIT = 16'h9669; + LUT4 com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_5_23_ ( + .I0(N_27416), + .I1(N_27664), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_1_1[1]), + .I3(com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_3_23__1810), + .O(com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_5_23__1868) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_3_22_.INIT = 16'h9669; + LUT4 com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_3_22_ ( + .I0(N_57), + .I1(N_10527), + .I2(N_27430), + .I3(N_27677), + .O(com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_3_22__1871) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_4_22_.INIT = 8'h96; + LUT3 com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_4_22_ ( + .I0(N_52), + .I1(N_125), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_3[2]), + .O(com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_4_22__1870) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_3_4_.INIT = 8'h96; + LUT3 com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_3_4_ ( + .I0(N_107), + .I1(N_10353), + .I2(N_27412), + .O(com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_3_4__1849) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_4_4_.INIT = 16'h6996; + LUT4 com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_4_4_ ( + .I0(N_22), + .I1(N_34), + .I2(N_113), + .I3(N_10345), + .O(com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_4_4__1848) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_4_7_.INIT = 8'h96; + LUT3 com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_4_7_ ( + .I0(N_140), + .I1(N_10341), + .I2(N_27401_i_0), + .O(com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_4_7__1844) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_3_1_.INIT = 16'h9669; + LUT4 com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_3_1_ ( + .I0(N_10341), + .I1(N_27416), + .I2(N_27664), + .I3(com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_1_1[1]), + .O(com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_3_1__1857) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_4_1_.INIT = 16'h9669; + LUT4 com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_4_1_ ( + .I0(N_34), + .I1(N_27372), + .I2(N_27655), + .I3(com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_2_1__1811), + .O(com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_4_1__1856) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_5_1_.INIT = 4'h6; + LUT2_L com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_5_1_ ( + .I0(N_10502_1), + .I1(N_10580), + .LO(com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_5_1__1855) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_3_27_.INIT = 8'h69; + LUT3_L com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_3_27_ ( + .I0(N_10367), + .I1(N_27671), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_1_27__1812), + .LO(com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_3_27__1896) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_4_27_.INIT = 16'h6996; + LUT4 com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_4_27_ ( + .I0(N_58), + .I1(N_61), + .I2(N_75), + .I3(N_27425), + .O(com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_4_27__1895) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_4_9_.INIT = 16'h9669; + LUT4 com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_4_9_ ( + .I0(N_63), + .I1(N_92_1), + .I2(N_106_1), + .I3(N_27680), + .O(com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_4_9__1839) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_4_0_.INIT = 16'h9996; + LUT4 com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_4_0_ ( + .I0(N_23), + .I1(N_10500_1), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d64_5__317), + .I3(com_llm_llm_rx_top_llm_rx_tlp_crc_initial_64_51), + .O(com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_4_0__1859) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_5_0_.INIT = 16'h6996; + LUT4_L com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_5_0_ ( + .I0(N_87), + .I1(N_159_1), + .I2(N_27523), + .I3(com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_2_0__1813), + .LO(com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_5_0__1858) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_3_30_.INIT = 16'h9669; + LUT4_L com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_3_30_ ( + .I0(N_12), + .I1(N_27501), + .I2(N_27665), + .I3(com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_2_30__1814), + .LO(com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_3_30__1890) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_3_21_.INIT = 16'h6996; + LUT4 com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_3_21_ ( + .I0(N_40), + .I1(N_10582_1), + .I2(N_27420), + .I3(com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_1_21__1815), + .O(com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_3_21__1873) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_2_12_.INIT = 16'h6996; + LUT4 com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_2_12_ ( + .I0(N_89), + .I1(N_10344), + .I2(N_10582_1), + .I3(com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_0_12__1816), + .O(com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_2_12__1888) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_3_12_.INIT = 8'h96; + LUT3_L com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_3_12_ ( + .I0(N_10351), + .I1(N_27399_i_0), + .I2(N_27411), + .LO(com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_3_12__1887) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_6_28_.INIT = 8'h96; + LUT3 com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_6_28_ ( + .I0(N_37), + .I1(N_10351), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_24__1817), + .O(com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_6_28__1894) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_6_5_.INIT = 16'h6996; + LUT4 com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_6_5_ ( + .I0(N_30), + .I1(N_51), + .I2(N_92), + .I3(N_160), + .O(com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_6_5__1846) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_5_29_.INIT = 8'h96; + LUT3 com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_5_29_ ( + .I0(N_53), + .I1(N_160_1), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_1_29__1818), + .O(com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_5_29__1893) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_6_29_.INIT = 8'h96; + LUT3 com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_6_29_ ( + .I0(N_10346), + .I1(N_10354), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_4_29__1819), + .O(com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_6_29__1892) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_3_14_.INIT = 16'h9669; + LUT4 com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_3_14_ ( + .I0(N_66), + .I1(N_87), + .I2(N_27619), + .I3(com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_14_32043_1820), + .O(com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_3_14__1883) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_4_14_.INIT = 8'h96; + LUT3_L com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_4_14_ ( + .I0(N_15), + .I1(N_113), + .I2(N_10480_1), + .LO(com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_4_14__1882) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_2_26_.INIT = 16'h6996; + LUT4 com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_2_26_ ( + .I0(N_58), + .I1(N_108), + .I2(N_10484), + .I3(N_27503), + .O(com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_2_26__1861) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_2_31_.INIT = 16'h9669; + LUT4 com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_2_31_ ( + .I0(N_42), + .I1(N_79), + .I2(N_27677), + .I3(com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_3__1821), + .O(com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_2_31__1889) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_7_25_.INIT = 16'h9669; + LUT4_L com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_7_25_ ( + .I0(N_91), + .I1(N_10562), + .I2(N_27399_i_0), + .I3(N_27619), + .LO(com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_7[25]) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_6_23_.INIT = 16'h6996; + LUT4_L com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_6_23_ ( + .I0(N_89), + .I1(N_124_1), + .I2(N_10489), + .I3(com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_1_23__1822), + .LO(com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_6_23__1867) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_1_6_.INIT = 8'h96; + LUT3 com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_1_6_ ( + .I0(N_41_1), + .I1(N_92_1), + .I2(N_10499), + .O(com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_6__1891) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_2_15_.INIT = 16'h9669; + LUT4 com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_2_15_ ( + .I0(N_10344), + .I1(N_10477), + .I2(N_10502_1), + .I3(N_27680), + .O(com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_2_15_) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_6_16_.INIT = 16'h6996; + LUT4 com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_6_16_ ( + .I0(N_39_1), + .I1(N_140_1), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_2_16__1824), + .I3(com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_3_16__1823), + .O(com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_6_16__1881) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_6_11_.INIT = 16'h6996; + LUT4_L com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_6_11_ ( + .I0(N_23), + .I1(N_38), + .I2(N_10481), + .I3(com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_1_11__1825), + .LO(com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_6_11__1836) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_6_3_.INIT = 16'h6996; + LUT4 com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_6_3_ ( + .I0(N_12), + .I1(N_22), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_1_3__1827), + .I3(com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_2_3__1826), + .O(com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_6_3__1850) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_8_22_.INIT = 16'h6996; + LUT4_L com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_8_22_ ( + .I0(N_10483), + .I1(N_10550), + .I2(N_27400_i_0), + .I3(com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_22__1828), + .LO(com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_8_22__1869) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_5_7_.INIT = 16'h6996; + LUT4 com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_5_7_ ( + .I0(N_35), + .I1(N_10354), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_1_7__1829), + .I3(com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_2_2_), + .O(com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_5_7__1843) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_8_9_.INIT = 16'h6996; + LUT4_L com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_8_9_ ( + .I0(N_126), + .I1(N_27400_i_0), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_2_9__1831), + .I3(com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_3_9__1830), + .LO(com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_8_9__1838) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_5_2_.INIT = 16'h6996; + LUT4_L com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_5_2_ ( + .I0(N_36), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_0_2__1832), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_2_2_), + .I3(com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_3[2]), + .LO(com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_5_2__1853) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_9_5_.INIT = 16'h6996; + LUT4_L com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_9_5_ ( + .I0(N_10344), + .I1(N_10482), + .I2(N_10582_1), + .I3(com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_5__1840), + .LO(com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_9[5]) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_4_8_.INIT = 16'h6996; + LUT4 com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_4_8_ ( + .I0(N_35), + .I1(N_60), + .I2(N_10342), + .I3(com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_1_8__1833), + .O(com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_4_8__1842) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_6_8_.INIT = 4'h6; + LUT2_L com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_6_8_ ( + .I0(N_10488), + .I1(N_10602), + .LO(com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_6_8__1841) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_5_6_.INIT = 16'h6996; + LUT4 com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_5_6_ ( + .I0(N_10484), + .I1(N_10610), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_1_6__1834), + .I3(com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_2_6_), + .O(com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_5_6__1845) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_3_18_.INIT = 16'h6996; + LUT4_L com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_3_18_ ( + .I0(N_54), + .I1(N_78), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_0_18__1835), + .I3(com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_18__1872), + .LO(com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_3_18__1878) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_11_.INIT = 16'h6996; + LUT4_L com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_11_ ( + .I0(N_10500), + .I1(N_10551), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_3_11__1837), + .I3(com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_6_11__1836), + .LO(com_llm_llm_rx_top_llm_rx_tlp_crc_new_c64[11]) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_9_.INIT = 16'h6996; + LUT4_L com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_9_ ( + .I0(N_10511), + .I1(N_10569), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_4_9__1839), + .I3(com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_8_9__1838), + .LO(com_llm_llm_rx_top_llm_rx_tlp_crc_new_c64[9]) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_8_.INIT = 16'h6996; + LUT4_L com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_8_ ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_4_8__1842), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_6_8__1841), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_2__1852), + .I3(com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_5__1840), + .LO(com_llm_llm_rx_top_llm_rx_tlp_crc_new_c64[8]) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_7_.INIT = 16'h6996; + LUT4_L com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_7_ ( + .I0(N_10488), + .I1(N_10510), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_4_7__1844), + .I3(com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_5_7__1843), + .LO(com_llm_llm_rx_top_llm_rx_tlp_crc_new_c64[7]) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_6_.INIT = 16'h6996; + LUT4_L com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_6_ ( + .I0(N_141_1), + .I1(N_27401_i_0), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_5_6__1845), + .I3(com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_6__1891), + .LO(com_llm_llm_rx_top_llm_rx_tlp_crc_new_c64[6]) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_5_.INIT = 16'h6996; + LUT4_L com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_5_ ( + .I0(N_42), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_2_5__1847), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_6_5__1846), + .I3(com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_9[5]), + .LO(com_llm_llm_rx_top_llm_rx_tlp_crc_new_c64[5]) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_4_.INIT = 16'h6996; + LUT4_L com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_4_ ( + .I0(N_10479), + .I1(N_10510), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_3_4__1849), + .I3(com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_4_4__1848), + .LO(com_llm_llm_rx_top_llm_rx_tlp_crc_new_c64[4]) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_3_.INIT = 16'h6996; + LUT4_L com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_3_ ( + .I0(N_10574), + .I1(N_27401_i_0), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_3_3__1851), + .I3(com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_6_3__1850), + .LO(com_llm_llm_rx_top_llm_rx_tlp_crc_new_c64[3]) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_2_.INIT = 16'h6996; + LUT4_L com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_2_ ( + .I0(N_10551), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_2_2__1854), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_5_2__1853), + .I3(com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_2__1852), + .LO(com_llm_llm_rx_top_llm_rx_tlp_crc_new_c64[2]) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_1_.INIT = 16'h6996; + LUT4_L com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_1_ ( + .I0(N_10602), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_3_1__1857), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_4_1__1856), + .I3(com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_5_1__1855), + .LO(com_llm_llm_rx_top_llm_rx_tlp_crc_new_c64[1]) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_0_.INIT = 16'h6996; + LUT4_L com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_0_ ( + .I0(N_10487), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_3_0__1860), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_4_0__1859), + .I3(com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_5_0__1858), + .LO(com_llm_llm_rx_top_llm_rx_tlp_crc_new_c64[0]) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_26_.INIT = 16'h6996; + LUT4_L com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_26_ ( + .I0(N_10480), + .I1(N_10505), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_2_26__1861), + .I3(com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_3_26__1902), + .LO(com_llm_llm_rx_top_llm_rx_tlp_crc_new_c64[26]) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_25_.INIT = 16'h6996; + LUT4_L com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_25_ ( + .I0(N_10550), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_3_25__1863), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_5_25__1862), + .I3(com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_7[25]), + .LO(com_llm_llm_rx_top_llm_rx_tlp_crc_new_c64[25]) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_24_.INIT = 16'h6996; + LUT4_L com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_24_ ( + .I0(N_10580), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_4_24__1866), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_5_24__1865), + .I3(com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_6_24__1864), + .LO(com_llm_llm_rx_top_llm_rx_tlp_crc_new_c64[24]) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_23_.INIT = 16'h6996; + LUT4_L com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_23_ ( + .I0(N_10499), + .I1(N_10565), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_5_23__1868), + .I3(com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_6_23__1867), + .LO(com_llm_llm_rx_top_llm_rx_tlp_crc_new_c64[23]) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_22_.INIT = 8'h96; + LUT3_L com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_22_ ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_3_22__1871), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_4_22__1870), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_8_22__1869), + .LO(com_llm_llm_rx_top_llm_rx_tlp_crc_new_c64[22]) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_21_.INIT = 16'h6996; + LUT4_L com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_21_ ( + .I0(N_10610), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_3_21__1873), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_12__1886), + .I3(com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_18__1872), + .LO(com_llm_llm_rx_top_llm_rx_tlp_crc_new_c64[21]) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_20_.INIT = 16'h6996; + LUT4_L com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_20_ ( + .I0(N_15), + .I1(N_10569), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_2_20__1874), + .I3(com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_4_20__1901), + .LO(com_llm_llm_rx_top_llm_rx_tlp_crc_new_c64[20]) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_19_.INIT = 16'h6996; + LUT4_L com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_19_ ( + .I0(N_10481), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_1_19__1877), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_2_19__1876), + .I3(com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_5_19__1875), + .LO(com_llm_llm_rx_top_llm_rx_tlp_crc_new_c64[19]) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_18_.INIT = 8'h96; + LUT3_L com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_18_ ( + .I0(N_10482), + .I1(N_10514), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_3_18__1878), + .LO(com_llm_llm_rx_top_llm_rx_tlp_crc_new_c64[18]) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_17_.INIT = 16'h6996; + LUT4_L com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_17_ ( + .I0(N_3), + .I1(N_27523), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_5_17__1880), + .I3(com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_6_17__1879), + .LO(com_llm_llm_rx_top_llm_rx_tlp_crc_new_c64[17]) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_16_.INIT = 16'h6996; + LUT4_L com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_16_ ( + .I0(N_40), + .I1(N_10353), + .I2(N_10500), + .I3(com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_6_16__1881), + .LO(com_llm_llm_rx_top_llm_rx_tlp_crc_new_c64[16]) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_15_.INIT = 16'h6996; + LUT4_L com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_15_ ( + .I0(N_141_1), + .I1(N_27401_i_0), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_4_15__1898), + .I3(com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_2_15_), + .LO(com_llm_llm_rx_top_llm_rx_tlp_crc_new_c64[15]) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_14_.INIT = 16'h6996; + LUT4_L com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_14_ ( + .I0(N_10511), + .I1(N_27391_i_0), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_3_14__1883), + .I3(com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_4_14__1882), + .LO(com_llm_llm_rx_top_llm_rx_tlp_crc_new_c64[14]) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_13_.INIT = 16'h6996; + LUT4_L com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_13_ ( + .I0(N_10483), + .I1(N_10499), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_5_13__1885), + .I3(com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_6_13__1884), + .LO(com_llm_llm_rx_top_llm_rx_tlp_crc_new_c64[13]) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_12_.INIT = 16'h6996; + LUT4_L com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_12_ ( + .I0(N_10479), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_2_12__1888), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_3_12__1887), + .I3(com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_12__1886), + .LO(com_llm_llm_rx_top_llm_rx_tlp_crc_new_c64[12]) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_31_.INIT = 16'h6996; + LUT4_L com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_31_ ( + .I0(N_126), + .I1(N_10505), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_2_31__1889), + .I3(com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_2_15_), + .LO(com_llm_llm_rx_top_llm_rx_tlp_crc_new_c64[31]) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_30_.INIT = 16'h6996; + LUT4_L com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_30_ ( + .I0(N_10616), + .I1(N_27391_i_0), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_3_30__1890), + .I3(com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_26__1903), + .LO(com_llm_llm_rx_top_llm_rx_tlp_crc_new_c64[30]) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_29_.INIT = 16'h6996; + LUT4_L com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_29_ ( + .I0(N_10483), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_5_29__1893), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_6_29__1892), + .I3(com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_6__1891), + .LO(com_llm_llm_rx_top_llm_rx_tlp_crc_new_c64[29]) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_28_.INIT = 16'h6996; + LUT4_L com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_28_ ( + .I0(N_10480), + .I1(N_10617), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_5_28__1900), + .I3(com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_6_28__1894), + .LO(com_llm_llm_rx_top_llm_rx_tlp_crc_new_c64[28]) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_27_.INIT = 16'h6996; + LUT4_L com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_27_ ( + .I0(N_10487), + .I1(N_10616), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_3_27__1896), + .I3(com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_4_27__1895), + .LO(com_llm_llm_rx_top_llm_rx_tlp_crc_new_c64[27]) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_1_0_10_.INIT = 16'h6996; + LUT4 com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_1_0_10_ ( + .I0(N_160), + .I1(N_10339), + .I2(N_10340), + .I3(com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_1_10__1897), + .O(com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_1_0[10]) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_4_1_15_.INIT = 8'h69; + LUT3 com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_4_1_15_ ( + .I0(N_37), + .I1(N_159_1), + .I2(N_27373), + .O(com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_4_1[15]) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_4_15_.INIT = 16'h9669; + LUT4 com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_4_15_ ( + .I0(N_78), + .I1(N_108), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_4_1[15]), + .I3(com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_15__1899), + .O(com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_4_15__1898) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_5_1_28_.INIT = 16'h6996; + LUT4 com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_5_1_28_ ( + .I0(N_10610_1), + .I1(N_27424), + .I2(N_27427), + .I3(N_27563), + .O(com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_5_1[28]) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_5_28_.INIT = 16'h9669; + LUT4 com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_5_28_ ( + .I0(N_126_1), + .I1(N_10343), + .I2(N_27680), + .I3(com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_5_1[28]), + .O(com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_5_28__1900) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_4_20_.INIT = 8'h96; + LUT3_L com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_4_20_ ( + .I0(N_10617), + .I1(N_10340), + .I2(N_57), + .LO(com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_4_20__1901) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_3_26_.INIT = 8'h69; + LUT3 com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_3_26_ ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_26__1903), + .I1(N_27658), + .I2(N_92), + .O(com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_3_26__1902) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_10_.INIT = 16'h6996; + LUT4_L com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_10_ ( + .I0(N_10514), + .I1(N_10565), + .I2(N_10574), + .I3(com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_1_0[10]), + .LO(com_llm_llm_rx_top_llm_rx_tlp_crc_new_c64[10]) + ); + VCC com_llm_llm_rx_top_llm_rx_tlp_sm_VCC ( + .P(com_llm_llm_rx_top_llm_rx_tlp_sm_VCC_1904) + ); + GND com_llm_llm_rx_top_llm_rx_tlp_sm_GND ( + .G(com_llm_llm_rx_top_llm_rx_tlp_sm_GND_1918) + ); + MUXCY_L com_llm_llm_rx_top_llm_rx_tlp_sm_tsn_eq_0_I_1 ( + .CI(com_llm_llm_rx_top_llm_rx_tlp_sm_VCC_1904), + .DI(com_llm_llm_rx_top_llm_rx_tlp_sm_GND_1918), + .LO(com_llm_llm_rx_top_llm_rx_tlp_sm_data_tmp[0]), + .S(com_llm_llm_rx_top_llm_rx_tlp_sm_N_43) + ); + MUXCY_L com_llm_llm_rx_top_llm_rx_tlp_sm_tsn_eq_0_I_10 ( + .CI(com_llm_llm_rx_top_llm_rx_tlp_sm_data_tmp[1]), + .DI(com_llm_llm_rx_top_llm_rx_tlp_sm_GND_1918), + .LO(com_llm_llm_rx_top_llm_rx_tlp_sm_data_tmp[2]), + .S(com_llm_llm_rx_top_llm_rx_tlp_sm_N_35) + ); + MUXCY_L com_llm_llm_rx_top_llm_rx_tlp_sm_tsn_eq_0_I_28 ( + .CI(com_llm_llm_rx_top_llm_rx_tlp_sm_data_tmp[2]), + .DI(com_llm_llm_rx_top_llm_rx_tlp_sm_GND_1918), + .LO(com_llm_llm_rx_top_llm_rx_tlp_sm_data_tmp[3]), + .S(com_llm_llm_rx_top_llm_rx_tlp_sm_N_19) + ); + MUXCY_L com_llm_llm_rx_top_llm_rx_tlp_sm_tsn_eq_0_I_37 ( + .CI(com_llm_llm_rx_top_llm_rx_tlp_sm_data_tmp[3]), + .DI(com_llm_llm_rx_top_llm_rx_tlp_sm_GND_1918), + .LO(com_llm_llm_rx_top_llm_rx_tlp_sm_data_tmp[4]), + .S(com_llm_llm_rx_top_llm_rx_tlp_sm_N_11) + ); + MUXCY_L com_llm_llm_rx_top_llm_rx_tlp_sm_tsn_eq_0_I_46 ( + .CI(com_llm_llm_rx_top_llm_rx_tlp_sm_data_tmp[0]), + .DI(com_llm_llm_rx_top_llm_rx_tlp_sm_GND_1918), + .LO(com_llm_llm_rx_top_llm_rx_tlp_sm_data_tmp[1]), + .S(com_llm_llm_rx_top_llm_rx_tlp_sm_N_3) + ); + MUXCY_L com_llm_llm_rx_top_llm_rx_tlp_sm_tlp_diff_tsn_cry_0 ( + .CI(com_llm_llm_rx_top_llm_rx_tlp_sm_VCC_1904), + .DI(com_llm_reg_next_rcv_tsn[0]), + .LO(com_llm_llm_rx_top_llm_rx_tlp_sm_tlp_diff_tsn_cry_0_1905), + .S(com_llm_llm_rx_top_llm_rx_tlp_sm_tlp_diff_tsn_axb_0_1942) + ); + MUXCY_L com_llm_llm_rx_top_llm_rx_tlp_sm_tlp_diff_tsn_cry_1 ( + .CI(com_llm_llm_rx_top_llm_rx_tlp_sm_tlp_diff_tsn_cry_0_1905), + .DI(com_llm_reg_next_rcv_tsn[1]), + .LO(com_llm_llm_rx_top_llm_rx_tlp_sm_tlp_diff_tsn_cry_1_1906), + .S(com_llm_llm_rx_top_llm_rx_tlp_sm_tlp_diff_tsn_axb_1_1941) + ); + MUXCY_L com_llm_llm_rx_top_llm_rx_tlp_sm_tlp_diff_tsn_cry_2 ( + .CI(com_llm_llm_rx_top_llm_rx_tlp_sm_tlp_diff_tsn_cry_1_1906), + .DI(com_llm_reg_next_rcv_tsn[2]), + .LO(com_llm_llm_rx_top_llm_rx_tlp_sm_tlp_diff_tsn_cry_2_1907), + .S(com_llm_llm_rx_top_llm_rx_tlp_sm_tlp_diff_tsn_axb_2_1940) + ); + MUXCY_L com_llm_llm_rx_top_llm_rx_tlp_sm_tlp_diff_tsn_cry_3 ( + .CI(com_llm_llm_rx_top_llm_rx_tlp_sm_tlp_diff_tsn_cry_2_1907), + .DI(com_llm_reg_next_rcv_tsn[3]), + .LO(com_llm_llm_rx_top_llm_rx_tlp_sm_tlp_diff_tsn_cry_3_1908), + .S(com_llm_llm_rx_top_llm_rx_tlp_sm_tlp_diff_tsn_axb_3_1939) + ); + MUXCY_L com_llm_llm_rx_top_llm_rx_tlp_sm_tlp_diff_tsn_cry_4 ( + .CI(com_llm_llm_rx_top_llm_rx_tlp_sm_tlp_diff_tsn_cry_3_1908), + .DI(com_llm_reg_next_rcv_tsn[4]), + .LO(com_llm_llm_rx_top_llm_rx_tlp_sm_tlp_diff_tsn_cry_4_1909), + .S(com_llm_llm_rx_top_llm_rx_tlp_sm_tlp_diff_tsn_axb_4_1938) + ); + MUXCY_L com_llm_llm_rx_top_llm_rx_tlp_sm_tlp_diff_tsn_cry_5 ( + .CI(com_llm_llm_rx_top_llm_rx_tlp_sm_tlp_diff_tsn_cry_4_1909), + .DI(com_llm_reg_next_rcv_tsn[5]), + .LO(com_llm_llm_rx_top_llm_rx_tlp_sm_tlp_diff_tsn_cry_5_1910), + .S(com_llm_llm_rx_top_llm_rx_tlp_sm_tlp_diff_tsn_axb_5_1937) + ); + MUXCY_L com_llm_llm_rx_top_llm_rx_tlp_sm_tlp_diff_tsn_cry_6 ( + .CI(com_llm_llm_rx_top_llm_rx_tlp_sm_tlp_diff_tsn_cry_5_1910), + .DI(com_llm_reg_next_rcv_tsn[6]), + .LO(com_llm_llm_rx_top_llm_rx_tlp_sm_tlp_diff_tsn_cry_6_1911), + .S(com_llm_llm_rx_top_llm_rx_tlp_sm_tlp_diff_tsn_axb_6_1936) + ); + MUXCY_L com_llm_llm_rx_top_llm_rx_tlp_sm_tlp_diff_tsn_cry_7 ( + .CI(com_llm_llm_rx_top_llm_rx_tlp_sm_tlp_diff_tsn_cry_6_1911), + .DI(com_llm_reg_next_rcv_tsn[7]), + .LO(com_llm_llm_rx_top_llm_rx_tlp_sm_tlp_diff_tsn_cry_7_1912), + .S(com_llm_llm_rx_top_llm_rx_tlp_sm_tlp_diff_tsn_axb_7_1935) + ); + MUXCY_L com_llm_llm_rx_top_llm_rx_tlp_sm_tlp_diff_tsn_cry_8 ( + .CI(com_llm_llm_rx_top_llm_rx_tlp_sm_tlp_diff_tsn_cry_7_1912), + .DI(com_llm_reg_next_rcv_tsn[8]), + .LO(com_llm_llm_rx_top_llm_rx_tlp_sm_tlp_diff_tsn_cry_8_1913), + .S(com_llm_llm_rx_top_llm_rx_tlp_sm_tlp_diff_tsn_axb_8_1934) + ); + MUXCY_L com_llm_llm_rx_top_llm_rx_tlp_sm_tlp_diff_tsn_cry_9 ( + .CI(com_llm_llm_rx_top_llm_rx_tlp_sm_tlp_diff_tsn_cry_8_1913), + .DI(com_llm_reg_next_rcv_tsn[9]), + .LO(com_llm_llm_rx_top_llm_rx_tlp_sm_tlp_diff_tsn_cry_9_1914), + .S(com_llm_llm_rx_top_llm_rx_tlp_sm_tlp_diff_tsn_axb_9_1933) + ); + MUXCY_L com_llm_llm_rx_top_llm_rx_tlp_sm_tlp_diff_tsn_cry_10 ( + .CI(com_llm_llm_rx_top_llm_rx_tlp_sm_tlp_diff_tsn_cry_9_1914), + .DI(com_llm_reg_next_rcv_tsn[10]), + .LO(com_llm_llm_rx_top_llm_rx_tlp_sm_tlp_diff_tsn_cry_10_1915), + .S(com_llm_llm_rx_top_llm_rx_tlp_sm_tlp_diff_tsn_axb_10_1932) + ); + XORCY com_llm_llm_rx_top_llm_rx_tlp_sm_tlp_diff_tsn_s_11 ( + .CI(com_llm_llm_rx_top_llm_rx_tlp_sm_tlp_diff_tsn_cry_10_1915), + .LI(com_llm_llm_rx_top_llm_rx_tlp_sm_tlp_diff_tsn_axb_11_1916), + .O(com_llm_llm_rx_top_llm_rx_tlp_sm_tlp_diff_tsn[11]) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_sm_lnk_reof_n22_0_a2_0_a2_1_0_a4.INIT = 4'h1; + LUT2 com_llm_llm_rx_top_llm_rx_tlp_sm_lnk_reof_n22_0_a2_0_a2_1_0_a4 ( + .I0(com_llm_llm_rx_top_rx_reof_n), + .I1(com_llm_llm_rx_top_rx_rsrc_rdy_n), + .O(com_llm_lnk_reof_n22_1) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_sm_reg_rx_tlp_tsn_err_lrfc_3_i_0_a3_0_a4.INIT = 4'h8; + LUT2 com_llm_llm_rx_top_llm_rx_tlp_sm_reg_rx_tlp_tsn_err_lrfc_3_i_0_a3_0_a4 ( + .I0(com_llm_llm_rx_top_rx_tlp_crc_err_n), + .I1(com_llm_llm_rx_top_rx_tlp_ferr_n), + .O(com_llm_N_38740) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_sm_lnk_rsrc_dsc_n_6_i_0_o2.INIT = 4'h8; + LUT2 com_llm_llm_rx_top_llm_rx_tlp_sm_lnk_rsrc_dsc_n_6_i_0_o2 ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_sm_link_up_1920), + .I1(com_llm_llm_rx_top_llm_rx_tlp_sm_tsn_eq), + .O(com_llm_N_30821_i) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_sm_un1_tlp_ip_q17_5_i_0_o3.INIT = 4'h2; + LUT2 com_llm_llm_rx_top_llm_rx_tlp_sm_un1_tlp_ip_q17_5_i_0_o3 ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_sm_link_up_1920), + .I1(com_llm_llm_rx_top_rx_sof_n), + .O(com_llm_llm_rx_top_llm_rx_tlp_sm_N_30815_i) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_sm_lnk_rsrc_rdy_n_7_i_0_a2.INIT = 4'h1; + LUT2 com_llm_llm_rx_top_llm_rx_tlp_sm_lnk_rsrc_rdy_n_7_i_0_a2 ( + .I0(com_llm_llm_rx_top_rx_reof_n), + .I1(com_llm_llm_rx_top_rx_sof_n), + .O(com_llm_llm_rx_top_llm_rx_tlp_sm_N_30967) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_sm_tlp_diff_tsn_axb_11.INIT = 4'h9; + LUT2 com_llm_llm_rx_top_llm_rx_tlp_sm_tlp_diff_tsn_axb_11 ( + .I0(com_llm_llm_rx_top_rx_tlp_tsn[11]), + .I1(com_llm_reg_next_rcv_tsn[11]), + .O(com_llm_llm_rx_top_llm_rx_tlp_sm_tlp_diff_tsn_axb_11_1916) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_sm_rx_tlp_tsn_err_crc_or_ferr_3_i_0_1.INIT = 4'h1; + LUT2 com_llm_llm_rx_top_llm_rx_tlp_sm_rx_tlp_tsn_err_crc_or_ferr_3_i_0_1 ( + .I0(com_llm_N_38740), + .I1(com_llm_reg_dllr_in_progress), + .O(com_llm_llm_rx_top_llm_rx_tlp_sm_rx_tlp_tsn_err_crc_or_ferr_3_i_0_1_1917) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_sm_reg_rx_tlp_tsn_err_0_a2_0_a2_0_a2_0_a4.INIT = 8'h15; + LUT3 com_llm_llm_rx_top_llm_rx_tlp_sm_reg_rx_tlp_tsn_err_0_a2_0_a2_0_a2_0_a4 ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_sm_reg_rx_tlp_tsn_err_lrfc_1921), + .I1(com_llm_llm_rx_top_llm_rx_tlp_sm_reg_rx_tlp_tsn_err_lrx_1919), + .I2(com_llm_llm_rx_top_llm_rx_tlp_sm_reg_rx_tlp_tsn_err_t_1924), + .O(com_llm_reg_rx_tlp_tsn_err_0_a2_0_a2_0_a2_0_a4) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_sm_reg_rx_tlp_tsn_err_lrx_3_0_a2_0_a2.INIT = 4'h2; + LUT2 com_llm_llm_rx_top_llm_rx_tlp_sm_reg_rx_tlp_tsn_err_lrx_3_0_a2_0_a2 ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_sm_N_30815_i), + .I1(com_llm_reg_dllr_in_progress), + .O(com_llm_llm_rx_top_llm_rx_tlp_sm_reg_rx_tlp_tsn_err_lrx_3) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_sm_un1_rx_reof_n_1_i_0_a2_0.INIT = 8'h02; + LUT3 com_llm_llm_rx_top_llm_rx_tlp_sm_un1_rx_reof_n_1_i_0_a2_0 ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_sm_tlp_diff_tsn[11]), + .I1(com_llm_llm_rx_top_rx_sof_n), + .I2(com_llm_reg_dllr_in_progress), + .O(com_llm_llm_rx_top_llm_rx_tlp_sm_tlp_range_error17) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_sm_lnk_rsrc_rdy_n_7_i_0_m3_0.INIT = 8'hE4; + LUT3_L com_llm_llm_rx_top_llm_rx_tlp_sm_lnk_rsrc_rdy_n_7_i_0_m3_0 ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_sm_N_30815_i), + .I1(com_llm_llm_rx_top_llm_rx_tlp_sm_tlp_ip_q_1931), + .I2(com_llm_llm_rx_top_llm_rx_tlp_sm_tsn_eq), + .LO(com_llm_llm_rx_top_llm_rx_tlp_sm_N_30896) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_sm_un1_tlp_ip_q17_5_i_0_a2.INIT = 8'h08; + LUT3 com_llm_llm_rx_top_llm_rx_tlp_sm_un1_tlp_ip_q17_5_i_0_a2 ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_sm_N_30815_i), + .I1(com_llm_llm_rx_top_llm_rx_tlp_sm_tsn_eq), + .I2(com_llm_llm_rx_top_rx_rsrc_rdy_n), + .O(com_llm_llm_rx_top_llm_rx_tlp_sm_N_30970) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_sm_N_67870_i.INIT = 16'hCFEF; + LUT4 com_llm_llm_rx_top_llm_rx_tlp_sm_N_67870_i ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_sm_tlp_range_error_1929), + .I1(com_llm_llm_rx_top_llm_rx_tlp_sm_tlp_range_error17), + .I2(com_llm_llm_rx_top_rx_reof_n), + .I3(com_llm_llm_rx_top_rx_tlp_crc_err_n), + .O(com_llm_llm_rx_top_llm_rx_tlp_sm_N_67870_i_1928) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_sm_tlp_ip_q18_0_a2_0_a2.INIT = 4'h8; + LUT2 com_llm_llm_rx_top_llm_rx_tlp_sm_tlp_ip_q18_0_a2_0_a2 ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_sm_N_30970), + .I1(com_llm_llm_rx_top_rx_reof_n), + .O(com_llm_llm_rx_top_llm_rx_tlp_sm_tlp_ip_q18) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_sm_N_36496_i.INIT = 8'hEF; + LUT3 com_llm_llm_rx_top_llm_rx_tlp_sm_N_36496_i ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_sm_N_30967), + .I1(com_llm_llm_rx_top_llm_rx_tlp_sm_N_30970), + .I2(com_lnk_reof_n), + .O(com_llm_llm_rx_top_llm_rx_tlp_sm_N_36496_i_1930) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_sm_rx_tlp_tsn_err_crc_or_ferr_3_i_0.INIT = 4'h4; + LUT2_L com_llm_llm_rx_top_llm_rx_tlp_sm_rx_tlp_tsn_err_crc_or_ferr_3_i_0 ( + .I0(com_N_38451), + .I1(com_llm_llm_rx_top_llm_rx_tlp_sm_rx_tlp_tsn_err_crc_or_ferr_3_i_0_1_1917), + .LO(com_llm_llm_rx_top_llm_rx_tlp_sm_N_13392_i) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_sm_reg_rx_tlp_tsn_err_lrfc_3_i_0.INIT = 4'h8; + LUT2_L com_llm_llm_rx_top_llm_rx_tlp_sm_reg_rx_tlp_tsn_err_lrfc_3_i_0 ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_sm_rx_tlp_tsn_err_crc_or_ferr_3_i_0_1_1917), + .I1(com_llm_llm_rx_top_llm_rx_tlp_sm_link_up_1920), + .LO(com_llm_llm_rx_top_llm_rx_tlp_sm_N_13390_i) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_sm_N_30979_i.INIT = 8'hF7; + LUT3_L com_llm_llm_rx_top_llm_rx_tlp_sm_N_30979_i ( + .I0(com_llm_N_38740), + .I1(com_llm_llm_rx_top_llm_rx_tlp_sm_tlp_range_error_1929), + .I2(com_llm_llm_rx_top_rx_reof_n), + .LO(com_llm_llm_rx_top_llm_rx_tlp_sm_N_30979_i_1922) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_sm_tlp_ip_q18_i.INIT = 4'h1; + LUT1_L com_llm_llm_rx_top_llm_rx_tlp_sm_tlp_ip_q18_i ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_sm_tlp_ip_q18), + .LO(com_llm_llm_rx_top_llm_rx_tlp_sm_tlp_ip_q18_i_1923) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_sm_N_67882_i.INIT = 16'hFDDD; + LUT4_L com_llm_llm_rx_top_llm_rx_tlp_sm_N_67882_i ( + .I0(com_llm_N_30821_i), + .I1(com_llm_llm_rx_top_llm_rx_tlp_sm_N_30967), + .I2(com_llm_N_38740), + .I3(com_llm_rx_rsrc_dsc_n), + .LO(com_llm_llm_rx_top_llm_rx_tlp_sm_N_67882_i_1925) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_sm_lnk_reof_n22_i.INIT = 8'h7F; + LUT3_L com_llm_llm_rx_top_llm_rx_tlp_sm_lnk_reof_n22_i ( + .I0(com_llm_lnk_reof_n22_1), + .I1(com_llm_llm_rx_top_llm_rx_tlp_sm_tlp_ip_q_1931), + .I2(com_llm_llm_rx_top_rx_sof_n), + .LO(com_llm_llm_rx_top_llm_rx_tlp_sm_lnk_reof_n22_i_1926) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_sm_N_67869_i.INIT = 8'hFD; + LUT3_L com_llm_llm_rx_top_llm_rx_tlp_sm_N_67869_i ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_sm_N_30896), + .I1(com_llm_llm_rx_top_llm_rx_tlp_sm_N_30967), + .I2(com_llm_llm_rx_top_rx_rsrc_rdy_n), + .LO(com_llm_llm_rx_top_llm_rx_tlp_sm_N_67869_i_1927) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_sm_reg_rx_tlp_tsn_dup_3_0_a2_0_a2.INIT = 16'h0008; + LUT4_L com_llm_llm_rx_top_llm_rx_tlp_sm_reg_rx_tlp_tsn_dup_3_0_a2_0_a2 ( + .I0(com_llm_reg_rx_tlp_tsn_err_0_a2_0_a2_0_a2_0_a4), + .I1(com_llm_llm_rx_top_llm_rx_tlp_sm_reg_rx_tlp_tsn_err_lrx_3), + .I2(com_llm_llm_rx_top_llm_rx_tlp_sm_tlp_diff_tsn[11]), + .I3(com_llm_llm_rx_top_llm_rx_tlp_sm_tsn_eq), + .LO(com_llm_llm_rx_top_llm_rx_tlp_sm_reg_rx_tlp_tsn_dup_3) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_sm_N_51406_i.INIT = 4'h1; + LUT1_L com_llm_llm_rx_top_llm_rx_tlp_sm_N_51406_i ( + .I0(com_llm_reg_rx_tlp_tsn_err_0_a2_0_a2_0_a2_0_a4), + .LO(com_llm_N_51406_i) + ); + MUXCY com_llm_llm_rx_top_llm_rx_tlp_sm_tsn_eq_0_I_19 ( + .CI(com_llm_llm_rx_top_llm_rx_tlp_sm_data_tmp[4]), + .DI(com_llm_llm_rx_top_llm_rx_tlp_sm_GND_1918), + .O(com_llm_llm_rx_top_llm_rx_tlp_sm_tsn_eq), + .S(com_llm_llm_rx_top_llm_rx_tlp_sm_N_27) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_sm_reg_rx_tlp_tsn_err_lrx ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_sm_reg_rx_tlp_tsn_err_lrx_3), + .Q(com_llm_llm_rx_top_llm_rx_tlp_sm_reg_rx_tlp_tsn_err_lrx_1919), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_sm_link_up ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_trn_lnk_up_n_i), + .Q(com_llm_llm_rx_top_llm_rx_tlp_sm_link_up_1920), + .CLR(plm_link_up_i) + ); + FD com_llm_llm_rx_top_llm_rx_tlp_sm_lnk_rrem_reg_2_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_rx_rrem[2]), + .Q(com_lnk_rrem[0]) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_sm_rx_tlp_tsn_err_crc_or_ferr ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_sm_N_13392_i), + .Q(com_rx_tlp_tsn_err_crc_or_ferr), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_sm_reg_rx_tlp_tsn_err_lrfc ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_sm_N_13390_i), + .Q(com_llm_llm_rx_top_llm_rx_tlp_sm_reg_rx_tlp_tsn_err_lrfc_1921), + .CLR(plm_link_up_i) + ); + FDP com_llm_llm_rx_top_llm_rx_tlp_sm_rx_tlp_range_err_n ( + .PRE(plm_link_up_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_sm_N_30979_i_1922), + .Q(com_rx_tlp_range_err_n) + ); + FDP com_llm_llm_rx_top_llm_rx_tlp_sm_lnk_rsof_n ( + .PRE(plm_link_up_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_sm_tlp_ip_q18_i_1923), + .Q(com_lnk_rsof_n) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_sm_reg_rx_tlp_tsn_err_t ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_sm_tlp_diff_tsn[11]), + .Q(com_llm_llm_rx_top_llm_rx_tlp_sm_reg_rx_tlp_tsn_err_t_1924), + .CLR(plm_link_up_i) + ); + FDP com_llm_llm_rx_top_llm_rx_tlp_sm_lnk_rsrc_dsc_n ( + .PRE(plm_link_up_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_sm_N_67882_i_1925), + .Q(com_lnk_rsrc_dsc_n) + ); + FDP com_llm_llm_rx_top_llm_rx_tlp_sm_lnk_reof_n ( + .PRE(plm_link_up_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_sm_lnk_reof_n22_i_1926), + .Q(com_lnk_reof_n) + ); + FDP com_llm_llm_rx_top_llm_rx_tlp_sm_lnk_rsrc_rdy_n ( + .PRE(plm_link_up_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_sm_N_67869_i_1927), + .Q(com_lnk_rsrc_rdy_n) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_sm_reg_rx_tlp_tsn_dup ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_sm_reg_rx_tlp_tsn_dup_3), + .Q(com_llm_reg_rx_tlp_tsn_dup), + .CLR(plm_link_up_i) + ); + FDCE com_llm_llm_rx_top_llm_rx_tlp_sm_tlp_range_error ( + .CE(com_llm_llm_rx_top_llm_rx_tlp_sm_N_67870_i_1928), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_sm_tlp_range_error17), + .Q(com_llm_llm_rx_top_llm_rx_tlp_sm_tlp_range_error_1929), + .CLR(plm_link_up_i) + ); + FD com_llm_llm_rx_top_llm_rx_tlp_sm_lnk_rd_11_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_rx_rd[11]), + .Q(com_lnk_rd_5077[11]) + ); + FD com_llm_llm_rx_top_llm_rx_tlp_sm_lnk_rd_10_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_rx_rd[10]), + .Q(com_lnk_rd_5077[10]) + ); + FD com_llm_llm_rx_top_llm_rx_tlp_sm_lnk_rd_9_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_rx_rd[9]), + .Q(com_lnk_rd_5077[9]) + ); + FD com_llm_llm_rx_top_llm_rx_tlp_sm_lnk_rd_8_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_rx_rd[8]), + .Q(com_lnk_rd_5077[8]) + ); + FD com_llm_llm_rx_top_llm_rx_tlp_sm_lnk_rd_7_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_rx_rd[7]), + .Q(com_lnk_rd_5077[7]) + ); + FD com_llm_llm_rx_top_llm_rx_tlp_sm_lnk_rd_6_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_rx_rd[6]), + .Q(com_lnk_rd[6]) + ); + FD com_llm_llm_rx_top_llm_rx_tlp_sm_lnk_rd_5_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_rx_rd[5]), + .Q(com_lnk_rd[5]) + ); + FD com_llm_llm_rx_top_llm_rx_tlp_sm_lnk_rd_4_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_rx_rd[4]), + .Q(com_lnk_rd[4]) + ); + FD com_llm_llm_rx_top_llm_rx_tlp_sm_lnk_rd_3_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_rx_rd[3]), + .Q(com_lnk_rd[3]) + ); + FD com_llm_llm_rx_top_llm_rx_tlp_sm_lnk_rd_2_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_rx_rd[2]), + .Q(com_lnk_rd[2]) + ); + FD com_llm_llm_rx_top_llm_rx_tlp_sm_lnk_rd_1_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_rx_rd[1]), + .Q(com_lnk_rd[1]) + ); + FD com_llm_llm_rx_top_llm_rx_tlp_sm_lnk_rd_0_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_rx_rd[0]), + .Q(com_lnk_rd[0]) + ); + FD com_llm_llm_rx_top_llm_rx_tlp_sm_lnk_rd_26_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_rx_rd[26]), + .Q(com_lnk_rd_5077[26]) + ); + FD com_llm_llm_rx_top_llm_rx_tlp_sm_lnk_rd_25_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_rx_rd[25]), + .Q(com_lnk_rd_5077[25]) + ); + FD com_llm_llm_rx_top_llm_rx_tlp_sm_lnk_rd_24_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_rx_rd[24]), + .Q(com_lnk_rd_5077[24]) + ); + FD com_llm_llm_rx_top_llm_rx_tlp_sm_lnk_rd_23_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_rx_rd[23]), + .Q(com_lnk_rd_5077[23]) + ); + FD com_llm_llm_rx_top_llm_rx_tlp_sm_lnk_rd_22_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_rx_rd[22]), + .Q(com_lnk_rd_5077[22]) + ); + FD com_llm_llm_rx_top_llm_rx_tlp_sm_lnk_rd_21_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_rx_rd[21]), + .Q(com_lnk_rd_5077[21]) + ); + FD com_llm_llm_rx_top_llm_rx_tlp_sm_lnk_rd_20_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_rx_rd[20]), + .Q(com_lnk_rd_5077[20]) + ); + FD com_llm_llm_rx_top_llm_rx_tlp_sm_lnk_rd_19_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_rx_rd[19]), + .Q(com_lnk_rd_5077[19]) + ); + FD com_llm_llm_rx_top_llm_rx_tlp_sm_lnk_rd_18_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_rx_rd[18]), + .Q(com_lnk_rd_5077[18]) + ); + FD com_llm_llm_rx_top_llm_rx_tlp_sm_lnk_rd_17_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_rx_rd[17]), + .Q(com_lnk_rd_5077[17]) + ); + FD com_llm_llm_rx_top_llm_rx_tlp_sm_lnk_rd_16_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_rx_rd[16]), + .Q(com_lnk_rd_5077[16]) + ); + FD com_llm_llm_rx_top_llm_rx_tlp_sm_lnk_rd_15_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_rx_rd[15]), + .Q(com_lnk_rd_5077[15]) + ); + FD com_llm_llm_rx_top_llm_rx_tlp_sm_lnk_rd_14_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_rx_rd[14]), + .Q(com_lnk_rd_5077[14]) + ); + FD com_llm_llm_rx_top_llm_rx_tlp_sm_lnk_rd_13_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_rx_rd[13]), + .Q(com_lnk_rd_5077[13]) + ); + FD com_llm_llm_rx_top_llm_rx_tlp_sm_lnk_rd_12_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_rx_rd[12]), + .Q(com_lnk_rd_5077[12]) + ); + FD com_llm_llm_rx_top_llm_rx_tlp_sm_lnk_rd_41_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_rx_rd[41]), + .Q(com_lnk_rd_5077[41]) + ); + FD com_llm_llm_rx_top_llm_rx_tlp_sm_lnk_rd_40_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_rx_rd[40]), + .Q(com_lnk_rd_5077[40]) + ); + FD com_llm_llm_rx_top_llm_rx_tlp_sm_lnk_rd_39_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_rx_rd[39]), + .Q(com_lnk_rd_5077[39]) + ); + FD com_llm_llm_rx_top_llm_rx_tlp_sm_lnk_rd_38_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_rx_rd[38]), + .Q(com_lnk_rd_5077[38]) + ); + FD com_llm_llm_rx_top_llm_rx_tlp_sm_lnk_rd_37_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_rx_rd[37]), + .Q(com_lnk_rd_5077[37]) + ); + FD com_llm_llm_rx_top_llm_rx_tlp_sm_lnk_rd_36_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_rx_rd[36]), + .Q(com_lnk_rd_5077[36]) + ); + FD com_llm_llm_rx_top_llm_rx_tlp_sm_lnk_rd_35_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_rx_rd[35]), + .Q(com_lnk_rd_5077[35]) + ); + FD com_llm_llm_rx_top_llm_rx_tlp_sm_lnk_rd_34_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_rx_rd[34]), + .Q(com_lnk_rd_5077[34]) + ); + FD com_llm_llm_rx_top_llm_rx_tlp_sm_lnk_rd_33_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_rx_rd[33]), + .Q(com_lnk_rd_5077[33]) + ); + FD com_llm_llm_rx_top_llm_rx_tlp_sm_lnk_rd_32_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_rx_rd[32]), + .Q(com_lnk_rd_5077[32]) + ); + FD com_llm_llm_rx_top_llm_rx_tlp_sm_lnk_rd_31_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_rx_rd[31]), + .Q(com_lnk_rd_5077[31]) + ); + FD com_llm_llm_rx_top_llm_rx_tlp_sm_lnk_rd_30_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_rx_rd[30]), + .Q(com_lnk_rd_5077[30]) + ); + FD com_llm_llm_rx_top_llm_rx_tlp_sm_lnk_rd_29_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_rx_rd[29]), + .Q(com_lnk_rd_5077[29]) + ); + FD com_llm_llm_rx_top_llm_rx_tlp_sm_lnk_rd_28_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_rx_rd[28]), + .Q(com_lnk_rd_5077[28]) + ); + FD com_llm_llm_rx_top_llm_rx_tlp_sm_lnk_rd_27_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_rx_rd[27]), + .Q(com_lnk_rd_5077[27]) + ); + FD com_llm_llm_rx_top_llm_rx_tlp_sm_lnk_rd_56_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_rx_rd[56]), + .Q(com_lnk_rd_5077[56]) + ); + FD com_llm_llm_rx_top_llm_rx_tlp_sm_lnk_rd_55_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_rx_rd[55]), + .Q(com_lnk_rd_5077[55]) + ); + FD com_llm_llm_rx_top_llm_rx_tlp_sm_lnk_rd_54_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_rx_rd[54]), + .Q(com_lnk_rd_5077[54]) + ); + FD com_llm_llm_rx_top_llm_rx_tlp_sm_lnk_rd_53_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_rx_rd[53]), + .Q(com_lnk_rd_5077[53]) + ); + FD com_llm_llm_rx_top_llm_rx_tlp_sm_lnk_rd_52_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_rx_rd[52]), + .Q(com_lnk_rd_5077[52]) + ); + FD com_llm_llm_rx_top_llm_rx_tlp_sm_lnk_rd_51_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_rx_rd[51]), + .Q(com_lnk_rd_5077[51]) + ); + FD com_llm_llm_rx_top_llm_rx_tlp_sm_lnk_rd_50_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_rx_rd[50]), + .Q(com_lnk_rd_5077[50]) + ); + FD com_llm_llm_rx_top_llm_rx_tlp_sm_lnk_rd_49_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_rx_rd[49]), + .Q(com_lnk_rd_5077[49]) + ); + FD com_llm_llm_rx_top_llm_rx_tlp_sm_lnk_rd_48_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_rx_rd[48]), + .Q(com_lnk_rd_5077[48]) + ); + FD com_llm_llm_rx_top_llm_rx_tlp_sm_lnk_rd_47_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_rx_rd[47]), + .Q(com_lnk_rd_5077[47]) + ); + FD com_llm_llm_rx_top_llm_rx_tlp_sm_lnk_rd_46_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_rx_rd[46]), + .Q(com_lnk_rd_5077[46]) + ); + FD com_llm_llm_rx_top_llm_rx_tlp_sm_lnk_rd_45_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_rx_rd[45]), + .Q(com_lnk_rd_5077[45]) + ); + FD com_llm_llm_rx_top_llm_rx_tlp_sm_lnk_rd_44_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_rx_rd[44]), + .Q(com_lnk_rd_5077[44]) + ); + FD com_llm_llm_rx_top_llm_rx_tlp_sm_lnk_rd_43_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_rx_rd[43]), + .Q(com_lnk_rd_5077[43]) + ); + FD com_llm_llm_rx_top_llm_rx_tlp_sm_lnk_rd_42_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_rx_rd[42]), + .Q(com_lnk_rd_5077[42]) + ); + FD com_llm_llm_rx_top_llm_rx_tlp_sm_lnk_rd_63_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_rx_rd[63]), + .Q(com_lnk_rd_5077[63]) + ); + FD com_llm_llm_rx_top_llm_rx_tlp_sm_lnk_rd_62_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_rx_rd[62]), + .Q(com_lnk_rd_5077[62]) + ); + FD com_llm_llm_rx_top_llm_rx_tlp_sm_lnk_rd_61_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_rx_rd[61]), + .Q(com_lnk_rd_5077[61]) + ); + FD com_llm_llm_rx_top_llm_rx_tlp_sm_lnk_rd_60_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_rx_rd[60]), + .Q(com_lnk_rd_5077[60]) + ); + FD com_llm_llm_rx_top_llm_rx_tlp_sm_lnk_rd_59_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_rx_rd[59]), + .Q(com_lnk_rd_5077[59]) + ); + FD com_llm_llm_rx_top_llm_rx_tlp_sm_lnk_rd_58_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_rx_rd[58]), + .Q(com_lnk_rd_5077[58]) + ); + FD com_llm_llm_rx_top_llm_rx_tlp_sm_lnk_rd_57_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_rx_rd[57]), + .Q(com_lnk_rd_5077[57]) + ); + FDCE com_llm_llm_rx_top_llm_rx_tlp_sm_tlp_ip_q ( + .CE(com_llm_llm_rx_top_llm_rx_tlp_sm_N_36496_i_1930), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_sm_tlp_ip_q18), + .Q(com_llm_llm_rx_top_llm_rx_tlp_sm_tlp_ip_q_1931), + .CLR(plm_link_up_i) + ); + INV com_llm_llm_rx_top_llm_rx_tlp_sm_lnk_rsof_n_i ( + .I(com_lnk_rsof_n), + .O(com_lnk_rsof_n_i) + ); + INV com_llm_llm_rx_top_llm_rx_tlp_sm_lnk_rsrc_rdy_n_i ( + .I(com_lnk_rsrc_rdy_n), + .O(com_lnk_rsrc_rdy_n_i) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_sm_tsn_eq_0_I_27.INIT = 16'h8421; + LUT4 com_llm_llm_rx_top_llm_rx_tlp_sm_tsn_eq_0_I_27 ( + .I0(com_llm_llm_rx_top_rx_tlp_tsn[10]), + .I1(com_llm_llm_rx_top_rx_tlp_tsn[11]), + .I2(com_llm_reg_next_rcv_tsn[10]), + .I3(com_llm_reg_next_rcv_tsn[11]), + .O(com_llm_llm_rx_top_llm_rx_tlp_sm_N_27) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_sm_tlp_diff_tsn_axb_10.INIT = 4'h9; + LUT2 com_llm_llm_rx_top_llm_rx_tlp_sm_tlp_diff_tsn_axb_10 ( + .I0(com_llm_llm_rx_top_rx_tlp_tsn[10]), + .I1(com_llm_reg_next_rcv_tsn[10]), + .O(com_llm_llm_rx_top_llm_rx_tlp_sm_tlp_diff_tsn_axb_10_1932) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_sm_tlp_diff_tsn_axb_9.INIT = 4'h9; + LUT2 com_llm_llm_rx_top_llm_rx_tlp_sm_tlp_diff_tsn_axb_9 ( + .I0(com_llm_llm_rx_top_rx_tlp_tsn[9]), + .I1(com_llm_reg_next_rcv_tsn[9]), + .O(com_llm_llm_rx_top_llm_rx_tlp_sm_tlp_diff_tsn_axb_9_1933) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_sm_tlp_diff_tsn_axb_8.INIT = 4'h9; + LUT2 com_llm_llm_rx_top_llm_rx_tlp_sm_tlp_diff_tsn_axb_8 ( + .I0(com_llm_llm_rx_top_rx_tlp_tsn[8]), + .I1(com_llm_reg_next_rcv_tsn[8]), + .O(com_llm_llm_rx_top_llm_rx_tlp_sm_tlp_diff_tsn_axb_8_1934) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_sm_tlp_diff_tsn_axb_7.INIT = 4'h9; + LUT2 com_llm_llm_rx_top_llm_rx_tlp_sm_tlp_diff_tsn_axb_7 ( + .I0(com_llm_llm_rx_top_rx_tlp_tsn[7]), + .I1(com_llm_reg_next_rcv_tsn[7]), + .O(com_llm_llm_rx_top_llm_rx_tlp_sm_tlp_diff_tsn_axb_7_1935) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_sm_tlp_diff_tsn_axb_6.INIT = 4'h9; + LUT2 com_llm_llm_rx_top_llm_rx_tlp_sm_tlp_diff_tsn_axb_6 ( + .I0(com_llm_llm_rx_top_rx_tlp_tsn[6]), + .I1(com_llm_reg_next_rcv_tsn[6]), + .O(com_llm_llm_rx_top_llm_rx_tlp_sm_tlp_diff_tsn_axb_6_1936) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_sm_tlp_diff_tsn_axb_5.INIT = 4'h9; + LUT2 com_llm_llm_rx_top_llm_rx_tlp_sm_tlp_diff_tsn_axb_5 ( + .I0(com_llm_llm_rx_top_rx_tlp_tsn[5]), + .I1(com_llm_reg_next_rcv_tsn[5]), + .O(com_llm_llm_rx_top_llm_rx_tlp_sm_tlp_diff_tsn_axb_5_1937) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_sm_tlp_diff_tsn_axb_4.INIT = 4'h9; + LUT2 com_llm_llm_rx_top_llm_rx_tlp_sm_tlp_diff_tsn_axb_4 ( + .I0(com_llm_llm_rx_top_rx_tlp_tsn[4]), + .I1(com_llm_reg_next_rcv_tsn[4]), + .O(com_llm_llm_rx_top_llm_rx_tlp_sm_tlp_diff_tsn_axb_4_1938) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_sm_tlp_diff_tsn_axb_3.INIT = 4'h9; + LUT2 com_llm_llm_rx_top_llm_rx_tlp_sm_tlp_diff_tsn_axb_3 ( + .I0(com_llm_llm_rx_top_rx_tlp_tsn[3]), + .I1(com_llm_reg_next_rcv_tsn[3]), + .O(com_llm_llm_rx_top_llm_rx_tlp_sm_tlp_diff_tsn_axb_3_1939) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_sm_tlp_diff_tsn_axb_2.INIT = 4'h9; + LUT2 com_llm_llm_rx_top_llm_rx_tlp_sm_tlp_diff_tsn_axb_2 ( + .I0(com_llm_llm_rx_top_rx_tlp_tsn[2]), + .I1(com_llm_reg_next_rcv_tsn[2]), + .O(com_llm_llm_rx_top_llm_rx_tlp_sm_tlp_diff_tsn_axb_2_1940) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_sm_tlp_diff_tsn_axb_1.INIT = 4'h9; + LUT2 com_llm_llm_rx_top_llm_rx_tlp_sm_tlp_diff_tsn_axb_1 ( + .I0(com_llm_llm_rx_top_rx_tlp_tsn[1]), + .I1(com_llm_reg_next_rcv_tsn[1]), + .O(com_llm_llm_rx_top_llm_rx_tlp_sm_tlp_diff_tsn_axb_1_1941) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_sm_tlp_diff_tsn_axb_0.INIT = 4'h9; + LUT2 com_llm_llm_rx_top_llm_rx_tlp_sm_tlp_diff_tsn_axb_0 ( + .I0(com_llm_llm_rx_top_rx_tlp_tsn[0]), + .I1(com_llm_reg_next_rcv_tsn[0]), + .O(com_llm_llm_rx_top_llm_rx_tlp_sm_tlp_diff_tsn_axb_0_1942) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_sm_tsn_eq_0_I_54.INIT = 16'h8421; + LUT4 com_llm_llm_rx_top_llm_rx_tlp_sm_tsn_eq_0_I_54 ( + .I0(com_llm_llm_rx_top_rx_tlp_tsn[2]), + .I1(com_llm_llm_rx_top_rx_tlp_tsn[3]), + .I2(com_llm_reg_next_rcv_tsn[2]), + .I3(com_llm_reg_next_rcv_tsn[3]), + .O(com_llm_llm_rx_top_llm_rx_tlp_sm_N_3) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_sm_tsn_eq_0_I_45.INIT = 16'h8421; + LUT4 com_llm_llm_rx_top_llm_rx_tlp_sm_tsn_eq_0_I_45 ( + .I0(com_llm_llm_rx_top_rx_tlp_tsn[8]), + .I1(com_llm_llm_rx_top_rx_tlp_tsn[9]), + .I2(com_llm_reg_next_rcv_tsn[8]), + .I3(com_llm_reg_next_rcv_tsn[9]), + .O(com_llm_llm_rx_top_llm_rx_tlp_sm_N_11) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_sm_tsn_eq_0_I_36.INIT = 16'h8421; + LUT4 com_llm_llm_rx_top_llm_rx_tlp_sm_tsn_eq_0_I_36 ( + .I0(com_llm_llm_rx_top_rx_tlp_tsn[6]), + .I1(com_llm_llm_rx_top_rx_tlp_tsn[7]), + .I2(com_llm_reg_next_rcv_tsn[6]), + .I3(com_llm_reg_next_rcv_tsn[7]), + .O(com_llm_llm_rx_top_llm_rx_tlp_sm_N_19) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_sm_tsn_eq_0_I_18.INIT = 16'h8421; + LUT4 com_llm_llm_rx_top_llm_rx_tlp_sm_tsn_eq_0_I_18 ( + .I0(com_llm_llm_rx_top_rx_tlp_tsn[4]), + .I1(com_llm_llm_rx_top_rx_tlp_tsn[5]), + .I2(com_llm_reg_next_rcv_tsn[4]), + .I3(com_llm_reg_next_rcv_tsn[5]), + .O(com_llm_llm_rx_top_llm_rx_tlp_sm_N_35) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_sm_tsn_eq_0_I_9.INIT = 16'h8421; + LUT4 com_llm_llm_rx_top_llm_rx_tlp_sm_tsn_eq_0_I_9 ( + .I0(com_llm_llm_rx_top_rx_tlp_tsn[0]), + .I1(com_llm_llm_rx_top_rx_tlp_tsn[1]), + .I2(com_llm_reg_next_rcv_tsn[0]), + .I3(com_llm_reg_next_rcv_tsn[1]), + .O(com_llm_llm_rx_top_llm_rx_tlp_sm_N_43) + ); + defparam com_llm_llm_common_N_34807_i_0_o3.INIT = 4'h2; + LUT2 com_llm_llm_common_N_34807_i_0_o3 ( + .I0(com_reg_tx_update_retry_int), + .I1(com_reg_tx_update_retry_q), + .O(com_N_38093_i) + ); + defparam com_llm_llm_common_reg_replay_to_val_3_i_m2_i_m3_i_m3_0_0_.INIT = 8'hB8; + LUT3_L com_llm_llm_common_reg_replay_to_val_3_i_m2_i_m3_i_m3_0_0_ ( + .I0(cfg_cfg_5072[448]), + .I1(cfg_cfg_5072[463]), + .I2(com_llm_llm_common_val_1_0_), + .LO(com_llm_llm_common_reg_replay_to_val_3_i_m2_i_m3_i_m3_0_0__1943) + ); + defparam com_llm_llm_common_reg_ack_to_val_3_0_i_m2_i_m3_i_m3_0_0_.INIT = 8'hB8; + LUT3_L com_llm_llm_common_reg_ack_to_val_3_0_i_m2_i_m3_i_m3_0_0_ ( + .I0(cfg_cfg_5072[432]), + .I1(cfg_cfg_5072[447]), + .I2(com_llm_llm_common_val_3_0_), + .LO(com_llm_llm_common_reg_ack_to_val_3_0_i_m2_i_m3_i_m3_0_0__1944) + ); + defparam com_llm_llm_common_reg_replay_to_val_3_0_a2_0_a2_0_a4_14_.INIT = 4'h8; + LUT2_L com_llm_llm_common_reg_replay_to_val_3_0_a2_0_a2_0_a4_14_ ( + .I0(cfg_cfg_5072[462]), + .I1(cfg_cfg_5072[463]), + .LO(com_llm_llm_common_reg_replay_to_val_3[14]) + ); + defparam com_llm_llm_common_reg_replay_to_val_3_0_a2_0_a2_0_a4_13_.INIT = 4'h8; + LUT2_L com_llm_llm_common_reg_replay_to_val_3_0_a2_0_a2_0_a4_13_ ( + .I0(cfg_cfg_5072[461]), + .I1(cfg_cfg_5072[463]), + .LO(com_llm_llm_common_reg_replay_to_val_3[13]) + ); + defparam com_llm_llm_common_reg_replay_to_val_3_0_a2_0_a2_0_a4_12_.INIT = 4'h8; + LUT2_L com_llm_llm_common_reg_replay_to_val_3_0_a2_0_a2_0_a4_12_ ( + .I0(cfg_cfg_5072[460]), + .I1(cfg_cfg_5072[463]), + .LO(com_llm_llm_common_reg_replay_to_val_3[12]) + ); + defparam com_llm_llm_common_reg_replay_to_val_3_0_a2_0_a2_0_a4_11_.INIT = 4'h8; + LUT2_L com_llm_llm_common_reg_replay_to_val_3_0_a2_0_a2_0_a4_11_ ( + .I0(cfg_cfg_5072[459]), + .I1(cfg_cfg_5072[463]), + .LO(com_llm_llm_common_reg_replay_to_val_3[11]) + ); + defparam com_llm_llm_common_reg_replay_to_val_3_0_a2_0_a2_0_a4_10_.INIT = 4'h8; + LUT2_L com_llm_llm_common_reg_replay_to_val_3_0_a2_0_a2_0_a4_10_ ( + .I0(cfg_cfg_5072[458]), + .I1(cfg_cfg_5072[463]), + .LO(com_llm_llm_common_reg_replay_to_val_3[10]) + ); + defparam com_llm_llm_common_reg_replay_to_val_3_0_a2_0_a2_0_a4_9_.INIT = 4'h8; + LUT2_L com_llm_llm_common_reg_replay_to_val_3_0_a2_0_a2_0_a4_9_ ( + .I0(cfg_cfg_5072[457]), + .I1(cfg_cfg_5072[463]), + .LO(com_llm_llm_common_reg_replay_to_val_3[9]) + ); + defparam com_llm_llm_common_reg_replay_to_val_3_i_m2_i_m3_i_m3_8_.INIT = 4'h8; + LUT2_L com_llm_llm_common_reg_replay_to_val_3_i_m2_i_m3_i_m3_8_ ( + .I0(cfg_cfg_5072[456]), + .I1(cfg_cfg_5072[463]), + .LO(com_llm_llm_common_reg_replay_to_val_3_i_m2_i_m3_i_m3_8__1945) + ); + defparam com_llm_llm_common_reg_replay_to_val_3_i_m2_i_m3_i_m3_0_7_.INIT = 8'hB8; + LUT3_L com_llm_llm_common_reg_replay_to_val_3_i_m2_i_m3_i_m3_0_7_ ( + .I0(cfg_cfg_5072[455]), + .I1(cfg_cfg_5072[463]), + .I2(com_llm_llm_common_val_1_7_), + .LO(com_llm_llm_common_reg_replay_to_val_3_i_m2_i_m3_i_m3_0_7__1946) + ); + defparam com_llm_llm_common_reg_replay_to_val_3_i_m2_i_m3_i_m3_0_6_.INIT = 8'hB8; + LUT3_L com_llm_llm_common_reg_replay_to_val_3_i_m2_i_m3_i_m3_0_6_ ( + .I0(cfg_cfg_5072[454]), + .I1(cfg_cfg_5072[463]), + .I2(com_llm_llm_common_val_3_0_), + .LO(com_llm_llm_common_reg_replay_to_val_3_i_m2_i_m3_i_m3_0_6__1947) + ); + defparam com_llm_llm_common_reg_replay_to_val_3_i_m2_i_m3_i_m3_5_.INIT = 4'h8; + LUT2_L com_llm_llm_common_reg_replay_to_val_3_i_m2_i_m3_i_m3_5_ ( + .I0(cfg_cfg_5072[453]), + .I1(cfg_cfg_5072[463]), + .LO(com_llm_llm_common_reg_replay_to_val_3_i_m2_i_m3_i_m3_5__1948) + ); + defparam com_llm_llm_common_N_69352_i.INIT = 4'hB; + LUT2_L com_llm_llm_common_N_69352_i ( + .I0(cfg_cfg_5072[452]), + .I1(cfg_cfg_5072[463]), + .LO(com_llm_llm_common_N_69352_i_1949) + ); + defparam com_llm_llm_common_reg_replay_to_val_3_i_m2_i_m3_i_m3_0_3_.INIT = 8'hB8; + LUT3_L com_llm_llm_common_reg_replay_to_val_3_i_m2_i_m3_i_m3_0_3_ ( + .I0(cfg_cfg_5072[451]), + .I1(cfg_cfg_5072[463]), + .I2(com_llm_llm_common_val_3_4_), + .LO(com_llm_llm_common_reg_replay_to_val_3_i_m2_i_m3_i_m3_0_3__1950) + ); + defparam com_llm_llm_common_reg_replay_to_val_3_i_m2_i_m3_i_m3_0_2_.INIT = 8'hB8; + LUT3_L com_llm_llm_common_reg_replay_to_val_3_i_m2_i_m3_i_m3_0_2_ ( + .I0(cfg_cfg_5072[450]), + .I1(cfg_cfg_5072[463]), + .I2(com_llm_llm_common_val_1_2_), + .LO(com_llm_llm_common_reg_replay_to_val_3_i_m2_i_m3_i_m3_0_2__1951) + ); + defparam com_llm_llm_common_reg_replay_to_val_3_i_m2_i_m3_i_m3_1_.INIT = 4'h8; + LUT2_L com_llm_llm_common_reg_replay_to_val_3_i_m2_i_m3_i_m3_1_ ( + .I0(cfg_cfg_5072[449]), + .I1(cfg_cfg_5072[463]), + .LO(com_llm_llm_common_reg_replay_to_val_3_i_m2_i_m3_i_m3_1__1952) + ); + defparam com_llm_llm_common_reg_ack_to_val_3_i_m2_i_m3_0_a4_14_.INIT = 4'h8; + LUT2_L com_llm_llm_common_reg_ack_to_val_3_i_m2_i_m3_0_a4_14_ ( + .I0(cfg_cfg_5072[446]), + .I1(cfg_cfg_5072[447]), + .LO(com_llm_llm_common_reg_ack_to_val_3_i_m2_i_m3_0_a4[14]) + ); + defparam com_llm_llm_common_reg_ack_to_val_3_i_m2_i_m3_0_a4_13_.INIT = 4'h8; + LUT2_L com_llm_llm_common_reg_ack_to_val_3_i_m2_i_m3_0_a4_13_ ( + .I0(cfg_cfg_5072[445]), + .I1(cfg_cfg_5072[447]), + .LO(com_llm_llm_common_reg_ack_to_val_3_i_m2_i_m3_0_a4[13]) + ); + defparam com_llm_llm_common_reg_ack_to_val_3_0_a2_0_a2_0_a4_12_.INIT = 4'h8; + LUT2_L com_llm_llm_common_reg_ack_to_val_3_0_a2_0_a2_0_a4_12_ ( + .I0(cfg_cfg_5072[444]), + .I1(cfg_cfg_5072[447]), + .LO(com_llm_llm_common_reg_ack_to_val_3_12_) + ); + defparam com_llm_llm_common_N_69357_i.INIT = 8'hB8; + LUT3_L com_llm_llm_common_N_69357_i ( + .I0(cfg_cfg_5072[443]), + .I1(cfg_cfg_5072[447]), + .I2(NlwRenamedSig_OI_cfg_lcommand_7_), + .LO(com_llm_llm_common_N_69357_i_1953) + ); + defparam com_llm_llm_common_reg_ack_to_val_3_i_m2_0_0_a4_10_.INIT = 4'h8; + LUT2_L com_llm_llm_common_reg_ack_to_val_3_i_m2_0_0_a4_10_ ( + .I0(cfg_cfg_5072[442]), + .I1(cfg_cfg_5072[447]), + .LO(com_llm_llm_common_reg_ack_to_val_3_i_m2_0_0_a4[10]) + ); + defparam com_llm_llm_common_reg_ack_to_val_3_i_m2_0_0_a4_0_9_.INIT = 4'h8; + LUT2_L com_llm_llm_common_reg_ack_to_val_3_i_m2_0_0_a4_0_9_ ( + .I0(cfg_cfg_5072[441]), + .I1(cfg_cfg_5072[447]), + .LO(com_llm_llm_common_reg_ack_to_val_3_i_m2_0_0_a4_0[9]) + ); + defparam com_llm_llm_common_reg_ack_to_val_3_0_a2_0_a2_0_a4_8_.INIT = 4'h8; + LUT2_L com_llm_llm_common_reg_ack_to_val_3_0_a2_0_a2_0_a4_8_ ( + .I0(cfg_cfg_5072[440]), + .I1(cfg_cfg_5072[447]), + .LO(com_llm_llm_common_reg_ack_to_val_3_8_) + ); + defparam com_llm_llm_common_N_69359_i.INIT = 8'h8B; + LUT3_L com_llm_llm_common_N_69359_i ( + .I0(cfg_cfg_5072[439]), + .I1(cfg_cfg_5072[447]), + .I2(NlwRenamedSig_OI_cfg_lcommand_7_), + .LO(com_llm_llm_common_N_69359_i_1954) + ); + defparam com_llm_llm_common_reg_ack_to_val_3_0_i_m2_i_m3_i_m3_0_6_.INIT = 8'hB8; + LUT3_L com_llm_llm_common_reg_ack_to_val_3_0_i_m2_i_m3_i_m3_0_6_ ( + .I0(cfg_cfg_5072[438]), + .I1(cfg_cfg_5072[447]), + .I2(com_llm_llm_common_val_1_0_), + .LO(com_llm_llm_common_reg_ack_to_val_3_0_i_m2_i_m3_i_m3_0_6__1955) + ); + defparam com_llm_llm_common_reg_ack_to_val_3_0_i_m2_i_m3_i_m3_0_5_.INIT = 8'hB8; + LUT3_L com_llm_llm_common_reg_ack_to_val_3_0_i_m2_i_m3_i_m3_0_5_ ( + .I0(cfg_cfg_5072[437]), + .I1(cfg_cfg_5072[447]), + .I2(com_llm_llm_common_val_1_2_), + .LO(com_llm_llm_common_reg_ack_to_val_3_0_i_m2_i_m3_i_m3_0_5__1956) + ); + defparam com_llm_llm_common_reg_ack_to_val_3_0_i_m2_i_m3_i_m3_0_4_.INIT = 8'hB8; + LUT3_L com_llm_llm_common_reg_ack_to_val_3_0_i_m2_i_m3_i_m3_0_4_ ( + .I0(cfg_cfg_5072[436]), + .I1(cfg_cfg_5072[447]), + .I2(com_llm_llm_common_val_3_4_), + .LO(com_llm_llm_common_reg_ack_to_val_3_0_i_m2_i_m3_i_m3_0_4__1957) + ); + defparam com_llm_llm_common_reg_ack_to_val_3_0_i_m2_i_m3_i_m3_0_3_.INIT = 8'hB8; + LUT3_L com_llm_llm_common_reg_ack_to_val_3_0_i_m2_i_m3_i_m3_0_3_ ( + .I0(cfg_cfg_5072[435]), + .I1(cfg_cfg_5072[447]), + .I2(com_llm_llm_common_val_2[3]), + .LO(com_llm_llm_common_reg_ack_to_val_3_0_i_m2_i_m3_i_m3_0_3__1958) + ); + defparam com_llm_llm_common_N_69353_i.INIT = 4'hB; + LUT2_L com_llm_llm_common_N_69353_i ( + .I0(cfg_cfg_5072[434]), + .I1(cfg_cfg_5072[447]), + .LO(com_llm_llm_common_N_69353_i_1959) + ); + defparam com_llm_llm_common_reg_ack_to_val_3_0_i_m2_i_m3_i_m3_1_.INIT = 4'h8; + LUT2_L com_llm_llm_common_reg_ack_to_val_3_0_i_m2_i_m3_i_m3_1_ ( + .I0(cfg_cfg_5072[433]), + .I1(cfg_cfg_5072[447]), + .LO(com_llm_llm_common_reg_ack_to_val_3_0_i_m2_i_m3_i_m3[1]) + ); + FDC com_llm_llm_common_reg_tx_update_retry_q ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_reg_tx_update_retry_int), + .Q(com_reg_tx_update_retry_q), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_common_reg_replay_to_val_0_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_common_reg_replay_to_val_3_i_m2_i_m3_i_m3_0_0__1943), + .Q(com_llm_llm_common_reg_replay_to_val[0]), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_common_reg_ack_to_val_0_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_common_reg_ack_to_val_3_0_i_m2_i_m3_i_m3_0_0__1944), + .Q(com_llm_reg_ack_to_val[0]), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_common_reg_replay_to_val_14_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_common_reg_replay_to_val_3[14]), + .Q(com_llm_llm_common_reg_replay_to_val[14]), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_common_reg_replay_to_val_13_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_common_reg_replay_to_val_3[13]), + .Q(com_llm_llm_common_reg_replay_to_val[13]), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_common_reg_replay_to_val_12_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_common_reg_replay_to_val_3[12]), + .Q(com_llm_llm_common_reg_replay_to_val[12]), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_common_reg_replay_to_val_11_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_common_reg_replay_to_val_3[11]), + .Q(com_llm_llm_common_reg_replay_to_val[11]), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_common_reg_replay_to_val_10_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_common_reg_replay_to_val_3[10]), + .Q(com_llm_llm_common_reg_replay_to_val[10]), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_common_reg_replay_to_val_9_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_common_reg_replay_to_val_3[9]), + .Q(com_llm_llm_common_reg_replay_to_val[9]), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_common_reg_replay_to_val_8_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_common_reg_replay_to_val_3_i_m2_i_m3_i_m3_8__1945), + .Q(com_llm_llm_common_reg_replay_to_val[8]), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_common_reg_replay_to_val_7_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_common_reg_replay_to_val_3_i_m2_i_m3_i_m3_0_7__1946), + .Q(com_llm_llm_common_reg_replay_to_val[7]), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_common_reg_replay_to_val_6_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_common_reg_replay_to_val_3_i_m2_i_m3_i_m3_0_6__1947), + .Q(com_llm_llm_common_reg_replay_to_val[6]), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_common_reg_replay_to_val_5_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_common_reg_replay_to_val_3_i_m2_i_m3_i_m3_5__1948), + .Q(com_llm_llm_common_reg_replay_to_val[5]), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_common_reg_replay_to_val_4_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_common_N_69352_i_1949), + .Q(com_llm_llm_common_reg_replay_to_val[4]), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_common_reg_replay_to_val_3_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_common_reg_replay_to_val_3_i_m2_i_m3_i_m3_0_3__1950), + .Q(com_llm_llm_common_reg_replay_to_val[3]), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_common_reg_replay_to_val_2_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_common_reg_replay_to_val_3_i_m2_i_m3_i_m3_0_2__1951), + .Q(com_llm_llm_common_reg_replay_to_val[2]), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_common_reg_replay_to_val_1_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_common_reg_replay_to_val_3_i_m2_i_m3_i_m3_1__1952), + .Q(com_llm_llm_common_reg_replay_to_val[1]), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_common_reg_ack_to_val_14_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_common_reg_ack_to_val_3_i_m2_i_m3_0_a4[14]), + .Q(com_llm_reg_ack_to_val[14]), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_common_reg_ack_to_val_13_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_common_reg_ack_to_val_3_i_m2_i_m3_0_a4[13]), + .Q(com_llm_reg_ack_to_val[13]), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_common_reg_ack_to_val_12_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_common_reg_ack_to_val_3_12_), + .Q(com_llm_reg_ack_to_val[12]), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_common_reg_ack_to_val_11_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_common_N_69357_i_1953), + .Q(com_llm_reg_ack_to_val[11]), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_common_reg_ack_to_val_10_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_common_reg_ack_to_val_3_i_m2_0_0_a4[10]), + .Q(com_llm_reg_ack_to_val[10]), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_common_reg_ack_to_val_9_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_common_reg_ack_to_val_3_i_m2_0_0_a4_0[9]), + .Q(com_llm_reg_ack_to_val[9]), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_common_reg_ack_to_val_8_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_common_reg_ack_to_val_3_8_), + .Q(com_llm_reg_ack_to_val[8]), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_common_reg_ack_to_val_7_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_common_N_69359_i_1954), + .Q(com_llm_reg_ack_to_val[7]), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_common_reg_ack_to_val_6_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_common_reg_ack_to_val_3_0_i_m2_i_m3_i_m3_0_6__1955), + .Q(com_llm_reg_ack_to_val[6]), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_common_reg_ack_to_val_5_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_common_reg_ack_to_val_3_0_i_m2_i_m3_i_m3_0_5__1956), + .Q(com_llm_reg_ack_to_val[5]), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_common_reg_ack_to_val_4_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_common_reg_ack_to_val_3_0_i_m2_i_m3_i_m3_0_4__1957), + .Q(com_llm_reg_ack_to_val[4]), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_common_reg_ack_to_val_3_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_common_reg_ack_to_val_3_0_i_m2_i_m3_i_m3_0_3__1958), + .Q(com_llm_reg_ack_to_val[3]), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_common_reg_ack_to_val_2_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_common_N_69353_i_1959), + .Q(com_llm_reg_ack_to_val[2]), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_common_reg_ack_to_val_1_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_common_reg_ack_to_val_3_0_i_m2_i_m3_i_m3[1]), + .Q(com_llm_reg_ack_to_val[1]), + .CLR(plm_link_up_i) + ); + FD com_llm_llm_common_replay_table_lat_o_1_7_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_common_N_3355_i_i), + .Q(com_llm_llm_common_val_1_7_) + ); + FD com_llm_llm_common_replay_table_lat_o_1_6_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_lat_d_i[2]), + .Q(com_llm_llm_common_val_3_0_) + ); + FD com_llm_llm_common_replay_table_lat_o_1_3_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_N_3419_i), + .Q(com_llm_llm_common_val_3_4_) + ); + defparam com_llm_llm_common_ack_no_synch_table_lat_d_i_o2_0_0_a2_0_a2_0_a2_5_.INIT = 4'h2; + LUT2 com_llm_llm_common_ack_no_synch_table_lat_d_i_o2_0_0_a2_0_a2_0_a2_5_ ( + .I0(com_N_3419_i), + .I1(NlwRenamedSig_OI_cfg_dcommand[5]), + .O(com_N_3355_i) + ); + defparam com_llm_llm_common_ack_no_synch_table_N_3355_i_i.INIT = 4'h1; + LUT1_L com_llm_llm_common_ack_no_synch_table_N_3355_i_i ( + .I0(com_N_3355_i), + .LO(com_llm_llm_common_N_3355_i_i) + ); + FD com_llm_llm_common_ack_no_synch_table_lat_o_1_6_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_N_3419_i_i), + .Q(com_llm_llm_common_val_1_0_) + ); + FD com_llm_llm_common_ack_no_synch_table_lat_o_1_5_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_lat_d[2]), + .Q(com_llm_llm_common_val_1_2_) + ); + FD com_llm_llm_common_ack_no_synch_table_lat_o_1_3_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_N_3355_i), + .Q(com_llm_llm_common_val_2[3]) + ); + defparam com_llm_llm_common_llm_link_sm_llm_link_main_sm_ns_link_i_i_0_0_a4_4_.INIT = 4'h1; + LUT2 com_llm_llm_common_llm_link_sm_llm_link_main_sm_ns_link_i_i_0_0_a4_4_ ( + .I0(com_llm_link_status_3_), + .I1(com_llm_llm_common_llm_link_sm_llm_link_main_sm_link_status[4]), + .O(com_N_38451) + ); + defparam com_llm_llm_common_llm_link_sm_llm_link_main_sm_ns_link_i_i_0_0_o3_i_a2_3_.INIT = 8'hE0; + LUT3 com_llm_llm_common_llm_link_sm_llm_link_main_sm_ns_link_i_i_0_0_o3_i_a2_3_ ( + .I0(com_llm_link_li2_rcv), + .I1(com_llm_link_update_fc_rcv), + .I2(com_llm_link_vc_rcv[0]), + .O(com_llm_llm_common_llm_link_sm_llm_link_main_sm_N_43066) + ); + defparam com_llm_llm_common_llm_link_sm_llm_link_main_sm_ns_link_i_0_0_i_o4_0_i_a2_1_0_2_.INIT = 8'h80; + LUT3 com_llm_llm_common_llm_link_sm_llm_link_main_sm_ns_link_i_0_0_i_o4_0_i_a2_1_0_2_ ( + .I0(com_llm_llm_common_llm_link_sm_llm_link_main_sm_link_fccpl_rcvq), + .I1(com_llm_llm_common_llm_link_sm_llm_link_main_sm_link_fcnp_rcvq), + .I2(plm_link_l0), + .O(com_llm_llm_common_llm_link_sm_llm_link_main_sm_N_50015_1_0) + ); + defparam com_llm_llm_common_llm_link_sm_llm_link_main_sm_ns_link_i_i_0_0_a4_3_.INIT = 8'h02; + LUT3 com_llm_llm_common_llm_link_sm_llm_link_main_sm_ns_link_i_i_0_0_a4_3_ ( + .I0(com_N_38451), + .I1(com_llm_llm_common_llm_link_sm_llm_link_main_sm_N_43066), + .I2(com_lnk_tfc_vc_hit), + .O(com_llm_llm_common_llm_link_sm_llm_link_main_sm_N_38455) + ); + defparam com_llm_llm_common_llm_link_sm_llm_link_main_sm_ns_link_i_i_0_0_0_0_1_.INIT = 16'hEC00; + LUT4 com_llm_llm_common_llm_link_sm_llm_link_main_sm_ns_link_i_i_0_0_0_0_1_ ( + .I0(com_llm_link_status_0_), + .I1(com_link_status[1]), + .I2(plm_link_l0), + .I3(plm_link_up_1), + .O(com_llm_llm_common_llm_link_sm_llm_link_main_sm_ns_link_i_i_0_0_0_0[1]) + ); + defparam com_llm_llm_common_llm_link_sm_llm_link_main_sm_trn_lnk_up_n_i.INIT = 4'h1; + LUT1_L com_llm_llm_common_llm_link_sm_llm_link_main_sm_trn_lnk_up_n_i ( + .I0(NlwRenamedSig_OI_trn_lnk_up_n), + .LO(com_llm_trn_lnk_up_n_i) + ); + defparam com_llm_llm_common_llm_link_sm_llm_link_main_sm_ns_link_i_i_0_0_4_.INIT = 8'h10; + LUT3_L com_llm_llm_common_llm_link_sm_llm_link_main_sm_ns_link_i_i_0_0_4_ ( + .I0(com_N_38451), + .I1(plm_link_l0), + .I2(plm_link_up_2), + .LO(com_llm_llm_common_llm_link_sm_llm_link_main_sm_N_13559_i) + ); + defparam com_llm_llm_common_llm_link_sm_llm_link_main_sm_ns_link_i_i_0_0_3_.INIT = 16'h0040; + LUT4_L com_llm_llm_common_llm_link_sm_llm_link_main_sm_ns_link_i_i_0_0_3_ ( + .I0(com_llm_llm_common_llm_link_sm_llm_link_main_sm_N_38455), + .I1(plm_link_l0), + .I2(plm_link_up_2), + .I3(NlwRenamedSig_OI_trn_lnk_up_n), + .LO(com_llm_llm_common_llm_link_sm_llm_link_main_sm_N_13964_i) + ); + defparam com_llm_llm_common_llm_link_sm_llm_link_main_sm_ns_link_i_0_0_i_2_.INIT = 16'hEC00; + LUT4_L com_llm_llm_common_llm_link_sm_llm_link_main_sm_ns_link_i_0_0_i_2_ ( + .I0(com_llm_llm_common_llm_link_sm_llm_link_main_sm_N_50015_1_0), + .I1(com_link_status[2]), + .I2(com_llm_llm_common_llm_link_sm_llm_link_main_sm_link_fcp_rcvq), + .I3(com_llm_llm_common_llm_link_sm_llm_link_main_sm_ns_link_i_0_0_i_2[2]), + .LO(com_llm_llm_common_llm_link_sm_llm_link_main_sm_N_40553_i) + ); + defparam com_llm_llm_common_llm_link_sm_llm_link_main_sm_ns_link_i_i_0_0_0_1_.INIT = 16'hDF00; + LUT4_L com_llm_llm_common_llm_link_sm_llm_link_main_sm_ns_link_i_i_0_0_0_1_ ( + .I0(com_llm_llm_common_llm_link_sm_llm_link_main_sm_N_50015_1_0), + .I1(com_llm_link_status_0_), + .I2(com_llm_llm_common_llm_link_sm_llm_link_main_sm_link_fcp_rcvq), + .I3(com_llm_llm_common_llm_link_sm_llm_link_main_sm_ns_link_i_i_0_0_0_0[1]), + .LO(com_llm_llm_common_llm_link_sm_llm_link_main_sm_N_18596_i) + ); + defparam com_llm_llm_common_llm_link_sm_llm_link_main_sm_N_69354_i.INIT = 8'h2F; + LUT3_L com_llm_llm_common_llm_link_sm_llm_link_main_sm_N_69354_i ( + .I0(com_llm_link_status_0_), + .I1(plm_link_l0), + .I2(plm_link_up_2), + .LO(com_llm_llm_common_llm_link_sm_llm_link_main_sm_N_69354_i_1960) + ); + defparam com_llm_llm_common_llm_link_sm_llm_link_main_sm_ns_link_i_0_0_i_2_1_2_.INIT = 16'h0353; + LUT4 com_llm_llm_common_llm_link_sm_llm_link_main_sm_ns_link_i_0_0_i_2_1_2_ ( + .I0(com_llm_llm_common_llm_link_sm_llm_link_main_sm_N_43066), + .I1(com_link_status[1]), + .I2(com_link_status[2]), + .I3(com_lnk_tfc_vc_hit), + .O(com_llm_llm_common_llm_link_sm_llm_link_main_sm_ns_link_i_0_0_i_2_1[2]) + ); + defparam com_llm_llm_common_llm_link_sm_llm_link_main_sm_ns_link_i_0_0_i_2_2_.INIT = 16'h9B00; + LUT4 com_llm_llm_common_llm_link_sm_llm_link_main_sm_ns_link_i_0_0_i_2_2_ ( + .I0(com_link_status[2]), + .I1(com_llm_llm_common_llm_link_sm_llm_link_main_sm_ns_link_i_0_0_i_2_1[2]), + .I2(plm_link_l0), + .I3(plm_link_up_2), + .O(com_llm_llm_common_llm_link_sm_llm_link_main_sm_ns_link_i_0_0_i_2[2]) + ); + defparam com_llm_llm_common_llm_link_sm_llm_link_main_sm_ns_link_i_i_0_a2_0_0_a2_3_.INIT = 8'h01; + LUT3 com_llm_llm_common_llm_link_sm_llm_link_main_sm_ns_link_i_i_0_a2_0_0_a2_3_ ( + .I0(com_link_status[2]), + .I1(com_llm_llm_common_llm_link_sm_llm_link_main_sm_link_status[4]), + .I2(com_llm_link_status_3_), + .O(NlwRenamedSig_OI_trn_lnk_up_n) + ); + FDC com_llm_llm_common_llm_link_sm_llm_link_main_sm_link_status_4_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_common_llm_link_sm_llm_link_main_sm_N_13559_i), + .Q(com_llm_llm_common_llm_link_sm_llm_link_main_sm_link_status[4]), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_common_llm_link_sm_llm_link_main_sm_link_status_3_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_common_llm_link_sm_llm_link_main_sm_N_13964_i), + .Q(com_llm_link_status_3_), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_common_llm_link_sm_llm_link_main_sm_link_status_2_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_common_llm_link_sm_llm_link_main_sm_N_40553_i), + .Q(com_link_status[2]), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_common_llm_link_sm_llm_link_main_sm_link_status_1_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_common_llm_link_sm_llm_link_main_sm_N_18596_i), + .Q(com_link_status[1]), + .CLR(plm_link_up_i) + ); + FDP com_llm_llm_common_llm_link_sm_llm_link_main_sm_link_status_0_ ( + .PRE(plm_link_up_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_common_llm_link_sm_llm_link_main_sm_N_69354_i_1960), + .Q(com_llm_link_status_0_) + ); + INV com_llm_llm_common_llm_link_sm_llm_link_main_sm_link_status_i_0_ ( + .I(com_llm_link_status_0_), + .O(com_llm_llm_common_link_status_i[0]) + ); + FDRE com_llm_llm_common_llm_link_sm_llm_link_main_sm_sticky0_q ( + .CE(com_llm_llm_common_llm_link_sm_llm_link_main_sm_sticky0_q5_i_1961), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_common_llm_link_sm_llm_link_main_sm_sticky0_qc_1962), + .Q(com_llm_llm_common_llm_link_sm_llm_link_main_sm_link_fcp_rcvq), + .R(com_llm_link_status_0_) + ); + defparam com_llm_llm_common_llm_link_sm_llm_link_main_sm_sticky0_q5_i.INIT = 4'hB; + LUT2 com_llm_llm_common_llm_link_sm_llm_link_main_sm_sticky0_q5_i ( + .I0(com_llm_link_status_0_), + .I1(com_llm_llm_common_llm_link_sm_llm_link_main_sm_link_fcp_rcvq), + .O(com_llm_llm_common_llm_link_sm_llm_link_main_sm_sticky0_q5_i_1961) + ); + defparam com_llm_llm_common_llm_link_sm_llm_link_main_sm_sticky0_qc.INIT = 4'h8; + LUT2_L com_llm_llm_common_llm_link_sm_llm_link_main_sm_sticky0_qc ( + .I0(com_llm_link_li1_p_rcv), + .I1(com_llm_link_vc_rcv[0]), + .LO(com_llm_llm_common_llm_link_sm_llm_link_main_sm_sticky0_qc_1962) + ); + FDRE com_llm_llm_common_llm_link_sm_llm_link_main_sm_sticky1_q ( + .CE(com_llm_llm_common_llm_link_sm_llm_link_main_sm_sticky1_q5_i_1963), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_common_llm_link_sm_llm_link_main_sm_sticky1_qc_1964), + .Q(com_llm_llm_common_llm_link_sm_llm_link_main_sm_link_fcnp_rcvq), + .R(com_llm_link_status_0_) + ); + defparam com_llm_llm_common_llm_link_sm_llm_link_main_sm_sticky1_q5_i.INIT = 4'hB; + LUT2 com_llm_llm_common_llm_link_sm_llm_link_main_sm_sticky1_q5_i ( + .I0(com_llm_link_status_0_), + .I1(com_llm_llm_common_llm_link_sm_llm_link_main_sm_link_fcnp_rcvq), + .O(com_llm_llm_common_llm_link_sm_llm_link_main_sm_sticky1_q5_i_1963) + ); + defparam com_llm_llm_common_llm_link_sm_llm_link_main_sm_sticky1_qc.INIT = 4'h8; + LUT2_L com_llm_llm_common_llm_link_sm_llm_link_main_sm_sticky1_qc ( + .I0(com_llm_link_li1_np_rcv), + .I1(com_llm_link_vc_rcv[0]), + .LO(com_llm_llm_common_llm_link_sm_llm_link_main_sm_sticky1_qc_1964) + ); + FDRE com_llm_llm_common_llm_link_sm_llm_link_main_sm_sticky2_q ( + .CE(com_llm_llm_common_llm_link_sm_llm_link_main_sm_sticky2_q5_i_1965), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_common_llm_link_sm_llm_link_main_sm_sticky2_qc_1966), + .Q(com_llm_llm_common_llm_link_sm_llm_link_main_sm_link_fccpl_rcvq), + .R(com_llm_link_status_0_) + ); + defparam com_llm_llm_common_llm_link_sm_llm_link_main_sm_sticky2_q5_i.INIT = 4'hB; + LUT2 com_llm_llm_common_llm_link_sm_llm_link_main_sm_sticky2_q5_i ( + .I0(com_llm_link_status_0_), + .I1(com_llm_llm_common_llm_link_sm_llm_link_main_sm_link_fccpl_rcvq), + .O(com_llm_llm_common_llm_link_sm_llm_link_main_sm_sticky2_q5_i_1965) + ); + defparam com_llm_llm_common_llm_link_sm_llm_link_main_sm_sticky2_qc.INIT = 4'h8; + LUT2_L com_llm_llm_common_llm_link_sm_llm_link_main_sm_sticky2_qc ( + .I0(com_llm_link_li1_cpl_rcv), + .I1(com_llm_link_vc_rcv[0]), + .LO(com_llm_llm_common_llm_link_sm_llm_link_main_sm_sticky2_qc_1966) + ); + VCC com_llm_llm_common_llm_common_reg_VCC ( + .P(com_llm_llm_common_llm_common_reg_VCC_1978) + ); + GND com_llm_llm_common_llm_common_reg_GND ( + .G(com_llm_llm_common_llm_common_reg_GND_2028) + ); + FDS com_llm_llm_common_llm_common_reg_reg_tx_curr_tsn_0_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_common_llm_common_reg_N_42834_i_2027), + .Q(com_llm_llm_common_llm_common_reg_reg_tx_curr_tsn[0]), + .S(plm_link_up_i) + ); + FDS com_llm_llm_common_llm_common_reg_reg_tx_curr_tsn_1_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_common_llm_common_reg_N_42833_i_2026), + .Q(com_llm_llm_common_llm_common_reg_reg_tx_curr_tsn[1]), + .S(plm_link_up_i) + ); + FDS com_llm_llm_common_llm_common_reg_reg_tx_curr_tsn_2_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_common_llm_common_reg_N_42832_i_2025), + .Q(com_llm_llm_common_llm_common_reg_reg_tx_curr_tsn[2]), + .S(plm_link_up_i) + ); + FDS com_llm_llm_common_llm_common_reg_reg_tx_curr_tsn_3_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_common_llm_common_reg_N_42831_i_2024), + .Q(com_llm_llm_common_llm_common_reg_reg_tx_curr_tsn[3]), + .S(plm_link_up_i) + ); + FDS com_llm_llm_common_llm_common_reg_reg_tx_curr_tsn_4_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_common_llm_common_reg_N_42830_i_2023), + .Q(com_llm_llm_common_llm_common_reg_reg_tx_curr_tsn[4]), + .S(plm_link_up_i) + ); + FDS com_llm_llm_common_llm_common_reg_reg_tx_curr_tsn_5_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_common_llm_common_reg_N_42829_i_2022), + .Q(com_llm_llm_common_llm_common_reg_reg_tx_curr_tsn[5]), + .S(plm_link_up_i) + ); + FDS com_llm_llm_common_llm_common_reg_reg_tx_curr_tsn_6_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_common_llm_common_reg_N_42828_i_2021), + .Q(com_llm_llm_common_llm_common_reg_reg_tx_curr_tsn[6]), + .S(plm_link_up_i) + ); + FDS com_llm_llm_common_llm_common_reg_reg_tx_curr_tsn_7_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_common_llm_common_reg_N_42827_i_2020), + .Q(com_llm_llm_common_llm_common_reg_reg_tx_curr_tsn[7]), + .S(plm_link_up_i) + ); + FDS com_llm_llm_common_llm_common_reg_reg_tx_curr_tsn_8_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_common_llm_common_reg_N_42826_i_2019), + .Q(com_llm_llm_common_llm_common_reg_reg_tx_curr_tsn[8]), + .S(plm_link_up_i) + ); + FDS com_llm_llm_common_llm_common_reg_reg_tx_curr_tsn_9_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_common_llm_common_reg_N_42825_i_2018), + .Q(com_llm_llm_common_llm_common_reg_reg_tx_curr_tsn[9]), + .S(plm_link_up_i) + ); + FDS com_llm_llm_common_llm_common_reg_reg_tx_curr_tsn_10_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_common_llm_common_reg_N_42824_i_2017), + .Q(com_llm_llm_common_llm_common_reg_reg_tx_curr_tsn[10]), + .S(plm_link_up_i) + ); + FDS com_llm_llm_common_llm_common_reg_reg_tx_curr_tsn_11_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_common_llm_common_reg_N_42823_i_2016), + .Q(com_llm_llm_common_llm_common_reg_reg_tx_curr_tsn[11]), + .S(plm_link_up_i) + ); + MUXCY_L com_llm_llm_common_llm_common_reg_ANSeqNum_Eq_AckdSeq_wire_0_I_1 ( + .CI(com_llm_llm_common_llm_common_reg_VCC_1978), + .DI(com_llm_llm_common_llm_common_reg_GND_2028), + .LO(com_llm_llm_common_llm_common_reg_data_tmp_2[0]), + .S(com_llm_llm_common_llm_common_reg_N_43) + ); + MUXCY_L com_llm_llm_common_llm_common_reg_ANSeqNum_Eq_AckdSeq_wire_0_I_10 ( + .CI(com_llm_llm_common_llm_common_reg_data_tmp_2[1]), + .DI(com_llm_llm_common_llm_common_reg_GND_2028), + .LO(com_llm_llm_common_llm_common_reg_data_tmp_2[2]), + .S(com_llm_llm_common_llm_common_reg_N_35) + ); + MUXCY_L com_llm_llm_common_llm_common_reg_ANSeqNum_Eq_AckdSeq_wire_0_I_28 ( + .CI(com_llm_llm_common_llm_common_reg_data_tmp_2[2]), + .DI(com_llm_llm_common_llm_common_reg_GND_2028), + .LO(com_llm_llm_common_llm_common_reg_data_tmp_2[3]), + .S(com_llm_llm_common_llm_common_reg_N_19) + ); + MUXCY_L com_llm_llm_common_llm_common_reg_ANSeqNum_Eq_AckdSeq_wire_0_I_37 ( + .CI(com_llm_llm_common_llm_common_reg_data_tmp_2[3]), + .DI(com_llm_llm_common_llm_common_reg_GND_2028), + .LO(com_llm_llm_common_llm_common_reg_data_tmp[4]), + .S(com_llm_llm_common_llm_common_reg_N_11) + ); + MUXCY_L com_llm_llm_common_llm_common_reg_ANSeqNum_Eq_AckdSeq_wire_0_I_46 ( + .CI(com_llm_llm_common_llm_common_reg_data_tmp_2[0]), + .DI(com_llm_llm_common_llm_common_reg_GND_2028), + .LO(com_llm_llm_common_llm_common_reg_data_tmp_2[1]), + .S(com_llm_llm_common_llm_common_reg_N_3) + ); + MUXCY_L com_llm_llm_common_llm_common_reg_rx_tsn_eq_sent_tsn_3_0_I_1 ( + .CI(com_llm_llm_common_llm_common_reg_VCC_1978), + .DI(com_llm_llm_common_llm_common_reg_GND_2028), + .LO(com_llm_llm_common_llm_common_reg_data_tmp_1[0]), + .S(com_llm_llm_common_llm_common_reg_N_43_0) + ); + MUXCY_L com_llm_llm_common_llm_common_reg_rx_tsn_eq_sent_tsn_3_0_I_10 ( + .CI(com_llm_llm_common_llm_common_reg_data_tmp_1[1]), + .DI(com_llm_llm_common_llm_common_reg_GND_2028), + .LO(com_llm_llm_common_llm_common_reg_data_tmp_1[2]), + .S(com_llm_llm_common_llm_common_reg_N_35_0) + ); + MUXCY_L com_llm_llm_common_llm_common_reg_rx_tsn_eq_sent_tsn_3_0_I_28 ( + .CI(com_llm_llm_common_llm_common_reg_data_tmp_1[2]), + .DI(com_llm_llm_common_llm_common_reg_GND_2028), + .LO(com_llm_llm_common_llm_common_reg_data_tmp_1[3]), + .S(com_llm_llm_common_llm_common_reg_N_19_0) + ); + MUXCY_L com_llm_llm_common_llm_common_reg_rx_tsn_eq_sent_tsn_3_0_I_37 ( + .CI(com_llm_llm_common_llm_common_reg_data_tmp_1[3]), + .DI(com_llm_llm_common_llm_common_reg_GND_2028), + .LO(com_llm_llm_common_llm_common_reg_data_tmp_0[4]), + .S(com_llm_llm_common_llm_common_reg_N_11_0) + ); + MUXCY_L com_llm_llm_common_llm_common_reg_rx_tsn_eq_sent_tsn_3_0_I_46 ( + .CI(com_llm_llm_common_llm_common_reg_data_tmp_1[0]), + .DI(com_llm_llm_common_llm_common_reg_GND_2028), + .LO(com_llm_llm_common_llm_common_reg_data_tmp_1[1]), + .S(com_llm_llm_common_llm_common_reg_N_3_0) + ); + MUXCY_L com_llm_llm_common_llm_common_reg_next_eq_mark_q_3_0_I_1 ( + .CI(com_llm_llm_common_llm_common_reg_VCC_1978), + .DI(com_llm_llm_common_llm_common_reg_GND_2028), + .LO(com_llm_llm_common_llm_common_reg_data_tmp_0[0]), + .S(com_llm_llm_common_llm_common_reg_N_43_1) + ); + MUXCY_L com_llm_llm_common_llm_common_reg_next_eq_mark_q_3_0_I_10 ( + .CI(com_llm_llm_common_llm_common_reg_data_tmp_0[1]), + .DI(com_llm_llm_common_llm_common_reg_GND_2028), + .LO(com_llm_llm_common_llm_common_reg_data_tmp_0[2]), + .S(com_llm_llm_common_llm_common_reg_N_35_1) + ); + MUXCY_L com_llm_llm_common_llm_common_reg_next_eq_mark_q_3_0_I_28 ( + .CI(com_llm_llm_common_llm_common_reg_data_tmp_0[2]), + .DI(com_llm_llm_common_llm_common_reg_GND_2028), + .LO(com_llm_llm_common_llm_common_reg_data_tmp_0[3]), + .S(com_llm_llm_common_llm_common_reg_N_19_1) + ); + MUXCY_L com_llm_llm_common_llm_common_reg_next_eq_mark_q_3_0_I_37 ( + .CI(com_llm_llm_common_llm_common_reg_data_tmp_0[3]), + .DI(com_llm_llm_common_llm_common_reg_GND_2028), + .LO(com_llm_llm_common_llm_common_reg_data_tmp_1[4]), + .S(com_llm_llm_common_llm_common_reg_N_11_1) + ); + MUXCY_L com_llm_llm_common_llm_common_reg_next_eq_mark_q_3_0_I_46 ( + .CI(com_llm_llm_common_llm_common_reg_data_tmp_0[0]), + .DI(com_llm_llm_common_llm_common_reg_GND_2028), + .LO(com_llm_llm_common_llm_common_reg_data_tmp_0[1]), + .S(com_llm_llm_common_llm_common_reg_N_3_1) + ); + MUXCY_L com_llm_llm_common_llm_common_reg_curr_eq_mark_q_3_0_I_1 ( + .CI(com_llm_llm_common_llm_common_reg_VCC_1978), + .DI(com_llm_llm_common_llm_common_reg_GND_2028), + .LO(com_llm_llm_common_llm_common_reg_data_tmp[0]), + .S(com_llm_llm_common_llm_common_reg_N_43_2) + ); + MUXCY_L com_llm_llm_common_llm_common_reg_curr_eq_mark_q_3_0_I_10 ( + .CI(com_llm_llm_common_llm_common_reg_data_tmp[1]), + .DI(com_llm_llm_common_llm_common_reg_GND_2028), + .LO(com_llm_llm_common_llm_common_reg_data_tmp[2]), + .S(com_llm_llm_common_llm_common_reg_N_35_2) + ); + MUXCY_L com_llm_llm_common_llm_common_reg_curr_eq_mark_q_3_0_I_28 ( + .CI(com_llm_llm_common_llm_common_reg_data_tmp[2]), + .DI(com_llm_llm_common_llm_common_reg_GND_2028), + .LO(com_llm_llm_common_llm_common_reg_data_tmp[3]), + .S(com_llm_llm_common_llm_common_reg_N_19_2) + ); + MUXCY_L com_llm_llm_common_llm_common_reg_curr_eq_mark_q_3_0_I_37 ( + .CI(com_llm_llm_common_llm_common_reg_data_tmp[3]), + .DI(com_llm_llm_common_llm_common_reg_GND_2028), + .LO(com_llm_llm_common_llm_common_reg_data_tmp_2[4]), + .S(com_llm_llm_common_llm_common_reg_N_11_2) + ); + MUXCY_L com_llm_llm_common_llm_common_reg_curr_eq_mark_q_3_0_I_46 ( + .CI(com_llm_llm_common_llm_common_reg_data_tmp[0]), + .DI(com_llm_llm_common_llm_common_reg_GND_2028), + .LO(com_llm_llm_common_llm_common_reg_data_tmp[1]), + .S(com_llm_llm_common_llm_common_reg_N_3_2) + ); + MUXCY_L com_llm_llm_common_llm_common_reg_un3_ttrans_st_hiwater_cry_0 ( + .CI(com_llm_llm_common_llm_common_reg_VCC_1978), + .DI(com_lnk_ttrans_seq[0]), + .LO(com_llm_llm_common_llm_common_reg_un3_ttrans_st_hiwater_cry_0_1967), + .S(com_llm_llm_common_llm_common_reg_un3_ttrans_st_hiwater_axb_0_2107) + ); + MUXCY_L com_llm_llm_common_llm_common_reg_un3_ttrans_st_hiwater_cry_1 ( + .CI(com_llm_llm_common_llm_common_reg_un3_ttrans_st_hiwater_cry_0_1967), + .DI(com_lnk_ttrans_seq[1]), + .LO(com_llm_llm_common_llm_common_reg_un3_ttrans_st_hiwater_cry_1_1968), + .S(com_llm_llm_common_llm_common_reg_un3_ttrans_st_hiwater_axb_1_2106) + ); + MUXCY_L com_llm_llm_common_llm_common_reg_un3_ttrans_st_hiwater_cry_2 ( + .CI(com_llm_llm_common_llm_common_reg_un3_ttrans_st_hiwater_cry_1_1968), + .DI(com_lnk_ttrans_seq[2]), + .LO(com_llm_llm_common_llm_common_reg_un3_ttrans_st_hiwater_cry_2_1969), + .S(com_llm_llm_common_llm_common_reg_un3_ttrans_st_hiwater_axb_2_2105) + ); + MUXCY_L com_llm_llm_common_llm_common_reg_un3_ttrans_st_hiwater_cry_3 ( + .CI(com_llm_llm_common_llm_common_reg_un3_ttrans_st_hiwater_cry_2_1969), + .DI(com_lnk_ttrans_seq[3]), + .LO(com_llm_llm_common_llm_common_reg_un3_ttrans_st_hiwater_cry_3_1970), + .S(com_llm_llm_common_llm_common_reg_un3_ttrans_st_hiwater_axb_3_2104) + ); + MUXCY_L com_llm_llm_common_llm_common_reg_un3_ttrans_st_hiwater_cry_4 ( + .CI(com_llm_llm_common_llm_common_reg_un3_ttrans_st_hiwater_cry_3_1970), + .DI(com_lnk_ttrans_seq[4]), + .LO(com_llm_llm_common_llm_common_reg_un3_ttrans_st_hiwater_cry_4_1971), + .S(com_llm_llm_common_llm_common_reg_un3_ttrans_st_hiwater_axb_4_2103) + ); + MUXCY_L com_llm_llm_common_llm_common_reg_un3_ttrans_st_hiwater_cry_5 ( + .CI(com_llm_llm_common_llm_common_reg_un3_ttrans_st_hiwater_cry_4_1971), + .DI(com_lnk_ttrans_seq[5]), + .LO(com_llm_llm_common_llm_common_reg_un3_ttrans_st_hiwater_cry_5_1972), + .S(com_llm_llm_common_llm_common_reg_un3_ttrans_st_hiwater_axb_5_2102) + ); + MUXCY_L com_llm_llm_common_llm_common_reg_un3_ttrans_st_hiwater_cry_6 ( + .CI(com_llm_llm_common_llm_common_reg_un3_ttrans_st_hiwater_cry_5_1972), + .DI(com_lnk_ttrans_seq[6]), + .LO(com_llm_llm_common_llm_common_reg_un3_ttrans_st_hiwater_cry_6_1973), + .S(com_llm_llm_common_llm_common_reg_un3_ttrans_st_hiwater_axb_6_2101) + ); + MUXCY_L com_llm_llm_common_llm_common_reg_un3_ttrans_st_hiwater_cry_7 ( + .CI(com_llm_llm_common_llm_common_reg_un3_ttrans_st_hiwater_cry_6_1973), + .DI(com_lnk_ttrans_seq[7]), + .LO(com_llm_llm_common_llm_common_reg_un3_ttrans_st_hiwater_cry_7_1974), + .S(com_llm_llm_common_llm_common_reg_un3_ttrans_st_hiwater_axb_7_2100) + ); + MUXCY_L com_llm_llm_common_llm_common_reg_un3_ttrans_st_hiwater_cry_8 ( + .CI(com_llm_llm_common_llm_common_reg_un3_ttrans_st_hiwater_cry_7_1974), + .DI(com_lnk_ttrans_seq[8]), + .LO(com_llm_llm_common_llm_common_reg_un3_ttrans_st_hiwater_cry_8_1975), + .S(com_llm_llm_common_llm_common_reg_un3_ttrans_st_hiwater_axb_8_2099) + ); + MUXCY_L com_llm_llm_common_llm_common_reg_un3_ttrans_st_hiwater_cry_9 ( + .CI(com_llm_llm_common_llm_common_reg_un3_ttrans_st_hiwater_cry_8_1975), + .DI(com_lnk_ttrans_seq[9]), + .LO(com_llm_llm_common_llm_common_reg_un3_ttrans_st_hiwater_cry_9_1976), + .S(com_llm_llm_common_llm_common_reg_un3_ttrans_st_hiwater_axb_9_2098) + ); + MUXCY_L com_llm_llm_common_llm_common_reg_un3_ttrans_st_hiwater_cry_10 ( + .CI(com_llm_llm_common_llm_common_reg_un3_ttrans_st_hiwater_cry_9_1976), + .DI(com_lnk_ttrans_seq[10]), + .LO(com_llm_llm_common_llm_common_reg_un3_ttrans_st_hiwater_cry_10_1977), + .S(com_llm_llm_common_llm_common_reg_un3_ttrans_st_hiwater_axb_10_2097) + ); + XORCY com_llm_llm_common_llm_common_reg_un3_ttrans_st_hiwater_s_11 ( + .CI(com_llm_llm_common_llm_common_reg_un3_ttrans_st_hiwater_cry_10_1977), + .LI(com_llm_llm_common_llm_common_reg_un3_ttrans_st_hiwater_axb_11_2003), + .O(com_llm_llm_common_llm_common_reg_un3_ttrans_st_hiwater_s_11_2037) + ); + MUXCY_L com_llm_llm_common_llm_common_reg_un3_tmp_result_cry_0 ( + .CI(com_llm_llm_common_llm_common_reg_VCC_1978), + .DI(com_lnk_ttrans_seq[0]), + .LO(com_llm_llm_common_llm_common_reg_un3_tmp_result_cry_0_1979), + .S(com_llm_llm_common_llm_common_reg_un3_tmp_result_axb_0_2096) + ); + MUXCY_L com_llm_llm_common_llm_common_reg_un3_tmp_result_cry_1 ( + .CI(com_llm_llm_common_llm_common_reg_un3_tmp_result_cry_0_1979), + .DI(com_lnk_ttrans_seq[1]), + .LO(com_llm_llm_common_llm_common_reg_un3_tmp_result_cry_1_1980), + .S(com_llm_llm_common_llm_common_reg_un3_tmp_result_axb_1_2095) + ); + MUXCY_L com_llm_llm_common_llm_common_reg_un3_tmp_result_cry_2 ( + .CI(com_llm_llm_common_llm_common_reg_un3_tmp_result_cry_1_1980), + .DI(com_lnk_ttrans_seq[2]), + .LO(com_llm_llm_common_llm_common_reg_un3_tmp_result_cry_2_1981), + .S(com_llm_llm_common_llm_common_reg_un3_tmp_result_axb_2_2094) + ); + MUXCY_L com_llm_llm_common_llm_common_reg_un3_tmp_result_cry_3 ( + .CI(com_llm_llm_common_llm_common_reg_un3_tmp_result_cry_2_1981), + .DI(com_lnk_ttrans_seq[3]), + .LO(com_llm_llm_common_llm_common_reg_un3_tmp_result_cry_3_1982), + .S(com_llm_llm_common_llm_common_reg_un3_tmp_result_axb_3_2093) + ); + MUXCY_L com_llm_llm_common_llm_common_reg_un3_tmp_result_cry_4 ( + .CI(com_llm_llm_common_llm_common_reg_un3_tmp_result_cry_3_1982), + .DI(com_lnk_ttrans_seq[4]), + .LO(com_llm_llm_common_llm_common_reg_un3_tmp_result_cry_4_1983), + .S(com_llm_llm_common_llm_common_reg_un3_tmp_result_axb_4_2092) + ); + MUXCY_L com_llm_llm_common_llm_common_reg_un3_tmp_result_cry_5 ( + .CI(com_llm_llm_common_llm_common_reg_un3_tmp_result_cry_4_1983), + .DI(com_lnk_ttrans_seq[5]), + .LO(com_llm_llm_common_llm_common_reg_un3_tmp_result_cry_5_1984), + .S(com_llm_llm_common_llm_common_reg_un3_tmp_result_axb_5_2091) + ); + MUXCY_L com_llm_llm_common_llm_common_reg_un3_tmp_result_cry_6 ( + .CI(com_llm_llm_common_llm_common_reg_un3_tmp_result_cry_5_1984), + .DI(com_lnk_ttrans_seq[6]), + .LO(com_llm_llm_common_llm_common_reg_un3_tmp_result_cry_6_1985), + .S(com_llm_llm_common_llm_common_reg_un3_tmp_result_axb_6_2090) + ); + MUXCY_L com_llm_llm_common_llm_common_reg_un3_tmp_result_cry_7 ( + .CI(com_llm_llm_common_llm_common_reg_un3_tmp_result_cry_6_1985), + .DI(com_lnk_ttrans_seq[7]), + .LO(com_llm_llm_common_llm_common_reg_un3_tmp_result_cry_7_1986), + .S(com_llm_llm_common_llm_common_reg_un3_tmp_result_axb_7_2089) + ); + MUXCY_L com_llm_llm_common_llm_common_reg_un3_tmp_result_cry_8 ( + .CI(com_llm_llm_common_llm_common_reg_un3_tmp_result_cry_7_1986), + .DI(com_lnk_ttrans_seq[8]), + .LO(com_llm_llm_common_llm_common_reg_un3_tmp_result_cry_8_1987), + .S(com_llm_llm_common_llm_common_reg_un3_tmp_result_axb_8_2088) + ); + MUXCY_L com_llm_llm_common_llm_common_reg_un3_tmp_result_cry_9 ( + .CI(com_llm_llm_common_llm_common_reg_un3_tmp_result_cry_8_1987), + .DI(com_lnk_ttrans_seq[9]), + .LO(com_llm_llm_common_llm_common_reg_un3_tmp_result_cry_9_1988), + .S(com_llm_llm_common_llm_common_reg_un3_tmp_result_axb_9_2087) + ); + MUXCY_L com_llm_llm_common_llm_common_reg_un3_tmp_result_cry_10 ( + .CI(com_llm_llm_common_llm_common_reg_un3_tmp_result_cry_9_1988), + .DI(com_lnk_ttrans_seq[10]), + .LO(com_llm_llm_common_llm_common_reg_un3_tmp_result_cry_10_1989), + .S(com_llm_llm_common_llm_common_reg_un3_tmp_result_axb_10_2086) + ); + XORCY com_llm_llm_common_llm_common_reg_un3_tmp_result_s_11 ( + .CI(com_llm_llm_common_llm_common_reg_un3_tmp_result_cry_10_1989), + .LI(com_llm_llm_common_llm_common_reg_un3_tmp_result_axb_11_2004), + .O(com_llm_llm_common_llm_common_reg_un3_tmp_result_s_11_2038) + ); + MUXCY_L com_llm_llm_common_llm_common_reg_reg_tx_next_tsn_4_cry_0 ( + .CI(plm_link_up_1), + .DI(com_llm_llm_common_llm_common_reg_GND_2028), + .LO(com_llm_llm_common_llm_common_reg_reg_tx_next_tsn_4_cry_0_1990), + .S(com_llm_llm_common_llm_common_reg_reg_tx_next_tsn_4_axb_0_2085) + ); + MUXCY_L com_llm_llm_common_llm_common_reg_reg_tx_next_tsn_4_cry_1 ( + .CI(com_llm_llm_common_llm_common_reg_reg_tx_next_tsn_4_cry_0_1990), + .DI(com_llm_llm_common_llm_common_reg_GND_2028), + .LO(com_llm_llm_common_llm_common_reg_reg_tx_next_tsn_4_cry_1_1991), + .S(com_llm_llm_common_llm_common_reg_reg_tx_next_tsn_4_axb_1_2015) + ); + XORCY com_llm_llm_common_llm_common_reg_reg_tx_next_tsn_4_s_1 ( + .CI(com_llm_llm_common_llm_common_reg_reg_tx_next_tsn_4_cry_0_1990), + .LI(com_llm_llm_common_llm_common_reg_reg_tx_next_tsn_4_axb_1_2015), + .O(com_llm_llm_common_llm_common_reg_reg_tx_next_tsn_4[1]) + ); + MUXCY_L com_llm_llm_common_llm_common_reg_reg_tx_next_tsn_4_cry_2 ( + .CI(com_llm_llm_common_llm_common_reg_reg_tx_next_tsn_4_cry_1_1991), + .DI(com_llm_llm_common_llm_common_reg_GND_2028), + .LO(com_llm_llm_common_llm_common_reg_reg_tx_next_tsn_4_cry_2_1992), + .S(com_llm_llm_common_llm_common_reg_reg_tx_next_tsn_4_axb_2_2014) + ); + XORCY com_llm_llm_common_llm_common_reg_reg_tx_next_tsn_4_s_2 ( + .CI(com_llm_llm_common_llm_common_reg_reg_tx_next_tsn_4_cry_1_1991), + .LI(com_llm_llm_common_llm_common_reg_reg_tx_next_tsn_4_axb_2_2014), + .O(com_llm_llm_common_llm_common_reg_reg_tx_next_tsn_4[2]) + ); + MUXCY_L com_llm_llm_common_llm_common_reg_reg_tx_next_tsn_4_cry_3 ( + .CI(com_llm_llm_common_llm_common_reg_reg_tx_next_tsn_4_cry_2_1992), + .DI(com_llm_llm_common_llm_common_reg_GND_2028), + .LO(com_llm_llm_common_llm_common_reg_reg_tx_next_tsn_4_cry_3_1993), + .S(com_llm_llm_common_llm_common_reg_reg_tx_next_tsn_4_axb_3_2013) + ); + XORCY com_llm_llm_common_llm_common_reg_reg_tx_next_tsn_4_s_3 ( + .CI(com_llm_llm_common_llm_common_reg_reg_tx_next_tsn_4_cry_2_1992), + .LI(com_llm_llm_common_llm_common_reg_reg_tx_next_tsn_4_axb_3_2013), + .O(com_llm_llm_common_llm_common_reg_reg_tx_next_tsn_4[3]) + ); + MUXCY_L com_llm_llm_common_llm_common_reg_reg_tx_next_tsn_4_cry_4 ( + .CI(com_llm_llm_common_llm_common_reg_reg_tx_next_tsn_4_cry_3_1993), + .DI(com_llm_llm_common_llm_common_reg_GND_2028), + .LO(com_llm_llm_common_llm_common_reg_reg_tx_next_tsn_4_cry_4_1994), + .S(com_llm_llm_common_llm_common_reg_reg_tx_next_tsn_4_axb_4_2012) + ); + XORCY com_llm_llm_common_llm_common_reg_reg_tx_next_tsn_4_s_4 ( + .CI(com_llm_llm_common_llm_common_reg_reg_tx_next_tsn_4_cry_3_1993), + .LI(com_llm_llm_common_llm_common_reg_reg_tx_next_tsn_4_axb_4_2012), + .O(com_llm_llm_common_llm_common_reg_reg_tx_next_tsn_4[4]) + ); + MUXCY_L com_llm_llm_common_llm_common_reg_reg_tx_next_tsn_4_cry_5 ( + .CI(com_llm_llm_common_llm_common_reg_reg_tx_next_tsn_4_cry_4_1994), + .DI(com_llm_llm_common_llm_common_reg_GND_2028), + .LO(com_llm_llm_common_llm_common_reg_reg_tx_next_tsn_4_cry_5_1995), + .S(com_llm_llm_common_llm_common_reg_reg_tx_next_tsn_4_axb_5_2011) + ); + XORCY com_llm_llm_common_llm_common_reg_reg_tx_next_tsn_4_s_5 ( + .CI(com_llm_llm_common_llm_common_reg_reg_tx_next_tsn_4_cry_4_1994), + .LI(com_llm_llm_common_llm_common_reg_reg_tx_next_tsn_4_axb_5_2011), + .O(com_llm_llm_common_llm_common_reg_reg_tx_next_tsn_4[5]) + ); + MUXCY_L com_llm_llm_common_llm_common_reg_reg_tx_next_tsn_4_cry_6 ( + .CI(com_llm_llm_common_llm_common_reg_reg_tx_next_tsn_4_cry_5_1995), + .DI(com_llm_llm_common_llm_common_reg_GND_2028), + .LO(com_llm_llm_common_llm_common_reg_reg_tx_next_tsn_4_cry_6_1996), + .S(com_llm_llm_common_llm_common_reg_reg_tx_next_tsn_4_axb_6_2010) + ); + XORCY com_llm_llm_common_llm_common_reg_reg_tx_next_tsn_4_s_6 ( + .CI(com_llm_llm_common_llm_common_reg_reg_tx_next_tsn_4_cry_5_1995), + .LI(com_llm_llm_common_llm_common_reg_reg_tx_next_tsn_4_axb_6_2010), + .O(com_llm_llm_common_llm_common_reg_reg_tx_next_tsn_4[6]) + ); + MUXCY_L com_llm_llm_common_llm_common_reg_reg_tx_next_tsn_4_cry_7 ( + .CI(com_llm_llm_common_llm_common_reg_reg_tx_next_tsn_4_cry_6_1996), + .DI(com_llm_llm_common_llm_common_reg_GND_2028), + .LO(com_llm_llm_common_llm_common_reg_reg_tx_next_tsn_4_cry_7_1997), + .S(com_llm_llm_common_llm_common_reg_reg_tx_next_tsn_4_axb_7_2009) + ); + XORCY com_llm_llm_common_llm_common_reg_reg_tx_next_tsn_4_s_7 ( + .CI(com_llm_llm_common_llm_common_reg_reg_tx_next_tsn_4_cry_6_1996), + .LI(com_llm_llm_common_llm_common_reg_reg_tx_next_tsn_4_axb_7_2009), + .O(com_llm_llm_common_llm_common_reg_reg_tx_next_tsn_4[7]) + ); + MUXCY_L com_llm_llm_common_llm_common_reg_reg_tx_next_tsn_4_cry_8 ( + .CI(com_llm_llm_common_llm_common_reg_reg_tx_next_tsn_4_cry_7_1997), + .DI(com_llm_llm_common_llm_common_reg_GND_2028), + .LO(com_llm_llm_common_llm_common_reg_reg_tx_next_tsn_4_cry_8_1998), + .S(com_llm_llm_common_llm_common_reg_reg_tx_next_tsn_4_axb_8_2008) + ); + XORCY com_llm_llm_common_llm_common_reg_reg_tx_next_tsn_4_s_8 ( + .CI(com_llm_llm_common_llm_common_reg_reg_tx_next_tsn_4_cry_7_1997), + .LI(com_llm_llm_common_llm_common_reg_reg_tx_next_tsn_4_axb_8_2008), + .O(com_llm_llm_common_llm_common_reg_reg_tx_next_tsn_4[8]) + ); + MUXCY_L com_llm_llm_common_llm_common_reg_reg_tx_next_tsn_4_cry_9 ( + .CI(com_llm_llm_common_llm_common_reg_reg_tx_next_tsn_4_cry_8_1998), + .DI(com_llm_llm_common_llm_common_reg_GND_2028), + .LO(com_llm_llm_common_llm_common_reg_reg_tx_next_tsn_4_cry_9_1999), + .S(com_llm_llm_common_llm_common_reg_reg_tx_next_tsn_4_axb_9_2007) + ); + XORCY com_llm_llm_common_llm_common_reg_reg_tx_next_tsn_4_s_9 ( + .CI(com_llm_llm_common_llm_common_reg_reg_tx_next_tsn_4_cry_8_1998), + .LI(com_llm_llm_common_llm_common_reg_reg_tx_next_tsn_4_axb_9_2007), + .O(com_llm_llm_common_llm_common_reg_reg_tx_next_tsn_4[9]) + ); + MUXCY_L com_llm_llm_common_llm_common_reg_reg_tx_next_tsn_4_cry_10 ( + .CI(com_llm_llm_common_llm_common_reg_reg_tx_next_tsn_4_cry_9_1999), + .DI(com_llm_llm_common_llm_common_reg_GND_2028), + .LO(com_llm_llm_common_llm_common_reg_reg_tx_next_tsn_4_cry_10_2000), + .S(com_llm_llm_common_llm_common_reg_reg_tx_next_tsn_4_axb_10_2006) + ); + XORCY com_llm_llm_common_llm_common_reg_reg_tx_next_tsn_4_s_10 ( + .CI(com_llm_llm_common_llm_common_reg_reg_tx_next_tsn_4_cry_9_1999), + .LI(com_llm_llm_common_llm_common_reg_reg_tx_next_tsn_4_axb_10_2006), + .O(com_llm_llm_common_llm_common_reg_reg_tx_next_tsn_4[10]) + ); + XORCY com_llm_llm_common_llm_common_reg_reg_tx_next_tsn_4_s_11 ( + .CI(com_llm_llm_common_llm_common_reg_reg_tx_next_tsn_4_cry_10_2000), + .LI(com_llm_llm_common_llm_common_reg_reg_tx_next_tsn_4_axb_11_2005), + .O(com_llm_llm_common_llm_common_reg_reg_tx_next_tsn_4[11]) + ); + FDR com_llm_llm_common_llm_common_reg_reg_tx_next_tsn_0_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_lnk_ttrans_seq_i[0]), + .Q(com_llm_llm_common_llm_common_reg_reg_tx_next_tsn[0]), + .R(plm_link_up_i) + ); + defparam com_llm_llm_common_llm_common_reg_un1_link_status_3_0_0_0_o4.INIT = 4'h1; + LUT2 com_llm_llm_common_llm_common_reg_un1_link_status_3_0_0_0_o4 ( + .I0(com_llm_llm_common_llm_common_reg_reg_rx_dllp_ack_vld_q_2033), + .I1(com_llm_llm_common_llm_common_reg_reg_rx_dllp_nak_vld_q_2032), + .O(com_llm_llm_common_llm_common_reg_N_41809_i) + ); + defparam com_llm_llm_common_llm_common_reg_lnk_sys_reset_n_0_a2_0_a2_0_a2.INIT = 4'h2; + LUT2 com_llm_llm_common_llm_common_reg_lnk_sys_reset_n_0_a2_0_a2_0_a2 ( + .I0(com_llm_link_status_0_), + .I1(plm_link_up_1), + .O(com_llm_llm_common_llm_common_reg_lnk_sys_reset_n_0_a2_0_a2_0_a2_2001) + ); + defparam com_llm_llm_common_llm_common_reg_un1_curr_eq_mark_q_0_a2_i_0_a4.INIT = 4'h8; + LUT2 com_llm_llm_common_llm_common_reg_un1_curr_eq_mark_q_0_a2_i_0_a4 ( + .I0(com_llm_llm_common_llm_common_reg_reg_tx_update_clr_q_2031), + .I1(com_reg_tx_update_retry_q), + .O(com_llm_llm_common_llm_common_reg_N_38751) + ); + defparam com_llm_llm_common_llm_common_reg_ANSeqNum_Eq_AckdSeq_5_0_a2_0_a2_0_a2_1_0.INIT = 16'h0100; + LUT4 com_llm_llm_common_llm_common_reg_ANSeqNum_Eq_AckdSeq_5_0_a2_0_a2_0_a2_1_0 ( + .I0(com_llm_rx_dllp[29]), + .I1(com_llm_rx_dllp[30]), + .I2(com_llm_rx_dllp[31]), + .I3(com_llm_rx_dllp_vld), + .O(com_llm_ANSeqNum_Eq_AckdSeq_5_0_a2_0_a2_0_a2_1_0) + ); + defparam com_llm_llm_common_llm_common_reg_N_69063_i.INIT = 16'hAAAB; + LUT4 com_llm_llm_common_llm_common_reg_N_69063_i ( + .I0(com_llm_link_status_0_), + .I1(com_llm_llm_common_llm_common_reg_replay_ip_2058), + .I2(com_llm_llm_common_llm_common_reg_ttrans_st_hiwater[11]), + .I3(com_lnk_tretry), + .O(com_llm_llm_common_llm_common_reg_N_69063_i_2070) + ); + defparam com_llm_llm_common_llm_common_reg_N_67865_i.INIT = 16'hFFFE; + LUT4 com_llm_llm_common_llm_common_reg_N_67865_i ( + .I0(com_llm_llm_common_llm_common_reg_N_38751), + .I1(com_llm_link_status_0_), + .I2(com_llm_llm_common_llm_common_reg_curr_eq_mark_q_2035), + .I3(com_llm_llm_common_llm_common_reg_next_eq_mark_q_2034), + .O(com_llm_llm_common_llm_common_reg_N_67865_i_2057) + ); + defparam com_llm_llm_common_llm_common_reg_un1_reg_rx_tlp_tsn_vld_i_0_0_a4.INIT = 16'h8000; + LUT4 com_llm_llm_common_llm_common_reg_un1_reg_rx_tlp_tsn_vld_i_0_0_a4 ( + .I0(com_llm_N_30821_i), + .I1(com_llm_N_38740), + .I2(com_llm_lnk_reof_n22_1), + .I3(com_llm_rx_rsrc_dsc_n), + .O(com_llm_llm_common_llm_common_reg_N_30966_1) + ); + defparam com_llm_llm_common_llm_common_reg_N_69244_i.INIT = 16'hF0F2; + LUT4 com_llm_llm_common_llm_common_reg_N_69244_i ( + .I0(com_llm_llm_common_llm_common_reg_N_38195_i), + .I1(com_llm_llm_common_llm_common_reg_N_41809_i), + .I2(com_llm_link_status_0_), + .I3(com_llm_llm_common_llm_common_reg_tmp_result[11]), + .O(com_llm_llm_common_llm_common_reg_N_69244_i_2083) + ); + defparam com_llm_llm_common_llm_common_reg_un1_reg_tx_dllp_ack_clr_1_i_0_1.INIT = 16'h0C08; + LUT4 com_llm_llm_common_llm_common_reg_un1_reg_tx_dllp_ack_clr_1_i_0_1 ( + .I0(com_llm_N_38737_1_i), + .I1(com_llm_reg_rx_tlp_tsn_err_0_a2_0_a2_0_a2_0_a4), + .I2(com_llm_reg_rx_tlp_tsn_dup), + .I3(com_llm_reg_tx_dllp_nak_vld), + .O(com_llm_llm_common_llm_common_reg_un1_reg_tx_dllp_ack_clr_1_i_0_1_2002) + ); + defparam com_llm_llm_common_llm_common_reg_N_67883_i.INIT = 8'hFB; + LUT3 com_llm_llm_common_llm_common_reg_N_67883_i ( + .I0(com_llm_llm_common_llm_common_reg_N_30966_1), + .I1(com_llm_reg_rx_tlp_tsn_err_0_a2_0_a2_0_a2_0_a4), + .I2(com_llm_link_status_0_), + .O(com_llm_llm_common_llm_common_reg_N_67883_i_2042) + ); + defparam com_llm_llm_common_llm_common_reg_N_69070_i.INIT = 8'h73; + LUT3 com_llm_llm_common_llm_common_reg_N_69070_i ( + .I0(com_llm_N_38737_1_i), + .I1(com_llm_reg_rx_tlp_tsn_err_0_a2_0_a2_0_a2_0_a4), + .I2(com_llm_reg_tx_dllp_nak_vld), + .O(com_llm_llm_common_llm_common_reg_N_69070_i_2041) + ); + defparam com_llm_llm_common_llm_common_reg_N_69044_i.INIT = 8'hFB; + LUT3 com_llm_llm_common_llm_common_reg_N_69044_i ( + .I0(com_llm_llm_common_llm_common_reg_N_30966_1), + .I1(com_llm_llm_common_llm_common_reg_un1_reg_tx_dllp_ack_clr_1_i_0_1_2002), + .I2(com_llm_reg_dllr_in_progress), + .O(com_llm_llm_common_llm_common_reg_N_69044_i_2056) + ); + defparam com_llm_llm_common_llm_common_reg_N_69229_i.INIT = 4'hB; + LUT2 com_llm_llm_common_llm_common_reg_N_69229_i ( + .I0(com_llm_llm_common_llm_common_reg_N_30966_1), + .I1(com_llm_llm_common_llm_common_reg_un1_reg_tx_dllp_ack_clr_1_i_0_1_2002), + .O(com_llm_llm_common_llm_common_reg_N_69229_i_2055) + ); + defparam com_llm_llm_common_llm_common_reg_NxtTxTSN_ANSeqNum_i_0_0.INIT = 4'h4; + LUT2_L com_llm_llm_common_llm_common_reg_NxtTxTSN_ANSeqNum_i_0_0 ( + .I0(com_llm_llm_common_llm_common_reg_N_41809_i), + .I1(com_llm_llm_common_llm_common_reg_NxtTxTSN_ANSeqNum_wire_2029), + .LO(com_llm_llm_common_llm_common_reg_N_13526_i) + ); + defparam com_llm_llm_common_llm_common_reg_ANSeqNum_AckdSeq_i_0_0.INIT = 4'h4; + LUT2_L com_llm_llm_common_llm_common_reg_ANSeqNum_AckdSeq_i_0_0 ( + .I0(com_llm_llm_common_llm_common_reg_N_41809_i), + .I1(com_llm_llm_common_llm_common_reg_ANSeqNum_AckdSeq_wire_2030), + .LO(com_llm_llm_common_llm_common_reg_N_13528_i) + ); + defparam com_llm_llm_common_llm_common_reg_un3_ttrans_st_hiwater_axb_11.INIT = 4'h9; + LUT2_L com_llm_llm_common_llm_common_reg_un3_ttrans_st_hiwater_axb_11 ( + .I0(com_llm_llm_common_llm_common_reg_hi_water_mark[11]), + .I1(com_lnk_ttrans_seq[11]), + .LO(com_llm_llm_common_llm_common_reg_un3_ttrans_st_hiwater_axb_11_2003) + ); + defparam com_llm_llm_common_llm_common_reg_un3_tmp_result_axb_11.INIT = 4'h9; + LUT2_L com_llm_llm_common_llm_common_reg_un3_tmp_result_axb_11 ( + .I0(com_llm_reg_rx_dllp_tsn_m1[11]), + .I1(com_lnk_ttrans_seq[11]), + .LO(com_llm_llm_common_llm_common_reg_un3_tmp_result_axb_11_2004) + ); + defparam com_llm_llm_common_llm_common_reg_N_67867_i.INIT = 16'hFEEE; + LUT4_L com_llm_llm_common_llm_common_reg_N_67867_i ( + .I0(com_llm_llm_common_llm_common_reg_N_41809_i), + .I1(com_llm_link_status_0_), + .I2(com_llm_llm_common_llm_common_reg_ANSeqNum_AckdSeq_wire_2030), + .I3(com_llm_llm_common_llm_common_reg_NxtTxTSN_ANSeqNum_wire_2029), + .LO(com_llm_llm_common_llm_common_reg_N_67867_i_2039) + ); + defparam com_llm_llm_common_llm_common_reg_ANSeqNum_Eq_AckdSeq_5_0_a2_0_a2_0_a2.INIT = 8'h80; + LUT3_L com_llm_llm_common_llm_common_reg_ANSeqNum_Eq_AckdSeq_5_0_a2_0_a2_0_a2 ( + .I0(com_llm_N_41810_i), + .I1(com_llm_ANSeqNum_Eq_AckdSeq_5_0_a2_0_a2_0_a2_1_0), + .I2(com_llm_llm_common_llm_common_reg_ANSeqNum_Eq_AckdSeq_wire), + .LO(com_llm_llm_common_llm_common_reg_ANSeqNum_Eq_AckdSeq_5) + ); + defparam com_llm_llm_common_llm_common_reg_reg_tx_next_tsn_4_axb_11.INIT = 4'h8; + LUT2_L com_llm_llm_common_llm_common_reg_reg_tx_next_tsn_4_axb_11 ( + .I0(com_lnk_ttrans_seq[11]), + .I1(plm_link_up_2), + .LO(com_llm_llm_common_llm_common_reg_reg_tx_next_tsn_4_axb_11_2005) + ); + defparam com_llm_llm_common_llm_common_reg_reg_tx_next_tsn_4_axb_10.INIT = 4'h8; + LUT2_L com_llm_llm_common_llm_common_reg_reg_tx_next_tsn_4_axb_10 ( + .I0(com_lnk_ttrans_seq[10]), + .I1(plm_link_up_2), + .LO(com_llm_llm_common_llm_common_reg_reg_tx_next_tsn_4_axb_10_2006) + ); + defparam com_llm_llm_common_llm_common_reg_reg_tx_next_tsn_4_axb_9.INIT = 4'h8; + LUT2_L com_llm_llm_common_llm_common_reg_reg_tx_next_tsn_4_axb_9 ( + .I0(com_lnk_ttrans_seq[9]), + .I1(plm_link_up_2), + .LO(com_llm_llm_common_llm_common_reg_reg_tx_next_tsn_4_axb_9_2007) + ); + defparam com_llm_llm_common_llm_common_reg_reg_tx_next_tsn_4_axb_8.INIT = 4'h8; + LUT2_L com_llm_llm_common_llm_common_reg_reg_tx_next_tsn_4_axb_8 ( + .I0(com_lnk_ttrans_seq[8]), + .I1(plm_link_up_2), + .LO(com_llm_llm_common_llm_common_reg_reg_tx_next_tsn_4_axb_8_2008) + ); + defparam com_llm_llm_common_llm_common_reg_reg_tx_next_tsn_4_axb_7.INIT = 4'h8; + LUT2_L com_llm_llm_common_llm_common_reg_reg_tx_next_tsn_4_axb_7 ( + .I0(com_lnk_ttrans_seq[7]), + .I1(plm_link_up_2), + .LO(com_llm_llm_common_llm_common_reg_reg_tx_next_tsn_4_axb_7_2009) + ); + defparam com_llm_llm_common_llm_common_reg_reg_tx_next_tsn_4_axb_6.INIT = 4'h8; + LUT2_L com_llm_llm_common_llm_common_reg_reg_tx_next_tsn_4_axb_6 ( + .I0(com_lnk_ttrans_seq[6]), + .I1(plm_link_up_2), + .LO(com_llm_llm_common_llm_common_reg_reg_tx_next_tsn_4_axb_6_2010) + ); + defparam com_llm_llm_common_llm_common_reg_reg_tx_next_tsn_4_axb_5.INIT = 4'h8; + LUT2_L com_llm_llm_common_llm_common_reg_reg_tx_next_tsn_4_axb_5 ( + .I0(com_lnk_ttrans_seq[5]), + .I1(plm_link_up_2), + .LO(com_llm_llm_common_llm_common_reg_reg_tx_next_tsn_4_axb_5_2011) + ); + defparam com_llm_llm_common_llm_common_reg_reg_tx_next_tsn_4_axb_4.INIT = 4'h8; + LUT2_L com_llm_llm_common_llm_common_reg_reg_tx_next_tsn_4_axb_4 ( + .I0(com_lnk_ttrans_seq[4]), + .I1(plm_link_up_2), + .LO(com_llm_llm_common_llm_common_reg_reg_tx_next_tsn_4_axb_4_2012) + ); + defparam com_llm_llm_common_llm_common_reg_reg_tx_next_tsn_4_axb_3.INIT = 4'h8; + LUT2_L com_llm_llm_common_llm_common_reg_reg_tx_next_tsn_4_axb_3 ( + .I0(com_lnk_ttrans_seq[3]), + .I1(plm_link_up_2), + .LO(com_llm_llm_common_llm_common_reg_reg_tx_next_tsn_4_axb_3_2013) + ); + defparam com_llm_llm_common_llm_common_reg_reg_tx_next_tsn_4_axb_2.INIT = 4'h8; + LUT2_L com_llm_llm_common_llm_common_reg_reg_tx_next_tsn_4_axb_2 ( + .I0(com_lnk_ttrans_seq[2]), + .I1(plm_link_up_2), + .LO(com_llm_llm_common_llm_common_reg_reg_tx_next_tsn_4_axb_2_2014) + ); + defparam com_llm_llm_common_llm_common_reg_reg_tx_next_tsn_4_axb_1.INIT = 4'h8; + LUT2_L com_llm_llm_common_llm_common_reg_reg_tx_next_tsn_4_axb_1 ( + .I0(com_lnk_ttrans_seq[1]), + .I1(plm_link_up_2), + .LO(com_llm_llm_common_llm_common_reg_reg_tx_next_tsn_4_axb_1_2015) + ); + defparam com_llm_llm_common_llm_common_reg_reg_dllr_in_progress17_0_a2_0_a2_0_a2.INIT = 4'h1; + LUT2_L com_llm_llm_common_llm_common_reg_reg_dllr_in_progress17_0_a2_0_a2_0_a2 ( + .I0(com_llm_reg_rx_tlp_tsn_err_0_a2_0_a2_0_a2_0_a4), + .I1(com_llm_link_status_0_), + .LO(com_llm_llm_common_llm_common_reg_reg_dllr_in_progress17) + ); + defparam com_llm_llm_common_llm_common_reg_N_42823_i.INIT = 4'hB; + LUT2_L com_llm_llm_common_llm_common_reg_N_42823_i ( + .I0(com_lnk_ttrans_seq[11]), + .I1(plm_link_up_2), + .LO(com_llm_llm_common_llm_common_reg_N_42823_i_2016) + ); + defparam com_llm_llm_common_llm_common_reg_N_42824_i.INIT = 4'hB; + LUT2_L com_llm_llm_common_llm_common_reg_N_42824_i ( + .I0(com_lnk_ttrans_seq[10]), + .I1(plm_link_up_2), + .LO(com_llm_llm_common_llm_common_reg_N_42824_i_2017) + ); + defparam com_llm_llm_common_llm_common_reg_N_42825_i.INIT = 4'hB; + LUT2_L com_llm_llm_common_llm_common_reg_N_42825_i ( + .I0(com_lnk_ttrans_seq[9]), + .I1(plm_link_up_2), + .LO(com_llm_llm_common_llm_common_reg_N_42825_i_2018) + ); + defparam com_llm_llm_common_llm_common_reg_N_42826_i.INIT = 4'hB; + LUT2_L com_llm_llm_common_llm_common_reg_N_42826_i ( + .I0(com_lnk_ttrans_seq[8]), + .I1(plm_link_up_2), + .LO(com_llm_llm_common_llm_common_reg_N_42826_i_2019) + ); + defparam com_llm_llm_common_llm_common_reg_N_42827_i.INIT = 4'hB; + LUT2_L com_llm_llm_common_llm_common_reg_N_42827_i ( + .I0(com_lnk_ttrans_seq[7]), + .I1(plm_link_up_2), + .LO(com_llm_llm_common_llm_common_reg_N_42827_i_2020) + ); + defparam com_llm_llm_common_llm_common_reg_N_42828_i.INIT = 4'hB; + LUT2_L com_llm_llm_common_llm_common_reg_N_42828_i ( + .I0(com_lnk_ttrans_seq[6]), + .I1(plm_link_up_2), + .LO(com_llm_llm_common_llm_common_reg_N_42828_i_2021) + ); + defparam com_llm_llm_common_llm_common_reg_N_42829_i.INIT = 4'hB; + LUT2_L com_llm_llm_common_llm_common_reg_N_42829_i ( + .I0(com_lnk_ttrans_seq[5]), + .I1(plm_link_up_2), + .LO(com_llm_llm_common_llm_common_reg_N_42829_i_2022) + ); + defparam com_llm_llm_common_llm_common_reg_N_42830_i.INIT = 4'hB; + LUT2_L com_llm_llm_common_llm_common_reg_N_42830_i ( + .I0(com_lnk_ttrans_seq[4]), + .I1(plm_link_up_2), + .LO(com_llm_llm_common_llm_common_reg_N_42830_i_2023) + ); + defparam com_llm_llm_common_llm_common_reg_N_42831_i.INIT = 4'hB; + LUT2_L com_llm_llm_common_llm_common_reg_N_42831_i ( + .I0(com_lnk_ttrans_seq[3]), + .I1(plm_link_up_2), + .LO(com_llm_llm_common_llm_common_reg_N_42831_i_2024) + ); + defparam com_llm_llm_common_llm_common_reg_N_42832_i.INIT = 4'hB; + LUT2_L com_llm_llm_common_llm_common_reg_N_42832_i ( + .I0(com_lnk_ttrans_seq[2]), + .I1(plm_link_up_2), + .LO(com_llm_llm_common_llm_common_reg_N_42832_i_2025) + ); + defparam com_llm_llm_common_llm_common_reg_N_42833_i.INIT = 4'hB; + LUT2_L com_llm_llm_common_llm_common_reg_N_42833_i ( + .I0(com_lnk_ttrans_seq[1]), + .I1(plm_link_up_2), + .LO(com_llm_llm_common_llm_common_reg_N_42833_i_2026) + ); + defparam com_llm_llm_common_llm_common_reg_N_42834_i.INIT = 4'hB; + LUT2_L com_llm_llm_common_llm_common_reg_N_42834_i ( + .I0(com_lnk_ttrans_seq[0]), + .I1(plm_link_up_2), + .LO(com_llm_llm_common_llm_common_reg_N_42834_i_2027) + ); + defparam com_llm_llm_common_llm_common_reg_N_42799_i.INIT = 4'hE; + LUT2_L com_llm_llm_common_llm_common_reg_N_42799_i ( + .I0(com_llm_link_status_0_), + .I1(com_llm_reg_next_rcv_tsn[11]), + .LO(com_llm_llm_common_llm_common_reg_N_42799_i_2043) + ); + defparam com_llm_llm_common_llm_common_reg_N_42800_i.INIT = 4'hE; + LUT2_L com_llm_llm_common_llm_common_reg_N_42800_i ( + .I0(com_llm_link_status_0_), + .I1(com_llm_reg_next_rcv_tsn[10]), + .LO(com_llm_llm_common_llm_common_reg_N_42800_i_2044) + ); + defparam com_llm_llm_common_llm_common_reg_N_42801_i.INIT = 4'hE; + LUT2_L com_llm_llm_common_llm_common_reg_N_42801_i ( + .I0(com_llm_link_status_0_), + .I1(com_llm_reg_next_rcv_tsn[9]), + .LO(com_llm_llm_common_llm_common_reg_N_42801_i_2045) + ); + defparam com_llm_llm_common_llm_common_reg_N_42802_i.INIT = 4'hE; + LUT2_L com_llm_llm_common_llm_common_reg_N_42802_i ( + .I0(com_llm_link_status_0_), + .I1(com_llm_reg_next_rcv_tsn[8]), + .LO(com_llm_llm_common_llm_common_reg_N_42802_i_2046) + ); + defparam com_llm_llm_common_llm_common_reg_N_42803_i.INIT = 4'hE; + LUT2_L com_llm_llm_common_llm_common_reg_N_42803_i ( + .I0(com_llm_link_status_0_), + .I1(com_llm_reg_next_rcv_tsn[7]), + .LO(com_llm_llm_common_llm_common_reg_N_42803_i_2047) + ); + defparam com_llm_llm_common_llm_common_reg_N_42804_i.INIT = 4'hE; + LUT2_L com_llm_llm_common_llm_common_reg_N_42804_i ( + .I0(com_llm_link_status_0_), + .I1(com_llm_reg_next_rcv_tsn[6]), + .LO(com_llm_llm_common_llm_common_reg_N_42804_i_2048) + ); + defparam com_llm_llm_common_llm_common_reg_N_42805_i.INIT = 4'hE; + LUT2_L com_llm_llm_common_llm_common_reg_N_42805_i ( + .I0(com_llm_link_status_0_), + .I1(com_llm_reg_next_rcv_tsn[5]), + .LO(com_llm_llm_common_llm_common_reg_N_42805_i_2049) + ); + defparam com_llm_llm_common_llm_common_reg_N_42806_i.INIT = 4'hE; + LUT2_L com_llm_llm_common_llm_common_reg_N_42806_i ( + .I0(com_llm_link_status_0_), + .I1(com_llm_reg_next_rcv_tsn[4]), + .LO(com_llm_llm_common_llm_common_reg_N_42806_i_2050) + ); + defparam com_llm_llm_common_llm_common_reg_N_42807_i.INIT = 4'hE; + LUT2_L com_llm_llm_common_llm_common_reg_N_42807_i ( + .I0(com_llm_link_status_0_), + .I1(com_llm_reg_next_rcv_tsn[3]), + .LO(com_llm_llm_common_llm_common_reg_N_42807_i_2051) + ); + defparam com_llm_llm_common_llm_common_reg_N_42808_i.INIT = 4'hE; + LUT2_L com_llm_llm_common_llm_common_reg_N_42808_i ( + .I0(com_llm_link_status_0_), + .I1(com_llm_reg_next_rcv_tsn[2]), + .LO(com_llm_llm_common_llm_common_reg_N_42808_i_2052) + ); + defparam com_llm_llm_common_llm_common_reg_N_42809_i.INIT = 4'hE; + LUT2_L com_llm_llm_common_llm_common_reg_N_42809_i ( + .I0(com_llm_link_status_0_), + .I1(com_llm_reg_next_rcv_tsn[1]), + .LO(com_llm_llm_common_llm_common_reg_N_42809_i_2053) + ); + defparam com_llm_llm_common_llm_common_reg_N_42810_i.INIT = 4'hE; + LUT2_L com_llm_llm_common_llm_common_reg_N_42810_i ( + .I0(com_llm_link_status_0_), + .I1(com_llm_reg_next_rcv_tsn[0]), + .LO(com_llm_llm_common_llm_common_reg_N_42810_i_2054) + ); + defparam com_llm_llm_common_llm_common_reg_reg_tx_dllp_ack_vld18_0_a2_0_a2_0_a4.INIT = 8'h08; + LUT3_L com_llm_llm_common_llm_common_reg_reg_tx_dllp_ack_vld18_0_a2_0_a2_0_a4 ( + .I0(com_llm_llm_common_llm_common_reg_N_30966_1), + .I1(com_llm_reg_rx_tlp_tsn_err_0_a2_0_a2_0_a2_0_a4), + .I2(com_llm_reg_rx_tlp_tsn_dup), + .LO(com_llm_llm_common_llm_common_reg_reg_tx_dllp_ack_vld18) + ); + defparam com_llm_llm_common_llm_common_reg_reg_tx_dllp_dup_vld18_i_0.INIT = 16'h0400; + LUT4_L com_llm_llm_common_llm_common_reg_reg_tx_dllp_dup_vld18_i_0 ( + .I0(com_llm_llm_common_llm_common_reg_N_30966_1), + .I1(com_llm_reg_rx_tlp_tsn_err_0_a2_0_a2_0_a2_0_a4), + .I2(com_llm_reg_dllr_in_progress), + .I3(com_llm_reg_rx_tlp_tsn_dup), + .LO(com_llm_llm_common_llm_common_reg_N_12552_i) + ); + defparam com_llm_llm_common_llm_common_reg_replay_ip21_0_a2_0_a2_0_a4.INIT = 4'h2; + LUT2_L com_llm_llm_common_llm_common_reg_replay_ip21_0_a2_0_a2_0_a4 ( + .I0(com_llm_llm_common_llm_common_reg_N_38751), + .I1(com_llm_link_status_0_), + .LO(com_llm_llm_common_llm_common_reg_replay_ip21) + ); + defparam com_llm_llm_common_llm_common_reg_N_42811_i.INIT = 4'hE; + LUT2_L com_llm_llm_common_llm_common_reg_N_42811_i ( + .I0(com_llm_link_status_0_), + .I1(com_lnk_ttrans_seq[11]), + .LO(com_llm_llm_common_llm_common_reg_N_42811_i_2059) + ); + defparam com_llm_llm_common_llm_common_reg_N_42812_i.INIT = 4'hE; + LUT2_L com_llm_llm_common_llm_common_reg_N_42812_i ( + .I0(com_llm_link_status_0_), + .I1(com_lnk_ttrans_seq[10]), + .LO(com_llm_llm_common_llm_common_reg_N_42812_i_2060) + ); + defparam com_llm_llm_common_llm_common_reg_N_42813_i.INIT = 4'hE; + LUT2_L com_llm_llm_common_llm_common_reg_N_42813_i ( + .I0(com_llm_link_status_0_), + .I1(com_lnk_ttrans_seq[9]), + .LO(com_llm_llm_common_llm_common_reg_N_42813_i_2061) + ); + defparam com_llm_llm_common_llm_common_reg_N_42814_i.INIT = 4'hE; + LUT2_L com_llm_llm_common_llm_common_reg_N_42814_i ( + .I0(com_llm_link_status_0_), + .I1(com_lnk_ttrans_seq[8]), + .LO(com_llm_llm_common_llm_common_reg_N_42814_i_2062) + ); + defparam com_llm_llm_common_llm_common_reg_N_42815_i.INIT = 4'hE; + LUT2_L com_llm_llm_common_llm_common_reg_N_42815_i ( + .I0(com_llm_link_status_0_), + .I1(com_lnk_ttrans_seq[7]), + .LO(com_llm_llm_common_llm_common_reg_N_42815_i_2063) + ); + defparam com_llm_llm_common_llm_common_reg_N_42816_i.INIT = 4'hE; + LUT2_L com_llm_llm_common_llm_common_reg_N_42816_i ( + .I0(com_llm_link_status_0_), + .I1(com_lnk_ttrans_seq[6]), + .LO(com_llm_llm_common_llm_common_reg_N_42816_i_2064) + ); + defparam com_llm_llm_common_llm_common_reg_N_42817_i.INIT = 4'hE; + LUT2_L com_llm_llm_common_llm_common_reg_N_42817_i ( + .I0(com_llm_link_status_0_), + .I1(com_lnk_ttrans_seq[5]), + .LO(com_llm_llm_common_llm_common_reg_N_42817_i_2065) + ); + defparam com_llm_llm_common_llm_common_reg_N_42818_i.INIT = 4'hE; + LUT2_L com_llm_llm_common_llm_common_reg_N_42818_i ( + .I0(com_llm_link_status_0_), + .I1(com_lnk_ttrans_seq[4]), + .LO(com_llm_llm_common_llm_common_reg_N_42818_i_2066) + ); + defparam com_llm_llm_common_llm_common_reg_N_42819_i.INIT = 4'hE; + LUT2_L com_llm_llm_common_llm_common_reg_N_42819_i ( + .I0(com_llm_link_status_0_), + .I1(com_lnk_ttrans_seq[3]), + .LO(com_llm_llm_common_llm_common_reg_N_42819_i_2067) + ); + defparam com_llm_llm_common_llm_common_reg_N_42820_i.INIT = 4'hE; + LUT2_L com_llm_llm_common_llm_common_reg_N_42820_i ( + .I0(com_llm_link_status_0_), + .I1(com_lnk_ttrans_seq[2]), + .LO(com_llm_llm_common_llm_common_reg_N_42820_i_2068) + ); + defparam com_llm_llm_common_llm_common_reg_N_42821_i.INIT = 4'hE; + LUT2_L com_llm_llm_common_llm_common_reg_N_42821_i ( + .I0(com_llm_link_status_0_), + .I1(com_lnk_ttrans_seq[1]), + .LO(com_llm_llm_common_llm_common_reg_N_42821_i_2069) + ); + defparam com_llm_llm_common_llm_common_reg_N_42822_i.INIT = 4'hE; + LUT2_L com_llm_llm_common_llm_common_reg_N_42822_i ( + .I0(com_llm_link_status_0_), + .I1(com_lnk_ttrans_seq[0]), + .LO(com_llm_llm_common_llm_common_reg_N_42822_i_2071) + ); + defparam com_llm_llm_common_llm_common_reg_N_42835_i.INIT = 4'hE; + LUT2_L com_llm_llm_common_llm_common_reg_N_42835_i ( + .I0(com_llm_link_status_0_), + .I1(com_llm_llm_common_llm_common_reg_reg_rx_dllp_tsn_q[11]), + .LO(com_llm_llm_common_llm_common_reg_N_42835_i_2072) + ); + defparam com_llm_llm_common_llm_common_reg_N_42836_i.INIT = 4'hE; + LUT2_L com_llm_llm_common_llm_common_reg_N_42836_i ( + .I0(com_llm_link_status_0_), + .I1(com_llm_llm_common_llm_common_reg_reg_rx_dllp_tsn_q[10]), + .LO(com_llm_llm_common_llm_common_reg_N_42836_i_2073) + ); + defparam com_llm_llm_common_llm_common_reg_N_42837_i.INIT = 4'hE; + LUT2_L com_llm_llm_common_llm_common_reg_N_42837_i ( + .I0(com_llm_link_status_0_), + .I1(com_llm_llm_common_llm_common_reg_reg_rx_dllp_tsn_q[9]), + .LO(com_llm_llm_common_llm_common_reg_N_42837_i_2074) + ); + defparam com_llm_llm_common_llm_common_reg_N_42838_i.INIT = 4'hE; + LUT2_L com_llm_llm_common_llm_common_reg_N_42838_i ( + .I0(com_llm_link_status_0_), + .I1(com_llm_llm_common_llm_common_reg_reg_rx_dllp_tsn_q[8]), + .LO(com_llm_llm_common_llm_common_reg_N_42838_i_2075) + ); + defparam com_llm_llm_common_llm_common_reg_N_42839_i.INIT = 4'hE; + LUT2_L com_llm_llm_common_llm_common_reg_N_42839_i ( + .I0(com_llm_link_status_0_), + .I1(com_llm_llm_common_llm_common_reg_reg_rx_dllp_tsn_q[7]), + .LO(com_llm_llm_common_llm_common_reg_N_42839_i_2076) + ); + defparam com_llm_llm_common_llm_common_reg_N_42840_i.INIT = 4'hE; + LUT2_L com_llm_llm_common_llm_common_reg_N_42840_i ( + .I0(com_llm_link_status_0_), + .I1(com_llm_llm_common_llm_common_reg_reg_rx_dllp_tsn_q[6]), + .LO(com_llm_llm_common_llm_common_reg_N_42840_i_2077) + ); + defparam com_llm_llm_common_llm_common_reg_N_42841_i.INIT = 4'hE; + LUT2_L com_llm_llm_common_llm_common_reg_N_42841_i ( + .I0(com_llm_link_status_0_), + .I1(com_llm_llm_common_llm_common_reg_reg_rx_dllp_tsn_q[5]), + .LO(com_llm_llm_common_llm_common_reg_N_42841_i_2078) + ); + defparam com_llm_llm_common_llm_common_reg_N_42842_i.INIT = 4'hE; + LUT2_L com_llm_llm_common_llm_common_reg_N_42842_i ( + .I0(com_llm_link_status_0_), + .I1(com_llm_llm_common_llm_common_reg_reg_rx_dllp_tsn_q[4]), + .LO(com_llm_llm_common_llm_common_reg_N_42842_i_2079) + ); + defparam com_llm_llm_common_llm_common_reg_N_42843_i.INIT = 4'hE; + LUT2_L com_llm_llm_common_llm_common_reg_N_42843_i ( + .I0(com_llm_link_status_0_), + .I1(com_llm_llm_common_llm_common_reg_reg_rx_dllp_tsn_q[3]), + .LO(com_llm_llm_common_llm_common_reg_N_42843_i_2080) + ); + defparam com_llm_llm_common_llm_common_reg_N_42844_i.INIT = 4'hE; + LUT2_L com_llm_llm_common_llm_common_reg_N_42844_i ( + .I0(com_llm_link_status_0_), + .I1(com_llm_llm_common_llm_common_reg_reg_rx_dllp_tsn_q[2]), + .LO(com_llm_llm_common_llm_common_reg_N_42844_i_2081) + ); + defparam com_llm_llm_common_llm_common_reg_N_42845_i.INIT = 4'hE; + LUT2_L com_llm_llm_common_llm_common_reg_N_42845_i ( + .I0(com_llm_link_status_0_), + .I1(com_llm_llm_common_llm_common_reg_reg_rx_dllp_tsn_q[1]), + .LO(com_llm_llm_common_llm_common_reg_N_42845_i_2082) + ); + defparam com_llm_llm_common_llm_common_reg_N_42846_i.INIT = 4'hE; + LUT2_L com_llm_llm_common_llm_common_reg_N_42846_i ( + .I0(com_llm_link_status_0_), + .I1(com_llm_llm_common_llm_common_reg_reg_rx_dllp_tsn_q[0]), + .LO(com_llm_llm_common_llm_common_reg_N_42846_i_2084) + ); + MUXCY com_llm_llm_common_llm_common_reg_curr_eq_mark_q_3_0_I_19 ( + .CI(com_llm_llm_common_llm_common_reg_data_tmp_2[4]), + .DI(com_llm_llm_common_llm_common_reg_GND_2028), + .O(com_llm_llm_common_llm_common_reg_curr_eq_mark_q_3), + .S(com_llm_llm_common_llm_common_reg_N_27) + ); + MUXCY com_llm_llm_common_llm_common_reg_next_eq_mark_q_3_0_I_19 ( + .CI(com_llm_llm_common_llm_common_reg_data_tmp_1[4]), + .DI(com_llm_llm_common_llm_common_reg_GND_2028), + .O(com_llm_llm_common_llm_common_reg_next_eq_mark_q_3), + .S(com_llm_llm_common_llm_common_reg_N_27_0) + ); + MUXCY com_llm_llm_common_llm_common_reg_rx_tsn_eq_sent_tsn_3_0_I_19 ( + .CI(com_llm_llm_common_llm_common_reg_data_tmp_0[4]), + .DI(com_llm_llm_common_llm_common_reg_GND_2028), + .O(com_llm_llm_common_llm_common_reg_rx_tsn_eq_sent_tsn_3), + .S(com_llm_llm_common_llm_common_reg_N_27_1) + ); + MUXCY com_llm_llm_common_llm_common_reg_ANSeqNum_Eq_AckdSeq_wire_0_I_19 ( + .CI(com_llm_llm_common_llm_common_reg_data_tmp[4]), + .DI(com_llm_llm_common_llm_common_reg_GND_2028), + .O(com_llm_llm_common_llm_common_reg_ANSeqNum_Eq_AckdSeq_wire), + .S(com_llm_llm_common_llm_common_reg_N_27_2) + ); + FDC com_llm_llm_common_llm_common_reg_NxtTxTSN_ANSeqNum_wire ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_common_llm_common_reg_result_i_0[11]), + .Q(com_llm_llm_common_llm_common_reg_NxtTxTSN_ANSeqNum_wire_2029), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_common_llm_common_reg_ANSeqNum_AckdSeq_wire ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_common_llm_common_reg_result_i[11]), + .Q(com_llm_llm_common_llm_common_reg_ANSeqNum_AckdSeq_wire_2030), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_common_llm_common_reg_reg_tx_update_clr_q ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_lnk_tretry), + .Q(com_llm_llm_common_llm_common_reg_reg_tx_update_clr_q_2031), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_common_llm_common_reg_reg_rx_dllp_nak_vld_q ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_reg_rx_dllp_nak_vld), + .Q(com_llm_llm_common_llm_common_reg_reg_rx_dllp_nak_vld_q_2032), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_common_llm_common_reg_reg_rx_dllp_ack_vld_q ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_reg_rx_dllp_ack_vld), + .Q(com_llm_llm_common_llm_common_reg_reg_rx_dllp_ack_vld_q_2033), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_common_llm_common_reg_next_eq_mark_q ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_common_llm_common_reg_next_eq_mark_q_3), + .Q(com_llm_llm_common_llm_common_reg_next_eq_mark_q_2034), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_common_llm_common_reg_curr_eq_mark_q ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_common_llm_common_reg_curr_eq_mark_q_3), + .Q(com_llm_llm_common_llm_common_reg_curr_eq_mark_q_2035), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_common_llm_common_reg_rx_tsn_eq_sent_tsn ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_common_llm_common_reg_rx_tsn_eq_sent_tsn_3), + .Q(com_llm_llm_common_llm_common_reg_rx_tsn_eq_sent_tsn_2036), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_common_llm_common_reg_ttrans_st_hiwater_11_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_common_llm_common_reg_un3_ttrans_st_hiwater_s_11_2037), + .Q(com_llm_llm_common_llm_common_reg_ttrans_st_hiwater[11]), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_common_llm_common_reg_tmp_result_11_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_common_llm_common_reg_un3_tmp_result_s_11_2038), + .Q(com_llm_llm_common_llm_common_reg_tmp_result[11]), + .CLR(plm_link_up_i) + ); + FDP com_llm_llm_common_llm_common_reg_rx_dllp_range_err_n ( + .PRE(plm_link_up_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_common_llm_common_reg_N_67867_i_2039), + .Q(com_llm_rx_dllp_range_err_n) + ); + FDC com_llm_llm_common_llm_common_reg_ANSeqNum_Eq_AckdSeq ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_common_llm_common_reg_ANSeqNum_Eq_AckdSeq_5), + .Q(com_llm_llm_common_llm_common_reg_ANSeqNum_Eq_AckdSeq_2040), + .CLR(plm_link_up_i) + ); + FD com_llm_llm_common_llm_common_reg_reg_tx_next_tsn_11_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_common_llm_common_reg_reg_tx_next_tsn_4[11]), + .Q(com_llm_llm_common_llm_common_reg_reg_tx_next_tsn[11]) + ); + FD com_llm_llm_common_llm_common_reg_reg_tx_next_tsn_10_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_common_llm_common_reg_reg_tx_next_tsn_4[10]), + .Q(com_llm_llm_common_llm_common_reg_reg_tx_next_tsn[10]) + ); + FD com_llm_llm_common_llm_common_reg_reg_tx_next_tsn_9_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_common_llm_common_reg_reg_tx_next_tsn_4[9]), + .Q(com_llm_llm_common_llm_common_reg_reg_tx_next_tsn[9]) + ); + FD com_llm_llm_common_llm_common_reg_reg_tx_next_tsn_8_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_common_llm_common_reg_reg_tx_next_tsn_4[8]), + .Q(com_llm_llm_common_llm_common_reg_reg_tx_next_tsn[8]) + ); + FD com_llm_llm_common_llm_common_reg_reg_tx_next_tsn_7_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_common_llm_common_reg_reg_tx_next_tsn_4[7]), + .Q(com_llm_llm_common_llm_common_reg_reg_tx_next_tsn[7]) + ); + FD com_llm_llm_common_llm_common_reg_reg_tx_next_tsn_6_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_common_llm_common_reg_reg_tx_next_tsn_4[6]), + .Q(com_llm_llm_common_llm_common_reg_reg_tx_next_tsn[6]) + ); + FD com_llm_llm_common_llm_common_reg_reg_tx_next_tsn_5_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_common_llm_common_reg_reg_tx_next_tsn_4[5]), + .Q(com_llm_llm_common_llm_common_reg_reg_tx_next_tsn[5]) + ); + FD com_llm_llm_common_llm_common_reg_reg_tx_next_tsn_4_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_common_llm_common_reg_reg_tx_next_tsn_4[4]), + .Q(com_llm_llm_common_llm_common_reg_reg_tx_next_tsn[4]) + ); + FD com_llm_llm_common_llm_common_reg_reg_tx_next_tsn_3_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_common_llm_common_reg_reg_tx_next_tsn_4[3]), + .Q(com_llm_llm_common_llm_common_reg_reg_tx_next_tsn[3]) + ); + FD com_llm_llm_common_llm_common_reg_reg_tx_next_tsn_2_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_common_llm_common_reg_reg_tx_next_tsn_4[2]), + .Q(com_llm_llm_common_llm_common_reg_reg_tx_next_tsn[2]) + ); + FD com_llm_llm_common_llm_common_reg_reg_tx_next_tsn_1_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_common_llm_common_reg_reg_tx_next_tsn_4[1]), + .Q(com_llm_llm_common_llm_common_reg_reg_tx_next_tsn[1]) + ); + FDC com_llm_llm_common_llm_common_reg_reg_rx_dllp_tsn_q_11_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_reg_rx_dllp_tsn[11]), + .Q(com_llm_llm_common_llm_common_reg_reg_rx_dllp_tsn_q[11]), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_common_llm_common_reg_reg_rx_dllp_tsn_q_10_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_reg_rx_dllp_tsn[10]), + .Q(com_llm_llm_common_llm_common_reg_reg_rx_dllp_tsn_q[10]), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_common_llm_common_reg_reg_rx_dllp_tsn_q_9_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_reg_rx_dllp_tsn[9]), + .Q(com_llm_llm_common_llm_common_reg_reg_rx_dllp_tsn_q[9]), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_common_llm_common_reg_reg_rx_dllp_tsn_q_8_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_reg_rx_dllp_tsn[8]), + .Q(com_llm_llm_common_llm_common_reg_reg_rx_dllp_tsn_q[8]), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_common_llm_common_reg_reg_rx_dllp_tsn_q_7_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_reg_rx_dllp_tsn[7]), + .Q(com_llm_llm_common_llm_common_reg_reg_rx_dllp_tsn_q[7]), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_common_llm_common_reg_reg_rx_dllp_tsn_q_6_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_reg_rx_dllp_tsn[6]), + .Q(com_llm_llm_common_llm_common_reg_reg_rx_dllp_tsn_q[6]), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_common_llm_common_reg_reg_rx_dllp_tsn_q_5_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_reg_rx_dllp_tsn[5]), + .Q(com_llm_llm_common_llm_common_reg_reg_rx_dllp_tsn_q[5]), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_common_llm_common_reg_reg_rx_dllp_tsn_q_4_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_reg_rx_dllp_tsn[4]), + .Q(com_llm_llm_common_llm_common_reg_reg_rx_dllp_tsn_q[4]), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_common_llm_common_reg_reg_rx_dllp_tsn_q_3_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_reg_rx_dllp_tsn[3]), + .Q(com_llm_llm_common_llm_common_reg_reg_rx_dllp_tsn_q[3]), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_common_llm_common_reg_reg_rx_dllp_tsn_q_2_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_reg_rx_dllp_tsn[2]), + .Q(com_llm_llm_common_llm_common_reg_reg_rx_dllp_tsn_q[2]), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_common_llm_common_reg_reg_rx_dllp_tsn_q_1_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_reg_rx_dllp_tsn[1]), + .Q(com_llm_llm_common_llm_common_reg_reg_rx_dllp_tsn_q[1]), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_common_llm_common_reg_reg_rx_dllp_tsn_q_0_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_reg_rx_dllp_tsn[0]), + .Q(com_llm_llm_common_llm_common_reg_reg_rx_dllp_tsn_q[0]), + .CLR(plm_link_up_i) + ); + FDCE com_llm_llm_common_llm_common_reg_reg_tx_dllp_nak_vld ( + .CE(com_llm_llm_common_llm_common_reg_N_69070_i_2041), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_N_51406_i), + .Q(com_llm_reg_tx_dllp_nak_vld), + .CLR(plm_link_up_i) + ); + FDCE com_llm_llm_common_llm_common_reg_reg_dllr_in_progress ( + .CE(com_llm_llm_common_llm_common_reg_N_67883_i_2042), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_common_llm_common_reg_reg_dllr_in_progress17), + .Q(com_llm_reg_dllr_in_progress), + .CLR(plm_link_up_i) + ); + FDPE com_llm_llm_common_llm_common_reg_reg_tx_dllp_tsn_11_ ( + .PRE(plm_link_up_i), + .CE(com_llm_llm_common_llm_common_reg_N_69071_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_common_llm_common_reg_N_42799_i_2043), + .Q(com_llm_reg_tx_dllp_tsn[11]) + ); + FDPE com_llm_llm_common_llm_common_reg_reg_tx_dllp_tsn_10_ ( + .PRE(plm_link_up_i), + .CE(com_llm_llm_common_llm_common_reg_N_69071_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_common_llm_common_reg_N_42800_i_2044), + .Q(com_llm_reg_tx_dllp_tsn[10]) + ); + FDPE com_llm_llm_common_llm_common_reg_reg_tx_dllp_tsn_9_ ( + .PRE(plm_link_up_i), + .CE(com_llm_llm_common_llm_common_reg_N_69071_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_common_llm_common_reg_N_42801_i_2045), + .Q(com_llm_reg_tx_dllp_tsn[9]) + ); + FDPE com_llm_llm_common_llm_common_reg_reg_tx_dllp_tsn_8_ ( + .PRE(plm_link_up_i), + .CE(com_llm_llm_common_llm_common_reg_N_69071_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_common_llm_common_reg_N_42802_i_2046), + .Q(com_llm_reg_tx_dllp_tsn[8]) + ); + FDPE com_llm_llm_common_llm_common_reg_reg_tx_dllp_tsn_7_ ( + .PRE(plm_link_up_i), + .CE(com_llm_llm_common_llm_common_reg_N_69071_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_common_llm_common_reg_N_42803_i_2047), + .Q(com_llm_reg_tx_dllp_tsn[7]) + ); + FDPE com_llm_llm_common_llm_common_reg_reg_tx_dllp_tsn_6_ ( + .PRE(plm_link_up_i), + .CE(com_llm_llm_common_llm_common_reg_N_69071_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_common_llm_common_reg_N_42804_i_2048), + .Q(com_llm_reg_tx_dllp_tsn[6]) + ); + FDPE com_llm_llm_common_llm_common_reg_reg_tx_dllp_tsn_5_ ( + .PRE(plm_link_up_i), + .CE(com_llm_llm_common_llm_common_reg_N_69071_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_common_llm_common_reg_N_42805_i_2049), + .Q(com_llm_reg_tx_dllp_tsn[5]) + ); + FDPE com_llm_llm_common_llm_common_reg_reg_tx_dllp_tsn_4_ ( + .PRE(plm_link_up_i), + .CE(com_llm_llm_common_llm_common_reg_N_69071_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_common_llm_common_reg_N_42806_i_2050), + .Q(com_llm_reg_tx_dllp_tsn[4]) + ); + FDPE com_llm_llm_common_llm_common_reg_reg_tx_dllp_tsn_3_ ( + .PRE(plm_link_up_i), + .CE(com_llm_llm_common_llm_common_reg_N_69071_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_common_llm_common_reg_N_42807_i_2051), + .Q(com_llm_reg_tx_dllp_tsn[3]) + ); + FDPE com_llm_llm_common_llm_common_reg_reg_tx_dllp_tsn_2_ ( + .PRE(plm_link_up_i), + .CE(com_llm_llm_common_llm_common_reg_N_69071_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_common_llm_common_reg_N_42808_i_2052), + .Q(com_llm_reg_tx_dllp_tsn[2]) + ); + FDPE com_llm_llm_common_llm_common_reg_reg_tx_dllp_tsn_1_ ( + .PRE(plm_link_up_i), + .CE(com_llm_llm_common_llm_common_reg_N_69071_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_common_llm_common_reg_N_42809_i_2053), + .Q(com_llm_reg_tx_dllp_tsn[1]) + ); + FDPE com_llm_llm_common_llm_common_reg_reg_tx_dllp_tsn_0_ ( + .PRE(plm_link_up_i), + .CE(com_llm_llm_common_llm_common_reg_N_69071_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_common_llm_common_reg_N_42810_i_2054), + .Q(com_llm_reg_tx_dllp_tsn[0]) + ); + FDCE com_llm_llm_common_llm_common_reg_reg_tx_dllp_ack_vld ( + .CE(com_llm_llm_common_llm_common_reg_N_69229_i_2055), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_common_llm_common_reg_reg_tx_dllp_ack_vld18), + .Q(com_llm_reg_tx_dllp_ack_vld), + .CLR(plm_link_up_i) + ); + FDCE com_llm_llm_common_llm_common_reg_reg_tx_dllp_dup_vld ( + .CE(com_llm_llm_common_llm_common_reg_N_69044_i_2056), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_common_llm_common_reg_N_12552_i), + .Q(com_llm_reg_tx_dllp_dup_vld), + .CLR(plm_link_up_i) + ); + FDCE com_llm_llm_common_llm_common_reg_replay_ip ( + .CE(com_llm_llm_common_llm_common_reg_N_67865_i_2057), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_common_llm_common_reg_replay_ip21), + .Q(com_llm_llm_common_llm_common_reg_replay_ip_2058), + .CLR(plm_link_up_i) + ); + FDPE com_llm_llm_common_llm_common_reg_hi_water_mark_11_ ( + .PRE(plm_link_up_i), + .CE(com_llm_llm_common_llm_common_reg_N_69063_i_2070), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_common_llm_common_reg_N_42811_i_2059), + .Q(com_llm_llm_common_llm_common_reg_hi_water_mark[11]) + ); + FDPE com_llm_llm_common_llm_common_reg_hi_water_mark_10_ ( + .PRE(plm_link_up_i), + .CE(com_llm_llm_common_llm_common_reg_N_69063_i_2070), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_common_llm_common_reg_N_42812_i_2060), + .Q(com_llm_llm_common_llm_common_reg_hi_water_mark[10]) + ); + FDPE com_llm_llm_common_llm_common_reg_hi_water_mark_9_ ( + .PRE(plm_link_up_i), + .CE(com_llm_llm_common_llm_common_reg_N_69063_i_2070), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_common_llm_common_reg_N_42813_i_2061), + .Q(com_llm_llm_common_llm_common_reg_hi_water_mark[9]) + ); + FDPE com_llm_llm_common_llm_common_reg_hi_water_mark_8_ ( + .PRE(plm_link_up_i), + .CE(com_llm_llm_common_llm_common_reg_N_69063_i_2070), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_common_llm_common_reg_N_42814_i_2062), + .Q(com_llm_llm_common_llm_common_reg_hi_water_mark[8]) + ); + FDPE com_llm_llm_common_llm_common_reg_hi_water_mark_7_ ( + .PRE(plm_link_up_i), + .CE(com_llm_llm_common_llm_common_reg_N_69063_i_2070), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_common_llm_common_reg_N_42815_i_2063), + .Q(com_llm_llm_common_llm_common_reg_hi_water_mark[7]) + ); + FDPE com_llm_llm_common_llm_common_reg_hi_water_mark_6_ ( + .PRE(plm_link_up_i), + .CE(com_llm_llm_common_llm_common_reg_N_69063_i_2070), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_common_llm_common_reg_N_42816_i_2064), + .Q(com_llm_llm_common_llm_common_reg_hi_water_mark[6]) + ); + FDPE com_llm_llm_common_llm_common_reg_hi_water_mark_5_ ( + .PRE(plm_link_up_i), + .CE(com_llm_llm_common_llm_common_reg_N_69063_i_2070), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_common_llm_common_reg_N_42817_i_2065), + .Q(com_llm_llm_common_llm_common_reg_hi_water_mark[5]) + ); + FDPE com_llm_llm_common_llm_common_reg_hi_water_mark_4_ ( + .PRE(plm_link_up_i), + .CE(com_llm_llm_common_llm_common_reg_N_69063_i_2070), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_common_llm_common_reg_N_42818_i_2066), + .Q(com_llm_llm_common_llm_common_reg_hi_water_mark[4]) + ); + FDPE com_llm_llm_common_llm_common_reg_hi_water_mark_3_ ( + .PRE(plm_link_up_i), + .CE(com_llm_llm_common_llm_common_reg_N_69063_i_2070), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_common_llm_common_reg_N_42819_i_2067), + .Q(com_llm_llm_common_llm_common_reg_hi_water_mark[3]) + ); + FDPE com_llm_llm_common_llm_common_reg_hi_water_mark_2_ ( + .PRE(plm_link_up_i), + .CE(com_llm_llm_common_llm_common_reg_N_69063_i_2070), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_common_llm_common_reg_N_42820_i_2068), + .Q(com_llm_llm_common_llm_common_reg_hi_water_mark[2]) + ); + FDPE com_llm_llm_common_llm_common_reg_hi_water_mark_1_ ( + .PRE(plm_link_up_i), + .CE(com_llm_llm_common_llm_common_reg_N_69063_i_2070), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_common_llm_common_reg_N_42821_i_2069), + .Q(com_llm_llm_common_llm_common_reg_hi_water_mark[1]) + ); + FDPE com_llm_llm_common_llm_common_reg_hi_water_mark_0_ ( + .PRE(plm_link_up_i), + .CE(com_llm_llm_common_llm_common_reg_N_69063_i_2070), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_common_llm_common_reg_N_42822_i_2071), + .Q(com_llm_llm_common_llm_common_reg_hi_water_mark[0]) + ); + FDPE com_llm_llm_common_llm_common_reg_reg_tx_ackd_tsn_11_ ( + .PRE(plm_link_up_i), + .CE(com_llm_llm_common_llm_common_reg_N_69244_i_2083), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_common_llm_common_reg_N_42835_i_2072), + .Q(com_lnk_tupdate_seq[11]) + ); + FDPE com_llm_llm_common_llm_common_reg_reg_tx_ackd_tsn_10_ ( + .PRE(plm_link_up_i), + .CE(com_llm_llm_common_llm_common_reg_N_69244_i_2083), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_common_llm_common_reg_N_42836_i_2073), + .Q(com_lnk_tupdate_seq[10]) + ); + FDPE com_llm_llm_common_llm_common_reg_reg_tx_ackd_tsn_9_ ( + .PRE(plm_link_up_i), + .CE(com_llm_llm_common_llm_common_reg_N_69244_i_2083), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_common_llm_common_reg_N_42837_i_2074), + .Q(com_lnk_tupdate_seq[9]) + ); + FDPE com_llm_llm_common_llm_common_reg_reg_tx_ackd_tsn_8_ ( + .PRE(plm_link_up_i), + .CE(com_llm_llm_common_llm_common_reg_N_69244_i_2083), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_common_llm_common_reg_N_42838_i_2075), + .Q(com_lnk_tupdate_seq[8]) + ); + FDPE com_llm_llm_common_llm_common_reg_reg_tx_ackd_tsn_7_ ( + .PRE(plm_link_up_i), + .CE(com_llm_llm_common_llm_common_reg_N_69244_i_2083), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_common_llm_common_reg_N_42839_i_2076), + .Q(com_lnk_tupdate_seq[7]) + ); + FDPE com_llm_llm_common_llm_common_reg_reg_tx_ackd_tsn_6_ ( + .PRE(plm_link_up_i), + .CE(com_llm_llm_common_llm_common_reg_N_69244_i_2083), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_common_llm_common_reg_N_42840_i_2077), + .Q(com_lnk_tupdate_seq[6]) + ); + FDPE com_llm_llm_common_llm_common_reg_reg_tx_ackd_tsn_5_ ( + .PRE(plm_link_up_i), + .CE(com_llm_llm_common_llm_common_reg_N_69244_i_2083), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_common_llm_common_reg_N_42841_i_2078), + .Q(com_lnk_tupdate_seq[5]) + ); + FDPE com_llm_llm_common_llm_common_reg_reg_tx_ackd_tsn_4_ ( + .PRE(plm_link_up_i), + .CE(com_llm_llm_common_llm_common_reg_N_69244_i_2083), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_common_llm_common_reg_N_42842_i_2079), + .Q(com_lnk_tupdate_seq[4]) + ); + FDPE com_llm_llm_common_llm_common_reg_reg_tx_ackd_tsn_3_ ( + .PRE(plm_link_up_i), + .CE(com_llm_llm_common_llm_common_reg_N_69244_i_2083), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_common_llm_common_reg_N_42843_i_2080), + .Q(com_lnk_tupdate_seq[3]) + ); + FDPE com_llm_llm_common_llm_common_reg_reg_tx_ackd_tsn_2_ ( + .PRE(plm_link_up_i), + .CE(com_llm_llm_common_llm_common_reg_N_69244_i_2083), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_common_llm_common_reg_N_42844_i_2081), + .Q(com_lnk_tupdate_seq[2]) + ); + FDPE com_llm_llm_common_llm_common_reg_reg_tx_ackd_tsn_1_ ( + .PRE(plm_link_up_i), + .CE(com_llm_llm_common_llm_common_reg_N_69244_i_2083), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_common_llm_common_reg_N_42845_i_2082), + .Q(com_lnk_tupdate_seq[1]) + ); + FDPE com_llm_llm_common_llm_common_reg_reg_tx_ackd_tsn_0_ ( + .PRE(plm_link_up_i), + .CE(com_llm_llm_common_llm_common_reg_N_69244_i_2083), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_common_llm_common_reg_N_42846_i_2084), + .Q(com_lnk_tupdate_seq[0]) + ); + defparam com_llm_llm_common_llm_common_reg_ANSeqNum_Eq_AckdSeq_wire_0_I_27.INIT = 16'h8421; + LUT4 com_llm_llm_common_llm_common_reg_ANSeqNum_Eq_AckdSeq_wire_0_I_27 ( + .I0(com_llm_reg_rx_dllp_tsn[10]), + .I1(com_llm_reg_rx_dllp_tsn[11]), + .I2(com_lnk_tupdate_seq[10]), + .I3(com_lnk_tupdate_seq[11]), + .O(com_llm_llm_common_llm_common_reg_N_27_2) + ); + defparam com_llm_llm_common_llm_common_reg_rx_tsn_eq_sent_tsn_3_0_I_27.INIT = 16'h8421; + LUT4 com_llm_llm_common_llm_common_reg_rx_tsn_eq_sent_tsn_3_0_I_27 ( + .I0(com_llm_reg_rx_dllp_tsn[10]), + .I1(com_llm_reg_rx_dllp_tsn[11]), + .I2(com_lnk_ttrans_seq[10]), + .I3(com_lnk_ttrans_seq[11]), + .O(com_llm_llm_common_llm_common_reg_N_27_1) + ); + defparam com_llm_llm_common_llm_common_reg_next_eq_mark_q_3_0_I_27.INIT = 16'h8421; + LUT4 com_llm_llm_common_llm_common_reg_next_eq_mark_q_3_0_I_27 ( + .I0(com_llm_llm_common_llm_common_reg_hi_water_mark[10]), + .I1(com_llm_llm_common_llm_common_reg_hi_water_mark[11]), + .I2(com_llm_llm_common_llm_common_reg_reg_tx_next_tsn[10]), + .I3(com_llm_llm_common_llm_common_reg_reg_tx_next_tsn[11]), + .O(com_llm_llm_common_llm_common_reg_N_27_0) + ); + defparam com_llm_llm_common_llm_common_reg_curr_eq_mark_q_3_0_I_27.INIT = 16'h8421; + LUT4 com_llm_llm_common_llm_common_reg_curr_eq_mark_q_3_0_I_27 ( + .I0(com_llm_llm_common_llm_common_reg_hi_water_mark[10]), + .I1(com_llm_llm_common_llm_common_reg_hi_water_mark[11]), + .I2(com_llm_llm_common_llm_common_reg_reg_tx_curr_tsn[10]), + .I3(com_llm_llm_common_llm_common_reg_reg_tx_curr_tsn[11]), + .O(com_llm_llm_common_llm_common_reg_N_27) + ); + defparam com_llm_llm_common_llm_common_reg_reg_tx_next_tsn_4_axb_0.INIT = 4'h9; + LUT2 com_llm_llm_common_llm_common_reg_reg_tx_next_tsn_4_axb_0 ( + .I0(com_lnk_ttrans_seq[0]), + .I1(plm_link_up_1), + .O(com_llm_llm_common_llm_common_reg_reg_tx_next_tsn_4_axb_0_2085) + ); + defparam com_llm_llm_common_llm_common_reg_un3_tmp_result_axb_10.INIT = 4'h9; + LUT2 com_llm_llm_common_llm_common_reg_un3_tmp_result_axb_10 ( + .I0(com_llm_reg_rx_dllp_tsn_m1[10]), + .I1(com_lnk_ttrans_seq[10]), + .O(com_llm_llm_common_llm_common_reg_un3_tmp_result_axb_10_2086) + ); + defparam com_llm_llm_common_llm_common_reg_un3_tmp_result_axb_9.INIT = 4'h9; + LUT2 com_llm_llm_common_llm_common_reg_un3_tmp_result_axb_9 ( + .I0(com_llm_reg_rx_dllp_tsn_m1[9]), + .I1(com_lnk_ttrans_seq[9]), + .O(com_llm_llm_common_llm_common_reg_un3_tmp_result_axb_9_2087) + ); + defparam com_llm_llm_common_llm_common_reg_un3_tmp_result_axb_8.INIT = 4'h9; + LUT2 com_llm_llm_common_llm_common_reg_un3_tmp_result_axb_8 ( + .I0(com_llm_reg_rx_dllp_tsn_m1[8]), + .I1(com_lnk_ttrans_seq[8]), + .O(com_llm_llm_common_llm_common_reg_un3_tmp_result_axb_8_2088) + ); + defparam com_llm_llm_common_llm_common_reg_un3_tmp_result_axb_7.INIT = 4'h9; + LUT2 com_llm_llm_common_llm_common_reg_un3_tmp_result_axb_7 ( + .I0(com_llm_reg_rx_dllp_tsn_m1[7]), + .I1(com_lnk_ttrans_seq[7]), + .O(com_llm_llm_common_llm_common_reg_un3_tmp_result_axb_7_2089) + ); + defparam com_llm_llm_common_llm_common_reg_un3_tmp_result_axb_6.INIT = 4'h9; + LUT2 com_llm_llm_common_llm_common_reg_un3_tmp_result_axb_6 ( + .I0(com_llm_reg_rx_dllp_tsn_m1[6]), + .I1(com_lnk_ttrans_seq[6]), + .O(com_llm_llm_common_llm_common_reg_un3_tmp_result_axb_6_2090) + ); + defparam com_llm_llm_common_llm_common_reg_un3_tmp_result_axb_5.INIT = 4'h9; + LUT2 com_llm_llm_common_llm_common_reg_un3_tmp_result_axb_5 ( + .I0(com_llm_reg_rx_dllp_tsn_m1[5]), + .I1(com_lnk_ttrans_seq[5]), + .O(com_llm_llm_common_llm_common_reg_un3_tmp_result_axb_5_2091) + ); + defparam com_llm_llm_common_llm_common_reg_un3_tmp_result_axb_4.INIT = 4'h9; + LUT2 com_llm_llm_common_llm_common_reg_un3_tmp_result_axb_4 ( + .I0(com_llm_reg_rx_dllp_tsn_m1[4]), + .I1(com_lnk_ttrans_seq[4]), + .O(com_llm_llm_common_llm_common_reg_un3_tmp_result_axb_4_2092) + ); + defparam com_llm_llm_common_llm_common_reg_un3_tmp_result_axb_3.INIT = 4'h9; + LUT2 com_llm_llm_common_llm_common_reg_un3_tmp_result_axb_3 ( + .I0(com_llm_reg_rx_dllp_tsn_m1[3]), + .I1(com_lnk_ttrans_seq[3]), + .O(com_llm_llm_common_llm_common_reg_un3_tmp_result_axb_3_2093) + ); + defparam com_llm_llm_common_llm_common_reg_un3_tmp_result_axb_2.INIT = 4'h9; + LUT2 com_llm_llm_common_llm_common_reg_un3_tmp_result_axb_2 ( + .I0(com_llm_reg_rx_dllp_tsn_m1[2]), + .I1(com_lnk_ttrans_seq[2]), + .O(com_llm_llm_common_llm_common_reg_un3_tmp_result_axb_2_2094) + ); + defparam com_llm_llm_common_llm_common_reg_un3_tmp_result_axb_1.INIT = 4'h9; + LUT2 com_llm_llm_common_llm_common_reg_un3_tmp_result_axb_1 ( + .I0(com_llm_reg_rx_dllp_tsn_m1[1]), + .I1(com_lnk_ttrans_seq[1]), + .O(com_llm_llm_common_llm_common_reg_un3_tmp_result_axb_1_2095) + ); + defparam com_llm_llm_common_llm_common_reg_un3_tmp_result_axb_0.INIT = 4'h6; + LUT2 com_llm_llm_common_llm_common_reg_un3_tmp_result_axb_0 ( + .I0(com_llm_reg_rx_dllp_tsn[0]), + .I1(com_lnk_ttrans_seq[0]), + .O(com_llm_llm_common_llm_common_reg_un3_tmp_result_axb_0_2096) + ); + defparam com_llm_llm_common_llm_common_reg_un3_ttrans_st_hiwater_axb_10.INIT = 4'h9; + LUT2 com_llm_llm_common_llm_common_reg_un3_ttrans_st_hiwater_axb_10 ( + .I0(com_llm_llm_common_llm_common_reg_hi_water_mark[10]), + .I1(com_lnk_ttrans_seq[10]), + .O(com_llm_llm_common_llm_common_reg_un3_ttrans_st_hiwater_axb_10_2097) + ); + defparam com_llm_llm_common_llm_common_reg_un3_ttrans_st_hiwater_axb_9.INIT = 4'h9; + LUT2 com_llm_llm_common_llm_common_reg_un3_ttrans_st_hiwater_axb_9 ( + .I0(com_llm_llm_common_llm_common_reg_hi_water_mark[9]), + .I1(com_lnk_ttrans_seq[9]), + .O(com_llm_llm_common_llm_common_reg_un3_ttrans_st_hiwater_axb_9_2098) + ); + defparam com_llm_llm_common_llm_common_reg_un3_ttrans_st_hiwater_axb_8.INIT = 4'h9; + LUT2 com_llm_llm_common_llm_common_reg_un3_ttrans_st_hiwater_axb_8 ( + .I0(com_llm_llm_common_llm_common_reg_hi_water_mark[8]), + .I1(com_lnk_ttrans_seq[8]), + .O(com_llm_llm_common_llm_common_reg_un3_ttrans_st_hiwater_axb_8_2099) + ); + defparam com_llm_llm_common_llm_common_reg_un3_ttrans_st_hiwater_axb_7.INIT = 4'h9; + LUT2 com_llm_llm_common_llm_common_reg_un3_ttrans_st_hiwater_axb_7 ( + .I0(com_llm_llm_common_llm_common_reg_hi_water_mark[7]), + .I1(com_lnk_ttrans_seq[7]), + .O(com_llm_llm_common_llm_common_reg_un3_ttrans_st_hiwater_axb_7_2100) + ); + defparam com_llm_llm_common_llm_common_reg_un3_ttrans_st_hiwater_axb_6.INIT = 4'h9; + LUT2 com_llm_llm_common_llm_common_reg_un3_ttrans_st_hiwater_axb_6 ( + .I0(com_llm_llm_common_llm_common_reg_hi_water_mark[6]), + .I1(com_lnk_ttrans_seq[6]), + .O(com_llm_llm_common_llm_common_reg_un3_ttrans_st_hiwater_axb_6_2101) + ); + defparam com_llm_llm_common_llm_common_reg_un3_ttrans_st_hiwater_axb_5.INIT = 4'h9; + LUT2 com_llm_llm_common_llm_common_reg_un3_ttrans_st_hiwater_axb_5 ( + .I0(com_llm_llm_common_llm_common_reg_hi_water_mark[5]), + .I1(com_lnk_ttrans_seq[5]), + .O(com_llm_llm_common_llm_common_reg_un3_ttrans_st_hiwater_axb_5_2102) + ); + defparam com_llm_llm_common_llm_common_reg_un3_ttrans_st_hiwater_axb_4.INIT = 4'h9; + LUT2 com_llm_llm_common_llm_common_reg_un3_ttrans_st_hiwater_axb_4 ( + .I0(com_llm_llm_common_llm_common_reg_hi_water_mark[4]), + .I1(com_lnk_ttrans_seq[4]), + .O(com_llm_llm_common_llm_common_reg_un3_ttrans_st_hiwater_axb_4_2103) + ); + defparam com_llm_llm_common_llm_common_reg_un3_ttrans_st_hiwater_axb_3.INIT = 4'h9; + LUT2 com_llm_llm_common_llm_common_reg_un3_ttrans_st_hiwater_axb_3 ( + .I0(com_llm_llm_common_llm_common_reg_hi_water_mark[3]), + .I1(com_lnk_ttrans_seq[3]), + .O(com_llm_llm_common_llm_common_reg_un3_ttrans_st_hiwater_axb_3_2104) + ); + defparam com_llm_llm_common_llm_common_reg_un3_ttrans_st_hiwater_axb_2.INIT = 4'h9; + LUT2 com_llm_llm_common_llm_common_reg_un3_ttrans_st_hiwater_axb_2 ( + .I0(com_llm_llm_common_llm_common_reg_hi_water_mark[2]), + .I1(com_lnk_ttrans_seq[2]), + .O(com_llm_llm_common_llm_common_reg_un3_ttrans_st_hiwater_axb_2_2105) + ); + defparam com_llm_llm_common_llm_common_reg_un3_ttrans_st_hiwater_axb_1.INIT = 4'h9; + LUT2 com_llm_llm_common_llm_common_reg_un3_ttrans_st_hiwater_axb_1 ( + .I0(com_llm_llm_common_llm_common_reg_hi_water_mark[1]), + .I1(com_lnk_ttrans_seq[1]), + .O(com_llm_llm_common_llm_common_reg_un3_ttrans_st_hiwater_axb_1_2106) + ); + defparam com_llm_llm_common_llm_common_reg_un3_ttrans_st_hiwater_axb_0.INIT = 4'h9; + LUT2 com_llm_llm_common_llm_common_reg_un3_ttrans_st_hiwater_axb_0 ( + .I0(com_llm_llm_common_llm_common_reg_hi_water_mark[0]), + .I1(com_lnk_ttrans_seq[0]), + .O(com_llm_llm_common_llm_common_reg_un3_ttrans_st_hiwater_axb_0_2107) + ); + defparam com_llm_llm_common_llm_common_reg_curr_eq_mark_q_3_0_I_54.INIT = 16'h8421; + LUT4 com_llm_llm_common_llm_common_reg_curr_eq_mark_q_3_0_I_54 ( + .I0(com_llm_llm_common_llm_common_reg_hi_water_mark[2]), + .I1(com_llm_llm_common_llm_common_reg_hi_water_mark[3]), + .I2(com_llm_llm_common_llm_common_reg_reg_tx_curr_tsn[2]), + .I3(com_llm_llm_common_llm_common_reg_reg_tx_curr_tsn[3]), + .O(com_llm_llm_common_llm_common_reg_N_3_2) + ); + defparam com_llm_llm_common_llm_common_reg_curr_eq_mark_q_3_0_I_45.INIT = 16'h8421; + LUT4 com_llm_llm_common_llm_common_reg_curr_eq_mark_q_3_0_I_45 ( + .I0(com_llm_llm_common_llm_common_reg_hi_water_mark[8]), + .I1(com_llm_llm_common_llm_common_reg_hi_water_mark[9]), + .I2(com_llm_llm_common_llm_common_reg_reg_tx_curr_tsn[8]), + .I3(com_llm_llm_common_llm_common_reg_reg_tx_curr_tsn[9]), + .O(com_llm_llm_common_llm_common_reg_N_11_2) + ); + defparam com_llm_llm_common_llm_common_reg_curr_eq_mark_q_3_0_I_36.INIT = 16'h8421; + LUT4 com_llm_llm_common_llm_common_reg_curr_eq_mark_q_3_0_I_36 ( + .I0(com_llm_llm_common_llm_common_reg_hi_water_mark[6]), + .I1(com_llm_llm_common_llm_common_reg_hi_water_mark[7]), + .I2(com_llm_llm_common_llm_common_reg_reg_tx_curr_tsn[6]), + .I3(com_llm_llm_common_llm_common_reg_reg_tx_curr_tsn[7]), + .O(com_llm_llm_common_llm_common_reg_N_19_2) + ); + defparam com_llm_llm_common_llm_common_reg_curr_eq_mark_q_3_0_I_18.INIT = 16'h8421; + LUT4 com_llm_llm_common_llm_common_reg_curr_eq_mark_q_3_0_I_18 ( + .I0(com_llm_llm_common_llm_common_reg_hi_water_mark[4]), + .I1(com_llm_llm_common_llm_common_reg_hi_water_mark[5]), + .I2(com_llm_llm_common_llm_common_reg_reg_tx_curr_tsn[4]), + .I3(com_llm_llm_common_llm_common_reg_reg_tx_curr_tsn[5]), + .O(com_llm_llm_common_llm_common_reg_N_35_2) + ); + defparam com_llm_llm_common_llm_common_reg_curr_eq_mark_q_3_0_I_9.INIT = 16'h8421; + LUT4 com_llm_llm_common_llm_common_reg_curr_eq_mark_q_3_0_I_9 ( + .I0(com_llm_llm_common_llm_common_reg_hi_water_mark[0]), + .I1(com_llm_llm_common_llm_common_reg_hi_water_mark[1]), + .I2(com_llm_llm_common_llm_common_reg_reg_tx_curr_tsn[0]), + .I3(com_llm_llm_common_llm_common_reg_reg_tx_curr_tsn[1]), + .O(com_llm_llm_common_llm_common_reg_N_43_2) + ); + defparam com_llm_llm_common_llm_common_reg_next_eq_mark_q_3_0_I_54.INIT = 16'h8421; + LUT4 com_llm_llm_common_llm_common_reg_next_eq_mark_q_3_0_I_54 ( + .I0(com_llm_llm_common_llm_common_reg_hi_water_mark[2]), + .I1(com_llm_llm_common_llm_common_reg_hi_water_mark[3]), + .I2(com_llm_llm_common_llm_common_reg_reg_tx_next_tsn[2]), + .I3(com_llm_llm_common_llm_common_reg_reg_tx_next_tsn[3]), + .O(com_llm_llm_common_llm_common_reg_N_3_1) + ); + defparam com_llm_llm_common_llm_common_reg_next_eq_mark_q_3_0_I_45.INIT = 16'h8421; + LUT4 com_llm_llm_common_llm_common_reg_next_eq_mark_q_3_0_I_45 ( + .I0(com_llm_llm_common_llm_common_reg_hi_water_mark[8]), + .I1(com_llm_llm_common_llm_common_reg_hi_water_mark[9]), + .I2(com_llm_llm_common_llm_common_reg_reg_tx_next_tsn[8]), + .I3(com_llm_llm_common_llm_common_reg_reg_tx_next_tsn[9]), + .O(com_llm_llm_common_llm_common_reg_N_11_1) + ); + defparam com_llm_llm_common_llm_common_reg_next_eq_mark_q_3_0_I_36.INIT = 16'h8421; + LUT4 com_llm_llm_common_llm_common_reg_next_eq_mark_q_3_0_I_36 ( + .I0(com_llm_llm_common_llm_common_reg_hi_water_mark[6]), + .I1(com_llm_llm_common_llm_common_reg_hi_water_mark[7]), + .I2(com_llm_llm_common_llm_common_reg_reg_tx_next_tsn[6]), + .I3(com_llm_llm_common_llm_common_reg_reg_tx_next_tsn[7]), + .O(com_llm_llm_common_llm_common_reg_N_19_1) + ); + defparam com_llm_llm_common_llm_common_reg_next_eq_mark_q_3_0_I_18.INIT = 16'h8421; + LUT4 com_llm_llm_common_llm_common_reg_next_eq_mark_q_3_0_I_18 ( + .I0(com_llm_llm_common_llm_common_reg_hi_water_mark[4]), + .I1(com_llm_llm_common_llm_common_reg_hi_water_mark[5]), + .I2(com_llm_llm_common_llm_common_reg_reg_tx_next_tsn[4]), + .I3(com_llm_llm_common_llm_common_reg_reg_tx_next_tsn[5]), + .O(com_llm_llm_common_llm_common_reg_N_35_1) + ); + defparam com_llm_llm_common_llm_common_reg_next_eq_mark_q_3_0_I_9.INIT = 16'h8421; + LUT4 com_llm_llm_common_llm_common_reg_next_eq_mark_q_3_0_I_9 ( + .I0(com_llm_llm_common_llm_common_reg_hi_water_mark[0]), + .I1(com_llm_llm_common_llm_common_reg_hi_water_mark[1]), + .I2(com_llm_llm_common_llm_common_reg_reg_tx_next_tsn[0]), + .I3(com_llm_llm_common_llm_common_reg_reg_tx_next_tsn[1]), + .O(com_llm_llm_common_llm_common_reg_N_43_1) + ); + defparam com_llm_llm_common_llm_common_reg_rx_tsn_eq_sent_tsn_3_0_I_54.INIT = 16'h8421; + LUT4 com_llm_llm_common_llm_common_reg_rx_tsn_eq_sent_tsn_3_0_I_54 ( + .I0(com_llm_reg_rx_dllp_tsn[2]), + .I1(com_llm_reg_rx_dllp_tsn[3]), + .I2(com_lnk_ttrans_seq[2]), + .I3(com_lnk_ttrans_seq[3]), + .O(com_llm_llm_common_llm_common_reg_N_3_0) + ); + defparam com_llm_llm_common_llm_common_reg_rx_tsn_eq_sent_tsn_3_0_I_45.INIT = 16'h8421; + LUT4 com_llm_llm_common_llm_common_reg_rx_tsn_eq_sent_tsn_3_0_I_45 ( + .I0(com_llm_reg_rx_dllp_tsn[8]), + .I1(com_llm_reg_rx_dllp_tsn[9]), + .I2(com_lnk_ttrans_seq[8]), + .I3(com_lnk_ttrans_seq[9]), + .O(com_llm_llm_common_llm_common_reg_N_11_0) + ); + defparam com_llm_llm_common_llm_common_reg_rx_tsn_eq_sent_tsn_3_0_I_36.INIT = 16'h8421; + LUT4 com_llm_llm_common_llm_common_reg_rx_tsn_eq_sent_tsn_3_0_I_36 ( + .I0(com_llm_reg_rx_dllp_tsn[6]), + .I1(com_llm_reg_rx_dllp_tsn[7]), + .I2(com_lnk_ttrans_seq[6]), + .I3(com_lnk_ttrans_seq[7]), + .O(com_llm_llm_common_llm_common_reg_N_19_0) + ); + defparam com_llm_llm_common_llm_common_reg_rx_tsn_eq_sent_tsn_3_0_I_18.INIT = 16'h8421; + LUT4 com_llm_llm_common_llm_common_reg_rx_tsn_eq_sent_tsn_3_0_I_18 ( + .I0(com_llm_reg_rx_dllp_tsn[4]), + .I1(com_llm_reg_rx_dllp_tsn[5]), + .I2(com_lnk_ttrans_seq[4]), + .I3(com_lnk_ttrans_seq[5]), + .O(com_llm_llm_common_llm_common_reg_N_35_0) + ); + defparam com_llm_llm_common_llm_common_reg_rx_tsn_eq_sent_tsn_3_0_I_9.INIT = 16'h8421; + LUT4 com_llm_llm_common_llm_common_reg_rx_tsn_eq_sent_tsn_3_0_I_9 ( + .I0(com_llm_reg_rx_dllp_tsn[0]), + .I1(com_llm_reg_rx_dllp_tsn[1]), + .I2(com_lnk_ttrans_seq[0]), + .I3(com_lnk_ttrans_seq[1]), + .O(com_llm_llm_common_llm_common_reg_N_43_0) + ); + defparam com_llm_llm_common_llm_common_reg_ANSeqNum_Eq_AckdSeq_wire_0_I_54.INIT = 16'h8421; + LUT4 com_llm_llm_common_llm_common_reg_ANSeqNum_Eq_AckdSeq_wire_0_I_54 ( + .I0(com_llm_reg_rx_dllp_tsn[2]), + .I1(com_llm_reg_rx_dllp_tsn[3]), + .I2(com_lnk_tupdate_seq[2]), + .I3(com_lnk_tupdate_seq[3]), + .O(com_llm_llm_common_llm_common_reg_N_3) + ); + defparam com_llm_llm_common_llm_common_reg_ANSeqNum_Eq_AckdSeq_wire_0_I_45.INIT = 16'h8421; + LUT4 com_llm_llm_common_llm_common_reg_ANSeqNum_Eq_AckdSeq_wire_0_I_45 ( + .I0(com_llm_reg_rx_dllp_tsn[8]), + .I1(com_llm_reg_rx_dllp_tsn[9]), + .I2(com_lnk_tupdate_seq[8]), + .I3(com_lnk_tupdate_seq[9]), + .O(com_llm_llm_common_llm_common_reg_N_11) + ); + defparam com_llm_llm_common_llm_common_reg_ANSeqNum_Eq_AckdSeq_wire_0_I_36.INIT = 16'h8421; + LUT4 com_llm_llm_common_llm_common_reg_ANSeqNum_Eq_AckdSeq_wire_0_I_36 ( + .I0(com_llm_reg_rx_dllp_tsn[6]), + .I1(com_llm_reg_rx_dllp_tsn[7]), + .I2(com_lnk_tupdate_seq[6]), + .I3(com_lnk_tupdate_seq[7]), + .O(com_llm_llm_common_llm_common_reg_N_19) + ); + defparam com_llm_llm_common_llm_common_reg_ANSeqNum_Eq_AckdSeq_wire_0_I_18.INIT = 16'h8421; + LUT4 com_llm_llm_common_llm_common_reg_ANSeqNum_Eq_AckdSeq_wire_0_I_18 ( + .I0(com_llm_reg_rx_dllp_tsn[4]), + .I1(com_llm_reg_rx_dllp_tsn[5]), + .I2(com_lnk_tupdate_seq[4]), + .I3(com_lnk_tupdate_seq[5]), + .O(com_llm_llm_common_llm_common_reg_N_35) + ); + defparam com_llm_llm_common_llm_common_reg_ANSeqNum_Eq_AckdSeq_wire_0_I_9.INIT = 16'h8421; + LUT4 com_llm_llm_common_llm_common_reg_ANSeqNum_Eq_AckdSeq_wire_0_I_9 ( + .I0(com_llm_reg_rx_dllp_tsn[0]), + .I1(com_llm_reg_rx_dllp_tsn[1]), + .I2(com_lnk_tupdate_seq[0]), + .I3(com_lnk_tupdate_seq[1]), + .O(com_llm_llm_common_llm_common_reg_N_43) + ); + VCC com_llm_llm_common_llm_common_reg_compare_1_VCC ( + .P(com_llm_llm_common_llm_common_reg_compare_1_VCC_2108) + ); + MUXCY_L com_llm_llm_common_llm_common_reg_compare_1_result_cry_0 ( + .CI(com_llm_llm_common_llm_common_reg_compare_1_VCC_2108), + .DI(com_llm_llm_common_llm_common_reg_hi_water_mark[0]), + .LO(com_llm_llm_common_llm_common_reg_compare_1_result_cry_0_2109), + .S(com_llm_llm_common_llm_common_reg_compare_1_result_axb_0_2131) + ); + MUXCY_L com_llm_llm_common_llm_common_reg_compare_1_result_cry_1 ( + .CI(com_llm_llm_common_llm_common_reg_compare_1_result_cry_0_2109), + .DI(com_llm_llm_common_llm_common_reg_hi_water_mark[1]), + .LO(com_llm_llm_common_llm_common_reg_compare_1_result_cry_1_2110), + .S(com_llm_llm_common_llm_common_reg_compare_1_result_axb_1_2130) + ); + MUXCY_L com_llm_llm_common_llm_common_reg_compare_1_result_cry_2 ( + .CI(com_llm_llm_common_llm_common_reg_compare_1_result_cry_1_2110), + .DI(com_llm_llm_common_llm_common_reg_hi_water_mark[2]), + .LO(com_llm_llm_common_llm_common_reg_compare_1_result_cry_2_2111), + .S(com_llm_llm_common_llm_common_reg_compare_1_result_axb_2_2129) + ); + MUXCY_L com_llm_llm_common_llm_common_reg_compare_1_result_cry_3 ( + .CI(com_llm_llm_common_llm_common_reg_compare_1_result_cry_2_2111), + .DI(com_llm_llm_common_llm_common_reg_hi_water_mark[3]), + .LO(com_llm_llm_common_llm_common_reg_compare_1_result_cry_3_2112), + .S(com_llm_llm_common_llm_common_reg_compare_1_result_axb_3_2128) + ); + MUXCY_L com_llm_llm_common_llm_common_reg_compare_1_result_cry_4 ( + .CI(com_llm_llm_common_llm_common_reg_compare_1_result_cry_3_2112), + .DI(com_llm_llm_common_llm_common_reg_hi_water_mark[4]), + .LO(com_llm_llm_common_llm_common_reg_compare_1_result_cry_4_2113), + .S(com_llm_llm_common_llm_common_reg_compare_1_result_axb_4_2127) + ); + MUXCY_L com_llm_llm_common_llm_common_reg_compare_1_result_cry_5 ( + .CI(com_llm_llm_common_llm_common_reg_compare_1_result_cry_4_2113), + .DI(com_llm_llm_common_llm_common_reg_hi_water_mark[5]), + .LO(com_llm_llm_common_llm_common_reg_compare_1_result_cry_5_2114), + .S(com_llm_llm_common_llm_common_reg_compare_1_result_axb_5_2126) + ); + MUXCY_L com_llm_llm_common_llm_common_reg_compare_1_result_cry_6 ( + .CI(com_llm_llm_common_llm_common_reg_compare_1_result_cry_5_2114), + .DI(com_llm_llm_common_llm_common_reg_hi_water_mark[6]), + .LO(com_llm_llm_common_llm_common_reg_compare_1_result_cry_6_2115), + .S(com_llm_llm_common_llm_common_reg_compare_1_result_axb_6_2125) + ); + MUXCY_L com_llm_llm_common_llm_common_reg_compare_1_result_cry_7 ( + .CI(com_llm_llm_common_llm_common_reg_compare_1_result_cry_6_2115), + .DI(com_llm_llm_common_llm_common_reg_hi_water_mark[7]), + .LO(com_llm_llm_common_llm_common_reg_compare_1_result_cry_7_2116), + .S(com_llm_llm_common_llm_common_reg_compare_1_result_axb_7_2124) + ); + MUXCY_L com_llm_llm_common_llm_common_reg_compare_1_result_cry_8 ( + .CI(com_llm_llm_common_llm_common_reg_compare_1_result_cry_7_2116), + .DI(com_llm_llm_common_llm_common_reg_hi_water_mark[8]), + .LO(com_llm_llm_common_llm_common_reg_compare_1_result_cry_8_2117), + .S(com_llm_llm_common_llm_common_reg_compare_1_result_axb_8_2123) + ); + MUXCY_L com_llm_llm_common_llm_common_reg_compare_1_result_cry_9 ( + .CI(com_llm_llm_common_llm_common_reg_compare_1_result_cry_8_2117), + .DI(com_llm_llm_common_llm_common_reg_hi_water_mark[9]), + .LO(com_llm_llm_common_llm_common_reg_compare_1_result_cry_9_2118), + .S(com_llm_llm_common_llm_common_reg_compare_1_result_axb_9_2122) + ); + MUXCY_L com_llm_llm_common_llm_common_reg_compare_1_result_cry_10 ( + .CI(com_llm_llm_common_llm_common_reg_compare_1_result_cry_9_2118), + .DI(com_llm_llm_common_llm_common_reg_hi_water_mark[10]), + .LO(com_llm_llm_common_llm_common_reg_compare_1_result_cry_10_2119), + .S(com_llm_llm_common_llm_common_reg_compare_1_result_axb_10_2121) + ); + XORCY com_llm_llm_common_llm_common_reg_compare_1_result_s_11 ( + .CI(com_llm_llm_common_llm_common_reg_compare_1_result_cry_10_2119), + .LI(com_llm_llm_common_llm_common_reg_compare_1_result_axb_11_2120), + .O(com_llm_llm_common_llm_common_reg_compare_1_result[11]) + ); + defparam com_llm_llm_common_llm_common_reg_compare_1_result_axb_11.INIT = 4'h9; + LUT2 com_llm_llm_common_llm_common_reg_compare_1_result_axb_11 ( + .I0(com_llm_llm_common_llm_common_reg_hi_water_mark[11]), + .I1(com_llm_reg_rx_dllp_tsn[11]), + .O(com_llm_llm_common_llm_common_reg_compare_1_result_axb_11_2120) + ); + defparam com_llm_llm_common_llm_common_reg_compare_1_result_i_11_.INIT = 4'h1; + LUT1_L com_llm_llm_common_llm_common_reg_compare_1_result_i_11_ ( + .I0(com_llm_llm_common_llm_common_reg_compare_1_result[11]), + .LO(com_llm_llm_common_llm_common_reg_result_i_0[11]) + ); + defparam com_llm_llm_common_llm_common_reg_compare_1_result_axb_10.INIT = 4'h9; + LUT2 com_llm_llm_common_llm_common_reg_compare_1_result_axb_10 ( + .I0(com_llm_llm_common_llm_common_reg_hi_water_mark[10]), + .I1(com_llm_reg_rx_dllp_tsn[10]), + .O(com_llm_llm_common_llm_common_reg_compare_1_result_axb_10_2121) + ); + defparam com_llm_llm_common_llm_common_reg_compare_1_result_axb_9.INIT = 4'h9; + LUT2 com_llm_llm_common_llm_common_reg_compare_1_result_axb_9 ( + .I0(com_llm_llm_common_llm_common_reg_hi_water_mark[9]), + .I1(com_llm_reg_rx_dllp_tsn[9]), + .O(com_llm_llm_common_llm_common_reg_compare_1_result_axb_9_2122) + ); + defparam com_llm_llm_common_llm_common_reg_compare_1_result_axb_8.INIT = 4'h9; + LUT2 com_llm_llm_common_llm_common_reg_compare_1_result_axb_8 ( + .I0(com_llm_llm_common_llm_common_reg_hi_water_mark[8]), + .I1(com_llm_reg_rx_dllp_tsn[8]), + .O(com_llm_llm_common_llm_common_reg_compare_1_result_axb_8_2123) + ); + defparam com_llm_llm_common_llm_common_reg_compare_1_result_axb_7.INIT = 4'h9; + LUT2 com_llm_llm_common_llm_common_reg_compare_1_result_axb_7 ( + .I0(com_llm_llm_common_llm_common_reg_hi_water_mark[7]), + .I1(com_llm_reg_rx_dllp_tsn[7]), + .O(com_llm_llm_common_llm_common_reg_compare_1_result_axb_7_2124) + ); + defparam com_llm_llm_common_llm_common_reg_compare_1_result_axb_6.INIT = 4'h9; + LUT2 com_llm_llm_common_llm_common_reg_compare_1_result_axb_6 ( + .I0(com_llm_llm_common_llm_common_reg_hi_water_mark[6]), + .I1(com_llm_reg_rx_dllp_tsn[6]), + .O(com_llm_llm_common_llm_common_reg_compare_1_result_axb_6_2125) + ); + defparam com_llm_llm_common_llm_common_reg_compare_1_result_axb_5.INIT = 4'h9; + LUT2 com_llm_llm_common_llm_common_reg_compare_1_result_axb_5 ( + .I0(com_llm_llm_common_llm_common_reg_hi_water_mark[5]), + .I1(com_llm_reg_rx_dllp_tsn[5]), + .O(com_llm_llm_common_llm_common_reg_compare_1_result_axb_5_2126) + ); + defparam com_llm_llm_common_llm_common_reg_compare_1_result_axb_4.INIT = 4'h9; + LUT2 com_llm_llm_common_llm_common_reg_compare_1_result_axb_4 ( + .I0(com_llm_llm_common_llm_common_reg_hi_water_mark[4]), + .I1(com_llm_reg_rx_dllp_tsn[4]), + .O(com_llm_llm_common_llm_common_reg_compare_1_result_axb_4_2127) + ); + defparam com_llm_llm_common_llm_common_reg_compare_1_result_axb_3.INIT = 4'h9; + LUT2 com_llm_llm_common_llm_common_reg_compare_1_result_axb_3 ( + .I0(com_llm_llm_common_llm_common_reg_hi_water_mark[3]), + .I1(com_llm_reg_rx_dllp_tsn[3]), + .O(com_llm_llm_common_llm_common_reg_compare_1_result_axb_3_2128) + ); + defparam com_llm_llm_common_llm_common_reg_compare_1_result_axb_2.INIT = 4'h9; + LUT2 com_llm_llm_common_llm_common_reg_compare_1_result_axb_2 ( + .I0(com_llm_llm_common_llm_common_reg_hi_water_mark[2]), + .I1(com_llm_reg_rx_dllp_tsn[2]), + .O(com_llm_llm_common_llm_common_reg_compare_1_result_axb_2_2129) + ); + defparam com_llm_llm_common_llm_common_reg_compare_1_result_axb_1.INIT = 4'h9; + LUT2 com_llm_llm_common_llm_common_reg_compare_1_result_axb_1 ( + .I0(com_llm_llm_common_llm_common_reg_hi_water_mark[1]), + .I1(com_llm_reg_rx_dllp_tsn[1]), + .O(com_llm_llm_common_llm_common_reg_compare_1_result_axb_1_2130) + ); + defparam com_llm_llm_common_llm_common_reg_compare_1_result_axb_0.INIT = 4'h9; + LUT2 com_llm_llm_common_llm_common_reg_compare_1_result_axb_0 ( + .I0(com_llm_llm_common_llm_common_reg_hi_water_mark[0]), + .I1(com_llm_reg_rx_dllp_tsn[0]), + .O(com_llm_llm_common_llm_common_reg_compare_1_result_axb_0_2131) + ); + VCC com_llm_llm_common_llm_common_reg_compare_2_VCC ( + .P(com_llm_llm_common_llm_common_reg_compare_2_VCC_2132) + ); + MUXCY_L com_llm_llm_common_llm_common_reg_compare_2_result_cry_0 ( + .CI(com_llm_llm_common_llm_common_reg_compare_2_VCC_2132), + .DI(com_llm_reg_rx_dllp_tsn[0]), + .LO(com_llm_llm_common_llm_common_reg_compare_2_result_cry_0_2133), + .S(com_llm_llm_common_llm_common_reg_compare_2_result_axb_0_2155) + ); + MUXCY_L com_llm_llm_common_llm_common_reg_compare_2_result_cry_1 ( + .CI(com_llm_llm_common_llm_common_reg_compare_2_result_cry_0_2133), + .DI(com_llm_reg_rx_dllp_tsn[1]), + .LO(com_llm_llm_common_llm_common_reg_compare_2_result_cry_1_2134), + .S(com_llm_llm_common_llm_common_reg_compare_2_result_axb_1_2154) + ); + MUXCY_L com_llm_llm_common_llm_common_reg_compare_2_result_cry_2 ( + .CI(com_llm_llm_common_llm_common_reg_compare_2_result_cry_1_2134), + .DI(com_llm_reg_rx_dllp_tsn[2]), + .LO(com_llm_llm_common_llm_common_reg_compare_2_result_cry_2_2135), + .S(com_llm_llm_common_llm_common_reg_compare_2_result_axb_2_2153) + ); + MUXCY_L com_llm_llm_common_llm_common_reg_compare_2_result_cry_3 ( + .CI(com_llm_llm_common_llm_common_reg_compare_2_result_cry_2_2135), + .DI(com_llm_reg_rx_dllp_tsn[3]), + .LO(com_llm_llm_common_llm_common_reg_compare_2_result_cry_3_2136), + .S(com_llm_llm_common_llm_common_reg_compare_2_result_axb_3_2152) + ); + MUXCY_L com_llm_llm_common_llm_common_reg_compare_2_result_cry_4 ( + .CI(com_llm_llm_common_llm_common_reg_compare_2_result_cry_3_2136), + .DI(com_llm_reg_rx_dllp_tsn[4]), + .LO(com_llm_llm_common_llm_common_reg_compare_2_result_cry_4_2137), + .S(com_llm_llm_common_llm_common_reg_compare_2_result_axb_4_2151) + ); + MUXCY_L com_llm_llm_common_llm_common_reg_compare_2_result_cry_5 ( + .CI(com_llm_llm_common_llm_common_reg_compare_2_result_cry_4_2137), + .DI(com_llm_reg_rx_dllp_tsn[5]), + .LO(com_llm_llm_common_llm_common_reg_compare_2_result_cry_5_2138), + .S(com_llm_llm_common_llm_common_reg_compare_2_result_axb_5_2150) + ); + MUXCY_L com_llm_llm_common_llm_common_reg_compare_2_result_cry_6 ( + .CI(com_llm_llm_common_llm_common_reg_compare_2_result_cry_5_2138), + .DI(com_llm_reg_rx_dllp_tsn[6]), + .LO(com_llm_llm_common_llm_common_reg_compare_2_result_cry_6_2139), + .S(com_llm_llm_common_llm_common_reg_compare_2_result_axb_6_2149) + ); + MUXCY_L com_llm_llm_common_llm_common_reg_compare_2_result_cry_7 ( + .CI(com_llm_llm_common_llm_common_reg_compare_2_result_cry_6_2139), + .DI(com_llm_reg_rx_dllp_tsn[7]), + .LO(com_llm_llm_common_llm_common_reg_compare_2_result_cry_7_2140), + .S(com_llm_llm_common_llm_common_reg_compare_2_result_axb_7_2148) + ); + MUXCY_L com_llm_llm_common_llm_common_reg_compare_2_result_cry_8 ( + .CI(com_llm_llm_common_llm_common_reg_compare_2_result_cry_7_2140), + .DI(com_llm_reg_rx_dllp_tsn[8]), + .LO(com_llm_llm_common_llm_common_reg_compare_2_result_cry_8_2141), + .S(com_llm_llm_common_llm_common_reg_compare_2_result_axb_8_2147) + ); + MUXCY_L com_llm_llm_common_llm_common_reg_compare_2_result_cry_9 ( + .CI(com_llm_llm_common_llm_common_reg_compare_2_result_cry_8_2141), + .DI(com_llm_reg_rx_dllp_tsn[9]), + .LO(com_llm_llm_common_llm_common_reg_compare_2_result_cry_9_2142), + .S(com_llm_llm_common_llm_common_reg_compare_2_result_axb_9_2146) + ); + MUXCY_L com_llm_llm_common_llm_common_reg_compare_2_result_cry_10 ( + .CI(com_llm_llm_common_llm_common_reg_compare_2_result_cry_9_2142), + .DI(com_llm_reg_rx_dllp_tsn[10]), + .LO(com_llm_llm_common_llm_common_reg_compare_2_result_cry_10_2143), + .S(com_llm_llm_common_llm_common_reg_compare_2_result_axb_10_2145) + ); + XORCY com_llm_llm_common_llm_common_reg_compare_2_result_s_11 ( + .CI(com_llm_llm_common_llm_common_reg_compare_2_result_cry_10_2143), + .LI(com_llm_llm_common_llm_common_reg_compare_2_result_axb_11_2144), + .O(com_llm_llm_common_llm_common_reg_compare_2_result[11]) + ); + defparam com_llm_llm_common_llm_common_reg_compare_2_result_axb_11.INIT = 4'h9; + LUT2 com_llm_llm_common_llm_common_reg_compare_2_result_axb_11 ( + .I0(com_llm_reg_rx_dllp_tsn[11]), + .I1(com_lnk_tupdate_seq[11]), + .O(com_llm_llm_common_llm_common_reg_compare_2_result_axb_11_2144) + ); + defparam com_llm_llm_common_llm_common_reg_compare_2_result_i_11_.INIT = 4'h1; + LUT1_L com_llm_llm_common_llm_common_reg_compare_2_result_i_11_ ( + .I0(com_llm_llm_common_llm_common_reg_compare_2_result[11]), + .LO(com_llm_llm_common_llm_common_reg_result_i[11]) + ); + defparam com_llm_llm_common_llm_common_reg_compare_2_result_axb_10.INIT = 4'h9; + LUT2 com_llm_llm_common_llm_common_reg_compare_2_result_axb_10 ( + .I0(com_llm_reg_rx_dllp_tsn[10]), + .I1(com_lnk_tupdate_seq[10]), + .O(com_llm_llm_common_llm_common_reg_compare_2_result_axb_10_2145) + ); + defparam com_llm_llm_common_llm_common_reg_compare_2_result_axb_9.INIT = 4'h9; + LUT2 com_llm_llm_common_llm_common_reg_compare_2_result_axb_9 ( + .I0(com_llm_reg_rx_dllp_tsn[9]), + .I1(com_lnk_tupdate_seq[9]), + .O(com_llm_llm_common_llm_common_reg_compare_2_result_axb_9_2146) + ); + defparam com_llm_llm_common_llm_common_reg_compare_2_result_axb_8.INIT = 4'h9; + LUT2 com_llm_llm_common_llm_common_reg_compare_2_result_axb_8 ( + .I0(com_llm_reg_rx_dllp_tsn[8]), + .I1(com_lnk_tupdate_seq[8]), + .O(com_llm_llm_common_llm_common_reg_compare_2_result_axb_8_2147) + ); + defparam com_llm_llm_common_llm_common_reg_compare_2_result_axb_7.INIT = 4'h9; + LUT2 com_llm_llm_common_llm_common_reg_compare_2_result_axb_7 ( + .I0(com_llm_reg_rx_dllp_tsn[7]), + .I1(com_lnk_tupdate_seq[7]), + .O(com_llm_llm_common_llm_common_reg_compare_2_result_axb_7_2148) + ); + defparam com_llm_llm_common_llm_common_reg_compare_2_result_axb_6.INIT = 4'h9; + LUT2 com_llm_llm_common_llm_common_reg_compare_2_result_axb_6 ( + .I0(com_llm_reg_rx_dllp_tsn[6]), + .I1(com_lnk_tupdate_seq[6]), + .O(com_llm_llm_common_llm_common_reg_compare_2_result_axb_6_2149) + ); + defparam com_llm_llm_common_llm_common_reg_compare_2_result_axb_5.INIT = 4'h9; + LUT2 com_llm_llm_common_llm_common_reg_compare_2_result_axb_5 ( + .I0(com_llm_reg_rx_dllp_tsn[5]), + .I1(com_lnk_tupdate_seq[5]), + .O(com_llm_llm_common_llm_common_reg_compare_2_result_axb_5_2150) + ); + defparam com_llm_llm_common_llm_common_reg_compare_2_result_axb_4.INIT = 4'h9; + LUT2 com_llm_llm_common_llm_common_reg_compare_2_result_axb_4 ( + .I0(com_llm_reg_rx_dllp_tsn[4]), + .I1(com_lnk_tupdate_seq[4]), + .O(com_llm_llm_common_llm_common_reg_compare_2_result_axb_4_2151) + ); + defparam com_llm_llm_common_llm_common_reg_compare_2_result_axb_3.INIT = 4'h9; + LUT2 com_llm_llm_common_llm_common_reg_compare_2_result_axb_3 ( + .I0(com_llm_reg_rx_dllp_tsn[3]), + .I1(com_lnk_tupdate_seq[3]), + .O(com_llm_llm_common_llm_common_reg_compare_2_result_axb_3_2152) + ); + defparam com_llm_llm_common_llm_common_reg_compare_2_result_axb_2.INIT = 4'h9; + LUT2 com_llm_llm_common_llm_common_reg_compare_2_result_axb_2 ( + .I0(com_llm_reg_rx_dllp_tsn[2]), + .I1(com_lnk_tupdate_seq[2]), + .O(com_llm_llm_common_llm_common_reg_compare_2_result_axb_2_2153) + ); + defparam com_llm_llm_common_llm_common_reg_compare_2_result_axb_1.INIT = 4'h9; + LUT2 com_llm_llm_common_llm_common_reg_compare_2_result_axb_1 ( + .I0(com_llm_reg_rx_dllp_tsn[1]), + .I1(com_lnk_tupdate_seq[1]), + .O(com_llm_llm_common_llm_common_reg_compare_2_result_axb_1_2154) + ); + defparam com_llm_llm_common_llm_common_reg_compare_2_result_axb_0.INIT = 4'h9; + LUT2 com_llm_llm_common_llm_common_reg_compare_2_result_axb_0 ( + .I0(com_llm_reg_rx_dllp_tsn[0]), + .I1(com_lnk_tupdate_seq[0]), + .O(com_llm_llm_common_llm_common_reg_compare_2_result_axb_0_2155) + ); + defparam com_llm_llm_common_llm_common_reg_llm_ack_nak_buf_un1_clr_nak_buffer_i_0_0_1.INIT = 4'h1; + LUT2 com_llm_llm_common_llm_common_reg_llm_ack_nak_buf_un1_clr_nak_buffer_i_0_0_1 ( + .I0(com_llm_link_status_0_), + .I1(com_reg_tx_update_retry_int), + .O(com_llm_llm_common_llm_common_reg_llm_ack_nak_buf_N_67884_1) + ); + defparam com_llm_llm_common_llm_common_reg_llm_ack_nak_buf_ack_pending_7_iv_0_0_0_o4.INIT = 8'h20; + LUT3 com_llm_llm_common_llm_common_reg_llm_ack_nak_buf_ack_pending_7_iv_0_0_0_o4 ( + .I0(com_llm_llm_common_llm_common_reg_ANSeqNum_AckdSeq_wire_2030), + .I1(com_llm_llm_common_llm_common_reg_ANSeqNum_Eq_AckdSeq_2040), + .I2(com_llm_llm_common_llm_common_reg_NxtTxTSN_ANSeqNum_wire_2029), + .O(com_llm_llm_common_llm_common_reg_N_38195_i) + ); + defparam com_llm_llm_common_llm_common_reg_llm_ack_nak_buf_nak_pending_8_0_a2_0_a2_3.INIT = 16'h0800; + LUT4 com_llm_llm_common_llm_common_reg_llm_ack_nak_buf_nak_pending_8_0_a2_0_a2_3 ( + .I0(com_llm_llm_common_llm_common_reg_ANSeqNum_AckdSeq_wire_2030), + .I1(com_llm_llm_common_llm_common_reg_NxtTxTSN_ANSeqNum_wire_2029), + .I2(com_llm_llm_common_llm_common_reg_nak_pending), + .I3(com_llm_llm_common_llm_common_reg_reg_rx_dllp_nak_vld_q_2032), + .O(com_llm_llm_common_llm_common_reg_llm_ack_nak_buf_N_38452) + ); + defparam com_llm_llm_common_llm_common_reg_llm_ack_nak_buf_ack_pending_7_iv_0_0_0_1.INIT = 16'hA888; + LUT4 com_llm_llm_common_llm_common_reg_llm_ack_nak_buf_ack_pending_7_iv_0_0_0_1 ( + .I0(com_llm_llm_common_llm_common_reg_N_38195_i), + .I1(com_llm_llm_common_llm_common_reg_reg_rx_dllp_ack_vld_q_2033), + .I2(com_llm_llm_common_llm_common_reg_reg_rx_dllp_nak_vld_q_2032), + .I3(com_llm_llm_common_llm_common_reg_rx_tsn_eq_sent_tsn_2036), + .O(com_llm_llm_common_llm_common_reg_llm_ack_nak_buf_N_8834_1_i) + ); + defparam com_llm_llm_common_llm_common_reg_llm_ack_nak_buf_N_67863_i.INIT = 16'hEFEE; + LUT4 com_llm_llm_common_llm_common_reg_llm_ack_nak_buf_N_67863_i ( + .I0(com_llm_llm_common_llm_common_reg_llm_ack_nak_buf_N_8834_1_i), + .I1(com_llm_link_status_0_), + .I2(com_llm_llm_common_llm_common_reg_llm_ack_nak_buf_acknak_state_q[1]), + .I3(com_reg_tx_update_ack), + .O(com_llm_llm_common_llm_common_reg_llm_ack_nak_buf_N_67863_i_2157) + ); + defparam com_llm_llm_common_llm_common_reg_llm_ack_nak_buf_acknak_state_q_5_0_a3_0_a2_0_a4_1_.INIT = 4'h4; + LUT2_L com_llm_llm_common_llm_common_reg_llm_ack_nak_buf_acknak_state_q_5_0_a3_0_a2_0_a4_1_ ( + .I0(com_llm_link_status_0_), + .I1(com_reg_tx_update_ack), + .LO(com_llm_llm_common_llm_common_reg_llm_ack_nak_buf_acknak_state_q_5[1]) + ); + defparam com_llm_llm_common_llm_common_reg_llm_ack_nak_buf_nak_pending_8_0_a2_0_a2.INIT = 16'h0008; + LUT4_L com_llm_llm_common_llm_common_reg_llm_ack_nak_buf_nak_pending_8_0_a2_0_a2 ( + .I0(com_llm_llm_common_llm_common_reg_llm_ack_nak_buf_N_38452), + .I1(com_llm_llm_common_llm_common_reg_llm_ack_nak_buf_N_67884_1), + .I2(com_llm_llm_common_llm_common_reg_rx_tsn_eq_sent_tsn_2036), + .I3(com_llm_llm_common_llm_common_reg_tmp_result[11]), + .LO(com_llm_llm_common_llm_common_reg_llm_ack_nak_buf_nak_pending_8) + ); + defparam com_llm_llm_common_llm_common_reg_llm_ack_nak_buf_ack_pending_7_iv_0_0_0.INIT = 16'h2022; + LUT4_L com_llm_llm_common_llm_common_reg_llm_ack_nak_buf_ack_pending_7_iv_0_0_0 ( + .I0(com_llm_llm_common_llm_common_reg_llm_ack_nak_buf_N_8834_1_i), + .I1(com_llm_link_status_0_), + .I2(com_llm_llm_common_llm_common_reg_rx_tsn_eq_sent_tsn_2036), + .I3(com_llm_llm_common_llm_common_reg_tmp_result[11]), + .LO(com_llm_llm_common_llm_common_reg_llm_ack_nak_buf_N_8834_i) + ); + defparam com_llm_llm_common_llm_common_reg_llm_ack_nak_buf_N_67884_i.INIT = 8'hFE; + LUT3 com_llm_llm_common_llm_common_reg_llm_ack_nak_buf_N_67884_i ( + .I0(com_llm_llm_common_llm_common_reg_llm_ack_nak_buf_N_38452), + .I1(com_reg_tx_update_retry_int), + .I2(com_llm_link_status_0_), + .O(com_llm_llm_common_llm_common_reg_llm_ack_nak_buf_N_67884_i_2156) + ); + FDC com_llm_llm_common_llm_common_reg_llm_ack_nak_buf_acknak_state_q_1_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_common_llm_common_reg_llm_ack_nak_buf_acknak_state_q_5[1]), + .Q(com_llm_llm_common_llm_common_reg_llm_ack_nak_buf_acknak_state_q[1]), + .CLR(plm_link_up_i) + ); + FDCE com_llm_llm_common_llm_common_reg_llm_ack_nak_buf_nak_pending ( + .CE(com_llm_llm_common_llm_common_reg_llm_ack_nak_buf_N_67884_i_2156), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_common_llm_common_reg_llm_ack_nak_buf_nak_pending_8), + .Q(com_llm_llm_common_llm_common_reg_nak_pending), + .CLR(plm_link_up_i) + ); + FDCE com_llm_llm_common_llm_common_reg_llm_ack_nak_buf_ack_pending ( + .CE(com_llm_llm_common_llm_common_reg_llm_ack_nak_buf_N_67863_i_2157), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_common_llm_common_reg_llm_ack_nak_buf_N_8834_i), + .Q(com_llm_llm_common_llm_common_reg_ack_pending), + .CLR(plm_link_up_i) + ); + defparam com_llm_llm_common_llm_common_reg_llm_ack_nak_fsm_ns_acknakfsm25_0_a2_0_a2_0_a2_0_a4.INIT = 4'h1; + LUT2 com_llm_llm_common_llm_common_reg_llm_ack_nak_fsm_ns_acknakfsm25_0_a2_0_a2_0_a2_0_a4 ( + .I0(com_llm_llm_common_llm_common_reg_nak_pending), + .I1(com_llm_llm_common_llm_common_reg_replay_timeout_flag), + .O(com_llm_llm_common_llm_common_reg_llm_ack_nak_fsm_N_38640) + ); + defparam com_llm_llm_common_llm_common_reg_llm_ack_nak_fsm_CS_ACKNAKFSM_cs_acknakfsm_5_i_0_0_0_.INIT = 16'h0105; + LUT4 com_llm_llm_common_llm_common_reg_llm_ack_nak_fsm_CS_ACKNAKFSM_cs_acknakfsm_5_i_0_0_0_ ( + .I0(com_llm_link_status_0_), + .I1(com_reg_tx_update_retry_int), + .I2(com_reg_tx_update_ack), + .I3(com_lnk_tretry), + .O(com_llm_llm_common_llm_common_reg_llm_ack_nak_fsm_cs_acknakfsm_5_i_0_0[0]) + ); + defparam com_llm_llm_common_llm_common_reg_llm_ack_nak_fsm_CS_ACKNAKFSM_cs_acknakfsm_5_i_0_0_2_.INIT = 8'hC4; + LUT3_L com_llm_llm_common_llm_common_reg_llm_ack_nak_fsm_CS_ACKNAKFSM_cs_acknakfsm_5_i_0_0_2_ ( + .I0(com_llm_llm_common_llm_common_reg_llm_ack_nak_fsm_N_38640), + .I1(com_llm_llm_common_llm_common_reg_llm_ack_nak_fsm_cs_acknakfsm_5_i_0_0[0]), + .I2(com_reg_tx_update_retry_int), + .LO(com_llm_llm_common_llm_common_reg_llm_ack_nak_fsm_N_11654_i) + ); + defparam com_llm_llm_common_llm_common_reg_llm_ack_nak_fsm_CS_ACKNAKFSM_cs_acknakfsm_5_0_a2_0_a2_1_.INIT = 16'h2000; + LUT4_L com_llm_llm_common_llm_common_reg_llm_ack_nak_fsm_CS_ACKNAKFSM_cs_acknakfsm_5_0_a2_0_a2_1_ ( + .I0(com_llm_llm_common_llm_common_reg_llm_ack_nak_fsm_N_38640), + .I1(com_llm_link_status_0_), + .I2(com_llm_llm_common_llm_common_reg_ack_pending), + .I3(com_llm_llm_common_llm_common_reg_llm_ack_nak_fsm_acknak_state[0]), + .LO(com_llm_llm_common_llm_common_reg_llm_ack_nak_fsm_cs_acknakfsm_5[1]) + ); + defparam com_llm_llm_common_llm_common_reg_llm_ack_nak_fsm_CS_ACKNAKFSM_N_68300_i.INIT = 16'h333B; + LUT4_L com_llm_llm_common_llm_common_reg_llm_ack_nak_fsm_CS_ACKNAKFSM_N_68300_i ( + .I0(com_llm_llm_common_llm_common_reg_llm_ack_nak_fsm_N_38640), + .I1(com_llm_llm_common_llm_common_reg_llm_ack_nak_fsm_cs_acknakfsm_5_i_0_0[0]), + .I2(com_llm_llm_common_llm_common_reg_ack_pending), + .I3(com_reg_tx_update_retry_int), + .LO(com_llm_llm_common_llm_common_reg_llm_ack_nak_fsm_N_68300_i) + ); + FDC com_llm_llm_common_llm_common_reg_llm_ack_nak_fsm_cs_acknakfsm_2_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_common_llm_common_reg_llm_ack_nak_fsm_N_11654_i), + .Q(com_reg_tx_update_retry_int), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_common_llm_common_reg_llm_ack_nak_fsm_cs_acknakfsm_1_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_common_llm_common_reg_llm_ack_nak_fsm_cs_acknakfsm_5[1]), + .Q(com_reg_tx_update_ack), + .CLR(plm_link_up_i) + ); + FDP com_llm_llm_common_llm_common_reg_llm_ack_nak_fsm_cs_acknakfsm_0_ ( + .PRE(plm_link_up_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_common_llm_common_reg_llm_ack_nak_fsm_N_68300_i), + .Q(com_llm_llm_common_llm_common_reg_llm_ack_nak_fsm_acknak_state[0]) + ); + VCC com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_VCC ( + .P(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_VCC_2158) + ); + GND com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_GND ( + .G(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_GND_2165) + ); + FDR com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_clear ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_N_67866_i_2163), + .Q(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_clear_2161), + .R(plm_link_up_i) + ); + FDR com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_q_0_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer[0]), + .Q(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_q[0]), + .R(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_N_9729_i_2160) + ); + FDR com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_q_1_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer[1]), + .Q(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_q[1]), + .R(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_N_9729_i_2160) + ); + FDR com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_q_2_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer[2]), + .Q(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_q[2]), + .R(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_N_9729_i_2160) + ); + FDR com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_q_3_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer[3]), + .Q(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_q[3]), + .R(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_N_9729_i_2160) + ); + FDR com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_q_4_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer[4]), + .Q(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_q[4]), + .R(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_N_9729_i_2160) + ); + FDR com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_q_5_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer[5]), + .Q(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_q[5]), + .R(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_N_9729_i_2160) + ); + FDR com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_q_6_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer[6]), + .Q(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_q[6]), + .R(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_N_9729_i_2160) + ); + FDR com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_q_7_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer[7]), + .Q(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_q[7]), + .R(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_N_9729_i_2160) + ); + FDR com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_q_8_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer[8]), + .Q(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_q[8]), + .R(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_N_9729_i_2160) + ); + FDR com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_q_9_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer[9]), + .Q(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_q[9]), + .R(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_N_9729_i_2160) + ); + FDR com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_q_10_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer[10]), + .Q(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_q[10]), + .R(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_N_9729_i_2160) + ); + FDR com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_q_11_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer[11]), + .Q(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_q[11]), + .R(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_N_9729_i_2160) + ); + FDR com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_q_12_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer[12]), + .Q(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_q[12]), + .R(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_N_9729_i_2160) + ); + FDR com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_q_13_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer[13]), + .Q(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_q[13]), + .R(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_N_9729_i_2160) + ); + FDR com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_q_14_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer[14]), + .Q(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_q[14]), + .R(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_N_9729_i_2160) + ); + FDR com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_set ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_set_3), + .Q(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_set_2159), + .R(plm_link_up_i) + ); + MUXCY_L com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_un1_diff_flag_0_I_1 ( + .CI(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_VCC_2158), + .DI(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_GND_2165), + .LO(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_data_tmp_1[0]), + .S(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_N_43) + ); + MUXCY_L com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_un1_diff_flag_0_I_10 ( + .CI(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_data_tmp_1[1]), + .DI(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_GND_2165), + .LO(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_data_tmp_1[2]), + .S(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_N_35) + ); + MUXCY_L com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_un1_diff_flag_0_I_28 ( + .CI(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_data_tmp_1[2]), + .DI(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_GND_2165), + .LO(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_data_tmp_1[3]), + .S(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_N_19) + ); + MUXCY_L com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_un1_diff_flag_0_I_37 ( + .CI(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_data_tmp_1[3]), + .DI(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_GND_2165), + .LO(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_data_tmp[4]), + .S(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_N_11) + ); + MUXCY_L com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_un1_diff_flag_0_I_46 ( + .CI(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_data_tmp_1[0]), + .DI(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_GND_2165), + .LO(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_data_tmp_1[1]), + .S(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_N_3) + ); + MUXCY_L com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_expire_pre_4_0_I_1 ( + .CI(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_VCC_2158), + .DI(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_GND_2165), + .LO(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_data_tmp_0[0]), + .S(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_N_57) + ); + MUXCY_L com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_expire_pre_4_0_I_10 ( + .CI(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_data_tmp_0[0]), + .DI(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_GND_2165), + .LO(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_data_tmp_0[1]), + .S(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_N_49) + ); + MUXCY_L com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_expire_pre_4_0_I_19 ( + .CI(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_data_tmp_0[1]), + .DI(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_GND_2165), + .LO(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_data_tmp_0[2]), + .S(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_N_41) + ); + MUXCY_L com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_expire_pre_4_0_I_28 ( + .CI(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_data_tmp_0[2]), + .DI(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_GND_2165), + .LO(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_data_tmp_0[3]), + .S(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_N_33) + ); + MUXCY_L com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_expire_pre_4_0_I_37 ( + .CI(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_data_tmp_0[3]), + .DI(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_GND_2165), + .LO(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_data_tmp_1[4]), + .S(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_N_25) + ); + MUXCY_L com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_expire_pre_4_0_I_46 ( + .CI(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_data_tmp_1[4]), + .DI(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_GND_2165), + .LO(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_data_tmp[5]), + .S(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_N_17) + ); + MUXCY_L com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_expire_pre_4_0_I_55 ( + .CI(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_data_tmp[5]), + .DI(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_GND_2165), + .LO(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_data_tmp[6]), + .S(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_N_9) + ); + MUXCY_L com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_reg_same_last_ackd_tsn_3_0_I_1 ( + .CI(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_VCC_2158), + .DI(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_GND_2165), + .LO(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_data_tmp[0]), + .S(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_N_43_0) + ); + MUXCY_L com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_reg_same_last_ackd_tsn_3_0_I_10 ( + .CI(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_data_tmp[1]), + .DI(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_GND_2165), + .LO(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_data_tmp[2]), + .S(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_N_35_0) + ); + MUXCY_L com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_reg_same_last_ackd_tsn_3_0_I_28 ( + .CI(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_data_tmp[2]), + .DI(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_GND_2165), + .LO(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_data_tmp[3]), + .S(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_N_19_0) + ); + MUXCY_L com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_reg_same_last_ackd_tsn_3_0_I_37 ( + .CI(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_data_tmp[3]), + .DI(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_GND_2165), + .LO(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_data_tmp_0[4]), + .S(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_N_11_0) + ); + MUXCY_L com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_reg_same_last_ackd_tsn_3_0_I_46 ( + .CI(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_data_tmp[0]), + .DI(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_GND_2165), + .LO(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_data_tmp[1]), + .S(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_N_3_0) + ); + FDRE com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_0_ ( + .CE(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_set_2159), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_s[0]), + .Q(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer[0]), + .R(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_N_9729_i_2160) + ); + MUXCY_L com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_cry_1_ ( + .CI(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer[0]), + .DI(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_GND_2165), + .LO(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_cry[1]), + .S(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_qxu[1]) + ); + XORCY com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_s_1_ ( + .CI(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer[0]), + .LI(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_qxu[1]), + .O(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_s[1]) + ); + FDRE com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_1_ ( + .CE(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_set_2159), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_s[1]), + .Q(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer[1]), + .R(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_N_9729_i_2160) + ); + MUXCY_L com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_cry_2_ ( + .CI(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_cry[1]), + .DI(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_GND_2165), + .LO(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_cry[2]), + .S(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_qxu[2]) + ); + XORCY com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_s_2_ ( + .CI(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_cry[1]), + .LI(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_qxu[2]), + .O(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_s[2]) + ); + FDRE com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_2_ ( + .CE(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_set_2159), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_s[2]), + .Q(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer[2]), + .R(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_N_9729_i_2160) + ); + MUXCY_L com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_cry_3_ ( + .CI(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_cry[2]), + .DI(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_GND_2165), + .LO(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_cry[3]), + .S(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_qxu[3]) + ); + XORCY com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_s_3_ ( + .CI(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_cry[2]), + .LI(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_qxu[3]), + .O(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_s[3]) + ); + FDRE com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_3_ ( + .CE(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_set_2159), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_s[3]), + .Q(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer[3]), + .R(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_N_9729_i_2160) + ); + MUXCY_L com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_cry_4_ ( + .CI(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_cry[3]), + .DI(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_GND_2165), + .LO(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_cry[4]), + .S(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_qxu[4]) + ); + XORCY com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_s_4_ ( + .CI(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_cry[3]), + .LI(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_qxu[4]), + .O(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_s[4]) + ); + FDRE com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_4_ ( + .CE(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_set_2159), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_s[4]), + .Q(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer[4]), + .R(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_N_9729_i_2160) + ); + MUXCY_L com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_cry_5_ ( + .CI(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_cry[4]), + .DI(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_GND_2165), + .LO(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_cry[5]), + .S(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_qxu[5]) + ); + XORCY com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_s_5_ ( + .CI(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_cry[4]), + .LI(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_qxu[5]), + .O(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_s[5]) + ); + FDRE com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_5_ ( + .CE(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_set_2159), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_s[5]), + .Q(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer[5]), + .R(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_N_9729_i_2160) + ); + MUXCY_L com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_cry_6_ ( + .CI(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_cry[5]), + .DI(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_GND_2165), + .LO(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_cry[6]), + .S(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_qxu[6]) + ); + XORCY com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_s_6_ ( + .CI(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_cry[5]), + .LI(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_qxu[6]), + .O(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_s[6]) + ); + FDRE com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_6_ ( + .CE(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_set_2159), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_s[6]), + .Q(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer[6]), + .R(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_N_9729_i_2160) + ); + MUXCY_L com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_cry_7_ ( + .CI(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_cry[6]), + .DI(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_GND_2165), + .LO(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_cry[7]), + .S(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_qxu[7]) + ); + XORCY com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_s_7_ ( + .CI(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_cry[6]), + .LI(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_qxu[7]), + .O(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_s[7]) + ); + FDRE com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_7_ ( + .CE(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_set_2159), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_s[7]), + .Q(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer[7]), + .R(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_N_9729_i_2160) + ); + MUXCY_L com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_cry_8_ ( + .CI(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_cry[7]), + .DI(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_GND_2165), + .LO(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_cry[8]), + .S(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_qxu[8]) + ); + XORCY com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_s_8_ ( + .CI(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_cry[7]), + .LI(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_qxu[8]), + .O(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_s[8]) + ); + FDRE com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_8_ ( + .CE(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_set_2159), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_s[8]), + .Q(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer[8]), + .R(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_N_9729_i_2160) + ); + MUXCY_L com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_cry_9_ ( + .CI(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_cry[8]), + .DI(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_GND_2165), + .LO(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_cry[9]), + .S(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_qxu[9]) + ); + XORCY com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_s_9_ ( + .CI(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_cry[8]), + .LI(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_qxu[9]), + .O(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_s[9]) + ); + FDRE com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_9_ ( + .CE(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_set_2159), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_s[9]), + .Q(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer[9]), + .R(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_N_9729_i_2160) + ); + MUXCY_L com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_cry_10_ ( + .CI(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_cry[9]), + .DI(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_GND_2165), + .LO(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_cry[10]), + .S(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_qxu[10]) + ); + XORCY com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_s_10_ ( + .CI(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_cry[9]), + .LI(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_qxu[10]), + .O(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_s[10]) + ); + FDRE com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_10_ ( + .CE(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_set_2159), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_s[10]), + .Q(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer[10]), + .R(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_N_9729_i_2160) + ); + MUXCY_L com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_cry_11_ ( + .CI(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_cry[10]), + .DI(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_GND_2165), + .LO(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_cry[11]), + .S(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_qxu[11]) + ); + XORCY com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_s_11_ ( + .CI(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_cry[10]), + .LI(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_qxu[11]), + .O(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_s[11]) + ); + FDRE com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_11_ ( + .CE(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_set_2159), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_s[11]), + .Q(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer[11]), + .R(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_N_9729_i_2160) + ); + MUXCY_L com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_cry_12_ ( + .CI(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_cry[11]), + .DI(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_GND_2165), + .LO(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_cry[12]), + .S(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_qxu[12]) + ); + XORCY com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_s_12_ ( + .CI(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_cry[11]), + .LI(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_qxu[12]), + .O(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_s[12]) + ); + FDRE com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_12_ ( + .CE(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_set_2159), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_s[12]), + .Q(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer[12]), + .R(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_N_9729_i_2160) + ); + MUXCY_L com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_cry_13_ ( + .CI(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_cry[12]), + .DI(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_GND_2165), + .LO(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_cry[13]), + .S(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_qxu[13]) + ); + XORCY com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_s_13_ ( + .CI(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_cry[12]), + .LI(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_qxu[13]), + .O(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_s[13]) + ); + FDRE com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_13_ ( + .CE(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_set_2159), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_s[13]), + .Q(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer[13]), + .R(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_N_9729_i_2160) + ); + XORCY com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_s_14_ ( + .CI(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_cry[13]), + .LI(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_qxu[14]), + .O(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_s[14]) + ); + FDRE com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_14_ ( + .CE(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_set_2159), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_s[14]), + .Q(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer[14]), + .R(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_N_9729_i_2160) + ); + defparam com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_num21_0_a2.INIT = 4'h8; + LUT2 com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_num21_0_a2 ( + .I0(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_reg_same_last_ackd_tsn_2170), + .I1(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_vld_q_2171), + .O(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_num21) + ); + defparam com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_un1_replay_num21_4_1_0_a2.INIT = 4'h8; + LUT2 com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_un1_replay_num21_4_1_0_a2 ( + .I0(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_ANSeqNum_AckdSeq_q_2169), + .I1(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_NxtTxTSN_ANSeqNum_q_2167), + .O(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_N_8619_1) + ); + defparam com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_expire_5_0_a2_0_a2_0_a2.INIT = 4'h4; + LUT2 com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_expire_5_0_a2_0_a2_0_a2 ( + .I0(com_llm_link_status_0_), + .I1(com_replay_timer_expire_pre), + .O(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_expire_5) + ); + defparam com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_N_9729_i.INIT = 4'hB; + LUT2 com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_N_9729_i ( + .I0(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_clear_2161), + .I1(plm_link_up_1), + .O(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_N_9729_i_2160) + ); + defparam com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_N_69069_i.INIT = 8'hEC; + LUT3 com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_N_69069_i ( + .I0(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_waiting_2186), + .I1(com_reg_tx_update_retry_int), + .I2(com_reg_tx_update_retry_q), + .O(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_N_69069_i_2185) + ); + defparam com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_un1_replay_num21_1_i.INIT = 16'h007F; + LUT4 com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_un1_replay_num21_1_i ( + .I0(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_N_8619_1), + .I1(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_ANSeqNum_Eq_AckdSeq_q_2168), + .I2(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_reg_rx_dllp_nak_vld_qq_2166), + .I3(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_num21), + .O(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_un1_replay_num21_1_i_2162) + ); + defparam com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_num_7_i_o2_1_.INIT = 8'h02; + LUT3 com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_num_7_i_o2_1_ ( + .I0(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_N_8619_1), + .I1(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_ANSeqNum_Eq_AckdSeq_q_2168), + .I2(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_num21), + .O(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_N_18621_i) + ); + defparam com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_clear_3_i_0_0_a4_0_0.INIT = 4'h8; + LUT2 com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_clear_3_i_0_0_a4_0_0 ( + .I0(com_llm_llm_common_llm_common_reg_N_38195_i), + .I1(com_llm_llm_common_llm_common_reg_reg_rx_dllp_ack_vld_q_2033), + .O(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_clear_3_i_0_0_a4_0_0_2164) + ); + defparam com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_N_67880_i.INIT = 16'hEEFE; + LUT4 com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_N_67880_i ( + .I0(com_llm_link_status_0_), + .I1(com_replay_vld), + .I2(com_llm_llm_common_llm_common_reg_replay_timeout_flag), + .I3(com_reg_tx_update_retry_int), + .O(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_N_67880_i_2184) + ); + defparam com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_un1_replay_num_ac0.INIT = 4'h4; + LUT2 com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_un1_replay_num_ac0 ( + .I0(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_un1_replay_num21_1_i_2162), + .I1(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_num_5081[0]), + .O(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_un1_replay_num_c1) + ); + defparam com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_expire_pre_5_0_a2_0_a2_0_a2.INIT = 4'h4; + LUT2_L com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_expire_pre_5_0_a2_0_a2_0_a2 ( + .I0(com_llm_link_status_0_), + .I1(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_expire_pre_4), + .LO(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_expire_pre_5) + ); + defparam com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_num_7_i_2_.INIT = 16'h1450; + LUT4_L com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_num_7_i_2_ ( + .I0(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_N_18621_i), + .I1(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_num_5081[1]), + .I2(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_num[2]), + .I3(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_un1_replay_num_c1), + .LO(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_N_18614_i) + ); + defparam com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_num_7_i_1_.INIT = 8'h14; + LUT3_L com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_num_7_i_1_ ( + .I0(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_N_18621_i), + .I1(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_num_5081[1]), + .I2(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_un1_replay_num_c1), + .LO(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_N_18612_i) + ); + defparam com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_num_7_iv_0_m2_0_0_.INIT = 16'hE4B1; + LUT4_L com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_num_7_iv_0_m2_0_0_ ( + .I0(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_N_18621_i), + .I1(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_un1_replay_num21_1_i_2162), + .I2(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_reg_rx_dllp_nak_vld_qq_2166), + .I3(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_num_5081[0]), + .LO(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_num_7_iv_0_m2_0[0]) + ); + defparam com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_N_42787_i.INIT = 4'hE; + LUT2_L com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_N_42787_i ( + .I0(com_llm_link_status_0_), + .I1(com_lnk_tupdate_seq[11]), + .LO(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_N_42787_i_2172) + ); + defparam com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_N_42788_i.INIT = 4'hE; + LUT2_L com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_N_42788_i ( + .I0(com_llm_link_status_0_), + .I1(com_lnk_tupdate_seq[10]), + .LO(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_N_42788_i_2173) + ); + defparam com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_N_42789_i.INIT = 4'hE; + LUT2_L com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_N_42789_i ( + .I0(com_llm_link_status_0_), + .I1(com_lnk_tupdate_seq[9]), + .LO(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_N_42789_i_2174) + ); + defparam com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_N_42790_i.INIT = 4'hE; + LUT2_L com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_N_42790_i ( + .I0(com_llm_link_status_0_), + .I1(com_lnk_tupdate_seq[8]), + .LO(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_N_42790_i_2175) + ); + defparam com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_N_42791_i.INIT = 4'hE; + LUT2_L com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_N_42791_i ( + .I0(com_llm_link_status_0_), + .I1(com_lnk_tupdate_seq[7]), + .LO(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_N_42791_i_2176) + ); + defparam com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_N_42792_i.INIT = 4'hE; + LUT2_L com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_N_42792_i ( + .I0(com_llm_link_status_0_), + .I1(com_lnk_tupdate_seq[6]), + .LO(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_N_42792_i_2177) + ); + defparam com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_N_42793_i.INIT = 4'hE; + LUT2_L com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_N_42793_i ( + .I0(com_llm_link_status_0_), + .I1(com_lnk_tupdate_seq[5]), + .LO(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_N_42793_i_2178) + ); + defparam com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_N_42794_i.INIT = 4'hE; + LUT2_L com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_N_42794_i ( + .I0(com_llm_link_status_0_), + .I1(com_lnk_tupdate_seq[4]), + .LO(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_N_42794_i_2179) + ); + defparam com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_N_42795_i.INIT = 4'hE; + LUT2_L com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_N_42795_i ( + .I0(com_llm_link_status_0_), + .I1(com_lnk_tupdate_seq[3]), + .LO(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_N_42795_i_2180) + ); + defparam com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_N_42796_i.INIT = 4'hE; + LUT2_L com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_N_42796_i ( + .I0(com_llm_link_status_0_), + .I1(com_lnk_tupdate_seq[2]), + .LO(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_N_42796_i_2181) + ); + defparam com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_N_42797_i.INIT = 4'hE; + LUT2_L com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_N_42797_i ( + .I0(com_llm_link_status_0_), + .I1(com_lnk_tupdate_seq[1]), + .LO(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_N_42797_i_2182) + ); + defparam com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_N_42798_i.INIT = 4'hE; + LUT2_L com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_N_42798_i ( + .I0(com_llm_link_status_0_), + .I1(com_lnk_tupdate_seq[0]), + .LO(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_N_42798_i_2183) + ); + defparam com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timeout_flag17_0_a2_0_a2_0_a2.INIT = 4'h4; + LUT2_L com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timeout_flag17_0_a2_0_a2_0_a2 ( + .I0(com_replay_timer_expire), + .I1(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_expire_5), + .LO(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timeout_flag17) + ); + defparam com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_set_3_0_a2_0_a2_0_a4.INIT = 4'h4; + LUT2_L com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_set_3_0_a2_0_a2_0_a4 ( + .I0(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_I_19), + .I1(plm_link_l0), + .LO(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_set_3) + ); + defparam com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_N_67866_i.INIT = 16'hFEAA; + LUT4_L com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_N_67866_i ( + .I0(com_llm_link_status_0_), + .I1(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_clear_3_i_0_0_a4_0_0_2164), + .I2(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_waiting_2186), + .I3(plm_link_l0), + .LO(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_N_67866_i_2163) + ); + MUXCY com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_reg_same_last_ackd_tsn_3_0_I_19 ( + .CI(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_data_tmp_0[4]), + .DI(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_GND_2165), + .O(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_reg_same_last_ackd_tsn_3), + .S(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_N_27) + ); + MUXCY com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_expire_pre_4_0_I_64 ( + .CI(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_data_tmp[6]), + .DI(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_GND_2165), + .O(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_expire_pre_4), + .S(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_N_7_i) + ); + MUXCY com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_un1_diff_flag_0_I_19 ( + .CI(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_data_tmp[4]), + .DI(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_GND_2165), + .O(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_I_19), + .S(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_N_27_0) + ); + FDC com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_reg_rx_dllp_nak_vld_qq ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_common_llm_common_reg_reg_rx_dllp_nak_vld_q_2032), + .Q(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_reg_rx_dllp_nak_vld_qq_2166), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_NxtTxTSN_ANSeqNum_q ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_common_llm_common_reg_N_13526_i), + .Q(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_NxtTxTSN_ANSeqNum_q_2167), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_ANSeqNum_Eq_AckdSeq_q ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_common_llm_common_reg_ANSeqNum_Eq_AckdSeq_2040), + .Q(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_ANSeqNum_Eq_AckdSeq_q_2168), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_ANSeqNum_AckdSeq_q ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_common_llm_common_reg_N_13528_i), + .Q(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_ANSeqNum_AckdSeq_q_2169), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_reg_same_last_ackd_tsn ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_reg_same_last_ackd_tsn_3), + .Q(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_reg_same_last_ackd_tsn_2170), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_expire ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_expire_5), + .Q(com_replay_timer_expire), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_vld_q ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_replay_vld), + .Q(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_vld_q_2171), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_num_2_q_0_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_num[2]), + .Q(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_num_2_q[0]), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_expire_pre ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_expire_pre_5), + .Q(com_replay_timer_expire_pre), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_num_2_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_N_18614_i), + .Q(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_num[2]), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_num_1_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_N_18612_i), + .Q(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_num_5081[1]), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_num_0_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_num_7_iv_0_m2_0[0]), + .Q(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_num_5081[0]), + .CLR(plm_link_up_i) + ); + FDP com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_reg_tx_ackd_tsn_q_11_ ( + .PRE(plm_link_up_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_N_42787_i_2172), + .Q(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_reg_tx_ackd_tsn_q[11]) + ); + FDP com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_reg_tx_ackd_tsn_q_10_ ( + .PRE(plm_link_up_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_N_42788_i_2173), + .Q(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_reg_tx_ackd_tsn_q[10]) + ); + FDP com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_reg_tx_ackd_tsn_q_9_ ( + .PRE(plm_link_up_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_N_42789_i_2174), + .Q(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_reg_tx_ackd_tsn_q[9]) + ); + FDP com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_reg_tx_ackd_tsn_q_8_ ( + .PRE(plm_link_up_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_N_42790_i_2175), + .Q(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_reg_tx_ackd_tsn_q[8]) + ); + FDP com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_reg_tx_ackd_tsn_q_7_ ( + .PRE(plm_link_up_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_N_42791_i_2176), + .Q(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_reg_tx_ackd_tsn_q[7]) + ); + FDP com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_reg_tx_ackd_tsn_q_6_ ( + .PRE(plm_link_up_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_N_42792_i_2177), + .Q(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_reg_tx_ackd_tsn_q[6]) + ); + FDP com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_reg_tx_ackd_tsn_q_5_ ( + .PRE(plm_link_up_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_N_42793_i_2178), + .Q(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_reg_tx_ackd_tsn_q[5]) + ); + FDP com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_reg_tx_ackd_tsn_q_4_ ( + .PRE(plm_link_up_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_N_42794_i_2179), + .Q(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_reg_tx_ackd_tsn_q[4]) + ); + FDP com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_reg_tx_ackd_tsn_q_3_ ( + .PRE(plm_link_up_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_N_42795_i_2180), + .Q(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_reg_tx_ackd_tsn_q[3]) + ); + FDP com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_reg_tx_ackd_tsn_q_2_ ( + .PRE(plm_link_up_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_N_42796_i_2181), + .Q(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_reg_tx_ackd_tsn_q[2]) + ); + FDP com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_reg_tx_ackd_tsn_q_1_ ( + .PRE(plm_link_up_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_N_42797_i_2182), + .Q(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_reg_tx_ackd_tsn_q[1]) + ); + FDP com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_reg_tx_ackd_tsn_q_0_ ( + .PRE(plm_link_up_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_N_42798_i_2183), + .Q(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_reg_tx_ackd_tsn_q[0]) + ); + FDCE com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timeout_flag ( + .CE(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_N_67880_i_2184), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timeout_flag17), + .Q(com_llm_llm_common_llm_common_reg_replay_timeout_flag), + .CLR(plm_link_up_i) + ); + FDCE com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_waiting ( + .CE(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_N_69069_i_2185), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_reg_tx_update_retry_int), + .Q(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_waiting_2186), + .CLR(plm_link_up_i) + ); + defparam com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_qxu_0_0_.INIT = 4'h2; + LUT1_L com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_qxu_0_0_ ( + .I0(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer[0]), + .LO(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_qxu[0]) + ); + defparam com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_qxu_0_14_.INIT = 4'h2; + LUT1_L com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_qxu_0_14_ ( + .I0(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer[14]), + .LO(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_qxu[14]) + ); + defparam com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_qxu_0_13_.INIT = 4'h2; + LUT1_L com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_qxu_0_13_ ( + .I0(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer[13]), + .LO(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_qxu[13]) + ); + defparam com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_qxu_0_12_.INIT = 4'h2; + LUT1_L com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_qxu_0_12_ ( + .I0(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer[12]), + .LO(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_qxu[12]) + ); + defparam com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_qxu_0_11_.INIT = 4'h2; + LUT1_L com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_qxu_0_11_ ( + .I0(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer[11]), + .LO(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_qxu[11]) + ); + defparam com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_qxu_0_10_.INIT = 4'h2; + LUT1_L com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_qxu_0_10_ ( + .I0(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer[10]), + .LO(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_qxu[10]) + ); + defparam com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_qxu_0_9_.INIT = 4'h2; + LUT1_L com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_qxu_0_9_ ( + .I0(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer[9]), + .LO(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_qxu[9]) + ); + defparam com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_qxu_0_8_.INIT = 4'h2; + LUT1_L com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_qxu_0_8_ ( + .I0(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer[8]), + .LO(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_qxu[8]) + ); + defparam com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_qxu_0_7_.INIT = 4'h2; + LUT1_L com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_qxu_0_7_ ( + .I0(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer[7]), + .LO(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_qxu[7]) + ); + defparam com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_qxu_0_6_.INIT = 4'h2; + LUT1_L com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_qxu_0_6_ ( + .I0(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer[6]), + .LO(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_qxu[6]) + ); + defparam com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_qxu_0_5_.INIT = 4'h2; + LUT1_L com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_qxu_0_5_ ( + .I0(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer[5]), + .LO(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_qxu[5]) + ); + defparam com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_qxu_0_4_.INIT = 4'h2; + LUT1_L com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_qxu_0_4_ ( + .I0(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer[4]), + .LO(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_qxu[4]) + ); + defparam com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_qxu_0_3_.INIT = 4'h2; + LUT1_L com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_qxu_0_3_ ( + .I0(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer[3]), + .LO(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_qxu[3]) + ); + defparam com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_qxu_0_2_.INIT = 4'h2; + LUT1_L com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_qxu_0_2_ ( + .I0(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer[2]), + .LO(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_qxu[2]) + ); + defparam com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_qxu_0_1_.INIT = 4'h2; + LUT1_L com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_qxu_0_1_ ( + .I0(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer[1]), + .LO(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_qxu[1]) + ); + defparam com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_s_0_.INIT = 4'h1; + LUT1_L com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_s_0_ ( + .I0(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_qxu[0]), + .LO(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_s[0]) + ); + defparam com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_un1_diff_flag_0_I_27.INIT = 16'h8421; + LUT4 com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_un1_diff_flag_0_I_27 ( + .I0(com_lnk_ttrans_seq[10]), + .I1(com_lnk_ttrans_seq[11]), + .I2(com_lnk_tupdate_seq[10]), + .I3(com_lnk_tupdate_seq[11]), + .O(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_N_27_0) + ); + defparam com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_expire_pre_4_0_N_7_i.INIT = 4'h9; + LUT2 com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_expire_pre_4_0_N_7_i ( + .I0(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_q[14]), + .I1(com_llm_llm_common_reg_replay_to_val[14]), + .O(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_N_7_i) + ); + defparam com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_reg_same_last_ackd_tsn_3_0_I_27.INIT = 16'h8421; + LUT4 com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_reg_same_last_ackd_tsn_3_0_I_27 ( + .I0(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_reg_tx_ackd_tsn_q[10]), + .I1(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_reg_tx_ackd_tsn_q[11]), + .I2(com_lnk_tupdate_seq[10]), + .I3(com_lnk_tupdate_seq[11]), + .O(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_N_27) + ); + defparam com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_reg_same_last_ackd_tsn_3_0_I_54.INIT = 16'h8421; + LUT4 com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_reg_same_last_ackd_tsn_3_0_I_54 ( + .I0(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_reg_tx_ackd_tsn_q[2]), + .I1(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_reg_tx_ackd_tsn_q[3]), + .I2(com_lnk_tupdate_seq[2]), + .I3(com_lnk_tupdate_seq[3]), + .O(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_N_3_0) + ); + defparam com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_reg_same_last_ackd_tsn_3_0_I_45.INIT = 16'h8421; + LUT4 com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_reg_same_last_ackd_tsn_3_0_I_45 ( + .I0(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_reg_tx_ackd_tsn_q[8]), + .I1(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_reg_tx_ackd_tsn_q[9]), + .I2(com_lnk_tupdate_seq[8]), + .I3(com_lnk_tupdate_seq[9]), + .O(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_N_11_0) + ); + defparam com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_reg_same_last_ackd_tsn_3_0_I_36.INIT = 16'h8421; + LUT4 com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_reg_same_last_ackd_tsn_3_0_I_36 ( + .I0(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_reg_tx_ackd_tsn_q[6]), + .I1(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_reg_tx_ackd_tsn_q[7]), + .I2(com_lnk_tupdate_seq[6]), + .I3(com_lnk_tupdate_seq[7]), + .O(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_N_19_0) + ); + defparam com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_reg_same_last_ackd_tsn_3_0_I_18.INIT = 16'h8421; + LUT4 com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_reg_same_last_ackd_tsn_3_0_I_18 ( + .I0(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_reg_tx_ackd_tsn_q[4]), + .I1(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_reg_tx_ackd_tsn_q[5]), + .I2(com_lnk_tupdate_seq[4]), + .I3(com_lnk_tupdate_seq[5]), + .O(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_N_35_0) + ); + defparam com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_reg_same_last_ackd_tsn_3_0_I_9.INIT = 16'h8421; + LUT4 com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_reg_same_last_ackd_tsn_3_0_I_9 ( + .I0(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_reg_tx_ackd_tsn_q[0]), + .I1(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_reg_tx_ackd_tsn_q[1]), + .I2(com_lnk_tupdate_seq[0]), + .I3(com_lnk_tupdate_seq[1]), + .O(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_N_43_0) + ); + defparam com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_expire_pre_4_0_I_63.INIT = 16'h8421; + LUT4 com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_expire_pre_4_0_I_63 ( + .I0(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_q[12]), + .I1(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_q[13]), + .I2(com_llm_llm_common_reg_replay_to_val[12]), + .I3(com_llm_llm_common_reg_replay_to_val[13]), + .O(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_N_9) + ); + defparam com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_expire_pre_4_0_I_54.INIT = 16'h8421; + LUT4 com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_expire_pre_4_0_I_54 ( + .I0(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_q[10]), + .I1(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_q[11]), + .I2(com_llm_llm_common_reg_replay_to_val[10]), + .I3(com_llm_llm_common_reg_replay_to_val[11]), + .O(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_N_17) + ); + defparam com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_expire_pre_4_0_I_45.INIT = 16'h8421; + LUT4 com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_expire_pre_4_0_I_45 ( + .I0(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_q[8]), + .I1(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_q[9]), + .I2(com_llm_llm_common_reg_replay_to_val[8]), + .I3(com_llm_llm_common_reg_replay_to_val[9]), + .O(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_N_25) + ); + defparam com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_expire_pre_4_0_I_36.INIT = 16'h8421; + LUT4 com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_expire_pre_4_0_I_36 ( + .I0(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_q[6]), + .I1(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_q[7]), + .I2(com_llm_llm_common_reg_replay_to_val[6]), + .I3(com_llm_llm_common_reg_replay_to_val[7]), + .O(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_N_33) + ); + defparam com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_expire_pre_4_0_I_27.INIT = 16'h8421; + LUT4 com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_expire_pre_4_0_I_27 ( + .I0(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_q[4]), + .I1(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_q[5]), + .I2(com_llm_llm_common_reg_replay_to_val[4]), + .I3(com_llm_llm_common_reg_replay_to_val[5]), + .O(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_N_41) + ); + defparam com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_expire_pre_4_0_I_18.INIT = 16'h8421; + LUT4 com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_expire_pre_4_0_I_18 ( + .I0(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_q[2]), + .I1(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_q[3]), + .I2(com_llm_llm_common_reg_replay_to_val[2]), + .I3(com_llm_llm_common_reg_replay_to_val[3]), + .O(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_N_49) + ); + defparam com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_expire_pre_4_0_I_9.INIT = 16'h8421; + LUT4 com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_expire_pre_4_0_I_9 ( + .I0(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_q[0]), + .I1(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_q[1]), + .I2(com_llm_llm_common_reg_replay_to_val[0]), + .I3(com_llm_llm_common_reg_replay_to_val[1]), + .O(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_N_57) + ); + defparam com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_un1_diff_flag_0_I_54.INIT = 16'h8421; + LUT4 com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_un1_diff_flag_0_I_54 ( + .I0(com_lnk_ttrans_seq[2]), + .I1(com_lnk_ttrans_seq[3]), + .I2(com_lnk_tupdate_seq[2]), + .I3(com_lnk_tupdate_seq[3]), + .O(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_N_3) + ); + defparam com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_un1_diff_flag_0_I_45.INIT = 16'h8421; + LUT4 com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_un1_diff_flag_0_I_45 ( + .I0(com_lnk_ttrans_seq[8]), + .I1(com_lnk_ttrans_seq[9]), + .I2(com_lnk_tupdate_seq[8]), + .I3(com_lnk_tupdate_seq[9]), + .O(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_N_11) + ); + defparam com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_un1_diff_flag_0_I_36.INIT = 16'h8421; + LUT4 com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_un1_diff_flag_0_I_36 ( + .I0(com_lnk_ttrans_seq[6]), + .I1(com_lnk_ttrans_seq[7]), + .I2(com_lnk_tupdate_seq[6]), + .I3(com_lnk_tupdate_seq[7]), + .O(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_N_19) + ); + defparam com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_un1_diff_flag_0_I_18.INIT = 16'h8421; + LUT4 com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_un1_diff_flag_0_I_18 ( + .I0(com_lnk_ttrans_seq[4]), + .I1(com_lnk_ttrans_seq[5]), + .I2(com_lnk_tupdate_seq[4]), + .I3(com_lnk_tupdate_seq[5]), + .O(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_N_35) + ); + defparam com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_un1_diff_flag_0_I_9.INIT = 16'h8421; + LUT4 com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_un1_diff_flag_0_I_9 ( + .I0(com_lnk_ttrans_seq[0]), + .I1(com_lnk_ttrans_seq[1]), + .I2(com_lnk_tupdate_seq[0]), + .I3(com_lnk_tupdate_seq[1]), + .O(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_N_43) + ); + GND com_llm_llm_common_llm_common_reg_llm_next_rcv_tsn_GND ( + .G(com_llm_llm_common_llm_common_reg_llm_next_rcv_tsn_GND_2187) + ); + MUXCY_L com_llm_llm_common_llm_common_reg_llm_next_rcv_tsn_out_cry_0_ ( + .CI(com_llm_llm_common_link_status_i[0]), + .DI(com_llm_llm_common_llm_common_reg_llm_next_rcv_tsn_GND_2187), + .LO(com_llm_llm_common_llm_common_reg_llm_next_rcv_tsn_out_cry[0]), + .S(com_llm_llm_common_llm_common_reg_llm_next_rcv_tsn_out_qxu[0]) + ); + XORCY com_llm_llm_common_llm_common_reg_llm_next_rcv_tsn_out_s_0_ ( + .CI(com_llm_llm_common_link_status_i[0]), + .LI(com_llm_llm_common_llm_common_reg_llm_next_rcv_tsn_out_qxu[0]), + .O(com_llm_llm_common_llm_common_reg_llm_next_rcv_tsn_out_s[0]) + ); + MUXCY_L com_llm_llm_common_llm_common_reg_llm_next_rcv_tsn_out_cry_1_ ( + .CI(com_llm_llm_common_llm_common_reg_llm_next_rcv_tsn_out_cry[0]), + .DI(com_llm_llm_common_llm_common_reg_llm_next_rcv_tsn_GND_2187), + .LO(com_llm_llm_common_llm_common_reg_llm_next_rcv_tsn_out_cry[1]), + .S(com_llm_llm_common_llm_common_reg_llm_next_rcv_tsn_out_qxu[1]) + ); + XORCY com_llm_llm_common_llm_common_reg_llm_next_rcv_tsn_out_s_1_ ( + .CI(com_llm_llm_common_llm_common_reg_llm_next_rcv_tsn_out_cry[0]), + .LI(com_llm_llm_common_llm_common_reg_llm_next_rcv_tsn_out_qxu[1]), + .O(com_llm_llm_common_llm_common_reg_llm_next_rcv_tsn_out_s[1]) + ); + MUXCY_L com_llm_llm_common_llm_common_reg_llm_next_rcv_tsn_out_cry_2_ ( + .CI(com_llm_llm_common_llm_common_reg_llm_next_rcv_tsn_out_cry[1]), + .DI(com_llm_llm_common_llm_common_reg_llm_next_rcv_tsn_GND_2187), + .LO(com_llm_llm_common_llm_common_reg_llm_next_rcv_tsn_out_cry[2]), + .S(com_llm_llm_common_llm_common_reg_llm_next_rcv_tsn_out_qxu[2]) + ); + XORCY com_llm_llm_common_llm_common_reg_llm_next_rcv_tsn_out_s_2_ ( + .CI(com_llm_llm_common_llm_common_reg_llm_next_rcv_tsn_out_cry[1]), + .LI(com_llm_llm_common_llm_common_reg_llm_next_rcv_tsn_out_qxu[2]), + .O(com_llm_llm_common_llm_common_reg_llm_next_rcv_tsn_out_s[2]) + ); + MUXCY_L com_llm_llm_common_llm_common_reg_llm_next_rcv_tsn_out_cry_3_ ( + .CI(com_llm_llm_common_llm_common_reg_llm_next_rcv_tsn_out_cry[2]), + .DI(com_llm_llm_common_llm_common_reg_llm_next_rcv_tsn_GND_2187), + .LO(com_llm_llm_common_llm_common_reg_llm_next_rcv_tsn_out_cry[3]), + .S(com_llm_llm_common_llm_common_reg_llm_next_rcv_tsn_out_qxu[3]) + ); + XORCY com_llm_llm_common_llm_common_reg_llm_next_rcv_tsn_out_s_3_ ( + .CI(com_llm_llm_common_llm_common_reg_llm_next_rcv_tsn_out_cry[2]), + .LI(com_llm_llm_common_llm_common_reg_llm_next_rcv_tsn_out_qxu[3]), + .O(com_llm_llm_common_llm_common_reg_llm_next_rcv_tsn_out_s[3]) + ); + MUXCY_L com_llm_llm_common_llm_common_reg_llm_next_rcv_tsn_out_cry_4_ ( + .CI(com_llm_llm_common_llm_common_reg_llm_next_rcv_tsn_out_cry[3]), + .DI(com_llm_llm_common_llm_common_reg_llm_next_rcv_tsn_GND_2187), + .LO(com_llm_llm_common_llm_common_reg_llm_next_rcv_tsn_out_cry[4]), + .S(com_llm_llm_common_llm_common_reg_llm_next_rcv_tsn_out_qxu[4]) + ); + XORCY com_llm_llm_common_llm_common_reg_llm_next_rcv_tsn_out_s_4_ ( + .CI(com_llm_llm_common_llm_common_reg_llm_next_rcv_tsn_out_cry[3]), + .LI(com_llm_llm_common_llm_common_reg_llm_next_rcv_tsn_out_qxu[4]), + .O(com_llm_llm_common_llm_common_reg_llm_next_rcv_tsn_out_s[4]) + ); + MUXCY_L com_llm_llm_common_llm_common_reg_llm_next_rcv_tsn_out_cry_5_ ( + .CI(com_llm_llm_common_llm_common_reg_llm_next_rcv_tsn_out_cry[4]), + .DI(com_llm_llm_common_llm_common_reg_llm_next_rcv_tsn_GND_2187), + .LO(com_llm_llm_common_llm_common_reg_llm_next_rcv_tsn_out_cry[5]), + .S(com_llm_llm_common_llm_common_reg_llm_next_rcv_tsn_out_qxu[5]) + ); + XORCY com_llm_llm_common_llm_common_reg_llm_next_rcv_tsn_out_s_5_ ( + .CI(com_llm_llm_common_llm_common_reg_llm_next_rcv_tsn_out_cry[4]), + .LI(com_llm_llm_common_llm_common_reg_llm_next_rcv_tsn_out_qxu[5]), + .O(com_llm_llm_common_llm_common_reg_llm_next_rcv_tsn_out_s[5]) + ); + MUXCY_L com_llm_llm_common_llm_common_reg_llm_next_rcv_tsn_out_cry_6_ ( + .CI(com_llm_llm_common_llm_common_reg_llm_next_rcv_tsn_out_cry[5]), + .DI(com_llm_llm_common_llm_common_reg_llm_next_rcv_tsn_GND_2187), + .LO(com_llm_llm_common_llm_common_reg_llm_next_rcv_tsn_out_cry[6]), + .S(com_llm_llm_common_llm_common_reg_llm_next_rcv_tsn_out_qxu[6]) + ); + XORCY com_llm_llm_common_llm_common_reg_llm_next_rcv_tsn_out_s_6_ ( + .CI(com_llm_llm_common_llm_common_reg_llm_next_rcv_tsn_out_cry[5]), + .LI(com_llm_llm_common_llm_common_reg_llm_next_rcv_tsn_out_qxu[6]), + .O(com_llm_llm_common_llm_common_reg_llm_next_rcv_tsn_out_s[6]) + ); + MUXCY_L com_llm_llm_common_llm_common_reg_llm_next_rcv_tsn_out_cry_7_ ( + .CI(com_llm_llm_common_llm_common_reg_llm_next_rcv_tsn_out_cry[6]), + .DI(com_llm_llm_common_llm_common_reg_llm_next_rcv_tsn_GND_2187), + .LO(com_llm_llm_common_llm_common_reg_llm_next_rcv_tsn_out_cry[7]), + .S(com_llm_llm_common_llm_common_reg_llm_next_rcv_tsn_out_qxu[7]) + ); + XORCY com_llm_llm_common_llm_common_reg_llm_next_rcv_tsn_out_s_7_ ( + .CI(com_llm_llm_common_llm_common_reg_llm_next_rcv_tsn_out_cry[6]), + .LI(com_llm_llm_common_llm_common_reg_llm_next_rcv_tsn_out_qxu[7]), + .O(com_llm_llm_common_llm_common_reg_llm_next_rcv_tsn_out_s[7]) + ); + MUXCY_L com_llm_llm_common_llm_common_reg_llm_next_rcv_tsn_out_cry_8_ ( + .CI(com_llm_llm_common_llm_common_reg_llm_next_rcv_tsn_out_cry[7]), + .DI(com_llm_llm_common_llm_common_reg_llm_next_rcv_tsn_GND_2187), + .LO(com_llm_llm_common_llm_common_reg_llm_next_rcv_tsn_out_cry[8]), + .S(com_llm_llm_common_llm_common_reg_llm_next_rcv_tsn_out_qxu[8]) + ); + XORCY com_llm_llm_common_llm_common_reg_llm_next_rcv_tsn_out_s_8_ ( + .CI(com_llm_llm_common_llm_common_reg_llm_next_rcv_tsn_out_cry[7]), + .LI(com_llm_llm_common_llm_common_reg_llm_next_rcv_tsn_out_qxu[8]), + .O(com_llm_llm_common_llm_common_reg_llm_next_rcv_tsn_out_s[8]) + ); + MUXCY_L com_llm_llm_common_llm_common_reg_llm_next_rcv_tsn_out_cry_9_ ( + .CI(com_llm_llm_common_llm_common_reg_llm_next_rcv_tsn_out_cry[8]), + .DI(com_llm_llm_common_llm_common_reg_llm_next_rcv_tsn_GND_2187), + .LO(com_llm_llm_common_llm_common_reg_llm_next_rcv_tsn_out_cry[9]), + .S(com_llm_llm_common_llm_common_reg_llm_next_rcv_tsn_out_qxu[9]) + ); + XORCY com_llm_llm_common_llm_common_reg_llm_next_rcv_tsn_out_s_9_ ( + .CI(com_llm_llm_common_llm_common_reg_llm_next_rcv_tsn_out_cry[8]), + .LI(com_llm_llm_common_llm_common_reg_llm_next_rcv_tsn_out_qxu[9]), + .O(com_llm_llm_common_llm_common_reg_llm_next_rcv_tsn_out_s[9]) + ); + MUXCY_L com_llm_llm_common_llm_common_reg_llm_next_rcv_tsn_out_cry_10_ ( + .CI(com_llm_llm_common_llm_common_reg_llm_next_rcv_tsn_out_cry[9]), + .DI(com_llm_llm_common_llm_common_reg_llm_next_rcv_tsn_GND_2187), + .LO(com_llm_llm_common_llm_common_reg_llm_next_rcv_tsn_out_cry[10]), + .S(com_llm_llm_common_llm_common_reg_llm_next_rcv_tsn_out_qxu[10]) + ); + XORCY com_llm_llm_common_llm_common_reg_llm_next_rcv_tsn_out_s_10_ ( + .CI(com_llm_llm_common_llm_common_reg_llm_next_rcv_tsn_out_cry[9]), + .LI(com_llm_llm_common_llm_common_reg_llm_next_rcv_tsn_out_qxu[10]), + .O(com_llm_llm_common_llm_common_reg_llm_next_rcv_tsn_out_s[10]) + ); + XORCY com_llm_llm_common_llm_common_reg_llm_next_rcv_tsn_out_s_11_ ( + .CI(com_llm_llm_common_llm_common_reg_llm_next_rcv_tsn_out_cry[10]), + .LI(com_llm_llm_common_llm_common_reg_llm_next_rcv_tsn_out_qxu[11]), + .O(com_llm_llm_common_llm_common_reg_llm_next_rcv_tsn_out_s[11]) + ); + defparam com_llm_llm_common_llm_common_reg_llm_next_rcv_tsn_N_69071_i.INIT = 8'hF8; + LUT3 com_llm_llm_common_llm_common_reg_llm_next_rcv_tsn_N_69071_i ( + .I0(com_llm_llm_common_llm_common_reg_N_30966_1), + .I1(com_llm_reg_rx_tlp_tsn_err_0_a2_0_a2_0_a2_0_a4), + .I2(com_llm_link_status_0_), + .O(com_llm_llm_common_llm_common_reg_N_69071_i) + ); + FDCE com_llm_llm_common_llm_common_reg_llm_next_rcv_tsn_out_11_ ( + .CE(com_llm_llm_common_llm_common_reg_N_69071_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_common_llm_common_reg_llm_next_rcv_tsn_out_s[11]), + .Q(com_llm_reg_next_rcv_tsn[11]), + .CLR(com_llm_llm_common_llm_common_reg_lnk_sys_reset_n_0_a2_0_a2_0_a2_2001) + ); + FDCE com_llm_llm_common_llm_common_reg_llm_next_rcv_tsn_out_10_ ( + .CE(com_llm_llm_common_llm_common_reg_N_69071_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_common_llm_common_reg_llm_next_rcv_tsn_out_s[10]), + .Q(com_llm_reg_next_rcv_tsn[10]), + .CLR(com_llm_llm_common_llm_common_reg_lnk_sys_reset_n_0_a2_0_a2_0_a2_2001) + ); + FDCE com_llm_llm_common_llm_common_reg_llm_next_rcv_tsn_out_9_ ( + .CE(com_llm_llm_common_llm_common_reg_N_69071_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_common_llm_common_reg_llm_next_rcv_tsn_out_s[9]), + .Q(com_llm_reg_next_rcv_tsn[9]), + .CLR(com_llm_llm_common_llm_common_reg_lnk_sys_reset_n_0_a2_0_a2_0_a2_2001) + ); + FDCE com_llm_llm_common_llm_common_reg_llm_next_rcv_tsn_out_8_ ( + .CE(com_llm_llm_common_llm_common_reg_N_69071_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_common_llm_common_reg_llm_next_rcv_tsn_out_s[8]), + .Q(com_llm_reg_next_rcv_tsn[8]), + .CLR(com_llm_llm_common_llm_common_reg_lnk_sys_reset_n_0_a2_0_a2_0_a2_2001) + ); + FDCE com_llm_llm_common_llm_common_reg_llm_next_rcv_tsn_out_7_ ( + .CE(com_llm_llm_common_llm_common_reg_N_69071_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_common_llm_common_reg_llm_next_rcv_tsn_out_s[7]), + .Q(com_llm_reg_next_rcv_tsn[7]), + .CLR(com_llm_llm_common_llm_common_reg_lnk_sys_reset_n_0_a2_0_a2_0_a2_2001) + ); + FDCE com_llm_llm_common_llm_common_reg_llm_next_rcv_tsn_out_6_ ( + .CE(com_llm_llm_common_llm_common_reg_N_69071_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_common_llm_common_reg_llm_next_rcv_tsn_out_s[6]), + .Q(com_llm_reg_next_rcv_tsn[6]), + .CLR(com_llm_llm_common_llm_common_reg_lnk_sys_reset_n_0_a2_0_a2_0_a2_2001) + ); + FDCE com_llm_llm_common_llm_common_reg_llm_next_rcv_tsn_out_5_ ( + .CE(com_llm_llm_common_llm_common_reg_N_69071_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_common_llm_common_reg_llm_next_rcv_tsn_out_s[5]), + .Q(com_llm_reg_next_rcv_tsn[5]), + .CLR(com_llm_llm_common_llm_common_reg_lnk_sys_reset_n_0_a2_0_a2_0_a2_2001) + ); + FDCE com_llm_llm_common_llm_common_reg_llm_next_rcv_tsn_out_4_ ( + .CE(com_llm_llm_common_llm_common_reg_N_69071_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_common_llm_common_reg_llm_next_rcv_tsn_out_s[4]), + .Q(com_llm_reg_next_rcv_tsn[4]), + .CLR(com_llm_llm_common_llm_common_reg_lnk_sys_reset_n_0_a2_0_a2_0_a2_2001) + ); + FDCE com_llm_llm_common_llm_common_reg_llm_next_rcv_tsn_out_3_ ( + .CE(com_llm_llm_common_llm_common_reg_N_69071_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_common_llm_common_reg_llm_next_rcv_tsn_out_s[3]), + .Q(com_llm_reg_next_rcv_tsn[3]), + .CLR(com_llm_llm_common_llm_common_reg_lnk_sys_reset_n_0_a2_0_a2_0_a2_2001) + ); + FDCE com_llm_llm_common_llm_common_reg_llm_next_rcv_tsn_out_2_ ( + .CE(com_llm_llm_common_llm_common_reg_N_69071_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_common_llm_common_reg_llm_next_rcv_tsn_out_s[2]), + .Q(com_llm_reg_next_rcv_tsn[2]), + .CLR(com_llm_llm_common_llm_common_reg_lnk_sys_reset_n_0_a2_0_a2_0_a2_2001) + ); + FDCE com_llm_llm_common_llm_common_reg_llm_next_rcv_tsn_out_1_ ( + .CE(com_llm_llm_common_llm_common_reg_N_69071_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_common_llm_common_reg_llm_next_rcv_tsn_out_s[1]), + .Q(com_llm_reg_next_rcv_tsn[1]), + .CLR(com_llm_llm_common_llm_common_reg_lnk_sys_reset_n_0_a2_0_a2_0_a2_2001) + ); + FDCE com_llm_llm_common_llm_common_reg_llm_next_rcv_tsn_out_0_ ( + .CE(com_llm_llm_common_llm_common_reg_N_69071_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_common_llm_common_reg_llm_next_rcv_tsn_out_s[0]), + .Q(com_llm_reg_next_rcv_tsn[0]), + .CLR(com_llm_llm_common_llm_common_reg_lnk_sys_reset_n_0_a2_0_a2_0_a2_2001) + ); + defparam com_llm_llm_common_llm_common_reg_llm_next_rcv_tsn_out_qxu_0_0_.INIT = 4'h4; + LUT2_L com_llm_llm_common_llm_common_reg_llm_next_rcv_tsn_out_qxu_0_0_ ( + .I0(com_llm_link_status_0_), + .I1(com_llm_reg_next_rcv_tsn[0]), + .LO(com_llm_llm_common_llm_common_reg_llm_next_rcv_tsn_out_qxu[0]) + ); + defparam com_llm_llm_common_llm_common_reg_llm_next_rcv_tsn_out_qxu_0_1_.INIT = 4'h4; + LUT2_L com_llm_llm_common_llm_common_reg_llm_next_rcv_tsn_out_qxu_0_1_ ( + .I0(com_llm_link_status_0_), + .I1(com_llm_reg_next_rcv_tsn[1]), + .LO(com_llm_llm_common_llm_common_reg_llm_next_rcv_tsn_out_qxu[1]) + ); + defparam com_llm_llm_common_llm_common_reg_llm_next_rcv_tsn_out_qxu_0_2_.INIT = 4'h4; + LUT2_L com_llm_llm_common_llm_common_reg_llm_next_rcv_tsn_out_qxu_0_2_ ( + .I0(com_llm_link_status_0_), + .I1(com_llm_reg_next_rcv_tsn[2]), + .LO(com_llm_llm_common_llm_common_reg_llm_next_rcv_tsn_out_qxu[2]) + ); + defparam com_llm_llm_common_llm_common_reg_llm_next_rcv_tsn_out_qxu_0_3_.INIT = 4'h4; + LUT2_L com_llm_llm_common_llm_common_reg_llm_next_rcv_tsn_out_qxu_0_3_ ( + .I0(com_llm_link_status_0_), + .I1(com_llm_reg_next_rcv_tsn[3]), + .LO(com_llm_llm_common_llm_common_reg_llm_next_rcv_tsn_out_qxu[3]) + ); + defparam com_llm_llm_common_llm_common_reg_llm_next_rcv_tsn_out_qxu_0_4_.INIT = 4'h4; + LUT2_L com_llm_llm_common_llm_common_reg_llm_next_rcv_tsn_out_qxu_0_4_ ( + .I0(com_llm_link_status_0_), + .I1(com_llm_reg_next_rcv_tsn[4]), + .LO(com_llm_llm_common_llm_common_reg_llm_next_rcv_tsn_out_qxu[4]) + ); + defparam com_llm_llm_common_llm_common_reg_llm_next_rcv_tsn_out_qxu_0_5_.INIT = 4'h4; + LUT2_L com_llm_llm_common_llm_common_reg_llm_next_rcv_tsn_out_qxu_0_5_ ( + .I0(com_llm_link_status_0_), + .I1(com_llm_reg_next_rcv_tsn[5]), + .LO(com_llm_llm_common_llm_common_reg_llm_next_rcv_tsn_out_qxu[5]) + ); + defparam com_llm_llm_common_llm_common_reg_llm_next_rcv_tsn_out_qxu_0_6_.INIT = 4'h4; + LUT2_L com_llm_llm_common_llm_common_reg_llm_next_rcv_tsn_out_qxu_0_6_ ( + .I0(com_llm_link_status_0_), + .I1(com_llm_reg_next_rcv_tsn[6]), + .LO(com_llm_llm_common_llm_common_reg_llm_next_rcv_tsn_out_qxu[6]) + ); + defparam com_llm_llm_common_llm_common_reg_llm_next_rcv_tsn_out_qxu_0_7_.INIT = 4'h4; + LUT2_L com_llm_llm_common_llm_common_reg_llm_next_rcv_tsn_out_qxu_0_7_ ( + .I0(com_llm_link_status_0_), + .I1(com_llm_reg_next_rcv_tsn[7]), + .LO(com_llm_llm_common_llm_common_reg_llm_next_rcv_tsn_out_qxu[7]) + ); + defparam com_llm_llm_common_llm_common_reg_llm_next_rcv_tsn_out_qxu_0_8_.INIT = 4'h4; + LUT2_L com_llm_llm_common_llm_common_reg_llm_next_rcv_tsn_out_qxu_0_8_ ( + .I0(com_llm_link_status_0_), + .I1(com_llm_reg_next_rcv_tsn[8]), + .LO(com_llm_llm_common_llm_common_reg_llm_next_rcv_tsn_out_qxu[8]) + ); + defparam com_llm_llm_common_llm_common_reg_llm_next_rcv_tsn_out_qxu_0_9_.INIT = 4'h4; + LUT2_L com_llm_llm_common_llm_common_reg_llm_next_rcv_tsn_out_qxu_0_9_ ( + .I0(com_llm_link_status_0_), + .I1(com_llm_reg_next_rcv_tsn[9]), + .LO(com_llm_llm_common_llm_common_reg_llm_next_rcv_tsn_out_qxu[9]) + ); + defparam com_llm_llm_common_llm_common_reg_llm_next_rcv_tsn_out_qxu_0_10_.INIT = 4'h4; + LUT2_L com_llm_llm_common_llm_common_reg_llm_next_rcv_tsn_out_qxu_0_10_ ( + .I0(com_llm_link_status_0_), + .I1(com_llm_reg_next_rcv_tsn[10]), + .LO(com_llm_llm_common_llm_common_reg_llm_next_rcv_tsn_out_qxu[10]) + ); + defparam com_llm_llm_common_llm_common_reg_llm_next_rcv_tsn_out_qxu_0_11_.INIT = 4'h4; + LUT2_L com_llm_llm_common_llm_common_reg_llm_next_rcv_tsn_out_qxu_0_11_ ( + .I0(com_llm_link_status_0_), + .I1(com_llm_reg_next_rcv_tsn[11]), + .LO(com_llm_llm_common_llm_common_reg_llm_next_rcv_tsn_out_qxu[11]) + ); + GND com_tlm_u_tlm_tx_data_src_GND ( + .G(com_tlm_u_tlm_tx_data_src_GND_2189) + ); + FDR com_tlm_u_tlm_tx_data_src_stat_tlp_wr_ep_o ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_data_src_stat_tlp_wr_ep_o_5), + .Q(com_cmmt_stat_tlp_tx_wr_ep), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_tx_data_src_cfg_sent_o ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_data_src_cfg_sent_d_2188), + .Q(com_tlm_u_tlm_tx_cfg_sent), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_tx_data_src_cfg_sent_d ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_data_src_cfg_sent_d_3), + .Q(com_tlm_u_tlm_tx_data_src_cfg_sent_d_2188), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_tx_data_src_buf_src_rdy_o ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_data_src_buf_src_rdy_o_3), + .Q(com_tlm_u_tlm_tx_ds_buf_src_rdy), + .R(plm_link_up_i) + ); + FDSE com_tlm_u_tlm_tx_data_src_lnk_trem_o ( + .CE(com_tlm_u_tlm_tx_data_src_N_17261_i_2190), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_data_src_N_17280_i_2191), + .Q(com_lnk_trem[0]), + .S(plm_link_up_i) + ); + FDRE com_tlm_u_tlm_tx_data_src_lnk_tsof_o ( + .CE(com_tlm_u_tlm_tx_data_src_N_17261_i_2190), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_data_src_lnk_tsof_o_5), + .Q(com_lnk_tsof), + .R(plm_link_up_i) + ); + FDRE com_tlm_u_tlm_tx_data_src_lnk_tretry_o ( + .CE(com_tlm_u_tlm_tx_data_src_N_17261_i_2190), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_data_src_lnk_tretry_o_5), + .Q(com_lnk_tretry), + .R(plm_link_up_i) + ); + FDRE com_tlm_u_tlm_tx_data_src_lnk_teof_o ( + .CE(com_tlm_u_tlm_tx_data_src_N_17261_i_2190), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_data_src_lnk_teof_o_5), + .Q(com_lnk_teof), + .R(plm_link_up_i) + ); + FDSE com_tlm_u_tlm_tx_data_src_lnk_ttrans_seq_o_0_ ( + .CE(com_tlm_u_tlm_tx_en_qq), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_data_src_lnk_ttrans_seq_o_4_i_m2_0[0]), + .Q(com_lnk_ttrans_seq[0]), + .S(plm_link_up_i) + ); + FDSE com_tlm_u_tlm_tx_data_src_lnk_ttrans_seq_o_1_ ( + .CE(com_tlm_u_tlm_tx_en_qq), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_data_src_lnk_ttrans_seq_o_4_i_m2_0[1]), + .Q(com_lnk_ttrans_seq[1]), + .S(plm_link_up_i) + ); + FDSE com_tlm_u_tlm_tx_data_src_lnk_ttrans_seq_o_2_ ( + .CE(com_tlm_u_tlm_tx_en_qq), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_data_src_lnk_ttrans_seq_o_4_i_m2_0[2]), + .Q(com_lnk_ttrans_seq[2]), + .S(plm_link_up_i) + ); + FDSE com_tlm_u_tlm_tx_data_src_lnk_ttrans_seq_o_3_ ( + .CE(com_tlm_u_tlm_tx_en_qq), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_data_src_lnk_ttrans_seq_o_4_i_m2_0[3]), + .Q(com_lnk_ttrans_seq[3]), + .S(plm_link_up_i) + ); + FDSE com_tlm_u_tlm_tx_data_src_lnk_ttrans_seq_o_4_ ( + .CE(com_tlm_u_tlm_tx_en_qq), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_data_src_lnk_ttrans_seq_o_4_i_m2_0[4]), + .Q(com_lnk_ttrans_seq[4]), + .S(plm_link_up_i) + ); + FDSE com_tlm_u_tlm_tx_data_src_lnk_ttrans_seq_o_5_ ( + .CE(com_tlm_u_tlm_tx_en_qq), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_data_src_lnk_ttrans_seq_o_4_i_m2_0[5]), + .Q(com_lnk_ttrans_seq[5]), + .S(plm_link_up_i) + ); + FDSE com_tlm_u_tlm_tx_data_src_lnk_ttrans_seq_o_6_ ( + .CE(com_tlm_u_tlm_tx_en_qq), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_data_src_lnk_ttrans_seq_o_4_i_m2_0[6]), + .Q(com_lnk_ttrans_seq[6]), + .S(plm_link_up_i) + ); + FDSE com_tlm_u_tlm_tx_data_src_lnk_ttrans_seq_o_7_ ( + .CE(com_tlm_u_tlm_tx_en_qq), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_data_src_lnk_ttrans_seq_o_4_i_m2_0[7]), + .Q(com_lnk_ttrans_seq[7]), + .S(plm_link_up_i) + ); + FDSE com_tlm_u_tlm_tx_data_src_lnk_ttrans_seq_o_8_ ( + .CE(com_tlm_u_tlm_tx_en_qq), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_data_src_lnk_ttrans_seq_o_4_i_m2_0[8]), + .Q(com_lnk_ttrans_seq[8]), + .S(plm_link_up_i) + ); + FDSE com_tlm_u_tlm_tx_data_src_lnk_ttrans_seq_o_9_ ( + .CE(com_tlm_u_tlm_tx_en_qq), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_data_src_lnk_ttrans_seq_o_4_i_m2_0[9]), + .Q(com_lnk_ttrans_seq[9]), + .S(plm_link_up_i) + ); + FDSE com_tlm_u_tlm_tx_data_src_lnk_ttrans_seq_o_10_ ( + .CE(com_tlm_u_tlm_tx_en_qq), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_data_src_lnk_ttrans_seq_o_4_i_m2_0[10]), + .Q(com_lnk_ttrans_seq[10]), + .S(plm_link_up_i) + ); + FDSE com_tlm_u_tlm_tx_data_src_lnk_ttrans_seq_o_11_ ( + .CE(com_tlm_u_tlm_tx_en_qq), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_data_src_lnk_ttrans_seq_o_4_i_m2_0[11]), + .Q(com_lnk_ttrans_seq[11]), + .S(plm_link_up_i) + ); + FDRE com_tlm_u_tlm_tx_data_src_lnk_tsrc_rdy_o ( + .CE(com_lnk_tdst_rdy_n_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_src_rdy), + .Q(com_tlm_u_tlm_tx_data_src_lnk_tsrc_rdy), + .R(plm_link_up_i) + ); + FDRE com_tlm_u_tlm_tx_data_src_tsn_cnt_0_ ( + .CE(com_tlm_u_tlm_tx_data_src_un1_lnk_tsrc_rdy_o_1_0_a2_2192), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_data_src_tsn_cnt_s[0]), + .Q(com_tlm_u_tlm_tx_data_src_tsn_cnt[0]), + .R(plm_link_up_i) + ); + MUXCY_L com_tlm_u_tlm_tx_data_src_tsn_cnt_cry_1_ ( + .CI(com_tlm_u_tlm_tx_data_src_tsn_cnt[0]), + .DI(com_tlm_u_tlm_tx_data_src_GND_2189), + .LO(com_tlm_u_tlm_tx_data_src_tsn_cnt_cry[1]), + .S(com_tlm_u_tlm_tx_data_src_tsn_cnt_qxu[1]) + ); + XORCY com_tlm_u_tlm_tx_data_src_tsn_cnt_s_1_ ( + .CI(com_tlm_u_tlm_tx_data_src_tsn_cnt[0]), + .LI(com_tlm_u_tlm_tx_data_src_tsn_cnt_qxu[1]), + .O(com_tlm_u_tlm_tx_data_src_tsn_cnt_s[1]) + ); + FDRE com_tlm_u_tlm_tx_data_src_tsn_cnt_1_ ( + .CE(com_tlm_u_tlm_tx_data_src_un1_lnk_tsrc_rdy_o_1_0_a2_2192), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_data_src_tsn_cnt_s[1]), + .Q(com_tlm_u_tlm_tx_data_src_tsn_cnt[1]), + .R(plm_link_up_i) + ); + MUXCY_L com_tlm_u_tlm_tx_data_src_tsn_cnt_cry_2_ ( + .CI(com_tlm_u_tlm_tx_data_src_tsn_cnt_cry[1]), + .DI(com_tlm_u_tlm_tx_data_src_GND_2189), + .LO(com_tlm_u_tlm_tx_data_src_tsn_cnt_cry[2]), + .S(com_tlm_u_tlm_tx_data_src_tsn_cnt_qxu[2]) + ); + XORCY com_tlm_u_tlm_tx_data_src_tsn_cnt_s_2_ ( + .CI(com_tlm_u_tlm_tx_data_src_tsn_cnt_cry[1]), + .LI(com_tlm_u_tlm_tx_data_src_tsn_cnt_qxu[2]), + .O(com_tlm_u_tlm_tx_data_src_tsn_cnt_s[2]) + ); + FDRE com_tlm_u_tlm_tx_data_src_tsn_cnt_2_ ( + .CE(com_tlm_u_tlm_tx_data_src_un1_lnk_tsrc_rdy_o_1_0_a2_2192), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_data_src_tsn_cnt_s[2]), + .Q(com_tlm_u_tlm_tx_data_src_tsn_cnt[2]), + .R(plm_link_up_i) + ); + MUXCY_L com_tlm_u_tlm_tx_data_src_tsn_cnt_cry_3_ ( + .CI(com_tlm_u_tlm_tx_data_src_tsn_cnt_cry[2]), + .DI(com_tlm_u_tlm_tx_data_src_GND_2189), + .LO(com_tlm_u_tlm_tx_data_src_tsn_cnt_cry[3]), + .S(com_tlm_u_tlm_tx_data_src_tsn_cnt_qxu[3]) + ); + XORCY com_tlm_u_tlm_tx_data_src_tsn_cnt_s_3_ ( + .CI(com_tlm_u_tlm_tx_data_src_tsn_cnt_cry[2]), + .LI(com_tlm_u_tlm_tx_data_src_tsn_cnt_qxu[3]), + .O(com_tlm_u_tlm_tx_data_src_tsn_cnt_s[3]) + ); + FDRE com_tlm_u_tlm_tx_data_src_tsn_cnt_3_ ( + .CE(com_tlm_u_tlm_tx_data_src_un1_lnk_tsrc_rdy_o_1_0_a2_2192), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_data_src_tsn_cnt_s[3]), + .Q(com_tlm_u_tlm_tx_data_src_tsn_cnt[3]), + .R(plm_link_up_i) + ); + MUXCY_L com_tlm_u_tlm_tx_data_src_tsn_cnt_cry_4_ ( + .CI(com_tlm_u_tlm_tx_data_src_tsn_cnt_cry[3]), + .DI(com_tlm_u_tlm_tx_data_src_GND_2189), + .LO(com_tlm_u_tlm_tx_data_src_tsn_cnt_cry[4]), + .S(com_tlm_u_tlm_tx_data_src_tsn_cnt_qxu[4]) + ); + XORCY com_tlm_u_tlm_tx_data_src_tsn_cnt_s_4_ ( + .CI(com_tlm_u_tlm_tx_data_src_tsn_cnt_cry[3]), + .LI(com_tlm_u_tlm_tx_data_src_tsn_cnt_qxu[4]), + .O(com_tlm_u_tlm_tx_data_src_tsn_cnt_s[4]) + ); + FDRE com_tlm_u_tlm_tx_data_src_tsn_cnt_4_ ( + .CE(com_tlm_u_tlm_tx_data_src_un1_lnk_tsrc_rdy_o_1_0_a2_2192), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_data_src_tsn_cnt_s[4]), + .Q(com_tlm_u_tlm_tx_data_src_tsn_cnt[4]), + .R(plm_link_up_i) + ); + MUXCY_L com_tlm_u_tlm_tx_data_src_tsn_cnt_cry_5_ ( + .CI(com_tlm_u_tlm_tx_data_src_tsn_cnt_cry[4]), + .DI(com_tlm_u_tlm_tx_data_src_GND_2189), + .LO(com_tlm_u_tlm_tx_data_src_tsn_cnt_cry[5]), + .S(com_tlm_u_tlm_tx_data_src_tsn_cnt_qxu[5]) + ); + XORCY com_tlm_u_tlm_tx_data_src_tsn_cnt_s_5_ ( + .CI(com_tlm_u_tlm_tx_data_src_tsn_cnt_cry[4]), + .LI(com_tlm_u_tlm_tx_data_src_tsn_cnt_qxu[5]), + .O(com_tlm_u_tlm_tx_data_src_tsn_cnt_s[5]) + ); + FDRE com_tlm_u_tlm_tx_data_src_tsn_cnt_5_ ( + .CE(com_tlm_u_tlm_tx_data_src_un1_lnk_tsrc_rdy_o_1_0_a2_2192), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_data_src_tsn_cnt_s[5]), + .Q(com_tlm_u_tlm_tx_data_src_tsn_cnt[5]), + .R(plm_link_up_i) + ); + MUXCY_L com_tlm_u_tlm_tx_data_src_tsn_cnt_cry_6_ ( + .CI(com_tlm_u_tlm_tx_data_src_tsn_cnt_cry[5]), + .DI(com_tlm_u_tlm_tx_data_src_GND_2189), + .LO(com_tlm_u_tlm_tx_data_src_tsn_cnt_cry[6]), + .S(com_tlm_u_tlm_tx_data_src_tsn_cnt_qxu[6]) + ); + XORCY com_tlm_u_tlm_tx_data_src_tsn_cnt_s_6_ ( + .CI(com_tlm_u_tlm_tx_data_src_tsn_cnt_cry[5]), + .LI(com_tlm_u_tlm_tx_data_src_tsn_cnt_qxu[6]), + .O(com_tlm_u_tlm_tx_data_src_tsn_cnt_s[6]) + ); + FDRE com_tlm_u_tlm_tx_data_src_tsn_cnt_6_ ( + .CE(com_tlm_u_tlm_tx_data_src_un1_lnk_tsrc_rdy_o_1_0_a2_2192), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_data_src_tsn_cnt_s[6]), + .Q(com_tlm_u_tlm_tx_data_src_tsn_cnt[6]), + .R(plm_link_up_i) + ); + MUXCY_L com_tlm_u_tlm_tx_data_src_tsn_cnt_cry_7_ ( + .CI(com_tlm_u_tlm_tx_data_src_tsn_cnt_cry[6]), + .DI(com_tlm_u_tlm_tx_data_src_GND_2189), + .LO(com_tlm_u_tlm_tx_data_src_tsn_cnt_cry[7]), + .S(com_tlm_u_tlm_tx_data_src_tsn_cnt_qxu[7]) + ); + XORCY com_tlm_u_tlm_tx_data_src_tsn_cnt_s_7_ ( + .CI(com_tlm_u_tlm_tx_data_src_tsn_cnt_cry[6]), + .LI(com_tlm_u_tlm_tx_data_src_tsn_cnt_qxu[7]), + .O(com_tlm_u_tlm_tx_data_src_tsn_cnt_s[7]) + ); + FDRE com_tlm_u_tlm_tx_data_src_tsn_cnt_7_ ( + .CE(com_tlm_u_tlm_tx_data_src_un1_lnk_tsrc_rdy_o_1_0_a2_2192), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_data_src_tsn_cnt_s[7]), + .Q(com_tlm_u_tlm_tx_data_src_tsn_cnt[7]), + .R(plm_link_up_i) + ); + MUXCY_L com_tlm_u_tlm_tx_data_src_tsn_cnt_cry_8_ ( + .CI(com_tlm_u_tlm_tx_data_src_tsn_cnt_cry[7]), + .DI(com_tlm_u_tlm_tx_data_src_GND_2189), + .LO(com_tlm_u_tlm_tx_data_src_tsn_cnt_cry[8]), + .S(com_tlm_u_tlm_tx_data_src_tsn_cnt_qxu[8]) + ); + XORCY com_tlm_u_tlm_tx_data_src_tsn_cnt_s_8_ ( + .CI(com_tlm_u_tlm_tx_data_src_tsn_cnt_cry[7]), + .LI(com_tlm_u_tlm_tx_data_src_tsn_cnt_qxu[8]), + .O(com_tlm_u_tlm_tx_data_src_tsn_cnt_s[8]) + ); + FDRE com_tlm_u_tlm_tx_data_src_tsn_cnt_8_ ( + .CE(com_tlm_u_tlm_tx_data_src_un1_lnk_tsrc_rdy_o_1_0_a2_2192), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_data_src_tsn_cnt_s[8]), + .Q(com_tlm_u_tlm_tx_data_src_tsn_cnt[8]), + .R(plm_link_up_i) + ); + MUXCY_L com_tlm_u_tlm_tx_data_src_tsn_cnt_cry_9_ ( + .CI(com_tlm_u_tlm_tx_data_src_tsn_cnt_cry[8]), + .DI(com_tlm_u_tlm_tx_data_src_GND_2189), + .LO(com_tlm_u_tlm_tx_data_src_tsn_cnt_cry[9]), + .S(com_tlm_u_tlm_tx_data_src_tsn_cnt_qxu[9]) + ); + XORCY com_tlm_u_tlm_tx_data_src_tsn_cnt_s_9_ ( + .CI(com_tlm_u_tlm_tx_data_src_tsn_cnt_cry[8]), + .LI(com_tlm_u_tlm_tx_data_src_tsn_cnt_qxu[9]), + .O(com_tlm_u_tlm_tx_data_src_tsn_cnt_s[9]) + ); + FDRE com_tlm_u_tlm_tx_data_src_tsn_cnt_9_ ( + .CE(com_tlm_u_tlm_tx_data_src_un1_lnk_tsrc_rdy_o_1_0_a2_2192), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_data_src_tsn_cnt_s[9]), + .Q(com_tlm_u_tlm_tx_data_src_tsn_cnt[9]), + .R(plm_link_up_i) + ); + MUXCY_L com_tlm_u_tlm_tx_data_src_tsn_cnt_cry_10_ ( + .CI(com_tlm_u_tlm_tx_data_src_tsn_cnt_cry[9]), + .DI(com_tlm_u_tlm_tx_data_src_GND_2189), + .LO(com_tlm_u_tlm_tx_data_src_tsn_cnt_cry[10]), + .S(com_tlm_u_tlm_tx_data_src_tsn_cnt_qxu[10]) + ); + XORCY com_tlm_u_tlm_tx_data_src_tsn_cnt_s_10_ ( + .CI(com_tlm_u_tlm_tx_data_src_tsn_cnt_cry[9]), + .LI(com_tlm_u_tlm_tx_data_src_tsn_cnt_qxu[10]), + .O(com_tlm_u_tlm_tx_data_src_tsn_cnt_s[10]) + ); + FDRE com_tlm_u_tlm_tx_data_src_tsn_cnt_10_ ( + .CE(com_tlm_u_tlm_tx_data_src_un1_lnk_tsrc_rdy_o_1_0_a2_2192), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_data_src_tsn_cnt_s[10]), + .Q(com_tlm_u_tlm_tx_data_src_tsn_cnt[10]), + .R(plm_link_up_i) + ); + XORCY com_tlm_u_tlm_tx_data_src_tsn_cnt_s_11_ ( + .CI(com_tlm_u_tlm_tx_data_src_tsn_cnt_cry[10]), + .LI(com_tlm_u_tlm_tx_data_src_tsn_cnt_qxu[11]), + .O(com_tlm_u_tlm_tx_data_src_tsn_cnt_s[11]) + ); + FDRE com_tlm_u_tlm_tx_data_src_tsn_cnt_11_ ( + .CE(com_tlm_u_tlm_tx_data_src_un1_lnk_tsrc_rdy_o_1_0_a2_2192), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_data_src_tsn_cnt_s[11]), + .Q(com_tlm_u_tlm_tx_data_src_tsn_cnt[11]), + .R(plm_link_up_i) + ); + defparam com_tlm_u_tlm_tx_data_src_N_17261_i.INIT = 4'h7; + LUT2 com_tlm_u_tlm_tx_data_src_N_17261_i ( + .I0(com_lnk_tdst_rdy_n), + .I1(com_tlm_u_tlm_tx_data_src_lnk_tsrc_rdy), + .O(com_tlm_u_tlm_tx_data_src_N_17261_i_2190) + ); + defparam com_tlm_u_tlm_tx_data_src_lnk_tsof_o_5_0_a2.INIT = 4'h8; + LUT2 com_tlm_u_tlm_tx_data_src_lnk_tsof_o_5_0_a2 ( + .I0(com_tlm_u_tlm_tx_en_qq), + .I1(com_tlm_u_tlm_tx_vc0_sof), + .O(com_tlm_u_tlm_tx_data_src_lnk_tsof_o_5) + ); + defparam com_tlm_u_tlm_tx_data_src_buf_src_rdy_o_3_0_a2.INIT = 4'h2; + LUT2 com_tlm_u_tlm_tx_data_src_buf_src_rdy_o_3_0_a2 ( + .I0(com_tlm_u_tlm_tx_data_src_lnk_tsof_o_5), + .I1(com_tlm_u_tlm_tx_vc0_retry), + .O(com_tlm_u_tlm_tx_data_src_buf_src_rdy_o_3) + ); + defparam com_tlm_u_tlm_tx_data_src_lnk_ttrans_seq_i_0_.INIT = 4'h1; + LUT1_L com_tlm_u_tlm_tx_data_src_lnk_ttrans_seq_i_0_ ( + .I0(com_lnk_ttrans_seq[0]), + .LO(com_lnk_ttrans_seq_i[0]) + ); + defparam com_tlm_u_tlm_tx_data_src_lnk_teof_i.INIT = 4'h1; + LUT1_L com_tlm_u_tlm_tx_data_src_lnk_teof_i ( + .I0(com_lnk_teof), + .LO(com_lnk_teof_i) + ); + defparam com_tlm_u_tlm_tx_data_src_lnk_tsof_i.INIT = 4'h1; + LUT1_L com_tlm_u_tlm_tx_data_src_lnk_tsof_i ( + .I0(com_lnk_tsof), + .LO(com_lnk_tsof_i) + ); + defparam com_tlm_u_tlm_tx_data_src_lnk_ttrans_seq_o_4_i_m2_0_11_.INIT = 8'hE2; + LUT3_L com_tlm_u_tlm_tx_data_src_lnk_ttrans_seq_o_4_i_m2_0_11_ ( + .I0(com_tlm_u_tlm_tx_data_src_tsn_cnt[11]), + .I1(com_tlm_u_tlm_tx_vc0_retry), + .I2(com_tlm_u_tlm_tx_vc0_retry_tsn[11]), + .LO(com_tlm_u_tlm_tx_data_src_lnk_ttrans_seq_o_4_i_m2_0[11]) + ); + defparam com_tlm_u_tlm_tx_data_src_lnk_ttrans_seq_o_4_i_m2_0_10_.INIT = 8'hE2; + LUT3_L com_tlm_u_tlm_tx_data_src_lnk_ttrans_seq_o_4_i_m2_0_10_ ( + .I0(com_tlm_u_tlm_tx_data_src_tsn_cnt[10]), + .I1(com_tlm_u_tlm_tx_vc0_retry), + .I2(com_tlm_u_tlm_tx_vc0_retry_tsn[10]), + .LO(com_tlm_u_tlm_tx_data_src_lnk_ttrans_seq_o_4_i_m2_0[10]) + ); + defparam com_tlm_u_tlm_tx_data_src_lnk_ttrans_seq_o_4_i_m2_0_9_.INIT = 8'hE2; + LUT3_L com_tlm_u_tlm_tx_data_src_lnk_ttrans_seq_o_4_i_m2_0_9_ ( + .I0(com_tlm_u_tlm_tx_data_src_tsn_cnt[9]), + .I1(com_tlm_u_tlm_tx_vc0_retry), + .I2(com_tlm_u_tlm_tx_vc0_retry_tsn[9]), + .LO(com_tlm_u_tlm_tx_data_src_lnk_ttrans_seq_o_4_i_m2_0[9]) + ); + defparam com_tlm_u_tlm_tx_data_src_lnk_ttrans_seq_o_4_i_m2_0_8_.INIT = 8'hE2; + LUT3_L com_tlm_u_tlm_tx_data_src_lnk_ttrans_seq_o_4_i_m2_0_8_ ( + .I0(com_tlm_u_tlm_tx_data_src_tsn_cnt[8]), + .I1(com_tlm_u_tlm_tx_vc0_retry), + .I2(com_tlm_u_tlm_tx_vc0_retry_tsn[8]), + .LO(com_tlm_u_tlm_tx_data_src_lnk_ttrans_seq_o_4_i_m2_0[8]) + ); + defparam com_tlm_u_tlm_tx_data_src_lnk_ttrans_seq_o_4_i_m2_0_7_.INIT = 8'hE2; + LUT3_L com_tlm_u_tlm_tx_data_src_lnk_ttrans_seq_o_4_i_m2_0_7_ ( + .I0(com_tlm_u_tlm_tx_data_src_tsn_cnt[7]), + .I1(com_tlm_u_tlm_tx_vc0_retry), + .I2(com_tlm_u_tlm_tx_vc0_retry_tsn[7]), + .LO(com_tlm_u_tlm_tx_data_src_lnk_ttrans_seq_o_4_i_m2_0[7]) + ); + defparam com_tlm_u_tlm_tx_data_src_lnk_ttrans_seq_o_4_i_m2_0_6_.INIT = 8'hE2; + LUT3_L com_tlm_u_tlm_tx_data_src_lnk_ttrans_seq_o_4_i_m2_0_6_ ( + .I0(com_tlm_u_tlm_tx_data_src_tsn_cnt[6]), + .I1(com_tlm_u_tlm_tx_vc0_retry), + .I2(com_tlm_u_tlm_tx_vc0_retry_tsn[6]), + .LO(com_tlm_u_tlm_tx_data_src_lnk_ttrans_seq_o_4_i_m2_0[6]) + ); + defparam com_tlm_u_tlm_tx_data_src_lnk_ttrans_seq_o_4_i_m2_0_5_.INIT = 8'hE2; + LUT3_L com_tlm_u_tlm_tx_data_src_lnk_ttrans_seq_o_4_i_m2_0_5_ ( + .I0(com_tlm_u_tlm_tx_data_src_tsn_cnt[5]), + .I1(com_tlm_u_tlm_tx_vc0_retry), + .I2(com_tlm_u_tlm_tx_vc0_retry_tsn[5]), + .LO(com_tlm_u_tlm_tx_data_src_lnk_ttrans_seq_o_4_i_m2_0[5]) + ); + defparam com_tlm_u_tlm_tx_data_src_lnk_ttrans_seq_o_4_i_m2_0_4_.INIT = 8'hE2; + LUT3_L com_tlm_u_tlm_tx_data_src_lnk_ttrans_seq_o_4_i_m2_0_4_ ( + .I0(com_tlm_u_tlm_tx_data_src_tsn_cnt[4]), + .I1(com_tlm_u_tlm_tx_vc0_retry), + .I2(com_tlm_u_tlm_tx_vc0_retry_tsn[4]), + .LO(com_tlm_u_tlm_tx_data_src_lnk_ttrans_seq_o_4_i_m2_0[4]) + ); + defparam com_tlm_u_tlm_tx_data_src_lnk_ttrans_seq_o_4_i_m2_0_3_.INIT = 8'hE2; + LUT3_L com_tlm_u_tlm_tx_data_src_lnk_ttrans_seq_o_4_i_m2_0_3_ ( + .I0(com_tlm_u_tlm_tx_data_src_tsn_cnt[3]), + .I1(com_tlm_u_tlm_tx_vc0_retry), + .I2(com_tlm_u_tlm_tx_vc0_retry_tsn[3]), + .LO(com_tlm_u_tlm_tx_data_src_lnk_ttrans_seq_o_4_i_m2_0[3]) + ); + defparam com_tlm_u_tlm_tx_data_src_lnk_ttrans_seq_o_4_i_m2_0_2_.INIT = 8'hE2; + LUT3_L com_tlm_u_tlm_tx_data_src_lnk_ttrans_seq_o_4_i_m2_0_2_ ( + .I0(com_tlm_u_tlm_tx_data_src_tsn_cnt[2]), + .I1(com_tlm_u_tlm_tx_vc0_retry), + .I2(com_tlm_u_tlm_tx_vc0_retry_tsn[2]), + .LO(com_tlm_u_tlm_tx_data_src_lnk_ttrans_seq_o_4_i_m2_0[2]) + ); + defparam com_tlm_u_tlm_tx_data_src_lnk_ttrans_seq_o_4_i_m2_0_1_.INIT = 8'hE2; + LUT3_L com_tlm_u_tlm_tx_data_src_lnk_ttrans_seq_o_4_i_m2_0_1_ ( + .I0(com_tlm_u_tlm_tx_data_src_tsn_cnt[1]), + .I1(com_tlm_u_tlm_tx_vc0_retry), + .I2(com_tlm_u_tlm_tx_vc0_retry_tsn[1]), + .LO(com_tlm_u_tlm_tx_data_src_lnk_ttrans_seq_o_4_i_m2_0[1]) + ); + defparam com_tlm_u_tlm_tx_data_src_lnk_ttrans_seq_o_4_i_m2_0_0_.INIT = 8'hE2; + LUT3_L com_tlm_u_tlm_tx_data_src_lnk_ttrans_seq_o_4_i_m2_0_0_ ( + .I0(com_tlm_u_tlm_tx_data_src_tsn_cnt[0]), + .I1(com_tlm_u_tlm_tx_vc0_retry), + .I2(com_tlm_u_tlm_tx_vc0_retry_tsn[0]), + .LO(com_tlm_u_tlm_tx_data_src_lnk_ttrans_seq_o_4_i_m2_0[0]) + ); + defparam com_tlm_u_tlm_tx_data_src_lnk_tretry_o_5_0_a2.INIT = 4'h8; + LUT2_L com_tlm_u_tlm_tx_data_src_lnk_tretry_o_5_0_a2 ( + .I0(com_tlm_u_tlm_tx_en_qq), + .I1(com_tlm_u_tlm_tx_vc0_retry), + .LO(com_tlm_u_tlm_tx_data_src_lnk_tretry_o_5) + ); + defparam com_tlm_u_tlm_tx_data_src_N_17280_i.INIT = 4'h7; + LUT2_L com_tlm_u_tlm_tx_data_src_N_17280_i ( + .I0(com_tlm_u_tlm_tx_en_qq), + .I1(com_tlm_u_tlm_tx_rdata_q_all[68]), + .LO(com_tlm_u_tlm_tx_data_src_N_17280_i_2191) + ); + defparam com_tlm_u_tlm_tx_data_src_N_69038_i.INIT = 8'hEA; + LUT3_L com_tlm_u_tlm_tx_data_src_N_69038_i ( + .I0(com_tlm_u_tlm_tx_vc0_d[46]), + .I1(com_tlm_u_tlm_tx_vc0_errfwd), + .I2(com_tlm_u_tlm_tx_vc0_sof), + .LO(com_tlm_u_tlm_tx_data_src_N_69038_i_2193) + ); + defparam com_tlm_u_tlm_tx_data_src_cfg_sent_d_3_0_a2.INIT = 4'h8; + LUT2_L com_tlm_u_tlm_tx_data_src_cfg_sent_d_3_0_a2 ( + .I0(com_tlm_u_tlm_tx_data_src_buf_src_rdy_o_3), + .I1(com_tlm_u_tlm_tx_vc0_cfg), + .LO(com_tlm_u_tlm_tx_data_src_cfg_sent_d_3) + ); + defparam com_tlm_u_tlm_tx_data_src_stat_tlp_wr_ep_o_5_0_a2.INIT = 16'hA888; + LUT4_L com_tlm_u_tlm_tx_data_src_stat_tlp_wr_ep_o_5_0_a2 ( + .I0(com_tlm_u_tlm_tx_data_src_buf_src_rdy_o_3), + .I1(com_tlm_u_tlm_tx_vc0_d[46]), + .I2(com_tlm_u_tlm_tx_vc0_errfwd), + .I3(com_tlm_u_tlm_tx_vc0_sof), + .LO(com_tlm_u_tlm_tx_data_src_stat_tlp_wr_ep_o_5) + ); + defparam com_tlm_u_tlm_tx_data_src_un1_lnk_tsrc_rdy_o_1_0_a2.INIT = 8'h40; + LUT3 com_tlm_u_tlm_tx_data_src_un1_lnk_tsrc_rdy_o_1_0_a2 ( + .I0(com_tlm_u_tlm_tx_vc0_retry), + .I1(com_tlm_u_tlm_tx_vc0_eof), + .I2(com_tlm_u_tlm_tx_en_qq), + .O(com_tlm_u_tlm_tx_data_src_un1_lnk_tsrc_rdy_o_1_0_a2_2192) + ); + FD com_tlm_u_tlm_tx_data_src_buf_num_o_0_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_buf_num[0]), + .Q(com_tlm_u_tlm_tx_ds_buf_num[0]) + ); + FD com_tlm_u_tlm_tx_data_src_buf_num_o_3_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_buf_num[3]), + .Q(com_tlm_u_tlm_tx_ds_buf_num[3]) + ); + FD com_tlm_u_tlm_tx_data_src_buf_num_o_2_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_buf_num[2]), + .Q(com_tlm_u_tlm_tx_ds_buf_num[2]) + ); + FD com_tlm_u_tlm_tx_data_src_buf_num_o_1_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_buf_num[1]), + .Q(com_tlm_u_tlm_tx_ds_buf_num[1]) + ); + FDE com_tlm_u_tlm_tx_data_src_lnk_td_o_63_ ( + .CE(com_tlm_u_tlm_tx_en_qq), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_d[63]), + .Q(com_lnk_td[63]) + ); + FDE com_tlm_u_tlm_tx_data_src_lnk_td_o_62_ ( + .CE(com_tlm_u_tlm_tx_en_qq), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_d[62]), + .Q(com_lnk_td[62]) + ); + FDE com_tlm_u_tlm_tx_data_src_lnk_td_o_61_ ( + .CE(com_tlm_u_tlm_tx_en_qq), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_d[61]), + .Q(com_lnk_td[61]) + ); + FDE com_tlm_u_tlm_tx_data_src_lnk_td_o_60_ ( + .CE(com_tlm_u_tlm_tx_en_qq), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_d[60]), + .Q(com_lnk_td[60]) + ); + FDE com_tlm_u_tlm_tx_data_src_lnk_td_o_59_ ( + .CE(com_tlm_u_tlm_tx_en_qq), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_d[59]), + .Q(com_lnk_td[59]) + ); + FDE com_tlm_u_tlm_tx_data_src_lnk_td_o_58_ ( + .CE(com_tlm_u_tlm_tx_en_qq), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_d[58]), + .Q(com_lnk_td[58]) + ); + FDE com_tlm_u_tlm_tx_data_src_lnk_td_o_57_ ( + .CE(com_tlm_u_tlm_tx_en_qq), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_d[57]), + .Q(com_lnk_td[57]) + ); + FDE com_tlm_u_tlm_tx_data_src_lnk_td_o_56_ ( + .CE(com_tlm_u_tlm_tx_en_qq), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_d[56]), + .Q(com_lnk_td[56]) + ); + FDE com_tlm_u_tlm_tx_data_src_lnk_td_o_55_ ( + .CE(com_tlm_u_tlm_tx_en_qq), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_d[55]), + .Q(com_lnk_td[55]) + ); + FDE com_tlm_u_tlm_tx_data_src_lnk_td_o_54_ ( + .CE(com_tlm_u_tlm_tx_en_qq), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_d[54]), + .Q(com_lnk_td[54]) + ); + FDE com_tlm_u_tlm_tx_data_src_lnk_td_o_53_ ( + .CE(com_tlm_u_tlm_tx_en_qq), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_d[53]), + .Q(com_lnk_td[53]) + ); + FDE com_tlm_u_tlm_tx_data_src_lnk_td_o_52_ ( + .CE(com_tlm_u_tlm_tx_en_qq), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_d[52]), + .Q(com_lnk_td[52]) + ); + FDE com_tlm_u_tlm_tx_data_src_lnk_td_o_51_ ( + .CE(com_tlm_u_tlm_tx_en_qq), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_d[51]), + .Q(com_lnk_td[51]) + ); + FDE com_tlm_u_tlm_tx_data_src_lnk_td_o_50_ ( + .CE(com_tlm_u_tlm_tx_en_qq), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_d[50]), + .Q(com_lnk_td[50]) + ); + FDE com_tlm_u_tlm_tx_data_src_lnk_td_o_49_ ( + .CE(com_tlm_u_tlm_tx_en_qq), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_d[49]), + .Q(com_lnk_td[49]) + ); + FDE com_tlm_u_tlm_tx_data_src_lnk_td_o_48_ ( + .CE(com_tlm_u_tlm_tx_en_qq), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_d[48]), + .Q(com_lnk_td[48]) + ); + FDE com_tlm_u_tlm_tx_data_src_lnk_td_o_47_ ( + .CE(com_tlm_u_tlm_tx_en_qq), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_d[47]), + .Q(com_lnk_td[47]) + ); + FDE com_tlm_u_tlm_tx_data_src_lnk_td_o_46_ ( + .CE(com_tlm_u_tlm_tx_en_qq), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_data_src_N_69038_i_2193), + .Q(com_lnk_td[46]) + ); + FDE com_tlm_u_tlm_tx_data_src_lnk_td_o_45_ ( + .CE(com_tlm_u_tlm_tx_en_qq), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_d[45]), + .Q(com_lnk_td[45]) + ); + FDE com_tlm_u_tlm_tx_data_src_lnk_td_o_44_ ( + .CE(com_tlm_u_tlm_tx_en_qq), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_d[44]), + .Q(com_lnk_td[44]) + ); + FDE com_tlm_u_tlm_tx_data_src_lnk_td_o_43_ ( + .CE(com_tlm_u_tlm_tx_en_qq), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_d[43]), + .Q(com_lnk_td[43]) + ); + FDE com_tlm_u_tlm_tx_data_src_lnk_td_o_42_ ( + .CE(com_tlm_u_tlm_tx_en_qq), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_d[42]), + .Q(com_lnk_td[42]) + ); + FDE com_tlm_u_tlm_tx_data_src_lnk_td_o_41_ ( + .CE(com_tlm_u_tlm_tx_en_qq), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_d[41]), + .Q(com_lnk_td[41]) + ); + FDE com_tlm_u_tlm_tx_data_src_lnk_td_o_40_ ( + .CE(com_tlm_u_tlm_tx_en_qq), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_d[40]), + .Q(com_lnk_td[40]) + ); + FDE com_tlm_u_tlm_tx_data_src_lnk_td_o_39_ ( + .CE(com_tlm_u_tlm_tx_en_qq), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_d[39]), + .Q(com_lnk_td[39]) + ); + FDE com_tlm_u_tlm_tx_data_src_lnk_td_o_38_ ( + .CE(com_tlm_u_tlm_tx_en_qq), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_d[38]), + .Q(com_lnk_td[38]) + ); + FDE com_tlm_u_tlm_tx_data_src_lnk_td_o_37_ ( + .CE(com_tlm_u_tlm_tx_en_qq), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_d[37]), + .Q(com_lnk_td[37]) + ); + FDE com_tlm_u_tlm_tx_data_src_lnk_td_o_36_ ( + .CE(com_tlm_u_tlm_tx_en_qq), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_d[36]), + .Q(com_lnk_td[36]) + ); + FDE com_tlm_u_tlm_tx_data_src_lnk_td_o_35_ ( + .CE(com_tlm_u_tlm_tx_en_qq), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_d[35]), + .Q(com_lnk_td[35]) + ); + FDE com_tlm_u_tlm_tx_data_src_lnk_td_o_34_ ( + .CE(com_tlm_u_tlm_tx_en_qq), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_d[34]), + .Q(com_lnk_td[34]) + ); + FDE com_tlm_u_tlm_tx_data_src_lnk_td_o_33_ ( + .CE(com_tlm_u_tlm_tx_en_qq), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_d[33]), + .Q(com_lnk_td[33]) + ); + FDE com_tlm_u_tlm_tx_data_src_lnk_td_o_32_ ( + .CE(com_tlm_u_tlm_tx_en_qq), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_d[32]), + .Q(com_lnk_td[32]) + ); + FDE com_tlm_u_tlm_tx_data_src_lnk_td_o_31_ ( + .CE(com_tlm_u_tlm_tx_en_qq), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_d[31]), + .Q(com_lnk_td[31]) + ); + FDE com_tlm_u_tlm_tx_data_src_lnk_td_o_30_ ( + .CE(com_tlm_u_tlm_tx_en_qq), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_d[30]), + .Q(com_lnk_td[30]) + ); + FDE com_tlm_u_tlm_tx_data_src_lnk_td_o_29_ ( + .CE(com_tlm_u_tlm_tx_en_qq), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_d[29]), + .Q(com_lnk_td[29]) + ); + FDE com_tlm_u_tlm_tx_data_src_lnk_td_o_28_ ( + .CE(com_tlm_u_tlm_tx_en_qq), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_d[28]), + .Q(com_lnk_td[28]) + ); + FDE com_tlm_u_tlm_tx_data_src_lnk_td_o_27_ ( + .CE(com_tlm_u_tlm_tx_en_qq), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_d[27]), + .Q(com_lnk_td[27]) + ); + FDE com_tlm_u_tlm_tx_data_src_lnk_td_o_26_ ( + .CE(com_tlm_u_tlm_tx_en_qq), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_d[26]), + .Q(com_lnk_td[26]) + ); + FDE com_tlm_u_tlm_tx_data_src_lnk_td_o_25_ ( + .CE(com_tlm_u_tlm_tx_en_qq), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_d[25]), + .Q(com_lnk_td[25]) + ); + FDE com_tlm_u_tlm_tx_data_src_lnk_td_o_24_ ( + .CE(com_tlm_u_tlm_tx_en_qq), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_d[24]), + .Q(com_lnk_td[24]) + ); + FDE com_tlm_u_tlm_tx_data_src_lnk_td_o_23_ ( + .CE(com_tlm_u_tlm_tx_en_qq), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_d[23]), + .Q(com_lnk_td[23]) + ); + FDE com_tlm_u_tlm_tx_data_src_lnk_td_o_22_ ( + .CE(com_tlm_u_tlm_tx_en_qq), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_d[22]), + .Q(com_lnk_td[22]) + ); + FDE com_tlm_u_tlm_tx_data_src_lnk_td_o_21_ ( + .CE(com_tlm_u_tlm_tx_en_qq), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_d[21]), + .Q(com_lnk_td[21]) + ); + FDE com_tlm_u_tlm_tx_data_src_lnk_td_o_20_ ( + .CE(com_tlm_u_tlm_tx_en_qq), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_d[20]), + .Q(com_lnk_td[20]) + ); + FDE com_tlm_u_tlm_tx_data_src_lnk_td_o_19_ ( + .CE(com_tlm_u_tlm_tx_en_qq), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_d[19]), + .Q(com_lnk_td[19]) + ); + FDE com_tlm_u_tlm_tx_data_src_lnk_td_o_18_ ( + .CE(com_tlm_u_tlm_tx_en_qq), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_d[18]), + .Q(com_lnk_td[18]) + ); + FDE com_tlm_u_tlm_tx_data_src_lnk_td_o_17_ ( + .CE(com_tlm_u_tlm_tx_en_qq), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_d[17]), + .Q(com_lnk_td[17]) + ); + FDE com_tlm_u_tlm_tx_data_src_lnk_td_o_16_ ( + .CE(com_tlm_u_tlm_tx_en_qq), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_d[16]), + .Q(com_lnk_td[16]) + ); + FDE com_tlm_u_tlm_tx_data_src_lnk_td_o_15_ ( + .CE(com_tlm_u_tlm_tx_en_qq), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_d[15]), + .Q(com_lnk_td[15]) + ); + FDE com_tlm_u_tlm_tx_data_src_lnk_td_o_14_ ( + .CE(com_tlm_u_tlm_tx_en_qq), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_d[14]), + .Q(com_lnk_td[14]) + ); + FDE com_tlm_u_tlm_tx_data_src_lnk_td_o_13_ ( + .CE(com_tlm_u_tlm_tx_en_qq), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_d[13]), + .Q(com_lnk_td[13]) + ); + FDE com_tlm_u_tlm_tx_data_src_lnk_td_o_12_ ( + .CE(com_tlm_u_tlm_tx_en_qq), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_d[12]), + .Q(com_lnk_td[12]) + ); + FDE com_tlm_u_tlm_tx_data_src_lnk_td_o_11_ ( + .CE(com_tlm_u_tlm_tx_en_qq), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_d[11]), + .Q(com_lnk_td[11]) + ); + FDE com_tlm_u_tlm_tx_data_src_lnk_td_o_10_ ( + .CE(com_tlm_u_tlm_tx_en_qq), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_d[10]), + .Q(com_lnk_td[10]) + ); + FDE com_tlm_u_tlm_tx_data_src_lnk_td_o_9_ ( + .CE(com_tlm_u_tlm_tx_en_qq), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_d[9]), + .Q(com_lnk_td[9]) + ); + FDE com_tlm_u_tlm_tx_data_src_lnk_td_o_8_ ( + .CE(com_tlm_u_tlm_tx_en_qq), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_d[8]), + .Q(com_lnk_td[8]) + ); + FDE com_tlm_u_tlm_tx_data_src_lnk_td_o_7_ ( + .CE(com_tlm_u_tlm_tx_en_qq), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_d[7]), + .Q(com_lnk_td[7]) + ); + FDE com_tlm_u_tlm_tx_data_src_lnk_td_o_6_ ( + .CE(com_tlm_u_tlm_tx_en_qq), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_d[6]), + .Q(com_lnk_td[6]) + ); + FDE com_tlm_u_tlm_tx_data_src_lnk_td_o_5_ ( + .CE(com_tlm_u_tlm_tx_en_qq), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_d[5]), + .Q(com_lnk_td[5]) + ); + FDE com_tlm_u_tlm_tx_data_src_lnk_td_o_4_ ( + .CE(com_tlm_u_tlm_tx_en_qq), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_d[4]), + .Q(com_lnk_td[4]) + ); + FDE com_tlm_u_tlm_tx_data_src_lnk_td_o_3_ ( + .CE(com_tlm_u_tlm_tx_en_qq), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_d[3]), + .Q(com_lnk_td[3]) + ); + FDE com_tlm_u_tlm_tx_data_src_lnk_td_o_2_ ( + .CE(com_tlm_u_tlm_tx_en_qq), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_d[2]), + .Q(com_lnk_td[2]) + ); + FDE com_tlm_u_tlm_tx_data_src_lnk_td_o_1_ ( + .CE(com_tlm_u_tlm_tx_en_qq), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_d[1]), + .Q(com_lnk_td[1]) + ); + FDE com_tlm_u_tlm_tx_data_src_lnk_td_o_0_ ( + .CE(com_tlm_u_tlm_tx_en_qq), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_d[0]), + .Q(com_lnk_td[0]) + ); + defparam com_tlm_u_tlm_tx_data_src_tsn_cnt_qxu_0_0_.INIT = 4'h2; + LUT1_L com_tlm_u_tlm_tx_data_src_tsn_cnt_qxu_0_0_ ( + .I0(com_tlm_u_tlm_tx_data_src_tsn_cnt[0]), + .LO(com_tlm_u_tlm_tx_data_src_tsn_cnt_qxu[0]) + ); + defparam com_tlm_u_tlm_tx_data_src_tsn_cnt_qxu_0_11_.INIT = 4'h2; + LUT1_L com_tlm_u_tlm_tx_data_src_tsn_cnt_qxu_0_11_ ( + .I0(com_tlm_u_tlm_tx_data_src_tsn_cnt[11]), + .LO(com_tlm_u_tlm_tx_data_src_tsn_cnt_qxu[11]) + ); + defparam com_tlm_u_tlm_tx_data_src_tsn_cnt_qxu_0_10_.INIT = 4'h2; + LUT1_L com_tlm_u_tlm_tx_data_src_tsn_cnt_qxu_0_10_ ( + .I0(com_tlm_u_tlm_tx_data_src_tsn_cnt[10]), + .LO(com_tlm_u_tlm_tx_data_src_tsn_cnt_qxu[10]) + ); + defparam com_tlm_u_tlm_tx_data_src_tsn_cnt_qxu_0_9_.INIT = 4'h2; + LUT1_L com_tlm_u_tlm_tx_data_src_tsn_cnt_qxu_0_9_ ( + .I0(com_tlm_u_tlm_tx_data_src_tsn_cnt[9]), + .LO(com_tlm_u_tlm_tx_data_src_tsn_cnt_qxu[9]) + ); + defparam com_tlm_u_tlm_tx_data_src_tsn_cnt_qxu_0_8_.INIT = 4'h2; + LUT1_L com_tlm_u_tlm_tx_data_src_tsn_cnt_qxu_0_8_ ( + .I0(com_tlm_u_tlm_tx_data_src_tsn_cnt[8]), + .LO(com_tlm_u_tlm_tx_data_src_tsn_cnt_qxu[8]) + ); + defparam com_tlm_u_tlm_tx_data_src_tsn_cnt_qxu_0_7_.INIT = 4'h2; + LUT1_L com_tlm_u_tlm_tx_data_src_tsn_cnt_qxu_0_7_ ( + .I0(com_tlm_u_tlm_tx_data_src_tsn_cnt[7]), + .LO(com_tlm_u_tlm_tx_data_src_tsn_cnt_qxu[7]) + ); + defparam com_tlm_u_tlm_tx_data_src_tsn_cnt_qxu_0_6_.INIT = 4'h2; + LUT1_L com_tlm_u_tlm_tx_data_src_tsn_cnt_qxu_0_6_ ( + .I0(com_tlm_u_tlm_tx_data_src_tsn_cnt[6]), + .LO(com_tlm_u_tlm_tx_data_src_tsn_cnt_qxu[6]) + ); + defparam com_tlm_u_tlm_tx_data_src_tsn_cnt_qxu_0_5_.INIT = 4'h2; + LUT1_L com_tlm_u_tlm_tx_data_src_tsn_cnt_qxu_0_5_ ( + .I0(com_tlm_u_tlm_tx_data_src_tsn_cnt[5]), + .LO(com_tlm_u_tlm_tx_data_src_tsn_cnt_qxu[5]) + ); + defparam com_tlm_u_tlm_tx_data_src_tsn_cnt_qxu_0_4_.INIT = 4'h2; + LUT1_L com_tlm_u_tlm_tx_data_src_tsn_cnt_qxu_0_4_ ( + .I0(com_tlm_u_tlm_tx_data_src_tsn_cnt[4]), + .LO(com_tlm_u_tlm_tx_data_src_tsn_cnt_qxu[4]) + ); + defparam com_tlm_u_tlm_tx_data_src_tsn_cnt_qxu_0_3_.INIT = 4'h2; + LUT1_L com_tlm_u_tlm_tx_data_src_tsn_cnt_qxu_0_3_ ( + .I0(com_tlm_u_tlm_tx_data_src_tsn_cnt[3]), + .LO(com_tlm_u_tlm_tx_data_src_tsn_cnt_qxu[3]) + ); + defparam com_tlm_u_tlm_tx_data_src_tsn_cnt_qxu_0_2_.INIT = 4'h2; + LUT1_L com_tlm_u_tlm_tx_data_src_tsn_cnt_qxu_0_2_ ( + .I0(com_tlm_u_tlm_tx_data_src_tsn_cnt[2]), + .LO(com_tlm_u_tlm_tx_data_src_tsn_cnt_qxu[2]) + ); + defparam com_tlm_u_tlm_tx_data_src_tsn_cnt_qxu_0_1_.INIT = 4'h2; + LUT1_L com_tlm_u_tlm_tx_data_src_tsn_cnt_qxu_0_1_ ( + .I0(com_tlm_u_tlm_tx_data_src_tsn_cnt[1]), + .LO(com_tlm_u_tlm_tx_data_src_tsn_cnt_qxu[1]) + ); + defparam com_tlm_u_tlm_tx_data_src_tsn_cnt_s_0_.INIT = 4'h1; + LUT1_L com_tlm_u_tlm_tx_data_src_tsn_cnt_s_0_ ( + .I0(com_tlm_u_tlm_tx_data_src_tsn_cnt_qxu[0]), + .LO(com_tlm_u_tlm_tx_data_src_tsn_cnt_s[0]) + ); + defparam com_tlm_u_tlm_tx_data_src_lnk_teof_o_5_0_a2.INIT = 4'h8; + LUT2_L com_tlm_u_tlm_tx_data_src_lnk_teof_o_5_0_a2 ( + .I0(com_tlm_u_tlm_tx_en_qq), + .I1(com_tlm_u_tlm_tx_vc0_eof), + .LO(com_tlm_u_tlm_tx_data_src_lnk_teof_o_5) + ); + VCC com_tlm_u_tlm_tx_ack_mgr_VCC ( + .P(com_tlm_u_tlm_tx_ack_mgr_VCC_2205) + ); + GND com_tlm_u_tlm_tx_ack_mgr_GND ( + .G(com_tlm_u_tlm_tx_ack_mgr_GND_2268) + ); + FDR com_tlm_u_tlm_tx_ack_mgr_jump_retry_tsn ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_ack_mgr_N_69234_i_2264), + .Q(com_tlm_u_tlm_tx_ack_mgr_jump_retry_tsn_2290), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_tx_ack_mgr_retry_src_rdy_o ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_ack_mgr_N_67879_i_2262), + .Q(com_tlm_u_tlm_tx_am_retry_src_rdy), + .R(plm_link_up_i) + ); + FDRSE com_tlm_u_tlm_tx_ack_mgr_retry_lock_o ( + .CE(com_tlm_u_tlm_tx_ack_mgr_N_69140_i_2234), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_ack_mgr_GND_2268), + .Q(com_tlm_u_tlm_tx_am_retry_lock), + .R(plm_link_up_i), + .S(com_N_38093_i) + ); + FDRE com_tlm_u_tlm_tx_ack_mgr_retry_tsn_o_0_ ( + .CE(com_tlm_u_tlm_tx_ack_mgr_N_69068_i_2230), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_ack_mgr_N_38266_i_2261), + .Q(com_tlm_u_tlm_tx_am_retry_tsn[0]), + .R(plm_link_up_i) + ); + FDRE com_tlm_u_tlm_tx_ack_mgr_retry_tsn_o_1_ ( + .CE(com_tlm_u_tlm_tx_ack_mgr_N_69068_i_2230), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_ack_mgr_un4_retry_tsn_o_s_1_2206), + .Q(com_tlm_u_tlm_tx_am_retry_tsn[1]), + .R(plm_link_up_i) + ); + FDRE com_tlm_u_tlm_tx_ack_mgr_retry_tsn_o_2_ ( + .CE(com_tlm_u_tlm_tx_ack_mgr_N_69068_i_2230), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_ack_mgr_un4_retry_tsn_o_s_2_2208), + .Q(com_tlm_u_tlm_tx_am_retry_tsn[2]), + .R(plm_link_up_i) + ); + FDRE com_tlm_u_tlm_tx_ack_mgr_retry_tsn_o_3_ ( + .CE(com_tlm_u_tlm_tx_ack_mgr_N_69068_i_2230), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_ack_mgr_un4_retry_tsn_o_s_3_2210), + .Q(com_tlm_u_tlm_tx_am_retry_tsn[3]), + .R(plm_link_up_i) + ); + FDRE com_tlm_u_tlm_tx_ack_mgr_retry_tsn_o_4_ ( + .CE(com_tlm_u_tlm_tx_ack_mgr_N_69068_i_2230), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_ack_mgr_un4_retry_tsn_o_s_4_2212), + .Q(com_tlm_u_tlm_tx_am_retry_tsn[4]), + .R(plm_link_up_i) + ); + FDRE com_tlm_u_tlm_tx_ack_mgr_retry_tsn_o_5_ ( + .CE(com_tlm_u_tlm_tx_ack_mgr_N_69068_i_2230), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_ack_mgr_un4_retry_tsn_o_s_5_2214), + .Q(com_tlm_u_tlm_tx_am_retry_tsn[5]), + .R(plm_link_up_i) + ); + FDRE com_tlm_u_tlm_tx_ack_mgr_retry_tsn_o_6_ ( + .CE(com_tlm_u_tlm_tx_ack_mgr_N_69068_i_2230), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_ack_mgr_un4_retry_tsn_o_s_6_2216), + .Q(com_tlm_u_tlm_tx_am_retry_tsn[6]), + .R(plm_link_up_i) + ); + FDRE com_tlm_u_tlm_tx_ack_mgr_retry_tsn_o_7_ ( + .CE(com_tlm_u_tlm_tx_ack_mgr_N_69068_i_2230), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_ack_mgr_un4_retry_tsn_o_s_7_2218), + .Q(com_tlm_u_tlm_tx_am_retry_tsn[7]), + .R(plm_link_up_i) + ); + FDRE com_tlm_u_tlm_tx_ack_mgr_retry_tsn_o_8_ ( + .CE(com_tlm_u_tlm_tx_ack_mgr_N_69068_i_2230), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_ack_mgr_un4_retry_tsn_o_s_8_2220), + .Q(com_tlm_u_tlm_tx_am_retry_tsn[8]), + .R(plm_link_up_i) + ); + FDRE com_tlm_u_tlm_tx_ack_mgr_retry_tsn_o_9_ ( + .CE(com_tlm_u_tlm_tx_ack_mgr_N_69068_i_2230), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_ack_mgr_un4_retry_tsn_o_s_9_2222), + .Q(com_tlm_u_tlm_tx_am_retry_tsn[9]), + .R(plm_link_up_i) + ); + FDRE com_tlm_u_tlm_tx_ack_mgr_retry_tsn_o_10_ ( + .CE(com_tlm_u_tlm_tx_ack_mgr_N_69068_i_2230), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_ack_mgr_un4_retry_tsn_o_s_10_2224), + .Q(com_tlm_u_tlm_tx_am_retry_tsn[10]), + .R(plm_link_up_i) + ); + FDRE com_tlm_u_tlm_tx_ack_mgr_retry_tsn_o_11_ ( + .CE(com_tlm_u_tlm_tx_ack_mgr_N_69068_i_2230), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_ack_mgr_un4_retry_tsn_o_s_11_2226), + .Q(com_tlm_u_tlm_tx_am_retry_tsn[11]), + .R(plm_link_up_i) + ); + FDRE com_tlm_u_tlm_tx_ack_mgr_nak_in_retry ( + .CE(com_tlm_u_tlm_tx_ack_mgr_N_69235_i_2232), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_ack_mgr_nak_in_retry19), + .Q(com_tlm_u_tlm_tx_ack_mgr_nak_in_retry_2265), + .R(plm_link_up_i) + ); + FDRSE com_tlm_u_tlm_tx_ack_mgr_nak_req ( + .CE(com_tlm_u_tlm_tx_ack_mgr_un1_lnk_rupdate_ack_i_0_a3_0_a2_0_a4_2228), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_ack_mgr_GND_2268), + .Q(com_tlm_u_tlm_tx_ack_mgr_nak_req_2229), + .R(plm_link_up_i), + .S(com_N_38093_i) + ); + FDRE com_tlm_u_tlm_tx_ack_mgr_ack_pending_o ( + .CE(com_tlm_u_tlm_tx_ack_mgr_mgr_state_0__2287), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_ack_mgr_N_38757_i_2249), + .Q(com_tlm_u_tlm_tx_ack_pending), + .R(plm_link_up_i) + ); + FDSE com_tlm_u_tlm_tx_ack_mgr_latest_ack_tsn_0_ ( + .CE(com_tlm_u_tlm_tx_ack_mgr_N_9704_i_i_i_2267), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_lnk_tupdate_seq[0]), + .Q(com_tlm_u_tlm_tx_ack_mgr_latest_ack_tsn[0]), + .S(plm_link_up_i) + ); + FDSE com_tlm_u_tlm_tx_ack_mgr_latest_ack_tsn_1_ ( + .CE(com_tlm_u_tlm_tx_ack_mgr_N_9704_i_i_i_2267), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_lnk_tupdate_seq[1]), + .Q(com_tlm_u_tlm_tx_ack_mgr_latest_ack_tsn[1]), + .S(plm_link_up_i) + ); + FDSE com_tlm_u_tlm_tx_ack_mgr_latest_ack_tsn_2_ ( + .CE(com_tlm_u_tlm_tx_ack_mgr_N_9704_i_i_i_2267), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_lnk_tupdate_seq[2]), + .Q(com_tlm_u_tlm_tx_ack_mgr_latest_ack_tsn[2]), + .S(plm_link_up_i) + ); + FDSE com_tlm_u_tlm_tx_ack_mgr_latest_ack_tsn_3_ ( + .CE(com_tlm_u_tlm_tx_ack_mgr_N_9704_i_i_i_2267), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_lnk_tupdate_seq[3]), + .Q(com_tlm_u_tlm_tx_ack_mgr_latest_ack_tsn[3]), + .S(plm_link_up_i) + ); + FDSE com_tlm_u_tlm_tx_ack_mgr_latest_ack_tsn_4_ ( + .CE(com_tlm_u_tlm_tx_ack_mgr_N_9704_i_i_i_2267), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_lnk_tupdate_seq[4]), + .Q(com_tlm_u_tlm_tx_ack_mgr_latest_ack_tsn[4]), + .S(plm_link_up_i) + ); + FDSE com_tlm_u_tlm_tx_ack_mgr_latest_ack_tsn_5_ ( + .CE(com_tlm_u_tlm_tx_ack_mgr_N_9704_i_i_i_2267), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_lnk_tupdate_seq[5]), + .Q(com_tlm_u_tlm_tx_ack_mgr_latest_ack_tsn[5]), + .S(plm_link_up_i) + ); + FDSE com_tlm_u_tlm_tx_ack_mgr_latest_ack_tsn_6_ ( + .CE(com_tlm_u_tlm_tx_ack_mgr_N_9704_i_i_i_2267), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_lnk_tupdate_seq[6]), + .Q(com_tlm_u_tlm_tx_ack_mgr_latest_ack_tsn[6]), + .S(plm_link_up_i) + ); + FDSE com_tlm_u_tlm_tx_ack_mgr_latest_ack_tsn_7_ ( + .CE(com_tlm_u_tlm_tx_ack_mgr_N_9704_i_i_i_2267), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_lnk_tupdate_seq[7]), + .Q(com_tlm_u_tlm_tx_ack_mgr_latest_ack_tsn[7]), + .S(plm_link_up_i) + ); + FDSE com_tlm_u_tlm_tx_ack_mgr_latest_ack_tsn_8_ ( + .CE(com_tlm_u_tlm_tx_ack_mgr_N_9704_i_i_i_2267), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_lnk_tupdate_seq[8]), + .Q(com_tlm_u_tlm_tx_ack_mgr_latest_ack_tsn[8]), + .S(plm_link_up_i) + ); + FDSE com_tlm_u_tlm_tx_ack_mgr_latest_ack_tsn_9_ ( + .CE(com_tlm_u_tlm_tx_ack_mgr_N_9704_i_i_i_2267), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_lnk_tupdate_seq[9]), + .Q(com_tlm_u_tlm_tx_ack_mgr_latest_ack_tsn[9]), + .S(plm_link_up_i) + ); + FDSE com_tlm_u_tlm_tx_ack_mgr_latest_ack_tsn_10_ ( + .CE(com_tlm_u_tlm_tx_ack_mgr_N_9704_i_i_i_2267), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_lnk_tupdate_seq[10]), + .Q(com_tlm_u_tlm_tx_ack_mgr_latest_ack_tsn[10]), + .S(plm_link_up_i) + ); + FDSE com_tlm_u_tlm_tx_ack_mgr_latest_ack_tsn_11_ ( + .CE(com_tlm_u_tlm_tx_ack_mgr_N_9704_i_i_i_2267), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_lnk_tupdate_seq[11]), + .Q(com_tlm_u_tlm_tx_ack_mgr_latest_ack_tsn[11]), + .S(plm_link_up_i) + ); + FDSE com_tlm_u_tlm_tx_ack_mgr_lnk_rupdate_seq_q_0_ ( + .CE(com_N_38093_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_lnk_tupdate_seq[0]), + .Q(com_tlm_u_tlm_tx_ack_mgr_lnk_rupdate_seq_q[0]), + .S(plm_link_up_i) + ); + FDSE com_tlm_u_tlm_tx_ack_mgr_lnk_rupdate_seq_q_1_ ( + .CE(com_N_38093_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_lnk_tupdate_seq[1]), + .Q(com_tlm_u_tlm_tx_ack_mgr_lnk_rupdate_seq_q[1]), + .S(plm_link_up_i) + ); + FDSE com_tlm_u_tlm_tx_ack_mgr_lnk_rupdate_seq_q_2_ ( + .CE(com_N_38093_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_lnk_tupdate_seq[2]), + .Q(com_tlm_u_tlm_tx_ack_mgr_lnk_rupdate_seq_q[2]), + .S(plm_link_up_i) + ); + FDSE com_tlm_u_tlm_tx_ack_mgr_lnk_rupdate_seq_q_3_ ( + .CE(com_N_38093_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_lnk_tupdate_seq[3]), + .Q(com_tlm_u_tlm_tx_ack_mgr_lnk_rupdate_seq_q[3]), + .S(plm_link_up_i) + ); + FDSE com_tlm_u_tlm_tx_ack_mgr_lnk_rupdate_seq_q_4_ ( + .CE(com_N_38093_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_lnk_tupdate_seq[4]), + .Q(com_tlm_u_tlm_tx_ack_mgr_lnk_rupdate_seq_q[4]), + .S(plm_link_up_i) + ); + FDSE com_tlm_u_tlm_tx_ack_mgr_lnk_rupdate_seq_q_5_ ( + .CE(com_N_38093_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_lnk_tupdate_seq[5]), + .Q(com_tlm_u_tlm_tx_ack_mgr_lnk_rupdate_seq_q[5]), + .S(plm_link_up_i) + ); + FDSE com_tlm_u_tlm_tx_ack_mgr_lnk_rupdate_seq_q_6_ ( + .CE(com_N_38093_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_lnk_tupdate_seq[6]), + .Q(com_tlm_u_tlm_tx_ack_mgr_lnk_rupdate_seq_q[6]), + .S(plm_link_up_i) + ); + FDSE com_tlm_u_tlm_tx_ack_mgr_lnk_rupdate_seq_q_7_ ( + .CE(com_N_38093_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_lnk_tupdate_seq[7]), + .Q(com_tlm_u_tlm_tx_ack_mgr_lnk_rupdate_seq_q[7]), + .S(plm_link_up_i) + ); + FDSE com_tlm_u_tlm_tx_ack_mgr_lnk_rupdate_seq_q_8_ ( + .CE(com_N_38093_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_lnk_tupdate_seq[8]), + .Q(com_tlm_u_tlm_tx_ack_mgr_lnk_rupdate_seq_q[8]), + .S(plm_link_up_i) + ); + FDSE com_tlm_u_tlm_tx_ack_mgr_lnk_rupdate_seq_q_9_ ( + .CE(com_N_38093_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_lnk_tupdate_seq[9]), + .Q(com_tlm_u_tlm_tx_ack_mgr_lnk_rupdate_seq_q[9]), + .S(plm_link_up_i) + ); + FDSE com_tlm_u_tlm_tx_ack_mgr_lnk_rupdate_seq_q_10_ ( + .CE(com_N_38093_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_lnk_tupdate_seq[10]), + .Q(com_tlm_u_tlm_tx_ack_mgr_lnk_rupdate_seq_q[10]), + .S(plm_link_up_i) + ); + FDSE com_tlm_u_tlm_tx_ack_mgr_lnk_rupdate_seq_q_11_ ( + .CE(com_N_38093_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_lnk_tupdate_seq[11]), + .Q(com_tlm_u_tlm_tx_ack_mgr_lnk_rupdate_seq_q[11]), + .S(plm_link_up_i) + ); + MUXCY_L com_tlm_u_tlm_tx_ack_mgr_unreg_frees_pend_un1_frees_pending_0_I_1 ( + .CI(com_tlm_u_tlm_tx_ack_mgr_VCC_2205), + .DI(com_tlm_u_tlm_tx_ack_mgr_GND_2268), + .LO(com_tlm_u_tlm_tx_ack_mgr_data_tmp_0[0]), + .S(com_tlm_u_tlm_tx_ack_mgr_N_43) + ); + MUXCY_L com_tlm_u_tlm_tx_ack_mgr_unreg_frees_pend_un1_frees_pending_0_I_10 ( + .CI(com_tlm_u_tlm_tx_ack_mgr_data_tmp_0[1]), + .DI(com_tlm_u_tlm_tx_ack_mgr_GND_2268), + .LO(com_tlm_u_tlm_tx_ack_mgr_data_tmp_0[2]), + .S(com_tlm_u_tlm_tx_ack_mgr_N_35) + ); + MUXCY_L com_tlm_u_tlm_tx_ack_mgr_unreg_frees_pend_un1_frees_pending_0_I_28 ( + .CI(com_tlm_u_tlm_tx_ack_mgr_data_tmp_0[2]), + .DI(com_tlm_u_tlm_tx_ack_mgr_GND_2268), + .LO(com_tlm_u_tlm_tx_ack_mgr_data_tmp_0[3]), + .S(com_tlm_u_tlm_tx_ack_mgr_N_19) + ); + MUXCY_L com_tlm_u_tlm_tx_ack_mgr_unreg_frees_pend_un1_frees_pending_0_I_37 ( + .CI(com_tlm_u_tlm_tx_ack_mgr_data_tmp_0[3]), + .DI(com_tlm_u_tlm_tx_ack_mgr_GND_2268), + .LO(com_tlm_u_tlm_tx_ack_mgr_data_tmp[4]), + .S(com_tlm_u_tlm_tx_ack_mgr_N_11) + ); + MUXCY_L com_tlm_u_tlm_tx_ack_mgr_unreg_frees_pend_un1_frees_pending_0_I_46 ( + .CI(com_tlm_u_tlm_tx_ack_mgr_data_tmp_0[0]), + .DI(com_tlm_u_tlm_tx_ack_mgr_GND_2268), + .LO(com_tlm_u_tlm_tx_ack_mgr_data_tmp_0[1]), + .S(com_tlm_u_tlm_tx_ack_mgr_N_3) + ); + MUXCY_L com_tlm_u_tlm_tx_ack_mgr_unreg_skips_pend_un1_skips_pending_0_I_1 ( + .CI(com_tlm_u_tlm_tx_ack_mgr_VCC_2205), + .DI(com_tlm_u_tlm_tx_ack_mgr_GND_2268), + .LO(com_tlm_u_tlm_tx_ack_mgr_data_tmp[0]), + .S(com_tlm_u_tlm_tx_ack_mgr_N_43_0) + ); + MUXCY_L com_tlm_u_tlm_tx_ack_mgr_unreg_skips_pend_un1_skips_pending_0_I_10 ( + .CI(com_tlm_u_tlm_tx_ack_mgr_data_tmp[1]), + .DI(com_tlm_u_tlm_tx_ack_mgr_GND_2268), + .LO(com_tlm_u_tlm_tx_ack_mgr_data_tmp[2]), + .S(com_tlm_u_tlm_tx_ack_mgr_N_35_0) + ); + MUXCY_L com_tlm_u_tlm_tx_ack_mgr_unreg_skips_pend_un1_skips_pending_0_I_28 ( + .CI(com_tlm_u_tlm_tx_ack_mgr_data_tmp[2]), + .DI(com_tlm_u_tlm_tx_ack_mgr_GND_2268), + .LO(com_tlm_u_tlm_tx_ack_mgr_data_tmp[3]), + .S(com_tlm_u_tlm_tx_ack_mgr_N_19_0) + ); + MUXCY_L com_tlm_u_tlm_tx_ack_mgr_unreg_skips_pend_un1_skips_pending_0_I_37 ( + .CI(com_tlm_u_tlm_tx_ack_mgr_data_tmp[3]), + .DI(com_tlm_u_tlm_tx_ack_mgr_GND_2268), + .LO(com_tlm_u_tlm_tx_ack_mgr_data_tmp_0[4]), + .S(com_tlm_u_tlm_tx_ack_mgr_N_11_0) + ); + MUXCY_L com_tlm_u_tlm_tx_ack_mgr_unreg_skips_pend_un1_skips_pending_0_I_46 ( + .CI(com_tlm_u_tlm_tx_ack_mgr_data_tmp[0]), + .DI(com_tlm_u_tlm_tx_ack_mgr_GND_2268), + .LO(com_tlm_u_tlm_tx_ack_mgr_data_tmp[1]), + .S(com_tlm_u_tlm_tx_ack_mgr_N_3_0) + ); + MUXCY_L com_tlm_u_tlm_tx_ack_mgr_un1_oldest_tsn_1_cry_0 ( + .CI(com_tlm_u_tlm_tx_ack_mgr_un1_fifo_ren_iv_0_a2_0_a4[0]), + .DI(com_tlm_u_tlm_tx_ack_mgr_GND_2268), + .LO(com_tlm_u_tlm_tx_ack_mgr_un1_oldest_tsn_1_cry_0_2194), + .S(com_tlm_u_tlm_tx_ack_mgr_un1_oldest_tsn_1_axb_0_2247) + ); + XORCY com_tlm_u_tlm_tx_ack_mgr_un1_oldest_tsn_1_s_0 ( + .CI(com_tlm_u_tlm_tx_ack_mgr_un1_fifo_ren_iv_0_a2_0_a4[0]), + .LI(com_tlm_u_tlm_tx_ack_mgr_un1_oldest_tsn_1_axb_0_2247), + .O(com_tlm_u_tlm_tx_ack_mgr_un1_oldest_tsn_1_s_0_2280) + ); + MUXCY_L com_tlm_u_tlm_tx_ack_mgr_un1_oldest_tsn_1_cry_1 ( + .CI(com_tlm_u_tlm_tx_ack_mgr_un1_oldest_tsn_1_cry_0_2194), + .DI(com_tlm_u_tlm_tx_ack_mgr_GND_2268), + .LO(com_tlm_u_tlm_tx_ack_mgr_un1_oldest_tsn_1_cry_1_2195), + .S(com_tlm_u_tlm_tx_ack_mgr_un1_oldest_tsn_1_axb_1_2246) + ); + XORCY com_tlm_u_tlm_tx_ack_mgr_un1_oldest_tsn_1_s_1 ( + .CI(com_tlm_u_tlm_tx_ack_mgr_un1_oldest_tsn_1_cry_0_2194), + .LI(com_tlm_u_tlm_tx_ack_mgr_un1_oldest_tsn_1_axb_1_2246), + .O(com_tlm_u_tlm_tx_ack_mgr_un1_oldest_tsn_1_s_1_2279) + ); + MUXCY_L com_tlm_u_tlm_tx_ack_mgr_un1_oldest_tsn_1_cry_2 ( + .CI(com_tlm_u_tlm_tx_ack_mgr_un1_oldest_tsn_1_cry_1_2195), + .DI(com_tlm_u_tlm_tx_ack_mgr_GND_2268), + .LO(com_tlm_u_tlm_tx_ack_mgr_un1_oldest_tsn_1_cry_2_2196), + .S(com_tlm_u_tlm_tx_ack_mgr_un1_oldest_tsn_1_axb_2_2245) + ); + XORCY com_tlm_u_tlm_tx_ack_mgr_un1_oldest_tsn_1_s_2 ( + .CI(com_tlm_u_tlm_tx_ack_mgr_un1_oldest_tsn_1_cry_1_2195), + .LI(com_tlm_u_tlm_tx_ack_mgr_un1_oldest_tsn_1_axb_2_2245), + .O(com_tlm_u_tlm_tx_ack_mgr_un1_oldest_tsn_1_s_2_2278) + ); + MUXCY_L com_tlm_u_tlm_tx_ack_mgr_un1_oldest_tsn_1_cry_3 ( + .CI(com_tlm_u_tlm_tx_ack_mgr_un1_oldest_tsn_1_cry_2_2196), + .DI(com_tlm_u_tlm_tx_ack_mgr_GND_2268), + .LO(com_tlm_u_tlm_tx_ack_mgr_un1_oldest_tsn_1_cry_3_2197), + .S(com_tlm_u_tlm_tx_ack_mgr_un1_oldest_tsn_1_axb_3_2244) + ); + XORCY com_tlm_u_tlm_tx_ack_mgr_un1_oldest_tsn_1_s_3 ( + .CI(com_tlm_u_tlm_tx_ack_mgr_un1_oldest_tsn_1_cry_2_2196), + .LI(com_tlm_u_tlm_tx_ack_mgr_un1_oldest_tsn_1_axb_3_2244), + .O(com_tlm_u_tlm_tx_ack_mgr_un1_oldest_tsn_1_s_3_2277) + ); + MUXCY_L com_tlm_u_tlm_tx_ack_mgr_un1_oldest_tsn_1_cry_4 ( + .CI(com_tlm_u_tlm_tx_ack_mgr_un1_oldest_tsn_1_cry_3_2197), + .DI(com_tlm_u_tlm_tx_ack_mgr_GND_2268), + .LO(com_tlm_u_tlm_tx_ack_mgr_un1_oldest_tsn_1_cry_4_2198), + .S(com_tlm_u_tlm_tx_ack_mgr_un1_oldest_tsn_1_axb_4_2243) + ); + XORCY com_tlm_u_tlm_tx_ack_mgr_un1_oldest_tsn_1_s_4 ( + .CI(com_tlm_u_tlm_tx_ack_mgr_un1_oldest_tsn_1_cry_3_2197), + .LI(com_tlm_u_tlm_tx_ack_mgr_un1_oldest_tsn_1_axb_4_2243), + .O(com_tlm_u_tlm_tx_ack_mgr_un1_oldest_tsn_1_s_4_2276) + ); + MUXCY_L com_tlm_u_tlm_tx_ack_mgr_un1_oldest_tsn_1_cry_5 ( + .CI(com_tlm_u_tlm_tx_ack_mgr_un1_oldest_tsn_1_cry_4_2198), + .DI(com_tlm_u_tlm_tx_ack_mgr_GND_2268), + .LO(com_tlm_u_tlm_tx_ack_mgr_un1_oldest_tsn_1_cry_5_2199), + .S(com_tlm_u_tlm_tx_ack_mgr_un1_oldest_tsn_1_axb_5_2242) + ); + XORCY com_tlm_u_tlm_tx_ack_mgr_un1_oldest_tsn_1_s_5 ( + .CI(com_tlm_u_tlm_tx_ack_mgr_un1_oldest_tsn_1_cry_4_2198), + .LI(com_tlm_u_tlm_tx_ack_mgr_un1_oldest_tsn_1_axb_5_2242), + .O(com_tlm_u_tlm_tx_ack_mgr_un1_oldest_tsn_1_s_5_2275) + ); + MUXCY_L com_tlm_u_tlm_tx_ack_mgr_un1_oldest_tsn_1_cry_6 ( + .CI(com_tlm_u_tlm_tx_ack_mgr_un1_oldest_tsn_1_cry_5_2199), + .DI(com_tlm_u_tlm_tx_ack_mgr_GND_2268), + .LO(com_tlm_u_tlm_tx_ack_mgr_un1_oldest_tsn_1_cry_6_2200), + .S(com_tlm_u_tlm_tx_ack_mgr_un1_oldest_tsn_1_axb_6_2241) + ); + XORCY com_tlm_u_tlm_tx_ack_mgr_un1_oldest_tsn_1_s_6 ( + .CI(com_tlm_u_tlm_tx_ack_mgr_un1_oldest_tsn_1_cry_5_2199), + .LI(com_tlm_u_tlm_tx_ack_mgr_un1_oldest_tsn_1_axb_6_2241), + .O(com_tlm_u_tlm_tx_ack_mgr_un1_oldest_tsn_1_s_6_2274) + ); + MUXCY_L com_tlm_u_tlm_tx_ack_mgr_un1_oldest_tsn_1_cry_7 ( + .CI(com_tlm_u_tlm_tx_ack_mgr_un1_oldest_tsn_1_cry_6_2200), + .DI(com_tlm_u_tlm_tx_ack_mgr_GND_2268), + .LO(com_tlm_u_tlm_tx_ack_mgr_un1_oldest_tsn_1_cry_7_2201), + .S(com_tlm_u_tlm_tx_ack_mgr_un1_oldest_tsn_1_axb_7_2240) + ); + XORCY com_tlm_u_tlm_tx_ack_mgr_un1_oldest_tsn_1_s_7 ( + .CI(com_tlm_u_tlm_tx_ack_mgr_un1_oldest_tsn_1_cry_6_2200), + .LI(com_tlm_u_tlm_tx_ack_mgr_un1_oldest_tsn_1_axb_7_2240), + .O(com_tlm_u_tlm_tx_ack_mgr_un1_oldest_tsn_1_s_7_2273) + ); + MUXCY_L com_tlm_u_tlm_tx_ack_mgr_un1_oldest_tsn_1_cry_8 ( + .CI(com_tlm_u_tlm_tx_ack_mgr_un1_oldest_tsn_1_cry_7_2201), + .DI(com_tlm_u_tlm_tx_ack_mgr_GND_2268), + .LO(com_tlm_u_tlm_tx_ack_mgr_un1_oldest_tsn_1_cry_8_2202), + .S(com_tlm_u_tlm_tx_ack_mgr_un1_oldest_tsn_1_axb_8_2239) + ); + XORCY com_tlm_u_tlm_tx_ack_mgr_un1_oldest_tsn_1_s_8 ( + .CI(com_tlm_u_tlm_tx_ack_mgr_un1_oldest_tsn_1_cry_7_2201), + .LI(com_tlm_u_tlm_tx_ack_mgr_un1_oldest_tsn_1_axb_8_2239), + .O(com_tlm_u_tlm_tx_ack_mgr_un1_oldest_tsn_1_s_8_2272) + ); + MUXCY_L com_tlm_u_tlm_tx_ack_mgr_un1_oldest_tsn_1_cry_9 ( + .CI(com_tlm_u_tlm_tx_ack_mgr_un1_oldest_tsn_1_cry_8_2202), + .DI(com_tlm_u_tlm_tx_ack_mgr_GND_2268), + .LO(com_tlm_u_tlm_tx_ack_mgr_un1_oldest_tsn_1_cry_9_2203), + .S(com_tlm_u_tlm_tx_ack_mgr_un1_oldest_tsn_1_axb_9_2238) + ); + XORCY com_tlm_u_tlm_tx_ack_mgr_un1_oldest_tsn_1_s_9 ( + .CI(com_tlm_u_tlm_tx_ack_mgr_un1_oldest_tsn_1_cry_8_2202), + .LI(com_tlm_u_tlm_tx_ack_mgr_un1_oldest_tsn_1_axb_9_2238), + .O(com_tlm_u_tlm_tx_ack_mgr_un1_oldest_tsn_1_s_9_2271) + ); + MUXCY_L com_tlm_u_tlm_tx_ack_mgr_un1_oldest_tsn_1_cry_10 ( + .CI(com_tlm_u_tlm_tx_ack_mgr_un1_oldest_tsn_1_cry_9_2203), + .DI(com_tlm_u_tlm_tx_ack_mgr_GND_2268), + .LO(com_tlm_u_tlm_tx_ack_mgr_un1_oldest_tsn_1_cry_10_2204), + .S(com_tlm_u_tlm_tx_ack_mgr_un1_oldest_tsn_1_axb_10_2237) + ); + XORCY com_tlm_u_tlm_tx_ack_mgr_un1_oldest_tsn_1_s_10 ( + .CI(com_tlm_u_tlm_tx_ack_mgr_un1_oldest_tsn_1_cry_9_2203), + .LI(com_tlm_u_tlm_tx_ack_mgr_un1_oldest_tsn_1_axb_10_2237), + .O(com_tlm_u_tlm_tx_ack_mgr_un1_oldest_tsn_1_s_10_2270) + ); + XORCY com_tlm_u_tlm_tx_ack_mgr_un1_oldest_tsn_1_s_11 ( + .CI(com_tlm_u_tlm_tx_ack_mgr_un1_oldest_tsn_1_cry_10_2204), + .LI(com_tlm_u_tlm_tx_ack_mgr_un1_oldest_tsn_1_axb_11_2236), + .O(com_tlm_u_tlm_tx_ack_mgr_un1_oldest_tsn_1_s_11_2269) + ); + MUXCY_L com_tlm_u_tlm_tx_ack_mgr_un4_retry_tsn_o_cry_0 ( + .CI(com_tlm_u_tlm_tx_ack_mgr_VCC_2205), + .DI(com_tlm_u_tlm_tx_ack_mgr_GND_2268), + .LO(com_tlm_u_tlm_tx_ack_mgr_un4_retry_tsn_o_cry_0_2207), + .S(com_tlm_u_tlm_tx_ack_mgr_un4_retry_tsn_o_axb_0_2289) + ); + MUXCY_L com_tlm_u_tlm_tx_ack_mgr_un4_retry_tsn_o_cry_1 ( + .CI(com_tlm_u_tlm_tx_ack_mgr_un4_retry_tsn_o_cry_0_2207), + .DI(com_tlm_u_tlm_tx_ack_mgr_GND_2268), + .LO(com_tlm_u_tlm_tx_ack_mgr_un4_retry_tsn_o_cry_1_2209), + .S(com_tlm_u_tlm_tx_ack_mgr_un4_retry_tsn_o_axb_1_2260) + ); + XORCY com_tlm_u_tlm_tx_ack_mgr_un4_retry_tsn_o_s_1 ( + .CI(com_tlm_u_tlm_tx_ack_mgr_un4_retry_tsn_o_cry_0_2207), + .LI(com_tlm_u_tlm_tx_ack_mgr_un4_retry_tsn_o_axb_1_2260), + .O(com_tlm_u_tlm_tx_ack_mgr_un4_retry_tsn_o_s_1_2206) + ); + MUXCY_L com_tlm_u_tlm_tx_ack_mgr_un4_retry_tsn_o_cry_2 ( + .CI(com_tlm_u_tlm_tx_ack_mgr_un4_retry_tsn_o_cry_1_2209), + .DI(com_tlm_u_tlm_tx_ack_mgr_GND_2268), + .LO(com_tlm_u_tlm_tx_ack_mgr_un4_retry_tsn_o_cry_2_2211), + .S(com_tlm_u_tlm_tx_ack_mgr_un4_retry_tsn_o_axb_2_2259) + ); + XORCY com_tlm_u_tlm_tx_ack_mgr_un4_retry_tsn_o_s_2 ( + .CI(com_tlm_u_tlm_tx_ack_mgr_un4_retry_tsn_o_cry_1_2209), + .LI(com_tlm_u_tlm_tx_ack_mgr_un4_retry_tsn_o_axb_2_2259), + .O(com_tlm_u_tlm_tx_ack_mgr_un4_retry_tsn_o_s_2_2208) + ); + MUXCY_L com_tlm_u_tlm_tx_ack_mgr_un4_retry_tsn_o_cry_3 ( + .CI(com_tlm_u_tlm_tx_ack_mgr_un4_retry_tsn_o_cry_2_2211), + .DI(com_tlm_u_tlm_tx_ack_mgr_GND_2268), + .LO(com_tlm_u_tlm_tx_ack_mgr_un4_retry_tsn_o_cry_3_2213), + .S(com_tlm_u_tlm_tx_ack_mgr_un4_retry_tsn_o_axb_3_2258) + ); + XORCY com_tlm_u_tlm_tx_ack_mgr_un4_retry_tsn_o_s_3 ( + .CI(com_tlm_u_tlm_tx_ack_mgr_un4_retry_tsn_o_cry_2_2211), + .LI(com_tlm_u_tlm_tx_ack_mgr_un4_retry_tsn_o_axb_3_2258), + .O(com_tlm_u_tlm_tx_ack_mgr_un4_retry_tsn_o_s_3_2210) + ); + MUXCY_L com_tlm_u_tlm_tx_ack_mgr_un4_retry_tsn_o_cry_4 ( + .CI(com_tlm_u_tlm_tx_ack_mgr_un4_retry_tsn_o_cry_3_2213), + .DI(com_tlm_u_tlm_tx_ack_mgr_GND_2268), + .LO(com_tlm_u_tlm_tx_ack_mgr_un4_retry_tsn_o_cry_4_2215), + .S(com_tlm_u_tlm_tx_ack_mgr_un4_retry_tsn_o_axb_4_2257) + ); + XORCY com_tlm_u_tlm_tx_ack_mgr_un4_retry_tsn_o_s_4 ( + .CI(com_tlm_u_tlm_tx_ack_mgr_un4_retry_tsn_o_cry_3_2213), + .LI(com_tlm_u_tlm_tx_ack_mgr_un4_retry_tsn_o_axb_4_2257), + .O(com_tlm_u_tlm_tx_ack_mgr_un4_retry_tsn_o_s_4_2212) + ); + MUXCY_L com_tlm_u_tlm_tx_ack_mgr_un4_retry_tsn_o_cry_5 ( + .CI(com_tlm_u_tlm_tx_ack_mgr_un4_retry_tsn_o_cry_4_2215), + .DI(com_tlm_u_tlm_tx_ack_mgr_GND_2268), + .LO(com_tlm_u_tlm_tx_ack_mgr_un4_retry_tsn_o_cry_5_2217), + .S(com_tlm_u_tlm_tx_ack_mgr_un4_retry_tsn_o_axb_5_2256) + ); + XORCY com_tlm_u_tlm_tx_ack_mgr_un4_retry_tsn_o_s_5 ( + .CI(com_tlm_u_tlm_tx_ack_mgr_un4_retry_tsn_o_cry_4_2215), + .LI(com_tlm_u_tlm_tx_ack_mgr_un4_retry_tsn_o_axb_5_2256), + .O(com_tlm_u_tlm_tx_ack_mgr_un4_retry_tsn_o_s_5_2214) + ); + MUXCY_L com_tlm_u_tlm_tx_ack_mgr_un4_retry_tsn_o_cry_6 ( + .CI(com_tlm_u_tlm_tx_ack_mgr_un4_retry_tsn_o_cry_5_2217), + .DI(com_tlm_u_tlm_tx_ack_mgr_GND_2268), + .LO(com_tlm_u_tlm_tx_ack_mgr_un4_retry_tsn_o_cry_6_2219), + .S(com_tlm_u_tlm_tx_ack_mgr_un4_retry_tsn_o_axb_6_2255) + ); + XORCY com_tlm_u_tlm_tx_ack_mgr_un4_retry_tsn_o_s_6 ( + .CI(com_tlm_u_tlm_tx_ack_mgr_un4_retry_tsn_o_cry_5_2217), + .LI(com_tlm_u_tlm_tx_ack_mgr_un4_retry_tsn_o_axb_6_2255), + .O(com_tlm_u_tlm_tx_ack_mgr_un4_retry_tsn_o_s_6_2216) + ); + MUXCY_L com_tlm_u_tlm_tx_ack_mgr_un4_retry_tsn_o_cry_7 ( + .CI(com_tlm_u_tlm_tx_ack_mgr_un4_retry_tsn_o_cry_6_2219), + .DI(com_tlm_u_tlm_tx_ack_mgr_GND_2268), + .LO(com_tlm_u_tlm_tx_ack_mgr_un4_retry_tsn_o_cry_7_2221), + .S(com_tlm_u_tlm_tx_ack_mgr_un4_retry_tsn_o_axb_7_2254) + ); + XORCY com_tlm_u_tlm_tx_ack_mgr_un4_retry_tsn_o_s_7 ( + .CI(com_tlm_u_tlm_tx_ack_mgr_un4_retry_tsn_o_cry_6_2219), + .LI(com_tlm_u_tlm_tx_ack_mgr_un4_retry_tsn_o_axb_7_2254), + .O(com_tlm_u_tlm_tx_ack_mgr_un4_retry_tsn_o_s_7_2218) + ); + MUXCY_L com_tlm_u_tlm_tx_ack_mgr_un4_retry_tsn_o_cry_8 ( + .CI(com_tlm_u_tlm_tx_ack_mgr_un4_retry_tsn_o_cry_7_2221), + .DI(com_tlm_u_tlm_tx_ack_mgr_GND_2268), + .LO(com_tlm_u_tlm_tx_ack_mgr_un4_retry_tsn_o_cry_8_2223), + .S(com_tlm_u_tlm_tx_ack_mgr_un4_retry_tsn_o_axb_8_2253) + ); + XORCY com_tlm_u_tlm_tx_ack_mgr_un4_retry_tsn_o_s_8 ( + .CI(com_tlm_u_tlm_tx_ack_mgr_un4_retry_tsn_o_cry_7_2221), + .LI(com_tlm_u_tlm_tx_ack_mgr_un4_retry_tsn_o_axb_8_2253), + .O(com_tlm_u_tlm_tx_ack_mgr_un4_retry_tsn_o_s_8_2220) + ); + MUXCY_L com_tlm_u_tlm_tx_ack_mgr_un4_retry_tsn_o_cry_9 ( + .CI(com_tlm_u_tlm_tx_ack_mgr_un4_retry_tsn_o_cry_8_2223), + .DI(com_tlm_u_tlm_tx_ack_mgr_GND_2268), + .LO(com_tlm_u_tlm_tx_ack_mgr_un4_retry_tsn_o_cry_9_2225), + .S(com_tlm_u_tlm_tx_ack_mgr_un4_retry_tsn_o_axb_9_2252) + ); + XORCY com_tlm_u_tlm_tx_ack_mgr_un4_retry_tsn_o_s_9 ( + .CI(com_tlm_u_tlm_tx_ack_mgr_un4_retry_tsn_o_cry_8_2223), + .LI(com_tlm_u_tlm_tx_ack_mgr_un4_retry_tsn_o_axb_9_2252), + .O(com_tlm_u_tlm_tx_ack_mgr_un4_retry_tsn_o_s_9_2222) + ); + MUXCY_L com_tlm_u_tlm_tx_ack_mgr_un4_retry_tsn_o_cry_10 ( + .CI(com_tlm_u_tlm_tx_ack_mgr_un4_retry_tsn_o_cry_9_2225), + .DI(com_tlm_u_tlm_tx_ack_mgr_GND_2268), + .LO(com_tlm_u_tlm_tx_ack_mgr_un4_retry_tsn_o_cry_10_2227), + .S(com_tlm_u_tlm_tx_ack_mgr_un4_retry_tsn_o_axb_10_2251) + ); + XORCY com_tlm_u_tlm_tx_ack_mgr_un4_retry_tsn_o_s_10 ( + .CI(com_tlm_u_tlm_tx_ack_mgr_un4_retry_tsn_o_cry_9_2225), + .LI(com_tlm_u_tlm_tx_ack_mgr_un4_retry_tsn_o_axb_10_2251), + .O(com_tlm_u_tlm_tx_ack_mgr_un4_retry_tsn_o_s_10_2224) + ); + XORCY com_tlm_u_tlm_tx_ack_mgr_un4_retry_tsn_o_s_11 ( + .CI(com_tlm_u_tlm_tx_ack_mgr_un4_retry_tsn_o_cry_10_2227), + .LI(com_tlm_u_tlm_tx_ack_mgr_un4_retry_tsn_o_axb_11_2250), + .O(com_tlm_u_tlm_tx_ack_mgr_un4_retry_tsn_o_s_11_2226) + ); + FDSE com_tlm_u_tlm_tx_ack_mgr_newest_freed_tsn_0_ ( + .CE(com_tlm_u_tlm_tx_N_38179_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_ack_mgr_newest_freed_tsn_s[0]), + .Q(com_tlm_u_tlm_tx_ack_mgr_newest_freed_tsn[0]), + .S(plm_link_up_i) + ); + MUXCY_L com_tlm_u_tlm_tx_ack_mgr_newest_freed_tsn_cry_1_ ( + .CI(com_tlm_u_tlm_tx_ack_mgr_newest_freed_tsn[0]), + .DI(com_tlm_u_tlm_tx_ack_mgr_GND_2268), + .LO(com_tlm_u_tlm_tx_ack_mgr_newest_freed_tsn_cry[1]), + .S(com_tlm_u_tlm_tx_ack_mgr_newest_freed_tsn_qxu[1]) + ); + XORCY com_tlm_u_tlm_tx_ack_mgr_newest_freed_tsn_s_1_ ( + .CI(com_tlm_u_tlm_tx_ack_mgr_newest_freed_tsn[0]), + .LI(com_tlm_u_tlm_tx_ack_mgr_newest_freed_tsn_qxu[1]), + .O(com_tlm_u_tlm_tx_ack_mgr_newest_freed_tsn_s[1]) + ); + FDSE com_tlm_u_tlm_tx_ack_mgr_newest_freed_tsn_1_ ( + .CE(com_tlm_u_tlm_tx_N_38179_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_ack_mgr_newest_freed_tsn_s[1]), + .Q(com_tlm_u_tlm_tx_ack_mgr_newest_freed_tsn[1]), + .S(plm_link_up_i) + ); + MUXCY_L com_tlm_u_tlm_tx_ack_mgr_newest_freed_tsn_cry_2_ ( + .CI(com_tlm_u_tlm_tx_ack_mgr_newest_freed_tsn_cry[1]), + .DI(com_tlm_u_tlm_tx_ack_mgr_GND_2268), + .LO(com_tlm_u_tlm_tx_ack_mgr_newest_freed_tsn_cry[2]), + .S(com_tlm_u_tlm_tx_ack_mgr_newest_freed_tsn_qxu[2]) + ); + XORCY com_tlm_u_tlm_tx_ack_mgr_newest_freed_tsn_s_2_ ( + .CI(com_tlm_u_tlm_tx_ack_mgr_newest_freed_tsn_cry[1]), + .LI(com_tlm_u_tlm_tx_ack_mgr_newest_freed_tsn_qxu[2]), + .O(com_tlm_u_tlm_tx_ack_mgr_newest_freed_tsn_s[2]) + ); + FDSE com_tlm_u_tlm_tx_ack_mgr_newest_freed_tsn_2_ ( + .CE(com_tlm_u_tlm_tx_N_38179_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_ack_mgr_newest_freed_tsn_s[2]), + .Q(com_tlm_u_tlm_tx_ack_mgr_newest_freed_tsn[2]), + .S(plm_link_up_i) + ); + MUXCY_L com_tlm_u_tlm_tx_ack_mgr_newest_freed_tsn_cry_3_ ( + .CI(com_tlm_u_tlm_tx_ack_mgr_newest_freed_tsn_cry[2]), + .DI(com_tlm_u_tlm_tx_ack_mgr_GND_2268), + .LO(com_tlm_u_tlm_tx_ack_mgr_newest_freed_tsn_cry[3]), + .S(com_tlm_u_tlm_tx_ack_mgr_newest_freed_tsn_qxu[3]) + ); + XORCY com_tlm_u_tlm_tx_ack_mgr_newest_freed_tsn_s_3_ ( + .CI(com_tlm_u_tlm_tx_ack_mgr_newest_freed_tsn_cry[2]), + .LI(com_tlm_u_tlm_tx_ack_mgr_newest_freed_tsn_qxu[3]), + .O(com_tlm_u_tlm_tx_ack_mgr_newest_freed_tsn_s[3]) + ); + FDSE com_tlm_u_tlm_tx_ack_mgr_newest_freed_tsn_3_ ( + .CE(com_tlm_u_tlm_tx_N_38179_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_ack_mgr_newest_freed_tsn_s[3]), + .Q(com_tlm_u_tlm_tx_ack_mgr_newest_freed_tsn[3]), + .S(plm_link_up_i) + ); + MUXCY_L com_tlm_u_tlm_tx_ack_mgr_newest_freed_tsn_cry_4_ ( + .CI(com_tlm_u_tlm_tx_ack_mgr_newest_freed_tsn_cry[3]), + .DI(com_tlm_u_tlm_tx_ack_mgr_GND_2268), + .LO(com_tlm_u_tlm_tx_ack_mgr_newest_freed_tsn_cry[4]), + .S(com_tlm_u_tlm_tx_ack_mgr_newest_freed_tsn_qxu[4]) + ); + XORCY com_tlm_u_tlm_tx_ack_mgr_newest_freed_tsn_s_4_ ( + .CI(com_tlm_u_tlm_tx_ack_mgr_newest_freed_tsn_cry[3]), + .LI(com_tlm_u_tlm_tx_ack_mgr_newest_freed_tsn_qxu[4]), + .O(com_tlm_u_tlm_tx_ack_mgr_newest_freed_tsn_s[4]) + ); + FDSE com_tlm_u_tlm_tx_ack_mgr_newest_freed_tsn_4_ ( + .CE(com_tlm_u_tlm_tx_N_38179_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_ack_mgr_newest_freed_tsn_s[4]), + .Q(com_tlm_u_tlm_tx_ack_mgr_newest_freed_tsn[4]), + .S(plm_link_up_i) + ); + MUXCY_L com_tlm_u_tlm_tx_ack_mgr_newest_freed_tsn_cry_5_ ( + .CI(com_tlm_u_tlm_tx_ack_mgr_newest_freed_tsn_cry[4]), + .DI(com_tlm_u_tlm_tx_ack_mgr_GND_2268), + .LO(com_tlm_u_tlm_tx_ack_mgr_newest_freed_tsn_cry[5]), + .S(com_tlm_u_tlm_tx_ack_mgr_newest_freed_tsn_qxu[5]) + ); + XORCY com_tlm_u_tlm_tx_ack_mgr_newest_freed_tsn_s_5_ ( + .CI(com_tlm_u_tlm_tx_ack_mgr_newest_freed_tsn_cry[4]), + .LI(com_tlm_u_tlm_tx_ack_mgr_newest_freed_tsn_qxu[5]), + .O(com_tlm_u_tlm_tx_ack_mgr_newest_freed_tsn_s[5]) + ); + FDSE com_tlm_u_tlm_tx_ack_mgr_newest_freed_tsn_5_ ( + .CE(com_tlm_u_tlm_tx_N_38179_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_ack_mgr_newest_freed_tsn_s[5]), + .Q(com_tlm_u_tlm_tx_ack_mgr_newest_freed_tsn[5]), + .S(plm_link_up_i) + ); + MUXCY_L com_tlm_u_tlm_tx_ack_mgr_newest_freed_tsn_cry_6_ ( + .CI(com_tlm_u_tlm_tx_ack_mgr_newest_freed_tsn_cry[5]), + .DI(com_tlm_u_tlm_tx_ack_mgr_GND_2268), + .LO(com_tlm_u_tlm_tx_ack_mgr_newest_freed_tsn_cry[6]), + .S(com_tlm_u_tlm_tx_ack_mgr_newest_freed_tsn_qxu[6]) + ); + XORCY com_tlm_u_tlm_tx_ack_mgr_newest_freed_tsn_s_6_ ( + .CI(com_tlm_u_tlm_tx_ack_mgr_newest_freed_tsn_cry[5]), + .LI(com_tlm_u_tlm_tx_ack_mgr_newest_freed_tsn_qxu[6]), + .O(com_tlm_u_tlm_tx_ack_mgr_newest_freed_tsn_s[6]) + ); + FDSE com_tlm_u_tlm_tx_ack_mgr_newest_freed_tsn_6_ ( + .CE(com_tlm_u_tlm_tx_N_38179_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_ack_mgr_newest_freed_tsn_s[6]), + .Q(com_tlm_u_tlm_tx_ack_mgr_newest_freed_tsn[6]), + .S(plm_link_up_i) + ); + MUXCY_L com_tlm_u_tlm_tx_ack_mgr_newest_freed_tsn_cry_7_ ( + .CI(com_tlm_u_tlm_tx_ack_mgr_newest_freed_tsn_cry[6]), + .DI(com_tlm_u_tlm_tx_ack_mgr_GND_2268), + .LO(com_tlm_u_tlm_tx_ack_mgr_newest_freed_tsn_cry[7]), + .S(com_tlm_u_tlm_tx_ack_mgr_newest_freed_tsn_qxu[7]) + ); + XORCY com_tlm_u_tlm_tx_ack_mgr_newest_freed_tsn_s_7_ ( + .CI(com_tlm_u_tlm_tx_ack_mgr_newest_freed_tsn_cry[6]), + .LI(com_tlm_u_tlm_tx_ack_mgr_newest_freed_tsn_qxu[7]), + .O(com_tlm_u_tlm_tx_ack_mgr_newest_freed_tsn_s[7]) + ); + FDSE com_tlm_u_tlm_tx_ack_mgr_newest_freed_tsn_7_ ( + .CE(com_tlm_u_tlm_tx_N_38179_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_ack_mgr_newest_freed_tsn_s[7]), + .Q(com_tlm_u_tlm_tx_ack_mgr_newest_freed_tsn[7]), + .S(plm_link_up_i) + ); + MUXCY_L com_tlm_u_tlm_tx_ack_mgr_newest_freed_tsn_cry_8_ ( + .CI(com_tlm_u_tlm_tx_ack_mgr_newest_freed_tsn_cry[7]), + .DI(com_tlm_u_tlm_tx_ack_mgr_GND_2268), + .LO(com_tlm_u_tlm_tx_ack_mgr_newest_freed_tsn_cry[8]), + .S(com_tlm_u_tlm_tx_ack_mgr_newest_freed_tsn_qxu[8]) + ); + XORCY com_tlm_u_tlm_tx_ack_mgr_newest_freed_tsn_s_8_ ( + .CI(com_tlm_u_tlm_tx_ack_mgr_newest_freed_tsn_cry[7]), + .LI(com_tlm_u_tlm_tx_ack_mgr_newest_freed_tsn_qxu[8]), + .O(com_tlm_u_tlm_tx_ack_mgr_newest_freed_tsn_s[8]) + ); + FDSE com_tlm_u_tlm_tx_ack_mgr_newest_freed_tsn_8_ ( + .CE(com_tlm_u_tlm_tx_N_38179_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_ack_mgr_newest_freed_tsn_s[8]), + .Q(com_tlm_u_tlm_tx_ack_mgr_newest_freed_tsn[8]), + .S(plm_link_up_i) + ); + MUXCY_L com_tlm_u_tlm_tx_ack_mgr_newest_freed_tsn_cry_9_ ( + .CI(com_tlm_u_tlm_tx_ack_mgr_newest_freed_tsn_cry[8]), + .DI(com_tlm_u_tlm_tx_ack_mgr_GND_2268), + .LO(com_tlm_u_tlm_tx_ack_mgr_newest_freed_tsn_cry[9]), + .S(com_tlm_u_tlm_tx_ack_mgr_newest_freed_tsn_qxu[9]) + ); + XORCY com_tlm_u_tlm_tx_ack_mgr_newest_freed_tsn_s_9_ ( + .CI(com_tlm_u_tlm_tx_ack_mgr_newest_freed_tsn_cry[8]), + .LI(com_tlm_u_tlm_tx_ack_mgr_newest_freed_tsn_qxu[9]), + .O(com_tlm_u_tlm_tx_ack_mgr_newest_freed_tsn_s[9]) + ); + FDSE com_tlm_u_tlm_tx_ack_mgr_newest_freed_tsn_9_ ( + .CE(com_tlm_u_tlm_tx_N_38179_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_ack_mgr_newest_freed_tsn_s[9]), + .Q(com_tlm_u_tlm_tx_ack_mgr_newest_freed_tsn[9]), + .S(plm_link_up_i) + ); + MUXCY_L com_tlm_u_tlm_tx_ack_mgr_newest_freed_tsn_cry_10_ ( + .CI(com_tlm_u_tlm_tx_ack_mgr_newest_freed_tsn_cry[9]), + .DI(com_tlm_u_tlm_tx_ack_mgr_GND_2268), + .LO(com_tlm_u_tlm_tx_ack_mgr_newest_freed_tsn_cry[10]), + .S(com_tlm_u_tlm_tx_ack_mgr_newest_freed_tsn_qxu[10]) + ); + XORCY com_tlm_u_tlm_tx_ack_mgr_newest_freed_tsn_s_10_ ( + .CI(com_tlm_u_tlm_tx_ack_mgr_newest_freed_tsn_cry[9]), + .LI(com_tlm_u_tlm_tx_ack_mgr_newest_freed_tsn_qxu[10]), + .O(com_tlm_u_tlm_tx_ack_mgr_newest_freed_tsn_s[10]) + ); + FDSE com_tlm_u_tlm_tx_ack_mgr_newest_freed_tsn_10_ ( + .CE(com_tlm_u_tlm_tx_N_38179_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_ack_mgr_newest_freed_tsn_s[10]), + .Q(com_tlm_u_tlm_tx_ack_mgr_newest_freed_tsn[10]), + .S(plm_link_up_i) + ); + XORCY com_tlm_u_tlm_tx_ack_mgr_newest_freed_tsn_s_11_ ( + .CI(com_tlm_u_tlm_tx_ack_mgr_newest_freed_tsn_cry[10]), + .LI(com_tlm_u_tlm_tx_ack_mgr_newest_freed_tsn_qxu[11]), + .O(com_tlm_u_tlm_tx_ack_mgr_newest_freed_tsn_s[11]) + ); + FDSE com_tlm_u_tlm_tx_ack_mgr_newest_freed_tsn_11_ ( + .CE(com_tlm_u_tlm_tx_N_38179_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_ack_mgr_newest_freed_tsn_s[11]), + .Q(com_tlm_u_tlm_tx_ack_mgr_newest_freed_tsn[11]), + .S(plm_link_up_i) + ); + FDR com_tlm_u_tlm_tx_ack_mgr_mgr_state_12_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_ack_mgr_mgr_statec_4_i), + .Q(com_tlm_u_tlm_tx_ack_mgr_mgr_state_12__2231), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_tx_ack_mgr_mgr_state_11_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_ack_mgr_mgr_statec_3_i), + .Q(com_tlm_u_tlm_tx_ack_mgr_mgr_state_11__2248), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_tx_ack_mgr_mgr_state_10_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_ack_mgr_mgr_statec_2_i), + .Q(com_tlm_u_tlm_tx_ack_mgr_mgr_state_10__2235), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_tx_ack_mgr_mgr_state_9_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_ack_mgr_mgr_statec_1_i), + .Q(com_tlm_u_tlm_tx_ack_mgr_mgr_state_9__2233), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_tx_ack_mgr_mgr_state_7_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_ack_mgr_mgr_statec_0_i), + .Q(com_tlm_u_tlm_tx_ack_mgr_mgr_state_7__2266), + .R(plm_link_up_i) + ); + defparam com_tlm_u_tlm_tx_ack_mgr_un1_lnk_rupdate_ack_i_0_a3_0_a2_0_a4.INIT = 4'h2; + LUT2 com_tlm_u_tlm_tx_ack_mgr_un1_lnk_rupdate_ack_i_0_a3_0_a2_0_a4 ( + .I0(com_reg_tx_update_ack), + .I1(com_tlm_u_tlm_tx_am_retry_lock), + .O(com_tlm_u_tlm_tx_ack_mgr_un1_lnk_rupdate_ack_i_0_a3_0_a2_0_a4_2228) + ); + defparam com_tlm_u_tlm_tx_ack_mgr_un1_lnk_rupdate_ack_i_1_i_0_0_o4_0.INIT = 4'h4; + LUT2 com_tlm_u_tlm_tx_ack_mgr_un1_lnk_rupdate_ack_i_1_i_0_0_o4_0 ( + .I0(com_tlm_u_tlm_tx_am_retry_dst_rdy), + .I1(com_tlm_u_tlm_tx_am_retry_src_rdy), + .O(com_tlm_u_tlm_tx_ack_mgr_N_38199_i) + ); + defparam com_tlm_u_tlm_tx_ack_mgr_mgr_state_4_i_0_0_o3_0_7_.INIT = 4'h8; + LUT2 com_tlm_u_tlm_tx_ack_mgr_mgr_state_4_i_0_0_o3_0_7_ ( + .I0(com_tlm_u_tlm_tx_ack_mgr_nak_req_2229), + .I1(com_tlm_u_tlm_tx_ack_mgr_un1_frees_pending), + .O(com_tlm_u_tlm_tx_ack_mgr_N_38242_i) + ); + defparam com_tlm_u_tlm_tx_ack_mgr_mgr_state_4_i_0_0_o3_10_.INIT = 4'h1; + LUT2 com_tlm_u_tlm_tx_ack_mgr_mgr_state_4_i_0_0_o3_10_ ( + .I0(com_tlm_u_tlm_tx_ack_mgr_mgr_state_8__2282), + .I1(com_tlm_u_tlm_tx_ack_mgr_mgr_state_10__2235), + .O(com_tlm_u_tlm_tx_ack_mgr_N_38191_i) + ); + defparam com_tlm_u_tlm_tx_ack_mgr_mgr_state_4_iv_0_0_o3_0_0_.INIT = 4'h1; + LUT2 com_tlm_u_tlm_tx_ack_mgr_mgr_state_4_iv_0_0_o3_0_0_ ( + .I0(com_tlm_u_tlm_tx_ack_mgr_mgr_state_0__2287), + .I1(com_tlm_u_tlm_tx_ack_mgr_mgr_state_12__2231), + .O(com_tlm_u_tlm_tx_ack_mgr_N_38186_i) + ); + defparam com_tlm_u_tlm_tx_ack_mgr_un1_nxt_mgr_state_i_0_0_o3_1.INIT = 4'h8; + LUT2 com_tlm_u_tlm_tx_ack_mgr_un1_nxt_mgr_state_i_0_0_o3_1 ( + .I0(com_tlm_u_tlm_tx_ack_mgr_mgr_state_7__2266), + .I1(com_tlm_u_tlm_tx_ack_mgr_un1_skips_pending), + .O(com_tlm_u_tlm_tx_ack_mgr_N_38146_i) + ); + defparam com_tlm_u_tlm_tx_ack_mgr_mgr_state_4_i_0_0_o3_7_.INIT = 4'h2; + LUT2 com_tlm_u_tlm_tx_ack_mgr_mgr_state_4_i_0_0_o3_7_ ( + .I0(com_tlm_u_tlm_tx_ack_mgr_mgr_state_7__2266), + .I1(com_tlm_u_tlm_tx_ack_mgr_un1_skips_pending), + .O(com_tlm_u_tlm_tx_ack_mgr_N_38101_i) + ); + defparam com_tlm_u_tlm_tx_ack_mgr_N_11776_i_i_o2_i_o3.INIT = 8'h01; + LUT3 com_tlm_u_tlm_tx_ack_mgr_N_11776_i_i_o2_i_o3 ( + .I0(com_tlm_u_tlm_tx_ack_mgr_mgr_state_0__2287), + .I1(com_tlm_u_tlm_tx_ack_mgr_mgr_state_2__2286), + .I2(com_tlm_u_tlm_tx_ack_mgr_mgr_state_4__2284), + .O(com_tlm_u_tlm_tx_ack_mgr_N_38168_i) + ); + defparam com_tlm_u_tlm_tx_ack_mgr_un1_nxt_mgr_state_i_0_0_o3_0.INIT = 16'h0040; + LUT4 com_tlm_u_tlm_tx_ack_mgr_un1_nxt_mgr_state_i_0_0_o3_0 ( + .I0(com_tlm_u_tlm_tx_ack_mgr_fifo_nxt_vld), + .I1(com_tlm_u_tlm_tx_ack_mgr_mgr_state_8__2282), + .I2(com_tlm_u_tlm_tx_am_retry_dst_rdy), + .I3(com_tlm_u_tlm_tx_ds_buf_src_rdy), + .O(com_tlm_u_tlm_tx_ack_mgr_N_38366_i) + ); + defparam com_tlm_u_tlm_tx_ack_mgr_mgr_state_4_iv_0_0_a4_0_0_0_.INIT = 8'h8A; + LUT3 com_tlm_u_tlm_tx_ack_mgr_mgr_state_4_iv_0_0_a4_0_0_0_ ( + .I0(com_tlm_u_tlm_tx_ack_mgr_N_38186_i), + .I1(com_tlm_u_tlm_tx_ack_mgr_nak_req_2229), + .I2(com_tlm_u_tlm_tx_ack_mgr_un1_frees_pending), + .O(com_tlm_u_tlm_tx_ack_mgr_mgr_state_4_iv_0_0_a4_0[0]) + ); + defparam com_tlm_u_tlm_tx_ack_mgr_mgr_state_4_0_0_0_a4_0_0_8_.INIT = 8'h8C; + LUT3 com_tlm_u_tlm_tx_ack_mgr_mgr_state_4_0_0_0_a4_0_0_8_ ( + .I0(com_tlm_u_tlm_tx_ack_mgr_fifo_nxt_vld), + .I1(com_tlm_u_tlm_tx_ack_mgr_mgr_state_8__2282), + .I2(com_tlm_u_tlm_tx_am_retry_dst_rdy), + .O(com_tlm_u_tlm_tx_ack_mgr_mgr_state_4_0_0_0_a4_0_0[8]) + ); + defparam com_tlm_u_tlm_tx_ack_mgr_N_69068_i.INIT = 4'hE; + LUT2 com_tlm_u_tlm_tx_ack_mgr_N_69068_i ( + .I0(com_tlm_u_tlm_tx_ack_mgr_N_38140_i), + .I1(com_tlm_u_tlm_tx_ack_mgr_jump_retry_tsn_2290), + .O(com_tlm_u_tlm_tx_ack_mgr_N_69068_i_2230) + ); + defparam com_tlm_u_tlm_tx_ack_mgr_mgr_state_4_i_i_0_o3_4_.INIT = 4'h8; + LUT2 com_tlm_u_tlm_tx_ack_mgr_mgr_state_4_i_i_0_o3_4_ ( + .I0(com_tlm_u_tlm_tx_ack_mgr_N_9704_i_i), + .I1(com_tlm_u_tlm_tx_ack_mgr_un1_frees_pending), + .O(com_tlm_u_tlm_tx_ack_mgr_mgr_state_4_i_i_0_o3[4]) + ); + defparam com_tlm_u_tlm_tx_ack_mgr_mgr_statec_1_1.INIT = 4'h8; + LUT2 com_tlm_u_tlm_tx_ack_mgr_mgr_statec_1_1 ( + .I0(com_tlm_u_tlm_tx_ack_mgr_N_9704_i_i), + .I1(com_tlm_u_tlm_tx_ack_mgr_mgr_state_8__2282), + .O(com_tlm_u_tlm_tx_ack_mgr_mgr_statec_1_i_1) + ); + defparam com_tlm_u_tlm_tx_ack_mgr_mgr_state_4_i_0_0_a4_11_.INIT = 16'h0203; + LUT4_L com_tlm_u_tlm_tx_ack_mgr_mgr_state_4_i_0_0_a4_11_ ( + .I0(com_tlm_u_tlm_tx_ack_mgr_N_38191_i), + .I1(com_tlm_u_tlm_tx_ack_mgr_mgr_state_7__2266), + .I2(com_tlm_u_tlm_tx_ack_mgr_mgr_state_9__2233), + .I3(com_tlm_u_tlm_tx_am_retry_dst_rdy), + .LO(com_tlm_u_tlm_tx_ack_mgr_N_38426) + ); + defparam com_tlm_u_tlm_tx_ack_mgr_mgr_state_4_iv_0_0_a4_1_0_0_.INIT = 4'h2; + LUT2 com_tlm_u_tlm_tx_ack_mgr_mgr_state_4_iv_0_0_a4_1_0_0_ ( + .I0(com_tlm_u_tlm_tx_ack_mgr_N_38168_i), + .I1(com_tlm_u_tlm_tx_ack_mgr_mgr_state_12__2231), + .O(com_tlm_u_tlm_tx_ack_mgr_mgr_state_4_iv_0_0_a4_1_0[0]) + ); + defparam com_tlm_u_tlm_tx_ack_mgr_N_69235_i.INIT = 4'h7; + LUT2 com_tlm_u_tlm_tx_ack_mgr_N_69235_i ( + .I0(com_tlm_u_tlm_tx_ack_mgr_N_9704_i_i), + .I1(com_tlm_u_tlm_tx_ack_mgr_N_38199_i), + .O(com_tlm_u_tlm_tx_ack_mgr_N_69235_i_2232) + ); + defparam com_tlm_u_tlm_tx_ack_mgr_mgr_state_4_iv_0_i_0_a4_2_.INIT = 16'h5100; + LUT4_L com_tlm_u_tlm_tx_ack_mgr_mgr_state_4_iv_0_i_0_a4_2_ ( + .I0(com_tlm_u_tlm_tx_ack_mgr_N_9704_i_i), + .I1(com_tlm_u_tlm_tx_ack_mgr_N_38186_i), + .I2(com_tlm_u_tlm_tx_ack_mgr_mgr_state_2__2286), + .I3(plm_link_up_1), + .LO(com_tlm_u_tlm_tx_ack_mgr_N_38742) + ); + defparam com_tlm_u_tlm_tx_ack_mgr_mgr_state_4_0_0_0_o3_0_8_.INIT = 16'h0013; + LUT4 com_tlm_u_tlm_tx_ack_mgr_mgr_state_4_0_0_0_o3_0_8_ ( + .I0(com_tlm_u_tlm_tx_ack_mgr_N_38242_i), + .I1(com_tlm_u_tlm_tx_ack_mgr_N_39057), + .I2(com_tlm_u_tlm_tx_ack_mgr_mgr_state_2__2286), + .I3(com_tlm_u_tlm_tx_ack_mgr_mgr_state_9__2233), + .O(com_tlm_u_tlm_tx_ack_mgr_mgr_state_4_0_0_0_o3_0[8]) + ); + defparam com_tlm_u_tlm_tx_ack_mgr_N_69140_i.INIT = 16'hA0A8; + LUT4 com_tlm_u_tlm_tx_ack_mgr_N_69140_i ( + .I0(com_tlm_u_tlm_tx_ack_mgr_N_9704_i_i), + .I1(com_tlm_u_tlm_tx_ack_mgr_N_38146_i), + .I2(com_tlm_u_tlm_tx_ack_mgr_N_38366_i), + .I3(com_tlm_u_tlm_tx_ack_mgr_fifo_vld), + .O(com_tlm_u_tlm_tx_ack_mgr_N_69140_i_2234) + ); + defparam com_tlm_u_tlm_tx_ack_mgr_un1_fifo_ren_iv_0_a2_0_a4_0_.INIT = 16'hDF00; + LUT4 com_tlm_u_tlm_tx_ack_mgr_un1_fifo_ren_iv_0_a2_0_a4_0_ ( + .I0(com_tlm_u_tlm_tx_ack_mgr_N_38092_i), + .I1(com_tlm_u_tlm_tx_ack_mgr_N_38101_i), + .I2(com_tlm_u_tlm_tx_ack_mgr_N_38388_2), + .I3(plm_link_up_1), + .O(com_tlm_u_tlm_tx_ack_mgr_un1_fifo_ren_iv_0_a2_0_a4[0]) + ); + defparam com_tlm_u_tlm_tx_ack_mgr_retry_src_rdy_o_3_i_0_0_0.INIT = 16'h3F2A; + LUT4 com_tlm_u_tlm_tx_ack_mgr_retry_src_rdy_o_3_i_0_0_0 ( + .I0(com_tlm_u_tlm_tx_ack_mgr_N_38191_i), + .I1(com_tlm_u_tlm_tx_ack_mgr_fifo_nxt_vld), + .I2(com_tlm_u_tlm_tx_ack_mgr_mgr_statec_1_i_1), + .I3(com_tlm_u_tlm_tx_am_retry_dst_rdy), + .O(com_tlm_u_tlm_tx_ack_mgr_retry_src_rdy_o_3_i_0_0_0_2263) + ); + defparam com_tlm_u_tlm_tx_ack_mgr_mgr_statec_0.INIT = 16'hA888; + LUT4_L com_tlm_u_tlm_tx_ack_mgr_mgr_statec_0 ( + .I0(com_tlm_u_tlm_tx_ack_mgr_N_9704_i_i), + .I1(com_tlm_u_tlm_tx_ack_mgr_N_38101_i), + .I2(com_tlm_u_tlm_tx_ack_mgr_N_38242_i), + .I3(com_tlm_u_tlm_tx_ack_mgr_mgr_state_4__2284), + .LO(com_tlm_u_tlm_tx_ack_mgr_mgr_statec_0_i) + ); + defparam com_tlm_u_tlm_tx_ack_mgr_mgr_statec_1.INIT = 16'h4000; + LUT4_L com_tlm_u_tlm_tx_ack_mgr_mgr_statec_1 ( + .I0(com_tlm_u_tlm_tx_ack_mgr_fifo_nxt_vld), + .I1(com_tlm_u_tlm_tx_ack_mgr_mgr_statec_1_i_1), + .I2(com_tlm_u_tlm_tx_am_retry_dst_rdy), + .I3(com_tlm_u_tlm_tx_ds_buf_src_rdy), + .LO(com_tlm_u_tlm_tx_ack_mgr_mgr_statec_1_i) + ); + defparam com_tlm_u_tlm_tx_ack_mgr_mgr_statec_2.INIT = 16'h00F4; + LUT4_L com_tlm_u_tlm_tx_ack_mgr_mgr_statec_2 ( + .I0(com_tlm_u_tlm_tx_ack_mgr_N_9704_i_i), + .I1(com_tlm_u_tlm_tx_ack_mgr_mgr_state_8__2282), + .I2(com_tlm_u_tlm_tx_ack_mgr_mgr_state_10__2235), + .I3(com_tlm_u_tlm_tx_am_retry_dst_rdy), + .LO(com_tlm_u_tlm_tx_ack_mgr_mgr_statec_2_i) + ); + defparam com_tlm_u_tlm_tx_ack_mgr_mgr_statec_3.INIT = 8'h31; + LUT3_L com_tlm_u_tlm_tx_ack_mgr_mgr_statec_3 ( + .I0(com_tlm_u_tlm_tx_ack_mgr_N_9704_i_i), + .I1(com_tlm_u_tlm_tx_ack_mgr_N_38426), + .I2(com_tlm_u_tlm_tx_ack_mgr_mgr_state_10__2235), + .LO(com_tlm_u_tlm_tx_ack_mgr_mgr_statec_3_i) + ); + defparam com_tlm_u_tlm_tx_ack_mgr_mgr_statec_4.INIT = 16'hA0A8; + LUT4_L com_tlm_u_tlm_tx_ack_mgr_mgr_statec_4 ( + .I0(com_tlm_u_tlm_tx_ack_mgr_N_9704_i_i), + .I1(com_tlm_u_tlm_tx_ack_mgr_N_38146_i), + .I2(com_tlm_u_tlm_tx_ack_mgr_N_38366_i), + .I3(com_tlm_u_tlm_tx_ack_mgr_fifo_vld), + .LO(com_tlm_u_tlm_tx_ack_mgr_mgr_statec_4_i) + ); + defparam com_tlm_u_tlm_tx_ack_mgr_un1_oldest_tsn_1_axb_11.INIT = 16'hD800; + LUT4_L com_tlm_u_tlm_tx_ack_mgr_un1_oldest_tsn_1_axb_11 ( + .I0(com_tlm_u_tlm_tx_ack_mgr_N_38092_i), + .I1(com_tlm_u_tlm_tx_ack_mgr_fifo_tsn[11]), + .I2(com_tlm_u_tlm_tx_ack_mgr_newest_freed_tsn[11]), + .I3(plm_link_up_2), + .LO(com_tlm_u_tlm_tx_ack_mgr_un1_oldest_tsn_1_axb_11_2236) + ); + defparam com_tlm_u_tlm_tx_ack_mgr_un1_oldest_tsn_1_axb_10.INIT = 16'hD800; + LUT4_L com_tlm_u_tlm_tx_ack_mgr_un1_oldest_tsn_1_axb_10 ( + .I0(com_tlm_u_tlm_tx_ack_mgr_N_38092_i), + .I1(com_tlm_u_tlm_tx_ack_mgr_fifo_tsn[10]), + .I2(com_tlm_u_tlm_tx_ack_mgr_newest_freed_tsn[10]), + .I3(plm_link_up_2), + .LO(com_tlm_u_tlm_tx_ack_mgr_un1_oldest_tsn_1_axb_10_2237) + ); + defparam com_tlm_u_tlm_tx_ack_mgr_un1_oldest_tsn_1_axb_9.INIT = 16'hD800; + LUT4_L com_tlm_u_tlm_tx_ack_mgr_un1_oldest_tsn_1_axb_9 ( + .I0(com_tlm_u_tlm_tx_ack_mgr_N_38092_i), + .I1(com_tlm_u_tlm_tx_ack_mgr_fifo_tsn[9]), + .I2(com_tlm_u_tlm_tx_ack_mgr_newest_freed_tsn[9]), + .I3(plm_link_up_2), + .LO(com_tlm_u_tlm_tx_ack_mgr_un1_oldest_tsn_1_axb_9_2238) + ); + defparam com_tlm_u_tlm_tx_ack_mgr_un1_oldest_tsn_1_axb_8.INIT = 16'hD800; + LUT4_L com_tlm_u_tlm_tx_ack_mgr_un1_oldest_tsn_1_axb_8 ( + .I0(com_tlm_u_tlm_tx_ack_mgr_N_38092_i), + .I1(com_tlm_u_tlm_tx_ack_mgr_fifo_tsn[8]), + .I2(com_tlm_u_tlm_tx_ack_mgr_newest_freed_tsn[8]), + .I3(plm_link_up_2), + .LO(com_tlm_u_tlm_tx_ack_mgr_un1_oldest_tsn_1_axb_8_2239) + ); + defparam com_tlm_u_tlm_tx_ack_mgr_un1_oldest_tsn_1_axb_7.INIT = 16'hD800; + LUT4_L com_tlm_u_tlm_tx_ack_mgr_un1_oldest_tsn_1_axb_7 ( + .I0(com_tlm_u_tlm_tx_ack_mgr_N_38092_i), + .I1(com_tlm_u_tlm_tx_ack_mgr_fifo_tsn[7]), + .I2(com_tlm_u_tlm_tx_ack_mgr_newest_freed_tsn[7]), + .I3(plm_link_up_2), + .LO(com_tlm_u_tlm_tx_ack_mgr_un1_oldest_tsn_1_axb_7_2240) + ); + defparam com_tlm_u_tlm_tx_ack_mgr_un1_oldest_tsn_1_axb_6.INIT = 16'hD800; + LUT4_L com_tlm_u_tlm_tx_ack_mgr_un1_oldest_tsn_1_axb_6 ( + .I0(com_tlm_u_tlm_tx_ack_mgr_N_38092_i), + .I1(com_tlm_u_tlm_tx_ack_mgr_fifo_tsn[6]), + .I2(com_tlm_u_tlm_tx_ack_mgr_newest_freed_tsn[6]), + .I3(plm_link_up_2), + .LO(com_tlm_u_tlm_tx_ack_mgr_un1_oldest_tsn_1_axb_6_2241) + ); + defparam com_tlm_u_tlm_tx_ack_mgr_un1_oldest_tsn_1_axb_5.INIT = 16'hD800; + LUT4_L com_tlm_u_tlm_tx_ack_mgr_un1_oldest_tsn_1_axb_5 ( + .I0(com_tlm_u_tlm_tx_ack_mgr_N_38092_i), + .I1(com_tlm_u_tlm_tx_ack_mgr_fifo_tsn[5]), + .I2(com_tlm_u_tlm_tx_ack_mgr_newest_freed_tsn[5]), + .I3(plm_link_up_2), + .LO(com_tlm_u_tlm_tx_ack_mgr_un1_oldest_tsn_1_axb_5_2242) + ); + defparam com_tlm_u_tlm_tx_ack_mgr_un1_oldest_tsn_1_axb_4.INIT = 16'hD800; + LUT4_L com_tlm_u_tlm_tx_ack_mgr_un1_oldest_tsn_1_axb_4 ( + .I0(com_tlm_u_tlm_tx_ack_mgr_N_38092_i), + .I1(com_tlm_u_tlm_tx_ack_mgr_fifo_tsn[4]), + .I2(com_tlm_u_tlm_tx_ack_mgr_newest_freed_tsn[4]), + .I3(plm_link_up_2), + .LO(com_tlm_u_tlm_tx_ack_mgr_un1_oldest_tsn_1_axb_4_2243) + ); + defparam com_tlm_u_tlm_tx_ack_mgr_un1_oldest_tsn_1_axb_3.INIT = 16'hD800; + LUT4_L com_tlm_u_tlm_tx_ack_mgr_un1_oldest_tsn_1_axb_3 ( + .I0(com_tlm_u_tlm_tx_ack_mgr_N_38092_i), + .I1(com_tlm_u_tlm_tx_ack_mgr_fifo_tsn[3]), + .I2(com_tlm_u_tlm_tx_ack_mgr_newest_freed_tsn[3]), + .I3(plm_link_up_2), + .LO(com_tlm_u_tlm_tx_ack_mgr_un1_oldest_tsn_1_axb_3_2244) + ); + defparam com_tlm_u_tlm_tx_ack_mgr_un1_oldest_tsn_1_axb_2.INIT = 16'hD800; + LUT4_L com_tlm_u_tlm_tx_ack_mgr_un1_oldest_tsn_1_axb_2 ( + .I0(com_tlm_u_tlm_tx_ack_mgr_N_38092_i), + .I1(com_tlm_u_tlm_tx_ack_mgr_fifo_tsn[2]), + .I2(com_tlm_u_tlm_tx_ack_mgr_newest_freed_tsn[2]), + .I3(plm_link_up_2), + .LO(com_tlm_u_tlm_tx_ack_mgr_un1_oldest_tsn_1_axb_2_2245) + ); + defparam com_tlm_u_tlm_tx_ack_mgr_un1_oldest_tsn_1_axb_1.INIT = 16'hD800; + LUT4_L com_tlm_u_tlm_tx_ack_mgr_un1_oldest_tsn_1_axb_1 ( + .I0(com_tlm_u_tlm_tx_ack_mgr_N_38092_i), + .I1(com_tlm_u_tlm_tx_ack_mgr_fifo_tsn[1]), + .I2(com_tlm_u_tlm_tx_ack_mgr_newest_freed_tsn[1]), + .I3(plm_link_up_2), + .LO(com_tlm_u_tlm_tx_ack_mgr_un1_oldest_tsn_1_axb_1_2246) + ); + defparam com_tlm_u_tlm_tx_ack_mgr_un1_oldest_tsn_1_axb_0.INIT = 16'hD800; + LUT4_L com_tlm_u_tlm_tx_ack_mgr_un1_oldest_tsn_1_axb_0 ( + .I0(com_tlm_u_tlm_tx_ack_mgr_N_38092_i), + .I1(com_tlm_u_tlm_tx_ack_mgr_fifo_tsn[0]), + .I2(com_tlm_u_tlm_tx_ack_mgr_newest_freed_tsn[0]), + .I3(plm_link_up_2), + .LO(com_tlm_u_tlm_tx_ack_mgr_un1_oldest_tsn_1_axb_0_2247) + ); + defparam com_tlm_u_tlm_tx_ack_mgr_N_69061_i.INIT = 16'hA200; + LUT4_L com_tlm_u_tlm_tx_ack_mgr_N_69061_i ( + .I0(com_tlm_u_tlm_tx_ack_mgr_N_9704_i_i), + .I1(com_tlm_u_tlm_tx_ack_mgr_mgr_state_4_0_0_0_o3_0[8]), + .I2(com_tlm_u_tlm_tx_ack_mgr_mgr_state_4_0_0_0_a4_0_0[8]), + .I3(plm_link_up_2), + .LO(com_tlm_u_tlm_tx_ack_mgr_N_69061_i_2281) + ); + defparam com_tlm_u_tlm_tx_ack_mgr_N_68235_i.INIT = 16'hF400; + LUT4_L com_tlm_u_tlm_tx_ack_mgr_N_68235_i ( + .I0(com_tlm_u_tlm_tx_ack_mgr_mgr_state_4_i_i_0_o3[4]), + .I1(com_tlm_u_tlm_tx_ack_mgr_mgr_state_4__2284), + .I2(com_tlm_u_tlm_tx_ack_mgr_mgr_state_11__2248), + .I3(plm_link_up_2), + .LO(com_tlm_u_tlm_tx_ack_mgr_N_68235_i_2283) + ); + defparam com_tlm_u_tlm_tx_ack_mgr_N_69138_i.INIT = 16'hAEAA; + LUT4_L com_tlm_u_tlm_tx_ack_mgr_N_69138_i ( + .I0(com_tlm_u_tlm_tx_ack_mgr_N_38742), + .I1(com_tlm_u_tlm_tx_ack_mgr_mgr_state_2__2286), + .I2(com_tlm_u_tlm_tx_ack_mgr_un1_frees_pending), + .I3(plm_link_up_2), + .LO(com_tlm_u_tlm_tx_ack_mgr_N_69138_i_2285) + ); + defparam com_tlm_u_tlm_tx_ack_mgr_mgr_state_4_iv_0_0_0_.INIT = 16'h02FF; + LUT4_L com_tlm_u_tlm_tx_ack_mgr_mgr_state_4_iv_0_0_0_ ( + .I0(com_tlm_u_tlm_tx_ack_mgr_N_9704_i_i), + .I1(com_tlm_u_tlm_tx_ack_mgr_mgr_state_4_iv_0_0_a4_0[0]), + .I2(com_tlm_u_tlm_tx_ack_mgr_mgr_state_4_iv_0_0_a4_1_0[0]), + .I3(plm_link_up_2), + .LO(com_tlm_u_tlm_tx_ack_mgr_N_8638_i) + ); + defparam com_tlm_u_tlm_tx_ack_mgr_N_38757_i.INIT = 4'hE; + LUT2_L com_tlm_u_tlm_tx_ack_mgr_N_38757_i ( + .I0(com_tlm_u_tlm_tx_ack_mgr_fifo_nxt_vld), + .I1(com_tlm_u_tlm_tx_ack_mgr_fifo_vld), + .LO(com_tlm_u_tlm_tx_ack_mgr_N_38757_i_2249) + ); + defparam com_tlm_u_tlm_tx_ack_mgr_nak_in_retry19_0_a3_0_a2_0_a4.INIT = 4'h8; + LUT2_L com_tlm_u_tlm_tx_ack_mgr_nak_in_retry19_0_a3_0_a2_0_a4 ( + .I0(com_N_38093_i), + .I1(com_tlm_u_tlm_tx_ack_mgr_N_38199_i), + .LO(com_tlm_u_tlm_tx_ack_mgr_nak_in_retry19) + ); + defparam com_tlm_u_tlm_tx_ack_mgr_un4_retry_tsn_o_axb_11.INIT = 8'hD8; + LUT3_L com_tlm_u_tlm_tx_ack_mgr_un4_retry_tsn_o_axb_11 ( + .I0(com_tlm_u_tlm_tx_ack_mgr_jump_retry_tsn_2290), + .I1(com_tlm_u_tlm_tx_ack_mgr_lnk_rupdate_seq_q[11]), + .I2(com_tlm_u_tlm_tx_am_retry_tsn[11]), + .LO(com_tlm_u_tlm_tx_ack_mgr_un4_retry_tsn_o_axb_11_2250) + ); + defparam com_tlm_u_tlm_tx_ack_mgr_un4_retry_tsn_o_axb_10.INIT = 8'hD8; + LUT3_L com_tlm_u_tlm_tx_ack_mgr_un4_retry_tsn_o_axb_10 ( + .I0(com_tlm_u_tlm_tx_ack_mgr_jump_retry_tsn_2290), + .I1(com_tlm_u_tlm_tx_ack_mgr_lnk_rupdate_seq_q[10]), + .I2(com_tlm_u_tlm_tx_am_retry_tsn[10]), + .LO(com_tlm_u_tlm_tx_ack_mgr_un4_retry_tsn_o_axb_10_2251) + ); + defparam com_tlm_u_tlm_tx_ack_mgr_un4_retry_tsn_o_axb_9.INIT = 8'hD8; + LUT3_L com_tlm_u_tlm_tx_ack_mgr_un4_retry_tsn_o_axb_9 ( + .I0(com_tlm_u_tlm_tx_ack_mgr_jump_retry_tsn_2290), + .I1(com_tlm_u_tlm_tx_ack_mgr_lnk_rupdate_seq_q[9]), + .I2(com_tlm_u_tlm_tx_am_retry_tsn[9]), + .LO(com_tlm_u_tlm_tx_ack_mgr_un4_retry_tsn_o_axb_9_2252) + ); + defparam com_tlm_u_tlm_tx_ack_mgr_un4_retry_tsn_o_axb_8.INIT = 8'hD8; + LUT3_L com_tlm_u_tlm_tx_ack_mgr_un4_retry_tsn_o_axb_8 ( + .I0(com_tlm_u_tlm_tx_ack_mgr_jump_retry_tsn_2290), + .I1(com_tlm_u_tlm_tx_ack_mgr_lnk_rupdate_seq_q[8]), + .I2(com_tlm_u_tlm_tx_am_retry_tsn[8]), + .LO(com_tlm_u_tlm_tx_ack_mgr_un4_retry_tsn_o_axb_8_2253) + ); + defparam com_tlm_u_tlm_tx_ack_mgr_un4_retry_tsn_o_axb_7.INIT = 8'hD8; + LUT3_L com_tlm_u_tlm_tx_ack_mgr_un4_retry_tsn_o_axb_7 ( + .I0(com_tlm_u_tlm_tx_ack_mgr_jump_retry_tsn_2290), + .I1(com_tlm_u_tlm_tx_ack_mgr_lnk_rupdate_seq_q[7]), + .I2(com_tlm_u_tlm_tx_am_retry_tsn[7]), + .LO(com_tlm_u_tlm_tx_ack_mgr_un4_retry_tsn_o_axb_7_2254) + ); + defparam com_tlm_u_tlm_tx_ack_mgr_un4_retry_tsn_o_axb_6.INIT = 8'hD8; + LUT3_L com_tlm_u_tlm_tx_ack_mgr_un4_retry_tsn_o_axb_6 ( + .I0(com_tlm_u_tlm_tx_ack_mgr_jump_retry_tsn_2290), + .I1(com_tlm_u_tlm_tx_ack_mgr_lnk_rupdate_seq_q[6]), + .I2(com_tlm_u_tlm_tx_am_retry_tsn[6]), + .LO(com_tlm_u_tlm_tx_ack_mgr_un4_retry_tsn_o_axb_6_2255) + ); + defparam com_tlm_u_tlm_tx_ack_mgr_un4_retry_tsn_o_axb_5.INIT = 8'hD8; + LUT3_L com_tlm_u_tlm_tx_ack_mgr_un4_retry_tsn_o_axb_5 ( + .I0(com_tlm_u_tlm_tx_ack_mgr_jump_retry_tsn_2290), + .I1(com_tlm_u_tlm_tx_ack_mgr_lnk_rupdate_seq_q[5]), + .I2(com_tlm_u_tlm_tx_am_retry_tsn[5]), + .LO(com_tlm_u_tlm_tx_ack_mgr_un4_retry_tsn_o_axb_5_2256) + ); + defparam com_tlm_u_tlm_tx_ack_mgr_un4_retry_tsn_o_axb_4.INIT = 8'hD8; + LUT3_L com_tlm_u_tlm_tx_ack_mgr_un4_retry_tsn_o_axb_4 ( + .I0(com_tlm_u_tlm_tx_ack_mgr_jump_retry_tsn_2290), + .I1(com_tlm_u_tlm_tx_ack_mgr_lnk_rupdate_seq_q[4]), + .I2(com_tlm_u_tlm_tx_am_retry_tsn[4]), + .LO(com_tlm_u_tlm_tx_ack_mgr_un4_retry_tsn_o_axb_4_2257) + ); + defparam com_tlm_u_tlm_tx_ack_mgr_un4_retry_tsn_o_axb_3.INIT = 8'hD8; + LUT3_L com_tlm_u_tlm_tx_ack_mgr_un4_retry_tsn_o_axb_3 ( + .I0(com_tlm_u_tlm_tx_ack_mgr_jump_retry_tsn_2290), + .I1(com_tlm_u_tlm_tx_ack_mgr_lnk_rupdate_seq_q[3]), + .I2(com_tlm_u_tlm_tx_am_retry_tsn[3]), + .LO(com_tlm_u_tlm_tx_ack_mgr_un4_retry_tsn_o_axb_3_2258) + ); + defparam com_tlm_u_tlm_tx_ack_mgr_un4_retry_tsn_o_axb_2.INIT = 8'hD8; + LUT3_L com_tlm_u_tlm_tx_ack_mgr_un4_retry_tsn_o_axb_2 ( + .I0(com_tlm_u_tlm_tx_ack_mgr_jump_retry_tsn_2290), + .I1(com_tlm_u_tlm_tx_ack_mgr_lnk_rupdate_seq_q[2]), + .I2(com_tlm_u_tlm_tx_am_retry_tsn[2]), + .LO(com_tlm_u_tlm_tx_ack_mgr_un4_retry_tsn_o_axb_2_2259) + ); + defparam com_tlm_u_tlm_tx_ack_mgr_un4_retry_tsn_o_axb_1.INIT = 8'hD8; + LUT3_L com_tlm_u_tlm_tx_ack_mgr_un4_retry_tsn_o_axb_1 ( + .I0(com_tlm_u_tlm_tx_ack_mgr_jump_retry_tsn_2290), + .I1(com_tlm_u_tlm_tx_ack_mgr_lnk_rupdate_seq_q[1]), + .I2(com_tlm_u_tlm_tx_am_retry_tsn[1]), + .LO(com_tlm_u_tlm_tx_ack_mgr_un4_retry_tsn_o_axb_1_2260) + ); + defparam com_tlm_u_tlm_tx_ack_mgr_N_38266_i.INIT = 8'h27; + LUT3_L com_tlm_u_tlm_tx_ack_mgr_N_38266_i ( + .I0(com_tlm_u_tlm_tx_ack_mgr_jump_retry_tsn_2290), + .I1(com_tlm_u_tlm_tx_ack_mgr_lnk_rupdate_seq_q[0]), + .I2(com_tlm_u_tlm_tx_am_retry_tsn[0]), + .LO(com_tlm_u_tlm_tx_ack_mgr_N_38266_i_2261) + ); + defparam com_tlm_u_tlm_tx_ack_mgr_N_67879_i.INIT = 8'h2F; + LUT3_L com_tlm_u_tlm_tx_ack_mgr_N_67879_i ( + .I0(com_tlm_u_tlm_tx_ack_mgr_N_9704_i_i), + .I1(com_tlm_u_tlm_tx_ack_mgr_mgr_state_4_0_0_0_o3_0[8]), + .I2(com_tlm_u_tlm_tx_ack_mgr_retry_src_rdy_o_3_i_0_0_0_2263), + .LO(com_tlm_u_tlm_tx_ack_mgr_N_67879_i_2262) + ); + defparam com_tlm_u_tlm_tx_ack_mgr_N_69234_i.INIT = 16'hE0AA; + LUT4_L com_tlm_u_tlm_tx_ack_mgr_N_69234_i ( + .I0(com_N_38093_i), + .I1(com_tlm_u_tlm_tx_ack_mgr_nak_in_retry_2265), + .I2(com_tlm_u_tlm_tx_am_retry_dst_rdy), + .I3(com_tlm_u_tlm_tx_am_retry_src_rdy), + .LO(com_tlm_u_tlm_tx_ack_mgr_N_69234_i_2264) + ); + defparam com_tlm_u_tlm_tx_ack_mgr_mgr_state_4_0_0_0_a3_8_.INIT = 8'h80; + LUT3 com_tlm_u_tlm_tx_ack_mgr_mgr_state_4_0_0_0_a3_8_ ( + .I0(com_tlm_u_tlm_tx_ack_mgr_fifo_vld), + .I1(com_tlm_u_tlm_tx_ack_mgr_un1_skips_pending), + .I2(com_tlm_u_tlm_tx_ack_mgr_mgr_state_7__2266), + .O(com_tlm_u_tlm_tx_ack_mgr_N_39057) + ); + defparam com_tlm_u_tlm_tx_ack_mgr_mgr_state_4_i_i_0_o3_0_4_.INIT = 8'h45; + LUT3 com_tlm_u_tlm_tx_ack_mgr_mgr_state_4_i_i_0_o3_0_4_ ( + .I0(com_reg_tx_update_ack), + .I1(com_reg_tx_update_retry_q), + .I2(com_reg_tx_update_retry_int), + .O(com_tlm_u_tlm_tx_ack_mgr_N_9704_i_i) + ); + defparam com_tlm_u_tlm_tx_ack_mgr_N_9704_i_i_i.INIT = 8'hF2; + LUT3 com_tlm_u_tlm_tx_ack_mgr_N_9704_i_i_i ( + .I0(com_reg_tx_update_retry_int), + .I1(com_reg_tx_update_retry_q), + .I2(com_reg_tx_update_ack), + .O(com_tlm_u_tlm_tx_ack_mgr_N_9704_i_i_i_2267) + ); + MUXCY com_tlm_u_tlm_tx_ack_mgr_unreg_skips_pend_un1_skips_pending_0_I_19 ( + .CI(com_tlm_u_tlm_tx_ack_mgr_data_tmp_0[4]), + .DI(com_tlm_u_tlm_tx_ack_mgr_GND_2268), + .O(com_tlm_u_tlm_tx_ack_mgr_un1_skips_pending), + .S(com_tlm_u_tlm_tx_ack_mgr_N_27) + ); + MUXCY com_tlm_u_tlm_tx_ack_mgr_unreg_frees_pend_un1_frees_pending_0_I_19 ( + .CI(com_tlm_u_tlm_tx_ack_mgr_data_tmp[4]), + .DI(com_tlm_u_tlm_tx_ack_mgr_GND_2268), + .O(com_tlm_u_tlm_tx_ack_mgr_un1_frees_pending), + .S(com_tlm_u_tlm_tx_ack_mgr_N_27_0) + ); + FD com_tlm_u_tlm_tx_ack_mgr_fifo_tsn_11_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_ack_mgr_un1_oldest_tsn_1_s_11_2269), + .Q(com_tlm_u_tlm_tx_ack_mgr_fifo_tsn[11]) + ); + FD com_tlm_u_tlm_tx_ack_mgr_fifo_tsn_10_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_ack_mgr_un1_oldest_tsn_1_s_10_2270), + .Q(com_tlm_u_tlm_tx_ack_mgr_fifo_tsn[10]) + ); + FD com_tlm_u_tlm_tx_ack_mgr_fifo_tsn_9_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_ack_mgr_un1_oldest_tsn_1_s_9_2271), + .Q(com_tlm_u_tlm_tx_ack_mgr_fifo_tsn[9]) + ); + FD com_tlm_u_tlm_tx_ack_mgr_fifo_tsn_8_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_ack_mgr_un1_oldest_tsn_1_s_8_2272), + .Q(com_tlm_u_tlm_tx_ack_mgr_fifo_tsn[8]) + ); + FD com_tlm_u_tlm_tx_ack_mgr_fifo_tsn_7_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_ack_mgr_un1_oldest_tsn_1_s_7_2273), + .Q(com_tlm_u_tlm_tx_ack_mgr_fifo_tsn[7]) + ); + FD com_tlm_u_tlm_tx_ack_mgr_fifo_tsn_6_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_ack_mgr_un1_oldest_tsn_1_s_6_2274), + .Q(com_tlm_u_tlm_tx_ack_mgr_fifo_tsn[6]) + ); + FD com_tlm_u_tlm_tx_ack_mgr_fifo_tsn_5_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_ack_mgr_un1_oldest_tsn_1_s_5_2275), + .Q(com_tlm_u_tlm_tx_ack_mgr_fifo_tsn[5]) + ); + FD com_tlm_u_tlm_tx_ack_mgr_fifo_tsn_4_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_ack_mgr_un1_oldest_tsn_1_s_4_2276), + .Q(com_tlm_u_tlm_tx_ack_mgr_fifo_tsn[4]) + ); + FD com_tlm_u_tlm_tx_ack_mgr_fifo_tsn_3_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_ack_mgr_un1_oldest_tsn_1_s_3_2277), + .Q(com_tlm_u_tlm_tx_ack_mgr_fifo_tsn[3]) + ); + FD com_tlm_u_tlm_tx_ack_mgr_fifo_tsn_2_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_ack_mgr_un1_oldest_tsn_1_s_2_2278), + .Q(com_tlm_u_tlm_tx_ack_mgr_fifo_tsn[2]) + ); + FD com_tlm_u_tlm_tx_ack_mgr_fifo_tsn_1_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_ack_mgr_un1_oldest_tsn_1_s_1_2279), + .Q(com_tlm_u_tlm_tx_ack_mgr_fifo_tsn[1]) + ); + FD com_tlm_u_tlm_tx_ack_mgr_fifo_tsn_0_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_ack_mgr_un1_oldest_tsn_1_s_0_2280), + .Q(com_tlm_u_tlm_tx_ack_mgr_fifo_tsn[0]) + ); + FD com_tlm_u_tlm_tx_ack_mgr_mgr_state_8_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_ack_mgr_N_69061_i_2281), + .Q(com_tlm_u_tlm_tx_ack_mgr_mgr_state_8__2282) + ); + FD com_tlm_u_tlm_tx_ack_mgr_mgr_state_4_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_ack_mgr_N_68235_i_2283), + .Q(com_tlm_u_tlm_tx_ack_mgr_mgr_state_4__2284) + ); + FD com_tlm_u_tlm_tx_ack_mgr_mgr_state_2_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_ack_mgr_N_69138_i_2285), + .Q(com_tlm_u_tlm_tx_ack_mgr_mgr_state_2__2286) + ); + FD com_tlm_u_tlm_tx_ack_mgr_mgr_state_0_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_ack_mgr_N_8638_i), + .Q(com_tlm_u_tlm_tx_ack_mgr_mgr_state_0__2287) + ); + INV com_tlm_u_tlm_tx_ack_mgr_N_38168_i_i ( + .I(com_tlm_u_tlm_tx_ack_mgr_N_38168_i), + .O(com_tlm_u_tlm_tx_ack_mgr_N_38168_i_i_2288) + ); + defparam com_tlm_u_tlm_tx_ack_mgr_newest_freed_tsn_qxu_0_0_.INIT = 4'h2; + LUT1_L com_tlm_u_tlm_tx_ack_mgr_newest_freed_tsn_qxu_0_0_ ( + .I0(com_tlm_u_tlm_tx_ack_mgr_newest_freed_tsn[0]), + .LO(com_tlm_u_tlm_tx_ack_mgr_newest_freed_tsn_qxu[0]) + ); + defparam com_tlm_u_tlm_tx_ack_mgr_newest_freed_tsn_qxu_0_11_.INIT = 4'h2; + LUT1_L com_tlm_u_tlm_tx_ack_mgr_newest_freed_tsn_qxu_0_11_ ( + .I0(com_tlm_u_tlm_tx_ack_mgr_newest_freed_tsn[11]), + .LO(com_tlm_u_tlm_tx_ack_mgr_newest_freed_tsn_qxu[11]) + ); + defparam com_tlm_u_tlm_tx_ack_mgr_newest_freed_tsn_qxu_0_10_.INIT = 4'h2; + LUT1_L com_tlm_u_tlm_tx_ack_mgr_newest_freed_tsn_qxu_0_10_ ( + .I0(com_tlm_u_tlm_tx_ack_mgr_newest_freed_tsn[10]), + .LO(com_tlm_u_tlm_tx_ack_mgr_newest_freed_tsn_qxu[10]) + ); + defparam com_tlm_u_tlm_tx_ack_mgr_newest_freed_tsn_qxu_0_9_.INIT = 4'h2; + LUT1_L com_tlm_u_tlm_tx_ack_mgr_newest_freed_tsn_qxu_0_9_ ( + .I0(com_tlm_u_tlm_tx_ack_mgr_newest_freed_tsn[9]), + .LO(com_tlm_u_tlm_tx_ack_mgr_newest_freed_tsn_qxu[9]) + ); + defparam com_tlm_u_tlm_tx_ack_mgr_newest_freed_tsn_qxu_0_8_.INIT = 4'h2; + LUT1_L com_tlm_u_tlm_tx_ack_mgr_newest_freed_tsn_qxu_0_8_ ( + .I0(com_tlm_u_tlm_tx_ack_mgr_newest_freed_tsn[8]), + .LO(com_tlm_u_tlm_tx_ack_mgr_newest_freed_tsn_qxu[8]) + ); + defparam com_tlm_u_tlm_tx_ack_mgr_newest_freed_tsn_qxu_0_7_.INIT = 4'h2; + LUT1_L com_tlm_u_tlm_tx_ack_mgr_newest_freed_tsn_qxu_0_7_ ( + .I0(com_tlm_u_tlm_tx_ack_mgr_newest_freed_tsn[7]), + .LO(com_tlm_u_tlm_tx_ack_mgr_newest_freed_tsn_qxu[7]) + ); + defparam com_tlm_u_tlm_tx_ack_mgr_newest_freed_tsn_qxu_0_6_.INIT = 4'h2; + LUT1_L com_tlm_u_tlm_tx_ack_mgr_newest_freed_tsn_qxu_0_6_ ( + .I0(com_tlm_u_tlm_tx_ack_mgr_newest_freed_tsn[6]), + .LO(com_tlm_u_tlm_tx_ack_mgr_newest_freed_tsn_qxu[6]) + ); + defparam com_tlm_u_tlm_tx_ack_mgr_newest_freed_tsn_qxu_0_5_.INIT = 4'h2; + LUT1_L com_tlm_u_tlm_tx_ack_mgr_newest_freed_tsn_qxu_0_5_ ( + .I0(com_tlm_u_tlm_tx_ack_mgr_newest_freed_tsn[5]), + .LO(com_tlm_u_tlm_tx_ack_mgr_newest_freed_tsn_qxu[5]) + ); + defparam com_tlm_u_tlm_tx_ack_mgr_newest_freed_tsn_qxu_0_4_.INIT = 4'h2; + LUT1_L com_tlm_u_tlm_tx_ack_mgr_newest_freed_tsn_qxu_0_4_ ( + .I0(com_tlm_u_tlm_tx_ack_mgr_newest_freed_tsn[4]), + .LO(com_tlm_u_tlm_tx_ack_mgr_newest_freed_tsn_qxu[4]) + ); + defparam com_tlm_u_tlm_tx_ack_mgr_newest_freed_tsn_qxu_0_3_.INIT = 4'h2; + LUT1_L com_tlm_u_tlm_tx_ack_mgr_newest_freed_tsn_qxu_0_3_ ( + .I0(com_tlm_u_tlm_tx_ack_mgr_newest_freed_tsn[3]), + .LO(com_tlm_u_tlm_tx_ack_mgr_newest_freed_tsn_qxu[3]) + ); + defparam com_tlm_u_tlm_tx_ack_mgr_newest_freed_tsn_qxu_0_2_.INIT = 4'h2; + LUT1_L com_tlm_u_tlm_tx_ack_mgr_newest_freed_tsn_qxu_0_2_ ( + .I0(com_tlm_u_tlm_tx_ack_mgr_newest_freed_tsn[2]), + .LO(com_tlm_u_tlm_tx_ack_mgr_newest_freed_tsn_qxu[2]) + ); + defparam com_tlm_u_tlm_tx_ack_mgr_newest_freed_tsn_qxu_0_1_.INIT = 4'h2; + LUT1_L com_tlm_u_tlm_tx_ack_mgr_newest_freed_tsn_qxu_0_1_ ( + .I0(com_tlm_u_tlm_tx_ack_mgr_newest_freed_tsn[1]), + .LO(com_tlm_u_tlm_tx_ack_mgr_newest_freed_tsn_qxu[1]) + ); + defparam com_tlm_u_tlm_tx_ack_mgr_newest_freed_tsn_s_0_.INIT = 4'h1; + LUT1_L com_tlm_u_tlm_tx_ack_mgr_newest_freed_tsn_s_0_ ( + .I0(com_tlm_u_tlm_tx_ack_mgr_newest_freed_tsn_qxu[0]), + .LO(com_tlm_u_tlm_tx_ack_mgr_newest_freed_tsn_s[0]) + ); + defparam com_tlm_u_tlm_tx_ack_mgr_unreg_frees_pend_un1_frees_pending_0_I_27.INIT = 16'h8421; + LUT4 com_tlm_u_tlm_tx_ack_mgr_unreg_frees_pend_un1_frees_pending_0_I_27 ( + .I0(com_tlm_u_tlm_tx_ack_mgr_latest_ack_tsn[10]), + .I1(com_tlm_u_tlm_tx_ack_mgr_latest_ack_tsn[11]), + .I2(com_tlm_u_tlm_tx_ack_mgr_newest_freed_tsn[10]), + .I3(com_tlm_u_tlm_tx_ack_mgr_newest_freed_tsn[11]), + .O(com_tlm_u_tlm_tx_ack_mgr_N_27_0) + ); + defparam com_tlm_u_tlm_tx_ack_mgr_unreg_skips_pend_un1_skips_pending_0_I_27.INIT = 16'h8421; + LUT4 com_tlm_u_tlm_tx_ack_mgr_unreg_skips_pend_un1_skips_pending_0_I_27 ( + .I0(com_tlm_u_tlm_tx_ack_mgr_fifo_tsn[10]), + .I1(com_tlm_u_tlm_tx_ack_mgr_fifo_tsn[11]), + .I2(com_tlm_u_tlm_tx_am_retry_tsn[10]), + .I3(com_tlm_u_tlm_tx_am_retry_tsn[11]), + .O(com_tlm_u_tlm_tx_ack_mgr_N_27) + ); + defparam com_tlm_u_tlm_tx_ack_mgr_un4_retry_tsn_o_axb_0.INIT = 8'hD8; + LUT3 com_tlm_u_tlm_tx_ack_mgr_un4_retry_tsn_o_axb_0 ( + .I0(com_tlm_u_tlm_tx_ack_mgr_jump_retry_tsn_2290), + .I1(com_tlm_u_tlm_tx_ack_mgr_lnk_rupdate_seq_q[0]), + .I2(com_tlm_u_tlm_tx_am_retry_tsn[0]), + .O(com_tlm_u_tlm_tx_ack_mgr_un4_retry_tsn_o_axb_0_2289) + ); + defparam com_tlm_u_tlm_tx_ack_mgr_unreg_skips_pend_un1_skips_pending_0_I_54.INIT = 16'h8421; + LUT4 com_tlm_u_tlm_tx_ack_mgr_unreg_skips_pend_un1_skips_pending_0_I_54 ( + .I0(com_tlm_u_tlm_tx_ack_mgr_fifo_tsn[2]), + .I1(com_tlm_u_tlm_tx_ack_mgr_fifo_tsn[3]), + .I2(com_tlm_u_tlm_tx_am_retry_tsn[2]), + .I3(com_tlm_u_tlm_tx_am_retry_tsn[3]), + .O(com_tlm_u_tlm_tx_ack_mgr_N_3_0) + ); + defparam com_tlm_u_tlm_tx_ack_mgr_unreg_skips_pend_un1_skips_pending_0_I_45.INIT = 16'h8421; + LUT4 com_tlm_u_tlm_tx_ack_mgr_unreg_skips_pend_un1_skips_pending_0_I_45 ( + .I0(com_tlm_u_tlm_tx_ack_mgr_fifo_tsn[8]), + .I1(com_tlm_u_tlm_tx_ack_mgr_fifo_tsn[9]), + .I2(com_tlm_u_tlm_tx_am_retry_tsn[8]), + .I3(com_tlm_u_tlm_tx_am_retry_tsn[9]), + .O(com_tlm_u_tlm_tx_ack_mgr_N_11_0) + ); + defparam com_tlm_u_tlm_tx_ack_mgr_unreg_skips_pend_un1_skips_pending_0_I_36.INIT = 16'h8421; + LUT4 com_tlm_u_tlm_tx_ack_mgr_unreg_skips_pend_un1_skips_pending_0_I_36 ( + .I0(com_tlm_u_tlm_tx_ack_mgr_fifo_tsn[6]), + .I1(com_tlm_u_tlm_tx_ack_mgr_fifo_tsn[7]), + .I2(com_tlm_u_tlm_tx_am_retry_tsn[6]), + .I3(com_tlm_u_tlm_tx_am_retry_tsn[7]), + .O(com_tlm_u_tlm_tx_ack_mgr_N_19_0) + ); + defparam com_tlm_u_tlm_tx_ack_mgr_unreg_skips_pend_un1_skips_pending_0_I_18.INIT = 16'h8421; + LUT4 com_tlm_u_tlm_tx_ack_mgr_unreg_skips_pend_un1_skips_pending_0_I_18 ( + .I0(com_tlm_u_tlm_tx_ack_mgr_fifo_tsn[4]), + .I1(com_tlm_u_tlm_tx_ack_mgr_fifo_tsn[5]), + .I2(com_tlm_u_tlm_tx_am_retry_tsn[4]), + .I3(com_tlm_u_tlm_tx_am_retry_tsn[5]), + .O(com_tlm_u_tlm_tx_ack_mgr_N_35_0) + ); + defparam com_tlm_u_tlm_tx_ack_mgr_unreg_skips_pend_un1_skips_pending_0_I_9.INIT = 16'h8421; + LUT4 com_tlm_u_tlm_tx_ack_mgr_unreg_skips_pend_un1_skips_pending_0_I_9 ( + .I0(com_tlm_u_tlm_tx_ack_mgr_fifo_tsn[0]), + .I1(com_tlm_u_tlm_tx_ack_mgr_fifo_tsn[1]), + .I2(com_tlm_u_tlm_tx_am_retry_tsn[0]), + .I3(com_tlm_u_tlm_tx_am_retry_tsn[1]), + .O(com_tlm_u_tlm_tx_ack_mgr_N_43_0) + ); + defparam com_tlm_u_tlm_tx_ack_mgr_unreg_frees_pend_un1_frees_pending_0_I_54.INIT = 16'h8421; + LUT4 com_tlm_u_tlm_tx_ack_mgr_unreg_frees_pend_un1_frees_pending_0_I_54 ( + .I0(com_tlm_u_tlm_tx_ack_mgr_latest_ack_tsn[2]), + .I1(com_tlm_u_tlm_tx_ack_mgr_latest_ack_tsn[3]), + .I2(com_tlm_u_tlm_tx_ack_mgr_newest_freed_tsn[2]), + .I3(com_tlm_u_tlm_tx_ack_mgr_newest_freed_tsn[3]), + .O(com_tlm_u_tlm_tx_ack_mgr_N_3) + ); + defparam com_tlm_u_tlm_tx_ack_mgr_unreg_frees_pend_un1_frees_pending_0_I_45.INIT = 16'h8421; + LUT4 com_tlm_u_tlm_tx_ack_mgr_unreg_frees_pend_un1_frees_pending_0_I_45 ( + .I0(com_tlm_u_tlm_tx_ack_mgr_latest_ack_tsn[8]), + .I1(com_tlm_u_tlm_tx_ack_mgr_latest_ack_tsn[9]), + .I2(com_tlm_u_tlm_tx_ack_mgr_newest_freed_tsn[8]), + .I3(com_tlm_u_tlm_tx_ack_mgr_newest_freed_tsn[9]), + .O(com_tlm_u_tlm_tx_ack_mgr_N_11) + ); + defparam com_tlm_u_tlm_tx_ack_mgr_unreg_frees_pend_un1_frees_pending_0_I_36.INIT = 16'h8421; + LUT4 com_tlm_u_tlm_tx_ack_mgr_unreg_frees_pend_un1_frees_pending_0_I_36 ( + .I0(com_tlm_u_tlm_tx_ack_mgr_latest_ack_tsn[6]), + .I1(com_tlm_u_tlm_tx_ack_mgr_latest_ack_tsn[7]), + .I2(com_tlm_u_tlm_tx_ack_mgr_newest_freed_tsn[6]), + .I3(com_tlm_u_tlm_tx_ack_mgr_newest_freed_tsn[7]), + .O(com_tlm_u_tlm_tx_ack_mgr_N_19) + ); + defparam com_tlm_u_tlm_tx_ack_mgr_unreg_frees_pend_un1_frees_pending_0_I_18.INIT = 16'h8421; + LUT4 com_tlm_u_tlm_tx_ack_mgr_unreg_frees_pend_un1_frees_pending_0_I_18 ( + .I0(com_tlm_u_tlm_tx_ack_mgr_latest_ack_tsn[4]), + .I1(com_tlm_u_tlm_tx_ack_mgr_latest_ack_tsn[5]), + .I2(com_tlm_u_tlm_tx_ack_mgr_newest_freed_tsn[4]), + .I3(com_tlm_u_tlm_tx_ack_mgr_newest_freed_tsn[5]), + .O(com_tlm_u_tlm_tx_ack_mgr_N_35) + ); + defparam com_tlm_u_tlm_tx_ack_mgr_unreg_frees_pend_un1_frees_pending_0_I_9.INIT = 16'h8421; + LUT4 com_tlm_u_tlm_tx_ack_mgr_unreg_frees_pend_un1_frees_pending_0_I_9 ( + .I0(com_tlm_u_tlm_tx_ack_mgr_latest_ack_tsn[0]), + .I1(com_tlm_u_tlm_tx_ack_mgr_latest_ack_tsn[1]), + .I2(com_tlm_u_tlm_tx_ack_mgr_newest_freed_tsn[0]), + .I3(com_tlm_u_tlm_tx_ack_mgr_newest_freed_tsn[1]), + .O(com_tlm_u_tlm_tx_ack_mgr_N_43) + ); + GND com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_GND ( + .G(com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_GND_2291) + ); + SRLC16E com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_srlrow_0__srlcol_0__srlinst ( + .CE(com_tlm_u_tlm_tx_ds_buf_src_rdy), + .D(com_tlm_u_tlm_tx_ds_buf_num[0]), + .Q(com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_shift_tap[0]), + .CLK(NlwRenamedSig_OI_trn_clk), + .Q15(NLW_com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_srlrow_0__srlcol_0__srlinst_Q15_UNCONNECTED), + .A0(com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_raddr_lo[0]), + .A1(com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_raddr_lo[1]), + .A2(com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_raddr_lo[2]), + .A3(com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_raddr_lo[3]) + ); + SRLC16E com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_srlrow_0__srlcol_3__srlinst ( + .CE(com_tlm_u_tlm_tx_ds_buf_src_rdy), + .D(com_tlm_u_tlm_tx_ds_buf_num[3]), + .Q(com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_shift_tap[3]), + .CLK(NlwRenamedSig_OI_trn_clk), + .Q15(NLW_com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_srlrow_0__srlcol_3__srlinst_Q15_UNCONNECTED), + .A0(com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_raddr_lo[0]), + .A1(com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_raddr_lo[1]), + .A2(com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_raddr_lo[2]), + .A3(com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_raddr_lo[3]) + ); + SRLC16E com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_srlrow_0__srlcol_2__srlinst ( + .CE(com_tlm_u_tlm_tx_ds_buf_src_rdy), + .D(com_tlm_u_tlm_tx_ds_buf_num[2]), + .Q(com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_shift_tap[2]), + .CLK(NlwRenamedSig_OI_trn_clk), + .Q15(NLW_com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_srlrow_0__srlcol_2__srlinst_Q15_UNCONNECTED), + .A0(com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_raddr_lo[0]), + .A1(com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_raddr_lo[1]), + .A2(com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_raddr_lo[2]), + .A3(com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_raddr_lo[3]) + ); + SRLC16E com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_srlrow_0__srlcol_1__srlinst ( + .CE(com_tlm_u_tlm_tx_ds_buf_src_rdy), + .D(com_tlm_u_tlm_tx_ds_buf_num[1]), + .Q(com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_shift_tap[1]), + .CLK(NlwRenamedSig_OI_trn_clk), + .Q15(NLW_com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_srlrow_0__srlcol_1__srlinst_Q15_UNCONNECTED), + .A0(com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_raddr_lo[0]), + .A1(com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_raddr_lo[1]), + .A2(com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_raddr_lo[2]), + .A3(com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_raddr_lo[3]) + ); + FDS com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_raddr_lo_0_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_raddr_lo_5_i_m2_i_m3_0[0]), + .Q(com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_raddr_lo[0]), + .S(plm_link_up_i) + ); + FDS com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_raddr_lo_1_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_raddr_lo_5_i_m2_i_m3_0[1]), + .Q(com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_raddr_lo[1]), + .S(plm_link_up_i) + ); + FDS com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_raddr_lo_2_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_raddr_lo_5_i_m2_i_m3_0[2]), + .Q(com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_raddr_lo[2]), + .S(plm_link_up_i) + ); + FDS com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_raddr_lo_3_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_raddr_lo_5_i_m2_i_m3_0[3]), + .Q(com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_raddr_lo[3]), + .S(plm_link_up_i) + ); + FDS com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_bkp_raddr_lo_0_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_bkp_raddr_lo_7_i_m2_0[0]), + .Q(com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_bkp_raddr_lo[0]), + .S(plm_link_up_i) + ); + FDS com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_bkp_raddr_lo_1_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_bkp_raddr_lo_7_i_m2_0[1]), + .Q(com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_bkp_raddr_lo[1]), + .S(plm_link_up_i) + ); + FDS com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_bkp_raddr_lo_2_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_bkp_raddr_lo_7_i_m2_0[2]), + .Q(com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_bkp_raddr_lo[2]), + .S(plm_link_up_i) + ); + FDS com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_bkp_raddr_lo_3_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_N_38376_i_2302), + .Q(com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_bkp_raddr_lo[3]), + .S(plm_link_up_i) + ); + FDRSE com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_bkp_nxt_vld ( + .CE(com_tlm_u_tlm_tx_ack_mgr_N_38168_i_i_2288), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_ack_mgr_fifo_nxt_vld), + .Q(com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_bkp_nxt_vld_2301), + .R(plm_link_up_i), + .S(com_tlm_u_tlm_tx_ds_buf_src_rdy) + ); + FDRE com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_nxt_vld_o ( + .CE(com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_N_67901_i_2296), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_nxt_vld_o_8_iv_i_m2_i_m3_0_2300), + .Q(com_tlm_u_tlm_tx_ack_mgr_fifo_nxt_vld), + .R(plm_link_up_i) + ); + FDRE com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_bkp_vld ( + .CE(com_tlm_u_tlm_tx_ack_mgr_N_38168_i_i_2288), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_ack_mgr_fifo_vld), + .Q(com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_bkp_vld_2299), + .R(plm_link_up_i) + ); + FDRE com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_bkp_data_0_ ( + .CE(com_tlm_u_tlm_tx_ack_mgr_N_38168_i_i_2288), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_freed_buf[0]), + .Q(com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_bkp_data[0]), + .R(plm_link_up_i) + ); + FDRE com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_bkp_data_1_ ( + .CE(com_tlm_u_tlm_tx_ack_mgr_N_38168_i_i_2288), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_freed_buf[1]), + .Q(com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_bkp_data[1]), + .R(plm_link_up_i) + ); + FDRE com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_bkp_data_2_ ( + .CE(com_tlm_u_tlm_tx_ack_mgr_N_38168_i_i_2288), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_freed_buf[2]), + .Q(com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_bkp_data[2]), + .R(plm_link_up_i) + ); + FDRE com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_bkp_data_3_ ( + .CE(com_tlm_u_tlm_tx_ack_mgr_N_38168_i_i_2288), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_freed_buf[3]), + .Q(com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_bkp_data[3]), + .R(plm_link_up_i) + ); + FDRE com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_vld_o ( + .CE(com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_N_69139_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_vld_o_5_i_m2_i_m3_0_2298), + .Q(com_tlm_u_tlm_tx_ack_mgr_fifo_vld), + .R(plm_link_up_i) + ); + defparam com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_un1_bkp_raddr_lo_1_p4.INIT = 16'h8000; + LUT4_L com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_un1_bkp_raddr_lo_1_p4 ( + .I0(com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_un1_bkp_raddr_lo_i_m2_0[0]), + .I1(com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_un1_bkp_raddr_lo_i_m2_0[1]), + .I2(com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_un1_bkp_raddr_lo_i_m2_0[2]), + .I3(com_tlm_u_tlm_tx_ds_buf_src_rdy), + .LO(com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_un1_bkp_raddr_lo_1_p4_2303) + ); + MUXCY_L com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_un1_raddr_lo_1_cry_0 ( + .CI(com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_GND_2291), + .DI(com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_raddr_lo[0]), + .LO(com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_un1_raddr_lo_1_cry_0_2292), + .S(com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_un1_raddr_lo_1_axb_0_2307) + ); + MUXCY_L com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_un1_raddr_lo_1_cry_1 ( + .CI(com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_un1_raddr_lo_1_cry_0_2292), + .DI(com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_raddr_lo[1]), + .LO(com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_un1_raddr_lo_1_cry_1_2293), + .S(com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_un1_raddr_lo_1_axb_1_2310) + ); + XORCY com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_un1_raddr_lo_1_s_1 ( + .CI(com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_un1_raddr_lo_1_cry_0_2292), + .LI(com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_un1_raddr_lo_1_axb_1_2310), + .O(com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_un1_raddr_lo_1_s_1_2306) + ); + MUXCY_L com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_un1_raddr_lo_1_cry_2 ( + .CI(com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_un1_raddr_lo_1_cry_1_2293), + .DI(com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_raddr_lo[2]), + .LO(com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_un1_raddr_lo_1_cry_2_2294), + .S(com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_un1_raddr_lo_1_axb_2_2309) + ); + XORCY com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_un1_raddr_lo_1_s_2 ( + .CI(com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_un1_raddr_lo_1_cry_1_2293), + .LI(com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_un1_raddr_lo_1_axb_2_2309), + .O(com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_un1_raddr_lo_1_s_2_2305) + ); + XORCY com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_un1_raddr_lo_1_s_3 ( + .CI(com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_un1_raddr_lo_1_cry_2_2294), + .LI(com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_un1_raddr_lo_1_axb_3_2295), + .O(com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_un1_raddr_lo_1_s_3_2304) + ); + defparam com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_raddr_w_backup_ct_o35_0_0_o3_0.INIT = 4'h8; + LUT2_L com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_raddr_w_backup_ct_o35_0_0_o3_0 ( + .I0(com_tlm_u_tlm_tx_am_retry_dst_rdy), + .I1(com_tlm_u_tlm_tx_am_retry_src_rdy), + .LO(com_tlm_u_tlm_tx_ack_mgr_N_38140_i) + ); + defparam com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_un1_bkp_i_1_i_0_0_o4.INIT = 4'h1; + LUT2 com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_un1_bkp_i_1_i_0_0_o4 ( + .I0(com_tlm_u_tlm_tx_ack_mgr_mgr_state_11__2248), + .I1(com_tlm_u_tlm_tx_ack_mgr_mgr_state_12__2231), + .O(com_tlm_u_tlm_tx_ack_mgr_N_38092_i) + ); + defparam com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_raddr_w_backup_ct_o35_0_0_o3_1.INIT = 8'h0E; + LUT3 com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_raddr_w_backup_ct_o35_0_0_o3_1 ( + .I0(com_tlm_u_tlm_tx_ack_mgr_mgr_state_2__2286), + .I1(com_tlm_u_tlm_tx_ack_mgr_mgr_state_4__2284), + .I2(com_tlm_u_tlm_tx_ack_mgr_un1_frees_pending), + .O(com_tlm_u_tlm_tx_N_38179_i) + ); + defparam com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_un1_bkp_i_1_i_0_0_a4_2.INIT = 16'h0001; + LUT4 com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_un1_bkp_i_1_i_0_0_a4_2 ( + .I0(com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_raddr_lo[0]), + .I1(com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_raddr_lo[1]), + .I2(com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_raddr_lo[2]), + .I3(com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_raddr_lo[3]), + .O(com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_un1_bkp_i_1_i_0_0_a4_2_2297) + ); + defparam com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_bkp_raddr_lo_7_i_i_o3_3_.INIT = 4'h1; + LUT2 com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_bkp_raddr_lo_7_i_i_o3_3_ ( + .I0(com_tlm_u_tlm_tx_ack_mgr_N_38168_i), + .I1(com_tlm_u_tlm_tx_ds_buf_src_rdy), + .O(com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_bkp_raddr_lo_7_i_i_o3[3]) + ); + defparam com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_raddr_w_backup_ct_o35_0_0_o3.INIT = 8'h40; + LUT3 com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_raddr_w_backup_ct_o35_0_0_o3 ( + .I0(com_tlm_u_tlm_tx_ack_mgr_N_38101_i), + .I1(com_tlm_u_tlm_tx_ack_mgr_N_38388_2), + .I2(com_tlm_u_tlm_tx_ack_mgr_fifo_vld), + .O(com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_ct_o35_0_0_o3) + ); + defparam com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_un1_bkp_raddr_lo_i_m2_0_0_.INIT = 16'hD8CC; + LUT4 com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_un1_bkp_raddr_lo_i_m2_0_0_ ( + .I0(com_tlm_u_tlm_tx_ack_mgr_N_38168_i), + .I1(com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_bkp_raddr_lo[0]), + .I2(com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_raddr_lo[0]), + .I3(com_tlm_u_tlm_tx_ds_buf_src_rdy), + .O(com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_un1_bkp_raddr_lo_i_m2_0[0]) + ); + defparam com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_un1_bkp_raddr_lo_i_m2_0_1_.INIT = 16'hD8CC; + LUT4 com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_un1_bkp_raddr_lo_i_m2_0_1_ ( + .I0(com_tlm_u_tlm_tx_ack_mgr_N_38168_i), + .I1(com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_bkp_raddr_lo[1]), + .I2(com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_raddr_lo[1]), + .I3(com_tlm_u_tlm_tx_ds_buf_src_rdy), + .O(com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_un1_bkp_raddr_lo_i_m2_0[1]) + ); + defparam com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_un1_bkp_raddr_lo_i_m2_0_2_.INIT = 16'hD8CC; + LUT4 com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_un1_bkp_raddr_lo_i_m2_0_2_ ( + .I0(com_tlm_u_tlm_tx_ack_mgr_N_38168_i), + .I1(com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_bkp_raddr_lo[2]), + .I2(com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_raddr_lo[2]), + .I3(com_tlm_u_tlm_tx_ds_buf_src_rdy), + .O(com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_un1_bkp_raddr_lo_i_m2_0[2]) + ); + defparam com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_un1_bkp_raddr_lo_i_3_.INIT = 16'hD8CC; + LUT4 com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_un1_bkp_raddr_lo_i_3_ ( + .I0(com_tlm_u_tlm_tx_ack_mgr_N_38168_i), + .I1(com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_bkp_raddr_lo[3]), + .I2(com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_raddr_lo[3]), + .I3(com_tlm_u_tlm_tx_ds_buf_src_rdy), + .O(com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_N_34665_i) + ); + defparam com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_un1_bkp_raddr_lo_1_ac0.INIT = 4'h8; + LUT2_L com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_un1_bkp_raddr_lo_1_ac0 ( + .I0(com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_un1_bkp_raddr_lo_i_m2_0[0]), + .I1(com_tlm_u_tlm_tx_ds_buf_src_rdy), + .LO(com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_un1_bkp_raddr_lo_1_c1) + ); + defparam com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_data_bits_N_69139_i.INIT = 16'hDFFF; + LUT4 com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_data_bits_N_69139_i ( + .I0(com_tlm_u_tlm_tx_ack_mgr_N_38092_i), + .I1(com_tlm_u_tlm_tx_ack_mgr_N_38101_i), + .I2(com_tlm_u_tlm_tx_ack_mgr_N_38388_2), + .I3(com_tlm_u_tlm_tx_ack_mgr_fifo_vld), + .O(com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_N_69139_i) + ); + defparam com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_un1_raddr_lo_1_axb_3.INIT = 16'hCC9C; + LUT4 com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_un1_raddr_lo_1_axb_3 ( + .I0(com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_ct_o35_0_0_o3), + .I1(com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_raddr_lo[3]), + .I2(com_tlm_u_tlm_tx_ack_mgr_fifo_nxt_vld), + .I3(com_tlm_u_tlm_tx_ds_buf_src_rdy), + .O(com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_un1_raddr_lo_1_axb_3_2295) + ); + defparam com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_N_67901_i.INIT = 16'hFF75; + LUT4 com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_N_67901_i ( + .I0(com_tlm_u_tlm_tx_ack_mgr_N_38092_i), + .I1(com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_ct_o35_0_0_o3), + .I2(com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_un1_bkp_i_1_i_0_0_a4_2_2297), + .I3(com_tlm_u_tlm_tx_ds_buf_src_rdy), + .O(com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_N_67901_i_2296) + ); + defparam com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_un1_raddr_lo_1_axb_0.INIT = 16'h639C; + LUT4 com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_un1_raddr_lo_1_axb_0 ( + .I0(com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_ct_o35_0_0_o3), + .I1(com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_raddr_lo[0]), + .I2(com_tlm_u_tlm_tx_ack_mgr_fifo_nxt_vld), + .I3(com_tlm_u_tlm_tx_ds_buf_src_rdy), + .O(com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_un1_raddr_lo_1_axb_0_2307) + ); + defparam com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_data_bits_d_o_4_i_m2_i_m3_0_3_.INIT = 8'hE4; + LUT3_L com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_data_bits_d_o_4_i_m2_i_m3_0_3_ ( + .I0(com_tlm_u_tlm_tx_ack_mgr_N_38092_i), + .I1(com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_bkp_data[3]), + .I2(com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_shift_tap[3]), + .LO(com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_d_o_4_i_m2_i_m3_0[3]) + ); + defparam com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_data_bits_d_o_4_i_m2_i_m3_0_2_.INIT = 8'hE4; + LUT3_L com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_data_bits_d_o_4_i_m2_i_m3_0_2_ ( + .I0(com_tlm_u_tlm_tx_ack_mgr_N_38092_i), + .I1(com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_bkp_data[2]), + .I2(com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_shift_tap[2]), + .LO(com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_d_o_4_i_m2_i_m3_0[2]) + ); + defparam com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_data_bits_d_o_4_i_m2_i_m3_0_1_.INIT = 8'hE4; + LUT3_L com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_data_bits_d_o_4_i_m2_i_m3_0_1_ ( + .I0(com_tlm_u_tlm_tx_ack_mgr_N_38092_i), + .I1(com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_bkp_data[1]), + .I2(com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_shift_tap[1]), + .LO(com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_d_o_4_i_m2_i_m3_0[1]) + ); + defparam com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_data_bits_d_o_4_i_m2_i_m3_0_0_.INIT = 8'hE4; + LUT3_L com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_data_bits_d_o_4_i_m2_i_m3_0_0_ ( + .I0(com_tlm_u_tlm_tx_ack_mgr_N_38092_i), + .I1(com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_bkp_data[0]), + .I2(com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_shift_tap[0]), + .LO(com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_d_o_4_i_m2_i_m3_0[0]) + ); + defparam com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_vld_o_5_i_m2_i_m3_0.INIT = 8'hE4; + LUT3_L com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_vld_o_5_i_m2_i_m3_0 ( + .I0(com_tlm_u_tlm_tx_ack_mgr_N_38092_i), + .I1(com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_bkp_vld_2299), + .I2(com_tlm_u_tlm_tx_ack_mgr_fifo_nxt_vld), + .LO(com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_vld_o_5_i_m2_i_m3_0_2298) + ); + defparam com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_nxt_vld_o_8_iv_i_m2_i_m3_0.INIT = 8'hE4; + LUT3_L com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_nxt_vld_o_8_iv_i_m2_i_m3_0 ( + .I0(com_tlm_u_tlm_tx_ack_mgr_N_38092_i), + .I1(com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_bkp_nxt_vld_2301), + .I2(com_tlm_u_tlm_tx_ds_buf_src_rdy), + .LO(com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_nxt_vld_o_8_iv_i_m2_i_m3_0_2300) + ); + defparam com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_N_38376_i.INIT = 16'hD1E2; + LUT4_L com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_N_38376_i ( + .I0(com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_N_34665_i), + .I1(com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_bkp_raddr_lo_7_i_i_o3[3]), + .I2(com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_raddr_lo[3]), + .I3(com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_un1_bkp_raddr_lo_1_p4_2303), + .LO(com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_N_38376_i_2302) + ); + defparam com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_bkp_raddr_lo_7_i_m2_0_2_.INIT = 16'hD1E2; + LUT4_L com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_bkp_raddr_lo_7_i_m2_0_2_ ( + .I0(com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_un1_bkp_raddr_lo_i_m2_0[2]), + .I1(com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_bkp_raddr_lo_7_i_i_o3[3]), + .I2(com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_raddr_lo[2]), + .I3(com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_un1_bkp_raddr_lo_1_ac0_1_2308), + .LO(com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_bkp_raddr_lo_7_i_m2_0[2]) + ); + defparam com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_bkp_raddr_lo_7_i_m2_0_1_.INIT = 16'hD1E2; + LUT4_L com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_bkp_raddr_lo_7_i_m2_0_1_ ( + .I0(com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_un1_bkp_raddr_lo_i_m2_0[1]), + .I1(com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_bkp_raddr_lo_7_i_i_o3[3]), + .I2(com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_raddr_lo[1]), + .I3(com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_un1_bkp_raddr_lo_1_c1), + .LO(com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_bkp_raddr_lo_7_i_m2_0[1]) + ); + defparam com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_bkp_raddr_lo_7_i_m2_0_0_.INIT = 16'h27D8; + LUT4_L com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_bkp_raddr_lo_7_i_m2_0_0_ ( + .I0(com_tlm_u_tlm_tx_ack_mgr_N_38168_i), + .I1(com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_bkp_raddr_lo[0]), + .I2(com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_raddr_lo[0]), + .I3(com_tlm_u_tlm_tx_ds_buf_src_rdy), + .LO(com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_bkp_raddr_lo_7_i_m2_0[0]) + ); + defparam com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_raddr_w_backup_raddr_lo_5_i_m2_i_m3_0_3_.INIT = 8'hE4; + LUT3_L com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_raddr_w_backup_raddr_lo_5_i_m2_i_m3_0_3_ ( + .I0(com_tlm_u_tlm_tx_ack_mgr_N_38092_i), + .I1(com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_bkp_raddr_lo[3]), + .I2(com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_un1_raddr_lo_1_s_3_2304), + .LO(com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_raddr_lo_5_i_m2_i_m3_0[3]) + ); + defparam com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_raddr_w_backup_raddr_lo_5_i_m2_i_m3_0_2_.INIT = 8'hE4; + LUT3_L com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_raddr_w_backup_raddr_lo_5_i_m2_i_m3_0_2_ ( + .I0(com_tlm_u_tlm_tx_ack_mgr_N_38092_i), + .I1(com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_bkp_raddr_lo[2]), + .I2(com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_un1_raddr_lo_1_s_2_2305), + .LO(com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_raddr_lo_5_i_m2_i_m3_0[2]) + ); + defparam com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_raddr_w_backup_raddr_lo_5_i_m2_i_m3_0_1_.INIT = 8'hE4; + LUT3_L com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_raddr_w_backup_raddr_lo_5_i_m2_i_m3_0_1_ ( + .I0(com_tlm_u_tlm_tx_ack_mgr_N_38092_i), + .I1(com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_bkp_raddr_lo[1]), + .I2(com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_un1_raddr_lo_1_s_1_2306), + .LO(com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_raddr_lo_5_i_m2_i_m3_0[1]) + ); + defparam com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_raddr_w_backup_raddr_lo_5_i_m2_i_m3_0_0_.INIT = 8'hE4; + LUT3_L com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_raddr_w_backup_raddr_lo_5_i_m2_i_m3_0_0_ ( + .I0(com_tlm_u_tlm_tx_ack_mgr_N_38092_i), + .I1(com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_bkp_raddr_lo[0]), + .I2(com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_un1_raddr_lo_1_axb_0_2307), + .LO(com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_raddr_lo_5_i_m2_i_m3_0[0]) + ); + defparam com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_raddr_w_backup_ct_o35_0_0_a4_2.INIT = 8'h15; + LUT3 com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_raddr_w_backup_ct_o35_0_0_a4_2 ( + .I0(com_tlm_u_tlm_tx_N_38179_i), + .I1(com_tlm_u_tlm_tx_am_retry_src_rdy), + .I2(com_tlm_u_tlm_tx_am_retry_dst_rdy), + .O(com_tlm_u_tlm_tx_ack_mgr_N_38388_2) + ); + defparam com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_un1_bkp_raddr_lo_1_ac0_1.INIT = 8'h80; + LUT3_L com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_un1_bkp_raddr_lo_1_ac0_1 ( + .I0(com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_un1_bkp_raddr_lo_i_m2_0[1]), + .I1(com_tlm_u_tlm_tx_ds_buf_src_rdy), + .I2(com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_un1_bkp_raddr_lo_i_m2_0[0]), + .LO(com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_un1_bkp_raddr_lo_1_ac0_1_2308) + ); + FDE com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_d_o_3_ ( + .CE(com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_N_69139_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_d_o_4_i_m2_i_m3_0[3]), + .Q(com_tlm_u_tlm_tx_freed_buf[3]) + ); + FDE com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_d_o_2_ ( + .CE(com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_N_69139_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_d_o_4_i_m2_i_m3_0[2]), + .Q(com_tlm_u_tlm_tx_freed_buf[2]) + ); + FDE com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_d_o_1_ ( + .CE(com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_N_69139_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_d_o_4_i_m2_i_m3_0[1]), + .Q(com_tlm_u_tlm_tx_freed_buf[1]) + ); + FDE com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_d_o_0_ ( + .CE(com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_N_69139_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_d_o_4_i_m2_i_m3_0[0]), + .Q(com_tlm_u_tlm_tx_freed_buf[0]) + ); + defparam com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_un1_raddr_lo_1_axb_2.INIT = 16'hCC9C; + LUT4 com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_un1_raddr_lo_1_axb_2 ( + .I0(com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_ct_o35_0_0_o3), + .I1(com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_raddr_lo[2]), + .I2(com_tlm_u_tlm_tx_ack_mgr_fifo_nxt_vld), + .I3(com_tlm_u_tlm_tx_ds_buf_src_rdy), + .O(com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_un1_raddr_lo_1_axb_2_2309) + ); + defparam com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_un1_raddr_lo_1_axb_1.INIT = 16'hCC9C; + LUT4 com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_un1_raddr_lo_1_axb_1 ( + .I0(com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_ct_o35_0_0_o3), + .I1(com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_raddr_lo[1]), + .I2(com_tlm_u_tlm_tx_ack_mgr_fifo_nxt_vld), + .I3(com_tlm_u_tlm_tx_ds_buf_src_rdy), + .O(com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_un1_raddr_lo_1_axb_1_2310) + ); + defparam com_tlm_u_tlm_tx_fc_snk_fc_init_vld_o_0_a2.INIT = 4'h2; + LUT2_L com_tlm_u_tlm_tx_fc_snk_fc_init_vld_o_0_a2 ( + .I0(com_lnk_rfc_type[2]), + .I1(com_lnk_rfc_vc_n[0]), + .LO(com_tlm_u_tlm_tx_fc_init_vld) + ); + defparam com_tlm_u_tlm_tx_fc_snk_fc_update_vld_o_0_a2.INIT = 4'h1; + LUT2_L com_tlm_u_tlm_tx_fc_snk_fc_update_vld_o_0_a2 ( + .I0(com_lnk_rfc_type[2]), + .I1(com_lnk_rfc_vc_n[0]), + .LO(com_tlm_u_tlm_tx_fc_update_vld) + ); + VCC com_tlm_u_tlm_tx_vc0_buf_pool_VCC ( + .P(com_tlm_u_tlm_tx_vc0_buf_pool_VCC_2313) + ); + GND com_tlm_u_tlm_tx_vc0_buf_pool_GND ( + .G(com_tlm_u_tlm_tx_vc0_buf_pool_GND_2320) + ); + FDRSE com_tlm_u_tlm_tx_vc0_buf_pool_buf_avail ( + .CE(com_tlm_u_tlm_tx_vc0_buf_pool_N_17124_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_buf_pool_GND_2320), + .Q(com_tlm_u_tlm_tx_vc0_in_frame), + .R(plm_link_up_i), + .S(com_tlm_u_tlm_tx_vc0_buf_pool_N_17127_i) + ); + FDRE com_tlm_u_tlm_tx_vc0_buf_pool_retry_d ( + .CE(com_tlm_u_tlm_tx_vc0_buf_pool_N_17122_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_buf_pool_retry_dd_2311), + .Q(com_tlm_u_tlm_tx_vc0_retry), + .R(plm_link_up_i) + ); + FDRE com_tlm_u_tlm_tx_vc0_buf_pool_retry_dd ( + .CE(com_tlm_u_tlm_tx_vc0_nxt_seq_state_0_sqmuxa_i_o2_i_a2), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_start_retry), + .Q(com_tlm_u_tlm_tx_vc0_buf_pool_retry_dd_2311), + .R(plm_link_up_i) + ); + FDRE com_tlm_u_tlm_tx_vc0_buf_pool_rvld_q_any ( + .CE(com_tlm_u_tlm_tx_vc0_buf_pool_N_17214_i_i_2406), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_buf_pool_rvld_any_2332), + .Q(com_tlm_u_tlm_tx_vc0_src_rdy), + .R(plm_link_up_i) + ); + FDRE com_tlm_u_tlm_tx_vc0_buf_pool_rvld_any ( + .CE(com_tlm_u_tlm_tx_vc0_buf_pool_N_69239_i_2325), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_buf_pool_N_51062_i_2404), + .Q(com_tlm_u_tlm_tx_vc0_buf_pool_rvld_any_2332), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_tx_vc0_buf_pool_rdata_sof_d_hold ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_buf_pool_rdata_sof_d_hold_3), + .Q(com_tlm_u_tlm_tx_vc0_buf_pool_rdata_sof_d_hold_2322), + .R(plm_link_up_i) + ); + FDRE com_tlm_u_tlm_tx_vc0_buf_pool_wdata_vld_any ( + .CE(com_tlm_u_tlm_tx_vc0_buf_pool_N_22106_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_trn_vld), + .Q(com_tlm_u_tlm_tx_vc0_buf_pool_wdata_vld_any_2324), + .R(plm_link_up_i) + ); + FDRE com_tlm_u_tlm_tx_vc0_buf_pool_rdata_sof ( + .CE(com_tlm_u_tlm_tx_vc0_buf_pool_en_ram_i_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_buf_pool_N_51062_i_2404), + .Q(com_tlm_u_tlm_tx_vc0_buf_pool_rdata_sof_2323), + .R(plm_link_up_i) + ); + FDRE com_tlm_u_tlm_tx_vc0_buf_pool_rdata_q_all_64_ ( + .CE(com_tlm_u_tlm_tx_vc0_buf_pool_N_17214_i_i_2406), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_buf_pool_rdata_q_all_5_64_), + .Q(com_tlm_u_tlm_tx_vc0_cfg), + .R(plm_link_up_i) + ); + FDRE com_tlm_u_tlm_tx_vc0_buf_pool_rdata_q_all_65_ ( + .CE(com_tlm_u_tlm_tx_vc0_buf_pool_N_17214_i_i_2406), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_buf_pool_rdata_q_all_5_65_), + .Q(com_tlm_u_tlm_tx_vc0_eof), + .R(plm_link_up_i) + ); + FDRE com_tlm_u_tlm_tx_vc0_buf_pool_rdata_q_all_66_ ( + .CE(com_tlm_u_tlm_tx_vc0_buf_pool_N_17214_i_i_2406), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_buf_pool_rdata_q_all_5_66_), + .Q(com_tlm_u_tlm_tx_vc0_sof), + .R(plm_link_up_i) + ); + FDRE com_tlm_u_tlm_tx_vc0_buf_pool_rdata_q_all_67_ ( + .CE(com_tlm_u_tlm_tx_vc0_buf_pool_N_17214_i_i_2406), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_rdata_q_all_5[67]), + .Q(com_tlm_u_tlm_tx_vc0_buf_pool_rdata_q_all[67]), + .R(plm_link_up_i) + ); + FDRE com_tlm_u_tlm_tx_vc0_buf_pool_rdata_q_all_68_ ( + .CE(com_tlm_u_tlm_tx_vc0_buf_pool_N_17214_i_i_2406), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_buf_pool_rdata_q_all_5_68_), + .Q(com_tlm_u_tlm_tx_rdata_q_all[68]), + .R(plm_link_up_i) + ); + FDRSE com_tlm_u_tlm_tx_vc0_buf_pool_errfwd_wen ( + .CE(com_tlm_u_tlm_tx_vc0_trn_vld), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_buf_pool_GND_2320), + .Q(com_tlm_u_tlm_tx_vc0_buf_pool_errfwd_wen_2312), + .R(plm_link_up_i), + .S(com_tlm_u_tlm_tx_vc0_buf_pool_N_22083_i) + ); + RAM16X1D com_tlm_u_tlm_tx_vc0_buf_pool_errfwd_0_I_1 ( + .DPO(com_tlm_u_tlm_tx_vc0_buf_pool_errfwd), + .WCLK(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_buf_pool_wdata_errfwd_2403), + .A0(com_tlm_u_tlm_tx_vc0_buf_pool_waddr_h[0]), + .A1(com_tlm_u_tlm_tx_vc0_buf_pool_waddr_h[1]), + .A2(com_tlm_u_tlm_tx_vc0_buf_pool_waddr_h[2]), + .A3(com_tlm_u_tlm_tx_vc0_buf_pool_waddr_h[3]), + .DPRA0(com_tlm_u_tlm_tx_vc0_buf_pool_raddr_h[0]), + .DPRA1(com_tlm_u_tlm_tx_vc0_buf_pool_raddr_h[1]), + .DPRA2(com_tlm_u_tlm_tx_vc0_buf_pool_raddr_h[2]), + .DPRA3(com_tlm_u_tlm_tx_vc0_buf_pool_raddr_h[3]), + .SPO(NLW_com_tlm_u_tlm_tx_vc0_buf_pool_errfwd_0_I_1_SPO_UNCONNECTED), + .WE(com_tlm_u_tlm_tx_vc0_buf_pool_errfwd_wen_2312) + ); + MUXCY_L com_tlm_u_tlm_tx_vc0_buf_pool_waddr_l_1_cry_0 ( + .CI(com_tlm_u_tlm_tx_vc0_buf_pool_VCC_2313), + .DI(com_tlm_u_tlm_tx_vc0_buf_pool_GND_2320), + .LO(com_tlm_u_tlm_tx_vc0_buf_pool_waddr_l_1_cry_0_2314), + .S(com_tlm_u_tlm_tx_vc0_buf_pool_waddr_l_1_axb_0_2407) + ); + MUXCY_L com_tlm_u_tlm_tx_vc0_buf_pool_waddr_l_1_cry_1 ( + .CI(com_tlm_u_tlm_tx_vc0_buf_pool_waddr_l_1_cry_0_2314), + .DI(com_tlm_u_tlm_tx_vc0_buf_pool_GND_2320), + .LO(com_tlm_u_tlm_tx_vc0_buf_pool_waddr_l_1_cry_1_2315), + .S(com_tlm_u_tlm_tx_vc0_buf_pool_waddr_l_1_axb_1_2331) + ); + XORCY com_tlm_u_tlm_tx_vc0_buf_pool_waddr_l_1_s_1 ( + .CI(com_tlm_u_tlm_tx_vc0_buf_pool_waddr_l_1_cry_0_2314), + .LI(com_tlm_u_tlm_tx_vc0_buf_pool_waddr_l_1_axb_1_2331), + .O(com_tlm_u_tlm_tx_vc0_buf_pool_waddr_l_1[1]) + ); + MUXCY_L com_tlm_u_tlm_tx_vc0_buf_pool_waddr_l_1_cry_2 ( + .CI(com_tlm_u_tlm_tx_vc0_buf_pool_waddr_l_1_cry_1_2315), + .DI(com_tlm_u_tlm_tx_vc0_buf_pool_GND_2320), + .LO(com_tlm_u_tlm_tx_vc0_buf_pool_waddr_l_1_cry_2_2316), + .S(com_tlm_u_tlm_tx_vc0_buf_pool_waddr_l_1_axb_2_2330) + ); + XORCY com_tlm_u_tlm_tx_vc0_buf_pool_waddr_l_1_s_2 ( + .CI(com_tlm_u_tlm_tx_vc0_buf_pool_waddr_l_1_cry_1_2315), + .LI(com_tlm_u_tlm_tx_vc0_buf_pool_waddr_l_1_axb_2_2330), + .O(com_tlm_u_tlm_tx_vc0_buf_pool_waddr_l_1[2]) + ); + MUXCY_L com_tlm_u_tlm_tx_vc0_buf_pool_waddr_l_1_cry_3 ( + .CI(com_tlm_u_tlm_tx_vc0_buf_pool_waddr_l_1_cry_2_2316), + .DI(com_tlm_u_tlm_tx_vc0_buf_pool_GND_2320), + .LO(com_tlm_u_tlm_tx_vc0_buf_pool_waddr_l_1_cry_3_2317), + .S(com_tlm_u_tlm_tx_vc0_buf_pool_waddr_l_1_axb_3_2329) + ); + XORCY com_tlm_u_tlm_tx_vc0_buf_pool_waddr_l_1_s_3 ( + .CI(com_tlm_u_tlm_tx_vc0_buf_pool_waddr_l_1_cry_2_2316), + .LI(com_tlm_u_tlm_tx_vc0_buf_pool_waddr_l_1_axb_3_2329), + .O(com_tlm_u_tlm_tx_vc0_buf_pool_waddr_l_1[3]) + ); + MUXCY_L com_tlm_u_tlm_tx_vc0_buf_pool_waddr_l_1_cry_4 ( + .CI(com_tlm_u_tlm_tx_vc0_buf_pool_waddr_l_1_cry_3_2317), + .DI(com_tlm_u_tlm_tx_vc0_buf_pool_GND_2320), + .LO(com_tlm_u_tlm_tx_vc0_buf_pool_waddr_l_1_cry_4_2318), + .S(com_tlm_u_tlm_tx_vc0_buf_pool_waddr_l_1_axb_4_2328) + ); + XORCY com_tlm_u_tlm_tx_vc0_buf_pool_waddr_l_1_s_4 ( + .CI(com_tlm_u_tlm_tx_vc0_buf_pool_waddr_l_1_cry_3_2317), + .LI(com_tlm_u_tlm_tx_vc0_buf_pool_waddr_l_1_axb_4_2328), + .O(com_tlm_u_tlm_tx_vc0_buf_pool_waddr_l_1[4]) + ); + MUXCY_L com_tlm_u_tlm_tx_vc0_buf_pool_waddr_l_1_cry_5 ( + .CI(com_tlm_u_tlm_tx_vc0_buf_pool_waddr_l_1_cry_4_2318), + .DI(com_tlm_u_tlm_tx_vc0_buf_pool_GND_2320), + .LO(com_tlm_u_tlm_tx_vc0_buf_pool_waddr_l_1_cry_5_2319), + .S(com_tlm_u_tlm_tx_vc0_buf_pool_waddr_l_1_axb_5_2327) + ); + XORCY com_tlm_u_tlm_tx_vc0_buf_pool_waddr_l_1_s_5 ( + .CI(com_tlm_u_tlm_tx_vc0_buf_pool_waddr_l_1_cry_4_2318), + .LI(com_tlm_u_tlm_tx_vc0_buf_pool_waddr_l_1_axb_5_2327), + .O(com_tlm_u_tlm_tx_vc0_buf_pool_waddr_l_1[5]) + ); + XORCY com_tlm_u_tlm_tx_vc0_buf_pool_waddr_l_1_s_6 ( + .CI(com_tlm_u_tlm_tx_vc0_buf_pool_waddr_l_1_cry_5_2319), + .LI(com_tlm_u_tlm_tx_vc0_buf_pool_waddr_l_1_axb_6_2326), + .O(com_tlm_u_tlm_tx_vc0_buf_pool_waddr_l_1[6]) + ); + FDRE com_tlm_u_tlm_tx_vc0_buf_pool_raddr_l_0_ ( + .CE(com_tlm_u_tlm_tx_vc0_buf_pool_en_ram_i_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_buf_pool_raddr_l_s[0]), + .Q(com_tlm_u_tlm_tx_vc0_buf_pool_raddr_l[0]), + .R(com_tlm_u_tlm_tx_vc0_nxt_seq_state_0_sqmuxa_i_o2_i_a2) + ); + MUXCY_L com_tlm_u_tlm_tx_vc0_buf_pool_raddr_l_cry_1_ ( + .CI(com_tlm_u_tlm_tx_vc0_buf_pool_raddr_l[0]), + .DI(com_tlm_u_tlm_tx_vc0_buf_pool_GND_2320), + .LO(com_tlm_u_tlm_tx_vc0_buf_pool_raddr_l_cry[1]), + .S(com_tlm_u_tlm_tx_vc0_buf_pool_raddr_l_qxu[1]) + ); + XORCY com_tlm_u_tlm_tx_vc0_buf_pool_raddr_l_s_1_ ( + .CI(com_tlm_u_tlm_tx_vc0_buf_pool_raddr_l[0]), + .LI(com_tlm_u_tlm_tx_vc0_buf_pool_raddr_l_qxu[1]), + .O(com_tlm_u_tlm_tx_vc0_buf_pool_raddr_l_s[1]) + ); + FDRE com_tlm_u_tlm_tx_vc0_buf_pool_raddr_l_1_ ( + .CE(com_tlm_u_tlm_tx_vc0_buf_pool_en_ram_i_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_buf_pool_raddr_l_s[1]), + .Q(com_tlm_u_tlm_tx_vc0_buf_pool_raddr_l[1]), + .R(com_tlm_u_tlm_tx_vc0_nxt_seq_state_0_sqmuxa_i_o2_i_a2) + ); + MUXCY_L com_tlm_u_tlm_tx_vc0_buf_pool_raddr_l_cry_2_ ( + .CI(com_tlm_u_tlm_tx_vc0_buf_pool_raddr_l_cry[1]), + .DI(com_tlm_u_tlm_tx_vc0_buf_pool_GND_2320), + .LO(com_tlm_u_tlm_tx_vc0_buf_pool_raddr_l_cry[2]), + .S(com_tlm_u_tlm_tx_vc0_buf_pool_raddr_l_qxu[2]) + ); + XORCY com_tlm_u_tlm_tx_vc0_buf_pool_raddr_l_s_2_ ( + .CI(com_tlm_u_tlm_tx_vc0_buf_pool_raddr_l_cry[1]), + .LI(com_tlm_u_tlm_tx_vc0_buf_pool_raddr_l_qxu[2]), + .O(com_tlm_u_tlm_tx_vc0_buf_pool_raddr_l_s[2]) + ); + FDRE com_tlm_u_tlm_tx_vc0_buf_pool_raddr_l_2_ ( + .CE(com_tlm_u_tlm_tx_vc0_buf_pool_en_ram_i_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_buf_pool_raddr_l_s[2]), + .Q(com_tlm_u_tlm_tx_vc0_buf_pool_raddr_l[2]), + .R(com_tlm_u_tlm_tx_vc0_nxt_seq_state_0_sqmuxa_i_o2_i_a2) + ); + MUXCY_L com_tlm_u_tlm_tx_vc0_buf_pool_raddr_l_cry_3_ ( + .CI(com_tlm_u_tlm_tx_vc0_buf_pool_raddr_l_cry[2]), + .DI(com_tlm_u_tlm_tx_vc0_buf_pool_GND_2320), + .LO(com_tlm_u_tlm_tx_vc0_buf_pool_raddr_l_cry[3]), + .S(com_tlm_u_tlm_tx_vc0_buf_pool_raddr_l_qxu[3]) + ); + XORCY com_tlm_u_tlm_tx_vc0_buf_pool_raddr_l_s_3_ ( + .CI(com_tlm_u_tlm_tx_vc0_buf_pool_raddr_l_cry[2]), + .LI(com_tlm_u_tlm_tx_vc0_buf_pool_raddr_l_qxu[3]), + .O(com_tlm_u_tlm_tx_vc0_buf_pool_raddr_l_s[3]) + ); + FDRE com_tlm_u_tlm_tx_vc0_buf_pool_raddr_l_3_ ( + .CE(com_tlm_u_tlm_tx_vc0_buf_pool_en_ram_i_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_buf_pool_raddr_l_s[3]), + .Q(com_tlm_u_tlm_tx_vc0_buf_pool_raddr_l[3]), + .R(com_tlm_u_tlm_tx_vc0_nxt_seq_state_0_sqmuxa_i_o2_i_a2) + ); + MUXCY_L com_tlm_u_tlm_tx_vc0_buf_pool_raddr_l_cry_4_ ( + .CI(com_tlm_u_tlm_tx_vc0_buf_pool_raddr_l_cry[3]), + .DI(com_tlm_u_tlm_tx_vc0_buf_pool_GND_2320), + .LO(com_tlm_u_tlm_tx_vc0_buf_pool_raddr_l_cry[4]), + .S(com_tlm_u_tlm_tx_vc0_buf_pool_raddr_l_qxu[4]) + ); + XORCY com_tlm_u_tlm_tx_vc0_buf_pool_raddr_l_s_4_ ( + .CI(com_tlm_u_tlm_tx_vc0_buf_pool_raddr_l_cry[3]), + .LI(com_tlm_u_tlm_tx_vc0_buf_pool_raddr_l_qxu[4]), + .O(com_tlm_u_tlm_tx_vc0_buf_pool_raddr_l_s[4]) + ); + FDRE com_tlm_u_tlm_tx_vc0_buf_pool_raddr_l_4_ ( + .CE(com_tlm_u_tlm_tx_vc0_buf_pool_en_ram_i_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_buf_pool_raddr_l_s[4]), + .Q(com_tlm_u_tlm_tx_vc0_buf_pool_raddr_l[4]), + .R(com_tlm_u_tlm_tx_vc0_nxt_seq_state_0_sqmuxa_i_o2_i_a2) + ); + MUXCY_L com_tlm_u_tlm_tx_vc0_buf_pool_raddr_l_cry_5_ ( + .CI(com_tlm_u_tlm_tx_vc0_buf_pool_raddr_l_cry[4]), + .DI(com_tlm_u_tlm_tx_vc0_buf_pool_GND_2320), + .LO(com_tlm_u_tlm_tx_vc0_buf_pool_raddr_l_cry[5]), + .S(com_tlm_u_tlm_tx_vc0_buf_pool_raddr_l_qxu[5]) + ); + XORCY com_tlm_u_tlm_tx_vc0_buf_pool_raddr_l_s_5_ ( + .CI(com_tlm_u_tlm_tx_vc0_buf_pool_raddr_l_cry[4]), + .LI(com_tlm_u_tlm_tx_vc0_buf_pool_raddr_l_qxu[5]), + .O(com_tlm_u_tlm_tx_vc0_buf_pool_raddr_l_s[5]) + ); + FDRE com_tlm_u_tlm_tx_vc0_buf_pool_raddr_l_5_ ( + .CE(com_tlm_u_tlm_tx_vc0_buf_pool_en_ram_i_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_buf_pool_raddr_l_s[5]), + .Q(com_tlm_u_tlm_tx_vc0_buf_pool_raddr_l[5]), + .R(com_tlm_u_tlm_tx_vc0_nxt_seq_state_0_sqmuxa_i_o2_i_a2) + ); + XORCY com_tlm_u_tlm_tx_vc0_buf_pool_raddr_l_s_6_ ( + .CI(com_tlm_u_tlm_tx_vc0_buf_pool_raddr_l_cry[5]), + .LI(com_tlm_u_tlm_tx_vc0_buf_pool_raddr_l_qxu[6]), + .O(com_tlm_u_tlm_tx_vc0_buf_pool_raddr_l_s[6]) + ); + FDRE com_tlm_u_tlm_tx_vc0_buf_pool_raddr_l_6_ ( + .CE(com_tlm_u_tlm_tx_vc0_buf_pool_en_ram_i_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_buf_pool_raddr_l_s[6]), + .Q(com_tlm_u_tlm_tx_vc0_buf_pool_raddr_l[6]), + .R(com_tlm_u_tlm_tx_vc0_nxt_seq_state_0_sqmuxa_i_o2_i_a2) + ); + FDR com_tlm_u_tlm_tx_vc0_buf_pool_start_xfer_q ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_nxt_seq_state_0_sqmuxa_i_o2_i_a2), + .Q(com_tlm_u_tlm_tx_vc0_buf_pool_start_xfer_q_2321), + .R(plm_link_up_i) + ); + defparam com_tlm_u_tlm_tx_vc0_buf_pool_rdata_q_all_5_0_a2_67_.INIT = 4'h8; + LUT2 com_tlm_u_tlm_tx_vc0_buf_pool_rdata_q_all_5_0_a2_67_ ( + .I0(com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all[67]), + .I1(com_tlm_u_tlm_tx_vc0_buf_pool_rvld_any_2332), + .O(com_tlm_u_tlm_tx_vc0_rdata_q_all_5[67]) + ); + defparam com_tlm_u_tlm_tx_vc0_buf_pool_rdata_sof_d_0_a2.INIT = 4'h1; + LUT2 com_tlm_u_tlm_tx_vc0_buf_pool_rdata_sof_d_0_a2 ( + .I0(com_tlm_u_tlm_tx_vc0_buf_pool_rdata_sof_d_hold_2322), + .I1(com_tlm_u_tlm_tx_vc0_buf_pool_start_xfer_q_2321), + .O(com_tlm_u_tlm_tx_vc0_buf_pool_rdata_sof_d_0_a2_2405) + ); + defparam com_tlm_u_tlm_tx_vc0_buf_pool_en_retry_d_i_o2.INIT = 4'h8; + LUT2 com_tlm_u_tlm_tx_vc0_buf_pool_en_retry_d_i_o2 ( + .I0(com_lnk_tdst_rdy_n), + .I1(com_tlm_u_tlm_tx_vc0_src_rdy), + .O(com_tlm_u_tlm_tx_vc0_N_17214_i) + ); + defparam com_tlm_u_tlm_tx_vc0_buf_pool_en_qq_0_a2.INIT = 4'h4; + LUT2 com_tlm_u_tlm_tx_vc0_buf_pool_en_qq_0_a2 ( + .I0(com_lnk_tdst_rdy_n), + .I1(com_tlm_u_tlm_tx_vc0_src_rdy), + .O(com_tlm_u_tlm_tx_en_qq) + ); + defparam com_tlm_u_tlm_tx_vc0_buf_pool_en_retry_d_i.INIT = 4'h4; + LUT2 com_tlm_u_tlm_tx_vc0_buf_pool_en_retry_d_i ( + .I0(com_tlm_u_tlm_tx_vc0_N_17214_i), + .I1(com_tlm_u_tlm_tx_vc0_buf_pool_rdata_sof_2323), + .O(com_tlm_u_tlm_tx_vc0_buf_pool_N_17122_i) + ); + defparam com_tlm_u_tlm_tx_vc0_buf_pool_wen_any_i_0_o2.INIT = 8'hC8; + LUT3 com_tlm_u_tlm_tx_vc0_buf_pool_wen_any_i_0_o2 ( + .I0(com_tlm_u_tlm_tx_vc0_buf_pool_wdata_65__2336), + .I1(com_tlm_u_tlm_tx_vc0_buf_pool_wdata_vld_any_2324), + .I2(com_tlm_u_tlm_tx_vc0_trn_vld), + .O(com_tlm_u_tlm_tx_vc0_buf_pool_N_22095_i) + ); + defparam com_tlm_u_tlm_tx_vc0_buf_pool_errfwd_wen_0_sqmuxa_i.INIT = 8'hE0; + LUT3 com_tlm_u_tlm_tx_vc0_buf_pool_errfwd_wen_0_sqmuxa_i ( + .I0(com_tlm_u_tlm_tx_vc0_trn_errfwd), + .I1(com_tlm_u_tlm_tx_vc0_trn_sof), + .I2(com_tlm_u_tlm_tx_vc0_trn_vld), + .O(com_tlm_u_tlm_tx_vc0_buf_pool_N_22083_i) + ); + defparam com_tlm_u_tlm_tx_vc0_buf_pool_write_rem_N_22106_i.INIT = 8'hFB; + LUT3 com_tlm_u_tlm_tx_vc0_buf_pool_write_rem_N_22106_i ( + .I0(com_tlm_u_tlm_tx_vc0_buf_pool_wdata_65__2336), + .I1(com_tlm_u_tlm_tx_vc0_buf_pool_wdata_vld_any_2324), + .I2(com_tlm_u_tlm_tx_vc0_trn_vld), + .O(com_tlm_u_tlm_tx_vc0_buf_pool_N_22106_i) + ); + defparam com_tlm_u_tlm_tx_vc0_buf_pool_un2_start_dst_rdy_o_i_0.INIT = 8'h40; + LUT3 com_tlm_u_tlm_tx_vc0_buf_pool_un2_start_dst_rdy_o_i_0 ( + .I0(com_tlm_u_tlm_tx_vc0_N_17214_i), + .I1(com_tlm_u_tlm_tx_vc0_in_frame), + .I2(com_tlm_u_tlm_tx_vc0_rdata_q_all_5[67]), + .O(com_tlm_u_tlm_tx_vc0_buf_pool_N_17124_i) + ); + defparam com_tlm_u_tlm_tx_vc0_buf_pool_en_ram_i_0_o2.INIT = 8'h4C; + LUT3 com_tlm_u_tlm_tx_vc0_buf_pool_en_ram_i_0_o2 ( + .I0(com_tlm_u_tlm_tx_vc0_N_17214_i), + .I1(com_tlm_u_tlm_tx_vc0_in_frame), + .I2(com_tlm_u_tlm_tx_vc0_buf_pool_rvld_any_2332), + .O(com_tlm_u_tlm_tx_vc0_buf_pool_en_ram_i_i) + ); + defparam com_tlm_u_tlm_tx_vc0_buf_pool_N_22107_i.INIT = 4'hE; + LUT2 com_tlm_u_tlm_tx_vc0_buf_pool_N_22107_i ( + .I0(com_tlm_u_tlm_tx_vc0_buf_pool_N_22095_i), + .I1(com_tlm_u_tlm_tx_vc0_trn_sof), + .O(com_tlm_u_tlm_tx_vc0_buf_pool_N_22107_i_2333) + ); + defparam com_tlm_u_tlm_tx_vc0_buf_pool_retry_dd_0_sqmuxa_i.INIT = 4'h8; + LUT2 com_tlm_u_tlm_tx_vc0_buf_pool_retry_dd_0_sqmuxa_i ( + .I0(com_tlm_u_tlm_tx_vc0_nxt_seq_state_0_sqmuxa_i_o2_i_a2), + .I1(plm_link_up_1), + .O(com_tlm_u_tlm_tx_vc0_buf_pool_N_17127_i) + ); + defparam com_tlm_u_tlm_tx_vc0_buf_pool_N_69239_i.INIT = 16'hDC50; + LUT4 com_tlm_u_tlm_tx_vc0_buf_pool_N_69239_i ( + .I0(com_tlm_u_tlm_tx_vc0_buf_pool_rdata_sof_d_0_a2_2405), + .I1(com_tlm_u_tlm_tx_en_qq), + .I2(com_tlm_u_tlm_tx_vc0_buf_pool_en_ram_i_i), + .I3(com_tlm_u_tlm_tx_vc0_buf_pool_rdata_q_all[67]), + .O(com_tlm_u_tlm_tx_vc0_buf_pool_N_69239_i_2325) + ); + defparam com_tlm_u_tlm_tx_vc0_buf_pool_raddr_h_0_0_3_.INIT = 8'hE4; + LUT3_L com_tlm_u_tlm_tx_vc0_buf_pool_raddr_h_0_0_3_ ( + .I0(com_tlm_u_tlm_tx_vc0_nxt_seq_state_0_sqmuxa_i_o2_i_a2), + .I1(com_tlm_u_tlm_tx_vc0_buf_pool_raddr_h[3]), + .I2(com_tlm_u_tlm_tx_vc0_start_buf_num[3]), + .LO(com_tlm_u_tlm_tx_vc0_buf_pool_raddr_h_0_0[3]) + ); + defparam com_tlm_u_tlm_tx_vc0_buf_pool_raddr_h_0_0_2_.INIT = 8'hE4; + LUT3_L com_tlm_u_tlm_tx_vc0_buf_pool_raddr_h_0_0_2_ ( + .I0(com_tlm_u_tlm_tx_vc0_nxt_seq_state_0_sqmuxa_i_o2_i_a2), + .I1(com_tlm_u_tlm_tx_vc0_buf_pool_raddr_h[2]), + .I2(com_tlm_u_tlm_tx_vc0_start_buf_num[2]), + .LO(com_tlm_u_tlm_tx_vc0_buf_pool_raddr_h_0_0[2]) + ); + defparam com_tlm_u_tlm_tx_vc0_buf_pool_raddr_h_0_0_1_.INIT = 8'hE4; + LUT3_L com_tlm_u_tlm_tx_vc0_buf_pool_raddr_h_0_0_1_ ( + .I0(com_tlm_u_tlm_tx_vc0_nxt_seq_state_0_sqmuxa_i_o2_i_a2), + .I1(com_tlm_u_tlm_tx_vc0_buf_pool_raddr_h[1]), + .I2(com_tlm_u_tlm_tx_vc0_start_buf_num[1]), + .LO(com_tlm_u_tlm_tx_vc0_buf_pool_raddr_h_0_0[1]) + ); + defparam com_tlm_u_tlm_tx_vc0_buf_pool_raddr_h_0_0_0_.INIT = 8'hE4; + LUT3_L com_tlm_u_tlm_tx_vc0_buf_pool_raddr_h_0_0_0_ ( + .I0(com_tlm_u_tlm_tx_vc0_nxt_seq_state_0_sqmuxa_i_o2_i_a2), + .I1(com_tlm_u_tlm_tx_vc0_buf_pool_raddr_h[0]), + .I2(com_tlm_u_tlm_tx_vc0_start_buf_num[0]), + .LO(com_tlm_u_tlm_tx_vc0_buf_pool_raddr_h_0_0[0]) + ); + defparam com_tlm_u_tlm_tx_vc0_buf_pool_waddr_h_0_0_3_.INIT = 8'hCA; + LUT3_L com_tlm_u_tlm_tx_vc0_buf_pool_waddr_h_0_0_3_ ( + .I0(com_tlm_u_tlm_tx_vc0_buf_pool_waddr_h[3]), + .I1(com_tlm_u_tlm_tx_vc0_tkn_buf_num[3]), + .I2(com_tlm_u_tlm_tx_vc0_trn_sof), + .LO(com_tlm_u_tlm_tx_vc0_buf_pool_waddr_h_0_0[3]) + ); + defparam com_tlm_u_tlm_tx_vc0_buf_pool_waddr_h_0_0_2_.INIT = 8'hCA; + LUT3_L com_tlm_u_tlm_tx_vc0_buf_pool_waddr_h_0_0_2_ ( + .I0(com_tlm_u_tlm_tx_vc0_buf_pool_waddr_h[2]), + .I1(com_tlm_u_tlm_tx_vc0_tkn_buf_num[2]), + .I2(com_tlm_u_tlm_tx_vc0_trn_sof), + .LO(com_tlm_u_tlm_tx_vc0_buf_pool_waddr_h_0_0[2]) + ); + defparam com_tlm_u_tlm_tx_vc0_buf_pool_waddr_h_0_0_1_.INIT = 8'hCA; + LUT3_L com_tlm_u_tlm_tx_vc0_buf_pool_waddr_h_0_0_1_ ( + .I0(com_tlm_u_tlm_tx_vc0_buf_pool_waddr_h[1]), + .I1(com_tlm_u_tlm_tx_vc0_tkn_buf_num[1]), + .I2(com_tlm_u_tlm_tx_vc0_trn_sof), + .LO(com_tlm_u_tlm_tx_vc0_buf_pool_waddr_h_0_0[1]) + ); + defparam com_tlm_u_tlm_tx_vc0_buf_pool_waddr_h_0_0_0_.INIT = 8'hCA; + LUT3_L com_tlm_u_tlm_tx_vc0_buf_pool_waddr_h_0_0_0_ ( + .I0(com_tlm_u_tlm_tx_vc0_buf_pool_waddr_h[0]), + .I1(com_tlm_u_tlm_tx_vc0_tkn_buf_num[0]), + .I2(com_tlm_u_tlm_tx_vc0_trn_sof), + .LO(com_tlm_u_tlm_tx_vc0_buf_pool_waddr_h_0_0[0]) + ); + defparam com_tlm_u_tlm_tx_vc0_buf_pool_waddr_l_1_axb_6.INIT = 4'hE; + LUT2_L com_tlm_u_tlm_tx_vc0_buf_pool_waddr_l_1_axb_6 ( + .I0(com_tlm_u_tlm_tx_vc0_buf_pool_waddr_l[6]), + .I1(com_tlm_u_tlm_tx_vc0_trn_sof), + .LO(com_tlm_u_tlm_tx_vc0_buf_pool_waddr_l_1_axb_6_2326) + ); + defparam com_tlm_u_tlm_tx_vc0_buf_pool_waddr_l_1_axb_5.INIT = 4'hE; + LUT2_L com_tlm_u_tlm_tx_vc0_buf_pool_waddr_l_1_axb_5 ( + .I0(com_tlm_u_tlm_tx_vc0_buf_pool_waddr_l[5]), + .I1(com_tlm_u_tlm_tx_vc0_trn_sof), + .LO(com_tlm_u_tlm_tx_vc0_buf_pool_waddr_l_1_axb_5_2327) + ); + defparam com_tlm_u_tlm_tx_vc0_buf_pool_waddr_l_1_axb_4.INIT = 4'hE; + LUT2_L com_tlm_u_tlm_tx_vc0_buf_pool_waddr_l_1_axb_4 ( + .I0(com_tlm_u_tlm_tx_vc0_buf_pool_waddr_l[4]), + .I1(com_tlm_u_tlm_tx_vc0_trn_sof), + .LO(com_tlm_u_tlm_tx_vc0_buf_pool_waddr_l_1_axb_4_2328) + ); + defparam com_tlm_u_tlm_tx_vc0_buf_pool_waddr_l_1_axb_3.INIT = 4'hE; + LUT2_L com_tlm_u_tlm_tx_vc0_buf_pool_waddr_l_1_axb_3 ( + .I0(com_tlm_u_tlm_tx_vc0_buf_pool_waddr_l[3]), + .I1(com_tlm_u_tlm_tx_vc0_trn_sof), + .LO(com_tlm_u_tlm_tx_vc0_buf_pool_waddr_l_1_axb_3_2329) + ); + defparam com_tlm_u_tlm_tx_vc0_buf_pool_waddr_l_1_axb_2.INIT = 4'hE; + LUT2_L com_tlm_u_tlm_tx_vc0_buf_pool_waddr_l_1_axb_2 ( + .I0(com_tlm_u_tlm_tx_vc0_buf_pool_waddr_l[2]), + .I1(com_tlm_u_tlm_tx_vc0_trn_sof), + .LO(com_tlm_u_tlm_tx_vc0_buf_pool_waddr_l_1_axb_2_2330) + ); + defparam com_tlm_u_tlm_tx_vc0_buf_pool_waddr_l_1_axb_1.INIT = 4'hE; + LUT2_L com_tlm_u_tlm_tx_vc0_buf_pool_waddr_l_1_axb_1 ( + .I0(com_tlm_u_tlm_tx_vc0_buf_pool_waddr_l[1]), + .I1(com_tlm_u_tlm_tx_vc0_trn_sof), + .LO(com_tlm_u_tlm_tx_vc0_buf_pool_waddr_l_1_axb_1_2331) + ); + defparam com_tlm_u_tlm_tx_vc0_buf_pool_rdata_q_all_5_0_a2_68_.INIT = 4'h8; + LUT2_L com_tlm_u_tlm_tx_vc0_buf_pool_rdata_q_all_5_0_a2_68_ ( + .I0(com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all[68]), + .I1(com_tlm_u_tlm_tx_vc0_buf_pool_rvld_any_2332), + .LO(com_tlm_u_tlm_tx_vc0_buf_pool_rdata_q_all_5_68_) + ); + defparam com_tlm_u_tlm_tx_vc0_buf_pool_rdata_q_all_5_0_a2_66_.INIT = 4'h8; + LUT2_L com_tlm_u_tlm_tx_vc0_buf_pool_rdata_q_all_5_0_a2_66_ ( + .I0(com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all[66]), + .I1(com_tlm_u_tlm_tx_vc0_buf_pool_rvld_any_2332), + .LO(com_tlm_u_tlm_tx_vc0_buf_pool_rdata_q_all_5_66_) + ); + defparam com_tlm_u_tlm_tx_vc0_buf_pool_rdata_q_all_5_0_a2_65_.INIT = 4'h8; + LUT2_L com_tlm_u_tlm_tx_vc0_buf_pool_rdata_q_all_5_0_a2_65_ ( + .I0(com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all[65]), + .I1(com_tlm_u_tlm_tx_vc0_buf_pool_rvld_any_2332), + .LO(com_tlm_u_tlm_tx_vc0_buf_pool_rdata_q_all_5_65_) + ); + defparam com_tlm_u_tlm_tx_vc0_buf_pool_rdata_q_all_5_0_a2_64_.INIT = 4'h8; + LUT2_L com_tlm_u_tlm_tx_vc0_buf_pool_rdata_q_all_5_0_a2_64_ ( + .I0(com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all[64]), + .I1(com_tlm_u_tlm_tx_vc0_buf_pool_rvld_any_2332), + .LO(com_tlm_u_tlm_tx_vc0_buf_pool_rdata_q_all_5_64_) + ); + defparam com_tlm_u_tlm_tx_vc0_buf_pool_N_68303_i.INIT = 8'hCE; + LUT3_L com_tlm_u_tlm_tx_vc0_buf_pool_N_68303_i ( + .I0(com_tlm_u_tlm_tx_vc0_buf_pool_wdata_errfwd_2403), + .I1(com_tlm_u_tlm_tx_vc0_trn_errfwd), + .I2(com_tlm_u_tlm_tx_vc0_trn_sof), + .LO(com_tlm_u_tlm_tx_vc0_buf_pool_N_68303_i_2402) + ); + defparam com_tlm_u_tlm_tx_vc0_buf_pool_rdata_sof_d_hold_3_0_a2.INIT = 4'h1; + LUT2_L com_tlm_u_tlm_tx_vc0_buf_pool_rdata_sof_d_hold_3_0_a2 ( + .I0(com_tlm_u_tlm_tx_vc0_buf_pool_rdata_sof_d_0_a2_2405), + .I1(com_tlm_u_tlm_tx_vc0_buf_pool_en_ram_i_i), + .LO(com_tlm_u_tlm_tx_vc0_buf_pool_rdata_sof_d_hold_3) + ); + FD com_tlm_u_tlm_tx_vc0_buf_pool_rdata_errfwd ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_buf_pool_errfwd), + .Q(com_tlm_u_tlm_tx_vc0_buf_pool_rdata_errfwd_2334) + ); + FD com_tlm_u_tlm_tx_vc0_buf_pool_raddr_h_3_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_buf_pool_raddr_h_0_0[3]), + .Q(com_tlm_u_tlm_tx_vc0_buf_pool_raddr_h[3]) + ); + FD com_tlm_u_tlm_tx_vc0_buf_pool_raddr_h_2_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_buf_pool_raddr_h_0_0[2]), + .Q(com_tlm_u_tlm_tx_vc0_buf_pool_raddr_h[2]) + ); + FD com_tlm_u_tlm_tx_vc0_buf_pool_raddr_h_1_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_buf_pool_raddr_h_0_0[1]), + .Q(com_tlm_u_tlm_tx_vc0_buf_pool_raddr_h[1]) + ); + FD com_tlm_u_tlm_tx_vc0_buf_pool_raddr_h_0_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_buf_pool_raddr_h_0_0[0]), + .Q(com_tlm_u_tlm_tx_vc0_buf_pool_raddr_h[0]) + ); + FD com_tlm_u_tlm_tx_vc0_buf_pool_waddr_h_3_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_buf_pool_waddr_h_0_0[3]), + .Q(com_tlm_u_tlm_tx_vc0_buf_pool_waddr_h[3]) + ); + FD com_tlm_u_tlm_tx_vc0_buf_pool_waddr_h_2_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_buf_pool_waddr_h_0_0[2]), + .Q(com_tlm_u_tlm_tx_vc0_buf_pool_waddr_h[2]) + ); + FD com_tlm_u_tlm_tx_vc0_buf_pool_waddr_h_1_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_buf_pool_waddr_h_0_0[1]), + .Q(com_tlm_u_tlm_tx_vc0_buf_pool_waddr_h[1]) + ); + FD com_tlm_u_tlm_tx_vc0_buf_pool_waddr_h_0_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_buf_pool_waddr_h_0_0[0]), + .Q(com_tlm_u_tlm_tx_vc0_buf_pool_waddr_h[0]) + ); + FDE com_tlm_u_tlm_tx_vc0_buf_pool_waddr_l_6_ ( + .CE(com_tlm_u_tlm_tx_vc0_buf_pool_N_22107_i_2333), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_buf_pool_waddr_l_1[6]), + .Q(com_tlm_u_tlm_tx_vc0_buf_pool_waddr_l[6]) + ); + FDE com_tlm_u_tlm_tx_vc0_buf_pool_waddr_l_5_ ( + .CE(com_tlm_u_tlm_tx_vc0_buf_pool_N_22107_i_2333), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_buf_pool_waddr_l_1[5]), + .Q(com_tlm_u_tlm_tx_vc0_buf_pool_waddr_l[5]) + ); + FDE com_tlm_u_tlm_tx_vc0_buf_pool_waddr_l_4_ ( + .CE(com_tlm_u_tlm_tx_vc0_buf_pool_N_22107_i_2333), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_buf_pool_waddr_l_1[4]), + .Q(com_tlm_u_tlm_tx_vc0_buf_pool_waddr_l[4]) + ); + FDE com_tlm_u_tlm_tx_vc0_buf_pool_waddr_l_3_ ( + .CE(com_tlm_u_tlm_tx_vc0_buf_pool_N_22107_i_2333), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_buf_pool_waddr_l_1[3]), + .Q(com_tlm_u_tlm_tx_vc0_buf_pool_waddr_l[3]) + ); + FDE com_tlm_u_tlm_tx_vc0_buf_pool_waddr_l_2_ ( + .CE(com_tlm_u_tlm_tx_vc0_buf_pool_N_22107_i_2333), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_buf_pool_waddr_l_1[2]), + .Q(com_tlm_u_tlm_tx_vc0_buf_pool_waddr_l[2]) + ); + FDE com_tlm_u_tlm_tx_vc0_buf_pool_waddr_l_1_ ( + .CE(com_tlm_u_tlm_tx_vc0_buf_pool_N_22107_i_2333), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_buf_pool_waddr_l_1[1]), + .Q(com_tlm_u_tlm_tx_vc0_buf_pool_waddr_l[1]) + ); + FDE com_tlm_u_tlm_tx_vc0_buf_pool_waddr_l_0_ ( + .CE(com_tlm_u_tlm_tx_vc0_buf_pool_N_22107_i_2333), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_buf_pool_waddr_l_1[0]), + .Q(com_tlm_u_tlm_tx_vc0_buf_pool_waddr_l[0]) + ); + FDE com_tlm_u_tlm_tx_vc0_buf_pool_rdata_reg_0__rdata_q_all_63_ ( + .CE(com_tlm_u_tlm_tx_vc0_buf_pool_N_17214_i_i_2406), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all[63]), + .Q(com_tlm_u_tlm_tx_vc0_d[63]) + ); + FDE com_tlm_u_tlm_tx_vc0_buf_pool_rdata_reg_0__rdata_q_all_62_ ( + .CE(com_tlm_u_tlm_tx_vc0_buf_pool_N_17214_i_i_2406), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all[62]), + .Q(com_tlm_u_tlm_tx_vc0_d[62]) + ); + FDE com_tlm_u_tlm_tx_vc0_buf_pool_rdata_reg_0__rdata_q_all_61_ ( + .CE(com_tlm_u_tlm_tx_vc0_buf_pool_N_17214_i_i_2406), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all[61]), + .Q(com_tlm_u_tlm_tx_vc0_d[61]) + ); + FDE com_tlm_u_tlm_tx_vc0_buf_pool_rdata_reg_0__rdata_q_all_60_ ( + .CE(com_tlm_u_tlm_tx_vc0_buf_pool_N_17214_i_i_2406), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all[60]), + .Q(com_tlm_u_tlm_tx_vc0_d[60]) + ); + FDE com_tlm_u_tlm_tx_vc0_buf_pool_rdata_reg_0__rdata_q_all_59_ ( + .CE(com_tlm_u_tlm_tx_vc0_buf_pool_N_17214_i_i_2406), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all[59]), + .Q(com_tlm_u_tlm_tx_vc0_d[59]) + ); + FDE com_tlm_u_tlm_tx_vc0_buf_pool_rdata_reg_0__rdata_q_all_58_ ( + .CE(com_tlm_u_tlm_tx_vc0_buf_pool_N_17214_i_i_2406), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all[58]), + .Q(com_tlm_u_tlm_tx_vc0_d[58]) + ); + FDE com_tlm_u_tlm_tx_vc0_buf_pool_rdata_reg_0__rdata_q_all_57_ ( + .CE(com_tlm_u_tlm_tx_vc0_buf_pool_N_17214_i_i_2406), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all[57]), + .Q(com_tlm_u_tlm_tx_vc0_d[57]) + ); + FDE com_tlm_u_tlm_tx_vc0_buf_pool_rdata_reg_0__rdata_q_all_56_ ( + .CE(com_tlm_u_tlm_tx_vc0_buf_pool_N_17214_i_i_2406), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all[56]), + .Q(com_tlm_u_tlm_tx_vc0_d[56]) + ); + FDE com_tlm_u_tlm_tx_vc0_buf_pool_rdata_reg_0__rdata_q_all_55_ ( + .CE(com_tlm_u_tlm_tx_vc0_buf_pool_N_17214_i_i_2406), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all[55]), + .Q(com_tlm_u_tlm_tx_vc0_d[55]) + ); + FDE com_tlm_u_tlm_tx_vc0_buf_pool_rdata_reg_0__rdata_q_all_54_ ( + .CE(com_tlm_u_tlm_tx_vc0_buf_pool_N_17214_i_i_2406), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all[54]), + .Q(com_tlm_u_tlm_tx_vc0_d[54]) + ); + FDE com_tlm_u_tlm_tx_vc0_buf_pool_rdata_reg_0__rdata_q_all_53_ ( + .CE(com_tlm_u_tlm_tx_vc0_buf_pool_N_17214_i_i_2406), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all[53]), + .Q(com_tlm_u_tlm_tx_vc0_d[53]) + ); + FDE com_tlm_u_tlm_tx_vc0_buf_pool_rdata_reg_0__rdata_q_all_52_ ( + .CE(com_tlm_u_tlm_tx_vc0_buf_pool_N_17214_i_i_2406), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all[52]), + .Q(com_tlm_u_tlm_tx_vc0_d[52]) + ); + FDE com_tlm_u_tlm_tx_vc0_buf_pool_rdata_reg_0__rdata_q_all_51_ ( + .CE(com_tlm_u_tlm_tx_vc0_buf_pool_N_17214_i_i_2406), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all[51]), + .Q(com_tlm_u_tlm_tx_vc0_d[51]) + ); + FDE com_tlm_u_tlm_tx_vc0_buf_pool_rdata_reg_0__rdata_q_all_50_ ( + .CE(com_tlm_u_tlm_tx_vc0_buf_pool_N_17214_i_i_2406), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all[50]), + .Q(com_tlm_u_tlm_tx_vc0_d[50]) + ); + FDE com_tlm_u_tlm_tx_vc0_buf_pool_rdata_reg_0__rdata_q_all_49_ ( + .CE(com_tlm_u_tlm_tx_vc0_buf_pool_N_17214_i_i_2406), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all[49]), + .Q(com_tlm_u_tlm_tx_vc0_d[49]) + ); + FDE com_tlm_u_tlm_tx_vc0_buf_pool_rdata_reg_0__rdata_q_all_48_ ( + .CE(com_tlm_u_tlm_tx_vc0_buf_pool_N_17214_i_i_2406), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all[48]), + .Q(com_tlm_u_tlm_tx_vc0_d[48]) + ); + FDE com_tlm_u_tlm_tx_vc0_buf_pool_rdata_reg_0__rdata_q_all_47_ ( + .CE(com_tlm_u_tlm_tx_vc0_buf_pool_N_17214_i_i_2406), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all[47]), + .Q(com_tlm_u_tlm_tx_vc0_d[47]) + ); + FDE com_tlm_u_tlm_tx_vc0_buf_pool_rdata_reg_0__rdata_q_all_46_ ( + .CE(com_tlm_u_tlm_tx_vc0_buf_pool_N_17214_i_i_2406), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all[46]), + .Q(com_tlm_u_tlm_tx_vc0_d[46]) + ); + FDE com_tlm_u_tlm_tx_vc0_buf_pool_rdata_reg_0__rdata_q_all_45_ ( + .CE(com_tlm_u_tlm_tx_vc0_buf_pool_N_17214_i_i_2406), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all[45]), + .Q(com_tlm_u_tlm_tx_vc0_d[45]) + ); + FDE com_tlm_u_tlm_tx_vc0_buf_pool_rdata_reg_0__rdata_q_all_44_ ( + .CE(com_tlm_u_tlm_tx_vc0_buf_pool_N_17214_i_i_2406), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all[44]), + .Q(com_tlm_u_tlm_tx_vc0_d[44]) + ); + FDE com_tlm_u_tlm_tx_vc0_buf_pool_rdata_reg_0__rdata_q_all_43_ ( + .CE(com_tlm_u_tlm_tx_vc0_buf_pool_N_17214_i_i_2406), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all[43]), + .Q(com_tlm_u_tlm_tx_vc0_d[43]) + ); + FDE com_tlm_u_tlm_tx_vc0_buf_pool_rdata_reg_0__rdata_q_all_42_ ( + .CE(com_tlm_u_tlm_tx_vc0_buf_pool_N_17214_i_i_2406), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all[42]), + .Q(com_tlm_u_tlm_tx_vc0_d[42]) + ); + FDE com_tlm_u_tlm_tx_vc0_buf_pool_rdata_reg_0__rdata_q_all_41_ ( + .CE(com_tlm_u_tlm_tx_vc0_buf_pool_N_17214_i_i_2406), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all[41]), + .Q(com_tlm_u_tlm_tx_vc0_d[41]) + ); + FDE com_tlm_u_tlm_tx_vc0_buf_pool_rdata_reg_0__rdata_q_all_40_ ( + .CE(com_tlm_u_tlm_tx_vc0_buf_pool_N_17214_i_i_2406), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all[40]), + .Q(com_tlm_u_tlm_tx_vc0_d[40]) + ); + FDE com_tlm_u_tlm_tx_vc0_buf_pool_rdata_reg_0__rdata_q_all_39_ ( + .CE(com_tlm_u_tlm_tx_vc0_buf_pool_N_17214_i_i_2406), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all[39]), + .Q(com_tlm_u_tlm_tx_vc0_d[39]) + ); + FDE com_tlm_u_tlm_tx_vc0_buf_pool_rdata_reg_0__rdata_q_all_38_ ( + .CE(com_tlm_u_tlm_tx_vc0_buf_pool_N_17214_i_i_2406), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all[38]), + .Q(com_tlm_u_tlm_tx_vc0_d[38]) + ); + FDE com_tlm_u_tlm_tx_vc0_buf_pool_rdata_reg_0__rdata_q_all_37_ ( + .CE(com_tlm_u_tlm_tx_vc0_buf_pool_N_17214_i_i_2406), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all[37]), + .Q(com_tlm_u_tlm_tx_vc0_d[37]) + ); + FDE com_tlm_u_tlm_tx_vc0_buf_pool_rdata_reg_0__rdata_q_all_36_ ( + .CE(com_tlm_u_tlm_tx_vc0_buf_pool_N_17214_i_i_2406), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all[36]), + .Q(com_tlm_u_tlm_tx_vc0_d[36]) + ); + FDE com_tlm_u_tlm_tx_vc0_buf_pool_rdata_reg_0__rdata_q_all_35_ ( + .CE(com_tlm_u_tlm_tx_vc0_buf_pool_N_17214_i_i_2406), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all[35]), + .Q(com_tlm_u_tlm_tx_vc0_d[35]) + ); + FDE com_tlm_u_tlm_tx_vc0_buf_pool_rdata_reg_0__rdata_q_all_34_ ( + .CE(com_tlm_u_tlm_tx_vc0_buf_pool_N_17214_i_i_2406), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all[34]), + .Q(com_tlm_u_tlm_tx_vc0_d[34]) + ); + FDE com_tlm_u_tlm_tx_vc0_buf_pool_rdata_reg_0__rdata_q_all_33_ ( + .CE(com_tlm_u_tlm_tx_vc0_buf_pool_N_17214_i_i_2406), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all[33]), + .Q(com_tlm_u_tlm_tx_vc0_d[33]) + ); + FDE com_tlm_u_tlm_tx_vc0_buf_pool_rdata_reg_0__rdata_q_all_32_ ( + .CE(com_tlm_u_tlm_tx_vc0_buf_pool_N_17214_i_i_2406), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all[32]), + .Q(com_tlm_u_tlm_tx_vc0_d[32]) + ); + FDE com_tlm_u_tlm_tx_vc0_buf_pool_rdata_reg_0__rdata_q_all_31_ ( + .CE(com_tlm_u_tlm_tx_vc0_buf_pool_N_17214_i_i_2406), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all[31]), + .Q(com_tlm_u_tlm_tx_vc0_d[31]) + ); + FDE com_tlm_u_tlm_tx_vc0_buf_pool_rdata_reg_0__rdata_q_all_30_ ( + .CE(com_tlm_u_tlm_tx_vc0_buf_pool_N_17214_i_i_2406), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all[30]), + .Q(com_tlm_u_tlm_tx_vc0_d[30]) + ); + FDE com_tlm_u_tlm_tx_vc0_buf_pool_rdata_reg_0__rdata_q_all_29_ ( + .CE(com_tlm_u_tlm_tx_vc0_buf_pool_N_17214_i_i_2406), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all[29]), + .Q(com_tlm_u_tlm_tx_vc0_d[29]) + ); + FDE com_tlm_u_tlm_tx_vc0_buf_pool_rdata_reg_0__rdata_q_all_28_ ( + .CE(com_tlm_u_tlm_tx_vc0_buf_pool_N_17214_i_i_2406), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all[28]), + .Q(com_tlm_u_tlm_tx_vc0_d[28]) + ); + FDE com_tlm_u_tlm_tx_vc0_buf_pool_rdata_reg_0__rdata_q_all_27_ ( + .CE(com_tlm_u_tlm_tx_vc0_buf_pool_N_17214_i_i_2406), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all[27]), + .Q(com_tlm_u_tlm_tx_vc0_d[27]) + ); + FDE com_tlm_u_tlm_tx_vc0_buf_pool_rdata_reg_0__rdata_q_all_26_ ( + .CE(com_tlm_u_tlm_tx_vc0_buf_pool_N_17214_i_i_2406), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all[26]), + .Q(com_tlm_u_tlm_tx_vc0_d[26]) + ); + FDE com_tlm_u_tlm_tx_vc0_buf_pool_rdata_reg_0__rdata_q_all_25_ ( + .CE(com_tlm_u_tlm_tx_vc0_buf_pool_N_17214_i_i_2406), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all[25]), + .Q(com_tlm_u_tlm_tx_vc0_d[25]) + ); + FDE com_tlm_u_tlm_tx_vc0_buf_pool_rdata_reg_0__rdata_q_all_24_ ( + .CE(com_tlm_u_tlm_tx_vc0_buf_pool_N_17214_i_i_2406), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all[24]), + .Q(com_tlm_u_tlm_tx_vc0_d[24]) + ); + FDE com_tlm_u_tlm_tx_vc0_buf_pool_rdata_reg_0__rdata_q_all_23_ ( + .CE(com_tlm_u_tlm_tx_vc0_buf_pool_N_17214_i_i_2406), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all[23]), + .Q(com_tlm_u_tlm_tx_vc0_d[23]) + ); + FDE com_tlm_u_tlm_tx_vc0_buf_pool_rdata_reg_0__rdata_q_all_22_ ( + .CE(com_tlm_u_tlm_tx_vc0_buf_pool_N_17214_i_i_2406), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all[22]), + .Q(com_tlm_u_tlm_tx_vc0_d[22]) + ); + FDE com_tlm_u_tlm_tx_vc0_buf_pool_rdata_reg_0__rdata_q_all_21_ ( + .CE(com_tlm_u_tlm_tx_vc0_buf_pool_N_17214_i_i_2406), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all[21]), + .Q(com_tlm_u_tlm_tx_vc0_d[21]) + ); + FDE com_tlm_u_tlm_tx_vc0_buf_pool_rdata_reg_0__rdata_q_all_20_ ( + .CE(com_tlm_u_tlm_tx_vc0_buf_pool_N_17214_i_i_2406), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all[20]), + .Q(com_tlm_u_tlm_tx_vc0_d[20]) + ); + FDE com_tlm_u_tlm_tx_vc0_buf_pool_rdata_reg_0__rdata_q_all_19_ ( + .CE(com_tlm_u_tlm_tx_vc0_buf_pool_N_17214_i_i_2406), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all[19]), + .Q(com_tlm_u_tlm_tx_vc0_d[19]) + ); + FDE com_tlm_u_tlm_tx_vc0_buf_pool_rdata_reg_0__rdata_q_all_18_ ( + .CE(com_tlm_u_tlm_tx_vc0_buf_pool_N_17214_i_i_2406), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all[18]), + .Q(com_tlm_u_tlm_tx_vc0_d[18]) + ); + FDE com_tlm_u_tlm_tx_vc0_buf_pool_rdata_reg_0__rdata_q_all_17_ ( + .CE(com_tlm_u_tlm_tx_vc0_buf_pool_N_17214_i_i_2406), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all[17]), + .Q(com_tlm_u_tlm_tx_vc0_d[17]) + ); + FDE com_tlm_u_tlm_tx_vc0_buf_pool_rdata_reg_0__rdata_q_all_16_ ( + .CE(com_tlm_u_tlm_tx_vc0_buf_pool_N_17214_i_i_2406), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all[16]), + .Q(com_tlm_u_tlm_tx_vc0_d[16]) + ); + FDE com_tlm_u_tlm_tx_vc0_buf_pool_rdata_reg_0__rdata_q_all_15_ ( + .CE(com_tlm_u_tlm_tx_vc0_buf_pool_N_17214_i_i_2406), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all[15]), + .Q(com_tlm_u_tlm_tx_vc0_d[15]) + ); + FDE com_tlm_u_tlm_tx_vc0_buf_pool_rdata_reg_0__rdata_q_all_14_ ( + .CE(com_tlm_u_tlm_tx_vc0_buf_pool_N_17214_i_i_2406), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all[14]), + .Q(com_tlm_u_tlm_tx_vc0_d[14]) + ); + FDE com_tlm_u_tlm_tx_vc0_buf_pool_rdata_reg_0__rdata_q_all_13_ ( + .CE(com_tlm_u_tlm_tx_vc0_buf_pool_N_17214_i_i_2406), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all[13]), + .Q(com_tlm_u_tlm_tx_vc0_d[13]) + ); + FDE com_tlm_u_tlm_tx_vc0_buf_pool_rdata_reg_0__rdata_q_all_12_ ( + .CE(com_tlm_u_tlm_tx_vc0_buf_pool_N_17214_i_i_2406), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all[12]), + .Q(com_tlm_u_tlm_tx_vc0_d[12]) + ); + FDE com_tlm_u_tlm_tx_vc0_buf_pool_rdata_reg_0__rdata_q_all_11_ ( + .CE(com_tlm_u_tlm_tx_vc0_buf_pool_N_17214_i_i_2406), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all[11]), + .Q(com_tlm_u_tlm_tx_vc0_d[11]) + ); + FDE com_tlm_u_tlm_tx_vc0_buf_pool_rdata_reg_0__rdata_q_all_10_ ( + .CE(com_tlm_u_tlm_tx_vc0_buf_pool_N_17214_i_i_2406), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all[10]), + .Q(com_tlm_u_tlm_tx_vc0_d[10]) + ); + FDE com_tlm_u_tlm_tx_vc0_buf_pool_rdata_reg_0__rdata_q_all_9_ ( + .CE(com_tlm_u_tlm_tx_vc0_buf_pool_N_17214_i_i_2406), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all[9]), + .Q(com_tlm_u_tlm_tx_vc0_d[9]) + ); + FDE com_tlm_u_tlm_tx_vc0_buf_pool_rdata_reg_0__rdata_q_all_8_ ( + .CE(com_tlm_u_tlm_tx_vc0_buf_pool_N_17214_i_i_2406), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all[8]), + .Q(com_tlm_u_tlm_tx_vc0_d[8]) + ); + FDE com_tlm_u_tlm_tx_vc0_buf_pool_rdata_reg_0__rdata_q_all_7_ ( + .CE(com_tlm_u_tlm_tx_vc0_buf_pool_N_17214_i_i_2406), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all[7]), + .Q(com_tlm_u_tlm_tx_vc0_d[7]) + ); + FDE com_tlm_u_tlm_tx_vc0_buf_pool_rdata_reg_0__rdata_q_all_6_ ( + .CE(com_tlm_u_tlm_tx_vc0_buf_pool_N_17214_i_i_2406), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all[6]), + .Q(com_tlm_u_tlm_tx_vc0_d[6]) + ); + FDE com_tlm_u_tlm_tx_vc0_buf_pool_rdata_reg_0__rdata_q_all_5_ ( + .CE(com_tlm_u_tlm_tx_vc0_buf_pool_N_17214_i_i_2406), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all[5]), + .Q(com_tlm_u_tlm_tx_vc0_d[5]) + ); + FDE com_tlm_u_tlm_tx_vc0_buf_pool_rdata_reg_0__rdata_q_all_4_ ( + .CE(com_tlm_u_tlm_tx_vc0_buf_pool_N_17214_i_i_2406), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all[4]), + .Q(com_tlm_u_tlm_tx_vc0_d[4]) + ); + FDE com_tlm_u_tlm_tx_vc0_buf_pool_rdata_reg_0__rdata_q_all_3_ ( + .CE(com_tlm_u_tlm_tx_vc0_buf_pool_N_17214_i_i_2406), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all[3]), + .Q(com_tlm_u_tlm_tx_vc0_d[3]) + ); + FDE com_tlm_u_tlm_tx_vc0_buf_pool_rdata_reg_0__rdata_q_all_2_ ( + .CE(com_tlm_u_tlm_tx_vc0_buf_pool_N_17214_i_i_2406), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all[2]), + .Q(com_tlm_u_tlm_tx_vc0_d[2]) + ); + FDE com_tlm_u_tlm_tx_vc0_buf_pool_rdata_reg_0__rdata_q_all_1_ ( + .CE(com_tlm_u_tlm_tx_vc0_buf_pool_N_17214_i_i_2406), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all[1]), + .Q(com_tlm_u_tlm_tx_vc0_d[1]) + ); + FDE com_tlm_u_tlm_tx_vc0_buf_pool_rdata_reg_0__rdata_q_all_0_ ( + .CE(com_tlm_u_tlm_tx_vc0_buf_pool_N_17214_i_i_2406), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all[0]), + .Q(com_tlm_u_tlm_tx_vc0_d[0]) + ); + FDE com_tlm_u_tlm_tx_vc0_buf_pool_rdata_q_errfwd ( + .CE(com_tlm_u_tlm_tx_vc0_buf_pool_N_17214_i_i_2406), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_buf_pool_rdata_errfwd_2334), + .Q(com_tlm_u_tlm_tx_vc0_errfwd) + ); + FDE com_tlm_u_tlm_tx_vc0_buf_pool_wdata_66_ ( + .CE(com_tlm_u_tlm_tx_vc0_buf_pool_N_22106_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_trn_sof), + .Q(com_tlm_u_tlm_tx_vc0_buf_pool_wdata_66__2335) + ); + FDE com_tlm_u_tlm_tx_vc0_buf_pool_wdata_65_ ( + .CE(com_tlm_u_tlm_tx_vc0_buf_pool_N_22106_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_trn_eof), + .Q(com_tlm_u_tlm_tx_vc0_buf_pool_wdata_65__2336) + ); + FDE com_tlm_u_tlm_tx_vc0_buf_pool_wdata_64_ ( + .CE(com_tlm_u_tlm_tx_vc0_buf_pool_N_22106_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_trn_cfg), + .Q(com_tlm_u_tlm_tx_vc0_buf_pool_wdata_64__2337) + ); + FDE com_tlm_u_tlm_tx_vc0_buf_pool_wdata_63_ ( + .CE(com_tlm_u_tlm_tx_vc0_buf_pool_N_22106_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_trn_d[63]), + .Q(com_tlm_u_tlm_tx_vc0_buf_pool_wdata_63__2338) + ); + FDE com_tlm_u_tlm_tx_vc0_buf_pool_wdata_62_ ( + .CE(com_tlm_u_tlm_tx_vc0_buf_pool_N_22106_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_trn_d[62]), + .Q(com_tlm_u_tlm_tx_vc0_buf_pool_wdata_62__2339) + ); + FDE com_tlm_u_tlm_tx_vc0_buf_pool_wdata_61_ ( + .CE(com_tlm_u_tlm_tx_vc0_buf_pool_N_22106_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_trn_d[61]), + .Q(com_tlm_u_tlm_tx_vc0_buf_pool_wdata_61__2340) + ); + FDE com_tlm_u_tlm_tx_vc0_buf_pool_wdata_60_ ( + .CE(com_tlm_u_tlm_tx_vc0_buf_pool_N_22106_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_trn_d[60]), + .Q(com_tlm_u_tlm_tx_vc0_buf_pool_wdata_60__2341) + ); + FDE com_tlm_u_tlm_tx_vc0_buf_pool_wdata_59_ ( + .CE(com_tlm_u_tlm_tx_vc0_buf_pool_N_22106_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_trn_d[59]), + .Q(com_tlm_u_tlm_tx_vc0_buf_pool_wdata_59__2342) + ); + FDE com_tlm_u_tlm_tx_vc0_buf_pool_wdata_58_ ( + .CE(com_tlm_u_tlm_tx_vc0_buf_pool_N_22106_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_trn_d[58]), + .Q(com_tlm_u_tlm_tx_vc0_buf_pool_wdata_58__2343) + ); + FDE com_tlm_u_tlm_tx_vc0_buf_pool_wdata_57_ ( + .CE(com_tlm_u_tlm_tx_vc0_buf_pool_N_22106_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_trn_d[57]), + .Q(com_tlm_u_tlm_tx_vc0_buf_pool_wdata_57__2344) + ); + FDE com_tlm_u_tlm_tx_vc0_buf_pool_wdata_56_ ( + .CE(com_tlm_u_tlm_tx_vc0_buf_pool_N_22106_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_trn_d[56]), + .Q(com_tlm_u_tlm_tx_vc0_buf_pool_wdata_56__2345) + ); + FDE com_tlm_u_tlm_tx_vc0_buf_pool_wdata_55_ ( + .CE(com_tlm_u_tlm_tx_vc0_buf_pool_N_22106_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_trn_d[55]), + .Q(com_tlm_u_tlm_tx_vc0_buf_pool_wdata_55__2346) + ); + FDE com_tlm_u_tlm_tx_vc0_buf_pool_wdata_54_ ( + .CE(com_tlm_u_tlm_tx_vc0_buf_pool_N_22106_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_trn_d[54]), + .Q(com_tlm_u_tlm_tx_vc0_buf_pool_wdata_54__2347) + ); + FDE com_tlm_u_tlm_tx_vc0_buf_pool_wdata_53_ ( + .CE(com_tlm_u_tlm_tx_vc0_buf_pool_N_22106_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_trn_d[53]), + .Q(com_tlm_u_tlm_tx_vc0_buf_pool_wdata_53__2348) + ); + FDE com_tlm_u_tlm_tx_vc0_buf_pool_wdata_52_ ( + .CE(com_tlm_u_tlm_tx_vc0_buf_pool_N_22106_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_trn_d[52]), + .Q(com_tlm_u_tlm_tx_vc0_buf_pool_wdata_52__2349) + ); + FDE com_tlm_u_tlm_tx_vc0_buf_pool_wdata_51_ ( + .CE(com_tlm_u_tlm_tx_vc0_buf_pool_N_22106_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_trn_d[51]), + .Q(com_tlm_u_tlm_tx_vc0_buf_pool_wdata_51__2350) + ); + FDE com_tlm_u_tlm_tx_vc0_buf_pool_wdata_50_ ( + .CE(com_tlm_u_tlm_tx_vc0_buf_pool_N_22106_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_trn_d[50]), + .Q(com_tlm_u_tlm_tx_vc0_buf_pool_wdata_50__2351) + ); + FDE com_tlm_u_tlm_tx_vc0_buf_pool_wdata_49_ ( + .CE(com_tlm_u_tlm_tx_vc0_buf_pool_N_22106_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_trn_d[49]), + .Q(com_tlm_u_tlm_tx_vc0_buf_pool_wdata_49__2352) + ); + FDE com_tlm_u_tlm_tx_vc0_buf_pool_wdata_48_ ( + .CE(com_tlm_u_tlm_tx_vc0_buf_pool_N_22106_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_trn_d[48]), + .Q(com_tlm_u_tlm_tx_vc0_buf_pool_wdata_48__2353) + ); + FDE com_tlm_u_tlm_tx_vc0_buf_pool_wdata_47_ ( + .CE(com_tlm_u_tlm_tx_vc0_buf_pool_N_22106_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_trn_d[47]), + .Q(com_tlm_u_tlm_tx_vc0_buf_pool_wdata_47__2354) + ); + FDE com_tlm_u_tlm_tx_vc0_buf_pool_wdata_46_ ( + .CE(com_tlm_u_tlm_tx_vc0_buf_pool_N_22106_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_trn_d[46]), + .Q(com_tlm_u_tlm_tx_vc0_buf_pool_wdata_46__2355) + ); + FDE com_tlm_u_tlm_tx_vc0_buf_pool_wdata_45_ ( + .CE(com_tlm_u_tlm_tx_vc0_buf_pool_N_22106_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_trn_d[45]), + .Q(com_tlm_u_tlm_tx_vc0_buf_pool_wdata_45__2356) + ); + FDE com_tlm_u_tlm_tx_vc0_buf_pool_wdata_44_ ( + .CE(com_tlm_u_tlm_tx_vc0_buf_pool_N_22106_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_trn_d[44]), + .Q(com_tlm_u_tlm_tx_vc0_buf_pool_wdata_44__2357) + ); + FDE com_tlm_u_tlm_tx_vc0_buf_pool_wdata_43_ ( + .CE(com_tlm_u_tlm_tx_vc0_buf_pool_N_22106_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_trn_d[43]), + .Q(com_tlm_u_tlm_tx_vc0_buf_pool_wdata_43__2358) + ); + FDE com_tlm_u_tlm_tx_vc0_buf_pool_wdata_42_ ( + .CE(com_tlm_u_tlm_tx_vc0_buf_pool_N_22106_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_trn_d[42]), + .Q(com_tlm_u_tlm_tx_vc0_buf_pool_wdata_42__2359) + ); + FDE com_tlm_u_tlm_tx_vc0_buf_pool_wdata_41_ ( + .CE(com_tlm_u_tlm_tx_vc0_buf_pool_N_22106_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_trn_d[41]), + .Q(com_tlm_u_tlm_tx_vc0_buf_pool_wdata_41__2360) + ); + FDE com_tlm_u_tlm_tx_vc0_buf_pool_wdata_40_ ( + .CE(com_tlm_u_tlm_tx_vc0_buf_pool_N_22106_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_trn_d[40]), + .Q(com_tlm_u_tlm_tx_vc0_buf_pool_wdata_40__2361) + ); + FDE com_tlm_u_tlm_tx_vc0_buf_pool_wdata_39_ ( + .CE(com_tlm_u_tlm_tx_vc0_buf_pool_N_22106_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_trn_d[39]), + .Q(com_tlm_u_tlm_tx_vc0_buf_pool_wdata_39__2362) + ); + FDE com_tlm_u_tlm_tx_vc0_buf_pool_wdata_38_ ( + .CE(com_tlm_u_tlm_tx_vc0_buf_pool_N_22106_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_trn_d[38]), + .Q(com_tlm_u_tlm_tx_vc0_buf_pool_wdata_38__2363) + ); + FDE com_tlm_u_tlm_tx_vc0_buf_pool_wdata_37_ ( + .CE(com_tlm_u_tlm_tx_vc0_buf_pool_N_22106_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_trn_d[37]), + .Q(com_tlm_u_tlm_tx_vc0_buf_pool_wdata_37__2364) + ); + FDE com_tlm_u_tlm_tx_vc0_buf_pool_wdata_36_ ( + .CE(com_tlm_u_tlm_tx_vc0_buf_pool_N_22106_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_trn_d[36]), + .Q(com_tlm_u_tlm_tx_vc0_buf_pool_wdata_36__2365) + ); + FDE com_tlm_u_tlm_tx_vc0_buf_pool_wdata_35_ ( + .CE(com_tlm_u_tlm_tx_vc0_buf_pool_N_22106_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_trn_d[35]), + .Q(com_tlm_u_tlm_tx_vc0_buf_pool_wdata_35__2366) + ); + FDE com_tlm_u_tlm_tx_vc0_buf_pool_wdata_34_ ( + .CE(com_tlm_u_tlm_tx_vc0_buf_pool_N_22106_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_trn_d[34]), + .Q(com_tlm_u_tlm_tx_vc0_buf_pool_wdata_34__2367) + ); + FDE com_tlm_u_tlm_tx_vc0_buf_pool_wdata_33_ ( + .CE(com_tlm_u_tlm_tx_vc0_buf_pool_N_22106_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_trn_d[33]), + .Q(com_tlm_u_tlm_tx_vc0_buf_pool_wdata_33__2368) + ); + FDE com_tlm_u_tlm_tx_vc0_buf_pool_wdata_32_ ( + .CE(com_tlm_u_tlm_tx_vc0_buf_pool_N_22106_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_trn_d[32]), + .Q(com_tlm_u_tlm_tx_vc0_buf_pool_wdata_32__2369) + ); + FDE com_tlm_u_tlm_tx_vc0_buf_pool_wdata_31_ ( + .CE(com_tlm_u_tlm_tx_vc0_buf_pool_N_22106_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_trn_d[31]), + .Q(com_tlm_u_tlm_tx_vc0_buf_pool_wdata_31__2370) + ); + FDE com_tlm_u_tlm_tx_vc0_buf_pool_wdata_30_ ( + .CE(com_tlm_u_tlm_tx_vc0_buf_pool_N_22106_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_trn_d[30]), + .Q(com_tlm_u_tlm_tx_vc0_buf_pool_wdata_30__2371) + ); + FDE com_tlm_u_tlm_tx_vc0_buf_pool_wdata_29_ ( + .CE(com_tlm_u_tlm_tx_vc0_buf_pool_N_22106_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_trn_d[29]), + .Q(com_tlm_u_tlm_tx_vc0_buf_pool_wdata_29__2372) + ); + FDE com_tlm_u_tlm_tx_vc0_buf_pool_wdata_28_ ( + .CE(com_tlm_u_tlm_tx_vc0_buf_pool_N_22106_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_trn_d[28]), + .Q(com_tlm_u_tlm_tx_vc0_buf_pool_wdata_28__2373) + ); + FDE com_tlm_u_tlm_tx_vc0_buf_pool_wdata_27_ ( + .CE(com_tlm_u_tlm_tx_vc0_buf_pool_N_22106_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_trn_d[27]), + .Q(com_tlm_u_tlm_tx_vc0_buf_pool_wdata_27__2374) + ); + FDE com_tlm_u_tlm_tx_vc0_buf_pool_wdata_26_ ( + .CE(com_tlm_u_tlm_tx_vc0_buf_pool_N_22106_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_trn_d[26]), + .Q(com_tlm_u_tlm_tx_vc0_buf_pool_wdata_26__2375) + ); + FDE com_tlm_u_tlm_tx_vc0_buf_pool_wdata_25_ ( + .CE(com_tlm_u_tlm_tx_vc0_buf_pool_N_22106_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_trn_d[25]), + .Q(com_tlm_u_tlm_tx_vc0_buf_pool_wdata_25__2376) + ); + FDE com_tlm_u_tlm_tx_vc0_buf_pool_wdata_24_ ( + .CE(com_tlm_u_tlm_tx_vc0_buf_pool_N_22106_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_trn_d[24]), + .Q(com_tlm_u_tlm_tx_vc0_buf_pool_wdata_24__2377) + ); + FDE com_tlm_u_tlm_tx_vc0_buf_pool_wdata_23_ ( + .CE(com_tlm_u_tlm_tx_vc0_buf_pool_N_22106_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_trn_d[23]), + .Q(com_tlm_u_tlm_tx_vc0_buf_pool_wdata_23__2378) + ); + FDE com_tlm_u_tlm_tx_vc0_buf_pool_wdata_22_ ( + .CE(com_tlm_u_tlm_tx_vc0_buf_pool_N_22106_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_trn_d[22]), + .Q(com_tlm_u_tlm_tx_vc0_buf_pool_wdata_22__2379) + ); + FDE com_tlm_u_tlm_tx_vc0_buf_pool_wdata_21_ ( + .CE(com_tlm_u_tlm_tx_vc0_buf_pool_N_22106_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_trn_d[21]), + .Q(com_tlm_u_tlm_tx_vc0_buf_pool_wdata_21__2380) + ); + FDE com_tlm_u_tlm_tx_vc0_buf_pool_wdata_20_ ( + .CE(com_tlm_u_tlm_tx_vc0_buf_pool_N_22106_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_trn_d[20]), + .Q(com_tlm_u_tlm_tx_vc0_buf_pool_wdata_20__2381) + ); + FDE com_tlm_u_tlm_tx_vc0_buf_pool_wdata_19_ ( + .CE(com_tlm_u_tlm_tx_vc0_buf_pool_N_22106_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_trn_d[19]), + .Q(com_tlm_u_tlm_tx_vc0_buf_pool_wdata_19__2382) + ); + FDE com_tlm_u_tlm_tx_vc0_buf_pool_wdata_18_ ( + .CE(com_tlm_u_tlm_tx_vc0_buf_pool_N_22106_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_trn_d[18]), + .Q(com_tlm_u_tlm_tx_vc0_buf_pool_wdata_18__2383) + ); + FDE com_tlm_u_tlm_tx_vc0_buf_pool_wdata_17_ ( + .CE(com_tlm_u_tlm_tx_vc0_buf_pool_N_22106_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_trn_d[17]), + .Q(com_tlm_u_tlm_tx_vc0_buf_pool_wdata_17__2384) + ); + FDE com_tlm_u_tlm_tx_vc0_buf_pool_wdata_16_ ( + .CE(com_tlm_u_tlm_tx_vc0_buf_pool_N_22106_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_trn_d[16]), + .Q(com_tlm_u_tlm_tx_vc0_buf_pool_wdata_16__2385) + ); + FDE com_tlm_u_tlm_tx_vc0_buf_pool_wdata_15_ ( + .CE(com_tlm_u_tlm_tx_vc0_buf_pool_N_22106_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_trn_d[15]), + .Q(com_tlm_u_tlm_tx_vc0_buf_pool_wdata_15__2386) + ); + FDE com_tlm_u_tlm_tx_vc0_buf_pool_wdata_14_ ( + .CE(com_tlm_u_tlm_tx_vc0_buf_pool_N_22106_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_trn_d[14]), + .Q(com_tlm_u_tlm_tx_vc0_buf_pool_wdata_14__2387) + ); + FDE com_tlm_u_tlm_tx_vc0_buf_pool_wdata_13_ ( + .CE(com_tlm_u_tlm_tx_vc0_buf_pool_N_22106_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_trn_d[13]), + .Q(com_tlm_u_tlm_tx_vc0_buf_pool_wdata_13__2388) + ); + FDE com_tlm_u_tlm_tx_vc0_buf_pool_wdata_12_ ( + .CE(com_tlm_u_tlm_tx_vc0_buf_pool_N_22106_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_trn_d[12]), + .Q(com_tlm_u_tlm_tx_vc0_buf_pool_wdata_12__2389) + ); + FDE com_tlm_u_tlm_tx_vc0_buf_pool_wdata_11_ ( + .CE(com_tlm_u_tlm_tx_vc0_buf_pool_N_22106_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_trn_d[11]), + .Q(com_tlm_u_tlm_tx_vc0_buf_pool_wdata_11__2390) + ); + FDE com_tlm_u_tlm_tx_vc0_buf_pool_wdata_10_ ( + .CE(com_tlm_u_tlm_tx_vc0_buf_pool_N_22106_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_trn_d[10]), + .Q(com_tlm_u_tlm_tx_vc0_buf_pool_wdata_10__2391) + ); + FDE com_tlm_u_tlm_tx_vc0_buf_pool_wdata_9_ ( + .CE(com_tlm_u_tlm_tx_vc0_buf_pool_N_22106_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_trn_d[9]), + .Q(com_tlm_u_tlm_tx_vc0_buf_pool_wdata_9__2392) + ); + FDE com_tlm_u_tlm_tx_vc0_buf_pool_wdata_8_ ( + .CE(com_tlm_u_tlm_tx_vc0_buf_pool_N_22106_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_trn_d[8]), + .Q(com_tlm_u_tlm_tx_vc0_buf_pool_wdata_8__2393) + ); + FDE com_tlm_u_tlm_tx_vc0_buf_pool_wdata_7_ ( + .CE(com_tlm_u_tlm_tx_vc0_buf_pool_N_22106_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_trn_d[7]), + .Q(com_tlm_u_tlm_tx_vc0_buf_pool_wdata_7__2394) + ); + FDE com_tlm_u_tlm_tx_vc0_buf_pool_wdata_6_ ( + .CE(com_tlm_u_tlm_tx_vc0_buf_pool_N_22106_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_trn_d[6]), + .Q(com_tlm_u_tlm_tx_vc0_buf_pool_wdata_6__2395) + ); + FDE com_tlm_u_tlm_tx_vc0_buf_pool_wdata_5_ ( + .CE(com_tlm_u_tlm_tx_vc0_buf_pool_N_22106_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_trn_d[5]), + .Q(com_tlm_u_tlm_tx_vc0_buf_pool_wdata_5__2396) + ); + FDE com_tlm_u_tlm_tx_vc0_buf_pool_wdata_4_ ( + .CE(com_tlm_u_tlm_tx_vc0_buf_pool_N_22106_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_trn_d[4]), + .Q(com_tlm_u_tlm_tx_vc0_buf_pool_wdata_4__2397) + ); + FDE com_tlm_u_tlm_tx_vc0_buf_pool_wdata_3_ ( + .CE(com_tlm_u_tlm_tx_vc0_buf_pool_N_22106_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_trn_d[3]), + .Q(com_tlm_u_tlm_tx_vc0_buf_pool_wdata_3__2398) + ); + FDE com_tlm_u_tlm_tx_vc0_buf_pool_wdata_2_ ( + .CE(com_tlm_u_tlm_tx_vc0_buf_pool_N_22106_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_trn_d[2]), + .Q(com_tlm_u_tlm_tx_vc0_buf_pool_wdata_2__2399) + ); + FDE com_tlm_u_tlm_tx_vc0_buf_pool_wdata_1_ ( + .CE(com_tlm_u_tlm_tx_vc0_buf_pool_N_22106_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_trn_d[1]), + .Q(com_tlm_u_tlm_tx_vc0_buf_pool_wdata_1__2400) + ); + FDE com_tlm_u_tlm_tx_vc0_buf_pool_wdata_0_ ( + .CE(com_tlm_u_tlm_tx_vc0_buf_pool_N_22106_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_trn_d[0]), + .Q(com_tlm_u_tlm_tx_vc0_buf_pool_wdata_0__2401) + ); + FDE com_tlm_u_tlm_tx_vc0_buf_pool_write_rem_wdata_68_ ( + .CE(com_tlm_u_tlm_tx_vc0_buf_pool_N_22106_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_trn_rem_i), + .Q(com_tlm_u_tlm_tx_vc0_buf_pool_wdata_68_) + ); + FDE com_tlm_u_tlm_tx_vc0_buf_pool_wdata_errfwd ( + .CE(com_tlm_u_tlm_tx_vc0_trn_vld), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_buf_pool_N_68303_i_2402), + .Q(com_tlm_u_tlm_tx_vc0_buf_pool_wdata_errfwd_2403) + ); + FDE com_tlm_u_tlm_tx_vc0_buf_pool_retry_tsn_dd_11_ ( + .CE(com_tlm_u_tlm_tx_vc0_nxt_seq_state_0_sqmuxa_i_o2_i_a2), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_start_retry_tsn[11]), + .Q(com_tlm_u_tlm_tx_vc0_buf_pool_retry_tsn_dd[11]) + ); + FDE com_tlm_u_tlm_tx_vc0_buf_pool_retry_tsn_dd_10_ ( + .CE(com_tlm_u_tlm_tx_vc0_nxt_seq_state_0_sqmuxa_i_o2_i_a2), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_start_retry_tsn[10]), + .Q(com_tlm_u_tlm_tx_vc0_buf_pool_retry_tsn_dd[10]) + ); + FDE com_tlm_u_tlm_tx_vc0_buf_pool_retry_tsn_dd_9_ ( + .CE(com_tlm_u_tlm_tx_vc0_nxt_seq_state_0_sqmuxa_i_o2_i_a2), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_start_retry_tsn[9]), + .Q(com_tlm_u_tlm_tx_vc0_buf_pool_retry_tsn_dd[9]) + ); + FDE com_tlm_u_tlm_tx_vc0_buf_pool_retry_tsn_dd_8_ ( + .CE(com_tlm_u_tlm_tx_vc0_nxt_seq_state_0_sqmuxa_i_o2_i_a2), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_start_retry_tsn[8]), + .Q(com_tlm_u_tlm_tx_vc0_buf_pool_retry_tsn_dd[8]) + ); + FDE com_tlm_u_tlm_tx_vc0_buf_pool_retry_tsn_dd_7_ ( + .CE(com_tlm_u_tlm_tx_vc0_nxt_seq_state_0_sqmuxa_i_o2_i_a2), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_start_retry_tsn[7]), + .Q(com_tlm_u_tlm_tx_vc0_buf_pool_retry_tsn_dd[7]) + ); + FDE com_tlm_u_tlm_tx_vc0_buf_pool_retry_tsn_dd_6_ ( + .CE(com_tlm_u_tlm_tx_vc0_nxt_seq_state_0_sqmuxa_i_o2_i_a2), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_start_retry_tsn[6]), + .Q(com_tlm_u_tlm_tx_vc0_buf_pool_retry_tsn_dd[6]) + ); + FDE com_tlm_u_tlm_tx_vc0_buf_pool_retry_tsn_dd_5_ ( + .CE(com_tlm_u_tlm_tx_vc0_nxt_seq_state_0_sqmuxa_i_o2_i_a2), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_start_retry_tsn[5]), + .Q(com_tlm_u_tlm_tx_vc0_buf_pool_retry_tsn_dd[5]) + ); + FDE com_tlm_u_tlm_tx_vc0_buf_pool_retry_tsn_dd_4_ ( + .CE(com_tlm_u_tlm_tx_vc0_nxt_seq_state_0_sqmuxa_i_o2_i_a2), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_start_retry_tsn[4]), + .Q(com_tlm_u_tlm_tx_vc0_buf_pool_retry_tsn_dd[4]) + ); + FDE com_tlm_u_tlm_tx_vc0_buf_pool_retry_tsn_dd_3_ ( + .CE(com_tlm_u_tlm_tx_vc0_nxt_seq_state_0_sqmuxa_i_o2_i_a2), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_start_retry_tsn[3]), + .Q(com_tlm_u_tlm_tx_vc0_buf_pool_retry_tsn_dd[3]) + ); + FDE com_tlm_u_tlm_tx_vc0_buf_pool_retry_tsn_dd_2_ ( + .CE(com_tlm_u_tlm_tx_vc0_nxt_seq_state_0_sqmuxa_i_o2_i_a2), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_start_retry_tsn[2]), + .Q(com_tlm_u_tlm_tx_vc0_buf_pool_retry_tsn_dd[2]) + ); + FDE com_tlm_u_tlm_tx_vc0_buf_pool_retry_tsn_dd_1_ ( + .CE(com_tlm_u_tlm_tx_vc0_nxt_seq_state_0_sqmuxa_i_o2_i_a2), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_start_retry_tsn[1]), + .Q(com_tlm_u_tlm_tx_vc0_buf_pool_retry_tsn_dd[1]) + ); + FDE com_tlm_u_tlm_tx_vc0_buf_pool_retry_tsn_dd_0_ ( + .CE(com_tlm_u_tlm_tx_vc0_nxt_seq_state_0_sqmuxa_i_o2_i_a2), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_start_retry_tsn[0]), + .Q(com_tlm_u_tlm_tx_vc0_buf_pool_retry_tsn_dd[0]) + ); + FDE com_tlm_u_tlm_tx_vc0_buf_pool_raddr_h_q_3_ ( + .CE(com_tlm_u_tlm_tx_vc0_buf_pool_en_ram_i_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_buf_pool_raddr_h[3]), + .Q(com_tlm_u_tlm_tx_vc0_buf_num[3]) + ); + FDE com_tlm_u_tlm_tx_vc0_buf_pool_raddr_h_q_2_ ( + .CE(com_tlm_u_tlm_tx_vc0_buf_pool_en_ram_i_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_buf_pool_raddr_h[2]), + .Q(com_tlm_u_tlm_tx_vc0_buf_num[2]) + ); + FDE com_tlm_u_tlm_tx_vc0_buf_pool_raddr_h_q_1_ ( + .CE(com_tlm_u_tlm_tx_vc0_buf_pool_en_ram_i_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_buf_pool_raddr_h[1]), + .Q(com_tlm_u_tlm_tx_vc0_buf_num[1]) + ); + FDE com_tlm_u_tlm_tx_vc0_buf_pool_raddr_h_q_0_ ( + .CE(com_tlm_u_tlm_tx_vc0_buf_pool_en_ram_i_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_buf_pool_raddr_h[0]), + .Q(com_tlm_u_tlm_tx_vc0_buf_num[0]) + ); + FDE com_tlm_u_tlm_tx_vc0_buf_pool_retry_tsn_d_11_ ( + .CE(com_tlm_u_tlm_tx_vc0_buf_pool_N_17122_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_buf_pool_retry_tsn_dd[11]), + .Q(com_tlm_u_tlm_tx_vc0_retry_tsn[11]) + ); + FDE com_tlm_u_tlm_tx_vc0_buf_pool_retry_tsn_d_10_ ( + .CE(com_tlm_u_tlm_tx_vc0_buf_pool_N_17122_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_buf_pool_retry_tsn_dd[10]), + .Q(com_tlm_u_tlm_tx_vc0_retry_tsn[10]) + ); + FDE com_tlm_u_tlm_tx_vc0_buf_pool_retry_tsn_d_9_ ( + .CE(com_tlm_u_tlm_tx_vc0_buf_pool_N_17122_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_buf_pool_retry_tsn_dd[9]), + .Q(com_tlm_u_tlm_tx_vc0_retry_tsn[9]) + ); + FDE com_tlm_u_tlm_tx_vc0_buf_pool_retry_tsn_d_8_ ( + .CE(com_tlm_u_tlm_tx_vc0_buf_pool_N_17122_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_buf_pool_retry_tsn_dd[8]), + .Q(com_tlm_u_tlm_tx_vc0_retry_tsn[8]) + ); + FDE com_tlm_u_tlm_tx_vc0_buf_pool_retry_tsn_d_7_ ( + .CE(com_tlm_u_tlm_tx_vc0_buf_pool_N_17122_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_buf_pool_retry_tsn_dd[7]), + .Q(com_tlm_u_tlm_tx_vc0_retry_tsn[7]) + ); + FDE com_tlm_u_tlm_tx_vc0_buf_pool_retry_tsn_d_6_ ( + .CE(com_tlm_u_tlm_tx_vc0_buf_pool_N_17122_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_buf_pool_retry_tsn_dd[6]), + .Q(com_tlm_u_tlm_tx_vc0_retry_tsn[6]) + ); + FDE com_tlm_u_tlm_tx_vc0_buf_pool_retry_tsn_d_5_ ( + .CE(com_tlm_u_tlm_tx_vc0_buf_pool_N_17122_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_buf_pool_retry_tsn_dd[5]), + .Q(com_tlm_u_tlm_tx_vc0_retry_tsn[5]) + ); + FDE com_tlm_u_tlm_tx_vc0_buf_pool_retry_tsn_d_4_ ( + .CE(com_tlm_u_tlm_tx_vc0_buf_pool_N_17122_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_buf_pool_retry_tsn_dd[4]), + .Q(com_tlm_u_tlm_tx_vc0_retry_tsn[4]) + ); + FDE com_tlm_u_tlm_tx_vc0_buf_pool_retry_tsn_d_3_ ( + .CE(com_tlm_u_tlm_tx_vc0_buf_pool_N_17122_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_buf_pool_retry_tsn_dd[3]), + .Q(com_tlm_u_tlm_tx_vc0_retry_tsn[3]) + ); + FDE com_tlm_u_tlm_tx_vc0_buf_pool_retry_tsn_d_2_ ( + .CE(com_tlm_u_tlm_tx_vc0_buf_pool_N_17122_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_buf_pool_retry_tsn_dd[2]), + .Q(com_tlm_u_tlm_tx_vc0_retry_tsn[2]) + ); + FDE com_tlm_u_tlm_tx_vc0_buf_pool_retry_tsn_d_1_ ( + .CE(com_tlm_u_tlm_tx_vc0_buf_pool_N_17122_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_buf_pool_retry_tsn_dd[1]), + .Q(com_tlm_u_tlm_tx_vc0_retry_tsn[1]) + ); + FDE com_tlm_u_tlm_tx_vc0_buf_pool_retry_tsn_d_0_ ( + .CE(com_tlm_u_tlm_tx_vc0_buf_pool_N_17122_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_buf_pool_retry_tsn_dd[0]), + .Q(com_tlm_u_tlm_tx_vc0_retry_tsn[0]) + ); + INV com_tlm_u_tlm_tx_vc0_buf_pool_N_51062_i ( + .I(com_tlm_u_tlm_tx_vc0_buf_pool_rdata_sof_d_0_a2_2405), + .O(com_tlm_u_tlm_tx_vc0_buf_pool_N_51062_i_2404) + ); + INV com_tlm_u_tlm_tx_vc0_buf_pool_N_17214_i_i ( + .I(com_tlm_u_tlm_tx_vc0_N_17214_i), + .O(com_tlm_u_tlm_tx_vc0_buf_pool_N_17214_i_i_2406) + ); + defparam com_tlm_u_tlm_tx_vc0_buf_pool_raddr_l_qxu_0_0_.INIT = 4'h2; + LUT1_L com_tlm_u_tlm_tx_vc0_buf_pool_raddr_l_qxu_0_0_ ( + .I0(com_tlm_u_tlm_tx_vc0_buf_pool_raddr_l[0]), + .LO(com_tlm_u_tlm_tx_vc0_buf_pool_raddr_l_qxu[0]) + ); + defparam com_tlm_u_tlm_tx_vc0_buf_pool_un5_waddr_l_0_a2_0_.INIT = 4'h1; + LUT2_L com_tlm_u_tlm_tx_vc0_buf_pool_un5_waddr_l_0_a2_0_ ( + .I0(com_tlm_u_tlm_tx_vc0_buf_pool_waddr_l[0]), + .I1(com_tlm_u_tlm_tx_vc0_trn_sof), + .LO(com_tlm_u_tlm_tx_vc0_buf_pool_waddr_l_1[0]) + ); + defparam com_tlm_u_tlm_tx_vc0_buf_pool_raddr_l_qxu_0_6_.INIT = 4'h2; + LUT1_L com_tlm_u_tlm_tx_vc0_buf_pool_raddr_l_qxu_0_6_ ( + .I0(com_tlm_u_tlm_tx_vc0_buf_pool_raddr_l[6]), + .LO(com_tlm_u_tlm_tx_vc0_buf_pool_raddr_l_qxu[6]) + ); + defparam com_tlm_u_tlm_tx_vc0_buf_pool_raddr_l_qxu_0_5_.INIT = 4'h2; + LUT1_L com_tlm_u_tlm_tx_vc0_buf_pool_raddr_l_qxu_0_5_ ( + .I0(com_tlm_u_tlm_tx_vc0_buf_pool_raddr_l[5]), + .LO(com_tlm_u_tlm_tx_vc0_buf_pool_raddr_l_qxu[5]) + ); + defparam com_tlm_u_tlm_tx_vc0_buf_pool_raddr_l_qxu_0_4_.INIT = 4'h2; + LUT1_L com_tlm_u_tlm_tx_vc0_buf_pool_raddr_l_qxu_0_4_ ( + .I0(com_tlm_u_tlm_tx_vc0_buf_pool_raddr_l[4]), + .LO(com_tlm_u_tlm_tx_vc0_buf_pool_raddr_l_qxu[4]) + ); + defparam com_tlm_u_tlm_tx_vc0_buf_pool_raddr_l_qxu_0_3_.INIT = 4'h2; + LUT1_L com_tlm_u_tlm_tx_vc0_buf_pool_raddr_l_qxu_0_3_ ( + .I0(com_tlm_u_tlm_tx_vc0_buf_pool_raddr_l[3]), + .LO(com_tlm_u_tlm_tx_vc0_buf_pool_raddr_l_qxu[3]) + ); + defparam com_tlm_u_tlm_tx_vc0_buf_pool_raddr_l_qxu_0_2_.INIT = 4'h2; + LUT1_L com_tlm_u_tlm_tx_vc0_buf_pool_raddr_l_qxu_0_2_ ( + .I0(com_tlm_u_tlm_tx_vc0_buf_pool_raddr_l[2]), + .LO(com_tlm_u_tlm_tx_vc0_buf_pool_raddr_l_qxu[2]) + ); + defparam com_tlm_u_tlm_tx_vc0_buf_pool_raddr_l_qxu_0_1_.INIT = 4'h2; + LUT1_L com_tlm_u_tlm_tx_vc0_buf_pool_raddr_l_qxu_0_1_ ( + .I0(com_tlm_u_tlm_tx_vc0_buf_pool_raddr_l[1]), + .LO(com_tlm_u_tlm_tx_vc0_buf_pool_raddr_l_qxu[1]) + ); + defparam com_tlm_u_tlm_tx_vc0_buf_pool_raddr_l_s_0_.INIT = 4'h1; + LUT1_L com_tlm_u_tlm_tx_vc0_buf_pool_raddr_l_s_0_ ( + .I0(com_tlm_u_tlm_tx_vc0_buf_pool_raddr_l_qxu[0]), + .LO(com_tlm_u_tlm_tx_vc0_buf_pool_raddr_l_s[0]) + ); + defparam com_tlm_u_tlm_tx_vc0_buf_pool_waddr_l_1_axb_0.INIT = 4'hE; + LUT2 com_tlm_u_tlm_tx_vc0_buf_pool_waddr_l_1_axb_0 ( + .I0(com_tlm_u_tlm_tx_vc0_buf_pool_waddr_l[0]), + .I1(com_tlm_u_tlm_tx_vc0_trn_sof), + .O(com_tlm_u_tlm_tx_vc0_buf_pool_waddr_l_1_axb_0_2407) + ); + VCC com_tlm_u_tlm_tx_vc0_buf_pool_bram_0__size8_bram_array_VCC ( + .P(com_tlm_u_tlm_tx_vc0_buf_pool_bram_0__size8_bram_array_VCC_2409) + ); + GND com_tlm_u_tlm_tx_vc0_buf_pool_bram_0__size8_bram_array_GND ( + .G(com_tlm_u_tlm_tx_vc0_buf_pool_bram_0__size8_bram_array_GND_2408) + ); + defparam com_tlm_u_tlm_tx_vc0_buf_pool_bram_0__size8_bram_array_ram_row_0__block_ram_0__ram2048x9_bram.WRITE_MODE_A = "NO_CHANGE"; + RAMB16_S9_S9 com_tlm_u_tlm_tx_vc0_buf_pool_bram_0__size8_bram_array_ram_row_0__block_ram_0__ram2048x9_bram ( + .ENA(com_tlm_u_tlm_tx_vc0_buf_pool_bram_0__size8_bram_array_VCC_2409), + .ENB(com_tlm_u_tlm_tx_vc0_buf_pool_bram_0__size8_bram_array_N_9690_i_2410), + .SSRA(com_reset_i_q), + .SSRB(com_reset_i_q), + .WEA(com_tlm_u_tlm_tx_vc0_buf_pool_N_22095_i), + .WEB(com_tlm_u_tlm_tx_vc0_buf_pool_bram_0__size8_bram_array_GND_2408), + .CLKA(NlwRenamedSig_OI_trn_clk), + .CLKB(NlwRenamedSig_OI_trn_clk), + .DIPB({com_tlm_u_tlm_tx_vc0_buf_pool_bram_0__size8_bram_array_GND_2408}), + .ADDRA({com_tlm_u_tlm_tx_vc0_buf_pool_waddr_h[3], com_tlm_u_tlm_tx_vc0_buf_pool_waddr_h[2], com_tlm_u_tlm_tx_vc0_buf_pool_waddr_h[1], +com_tlm_u_tlm_tx_vc0_buf_pool_waddr_h[0], com_tlm_u_tlm_tx_vc0_buf_pool_waddr_l[6], com_tlm_u_tlm_tx_vc0_buf_pool_waddr_l[5], +com_tlm_u_tlm_tx_vc0_buf_pool_waddr_l[4], com_tlm_u_tlm_tx_vc0_buf_pool_waddr_l[3], com_tlm_u_tlm_tx_vc0_buf_pool_waddr_l[2], +com_tlm_u_tlm_tx_vc0_buf_pool_waddr_l[1], com_tlm_u_tlm_tx_vc0_buf_pool_waddr_l[0]}), + .ADDRB({com_tlm_u_tlm_tx_vc0_buf_pool_raddr_h[3], com_tlm_u_tlm_tx_vc0_buf_pool_raddr_h[2], com_tlm_u_tlm_tx_vc0_buf_pool_raddr_h[1], +com_tlm_u_tlm_tx_vc0_buf_pool_raddr_h[0], com_tlm_u_tlm_tx_vc0_buf_pool_raddr_l[6], com_tlm_u_tlm_tx_vc0_buf_pool_raddr_l[5], +com_tlm_u_tlm_tx_vc0_buf_pool_raddr_l[4], com_tlm_u_tlm_tx_vc0_buf_pool_raddr_l[3], com_tlm_u_tlm_tx_vc0_buf_pool_raddr_l[2], +com_tlm_u_tlm_tx_vc0_buf_pool_raddr_l[1], com_tlm_u_tlm_tx_vc0_buf_pool_raddr_l[0]}), + .DOPA({NLW_com_tlm_u_tlm_tx_vc0_buf_pool_bram_0__size8_bram_array_ram_row_0__block_ram_0__ram2048x9_bram_DOPA_0__UNCONNECTED}), + .DIA({com_tlm_u_tlm_tx_vc0_buf_pool_wdata_7__2394, com_tlm_u_tlm_tx_vc0_buf_pool_wdata_6__2395, com_tlm_u_tlm_tx_vc0_buf_pool_wdata_5__2396, +com_tlm_u_tlm_tx_vc0_buf_pool_wdata_4__2397, com_tlm_u_tlm_tx_vc0_buf_pool_wdata_3__2398, com_tlm_u_tlm_tx_vc0_buf_pool_wdata_2__2399, +com_tlm_u_tlm_tx_vc0_buf_pool_wdata_1__2400, com_tlm_u_tlm_tx_vc0_buf_pool_wdata_0__2401}), + .DIB({com_tlm_u_tlm_tx_vc0_buf_pool_bram_0__size8_bram_array_GND_2408, com_tlm_u_tlm_tx_vc0_buf_pool_bram_0__size8_bram_array_GND_2408, +com_tlm_u_tlm_tx_vc0_buf_pool_bram_0__size8_bram_array_GND_2408, com_tlm_u_tlm_tx_vc0_buf_pool_bram_0__size8_bram_array_GND_2408, +com_tlm_u_tlm_tx_vc0_buf_pool_bram_0__size8_bram_array_GND_2408, com_tlm_u_tlm_tx_vc0_buf_pool_bram_0__size8_bram_array_GND_2408, +com_tlm_u_tlm_tx_vc0_buf_pool_bram_0__size8_bram_array_GND_2408, com_tlm_u_tlm_tx_vc0_buf_pool_bram_0__size8_bram_array_GND_2408}), + .DOPB({com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all[8]}), + .DIPA({com_tlm_u_tlm_tx_vc0_buf_pool_wdata_8__2393}), + .DOA({NLW_com_tlm_u_tlm_tx_vc0_buf_pool_bram_0__size8_bram_array_ram_row_0__block_ram_0__ram2048x9_bram_DOA_7__UNCONNECTED, +NLW_com_tlm_u_tlm_tx_vc0_buf_pool_bram_0__size8_bram_array_ram_row_0__block_ram_0__ram2048x9_bram_DOA_6__UNCONNECTED, +NLW_com_tlm_u_tlm_tx_vc0_buf_pool_bram_0__size8_bram_array_ram_row_0__block_ram_0__ram2048x9_bram_DOA_5__UNCONNECTED, +NLW_com_tlm_u_tlm_tx_vc0_buf_pool_bram_0__size8_bram_array_ram_row_0__block_ram_0__ram2048x9_bram_DOA_4__UNCONNECTED, +NLW_com_tlm_u_tlm_tx_vc0_buf_pool_bram_0__size8_bram_array_ram_row_0__block_ram_0__ram2048x9_bram_DOA_3__UNCONNECTED, +NLW_com_tlm_u_tlm_tx_vc0_buf_pool_bram_0__size8_bram_array_ram_row_0__block_ram_0__ram2048x9_bram_DOA_2__UNCONNECTED, +NLW_com_tlm_u_tlm_tx_vc0_buf_pool_bram_0__size8_bram_array_ram_row_0__block_ram_0__ram2048x9_bram_DOA_1__UNCONNECTED, +NLW_com_tlm_u_tlm_tx_vc0_buf_pool_bram_0__size8_bram_array_ram_row_0__block_ram_0__ram2048x9_bram_DOA_0__UNCONNECTED}), + .DOB({com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all[7], com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all[6], com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all[5], +com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all[4], com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all[3], com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all[2], +com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all[1], com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all[0]}) + ); + defparam com_tlm_u_tlm_tx_vc0_buf_pool_bram_0__size8_bram_array_ram_row_0__block_ram_1__ram2048x9_bram.WRITE_MODE_A = "NO_CHANGE"; + RAMB16_S9_S9 com_tlm_u_tlm_tx_vc0_buf_pool_bram_0__size8_bram_array_ram_row_0__block_ram_1__ram2048x9_bram ( + .ENA(com_tlm_u_tlm_tx_vc0_buf_pool_bram_0__size8_bram_array_VCC_2409), + .ENB(com_tlm_u_tlm_tx_vc0_buf_pool_bram_0__size8_bram_array_N_9690_i_2410), + .SSRA(com_reset_i_q), + .SSRB(com_reset_i_q), + .WEA(com_tlm_u_tlm_tx_vc0_buf_pool_N_22095_i), + .WEB(com_tlm_u_tlm_tx_vc0_buf_pool_bram_0__size8_bram_array_GND_2408), + .CLKA(NlwRenamedSig_OI_trn_clk), + .CLKB(NlwRenamedSig_OI_trn_clk), + .DIPB({com_tlm_u_tlm_tx_vc0_buf_pool_bram_0__size8_bram_array_GND_2408}), + .ADDRA({com_tlm_u_tlm_tx_vc0_buf_pool_waddr_h[3], com_tlm_u_tlm_tx_vc0_buf_pool_waddr_h[2], com_tlm_u_tlm_tx_vc0_buf_pool_waddr_h[1], +com_tlm_u_tlm_tx_vc0_buf_pool_waddr_h[0], com_tlm_u_tlm_tx_vc0_buf_pool_waddr_l[6], com_tlm_u_tlm_tx_vc0_buf_pool_waddr_l[5], +com_tlm_u_tlm_tx_vc0_buf_pool_waddr_l[4], com_tlm_u_tlm_tx_vc0_buf_pool_waddr_l[3], com_tlm_u_tlm_tx_vc0_buf_pool_waddr_l[2], +com_tlm_u_tlm_tx_vc0_buf_pool_waddr_l[1], com_tlm_u_tlm_tx_vc0_buf_pool_waddr_l[0]}), + .ADDRB({com_tlm_u_tlm_tx_vc0_buf_pool_raddr_h[3], com_tlm_u_tlm_tx_vc0_buf_pool_raddr_h[2], com_tlm_u_tlm_tx_vc0_buf_pool_raddr_h[1], +com_tlm_u_tlm_tx_vc0_buf_pool_raddr_h[0], com_tlm_u_tlm_tx_vc0_buf_pool_raddr_l[6], com_tlm_u_tlm_tx_vc0_buf_pool_raddr_l[5], +com_tlm_u_tlm_tx_vc0_buf_pool_raddr_l[4], com_tlm_u_tlm_tx_vc0_buf_pool_raddr_l[3], com_tlm_u_tlm_tx_vc0_buf_pool_raddr_l[2], +com_tlm_u_tlm_tx_vc0_buf_pool_raddr_l[1], com_tlm_u_tlm_tx_vc0_buf_pool_raddr_l[0]}), + .DOPA({NLW_com_tlm_u_tlm_tx_vc0_buf_pool_bram_0__size8_bram_array_ram_row_0__block_ram_1__ram2048x9_bram_DOPA_0__UNCONNECTED}), + .DIA({com_tlm_u_tlm_tx_vc0_buf_pool_wdata_16__2385, com_tlm_u_tlm_tx_vc0_buf_pool_wdata_15__2386, com_tlm_u_tlm_tx_vc0_buf_pool_wdata_14__2387, +com_tlm_u_tlm_tx_vc0_buf_pool_wdata_13__2388, com_tlm_u_tlm_tx_vc0_buf_pool_wdata_12__2389, com_tlm_u_tlm_tx_vc0_buf_pool_wdata_11__2390, +com_tlm_u_tlm_tx_vc0_buf_pool_wdata_10__2391, com_tlm_u_tlm_tx_vc0_buf_pool_wdata_9__2392}), + .DIB({com_tlm_u_tlm_tx_vc0_buf_pool_bram_0__size8_bram_array_GND_2408, com_tlm_u_tlm_tx_vc0_buf_pool_bram_0__size8_bram_array_GND_2408, +com_tlm_u_tlm_tx_vc0_buf_pool_bram_0__size8_bram_array_GND_2408, com_tlm_u_tlm_tx_vc0_buf_pool_bram_0__size8_bram_array_GND_2408, +com_tlm_u_tlm_tx_vc0_buf_pool_bram_0__size8_bram_array_GND_2408, com_tlm_u_tlm_tx_vc0_buf_pool_bram_0__size8_bram_array_GND_2408, +com_tlm_u_tlm_tx_vc0_buf_pool_bram_0__size8_bram_array_GND_2408, com_tlm_u_tlm_tx_vc0_buf_pool_bram_0__size8_bram_array_GND_2408}), + .DOPB({com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all[17]}), + .DIPA({com_tlm_u_tlm_tx_vc0_buf_pool_wdata_17__2384}), + .DOA({NLW_com_tlm_u_tlm_tx_vc0_buf_pool_bram_0__size8_bram_array_ram_row_0__block_ram_1__ram2048x9_bram_DOA_7__UNCONNECTED, +NLW_com_tlm_u_tlm_tx_vc0_buf_pool_bram_0__size8_bram_array_ram_row_0__block_ram_1__ram2048x9_bram_DOA_6__UNCONNECTED, +NLW_com_tlm_u_tlm_tx_vc0_buf_pool_bram_0__size8_bram_array_ram_row_0__block_ram_1__ram2048x9_bram_DOA_5__UNCONNECTED, +NLW_com_tlm_u_tlm_tx_vc0_buf_pool_bram_0__size8_bram_array_ram_row_0__block_ram_1__ram2048x9_bram_DOA_4__UNCONNECTED, +NLW_com_tlm_u_tlm_tx_vc0_buf_pool_bram_0__size8_bram_array_ram_row_0__block_ram_1__ram2048x9_bram_DOA_3__UNCONNECTED, +NLW_com_tlm_u_tlm_tx_vc0_buf_pool_bram_0__size8_bram_array_ram_row_0__block_ram_1__ram2048x9_bram_DOA_2__UNCONNECTED, +NLW_com_tlm_u_tlm_tx_vc0_buf_pool_bram_0__size8_bram_array_ram_row_0__block_ram_1__ram2048x9_bram_DOA_1__UNCONNECTED, +NLW_com_tlm_u_tlm_tx_vc0_buf_pool_bram_0__size8_bram_array_ram_row_0__block_ram_1__ram2048x9_bram_DOA_0__UNCONNECTED}), + .DOB({com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all[16], com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all[15], com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all[14], +com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all[13], com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all[12], com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all[11], +com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all[10], com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all[9]}) + ); + defparam com_tlm_u_tlm_tx_vc0_buf_pool_bram_0__size8_bram_array_ram_row_0__block_ram_3__ram2048x9_bram.WRITE_MODE_A = "NO_CHANGE"; + RAMB16_S9_S9 com_tlm_u_tlm_tx_vc0_buf_pool_bram_0__size8_bram_array_ram_row_0__block_ram_3__ram2048x9_bram ( + .ENA(com_tlm_u_tlm_tx_vc0_buf_pool_bram_0__size8_bram_array_VCC_2409), + .ENB(com_tlm_u_tlm_tx_vc0_buf_pool_bram_0__size8_bram_array_N_9690_i_2410), + .SSRA(com_reset_i_q), + .SSRB(com_reset_i_q), + .WEA(com_tlm_u_tlm_tx_vc0_buf_pool_N_22095_i), + .WEB(com_tlm_u_tlm_tx_vc0_buf_pool_bram_0__size8_bram_array_GND_2408), + .CLKA(NlwRenamedSig_OI_trn_clk), + .CLKB(NlwRenamedSig_OI_trn_clk), + .DIPB({com_tlm_u_tlm_tx_vc0_buf_pool_bram_0__size8_bram_array_GND_2408}), + .ADDRA({com_tlm_u_tlm_tx_vc0_buf_pool_waddr_h[3], com_tlm_u_tlm_tx_vc0_buf_pool_waddr_h[2], com_tlm_u_tlm_tx_vc0_buf_pool_waddr_h[1], +com_tlm_u_tlm_tx_vc0_buf_pool_waddr_h[0], com_tlm_u_tlm_tx_vc0_buf_pool_waddr_l[6], com_tlm_u_tlm_tx_vc0_buf_pool_waddr_l[5], +com_tlm_u_tlm_tx_vc0_buf_pool_waddr_l[4], com_tlm_u_tlm_tx_vc0_buf_pool_waddr_l[3], com_tlm_u_tlm_tx_vc0_buf_pool_waddr_l[2], +com_tlm_u_tlm_tx_vc0_buf_pool_waddr_l[1], com_tlm_u_tlm_tx_vc0_buf_pool_waddr_l[0]}), + .ADDRB({com_tlm_u_tlm_tx_vc0_buf_pool_raddr_h[3], com_tlm_u_tlm_tx_vc0_buf_pool_raddr_h[2], com_tlm_u_tlm_tx_vc0_buf_pool_raddr_h[1], +com_tlm_u_tlm_tx_vc0_buf_pool_raddr_h[0], com_tlm_u_tlm_tx_vc0_buf_pool_raddr_l[6], com_tlm_u_tlm_tx_vc0_buf_pool_raddr_l[5], +com_tlm_u_tlm_tx_vc0_buf_pool_raddr_l[4], com_tlm_u_tlm_tx_vc0_buf_pool_raddr_l[3], com_tlm_u_tlm_tx_vc0_buf_pool_raddr_l[2], +com_tlm_u_tlm_tx_vc0_buf_pool_raddr_l[1], com_tlm_u_tlm_tx_vc0_buf_pool_raddr_l[0]}), + .DOPA({NLW_com_tlm_u_tlm_tx_vc0_buf_pool_bram_0__size8_bram_array_ram_row_0__block_ram_3__ram2048x9_bram_DOPA_0__UNCONNECTED}), + .DIA({com_tlm_u_tlm_tx_vc0_buf_pool_wdata_34__2367, com_tlm_u_tlm_tx_vc0_buf_pool_wdata_33__2368, com_tlm_u_tlm_tx_vc0_buf_pool_wdata_32__2369, +com_tlm_u_tlm_tx_vc0_buf_pool_wdata_31__2370, com_tlm_u_tlm_tx_vc0_buf_pool_wdata_30__2371, com_tlm_u_tlm_tx_vc0_buf_pool_wdata_29__2372, +com_tlm_u_tlm_tx_vc0_buf_pool_wdata_28__2373, com_tlm_u_tlm_tx_vc0_buf_pool_wdata_27__2374}), + .DIB({com_tlm_u_tlm_tx_vc0_buf_pool_bram_0__size8_bram_array_GND_2408, com_tlm_u_tlm_tx_vc0_buf_pool_bram_0__size8_bram_array_GND_2408, +com_tlm_u_tlm_tx_vc0_buf_pool_bram_0__size8_bram_array_GND_2408, com_tlm_u_tlm_tx_vc0_buf_pool_bram_0__size8_bram_array_GND_2408, +com_tlm_u_tlm_tx_vc0_buf_pool_bram_0__size8_bram_array_GND_2408, com_tlm_u_tlm_tx_vc0_buf_pool_bram_0__size8_bram_array_GND_2408, +com_tlm_u_tlm_tx_vc0_buf_pool_bram_0__size8_bram_array_GND_2408, com_tlm_u_tlm_tx_vc0_buf_pool_bram_0__size8_bram_array_GND_2408}), + .DOPB({com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all[35]}), + .DIPA({com_tlm_u_tlm_tx_vc0_buf_pool_wdata_35__2366}), + .DOA({NLW_com_tlm_u_tlm_tx_vc0_buf_pool_bram_0__size8_bram_array_ram_row_0__block_ram_3__ram2048x9_bram_DOA_7__UNCONNECTED, +NLW_com_tlm_u_tlm_tx_vc0_buf_pool_bram_0__size8_bram_array_ram_row_0__block_ram_3__ram2048x9_bram_DOA_6__UNCONNECTED, +NLW_com_tlm_u_tlm_tx_vc0_buf_pool_bram_0__size8_bram_array_ram_row_0__block_ram_3__ram2048x9_bram_DOA_5__UNCONNECTED, +NLW_com_tlm_u_tlm_tx_vc0_buf_pool_bram_0__size8_bram_array_ram_row_0__block_ram_3__ram2048x9_bram_DOA_4__UNCONNECTED, +NLW_com_tlm_u_tlm_tx_vc0_buf_pool_bram_0__size8_bram_array_ram_row_0__block_ram_3__ram2048x9_bram_DOA_3__UNCONNECTED, +NLW_com_tlm_u_tlm_tx_vc0_buf_pool_bram_0__size8_bram_array_ram_row_0__block_ram_3__ram2048x9_bram_DOA_2__UNCONNECTED, +NLW_com_tlm_u_tlm_tx_vc0_buf_pool_bram_0__size8_bram_array_ram_row_0__block_ram_3__ram2048x9_bram_DOA_1__UNCONNECTED, +NLW_com_tlm_u_tlm_tx_vc0_buf_pool_bram_0__size8_bram_array_ram_row_0__block_ram_3__ram2048x9_bram_DOA_0__UNCONNECTED}), + .DOB({com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all[34], com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all[33], com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all[32], +com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all[31], com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all[30], com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all[29], +com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all[28], com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all[27]}) + ); + defparam com_tlm_u_tlm_tx_vc0_buf_pool_bram_0__size8_bram_array_ram_row_0__block_ram_4__ram2048x9_bram.WRITE_MODE_A = "NO_CHANGE"; + RAMB16_S9_S9 com_tlm_u_tlm_tx_vc0_buf_pool_bram_0__size8_bram_array_ram_row_0__block_ram_4__ram2048x9_bram ( + .ENA(com_tlm_u_tlm_tx_vc0_buf_pool_bram_0__size8_bram_array_VCC_2409), + .ENB(com_tlm_u_tlm_tx_vc0_buf_pool_bram_0__size8_bram_array_N_9690_i_2410), + .SSRA(com_reset_i_q), + .SSRB(com_reset_i_q), + .WEA(com_tlm_u_tlm_tx_vc0_buf_pool_N_22095_i), + .WEB(com_tlm_u_tlm_tx_vc0_buf_pool_bram_0__size8_bram_array_GND_2408), + .CLKA(NlwRenamedSig_OI_trn_clk), + .CLKB(NlwRenamedSig_OI_trn_clk), + .DIPB({com_tlm_u_tlm_tx_vc0_buf_pool_bram_0__size8_bram_array_GND_2408}), + .ADDRA({com_tlm_u_tlm_tx_vc0_buf_pool_waddr_h[3], com_tlm_u_tlm_tx_vc0_buf_pool_waddr_h[2], com_tlm_u_tlm_tx_vc0_buf_pool_waddr_h[1], +com_tlm_u_tlm_tx_vc0_buf_pool_waddr_h[0], com_tlm_u_tlm_tx_vc0_buf_pool_waddr_l[6], com_tlm_u_tlm_tx_vc0_buf_pool_waddr_l[5], +com_tlm_u_tlm_tx_vc0_buf_pool_waddr_l[4], com_tlm_u_tlm_tx_vc0_buf_pool_waddr_l[3], com_tlm_u_tlm_tx_vc0_buf_pool_waddr_l[2], +com_tlm_u_tlm_tx_vc0_buf_pool_waddr_l[1], com_tlm_u_tlm_tx_vc0_buf_pool_waddr_l[0]}), + .ADDRB({com_tlm_u_tlm_tx_vc0_buf_pool_raddr_h[3], com_tlm_u_tlm_tx_vc0_buf_pool_raddr_h[2], com_tlm_u_tlm_tx_vc0_buf_pool_raddr_h[1], +com_tlm_u_tlm_tx_vc0_buf_pool_raddr_h[0], com_tlm_u_tlm_tx_vc0_buf_pool_raddr_l[6], com_tlm_u_tlm_tx_vc0_buf_pool_raddr_l[5], +com_tlm_u_tlm_tx_vc0_buf_pool_raddr_l[4], com_tlm_u_tlm_tx_vc0_buf_pool_raddr_l[3], com_tlm_u_tlm_tx_vc0_buf_pool_raddr_l[2], +com_tlm_u_tlm_tx_vc0_buf_pool_raddr_l[1], com_tlm_u_tlm_tx_vc0_buf_pool_raddr_l[0]}), + .DOPA({NLW_com_tlm_u_tlm_tx_vc0_buf_pool_bram_0__size8_bram_array_ram_row_0__block_ram_4__ram2048x9_bram_DOPA_0__UNCONNECTED}), + .DIA({com_tlm_u_tlm_tx_vc0_buf_pool_wdata_43__2358, com_tlm_u_tlm_tx_vc0_buf_pool_wdata_42__2359, com_tlm_u_tlm_tx_vc0_buf_pool_wdata_41__2360, +com_tlm_u_tlm_tx_vc0_buf_pool_wdata_40__2361, com_tlm_u_tlm_tx_vc0_buf_pool_wdata_39__2362, com_tlm_u_tlm_tx_vc0_buf_pool_wdata_38__2363, +com_tlm_u_tlm_tx_vc0_buf_pool_wdata_37__2364, com_tlm_u_tlm_tx_vc0_buf_pool_wdata_36__2365}), + .DIB({com_tlm_u_tlm_tx_vc0_buf_pool_bram_0__size8_bram_array_GND_2408, com_tlm_u_tlm_tx_vc0_buf_pool_bram_0__size8_bram_array_GND_2408, +com_tlm_u_tlm_tx_vc0_buf_pool_bram_0__size8_bram_array_GND_2408, com_tlm_u_tlm_tx_vc0_buf_pool_bram_0__size8_bram_array_GND_2408, +com_tlm_u_tlm_tx_vc0_buf_pool_bram_0__size8_bram_array_GND_2408, com_tlm_u_tlm_tx_vc0_buf_pool_bram_0__size8_bram_array_GND_2408, +com_tlm_u_tlm_tx_vc0_buf_pool_bram_0__size8_bram_array_GND_2408, com_tlm_u_tlm_tx_vc0_buf_pool_bram_0__size8_bram_array_GND_2408}), + .DOPB({com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all[44]}), + .DIPA({com_tlm_u_tlm_tx_vc0_buf_pool_wdata_44__2357}), + .DOA({NLW_com_tlm_u_tlm_tx_vc0_buf_pool_bram_0__size8_bram_array_ram_row_0__block_ram_4__ram2048x9_bram_DOA_7__UNCONNECTED, +NLW_com_tlm_u_tlm_tx_vc0_buf_pool_bram_0__size8_bram_array_ram_row_0__block_ram_4__ram2048x9_bram_DOA_6__UNCONNECTED, +NLW_com_tlm_u_tlm_tx_vc0_buf_pool_bram_0__size8_bram_array_ram_row_0__block_ram_4__ram2048x9_bram_DOA_5__UNCONNECTED, +NLW_com_tlm_u_tlm_tx_vc0_buf_pool_bram_0__size8_bram_array_ram_row_0__block_ram_4__ram2048x9_bram_DOA_4__UNCONNECTED, +NLW_com_tlm_u_tlm_tx_vc0_buf_pool_bram_0__size8_bram_array_ram_row_0__block_ram_4__ram2048x9_bram_DOA_3__UNCONNECTED, +NLW_com_tlm_u_tlm_tx_vc0_buf_pool_bram_0__size8_bram_array_ram_row_0__block_ram_4__ram2048x9_bram_DOA_2__UNCONNECTED, +NLW_com_tlm_u_tlm_tx_vc0_buf_pool_bram_0__size8_bram_array_ram_row_0__block_ram_4__ram2048x9_bram_DOA_1__UNCONNECTED, +NLW_com_tlm_u_tlm_tx_vc0_buf_pool_bram_0__size8_bram_array_ram_row_0__block_ram_4__ram2048x9_bram_DOA_0__UNCONNECTED}), + .DOB({com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all[43], com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all[42], com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all[41], +com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all[40], com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all[39], com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all[38], +com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all[37], com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all[36]}) + ); + defparam com_tlm_u_tlm_tx_vc0_buf_pool_bram_0__size8_bram_array_ram_row_0__block_ram_6__ram2048x9_bram.WRITE_MODE_A = "NO_CHANGE"; + RAMB16_S9_S9 com_tlm_u_tlm_tx_vc0_buf_pool_bram_0__size8_bram_array_ram_row_0__block_ram_6__ram2048x9_bram ( + .ENA(com_tlm_u_tlm_tx_vc0_buf_pool_bram_0__size8_bram_array_VCC_2409), + .ENB(com_tlm_u_tlm_tx_vc0_buf_pool_bram_0__size8_bram_array_N_9690_i_2410), + .SSRA(com_reset_i_q), + .SSRB(com_reset_i_q), + .WEA(com_tlm_u_tlm_tx_vc0_buf_pool_N_22095_i), + .WEB(com_tlm_u_tlm_tx_vc0_buf_pool_bram_0__size8_bram_array_GND_2408), + .CLKA(NlwRenamedSig_OI_trn_clk), + .CLKB(NlwRenamedSig_OI_trn_clk), + .DIPB({com_tlm_u_tlm_tx_vc0_buf_pool_bram_0__size8_bram_array_GND_2408}), + .ADDRA({com_tlm_u_tlm_tx_vc0_buf_pool_waddr_h[3], com_tlm_u_tlm_tx_vc0_buf_pool_waddr_h[2], com_tlm_u_tlm_tx_vc0_buf_pool_waddr_h[1], +com_tlm_u_tlm_tx_vc0_buf_pool_waddr_h[0], com_tlm_u_tlm_tx_vc0_buf_pool_waddr_l[6], com_tlm_u_tlm_tx_vc0_buf_pool_waddr_l[5], +com_tlm_u_tlm_tx_vc0_buf_pool_waddr_l[4], com_tlm_u_tlm_tx_vc0_buf_pool_waddr_l[3], com_tlm_u_tlm_tx_vc0_buf_pool_waddr_l[2], +com_tlm_u_tlm_tx_vc0_buf_pool_waddr_l[1], com_tlm_u_tlm_tx_vc0_buf_pool_waddr_l[0]}), + .ADDRB({com_tlm_u_tlm_tx_vc0_buf_pool_raddr_h[3], com_tlm_u_tlm_tx_vc0_buf_pool_raddr_h[2], com_tlm_u_tlm_tx_vc0_buf_pool_raddr_h[1], +com_tlm_u_tlm_tx_vc0_buf_pool_raddr_h[0], com_tlm_u_tlm_tx_vc0_buf_pool_raddr_l[6], com_tlm_u_tlm_tx_vc0_buf_pool_raddr_l[5], +com_tlm_u_tlm_tx_vc0_buf_pool_raddr_l[4], com_tlm_u_tlm_tx_vc0_buf_pool_raddr_l[3], com_tlm_u_tlm_tx_vc0_buf_pool_raddr_l[2], +com_tlm_u_tlm_tx_vc0_buf_pool_raddr_l[1], com_tlm_u_tlm_tx_vc0_buf_pool_raddr_l[0]}), + .DOPA({NLW_com_tlm_u_tlm_tx_vc0_buf_pool_bram_0__size8_bram_array_ram_row_0__block_ram_6__ram2048x9_bram_DOPA_0__UNCONNECTED}), + .DIA({com_tlm_u_tlm_tx_vc0_buf_pool_wdata_61__2340, com_tlm_u_tlm_tx_vc0_buf_pool_wdata_60__2341, com_tlm_u_tlm_tx_vc0_buf_pool_wdata_59__2342, +com_tlm_u_tlm_tx_vc0_buf_pool_wdata_58__2343, com_tlm_u_tlm_tx_vc0_buf_pool_wdata_57__2344, com_tlm_u_tlm_tx_vc0_buf_pool_wdata_56__2345, +com_tlm_u_tlm_tx_vc0_buf_pool_wdata_55__2346, com_tlm_u_tlm_tx_vc0_buf_pool_wdata_54__2347}), + .DIB({com_tlm_u_tlm_tx_vc0_buf_pool_bram_0__size8_bram_array_GND_2408, com_tlm_u_tlm_tx_vc0_buf_pool_bram_0__size8_bram_array_GND_2408, +com_tlm_u_tlm_tx_vc0_buf_pool_bram_0__size8_bram_array_GND_2408, com_tlm_u_tlm_tx_vc0_buf_pool_bram_0__size8_bram_array_GND_2408, +com_tlm_u_tlm_tx_vc0_buf_pool_bram_0__size8_bram_array_GND_2408, com_tlm_u_tlm_tx_vc0_buf_pool_bram_0__size8_bram_array_GND_2408, +com_tlm_u_tlm_tx_vc0_buf_pool_bram_0__size8_bram_array_GND_2408, com_tlm_u_tlm_tx_vc0_buf_pool_bram_0__size8_bram_array_GND_2408}), + .DOPB({com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all[62]}), + .DIPA({com_tlm_u_tlm_tx_vc0_buf_pool_wdata_62__2339}), + .DOA({NLW_com_tlm_u_tlm_tx_vc0_buf_pool_bram_0__size8_bram_array_ram_row_0__block_ram_6__ram2048x9_bram_DOA_7__UNCONNECTED, +NLW_com_tlm_u_tlm_tx_vc0_buf_pool_bram_0__size8_bram_array_ram_row_0__block_ram_6__ram2048x9_bram_DOA_6__UNCONNECTED, +NLW_com_tlm_u_tlm_tx_vc0_buf_pool_bram_0__size8_bram_array_ram_row_0__block_ram_6__ram2048x9_bram_DOA_5__UNCONNECTED, +NLW_com_tlm_u_tlm_tx_vc0_buf_pool_bram_0__size8_bram_array_ram_row_0__block_ram_6__ram2048x9_bram_DOA_4__UNCONNECTED, +NLW_com_tlm_u_tlm_tx_vc0_buf_pool_bram_0__size8_bram_array_ram_row_0__block_ram_6__ram2048x9_bram_DOA_3__UNCONNECTED, +NLW_com_tlm_u_tlm_tx_vc0_buf_pool_bram_0__size8_bram_array_ram_row_0__block_ram_6__ram2048x9_bram_DOA_2__UNCONNECTED, +NLW_com_tlm_u_tlm_tx_vc0_buf_pool_bram_0__size8_bram_array_ram_row_0__block_ram_6__ram2048x9_bram_DOA_1__UNCONNECTED, +NLW_com_tlm_u_tlm_tx_vc0_buf_pool_bram_0__size8_bram_array_ram_row_0__block_ram_6__ram2048x9_bram_DOA_0__UNCONNECTED}), + .DOB({com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all[61], com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all[60], com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all[59], +com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all[58], com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all[57], com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all[56], +com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all[55], com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all[54]}) + ); + defparam com_tlm_u_tlm_tx_vc0_buf_pool_bram_0__size8_bram_array_ram_row_0__block_ram_7__ram2048x9_bram.WRITE_MODE_A = "NO_CHANGE"; + RAMB16_S9_S9 com_tlm_u_tlm_tx_vc0_buf_pool_bram_0__size8_bram_array_ram_row_0__block_ram_7__ram2048x9_bram ( + .ENA(com_tlm_u_tlm_tx_vc0_buf_pool_bram_0__size8_bram_array_VCC_2409), + .ENB(com_tlm_u_tlm_tx_vc0_buf_pool_bram_0__size8_bram_array_N_9690_i_2410), + .SSRA(com_reset_i_q), + .SSRB(com_reset_i_q), + .WEA(com_tlm_u_tlm_tx_vc0_buf_pool_N_22095_i), + .WEB(com_tlm_u_tlm_tx_vc0_buf_pool_bram_0__size8_bram_array_GND_2408), + .CLKA(NlwRenamedSig_OI_trn_clk), + .CLKB(NlwRenamedSig_OI_trn_clk), + .DIPB({com_tlm_u_tlm_tx_vc0_buf_pool_bram_0__size8_bram_array_GND_2408}), + .ADDRA({com_tlm_u_tlm_tx_vc0_buf_pool_waddr_h[3], com_tlm_u_tlm_tx_vc0_buf_pool_waddr_h[2], com_tlm_u_tlm_tx_vc0_buf_pool_waddr_h[1], +com_tlm_u_tlm_tx_vc0_buf_pool_waddr_h[0], com_tlm_u_tlm_tx_vc0_buf_pool_waddr_l[6], com_tlm_u_tlm_tx_vc0_buf_pool_waddr_l[5], +com_tlm_u_tlm_tx_vc0_buf_pool_waddr_l[4], com_tlm_u_tlm_tx_vc0_buf_pool_waddr_l[3], com_tlm_u_tlm_tx_vc0_buf_pool_waddr_l[2], +com_tlm_u_tlm_tx_vc0_buf_pool_waddr_l[1], com_tlm_u_tlm_tx_vc0_buf_pool_waddr_l[0]}), + .ADDRB({com_tlm_u_tlm_tx_vc0_buf_pool_raddr_h[3], com_tlm_u_tlm_tx_vc0_buf_pool_raddr_h[2], com_tlm_u_tlm_tx_vc0_buf_pool_raddr_h[1], +com_tlm_u_tlm_tx_vc0_buf_pool_raddr_h[0], com_tlm_u_tlm_tx_vc0_buf_pool_raddr_l[6], com_tlm_u_tlm_tx_vc0_buf_pool_raddr_l[5], +com_tlm_u_tlm_tx_vc0_buf_pool_raddr_l[4], com_tlm_u_tlm_tx_vc0_buf_pool_raddr_l[3], com_tlm_u_tlm_tx_vc0_buf_pool_raddr_l[2], +com_tlm_u_tlm_tx_vc0_buf_pool_raddr_l[1], com_tlm_u_tlm_tx_vc0_buf_pool_raddr_l[0]}), + .DOPA({NLW_com_tlm_u_tlm_tx_vc0_buf_pool_bram_0__size8_bram_array_ram_row_0__block_ram_7__ram2048x9_bram_DOPA_0__UNCONNECTED}), + .DIA({com_tlm_u_tlm_tx_vc0_buf_pool_bram_0__size8_bram_array_GND_2408, com_tlm_u_tlm_tx_vc0_buf_pool_bram_0__size8_bram_array_GND_2408, +com_tlm_u_tlm_tx_vc0_buf_pool_wdata_68_, com_tlm_u_tlm_tx_vc0_trn_eof, com_tlm_u_tlm_tx_vc0_buf_pool_wdata_66__2335, +com_tlm_u_tlm_tx_vc0_buf_pool_wdata_65__2336, com_tlm_u_tlm_tx_vc0_buf_pool_wdata_64__2337, com_tlm_u_tlm_tx_vc0_buf_pool_wdata_63__2338}), + .DIB({com_tlm_u_tlm_tx_vc0_buf_pool_bram_0__size8_bram_array_GND_2408, com_tlm_u_tlm_tx_vc0_buf_pool_bram_0__size8_bram_array_GND_2408, +com_tlm_u_tlm_tx_vc0_buf_pool_bram_0__size8_bram_array_GND_2408, com_tlm_u_tlm_tx_vc0_buf_pool_bram_0__size8_bram_array_GND_2408, +com_tlm_u_tlm_tx_vc0_buf_pool_bram_0__size8_bram_array_GND_2408, com_tlm_u_tlm_tx_vc0_buf_pool_bram_0__size8_bram_array_GND_2408, +com_tlm_u_tlm_tx_vc0_buf_pool_bram_0__size8_bram_array_GND_2408, com_tlm_u_tlm_tx_vc0_buf_pool_bram_0__size8_bram_array_GND_2408}), + .DOPB({NLW_com_tlm_u_tlm_tx_vc0_buf_pool_bram_0__size8_bram_array_ram_row_0__block_ram_7__ram2048x9_bram_DOPB_0__UNCONNECTED}), + .DIPA({com_tlm_u_tlm_tx_vc0_buf_pool_bram_0__size8_bram_array_GND_2408}), + .DOA({NLW_com_tlm_u_tlm_tx_vc0_buf_pool_bram_0__size8_bram_array_ram_row_0__block_ram_7__ram2048x9_bram_DOA_7__UNCONNECTED, +NLW_com_tlm_u_tlm_tx_vc0_buf_pool_bram_0__size8_bram_array_ram_row_0__block_ram_7__ram2048x9_bram_DOA_6__UNCONNECTED, +NLW_com_tlm_u_tlm_tx_vc0_buf_pool_bram_0__size8_bram_array_ram_row_0__block_ram_7__ram2048x9_bram_DOA_5__UNCONNECTED, +NLW_com_tlm_u_tlm_tx_vc0_buf_pool_bram_0__size8_bram_array_ram_row_0__block_ram_7__ram2048x9_bram_DOA_4__UNCONNECTED, +NLW_com_tlm_u_tlm_tx_vc0_buf_pool_bram_0__size8_bram_array_ram_row_0__block_ram_7__ram2048x9_bram_DOA_3__UNCONNECTED, +NLW_com_tlm_u_tlm_tx_vc0_buf_pool_bram_0__size8_bram_array_ram_row_0__block_ram_7__ram2048x9_bram_DOA_2__UNCONNECTED, +NLW_com_tlm_u_tlm_tx_vc0_buf_pool_bram_0__size8_bram_array_ram_row_0__block_ram_7__ram2048x9_bram_DOA_1__UNCONNECTED, +NLW_com_tlm_u_tlm_tx_vc0_buf_pool_bram_0__size8_bram_array_ram_row_0__block_ram_7__ram2048x9_bram_DOA_0__UNCONNECTED}), + .DOB({NLW_com_tlm_u_tlm_tx_vc0_buf_pool_bram_0__size8_bram_array_ram_row_0__block_ram_7__ram2048x9_bram_DOB_7__UNCONNECTED, +NLW_com_tlm_u_tlm_tx_vc0_buf_pool_bram_0__size8_bram_array_ram_row_0__block_ram_7__ram2048x9_bram_DOB_6__UNCONNECTED, +com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all[68], com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all[67], com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all[66], +com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all[65], com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all[64], com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all[63]}) + ); + defparam com_tlm_u_tlm_tx_vc0_buf_pool_bram_0__size8_bram_array_ram_row_0__block_ram_2__ram2048x9_bram.WRITE_MODE_A = "NO_CHANGE"; + RAMB16_S9_S9 com_tlm_u_tlm_tx_vc0_buf_pool_bram_0__size8_bram_array_ram_row_0__block_ram_2__ram2048x9_bram ( + .ENA(com_tlm_u_tlm_tx_vc0_buf_pool_bram_0__size8_bram_array_VCC_2409), + .ENB(com_tlm_u_tlm_tx_vc0_buf_pool_bram_0__size8_bram_array_N_9690_i_2410), + .SSRA(com_reset_i_q), + .SSRB(com_reset_i_q), + .WEA(com_tlm_u_tlm_tx_vc0_buf_pool_N_22095_i), + .WEB(com_tlm_u_tlm_tx_vc0_buf_pool_bram_0__size8_bram_array_GND_2408), + .CLKA(NlwRenamedSig_OI_trn_clk), + .CLKB(NlwRenamedSig_OI_trn_clk), + .DIPB({com_tlm_u_tlm_tx_vc0_buf_pool_bram_0__size8_bram_array_GND_2408}), + .ADDRA({com_tlm_u_tlm_tx_vc0_buf_pool_waddr_h[3], com_tlm_u_tlm_tx_vc0_buf_pool_waddr_h[2], com_tlm_u_tlm_tx_vc0_buf_pool_waddr_h[1], +com_tlm_u_tlm_tx_vc0_buf_pool_waddr_h[0], com_tlm_u_tlm_tx_vc0_buf_pool_waddr_l[6], com_tlm_u_tlm_tx_vc0_buf_pool_waddr_l[5], +com_tlm_u_tlm_tx_vc0_buf_pool_waddr_l[4], com_tlm_u_tlm_tx_vc0_buf_pool_waddr_l[3], com_tlm_u_tlm_tx_vc0_buf_pool_waddr_l[2], +com_tlm_u_tlm_tx_vc0_buf_pool_waddr_l[1], com_tlm_u_tlm_tx_vc0_buf_pool_waddr_l[0]}), + .ADDRB({com_tlm_u_tlm_tx_vc0_buf_pool_raddr_h[3], com_tlm_u_tlm_tx_vc0_buf_pool_raddr_h[2], com_tlm_u_tlm_tx_vc0_buf_pool_raddr_h[1], +com_tlm_u_tlm_tx_vc0_buf_pool_raddr_h[0], com_tlm_u_tlm_tx_vc0_buf_pool_raddr_l[6], com_tlm_u_tlm_tx_vc0_buf_pool_raddr_l[5], +com_tlm_u_tlm_tx_vc0_buf_pool_raddr_l[4], com_tlm_u_tlm_tx_vc0_buf_pool_raddr_l[3], com_tlm_u_tlm_tx_vc0_buf_pool_raddr_l[2], +com_tlm_u_tlm_tx_vc0_buf_pool_raddr_l[1], com_tlm_u_tlm_tx_vc0_buf_pool_raddr_l[0]}), + .DOPA({NLW_com_tlm_u_tlm_tx_vc0_buf_pool_bram_0__size8_bram_array_ram_row_0__block_ram_2__ram2048x9_bram_DOPA_0__UNCONNECTED}), + .DIA({com_tlm_u_tlm_tx_vc0_buf_pool_wdata_25__2376, com_tlm_u_tlm_tx_vc0_buf_pool_wdata_24__2377, com_tlm_u_tlm_tx_vc0_buf_pool_wdata_23__2378, +com_tlm_u_tlm_tx_vc0_buf_pool_wdata_22__2379, com_tlm_u_tlm_tx_vc0_buf_pool_wdata_21__2380, com_tlm_u_tlm_tx_vc0_buf_pool_wdata_20__2381, +com_tlm_u_tlm_tx_vc0_buf_pool_wdata_19__2382, com_tlm_u_tlm_tx_vc0_buf_pool_wdata_18__2383}), + .DIB({com_tlm_u_tlm_tx_vc0_buf_pool_bram_0__size8_bram_array_GND_2408, com_tlm_u_tlm_tx_vc0_buf_pool_bram_0__size8_bram_array_GND_2408, +com_tlm_u_tlm_tx_vc0_buf_pool_bram_0__size8_bram_array_GND_2408, com_tlm_u_tlm_tx_vc0_buf_pool_bram_0__size8_bram_array_GND_2408, +com_tlm_u_tlm_tx_vc0_buf_pool_bram_0__size8_bram_array_GND_2408, com_tlm_u_tlm_tx_vc0_buf_pool_bram_0__size8_bram_array_GND_2408, +com_tlm_u_tlm_tx_vc0_buf_pool_bram_0__size8_bram_array_GND_2408, com_tlm_u_tlm_tx_vc0_buf_pool_bram_0__size8_bram_array_GND_2408}), + .DOPB({com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all[26]}), + .DIPA({com_tlm_u_tlm_tx_vc0_buf_pool_wdata_26__2375}), + .DOA({NLW_com_tlm_u_tlm_tx_vc0_buf_pool_bram_0__size8_bram_array_ram_row_0__block_ram_2__ram2048x9_bram_DOA_7__UNCONNECTED, +NLW_com_tlm_u_tlm_tx_vc0_buf_pool_bram_0__size8_bram_array_ram_row_0__block_ram_2__ram2048x9_bram_DOA_6__UNCONNECTED, +NLW_com_tlm_u_tlm_tx_vc0_buf_pool_bram_0__size8_bram_array_ram_row_0__block_ram_2__ram2048x9_bram_DOA_5__UNCONNECTED, +NLW_com_tlm_u_tlm_tx_vc0_buf_pool_bram_0__size8_bram_array_ram_row_0__block_ram_2__ram2048x9_bram_DOA_4__UNCONNECTED, +NLW_com_tlm_u_tlm_tx_vc0_buf_pool_bram_0__size8_bram_array_ram_row_0__block_ram_2__ram2048x9_bram_DOA_3__UNCONNECTED, +NLW_com_tlm_u_tlm_tx_vc0_buf_pool_bram_0__size8_bram_array_ram_row_0__block_ram_2__ram2048x9_bram_DOA_2__UNCONNECTED, +NLW_com_tlm_u_tlm_tx_vc0_buf_pool_bram_0__size8_bram_array_ram_row_0__block_ram_2__ram2048x9_bram_DOA_1__UNCONNECTED, +NLW_com_tlm_u_tlm_tx_vc0_buf_pool_bram_0__size8_bram_array_ram_row_0__block_ram_2__ram2048x9_bram_DOA_0__UNCONNECTED}), + .DOB({com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all[25], com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all[24], com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all[23], +com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all[22], com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all[21], com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all[20], +com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all[19], com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all[18]}) + ); + defparam com_tlm_u_tlm_tx_vc0_buf_pool_bram_0__size8_bram_array_ram_row_0__block_ram_5__ram2048x9_bram.WRITE_MODE_A = "NO_CHANGE"; + RAMB16_S9_S9 com_tlm_u_tlm_tx_vc0_buf_pool_bram_0__size8_bram_array_ram_row_0__block_ram_5__ram2048x9_bram ( + .ENA(com_tlm_u_tlm_tx_vc0_buf_pool_bram_0__size8_bram_array_VCC_2409), + .ENB(com_tlm_u_tlm_tx_vc0_buf_pool_bram_0__size8_bram_array_N_9690_i_2410), + .SSRA(com_reset_i_q), + .SSRB(com_reset_i_q), + .WEA(com_tlm_u_tlm_tx_vc0_buf_pool_N_22095_i), + .WEB(com_tlm_u_tlm_tx_vc0_buf_pool_bram_0__size8_bram_array_GND_2408), + .CLKA(NlwRenamedSig_OI_trn_clk), + .CLKB(NlwRenamedSig_OI_trn_clk), + .DIPB({com_tlm_u_tlm_tx_vc0_buf_pool_bram_0__size8_bram_array_GND_2408}), + .ADDRA({com_tlm_u_tlm_tx_vc0_buf_pool_waddr_h[3], com_tlm_u_tlm_tx_vc0_buf_pool_waddr_h[2], com_tlm_u_tlm_tx_vc0_buf_pool_waddr_h[1], +com_tlm_u_tlm_tx_vc0_buf_pool_waddr_h[0], com_tlm_u_tlm_tx_vc0_buf_pool_waddr_l[6], com_tlm_u_tlm_tx_vc0_buf_pool_waddr_l[5], +com_tlm_u_tlm_tx_vc0_buf_pool_waddr_l[4], com_tlm_u_tlm_tx_vc0_buf_pool_waddr_l[3], com_tlm_u_tlm_tx_vc0_buf_pool_waddr_l[2], +com_tlm_u_tlm_tx_vc0_buf_pool_waddr_l[1], com_tlm_u_tlm_tx_vc0_buf_pool_waddr_l[0]}), + .ADDRB({com_tlm_u_tlm_tx_vc0_buf_pool_raddr_h[3], com_tlm_u_tlm_tx_vc0_buf_pool_raddr_h[2], com_tlm_u_tlm_tx_vc0_buf_pool_raddr_h[1], +com_tlm_u_tlm_tx_vc0_buf_pool_raddr_h[0], com_tlm_u_tlm_tx_vc0_buf_pool_raddr_l[6], com_tlm_u_tlm_tx_vc0_buf_pool_raddr_l[5], +com_tlm_u_tlm_tx_vc0_buf_pool_raddr_l[4], com_tlm_u_tlm_tx_vc0_buf_pool_raddr_l[3], com_tlm_u_tlm_tx_vc0_buf_pool_raddr_l[2], +com_tlm_u_tlm_tx_vc0_buf_pool_raddr_l[1], com_tlm_u_tlm_tx_vc0_buf_pool_raddr_l[0]}), + .DOPA({NLW_com_tlm_u_tlm_tx_vc0_buf_pool_bram_0__size8_bram_array_ram_row_0__block_ram_5__ram2048x9_bram_DOPA_0__UNCONNECTED}), + .DIA({com_tlm_u_tlm_tx_vc0_buf_pool_wdata_52__2349, com_tlm_u_tlm_tx_vc0_buf_pool_wdata_51__2350, com_tlm_u_tlm_tx_vc0_buf_pool_wdata_50__2351, +com_tlm_u_tlm_tx_vc0_buf_pool_wdata_49__2352, com_tlm_u_tlm_tx_vc0_buf_pool_wdata_48__2353, com_tlm_u_tlm_tx_vc0_buf_pool_wdata_47__2354, +com_tlm_u_tlm_tx_vc0_buf_pool_wdata_46__2355, com_tlm_u_tlm_tx_vc0_buf_pool_wdata_45__2356}), + .DIB({com_tlm_u_tlm_tx_vc0_buf_pool_bram_0__size8_bram_array_GND_2408, com_tlm_u_tlm_tx_vc0_buf_pool_bram_0__size8_bram_array_GND_2408, +com_tlm_u_tlm_tx_vc0_buf_pool_bram_0__size8_bram_array_GND_2408, com_tlm_u_tlm_tx_vc0_buf_pool_bram_0__size8_bram_array_GND_2408, +com_tlm_u_tlm_tx_vc0_buf_pool_bram_0__size8_bram_array_GND_2408, com_tlm_u_tlm_tx_vc0_buf_pool_bram_0__size8_bram_array_GND_2408, +com_tlm_u_tlm_tx_vc0_buf_pool_bram_0__size8_bram_array_GND_2408, com_tlm_u_tlm_tx_vc0_buf_pool_bram_0__size8_bram_array_GND_2408}), + .DOPB({com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all[53]}), + .DIPA({com_tlm_u_tlm_tx_vc0_buf_pool_wdata_53__2348}), + .DOA({NLW_com_tlm_u_tlm_tx_vc0_buf_pool_bram_0__size8_bram_array_ram_row_0__block_ram_5__ram2048x9_bram_DOA_7__UNCONNECTED, +NLW_com_tlm_u_tlm_tx_vc0_buf_pool_bram_0__size8_bram_array_ram_row_0__block_ram_5__ram2048x9_bram_DOA_6__UNCONNECTED, +NLW_com_tlm_u_tlm_tx_vc0_buf_pool_bram_0__size8_bram_array_ram_row_0__block_ram_5__ram2048x9_bram_DOA_5__UNCONNECTED, +NLW_com_tlm_u_tlm_tx_vc0_buf_pool_bram_0__size8_bram_array_ram_row_0__block_ram_5__ram2048x9_bram_DOA_4__UNCONNECTED, +NLW_com_tlm_u_tlm_tx_vc0_buf_pool_bram_0__size8_bram_array_ram_row_0__block_ram_5__ram2048x9_bram_DOA_3__UNCONNECTED, +NLW_com_tlm_u_tlm_tx_vc0_buf_pool_bram_0__size8_bram_array_ram_row_0__block_ram_5__ram2048x9_bram_DOA_2__UNCONNECTED, +NLW_com_tlm_u_tlm_tx_vc0_buf_pool_bram_0__size8_bram_array_ram_row_0__block_ram_5__ram2048x9_bram_DOA_1__UNCONNECTED, +NLW_com_tlm_u_tlm_tx_vc0_buf_pool_bram_0__size8_bram_array_ram_row_0__block_ram_5__ram2048x9_bram_DOA_0__UNCONNECTED}), + .DOB({com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all[52], com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all[51], com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all[50], +com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all[49], com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all[48], com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all[47], +com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all[46], com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all[45]}) + ); + defparam com_tlm_u_tlm_tx_vc0_buf_pool_bram_0__size8_bram_array_N_9690_i.INIT = 4'hE; + LUT2 com_tlm_u_tlm_tx_vc0_buf_pool_bram_0__size8_bram_array_N_9690_i ( + .I0(com_reset_i_q), + .I1(com_tlm_u_tlm_tx_vc0_buf_pool_en_ram_i_i), + .O(com_tlm_u_tlm_tx_vc0_buf_pool_bram_0__size8_bram_array_N_9690_i_2410) + ); + VCC com_tlm_u_tlm_tx_vc0_trn_VCC ( + .P(com_tlm_u_tlm_tx_vc0_trn_VCC_2500) + ); + GND com_tlm_u_tlm_tx_vc0_trn_GND ( + .G(com_tlm_u_tlm_tx_vc0_trn_GND_2498) + ); + FDR com_tlm_u_tlm_tx_vc0_trn_pkts_in_trn_0_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_trn_un1_pkts_in_trn_1_axb0_2504), + .Q(com_tlm_u_tlm_tx_vc0_trn_pkts_in_trn[0]), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_tx_vc0_trn_pkts_in_trn_1_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_trn_un1_pkts_in_trn_1_axbxc1_2468), + .Q(com_tlm_u_tlm_tx_vc0_trn_pkts_in_trn[1]), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_tx_vc0_trn_trn_tbuf_av_o_0_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_trn_un1_trn_tbuf_av_o_1_axb_0_2433), + .Q(NlwRenamedSig_OI_trn_tbuf_av[0]), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_tx_vc0_trn_trn_tbuf_av_o_1_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_trn_un1_trn_tbuf_av_o_1_s_1_2412), + .Q(NlwRenamedSig_OI_trn_tbuf_av[1]), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_tx_vc0_trn_trn_tbuf_av_o_2_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_trn_un1_trn_tbuf_av_o_1_s_2_2415), + .Q(NlwRenamedSig_OI_trn_tbuf_av[2]), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_tx_vc0_trn_trn_tbuf_av_o_3_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_trn_un1_trn_tbuf_av_o_1_s_3_2418), + .Q(NlwRenamedSig_OI_trn_tbuf_av[3]), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_tx_vc0_trn_trn_tbuf_av_o_4_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_trn_un1_trn_tbuf_av_o_1_s_4_2420), + .Q(NlwRenamedSig_OI_trn_tbuf_av[4]), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_tx_vc0_trn_buffer_rdy ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_trn_N_13653_i), + .Q(com_tlm_u_tlm_tx_vc0_trn_buffer_rdy_2427), + .R(plm_link_up_i) + ); + FDSE com_tlm_u_tlm_tx_vc0_trn_buf_av_one ( + .CE(com_tlm_u_tlm_tx_vc0_trn_N_68959_i_2438), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_trn_N_13806_i), + .Q(com_tlm_u_tlm_tx_vc0_trn_buf_av_one_2463), + .S(plm_link_up_i) + ); + FDSE com_tlm_u_tlm_tx_vc0_trn_buf_av_zero ( + .CE(com_tlm_u_tlm_tx_vc0_trn_N_68960_i_2437), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_trn_N_13806_i), + .Q(com_tlm_u_tlm_tx_vc0_trn_buf_av_zero_2426), + .S(plm_link_up_i) + ); + FDR com_tlm_u_tlm_tx_vc0_trn_trn_tdst_rdy_o ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_trn_N_68987_i_2460), + .Q(com_tlm_u_tlm_tx_vc0_trn_trn_tdst_rdy), + .R(plm_link_up_i) + ); + FDRSE com_tlm_u_tlm_tx_vc0_trn_usr_calc_eof ( + .CE(com_tlm_u_tlm_tx_vc0_trn_N_48897_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_trn_GND_2498), + .Q(com_tlm_u_tlm_tx_vc0_trn_usr_calc_eof_2440), + .R(plm_link_up_i), + .S(com_tlm_u_tlm_tx_vc0_trn_N_13650_i) + ); + FDR com_tlm_u_tlm_tx_vc0_trn_cmm_tdst_rdy_o ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_trn_N_68986_i_2458), + .Q(com_cmmt_tdst_rdy), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_tx_vc0_trn_dsc_in_q ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_trn_N_28290_i), + .Q(com_tlm_u_tlm_tx_vc0_trn_dsc_in_q_2425), + .R(plm_link_up_i) + ); + FDRS com_tlm_u_tlm_tx_vc0_trn_vld_o ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_trn_N_68621_i_2454), + .Q(com_tlm_u_tlm_tx_vc0_trn_vld), + .R(plm_link_up_i), + .S(com_tlm_u_tlm_tx_vc0_trn_vld_o_5_i_i_a2_i_a2_2456) + ); + FDS com_tlm_u_tlm_tx_vc0_trn_rem_o ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_trn_N_68115_i_2452), + .Q(com_tlm_u_tlm_tx_vc0_trn_trn_rem), + .S(plm_link_up_i) + ); + FDR com_tlm_u_tlm_tx_vc0_trn_sof_o ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_trn_N_68957_i_2449), + .Q(com_tlm_u_tlm_tx_vc0_trn_sof), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_tx_vc0_trn_errfwd_o ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_trn_N_28286_i), + .Q(com_tlm_u_tlm_tx_vc0_trn_errfwd), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_tx_vc0_trn_eof_o ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_trn_N_28284_i), + .Q(com_tlm_u_tlm_tx_vc0_trn_eof), + .R(plm_link_up_i) + ); + FDRSE com_tlm_u_tlm_tx_vc0_trn_usr_frame ( + .CE(com_tlm_u_tlm_tx_vc0_trn_N_68766_i_2429), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_trn_GND_2498), + .Q(com_tlm_u_tlm_tx_vc0_trn_usr_frame_2451), + .R(plm_link_up_i), + .S(com_tlm_u_tlm_tx_vc0_trn_un1_usr_vld_0_a4_0_a2_0_a2_0_a2_2422) + ); + FDRE com_tlm_u_tlm_tx_vc0_trn_usr_frame_in ( + .CE(com_tlm_u_tlm_tx_vc0_trn_N_67955_i_2432), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_trn_usr_frame_in17), + .Q(com_tlm_u_tlm_tx_vc0_trn_usr_frame_in_2461), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_tx_vc0_trn_start_frame_q ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_trn_N_68962_i_2446), + .Q(com_tlm_u_tlm_tx_vc0_trn_start_frame_q_2470), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_tx_vc0_trn_load_counter_q ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_trn_load_counter_2503), + .Q(com_tlm_u_tlm_tx_vc0_trn_load_counter_q_2423), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_tx_vc0_trn_usr_abort ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_trn_N_13635_i), + .Q(com_tlm_u_tlm_tx_vc0_trn_usr_abort_2496), + .R(plm_link_up_i) + ); + FDRE com_tlm_u_tlm_tx_vc0_trn_cfg_frame_in ( + .CE(com_tlm_u_tlm_tx_vc0_trn_N_13633_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmmt_trem_n_0_sqmuxa), + .Q(com_tlm_u_tlm_tx_vc0_trn_cfg_frame_in_2459), + .R(plm_link_up_i) + ); + FDRE com_tlm_u_tlm_tx_vc0_trn_load_counter ( + .CE(com_tlm_u_tlm_tx_vc0_trn_N_48897_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_trn_usr_start), + .Q(com_tlm_u_tlm_tx_vc0_trn_load_counter_2503), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_tx_vc0_trn_pkt_incoming_o ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_trn_un13_pkt_incoming_o_i_2445), + .Q(com_tlm_u_tlm_tx_pkt_incoming), + .R(plm_link_up_i) + ); + FDS com_tlm_u_tlm_tx_vc0_trn_usr_rem ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_trn_N_49952_i_2444), + .Q(com_tlm_u_tlm_tx_vc0_trn_usr_rem_2453), + .S(plm_link_up_i) + ); + FDR com_tlm_u_tlm_tx_vc0_trn_usr_eof_filt_q_1_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_trn_usr_eof_filt), + .Q(com_tlm_u_tlm_tx_vc0_trn_usr_eof_filt_q_1__2497), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_tx_vc0_trn_cfg_accepted_o ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_trn_cfg_start), + .Q(com_tlm_u_tlm_tx_cfg_accepted), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_tx_vc0_trn_usr_eof ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_trn_N_49953_i_2442), + .Q(com_tlm_u_tlm_tx_vc0_trn_usr_eof_2443), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_tx_vc0_trn_usr_dsc ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_trn_N_48986_i_i_2441), + .Q(com_tlm_u_tlm_tx_vc0_trn_usr_dsc_2430), + .R(plm_link_up_i) + ); + FDRSE com_tlm_u_tlm_tx_vc0_trn_released_buf_x ( + .CE(com_tlm_u_tlm_tx_vc0_trn_usr_abort_i_2495), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_trn_GND_2498), + .Q(com_tlm_u_tlm_tx_vc0_trn_released_buf_x_2469), + .R(plm_link_up_i), + .S(com_tlm_u_tlm_tx_vc0_released_buf) + ); + FDR com_tlm_u_tlm_tx_vc0_trn_usr_sof ( + .C(NlwRenamedSig_OI_trn_clk), + .D(trn_tsof_n_i), + .Q(com_tlm_u_tlm_tx_vc0_trn_usr_sof_2424), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_tx_vc0_trn_usr_errfwd ( + .C(NlwRenamedSig_OI_trn_clk), + .D(trn_terrfwd_n_i), + .Q(com_tlm_u_tlm_tx_vc0_trn_usr_errfwd_2448), + .R(plm_link_up_i) + ); + MUXCY_L com_tlm_u_tlm_tx_vc0_trn_un1_trn_tbuf_av_o_1_cry_0 ( + .CI(com_tlm_u_tlm_tx_vc0_trn_GND_2498), + .DI(com_tlm_u_tlm_tx_vc0_trn_un1_trn_tbuf_av_o_1_cry_0_ma_2499), + .LO(com_tlm_u_tlm_tx_vc0_trn_un1_trn_tbuf_av_o_1_cry_0_2413), + .S(com_tlm_u_tlm_tx_vc0_trn_un1_trn_tbuf_av_o_1_axb_0_2433) + ); + MULT_AND com_tlm_u_tlm_tx_vc0_trn_un1_trn_tbuf_av_o_1_cry_1 ( + .I0(com_tlm_u_tlm_tx_vc0_trn_N_13806_i), + .I1(com_tlm_u_tlm_tx_vc0_trn_start_frame_q_2470), + .LO(com_tlm_u_tlm_tx_vc0_trn_un1_trn_tbuf_av_o_1_cry_1_0_2411) + ); + MUXCY_L com_tlm_u_tlm_tx_vc0_trn_un1_trn_tbuf_av_o_1_cry_1_0 ( + .CI(com_tlm_u_tlm_tx_vc0_trn_un1_trn_tbuf_av_o_1_cry_0_2413), + .DI(com_tlm_u_tlm_tx_vc0_trn_un1_trn_tbuf_av_o_1_cry_1_0_2411), + .LO(com_tlm_u_tlm_tx_vc0_trn_un1_trn_tbuf_av_o_1_cry_1_2416), + .S(com_tlm_u_tlm_tx_vc0_trn_un1_trn_tbuf_av_o_1_axb_1_2467) + ); + XORCY com_tlm_u_tlm_tx_vc0_trn_un1_trn_tbuf_av_o_1_s_1 ( + .CI(com_tlm_u_tlm_tx_vc0_trn_un1_trn_tbuf_av_o_1_cry_0_2413), + .LI(com_tlm_u_tlm_tx_vc0_trn_un1_trn_tbuf_av_o_1_axb_1_2467), + .O(com_tlm_u_tlm_tx_vc0_trn_un1_trn_tbuf_av_o_1_s_1_2412) + ); + MULT_AND com_tlm_u_tlm_tx_vc0_trn_un1_trn_tbuf_av_o_1_cry_2 ( + .I0(com_tlm_u_tlm_tx_vc0_trn_N_13806_i), + .I1(com_tlm_u_tlm_tx_vc0_trn_start_frame_q_2470), + .LO(com_tlm_u_tlm_tx_vc0_trn_un1_trn_tbuf_av_o_1_cry_2_0_2414) + ); + MUXCY_L com_tlm_u_tlm_tx_vc0_trn_un1_trn_tbuf_av_o_1_cry_2_0 ( + .CI(com_tlm_u_tlm_tx_vc0_trn_un1_trn_tbuf_av_o_1_cry_1_2416), + .DI(com_tlm_u_tlm_tx_vc0_trn_un1_trn_tbuf_av_o_1_cry_2_0_2414), + .LO(com_tlm_u_tlm_tx_vc0_trn_un1_trn_tbuf_av_o_1_cry_2_2419), + .S(com_tlm_u_tlm_tx_vc0_trn_un1_trn_tbuf_av_o_1_axb_2_2466) + ); + XORCY com_tlm_u_tlm_tx_vc0_trn_un1_trn_tbuf_av_o_1_s_2 ( + .CI(com_tlm_u_tlm_tx_vc0_trn_un1_trn_tbuf_av_o_1_cry_1_2416), + .LI(com_tlm_u_tlm_tx_vc0_trn_un1_trn_tbuf_av_o_1_axb_2_2466), + .O(com_tlm_u_tlm_tx_vc0_trn_un1_trn_tbuf_av_o_1_s_2_2415) + ); + MULT_AND com_tlm_u_tlm_tx_vc0_trn_un1_trn_tbuf_av_o_1_cry_3 ( + .I0(com_tlm_u_tlm_tx_vc0_trn_N_13806_i), + .I1(com_tlm_u_tlm_tx_vc0_trn_start_frame_q_2470), + .LO(com_tlm_u_tlm_tx_vc0_trn_un1_trn_tbuf_av_o_1_cry_3_0_2417) + ); + MUXCY_L com_tlm_u_tlm_tx_vc0_trn_un1_trn_tbuf_av_o_1_cry_3_0 ( + .CI(com_tlm_u_tlm_tx_vc0_trn_un1_trn_tbuf_av_o_1_cry_2_2419), + .DI(com_tlm_u_tlm_tx_vc0_trn_un1_trn_tbuf_av_o_1_cry_3_0_2417), + .LO(com_tlm_u_tlm_tx_vc0_trn_un1_trn_tbuf_av_o_1_cry_3_2421), + .S(com_tlm_u_tlm_tx_vc0_trn_un1_trn_tbuf_av_o_1_axb_3_2465) + ); + XORCY com_tlm_u_tlm_tx_vc0_trn_un1_trn_tbuf_av_o_1_s_3 ( + .CI(com_tlm_u_tlm_tx_vc0_trn_un1_trn_tbuf_av_o_1_cry_2_2419), + .LI(com_tlm_u_tlm_tx_vc0_trn_un1_trn_tbuf_av_o_1_axb_3_2465), + .O(com_tlm_u_tlm_tx_vc0_trn_un1_trn_tbuf_av_o_1_s_3_2418) + ); + XORCY com_tlm_u_tlm_tx_vc0_trn_un1_trn_tbuf_av_o_1_s_4 ( + .CI(com_tlm_u_tlm_tx_vc0_trn_un1_trn_tbuf_av_o_1_cry_3_2421), + .LI(com_tlm_u_tlm_tx_vc0_trn_un1_trn_tbuf_av_o_1_axb_4_2464), + .O(com_tlm_u_tlm_tx_vc0_trn_un1_trn_tbuf_av_o_1_s_4_2420) + ); + MUXCY_L com_tlm_u_tlm_tx_vc0_trn_len_counter_cry_0_ ( + .CI(com_tlm_u_tlm_tx_vc0_trn_load_counter_2503), + .DI(com_tlm_u_tlm_tx_vc0_trn_VCC_2500), + .LO(com_tlm_u_tlm_tx_vc0_trn_len_counter_cry[0]), + .S(com_tlm_u_tlm_tx_vc0_trn_len_counter_qxu[0]) + ); + XORCY com_tlm_u_tlm_tx_vc0_trn_len_counter_s_0_ ( + .CI(com_tlm_u_tlm_tx_vc0_trn_load_counter_2503), + .LI(com_tlm_u_tlm_tx_vc0_trn_len_counter_qxu[0]), + .O(com_tlm_u_tlm_tx_vc0_trn_len_counter_s[0]) + ); + FDRE com_tlm_u_tlm_tx_vc0_trn_len_counter_0_ ( + .CE(com_tlm_u_tlm_tx_vc0_trn_N_48897_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_trn_len_counter_s[0]), + .Q(com_tlm_u_tlm_tx_vc0_trn_len_counter[0]), + .R(plm_link_up_i) + ); + MUXCY_L com_tlm_u_tlm_tx_vc0_trn_len_counter_cry_1_ ( + .CI(com_tlm_u_tlm_tx_vc0_trn_len_counter_cry[0]), + .DI(com_tlm_u_tlm_tx_vc0_trn_VCC_2500), + .LO(com_tlm_u_tlm_tx_vc0_trn_len_counter_cry[1]), + .S(com_tlm_u_tlm_tx_vc0_trn_len_counter_qxu[1]) + ); + XORCY com_tlm_u_tlm_tx_vc0_trn_len_counter_s_1_ ( + .CI(com_tlm_u_tlm_tx_vc0_trn_len_counter_cry[0]), + .LI(com_tlm_u_tlm_tx_vc0_trn_len_counter_qxu[1]), + .O(com_tlm_u_tlm_tx_vc0_trn_len_counter_s[1]) + ); + FDRE com_tlm_u_tlm_tx_vc0_trn_len_counter_1_ ( + .CE(com_tlm_u_tlm_tx_vc0_trn_N_48897_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_trn_len_counter_s[1]), + .Q(com_tlm_u_tlm_tx_vc0_trn_len_counter[1]), + .R(plm_link_up_i) + ); + MUXCY_L com_tlm_u_tlm_tx_vc0_trn_len_counter_cry_2_ ( + .CI(com_tlm_u_tlm_tx_vc0_trn_len_counter_cry[1]), + .DI(com_tlm_u_tlm_tx_vc0_trn_VCC_2500), + .LO(com_tlm_u_tlm_tx_vc0_trn_len_counter_cry[2]), + .S(com_tlm_u_tlm_tx_vc0_trn_len_counter_qxu[2]) + ); + XORCY com_tlm_u_tlm_tx_vc0_trn_len_counter_s_2_ ( + .CI(com_tlm_u_tlm_tx_vc0_trn_len_counter_cry[1]), + .LI(com_tlm_u_tlm_tx_vc0_trn_len_counter_qxu[2]), + .O(com_tlm_u_tlm_tx_vc0_trn_len_counter_s[2]) + ); + FDRE com_tlm_u_tlm_tx_vc0_trn_len_counter_2_ ( + .CE(com_tlm_u_tlm_tx_vc0_trn_N_48897_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_trn_len_counter_s[2]), + .Q(com_tlm_u_tlm_tx_vc0_trn_len_counter[2]), + .R(plm_link_up_i) + ); + MUXCY_L com_tlm_u_tlm_tx_vc0_trn_len_counter_cry_3_ ( + .CI(com_tlm_u_tlm_tx_vc0_trn_len_counter_cry[2]), + .DI(com_tlm_u_tlm_tx_vc0_trn_VCC_2500), + .LO(com_tlm_u_tlm_tx_vc0_trn_len_counter_cry[3]), + .S(com_tlm_u_tlm_tx_vc0_trn_len_counter_qxu[3]) + ); + XORCY com_tlm_u_tlm_tx_vc0_trn_len_counter_s_3_ ( + .CI(com_tlm_u_tlm_tx_vc0_trn_len_counter_cry[2]), + .LI(com_tlm_u_tlm_tx_vc0_trn_len_counter_qxu[3]), + .O(com_tlm_u_tlm_tx_vc0_trn_len_counter_s[3]) + ); + FDRE com_tlm_u_tlm_tx_vc0_trn_len_counter_3_ ( + .CE(com_tlm_u_tlm_tx_vc0_trn_N_48897_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_trn_len_counter_s[3]), + .Q(com_tlm_u_tlm_tx_vc0_trn_len_counter[3]), + .R(plm_link_up_i) + ); + MUXCY_L com_tlm_u_tlm_tx_vc0_trn_len_counter_cry_4_ ( + .CI(com_tlm_u_tlm_tx_vc0_trn_len_counter_cry[3]), + .DI(com_tlm_u_tlm_tx_vc0_trn_VCC_2500), + .LO(com_tlm_u_tlm_tx_vc0_trn_len_counter_cry[4]), + .S(com_tlm_u_tlm_tx_vc0_trn_len_counter_qxu[4]) + ); + XORCY com_tlm_u_tlm_tx_vc0_trn_len_counter_s_4_ ( + .CI(com_tlm_u_tlm_tx_vc0_trn_len_counter_cry[3]), + .LI(com_tlm_u_tlm_tx_vc0_trn_len_counter_qxu[4]), + .O(com_tlm_u_tlm_tx_vc0_trn_len_counter_s[4]) + ); + FDRE com_tlm_u_tlm_tx_vc0_trn_len_counter_4_ ( + .CE(com_tlm_u_tlm_tx_vc0_trn_N_48897_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_trn_len_counter_s[4]), + .Q(com_tlm_u_tlm_tx_vc0_trn_len_counter[4]), + .R(plm_link_up_i) + ); + MUXCY_L com_tlm_u_tlm_tx_vc0_trn_len_counter_cry_5_ ( + .CI(com_tlm_u_tlm_tx_vc0_trn_len_counter_cry[4]), + .DI(com_tlm_u_tlm_tx_vc0_trn_VCC_2500), + .LO(com_tlm_u_tlm_tx_vc0_trn_len_counter_cry[5]), + .S(com_tlm_u_tlm_tx_vc0_trn_len_counter_qxu[5]) + ); + XORCY com_tlm_u_tlm_tx_vc0_trn_len_counter_s_5_ ( + .CI(com_tlm_u_tlm_tx_vc0_trn_len_counter_cry[4]), + .LI(com_tlm_u_tlm_tx_vc0_trn_len_counter_qxu[5]), + .O(com_tlm_u_tlm_tx_vc0_trn_len_counter_s[5]) + ); + FDRE com_tlm_u_tlm_tx_vc0_trn_len_counter_5_ ( + .CE(com_tlm_u_tlm_tx_vc0_trn_N_48897_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_trn_len_counter_s[5]), + .Q(com_tlm_u_tlm_tx_vc0_trn_len_counter[5]), + .R(plm_link_up_i) + ); + XORCY com_tlm_u_tlm_tx_vc0_trn_len_counter_s_6_ ( + .CI(com_tlm_u_tlm_tx_vc0_trn_len_counter_cry[5]), + .LI(com_tlm_u_tlm_tx_vc0_trn_len_counter_qxu[6]), + .O(com_tlm_u_tlm_tx_vc0_trn_len_counter_s[6]) + ); + FDRE com_tlm_u_tlm_tx_vc0_trn_len_counter_6_ ( + .CE(com_tlm_u_tlm_tx_vc0_trn_N_48897_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_trn_len_counter_s[6]), + .Q(com_tlm_u_tlm_tx_vc0_trn_len_counter[6]), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_tx_vc0_trn_usr_vld ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_trn_N_48897_i), + .Q(com_tlm_u_tlm_tx_vc0_trn_usr_vld_2450), + .R(plm_link_up_i) + ); + defparam com_tlm_u_tlm_tx_vc0_trn_load_val_64_load_value10.INIT = 4'h8; + LUT2 com_tlm_u_tlm_tx_vc0_trn_load_val_64_load_value10 ( + .I0(trn_td_5057[47]), + .I1(trn_td_5057[61]), + .O(com_tlm_u_tlm_tx_vc0_trn_load_value10) + ); + defparam com_tlm_u_tlm_tx_vc0_trn_pkts_in_trn_1_sqmuxa_5604_i_0_0_0_o3.INIT = 4'h2; + LUT2 com_tlm_u_tlm_tx_vc0_trn_pkts_in_trn_1_sqmuxa_5604_i_0_0_0_o3 ( + .I0(com_tlm_u_tlm_tx_vc0_trn_usr_frame_in_2461), + .I1(trn_tsrc_dsc_n), + .O(com_tlm_u_tlm_tx_vc0_trn_pkts_in_trn_1_sqmuxa_5604_i_0_0_0_o3_2457) + ); + defparam com_tlm_u_tlm_tx_vc0_trn_un1_trn_tsrc_dsc_i_i_0_0_0_o2.INIT = 4'h4; + LUT2 com_tlm_u_tlm_tx_vc0_trn_un1_trn_tsrc_dsc_i_i_0_0_0_o2 ( + .I0(com_tlm_u_tlm_tx_vc0_trn_trn_tdst_dsc), + .I1(trn_tsrc_dsc_n), + .O(com_tlm_u_tlm_tx_vc0_trn_N_48986_i) + ); + defparam com_tlm_u_tlm_tx_vc0_trn_un1_usr_abort_8_0_0_0_0_a3_1.INIT = 4'h2; + LUT2 com_tlm_u_tlm_tx_vc0_trn_un1_usr_abort_8_0_0_0_0_a3_1 ( + .I0(NlwRenamedSig_OI_trn_tbuf_av[0]), + .I1(NlwRenamedSig_OI_trn_tbuf_av[1]), + .O(com_tlm_u_tlm_tx_vc0_trn_N_50761_1) + ); + defparam com_tlm_u_tlm_tx_vc0_trn_usr_calc_eof_0_sqmuxa_i_0_0_a2.INIT = 4'h1; + LUT2_L com_tlm_u_tlm_tx_vc0_trn_usr_calc_eof_0_sqmuxa_i_0_0_a2 ( + .I0(com_tlm_u_tlm_tx_vc0_trn_usr_frame_in_2461), + .I1(trn_tsof_n), + .LO(com_tlm_u_tlm_tx_vc0_trn_N_39946) + ); + defparam com_tlm_u_tlm_tx_vc0_trn_un1_usr_abort_2_i_0_a2_0_o2.INIT = 4'h1; + LUT2 com_tlm_u_tlm_tx_vc0_trn_un1_usr_abort_2_i_0_a2_0_o2 ( + .I0(com_tlm_u_tlm_tx_vc0_trn_released_buf_x_2469), + .I1(com_tlm_u_tlm_tx_vc0_trn_usr_abort_2496), + .O(com_tlm_u_tlm_tx_vc0_trn_N_13806_i) + ); + defparam com_tlm_u_tlm_tx_vc0_trn_cmm_tdst_rdy_o_3_0_0_0_0_o3.INIT = 4'h4; + LUT2 com_tlm_u_tlm_tx_vc0_trn_cmm_tdst_rdy_o_3_0_0_0_0_o3 ( + .I0(com_req_pkt_tx), + .I1(com_state_0_), + .O(com_N_48843_i) + ); + defparam com_tlm_u_tlm_tx_vc0_trn_un1_usr_vld_0_a4_0_a2_0_a2_0_a2.INIT = 4'h8; + LUT2 com_tlm_u_tlm_tx_vc0_trn_un1_usr_vld_0_a4_0_a2_0_a2_0_a2 ( + .I0(com_tlm_u_tlm_tx_vc0_trn_usr_sof_2424), + .I1(com_tlm_u_tlm_tx_vc0_trn_usr_vld_2450), + .O(com_tlm_u_tlm_tx_vc0_trn_un1_usr_vld_0_a4_0_a2_0_a2_0_a2_2422) + ); + defparam com_tlm_u_tlm_tx_vc0_trn_usr_sof_filt_0_a4_0_a2_0_a2_0_a2.INIT = 4'h4; + LUT2 com_tlm_u_tlm_tx_vc0_trn_usr_sof_filt_0_a4_0_a2_0_a2_0_a2 ( + .I0(com_tlm_u_tlm_tx_vc0_trn_usr_frame_2451), + .I1(com_tlm_u_tlm_tx_vc0_trn_usr_sof_2424), + .O(com_tlm_u_tlm_tx_vc0_trn_usr_sof_filt) + ); + defparam com_tlm_u_tlm_tx_vc0_trn_trn_tdst_rdy_o_3_0_0_0_o2_0_0_o2.INIT = 4'h1; + LUT2 com_tlm_u_tlm_tx_vc0_trn_trn_tdst_rdy_o_3_0_0_0_o2_0_0_o2 ( + .I0(com_gnt_pkt_tx), + .I1(com_state_4_), + .O(com_N_48836_i) + ); + defparam com_tlm_u_tlm_tx_vc0_trn_usr_vldc.INIT = 4'h2; + LUT2 com_tlm_u_tlm_tx_vc0_trn_usr_vldc ( + .I0(com_tlm_u_tlm_tx_vc0_trn_trn_tdst_rdy), + .I1(trn_tsrc_rdy_n), + .O(com_tlm_u_tlm_tx_vc0_trn_N_48897_i) + ); + defparam com_tlm_u_tlm_tx_vc0_trn_usr_calc_eof_0_sqmuxa_i_0_0_0.INIT = 4'h2; + LUT2 com_tlm_u_tlm_tx_vc0_trn_usr_calc_eof_0_sqmuxa_i_0_0_0 ( + .I0(com_tlm_u_tlm_tx_vc0_trn_len_counter[0]), + .I1(com_tlm_u_tlm_tx_vc0_trn_load_counter_q_2423), + .O(com_tlm_u_tlm_tx_vc0_trn_usr_calc_eof_0_sqmuxa_i_0_0_0_2436) + ); + defparam com_tlm_u_tlm_tx_vc0_trn_trn_tdst_rdy_o_3_0_0_0_a2_0_0_0.INIT = 4'h1; + LUT2 com_tlm_u_tlm_tx_vc0_trn_trn_tdst_rdy_o_3_0_0_0_a2_0_0_0 ( + .I0(com_tlm_u_tlm_tx_vc0_trn_trn_tdst_dsc), + .I1(com_tlm_u_tlm_tx_vc0_trn_cfg_frame_in_2459), + .O(com_tlm_u_tlm_tx_vc0_trn_trn_tdst_rdy_o_3_0_0_0_a2_0_0) + ); + defparam com_tlm_u_tlm_tx_vc0_trn_un1_trn_tsrc_dsc_i_i_0_0_0_a2.INIT = 4'h2; + LUT2 com_tlm_u_tlm_tx_vc0_trn_un1_trn_tsrc_dsc_i_i_0_0_0_a2 ( + .I0(com_tlm_u_tlm_tx_vc0_trn_N_48897_i), + .I1(trn_teof_n), + .O(com_tlm_u_tlm_tx_vc0_trn_N_49515) + ); + defparam com_tlm_u_tlm_tx_vc0_trn_trn_tdst_rdy_o_3_0_0_0_o2_0_0.INIT = 4'h2; + LUT2 com_tlm_u_tlm_tx_vc0_trn_trn_tdst_rdy_o_3_0_0_0_o2_0_0 ( + .I0(com_N_48836_i), + .I1(com_N_48843_i), + .O(com_tlm_u_tlm_tx_vc0_trn_trn_tdst_rdy_o_3_0_0_0_o2_0_0_2428) + ); + defparam com_tlm_u_tlm_tx_vc0_trn_un1_trn_tsrc_dsc_i_i_0_0_0_o3.INIT = 4'h2; + LUT2 com_tlm_u_tlm_tx_vc0_trn_un1_trn_tsrc_dsc_i_i_0_0_0_o3 ( + .I0(com_tlm_u_tlm_tx_vc0_trn_N_48897_i), + .I1(trn_tsof_n), + .O(com_tlm_u_tlm_tx_vc0_trn_N_48904_i) + ); + defparam com_tlm_u_tlm_tx_vc0_trn_un1_usr_dsc_1_i_0_0_a2.INIT = 8'h80; + LUT3 com_tlm_u_tlm_tx_vc0_trn_un1_usr_dsc_1_i_0_0_a2 ( + .I0(com_tlm_u_tlm_tx_vc0_trn_usr_eof_2443), + .I1(com_tlm_u_tlm_tx_vc0_trn_usr_frame_2451), + .I2(com_tlm_u_tlm_tx_vc0_trn_usr_vld_2450), + .O(com_tlm_u_tlm_tx_vc0_trn_N_49601) + ); + defparam com_tlm_u_tlm_tx_vc0_trn_usr_calc_eof_0_sqmuxa_i_0_0_o2.INIT = 4'h8; + LUT2 com_tlm_u_tlm_tx_vc0_trn_usr_calc_eof_0_sqmuxa_i_0_0_o2 ( + .I0(com_tlm_u_tlm_tx_vc0_trn_N_48897_i), + .I1(plm_link_up_1), + .O(com_tlm_u_tlm_tx_vc0_trn_N_39869_i) + ); + defparam com_tlm_u_tlm_tx_vc0_trn_vld_o_5_i_i_a2_i_a2.INIT = 8'hE0; + LUT3 com_tlm_u_tlm_tx_vc0_trn_vld_o_5_i_i_a2_i_a2 ( + .I0(com_tlm_u_tlm_tx_vc0_trn_usr_frame_2451), + .I1(com_tlm_u_tlm_tx_vc0_trn_usr_sof_2424), + .I2(com_tlm_u_tlm_tx_vc0_trn_usr_vld_2450), + .O(com_tlm_u_tlm_tx_vc0_trn_vld_o_5_i_i_a2_i_a2_2456) + ); + defparam com_tlm_u_tlm_tx_vc0_trn_pkts_in_trn28_i_0_0_0_0_o3.INIT = 8'h01; + LUT3 com_tlm_u_tlm_tx_vc0_trn_pkts_in_trn28_i_0_0_0_0_o3 ( + .I0(com_tlm_u_tlm_tx_vc0_trn_trn_tdst_dsc), + .I1(com_tlm_u_tlm_tx_vc0_trn_dsc_in_q_2425), + .I2(com_tlm_u_tlm_tx_vc0_trn_usr_eof_filt_q_4_), + .O(com_tlm_u_tlm_tx_vc0_trn_N_48939_i) + ); + defparam com_tlm_u_tlm_tx_vc0_trn_un1_usr_abort_8_0_0_0_0_a2_0_0.INIT = 8'h01; + LUT3 com_tlm_u_tlm_tx_vc0_trn_un1_usr_abort_8_0_0_0_0_a2_0_0 ( + .I0(NlwRenamedSig_OI_trn_tbuf_av[2]), + .I1(NlwRenamedSig_OI_trn_tbuf_av[3]), + .I2(NlwRenamedSig_OI_trn_tbuf_av[4]), + .O(com_tlm_u_tlm_tx_vc0_trn_un1_usr_abort_8_0_0_0_0_a2_0) + ); + defparam com_tlm_u_tlm_tx_vc0_trn_usr_calc_eof_0_sqmuxa_i_0_0_5.INIT = 16'h0001; + LUT4 com_tlm_u_tlm_tx_vc0_trn_usr_calc_eof_0_sqmuxa_i_0_0_5 ( + .I0(com_tlm_u_tlm_tx_vc0_trn_len_counter[1]), + .I1(com_tlm_u_tlm_tx_vc0_trn_len_counter[2]), + .I2(com_tlm_u_tlm_tx_vc0_trn_len_counter[4]), + .I3(com_tlm_u_tlm_tx_vc0_trn_len_counter[6]), + .O(com_tlm_u_tlm_tx_vc0_trn_usr_calc_eof_0_sqmuxa_i_0_0_5_2435) + ); + defparam com_tlm_u_tlm_tx_vc0_trn_buffer_rdy_3_i_0_0_0_0.INIT = 8'h13; + LUT3 com_tlm_u_tlm_tx_vc0_trn_buffer_rdy_3_i_0_0_0_0 ( + .I0(com_tlm_u_tlm_tx_vc0_trn_buf_av_one_2463), + .I1(com_tlm_u_tlm_tx_vc0_trn_buf_av_zero_2426), + .I2(com_tlm_u_tlm_tx_vc0_trn_start_frame_q_2470), + .O(com_tlm_u_tlm_tx_vc0_trn_buffer_rdy_3_i_0_0_0_0_2462) + ); + defparam com_tlm_u_tlm_tx_vc0_trn_start_frame_i_0_0_0_a2.INIT = 4'h2; + LUT2 com_tlm_u_tlm_tx_vc0_trn_start_frame_i_0_0_0_a2 ( + .I0(com_tlm_u_tlm_tx_vc0_trn_N_48904_i), + .I1(com_tlm_u_tlm_tx_vc0_trn_usr_frame_in_2461), + .O(com_tlm_u_tlm_tx_vc0_trn_usr_start) + ); + defparam com_tlm_u_tlm_tx_vc0_trn_start_frame_i_0_0_0_a2_0.INIT = 8'h80; + LUT3 com_tlm_u_tlm_tx_vc0_trn_start_frame_i_0_0_0_a2_0 ( + .I0(com_N_48836_i), + .I1(com_cmmt_trem_n_0_sqmuxa), + .I2(com_cmmt_tdst_rdy), + .O(com_tlm_u_tlm_tx_vc0_trn_cfg_start) + ); + defparam com_tlm_u_tlm_tx_vc0_trn_vld_o_5_i_i_a2_i_a3.INIT = 8'h20; + LUT3 com_tlm_u_tlm_tx_vc0_trn_vld_o_5_i_i_a2_i_a3 ( + .I0(com_N_48836_i), + .I1(com_N_48843_i), + .I2(com_cmmt_tdst_rdy), + .O(com_tlm_u_tlm_tx_vc0_trn_vld_o_5_i_i_a2_i_a3_2455) + ); + defparam com_tlm_u_tlm_tx_vc0_trn_d_o_4_0_0_0_a3_12_.INIT = 8'h20; + LUT3 com_tlm_u_tlm_tx_vc0_trn_d_o_4_0_0_0_a3_12_ ( + .I0(com_N_48836_i), + .I1(com_state_0_), + .I2(com_cmmt_tdst_rdy), + .O(com_tlm_u_tlm_tx_vc0_trn_d_o_4_0_0_0_a3[12]) + ); + defparam com_tlm_u_tlm_tx_vc0_trn_rem_o_5_0_0_0_o3_1.INIT = 16'h0F01; + LUT4_L com_tlm_u_tlm_tx_vc0_trn_rem_o_5_0_0_0_o3_1 ( + .I0(com_tlp_data_0_), + .I1(com_tlp_data_29_), + .I2(com_cmmt_trem_n_0_sqmuxa), + .I3(com_state_0_), + .LO(com_tlm_u_tlm_tx_vc0_trn_rem_o_5_0_0_0_o3_1_2431) + ); + defparam com_tlm_u_tlm_tx_vc0_trn_trn_tdst_rdy_o_3_0_0_0_a2.INIT = 16'h0040; + LUT4_L com_tlm_u_tlm_tx_vc0_trn_trn_tdst_rdy_o_3_0_0_0_a2 ( + .I0(com_tlm_u_tlm_tx_vc0_trn_trn_tdst_rdy_o_3_0_0_0_o2_0_0_2428), + .I1(com_cmmt_ppm_suspend_req_n), + .I2(com_tlm_u_tlm_tx_vc0_trn_buffer_rdy_2427), + .I3(com_tlm_u_tlm_tx_vc0_trn_cfg_frame_in_2459), + .LO(com_tlm_u_tlm_tx_vc0_trn_N_39932) + ); + defparam com_tlm_u_tlm_tx_vc0_trn_cmm_tdst_rdy_o_3_0_0_0_0_a2_0.INIT = 16'h0020; + LUT4_L com_tlm_u_tlm_tx_vc0_trn_cmm_tdst_rdy_o_3_0_0_0_0_a2_0 ( + .I0(com_tlm_u_tlm_tx_vc0_trn_trn_tdst_rdy_o_3_0_0_0_o2_0_0_2428), + .I1(com_tlm_u_tlm_tx_vc0_trn_trn_tdst_rdy), + .I2(com_tlm_u_tlm_tx_vc0_trn_buffer_rdy_2427), + .I3(com_tlm_u_tlm_tx_vc0_trn_usr_frame_in_2461), + .LO(com_tlm_u_tlm_tx_vc0_trn_N_49237) + ); + defparam com_tlm_u_tlm_tx_vc0_trn_usr_calc_eof_0_sqmuxa_i_0_0_7.INIT = 16'h0001; + LUT4 com_tlm_u_tlm_tx_vc0_trn_usr_calc_eof_0_sqmuxa_i_0_0_7 ( + .I0(com_tlm_u_tlm_tx_vc0_trn_N_39946), + .I1(com_tlm_u_tlm_tx_vc0_trn_len_counter[3]), + .I2(com_tlm_u_tlm_tx_vc0_trn_len_counter[5]), + .I3(com_tlm_u_tlm_tx_vc0_trn_load_counter_2503), + .O(com_tlm_u_tlm_tx_vc0_trn_usr_calc_eof_0_sqmuxa_i_0_0_7_2434) + ); + defparam com_tlm_u_tlm_tx_vc0_trn_eof_o_5_i_0_0_0.INIT = 16'h0BFF; + LUT4 com_tlm_u_tlm_tx_vc0_trn_eof_o_5_i_0_0_0 ( + .I0(com_tlm_u_tlm_tx_vc0_trn_usr_eof_2443), + .I1(com_tlm_u_tlm_tx_vc0_trn_usr_frame_2451), + .I2(com_tlm_u_tlm_tx_vc0_trn_usr_sof_filt), + .I3(com_tlm_u_tlm_tx_vc0_trn_usr_vld_2450), + .O(com_tlm_u_tlm_tx_vc0_trn_eof_o_5_i_0_0_0_2447) + ); + defparam com_tlm_u_tlm_tx_vc0_trn_N_68766_i.INIT = 4'hE; + LUT2 com_tlm_u_tlm_tx_vc0_trn_N_68766_i ( + .I0(com_tlm_u_tlm_tx_vc0_trn_N_49601), + .I1(com_tlm_u_tlm_tx_vc0_trn_usr_dsc_2430), + .O(com_tlm_u_tlm_tx_vc0_trn_N_68766_i_2429) + ); + defparam com_tlm_u_tlm_tx_vc0_trn_d_o_4_i_0_0_a2_1_57_.INIT = 4'h4; + LUT2 com_tlm_u_tlm_tx_vc0_trn_d_o_4_i_0_0_a2_1_57_ ( + .I0(com_tlp_data_27_), + .I1(com_tlm_u_tlm_tx_vc0_trn_cfg_start), + .O(com_tlm_u_tlm_tx_vc0_trn_d_o_4_i_0_0_a2_1[57]) + ); + defparam com_tlm_u_tlm_tx_vc0_trn_un1_usr_abort_8_0_0_0_0_o3.INIT = 16'hF35F; + LUT4 com_tlm_u_tlm_tx_vc0_trn_un1_usr_abort_8_0_0_0_0_o3 ( + .I0(com_tlm_u_tlm_tx_vc0_trn_N_49500), + .I1(com_tlm_u_tlm_tx_vc0_trn_un1_buf_av_one_1_i_0_0_0_a2[0]), + .I2(NlwRenamedSig_OI_trn_tbuf_av[0]), + .I3(NlwRenamedSig_OI_trn_tbuf_av[1]), + .O(com_tlm_u_tlm_tx_vc0_trn_un1_usr_abort_8_0_0_0_0_o3_2439) + ); + defparam com_tlm_u_tlm_tx_vc0_trn_d_o_4_i_0_0_a2_59_.INIT = 4'h1; + LUT2 com_tlm_u_tlm_tx_vc0_trn_d_o_4_i_0_0_a2_59_ ( + .I0(com_tlm_u_tlm_tx_vc0_trn_vld_o_5_i_i_a2_i_a3_2455), + .I1(com_tlm_u_tlm_tx_vc0_trn_usr_d[59]), + .O(com_tlm_u_tlm_tx_vc0_trn_N_49591) + ); + defparam com_tlm_u_tlm_tx_vc0_trn_d_o_4_i_0_0_a2_57_.INIT = 4'h1; + LUT2 com_tlm_u_tlm_tx_vc0_trn_d_o_4_i_0_0_a2_57_ ( + .I0(com_tlm_u_tlm_tx_vc0_trn_vld_o_5_i_i_a2_i_a3_2455), + .I1(com_tlm_u_tlm_tx_vc0_trn_usr_d[57]), + .O(com_tlm_u_tlm_tx_vc0_trn_N_49588) + ); + defparam com_tlm_u_tlm_tx_vc0_trn_rem_o_5_0_0_0_a2.INIT = 16'h0002; + LUT4_L com_tlm_u_tlm_tx_vc0_trn_rem_o_5_0_0_0_a2 ( + .I0(com_N_48836_i), + .I1(com_tlm_u_tlm_tx_vc0_trn_vld_o_5_i_i_a2_i_a2_2456), + .I2(com_tlm_u_tlm_tx_vc0_trn_rem_o_5_0_0_0_o3_1_2431), + .I3(com_state_2_), + .LO(com_tlm_u_tlm_tx_vc0_trn_N_49231) + ); + defparam com_tlm_u_tlm_tx_vc0_trn_N_67955_i.INIT = 8'hFB; + LUT3 com_tlm_u_tlm_tx_vc0_trn_N_67955_i ( + .I0(com_tlm_u_tlm_tx_vc0_trn_N_48904_i), + .I1(com_tlm_u_tlm_tx_vc0_trn_N_48986_i), + .I2(com_tlm_u_tlm_tx_vc0_trn_N_49515), + .O(com_tlm_u_tlm_tx_vc0_trn_N_67955_i_2432) + ); + defparam com_tlm_u_tlm_tx_vc0_trn_cfg_frame_in_en_i_0_0_0.INIT = 8'hC4; + LUT3 com_tlm_u_tlm_tx_vc0_trn_cfg_frame_in_en_i_0_0_0 ( + .I0(com_grant_reg_iv_0_0_0_a2), + .I1(com_tlm_u_tlm_tx_vc0_trn_vld_o_5_i_i_a2_i_a3_2455), + .I2(com_state_0_), + .O(com_tlm_u_tlm_tx_vc0_trn_N_13633_i) + ); + defparam com_tlm_u_tlm_tx_vc0_trn_un1_trn_tbuf_av_o_1_axb_0.INIT = 16'h13EC; + LUT4 com_tlm_u_tlm_tx_vc0_trn_un1_trn_tbuf_av_o_1_axb_0 ( + .I0(com_tlm_u_tlm_tx_vc0_trn_N_49500), + .I1(com_tlm_u_tlm_tx_vc0_trn_un1_buf_av_one_1_i_0_0_0_a2[0]), + .I2(plm_link_up_1), + .I3(NlwRenamedSig_OI_trn_tbuf_av[0]), + .O(com_tlm_u_tlm_tx_vc0_trn_un1_trn_tbuf_av_o_1_axb_0_2433) + ); + defparam com_tlm_u_tlm_tx_vc0_trn_usr_calc_eof_0_sqmuxa_i_0_0.INIT = 16'h8000; + LUT4 com_tlm_u_tlm_tx_vc0_trn_usr_calc_eof_0_sqmuxa_i_0_0 ( + .I0(com_tlm_u_tlm_tx_vc0_trn_N_39869_i), + .I1(com_tlm_u_tlm_tx_vc0_trn_usr_calc_eof_0_sqmuxa_i_0_0_0_2436), + .I2(com_tlm_u_tlm_tx_vc0_trn_usr_calc_eof_0_sqmuxa_i_0_0_5_2435), + .I3(com_tlm_u_tlm_tx_vc0_trn_usr_calc_eof_0_sqmuxa_i_0_0_7_2434), + .O(com_tlm_u_tlm_tx_vc0_trn_N_13650_i) + ); + defparam com_tlm_u_tlm_tx_vc0_trn_pkts_in_trn_1_sqmuxa_5604_i_0_0_0.INIT = 16'h0D00; + LUT4 com_tlm_u_tlm_tx_vc0_trn_pkts_in_trn_1_sqmuxa_5604_i_0_0_0 ( + .I0(com_tlm_u_tlm_tx_vc0_trn_N_48939_i), + .I1(com_tlm_u_tlm_tx_vc0_trn_pkts_in_trn_1_sqmuxa_5604_i_0_0_0_o3_2457), + .I2(com_tlm_u_tlm_tx_vc0_trn_usr_start), + .I3(plm_link_up_1), + .O(com_tlm_u_tlm_tx_vc0_trn_N_13683_i) + ); + defparam com_tlm_u_tlm_tx_vc0_trn_pkts_in_trn28_i_0_0_0_0_32184.INIT = 16'h39F9; + LUT4 com_tlm_u_tlm_tx_vc0_trn_pkts_in_trn28_i_0_0_0_0_32184 ( + .I0(com_tlm_u_tlm_tx_vc0_trn_N_48904_i), + .I1(com_tlm_u_tlm_tx_vc0_trn_N_48939_i), + .I2(com_tlm_u_tlm_tx_vc0_trn_usr_frame_in_2461), + .I3(trn_tsrc_dsc_n), + .O(com_tlm_u_tlm_tx_vc0_trn_pkts_in_trn28_i_0_0_0_0_32184_2505) + ); + defparam com_tlm_u_tlm_tx_vc0_trn_d_o_4_i_0_0_0_61_.INIT = 16'hC4F5; + LUT4_L com_tlm_u_tlm_tx_vc0_trn_d_o_4_i_0_0_0_61_ ( + .I0(com_tlm_u_tlm_tx_vc0_trn_d_o_4_0_0_0_a3[12]), + .I1(com_tlp_data_29_), + .I2(com_TLP_data_reg_29_), + .I3(com_tlm_u_tlm_tx_vc0_trn_cfg_start), + .LO(com_tlm_u_tlm_tx_vc0_trn_d_o_4_i_0_0_0[61]) + ); + defparam com_tlm_u_tlm_tx_vc0_trn_d_o_4_i_i_i_0_32_.INIT = 16'hF3A2; + LUT4_L com_tlm_u_tlm_tx_vc0_trn_d_o_4_i_i_i_0_32_ ( + .I0(com_tlm_u_tlm_tx_vc0_trn_vld_o_5_i_i_a2_i_a3_2455), + .I1(com_tlm_u_tlm_tx_vc0_trn_d_o_4_0_0_0_a3[12]), + .I2(com_TLP_data_reg_0_), + .I3(com_tlm_u_tlm_tx_vc0_trn_usr_d[32]), + .LO(com_tlm_u_tlm_tx_vc0_trn_d_o_4_i_i_i_0[32]) + ); + defparam com_tlm_u_tlm_tx_vc0_trn_d_o_4_i_0_0_0_62_.INIT = 16'hF3A2; + LUT4_L com_tlm_u_tlm_tx_vc0_trn_d_o_4_i_0_0_0_62_ ( + .I0(com_tlm_u_tlm_tx_vc0_trn_vld_o_5_i_i_a2_i_a3_2455), + .I1(com_tlm_u_tlm_tx_vc0_trn_d_o_4_0_0_0_a3[12]), + .I2(com_TLP_data_reg_30_), + .I3(com_tlm_u_tlm_tx_vc0_trn_usr_d[62]), + .LO(com_tlm_u_tlm_tx_vc0_trn_d_o_4_i_0_0_0[62]) + ); + defparam com_tlm_u_tlm_tx_vc0_trn_N_68960_i.INIT = 16'hEAAA; + LUT4 com_tlm_u_tlm_tx_vc0_trn_N_68960_i ( + .I0(com_tlm_u_tlm_tx_vc0_trn_N_49500), + .I1(com_tlm_u_tlm_tx_vc0_trn_un1_buf_av_one_1_i_0_0_0_a2[0]), + .I2(com_tlm_u_tlm_tx_vc0_trn_N_50761_1), + .I3(com_tlm_u_tlm_tx_vc0_trn_un1_usr_abort_8_0_0_0_0_a2_0), + .O(com_tlm_u_tlm_tx_vc0_trn_N_68960_i_2437) + ); + defparam com_tlm_u_tlm_tx_vc0_trn_pkts_in_trn28_i_0_0_0_0.INIT = 4'h8; + LUT2 com_tlm_u_tlm_tx_vc0_trn_pkts_in_trn28_i_0_0_0_0 ( + .I0(com_tlm_u_tlm_tx_vc0_trn_pkts_in_trn28_i_0_0_0_0_32184_2505), + .I1(plm_link_up_1), + .O(com_tlm_u_tlm_tx_vc0_trn_pkts_in_trn28_i_i) + ); + defparam com_tlm_u_tlm_tx_vc0_trn_N_68959_i.INIT = 16'h30BA; + LUT4 com_tlm_u_tlm_tx_vc0_trn_N_68959_i ( + .I0(com_tlm_u_tlm_tx_vc0_trn_N_49500), + .I1(com_tlm_u_tlm_tx_vc0_trn_un1_usr_abort_8_0_0_0_0_o3_2439), + .I2(com_tlm_u_tlm_tx_vc0_trn_un1_usr_abort_8_0_0_0_0_a2_0), + .I3(plm_link_up_1), + .O(com_tlm_u_tlm_tx_vc0_trn_N_68959_i_2438) + ); + defparam com_tlm_u_tlm_tx_vc0_trn_usr_no_eof_err14_0_a4_0_a2_0_a2.INIT = 16'h8000; + LUT4_L com_tlm_u_tlm_tx_vc0_trn_usr_no_eof_err14_0_a4_0_a2_0_a2 ( + .I0(com_tlm_u_tlm_tx_vc0_trn_N_39869_i), + .I1(com_tlm_u_tlm_tx_vc0_trn_usr_calc_eof_2440), + .I2(com_tlm_u_tlm_tx_vc0_trn_usr_frame_in_2461), + .I3(trn_teof_n), + .LO(com_tlm_u_tlm_tx_vc0_trn_usr_no_eof_err14) + ); + defparam com_tlm_u_tlm_tx_vc0_trn_d_o_4_i_0_0_1_.INIT = 8'hD8; + LUT3_L com_tlm_u_tlm_tx_vc0_trn_d_o_4_i_0_0_1_ ( + .I0(com_tlm_u_tlm_tx_vc0_trn_vld_o_5_i_i_a2_i_a3_2455), + .I1(com_N_51601), + .I2(com_tlm_u_tlm_tx_vc0_trn_usr_d[1]), + .LO(com_tlm_u_tlm_tx_vc0_trn_N_31925_i) + ); + defparam com_tlm_u_tlm_tx_vc0_trn_d_o_4_i_0_0_0_.INIT = 8'hD8; + LUT3_L com_tlm_u_tlm_tx_vc0_trn_d_o_4_i_0_0_0_ ( + .I0(com_tlm_u_tlm_tx_vc0_trn_vld_o_5_i_i_a2_i_a3_2455), + .I1(com_N_51600), + .I2(com_tlm_u_tlm_tx_vc0_trn_usr_d[0]), + .LO(com_tlm_u_tlm_tx_vc0_trn_N_31923_i) + ); + defparam com_tlm_u_tlm_tx_vc0_trn_N_68408_i.INIT = 16'hD5C0; + LUT4_L com_tlm_u_tlm_tx_vc0_trn_N_68408_i ( + .I0(com_tlm_u_tlm_tx_vc0_trn_vld_o_5_i_i_a2_i_a3_2455), + .I1(com_tlm_u_tlm_tx_vc0_trn_d_o_4_0_0_0_a3[12]), + .I2(com_TLP_data_reg_48_), + .I3(com_tlm_u_tlm_tx_vc0_trn_usr_d[16]), + .LO(com_tlm_u_tlm_tx_vc0_trn_N_68408_i_2471) + ); + defparam com_tlm_u_tlm_tx_vc0_trn_d_o_4_i_0_0_15_.INIT = 8'hD8; + LUT3_L com_tlm_u_tlm_tx_vc0_trn_d_o_4_i_0_0_15_ ( + .I0(com_tlm_u_tlm_tx_vc0_trn_vld_o_5_i_i_a2_i_a3_2455), + .I1(com_N_51613), + .I2(com_tlm_u_tlm_tx_vc0_trn_usr_d[15]), + .LO(com_tlm_u_tlm_tx_vc0_trn_N_31951_i) + ); + defparam com_tlm_u_tlm_tx_vc0_trn_N_68407_i.INIT = 16'hD5C0; + LUT4_L com_tlm_u_tlm_tx_vc0_trn_N_68407_i ( + .I0(com_tlm_u_tlm_tx_vc0_trn_vld_o_5_i_i_a2_i_a3_2455), + .I1(com_tlm_u_tlm_tx_vc0_trn_d_o_4_0_0_0_a3[12]), + .I2(com_TLP_data_reg_46_), + .I3(com_tlm_u_tlm_tx_vc0_trn_usr_d[14]), + .LO(com_tlm_u_tlm_tx_vc0_trn_N_68407_i_2472) + ); + defparam com_tlm_u_tlm_tx_vc0_trn_d_o_4_i_0_0_13_.INIT = 8'hD8; + LUT3_L com_tlm_u_tlm_tx_vc0_trn_d_o_4_i_0_0_13_ ( + .I0(com_tlm_u_tlm_tx_vc0_trn_vld_o_5_i_i_a2_i_a3_2455), + .I1(com_N_51612), + .I2(com_tlm_u_tlm_tx_vc0_trn_usr_d[13]), + .LO(com_tlm_u_tlm_tx_vc0_trn_N_31948_i) + ); + defparam com_tlm_u_tlm_tx_vc0_trn_N_68406_i.INIT = 16'hD5C0; + LUT4_L com_tlm_u_tlm_tx_vc0_trn_N_68406_i ( + .I0(com_tlm_u_tlm_tx_vc0_trn_vld_o_5_i_i_a2_i_a3_2455), + .I1(com_tlm_u_tlm_tx_vc0_trn_d_o_4_0_0_0_a3[12]), + .I2(com_TLP_data_reg_44_), + .I3(com_tlm_u_tlm_tx_vc0_trn_usr_d[12]), + .LO(com_tlm_u_tlm_tx_vc0_trn_N_68406_i_2473) + ); + defparam com_tlm_u_tlm_tx_vc0_trn_d_o_4_i_0_0_11_.INIT = 8'hD8; + LUT3_L com_tlm_u_tlm_tx_vc0_trn_d_o_4_i_0_0_11_ ( + .I0(com_tlm_u_tlm_tx_vc0_trn_vld_o_5_i_i_a2_i_a3_2455), + .I1(com_N_51611), + .I2(com_tlm_u_tlm_tx_vc0_trn_usr_d[11]), + .LO(com_tlm_u_tlm_tx_vc0_trn_N_31945_i) + ); + defparam com_tlm_u_tlm_tx_vc0_trn_d_o_4_i_0_0_10_.INIT = 8'hD8; + LUT3_L com_tlm_u_tlm_tx_vc0_trn_d_o_4_i_0_0_10_ ( + .I0(com_tlm_u_tlm_tx_vc0_trn_vld_o_5_i_i_a2_i_a3_2455), + .I1(com_N_51610), + .I2(com_tlm_u_tlm_tx_vc0_trn_usr_d[10]), + .LO(com_tlm_u_tlm_tx_vc0_trn_N_31943_i) + ); + defparam com_tlm_u_tlm_tx_vc0_trn_d_o_4_i_0_0_9_.INIT = 8'hD8; + LUT3_L com_tlm_u_tlm_tx_vc0_trn_d_o_4_i_0_0_9_ ( + .I0(com_tlm_u_tlm_tx_vc0_trn_vld_o_5_i_i_a2_i_a3_2455), + .I1(com_N_51609), + .I2(com_tlm_u_tlm_tx_vc0_trn_usr_d[9]), + .LO(com_tlm_u_tlm_tx_vc0_trn_N_31941_i) + ); + defparam com_tlm_u_tlm_tx_vc0_trn_d_o_4_i_0_0_8_.INIT = 8'hD8; + LUT3_L com_tlm_u_tlm_tx_vc0_trn_d_o_4_i_0_0_8_ ( + .I0(com_tlm_u_tlm_tx_vc0_trn_vld_o_5_i_i_a2_i_a3_2455), + .I1(com_N_51608), + .I2(com_tlm_u_tlm_tx_vc0_trn_usr_d[8]), + .LO(com_tlm_u_tlm_tx_vc0_trn_N_31939_i) + ); + defparam com_tlm_u_tlm_tx_vc0_trn_d_o_4_i_0_0_7_.INIT = 8'hD8; + LUT3_L com_tlm_u_tlm_tx_vc0_trn_d_o_4_i_0_0_7_ ( + .I0(com_tlm_u_tlm_tx_vc0_trn_vld_o_5_i_i_a2_i_a3_2455), + .I1(com_N_51607), + .I2(com_tlm_u_tlm_tx_vc0_trn_usr_d[7]), + .LO(com_tlm_u_tlm_tx_vc0_trn_N_31937_i) + ); + defparam com_tlm_u_tlm_tx_vc0_trn_d_o_4_i_0_0_6_.INIT = 8'hD8; + LUT3_L com_tlm_u_tlm_tx_vc0_trn_d_o_4_i_0_0_6_ ( + .I0(com_tlm_u_tlm_tx_vc0_trn_vld_o_5_i_i_a2_i_a3_2455), + .I1(com_N_51606), + .I2(com_tlm_u_tlm_tx_vc0_trn_usr_d[6]), + .LO(com_tlm_u_tlm_tx_vc0_trn_N_31935_i) + ); + defparam com_tlm_u_tlm_tx_vc0_trn_d_o_4_i_0_0_5_.INIT = 8'hD8; + LUT3_L com_tlm_u_tlm_tx_vc0_trn_d_o_4_i_0_0_5_ ( + .I0(com_tlm_u_tlm_tx_vc0_trn_vld_o_5_i_i_a2_i_a3_2455), + .I1(com_N_51605), + .I2(com_tlm_u_tlm_tx_vc0_trn_usr_d[5]), + .LO(com_tlm_u_tlm_tx_vc0_trn_N_31933_i) + ); + defparam com_tlm_u_tlm_tx_vc0_trn_d_o_4_i_0_0_4_.INIT = 8'hD8; + LUT3_L com_tlm_u_tlm_tx_vc0_trn_d_o_4_i_0_0_4_ ( + .I0(com_tlm_u_tlm_tx_vc0_trn_vld_o_5_i_i_a2_i_a3_2455), + .I1(com_N_51604), + .I2(com_tlm_u_tlm_tx_vc0_trn_usr_d[4]), + .LO(com_tlm_u_tlm_tx_vc0_trn_N_31931_i) + ); + defparam com_tlm_u_tlm_tx_vc0_trn_d_o_4_i_0_0_3_.INIT = 8'hD8; + LUT3_L com_tlm_u_tlm_tx_vc0_trn_d_o_4_i_0_0_3_ ( + .I0(com_tlm_u_tlm_tx_vc0_trn_vld_o_5_i_i_a2_i_a3_2455), + .I1(com_N_51603), + .I2(com_tlm_u_tlm_tx_vc0_trn_usr_d[3]), + .LO(com_tlm_u_tlm_tx_vc0_trn_N_31929_i) + ); + defparam com_tlm_u_tlm_tx_vc0_trn_d_o_4_i_0_0_2_.INIT = 8'hD8; + LUT3_L com_tlm_u_tlm_tx_vc0_trn_d_o_4_i_0_0_2_ ( + .I0(com_tlm_u_tlm_tx_vc0_trn_vld_o_5_i_i_a2_i_a3_2455), + .I1(com_N_51602), + .I2(com_tlm_u_tlm_tx_vc0_trn_usr_d[2]), + .LO(com_tlm_u_tlm_tx_vc0_trn_N_31927_i) + ); + defparam com_tlm_u_tlm_tx_vc0_trn_d_o_4_i_0_0_31_.INIT = 8'hD8; + LUT3_L com_tlm_u_tlm_tx_vc0_trn_d_o_4_i_0_0_31_ ( + .I0(com_tlm_u_tlm_tx_vc0_trn_vld_o_5_i_i_a2_i_a3_2455), + .I1(com_N_51626), + .I2(com_tlm_u_tlm_tx_vc0_trn_usr_d[31]), + .LO(com_tlm_u_tlm_tx_vc0_trn_N_31980_i) + ); + defparam com_tlm_u_tlm_tx_vc0_trn_d_o_4_i_0_0_30_.INIT = 8'hD8; + LUT3_L com_tlm_u_tlm_tx_vc0_trn_d_o_4_i_0_0_30_ ( + .I0(com_tlm_u_tlm_tx_vc0_trn_vld_o_5_i_i_a2_i_a3_2455), + .I1(com_N_51625), + .I2(com_tlm_u_tlm_tx_vc0_trn_usr_d[30]), + .LO(com_tlm_u_tlm_tx_vc0_trn_N_31978_i) + ); + defparam com_tlm_u_tlm_tx_vc0_trn_d_o_4_i_0_0_29_.INIT = 8'hD8; + LUT3_L com_tlm_u_tlm_tx_vc0_trn_d_o_4_i_0_0_29_ ( + .I0(com_tlm_u_tlm_tx_vc0_trn_vld_o_5_i_i_a2_i_a3_2455), + .I1(com_N_51624), + .I2(com_tlm_u_tlm_tx_vc0_trn_usr_d[29]), + .LO(com_tlm_u_tlm_tx_vc0_trn_N_31976_i) + ); + defparam com_tlm_u_tlm_tx_vc0_trn_d_o_4_i_0_0_28_.INIT = 8'hD8; + LUT3_L com_tlm_u_tlm_tx_vc0_trn_d_o_4_i_0_0_28_ ( + .I0(com_tlm_u_tlm_tx_vc0_trn_vld_o_5_i_i_a2_i_a3_2455), + .I1(com_N_51623), + .I2(com_tlm_u_tlm_tx_vc0_trn_usr_d[28]), + .LO(com_tlm_u_tlm_tx_vc0_trn_N_31974_i) + ); + defparam com_tlm_u_tlm_tx_vc0_trn_d_o_4_i_0_0_27_.INIT = 8'hD8; + LUT3_L com_tlm_u_tlm_tx_vc0_trn_d_o_4_i_0_0_27_ ( + .I0(com_tlm_u_tlm_tx_vc0_trn_vld_o_5_i_i_a2_i_a3_2455), + .I1(com_N_51622), + .I2(com_tlm_u_tlm_tx_vc0_trn_usr_d[27]), + .LO(com_tlm_u_tlm_tx_vc0_trn_N_31972_i) + ); + defparam com_tlm_u_tlm_tx_vc0_trn_d_o_4_i_0_0_26_.INIT = 8'hD8; + LUT3_L com_tlm_u_tlm_tx_vc0_trn_d_o_4_i_0_0_26_ ( + .I0(com_tlm_u_tlm_tx_vc0_trn_vld_o_5_i_i_a2_i_a3_2455), + .I1(com_N_51621), + .I2(com_tlm_u_tlm_tx_vc0_trn_usr_d[26]), + .LO(com_tlm_u_tlm_tx_vc0_trn_N_31970_i) + ); + defparam com_tlm_u_tlm_tx_vc0_trn_d_o_4_i_0_0_25_.INIT = 8'hD8; + LUT3_L com_tlm_u_tlm_tx_vc0_trn_d_o_4_i_0_0_25_ ( + .I0(com_tlm_u_tlm_tx_vc0_trn_vld_o_5_i_i_a2_i_a3_2455), + .I1(com_N_51620), + .I2(com_tlm_u_tlm_tx_vc0_trn_usr_d[25]), + .LO(com_tlm_u_tlm_tx_vc0_trn_N_31968_i) + ); + defparam com_tlm_u_tlm_tx_vc0_trn_d_o_4_i_0_0_24_.INIT = 8'hD8; + LUT3_L com_tlm_u_tlm_tx_vc0_trn_d_o_4_i_0_0_24_ ( + .I0(com_tlm_u_tlm_tx_vc0_trn_vld_o_5_i_i_a2_i_a3_2455), + .I1(com_N_51619), + .I2(com_tlm_u_tlm_tx_vc0_trn_usr_d[24]), + .LO(com_tlm_u_tlm_tx_vc0_trn_N_31966_i) + ); + defparam com_tlm_u_tlm_tx_vc0_trn_d_o_4_i_0_0_23_.INIT = 8'hD8; + LUT3_L com_tlm_u_tlm_tx_vc0_trn_d_o_4_i_0_0_23_ ( + .I0(com_tlm_u_tlm_tx_vc0_trn_vld_o_5_i_i_a2_i_a3_2455), + .I1(com_N_51618), + .I2(com_tlm_u_tlm_tx_vc0_trn_usr_d[23]), + .LO(com_tlm_u_tlm_tx_vc0_trn_N_31964_i) + ); + defparam com_tlm_u_tlm_tx_vc0_trn_d_o_4_i_0_0_22_.INIT = 8'hD8; + LUT3_L com_tlm_u_tlm_tx_vc0_trn_d_o_4_i_0_0_22_ ( + .I0(com_tlm_u_tlm_tx_vc0_trn_vld_o_5_i_i_a2_i_a3_2455), + .I1(com_N_51617), + .I2(com_tlm_u_tlm_tx_vc0_trn_usr_d[22]), + .LO(com_tlm_u_tlm_tx_vc0_trn_N_31962_i) + ); + defparam com_tlm_u_tlm_tx_vc0_trn_d_o_4_i_0_0_21_.INIT = 8'hD8; + LUT3_L com_tlm_u_tlm_tx_vc0_trn_d_o_4_i_0_0_21_ ( + .I0(com_tlm_u_tlm_tx_vc0_trn_vld_o_5_i_i_a2_i_a3_2455), + .I1(com_N_51616), + .I2(com_tlm_u_tlm_tx_vc0_trn_usr_d[21]), + .LO(com_tlm_u_tlm_tx_vc0_trn_N_31960_i) + ); + defparam com_tlm_u_tlm_tx_vc0_trn_d_o_4_i_0_0_20_.INIT = 8'hD8; + LUT3_L com_tlm_u_tlm_tx_vc0_trn_d_o_4_i_0_0_20_ ( + .I0(com_tlm_u_tlm_tx_vc0_trn_vld_o_5_i_i_a2_i_a3_2455), + .I1(com_N_51615), + .I2(com_tlm_u_tlm_tx_vc0_trn_usr_d[20]), + .LO(com_tlm_u_tlm_tx_vc0_trn_N_31958_i) + ); + defparam com_tlm_u_tlm_tx_vc0_trn_d_o_4_i_0_0_19_.INIT = 8'hD8; + LUT3_L com_tlm_u_tlm_tx_vc0_trn_d_o_4_i_0_0_19_ ( + .I0(com_tlm_u_tlm_tx_vc0_trn_vld_o_5_i_i_a2_i_a3_2455), + .I1(com_N_51614), + .I2(com_tlm_u_tlm_tx_vc0_trn_usr_d[19]), + .LO(com_tlm_u_tlm_tx_vc0_trn_N_31956_i) + ); + defparam com_tlm_u_tlm_tx_vc0_trn_N_68410_i.INIT = 16'hD5C0; + LUT4_L com_tlm_u_tlm_tx_vc0_trn_N_68410_i ( + .I0(com_tlm_u_tlm_tx_vc0_trn_vld_o_5_i_i_a2_i_a3_2455), + .I1(com_tlm_u_tlm_tx_vc0_trn_d_o_4_0_0_0_a3[12]), + .I2(com_TLP_data_reg_50_), + .I3(com_tlm_u_tlm_tx_vc0_trn_usr_d[18]), + .LO(com_tlm_u_tlm_tx_vc0_trn_N_68410_i_2474) + ); + defparam com_tlm_u_tlm_tx_vc0_trn_N_68409_i.INIT = 16'hD5C0; + LUT4_L com_tlm_u_tlm_tx_vc0_trn_N_68409_i ( + .I0(com_tlm_u_tlm_tx_vc0_trn_vld_o_5_i_i_a2_i_a3_2455), + .I1(com_tlm_u_tlm_tx_vc0_trn_d_o_4_0_0_0_a3[12]), + .I2(com_TLP_data_reg_49_), + .I3(com_tlm_u_tlm_tx_vc0_trn_usr_d[17]), + .LO(com_tlm_u_tlm_tx_vc0_trn_N_68409_i_2475) + ); + defparam com_tlm_u_tlm_tx_vc0_trn_N_68421_i.INIT = 16'hD5C0; + LUT4_L com_tlm_u_tlm_tx_vc0_trn_N_68421_i ( + .I0(com_tlm_u_tlm_tx_vc0_trn_vld_o_5_i_i_a2_i_a3_2455), + .I1(com_tlm_u_tlm_tx_vc0_trn_d_o_4_0_0_0_a3[12]), + .I2(com_TLP_data_reg_14_), + .I3(com_tlm_u_tlm_tx_vc0_trn_usr_d[46]), + .LO(com_tlm_u_tlm_tx_vc0_trn_N_68421_i_2476) + ); + defparam com_tlm_u_tlm_tx_vc0_trn_d_o_4_i_0_0_45_.INIT = 8'hD8; + LUT3_L com_tlm_u_tlm_tx_vc0_trn_d_o_4_i_0_0_45_ ( + .I0(com_tlm_u_tlm_tx_vc0_trn_vld_o_5_i_i_a2_i_a3_2455), + .I1(com_N_51628), + .I2(com_tlm_u_tlm_tx_vc0_trn_usr_d[45]), + .LO(com_tlm_u_tlm_tx_vc0_trn_N_31997_i) + ); + defparam com_tlm_u_tlm_tx_vc0_trn_d_o_4_i_0_0_44_.INIT = 8'hD8; + LUT3_L com_tlm_u_tlm_tx_vc0_trn_d_o_4_i_0_0_44_ ( + .I0(com_tlm_u_tlm_tx_vc0_trn_vld_o_5_i_i_a2_i_a3_2455), + .I1(com_N_51627), + .I2(com_tlm_u_tlm_tx_vc0_trn_usr_d[44]), + .LO(com_tlm_u_tlm_tx_vc0_trn_N_31995_i) + ); + defparam com_tlm_u_tlm_tx_vc0_trn_N_68420_i.INIT = 16'hD5C0; + LUT4_L com_tlm_u_tlm_tx_vc0_trn_N_68420_i ( + .I0(com_tlm_u_tlm_tx_vc0_trn_vld_o_5_i_i_a2_i_a3_2455), + .I1(com_tlm_u_tlm_tx_vc0_trn_d_o_4_0_0_0_a3[12]), + .I2(com_TLP_data_reg_11_), + .I3(com_tlm_u_tlm_tx_vc0_trn_usr_d[43]), + .LO(com_tlm_u_tlm_tx_vc0_trn_N_68420_i_2477) + ); + defparam com_tlm_u_tlm_tx_vc0_trn_N_68419_i.INIT = 16'hD5C0; + LUT4_L com_tlm_u_tlm_tx_vc0_trn_N_68419_i ( + .I0(com_tlm_u_tlm_tx_vc0_trn_vld_o_5_i_i_a2_i_a3_2455), + .I1(com_tlm_u_tlm_tx_vc0_trn_d_o_4_0_0_0_a3[12]), + .I2(com_TLP_data_reg_10_), + .I3(com_tlm_u_tlm_tx_vc0_trn_usr_d[42]), + .LO(com_tlm_u_tlm_tx_vc0_trn_N_68419_i_2478) + ); + defparam com_tlm_u_tlm_tx_vc0_trn_N_68418_i.INIT = 16'hD5C0; + LUT4_L com_tlm_u_tlm_tx_vc0_trn_N_68418_i ( + .I0(com_tlm_u_tlm_tx_vc0_trn_vld_o_5_i_i_a2_i_a3_2455), + .I1(com_tlm_u_tlm_tx_vc0_trn_d_o_4_0_0_0_a3[12]), + .I2(com_TLP_data_reg_9_), + .I3(com_tlm_u_tlm_tx_vc0_trn_usr_d[41]), + .LO(com_tlm_u_tlm_tx_vc0_trn_N_68418_i_2479) + ); + defparam com_tlm_u_tlm_tx_vc0_trn_N_68417_i.INIT = 16'hD5C0; + LUT4_L com_tlm_u_tlm_tx_vc0_trn_N_68417_i ( + .I0(com_tlm_u_tlm_tx_vc0_trn_vld_o_5_i_i_a2_i_a3_2455), + .I1(com_tlm_u_tlm_tx_vc0_trn_d_o_4_0_0_0_a3[12]), + .I2(com_TLP_data_reg_8_), + .I3(com_tlm_u_tlm_tx_vc0_trn_usr_d[40]), + .LO(com_tlm_u_tlm_tx_vc0_trn_N_68417_i_2480) + ); + defparam com_tlm_u_tlm_tx_vc0_trn_N_68768_i.INIT = 16'hD5C0; + LUT4_L com_tlm_u_tlm_tx_vc0_trn_N_68768_i ( + .I0(com_tlm_u_tlm_tx_vc0_trn_vld_o_5_i_i_a2_i_a3_2455), + .I1(com_tlm_u_tlm_tx_vc0_trn_d_o_4_0_0_0_a3[12]), + .I2(com_TLP_data_reg_7_), + .I3(com_tlm_u_tlm_tx_vc0_trn_usr_d[39]), + .LO(com_tlm_u_tlm_tx_vc0_trn_N_68768_i_2481) + ); + defparam com_tlm_u_tlm_tx_vc0_trn_N_68416_i.INIT = 16'hD5C0; + LUT4_L com_tlm_u_tlm_tx_vc0_trn_N_68416_i ( + .I0(com_tlm_u_tlm_tx_vc0_trn_vld_o_5_i_i_a2_i_a3_2455), + .I1(com_tlm_u_tlm_tx_vc0_trn_d_o_4_0_0_0_a3[12]), + .I2(com_TLP_data_reg_6_), + .I3(com_tlm_u_tlm_tx_vc0_trn_usr_d[38]), + .LO(com_tlm_u_tlm_tx_vc0_trn_N_68416_i_2482) + ); + defparam com_tlm_u_tlm_tx_vc0_trn_N_68415_i.INIT = 16'hD5C0; + LUT4_L com_tlm_u_tlm_tx_vc0_trn_N_68415_i ( + .I0(com_tlm_u_tlm_tx_vc0_trn_vld_o_5_i_i_a2_i_a3_2455), + .I1(com_tlm_u_tlm_tx_vc0_trn_d_o_4_0_0_0_a3[12]), + .I2(com_TLP_data_reg_5_), + .I3(com_tlm_u_tlm_tx_vc0_trn_usr_d[37]), + .LO(com_tlm_u_tlm_tx_vc0_trn_N_68415_i_2483) + ); + defparam com_tlm_u_tlm_tx_vc0_trn_N_68414_i.INIT = 16'hD5C0; + LUT4_L com_tlm_u_tlm_tx_vc0_trn_N_68414_i ( + .I0(com_tlm_u_tlm_tx_vc0_trn_vld_o_5_i_i_a2_i_a3_2455), + .I1(com_tlm_u_tlm_tx_vc0_trn_d_o_4_0_0_0_a3[12]), + .I2(com_TLP_data_reg_4_), + .I3(com_tlm_u_tlm_tx_vc0_trn_usr_d[36]), + .LO(com_tlm_u_tlm_tx_vc0_trn_N_68414_i_2484) + ); + defparam com_tlm_u_tlm_tx_vc0_trn_N_68413_i.INIT = 16'hD5C0; + LUT4_L com_tlm_u_tlm_tx_vc0_trn_N_68413_i ( + .I0(com_tlm_u_tlm_tx_vc0_trn_vld_o_5_i_i_a2_i_a3_2455), + .I1(com_tlm_u_tlm_tx_vc0_trn_d_o_4_0_0_0_a3[12]), + .I2(com_TLP_data_reg_3_), + .I3(com_tlm_u_tlm_tx_vc0_trn_usr_d[35]), + .LO(com_tlm_u_tlm_tx_vc0_trn_N_68413_i_2485) + ); + defparam com_tlm_u_tlm_tx_vc0_trn_N_68412_i.INIT = 16'hD5C0; + LUT4_L com_tlm_u_tlm_tx_vc0_trn_N_68412_i ( + .I0(com_tlm_u_tlm_tx_vc0_trn_vld_o_5_i_i_a2_i_a3_2455), + .I1(com_tlm_u_tlm_tx_vc0_trn_d_o_4_0_0_0_a3[12]), + .I2(com_TLP_data_reg_2_), + .I3(com_tlm_u_tlm_tx_vc0_trn_usr_d[34]), + .LO(com_tlm_u_tlm_tx_vc0_trn_N_68412_i_2486) + ); + defparam com_tlm_u_tlm_tx_vc0_trn_N_68411_i.INIT = 16'hD5C0; + LUT4_L com_tlm_u_tlm_tx_vc0_trn_N_68411_i ( + .I0(com_tlm_u_tlm_tx_vc0_trn_vld_o_5_i_i_a2_i_a3_2455), + .I1(com_tlm_u_tlm_tx_vc0_trn_d_o_4_0_0_0_a3[12]), + .I2(com_TLP_data_reg_1_), + .I3(com_tlm_u_tlm_tx_vc0_trn_usr_d[33]), + .LO(com_tlm_u_tlm_tx_vc0_trn_N_68411_i_2487) + ); + defparam com_tlm_u_tlm_tx_vc0_trn_d_o_4_i_i_i_32_.INIT = 8'hB0; + LUT3_L com_tlm_u_tlm_tx_vc0_trn_d_o_4_i_i_i_32_ ( + .I0(com_tlp_data_0_), + .I1(com_tlm_u_tlm_tx_vc0_trn_cfg_start), + .I2(com_tlm_u_tlm_tx_vc0_trn_d_o_4_i_i_i_0[32]), + .LO(com_tlm_u_tlm_tx_vc0_trn_N_48002_i) + ); + defparam com_tlm_u_tlm_tx_vc0_trn_d_o_4_i_0_0_61_.INIT = 8'hC8; + LUT3_L com_tlm_u_tlm_tx_vc0_trn_d_o_4_i_0_0_61_ ( + .I0(com_tlm_u_tlm_tx_vc0_trn_vld_o_5_i_i_a2_i_a3_2455), + .I1(com_tlm_u_tlm_tx_vc0_trn_d_o_4_i_0_0_0[61]), + .I2(com_tlm_u_tlm_tx_vc0_trn_usr_d[61]), + .LO(com_tlm_u_tlm_tx_vc0_trn_N_28282_i) + ); + defparam com_tlm_u_tlm_tx_vc0_trn_d_o_4_i_0_0_60_.INIT = 8'hD8; + LUT3_L com_tlm_u_tlm_tx_vc0_trn_d_o_4_i_0_0_60_ ( + .I0(com_tlm_u_tlm_tx_vc0_trn_vld_o_5_i_i_a2_i_a3_2455), + .I1(com_cmmt_td_0_i_m2_i_m2_i_m2_i_m3_0[60]), + .I2(com_tlm_u_tlm_tx_vc0_trn_usr_d[60]), + .LO(com_tlm_u_tlm_tx_vc0_trn_N_32006_i) + ); + defparam com_tlm_u_tlm_tx_vc0_trn_d_o_4_i_0_0_59_.INIT = 16'h1101; + LUT4_L com_tlm_u_tlm_tx_vc0_trn_d_o_4_i_0_0_59_ ( + .I0(com_tlm_u_tlm_tx_vc0_trn_d_o_4_i_0_0_a2_1[57]), + .I1(com_tlm_u_tlm_tx_vc0_trn_N_49591), + .I2(com_tlm_u_tlm_tx_vc0_trn_d_o_4_0_0_0_a3[12]), + .I3(com_TLP_data_reg_27_), + .LO(com_tlm_u_tlm_tx_vc0_trn_N_28280_i) + ); + defparam com_tlm_u_tlm_tx_vc0_trn_d_o_4_i_m3_i_0_58_.INIT = 8'hD8; + LUT3_L com_tlm_u_tlm_tx_vc0_trn_d_o_4_i_m3_i_0_58_ ( + .I0(com_tlm_u_tlm_tx_vc0_trn_vld_o_5_i_i_a2_i_a3_2455), + .I1(com_N_51633), + .I2(com_tlm_u_tlm_tx_vc0_trn_usr_d[58]), + .LO(com_tlm_u_tlm_tx_vc0_trn_N_39535_i) + ); + defparam com_tlm_u_tlm_tx_vc0_trn_d_o_4_i_0_0_57_.INIT = 16'h1101; + LUT4_L com_tlm_u_tlm_tx_vc0_trn_d_o_4_i_0_0_57_ ( + .I0(com_tlm_u_tlm_tx_vc0_trn_N_49588), + .I1(com_tlm_u_tlm_tx_vc0_trn_d_o_4_i_0_0_a2_1[57]), + .I2(com_tlm_u_tlm_tx_vc0_trn_d_o_4_0_0_0_a3[12]), + .I3(com_TLP_data_reg_25_), + .LO(com_tlm_u_tlm_tx_vc0_trn_N_28276_i) + ); + defparam com_tlm_u_tlm_tx_vc0_trn_d_o_4_i_m3_i_0_56_.INIT = 8'hD8; + LUT3_L com_tlm_u_tlm_tx_vc0_trn_d_o_4_i_m3_i_0_56_ ( + .I0(com_tlm_u_tlm_tx_vc0_trn_vld_o_5_i_i_a2_i_a3_2455), + .I1(com_N_51632), + .I2(com_tlm_u_tlm_tx_vc0_trn_usr_d[56]), + .LO(com_tlm_u_tlm_tx_vc0_trn_N_39533_i) + ); + defparam com_tlm_u_tlm_tx_vc0_trn_N_68427_i.INIT = 16'hD5C0; + LUT4_L com_tlm_u_tlm_tx_vc0_trn_N_68427_i ( + .I0(com_tlm_u_tlm_tx_vc0_trn_vld_o_5_i_i_a2_i_a3_2455), + .I1(com_tlm_u_tlm_tx_vc0_trn_d_o_4_0_0_0_a3[12]), + .I2(com_TLP_data_reg_23_), + .I3(com_tlm_u_tlm_tx_vc0_trn_usr_d[55]), + .LO(com_tlm_u_tlm_tx_vc0_trn_N_68427_i_2488) + ); + defparam com_tlm_u_tlm_tx_vc0_trn_d_o_4_i_m2_i_0_0_54_.INIT = 8'hD8; + LUT3_L com_tlm_u_tlm_tx_vc0_trn_d_o_4_i_m2_i_0_0_54_ ( + .I0(com_tlm_u_tlm_tx_vc0_trn_vld_o_5_i_i_a2_i_a3_2455), + .I1(com_N_51631), + .I2(com_tlm_u_tlm_tx_vc0_trn_usr_d[54]), + .LO(com_tlm_u_tlm_tx_vc0_trn_N_32089_i) + ); + defparam com_tlm_u_tlm_tx_vc0_trn_d_o_4_i_m2_i_0_0_53_.INIT = 8'hD8; + LUT3_L com_tlm_u_tlm_tx_vc0_trn_d_o_4_i_m2_i_0_0_53_ ( + .I0(com_tlm_u_tlm_tx_vc0_trn_vld_o_5_i_i_a2_i_a3_2455), + .I1(com_N_51630), + .I2(com_tlm_u_tlm_tx_vc0_trn_usr_d[53]), + .LO(com_tlm_u_tlm_tx_vc0_trn_N_32087_i) + ); + defparam com_tlm_u_tlm_tx_vc0_trn_d_o_4_i_m2_i_0_0_52_.INIT = 8'hD8; + LUT3_L com_tlm_u_tlm_tx_vc0_trn_d_o_4_i_m2_i_0_0_52_ ( + .I0(com_tlm_u_tlm_tx_vc0_trn_vld_o_5_i_i_a2_i_a3_2455), + .I1(com_N_51629), + .I2(com_tlm_u_tlm_tx_vc0_trn_usr_d[52]), + .LO(com_tlm_u_tlm_tx_vc0_trn_N_32085_i) + ); + defparam com_tlm_u_tlm_tx_vc0_trn_N_68426_i.INIT = 16'hD5C0; + LUT4_L com_tlm_u_tlm_tx_vc0_trn_N_68426_i ( + .I0(com_tlm_u_tlm_tx_vc0_trn_vld_o_5_i_i_a2_i_a3_2455), + .I1(com_tlm_u_tlm_tx_vc0_trn_d_o_4_0_0_0_a3[12]), + .I2(com_TLP_data_reg_19_), + .I3(com_tlm_u_tlm_tx_vc0_trn_usr_d[51]), + .LO(com_tlm_u_tlm_tx_vc0_trn_N_68426_i_2489) + ); + defparam com_tlm_u_tlm_tx_vc0_trn_N_68425_i.INIT = 16'hD5C0; + LUT4_L com_tlm_u_tlm_tx_vc0_trn_N_68425_i ( + .I0(com_tlm_u_tlm_tx_vc0_trn_vld_o_5_i_i_a2_i_a3_2455), + .I1(com_tlm_u_tlm_tx_vc0_trn_d_o_4_0_0_0_a3[12]), + .I2(com_TLP_data_reg_18_), + .I3(com_tlm_u_tlm_tx_vc0_trn_usr_d[50]), + .LO(com_tlm_u_tlm_tx_vc0_trn_N_68425_i_2490) + ); + defparam com_tlm_u_tlm_tx_vc0_trn_N_68424_i.INIT = 16'hD5C0; + LUT4_L com_tlm_u_tlm_tx_vc0_trn_N_68424_i ( + .I0(com_tlm_u_tlm_tx_vc0_trn_vld_o_5_i_i_a2_i_a3_2455), + .I1(com_tlm_u_tlm_tx_vc0_trn_d_o_4_0_0_0_a3[12]), + .I2(com_TLP_data_reg_17_), + .I3(com_tlm_u_tlm_tx_vc0_trn_usr_d[49]), + .LO(com_tlm_u_tlm_tx_vc0_trn_N_68424_i_2491) + ); + defparam com_tlm_u_tlm_tx_vc0_trn_N_68423_i.INIT = 16'hD5C0; + LUT4_L com_tlm_u_tlm_tx_vc0_trn_N_68423_i ( + .I0(com_tlm_u_tlm_tx_vc0_trn_vld_o_5_i_i_a2_i_a3_2455), + .I1(com_tlm_u_tlm_tx_vc0_trn_d_o_4_0_0_0_a3[12]), + .I2(com_TLP_data_reg_16_), + .I3(com_tlm_u_tlm_tx_vc0_trn_usr_d[48]), + .LO(com_tlm_u_tlm_tx_vc0_trn_N_68423_i_2492) + ); + defparam com_tlm_u_tlm_tx_vc0_trn_N_68422_i.INIT = 16'hD5C0; + LUT4_L com_tlm_u_tlm_tx_vc0_trn_N_68422_i ( + .I0(com_tlm_u_tlm_tx_vc0_trn_vld_o_5_i_i_a2_i_a3_2455), + .I1(com_tlm_u_tlm_tx_vc0_trn_d_o_4_0_0_0_a3[12]), + .I2(com_TLP_data_reg_15_), + .I3(com_tlm_u_tlm_tx_vc0_trn_usr_d[47]), + .LO(com_tlm_u_tlm_tx_vc0_trn_N_68422_i_2493) + ); + defparam com_tlm_u_tlm_tx_vc0_trn_N_68767_i.INIT = 16'hD5C0; + LUT4_L com_tlm_u_tlm_tx_vc0_trn_N_68767_i ( + .I0(com_tlm_u_tlm_tx_vc0_trn_vld_o_5_i_i_a2_i_a3_2455), + .I1(com_tlm_u_tlm_tx_vc0_trn_d_o_4_0_0_0_a3[12]), + .I2(com_TLP_data_reg_31_), + .I3(com_tlm_u_tlm_tx_vc0_trn_usr_d[63]), + .LO(com_tlm_u_tlm_tx_vc0_trn_N_68767_i_2494) + ); + defparam com_tlm_u_tlm_tx_vc0_trn_d_o_4_i_0_0_62_.INIT = 8'hB0; + LUT3_L com_tlm_u_tlm_tx_vc0_trn_d_o_4_i_0_0_62_ ( + .I0(com_tlp_data_0_), + .I1(com_tlm_u_tlm_tx_vc0_trn_cfg_start), + .I2(com_tlm_u_tlm_tx_vc0_trn_d_o_4_i_0_0_0[62]), + .LO(com_tlm_u_tlm_tx_vc0_trn_N_32008_i) + ); + defparam com_tlm_u_tlm_tx_vc0_trn_trn_rem_i.INIT = 4'h1; + LUT1_L com_tlm_u_tlm_tx_vc0_trn_trn_rem_i ( + .I0(com_tlm_u_tlm_tx_vc0_trn_trn_rem), + .LO(com_tlm_u_tlm_tx_vc0_trn_rem_i) + ); + defparam com_tlm_u_tlm_tx_vc0_trn_usr_d_i_62_.INIT = 4'h1; + LUT1_L com_tlm_u_tlm_tx_vc0_trn_usr_d_i_62_ ( + .I0(com_tlm_u_tlm_tx_vc0_trn_usr_d[62]), + .LO(com_tlm_u_tlm_tx_vc0_trn_usr_d_i[62]) + ); + defparam com_tlm_u_tlm_tx_vc0_trn_N_48986_i_i.INIT = 4'h1; + LUT1_L com_tlm_u_tlm_tx_vc0_trn_N_48986_i_i ( + .I0(com_tlm_u_tlm_tx_vc0_trn_N_48986_i), + .LO(com_tlm_u_tlm_tx_vc0_trn_N_48986_i_i_2441) + ); + defparam com_tlm_u_tlm_tx_vc0_trn_N_49953_i.INIT = 4'hB; + LUT2_L com_tlm_u_tlm_tx_vc0_trn_N_49953_i ( + .I0(com_tlm_u_tlm_tx_vc0_trn_trn_tdst_dsc), + .I1(trn_teof_n), + .LO(com_tlm_u_tlm_tx_vc0_trn_N_49953_i_2442) + ); + defparam com_tlm_u_tlm_tx_vc0_trn_usr_eof_filt_0_a2_0_a2_0_a2.INIT = 4'h8; + LUT2_L com_tlm_u_tlm_tx_vc0_trn_usr_eof_filt_0_a2_0_a2_0_a2 ( + .I0(com_tlm_u_tlm_tx_vc0_trn_usr_eof_2443), + .I1(com_tlm_u_tlm_tx_vc0_trn_usr_frame_2451), + .LO(com_tlm_u_tlm_tx_vc0_trn_usr_eof_filt) + ); + defparam com_tlm_u_tlm_tx_vc0_trn_N_49952_i.INIT = 4'hB; + LUT2_L com_tlm_u_tlm_tx_vc0_trn_N_49952_i ( + .I0(trn_teof_n), + .I1(trn_trem_n_5058[0]), + .LO(com_tlm_u_tlm_tx_vc0_trn_N_49952_i_2444) + ); + defparam com_tlm_u_tlm_tx_vc0_trn_un13_pkt_incoming_o_i.INIT = 4'hE; + LUT2_L com_tlm_u_tlm_tx_vc0_trn_un13_pkt_incoming_o_i ( + .I0(com_tlm_u_tlm_tx_vc0_trn_pkts_in_trn[0]), + .I1(com_tlm_u_tlm_tx_vc0_trn_pkts_in_trn[1]), + .LO(com_tlm_u_tlm_tx_vc0_trn_un13_pkt_incoming_o_i_2445) + ); + defparam com_tlm_u_tlm_tx_vc0_trn_usr_abort_3_i_0_0_0.INIT = 4'h4; + LUT2_L com_tlm_u_tlm_tx_vc0_trn_usr_abort_3_i_0_0_0 ( + .I0(com_tlm_u_tlm_tx_vc0_trn_N_48986_i), + .I1(com_tlm_u_tlm_tx_vc0_trn_usr_frame_in_2461), + .LO(com_tlm_u_tlm_tx_vc0_trn_N_13635_i) + ); + defparam com_tlm_u_tlm_tx_vc0_trn_load_val_64_load_value10_i.INIT = 4'h1; + LUT1_L com_tlm_u_tlm_tx_vc0_trn_load_val_64_load_value10_i ( + .I0(com_tlm_u_tlm_tx_vc0_trn_load_value10), + .LO(com_tlm_u_tlm_tx_vc0_trn_load_value10_i) + ); + defparam com_tlm_u_tlm_tx_vc0_trn_N_68962_i.INIT = 4'hE; + LUT2_L com_tlm_u_tlm_tx_vc0_trn_N_68962_i ( + .I0(com_tlm_u_tlm_tx_vc0_trn_cfg_start), + .I1(com_tlm_u_tlm_tx_vc0_trn_usr_start), + .LO(com_tlm_u_tlm_tx_vc0_trn_N_68962_i_2446) + ); + defparam com_tlm_u_tlm_tx_vc0_trn_usr_frame_in17_0_a4_0_a2_0_a2_0_a2.INIT = 4'h2; + LUT2_L com_tlm_u_tlm_tx_vc0_trn_usr_frame_in17_0_a4_0_a2_0_a2_0_a2 ( + .I0(com_tlm_u_tlm_tx_vc0_trn_N_48986_i), + .I1(trn_tsof_n), + .LO(com_tlm_u_tlm_tx_vc0_trn_usr_frame_in17) + ); + defparam com_tlm_u_tlm_tx_vc0_trn_eof_o_5_i_0_0.INIT = 16'hC444; + LUT4_L com_tlm_u_tlm_tx_vc0_trn_eof_o_5_i_0_0 ( + .I0(com_grant_reg_iv_0_0_0_a2), + .I1(com_tlm_u_tlm_tx_vc0_trn_eof_o_5_i_0_0_0_2447), + .I2(com_tlm_u_tlm_tx_vc0_trn_usr_frame_2451), + .I3(com_tlm_u_tlm_tx_vc0_trn_usr_vld_2450), + .LO(com_tlm_u_tlm_tx_vc0_trn_N_28284_i) + ); + defparam com_tlm_u_tlm_tx_vc0_trn_errfwd_o_5_i_0_0.INIT = 4'h8; + LUT2_L com_tlm_u_tlm_tx_vc0_trn_errfwd_o_5_i_0_0 ( + .I0(com_tlm_u_tlm_tx_vc0_trn_vld_o_5_i_i_a2_i_a2_2456), + .I1(com_tlm_u_tlm_tx_vc0_trn_usr_errfwd_2448), + .LO(com_tlm_u_tlm_tx_vc0_trn_N_28286_i) + ); + defparam com_tlm_u_tlm_tx_vc0_trn_N_68957_i.INIT = 16'hF2AA; + LUT4_L com_tlm_u_tlm_tx_vc0_trn_N_68957_i ( + .I0(com_tlm_u_tlm_tx_vc0_trn_cfg_start), + .I1(com_tlm_u_tlm_tx_vc0_trn_usr_frame_2451), + .I2(com_tlm_u_tlm_tx_vc0_trn_usr_sof_filt), + .I3(com_tlm_u_tlm_tx_vc0_trn_usr_vld_2450), + .LO(com_tlm_u_tlm_tx_vc0_trn_N_68957_i_2449) + ); + defparam com_tlm_u_tlm_tx_vc0_trn_N_68115_i.INIT = 16'hFEAE; + LUT4_L com_tlm_u_tlm_tx_vc0_trn_N_68115_i ( + .I0(com_tlm_u_tlm_tx_vc0_trn_N_49231), + .I1(com_grant_reg_iv_0_0_0_a2), + .I2(com_tlm_u_tlm_tx_vc0_trn_vld_o_5_i_i_a2_i_a2_2456), + .I3(com_tlm_u_tlm_tx_vc0_trn_usr_rem_2453), + .LO(com_tlm_u_tlm_tx_vc0_trn_N_68115_i_2452) + ); + defparam com_tlm_u_tlm_tx_vc0_trn_N_68621_i.INIT = 4'hE; + LUT2_L com_tlm_u_tlm_tx_vc0_trn_N_68621_i ( + .I0(com_tlm_u_tlm_tx_vc0_trn_vld_o_5_i_i_a2_i_a2_2456), + .I1(com_tlm_u_tlm_tx_vc0_trn_vld_o_5_i_i_a2_i_a3_2455), + .LO(com_tlm_u_tlm_tx_vc0_trn_N_68621_i_2454) + ); + defparam com_tlm_u_tlm_tx_vc0_trn_dsc_in_q_3_0_i_0_0.INIT = 8'hE0; + LUT3_L com_tlm_u_tlm_tx_vc0_trn_dsc_in_q_3_0_i_0_0 ( + .I0(com_tlm_u_tlm_tx_vc0_trn_pkts_in_trn_1_sqmuxa_5604_i_0_0_0_o3_2457), + .I1(com_tlm_u_tlm_tx_vc0_trn_trn_tdst_dsc), + .I2(com_tlm_u_tlm_tx_vc0_trn_usr_eof_filt_q_4_), + .LO(com_tlm_u_tlm_tx_vc0_trn_N_28290_i) + ); + defparam com_tlm_u_tlm_tx_vc0_trn_N_68986_i.INIT = 16'hAEAA; + LUT4_L com_tlm_u_tlm_tx_vc0_trn_N_68986_i ( + .I0(com_tlm_u_tlm_tx_vc0_trn_N_49237), + .I1(com_grant_reg_iv_0_0_0_a2), + .I2(com_tlm_u_tlm_tx_vc0_trn_trn_tdst_rdy), + .I3(com_tlm_u_tlm_tx_vc0_trn_cfg_frame_in_2459), + .LO(com_tlm_u_tlm_tx_vc0_trn_N_68986_i_2458) + ); + defparam com_tlm_u_tlm_tx_vc0_trn_N_68987_i.INIT = 16'hBAAA; + LUT4_L com_tlm_u_tlm_tx_vc0_trn_N_68987_i ( + .I0(com_tlm_u_tlm_tx_vc0_trn_N_39932), + .I1(com_tlm_u_tlm_tx_vc0_trn_N_49515), + .I2(com_tlm_u_tlm_tx_vc0_trn_trn_tdst_rdy_o_3_0_0_0_a2_0_0), + .I3(com_tlm_u_tlm_tx_vc0_trn_usr_frame_in_2461), + .LO(com_tlm_u_tlm_tx_vc0_trn_N_68987_i_2460) + ); + defparam com_tlm_u_tlm_tx_vc0_trn_buffer_rdy_3_i_0_0_0.INIT = 16'h444C; + LUT4_L com_tlm_u_tlm_tx_vc0_trn_buffer_rdy_3_i_0_0_0 ( + .I0(com_tlm_u_tlm_tx_vc0_trn_buf_av_one_2463), + .I1(com_tlm_u_tlm_tx_vc0_trn_buffer_rdy_3_i_0_0_0_0_2462), + .I2(com_tlm_u_tlm_tx_vc0_trn_cfg_start), + .I3(com_tlm_u_tlm_tx_vc0_trn_usr_start), + .LO(com_tlm_u_tlm_tx_vc0_trn_N_13653_i) + ); + defparam com_tlm_u_tlm_tx_vc0_trn_un1_trn_tbuf_av_o_1_axb_4.INIT = 8'h78; + LUT3_L com_tlm_u_tlm_tx_vc0_trn_un1_trn_tbuf_av_o_1_axb_4 ( + .I0(com_tlm_u_tlm_tx_vc0_trn_N_13806_i), + .I1(com_tlm_u_tlm_tx_vc0_trn_start_frame_q_2470), + .I2(NlwRenamedSig_OI_trn_tbuf_av[4]), + .LO(com_tlm_u_tlm_tx_vc0_trn_un1_trn_tbuf_av_o_1_axb_4_2464) + ); + defparam com_tlm_u_tlm_tx_vc0_trn_un1_trn_tbuf_av_o_1_axb_3.INIT = 8'h78; + LUT3_L com_tlm_u_tlm_tx_vc0_trn_un1_trn_tbuf_av_o_1_axb_3 ( + .I0(com_tlm_u_tlm_tx_vc0_trn_N_13806_i), + .I1(com_tlm_u_tlm_tx_vc0_trn_start_frame_q_2470), + .I2(NlwRenamedSig_OI_trn_tbuf_av[3]), + .LO(com_tlm_u_tlm_tx_vc0_trn_un1_trn_tbuf_av_o_1_axb_3_2465) + ); + defparam com_tlm_u_tlm_tx_vc0_trn_un1_trn_tbuf_av_o_1_axb_2.INIT = 8'h78; + LUT3_L com_tlm_u_tlm_tx_vc0_trn_un1_trn_tbuf_av_o_1_axb_2 ( + .I0(com_tlm_u_tlm_tx_vc0_trn_N_13806_i), + .I1(com_tlm_u_tlm_tx_vc0_trn_start_frame_q_2470), + .I2(NlwRenamedSig_OI_trn_tbuf_av[2]), + .LO(com_tlm_u_tlm_tx_vc0_trn_un1_trn_tbuf_av_o_1_axb_2_2466) + ); + defparam com_tlm_u_tlm_tx_vc0_trn_un1_trn_tbuf_av_o_1_axb_1.INIT = 8'h78; + LUT3_L com_tlm_u_tlm_tx_vc0_trn_un1_trn_tbuf_av_o_1_axb_1 ( + .I0(com_tlm_u_tlm_tx_vc0_trn_N_13806_i), + .I1(com_tlm_u_tlm_tx_vc0_trn_start_frame_q_2470), + .I2(NlwRenamedSig_OI_trn_tbuf_av[1]), + .LO(com_tlm_u_tlm_tx_vc0_trn_un1_trn_tbuf_av_o_1_axb_1_2467) + ); + defparam com_tlm_u_tlm_tx_vc0_trn_un1_pkts_in_trn_1_axbxc1.INIT = 16'h956A; + LUT4_L com_tlm_u_tlm_tx_vc0_trn_un1_pkts_in_trn_1_axbxc1 ( + .I0(com_tlm_u_tlm_tx_vc0_trn_N_13683_i), + .I1(com_tlm_u_tlm_tx_vc0_trn_pkts_in_trn28_i_i), + .I2(com_tlm_u_tlm_tx_vc0_trn_pkts_in_trn[0]), + .I3(com_tlm_u_tlm_tx_vc0_trn_pkts_in_trn[1]), + .LO(com_tlm_u_tlm_tx_vc0_trn_un1_pkts_in_trn_1_axbxc1_2468) + ); + defparam com_tlm_u_tlm_tx_vc0_trn_un1_buf_av_one_1_i_0_0_0_a2_0_.INIT = 8'h02; + LUT3 com_tlm_u_tlm_tx_vc0_trn_un1_buf_av_one_1_i_0_0_0_a2_0_ ( + .I0(com_tlm_u_tlm_tx_vc0_trn_start_frame_q_2470), + .I1(com_tlm_u_tlm_tx_vc0_trn_usr_abort_2496), + .I2(com_tlm_u_tlm_tx_vc0_trn_released_buf_x_2469), + .O(com_tlm_u_tlm_tx_vc0_trn_un1_buf_av_one_1_i_0_0_0_a2[0]) + ); + defparam com_tlm_u_tlm_tx_vc0_trn_un1_usr_abort_6_0_0_0_0_a2.INIT = 8'h54; + LUT3 com_tlm_u_tlm_tx_vc0_trn_un1_usr_abort_6_0_0_0_0_a2 ( + .I0(com_tlm_u_tlm_tx_vc0_trn_start_frame_q_2470), + .I1(com_tlm_u_tlm_tx_vc0_trn_usr_abort_2496), + .I2(com_tlm_u_tlm_tx_vc0_trn_released_buf_x_2469), + .O(com_tlm_u_tlm_tx_vc0_trn_N_49500) + ); + FD com_tlm_u_tlm_tx_vc0_trn_usr_eof_filt_q_DOUT_0_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_trn_usr_eof_filt_q_N_6), + .Q(com_tlm_u_tlm_tx_vc0_trn_usr_eof_filt_q_4_) + ); + FD com_tlm_u_tlm_tx_vc0_trn_usr_no_eof_err ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_trn_usr_no_eof_err14), + .Q(com_tlm_u_tlm_tx_vc0_trn_trn_tdst_dsc) + ); + FD com_tlm_u_tlm_tx_vc0_trn_d_o_1_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_trn_N_31925_i), + .Q(com_tlm_u_tlm_tx_vc0_trn_d[1]) + ); + FD com_tlm_u_tlm_tx_vc0_trn_d_o_0_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_trn_N_31923_i), + .Q(com_tlm_u_tlm_tx_vc0_trn_d[0]) + ); + FD com_tlm_u_tlm_tx_vc0_trn_d_o_16_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_trn_N_68408_i_2471), + .Q(com_tlm_u_tlm_tx_vc0_trn_d[16]) + ); + FD com_tlm_u_tlm_tx_vc0_trn_d_o_15_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_trn_N_31951_i), + .Q(com_tlm_u_tlm_tx_vc0_trn_d[15]) + ); + FD com_tlm_u_tlm_tx_vc0_trn_d_o_14_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_trn_N_68407_i_2472), + .Q(com_tlm_u_tlm_tx_vc0_trn_d[14]) + ); + FD com_tlm_u_tlm_tx_vc0_trn_d_o_13_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_trn_N_31948_i), + .Q(com_tlm_u_tlm_tx_vc0_trn_d[13]) + ); + FD com_tlm_u_tlm_tx_vc0_trn_d_o_12_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_trn_N_68406_i_2473), + .Q(com_tlm_u_tlm_tx_vc0_trn_d[12]) + ); + FD com_tlm_u_tlm_tx_vc0_trn_d_o_11_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_trn_N_31945_i), + .Q(com_tlm_u_tlm_tx_vc0_trn_d[11]) + ); + FD com_tlm_u_tlm_tx_vc0_trn_d_o_10_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_trn_N_31943_i), + .Q(com_tlm_u_tlm_tx_vc0_trn_d[10]) + ); + FD com_tlm_u_tlm_tx_vc0_trn_d_o_9_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_trn_N_31941_i), + .Q(com_tlm_u_tlm_tx_vc0_trn_d[9]) + ); + FD com_tlm_u_tlm_tx_vc0_trn_d_o_8_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_trn_N_31939_i), + .Q(com_tlm_u_tlm_tx_vc0_trn_d[8]) + ); + FD com_tlm_u_tlm_tx_vc0_trn_d_o_7_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_trn_N_31937_i), + .Q(com_tlm_u_tlm_tx_vc0_trn_d[7]) + ); + FD com_tlm_u_tlm_tx_vc0_trn_d_o_6_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_trn_N_31935_i), + .Q(com_tlm_u_tlm_tx_vc0_trn_d[6]) + ); + FD com_tlm_u_tlm_tx_vc0_trn_d_o_5_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_trn_N_31933_i), + .Q(com_tlm_u_tlm_tx_vc0_trn_d[5]) + ); + FD com_tlm_u_tlm_tx_vc0_trn_d_o_4_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_trn_N_31931_i), + .Q(com_tlm_u_tlm_tx_vc0_trn_d[4]) + ); + FD com_tlm_u_tlm_tx_vc0_trn_d_o_3_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_trn_N_31929_i), + .Q(com_tlm_u_tlm_tx_vc0_trn_d[3]) + ); + FD com_tlm_u_tlm_tx_vc0_trn_d_o_2_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_trn_N_31927_i), + .Q(com_tlm_u_tlm_tx_vc0_trn_d[2]) + ); + FD com_tlm_u_tlm_tx_vc0_trn_d_o_31_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_trn_N_31980_i), + .Q(com_tlm_u_tlm_tx_vc0_trn_d[31]) + ); + FD com_tlm_u_tlm_tx_vc0_trn_d_o_30_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_trn_N_31978_i), + .Q(com_tlm_u_tlm_tx_vc0_trn_d[30]) + ); + FD com_tlm_u_tlm_tx_vc0_trn_d_o_29_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_trn_N_31976_i), + .Q(com_tlm_u_tlm_tx_vc0_trn_d[29]) + ); + FD com_tlm_u_tlm_tx_vc0_trn_d_o_28_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_trn_N_31974_i), + .Q(com_tlm_u_tlm_tx_vc0_trn_d[28]) + ); + FD com_tlm_u_tlm_tx_vc0_trn_d_o_27_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_trn_N_31972_i), + .Q(com_tlm_u_tlm_tx_vc0_trn_d[27]) + ); + FD com_tlm_u_tlm_tx_vc0_trn_d_o_26_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_trn_N_31970_i), + .Q(com_tlm_u_tlm_tx_vc0_trn_d[26]) + ); + FD com_tlm_u_tlm_tx_vc0_trn_d_o_25_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_trn_N_31968_i), + .Q(com_tlm_u_tlm_tx_vc0_trn_d[25]) + ); + FD com_tlm_u_tlm_tx_vc0_trn_d_o_24_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_trn_N_31966_i), + .Q(com_tlm_u_tlm_tx_vc0_trn_d[24]) + ); + FD com_tlm_u_tlm_tx_vc0_trn_d_o_23_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_trn_N_31964_i), + .Q(com_tlm_u_tlm_tx_vc0_trn_d[23]) + ); + FD com_tlm_u_tlm_tx_vc0_trn_d_o_22_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_trn_N_31962_i), + .Q(com_tlm_u_tlm_tx_vc0_trn_d[22]) + ); + FD com_tlm_u_tlm_tx_vc0_trn_d_o_21_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_trn_N_31960_i), + .Q(com_tlm_u_tlm_tx_vc0_trn_d[21]) + ); + FD com_tlm_u_tlm_tx_vc0_trn_d_o_20_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_trn_N_31958_i), + .Q(com_tlm_u_tlm_tx_vc0_trn_d[20]) + ); + FD com_tlm_u_tlm_tx_vc0_trn_d_o_19_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_trn_N_31956_i), + .Q(com_tlm_u_tlm_tx_vc0_trn_d[19]) + ); + FD com_tlm_u_tlm_tx_vc0_trn_d_o_18_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_trn_N_68410_i_2474), + .Q(com_tlm_u_tlm_tx_vc0_trn_d[18]) + ); + FD com_tlm_u_tlm_tx_vc0_trn_d_o_17_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_trn_N_68409_i_2475), + .Q(com_tlm_u_tlm_tx_vc0_trn_d[17]) + ); + FD com_tlm_u_tlm_tx_vc0_trn_d_o_46_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_trn_N_68421_i_2476), + .Q(com_tlm_u_tlm_tx_vc0_trn_d[46]) + ); + FD com_tlm_u_tlm_tx_vc0_trn_d_o_45_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_trn_N_31997_i), + .Q(com_tlm_u_tlm_tx_vc0_trn_d[45]) + ); + FD com_tlm_u_tlm_tx_vc0_trn_d_o_44_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_trn_N_31995_i), + .Q(com_tlm_u_tlm_tx_vc0_trn_d[44]) + ); + FD com_tlm_u_tlm_tx_vc0_trn_d_o_43_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_trn_N_68420_i_2477), + .Q(com_tlm_u_tlm_tx_vc0_trn_d[43]) + ); + FD com_tlm_u_tlm_tx_vc0_trn_d_o_42_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_trn_N_68419_i_2478), + .Q(com_tlm_u_tlm_tx_vc0_trn_d[42]) + ); + FD com_tlm_u_tlm_tx_vc0_trn_d_o_41_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_trn_N_68418_i_2479), + .Q(com_tlm_u_tlm_tx_vc0_trn_d[41]) + ); + FD com_tlm_u_tlm_tx_vc0_trn_d_o_40_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_trn_N_68417_i_2480), + .Q(com_tlm_u_tlm_tx_vc0_trn_d[40]) + ); + FD com_tlm_u_tlm_tx_vc0_trn_d_o_39_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_trn_N_68768_i_2481), + .Q(com_tlm_u_tlm_tx_vc0_trn_d[39]) + ); + FD com_tlm_u_tlm_tx_vc0_trn_d_o_38_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_trn_N_68416_i_2482), + .Q(com_tlm_u_tlm_tx_vc0_trn_d[38]) + ); + FD com_tlm_u_tlm_tx_vc0_trn_d_o_37_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_trn_N_68415_i_2483), + .Q(com_tlm_u_tlm_tx_vc0_trn_d[37]) + ); + FD com_tlm_u_tlm_tx_vc0_trn_d_o_36_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_trn_N_68414_i_2484), + .Q(com_tlm_u_tlm_tx_vc0_trn_d[36]) + ); + FD com_tlm_u_tlm_tx_vc0_trn_d_o_35_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_trn_N_68413_i_2485), + .Q(com_tlm_u_tlm_tx_vc0_trn_d[35]) + ); + FD com_tlm_u_tlm_tx_vc0_trn_d_o_34_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_trn_N_68412_i_2486), + .Q(com_tlm_u_tlm_tx_vc0_trn_d[34]) + ); + FD com_tlm_u_tlm_tx_vc0_trn_d_o_33_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_trn_N_68411_i_2487), + .Q(com_tlm_u_tlm_tx_vc0_trn_d[33]) + ); + FD com_tlm_u_tlm_tx_vc0_trn_d_o_32_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_trn_N_48002_i), + .Q(com_tlm_u_tlm_tx_vc0_trn_d[32]) + ); + FD com_tlm_u_tlm_tx_vc0_trn_d_o_61_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_trn_N_28282_i), + .Q(com_tlm_u_tlm_tx_vc0_trn_d[61]) + ); + FD com_tlm_u_tlm_tx_vc0_trn_d_o_60_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_trn_N_32006_i), + .Q(com_tlm_u_tlm_tx_vc0_trn_d[60]) + ); + FD com_tlm_u_tlm_tx_vc0_trn_d_o_59_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_trn_N_28280_i), + .Q(com_tlm_u_tlm_tx_vc0_trn_d[59]) + ); + FD com_tlm_u_tlm_tx_vc0_trn_d_o_58_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_trn_N_39535_i), + .Q(com_tlm_u_tlm_tx_vc0_trn_d[58]) + ); + FD com_tlm_u_tlm_tx_vc0_trn_d_o_57_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_trn_N_28276_i), + .Q(com_tlm_u_tlm_tx_vc0_trn_d[57]) + ); + FD com_tlm_u_tlm_tx_vc0_trn_d_o_56_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_trn_N_39533_i), + .Q(com_tlm_u_tlm_tx_vc0_trn_d[56]) + ); + FD com_tlm_u_tlm_tx_vc0_trn_d_o_55_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_trn_N_68427_i_2488), + .Q(com_tlm_u_tlm_tx_vc0_trn_d[55]) + ); + FD com_tlm_u_tlm_tx_vc0_trn_d_o_54_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_trn_N_32089_i), + .Q(com_tlm_u_tlm_tx_vc0_trn_d[54]) + ); + FD com_tlm_u_tlm_tx_vc0_trn_d_o_53_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_trn_N_32087_i), + .Q(com_tlm_u_tlm_tx_vc0_trn_d[53]) + ); + FD com_tlm_u_tlm_tx_vc0_trn_d_o_52_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_trn_N_32085_i), + .Q(com_tlm_u_tlm_tx_vc0_trn_d[52]) + ); + FD com_tlm_u_tlm_tx_vc0_trn_d_o_51_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_trn_N_68426_i_2489), + .Q(com_tlm_u_tlm_tx_vc0_trn_d[51]) + ); + FD com_tlm_u_tlm_tx_vc0_trn_d_o_50_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_trn_N_68425_i_2490), + .Q(com_tlm_u_tlm_tx_vc0_trn_d[50]) + ); + FD com_tlm_u_tlm_tx_vc0_trn_d_o_49_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_trn_N_68424_i_2491), + .Q(com_tlm_u_tlm_tx_vc0_trn_d[49]) + ); + FD com_tlm_u_tlm_tx_vc0_trn_d_o_48_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_trn_N_68423_i_2492), + .Q(com_tlm_u_tlm_tx_vc0_trn_d[48]) + ); + FD com_tlm_u_tlm_tx_vc0_trn_d_o_47_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_trn_N_68422_i_2493), + .Q(com_tlm_u_tlm_tx_vc0_trn_d[47]) + ); + FD com_tlm_u_tlm_tx_vc0_trn_d_o_63_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_trn_N_68767_i_2494), + .Q(com_tlm_u_tlm_tx_vc0_trn_d[63]) + ); + FD com_tlm_u_tlm_tx_vc0_trn_d_o_62_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_trn_N_32008_i), + .Q(com_tlm_u_tlm_tx_vc0_trn_d[62]) + ); + FD com_tlm_u_tlm_tx_vc0_trn_usr_d_5_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(trn_td_5057[5]), + .Q(com_tlm_u_tlm_tx_vc0_trn_usr_d[5]) + ); + FD com_tlm_u_tlm_tx_vc0_trn_usr_d_4_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(trn_td_5057[4]), + .Q(com_tlm_u_tlm_tx_vc0_trn_usr_d[4]) + ); + FD com_tlm_u_tlm_tx_vc0_trn_usr_d_3_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(trn_td_5057[3]), + .Q(com_tlm_u_tlm_tx_vc0_trn_usr_d[3]) + ); + FD com_tlm_u_tlm_tx_vc0_trn_usr_d_2_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(trn_td_5057[2]), + .Q(com_tlm_u_tlm_tx_vc0_trn_usr_d[2]) + ); + FD com_tlm_u_tlm_tx_vc0_trn_usr_d_1_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(trn_td_5057[1]), + .Q(com_tlm_u_tlm_tx_vc0_trn_usr_d[1]) + ); + FD com_tlm_u_tlm_tx_vc0_trn_usr_d_0_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(trn_td_5057[0]), + .Q(com_tlm_u_tlm_tx_vc0_trn_usr_d[0]) + ); + FD com_tlm_u_tlm_tx_vc0_trn_usr_d_20_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(trn_td_5057[20]), + .Q(com_tlm_u_tlm_tx_vc0_trn_usr_d[20]) + ); + FD com_tlm_u_tlm_tx_vc0_trn_usr_d_19_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(trn_td_5057[19]), + .Q(com_tlm_u_tlm_tx_vc0_trn_usr_d[19]) + ); + FD com_tlm_u_tlm_tx_vc0_trn_usr_d_18_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(trn_td_5057[18]), + .Q(com_tlm_u_tlm_tx_vc0_trn_usr_d[18]) + ); + FD com_tlm_u_tlm_tx_vc0_trn_usr_d_17_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(trn_td_5057[17]), + .Q(com_tlm_u_tlm_tx_vc0_trn_usr_d[17]) + ); + FD com_tlm_u_tlm_tx_vc0_trn_usr_d_16_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(trn_td_5057[16]), + .Q(com_tlm_u_tlm_tx_vc0_trn_usr_d[16]) + ); + FD com_tlm_u_tlm_tx_vc0_trn_usr_d_15_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(trn_td_5057[15]), + .Q(com_tlm_u_tlm_tx_vc0_trn_usr_d[15]) + ); + FD com_tlm_u_tlm_tx_vc0_trn_usr_d_14_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(trn_td_5057[14]), + .Q(com_tlm_u_tlm_tx_vc0_trn_usr_d[14]) + ); + FD com_tlm_u_tlm_tx_vc0_trn_usr_d_13_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(trn_td_5057[13]), + .Q(com_tlm_u_tlm_tx_vc0_trn_usr_d[13]) + ); + FD com_tlm_u_tlm_tx_vc0_trn_usr_d_12_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(trn_td_5057[12]), + .Q(com_tlm_u_tlm_tx_vc0_trn_usr_d[12]) + ); + FD com_tlm_u_tlm_tx_vc0_trn_usr_d_11_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(trn_td_5057[11]), + .Q(com_tlm_u_tlm_tx_vc0_trn_usr_d[11]) + ); + FD com_tlm_u_tlm_tx_vc0_trn_usr_d_10_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(trn_td_5057[10]), + .Q(com_tlm_u_tlm_tx_vc0_trn_usr_d[10]) + ); + FD com_tlm_u_tlm_tx_vc0_trn_usr_d_9_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(trn_td_5057[9]), + .Q(com_tlm_u_tlm_tx_vc0_trn_usr_d[9]) + ); + FD com_tlm_u_tlm_tx_vc0_trn_usr_d_8_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(trn_td_5057[8]), + .Q(com_tlm_u_tlm_tx_vc0_trn_usr_d[8]) + ); + FD com_tlm_u_tlm_tx_vc0_trn_usr_d_7_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(trn_td_5057[7]), + .Q(com_tlm_u_tlm_tx_vc0_trn_usr_d[7]) + ); + FD com_tlm_u_tlm_tx_vc0_trn_usr_d_6_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(trn_td_5057[6]), + .Q(com_tlm_u_tlm_tx_vc0_trn_usr_d[6]) + ); + FD com_tlm_u_tlm_tx_vc0_trn_usr_d_35_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(trn_td_5057[35]), + .Q(com_tlm_u_tlm_tx_vc0_trn_usr_d[35]) + ); + FD com_tlm_u_tlm_tx_vc0_trn_usr_d_34_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(trn_td_5057[34]), + .Q(com_tlm_u_tlm_tx_vc0_trn_usr_d[34]) + ); + FD com_tlm_u_tlm_tx_vc0_trn_usr_d_33_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(trn_td_5057[33]), + .Q(com_tlm_u_tlm_tx_vc0_trn_usr_d[33]) + ); + FD com_tlm_u_tlm_tx_vc0_trn_usr_d_32_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(trn_td_5057[32]), + .Q(com_tlm_u_tlm_tx_vc0_trn_usr_d[32]) + ); + FD com_tlm_u_tlm_tx_vc0_trn_usr_d_31_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(trn_td_5057[31]), + .Q(com_tlm_u_tlm_tx_vc0_trn_usr_d[31]) + ); + FD com_tlm_u_tlm_tx_vc0_trn_usr_d_30_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(trn_td_5057[30]), + .Q(com_tlm_u_tlm_tx_vc0_trn_usr_d[30]) + ); + FD com_tlm_u_tlm_tx_vc0_trn_usr_d_29_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(trn_td_5057[29]), + .Q(com_tlm_u_tlm_tx_vc0_trn_usr_d[29]) + ); + FD com_tlm_u_tlm_tx_vc0_trn_usr_d_28_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(trn_td_5057[28]), + .Q(com_tlm_u_tlm_tx_vc0_trn_usr_d[28]) + ); + FD com_tlm_u_tlm_tx_vc0_trn_usr_d_27_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(trn_td_5057[27]), + .Q(com_tlm_u_tlm_tx_vc0_trn_usr_d[27]) + ); + FD com_tlm_u_tlm_tx_vc0_trn_usr_d_26_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(trn_td_5057[26]), + .Q(com_tlm_u_tlm_tx_vc0_trn_usr_d[26]) + ); + FD com_tlm_u_tlm_tx_vc0_trn_usr_d_25_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(trn_td_5057[25]), + .Q(com_tlm_u_tlm_tx_vc0_trn_usr_d[25]) + ); + FD com_tlm_u_tlm_tx_vc0_trn_usr_d_24_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(trn_td_5057[24]), + .Q(com_tlm_u_tlm_tx_vc0_trn_usr_d[24]) + ); + FD com_tlm_u_tlm_tx_vc0_trn_usr_d_23_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(trn_td_5057[23]), + .Q(com_tlm_u_tlm_tx_vc0_trn_usr_d[23]) + ); + FD com_tlm_u_tlm_tx_vc0_trn_usr_d_22_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(trn_td_5057[22]), + .Q(com_tlm_u_tlm_tx_vc0_trn_usr_d[22]) + ); + FD com_tlm_u_tlm_tx_vc0_trn_usr_d_21_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(trn_td_5057[21]), + .Q(com_tlm_u_tlm_tx_vc0_trn_usr_d[21]) + ); + FD com_tlm_u_tlm_tx_vc0_trn_usr_d_50_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(trn_td_5057[50]), + .Q(com_tlm_u_tlm_tx_vc0_trn_usr_d[50]) + ); + FD com_tlm_u_tlm_tx_vc0_trn_usr_d_49_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(trn_td_5057[49]), + .Q(com_tlm_u_tlm_tx_vc0_trn_usr_d[49]) + ); + FD com_tlm_u_tlm_tx_vc0_trn_usr_d_48_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(trn_td_5057[48]), + .Q(com_tlm_u_tlm_tx_vc0_trn_usr_d[48]) + ); + FD com_tlm_u_tlm_tx_vc0_trn_usr_d_47_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(trn_td_5057[47]), + .Q(com_tlm_u_tlm_tx_vc0_trn_usr_d[47]) + ); + FD com_tlm_u_tlm_tx_vc0_trn_usr_d_46_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(trn_td_5057[46]), + .Q(com_tlm_u_tlm_tx_vc0_trn_usr_d[46]) + ); + FD com_tlm_u_tlm_tx_vc0_trn_usr_d_45_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(trn_td_5057[45]), + .Q(com_tlm_u_tlm_tx_vc0_trn_usr_d[45]) + ); + FD com_tlm_u_tlm_tx_vc0_trn_usr_d_44_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(trn_td_5057[44]), + .Q(com_tlm_u_tlm_tx_vc0_trn_usr_d[44]) + ); + FD com_tlm_u_tlm_tx_vc0_trn_usr_d_43_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(trn_td_5057[43]), + .Q(com_tlm_u_tlm_tx_vc0_trn_usr_d[43]) + ); + FD com_tlm_u_tlm_tx_vc0_trn_usr_d_42_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(trn_td_5057[42]), + .Q(com_tlm_u_tlm_tx_vc0_trn_usr_d[42]) + ); + FD com_tlm_u_tlm_tx_vc0_trn_usr_d_41_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(trn_td_5057[41]), + .Q(com_tlm_u_tlm_tx_vc0_trn_usr_d[41]) + ); + FD com_tlm_u_tlm_tx_vc0_trn_usr_d_40_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(trn_td_5057[40]), + .Q(com_tlm_u_tlm_tx_vc0_trn_usr_d[40]) + ); + FD com_tlm_u_tlm_tx_vc0_trn_usr_d_39_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(trn_td_5057[39]), + .Q(com_tlm_u_tlm_tx_vc0_trn_usr_d[39]) + ); + FD com_tlm_u_tlm_tx_vc0_trn_usr_d_38_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(trn_td_5057[38]), + .Q(com_tlm_u_tlm_tx_vc0_trn_usr_d[38]) + ); + FD com_tlm_u_tlm_tx_vc0_trn_usr_d_37_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(trn_td_5057[37]), + .Q(com_tlm_u_tlm_tx_vc0_trn_usr_d[37]) + ); + FD com_tlm_u_tlm_tx_vc0_trn_usr_d_36_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(trn_td_5057[36]), + .Q(com_tlm_u_tlm_tx_vc0_trn_usr_d[36]) + ); + FD com_tlm_u_tlm_tx_vc0_trn_usr_d_63_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(trn_td_5057[63]), + .Q(com_tlm_u_tlm_tx_vc0_trn_usr_d[63]) + ); + FD com_tlm_u_tlm_tx_vc0_trn_usr_d_62_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(trn_td_5057[62]), + .Q(com_tlm_u_tlm_tx_vc0_trn_usr_d[62]) + ); + FD com_tlm_u_tlm_tx_vc0_trn_usr_d_61_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(trn_td_5057[61]), + .Q(com_tlm_u_tlm_tx_vc0_trn_usr_d[61]) + ); + FD com_tlm_u_tlm_tx_vc0_trn_usr_d_60_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(trn_td_5057[60]), + .Q(com_tlm_u_tlm_tx_vc0_trn_usr_d[60]) + ); + FD com_tlm_u_tlm_tx_vc0_trn_usr_d_59_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(trn_td_5057[59]), + .Q(com_tlm_u_tlm_tx_vc0_trn_usr_d[59]) + ); + FD com_tlm_u_tlm_tx_vc0_trn_usr_d_58_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(trn_td_5057[58]), + .Q(com_tlm_u_tlm_tx_vc0_trn_usr_d[58]) + ); + FD com_tlm_u_tlm_tx_vc0_trn_usr_d_57_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(trn_td_5057[57]), + .Q(com_tlm_u_tlm_tx_vc0_trn_usr_d[57]) + ); + FD com_tlm_u_tlm_tx_vc0_trn_usr_d_56_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(trn_td_5057[56]), + .Q(com_tlm_u_tlm_tx_vc0_trn_usr_d[56]) + ); + FD com_tlm_u_tlm_tx_vc0_trn_usr_d_55_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(trn_td_5057[55]), + .Q(com_tlm_u_tlm_tx_vc0_trn_usr_d[55]) + ); + FD com_tlm_u_tlm_tx_vc0_trn_usr_d_54_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(trn_td_5057[54]), + .Q(com_tlm_u_tlm_tx_vc0_trn_usr_d[54]) + ); + FD com_tlm_u_tlm_tx_vc0_trn_usr_d_53_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(trn_td_5057[53]), + .Q(com_tlm_u_tlm_tx_vc0_trn_usr_d[53]) + ); + FD com_tlm_u_tlm_tx_vc0_trn_usr_d_52_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(trn_td_5057[52]), + .Q(com_tlm_u_tlm_tx_vc0_trn_usr_d[52]) + ); + FD com_tlm_u_tlm_tx_vc0_trn_usr_d_51_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(trn_td_5057[51]), + .Q(com_tlm_u_tlm_tx_vc0_trn_usr_d[51]) + ); + FDE com_tlm_u_tlm_tx_vc0_trn_load_value_6_ ( + .CE(com_tlm_u_tlm_tx_vc0_trn_N_48897_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_trn_load_value10), + .Q(com_tlm_u_tlm_tx_vc0_trn_load_value_6__2501) + ); + FDE com_tlm_u_tlm_tx_vc0_trn_load_value_0_ ( + .CE(com_tlm_u_tlm_tx_vc0_trn_N_48897_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_trn_load_value10_i), + .Q(com_tlm_u_tlm_tx_vc0_trn_load_value_0__2502) + ); + INV com_tlm_u_tlm_tx_vc0_trn_usr_abort_i ( + .I(com_tlm_u_tlm_tx_vc0_trn_usr_abort_2496), + .O(com_tlm_u_tlm_tx_vc0_trn_usr_abort_i_2495) + ); + INV com_tlm_u_tlm_tx_vc0_trn_trn_tdst_dsc_i ( + .I(com_tlm_u_tlm_tx_vc0_trn_trn_tdst_dsc), + .O(trn_tdst_dsc_n) + ); + INV com_tlm_u_tlm_tx_vc0_trn_trn_tdst_rdy_i ( + .I(com_tlm_u_tlm_tx_vc0_trn_trn_tdst_rdy), + .O(trn_tdst_rdy_n) + ); + SRL16 com_tlm_u_tlm_tx_vc0_trn_usr_eof_filt_q_I_1 ( + .D(com_tlm_u_tlm_tx_vc0_trn_usr_eof_filt_q_1__2497), + .Q(com_tlm_u_tlm_tx_vc0_trn_usr_eof_filt_q_N_6), + .CLK(NlwRenamedSig_OI_trn_clk), + .A0(com_tlm_u_tlm_tx_vc0_trn_VCC_2500), + .A1(com_tlm_u_tlm_tx_vc0_trn_GND_2498), + .A2(com_tlm_u_tlm_tx_vc0_trn_GND_2498), + .A3(com_tlm_u_tlm_tx_vc0_trn_GND_2498) + ); + MULT_AND com_tlm_u_tlm_tx_vc0_trn_un1_trn_tbuf_av_o_1_cry_0_ma ( + .I0(NlwRenamedSig_OI_trn_tbuf_av[0]), + .I1(com_tlm_u_tlm_tx_vc0_trn_VCC_2500), + .LO(com_tlm_u_tlm_tx_vc0_trn_un1_trn_tbuf_av_o_1_cry_0_ma_2499) + ); + defparam com_tlm_u_tlm_tx_vc0_trn_len_counter_qxu_0_6_.INIT = 8'h1D; + LUT3_L com_tlm_u_tlm_tx_vc0_trn_len_counter_qxu_0_6_ ( + .I0(com_tlm_u_tlm_tx_vc0_trn_len_counter[6]), + .I1(com_tlm_u_tlm_tx_vc0_trn_load_counter_2503), + .I2(com_tlm_u_tlm_tx_vc0_trn_load_value_6__2501), + .LO(com_tlm_u_tlm_tx_vc0_trn_len_counter_qxu[6]) + ); + defparam com_tlm_u_tlm_tx_vc0_trn_len_counter_qxu_0_5_.INIT = 8'h1D; + LUT3_L com_tlm_u_tlm_tx_vc0_trn_len_counter_qxu_0_5_ ( + .I0(com_tlm_u_tlm_tx_vc0_trn_len_counter[5]), + .I1(com_tlm_u_tlm_tx_vc0_trn_load_counter_2503), + .I2(com_tlm_u_tlm_tx_vc0_trn_load_value_0__2502), + .LO(com_tlm_u_tlm_tx_vc0_trn_len_counter_qxu[5]) + ); + defparam com_tlm_u_tlm_tx_vc0_trn_len_counter_qxu_0_4_.INIT = 8'h1D; + LUT3_L com_tlm_u_tlm_tx_vc0_trn_len_counter_qxu_0_4_ ( + .I0(com_tlm_u_tlm_tx_vc0_trn_len_counter[4]), + .I1(com_tlm_u_tlm_tx_vc0_trn_load_counter_2503), + .I2(com_tlm_u_tlm_tx_vc0_trn_load_value_0__2502), + .LO(com_tlm_u_tlm_tx_vc0_trn_len_counter_qxu[4]) + ); + defparam com_tlm_u_tlm_tx_vc0_trn_len_counter_qxu_0_3_.INIT = 8'h1D; + LUT3_L com_tlm_u_tlm_tx_vc0_trn_len_counter_qxu_0_3_ ( + .I0(com_tlm_u_tlm_tx_vc0_trn_len_counter[3]), + .I1(com_tlm_u_tlm_tx_vc0_trn_load_counter_2503), + .I2(com_tlm_u_tlm_tx_vc0_trn_load_value_0__2502), + .LO(com_tlm_u_tlm_tx_vc0_trn_len_counter_qxu[3]) + ); + defparam com_tlm_u_tlm_tx_vc0_trn_len_counter_qxu_0_2_.INIT = 8'h1D; + LUT3_L com_tlm_u_tlm_tx_vc0_trn_len_counter_qxu_0_2_ ( + .I0(com_tlm_u_tlm_tx_vc0_trn_len_counter[2]), + .I1(com_tlm_u_tlm_tx_vc0_trn_load_counter_2503), + .I2(com_tlm_u_tlm_tx_vc0_trn_load_value_0__2502), + .LO(com_tlm_u_tlm_tx_vc0_trn_len_counter_qxu[2]) + ); + defparam com_tlm_u_tlm_tx_vc0_trn_len_counter_qxu_0_1_.INIT = 8'h1D; + LUT3_L com_tlm_u_tlm_tx_vc0_trn_len_counter_qxu_0_1_ ( + .I0(com_tlm_u_tlm_tx_vc0_trn_len_counter[1]), + .I1(com_tlm_u_tlm_tx_vc0_trn_load_counter_2503), + .I2(com_tlm_u_tlm_tx_vc0_trn_load_value_0__2502), + .LO(com_tlm_u_tlm_tx_vc0_trn_len_counter_qxu[1]) + ); + defparam com_tlm_u_tlm_tx_vc0_trn_len_counter_qxu_0_0_.INIT = 8'h1D; + LUT3_L com_tlm_u_tlm_tx_vc0_trn_len_counter_qxu_0_0_ ( + .I0(com_tlm_u_tlm_tx_vc0_trn_len_counter[0]), + .I1(com_tlm_u_tlm_tx_vc0_trn_load_counter_2503), + .I2(com_tlm_u_tlm_tx_vc0_trn_load_value_0__2502), + .LO(com_tlm_u_tlm_tx_vc0_trn_len_counter_qxu[0]) + ); + defparam com_tlm_u_tlm_tx_vc0_trn_un1_pkts_in_trn_1_axb0.INIT = 8'h6A; + LUT3_L com_tlm_u_tlm_tx_vc0_trn_un1_pkts_in_trn_1_axb0 ( + .I0(com_tlm_u_tlm_tx_vc0_trn_pkts_in_trn[0]), + .I1(plm_link_up_1), + .I2(com_tlm_u_tlm_tx_vc0_trn_pkts_in_trn28_i_0_0_0_0_32184_2505), + .LO(com_tlm_u_tlm_tx_vc0_trn_un1_pkts_in_trn_1_axb0_2504) + ); + GND com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_GND ( + .G(com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_GND_2509) + ); + FDRE com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_sof_q ( + .CE(com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_N_68763_i_2517), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_N_68968_i_2532), + .Q(com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_sof_q_2533), + .R(plm_link_up_i) + ); + FDRE com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_usr_dsc_q ( + .CE(com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_N_68765_i_2516), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_N_48921_i_2525), + .Q(com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_usr_dsc_q_2514), + .R(plm_link_up_i) + ); + MUXCY_L com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_un1_usr_d_i_3_cry_0 ( + .CI(com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_usr_credits14_i_2513), + .DI(com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_GND_2509), + .LO(com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_un1_usr_d_i_3_cry_0_2506), + .S(com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_un1_usr_d_i_3_axb_0_2539) + ); + XORCY com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_un1_usr_d_i_3_s_0 ( + .CI(com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_usr_credits14_i_2513), + .LI(com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_un1_usr_d_i_3_axb_0_2539), + .O(com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_un1_usr_d_i_3_s_0_2524) + ); + MUXCY_L com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_un1_usr_d_i_3_cry_1 ( + .CI(com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_un1_usr_d_i_3_cry_0_2506), + .DI(com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_GND_2509), + .LO(com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_un1_usr_d_i_3_cry_1_2507), + .S(com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_un1_usr_d_i_3_axb_1_2538) + ); + XORCY com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_un1_usr_d_i_3_s_1 ( + .CI(com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_un1_usr_d_i_3_cry_0_2506), + .LI(com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_un1_usr_d_i_3_axb_1_2538), + .O(com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_un1_usr_d_i_3_s_1_2523) + ); + MUXCY_L com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_un1_usr_d_i_3_cry_2 ( + .CI(com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_un1_usr_d_i_3_cry_1_2507), + .DI(com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_GND_2509), + .LO(com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_un1_usr_d_i_3_cry_2_2508), + .S(com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_un1_usr_d_i_3_axb_2_2537) + ); + XORCY com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_un1_usr_d_i_3_s_2 ( + .CI(com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_un1_usr_d_i_3_cry_1_2507), + .LI(com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_un1_usr_d_i_3_axb_2_2537), + .O(com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_un1_usr_d_i_3_s_2_2522) + ); + MUXCY_L com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_un1_usr_d_i_3_cry_3 ( + .CI(com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_un1_usr_d_i_3_cry_2_2508), + .DI(com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_GND_2509), + .LO(com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_un1_usr_d_i_3_cry_3_2510), + .S(com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_un1_usr_d_i_3_axb_3_2536) + ); + XORCY com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_un1_usr_d_i_3_s_3 ( + .CI(com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_un1_usr_d_i_3_cry_2_2508), + .LI(com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_un1_usr_d_i_3_axb_3_2536), + .O(com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_un1_usr_d_i_3_s_3_2521) + ); + MUXCY_L com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_un1_usr_d_i_3_cry_4 ( + .CI(com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_un1_usr_d_i_3_cry_3_2510), + .DI(com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_GND_2509), + .LO(com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_un1_usr_d_i_3_cry_4_2511), + .S(com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_un1_usr_d_i_3_axb_4_2535) + ); + XORCY com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_un1_usr_d_i_3_s_4 ( + .CI(com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_un1_usr_d_i_3_cry_3_2510), + .LI(com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_un1_usr_d_i_3_axb_4_2535), + .O(com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_un1_usr_d_i_3_s_4_2520) + ); + XORCY com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_un1_usr_d_i_3_s_5 ( + .CI(com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_un1_usr_d_i_3_cry_4_2511), + .LI(com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_un1_usr_d_i_3_axb_5_2512), + .O(com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_un1_usr_d_i_3_s_5_2519) + ); + defparam com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_un1_usr_d_i_3_axb_5.INIT = 4'h2; + LUT1 com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_un1_usr_d_i_3_axb_5 ( + .I0(com_tlm_u_tlm_tx_vc0_trn_usr_d[39]), + .O(com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_un1_usr_d_i_3_axb_5_2512) + ); + defparam com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_usr_cat20_0_a2_0_a2_0_a2_1_0_.INIT = 4'h1; + LUT2_L com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_usr_cat20_0_a2_0_a2_0_a2_1_0_ ( + .I0(com_tlm_u_tlm_tx_vc0_trn_usr_d[58]), + .I1(com_tlm_u_tlm_tx_vc0_trn_usr_d[61]), + .LO(com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_usr_cat20_0_a2_0_a2_0_a2_1[0]) + ); + defparam com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_un1_usr_sof_i_1_i_0_0_m2_0.INIT = 8'hB8; + LUT3 com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_un1_usr_sof_i_1_i_0_0_m2_0 ( + .I0(com_tlm_u_tlm_tx_vc0_trn_usr_eof_2443), + .I1(com_tlm_u_tlm_tx_vc0_trn_usr_frame_2451), + .I2(com_tlm_u_tlm_tx_vc0_trn_usr_sof_2424), + .O(com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_un1_usr_sof_i_1_i_0_0_m2_0_2526) + ); + defparam com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_usr_credits14_i.INIT = 4'hE; + LUT2 com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_usr_credits14_i ( + .I0(com_tlm_u_tlm_tx_vc0_trn_usr_d[32]), + .I1(com_tlm_u_tlm_tx_vc0_trn_usr_d[33]), + .O(com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_usr_credits14_i_2513) + ); + defparam com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_usr_cat19_0_0_0_1.INIT = 16'h0103; + LUT4_L com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_usr_cat19_0_0_0_1 ( + .I0(com_tlm_u_tlm_tx_vc0_trn_usr_d[58]), + .I1(com_tlm_u_tlm_tx_vc0_trn_usr_d[59]), + .I2(com_tlm_u_tlm_tx_vc0_trn_usr_d[60]), + .I3(com_tlm_u_tlm_tx_vc0_trn_usr_d[61]), + .LO(com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_usr_cat19_0_0_0_1_2515) + ); + defparam com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_frame_vld_o14_0_i_i_a2_1.INIT = 8'h02; + LUT3 com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_frame_vld_o14_0_i_i_a2_1 ( + .I0(com_tlm_u_tlm_tx_vc0_trn_N_49601), + .I1(com_tlm_u_tlm_tx_vc0_trn_usr_dsc_2430), + .I2(com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_usr_dsc_q_2514), + .O(com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_frame_vld_o14_0_i_i_a2_1_2518) + ); + defparam com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_usr_cat19_0_0_0_3.INIT = 16'h3700; + LUT4_L com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_usr_cat19_0_0_0_3 ( + .I0(com_tlm_u_tlm_tx_vc0_trn_usr_d[56]), + .I1(com_tlm_u_tlm_tx_vc0_trn_usr_d[57]), + .I2(com_tlm_u_tlm_tx_vc0_trn_usr_d[61]), + .I3(com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_usr_cat19_0_0_0_1_2515), + .LO(com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_usr_cat19_0_0_0_3_2527) + ); + defparam com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_N_68765_i.INIT = 4'hE; + LUT2 com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_N_68765_i ( + .I0(com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_un1_usr_sof_i_1_i_0_0_m2_0_2526), + .I1(com_tlm_u_tlm_tx_vc0_trn_usr_dsc_2430), + .O(com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_N_68765_i_2516) + ); + defparam com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_N_68763_i.INIT = 4'hE; + LUT2 com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_N_68763_i ( + .I0(com_tlm_u_tlm_tx_vc0_trn_vld_o_5_i_i_a2_i_a3_2455), + .I1(com_tlm_u_tlm_tx_vc0_trn_usr_vld_2450), + .O(com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_N_68763_i_2517) + ); + defparam com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_N_68968_i.INIT = 8'hEA; + LUT3 com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_N_68968_i ( + .I0(com_tlm_u_tlm_tx_vc0_trn_cfg_start), + .I1(com_tlm_u_tlm_tx_vc0_trn_usr_sof_filt), + .I2(com_tlm_u_tlm_tx_vc0_trn_usr_vld_2450), + .O(com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_N_68968_i_2532) + ); + defparam com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_N_68764_i.INIT = 16'hF400; + LUT4_L com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_N_68764_i ( + .I0(com_grant_reg_iv_0_0_0_a2), + .I1(com_tlm_u_tlm_tx_vc0_trn_vld_o_5_i_i_a2_i_a3_2455), + .I2(com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_frame_vld_o14_0_i_i_a2_1_2518), + .I3(plm_link_up_1), + .LO(com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_N_68764_i_2528) + ); + defparam com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_usr_credits_6_1_a2_0_a2_0_a2_5_.INIT = 4'h8; + LUT2_L com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_usr_credits_6_1_a2_0_a2_0_a2_5_ ( + .I0(com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_un1_usr_d_i_3_s_5_2519), + .I1(com_tlm_u_tlm_tx_vc0_trn_usr_d[62]), + .LO(com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_usr_credits_6[5]) + ); + defparam com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_usr_credits_6_1_a2_0_a2_0_a2_4_.INIT = 4'h8; + LUT2_L com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_usr_credits_6_1_a2_0_a2_0_a2_4_ ( + .I0(com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_un1_usr_d_i_3_s_4_2520), + .I1(com_tlm_u_tlm_tx_vc0_trn_usr_d[62]), + .LO(com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_usr_credits_6[4]) + ); + defparam com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_usr_credits_6_1_a2_0_a2_0_a2_3_.INIT = 4'h8; + LUT2_L com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_usr_credits_6_1_a2_0_a2_0_a2_3_ ( + .I0(com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_un1_usr_d_i_3_s_3_2521), + .I1(com_tlm_u_tlm_tx_vc0_trn_usr_d[62]), + .LO(com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_usr_credits_6[3]) + ); + defparam com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_usr_credits_6_1_a2_0_a2_0_a2_2_.INIT = 4'h8; + LUT2_L com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_usr_credits_6_1_a2_0_a2_0_a2_2_ ( + .I0(com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_un1_usr_d_i_3_s_2_2522), + .I1(com_tlm_u_tlm_tx_vc0_trn_usr_d[62]), + .LO(com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_usr_credits_6[2]) + ); + defparam com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_usr_credits_6_1_a2_0_a2_0_a2_1_.INIT = 4'h8; + LUT2_L com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_usr_credits_6_1_a2_0_a2_0_a2_1_ ( + .I0(com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_un1_usr_d_i_3_s_1_2523), + .I1(com_tlm_u_tlm_tx_vc0_trn_usr_d[62]), + .LO(com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_usr_credits_6[1]) + ); + defparam com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_usr_credits_6_1_a2_0_a2_0_a2_0_.INIT = 4'h8; + LUT2_L com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_usr_credits_6_1_a2_0_a2_0_a2_0_ ( + .I0(com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_un1_usr_d_i_3_s_0_2524), + .I1(com_tlm_u_tlm_tx_vc0_trn_usr_d[62]), + .LO(com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_usr_credits_6[0]) + ); + defparam com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_cat_o_2_0_1_.INIT = 8'hAC; + LUT3_L com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_cat_o_2_0_1_ ( + .I0(com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_cfg_cat[1]), + .I1(com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_usr_cat[1]), + .I2(com_tlm_u_tlm_tx_vc0_trn_cfg), + .LO(com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_cat_o_2[1]) + ); + defparam com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_cat_o_2_0_.INIT = 4'h2; + LUT2_L com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_cat_o_2_0_ ( + .I0(com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_usr_cat[0]), + .I1(com_tlm_u_tlm_tx_vc0_trn_cfg), + .LO(com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_cat_o_2[0]) + ); + defparam com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_N_48921_i.INIT = 4'h1; + LUT1_L com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_N_48921_i ( + .I0(com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_un1_usr_sof_i_1_i_0_0_m2_0_2526), + .LO(com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_N_48921_i_2525) + ); + defparam com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_credits_o_2_0_a4_0_a2_0_a2_0_a2_5_.INIT = 4'h8; + LUT2_L com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_credits_o_2_0_a4_0_a2_0_a2_0_a2_5_ ( + .I0(com_tlm_u_tlm_tx_vc0_trn_usr_vld_2450), + .I1(com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_usr_credits[5]), + .LO(com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_credits_o_2[5]) + ); + defparam com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_credits_o_2_0_a4_0_a2_0_a2_0_a2_4_.INIT = 4'h8; + LUT2_L com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_credits_o_2_0_a4_0_a2_0_a2_0_a2_4_ ( + .I0(com_tlm_u_tlm_tx_vc0_trn_usr_vld_2450), + .I1(com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_usr_credits[4]), + .LO(com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_credits_o_2[4]) + ); + defparam com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_credits_o_2_0_a4_0_a2_0_a2_0_a2_3_.INIT = 4'h8; + LUT2_L com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_credits_o_2_0_a4_0_a2_0_a2_0_a2_3_ ( + .I0(com_tlm_u_tlm_tx_vc0_trn_usr_vld_2450), + .I1(com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_usr_credits[3]), + .LO(com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_credits_o_2[3]) + ); + defparam com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_credits_o_2_0_a4_0_a2_0_a2_0_a2_2_.INIT = 4'h8; + LUT2_L com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_credits_o_2_0_a4_0_a2_0_a2_0_a2_2_ ( + .I0(com_tlm_u_tlm_tx_vc0_trn_usr_vld_2450), + .I1(com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_usr_credits[2]), + .LO(com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_credits_o_2[2]) + ); + defparam com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_credits_o_2_0_a4_0_a2_0_a2_0_a2_1_.INIT = 4'h8; + LUT2_L com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_credits_o_2_0_a4_0_a2_0_a2_0_a2_1_ ( + .I0(com_tlm_u_tlm_tx_vc0_trn_usr_vld_2450), + .I1(com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_usr_credits[1]), + .LO(com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_credits_o_2[1]) + ); + defparam com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_credits_o_2_i_m2_i_m3_i_m2_i_m3_0_0_.INIT = 8'hE4; + LUT3_L com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_credits_o_2_i_m2_i_m3_i_m2_i_m3_0_0_ ( + .I0(com_tlm_u_tlm_tx_vc0_trn_usr_vld_2450), + .I1(com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_cfg_credits_2529), + .I2(com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_usr_credits[0]), + .LO(com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_credits_o_2_i_m2_i_m3_i_m2_i_m3_0[0]) + ); + defparam com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_no_payload_o_2_i_m2_i_m3_i_m2_i_m3_0.INIT = 8'hE4; + LUT3_L com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_no_payload_o_2_i_m2_i_m3_i_m2_i_m3_0 ( + .I0(com_tlm_u_tlm_tx_vc0_trn_usr_vld_2450), + .I1(com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_cfg_no_payload_2531), + .I2(com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_usr_no_payload_2530), + .LO(com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_no_payload_o_2_i_m2_i_m3_i_m2_i_m3_0_2534) + ); + defparam com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_usr_cat20_0_a2_0_a2_0_a2_0_.INIT = 16'h0800; + LUT4_L com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_usr_cat20_0_a2_0_a2_0_a2_0_ ( + .I0(com_tlm_u_tlm_tx_vc0_trn_usr_d[57]), + .I1(com_tlm_u_tlm_tx_vc0_trn_usr_d[59]), + .I2(com_tlm_u_tlm_tx_vc0_trn_usr_d[60]), + .I3(com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_usr_cat20_0_a2_0_a2_0_a2_1[0]), + .LO(com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_usr_cat20[0]) + ); + defparam com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_usr_cat19_0_0_0.INIT = 16'h6700; + LUT4_L com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_usr_cat19_0_0_0 ( + .I0(com_tlm_u_tlm_tx_vc0_trn_usr_d[57]), + .I1(com_tlm_u_tlm_tx_vc0_trn_usr_d[58]), + .I2(com_tlm_u_tlm_tx_vc0_trn_usr_d[62]), + .I3(com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_usr_cat19_0_0_0_3_2527), + .LO(com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_N_9677_i) + ); + FD com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_frame_vld_o_1 ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_N_68764_i_2528), + .Q(com_tlm_u_tlm_tx_vc0_frame_vld) + ); + FDE com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_usr_credits_5_ ( + .CE(com_tlm_u_tlm_tx_vc0_trn_usr_sof_filt), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_usr_credits_6[5]), + .Q(com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_usr_credits[5]) + ); + FDE com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_usr_credits_4_ ( + .CE(com_tlm_u_tlm_tx_vc0_trn_usr_sof_filt), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_usr_credits_6[4]), + .Q(com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_usr_credits[4]) + ); + FDE com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_usr_credits_3_ ( + .CE(com_tlm_u_tlm_tx_vc0_trn_usr_sof_filt), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_usr_credits_6[3]), + .Q(com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_usr_credits[3]) + ); + FDE com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_usr_credits_2_ ( + .CE(com_tlm_u_tlm_tx_vc0_trn_usr_sof_filt), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_usr_credits_6[2]), + .Q(com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_usr_credits[2]) + ); + FDE com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_usr_credits_1_ ( + .CE(com_tlm_u_tlm_tx_vc0_trn_usr_sof_filt), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_usr_credits_6[1]), + .Q(com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_usr_credits[1]) + ); + FDE com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_usr_credits_0_ ( + .CE(com_tlm_u_tlm_tx_vc0_trn_usr_sof_filt), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_usr_credits_6[0]), + .Q(com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_usr_credits[0]) + ); + FD com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_cat_o_1_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_cat_o_2[1]), + .Q(com_tlm_u_tlm_tx_vc0_cat[1]) + ); + FD com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_cat_o_0_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_cat_o_2[0]), + .Q(com_tlm_u_tlm_tx_vc0_cat[0]) + ); + FDE com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_cfg_credits ( + .CE(com_cmmt_trem_n_0_sqmuxa), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_N_39480_i), + .Q(com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_cfg_credits_2529) + ); + FDE com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_usr_no_payload ( + .CE(com_tlm_u_tlm_tx_vc0_trn_usr_sof_filt), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_trn_usr_d_i[62]), + .Q(com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_usr_no_payload_2530) + ); + FDE com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_cfg_no_payload ( + .CE(com_cmmt_trem_n_0_sqmuxa), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_N_39480_i_i), + .Q(com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_cfg_no_payload_2531) + ); + FDE com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_cfg_cat_1_ ( + .CE(com_cmmt_trem_n_0_sqmuxa), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_N_68483_i), + .Q(com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_cfg_cat[1]) + ); + FDE com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_cfg_o ( + .CE(com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_N_68968_i_2532), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_trn_cfg_start), + .Q(com_tlm_u_tlm_tx_vc0_trn_cfg) + ); + FDE com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_credits_o_5_ ( + .CE(com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_sof_q_2533), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_credits_o_2[5]), + .Q(com_tlm_u_tlm_tx_vc0_credits[5]) + ); + FDE com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_credits_o_4_ ( + .CE(com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_sof_q_2533), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_credits_o_2[4]), + .Q(com_tlm_u_tlm_tx_vc0_credits[4]) + ); + FDE com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_credits_o_3_ ( + .CE(com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_sof_q_2533), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_credits_o_2[3]), + .Q(com_tlm_u_tlm_tx_vc0_credits[3]) + ); + FDE com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_credits_o_2_ ( + .CE(com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_sof_q_2533), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_credits_o_2[2]), + .Q(com_tlm_u_tlm_tx_vc0_credits[2]) + ); + FDE com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_credits_o_1_ ( + .CE(com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_sof_q_2533), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_credits_o_2[1]), + .Q(com_tlm_u_tlm_tx_vc0_credits[1]) + ); + FDE com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_credits_o_0_ ( + .CE(com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_sof_q_2533), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_credits_o_2_i_m2_i_m3_i_m2_i_m3_0[0]), + .Q(com_tlm_u_tlm_tx_vc0_credits[0]) + ); + FDE com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_no_payload_o ( + .CE(com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_sof_q_2533), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_no_payload_o_2_i_m2_i_m3_i_m2_i_m3_0_2534), + .Q(com_tlm_u_tlm_tx_vc0_no_payload) + ); + FDE com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_usr_cat_1_ ( + .CE(com_tlm_u_tlm_tx_vc0_trn_usr_sof_filt), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_usr_cat20[0]), + .Q(com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_usr_cat[1]) + ); + FDE com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_usr_cat_0_ ( + .CE(com_tlm_u_tlm_tx_vc0_trn_usr_sof_filt), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_N_9677_i), + .Q(com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_usr_cat[0]) + ); + defparam com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_un1_usr_d_i_3_axb_4.INIT = 4'h2; + LUT1 com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_un1_usr_d_i_3_axb_4 ( + .I0(com_tlm_u_tlm_tx_vc0_trn_usr_d[38]), + .O(com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_un1_usr_d_i_3_axb_4_2535) + ); + defparam com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_un1_usr_d_i_3_axb_3.INIT = 4'h2; + LUT1 com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_un1_usr_d_i_3_axb_3 ( + .I0(com_tlm_u_tlm_tx_vc0_trn_usr_d[37]), + .O(com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_un1_usr_d_i_3_axb_3_2536) + ); + defparam com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_un1_usr_d_i_3_axb_2.INIT = 4'h2; + LUT1 com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_un1_usr_d_i_3_axb_2 ( + .I0(com_tlm_u_tlm_tx_vc0_trn_usr_d[36]), + .O(com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_un1_usr_d_i_3_axb_2_2537) + ); + defparam com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_un1_usr_d_i_3_axb_1.INIT = 4'h2; + LUT1 com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_un1_usr_d_i_3_axb_1 ( + .I0(com_tlm_u_tlm_tx_vc0_trn_usr_d[35]), + .O(com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_un1_usr_d_i_3_axb_1_2538) + ); + defparam com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_un1_usr_d_i_3_axb_0.INIT = 4'h2; + LUT1 com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_un1_usr_d_i_3_axb_0 ( + .I0(com_tlm_u_tlm_tx_vc0_trn_usr_d[34]), + .O(com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_un1_usr_d_i_3_axb_0_2539) + ); + VCC com_tlm_u_tlm_tx_vc0_token_fifo_VCC ( + .P(com_tlm_u_tlm_tx_vc0_token_fifo_VCC_2540) + ); + FDR com_tlm_u_tlm_tx_vc0_token_fifo_token_index_0_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_token_fifo_un1_token_index_axbxc0_2549), + .Q(com_tlm_u_tlm_tx_vc0_token_fifo_token_index[0]), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_tx_vc0_token_fifo_token_index_1_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_token_fifo_un1_token_index_axbxc1_2548), + .Q(com_tlm_u_tlm_tx_vc0_token_fifo_token_index[1]), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_tx_vc0_token_fifo_token_index_2_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_token_fifo_un1_token_index_axbxc2_2547), + .Q(com_tlm_u_tlm_tx_vc0_token_fifo_token_index[2]), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_tx_vc0_token_fifo_token_index_3_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_token_fifo_un1_token_index_axbxc3_2545), + .Q(com_tlm_u_tlm_tx_vc0_token_fifo_token_index[3]), + .R(plm_link_up_i) + ); + FDRE com_tlm_u_tlm_tx_vc0_token_fifo_tokens_loaded ( + .CE(com_tlm_u_tlm_tx_vc0_token_fifo_tokens_loaded_0_sqmuxa), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_token_fifo_VCC_2540), + .Q(com_tlm_u_tlm_tx_vc0_token_fifo_tokens_loaded_2550), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_tx_vc0_token_fifo_fifo_wen ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_token_fifo_N_69041_i_2544), + .Q(com_tlm_u_tlm_tx_vc0_released_buf), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_tx_vc0_token_fifo_fifo_d_0_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_token_fifo_fifo_d_6_i_m2_i_m2_0_0__2543), + .Q(com_tlm_u_tlm_tx_vc0_token_fifo_fifo_d[0]), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_tx_vc0_token_fifo_fifo_d_1_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_token_fifo_N_69042_i_2542), + .Q(com_tlm_u_tlm_tx_vc0_token_fifo_fifo_d[1]), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_tx_vc0_token_fifo_fifo_d_2_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_token_fifo_fifo_d_6_i_m2_i_m2_0_2__2541), + .Q(com_tlm_u_tlm_tx_vc0_token_fifo_fifo_d[2]), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_tx_vc0_token_fifo_fifo_d_3_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_token_fifo_fifo_d_6_i_o2_i_m2_0[3]), + .Q(com_tlm_u_tlm_tx_vc0_token_fifo_fifo_d[3]), + .R(plm_link_up_i) + ); + defparam com_tlm_u_tlm_tx_vc0_token_fifo_un1_token_index_p4.INIT = 16'h0080; + LUT4_L com_tlm_u_tlm_tx_vc0_token_fifo_un1_token_index_p4 ( + .I0(com_tlm_u_tlm_tx_vc0_token_fifo_token_index[0]), + .I1(com_tlm_u_tlm_tx_vc0_token_fifo_token_index[1]), + .I2(com_tlm_u_tlm_tx_vc0_token_fifo_token_index[2]), + .I3(com_tlm_u_tlm_tx_vc0_token_fifo_tokens_loaded_2550), + .LO(com_tlm_u_tlm_tx_vc0_token_fifo_un1_token_index_p4_2546) + ); + defparam com_tlm_u_tlm_tx_vc0_token_fifo_tokens_loaded_0_sqmuxa_0_a3_3_a4.INIT = 4'h2; + LUT2 com_tlm_u_tlm_tx_vc0_token_fifo_tokens_loaded_0_sqmuxa_0_a3_3_a4 ( + .I0(com_tlm_u_tlm_tx_vc0_token_fifo_token_index[1]), + .I1(com_tlm_u_tlm_tx_vc0_token_fifo_tokens_loaded_2550), + .O(com_tlm_u_tlm_tx_vc0_token_fifo_N_35026) + ); + defparam com_tlm_u_tlm_tx_vc0_token_fifo_tokens_loaded_0_sqmuxa_0_a3_3_a2.INIT = 16'h8000; + LUT4 com_tlm_u_tlm_tx_vc0_token_fifo_tokens_loaded_0_sqmuxa_0_a3_3_a2 ( + .I0(com_tlm_u_tlm_tx_vc0_token_fifo_N_35026), + .I1(com_tlm_u_tlm_tx_vc0_token_fifo_token_index[0]), + .I2(com_tlm_u_tlm_tx_vc0_token_fifo_token_index[2]), + .I3(com_tlm_u_tlm_tx_vc0_token_fifo_token_index[3]), + .O(com_tlm_u_tlm_tx_vc0_token_fifo_tokens_loaded_0_sqmuxa) + ); + defparam com_tlm_u_tlm_tx_vc0_token_fifo_fifo_d_6_i_o2_i_m2_0_3_.INIT = 8'hAC; + LUT3_L com_tlm_u_tlm_tx_vc0_token_fifo_fifo_d_6_i_o2_i_m2_0_3_ ( + .I0(com_tlm_u_tlm_tx_freed_buf[3]), + .I1(com_tlm_u_tlm_tx_vc0_token_fifo_token_index[3]), + .I2(com_tlm_u_tlm_tx_vc0_token_fifo_tokens_loaded_2550), + .LO(com_tlm_u_tlm_tx_vc0_token_fifo_fifo_d_6_i_o2_i_m2_0[3]) + ); + defparam com_tlm_u_tlm_tx_vc0_token_fifo_fifo_d_6_i_m2_i_m2_0_2_.INIT = 8'hAC; + LUT3_L com_tlm_u_tlm_tx_vc0_token_fifo_fifo_d_6_i_m2_i_m2_0_2_ ( + .I0(com_tlm_u_tlm_tx_freed_buf[2]), + .I1(com_tlm_u_tlm_tx_vc0_token_fifo_token_index[2]), + .I2(com_tlm_u_tlm_tx_vc0_token_fifo_tokens_loaded_2550), + .LO(com_tlm_u_tlm_tx_vc0_token_fifo_fifo_d_6_i_m2_i_m2_0_2__2541) + ); + defparam com_tlm_u_tlm_tx_vc0_token_fifo_N_69042_i.INIT = 8'hEA; + LUT3_L com_tlm_u_tlm_tx_vc0_token_fifo_N_69042_i ( + .I0(com_tlm_u_tlm_tx_vc0_token_fifo_N_35026), + .I1(com_tlm_u_tlm_tx_freed_buf[1]), + .I2(com_tlm_u_tlm_tx_vc0_token_fifo_tokens_loaded_2550), + .LO(com_tlm_u_tlm_tx_vc0_token_fifo_N_69042_i_2542) + ); + defparam com_tlm_u_tlm_tx_vc0_token_fifo_fifo_d_6_i_m2_i_m2_0_0_.INIT = 8'hAC; + LUT3_L com_tlm_u_tlm_tx_vc0_token_fifo_fifo_d_6_i_m2_i_m2_0_0_ ( + .I0(com_tlm_u_tlm_tx_freed_buf[0]), + .I1(com_tlm_u_tlm_tx_vc0_token_fifo_token_index[0]), + .I2(com_tlm_u_tlm_tx_vc0_token_fifo_tokens_loaded_2550), + .LO(com_tlm_u_tlm_tx_vc0_token_fifo_fifo_d_6_i_m2_i_m2_0_0__2543) + ); + defparam com_tlm_u_tlm_tx_vc0_token_fifo_N_69041_i.INIT = 4'hB; + LUT2_L com_tlm_u_tlm_tx_vc0_token_fifo_N_69041_i ( + .I0(com_tlm_u_tlm_tx_N_38179_i), + .I1(com_tlm_u_tlm_tx_vc0_token_fifo_tokens_loaded_2550), + .LO(com_tlm_u_tlm_tx_vc0_token_fifo_N_69041_i_2544) + ); + defparam com_tlm_u_tlm_tx_vc0_token_fifo_un1_token_index_axbxc3.INIT = 4'h6; + LUT2_L com_tlm_u_tlm_tx_vc0_token_fifo_un1_token_index_axbxc3 ( + .I0(com_tlm_u_tlm_tx_vc0_token_fifo_token_index[3]), + .I1(com_tlm_u_tlm_tx_vc0_token_fifo_un1_token_index_p4_2546), + .LO(com_tlm_u_tlm_tx_vc0_token_fifo_un1_token_index_axbxc3_2545) + ); + defparam com_tlm_u_tlm_tx_vc0_token_fifo_un1_token_index_axbxc2.INIT = 16'hF078; + LUT4_L com_tlm_u_tlm_tx_vc0_token_fifo_un1_token_index_axbxc2 ( + .I0(com_tlm_u_tlm_tx_vc0_token_fifo_token_index[0]), + .I1(com_tlm_u_tlm_tx_vc0_token_fifo_token_index[1]), + .I2(com_tlm_u_tlm_tx_vc0_token_fifo_token_index[2]), + .I3(com_tlm_u_tlm_tx_vc0_token_fifo_tokens_loaded_2550), + .LO(com_tlm_u_tlm_tx_vc0_token_fifo_un1_token_index_axbxc2_2547) + ); + defparam com_tlm_u_tlm_tx_vc0_token_fifo_un1_token_index_axbxc1.INIT = 8'hC6; + LUT3_L com_tlm_u_tlm_tx_vc0_token_fifo_un1_token_index_axbxc1 ( + .I0(com_tlm_u_tlm_tx_vc0_token_fifo_token_index[0]), + .I1(com_tlm_u_tlm_tx_vc0_token_fifo_token_index[1]), + .I2(com_tlm_u_tlm_tx_vc0_token_fifo_tokens_loaded_2550), + .LO(com_tlm_u_tlm_tx_vc0_token_fifo_un1_token_index_axbxc1_2548) + ); + defparam com_tlm_u_tlm_tx_vc0_token_fifo_un1_token_index_axbxc0.INIT = 4'h9; + LUT2_L com_tlm_u_tlm_tx_vc0_token_fifo_un1_token_index_axbxc0 ( + .I0(com_tlm_u_tlm_tx_vc0_token_fifo_token_index[0]), + .I1(com_tlm_u_tlm_tx_vc0_token_fifo_tokens_loaded_2550), + .LO(com_tlm_u_tlm_tx_vc0_token_fifo_un1_token_index_axbxc0_2549) + ); + GND com_tlm_u_tlm_tx_vc0_token_fifo_t_fifo_GND ( + .G(com_tlm_u_tlm_tx_vc0_token_fifo_t_fifo_GND_2551) + ); + SRLC16E com_tlm_u_tlm_tx_vc0_token_fifo_t_fifo_srlrow_0__srlcol_0__srlinst ( + .CE(com_tlm_u_tlm_tx_vc0_released_buf), + .D(com_tlm_u_tlm_tx_vc0_token_fifo_fifo_d[0]), + .Q(com_tlm_u_tlm_tx_vc0_token_fifo_t_fifo_shift_tap[0]), + .CLK(NlwRenamedSig_OI_trn_clk), + .Q15(NLW_com_tlm_u_tlm_tx_vc0_token_fifo_t_fifo_srlrow_0__srlcol_0__srlinst_Q15_UNCONNECTED), + .A0(com_tlm_u_tlm_tx_vc0_token_fifo_t_fifo_raddr_lo[0]), + .A1(com_tlm_u_tlm_tx_vc0_token_fifo_t_fifo_raddr_lo[1]), + .A2(com_tlm_u_tlm_tx_vc0_token_fifo_t_fifo_raddr_lo[2]), + .A3(com_tlm_u_tlm_tx_vc0_token_fifo_t_fifo_raddr_lo[3]) + ); + SRLC16E com_tlm_u_tlm_tx_vc0_token_fifo_t_fifo_srlrow_0__srlcol_3__srlinst ( + .CE(com_tlm_u_tlm_tx_vc0_released_buf), + .D(com_tlm_u_tlm_tx_vc0_token_fifo_fifo_d[3]), + .Q(com_tlm_u_tlm_tx_vc0_token_fifo_t_fifo_shift_tap[3]), + .CLK(NlwRenamedSig_OI_trn_clk), + .Q15(NLW_com_tlm_u_tlm_tx_vc0_token_fifo_t_fifo_srlrow_0__srlcol_3__srlinst_Q15_UNCONNECTED), + .A0(com_tlm_u_tlm_tx_vc0_token_fifo_t_fifo_raddr_lo[0]), + .A1(com_tlm_u_tlm_tx_vc0_token_fifo_t_fifo_raddr_lo[1]), + .A2(com_tlm_u_tlm_tx_vc0_token_fifo_t_fifo_raddr_lo[2]), + .A3(com_tlm_u_tlm_tx_vc0_token_fifo_t_fifo_raddr_lo[3]) + ); + SRLC16E com_tlm_u_tlm_tx_vc0_token_fifo_t_fifo_srlrow_0__srlcol_2__srlinst ( + .CE(com_tlm_u_tlm_tx_vc0_released_buf), + .D(com_tlm_u_tlm_tx_vc0_token_fifo_fifo_d[2]), + .Q(com_tlm_u_tlm_tx_vc0_token_fifo_t_fifo_shift_tap[2]), + .CLK(NlwRenamedSig_OI_trn_clk), + .Q15(NLW_com_tlm_u_tlm_tx_vc0_token_fifo_t_fifo_srlrow_0__srlcol_2__srlinst_Q15_UNCONNECTED), + .A0(com_tlm_u_tlm_tx_vc0_token_fifo_t_fifo_raddr_lo[0]), + .A1(com_tlm_u_tlm_tx_vc0_token_fifo_t_fifo_raddr_lo[1]), + .A2(com_tlm_u_tlm_tx_vc0_token_fifo_t_fifo_raddr_lo[2]), + .A3(com_tlm_u_tlm_tx_vc0_token_fifo_t_fifo_raddr_lo[3]) + ); + SRLC16E com_tlm_u_tlm_tx_vc0_token_fifo_t_fifo_srlrow_0__srlcol_1__srlinst ( + .CE(com_tlm_u_tlm_tx_vc0_released_buf), + .D(com_tlm_u_tlm_tx_vc0_token_fifo_fifo_d[1]), + .Q(com_tlm_u_tlm_tx_vc0_token_fifo_t_fifo_shift_tap[1]), + .CLK(NlwRenamedSig_OI_trn_clk), + .Q15(NLW_com_tlm_u_tlm_tx_vc0_token_fifo_t_fifo_srlrow_0__srlcol_1__srlinst_Q15_UNCONNECTED), + .A0(com_tlm_u_tlm_tx_vc0_token_fifo_t_fifo_raddr_lo[0]), + .A1(com_tlm_u_tlm_tx_vc0_token_fifo_t_fifo_raddr_lo[1]), + .A2(com_tlm_u_tlm_tx_vc0_token_fifo_t_fifo_raddr_lo[2]), + .A3(com_tlm_u_tlm_tx_vc0_token_fifo_t_fifo_raddr_lo[3]) + ); + FDS com_tlm_u_tlm_tx_vc0_token_fifo_t_fifo_raddr_lo_0_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_token_fifo_t_fifo_un1_raddr_lo_1_axb_0_2557), + .Q(com_tlm_u_tlm_tx_vc0_token_fifo_t_fifo_raddr_lo[0]), + .S(plm_link_up_i) + ); + FDS com_tlm_u_tlm_tx_vc0_token_fifo_t_fifo_raddr_lo_1_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_token_fifo_t_fifo_un1_raddr_lo_1_s_1_0), + .Q(com_tlm_u_tlm_tx_vc0_token_fifo_t_fifo_raddr_lo[1]), + .S(plm_link_up_i) + ); + FDS com_tlm_u_tlm_tx_vc0_token_fifo_t_fifo_raddr_lo_2_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_token_fifo_t_fifo_un1_raddr_lo_1_s_2_0), + .Q(com_tlm_u_tlm_tx_vc0_token_fifo_t_fifo_raddr_lo[2]), + .S(plm_link_up_i) + ); + FDS com_tlm_u_tlm_tx_vc0_token_fifo_t_fifo_raddr_lo_3_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_token_fifo_t_fifo_un1_raddr_lo_1_s_3_0), + .Q(com_tlm_u_tlm_tx_vc0_token_fifo_t_fifo_raddr_lo[3]), + .S(plm_link_up_i) + ); + FDRE com_tlm_u_tlm_tx_vc0_token_fifo_t_fifo_nxt_vld_o ( + .CE(com_tlm_u_tlm_tx_vc0_token_fifo_t_fifo_N_68485_i_2555), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_released_buf), + .Q(com_tlm_u_tlm_tx_vc0_token_fifo_t_fifo_nxt_vld_o_2561), + .R(plm_link_up_i) + ); + FDRE com_tlm_u_tlm_tx_vc0_token_fifo_t_fifo_vld_o ( + .CE(com_tlm_u_tlm_tx_vc0_token_fifo_t_fifo_N_48885_i_i_2563), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_token_fifo_t_fifo_nxt_vld_o_2561), + .Q(com_tlm_u_tlm_tx_vc0_token_fifo_t_fifo_vld_o_2562), + .R(plm_link_up_i) + ); + MUXCY_L com_tlm_u_tlm_tx_vc0_token_fifo_t_fifo_un1_raddr_lo_1_cry_0 ( + .CI(com_tlm_u_tlm_tx_vc0_token_fifo_t_fifo_GND_2551), + .DI(com_tlm_u_tlm_tx_vc0_token_fifo_t_fifo_raddr_lo[0]), + .LO(com_tlm_u_tlm_tx_vc0_token_fifo_t_fifo_un1_raddr_lo_1_cry_0_2552), + .S(com_tlm_u_tlm_tx_vc0_token_fifo_t_fifo_un1_raddr_lo_1_axb_0_2557) + ); + MUXCY_L com_tlm_u_tlm_tx_vc0_token_fifo_t_fifo_un1_raddr_lo_1_cry_1 ( + .CI(com_tlm_u_tlm_tx_vc0_token_fifo_t_fifo_un1_raddr_lo_1_cry_0_2552), + .DI(com_tlm_u_tlm_tx_vc0_token_fifo_t_fifo_raddr_lo[1]), + .LO(com_tlm_u_tlm_tx_vc0_token_fifo_t_fifo_un1_raddr_lo_1_cry_1_2553), + .S(com_tlm_u_tlm_tx_vc0_token_fifo_t_fifo_un1_raddr_lo_1_axb_1_2560) + ); + XORCY com_tlm_u_tlm_tx_vc0_token_fifo_t_fifo_un1_raddr_lo_1_s_1 ( + .CI(com_tlm_u_tlm_tx_vc0_token_fifo_t_fifo_un1_raddr_lo_1_cry_0_2552), + .LI(com_tlm_u_tlm_tx_vc0_token_fifo_t_fifo_un1_raddr_lo_1_axb_1_2560), + .O(com_tlm_u_tlm_tx_vc0_token_fifo_t_fifo_un1_raddr_lo_1_s_1_0) + ); + MUXCY_L com_tlm_u_tlm_tx_vc0_token_fifo_t_fifo_un1_raddr_lo_1_cry_2 ( + .CI(com_tlm_u_tlm_tx_vc0_token_fifo_t_fifo_un1_raddr_lo_1_cry_1_2553), + .DI(com_tlm_u_tlm_tx_vc0_token_fifo_t_fifo_raddr_lo[2]), + .LO(com_tlm_u_tlm_tx_vc0_token_fifo_t_fifo_un1_raddr_lo_1_cry_2_2554), + .S(com_tlm_u_tlm_tx_vc0_token_fifo_t_fifo_un1_raddr_lo_1_axb_2_2559) + ); + XORCY com_tlm_u_tlm_tx_vc0_token_fifo_t_fifo_un1_raddr_lo_1_s_2 ( + .CI(com_tlm_u_tlm_tx_vc0_token_fifo_t_fifo_un1_raddr_lo_1_cry_1_2553), + .LI(com_tlm_u_tlm_tx_vc0_token_fifo_t_fifo_un1_raddr_lo_1_axb_2_2559), + .O(com_tlm_u_tlm_tx_vc0_token_fifo_t_fifo_un1_raddr_lo_1_s_2_0) + ); + XORCY com_tlm_u_tlm_tx_vc0_token_fifo_t_fifo_un1_raddr_lo_1_s_3 ( + .CI(com_tlm_u_tlm_tx_vc0_token_fifo_t_fifo_un1_raddr_lo_1_cry_2_2554), + .LI(com_tlm_u_tlm_tx_vc0_token_fifo_t_fifo_un1_raddr_lo_1_axb_3_2558), + .O(com_tlm_u_tlm_tx_vc0_token_fifo_t_fifo_un1_raddr_lo_1_s_3_0) + ); + defparam com_tlm_u_tlm_tx_vc0_token_fifo_t_fifo_raddr_en_0_0_0_o3.INIT = 4'h4; + LUT2 com_tlm_u_tlm_tx_vc0_token_fifo_t_fifo_raddr_en_0_0_0_o3 ( + .I0(com_tlm_u_tlm_tx_vc0_frame_vld), + .I1(com_tlm_u_tlm_tx_vc0_token_fifo_t_fifo_vld_o_2562), + .O(com_tlm_u_tlm_tx_vc0_token_fifo_t_fifo_N_48885_i) + ); + defparam com_tlm_u_tlm_tx_vc0_token_fifo_t_fifo_un1_bkp_i_1_i_0_0_0_a2_2.INIT = 16'h0001; + LUT4 com_tlm_u_tlm_tx_vc0_token_fifo_t_fifo_un1_bkp_i_1_i_0_0_0_a2_2 ( + .I0(com_tlm_u_tlm_tx_vc0_token_fifo_t_fifo_raddr_lo[0]), + .I1(com_tlm_u_tlm_tx_vc0_token_fifo_t_fifo_raddr_lo[1]), + .I2(com_tlm_u_tlm_tx_vc0_token_fifo_t_fifo_raddr_lo[2]), + .I3(com_tlm_u_tlm_tx_vc0_token_fifo_t_fifo_raddr_lo[3]), + .O(com_tlm_u_tlm_tx_vc0_token_fifo_t_fifo_un1_bkp_i_1_i_0_0_0_a2_2_2556) + ); + defparam com_tlm_u_tlm_tx_vc0_token_fifo_t_fifo_N_68485_i.INIT = 8'hDC; + LUT3 com_tlm_u_tlm_tx_vc0_token_fifo_t_fifo_N_68485_i ( + .I0(com_tlm_u_tlm_tx_vc0_token_fifo_t_fifo_N_48885_i), + .I1(com_tlm_u_tlm_tx_vc0_released_buf), + .I2(com_tlm_u_tlm_tx_vc0_token_fifo_t_fifo_un1_bkp_i_1_i_0_0_0_a2_2_2556), + .O(com_tlm_u_tlm_tx_vc0_token_fifo_t_fifo_N_68485_i_2555) + ); + defparam com_tlm_u_tlm_tx_vc0_token_fifo_t_fifo_un1_raddr_lo_1_axb_0.INIT = 16'h693C; + LUT4 com_tlm_u_tlm_tx_vc0_token_fifo_t_fifo_un1_raddr_lo_1_axb_0 ( + .I0(com_tlm_u_tlm_tx_vc0_token_fifo_t_fifo_N_48885_i), + .I1(com_tlm_u_tlm_tx_vc0_released_buf), + .I2(com_tlm_u_tlm_tx_vc0_token_fifo_t_fifo_raddr_lo[0]), + .I3(com_tlm_u_tlm_tx_vc0_token_fifo_t_fifo_nxt_vld_o_2561), + .O(com_tlm_u_tlm_tx_vc0_token_fifo_t_fifo_un1_raddr_lo_1_axb_0_2557) + ); + defparam com_tlm_u_tlm_tx_vc0_token_fifo_t_fifo_un1_raddr_lo_1_axb_3.INIT = 16'hE1F0; + LUT4_L com_tlm_u_tlm_tx_vc0_token_fifo_t_fifo_un1_raddr_lo_1_axb_3 ( + .I0(com_tlm_u_tlm_tx_vc0_token_fifo_t_fifo_N_48885_i), + .I1(com_tlm_u_tlm_tx_vc0_released_buf), + .I2(com_tlm_u_tlm_tx_vc0_token_fifo_t_fifo_raddr_lo[3]), + .I3(com_tlm_u_tlm_tx_vc0_token_fifo_t_fifo_nxt_vld_o_2561), + .LO(com_tlm_u_tlm_tx_vc0_token_fifo_t_fifo_un1_raddr_lo_1_axb_3_2558) + ); + defparam com_tlm_u_tlm_tx_vc0_token_fifo_t_fifo_un1_raddr_lo_1_axb_2.INIT = 16'hE1F0; + LUT4_L com_tlm_u_tlm_tx_vc0_token_fifo_t_fifo_un1_raddr_lo_1_axb_2 ( + .I0(com_tlm_u_tlm_tx_vc0_token_fifo_t_fifo_N_48885_i), + .I1(com_tlm_u_tlm_tx_vc0_released_buf), + .I2(com_tlm_u_tlm_tx_vc0_token_fifo_t_fifo_raddr_lo[2]), + .I3(com_tlm_u_tlm_tx_vc0_token_fifo_t_fifo_nxt_vld_o_2561), + .LO(com_tlm_u_tlm_tx_vc0_token_fifo_t_fifo_un1_raddr_lo_1_axb_2_2559) + ); + defparam com_tlm_u_tlm_tx_vc0_token_fifo_t_fifo_un1_raddr_lo_1_axb_1.INIT = 16'hE1F0; + LUT4_L com_tlm_u_tlm_tx_vc0_token_fifo_t_fifo_un1_raddr_lo_1_axb_1 ( + .I0(com_tlm_u_tlm_tx_vc0_token_fifo_t_fifo_N_48885_i), + .I1(com_tlm_u_tlm_tx_vc0_released_buf), + .I2(com_tlm_u_tlm_tx_vc0_token_fifo_t_fifo_raddr_lo[1]), + .I3(com_tlm_u_tlm_tx_vc0_token_fifo_t_fifo_nxt_vld_o_2561), + .LO(com_tlm_u_tlm_tx_vc0_token_fifo_t_fifo_un1_raddr_lo_1_axb_1_2560) + ); + defparam com_tlm_u_tlm_tx_vc0_token_fifo_t_fifo_N_48885_i_i.INIT = 4'hD; + LUT2 com_tlm_u_tlm_tx_vc0_token_fifo_t_fifo_N_48885_i_i ( + .I0(com_tlm_u_tlm_tx_vc0_token_fifo_t_fifo_vld_o_2562), + .I1(com_tlm_u_tlm_tx_vc0_frame_vld), + .O(com_tlm_u_tlm_tx_vc0_token_fifo_t_fifo_N_48885_i_i_2563) + ); + FDE com_tlm_u_tlm_tx_vc0_token_fifo_t_fifo_d_o_3_ ( + .CE(com_tlm_u_tlm_tx_vc0_token_fifo_t_fifo_N_48885_i_i_2563), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_token_fifo_t_fifo_shift_tap[3]), + .Q(com_tlm_u_tlm_tx_vc0_tkn_buf_num[3]) + ); + FDE com_tlm_u_tlm_tx_vc0_token_fifo_t_fifo_d_o_2_ ( + .CE(com_tlm_u_tlm_tx_vc0_token_fifo_t_fifo_N_48885_i_i_2563), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_token_fifo_t_fifo_shift_tap[2]), + .Q(com_tlm_u_tlm_tx_vc0_tkn_buf_num[2]) + ); + FDE com_tlm_u_tlm_tx_vc0_token_fifo_t_fifo_d_o_1_ ( + .CE(com_tlm_u_tlm_tx_vc0_token_fifo_t_fifo_N_48885_i_i_2563), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_token_fifo_t_fifo_shift_tap[1]), + .Q(com_tlm_u_tlm_tx_vc0_tkn_buf_num[1]) + ); + FDE com_tlm_u_tlm_tx_vc0_token_fifo_t_fifo_d_o_0_ ( + .CE(com_tlm_u_tlm_tx_vc0_token_fifo_t_fifo_N_48885_i_i_2563), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_token_fifo_t_fifo_shift_tap[0]), + .Q(com_tlm_u_tlm_tx_vc0_tkn_buf_num[0]) + ); + VCC com_tlm_u_tlm_tx_vc0_frm_seq_VCC ( + .P(com_tlm_u_tlm_tx_vc0_frm_seq_VCC_2614) + ); + GND com_tlm_u_tlm_tx_vc0_frm_seq_GND ( + .G(com_tlm_u_tlm_tx_vc0_frm_seq_GND_2567) + ); + FDR com_tlm_u_tlm_tx_vc0_frm_seq_oq_ren ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_N_8842_i), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_oq_ren_2617), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_tx_vc0_frm_seq_consumed_nph ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_N_48333_i), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_consumed_nph_2564), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_tx_vc0_frm_seq_bq_wen ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_N_13930_i), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_bq_wen_2622), + .R(plm_link_up_i) + ); + FDS com_tlm_u_tlm_tx_vc0_frm_seq_queue_state_0_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_N_40766_i), + .Q(com_tlm_u_tlm_tx_queue_state[0]), + .S(plm_link_up_i) + ); + FDR com_tlm_u_tlm_tx_vc0_frm_seq_queue_state_1_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_N_8943_i), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_queue_state[1]), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_tx_vc0_frm_seq_queue_state_2_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_N_67885_i_2634), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_queue_state[2]), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_tx_vc0_frm_seq_queue_state_3_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_nxt_queue_state_1_sqmuxa_1), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_queue_state[3]), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_tx_vc0_frm_seq_consumed_ph ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_N_48358_i), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_consumed_ph_2565), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_tx_vc0_frm_seq_consumed_cplh ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_N_48356_i), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_consumed_cplh_2566), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_tx_vc0_frm_seq_sq_wen ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_N_49115_i), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_sq_wen_2640), + .R(plm_link_up_i) + ); + FDS com_tlm_u_tlm_tx_vc0_frm_seq_seq_state_0_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_N_17156_i), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_seq_state[0]), + .S(plm_link_up_i) + ); + FDR com_tlm_u_tlm_tx_vc0_frm_seq_seq_state_1_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_nxt_seq_state_0_sqmuxa_2), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_seq_state[1]), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_tx_vc0_frm_seq_seq_state_2_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_nxt_seq_state_0_sqmuxa_1), + .Q(com_tlm_u_tlm_tx_am_retry_dst_rdy), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_tx_vc0_frm_seq_seq_state_3_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_N_42589_i_2633), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_start_src_rdy), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_tx_vc0_frm_seq_header_vld_oq ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_N_13932_i), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_header_vld_oq_2624), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_tx_vc0_frm_seq_bnpd_diff_11_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_un4_bnpd_diff_s_11_2602), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_bnpd_diff[11]), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_tx_vc0_frm_seq_pd_diff_11_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_un4_pd_diff_s_11_2615), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_pd_diff[11]), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_tx_vc0_frm_seq_npd_diff_11_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_un4_npd_diff_s_11_2578), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_npd_diff[11]), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_tx_vc0_frm_seq_cpld_diff_11_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_un4_cpld_diff_s_11_2590), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_cpld_diff[11]), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_tx_vc0_frm_seq_nonposted_vld_oq ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_nonposted_vld_oq_3), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_nonposted_vld_oq_2625), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_tx_vc0_frm_seq_header_vld_bq ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_header_vld_bq_3), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_header_vld_bq_2618), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_tx_vc0_frm_seq_last_buf_num_match ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_last_buf_num_match_3), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_last_buf_num_match_2635), + .R(plm_link_up_i) + ); + FDRSE com_tlm_u_tlm_tx_vc0_frm_seq_bq_holdoff ( + .CE(com_tlm_u_tlm_tx_vc0_frm_seq_bq_vld), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_GND_2567), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_bq_holdoff_2621), + .R(plm_link_up_i), + .S(com_tlm_u_tlm_tx_vc0_frm_seq_bq_holdoff13) + ); + FDRE com_tlm_u_tlm_tx_vc0_frm_seq_start_retry_o ( + .CE(com_tlm_u_tlm_tx_vc0_frm_seq_N_41839_i_i_2638), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_am_retry_dst_rdy), + .Q(com_tlm_u_tlm_tx_vc0_start_retry), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_tx_vc0_frm_seq_bq_no_payload_qq ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_bq_q[10]), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_bq_no_payload_qq_2619), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_tx_vc0_frm_seq_oq_no_payload_qq ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_bq_d[10]), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_oq_no_payload_qq_2623), + .R(plm_link_up_i) + ); + FDRE com_tlm_u_tlm_tx_vc0_frm_seq_last_buf_num_0_ ( + .CE(com_tlm_u_tlm_tx_vc0_frm_seq_seq_state[1]), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_sq_q[0]), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_last_buf_num[0]), + .R(plm_link_up_i) + ); + FDRE com_tlm_u_tlm_tx_vc0_frm_seq_last_buf_num_1_ ( + .CE(com_tlm_u_tlm_tx_vc0_frm_seq_seq_state[1]), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_sq_q[1]), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_last_buf_num[1]), + .R(plm_link_up_i) + ); + FDRE com_tlm_u_tlm_tx_vc0_frm_seq_last_buf_num_2_ ( + .CE(com_tlm_u_tlm_tx_vc0_frm_seq_seq_state[1]), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_sq_q[2]), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_last_buf_num[2]), + .R(plm_link_up_i) + ); + FDRE com_tlm_u_tlm_tx_vc0_frm_seq_last_buf_num_3_ ( + .CE(com_tlm_u_tlm_tx_vc0_frm_seq_seq_state[1]), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_sq_q[3]), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_last_buf_num[3]), + .R(plm_link_up_i) + ); + MUXCY_L com_tlm_u_tlm_tx_vc0_frm_seq_un4_npd_diff_cry_0 ( + .CI(com_tlm_u_tlm_tx_vc0_frm_seq_VCC_2614), + .DI(com_tlm_u_tlm_tx_vc0_frm_seq_npd_av[0]), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_un4_npd_diff_cry_0_2568), + .S(com_tlm_u_tlm_tx_vc0_frm_seq_un4_npd_diff_axb_0_2669) + ); + MUXCY_L com_tlm_u_tlm_tx_vc0_frm_seq_un4_npd_diff_cry_1 ( + .CI(com_tlm_u_tlm_tx_vc0_frm_seq_un4_npd_diff_cry_0_2568), + .DI(com_tlm_u_tlm_tx_vc0_frm_seq_npd_av[1]), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_un4_npd_diff_cry_1_2569), + .S(com_tlm_u_tlm_tx_vc0_frm_seq_un4_npd_diff_axb_1_2668) + ); + MUXCY_L com_tlm_u_tlm_tx_vc0_frm_seq_un4_npd_diff_cry_2 ( + .CI(com_tlm_u_tlm_tx_vc0_frm_seq_un4_npd_diff_cry_1_2569), + .DI(com_tlm_u_tlm_tx_vc0_frm_seq_npd_av[2]), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_un4_npd_diff_cry_2_2570), + .S(com_tlm_u_tlm_tx_vc0_frm_seq_un4_npd_diff_axb_2_2667) + ); + MUXCY_L com_tlm_u_tlm_tx_vc0_frm_seq_un4_npd_diff_cry_3 ( + .CI(com_tlm_u_tlm_tx_vc0_frm_seq_un4_npd_diff_cry_2_2570), + .DI(com_tlm_u_tlm_tx_vc0_frm_seq_npd_av[3]), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_un4_npd_diff_cry_3_2571), + .S(com_tlm_u_tlm_tx_vc0_frm_seq_un4_npd_diff_axb_3_2666) + ); + MUXCY_L com_tlm_u_tlm_tx_vc0_frm_seq_un4_npd_diff_cry_4 ( + .CI(com_tlm_u_tlm_tx_vc0_frm_seq_un4_npd_diff_cry_3_2571), + .DI(com_tlm_u_tlm_tx_vc0_frm_seq_npd_av[4]), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_un4_npd_diff_cry_4_2572), + .S(com_tlm_u_tlm_tx_vc0_frm_seq_un4_npd_diff_axb_4_2665) + ); + MUXCY_L com_tlm_u_tlm_tx_vc0_frm_seq_un4_npd_diff_cry_5 ( + .CI(com_tlm_u_tlm_tx_vc0_frm_seq_un4_npd_diff_cry_4_2572), + .DI(com_tlm_u_tlm_tx_vc0_frm_seq_npd_av[5]), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_un4_npd_diff_cry_5_2573), + .S(com_tlm_u_tlm_tx_vc0_frm_seq_un4_npd_diff_axb_5_2664) + ); + MUXCY_L com_tlm_u_tlm_tx_vc0_frm_seq_un4_npd_diff_cry_6 ( + .CI(com_tlm_u_tlm_tx_vc0_frm_seq_un4_npd_diff_cry_5_2573), + .DI(com_tlm_u_tlm_tx_vc0_frm_seq_VCC_2614), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_un4_npd_diff_cry_6_2574), + .S(com_tlm_u_tlm_tx_vc0_frm_seq_npd_av_i[6]) + ); + MUXCY_L com_tlm_u_tlm_tx_vc0_frm_seq_un4_npd_diff_cry_7 ( + .CI(com_tlm_u_tlm_tx_vc0_frm_seq_un4_npd_diff_cry_6_2574), + .DI(com_tlm_u_tlm_tx_vc0_frm_seq_VCC_2614), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_un4_npd_diff_cry_7_2575), + .S(com_tlm_u_tlm_tx_vc0_frm_seq_npd_av_i[7]) + ); + MUXCY_L com_tlm_u_tlm_tx_vc0_frm_seq_un4_npd_diff_cry_8 ( + .CI(com_tlm_u_tlm_tx_vc0_frm_seq_un4_npd_diff_cry_7_2575), + .DI(com_tlm_u_tlm_tx_vc0_frm_seq_VCC_2614), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_un4_npd_diff_cry_8_2576), + .S(com_tlm_u_tlm_tx_vc0_frm_seq_npd_av_i[8]) + ); + MUXCY_L com_tlm_u_tlm_tx_vc0_frm_seq_un4_npd_diff_cry_9 ( + .CI(com_tlm_u_tlm_tx_vc0_frm_seq_un4_npd_diff_cry_8_2576), + .DI(com_tlm_u_tlm_tx_vc0_frm_seq_VCC_2614), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_un4_npd_diff_cry_9_2577), + .S(com_tlm_u_tlm_tx_vc0_frm_seq_npd_av_i[9]) + ); + MUXCY_L com_tlm_u_tlm_tx_vc0_frm_seq_un4_npd_diff_cry_10 ( + .CI(com_tlm_u_tlm_tx_vc0_frm_seq_un4_npd_diff_cry_9_2577), + .DI(com_tlm_u_tlm_tx_vc0_frm_seq_VCC_2614), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_un4_npd_diff_cry_10_2579), + .S(com_tlm_u_tlm_tx_vc0_frm_seq_npd_av_i[10]) + ); + XORCY com_tlm_u_tlm_tx_vc0_frm_seq_un4_npd_diff_s_11 ( + .CI(com_tlm_u_tlm_tx_vc0_frm_seq_un4_npd_diff_cry_10_2579), + .LI(com_tlm_u_tlm_tx_vc0_frm_seq_un4_npd_diff_s_11_sf_2629), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_un4_npd_diff_s_11_2578) + ); + MUXCY_L com_tlm_u_tlm_tx_vc0_frm_seq_un4_cpld_diff_cry_0 ( + .CI(com_tlm_u_tlm_tx_vc0_frm_seq_VCC_2614), + .DI(com_tlm_u_tlm_tx_vc0_frm_seq_cpld_av_0_), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_un4_cpld_diff_cry_0_2580), + .S(com_tlm_u_tlm_tx_vc0_frm_seq_un4_cpld_diff_axb_0_2663) + ); + MUXCY_L com_tlm_u_tlm_tx_vc0_frm_seq_un4_cpld_diff_cry_1 ( + .CI(com_tlm_u_tlm_tx_vc0_frm_seq_un4_cpld_diff_cry_0_2580), + .DI(com_tlm_u_tlm_tx_vc0_frm_seq_cpld_av_1_), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_un4_cpld_diff_cry_1_2581), + .S(com_tlm_u_tlm_tx_vc0_frm_seq_un4_cpld_diff_axb_1_2662) + ); + MUXCY_L com_tlm_u_tlm_tx_vc0_frm_seq_un4_cpld_diff_cry_2 ( + .CI(com_tlm_u_tlm_tx_vc0_frm_seq_un4_cpld_diff_cry_1_2581), + .DI(com_tlm_u_tlm_tx_vc0_frm_seq_cpld_av_2_), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_un4_cpld_diff_cry_2_2582), + .S(com_tlm_u_tlm_tx_vc0_frm_seq_un4_cpld_diff_axb_2_2661) + ); + MUXCY_L com_tlm_u_tlm_tx_vc0_frm_seq_un4_cpld_diff_cry_3 ( + .CI(com_tlm_u_tlm_tx_vc0_frm_seq_un4_cpld_diff_cry_2_2582), + .DI(com_tlm_u_tlm_tx_vc0_frm_seq_cpld_av_3_), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_un4_cpld_diff_cry_3_2583), + .S(com_tlm_u_tlm_tx_vc0_frm_seq_un4_cpld_diff_axb_3_2660) + ); + MUXCY_L com_tlm_u_tlm_tx_vc0_frm_seq_un4_cpld_diff_cry_4 ( + .CI(com_tlm_u_tlm_tx_vc0_frm_seq_un4_cpld_diff_cry_3_2583), + .DI(com_tlm_u_tlm_tx_vc0_frm_seq_cpld_av_4_), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_un4_cpld_diff_cry_4_2584), + .S(com_tlm_u_tlm_tx_vc0_frm_seq_un4_cpld_diff_axb_4_2659) + ); + MUXCY_L com_tlm_u_tlm_tx_vc0_frm_seq_un4_cpld_diff_cry_5 ( + .CI(com_tlm_u_tlm_tx_vc0_frm_seq_un4_cpld_diff_cry_4_2584), + .DI(com_tlm_u_tlm_tx_vc0_frm_seq_cpld_av_5_), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_un4_cpld_diff_cry_5_2585), + .S(com_tlm_u_tlm_tx_vc0_frm_seq_un4_cpld_diff_axb_5_2658) + ); + MUXCY_L com_tlm_u_tlm_tx_vc0_frm_seq_un4_cpld_diff_cry_6 ( + .CI(com_tlm_u_tlm_tx_vc0_frm_seq_un4_cpld_diff_cry_5_2585), + .DI(com_tlm_u_tlm_tx_vc0_frm_seq_VCC_2614), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_un4_cpld_diff_cry_6_2586), + .S(com_tlm_u_tlm_tx_vc0_frm_seq_cpld_av_i[6]) + ); + MUXCY_L com_tlm_u_tlm_tx_vc0_frm_seq_un4_cpld_diff_cry_7 ( + .CI(com_tlm_u_tlm_tx_vc0_frm_seq_un4_cpld_diff_cry_6_2586), + .DI(com_tlm_u_tlm_tx_vc0_frm_seq_VCC_2614), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_un4_cpld_diff_cry_7_2587), + .S(com_tlm_u_tlm_tx_vc0_frm_seq_cpld_av_i[7]) + ); + MUXCY_L com_tlm_u_tlm_tx_vc0_frm_seq_un4_cpld_diff_cry_8 ( + .CI(com_tlm_u_tlm_tx_vc0_frm_seq_un4_cpld_diff_cry_7_2587), + .DI(com_tlm_u_tlm_tx_vc0_frm_seq_VCC_2614), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_un4_cpld_diff_cry_8_2588), + .S(com_tlm_u_tlm_tx_vc0_frm_seq_cpld_av_i[8]) + ); + MUXCY_L com_tlm_u_tlm_tx_vc0_frm_seq_un4_cpld_diff_cry_9 ( + .CI(com_tlm_u_tlm_tx_vc0_frm_seq_un4_cpld_diff_cry_8_2588), + .DI(com_tlm_u_tlm_tx_vc0_frm_seq_VCC_2614), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_un4_cpld_diff_cry_9_2589), + .S(com_tlm_u_tlm_tx_vc0_frm_seq_cpld_av_i[9]) + ); + MUXCY_L com_tlm_u_tlm_tx_vc0_frm_seq_un4_cpld_diff_cry_10 ( + .CI(com_tlm_u_tlm_tx_vc0_frm_seq_un4_cpld_diff_cry_9_2589), + .DI(com_tlm_u_tlm_tx_vc0_frm_seq_VCC_2614), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_un4_cpld_diff_cry_10_2591), + .S(com_tlm_u_tlm_tx_vc0_frm_seq_cpld_av_i[10]) + ); + XORCY com_tlm_u_tlm_tx_vc0_frm_seq_un4_cpld_diff_s_11 ( + .CI(com_tlm_u_tlm_tx_vc0_frm_seq_un4_cpld_diff_cry_10_2591), + .LI(com_tlm_u_tlm_tx_vc0_frm_seq_un4_cpld_diff_s_11_sf_2628), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_un4_cpld_diff_s_11_2590) + ); + MUXCY_L com_tlm_u_tlm_tx_vc0_frm_seq_un4_bnpd_diff_cry_0 ( + .CI(com_tlm_u_tlm_tx_vc0_frm_seq_VCC_2614), + .DI(com_tlm_u_tlm_tx_vc0_frm_seq_npd_av[0]), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_un4_bnpd_diff_cry_0_2592), + .S(com_tlm_u_tlm_tx_vc0_frm_seq_un4_bnpd_diff_axb_0_2657) + ); + MUXCY_L com_tlm_u_tlm_tx_vc0_frm_seq_un4_bnpd_diff_cry_1 ( + .CI(com_tlm_u_tlm_tx_vc0_frm_seq_un4_bnpd_diff_cry_0_2592), + .DI(com_tlm_u_tlm_tx_vc0_frm_seq_npd_av[1]), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_un4_bnpd_diff_cry_1_2593), + .S(com_tlm_u_tlm_tx_vc0_frm_seq_un4_bnpd_diff_axb_1_2656) + ); + MUXCY_L com_tlm_u_tlm_tx_vc0_frm_seq_un4_bnpd_diff_cry_2 ( + .CI(com_tlm_u_tlm_tx_vc0_frm_seq_un4_bnpd_diff_cry_1_2593), + .DI(com_tlm_u_tlm_tx_vc0_frm_seq_npd_av[2]), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_un4_bnpd_diff_cry_2_2594), + .S(com_tlm_u_tlm_tx_vc0_frm_seq_un4_bnpd_diff_axb_2_2655) + ); + MUXCY_L com_tlm_u_tlm_tx_vc0_frm_seq_un4_bnpd_diff_cry_3 ( + .CI(com_tlm_u_tlm_tx_vc0_frm_seq_un4_bnpd_diff_cry_2_2594), + .DI(com_tlm_u_tlm_tx_vc0_frm_seq_npd_av[3]), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_un4_bnpd_diff_cry_3_2595), + .S(com_tlm_u_tlm_tx_vc0_frm_seq_un4_bnpd_diff_axb_3_2654) + ); + MUXCY_L com_tlm_u_tlm_tx_vc0_frm_seq_un4_bnpd_diff_cry_4 ( + .CI(com_tlm_u_tlm_tx_vc0_frm_seq_un4_bnpd_diff_cry_3_2595), + .DI(com_tlm_u_tlm_tx_vc0_frm_seq_npd_av[4]), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_un4_bnpd_diff_cry_4_2596), + .S(com_tlm_u_tlm_tx_vc0_frm_seq_un4_bnpd_diff_axb_4_2653) + ); + MUXCY_L com_tlm_u_tlm_tx_vc0_frm_seq_un4_bnpd_diff_cry_5 ( + .CI(com_tlm_u_tlm_tx_vc0_frm_seq_un4_bnpd_diff_cry_4_2596), + .DI(com_tlm_u_tlm_tx_vc0_frm_seq_npd_av[5]), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_un4_bnpd_diff_cry_5_2597), + .S(com_tlm_u_tlm_tx_vc0_frm_seq_un4_bnpd_diff_axb_5_2652) + ); + MUXCY_L com_tlm_u_tlm_tx_vc0_frm_seq_un4_bnpd_diff_cry_6 ( + .CI(com_tlm_u_tlm_tx_vc0_frm_seq_un4_bnpd_diff_cry_5_2597), + .DI(com_tlm_u_tlm_tx_vc0_frm_seq_VCC_2614), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_un4_bnpd_diff_cry_6_2598), + .S(com_tlm_u_tlm_tx_vc0_frm_seq_un4_bnpd_diff_cry_6_sf_2651) + ); + MUXCY_L com_tlm_u_tlm_tx_vc0_frm_seq_un4_bnpd_diff_cry_7 ( + .CI(com_tlm_u_tlm_tx_vc0_frm_seq_un4_bnpd_diff_cry_6_2598), + .DI(com_tlm_u_tlm_tx_vc0_frm_seq_VCC_2614), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_un4_bnpd_diff_cry_7_2599), + .S(com_tlm_u_tlm_tx_vc0_frm_seq_un4_bnpd_diff_cry_7_sf_2650) + ); + MUXCY_L com_tlm_u_tlm_tx_vc0_frm_seq_un4_bnpd_diff_cry_8 ( + .CI(com_tlm_u_tlm_tx_vc0_frm_seq_un4_bnpd_diff_cry_7_2599), + .DI(com_tlm_u_tlm_tx_vc0_frm_seq_VCC_2614), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_un4_bnpd_diff_cry_8_2600), + .S(com_tlm_u_tlm_tx_vc0_frm_seq_un4_bnpd_diff_cry_8_sf_2649) + ); + MUXCY_L com_tlm_u_tlm_tx_vc0_frm_seq_un4_bnpd_diff_cry_9 ( + .CI(com_tlm_u_tlm_tx_vc0_frm_seq_un4_bnpd_diff_cry_8_2600), + .DI(com_tlm_u_tlm_tx_vc0_frm_seq_VCC_2614), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_un4_bnpd_diff_cry_9_2601), + .S(com_tlm_u_tlm_tx_vc0_frm_seq_un4_bnpd_diff_cry_9_sf_2648) + ); + MUXCY_L com_tlm_u_tlm_tx_vc0_frm_seq_un4_bnpd_diff_cry_10 ( + .CI(com_tlm_u_tlm_tx_vc0_frm_seq_un4_bnpd_diff_cry_9_2601), + .DI(com_tlm_u_tlm_tx_vc0_frm_seq_VCC_2614), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_un4_bnpd_diff_cry_10_2603), + .S(com_tlm_u_tlm_tx_vc0_frm_seq_un4_bnpd_diff_cry_10_sf_2647) + ); + XORCY com_tlm_u_tlm_tx_vc0_frm_seq_un4_bnpd_diff_s_11 ( + .CI(com_tlm_u_tlm_tx_vc0_frm_seq_un4_bnpd_diff_cry_10_2603), + .LI(com_tlm_u_tlm_tx_vc0_frm_seq_un4_bnpd_diff_s_11_sf_2631), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_un4_bnpd_diff_s_11_2602) + ); + MUXCY_L com_tlm_u_tlm_tx_vc0_frm_seq_un4_pd_diff_cry_0 ( + .CI(com_tlm_u_tlm_tx_vc0_frm_seq_VCC_2614), + .DI(com_tlm_u_tlm_tx_vc0_frm_seq_pd_av_0_), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_un4_pd_diff_cry_0_2604), + .S(com_tlm_u_tlm_tx_vc0_frm_seq_un4_pd_diff_axb_0_2646) + ); + MUXCY_L com_tlm_u_tlm_tx_vc0_frm_seq_un4_pd_diff_cry_1 ( + .CI(com_tlm_u_tlm_tx_vc0_frm_seq_un4_pd_diff_cry_0_2604), + .DI(com_tlm_u_tlm_tx_vc0_frm_seq_pd_av_1_), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_un4_pd_diff_cry_1_2605), + .S(com_tlm_u_tlm_tx_vc0_frm_seq_un4_pd_diff_axb_1_2645) + ); + MUXCY_L com_tlm_u_tlm_tx_vc0_frm_seq_un4_pd_diff_cry_2 ( + .CI(com_tlm_u_tlm_tx_vc0_frm_seq_un4_pd_diff_cry_1_2605), + .DI(com_tlm_u_tlm_tx_vc0_frm_seq_pd_av_2_), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_un4_pd_diff_cry_2_2606), + .S(com_tlm_u_tlm_tx_vc0_frm_seq_un4_pd_diff_axb_2_2644) + ); + MUXCY_L com_tlm_u_tlm_tx_vc0_frm_seq_un4_pd_diff_cry_3 ( + .CI(com_tlm_u_tlm_tx_vc0_frm_seq_un4_pd_diff_cry_2_2606), + .DI(com_tlm_u_tlm_tx_vc0_frm_seq_pd_av_3_), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_un4_pd_diff_cry_3_2607), + .S(com_tlm_u_tlm_tx_vc0_frm_seq_un4_pd_diff_axb_3_2643) + ); + MUXCY_L com_tlm_u_tlm_tx_vc0_frm_seq_un4_pd_diff_cry_4 ( + .CI(com_tlm_u_tlm_tx_vc0_frm_seq_un4_pd_diff_cry_3_2607), + .DI(com_tlm_u_tlm_tx_vc0_frm_seq_pd_av_4_), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_un4_pd_diff_cry_4_2608), + .S(com_tlm_u_tlm_tx_vc0_frm_seq_un4_pd_diff_axb_4_2642) + ); + MUXCY_L com_tlm_u_tlm_tx_vc0_frm_seq_un4_pd_diff_cry_5 ( + .CI(com_tlm_u_tlm_tx_vc0_frm_seq_un4_pd_diff_cry_4_2608), + .DI(com_tlm_u_tlm_tx_vc0_frm_seq_pd_av_5_), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_un4_pd_diff_cry_5_2609), + .S(com_tlm_u_tlm_tx_vc0_frm_seq_un4_pd_diff_axb_5_2641) + ); + MUXCY_L com_tlm_u_tlm_tx_vc0_frm_seq_un4_pd_diff_cry_6 ( + .CI(com_tlm_u_tlm_tx_vc0_frm_seq_un4_pd_diff_cry_5_2609), + .DI(com_tlm_u_tlm_tx_vc0_frm_seq_VCC_2614), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_un4_pd_diff_cry_6_2610), + .S(com_tlm_u_tlm_tx_vc0_frm_seq_pd_av_i[6]) + ); + MUXCY_L com_tlm_u_tlm_tx_vc0_frm_seq_un4_pd_diff_cry_7 ( + .CI(com_tlm_u_tlm_tx_vc0_frm_seq_un4_pd_diff_cry_6_2610), + .DI(com_tlm_u_tlm_tx_vc0_frm_seq_VCC_2614), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_un4_pd_diff_cry_7_2611), + .S(com_tlm_u_tlm_tx_vc0_frm_seq_pd_av_i[7]) + ); + MUXCY_L com_tlm_u_tlm_tx_vc0_frm_seq_un4_pd_diff_cry_8 ( + .CI(com_tlm_u_tlm_tx_vc0_frm_seq_un4_pd_diff_cry_7_2611), + .DI(com_tlm_u_tlm_tx_vc0_frm_seq_VCC_2614), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_un4_pd_diff_cry_8_2612), + .S(com_tlm_u_tlm_tx_vc0_frm_seq_pd_av_i[8]) + ); + MUXCY_L com_tlm_u_tlm_tx_vc0_frm_seq_un4_pd_diff_cry_9 ( + .CI(com_tlm_u_tlm_tx_vc0_frm_seq_un4_pd_diff_cry_8_2612), + .DI(com_tlm_u_tlm_tx_vc0_frm_seq_VCC_2614), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_un4_pd_diff_cry_9_2613), + .S(com_tlm_u_tlm_tx_vc0_frm_seq_pd_av_i[9]) + ); + MUXCY_L com_tlm_u_tlm_tx_vc0_frm_seq_un4_pd_diff_cry_10 ( + .CI(com_tlm_u_tlm_tx_vc0_frm_seq_un4_pd_diff_cry_9_2613), + .DI(com_tlm_u_tlm_tx_vc0_frm_seq_VCC_2614), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_un4_pd_diff_cry_10_2616), + .S(com_tlm_u_tlm_tx_vc0_frm_seq_pd_av_i[10]) + ); + XORCY com_tlm_u_tlm_tx_vc0_frm_seq_un4_pd_diff_s_11 ( + .CI(com_tlm_u_tlm_tx_vc0_frm_seq_un4_pd_diff_cry_10_2616), + .LI(com_tlm_u_tlm_tx_vc0_frm_seq_un4_pd_diff_s_11_sf_2630), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_un4_pd_diff_s_11_2615) + ); + FDR com_tlm_u_tlm_tx_vc0_frm_seq_oq_cat_qq_1_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_oq_q[12]), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_oq_cat_qq[1]), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_tx_vc0_frm_seq_oq_cat_qq_0_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_oq_q[11]), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_oq_cat_qq[0]), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_tx_vc0_frm_seq_bq_ren ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_bq_renc_i), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_bq_ren_2620), + .R(plm_link_up_i) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_last_buf_num_match_3_0.INIT = 4'h6; + LUT2 com_tlm_u_tlm_tx_vc0_frm_seq_last_buf_num_match_3_0 ( + .I0(com_tlm_u_tlm_tx_ds_buf_num[0]), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_last_buf_num[0]), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_last_buf_num_match_3_0_2627) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_nxt_queue_state_1_sqmuxa_1_0_a2_0_a4_1.INIT = 4'h2; + LUT2 com_tlm_u_tlm_tx_vc0_frm_seq_nxt_queue_state_1_sqmuxa_1_0_a2_0_a4_1 ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_queue_state[2]), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_sq_wen_2640), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_nxt_queue_state_1_sqmuxa_1_1) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_header_vld_oq_7_u_i_o2.INIT = 4'h4; + LUT2 com_tlm_u_tlm_tx_vc0_frm_seq_header_vld_oq_7_u_i_o2 ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_oq_ren_2617), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_oq_vld), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_N_51001_i) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_bq_holdoff13_0_a2_0_a2_0_a2.INIT = 4'h4; + LUT2 com_tlm_u_tlm_tx_vc0_frm_seq_bq_holdoff13_0_a2_0_a2_0_a2 ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_bq_vld), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_bq_wen_2622), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_bq_holdoff13) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_header_vld_oq_7_u_i_0_0_a2.INIT = 4'h4; + LUT2 com_tlm_u_tlm_tx_vc0_frm_seq_header_vld_oq_7_u_i_0_0_a2 ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_cplh_av), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_oq_q[12]), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_N_49528) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_oq_rdy_u_i_m4_0.INIT = 8'hB8; + LUT3_L com_tlm_u_tlm_tx_vc0_frm_seq_oq_rdy_u_i_m4_0 ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_npd_diff[11]), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_oq_cat_qq[0]), + .I2(com_tlm_u_tlm_tx_vc0_frm_seq_pd_diff[11]), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_N_51066) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_N_41839_i_i.INIT = 4'hE; + LUT2 com_tlm_u_tlm_tx_vc0_frm_seq_N_41839_i_i ( + .I0(com_tlm_u_tlm_tx_am_retry_dst_rdy), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_seq_state[1]), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_N_41839_i_i_2638) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_bq_rdy.INIT = 8'hD0; + LUT3 com_tlm_u_tlm_tx_vc0_frm_seq_bq_rdy ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_bnpd_diff[11]), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_bq_no_payload_qq_2619), + .I2(com_tlm_u_tlm_tx_vc0_frm_seq_header_vld_bq_2618), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_bq_rdy_2636) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_nonposted_vld_oq_3_0_a2_0_a2_0_a2_1.INIT = 8'h08; + LUT3 com_tlm_u_tlm_tx_vc0_frm_seq_nonposted_vld_oq_3_0_a2_0_a2_0_a2_1 ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_N_51001_i), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_av_valid), + .I2(com_tlm_u_tlm_tx_vc0_frm_seq_bq_ren_2620), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_nonposted_vld_oq_3_1) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_header_vld_oq_7_u_i_0_0_a2_2.INIT = 16'h0020; + LUT4 com_tlm_u_tlm_tx_vc0_frm_seq_header_vld_oq_7_u_i_0_0_a2_2 ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_bq_holdoff_2621), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_bq_vld), + .I2(com_tlm_u_tlm_tx_vc0_frm_seq_oq_q[11]), + .I3(com_tlm_u_tlm_tx_vc0_frm_seq_oq_q[12]), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_N_49531) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_reg_ren_bq_wen_14_u_i_0_0_o3.INIT = 8'h10; + LUT3 com_tlm_u_tlm_tx_vc0_frm_seq_reg_ren_bq_wen_14_u_i_0_0_o3 ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_sq_cnt[0]), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_sq_cnt[1]), + .I2(com_tlm_u_tlm_tx_vc0_frm_seq_sq_cnt[2]), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_N_48914_i) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_nxt_queue_state_0_i_0_a4_0_2_.INIT = 8'h04; + LUT3 com_tlm_u_tlm_tx_vc0_frm_seq_nxt_queue_state_0_i_0_a4_0_2_ ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_last_buf_num_match_2635), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_queue_state[3]), + .I2(com_tlm_u_tlm_tx_vc0_frm_seq_sq_wen_2640), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_N_38458) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_reg_ren_oq_ren_12_iv_0_0_0_o2.INIT = 8'h01; + LUT3 com_tlm_u_tlm_tx_vc0_frm_seq_reg_ren_oq_ren_12_iv_0_0_0_o2 ( + .I0(com_link_status[2]), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_bq_wen_2622), + .I2(com_tlm_u_tlm_tx_vc0_frm_seq_sq_wen_2640), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_N_48937_i) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_last_buf_num_match_3_NE_0.INIT = 16'h8421; + LUT4 com_tlm_u_tlm_tx_vc0_frm_seq_last_buf_num_match_3_NE_0 ( + .I0(com_tlm_u_tlm_tx_ds_buf_num[2]), + .I1(com_tlm_u_tlm_tx_ds_buf_num[3]), + .I2(com_tlm_u_tlm_tx_vc0_frm_seq_last_buf_num[2]), + .I3(com_tlm_u_tlm_tx_vc0_frm_seq_last_buf_num[3]), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_last_buf_num_match_3_NE_0_2626) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_un1_seq_state_2_i_0_a2.INIT = 16'hD080; + LUT4 com_tlm_u_tlm_tx_vc0_frm_seq_un1_seq_state_2_i_0_a2 ( + .I0(com_tlm_u_tlm_tx_am_retry_lock), + .I1(com_tlm_u_tlm_tx_am_retry_src_rdy), + .I2(com_tlm_u_tlm_tx_vc0_frm_seq_seq_state[0]), + .I3(com_tlm_u_tlm_tx_vc0_frm_seq_sq_vld), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_N_42588) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_oq_rdy_u_i_m3_0.INIT = 8'hCA; + LUT3_L com_tlm_u_tlm_tx_vc0_frm_seq_oq_rdy_u_i_m3_0 ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_N_51066), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_cpld_diff[11]), + .I2(com_tlm_u_tlm_tx_vc0_frm_seq_oq_cat_qq[1]), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_N_51067) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_nxt_queue_state_0_i_0_a4_1_2_.INIT = 16'h0008; + LUT4 com_tlm_u_tlm_tx_vc0_frm_seq_nxt_queue_state_0_i_0_a4_1_2_ ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_queue_state[1]), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_seq_state[1]), + .I2(com_tlm_u_tlm_tx_vc0_frm_seq_sq_nxt_vld), + .I3(com_tlm_u_tlm_tx_vc0_frm_seq_sq_wen_2640), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_N_38459) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_header_vld_oq_7_u_i_0_0_32086.INIT = 16'hFBF8; + LUT4 com_tlm_u_tlm_tx_vc0_frm_seq_header_vld_oq_7_u_i_0_0_32086 ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_nph_av), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_oq_q[11]), + .I2(com_tlm_u_tlm_tx_vc0_frm_seq_oq_q[12]), + .I3(com_tlm_u_tlm_tx_vc0_frm_seq_ph_av), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_header_vld_oq_7_u_i_0_0_32086_2632) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_un1_seq_state_2_i_a2_0.INIT = 16'h8C00; + LUT4 com_tlm_u_tlm_tx_vc0_frm_seq_un1_seq_state_2_i_a2_0 ( + .I0(com_tlm_u_tlm_tx_vc0_N_17214_i), + .I1(com_tlm_u_tlm_tx_vc0_in_frame), + .I2(com_tlm_u_tlm_tx_vc0_rdata_q_all_5[67]), + .I3(com_tlm_u_tlm_tx_vc0_frm_seq_start_src_rdy), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_N_17291) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_nxt_seq_state_0_sqmuxa_i_o2_i_a2.INIT = 16'h7300; + LUT4 com_tlm_u_tlm_tx_vc0_frm_seq_nxt_seq_state_0_sqmuxa_i_o2_i_a2 ( + .I0(com_tlm_u_tlm_tx_vc0_N_17214_i), + .I1(com_tlm_u_tlm_tx_vc0_in_frame), + .I2(com_tlm_u_tlm_tx_vc0_rdata_q_all_5[67]), + .I3(com_tlm_u_tlm_tx_vc0_frm_seq_start_src_rdy), + .O(com_tlm_u_tlm_tx_vc0_nxt_seq_state_0_sqmuxa_i_o2_i_a2) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_bq_wen_1_sqmuxa_i_0_0_o2.INIT = 8'h04; + LUT3 com_tlm_u_tlm_tx_vc0_frm_seq_bq_wen_1_sqmuxa_i_0_0_o2 ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_N_48914_i), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_N_48937_i), + .I2(com_link_status[1]), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_N_48967_i) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_reg_ren_bq_wen_14_u_i_0_0_0.INIT = 8'hB0; + LUT3 com_tlm_u_tlm_tx_vc0_frm_seq_reg_ren_bq_wen_14_u_i_0_0_0 ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_N_48914_i), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_bq_rdy_2636), + .I2(com_tlm_u_tlm_tx_vc0_frm_seq_nonposted_vld_oq_2625), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_bq_wen_14_u_i_0_0_0) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_oq_rdy_u_i_i_a2.INIT = 8'hC4; + LUT3 com_tlm_u_tlm_tx_vc0_frm_seq_oq_rdy_u_i_i_a2 ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_N_51067), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_header_vld_oq_2624), + .I2(com_tlm_u_tlm_tx_vc0_frm_seq_oq_no_payload_qq_2623), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_oq_rdy_u_i_i_a2_2637) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_reg_ren_consumed_nph_10_iv_0_i_i_o2.INIT = 8'hA8; + LUT3 com_tlm_u_tlm_tx_vc0_frm_seq_reg_ren_consumed_nph_10_iv_0_i_i_o2 ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_N_48967_i), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_oq_rdy_u_i_i_a2_2637), + .I2(com_tlm_u_tlm_tx_vc0_frm_seq_bq_rdy_2636), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_N_49115_i) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_reg_ren_consumed_cplh_10_i_i_a2_i_1.INIT = 16'h0008; + LUT4 com_tlm_u_tlm_tx_vc0_frm_seq_reg_ren_consumed_cplh_10_i_i_a2_i_1 ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_N_48967_i), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_oq_rdy_u_i_i_a2_2637), + .I2(com_tlm_u_tlm_tx_vc0_frm_seq_bq_rdy_2636), + .I3(com_tlm_u_tlm_tx_vc0_frm_seq_oq_q[11]), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_consumed_cplh_10_i_i_a2_i_1) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_reg_ren_oq_ren_12_iv_0_0_0_0.INIT = 16'h0A08; + LUT4_L com_tlm_u_tlm_tx_vc0_frm_seq_reg_ren_oq_ren_12_iv_0_0_0_0 ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_N_48937_i), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_oq_rdy_u_i_i_a2_2637), + .I2(com_link_status[1]), + .I3(com_tlm_u_tlm_tx_vc0_frm_seq_nonposted_vld_oq_2625), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_oq_ren_12_iv_0_0_0_0) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_bq_renc.INIT = 16'h0400; + LUT4_L com_tlm_u_tlm_tx_vc0_frm_seq_bq_renc ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_N_48914_i), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_N_48937_i), + .I2(com_link_status[1]), + .I3(com_tlm_u_tlm_tx_vc0_frm_seq_bq_rdy_2636), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_bq_renc_i) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_reg_ren_consumed_credits_4_i_m3_i_m4_i_m3_0_1_.INIT = 8'hCA; + LUT3_L com_tlm_u_tlm_tx_vc0_frm_seq_reg_ren_consumed_credits_4_i_m3_i_m4_i_m3_0_1_ ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_bq_d[5]), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_bq_q[5]), + .I2(com_tlm_u_tlm_tx_vc0_frm_seq_bq_rdy_2636), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_consumed_credits_4_i_m3_i_m4_i_m3_0[1]) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_reg_ren_consumed_credits_4_i_m3_i_m4_i_m3_0_0_.INIT = 8'hCA; + LUT3_L com_tlm_u_tlm_tx_vc0_frm_seq_reg_ren_consumed_credits_4_i_m3_i_m4_i_m3_0_0_ ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_bq_d[4]), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_bq_q[4]), + .I2(com_tlm_u_tlm_tx_vc0_frm_seq_bq_rdy_2636), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_consumed_credits_4_i_m3_i_m4_i_m3_0[0]) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_reg_ren_sq_d_4_i_m3_i_m4_i_m3_0_3_.INIT = 8'hCA; + LUT3_L com_tlm_u_tlm_tx_vc0_frm_seq_reg_ren_sq_d_4_i_m3_i_m4_i_m3_0_3_ ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_bq_d[3]), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_bq_q[3]), + .I2(com_tlm_u_tlm_tx_vc0_frm_seq_bq_rdy_2636), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_sq_d_4_i_m3_i_m4_i_m3_0[3]) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_reg_ren_sq_d_4_i_m3_i_m4_i_m3_0_2_.INIT = 8'hCA; + LUT3_L com_tlm_u_tlm_tx_vc0_frm_seq_reg_ren_sq_d_4_i_m3_i_m4_i_m3_0_2_ ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_bq_d[2]), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_bq_q[2]), + .I2(com_tlm_u_tlm_tx_vc0_frm_seq_bq_rdy_2636), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_sq_d_4_i_m3_i_m4_i_m3_0[2]) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_reg_ren_sq_d_4_i_m3_i_m4_i_m3_0_1_.INIT = 8'hCA; + LUT3_L com_tlm_u_tlm_tx_vc0_frm_seq_reg_ren_sq_d_4_i_m3_i_m4_i_m3_0_1_ ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_bq_d[1]), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_bq_q[1]), + .I2(com_tlm_u_tlm_tx_vc0_frm_seq_bq_rdy_2636), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_sq_d_4_i_m3_i_m4_i_m3_0[1]) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_reg_ren_sq_d_4_i_m3_i_m4_i_m3_0_0_.INIT = 8'hCA; + LUT3_L com_tlm_u_tlm_tx_vc0_frm_seq_reg_ren_sq_d_4_i_m3_i_m4_i_m3_0_0_ ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_bq_d[0]), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_bq_q[0]), + .I2(com_tlm_u_tlm_tx_vc0_frm_seq_bq_rdy_2636), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_sq_d_4_i_m3_i_m4_i_m3_0[0]) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_reg_ren_consumed_credits_4_i_m3_i_m4_i_m3_0_5_.INIT = 8'hCA; + LUT3_L com_tlm_u_tlm_tx_vc0_frm_seq_reg_ren_consumed_credits_4_i_m3_i_m4_i_m3_0_5_ ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_bq_d[9]), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_bq_q[9]), + .I2(com_tlm_u_tlm_tx_vc0_frm_seq_bq_rdy_2636), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_consumed_credits_4_i_m3_i_m4_i_m3_0[5]) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_reg_ren_consumed_credits_4_i_m3_i_m4_i_m3_0_4_.INIT = 8'hCA; + LUT3_L com_tlm_u_tlm_tx_vc0_frm_seq_reg_ren_consumed_credits_4_i_m3_i_m4_i_m3_0_4_ ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_bq_d[8]), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_bq_q[8]), + .I2(com_tlm_u_tlm_tx_vc0_frm_seq_bq_rdy_2636), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_consumed_credits_4_i_m3_i_m4_i_m3_0[4]) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_reg_ren_consumed_credits_4_i_m3_i_m4_i_m3_0_3_.INIT = 8'hCA; + LUT3_L com_tlm_u_tlm_tx_vc0_frm_seq_reg_ren_consumed_credits_4_i_m3_i_m4_i_m3_0_3_ ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_bq_d[7]), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_bq_q[7]), + .I2(com_tlm_u_tlm_tx_vc0_frm_seq_bq_rdy_2636), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_consumed_credits_4_i_m3_i_m4_i_m3_0[3]) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_reg_ren_consumed_credits_4_i_m3_i_m4_i_m3_0_2_.INIT = 8'hCA; + LUT3_L com_tlm_u_tlm_tx_vc0_frm_seq_reg_ren_consumed_credits_4_i_m3_i_m4_i_m3_0_2_ ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_bq_d[6]), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_bq_q[6]), + .I2(com_tlm_u_tlm_tx_vc0_frm_seq_bq_rdy_2636), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_consumed_credits_4_i_m3_i_m4_i_m3_0[2]) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_start_buf_o_2_i_m2_i_m2_i_m3_0_3_.INIT = 8'hD8; + LUT3_L com_tlm_u_tlm_tx_vc0_frm_seq_start_buf_o_2_i_m2_i_m2_i_m3_0_3_ ( + .I0(com_tlm_u_tlm_tx_am_retry_dst_rdy), + .I1(com_tlm_u_tlm_tx_freed_buf[3]), + .I2(com_tlm_u_tlm_tx_vc0_frm_seq_sq_q[3]), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_start_buf_o_2_i_m2_i_m2_i_m3_0[3]) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_start_buf_o_2_i_m2_i_m2_i_m3_0_2_.INIT = 8'hD8; + LUT3_L com_tlm_u_tlm_tx_vc0_frm_seq_start_buf_o_2_i_m2_i_m2_i_m3_0_2_ ( + .I0(com_tlm_u_tlm_tx_am_retry_dst_rdy), + .I1(com_tlm_u_tlm_tx_freed_buf[2]), + .I2(com_tlm_u_tlm_tx_vc0_frm_seq_sq_q[2]), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_start_buf_o_2_i_m2_i_m2_i_m3_0[2]) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_start_buf_o_2_i_m2_i_m2_i_m3_0_1_.INIT = 8'hD8; + LUT3_L com_tlm_u_tlm_tx_vc0_frm_seq_start_buf_o_2_i_m2_i_m2_i_m3_0_1_ ( + .I0(com_tlm_u_tlm_tx_am_retry_dst_rdy), + .I1(com_tlm_u_tlm_tx_freed_buf[1]), + .I2(com_tlm_u_tlm_tx_vc0_frm_seq_sq_q[1]), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_start_buf_o_2_i_m2_i_m2_i_m3_0[1]) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_start_buf_o_2_i_m2_i_m2_i_m3_0_0_.INIT = 8'hD8; + LUT3_L com_tlm_u_tlm_tx_vc0_frm_seq_start_buf_o_2_i_m2_i_m2_i_m3_0_0_ ( + .I0(com_tlm_u_tlm_tx_am_retry_dst_rdy), + .I1(com_tlm_u_tlm_tx_freed_buf[0]), + .I2(com_tlm_u_tlm_tx_vc0_frm_seq_sq_q[0]), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_start_buf_o_2_i_m2_i_m2_i_m3_0[0]) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_last_buf_num_match_3_NE.INIT = 16'h0900; + LUT4_L com_tlm_u_tlm_tx_vc0_frm_seq_last_buf_num_match_3_NE ( + .I0(com_tlm_u_tlm_tx_ds_buf_num[1]), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_last_buf_num[1]), + .I2(com_tlm_u_tlm_tx_vc0_frm_seq_last_buf_num_match_3_0_2627), + .I3(com_tlm_u_tlm_tx_vc0_frm_seq_last_buf_num_match_3_NE_0_2626), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_last_buf_num_match_3) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_header_vld_bq_3_0_a2_0_a2_0_a2.INIT = 16'h0080; + LUT4_L com_tlm_u_tlm_tx_vc0_frm_seq_header_vld_bq_3_0_a2_0_a2_0_a2 ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_av_valid), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_bq_vld), + .I2(com_tlm_u_tlm_tx_vc0_frm_seq_nph_av), + .I3(com_tlm_u_tlm_tx_vc0_frm_seq_sq_wen_2640), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_header_vld_bq_3) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_nonposted_vld_oq_3_0_a2_0_a2_0_a2.INIT = 8'h08; + LUT3_L com_tlm_u_tlm_tx_vc0_frm_seq_nonposted_vld_oq_3_0_a2_0_a2_0_a2 ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_nonposted_vld_oq_3_1), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_oq_q[11]), + .I2(com_tlm_u_tlm_tx_vc0_frm_seq_oq_q[12]), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_nonposted_vld_oq_3) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_un4_cpld_diff_s_11_sf.INIT = 4'h1; + LUT1_L com_tlm_u_tlm_tx_vc0_frm_seq_un4_cpld_diff_s_11_sf ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_cpld_av_11_), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_un4_cpld_diff_s_11_sf_2628) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_un4_npd_diff_s_11_sf.INIT = 4'h1; + LUT1_L com_tlm_u_tlm_tx_vc0_frm_seq_un4_npd_diff_s_11_sf ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_npd_av[11]), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_un4_npd_diff_s_11_sf_2629) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_un4_pd_diff_s_11_sf.INIT = 4'h1; + LUT1_L com_tlm_u_tlm_tx_vc0_frm_seq_un4_pd_diff_s_11_sf ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_pd_av_11_), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_un4_pd_diff_s_11_sf_2630) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_un4_bnpd_diff_s_11_sf.INIT = 4'h1; + LUT1_L com_tlm_u_tlm_tx_vc0_frm_seq_un4_bnpd_diff_s_11_sf ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_npd_av[11]), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_un4_bnpd_diff_s_11_sf_2631) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_header_vld_oq_7_u_i_0_0.INIT = 16'h1000; + LUT4_L com_tlm_u_tlm_tx_vc0_frm_seq_header_vld_oq_7_u_i_0_0 ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_N_49528), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_N_49531), + .I2(com_tlm_u_tlm_tx_vc0_frm_seq_header_vld_oq_7_u_i_0_0_32086_2632), + .I3(com_tlm_u_tlm_tx_vc0_frm_seq_nonposted_vld_oq_3_1), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_N_13932_i) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_N_42589_i.INIT = 8'hFE; + LUT3_L com_tlm_u_tlm_tx_vc0_frm_seq_N_42589_i ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_N_17291), + .I1(com_tlm_u_tlm_tx_am_retry_dst_rdy), + .I2(com_tlm_u_tlm_tx_vc0_frm_seq_seq_state[1]), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_N_42589_i_2633) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_nxt_seq_state_0_sqmuxa_1_0_a3_0_a2_0_a2.INIT = 8'h80; + LUT3_L com_tlm_u_tlm_tx_vc0_frm_seq_nxt_seq_state_0_sqmuxa_1_0_a3_0_a2_0_a2 ( + .I0(com_tlm_u_tlm_tx_am_retry_lock), + .I1(com_tlm_u_tlm_tx_am_retry_src_rdy), + .I2(com_tlm_u_tlm_tx_vc0_frm_seq_seq_state[0]), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_nxt_seq_state_0_sqmuxa_1) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_nxt_seq_state_0_sqmuxa_2_0_a3_0_a2_0_a2.INIT = 8'h40; + LUT3_L com_tlm_u_tlm_tx_vc0_frm_seq_nxt_seq_state_0_sqmuxa_2_0_a3_0_a2_0_a2 ( + .I0(com_tlm_u_tlm_tx_am_retry_lock), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_seq_state[0]), + .I2(com_tlm_u_tlm_tx_vc0_frm_seq_sq_vld), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_nxt_seq_state_0_sqmuxa_2) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_un1_seq_state_2_i_0.INIT = 16'h0001; + LUT4_L com_tlm_u_tlm_tx_vc0_frm_seq_un1_seq_state_2_i_0 ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_N_17291), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_N_42588), + .I2(com_tlm_u_tlm_tx_am_retry_dst_rdy), + .I3(com_tlm_u_tlm_tx_vc0_frm_seq_seq_state[1]), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_N_17156_i) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_reg_ren_consumed_cplh_10_i_i_a2_i.INIT = 4'h8; + LUT2_L com_tlm_u_tlm_tx_vc0_frm_seq_reg_ren_consumed_cplh_10_i_i_a2_i ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_consumed_cplh_10_i_i_a2_i_1), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_oq_q[12]), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_N_48356_i) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_reg_ren_consumed_ph_10_i_i_a2_i.INIT = 4'h2; + LUT2_L com_tlm_u_tlm_tx_vc0_frm_seq_reg_ren_consumed_ph_10_i_i_a2_i ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_consumed_cplh_10_i_i_a2_i_1), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_oq_q[12]), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_N_48358_i) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_N_67885_i.INIT = 16'hEFEE; + LUT4_L com_tlm_u_tlm_tx_vc0_frm_seq_N_67885_i ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_N_38458), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_N_38459), + .I2(com_tlm_u_tlm_tx_ds_buf_src_rdy), + .I3(com_tlm_u_tlm_tx_vc0_frm_seq_nxt_queue_state_1_sqmuxa_1_1), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_N_67885_i_2634) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_nxt_queue_state_0_0_0_1_.INIT = 16'hFFA2; + LUT4_L com_tlm_u_tlm_tx_vc0_frm_seq_nxt_queue_state_0_0_0_1_ ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_queue_state[1]), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_seq_state[1]), + .I2(com_tlm_u_tlm_tx_vc0_frm_seq_sq_nxt_vld), + .I3(com_tlm_u_tlm_tx_vc0_frm_seq_sq_wen_2640), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_N_8943_i) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_nxt_queue_state_0_i_0_i_0_.INIT = 16'h00EC; + LUT4_L com_tlm_u_tlm_tx_vc0_frm_seq_nxt_queue_state_0_i_0_i_0_ ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_last_buf_num_match_2635), + .I1(com_tlm_u_tlm_tx_queue_state[0]), + .I2(com_tlm_u_tlm_tx_vc0_frm_seq_queue_state[3]), + .I3(com_tlm_u_tlm_tx_vc0_frm_seq_sq_wen_2640), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_N_40766_i) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_reg_ren_bq_wen_14_u_i_0_0.INIT = 16'h0200; + LUT4_L com_tlm_u_tlm_tx_vc0_frm_seq_reg_ren_bq_wen_14_u_i_0_0 ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_N_48937_i), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_oq_rdy_u_i_i_a2_2637), + .I2(com_link_status[1]), + .I3(com_tlm_u_tlm_tx_vc0_frm_seq_bq_wen_14_u_i_0_0_0), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_N_13930_i) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_reg_ren_consumed_nph_10_iv_0_i_i.INIT = 16'h88A8; + LUT4_L com_tlm_u_tlm_tx_vc0_frm_seq_reg_ren_consumed_nph_10_iv_0_i_i ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_N_49115_i), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_bq_rdy_2636), + .I2(com_tlm_u_tlm_tx_vc0_frm_seq_oq_q[11]), + .I3(com_tlm_u_tlm_tx_vc0_frm_seq_oq_q[12]), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_N_48333_i) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_reg_ren_oq_ren_12_iv_0_0_0.INIT = 16'h2700; + LUT4_L com_tlm_u_tlm_tx_vc0_frm_seq_reg_ren_oq_ren_12_iv_0_0_0 ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_N_48914_i), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_oq_rdy_u_i_i_a2_2637), + .I2(com_tlm_u_tlm_tx_vc0_frm_seq_bq_rdy_2636), + .I3(com_tlm_u_tlm_tx_vc0_frm_seq_oq_ren_12_iv_0_0_0_0), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_N_8842_i) + ); + FD com_tlm_u_tlm_tx_vc0_frm_seq_consumed_credits_1_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_consumed_credits_4_i_m3_i_m4_i_m3_0[1]), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_consumed_credits[1]) + ); + FD com_tlm_u_tlm_tx_vc0_frm_seq_consumed_credits_0_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_consumed_credits_4_i_m3_i_m4_i_m3_0[0]), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_consumed_credits[0]) + ); + FD com_tlm_u_tlm_tx_vc0_frm_seq_sq_d_3_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_sq_d_4_i_m3_i_m4_i_m3_0[3]), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_sq_d[3]) + ); + FD com_tlm_u_tlm_tx_vc0_frm_seq_sq_d_2_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_sq_d_4_i_m3_i_m4_i_m3_0[2]), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_sq_d[2]) + ); + FD com_tlm_u_tlm_tx_vc0_frm_seq_sq_d_1_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_sq_d_4_i_m3_i_m4_i_m3_0[1]), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_sq_d[1]) + ); + FD com_tlm_u_tlm_tx_vc0_frm_seq_sq_d_0_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_sq_d_4_i_m3_i_m4_i_m3_0[0]), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_sq_d[0]) + ); + FD com_tlm_u_tlm_tx_vc0_frm_seq_consumed_credits_5_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_consumed_credits_4_i_m3_i_m4_i_m3_0[5]), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_consumed_credits[5]) + ); + FD com_tlm_u_tlm_tx_vc0_frm_seq_consumed_credits_4_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_consumed_credits_4_i_m3_i_m4_i_m3_0[4]), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_consumed_credits[4]) + ); + FD com_tlm_u_tlm_tx_vc0_frm_seq_consumed_credits_3_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_consumed_credits_4_i_m3_i_m4_i_m3_0[3]), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_consumed_credits[3]) + ); + FD com_tlm_u_tlm_tx_vc0_frm_seq_consumed_credits_2_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_consumed_credits_4_i_m3_i_m4_i_m3_0[2]), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_consumed_credits[2]) + ); + FDE com_tlm_u_tlm_tx_vc0_frm_seq_start_retry_tsn_o_11_ ( + .CE(com_tlm_u_tlm_tx_am_retry_dst_rdy), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_am_retry_tsn[11]), + .Q(com_tlm_u_tlm_tx_vc0_start_retry_tsn[11]) + ); + FDE com_tlm_u_tlm_tx_vc0_frm_seq_start_retry_tsn_o_10_ ( + .CE(com_tlm_u_tlm_tx_am_retry_dst_rdy), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_am_retry_tsn[10]), + .Q(com_tlm_u_tlm_tx_vc0_start_retry_tsn[10]) + ); + FDE com_tlm_u_tlm_tx_vc0_frm_seq_start_retry_tsn_o_9_ ( + .CE(com_tlm_u_tlm_tx_am_retry_dst_rdy), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_am_retry_tsn[9]), + .Q(com_tlm_u_tlm_tx_vc0_start_retry_tsn[9]) + ); + FDE com_tlm_u_tlm_tx_vc0_frm_seq_start_retry_tsn_o_8_ ( + .CE(com_tlm_u_tlm_tx_am_retry_dst_rdy), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_am_retry_tsn[8]), + .Q(com_tlm_u_tlm_tx_vc0_start_retry_tsn[8]) + ); + FDE com_tlm_u_tlm_tx_vc0_frm_seq_start_retry_tsn_o_7_ ( + .CE(com_tlm_u_tlm_tx_am_retry_dst_rdy), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_am_retry_tsn[7]), + .Q(com_tlm_u_tlm_tx_vc0_start_retry_tsn[7]) + ); + FDE com_tlm_u_tlm_tx_vc0_frm_seq_start_retry_tsn_o_6_ ( + .CE(com_tlm_u_tlm_tx_am_retry_dst_rdy), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_am_retry_tsn[6]), + .Q(com_tlm_u_tlm_tx_vc0_start_retry_tsn[6]) + ); + FDE com_tlm_u_tlm_tx_vc0_frm_seq_start_retry_tsn_o_5_ ( + .CE(com_tlm_u_tlm_tx_am_retry_dst_rdy), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_am_retry_tsn[5]), + .Q(com_tlm_u_tlm_tx_vc0_start_retry_tsn[5]) + ); + FDE com_tlm_u_tlm_tx_vc0_frm_seq_start_retry_tsn_o_4_ ( + .CE(com_tlm_u_tlm_tx_am_retry_dst_rdy), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_am_retry_tsn[4]), + .Q(com_tlm_u_tlm_tx_vc0_start_retry_tsn[4]) + ); + FDE com_tlm_u_tlm_tx_vc0_frm_seq_start_retry_tsn_o_3_ ( + .CE(com_tlm_u_tlm_tx_am_retry_dst_rdy), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_am_retry_tsn[3]), + .Q(com_tlm_u_tlm_tx_vc0_start_retry_tsn[3]) + ); + FDE com_tlm_u_tlm_tx_vc0_frm_seq_start_retry_tsn_o_2_ ( + .CE(com_tlm_u_tlm_tx_am_retry_dst_rdy), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_am_retry_tsn[2]), + .Q(com_tlm_u_tlm_tx_vc0_start_retry_tsn[2]) + ); + FDE com_tlm_u_tlm_tx_vc0_frm_seq_start_retry_tsn_o_1_ ( + .CE(com_tlm_u_tlm_tx_am_retry_dst_rdy), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_am_retry_tsn[1]), + .Q(com_tlm_u_tlm_tx_vc0_start_retry_tsn[1]) + ); + FDE com_tlm_u_tlm_tx_vc0_frm_seq_start_retry_tsn_o_0_ ( + .CE(com_tlm_u_tlm_tx_am_retry_dst_rdy), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_am_retry_tsn[0]), + .Q(com_tlm_u_tlm_tx_vc0_start_retry_tsn[0]) + ); + FDE com_tlm_u_tlm_tx_vc0_frm_seq_start_buf_o_3_ ( + .CE(com_tlm_u_tlm_tx_vc0_frm_seq_N_41839_i_i_2638), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_start_buf_o_2_i_m2_i_m2_i_m3_0[3]), + .Q(com_tlm_u_tlm_tx_vc0_start_buf_num[3]) + ); + FDE com_tlm_u_tlm_tx_vc0_frm_seq_start_buf_o_2_ ( + .CE(com_tlm_u_tlm_tx_vc0_frm_seq_N_41839_i_i_2638), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_start_buf_o_2_i_m2_i_m2_i_m3_0[2]), + .Q(com_tlm_u_tlm_tx_vc0_start_buf_num[2]) + ); + FDE com_tlm_u_tlm_tx_vc0_frm_seq_start_buf_o_1_ ( + .CE(com_tlm_u_tlm_tx_vc0_frm_seq_N_41839_i_i_2638), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_start_buf_o_2_i_m2_i_m2_i_m3_0[1]), + .Q(com_tlm_u_tlm_tx_vc0_start_buf_num[1]) + ); + FDE com_tlm_u_tlm_tx_vc0_frm_seq_start_buf_o_0_ ( + .CE(com_tlm_u_tlm_tx_vc0_frm_seq_N_41839_i_i_2638), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_start_buf_o_2_i_m2_i_m2_i_m3_0[0]), + .Q(com_tlm_u_tlm_tx_vc0_start_buf_num[0]) + ); + INV com_tlm_u_tlm_tx_vc0_frm_seq_N_51001_i_i ( + .I(com_tlm_u_tlm_tx_vc0_frm_seq_N_51001_i), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_N_51001_i_i_2639) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_nxt_queue_state_1_sqmuxa_1_0_a2_0_a4.INIT = 8'h20; + LUT3_L com_tlm_u_tlm_tx_vc0_frm_seq_nxt_queue_state_1_sqmuxa_1_0_a2_0_a4 ( + .I0(com_tlm_u_tlm_tx_ds_buf_src_rdy), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_sq_wen_2640), + .I2(com_tlm_u_tlm_tx_vc0_frm_seq_queue_state[2]), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_nxt_queue_state_1_sqmuxa_1) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_un4_pd_diff_axb_5.INIT = 4'h9; + LUT2 com_tlm_u_tlm_tx_vc0_frm_seq_un4_pd_diff_axb_5 ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_bq_d[9]), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_pd_av_5_), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_un4_pd_diff_axb_5_2641) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_un4_pd_diff_axb_4.INIT = 4'h9; + LUT2 com_tlm_u_tlm_tx_vc0_frm_seq_un4_pd_diff_axb_4 ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_bq_d[8]), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_pd_av_4_), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_un4_pd_diff_axb_4_2642) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_un4_pd_diff_axb_3.INIT = 4'h9; + LUT2 com_tlm_u_tlm_tx_vc0_frm_seq_un4_pd_diff_axb_3 ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_bq_d[7]), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_pd_av_3_), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_un4_pd_diff_axb_3_2643) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_un4_pd_diff_axb_2.INIT = 4'h9; + LUT2 com_tlm_u_tlm_tx_vc0_frm_seq_un4_pd_diff_axb_2 ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_bq_d[6]), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_pd_av_2_), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_un4_pd_diff_axb_2_2644) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_un4_pd_diff_axb_1.INIT = 4'h9; + LUT2 com_tlm_u_tlm_tx_vc0_frm_seq_un4_pd_diff_axb_1 ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_bq_d[5]), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_pd_av_1_), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_un4_pd_diff_axb_1_2645) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_un4_pd_diff_axb_0.INIT = 4'h9; + LUT2 com_tlm_u_tlm_tx_vc0_frm_seq_un4_pd_diff_axb_0 ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_bq_d[4]), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_pd_av_0_), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_un4_pd_diff_axb_0_2646) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_un4_bnpd_diff_cry_10_sf.INIT = 4'h1; + LUT1 com_tlm_u_tlm_tx_vc0_frm_seq_un4_bnpd_diff_cry_10_sf ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_npd_av[10]), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_un4_bnpd_diff_cry_10_sf_2647) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_un4_bnpd_diff_cry_9_sf.INIT = 4'h1; + LUT1 com_tlm_u_tlm_tx_vc0_frm_seq_un4_bnpd_diff_cry_9_sf ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_npd_av[9]), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_un4_bnpd_diff_cry_9_sf_2648) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_un4_bnpd_diff_cry_8_sf.INIT = 4'h1; + LUT1 com_tlm_u_tlm_tx_vc0_frm_seq_un4_bnpd_diff_cry_8_sf ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_npd_av[8]), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_un4_bnpd_diff_cry_8_sf_2649) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_un4_bnpd_diff_cry_7_sf.INIT = 4'h1; + LUT1 com_tlm_u_tlm_tx_vc0_frm_seq_un4_bnpd_diff_cry_7_sf ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_npd_av[7]), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_un4_bnpd_diff_cry_7_sf_2650) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_un4_bnpd_diff_cry_6_sf.INIT = 4'h1; + LUT1 com_tlm_u_tlm_tx_vc0_frm_seq_un4_bnpd_diff_cry_6_sf ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_npd_av[6]), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_un4_bnpd_diff_cry_6_sf_2651) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_un4_bnpd_diff_axb_5.INIT = 4'h9; + LUT2 com_tlm_u_tlm_tx_vc0_frm_seq_un4_bnpd_diff_axb_5 ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_bq_q[9]), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_npd_av[5]), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_un4_bnpd_diff_axb_5_2652) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_un4_bnpd_diff_axb_4.INIT = 4'h9; + LUT2 com_tlm_u_tlm_tx_vc0_frm_seq_un4_bnpd_diff_axb_4 ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_bq_q[8]), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_npd_av[4]), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_un4_bnpd_diff_axb_4_2653) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_un4_bnpd_diff_axb_3.INIT = 4'h9; + LUT2 com_tlm_u_tlm_tx_vc0_frm_seq_un4_bnpd_diff_axb_3 ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_bq_q[7]), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_npd_av[3]), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_un4_bnpd_diff_axb_3_2654) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_un4_bnpd_diff_axb_2.INIT = 4'h9; + LUT2 com_tlm_u_tlm_tx_vc0_frm_seq_un4_bnpd_diff_axb_2 ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_bq_q[6]), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_npd_av[2]), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_un4_bnpd_diff_axb_2_2655) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_un4_bnpd_diff_axb_1.INIT = 4'h9; + LUT2 com_tlm_u_tlm_tx_vc0_frm_seq_un4_bnpd_diff_axb_1 ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_bq_q[5]), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_npd_av[1]), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_un4_bnpd_diff_axb_1_2656) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_un4_bnpd_diff_axb_0.INIT = 4'h9; + LUT2 com_tlm_u_tlm_tx_vc0_frm_seq_un4_bnpd_diff_axb_0 ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_bq_q[4]), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_npd_av[0]), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_un4_bnpd_diff_axb_0_2657) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_un4_cpld_diff_axb_5.INIT = 4'h9; + LUT2 com_tlm_u_tlm_tx_vc0_frm_seq_un4_cpld_diff_axb_5 ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_bq_d[9]), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_cpld_av_5_), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_un4_cpld_diff_axb_5_2658) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_un4_cpld_diff_axb_4.INIT = 4'h9; + LUT2 com_tlm_u_tlm_tx_vc0_frm_seq_un4_cpld_diff_axb_4 ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_bq_d[8]), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_cpld_av_4_), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_un4_cpld_diff_axb_4_2659) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_un4_cpld_diff_axb_3.INIT = 4'h9; + LUT2 com_tlm_u_tlm_tx_vc0_frm_seq_un4_cpld_diff_axb_3 ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_bq_d[7]), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_cpld_av_3_), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_un4_cpld_diff_axb_3_2660) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_un4_cpld_diff_axb_2.INIT = 4'h9; + LUT2 com_tlm_u_tlm_tx_vc0_frm_seq_un4_cpld_diff_axb_2 ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_bq_d[6]), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_cpld_av_2_), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_un4_cpld_diff_axb_2_2661) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_un4_cpld_diff_axb_1.INIT = 4'h9; + LUT2 com_tlm_u_tlm_tx_vc0_frm_seq_un4_cpld_diff_axb_1 ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_bq_d[5]), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_cpld_av_1_), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_un4_cpld_diff_axb_1_2662) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_un4_cpld_diff_axb_0.INIT = 4'h9; + LUT2 com_tlm_u_tlm_tx_vc0_frm_seq_un4_cpld_diff_axb_0 ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_bq_d[4]), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_cpld_av_0_), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_un4_cpld_diff_axb_0_2663) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_un4_npd_diff_axb_5.INIT = 4'h9; + LUT2 com_tlm_u_tlm_tx_vc0_frm_seq_un4_npd_diff_axb_5 ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_bq_d[9]), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_npd_av[5]), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_un4_npd_diff_axb_5_2664) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_un4_npd_diff_axb_4.INIT = 4'h9; + LUT2 com_tlm_u_tlm_tx_vc0_frm_seq_un4_npd_diff_axb_4 ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_bq_d[8]), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_npd_av[4]), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_un4_npd_diff_axb_4_2665) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_un4_npd_diff_axb_3.INIT = 4'h9; + LUT2 com_tlm_u_tlm_tx_vc0_frm_seq_un4_npd_diff_axb_3 ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_bq_d[7]), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_npd_av[3]), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_un4_npd_diff_axb_3_2666) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_un4_npd_diff_axb_2.INIT = 4'h9; + LUT2 com_tlm_u_tlm_tx_vc0_frm_seq_un4_npd_diff_axb_2 ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_bq_d[6]), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_npd_av[2]), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_un4_npd_diff_axb_2_2667) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_un4_npd_diff_axb_1.INIT = 4'h9; + LUT2 com_tlm_u_tlm_tx_vc0_frm_seq_un4_npd_diff_axb_1 ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_bq_d[5]), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_npd_av[1]), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_un4_npd_diff_axb_1_2668) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_un4_npd_diff_axb_0.INIT = 4'h9; + LUT2 com_tlm_u_tlm_tx_vc0_frm_seq_un4_npd_diff_axb_0 ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_bq_d[4]), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_npd_av[0]), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_un4_npd_diff_axb_0_2669) + ); + GND com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_GND ( + .G(com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_GND_2670) + ); + SRLC16E com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_srlrow_0__srlcol_0__srlinst ( + .CE(com_tlm_u_tlm_tx_vc0_frame_vld), + .D(com_tlm_u_tlm_tx_vc0_tkn_buf_num[0]), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_shift_tap[0]), + .CLK(NlwRenamedSig_OI_trn_clk), + .Q15(NLW_com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_srlrow_0__srlcol_0__srlinst_Q15_UNCONNECTED), + .A0(com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_raddr_lo[0]), + .A1(com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_raddr_lo[1]), + .A2(com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_raddr_lo[2]), + .A3(com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_raddr_lo[3]) + ); + SRLC16E com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_srlrow_0__srlcol_9__srlinst ( + .CE(com_tlm_u_tlm_tx_vc0_frame_vld), + .D(com_tlm_u_tlm_tx_vc0_credits[5]), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_shift_tap[9]), + .CLK(NlwRenamedSig_OI_trn_clk), + .Q15(NLW_com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_srlrow_0__srlcol_9__srlinst_Q15_UNCONNECTED), + .A0(com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_raddr_lo[0]), + .A1(com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_raddr_lo[1]), + .A2(com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_raddr_lo[2]), + .A3(com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_raddr_lo[3]) + ); + SRLC16E com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_srlrow_0__srlcol_5__srlinst ( + .CE(com_tlm_u_tlm_tx_vc0_frame_vld), + .D(com_tlm_u_tlm_tx_vc0_credits[1]), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_shift_tap[5]), + .CLK(NlwRenamedSig_OI_trn_clk), + .Q15(NLW_com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_srlrow_0__srlcol_5__srlinst_Q15_UNCONNECTED), + .A0(com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_raddr_lo[0]), + .A1(com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_raddr_lo[1]), + .A2(com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_raddr_lo[2]), + .A3(com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_raddr_lo[3]) + ); + SRLC16E com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_srlrow_0__srlcol_1__srlinst ( + .CE(com_tlm_u_tlm_tx_vc0_frame_vld), + .D(com_tlm_u_tlm_tx_vc0_tkn_buf_num[1]), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_shift_tap[1]), + .CLK(NlwRenamedSig_OI_trn_clk), + .Q15(NLW_com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_srlrow_0__srlcol_1__srlinst_Q15_UNCONNECTED), + .A0(com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_raddr_lo[0]), + .A1(com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_raddr_lo[1]), + .A2(com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_raddr_lo[2]), + .A3(com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_raddr_lo[3]) + ); + SRLC16E com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_srlrow_0__srlcol_10__srlinst ( + .CE(com_tlm_u_tlm_tx_vc0_frame_vld), + .D(com_tlm_u_tlm_tx_vc0_no_payload), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_shift_tap[10]), + .CLK(NlwRenamedSig_OI_trn_clk), + .Q15(NLW_com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_srlrow_0__srlcol_10__srlinst_Q15_UNCONNECTED), + .A0(com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_raddr_lo[0]), + .A1(com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_raddr_lo[1]), + .A2(com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_raddr_lo[2]), + .A3(com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_raddr_lo[3]) + ); + SRLC16E com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_srlrow_0__srlcol_6__srlinst ( + .CE(com_tlm_u_tlm_tx_vc0_frame_vld), + .D(com_tlm_u_tlm_tx_vc0_credits[2]), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_shift_tap[6]), + .CLK(NlwRenamedSig_OI_trn_clk), + .Q15(NLW_com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_srlrow_0__srlcol_6__srlinst_Q15_UNCONNECTED), + .A0(com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_raddr_lo[0]), + .A1(com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_raddr_lo[1]), + .A2(com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_raddr_lo[2]), + .A3(com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_raddr_lo[3]) + ); + SRLC16E com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_srlrow_0__srlcol_2__srlinst ( + .CE(com_tlm_u_tlm_tx_vc0_frame_vld), + .D(com_tlm_u_tlm_tx_vc0_tkn_buf_num[2]), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_shift_tap[2]), + .CLK(NlwRenamedSig_OI_trn_clk), + .Q15(NLW_com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_srlrow_0__srlcol_2__srlinst_Q15_UNCONNECTED), + .A0(com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_raddr_lo[0]), + .A1(com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_raddr_lo[1]), + .A2(com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_raddr_lo[2]), + .A3(com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_raddr_lo[3]) + ); + SRLC16E com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_srlrow_0__srlcol_11__srlinst ( + .CE(com_tlm_u_tlm_tx_vc0_frame_vld), + .D(com_tlm_u_tlm_tx_vc0_cat[0]), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_shift_tap[11]), + .CLK(NlwRenamedSig_OI_trn_clk), + .Q15(NLW_com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_srlrow_0__srlcol_11__srlinst_Q15_UNCONNECTED), + .A0(com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_raddr_lo[0]), + .A1(com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_raddr_lo[1]), + .A2(com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_raddr_lo[2]), + .A3(com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_raddr_lo[3]) + ); + SRLC16E com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_srlrow_0__srlcol_7__srlinst ( + .CE(com_tlm_u_tlm_tx_vc0_frame_vld), + .D(com_tlm_u_tlm_tx_vc0_credits[3]), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_shift_tap[7]), + .CLK(NlwRenamedSig_OI_trn_clk), + .Q15(NLW_com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_srlrow_0__srlcol_7__srlinst_Q15_UNCONNECTED), + .A0(com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_raddr_lo[0]), + .A1(com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_raddr_lo[1]), + .A2(com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_raddr_lo[2]), + .A3(com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_raddr_lo[3]) + ); + SRLC16E com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_srlrow_0__srlcol_3__srlinst ( + .CE(com_tlm_u_tlm_tx_vc0_frame_vld), + .D(com_tlm_u_tlm_tx_vc0_tkn_buf_num[3]), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_shift_tap[3]), + .CLK(NlwRenamedSig_OI_trn_clk), + .Q15(NLW_com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_srlrow_0__srlcol_3__srlinst_Q15_UNCONNECTED), + .A0(com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_raddr_lo[0]), + .A1(com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_raddr_lo[1]), + .A2(com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_raddr_lo[2]), + .A3(com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_raddr_lo[3]) + ); + SRLC16E com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_srlrow_0__srlcol_12__srlinst ( + .CE(com_tlm_u_tlm_tx_vc0_frame_vld), + .D(com_tlm_u_tlm_tx_vc0_cat[1]), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_shift_tap[12]), + .CLK(NlwRenamedSig_OI_trn_clk), + .Q15(NLW_com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_srlrow_0__srlcol_12__srlinst_Q15_UNCONNECTED), + .A0(com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_raddr_lo[0]), + .A1(com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_raddr_lo[1]), + .A2(com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_raddr_lo[2]), + .A3(com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_raddr_lo[3]) + ); + SRLC16E com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_srlrow_0__srlcol_8__srlinst ( + .CE(com_tlm_u_tlm_tx_vc0_frame_vld), + .D(com_tlm_u_tlm_tx_vc0_credits[4]), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_shift_tap[8]), + .CLK(NlwRenamedSig_OI_trn_clk), + .Q15(NLW_com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_srlrow_0__srlcol_8__srlinst_Q15_UNCONNECTED), + .A0(com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_raddr_lo[0]), + .A1(com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_raddr_lo[1]), + .A2(com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_raddr_lo[2]), + .A3(com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_raddr_lo[3]) + ); + SRLC16E com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_srlrow_0__srlcol_4__srlinst ( + .CE(com_tlm_u_tlm_tx_vc0_frame_vld), + .D(com_tlm_u_tlm_tx_vc0_credits[0]), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_shift_tap[4]), + .CLK(NlwRenamedSig_OI_trn_clk), + .Q15(NLW_com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_srlrow_0__srlcol_4__srlinst_Q15_UNCONNECTED), + .A0(com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_raddr_lo[0]), + .A1(com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_raddr_lo[1]), + .A2(com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_raddr_lo[2]), + .A3(com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_raddr_lo[3]) + ); + FDS com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_raddr_lo_0_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_un1_raddr_lo_1_axb_0_2674), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_raddr_lo[0]), + .S(plm_link_up_i) + ); + FDS com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_raddr_lo_1_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_un1_raddr_lo_1_s_1_1), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_raddr_lo[1]), + .S(plm_link_up_i) + ); + FDS com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_raddr_lo_2_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_un1_raddr_lo_1_s_2_1), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_raddr_lo[2]), + .S(plm_link_up_i) + ); + FDS com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_raddr_lo_3_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_un1_raddr_lo_1_s_3_1), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_raddr_lo[3]), + .S(plm_link_up_i) + ); + FDRE com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_nxt_vld_o ( + .CE(com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_N_68484_i_2675), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_srl_wen), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_nxt_vld_o_1), + .R(plm_link_up_i) + ); + FDRE com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_vld_o ( + .CE(com_tlm_u_tlm_tx_vc0_frm_seq_N_51001_i_i_2639), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_N_50019_i_2677), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_oq_vld), + .R(plm_link_up_i) + ); + MUXCY_L com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_un1_raddr_lo_1_cry_0 ( + .CI(com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_GND_2670), + .DI(com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_raddr_lo[0]), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_un1_raddr_lo_1_cry_0_2671), + .S(com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_un1_raddr_lo_1_axb_0_2674) + ); + MUXCY_L com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_un1_raddr_lo_1_cry_1 ( + .CI(com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_un1_raddr_lo_1_cry_0_2671), + .DI(com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_raddr_lo[1]), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_un1_raddr_lo_1_cry_1_2672), + .S(com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_un1_raddr_lo_1_axb_1_2680) + ); + XORCY com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_un1_raddr_lo_1_s_1 ( + .CI(com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_un1_raddr_lo_1_cry_0_2671), + .LI(com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_un1_raddr_lo_1_axb_1_2680), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_un1_raddr_lo_1_s_1_1) + ); + MUXCY_L com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_un1_raddr_lo_1_cry_2 ( + .CI(com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_un1_raddr_lo_1_cry_1_2672), + .DI(com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_raddr_lo[2]), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_un1_raddr_lo_1_cry_2_2673), + .S(com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_un1_raddr_lo_1_axb_2_2679) + ); + XORCY com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_un1_raddr_lo_1_s_2 ( + .CI(com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_un1_raddr_lo_1_cry_1_2672), + .LI(com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_un1_raddr_lo_1_axb_2_2679), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_un1_raddr_lo_1_s_2_1) + ); + XORCY com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_un1_raddr_lo_1_s_3 ( + .CI(com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_un1_raddr_lo_1_cry_2_2673), + .LI(com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_un1_raddr_lo_1_axb_3_2678), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_un1_raddr_lo_1_s_3_1) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_un1_bkp_i_1_i_0_0_0_a2_0_2.INIT = 16'h0001; + LUT4 com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_un1_bkp_i_1_i_0_0_0_a2_0_2 ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_raddr_lo[0]), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_raddr_lo[1]), + .I2(com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_raddr_lo[2]), + .I3(com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_raddr_lo[3]), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_un1_bkp_i_1_i_0_0_0_a2_0_2_2676) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_un1_bkp_i_1_i_0_0_0_a2.INIT = 8'hC8; + LUT3 com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_un1_bkp_i_1_i_0_0_0_a2 ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_N_51001_i), + .I1(com_tlm_u_tlm_tx_vc0_frame_vld), + .I2(com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_nxt_vld_o_1), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_srl_wen) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_un1_raddr_lo_1_axb_0.INIT = 16'h6978; + LUT4 com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_un1_raddr_lo_1_axb_0 ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_N_51001_i), + .I1(com_tlm_u_tlm_tx_vc0_frame_vld), + .I2(com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_raddr_lo[0]), + .I3(com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_nxt_vld_o_1), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_un1_raddr_lo_1_axb_0_2674) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_N_68484_i.INIT = 8'hDC; + LUT3 com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_N_68484_i ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_N_51001_i), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_srl_wen), + .I2(com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_un1_bkp_i_1_i_0_0_0_a2_0_2_2676), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_N_68484_i_2675) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_N_50019_i.INIT = 4'hE; + LUT2_L com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_N_50019_i ( + .I0(com_tlm_u_tlm_tx_vc0_frame_vld), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_nxt_vld_o_1), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_N_50019_i_2677) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_data_bits_d_o_14_0_i_m3_i_m4_i_m3_0_12_.INIT = 8'hCA; + LUT3_L com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_data_bits_d_o_14_0_i_m3_i_m4_i_m3_0_12_ ( + .I0(com_tlm_u_tlm_tx_vc0_cat[1]), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_shift_tap[12]), + .I2(com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_nxt_vld_o_1), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_d_o_14_0_i_m3_i_m4_i_m3_0[12]) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_data_bits_d_o_14_0_i_m3_i_m4_i_m3_0_11_.INIT = 8'hCA; + LUT3_L com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_data_bits_d_o_14_0_i_m3_i_m4_i_m3_0_11_ ( + .I0(com_tlm_u_tlm_tx_vc0_cat[0]), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_shift_tap[11]), + .I2(com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_nxt_vld_o_1), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_d_o_14_0_i_m3_i_m4_i_m3_0[11]) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_data_bits_d_o_14_0_i_m3_i_m4_i_m3_0_10_.INIT = 8'hB8; + LUT3_L com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_data_bits_d_o_14_0_i_m3_i_m4_i_m3_0_10_ ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_shift_tap[10]), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_nxt_vld_o_1), + .I2(com_tlm_u_tlm_tx_vc0_no_payload), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_d_o_14_0_i_m3_i_m4_i_m3_0[10]) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_data_bits_d_o_14_0_i_m3_i_m4_i_m3_0_9_.INIT = 8'hCA; + LUT3_L com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_data_bits_d_o_14_0_i_m3_i_m4_i_m3_0_9_ ( + .I0(com_tlm_u_tlm_tx_vc0_credits[5]), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_shift_tap[9]), + .I2(com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_nxt_vld_o_1), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_d_o_14_0_i_m3_i_m4_i_m3_0[9]) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_data_bits_d_o_14_0_i_m3_i_m4_i_m3_0_8_.INIT = 8'hCA; + LUT3_L com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_data_bits_d_o_14_0_i_m3_i_m4_i_m3_0_8_ ( + .I0(com_tlm_u_tlm_tx_vc0_credits[4]), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_shift_tap[8]), + .I2(com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_nxt_vld_o_1), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_d_o_14_0_i_m3_i_m4_i_m3_0[8]) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_data_bits_d_o_14_0_i_m3_i_m4_i_m3_0_7_.INIT = 8'hCA; + LUT3_L com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_data_bits_d_o_14_0_i_m3_i_m4_i_m3_0_7_ ( + .I0(com_tlm_u_tlm_tx_vc0_credits[3]), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_shift_tap[7]), + .I2(com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_nxt_vld_o_1), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_d_o_14_0_i_m3_i_m4_i_m3_0[7]) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_data_bits_d_o_14_0_i_m3_i_m4_i_m3_0_6_.INIT = 8'hCA; + LUT3_L com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_data_bits_d_o_14_0_i_m3_i_m4_i_m3_0_6_ ( + .I0(com_tlm_u_tlm_tx_vc0_credits[2]), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_shift_tap[6]), + .I2(com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_nxt_vld_o_1), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_d_o_14_0_i_m3_i_m4_i_m3_0[6]) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_data_bits_d_o_14_0_i_m3_i_m4_i_m3_0_5_.INIT = 8'hCA; + LUT3_L com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_data_bits_d_o_14_0_i_m3_i_m4_i_m3_0_5_ ( + .I0(com_tlm_u_tlm_tx_vc0_credits[1]), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_shift_tap[5]), + .I2(com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_nxt_vld_o_1), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_d_o_14_0_i_m3_i_m4_i_m3_0[5]) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_data_bits_d_o_14_0_i_m3_i_m4_i_m3_0_4_.INIT = 8'hCA; + LUT3_L com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_data_bits_d_o_14_0_i_m3_i_m4_i_m3_0_4_ ( + .I0(com_tlm_u_tlm_tx_vc0_credits[0]), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_shift_tap[4]), + .I2(com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_nxt_vld_o_1), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_d_o_14_0_i_m3_i_m4_i_m3_0[4]) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_data_bits_d_o_14_0_i_m3_i_m4_i_m3_0_3_.INIT = 8'hB8; + LUT3_L com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_data_bits_d_o_14_0_i_m3_i_m4_i_m3_0_3_ ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_shift_tap[3]), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_nxt_vld_o_1), + .I2(com_tlm_u_tlm_tx_vc0_tkn_buf_num[3]), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_d_o_14_0_i_m3_i_m4_i_m3_0[3]) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_data_bits_d_o_14_0_i_m3_i_m4_i_m3_0_2_.INIT = 8'hB8; + LUT3_L com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_data_bits_d_o_14_0_i_m3_i_m4_i_m3_0_2_ ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_shift_tap[2]), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_nxt_vld_o_1), + .I2(com_tlm_u_tlm_tx_vc0_tkn_buf_num[2]), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_d_o_14_0_i_m3_i_m4_i_m3_0[2]) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_data_bits_d_o_14_0_i_m3_i_m4_i_m3_0_1_.INIT = 8'hB8; + LUT3_L com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_data_bits_d_o_14_0_i_m3_i_m4_i_m3_0_1_ ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_shift_tap[1]), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_nxt_vld_o_1), + .I2(com_tlm_u_tlm_tx_vc0_tkn_buf_num[1]), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_d_o_14_0_i_m3_i_m4_i_m3_0[1]) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_data_bits_d_o_14_0_i_m3_i_m4_i_m3_0_0_.INIT = 8'hB8; + LUT3_L com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_data_bits_d_o_14_0_i_m3_i_m4_i_m3_0_0_ ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_shift_tap[0]), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_nxt_vld_o_1), + .I2(com_tlm_u_tlm_tx_vc0_tkn_buf_num[0]), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_d_o_14_0_i_m3_i_m4_i_m3_0[0]) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_un1_raddr_lo_1_axb_3.INIT = 16'hE1F0; + LUT4_L com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_un1_raddr_lo_1_axb_3 ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_N_51001_i), + .I1(com_tlm_u_tlm_tx_vc0_frame_vld), + .I2(com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_raddr_lo[3]), + .I3(com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_nxt_vld_o_1), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_un1_raddr_lo_1_axb_3_2678) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_un1_raddr_lo_1_axb_2.INIT = 16'hE1F0; + LUT4_L com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_un1_raddr_lo_1_axb_2 ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_N_51001_i), + .I1(com_tlm_u_tlm_tx_vc0_frame_vld), + .I2(com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_raddr_lo[2]), + .I3(com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_nxt_vld_o_1), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_un1_raddr_lo_1_axb_2_2679) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_un1_raddr_lo_1_axb_1.INIT = 16'hE1F0; + LUT4_L com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_un1_raddr_lo_1_axb_1 ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_N_51001_i), + .I1(com_tlm_u_tlm_tx_vc0_frame_vld), + .I2(com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_raddr_lo[1]), + .I3(com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_nxt_vld_o_1), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_un1_raddr_lo_1_axb_1_2680) + ); + FDE com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_d_o_12_ ( + .CE(com_tlm_u_tlm_tx_vc0_frm_seq_N_51001_i_i_2639), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_d_o_14_0_i_m3_i_m4_i_m3_0[12]), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_oq_q[12]) + ); + FDE com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_d_o_11_ ( + .CE(com_tlm_u_tlm_tx_vc0_frm_seq_N_51001_i_i_2639), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_d_o_14_0_i_m3_i_m4_i_m3_0[11]), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_oq_q[11]) + ); + FDE com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_d_o_10_ ( + .CE(com_tlm_u_tlm_tx_vc0_frm_seq_N_51001_i_i_2639), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_d_o_14_0_i_m3_i_m4_i_m3_0[10]), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_bq_d[10]) + ); + FDE com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_d_o_9_ ( + .CE(com_tlm_u_tlm_tx_vc0_frm_seq_N_51001_i_i_2639), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_d_o_14_0_i_m3_i_m4_i_m3_0[9]), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_bq_d[9]) + ); + FDE com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_d_o_8_ ( + .CE(com_tlm_u_tlm_tx_vc0_frm_seq_N_51001_i_i_2639), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_d_o_14_0_i_m3_i_m4_i_m3_0[8]), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_bq_d[8]) + ); + FDE com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_d_o_7_ ( + .CE(com_tlm_u_tlm_tx_vc0_frm_seq_N_51001_i_i_2639), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_d_o_14_0_i_m3_i_m4_i_m3_0[7]), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_bq_d[7]) + ); + FDE com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_d_o_6_ ( + .CE(com_tlm_u_tlm_tx_vc0_frm_seq_N_51001_i_i_2639), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_d_o_14_0_i_m3_i_m4_i_m3_0[6]), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_bq_d[6]) + ); + FDE com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_d_o_5_ ( + .CE(com_tlm_u_tlm_tx_vc0_frm_seq_N_51001_i_i_2639), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_d_o_14_0_i_m3_i_m4_i_m3_0[5]), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_bq_d[5]) + ); + FDE com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_d_o_4_ ( + .CE(com_tlm_u_tlm_tx_vc0_frm_seq_N_51001_i_i_2639), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_d_o_14_0_i_m3_i_m4_i_m3_0[4]), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_bq_d[4]) + ); + FDE com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_d_o_3_ ( + .CE(com_tlm_u_tlm_tx_vc0_frm_seq_N_51001_i_i_2639), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_d_o_14_0_i_m3_i_m4_i_m3_0[3]), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_bq_d[3]) + ); + FDE com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_d_o_2_ ( + .CE(com_tlm_u_tlm_tx_vc0_frm_seq_N_51001_i_i_2639), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_d_o_14_0_i_m3_i_m4_i_m3_0[2]), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_bq_d[2]) + ); + FDE com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_d_o_1_ ( + .CE(com_tlm_u_tlm_tx_vc0_frm_seq_N_51001_i_i_2639), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_d_o_14_0_i_m3_i_m4_i_m3_0[1]), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_bq_d[1]) + ); + FDE com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_d_o_0_ ( + .CE(com_tlm_u_tlm_tx_vc0_frm_seq_N_51001_i_i_2639), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_d_o_14_0_i_m3_i_m4_i_m3_0[0]), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_bq_d[0]) + ); + GND com_tlm_u_tlm_tx_vc0_frm_seq_bq_fifo_GND ( + .G(com_tlm_u_tlm_tx_vc0_frm_seq_bq_fifo_GND_2681) + ); + SRLC16E com_tlm_u_tlm_tx_vc0_frm_seq_bq_fifo_srlrow_0__srlcol_0__srlinst ( + .CE(com_tlm_u_tlm_tx_vc0_frm_seq_bq_wen_2622), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_bq_d[0]), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_bq_fifo_shift_tap[0]), + .CLK(NlwRenamedSig_OI_trn_clk), + .Q15(NLW_com_tlm_u_tlm_tx_vc0_frm_seq_bq_fifo_srlrow_0__srlcol_0__srlinst_Q15_UNCONNECTED), + .A0(com_tlm_u_tlm_tx_vc0_frm_seq_bq_fifo_raddr_lo[0]), + .A1(com_tlm_u_tlm_tx_vc0_frm_seq_bq_fifo_raddr_lo[1]), + .A2(com_tlm_u_tlm_tx_vc0_frm_seq_bq_fifo_raddr_lo[2]), + .A3(com_tlm_u_tlm_tx_vc0_frm_seq_bq_fifo_raddr_lo[3]) + ); + SRLC16E com_tlm_u_tlm_tx_vc0_frm_seq_bq_fifo_srlrow_0__srlcol_5__srlinst ( + .CE(com_tlm_u_tlm_tx_vc0_frm_seq_bq_wen_2622), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_bq_d[5]), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_bq_fifo_shift_tap[5]), + .CLK(NlwRenamedSig_OI_trn_clk), + .Q15(NLW_com_tlm_u_tlm_tx_vc0_frm_seq_bq_fifo_srlrow_0__srlcol_5__srlinst_Q15_UNCONNECTED), + .A0(com_tlm_u_tlm_tx_vc0_frm_seq_bq_fifo_raddr_lo[0]), + .A1(com_tlm_u_tlm_tx_vc0_frm_seq_bq_fifo_raddr_lo[1]), + .A2(com_tlm_u_tlm_tx_vc0_frm_seq_bq_fifo_raddr_lo[2]), + .A3(com_tlm_u_tlm_tx_vc0_frm_seq_bq_fifo_raddr_lo[3]) + ); + SRLC16E com_tlm_u_tlm_tx_vc0_frm_seq_bq_fifo_srlrow_0__srlcol_9__srlinst ( + .CE(com_tlm_u_tlm_tx_vc0_frm_seq_bq_wen_2622), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_bq_d[9]), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_bq_fifo_shift_tap[9]), + .CLK(NlwRenamedSig_OI_trn_clk), + .Q15(NLW_com_tlm_u_tlm_tx_vc0_frm_seq_bq_fifo_srlrow_0__srlcol_9__srlinst_Q15_UNCONNECTED), + .A0(com_tlm_u_tlm_tx_vc0_frm_seq_bq_fifo_raddr_lo[0]), + .A1(com_tlm_u_tlm_tx_vc0_frm_seq_bq_fifo_raddr_lo[1]), + .A2(com_tlm_u_tlm_tx_vc0_frm_seq_bq_fifo_raddr_lo[2]), + .A3(com_tlm_u_tlm_tx_vc0_frm_seq_bq_fifo_raddr_lo[3]) + ); + SRLC16E com_tlm_u_tlm_tx_vc0_frm_seq_bq_fifo_srlrow_0__srlcol_10__srlinst ( + .CE(com_tlm_u_tlm_tx_vc0_frm_seq_bq_wen_2622), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_bq_d[10]), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_bq_fifo_shift_tap[10]), + .CLK(NlwRenamedSig_OI_trn_clk), + .Q15(NLW_com_tlm_u_tlm_tx_vc0_frm_seq_bq_fifo_srlrow_0__srlcol_10__srlinst_Q15_UNCONNECTED), + .A0(com_tlm_u_tlm_tx_vc0_frm_seq_bq_fifo_raddr_lo[0]), + .A1(com_tlm_u_tlm_tx_vc0_frm_seq_bq_fifo_raddr_lo[1]), + .A2(com_tlm_u_tlm_tx_vc0_frm_seq_bq_fifo_raddr_lo[2]), + .A3(com_tlm_u_tlm_tx_vc0_frm_seq_bq_fifo_raddr_lo[3]) + ); + SRLC16E com_tlm_u_tlm_tx_vc0_frm_seq_bq_fifo_srlrow_0__srlcol_6__srlinst ( + .CE(com_tlm_u_tlm_tx_vc0_frm_seq_bq_wen_2622), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_bq_d[6]), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_bq_fifo_shift_tap[6]), + .CLK(NlwRenamedSig_OI_trn_clk), + .Q15(NLW_com_tlm_u_tlm_tx_vc0_frm_seq_bq_fifo_srlrow_0__srlcol_6__srlinst_Q15_UNCONNECTED), + .A0(com_tlm_u_tlm_tx_vc0_frm_seq_bq_fifo_raddr_lo[0]), + .A1(com_tlm_u_tlm_tx_vc0_frm_seq_bq_fifo_raddr_lo[1]), + .A2(com_tlm_u_tlm_tx_vc0_frm_seq_bq_fifo_raddr_lo[2]), + .A3(com_tlm_u_tlm_tx_vc0_frm_seq_bq_fifo_raddr_lo[3]) + ); + SRLC16E com_tlm_u_tlm_tx_vc0_frm_seq_bq_fifo_srlrow_0__srlcol_7__srlinst ( + .CE(com_tlm_u_tlm_tx_vc0_frm_seq_bq_wen_2622), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_bq_d[7]), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_bq_fifo_shift_tap[7]), + .CLK(NlwRenamedSig_OI_trn_clk), + .Q15(NLW_com_tlm_u_tlm_tx_vc0_frm_seq_bq_fifo_srlrow_0__srlcol_7__srlinst_Q15_UNCONNECTED), + .A0(com_tlm_u_tlm_tx_vc0_frm_seq_bq_fifo_raddr_lo[0]), + .A1(com_tlm_u_tlm_tx_vc0_frm_seq_bq_fifo_raddr_lo[1]), + .A2(com_tlm_u_tlm_tx_vc0_frm_seq_bq_fifo_raddr_lo[2]), + .A3(com_tlm_u_tlm_tx_vc0_frm_seq_bq_fifo_raddr_lo[3]) + ); + SRLC16E com_tlm_u_tlm_tx_vc0_frm_seq_bq_fifo_srlrow_0__srlcol_4__srlinst ( + .CE(com_tlm_u_tlm_tx_vc0_frm_seq_bq_wen_2622), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_bq_d[4]), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_bq_fifo_shift_tap[4]), + .CLK(NlwRenamedSig_OI_trn_clk), + .Q15(NLW_com_tlm_u_tlm_tx_vc0_frm_seq_bq_fifo_srlrow_0__srlcol_4__srlinst_Q15_UNCONNECTED), + .A0(com_tlm_u_tlm_tx_vc0_frm_seq_bq_fifo_raddr_lo[0]), + .A1(com_tlm_u_tlm_tx_vc0_frm_seq_bq_fifo_raddr_lo[1]), + .A2(com_tlm_u_tlm_tx_vc0_frm_seq_bq_fifo_raddr_lo[2]), + .A3(com_tlm_u_tlm_tx_vc0_frm_seq_bq_fifo_raddr_lo[3]) + ); + SRLC16E com_tlm_u_tlm_tx_vc0_frm_seq_bq_fifo_srlrow_0__srlcol_3__srlinst ( + .CE(com_tlm_u_tlm_tx_vc0_frm_seq_bq_wen_2622), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_bq_d[3]), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_bq_fifo_shift_tap[3]), + .CLK(NlwRenamedSig_OI_trn_clk), + .Q15(NLW_com_tlm_u_tlm_tx_vc0_frm_seq_bq_fifo_srlrow_0__srlcol_3__srlinst_Q15_UNCONNECTED), + .A0(com_tlm_u_tlm_tx_vc0_frm_seq_bq_fifo_raddr_lo[0]), + .A1(com_tlm_u_tlm_tx_vc0_frm_seq_bq_fifo_raddr_lo[1]), + .A2(com_tlm_u_tlm_tx_vc0_frm_seq_bq_fifo_raddr_lo[2]), + .A3(com_tlm_u_tlm_tx_vc0_frm_seq_bq_fifo_raddr_lo[3]) + ); + SRLC16E com_tlm_u_tlm_tx_vc0_frm_seq_bq_fifo_srlrow_0__srlcol_8__srlinst ( + .CE(com_tlm_u_tlm_tx_vc0_frm_seq_bq_wen_2622), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_bq_d[8]), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_bq_fifo_shift_tap[8]), + .CLK(NlwRenamedSig_OI_trn_clk), + .Q15(NLW_com_tlm_u_tlm_tx_vc0_frm_seq_bq_fifo_srlrow_0__srlcol_8__srlinst_Q15_UNCONNECTED), + .A0(com_tlm_u_tlm_tx_vc0_frm_seq_bq_fifo_raddr_lo[0]), + .A1(com_tlm_u_tlm_tx_vc0_frm_seq_bq_fifo_raddr_lo[1]), + .A2(com_tlm_u_tlm_tx_vc0_frm_seq_bq_fifo_raddr_lo[2]), + .A3(com_tlm_u_tlm_tx_vc0_frm_seq_bq_fifo_raddr_lo[3]) + ); + SRLC16E com_tlm_u_tlm_tx_vc0_frm_seq_bq_fifo_srlrow_0__srlcol_1__srlinst ( + .CE(com_tlm_u_tlm_tx_vc0_frm_seq_bq_wen_2622), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_bq_d[1]), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_bq_fifo_shift_tap[1]), + .CLK(NlwRenamedSig_OI_trn_clk), + .Q15(NLW_com_tlm_u_tlm_tx_vc0_frm_seq_bq_fifo_srlrow_0__srlcol_1__srlinst_Q15_UNCONNECTED), + .A0(com_tlm_u_tlm_tx_vc0_frm_seq_bq_fifo_raddr_lo[0]), + .A1(com_tlm_u_tlm_tx_vc0_frm_seq_bq_fifo_raddr_lo[1]), + .A2(com_tlm_u_tlm_tx_vc0_frm_seq_bq_fifo_raddr_lo[2]), + .A3(com_tlm_u_tlm_tx_vc0_frm_seq_bq_fifo_raddr_lo[3]) + ); + SRLC16E com_tlm_u_tlm_tx_vc0_frm_seq_bq_fifo_srlrow_0__srlcol_2__srlinst ( + .CE(com_tlm_u_tlm_tx_vc0_frm_seq_bq_wen_2622), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_bq_d[2]), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_bq_fifo_shift_tap[2]), + .CLK(NlwRenamedSig_OI_trn_clk), + .Q15(NLW_com_tlm_u_tlm_tx_vc0_frm_seq_bq_fifo_srlrow_0__srlcol_2__srlinst_Q15_UNCONNECTED), + .A0(com_tlm_u_tlm_tx_vc0_frm_seq_bq_fifo_raddr_lo[0]), + .A1(com_tlm_u_tlm_tx_vc0_frm_seq_bq_fifo_raddr_lo[1]), + .A2(com_tlm_u_tlm_tx_vc0_frm_seq_bq_fifo_raddr_lo[2]), + .A3(com_tlm_u_tlm_tx_vc0_frm_seq_bq_fifo_raddr_lo[3]) + ); + FDS com_tlm_u_tlm_tx_vc0_frm_seq_bq_fifo_raddr_lo_0_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_bq_fifo_un1_raddr_lo_1_axb_0_2687), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_bq_fifo_raddr_lo[0]), + .S(plm_link_up_i) + ); + FDS com_tlm_u_tlm_tx_vc0_frm_seq_bq_fifo_raddr_lo_1_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_bq_fifo_un1_raddr_lo_1_s_1_2), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_bq_fifo_raddr_lo[1]), + .S(plm_link_up_i) + ); + FDS com_tlm_u_tlm_tx_vc0_frm_seq_bq_fifo_raddr_lo_2_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_bq_fifo_un1_raddr_lo_1_s_2_2), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_bq_fifo_raddr_lo[2]), + .S(plm_link_up_i) + ); + FDS com_tlm_u_tlm_tx_vc0_frm_seq_bq_fifo_raddr_lo_3_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_bq_fifo_un1_raddr_lo_1_s_3_2), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_bq_fifo_raddr_lo[3]), + .S(plm_link_up_i) + ); + FDRE com_tlm_u_tlm_tx_vc0_frm_seq_bq_fifo_nxt_vld_o ( + .CE(com_tlm_u_tlm_tx_vc0_frm_seq_bq_fifo_N_69265_i_2685), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_bq_wen_2622), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_bq_fifo_nxt_vld_o_0), + .R(plm_link_up_i) + ); + FDRE com_tlm_u_tlm_tx_vc0_frm_seq_bq_fifo_vld_o ( + .CE(com_tlm_u_tlm_tx_vc0_frm_seq_bq_fifo_N_48886_i_i_2691), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_bq_fifo_nxt_vld_o_0), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_bq_vld), + .R(plm_link_up_i) + ); + MUXCY_L com_tlm_u_tlm_tx_vc0_frm_seq_bq_fifo_un1_raddr_lo_1_cry_0 ( + .CI(com_tlm_u_tlm_tx_vc0_frm_seq_bq_fifo_GND_2681), + .DI(com_tlm_u_tlm_tx_vc0_frm_seq_bq_fifo_raddr_lo[0]), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_bq_fifo_un1_raddr_lo_1_cry_0_2682), + .S(com_tlm_u_tlm_tx_vc0_frm_seq_bq_fifo_un1_raddr_lo_1_axb_0_2687) + ); + MUXCY_L com_tlm_u_tlm_tx_vc0_frm_seq_bq_fifo_un1_raddr_lo_1_cry_1 ( + .CI(com_tlm_u_tlm_tx_vc0_frm_seq_bq_fifo_un1_raddr_lo_1_cry_0_2682), + .DI(com_tlm_u_tlm_tx_vc0_frm_seq_bq_fifo_raddr_lo[1]), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_bq_fifo_un1_raddr_lo_1_cry_1_2683), + .S(com_tlm_u_tlm_tx_vc0_frm_seq_bq_fifo_un1_raddr_lo_1_axb_1_2690) + ); + XORCY com_tlm_u_tlm_tx_vc0_frm_seq_bq_fifo_un1_raddr_lo_1_s_1 ( + .CI(com_tlm_u_tlm_tx_vc0_frm_seq_bq_fifo_un1_raddr_lo_1_cry_0_2682), + .LI(com_tlm_u_tlm_tx_vc0_frm_seq_bq_fifo_un1_raddr_lo_1_axb_1_2690), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_bq_fifo_un1_raddr_lo_1_s_1_2) + ); + MUXCY_L com_tlm_u_tlm_tx_vc0_frm_seq_bq_fifo_un1_raddr_lo_1_cry_2 ( + .CI(com_tlm_u_tlm_tx_vc0_frm_seq_bq_fifo_un1_raddr_lo_1_cry_1_2683), + .DI(com_tlm_u_tlm_tx_vc0_frm_seq_bq_fifo_raddr_lo[2]), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_bq_fifo_un1_raddr_lo_1_cry_2_2684), + .S(com_tlm_u_tlm_tx_vc0_frm_seq_bq_fifo_un1_raddr_lo_1_axb_2_2689) + ); + XORCY com_tlm_u_tlm_tx_vc0_frm_seq_bq_fifo_un1_raddr_lo_1_s_2 ( + .CI(com_tlm_u_tlm_tx_vc0_frm_seq_bq_fifo_un1_raddr_lo_1_cry_1_2683), + .LI(com_tlm_u_tlm_tx_vc0_frm_seq_bq_fifo_un1_raddr_lo_1_axb_2_2689), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_bq_fifo_un1_raddr_lo_1_s_2_2) + ); + XORCY com_tlm_u_tlm_tx_vc0_frm_seq_bq_fifo_un1_raddr_lo_1_s_3 ( + .CI(com_tlm_u_tlm_tx_vc0_frm_seq_bq_fifo_un1_raddr_lo_1_cry_2_2684), + .LI(com_tlm_u_tlm_tx_vc0_frm_seq_bq_fifo_un1_raddr_lo_1_axb_3_2688), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_bq_fifo_un1_raddr_lo_1_s_3_2) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_bq_fifo_un1_bkp_i_1_i_0_0_0_0_o3.INIT = 4'h4; + LUT2 com_tlm_u_tlm_tx_vc0_frm_seq_bq_fifo_un1_bkp_i_1_i_0_0_0_0_o3 ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_bq_ren_2620), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_bq_vld), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_bq_fifo_N_48886_i) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_bq_fifo_un1_bkp_i_1_i_0_0_0_0_a2_2.INIT = 16'h0001; + LUT4 com_tlm_u_tlm_tx_vc0_frm_seq_bq_fifo_un1_bkp_i_1_i_0_0_0_0_a2_2 ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_bq_fifo_raddr_lo[0]), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_bq_fifo_raddr_lo[1]), + .I2(com_tlm_u_tlm_tx_vc0_frm_seq_bq_fifo_raddr_lo[2]), + .I3(com_tlm_u_tlm_tx_vc0_frm_seq_bq_fifo_raddr_lo[3]), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_bq_fifo_un1_bkp_i_1_i_0_0_0_0_a2_2_2686) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_bq_fifo_N_69265_i.INIT = 8'hF4; + LUT3 com_tlm_u_tlm_tx_vc0_frm_seq_bq_fifo_N_69265_i ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_bq_fifo_N_48886_i), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_bq_fifo_un1_bkp_i_1_i_0_0_0_0_a2_2_2686), + .I2(com_tlm_u_tlm_tx_vc0_frm_seq_bq_wen_2622), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_bq_fifo_N_69265_i_2685) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_bq_fifo_un1_raddr_lo_1_axb_0.INIT = 16'h693C; + LUT4 com_tlm_u_tlm_tx_vc0_frm_seq_bq_fifo_un1_raddr_lo_1_axb_0 ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_bq_fifo_N_48886_i), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_bq_fifo_raddr_lo[0]), + .I2(com_tlm_u_tlm_tx_vc0_frm_seq_bq_wen_2622), + .I3(com_tlm_u_tlm_tx_vc0_frm_seq_bq_fifo_nxt_vld_o_0), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_bq_fifo_un1_raddr_lo_1_axb_0_2687) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_bq_fifo_un1_raddr_lo_1_axb_3.INIT = 16'hC9CC; + LUT4_L com_tlm_u_tlm_tx_vc0_frm_seq_bq_fifo_un1_raddr_lo_1_axb_3 ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_bq_fifo_N_48886_i), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_bq_fifo_raddr_lo[3]), + .I2(com_tlm_u_tlm_tx_vc0_frm_seq_bq_wen_2622), + .I3(com_tlm_u_tlm_tx_vc0_frm_seq_bq_fifo_nxt_vld_o_0), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_bq_fifo_un1_raddr_lo_1_axb_3_2688) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_bq_fifo_un1_raddr_lo_1_axb_2.INIT = 16'hC9CC; + LUT4_L com_tlm_u_tlm_tx_vc0_frm_seq_bq_fifo_un1_raddr_lo_1_axb_2 ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_bq_fifo_N_48886_i), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_bq_fifo_raddr_lo[2]), + .I2(com_tlm_u_tlm_tx_vc0_frm_seq_bq_wen_2622), + .I3(com_tlm_u_tlm_tx_vc0_frm_seq_bq_fifo_nxt_vld_o_0), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_bq_fifo_un1_raddr_lo_1_axb_2_2689) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_bq_fifo_un1_raddr_lo_1_axb_1.INIT = 16'hC9CC; + LUT4_L com_tlm_u_tlm_tx_vc0_frm_seq_bq_fifo_un1_raddr_lo_1_axb_1 ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_bq_fifo_N_48886_i), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_bq_fifo_raddr_lo[1]), + .I2(com_tlm_u_tlm_tx_vc0_frm_seq_bq_wen_2622), + .I3(com_tlm_u_tlm_tx_vc0_frm_seq_bq_fifo_nxt_vld_o_0), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_bq_fifo_un1_raddr_lo_1_axb_1_2690) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_bq_fifo_N_48886_i_i.INIT = 4'hD; + LUT2 com_tlm_u_tlm_tx_vc0_frm_seq_bq_fifo_N_48886_i_i ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_bq_vld), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_bq_ren_2620), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_bq_fifo_N_48886_i_i_2691) + ); + FDE com_tlm_u_tlm_tx_vc0_frm_seq_bq_fifo_d_o_10_ ( + .CE(com_tlm_u_tlm_tx_vc0_frm_seq_bq_fifo_N_48886_i_i_2691), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_bq_fifo_shift_tap[10]), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_bq_q[10]) + ); + FDE com_tlm_u_tlm_tx_vc0_frm_seq_bq_fifo_d_o_9_ ( + .CE(com_tlm_u_tlm_tx_vc0_frm_seq_bq_fifo_N_48886_i_i_2691), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_bq_fifo_shift_tap[9]), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_bq_q[9]) + ); + FDE com_tlm_u_tlm_tx_vc0_frm_seq_bq_fifo_d_o_8_ ( + .CE(com_tlm_u_tlm_tx_vc0_frm_seq_bq_fifo_N_48886_i_i_2691), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_bq_fifo_shift_tap[8]), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_bq_q[8]) + ); + FDE com_tlm_u_tlm_tx_vc0_frm_seq_bq_fifo_d_o_7_ ( + .CE(com_tlm_u_tlm_tx_vc0_frm_seq_bq_fifo_N_48886_i_i_2691), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_bq_fifo_shift_tap[7]), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_bq_q[7]) + ); + FDE com_tlm_u_tlm_tx_vc0_frm_seq_bq_fifo_d_o_6_ ( + .CE(com_tlm_u_tlm_tx_vc0_frm_seq_bq_fifo_N_48886_i_i_2691), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_bq_fifo_shift_tap[6]), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_bq_q[6]) + ); + FDE com_tlm_u_tlm_tx_vc0_frm_seq_bq_fifo_d_o_5_ ( + .CE(com_tlm_u_tlm_tx_vc0_frm_seq_bq_fifo_N_48886_i_i_2691), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_bq_fifo_shift_tap[5]), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_bq_q[5]) + ); + FDE com_tlm_u_tlm_tx_vc0_frm_seq_bq_fifo_d_o_4_ ( + .CE(com_tlm_u_tlm_tx_vc0_frm_seq_bq_fifo_N_48886_i_i_2691), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_bq_fifo_shift_tap[4]), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_bq_q[4]) + ); + FDE com_tlm_u_tlm_tx_vc0_frm_seq_bq_fifo_d_o_3_ ( + .CE(com_tlm_u_tlm_tx_vc0_frm_seq_bq_fifo_N_48886_i_i_2691), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_bq_fifo_shift_tap[3]), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_bq_q[3]) + ); + FDE com_tlm_u_tlm_tx_vc0_frm_seq_bq_fifo_d_o_2_ ( + .CE(com_tlm_u_tlm_tx_vc0_frm_seq_bq_fifo_N_48886_i_i_2691), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_bq_fifo_shift_tap[2]), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_bq_q[2]) + ); + FDE com_tlm_u_tlm_tx_vc0_frm_seq_bq_fifo_d_o_1_ ( + .CE(com_tlm_u_tlm_tx_vc0_frm_seq_bq_fifo_N_48886_i_i_2691), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_bq_fifo_shift_tap[1]), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_bq_q[1]) + ); + FDE com_tlm_u_tlm_tx_vc0_frm_seq_bq_fifo_d_o_0_ ( + .CE(com_tlm_u_tlm_tx_vc0_frm_seq_bq_fifo_N_48886_i_i_2691), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_bq_fifo_shift_tap[0]), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_bq_q[0]) + ); + GND com_tlm_u_tlm_tx_vc0_frm_seq_sq_fifo_GND ( + .G(com_tlm_u_tlm_tx_vc0_frm_seq_sq_fifo_GND_2692) + ); + SRLC16E com_tlm_u_tlm_tx_vc0_frm_seq_sq_fifo_srlrow_0__srlcol_0__srlinst ( + .CE(com_tlm_u_tlm_tx_vc0_frm_seq_sq_wen_2640), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_sq_d[0]), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_sq_fifo_shift_tap[0]), + .CLK(NlwRenamedSig_OI_trn_clk), + .Q15(NLW_com_tlm_u_tlm_tx_vc0_frm_seq_sq_fifo_srlrow_0__srlcol_0__srlinst_Q15_UNCONNECTED), + .A0(com_tlm_u_tlm_tx_vc0_frm_seq_sq_fifo_raddr_lo[0]), + .A1(com_tlm_u_tlm_tx_vc0_frm_seq_sq_fifo_raddr_lo[1]), + .A2(com_tlm_u_tlm_tx_vc0_frm_seq_sq_fifo_GND_2692), + .A3(com_tlm_u_tlm_tx_vc0_frm_seq_sq_fifo_GND_2692) + ); + SRLC16E com_tlm_u_tlm_tx_vc0_frm_seq_sq_fifo_srlrow_0__srlcol_3__srlinst ( + .CE(com_tlm_u_tlm_tx_vc0_frm_seq_sq_wen_2640), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_sq_d[3]), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_sq_fifo_shift_tap[3]), + .CLK(NlwRenamedSig_OI_trn_clk), + .Q15(NLW_com_tlm_u_tlm_tx_vc0_frm_seq_sq_fifo_srlrow_0__srlcol_3__srlinst_Q15_UNCONNECTED), + .A0(com_tlm_u_tlm_tx_vc0_frm_seq_sq_fifo_raddr_lo[0]), + .A1(com_tlm_u_tlm_tx_vc0_frm_seq_sq_fifo_raddr_lo[1]), + .A2(com_tlm_u_tlm_tx_vc0_frm_seq_sq_fifo_GND_2692), + .A3(com_tlm_u_tlm_tx_vc0_frm_seq_sq_fifo_GND_2692) + ); + SRLC16E com_tlm_u_tlm_tx_vc0_frm_seq_sq_fifo_srlrow_0__srlcol_2__srlinst ( + .CE(com_tlm_u_tlm_tx_vc0_frm_seq_sq_wen_2640), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_sq_d[2]), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_sq_fifo_shift_tap[2]), + .CLK(NlwRenamedSig_OI_trn_clk), + .Q15(NLW_com_tlm_u_tlm_tx_vc0_frm_seq_sq_fifo_srlrow_0__srlcol_2__srlinst_Q15_UNCONNECTED), + .A0(com_tlm_u_tlm_tx_vc0_frm_seq_sq_fifo_raddr_lo[0]), + .A1(com_tlm_u_tlm_tx_vc0_frm_seq_sq_fifo_raddr_lo[1]), + .A2(com_tlm_u_tlm_tx_vc0_frm_seq_sq_fifo_GND_2692), + .A3(com_tlm_u_tlm_tx_vc0_frm_seq_sq_fifo_GND_2692) + ); + SRLC16E com_tlm_u_tlm_tx_vc0_frm_seq_sq_fifo_srlrow_0__srlcol_1__srlinst ( + .CE(com_tlm_u_tlm_tx_vc0_frm_seq_sq_wen_2640), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_sq_d[1]), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_sq_fifo_shift_tap[1]), + .CLK(NlwRenamedSig_OI_trn_clk), + .Q15(NLW_com_tlm_u_tlm_tx_vc0_frm_seq_sq_fifo_srlrow_0__srlcol_1__srlinst_Q15_UNCONNECTED), + .A0(com_tlm_u_tlm_tx_vc0_frm_seq_sq_fifo_raddr_lo[0]), + .A1(com_tlm_u_tlm_tx_vc0_frm_seq_sq_fifo_raddr_lo[1]), + .A2(com_tlm_u_tlm_tx_vc0_frm_seq_sq_fifo_GND_2692), + .A3(com_tlm_u_tlm_tx_vc0_frm_seq_sq_fifo_GND_2692) + ); + FDS com_tlm_u_tlm_tx_vc0_frm_seq_sq_fifo_raddr_lo_0_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_sq_fifo_un1_raddr_lo_1_axb_0_2696), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_sq_fifo_raddr_lo[0]), + .S(plm_link_up_i) + ); + FDS com_tlm_u_tlm_tx_vc0_frm_seq_sq_fifo_raddr_lo_1_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_sq_fifo_un1_raddr_lo_1_s_1_3), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_sq_fifo_raddr_lo[1]), + .S(plm_link_up_i) + ); + FDS com_tlm_u_tlm_tx_vc0_frm_seq_sq_fifo_raddr_lo_2_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_sq_fifo_un1_raddr_lo_1_s_2_3), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_sq_fifo_raddr_lo[2]), + .S(plm_link_up_i) + ); + FDS com_tlm_u_tlm_tx_vc0_frm_seq_sq_fifo_raddr_lo_3_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_sq_fifo_un1_raddr_lo_1_s_3_3), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_sq_fifo_raddr_lo[3]), + .S(plm_link_up_i) + ); + FDRE com_tlm_u_tlm_tx_vc0_frm_seq_sq_fifo_nxt_vld_o ( + .CE(com_tlm_u_tlm_tx_vc0_frm_seq_sq_fifo_N_69199_i_2697), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_sq_fifo_srl_wen), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_sq_nxt_vld), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_tx_vc0_frm_seq_sq_fifo_ct_o_0_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_sq_fifo_un1_ct_o_axb0_2703), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_sq_cnt[0]), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_tx_vc0_frm_seq_sq_fifo_ct_o_1_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_sq_fifo_un1_ct_o_axbxc1_2702), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_sq_cnt[1]), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_tx_vc0_frm_seq_sq_fifo_ct_o_2_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_sq_fifo_un1_ct_o_axbxc2_2700), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_sq_cnt[2]), + .R(plm_link_up_i) + ); + FDRE com_tlm_u_tlm_tx_vc0_frm_seq_sq_fifo_vld_o ( + .CE(com_tlm_u_tlm_tx_vc0_frm_seq_sq_fifo_N_41745_i_i_2707), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_sq_fifo_N_38461_i_2699), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_sq_vld), + .R(plm_link_up_i) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_sq_fifo_un1_ct_o_p4.INIT = 16'hDC40; + LUT4_L com_tlm_u_tlm_tx_vc0_frm_seq_sq_fifo_un1_ct_o_p4 ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_sq_fifo_N_41841_i), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_sq_fifo_un1_ct_o190_0_a2_0_a2_0_a2[1]), + .I2(com_tlm_u_tlm_tx_vc0_frm_seq_sq_cnt[0]), + .I3(com_tlm_u_tlm_tx_vc0_frm_seq_sq_cnt[1]), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_sq_fifo_un1_ct_o_p4_2701) + ); + MUXCY_L com_tlm_u_tlm_tx_vc0_frm_seq_sq_fifo_un1_raddr_lo_1_cry_0 ( + .CI(com_tlm_u_tlm_tx_vc0_frm_seq_sq_fifo_GND_2692), + .DI(com_tlm_u_tlm_tx_vc0_frm_seq_sq_fifo_raddr_lo[0]), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_sq_fifo_un1_raddr_lo_1_cry_0_2693), + .S(com_tlm_u_tlm_tx_vc0_frm_seq_sq_fifo_un1_raddr_lo_1_axb_0_2696) + ); + MUXCY_L com_tlm_u_tlm_tx_vc0_frm_seq_sq_fifo_un1_raddr_lo_1_cry_1 ( + .CI(com_tlm_u_tlm_tx_vc0_frm_seq_sq_fifo_un1_raddr_lo_1_cry_0_2693), + .DI(com_tlm_u_tlm_tx_vc0_frm_seq_sq_fifo_raddr_lo[1]), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_sq_fifo_un1_raddr_lo_1_cry_1_2694), + .S(com_tlm_u_tlm_tx_vc0_frm_seq_sq_fifo_un1_raddr_lo_1_axb_1_2706) + ); + XORCY com_tlm_u_tlm_tx_vc0_frm_seq_sq_fifo_un1_raddr_lo_1_s_1 ( + .CI(com_tlm_u_tlm_tx_vc0_frm_seq_sq_fifo_un1_raddr_lo_1_cry_0_2693), + .LI(com_tlm_u_tlm_tx_vc0_frm_seq_sq_fifo_un1_raddr_lo_1_axb_1_2706), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_sq_fifo_un1_raddr_lo_1_s_1_3) + ); + MUXCY_L com_tlm_u_tlm_tx_vc0_frm_seq_sq_fifo_un1_raddr_lo_1_cry_2 ( + .CI(com_tlm_u_tlm_tx_vc0_frm_seq_sq_fifo_un1_raddr_lo_1_cry_1_2694), + .DI(com_tlm_u_tlm_tx_vc0_frm_seq_sq_fifo_raddr_lo[2]), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_sq_fifo_un1_raddr_lo_1_cry_2_2695), + .S(com_tlm_u_tlm_tx_vc0_frm_seq_sq_fifo_un1_raddr_lo_1_axb_2_2705) + ); + XORCY com_tlm_u_tlm_tx_vc0_frm_seq_sq_fifo_un1_raddr_lo_1_s_2 ( + .CI(com_tlm_u_tlm_tx_vc0_frm_seq_sq_fifo_un1_raddr_lo_1_cry_1_2694), + .LI(com_tlm_u_tlm_tx_vc0_frm_seq_sq_fifo_un1_raddr_lo_1_axb_2_2705), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_sq_fifo_un1_raddr_lo_1_s_2_3) + ); + XORCY com_tlm_u_tlm_tx_vc0_frm_seq_sq_fifo_un1_raddr_lo_1_s_3 ( + .CI(com_tlm_u_tlm_tx_vc0_frm_seq_sq_fifo_un1_raddr_lo_1_cry_2_2695), + .LI(com_tlm_u_tlm_tx_vc0_frm_seq_sq_fifo_un1_raddr_lo_1_axb_3_2704), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_sq_fifo_un1_raddr_lo_1_s_3_3) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_sq_fifo_raddr_en_0_0_0_o4.INIT = 4'h4; + LUT2 com_tlm_u_tlm_tx_vc0_frm_seq_sq_fifo_raddr_en_0_0_0_o4 ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_seq_state[1]), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_sq_vld), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_sq_fifo_N_41745_i) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_sq_fifo_std_ct_ct_o190_0_x2_0_x2_i_x4.INIT = 8'h87; + LUT3 com_tlm_u_tlm_tx_vc0_frm_seq_sq_fifo_std_ct_ct_o190_0_x2_0_x2_i_x4 ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_seq_state[1]), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_sq_vld), + .I2(com_tlm_u_tlm_tx_vc0_frm_seq_sq_wen_2640), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_sq_fifo_N_41841_i) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_sq_fifo_un1_ct_o190_0_a2_0_a2_0_a2_1_.INIT = 8'h08; + LUT3 com_tlm_u_tlm_tx_vc0_frm_seq_sq_fifo_un1_ct_o190_0_a2_0_a2_0_a2_1_ ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_seq_state[1]), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_sq_vld), + .I2(com_tlm_u_tlm_tx_vc0_frm_seq_sq_wen_2640), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_sq_fifo_un1_ct_o190_0_a2_0_a2_0_a2[1]) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_sq_fifo_un1_bkp_i_1_i_0_0_a2_0_2.INIT = 16'h0001; + LUT4 com_tlm_u_tlm_tx_vc0_frm_seq_sq_fifo_un1_bkp_i_1_i_0_0_a2_0_2 ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_sq_fifo_raddr_lo[0]), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_sq_fifo_raddr_lo[1]), + .I2(com_tlm_u_tlm_tx_vc0_frm_seq_sq_fifo_raddr_lo[2]), + .I3(com_tlm_u_tlm_tx_vc0_frm_seq_sq_fifo_raddr_lo[3]), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_sq_fifo_un1_bkp_i_1_i_0_0_a2_0_2_2698) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_sq_fifo_un1_bkp_i_1_i_0_0_a2.INIT = 8'hE0; + LUT3 com_tlm_u_tlm_tx_vc0_frm_seq_sq_fifo_un1_bkp_i_1_i_0_0_a2 ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_sq_fifo_N_41745_i), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_sq_nxt_vld), + .I2(com_tlm_u_tlm_tx_vc0_frm_seq_sq_wen_2640), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_sq_fifo_srl_wen) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_sq_fifo_un1_raddr_lo_1_axb_0.INIT = 16'h669C; + LUT4 com_tlm_u_tlm_tx_vc0_frm_seq_sq_fifo_un1_raddr_lo_1_axb_0 ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_sq_fifo_N_41745_i), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_sq_fifo_raddr_lo[0]), + .I2(com_tlm_u_tlm_tx_vc0_frm_seq_sq_nxt_vld), + .I3(com_tlm_u_tlm_tx_vc0_frm_seq_sq_wen_2640), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_sq_fifo_un1_raddr_lo_1_axb_0_2696) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_sq_fifo_N_69199_i.INIT = 8'hDC; + LUT3 com_tlm_u_tlm_tx_vc0_frm_seq_sq_fifo_N_69199_i ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_sq_fifo_N_41745_i), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_sq_fifo_srl_wen), + .I2(com_tlm_u_tlm_tx_vc0_frm_seq_sq_fifo_un1_bkp_i_1_i_0_0_a2_0_2_2698), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_sq_fifo_N_69199_i_2697) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_sq_fifo_N_38461_i.INIT = 4'hE; + LUT2_L com_tlm_u_tlm_tx_vc0_frm_seq_sq_fifo_N_38461_i ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_sq_nxt_vld), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_sq_wen_2640), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_sq_fifo_N_38461_i_2699) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_sq_fifo_data_bits_d_o_24_0_i_m2_i_m4_0_3_.INIT = 8'hCA; + LUT3_L com_tlm_u_tlm_tx_vc0_frm_seq_sq_fifo_data_bits_d_o_24_0_i_m2_i_m4_0_3_ ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_sq_d[3]), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_sq_fifo_shift_tap[3]), + .I2(com_tlm_u_tlm_tx_vc0_frm_seq_sq_nxt_vld), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_sq_fifo_d_o_24_0_i_m2_i_m4_0[3]) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_sq_fifo_data_bits_d_o_24_0_i_m2_i_m4_0_2_.INIT = 8'hCA; + LUT3_L com_tlm_u_tlm_tx_vc0_frm_seq_sq_fifo_data_bits_d_o_24_0_i_m2_i_m4_0_2_ ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_sq_d[2]), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_sq_fifo_shift_tap[2]), + .I2(com_tlm_u_tlm_tx_vc0_frm_seq_sq_nxt_vld), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_sq_fifo_d_o_24_0_i_m2_i_m4_0[2]) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_sq_fifo_data_bits_d_o_24_0_i_m2_i_m4_0_1_.INIT = 8'hCA; + LUT3_L com_tlm_u_tlm_tx_vc0_frm_seq_sq_fifo_data_bits_d_o_24_0_i_m2_i_m4_0_1_ ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_sq_d[1]), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_sq_fifo_shift_tap[1]), + .I2(com_tlm_u_tlm_tx_vc0_frm_seq_sq_nxt_vld), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_sq_fifo_d_o_24_0_i_m2_i_m4_0[1]) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_sq_fifo_data_bits_d_o_24_0_i_m2_i_m4_0_0_.INIT = 8'hCA; + LUT3_L com_tlm_u_tlm_tx_vc0_frm_seq_sq_fifo_data_bits_d_o_24_0_i_m2_i_m4_0_0_ ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_sq_d[0]), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_sq_fifo_shift_tap[0]), + .I2(com_tlm_u_tlm_tx_vc0_frm_seq_sq_nxt_vld), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_sq_fifo_d_o_24_0_i_m2_i_m4_0[0]) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_sq_fifo_un1_ct_o_axbxc2.INIT = 8'h96; + LUT3_L com_tlm_u_tlm_tx_vc0_frm_seq_sq_fifo_un1_ct_o_axbxc2 ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_sq_fifo_un1_ct_o190_0_a2_0_a2_0_a2[1]), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_sq_cnt[2]), + .I2(com_tlm_u_tlm_tx_vc0_frm_seq_sq_fifo_un1_ct_o_p4_2701), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_sq_fifo_un1_ct_o_axbxc2_2700) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_sq_fifo_un1_ct_o_axbxc1.INIT = 16'h639C; + LUT4_L com_tlm_u_tlm_tx_vc0_frm_seq_sq_fifo_un1_ct_o_axbxc1 ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_sq_fifo_N_41841_i), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_sq_fifo_un1_ct_o190_0_a2_0_a2_0_a2[1]), + .I2(com_tlm_u_tlm_tx_vc0_frm_seq_sq_cnt[0]), + .I3(com_tlm_u_tlm_tx_vc0_frm_seq_sq_cnt[1]), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_sq_fifo_un1_ct_o_axbxc1_2702) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_sq_fifo_un1_ct_o_axb0.INIT = 4'h9; + LUT2_L com_tlm_u_tlm_tx_vc0_frm_seq_sq_fifo_un1_ct_o_axb0 ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_sq_fifo_N_41841_i), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_sq_cnt[0]), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_sq_fifo_un1_ct_o_axb0_2703) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_sq_fifo_un1_raddr_lo_1_axb_3.INIT = 16'hCC9C; + LUT4_L com_tlm_u_tlm_tx_vc0_frm_seq_sq_fifo_un1_raddr_lo_1_axb_3 ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_sq_fifo_N_41745_i), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_sq_fifo_raddr_lo[3]), + .I2(com_tlm_u_tlm_tx_vc0_frm_seq_sq_nxt_vld), + .I3(com_tlm_u_tlm_tx_vc0_frm_seq_sq_wen_2640), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_sq_fifo_un1_raddr_lo_1_axb_3_2704) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_sq_fifo_un1_raddr_lo_1_axb_2.INIT = 16'hCC9C; + LUT4_L com_tlm_u_tlm_tx_vc0_frm_seq_sq_fifo_un1_raddr_lo_1_axb_2 ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_sq_fifo_N_41745_i), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_sq_fifo_raddr_lo[2]), + .I2(com_tlm_u_tlm_tx_vc0_frm_seq_sq_nxt_vld), + .I3(com_tlm_u_tlm_tx_vc0_frm_seq_sq_wen_2640), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_sq_fifo_un1_raddr_lo_1_axb_2_2705) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_sq_fifo_un1_raddr_lo_1_axb_1.INIT = 16'hCC9C; + LUT4_L com_tlm_u_tlm_tx_vc0_frm_seq_sq_fifo_un1_raddr_lo_1_axb_1 ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_sq_fifo_N_41745_i), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_sq_fifo_raddr_lo[1]), + .I2(com_tlm_u_tlm_tx_vc0_frm_seq_sq_nxt_vld), + .I3(com_tlm_u_tlm_tx_vc0_frm_seq_sq_wen_2640), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_sq_fifo_un1_raddr_lo_1_axb_1_2706) + ); + FDE com_tlm_u_tlm_tx_vc0_frm_seq_sq_fifo_d_o_3_ ( + .CE(com_tlm_u_tlm_tx_vc0_frm_seq_sq_fifo_N_41745_i_i_2707), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_sq_fifo_d_o_24_0_i_m2_i_m4_0[3]), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_sq_q[3]) + ); + FDE com_tlm_u_tlm_tx_vc0_frm_seq_sq_fifo_d_o_2_ ( + .CE(com_tlm_u_tlm_tx_vc0_frm_seq_sq_fifo_N_41745_i_i_2707), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_sq_fifo_d_o_24_0_i_m2_i_m4_0[2]), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_sq_q[2]) + ); + FDE com_tlm_u_tlm_tx_vc0_frm_seq_sq_fifo_d_o_1_ ( + .CE(com_tlm_u_tlm_tx_vc0_frm_seq_sq_fifo_N_41745_i_i_2707), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_sq_fifo_d_o_24_0_i_m2_i_m4_0[1]), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_sq_q[1]) + ); + FDE com_tlm_u_tlm_tx_vc0_frm_seq_sq_fifo_d_o_0_ ( + .CE(com_tlm_u_tlm_tx_vc0_frm_seq_sq_fifo_N_41745_i_i_2707), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_sq_fifo_d_o_24_0_i_m2_i_m4_0[0]), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_sq_q[0]) + ); + INV com_tlm_u_tlm_tx_vc0_frm_seq_sq_fifo_N_41745_i_i ( + .I(com_tlm_u_tlm_tx_vc0_frm_seq_sq_fifo_N_41745_i), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_sq_fifo_N_41745_i_i_2707) + ); + VCC com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_VCC ( + .P(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_VCC_2810) + ); + GND com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_GND ( + .G(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_GND_2822) + ); + FDS com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_min_data_cred_3_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_min_data_cred_7[3]), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_min_data_cred[3]), + .S(plm_link_up_i) + ); + FDR com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_min_data_cred_4_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_min_data_cred_7[4]), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_min_data_cred[4]), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_min_data_cred_5_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_N_43656_i), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_min_data_cred[5]), + .R(plm_link_up_i) + ); + FDS com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_pd_av_o_0_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_pd_av_o_6[0]), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_pd_av_0_), + .S(plm_link_up_i) + ); + FDS com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_pd_av_o_1_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_pd_av_o_6[1]), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_pd_av_1_), + .S(plm_link_up_i) + ); + FDS com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_pd_av_o_2_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_pd_av_o_6[2]), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_pd_av_2_), + .S(plm_link_up_i) + ); + FDS com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_pd_av_o_3_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_pd_av_o_6[3]), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_pd_av_3_), + .S(plm_link_up_i) + ); + FDS com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_pd_av_o_4_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_pd_av_o_6[4]), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_pd_av_4_), + .S(plm_link_up_i) + ); + FDS com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_pd_av_o_5_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_pd_av_o_6[5]), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_pd_av_5_), + .S(plm_link_up_i) + ); + FDS com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_pd_av_o_6_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_pd_av_o_6[6]), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_pd_av[6]), + .S(plm_link_up_i) + ); + FDS com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_pd_av_o_7_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_pd_av_o_6[7]), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_pd_av[7]), + .S(plm_link_up_i) + ); + FDS com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_pd_av_o_8_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_pd_av_o_6[8]), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_pd_av[8]), + .S(plm_link_up_i) + ); + FDS com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_pd_av_o_9_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_pd_av_o_6[9]), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_pd_av[9]), + .S(plm_link_up_i) + ); + FDS com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_pd_av_o_10_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_pd_av_o_6[10]), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_pd_av[10]), + .S(plm_link_up_i) + ); + FDR com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_pd_av_o_11_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_pd_av_o_6[11]), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_pd_av_11_), + .R(plm_link_up_i) + ); + FDS com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_npd_av_o_0_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_npd_av_o_6[0]), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_npd_av[0]), + .S(plm_link_up_i) + ); + FDS com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_npd_av_o_1_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_npd_av_o_6[1]), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_npd_av[1]), + .S(plm_link_up_i) + ); + FDS com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_npd_av_o_2_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_npd_av_o_6[2]), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_npd_av[2]), + .S(plm_link_up_i) + ); + FDS com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_npd_av_o_3_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_npd_av_o_6[3]), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_npd_av[3]), + .S(plm_link_up_i) + ); + FDS com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_npd_av_o_4_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_npd_av_o_6[4]), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_npd_av[4]), + .S(plm_link_up_i) + ); + FDS com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_npd_av_o_5_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_npd_av_o_6[5]), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_npd_av[5]), + .S(plm_link_up_i) + ); + FDS com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_npd_av_o_6_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_npd_av_o_6[6]), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_npd_av[6]), + .S(plm_link_up_i) + ); + FDS com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_npd_av_o_7_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_npd_av_o_6[7]), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_npd_av[7]), + .S(plm_link_up_i) + ); + FDS com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_npd_av_o_8_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_npd_av_o_6[8]), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_npd_av[8]), + .S(plm_link_up_i) + ); + FDS com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_npd_av_o_9_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_npd_av_o_6[9]), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_npd_av[9]), + .S(plm_link_up_i) + ); + FDS com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_npd_av_o_10_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_npd_av_o_6[10]), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_npd_av[10]), + .S(plm_link_up_i) + ); + FDR com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_npd_av_o_11_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_npd_av_o_6[11]), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_npd_av[11]), + .R(plm_link_up_i) + ); + FDS com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_cpld_av_o_0_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_cpld_av_o_6[0]), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_cpld_av_0_), + .S(plm_link_up_i) + ); + FDS com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_cpld_av_o_1_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_cpld_av_o_6[1]), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_cpld_av_1_), + .S(plm_link_up_i) + ); + FDS com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_cpld_av_o_2_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_cpld_av_o_6[2]), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_cpld_av_2_), + .S(plm_link_up_i) + ); + FDS com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_cpld_av_o_3_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_cpld_av_o_6[3]), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_cpld_av_3_), + .S(plm_link_up_i) + ); + FDS com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_cpld_av_o_4_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_cpld_av_o_6[4]), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_cpld_av_4_), + .S(plm_link_up_i) + ); + FDS com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_cpld_av_o_5_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_cpld_av_o_6[5]), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_cpld_av_5_), + .S(plm_link_up_i) + ); + FDS com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_cpld_av_o_6_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_cpld_av_o_6[6]), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_cpld_av[6]), + .S(plm_link_up_i) + ); + FDS com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_cpld_av_o_7_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_cpld_av_o_6[7]), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_cpld_av[7]), + .S(plm_link_up_i) + ); + FDS com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_cpld_av_o_8_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_cpld_av_o_6[8]), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_cpld_av[8]), + .S(plm_link_up_i) + ); + FDS com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_cpld_av_o_9_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_cpld_av_o_6[9]), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_cpld_av[9]), + .S(plm_link_up_i) + ); + FDS com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_cpld_av_o_10_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_cpld_av_o_6[10]), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_cpld_av[10]), + .S(plm_link_up_i) + ); + FDR com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_cpld_av_o_11_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_cpld_av_o_6[11]), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_cpld_av_11_), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_PD_0_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_PD_1_axb_0_2889), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_PD[0]), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_PD_1_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_PD_1_s_1_2728), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_PD[1]), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_PD_2_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_PD_1_s_2_2731), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_PD[2]), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_PD_3_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_PD_1_s_3_2734), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_PD[3]), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_PD_4_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_PD_1_s_4_2737), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_PD[4]), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_PD_5_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_PD_1_s_5_2740), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_PD[5]), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_PD_6_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_PD_1_s_6_2742), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_PD[6]), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_PD_7_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_PD_1_s_7_2744), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_PD[7]), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_PD_8_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_PD_1_s_8_2746), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_PD[8]), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_PD_9_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_PD_1_s_9_2748), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_PD[9]), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_PD_10_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_PD_1_s_10_2750), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_PD[10]), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_PD_11_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_PD_1_s_11_2752), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_PD[11]), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_NPD_0_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_NPD_1_axb_0_2890), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_NPD[0]), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_NPD_1_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_NPD_1_s_1_2756), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_NPD[1]), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_NPD_2_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_NPD_1_s_2_2759), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_NPD[2]), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_NPD_3_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_NPD_1_s_3_2762), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_NPD[3]), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_NPD_4_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_NPD_1_s_4_2765), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_NPD[4]), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_NPD_5_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_NPD_1_s_5_2768), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_NPD[5]), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_NPD_6_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_NPD_1_s_6_2770), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_NPD[6]), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_NPD_7_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_NPD_1_s_7_2772), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_NPD[7]), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_NPD_8_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_NPD_1_s_8_2774), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_NPD[8]), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_NPD_9_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_NPD_1_s_9_2776), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_NPD[9]), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_NPD_10_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_NPD_1_s_10_2778), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_NPD[10]), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_NPD_11_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_NPD_1_s_11_2780), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_NPD[11]), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_CPLD_0_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_CPLD_1_axb_0_2891), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_CPLD[0]), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_CPLD_1_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_CPLD_1_s_1_2784), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_CPLD[1]), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_CPLD_2_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_CPLD_1_s_2_2787), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_CPLD[2]), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_CPLD_3_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_CPLD_1_s_3_2790), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_CPLD[3]), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_CPLD_4_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_CPLD_1_s_4_2793), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_CPLD[4]), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_CPLD_5_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_CPLD_1_s_5_2796), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_CPLD[5]), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_CPLD_6_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_CPLD_1_s_6_2798), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_CPLD[6]), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_CPLD_7_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_CPLD_1_s_7_2800), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_CPLD[7]), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_CPLD_8_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_CPLD_1_s_8_2802), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_CPLD[8]), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_CPLD_9_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_CPLD_1_s_9_2804), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_CPLD[9]), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_CPLD_10_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_CPLD_1_s_10_2806), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_CPLD[10]), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_CPLD_11_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_CPLD_1_s_11_2808), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_CPLD[11]), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_credits_ok_0_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_credits_ok_3[0]), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_credits_ok[0]), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_credits_ok_1_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_credits_ok[0]), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_credits_ok[1]), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_credits_ok_2_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_credits_ok[1]), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_credits_ok[2]), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_av_hdr_cred ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_N_68153_i_2943), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_av_hdr_cred_2947), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_av_data_cred_0_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_N_43769_i), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_av_data_cred[0]), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_av_data_cred_1_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_N_43771_i), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_av_data_cred[1]), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_av_data_cred_2_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_N_43773_i), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_av_data_cred[2]), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_av_data_cred_3_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_N_43775_i), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_av_data_cred[3]), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_av_data_cred_4_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_N_43777_i), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_av_data_cred[4]), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_av_data_cred_5_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_N_43779_i), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_av_data_cred[5]), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_av_data_cred_6_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_N_43781_i), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_av_data_cred[6]), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_av_data_cred_7_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_N_43783_i), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_av_data_cred[7]), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_av_data_cred_8_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_N_43785_i), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_av_data_cred[8]), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_av_data_cred_9_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_N_43787_i), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_av_data_cred[9]), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_av_data_cred_10_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_N_43789_i), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_av_data_cred[10]), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_av_data_cred_11_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_N_43791_i), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_av_data_cred[11]), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_ph_av_o ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_N_8621_i_2938), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_ph_av), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_nph_av_o ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_N_8622_i_2933), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_nph_av), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_cplh_av_o ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_N_8620_i_2928), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_cplh_av), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_err_fc_o ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_err_fc_o13), + .Q(com_tlm_cmmt_err_flow_control), + .R(plm_link_up_i) + ); + FDRE com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_limit_PH_0_ ( + .CE(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_N_69425_i_2901), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_header_qq[0]), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_limit_PH[0]), + .R(plm_link_up_i) + ); + FDRE com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_limit_PH_1_ ( + .CE(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_N_69425_i_2901), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_header_qq[1]), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_limit_PH[1]), + .R(plm_link_up_i) + ); + FDRE com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_limit_PH_2_ ( + .CE(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_N_69425_i_2901), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_header_qq[2]), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_limit_PH[2]), + .R(plm_link_up_i) + ); + FDRE com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_limit_PH_3_ ( + .CE(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_N_69425_i_2901), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_header_qq[3]), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_limit_PH[3]), + .R(plm_link_up_i) + ); + FDRE com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_limit_PH_4_ ( + .CE(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_N_69425_i_2901), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_header_qq[4]), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_limit_PH[4]), + .R(plm_link_up_i) + ); + FDRE com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_limit_PH_5_ ( + .CE(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_N_69425_i_2901), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_header_qq[5]), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_limit_PH[5]), + .R(plm_link_up_i) + ); + FDRE com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_limit_PH_6_ ( + .CE(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_N_69425_i_2901), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_header_qq[6]), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_limit_PH[6]), + .R(plm_link_up_i) + ); + FDRE com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_limit_PH_7_ ( + .CE(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_N_69425_i_2901), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_header_qq[7]), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_limit_PH[7]), + .R(plm_link_up_i) + ); + FDRE com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_limit_PD_0_ ( + .CE(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_N_69425_i_2901), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_data_qq[0]), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_limit_PD[0]), + .R(plm_link_up_i) + ); + FDRE com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_limit_PD_1_ ( + .CE(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_N_69425_i_2901), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_data_qq[1]), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_limit_PD[1]), + .R(plm_link_up_i) + ); + FDRE com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_limit_PD_2_ ( + .CE(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_N_69425_i_2901), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_data_qq[2]), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_limit_PD[2]), + .R(plm_link_up_i) + ); + FDRE com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_limit_PD_3_ ( + .CE(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_N_69425_i_2901), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_data_qq[3]), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_limit_PD[3]), + .R(plm_link_up_i) + ); + FDRE com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_limit_PD_4_ ( + .CE(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_N_69425_i_2901), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_data_qq[4]), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_limit_PD[4]), + .R(plm_link_up_i) + ); + FDRE com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_limit_PD_5_ ( + .CE(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_N_69425_i_2901), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_data_qq[5]), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_limit_PD[5]), + .R(plm_link_up_i) + ); + FDRE com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_limit_PD_6_ ( + .CE(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_N_69425_i_2901), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_data_qq[6]), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_limit_PD[6]), + .R(plm_link_up_i) + ); + FDRE com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_limit_PD_7_ ( + .CE(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_N_69425_i_2901), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_data_qq[7]), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_limit_PD[7]), + .R(plm_link_up_i) + ); + FDRE com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_limit_PD_8_ ( + .CE(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_N_69425_i_2901), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_data_qq[8]), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_limit_PD[8]), + .R(plm_link_up_i) + ); + FDRE com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_limit_PD_9_ ( + .CE(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_N_69425_i_2901), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_data_qq[9]), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_limit_PD[9]), + .R(plm_link_up_i) + ); + FDRE com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_limit_PD_10_ ( + .CE(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_N_69425_i_2901), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_data_qq[10]), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_limit_PD[10]), + .R(plm_link_up_i) + ); + FDRE com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_limit_PD_11_ ( + .CE(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_N_69425_i_2901), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_data_qq[11]), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_limit_PD[11]), + .R(plm_link_up_i) + ); + FDRE com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_limit_NPH_0_ ( + .CE(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_N_69426_i_2904), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_header_qq[0]), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_limit_NPH[0]), + .R(plm_link_up_i) + ); + FDRE com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_limit_NPH_1_ ( + .CE(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_N_69426_i_2904), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_header_qq[1]), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_limit_NPH[1]), + .R(plm_link_up_i) + ); + FDRE com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_limit_NPH_2_ ( + .CE(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_N_69426_i_2904), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_header_qq[2]), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_limit_NPH[2]), + .R(plm_link_up_i) + ); + FDRE com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_limit_NPH_3_ ( + .CE(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_N_69426_i_2904), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_header_qq[3]), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_limit_NPH[3]), + .R(plm_link_up_i) + ); + FDRE com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_limit_NPH_4_ ( + .CE(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_N_69426_i_2904), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_header_qq[4]), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_limit_NPH[4]), + .R(plm_link_up_i) + ); + FDRE com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_limit_NPH_5_ ( + .CE(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_N_69426_i_2904), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_header_qq[5]), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_limit_NPH[5]), + .R(plm_link_up_i) + ); + FDRE com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_limit_NPH_6_ ( + .CE(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_N_69426_i_2904), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_header_qq[6]), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_limit_NPH[6]), + .R(plm_link_up_i) + ); + FDRE com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_limit_NPH_7_ ( + .CE(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_N_69426_i_2904), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_header_qq[7]), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_limit_NPH[7]), + .R(plm_link_up_i) + ); + FDRE com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_limit_NPD_0_ ( + .CE(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_N_69426_i_2904), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_data_qq[0]), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_limit_NPD[0]), + .R(plm_link_up_i) + ); + FDRE com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_limit_NPD_1_ ( + .CE(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_N_69426_i_2904), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_data_qq[1]), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_limit_NPD[1]), + .R(plm_link_up_i) + ); + FDRE com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_limit_NPD_2_ ( + .CE(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_N_69426_i_2904), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_data_qq[2]), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_limit_NPD[2]), + .R(plm_link_up_i) + ); + FDRE com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_limit_NPD_3_ ( + .CE(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_N_69426_i_2904), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_data_qq[3]), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_limit_NPD[3]), + .R(plm_link_up_i) + ); + FDRE com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_limit_NPD_4_ ( + .CE(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_N_69426_i_2904), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_data_qq[4]), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_limit_NPD[4]), + .R(plm_link_up_i) + ); + FDRE com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_limit_NPD_5_ ( + .CE(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_N_69426_i_2904), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_data_qq[5]), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_limit_NPD[5]), + .R(plm_link_up_i) + ); + FDRE com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_limit_NPD_6_ ( + .CE(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_N_69426_i_2904), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_data_qq[6]), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_limit_NPD[6]), + .R(plm_link_up_i) + ); + FDRE com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_limit_NPD_7_ ( + .CE(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_N_69426_i_2904), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_data_qq[7]), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_limit_NPD[7]), + .R(plm_link_up_i) + ); + FDRE com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_limit_NPD_8_ ( + .CE(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_N_69426_i_2904), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_data_qq[8]), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_limit_NPD[8]), + .R(plm_link_up_i) + ); + FDRE com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_limit_NPD_9_ ( + .CE(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_N_69426_i_2904), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_data_qq[9]), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_limit_NPD[9]), + .R(plm_link_up_i) + ); + FDRE com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_limit_NPD_10_ ( + .CE(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_N_69426_i_2904), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_data_qq[10]), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_limit_NPD[10]), + .R(plm_link_up_i) + ); + FDRE com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_limit_NPD_11_ ( + .CE(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_N_69426_i_2904), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_data_qq[11]), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_limit_NPD[11]), + .R(plm_link_up_i) + ); + FDRE com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_limit_CPLH_0_ ( + .CE(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_N_69427_i_2907), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_header_qq[0]), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_limit_CPLH[0]), + .R(plm_link_up_i) + ); + FDRE com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_limit_CPLH_1_ ( + .CE(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_N_69427_i_2907), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_header_qq[1]), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_limit_CPLH[1]), + .R(plm_link_up_i) + ); + FDRE com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_limit_CPLH_2_ ( + .CE(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_N_69427_i_2907), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_header_qq[2]), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_limit_CPLH[2]), + .R(plm_link_up_i) + ); + FDRE com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_limit_CPLH_3_ ( + .CE(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_N_69427_i_2907), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_header_qq[3]), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_limit_CPLH[3]), + .R(plm_link_up_i) + ); + FDRE com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_limit_CPLH_4_ ( + .CE(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_N_69427_i_2907), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_header_qq[4]), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_limit_CPLH[4]), + .R(plm_link_up_i) + ); + FDRE com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_limit_CPLH_5_ ( + .CE(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_N_69427_i_2907), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_header_qq[5]), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_limit_CPLH[5]), + .R(plm_link_up_i) + ); + FDRE com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_limit_CPLH_6_ ( + .CE(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_N_69427_i_2907), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_header_qq[6]), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_limit_CPLH[6]), + .R(plm_link_up_i) + ); + FDRE com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_limit_CPLH_7_ ( + .CE(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_N_69427_i_2907), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_header_qq[7]), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_limit_CPLH[7]), + .R(plm_link_up_i) + ); + FDRE com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_limit_CPLD_0_ ( + .CE(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_N_69427_i_2907), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_data_qq[0]), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_limit_CPLD[0]), + .R(plm_link_up_i) + ); + FDRE com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_limit_CPLD_1_ ( + .CE(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_N_69427_i_2907), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_data_qq[1]), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_limit_CPLD[1]), + .R(plm_link_up_i) + ); + FDRE com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_limit_CPLD_2_ ( + .CE(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_N_69427_i_2907), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_data_qq[2]), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_limit_CPLD[2]), + .R(plm_link_up_i) + ); + FDRE com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_limit_CPLD_3_ ( + .CE(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_N_69427_i_2907), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_data_qq[3]), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_limit_CPLD[3]), + .R(plm_link_up_i) + ); + FDRE com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_limit_CPLD_4_ ( + .CE(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_N_69427_i_2907), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_data_qq[4]), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_limit_CPLD[4]), + .R(plm_link_up_i) + ); + FDRE com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_limit_CPLD_5_ ( + .CE(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_N_69427_i_2907), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_data_qq[5]), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_limit_CPLD[5]), + .R(plm_link_up_i) + ); + FDRE com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_limit_CPLD_6_ ( + .CE(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_N_69427_i_2907), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_data_qq[6]), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_limit_CPLD[6]), + .R(plm_link_up_i) + ); + FDRE com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_limit_CPLD_7_ ( + .CE(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_N_69427_i_2907), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_data_qq[7]), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_limit_CPLD[7]), + .R(plm_link_up_i) + ); + FDRE com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_limit_CPLD_8_ ( + .CE(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_N_69427_i_2907), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_data_qq[8]), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_limit_CPLD[8]), + .R(plm_link_up_i) + ); + FDRE com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_limit_CPLD_9_ ( + .CE(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_N_69427_i_2907), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_data_qq[9]), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_limit_CPLD[9]), + .R(plm_link_up_i) + ); + FDRE com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_limit_CPLD_10_ ( + .CE(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_N_69427_i_2907), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_data_qq[10]), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_limit_CPLD[10]), + .R(plm_link_up_i) + ); + FDRE com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_limit_CPLD_11_ ( + .CE(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_N_69427_i_2907), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_data_qq[11]), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_limit_CPLD[11]), + .R(plm_link_up_i) + ); + FDRE com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_infinite_PH ( + .CE(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_init_pc_2894), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_infinite_header_q_3014), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_infinite_PH_2897), + .R(plm_link_up_i) + ); + FDRE com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_infinite_PD ( + .CE(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_init_pc_2894), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_infinite_data_q_3016), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_infinite_PD_3030), + .R(plm_link_up_i) + ); + FDRE com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_infinite_NPH ( + .CE(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_init_npc_2893), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_infinite_header_q_3014), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_infinite_NPH_2896), + .R(plm_link_up_i) + ); + FDRE com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_infinite_NPD ( + .CE(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_init_npc_2893), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_infinite_data_q_3016), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_infinite_NPD_3028), + .R(plm_link_up_i) + ); + FDRE com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_infinite_CPLH ( + .CE(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_init_cplc_2892), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_infinite_header_q_3014), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_infinite_CPLH_2919), + .R(plm_link_up_i) + ); + FDRE com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_infinite_CPLD ( + .CE(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_init_cplc_2892), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_infinite_data_q_3016), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_infinite_CPLD_3026), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_av_valid_o ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_av_valid_o_4), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_av_valid), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_update_p ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_update_p_3), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_update_p_2902), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_update_np ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_update_np_3), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_update_np_2905), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_update_cpl ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_update_cpl_3), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_update_cpl_2908), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_suspend_rdy_o ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_suspend_rdy_o_3_2922), + .Q(com_tlm_u_tlm_tx_suspend_credit_rdy), + .R(plm_link_up_i) + ); + FDS com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_q ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_N_13857_i_2921), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_q_2924), + .S(plm_link_up_i) + ); + FDR com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_update_vld_qq ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_update_vld_q_2923), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_update_vld_qq_2925), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_update_vld_q ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_fc_update_vld), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_update_vld_q_2923), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_init_vld_q ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_fc_init_vld), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_init_vld_q_2895), + .R(plm_link_up_i) + ); + MUXCY_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un7_credits_ok_cry_0 ( + .CI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_GND_2822), + .DI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_suspend_cat[1]), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un7_credits_ok_cry_0_2708), + .S(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un7_credits_ok_axb_0_i_3060) + ); + MUXCY_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un7_credits_ok_cry_1 ( + .CI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un7_credits_ok_cry_0_2708), + .DI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_GND_2822), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un7_credits_ok_cry_1_2709), + .S(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_av_data_cred_i_1__3059) + ); + MUXCY_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un7_credits_ok_cry_2 ( + .CI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un7_credits_ok_cry_1_2709), + .DI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_GND_2822), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un7_credits_ok_cry_2_2710), + .S(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_av_data_cred_i_2__3058) + ); + MUXCY_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un7_credits_ok_cry_3 ( + .CI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un7_credits_ok_cry_2_2710), + .DI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_min_data_cred[3]), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un7_credits_ok_cry_3_2711), + .S(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un7_credits_ok_axb_3_i_3057) + ); + MUXCY_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un7_credits_ok_cry_4 ( + .CI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un7_credits_ok_cry_3_2711), + .DI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_min_data_cred[4]), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un7_credits_ok_cry_4_2712), + .S(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un7_credits_ok_axb_4_i_3056) + ); + MUXCY_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un7_credits_ok_cry_5 ( + .CI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un7_credits_ok_cry_4_2712), + .DI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_min_data_cred[5]), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un7_credits_ok_cry_5_2713), + .S(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un7_credits_ok_axb_5_i_3055) + ); + MUXCY_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un7_credits_ok_cry_6 ( + .CI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un7_credits_ok_cry_5_2713), + .DI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_GND_2822), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un7_credits_ok_cry_6_2714), + .S(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_av_data_cred_i_6__3054) + ); + MUXCY_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un7_credits_ok_cry_7 ( + .CI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un7_credits_ok_cry_6_2714), + .DI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_GND_2822), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un7_credits_ok_cry_7_2715), + .S(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_av_data_cred_i_7__3053) + ); + MUXCY_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un7_credits_ok_cry_8 ( + .CI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un7_credits_ok_cry_7_2715), + .DI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_GND_2822), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un7_credits_ok_cry_8_2716), + .S(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_av_data_cred_i_8__3052) + ); + MUXCY_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un7_credits_ok_cry_9 ( + .CI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un7_credits_ok_cry_8_2716), + .DI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_GND_2822), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un7_credits_ok_cry_9_2717), + .S(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_av_data_cred_i_9__3051) + ); + MUXCY_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un7_credits_ok_cry_10 ( + .CI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un7_credits_ok_cry_9_2717), + .DI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_GND_2822), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un7_credits_ok_cry_10_2718), + .S(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_av_data_cred_i_10__3050) + ); + MUXCY com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un7_credits_ok_cry_11 ( + .CI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un7_credits_ok_cry_10_2718), + .DI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_GND_2822), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un7_credits_ok_cry_11_2946), + .S(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_av_data_cred_i_11__3049) + ); + MUXCY_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_fc_diff_header_cry_0 ( + .CI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_VCC_2810), + .DI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_header_q[0]), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_fc_diff_header_cry_0_2719), + .S(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_fc_diff_header_axb_0_3048) + ); + MUXCY_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_fc_diff_header_cry_1 ( + .CI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_fc_diff_header_cry_0_2719), + .DI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_header_q[1]), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_fc_diff_header_cry_1_2720), + .S(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_fc_diff_header_axb_1_3047) + ); + MUXCY_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_fc_diff_header_cry_2 ( + .CI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_fc_diff_header_cry_1_2720), + .DI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_header_q[2]), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_fc_diff_header_cry_2_2721), + .S(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_fc_diff_header_axb_2_3046) + ); + MUXCY_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_fc_diff_header_cry_3 ( + .CI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_fc_diff_header_cry_2_2721), + .DI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_header_q[3]), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_fc_diff_header_cry_3_2722), + .S(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_fc_diff_header_axb_3_3045) + ); + MUXCY_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_fc_diff_header_cry_4 ( + .CI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_fc_diff_header_cry_3_2722), + .DI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_header_q[4]), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_fc_diff_header_cry_4_2723), + .S(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_fc_diff_header_axb_4_3044) + ); + MUXCY_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_fc_diff_header_cry_5 ( + .CI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_fc_diff_header_cry_4_2723), + .DI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_header_q[5]), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_fc_diff_header_cry_5_2724), + .S(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_fc_diff_header_axb_5_3043) + ); + MUXCY_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_fc_diff_header_cry_6 ( + .CI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_fc_diff_header_cry_5_2724), + .DI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_header_q[6]), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_fc_diff_header_cry_6_2725), + .S(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_fc_diff_header_axb_6_3042) + ); + XORCY com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_fc_diff_header_s_7 ( + .CI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_fc_diff_header_cry_6_2725), + .LI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_fc_diff_header_axb_7_2918), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_fc_diff_header[7]) + ); + MULT_AND com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_PD_1_cry_0 ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_consumed_credits[0]), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_consumed_ph_2565), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_PD_1_cry_0_0_2726) + ); + MUXCY_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_PD_1_cry_0_0 ( + .CI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_GND_2822), + .DI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_PD_1_cry_0_0_2726), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_PD_1_cry_0_2729), + .S(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_PD_1_axb_0_2889) + ); + MULT_AND com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_PD_1_cry_1 ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_consumed_credits[1]), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_consumed_ph_2565), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_PD_1_cry_1_0_2727) + ); + MUXCY_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_PD_1_cry_1_0 ( + .CI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_PD_1_cry_0_2729), + .DI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_PD_1_cry_1_0_2727), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_PD_1_cry_1_2732), + .S(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_PD_1_axb_1_2980) + ); + XORCY com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_PD_1_s_1 ( + .CI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_PD_1_cry_0_2729), + .LI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_PD_1_axb_1_2980), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_PD_1_s_1_2728) + ); + MULT_AND com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_PD_1_cry_2 ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_consumed_credits[2]), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_consumed_ph_2565), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_PD_1_cry_2_0_2730) + ); + MUXCY_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_PD_1_cry_2_0 ( + .CI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_PD_1_cry_1_2732), + .DI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_PD_1_cry_2_0_2730), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_PD_1_cry_2_2735), + .S(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_PD_1_axb_2_2979) + ); + XORCY com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_PD_1_s_2 ( + .CI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_PD_1_cry_1_2732), + .LI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_PD_1_axb_2_2979), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_PD_1_s_2_2731) + ); + MULT_AND com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_PD_1_cry_3 ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_consumed_credits[3]), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_consumed_ph_2565), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_PD_1_cry_3_0_2733) + ); + MUXCY_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_PD_1_cry_3_0 ( + .CI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_PD_1_cry_2_2735), + .DI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_PD_1_cry_3_0_2733), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_PD_1_cry_3_2738), + .S(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_PD_1_axb_3_2978) + ); + XORCY com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_PD_1_s_3 ( + .CI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_PD_1_cry_2_2735), + .LI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_PD_1_axb_3_2978), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_PD_1_s_3_2734) + ); + MULT_AND com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_PD_1_cry_4 ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_consumed_credits[4]), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_consumed_ph_2565), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_PD_1_cry_4_0_2736) + ); + MUXCY_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_PD_1_cry_4_0 ( + .CI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_PD_1_cry_3_2738), + .DI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_PD_1_cry_4_0_2736), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_PD_1_cry_4_2741), + .S(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_PD_1_axb_4_2977) + ); + XORCY com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_PD_1_s_4 ( + .CI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_PD_1_cry_3_2738), + .LI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_PD_1_axb_4_2977), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_PD_1_s_4_2737) + ); + MULT_AND com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_PD_1_cry_5 ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_consumed_credits[5]), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_consumed_ph_2565), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_PD_1_cry_5_0_2739) + ); + MUXCY_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_PD_1_cry_5_0 ( + .CI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_PD_1_cry_4_2741), + .DI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_PD_1_cry_5_0_2739), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_PD_1_cry_5_2743), + .S(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_PD_1_axb_5_2976) + ); + XORCY com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_PD_1_s_5 ( + .CI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_PD_1_cry_4_2741), + .LI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_PD_1_axb_5_2976), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_PD_1_s_5_2740) + ); + MUXCY_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_PD_1_cry_6 ( + .CI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_PD_1_cry_5_2743), + .DI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_GND_2822), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_PD_1_cry_6_2745), + .S(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_PD_1_axb_6_2975) + ); + XORCY com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_PD_1_s_6 ( + .CI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_PD_1_cry_5_2743), + .LI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_PD_1_axb_6_2975), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_PD_1_s_6_2742) + ); + MUXCY_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_PD_1_cry_7 ( + .CI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_PD_1_cry_6_2745), + .DI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_GND_2822), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_PD_1_cry_7_2747), + .S(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_PD_1_axb_7_2974) + ); + XORCY com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_PD_1_s_7 ( + .CI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_PD_1_cry_6_2745), + .LI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_PD_1_axb_7_2974), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_PD_1_s_7_2744) + ); + MUXCY_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_PD_1_cry_8 ( + .CI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_PD_1_cry_7_2747), + .DI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_GND_2822), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_PD_1_cry_8_2749), + .S(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_PD_1_axb_8_2973) + ); + XORCY com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_PD_1_s_8 ( + .CI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_PD_1_cry_7_2747), + .LI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_PD_1_axb_8_2973), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_PD_1_s_8_2746) + ); + MUXCY_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_PD_1_cry_9 ( + .CI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_PD_1_cry_8_2749), + .DI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_GND_2822), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_PD_1_cry_9_2751), + .S(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_PD_1_axb_9_2972) + ); + XORCY com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_PD_1_s_9 ( + .CI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_PD_1_cry_8_2749), + .LI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_PD_1_axb_9_2972), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_PD_1_s_9_2748) + ); + MUXCY_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_PD_1_cry_10 ( + .CI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_PD_1_cry_9_2751), + .DI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_GND_2822), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_PD_1_cry_10_2753), + .S(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_PD_1_axb_10_2971) + ); + XORCY com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_PD_1_s_10 ( + .CI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_PD_1_cry_9_2751), + .LI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_PD_1_axb_10_2971), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_PD_1_s_10_2750) + ); + XORCY com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_PD_1_s_11 ( + .CI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_PD_1_cry_10_2753), + .LI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_PD_1_axb_11_2970), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_PD_1_s_11_2752) + ); + MULT_AND com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_NPD_1_cry_0 ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_consumed_credits[0]), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_consumed_nph_2564), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_NPD_1_cry_0_0_2754) + ); + MUXCY_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_NPD_1_cry_0_0 ( + .CI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_GND_2822), + .DI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_NPD_1_cry_0_0_2754), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_NPD_1_cry_0_2757), + .S(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_NPD_1_axb_0_2890) + ); + MULT_AND com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_NPD_1_cry_1 ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_consumed_credits[1]), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_consumed_nph_2564), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_NPD_1_cry_1_0_2755) + ); + MUXCY_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_NPD_1_cry_1_0 ( + .CI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_NPD_1_cry_0_2757), + .DI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_NPD_1_cry_1_0_2755), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_NPD_1_cry_1_2760), + .S(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_NPD_1_axb_1_2969) + ); + XORCY com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_NPD_1_s_1 ( + .CI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_NPD_1_cry_0_2757), + .LI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_NPD_1_axb_1_2969), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_NPD_1_s_1_2756) + ); + MULT_AND com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_NPD_1_cry_2 ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_consumed_credits[2]), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_consumed_nph_2564), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_NPD_1_cry_2_0_2758) + ); + MUXCY_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_NPD_1_cry_2_0 ( + .CI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_NPD_1_cry_1_2760), + .DI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_NPD_1_cry_2_0_2758), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_NPD_1_cry_2_2763), + .S(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_NPD_1_axb_2_2968) + ); + XORCY com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_NPD_1_s_2 ( + .CI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_NPD_1_cry_1_2760), + .LI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_NPD_1_axb_2_2968), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_NPD_1_s_2_2759) + ); + MULT_AND com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_NPD_1_cry_3 ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_consumed_credits[3]), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_consumed_nph_2564), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_NPD_1_cry_3_0_2761) + ); + MUXCY_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_NPD_1_cry_3_0 ( + .CI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_NPD_1_cry_2_2763), + .DI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_NPD_1_cry_3_0_2761), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_NPD_1_cry_3_2766), + .S(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_NPD_1_axb_3_2967) + ); + XORCY com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_NPD_1_s_3 ( + .CI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_NPD_1_cry_2_2763), + .LI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_NPD_1_axb_3_2967), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_NPD_1_s_3_2762) + ); + MULT_AND com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_NPD_1_cry_4 ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_consumed_credits[4]), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_consumed_nph_2564), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_NPD_1_cry_4_0_2764) + ); + MUXCY_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_NPD_1_cry_4_0 ( + .CI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_NPD_1_cry_3_2766), + .DI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_NPD_1_cry_4_0_2764), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_NPD_1_cry_4_2769), + .S(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_NPD_1_axb_4_2966) + ); + XORCY com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_NPD_1_s_4 ( + .CI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_NPD_1_cry_3_2766), + .LI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_NPD_1_axb_4_2966), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_NPD_1_s_4_2765) + ); + MULT_AND com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_NPD_1_cry_5 ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_consumed_credits[5]), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_consumed_nph_2564), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_NPD_1_cry_5_0_2767) + ); + MUXCY_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_NPD_1_cry_5_0 ( + .CI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_NPD_1_cry_4_2769), + .DI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_NPD_1_cry_5_0_2767), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_NPD_1_cry_5_2771), + .S(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_NPD_1_axb_5_2965) + ); + XORCY com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_NPD_1_s_5 ( + .CI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_NPD_1_cry_4_2769), + .LI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_NPD_1_axb_5_2965), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_NPD_1_s_5_2768) + ); + MUXCY_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_NPD_1_cry_6 ( + .CI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_NPD_1_cry_5_2771), + .DI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_GND_2822), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_NPD_1_cry_6_2773), + .S(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_NPD_1_axb_6_2964) + ); + XORCY com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_NPD_1_s_6 ( + .CI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_NPD_1_cry_5_2771), + .LI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_NPD_1_axb_6_2964), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_NPD_1_s_6_2770) + ); + MUXCY_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_NPD_1_cry_7 ( + .CI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_NPD_1_cry_6_2773), + .DI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_GND_2822), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_NPD_1_cry_7_2775), + .S(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_NPD_1_axb_7_2963) + ); + XORCY com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_NPD_1_s_7 ( + .CI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_NPD_1_cry_6_2773), + .LI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_NPD_1_axb_7_2963), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_NPD_1_s_7_2772) + ); + MUXCY_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_NPD_1_cry_8 ( + .CI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_NPD_1_cry_7_2775), + .DI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_GND_2822), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_NPD_1_cry_8_2777), + .S(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_NPD_1_axb_8_2962) + ); + XORCY com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_NPD_1_s_8 ( + .CI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_NPD_1_cry_7_2775), + .LI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_NPD_1_axb_8_2962), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_NPD_1_s_8_2774) + ); + MUXCY_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_NPD_1_cry_9 ( + .CI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_NPD_1_cry_8_2777), + .DI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_GND_2822), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_NPD_1_cry_9_2779), + .S(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_NPD_1_axb_9_2961) + ); + XORCY com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_NPD_1_s_9 ( + .CI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_NPD_1_cry_8_2777), + .LI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_NPD_1_axb_9_2961), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_NPD_1_s_9_2776) + ); + MUXCY_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_NPD_1_cry_10 ( + .CI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_NPD_1_cry_9_2779), + .DI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_GND_2822), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_NPD_1_cry_10_2781), + .S(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_NPD_1_axb_10_2960) + ); + XORCY com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_NPD_1_s_10 ( + .CI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_NPD_1_cry_9_2779), + .LI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_NPD_1_axb_10_2960), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_NPD_1_s_10_2778) + ); + XORCY com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_NPD_1_s_11 ( + .CI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_NPD_1_cry_10_2781), + .LI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_NPD_1_axb_11_2959), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_NPD_1_s_11_2780) + ); + MULT_AND com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_CPLD_1_cry_0 ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_consumed_cplh_2566), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_consumed_credits[0]), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_CPLD_1_cry_0_0_2782) + ); + MUXCY_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_CPLD_1_cry_0_0 ( + .CI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_GND_2822), + .DI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_CPLD_1_cry_0_0_2782), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_CPLD_1_cry_0_2785), + .S(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_CPLD_1_axb_0_2891) + ); + MULT_AND com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_CPLD_1_cry_1 ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_consumed_cplh_2566), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_consumed_credits[1]), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_CPLD_1_cry_1_0_2783) + ); + MUXCY_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_CPLD_1_cry_1_0 ( + .CI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_CPLD_1_cry_0_2785), + .DI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_CPLD_1_cry_1_0_2783), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_CPLD_1_cry_1_2788), + .S(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_CPLD_1_axb_1_2958) + ); + XORCY com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_CPLD_1_s_1 ( + .CI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_CPLD_1_cry_0_2785), + .LI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_CPLD_1_axb_1_2958), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_CPLD_1_s_1_2784) + ); + MULT_AND com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_CPLD_1_cry_2 ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_consumed_cplh_2566), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_consumed_credits[2]), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_CPLD_1_cry_2_0_2786) + ); + MUXCY_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_CPLD_1_cry_2_0 ( + .CI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_CPLD_1_cry_1_2788), + .DI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_CPLD_1_cry_2_0_2786), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_CPLD_1_cry_2_2791), + .S(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_CPLD_1_axb_2_2957) + ); + XORCY com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_CPLD_1_s_2 ( + .CI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_CPLD_1_cry_1_2788), + .LI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_CPLD_1_axb_2_2957), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_CPLD_1_s_2_2787) + ); + MULT_AND com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_CPLD_1_cry_3 ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_consumed_cplh_2566), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_consumed_credits[3]), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_CPLD_1_cry_3_0_2789) + ); + MUXCY_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_CPLD_1_cry_3_0 ( + .CI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_CPLD_1_cry_2_2791), + .DI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_CPLD_1_cry_3_0_2789), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_CPLD_1_cry_3_2794), + .S(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_CPLD_1_axb_3_2956) + ); + XORCY com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_CPLD_1_s_3 ( + .CI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_CPLD_1_cry_2_2791), + .LI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_CPLD_1_axb_3_2956), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_CPLD_1_s_3_2790) + ); + MULT_AND com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_CPLD_1_cry_4 ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_consumed_cplh_2566), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_consumed_credits[4]), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_CPLD_1_cry_4_0_2792) + ); + MUXCY_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_CPLD_1_cry_4_0 ( + .CI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_CPLD_1_cry_3_2794), + .DI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_CPLD_1_cry_4_0_2792), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_CPLD_1_cry_4_2797), + .S(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_CPLD_1_axb_4_2955) + ); + XORCY com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_CPLD_1_s_4 ( + .CI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_CPLD_1_cry_3_2794), + .LI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_CPLD_1_axb_4_2955), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_CPLD_1_s_4_2793) + ); + MULT_AND com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_CPLD_1_cry_5 ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_consumed_cplh_2566), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_consumed_credits[5]), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_CPLD_1_cry_5_0_2795) + ); + MUXCY_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_CPLD_1_cry_5_0 ( + .CI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_CPLD_1_cry_4_2797), + .DI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_CPLD_1_cry_5_0_2795), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_CPLD_1_cry_5_2799), + .S(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_CPLD_1_axb_5_2954) + ); + XORCY com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_CPLD_1_s_5 ( + .CI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_CPLD_1_cry_4_2797), + .LI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_CPLD_1_axb_5_2954), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_CPLD_1_s_5_2796) + ); + MUXCY_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_CPLD_1_cry_6 ( + .CI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_CPLD_1_cry_5_2799), + .DI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_GND_2822), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_CPLD_1_cry_6_2801), + .S(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_CPLD_1_axb_6_2953) + ); + XORCY com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_CPLD_1_s_6 ( + .CI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_CPLD_1_cry_5_2799), + .LI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_CPLD_1_axb_6_2953), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_CPLD_1_s_6_2798) + ); + MUXCY_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_CPLD_1_cry_7 ( + .CI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_CPLD_1_cry_6_2801), + .DI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_GND_2822), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_CPLD_1_cry_7_2803), + .S(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_CPLD_1_axb_7_2952) + ); + XORCY com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_CPLD_1_s_7 ( + .CI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_CPLD_1_cry_6_2801), + .LI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_CPLD_1_axb_7_2952), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_CPLD_1_s_7_2800) + ); + MUXCY_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_CPLD_1_cry_8 ( + .CI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_CPLD_1_cry_7_2803), + .DI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_GND_2822), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_CPLD_1_cry_8_2805), + .S(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_CPLD_1_axb_8_2951) + ); + XORCY com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_CPLD_1_s_8 ( + .CI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_CPLD_1_cry_7_2803), + .LI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_CPLD_1_axb_8_2951), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_CPLD_1_s_8_2802) + ); + MUXCY_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_CPLD_1_cry_9 ( + .CI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_CPLD_1_cry_8_2805), + .DI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_GND_2822), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_CPLD_1_cry_9_2807), + .S(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_CPLD_1_axb_9_2950) + ); + XORCY com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_CPLD_1_s_9 ( + .CI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_CPLD_1_cry_8_2805), + .LI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_CPLD_1_axb_9_2950), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_CPLD_1_s_9_2804) + ); + MUXCY_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_CPLD_1_cry_10 ( + .CI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_CPLD_1_cry_9_2807), + .DI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_GND_2822), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_CPLD_1_cry_10_2809), + .S(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_CPLD_1_axb_10_2949) + ); + XORCY com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_CPLD_1_s_10 ( + .CI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_CPLD_1_cry_9_2807), + .LI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_CPLD_1_axb_10_2949), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_CPLD_1_s_10_2806) + ); + XORCY com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_CPLD_1_s_11 ( + .CI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_CPLD_1_cry_10_2809), + .LI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_CPLD_1_axb_11_2948), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_CPLD_1_s_11_2808) + ); + MUXCY_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_fc_diff_data_cry_0 ( + .CI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_VCC_2810), + .DI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_data_q[0]), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_fc_diff_data_cry_0_2811), + .S(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_fc_diff_data_axb_0_3041) + ); + MUXCY_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_fc_diff_data_cry_1 ( + .CI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_fc_diff_data_cry_0_2811), + .DI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_data_q[1]), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_fc_diff_data_cry_1_2812), + .S(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_fc_diff_data_axb_1_3040) + ); + MUXCY_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_fc_diff_data_cry_2 ( + .CI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_fc_diff_data_cry_1_2812), + .DI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_data_q[2]), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_fc_diff_data_cry_2_2813), + .S(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_fc_diff_data_axb_2_3039) + ); + MUXCY_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_fc_diff_data_cry_3 ( + .CI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_fc_diff_data_cry_2_2813), + .DI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_data_q[3]), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_fc_diff_data_cry_3_2814), + .S(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_fc_diff_data_axb_3_3038) + ); + MUXCY_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_fc_diff_data_cry_4 ( + .CI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_fc_diff_data_cry_3_2814), + .DI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_data_q[4]), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_fc_diff_data_cry_4_2815), + .S(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_fc_diff_data_axb_4_3037) + ); + MUXCY_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_fc_diff_data_cry_5 ( + .CI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_fc_diff_data_cry_4_2815), + .DI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_data_q[5]), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_fc_diff_data_cry_5_2816), + .S(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_fc_diff_data_axb_5_3036) + ); + MUXCY_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_fc_diff_data_cry_6 ( + .CI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_fc_diff_data_cry_5_2816), + .DI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_data_q[6]), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_fc_diff_data_cry_6_2817), + .S(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_fc_diff_data_axb_6_3035) + ); + MUXCY_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_fc_diff_data_cry_7 ( + .CI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_fc_diff_data_cry_6_2817), + .DI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_data_q[7]), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_fc_diff_data_cry_7_2818), + .S(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_fc_diff_data_axb_7_3034) + ); + MUXCY_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_fc_diff_data_cry_8 ( + .CI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_fc_diff_data_cry_7_2818), + .DI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_data_q[8]), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_fc_diff_data_cry_8_2819), + .S(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_fc_diff_data_axb_8_3033) + ); + MUXCY_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_fc_diff_data_cry_9 ( + .CI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_fc_diff_data_cry_8_2819), + .DI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_data_q[9]), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_fc_diff_data_cry_9_2820), + .S(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_fc_diff_data_axb_9_3032) + ); + MUXCY_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_fc_diff_data_cry_10 ( + .CI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_fc_diff_data_cry_9_2820), + .DI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_data_q[10]), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_fc_diff_data_cry_10_2821), + .S(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_fc_diff_data_axb_10_3031) + ); + XORCY com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_fc_diff_data_s_11 ( + .CI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_fc_diff_data_cry_10_2821), + .LI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_fc_diff_data_axb_11_2917), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_fc_diff_data[11]) + ); + FDRE com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_PH_0_ ( + .CE(com_tlm_u_tlm_tx_vc0_frm_seq_consumed_ph_2565), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_PH_s[0]), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_PH[0]), + .R(plm_link_up_i) + ); + MUXCY_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_PH_cry_1_ ( + .CI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_PH[0]), + .DI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_GND_2822), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_PH_cry[1]), + .S(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_PH_qxu[1]) + ); + XORCY com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_PH_s_1_ ( + .CI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_PH[0]), + .LI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_PH_qxu[1]), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_PH_s[1]) + ); + FDRE com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_PH_1_ ( + .CE(com_tlm_u_tlm_tx_vc0_frm_seq_consumed_ph_2565), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_PH_s[1]), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_PH[1]), + .R(plm_link_up_i) + ); + MUXCY_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_PH_cry_2_ ( + .CI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_PH_cry[1]), + .DI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_GND_2822), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_PH_cry[2]), + .S(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_PH_qxu[2]) + ); + XORCY com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_PH_s_2_ ( + .CI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_PH_cry[1]), + .LI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_PH_qxu[2]), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_PH_s[2]) + ); + FDRE com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_PH_2_ ( + .CE(com_tlm_u_tlm_tx_vc0_frm_seq_consumed_ph_2565), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_PH_s[2]), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_PH[2]), + .R(plm_link_up_i) + ); + MUXCY_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_PH_cry_3_ ( + .CI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_PH_cry[2]), + .DI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_GND_2822), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_PH_cry[3]), + .S(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_PH_qxu[3]) + ); + XORCY com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_PH_s_3_ ( + .CI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_PH_cry[2]), + .LI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_PH_qxu[3]), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_PH_s[3]) + ); + FDRE com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_PH_3_ ( + .CE(com_tlm_u_tlm_tx_vc0_frm_seq_consumed_ph_2565), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_PH_s[3]), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_PH[3]), + .R(plm_link_up_i) + ); + MUXCY_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_PH_cry_4_ ( + .CI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_PH_cry[3]), + .DI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_GND_2822), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_PH_cry[4]), + .S(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_PH_qxu[4]) + ); + XORCY com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_PH_s_4_ ( + .CI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_PH_cry[3]), + .LI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_PH_qxu[4]), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_PH_s[4]) + ); + FDRE com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_PH_4_ ( + .CE(com_tlm_u_tlm_tx_vc0_frm_seq_consumed_ph_2565), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_PH_s[4]), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_PH[4]), + .R(plm_link_up_i) + ); + MUXCY_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_PH_cry_5_ ( + .CI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_PH_cry[4]), + .DI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_GND_2822), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_PH_cry[5]), + .S(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_PH_qxu[5]) + ); + XORCY com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_PH_s_5_ ( + .CI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_PH_cry[4]), + .LI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_PH_qxu[5]), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_PH_s[5]) + ); + FDRE com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_PH_5_ ( + .CE(com_tlm_u_tlm_tx_vc0_frm_seq_consumed_ph_2565), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_PH_s[5]), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_PH[5]), + .R(plm_link_up_i) + ); + MUXCY_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_PH_cry_6_ ( + .CI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_PH_cry[5]), + .DI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_GND_2822), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_PH_cry[6]), + .S(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_PH_qxu[6]) + ); + XORCY com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_PH_s_6_ ( + .CI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_PH_cry[5]), + .LI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_PH_qxu[6]), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_PH_s[6]) + ); + FDRE com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_PH_6_ ( + .CE(com_tlm_u_tlm_tx_vc0_frm_seq_consumed_ph_2565), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_PH_s[6]), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_PH[6]), + .R(plm_link_up_i) + ); + XORCY com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_PH_s_7_ ( + .CI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_PH_cry[6]), + .LI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_PH_qxu[7]), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_PH_s[7]) + ); + FDRE com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_PH_7_ ( + .CE(com_tlm_u_tlm_tx_vc0_frm_seq_consumed_ph_2565), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_PH_s[7]), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_PH[7]), + .R(plm_link_up_i) + ); + FDRE com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_NPH_0_ ( + .CE(com_tlm_u_tlm_tx_vc0_frm_seq_consumed_nph_2564), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_NPH_s[0]), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_NPH[0]), + .R(plm_link_up_i) + ); + MUXCY_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_NPH_cry_1_ ( + .CI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_NPH[0]), + .DI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_GND_2822), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_NPH_cry[1]), + .S(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_NPH_qxu[1]) + ); + XORCY com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_NPH_s_1_ ( + .CI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_NPH[0]), + .LI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_NPH_qxu[1]), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_NPH_s[1]) + ); + FDRE com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_NPH_1_ ( + .CE(com_tlm_u_tlm_tx_vc0_frm_seq_consumed_nph_2564), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_NPH_s[1]), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_NPH[1]), + .R(plm_link_up_i) + ); + MUXCY_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_NPH_cry_2_ ( + .CI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_NPH_cry[1]), + .DI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_GND_2822), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_NPH_cry[2]), + .S(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_NPH_qxu[2]) + ); + XORCY com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_NPH_s_2_ ( + .CI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_NPH_cry[1]), + .LI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_NPH_qxu[2]), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_NPH_s[2]) + ); + FDRE com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_NPH_2_ ( + .CE(com_tlm_u_tlm_tx_vc0_frm_seq_consumed_nph_2564), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_NPH_s[2]), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_NPH[2]), + .R(plm_link_up_i) + ); + MUXCY_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_NPH_cry_3_ ( + .CI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_NPH_cry[2]), + .DI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_GND_2822), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_NPH_cry[3]), + .S(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_NPH_qxu[3]) + ); + XORCY com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_NPH_s_3_ ( + .CI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_NPH_cry[2]), + .LI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_NPH_qxu[3]), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_NPH_s[3]) + ); + FDRE com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_NPH_3_ ( + .CE(com_tlm_u_tlm_tx_vc0_frm_seq_consumed_nph_2564), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_NPH_s[3]), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_NPH[3]), + .R(plm_link_up_i) + ); + MUXCY_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_NPH_cry_4_ ( + .CI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_NPH_cry[3]), + .DI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_GND_2822), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_NPH_cry[4]), + .S(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_NPH_qxu[4]) + ); + XORCY com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_NPH_s_4_ ( + .CI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_NPH_cry[3]), + .LI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_NPH_qxu[4]), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_NPH_s[4]) + ); + FDRE com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_NPH_4_ ( + .CE(com_tlm_u_tlm_tx_vc0_frm_seq_consumed_nph_2564), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_NPH_s[4]), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_NPH[4]), + .R(plm_link_up_i) + ); + MUXCY_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_NPH_cry_5_ ( + .CI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_NPH_cry[4]), + .DI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_GND_2822), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_NPH_cry[5]), + .S(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_NPH_qxu[5]) + ); + XORCY com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_NPH_s_5_ ( + .CI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_NPH_cry[4]), + .LI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_NPH_qxu[5]), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_NPH_s[5]) + ); + FDRE com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_NPH_5_ ( + .CE(com_tlm_u_tlm_tx_vc0_frm_seq_consumed_nph_2564), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_NPH_s[5]), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_NPH[5]), + .R(plm_link_up_i) + ); + MUXCY_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_NPH_cry_6_ ( + .CI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_NPH_cry[5]), + .DI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_GND_2822), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_NPH_cry[6]), + .S(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_NPH_qxu[6]) + ); + XORCY com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_NPH_s_6_ ( + .CI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_NPH_cry[5]), + .LI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_NPH_qxu[6]), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_NPH_s[6]) + ); + FDRE com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_NPH_6_ ( + .CE(com_tlm_u_tlm_tx_vc0_frm_seq_consumed_nph_2564), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_NPH_s[6]), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_NPH[6]), + .R(plm_link_up_i) + ); + XORCY com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_NPH_s_7_ ( + .CI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_NPH_cry[6]), + .LI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_NPH_qxu[7]), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_NPH_s[7]) + ); + FDRE com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_NPH_7_ ( + .CE(com_tlm_u_tlm_tx_vc0_frm_seq_consumed_nph_2564), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_NPH_s[7]), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_NPH[7]), + .R(plm_link_up_i) + ); + FDRE com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_CPLH_0_ ( + .CE(com_tlm_u_tlm_tx_vc0_frm_seq_consumed_cplh_2566), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_CPLH_s[0]), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_CPLH[0]), + .R(plm_link_up_i) + ); + MUXCY_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_CPLH_cry_1_ ( + .CI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_CPLH[0]), + .DI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_GND_2822), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_CPLH_cry[1]), + .S(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_CPLH_qxu[1]) + ); + XORCY com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_CPLH_s_1_ ( + .CI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_CPLH[0]), + .LI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_CPLH_qxu[1]), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_CPLH_s[1]) + ); + FDRE com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_CPLH_1_ ( + .CE(com_tlm_u_tlm_tx_vc0_frm_seq_consumed_cplh_2566), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_CPLH_s[1]), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_CPLH[1]), + .R(plm_link_up_i) + ); + MUXCY_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_CPLH_cry_2_ ( + .CI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_CPLH_cry[1]), + .DI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_GND_2822), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_CPLH_cry[2]), + .S(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_CPLH_qxu[2]) + ); + XORCY com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_CPLH_s_2_ ( + .CI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_CPLH_cry[1]), + .LI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_CPLH_qxu[2]), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_CPLH_s[2]) + ); + FDRE com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_CPLH_2_ ( + .CE(com_tlm_u_tlm_tx_vc0_frm_seq_consumed_cplh_2566), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_CPLH_s[2]), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_CPLH[2]), + .R(plm_link_up_i) + ); + MUXCY_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_CPLH_cry_3_ ( + .CI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_CPLH_cry[2]), + .DI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_GND_2822), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_CPLH_cry[3]), + .S(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_CPLH_qxu[3]) + ); + XORCY com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_CPLH_s_3_ ( + .CI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_CPLH_cry[2]), + .LI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_CPLH_qxu[3]), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_CPLH_s[3]) + ); + FDRE com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_CPLH_3_ ( + .CE(com_tlm_u_tlm_tx_vc0_frm_seq_consumed_cplh_2566), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_CPLH_s[3]), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_CPLH[3]), + .R(plm_link_up_i) + ); + MUXCY_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_CPLH_cry_4_ ( + .CI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_CPLH_cry[3]), + .DI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_GND_2822), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_CPLH_cry[4]), + .S(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_CPLH_qxu[4]) + ); + XORCY com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_CPLH_s_4_ ( + .CI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_CPLH_cry[3]), + .LI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_CPLH_qxu[4]), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_CPLH_s[4]) + ); + FDRE com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_CPLH_4_ ( + .CE(com_tlm_u_tlm_tx_vc0_frm_seq_consumed_cplh_2566), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_CPLH_s[4]), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_CPLH[4]), + .R(plm_link_up_i) + ); + MUXCY_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_CPLH_cry_5_ ( + .CI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_CPLH_cry[4]), + .DI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_GND_2822), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_CPLH_cry[5]), + .S(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_CPLH_qxu[5]) + ); + XORCY com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_CPLH_s_5_ ( + .CI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_CPLH_cry[4]), + .LI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_CPLH_qxu[5]), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_CPLH_s[5]) + ); + FDRE com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_CPLH_5_ ( + .CE(com_tlm_u_tlm_tx_vc0_frm_seq_consumed_cplh_2566), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_CPLH_s[5]), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_CPLH[5]), + .R(plm_link_up_i) + ); + MUXCY_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_CPLH_cry_6_ ( + .CI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_CPLH_cry[5]), + .DI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_GND_2822), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_CPLH_cry[6]), + .S(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_CPLH_qxu[6]) + ); + XORCY com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_CPLH_s_6_ ( + .CI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_CPLH_cry[5]), + .LI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_CPLH_qxu[6]), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_CPLH_s[6]) + ); + FDRE com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_CPLH_6_ ( + .CE(com_tlm_u_tlm_tx_vc0_frm_seq_consumed_cplh_2566), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_CPLH_s[6]), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_CPLH[6]), + .R(plm_link_up_i) + ); + XORCY com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_CPLH_s_7_ ( + .CI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_CPLH_cry[6]), + .LI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_CPLH_qxu[7]), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_CPLH_s[7]) + ); + FDRE com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_CPLH_7_ ( + .CE(com_tlm_u_tlm_tx_vc0_frm_seq_consumed_cplh_2566), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_CPLH_s[7]), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_CPLH[7]), + .R(plm_link_up_i) + ); + MULT_AND com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_cpld_av_o_6_cry_0 ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_CPLD_i[0]), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_infinite_CPLD_i_3022), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_cpld_av_o_6_cry_0_0_2823) + ); + MUXCY_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_cpld_av_o_6_cry_0_0 ( + .CI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_infinite_CPLD_i_3022), + .DI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_cpld_av_o_6_cry_0_0_2823), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_cpld_av_o_6_cry_0_2825), + .S(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_cpld_av_o_6_axb_0_2991) + ); + XORCY com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_cpld_av_o_6_s_0 ( + .CI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_infinite_CPLD_i_3022), + .LI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_cpld_av_o_6_axb_0_2991), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_cpld_av_o_6[0]) + ); + MULT_AND com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_cpld_av_o_6_cry_1 ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_CPLD_i[1]), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_infinite_CPLD_i_3022), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_cpld_av_o_6_cry_1_0_2824) + ); + MUXCY_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_cpld_av_o_6_cry_1_0 ( + .CI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_cpld_av_o_6_cry_0_2825), + .DI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_cpld_av_o_6_cry_1_0_2824), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_cpld_av_o_6_cry_1_2827), + .S(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_cpld_av_o_6_axb_1_2990) + ); + XORCY com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_cpld_av_o_6_s_1 ( + .CI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_cpld_av_o_6_cry_0_2825), + .LI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_cpld_av_o_6_axb_1_2990), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_cpld_av_o_6[1]) + ); + MULT_AND com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_cpld_av_o_6_cry_2 ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_CPLD_i[2]), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_infinite_CPLD_i_3022), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_cpld_av_o_6_cry_2_0_2826) + ); + MUXCY_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_cpld_av_o_6_cry_2_0 ( + .CI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_cpld_av_o_6_cry_1_2827), + .DI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_cpld_av_o_6_cry_2_0_2826), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_cpld_av_o_6_cry_2_2829), + .S(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_cpld_av_o_6_axb_2_2989) + ); + XORCY com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_cpld_av_o_6_s_2 ( + .CI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_cpld_av_o_6_cry_1_2827), + .LI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_cpld_av_o_6_axb_2_2989), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_cpld_av_o_6[2]) + ); + MULT_AND com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_cpld_av_o_6_cry_3 ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_CPLD_i[3]), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_infinite_CPLD_i_3022), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_cpld_av_o_6_cry_3_0_2828) + ); + MUXCY_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_cpld_av_o_6_cry_3_0 ( + .CI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_cpld_av_o_6_cry_2_2829), + .DI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_cpld_av_o_6_cry_3_0_2828), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_cpld_av_o_6_cry_3_2831), + .S(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_cpld_av_o_6_axb_3_2988) + ); + XORCY com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_cpld_av_o_6_s_3 ( + .CI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_cpld_av_o_6_cry_2_2829), + .LI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_cpld_av_o_6_axb_3_2988), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_cpld_av_o_6[3]) + ); + MULT_AND com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_cpld_av_o_6_cry_4 ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_CPLD_i[4]), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_infinite_CPLD_i_3022), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_cpld_av_o_6_cry_4_0_2830) + ); + MUXCY_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_cpld_av_o_6_cry_4_0 ( + .CI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_cpld_av_o_6_cry_3_2831), + .DI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_cpld_av_o_6_cry_4_0_2830), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_cpld_av_o_6_cry_4_2833), + .S(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_cpld_av_o_6_axb_4_2987) + ); + XORCY com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_cpld_av_o_6_s_4 ( + .CI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_cpld_av_o_6_cry_3_2831), + .LI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_cpld_av_o_6_axb_4_2987), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_cpld_av_o_6[4]) + ); + MULT_AND com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_cpld_av_o_6_cry_5 ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_CPLD_i[5]), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_infinite_CPLD_i_3022), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_cpld_av_o_6_cry_5_0_2832) + ); + MUXCY_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_cpld_av_o_6_cry_5_0 ( + .CI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_cpld_av_o_6_cry_4_2833), + .DI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_cpld_av_o_6_cry_5_0_2832), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_cpld_av_o_6_cry_5_2835), + .S(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_cpld_av_o_6_axb_5_2986) + ); + XORCY com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_cpld_av_o_6_s_5 ( + .CI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_cpld_av_o_6_cry_4_2833), + .LI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_cpld_av_o_6_axb_5_2986), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_cpld_av_o_6[5]) + ); + MULT_AND com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_cpld_av_o_6_cry_6 ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_CPLD_i[6]), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_infinite_CPLD_i_3022), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_cpld_av_o_6_cry_6_0_2834) + ); + MUXCY_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_cpld_av_o_6_cry_6_0 ( + .CI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_cpld_av_o_6_cry_5_2835), + .DI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_cpld_av_o_6_cry_6_0_2834), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_cpld_av_o_6_cry_6_2837), + .S(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_cpld_av_o_6_axb_6_2985) + ); + XORCY com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_cpld_av_o_6_s_6 ( + .CI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_cpld_av_o_6_cry_5_2835), + .LI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_cpld_av_o_6_axb_6_2985), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_cpld_av_o_6[6]) + ); + MULT_AND com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_cpld_av_o_6_cry_7 ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_CPLD_i[7]), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_infinite_CPLD_i_3022), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_cpld_av_o_6_cry_7_0_2836) + ); + MUXCY_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_cpld_av_o_6_cry_7_0 ( + .CI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_cpld_av_o_6_cry_6_2837), + .DI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_cpld_av_o_6_cry_7_0_2836), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_cpld_av_o_6_cry_7_2839), + .S(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_cpld_av_o_6_axb_7_2984) + ); + XORCY com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_cpld_av_o_6_s_7 ( + .CI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_cpld_av_o_6_cry_6_2837), + .LI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_cpld_av_o_6_axb_7_2984), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_cpld_av_o_6[7]) + ); + MULT_AND com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_cpld_av_o_6_cry_8 ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_CPLD_i[8]), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_infinite_CPLD_i_3022), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_cpld_av_o_6_cry_8_0_2838) + ); + MUXCY_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_cpld_av_o_6_cry_8_0 ( + .CI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_cpld_av_o_6_cry_7_2839), + .DI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_cpld_av_o_6_cry_8_0_2838), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_cpld_av_o_6_cry_8_2841), + .S(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_cpld_av_o_6_axb_8_2983) + ); + XORCY com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_cpld_av_o_6_s_8 ( + .CI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_cpld_av_o_6_cry_7_2839), + .LI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_cpld_av_o_6_axb_8_2983), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_cpld_av_o_6[8]) + ); + MULT_AND com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_cpld_av_o_6_cry_9 ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_CPLD_i[9]), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_infinite_CPLD_i_3022), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_cpld_av_o_6_cry_9_0_2840) + ); + MUXCY_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_cpld_av_o_6_cry_9_0 ( + .CI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_cpld_av_o_6_cry_8_2841), + .DI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_cpld_av_o_6_cry_9_0_2840), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_cpld_av_o_6_cry_9_2843), + .S(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_cpld_av_o_6_axb_9_2982) + ); + XORCY com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_cpld_av_o_6_s_9 ( + .CI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_cpld_av_o_6_cry_8_2841), + .LI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_cpld_av_o_6_axb_9_2982), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_cpld_av_o_6[9]) + ); + MULT_AND com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_cpld_av_o_6_cry_10 ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_CPLD_i[10]), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_infinite_CPLD_i_3022), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_cpld_av_o_6_cry_10_0_2842) + ); + MUXCY_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_cpld_av_o_6_cry_10_0 ( + .CI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_cpld_av_o_6_cry_9_2843), + .DI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_cpld_av_o_6_cry_10_0_2842), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_cpld_av_o_6_cry_10_2844), + .S(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_cpld_av_o_6_axb_10_2981) + ); + XORCY com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_cpld_av_o_6_s_10 ( + .CI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_cpld_av_o_6_cry_9_2843), + .LI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_cpld_av_o_6_axb_10_2981), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_cpld_av_o_6[10]) + ); + XORCY com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_cpld_av_o_6_s_11 ( + .CI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_cpld_av_o_6_cry_10_2844), + .LI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_cpld_av_o_6_axb_11_3025), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_cpld_av_o_6[11]) + ); + MULT_AND com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_npd_av_o_6_cry_0 ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_NPD_i[0]), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_infinite_NPD_i_3023), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_npd_av_o_6_cry_0_0_2845) + ); + MUXCY_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_npd_av_o_6_cry_0_0 ( + .CI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_infinite_NPD_i_3023), + .DI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_npd_av_o_6_cry_0_0_2845), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_npd_av_o_6_cry_0_2847), + .S(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_npd_av_o_6_axb_0_3002) + ); + XORCY com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_npd_av_o_6_s_0 ( + .CI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_infinite_NPD_i_3023), + .LI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_npd_av_o_6_axb_0_3002), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_npd_av_o_6[0]) + ); + MULT_AND com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_npd_av_o_6_cry_1 ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_NPD_i[1]), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_infinite_NPD_i_3023), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_npd_av_o_6_cry_1_0_2846) + ); + MUXCY_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_npd_av_o_6_cry_1_0 ( + .CI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_npd_av_o_6_cry_0_2847), + .DI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_npd_av_o_6_cry_1_0_2846), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_npd_av_o_6_cry_1_2849), + .S(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_npd_av_o_6_axb_1_3001) + ); + XORCY com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_npd_av_o_6_s_1 ( + .CI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_npd_av_o_6_cry_0_2847), + .LI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_npd_av_o_6_axb_1_3001), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_npd_av_o_6[1]) + ); + MULT_AND com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_npd_av_o_6_cry_2 ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_NPD_i[2]), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_infinite_NPD_i_3023), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_npd_av_o_6_cry_2_0_2848) + ); + MUXCY_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_npd_av_o_6_cry_2_0 ( + .CI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_npd_av_o_6_cry_1_2849), + .DI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_npd_av_o_6_cry_2_0_2848), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_npd_av_o_6_cry_2_2851), + .S(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_npd_av_o_6_axb_2_3000) + ); + XORCY com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_npd_av_o_6_s_2 ( + .CI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_npd_av_o_6_cry_1_2849), + .LI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_npd_av_o_6_axb_2_3000), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_npd_av_o_6[2]) + ); + MULT_AND com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_npd_av_o_6_cry_3 ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_NPD_i[3]), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_infinite_NPD_i_3023), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_npd_av_o_6_cry_3_0_2850) + ); + MUXCY_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_npd_av_o_6_cry_3_0 ( + .CI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_npd_av_o_6_cry_2_2851), + .DI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_npd_av_o_6_cry_3_0_2850), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_npd_av_o_6_cry_3_2853), + .S(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_npd_av_o_6_axb_3_2999) + ); + XORCY com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_npd_av_o_6_s_3 ( + .CI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_npd_av_o_6_cry_2_2851), + .LI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_npd_av_o_6_axb_3_2999), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_npd_av_o_6[3]) + ); + MULT_AND com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_npd_av_o_6_cry_4 ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_NPD_i[4]), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_infinite_NPD_i_3023), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_npd_av_o_6_cry_4_0_2852) + ); + MUXCY_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_npd_av_o_6_cry_4_0 ( + .CI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_npd_av_o_6_cry_3_2853), + .DI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_npd_av_o_6_cry_4_0_2852), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_npd_av_o_6_cry_4_2855), + .S(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_npd_av_o_6_axb_4_2998) + ); + XORCY com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_npd_av_o_6_s_4 ( + .CI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_npd_av_o_6_cry_3_2853), + .LI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_npd_av_o_6_axb_4_2998), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_npd_av_o_6[4]) + ); + MULT_AND com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_npd_av_o_6_cry_5 ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_NPD_i[5]), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_infinite_NPD_i_3023), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_npd_av_o_6_cry_5_0_2854) + ); + MUXCY_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_npd_av_o_6_cry_5_0 ( + .CI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_npd_av_o_6_cry_4_2855), + .DI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_npd_av_o_6_cry_5_0_2854), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_npd_av_o_6_cry_5_2857), + .S(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_npd_av_o_6_axb_5_2997) + ); + XORCY com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_npd_av_o_6_s_5 ( + .CI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_npd_av_o_6_cry_4_2855), + .LI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_npd_av_o_6_axb_5_2997), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_npd_av_o_6[5]) + ); + MULT_AND com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_npd_av_o_6_cry_6 ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_NPD_i[6]), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_infinite_NPD_i_3023), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_npd_av_o_6_cry_6_0_2856) + ); + MUXCY_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_npd_av_o_6_cry_6_0 ( + .CI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_npd_av_o_6_cry_5_2857), + .DI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_npd_av_o_6_cry_6_0_2856), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_npd_av_o_6_cry_6_2859), + .S(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_npd_av_o_6_axb_6_2996) + ); + XORCY com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_npd_av_o_6_s_6 ( + .CI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_npd_av_o_6_cry_5_2857), + .LI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_npd_av_o_6_axb_6_2996), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_npd_av_o_6[6]) + ); + MULT_AND com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_npd_av_o_6_cry_7 ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_NPD_i[7]), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_infinite_NPD_i_3023), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_npd_av_o_6_cry_7_0_2858) + ); + MUXCY_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_npd_av_o_6_cry_7_0 ( + .CI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_npd_av_o_6_cry_6_2859), + .DI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_npd_av_o_6_cry_7_0_2858), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_npd_av_o_6_cry_7_2861), + .S(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_npd_av_o_6_axb_7_2995) + ); + XORCY com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_npd_av_o_6_s_7 ( + .CI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_npd_av_o_6_cry_6_2859), + .LI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_npd_av_o_6_axb_7_2995), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_npd_av_o_6[7]) + ); + MULT_AND com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_npd_av_o_6_cry_8 ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_NPD_i[8]), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_infinite_NPD_i_3023), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_npd_av_o_6_cry_8_0_2860) + ); + MUXCY_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_npd_av_o_6_cry_8_0 ( + .CI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_npd_av_o_6_cry_7_2861), + .DI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_npd_av_o_6_cry_8_0_2860), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_npd_av_o_6_cry_8_2863), + .S(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_npd_av_o_6_axb_8_2994) + ); + XORCY com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_npd_av_o_6_s_8 ( + .CI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_npd_av_o_6_cry_7_2861), + .LI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_npd_av_o_6_axb_8_2994), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_npd_av_o_6[8]) + ); + MULT_AND com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_npd_av_o_6_cry_9 ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_NPD_i[9]), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_infinite_NPD_i_3023), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_npd_av_o_6_cry_9_0_2862) + ); + MUXCY_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_npd_av_o_6_cry_9_0 ( + .CI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_npd_av_o_6_cry_8_2863), + .DI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_npd_av_o_6_cry_9_0_2862), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_npd_av_o_6_cry_9_2865), + .S(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_npd_av_o_6_axb_9_2993) + ); + XORCY com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_npd_av_o_6_s_9 ( + .CI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_npd_av_o_6_cry_8_2863), + .LI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_npd_av_o_6_axb_9_2993), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_npd_av_o_6[9]) + ); + MULT_AND com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_npd_av_o_6_cry_10 ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_NPD_i[10]), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_infinite_NPD_i_3023), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_npd_av_o_6_cry_10_0_2864) + ); + MUXCY_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_npd_av_o_6_cry_10_0 ( + .CI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_npd_av_o_6_cry_9_2865), + .DI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_npd_av_o_6_cry_10_0_2864), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_npd_av_o_6_cry_10_2866), + .S(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_npd_av_o_6_axb_10_2992) + ); + XORCY com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_npd_av_o_6_s_10 ( + .CI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_npd_av_o_6_cry_9_2865), + .LI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_npd_av_o_6_axb_10_2992), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_npd_av_o_6[10]) + ); + XORCY com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_npd_av_o_6_s_11 ( + .CI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_npd_av_o_6_cry_10_2866), + .LI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_npd_av_o_6_axb_11_3027), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_npd_av_o_6[11]) + ); + MULT_AND com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_pd_av_o_6_cry_0 ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_PD_i[0]), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_infinite_PD_i_3024), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_pd_av_o_6_cry_0_0_2867) + ); + MUXCY_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_pd_av_o_6_cry_0_0 ( + .CI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_infinite_PD_i_3024), + .DI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_pd_av_o_6_cry_0_0_2867), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_pd_av_o_6_cry_0_2869), + .S(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_pd_av_o_6_axb_0_3013) + ); + XORCY com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_pd_av_o_6_s_0 ( + .CI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_infinite_PD_i_3024), + .LI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_pd_av_o_6_axb_0_3013), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_pd_av_o_6[0]) + ); + MULT_AND com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_pd_av_o_6_cry_1 ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_PD_i[1]), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_infinite_PD_i_3024), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_pd_av_o_6_cry_1_0_2868) + ); + MUXCY_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_pd_av_o_6_cry_1_0 ( + .CI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_pd_av_o_6_cry_0_2869), + .DI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_pd_av_o_6_cry_1_0_2868), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_pd_av_o_6_cry_1_2871), + .S(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_pd_av_o_6_axb_1_3012) + ); + XORCY com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_pd_av_o_6_s_1 ( + .CI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_pd_av_o_6_cry_0_2869), + .LI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_pd_av_o_6_axb_1_3012), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_pd_av_o_6[1]) + ); + MULT_AND com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_pd_av_o_6_cry_2 ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_PD_i[2]), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_infinite_PD_i_3024), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_pd_av_o_6_cry_2_0_2870) + ); + MUXCY_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_pd_av_o_6_cry_2_0 ( + .CI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_pd_av_o_6_cry_1_2871), + .DI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_pd_av_o_6_cry_2_0_2870), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_pd_av_o_6_cry_2_2873), + .S(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_pd_av_o_6_axb_2_3011) + ); + XORCY com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_pd_av_o_6_s_2 ( + .CI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_pd_av_o_6_cry_1_2871), + .LI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_pd_av_o_6_axb_2_3011), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_pd_av_o_6[2]) + ); + MULT_AND com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_pd_av_o_6_cry_3 ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_PD_i[3]), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_infinite_PD_i_3024), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_pd_av_o_6_cry_3_0_2872) + ); + MUXCY_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_pd_av_o_6_cry_3_0 ( + .CI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_pd_av_o_6_cry_2_2873), + .DI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_pd_av_o_6_cry_3_0_2872), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_pd_av_o_6_cry_3_2875), + .S(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_pd_av_o_6_axb_3_3010) + ); + XORCY com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_pd_av_o_6_s_3 ( + .CI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_pd_av_o_6_cry_2_2873), + .LI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_pd_av_o_6_axb_3_3010), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_pd_av_o_6[3]) + ); + MULT_AND com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_pd_av_o_6_cry_4 ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_PD_i[4]), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_infinite_PD_i_3024), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_pd_av_o_6_cry_4_0_2874) + ); + MUXCY_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_pd_av_o_6_cry_4_0 ( + .CI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_pd_av_o_6_cry_3_2875), + .DI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_pd_av_o_6_cry_4_0_2874), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_pd_av_o_6_cry_4_2877), + .S(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_pd_av_o_6_axb_4_3009) + ); + XORCY com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_pd_av_o_6_s_4 ( + .CI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_pd_av_o_6_cry_3_2875), + .LI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_pd_av_o_6_axb_4_3009), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_pd_av_o_6[4]) + ); + MULT_AND com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_pd_av_o_6_cry_5 ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_PD_i[5]), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_infinite_PD_i_3024), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_pd_av_o_6_cry_5_0_2876) + ); + MUXCY_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_pd_av_o_6_cry_5_0 ( + .CI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_pd_av_o_6_cry_4_2877), + .DI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_pd_av_o_6_cry_5_0_2876), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_pd_av_o_6_cry_5_2879), + .S(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_pd_av_o_6_axb_5_3008) + ); + XORCY com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_pd_av_o_6_s_5 ( + .CI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_pd_av_o_6_cry_4_2877), + .LI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_pd_av_o_6_axb_5_3008), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_pd_av_o_6[5]) + ); + MULT_AND com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_pd_av_o_6_cry_6 ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_PD_i[6]), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_infinite_PD_i_3024), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_pd_av_o_6_cry_6_0_2878) + ); + MUXCY_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_pd_av_o_6_cry_6_0 ( + .CI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_pd_av_o_6_cry_5_2879), + .DI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_pd_av_o_6_cry_6_0_2878), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_pd_av_o_6_cry_6_2881), + .S(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_pd_av_o_6_axb_6_3007) + ); + XORCY com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_pd_av_o_6_s_6 ( + .CI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_pd_av_o_6_cry_5_2879), + .LI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_pd_av_o_6_axb_6_3007), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_pd_av_o_6[6]) + ); + MULT_AND com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_pd_av_o_6_cry_7 ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_PD_i[7]), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_infinite_PD_i_3024), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_pd_av_o_6_cry_7_0_2880) + ); + MUXCY_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_pd_av_o_6_cry_7_0 ( + .CI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_pd_av_o_6_cry_6_2881), + .DI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_pd_av_o_6_cry_7_0_2880), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_pd_av_o_6_cry_7_2883), + .S(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_pd_av_o_6_axb_7_3006) + ); + XORCY com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_pd_av_o_6_s_7 ( + .CI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_pd_av_o_6_cry_6_2881), + .LI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_pd_av_o_6_axb_7_3006), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_pd_av_o_6[7]) + ); + MULT_AND com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_pd_av_o_6_cry_8 ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_PD_i[8]), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_infinite_PD_i_3024), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_pd_av_o_6_cry_8_0_2882) + ); + MUXCY_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_pd_av_o_6_cry_8_0 ( + .CI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_pd_av_o_6_cry_7_2883), + .DI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_pd_av_o_6_cry_8_0_2882), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_pd_av_o_6_cry_8_2885), + .S(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_pd_av_o_6_axb_8_3005) + ); + XORCY com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_pd_av_o_6_s_8 ( + .CI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_pd_av_o_6_cry_7_2883), + .LI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_pd_av_o_6_axb_8_3005), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_pd_av_o_6[8]) + ); + MULT_AND com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_pd_av_o_6_cry_9 ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_PD_i[9]), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_infinite_PD_i_3024), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_pd_av_o_6_cry_9_0_2884) + ); + MUXCY_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_pd_av_o_6_cry_9_0 ( + .CI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_pd_av_o_6_cry_8_2885), + .DI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_pd_av_o_6_cry_9_0_2884), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_pd_av_o_6_cry_9_2887), + .S(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_pd_av_o_6_axb_9_3004) + ); + XORCY com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_pd_av_o_6_s_9 ( + .CI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_pd_av_o_6_cry_8_2885), + .LI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_pd_av_o_6_axb_9_3004), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_pd_av_o_6[9]) + ); + MULT_AND com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_pd_av_o_6_cry_10 ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_PD_i[10]), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_infinite_PD_i_3024), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_pd_av_o_6_cry_10_0_2886) + ); + MUXCY_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_pd_av_o_6_cry_10_0 ( + .CI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_pd_av_o_6_cry_9_2887), + .DI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_pd_av_o_6_cry_10_0_2886), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_pd_av_o_6_cry_10_2888), + .S(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_pd_av_o_6_axb_10_3003) + ); + XORCY com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_pd_av_o_6_s_10 ( + .CI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_pd_av_o_6_cry_9_2887), + .LI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_pd_av_o_6_axb_10_3003), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_pd_av_o_6[10]) + ); + XORCY com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_pd_av_o_6_s_11 ( + .CI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_pd_av_o_6_cry_10_2888), + .LI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_pd_av_o_6_axb_11_3029), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_pd_av_o_6[11]) + ); + FDR com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_suspend_cat_1_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_suspend_cat[0]), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_suspend_cat[1]), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_suspend_cat_0_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_N_57213_i_2910), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_suspend_cat[0]), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_init_cpl ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_init_cplc_2892), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_init_cpl_2909), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_init_np ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_init_npc_2893), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_init_np_2906), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_init_p ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_init_pc_2894), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_init_p_2903), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_init_vld_qq ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_init_vld_q_2895), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_init_vld_qq_2926), + .R(plm_link_up_i) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_min_data_cred_7_i_0_a2_5_.INIT = 4'h1; + LUT2 com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_min_data_cred_7_i_0_a2_5_ ( + .I0(NlwRenamedSig_OI_cfg_dcommand[6]), + .I1(NlwRenamedSig_OI_cfg_dcommand[7]), + .O(com_N_3419_i) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un8_suspend_cat_axbxc1.INIT = 4'h6; + LUT2 com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un8_suspend_cat_axbxc1 ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_suspend_cat[0]), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_suspend_cat[1]), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un8_suspend_cat_axbxc1_2945) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_infinite_header_q_2_0_a2_0.INIT = 4'h1; + LUT2 com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_infinite_header_q_2_0_a2_0 ( + .I0(com_lnk_rfc_header[0]), + .I1(com_lnk_rfc_header[1]), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_infinite_header_q_2_0_a2_0_2912) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_prev_limit_header_q_5_0_0_7_.INIT = 8'hD8; + LUT3_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_prev_limit_header_q_5_0_0_7_ ( + .I0(com_lnk_rfc_type[0]), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_limit_NPH[7]), + .I2(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_limit_PH[7]), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_prev_limit_header_q_5_0_0[7]) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_prev_limit_header_q_5_0_0_6_.INIT = 8'hD8; + LUT3_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_prev_limit_header_q_5_0_0_6_ ( + .I0(com_lnk_rfc_type[0]), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_limit_NPH[6]), + .I2(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_limit_PH[6]), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_prev_limit_header_q_5_0_0[6]) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_prev_limit_header_q_5_0_0_5_.INIT = 8'hD8; + LUT3_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_prev_limit_header_q_5_0_0_5_ ( + .I0(com_lnk_rfc_type[0]), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_limit_NPH[5]), + .I2(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_limit_PH[5]), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_prev_limit_header_q_5_0_0[5]) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_prev_limit_header_q_5_0_0_4_.INIT = 8'hD8; + LUT3_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_prev_limit_header_q_5_0_0_4_ ( + .I0(com_lnk_rfc_type[0]), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_limit_NPH[4]), + .I2(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_limit_PH[4]), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_prev_limit_header_q_5_0_0[4]) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_prev_limit_header_q_5_0_0_3_.INIT = 8'hD8; + LUT3_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_prev_limit_header_q_5_0_0_3_ ( + .I0(com_lnk_rfc_type[0]), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_limit_NPH[3]), + .I2(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_limit_PH[3]), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_prev_limit_header_q_5_0_0[3]) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_prev_limit_header_q_5_0_0_2_.INIT = 8'hD8; + LUT3_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_prev_limit_header_q_5_0_0_2_ ( + .I0(com_lnk_rfc_type[0]), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_limit_NPH[2]), + .I2(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_limit_PH[2]), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_prev_limit_header_q_5_0_0[2]) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_prev_limit_header_q_5_0_0_1_.INIT = 8'hD8; + LUT3_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_prev_limit_header_q_5_0_0_1_ ( + .I0(com_lnk_rfc_type[0]), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_limit_NPH[1]), + .I2(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_limit_PH[1]), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_prev_limit_header_q_5_0_0[1]) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_prev_limit_header_q_5_0_0_0_.INIT = 8'hD8; + LUT3_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_prev_limit_header_q_5_0_0_0_ ( + .I0(com_lnk_rfc_type[0]), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_limit_NPH[0]), + .I2(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_limit_PH[0]), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_prev_limit_header_q_5_0_0[0]) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_prev_limit_data_q_5_0_0_11_.INIT = 8'hD8; + LUT3_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_prev_limit_data_q_5_0_0_11_ ( + .I0(com_lnk_rfc_type[0]), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_limit_NPD[11]), + .I2(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_limit_PD[11]), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_prev_limit_data_q_5_0_0[11]) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_prev_limit_data_q_5_0_0_10_.INIT = 8'hD8; + LUT3_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_prev_limit_data_q_5_0_0_10_ ( + .I0(com_lnk_rfc_type[0]), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_limit_NPD[10]), + .I2(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_limit_PD[10]), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_prev_limit_data_q_5_0_0[10]) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_prev_limit_data_q_5_0_0_9_.INIT = 8'hD8; + LUT3_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_prev_limit_data_q_5_0_0_9_ ( + .I0(com_lnk_rfc_type[0]), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_limit_NPD[9]), + .I2(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_limit_PD[9]), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_prev_limit_data_q_5_0_0[9]) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_prev_limit_data_q_5_0_0_8_.INIT = 8'hD8; + LUT3_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_prev_limit_data_q_5_0_0_8_ ( + .I0(com_lnk_rfc_type[0]), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_limit_NPD[8]), + .I2(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_limit_PD[8]), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_prev_limit_data_q_5_0_0[8]) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_prev_limit_data_q_5_0_0_7_.INIT = 8'hD8; + LUT3_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_prev_limit_data_q_5_0_0_7_ ( + .I0(com_lnk_rfc_type[0]), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_limit_NPD[7]), + .I2(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_limit_PD[7]), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_prev_limit_data_q_5_0_0[7]) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_prev_limit_data_q_5_0_0_6_.INIT = 8'hD8; + LUT3_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_prev_limit_data_q_5_0_0_6_ ( + .I0(com_lnk_rfc_type[0]), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_limit_NPD[6]), + .I2(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_limit_PD[6]), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_prev_limit_data_q_5_0_0[6]) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_prev_limit_data_q_5_0_0_5_.INIT = 8'hD8; + LUT3_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_prev_limit_data_q_5_0_0_5_ ( + .I0(com_lnk_rfc_type[0]), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_limit_NPD[5]), + .I2(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_limit_PD[5]), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_prev_limit_data_q_5_0_0[5]) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_prev_limit_data_q_5_0_0_4_.INIT = 8'hD8; + LUT3_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_prev_limit_data_q_5_0_0_4_ ( + .I0(com_lnk_rfc_type[0]), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_limit_NPD[4]), + .I2(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_limit_PD[4]), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_prev_limit_data_q_5_0_0[4]) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_prev_limit_data_q_5_0_0_3_.INIT = 8'hD8; + LUT3_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_prev_limit_data_q_5_0_0_3_ ( + .I0(com_lnk_rfc_type[0]), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_limit_NPD[3]), + .I2(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_limit_PD[3]), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_prev_limit_data_q_5_0_0[3]) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_prev_limit_data_q_5_0_0_2_.INIT = 8'hD8; + LUT3_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_prev_limit_data_q_5_0_0_2_ ( + .I0(com_lnk_rfc_type[0]), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_limit_NPD[2]), + .I2(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_limit_PD[2]), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_prev_limit_data_q_5_0_0[2]) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_prev_limit_data_q_5_0_0_1_.INIT = 8'hD8; + LUT3_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_prev_limit_data_q_5_0_0_1_ ( + .I0(com_lnk_rfc_type[0]), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_limit_NPD[1]), + .I2(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_limit_PD[1]), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_prev_limit_data_q_5_0_0[1]) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_prev_limit_data_q_5_0_0_0_.INIT = 8'hD8; + LUT3_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_prev_limit_data_q_5_0_0_0_ ( + .I0(com_lnk_rfc_type[0]), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_limit_NPD[0]), + .I2(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_limit_PD[0]), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_prev_limit_data_q_5_0_0[0]) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_infinite_header_q_5_0_0.INIT = 8'hD8; + LUT3_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_infinite_header_q_5_0_0 ( + .I0(com_lnk_rfc_type[0]), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_infinite_NPH_2896), + .I2(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_infinite_PH_2897), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_infinite_header_q_5_0_0_2920) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_infinite_data_q_5_0_0.INIT = 8'hD8; + LUT3_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_infinite_data_q_5_0_0 ( + .I0(com_lnk_rfc_type[0]), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_infinite_NPD_3028), + .I2(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_infinite_PD_3030), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_infinite_data_q_5_0_0_2916) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_new_limit_data_ok_0.INIT = 8'hD1; + LUT3_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_new_limit_data_ok_0 ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_fc_diff_data_q[11]), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_infinite_data_qq_3020), + .I2(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_infinite_data_qq_3017), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_new_limit_data_ok) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_susp_credits33_0_a2_0_a2_0_a2.INIT = 4'h8; + LUT2 com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_susp_credits33_0_a2_0_a2_0_a2 ( + .I0(com_N_3419_i), + .I1(NlwRenamedSig_OI_cfg_dcommand[5]), + .O(com_lat_d[2]) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_av_data_cred_7_i_0_a3_0_0_.INIT = 4'h4; + LUT2 com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_av_data_cred_7_i_0_a3_0_0_ ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_suspend_cat[0]), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_suspend_cat[1]), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_N_50493) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_PD_1_axb_0.INIT = 8'h78; + LUT3 com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_PD_1_axb_0 ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_consumed_credits[0]), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_consumed_ph_2565), + .I2(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_PD[0]), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_PD_1_axb_0_2889) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_NPD_1_axb_0.INIT = 8'h78; + LUT3 com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_NPD_1_axb_0 ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_consumed_credits[0]), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_consumed_nph_2564), + .I2(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_NPD[0]), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_NPD_1_axb_0_2890) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_CPLD_1_axb_0.INIT = 8'h78; + LUT3 com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_CPLD_1_axb_0 ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_consumed_cplh_2566), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_consumed_credits[0]), + .I2(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_CPLD[0]), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_CPLD_1_axb_0_2891) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_init_cplc.INIT = 8'h40; + LUT3 com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_init_cplc ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_cat_q[0]), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_cat_q[1]), + .I2(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_init_vld_q_2895), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_init_cplc_2892) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_init_npc.INIT = 8'h20; + LUT3 com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_init_npc ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_cat_q[0]), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_cat_q[1]), + .I2(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_init_vld_q_2895), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_init_npc_2893) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_init_pc.INIT = 8'h10; + LUT3 com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_init_pc ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_cat_q[0]), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_cat_q[1]), + .I2(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_init_vld_q_2895), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_init_pc_2894) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_infinite_header_q_2_0_a2_4.INIT = 16'h0001; + LUT4 com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_infinite_header_q_2_0_a2_4 ( + .I0(com_lnk_rfc_header[4]), + .I1(com_lnk_rfc_header[5]), + .I2(com_lnk_rfc_header[6]), + .I3(com_lnk_rfc_header[7]), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_infinite_header_q_2_0_a2_4_2911) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_infinite_data_q_2_0_a2_6.INIT = 16'h0001; + LUT4 com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_infinite_data_q_2_0_a2_6 ( + .I0(com_lnk_rfc_data[0]), + .I1(com_lnk_rfc_data[1]), + .I2(com_lnk_rfc_data[2]), + .I3(com_lnk_rfc_data[3]), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_infinite_data_q_2_0_a2_6_2915) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_infinite_data_q_2_0_a2_7.INIT = 16'h0001; + LUT4 com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_infinite_data_q_2_0_a2_7 ( + .I0(com_lnk_rfc_data[8]), + .I1(com_lnk_rfc_data[9]), + .I2(com_lnk_rfc_data[10]), + .I3(com_lnk_rfc_data[11]), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_infinite_data_q_2_0_a2_7_2914) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_infinite_data_q_2_0_a2_8.INIT = 16'h0001; + LUT4 com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_infinite_data_q_2_0_a2_8 ( + .I0(com_lnk_rfc_data[4]), + .I1(com_lnk_rfc_data[5]), + .I2(com_lnk_rfc_data[6]), + .I3(com_lnk_rfc_data[7]), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_infinite_data_q_2_0_a2_8_2913) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_nph_av_o_6_0.INIT = 8'h21; + LUT3 com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_nph_av_o_6_0 ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_NPH[6]), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_infinite_NPH_2896), + .I2(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_limit_NPH[6]), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_nph_av_o_6_0_2937) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_nph_av_o_6_1.INIT = 16'h8421; + LUT4 com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_nph_av_o_6_1 ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_NPH[4]), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_NPH[5]), + .I2(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_limit_NPH[4]), + .I3(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_limit_NPH[5]), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_nph_av_o_6_1_2936) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_nph_av_o_6_2.INIT = 16'h8421; + LUT4 com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_nph_av_o_6_2 ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_NPH[3]), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_NPH[7]), + .I2(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_limit_NPH[3]), + .I3(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_limit_NPH[7]), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_nph_av_o_6_2_2935) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_nph_av_o_6_3.INIT = 16'h8421; + LUT4_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_nph_av_o_6_3 ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_NPH[1]), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_NPH[2]), + .I2(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_limit_NPH[1]), + .I3(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_limit_NPH[2]), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_nph_av_o_6_3_2898) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_ph_av_o_6_0.INIT = 8'h21; + LUT3 com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_ph_av_o_6_0 ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_PH[6]), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_infinite_PH_2897), + .I2(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_limit_PH[6]), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_ph_av_o_6_0_2942) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_ph_av_o_6_1.INIT = 16'h8421; + LUT4 com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_ph_av_o_6_1 ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_PH[4]), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_PH[5]), + .I2(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_limit_PH[4]), + .I3(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_limit_PH[5]), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_ph_av_o_6_1_2941) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_ph_av_o_6_2.INIT = 16'h8421; + LUT4 com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_ph_av_o_6_2 ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_PH[3]), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_PH[7]), + .I2(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_limit_PH[3]), + .I3(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_limit_PH[7]), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_ph_av_o_6_2_2940) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_ph_av_o_6_3.INIT = 16'h8421; + LUT4_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_ph_av_o_6_3 ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_PH[1]), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_PH[2]), + .I2(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_limit_PH[1]), + .I3(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_limit_PH[2]), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_ph_av_o_6_3_2899) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_infinite_CPLH_0.INIT = 8'h21; + LUT3 com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_infinite_CPLH_0 ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_CPLH[6]), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_infinite_CPLH_2919), + .I2(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_limit_CPLH[6]), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_infinite_CPLH_0_2932) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_infinite_CPLH_1.INIT = 16'h8421; + LUT4 com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_infinite_CPLH_1 ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_CPLH[4]), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_CPLH[5]), + .I2(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_limit_CPLH[4]), + .I3(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_limit_CPLH[5]), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_infinite_CPLH_1_2931) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_infinite_CPLH_2.INIT = 16'h8421; + LUT4 com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_infinite_CPLH_2 ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_CPLH[3]), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_CPLH[7]), + .I2(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_limit_CPLH[3]), + .I3(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_limit_CPLH[7]), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_infinite_CPLH_2_2930) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_infinite_CPLH_3.INIT = 16'h8421; + LUT4_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_infinite_CPLH_3 ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_CPLH[1]), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_CPLH[2]), + .I2(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_limit_CPLH[1]), + .I3(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_limit_CPLH[2]), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_infinite_CPLH_3_2900) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_av_hdr_cred_7_iv_i_0_0_0.INIT = 16'h135F; + LUT4 com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_av_hdr_cred_7_iv_i_0_0_0 ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_cplh_av), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_suspend_cat[0]), + .I2(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_suspend_cat[1]), + .I3(com_tlm_u_tlm_tx_vc0_frm_seq_nph_av), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_av_hdr_cred_7_iv_i_0_0_0_2944) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_new_limit_header_ok_3_0_a2.INIT = 16'hD010; + LUT4 com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_new_limit_header_ok_3_0_a2 ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_fc_diff_header_q[7]), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_infinite_header_qq_3018), + .I2(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_new_limit_data_ok), + .I3(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_infinite_header_qq_3015), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_new_limit_header_ok_3_0_a2_2927) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_nph_av_o_6_4.INIT = 8'h90; + LUT3_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_nph_av_o_6_4 ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_NPH[0]), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_limit_NPH[0]), + .I2(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_nph_av_o_6_3_2898), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_nph_av_o_6_4_2934) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_ph_av_o_6_4.INIT = 8'h90; + LUT3_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_ph_av_o_6_4 ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_PH[0]), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_limit_PH[0]), + .I2(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_ph_av_o_6_3_2899), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_ph_av_o_6_4_2939) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_infinite_CPLH_4.INIT = 8'h90; + LUT3_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_infinite_CPLH_4 ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_CPLH[0]), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_limit_CPLH[0]), + .I2(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_infinite_CPLH_3_2900), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_infinite_CPLH_4_2929) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_av_data_cred_7_i_0_0_6_.INIT = 16'hFD64; + LUT4 com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_av_data_cred_7_i_0_0_6_ ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_suspend_cat[0]), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_suspend_cat[1]), + .I2(com_tlm_u_tlm_tx_vc0_frm_seq_npd_av[6]), + .I3(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_pd_av[6]), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_av_data_cred_7_i_0_0[6]) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_av_data_cred_7_i_0_0_3_.INIT = 16'hFD64; + LUT4 com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_av_data_cred_7_i_0_0_3_ ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_suspend_cat[0]), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_suspend_cat[1]), + .I2(com_tlm_u_tlm_tx_vc0_frm_seq_npd_av[3]), + .I3(com_tlm_u_tlm_tx_vc0_frm_seq_pd_av_3_), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_av_data_cred_7_i_0_0[3]) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_av_data_cred_7_i_0_0_1_.INIT = 16'hFD64; + LUT4 com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_av_data_cred_7_i_0_0_1_ ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_suspend_cat[0]), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_suspend_cat[1]), + .I2(com_tlm_u_tlm_tx_vc0_frm_seq_npd_av[1]), + .I3(com_tlm_u_tlm_tx_vc0_frm_seq_pd_av_1_), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_av_data_cred_7_i_0_0[1]) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_av_data_cred_7_i_0_0_0_.INIT = 16'hFD64; + LUT4 com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_av_data_cred_7_i_0_0_0_ ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_suspend_cat[0]), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_suspend_cat[1]), + .I2(com_tlm_u_tlm_tx_vc0_frm_seq_npd_av[0]), + .I3(com_tlm_u_tlm_tx_vc0_frm_seq_pd_av_0_), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_av_data_cred_7_i_0_0[0]) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_av_data_cred_7_i_0_0_4_.INIT = 16'hFD64; + LUT4 com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_av_data_cred_7_i_0_0_4_ ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_suspend_cat[0]), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_suspend_cat[1]), + .I2(com_tlm_u_tlm_tx_vc0_frm_seq_npd_av[4]), + .I3(com_tlm_u_tlm_tx_vc0_frm_seq_pd_av_4_), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_av_data_cred_7_i_0_0[4]) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_av_data_cred_7_i_0_0_7_.INIT = 16'hFD64; + LUT4 com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_av_data_cred_7_i_0_0_7_ ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_suspend_cat[0]), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_suspend_cat[1]), + .I2(com_tlm_u_tlm_tx_vc0_frm_seq_npd_av[7]), + .I3(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_pd_av[7]), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_av_data_cred_7_i_0_0[7]) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_av_data_cred_7_i_0_0_2_.INIT = 16'hFD64; + LUT4 com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_av_data_cred_7_i_0_0_2_ ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_suspend_cat[0]), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_suspend_cat[1]), + .I2(com_tlm_u_tlm_tx_vc0_frm_seq_npd_av[2]), + .I3(com_tlm_u_tlm_tx_vc0_frm_seq_pd_av_2_), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_av_data_cred_7_i_0_0[2]) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_av_data_cred_7_i_0_0_10_.INIT = 16'hFD64; + LUT4 com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_av_data_cred_7_i_0_0_10_ ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_suspend_cat[0]), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_suspend_cat[1]), + .I2(com_tlm_u_tlm_tx_vc0_frm_seq_npd_av[10]), + .I3(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_pd_av[10]), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_av_data_cred_7_i_0_0[10]) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_av_data_cred_7_i_0_0_5_.INIT = 16'hFD64; + LUT4 com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_av_data_cred_7_i_0_0_5_ ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_suspend_cat[0]), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_suspend_cat[1]), + .I2(com_tlm_u_tlm_tx_vc0_frm_seq_npd_av[5]), + .I3(com_tlm_u_tlm_tx_vc0_frm_seq_pd_av_5_), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_av_data_cred_7_i_0_0[5]) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_av_data_cred_7_i_0_0_9_.INIT = 16'hFD64; + LUT4 com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_av_data_cred_7_i_0_0_9_ ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_suspend_cat[0]), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_suspend_cat[1]), + .I2(com_tlm_u_tlm_tx_vc0_frm_seq_npd_av[9]), + .I3(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_pd_av[9]), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_av_data_cred_7_i_0_0[9]) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_av_data_cred_7_i_0_0_8_.INIT = 16'hFD64; + LUT4 com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_av_data_cred_7_i_0_0_8_ ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_suspend_cat[0]), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_suspend_cat[1]), + .I2(com_tlm_u_tlm_tx_vc0_frm_seq_npd_av[8]), + .I3(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_pd_av[8]), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_av_data_cred_7_i_0_0[8]) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_av_data_cred_7_i_0_0_11_.INIT = 16'hFD64; + LUT4 com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_av_data_cred_7_i_0_0_11_ ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_suspend_cat[0]), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_suspend_cat[1]), + .I2(com_tlm_u_tlm_tx_vc0_frm_seq_npd_av[11]), + .I3(com_tlm_u_tlm_tx_vc0_frm_seq_pd_av_11_), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_av_data_cred_7_i_0_0[11]) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_N_69425_i.INIT = 8'hEC; + LUT3 com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_N_69425_i ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_new_limit_header_ok_3_0_a2_2927), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_init_p_2903), + .I2(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_update_p_2902), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_N_69425_i_2901) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_N_69426_i.INIT = 8'hEC; + LUT3 com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_N_69426_i ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_new_limit_header_ok_3_0_a2_2927), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_init_np_2906), + .I2(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_update_np_2905), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_N_69426_i_2904) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_N_69427_i.INIT = 8'hEC; + LUT3 com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_N_69427_i ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_new_limit_header_ok_3_0_a2_2927), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_init_cpl_2909), + .I2(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_update_cpl_2908), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_N_69427_i_2907) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_N_57213_i.INIT = 4'h1; + LUT1_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_N_57213_i ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un8_suspend_cat_axbxc1_2945), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_N_57213_i_2910) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_infinite_header_q_2_0_a2.INIT = 16'h1000; + LUT4_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_infinite_header_q_2_0_a2 ( + .I0(com_lnk_rfc_header[2]), + .I1(com_lnk_rfc_header[3]), + .I2(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_infinite_header_q_2_0_a2_0_2912), + .I3(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_infinite_header_q_2_0_a2_4_2911), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_infinite_header_q_2) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_infinite_data_q_2_0_a2.INIT = 8'h80; + LUT3_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_infinite_data_q_2_0_a2 ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_infinite_data_q_2_0_a2_6_2915), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_infinite_data_q_2_0_a2_7_2914), + .I2(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_infinite_data_q_2_0_a2_8_2913), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_infinite_data_q_2) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_infinite_data_q_5_u_0.INIT = 8'hE2; + LUT3_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_infinite_data_q_5_u_0 ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_infinite_data_q_5_0_0_2916), + .I1(com_lnk_rfc_type[1]), + .I2(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_infinite_CPLD_3026), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_infinite_data_q_5) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_fc_diff_data_axb_11.INIT = 4'h9; + LUT2_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_fc_diff_data_axb_11 ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_prev_limit_data_q[11]), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_data_q[11]), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_fc_diff_data_axb_11_2917) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_fc_diff_header_axb_7.INIT = 4'h9; + LUT2_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_fc_diff_header_axb_7 ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_prev_limit_header_q[7]), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_header_q[7]), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_fc_diff_header_axb_7_2918) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_infinite_header_q_5_u_0.INIT = 8'hE2; + LUT3_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_infinite_header_q_5_u_0 ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_infinite_header_q_5_0_0_2920), + .I1(com_lnk_rfc_type[1]), + .I2(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_infinite_CPLH_2919), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_infinite_header_q_5) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_prev_limit_data_q_5_1_7_.INIT = 8'hE2; + LUT3_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_prev_limit_data_q_5_1_7_ ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_prev_limit_data_q_5_0_0[7]), + .I1(com_lnk_rfc_type[1]), + .I2(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_limit_CPLD[7]), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_prev_limit_data_q_5[7]) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_prev_limit_data_q_5_1_6_.INIT = 8'hE2; + LUT3_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_prev_limit_data_q_5_1_6_ ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_prev_limit_data_q_5_0_0[6]), + .I1(com_lnk_rfc_type[1]), + .I2(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_limit_CPLD[6]), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_prev_limit_data_q_5[6]) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_prev_limit_data_q_5_1_5_.INIT = 8'hE2; + LUT3_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_prev_limit_data_q_5_1_5_ ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_prev_limit_data_q_5_0_0[5]), + .I1(com_lnk_rfc_type[1]), + .I2(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_limit_CPLD[5]), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_prev_limit_data_q_5[5]) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_prev_limit_data_q_5_1_4_.INIT = 8'hE2; + LUT3_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_prev_limit_data_q_5_1_4_ ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_prev_limit_data_q_5_0_0[4]), + .I1(com_lnk_rfc_type[1]), + .I2(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_limit_CPLD[4]), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_prev_limit_data_q_5[4]) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_prev_limit_data_q_5_1_3_.INIT = 8'hE2; + LUT3_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_prev_limit_data_q_5_1_3_ ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_prev_limit_data_q_5_0_0[3]), + .I1(com_lnk_rfc_type[1]), + .I2(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_limit_CPLD[3]), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_prev_limit_data_q_5[3]) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_prev_limit_data_q_5_1_2_.INIT = 8'hE2; + LUT3_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_prev_limit_data_q_5_1_2_ ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_prev_limit_data_q_5_0_0[2]), + .I1(com_lnk_rfc_type[1]), + .I2(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_limit_CPLD[2]), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_prev_limit_data_q_5[2]) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_prev_limit_data_q_5_1_1_.INIT = 8'hE2; + LUT3_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_prev_limit_data_q_5_1_1_ ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_prev_limit_data_q_5_0_0[1]), + .I1(com_lnk_rfc_type[1]), + .I2(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_limit_CPLD[1]), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_prev_limit_data_q_5[1]) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_prev_limit_data_q_5_1_0_.INIT = 8'hE2; + LUT3_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_prev_limit_data_q_5_1_0_ ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_prev_limit_data_q_5_0_0[0]), + .I1(com_lnk_rfc_type[1]), + .I2(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_limit_CPLD[0]), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_prev_limit_data_q_5[0]) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_prev_limit_header_q_5_1_7_.INIT = 8'hE2; + LUT3_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_prev_limit_header_q_5_1_7_ ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_prev_limit_header_q_5_0_0[7]), + .I1(com_lnk_rfc_type[1]), + .I2(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_limit_CPLH[7]), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_prev_limit_header_q_5[7]) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_prev_limit_header_q_5_1_6_.INIT = 8'hE2; + LUT3_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_prev_limit_header_q_5_1_6_ ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_prev_limit_header_q_5_0_0[6]), + .I1(com_lnk_rfc_type[1]), + .I2(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_limit_CPLH[6]), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_prev_limit_header_q_5[6]) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_prev_limit_header_q_5_1_5_.INIT = 8'hE2; + LUT3_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_prev_limit_header_q_5_1_5_ ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_prev_limit_header_q_5_0_0[5]), + .I1(com_lnk_rfc_type[1]), + .I2(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_limit_CPLH[5]), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_prev_limit_header_q_5[5]) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_prev_limit_header_q_5_1_4_.INIT = 8'hE2; + LUT3_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_prev_limit_header_q_5_1_4_ ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_prev_limit_header_q_5_0_0[4]), + .I1(com_lnk_rfc_type[1]), + .I2(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_limit_CPLH[4]), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_prev_limit_header_q_5[4]) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_prev_limit_header_q_5_1_3_.INIT = 8'hE2; + LUT3_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_prev_limit_header_q_5_1_3_ ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_prev_limit_header_q_5_0_0[3]), + .I1(com_lnk_rfc_type[1]), + .I2(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_limit_CPLH[3]), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_prev_limit_header_q_5[3]) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_prev_limit_header_q_5_1_2_.INIT = 8'hE2; + LUT3_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_prev_limit_header_q_5_1_2_ ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_prev_limit_header_q_5_0_0[2]), + .I1(com_lnk_rfc_type[1]), + .I2(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_limit_CPLH[2]), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_prev_limit_header_q_5[2]) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_prev_limit_header_q_5_1_1_.INIT = 8'hE2; + LUT3_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_prev_limit_header_q_5_1_1_ ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_prev_limit_header_q_5_0_0[1]), + .I1(com_lnk_rfc_type[1]), + .I2(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_limit_CPLH[1]), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_prev_limit_header_q_5[1]) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_prev_limit_header_q_5_1_0_.INIT = 8'hE2; + LUT3_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_prev_limit_header_q_5_1_0_ ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_prev_limit_header_q_5_0_0[0]), + .I1(com_lnk_rfc_type[1]), + .I2(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_limit_CPLH[0]), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_prev_limit_header_q_5[0]) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_prev_limit_data_q_5_1_11_.INIT = 8'hE2; + LUT3_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_prev_limit_data_q_5_1_11_ ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_prev_limit_data_q_5_0_0[11]), + .I1(com_lnk_rfc_type[1]), + .I2(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_limit_CPLD[11]), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_prev_limit_data_q_5[11]) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_prev_limit_data_q_5_1_10_.INIT = 8'hE2; + LUT3_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_prev_limit_data_q_5_1_10_ ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_prev_limit_data_q_5_0_0[10]), + .I1(com_lnk_rfc_type[1]), + .I2(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_limit_CPLD[10]), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_prev_limit_data_q_5[10]) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_prev_limit_data_q_5_1_9_.INIT = 8'hE2; + LUT3_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_prev_limit_data_q_5_1_9_ ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_prev_limit_data_q_5_0_0[9]), + .I1(com_lnk_rfc_type[1]), + .I2(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_limit_CPLD[9]), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_prev_limit_data_q_5[9]) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_prev_limit_data_q_5_1_8_.INIT = 8'hE2; + LUT3_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_prev_limit_data_q_5_1_8_ ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_prev_limit_data_q_5_0_0[8]), + .I1(com_lnk_rfc_type[1]), + .I2(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_limit_CPLD[8]), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_prev_limit_data_q_5[8]) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_lat_d_i_2_.INIT = 4'h1; + LUT1_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_lat_d_i_2_ ( + .I0(com_lat_d[2]), + .LO(com_lat_d_i[2]) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_N_13857_i.INIT = 8'hFE; + LUT3_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_N_13857_i ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_consumed_cplh_2566), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_consumed_nph_2564), + .I2(com_tlm_u_tlm_tx_vc0_frm_seq_consumed_ph_2565), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_N_13857_i_2921) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_suspend_rdy_o_3.INIT = 8'h80; + LUT3_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_suspend_rdy_o_3 ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_credits_ok[0]), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_credits_ok[1]), + .I2(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_credits_ok[2]), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_suspend_rdy_o_3_2922) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_update_cpl_3_0_a2.INIT = 8'h40; + LUT3_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_update_cpl_3_0_a2 ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_cat_q[0]), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_cat_q[1]), + .I2(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_update_vld_q_2923), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_update_cpl_3) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_update_np_3_0_a2.INIT = 8'h20; + LUT3_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_update_np_3_0_a2 ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_cat_q[0]), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_cat_q[1]), + .I2(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_update_vld_q_2923), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_update_np_3) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_update_p_3_0_a2.INIT = 8'h10; + LUT3_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_update_p_3_0_a2 ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_cat_q[0]), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_cat_q[1]), + .I2(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_update_vld_q_2923), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_update_p_3) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_av_valid_o_4_0_a2.INIT = 16'h0001; + LUT4_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_av_valid_o_4_0_a2 ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_consumed_cplh_2566), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_consumed_nph_2564), + .I2(com_tlm_u_tlm_tx_vc0_frm_seq_consumed_ph_2565), + .I3(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_q_2924), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_av_valid_o_4) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_err_fc_o13_0_a2.INIT = 8'h54; + LUT3_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_err_fc_o13_0_a2 ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_new_limit_header_ok_3_0_a2_2927), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_init_vld_qq_2926), + .I2(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_update_vld_qq_2925), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_err_fc_o13) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_N_8620_i.INIT = 16'h7FFF; + LUT4_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_N_8620_i ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_infinite_CPLH_0_2932), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_infinite_CPLH_1_2931), + .I2(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_infinite_CPLH_2_2930), + .I3(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_infinite_CPLH_4_2929), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_N_8620_i_2928) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_N_8622_i.INIT = 16'h7FFF; + LUT4_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_N_8622_i ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_nph_av_o_6_0_2937), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_nph_av_o_6_1_2936), + .I2(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_nph_av_o_6_2_2935), + .I3(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_nph_av_o_6_4_2934), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_N_8622_i_2933) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_N_8621_i.INIT = 16'h7FFF; + LUT4_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_N_8621_i ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_ph_av_o_6_0_2942), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_ph_av_o_6_1_2941), + .I2(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_ph_av_o_6_2_2940), + .I3(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_ph_av_o_6_4_2939), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_N_8621_i_2938) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_av_data_cred_7_i_0_11_.INIT = 8'hD0; + LUT3_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_av_data_cred_7_i_0_11_ ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_N_50493), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_cpld_av_11_), + .I2(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_av_data_cred_7_i_0_0[11]), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_N_43791_i) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_av_data_cred_7_i_0_10_.INIT = 8'hD0; + LUT3_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_av_data_cred_7_i_0_10_ ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_N_50493), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_cpld_av[10]), + .I2(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_av_data_cred_7_i_0_0[10]), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_N_43789_i) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_av_data_cred_7_i_0_9_.INIT = 8'hD0; + LUT3_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_av_data_cred_7_i_0_9_ ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_N_50493), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_cpld_av[9]), + .I2(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_av_data_cred_7_i_0_0[9]), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_N_43787_i) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_av_data_cred_7_i_0_8_.INIT = 8'hD0; + LUT3_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_av_data_cred_7_i_0_8_ ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_N_50493), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_cpld_av[8]), + .I2(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_av_data_cred_7_i_0_0[8]), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_N_43785_i) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_av_data_cred_7_i_0_7_.INIT = 8'hD0; + LUT3_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_av_data_cred_7_i_0_7_ ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_N_50493), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_cpld_av[7]), + .I2(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_av_data_cred_7_i_0_0[7]), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_N_43783_i) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_av_data_cred_7_i_0_6_.INIT = 8'hD0; + LUT3_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_av_data_cred_7_i_0_6_ ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_N_50493), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_cpld_av[6]), + .I2(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_av_data_cred_7_i_0_0[6]), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_N_43781_i) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_av_data_cred_7_i_0_5_.INIT = 8'hD0; + LUT3_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_av_data_cred_7_i_0_5_ ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_N_50493), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_cpld_av_5_), + .I2(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_av_data_cred_7_i_0_0[5]), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_N_43779_i) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_av_data_cred_7_i_0_4_.INIT = 8'hD0; + LUT3_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_av_data_cred_7_i_0_4_ ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_N_50493), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_cpld_av_4_), + .I2(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_av_data_cred_7_i_0_0[4]), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_N_43777_i) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_av_data_cred_7_i_0_3_.INIT = 8'hD0; + LUT3_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_av_data_cred_7_i_0_3_ ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_N_50493), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_cpld_av_3_), + .I2(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_av_data_cred_7_i_0_0[3]), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_N_43775_i) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_av_data_cred_7_i_0_2_.INIT = 8'hD0; + LUT3_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_av_data_cred_7_i_0_2_ ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_N_50493), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_cpld_av_2_), + .I2(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_av_data_cred_7_i_0_0[2]), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_N_43773_i) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_av_data_cred_7_i_0_1_.INIT = 8'hD0; + LUT3_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_av_data_cred_7_i_0_1_ ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_N_50493), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_cpld_av_1_), + .I2(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_av_data_cred_7_i_0_0[1]), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_N_43771_i) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_av_data_cred_7_i_0_0_.INIT = 8'hD0; + LUT3_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_av_data_cred_7_i_0_0_ ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_N_50493), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_cpld_av_0_), + .I2(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_av_data_cred_7_i_0_0[0]), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_N_43769_i) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_N_68153_i.INIT = 8'h73; + LUT3_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_N_68153_i ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un8_suspend_cat_axbxc1_2945), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_av_hdr_cred_7_iv_i_0_0_0_2944), + .I2(com_tlm_u_tlm_tx_vc0_frm_seq_ph_av), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_N_68153_i_2943) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_credits_ok_3_0_.INIT = 4'h2; + LUT2_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_credits_ok_3_0_ ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_av_hdr_cred_2947), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un7_credits_ok_cry_11_2946), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_credits_ok_3[0]) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_CPLD_1_axb_11.INIT = 4'h2; + LUT1_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_CPLD_1_axb_11 ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_CPLD[11]), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_CPLD_1_axb_11_2948) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_CPLD_1_axb_10.INIT = 4'h2; + LUT1_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_CPLD_1_axb_10 ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_CPLD[10]), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_CPLD_1_axb_10_2949) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_CPLD_1_axb_9.INIT = 4'h2; + LUT1_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_CPLD_1_axb_9 ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_CPLD[9]), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_CPLD_1_axb_9_2950) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_CPLD_1_axb_8.INIT = 4'h2; + LUT1_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_CPLD_1_axb_8 ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_CPLD[8]), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_CPLD_1_axb_8_2951) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_CPLD_1_axb_7.INIT = 4'h2; + LUT1_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_CPLD_1_axb_7 ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_CPLD[7]), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_CPLD_1_axb_7_2952) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_CPLD_1_axb_6.INIT = 4'h2; + LUT1_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_CPLD_1_axb_6 ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_CPLD[6]), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_CPLD_1_axb_6_2953) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_CPLD_1_axb_5.INIT = 8'h78; + LUT3_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_CPLD_1_axb_5 ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_consumed_cplh_2566), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_consumed_credits[5]), + .I2(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_CPLD[5]), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_CPLD_1_axb_5_2954) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_CPLD_1_axb_4.INIT = 8'h78; + LUT3_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_CPLD_1_axb_4 ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_consumed_cplh_2566), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_consumed_credits[4]), + .I2(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_CPLD[4]), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_CPLD_1_axb_4_2955) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_CPLD_1_axb_3.INIT = 8'h78; + LUT3_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_CPLD_1_axb_3 ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_consumed_cplh_2566), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_consumed_credits[3]), + .I2(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_CPLD[3]), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_CPLD_1_axb_3_2956) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_CPLD_1_axb_2.INIT = 8'h78; + LUT3_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_CPLD_1_axb_2 ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_consumed_cplh_2566), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_consumed_credits[2]), + .I2(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_CPLD[2]), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_CPLD_1_axb_2_2957) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_CPLD_1_axb_1.INIT = 8'h78; + LUT3_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_CPLD_1_axb_1 ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_consumed_cplh_2566), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_consumed_credits[1]), + .I2(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_CPLD[1]), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_CPLD_1_axb_1_2958) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_NPD_1_axb_11.INIT = 4'h2; + LUT1_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_NPD_1_axb_11 ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_NPD[11]), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_NPD_1_axb_11_2959) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_NPD_1_axb_10.INIT = 4'h2; + LUT1_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_NPD_1_axb_10 ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_NPD[10]), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_NPD_1_axb_10_2960) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_NPD_1_axb_9.INIT = 4'h2; + LUT1_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_NPD_1_axb_9 ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_NPD[9]), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_NPD_1_axb_9_2961) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_NPD_1_axb_8.INIT = 4'h2; + LUT1_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_NPD_1_axb_8 ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_NPD[8]), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_NPD_1_axb_8_2962) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_NPD_1_axb_7.INIT = 4'h2; + LUT1_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_NPD_1_axb_7 ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_NPD[7]), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_NPD_1_axb_7_2963) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_NPD_1_axb_6.INIT = 4'h2; + LUT1_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_NPD_1_axb_6 ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_NPD[6]), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_NPD_1_axb_6_2964) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_NPD_1_axb_5.INIT = 8'h78; + LUT3_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_NPD_1_axb_5 ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_consumed_credits[5]), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_consumed_nph_2564), + .I2(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_NPD[5]), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_NPD_1_axb_5_2965) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_NPD_1_axb_4.INIT = 8'h78; + LUT3_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_NPD_1_axb_4 ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_consumed_credits[4]), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_consumed_nph_2564), + .I2(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_NPD[4]), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_NPD_1_axb_4_2966) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_NPD_1_axb_3.INIT = 8'h78; + LUT3_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_NPD_1_axb_3 ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_consumed_credits[3]), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_consumed_nph_2564), + .I2(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_NPD[3]), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_NPD_1_axb_3_2967) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_NPD_1_axb_2.INIT = 8'h78; + LUT3_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_NPD_1_axb_2 ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_consumed_credits[2]), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_consumed_nph_2564), + .I2(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_NPD[2]), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_NPD_1_axb_2_2968) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_NPD_1_axb_1.INIT = 8'h78; + LUT3_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_NPD_1_axb_1 ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_consumed_credits[1]), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_consumed_nph_2564), + .I2(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_NPD[1]), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_NPD_1_axb_1_2969) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_PD_1_axb_11.INIT = 4'h2; + LUT1_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_PD_1_axb_11 ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_PD[11]), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_PD_1_axb_11_2970) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_PD_1_axb_10.INIT = 4'h2; + LUT1_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_PD_1_axb_10 ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_PD[10]), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_PD_1_axb_10_2971) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_PD_1_axb_9.INIT = 4'h2; + LUT1_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_PD_1_axb_9 ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_PD[9]), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_PD_1_axb_9_2972) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_PD_1_axb_8.INIT = 4'h2; + LUT1_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_PD_1_axb_8 ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_PD[8]), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_PD_1_axb_8_2973) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_PD_1_axb_7.INIT = 4'h2; + LUT1_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_PD_1_axb_7 ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_PD[7]), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_PD_1_axb_7_2974) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_PD_1_axb_6.INIT = 4'h2; + LUT1_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_PD_1_axb_6 ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_PD[6]), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_PD_1_axb_6_2975) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_PD_1_axb_5.INIT = 8'h78; + LUT3_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_PD_1_axb_5 ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_consumed_credits[5]), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_consumed_ph_2565), + .I2(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_PD[5]), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_PD_1_axb_5_2976) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_PD_1_axb_4.INIT = 8'h78; + LUT3_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_PD_1_axb_4 ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_consumed_credits[4]), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_consumed_ph_2565), + .I2(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_PD[4]), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_PD_1_axb_4_2977) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_PD_1_axb_3.INIT = 8'h78; + LUT3_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_PD_1_axb_3 ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_consumed_credits[3]), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_consumed_ph_2565), + .I2(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_PD[3]), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_PD_1_axb_3_2978) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_PD_1_axb_2.INIT = 8'h78; + LUT3_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_PD_1_axb_2 ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_consumed_credits[2]), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_consumed_ph_2565), + .I2(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_PD[2]), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_PD_1_axb_2_2979) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_PD_1_axb_1.INIT = 8'h78; + LUT3_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_PD_1_axb_1 ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_consumed_credits[1]), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_consumed_ph_2565), + .I2(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_PD[1]), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_PD_1_axb_1_2980) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_cpld_av_o_6_axb_10.INIT = 8'h7B; + LUT3_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_cpld_av_o_6_axb_10 ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_CPLD_i[10]), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_infinite_CPLD_i_3022), + .I2(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_limit_CPLD[10]), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_cpld_av_o_6_axb_10_2981) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_cpld_av_o_6_axb_9.INIT = 8'h7B; + LUT3_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_cpld_av_o_6_axb_9 ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_CPLD_i[9]), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_infinite_CPLD_i_3022), + .I2(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_limit_CPLD[9]), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_cpld_av_o_6_axb_9_2982) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_cpld_av_o_6_axb_8.INIT = 8'h7B; + LUT3_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_cpld_av_o_6_axb_8 ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_CPLD_i[8]), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_infinite_CPLD_i_3022), + .I2(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_limit_CPLD[8]), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_cpld_av_o_6_axb_8_2983) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_cpld_av_o_6_axb_7.INIT = 8'h7B; + LUT3_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_cpld_av_o_6_axb_7 ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_CPLD_i[7]), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_infinite_CPLD_i_3022), + .I2(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_limit_CPLD[7]), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_cpld_av_o_6_axb_7_2984) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_cpld_av_o_6_axb_6.INIT = 8'h7B; + LUT3_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_cpld_av_o_6_axb_6 ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_CPLD_i[6]), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_infinite_CPLD_i_3022), + .I2(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_limit_CPLD[6]), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_cpld_av_o_6_axb_6_2985) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_cpld_av_o_6_axb_5.INIT = 8'h7B; + LUT3_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_cpld_av_o_6_axb_5 ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_CPLD_i[5]), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_infinite_CPLD_i_3022), + .I2(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_limit_CPLD[5]), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_cpld_av_o_6_axb_5_2986) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_cpld_av_o_6_axb_4.INIT = 8'h7B; + LUT3_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_cpld_av_o_6_axb_4 ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_CPLD_i[4]), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_infinite_CPLD_i_3022), + .I2(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_limit_CPLD[4]), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_cpld_av_o_6_axb_4_2987) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_cpld_av_o_6_axb_3.INIT = 8'h7B; + LUT3_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_cpld_av_o_6_axb_3 ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_CPLD_i[3]), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_infinite_CPLD_i_3022), + .I2(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_limit_CPLD[3]), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_cpld_av_o_6_axb_3_2988) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_cpld_av_o_6_axb_2.INIT = 8'h7B; + LUT3_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_cpld_av_o_6_axb_2 ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_CPLD_i[2]), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_infinite_CPLD_i_3022), + .I2(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_limit_CPLD[2]), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_cpld_av_o_6_axb_2_2989) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_cpld_av_o_6_axb_1.INIT = 8'h7B; + LUT3_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_cpld_av_o_6_axb_1 ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_CPLD_i[1]), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_infinite_CPLD_i_3022), + .I2(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_limit_CPLD[1]), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_cpld_av_o_6_axb_1_2990) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_cpld_av_o_6_axb_0.INIT = 8'h7B; + LUT3_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_cpld_av_o_6_axb_0 ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_CPLD_i[0]), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_infinite_CPLD_i_3022), + .I2(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_limit_CPLD[0]), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_cpld_av_o_6_axb_0_2991) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_npd_av_o_6_axb_10.INIT = 8'h7B; + LUT3_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_npd_av_o_6_axb_10 ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_NPD_i[10]), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_infinite_NPD_i_3023), + .I2(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_limit_NPD[10]), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_npd_av_o_6_axb_10_2992) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_npd_av_o_6_axb_9.INIT = 8'h7B; + LUT3_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_npd_av_o_6_axb_9 ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_NPD_i[9]), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_infinite_NPD_i_3023), + .I2(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_limit_NPD[9]), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_npd_av_o_6_axb_9_2993) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_npd_av_o_6_axb_8.INIT = 8'h7B; + LUT3_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_npd_av_o_6_axb_8 ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_NPD_i[8]), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_infinite_NPD_i_3023), + .I2(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_limit_NPD[8]), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_npd_av_o_6_axb_8_2994) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_npd_av_o_6_axb_7.INIT = 8'h7B; + LUT3_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_npd_av_o_6_axb_7 ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_NPD_i[7]), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_infinite_NPD_i_3023), + .I2(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_limit_NPD[7]), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_npd_av_o_6_axb_7_2995) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_npd_av_o_6_axb_6.INIT = 8'h7B; + LUT3_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_npd_av_o_6_axb_6 ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_NPD_i[6]), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_infinite_NPD_i_3023), + .I2(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_limit_NPD[6]), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_npd_av_o_6_axb_6_2996) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_npd_av_o_6_axb_5.INIT = 8'h7B; + LUT3_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_npd_av_o_6_axb_5 ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_NPD_i[5]), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_infinite_NPD_i_3023), + .I2(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_limit_NPD[5]), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_npd_av_o_6_axb_5_2997) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_npd_av_o_6_axb_4.INIT = 8'h7B; + LUT3_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_npd_av_o_6_axb_4 ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_NPD_i[4]), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_infinite_NPD_i_3023), + .I2(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_limit_NPD[4]), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_npd_av_o_6_axb_4_2998) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_npd_av_o_6_axb_3.INIT = 8'h7B; + LUT3_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_npd_av_o_6_axb_3 ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_NPD_i[3]), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_infinite_NPD_i_3023), + .I2(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_limit_NPD[3]), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_npd_av_o_6_axb_3_2999) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_npd_av_o_6_axb_2.INIT = 8'h7B; + LUT3_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_npd_av_o_6_axb_2 ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_NPD_i[2]), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_infinite_NPD_i_3023), + .I2(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_limit_NPD[2]), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_npd_av_o_6_axb_2_3000) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_npd_av_o_6_axb_1.INIT = 8'h7B; + LUT3_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_npd_av_o_6_axb_1 ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_NPD_i[1]), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_infinite_NPD_i_3023), + .I2(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_limit_NPD[1]), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_npd_av_o_6_axb_1_3001) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_npd_av_o_6_axb_0.INIT = 8'h7B; + LUT3_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_npd_av_o_6_axb_0 ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_NPD_i[0]), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_infinite_NPD_i_3023), + .I2(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_limit_NPD[0]), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_npd_av_o_6_axb_0_3002) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_pd_av_o_6_axb_10.INIT = 8'h7B; + LUT3_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_pd_av_o_6_axb_10 ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_PD_i[10]), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_infinite_PD_i_3024), + .I2(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_limit_PD[10]), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_pd_av_o_6_axb_10_3003) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_pd_av_o_6_axb_9.INIT = 8'h7B; + LUT3_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_pd_av_o_6_axb_9 ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_PD_i[9]), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_infinite_PD_i_3024), + .I2(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_limit_PD[9]), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_pd_av_o_6_axb_9_3004) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_pd_av_o_6_axb_8.INIT = 8'h7B; + LUT3_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_pd_av_o_6_axb_8 ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_PD_i[8]), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_infinite_PD_i_3024), + .I2(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_limit_PD[8]), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_pd_av_o_6_axb_8_3005) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_pd_av_o_6_axb_7.INIT = 8'h7B; + LUT3_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_pd_av_o_6_axb_7 ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_PD_i[7]), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_infinite_PD_i_3024), + .I2(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_limit_PD[7]), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_pd_av_o_6_axb_7_3006) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_pd_av_o_6_axb_6.INIT = 8'h7B; + LUT3_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_pd_av_o_6_axb_6 ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_PD_i[6]), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_infinite_PD_i_3024), + .I2(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_limit_PD[6]), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_pd_av_o_6_axb_6_3007) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_pd_av_o_6_axb_5.INIT = 8'h7B; + LUT3_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_pd_av_o_6_axb_5 ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_PD_i[5]), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_infinite_PD_i_3024), + .I2(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_limit_PD[5]), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_pd_av_o_6_axb_5_3008) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_pd_av_o_6_axb_4.INIT = 8'h7B; + LUT3_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_pd_av_o_6_axb_4 ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_PD_i[4]), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_infinite_PD_i_3024), + .I2(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_limit_PD[4]), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_pd_av_o_6_axb_4_3009) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_pd_av_o_6_axb_3.INIT = 8'h7B; + LUT3_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_pd_av_o_6_axb_3 ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_PD_i[3]), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_infinite_PD_i_3024), + .I2(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_limit_PD[3]), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_pd_av_o_6_axb_3_3010) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_pd_av_o_6_axb_2.INIT = 8'h7B; + LUT3_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_pd_av_o_6_axb_2 ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_PD_i[2]), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_infinite_PD_i_3024), + .I2(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_limit_PD[2]), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_pd_av_o_6_axb_2_3011) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_pd_av_o_6_axb_1.INIT = 8'h7B; + LUT3_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_pd_av_o_6_axb_1 ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_PD_i[1]), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_infinite_PD_i_3024), + .I2(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_limit_PD[1]), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_pd_av_o_6_axb_1_3012) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_pd_av_o_6_axb_0.INIT = 8'h7B; + LUT3_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_pd_av_o_6_axb_0 ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_PD_i[0]), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_infinite_PD_i_3024), + .I2(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_limit_PD[0]), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_pd_av_o_6_axb_0_3013) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_min_data_cred_7_i_0_5_.INIT = 4'h1; + LUT2_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_min_data_cred_7_i_0_5_ ( + .I0(com_N_3419_i), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_suspend_cat[0]), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_N_43656_i) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_min_data_cred_7_0_a2_0_a2_4_.INIT = 4'h2; + LUT2_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_min_data_cred_7_0_a2_0_a2_4_ ( + .I0(com_lat_d[2]), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_suspend_cat[0]), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_min_data_cred_7[4]) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_min_data_cred_7_0_a2_0_a2_3_.INIT = 4'h2; + LUT2_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_min_data_cred_7_0_a2_0_a2_3_ ( + .I0(com_N_3355_i), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_suspend_cat[0]), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_min_data_cred_7[3]) + ); + FD com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_infinite_header_q ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_infinite_header_q_2), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_infinite_header_q_3014) + ); + FD com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_infinite_data_q ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_infinite_data_q_2), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_infinite_data_q_3016) + ); + FD com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_infinite_data_q ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_infinite_data_q_5), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_infinite_data_q_3019) + ); + FD com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_infinite_header_qq ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_infinite_header_q_3014), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_infinite_header_qq_3015) + ); + FD com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_infinite_data_qq ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_infinite_data_q_3016), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_infinite_data_qq_3017) + ); + FD com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_fc_diff_data_q_11_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_fc_diff_data[11]), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_fc_diff_data_q[11]) + ); + FD com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_fc_diff_header_q_7_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_fc_diff_header[7]), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_fc_diff_header_q[7]) + ); + FD com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_infinite_header_qq ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_infinite_header_q_3021), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_infinite_header_qq_3018) + ); + FD com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_infinite_data_qq ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_infinite_data_q_3019), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_infinite_data_qq_3020) + ); + FD com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_infinite_header_q ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_infinite_header_q_5), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_infinite_header_q_3021) + ); + FD com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_prev_limit_data_q_7_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_prev_limit_data_q_5[7]), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_prev_limit_data_q[7]) + ); + FD com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_prev_limit_data_q_6_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_prev_limit_data_q_5[6]), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_prev_limit_data_q[6]) + ); + FD com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_prev_limit_data_q_5_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_prev_limit_data_q_5[5]), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_prev_limit_data_q[5]) + ); + FD com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_prev_limit_data_q_4_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_prev_limit_data_q_5[4]), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_prev_limit_data_q[4]) + ); + FD com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_prev_limit_data_q_3_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_prev_limit_data_q_5[3]), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_prev_limit_data_q[3]) + ); + FD com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_prev_limit_data_q_2_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_prev_limit_data_q_5[2]), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_prev_limit_data_q[2]) + ); + FD com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_prev_limit_data_q_1_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_prev_limit_data_q_5[1]), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_prev_limit_data_q[1]) + ); + FD com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_prev_limit_data_q_0_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_prev_limit_data_q_5[0]), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_prev_limit_data_q[0]) + ); + FD com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_data_q_0_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_lnk_rfc_data[0]), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_data_q[0]) + ); + FD com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_cat_q_1_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_lnk_rfc_type[1]), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_cat_q[1]) + ); + FD com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_cat_q_0_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_lnk_rfc_type[0]), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_cat_q[0]) + ); + FD com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_prev_limit_header_q_7_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_prev_limit_header_q_5[7]), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_prev_limit_header_q[7]) + ); + FD com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_prev_limit_header_q_6_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_prev_limit_header_q_5[6]), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_prev_limit_header_q[6]) + ); + FD com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_prev_limit_header_q_5_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_prev_limit_header_q_5[5]), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_prev_limit_header_q[5]) + ); + FD com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_prev_limit_header_q_4_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_prev_limit_header_q_5[4]), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_prev_limit_header_q[4]) + ); + FD com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_prev_limit_header_q_3_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_prev_limit_header_q_5[3]), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_prev_limit_header_q[3]) + ); + FD com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_prev_limit_header_q_2_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_prev_limit_header_q_5[2]), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_prev_limit_header_q[2]) + ); + FD com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_prev_limit_header_q_1_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_prev_limit_header_q_5[1]), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_prev_limit_header_q[1]) + ); + FD com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_prev_limit_header_q_0_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_prev_limit_header_q_5[0]), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_prev_limit_header_q[0]) + ); + FD com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_prev_limit_data_q_11_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_prev_limit_data_q_5[11]), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_prev_limit_data_q[11]) + ); + FD com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_prev_limit_data_q_10_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_prev_limit_data_q_5[10]), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_prev_limit_data_q[10]) + ); + FD com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_prev_limit_data_q_9_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_prev_limit_data_q_5[9]), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_prev_limit_data_q[9]) + ); + FD com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_prev_limit_data_q_8_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_prev_limit_data_q_5[8]), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_prev_limit_data_q[8]) + ); + FD com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_header_q_3_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_lnk_rfc_header[3]), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_header_q[3]) + ); + FD com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_header_q_2_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_lnk_rfc_header[2]), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_header_q[2]) + ); + FD com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_header_q_1_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_lnk_rfc_header[1]), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_header_q[1]) + ); + FD com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_header_q_0_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_lnk_rfc_header[0]), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_header_q[0]) + ); + FD com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_data_q_11_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_lnk_rfc_data[11]), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_data_q[11]) + ); + FD com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_data_q_10_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_lnk_rfc_data[10]), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_data_q[10]) + ); + FD com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_data_q_9_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_lnk_rfc_data[9]), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_data_q[9]) + ); + FD com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_data_q_8_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_lnk_rfc_data[8]), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_data_q[8]) + ); + FD com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_data_q_7_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_lnk_rfc_data[7]), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_data_q[7]) + ); + FD com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_data_q_6_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_lnk_rfc_data[6]), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_data_q[6]) + ); + FD com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_data_q_5_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_lnk_rfc_data[5]), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_data_q[5]) + ); + FD com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_data_q_4_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_lnk_rfc_data[4]), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_data_q[4]) + ); + FD com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_data_q_3_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_lnk_rfc_data[3]), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_data_q[3]) + ); + FD com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_data_q_2_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_lnk_rfc_data[2]), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_data_q[2]) + ); + FD com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_data_q_1_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_lnk_rfc_data[1]), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_data_q[1]) + ); + FD com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_data_qq_10_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_data_q[10]), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_data_qq[10]) + ); + FD com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_data_qq_9_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_data_q[9]), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_data_qq[9]) + ); + FD com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_data_qq_8_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_data_q[8]), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_data_qq[8]) + ); + FD com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_data_qq_7_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_data_q[7]), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_data_qq[7]) + ); + FD com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_data_qq_6_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_data_q[6]), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_data_qq[6]) + ); + FD com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_data_qq_5_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_data_q[5]), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_data_qq[5]) + ); + FD com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_data_qq_4_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_data_q[4]), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_data_qq[4]) + ); + FD com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_data_qq_3_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_data_q[3]), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_data_qq[3]) + ); + FD com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_data_qq_2_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_data_q[2]), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_data_qq[2]) + ); + FD com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_data_qq_1_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_data_q[1]), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_data_qq[1]) + ); + FD com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_data_qq_0_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_data_q[0]), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_data_qq[0]) + ); + FD com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_header_q_7_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_lnk_rfc_header[7]), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_header_q[7]) + ); + FD com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_header_q_6_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_lnk_rfc_header[6]), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_header_q[6]) + ); + FD com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_header_q_5_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_lnk_rfc_header[5]), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_header_q[5]) + ); + FD com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_header_q_4_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_lnk_rfc_header[4]), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_header_q[4]) + ); + FD com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_header_qq_7_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_header_q[7]), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_header_qq[7]) + ); + FD com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_header_qq_6_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_header_q[6]), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_header_qq[6]) + ); + FD com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_header_qq_5_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_header_q[5]), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_header_qq[5]) + ); + FD com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_header_qq_4_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_header_q[4]), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_header_qq[4]) + ); + FD com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_header_qq_3_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_header_q[3]), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_header_qq[3]) + ); + FD com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_header_qq_2_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_header_q[2]), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_header_qq[2]) + ); + FD com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_header_qq_1_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_header_q[1]), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_header_qq[1]) + ); + FD com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_header_qq_0_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_header_q[0]), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_header_qq[0]) + ); + FD com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_data_qq_11_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_data_q[11]), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_data_qq[11]) + ); + INV com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_infinite_CPLD_i ( + .I(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_infinite_CPLD_3026), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_infinite_CPLD_i_3022) + ); + INV com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_CPLD_i_0_ ( + .I(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_CPLD[0]), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_CPLD_i[0]) + ); + INV com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_CPLD_i_1_ ( + .I(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_CPLD[1]), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_CPLD_i[1]) + ); + INV com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_CPLD_i_2_ ( + .I(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_CPLD[2]), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_CPLD_i[2]) + ); + INV com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_CPLD_i_3_ ( + .I(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_CPLD[3]), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_CPLD_i[3]) + ); + INV com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_CPLD_i_4_ ( + .I(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_CPLD[4]), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_CPLD_i[4]) + ); + INV com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_CPLD_i_5_ ( + .I(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_CPLD[5]), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_CPLD_i[5]) + ); + INV com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_CPLD_i_6_ ( + .I(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_CPLD[6]), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_CPLD_i[6]) + ); + INV com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_CPLD_i_7_ ( + .I(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_CPLD[7]), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_CPLD_i[7]) + ); + INV com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_CPLD_i_8_ ( + .I(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_CPLD[8]), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_CPLD_i[8]) + ); + INV com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_CPLD_i_9_ ( + .I(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_CPLD[9]), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_CPLD_i[9]) + ); + INV com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_CPLD_i_10_ ( + .I(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_CPLD[10]), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_CPLD_i[10]) + ); + INV com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_infinite_NPD_i ( + .I(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_infinite_NPD_3028), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_infinite_NPD_i_3023) + ); + INV com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_NPD_i_0_ ( + .I(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_NPD[0]), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_NPD_i[0]) + ); + INV com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_NPD_i_1_ ( + .I(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_NPD[1]), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_NPD_i[1]) + ); + INV com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_NPD_i_2_ ( + .I(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_NPD[2]), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_NPD_i[2]) + ); + INV com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_NPD_i_3_ ( + .I(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_NPD[3]), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_NPD_i[3]) + ); + INV com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_NPD_i_4_ ( + .I(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_NPD[4]), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_NPD_i[4]) + ); + INV com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_NPD_i_5_ ( + .I(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_NPD[5]), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_NPD_i[5]) + ); + INV com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_NPD_i_6_ ( + .I(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_NPD[6]), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_NPD_i[6]) + ); + INV com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_NPD_i_7_ ( + .I(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_NPD[7]), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_NPD_i[7]) + ); + INV com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_NPD_i_8_ ( + .I(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_NPD[8]), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_NPD_i[8]) + ); + INV com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_NPD_i_9_ ( + .I(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_NPD[9]), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_NPD_i[9]) + ); + INV com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_NPD_i_10_ ( + .I(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_NPD[10]), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_NPD_i[10]) + ); + INV com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_infinite_PD_i ( + .I(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_infinite_PD_3030), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_infinite_PD_i_3024) + ); + INV com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_PD_i_0_ ( + .I(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_PD[0]), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_PD_i[0]) + ); + INV com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_PD_i_1_ ( + .I(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_PD[1]), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_PD_i[1]) + ); + INV com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_PD_i_2_ ( + .I(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_PD[2]), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_PD_i[2]) + ); + INV com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_PD_i_3_ ( + .I(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_PD[3]), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_PD_i[3]) + ); + INV com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_PD_i_4_ ( + .I(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_PD[4]), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_PD_i[4]) + ); + INV com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_PD_i_5_ ( + .I(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_PD[5]), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_PD_i[5]) + ); + INV com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_PD_i_6_ ( + .I(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_PD[6]), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_PD_i[6]) + ); + INV com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_PD_i_7_ ( + .I(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_PD[7]), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_PD_i[7]) + ); + INV com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_PD_i_8_ ( + .I(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_PD[8]), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_PD_i[8]) + ); + INV com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_PD_i_9_ ( + .I(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_PD[9]), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_PD_i[9]) + ); + INV com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_PD_i_10_ ( + .I(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_PD[10]), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_PD_i[10]) + ); + INV com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_N_3419_i_i ( + .I(com_N_3419_i), + .O(com_N_3419_i_i) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_PH_qxu_0_0_.INIT = 4'h2; + LUT1_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_PH_qxu_0_0_ ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_PH[0]), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_PH_qxu[0]) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_NPH_qxu_0_0_.INIT = 4'h2; + LUT1_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_NPH_qxu_0_0_ ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_NPH[0]), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_NPH_qxu[0]) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_CPLH_qxu_0_0_.INIT = 4'h2; + LUT1_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_CPLH_qxu_0_0_ ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_CPLH[0]), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_CPLH_qxu[0]) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_CPLH_qxu_0_7_.INIT = 4'h2; + LUT1_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_CPLH_qxu_0_7_ ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_CPLH[7]), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_CPLH_qxu[7]) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_CPLH_qxu_0_6_.INIT = 4'h2; + LUT1_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_CPLH_qxu_0_6_ ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_CPLH[6]), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_CPLH_qxu[6]) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_CPLH_qxu_0_5_.INIT = 4'h2; + LUT1_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_CPLH_qxu_0_5_ ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_CPLH[5]), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_CPLH_qxu[5]) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_CPLH_qxu_0_4_.INIT = 4'h2; + LUT1_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_CPLH_qxu_0_4_ ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_CPLH[4]), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_CPLH_qxu[4]) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_CPLH_qxu_0_3_.INIT = 4'h2; + LUT1_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_CPLH_qxu_0_3_ ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_CPLH[3]), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_CPLH_qxu[3]) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_CPLH_qxu_0_2_.INIT = 4'h2; + LUT1_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_CPLH_qxu_0_2_ ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_CPLH[2]), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_CPLH_qxu[2]) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_CPLH_qxu_0_1_.INIT = 4'h2; + LUT1_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_CPLH_qxu_0_1_ ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_CPLH[1]), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_CPLH_qxu[1]) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_CPLH_s_0_.INIT = 4'h1; + LUT1_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_CPLH_s_0_ ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_CPLH_qxu[0]), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_CPLH_s[0]) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_NPH_qxu_0_7_.INIT = 4'h2; + LUT1_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_NPH_qxu_0_7_ ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_NPH[7]), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_NPH_qxu[7]) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_NPH_qxu_0_6_.INIT = 4'h2; + LUT1_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_NPH_qxu_0_6_ ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_NPH[6]), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_NPH_qxu[6]) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_NPH_qxu_0_5_.INIT = 4'h2; + LUT1_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_NPH_qxu_0_5_ ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_NPH[5]), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_NPH_qxu[5]) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_NPH_qxu_0_4_.INIT = 4'h2; + LUT1_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_NPH_qxu_0_4_ ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_NPH[4]), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_NPH_qxu[4]) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_NPH_qxu_0_3_.INIT = 4'h2; + LUT1_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_NPH_qxu_0_3_ ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_NPH[3]), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_NPH_qxu[3]) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_NPH_qxu_0_2_.INIT = 4'h2; + LUT1_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_NPH_qxu_0_2_ ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_NPH[2]), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_NPH_qxu[2]) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_NPH_qxu_0_1_.INIT = 4'h2; + LUT1_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_NPH_qxu_0_1_ ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_NPH[1]), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_NPH_qxu[1]) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_NPH_s_0_.INIT = 4'h1; + LUT1_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_NPH_s_0_ ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_NPH_qxu[0]), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_NPH_s[0]) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_PH_qxu_0_7_.INIT = 4'h2; + LUT1_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_PH_qxu_0_7_ ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_PH[7]), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_PH_qxu[7]) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_PH_qxu_0_6_.INIT = 4'h2; + LUT1_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_PH_qxu_0_6_ ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_PH[6]), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_PH_qxu[6]) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_PH_qxu_0_5_.INIT = 4'h2; + LUT1_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_PH_qxu_0_5_ ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_PH[5]), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_PH_qxu[5]) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_PH_qxu_0_4_.INIT = 4'h2; + LUT1_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_PH_qxu_0_4_ ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_PH[4]), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_PH_qxu[4]) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_PH_qxu_0_3_.INIT = 4'h2; + LUT1_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_PH_qxu_0_3_ ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_PH[3]), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_PH_qxu[3]) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_PH_qxu_0_2_.INIT = 4'h2; + LUT1_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_PH_qxu_0_2_ ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_PH[2]), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_PH_qxu[2]) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_PH_qxu_0_1_.INIT = 4'h2; + LUT1_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_PH_qxu_0_1_ ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_PH[1]), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_PH_qxu[1]) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_PH_s_0_.INIT = 4'h1; + LUT1_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_PH_s_0_ ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_PH_qxu[0]), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_PH_s[0]) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_cpld_av_o_6_axb_11.INIT = 8'h09; + LUT3_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_cpld_av_o_6_axb_11 ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_limit_CPLD[11]), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_CPLD[11]), + .I2(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_infinite_CPLD_3026), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_cpld_av_o_6_axb_11_3025) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_npd_av_o_6_axb_11.INIT = 8'h09; + LUT3_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_npd_av_o_6_axb_11 ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_limit_NPD[11]), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_NPD[11]), + .I2(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_infinite_NPD_3028), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_npd_av_o_6_axb_11_3027) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_pd_av_o_6_axb_11.INIT = 8'h09; + LUT3_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_pd_av_o_6_axb_11 ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_limit_PD[11]), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_PD[11]), + .I2(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_infinite_PD_3030), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_pd_av_o_6_axb_11_3029) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_fc_diff_data_axb_10.INIT = 4'h9; + LUT2 com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_fc_diff_data_axb_10 ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_prev_limit_data_q[10]), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_data_q[10]), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_fc_diff_data_axb_10_3031) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_fc_diff_data_axb_9.INIT = 4'h9; + LUT2 com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_fc_diff_data_axb_9 ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_prev_limit_data_q[9]), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_data_q[9]), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_fc_diff_data_axb_9_3032) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_fc_diff_data_axb_8.INIT = 4'h9; + LUT2 com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_fc_diff_data_axb_8 ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_prev_limit_data_q[8]), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_data_q[8]), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_fc_diff_data_axb_8_3033) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_fc_diff_data_axb_7.INIT = 4'h9; + LUT2 com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_fc_diff_data_axb_7 ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_prev_limit_data_q[7]), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_data_q[7]), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_fc_diff_data_axb_7_3034) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_fc_diff_data_axb_6.INIT = 4'h9; + LUT2 com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_fc_diff_data_axb_6 ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_prev_limit_data_q[6]), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_data_q[6]), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_fc_diff_data_axb_6_3035) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_fc_diff_data_axb_5.INIT = 4'h9; + LUT2 com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_fc_diff_data_axb_5 ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_prev_limit_data_q[5]), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_data_q[5]), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_fc_diff_data_axb_5_3036) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_fc_diff_data_axb_4.INIT = 4'h9; + LUT2 com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_fc_diff_data_axb_4 ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_prev_limit_data_q[4]), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_data_q[4]), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_fc_diff_data_axb_4_3037) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_fc_diff_data_axb_3.INIT = 4'h9; + LUT2 com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_fc_diff_data_axb_3 ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_prev_limit_data_q[3]), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_data_q[3]), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_fc_diff_data_axb_3_3038) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_fc_diff_data_axb_2.INIT = 4'h9; + LUT2 com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_fc_diff_data_axb_2 ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_prev_limit_data_q[2]), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_data_q[2]), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_fc_diff_data_axb_2_3039) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_fc_diff_data_axb_1.INIT = 4'h9; + LUT2 com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_fc_diff_data_axb_1 ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_prev_limit_data_q[1]), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_data_q[1]), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_fc_diff_data_axb_1_3040) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_fc_diff_data_axb_0.INIT = 4'h9; + LUT2 com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_fc_diff_data_axb_0 ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_prev_limit_data_q[0]), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_data_q[0]), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_fc_diff_data_axb_0_3041) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_pd_av_i_10_.INIT = 4'h1; + LUT1 com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_pd_av_i_10_ ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_pd_av[10]), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_pd_av_i[10]) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_pd_av_i_9_.INIT = 4'h1; + LUT1 com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_pd_av_i_9_ ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_pd_av[9]), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_pd_av_i[9]) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_pd_av_i_8_.INIT = 4'h1; + LUT1 com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_pd_av_i_8_ ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_pd_av[8]), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_pd_av_i[8]) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_pd_av_i_7_.INIT = 4'h1; + LUT1 com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_pd_av_i_7_ ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_pd_av[7]), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_pd_av_i[7]) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_pd_av_i_6_.INIT = 4'h1; + LUT1 com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_pd_av_i_6_ ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_pd_av[6]), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_pd_av_i[6]) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_fc_diff_header_axb_6.INIT = 4'h9; + LUT2 com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_fc_diff_header_axb_6 ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_prev_limit_header_q[6]), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_header_q[6]), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_fc_diff_header_axb_6_3042) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_fc_diff_header_axb_5.INIT = 4'h9; + LUT2 com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_fc_diff_header_axb_5 ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_prev_limit_header_q[5]), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_header_q[5]), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_fc_diff_header_axb_5_3043) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_fc_diff_header_axb_4.INIT = 4'h9; + LUT2 com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_fc_diff_header_axb_4 ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_prev_limit_header_q[4]), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_header_q[4]), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_fc_diff_header_axb_4_3044) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_fc_diff_header_axb_3.INIT = 4'h9; + LUT2 com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_fc_diff_header_axb_3 ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_prev_limit_header_q[3]), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_header_q[3]), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_fc_diff_header_axb_3_3045) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_fc_diff_header_axb_2.INIT = 4'h9; + LUT2 com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_fc_diff_header_axb_2 ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_prev_limit_header_q[2]), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_header_q[2]), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_fc_diff_header_axb_2_3046) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_fc_diff_header_axb_1.INIT = 4'h9; + LUT2 com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_fc_diff_header_axb_1 ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_prev_limit_header_q[1]), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_header_q[1]), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_fc_diff_header_axb_1_3047) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_fc_diff_header_axb_0.INIT = 4'h9; + LUT2 com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_fc_diff_header_axb_0 ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_prev_limit_header_q[0]), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_header_q[0]), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_fc_diff_header_axb_0_3048) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_cpld_av_i_10_.INIT = 4'h1; + LUT1 com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_cpld_av_i_10_ ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_cpld_av[10]), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_cpld_av_i[10]) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_cpld_av_i_9_.INIT = 4'h1; + LUT1 com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_cpld_av_i_9_ ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_cpld_av[9]), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_cpld_av_i[9]) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_cpld_av_i_8_.INIT = 4'h1; + LUT1 com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_cpld_av_i_8_ ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_cpld_av[8]), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_cpld_av_i[8]) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_cpld_av_i_7_.INIT = 4'h1; + LUT1 com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_cpld_av_i_7_ ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_cpld_av[7]), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_cpld_av_i[7]) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_cpld_av_i_6_.INIT = 4'h1; + LUT1 com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_cpld_av_i_6_ ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_cpld_av[6]), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_cpld_av_i[6]) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_npd_av_i_10_.INIT = 4'h1; + LUT1 com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_npd_av_i_10_ ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_npd_av[10]), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_npd_av_i[10]) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_npd_av_i_9_.INIT = 4'h1; + LUT1 com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_npd_av_i_9_ ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_npd_av[9]), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_npd_av_i[9]) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_npd_av_i_8_.INIT = 4'h1; + LUT1 com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_npd_av_i_8_ ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_npd_av[8]), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_npd_av_i[8]) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_npd_av_i_7_.INIT = 4'h1; + LUT1 com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_npd_av_i_7_ ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_npd_av[7]), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_npd_av_i[7]) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_npd_av_i_6_.INIT = 4'h1; + LUT1 com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_npd_av_i_6_ ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_npd_av[6]), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_npd_av_i[6]) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_av_data_cred_i_11_.INIT = 4'h1; + LUT1 com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_av_data_cred_i_11_ ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_av_data_cred[11]), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_av_data_cred_i_11__3049) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_av_data_cred_i_10_.INIT = 4'h1; + LUT1 com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_av_data_cred_i_10_ ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_av_data_cred[10]), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_av_data_cred_i_10__3050) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_av_data_cred_i_9_.INIT = 4'h1; + LUT1 com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_av_data_cred_i_9_ ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_av_data_cred[9]), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_av_data_cred_i_9__3051) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_av_data_cred_i_8_.INIT = 4'h1; + LUT1 com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_av_data_cred_i_8_ ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_av_data_cred[8]), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_av_data_cred_i_8__3052) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_av_data_cred_i_7_.INIT = 4'h1; + LUT1 com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_av_data_cred_i_7_ ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_av_data_cred[7]), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_av_data_cred_i_7__3053) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_av_data_cred_i_6_.INIT = 4'h1; + LUT1 com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_av_data_cred_i_6_ ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_av_data_cred[6]), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_av_data_cred_i_6__3054) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un7_credits_ok_axb_5_i.INIT = 4'h9; + LUT2 com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un7_credits_ok_axb_5_i ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_av_data_cred[5]), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_min_data_cred[5]), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un7_credits_ok_axb_5_i_3055) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un7_credits_ok_axb_4_i.INIT = 4'h9; + LUT2 com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un7_credits_ok_axb_4_i ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_av_data_cred[4]), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_min_data_cred[4]), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un7_credits_ok_axb_4_i_3056) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un7_credits_ok_axb_3_i.INIT = 4'h9; + LUT2 com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un7_credits_ok_axb_3_i ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_av_data_cred[3]), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_min_data_cred[3]), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un7_credits_ok_axb_3_i_3057) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_av_data_cred_i_2_.INIT = 4'h1; + LUT1 com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_av_data_cred_i_2_ ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_av_data_cred[2]), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_av_data_cred_i_2__3058) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_av_data_cred_i_1_.INIT = 4'h1; + LUT1 com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_av_data_cred_i_1_ ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_av_data_cred[1]), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_av_data_cred_i_1__3059) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un7_credits_ok_axb_0_i.INIT = 4'h9; + LUT2 com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un7_credits_ok_axb_0_i ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_av_data_cred[0]), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_suspend_cat[1]), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un7_credits_ok_axb_0_i_3060) + ); + GND com_tlm_u_tlm_tx_pm_ctrl_GND ( + .G(com_tlm_u_tlm_tx_pm_ctrl_GND_3061) + ); + FDR com_tlm_u_tlm_tx_pm_ctrl_cfg_ct_0_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_pm_ctrl_un1_cfg_ct_axb_0_3070), + .Q(com_tlm_u_tlm_tx_pm_ctrl_cfg_ct[0]), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_tx_pm_ctrl_cfg_ct_1_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_pm_ctrl_un1_cfg_ct_s_1_3062), + .Q(com_tlm_u_tlm_tx_pm_ctrl_cfg_ct[1]), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_tx_pm_ctrl_cfg_ct_2_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_pm_ctrl_un1_cfg_ct_s_2_3064), + .Q(com_tlm_u_tlm_tx_pm_ctrl_cfg_ct[2]), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_tx_pm_ctrl_cfg_ct_3_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_pm_ctrl_un1_cfg_ct_s_3_3066), + .Q(com_tlm_u_tlm_tx_pm_ctrl_cfg_ct[3]), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_tx_pm_ctrl_cfg_ct_4_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_pm_ctrl_un1_cfg_ct_s_4_3068), + .Q(com_tlm_u_tlm_tx_pm_ctrl_cfg_ct[4]), + .R(plm_link_up_i) + ); + FDRSE com_tlm_u_tlm_tx_pm_ctrl_cfg_pending ( + .CE(com_tlm_u_tlm_tx_pm_ctrl_cfg_ct23), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_pm_ctrl_N_17874_i_3072), + .Q(com_tlm_u_tlm_tx_pm_ctrl_cfg_pending_3071), + .R(plm_link_up_i), + .S(com_tlm_u_tlm_tx_cfg_accepted) + ); + FDR com_tlm_u_tlm_tx_pm_ctrl_aspm_suspend_req_o ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_pm_ctrl_N_42587), + .Q(com_cmmt_aspm_suspend_req), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_tx_pm_ctrl_ppm_suspend_ok_o ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_pm_ctrl_ppm_suspend_ok_o_3), + .Q(com_cmmt_ppm_suspend_ok), + .R(plm_link_up_i) + ); + MUXCY_L com_tlm_u_tlm_tx_pm_ctrl_un1_cfg_ct_cry_0 ( + .CI(com_tlm_u_tlm_tx_pm_ctrl_GND_3061), + .DI(com_tlm_u_tlm_tx_pm_ctrl_cfg_ct[0]), + .LO(com_tlm_u_tlm_tx_pm_ctrl_un1_cfg_ct_cry_0_3063), + .S(com_tlm_u_tlm_tx_pm_ctrl_un1_cfg_ct_axb_0_3070) + ); + MUXCY_L com_tlm_u_tlm_tx_pm_ctrl_un1_cfg_ct_cry_1 ( + .CI(com_tlm_u_tlm_tx_pm_ctrl_un1_cfg_ct_cry_0_3063), + .DI(com_tlm_u_tlm_tx_pm_ctrl_cfg_ct[1]), + .LO(com_tlm_u_tlm_tx_pm_ctrl_un1_cfg_ct_cry_1_3065), + .S(com_tlm_u_tlm_tx_pm_ctrl_un1_cfg_ct_axb_1_3076) + ); + XORCY com_tlm_u_tlm_tx_pm_ctrl_un1_cfg_ct_s_1 ( + .CI(com_tlm_u_tlm_tx_pm_ctrl_un1_cfg_ct_cry_0_3063), + .LI(com_tlm_u_tlm_tx_pm_ctrl_un1_cfg_ct_axb_1_3076), + .O(com_tlm_u_tlm_tx_pm_ctrl_un1_cfg_ct_s_1_3062) + ); + MUXCY_L com_tlm_u_tlm_tx_pm_ctrl_un1_cfg_ct_cry_2 ( + .CI(com_tlm_u_tlm_tx_pm_ctrl_un1_cfg_ct_cry_1_3065), + .DI(com_tlm_u_tlm_tx_pm_ctrl_cfg_ct[2]), + .LO(com_tlm_u_tlm_tx_pm_ctrl_un1_cfg_ct_cry_2_3067), + .S(com_tlm_u_tlm_tx_pm_ctrl_un1_cfg_ct_axb_2_3075) + ); + XORCY com_tlm_u_tlm_tx_pm_ctrl_un1_cfg_ct_s_2 ( + .CI(com_tlm_u_tlm_tx_pm_ctrl_un1_cfg_ct_cry_1_3065), + .LI(com_tlm_u_tlm_tx_pm_ctrl_un1_cfg_ct_axb_2_3075), + .O(com_tlm_u_tlm_tx_pm_ctrl_un1_cfg_ct_s_2_3064) + ); + MUXCY_L com_tlm_u_tlm_tx_pm_ctrl_un1_cfg_ct_cry_3 ( + .CI(com_tlm_u_tlm_tx_pm_ctrl_un1_cfg_ct_cry_2_3067), + .DI(com_tlm_u_tlm_tx_pm_ctrl_cfg_ct[3]), + .LO(com_tlm_u_tlm_tx_pm_ctrl_un1_cfg_ct_cry_3_3069), + .S(com_tlm_u_tlm_tx_pm_ctrl_un1_cfg_ct_axb_3_3074) + ); + XORCY com_tlm_u_tlm_tx_pm_ctrl_un1_cfg_ct_s_3 ( + .CI(com_tlm_u_tlm_tx_pm_ctrl_un1_cfg_ct_cry_2_3067), + .LI(com_tlm_u_tlm_tx_pm_ctrl_un1_cfg_ct_axb_3_3074), + .O(com_tlm_u_tlm_tx_pm_ctrl_un1_cfg_ct_s_3_3066) + ); + XORCY com_tlm_u_tlm_tx_pm_ctrl_un1_cfg_ct_s_4 ( + .CI(com_tlm_u_tlm_tx_pm_ctrl_un1_cfg_ct_cry_3_3069), + .LI(com_tlm_u_tlm_tx_pm_ctrl_un1_cfg_ct_axb_4_3073), + .O(com_tlm_u_tlm_tx_pm_ctrl_un1_cfg_ct_s_4_3068) + ); + defparam com_tlm_u_tlm_tx_pm_ctrl_cfg_ct23_0_a2.INIT = 4'h4; + LUT2 com_tlm_u_tlm_tx_pm_ctrl_cfg_ct23_0_a2 ( + .I0(com_tlm_u_tlm_tx_cfg_accepted), + .I1(com_tlm_u_tlm_tx_cfg_sent), + .O(com_tlm_u_tlm_tx_pm_ctrl_cfg_ct23) + ); + defparam com_tlm_u_tlm_tx_pm_ctrl_un1_cfg_ct_axb_0.INIT = 8'h96; + LUT3 com_tlm_u_tlm_tx_pm_ctrl_un1_cfg_ct_axb_0 ( + .I0(com_tlm_u_tlm_tx_cfg_accepted), + .I1(com_tlm_u_tlm_tx_cfg_sent), + .I2(com_tlm_u_tlm_tx_pm_ctrl_cfg_ct[0]), + .O(com_tlm_u_tlm_tx_pm_ctrl_un1_cfg_ct_axb_0_3070) + ); + defparam com_tlm_u_tlm_tx_pm_ctrl_ppm_suspend_ok_o_3_0_a4_0_a2_0_a2.INIT = 16'h0100; + LUT4_L com_tlm_u_tlm_tx_pm_ctrl_ppm_suspend_ok_o_3_0_a4_0_a2_0_a2 ( + .I0(com_cmmt_ppm_suspend_req_n), + .I1(com_tlm_u_tlm_tx_ack_pending), + .I2(com_tlm_u_tlm_tx_pm_ctrl_cfg_pending_3071), + .I3(com_tlm_u_tlm_tx_suspend_credit_rdy), + .LO(com_tlm_u_tlm_tx_pm_ctrl_ppm_suspend_ok_o_3) + ); + defparam com_tlm_u_tlm_tx_pm_ctrl_aspm_suspend_req_o_3_i_0_0_a2.INIT = 16'h0200; + LUT4_L com_tlm_u_tlm_tx_pm_ctrl_aspm_suspend_req_o_3_i_0_0_a2 ( + .I0(com_tlm_aspm_ok), + .I1(com_tlm_u_tlm_tx_ack_pending), + .I2(com_tlm_u_tlm_tx_pkt_incoming), + .I3(com_tlm_u_tlm_tx_queue_state[0]), + .LO(com_tlm_u_tlm_tx_pm_ctrl_N_42587) + ); + defparam com_tlm_u_tlm_tx_pm_ctrl_N_17874_i.INIT = 16'hFFFE; + LUT4_L com_tlm_u_tlm_tx_pm_ctrl_N_17874_i ( + .I0(com_tlm_u_tlm_tx_pm_ctrl_cfg_ct[1]), + .I1(com_tlm_u_tlm_tx_pm_ctrl_cfg_ct[2]), + .I2(com_tlm_u_tlm_tx_pm_ctrl_cfg_ct[3]), + .I3(com_tlm_u_tlm_tx_pm_ctrl_cfg_ct[4]), + .LO(com_tlm_u_tlm_tx_pm_ctrl_N_17874_i_3072) + ); + defparam com_tlm_u_tlm_tx_pm_ctrl_un1_cfg_ct_axb_4.INIT = 4'h6; + LUT2_L com_tlm_u_tlm_tx_pm_ctrl_un1_cfg_ct_axb_4 ( + .I0(com_tlm_u_tlm_tx_pm_ctrl_cfg_ct23), + .I1(com_tlm_u_tlm_tx_pm_ctrl_cfg_ct[4]), + .LO(com_tlm_u_tlm_tx_pm_ctrl_un1_cfg_ct_axb_4_3073) + ); + defparam com_tlm_u_tlm_tx_pm_ctrl_un1_cfg_ct_axb_3.INIT = 4'h6; + LUT2_L com_tlm_u_tlm_tx_pm_ctrl_un1_cfg_ct_axb_3 ( + .I0(com_tlm_u_tlm_tx_pm_ctrl_cfg_ct23), + .I1(com_tlm_u_tlm_tx_pm_ctrl_cfg_ct[3]), + .LO(com_tlm_u_tlm_tx_pm_ctrl_un1_cfg_ct_axb_3_3074) + ); + defparam com_tlm_u_tlm_tx_pm_ctrl_un1_cfg_ct_axb_2.INIT = 4'h6; + LUT2_L com_tlm_u_tlm_tx_pm_ctrl_un1_cfg_ct_axb_2 ( + .I0(com_tlm_u_tlm_tx_pm_ctrl_cfg_ct23), + .I1(com_tlm_u_tlm_tx_pm_ctrl_cfg_ct[2]), + .LO(com_tlm_u_tlm_tx_pm_ctrl_un1_cfg_ct_axb_2_3075) + ); + defparam com_tlm_u_tlm_tx_pm_ctrl_un1_cfg_ct_axb_1.INIT = 8'hA6; + LUT3_L com_tlm_u_tlm_tx_pm_ctrl_un1_cfg_ct_axb_1 ( + .I0(com_tlm_u_tlm_tx_pm_ctrl_cfg_ct[1]), + .I1(com_tlm_u_tlm_tx_cfg_sent), + .I2(com_tlm_u_tlm_tx_cfg_accepted), + .LO(com_tlm_u_tlm_tx_pm_ctrl_un1_cfg_ct_axb_1_3076) + ); + GND com_tlm_u_tlm_rx_vc0_rd_mon_GND ( + .G(com_tlm_u_tlm_rx_vc0_rd_mon_GND_3077) + ); + FDS com_tlm_u_tlm_rx_vc0_rd_mon_word_ct_0_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_rd_mon_N_13398_i), + .Q(com_tlm_u_tlm_rx_vc0_rd_mon_word_ct[0]), + .S(plm_link_up_i) + ); + FDRS com_tlm_u_tlm_rx_vc0_rd_mon_fc_free_1data_o ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_rd_mon_N_68337_i_3085), + .Q(com_tlm_u_tlm_rx_vc0_fc_free_1data), + .R(plm_link_up_i), + .S(com_tlm_u_tlm_rx_vc0_rd_mon_fc_free_1data_d_3078) + ); + FDR com_tlm_u_tlm_rx_vc0_rd_mon_fc_free_1header_o ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_rd_mon_fc_free_1header_o_5), + .Q(com_tlm_u_tlm_rx_vc0_fc_free_1header), + .R(plm_link_up_i) + ); + FDRE com_tlm_u_tlm_rx_vc0_rd_mon_unaligned_header_q ( + .CE(com_tlm_u_tlm_rx_vc0_rd_mon_N_68343_i_3088), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_rd_mon_N_41825_i_0_i_3084), + .Q(com_tlm_u_tlm_rx_vc0_rd_mon_unaligned_header_q_3080), + .R(plm_link_up_i) + ); + FDRSE com_tlm_u_tlm_rx_vc0_rd_mon_in_header ( + .CE(com_tlm_u_tlm_rx_vc0_rd_mon_un1_word_ct_2_0_a2_0_a2_0_a2_3087), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_rd_mon_GND_3077), + .Q(com_tlm_u_tlm_rx_vc0_rd_mon_in_header_3086), + .R(plm_link_up_i), + .S(com_tlm_u_tlm_rx_vc0_rd_mon_N_68343_i_3088) + ); + FDR com_tlm_u_tlm_rx_vc0_rd_mon_fc_free_p_o ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_rd_mon_fc_free_p_o_3_3081), + .Q(com_tlm_u_tlm_rx_vc0_fc_free_p), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_rx_vc0_rd_mon_fc_free_np_o ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_rd_mon_np_q_3082), + .Q(com_tlm_u_tlm_rx_vc0_fc_free_np), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_rx_vc0_rd_mon_fc_free_cpl_o ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_rd_mon_cpl_q_3083), + .Q(com_tlm_u_tlm_rx_vc0_fc_free_cpl), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_rx_vc0_rd_mon_np_q ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_np), + .Q(com_tlm_u_tlm_rx_vc0_rd_mon_np_q_3082), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_rx_vc0_rd_mon_cpl_q ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_cpl), + .Q(com_tlm_u_tlm_rx_vc0_rd_mon_cpl_q_3083), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_rx_vc0_rd_mon_fc_free_eof_o ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_N_41738_i_i), + .Q(com_tlm_u_tlm_rx_vc0_fc_free_eof), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_rx_vc0_rd_mon_fc_free_1data_d ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_rd_mon_fc_free_1data_dc_3079), + .Q(com_tlm_u_tlm_rx_vc0_rd_mon_fc_free_1data_d_3078), + .R(plm_link_up_i) + ); + defparam com_tlm_u_tlm_rx_vc0_rd_mon_word_ct_8_iv_i_0_0_o4_0_.INIT = 4'h2; + LUT2 com_tlm_u_tlm_rx_vc0_rd_mon_word_ct_8_iv_i_0_0_o4_0_ ( + .I0(com_tlm_u_tlm_rx_vc0_trn_rsrc_rdy), + .I1(trn_rdst_rdy_n), + .O(com_tlm_u_tlm_rx_vc0_N_41735_i) + ); + defparam com_tlm_u_tlm_rx_vc0_rd_mon_word_ct_8_iv_i_0_0_a3_0_.INIT = 4'h1; + LUT2 com_tlm_u_tlm_rx_vc0_rd_mon_word_ct_8_iv_i_0_0_a3_0_ ( + .I0(com_tlm_u_tlm_rx_vc0_cmmt_reof), + .I1(com_tlm_u_tlm_rx_vc0_cmmt_rsof), + .O(com_tlm_u_tlm_rx_vc0_rd_mon_N_43135) + ); + defparam com_tlm_u_tlm_rx_vc0_rd_mon_word_ct_8_iv_i_0_0_o4_1_0_.INIT = 8'h40; + LUT3 com_tlm_u_tlm_rx_vc0_rd_mon_word_ct_8_iv_i_0_0_o4_1_0_ ( + .I0(cfg_cfg_5072[508]), + .I1(NlwRenamedSig_OI_trn_rd[47]), + .I2(NlwRenamedSig_OI_trn_rd[61]), + .O(com_tlm_u_tlm_rx_vc0_rd_mon_word_ct_8_iv_i_0_0_o4_1[0]) + ); + defparam com_tlm_u_tlm_rx_vc0_rd_mon_un1_trn_sof_i_1_i_i_0_o2_0_o2_0_o2.INIT = 16'h153F; + LUT4 com_tlm_u_tlm_rx_vc0_rd_mon_un1_trn_sof_i_1_i_i_0_o2_0_o2_0_o2 ( + .I0(com_tlm_u_tlm_rx_vc0_N_41735_i), + .I1(com_tlm_u_tlm_rx_vc0_N_41743_i), + .I2(com_tlm_u_tlm_rx_vc0_cmmt_rsof), + .I3(com_tlm_u_tlm_rx_vc0_trn_rsof), + .O(com_tlm_u_tlm_rx_vc0_rd_mon_un1_trn_sof_i_1_i_i_0_o2_0_o2_0_o2_3089) + ); + defparam com_tlm_u_tlm_rx_vc0_rd_mon_un1_word_ct_2_0_a2_0_a2_0_a2.INIT = 8'h0E; + LUT3 com_tlm_u_tlm_rx_vc0_rd_mon_un1_word_ct_2_0_a2_0_a2_0_a2 ( + .I0(com_tlm_u_tlm_rx_vc0_N_41735_i), + .I1(com_tlm_u_tlm_rx_vc0_N_41743_i), + .I2(com_tlm_u_tlm_rx_vc0_rd_mon_word_ct[0]), + .O(com_tlm_u_tlm_rx_vc0_rd_mon_un1_word_ct_2_0_a2_0_a2_0_a2_3087) + ); + defparam com_tlm_u_tlm_rx_vc0_rd_mon_word_ct_8_iv_i_0_0_a2_0_1_0_.INIT = 16'hE211; + LUT4 com_tlm_u_tlm_rx_vc0_rd_mon_word_ct_8_iv_i_0_0_a2_0_1_0_ ( + .I0(com_tlm_u_tlm_rx_vc0_N_41735_i), + .I1(com_tlm_u_tlm_rx_vc0_N_41743_i), + .I2(com_tlm_u_tlm_rx_vc0_rd_mon_N_43135), + .I3(com_tlm_u_tlm_rx_vc0_rd_mon_word_ct[0]), + .O(com_tlm_u_tlm_rx_vc0_rd_mon_N_42463_1) + ); + defparam com_tlm_u_tlm_rx_vc0_rd_mon_word_ct_8_iv_i_0_0_0_0_.INIT = 16'hBBB0; + LUT4_L com_tlm_u_tlm_rx_vc0_rd_mon_word_ct_8_iv_i_0_0_0_0_ ( + .I0(com_tlm_u_tlm_rx_vc0_N_41735_i), + .I1(com_tlm_u_tlm_rx_vc0_rd_mon_N_42463_1), + .I2(com_tlm_u_tlm_rx_vc0_rd_mon_un1_trn_sof_i_1_i_i_0_o2_0_o2_0_o2_3089), + .I3(com_tlm_u_tlm_rx_vc0_rd_mon_word_ct_8_iv_i_0_0_o4_1[0]), + .LO(com_tlm_u_tlm_rx_vc0_rd_mon_word_ct_8_iv_i_0_0_0[0]) + ); + defparam com_tlm_u_tlm_rx_vc0_rd_mon_fc_free_1data_dc.INIT = 16'h0040; + LUT4_L com_tlm_u_tlm_rx_vc0_rd_mon_fc_free_1data_dc ( + .I0(com_tlm_u_tlm_rx_vc0_N_41738_i), + .I1(com_tlm_u_tlm_rx_vc0_trn_rrem), + .I2(com_tlm_u_tlm_rx_vc0_rd_mon_unaligned_header_q_3080), + .I3(com_tlm_u_tlm_rx_vc0_rd_mon_word_ct[0]), + .LO(com_tlm_u_tlm_rx_vc0_rd_mon_fc_free_1data_dc_3079) + ); + defparam com_tlm_u_tlm_rx_vc0_rd_mon_fc_free_p_o_3.INIT = 4'h1; + LUT2_L com_tlm_u_tlm_rx_vc0_rd_mon_fc_free_p_o_3 ( + .I0(com_tlm_u_tlm_rx_vc0_rd_mon_cpl_q_3083), + .I1(com_tlm_u_tlm_rx_vc0_rd_mon_np_q_3082), + .LO(com_tlm_u_tlm_rx_vc0_rd_mon_fc_free_p_o_3_3081) + ); + defparam com_tlm_u_tlm_rx_vc0_rd_mon_N_41825_i_0_i.INIT = 8'h4B; + LUT3_L com_tlm_u_tlm_rx_vc0_rd_mon_N_41825_i_0_i ( + .I0(cfg_cfg_5072[508]), + .I1(NlwRenamedSig_OI_trn_rd[47]), + .I2(NlwRenamedSig_OI_trn_rd[61]), + .LO(com_tlm_u_tlm_rx_vc0_rd_mon_N_41825_i_0_i_3084) + ); + defparam com_tlm_u_tlm_rx_vc0_rd_mon_fc_free_1header_o_5_0_a2_0_a2_0_a2.INIT = 4'h8; + LUT2_L com_tlm_u_tlm_rx_vc0_rd_mon_fc_free_1header_o_5_0_a2_0_a2_0_a2 ( + .I0(com_tlm_u_tlm_rx_vc0_rd_mon_un1_word_ct_2_0_a2_0_a2_0_a2_3087), + .I1(com_tlm_u_tlm_rx_vc0_rd_mon_in_header_3086), + .LO(com_tlm_u_tlm_rx_vc0_rd_mon_fc_free_1header_o_5) + ); + defparam com_tlm_u_tlm_rx_vc0_rd_mon_N_68337_i.INIT = 8'h0D; + LUT3_L com_tlm_u_tlm_rx_vc0_rd_mon_N_68337_i ( + .I0(com_tlm_u_tlm_rx_vc0_N_41738_i), + .I1(com_tlm_u_tlm_rx_vc0_rd_mon_un1_word_ct_2_0_a2_0_a2_0_a2_3087), + .I2(com_tlm_u_tlm_rx_vc0_rd_mon_in_header_3086), + .LO(com_tlm_u_tlm_rx_vc0_rd_mon_N_68337_i_3085) + ); + defparam com_tlm_u_tlm_rx_vc0_rd_mon_word_ct_8_iv_i_0_0_0_.INIT = 16'hFD00; + LUT4_L com_tlm_u_tlm_rx_vc0_rd_mon_word_ct_8_iv_i_0_0_0_ ( + .I0(com_tlm_u_tlm_rx_vc0_rd_mon_N_42463_1), + .I1(com_tlm_u_tlm_rx_vc0_trn_reof), + .I2(com_tlm_u_tlm_rx_vc0_trn_rsof), + .I3(com_tlm_u_tlm_rx_vc0_rd_mon_word_ct_8_iv_i_0_0_0[0]), + .LO(com_tlm_u_tlm_rx_vc0_rd_mon_N_13398_i) + ); + INV com_tlm_u_tlm_rx_vc0_rd_mon_N_68343_i ( + .I(com_tlm_u_tlm_rx_vc0_rd_mon_un1_trn_sof_i_1_i_i_0_o2_0_o2_0_o2_3089), + .O(com_tlm_u_tlm_rx_vc0_rd_mon_N_68343_i_3088) + ); + GND com_tlm_u_tlm_rx_vc0_fifo_GND ( + .G(com_tlm_u_tlm_rx_vc0_fifo_GND_3090) + ); + FDRSE com_tlm_u_tlm_rx_vc0_fifo_select_bq ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_N_67945_i_3194), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_GND_3090), + .Q(com_tlm_u_tlm_rx_vc0_fifo_select_bq_3108), + .R(plm_link_up_i), + .S(com_tlm_u_tlm_rx_vc0_fifo_select_bq_0_sqmuxa_3097) + ); + FDRE com_tlm_u_tlm_rx_vc0_fifo_select_usr ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_N_67945_i_3194), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_select_usr_7), + .Q(com_tlm_u_tlm_rx_vc0_fifo_select_usr_3103), + .R(plm_link_up_i) + ); + FDRE com_tlm_u_tlm_rx_vc0_fifo_select_cfg ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_N_67945_i_3194), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_select_cfg_7), + .Q(com_tlm_u_tlm_rx_vc0_fifo_select_cfg_3106), + .R(plm_link_up_i) + ); + FDRE com_tlm_u_tlm_rx_vc0_fifo_select_oq ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_N_67945_i_3194), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_select_bq17_3111), + .Q(com_tlm_u_tlm_rx_vc0_fifo_select_oq_3107), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_rx_vc0_fifo_select_oq2bq_d ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_select_oq2bq_d_5_3109), + .Q(com_tlm_u_tlm_rx_vc0_fifo_select_oq2bq_d_3110), + .R(plm_link_up_i) + ); + FDRE com_tlm_u_tlm_rx_vc0_fifo_cfg_src_rdy_d ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_N_68339_i_3192), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_cfg_src_rdy_d_3_3104), + .Q(com_cmmt_rsrc_rdy), + .R(plm_link_up_i) + ); + FDRE com_tlm_u_tlm_rx_vc0_fifo_usr_src_rdy_d ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_N_68339_i_3192), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_usr_src_rdy_d_3_3102), + .Q(com_tlm_u_tlm_rx_vc0_trn_rsrc_rdy), + .R(plm_link_up_i) + ); + FDRE com_tlm_u_tlm_rx_vc0_fifo_usr_sof_d ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_N_68339_i_3192), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_N_9519_i_3100), + .Q(com_tlm_u_tlm_rx_vc0_trn_rsof), + .R(plm_link_up_i) + ); + FDRE com_tlm_u_tlm_rx_vc0_fifo_select_oq2bq ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_un1_select_oq2bq_d_1_i_3114), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_select_oq2bq_5), + .Q(com_tlm_u_tlm_rx_vc0_fifo_select_oq2bq_3117), + .R(plm_link_up_i) + ); + FDRE com_tlm_u_tlm_rx_vc0_fifo_cfg_eof_d ( + .CE(com_tlm_u_tlm_rx_vc0_N_41743_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_N_9522_i), + .Q(com_tlm_u_tlm_rx_vc0_cmmt_reof), + .R(plm_link_up_i) + ); + FDRE com_tlm_u_tlm_rx_vc0_fifo_cfg_sof_d ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_N_68339_i_3192), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_N_9521_i_3099), + .Q(com_tlm_u_tlm_rx_vc0_cmmt_rsof), + .R(plm_link_up_i) + ); + FDRE com_tlm_u_tlm_rx_vc0_fifo_usr_eof_d ( + .CE(com_tlm_u_tlm_rx_vc0_N_41735_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_N_9522_i), + .Q(com_tlm_u_tlm_rx_vc0_trn_reof), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_rx_vc0_fifo_wen_aux_oq ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_wen_aux_oq_3), + .Q(com_tlm_u_tlm_rx_vc0_fifo_wen_aux_oq_3091), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_rx_vc0_fifo_usr_src_dsc_o ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_reset_i_q_i_3098), + .Q(com_tlm_u_tlm_rx_vc0_fifo_trn_rsrc_dsc), + .R(plm_link_up) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_un1_wait_bqr.INIT = 4'h1; + LUT2 com_tlm_u_tlm_rx_vc0_fifo_un1_wait_bqr ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_data_vld_bqr), + .I1(com_tlm_u_tlm_rx_vc0_fifo_nxt_vld_bqr), + .O(com_tlm_u_tlm_rx_vc0_fifo_N_9528) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_un4_cfg_sof_d_1_0_a2.INIT = 4'h8; + LUT2 com_tlm_u_tlm_rx_vc0_fifo_un4_cfg_sof_d_1_0_a2 ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_data_bqr_64_), + .I1(com_tlm_u_tlm_rx_vc0_fifo_select_bq_3108), + .O(com_tlm_u_tlm_rx_vc0_fifo_un4_cfg_sof_d_1) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_adv_pkt_out_i_0_0_a2.INIT = 4'h1; + LUT2 com_tlm_u_tlm_rx_vc0_fifo_adv_pkt_out_i_0_0_a2 ( + .I0(com_cmmt_rsrc_rdy), + .I1(com_tlm_u_tlm_rx_vc0_trn_rsrc_rdy), + .O(com_tlm_u_tlm_rx_vc0_fifo_adv_pkt_out_i_0_0_a2_3094) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_cfg_nxt_rdy_0_a2_0_a2.INIT = 4'h1; + LUT2 com_tlm_u_tlm_rx_vc0_fifo_cfg_nxt_rdy_0_a2_0_a2 ( + .I0(com_cmmt_rdst_rdy_n), + .I1(com_cmmt_rsrc_rdy), + .O(com_tlm_u_tlm_rx_vc0_fifo_cfg_nxt_rdy) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_cfg_adv_out_0_o2_i_a2_0_o4.INIT = 4'h4; + LUT2 com_tlm_u_tlm_rx_vc0_fifo_cfg_adv_out_0_o2_i_a2_0_o4 ( + .I0(com_cmmt_rdst_rdy_n), + .I1(com_cmmt_rsrc_rdy), + .O(com_tlm_u_tlm_rx_vc0_N_41743_i) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_un5_usr_src_rdy_d.INIT = 4'h8; + LUT2 com_tlm_u_tlm_rx_vc0_fifo_un5_usr_src_rdy_d ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_data_vld_oqr), + .I1(com_tlm_u_tlm_rx_vc0_fifo_select_oq_3107), + .O(com_tlm_u_tlm_rx_vc0_fifo_un5_usr_src_rdy_d_3105) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_cfg_eof_d_3_0_o3_0.INIT = 4'h8; + LUT2 com_tlm_u_tlm_rx_vc0_fifo_cfg_eof_d_3_0_o3_0 ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_ram_dout[65]), + .I1(com_tlm_u_tlm_rx_vc0_fifo_select_oq_3107), + .O(com_tlm_u_tlm_rx_vc0_fifo_N_14286_i) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_un1_select_oq2bq_d_1_i.INIT = 4'hE; + LUT2 com_tlm_u_tlm_rx_vc0_fifo_un1_select_oq2bq_d_1_i ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_select_oq2bq_3117), + .I1(com_tlm_u_tlm_rx_vc0_fifo_select_oq2bq_d_3110), + .O(com_tlm_u_tlm_rx_vc0_fifo_un1_select_oq2bq_d_1_i_3114) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_un5_cfg_sof_d_1.INIT = 4'h8; + LUT2 com_tlm_u_tlm_rx_vc0_fifo_un5_cfg_sof_d_1 ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_select_oq_3107), + .I1(com_tlm_u_tlm_rx_vc0_fifo_sof_oqr), + .O(com_tlm_u_tlm_rx_vc0_fifo_un5_cfg_sof_d_1_3101) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_un1_adv_pkt_oq_1.INIT = 16'h0008; + LUT4 com_tlm_u_tlm_rx_vc0_fifo_un1_adv_pkt_oq_1 ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_aux_vld_oqr), + .I1(com_tlm_u_tlm_rx_vc0_fifo_data_vld_oqr), + .I2(com_tlm_u_tlm_rx_vc0_fifo_select_oq2bq_3117), + .I3(com_tlm_u_tlm_rx_vc0_fifo_select_oq2bq_d_3110), + .O(com_tlm_u_tlm_rx_vc0_fifo_un1_adv_pkt_oq_1_3093) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_un4_adv_pkt_oq_0.INIT = 16'h8BBB; + LUT4_L com_tlm_u_tlm_rx_vc0_fifo_un4_adv_pkt_oq_0 ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_cfg_nxt_rdy), + .I1(com_tlm_u_tlm_rx_vc0_fifo_cfg_oqr), + .I2(com_tlm_u_tlm_rx_vc0_fifo_np_oqr), + .I3(trn_rnp_ok_n), + .LO(com_tlm_u_tlm_rx_vc0_fifo_un4_adv_pkt_oq) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_adv_pkt_bq_0.INIT = 16'hCA00; + LUT4 com_tlm_u_tlm_rx_vc0_fifo_adv_pkt_bq_0 ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_aux_vld), + .I1(com_tlm_u_tlm_rx_vc0_fifo_aux_vld_q), + .I2(com_tlm_u_tlm_rx_vc0_fifo_sof_hold), + .I3(com_tlm_u_tlm_rx_vc0_fifo_data_vld_bqr), + .O(com_tlm_u_tlm_rx_vc0_fifo_adv_pkt_bq_0_3092) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_adv_pkt_in_i_0.INIT = 16'h8CA0; + LUT4 com_tlm_u_tlm_rx_vc0_fifo_adv_pkt_in_i_0 ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_data_vld_bqr), + .I1(com_tlm_u_tlm_rx_vc0_fifo_data_vld_oqr), + .I2(com_tlm_u_tlm_rx_vc0_fifo_select_bq_3108), + .I3(com_tlm_u_tlm_rx_vc0_fifo_select_oq_3107), + .O(com_tlm_u_tlm_rx_vc0_fifo_adv_pkt_in_i_0_3095) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_N_14376_i.INIT = 16'hECA0; + LUT4 com_tlm_u_tlm_rx_vc0_fifo_N_14376_i ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_data_bqr_46_), + .I1(com_tlm_u_tlm_rx_vc0_fifo_ep_oqr), + .I2(com_tlm_u_tlm_rx_vc0_fifo_select_bq_3108), + .I3(com_tlm_u_tlm_rx_vc0_fifo_select_oq_3107), + .O(com_tlm_u_tlm_rx_vc0_fifo_N_14376_i_3145) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_cfg_eof_d_3_0.INIT = 16'hECA0; + LUT4 com_tlm_u_tlm_rx_vc0_fifo_cfg_eof_d_3_0 ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_N_14286_i), + .I1(com_tlm_u_tlm_rx_vc0_fifo_data_bqr_65_), + .I2(com_tlm_u_tlm_rx_vc0_fifo_data_vld_oqr), + .I3(com_tlm_u_tlm_rx_vc0_fifo_select_bq_3108), + .O(com_tlm_u_tlm_rx_vc0_fifo_N_9522_i) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_adv_pkt_out_i_0_0_o2.INIT = 16'h153F; + LUT4 com_tlm_u_tlm_rx_vc0_fifo_adv_pkt_out_i_0_0_o2 ( + .I0(com_tlm_u_tlm_rx_vc0_N_41735_i), + .I1(com_tlm_u_tlm_rx_vc0_N_41743_i), + .I2(com_tlm_u_tlm_rx_vc0_cmmt_reof), + .I3(com_tlm_u_tlm_rx_vc0_trn_reof), + .O(com_tlm_u_tlm_rx_vc0_N_41738_i) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_adv_out_i_0.INIT = 8'h01; + LUT3 com_tlm_u_tlm_rx_vc0_fifo_adv_out_i_0 ( + .I0(com_tlm_u_tlm_rx_vc0_N_41735_i), + .I1(com_tlm_u_tlm_rx_vc0_N_41743_i), + .I2(com_tlm_u_tlm_rx_vc0_fifo_adv_pkt_out_i_0_0_a2_3094), + .O(com_tlm_u_tlm_rx_vc0_fifo_adv_out_i_0_3193) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_adv_pkt_bq.INIT = 16'h80A2; + LUT4 com_tlm_u_tlm_rx_vc0_fifo_adv_pkt_bq ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_adv_pkt_bq_0_3092), + .I1(com_tlm_u_tlm_rx_vc0_fifo_aux_bqr[7]), + .I2(com_tlm_u_tlm_rx_vc0_fifo_cfg_nxt_rdy), + .I3(trn_rnp_ok_n), + .O(com_tlm_u_tlm_rx_vc0_fifo_adv_pkt_bq_3113) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_un1_adv_pkt_oq.INIT = 16'hB000; + LUT4 com_tlm_u_tlm_rx_vc0_fifo_un1_adv_pkt_oq ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_N_9528), + .I1(com_tlm_u_tlm_rx_vc0_fifo_np_oqr), + .I2(com_tlm_u_tlm_rx_vc0_fifo_un1_adv_pkt_oq_1_3093), + .I3(com_tlm_u_tlm_rx_vc0_fifo_un4_adv_pkt_oq), + .O(com_tlm_u_tlm_rx_vc0_fifo_un1_adv_pkt_oq_3112) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_N_68338_i.INIT = 4'hD; + LUT2 com_tlm_u_tlm_rx_vc0_fifo_N_68338_i ( + .I0(com_tlm_u_tlm_rx_vc0_N_41738_i), + .I1(com_tlm_u_tlm_rx_vc0_fifo_adv_pkt_out_i_0_0_a2_3094), + .O(com_tlm_u_tlm_rx_vc0_fifo_N_68338_i_3126) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_ren_oq_i_o2.INIT = 8'h0B; + LUT3 com_tlm_u_tlm_rx_vc0_fifo_ren_oq_i_o2 ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_adv_out_i_0_3193), + .I1(com_tlm_u_tlm_rx_vc0_fifo_select_oq_3107), + .I2(com_tlm_u_tlm_rx_vc0_fifo_select_oq2bq_3117), + .O(com_tlm_u_tlm_rx_vc0_fifo_N_9516_i_i) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_adv_pkt_in_i_1.INIT = 16'h8CCC; + LUT4 com_tlm_u_tlm_rx_vc0_fifo_adv_pkt_in_i_1 ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_adv_out_i_0_3193), + .I1(com_tlm_u_tlm_rx_vc0_fifo_adv_pkt_in_i_0_3095), + .I2(com_tlm_u_tlm_rx_vc0_fifo_data_bqr_65_), + .I3(com_tlm_u_tlm_rx_vc0_fifo_select_bq_3108), + .O(com_tlm_u_tlm_rx_vc0_fifo_adv_pkt_in_i_1_3096) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_adv_pkt_in_i.INIT = 16'h50D0; + LUT4 com_tlm_u_tlm_rx_vc0_fifo_adv_pkt_in_i ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_N_14286_i), + .I1(com_tlm_u_tlm_rx_vc0_fifo_adv_out_i_0_3193), + .I2(com_tlm_u_tlm_rx_vc0_fifo_adv_pkt_in_i_1_3096), + .I3(com_tlm_u_tlm_rx_vc0_fifo_select_oq2bq_3117), + .O(com_tlm_u_tlm_rx_vc0_fifo_adv_pkt_in_i_3195) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_un1_data_oqr_0_0_.INIT = 8'hE4; + LUT3_L com_tlm_u_tlm_rx_vc0_fifo_un1_data_oqr_0_0_ ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_N_9516_i_i), + .I1(com_tlm_u_tlm_rx_vc0_fifo_eof_oqr), + .I2(com_tlm_u_tlm_rx_vc0_fifo_sof_oqr), + .LO(com_tlm_u_tlm_rx_vc0_fifo_un1_data_oqr[0]) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_select_bq_0_sqmuxa.INIT = 4'h4; + LUT2 com_tlm_u_tlm_rx_vc0_fifo_select_bq_0_sqmuxa ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_adv_pkt_in_i_3195), + .I1(com_tlm_u_tlm_rx_vc0_fifo_adv_pkt_bq_3113), + .O(com_tlm_u_tlm_rx_vc0_fifo_select_bq_0_sqmuxa_3097) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_N_41738_i_i.INIT = 4'h1; + LUT1_L com_tlm_u_tlm_rx_vc0_fifo_N_41738_i_i ( + .I0(com_tlm_u_tlm_rx_vc0_N_41738_i), + .LO(com_tlm_u_tlm_rx_vc0_N_41738_i_i) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_reset_i_q_i.INIT = 4'h1; + LUT1_L com_tlm_u_tlm_rx_vc0_fifo_reset_i_q_i ( + .I0(com_reset_i_q), + .LO(com_tlm_u_tlm_rx_vc0_fifo_reset_i_q_i_3098) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_rem_out_rem_out_N_9523_i.INIT = 16'hECA0; + LUT4_L com_tlm_u_tlm_rx_vc0_fifo_rem_out_rem_out_N_9523_i ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_data_bqr_67_), + .I1(com_tlm_u_tlm_rx_vc0_fifo_rem_oqr), + .I2(com_tlm_u_tlm_rx_vc0_fifo_select_bq_3108), + .I3(com_tlm_u_tlm_rx_vc0_fifo_select_oq_3107), + .LO(com_tlm_u_tlm_rx_vc0_fifo_N_9523_i) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_N_9521_i.INIT = 16'hECA0; + LUT4_L com_tlm_u_tlm_rx_vc0_fifo_N_9521_i ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_aux_bqr[7]), + .I1(com_tlm_u_tlm_rx_vc0_fifo_cfg_oqr), + .I2(com_tlm_u_tlm_rx_vc0_fifo_un4_cfg_sof_d_1), + .I3(com_tlm_u_tlm_rx_vc0_fifo_un5_cfg_sof_d_1_3101), + .LO(com_tlm_u_tlm_rx_vc0_fifo_N_9521_i_3099) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_select_oq2bq_5_0.INIT = 16'h0A33; + LUT4_L com_tlm_u_tlm_rx_vc0_fifo_select_oq2bq_5_0 ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_data_vld_oqr), + .I1(com_tlm_u_tlm_rx_vc0_fifo_eof_oqr), + .I2(com_tlm_u_tlm_rx_vc0_fifo_select_oq_3107), + .I3(com_tlm_u_tlm_rx_vc0_fifo_select_oq2bq_d_3110), + .LO(com_tlm_u_tlm_rx_vc0_fifo_select_oq2bq_5) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_N_9519_i.INIT = 16'h7350; + LUT4_L com_tlm_u_tlm_rx_vc0_fifo_N_9519_i ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_aux_bqr[7]), + .I1(com_tlm_u_tlm_rx_vc0_fifo_cfg_oqr), + .I2(com_tlm_u_tlm_rx_vc0_fifo_un4_cfg_sof_d_1), + .I3(com_tlm_u_tlm_rx_vc0_fifo_un5_cfg_sof_d_1_3101), + .LO(com_tlm_u_tlm_rx_vc0_fifo_N_9519_i_3100) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_N_9308_i.INIT = 16'hECA0; + LUT4_L com_tlm_u_tlm_rx_vc0_fifo_N_9308_i ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_aux_bqr[6]), + .I1(com_tlm_u_tlm_rx_vc0_fifo_aux_oqr[6]), + .I2(com_tlm_u_tlm_rx_vc0_fifo_select_bq_3108), + .I3(com_tlm_u_tlm_rx_vc0_fifo_select_oq_3107), + .LO(com_tlm_u_tlm_rx_vc0_fifo_N_9308_i_3118) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_N_9309_i.INIT = 16'hECA0; + LUT4_L com_tlm_u_tlm_rx_vc0_fifo_N_9309_i ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_aux_bqr[5]), + .I1(com_tlm_u_tlm_rx_vc0_fifo_aux_oqr[5]), + .I2(com_tlm_u_tlm_rx_vc0_fifo_select_bq_3108), + .I3(com_tlm_u_tlm_rx_vc0_fifo_select_oq_3107), + .LO(com_tlm_u_tlm_rx_vc0_fifo_N_9309_i_3119) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_N_9310_i.INIT = 16'hECA0; + LUT4_L com_tlm_u_tlm_rx_vc0_fifo_N_9310_i ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_aux_bqr[4]), + .I1(com_tlm_u_tlm_rx_vc0_fifo_aux_oqr[4]), + .I2(com_tlm_u_tlm_rx_vc0_fifo_select_bq_3108), + .I3(com_tlm_u_tlm_rx_vc0_fifo_select_oq_3107), + .LO(com_tlm_u_tlm_rx_vc0_fifo_N_9310_i_3120) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_N_9311_i.INIT = 16'hECA0; + LUT4_L com_tlm_u_tlm_rx_vc0_fifo_N_9311_i ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_aux_bqr[3]), + .I1(com_tlm_u_tlm_rx_vc0_fifo_aux_oqr[3]), + .I2(com_tlm_u_tlm_rx_vc0_fifo_select_bq_3108), + .I3(com_tlm_u_tlm_rx_vc0_fifo_select_oq_3107), + .LO(com_tlm_u_tlm_rx_vc0_fifo_N_9311_i_3121) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_N_9312_i.INIT = 16'hECA0; + LUT4_L com_tlm_u_tlm_rx_vc0_fifo_N_9312_i ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_aux_bqr[2]), + .I1(com_tlm_u_tlm_rx_vc0_fifo_aux_oqr[2]), + .I2(com_tlm_u_tlm_rx_vc0_fifo_select_bq_3108), + .I3(com_tlm_u_tlm_rx_vc0_fifo_select_oq_3107), + .LO(com_tlm_u_tlm_rx_vc0_fifo_N_9312_i_3122) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_N_9313_i.INIT = 16'hECA0; + LUT4_L com_tlm_u_tlm_rx_vc0_fifo_N_9313_i ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_aux_bqr[1]), + .I1(com_tlm_u_tlm_rx_vc0_fifo_aux_oqr[1]), + .I2(com_tlm_u_tlm_rx_vc0_fifo_select_bq_3108), + .I3(com_tlm_u_tlm_rx_vc0_fifo_select_oq_3107), + .LO(com_tlm_u_tlm_rx_vc0_fifo_N_9313_i_3123) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_N_9314_i.INIT = 16'hECA0; + LUT4_L com_tlm_u_tlm_rx_vc0_fifo_N_9314_i ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_aux_bqr[0]), + .I1(com_tlm_u_tlm_rx_vc0_fifo_aux_oqr[0]), + .I2(com_tlm_u_tlm_rx_vc0_fifo_select_bq_3108), + .I3(com_tlm_u_tlm_rx_vc0_fifo_select_oq_3107), + .LO(com_tlm_u_tlm_rx_vc0_fifo_N_9314_i_3124) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_un8_cpl_d.INIT = 4'h8; + LUT2_L com_tlm_u_tlm_rx_vc0_fifo_un8_cpl_d ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_ram_dout[66]), + .I1(com_tlm_u_tlm_rx_vc0_fifo_un5_usr_src_rdy_d_3105), + .LO(com_tlm_u_tlm_rx_vc0_fifo_un8_cpl_d_3125) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_N_9520_i.INIT = 8'hEC; + LUT3_L com_tlm_u_tlm_rx_vc0_fifo_N_9520_i ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_np_oqr), + .I1(com_tlm_u_tlm_rx_vc0_fifo_select_bq_3108), + .I2(com_tlm_u_tlm_rx_vc0_fifo_select_oq_3107), + .LO(com_tlm_u_tlm_rx_vc0_fifo_N_9520_i_3127) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_usr_src_rdy_d_3.INIT = 16'hF080; + LUT4_L com_tlm_u_tlm_rx_vc0_fifo_usr_src_rdy_d_3 ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_data_vld_bqr), + .I1(com_tlm_u_tlm_rx_vc0_fifo_select_bq_3108), + .I2(com_tlm_u_tlm_rx_vc0_fifo_select_usr_3103), + .I3(com_tlm_u_tlm_rx_vc0_fifo_un5_usr_src_rdy_d_3105), + .LO(com_tlm_u_tlm_rx_vc0_fifo_usr_src_rdy_d_3_3102) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_cfg_src_rdy_d_3.INIT = 16'hF080; + LUT4_L com_tlm_u_tlm_rx_vc0_fifo_cfg_src_rdy_d_3 ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_data_vld_bqr), + .I1(com_tlm_u_tlm_rx_vc0_fifo_select_bq_3108), + .I2(com_tlm_u_tlm_rx_vc0_fifo_select_cfg_3106), + .I3(com_tlm_u_tlm_rx_vc0_fifo_un5_usr_src_rdy_d_3105), + .LO(com_tlm_u_tlm_rx_vc0_fifo_cfg_src_rdy_d_3_3104) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_N_9245_i.INIT = 16'hECA0; + LUT4_L com_tlm_u_tlm_rx_vc0_fifo_N_9245_i ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_data_bqr_63_), + .I1(com_tlm_u_tlm_rx_vc0_fifo_data_oqr_63_), + .I2(com_tlm_u_tlm_rx_vc0_fifo_select_bq_3108), + .I3(com_tlm_u_tlm_rx_vc0_fifo_select_oq_3107), + .LO(com_tlm_u_tlm_rx_vc0_fifo_N_9245_i_3128) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_N_9246_i.INIT = 16'hECA0; + LUT4_L com_tlm_u_tlm_rx_vc0_fifo_N_9246_i ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_data_bqr_62_), + .I1(com_tlm_u_tlm_rx_vc0_fifo_data_oqr_62_), + .I2(com_tlm_u_tlm_rx_vc0_fifo_select_bq_3108), + .I3(com_tlm_u_tlm_rx_vc0_fifo_select_oq_3107), + .LO(com_tlm_u_tlm_rx_vc0_fifo_N_9246_i_3129) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_N_9247_i.INIT = 16'hECA0; + LUT4_L com_tlm_u_tlm_rx_vc0_fifo_N_9247_i ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_data_bqr_61_), + .I1(com_tlm_u_tlm_rx_vc0_fifo_data_oqr_61_), + .I2(com_tlm_u_tlm_rx_vc0_fifo_select_bq_3108), + .I3(com_tlm_u_tlm_rx_vc0_fifo_select_oq_3107), + .LO(com_tlm_u_tlm_rx_vc0_fifo_N_9247_i_3130) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_N_9248_i.INIT = 16'hECA0; + LUT4_L com_tlm_u_tlm_rx_vc0_fifo_N_9248_i ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_data_bqr_60_), + .I1(com_tlm_u_tlm_rx_vc0_fifo_data_oqr_60_), + .I2(com_tlm_u_tlm_rx_vc0_fifo_select_bq_3108), + .I3(com_tlm_u_tlm_rx_vc0_fifo_select_oq_3107), + .LO(com_tlm_u_tlm_rx_vc0_fifo_N_9248_i_3131) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_N_9249_i.INIT = 16'hECA0; + LUT4_L com_tlm_u_tlm_rx_vc0_fifo_N_9249_i ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_data_bqr_59_), + .I1(com_tlm_u_tlm_rx_vc0_fifo_data_oqr_59_), + .I2(com_tlm_u_tlm_rx_vc0_fifo_select_bq_3108), + .I3(com_tlm_u_tlm_rx_vc0_fifo_select_oq_3107), + .LO(com_tlm_u_tlm_rx_vc0_fifo_N_9249_i_3132) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_N_14338_i.INIT = 16'hECA0; + LUT4_L com_tlm_u_tlm_rx_vc0_fifo_N_14338_i ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_data_bqr_58_), + .I1(com_tlm_u_tlm_rx_vc0_fifo_data_oqr_58_), + .I2(com_tlm_u_tlm_rx_vc0_fifo_select_bq_3108), + .I3(com_tlm_u_tlm_rx_vc0_fifo_select_oq_3107), + .LO(com_tlm_u_tlm_rx_vc0_fifo_N_14338_i_3133) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_N_14339_i.INIT = 16'hECA0; + LUT4_L com_tlm_u_tlm_rx_vc0_fifo_N_14339_i ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_data_bqr_57_), + .I1(com_tlm_u_tlm_rx_vc0_fifo_data_oqr_57_), + .I2(com_tlm_u_tlm_rx_vc0_fifo_select_bq_3108), + .I3(com_tlm_u_tlm_rx_vc0_fifo_select_oq_3107), + .LO(com_tlm_u_tlm_rx_vc0_fifo_N_14339_i_3134) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_N_14340_i.INIT = 16'hECA0; + LUT4_L com_tlm_u_tlm_rx_vc0_fifo_N_14340_i ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_data_bqr_56_), + .I1(com_tlm_u_tlm_rx_vc0_fifo_data_oqr_56_), + .I2(com_tlm_u_tlm_rx_vc0_fifo_select_bq_3108), + .I3(com_tlm_u_tlm_rx_vc0_fifo_select_oq_3107), + .LO(com_tlm_u_tlm_rx_vc0_fifo_N_14340_i_3135) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_N_14341_i.INIT = 16'hECA0; + LUT4_L com_tlm_u_tlm_rx_vc0_fifo_N_14341_i ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_data_bqr_55_), + .I1(com_tlm_u_tlm_rx_vc0_fifo_data_oqr_55_), + .I2(com_tlm_u_tlm_rx_vc0_fifo_select_bq_3108), + .I3(com_tlm_u_tlm_rx_vc0_fifo_select_oq_3107), + .LO(com_tlm_u_tlm_rx_vc0_fifo_N_14341_i_3136) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_N_14342_i.INIT = 16'hECA0; + LUT4_L com_tlm_u_tlm_rx_vc0_fifo_N_14342_i ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_data_bqr_54_), + .I1(com_tlm_u_tlm_rx_vc0_fifo_data_oqr_54_), + .I2(com_tlm_u_tlm_rx_vc0_fifo_select_bq_3108), + .I3(com_tlm_u_tlm_rx_vc0_fifo_select_oq_3107), + .LO(com_tlm_u_tlm_rx_vc0_fifo_N_14342_i_3137) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_N_14343_i.INIT = 16'hECA0; + LUT4_L com_tlm_u_tlm_rx_vc0_fifo_N_14343_i ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_data_bqr_53_), + .I1(com_tlm_u_tlm_rx_vc0_fifo_data_oqr_53_), + .I2(com_tlm_u_tlm_rx_vc0_fifo_select_bq_3108), + .I3(com_tlm_u_tlm_rx_vc0_fifo_select_oq_3107), + .LO(com_tlm_u_tlm_rx_vc0_fifo_N_14343_i_3138) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_N_14344_i.INIT = 16'hECA0; + LUT4_L com_tlm_u_tlm_rx_vc0_fifo_N_14344_i ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_data_bqr_52_), + .I1(com_tlm_u_tlm_rx_vc0_fifo_data_oqr_52_), + .I2(com_tlm_u_tlm_rx_vc0_fifo_select_bq_3108), + .I3(com_tlm_u_tlm_rx_vc0_fifo_select_oq_3107), + .LO(com_tlm_u_tlm_rx_vc0_fifo_N_14344_i_3139) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_N_14345_i.INIT = 16'hECA0; + LUT4_L com_tlm_u_tlm_rx_vc0_fifo_N_14345_i ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_data_bqr_51_), + .I1(com_tlm_u_tlm_rx_vc0_fifo_data_oqr_51_), + .I2(com_tlm_u_tlm_rx_vc0_fifo_select_bq_3108), + .I3(com_tlm_u_tlm_rx_vc0_fifo_select_oq_3107), + .LO(com_tlm_u_tlm_rx_vc0_fifo_N_14345_i_3140) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_N_14346_i.INIT = 16'hECA0; + LUT4_L com_tlm_u_tlm_rx_vc0_fifo_N_14346_i ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_data_bqr_50_), + .I1(com_tlm_u_tlm_rx_vc0_fifo_data_oqr_50_), + .I2(com_tlm_u_tlm_rx_vc0_fifo_select_bq_3108), + .I3(com_tlm_u_tlm_rx_vc0_fifo_select_oq_3107), + .LO(com_tlm_u_tlm_rx_vc0_fifo_N_14346_i_3141) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_N_14347_i.INIT = 16'hECA0; + LUT4_L com_tlm_u_tlm_rx_vc0_fifo_N_14347_i ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_data_bqr_49_), + .I1(com_tlm_u_tlm_rx_vc0_fifo_data_oqr_49_), + .I2(com_tlm_u_tlm_rx_vc0_fifo_select_bq_3108), + .I3(com_tlm_u_tlm_rx_vc0_fifo_select_oq_3107), + .LO(com_tlm_u_tlm_rx_vc0_fifo_N_14347_i_3142) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_N_14348_i.INIT = 16'hECA0; + LUT4_L com_tlm_u_tlm_rx_vc0_fifo_N_14348_i ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_data_bqr_48_), + .I1(com_tlm_u_tlm_rx_vc0_fifo_data_oqr_48_), + .I2(com_tlm_u_tlm_rx_vc0_fifo_select_bq_3108), + .I3(com_tlm_u_tlm_rx_vc0_fifo_select_oq_3107), + .LO(com_tlm_u_tlm_rx_vc0_fifo_N_14348_i_3143) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_N_14379_i.INIT = 16'hECA0; + LUT4_L com_tlm_u_tlm_rx_vc0_fifo_N_14379_i ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_data_bqr_47_), + .I1(com_tlm_u_tlm_rx_vc0_fifo_data_oqr_47_), + .I2(com_tlm_u_tlm_rx_vc0_fifo_select_bq_3108), + .I3(com_tlm_u_tlm_rx_vc0_fifo_select_oq_3107), + .LO(com_tlm_u_tlm_rx_vc0_fifo_N_14379_i_3144) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_N_9262_i.INIT = 16'hECA0; + LUT4_L com_tlm_u_tlm_rx_vc0_fifo_N_9262_i ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_data_bqr_45_), + .I1(com_tlm_u_tlm_rx_vc0_fifo_data_oqr_45_), + .I2(com_tlm_u_tlm_rx_vc0_fifo_select_bq_3108), + .I3(com_tlm_u_tlm_rx_vc0_fifo_select_oq_3107), + .LO(com_tlm_u_tlm_rx_vc0_fifo_N_9262_i_3146) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_N_9263_i.INIT = 16'hECA0; + LUT4_L com_tlm_u_tlm_rx_vc0_fifo_N_9263_i ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_data_bqr_44_), + .I1(com_tlm_u_tlm_rx_vc0_fifo_data_oqr_44_), + .I2(com_tlm_u_tlm_rx_vc0_fifo_select_bq_3108), + .I3(com_tlm_u_tlm_rx_vc0_fifo_select_oq_3107), + .LO(com_tlm_u_tlm_rx_vc0_fifo_N_9263_i_3147) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_N_9264_i.INIT = 16'hECA0; + LUT4_L com_tlm_u_tlm_rx_vc0_fifo_N_9264_i ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_data_bqr_43_), + .I1(com_tlm_u_tlm_rx_vc0_fifo_data_oqr_43_), + .I2(com_tlm_u_tlm_rx_vc0_fifo_select_bq_3108), + .I3(com_tlm_u_tlm_rx_vc0_fifo_select_oq_3107), + .LO(com_tlm_u_tlm_rx_vc0_fifo_N_9264_i_3148) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_N_9265_i.INIT = 16'hECA0; + LUT4_L com_tlm_u_tlm_rx_vc0_fifo_N_9265_i ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_data_bqr_42_), + .I1(com_tlm_u_tlm_rx_vc0_fifo_data_oqr_42_), + .I2(com_tlm_u_tlm_rx_vc0_fifo_select_bq_3108), + .I3(com_tlm_u_tlm_rx_vc0_fifo_select_oq_3107), + .LO(com_tlm_u_tlm_rx_vc0_fifo_N_9265_i_3149) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_N_9266_i.INIT = 16'hECA0; + LUT4_L com_tlm_u_tlm_rx_vc0_fifo_N_9266_i ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_data_bqr_41_), + .I1(com_tlm_u_tlm_rx_vc0_fifo_data_oqr_41_), + .I2(com_tlm_u_tlm_rx_vc0_fifo_select_bq_3108), + .I3(com_tlm_u_tlm_rx_vc0_fifo_select_oq_3107), + .LO(com_tlm_u_tlm_rx_vc0_fifo_N_9266_i_3150) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_N_9267_i.INIT = 16'hECA0; + LUT4_L com_tlm_u_tlm_rx_vc0_fifo_N_9267_i ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_data_bqr_40_), + .I1(com_tlm_u_tlm_rx_vc0_fifo_data_oqr_40_), + .I2(com_tlm_u_tlm_rx_vc0_fifo_select_bq_3108), + .I3(com_tlm_u_tlm_rx_vc0_fifo_select_oq_3107), + .LO(com_tlm_u_tlm_rx_vc0_fifo_N_9267_i_3151) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_N_9268_i.INIT = 16'hECA0; + LUT4_L com_tlm_u_tlm_rx_vc0_fifo_N_9268_i ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_data_bqr_39_), + .I1(com_tlm_u_tlm_rx_vc0_fifo_data_oqr_39_), + .I2(com_tlm_u_tlm_rx_vc0_fifo_select_bq_3108), + .I3(com_tlm_u_tlm_rx_vc0_fifo_select_oq_3107), + .LO(com_tlm_u_tlm_rx_vc0_fifo_N_9268_i_3152) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_N_9269_i.INIT = 16'hECA0; + LUT4_L com_tlm_u_tlm_rx_vc0_fifo_N_9269_i ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_data_bqr_38_), + .I1(com_tlm_u_tlm_rx_vc0_fifo_data_oqr_38_), + .I2(com_tlm_u_tlm_rx_vc0_fifo_select_bq_3108), + .I3(com_tlm_u_tlm_rx_vc0_fifo_select_oq_3107), + .LO(com_tlm_u_tlm_rx_vc0_fifo_N_9269_i_3153) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_N_9270_i.INIT = 16'hECA0; + LUT4_L com_tlm_u_tlm_rx_vc0_fifo_N_9270_i ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_data_bqr_37_), + .I1(com_tlm_u_tlm_rx_vc0_fifo_data_oqr_37_), + .I2(com_tlm_u_tlm_rx_vc0_fifo_select_bq_3108), + .I3(com_tlm_u_tlm_rx_vc0_fifo_select_oq_3107), + .LO(com_tlm_u_tlm_rx_vc0_fifo_N_9270_i_3154) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_N_9271_i.INIT = 16'hECA0; + LUT4_L com_tlm_u_tlm_rx_vc0_fifo_N_9271_i ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_data_bqr_36_), + .I1(com_tlm_u_tlm_rx_vc0_fifo_data_oqr_36_), + .I2(com_tlm_u_tlm_rx_vc0_fifo_select_bq_3108), + .I3(com_tlm_u_tlm_rx_vc0_fifo_select_oq_3107), + .LO(com_tlm_u_tlm_rx_vc0_fifo_N_9271_i_3155) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_N_9272_i.INIT = 16'hECA0; + LUT4_L com_tlm_u_tlm_rx_vc0_fifo_N_9272_i ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_data_bqr_35_), + .I1(com_tlm_u_tlm_rx_vc0_fifo_data_oqr_35_), + .I2(com_tlm_u_tlm_rx_vc0_fifo_select_bq_3108), + .I3(com_tlm_u_tlm_rx_vc0_fifo_select_oq_3107), + .LO(com_tlm_u_tlm_rx_vc0_fifo_N_9272_i_3156) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_N_9273_i.INIT = 16'hECA0; + LUT4_L com_tlm_u_tlm_rx_vc0_fifo_N_9273_i ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_data_bqr_34_), + .I1(com_tlm_u_tlm_rx_vc0_fifo_data_oqr_34_), + .I2(com_tlm_u_tlm_rx_vc0_fifo_select_bq_3108), + .I3(com_tlm_u_tlm_rx_vc0_fifo_select_oq_3107), + .LO(com_tlm_u_tlm_rx_vc0_fifo_N_9273_i_3157) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_N_9274_i.INIT = 16'hECA0; + LUT4_L com_tlm_u_tlm_rx_vc0_fifo_N_9274_i ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_data_bqr_33_), + .I1(com_tlm_u_tlm_rx_vc0_fifo_data_oqr_33_), + .I2(com_tlm_u_tlm_rx_vc0_fifo_select_bq_3108), + .I3(com_tlm_u_tlm_rx_vc0_fifo_select_oq_3107), + .LO(com_tlm_u_tlm_rx_vc0_fifo_N_9274_i_3158) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_N_9275_i.INIT = 16'hECA0; + LUT4_L com_tlm_u_tlm_rx_vc0_fifo_N_9275_i ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_data_bqr_32_), + .I1(com_tlm_u_tlm_rx_vc0_fifo_data_oqr_32_), + .I2(com_tlm_u_tlm_rx_vc0_fifo_select_bq_3108), + .I3(com_tlm_u_tlm_rx_vc0_fifo_select_oq_3107), + .LO(com_tlm_u_tlm_rx_vc0_fifo_N_9275_i_3159) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_N_9276_i.INIT = 16'hECA0; + LUT4_L com_tlm_u_tlm_rx_vc0_fifo_N_9276_i ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_data_bqr_31_), + .I1(com_tlm_u_tlm_rx_vc0_fifo_data_oqr_31_), + .I2(com_tlm_u_tlm_rx_vc0_fifo_select_bq_3108), + .I3(com_tlm_u_tlm_rx_vc0_fifo_select_oq_3107), + .LO(com_tlm_u_tlm_rx_vc0_fifo_N_9276_i_3160) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_N_9277_i.INIT = 16'hECA0; + LUT4_L com_tlm_u_tlm_rx_vc0_fifo_N_9277_i ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_data_bqr_30_), + .I1(com_tlm_u_tlm_rx_vc0_fifo_data_oqr_30_), + .I2(com_tlm_u_tlm_rx_vc0_fifo_select_bq_3108), + .I3(com_tlm_u_tlm_rx_vc0_fifo_select_oq_3107), + .LO(com_tlm_u_tlm_rx_vc0_fifo_N_9277_i_3161) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_N_9278_i.INIT = 16'hECA0; + LUT4_L com_tlm_u_tlm_rx_vc0_fifo_N_9278_i ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_data_bqr_29_), + .I1(com_tlm_u_tlm_rx_vc0_fifo_data_oqr_29_), + .I2(com_tlm_u_tlm_rx_vc0_fifo_select_bq_3108), + .I3(com_tlm_u_tlm_rx_vc0_fifo_select_oq_3107), + .LO(com_tlm_u_tlm_rx_vc0_fifo_N_9278_i_3162) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_N_9279_i.INIT = 16'hECA0; + LUT4_L com_tlm_u_tlm_rx_vc0_fifo_N_9279_i ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_data_bqr_28_), + .I1(com_tlm_u_tlm_rx_vc0_fifo_data_oqr_28_), + .I2(com_tlm_u_tlm_rx_vc0_fifo_select_bq_3108), + .I3(com_tlm_u_tlm_rx_vc0_fifo_select_oq_3107), + .LO(com_tlm_u_tlm_rx_vc0_fifo_N_9279_i_3163) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_N_9280_i.INIT = 16'hECA0; + LUT4_L com_tlm_u_tlm_rx_vc0_fifo_N_9280_i ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_data_bqr_27_), + .I1(com_tlm_u_tlm_rx_vc0_fifo_data_oqr_27_), + .I2(com_tlm_u_tlm_rx_vc0_fifo_select_bq_3108), + .I3(com_tlm_u_tlm_rx_vc0_fifo_select_oq_3107), + .LO(com_tlm_u_tlm_rx_vc0_fifo_N_9280_i_3164) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_N_9281_i.INIT = 16'hECA0; + LUT4_L com_tlm_u_tlm_rx_vc0_fifo_N_9281_i ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_data_bqr_26_), + .I1(com_tlm_u_tlm_rx_vc0_fifo_data_oqr_26_), + .I2(com_tlm_u_tlm_rx_vc0_fifo_select_bq_3108), + .I3(com_tlm_u_tlm_rx_vc0_fifo_select_oq_3107), + .LO(com_tlm_u_tlm_rx_vc0_fifo_N_9281_i_3165) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_N_9282_i.INIT = 16'hECA0; + LUT4_L com_tlm_u_tlm_rx_vc0_fifo_N_9282_i ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_data_bqr_25_), + .I1(com_tlm_u_tlm_rx_vc0_fifo_data_oqr_25_), + .I2(com_tlm_u_tlm_rx_vc0_fifo_select_bq_3108), + .I3(com_tlm_u_tlm_rx_vc0_fifo_select_oq_3107), + .LO(com_tlm_u_tlm_rx_vc0_fifo_N_9282_i_3166) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_N_9283_i.INIT = 16'hECA0; + LUT4_L com_tlm_u_tlm_rx_vc0_fifo_N_9283_i ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_data_bqr_24_), + .I1(com_tlm_u_tlm_rx_vc0_fifo_data_oqr_24_), + .I2(com_tlm_u_tlm_rx_vc0_fifo_select_bq_3108), + .I3(com_tlm_u_tlm_rx_vc0_fifo_select_oq_3107), + .LO(com_tlm_u_tlm_rx_vc0_fifo_N_9283_i_3167) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_N_14349_i.INIT = 16'hECA0; + LUT4_L com_tlm_u_tlm_rx_vc0_fifo_N_14349_i ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_data_bqr_23_), + .I1(com_tlm_u_tlm_rx_vc0_fifo_data_oqr_23_), + .I2(com_tlm_u_tlm_rx_vc0_fifo_select_bq_3108), + .I3(com_tlm_u_tlm_rx_vc0_fifo_select_oq_3107), + .LO(com_tlm_u_tlm_rx_vc0_fifo_N_14349_i_3168) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_N_14350_i.INIT = 16'hECA0; + LUT4_L com_tlm_u_tlm_rx_vc0_fifo_N_14350_i ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_data_bqr_22_), + .I1(com_tlm_u_tlm_rx_vc0_fifo_data_oqr_22_), + .I2(com_tlm_u_tlm_rx_vc0_fifo_select_bq_3108), + .I3(com_tlm_u_tlm_rx_vc0_fifo_select_oq_3107), + .LO(com_tlm_u_tlm_rx_vc0_fifo_N_14350_i_3169) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_N_14351_i.INIT = 16'hECA0; + LUT4_L com_tlm_u_tlm_rx_vc0_fifo_N_14351_i ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_data_bqr_21_), + .I1(com_tlm_u_tlm_rx_vc0_fifo_data_oqr_21_), + .I2(com_tlm_u_tlm_rx_vc0_fifo_select_bq_3108), + .I3(com_tlm_u_tlm_rx_vc0_fifo_select_oq_3107), + .LO(com_tlm_u_tlm_rx_vc0_fifo_N_14351_i_3170) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_N_14352_i.INIT = 16'hECA0; + LUT4_L com_tlm_u_tlm_rx_vc0_fifo_N_14352_i ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_data_bqr_20_), + .I1(com_tlm_u_tlm_rx_vc0_fifo_data_oqr_20_), + .I2(com_tlm_u_tlm_rx_vc0_fifo_select_bq_3108), + .I3(com_tlm_u_tlm_rx_vc0_fifo_select_oq_3107), + .LO(com_tlm_u_tlm_rx_vc0_fifo_N_14352_i_3171) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_N_14353_i.INIT = 16'hECA0; + LUT4_L com_tlm_u_tlm_rx_vc0_fifo_N_14353_i ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_data_bqr_19_), + .I1(com_tlm_u_tlm_rx_vc0_fifo_data_oqr_19_), + .I2(com_tlm_u_tlm_rx_vc0_fifo_select_bq_3108), + .I3(com_tlm_u_tlm_rx_vc0_fifo_select_oq_3107), + .LO(com_tlm_u_tlm_rx_vc0_fifo_N_14353_i_3172) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_N_14354_i.INIT = 16'hECA0; + LUT4_L com_tlm_u_tlm_rx_vc0_fifo_N_14354_i ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_data_bqr_18_), + .I1(com_tlm_u_tlm_rx_vc0_fifo_data_oqr_18_), + .I2(com_tlm_u_tlm_rx_vc0_fifo_select_bq_3108), + .I3(com_tlm_u_tlm_rx_vc0_fifo_select_oq_3107), + .LO(com_tlm_u_tlm_rx_vc0_fifo_N_14354_i_3173) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_N_14355_i.INIT = 16'hECA0; + LUT4_L com_tlm_u_tlm_rx_vc0_fifo_N_14355_i ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_data_bqr_17_), + .I1(com_tlm_u_tlm_rx_vc0_fifo_data_oqr_17_), + .I2(com_tlm_u_tlm_rx_vc0_fifo_select_bq_3108), + .I3(com_tlm_u_tlm_rx_vc0_fifo_select_oq_3107), + .LO(com_tlm_u_tlm_rx_vc0_fifo_N_14355_i_3174) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_N_14356_i.INIT = 16'hECA0; + LUT4_L com_tlm_u_tlm_rx_vc0_fifo_N_14356_i ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_data_bqr_16_), + .I1(com_tlm_u_tlm_rx_vc0_fifo_data_oqr_16_), + .I2(com_tlm_u_tlm_rx_vc0_fifo_select_bq_3108), + .I3(com_tlm_u_tlm_rx_vc0_fifo_select_oq_3107), + .LO(com_tlm_u_tlm_rx_vc0_fifo_N_14356_i_3175) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_N_14357_i.INIT = 16'hECA0; + LUT4_L com_tlm_u_tlm_rx_vc0_fifo_N_14357_i ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_data_bqr_15_), + .I1(com_tlm_u_tlm_rx_vc0_fifo_data_oqr_15_), + .I2(com_tlm_u_tlm_rx_vc0_fifo_select_bq_3108), + .I3(com_tlm_u_tlm_rx_vc0_fifo_select_oq_3107), + .LO(com_tlm_u_tlm_rx_vc0_fifo_N_14357_i_3176) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_N_14358_i.INIT = 16'hECA0; + LUT4_L com_tlm_u_tlm_rx_vc0_fifo_N_14358_i ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_data_bqr_14_), + .I1(com_tlm_u_tlm_rx_vc0_fifo_data_oqr_14_), + .I2(com_tlm_u_tlm_rx_vc0_fifo_select_bq_3108), + .I3(com_tlm_u_tlm_rx_vc0_fifo_select_oq_3107), + .LO(com_tlm_u_tlm_rx_vc0_fifo_N_14358_i_3177) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_N_14359_i.INIT = 16'hECA0; + LUT4_L com_tlm_u_tlm_rx_vc0_fifo_N_14359_i ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_data_bqr_13_), + .I1(com_tlm_u_tlm_rx_vc0_fifo_data_oqr_13_), + .I2(com_tlm_u_tlm_rx_vc0_fifo_select_bq_3108), + .I3(com_tlm_u_tlm_rx_vc0_fifo_select_oq_3107), + .LO(com_tlm_u_tlm_rx_vc0_fifo_N_14359_i_3178) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_N_14360_i.INIT = 16'hECA0; + LUT4_L com_tlm_u_tlm_rx_vc0_fifo_N_14360_i ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_data_bqr_12_), + .I1(com_tlm_u_tlm_rx_vc0_fifo_data_oqr_12_), + .I2(com_tlm_u_tlm_rx_vc0_fifo_select_bq_3108), + .I3(com_tlm_u_tlm_rx_vc0_fifo_select_oq_3107), + .LO(com_tlm_u_tlm_rx_vc0_fifo_N_14360_i_3179) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_N_14361_i.INIT = 16'hECA0; + LUT4_L com_tlm_u_tlm_rx_vc0_fifo_N_14361_i ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_data_bqr_11_), + .I1(com_tlm_u_tlm_rx_vc0_fifo_data_oqr_11_), + .I2(com_tlm_u_tlm_rx_vc0_fifo_select_bq_3108), + .I3(com_tlm_u_tlm_rx_vc0_fifo_select_oq_3107), + .LO(com_tlm_u_tlm_rx_vc0_fifo_N_14361_i_3180) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_N_14362_i.INIT = 16'hECA0; + LUT4_L com_tlm_u_tlm_rx_vc0_fifo_N_14362_i ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_data_bqr_10_), + .I1(com_tlm_u_tlm_rx_vc0_fifo_data_oqr_10_), + .I2(com_tlm_u_tlm_rx_vc0_fifo_select_bq_3108), + .I3(com_tlm_u_tlm_rx_vc0_fifo_select_oq_3107), + .LO(com_tlm_u_tlm_rx_vc0_fifo_N_14362_i_3181) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_N_14363_i.INIT = 16'hECA0; + LUT4_L com_tlm_u_tlm_rx_vc0_fifo_N_14363_i ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_data_bqr_9_), + .I1(com_tlm_u_tlm_rx_vc0_fifo_data_oqr_9_), + .I2(com_tlm_u_tlm_rx_vc0_fifo_select_bq_3108), + .I3(com_tlm_u_tlm_rx_vc0_fifo_select_oq_3107), + .LO(com_tlm_u_tlm_rx_vc0_fifo_N_14363_i_3182) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_N_14364_i.INIT = 16'hECA0; + LUT4_L com_tlm_u_tlm_rx_vc0_fifo_N_14364_i ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_data_bqr_8_), + .I1(com_tlm_u_tlm_rx_vc0_fifo_data_oqr_8_), + .I2(com_tlm_u_tlm_rx_vc0_fifo_select_bq_3108), + .I3(com_tlm_u_tlm_rx_vc0_fifo_select_oq_3107), + .LO(com_tlm_u_tlm_rx_vc0_fifo_N_14364_i_3183) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_N_14365_i.INIT = 16'hECA0; + LUT4_L com_tlm_u_tlm_rx_vc0_fifo_N_14365_i ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_data_bqr_7_), + .I1(com_tlm_u_tlm_rx_vc0_fifo_data_oqr_7_), + .I2(com_tlm_u_tlm_rx_vc0_fifo_select_bq_3108), + .I3(com_tlm_u_tlm_rx_vc0_fifo_select_oq_3107), + .LO(com_tlm_u_tlm_rx_vc0_fifo_N_14365_i_3184) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_N_14366_i.INIT = 16'hECA0; + LUT4_L com_tlm_u_tlm_rx_vc0_fifo_N_14366_i ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_data_bqr_6_), + .I1(com_tlm_u_tlm_rx_vc0_fifo_data_oqr_6_), + .I2(com_tlm_u_tlm_rx_vc0_fifo_select_bq_3108), + .I3(com_tlm_u_tlm_rx_vc0_fifo_select_oq_3107), + .LO(com_tlm_u_tlm_rx_vc0_fifo_N_14366_i_3185) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_N_14367_i.INIT = 16'hECA0; + LUT4_L com_tlm_u_tlm_rx_vc0_fifo_N_14367_i ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_data_bqr_5_), + .I1(com_tlm_u_tlm_rx_vc0_fifo_data_oqr_5_), + .I2(com_tlm_u_tlm_rx_vc0_fifo_select_bq_3108), + .I3(com_tlm_u_tlm_rx_vc0_fifo_select_oq_3107), + .LO(com_tlm_u_tlm_rx_vc0_fifo_N_14367_i_3186) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_N_14368_i.INIT = 16'hECA0; + LUT4_L com_tlm_u_tlm_rx_vc0_fifo_N_14368_i ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_data_bqr_4_), + .I1(com_tlm_u_tlm_rx_vc0_fifo_data_oqr_4_), + .I2(com_tlm_u_tlm_rx_vc0_fifo_select_bq_3108), + .I3(com_tlm_u_tlm_rx_vc0_fifo_select_oq_3107), + .LO(com_tlm_u_tlm_rx_vc0_fifo_N_14368_i_3187) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_N_14369_i.INIT = 16'hECA0; + LUT4_L com_tlm_u_tlm_rx_vc0_fifo_N_14369_i ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_data_bqr_3_), + .I1(com_tlm_u_tlm_rx_vc0_fifo_data_oqr_3_), + .I2(com_tlm_u_tlm_rx_vc0_fifo_select_bq_3108), + .I3(com_tlm_u_tlm_rx_vc0_fifo_select_oq_3107), + .LO(com_tlm_u_tlm_rx_vc0_fifo_N_14369_i_3188) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_N_14370_i.INIT = 16'hECA0; + LUT4_L com_tlm_u_tlm_rx_vc0_fifo_N_14370_i ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_data_bqr_2_), + .I1(com_tlm_u_tlm_rx_vc0_fifo_data_oqr_2_), + .I2(com_tlm_u_tlm_rx_vc0_fifo_select_bq_3108), + .I3(com_tlm_u_tlm_rx_vc0_fifo_select_oq_3107), + .LO(com_tlm_u_tlm_rx_vc0_fifo_N_14370_i_3189) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_N_14371_i.INIT = 16'hECA0; + LUT4_L com_tlm_u_tlm_rx_vc0_fifo_N_14371_i ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_data_bqr_1_), + .I1(com_tlm_u_tlm_rx_vc0_fifo_data_oqr_1_), + .I2(com_tlm_u_tlm_rx_vc0_fifo_select_bq_3108), + .I3(com_tlm_u_tlm_rx_vc0_fifo_select_oq_3107), + .LO(com_tlm_u_tlm_rx_vc0_fifo_N_14371_i_3190) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_N_14372_i.INIT = 16'hECA0; + LUT4_L com_tlm_u_tlm_rx_vc0_fifo_N_14372_i ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_data_bqr_0_), + .I1(com_tlm_u_tlm_rx_vc0_fifo_data_oqr_0_), + .I2(com_tlm_u_tlm_rx_vc0_fifo_select_bq_3108), + .I3(com_tlm_u_tlm_rx_vc0_fifo_select_oq_3107), + .LO(com_tlm_u_tlm_rx_vc0_fifo_N_14372_i_3191) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_select_oq2bq_d_5.INIT = 8'h20; + LUT3_L com_tlm_u_tlm_rx_vc0_fifo_select_oq2bq_d_5 ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_np_oqr), + .I1(com_tlm_u_tlm_rx_vc0_fifo_select_oq2bq_d_3110), + .I2(com_tlm_u_tlm_rx_vc0_fifo_un1_data_oqr[0]), + .LO(com_tlm_u_tlm_rx_vc0_fifo_select_oq2bq_d_5_3109) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_select_bq17.INIT = 4'h4; + LUT2_L com_tlm_u_tlm_rx_vc0_fifo_select_bq17 ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_adv_pkt_bq_3113), + .I1(com_tlm_u_tlm_rx_vc0_fifo_un1_adv_pkt_oq_3112), + .LO(com_tlm_u_tlm_rx_vc0_fifo_select_bq17_3111) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_select_cfg_7_u_0.INIT = 16'hD888; + LUT4_L com_tlm_u_tlm_rx_vc0_fifo_select_cfg_7_u_0 ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_adv_pkt_bq_3113), + .I1(com_tlm_u_tlm_rx_vc0_fifo_aux_bqr[7]), + .I2(com_tlm_u_tlm_rx_vc0_fifo_cfg_oqr), + .I3(com_tlm_u_tlm_rx_vc0_fifo_un1_adv_pkt_oq_3112), + .LO(com_tlm_u_tlm_rx_vc0_fifo_select_cfg_7) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_select_usr_7_u_0.INIT = 16'h2722; + LUT4_L com_tlm_u_tlm_rx_vc0_fifo_select_usr_7_u_0 ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_adv_pkt_bq_3113), + .I1(com_tlm_u_tlm_rx_vc0_fifo_aux_bqr[7]), + .I2(com_tlm_u_tlm_rx_vc0_fifo_cfg_oqr), + .I3(com_tlm_u_tlm_rx_vc0_fifo_un1_adv_pkt_oq_3112), + .LO(com_tlm_u_tlm_rx_vc0_fifo_select_usr_7) + ); + FDRE com_tlm_u_tlm_rx_vc0_fifo_select_oq2bq_1 ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_un1_select_oq2bq_d_1_i_3114), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_select_oq2bq_5), + .Q(com_tlm_u_tlm_rx_vc0_fifo_select_oq2bq_1_3115), + .R(plm_link_up_i) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_wen_aux_bq.INIT = 8'h80; + LUT3 com_tlm_u_tlm_rx_vc0_fifo_wen_aux_bq ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_select_oq2bq_3117), + .I1(com_tlm_u_tlm_rx_vc0_fifo_ram_dout[64]), + .I2(com_tlm_u_tlm_rx_vc0_fifo_data_vld_oqr), + .O(com_tlm_u_tlm_rx_vc0_fifo_wen_aux_bq_3116) + ); + FD com_tlm_u_tlm_rx_vc0_fifo_reset_i_q ( + .C(NlwRenamedSig_OI_trn_clk), + .D(plm_link_up_0), + .Q(com_reset_i_q) + ); + FD com_tlm_u_tlm_rx_vc0_fifo_aux_in_1_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_aux_i_d[1]), + .Q(com_tlm_u_tlm_rx_vc0_fifo_aux_in[1]) + ); + FD com_tlm_u_tlm_rx_vc0_fifo_aux_in_0_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_aux_i_d[0]), + .Q(com_tlm_u_tlm_rx_vc0_fifo_aux_in[0]) + ); + FD com_tlm_u_tlm_rx_vc0_fifo_aux_in_8_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_aux_i_d[8]), + .Q(com_tlm_u_tlm_rx_vc0_fifo_aux_in[8]) + ); + FD com_tlm_u_tlm_rx_vc0_fifo_aux_in_7_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_aux_i_d[7]), + .Q(com_tlm_u_tlm_rx_vc0_fifo_aux_in[7]) + ); + FD com_tlm_u_tlm_rx_vc0_fifo_aux_in_6_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_aux_i_d[6]), + .Q(com_tlm_u_tlm_rx_vc0_fifo_aux_in[6]) + ); + FD com_tlm_u_tlm_rx_vc0_fifo_aux_in_5_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_aux_i_d[5]), + .Q(com_tlm_u_tlm_rx_vc0_fifo_aux_in[5]) + ); + FD com_tlm_u_tlm_rx_vc0_fifo_aux_in_4_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_aux_i_d[4]), + .Q(com_tlm_u_tlm_rx_vc0_fifo_aux_in[4]) + ); + FD com_tlm_u_tlm_rx_vc0_fifo_aux_in_3_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_aux_i_d[3]), + .Q(com_tlm_u_tlm_rx_vc0_fifo_aux_in[3]) + ); + FD com_tlm_u_tlm_rx_vc0_fifo_aux_in_2_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_aux_i_d[2]), + .Q(com_tlm_u_tlm_rx_vc0_fifo_aux_in[2]) + ); + FDE com_tlm_u_tlm_rx_vc0_fifo_aux_i_d_6_ ( + .CE(com_tlm_u_tlm_rx_ds_bar_src_rdy), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_ds_bar[6]), + .Q(com_tlm_u_tlm_rx_vc0_fifo_aux_i_d[6]) + ); + FDE com_tlm_u_tlm_rx_vc0_fifo_aux_i_d_5_ ( + .CE(com_tlm_u_tlm_rx_ds_bar_src_rdy), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_ds_bar[5]), + .Q(com_tlm_u_tlm_rx_vc0_fifo_aux_i_d[5]) + ); + FDE com_tlm_u_tlm_rx_vc0_fifo_aux_i_d_4_ ( + .CE(com_tlm_u_tlm_rx_ds_bar_src_rdy), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_ds_bar[4]), + .Q(com_tlm_u_tlm_rx_vc0_fifo_aux_i_d[4]) + ); + FDE com_tlm_u_tlm_rx_vc0_fifo_aux_i_d_3_ ( + .CE(com_tlm_u_tlm_rx_ds_bar_src_rdy), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_ds_bar[3]), + .Q(com_tlm_u_tlm_rx_vc0_fifo_aux_i_d[3]) + ); + FDE com_tlm_u_tlm_rx_vc0_fifo_aux_i_d_2_ ( + .CE(com_tlm_u_tlm_rx_ds_bar_src_rdy), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_ds_bar[2]), + .Q(com_tlm_u_tlm_rx_vc0_fifo_aux_i_d[2]) + ); + FDE com_tlm_u_tlm_rx_vc0_fifo_aux_i_d_1_ ( + .CE(com_tlm_u_tlm_rx_ds_bar_src_rdy), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_ds_bar[1]), + .Q(com_tlm_u_tlm_rx_vc0_fifo_aux_i_d[1]) + ); + FDE com_tlm_u_tlm_rx_vc0_fifo_aux_i_d_0_ ( + .CE(com_tlm_u_tlm_rx_ds_bar_src_rdy), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_ds_bar[0]), + .Q(com_tlm_u_tlm_rx_vc0_fifo_aux_i_d[0]) + ); + FDE com_tlm_u_tlm_rx_vc0_fifo_aux_i_d_8_ ( + .CE(com_tlm_u_tlm_rx_ds_sof), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_ds_np), + .Q(com_tlm_u_tlm_rx_vc0_fifo_aux_i_d[8]) + ); + FDE com_tlm_u_tlm_rx_vc0_fifo_aux_i_d_7_ ( + .CE(com_tlm_u_tlm_rx_ds_sof), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_ds_cfg), + .Q(com_tlm_u_tlm_rx_vc0_fifo_aux_i_d[7]) + ); + FDE com_tlm_u_tlm_rx_vc0_fifo_rem_d ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_N_68339_i_3192), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_N_9523_i), + .Q(com_tlm_u_tlm_rx_vc0_trn_rrem) + ); + FDE com_tlm_u_tlm_rx_vc0_fifo_bar_d_6_ ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_N_68338_i_3126), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_N_9308_i_3118), + .Q(com_tlm_u_tlm_rx_vc0_fifo_trn_rbar_hit[6]) + ); + FDE com_tlm_u_tlm_rx_vc0_fifo_bar_d_5_ ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_N_68338_i_3126), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_N_9309_i_3119), + .Q(com_tlm_u_tlm_rx_vc0_fifo_trn_rbar_hit[5]) + ); + FDE com_tlm_u_tlm_rx_vc0_fifo_bar_d_4_ ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_N_68338_i_3126), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_N_9310_i_3120), + .Q(com_tlm_u_tlm_rx_vc0_fifo_trn_rbar_hit[4]) + ); + FDE com_tlm_u_tlm_rx_vc0_fifo_bar_d_3_ ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_N_68338_i_3126), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_N_9311_i_3121), + .Q(com_tlm_u_tlm_rx_vc0_fifo_trn_rbar_hit[3]) + ); + FDE com_tlm_u_tlm_rx_vc0_fifo_bar_d_2_ ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_N_68338_i_3126), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_N_9312_i_3122), + .Q(com_tlm_u_tlm_rx_vc0_fifo_trn_rbar_hit[2]) + ); + FDE com_tlm_u_tlm_rx_vc0_fifo_bar_d_1_ ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_N_68338_i_3126), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_N_9313_i_3123), + .Q(com_tlm_u_tlm_rx_vc0_fifo_trn_rbar_hit[1]) + ); + FDE com_tlm_u_tlm_rx_vc0_fifo_bar_d_0_ ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_N_68338_i_3126), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_N_9314_i_3124), + .Q(com_tlm_u_tlm_rx_vc0_fifo_trn_rbar_hit[0]) + ); + FDE com_tlm_u_tlm_rx_vc0_fifo_cpl_d ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_N_68338_i_3126), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_un8_cpl_d_3125), + .Q(com_tlm_u_tlm_rx_vc0_fifo_cpl) + ); + FDE com_tlm_u_tlm_rx_vc0_fifo_ep_d ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_N_68338_i_3126), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_N_14376_i_3145), + .Q(com_tlm_u_tlm_rx_vc0_fifo_trn_rerrfwd) + ); + FDE com_tlm_u_tlm_rx_vc0_fifo_np_d ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_N_68338_i_3126), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_N_9520_i_3127), + .Q(com_tlm_u_tlm_rx_vc0_fifo_np) + ); + FDE com_tlm_u_tlm_rx_vc0_fifo_d_d_63_ ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_N_68339_i_3192), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_N_9245_i_3128), + .Q(NlwRenamedSig_OI_trn_rd[63]) + ); + FDE com_tlm_u_tlm_rx_vc0_fifo_d_d_62_ ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_N_68339_i_3192), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_N_9246_i_3129), + .Q(NlwRenamedSig_OI_trn_rd[62]) + ); + FDE com_tlm_u_tlm_rx_vc0_fifo_d_d_61_ ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_N_68339_i_3192), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_N_9247_i_3130), + .Q(NlwRenamedSig_OI_trn_rd[61]) + ); + FDE com_tlm_u_tlm_rx_vc0_fifo_d_d_60_ ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_N_68339_i_3192), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_N_9248_i_3131), + .Q(NlwRenamedSig_OI_trn_rd[60]) + ); + FDE com_tlm_u_tlm_rx_vc0_fifo_d_d_59_ ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_N_68339_i_3192), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_N_9249_i_3132), + .Q(NlwRenamedSig_OI_trn_rd[59]) + ); + FDE com_tlm_u_tlm_rx_vc0_fifo_d_d_58_ ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_N_68339_i_3192), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_N_14338_i_3133), + .Q(NlwRenamedSig_OI_trn_rd[58]) + ); + FDE com_tlm_u_tlm_rx_vc0_fifo_d_d_57_ ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_N_68339_i_3192), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_N_14339_i_3134), + .Q(NlwRenamedSig_OI_trn_rd[57]) + ); + FDE com_tlm_u_tlm_rx_vc0_fifo_d_d_56_ ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_N_68339_i_3192), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_N_14340_i_3135), + .Q(NlwRenamedSig_OI_trn_rd[56]) + ); + FDE com_tlm_u_tlm_rx_vc0_fifo_d_d_55_ ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_N_68339_i_3192), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_N_14341_i_3136), + .Q(NlwRenamedSig_OI_trn_rd[55]) + ); + FDE com_tlm_u_tlm_rx_vc0_fifo_d_d_54_ ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_N_68339_i_3192), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_N_14342_i_3137), + .Q(NlwRenamedSig_OI_trn_rd[54]) + ); + FDE com_tlm_u_tlm_rx_vc0_fifo_d_d_53_ ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_N_68339_i_3192), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_N_14343_i_3138), + .Q(NlwRenamedSig_OI_trn_rd[53]) + ); + FDE com_tlm_u_tlm_rx_vc0_fifo_d_d_52_ ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_N_68339_i_3192), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_N_14344_i_3139), + .Q(NlwRenamedSig_OI_trn_rd[52]) + ); + FDE com_tlm_u_tlm_rx_vc0_fifo_d_d_51_ ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_N_68339_i_3192), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_N_14345_i_3140), + .Q(NlwRenamedSig_OI_trn_rd[51]) + ); + FDE com_tlm_u_tlm_rx_vc0_fifo_d_d_50_ ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_N_68339_i_3192), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_N_14346_i_3141), + .Q(NlwRenamedSig_OI_trn_rd[50]) + ); + FDE com_tlm_u_tlm_rx_vc0_fifo_d_d_49_ ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_N_68339_i_3192), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_N_14347_i_3142), + .Q(NlwRenamedSig_OI_trn_rd[49]) + ); + FDE com_tlm_u_tlm_rx_vc0_fifo_d_d_48_ ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_N_68339_i_3192), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_N_14348_i_3143), + .Q(NlwRenamedSig_OI_trn_rd[48]) + ); + FDE com_tlm_u_tlm_rx_vc0_fifo_d_d_47_ ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_N_68339_i_3192), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_N_14379_i_3144), + .Q(NlwRenamedSig_OI_trn_rd[47]) + ); + FDE com_tlm_u_tlm_rx_vc0_fifo_d_d_46_ ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_N_68339_i_3192), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_N_14376_i_3145), + .Q(NlwRenamedSig_OI_trn_rd[46]) + ); + FDE com_tlm_u_tlm_rx_vc0_fifo_d_d_45_ ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_N_68339_i_3192), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_N_9262_i_3146), + .Q(NlwRenamedSig_OI_trn_rd[45]) + ); + FDE com_tlm_u_tlm_rx_vc0_fifo_d_d_44_ ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_N_68339_i_3192), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_N_9263_i_3147), + .Q(NlwRenamedSig_OI_trn_rd[44]) + ); + FDE com_tlm_u_tlm_rx_vc0_fifo_d_d_43_ ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_N_68339_i_3192), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_N_9264_i_3148), + .Q(NlwRenamedSig_OI_trn_rd[43]) + ); + FDE com_tlm_u_tlm_rx_vc0_fifo_d_d_42_ ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_N_68339_i_3192), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_N_9265_i_3149), + .Q(NlwRenamedSig_OI_trn_rd[42]) + ); + FDE com_tlm_u_tlm_rx_vc0_fifo_d_d_41_ ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_N_68339_i_3192), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_N_9266_i_3150), + .Q(NlwRenamedSig_OI_trn_rd[41]) + ); + FDE com_tlm_u_tlm_rx_vc0_fifo_d_d_40_ ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_N_68339_i_3192), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_N_9267_i_3151), + .Q(NlwRenamedSig_OI_trn_rd[40]) + ); + FDE com_tlm_u_tlm_rx_vc0_fifo_d_d_39_ ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_N_68339_i_3192), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_N_9268_i_3152), + .Q(NlwRenamedSig_OI_trn_rd[39]) + ); + FDE com_tlm_u_tlm_rx_vc0_fifo_d_d_38_ ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_N_68339_i_3192), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_N_9269_i_3153), + .Q(NlwRenamedSig_OI_trn_rd[38]) + ); + FDE com_tlm_u_tlm_rx_vc0_fifo_d_d_37_ ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_N_68339_i_3192), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_N_9270_i_3154), + .Q(NlwRenamedSig_OI_trn_rd[37]) + ); + FDE com_tlm_u_tlm_rx_vc0_fifo_d_d_36_ ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_N_68339_i_3192), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_N_9271_i_3155), + .Q(NlwRenamedSig_OI_trn_rd[36]) + ); + FDE com_tlm_u_tlm_rx_vc0_fifo_d_d_35_ ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_N_68339_i_3192), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_N_9272_i_3156), + .Q(NlwRenamedSig_OI_trn_rd[35]) + ); + FDE com_tlm_u_tlm_rx_vc0_fifo_d_d_34_ ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_N_68339_i_3192), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_N_9273_i_3157), + .Q(NlwRenamedSig_OI_trn_rd[34]) + ); + FDE com_tlm_u_tlm_rx_vc0_fifo_d_d_33_ ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_N_68339_i_3192), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_N_9274_i_3158), + .Q(NlwRenamedSig_OI_trn_rd[33]) + ); + FDE com_tlm_u_tlm_rx_vc0_fifo_d_d_32_ ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_N_68339_i_3192), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_N_9275_i_3159), + .Q(NlwRenamedSig_OI_trn_rd[32]) + ); + FDE com_tlm_u_tlm_rx_vc0_fifo_d_d_31_ ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_N_68339_i_3192), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_N_9276_i_3160), + .Q(NlwRenamedSig_OI_trn_rd[31]) + ); + FDE com_tlm_u_tlm_rx_vc0_fifo_d_d_30_ ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_N_68339_i_3192), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_N_9277_i_3161), + .Q(NlwRenamedSig_OI_trn_rd[30]) + ); + FDE com_tlm_u_tlm_rx_vc0_fifo_d_d_29_ ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_N_68339_i_3192), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_N_9278_i_3162), + .Q(NlwRenamedSig_OI_trn_rd[29]) + ); + FDE com_tlm_u_tlm_rx_vc0_fifo_d_d_28_ ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_N_68339_i_3192), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_N_9279_i_3163), + .Q(NlwRenamedSig_OI_trn_rd[28]) + ); + FDE com_tlm_u_tlm_rx_vc0_fifo_d_d_27_ ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_N_68339_i_3192), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_N_9280_i_3164), + .Q(NlwRenamedSig_OI_trn_rd[27]) + ); + FDE com_tlm_u_tlm_rx_vc0_fifo_d_d_26_ ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_N_68339_i_3192), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_N_9281_i_3165), + .Q(NlwRenamedSig_OI_trn_rd[26]) + ); + FDE com_tlm_u_tlm_rx_vc0_fifo_d_d_25_ ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_N_68339_i_3192), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_N_9282_i_3166), + .Q(NlwRenamedSig_OI_trn_rd[25]) + ); + FDE com_tlm_u_tlm_rx_vc0_fifo_d_d_24_ ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_N_68339_i_3192), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_N_9283_i_3167), + .Q(NlwRenamedSig_OI_trn_rd[24]) + ); + FDE com_tlm_u_tlm_rx_vc0_fifo_d_d_23_ ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_N_68339_i_3192), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_N_14349_i_3168), + .Q(NlwRenamedSig_OI_trn_rd[23]) + ); + FDE com_tlm_u_tlm_rx_vc0_fifo_d_d_22_ ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_N_68339_i_3192), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_N_14350_i_3169), + .Q(NlwRenamedSig_OI_trn_rd[22]) + ); + FDE com_tlm_u_tlm_rx_vc0_fifo_d_d_21_ ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_N_68339_i_3192), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_N_14351_i_3170), + .Q(NlwRenamedSig_OI_trn_rd[21]) + ); + FDE com_tlm_u_tlm_rx_vc0_fifo_d_d_20_ ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_N_68339_i_3192), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_N_14352_i_3171), + .Q(NlwRenamedSig_OI_trn_rd[20]) + ); + FDE com_tlm_u_tlm_rx_vc0_fifo_d_d_19_ ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_N_68339_i_3192), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_N_14353_i_3172), + .Q(NlwRenamedSig_OI_trn_rd[19]) + ); + FDE com_tlm_u_tlm_rx_vc0_fifo_d_d_18_ ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_N_68339_i_3192), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_N_14354_i_3173), + .Q(NlwRenamedSig_OI_trn_rd[18]) + ); + FDE com_tlm_u_tlm_rx_vc0_fifo_d_d_17_ ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_N_68339_i_3192), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_N_14355_i_3174), + .Q(NlwRenamedSig_OI_trn_rd[17]) + ); + FDE com_tlm_u_tlm_rx_vc0_fifo_d_d_16_ ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_N_68339_i_3192), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_N_14356_i_3175), + .Q(NlwRenamedSig_OI_trn_rd[16]) + ); + FDE com_tlm_u_tlm_rx_vc0_fifo_d_d_15_ ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_N_68339_i_3192), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_N_14357_i_3176), + .Q(NlwRenamedSig_OI_trn_rd[15]) + ); + FDE com_tlm_u_tlm_rx_vc0_fifo_d_d_14_ ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_N_68339_i_3192), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_N_14358_i_3177), + .Q(NlwRenamedSig_OI_trn_rd[14]) + ); + FDE com_tlm_u_tlm_rx_vc0_fifo_d_d_13_ ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_N_68339_i_3192), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_N_14359_i_3178), + .Q(NlwRenamedSig_OI_trn_rd[13]) + ); + FDE com_tlm_u_tlm_rx_vc0_fifo_d_d_12_ ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_N_68339_i_3192), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_N_14360_i_3179), + .Q(NlwRenamedSig_OI_trn_rd[12]) + ); + FDE com_tlm_u_tlm_rx_vc0_fifo_d_d_11_ ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_N_68339_i_3192), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_N_14361_i_3180), + .Q(NlwRenamedSig_OI_trn_rd[11]) + ); + FDE com_tlm_u_tlm_rx_vc0_fifo_d_d_10_ ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_N_68339_i_3192), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_N_14362_i_3181), + .Q(NlwRenamedSig_OI_trn_rd[10]) + ); + FDE com_tlm_u_tlm_rx_vc0_fifo_d_d_9_ ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_N_68339_i_3192), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_N_14363_i_3182), + .Q(NlwRenamedSig_OI_trn_rd[9]) + ); + FDE com_tlm_u_tlm_rx_vc0_fifo_d_d_8_ ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_N_68339_i_3192), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_N_14364_i_3183), + .Q(NlwRenamedSig_OI_trn_rd[8]) + ); + FDE com_tlm_u_tlm_rx_vc0_fifo_d_d_7_ ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_N_68339_i_3192), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_N_14365_i_3184), + .Q(NlwRenamedSig_OI_trn_rd[7]) + ); + FDE com_tlm_u_tlm_rx_vc0_fifo_d_d_6_ ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_N_68339_i_3192), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_N_14366_i_3185), + .Q(NlwRenamedSig_OI_trn_rd[6]) + ); + FDE com_tlm_u_tlm_rx_vc0_fifo_d_d_5_ ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_N_68339_i_3192), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_N_14367_i_3186), + .Q(NlwRenamedSig_OI_trn_rd[5]) + ); + FDE com_tlm_u_tlm_rx_vc0_fifo_d_d_4_ ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_N_68339_i_3192), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_N_14368_i_3187), + .Q(NlwRenamedSig_OI_trn_rd[4]) + ); + FDE com_tlm_u_tlm_rx_vc0_fifo_d_d_3_ ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_N_68339_i_3192), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_N_14369_i_3188), + .Q(NlwRenamedSig_OI_trn_rd[3]) + ); + FDE com_tlm_u_tlm_rx_vc0_fifo_d_d_2_ ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_N_68339_i_3192), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_N_14370_i_3189), + .Q(NlwRenamedSig_OI_trn_rd[2]) + ); + FDE com_tlm_u_tlm_rx_vc0_fifo_d_d_1_ ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_N_68339_i_3192), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_N_14371_i_3190), + .Q(NlwRenamedSig_OI_trn_rd[1]) + ); + FDE com_tlm_u_tlm_rx_vc0_fifo_d_d_0_ ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_N_68339_i_3192), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_N_14372_i_3191), + .Q(NlwRenamedSig_OI_trn_rd[0]) + ); + INV com_tlm_u_tlm_rx_vc0_fifo_trn_rbar_hit_i_0_ ( + .I(com_tlm_u_tlm_rx_vc0_fifo_trn_rbar_hit[0]), + .O(trn_rbar_hit_n_5059[0]) + ); + INV com_tlm_u_tlm_rx_vc0_fifo_trn_rbar_hit_i_1_ ( + .I(com_tlm_u_tlm_rx_vc0_fifo_trn_rbar_hit[1]), + .O(trn_rbar_hit_n_5059[1]) + ); + INV com_tlm_u_tlm_rx_vc0_fifo_trn_rbar_hit_i_2_ ( + .I(com_tlm_u_tlm_rx_vc0_fifo_trn_rbar_hit[2]), + .O(trn_rbar_hit_n_5059[2]) + ); + INV com_tlm_u_tlm_rx_vc0_fifo_trn_rbar_hit_i_3_ ( + .I(com_tlm_u_tlm_rx_vc0_fifo_trn_rbar_hit[3]), + .O(trn_rbar_hit_n_5059[3]) + ); + INV com_tlm_u_tlm_rx_vc0_fifo_trn_rbar_hit_i_4_ ( + .I(com_tlm_u_tlm_rx_vc0_fifo_trn_rbar_hit[4]), + .O(trn_rbar_hit_n_5059[4]) + ); + INV com_tlm_u_tlm_rx_vc0_fifo_trn_rbar_hit_i_5_ ( + .I(com_tlm_u_tlm_rx_vc0_fifo_trn_rbar_hit[5]), + .O(trn_rbar_hit_n_5059[5]) + ); + INV com_tlm_u_tlm_rx_vc0_fifo_trn_rbar_hit_i_6_ ( + .I(com_tlm_u_tlm_rx_vc0_fifo_trn_rbar_hit[6]), + .O(trn_rbar_hit_n_5059[6]) + ); + INV com_tlm_u_tlm_rx_vc0_fifo_trn_rerrfwd_i ( + .I(com_tlm_u_tlm_rx_vc0_fifo_trn_rerrfwd), + .O(trn_rerrfwd_n) + ); + INV com_tlm_u_tlm_rx_vc0_fifo_trn_rsrc_dsc_i ( + .I(com_tlm_u_tlm_rx_vc0_fifo_trn_rsrc_dsc), + .O(trn_rsrc_dsc_n) + ); + INV com_tlm_u_tlm_rx_vc0_fifo_trn_rsrc_rdy_i ( + .I(com_tlm_u_tlm_rx_vc0_trn_rsrc_rdy), + .O(trn_rsrc_rdy_n) + ); + INV com_tlm_u_tlm_rx_vc0_fifo_trn_reof_i ( + .I(com_tlm_u_tlm_rx_vc0_trn_reof), + .O(trn_reof_n) + ); + INV com_tlm_u_tlm_rx_vc0_fifo_trn_rsof_i ( + .I(com_tlm_u_tlm_rx_vc0_trn_rsof), + .O(trn_rsof_n) + ); + INV com_tlm_u_tlm_rx_vc0_fifo_trn_rrem_i ( + .I(com_tlm_u_tlm_rx_vc0_trn_rrem), + .O(NlwRenamedSignal_trn_rrem_n[3]) + ); + INV com_tlm_u_tlm_rx_vc0_fifo_N_68339_i ( + .I(com_tlm_u_tlm_rx_vc0_fifo_adv_out_i_0_3193), + .O(com_tlm_u_tlm_rx_vc0_fifo_N_68339_i_3192) + ); + INV com_tlm_u_tlm_rx_vc0_fifo_N_67945_i ( + .I(com_tlm_u_tlm_rx_vc0_fifo_adv_pkt_in_i_3195), + .O(com_tlm_u_tlm_rx_vc0_fifo_N_67945_i_3194) + ); + VCC com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_VCC ( + .P(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_VCC_3309) + ); + GND com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_GND ( + .G(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_GND_3259) + ); + FDRE com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr_bkp_0_ ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_frm_vld_3301), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr_p1[0]), + .Q(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr_bkp[0]), + .R(plm_link_up_i) + ); + FDRE com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr_bkp_1_ ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_frm_vld_3301), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr_p1[1]), + .Q(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr_bkp[1]), + .R(plm_link_up_i) + ); + FDRE com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr_bkp_2_ ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_frm_vld_3301), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr_p1[2]), + .Q(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr_bkp[2]), + .R(plm_link_up_i) + ); + FDRE com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr_bkp_3_ ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_frm_vld_3301), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr_p1[3]), + .Q(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr_bkp[3]), + .R(plm_link_up_i) + ); + FDRE com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr_bkp_4_ ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_frm_vld_3301), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr_p1[4]), + .Q(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr_bkp[4]), + .R(plm_link_up_i) + ); + FDRE com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr_bkp_5_ ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_frm_vld_3301), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr_p1[5]), + .Q(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr_bkp[5]), + .R(plm_link_up_i) + ); + FDRE com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr_bkp_6_ ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_frm_vld_3301), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr_p1[6]), + .Q(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr_bkp[6]), + .R(plm_link_up_i) + ); + FDRE com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr_bkp_7_ ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_frm_vld_3301), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr_p1[7]), + .Q(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr_bkp[7]), + .R(plm_link_up_i) + ); + FDRE com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr_bkp_8_ ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_frm_vld_3301), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr_p1[8]), + .Q(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr_bkp[8]), + .R(plm_link_up_i) + ); + FDRE com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr_bkp_9_ ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_frm_vld_3301), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr_p1[9]), + .Q(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr_bkp[9]), + .R(plm_link_up_i) + ); + FDS com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr_p1_0_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_waddr_p1_1_s_0_3196), + .Q(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr_p1[0]), + .S(plm_link_up_i) + ); + FDR com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr_p1_1_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_waddr_p1_1_s_1_3197), + .Q(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr_p1[1]), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr_p1_2_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_waddr_p1_1_s_2_3199), + .Q(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr_p1[2]), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr_p1_3_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_waddr_p1_1_s_3_3201), + .Q(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr_p1[3]), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr_p1_4_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_waddr_p1_1_s_4_3203), + .Q(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr_p1[4]), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr_p1_5_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_waddr_p1_1_s_5_3205), + .Q(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr_p1[5]), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr_p1_6_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_waddr_p1_1_s_6_3207), + .Q(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr_p1[6]), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr_p1_7_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_waddr_p1_1_s_7_3209), + .Q(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr_p1[7]), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr_p1_8_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_waddr_p1_1_s_8_3211), + .Q(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr_p1[8]), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr_p1_9_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_waddr_p1_1_s_9_3213), + .Q(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr_p1[9]), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_vld_ct_0_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_vld_ct_1_axb_0_3262), + .Q(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_vld_ct[0]), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_vld_ct_1_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_vld_ct_1_s_1_3239), + .Q(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_vld_ct[1]), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_vld_ct_2_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_vld_ct_1_s_2_3241), + .Q(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_vld_ct[2]), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_vld_ct_3_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_vld_ct_1_s_3_3243), + .Q(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_vld_ct[3]), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_vld_ct_4_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_vld_ct_1_s_4_3245), + .Q(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_vld_ct[4]), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_vld_ct_5_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_vld_ct_1_s_5_3247), + .Q(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_vld_ct[5]), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_vld_ct_6_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_vld_ct_1_s_6_3249), + .Q(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_vld_ct[6]), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_vld_ct_7_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_vld_ct_1_s_7_3252), + .Q(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_vld_ct[7]), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_vld_ct_8_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_vld_ct_1_s_8_3255), + .Q(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_vld_ct[8]), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_vld_ct_9_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_vld_ct_1_s_9_3257), + .Q(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_vld_ct[9]), + .R(plm_link_up_i) + ); + FDSE com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_pkt_ct_m1_0_ ( + .CE(com_tlm_u_tlm_rx_ds_src_rdy), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un8_pkt_ct_m1_i[0]), + .Q(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_pkt_ct_m1[0]), + .S(plm_link_up_i) + ); + FDRE com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_pkt_ct_m1_1_ ( + .CE(com_tlm_u_tlm_rx_ds_src_rdy), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un3_pkt_ct_m1_s_1_3227), + .Q(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_pkt_ct_m1[1]), + .R(plm_link_up_i) + ); + FDRE com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_pkt_ct_m1_2_ ( + .CE(com_tlm_u_tlm_rx_ds_src_rdy), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un3_pkt_ct_m1_s_2_3229), + .Q(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_pkt_ct_m1[2]), + .R(plm_link_up_i) + ); + FDRE com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_pkt_ct_m1_3_ ( + .CE(com_tlm_u_tlm_rx_ds_src_rdy), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un3_pkt_ct_m1_s_3_3231), + .Q(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_pkt_ct_m1[3]), + .R(plm_link_up_i) + ); + FDRE com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_pkt_ct_m1_4_ ( + .CE(com_tlm_u_tlm_rx_ds_src_rdy), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un3_pkt_ct_m1_s_4_3233), + .Q(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_pkt_ct_m1[4]), + .R(plm_link_up_i) + ); + FDRE com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_pkt_ct_m1_5_ ( + .CE(com_tlm_u_tlm_rx_ds_src_rdy), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un3_pkt_ct_m1_s_5_3235), + .Q(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_pkt_ct_m1[5]), + .R(plm_link_up_i) + ); + FDRE com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_pkt_ct_m1_6_ ( + .CE(com_tlm_u_tlm_rx_ds_src_rdy), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un3_pkt_ct_m1_s_6_3237), + .Q(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_pkt_ct_m1[6]), + .R(plm_link_up_i) + ); + FDRE com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_pkt_ct_0_ ( + .CE(com_tlm_u_tlm_rx_ds_src_rdy), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un8_pkt_ct[0]), + .Q(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_pkt_ct[0]), + .R(plm_link_up_i) + ); + FDSE com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_pkt_ct_1_ ( + .CE(com_tlm_u_tlm_rx_ds_src_rdy), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un3_pkt_ct_s_1_3215), + .Q(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_pkt_ct[1]), + .S(plm_link_up_i) + ); + FDRE com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_pkt_ct_2_ ( + .CE(com_tlm_u_tlm_rx_ds_src_rdy), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un3_pkt_ct_s_2_3217), + .Q(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_pkt_ct[2]), + .R(plm_link_up_i) + ); + FDRE com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_pkt_ct_3_ ( + .CE(com_tlm_u_tlm_rx_ds_src_rdy), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un3_pkt_ct_s_3_3219), + .Q(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_pkt_ct[3]), + .R(plm_link_up_i) + ); + FDRE com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_pkt_ct_4_ ( + .CE(com_tlm_u_tlm_rx_ds_src_rdy), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un3_pkt_ct_s_4_3221), + .Q(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_pkt_ct[4]), + .R(plm_link_up_i) + ); + FDRE com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_pkt_ct_5_ ( + .CE(com_tlm_u_tlm_rx_ds_src_rdy), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un3_pkt_ct_s_5_3223), + .Q(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_pkt_ct[5]), + .R(plm_link_up_i) + ); + FDRE com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_pkt_ct_6_ ( + .CE(com_tlm_u_tlm_rx_ds_src_rdy), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un3_pkt_ct_s_6_3225), + .Q(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_pkt_ct[6]), + .R(plm_link_up_i) + ); + FDRE com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_all_full ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_N_9613_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_N_9613_2), + .Q(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_all_full_3264), + .R(plm_link_up_i) + ); + FDRE com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_vld_o ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_N_9616_i_3306), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_nxt_vld_3303), + .Q(com_tlm_u_tlm_rx_vc0_fifo_data_vld_oqr), + .R(plm_link_up_i) + ); + FDRSE com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_nxt_vld ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_vld_ct_eq_1_3265), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_GND_3259), + .Q(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_nxt_vld_3303), + .R(plm_link_up_i), + .S(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_vld_ct25) + ); + FDRE com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_lockout ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_wen_i_1_0), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_ds_eof_i), + .Q(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_lockout_3260), + .R(plm_link_up_i) + ); + MUXCY_L com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_waddr_p1_1_cry_0 ( + .CI(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_N_9612_i_3304), + .DI(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_GND_3259), + .LO(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_waddr_p1_1_cry_0_3198), + .S(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_waddr_p1_1_axb_0_3299) + ); + XORCY com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_waddr_p1_1_s_0 ( + .CI(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_N_9612_i_3304), + .LI(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_waddr_p1_1_axb_0_3299), + .O(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_waddr_p1_1_s_0_3196) + ); + MUXCY_L com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_waddr_p1_1_cry_1 ( + .CI(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_waddr_p1_1_cry_0_3198), + .DI(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_GND_3259), + .LO(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_waddr_p1_1_cry_1_3200), + .S(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_waddr_p1_1_axb_1_3298) + ); + XORCY com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_waddr_p1_1_s_1 ( + .CI(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_waddr_p1_1_cry_0_3198), + .LI(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_waddr_p1_1_axb_1_3298), + .O(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_waddr_p1_1_s_1_3197) + ); + MUXCY_L com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_waddr_p1_1_cry_2 ( + .CI(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_waddr_p1_1_cry_1_3200), + .DI(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_GND_3259), + .LO(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_waddr_p1_1_cry_2_3202), + .S(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_waddr_p1_1_axb_2_3297) + ); + XORCY com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_waddr_p1_1_s_2 ( + .CI(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_waddr_p1_1_cry_1_3200), + .LI(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_waddr_p1_1_axb_2_3297), + .O(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_waddr_p1_1_s_2_3199) + ); + MUXCY_L com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_waddr_p1_1_cry_3 ( + .CI(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_waddr_p1_1_cry_2_3202), + .DI(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_GND_3259), + .LO(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_waddr_p1_1_cry_3_3204), + .S(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_waddr_p1_1_axb_3_3296) + ); + XORCY com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_waddr_p1_1_s_3 ( + .CI(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_waddr_p1_1_cry_2_3202), + .LI(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_waddr_p1_1_axb_3_3296), + .O(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_waddr_p1_1_s_3_3201) + ); + MUXCY_L com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_waddr_p1_1_cry_4 ( + .CI(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_waddr_p1_1_cry_3_3204), + .DI(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_GND_3259), + .LO(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_waddr_p1_1_cry_4_3206), + .S(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_waddr_p1_1_axb_4_3295) + ); + XORCY com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_waddr_p1_1_s_4 ( + .CI(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_waddr_p1_1_cry_3_3204), + .LI(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_waddr_p1_1_axb_4_3295), + .O(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_waddr_p1_1_s_4_3203) + ); + MUXCY_L com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_waddr_p1_1_cry_5 ( + .CI(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_waddr_p1_1_cry_4_3206), + .DI(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_GND_3259), + .LO(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_waddr_p1_1_cry_5_3208), + .S(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_waddr_p1_1_axb_5_3294) + ); + XORCY com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_waddr_p1_1_s_5 ( + .CI(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_waddr_p1_1_cry_4_3206), + .LI(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_waddr_p1_1_axb_5_3294), + .O(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_waddr_p1_1_s_5_3205) + ); + MUXCY_L com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_waddr_p1_1_cry_6 ( + .CI(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_waddr_p1_1_cry_5_3208), + .DI(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_GND_3259), + .LO(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_waddr_p1_1_cry_6_3210), + .S(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_waddr_p1_1_axb_6_3293) + ); + XORCY com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_waddr_p1_1_s_6 ( + .CI(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_waddr_p1_1_cry_5_3208), + .LI(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_waddr_p1_1_axb_6_3293), + .O(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_waddr_p1_1_s_6_3207) + ); + MUXCY_L com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_waddr_p1_1_cry_7 ( + .CI(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_waddr_p1_1_cry_6_3210), + .DI(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_GND_3259), + .LO(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_waddr_p1_1_cry_7_3212), + .S(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_waddr_p1_1_axb_7_3292) + ); + XORCY com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_waddr_p1_1_s_7 ( + .CI(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_waddr_p1_1_cry_6_3210), + .LI(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_waddr_p1_1_axb_7_3292), + .O(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_waddr_p1_1_s_7_3209) + ); + MUXCY_L com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_waddr_p1_1_cry_8 ( + .CI(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_waddr_p1_1_cry_7_3212), + .DI(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_GND_3259), + .LO(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_waddr_p1_1_cry_8_3214), + .S(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_waddr_p1_1_axb_8_3291) + ); + XORCY com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_waddr_p1_1_s_8 ( + .CI(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_waddr_p1_1_cry_7_3212), + .LI(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_waddr_p1_1_axb_8_3291), + .O(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_waddr_p1_1_s_8_3211) + ); + XORCY com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_waddr_p1_1_s_9 ( + .CI(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_waddr_p1_1_cry_8_3214), + .LI(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_waddr_p1_1_axb_9_3290), + .O(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_waddr_p1_1_s_9_3213) + ); + MUXCY_L com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un3_pkt_ct_cry_0 ( + .CI(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_VCC_3309), + .DI(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_GND_3259), + .LO(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un3_pkt_ct_cry_0_3216), + .S(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un3_pkt_ct_axb_0_3311) + ); + MUXCY_L com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un3_pkt_ct_cry_1 ( + .CI(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un3_pkt_ct_cry_0_3216), + .DI(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_GND_3259), + .LO(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un3_pkt_ct_cry_1_3218), + .S(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un3_pkt_ct_axb_1_3274) + ); + XORCY com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un3_pkt_ct_s_1 ( + .CI(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un3_pkt_ct_cry_0_3216), + .LI(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un3_pkt_ct_axb_1_3274), + .O(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un3_pkt_ct_s_1_3215) + ); + MUXCY_L com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un3_pkt_ct_cry_2 ( + .CI(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un3_pkt_ct_cry_1_3218), + .DI(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_GND_3259), + .LO(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un3_pkt_ct_cry_2_3220), + .S(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un3_pkt_ct_axb_2_3273) + ); + XORCY com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un3_pkt_ct_s_2 ( + .CI(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un3_pkt_ct_cry_1_3218), + .LI(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un3_pkt_ct_axb_2_3273), + .O(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un3_pkt_ct_s_2_3217) + ); + MUXCY_L com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un3_pkt_ct_cry_3 ( + .CI(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un3_pkt_ct_cry_2_3220), + .DI(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_GND_3259), + .LO(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un3_pkt_ct_cry_3_3222), + .S(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un3_pkt_ct_axb_3_3272) + ); + XORCY com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un3_pkt_ct_s_3 ( + .CI(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un3_pkt_ct_cry_2_3220), + .LI(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un3_pkt_ct_axb_3_3272), + .O(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un3_pkt_ct_s_3_3219) + ); + MUXCY_L com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un3_pkt_ct_cry_4 ( + .CI(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un3_pkt_ct_cry_3_3222), + .DI(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_GND_3259), + .LO(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un3_pkt_ct_cry_4_3224), + .S(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un3_pkt_ct_axb_4_3271) + ); + XORCY com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un3_pkt_ct_s_4 ( + .CI(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un3_pkt_ct_cry_3_3222), + .LI(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un3_pkt_ct_axb_4_3271), + .O(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un3_pkt_ct_s_4_3221) + ); + MUXCY_L com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un3_pkt_ct_cry_5 ( + .CI(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un3_pkt_ct_cry_4_3224), + .DI(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_GND_3259), + .LO(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un3_pkt_ct_cry_5_3226), + .S(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un3_pkt_ct_axb_5_3270) + ); + XORCY com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un3_pkt_ct_s_5 ( + .CI(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un3_pkt_ct_cry_4_3224), + .LI(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un3_pkt_ct_axb_5_3270), + .O(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un3_pkt_ct_s_5_3223) + ); + XORCY com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un3_pkt_ct_s_6 ( + .CI(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un3_pkt_ct_cry_5_3226), + .LI(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un3_pkt_ct_axb_6_3269), + .O(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un3_pkt_ct_s_6_3225) + ); + MUXCY_L com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un3_pkt_ct_m1_cry_0 ( + .CI(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_VCC_3309), + .DI(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_GND_3259), + .LO(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un3_pkt_ct_m1_cry_0_3228), + .S(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un3_pkt_ct_m1_axb_0_3310) + ); + MUXCY_L com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un3_pkt_ct_m1_cry_1 ( + .CI(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un3_pkt_ct_m1_cry_0_3228), + .DI(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_GND_3259), + .LO(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un3_pkt_ct_m1_cry_1_3230), + .S(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un3_pkt_ct_m1_axb_1_3280) + ); + XORCY com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un3_pkt_ct_m1_s_1 ( + .CI(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un3_pkt_ct_m1_cry_0_3228), + .LI(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un3_pkt_ct_m1_axb_1_3280), + .O(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un3_pkt_ct_m1_s_1_3227) + ); + MUXCY_L com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un3_pkt_ct_m1_cry_2 ( + .CI(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un3_pkt_ct_m1_cry_1_3230), + .DI(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_GND_3259), + .LO(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un3_pkt_ct_m1_cry_2_3232), + .S(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un3_pkt_ct_m1_axb_2_3279) + ); + XORCY com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un3_pkt_ct_m1_s_2 ( + .CI(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un3_pkt_ct_m1_cry_1_3230), + .LI(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un3_pkt_ct_m1_axb_2_3279), + .O(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un3_pkt_ct_m1_s_2_3229) + ); + MUXCY_L com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un3_pkt_ct_m1_cry_3 ( + .CI(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un3_pkt_ct_m1_cry_2_3232), + .DI(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_GND_3259), + .LO(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un3_pkt_ct_m1_cry_3_3234), + .S(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un3_pkt_ct_m1_axb_3_3278) + ); + XORCY com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un3_pkt_ct_m1_s_3 ( + .CI(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un3_pkt_ct_m1_cry_2_3232), + .LI(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un3_pkt_ct_m1_axb_3_3278), + .O(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un3_pkt_ct_m1_s_3_3231) + ); + MUXCY_L com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un3_pkt_ct_m1_cry_4 ( + .CI(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un3_pkt_ct_m1_cry_3_3234), + .DI(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_GND_3259), + .LO(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un3_pkt_ct_m1_cry_4_3236), + .S(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un3_pkt_ct_m1_axb_4_3277) + ); + XORCY com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un3_pkt_ct_m1_s_4 ( + .CI(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un3_pkt_ct_m1_cry_3_3234), + .LI(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un3_pkt_ct_m1_axb_4_3277), + .O(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un3_pkt_ct_m1_s_4_3233) + ); + MUXCY_L com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un3_pkt_ct_m1_cry_5 ( + .CI(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un3_pkt_ct_m1_cry_4_3236), + .DI(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_GND_3259), + .LO(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un3_pkt_ct_m1_cry_5_3238), + .S(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un3_pkt_ct_m1_axb_5_3276) + ); + XORCY com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un3_pkt_ct_m1_s_5 ( + .CI(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un3_pkt_ct_m1_cry_4_3236), + .LI(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un3_pkt_ct_m1_axb_5_3276), + .O(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un3_pkt_ct_m1_s_5_3235) + ); + XORCY com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un3_pkt_ct_m1_s_6 ( + .CI(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un3_pkt_ct_m1_cry_5_3238), + .LI(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un3_pkt_ct_m1_axb_6_3275), + .O(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un3_pkt_ct_m1_s_6_3237) + ); + MUXCY_L com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_vld_ct_1_cry_0 ( + .CI(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_GND_3259), + .DI(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_vld_ct[0]), + .LO(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_vld_ct_1_cry_0_3240), + .S(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_vld_ct_1_axb_0_3262) + ); + MUXCY_L com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_vld_ct_1_cry_1 ( + .CI(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_vld_ct_1_cry_0_3240), + .DI(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_vld_ct[1]), + .LO(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_vld_ct_1_cry_1_3242), + .S(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_vld_ct_1_axb_1_3289) + ); + XORCY com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_vld_ct_1_s_1 ( + .CI(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_vld_ct_1_cry_0_3240), + .LI(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_vld_ct_1_axb_1_3289), + .O(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_vld_ct_1_s_1_3239) + ); + MUXCY_L com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_vld_ct_1_cry_2 ( + .CI(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_vld_ct_1_cry_1_3242), + .DI(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_vld_ct[2]), + .LO(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_vld_ct_1_cry_2_3244), + .S(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_vld_ct_1_axb_2_3288) + ); + XORCY com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_vld_ct_1_s_2 ( + .CI(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_vld_ct_1_cry_1_3242), + .LI(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_vld_ct_1_axb_2_3288), + .O(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_vld_ct_1_s_2_3241) + ); + MUXCY_L com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_vld_ct_1_cry_3 ( + .CI(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_vld_ct_1_cry_2_3244), + .DI(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_vld_ct[3]), + .LO(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_vld_ct_1_cry_3_3246), + .S(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_vld_ct_1_axb_3_3287) + ); + XORCY com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_vld_ct_1_s_3 ( + .CI(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_vld_ct_1_cry_2_3244), + .LI(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_vld_ct_1_axb_3_3287), + .O(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_vld_ct_1_s_3_3243) + ); + MUXCY_L com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_vld_ct_1_cry_4 ( + .CI(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_vld_ct_1_cry_3_3246), + .DI(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_vld_ct[4]), + .LO(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_vld_ct_1_cry_4_3248), + .S(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_vld_ct_1_axb_4_3286) + ); + XORCY com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_vld_ct_1_s_4 ( + .CI(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_vld_ct_1_cry_3_3246), + .LI(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_vld_ct_1_axb_4_3286), + .O(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_vld_ct_1_s_4_3245) + ); + MUXCY_L com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_vld_ct_1_cry_5 ( + .CI(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_vld_ct_1_cry_4_3248), + .DI(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_vld_ct[5]), + .LO(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_vld_ct_1_cry_5_3250), + .S(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_vld_ct_1_axb_5_3285) + ); + XORCY com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_vld_ct_1_s_5 ( + .CI(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_vld_ct_1_cry_4_3248), + .LI(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_vld_ct_1_axb_5_3285), + .O(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_vld_ct_1_s_5_3247) + ); + MUXCY_L com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_vld_ct_1_cry_6 ( + .CI(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_vld_ct_1_cry_5_3250), + .DI(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_vld_ct_1_cry_6_ma_3308), + .LO(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_vld_ct_1_cry_6_3253), + .S(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_vld_ct_1_axb_6_3284) + ); + XORCY com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_vld_ct_1_s_6 ( + .CI(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_vld_ct_1_cry_5_3250), + .LI(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_vld_ct_1_axb_6_3284), + .O(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_vld_ct_1_s_6_3249) + ); + MULT_AND com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_vld_ct_1_cry_7 ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_pop_3302), + .I1(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_vld_ct25_i), + .LO(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_vld_ct_1_cry_7_0_3251) + ); + MUXCY_L com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_vld_ct_1_cry_7_0 ( + .CI(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_vld_ct_1_cry_6_3253), + .DI(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_vld_ct_1_cry_7_0_3251), + .LO(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_vld_ct_1_cry_7_3256), + .S(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_vld_ct_1_axb_7_3283) + ); + XORCY com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_vld_ct_1_s_7 ( + .CI(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_vld_ct_1_cry_6_3253), + .LI(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_vld_ct_1_axb_7_3283), + .O(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_vld_ct_1_s_7_3252) + ); + MULT_AND com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_vld_ct_1_cry_8 ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_pop_3302), + .I1(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_vld_ct25_i), + .LO(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_vld_ct_1_cry_8_0_3254) + ); + MUXCY_L com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_vld_ct_1_cry_8_0 ( + .CI(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_vld_ct_1_cry_7_3256), + .DI(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_vld_ct_1_cry_8_0_3254), + .LO(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_vld_ct_1_cry_8_3258), + .S(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_vld_ct_1_axb_8_3282) + ); + XORCY com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_vld_ct_1_s_8 ( + .CI(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_vld_ct_1_cry_7_3256), + .LI(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_vld_ct_1_axb_8_3282), + .O(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_vld_ct_1_s_8_3255) + ); + XORCY com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_vld_ct_1_s_9 ( + .CI(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_vld_ct_1_cry_8_3258), + .LI(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_vld_ct_1_axb_9_3281), + .O(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_vld_ct_1_s_9_3257) + ); + FDRE com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_raddr_0_ ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_pop_3302), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_raddr_s[0]), + .Q(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_raddr[0]), + .R(plm_link_up_i) + ); + MUXCY_L com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_raddr_cry_1_ ( + .CI(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_raddr[0]), + .DI(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_GND_3259), + .LO(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_raddr_cry[1]), + .S(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_raddr_qxu[1]) + ); + XORCY com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_raddr_s_1_ ( + .CI(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_raddr[0]), + .LI(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_raddr_qxu[1]), + .O(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_raddr_s[1]) + ); + FDRE com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_raddr_1_ ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_pop_3302), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_raddr_s[1]), + .Q(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_raddr[1]), + .R(plm_link_up_i) + ); + MUXCY_L com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_raddr_cry_2_ ( + .CI(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_raddr_cry[1]), + .DI(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_GND_3259), + .LO(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_raddr_cry[2]), + .S(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_raddr_qxu[2]) + ); + XORCY com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_raddr_s_2_ ( + .CI(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_raddr_cry[1]), + .LI(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_raddr_qxu[2]), + .O(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_raddr_s[2]) + ); + FDRE com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_raddr_2_ ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_pop_3302), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_raddr_s[2]), + .Q(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_raddr[2]), + .R(plm_link_up_i) + ); + MUXCY_L com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_raddr_cry_3_ ( + .CI(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_raddr_cry[2]), + .DI(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_GND_3259), + .LO(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_raddr_cry[3]), + .S(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_raddr_qxu[3]) + ); + XORCY com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_raddr_s_3_ ( + .CI(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_raddr_cry[2]), + .LI(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_raddr_qxu[3]), + .O(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_raddr_s[3]) + ); + FDRE com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_raddr_3_ ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_pop_3302), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_raddr_s[3]), + .Q(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_raddr[3]), + .R(plm_link_up_i) + ); + MUXCY_L com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_raddr_cry_4_ ( + .CI(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_raddr_cry[3]), + .DI(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_GND_3259), + .LO(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_raddr_cry[4]), + .S(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_raddr_qxu[4]) + ); + XORCY com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_raddr_s_4_ ( + .CI(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_raddr_cry[3]), + .LI(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_raddr_qxu[4]), + .O(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_raddr_s[4]) + ); + FDRE com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_raddr_4_ ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_pop_3302), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_raddr_s[4]), + .Q(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_raddr[4]), + .R(plm_link_up_i) + ); + MUXCY_L com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_raddr_cry_5_ ( + .CI(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_raddr_cry[4]), + .DI(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_GND_3259), + .LO(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_raddr_cry[5]), + .S(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_raddr_qxu[5]) + ); + XORCY com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_raddr_s_5_ ( + .CI(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_raddr_cry[4]), + .LI(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_raddr_qxu[5]), + .O(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_raddr_s[5]) + ); + FDRE com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_raddr_5_ ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_pop_3302), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_raddr_s[5]), + .Q(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_raddr[5]), + .R(plm_link_up_i) + ); + MUXCY_L com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_raddr_cry_6_ ( + .CI(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_raddr_cry[5]), + .DI(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_GND_3259), + .LO(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_raddr_cry[6]), + .S(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_raddr_qxu[6]) + ); + XORCY com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_raddr_s_6_ ( + .CI(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_raddr_cry[5]), + .LI(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_raddr_qxu[6]), + .O(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_raddr_s[6]) + ); + FDRE com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_raddr_6_ ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_pop_3302), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_raddr_s[6]), + .Q(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_raddr[6]), + .R(plm_link_up_i) + ); + MUXCY_L com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_raddr_cry_7_ ( + .CI(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_raddr_cry[6]), + .DI(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_GND_3259), + .LO(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_raddr_cry[7]), + .S(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_raddr_qxu[7]) + ); + XORCY com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_raddr_s_7_ ( + .CI(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_raddr_cry[6]), + .LI(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_raddr_qxu[7]), + .O(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_raddr_s[7]) + ); + FDRE com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_raddr_7_ ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_pop_3302), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_raddr_s[7]), + .Q(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_raddr[7]), + .R(plm_link_up_i) + ); + MUXCY_L com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_raddr_cry_8_ ( + .CI(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_raddr_cry[7]), + .DI(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_GND_3259), + .LO(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_raddr_cry[8]), + .S(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_raddr_qxu[8]) + ); + XORCY com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_raddr_s_8_ ( + .CI(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_raddr_cry[7]), + .LI(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_raddr_qxu[8]), + .O(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_raddr_s[8]) + ); + FDRE com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_raddr_8_ ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_pop_3302), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_raddr_s[8]), + .Q(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_raddr[8]), + .R(plm_link_up_i) + ); + XORCY com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_raddr_s_9_ ( + .CI(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_raddr_cry[8]), + .LI(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_raddr_qxu[9]), + .O(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_raddr_s[9]) + ); + FDRE com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_raddr_9_ ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_pop_3302), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_raddr_s[9]), + .Q(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_raddr[9]), + .R(plm_link_up_i) + ); + MUXCY_L com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr_cry_0_ ( + .CI(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_overflow_1_i), + .DI(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_GND_3259), + .LO(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr_cry[0]), + .S(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr_qxu[0]) + ); + XORCY com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr_s_0_ ( + .CI(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_overflow_1_i), + .LI(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr_qxu[0]), + .O(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr_s[0]) + ); + FDRE com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr_0_ ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_N_9199_i_3263), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr_s[0]), + .Q(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr[0]), + .R(plm_link_up_i) + ); + MUXCY_L com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr_cry_1_ ( + .CI(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr_cry[0]), + .DI(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_GND_3259), + .LO(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr_cry[1]), + .S(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr_qxu[1]) + ); + XORCY com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr_s_1_ ( + .CI(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr_cry[0]), + .LI(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr_qxu[1]), + .O(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr_s[1]) + ); + FDRE com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr_1_ ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_N_9199_i_3263), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr_s[1]), + .Q(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr[1]), + .R(plm_link_up_i) + ); + MUXCY_L com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr_cry_2_ ( + .CI(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr_cry[1]), + .DI(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_GND_3259), + .LO(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr_cry[2]), + .S(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr_qxu[2]) + ); + XORCY com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr_s_2_ ( + .CI(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr_cry[1]), + .LI(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr_qxu[2]), + .O(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr_s[2]) + ); + FDRE com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr_2_ ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_N_9199_i_3263), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr_s[2]), + .Q(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr[2]), + .R(plm_link_up_i) + ); + MUXCY_L com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr_cry_3_ ( + .CI(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr_cry[2]), + .DI(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_GND_3259), + .LO(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr_cry[3]), + .S(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr_qxu[3]) + ); + XORCY com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr_s_3_ ( + .CI(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr_cry[2]), + .LI(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr_qxu[3]), + .O(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr_s[3]) + ); + FDRE com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr_3_ ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_N_9199_i_3263), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr_s[3]), + .Q(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr[3]), + .R(plm_link_up_i) + ); + MUXCY_L com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr_cry_4_ ( + .CI(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr_cry[3]), + .DI(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_GND_3259), + .LO(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr_cry[4]), + .S(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr_qxu[4]) + ); + XORCY com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr_s_4_ ( + .CI(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr_cry[3]), + .LI(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr_qxu[4]), + .O(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr_s[4]) + ); + FDRE com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr_4_ ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_N_9199_i_3263), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr_s[4]), + .Q(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr[4]), + .R(plm_link_up_i) + ); + MUXCY_L com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr_cry_5_ ( + .CI(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr_cry[4]), + .DI(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_GND_3259), + .LO(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr_cry[5]), + .S(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr_qxu[5]) + ); + XORCY com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr_s_5_ ( + .CI(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr_cry[4]), + .LI(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr_qxu[5]), + .O(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr_s[5]) + ); + FDRE com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr_5_ ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_N_9199_i_3263), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr_s[5]), + .Q(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr[5]), + .R(plm_link_up_i) + ); + MUXCY_L com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr_cry_6_ ( + .CI(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr_cry[5]), + .DI(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_GND_3259), + .LO(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr_cry[6]), + .S(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr_qxu[6]) + ); + XORCY com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr_s_6_ ( + .CI(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr_cry[5]), + .LI(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr_qxu[6]), + .O(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr_s[6]) + ); + FDRE com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr_6_ ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_N_9199_i_3263), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr_s[6]), + .Q(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr[6]), + .R(plm_link_up_i) + ); + MUXCY_L com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr_cry_7_ ( + .CI(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr_cry[6]), + .DI(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_GND_3259), + .LO(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr_cry[7]), + .S(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr_qxu[7]) + ); + XORCY com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr_s_7_ ( + .CI(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr_cry[6]), + .LI(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr_qxu[7]), + .O(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr_s[7]) + ); + FDRE com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr_7_ ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_N_9199_i_3263), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr_s[7]), + .Q(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr[7]), + .R(plm_link_up_i) + ); + MUXCY_L com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr_cry_8_ ( + .CI(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr_cry[7]), + .DI(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_GND_3259), + .LO(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr_cry[8]), + .S(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr_qxu[8]) + ); + XORCY com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr_s_8_ ( + .CI(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr_cry[7]), + .LI(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr_qxu[8]), + .O(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr_s[8]) + ); + FDRE com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr_8_ ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_N_9199_i_3263), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr_s[8]), + .Q(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr[8]), + .R(plm_link_up_i) + ); + XORCY com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr_s_9_ ( + .CI(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr_cry[8]), + .LI(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr_qxu[9]), + .O(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr_s[9]) + ); + FDRE com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr_9_ ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_N_9199_i_3263), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr_s[9]), + .Q(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr[9]), + .R(plm_link_up_i) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un6_d_o_0_.INIT = 4'h8; + LUT2 com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un6_d_o_0_ ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_data_vld_oqr), + .I1(com_tlm_u_tlm_rx_vc0_fifo_ram_dout[64]), + .O(com_tlm_u_tlm_rx_vc0_fifo_sof_oqr) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un6_d_o_3_.INIT = 4'h8; + LUT2 com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un6_d_o_3_ ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_data_vld_oqr), + .I1(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_ram_dout[67]), + .O(com_tlm_u_tlm_rx_vc0_fifo_rem_oqr) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un6_d_o_0_a2_1_.INIT = 4'h8; + LUT2 com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un6_d_o_0_a2_1_ ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_data_vld_oqr), + .I1(com_tlm_u_tlm_rx_vc0_fifo_ram_dout[65]), + .O(com_tlm_u_tlm_rx_vc0_fifo_eof_oqr) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_standard_all_full_un1_waddr_p1_3.INIT = 4'h6; + LUT2 com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_standard_all_full_un1_waddr_p1_3 ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_raddr[3]), + .I1(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr_p1[3]), + .O(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_waddr_p1_3) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_vld_ct_eq_1_2.INIT = 4'h1; + LUT2 com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_vld_ct_eq_1_2 ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_vld_ct[1]), + .I1(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_vld_ct[2]), + .O(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_vld_ct_eq_1_2_3268) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un10_vld_ct_0_0_.INIT = 8'hCA; + LUT3 com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un10_vld_ct_0_0_ ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_pkt_ct[0]), + .I1(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_pkt_ct_m1[0]), + .I2(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_pop_3302), + .O(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un10_vld_ct[0]) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un10_vld_ct_0_1_.INIT = 8'hCA; + LUT3 com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un10_vld_ct_0_1_ ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_pkt_ct[1]), + .I1(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_pkt_ct_m1[1]), + .I2(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_pop_3302), + .O(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un10_vld_ct[1]) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un10_vld_ct_0_2_.INIT = 8'hCA; + LUT3 com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un10_vld_ct_0_2_ ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_pkt_ct[2]), + .I1(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_pkt_ct_m1[2]), + .I2(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_pop_3302), + .O(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un10_vld_ct[2]) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un10_vld_ct_0_3_.INIT = 8'hCA; + LUT3 com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un10_vld_ct_0_3_ ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_pkt_ct[3]), + .I1(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_pkt_ct_m1[3]), + .I2(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_pop_3302), + .O(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un10_vld_ct[3]) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un10_vld_ct_0_4_.INIT = 8'hCA; + LUT3 com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un10_vld_ct_0_4_ ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_pkt_ct[4]), + .I1(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_pkt_ct_m1[4]), + .I2(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_pop_3302), + .O(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un10_vld_ct[4]) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un10_vld_ct_0_5_.INIT = 8'hCA; + LUT3 com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un10_vld_ct_0_5_ ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_pkt_ct[5]), + .I1(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_pkt_ct_m1[5]), + .I2(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_pop_3302), + .O(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un10_vld_ct[5]) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un10_vld_ct_0_6_.INIT = 8'hCA; + LUT3 com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un10_vld_ct_0_6_ ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_pkt_ct[6]), + .I1(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_pkt_ct_m1[6]), + .I2(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_pop_3302), + .O(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un10_vld_ct[6]) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_wen_i_1.INIT = 8'hC8; + LUT3 com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_wen_i_1 ( + .I0(com_tlm_u_tlm_rx_ds_eof), + .I1(com_tlm_u_tlm_rx_ds_src_rdy), + .I2(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_all_full_3264), + .O(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_wen_i_1_0) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_push.INIT = 8'h02; + LUT3 com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_push ( + .I0(com_tlm_u_tlm_rx_ds_src_rdy), + .I1(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_all_full_3264), + .I2(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_lockout_3260), + .O(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_push_3305) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_standard_all_full_un1_wen_i_1.INIT = 16'h8421; + LUT4_L com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_standard_all_full_un1_wen_i_1 ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_raddr[7]), + .I1(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_raddr[8]), + .I2(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr_p1[7]), + .I3(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr_p1[8]), + .LO(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_wen_i_1_3261) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_standard_all_full_un1_wen_i_2.INIT = 16'h8421; + LUT4 com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_standard_all_full_un1_wen_i_2 ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_raddr[5]), + .I1(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_raddr[6]), + .I2(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr_p1[5]), + .I3(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr_p1[6]), + .O(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_wen_i_2) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_standard_all_full_un1_wen_i_4.INIT = 16'h8421; + LUT4_L com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_standard_all_full_un1_wen_i_4 ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_raddr[0]), + .I1(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_raddr[2]), + .I2(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr_p1[0]), + .I3(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr_p1[2]), + .LO(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_wen_i_4) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_vld_ct_eq_1_5.INIT = 16'h0002; + LUT4 com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_vld_ct_eq_1_5 ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_vld_ct[0]), + .I1(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_vld_ct[7]), + .I2(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_vld_ct[8]), + .I3(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_vld_ct[9]), + .O(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_vld_ct_eq_1_5_3267) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_vld_ct_eq_1_6.INIT = 16'h0001; + LUT4 com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_vld_ct_eq_1_6 ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_vld_ct[3]), + .I1(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_vld_ct[4]), + .I2(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_vld_ct[5]), + .I3(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_vld_ct[6]), + .O(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_vld_ct_eq_1_6_3266) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_frm_vld.INIT = 8'h40; + LUT3 com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_frm_vld ( + .I0(com_tlm_u_tlm_rx_ds_dsc), + .I1(com_tlm_u_tlm_rx_ds_eof), + .I2(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_push_3305), + .O(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_frm_vld_3301) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_standard_all_full_un1_wen_i_5.INIT = 8'h84; + LUT3 com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_standard_all_full_un1_wen_i_5 ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_raddr[1]), + .I1(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_wen_i_4), + .I2(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr_p1[1]), + .O(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_wen_i_5) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_standard_all_full_un1_wen_i_6.INIT = 16'h2010; + LUT4 com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_standard_all_full_un1_wen_i_6 ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_raddr[4]), + .I1(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_waddr_p1_3), + .I2(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_wen_i_2), + .I3(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr_p1[4]), + .O(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_wen_i_6) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_standard_all_full_un1_wen_i_7.INIT = 16'h8020; + LUT4 com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_standard_all_full_un1_wen_i_7 ( + .I0(com_tlm_u_tlm_rx_ds_src_rdy), + .I1(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_raddr[9]), + .I2(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_wen_i_1_3261), + .I3(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr_p1[9]), + .O(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_wen_i_7) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_standard_vld_ct_vld_ct25.INIT = 4'h8; + LUT2 com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_standard_vld_ct_vld_ct25 ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_frm_vld_3301), + .I1(plm_link_up_1), + .O(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_vld_ct25) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_overflow_1.INIT = 16'h3F15; + LUT4 com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_overflow_1 ( + .I0(com_tlm_u_tlm_rx_ds_eof), + .I1(com_tlm_u_tlm_rx_ds_src_rdy), + .I2(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_all_full_3264), + .I3(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_frm_vld_3301), + .O(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_overflow_1_i) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_pop.INIT = 4'h8; + LUT2 com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_pop ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_N_9516_i_i), + .I1(com_tlm_u_tlm_rx_vc0_fifo_data_vld_oqr), + .O(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_pop_3307) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr16.INIT = 4'h4; + LUT2 com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr16 ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_overflow_1_i), + .I1(plm_link_up_1), + .O(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr16_3300) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_vld_ct_1_axb_0.INIT = 16'h1DE2; + LUT4 com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_vld_ct_1_axb_0 ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_pop_3302), + .I1(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_vld_ct25), + .I2(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un10_vld_ct[0]), + .I3(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_vld_ct[0]), + .O(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_vld_ct_1_axb_0_3262) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_N_9199_i.INIT = 4'hB; + LUT2 com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_N_9199_i ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_push_3305), + .I1(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_overflow_1_i), + .O(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_N_9199_i_3263) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_standard_all_full_un1_ren_i_2.INIT = 16'h0222; + LUT4 com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_standard_all_full_un1_ren_i_2 ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_pop_3307), + .I1(com_tlm_u_tlm_rx_ds_dsc), + .I2(com_tlm_u_tlm_rx_ds_src_rdy), + .I3(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_all_full_3264), + .O(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_N_9613_2) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_vld_ct_eq_1.INIT = 16'h4000; + LUT4 com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_vld_ct_eq_1 ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_pop_3307), + .I1(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_vld_ct_eq_1_2_3268), + .I2(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_vld_ct_eq_1_5_3267), + .I3(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_vld_ct_eq_1_6_3266), + .O(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_vld_ct_eq_1_3265) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_standard_all_full_N_9613_i.INIT = 16'hD555; + LUT4 com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_standard_all_full_N_9613_i ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_N_9613_2), + .I1(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_wen_i_5), + .I2(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_wen_i_6), + .I3(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_wen_i_7), + .O(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_N_9613_i) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr_qxu_9_.INIT = 8'hD8; + LUT3_L com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr_qxu_9_ ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_overflow_1_i), + .I1(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr[9]), + .I2(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr_bkp[9]), + .LO(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr_qxu[9]) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr_qxu_8_.INIT = 8'hD8; + LUT3_L com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr_qxu_8_ ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_overflow_1_i), + .I1(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr[8]), + .I2(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr_bkp[8]), + .LO(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr_qxu[8]) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr_qxu_7_.INIT = 8'hD8; + LUT3_L com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr_qxu_7_ ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_overflow_1_i), + .I1(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr[7]), + .I2(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr_bkp[7]), + .LO(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr_qxu[7]) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr_qxu_6_.INIT = 8'hD8; + LUT3_L com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr_qxu_6_ ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_overflow_1_i), + .I1(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr[6]), + .I2(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr_bkp[6]), + .LO(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr_qxu[6]) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr_qxu_5_.INIT = 8'hD8; + LUT3_L com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr_qxu_5_ ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_overflow_1_i), + .I1(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr[5]), + .I2(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr_bkp[5]), + .LO(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr_qxu[5]) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr_qxu_4_.INIT = 8'hD8; + LUT3_L com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr_qxu_4_ ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_overflow_1_i), + .I1(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr[4]), + .I2(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr_bkp[4]), + .LO(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr_qxu[4]) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr_qxu_3_.INIT = 8'hD8; + LUT3_L com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr_qxu_3_ ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_overflow_1_i), + .I1(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr[3]), + .I2(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr_bkp[3]), + .LO(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr_qxu[3]) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr_qxu_2_.INIT = 8'hD8; + LUT3_L com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr_qxu_2_ ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_overflow_1_i), + .I1(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr[2]), + .I2(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr_bkp[2]), + .LO(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr_qxu[2]) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr_qxu_1_.INIT = 8'hD8; + LUT3_L com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr_qxu_1_ ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_overflow_1_i), + .I1(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr[1]), + .I2(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr_bkp[1]), + .LO(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr_qxu[1]) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr_qxu_0_.INIT = 8'hD8; + LUT3_L com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr_qxu_0_ ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_overflow_1_i), + .I1(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr[0]), + .I2(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr_bkp[0]), + .LO(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr_qxu[0]) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un3_pkt_ct_axb_6.INIT = 4'h4; + LUT2_L com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un3_pkt_ct_axb_6 ( + .I0(com_tlm_u_tlm_rx_ds_sof), + .I1(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_pkt_ct[6]), + .LO(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un3_pkt_ct_axb_6_3269) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un3_pkt_ct_axb_5.INIT = 4'h4; + LUT2_L com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un3_pkt_ct_axb_5 ( + .I0(com_tlm_u_tlm_rx_ds_sof), + .I1(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_pkt_ct[5]), + .LO(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un3_pkt_ct_axb_5_3270) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un3_pkt_ct_axb_4.INIT = 4'h4; + LUT2_L com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un3_pkt_ct_axb_4 ( + .I0(com_tlm_u_tlm_rx_ds_sof), + .I1(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_pkt_ct[4]), + .LO(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un3_pkt_ct_axb_4_3271) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un3_pkt_ct_axb_3.INIT = 4'h4; + LUT2_L com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un3_pkt_ct_axb_3 ( + .I0(com_tlm_u_tlm_rx_ds_sof), + .I1(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_pkt_ct[3]), + .LO(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un3_pkt_ct_axb_3_3272) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un3_pkt_ct_axb_2.INIT = 4'h4; + LUT2_L com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un3_pkt_ct_axb_2 ( + .I0(com_tlm_u_tlm_rx_ds_sof), + .I1(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_pkt_ct[2]), + .LO(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un3_pkt_ct_axb_2_3273) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un3_pkt_ct_axb_1.INIT = 4'h4; + LUT2_L com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un3_pkt_ct_axb_1 ( + .I0(com_tlm_u_tlm_rx_ds_sof), + .I1(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_pkt_ct[1]), + .LO(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un3_pkt_ct_axb_1_3274) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un3_pkt_ct_m1_axb_6.INIT = 4'h4; + LUT2_L com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un3_pkt_ct_m1_axb_6 ( + .I0(com_tlm_u_tlm_rx_ds_sof), + .I1(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_pkt_ct_m1[6]), + .LO(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un3_pkt_ct_m1_axb_6_3275) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un3_pkt_ct_m1_axb_5.INIT = 4'h4; + LUT2_L com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un3_pkt_ct_m1_axb_5 ( + .I0(com_tlm_u_tlm_rx_ds_sof), + .I1(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_pkt_ct_m1[5]), + .LO(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un3_pkt_ct_m1_axb_5_3276) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un3_pkt_ct_m1_axb_4.INIT = 4'h4; + LUT2_L com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un3_pkt_ct_m1_axb_4 ( + .I0(com_tlm_u_tlm_rx_ds_sof), + .I1(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_pkt_ct_m1[4]), + .LO(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un3_pkt_ct_m1_axb_4_3277) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un3_pkt_ct_m1_axb_3.INIT = 4'h4; + LUT2_L com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un3_pkt_ct_m1_axb_3 ( + .I0(com_tlm_u_tlm_rx_ds_sof), + .I1(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_pkt_ct_m1[3]), + .LO(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un3_pkt_ct_m1_axb_3_3278) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un3_pkt_ct_m1_axb_2.INIT = 4'h4; + LUT2_L com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un3_pkt_ct_m1_axb_2 ( + .I0(com_tlm_u_tlm_rx_ds_sof), + .I1(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_pkt_ct_m1[2]), + .LO(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un3_pkt_ct_m1_axb_2_3279) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un3_pkt_ct_m1_axb_1.INIT = 4'h4; + LUT2_L com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un3_pkt_ct_m1_axb_1 ( + .I0(com_tlm_u_tlm_rx_ds_sof), + .I1(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_pkt_ct_m1[1]), + .LO(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un3_pkt_ct_m1_axb_1_3280) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un8_pkt_ct_m1_i_0_.INIT = 4'hB; + LUT2_L com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un8_pkt_ct_m1_i_0_ ( + .I0(com_tlm_u_tlm_rx_ds_sof), + .I1(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_pkt_ct_m1[0]), + .LO(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un8_pkt_ct_m1_i[0]) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_vld_ct_1_axb_9.INIT = 8'h78; + LUT3_L com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_vld_ct_1_axb_9 ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_pop_3302), + .I1(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_vld_ct25_i), + .I2(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_vld_ct[9]), + .LO(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_vld_ct_1_axb_9_3281) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_vld_ct_1_axb_8.INIT = 8'h78; + LUT3_L com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_vld_ct_1_axb_8 ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_pop_3302), + .I1(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_vld_ct25_i), + .I2(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_vld_ct[8]), + .LO(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_vld_ct_1_axb_8_3282) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_vld_ct_1_axb_7.INIT = 8'h78; + LUT3_L com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_vld_ct_1_axb_7 ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_pop_3302), + .I1(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_vld_ct25_i), + .I2(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_vld_ct[7]), + .LO(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_vld_ct_1_axb_7_3283) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_vld_ct_1_axb_6.INIT = 16'h1DE2; + LUT4_L com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_vld_ct_1_axb_6 ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_pop_3302), + .I1(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_vld_ct25), + .I2(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un10_vld_ct[6]), + .I3(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_vld_ct[6]), + .LO(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_vld_ct_1_axb_6_3284) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_vld_ct_1_axb_5.INIT = 16'h1DE2; + LUT4_L com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_vld_ct_1_axb_5 ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_pop_3302), + .I1(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_vld_ct25), + .I2(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un10_vld_ct[5]), + .I3(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_vld_ct[5]), + .LO(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_vld_ct_1_axb_5_3285) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_vld_ct_1_axb_4.INIT = 16'h1DE2; + LUT4_L com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_vld_ct_1_axb_4 ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_pop_3302), + .I1(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_vld_ct25), + .I2(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un10_vld_ct[4]), + .I3(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_vld_ct[4]), + .LO(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_vld_ct_1_axb_4_3286) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_vld_ct_1_axb_3.INIT = 16'h1DE2; + LUT4_L com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_vld_ct_1_axb_3 ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_pop_3302), + .I1(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_vld_ct25), + .I2(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un10_vld_ct[3]), + .I3(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_vld_ct[3]), + .LO(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_vld_ct_1_axb_3_3287) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_vld_ct_1_axb_2.INIT = 16'h1DE2; + LUT4_L com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_vld_ct_1_axb_2 ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_pop_3302), + .I1(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_vld_ct25), + .I2(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un10_vld_ct[2]), + .I3(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_vld_ct[2]), + .LO(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_vld_ct_1_axb_2_3288) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_vld_ct_1_axb_1.INIT = 16'h1DE2; + LUT4_L com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_vld_ct_1_axb_1 ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_pop_3302), + .I1(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_vld_ct25), + .I2(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un10_vld_ct[1]), + .I3(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_vld_ct[1]), + .LO(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_vld_ct_1_axb_1_3289) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_waddr_p1_1_axb_9.INIT = 8'hD8; + LUT3_L com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_waddr_p1_1_axb_9 ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr16_3300), + .I1(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr_bkp[9]), + .I2(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr_p1[9]), + .LO(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_waddr_p1_1_axb_9_3290) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_waddr_p1_1_axb_8.INIT = 8'hD8; + LUT3_L com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_waddr_p1_1_axb_8 ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr16_3300), + .I1(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr_bkp[8]), + .I2(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr_p1[8]), + .LO(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_waddr_p1_1_axb_8_3291) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_waddr_p1_1_axb_7.INIT = 8'hD8; + LUT3_L com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_waddr_p1_1_axb_7 ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr16_3300), + .I1(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr_bkp[7]), + .I2(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr_p1[7]), + .LO(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_waddr_p1_1_axb_7_3292) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_waddr_p1_1_axb_6.INIT = 8'hD8; + LUT3_L com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_waddr_p1_1_axb_6 ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr16_3300), + .I1(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr_bkp[6]), + .I2(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr_p1[6]), + .LO(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_waddr_p1_1_axb_6_3293) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_waddr_p1_1_axb_5.INIT = 8'hD8; + LUT3_L com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_waddr_p1_1_axb_5 ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr16_3300), + .I1(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr_bkp[5]), + .I2(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr_p1[5]), + .LO(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_waddr_p1_1_axb_5_3294) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_waddr_p1_1_axb_4.INIT = 8'hD8; + LUT3_L com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_waddr_p1_1_axb_4 ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr16_3300), + .I1(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr_bkp[4]), + .I2(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr_p1[4]), + .LO(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_waddr_p1_1_axb_4_3295) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_waddr_p1_1_axb_3.INIT = 8'hD8; + LUT3_L com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_waddr_p1_1_axb_3 ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr16_3300), + .I1(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr_bkp[3]), + .I2(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr_p1[3]), + .LO(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_waddr_p1_1_axb_3_3296) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_waddr_p1_1_axb_2.INIT = 8'hD8; + LUT3_L com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_waddr_p1_1_axb_2 ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr16_3300), + .I1(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr_bkp[2]), + .I2(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr_p1[2]), + .LO(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_waddr_p1_1_axb_2_3297) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_waddr_p1_1_axb_1.INIT = 8'hD8; + LUT3_L com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_waddr_p1_1_axb_1 ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr16_3300), + .I1(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr_bkp[1]), + .I2(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr_p1[1]), + .LO(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_waddr_p1_1_axb_1_3298) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_waddr_p1_1_axb_0.INIT = 8'hD8; + LUT3_L com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_waddr_p1_1_axb_0 ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr16_3300), + .I1(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr_bkp[0]), + .I2(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr_p1[0]), + .LO(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_waddr_p1_1_axb_0_3299) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_standard_vld_ct_vld_ct25_i.INIT = 4'h7; + LUT2 com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_standard_vld_ct_vld_ct25_i ( + .I0(plm_link_up_1), + .I1(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_frm_vld_3301), + .O(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_vld_ct25_i) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_pop.INIT = 8'h2A; + LUT3 com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_pop ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_nxt_vld_3303), + .I1(com_tlm_u_tlm_rx_vc0_fifo_data_vld_oqr), + .I2(com_tlm_u_tlm_rx_vc0_fifo_N_9516_i_i), + .O(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_pop_3302) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_N_9612_i.INIT = 8'hAE; + LUT3 com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_N_9612_i ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_push_3305), + .I1(plm_link_up_1), + .I2(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_overflow_1_i), + .O(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_N_9612_i_3304) + ); + INV com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_N_9616_i ( + .I(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_pop_3307), + .O(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_N_9616_i_3306) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_raddr_qxu_0_0_.INIT = 4'h2; + LUT1_L com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_raddr_qxu_0_0_ ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_raddr[0]), + .LO(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_raddr_qxu[0]) + ); + MULT_AND com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_vld_ct_1_cry_6_ma ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_vld_ct[6]), + .I1(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_VCC_3309), + .LO(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_vld_ct_1_cry_6_ma_3308) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_raddr_qxu_0_9_.INIT = 4'h2; + LUT1_L com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_raddr_qxu_0_9_ ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_raddr[9]), + .LO(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_raddr_qxu[9]) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_raddr_qxu_0_8_.INIT = 4'h2; + LUT1_L com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_raddr_qxu_0_8_ ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_raddr[8]), + .LO(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_raddr_qxu[8]) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_raddr_qxu_0_7_.INIT = 4'h2; + LUT1_L com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_raddr_qxu_0_7_ ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_raddr[7]), + .LO(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_raddr_qxu[7]) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_raddr_qxu_0_6_.INIT = 4'h2; + LUT1_L com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_raddr_qxu_0_6_ ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_raddr[6]), + .LO(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_raddr_qxu[6]) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_raddr_qxu_0_5_.INIT = 4'h2; + LUT1_L com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_raddr_qxu_0_5_ ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_raddr[5]), + .LO(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_raddr_qxu[5]) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_raddr_qxu_0_4_.INIT = 4'h2; + LUT1_L com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_raddr_qxu_0_4_ ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_raddr[4]), + .LO(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_raddr_qxu[4]) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_raddr_qxu_0_3_.INIT = 4'h2; + LUT1_L com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_raddr_qxu_0_3_ ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_raddr[3]), + .LO(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_raddr_qxu[3]) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_raddr_qxu_0_2_.INIT = 4'h2; + LUT1_L com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_raddr_qxu_0_2_ ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_raddr[2]), + .LO(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_raddr_qxu[2]) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_raddr_qxu_0_1_.INIT = 4'h2; + LUT1_L com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_raddr_qxu_0_1_ ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_raddr[1]), + .LO(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_raddr_qxu[1]) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_raddr_s_0_.INIT = 4'h1; + LUT1_L com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_raddr_s_0_ ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_raddr_qxu[0]), + .LO(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_raddr_s[0]) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un8_pkt_ct_0_.INIT = 4'h1; + LUT2_L com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un8_pkt_ct_0_ ( + .I0(com_tlm_u_tlm_rx_ds_sof), + .I1(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_pkt_ct[0]), + .LO(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un8_pkt_ct[0]) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un3_pkt_ct_m1_axb_0.INIT = 4'h4; + LUT2 com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un3_pkt_ct_m1_axb_0 ( + .I0(com_tlm_u_tlm_rx_ds_sof), + .I1(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_pkt_ct_m1[0]), + .O(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un3_pkt_ct_m1_axb_0_3310) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un3_pkt_ct_axb_0.INIT = 4'hE; + LUT2 com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un3_pkt_ct_axb_0 ( + .I0(com_tlm_u_tlm_rx_ds_sof), + .I1(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_pkt_ct[0]), + .O(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un3_pkt_ct_axb_0_3311) + ); + VCC com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_queue_ram_VCC ( + .P(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_queue_ram_VCC_3312) + ); + GND com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_queue_ram_GND ( + .G(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_queue_ram_GND_3313) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_queue_ram_ram_row_0__block_ram_0__ram1024x18_bram.WRITE_MODE_A = "NO_CHANGE"; + RAMB16_S18_S18 com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_queue_ram_ram_row_0__block_ram_0__ram1024x18_bram ( + .ENA(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_queue_ram_VCC_3312), + .ENB(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_queue_ram_N_9618_i_3314), + .SSRA(com_reset_i_q), + .SSRB(com_reset_i_q), + .WEA(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_push_3305), + .WEB(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_queue_ram_GND_3313), + .CLKA(NlwRenamedSig_OI_trn_clk), + .CLKB(NlwRenamedSig_OI_trn_clk), + .ADDRA({com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr[9], com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr[8], +com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr[7], com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr[6], +com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr[5], com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr[4], +com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr[3], com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr[2], +com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr[1], com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr[0]}), + .DOPA({NLW_com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_queue_ram_ram_row_0__block_ram_0__ram1024x18_bram_DOPA_1__UNCONNECTED, +NLW_com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_queue_ram_ram_row_0__block_ram_0__ram1024x18_bram_DOPA_0__UNCONNECTED}), + .ADDRB({com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_raddr[9], com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_raddr[8], +com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_raddr[7], com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_raddr[6], +com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_raddr[5], com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_raddr[4], +com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_raddr[3], com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_raddr[2], +com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_raddr[1], com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_raddr[0]}), + .DOPB({com_tlm_u_tlm_rx_vc0_fifo_data_oqr_17_, com_tlm_u_tlm_rx_vc0_fifo_data_oqr_16_}), + .DIA({com_tlm_u_tlm_rx_ds_d[15], com_tlm_u_tlm_rx_ds_d[14], com_tlm_u_tlm_rx_ds_d[13], com_tlm_u_tlm_rx_ds_d[12], com_tlm_u_tlm_rx_ds_d[11], +com_tlm_u_tlm_rx_ds_d[10], com_tlm_u_tlm_rx_ds_d[9], com_tlm_u_tlm_rx_ds_d[8], com_tlm_u_tlm_rx_ds_d[7], com_tlm_u_tlm_rx_ds_d[6], +com_tlm_u_tlm_rx_ds_d[5], com_tlm_u_tlm_rx_ds_d[4], com_tlm_u_tlm_rx_ds_d[3], com_tlm_u_tlm_rx_ds_d[2], com_tlm_u_tlm_rx_ds_d[1], +com_tlm_u_tlm_rx_ds_d[0]}), + .DIB({com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_queue_ram_GND_3313, com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_queue_ram_GND_3313, +com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_queue_ram_GND_3313, com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_queue_ram_GND_3313, +com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_queue_ram_GND_3313, com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_queue_ram_GND_3313, +com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_queue_ram_GND_3313, com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_queue_ram_GND_3313, +com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_queue_ram_GND_3313, com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_queue_ram_GND_3313, +com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_queue_ram_GND_3313, com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_queue_ram_GND_3313, +com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_queue_ram_GND_3313, com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_queue_ram_GND_3313, +com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_queue_ram_GND_3313, com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_queue_ram_GND_3313}), + .DOA({NLW_com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_queue_ram_ram_row_0__block_ram_0__ram1024x18_bram_DOA_15__UNCONNECTED, +NLW_com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_queue_ram_ram_row_0__block_ram_0__ram1024x18_bram_DOA_14__UNCONNECTED, +NLW_com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_queue_ram_ram_row_0__block_ram_0__ram1024x18_bram_DOA_13__UNCONNECTED, +NLW_com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_queue_ram_ram_row_0__block_ram_0__ram1024x18_bram_DOA_12__UNCONNECTED, +NLW_com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_queue_ram_ram_row_0__block_ram_0__ram1024x18_bram_DOA_11__UNCONNECTED, +NLW_com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_queue_ram_ram_row_0__block_ram_0__ram1024x18_bram_DOA_10__UNCONNECTED, +NLW_com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_queue_ram_ram_row_0__block_ram_0__ram1024x18_bram_DOA_9__UNCONNECTED, +NLW_com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_queue_ram_ram_row_0__block_ram_0__ram1024x18_bram_DOA_8__UNCONNECTED, +NLW_com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_queue_ram_ram_row_0__block_ram_0__ram1024x18_bram_DOA_7__UNCONNECTED, +NLW_com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_queue_ram_ram_row_0__block_ram_0__ram1024x18_bram_DOA_6__UNCONNECTED, +NLW_com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_queue_ram_ram_row_0__block_ram_0__ram1024x18_bram_DOA_5__UNCONNECTED, +NLW_com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_queue_ram_ram_row_0__block_ram_0__ram1024x18_bram_DOA_4__UNCONNECTED, +NLW_com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_queue_ram_ram_row_0__block_ram_0__ram1024x18_bram_DOA_3__UNCONNECTED, +NLW_com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_queue_ram_ram_row_0__block_ram_0__ram1024x18_bram_DOA_2__UNCONNECTED, +NLW_com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_queue_ram_ram_row_0__block_ram_0__ram1024x18_bram_DOA_1__UNCONNECTED, +NLW_com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_queue_ram_ram_row_0__block_ram_0__ram1024x18_bram_DOA_0__UNCONNECTED}), + .DOB({com_tlm_u_tlm_rx_vc0_fifo_data_oqr_15_, com_tlm_u_tlm_rx_vc0_fifo_data_oqr_14_, com_tlm_u_tlm_rx_vc0_fifo_data_oqr_13_, +com_tlm_u_tlm_rx_vc0_fifo_data_oqr_12_, com_tlm_u_tlm_rx_vc0_fifo_data_oqr_11_, com_tlm_u_tlm_rx_vc0_fifo_data_oqr_10_, +com_tlm_u_tlm_rx_vc0_fifo_data_oqr_9_, com_tlm_u_tlm_rx_vc0_fifo_data_oqr_8_, com_tlm_u_tlm_rx_vc0_fifo_data_oqr_7_, +com_tlm_u_tlm_rx_vc0_fifo_data_oqr_6_, com_tlm_u_tlm_rx_vc0_fifo_data_oqr_5_, com_tlm_u_tlm_rx_vc0_fifo_data_oqr_4_, +com_tlm_u_tlm_rx_vc0_fifo_data_oqr_3_, com_tlm_u_tlm_rx_vc0_fifo_data_oqr_2_, com_tlm_u_tlm_rx_vc0_fifo_data_oqr_1_, +com_tlm_u_tlm_rx_vc0_fifo_data_oqr_0_}), + .DIPA({com_tlm_u_tlm_rx_ds_d[17], com_tlm_u_tlm_rx_ds_d[16]}), + .DIPB({com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_queue_ram_GND_3313, com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_queue_ram_GND_3313}) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_queue_ram_ram_row_0__block_ram_1__ram1024x18_bram.WRITE_MODE_A = "NO_CHANGE"; + RAMB16_S18_S18 com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_queue_ram_ram_row_0__block_ram_1__ram1024x18_bram ( + .ENA(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_queue_ram_VCC_3312), + .ENB(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_queue_ram_N_9618_i_3314), + .SSRA(com_reset_i_q), + .SSRB(com_reset_i_q), + .WEA(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_push_3305), + .WEB(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_queue_ram_GND_3313), + .CLKA(NlwRenamedSig_OI_trn_clk), + .CLKB(NlwRenamedSig_OI_trn_clk), + .ADDRA({com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr[9], com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr[8], +com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr[7], com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr[6], +com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr[5], com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr[4], +com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr[3], com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr[2], +com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr[1], com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr[0]}), + .DOPA({NLW_com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_queue_ram_ram_row_0__block_ram_1__ram1024x18_bram_DOPA_1__UNCONNECTED, +NLW_com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_queue_ram_ram_row_0__block_ram_1__ram1024x18_bram_DOPA_0__UNCONNECTED}), + .ADDRB({com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_raddr[9], com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_raddr[8], +com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_raddr[7], com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_raddr[6], +com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_raddr[5], com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_raddr[4], +com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_raddr[3], com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_raddr[2], +com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_raddr[1], com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_raddr[0]}), + .DOPB({com_tlm_u_tlm_rx_vc0_fifo_data_oqr_35_, com_tlm_u_tlm_rx_vc0_fifo_data_oqr_34_}), + .DIA({com_tlm_u_tlm_rx_ds_d[33], com_tlm_u_tlm_rx_ds_d[32], com_tlm_u_tlm_rx_ds_d[31], com_tlm_u_tlm_rx_ds_d[30], com_tlm_u_tlm_rx_ds_d[29], +com_tlm_u_tlm_rx_ds_d[28], com_tlm_u_tlm_rx_ds_d[27], com_tlm_u_tlm_rx_ds_d[26], com_tlm_u_tlm_rx_ds_d[25], com_tlm_u_tlm_rx_ds_d[24], +com_tlm_u_tlm_rx_ds_d[23], com_tlm_u_tlm_rx_ds_d[22], com_tlm_u_tlm_rx_ds_d[21], com_tlm_u_tlm_rx_ds_d[20], com_tlm_u_tlm_rx_ds_d[19], +com_tlm_u_tlm_rx_ds_d[18]}), + .DIB({com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_queue_ram_GND_3313, com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_queue_ram_GND_3313, +com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_queue_ram_GND_3313, com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_queue_ram_GND_3313, +com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_queue_ram_GND_3313, com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_queue_ram_GND_3313, +com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_queue_ram_GND_3313, com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_queue_ram_GND_3313, +com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_queue_ram_GND_3313, com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_queue_ram_GND_3313, +com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_queue_ram_GND_3313, com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_queue_ram_GND_3313, +com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_queue_ram_GND_3313, com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_queue_ram_GND_3313, +com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_queue_ram_GND_3313, com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_queue_ram_GND_3313}), + .DOA({NLW_com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_queue_ram_ram_row_0__block_ram_1__ram1024x18_bram_DOA_15__UNCONNECTED, +NLW_com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_queue_ram_ram_row_0__block_ram_1__ram1024x18_bram_DOA_14__UNCONNECTED, +NLW_com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_queue_ram_ram_row_0__block_ram_1__ram1024x18_bram_DOA_13__UNCONNECTED, +NLW_com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_queue_ram_ram_row_0__block_ram_1__ram1024x18_bram_DOA_12__UNCONNECTED, +NLW_com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_queue_ram_ram_row_0__block_ram_1__ram1024x18_bram_DOA_11__UNCONNECTED, +NLW_com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_queue_ram_ram_row_0__block_ram_1__ram1024x18_bram_DOA_10__UNCONNECTED, +NLW_com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_queue_ram_ram_row_0__block_ram_1__ram1024x18_bram_DOA_9__UNCONNECTED, +NLW_com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_queue_ram_ram_row_0__block_ram_1__ram1024x18_bram_DOA_8__UNCONNECTED, +NLW_com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_queue_ram_ram_row_0__block_ram_1__ram1024x18_bram_DOA_7__UNCONNECTED, +NLW_com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_queue_ram_ram_row_0__block_ram_1__ram1024x18_bram_DOA_6__UNCONNECTED, +NLW_com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_queue_ram_ram_row_0__block_ram_1__ram1024x18_bram_DOA_5__UNCONNECTED, +NLW_com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_queue_ram_ram_row_0__block_ram_1__ram1024x18_bram_DOA_4__UNCONNECTED, +NLW_com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_queue_ram_ram_row_0__block_ram_1__ram1024x18_bram_DOA_3__UNCONNECTED, +NLW_com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_queue_ram_ram_row_0__block_ram_1__ram1024x18_bram_DOA_2__UNCONNECTED, +NLW_com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_queue_ram_ram_row_0__block_ram_1__ram1024x18_bram_DOA_1__UNCONNECTED, +NLW_com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_queue_ram_ram_row_0__block_ram_1__ram1024x18_bram_DOA_0__UNCONNECTED}), + .DOB({com_tlm_u_tlm_rx_vc0_fifo_data_oqr_33_, com_tlm_u_tlm_rx_vc0_fifo_data_oqr_32_, com_tlm_u_tlm_rx_vc0_fifo_data_oqr_31_, +com_tlm_u_tlm_rx_vc0_fifo_data_oqr_30_, com_tlm_u_tlm_rx_vc0_fifo_data_oqr_29_, com_tlm_u_tlm_rx_vc0_fifo_data_oqr_28_, +com_tlm_u_tlm_rx_vc0_fifo_data_oqr_27_, com_tlm_u_tlm_rx_vc0_fifo_data_oqr_26_, com_tlm_u_tlm_rx_vc0_fifo_data_oqr_25_, +com_tlm_u_tlm_rx_vc0_fifo_data_oqr_24_, com_tlm_u_tlm_rx_vc0_fifo_data_oqr_23_, com_tlm_u_tlm_rx_vc0_fifo_data_oqr_22_, +com_tlm_u_tlm_rx_vc0_fifo_data_oqr_21_, com_tlm_u_tlm_rx_vc0_fifo_data_oqr_20_, com_tlm_u_tlm_rx_vc0_fifo_data_oqr_19_, +com_tlm_u_tlm_rx_vc0_fifo_data_oqr_18_}), + .DIPA({com_tlm_u_tlm_rx_ds_d[35], com_tlm_u_tlm_rx_ds_d[34]}), + .DIPB({com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_queue_ram_GND_3313, com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_queue_ram_GND_3313}) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_queue_ram_ram_row_0__block_ram_2__ram1024x18_bram.WRITE_MODE_A = "NO_CHANGE"; + RAMB16_S18_S18 com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_queue_ram_ram_row_0__block_ram_2__ram1024x18_bram ( + .ENA(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_queue_ram_VCC_3312), + .ENB(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_queue_ram_N_9618_i_3314), + .SSRA(com_reset_i_q), + .SSRB(com_reset_i_q), + .WEA(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_push_3305), + .WEB(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_queue_ram_GND_3313), + .CLKA(NlwRenamedSig_OI_trn_clk), + .CLKB(NlwRenamedSig_OI_trn_clk), + .ADDRA({com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr[9], com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr[8], +com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr[7], com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr[6], +com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr[5], com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr[4], +com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr[3], com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr[2], +com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr[1], com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr[0]}), + .DOPA({NLW_com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_queue_ram_ram_row_0__block_ram_2__ram1024x18_bram_DOPA_1__UNCONNECTED, +NLW_com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_queue_ram_ram_row_0__block_ram_2__ram1024x18_bram_DOPA_0__UNCONNECTED}), + .ADDRB({com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_raddr[9], com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_raddr[8], +com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_raddr[7], com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_raddr[6], +com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_raddr[5], com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_raddr[4], +com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_raddr[3], com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_raddr[2], +com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_raddr[1], com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_raddr[0]}), + .DOPB({com_tlm_u_tlm_rx_vc0_fifo_data_oqr_53_, com_tlm_u_tlm_rx_vc0_fifo_data_oqr_52_}), + .DIA({com_tlm_u_tlm_rx_ds_d[51], com_tlm_u_tlm_rx_ds_d[50], com_tlm_u_tlm_rx_ds_d[49], com_tlm_u_tlm_rx_ds_d[48], com_tlm_u_tlm_rx_ds_d[47], +com_tlm_u_tlm_rx_ds_d[46], com_tlm_u_tlm_rx_ds_d[45], com_tlm_u_tlm_rx_ds_d[44], com_tlm_u_tlm_rx_ds_d[43], com_tlm_u_tlm_rx_ds_d[42], +com_tlm_u_tlm_rx_ds_d[41], com_tlm_u_tlm_rx_ds_d[40], com_tlm_u_tlm_rx_ds_d[39], com_tlm_u_tlm_rx_ds_d[38], com_tlm_u_tlm_rx_ds_d[37], +com_tlm_u_tlm_rx_ds_d[36]}), + .DIB({com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_queue_ram_GND_3313, com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_queue_ram_GND_3313, +com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_queue_ram_GND_3313, com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_queue_ram_GND_3313, +com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_queue_ram_GND_3313, com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_queue_ram_GND_3313, +com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_queue_ram_GND_3313, com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_queue_ram_GND_3313, +com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_queue_ram_GND_3313, com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_queue_ram_GND_3313, +com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_queue_ram_GND_3313, com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_queue_ram_GND_3313, +com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_queue_ram_GND_3313, com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_queue_ram_GND_3313, +com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_queue_ram_GND_3313, com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_queue_ram_GND_3313}), + .DOA({NLW_com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_queue_ram_ram_row_0__block_ram_2__ram1024x18_bram_DOA_15__UNCONNECTED, +NLW_com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_queue_ram_ram_row_0__block_ram_2__ram1024x18_bram_DOA_14__UNCONNECTED, +NLW_com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_queue_ram_ram_row_0__block_ram_2__ram1024x18_bram_DOA_13__UNCONNECTED, +NLW_com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_queue_ram_ram_row_0__block_ram_2__ram1024x18_bram_DOA_12__UNCONNECTED, +NLW_com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_queue_ram_ram_row_0__block_ram_2__ram1024x18_bram_DOA_11__UNCONNECTED, +NLW_com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_queue_ram_ram_row_0__block_ram_2__ram1024x18_bram_DOA_10__UNCONNECTED, +NLW_com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_queue_ram_ram_row_0__block_ram_2__ram1024x18_bram_DOA_9__UNCONNECTED, +NLW_com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_queue_ram_ram_row_0__block_ram_2__ram1024x18_bram_DOA_8__UNCONNECTED, +NLW_com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_queue_ram_ram_row_0__block_ram_2__ram1024x18_bram_DOA_7__UNCONNECTED, +NLW_com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_queue_ram_ram_row_0__block_ram_2__ram1024x18_bram_DOA_6__UNCONNECTED, +NLW_com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_queue_ram_ram_row_0__block_ram_2__ram1024x18_bram_DOA_5__UNCONNECTED, +NLW_com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_queue_ram_ram_row_0__block_ram_2__ram1024x18_bram_DOA_4__UNCONNECTED, +NLW_com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_queue_ram_ram_row_0__block_ram_2__ram1024x18_bram_DOA_3__UNCONNECTED, +NLW_com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_queue_ram_ram_row_0__block_ram_2__ram1024x18_bram_DOA_2__UNCONNECTED, +NLW_com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_queue_ram_ram_row_0__block_ram_2__ram1024x18_bram_DOA_1__UNCONNECTED, +NLW_com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_queue_ram_ram_row_0__block_ram_2__ram1024x18_bram_DOA_0__UNCONNECTED}), + .DOB({com_tlm_u_tlm_rx_vc0_fifo_data_oqr_51_, com_tlm_u_tlm_rx_vc0_fifo_data_oqr_50_, com_tlm_u_tlm_rx_vc0_fifo_data_oqr_49_, +com_tlm_u_tlm_rx_vc0_fifo_data_oqr_48_, com_tlm_u_tlm_rx_vc0_fifo_data_oqr_47_, com_tlm_u_tlm_rx_vc0_fifo_ep_oqr, +com_tlm_u_tlm_rx_vc0_fifo_data_oqr_45_, com_tlm_u_tlm_rx_vc0_fifo_data_oqr_44_, com_tlm_u_tlm_rx_vc0_fifo_data_oqr_43_, +com_tlm_u_tlm_rx_vc0_fifo_data_oqr_42_, com_tlm_u_tlm_rx_vc0_fifo_data_oqr_41_, com_tlm_u_tlm_rx_vc0_fifo_data_oqr_40_, +com_tlm_u_tlm_rx_vc0_fifo_data_oqr_39_, com_tlm_u_tlm_rx_vc0_fifo_data_oqr_38_, com_tlm_u_tlm_rx_vc0_fifo_data_oqr_37_, +com_tlm_u_tlm_rx_vc0_fifo_data_oqr_36_}), + .DIPA({com_tlm_u_tlm_rx_ds_d[53], com_tlm_u_tlm_rx_ds_d[52]}), + .DIPB({com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_queue_ram_GND_3313, com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_queue_ram_GND_3313}) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_queue_ram_ram_row_0__block_ram_3__ram1024x18_bram.WRITE_MODE_A = "NO_CHANGE"; + RAMB16_S18_S18 com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_queue_ram_ram_row_0__block_ram_3__ram1024x18_bram ( + .ENA(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_queue_ram_VCC_3312), + .ENB(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_queue_ram_N_9618_i_3314), + .SSRA(com_reset_i_q), + .SSRB(com_reset_i_q), + .WEA(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_push_3305), + .WEB(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_queue_ram_GND_3313), + .CLKA(NlwRenamedSig_OI_trn_clk), + .CLKB(NlwRenamedSig_OI_trn_clk), + .ADDRA({com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr[9], com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr[8], +com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr[7], com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr[6], +com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr[5], com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr[4], +com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr[3], com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr[2], +com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr[1], com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr[0]}), + .DOPA({NLW_com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_queue_ram_ram_row_0__block_ram_3__ram1024x18_bram_DOPA_1__UNCONNECTED, +NLW_com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_queue_ram_ram_row_0__block_ram_3__ram1024x18_bram_DOPA_0__UNCONNECTED}), + .ADDRB({com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_raddr[9], com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_raddr[8], +com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_raddr[7], com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_raddr[6], +com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_raddr[5], com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_raddr[4], +com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_raddr[3], com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_raddr[2], +com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_raddr[1], com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_raddr[0]}), + .DOPB({NLW_com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_queue_ram_ram_row_0__block_ram_3__ram1024x18_bram_DOPB_1__UNCONNECTED, +NLW_com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_queue_ram_ram_row_0__block_ram_3__ram1024x18_bram_DOPB_0__UNCONNECTED}), + .DIA({com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_queue_ram_GND_3313, com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_queue_ram_GND_3313, +com_tlm_u_tlm_rx_ds_rem, com_tlm_u_tlm_rx_ds_cpl, com_tlm_u_tlm_rx_ds_eof, com_tlm_u_tlm_rx_ds_sof, com_tlm_u_tlm_rx_ds_d[63], +com_tlm_u_tlm_rx_ds_d[62], com_tlm_u_tlm_rx_ds_d[61], com_tlm_u_tlm_rx_ds_d[60], com_tlm_u_tlm_rx_ds_d[59], com_tlm_u_tlm_rx_ds_d[58], +com_tlm_u_tlm_rx_ds_d[57], com_tlm_u_tlm_rx_ds_d[56], com_tlm_u_tlm_rx_ds_d[55], com_tlm_u_tlm_rx_ds_d[54]}), + .DIB({com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_queue_ram_GND_3313, com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_queue_ram_GND_3313, +com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_queue_ram_GND_3313, com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_queue_ram_GND_3313, +com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_queue_ram_GND_3313, com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_queue_ram_GND_3313, +com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_queue_ram_GND_3313, com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_queue_ram_GND_3313, +com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_queue_ram_GND_3313, com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_queue_ram_GND_3313, +com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_queue_ram_GND_3313, com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_queue_ram_GND_3313, +com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_queue_ram_GND_3313, com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_queue_ram_GND_3313, +com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_queue_ram_GND_3313, com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_queue_ram_GND_3313}), + .DOA({NLW_com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_queue_ram_ram_row_0__block_ram_3__ram1024x18_bram_DOA_15__UNCONNECTED, +NLW_com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_queue_ram_ram_row_0__block_ram_3__ram1024x18_bram_DOA_14__UNCONNECTED, +NLW_com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_queue_ram_ram_row_0__block_ram_3__ram1024x18_bram_DOA_13__UNCONNECTED, +NLW_com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_queue_ram_ram_row_0__block_ram_3__ram1024x18_bram_DOA_12__UNCONNECTED, +NLW_com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_queue_ram_ram_row_0__block_ram_3__ram1024x18_bram_DOA_11__UNCONNECTED, +NLW_com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_queue_ram_ram_row_0__block_ram_3__ram1024x18_bram_DOA_10__UNCONNECTED, +NLW_com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_queue_ram_ram_row_0__block_ram_3__ram1024x18_bram_DOA_9__UNCONNECTED, +NLW_com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_queue_ram_ram_row_0__block_ram_3__ram1024x18_bram_DOA_8__UNCONNECTED, +NLW_com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_queue_ram_ram_row_0__block_ram_3__ram1024x18_bram_DOA_7__UNCONNECTED, +NLW_com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_queue_ram_ram_row_0__block_ram_3__ram1024x18_bram_DOA_6__UNCONNECTED, +NLW_com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_queue_ram_ram_row_0__block_ram_3__ram1024x18_bram_DOA_5__UNCONNECTED, +NLW_com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_queue_ram_ram_row_0__block_ram_3__ram1024x18_bram_DOA_4__UNCONNECTED, +NLW_com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_queue_ram_ram_row_0__block_ram_3__ram1024x18_bram_DOA_3__UNCONNECTED, +NLW_com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_queue_ram_ram_row_0__block_ram_3__ram1024x18_bram_DOA_2__UNCONNECTED, +NLW_com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_queue_ram_ram_row_0__block_ram_3__ram1024x18_bram_DOA_1__UNCONNECTED, +NLW_com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_queue_ram_ram_row_0__block_ram_3__ram1024x18_bram_DOA_0__UNCONNECTED}), + .DOB({NLW_com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_queue_ram_ram_row_0__block_ram_3__ram1024x18_bram_DOB_15__UNCONNECTED, +NLW_com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_queue_ram_ram_row_0__block_ram_3__ram1024x18_bram_DOB_14__UNCONNECTED, +com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_ram_dout[67], com_tlm_u_tlm_rx_vc0_fifo_ram_dout[66], com_tlm_u_tlm_rx_vc0_fifo_ram_dout[65], +com_tlm_u_tlm_rx_vc0_fifo_ram_dout[64], com_tlm_u_tlm_rx_vc0_fifo_data_oqr_63_, com_tlm_u_tlm_rx_vc0_fifo_data_oqr_62_, +com_tlm_u_tlm_rx_vc0_fifo_data_oqr_61_, com_tlm_u_tlm_rx_vc0_fifo_data_oqr_60_, com_tlm_u_tlm_rx_vc0_fifo_data_oqr_59_, +com_tlm_u_tlm_rx_vc0_fifo_data_oqr_58_, com_tlm_u_tlm_rx_vc0_fifo_data_oqr_57_, com_tlm_u_tlm_rx_vc0_fifo_data_oqr_56_, +com_tlm_u_tlm_rx_vc0_fifo_data_oqr_55_, com_tlm_u_tlm_rx_vc0_fifo_data_oqr_54_}), + .DIPA({com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_queue_ram_GND_3313, com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_queue_ram_GND_3313}), + .DIPB({com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_queue_ram_GND_3313, com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_queue_ram_GND_3313}) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_queue_ram_N_9618_i.INIT = 4'hE; + LUT2 com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_queue_ram_N_9618_i ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_pop_3302), + .I1(com_reset_i_q), + .O(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_queue_ram_N_9618_i_3314) + ); + VCC com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_VCC ( + .P(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_VCC_3334) + ); + GND com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_GND ( + .G(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_GND_3315) + ); + SRLC16E com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_srlrow_3__srlcol_4__srlinst ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_wen_aux_oq_3091), + .D(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_shift_in[31]), + .Q(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_shift_tap[31]), + .CLK(NlwRenamedSig_OI_trn_clk), + .Q15(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_shift_in[40]), + .A0(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_lo[0]), + .A1(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_lo[1]), + .A2(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_lo[2]), + .A3(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_lo[3]) + ); + SRLC16E com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_srlrow_2__srlcol_0__srlinst ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_wen_aux_oq_3091), + .D(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_shift_in[18]), + .Q(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_shift_tap[18]), + .CLK(NlwRenamedSig_OI_trn_clk), + .Q15(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_shift_in[27]), + .A0(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_lo[0]), + .A1(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_lo[1]), + .A2(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_lo[2]), + .A3(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_lo[3]) + ); + SRLC16E com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_srlrow_1__srlcol_6__srlinst ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_wen_aux_oq_3091), + .D(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_shift_in[15]), + .Q(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_shift_tap[15]), + .CLK(NlwRenamedSig_OI_trn_clk), + .Q15(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_shift_in[24]), + .A0(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_lo[0]), + .A1(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_lo[1]), + .A2(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_lo[2]), + .A3(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_lo[3]) + ); + SRLC16E com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_srlrow_4__srlcol_8__srlinst ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_wen_aux_oq_3091), + .D(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_shift_in[44]), + .Q(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_shift_tap[44]), + .CLK(NlwRenamedSig_OI_trn_clk), + .Q15(NLW_com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_srlrow_4__srlcol_8__srlinst_Q15_UNCONNECTED), + .A0(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_lo[0]), + .A1(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_lo[1]), + .A2(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_lo[2]), + .A3(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_lo[3]) + ); + SRLC16E com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_srlrow_4__srlcol_5__srlinst ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_wen_aux_oq_3091), + .D(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_shift_in[41]), + .Q(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_shift_tap[41]), + .CLK(NlwRenamedSig_OI_trn_clk), + .Q15(NLW_com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_srlrow_4__srlcol_5__srlinst_Q15_UNCONNECTED), + .A0(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_lo[0]), + .A1(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_lo[1]), + .A2(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_lo[2]), + .A3(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_lo[3]) + ); + SRLC16E com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_srlrow_4__srlcol_6__srlinst ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_wen_aux_oq_3091), + .D(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_shift_in[42]), + .Q(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_shift_tap[42]), + .CLK(NlwRenamedSig_OI_trn_clk), + .Q15(NLW_com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_srlrow_4__srlcol_6__srlinst_Q15_UNCONNECTED), + .A0(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_lo[0]), + .A1(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_lo[1]), + .A2(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_lo[2]), + .A3(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_lo[3]) + ); + SRLC16E com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_srlrow_4__srlcol_7__srlinst ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_wen_aux_oq_3091), + .D(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_shift_in[43]), + .Q(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_shift_tap[43]), + .CLK(NlwRenamedSig_OI_trn_clk), + .Q15(NLW_com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_srlrow_4__srlcol_7__srlinst_Q15_UNCONNECTED), + .A0(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_lo[0]), + .A1(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_lo[1]), + .A2(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_lo[2]), + .A3(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_lo[3]) + ); + SRLC16E com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_srlrow_4__srlcol_4__srlinst ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_wen_aux_oq_3091), + .D(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_shift_in[40]), + .Q(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_shift_tap[40]), + .CLK(NlwRenamedSig_OI_trn_clk), + .Q15(NLW_com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_srlrow_4__srlcol_4__srlinst_Q15_UNCONNECTED), + .A0(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_lo[0]), + .A1(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_lo[1]), + .A2(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_lo[2]), + .A3(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_lo[3]) + ); + SRLC16E com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_srlrow_1__srlcol_7__srlinst ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_wen_aux_oq_3091), + .D(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_shift_in[16]), + .Q(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_shift_tap[16]), + .CLK(NlwRenamedSig_OI_trn_clk), + .Q15(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_shift_in[25]), + .A0(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_lo[0]), + .A1(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_lo[1]), + .A2(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_lo[2]), + .A3(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_lo[3]) + ); + SRLC16E com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_srlrow_0__srlcol_3__srlinst ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_wen_aux_oq_3091), + .D(com_tlm_u_tlm_rx_vc0_fifo_aux_in[3]), + .Q(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_shift_tap[3]), + .CLK(NlwRenamedSig_OI_trn_clk), + .Q15(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_shift_in[12]), + .A0(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_lo[0]), + .A1(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_lo[1]), + .A2(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_lo[2]), + .A3(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_lo[3]) + ); + SRLC16E com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_srlrow_3__srlcol_3__srlinst ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_wen_aux_oq_3091), + .D(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_shift_in[30]), + .Q(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_shift_tap[30]), + .CLK(NlwRenamedSig_OI_trn_clk), + .Q15(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_shift_in[39]), + .A0(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_lo[0]), + .A1(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_lo[1]), + .A2(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_lo[2]), + .A3(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_lo[3]) + ); + SRLC16E com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_srlrow_1__srlcol_8__srlinst ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_wen_aux_oq_3091), + .D(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_shift_in[17]), + .Q(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_shift_tap[17]), + .CLK(NlwRenamedSig_OI_trn_clk), + .Q15(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_shift_in[26]), + .A0(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_lo[0]), + .A1(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_lo[1]), + .A2(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_lo[2]), + .A3(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_lo[3]) + ); + SRLC16E com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_srlrow_0__srlcol_4__srlinst ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_wen_aux_oq_3091), + .D(com_tlm_u_tlm_rx_vc0_fifo_aux_in[4]), + .Q(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_shift_tap[4]), + .CLK(NlwRenamedSig_OI_trn_clk), + .Q15(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_shift_in[13]), + .A0(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_lo[0]), + .A1(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_lo[1]), + .A2(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_lo[2]), + .A3(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_lo[3]) + ); + SRLC16E com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_srlrow_3__srlcol_2__srlinst ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_wen_aux_oq_3091), + .D(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_shift_in[29]), + .Q(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_shift_tap[29]), + .CLK(NlwRenamedSig_OI_trn_clk), + .Q15(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_shift_in[38]), + .A0(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_lo[0]), + .A1(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_lo[1]), + .A2(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_lo[2]), + .A3(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_lo[3]) + ); + SRLC16E com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_srlrow_0__srlcol_2__srlinst ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_wen_aux_oq_3091), + .D(com_tlm_u_tlm_rx_vc0_fifo_aux_in[2]), + .Q(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_shift_tap[2]), + .CLK(NlwRenamedSig_OI_trn_clk), + .Q15(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_shift_in[11]), + .A0(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_lo[0]), + .A1(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_lo[1]), + .A2(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_lo[2]), + .A3(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_lo[3]) + ); + SRLC16E com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_srlrow_0__srlcol_5__srlinst ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_wen_aux_oq_3091), + .D(com_tlm_u_tlm_rx_vc0_fifo_aux_in[5]), + .Q(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_shift_tap[5]), + .CLK(NlwRenamedSig_OI_trn_clk), + .Q15(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_shift_in[14]), + .A0(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_lo[0]), + .A1(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_lo[1]), + .A2(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_lo[2]), + .A3(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_lo[3]) + ); + SRLC16E com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_srlrow_3__srlcol_5__srlinst ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_wen_aux_oq_3091), + .D(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_shift_in[32]), + .Q(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_shift_tap[32]), + .CLK(NlwRenamedSig_OI_trn_clk), + .Q15(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_shift_in[41]), + .A0(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_lo[0]), + .A1(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_lo[1]), + .A2(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_lo[2]), + .A3(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_lo[3]) + ); + SRLC16E com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_srlrow_2__srlcol_1__srlinst ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_wen_aux_oq_3091), + .D(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_shift_in[19]), + .Q(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_shift_tap[19]), + .CLK(NlwRenamedSig_OI_trn_clk), + .Q15(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_shift_in[28]), + .A0(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_lo[0]), + .A1(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_lo[1]), + .A2(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_lo[2]), + .A3(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_lo[3]) + ); + SRLC16E com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_srlrow_0__srlcol_6__srlinst ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_wen_aux_oq_3091), + .D(com_tlm_u_tlm_rx_vc0_fifo_aux_in[6]), + .Q(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_shift_tap[6]), + .CLK(NlwRenamedSig_OI_trn_clk), + .Q15(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_shift_in[15]), + .A0(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_lo[0]), + .A1(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_lo[1]), + .A2(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_lo[2]), + .A3(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_lo[3]) + ); + SRLC16E com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_srlrow_3__srlcol_6__srlinst ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_wen_aux_oq_3091), + .D(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_shift_in[33]), + .Q(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_shift_tap[33]), + .CLK(NlwRenamedSig_OI_trn_clk), + .Q15(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_shift_in[42]), + .A0(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_lo[0]), + .A1(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_lo[1]), + .A2(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_lo[2]), + .A3(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_lo[3]) + ); + SRLC16E com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_srlrow_2__srlcol_2__srlinst ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_wen_aux_oq_3091), + .D(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_shift_in[20]), + .Q(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_shift_tap[20]), + .CLK(NlwRenamedSig_OI_trn_clk), + .Q15(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_shift_in[29]), + .A0(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_lo[0]), + .A1(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_lo[1]), + .A2(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_lo[2]), + .A3(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_lo[3]) + ); + SRLC16E com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_srlrow_0__srlcol_7__srlinst ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_wen_aux_oq_3091), + .D(com_tlm_u_tlm_rx_vc0_fifo_aux_in[7]), + .Q(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_shift_tap[7]), + .CLK(NlwRenamedSig_OI_trn_clk), + .Q15(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_shift_in[16]), + .A0(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_lo[0]), + .A1(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_lo[1]), + .A2(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_lo[2]), + .A3(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_lo[3]) + ); + SRLC16E com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_srlrow_3__srlcol_7__srlinst ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_wen_aux_oq_3091), + .D(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_shift_in[34]), + .Q(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_shift_tap[34]), + .CLK(NlwRenamedSig_OI_trn_clk), + .Q15(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_shift_in[43]), + .A0(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_lo[0]), + .A1(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_lo[1]), + .A2(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_lo[2]), + .A3(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_lo[3]) + ); + SRLC16E com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_srlrow_2__srlcol_3__srlinst ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_wen_aux_oq_3091), + .D(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_shift_in[21]), + .Q(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_shift_tap[21]), + .CLK(NlwRenamedSig_OI_trn_clk), + .Q15(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_shift_in[30]), + .A0(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_lo[0]), + .A1(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_lo[1]), + .A2(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_lo[2]), + .A3(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_lo[3]) + ); + SRLC16E com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_srlrow_0__srlcol_8__srlinst ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_wen_aux_oq_3091), + .D(com_tlm_u_tlm_rx_vc0_fifo_aux_in[8]), + .Q(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_shift_tap[8]), + .CLK(NlwRenamedSig_OI_trn_clk), + .Q15(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_shift_in[17]), + .A0(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_lo[0]), + .A1(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_lo[1]), + .A2(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_lo[2]), + .A3(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_lo[3]) + ); + SRLC16E com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_srlrow_3__srlcol_8__srlinst ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_wen_aux_oq_3091), + .D(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_shift_in[35]), + .Q(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_shift_tap[35]), + .CLK(NlwRenamedSig_OI_trn_clk), + .Q15(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_shift_in[44]), + .A0(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_lo[0]), + .A1(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_lo[1]), + .A2(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_lo[2]), + .A3(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_lo[3]) + ); + SRLC16E com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_srlrow_2__srlcol_4__srlinst ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_wen_aux_oq_3091), + .D(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_shift_in[22]), + .Q(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_shift_tap[22]), + .CLK(NlwRenamedSig_OI_trn_clk), + .Q15(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_shift_in[31]), + .A0(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_lo[0]), + .A1(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_lo[1]), + .A2(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_lo[2]), + .A3(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_lo[3]) + ); + SRLC16E com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_srlrow_1__srlcol_0__srlinst ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_wen_aux_oq_3091), + .D(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_shift_in[9]), + .Q(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_shift_tap[9]), + .CLK(NlwRenamedSig_OI_trn_clk), + .Q15(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_shift_in[18]), + .A0(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_lo[0]), + .A1(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_lo[1]), + .A2(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_lo[2]), + .A3(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_lo[3]) + ); + SRLC16E com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_srlrow_4__srlcol_0__srlinst ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_wen_aux_oq_3091), + .D(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_shift_in[36]), + .Q(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_shift_tap[36]), + .CLK(NlwRenamedSig_OI_trn_clk), + .Q15(NLW_com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_srlrow_4__srlcol_0__srlinst_Q15_UNCONNECTED), + .A0(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_lo[0]), + .A1(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_lo[1]), + .A2(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_lo[2]), + .A3(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_lo[3]) + ); + SRLC16E com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_srlrow_2__srlcol_5__srlinst ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_wen_aux_oq_3091), + .D(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_shift_in[23]), + .Q(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_shift_tap[23]), + .CLK(NlwRenamedSig_OI_trn_clk), + .Q15(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_shift_in[32]), + .A0(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_lo[0]), + .A1(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_lo[1]), + .A2(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_lo[2]), + .A3(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_lo[3]) + ); + SRLC16E com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_srlrow_1__srlcol_1__srlinst ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_wen_aux_oq_3091), + .D(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_shift_in[10]), + .Q(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_shift_tap[10]), + .CLK(NlwRenamedSig_OI_trn_clk), + .Q15(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_shift_in[19]), + .A0(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_lo[0]), + .A1(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_lo[1]), + .A2(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_lo[2]), + .A3(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_lo[3]) + ); + SRLC16E com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_srlrow_4__srlcol_1__srlinst ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_wen_aux_oq_3091), + .D(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_shift_in[37]), + .Q(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_shift_tap[37]), + .CLK(NlwRenamedSig_OI_trn_clk), + .Q15(NLW_com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_srlrow_4__srlcol_1__srlinst_Q15_UNCONNECTED), + .A0(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_lo[0]), + .A1(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_lo[1]), + .A2(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_lo[2]), + .A3(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_lo[3]) + ); + SRLC16E com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_srlrow_2__srlcol_6__srlinst ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_wen_aux_oq_3091), + .D(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_shift_in[24]), + .Q(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_shift_tap[24]), + .CLK(NlwRenamedSig_OI_trn_clk), + .Q15(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_shift_in[33]), + .A0(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_lo[0]), + .A1(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_lo[1]), + .A2(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_lo[2]), + .A3(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_lo[3]) + ); + SRLC16E com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_srlrow_3__srlcol_0__srlinst ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_wen_aux_oq_3091), + .D(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_shift_in[27]), + .Q(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_shift_tap[27]), + .CLK(NlwRenamedSig_OI_trn_clk), + .Q15(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_shift_in[36]), + .A0(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_lo[0]), + .A1(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_lo[1]), + .A2(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_lo[2]), + .A3(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_lo[3]) + ); + SRLC16E com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_srlrow_0__srlcol_0__srlinst ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_wen_aux_oq_3091), + .D(com_tlm_u_tlm_rx_vc0_fifo_aux_in[0]), + .Q(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_shift_tap[0]), + .CLK(NlwRenamedSig_OI_trn_clk), + .Q15(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_shift_in[9]), + .A0(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_lo[0]), + .A1(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_lo[1]), + .A2(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_lo[2]), + .A3(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_lo[3]) + ); + SRLC16E com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_srlrow_2__srlcol_7__srlinst ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_wen_aux_oq_3091), + .D(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_shift_in[25]), + .Q(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_shift_tap[25]), + .CLK(NlwRenamedSig_OI_trn_clk), + .Q15(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_shift_in[34]), + .A0(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_lo[0]), + .A1(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_lo[1]), + .A2(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_lo[2]), + .A3(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_lo[3]) + ); + SRLC16E com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_srlrow_1__srlcol_3__srlinst ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_wen_aux_oq_3091), + .D(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_shift_in[12]), + .Q(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_shift_tap[12]), + .CLK(NlwRenamedSig_OI_trn_clk), + .Q15(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_shift_in[21]), + .A0(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_lo[0]), + .A1(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_lo[1]), + .A2(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_lo[2]), + .A3(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_lo[3]) + ); + SRLC16E com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_srlrow_4__srlcol_3__srlinst ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_wen_aux_oq_3091), + .D(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_shift_in[39]), + .Q(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_shift_tap[39]), + .CLK(NlwRenamedSig_OI_trn_clk), + .Q15(NLW_com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_srlrow_4__srlcol_3__srlinst_Q15_UNCONNECTED), + .A0(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_lo[0]), + .A1(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_lo[1]), + .A2(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_lo[2]), + .A3(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_lo[3]) + ); + SRLC16E com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_srlrow_2__srlcol_8__srlinst ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_wen_aux_oq_3091), + .D(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_shift_in[26]), + .Q(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_shift_tap[26]), + .CLK(NlwRenamedSig_OI_trn_clk), + .Q15(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_shift_in[35]), + .A0(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_lo[0]), + .A1(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_lo[1]), + .A2(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_lo[2]), + .A3(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_lo[3]) + ); + SRLC16E com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_srlrow_1__srlcol_4__srlinst ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_wen_aux_oq_3091), + .D(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_shift_in[13]), + .Q(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_shift_tap[13]), + .CLK(NlwRenamedSig_OI_trn_clk), + .Q15(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_shift_in[22]), + .A0(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_lo[0]), + .A1(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_lo[1]), + .A2(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_lo[2]), + .A3(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_lo[3]) + ); + SRLC16E com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_srlrow_4__srlcol_2__srlinst ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_wen_aux_oq_3091), + .D(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_shift_in[38]), + .Q(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_shift_tap[38]), + .CLK(NlwRenamedSig_OI_trn_clk), + .Q15(NLW_com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_srlrow_4__srlcol_2__srlinst_Q15_UNCONNECTED), + .A0(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_lo[0]), + .A1(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_lo[1]), + .A2(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_lo[2]), + .A3(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_lo[3]) + ); + SRLC16E com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_srlrow_1__srlcol_2__srlinst ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_wen_aux_oq_3091), + .D(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_shift_in[11]), + .Q(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_shift_tap[11]), + .CLK(NlwRenamedSig_OI_trn_clk), + .Q15(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_shift_in[20]), + .A0(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_lo[0]), + .A1(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_lo[1]), + .A2(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_lo[2]), + .A3(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_lo[3]) + ); + SRLC16E com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_srlrow_3__srlcol_1__srlinst ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_wen_aux_oq_3091), + .D(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_shift_in[28]), + .Q(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_shift_tap[28]), + .CLK(NlwRenamedSig_OI_trn_clk), + .Q15(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_shift_in[37]), + .A0(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_lo[0]), + .A1(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_lo[1]), + .A2(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_lo[2]), + .A3(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_lo[3]) + ); + SRLC16E com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_srlrow_0__srlcol_1__srlinst ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_wen_aux_oq_3091), + .D(com_tlm_u_tlm_rx_vc0_fifo_aux_in[1]), + .Q(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_shift_tap[1]), + .CLK(NlwRenamedSig_OI_trn_clk), + .Q15(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_shift_in[10]), + .A0(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_lo[0]), + .A1(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_lo[1]), + .A2(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_lo[2]), + .A3(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_lo[3]) + ); + SRLC16E com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_srlrow_1__srlcol_5__srlinst ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_wen_aux_oq_3091), + .D(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_shift_in[14]), + .Q(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_shift_tap[14]), + .CLK(NlwRenamedSig_OI_trn_clk), + .Q15(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_shift_in[23]), + .A0(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_lo[0]), + .A1(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_lo[1]), + .A2(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_lo[2]), + .A3(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_lo[3]) + ); + FDS com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_lo_0_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_un1_raddr_lo_1_axb_0_3321), + .Q(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_lo[0]), + .S(plm_link_up_i) + ); + FDS com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_lo_1_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_un1_raddr_lo_1_s_1_4), + .Q(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_lo[1]), + .S(plm_link_up_i) + ); + FDS com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_lo_2_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_un1_raddr_lo_1_s_2_4), + .Q(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_lo[2]), + .S(plm_link_up_i) + ); + FDS com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_lo_3_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_un1_raddr_lo_1_s_3_4), + .Q(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_lo[3]), + .S(plm_link_up_i) + ); + FDRE com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_hi_0_ ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_un1_bkp_i_3_i_3323), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_hi_53_0_), + .Q(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_hi[0]), + .R(plm_link_up_i) + ); + FDRE com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_hi_1_ ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_un1_bkp_i_3_i_3323), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_hi_53_0_i_m2_0[1]), + .Q(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_hi[1]), + .R(plm_link_up_i) + ); + FDRE com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_hi_2_ ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_un1_bkp_i_3_i_3323), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_hi_53_0_i_m2_0[2]), + .Q(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_hi[2]), + .R(plm_link_up_i) + ); + FDRE com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_hi_3_ ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_un1_bkp_i_3_i_3323), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_hi_53_0_i_m2_0[3]), + .Q(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_hi[3]), + .R(plm_link_up_i) + ); + FDRE com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_hi_4_ ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_un1_bkp_i_3_i_3323), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_hi_53_4_), + .Q(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_hi[4]), + .R(plm_link_up_i) + ); + FDRE com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_nxt_vld_o ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_un1_bkp_i_1_i_3322), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_hi_eq_1_m_i_3326), + .Q(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_nxt_vld_o_2), + .R(plm_link_up_i) + ); + FDRE com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_d_o_0_ ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_N_9610_i_3331), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_N_68074_i), + .Q(com_tlm_u_tlm_rx_vc0_fifo_aux_oqr[0]), + .R(plm_link_up_i) + ); + FDRE com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_d_o_1_ ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_N_9610_i_3331), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_N_67944_i), + .Q(com_tlm_u_tlm_rx_vc0_fifo_aux_oqr[1]), + .R(plm_link_up_i) + ); + FDRE com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_d_o_2_ ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_N_9610_i_3331), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_N_67943_i), + .Q(com_tlm_u_tlm_rx_vc0_fifo_aux_oqr[2]), + .R(plm_link_up_i) + ); + FDRE com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_d_o_3_ ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_N_9610_i_3331), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_N_67942_i), + .Q(com_tlm_u_tlm_rx_vc0_fifo_aux_oqr[3]), + .R(plm_link_up_i) + ); + FDRE com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_d_o_4_ ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_N_9610_i_3331), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_N_67941_i), + .Q(com_tlm_u_tlm_rx_vc0_fifo_aux_oqr[4]), + .R(plm_link_up_i) + ); + FDRE com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_d_o_5_ ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_N_9610_i_3331), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_N_67940_i), + .Q(com_tlm_u_tlm_rx_vc0_fifo_aux_oqr[5]), + .R(plm_link_up_i) + ); + FDRE com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_d_o_6_ ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_N_9610_i_3331), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_N_68075_i), + .Q(com_tlm_u_tlm_rx_vc0_fifo_aux_oqr[6]), + .R(plm_link_up_i) + ); + FDRE com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_d_o_7_ ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_N_9610_i_3331), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_N_68076_i), + .Q(com_tlm_u_tlm_rx_vc0_fifo_cfg_oqr), + .R(plm_link_up_i) + ); + FDRE com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_d_o_8_ ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_N_9610_i_3331), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_N_67946_i), + .Q(com_tlm_u_tlm_rx_vc0_fifo_np_oqr), + .R(plm_link_up_i) + ); + FDRE com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_vld_o ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_N_9610_i_3331), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_N_14175_i), + .Q(com_tlm_u_tlm_rx_vc0_fifo_aux_vld_oqr), + .R(plm_link_up_i) + ); + MUXCY_L com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_un1_raddr_lo_1_cry_0 ( + .CI(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_GND_3315), + .DI(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_un1_raddr_lo_1_cry_0_ma_3333), + .LO(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_un1_raddr_lo_1_cry_0_3317), + .S(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_un1_raddr_lo_1_axb_0_3321) + ); + MULT_AND com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_un1_raddr_lo_1_cry_1 ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_N_14111), + .I1(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_d_o_0_sqmuxa_3330), + .LO(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_un1_raddr_lo_1_cry_1_0_3316) + ); + MUXCY_L com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_un1_raddr_lo_1_cry_1_0 ( + .CI(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_un1_raddr_lo_1_cry_0_3317), + .DI(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_un1_raddr_lo_1_cry_1_0_3316), + .LO(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_un1_raddr_lo_1_cry_1_3319), + .S(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_un1_raddr_lo_1_axb_1_3329) + ); + XORCY com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_un1_raddr_lo_1_s_1 ( + .CI(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_un1_raddr_lo_1_cry_0_3317), + .LI(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_un1_raddr_lo_1_axb_1_3329), + .O(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_un1_raddr_lo_1_s_1_4) + ); + MULT_AND com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_un1_raddr_lo_1_cry_2 ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_N_14111), + .I1(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_d_o_0_sqmuxa_3330), + .LO(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_un1_raddr_lo_1_cry_2_0_3318) + ); + MUXCY_L com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_un1_raddr_lo_1_cry_2_0 ( + .CI(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_un1_raddr_lo_1_cry_1_3319), + .DI(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_un1_raddr_lo_1_cry_2_0_3318), + .LO(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_un1_raddr_lo_1_cry_2_3320), + .S(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_un1_raddr_lo_1_axb_2_3328) + ); + XORCY com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_un1_raddr_lo_1_s_2 ( + .CI(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_un1_raddr_lo_1_cry_1_3319), + .LI(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_un1_raddr_lo_1_axb_2_3328), + .O(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_un1_raddr_lo_1_s_2_4) + ); + XORCY com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_un1_raddr_lo_1_s_3 ( + .CI(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_un1_raddr_lo_1_cry_2_3320), + .LI(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_un1_raddr_lo_1_axb_3_3327), + .O(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_un1_raddr_lo_1_s_3_4) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_control_bits_d_o_34_0_1_a4_4_0_.INIT = 4'h8; + LUT2 com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_control_bits_d_o_34_0_1_a4_4_0_ ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_hi[1]), + .I1(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_nxt_vld_o_2), + .O(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_N_14181) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_control_bits_d_o_34_0_1_a4_3_0_.INIT = 4'h8; + LUT2 com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_control_bits_d_o_34_0_1_a4_3_0_ ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_hi[0]), + .I1(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_nxt_vld_o_2), + .O(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_N_14180) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_control_bits_d_o_34_0_1_a4_2_0_.INIT = 4'h8; + LUT2 com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_control_bits_d_o_34_0_1_a4_2_0_ ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_hi[3]), + .I1(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_nxt_vld_o_2), + .O(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_N_14179) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_control_bits_d_o_34_0_1_a4_1_0_.INIT = 4'h8; + LUT2 com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_control_bits_d_o_34_0_1_a4_1_0_ ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_hi[2]), + .I1(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_nxt_vld_o_2), + .O(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_N_14178) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_control_bits_d_o_34_0_1_a4_0_0_.INIT = 4'h8; + LUT2 com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_control_bits_d_o_34_0_1_a4_0_0_ ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_hi[4]), + .I1(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_nxt_vld_o_2), + .O(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_N_14177) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_control_bits_d_o_34_0_1_a4_0_.INIT = 4'h4; + LUT2 com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_control_bits_d_o_34_0_1_a4_0_ ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_nxt_vld_o_2), + .I1(com_tlm_u_tlm_rx_vc0_fifo_wen_aux_oq_3091), + .O(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_N_14176) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_un1_raddr_lo_1_axb_0.INIT = 8'h69; + LUT3 com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_un1_raddr_lo_1_axb_0 ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_N_14111), + .I1(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_d_o_0_sqmuxa_3330), + .I2(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_lo[0]), + .O(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_un1_raddr_lo_1_axb_0_3321) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddrshift_un7_raddr_shiftup_1.INIT = 16'h0001; + LUT4 com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddrshift_un7_raddr_shiftup_1 ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_hi[1]), + .I1(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_hi[2]), + .I2(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_hi[3]), + .I3(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_hi[4]), + .O(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_N_9609_1) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_un11_nxt_vld_o_en_2.INIT = 16'h0001; + LUT4 com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_un11_nxt_vld_o_en_2 ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_lo[0]), + .I1(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_lo[1]), + .I2(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_lo[2]), + .I3(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_lo[3]), + .O(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_un11_nxt_vld_o_en_2_3324) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_overwrap_2.INIT = 16'h8000; + LUT4 com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_overwrap_2 ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_lo[0]), + .I1(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_lo[1]), + .I2(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_lo[2]), + .I3(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_lo[3]), + .O(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_overwrap_2_3325) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_control_bits_d_o_34_0_1_0_7_.INIT = 16'h135F; + LUT4 com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_control_bits_d_o_34_0_1_0_7_ ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_N_14176), + .I1(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_N_14177), + .I2(com_tlm_u_tlm_rx_vc0_fifo_aux_in[7]), + .I3(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_shift_tap[43]), + .O(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_d_o_34_0_1_0[7]) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_control_bits_d_o_34_0_1_1_7_.INIT = 16'h153F; + LUT4 com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_control_bits_d_o_34_0_1_1_7_ ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_N_14178), + .I1(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_N_14181), + .I2(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_shift_tap[16]), + .I3(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_shift_tap[25]), + .O(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_d_o_34_0_1_1[7]) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_control_bits_d_o_34_0_1_2_7_.INIT = 16'h153F; + LUT4 com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_control_bits_d_o_34_0_1_2_7_ ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_N_14179), + .I1(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_N_14180), + .I2(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_shift_tap[7]), + .I3(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_shift_tap[34]), + .O(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_d_o_34_0_1_2[7]) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_control_bits_d_o_34_0_1_0_8_.INIT = 16'h135F; + LUT4 com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_control_bits_d_o_34_0_1_0_8_ ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_N_14176), + .I1(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_N_14177), + .I2(com_tlm_u_tlm_rx_vc0_fifo_aux_in[8]), + .I3(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_shift_tap[44]), + .O(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_d_o_34_0_1_0[8]) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_control_bits_d_o_34_0_1_1_8_.INIT = 16'h153F; + LUT4 com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_control_bits_d_o_34_0_1_1_8_ ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_N_14178), + .I1(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_N_14181), + .I2(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_shift_tap[17]), + .I3(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_shift_tap[26]), + .O(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_d_o_34_0_1_1[8]) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_control_bits_d_o_34_0_1_2_8_.INIT = 16'h153F; + LUT4 com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_control_bits_d_o_34_0_1_2_8_ ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_N_14179), + .I1(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_N_14180), + .I2(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_shift_tap[8]), + .I3(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_shift_tap[35]), + .O(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_d_o_34_0_1_2[8]) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_control_bits_d_o_34_0_1_0_2_.INIT = 16'h135F; + LUT4 com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_control_bits_d_o_34_0_1_0_2_ ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_N_14176), + .I1(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_N_14177), + .I2(com_tlm_u_tlm_rx_vc0_fifo_aux_in[2]), + .I3(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_shift_tap[38]), + .O(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_d_o_34_0_1_0[2]) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_control_bits_d_o_34_0_1_1_2_.INIT = 16'h135F; + LUT4 com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_control_bits_d_o_34_0_1_1_2_ ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_N_14178), + .I1(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_N_14179), + .I2(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_shift_tap[20]), + .I3(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_shift_tap[29]), + .O(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_d_o_34_0_1_1[2]) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_control_bits_d_o_34_0_1_2_2_.INIT = 16'h135F; + LUT4 com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_control_bits_d_o_34_0_1_2_2_ ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_N_14180), + .I1(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_N_14181), + .I2(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_shift_tap[2]), + .I3(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_shift_tap[11]), + .O(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_d_o_34_0_1_2[2]) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_control_bits_d_o_34_0_1_0_6_.INIT = 16'h135F; + LUT4 com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_control_bits_d_o_34_0_1_0_6_ ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_N_14176), + .I1(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_N_14177), + .I2(com_tlm_u_tlm_rx_vc0_fifo_aux_in[6]), + .I3(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_shift_tap[42]), + .O(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_d_o_34_0_1_0[6]) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_control_bits_d_o_34_0_1_1_6_.INIT = 16'h153F; + LUT4 com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_control_bits_d_o_34_0_1_1_6_ ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_N_14178), + .I1(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_N_14181), + .I2(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_shift_tap[15]), + .I3(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_shift_tap[24]), + .O(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_d_o_34_0_1_1[6]) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_control_bits_d_o_34_0_1_2_6_.INIT = 16'h153F; + LUT4 com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_control_bits_d_o_34_0_1_2_6_ ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_N_14179), + .I1(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_N_14180), + .I2(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_shift_tap[6]), + .I3(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_shift_tap[33]), + .O(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_d_o_34_0_1_2[6]) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_control_bits_d_o_34_0_1_0_5_.INIT = 16'h135F; + LUT4 com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_control_bits_d_o_34_0_1_0_5_ ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_N_14176), + .I1(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_N_14177), + .I2(com_tlm_u_tlm_rx_vc0_fifo_aux_in[5]), + .I3(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_shift_tap[41]), + .O(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_d_o_34_0_1_0[5]) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_control_bits_d_o_34_0_1_1_5_.INIT = 16'h153F; + LUT4 com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_control_bits_d_o_34_0_1_1_5_ ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_N_14178), + .I1(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_N_14180), + .I2(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_shift_tap[5]), + .I3(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_shift_tap[23]), + .O(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_d_o_34_0_1_1[5]) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_control_bits_d_o_34_0_1_2_5_.INIT = 16'h153F; + LUT4 com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_control_bits_d_o_34_0_1_2_5_ ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_N_14179), + .I1(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_N_14181), + .I2(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_shift_tap[14]), + .I3(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_shift_tap[32]), + .O(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_d_o_34_0_1_2[5]) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_control_bits_d_o_34_0_1_0_1_.INIT = 16'h135F; + LUT4 com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_control_bits_d_o_34_0_1_0_1_ ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_N_14176), + .I1(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_N_14177), + .I2(com_tlm_u_tlm_rx_vc0_fifo_aux_in[1]), + .I3(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_shift_tap[37]), + .O(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_d_o_34_0_1_0[1]) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_control_bits_d_o_34_0_1_1_1_.INIT = 16'h135F; + LUT4 com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_control_bits_d_o_34_0_1_1_1_ ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_N_14178), + .I1(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_N_14179), + .I2(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_shift_tap[19]), + .I3(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_shift_tap[28]), + .O(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_d_o_34_0_1_1[1]) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_control_bits_d_o_34_0_1_2_1_.INIT = 16'h135F; + LUT4 com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_control_bits_d_o_34_0_1_2_1_ ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_N_14180), + .I1(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_N_14181), + .I2(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_shift_tap[1]), + .I3(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_shift_tap[10]), + .O(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_d_o_34_0_1_2[1]) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_control_bits_d_o_34_0_1_0_4_.INIT = 16'h135F; + LUT4 com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_control_bits_d_o_34_0_1_0_4_ ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_N_14176), + .I1(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_N_14177), + .I2(com_tlm_u_tlm_rx_vc0_fifo_aux_in[4]), + .I3(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_shift_tap[40]), + .O(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_d_o_34_0_1_0[4]) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_control_bits_d_o_34_0_1_1_4_.INIT = 16'h153F; + LUT4 com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_control_bits_d_o_34_0_1_1_4_ ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_N_14178), + .I1(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_N_14180), + .I2(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_shift_tap[4]), + .I3(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_shift_tap[22]), + .O(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_d_o_34_0_1_1[4]) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_control_bits_d_o_34_0_1_2_4_.INIT = 16'h153F; + LUT4 com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_control_bits_d_o_34_0_1_2_4_ ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_N_14179), + .I1(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_N_14181), + .I2(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_shift_tap[13]), + .I3(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_shift_tap[31]), + .O(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_d_o_34_0_1_2[4]) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_control_bits_d_o_34_0_1_0_3_.INIT = 16'h135F; + LUT4 com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_control_bits_d_o_34_0_1_0_3_ ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_N_14176), + .I1(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_N_14177), + .I2(com_tlm_u_tlm_rx_vc0_fifo_aux_in[3]), + .I3(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_shift_tap[39]), + .O(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_d_o_34_0_1_0[3]) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_control_bits_d_o_34_0_1_1_3_.INIT = 16'h135F; + LUT4 com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_control_bits_d_o_34_0_1_1_3_ ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_N_14178), + .I1(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_N_14179), + .I2(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_shift_tap[21]), + .I3(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_shift_tap[30]), + .O(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_d_o_34_0_1_1[3]) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_control_bits_d_o_34_0_1_2_3_.INIT = 16'h135F; + LUT4 com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_control_bits_d_o_34_0_1_2_3_ ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_N_14180), + .I1(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_N_14181), + .I2(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_shift_tap[3]), + .I3(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_shift_tap[12]), + .O(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_d_o_34_0_1_2[3]) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_control_bits_d_o_34_0_1_0_0_.INIT = 16'h135F; + LUT4 com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_control_bits_d_o_34_0_1_0_0_ ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_N_14176), + .I1(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_N_14177), + .I2(com_tlm_u_tlm_rx_vc0_fifo_aux_in[0]), + .I3(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_shift_tap[36]), + .O(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_d_o_34_0_1_0[0]) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_control_bits_d_o_34_0_1_1_0_.INIT = 16'h135F; + LUT4 com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_control_bits_d_o_34_0_1_1_0_ ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_N_14178), + .I1(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_N_14179), + .I2(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_shift_tap[18]), + .I3(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_shift_tap[27]), + .O(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_d_o_34_0_1_1[0]) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_control_bits_d_o_34_0_1_2_0_.INIT = 16'h135F; + LUT4 com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_control_bits_d_o_34_0_1_2_0_ ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_N_14180), + .I1(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_N_14181), + .I2(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_shift_tap[0]), + .I3(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_shift_tap[9]), + .O(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_d_o_34_0_1_2[0]) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_srl_ren.INIT = 8'h8C; + LUT3 com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_srl_ren ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_N_9516_i_i), + .I1(com_tlm_u_tlm_rx_vc0_fifo_aux_vld_oqr), + .I2(com_tlm_u_tlm_rx_vc0_fifo_sof_oqr), + .O(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_srl_ren_3332) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_d_o_0_sqmuxa.INIT = 4'h4; + LUT2 com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_d_o_0_sqmuxa ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_srl_ren_3332), + .I1(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_nxt_vld_o_2), + .O(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_d_o_0_sqmuxa_3330) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_un1_bkp_i_1_i.INIT = 8'h73; + LUT3 com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_un1_bkp_i_1_i ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_srl_ren_3332), + .I1(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_N_14111), + .I2(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_un11_nxt_vld_o_en_2_3324), + .O(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_un1_bkp_i_1_i_3322) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_N_68999_i.INIT = 8'h1F; + LUT3 com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_N_68999_i ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_srl_ren_3332), + .I1(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_nxt_vld_o_2), + .I2(com_tlm_u_tlm_rx_vc0_fifo_wen_aux_oq_3091), + .O(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_N_14111) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_un1_bkp_i_3_i.INIT = 16'h6420; + LUT4 com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_un1_bkp_i_3_i ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_srl_ren_3332), + .I1(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_N_14111), + .I2(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_overwrap_2_3325), + .I3(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_un11_nxt_vld_o_en_2_3324), + .O(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_un1_bkp_i_3_i_3323) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_control_bits_N_14175_i.INIT = 4'hE; + LUT2_L com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_control_bits_N_14175_i ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_nxt_vld_o_2), + .I1(com_tlm_u_tlm_rx_vc0_fifo_wen_aux_oq_3091), + .LO(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_N_14175_i) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_control_bits_N_67946_i.INIT = 8'h7F; + LUT3_L com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_control_bits_N_67946_i ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_d_o_34_0_1_0[8]), + .I1(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_d_o_34_0_1_1[8]), + .I2(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_d_o_34_0_1_2[8]), + .LO(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_N_67946_i) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_control_bits_N_68076_i.INIT = 8'h7F; + LUT3_L com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_control_bits_N_68076_i ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_d_o_34_0_1_0[7]), + .I1(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_d_o_34_0_1_1[7]), + .I2(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_d_o_34_0_1_2[7]), + .LO(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_N_68076_i) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_control_bits_N_68075_i.INIT = 8'h7F; + LUT3_L com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_control_bits_N_68075_i ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_d_o_34_0_1_0[6]), + .I1(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_d_o_34_0_1_1[6]), + .I2(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_d_o_34_0_1_2[6]), + .LO(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_N_68075_i) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_control_bits_N_67940_i.INIT = 8'h7F; + LUT3_L com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_control_bits_N_67940_i ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_d_o_34_0_1_0[5]), + .I1(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_d_o_34_0_1_1[5]), + .I2(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_d_o_34_0_1_2[5]), + .LO(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_N_67940_i) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_control_bits_N_67941_i.INIT = 8'h7F; + LUT3_L com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_control_bits_N_67941_i ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_d_o_34_0_1_0[4]), + .I1(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_d_o_34_0_1_1[4]), + .I2(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_d_o_34_0_1_2[4]), + .LO(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_N_67941_i) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_control_bits_N_67942_i.INIT = 8'h7F; + LUT3_L com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_control_bits_N_67942_i ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_d_o_34_0_1_0[3]), + .I1(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_d_o_34_0_1_1[3]), + .I2(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_d_o_34_0_1_2[3]), + .LO(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_N_67942_i) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_control_bits_N_67943_i.INIT = 8'h7F; + LUT3_L com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_control_bits_N_67943_i ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_d_o_34_0_1_0[2]), + .I1(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_d_o_34_0_1_1[2]), + .I2(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_d_o_34_0_1_2[2]), + .LO(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_N_67943_i) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_control_bits_N_67944_i.INIT = 8'h7F; + LUT3_L com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_control_bits_N_67944_i ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_d_o_34_0_1_0[1]), + .I1(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_d_o_34_0_1_1[1]), + .I2(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_d_o_34_0_1_2[1]), + .LO(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_N_67944_i) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_control_bits_N_68074_i.INIT = 8'h7F; + LUT3_L com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_control_bits_N_68074_i ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_d_o_34_0_1_0[0]), + .I1(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_d_o_34_0_1_1[0]), + .I2(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_d_o_34_0_1_2[0]), + .LO(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_N_68074_i) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_hi_eq_1_m_i.INIT = 8'h7F; + LUT3_L com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_hi_eq_1_m_i ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_N_9609_1), + .I1(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_N_14111), + .I2(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_hi[0]), + .LO(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_hi_eq_1_m_i_3326) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_hi_53_0_4_.INIT = 4'h4; + LUT2_L com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_hi_53_0_4_ ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_N_14111), + .I1(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_hi[3]), + .LO(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_hi_53_4_) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_hi_53_0_i_m2_0_3_.INIT = 8'hE4; + LUT3_L com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_hi_53_0_i_m2_0_3_ ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_N_14111), + .I1(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_hi[2]), + .I2(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_hi[4]), + .LO(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_hi_53_0_i_m2_0[3]) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_hi_53_0_i_m2_0_2_.INIT = 8'hE4; + LUT3_L com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_hi_53_0_i_m2_0_2_ ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_N_14111), + .I1(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_hi[1]), + .I2(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_hi[3]), + .LO(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_hi_53_0_i_m2_0[2]) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_hi_53_0_i_m2_0_1_.INIT = 8'hE4; + LUT3_L com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_hi_53_0_i_m2_0_1_ ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_N_14111), + .I1(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_hi[0]), + .I2(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_hi[2]), + .LO(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_hi_53_0_i_m2_0[1]) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_hi_53_0_0_0_.INIT = 16'hCE02; + LUT4_L com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_hi_53_0_0_0_ ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_N_9609_1), + .I1(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_N_14111), + .I2(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_hi[0]), + .I3(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_hi[1]), + .LO(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_hi_53_0_) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_un1_raddr_lo_1_axb_3.INIT = 8'h78; + LUT3_L com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_un1_raddr_lo_1_axb_3 ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_N_14111), + .I1(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_d_o_0_sqmuxa_3330), + .I2(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_lo[3]), + .LO(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_un1_raddr_lo_1_axb_3_3327) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_un1_raddr_lo_1_axb_2.INIT = 8'h78; + LUT3_L com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_un1_raddr_lo_1_axb_2 ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_N_14111), + .I1(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_d_o_0_sqmuxa_3330), + .I2(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_lo[2]), + .LO(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_un1_raddr_lo_1_axb_2_3328) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_un1_raddr_lo_1_axb_1.INIT = 8'h78; + LUT3_L com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_un1_raddr_lo_1_axb_1 ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_N_14111), + .I1(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_d_o_0_sqmuxa_3330), + .I2(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_lo[1]), + .LO(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_un1_raddr_lo_1_axb_1_3329) + ); + INV com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_N_9610_i ( + .I(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_srl_ren_3332), + .O(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_N_9610_i_3331) + ); + MULT_AND com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_un1_raddr_lo_1_cry_0_ma ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_lo[0]), + .I1(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_VCC_3334), + .LO(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_un1_raddr_lo_1_cry_0_ma_3333) + ); + FDR com_tlm_u_tlm_rx_vc0_fifo_byp_queue_sof_hold ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_N_14199_i), + .Q(com_tlm_u_tlm_rx_vc0_fifo_sof_hold), + .R(plm_link_up_i) + ); + FDRE com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_vld_q ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_ren), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_aux_vld), + .Q(com_tlm_u_tlm_rx_vc0_fifo_aux_vld_q), + .R(plm_link_up_i) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_ren_0_a2.INIT = 4'h4; + LUT2 com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_ren_0_a2 ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_sof_hold), + .I1(com_tlm_u_tlm_rx_vc0_fifo_data_bqr_64_), + .O(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_ren) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_o_0_2_.INIT = 8'hCA; + LUT3_L com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_o_0_2_ ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux[2]), + .I1(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_q[2]), + .I2(com_tlm_u_tlm_rx_vc0_fifo_sof_hold), + .LO(com_tlm_u_tlm_rx_vc0_fifo_aux_bqr[2]) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_o_0_7_.INIT = 8'hCA; + LUT3 com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_o_0_7_ ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux[7]), + .I1(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_q[7]), + .I2(com_tlm_u_tlm_rx_vc0_fifo_sof_hold), + .O(com_tlm_u_tlm_rx_vc0_fifo_aux_bqr[7]) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_o_0_6_.INIT = 8'hCA; + LUT3_L com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_o_0_6_ ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux[6]), + .I1(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_q[6]), + .I2(com_tlm_u_tlm_rx_vc0_fifo_sof_hold), + .LO(com_tlm_u_tlm_rx_vc0_fifo_aux_bqr[6]) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_o_0_5_.INIT = 8'hCA; + LUT3_L com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_o_0_5_ ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux[5]), + .I1(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_q[5]), + .I2(com_tlm_u_tlm_rx_vc0_fifo_sof_hold), + .LO(com_tlm_u_tlm_rx_vc0_fifo_aux_bqr[5]) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_o_0_4_.INIT = 8'hCA; + LUT3_L com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_o_0_4_ ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux[4]), + .I1(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_q[4]), + .I2(com_tlm_u_tlm_rx_vc0_fifo_sof_hold), + .LO(com_tlm_u_tlm_rx_vc0_fifo_aux_bqr[4]) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_o_0_3_.INIT = 8'hCA; + LUT3_L com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_o_0_3_ ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux[3]), + .I1(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_q[3]), + .I2(com_tlm_u_tlm_rx_vc0_fifo_sof_hold), + .LO(com_tlm_u_tlm_rx_vc0_fifo_aux_bqr[3]) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_o_0_1_.INIT = 8'hCA; + LUT3_L com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_o_0_1_ ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux[1]), + .I1(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_q[1]), + .I2(com_tlm_u_tlm_rx_vc0_fifo_sof_hold), + .LO(com_tlm_u_tlm_rx_vc0_fifo_aux_bqr[1]) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_o_0_0_.INIT = 8'hCA; + LUT3_L com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_o_0_0_ ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux[0]), + .I1(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_q[0]), + .I2(com_tlm_u_tlm_rx_vc0_fifo_sof_hold), + .LO(com_tlm_u_tlm_rx_vc0_fifo_aux_bqr[0]) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_ren_64_sof_hold_3_i_a2.INIT = 4'h4; + LUT2 com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_ren_64_sof_hold_3_i_a2 ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_adv_out_i_0_3193), + .I1(com_tlm_u_tlm_rx_vc0_fifo_select_bq_3108), + .O(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_N_14337) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_ren_64_sof_hold_3_i.INIT = 4'h4; + LUT2_L com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_ren_64_sof_hold_3_i ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_N_14337), + .I1(com_tlm_u_tlm_rx_vc0_fifo_data_bqr_64_), + .LO(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_N_14199_i) + ); + FDE com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_q_7_ ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_ren), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux[7]), + .Q(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_q[7]) + ); + FDE com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_q_6_ ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_ren), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux[6]), + .Q(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_q[6]) + ); + FDE com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_q_5_ ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_ren), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux[5]), + .Q(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_q[5]) + ); + FDE com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_q_4_ ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_ren), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux[4]), + .Q(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_q[4]) + ); + FDE com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_q_3_ ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_ren), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux[3]), + .Q(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_q[3]) + ); + FDE com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_q_2_ ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_ren), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux[2]), + .Q(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_q[2]) + ); + FDE com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_q_1_ ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_ren), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux[1]), + .Q(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_q[1]) + ); + FDE com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_q_0_ ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_ren), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux[0]), + .Q(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_q[0]) + ); + GND com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_GND ( + .G(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_GND_3335) + ); + SRLC16E com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_srlrow_0__srlcol_0__srlinst ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_select_oq2bq_3117), + .D(com_tlm_u_tlm_rx_vc0_fifo_data_oqr_0_), + .Q(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_0_), + .CLK(NlwRenamedSig_OI_trn_clk), + .Q15(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_in_72_), + .A0(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[0]), + .A1(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[1]), + .A2(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[2]), + .A3(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[3]) + ); + SRLC16E com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_srlrow_1__srlcol_9__srlinst ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_select_oq2bq_3117), + .D(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_in_81_), + .Q(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_81_), + .CLK(NlwRenamedSig_OI_trn_clk), + .Q15(NLW_com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_srlrow_1__srlcol_9__srlinst_Q15_UNCONNECTED), + .A0(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[0]), + .A1(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[1]), + .A2(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[2]), + .A3(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[3]) + ); + SRLC16E com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_srlrow_0__srlcol_41__srlinst ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_select_oq2bq_1_3115), + .D(com_tlm_u_tlm_rx_vc0_fifo_data_oqr_41_), + .Q(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_41_), + .CLK(NlwRenamedSig_OI_trn_clk), + .Q15(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_in_113_), + .A0(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[0]), + .A1(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[1]), + .A2(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[2]), + .A3(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[3]) + ); + SRLC16E com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_srlrow_0__srlcol_1__srlinst ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_select_oq2bq_3117), + .D(com_tlm_u_tlm_rx_vc0_fifo_data_oqr_1_), + .Q(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_1_), + .CLK(NlwRenamedSig_OI_trn_clk), + .Q15(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_in_73_), + .A0(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[0]), + .A1(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[1]), + .A2(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[2]), + .A3(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[3]) + ); + SRLC16E com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_srlrow_1__srlcol_10__srlinst ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_select_oq2bq_3117), + .D(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_in_82_), + .Q(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_82_), + .CLK(NlwRenamedSig_OI_trn_clk), + .Q15(NLW_com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_srlrow_1__srlcol_10__srlinst_Q15_UNCONNECTED), + .A0(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[0]), + .A1(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[1]), + .A2(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[2]), + .A3(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[3]) + ); + SRLC16E com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_srlrow_0__srlcol_42__srlinst ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_select_oq2bq_1_3115), + .D(com_tlm_u_tlm_rx_vc0_fifo_data_oqr_42_), + .Q(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_42_), + .CLK(NlwRenamedSig_OI_trn_clk), + .Q15(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_in_114_), + .A0(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[0]), + .A1(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[1]), + .A2(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[2]), + .A3(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[3]) + ); + SRLC16E com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_srlrow_0__srlcol_2__srlinst ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_select_oq2bq_3117), + .D(com_tlm_u_tlm_rx_vc0_fifo_data_oqr_2_), + .Q(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_2_), + .CLK(NlwRenamedSig_OI_trn_clk), + .Q15(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_in_74_), + .A0(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[0]), + .A1(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[1]), + .A2(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[2]), + .A3(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[3]) + ); + SRLC16E com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_srlrow_1__srlcol_11__srlinst ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_select_oq2bq_3117), + .D(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_in_83_), + .Q(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_83_), + .CLK(NlwRenamedSig_OI_trn_clk), + .Q15(NLW_com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_srlrow_1__srlcol_11__srlinst_Q15_UNCONNECTED), + .A0(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[0]), + .A1(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[1]), + .A2(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[2]), + .A3(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[3]) + ); + SRLC16E com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_srlrow_0__srlcol_43__srlinst ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_select_oq2bq_1_3115), + .D(com_tlm_u_tlm_rx_vc0_fifo_data_oqr_43_), + .Q(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_43_), + .CLK(NlwRenamedSig_OI_trn_clk), + .Q15(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_in_115_), + .A0(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[0]), + .A1(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[1]), + .A2(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[2]), + .A3(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[3]) + ); + SRLC16E com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_srlrow_0__srlcol_3__srlinst ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_select_oq2bq_3117), + .D(com_tlm_u_tlm_rx_vc0_fifo_data_oqr_3_), + .Q(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_3_), + .CLK(NlwRenamedSig_OI_trn_clk), + .Q15(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_in_75_), + .A0(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[0]), + .A1(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[1]), + .A2(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[2]), + .A3(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[3]) + ); + SRLC16E com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_srlrow_0__srlcol_21__srlinst ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_select_oq2bq_3117), + .D(com_tlm_u_tlm_rx_vc0_fifo_data_oqr_21_), + .Q(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_21_), + .CLK(NlwRenamedSig_OI_trn_clk), + .Q15(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_in_93_), + .A0(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[0]), + .A1(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[1]), + .A2(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[2]), + .A3(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[3]) + ); + SRLC16E com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_srlrow_1__srlcol_30__srlinst ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_select_oq2bq_1_3115), + .D(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_in_102_), + .Q(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_102_), + .CLK(NlwRenamedSig_OI_trn_clk), + .Q15(NLW_com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_srlrow_1__srlcol_30__srlinst_Q15_UNCONNECTED), + .A0(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[0]), + .A1(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[1]), + .A2(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[2]), + .A3(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[3]) + ); + SRLC16E com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_srlrow_0__srlcol_4__srlinst ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_select_oq2bq_3117), + .D(com_tlm_u_tlm_rx_vc0_fifo_data_oqr_4_), + .Q(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_4_), + .CLK(NlwRenamedSig_OI_trn_clk), + .Q15(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_in_76_), + .A0(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[0]), + .A1(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[1]), + .A2(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[2]), + .A3(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[3]) + ); + SRLC16E com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_srlrow_1__srlcol_13__srlinst ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_select_oq2bq_3117), + .D(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_in_85_), + .Q(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_85_), + .CLK(NlwRenamedSig_OI_trn_clk), + .Q15(NLW_com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_srlrow_1__srlcol_13__srlinst_Q15_UNCONNECTED), + .A0(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[0]), + .A1(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[1]), + .A2(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[2]), + .A3(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[3]) + ); + SRLC16E com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_srlrow_0__srlcol_60__srlinst ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_select_oq2bq_1_3115), + .D(com_tlm_u_tlm_rx_vc0_fifo_data_oqr_60_), + .Q(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_60_), + .CLK(NlwRenamedSig_OI_trn_clk), + .Q15(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_in_132_), + .A0(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[0]), + .A1(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[1]), + .A2(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[2]), + .A3(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[3]) + ); + SRLC16E com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_srlrow_0__srlcol_20__srlinst ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_select_oq2bq_3117), + .D(com_tlm_u_tlm_rx_vc0_fifo_data_oqr_20_), + .Q(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_20_), + .CLK(NlwRenamedSig_OI_trn_clk), + .Q15(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_in_92_), + .A0(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[0]), + .A1(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[1]), + .A2(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[2]), + .A3(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[3]) + ); + SRLC16E com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_srlrow_1__srlcol_14__srlinst ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_select_oq2bq_3117), + .D(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_in_86_), + .Q(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_86_), + .CLK(NlwRenamedSig_OI_trn_clk), + .Q15(NLW_com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_srlrow_1__srlcol_14__srlinst_Q15_UNCONNECTED), + .A0(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[0]), + .A1(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[1]), + .A2(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[2]), + .A3(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[3]) + ); + SRLC16E com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_srlrow_0__srlcol_46__srlinst ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_select_oq2bq_1_3115), + .D(com_tlm_u_tlm_rx_vc0_fifo_ep_oqr), + .Q(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_46_), + .CLK(NlwRenamedSig_OI_trn_clk), + .Q15(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_in_118_), + .A0(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[0]), + .A1(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[1]), + .A2(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[2]), + .A3(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[3]) + ); + SRLC16E com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_srlrow_0__srlcol_6__srlinst ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_select_oq2bq_3117), + .D(com_tlm_u_tlm_rx_vc0_fifo_data_oqr_6_), + .Q(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_6_), + .CLK(NlwRenamedSig_OI_trn_clk), + .Q15(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_in_78_), + .A0(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[0]), + .A1(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[1]), + .A2(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[2]), + .A3(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[3]) + ); + SRLC16E com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_srlrow_0__srlcol_54__srlinst ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_select_oq2bq_1_3115), + .D(com_tlm_u_tlm_rx_vc0_fifo_data_oqr_54_), + .Q(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_54_), + .CLK(NlwRenamedSig_OI_trn_clk), + .Q15(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_in_126_), + .A0(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[0]), + .A1(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[1]), + .A2(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[2]), + .A3(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[3]) + ); + SRLC16E com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_srlrow_0__srlcol_14__srlinst ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_select_oq2bq_3117), + .D(com_tlm_u_tlm_rx_vc0_fifo_data_oqr_14_), + .Q(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_14_), + .CLK(NlwRenamedSig_OI_trn_clk), + .Q15(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_in_86_), + .A0(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[0]), + .A1(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[1]), + .A2(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[2]), + .A3(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[3]) + ); + SRLC16E com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_srlrow_0__srlcol_7__srlinst ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_select_oq2bq_3117), + .D(com_tlm_u_tlm_rx_vc0_fifo_data_oqr_7_), + .Q(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_7_), + .CLK(NlwRenamedSig_OI_trn_clk), + .Q15(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_in_79_), + .A0(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[0]), + .A1(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[1]), + .A2(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[2]), + .A3(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[3]) + ); + SRLC16E com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_srlrow_1__srlcol_16__srlinst ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_select_oq2bq_3117), + .D(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_in_88_), + .Q(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_88_), + .CLK(NlwRenamedSig_OI_trn_clk), + .Q15(NLW_com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_srlrow_1__srlcol_16__srlinst_Q15_UNCONNECTED), + .A0(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[0]), + .A1(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[1]), + .A2(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[2]), + .A3(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[3]) + ); + SRLC16E com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_srlrow_0__srlcol_57__srlinst ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_select_oq2bq_1_3115), + .D(com_tlm_u_tlm_rx_vc0_fifo_data_oqr_57_), + .Q(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_57_), + .CLK(NlwRenamedSig_OI_trn_clk), + .Q15(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_in_129_), + .A0(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[0]), + .A1(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[1]), + .A2(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[2]), + .A3(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[3]) + ); + SRLC16E com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_srlrow_0__srlcol_17__srlinst ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_select_oq2bq_3117), + .D(com_tlm_u_tlm_rx_vc0_fifo_data_oqr_17_), + .Q(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_17_), + .CLK(NlwRenamedSig_OI_trn_clk), + .Q15(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_in_89_), + .A0(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[0]), + .A1(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[1]), + .A2(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[2]), + .A3(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[3]) + ); + SRLC16E com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_srlrow_1__srlcol_17__srlinst ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_select_oq2bq_3117), + .D(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_in_89_), + .Q(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_89_), + .CLK(NlwRenamedSig_OI_trn_clk), + .Q15(NLW_com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_srlrow_1__srlcol_17__srlinst_Q15_UNCONNECTED), + .A0(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[0]), + .A1(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[1]), + .A2(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[2]), + .A3(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[3]) + ); + SRLC16E com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_srlrow_0__srlcol_49__srlinst ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_select_oq2bq_1_3115), + .D(com_tlm_u_tlm_rx_vc0_fifo_data_oqr_49_), + .Q(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_49_), + .CLK(NlwRenamedSig_OI_trn_clk), + .Q15(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_in_121_), + .A0(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[0]), + .A1(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[1]), + .A2(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[2]), + .A3(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[3]) + ); + SRLC16E com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_srlrow_0__srlcol_9__srlinst ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_select_oq2bq_3117), + .D(com_tlm_u_tlm_rx_vc0_fifo_data_oqr_9_), + .Q(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_9_), + .CLK(NlwRenamedSig_OI_trn_clk), + .Q15(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_in_81_), + .A0(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[0]), + .A1(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[1]), + .A2(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[2]), + .A3(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[3]) + ); + SRLC16E com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_srlrow_1__srlcol_18__srlinst ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_select_oq2bq_3117), + .D(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_in_90_), + .Q(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_90_), + .CLK(NlwRenamedSig_OI_trn_clk), + .Q15(NLW_com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_srlrow_1__srlcol_18__srlinst_Q15_UNCONNECTED), + .A0(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[0]), + .A1(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[1]), + .A2(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[2]), + .A3(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[3]) + ); + SRLC16E com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_srlrow_0__srlcol_50__srlinst ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_select_oq2bq_1_3115), + .D(com_tlm_u_tlm_rx_vc0_fifo_data_oqr_50_), + .Q(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_50_), + .CLK(NlwRenamedSig_OI_trn_clk), + .Q15(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_in_122_), + .A0(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[0]), + .A1(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[1]), + .A2(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[2]), + .A3(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[3]) + ); + SRLC16E com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_srlrow_0__srlcol_10__srlinst ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_select_oq2bq_3117), + .D(com_tlm_u_tlm_rx_vc0_fifo_data_oqr_10_), + .Q(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_10_), + .CLK(NlwRenamedSig_OI_trn_clk), + .Q15(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_in_82_), + .A0(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[0]), + .A1(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[1]), + .A2(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[2]), + .A3(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[3]) + ); + SRLC16E com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_srlrow_1__srlcol_19__srlinst ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_select_oq2bq_3117), + .D(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_in_91_), + .Q(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_91_), + .CLK(NlwRenamedSig_OI_trn_clk), + .Q15(NLW_com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_srlrow_1__srlcol_19__srlinst_Q15_UNCONNECTED), + .A0(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[0]), + .A1(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[1]), + .A2(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[2]), + .A3(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[3]) + ); + SRLC16E com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_srlrow_0__srlcol_51__srlinst ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_select_oq2bq_1_3115), + .D(com_tlm_u_tlm_rx_vc0_fifo_data_oqr_51_), + .Q(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_51_), + .CLK(NlwRenamedSig_OI_trn_clk), + .Q15(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_in_123_), + .A0(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[0]), + .A1(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[1]), + .A2(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[2]), + .A3(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[3]) + ); + SRLC16E com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_srlrow_0__srlcol_11__srlinst ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_select_oq2bq_3117), + .D(com_tlm_u_tlm_rx_vc0_fifo_data_oqr_11_), + .Q(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_11_), + .CLK(NlwRenamedSig_OI_trn_clk), + .Q15(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_in_83_), + .A0(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[0]), + .A1(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[1]), + .A2(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[2]), + .A3(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[3]) + ); + SRLC16E com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_srlrow_1__srlcol_20__srlinst ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_select_oq2bq_3117), + .D(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_in_92_), + .Q(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_92_), + .CLK(NlwRenamedSig_OI_trn_clk), + .Q15(NLW_com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_srlrow_1__srlcol_20__srlinst_Q15_UNCONNECTED), + .A0(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[0]), + .A1(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[1]), + .A2(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[2]), + .A3(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[3]) + ); + SRLC16E com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_srlrow_0__srlcol_52__srlinst ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_select_oq2bq_1_3115), + .D(com_tlm_u_tlm_rx_vc0_fifo_data_oqr_52_), + .Q(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_52_), + .CLK(NlwRenamedSig_OI_trn_clk), + .Q15(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_in_124_), + .A0(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[0]), + .A1(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[1]), + .A2(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[2]), + .A3(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[3]) + ); + SRLC16E com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_srlrow_0__srlcol_12__srlinst ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_select_oq2bq_3117), + .D(com_tlm_u_tlm_rx_vc0_fifo_data_oqr_12_), + .Q(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_12_), + .CLK(NlwRenamedSig_OI_trn_clk), + .Q15(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_in_84_), + .A0(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[0]), + .A1(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[1]), + .A2(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[2]), + .A3(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[3]) + ); + SRLC16E com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_srlrow_0__srlcol_48__srlinst ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_select_oq2bq_1_3115), + .D(com_tlm_u_tlm_rx_vc0_fifo_data_oqr_48_), + .Q(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_48_), + .CLK(NlwRenamedSig_OI_trn_clk), + .Q15(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_in_120_), + .A0(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[0]), + .A1(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[1]), + .A2(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[2]), + .A3(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[3]) + ); + SRLC16E com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_srlrow_0__srlcol_8__srlinst ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_select_oq2bq_3117), + .D(com_tlm_u_tlm_rx_vc0_fifo_data_oqr_8_), + .Q(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_8_), + .CLK(NlwRenamedSig_OI_trn_clk), + .Q15(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_in_80_), + .A0(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[0]), + .A1(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[1]), + .A2(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[2]), + .A3(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[3]) + ); + SRLC16E com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_srlrow_0__srlcol_13__srlinst ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_select_oq2bq_3117), + .D(com_tlm_u_tlm_rx_vc0_fifo_data_oqr_13_), + .Q(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_13_), + .CLK(NlwRenamedSig_OI_trn_clk), + .Q15(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_in_85_), + .A0(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[0]), + .A1(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[1]), + .A2(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[2]), + .A3(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[3]) + ); + SRLC16E com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_srlrow_1__srlcol_22__srlinst ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_select_oq2bq_3117), + .D(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_in_94_), + .Q(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_94_), + .CLK(NlwRenamedSig_OI_trn_clk), + .Q15(NLW_com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_srlrow_1__srlcol_22__srlinst_Q15_UNCONNECTED), + .A0(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[0]), + .A1(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[1]), + .A2(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[2]), + .A3(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[3]) + ); + SRLC16E com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_srlrow_1__srlcol_61__srlinst ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_select_oq2bq_1_3115), + .D(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_in_133_), + .Q(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_133_), + .CLK(NlwRenamedSig_OI_trn_clk), + .Q15(NLW_com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_srlrow_1__srlcol_61__srlinst_Q15_UNCONNECTED), + .A0(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[0]), + .A1(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[1]), + .A2(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[2]), + .A3(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[3]) + ); + SRLC16E com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_srlrow_1__srlcol_57__srlinst ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_select_oq2bq_1_3115), + .D(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_in_129_), + .Q(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_129_), + .CLK(NlwRenamedSig_OI_trn_clk), + .Q15(NLW_com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_srlrow_1__srlcol_57__srlinst_Q15_UNCONNECTED), + .A0(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[0]), + .A1(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[1]), + .A2(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[2]), + .A3(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[3]) + ); + SRLC16E com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_srlrow_1__srlcol_23__srlinst ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_select_oq2bq_3117), + .D(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_in_95_), + .Q(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_95_), + .CLK(NlwRenamedSig_OI_trn_clk), + .Q15(NLW_com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_srlrow_1__srlcol_23__srlinst_Q15_UNCONNECTED), + .A0(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[0]), + .A1(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[1]), + .A2(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[2]), + .A3(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[3]) + ); + SRLC16E com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_srlrow_0__srlcol_55__srlinst ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_select_oq2bq_1_3115), + .D(com_tlm_u_tlm_rx_vc0_fifo_data_oqr_55_), + .Q(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_55_), + .CLK(NlwRenamedSig_OI_trn_clk), + .Q15(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_in_127_), + .A0(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[0]), + .A1(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[1]), + .A2(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[2]), + .A3(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[3]) + ); + SRLC16E com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_srlrow_0__srlcol_15__srlinst ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_select_oq2bq_3117), + .D(com_tlm_u_tlm_rx_vc0_fifo_data_oqr_15_), + .Q(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_15_), + .CLK(NlwRenamedSig_OI_trn_clk), + .Q15(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_in_87_), + .A0(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[0]), + .A1(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[1]), + .A2(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[2]), + .A3(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[3]) + ); + SRLC16E com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_srlrow_1__srlcol_24__srlinst ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_select_oq2bq_3117), + .D(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_in_96_), + .Q(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_96_), + .CLK(NlwRenamedSig_OI_trn_clk), + .Q15(NLW_com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_srlrow_1__srlcol_24__srlinst_Q15_UNCONNECTED), + .A0(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[0]), + .A1(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[1]), + .A2(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[2]), + .A3(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[3]) + ); + SRLC16E com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_srlrow_0__srlcol_56__srlinst ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_select_oq2bq_1_3115), + .D(com_tlm_u_tlm_rx_vc0_fifo_data_oqr_56_), + .Q(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_56_), + .CLK(NlwRenamedSig_OI_trn_clk), + .Q15(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_in_128_), + .A0(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[0]), + .A1(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[1]), + .A2(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[2]), + .A3(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[3]) + ); + SRLC16E com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_srlrow_0__srlcol_16__srlinst ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_select_oq2bq_3117), + .D(com_tlm_u_tlm_rx_vc0_fifo_data_oqr_16_), + .Q(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_16_), + .CLK(NlwRenamedSig_OI_trn_clk), + .Q15(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_in_88_), + .A0(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[0]), + .A1(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[1]), + .A2(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[2]), + .A3(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[3]) + ); + SRLC16E com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_srlrow_1__srlcol_25__srlinst ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_select_oq2bq_3117), + .D(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_in_97_), + .Q(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_97_), + .CLK(NlwRenamedSig_OI_trn_clk), + .Q15(NLW_com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_srlrow_1__srlcol_25__srlinst_Q15_UNCONNECTED), + .A0(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[0]), + .A1(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[1]), + .A2(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[2]), + .A3(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[3]) + ); + SRLC16E com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_srlrow_1__srlcol_26__srlinst ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_select_oq2bq_3117), + .D(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_in_98_), + .Q(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_98_), + .CLK(NlwRenamedSig_OI_trn_clk), + .Q15(NLW_com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_srlrow_1__srlcol_26__srlinst_Q15_UNCONNECTED), + .A0(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[0]), + .A1(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[1]), + .A2(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[2]), + .A3(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[3]) + ); + SRLC16E com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_srlrow_0__srlcol_58__srlinst ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_select_oq2bq_1_3115), + .D(com_tlm_u_tlm_rx_vc0_fifo_data_oqr_58_), + .Q(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_58_), + .CLK(NlwRenamedSig_OI_trn_clk), + .Q15(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_in_130_), + .A0(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[0]), + .A1(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[1]), + .A2(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[2]), + .A3(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[3]) + ); + SRLC16E com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_srlrow_0__srlcol_18__srlinst ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_select_oq2bq_3117), + .D(com_tlm_u_tlm_rx_vc0_fifo_data_oqr_18_), + .Q(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_18_), + .CLK(NlwRenamedSig_OI_trn_clk), + .Q15(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_in_90_), + .A0(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[0]), + .A1(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[1]), + .A2(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[2]), + .A3(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[3]) + ); + SRLC16E com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_srlrow_1__srlcol_27__srlinst ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_select_oq2bq_3117), + .D(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_in_99_), + .Q(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_99_), + .CLK(NlwRenamedSig_OI_trn_clk), + .Q15(NLW_com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_srlrow_1__srlcol_27__srlinst_Q15_UNCONNECTED), + .A0(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[0]), + .A1(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[1]), + .A2(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[2]), + .A3(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[3]) + ); + SRLC16E com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_srlrow_0__srlcol_59__srlinst ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_select_oq2bq_1_3115), + .D(com_tlm_u_tlm_rx_vc0_fifo_data_oqr_59_), + .Q(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_59_), + .CLK(NlwRenamedSig_OI_trn_clk), + .Q15(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_in_131_), + .A0(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[0]), + .A1(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[1]), + .A2(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[2]), + .A3(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[3]) + ); + SRLC16E com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_srlrow_0__srlcol_19__srlinst ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_select_oq2bq_3117), + .D(com_tlm_u_tlm_rx_vc0_fifo_data_oqr_19_), + .Q(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_19_), + .CLK(NlwRenamedSig_OI_trn_clk), + .Q15(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_in_91_), + .A0(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[0]), + .A1(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[1]), + .A2(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[2]), + .A3(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[3]) + ); + SRLC16E com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_srlrow_1__srlcol_28__srlinst ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_select_oq2bq_3117), + .D(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_in_100_), + .Q(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_100_), + .CLK(NlwRenamedSig_OI_trn_clk), + .Q15(NLW_com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_srlrow_1__srlcol_28__srlinst_Q15_UNCONNECTED), + .A0(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[0]), + .A1(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[1]), + .A2(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[2]), + .A3(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[3]) + ); + SRLC16E com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_srlrow_1__srlcol_67__srlinst ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_select_oq2bq_1_3115), + .D(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_in_139_), + .Q(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_139_), + .CLK(NlwRenamedSig_OI_trn_clk), + .Q15(NLW_com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_srlrow_1__srlcol_67__srlinst_Q15_UNCONNECTED), + .A0(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[0]), + .A1(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[1]), + .A2(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[2]), + .A3(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[3]) + ); + SRLC16E com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_srlrow_1__srlcol_63__srlinst ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_select_oq2bq_1_3115), + .D(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_in_135_), + .Q(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_135_), + .CLK(NlwRenamedSig_OI_trn_clk), + .Q15(NLW_com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_srlrow_1__srlcol_63__srlinst_Q15_UNCONNECTED), + .A0(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[0]), + .A1(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[1]), + .A2(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[2]), + .A3(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[3]) + ); + SRLC16E com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_srlrow_1__srlcol_29__srlinst ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_select_oq2bq_3117), + .D(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_in_101_), + .Q(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_101_), + .CLK(NlwRenamedSig_OI_trn_clk), + .Q15(NLW_com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_srlrow_1__srlcol_29__srlinst_Q15_UNCONNECTED), + .A0(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[0]), + .A1(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[1]), + .A2(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[2]), + .A3(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[3]) + ); + SRLC16E com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_srlrow_0__srlcol_61__srlinst ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_select_oq2bq_1_3115), + .D(com_tlm_u_tlm_rx_vc0_fifo_data_oqr_61_), + .Q(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_61_), + .CLK(NlwRenamedSig_OI_trn_clk), + .Q15(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_in_133_), + .A0(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[0]), + .A1(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[1]), + .A2(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[2]), + .A3(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[3]) + ); + SRLC16E com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_srlrow_1__srlcol_21__srlinst ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_select_oq2bq_3117), + .D(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_in_93_), + .Q(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_93_), + .CLK(NlwRenamedSig_OI_trn_clk), + .Q15(NLW_com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_srlrow_1__srlcol_21__srlinst_Q15_UNCONNECTED), + .A0(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[0]), + .A1(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[1]), + .A2(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[2]), + .A3(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[3]) + ); + SRLC16E com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_srlrow_0__srlcol_53__srlinst ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_select_oq2bq_1_3115), + .D(com_tlm_u_tlm_rx_vc0_fifo_data_oqr_53_), + .Q(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_53_), + .CLK(NlwRenamedSig_OI_trn_clk), + .Q15(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_in_125_), + .A0(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[0]), + .A1(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[1]), + .A2(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[2]), + .A3(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[3]) + ); + SRLC16E com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_srlrow_0__srlcol_62__srlinst ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_select_oq2bq_1_3115), + .D(com_tlm_u_tlm_rx_vc0_fifo_data_oqr_62_), + .Q(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_62_), + .CLK(NlwRenamedSig_OI_trn_clk), + .Q15(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_in_134_), + .A0(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[0]), + .A1(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[1]), + .A2(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[2]), + .A3(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[3]) + ); + SRLC16E com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_srlrow_0__srlcol_22__srlinst ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_select_oq2bq_3117), + .D(com_tlm_u_tlm_rx_vc0_fifo_data_oqr_22_), + .Q(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_22_), + .CLK(NlwRenamedSig_OI_trn_clk), + .Q15(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_in_94_), + .A0(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[0]), + .A1(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[1]), + .A2(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[2]), + .A3(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[3]) + ); + SRLC16E com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_srlrow_1__srlcol_31__srlinst ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_select_oq2bq_1_3115), + .D(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_in_103_), + .Q(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_103_), + .CLK(NlwRenamedSig_OI_trn_clk), + .Q15(NLW_com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_srlrow_1__srlcol_31__srlinst_Q15_UNCONNECTED), + .A0(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[0]), + .A1(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[1]), + .A2(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[2]), + .A3(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[3]) + ); + SRLC16E com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_srlrow_0__srlcol_63__srlinst ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_select_oq2bq_1_3115), + .D(com_tlm_u_tlm_rx_vc0_fifo_data_oqr_63_), + .Q(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_63_), + .CLK(NlwRenamedSig_OI_trn_clk), + .Q15(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_in_135_), + .A0(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[0]), + .A1(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[1]), + .A2(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[2]), + .A3(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[3]) + ); + SRLC16E com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_srlrow_0__srlcol_23__srlinst ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_select_oq2bq_3117), + .D(com_tlm_u_tlm_rx_vc0_fifo_data_oqr_23_), + .Q(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_23_), + .CLK(NlwRenamedSig_OI_trn_clk), + .Q15(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_in_95_), + .A0(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[0]), + .A1(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[1]), + .A2(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[2]), + .A3(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[3]) + ); + SRLC16E com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_srlrow_1__srlcol_32__srlinst ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_select_oq2bq_1_3115), + .D(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_in_104_), + .Q(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_104_), + .CLK(NlwRenamedSig_OI_trn_clk), + .Q15(NLW_com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_srlrow_1__srlcol_32__srlinst_Q15_UNCONNECTED), + .A0(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[0]), + .A1(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[1]), + .A2(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[2]), + .A3(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[3]) + ); + SRLC16E com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_srlrow_0__srlcol_64__srlinst ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_select_oq2bq_1_3115), + .D(com_tlm_u_tlm_rx_vc0_fifo_sof_oqr), + .Q(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_64_), + .CLK(NlwRenamedSig_OI_trn_clk), + .Q15(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_in_136_), + .A0(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[0]), + .A1(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[1]), + .A2(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[2]), + .A3(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[3]) + ); + SRLC16E com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_srlrow_0__srlcol_24__srlinst ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_select_oq2bq_3117), + .D(com_tlm_u_tlm_rx_vc0_fifo_data_oqr_24_), + .Q(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_24_), + .CLK(NlwRenamedSig_OI_trn_clk), + .Q15(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_in_96_), + .A0(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[0]), + .A1(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[1]), + .A2(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[2]), + .A3(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[3]) + ); + SRLC16E com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_srlrow_1__srlcol_33__srlinst ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_select_oq2bq_1_3115), + .D(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_in_105_), + .Q(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_105_), + .CLK(NlwRenamedSig_OI_trn_clk), + .Q15(NLW_com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_srlrow_1__srlcol_33__srlinst_Q15_UNCONNECTED), + .A0(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[0]), + .A1(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[1]), + .A2(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[2]), + .A3(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[3]) + ); + SRLC16E com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_srlrow_0__srlcol_65__srlinst ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_select_oq2bq_1_3115), + .D(com_tlm_u_tlm_rx_vc0_fifo_eof_oqr), + .Q(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_65_), + .CLK(NlwRenamedSig_OI_trn_clk), + .Q15(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_in_137_), + .A0(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[0]), + .A1(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[1]), + .A2(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[2]), + .A3(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[3]) + ); + SRLC16E com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_srlrow_0__srlcol_25__srlinst ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_select_oq2bq_3117), + .D(com_tlm_u_tlm_rx_vc0_fifo_data_oqr_25_), + .Q(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_25_), + .CLK(NlwRenamedSig_OI_trn_clk), + .Q15(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_in_97_), + .A0(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[0]), + .A1(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[1]), + .A2(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[2]), + .A3(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[3]) + ); + SRLC16E com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_srlrow_1__srlcol_34__srlinst ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_select_oq2bq_1_3115), + .D(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_in_106_), + .Q(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_106_), + .CLK(NlwRenamedSig_OI_trn_clk), + .Q15(NLW_com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_srlrow_1__srlcol_34__srlinst_Q15_UNCONNECTED), + .A0(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[0]), + .A1(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[1]), + .A2(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[2]), + .A3(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[3]) + ); + SRLC16E com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_srlrow_0__srlcol_26__srlinst ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_select_oq2bq_3117), + .D(com_tlm_u_tlm_rx_vc0_fifo_data_oqr_26_), + .Q(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_26_), + .CLK(NlwRenamedSig_OI_trn_clk), + .Q15(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_in_98_), + .A0(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[0]), + .A1(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[1]), + .A2(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[2]), + .A3(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[3]) + ); + SRLC16E com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_srlrow_1__srlcol_35__srlinst ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_select_oq2bq_1_3115), + .D(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_in_107_), + .Q(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_107_), + .CLK(NlwRenamedSig_OI_trn_clk), + .Q15(NLW_com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_srlrow_1__srlcol_35__srlinst_Q15_UNCONNECTED), + .A0(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[0]), + .A1(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[1]), + .A2(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[2]), + .A3(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[3]) + ); + SRLC16E com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_srlrow_0__srlcol_67__srlinst ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_select_oq2bq_1_3115), + .D(com_tlm_u_tlm_rx_vc0_fifo_rem_oqr), + .Q(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_67_), + .CLK(NlwRenamedSig_OI_trn_clk), + .Q15(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_in_139_), + .A0(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[0]), + .A1(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[1]), + .A2(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[2]), + .A3(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[3]) + ); + SRLC16E com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_srlrow_0__srlcol_27__srlinst ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_select_oq2bq_3117), + .D(com_tlm_u_tlm_rx_vc0_fifo_data_oqr_27_), + .Q(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_27_), + .CLK(NlwRenamedSig_OI_trn_clk), + .Q15(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_in_99_), + .A0(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[0]), + .A1(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[1]), + .A2(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[2]), + .A3(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[3]) + ); + SRLC16E com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_srlrow_1__srlcol_36__srlinst ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_select_oq2bq_1_3115), + .D(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_in_108_), + .Q(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_108_), + .CLK(NlwRenamedSig_OI_trn_clk), + .Q15(NLW_com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_srlrow_1__srlcol_36__srlinst_Q15_UNCONNECTED), + .A0(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[0]), + .A1(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[1]), + .A2(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[2]), + .A3(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[3]) + ); + SRLC16E com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_srlrow_0__srlcol_28__srlinst ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_select_oq2bq_3117), + .D(com_tlm_u_tlm_rx_vc0_fifo_data_oqr_28_), + .Q(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_28_), + .CLK(NlwRenamedSig_OI_trn_clk), + .Q15(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_in_100_), + .A0(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[0]), + .A1(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[1]), + .A2(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[2]), + .A3(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[3]) + ); + SRLC16E com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_srlrow_1__srlcol_37__srlinst ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_select_oq2bq_1_3115), + .D(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_in_109_), + .Q(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_109_), + .CLK(NlwRenamedSig_OI_trn_clk), + .Q15(NLW_com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_srlrow_1__srlcol_37__srlinst_Q15_UNCONNECTED), + .A0(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[0]), + .A1(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[1]), + .A2(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[2]), + .A3(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[3]) + ); + SRLC16E com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_srlrow_0__srlcol_29__srlinst ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_select_oq2bq_3117), + .D(com_tlm_u_tlm_rx_vc0_fifo_data_oqr_29_), + .Q(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_29_), + .CLK(NlwRenamedSig_OI_trn_clk), + .Q15(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_in_101_), + .A0(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[0]), + .A1(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[1]), + .A2(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[2]), + .A3(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[3]) + ); + SRLC16E com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_srlrow_1__srlcol_38__srlinst ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_select_oq2bq_1_3115), + .D(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_in_110_), + .Q(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_110_), + .CLK(NlwRenamedSig_OI_trn_clk), + .Q15(NLW_com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_srlrow_1__srlcol_38__srlinst_Q15_UNCONNECTED), + .A0(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[0]), + .A1(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[1]), + .A2(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[2]), + .A3(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[3]) + ); + SRLC16E com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_srlrow_0__srlcol_30__srlinst ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_select_oq2bq_1_3115), + .D(com_tlm_u_tlm_rx_vc0_fifo_data_oqr_30_), + .Q(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_30_), + .CLK(NlwRenamedSig_OI_trn_clk), + .Q15(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_in_102_), + .A0(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[0]), + .A1(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[1]), + .A2(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[2]), + .A3(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[3]) + ); + SRLC16E com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_srlrow_1__srlcol_39__srlinst ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_select_oq2bq_1_3115), + .D(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_in_111_), + .Q(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_111_), + .CLK(NlwRenamedSig_OI_trn_clk), + .Q15(NLW_com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_srlrow_1__srlcol_39__srlinst_Q15_UNCONNECTED), + .A0(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[0]), + .A1(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[1]), + .A2(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[2]), + .A3(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[3]) + ); + SRLC16E com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_srlrow_0__srlcol_31__srlinst ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_select_oq2bq_1_3115), + .D(com_tlm_u_tlm_rx_vc0_fifo_data_oqr_31_), + .Q(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_31_), + .CLK(NlwRenamedSig_OI_trn_clk), + .Q15(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_in_103_), + .A0(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[0]), + .A1(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[1]), + .A2(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[2]), + .A3(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[3]) + ); + SRLC16E com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_srlrow_1__srlcol_40__srlinst ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_select_oq2bq_1_3115), + .D(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_in_112_), + .Q(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_112_), + .CLK(NlwRenamedSig_OI_trn_clk), + .Q15(NLW_com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_srlrow_1__srlcol_40__srlinst_Q15_UNCONNECTED), + .A0(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[0]), + .A1(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[1]), + .A2(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[2]), + .A3(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[3]) + ); + SRLC16E com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_srlrow_1__srlcol_0__srlinst ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_select_oq2bq_3117), + .D(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_in_72_), + .Q(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_72_), + .CLK(NlwRenamedSig_OI_trn_clk), + .Q15(NLW_com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_srlrow_1__srlcol_0__srlinst_Q15_UNCONNECTED), + .A0(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[0]), + .A1(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[1]), + .A2(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[2]), + .A3(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[3]) + ); + SRLC16E com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_srlrow_0__srlcol_32__srlinst ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_select_oq2bq_1_3115), + .D(com_tlm_u_tlm_rx_vc0_fifo_data_oqr_32_), + .Q(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_32_), + .CLK(NlwRenamedSig_OI_trn_clk), + .Q15(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_in_104_), + .A0(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[0]), + .A1(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[1]), + .A2(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[2]), + .A3(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[3]) + ); + SRLC16E com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_srlrow_1__srlcol_41__srlinst ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_select_oq2bq_1_3115), + .D(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_in_113_), + .Q(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_113_), + .CLK(NlwRenamedSig_OI_trn_clk), + .Q15(NLW_com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_srlrow_1__srlcol_41__srlinst_Q15_UNCONNECTED), + .A0(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[0]), + .A1(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[1]), + .A2(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[2]), + .A3(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[3]) + ); + SRLC16E com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_srlrow_1__srlcol_1__srlinst ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_select_oq2bq_3117), + .D(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_in_73_), + .Q(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_73_), + .CLK(NlwRenamedSig_OI_trn_clk), + .Q15(NLW_com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_srlrow_1__srlcol_1__srlinst_Q15_UNCONNECTED), + .A0(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[0]), + .A1(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[1]), + .A2(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[2]), + .A3(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[3]) + ); + SRLC16E com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_srlrow_0__srlcol_33__srlinst ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_select_oq2bq_1_3115), + .D(com_tlm_u_tlm_rx_vc0_fifo_data_oqr_33_), + .Q(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_33_), + .CLK(NlwRenamedSig_OI_trn_clk), + .Q15(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_in_105_), + .A0(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[0]), + .A1(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[1]), + .A2(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[2]), + .A3(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[3]) + ); + SRLC16E com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_srlrow_1__srlcol_42__srlinst ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_select_oq2bq_1_3115), + .D(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_in_114_), + .Q(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_114_), + .CLK(NlwRenamedSig_OI_trn_clk), + .Q15(NLW_com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_srlrow_1__srlcol_42__srlinst_Q15_UNCONNECTED), + .A0(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[0]), + .A1(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[1]), + .A2(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[2]), + .A3(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[3]) + ); + SRLC16E com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_srlrow_1__srlcol_2__srlinst ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_select_oq2bq_3117), + .D(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_in_74_), + .Q(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_74_), + .CLK(NlwRenamedSig_OI_trn_clk), + .Q15(NLW_com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_srlrow_1__srlcol_2__srlinst_Q15_UNCONNECTED), + .A0(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[0]), + .A1(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[1]), + .A2(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[2]), + .A3(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[3]) + ); + SRLC16E com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_srlrow_0__srlcol_34__srlinst ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_select_oq2bq_1_3115), + .D(com_tlm_u_tlm_rx_vc0_fifo_data_oqr_34_), + .Q(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_34_), + .CLK(NlwRenamedSig_OI_trn_clk), + .Q15(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_in_106_), + .A0(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[0]), + .A1(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[1]), + .A2(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[2]), + .A3(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[3]) + ); + SRLC16E com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_srlrow_1__srlcol_43__srlinst ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_select_oq2bq_1_3115), + .D(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_in_115_), + .Q(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_115_), + .CLK(NlwRenamedSig_OI_trn_clk), + .Q15(NLW_com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_srlrow_1__srlcol_43__srlinst_Q15_UNCONNECTED), + .A0(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[0]), + .A1(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[1]), + .A2(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[2]), + .A3(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[3]) + ); + SRLC16E com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_srlrow_1__srlcol_3__srlinst ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_select_oq2bq_3117), + .D(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_in_75_), + .Q(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_75_), + .CLK(NlwRenamedSig_OI_trn_clk), + .Q15(NLW_com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_srlrow_1__srlcol_3__srlinst_Q15_UNCONNECTED), + .A0(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[0]), + .A1(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[1]), + .A2(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[2]), + .A3(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[3]) + ); + SRLC16E com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_srlrow_0__srlcol_35__srlinst ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_select_oq2bq_1_3115), + .D(com_tlm_u_tlm_rx_vc0_fifo_data_oqr_35_), + .Q(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_35_), + .CLK(NlwRenamedSig_OI_trn_clk), + .Q15(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_in_107_), + .A0(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[0]), + .A1(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[1]), + .A2(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[2]), + .A3(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[3]) + ); + SRLC16E com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_srlrow_1__srlcol_44__srlinst ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_select_oq2bq_1_3115), + .D(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_in_116_), + .Q(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_116_), + .CLK(NlwRenamedSig_OI_trn_clk), + .Q15(NLW_com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_srlrow_1__srlcol_44__srlinst_Q15_UNCONNECTED), + .A0(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[0]), + .A1(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[1]), + .A2(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[2]), + .A3(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[3]) + ); + SRLC16E com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_srlrow_1__srlcol_4__srlinst ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_select_oq2bq_3117), + .D(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_in_76_), + .Q(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_76_), + .CLK(NlwRenamedSig_OI_trn_clk), + .Q15(NLW_com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_srlrow_1__srlcol_4__srlinst_Q15_UNCONNECTED), + .A0(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[0]), + .A1(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[1]), + .A2(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[2]), + .A3(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[3]) + ); + SRLC16E com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_srlrow_0__srlcol_36__srlinst ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_select_oq2bq_1_3115), + .D(com_tlm_u_tlm_rx_vc0_fifo_data_oqr_36_), + .Q(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_36_), + .CLK(NlwRenamedSig_OI_trn_clk), + .Q15(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_in_108_), + .A0(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[0]), + .A1(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[1]), + .A2(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[2]), + .A3(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[3]) + ); + SRLC16E com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_srlrow_1__srlcol_45__srlinst ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_select_oq2bq_1_3115), + .D(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_in_117_), + .Q(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_117_), + .CLK(NlwRenamedSig_OI_trn_clk), + .Q15(NLW_com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_srlrow_1__srlcol_45__srlinst_Q15_UNCONNECTED), + .A0(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[0]), + .A1(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[1]), + .A2(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[2]), + .A3(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[3]) + ); + SRLC16E com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_srlrow_1__srlcol_5__srlinst ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_select_oq2bq_3117), + .D(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_in_77_), + .Q(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_77_), + .CLK(NlwRenamedSig_OI_trn_clk), + .Q15(NLW_com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_srlrow_1__srlcol_5__srlinst_Q15_UNCONNECTED), + .A0(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[0]), + .A1(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[1]), + .A2(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[2]), + .A3(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[3]) + ); + SRLC16E com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_srlrow_0__srlcol_37__srlinst ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_select_oq2bq_1_3115), + .D(com_tlm_u_tlm_rx_vc0_fifo_data_oqr_37_), + .Q(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_37_), + .CLK(NlwRenamedSig_OI_trn_clk), + .Q15(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_in_109_), + .A0(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[0]), + .A1(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[1]), + .A2(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[2]), + .A3(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[3]) + ); + SRLC16E com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_srlrow_1__srlcol_46__srlinst ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_select_oq2bq_1_3115), + .D(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_in_118_), + .Q(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_118_), + .CLK(NlwRenamedSig_OI_trn_clk), + .Q15(NLW_com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_srlrow_1__srlcol_46__srlinst_Q15_UNCONNECTED), + .A0(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[0]), + .A1(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[1]), + .A2(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[2]), + .A3(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[3]) + ); + SRLC16E com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_srlrow_1__srlcol_6__srlinst ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_select_oq2bq_3117), + .D(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_in_78_), + .Q(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_78_), + .CLK(NlwRenamedSig_OI_trn_clk), + .Q15(NLW_com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_srlrow_1__srlcol_6__srlinst_Q15_UNCONNECTED), + .A0(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[0]), + .A1(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[1]), + .A2(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[2]), + .A3(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[3]) + ); + SRLC16E com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_srlrow_0__srlcol_45__srlinst ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_select_oq2bq_1_3115), + .D(com_tlm_u_tlm_rx_vc0_fifo_data_oqr_45_), + .Q(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_45_), + .CLK(NlwRenamedSig_OI_trn_clk), + .Q15(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_in_117_), + .A0(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[0]), + .A1(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[1]), + .A2(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[2]), + .A3(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[3]) + ); + SRLC16E com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_srlrow_0__srlcol_5__srlinst ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_select_oq2bq_3117), + .D(com_tlm_u_tlm_rx_vc0_fifo_data_oqr_5_), + .Q(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_5_), + .CLK(NlwRenamedSig_OI_trn_clk), + .Q15(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_in_77_), + .A0(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[0]), + .A1(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[1]), + .A2(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[2]), + .A3(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[3]) + ); + SRLC16E com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_srlrow_1__srlcol_7__srlinst ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_select_oq2bq_3117), + .D(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_in_79_), + .Q(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_79_), + .CLK(NlwRenamedSig_OI_trn_clk), + .Q15(NLW_com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_srlrow_1__srlcol_7__srlinst_Q15_UNCONNECTED), + .A0(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[0]), + .A1(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[1]), + .A2(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[2]), + .A3(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[3]) + ); + SRLC16E com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_srlrow_0__srlcol_39__srlinst ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_select_oq2bq_1_3115), + .D(com_tlm_u_tlm_rx_vc0_fifo_data_oqr_39_), + .Q(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_39_), + .CLK(NlwRenamedSig_OI_trn_clk), + .Q15(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_in_111_), + .A0(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[0]), + .A1(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[1]), + .A2(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[2]), + .A3(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[3]) + ); + SRLC16E com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_srlrow_1__srlcol_12__srlinst ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_select_oq2bq_3117), + .D(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_in_84_), + .Q(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_84_), + .CLK(NlwRenamedSig_OI_trn_clk), + .Q15(NLW_com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_srlrow_1__srlcol_12__srlinst_Q15_UNCONNECTED), + .A0(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[0]), + .A1(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[1]), + .A2(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[2]), + .A3(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[3]) + ); + SRLC16E com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_srlrow_0__srlcol_44__srlinst ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_select_oq2bq_1_3115), + .D(com_tlm_u_tlm_rx_vc0_fifo_data_oqr_44_), + .Q(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_44_), + .CLK(NlwRenamedSig_OI_trn_clk), + .Q15(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_in_116_), + .A0(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[0]), + .A1(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[1]), + .A2(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[2]), + .A3(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[3]) + ); + SRLC16E com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_srlrow_0__srlcol_40__srlinst ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_select_oq2bq_1_3115), + .D(com_tlm_u_tlm_rx_vc0_fifo_data_oqr_40_), + .Q(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_40_), + .CLK(NlwRenamedSig_OI_trn_clk), + .Q15(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_in_112_), + .A0(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[0]), + .A1(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[1]), + .A2(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[2]), + .A3(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[3]) + ); + SRLC16E com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_srlrow_1__srlcol_49__srlinst ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_select_oq2bq_1_3115), + .D(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_in_121_), + .Q(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_121_), + .CLK(NlwRenamedSig_OI_trn_clk), + .Q15(NLW_com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_srlrow_1__srlcol_49__srlinst_Q15_UNCONNECTED), + .A0(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[0]), + .A1(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[1]), + .A2(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[2]), + .A3(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[3]) + ); + SRLC16E com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_srlrow_1__srlcol_15__srlinst ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_select_oq2bq_3117), + .D(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_in_87_), + .Q(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_87_), + .CLK(NlwRenamedSig_OI_trn_clk), + .Q15(NLW_com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_srlrow_1__srlcol_15__srlinst_Q15_UNCONNECTED), + .A0(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[0]), + .A1(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[1]), + .A2(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[2]), + .A3(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[3]) + ); + SRLC16E com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_srlrow_0__srlcol_47__srlinst ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_select_oq2bq_1_3115), + .D(com_tlm_u_tlm_rx_vc0_fifo_data_oqr_47_), + .Q(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_47_), + .CLK(NlwRenamedSig_OI_trn_clk), + .Q15(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_in_119_), + .A0(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[0]), + .A1(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[1]), + .A2(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[2]), + .A3(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[3]) + ); + SRLC16E com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_srlrow_1__srlcol_50__srlinst ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_select_oq2bq_1_3115), + .D(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_in_122_), + .Q(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_122_), + .CLK(NlwRenamedSig_OI_trn_clk), + .Q15(NLW_com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_srlrow_1__srlcol_50__srlinst_Q15_UNCONNECTED), + .A0(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[0]), + .A1(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[1]), + .A2(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[2]), + .A3(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[3]) + ); + SRLC16E com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_srlrow_1__srlcol_64__srlinst ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_select_oq2bq_1_3115), + .D(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_in_136_), + .Q(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_136_), + .CLK(NlwRenamedSig_OI_trn_clk), + .Q15(NLW_com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_srlrow_1__srlcol_64__srlinst_Q15_UNCONNECTED), + .A0(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[0]), + .A1(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[1]), + .A2(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[2]), + .A3(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[3]) + ); + SRLC16E com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_srlrow_1__srlcol_51__srlinst ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_select_oq2bq_1_3115), + .D(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_in_123_), + .Q(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_123_), + .CLK(NlwRenamedSig_OI_trn_clk), + .Q15(NLW_com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_srlrow_1__srlcol_51__srlinst_Q15_UNCONNECTED), + .A0(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[0]), + .A1(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[1]), + .A2(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[2]), + .A3(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[3]) + ); + SRLC16E com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_srlrow_1__srlcol_65__srlinst ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_select_oq2bq_1_3115), + .D(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_in_137_), + .Q(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_137_), + .CLK(NlwRenamedSig_OI_trn_clk), + .Q15(NLW_com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_srlrow_1__srlcol_65__srlinst_Q15_UNCONNECTED), + .A0(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[0]), + .A1(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[1]), + .A2(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[2]), + .A3(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[3]) + ); + SRLC16E com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_srlrow_1__srlcol_52__srlinst ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_select_oq2bq_1_3115), + .D(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_in_124_), + .Q(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_124_), + .CLK(NlwRenamedSig_OI_trn_clk), + .Q15(NLW_com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_srlrow_1__srlcol_52__srlinst_Q15_UNCONNECTED), + .A0(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[0]), + .A1(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[1]), + .A2(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[2]), + .A3(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[3]) + ); + SRLC16E com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_srlrow_1__srlcol_48__srlinst ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_select_oq2bq_1_3115), + .D(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_in_120_), + .Q(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_120_), + .CLK(NlwRenamedSig_OI_trn_clk), + .Q15(NLW_com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_srlrow_1__srlcol_48__srlinst_Q15_UNCONNECTED), + .A0(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[0]), + .A1(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[1]), + .A2(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[2]), + .A3(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[3]) + ); + SRLC16E com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_srlrow_1__srlcol_8__srlinst ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_select_oq2bq_3117), + .D(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_in_80_), + .Q(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_80_), + .CLK(NlwRenamedSig_OI_trn_clk), + .Q15(NLW_com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_srlrow_1__srlcol_8__srlinst_Q15_UNCONNECTED), + .A0(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[0]), + .A1(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[1]), + .A2(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[2]), + .A3(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[3]) + ); + SRLC16E com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_srlrow_1__srlcol_53__srlinst ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_select_oq2bq_1_3115), + .D(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_in_125_), + .Q(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_125_), + .CLK(NlwRenamedSig_OI_trn_clk), + .Q15(NLW_com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_srlrow_1__srlcol_53__srlinst_Q15_UNCONNECTED), + .A0(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[0]), + .A1(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[1]), + .A2(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[2]), + .A3(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[3]) + ); + SRLC16E com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_srlrow_1__srlcol_58__srlinst ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_select_oq2bq_1_3115), + .D(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_in_130_), + .Q(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_130_), + .CLK(NlwRenamedSig_OI_trn_clk), + .Q15(NLW_com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_srlrow_1__srlcol_58__srlinst_Q15_UNCONNECTED), + .A0(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[0]), + .A1(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[1]), + .A2(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[2]), + .A3(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[3]) + ); + SRLC16E com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_srlrow_1__srlcol_54__srlinst ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_select_oq2bq_1_3115), + .D(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_in_126_), + .Q(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_126_), + .CLK(NlwRenamedSig_OI_trn_clk), + .Q15(NLW_com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_srlrow_1__srlcol_54__srlinst_Q15_UNCONNECTED), + .A0(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[0]), + .A1(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[1]), + .A2(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[2]), + .A3(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[3]) + ); + SRLC16E com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_srlrow_1__srlcol_60__srlinst ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_select_oq2bq_1_3115), + .D(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_in_132_), + .Q(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_132_), + .CLK(NlwRenamedSig_OI_trn_clk), + .Q15(NLW_com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_srlrow_1__srlcol_60__srlinst_Q15_UNCONNECTED), + .A0(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[0]), + .A1(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[1]), + .A2(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[2]), + .A3(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[3]) + ); + SRLC16E com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_srlrow_1__srlcol_59__srlinst ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_select_oq2bq_1_3115), + .D(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_in_131_), + .Q(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_131_), + .CLK(NlwRenamedSig_OI_trn_clk), + .Q15(NLW_com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_srlrow_1__srlcol_59__srlinst_Q15_UNCONNECTED), + .A0(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[0]), + .A1(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[1]), + .A2(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[2]), + .A3(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[3]) + ); + SRLC16E com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_srlrow_1__srlcol_55__srlinst ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_select_oq2bq_1_3115), + .D(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_in_127_), + .Q(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_127_), + .CLK(NlwRenamedSig_OI_trn_clk), + .Q15(NLW_com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_srlrow_1__srlcol_55__srlinst_Q15_UNCONNECTED), + .A0(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[0]), + .A1(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[1]), + .A2(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[2]), + .A3(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[3]) + ); + SRLC16E com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_srlrow_0__srlcol_38__srlinst ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_select_oq2bq_1_3115), + .D(com_tlm_u_tlm_rx_vc0_fifo_data_oqr_38_), + .Q(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_38_), + .CLK(NlwRenamedSig_OI_trn_clk), + .Q15(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_in_110_), + .A0(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[0]), + .A1(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[1]), + .A2(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[2]), + .A3(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[3]) + ); + SRLC16E com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_srlrow_1__srlcol_47__srlinst ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_select_oq2bq_1_3115), + .D(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_in_119_), + .Q(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_119_), + .CLK(NlwRenamedSig_OI_trn_clk), + .Q15(NLW_com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_srlrow_1__srlcol_47__srlinst_Q15_UNCONNECTED), + .A0(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[0]), + .A1(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[1]), + .A2(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[2]), + .A3(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[3]) + ); + SRLC16E com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_srlrow_1__srlcol_56__srlinst ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_select_oq2bq_1_3115), + .D(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_in_128_), + .Q(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_128_), + .CLK(NlwRenamedSig_OI_trn_clk), + .Q15(NLW_com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_srlrow_1__srlcol_56__srlinst_Q15_UNCONNECTED), + .A0(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[0]), + .A1(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[1]), + .A2(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[2]), + .A3(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[3]) + ); + SRLC16E com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_srlrow_1__srlcol_62__srlinst ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_select_oq2bq_1_3115), + .D(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_in_134_), + .Q(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_134_), + .CLK(NlwRenamedSig_OI_trn_clk), + .Q15(NLW_com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_srlrow_1__srlcol_62__srlinst_Q15_UNCONNECTED), + .A0(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[0]), + .A1(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[1]), + .A2(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[2]), + .A3(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[3]) + ); + FDS com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_0_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_un1_raddr_lo_1_axb_0_3352), + .Q(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[0]), + .S(plm_link_up_i) + ); + FDS com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_un1_raddr_lo_1_s_1_5), + .Q(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[1]), + .S(plm_link_up_i) + ); + FDS com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_2_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_un1_raddr_lo_1_s_2_5), + .Q(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[2]), + .S(plm_link_up_i) + ); + FDS com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_3_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_un1_raddr_lo_1_s_3_5), + .Q(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[3]), + .S(plm_link_up_i) + ); + FDRE com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_hi_0_ ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_un1_bkp_i_3_i_3342), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_hi_62[0]), + .Q(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_hi[0]), + .R(plm_link_up_i) + ); + FDRE com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_hi_1_ ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_un1_bkp_i_3_i_3342), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_hi_62[1]), + .Q(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_hi[1]), + .R(plm_link_up_i) + ); + FDRE com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_control_bits_d_o_64_ ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_9597_i_3418), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_d_o_d_m_64__3348), + .Q(com_tlm_u_tlm_rx_vc0_fifo_data_bqr_64_), + .R(plm_link_up_i) + ); + FDRE com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_control_bits_d_o_65_ ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_9597_i_3418), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_d_o_d_m_65__3347), + .Q(com_tlm_u_tlm_rx_vc0_fifo_data_bqr_65_), + .R(plm_link_up_i) + ); + FDRE com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_control_bits_d_o_67_ ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_9597_i_3418), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_d_o_d_m_67__3346), + .Q(com_tlm_u_tlm_rx_vc0_fifo_data_bqr_67_), + .R(plm_link_up_i) + ); + FDRE com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_nxt_vld_o ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_un1_bkp_i_1_i_3341), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_hi_eq_1_m_i_3345), + .Q(com_tlm_u_tlm_rx_vc0_fifo_nxt_vld_bqr), + .R(plm_link_up_i) + ); + FDRE com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_vld_o ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_9597_i_3418), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_nxt_vld_bqr), + .Q(com_tlm_u_tlm_rx_vc0_fifo_data_vld_bqr), + .R(plm_link_up_i) + ); + MUXCY_L com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_un1_raddr_lo_1_cry_0 ( + .CI(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_GND_3335), + .DI(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[0]), + .LO(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_un1_raddr_lo_1_cry_0_3336), + .S(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_un1_raddr_lo_1_axb_0_3352) + ); + MUXCY_L com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_un1_raddr_lo_1_cry_1 ( + .CI(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_un1_raddr_lo_1_cry_0_3336), + .DI(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[1]), + .LO(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_un1_raddr_lo_1_cry_1_3337), + .S(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_un1_raddr_lo_1_axb_1_3351) + ); + XORCY com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_un1_raddr_lo_1_s_1 ( + .CI(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_un1_raddr_lo_1_cry_0_3336), + .LI(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_un1_raddr_lo_1_axb_1_3351), + .O(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_un1_raddr_lo_1_s_1_5) + ); + MUXCY_L com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_un1_raddr_lo_1_cry_2 ( + .CI(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_un1_raddr_lo_1_cry_1_3337), + .DI(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[2]), + .LO(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_un1_raddr_lo_1_cry_2_3338), + .S(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_un1_raddr_lo_1_axb_2_3350) + ); + XORCY com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_un1_raddr_lo_1_s_2 ( + .CI(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_un1_raddr_lo_1_cry_1_3337), + .LI(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_un1_raddr_lo_1_axb_2_3350), + .O(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_un1_raddr_lo_1_s_2_5) + ); + XORCY com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_un1_raddr_lo_1_s_3 ( + .CI(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_un1_raddr_lo_1_cry_2_3338), + .LI(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_un1_raddr_lo_1_axb_3_3349), + .O(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_un1_raddr_lo_1_s_3_5) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_outcol_multi_outcol_67__un613_d_o_d_0_.INIT = 4'h8; + LUT2 com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_outcol_multi_outcol_67__un613_d_o_d_0_ ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_hi[0]), + .I1(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_67_), + .O(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_un613_d_o_d[0]) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_outcol_multi_outcol_65__un597_d_o_d_0_.INIT = 4'h8; + LUT2 com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_outcol_multi_outcol_65__un597_d_o_d_0_ ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_hi[0]), + .I1(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_65_), + .O(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_un597_d_o_d[0]) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_outcol_multi_outcol_64__un589_d_o_d_0_.INIT = 4'h8; + LUT2 com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_outcol_multi_outcol_64__un589_d_o_d_0_ ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_hi[0]), + .I1(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_64_), + .O(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_un589_d_o_d[0]) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_un13_nxt_vld_o_en_1.INIT = 4'h1; + LUT2 com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_un13_nxt_vld_o_en_1 ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[1]), + .I1(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[2]), + .O(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_un13_nxt_vld_o_en_1_3340) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_overwrap_0.INIT = 4'h8; + LUT2_L com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_overwrap_0 ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[0]), + .I1(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[3]), + .LO(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_overwrap_0_3339) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_overwrap_3.INIT = 16'h8000; + LUT4 com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_overwrap_3 ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[1]), + .I1(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[2]), + .I2(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_overwrap_0_3339), + .I3(com_tlm_u_tlm_rx_vc0_fifo_select_oq2bq_3117), + .O(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_overwrap_3_3344) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_srl_ren.INIT = 4'h4; + LUT2 com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_srl_ren ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_N_14337), + .I1(com_tlm_u_tlm_rx_vc0_fifo_data_vld_bqr), + .O(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_srl_ren_0) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_un13_nxt_vld_o_en.INIT = 16'h0100; + LUT4 com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_un13_nxt_vld_o_en ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_srl_ren_0), + .I1(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[0]), + .I2(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[3]), + .I3(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_un13_nxt_vld_o_en_1_3340), + .O(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_un13_nxt_vld_o_en_3343) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_un1_bkp_i_1_i.INIT = 4'hE; + LUT2 com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_un1_bkp_i_1_i ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_un13_nxt_vld_o_en_3343), + .I1(com_tlm_u_tlm_rx_vc0_fifo_select_oq2bq_3117), + .O(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_un1_bkp_i_1_i_3341) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_un1_raddr_lo_1_axb_0.INIT = 8'h96; + LUT3 com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_un1_raddr_lo_1_axb_0 ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_d_o_0_sqmuxa_3353), + .I1(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[0]), + .I2(com_tlm_u_tlm_rx_vc0_fifo_select_oq2bq_3117), + .O(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_un1_raddr_lo_1_axb_0_3352) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_un1_bkp_i_3_i.INIT = 16'h44F4; + LUT4 com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_un1_bkp_i_3_i ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_d_o_0_sqmuxa_3353), + .I1(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_overwrap_3_3344), + .I2(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_un13_nxt_vld_o_en_3343), + .I3(com_tlm_u_tlm_rx_vc0_fifo_select_oq2bq_3117), + .O(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_un1_bkp_i_3_i_3342) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_9533_i.INIT = 16'hECA0; + LUT4_L com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_9533_i ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_hi[0]), + .I1(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_hi[1]), + .I2(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_63_), + .I3(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_135_), + .LO(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_9533_i_3354) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_9534_i.INIT = 16'hECA0; + LUT4_L com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_9534_i ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_hi[0]), + .I1(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_hi[1]), + .I2(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_62_), + .I3(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_134_), + .LO(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_9534_i_3355) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_9535_i.INIT = 16'hECA0; + LUT4_L com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_9535_i ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_hi[0]), + .I1(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_hi[1]), + .I2(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_61_), + .I3(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_133_), + .LO(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_9535_i_3356) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_9536_i.INIT = 16'hECA0; + LUT4_L com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_9536_i ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_hi[0]), + .I1(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_hi[1]), + .I2(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_60_), + .I3(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_132_), + .LO(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_9536_i_3357) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_9537_i.INIT = 16'hECA0; + LUT4_L com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_9537_i ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_hi[0]), + .I1(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_hi[1]), + .I2(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_59_), + .I3(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_131_), + .LO(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_9537_i_3358) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_9538_i.INIT = 16'hECA0; + LUT4_L com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_9538_i ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_hi[0]), + .I1(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_hi[1]), + .I2(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_58_), + .I3(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_130_), + .LO(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_9538_i_3359) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_9539_i.INIT = 16'hECA0; + LUT4_L com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_9539_i ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_hi[0]), + .I1(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_hi[1]), + .I2(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_57_), + .I3(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_129_), + .LO(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_9539_i_3360) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_9540_i.INIT = 16'hECA0; + LUT4_L com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_9540_i ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_hi[0]), + .I1(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_hi[1]), + .I2(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_56_), + .I3(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_128_), + .LO(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_9540_i_3361) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_9541_i.INIT = 16'hECA0; + LUT4_L com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_9541_i ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_hi[0]), + .I1(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_hi[1]), + .I2(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_55_), + .I3(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_127_), + .LO(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_9541_i_3362) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_9542_i.INIT = 16'hECA0; + LUT4_L com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_9542_i ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_hi[0]), + .I1(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_hi[1]), + .I2(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_54_), + .I3(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_126_), + .LO(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_9542_i_3363) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_9543_i.INIT = 16'hECA0; + LUT4_L com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_9543_i ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_hi[0]), + .I1(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_hi[1]), + .I2(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_53_), + .I3(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_125_), + .LO(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_9543_i_3364) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_9544_i.INIT = 16'hECA0; + LUT4_L com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_9544_i ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_hi[0]), + .I1(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_hi[1]), + .I2(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_52_), + .I3(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_124_), + .LO(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_9544_i_3365) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_9545_i.INIT = 16'hECA0; + LUT4_L com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_9545_i ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_hi[0]), + .I1(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_hi[1]), + .I2(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_51_), + .I3(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_123_), + .LO(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_9545_i_3366) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_9546_i.INIT = 16'hECA0; + LUT4_L com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_9546_i ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_hi[0]), + .I1(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_hi[1]), + .I2(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_50_), + .I3(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_122_), + .LO(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_9546_i_3367) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_9547_i.INIT = 16'hECA0; + LUT4_L com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_9547_i ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_hi[0]), + .I1(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_hi[1]), + .I2(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_49_), + .I3(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_121_), + .LO(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_9547_i_3368) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_9548_i.INIT = 16'hECA0; + LUT4_L com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_9548_i ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_hi[0]), + .I1(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_hi[1]), + .I2(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_48_), + .I3(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_120_), + .LO(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_9548_i_3369) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_9549_i.INIT = 16'hECA0; + LUT4_L com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_9549_i ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_hi[0]), + .I1(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_hi[1]), + .I2(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_47_), + .I3(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_119_), + .LO(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_9549_i_3370) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_9550_i.INIT = 16'hECA0; + LUT4_L com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_9550_i ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_hi[0]), + .I1(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_hi[1]), + .I2(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_46_), + .I3(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_118_), + .LO(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_9550_i_3371) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_9551_i.INIT = 16'hECA0; + LUT4_L com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_9551_i ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_hi[0]), + .I1(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_hi[1]), + .I2(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_45_), + .I3(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_117_), + .LO(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_9551_i_3372) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_9552_i.INIT = 16'hECA0; + LUT4_L com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_9552_i ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_hi[0]), + .I1(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_hi[1]), + .I2(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_44_), + .I3(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_116_), + .LO(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_9552_i_3373) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_9553_i.INIT = 16'hECA0; + LUT4_L com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_9553_i ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_hi[0]), + .I1(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_hi[1]), + .I2(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_43_), + .I3(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_115_), + .LO(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_9553_i_3374) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_9554_i.INIT = 16'hECA0; + LUT4_L com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_9554_i ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_hi[0]), + .I1(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_hi[1]), + .I2(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_42_), + .I3(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_114_), + .LO(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_9554_i_3375) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_9555_i.INIT = 16'hECA0; + LUT4_L com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_9555_i ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_hi[0]), + .I1(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_hi[1]), + .I2(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_41_), + .I3(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_113_), + .LO(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_9555_i_3376) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_9556_i.INIT = 16'hECA0; + LUT4_L com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_9556_i ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_hi[0]), + .I1(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_hi[1]), + .I2(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_40_), + .I3(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_112_), + .LO(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_9556_i_3377) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_9557_i.INIT = 16'hECA0; + LUT4_L com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_9557_i ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_hi[0]), + .I1(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_hi[1]), + .I2(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_39_), + .I3(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_111_), + .LO(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_9557_i_3378) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_9558_i.INIT = 16'hECA0; + LUT4_L com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_9558_i ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_hi[0]), + .I1(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_hi[1]), + .I2(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_38_), + .I3(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_110_), + .LO(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_9558_i_3379) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_9559_i.INIT = 16'hECA0; + LUT4_L com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_9559_i ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_hi[0]), + .I1(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_hi[1]), + .I2(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_37_), + .I3(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_109_), + .LO(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_9559_i_3380) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_9560_i.INIT = 16'hECA0; + LUT4_L com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_9560_i ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_hi[0]), + .I1(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_hi[1]), + .I2(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_36_), + .I3(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_108_), + .LO(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_9560_i_3381) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_9561_i.INIT = 16'hECA0; + LUT4_L com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_9561_i ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_hi[0]), + .I1(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_hi[1]), + .I2(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_35_), + .I3(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_107_), + .LO(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_9561_i_3382) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_9562_i.INIT = 16'hECA0; + LUT4_L com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_9562_i ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_hi[0]), + .I1(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_hi[1]), + .I2(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_34_), + .I3(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_106_), + .LO(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_9562_i_3383) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_9563_i.INIT = 16'hECA0; + LUT4_L com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_9563_i ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_hi[0]), + .I1(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_hi[1]), + .I2(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_33_), + .I3(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_105_), + .LO(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_9563_i_3384) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_9564_i.INIT = 16'hECA0; + LUT4_L com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_9564_i ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_hi[0]), + .I1(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_hi[1]), + .I2(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_32_), + .I3(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_104_), + .LO(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_9564_i_3385) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_9565_i.INIT = 16'hECA0; + LUT4_L com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_9565_i ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_hi[0]), + .I1(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_hi[1]), + .I2(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_31_), + .I3(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_103_), + .LO(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_9565_i_3386) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_9566_i.INIT = 16'hECA0; + LUT4_L com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_9566_i ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_hi[0]), + .I1(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_hi[1]), + .I2(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_30_), + .I3(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_102_), + .LO(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_9566_i_3387) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_9567_i.INIT = 16'hECA0; + LUT4_L com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_9567_i ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_hi[0]), + .I1(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_hi[1]), + .I2(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_29_), + .I3(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_101_), + .LO(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_9567_i_3388) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_9568_i.INIT = 16'hECA0; + LUT4_L com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_9568_i ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_hi[0]), + .I1(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_hi[1]), + .I2(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_28_), + .I3(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_100_), + .LO(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_9568_i_3389) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_9569_i.INIT = 16'hECA0; + LUT4_L com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_9569_i ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_hi[0]), + .I1(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_hi[1]), + .I2(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_27_), + .I3(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_99_), + .LO(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_9569_i_3390) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_9570_i.INIT = 16'hECA0; + LUT4_L com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_9570_i ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_hi[0]), + .I1(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_hi[1]), + .I2(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_26_), + .I3(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_98_), + .LO(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_9570_i_3391) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_9571_i.INIT = 16'hECA0; + LUT4_L com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_9571_i ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_hi[0]), + .I1(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_hi[1]), + .I2(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_25_), + .I3(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_97_), + .LO(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_9571_i_3392) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_9572_i.INIT = 16'hECA0; + LUT4_L com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_9572_i ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_hi[0]), + .I1(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_hi[1]), + .I2(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_24_), + .I3(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_96_), + .LO(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_9572_i_3393) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_9573_i.INIT = 16'hECA0; + LUT4_L com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_9573_i ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_hi[0]), + .I1(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_hi[1]), + .I2(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_23_), + .I3(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_95_), + .LO(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_9573_i_3394) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_9574_i.INIT = 16'hECA0; + LUT4_L com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_9574_i ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_hi[0]), + .I1(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_hi[1]), + .I2(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_22_), + .I3(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_94_), + .LO(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_9574_i_3395) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_9575_i.INIT = 16'hECA0; + LUT4_L com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_9575_i ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_hi[0]), + .I1(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_hi[1]), + .I2(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_21_), + .I3(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_93_), + .LO(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_9575_i_3396) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_9576_i.INIT = 16'hECA0; + LUT4_L com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_9576_i ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_hi[0]), + .I1(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_hi[1]), + .I2(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_20_), + .I3(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_92_), + .LO(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_9576_i_3397) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_9577_i.INIT = 16'hECA0; + LUT4_L com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_9577_i ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_hi[0]), + .I1(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_hi[1]), + .I2(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_19_), + .I3(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_91_), + .LO(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_9577_i_3398) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_9578_i.INIT = 16'hECA0; + LUT4_L com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_9578_i ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_hi[0]), + .I1(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_hi[1]), + .I2(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_18_), + .I3(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_90_), + .LO(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_9578_i_3399) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_9579_i.INIT = 16'hECA0; + LUT4_L com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_9579_i ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_hi[0]), + .I1(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_hi[1]), + .I2(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_17_), + .I3(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_89_), + .LO(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_9579_i_3400) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_9580_i.INIT = 16'hECA0; + LUT4_L com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_9580_i ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_hi[0]), + .I1(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_hi[1]), + .I2(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_16_), + .I3(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_88_), + .LO(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_9580_i_3401) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_9581_i.INIT = 16'hECA0; + LUT4_L com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_9581_i ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_hi[0]), + .I1(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_hi[1]), + .I2(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_15_), + .I3(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_87_), + .LO(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_9581_i_3402) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_9582_i.INIT = 16'hECA0; + LUT4_L com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_9582_i ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_hi[0]), + .I1(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_hi[1]), + .I2(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_14_), + .I3(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_86_), + .LO(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_9582_i_3403) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_9583_i.INIT = 16'hECA0; + LUT4_L com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_9583_i ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_hi[0]), + .I1(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_hi[1]), + .I2(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_13_), + .I3(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_85_), + .LO(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_9583_i_3404) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_9584_i.INIT = 16'hECA0; + LUT4_L com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_9584_i ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_hi[0]), + .I1(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_hi[1]), + .I2(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_12_), + .I3(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_84_), + .LO(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_9584_i_3405) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_9585_i.INIT = 16'hECA0; + LUT4_L com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_9585_i ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_hi[0]), + .I1(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_hi[1]), + .I2(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_11_), + .I3(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_83_), + .LO(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_9585_i_3406) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_9586_i.INIT = 16'hECA0; + LUT4_L com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_9586_i ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_hi[0]), + .I1(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_hi[1]), + .I2(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_10_), + .I3(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_82_), + .LO(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_9586_i_3407) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_9587_i.INIT = 16'hECA0; + LUT4_L com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_9587_i ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_hi[0]), + .I1(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_hi[1]), + .I2(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_9_), + .I3(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_81_), + .LO(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_9587_i_3408) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_9588_i.INIT = 16'hECA0; + LUT4_L com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_9588_i ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_hi[0]), + .I1(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_hi[1]), + .I2(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_8_), + .I3(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_80_), + .LO(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_9588_i_3409) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_9589_i.INIT = 16'hECA0; + LUT4_L com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_9589_i ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_hi[0]), + .I1(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_hi[1]), + .I2(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_7_), + .I3(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_79_), + .LO(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_9589_i_3410) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_9590_i.INIT = 16'hECA0; + LUT4_L com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_9590_i ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_hi[0]), + .I1(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_hi[1]), + .I2(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_6_), + .I3(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_78_), + .LO(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_9590_i_3411) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_9591_i.INIT = 16'hECA0; + LUT4_L com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_9591_i ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_hi[0]), + .I1(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_hi[1]), + .I2(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_5_), + .I3(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_77_), + .LO(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_9591_i_3412) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_9592_i.INIT = 16'hECA0; + LUT4_L com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_9592_i ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_hi[0]), + .I1(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_hi[1]), + .I2(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_4_), + .I3(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_76_), + .LO(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_9592_i_3413) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_9593_i.INIT = 16'hECA0; + LUT4_L com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_9593_i ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_hi[0]), + .I1(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_hi[1]), + .I2(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_3_), + .I3(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_75_), + .LO(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_9593_i_3414) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_9594_i.INIT = 16'hECA0; + LUT4_L com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_9594_i ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_hi[0]), + .I1(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_hi[1]), + .I2(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_2_), + .I3(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_74_), + .LO(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_9594_i_3415) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_9595_i.INIT = 16'hECA0; + LUT4_L com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_9595_i ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_hi[0]), + .I1(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_hi[1]), + .I2(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_1_), + .I3(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_73_), + .LO(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_9595_i_3416) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_9596_i.INIT = 16'hECA0; + LUT4_L com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_9596_i ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_hi[0]), + .I1(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_hi[1]), + .I2(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_0_), + .I3(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_72_), + .LO(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_9596_i_3417) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_hi_eq_1_m_i.INIT = 8'hFD; + LUT3_L com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_hi_eq_1_m_i ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_hi[0]), + .I1(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_hi[1]), + .I2(com_tlm_u_tlm_rx_vc0_fifo_select_oq2bq_3117), + .LO(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_hi_eq_1_m_i_3345) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_d_o_d_m_67_.INIT = 16'hA888; + LUT4_L com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_d_o_d_m_67_ ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_d_o_0_sqmuxa_3353), + .I1(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_un613_d_o_d[0]), + .I2(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_hi[1]), + .I3(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_139_), + .LO(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_d_o_d_m_67__3346) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_d_o_d_m_65_.INIT = 16'hA888; + LUT4_L com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_d_o_d_m_65_ ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_d_o_0_sqmuxa_3353), + .I1(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_un597_d_o_d[0]), + .I2(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_hi[1]), + .I3(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_137_), + .LO(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_d_o_d_m_65__3347) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_d_o_d_m_64_.INIT = 16'hA888; + LUT4_L com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_d_o_d_m_64_ ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_d_o_0_sqmuxa_3353), + .I1(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_un589_d_o_d[0]), + .I2(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_hi[1]), + .I3(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_136_), + .LO(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_d_o_d_m_64__3348) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_hi_62_0_1_.INIT = 4'h8; + LUT2_L com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_hi_62_0_1_ ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_hi[0]), + .I1(com_tlm_u_tlm_rx_vc0_fifo_select_oq2bq_3117), + .LO(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_hi_62[1]) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_hi_62_0_0_0_.INIT = 8'h1C; + LUT3_L com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_hi_62_0_0_0_ ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_hi[0]), + .I1(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_hi[1]), + .I2(com_tlm_u_tlm_rx_vc0_fifo_select_oq2bq_3117), + .LO(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_hi_62[0]) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_un1_raddr_lo_1_axb_3.INIT = 8'hC6; + LUT3_L com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_un1_raddr_lo_1_axb_3 ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_d_o_0_sqmuxa_3353), + .I1(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[3]), + .I2(com_tlm_u_tlm_rx_vc0_fifo_select_oq2bq_3117), + .LO(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_un1_raddr_lo_1_axb_3_3349) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_un1_raddr_lo_1_axb_2.INIT = 8'hC6; + LUT3_L com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_un1_raddr_lo_1_axb_2 ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_d_o_0_sqmuxa_3353), + .I1(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[2]), + .I2(com_tlm_u_tlm_rx_vc0_fifo_select_oq2bq_3117), + .LO(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_un1_raddr_lo_1_axb_2_3350) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_un1_raddr_lo_1_axb_1.INIT = 8'hC6; + LUT3_L com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_un1_raddr_lo_1_axb_1 ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_d_o_0_sqmuxa_3353), + .I1(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[1]), + .I2(com_tlm_u_tlm_rx_vc0_fifo_select_oq2bq_3117), + .LO(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_un1_raddr_lo_1_axb_1_3351) + ); + FDS com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1_0_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_un1_raddr_lo_1_axb_0_3352), + .Q(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[0]), + .S(plm_link_up_i) + ); + FDS com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1_1_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_un1_raddr_lo_1_s_1_5), + .Q(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[1]), + .S(plm_link_up_i) + ); + FDS com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1_2_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_un1_raddr_lo_1_s_2_5), + .Q(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[2]), + .S(plm_link_up_i) + ); + FDS com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1_3_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_un1_raddr_lo_1_s_3_5), + .Q(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[3]), + .S(plm_link_up_i) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_d_o_0_sqmuxa.INIT = 8'hA2; + LUT3 com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_d_o_0_sqmuxa ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_nxt_vld_bqr), + .I1(com_tlm_u_tlm_rx_vc0_fifo_data_vld_bqr), + .I2(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_N_14337), + .O(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_d_o_0_sqmuxa_3353) + ); + FDE com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_data_bits_d_o_63_ ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_9597_i_3418), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_9533_i_3354), + .Q(com_tlm_u_tlm_rx_vc0_fifo_data_bqr_63_) + ); + FDE com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_data_bits_d_o_62_ ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_9597_i_3418), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_9534_i_3355), + .Q(com_tlm_u_tlm_rx_vc0_fifo_data_bqr_62_) + ); + FDE com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_data_bits_d_o_61_ ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_9597_i_3418), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_9535_i_3356), + .Q(com_tlm_u_tlm_rx_vc0_fifo_data_bqr_61_) + ); + FDE com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_data_bits_d_o_60_ ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_9597_i_3418), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_9536_i_3357), + .Q(com_tlm_u_tlm_rx_vc0_fifo_data_bqr_60_) + ); + FDE com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_data_bits_d_o_59_ ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_9597_i_3418), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_9537_i_3358), + .Q(com_tlm_u_tlm_rx_vc0_fifo_data_bqr_59_) + ); + FDE com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_data_bits_d_o_58_ ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_9597_i_3418), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_9538_i_3359), + .Q(com_tlm_u_tlm_rx_vc0_fifo_data_bqr_58_) + ); + FDE com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_data_bits_d_o_57_ ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_9597_i_3418), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_9539_i_3360), + .Q(com_tlm_u_tlm_rx_vc0_fifo_data_bqr_57_) + ); + FDE com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_data_bits_d_o_56_ ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_9597_i_3418), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_9540_i_3361), + .Q(com_tlm_u_tlm_rx_vc0_fifo_data_bqr_56_) + ); + FDE com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_data_bits_d_o_55_ ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_9597_i_3418), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_9541_i_3362), + .Q(com_tlm_u_tlm_rx_vc0_fifo_data_bqr_55_) + ); + FDE com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_data_bits_d_o_54_ ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_9597_i_3418), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_9542_i_3363), + .Q(com_tlm_u_tlm_rx_vc0_fifo_data_bqr_54_) + ); + FDE com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_data_bits_d_o_53_ ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_9597_i_3418), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_9543_i_3364), + .Q(com_tlm_u_tlm_rx_vc0_fifo_data_bqr_53_) + ); + FDE com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_data_bits_d_o_52_ ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_9597_i_3418), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_9544_i_3365), + .Q(com_tlm_u_tlm_rx_vc0_fifo_data_bqr_52_) + ); + FDE com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_data_bits_d_o_51_ ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_9597_i_3418), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_9545_i_3366), + .Q(com_tlm_u_tlm_rx_vc0_fifo_data_bqr_51_) + ); + FDE com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_data_bits_d_o_50_ ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_9597_i_3418), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_9546_i_3367), + .Q(com_tlm_u_tlm_rx_vc0_fifo_data_bqr_50_) + ); + FDE com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_data_bits_d_o_49_ ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_9597_i_3418), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_9547_i_3368), + .Q(com_tlm_u_tlm_rx_vc0_fifo_data_bqr_49_) + ); + FDE com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_data_bits_d_o_48_ ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_9597_i_3418), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_9548_i_3369), + .Q(com_tlm_u_tlm_rx_vc0_fifo_data_bqr_48_) + ); + FDE com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_data_bits_d_o_47_ ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_9597_i_3418), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_9549_i_3370), + .Q(com_tlm_u_tlm_rx_vc0_fifo_data_bqr_47_) + ); + FDE com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_data_bits_d_o_46_ ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_9597_i_3418), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_9550_i_3371), + .Q(com_tlm_u_tlm_rx_vc0_fifo_data_bqr_46_) + ); + FDE com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_data_bits_d_o_45_ ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_9597_i_3418), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_9551_i_3372), + .Q(com_tlm_u_tlm_rx_vc0_fifo_data_bqr_45_) + ); + FDE com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_data_bits_d_o_44_ ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_9597_i_3418), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_9552_i_3373), + .Q(com_tlm_u_tlm_rx_vc0_fifo_data_bqr_44_) + ); + FDE com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_data_bits_d_o_43_ ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_9597_i_3418), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_9553_i_3374), + .Q(com_tlm_u_tlm_rx_vc0_fifo_data_bqr_43_) + ); + FDE com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_data_bits_d_o_42_ ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_9597_i_3418), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_9554_i_3375), + .Q(com_tlm_u_tlm_rx_vc0_fifo_data_bqr_42_) + ); + FDE com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_data_bits_d_o_41_ ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_9597_i_3418), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_9555_i_3376), + .Q(com_tlm_u_tlm_rx_vc0_fifo_data_bqr_41_) + ); + FDE com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_data_bits_d_o_40_ ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_9597_i_3418), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_9556_i_3377), + .Q(com_tlm_u_tlm_rx_vc0_fifo_data_bqr_40_) + ); + FDE com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_data_bits_d_o_39_ ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_9597_i_3418), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_9557_i_3378), + .Q(com_tlm_u_tlm_rx_vc0_fifo_data_bqr_39_) + ); + FDE com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_data_bits_d_o_38_ ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_9597_i_3418), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_9558_i_3379), + .Q(com_tlm_u_tlm_rx_vc0_fifo_data_bqr_38_) + ); + FDE com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_data_bits_d_o_37_ ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_9597_i_3418), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_9559_i_3380), + .Q(com_tlm_u_tlm_rx_vc0_fifo_data_bqr_37_) + ); + FDE com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_data_bits_d_o_36_ ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_9597_i_3418), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_9560_i_3381), + .Q(com_tlm_u_tlm_rx_vc0_fifo_data_bqr_36_) + ); + FDE com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_data_bits_d_o_35_ ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_9597_i_3418), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_9561_i_3382), + .Q(com_tlm_u_tlm_rx_vc0_fifo_data_bqr_35_) + ); + FDE com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_data_bits_d_o_34_ ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_9597_i_3418), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_9562_i_3383), + .Q(com_tlm_u_tlm_rx_vc0_fifo_data_bqr_34_) + ); + FDE com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_data_bits_d_o_33_ ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_9597_i_3418), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_9563_i_3384), + .Q(com_tlm_u_tlm_rx_vc0_fifo_data_bqr_33_) + ); + FDE com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_data_bits_d_o_32_ ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_9597_i_3418), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_9564_i_3385), + .Q(com_tlm_u_tlm_rx_vc0_fifo_data_bqr_32_) + ); + FDE com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_data_bits_d_o_31_ ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_9597_i_3418), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_9565_i_3386), + .Q(com_tlm_u_tlm_rx_vc0_fifo_data_bqr_31_) + ); + FDE com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_data_bits_d_o_30_ ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_9597_i_3418), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_9566_i_3387), + .Q(com_tlm_u_tlm_rx_vc0_fifo_data_bqr_30_) + ); + FDE com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_data_bits_d_o_29_ ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_9597_i_3418), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_9567_i_3388), + .Q(com_tlm_u_tlm_rx_vc0_fifo_data_bqr_29_) + ); + FDE com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_data_bits_d_o_28_ ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_9597_i_3418), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_9568_i_3389), + .Q(com_tlm_u_tlm_rx_vc0_fifo_data_bqr_28_) + ); + FDE com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_data_bits_d_o_27_ ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_9597_i_3418), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_9569_i_3390), + .Q(com_tlm_u_tlm_rx_vc0_fifo_data_bqr_27_) + ); + FDE com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_data_bits_d_o_26_ ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_9597_i_3418), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_9570_i_3391), + .Q(com_tlm_u_tlm_rx_vc0_fifo_data_bqr_26_) + ); + FDE com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_data_bits_d_o_25_ ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_9597_i_3418), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_9571_i_3392), + .Q(com_tlm_u_tlm_rx_vc0_fifo_data_bqr_25_) + ); + FDE com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_data_bits_d_o_24_ ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_9597_i_3418), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_9572_i_3393), + .Q(com_tlm_u_tlm_rx_vc0_fifo_data_bqr_24_) + ); + FDE com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_data_bits_d_o_23_ ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_9597_i_3418), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_9573_i_3394), + .Q(com_tlm_u_tlm_rx_vc0_fifo_data_bqr_23_) + ); + FDE com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_data_bits_d_o_22_ ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_9597_i_3418), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_9574_i_3395), + .Q(com_tlm_u_tlm_rx_vc0_fifo_data_bqr_22_) + ); + FDE com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_data_bits_d_o_21_ ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_9597_i_3418), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_9575_i_3396), + .Q(com_tlm_u_tlm_rx_vc0_fifo_data_bqr_21_) + ); + FDE com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_data_bits_d_o_20_ ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_9597_i_3418), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_9576_i_3397), + .Q(com_tlm_u_tlm_rx_vc0_fifo_data_bqr_20_) + ); + FDE com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_data_bits_d_o_19_ ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_9597_i_3418), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_9577_i_3398), + .Q(com_tlm_u_tlm_rx_vc0_fifo_data_bqr_19_) + ); + FDE com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_data_bits_d_o_18_ ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_9597_i_3418), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_9578_i_3399), + .Q(com_tlm_u_tlm_rx_vc0_fifo_data_bqr_18_) + ); + FDE com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_data_bits_d_o_17_ ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_9597_i_3418), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_9579_i_3400), + .Q(com_tlm_u_tlm_rx_vc0_fifo_data_bqr_17_) + ); + FDE com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_data_bits_d_o_16_ ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_9597_i_3418), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_9580_i_3401), + .Q(com_tlm_u_tlm_rx_vc0_fifo_data_bqr_16_) + ); + FDE com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_data_bits_d_o_15_ ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_9597_i_3418), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_9581_i_3402), + .Q(com_tlm_u_tlm_rx_vc0_fifo_data_bqr_15_) + ); + FDE com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_data_bits_d_o_14_ ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_9597_i_3418), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_9582_i_3403), + .Q(com_tlm_u_tlm_rx_vc0_fifo_data_bqr_14_) + ); + FDE com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_data_bits_d_o_13_ ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_9597_i_3418), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_9583_i_3404), + .Q(com_tlm_u_tlm_rx_vc0_fifo_data_bqr_13_) + ); + FDE com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_data_bits_d_o_12_ ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_9597_i_3418), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_9584_i_3405), + .Q(com_tlm_u_tlm_rx_vc0_fifo_data_bqr_12_) + ); + FDE com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_data_bits_d_o_11_ ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_9597_i_3418), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_9585_i_3406), + .Q(com_tlm_u_tlm_rx_vc0_fifo_data_bqr_11_) + ); + FDE com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_data_bits_d_o_10_ ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_9597_i_3418), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_9586_i_3407), + .Q(com_tlm_u_tlm_rx_vc0_fifo_data_bqr_10_) + ); + FDE com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_data_bits_d_o_9_ ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_9597_i_3418), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_9587_i_3408), + .Q(com_tlm_u_tlm_rx_vc0_fifo_data_bqr_9_) + ); + FDE com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_data_bits_d_o_8_ ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_9597_i_3418), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_9588_i_3409), + .Q(com_tlm_u_tlm_rx_vc0_fifo_data_bqr_8_) + ); + FDE com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_data_bits_d_o_7_ ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_9597_i_3418), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_9589_i_3410), + .Q(com_tlm_u_tlm_rx_vc0_fifo_data_bqr_7_) + ); + FDE com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_data_bits_d_o_6_ ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_9597_i_3418), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_9590_i_3411), + .Q(com_tlm_u_tlm_rx_vc0_fifo_data_bqr_6_) + ); + FDE com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_data_bits_d_o_5_ ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_9597_i_3418), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_9591_i_3412), + .Q(com_tlm_u_tlm_rx_vc0_fifo_data_bqr_5_) + ); + FDE com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_data_bits_d_o_4_ ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_9597_i_3418), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_9592_i_3413), + .Q(com_tlm_u_tlm_rx_vc0_fifo_data_bqr_4_) + ); + FDE com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_data_bits_d_o_3_ ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_9597_i_3418), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_9593_i_3414), + .Q(com_tlm_u_tlm_rx_vc0_fifo_data_bqr_3_) + ); + FDE com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_data_bits_d_o_2_ ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_9597_i_3418), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_9594_i_3415), + .Q(com_tlm_u_tlm_rx_vc0_fifo_data_bqr_2_) + ); + FDE com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_data_bits_d_o_1_ ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_9597_i_3418), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_9595_i_3416), + .Q(com_tlm_u_tlm_rx_vc0_fifo_data_bqr_1_) + ); + FDE com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_data_bits_d_o_0_ ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_9597_i_3418), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_9596_i_3417), + .Q(com_tlm_u_tlm_rx_vc0_fifo_data_bqr_0_) + ); + INV com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_9597_i ( + .I(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_srl_ren_0), + .O(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_9597_i_3418) + ); + GND com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_queue_aux_queue_GND ( + .G(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_queue_aux_queue_GND_3419) + ); + SRLC16E com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_queue_aux_queue_srlrow_0__srlcol_0__srlinst ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_wen_aux_bq_3116), + .D(com_tlm_u_tlm_rx_vc0_fifo_aux_oqr[0]), + .Q(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_queue_aux_queue_shift_tap[0]), + .CLK(NlwRenamedSig_OI_trn_clk), + .Q15(NLW_com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_queue_aux_queue_srlrow_0__srlcol_0__srlinst_Q15_UNCONNECTED), + .A0(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_queue_aux_queue_raddr_lo[0]), + .A1(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_queue_aux_queue_raddr_lo[1]), + .A2(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_queue_aux_queue_raddr_lo[2]), + .A3(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_queue_aux_queue_raddr_lo[3]) + ); + SRLC16E com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_queue_aux_queue_srlrow_0__srlcol_3__srlinst ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_wen_aux_bq_3116), + .D(com_tlm_u_tlm_rx_vc0_fifo_aux_oqr[3]), + .Q(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_queue_aux_queue_shift_tap[3]), + .CLK(NlwRenamedSig_OI_trn_clk), + .Q15(NLW_com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_queue_aux_queue_srlrow_0__srlcol_3__srlinst_Q15_UNCONNECTED), + .A0(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_queue_aux_queue_raddr_lo[0]), + .A1(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_queue_aux_queue_raddr_lo[1]), + .A2(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_queue_aux_queue_raddr_lo[2]), + .A3(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_queue_aux_queue_raddr_lo[3]) + ); + SRLC16E com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_queue_aux_queue_srlrow_0__srlcol_2__srlinst ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_wen_aux_bq_3116), + .D(com_tlm_u_tlm_rx_vc0_fifo_aux_oqr[2]), + .Q(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_queue_aux_queue_shift_tap[2]), + .CLK(NlwRenamedSig_OI_trn_clk), + .Q15(NLW_com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_queue_aux_queue_srlrow_0__srlcol_2__srlinst_Q15_UNCONNECTED), + .A0(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_queue_aux_queue_raddr_lo[0]), + .A1(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_queue_aux_queue_raddr_lo[1]), + .A2(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_queue_aux_queue_raddr_lo[2]), + .A3(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_queue_aux_queue_raddr_lo[3]) + ); + SRLC16E com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_queue_aux_queue_srlrow_0__srlcol_1__srlinst ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_wen_aux_bq_3116), + .D(com_tlm_u_tlm_rx_vc0_fifo_aux_oqr[1]), + .Q(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_queue_aux_queue_shift_tap[1]), + .CLK(NlwRenamedSig_OI_trn_clk), + .Q15(NLW_com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_queue_aux_queue_srlrow_0__srlcol_1__srlinst_Q15_UNCONNECTED), + .A0(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_queue_aux_queue_raddr_lo[0]), + .A1(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_queue_aux_queue_raddr_lo[1]), + .A2(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_queue_aux_queue_raddr_lo[2]), + .A3(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_queue_aux_queue_raddr_lo[3]) + ); + SRLC16E com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_queue_aux_queue_srlrow_0__srlcol_4__srlinst ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_wen_aux_bq_3116), + .D(com_tlm_u_tlm_rx_vc0_fifo_aux_oqr[4]), + .Q(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_queue_aux_queue_shift_tap[4]), + .CLK(NlwRenamedSig_OI_trn_clk), + .Q15(NLW_com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_queue_aux_queue_srlrow_0__srlcol_4__srlinst_Q15_UNCONNECTED), + .A0(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_queue_aux_queue_raddr_lo[0]), + .A1(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_queue_aux_queue_raddr_lo[1]), + .A2(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_queue_aux_queue_raddr_lo[2]), + .A3(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_queue_aux_queue_raddr_lo[3]) + ); + SRLC16E com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_queue_aux_queue_srlrow_0__srlcol_7__srlinst ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_wen_aux_bq_3116), + .D(com_tlm_u_tlm_rx_vc0_fifo_cfg_oqr), + .Q(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_queue_aux_queue_shift_tap[7]), + .CLK(NlwRenamedSig_OI_trn_clk), + .Q15(NLW_com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_queue_aux_queue_srlrow_0__srlcol_7__srlinst_Q15_UNCONNECTED), + .A0(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_queue_aux_queue_raddr_lo[0]), + .A1(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_queue_aux_queue_raddr_lo[1]), + .A2(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_queue_aux_queue_raddr_lo[2]), + .A3(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_queue_aux_queue_raddr_lo[3]) + ); + SRLC16E com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_queue_aux_queue_srlrow_0__srlcol_6__srlinst ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_wen_aux_bq_3116), + .D(com_tlm_u_tlm_rx_vc0_fifo_aux_oqr[6]), + .Q(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_queue_aux_queue_shift_tap[6]), + .CLK(NlwRenamedSig_OI_trn_clk), + .Q15(NLW_com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_queue_aux_queue_srlrow_0__srlcol_6__srlinst_Q15_UNCONNECTED), + .A0(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_queue_aux_queue_raddr_lo[0]), + .A1(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_queue_aux_queue_raddr_lo[1]), + .A2(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_queue_aux_queue_raddr_lo[2]), + .A3(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_queue_aux_queue_raddr_lo[3]) + ); + SRLC16E com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_queue_aux_queue_srlrow_0__srlcol_5__srlinst ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_wen_aux_bq_3116), + .D(com_tlm_u_tlm_rx_vc0_fifo_aux_oqr[5]), + .Q(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_queue_aux_queue_shift_tap[5]), + .CLK(NlwRenamedSig_OI_trn_clk), + .Q15(NLW_com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_queue_aux_queue_srlrow_0__srlcol_5__srlinst_Q15_UNCONNECTED), + .A0(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_queue_aux_queue_raddr_lo[0]), + .A1(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_queue_aux_queue_raddr_lo[1]), + .A2(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_queue_aux_queue_raddr_lo[2]), + .A3(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_queue_aux_queue_raddr_lo[3]) + ); + FDS com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_queue_aux_queue_raddr_lo_0_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_queue_aux_queue_un1_raddr_lo_1_axb_0_3426), + .Q(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_queue_aux_queue_raddr_lo[0]), + .S(plm_link_up_i) + ); + FDS com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_queue_aux_queue_raddr_lo_1_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_queue_aux_queue_un1_raddr_lo_1_s_1_6), + .Q(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_queue_aux_queue_raddr_lo[1]), + .S(plm_link_up_i) + ); + FDS com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_queue_aux_queue_raddr_lo_2_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_queue_aux_queue_un1_raddr_lo_1_s_2_6), + .Q(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_queue_aux_queue_raddr_lo[2]), + .S(plm_link_up_i) + ); + FDS com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_queue_aux_queue_raddr_lo_3_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_queue_aux_queue_un1_raddr_lo_1_s_3_6), + .Q(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_queue_aux_queue_raddr_lo[3]), + .S(plm_link_up_i) + ); + FDRE com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_queue_aux_queue_d_o_0_ ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_queue_aux_queue_N_9529_i_3423), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_queue_aux_queue_shift_tap_m[0]), + .Q(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux[0]), + .R(plm_link_up_i) + ); + FDRE com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_queue_aux_queue_d_o_1_ ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_queue_aux_queue_N_9529_i_3423), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_queue_aux_queue_shift_tap_m[1]), + .Q(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux[1]), + .R(plm_link_up_i) + ); + FDRE com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_queue_aux_queue_d_o_2_ ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_queue_aux_queue_N_9529_i_3423), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_queue_aux_queue_shift_tap_m[2]), + .Q(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux[2]), + .R(plm_link_up_i) + ); + FDRE com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_queue_aux_queue_d_o_3_ ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_queue_aux_queue_N_9529_i_3423), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_queue_aux_queue_shift_tap_m[3]), + .Q(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux[3]), + .R(plm_link_up_i) + ); + FDRE com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_queue_aux_queue_d_o_4_ ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_queue_aux_queue_N_9529_i_3423), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_queue_aux_queue_shift_tap_m[4]), + .Q(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux[4]), + .R(plm_link_up_i) + ); + FDRE com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_queue_aux_queue_d_o_5_ ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_queue_aux_queue_N_9529_i_3423), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_queue_aux_queue_shift_tap_m[5]), + .Q(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux[5]), + .R(plm_link_up_i) + ); + FDRE com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_queue_aux_queue_d_o_6_ ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_queue_aux_queue_N_9529_i_3423), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_queue_aux_queue_shift_tap_m[6]), + .Q(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux[6]), + .R(plm_link_up_i) + ); + FDRE com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_queue_aux_queue_d_o_7_ ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_queue_aux_queue_N_9529_i_3423), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_queue_aux_queue_shift_tap_m[7]), + .Q(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux[7]), + .R(plm_link_up_i) + ); + FDRE com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_queue_aux_queue_nxt_vld_o ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_queue_aux_queue_un1_bkp_i_1_i_3424), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_wen_aux_bq_3116), + .Q(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_queue_aux_queue_un1_aux_queue), + .R(plm_link_up_i) + ); + FDRE com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_queue_aux_queue_vld_o ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_queue_aux_queue_N_9529_i_3423), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_queue_aux_queue_un1_aux_queue), + .Q(com_tlm_u_tlm_rx_vc0_fifo_aux_vld), + .R(plm_link_up_i) + ); + MUXCY_L com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_queue_aux_queue_un1_raddr_lo_1_cry_0 ( + .CI(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_queue_aux_queue_GND_3419), + .DI(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_queue_aux_queue_raddr_lo[0]), + .LO(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_queue_aux_queue_un1_raddr_lo_1_cry_0_3420), + .S(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_queue_aux_queue_un1_raddr_lo_1_axb_0_3426) + ); + MUXCY_L com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_queue_aux_queue_un1_raddr_lo_1_cry_1 ( + .CI(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_queue_aux_queue_un1_raddr_lo_1_cry_0_3420), + .DI(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_queue_aux_queue_raddr_lo[1]), + .LO(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_queue_aux_queue_un1_raddr_lo_1_cry_1_3421), + .S(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_queue_aux_queue_un1_raddr_lo_1_axb_1_3429) + ); + XORCY com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_queue_aux_queue_un1_raddr_lo_1_s_1 ( + .CI(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_queue_aux_queue_un1_raddr_lo_1_cry_0_3420), + .LI(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_queue_aux_queue_un1_raddr_lo_1_axb_1_3429), + .O(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_queue_aux_queue_un1_raddr_lo_1_s_1_6) + ); + MUXCY_L com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_queue_aux_queue_un1_raddr_lo_1_cry_2 ( + .CI(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_queue_aux_queue_un1_raddr_lo_1_cry_1_3421), + .DI(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_queue_aux_queue_raddr_lo[2]), + .LO(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_queue_aux_queue_un1_raddr_lo_1_cry_2_3422), + .S(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_queue_aux_queue_un1_raddr_lo_1_axb_2_3428) + ); + XORCY com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_queue_aux_queue_un1_raddr_lo_1_s_2 ( + .CI(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_queue_aux_queue_un1_raddr_lo_1_cry_1_3421), + .LI(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_queue_aux_queue_un1_raddr_lo_1_axb_2_3428), + .O(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_queue_aux_queue_un1_raddr_lo_1_s_2_6) + ); + XORCY com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_queue_aux_queue_un1_raddr_lo_1_s_3 ( + .CI(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_queue_aux_queue_un1_raddr_lo_1_cry_2_3422), + .LI(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_queue_aux_queue_un1_raddr_lo_1_axb_3_3427), + .O(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_queue_aux_queue_un1_raddr_lo_1_s_3_6) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_queue_aux_queue_un15_nxt_vld_o_en_2.INIT = 16'h0001; + LUT4 com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_queue_aux_queue_un15_nxt_vld_o_en_2 ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_queue_aux_queue_raddr_lo[0]), + .I1(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_queue_aux_queue_raddr_lo[1]), + .I2(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_queue_aux_queue_raddr_lo[2]), + .I3(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_queue_aux_queue_raddr_lo[3]), + .O(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_queue_aux_queue_un15_nxt_vld_o_en_2_3425) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_queue_aux_queue_d_o_0_sqmuxa.INIT = 8'h8A; + LUT3 com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_queue_aux_queue_d_o_0_sqmuxa ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_queue_aux_queue_un1_aux_queue), + .I1(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_ren), + .I2(com_tlm_u_tlm_rx_vc0_fifo_aux_vld), + .O(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_queue_aux_queue_d_o_0_sqmuxa_3430) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_queue_aux_queue_N_9529_i.INIT = 4'hB; + LUT2 com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_queue_aux_queue_N_9529_i ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_ren), + .I1(com_tlm_u_tlm_rx_vc0_fifo_aux_vld), + .O(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_queue_aux_queue_N_9529_i_3423) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_queue_aux_queue_un1_bkp_i_1_i.INIT = 16'hFF8A; + LUT4 com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_queue_aux_queue_un1_bkp_i_1_i ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_queue_aux_queue_un15_nxt_vld_o_en_2_3425), + .I1(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_ren), + .I2(com_tlm_u_tlm_rx_vc0_fifo_aux_vld), + .I3(com_tlm_u_tlm_rx_vc0_fifo_wen_aux_bq_3116), + .O(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_queue_aux_queue_un1_bkp_i_1_i_3424) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_queue_aux_queue_un1_raddr_lo_1_axb_0.INIT = 8'h96; + LUT3 com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_queue_aux_queue_un1_raddr_lo_1_axb_0 ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_queue_aux_queue_d_o_0_sqmuxa_3430), + .I1(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_queue_aux_queue_raddr_lo[0]), + .I2(com_tlm_u_tlm_rx_vc0_fifo_wen_aux_bq_3116), + .O(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_queue_aux_queue_un1_raddr_lo_1_axb_0_3426) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_queue_aux_queue_shift_tap_m_7_.INIT = 4'h8; + LUT2_L com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_queue_aux_queue_shift_tap_m_7_ ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_queue_aux_queue_d_o_0_sqmuxa_3430), + .I1(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_queue_aux_queue_shift_tap[7]), + .LO(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_queue_aux_queue_shift_tap_m[7]) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_queue_aux_queue_shift_tap_m_6_.INIT = 4'h8; + LUT2_L com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_queue_aux_queue_shift_tap_m_6_ ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_queue_aux_queue_d_o_0_sqmuxa_3430), + .I1(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_queue_aux_queue_shift_tap[6]), + .LO(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_queue_aux_queue_shift_tap_m[6]) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_queue_aux_queue_shift_tap_m_5_.INIT = 4'h8; + LUT2_L com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_queue_aux_queue_shift_tap_m_5_ ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_queue_aux_queue_d_o_0_sqmuxa_3430), + .I1(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_queue_aux_queue_shift_tap[5]), + .LO(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_queue_aux_queue_shift_tap_m[5]) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_queue_aux_queue_shift_tap_m_4_.INIT = 4'h8; + LUT2_L com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_queue_aux_queue_shift_tap_m_4_ ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_queue_aux_queue_d_o_0_sqmuxa_3430), + .I1(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_queue_aux_queue_shift_tap[4]), + .LO(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_queue_aux_queue_shift_tap_m[4]) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_queue_aux_queue_shift_tap_m_3_.INIT = 4'h8; + LUT2_L com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_queue_aux_queue_shift_tap_m_3_ ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_queue_aux_queue_d_o_0_sqmuxa_3430), + .I1(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_queue_aux_queue_shift_tap[3]), + .LO(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_queue_aux_queue_shift_tap_m[3]) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_queue_aux_queue_shift_tap_m_2_.INIT = 4'h8; + LUT2_L com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_queue_aux_queue_shift_tap_m_2_ ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_queue_aux_queue_d_o_0_sqmuxa_3430), + .I1(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_queue_aux_queue_shift_tap[2]), + .LO(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_queue_aux_queue_shift_tap_m[2]) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_queue_aux_queue_shift_tap_m_1_.INIT = 4'h8; + LUT2_L com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_queue_aux_queue_shift_tap_m_1_ ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_queue_aux_queue_d_o_0_sqmuxa_3430), + .I1(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_queue_aux_queue_shift_tap[1]), + .LO(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_queue_aux_queue_shift_tap_m[1]) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_queue_aux_queue_shift_tap_m_0_.INIT = 4'h8; + LUT2_L com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_queue_aux_queue_shift_tap_m_0_ ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_queue_aux_queue_d_o_0_sqmuxa_3430), + .I1(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_queue_aux_queue_shift_tap[0]), + .LO(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_queue_aux_queue_shift_tap_m[0]) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_queue_aux_queue_un1_raddr_lo_1_axb_3.INIT = 8'hC6; + LUT3_L com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_queue_aux_queue_un1_raddr_lo_1_axb_3 ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_queue_aux_queue_d_o_0_sqmuxa_3430), + .I1(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_queue_aux_queue_raddr_lo[3]), + .I2(com_tlm_u_tlm_rx_vc0_fifo_wen_aux_bq_3116), + .LO(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_queue_aux_queue_un1_raddr_lo_1_axb_3_3427) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_queue_aux_queue_un1_raddr_lo_1_axb_2.INIT = 8'hC6; + LUT3_L com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_queue_aux_queue_un1_raddr_lo_1_axb_2 ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_queue_aux_queue_d_o_0_sqmuxa_3430), + .I1(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_queue_aux_queue_raddr_lo[2]), + .I2(com_tlm_u_tlm_rx_vc0_fifo_wen_aux_bq_3116), + .LO(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_queue_aux_queue_un1_raddr_lo_1_axb_2_3428) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_queue_aux_queue_un1_raddr_lo_1_axb_1.INIT = 8'hC6; + LUT3_L com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_queue_aux_queue_un1_raddr_lo_1_axb_1 ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_queue_aux_queue_d_o_0_sqmuxa_3430), + .I1(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_queue_aux_queue_raddr_lo[1]), + .I2(com_tlm_u_tlm_rx_vc0_fifo_wen_aux_bq_3116), + .LO(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_queue_aux_queue_un1_raddr_lo_1_axb_1_3429) + ); + GND com_tlm_u_tlm_rx_vc0_flow_ctrl_GND ( + .G(com_tlm_u_tlm_rx_vc0_flow_ctrl_GND_3431) + ); + FDS com_tlm_u_tlm_rx_vc0_flow_ctrl_freeze_timer ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_aspm_ok_i), + .Q(com_tlm_u_tlm_rx_vc0_flow_ctrl_freeze_timer_3437), + .S(plm_link_up_i) + ); + FDR com_tlm_u_tlm_rx_vc0_flow_ctrl_err_overflow_o ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_flow_ctrl_N_16796_i_3432), + .Q(com_tlm_cmmt_err_rbuf_overflow), + .R(plm_link_up_i) + ); + MUXCY_L com_tlm_u_tlm_rx_vc0_flow_ctrl_lat_timer_cry_0_ ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_un1_lat_timer_i), + .DI(com_tlm_u_tlm_rx_vc0_flow_ctrl_GND_3431), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_lat_timer_cry[0]), + .S(com_tlm_u_tlm_rx_vc0_flow_ctrl_lat_timer_qxu[0]) + ); + XORCY com_tlm_u_tlm_rx_vc0_flow_ctrl_lat_timer_s_0_ ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_un1_lat_timer_i), + .LI(com_tlm_u_tlm_rx_vc0_flow_ctrl_lat_timer_qxu[0]), + .O(com_tlm_u_tlm_rx_vc0_flow_ctrl_lat_timer_s[0]) + ); + FDRE com_tlm_u_tlm_rx_vc0_flow_ctrl_lat_timer_0_ ( + .CE(com_tlm_u_tlm_rx_vc0_flow_ctrl_N_42529_i_3434), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_flow_ctrl_lat_timer_s[0]), + .Q(com_tlm_u_tlm_rx_vc0_flow_ctrl_lat_timer[0]), + .R(plm_link_up_i) + ); + MUXCY_L com_tlm_u_tlm_rx_vc0_flow_ctrl_lat_timer_cry_1_ ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_lat_timer_cry[0]), + .DI(com_tlm_u_tlm_rx_vc0_flow_ctrl_GND_3431), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_lat_timer_cry[1]), + .S(com_tlm_u_tlm_rx_vc0_flow_ctrl_lat_timer_qxu[1]) + ); + XORCY com_tlm_u_tlm_rx_vc0_flow_ctrl_lat_timer_s_1_ ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_lat_timer_cry[0]), + .LI(com_tlm_u_tlm_rx_vc0_flow_ctrl_lat_timer_qxu[1]), + .O(com_tlm_u_tlm_rx_vc0_flow_ctrl_lat_timer_s[1]) + ); + FDRE com_tlm_u_tlm_rx_vc0_flow_ctrl_lat_timer_1_ ( + .CE(com_tlm_u_tlm_rx_vc0_flow_ctrl_N_42529_i_3434), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_flow_ctrl_lat_timer_s[1]), + .Q(com_tlm_u_tlm_rx_vc0_flow_ctrl_lat_timer[1]), + .R(plm_link_up_i) + ); + MUXCY_L com_tlm_u_tlm_rx_vc0_flow_ctrl_lat_timer_cry_2_ ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_lat_timer_cry[1]), + .DI(com_tlm_u_tlm_rx_vc0_flow_ctrl_GND_3431), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_lat_timer_cry[2]), + .S(com_tlm_u_tlm_rx_vc0_flow_ctrl_lat_timer_qxu[2]) + ); + XORCY com_tlm_u_tlm_rx_vc0_flow_ctrl_lat_timer_s_2_ ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_lat_timer_cry[1]), + .LI(com_tlm_u_tlm_rx_vc0_flow_ctrl_lat_timer_qxu[2]), + .O(com_tlm_u_tlm_rx_vc0_flow_ctrl_lat_timer_s[2]) + ); + FDRE com_tlm_u_tlm_rx_vc0_flow_ctrl_lat_timer_2_ ( + .CE(com_tlm_u_tlm_rx_vc0_flow_ctrl_N_42529_i_3434), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_flow_ctrl_lat_timer_s[2]), + .Q(com_tlm_u_tlm_rx_vc0_flow_ctrl_lat_timer[2]), + .R(plm_link_up_i) + ); + MUXCY_L com_tlm_u_tlm_rx_vc0_flow_ctrl_lat_timer_cry_3_ ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_lat_timer_cry[2]), + .DI(com_tlm_u_tlm_rx_vc0_flow_ctrl_GND_3431), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_lat_timer_cry[3]), + .S(com_tlm_u_tlm_rx_vc0_flow_ctrl_lat_timer_qxu[3]) + ); + XORCY com_tlm_u_tlm_rx_vc0_flow_ctrl_lat_timer_s_3_ ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_lat_timer_cry[2]), + .LI(com_tlm_u_tlm_rx_vc0_flow_ctrl_lat_timer_qxu[3]), + .O(com_tlm_u_tlm_rx_vc0_flow_ctrl_lat_timer_s[3]) + ); + FDRE com_tlm_u_tlm_rx_vc0_flow_ctrl_lat_timer_3_ ( + .CE(com_tlm_u_tlm_rx_vc0_flow_ctrl_N_42529_i_3434), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_flow_ctrl_lat_timer_s[3]), + .Q(com_tlm_u_tlm_rx_vc0_flow_ctrl_lat_timer[3]), + .R(plm_link_up_i) + ); + MUXCY_L com_tlm_u_tlm_rx_vc0_flow_ctrl_lat_timer_cry_4_ ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_lat_timer_cry[3]), + .DI(com_tlm_u_tlm_rx_vc0_flow_ctrl_GND_3431), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_lat_timer_cry[4]), + .S(com_tlm_u_tlm_rx_vc0_flow_ctrl_lat_timer_qxu[4]) + ); + XORCY com_tlm_u_tlm_rx_vc0_flow_ctrl_lat_timer_s_4_ ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_lat_timer_cry[3]), + .LI(com_tlm_u_tlm_rx_vc0_flow_ctrl_lat_timer_qxu[4]), + .O(com_tlm_u_tlm_rx_vc0_flow_ctrl_lat_timer_s[4]) + ); + FDRE com_tlm_u_tlm_rx_vc0_flow_ctrl_lat_timer_4_ ( + .CE(com_tlm_u_tlm_rx_vc0_flow_ctrl_N_42529_i_3434), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_flow_ctrl_lat_timer_s[4]), + .Q(com_tlm_u_tlm_rx_vc0_flow_ctrl_lat_timer[4]), + .R(plm_link_up_i) + ); + MUXCY_L com_tlm_u_tlm_rx_vc0_flow_ctrl_lat_timer_cry_5_ ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_lat_timer_cry[4]), + .DI(com_tlm_u_tlm_rx_vc0_flow_ctrl_GND_3431), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_lat_timer_cry[5]), + .S(com_tlm_u_tlm_rx_vc0_flow_ctrl_lat_timer_qxu[5]) + ); + XORCY com_tlm_u_tlm_rx_vc0_flow_ctrl_lat_timer_s_5_ ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_lat_timer_cry[4]), + .LI(com_tlm_u_tlm_rx_vc0_flow_ctrl_lat_timer_qxu[5]), + .O(com_tlm_u_tlm_rx_vc0_flow_ctrl_lat_timer_s[5]) + ); + FDSE com_tlm_u_tlm_rx_vc0_flow_ctrl_lat_timer_5_ ( + .CE(com_tlm_u_tlm_rx_vc0_flow_ctrl_N_42529_i_3434), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_flow_ctrl_lat_timer_s[5]), + .Q(com_tlm_u_tlm_rx_vc0_flow_ctrl_lat_timer[5]), + .S(plm_link_up_i) + ); + MUXCY_L com_tlm_u_tlm_rx_vc0_flow_ctrl_lat_timer_cry_6_ ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_lat_timer_cry[5]), + .DI(com_tlm_u_tlm_rx_vc0_flow_ctrl_GND_3431), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_lat_timer_cry[6]), + .S(com_tlm_u_tlm_rx_vc0_flow_ctrl_lat_timer_qxu[6]) + ); + XORCY com_tlm_u_tlm_rx_vc0_flow_ctrl_lat_timer_s_6_ ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_lat_timer_cry[5]), + .LI(com_tlm_u_tlm_rx_vc0_flow_ctrl_lat_timer_qxu[6]), + .O(com_tlm_u_tlm_rx_vc0_flow_ctrl_lat_timer_s[6]) + ); + FDSE com_tlm_u_tlm_rx_vc0_flow_ctrl_lat_timer_6_ ( + .CE(com_tlm_u_tlm_rx_vc0_flow_ctrl_N_42529_i_3434), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_flow_ctrl_lat_timer_s[6]), + .Q(com_tlm_u_tlm_rx_vc0_flow_ctrl_lat_timer[6]), + .S(plm_link_up_i) + ); + MUXCY_L com_tlm_u_tlm_rx_vc0_flow_ctrl_lat_timer_cry_7_ ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_lat_timer_cry[6]), + .DI(com_tlm_u_tlm_rx_vc0_flow_ctrl_GND_3431), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_lat_timer_cry[7]), + .S(com_tlm_u_tlm_rx_vc0_flow_ctrl_lat_timer_qxu[7]) + ); + XORCY com_tlm_u_tlm_rx_vc0_flow_ctrl_lat_timer_s_7_ ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_lat_timer_cry[6]), + .LI(com_tlm_u_tlm_rx_vc0_flow_ctrl_lat_timer_qxu[7]), + .O(com_tlm_u_tlm_rx_vc0_flow_ctrl_lat_timer_s[7]) + ); + FDSE com_tlm_u_tlm_rx_vc0_flow_ctrl_lat_timer_7_ ( + .CE(com_tlm_u_tlm_rx_vc0_flow_ctrl_N_42529_i_3434), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_flow_ctrl_lat_timer_s[7]), + .Q(com_tlm_u_tlm_rx_vc0_flow_ctrl_lat_timer[7]), + .S(plm_link_up_i) + ); + MUXCY_L com_tlm_u_tlm_rx_vc0_flow_ctrl_lat_timer_cry_8_ ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_lat_timer_cry[7]), + .DI(com_tlm_u_tlm_rx_vc0_flow_ctrl_GND_3431), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_lat_timer_cry[8]), + .S(com_tlm_u_tlm_rx_vc0_flow_ctrl_lat_timer_qxu[8]) + ); + XORCY com_tlm_u_tlm_rx_vc0_flow_ctrl_lat_timer_s_8_ ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_lat_timer_cry[7]), + .LI(com_tlm_u_tlm_rx_vc0_flow_ctrl_lat_timer_qxu[8]), + .O(com_tlm_u_tlm_rx_vc0_flow_ctrl_lat_timer_s[8]) + ); + FDSE com_tlm_u_tlm_rx_vc0_flow_ctrl_lat_timer_8_ ( + .CE(com_tlm_u_tlm_rx_vc0_flow_ctrl_N_42529_i_3434), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_flow_ctrl_lat_timer_s[8]), + .Q(com_tlm_u_tlm_rx_vc0_flow_ctrl_lat_timer[8]), + .S(plm_link_up_i) + ); + XORCY com_tlm_u_tlm_rx_vc0_flow_ctrl_lat_timer_s_9_ ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_lat_timer_cry[8]), + .LI(com_tlm_u_tlm_rx_vc0_flow_ctrl_lat_timer_qxu[9]), + .O(com_tlm_u_tlm_rx_vc0_flow_ctrl_lat_timer_s[9]) + ); + FDRE com_tlm_u_tlm_rx_vc0_flow_ctrl_lat_timer_9_ ( + .CE(com_tlm_u_tlm_rx_vc0_flow_ctrl_N_42529_i_3434), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_flow_ctrl_lat_timer_s[9]), + .Q(com_tlm_u_tlm_rx_vc0_flow_ctrl_lat_timer[9]), + .R(plm_link_up_i) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_un1_lat_timer_1_a2_0_a2.INIT = 4'h1; + LUT2 com_tlm_u_tlm_rx_vc0_flow_ctrl_un1_lat_timer_1_a2_0_a2 ( + .I0(com_tlm_u_tlm_rx_vc0_flow_ctrl_freeze_timer_3437), + .I1(com_tlm_u_tlm_rx_vc0_flow_ctrl_lat_timer[9]), + .O(com_tlm_u_tlm_rx_vc0_flow_ctrl_un1_lat_timer_i) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_err_overflow_o_3_0_a2_3.INIT = 16'h0001; + LUT4_L com_tlm_u_tlm_rx_vc0_flow_ctrl_err_overflow_o_3_0_a2_3 ( + .I0(com_tlm_u_tlm_rx_vc0_flow_ctrl_fc_d_advert[11]), + .I1(com_tlm_u_tlm_rx_vc0_flow_ctrl_fc_h_advert[7]), + .I2(com_tlm_u_tlm_rx_vc0_flow_ctrl_fc_d_advert_0[11]), + .I3(com_tlm_u_tlm_rx_vc0_flow_ctrl_fc_h_advert_0[7]), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_err_overflow_o_3_0_a2_3_3433) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_lat_timer_qxu_8_.INIT = 8'hCA; + LUT3_L com_tlm_u_tlm_rx_vc0_flow_ctrl_lat_timer_qxu_8_ ( + .I0(com_tlm_u_tlm_rx_vc0_flow_ctrl_freeze_timer_3437), + .I1(com_tlm_u_tlm_rx_vc0_flow_ctrl_lat_timer[8]), + .I2(com_tlm_u_tlm_rx_vc0_flow_ctrl_un1_lat_timer_i), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_lat_timer_qxu[8]) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_lat_timer_qxu_7_.INIT = 8'hCA; + LUT3_L com_tlm_u_tlm_rx_vc0_flow_ctrl_lat_timer_qxu_7_ ( + .I0(com_tlm_u_tlm_rx_vc0_flow_ctrl_freeze_timer_3437), + .I1(com_tlm_u_tlm_rx_vc0_flow_ctrl_lat_timer[7]), + .I2(com_tlm_u_tlm_rx_vc0_flow_ctrl_un1_lat_timer_i), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_lat_timer_qxu[7]) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_lat_timer_qxu_6_.INIT = 8'hCA; + LUT3_L com_tlm_u_tlm_rx_vc0_flow_ctrl_lat_timer_qxu_6_ ( + .I0(com_tlm_u_tlm_rx_vc0_flow_ctrl_freeze_timer_3437), + .I1(com_tlm_u_tlm_rx_vc0_flow_ctrl_lat_timer[6]), + .I2(com_tlm_u_tlm_rx_vc0_flow_ctrl_un1_lat_timer_i), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_lat_timer_qxu[6]) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_lat_timer_qxu_5_.INIT = 8'hCA; + LUT3_L com_tlm_u_tlm_rx_vc0_flow_ctrl_lat_timer_qxu_5_ ( + .I0(com_tlm_u_tlm_rx_vc0_flow_ctrl_freeze_timer_3437), + .I1(com_tlm_u_tlm_rx_vc0_flow_ctrl_lat_timer[5]), + .I2(com_tlm_u_tlm_rx_vc0_flow_ctrl_un1_lat_timer_i), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_lat_timer_qxu[5]) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_lat_prescale_term10_0_a3.INIT = 4'h2; + LUT2_L com_tlm_u_tlm_rx_vc0_flow_ctrl_lat_prescale_term10_0_a3 ( + .I0(com_tlm_u_tlm_rx_vc0_flow_ctrl_lat_prescale[0]), + .I1(com_tlm_u_tlm_rx_vc0_flow_ctrl_lat_prescale[1]), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_lat_prescale_term10) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_N_69387_i.INIT = 4'hB; + LUT2_L com_tlm_u_tlm_rx_vc0_flow_ctrl_N_69387_i ( + .I0(com_tlm_u_tlm_rx_vc0_flow_ctrl_lat_prescale[0]), + .I1(com_tlm_u_tlm_rx_vc0_flow_ctrl_lat_prescale[1]), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_N_69387_i_3436) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_lat_prescale_i_0_.INIT = 4'h1; + LUT1_L com_tlm_u_tlm_rx_vc0_flow_ctrl_lat_prescale_i_0_ ( + .I0(com_tlm_u_tlm_rx_vc0_flow_ctrl_lat_prescale[0]), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_lat_prescale_i[0]) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_N_16796_i.INIT = 8'hFD; + LUT3_L com_tlm_u_tlm_rx_vc0_flow_ctrl_N_16796_i ( + .I0(com_tlm_u_tlm_rx_vc0_flow_ctrl_err_overflow_o_3_0_a2_3_3433), + .I1(NlwRenamedSig_OI_trn_rfc_cpld_av[11]), + .I2(NlwRenamedSig_OI_trn_rfc_cplh_av[7]), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_N_16796_i_3432) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_N_42529_i.INIT = 8'hFE; + LUT3 com_tlm_u_tlm_rx_vc0_flow_ctrl_N_42529_i ( + .I0(com_tlm_u_tlm_rx_vc0_flow_ctrl_lat_prescale_term_3435), + .I1(com_tlm_u_tlm_rx_vc0_flow_ctrl_lat_timer[9]), + .I2(com_tlm_u_tlm_rx_vc0_flow_ctrl_freeze_timer_3437), + .O(com_tlm_u_tlm_rx_vc0_flow_ctrl_N_42529_i_3434) + ); + FD com_tlm_u_tlm_rx_vc0_flow_ctrl_lat_prescale_term ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_flow_ctrl_lat_prescale_term10), + .Q(com_tlm_u_tlm_rx_vc0_flow_ctrl_lat_prescale_term_3435) + ); + FD com_tlm_u_tlm_rx_vc0_flow_ctrl_lat_prescale_1_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_flow_ctrl_N_69387_i_3436), + .Q(com_tlm_u_tlm_rx_vc0_flow_ctrl_lat_prescale[1]) + ); + FD com_tlm_u_tlm_rx_vc0_flow_ctrl_lat_prescale_0_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_flow_ctrl_lat_prescale_i[0]), + .Q(com_tlm_u_tlm_rx_vc0_flow_ctrl_lat_prescale[0]) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_lat_timer_qxu_0_9_.INIT = 4'h8; + LUT2_L com_tlm_u_tlm_rx_vc0_flow_ctrl_lat_timer_qxu_0_9_ ( + .I0(com_tlm_u_tlm_rx_vc0_flow_ctrl_lat_timer[9]), + .I1(com_tlm_u_tlm_rx_vc0_flow_ctrl_un1_lat_timer_i), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_lat_timer_qxu[9]) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_lat_timer_qxu_0_4_.INIT = 4'h8; + LUT2_L com_tlm_u_tlm_rx_vc0_flow_ctrl_lat_timer_qxu_0_4_ ( + .I0(com_tlm_u_tlm_rx_vc0_flow_ctrl_lat_timer[4]), + .I1(com_tlm_u_tlm_rx_vc0_flow_ctrl_un1_lat_timer_i), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_lat_timer_qxu[4]) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_lat_timer_qxu_0_3_.INIT = 4'h8; + LUT2_L com_tlm_u_tlm_rx_vc0_flow_ctrl_lat_timer_qxu_0_3_ ( + .I0(com_tlm_u_tlm_rx_vc0_flow_ctrl_lat_timer[3]), + .I1(com_tlm_u_tlm_rx_vc0_flow_ctrl_un1_lat_timer_i), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_lat_timer_qxu[3]) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_lat_timer_qxu_0_2_.INIT = 4'h8; + LUT2_L com_tlm_u_tlm_rx_vc0_flow_ctrl_lat_timer_qxu_0_2_ ( + .I0(com_tlm_u_tlm_rx_vc0_flow_ctrl_lat_timer[2]), + .I1(com_tlm_u_tlm_rx_vc0_flow_ctrl_un1_lat_timer_i), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_lat_timer_qxu[2]) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_lat_timer_qxu_0_1_.INIT = 4'h8; + LUT2_L com_tlm_u_tlm_rx_vc0_flow_ctrl_lat_timer_qxu_0_1_ ( + .I0(com_tlm_u_tlm_rx_vc0_flow_ctrl_lat_timer[1]), + .I1(com_tlm_u_tlm_rx_vc0_flow_ctrl_un1_lat_timer_i), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_lat_timer_qxu[1]) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_lat_timer_qxu_0_0_.INIT = 4'h8; + LUT2_L com_tlm_u_tlm_rx_vc0_flow_ctrl_lat_timer_qxu_0_0_ ( + .I0(com_tlm_u_tlm_rx_vc0_flow_ctrl_lat_timer[0]), + .I1(com_tlm_u_tlm_rx_vc0_flow_ctrl_un1_lat_timer_i), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_lat_timer_qxu[0]) + ); + VCC com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_VCC ( + .P(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_VCC_3536) + ); + GND com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_GND ( + .G(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_GND_3548) + ); + FDS com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_send_state_0_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_N_68904_i_3609), + .Q(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_send_state_0__3611), + .S(plm_link_up_i) + ); + FDR com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_send_state_1_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_N_68903_i_3608), + .Q(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_req_p_src_rdy), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_send_state_2_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_N_68902_i_3607), + .Q(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_send_state_2__3610), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_d_con_0_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un1_fc_d_con_1_axb_0_3549), + .Q(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_d_con[0]), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_d_con_1_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un1_fc_d_con_1_s_1_3489), + .Q(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_d_con[1]), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_d_con_2_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un1_fc_d_con_1_s_2_3492), + .Q(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_d_con[2]), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_d_con_3_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un1_fc_d_con_1_s_3_3495), + .Q(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_d_con[3]), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_d_con_4_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un1_fc_d_con_1_s_4_3498), + .Q(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_d_con[4]), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_d_con_5_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un1_fc_d_con_1_s_5_3501), + .Q(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_d_con[5]), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_d_con_6_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un1_fc_d_con_1_s_6_3503), + .Q(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_d_con[6]), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_d_con_7_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un1_fc_d_con_1_s_7_3505), + .Q(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_d_con[7]), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_d_con_8_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un1_fc_d_con_1_s_8_3507), + .Q(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_d_con[8]), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_d_con_9_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un1_fc_d_con_1_s_9_3509), + .Q(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_d_con[9]), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_d_con_10_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un1_fc_d_con_1_s_10_3511), + .Q(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_d_con[10]), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_d_con_11_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un1_fc_d_con_1_s_11_3513), + .Q(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_d_con[11]), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_req_d_o_0_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_d_o_0[0]), + .Q(com_tlm_u_tlm_rx_fc_req_pd[0]), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_req_d_o_1_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_d_o_0[1]), + .Q(com_tlm_u_tlm_rx_fc_req_pd[1]), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_req_d_o_2_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_d_o_0[2]), + .Q(com_tlm_u_tlm_rx_fc_req_pd[2]), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_req_d_o_3_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_d_o_0[3]), + .Q(com_tlm_u_tlm_rx_fc_req_pd[3]), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_req_d_o_4_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_d_o_0[4]), + .Q(com_tlm_u_tlm_rx_fc_req_pd[4]), + .R(plm_link_up_i) + ); + FDS com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_req_d_o_5_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_d_o_0[5]), + .Q(com_tlm_u_tlm_rx_fc_req_pd[5]), + .S(plm_link_up_i) + ); + FDR com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_req_d_o_6_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_d_o_0[6]), + .Q(com_tlm_u_tlm_rx_fc_req_pd[6]), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_req_d_o_7_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_d_o_0[7]), + .Q(com_tlm_u_tlm_rx_fc_req_pd[7]), + .R(plm_link_up_i) + ); + FDS com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_req_d_o_8_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_d_o_0[8]), + .Q(com_tlm_u_tlm_rx_fc_req_pd[8]), + .S(plm_link_up_i) + ); + FDR com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_req_d_o_9_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_d_o_0[9]), + .Q(com_tlm_u_tlm_rx_fc_req_pd[9]), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_req_d_o_10_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_d_o_0[10]), + .Q(com_tlm_u_tlm_rx_fc_req_pd[10]), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_req_d_o_11_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_d_o_0[11]), + .Q(com_tlm_u_tlm_rx_fc_req_pd[11]), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_h_av_o_0_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_h_av_o_axb_0_i_3582), + .Q(trn_rfc_ph_av_5062[0]), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_h_av_o_1_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_h_av_o_s_1_3515), + .Q(trn_rfc_ph_av_5062[1]), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_h_av_o_2_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_h_av_o_s_2_3517), + .Q(trn_rfc_ph_av_5062[2]), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_h_av_o_3_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_h_av_o_s_3_3519), + .Q(trn_rfc_ph_av_5062[3]), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_h_av_o_4_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_h_av_o_s_4_3521), + .Q(trn_rfc_ph_av_5062[4]), + .R(plm_link_up_i) + ); + FDS com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_h_av_o_5_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_h_av_o_s_5_3523), + .Q(trn_rfc_ph_av_5062[5]), + .S(plm_link_up_i) + ); + FDR com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_h_av_o_6_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_h_av_o_s_6_3525), + .Q(trn_rfc_ph_av_5062[6]), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_h_av_o_7_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_h_av_o_s_7_3527), + .Q(trn_rfc_ph_av_5062[7]), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_d_av_o_0_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_d_av_o_axb_0_i_3573), + .Q(trn_rfc_pd_av_5063[0]), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_d_av_o_1_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_d_av_o_s_1_3465), + .Q(trn_rfc_pd_av_5063[1]), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_d_av_o_2_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_d_av_o_s_2_3467), + .Q(trn_rfc_pd_av_5063[2]), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_d_av_o_3_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_d_av_o_s_3_3469), + .Q(trn_rfc_pd_av_5063[3]), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_d_av_o_4_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_d_av_o_s_4_3471), + .Q(trn_rfc_pd_av_5063[4]), + .R(plm_link_up_i) + ); + FDS com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_d_av_o_5_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_d_av_o_s_5_3473), + .Q(trn_rfc_pd_av_5063[5]), + .S(plm_link_up_i) + ); + FDR com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_d_av_o_6_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_d_av_o_s_6_3475), + .Q(trn_rfc_pd_av_5063[6]), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_d_av_o_7_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_d_av_o_s_7_3477), + .Q(trn_rfc_pd_av_5063[7]), + .R(plm_link_up_i) + ); + FDS com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_d_av_o_8_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_d_av_o_s_8_3479), + .Q(trn_rfc_pd_av_5063[8]), + .S(plm_link_up_i) + ); + FDR com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_d_av_o_9_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_d_av_o_s_9_3481), + .Q(trn_rfc_pd_av_5063[9]), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_d_av_o_10_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_d_av_o_s_10_3483), + .Q(trn_rfc_pd_av_5063[10]), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_d_av_o_11_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_d_av_o_s_11_3485), + .Q(trn_rfc_pd_av_5063[11]), + .R(plm_link_up_i) + ); + FDRE com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_h_alo_0_ ( + .CE(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_gnt), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_lnk_tfc_header[0]), + .Q(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_h_alo[0]), + .R(plm_link_up_i) + ); + FDRE com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_h_alo_1_ ( + .CE(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_gnt), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_lnk_tfc_header[1]), + .Q(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_h_alo[1]), + .R(plm_link_up_i) + ); + FDRE com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_h_alo_2_ ( + .CE(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_gnt), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_lnk_tfc_header[2]), + .Q(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_h_alo[2]), + .R(plm_link_up_i) + ); + FDRE com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_h_alo_3_ ( + .CE(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_gnt), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_lnk_tfc_header[3]), + .Q(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_h_alo[3]), + .R(plm_link_up_i) + ); + FDRE com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_h_alo_4_ ( + .CE(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_gnt), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_lnk_tfc_header[4]), + .Q(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_h_alo[4]), + .R(plm_link_up_i) + ); + FDSE com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_h_alo_5_ ( + .CE(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_gnt), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_lnk_tfc_header[5]), + .Q(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_h_alo[5]), + .S(plm_link_up_i) + ); + FDRE com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_h_alo_6_ ( + .CE(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_gnt), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_lnk_tfc_header[6]), + .Q(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_h_alo[6]), + .R(plm_link_up_i) + ); + FDRE com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_h_alo_7_ ( + .CE(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_gnt), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_lnk_tfc_header[7]), + .Q(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_h_alo[7]), + .R(plm_link_up_i) + ); + FDRE com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_d_alo_0_ ( + .CE(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_gnt), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_lnk_tfc_data[0]), + .Q(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_d_alo[0]), + .R(plm_link_up_i) + ); + FDRE com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_d_alo_1_ ( + .CE(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_gnt), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_lnk_tfc_data[1]), + .Q(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_d_alo[1]), + .R(plm_link_up_i) + ); + FDRE com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_d_alo_2_ ( + .CE(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_gnt), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_lnk_tfc_data[2]), + .Q(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_d_alo[2]), + .R(plm_link_up_i) + ); + FDRE com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_d_alo_3_ ( + .CE(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_gnt), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_lnk_tfc_data[3]), + .Q(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_d_alo[3]), + .R(plm_link_up_i) + ); + FDRE com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_d_alo_4_ ( + .CE(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_gnt), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_lnk_tfc_data[4]), + .Q(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_d_alo[4]), + .R(plm_link_up_i) + ); + FDSE com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_d_alo_5_ ( + .CE(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_gnt), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_lnk_tfc_data[5]), + .Q(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_d_alo[5]), + .S(plm_link_up_i) + ); + FDRE com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_d_alo_6_ ( + .CE(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_gnt), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_lnk_tfc_data[6]), + .Q(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_d_alo[6]), + .R(plm_link_up_i) + ); + FDRE com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_d_alo_7_ ( + .CE(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_gnt), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_lnk_tfc_data[7]), + .Q(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_d_alo[7]), + .R(plm_link_up_i) + ); + FDSE com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_d_alo_8_ ( + .CE(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_gnt), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_lnk_tfc_data[8]), + .Q(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_d_alo[8]), + .S(plm_link_up_i) + ); + FDRE com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_d_alo_9_ ( + .CE(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_gnt), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_lnk_tfc_data[9]), + .Q(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_d_alo[9]), + .R(plm_link_up_i) + ); + FDRE com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_d_alo_10_ ( + .CE(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_gnt), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_lnk_tfc_data[10]), + .Q(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_d_alo[10]), + .R(plm_link_up_i) + ); + FDRE com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_d_alo_11_ ( + .CE(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_gnt), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_lnk_tfc_data[11]), + .Q(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_d_alo[11]), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_free_q2 ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_free_q_3438), + .Q(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_free_q2_3550), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_req_h_o_0_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_h_o_0[0]), + .Q(com_tlm_u_tlm_rx_fc_req_ph[0]), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_req_h_o_1_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_h_o_0[1]), + .Q(com_tlm_u_tlm_rx_fc_req_ph[1]), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_req_h_o_2_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_h_o_0[2]), + .Q(com_tlm_u_tlm_rx_fc_req_ph[2]), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_req_h_o_3_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_h_o_0[3]), + .Q(com_tlm_u_tlm_rx_fc_req_ph[3]), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_req_h_o_4_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_h_o_0[4]), + .Q(com_tlm_u_tlm_rx_fc_req_ph[4]), + .R(plm_link_up_i) + ); + FDS com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_req_h_o_5_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_h_o_0[5]), + .Q(com_tlm_u_tlm_rx_fc_req_ph[5]), + .S(plm_link_up_i) + ); + FDR com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_req_h_o_6_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_h_o_0[6]), + .Q(com_tlm_u_tlm_rx_fc_req_ph[6]), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_req_h_o_7_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_h_o_0[7]), + .Q(com_tlm_u_tlm_rx_fc_req_ph[7]), + .R(plm_link_up_i) + ); + FDRSE com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_free_hold ( + .CE(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_send_state_0__3611), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_GND_3548), + .Q(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_free_hold_3551), + .R(plm_link_up_i), + .S(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_free_hold13) + ); + FDR com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_free_q ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_free_q_3), + .Q(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_free_q_3438), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_free_h ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_free_h_3), + .Q(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_free_h_3439), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_free_d ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_free_d_3), + .Q(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_free_d_3448), + .R(plm_link_up_i) + ); + MUXCY_L com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_h_o_cry_0 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_free_h_3439), + .DI(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_N_41749_i), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_h_o_cry_0_3440), + .S(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_h_o_axb_0_3561) + ); + XORCY com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_h_o_s_0 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_free_h_3439), + .LI(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_h_o_axb_0_3561), + .O(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_h_o_0[0]) + ); + MUXCY_L com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_h_o_cry_1 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_h_o_cry_0_3440), + .DI(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_GND_3548), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_h_o_cry_1_3441), + .S(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_h_o_axb_1_3560) + ); + XORCY com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_h_o_s_1 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_h_o_cry_0_3440), + .LI(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_h_o_axb_1_3560), + .O(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_h_o_0[1]) + ); + MUXCY_L com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_h_o_cry_2 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_h_o_cry_1_3441), + .DI(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_GND_3548), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_h_o_cry_2_3442), + .S(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_h_o_axb_2_3559) + ); + XORCY com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_h_o_s_2 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_h_o_cry_1_3441), + .LI(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_h_o_axb_2_3559), + .O(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_h_o_0[2]) + ); + MUXCY_L com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_h_o_cry_3 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_h_o_cry_2_3442), + .DI(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_GND_3548), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_h_o_cry_3_3443), + .S(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_h_o_axb_3_3558) + ); + XORCY com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_h_o_s_3 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_h_o_cry_2_3442), + .LI(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_h_o_axb_3_3558), + .O(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_h_o_0[3]) + ); + MUXCY_L com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_h_o_cry_4 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_h_o_cry_3_3443), + .DI(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_GND_3548), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_h_o_cry_4_3444), + .S(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_h_o_axb_4_3557) + ); + XORCY com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_h_o_s_4 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_h_o_cry_3_3443), + .LI(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_h_o_axb_4_3557), + .O(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_h_o_0[4]) + ); + MUXCY_L com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_h_o_cry_5 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_h_o_cry_4_3444), + .DI(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_GND_3548), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_h_o_cry_5_3445), + .S(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_h_o_axb_5_3556) + ); + XORCY com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_h_o_s_5 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_h_o_cry_4_3444), + .LI(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_h_o_axb_5_3556), + .O(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_h_o_0[5]) + ); + MUXCY_L com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_h_o_cry_6 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_h_o_cry_5_3445), + .DI(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_GND_3548), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_h_o_cry_6_3446), + .S(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_h_o_axb_6_3555) + ); + XORCY com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_h_o_s_6 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_h_o_cry_5_3445), + .LI(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_h_o_axb_6_3555), + .O(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_h_o_0[6]) + ); + XORCY com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_h_o_s_7 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_h_o_cry_6_3446), + .LI(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_h_o_axb_7_3554), + .O(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_h_o_0[7]) + ); + MULT_AND com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_d_o_cry_0 ( + .I0(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_N_41749_i), + .I1(com_tlm_u_tlm_rx_fc_use_data[0]), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_d_o_cry_0_0_3447) + ); + MUXCY_L com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_d_o_cry_0_0 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_free_d_3448), + .DI(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_d_o_cry_0_0_3447), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_d_o_cry_0_3450), + .S(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_d_o_axb_0_3595) + ); + XORCY com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_d_o_s_0 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_free_d_3448), + .LI(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_d_o_axb_0_3595), + .O(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_d_o_0[0]) + ); + MULT_AND com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_d_o_cry_1 ( + .I0(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_N_41749_i), + .I1(com_tlm_u_tlm_rx_fc_use_data[1]), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_d_o_cry_1_0_3449) + ); + MUXCY_L com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_d_o_cry_1_0 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_d_o_cry_0_3450), + .DI(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_d_o_cry_1_0_3449), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_d_o_cry_1_3452), + .S(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_d_o_axb_1_3594) + ); + XORCY com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_d_o_s_1 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_d_o_cry_0_3450), + .LI(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_d_o_axb_1_3594), + .O(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_d_o_0[1]) + ); + MULT_AND com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_d_o_cry_2 ( + .I0(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_N_41749_i), + .I1(com_tlm_u_tlm_rx_fc_use_data[2]), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_d_o_cry_2_0_3451) + ); + MUXCY_L com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_d_o_cry_2_0 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_d_o_cry_1_3452), + .DI(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_d_o_cry_2_0_3451), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_d_o_cry_2_3454), + .S(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_d_o_axb_2_3593) + ); + XORCY com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_d_o_s_2 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_d_o_cry_1_3452), + .LI(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_d_o_axb_2_3593), + .O(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_d_o_0[2]) + ); + MULT_AND com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_d_o_cry_3 ( + .I0(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_N_41749_i), + .I1(com_tlm_u_tlm_rx_fc_use_data[3]), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_d_o_cry_3_0_3453) + ); + MUXCY_L com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_d_o_cry_3_0 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_d_o_cry_2_3454), + .DI(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_d_o_cry_3_0_3453), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_d_o_cry_3_3456), + .S(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_d_o_axb_3_3592) + ); + XORCY com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_d_o_s_3 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_d_o_cry_2_3454), + .LI(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_d_o_axb_3_3592), + .O(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_d_o_0[3]) + ); + MULT_AND com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_d_o_cry_4 ( + .I0(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_N_41749_i), + .I1(com_tlm_u_tlm_rx_fc_use_data[4]), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_d_o_cry_4_0_3455) + ); + MUXCY_L com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_d_o_cry_4_0 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_d_o_cry_3_3456), + .DI(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_d_o_cry_4_0_3455), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_d_o_cry_4_3458), + .S(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_d_o_axb_4_3591) + ); + XORCY com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_d_o_s_4 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_d_o_cry_3_3456), + .LI(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_d_o_axb_4_3591), + .O(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_d_o_0[4]) + ); + MULT_AND com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_d_o_cry_5 ( + .I0(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_N_41749_i), + .I1(com_tlm_u_tlm_rx_fc_use_data[5]), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_d_o_cry_5_0_3457) + ); + MUXCY_L com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_d_o_cry_5_0 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_d_o_cry_4_3458), + .DI(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_d_o_cry_5_0_3457), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_d_o_cry_5_3459), + .S(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_d_o_axb_5_3590) + ); + XORCY com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_d_o_s_5 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_d_o_cry_4_3458), + .LI(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_d_o_axb_5_3590), + .O(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_d_o_0[5]) + ); + MUXCY_L com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_d_o_cry_6 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_d_o_cry_5_3459), + .DI(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_GND_3548), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_d_o_cry_6_3460), + .S(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_d_o_axb_6_3589) + ); + XORCY com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_d_o_s_6 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_d_o_cry_5_3459), + .LI(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_d_o_axb_6_3589), + .O(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_d_o_0[6]) + ); + MUXCY_L com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_d_o_cry_7 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_d_o_cry_6_3460), + .DI(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_GND_3548), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_d_o_cry_7_3461), + .S(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_d_o_axb_7_3588) + ); + XORCY com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_d_o_s_7 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_d_o_cry_6_3460), + .LI(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_d_o_axb_7_3588), + .O(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_d_o_0[7]) + ); + MUXCY_L com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_d_o_cry_8 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_d_o_cry_7_3461), + .DI(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_GND_3548), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_d_o_cry_8_3462), + .S(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_d_o_axb_8_3587) + ); + XORCY com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_d_o_s_8 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_d_o_cry_7_3461), + .LI(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_d_o_axb_8_3587), + .O(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_d_o_0[8]) + ); + MUXCY_L com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_d_o_cry_9 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_d_o_cry_8_3462), + .DI(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_GND_3548), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_d_o_cry_9_3463), + .S(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_d_o_axb_9_3586) + ); + XORCY com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_d_o_s_9 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_d_o_cry_8_3462), + .LI(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_d_o_axb_9_3586), + .O(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_d_o_0[9]) + ); + MUXCY_L com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_d_o_cry_10 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_d_o_cry_9_3463), + .DI(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_GND_3548), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_d_o_cry_10_3464), + .S(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_d_o_axb_10_3585) + ); + XORCY com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_d_o_s_10 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_d_o_cry_9_3463), + .LI(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_d_o_axb_10_3585), + .O(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_d_o_0[10]) + ); + XORCY com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_d_o_s_11 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_d_o_cry_10_3464), + .LI(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_d_o_axb_11_3584), + .O(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_d_o_0[11]) + ); + MUXCY_L com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_d_av_o_cry_0 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_VCC_3536), + .DI(com_tlm_u_tlm_rx_fc_req_pd[0]), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_d_av_o_cry_0_3466), + .S(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_d_av_o_axb_0_3574) + ); + MUXCY_L com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_d_av_o_cry_1 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_d_av_o_cry_0_3466), + .DI(com_tlm_u_tlm_rx_fc_req_pd[1]), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_d_av_o_cry_1_3468), + .S(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_d_av_o_axb_1_3572) + ); + XORCY com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_d_av_o_s_1 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_d_av_o_cry_0_3466), + .LI(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_d_av_o_axb_1_3572), + .O(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_d_av_o_s_1_3465) + ); + MUXCY_L com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_d_av_o_cry_2 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_d_av_o_cry_1_3468), + .DI(com_tlm_u_tlm_rx_fc_req_pd[2]), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_d_av_o_cry_2_3470), + .S(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_d_av_o_axb_2_3571) + ); + XORCY com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_d_av_o_s_2 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_d_av_o_cry_1_3468), + .LI(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_d_av_o_axb_2_3571), + .O(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_d_av_o_s_2_3467) + ); + MUXCY_L com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_d_av_o_cry_3 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_d_av_o_cry_2_3470), + .DI(com_tlm_u_tlm_rx_fc_req_pd[3]), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_d_av_o_cry_3_3472), + .S(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_d_av_o_axb_3_3570) + ); + XORCY com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_d_av_o_s_3 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_d_av_o_cry_2_3470), + .LI(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_d_av_o_axb_3_3570), + .O(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_d_av_o_s_3_3469) + ); + MUXCY_L com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_d_av_o_cry_4 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_d_av_o_cry_3_3472), + .DI(com_tlm_u_tlm_rx_fc_req_pd[4]), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_d_av_o_cry_4_3474), + .S(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_d_av_o_axb_4_3569) + ); + XORCY com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_d_av_o_s_4 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_d_av_o_cry_3_3472), + .LI(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_d_av_o_axb_4_3569), + .O(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_d_av_o_s_4_3471) + ); + MUXCY_L com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_d_av_o_cry_5 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_d_av_o_cry_4_3474), + .DI(com_tlm_u_tlm_rx_fc_req_pd[5]), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_d_av_o_cry_5_3476), + .S(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_d_av_o_axb_5_3568) + ); + XORCY com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_d_av_o_s_5 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_d_av_o_cry_4_3474), + .LI(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_d_av_o_axb_5_3568), + .O(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_d_av_o_s_5_3473) + ); + MUXCY_L com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_d_av_o_cry_6 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_d_av_o_cry_5_3476), + .DI(com_tlm_u_tlm_rx_fc_req_pd[6]), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_d_av_o_cry_6_3478), + .S(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_d_av_o_axb_6_3567) + ); + XORCY com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_d_av_o_s_6 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_d_av_o_cry_5_3476), + .LI(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_d_av_o_axb_6_3567), + .O(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_d_av_o_s_6_3475) + ); + MUXCY_L com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_d_av_o_cry_7 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_d_av_o_cry_6_3478), + .DI(com_tlm_u_tlm_rx_fc_req_pd[7]), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_d_av_o_cry_7_3480), + .S(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_d_av_o_axb_7_3566) + ); + XORCY com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_d_av_o_s_7 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_d_av_o_cry_6_3478), + .LI(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_d_av_o_axb_7_3566), + .O(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_d_av_o_s_7_3477) + ); + MUXCY_L com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_d_av_o_cry_8 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_d_av_o_cry_7_3480), + .DI(com_tlm_u_tlm_rx_fc_req_pd[8]), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_d_av_o_cry_8_3482), + .S(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_d_av_o_axb_8_3565) + ); + XORCY com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_d_av_o_s_8 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_d_av_o_cry_7_3480), + .LI(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_d_av_o_axb_8_3565), + .O(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_d_av_o_s_8_3479) + ); + MUXCY_L com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_d_av_o_cry_9 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_d_av_o_cry_8_3482), + .DI(com_tlm_u_tlm_rx_fc_req_pd[9]), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_d_av_o_cry_9_3484), + .S(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_d_av_o_axb_9_3564) + ); + XORCY com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_d_av_o_s_9 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_d_av_o_cry_8_3482), + .LI(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_d_av_o_axb_9_3564), + .O(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_d_av_o_s_9_3481) + ); + MUXCY_L com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_d_av_o_cry_10 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_d_av_o_cry_9_3484), + .DI(com_tlm_u_tlm_rx_fc_req_pd[10]), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_d_av_o_cry_10_3486), + .S(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_d_av_o_axb_10_3563) + ); + XORCY com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_d_av_o_s_10 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_d_av_o_cry_9_3484), + .LI(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_d_av_o_axb_10_3563), + .O(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_d_av_o_s_10_3483) + ); + XORCY com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_d_av_o_s_11 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_d_av_o_cry_10_3486), + .LI(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_d_av_o_axb_11_3562), + .O(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_d_av_o_s_11_3485) + ); + MULT_AND com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un1_fc_d_con_1_cry_0 ( + .I0(com_tlm_u_tlm_rx_fc_use_p), + .I1(com_tlm_u_tlm_rx_fc_use_data[0]), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un1_fc_d_con_1_cry_0_0_3487) + ); + MUXCY_L com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un1_fc_d_con_1_cry_0_0 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_GND_3548), + .DI(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un1_fc_d_con_1_cry_0_0_3487), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un1_fc_d_con_1_cry_0_3490), + .S(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un1_fc_d_con_1_axb_0_3549) + ); + MULT_AND com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un1_fc_d_con_1_cry_1 ( + .I0(com_tlm_u_tlm_rx_fc_use_p), + .I1(com_tlm_u_tlm_rx_fc_use_data[1]), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un1_fc_d_con_1_cry_1_0_3488) + ); + MUXCY_L com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un1_fc_d_con_1_cry_1_0 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un1_fc_d_con_1_cry_0_3490), + .DI(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un1_fc_d_con_1_cry_1_0_3488), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un1_fc_d_con_1_cry_1_3493), + .S(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un1_fc_d_con_1_axb_1_3606) + ); + XORCY com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un1_fc_d_con_1_s_1 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un1_fc_d_con_1_cry_0_3490), + .LI(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un1_fc_d_con_1_axb_1_3606), + .O(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un1_fc_d_con_1_s_1_3489) + ); + MULT_AND com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un1_fc_d_con_1_cry_2 ( + .I0(com_tlm_u_tlm_rx_fc_use_p), + .I1(com_tlm_u_tlm_rx_fc_use_data[2]), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un1_fc_d_con_1_cry_2_0_3491) + ); + MUXCY_L com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un1_fc_d_con_1_cry_2_0 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un1_fc_d_con_1_cry_1_3493), + .DI(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un1_fc_d_con_1_cry_2_0_3491), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un1_fc_d_con_1_cry_2_3496), + .S(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un1_fc_d_con_1_axb_2_3605) + ); + XORCY com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un1_fc_d_con_1_s_2 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un1_fc_d_con_1_cry_1_3493), + .LI(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un1_fc_d_con_1_axb_2_3605), + .O(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un1_fc_d_con_1_s_2_3492) + ); + MULT_AND com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un1_fc_d_con_1_cry_3 ( + .I0(com_tlm_u_tlm_rx_fc_use_p), + .I1(com_tlm_u_tlm_rx_fc_use_data[3]), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un1_fc_d_con_1_cry_3_0_3494) + ); + MUXCY_L com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un1_fc_d_con_1_cry_3_0 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un1_fc_d_con_1_cry_2_3496), + .DI(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un1_fc_d_con_1_cry_3_0_3494), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un1_fc_d_con_1_cry_3_3499), + .S(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un1_fc_d_con_1_axb_3_3604) + ); + XORCY com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un1_fc_d_con_1_s_3 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un1_fc_d_con_1_cry_2_3496), + .LI(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un1_fc_d_con_1_axb_3_3604), + .O(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un1_fc_d_con_1_s_3_3495) + ); + MULT_AND com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un1_fc_d_con_1_cry_4 ( + .I0(com_tlm_u_tlm_rx_fc_use_p), + .I1(com_tlm_u_tlm_rx_fc_use_data[4]), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un1_fc_d_con_1_cry_4_0_3497) + ); + MUXCY_L com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un1_fc_d_con_1_cry_4_0 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un1_fc_d_con_1_cry_3_3499), + .DI(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un1_fc_d_con_1_cry_4_0_3497), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un1_fc_d_con_1_cry_4_3502), + .S(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un1_fc_d_con_1_axb_4_3603) + ); + XORCY com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un1_fc_d_con_1_s_4 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un1_fc_d_con_1_cry_3_3499), + .LI(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un1_fc_d_con_1_axb_4_3603), + .O(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un1_fc_d_con_1_s_4_3498) + ); + MULT_AND com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un1_fc_d_con_1_cry_5 ( + .I0(com_tlm_u_tlm_rx_fc_use_p), + .I1(com_tlm_u_tlm_rx_fc_use_data[5]), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un1_fc_d_con_1_cry_5_0_3500) + ); + MUXCY_L com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un1_fc_d_con_1_cry_5_0 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un1_fc_d_con_1_cry_4_3502), + .DI(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un1_fc_d_con_1_cry_5_0_3500), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un1_fc_d_con_1_cry_5_3504), + .S(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un1_fc_d_con_1_axb_5_3602) + ); + XORCY com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un1_fc_d_con_1_s_5 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un1_fc_d_con_1_cry_4_3502), + .LI(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un1_fc_d_con_1_axb_5_3602), + .O(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un1_fc_d_con_1_s_5_3501) + ); + MUXCY_L com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un1_fc_d_con_1_cry_6 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un1_fc_d_con_1_cry_5_3504), + .DI(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_GND_3548), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un1_fc_d_con_1_cry_6_3506), + .S(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un1_fc_d_con_1_axb_6_3601) + ); + XORCY com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un1_fc_d_con_1_s_6 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un1_fc_d_con_1_cry_5_3504), + .LI(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un1_fc_d_con_1_axb_6_3601), + .O(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un1_fc_d_con_1_s_6_3503) + ); + MUXCY_L com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un1_fc_d_con_1_cry_7 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un1_fc_d_con_1_cry_6_3506), + .DI(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_GND_3548), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un1_fc_d_con_1_cry_7_3508), + .S(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un1_fc_d_con_1_axb_7_3600) + ); + XORCY com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un1_fc_d_con_1_s_7 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un1_fc_d_con_1_cry_6_3506), + .LI(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un1_fc_d_con_1_axb_7_3600), + .O(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un1_fc_d_con_1_s_7_3505) + ); + MUXCY_L com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un1_fc_d_con_1_cry_8 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un1_fc_d_con_1_cry_7_3508), + .DI(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_GND_3548), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un1_fc_d_con_1_cry_8_3510), + .S(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un1_fc_d_con_1_axb_8_3599) + ); + XORCY com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un1_fc_d_con_1_s_8 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un1_fc_d_con_1_cry_7_3508), + .LI(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un1_fc_d_con_1_axb_8_3599), + .O(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un1_fc_d_con_1_s_8_3507) + ); + MUXCY_L com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un1_fc_d_con_1_cry_9 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un1_fc_d_con_1_cry_8_3510), + .DI(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_GND_3548), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un1_fc_d_con_1_cry_9_3512), + .S(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un1_fc_d_con_1_axb_9_3598) + ); + XORCY com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un1_fc_d_con_1_s_9 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un1_fc_d_con_1_cry_8_3510), + .LI(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un1_fc_d_con_1_axb_9_3598), + .O(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un1_fc_d_con_1_s_9_3509) + ); + MUXCY_L com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un1_fc_d_con_1_cry_10 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un1_fc_d_con_1_cry_9_3512), + .DI(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_GND_3548), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un1_fc_d_con_1_cry_10_3514), + .S(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un1_fc_d_con_1_axb_10_3597) + ); + XORCY com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un1_fc_d_con_1_s_10 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un1_fc_d_con_1_cry_9_3512), + .LI(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un1_fc_d_con_1_axb_10_3597), + .O(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un1_fc_d_con_1_s_10_3511) + ); + XORCY com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un1_fc_d_con_1_s_11 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un1_fc_d_con_1_cry_10_3514), + .LI(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un1_fc_d_con_1_axb_11_3596), + .O(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un1_fc_d_con_1_s_11_3513) + ); + MUXCY_L com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_h_av_o_cry_0 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_VCC_3536), + .DI(com_tlm_u_tlm_rx_fc_req_ph[0]), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_h_av_o_cry_0_3516), + .S(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_h_av_o_axb_0_3583) + ); + MUXCY_L com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_h_av_o_cry_1 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_h_av_o_cry_0_3516), + .DI(com_tlm_u_tlm_rx_fc_req_ph[1]), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_h_av_o_cry_1_3518), + .S(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_h_av_o_axb_1_3581) + ); + XORCY com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_h_av_o_s_1 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_h_av_o_cry_0_3516), + .LI(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_h_av_o_axb_1_3581), + .O(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_h_av_o_s_1_3515) + ); + MUXCY_L com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_h_av_o_cry_2 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_h_av_o_cry_1_3518), + .DI(com_tlm_u_tlm_rx_fc_req_ph[2]), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_h_av_o_cry_2_3520), + .S(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_h_av_o_axb_2_3580) + ); + XORCY com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_h_av_o_s_2 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_h_av_o_cry_1_3518), + .LI(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_h_av_o_axb_2_3580), + .O(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_h_av_o_s_2_3517) + ); + MUXCY_L com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_h_av_o_cry_3 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_h_av_o_cry_2_3520), + .DI(com_tlm_u_tlm_rx_fc_req_ph[3]), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_h_av_o_cry_3_3522), + .S(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_h_av_o_axb_3_3579) + ); + XORCY com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_h_av_o_s_3 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_h_av_o_cry_2_3520), + .LI(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_h_av_o_axb_3_3579), + .O(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_h_av_o_s_3_3519) + ); + MUXCY_L com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_h_av_o_cry_4 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_h_av_o_cry_3_3522), + .DI(com_tlm_u_tlm_rx_fc_req_ph[4]), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_h_av_o_cry_4_3524), + .S(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_h_av_o_axb_4_3578) + ); + XORCY com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_h_av_o_s_4 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_h_av_o_cry_3_3522), + .LI(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_h_av_o_axb_4_3578), + .O(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_h_av_o_s_4_3521) + ); + MUXCY_L com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_h_av_o_cry_5 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_h_av_o_cry_4_3524), + .DI(com_tlm_u_tlm_rx_fc_req_ph[5]), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_h_av_o_cry_5_3526), + .S(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_h_av_o_axb_5_3577) + ); + XORCY com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_h_av_o_s_5 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_h_av_o_cry_4_3524), + .LI(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_h_av_o_axb_5_3577), + .O(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_h_av_o_s_5_3523) + ); + MUXCY_L com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_h_av_o_cry_6 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_h_av_o_cry_5_3526), + .DI(com_tlm_u_tlm_rx_fc_req_ph[6]), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_h_av_o_cry_6_3528), + .S(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_h_av_o_axb_6_3576) + ); + XORCY com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_h_av_o_s_6 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_h_av_o_cry_5_3526), + .LI(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_h_av_o_axb_6_3576), + .O(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_h_av_o_s_6_3525) + ); + XORCY com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_h_av_o_s_7 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_h_av_o_cry_6_3528), + .LI(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_h_av_o_axb_7_3575), + .O(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_h_av_o_s_7_3527) + ); + MUXCY_L com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_h_advert_1_cry_0 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_VCC_3536), + .DI(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_h_alo[0]), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_h_advert_1_cry_0_3529), + .S(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_h_advert_1_axb_0_3629) + ); + MUXCY_L com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_h_advert_1_cry_1 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_h_advert_1_cry_0_3529), + .DI(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_h_alo[1]), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_h_advert_1_cry_1_3530), + .S(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_h_advert_1_axb_1_3628) + ); + MUXCY_L com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_h_advert_1_cry_2 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_h_advert_1_cry_1_3530), + .DI(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_h_alo[2]), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_h_advert_1_cry_2_3531), + .S(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_h_advert_1_axb_2_3627) + ); + MUXCY_L com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_h_advert_1_cry_3 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_h_advert_1_cry_2_3531), + .DI(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_h_alo[3]), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_h_advert_1_cry_3_3532), + .S(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_h_advert_1_axb_3_3626) + ); + MUXCY_L com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_h_advert_1_cry_4 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_h_advert_1_cry_3_3532), + .DI(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_h_alo[4]), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_h_advert_1_cry_4_3533), + .S(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_h_advert_1_axb_4_3625) + ); + MUXCY_L com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_h_advert_1_cry_5 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_h_advert_1_cry_4_3533), + .DI(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_h_alo[5]), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_h_advert_1_cry_5_3534), + .S(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_h_advert_1_axb_5_3624) + ); + MUXCY_L com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_h_advert_1_cry_6 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_h_advert_1_cry_5_3534), + .DI(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_h_alo[6]), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_h_advert_1_cry_6_3535), + .S(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_h_advert_1_axb_6_3623) + ); + XORCY com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_h_advert_1_s_7 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_h_advert_1_cry_6_3535), + .LI(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_h_advert_1_axb_7_3553), + .O(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_h_advert_1[7]) + ); + MUXCY_L com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_d_advert_1_cry_0 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_VCC_3536), + .DI(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_d_alo[0]), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_d_advert_1_cry_0_3537), + .S(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_d_advert_1_axb_0_3622) + ); + MUXCY_L com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_d_advert_1_cry_1 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_d_advert_1_cry_0_3537), + .DI(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_d_alo[1]), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_d_advert_1_cry_1_3538), + .S(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_d_advert_1_axb_1_3621) + ); + MUXCY_L com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_d_advert_1_cry_2 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_d_advert_1_cry_1_3538), + .DI(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_d_alo[2]), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_d_advert_1_cry_2_3539), + .S(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_d_advert_1_axb_2_3620) + ); + MUXCY_L com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_d_advert_1_cry_3 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_d_advert_1_cry_2_3539), + .DI(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_d_alo[3]), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_d_advert_1_cry_3_3540), + .S(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_d_advert_1_axb_3_3619) + ); + MUXCY_L com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_d_advert_1_cry_4 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_d_advert_1_cry_3_3540), + .DI(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_d_alo[4]), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_d_advert_1_cry_4_3541), + .S(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_d_advert_1_axb_4_3618) + ); + MUXCY_L com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_d_advert_1_cry_5 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_d_advert_1_cry_4_3541), + .DI(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_d_alo[5]), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_d_advert_1_cry_5_3542), + .S(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_d_advert_1_axb_5_3617) + ); + MUXCY_L com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_d_advert_1_cry_6 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_d_advert_1_cry_5_3542), + .DI(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_d_alo[6]), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_d_advert_1_cry_6_3543), + .S(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_d_advert_1_axb_6_3616) + ); + MUXCY_L com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_d_advert_1_cry_7 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_d_advert_1_cry_6_3543), + .DI(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_d_alo[7]), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_d_advert_1_cry_7_3544), + .S(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_d_advert_1_axb_7_3615) + ); + MUXCY_L com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_d_advert_1_cry_8 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_d_advert_1_cry_7_3544), + .DI(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_d_alo[8]), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_d_advert_1_cry_8_3545), + .S(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_d_advert_1_axb_8_3614) + ); + MUXCY_L com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_d_advert_1_cry_9 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_d_advert_1_cry_8_3545), + .DI(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_d_alo[9]), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_d_advert_1_cry_9_3546), + .S(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_d_advert_1_axb_9_3613) + ); + MUXCY_L com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_d_advert_1_cry_10 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_d_advert_1_cry_9_3546), + .DI(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_d_alo[10]), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_d_advert_1_cry_10_3547), + .S(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_d_advert_1_axb_10_3612) + ); + XORCY com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_d_advert_1_s_11 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_d_advert_1_cry_10_3547), + .LI(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_d_advert_1_axb_11_3552), + .O(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_d_advert_1[11]) + ); + FDRE com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_h_con_0_ ( + .CE(com_tlm_u_tlm_rx_fc_use_p), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_h_con_s[0]), + .Q(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_h_con[0]), + .R(plm_link_up_i) + ); + MUXCY_L com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_h_con_cry_1_ ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_h_con[0]), + .DI(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_GND_3548), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_h_con_cry[1]), + .S(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_h_con_qxu[1]) + ); + XORCY com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_h_con_s_1_ ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_h_con[0]), + .LI(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_h_con_qxu[1]), + .O(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_h_con_s[1]) + ); + FDRE com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_h_con_1_ ( + .CE(com_tlm_u_tlm_rx_fc_use_p), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_h_con_s[1]), + .Q(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_h_con[1]), + .R(plm_link_up_i) + ); + MUXCY_L com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_h_con_cry_2_ ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_h_con_cry[1]), + .DI(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_GND_3548), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_h_con_cry[2]), + .S(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_h_con_qxu[2]) + ); + XORCY com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_h_con_s_2_ ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_h_con_cry[1]), + .LI(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_h_con_qxu[2]), + .O(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_h_con_s[2]) + ); + FDRE com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_h_con_2_ ( + .CE(com_tlm_u_tlm_rx_fc_use_p), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_h_con_s[2]), + .Q(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_h_con[2]), + .R(plm_link_up_i) + ); + MUXCY_L com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_h_con_cry_3_ ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_h_con_cry[2]), + .DI(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_GND_3548), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_h_con_cry[3]), + .S(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_h_con_qxu[3]) + ); + XORCY com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_h_con_s_3_ ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_h_con_cry[2]), + .LI(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_h_con_qxu[3]), + .O(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_h_con_s[3]) + ); + FDRE com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_h_con_3_ ( + .CE(com_tlm_u_tlm_rx_fc_use_p), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_h_con_s[3]), + .Q(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_h_con[3]), + .R(plm_link_up_i) + ); + MUXCY_L com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_h_con_cry_4_ ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_h_con_cry[3]), + .DI(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_GND_3548), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_h_con_cry[4]), + .S(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_h_con_qxu[4]) + ); + XORCY com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_h_con_s_4_ ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_h_con_cry[3]), + .LI(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_h_con_qxu[4]), + .O(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_h_con_s[4]) + ); + FDRE com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_h_con_4_ ( + .CE(com_tlm_u_tlm_rx_fc_use_p), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_h_con_s[4]), + .Q(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_h_con[4]), + .R(plm_link_up_i) + ); + MUXCY_L com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_h_con_cry_5_ ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_h_con_cry[4]), + .DI(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_GND_3548), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_h_con_cry[5]), + .S(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_h_con_qxu[5]) + ); + XORCY com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_h_con_s_5_ ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_h_con_cry[4]), + .LI(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_h_con_qxu[5]), + .O(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_h_con_s[5]) + ); + FDRE com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_h_con_5_ ( + .CE(com_tlm_u_tlm_rx_fc_use_p), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_h_con_s[5]), + .Q(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_h_con[5]), + .R(plm_link_up_i) + ); + MUXCY_L com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_h_con_cry_6_ ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_h_con_cry[5]), + .DI(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_GND_3548), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_h_con_cry[6]), + .S(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_h_con_qxu[6]) + ); + XORCY com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_h_con_s_6_ ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_h_con_cry[5]), + .LI(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_h_con_qxu[6]), + .O(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_h_con_s[6]) + ); + FDRE com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_h_con_6_ ( + .CE(com_tlm_u_tlm_rx_fc_use_p), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_h_con_s[6]), + .Q(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_h_con[6]), + .R(plm_link_up_i) + ); + XORCY com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_h_con_s_7_ ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_h_con_cry[6]), + .LI(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_h_con_qxu[7]), + .O(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_h_con_s[7]) + ); + FDRE com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_h_con_7_ ( + .CE(com_tlm_u_tlm_rx_fc_use_p), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_h_con_s[7]), + .Q(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_h_con[7]), + .R(plm_link_up_i) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_unuse_direct_N_14448_i_0_o4.INIT = 4'h8; + LUT2 com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_unuse_direct_N_14448_i_0_o4 ( + .I0(com_tlm_u_tlm_rx_fc_unuse), + .I1(com_tlm_u_tlm_rx_fc_use_p), + .O(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_N_41749_i) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_free_hold13_0_a2_0_a2.INIT = 4'h2; + LUT2 com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_free_hold13_0_a2_0_a2 ( + .I0(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_free_q2_3550), + .I1(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_send_state_0__3611), + .O(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_free_hold13) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_send_state_13_0_i_0_a2_2_.INIT = 4'h8; + LUT2 com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_send_state_13_0_i_0_a2_2_ ( + .I0(com_tlm_u_tlm_rx_fc_req_p_dst_rdy), + .I1(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_req_p_src_rdy), + .O(com_tlm_u_tlm_rx_fc_send_state_0_sqmuxa) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_d_av_o_axb_0.INIT = 4'h9; + LUT2 com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_d_av_o_axb_0 ( + .I0(com_tlm_u_tlm_rx_fc_req_pd[0]), + .I1(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_d_con[0]), + .O(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_d_av_o_axb_0_3574) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_h_av_o_axb_0.INIT = 4'h9; + LUT2 com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_h_av_o_axb_0 ( + .I0(com_tlm_u_tlm_rx_fc_req_ph[0]), + .I1(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_h_con[0]), + .O(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_h_av_o_axb_0_3583) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un1_fc_d_con_1_axb_0.INIT = 8'h78; + LUT3 com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un1_fc_d_con_1_axb_0 ( + .I0(com_tlm_u_tlm_rx_fc_use_data[0]), + .I1(com_tlm_u_tlm_rx_fc_use_p), + .I2(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_d_con[0]), + .O(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un1_fc_d_con_1_axb_0_3549) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_send_state_13_0_i_0_o4_1_.INIT = 16'h0001; + LUT4 com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_send_state_13_0_i_0_o4_1_ ( + .I0(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_N_41749_i), + .I1(com_tlm_u_tlm_rx_vc0_flow_ctrl_lat_timer[9]), + .I2(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_free_hold_3551), + .I3(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_free_q2_3550), + .O(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_N_42050_i) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_gnt_0_a2_0_a2_0_a2.INIT = 4'h4; + LUT2 com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_gnt_0_a2_0_a2_0_a2 ( + .I0(com_lnk_tfc_type[0]), + .I1(com_tlm_u_tlm_rx_vc0_flow_ctrl_fc_gnt_3), + .O(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_gnt) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_d_advert_1_axb_11.INIT = 4'h9; + LUT2_L com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_d_advert_1_axb_11 ( + .I0(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_d_alo[11]), + .I1(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_d_con[11]), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_d_advert_1_axb_11_3552) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_h_advert_1_axb_7.INIT = 4'h9; + LUT2_L com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_h_advert_1_axb_7 ( + .I0(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_h_alo[7]), + .I1(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_h_con[7]), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_h_advert_1_axb_7_3553) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_free_d_3_0_a2.INIT = 4'h8; + LUT2_L com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_free_d_3_0_a2 ( + .I0(com_tlm_u_tlm_rx_vc0_fc_free_1data), + .I1(com_tlm_u_tlm_rx_vc0_fc_free_p), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_free_d_3) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_free_h_3_0_a2.INIT = 4'h8; + LUT2_L com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_free_h_3_0_a2 ( + .I0(com_tlm_u_tlm_rx_vc0_fc_free_1header), + .I1(com_tlm_u_tlm_rx_vc0_fc_free_p), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_free_h_3) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_free_q_3_0_a2.INIT = 4'h8; + LUT2_L com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_free_q_3_0_a2 ( + .I0(com_tlm_u_tlm_rx_vc0_fc_free_eof), + .I1(com_tlm_u_tlm_rx_vc0_fc_free_p), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_free_q_3) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_h_o_axb_7.INIT = 4'h2; + LUT1_L com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_h_o_axb_7 ( + .I0(com_tlm_u_tlm_rx_fc_req_ph[7]), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_h_o_axb_7_3554) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_h_o_axb_6.INIT = 4'h2; + LUT1_L com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_h_o_axb_6 ( + .I0(com_tlm_u_tlm_rx_fc_req_ph[6]), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_h_o_axb_6_3555) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_h_o_axb_5.INIT = 4'h2; + LUT1_L com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_h_o_axb_5 ( + .I0(com_tlm_u_tlm_rx_fc_req_ph[5]), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_h_o_axb_5_3556) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_h_o_axb_4.INIT = 4'h2; + LUT1_L com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_h_o_axb_4 ( + .I0(com_tlm_u_tlm_rx_fc_req_ph[4]), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_h_o_axb_4_3557) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_h_o_axb_3.INIT = 4'h2; + LUT1_L com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_h_o_axb_3 ( + .I0(com_tlm_u_tlm_rx_fc_req_ph[3]), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_h_o_axb_3_3558) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_h_o_axb_2.INIT = 4'h2; + LUT1_L com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_h_o_axb_2 ( + .I0(com_tlm_u_tlm_rx_fc_req_ph[2]), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_h_o_axb_2_3559) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_h_o_axb_1.INIT = 4'h2; + LUT1_L com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_h_o_axb_1 ( + .I0(com_tlm_u_tlm_rx_fc_req_ph[1]), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_h_o_axb_1_3560) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_h_o_axb_0.INIT = 4'h6; + LUT2_L com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_h_o_axb_0 ( + .I0(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_N_41749_i), + .I1(com_tlm_u_tlm_rx_fc_req_ph[0]), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_h_o_axb_0_3561) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_d_av_o_axb_11.INIT = 4'h9; + LUT2_L com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_d_av_o_axb_11 ( + .I0(com_tlm_u_tlm_rx_fc_req_pd[11]), + .I1(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_d_con[11]), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_d_av_o_axb_11_3562) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_d_av_o_axb_10.INIT = 4'h9; + LUT2_L com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_d_av_o_axb_10 ( + .I0(com_tlm_u_tlm_rx_fc_req_pd[10]), + .I1(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_d_con[10]), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_d_av_o_axb_10_3563) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_d_av_o_axb_9.INIT = 4'h9; + LUT2_L com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_d_av_o_axb_9 ( + .I0(com_tlm_u_tlm_rx_fc_req_pd[9]), + .I1(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_d_con[9]), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_d_av_o_axb_9_3564) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_d_av_o_axb_8.INIT = 4'h9; + LUT2_L com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_d_av_o_axb_8 ( + .I0(com_tlm_u_tlm_rx_fc_req_pd[8]), + .I1(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_d_con[8]), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_d_av_o_axb_8_3565) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_d_av_o_axb_7.INIT = 4'h9; + LUT2_L com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_d_av_o_axb_7 ( + .I0(com_tlm_u_tlm_rx_fc_req_pd[7]), + .I1(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_d_con[7]), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_d_av_o_axb_7_3566) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_d_av_o_axb_6.INIT = 4'h9; + LUT2_L com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_d_av_o_axb_6 ( + .I0(com_tlm_u_tlm_rx_fc_req_pd[6]), + .I1(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_d_con[6]), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_d_av_o_axb_6_3567) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_d_av_o_axb_5.INIT = 4'h9; + LUT2_L com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_d_av_o_axb_5 ( + .I0(com_tlm_u_tlm_rx_fc_req_pd[5]), + .I1(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_d_con[5]), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_d_av_o_axb_5_3568) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_d_av_o_axb_4.INIT = 4'h9; + LUT2_L com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_d_av_o_axb_4 ( + .I0(com_tlm_u_tlm_rx_fc_req_pd[4]), + .I1(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_d_con[4]), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_d_av_o_axb_4_3569) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_d_av_o_axb_3.INIT = 4'h9; + LUT2_L com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_d_av_o_axb_3 ( + .I0(com_tlm_u_tlm_rx_fc_req_pd[3]), + .I1(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_d_con[3]), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_d_av_o_axb_3_3570) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_d_av_o_axb_2.INIT = 4'h9; + LUT2_L com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_d_av_o_axb_2 ( + .I0(com_tlm_u_tlm_rx_fc_req_pd[2]), + .I1(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_d_con[2]), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_d_av_o_axb_2_3571) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_d_av_o_axb_1.INIT = 4'h9; + LUT2_L com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_d_av_o_axb_1 ( + .I0(com_tlm_u_tlm_rx_fc_req_pd[1]), + .I1(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_d_con[1]), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_d_av_o_axb_1_3572) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_d_av_o_axb_0_i.INIT = 4'h1; + LUT1_L com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_d_av_o_axb_0_i ( + .I0(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_d_av_o_axb_0_3574), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_d_av_o_axb_0_i_3573) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_h_av_o_axb_7.INIT = 4'h9; + LUT2_L com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_h_av_o_axb_7 ( + .I0(com_tlm_u_tlm_rx_fc_req_ph[7]), + .I1(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_h_con[7]), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_h_av_o_axb_7_3575) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_h_av_o_axb_6.INIT = 4'h9; + LUT2_L com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_h_av_o_axb_6 ( + .I0(com_tlm_u_tlm_rx_fc_req_ph[6]), + .I1(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_h_con[6]), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_h_av_o_axb_6_3576) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_h_av_o_axb_5.INIT = 4'h9; + LUT2_L com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_h_av_o_axb_5 ( + .I0(com_tlm_u_tlm_rx_fc_req_ph[5]), + .I1(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_h_con[5]), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_h_av_o_axb_5_3577) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_h_av_o_axb_4.INIT = 4'h9; + LUT2_L com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_h_av_o_axb_4 ( + .I0(com_tlm_u_tlm_rx_fc_req_ph[4]), + .I1(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_h_con[4]), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_h_av_o_axb_4_3578) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_h_av_o_axb_3.INIT = 4'h9; + LUT2_L com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_h_av_o_axb_3 ( + .I0(com_tlm_u_tlm_rx_fc_req_ph[3]), + .I1(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_h_con[3]), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_h_av_o_axb_3_3579) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_h_av_o_axb_2.INIT = 4'h9; + LUT2_L com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_h_av_o_axb_2 ( + .I0(com_tlm_u_tlm_rx_fc_req_ph[2]), + .I1(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_h_con[2]), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_h_av_o_axb_2_3580) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_h_av_o_axb_1.INIT = 4'h9; + LUT2_L com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_h_av_o_axb_1 ( + .I0(com_tlm_u_tlm_rx_fc_req_ph[1]), + .I1(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_h_con[1]), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_h_av_o_axb_1_3581) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_h_av_o_axb_0_i.INIT = 4'h1; + LUT1_L com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_h_av_o_axb_0_i ( + .I0(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_h_av_o_axb_0_3583), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_h_av_o_axb_0_i_3582) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_d_o_axb_11.INIT = 4'h2; + LUT1_L com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_d_o_axb_11 ( + .I0(com_tlm_u_tlm_rx_fc_req_pd[11]), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_d_o_axb_11_3584) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_d_o_axb_10.INIT = 4'h2; + LUT1_L com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_d_o_axb_10 ( + .I0(com_tlm_u_tlm_rx_fc_req_pd[10]), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_d_o_axb_10_3585) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_d_o_axb_9.INIT = 4'h2; + LUT1_L com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_d_o_axb_9 ( + .I0(com_tlm_u_tlm_rx_fc_req_pd[9]), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_d_o_axb_9_3586) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_d_o_axb_8.INIT = 4'h2; + LUT1_L com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_d_o_axb_8 ( + .I0(com_tlm_u_tlm_rx_fc_req_pd[8]), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_d_o_axb_8_3587) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_d_o_axb_7.INIT = 4'h2; + LUT1_L com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_d_o_axb_7 ( + .I0(com_tlm_u_tlm_rx_fc_req_pd[7]), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_d_o_axb_7_3588) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_d_o_axb_6.INIT = 4'h2; + LUT1_L com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_d_o_axb_6 ( + .I0(com_tlm_u_tlm_rx_fc_req_pd[6]), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_d_o_axb_6_3589) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_d_o_axb_5.INIT = 8'h6C; + LUT3_L com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_d_o_axb_5 ( + .I0(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_N_41749_i), + .I1(com_tlm_u_tlm_rx_fc_req_pd[5]), + .I2(com_tlm_u_tlm_rx_fc_use_data[5]), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_d_o_axb_5_3590) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_d_o_axb_4.INIT = 8'h6C; + LUT3_L com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_d_o_axb_4 ( + .I0(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_N_41749_i), + .I1(com_tlm_u_tlm_rx_fc_req_pd[4]), + .I2(com_tlm_u_tlm_rx_fc_use_data[4]), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_d_o_axb_4_3591) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_d_o_axb_3.INIT = 8'h6C; + LUT3_L com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_d_o_axb_3 ( + .I0(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_N_41749_i), + .I1(com_tlm_u_tlm_rx_fc_req_pd[3]), + .I2(com_tlm_u_tlm_rx_fc_use_data[3]), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_d_o_axb_3_3592) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_d_o_axb_2.INIT = 8'h6C; + LUT3_L com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_d_o_axb_2 ( + .I0(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_N_41749_i), + .I1(com_tlm_u_tlm_rx_fc_req_pd[2]), + .I2(com_tlm_u_tlm_rx_fc_use_data[2]), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_d_o_axb_2_3593) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_d_o_axb_1.INIT = 8'h6C; + LUT3_L com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_d_o_axb_1 ( + .I0(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_N_41749_i), + .I1(com_tlm_u_tlm_rx_fc_req_pd[1]), + .I2(com_tlm_u_tlm_rx_fc_use_data[1]), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_d_o_axb_1_3594) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_d_o_axb_0.INIT = 8'h6C; + LUT3_L com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_d_o_axb_0 ( + .I0(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_N_41749_i), + .I1(com_tlm_u_tlm_rx_fc_req_pd[0]), + .I2(com_tlm_u_tlm_rx_fc_use_data[0]), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_d_o_axb_0_3595) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un1_fc_d_con_1_axb_11.INIT = 4'h2; + LUT1_L com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un1_fc_d_con_1_axb_11 ( + .I0(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_d_con[11]), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un1_fc_d_con_1_axb_11_3596) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un1_fc_d_con_1_axb_10.INIT = 4'h2; + LUT1_L com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un1_fc_d_con_1_axb_10 ( + .I0(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_d_con[10]), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un1_fc_d_con_1_axb_10_3597) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un1_fc_d_con_1_axb_9.INIT = 4'h2; + LUT1_L com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un1_fc_d_con_1_axb_9 ( + .I0(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_d_con[9]), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un1_fc_d_con_1_axb_9_3598) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un1_fc_d_con_1_axb_8.INIT = 4'h2; + LUT1_L com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un1_fc_d_con_1_axb_8 ( + .I0(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_d_con[8]), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un1_fc_d_con_1_axb_8_3599) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un1_fc_d_con_1_axb_7.INIT = 4'h2; + LUT1_L com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un1_fc_d_con_1_axb_7 ( + .I0(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_d_con[7]), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un1_fc_d_con_1_axb_7_3600) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un1_fc_d_con_1_axb_6.INIT = 4'h2; + LUT1_L com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un1_fc_d_con_1_axb_6 ( + .I0(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_d_con[6]), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un1_fc_d_con_1_axb_6_3601) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un1_fc_d_con_1_axb_5.INIT = 8'h78; + LUT3_L com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un1_fc_d_con_1_axb_5 ( + .I0(com_tlm_u_tlm_rx_fc_use_data[5]), + .I1(com_tlm_u_tlm_rx_fc_use_p), + .I2(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_d_con[5]), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un1_fc_d_con_1_axb_5_3602) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un1_fc_d_con_1_axb_4.INIT = 8'h78; + LUT3_L com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un1_fc_d_con_1_axb_4 ( + .I0(com_tlm_u_tlm_rx_fc_use_data[4]), + .I1(com_tlm_u_tlm_rx_fc_use_p), + .I2(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_d_con[4]), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un1_fc_d_con_1_axb_4_3603) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un1_fc_d_con_1_axb_3.INIT = 8'h78; + LUT3_L com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un1_fc_d_con_1_axb_3 ( + .I0(com_tlm_u_tlm_rx_fc_use_data[3]), + .I1(com_tlm_u_tlm_rx_fc_use_p), + .I2(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_d_con[3]), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un1_fc_d_con_1_axb_3_3604) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un1_fc_d_con_1_axb_2.INIT = 8'h78; + LUT3_L com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un1_fc_d_con_1_axb_2 ( + .I0(com_tlm_u_tlm_rx_fc_use_data[2]), + .I1(com_tlm_u_tlm_rx_fc_use_p), + .I2(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_d_con[2]), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un1_fc_d_con_1_axb_2_3605) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un1_fc_d_con_1_axb_1.INIT = 8'h78; + LUT3_L com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un1_fc_d_con_1_axb_1 ( + .I0(com_tlm_u_tlm_rx_fc_use_data[1]), + .I1(com_tlm_u_tlm_rx_fc_use_p), + .I2(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_d_con[1]), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un1_fc_d_con_1_axb_1_3606) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_N_68902_i.INIT = 8'hF4; + LUT3_L com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_N_68902_i ( + .I0(com_tlm_u_tlm_rx_fc_sched_p), + .I1(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_send_state_2__3610), + .I2(com_tlm_u_tlm_rx_fc_send_state_0_sqmuxa), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_N_68902_i_3607) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_N_68903_i.INIT = 16'h7530; + LUT4_L com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_N_68903_i ( + .I0(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_N_42050_i), + .I1(com_tlm_u_tlm_rx_fc_req_p_dst_rdy), + .I2(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_req_p_src_rdy), + .I3(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_send_state_0__3611), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_N_68903_i_3608) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_N_68904_i.INIT = 16'hECA0; + LUT4_L com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_N_68904_i ( + .I0(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_N_42050_i), + .I1(com_tlm_u_tlm_rx_fc_sched_p), + .I2(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_send_state_0__3611), + .I3(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_send_state_2__3610), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_N_68904_i_3609) + ); + FD com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_d_advert_11_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_d_advert_1[11]), + .Q(com_tlm_u_tlm_rx_vc0_flow_ctrl_fc_d_advert_0[11]) + ); + FD com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_h_advert_7_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_h_advert_1[7]), + .Q(com_tlm_u_tlm_rx_vc0_flow_ctrl_fc_h_advert_0[7]) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_h_con_qxu_0_0_.INIT = 4'h2; + LUT1_L com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_h_con_qxu_0_0_ ( + .I0(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_h_con[0]), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_h_con_qxu[0]) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_h_con_qxu_0_7_.INIT = 4'h2; + LUT1_L com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_h_con_qxu_0_7_ ( + .I0(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_h_con[7]), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_h_con_qxu[7]) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_h_con_qxu_0_6_.INIT = 4'h2; + LUT1_L com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_h_con_qxu_0_6_ ( + .I0(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_h_con[6]), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_h_con_qxu[6]) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_h_con_qxu_0_5_.INIT = 4'h2; + LUT1_L com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_h_con_qxu_0_5_ ( + .I0(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_h_con[5]), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_h_con_qxu[5]) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_h_con_qxu_0_4_.INIT = 4'h2; + LUT1_L com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_h_con_qxu_0_4_ ( + .I0(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_h_con[4]), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_h_con_qxu[4]) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_h_con_qxu_0_3_.INIT = 4'h2; + LUT1_L com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_h_con_qxu_0_3_ ( + .I0(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_h_con[3]), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_h_con_qxu[3]) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_h_con_qxu_0_2_.INIT = 4'h2; + LUT1_L com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_h_con_qxu_0_2_ ( + .I0(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_h_con[2]), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_h_con_qxu[2]) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_h_con_qxu_0_1_.INIT = 4'h2; + LUT1_L com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_h_con_qxu_0_1_ ( + .I0(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_h_con[1]), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_h_con_qxu[1]) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_h_con_s_0_.INIT = 4'h1; + LUT1_L com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_h_con_s_0_ ( + .I0(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_h_con_qxu[0]), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_h_con_s[0]) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_d_advert_1_axb_10.INIT = 4'h9; + LUT2 com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_d_advert_1_axb_10 ( + .I0(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_d_alo[10]), + .I1(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_d_con[10]), + .O(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_d_advert_1_axb_10_3612) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_d_advert_1_axb_9.INIT = 4'h9; + LUT2 com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_d_advert_1_axb_9 ( + .I0(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_d_alo[9]), + .I1(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_d_con[9]), + .O(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_d_advert_1_axb_9_3613) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_d_advert_1_axb_8.INIT = 4'h9; + LUT2 com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_d_advert_1_axb_8 ( + .I0(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_d_alo[8]), + .I1(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_d_con[8]), + .O(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_d_advert_1_axb_8_3614) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_d_advert_1_axb_7.INIT = 4'h9; + LUT2 com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_d_advert_1_axb_7 ( + .I0(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_d_alo[7]), + .I1(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_d_con[7]), + .O(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_d_advert_1_axb_7_3615) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_d_advert_1_axb_6.INIT = 4'h9; + LUT2 com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_d_advert_1_axb_6 ( + .I0(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_d_alo[6]), + .I1(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_d_con[6]), + .O(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_d_advert_1_axb_6_3616) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_d_advert_1_axb_5.INIT = 4'h9; + LUT2 com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_d_advert_1_axb_5 ( + .I0(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_d_alo[5]), + .I1(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_d_con[5]), + .O(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_d_advert_1_axb_5_3617) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_d_advert_1_axb_4.INIT = 4'h9; + LUT2 com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_d_advert_1_axb_4 ( + .I0(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_d_alo[4]), + .I1(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_d_con[4]), + .O(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_d_advert_1_axb_4_3618) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_d_advert_1_axb_3.INIT = 4'h9; + LUT2 com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_d_advert_1_axb_3 ( + .I0(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_d_alo[3]), + .I1(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_d_con[3]), + .O(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_d_advert_1_axb_3_3619) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_d_advert_1_axb_2.INIT = 4'h9; + LUT2 com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_d_advert_1_axb_2 ( + .I0(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_d_alo[2]), + .I1(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_d_con[2]), + .O(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_d_advert_1_axb_2_3620) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_d_advert_1_axb_1.INIT = 4'h9; + LUT2 com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_d_advert_1_axb_1 ( + .I0(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_d_alo[1]), + .I1(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_d_con[1]), + .O(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_d_advert_1_axb_1_3621) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_d_advert_1_axb_0.INIT = 4'h9; + LUT2 com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_d_advert_1_axb_0 ( + .I0(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_d_alo[0]), + .I1(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_d_con[0]), + .O(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_d_advert_1_axb_0_3622) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_h_advert_1_axb_6.INIT = 4'h9; + LUT2 com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_h_advert_1_axb_6 ( + .I0(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_h_alo[6]), + .I1(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_h_con[6]), + .O(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_h_advert_1_axb_6_3623) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_h_advert_1_axb_5.INIT = 4'h9; + LUT2 com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_h_advert_1_axb_5 ( + .I0(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_h_alo[5]), + .I1(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_h_con[5]), + .O(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_h_advert_1_axb_5_3624) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_h_advert_1_axb_4.INIT = 4'h9; + LUT2 com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_h_advert_1_axb_4 ( + .I0(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_h_alo[4]), + .I1(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_h_con[4]), + .O(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_h_advert_1_axb_4_3625) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_h_advert_1_axb_3.INIT = 4'h9; + LUT2 com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_h_advert_1_axb_3 ( + .I0(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_h_alo[3]), + .I1(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_h_con[3]), + .O(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_h_advert_1_axb_3_3626) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_h_advert_1_axb_2.INIT = 4'h9; + LUT2 com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_h_advert_1_axb_2 ( + .I0(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_h_alo[2]), + .I1(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_h_con[2]), + .O(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_h_advert_1_axb_2_3627) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_h_advert_1_axb_1.INIT = 4'h9; + LUT2 com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_h_advert_1_axb_1 ( + .I0(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_h_alo[1]), + .I1(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_h_con[1]), + .O(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_h_advert_1_axb_1_3628) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_h_advert_1_axb_0.INIT = 4'h9; + LUT2 com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_h_advert_1_axb_0 ( + .I0(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_h_alo[0]), + .I1(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_h_con[0]), + .O(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_h_advert_1_axb_0_3629) + ); + VCC com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_VCC ( + .P(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_VCC_3717) + ); + GND com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_GND ( + .G(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_GND_3729) + ); + FDS com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_send_state_0_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_N_68907_i_3790), + .Q(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_send_state_0__3792), + .S(plm_link_up_i) + ); + FDR com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_send_state_1_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_N_68906_i_3789), + .Q(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_req_np_src_rdy), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_send_state_2_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_N_68905_i_3788), + .Q(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_send_state_2__3791), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_d_con_0_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un1_fc_d_con_1_axb_0_3730), + .Q(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_d_con[0]), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_d_con_1_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un1_fc_d_con_1_s_1_0), + .Q(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_d_con[1]), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_d_con_2_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un1_fc_d_con_1_s_2_0), + .Q(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_d_con[2]), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_d_con_3_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un1_fc_d_con_1_s_3_0), + .Q(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_d_con[3]), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_d_con_4_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un1_fc_d_con_1_s_4_0), + .Q(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_d_con[4]), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_d_con_5_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un1_fc_d_con_1_s_5_0), + .Q(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_d_con[5]), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_d_con_6_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un1_fc_d_con_1_s_6_0), + .Q(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_d_con[6]), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_d_con_7_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un1_fc_d_con_1_s_7_0), + .Q(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_d_con[7]), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_d_con_8_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un1_fc_d_con_1_s_8_0), + .Q(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_d_con[8]), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_d_con_9_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un1_fc_d_con_1_s_9_0), + .Q(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_d_con[9]), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_d_con_10_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un1_fc_d_con_1_s_10_0), + .Q(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_d_con[10]), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_d_con_11_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un1_fc_d_con_1_s_11_0), + .Q(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_d_con[11]), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_req_d_o_0_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_d_o_0[0]), + .Q(com_tlm_u_tlm_rx_fc_req_npd[0]), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_req_d_o_1_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_d_o_0[1]), + .Q(com_tlm_u_tlm_rx_fc_req_npd[1]), + .R(plm_link_up_i) + ); + FDS com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_req_d_o_2_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_d_o_0[2]), + .Q(com_tlm_u_tlm_rx_fc_req_npd[2]), + .S(plm_link_up_i) + ); + FDS com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_req_d_o_3_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_d_o_0[3]), + .Q(com_tlm_u_tlm_rx_fc_req_npd[3]), + .S(plm_link_up_i) + ); + FDR com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_req_d_o_4_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_d_o_0[4]), + .Q(com_tlm_u_tlm_rx_fc_req_npd[4]), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_req_d_o_5_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_d_o_0[5]), + .Q(com_tlm_u_tlm_rx_fc_req_npd[5]), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_req_d_o_6_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_d_o_0[6]), + .Q(com_tlm_u_tlm_rx_fc_req_npd[6]), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_req_d_o_7_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_d_o_0[7]), + .Q(com_tlm_u_tlm_rx_fc_req_npd[7]), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_req_d_o_8_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_d_o_0[8]), + .Q(com_tlm_u_tlm_rx_fc_req_npd[8]), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_req_d_o_9_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_d_o_0[9]), + .Q(com_tlm_u_tlm_rx_fc_req_npd[9]), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_req_d_o_10_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_d_o_0[10]), + .Q(com_tlm_u_tlm_rx_fc_req_npd[10]), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_req_d_o_11_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_d_o_0[11]), + .Q(com_tlm_u_tlm_rx_fc_req_npd[11]), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_h_av_o_0_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un35_fc_h_av_o_axb_0_i_3763), + .Q(trn_rfc_nph_av_5060[0]), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_h_av_o_1_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un35_fc_h_av_o_s_1_3674), + .Q(trn_rfc_nph_av_5060[1]), + .R(plm_link_up_i) + ); + FDS com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_h_av_o_2_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un35_fc_h_av_o_s_2_3676), + .Q(trn_rfc_nph_av_5060[2]), + .S(plm_link_up_i) + ); + FDS com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_h_av_o_3_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un35_fc_h_av_o_s_3_3678), + .Q(trn_rfc_nph_av_5060[3]), + .S(plm_link_up_i) + ); + FDR com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_h_av_o_4_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un35_fc_h_av_o_s_4_3680), + .Q(trn_rfc_nph_av_5060[4]), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_h_av_o_5_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un35_fc_h_av_o_s_5_3682), + .Q(trn_rfc_nph_av_5060[5]), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_h_av_o_6_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un35_fc_h_av_o_s_6_3684), + .Q(trn_rfc_nph_av_5060[6]), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_h_av_o_7_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un35_fc_h_av_o_s_7_3686), + .Q(trn_rfc_nph_av_5060[7]), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_d_av_o_0_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un36_fc_d_av_o_axb_0_i_3754), + .Q(trn_rfc_npd_av_5061[0]), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_d_av_o_1_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un36_fc_d_av_o_s_1_3688), + .Q(trn_rfc_npd_av_5061[1]), + .R(plm_link_up_i) + ); + FDS com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_d_av_o_2_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un36_fc_d_av_o_s_2_3690), + .Q(trn_rfc_npd_av_5061[2]), + .S(plm_link_up_i) + ); + FDS com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_d_av_o_3_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un36_fc_d_av_o_s_3_3692), + .Q(trn_rfc_npd_av_5061[3]), + .S(plm_link_up_i) + ); + FDR com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_d_av_o_4_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un36_fc_d_av_o_s_4_3694), + .Q(trn_rfc_npd_av_5061[4]), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_d_av_o_5_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un36_fc_d_av_o_s_5_3696), + .Q(trn_rfc_npd_av_5061[5]), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_d_av_o_6_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un36_fc_d_av_o_s_6_3698), + .Q(trn_rfc_npd_av_5061[6]), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_d_av_o_7_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un36_fc_d_av_o_s_7_3700), + .Q(trn_rfc_npd_av_5061[7]), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_d_av_o_8_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un36_fc_d_av_o_s_8_3702), + .Q(trn_rfc_npd_av_5061[8]), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_d_av_o_9_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un36_fc_d_av_o_s_9_3704), + .Q(trn_rfc_npd_av_5061[9]), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_d_av_o_10_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un36_fc_d_av_o_s_10_3706), + .Q(trn_rfc_npd_av_5061[10]), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_d_av_o_11_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un36_fc_d_av_o_s_11_3708), + .Q(trn_rfc_npd_av_5061[11]), + .R(plm_link_up_i) + ); + FDRE com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_h_alo_0_ ( + .CE(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_gnt), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_lnk_tfc_header[0]), + .Q(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_h_alo[0]), + .R(plm_link_up_i) + ); + FDRE com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_h_alo_1_ ( + .CE(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_gnt), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_lnk_tfc_header[1]), + .Q(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_h_alo[1]), + .R(plm_link_up_i) + ); + FDSE com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_h_alo_2_ ( + .CE(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_gnt), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_lnk_tfc_header[2]), + .Q(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_h_alo[2]), + .S(plm_link_up_i) + ); + FDSE com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_h_alo_3_ ( + .CE(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_gnt), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_lnk_tfc_header[3]), + .Q(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_h_alo[3]), + .S(plm_link_up_i) + ); + FDRE com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_h_alo_4_ ( + .CE(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_gnt), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_lnk_tfc_header[4]), + .Q(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_h_alo[4]), + .R(plm_link_up_i) + ); + FDRE com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_h_alo_5_ ( + .CE(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_gnt), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_lnk_tfc_header[5]), + .Q(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_h_alo[5]), + .R(plm_link_up_i) + ); + FDRE com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_h_alo_6_ ( + .CE(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_gnt), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_lnk_tfc_header[6]), + .Q(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_h_alo[6]), + .R(plm_link_up_i) + ); + FDRE com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_h_alo_7_ ( + .CE(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_gnt), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_lnk_tfc_header[7]), + .Q(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_h_alo[7]), + .R(plm_link_up_i) + ); + FDRE com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_d_alo_0_ ( + .CE(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_gnt), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_lnk_tfc_data[0]), + .Q(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_d_alo[0]), + .R(plm_link_up_i) + ); + FDRE com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_d_alo_1_ ( + .CE(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_gnt), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_lnk_tfc_data[1]), + .Q(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_d_alo[1]), + .R(plm_link_up_i) + ); + FDSE com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_d_alo_2_ ( + .CE(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_gnt), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_lnk_tfc_data[2]), + .Q(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_d_alo[2]), + .S(plm_link_up_i) + ); + FDSE com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_d_alo_3_ ( + .CE(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_gnt), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_lnk_tfc_data[3]), + .Q(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_d_alo[3]), + .S(plm_link_up_i) + ); + FDRE com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_d_alo_4_ ( + .CE(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_gnt), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_lnk_tfc_data[4]), + .Q(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_d_alo[4]), + .R(plm_link_up_i) + ); + FDRE com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_d_alo_5_ ( + .CE(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_gnt), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_lnk_tfc_data[5]), + .Q(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_d_alo[5]), + .R(plm_link_up_i) + ); + FDRE com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_d_alo_6_ ( + .CE(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_gnt), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_lnk_tfc_data[6]), + .Q(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_d_alo[6]), + .R(plm_link_up_i) + ); + FDRE com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_d_alo_7_ ( + .CE(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_gnt), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_lnk_tfc_data[7]), + .Q(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_d_alo[7]), + .R(plm_link_up_i) + ); + FDRE com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_d_alo_8_ ( + .CE(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_gnt), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_lnk_tfc_data[8]), + .Q(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_d_alo[8]), + .R(plm_link_up_i) + ); + FDRE com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_d_alo_9_ ( + .CE(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_gnt), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_lnk_tfc_data[9]), + .Q(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_d_alo[9]), + .R(plm_link_up_i) + ); + FDRE com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_d_alo_10_ ( + .CE(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_gnt), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_lnk_tfc_data[10]), + .Q(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_d_alo[10]), + .R(plm_link_up_i) + ); + FDRE com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_d_alo_11_ ( + .CE(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_gnt), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_lnk_tfc_data[11]), + .Q(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_d_alo[11]), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_free_q2 ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_free_q_3630), + .Q(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_free_q2_3731), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_req_h_o_0_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_h_o_0[0]), + .Q(com_tlm_u_tlm_rx_fc_req_nph[0]), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_req_h_o_1_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_h_o_0[1]), + .Q(com_tlm_u_tlm_rx_fc_req_nph[1]), + .R(plm_link_up_i) + ); + FDS com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_req_h_o_2_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_h_o_0[2]), + .Q(com_tlm_u_tlm_rx_fc_req_nph[2]), + .S(plm_link_up_i) + ); + FDS com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_req_h_o_3_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_h_o_0[3]), + .Q(com_tlm_u_tlm_rx_fc_req_nph[3]), + .S(plm_link_up_i) + ); + FDR com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_req_h_o_4_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_h_o_0[4]), + .Q(com_tlm_u_tlm_rx_fc_req_nph[4]), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_req_h_o_5_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_h_o_0[5]), + .Q(com_tlm_u_tlm_rx_fc_req_nph[5]), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_req_h_o_6_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_h_o_0[6]), + .Q(com_tlm_u_tlm_rx_fc_req_nph[6]), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_req_h_o_7_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_h_o_0[7]), + .Q(com_tlm_u_tlm_rx_fc_req_nph[7]), + .R(plm_link_up_i) + ); + FDRSE com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_free_hold ( + .CE(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_send_state_0__3792), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_GND_3729), + .Q(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_free_hold_3732), + .R(plm_link_up_i), + .S(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_free_hold34) + ); + FDR com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_free_q ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_free_q_8), + .Q(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_free_q_3630), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_free_h ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_free_h_8), + .Q(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_free_h_3631), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_free_d ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_free_d_8), + .Q(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_free_d_3640), + .R(plm_link_up_i) + ); + MUXCY_L com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_h_o_cry_0 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_free_h_3631), + .DI(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_N_41750_i), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_h_o_cry_0_3632), + .S(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_h_o_axb_0_3742) + ); + XORCY com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_h_o_s_0 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_free_h_3631), + .LI(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_h_o_axb_0_3742), + .O(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_h_o_0[0]) + ); + MUXCY_L com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_h_o_cry_1 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_h_o_cry_0_3632), + .DI(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_GND_3729), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_h_o_cry_1_3633), + .S(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_h_o_axb_1_3741) + ); + XORCY com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_h_o_s_1 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_h_o_cry_0_3632), + .LI(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_h_o_axb_1_3741), + .O(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_h_o_0[1]) + ); + MUXCY_L com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_h_o_cry_2 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_h_o_cry_1_3633), + .DI(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_GND_3729), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_h_o_cry_2_3634), + .S(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_h_o_axb_2_3740) + ); + XORCY com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_h_o_s_2 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_h_o_cry_1_3633), + .LI(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_h_o_axb_2_3740), + .O(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_h_o_0[2]) + ); + MUXCY_L com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_h_o_cry_3 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_h_o_cry_2_3634), + .DI(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_GND_3729), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_h_o_cry_3_3635), + .S(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_h_o_axb_3_3739) + ); + XORCY com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_h_o_s_3 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_h_o_cry_2_3634), + .LI(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_h_o_axb_3_3739), + .O(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_h_o_0[3]) + ); + MUXCY_L com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_h_o_cry_4 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_h_o_cry_3_3635), + .DI(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_GND_3729), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_h_o_cry_4_3636), + .S(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_h_o_axb_4_3738) + ); + XORCY com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_h_o_s_4 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_h_o_cry_3_3635), + .LI(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_h_o_axb_4_3738), + .O(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_h_o_0[4]) + ); + MUXCY_L com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_h_o_cry_5 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_h_o_cry_4_3636), + .DI(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_GND_3729), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_h_o_cry_5_3637), + .S(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_h_o_axb_5_3737) + ); + XORCY com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_h_o_s_5 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_h_o_cry_4_3636), + .LI(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_h_o_axb_5_3737), + .O(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_h_o_0[5]) + ); + MUXCY_L com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_h_o_cry_6 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_h_o_cry_5_3637), + .DI(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_GND_3729), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_h_o_cry_6_3638), + .S(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_h_o_axb_6_3736) + ); + XORCY com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_h_o_s_6 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_h_o_cry_5_3637), + .LI(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_h_o_axb_6_3736), + .O(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_h_o_0[6]) + ); + XORCY com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_h_o_s_7 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_h_o_cry_6_3638), + .LI(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_h_o_axb_7_3735), + .O(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_h_o_0[7]) + ); + MULT_AND com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_d_o_cry_0 ( + .I0(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_N_41750_i), + .I1(com_tlm_u_tlm_rx_fc_use_data[0]), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_d_o_cry_0_0_3639) + ); + MUXCY_L com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_d_o_cry_0_0 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_free_d_3640), + .DI(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_d_o_cry_0_0_3639), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_d_o_cry_0_3642), + .S(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_d_o_axb_0_3776) + ); + XORCY com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_d_o_s_0 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_free_d_3640), + .LI(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_d_o_axb_0_3776), + .O(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_d_o_0[0]) + ); + MULT_AND com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_d_o_cry_1 ( + .I0(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_N_41750_i), + .I1(com_tlm_u_tlm_rx_fc_use_data[1]), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_d_o_cry_1_0_3641) + ); + MUXCY_L com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_d_o_cry_1_0 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_d_o_cry_0_3642), + .DI(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_d_o_cry_1_0_3641), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_d_o_cry_1_3644), + .S(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_d_o_axb_1_3775) + ); + XORCY com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_d_o_s_1 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_d_o_cry_0_3642), + .LI(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_d_o_axb_1_3775), + .O(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_d_o_0[1]) + ); + MULT_AND com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_d_o_cry_2 ( + .I0(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_N_41750_i), + .I1(com_tlm_u_tlm_rx_fc_use_data[2]), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_d_o_cry_2_0_3643) + ); + MUXCY_L com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_d_o_cry_2_0 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_d_o_cry_1_3644), + .DI(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_d_o_cry_2_0_3643), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_d_o_cry_2_3646), + .S(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_d_o_axb_2_3774) + ); + XORCY com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_d_o_s_2 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_d_o_cry_1_3644), + .LI(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_d_o_axb_2_3774), + .O(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_d_o_0[2]) + ); + MULT_AND com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_d_o_cry_3 ( + .I0(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_N_41750_i), + .I1(com_tlm_u_tlm_rx_fc_use_data[3]), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_d_o_cry_3_0_3645) + ); + MUXCY_L com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_d_o_cry_3_0 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_d_o_cry_2_3646), + .DI(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_d_o_cry_3_0_3645), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_d_o_cry_3_3648), + .S(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_d_o_axb_3_3773) + ); + XORCY com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_d_o_s_3 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_d_o_cry_2_3646), + .LI(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_d_o_axb_3_3773), + .O(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_d_o_0[3]) + ); + MULT_AND com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_d_o_cry_4 ( + .I0(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_N_41750_i), + .I1(com_tlm_u_tlm_rx_fc_use_data[4]), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_d_o_cry_4_0_3647) + ); + MUXCY_L com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_d_o_cry_4_0 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_d_o_cry_3_3648), + .DI(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_d_o_cry_4_0_3647), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_d_o_cry_4_3650), + .S(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_d_o_axb_4_3772) + ); + XORCY com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_d_o_s_4 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_d_o_cry_3_3648), + .LI(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_d_o_axb_4_3772), + .O(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_d_o_0[4]) + ); + MULT_AND com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_d_o_cry_5 ( + .I0(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_N_41750_i), + .I1(com_tlm_u_tlm_rx_fc_use_data[5]), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_d_o_cry_5_0_3649) + ); + MUXCY_L com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_d_o_cry_5_0 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_d_o_cry_4_3650), + .DI(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_d_o_cry_5_0_3649), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_d_o_cry_5_3651), + .S(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_d_o_axb_5_3771) + ); + XORCY com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_d_o_s_5 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_d_o_cry_4_3650), + .LI(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_d_o_axb_5_3771), + .O(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_d_o_0[5]) + ); + MUXCY_L com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_d_o_cry_6 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_d_o_cry_5_3651), + .DI(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_GND_3729), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_d_o_cry_6_3652), + .S(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_d_o_axb_6_3770) + ); + XORCY com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_d_o_s_6 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_d_o_cry_5_3651), + .LI(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_d_o_axb_6_3770), + .O(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_d_o_0[6]) + ); + MUXCY_L com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_d_o_cry_7 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_d_o_cry_6_3652), + .DI(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_GND_3729), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_d_o_cry_7_3653), + .S(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_d_o_axb_7_3769) + ); + XORCY com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_d_o_s_7 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_d_o_cry_6_3652), + .LI(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_d_o_axb_7_3769), + .O(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_d_o_0[7]) + ); + MUXCY_L com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_d_o_cry_8 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_d_o_cry_7_3653), + .DI(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_GND_3729), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_d_o_cry_8_3654), + .S(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_d_o_axb_8_3768) + ); + XORCY com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_d_o_s_8 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_d_o_cry_7_3653), + .LI(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_d_o_axb_8_3768), + .O(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_d_o_0[8]) + ); + MUXCY_L com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_d_o_cry_9 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_d_o_cry_8_3654), + .DI(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_GND_3729), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_d_o_cry_9_3655), + .S(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_d_o_axb_9_3767) + ); + XORCY com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_d_o_s_9 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_d_o_cry_8_3654), + .LI(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_d_o_axb_9_3767), + .O(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_d_o_0[9]) + ); + MUXCY_L com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_d_o_cry_10 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_d_o_cry_9_3655), + .DI(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_GND_3729), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_d_o_cry_10_3656), + .S(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_d_o_axb_10_3766) + ); + XORCY com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_d_o_s_10 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_d_o_cry_9_3655), + .LI(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_d_o_axb_10_3766), + .O(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_d_o_0[10]) + ); + XORCY com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_d_o_s_11 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_d_o_cry_10_3656), + .LI(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_d_o_axb_11_3765), + .O(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_d_o_0[11]) + ); + MULT_AND com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un1_fc_d_con_1_cry_0 ( + .I0(com_tlm_u_tlm_rx_fc_use_np), + .I1(com_tlm_u_tlm_rx_fc_use_data[0]), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un1_fc_d_con_1_cry_0_0_3657) + ); + MUXCY_L com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un1_fc_d_con_1_cry_0_0 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_GND_3729), + .DI(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un1_fc_d_con_1_cry_0_0_3657), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un1_fc_d_con_1_cry_0_3659), + .S(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un1_fc_d_con_1_axb_0_3730) + ); + MULT_AND com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un1_fc_d_con_1_cry_1 ( + .I0(com_tlm_u_tlm_rx_fc_use_np), + .I1(com_tlm_u_tlm_rx_fc_use_data[1]), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un1_fc_d_con_1_cry_1_0_3658) + ); + MUXCY_L com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un1_fc_d_con_1_cry_1_0 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un1_fc_d_con_1_cry_0_3659), + .DI(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un1_fc_d_con_1_cry_1_0_3658), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un1_fc_d_con_1_cry_1_3661), + .S(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un1_fc_d_con_1_axb_1_3787) + ); + XORCY com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un1_fc_d_con_1_s_1 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un1_fc_d_con_1_cry_0_3659), + .LI(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un1_fc_d_con_1_axb_1_3787), + .O(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un1_fc_d_con_1_s_1_0) + ); + MULT_AND com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un1_fc_d_con_1_cry_2 ( + .I0(com_tlm_u_tlm_rx_fc_use_np), + .I1(com_tlm_u_tlm_rx_fc_use_data[2]), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un1_fc_d_con_1_cry_2_0_3660) + ); + MUXCY_L com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un1_fc_d_con_1_cry_2_0 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un1_fc_d_con_1_cry_1_3661), + .DI(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un1_fc_d_con_1_cry_2_0_3660), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un1_fc_d_con_1_cry_2_3663), + .S(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un1_fc_d_con_1_axb_2_3786) + ); + XORCY com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un1_fc_d_con_1_s_2 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un1_fc_d_con_1_cry_1_3661), + .LI(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un1_fc_d_con_1_axb_2_3786), + .O(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un1_fc_d_con_1_s_2_0) + ); + MULT_AND com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un1_fc_d_con_1_cry_3 ( + .I0(com_tlm_u_tlm_rx_fc_use_np), + .I1(com_tlm_u_tlm_rx_fc_use_data[3]), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un1_fc_d_con_1_cry_3_0_3662) + ); + MUXCY_L com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un1_fc_d_con_1_cry_3_0 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un1_fc_d_con_1_cry_2_3663), + .DI(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un1_fc_d_con_1_cry_3_0_3662), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un1_fc_d_con_1_cry_3_3665), + .S(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un1_fc_d_con_1_axb_3_3785) + ); + XORCY com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un1_fc_d_con_1_s_3 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un1_fc_d_con_1_cry_2_3663), + .LI(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un1_fc_d_con_1_axb_3_3785), + .O(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un1_fc_d_con_1_s_3_0) + ); + MULT_AND com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un1_fc_d_con_1_cry_4 ( + .I0(com_tlm_u_tlm_rx_fc_use_np), + .I1(com_tlm_u_tlm_rx_fc_use_data[4]), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un1_fc_d_con_1_cry_4_0_3664) + ); + MUXCY_L com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un1_fc_d_con_1_cry_4_0 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un1_fc_d_con_1_cry_3_3665), + .DI(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un1_fc_d_con_1_cry_4_0_3664), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un1_fc_d_con_1_cry_4_3667), + .S(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un1_fc_d_con_1_axb_4_3784) + ); + XORCY com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un1_fc_d_con_1_s_4 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un1_fc_d_con_1_cry_3_3665), + .LI(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un1_fc_d_con_1_axb_4_3784), + .O(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un1_fc_d_con_1_s_4_0) + ); + MULT_AND com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un1_fc_d_con_1_cry_5 ( + .I0(com_tlm_u_tlm_rx_fc_use_np), + .I1(com_tlm_u_tlm_rx_fc_use_data[5]), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un1_fc_d_con_1_cry_5_0_3666) + ); + MUXCY_L com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un1_fc_d_con_1_cry_5_0 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un1_fc_d_con_1_cry_4_3667), + .DI(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un1_fc_d_con_1_cry_5_0_3666), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un1_fc_d_con_1_cry_5_3668), + .S(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un1_fc_d_con_1_axb_5_3783) + ); + XORCY com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un1_fc_d_con_1_s_5 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un1_fc_d_con_1_cry_4_3667), + .LI(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un1_fc_d_con_1_axb_5_3783), + .O(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un1_fc_d_con_1_s_5_0) + ); + MUXCY_L com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un1_fc_d_con_1_cry_6 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un1_fc_d_con_1_cry_5_3668), + .DI(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_GND_3729), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un1_fc_d_con_1_cry_6_3669), + .S(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un1_fc_d_con_1_axb_6_3782) + ); + XORCY com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un1_fc_d_con_1_s_6 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un1_fc_d_con_1_cry_5_3668), + .LI(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un1_fc_d_con_1_axb_6_3782), + .O(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un1_fc_d_con_1_s_6_0) + ); + MUXCY_L com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un1_fc_d_con_1_cry_7 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un1_fc_d_con_1_cry_6_3669), + .DI(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_GND_3729), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un1_fc_d_con_1_cry_7_3670), + .S(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un1_fc_d_con_1_axb_7_3781) + ); + XORCY com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un1_fc_d_con_1_s_7 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un1_fc_d_con_1_cry_6_3669), + .LI(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un1_fc_d_con_1_axb_7_3781), + .O(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un1_fc_d_con_1_s_7_0) + ); + MUXCY_L com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un1_fc_d_con_1_cry_8 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un1_fc_d_con_1_cry_7_3670), + .DI(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_GND_3729), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un1_fc_d_con_1_cry_8_3671), + .S(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un1_fc_d_con_1_axb_8_3780) + ); + XORCY com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un1_fc_d_con_1_s_8 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un1_fc_d_con_1_cry_7_3670), + .LI(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un1_fc_d_con_1_axb_8_3780), + .O(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un1_fc_d_con_1_s_8_0) + ); + MUXCY_L com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un1_fc_d_con_1_cry_9 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un1_fc_d_con_1_cry_8_3671), + .DI(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_GND_3729), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un1_fc_d_con_1_cry_9_3672), + .S(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un1_fc_d_con_1_axb_9_3779) + ); + XORCY com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un1_fc_d_con_1_s_9 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un1_fc_d_con_1_cry_8_3671), + .LI(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un1_fc_d_con_1_axb_9_3779), + .O(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un1_fc_d_con_1_s_9_0) + ); + MUXCY_L com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un1_fc_d_con_1_cry_10 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un1_fc_d_con_1_cry_9_3672), + .DI(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_GND_3729), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un1_fc_d_con_1_cry_10_3673), + .S(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un1_fc_d_con_1_axb_10_3778) + ); + XORCY com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un1_fc_d_con_1_s_10 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un1_fc_d_con_1_cry_9_3672), + .LI(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un1_fc_d_con_1_axb_10_3778), + .O(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un1_fc_d_con_1_s_10_0) + ); + XORCY com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un1_fc_d_con_1_s_11 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un1_fc_d_con_1_cry_10_3673), + .LI(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un1_fc_d_con_1_axb_11_3777), + .O(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un1_fc_d_con_1_s_11_0) + ); + MUXCY_L com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un35_fc_h_av_o_cry_0 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_VCC_3717), + .DI(com_tlm_u_tlm_rx_fc_req_nph[0]), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un35_fc_h_av_o_cry_0_3675), + .S(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un35_fc_h_av_o_axb_0_3764) + ); + MUXCY_L com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un35_fc_h_av_o_cry_1 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un35_fc_h_av_o_cry_0_3675), + .DI(com_tlm_u_tlm_rx_fc_req_nph[1]), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un35_fc_h_av_o_cry_1_3677), + .S(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un35_fc_h_av_o_axb_1_3762) + ); + XORCY com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un35_fc_h_av_o_s_1 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un35_fc_h_av_o_cry_0_3675), + .LI(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un35_fc_h_av_o_axb_1_3762), + .O(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un35_fc_h_av_o_s_1_3674) + ); + MUXCY_L com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un35_fc_h_av_o_cry_2 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un35_fc_h_av_o_cry_1_3677), + .DI(com_tlm_u_tlm_rx_fc_req_nph[2]), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un35_fc_h_av_o_cry_2_3679), + .S(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un35_fc_h_av_o_axb_2_3761) + ); + XORCY com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un35_fc_h_av_o_s_2 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un35_fc_h_av_o_cry_1_3677), + .LI(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un35_fc_h_av_o_axb_2_3761), + .O(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un35_fc_h_av_o_s_2_3676) + ); + MUXCY_L com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un35_fc_h_av_o_cry_3 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un35_fc_h_av_o_cry_2_3679), + .DI(com_tlm_u_tlm_rx_fc_req_nph[3]), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un35_fc_h_av_o_cry_3_3681), + .S(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un35_fc_h_av_o_axb_3_3760) + ); + XORCY com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un35_fc_h_av_o_s_3 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un35_fc_h_av_o_cry_2_3679), + .LI(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un35_fc_h_av_o_axb_3_3760), + .O(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un35_fc_h_av_o_s_3_3678) + ); + MUXCY_L com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un35_fc_h_av_o_cry_4 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un35_fc_h_av_o_cry_3_3681), + .DI(com_tlm_u_tlm_rx_fc_req_nph[4]), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un35_fc_h_av_o_cry_4_3683), + .S(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un35_fc_h_av_o_axb_4_3759) + ); + XORCY com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un35_fc_h_av_o_s_4 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un35_fc_h_av_o_cry_3_3681), + .LI(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un35_fc_h_av_o_axb_4_3759), + .O(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un35_fc_h_av_o_s_4_3680) + ); + MUXCY_L com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un35_fc_h_av_o_cry_5 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un35_fc_h_av_o_cry_4_3683), + .DI(com_tlm_u_tlm_rx_fc_req_nph[5]), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un35_fc_h_av_o_cry_5_3685), + .S(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un35_fc_h_av_o_axb_5_3758) + ); + XORCY com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un35_fc_h_av_o_s_5 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un35_fc_h_av_o_cry_4_3683), + .LI(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un35_fc_h_av_o_axb_5_3758), + .O(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un35_fc_h_av_o_s_5_3682) + ); + MUXCY_L com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un35_fc_h_av_o_cry_6 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un35_fc_h_av_o_cry_5_3685), + .DI(com_tlm_u_tlm_rx_fc_req_nph[6]), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un35_fc_h_av_o_cry_6_3687), + .S(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un35_fc_h_av_o_axb_6_3757) + ); + XORCY com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un35_fc_h_av_o_s_6 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un35_fc_h_av_o_cry_5_3685), + .LI(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un35_fc_h_av_o_axb_6_3757), + .O(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un35_fc_h_av_o_s_6_3684) + ); + XORCY com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un35_fc_h_av_o_s_7 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un35_fc_h_av_o_cry_6_3687), + .LI(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un35_fc_h_av_o_axb_7_3756), + .O(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un35_fc_h_av_o_s_7_3686) + ); + MUXCY_L com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un36_fc_d_av_o_cry_0 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_VCC_3717), + .DI(com_tlm_u_tlm_rx_fc_req_npd[0]), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un36_fc_d_av_o_cry_0_3689), + .S(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un36_fc_d_av_o_axb_0_3755) + ); + MUXCY_L com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un36_fc_d_av_o_cry_1 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un36_fc_d_av_o_cry_0_3689), + .DI(com_tlm_u_tlm_rx_fc_req_npd[1]), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un36_fc_d_av_o_cry_1_3691), + .S(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un36_fc_d_av_o_axb_1_3753) + ); + XORCY com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un36_fc_d_av_o_s_1 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un36_fc_d_av_o_cry_0_3689), + .LI(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un36_fc_d_av_o_axb_1_3753), + .O(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un36_fc_d_av_o_s_1_3688) + ); + MUXCY_L com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un36_fc_d_av_o_cry_2 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un36_fc_d_av_o_cry_1_3691), + .DI(com_tlm_u_tlm_rx_fc_req_npd[2]), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un36_fc_d_av_o_cry_2_3693), + .S(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un36_fc_d_av_o_axb_2_3752) + ); + XORCY com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un36_fc_d_av_o_s_2 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un36_fc_d_av_o_cry_1_3691), + .LI(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un36_fc_d_av_o_axb_2_3752), + .O(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un36_fc_d_av_o_s_2_3690) + ); + MUXCY_L com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un36_fc_d_av_o_cry_3 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un36_fc_d_av_o_cry_2_3693), + .DI(com_tlm_u_tlm_rx_fc_req_npd[3]), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un36_fc_d_av_o_cry_3_3695), + .S(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un36_fc_d_av_o_axb_3_3751) + ); + XORCY com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un36_fc_d_av_o_s_3 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un36_fc_d_av_o_cry_2_3693), + .LI(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un36_fc_d_av_o_axb_3_3751), + .O(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un36_fc_d_av_o_s_3_3692) + ); + MUXCY_L com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un36_fc_d_av_o_cry_4 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un36_fc_d_av_o_cry_3_3695), + .DI(com_tlm_u_tlm_rx_fc_req_npd[4]), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un36_fc_d_av_o_cry_4_3697), + .S(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un36_fc_d_av_o_axb_4_3750) + ); + XORCY com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un36_fc_d_av_o_s_4 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un36_fc_d_av_o_cry_3_3695), + .LI(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un36_fc_d_av_o_axb_4_3750), + .O(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un36_fc_d_av_o_s_4_3694) + ); + MUXCY_L com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un36_fc_d_av_o_cry_5 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un36_fc_d_av_o_cry_4_3697), + .DI(com_tlm_u_tlm_rx_fc_req_npd[5]), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un36_fc_d_av_o_cry_5_3699), + .S(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un36_fc_d_av_o_axb_5_3749) + ); + XORCY com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un36_fc_d_av_o_s_5 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un36_fc_d_av_o_cry_4_3697), + .LI(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un36_fc_d_av_o_axb_5_3749), + .O(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un36_fc_d_av_o_s_5_3696) + ); + MUXCY_L com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un36_fc_d_av_o_cry_6 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un36_fc_d_av_o_cry_5_3699), + .DI(com_tlm_u_tlm_rx_fc_req_npd[6]), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un36_fc_d_av_o_cry_6_3701), + .S(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un36_fc_d_av_o_axb_6_3748) + ); + XORCY com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un36_fc_d_av_o_s_6 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un36_fc_d_av_o_cry_5_3699), + .LI(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un36_fc_d_av_o_axb_6_3748), + .O(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un36_fc_d_av_o_s_6_3698) + ); + MUXCY_L com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un36_fc_d_av_o_cry_7 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un36_fc_d_av_o_cry_6_3701), + .DI(com_tlm_u_tlm_rx_fc_req_npd[7]), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un36_fc_d_av_o_cry_7_3703), + .S(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un36_fc_d_av_o_axb_7_3747) + ); + XORCY com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un36_fc_d_av_o_s_7 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un36_fc_d_av_o_cry_6_3701), + .LI(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un36_fc_d_av_o_axb_7_3747), + .O(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un36_fc_d_av_o_s_7_3700) + ); + MUXCY_L com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un36_fc_d_av_o_cry_8 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un36_fc_d_av_o_cry_7_3703), + .DI(com_tlm_u_tlm_rx_fc_req_npd[8]), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un36_fc_d_av_o_cry_8_3705), + .S(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un36_fc_d_av_o_axb_8_3746) + ); + XORCY com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un36_fc_d_av_o_s_8 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un36_fc_d_av_o_cry_7_3703), + .LI(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un36_fc_d_av_o_axb_8_3746), + .O(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un36_fc_d_av_o_s_8_3702) + ); + MUXCY_L com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un36_fc_d_av_o_cry_9 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un36_fc_d_av_o_cry_8_3705), + .DI(com_tlm_u_tlm_rx_fc_req_npd[9]), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un36_fc_d_av_o_cry_9_3707), + .S(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un36_fc_d_av_o_axb_9_3745) + ); + XORCY com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un36_fc_d_av_o_s_9 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un36_fc_d_av_o_cry_8_3705), + .LI(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un36_fc_d_av_o_axb_9_3745), + .O(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un36_fc_d_av_o_s_9_3704) + ); + MUXCY_L com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un36_fc_d_av_o_cry_10 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un36_fc_d_av_o_cry_9_3707), + .DI(com_tlm_u_tlm_rx_fc_req_npd[10]), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un36_fc_d_av_o_cry_10_3709), + .S(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un36_fc_d_av_o_axb_10_3744) + ); + XORCY com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un36_fc_d_av_o_s_10 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un36_fc_d_av_o_cry_9_3707), + .LI(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un36_fc_d_av_o_axb_10_3744), + .O(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un36_fc_d_av_o_s_10_3706) + ); + XORCY com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un36_fc_d_av_o_s_11 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un36_fc_d_av_o_cry_10_3709), + .LI(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un36_fc_d_av_o_axb_11_3743), + .O(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un36_fc_d_av_o_s_11_3708) + ); + MUXCY_L com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un5_fc_h_advert_cry_0 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_VCC_3717), + .DI(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_h_alo[0]), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un5_fc_h_advert_cry_0_3710), + .S(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un5_fc_h_advert_axb_0_3812) + ); + MUXCY_L com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un5_fc_h_advert_cry_1 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un5_fc_h_advert_cry_0_3710), + .DI(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_h_alo[1]), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un5_fc_h_advert_cry_1_3711), + .S(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un5_fc_h_advert_axb_1_3811) + ); + MUXCY_L com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un5_fc_h_advert_cry_2 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un5_fc_h_advert_cry_1_3711), + .DI(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_h_alo[2]), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un5_fc_h_advert_cry_2_3712), + .S(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un5_fc_h_advert_axb_2_3810) + ); + MUXCY_L com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un5_fc_h_advert_cry_3 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un5_fc_h_advert_cry_2_3712), + .DI(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_h_alo[3]), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un5_fc_h_advert_cry_3_3713), + .S(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un5_fc_h_advert_axb_3_3809) + ); + MUXCY_L com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un5_fc_h_advert_cry_4 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un5_fc_h_advert_cry_3_3713), + .DI(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_h_alo[4]), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un5_fc_h_advert_cry_4_3714), + .S(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un5_fc_h_advert_axb_4_3808) + ); + MUXCY_L com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un5_fc_h_advert_cry_5 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un5_fc_h_advert_cry_4_3714), + .DI(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_h_alo[5]), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un5_fc_h_advert_cry_5_3715), + .S(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un5_fc_h_advert_axb_5_3807) + ); + MUXCY_L com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un5_fc_h_advert_cry_6 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un5_fc_h_advert_cry_5_3715), + .DI(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_h_alo[6]), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un5_fc_h_advert_cry_6_3716), + .S(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un5_fc_h_advert_axb_6_3806) + ); + XORCY com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un5_fc_h_advert_s_7 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un5_fc_h_advert_cry_6_3716), + .LI(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un5_fc_h_advert_axb_7_3734), + .O(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un5_fc_h_advert_s_7_3794) + ); + MUXCY_L com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un5_fc_d_advert_cry_0 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_VCC_3717), + .DI(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_d_alo[0]), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un5_fc_d_advert_cry_0_3718), + .S(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un5_fc_d_advert_axb_0_3805) + ); + MUXCY_L com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un5_fc_d_advert_cry_1 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un5_fc_d_advert_cry_0_3718), + .DI(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_d_alo[1]), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un5_fc_d_advert_cry_1_3719), + .S(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un5_fc_d_advert_axb_1_3804) + ); + MUXCY_L com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un5_fc_d_advert_cry_2 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un5_fc_d_advert_cry_1_3719), + .DI(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_d_alo[2]), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un5_fc_d_advert_cry_2_3720), + .S(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un5_fc_d_advert_axb_2_3803) + ); + MUXCY_L com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un5_fc_d_advert_cry_3 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un5_fc_d_advert_cry_2_3720), + .DI(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_d_alo[3]), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un5_fc_d_advert_cry_3_3721), + .S(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un5_fc_d_advert_axb_3_3802) + ); + MUXCY_L com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un5_fc_d_advert_cry_4 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un5_fc_d_advert_cry_3_3721), + .DI(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_d_alo[4]), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un5_fc_d_advert_cry_4_3722), + .S(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un5_fc_d_advert_axb_4_3801) + ); + MUXCY_L com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un5_fc_d_advert_cry_5 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un5_fc_d_advert_cry_4_3722), + .DI(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_d_alo[5]), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un5_fc_d_advert_cry_5_3723), + .S(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un5_fc_d_advert_axb_5_3800) + ); + MUXCY_L com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un5_fc_d_advert_cry_6 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un5_fc_d_advert_cry_5_3723), + .DI(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_d_alo[6]), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un5_fc_d_advert_cry_6_3724), + .S(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un5_fc_d_advert_axb_6_3799) + ); + MUXCY_L com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un5_fc_d_advert_cry_7 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un5_fc_d_advert_cry_6_3724), + .DI(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_d_alo[7]), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un5_fc_d_advert_cry_7_3725), + .S(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un5_fc_d_advert_axb_7_3798) + ); + MUXCY_L com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un5_fc_d_advert_cry_8 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un5_fc_d_advert_cry_7_3725), + .DI(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_d_alo[8]), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un5_fc_d_advert_cry_8_3726), + .S(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un5_fc_d_advert_axb_8_3797) + ); + MUXCY_L com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un5_fc_d_advert_cry_9 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un5_fc_d_advert_cry_8_3726), + .DI(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_d_alo[9]), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un5_fc_d_advert_cry_9_3727), + .S(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un5_fc_d_advert_axb_9_3796) + ); + MUXCY_L com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un5_fc_d_advert_cry_10 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un5_fc_d_advert_cry_9_3727), + .DI(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_d_alo[10]), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un5_fc_d_advert_cry_10_3728), + .S(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un5_fc_d_advert_axb_10_3795) + ); + XORCY com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un5_fc_d_advert_s_11 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un5_fc_d_advert_cry_10_3728), + .LI(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un5_fc_d_advert_axb_11_3733), + .O(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un5_fc_d_advert_s_11_3793) + ); + FDRE com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_h_con_0_ ( + .CE(com_tlm_u_tlm_rx_fc_use_np), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_h_con_s[0]), + .Q(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_h_con[0]), + .R(plm_link_up_i) + ); + MUXCY_L com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_h_con_cry_1_ ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_h_con[0]), + .DI(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_GND_3729), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_h_con_cry[1]), + .S(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_h_con_qxu[1]) + ); + XORCY com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_h_con_s_1_ ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_h_con[0]), + .LI(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_h_con_qxu[1]), + .O(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_h_con_s[1]) + ); + FDRE com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_h_con_1_ ( + .CE(com_tlm_u_tlm_rx_fc_use_np), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_h_con_s[1]), + .Q(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_h_con[1]), + .R(plm_link_up_i) + ); + MUXCY_L com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_h_con_cry_2_ ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_h_con_cry[1]), + .DI(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_GND_3729), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_h_con_cry[2]), + .S(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_h_con_qxu[2]) + ); + XORCY com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_h_con_s_2_ ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_h_con_cry[1]), + .LI(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_h_con_qxu[2]), + .O(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_h_con_s[2]) + ); + FDRE com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_h_con_2_ ( + .CE(com_tlm_u_tlm_rx_fc_use_np), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_h_con_s[2]), + .Q(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_h_con[2]), + .R(plm_link_up_i) + ); + MUXCY_L com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_h_con_cry_3_ ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_h_con_cry[2]), + .DI(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_GND_3729), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_h_con_cry[3]), + .S(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_h_con_qxu[3]) + ); + XORCY com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_h_con_s_3_ ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_h_con_cry[2]), + .LI(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_h_con_qxu[3]), + .O(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_h_con_s[3]) + ); + FDRE com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_h_con_3_ ( + .CE(com_tlm_u_tlm_rx_fc_use_np), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_h_con_s[3]), + .Q(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_h_con[3]), + .R(plm_link_up_i) + ); + MUXCY_L com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_h_con_cry_4_ ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_h_con_cry[3]), + .DI(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_GND_3729), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_h_con_cry[4]), + .S(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_h_con_qxu[4]) + ); + XORCY com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_h_con_s_4_ ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_h_con_cry[3]), + .LI(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_h_con_qxu[4]), + .O(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_h_con_s[4]) + ); + FDRE com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_h_con_4_ ( + .CE(com_tlm_u_tlm_rx_fc_use_np), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_h_con_s[4]), + .Q(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_h_con[4]), + .R(plm_link_up_i) + ); + MUXCY_L com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_h_con_cry_5_ ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_h_con_cry[4]), + .DI(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_GND_3729), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_h_con_cry[5]), + .S(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_h_con_qxu[5]) + ); + XORCY com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_h_con_s_5_ ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_h_con_cry[4]), + .LI(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_h_con_qxu[5]), + .O(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_h_con_s[5]) + ); + FDRE com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_h_con_5_ ( + .CE(com_tlm_u_tlm_rx_fc_use_np), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_h_con_s[5]), + .Q(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_h_con[5]), + .R(plm_link_up_i) + ); + MUXCY_L com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_h_con_cry_6_ ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_h_con_cry[5]), + .DI(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_GND_3729), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_h_con_cry[6]), + .S(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_h_con_qxu[6]) + ); + XORCY com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_h_con_s_6_ ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_h_con_cry[5]), + .LI(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_h_con_qxu[6]), + .O(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_h_con_s[6]) + ); + FDRE com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_h_con_6_ ( + .CE(com_tlm_u_tlm_rx_fc_use_np), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_h_con_s[6]), + .Q(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_h_con[6]), + .R(plm_link_up_i) + ); + XORCY com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_h_con_s_7_ ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_h_con_cry[6]), + .LI(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_h_con_qxu[7]), + .O(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_h_con_s[7]) + ); + FDRE com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_h_con_7_ ( + .CE(com_tlm_u_tlm_rx_fc_use_np), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_h_con_s[7]), + .Q(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_h_con[7]), + .R(plm_link_up_i) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_unuse_direct_N_14449_i_0_o4.INIT = 4'h8; + LUT2 com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_unuse_direct_N_14449_i_0_o4 ( + .I0(com_tlm_u_tlm_rx_fc_unuse), + .I1(com_tlm_u_tlm_rx_fc_use_np), + .O(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_N_41750_i) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_free_hold34_0_a2_0_a2.INIT = 4'h2; + LUT2 com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_free_hold34_0_a2_0_a2 ( + .I0(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_free_q2_3731), + .I1(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_send_state_0__3792), + .O(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_free_hold34) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_send_state_28_0_i_0_a2_2_.INIT = 4'h8; + LUT2 com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_send_state_28_0_i_0_a2_2_ ( + .I0(com_tlm_u_tlm_rx_fc_req_np_dst_rdy), + .I1(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_req_np_src_rdy), + .O(com_tlm_u_tlm_rx_fc_send_state_0_sqmuxa_0) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un35_fc_h_av_o_axb_0.INIT = 4'h9; + LUT2 com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un35_fc_h_av_o_axb_0 ( + .I0(com_tlm_u_tlm_rx_fc_req_nph[0]), + .I1(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_h_con[0]), + .O(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un35_fc_h_av_o_axb_0_3764) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un36_fc_d_av_o_axb_0.INIT = 4'h9; + LUT2 com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un36_fc_d_av_o_axb_0 ( + .I0(com_tlm_u_tlm_rx_fc_req_npd[0]), + .I1(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_d_con[0]), + .O(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un36_fc_d_av_o_axb_0_3755) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un1_fc_d_con_1_axb_0.INIT = 8'h78; + LUT3 com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un1_fc_d_con_1_axb_0 ( + .I0(com_tlm_u_tlm_rx_fc_use_data[0]), + .I1(com_tlm_u_tlm_rx_fc_use_np), + .I2(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_d_con[0]), + .O(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un1_fc_d_con_1_axb_0_3730) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_send_state_28_0_i_0_o4_1_.INIT = 16'h0001; + LUT4 com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_send_state_28_0_i_0_o4_1_ ( + .I0(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_N_41750_i), + .I1(com_tlm_u_tlm_rx_vc0_flow_ctrl_lat_timer[9]), + .I2(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_free_hold_3732), + .I3(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_free_q2_3731), + .O(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_N_42049_i) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_gnt_0_a2_0_a2_0_a2_1.INIT = 16'h0200; + LUT4 com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_gnt_0_a2_0_a2_0_a2_1 ( + .I0(com_un1_lnk_tfc_dst_rdy_i_0_o2_i_a2), + .I1(com_lnk_tfc_type[1]), + .I2(com_lnk_tfc_type[2]), + .I3(com_lnk_tfc_type[3]), + .O(com_tlm_u_tlm_rx_vc0_flow_ctrl_fc_gnt_3) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_gnt_0_a2_0_a2_0_a2.INIT = 4'h8; + LUT2 com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_gnt_0_a2_0_a2_0_a2 ( + .I0(com_lnk_tfc_type[0]), + .I1(com_tlm_u_tlm_rx_vc0_flow_ctrl_fc_gnt_3), + .O(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_gnt) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un5_fc_d_advert_axb_11.INIT = 4'h9; + LUT2_L com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un5_fc_d_advert_axb_11 ( + .I0(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_d_alo[11]), + .I1(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_d_con[11]), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un5_fc_d_advert_axb_11_3733) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un5_fc_h_advert_axb_7.INIT = 4'h9; + LUT2_L com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un5_fc_h_advert_axb_7 ( + .I0(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_h_alo[7]), + .I1(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_h_con[7]), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un5_fc_h_advert_axb_7_3734) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_free_d_8_0_a2.INIT = 4'h8; + LUT2_L com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_free_d_8_0_a2 ( + .I0(com_tlm_u_tlm_rx_vc0_fc_free_1data), + .I1(com_tlm_u_tlm_rx_vc0_fc_free_np), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_free_d_8) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_free_h_8_0_a2.INIT = 4'h8; + LUT2_L com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_free_h_8_0_a2 ( + .I0(com_tlm_u_tlm_rx_vc0_fc_free_1header), + .I1(com_tlm_u_tlm_rx_vc0_fc_free_np), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_free_h_8) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_free_q_8_0_a2.INIT = 4'h8; + LUT2_L com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_free_q_8_0_a2 ( + .I0(com_tlm_u_tlm_rx_vc0_fc_free_eof), + .I1(com_tlm_u_tlm_rx_vc0_fc_free_np), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_free_q_8) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_h_o_axb_7.INIT = 4'h2; + LUT1_L com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_h_o_axb_7 ( + .I0(com_tlm_u_tlm_rx_fc_req_nph[7]), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_h_o_axb_7_3735) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_h_o_axb_6.INIT = 4'h2; + LUT1_L com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_h_o_axb_6 ( + .I0(com_tlm_u_tlm_rx_fc_req_nph[6]), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_h_o_axb_6_3736) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_h_o_axb_5.INIT = 4'h2; + LUT1_L com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_h_o_axb_5 ( + .I0(com_tlm_u_tlm_rx_fc_req_nph[5]), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_h_o_axb_5_3737) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_h_o_axb_4.INIT = 4'h2; + LUT1_L com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_h_o_axb_4 ( + .I0(com_tlm_u_tlm_rx_fc_req_nph[4]), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_h_o_axb_4_3738) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_h_o_axb_3.INIT = 4'h2; + LUT1_L com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_h_o_axb_3 ( + .I0(com_tlm_u_tlm_rx_fc_req_nph[3]), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_h_o_axb_3_3739) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_h_o_axb_2.INIT = 4'h2; + LUT1_L com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_h_o_axb_2 ( + .I0(com_tlm_u_tlm_rx_fc_req_nph[2]), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_h_o_axb_2_3740) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_h_o_axb_1.INIT = 4'h2; + LUT1_L com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_h_o_axb_1 ( + .I0(com_tlm_u_tlm_rx_fc_req_nph[1]), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_h_o_axb_1_3741) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_h_o_axb_0.INIT = 4'h6; + LUT2_L com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_h_o_axb_0 ( + .I0(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_N_41750_i), + .I1(com_tlm_u_tlm_rx_fc_req_nph[0]), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_h_o_axb_0_3742) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un36_fc_d_av_o_axb_11.INIT = 4'h9; + LUT2_L com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un36_fc_d_av_o_axb_11 ( + .I0(com_tlm_u_tlm_rx_fc_req_npd[11]), + .I1(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_d_con[11]), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un36_fc_d_av_o_axb_11_3743) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un36_fc_d_av_o_axb_10.INIT = 4'h9; + LUT2_L com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un36_fc_d_av_o_axb_10 ( + .I0(com_tlm_u_tlm_rx_fc_req_npd[10]), + .I1(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_d_con[10]), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un36_fc_d_av_o_axb_10_3744) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un36_fc_d_av_o_axb_9.INIT = 4'h9; + LUT2_L com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un36_fc_d_av_o_axb_9 ( + .I0(com_tlm_u_tlm_rx_fc_req_npd[9]), + .I1(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_d_con[9]), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un36_fc_d_av_o_axb_9_3745) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un36_fc_d_av_o_axb_8.INIT = 4'h9; + LUT2_L com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un36_fc_d_av_o_axb_8 ( + .I0(com_tlm_u_tlm_rx_fc_req_npd[8]), + .I1(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_d_con[8]), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un36_fc_d_av_o_axb_8_3746) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un36_fc_d_av_o_axb_7.INIT = 4'h9; + LUT2_L com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un36_fc_d_av_o_axb_7 ( + .I0(com_tlm_u_tlm_rx_fc_req_npd[7]), + .I1(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_d_con[7]), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un36_fc_d_av_o_axb_7_3747) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un36_fc_d_av_o_axb_6.INIT = 4'h9; + LUT2_L com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un36_fc_d_av_o_axb_6 ( + .I0(com_tlm_u_tlm_rx_fc_req_npd[6]), + .I1(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_d_con[6]), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un36_fc_d_av_o_axb_6_3748) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un36_fc_d_av_o_axb_5.INIT = 4'h9; + LUT2_L com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un36_fc_d_av_o_axb_5 ( + .I0(com_tlm_u_tlm_rx_fc_req_npd[5]), + .I1(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_d_con[5]), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un36_fc_d_av_o_axb_5_3749) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un36_fc_d_av_o_axb_4.INIT = 4'h9; + LUT2_L com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un36_fc_d_av_o_axb_4 ( + .I0(com_tlm_u_tlm_rx_fc_req_npd[4]), + .I1(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_d_con[4]), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un36_fc_d_av_o_axb_4_3750) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un36_fc_d_av_o_axb_3.INIT = 4'h9; + LUT2_L com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un36_fc_d_av_o_axb_3 ( + .I0(com_tlm_u_tlm_rx_fc_req_npd[3]), + .I1(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_d_con[3]), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un36_fc_d_av_o_axb_3_3751) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un36_fc_d_av_o_axb_2.INIT = 4'h9; + LUT2_L com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un36_fc_d_av_o_axb_2 ( + .I0(com_tlm_u_tlm_rx_fc_req_npd[2]), + .I1(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_d_con[2]), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un36_fc_d_av_o_axb_2_3752) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un36_fc_d_av_o_axb_1.INIT = 4'h9; + LUT2_L com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un36_fc_d_av_o_axb_1 ( + .I0(com_tlm_u_tlm_rx_fc_req_npd[1]), + .I1(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_d_con[1]), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un36_fc_d_av_o_axb_1_3753) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un36_fc_d_av_o_axb_0_i.INIT = 4'h1; + LUT1_L com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un36_fc_d_av_o_axb_0_i ( + .I0(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un36_fc_d_av_o_axb_0_3755), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un36_fc_d_av_o_axb_0_i_3754) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un35_fc_h_av_o_axb_7.INIT = 4'h9; + LUT2_L com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un35_fc_h_av_o_axb_7 ( + .I0(com_tlm_u_tlm_rx_fc_req_nph[7]), + .I1(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_h_con[7]), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un35_fc_h_av_o_axb_7_3756) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un35_fc_h_av_o_axb_6.INIT = 4'h9; + LUT2_L com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un35_fc_h_av_o_axb_6 ( + .I0(com_tlm_u_tlm_rx_fc_req_nph[6]), + .I1(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_h_con[6]), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un35_fc_h_av_o_axb_6_3757) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un35_fc_h_av_o_axb_5.INIT = 4'h9; + LUT2_L com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un35_fc_h_av_o_axb_5 ( + .I0(com_tlm_u_tlm_rx_fc_req_nph[5]), + .I1(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_h_con[5]), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un35_fc_h_av_o_axb_5_3758) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un35_fc_h_av_o_axb_4.INIT = 4'h9; + LUT2_L com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un35_fc_h_av_o_axb_4 ( + .I0(com_tlm_u_tlm_rx_fc_req_nph[4]), + .I1(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_h_con[4]), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un35_fc_h_av_o_axb_4_3759) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un35_fc_h_av_o_axb_3.INIT = 4'h9; + LUT2_L com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un35_fc_h_av_o_axb_3 ( + .I0(com_tlm_u_tlm_rx_fc_req_nph[3]), + .I1(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_h_con[3]), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un35_fc_h_av_o_axb_3_3760) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un35_fc_h_av_o_axb_2.INIT = 4'h9; + LUT2_L com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un35_fc_h_av_o_axb_2 ( + .I0(com_tlm_u_tlm_rx_fc_req_nph[2]), + .I1(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_h_con[2]), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un35_fc_h_av_o_axb_2_3761) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un35_fc_h_av_o_axb_1.INIT = 4'h9; + LUT2_L com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un35_fc_h_av_o_axb_1 ( + .I0(com_tlm_u_tlm_rx_fc_req_nph[1]), + .I1(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_h_con[1]), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un35_fc_h_av_o_axb_1_3762) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un35_fc_h_av_o_axb_0_i.INIT = 4'h1; + LUT1_L com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un35_fc_h_av_o_axb_0_i ( + .I0(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un35_fc_h_av_o_axb_0_3764), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un35_fc_h_av_o_axb_0_i_3763) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_d_o_axb_11.INIT = 4'h2; + LUT1_L com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_d_o_axb_11 ( + .I0(com_tlm_u_tlm_rx_fc_req_npd[11]), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_d_o_axb_11_3765) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_d_o_axb_10.INIT = 4'h2; + LUT1_L com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_d_o_axb_10 ( + .I0(com_tlm_u_tlm_rx_fc_req_npd[10]), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_d_o_axb_10_3766) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_d_o_axb_9.INIT = 4'h2; + LUT1_L com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_d_o_axb_9 ( + .I0(com_tlm_u_tlm_rx_fc_req_npd[9]), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_d_o_axb_9_3767) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_d_o_axb_8.INIT = 4'h2; + LUT1_L com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_d_o_axb_8 ( + .I0(com_tlm_u_tlm_rx_fc_req_npd[8]), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_d_o_axb_8_3768) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_d_o_axb_7.INIT = 4'h2; + LUT1_L com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_d_o_axb_7 ( + .I0(com_tlm_u_tlm_rx_fc_req_npd[7]), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_d_o_axb_7_3769) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_d_o_axb_6.INIT = 4'h2; + LUT1_L com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_d_o_axb_6 ( + .I0(com_tlm_u_tlm_rx_fc_req_npd[6]), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_d_o_axb_6_3770) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_d_o_axb_5.INIT = 8'h6C; + LUT3_L com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_d_o_axb_5 ( + .I0(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_N_41750_i), + .I1(com_tlm_u_tlm_rx_fc_req_npd[5]), + .I2(com_tlm_u_tlm_rx_fc_use_data[5]), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_d_o_axb_5_3771) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_d_o_axb_4.INIT = 8'h6C; + LUT3_L com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_d_o_axb_4 ( + .I0(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_N_41750_i), + .I1(com_tlm_u_tlm_rx_fc_req_npd[4]), + .I2(com_tlm_u_tlm_rx_fc_use_data[4]), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_d_o_axb_4_3772) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_d_o_axb_3.INIT = 8'h6C; + LUT3_L com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_d_o_axb_3 ( + .I0(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_N_41750_i), + .I1(com_tlm_u_tlm_rx_fc_req_npd[3]), + .I2(com_tlm_u_tlm_rx_fc_use_data[3]), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_d_o_axb_3_3773) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_d_o_axb_2.INIT = 8'h6C; + LUT3_L com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_d_o_axb_2 ( + .I0(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_N_41750_i), + .I1(com_tlm_u_tlm_rx_fc_req_npd[2]), + .I2(com_tlm_u_tlm_rx_fc_use_data[2]), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_d_o_axb_2_3774) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_d_o_axb_1.INIT = 8'h6C; + LUT3_L com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_d_o_axb_1 ( + .I0(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_N_41750_i), + .I1(com_tlm_u_tlm_rx_fc_req_npd[1]), + .I2(com_tlm_u_tlm_rx_fc_use_data[1]), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_d_o_axb_1_3775) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_d_o_axb_0.INIT = 8'h6C; + LUT3_L com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_d_o_axb_0 ( + .I0(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_N_41750_i), + .I1(com_tlm_u_tlm_rx_fc_req_npd[0]), + .I2(com_tlm_u_tlm_rx_fc_use_data[0]), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_d_o_axb_0_3776) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un1_fc_d_con_1_axb_11.INIT = 4'h2; + LUT1_L com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un1_fc_d_con_1_axb_11 ( + .I0(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_d_con[11]), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un1_fc_d_con_1_axb_11_3777) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un1_fc_d_con_1_axb_10.INIT = 4'h2; + LUT1_L com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un1_fc_d_con_1_axb_10 ( + .I0(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_d_con[10]), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un1_fc_d_con_1_axb_10_3778) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un1_fc_d_con_1_axb_9.INIT = 4'h2; + LUT1_L com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un1_fc_d_con_1_axb_9 ( + .I0(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_d_con[9]), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un1_fc_d_con_1_axb_9_3779) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un1_fc_d_con_1_axb_8.INIT = 4'h2; + LUT1_L com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un1_fc_d_con_1_axb_8 ( + .I0(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_d_con[8]), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un1_fc_d_con_1_axb_8_3780) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un1_fc_d_con_1_axb_7.INIT = 4'h2; + LUT1_L com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un1_fc_d_con_1_axb_7 ( + .I0(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_d_con[7]), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un1_fc_d_con_1_axb_7_3781) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un1_fc_d_con_1_axb_6.INIT = 4'h2; + LUT1_L com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un1_fc_d_con_1_axb_6 ( + .I0(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_d_con[6]), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un1_fc_d_con_1_axb_6_3782) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un1_fc_d_con_1_axb_5.INIT = 8'h78; + LUT3_L com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un1_fc_d_con_1_axb_5 ( + .I0(com_tlm_u_tlm_rx_fc_use_data[5]), + .I1(com_tlm_u_tlm_rx_fc_use_np), + .I2(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_d_con[5]), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un1_fc_d_con_1_axb_5_3783) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un1_fc_d_con_1_axb_4.INIT = 8'h78; + LUT3_L com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un1_fc_d_con_1_axb_4 ( + .I0(com_tlm_u_tlm_rx_fc_use_data[4]), + .I1(com_tlm_u_tlm_rx_fc_use_np), + .I2(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_d_con[4]), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un1_fc_d_con_1_axb_4_3784) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un1_fc_d_con_1_axb_3.INIT = 8'h78; + LUT3_L com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un1_fc_d_con_1_axb_3 ( + .I0(com_tlm_u_tlm_rx_fc_use_data[3]), + .I1(com_tlm_u_tlm_rx_fc_use_np), + .I2(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_d_con[3]), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un1_fc_d_con_1_axb_3_3785) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un1_fc_d_con_1_axb_2.INIT = 8'h78; + LUT3_L com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un1_fc_d_con_1_axb_2 ( + .I0(com_tlm_u_tlm_rx_fc_use_data[2]), + .I1(com_tlm_u_tlm_rx_fc_use_np), + .I2(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_d_con[2]), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un1_fc_d_con_1_axb_2_3786) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un1_fc_d_con_1_axb_1.INIT = 8'h78; + LUT3_L com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un1_fc_d_con_1_axb_1 ( + .I0(com_tlm_u_tlm_rx_fc_use_data[1]), + .I1(com_tlm_u_tlm_rx_fc_use_np), + .I2(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_d_con[1]), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un1_fc_d_con_1_axb_1_3787) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_N_68905_i.INIT = 8'hF4; + LUT3_L com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_N_68905_i ( + .I0(com_tlm_u_tlm_rx_fc_sched_np), + .I1(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_send_state_2__3791), + .I2(com_tlm_u_tlm_rx_fc_send_state_0_sqmuxa_0), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_N_68905_i_3788) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_N_68906_i.INIT = 16'h7530; + LUT4_L com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_N_68906_i ( + .I0(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_N_42049_i), + .I1(com_tlm_u_tlm_rx_fc_req_np_dst_rdy), + .I2(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_req_np_src_rdy), + .I3(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_send_state_0__3792), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_N_68906_i_3789) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_N_68907_i.INIT = 16'hECA0; + LUT4_L com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_N_68907_i ( + .I0(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_N_42049_i), + .I1(com_tlm_u_tlm_rx_fc_sched_np), + .I2(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_send_state_0__3792), + .I3(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_send_state_2__3791), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_N_68907_i_3790) + ); + FD com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_d_advert_11_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un5_fc_d_advert_s_11_3793), + .Q(com_tlm_u_tlm_rx_vc0_flow_ctrl_fc_d_advert[11]) + ); + FD com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_h_advert_7_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un5_fc_h_advert_s_7_3794), + .Q(com_tlm_u_tlm_rx_vc0_flow_ctrl_fc_h_advert[7]) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_h_con_qxu_0_0_.INIT = 4'h2; + LUT1_L com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_h_con_qxu_0_0_ ( + .I0(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_h_con[0]), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_h_con_qxu[0]) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_h_con_qxu_0_7_.INIT = 4'h2; + LUT1_L com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_h_con_qxu_0_7_ ( + .I0(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_h_con[7]), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_h_con_qxu[7]) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_h_con_qxu_0_6_.INIT = 4'h2; + LUT1_L com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_h_con_qxu_0_6_ ( + .I0(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_h_con[6]), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_h_con_qxu[6]) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_h_con_qxu_0_5_.INIT = 4'h2; + LUT1_L com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_h_con_qxu_0_5_ ( + .I0(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_h_con[5]), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_h_con_qxu[5]) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_h_con_qxu_0_4_.INIT = 4'h2; + LUT1_L com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_h_con_qxu_0_4_ ( + .I0(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_h_con[4]), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_h_con_qxu[4]) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_h_con_qxu_0_3_.INIT = 4'h2; + LUT1_L com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_h_con_qxu_0_3_ ( + .I0(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_h_con[3]), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_h_con_qxu[3]) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_h_con_qxu_0_2_.INIT = 4'h2; + LUT1_L com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_h_con_qxu_0_2_ ( + .I0(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_h_con[2]), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_h_con_qxu[2]) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_h_con_qxu_0_1_.INIT = 4'h2; + LUT1_L com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_h_con_qxu_0_1_ ( + .I0(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_h_con[1]), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_h_con_qxu[1]) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_h_con_s_0_.INIT = 4'h1; + LUT1_L com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_h_con_s_0_ ( + .I0(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_h_con_qxu[0]), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_h_con_s[0]) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un5_fc_d_advert_axb_10.INIT = 4'h9; + LUT2 com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un5_fc_d_advert_axb_10 ( + .I0(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_d_alo[10]), + .I1(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_d_con[10]), + .O(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un5_fc_d_advert_axb_10_3795) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un5_fc_d_advert_axb_9.INIT = 4'h9; + LUT2 com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un5_fc_d_advert_axb_9 ( + .I0(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_d_alo[9]), + .I1(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_d_con[9]), + .O(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un5_fc_d_advert_axb_9_3796) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un5_fc_d_advert_axb_8.INIT = 4'h9; + LUT2 com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un5_fc_d_advert_axb_8 ( + .I0(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_d_alo[8]), + .I1(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_d_con[8]), + .O(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un5_fc_d_advert_axb_8_3797) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un5_fc_d_advert_axb_7.INIT = 4'h9; + LUT2 com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un5_fc_d_advert_axb_7 ( + .I0(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_d_alo[7]), + .I1(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_d_con[7]), + .O(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un5_fc_d_advert_axb_7_3798) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un5_fc_d_advert_axb_6.INIT = 4'h9; + LUT2 com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un5_fc_d_advert_axb_6 ( + .I0(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_d_alo[6]), + .I1(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_d_con[6]), + .O(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un5_fc_d_advert_axb_6_3799) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un5_fc_d_advert_axb_5.INIT = 4'h9; + LUT2 com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un5_fc_d_advert_axb_5 ( + .I0(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_d_alo[5]), + .I1(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_d_con[5]), + .O(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un5_fc_d_advert_axb_5_3800) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un5_fc_d_advert_axb_4.INIT = 4'h9; + LUT2 com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un5_fc_d_advert_axb_4 ( + .I0(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_d_alo[4]), + .I1(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_d_con[4]), + .O(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un5_fc_d_advert_axb_4_3801) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un5_fc_d_advert_axb_3.INIT = 4'h9; + LUT2 com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un5_fc_d_advert_axb_3 ( + .I0(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_d_alo[3]), + .I1(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_d_con[3]), + .O(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un5_fc_d_advert_axb_3_3802) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un5_fc_d_advert_axb_2.INIT = 4'h9; + LUT2 com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un5_fc_d_advert_axb_2 ( + .I0(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_d_alo[2]), + .I1(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_d_con[2]), + .O(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un5_fc_d_advert_axb_2_3803) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un5_fc_d_advert_axb_1.INIT = 4'h9; + LUT2 com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un5_fc_d_advert_axb_1 ( + .I0(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_d_alo[1]), + .I1(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_d_con[1]), + .O(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un5_fc_d_advert_axb_1_3804) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un5_fc_d_advert_axb_0.INIT = 4'h9; + LUT2 com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un5_fc_d_advert_axb_0 ( + .I0(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_d_alo[0]), + .I1(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_d_con[0]), + .O(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un5_fc_d_advert_axb_0_3805) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un5_fc_h_advert_axb_6.INIT = 4'h9; + LUT2 com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un5_fc_h_advert_axb_6 ( + .I0(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_h_alo[6]), + .I1(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_h_con[6]), + .O(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un5_fc_h_advert_axb_6_3806) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un5_fc_h_advert_axb_5.INIT = 4'h9; + LUT2 com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un5_fc_h_advert_axb_5 ( + .I0(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_h_alo[5]), + .I1(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_h_con[5]), + .O(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un5_fc_h_advert_axb_5_3807) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un5_fc_h_advert_axb_4.INIT = 4'h9; + LUT2 com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un5_fc_h_advert_axb_4 ( + .I0(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_h_alo[4]), + .I1(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_h_con[4]), + .O(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un5_fc_h_advert_axb_4_3808) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un5_fc_h_advert_axb_3.INIT = 4'h9; + LUT2 com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un5_fc_h_advert_axb_3 ( + .I0(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_h_alo[3]), + .I1(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_h_con[3]), + .O(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un5_fc_h_advert_axb_3_3809) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un5_fc_h_advert_axb_2.INIT = 4'h9; + LUT2 com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un5_fc_h_advert_axb_2 ( + .I0(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_h_alo[2]), + .I1(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_h_con[2]), + .O(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un5_fc_h_advert_axb_2_3810) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un5_fc_h_advert_axb_1.INIT = 4'h9; + LUT2 com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un5_fc_h_advert_axb_1 ( + .I0(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_h_alo[1]), + .I1(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_h_con[1]), + .O(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un5_fc_h_advert_axb_1_3811) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un5_fc_h_advert_axb_0.INIT = 4'h9; + LUT2 com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un5_fc_h_advert_axb_0 ( + .I0(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_h_alo[0]), + .I1(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_h_con[0]), + .O(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un5_fc_h_advert_axb_0_3812) + ); + VCC com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_VCC ( + .P(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_VCC_4013) + ); + GND com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_GND ( + .G(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_GND_3893) + ); + FDR com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_d_con_0_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_d_con_2_axb_0_3896), + .Q(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_d_con[0]), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_d_con_1_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_d_con_2_s_1_3837), + .Q(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_d_con[1]), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_d_con_2_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_d_con_2_s_2_3840), + .Q(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_d_con[2]), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_d_con_3_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_d_con_2_s_3_3843), + .Q(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_d_con[3]), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_d_con_4_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_d_con_2_s_4_3846), + .Q(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_d_con[4]), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_d_con_5_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_d_con_2_s_5_3849), + .Q(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_d_con[5]), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_d_con_6_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_d_con_2_s_6_3851), + .Q(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_d_con[6]), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_d_con_7_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_d_con_2_s_7_3853), + .Q(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_d_con[7]), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_d_con_8_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_d_con_2_s_8_3855), + .Q(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_d_con[8]), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_d_con_9_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_d_con_2_s_9_3857), + .Q(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_d_con[9]), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_d_con_10_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_d_con_2_s_10_3859), + .Q(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_d_con[10]), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_d_con_11_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_d_con_2_s_11_3861), + .Q(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_d_con[11]), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_free_h ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_free_h_13), + .Q(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_free_h_3894), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_free_d ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_free_d_13), + .Q(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_free_d_3895), + .R(plm_link_up_i) + ); + MUXCY_L com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_h_o_2_cry_0 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_free_h[0]), + .DI(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_h_o_i_m2_i_m3_i_m3_0_0__4005), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_h_o_2_cry_0_3813), + .S(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_h_o_2_axb_0_3923) + ); + XORCY com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_h_o_2_s_0 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_free_h[0]), + .LI(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_h_o_2_axb_0_3923), + .O(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_h_o_2_s_0_3974) + ); + MUXCY_L com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_h_o_2_cry_1 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_h_o_2_cry_0_3813), + .DI(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_GND_3893), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_h_o_2_cry_1_3814), + .S(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_h_o_2_axb_1_3922) + ); + XORCY com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_h_o_2_s_1 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_h_o_2_cry_0_3813), + .LI(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_h_o_2_axb_1_3922), + .O(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_h_o_2_s_1_3973) + ); + MUXCY_L com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_h_o_2_cry_2 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_h_o_2_cry_1_3814), + .DI(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_h_o_i_m2_i_m3_i_m3_0_2__4007), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_h_o_2_cry_2_3815), + .S(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_h_o_2_axb_2_3921) + ); + XORCY com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_h_o_2_s_2 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_h_o_2_cry_1_3814), + .LI(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_h_o_2_axb_2_3921), + .O(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_h_o_2_s_2_3972) + ); + MUXCY_L com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_h_o_2_cry_3 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_h_o_2_cry_2_3815), + .DI(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_GND_3893), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_h_o_2_cry_3_3816), + .S(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_h_o_2_axb_3_3920) + ); + XORCY com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_h_o_2_s_3 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_h_o_2_cry_2_3815), + .LI(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_h_o_2_axb_3_3920), + .O(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_h_o_2_s_3_3971) + ); + MUXCY_L com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_h_o_2_cry_4 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_h_o_2_cry_3_3816), + .DI(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_GND_3893), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_h_o_2_cry_4_3817), + .S(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_h_o_2_axb_4_3919) + ); + XORCY com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_h_o_2_s_4 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_h_o_2_cry_3_3816), + .LI(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_h_o_2_axb_4_3919), + .O(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_h_o_2_s_4_3970) + ); + MUXCY_L com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_h_o_2_cry_5 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_h_o_2_cry_4_3817), + .DI(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_N_8995_i_4009), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_h_o_2_cry_5_3818), + .S(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_h_o_2_axb_5_3918) + ); + XORCY com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_h_o_2_s_5 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_h_o_2_cry_4_3817), + .LI(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_h_o_2_axb_5_3918), + .O(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_h_o_2_s_5_3969) + ); + MUXCY_L com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_h_o_2_cry_6 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_h_o_2_cry_5_3818), + .DI(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_GND_3893), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_h_o_2_cry_6_3819), + .S(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_h_o_2_axb_6_3917) + ); + XORCY com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_h_o_2_s_6 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_h_o_2_cry_5_3818), + .LI(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_h_o_2_axb_6_3917), + .O(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_h_o_2_s_6_3968) + ); + XORCY com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_h_o_2_s_7 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_h_o_2_cry_6_3819), + .LI(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_h_o_2_axb_7_3916), + .O(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_h_o_2_s_7_3967) + ); + MUXCY_L com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_2_cry_0 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_free_d[0]), + .DI(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_2_cry_0_ma_4010), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_2_cry_0_3821), + .S(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_2_axb_0_3915) + ); + XORCY com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_2_s_0 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_free_d[0]), + .LI(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_2_axb_0_3915), + .O(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_2_s_0_3966) + ); + MULT_AND com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_2_cry_1 ( + .I0(com_tlm_u_tlm_rx_fc_use_data[1]), + .I1(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_N_42502_1), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_2_cry_1_0_3820) + ); + MUXCY_L com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_2_cry_1_0 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_2_cry_0_3821), + .DI(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_2_cry_1_0_3820), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_2_cry_1_3823), + .S(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_2_axb_1_3914) + ); + XORCY com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_2_s_1 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_2_cry_0_3821), + .LI(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_2_axb_1_3914), + .O(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_2_s_1_3965) + ); + MULT_AND com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_2_cry_2 ( + .I0(com_tlm_u_tlm_rx_fc_use_data[2]), + .I1(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_N_42502_1), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_2_cry_2_0_3822) + ); + MUXCY_L com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_2_cry_2_0 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_2_cry_1_3823), + .DI(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_2_cry_2_0_3822), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_2_cry_2_3825), + .S(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_2_axb_2_3913) + ); + XORCY com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_2_s_2 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_2_cry_1_3823), + .LI(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_2_axb_2_3913), + .O(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_2_s_2_3964) + ); + MULT_AND com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_2_cry_3 ( + .I0(com_tlm_u_tlm_rx_fc_use_data[3]), + .I1(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_N_42502_1), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_2_cry_3_0_3824) + ); + MUXCY_L com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_2_cry_3_0 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_2_cry_2_3825), + .DI(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_2_cry_3_0_3824), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_2_cry_3_3826), + .S(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_2_axb_3_3936) + ); + XORCY com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_2_s_3 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_2_cry_2_3825), + .LI(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_2_axb_3_3936), + .O(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_2_s_3_3987) + ); + MUXCY_L com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_2_cry_4 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_2_cry_3_3826), + .DI(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_2_cry_4_ma_4012), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_2_cry_4_3828), + .S(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_2_axb_4_3935) + ); + XORCY com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_2_s_4 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_2_cry_3_3826), + .LI(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_2_axb_4_3935), + .O(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_2_s_4_3986) + ); + MULT_AND com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_2_cry_5 ( + .I0(com_tlm_u_tlm_rx_fc_use_data[5]), + .I1(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_N_42502_1), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_2_cry_5_0_3827) + ); + MUXCY_L com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_2_cry_5_0 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_2_cry_4_3828), + .DI(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_2_cry_5_0_3827), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_2_cry_5_3829), + .S(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_2_axb_5_3934) + ); + XORCY com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_2_s_5 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_2_cry_4_3828), + .LI(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_2_axb_5_3934), + .O(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_2_s_5_3985) + ); + MUXCY_L com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_2_cry_6 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_2_cry_5_3829), + .DI(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_GND_3893), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_2_cry_6_3830), + .S(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_2_axb_6_3933) + ); + XORCY com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_2_s_6 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_2_cry_5_3829), + .LI(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_2_axb_6_3933), + .O(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_2_s_6_3984) + ); + MUXCY_L com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_2_cry_7 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_2_cry_6_3830), + .DI(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_N_9006_i_4003), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_2_cry_7_3831), + .S(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_2_axb_7_3932) + ); + XORCY com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_2_s_7 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_2_cry_6_3830), + .LI(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_2_axb_7_3932), + .O(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_2_s_7_3983) + ); + MUXCY_L com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_2_cry_8 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_2_cry_7_3831), + .DI(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_GND_3893), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_2_cry_8_3832), + .S(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_2_axb_8_3931) + ); + XORCY com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_2_s_8 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_2_cry_7_3831), + .LI(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_2_axb_8_3931), + .O(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_2_s_8_3982) + ); + MUXCY_L com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_2_cry_9 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_2_cry_8_3832), + .DI(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_GND_3893), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_2_cry_9_3833), + .S(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_2_axb_9_3930) + ); + XORCY com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_2_s_9 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_2_cry_8_3832), + .LI(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_2_axb_9_3930), + .O(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_2_s_9_3981) + ); + MUXCY_L com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_2_cry_10 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_2_cry_9_3833), + .DI(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_GND_3893), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_2_cry_10_3834), + .S(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_2_axb_10_3929) + ); + XORCY com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_2_s_10 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_2_cry_9_3833), + .LI(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_2_axb_10_3929), + .O(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_2_s_10_3980) + ); + XORCY com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_2_s_11 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_2_cry_10_3834), + .LI(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_2_axb_11_3928), + .O(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_2_s_11_3979) + ); + MULT_AND com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_d_con_2_cry_0 ( + .I0(com_tlm_u_tlm_rx_fc_use_cpl), + .I1(com_tlm_u_tlm_rx_fc_use_data[0]), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_d_con_2_cry_0_0_3835) + ); + MUXCY_L com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_d_con_2_cry_0_0 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_GND_3893), + .DI(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_d_con_2_cry_0_0_3835), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_d_con_2_cry_0_3838), + .S(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_d_con_2_axb_0_3896) + ); + MULT_AND com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_d_con_2_cry_1 ( + .I0(com_tlm_u_tlm_rx_fc_use_cpl), + .I1(com_tlm_u_tlm_rx_fc_use_data[1]), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_d_con_2_cry_1_0_3836) + ); + MUXCY_L com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_d_con_2_cry_1_0 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_d_con_2_cry_0_3838), + .DI(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_d_con_2_cry_1_0_3836), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_d_con_2_cry_1_3841), + .S(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_d_con_2_axb_1_3947) + ); + XORCY com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_d_con_2_s_1 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_d_con_2_cry_0_3838), + .LI(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_d_con_2_axb_1_3947), + .O(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_d_con_2_s_1_3837) + ); + MULT_AND com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_d_con_2_cry_2 ( + .I0(com_tlm_u_tlm_rx_fc_use_cpl), + .I1(com_tlm_u_tlm_rx_fc_use_data[2]), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_d_con_2_cry_2_0_3839) + ); + MUXCY_L com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_d_con_2_cry_2_0 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_d_con_2_cry_1_3841), + .DI(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_d_con_2_cry_2_0_3839), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_d_con_2_cry_2_3844), + .S(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_d_con_2_axb_2_3946) + ); + XORCY com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_d_con_2_s_2 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_d_con_2_cry_1_3841), + .LI(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_d_con_2_axb_2_3946), + .O(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_d_con_2_s_2_3840) + ); + MULT_AND com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_d_con_2_cry_3 ( + .I0(com_tlm_u_tlm_rx_fc_use_cpl), + .I1(com_tlm_u_tlm_rx_fc_use_data[3]), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_d_con_2_cry_3_0_3842) + ); + MUXCY_L com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_d_con_2_cry_3_0 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_d_con_2_cry_2_3844), + .DI(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_d_con_2_cry_3_0_3842), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_d_con_2_cry_3_3847), + .S(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_d_con_2_axb_3_3945) + ); + XORCY com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_d_con_2_s_3 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_d_con_2_cry_2_3844), + .LI(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_d_con_2_axb_3_3945), + .O(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_d_con_2_s_3_3843) + ); + MULT_AND com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_d_con_2_cry_4 ( + .I0(com_tlm_u_tlm_rx_fc_use_cpl), + .I1(com_tlm_u_tlm_rx_fc_use_data[4]), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_d_con_2_cry_4_0_3845) + ); + MUXCY_L com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_d_con_2_cry_4_0 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_d_con_2_cry_3_3847), + .DI(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_d_con_2_cry_4_0_3845), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_d_con_2_cry_4_3850), + .S(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_d_con_2_axb_4_3944) + ); + XORCY com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_d_con_2_s_4 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_d_con_2_cry_3_3847), + .LI(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_d_con_2_axb_4_3944), + .O(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_d_con_2_s_4_3846) + ); + MULT_AND com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_d_con_2_cry_5 ( + .I0(com_tlm_u_tlm_rx_fc_use_cpl), + .I1(com_tlm_u_tlm_rx_fc_use_data[5]), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_d_con_2_cry_5_0_3848) + ); + MUXCY_L com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_d_con_2_cry_5_0 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_d_con_2_cry_4_3850), + .DI(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_d_con_2_cry_5_0_3848), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_d_con_2_cry_5_3852), + .S(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_d_con_2_axb_5_3943) + ); + XORCY com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_d_con_2_s_5 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_d_con_2_cry_4_3850), + .LI(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_d_con_2_axb_5_3943), + .O(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_d_con_2_s_5_3849) + ); + MUXCY_L com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_d_con_2_cry_6 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_d_con_2_cry_5_3852), + .DI(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_GND_3893), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_d_con_2_cry_6_3854), + .S(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_d_con_2_axb_6_3942) + ); + XORCY com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_d_con_2_s_6 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_d_con_2_cry_5_3852), + .LI(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_d_con_2_axb_6_3942), + .O(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_d_con_2_s_6_3851) + ); + MUXCY_L com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_d_con_2_cry_7 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_d_con_2_cry_6_3854), + .DI(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_GND_3893), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_d_con_2_cry_7_3856), + .S(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_d_con_2_axb_7_3941) + ); + XORCY com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_d_con_2_s_7 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_d_con_2_cry_6_3854), + .LI(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_d_con_2_axb_7_3941), + .O(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_d_con_2_s_7_3853) + ); + MUXCY_L com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_d_con_2_cry_8 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_d_con_2_cry_7_3856), + .DI(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_GND_3893), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_d_con_2_cry_8_3858), + .S(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_d_con_2_axb_8_3940) + ); + XORCY com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_d_con_2_s_8 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_d_con_2_cry_7_3856), + .LI(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_d_con_2_axb_8_3940), + .O(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_d_con_2_s_8_3855) + ); + MUXCY_L com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_d_con_2_cry_9 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_d_con_2_cry_8_3858), + .DI(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_GND_3893), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_d_con_2_cry_9_3860), + .S(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_d_con_2_axb_9_3939) + ); + XORCY com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_d_con_2_s_9 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_d_con_2_cry_8_3858), + .LI(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_d_con_2_axb_9_3939), + .O(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_d_con_2_s_9_3857) + ); + MUXCY_L com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_d_con_2_cry_10 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_d_con_2_cry_9_3860), + .DI(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_GND_3893), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_d_con_2_cry_10_3862), + .S(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_d_con_2_axb_10_3938) + ); + XORCY com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_d_con_2_s_10 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_d_con_2_cry_9_3860), + .LI(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_d_con_2_axb_10_3938), + .O(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_d_con_2_s_10_3859) + ); + XORCY com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_d_con_2_s_11 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_d_con_2_cry_10_3862), + .LI(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_d_con_2_axb_11_3937), + .O(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_d_con_2_s_11_3861) + ); + MUXCY_L com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_h_o_1_cry_0 ( + .CI(plm_link_up_1), + .DI(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_h_o_1_cry_0_ma_4004), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_h_o_1_cry_0_3864), + .S(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_h_o_1_axb_0_3901) + ); + XORCY com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_h_o_1_s_0 ( + .CI(plm_link_up_1), + .LI(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_h_o_1_axb_0_3901), + .O(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_h_o_1_s_0_3952) + ); + MULT_AND com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_h_o_1_cry_1 ( + .I0(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_h_con_i_1__3988), + .I1(plm_link_up_1), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_h_o_1_cry_1_0_3863) + ); + MUXCY_L com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_h_o_1_cry_1_0 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_h_o_1_cry_0_3864), + .DI(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_h_o_1_cry_1_0_3863), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_h_o_1_cry_1_3865), + .S(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_h_o_1_axb_1_3900) + ); + XORCY com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_h_o_1_s_1 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_h_o_1_cry_0_3864), + .LI(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_h_o_1_axb_1_3900), + .O(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_h_o_1_s_1_3951) + ); + MUXCY_L com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_h_o_1_cry_2 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_h_o_1_cry_1_3865), + .DI(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_h_o_1_cry_2_ma_4006), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_h_o_1_cry_2_3867), + .S(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_h_o_1_axb_2_3899) + ); + XORCY com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_h_o_1_s_2 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_h_o_1_cry_1_3865), + .LI(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_h_o_1_axb_2_3899), + .O(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_h_o_1_s_2_3950) + ); + MULT_AND com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_h_o_1_cry_3 ( + .I0(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_h_con_i_3__3989), + .I1(plm_link_up_1), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_h_o_1_cry_3_0_3866) + ); + MUXCY_L com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_h_o_1_cry_3_0 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_h_o_1_cry_2_3867), + .DI(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_h_o_1_cry_3_0_3866), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_h_o_1_cry_3_3869), + .S(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_h_o_1_axb_3_3898) + ); + XORCY com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_h_o_1_s_3 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_h_o_1_cry_2_3867), + .LI(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_h_o_1_axb_3_3898), + .O(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_h_o_1_s_3_3949) + ); + MULT_AND com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_h_o_1_cry_4 ( + .I0(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_h_con_i_4__3990), + .I1(plm_link_up_2), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_h_o_1_cry_4_0_3868) + ); + MUXCY_L com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_h_o_1_cry_4_0 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_h_o_1_cry_3_3869), + .DI(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_h_o_1_cry_4_0_3868), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_h_o_1_cry_4_3870), + .S(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_h_o_1_axb_4_3927) + ); + XORCY com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_h_o_1_s_4 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_h_o_1_cry_3_3869), + .LI(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_h_o_1_axb_4_3927), + .O(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_h_o_1_s_4_3978) + ); + MUXCY_L com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_h_o_1_cry_5 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_h_o_1_cry_4_3870), + .DI(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_h_o_1_cry_5_ma_4008), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_h_o_1_cry_5_3872), + .S(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_h_o_1_axb_5_3926) + ); + XORCY com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_h_o_1_s_5 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_h_o_1_cry_4_3870), + .LI(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_h_o_1_axb_5_3926), + .O(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_h_o_1_s_5_3977) + ); + MULT_AND com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_h_o_1_cry_6 ( + .I0(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_h_con_i_6__3991), + .I1(plm_link_up_2), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_h_o_1_cry_6_0_3871) + ); + MUXCY_L com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_h_o_1_cry_6_0 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_h_o_1_cry_5_3872), + .DI(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_h_o_1_cry_6_0_3871), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_h_o_1_cry_6_3873), + .S(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_h_o_1_axb_6_3925) + ); + XORCY com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_h_o_1_s_6 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_h_o_1_cry_5_3872), + .LI(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_h_o_1_axb_6_3925), + .O(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_h_o_1_s_6_3976) + ); + XORCY com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_h_o_1_s_7 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_h_o_1_cry_6_3873), + .LI(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_h_o_1_axb_7_3924), + .O(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_h_o_1_s_7_3975) + ); + MUXCY_L com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_1_cry_0 ( + .CI(plm_link_up_1), + .DI(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_1_cry_0_ma_4000), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_1_cry_0_3875), + .S(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_1_axb_0_3897) + ); + XORCY com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_1_s_0 ( + .CI(plm_link_up_1), + .LI(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_1_axb_0_3897), + .O(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_1_s_0_3948) + ); + MULT_AND com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_1_cry_1 ( + .I0(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_d_con_i_1__3992), + .I1(plm_link_up_1), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_1_cry_1_0_3874) + ); + MUXCY_L com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_1_cry_1_0 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_1_cry_0_3875), + .DI(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_1_cry_1_0_3874), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_1_cry_1_3877), + .S(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_1_axb_1_3912) + ); + XORCY com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_1_s_1 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_1_cry_0_3875), + .LI(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_1_axb_1_3912), + .O(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_1_s_1_3963) + ); + MULT_AND com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_1_cry_2 ( + .I0(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_d_con_i_2__3993), + .I1(plm_link_up_1), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_1_cry_2_0_3876) + ); + MUXCY_L com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_1_cry_2_0 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_1_cry_1_3877), + .DI(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_1_cry_2_0_3876), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_1_cry_2_3879), + .S(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_1_axb_2_3911) + ); + XORCY com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_1_s_2 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_1_cry_1_3877), + .LI(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_1_axb_2_3911), + .O(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_1_s_2_3962) + ); + MULT_AND com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_1_cry_3 ( + .I0(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_d_con_i_3__3994), + .I1(plm_link_up_1), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_1_cry_3_0_3878) + ); + MUXCY_L com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_1_cry_3_0 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_1_cry_2_3879), + .DI(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_1_cry_3_0_3878), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_1_cry_3_3880), + .S(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_1_axb_3_3910) + ); + XORCY com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_1_s_3 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_1_cry_2_3879), + .LI(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_1_axb_3_3910), + .O(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_1_s_3_3961) + ); + MUXCY_L com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_1_cry_4 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_1_cry_3_3880), + .DI(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_1_cry_4_ma_4001), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_1_cry_4_3882), + .S(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_1_axb_4_3909) + ); + XORCY com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_1_s_4 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_1_cry_3_3880), + .LI(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_1_axb_4_3909), + .O(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_1_s_4_3960) + ); + MULT_AND com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_1_cry_5 ( + .I0(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_d_con_i_5__3995), + .I1(plm_link_up_1), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_1_cry_5_0_3881) + ); + MUXCY_L com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_1_cry_5_0 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_1_cry_4_3882), + .DI(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_1_cry_5_0_3881), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_1_cry_5_3884), + .S(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_1_axb_5_3908) + ); + XORCY com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_1_s_5 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_1_cry_4_3882), + .LI(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_1_axb_5_3908), + .O(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_1_s_5_3959) + ); + MULT_AND com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_1_cry_6 ( + .I0(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_d_con_i_6__3996), + .I1(plm_link_up_1), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_1_cry_6_0_3883) + ); + MUXCY_L com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_1_cry_6_0 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_1_cry_5_3884), + .DI(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_1_cry_6_0_3883), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_1_cry_6_3885), + .S(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_1_axb_6_3907) + ); + XORCY com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_1_s_6 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_1_cry_5_3884), + .LI(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_1_axb_6_3907), + .O(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_1_s_6_3958) + ); + MUXCY_L com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_1_cry_7 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_1_cry_6_3885), + .DI(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_1_cry_7_ma_4002), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_1_cry_7_3887), + .S(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_1_axb_7_3906) + ); + XORCY com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_1_s_7 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_1_cry_6_3885), + .LI(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_1_axb_7_3906), + .O(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_1_s_7_3957) + ); + MULT_AND com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_1_cry_8 ( + .I0(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_d_con_i_8__3997), + .I1(plm_link_up_1), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_1_cry_8_0_3886) + ); + MUXCY_L com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_1_cry_8_0 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_1_cry_7_3887), + .DI(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_1_cry_8_0_3886), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_1_cry_8_3889), + .S(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_1_axb_8_3905) + ); + XORCY com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_1_s_8 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_1_cry_7_3887), + .LI(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_1_axb_8_3905), + .O(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_1_s_8_3956) + ); + MULT_AND com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_1_cry_9 ( + .I0(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_d_con_i_9__3998), + .I1(plm_link_up_1), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_1_cry_9_0_3888) + ); + MUXCY_L com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_1_cry_9_0 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_1_cry_8_3889), + .DI(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_1_cry_9_0_3888), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_1_cry_9_3891), + .S(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_1_axb_9_3904) + ); + XORCY com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_1_s_9 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_1_cry_8_3889), + .LI(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_1_axb_9_3904), + .O(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_1_s_9_3955) + ); + MULT_AND com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_1_cry_10 ( + .I0(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_d_con_i_10__3999), + .I1(plm_link_up_1), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_1_cry_10_0_3890) + ); + MUXCY_L com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_1_cry_10_0 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_1_cry_9_3891), + .DI(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_1_cry_10_0_3890), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_1_cry_10_3892), + .S(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_1_axb_10_3903) + ); + XORCY com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_1_s_10 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_1_cry_9_3891), + .LI(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_1_axb_10_3903), + .O(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_1_s_10_3954) + ); + XORCY com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_1_s_11 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_1_cry_10_3892), + .LI(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_1_axb_11_3902), + .O(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_1_s_11_3953) + ); + FDRE com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_h_con_0_ ( + .CE(com_tlm_u_tlm_rx_fc_use_cpl), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_h_con_s[0]), + .Q(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_h_con[0]), + .R(plm_link_up_i) + ); + MUXCY_L com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_h_con_cry_1_ ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_h_con[0]), + .DI(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_GND_3893), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_h_con_cry[1]), + .S(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_h_con_qxu[1]) + ); + XORCY com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_h_con_s_1_ ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_h_con[0]), + .LI(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_h_con_qxu[1]), + .O(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_h_con_s[1]) + ); + FDRE com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_h_con_1_ ( + .CE(com_tlm_u_tlm_rx_fc_use_cpl), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_h_con_s[1]), + .Q(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_h_con[1]), + .R(plm_link_up_i) + ); + MUXCY_L com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_h_con_cry_2_ ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_h_con_cry[1]), + .DI(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_GND_3893), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_h_con_cry[2]), + .S(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_h_con_qxu[2]) + ); + XORCY com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_h_con_s_2_ ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_h_con_cry[1]), + .LI(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_h_con_qxu[2]), + .O(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_h_con_s[2]) + ); + FDRE com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_h_con_2_ ( + .CE(com_tlm_u_tlm_rx_fc_use_cpl), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_h_con_s[2]), + .Q(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_h_con[2]), + .R(plm_link_up_i) + ); + MUXCY_L com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_h_con_cry_3_ ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_h_con_cry[2]), + .DI(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_GND_3893), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_h_con_cry[3]), + .S(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_h_con_qxu[3]) + ); + XORCY com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_h_con_s_3_ ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_h_con_cry[2]), + .LI(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_h_con_qxu[3]), + .O(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_h_con_s[3]) + ); + FDRE com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_h_con_3_ ( + .CE(com_tlm_u_tlm_rx_fc_use_cpl), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_h_con_s[3]), + .Q(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_h_con[3]), + .R(plm_link_up_i) + ); + MUXCY_L com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_h_con_cry_4_ ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_h_con_cry[3]), + .DI(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_GND_3893), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_h_con_cry[4]), + .S(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_h_con_qxu[4]) + ); + XORCY com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_h_con_s_4_ ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_h_con_cry[3]), + .LI(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_h_con_qxu[4]), + .O(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_h_con_s[4]) + ); + FDRE com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_h_con_4_ ( + .CE(com_tlm_u_tlm_rx_fc_use_cpl), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_h_con_s[4]), + .Q(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_h_con[4]), + .R(plm_link_up_i) + ); + MUXCY_L com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_h_con_cry_5_ ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_h_con_cry[4]), + .DI(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_GND_3893), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_h_con_cry[5]), + .S(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_h_con_qxu[5]) + ); + XORCY com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_h_con_s_5_ ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_h_con_cry[4]), + .LI(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_h_con_qxu[5]), + .O(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_h_con_s[5]) + ); + FDRE com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_h_con_5_ ( + .CE(com_tlm_u_tlm_rx_fc_use_cpl), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_h_con_s[5]), + .Q(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_h_con[5]), + .R(plm_link_up_i) + ); + MUXCY_L com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_h_con_cry_6_ ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_h_con_cry[5]), + .DI(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_GND_3893), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_h_con_cry[6]), + .S(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_h_con_qxu[6]) + ); + XORCY com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_h_con_s_6_ ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_h_con_cry[5]), + .LI(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_h_con_qxu[6]), + .O(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_h_con_s[6]) + ); + FDRE com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_h_con_6_ ( + .CE(com_tlm_u_tlm_rx_fc_use_cpl), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_h_con_s[6]), + .Q(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_h_con[6]), + .R(plm_link_up_i) + ); + XORCY com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_h_con_s_7_ ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_h_con_cry[6]), + .LI(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_h_con_qxu[7]), + .O(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_h_con_s[7]) + ); + FDRE com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_h_con_7_ ( + .CE(com_tlm_u_tlm_rx_fc_use_cpl), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_h_con_s[7]), + .Q(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_h_con[7]), + .R(plm_link_up_i) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_free_h_0_.INIT = 4'h8; + LUT2 com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_free_h_0_ ( + .I0(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_free_h_3894), + .I1(plm_link_up_1), + .O(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_free_h[0]) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_free_d_0_.INIT = 4'h8; + LUT2 com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_free_d_0_ ( + .I0(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_free_d_3895), + .I1(plm_link_up_1), + .O(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_free_d[0]) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_h_o_5_.INIT = 4'h4; + LUT2_L com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_h_o_5_ ( + .I0(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_req_h_o[5]), + .I1(plm_link_up_1), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_h_o[5]) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_unuse_d28_1_i_0_a4_0_.INIT = 4'h8; + LUT2 com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_unuse_d28_1_i_0_a4_0_ ( + .I0(com_tlm_u_tlm_rx_fc_unuse), + .I1(com_tlm_u_tlm_rx_fc_use_cpl), + .O(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_N_43127) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_h_o_i_m2_i_m3_i_m3_0_2_.INIT = 8'hCA; + LUT3 com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_h_o_i_m2_i_m3_i_m3_0_2_ ( + .I0(cfg_cfg_5072[508]), + .I1(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_req_h_o[2]), + .I2(plm_link_up_1), + .O(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_h_o_i_m2_i_m3_i_m3_0_2__4007) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_h_o_i_m2_i_m3_i_m3_0_0_.INIT = 8'hCA; + LUT3 com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_h_o_i_m2_i_m3_i_m3_0_0_ ( + .I0(cfg_cfg_5072[508]), + .I1(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_req_h_o[0]), + .I2(plm_link_up_1), + .O(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_h_o_i_m2_i_m3_i_m3_0_0__4005) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_i_m2_i_m3_i_m3_0_4_.INIT = 8'hCA; + LUT3 com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_i_m2_i_m3_i_m3_0_4_ ( + .I0(cfg_cfg_5072[508]), + .I1(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_req_d_o[4]), + .I2(plm_link_up_1), + .O(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_i_m2_i_m3_i_m3_0_4__4014) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_i_m2_i_m3_i_m3_0_0_.INIT = 8'hCA; + LUT3 com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_i_m2_i_m3_i_m3_0_0_ ( + .I0(cfg_cfg_5072[508]), + .I1(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_req_d_o[0]), + .I2(plm_link_up_1), + .O(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_i_m2_i_m3_i_m3_0_0__4011) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_d_con_2_axb_0.INIT = 8'h78; + LUT3 com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_d_con_2_axb_0 ( + .I0(com_tlm_u_tlm_rx_fc_use_cpl), + .I1(com_tlm_u_tlm_rx_fc_use_data[0]), + .I2(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_d_con[0]), + .O(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_d_con_2_axb_0_3896) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_N_9006_i.INIT = 4'hB; + LUT2 com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_N_9006_i ( + .I0(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_req_d_o[7]), + .I1(plm_link_up_1), + .O(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_N_9006_i_4003) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_1_axb_0.INIT = 8'h95; + LUT3_L com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_1_axb_0 ( + .I0(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_i_m2_i_m3_i_m3_0_0__4011), + .I1(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_d_con[0]), + .I2(plm_link_up_1), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_1_axb_0_3897) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_h_o_1_axb_3.INIT = 8'h6F; + LUT3_L com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_h_o_1_axb_3 ( + .I0(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_h_con_i_3__3989), + .I1(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_req_h_o[3]), + .I2(plm_link_up_1), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_h_o_1_axb_3_3898) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_h_o_1_axb_2.INIT = 8'h95; + LUT3_L com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_h_o_1_axb_2 ( + .I0(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_h_o_i_m2_i_m3_i_m3_0_2__4007), + .I1(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_h_con[2]), + .I2(plm_link_up_1), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_h_o_1_axb_2_3899) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_h_o_1_axb_1.INIT = 8'h6F; + LUT3_L com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_h_o_1_axb_1 ( + .I0(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_h_con_i_1__3988), + .I1(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_req_h_o[1]), + .I2(plm_link_up_1), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_h_o_1_axb_1_3900) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_h_o_1_axb_0.INIT = 8'h95; + LUT3_L com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_h_o_1_axb_0 ( + .I0(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_h_o_i_m2_i_m3_i_m3_0_0__4005), + .I1(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_h_con[0]), + .I2(plm_link_up_1), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_h_o_1_axb_0_3901) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_1_axb_11.INIT = 8'h9F; + LUT3_L com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_1_axb_11 ( + .I0(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_d_con[11]), + .I1(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_req_d_o[11]), + .I2(plm_link_up_1), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_1_axb_11_3902) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_1_axb_10.INIT = 8'h6F; + LUT3_L com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_1_axb_10 ( + .I0(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_d_con_i_10__3999), + .I1(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_req_d_o[10]), + .I2(plm_link_up_1), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_1_axb_10_3903) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_1_axb_9.INIT = 8'h6F; + LUT3_L com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_1_axb_9 ( + .I0(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_d_con_i_9__3998), + .I1(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_req_d_o[9]), + .I2(plm_link_up_1), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_1_axb_9_3904) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_1_axb_8.INIT = 8'h6F; + LUT3_L com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_1_axb_8 ( + .I0(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_d_con_i_8__3997), + .I1(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_req_d_o[8]), + .I2(plm_link_up_1), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_1_axb_8_3905) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_1_axb_7.INIT = 8'h90; + LUT3_L com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_1_axb_7 ( + .I0(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_d_con[7]), + .I1(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_req_d_o[7]), + .I2(plm_link_up_1), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_1_axb_7_3906) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_1_axb_6.INIT = 8'h6F; + LUT3_L com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_1_axb_6 ( + .I0(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_d_con_i_6__3996), + .I1(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_req_d_o[6]), + .I2(plm_link_up_1), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_1_axb_6_3907) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_1_axb_5.INIT = 8'h6F; + LUT3_L com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_1_axb_5 ( + .I0(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_d_con_i_5__3995), + .I1(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_req_d_o[5]), + .I2(plm_link_up_1), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_1_axb_5_3908) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_1_axb_4.INIT = 8'h95; + LUT3_L com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_1_axb_4 ( + .I0(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_i_m2_i_m3_i_m3_0_4__4014), + .I1(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_d_con[4]), + .I2(plm_link_up_1), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_1_axb_4_3909) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_1_axb_3.INIT = 8'h6F; + LUT3_L com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_1_axb_3 ( + .I0(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_d_con_i_3__3994), + .I1(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_req_d_o[3]), + .I2(plm_link_up_1), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_1_axb_3_3910) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_1_axb_2.INIT = 8'h6F; + LUT3_L com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_1_axb_2 ( + .I0(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_d_con_i_2__3993), + .I1(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_req_d_o[2]), + .I2(plm_link_up_1), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_1_axb_2_3911) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_1_axb_1.INIT = 8'h6F; + LUT3_L com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_1_axb_1 ( + .I0(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_d_con_i_1__3992), + .I1(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_req_d_o[1]), + .I2(plm_link_up_1), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_1_axb_1_3912) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_2_axb_2.INIT = 16'h7877; + LUT4_L com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_2_axb_2 ( + .I0(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_N_42502_1), + .I1(com_tlm_u_tlm_rx_fc_use_data[2]), + .I2(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_req_d_o[2]), + .I3(plm_link_up_1), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_2_axb_2_3913) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_2_axb_1.INIT = 16'h7877; + LUT4_L com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_2_axb_1 ( + .I0(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_N_42502_1), + .I1(com_tlm_u_tlm_rx_fc_use_data[1]), + .I2(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_req_d_o[1]), + .I3(plm_link_up_1), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_2_axb_1_3914) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_2_axb_0.INIT = 16'h6A55; + LUT4_L com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_2_axb_0 ( + .I0(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_i_m2_i_m3_i_m3_0_0__4011), + .I1(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_N_43127), + .I2(com_tlm_u_tlm_rx_fc_use_data[0]), + .I3(plm_link_up_1), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_2_axb_0_3915) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_h_o_2_axb_7.INIT = 4'hB; + LUT2_L com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_h_o_2_axb_7 ( + .I0(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_req_h_o[7]), + .I1(plm_link_up_1), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_h_o_2_axb_7_3916) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_h_o_2_axb_6.INIT = 4'hB; + LUT2_L com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_h_o_2_axb_6 ( + .I0(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_req_h_o[6]), + .I1(plm_link_up_2), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_h_o_2_axb_6_3917) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_h_o_2_axb_5.INIT = 4'h8; + LUT2_L com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_h_o_2_axb_5 ( + .I0(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_req_h_o[5]), + .I1(plm_link_up_2), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_h_o_2_axb_5_3918) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_h_o_2_axb_4.INIT = 4'hB; + LUT2_L com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_h_o_2_axb_4 ( + .I0(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_req_h_o[4]), + .I1(plm_link_up_2), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_h_o_2_axb_4_3919) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_h_o_2_axb_3.INIT = 4'hB; + LUT2_L com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_h_o_2_axb_3 ( + .I0(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_req_h_o[3]), + .I1(plm_link_up_2), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_h_o_2_axb_3_3920) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_h_o_2_axb_2.INIT = 4'h9; + LUT2_L com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_h_o_2_axb_2 ( + .I0(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_h_o_i_m2_i_m3_i_m3_0_2__4007), + .I1(plm_link_up_2), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_h_o_2_axb_2_3921) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_h_o_2_axb_1.INIT = 4'hB; + LUT2_L com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_h_o_2_axb_1 ( + .I0(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_req_h_o[1]), + .I1(plm_link_up_2), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_h_o_2_axb_1_3922) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_h_o_2_axb_0.INIT = 8'h65; + LUT3_L com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_h_o_2_axb_0 ( + .I0(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_h_o_i_m2_i_m3_i_m3_0_0__4005), + .I1(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_N_43127), + .I2(plm_link_up_2), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_h_o_2_axb_0_3923) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_h_o_1_axb_7.INIT = 8'h9F; + LUT3_L com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_h_o_1_axb_7 ( + .I0(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_h_con[7]), + .I1(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_req_h_o[7]), + .I2(plm_link_up_2), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_h_o_1_axb_7_3924) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_h_o_1_axb_6.INIT = 8'h6F; + LUT3_L com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_h_o_1_axb_6 ( + .I0(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_h_con_i_6__3991), + .I1(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_req_h_o[6]), + .I2(plm_link_up_2), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_h_o_1_axb_6_3925) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_h_o_1_axb_5.INIT = 8'h6A; + LUT3_L com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_h_o_1_axb_5 ( + .I0(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_h_o[5]), + .I1(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_h_con[5]), + .I2(plm_link_up_2), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_h_o_1_axb_5_3926) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_h_o_1_axb_4.INIT = 8'h6F; + LUT3_L com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_h_o_1_axb_4 ( + .I0(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_h_con_i_4__3990), + .I1(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_req_h_o[4]), + .I2(plm_link_up_2), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_h_o_1_axb_4_3927) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_2_axb_11.INIT = 4'hB; + LUT2_L com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_2_axb_11 ( + .I0(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_req_d_o[11]), + .I1(plm_link_up_2), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_2_axb_11_3928) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_2_axb_10.INIT = 4'hB; + LUT2_L com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_2_axb_10 ( + .I0(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_req_d_o[10]), + .I1(plm_link_up_2), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_2_axb_10_3929) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_2_axb_9.INIT = 4'hB; + LUT2_L com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_2_axb_9 ( + .I0(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_req_d_o[9]), + .I1(plm_link_up_2), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_2_axb_9_3930) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_2_axb_8.INIT = 4'hB; + LUT2_L com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_2_axb_8 ( + .I0(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_req_d_o[8]), + .I1(plm_link_up_2), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_2_axb_8_3931) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_2_axb_7.INIT = 4'h8; + LUT2_L com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_2_axb_7 ( + .I0(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_req_d_o[7]), + .I1(plm_link_up_2), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_2_axb_7_3932) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_2_axb_6.INIT = 4'hB; + LUT2_L com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_2_axb_6 ( + .I0(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_req_d_o[6]), + .I1(plm_link_up_2), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_2_axb_6_3933) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_2_axb_5.INIT = 16'h7877; + LUT4_L com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_2_axb_5 ( + .I0(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_N_42502_1), + .I1(com_tlm_u_tlm_rx_fc_use_data[5]), + .I2(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_req_d_o[5]), + .I3(plm_link_up_2), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_2_axb_5_3934) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_2_axb_4.INIT = 16'h6A55; + LUT4_L com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_2_axb_4 ( + .I0(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_i_m2_i_m3_i_m3_0_4__4014), + .I1(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_N_43127), + .I2(com_tlm_u_tlm_rx_fc_use_data[4]), + .I3(plm_link_up_2), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_2_axb_4_3935) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_2_axb_3.INIT = 16'h7877; + LUT4_L com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_2_axb_3 ( + .I0(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_N_42502_1), + .I1(com_tlm_u_tlm_rx_fc_use_data[3]), + .I2(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_req_d_o[3]), + .I3(plm_link_up_2), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_2_axb_3_3936) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_free_d_13_0_a2.INIT = 4'h8; + LUT2_L com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_free_d_13_0_a2 ( + .I0(com_tlm_u_tlm_rx_vc0_fc_free_1data), + .I1(com_tlm_u_tlm_rx_vc0_fc_free_cpl), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_free_d_13) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_free_h_13_0_a2.INIT = 4'h8; + LUT2_L com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_free_h_13_0_a2 ( + .I0(com_tlm_u_tlm_rx_vc0_fc_free_1header), + .I1(com_tlm_u_tlm_rx_vc0_fc_free_cpl), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_free_h_13) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_d_con_2_axb_11.INIT = 4'h2; + LUT1_L com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_d_con_2_axb_11 ( + .I0(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_d_con[11]), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_d_con_2_axb_11_3937) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_d_con_2_axb_10.INIT = 4'h2; + LUT1_L com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_d_con_2_axb_10 ( + .I0(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_d_con[10]), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_d_con_2_axb_10_3938) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_d_con_2_axb_9.INIT = 4'h2; + LUT1_L com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_d_con_2_axb_9 ( + .I0(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_d_con[9]), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_d_con_2_axb_9_3939) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_d_con_2_axb_8.INIT = 4'h2; + LUT1_L com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_d_con_2_axb_8 ( + .I0(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_d_con[8]), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_d_con_2_axb_8_3940) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_d_con_2_axb_7.INIT = 4'h2; + LUT1_L com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_d_con_2_axb_7 ( + .I0(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_d_con[7]), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_d_con_2_axb_7_3941) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_d_con_2_axb_6.INIT = 4'h2; + LUT1_L com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_d_con_2_axb_6 ( + .I0(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_d_con[6]), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_d_con_2_axb_6_3942) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_d_con_2_axb_5.INIT = 8'h78; + LUT3_L com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_d_con_2_axb_5 ( + .I0(com_tlm_u_tlm_rx_fc_use_cpl), + .I1(com_tlm_u_tlm_rx_fc_use_data[5]), + .I2(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_d_con[5]), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_d_con_2_axb_5_3943) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_d_con_2_axb_4.INIT = 8'h78; + LUT3_L com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_d_con_2_axb_4 ( + .I0(com_tlm_u_tlm_rx_fc_use_cpl), + .I1(com_tlm_u_tlm_rx_fc_use_data[4]), + .I2(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_d_con[4]), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_d_con_2_axb_4_3944) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_d_con_2_axb_3.INIT = 8'h78; + LUT3_L com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_d_con_2_axb_3 ( + .I0(com_tlm_u_tlm_rx_fc_use_cpl), + .I1(com_tlm_u_tlm_rx_fc_use_data[3]), + .I2(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_d_con[3]), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_d_con_2_axb_3_3945) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_d_con_2_axb_2.INIT = 8'h78; + LUT3_L com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_d_con_2_axb_2 ( + .I0(com_tlm_u_tlm_rx_fc_use_cpl), + .I1(com_tlm_u_tlm_rx_fc_use_data[2]), + .I2(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_d_con[2]), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_d_con_2_axb_2_3946) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_d_con_2_axb_1.INIT = 8'h78; + LUT3_L com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_d_con_2_axb_1 ( + .I0(com_tlm_u_tlm_rx_fc_use_cpl), + .I1(com_tlm_u_tlm_rx_fc_use_data[1]), + .I2(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_d_con[1]), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_d_con_2_axb_1_3947) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_N_8995_i.INIT = 4'hD; + LUT2 com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_N_8995_i ( + .I0(plm_link_up_1), + .I1(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_req_h_o[5]), + .O(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_N_8995_i_4009) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_unuse_d_0_a2_0_a2_1_5_.INIT = 8'h80; + LUT3 com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_unuse_d_0_a2_0_a2_1_5_ ( + .I0(plm_link_up_1), + .I1(com_tlm_u_tlm_rx_fc_use_cpl), + .I2(com_tlm_u_tlm_rx_fc_unuse), + .O(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_N_42502_1) + ); + FD com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_d_av_o_0_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_1_s_0_3948), + .Q(trn_rfc_cpld_av_5065[0]) + ); + FD com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_h_av_o_3_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_h_o_1_s_3_3949), + .Q(trn_rfc_cplh_av_5064[3]) + ); + FD com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_h_av_o_2_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_h_o_1_s_2_3950), + .Q(trn_rfc_cplh_av_5064[2]) + ); + FD com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_h_av_o_1_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_h_o_1_s_1_3951), + .Q(trn_rfc_cplh_av_5064[1]) + ); + FD com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_h_av_o_0_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_h_o_1_s_0_3952), + .Q(trn_rfc_cplh_av_5064[0]) + ); + FD com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_d_av_o_11_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_1_s_11_3953), + .Q(NlwRenamedSig_OI_trn_rfc_cpld_av[11]) + ); + FD com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_d_av_o_10_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_1_s_10_3954), + .Q(trn_rfc_cpld_av_5065[10]) + ); + FD com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_d_av_o_9_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_1_s_9_3955), + .Q(trn_rfc_cpld_av_5065[9]) + ); + FD com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_d_av_o_8_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_1_s_8_3956), + .Q(trn_rfc_cpld_av_5065[8]) + ); + FD com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_d_av_o_7_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_1_s_7_3957), + .Q(trn_rfc_cpld_av_5065[7]) + ); + FD com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_d_av_o_6_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_1_s_6_3958), + .Q(trn_rfc_cpld_av_5065[6]) + ); + FD com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_d_av_o_5_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_1_s_5_3959), + .Q(trn_rfc_cpld_av_5065[5]) + ); + FD com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_d_av_o_4_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_1_s_4_3960), + .Q(trn_rfc_cpld_av_5065[4]) + ); + FD com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_d_av_o_3_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_1_s_3_3961), + .Q(trn_rfc_cpld_av_5065[3]) + ); + FD com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_d_av_o_2_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_1_s_2_3962), + .Q(trn_rfc_cpld_av_5065[2]) + ); + FD com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_d_av_o_1_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_1_s_1_3963), + .Q(trn_rfc_cpld_av_5065[1]) + ); + FD com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_req_d_o_2_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_2_s_2_3964), + .Q(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_req_d_o[2]) + ); + FD com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_req_d_o_1_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_2_s_1_3965), + .Q(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_req_d_o[1]) + ); + FD com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_req_d_o_0_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_2_s_0_3966), + .Q(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_req_d_o[0]) + ); + FD com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_req_h_o_7_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_h_o_2_s_7_3967), + .Q(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_req_h_o[7]) + ); + FD com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_req_h_o_6_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_h_o_2_s_6_3968), + .Q(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_req_h_o[6]) + ); + FD com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_req_h_o_5_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_h_o_2_s_5_3969), + .Q(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_req_h_o[5]) + ); + FD com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_req_h_o_4_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_h_o_2_s_4_3970), + .Q(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_req_h_o[4]) + ); + FD com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_req_h_o_3_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_h_o_2_s_3_3971), + .Q(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_req_h_o[3]) + ); + FD com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_req_h_o_2_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_h_o_2_s_2_3972), + .Q(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_req_h_o[2]) + ); + FD com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_req_h_o_1_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_h_o_2_s_1_3973), + .Q(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_req_h_o[1]) + ); + FD com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_req_h_o_0_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_h_o_2_s_0_3974), + .Q(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_req_h_o[0]) + ); + FD com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_h_av_o_7_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_h_o_1_s_7_3975), + .Q(NlwRenamedSig_OI_trn_rfc_cplh_av[7]) + ); + FD com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_h_av_o_6_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_h_o_1_s_6_3976), + .Q(trn_rfc_cplh_av_5064[6]) + ); + FD com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_h_av_o_5_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_h_o_1_s_5_3977), + .Q(trn_rfc_cplh_av_5064[5]) + ); + FD com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_h_av_o_4_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_h_o_1_s_4_3978), + .Q(trn_rfc_cplh_av_5064[4]) + ); + FD com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_req_d_o_11_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_2_s_11_3979), + .Q(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_req_d_o[11]) + ); + FD com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_req_d_o_10_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_2_s_10_3980), + .Q(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_req_d_o[10]) + ); + FD com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_req_d_o_9_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_2_s_9_3981), + .Q(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_req_d_o[9]) + ); + FD com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_req_d_o_8_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_2_s_8_3982), + .Q(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_req_d_o[8]) + ); + FD com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_req_d_o_7_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_2_s_7_3983), + .Q(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_req_d_o[7]) + ); + FD com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_req_d_o_6_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_2_s_6_3984), + .Q(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_req_d_o[6]) + ); + FD com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_req_d_o_5_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_2_s_5_3985), + .Q(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_req_d_o[5]) + ); + FD com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_req_d_o_4_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_2_s_4_3986), + .Q(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_req_d_o[4]) + ); + FD com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_req_d_o_3_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_2_s_3_3987), + .Q(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_req_d_o[3]) + ); + INV com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_h_con_i_1_ ( + .I(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_h_con[1]), + .O(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_h_con_i_1__3988) + ); + INV com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_h_con_i_3_ ( + .I(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_h_con[3]), + .O(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_h_con_i_3__3989) + ); + INV com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_h_con_i_4_ ( + .I(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_h_con[4]), + .O(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_h_con_i_4__3990) + ); + INV com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_h_con_i_6_ ( + .I(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_h_con[6]), + .O(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_h_con_i_6__3991) + ); + INV com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_d_con_i_1_ ( + .I(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_d_con[1]), + .O(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_d_con_i_1__3992) + ); + INV com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_d_con_i_2_ ( + .I(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_d_con[2]), + .O(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_d_con_i_2__3993) + ); + INV com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_d_con_i_3_ ( + .I(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_d_con[3]), + .O(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_d_con_i_3__3994) + ); + INV com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_d_con_i_5_ ( + .I(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_d_con[5]), + .O(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_d_con_i_5__3995) + ); + INV com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_d_con_i_6_ ( + .I(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_d_con[6]), + .O(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_d_con_i_6__3996) + ); + INV com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_d_con_i_8_ ( + .I(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_d_con[8]), + .O(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_d_con_i_8__3997) + ); + INV com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_d_con_i_9_ ( + .I(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_d_con[9]), + .O(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_d_con_i_9__3998) + ); + INV com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_d_con_i_10_ ( + .I(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_d_con[10]), + .O(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_d_con_i_10__3999) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_h_con_qxu_0_0_.INIT = 4'h2; + LUT1_L com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_h_con_qxu_0_0_ ( + .I0(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_h_con[0]), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_h_con_qxu[0]) + ); + MULT_AND com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_1_cry_0_ma ( + .I0(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_i_m2_i_m3_i_m3_0_0__4011), + .I1(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_VCC_4013), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_1_cry_0_ma_4000) + ); + MULT_AND com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_1_cry_4_ma ( + .I0(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_i_m2_i_m3_i_m3_0_4__4014), + .I1(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_VCC_4013), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_1_cry_4_ma_4001) + ); + MULT_AND com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_1_cry_7_ma ( + .I0(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_N_9006_i_4003), + .I1(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_VCC_4013), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_1_cry_7_ma_4002) + ); + MULT_AND com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_h_o_1_cry_0_ma ( + .I0(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_h_o_i_m2_i_m3_i_m3_0_0__4005), + .I1(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_VCC_4013), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_h_o_1_cry_0_ma_4004) + ); + MULT_AND com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_h_o_1_cry_2_ma ( + .I0(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_h_o_i_m2_i_m3_i_m3_0_2__4007), + .I1(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_VCC_4013), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_h_o_1_cry_2_ma_4006) + ); + MULT_AND com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_h_o_1_cry_5_ma ( + .I0(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_N_8995_i_4009), + .I1(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_VCC_4013), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_h_o_1_cry_5_ma_4008) + ); + MULT_AND com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_2_cry_0_ma ( + .I0(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_i_m2_i_m3_i_m3_0_0__4011), + .I1(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_VCC_4013), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_2_cry_0_ma_4010) + ); + MULT_AND com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_2_cry_4_ma ( + .I0(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_i_m2_i_m3_i_m3_0_4__4014), + .I1(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_VCC_4013), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_2_cry_4_ma_4012) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_h_con_qxu_0_7_.INIT = 4'h2; + LUT1_L com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_h_con_qxu_0_7_ ( + .I0(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_h_con[7]), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_h_con_qxu[7]) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_h_con_qxu_0_6_.INIT = 4'h2; + LUT1_L com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_h_con_qxu_0_6_ ( + .I0(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_h_con[6]), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_h_con_qxu[6]) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_h_con_qxu_0_5_.INIT = 4'h2; + LUT1_L com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_h_con_qxu_0_5_ ( + .I0(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_h_con[5]), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_h_con_qxu[5]) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_h_con_qxu_0_4_.INIT = 4'h2; + LUT1_L com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_h_con_qxu_0_4_ ( + .I0(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_h_con[4]), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_h_con_qxu[4]) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_h_con_qxu_0_3_.INIT = 4'h2; + LUT1_L com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_h_con_qxu_0_3_ ( + .I0(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_h_con[3]), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_h_con_qxu[3]) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_h_con_qxu_0_2_.INIT = 4'h2; + LUT1_L com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_h_con_qxu_0_2_ ( + .I0(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_h_con[2]), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_h_con_qxu[2]) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_h_con_qxu_0_1_.INIT = 4'h2; + LUT1_L com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_h_con_qxu_0_1_ ( + .I0(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_h_con[1]), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_h_con_qxu[1]) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_h_con_s_0_.INIT = 4'h1; + LUT1_L com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_h_con_s_0_ ( + .I0(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_h_con_qxu[0]), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_h_con_s[0]) + ); + VCC com_tlm_u_tlm_rx_data_snk_VCC ( + .P(com_tlm_u_tlm_rx_data_snk_VCC_4101) + ); + GND com_tlm_u_tlm_rx_data_snk_GND ( + .G(com_tlm_u_tlm_rx_data_snk_GND_4100) + ); + FDR com_tlm_u_tlm_rx_data_snk_src_rdy_o ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_src_rdy_o_8), + .Q(com_tlm_u_tlm_rx_ds_src_rdy), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_rx_data_snk_stat_tlp_ep_o ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_stat_tlp_ep_o_5_4066), + .Q(com_cmmt_stat_tlp_rx_ep), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_rx_data_snk_stat_tlp_cpl_ur_o ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_stat_tlp_cpl_ur_o_5_4064), + .Q(com_cmmt_stat_tlp_rx_cpl_ur), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_rx_data_snk_stat_tlp_cpl_ep_o ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_stat_tlp_cpl_ep_o_5_4062), + .Q(com_cmmt_stat_tlp_rx_cpl_ep), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_rx_data_snk_stat_tlp_cpl_abort_o ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_stat_tlp_cpl_abort_o_5_4060), + .Q(com_cmmt_stat_tlp_rx_cpl_abort), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_rx_data_snk_dsc_o ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_dsc_o_5), + .Q(com_tlm_u_tlm_rx_ds_dsc), + .R(plm_link_up_i) + ); + FDRE com_tlm_u_tlm_rx_data_snk_cur_byte_ct_1dw_0_ ( + .CE(com_tlm_u_tlm_rx_data_snk_latch_2nd_dword), + .C(NlwRenamedSig_OI_trn_clk), + .D(N_14703_i), + .Q(com_tlm_u_tlm_rx_data_snk_cur_byte_ct_1dw[0]), + .R(plm_link_up_i) + ); + FDRE com_tlm_u_tlm_rx_data_snk_cur_byte_ct_1dw_1_ ( + .CE(com_tlm_u_tlm_rx_data_snk_latch_2nd_dword), + .C(NlwRenamedSig_OI_trn_clk), + .D(N_14705_i), + .Q(com_tlm_u_tlm_rx_data_snk_cur_byte_ct_1dw[1]), + .R(plm_link_up_i) + ); + FDRE com_tlm_u_tlm_rx_data_snk_cur_byte_ct_1dw_2_ ( + .CE(com_tlm_u_tlm_rx_data_snk_latch_2nd_dword), + .C(NlwRenamedSig_OI_trn_clk), + .D(N_36389_i), + .Q(com_tlm_u_tlm_rx_data_snk_cur_byte_ct_1dw[2]), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_rx_data_snk_fc_unuse_o ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_fc_unuse_o_5_4059), + .Q(com_tlm_u_tlm_rx_fc_unuse), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_rx_data_snk_cur_drop ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_next_cur_drop_4102), + .Q(com_tlm_u_tlm_rx_data_snk_cur_drop_4034), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_rx_data_snk_fc_use_p_o ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_fc_use_p_o_5_4058), + .Q(com_tlm_u_tlm_rx_fc_use_p), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_rx_data_snk_fc_use_np_o ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_fc_use_np_o_5_4057), + .Q(com_tlm_u_tlm_rx_fc_use_np), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_rx_data_snk_fc_use_cpl_o ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_fc_use_cpl_o_5_4056), + .Q(com_tlm_u_tlm_rx_fc_use_cpl), + .R(plm_link_up_i) + ); + FDRSE com_tlm_u_tlm_rx_data_snk_vc_hit_o ( + .CE(com_tlm_u_tlm_rx_data_snk_GND_4100), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_GND_4100), + .Q(com_lnk_tfc_vc_hit), + .R(plm_link_up_i), + .S(com_tlm_u_tlm_rx_wen_aux_oq_3) + ); + FDS com_tlm_u_tlm_rx_data_snk_rem_q_1_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_N_69055_i_4055), + .Q(com_tlm_u_tlm_rx_data_snk_rem_q_1__4098), + .S(plm_link_up_i) + ); + FDRE com_tlm_u_tlm_rx_data_snk_cur_first_be_adj_0_ ( + .CE(com_tlm_u_tlm_rx_data_snk_latch_2nd_dword), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_N_68789_i_4054), + .Q(com_tlm_u_tlm_rx_data_snk_cur_first_be_adj[0]), + .R(plm_link_up_i) + ); + FDRE com_tlm_u_tlm_rx_data_snk_cur_first_be_adj_1_ ( + .CE(com_tlm_u_tlm_rx_data_snk_latch_2nd_dword), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_N_14699_i), + .Q(com_tlm_u_tlm_rx_data_snk_cur_first_be_adj[1]), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_rx_data_snk_err_tlp_ur_o ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_err_tlp_ur_o_3_4053), + .Q(com_cmmt_err_tlp_ur), + .R(plm_link_up_i) + ); + FDRE com_tlm_u_tlm_rx_data_snk_remove_lastword ( + .CE(com_tlm_u_tlm_rx_data_snk_N_9484_i_4030), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_remove_lastword_6), + .Q(com_tlm_u_tlm_rx_data_snk_remove_lastword_4050), + .R(plm_link_up_i) + ); + FDRE com_tlm_u_tlm_rx_data_snk_cur_cpl_ur ( + .CE(com_tlm_u_tlm_rx_data_snk_latch_1st_dword_q2), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_cur_cpl_ur_6), + .Q(com_tlm_u_tlm_rx_data_snk_cur_cpl_ur_4065), + .R(plm_link_up_i) + ); + FDRE com_tlm_u_tlm_rx_data_snk_cur_cpl_abort ( + .CE(com_tlm_u_tlm_rx_data_snk_latch_1st_dword_q2), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_cur_cpl_abort_6), + .Q(com_tlm_u_tlm_rx_data_snk_cur_cpl_abort_4061), + .R(plm_link_up_i) + ); + FDS com_tlm_u_tlm_rx_data_snk_rem_o ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_rem_o_5), + .Q(com_tlm_u_tlm_rx_ds_rem), + .S(plm_link_up_i) + ); + FDR com_tlm_u_tlm_rx_data_snk_eof_o ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_eof_o_5), + .Q(com_tlm_u_tlm_rx_ds_eof), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_rx_data_snk_src_rdy_q_1_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_N_13363_i), + .Q(com_tlm_u_tlm_rx_data_snk_src_rdy_q_1__4099), + .R(plm_link_up_i) + ); + FDRE com_tlm_u_tlm_rx_data_snk_packet_ip ( + .CE(com_lnk_rsrc_rdy_n_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_N_13361_i), + .Q(com_tlm_u_tlm_rx_data_snk_packet_ip_4048), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_rx_data_snk_err_tlp_malformed_o ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_err_tlp_malformed_o_3_4049), + .Q(com_tlm_cmmt_err_tlp_malformed), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_rx_data_snk_eof_nd_q_1_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_eof_nd_q_3[1]), + .Q(com_tlm_u_tlm_rx_data_snk_eof_nd_q_1__4096), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_rx_data_snk_dsc_q_1_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_dsc_q_3[1]), + .Q(com_tlm_u_tlm_rx_data_snk_dsc_q_1__4095), + .R(plm_link_up_i) + ); + FDRE com_tlm_u_tlm_rx_data_snk_cur_cpl_ep ( + .CE(com_tlm_u_tlm_rx_data_snk_latch_1st_dword_q2), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_cur_cpl_ep_6), + .Q(com_tlm_u_tlm_rx_data_snk_cur_cpl_ep_4063), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_rx_data_snk_sof_q_1_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_sof_q_3[1]), + .Q(com_tlm_u_tlm_rx_data_snk_sof_q_1__4097), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_rx_data_snk_eof_q_1_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_N_36411_i), + .Q(com_tlm_u_tlm_rx_data_snk_eof_q_1__4073), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_rx_data_snk_sof_o ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_sof_q_5__4070), + .Q(com_tlm_u_tlm_rx_ds_sof), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_rx_data_snk_latch_1st_dword_q3 ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_latch_1st_dword_q2), + .Q(com_tlm_u_tlm_rx_data_snk_latch_1st_dword_q3_4015), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_rx_data_snk_err_tlp_p_o ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_ds_np_i_4047), + .Q(com_cmmt_err_tlp_p_cpl), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_rx_data_snk_latch_1st_dword_q4 ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_latch_1st_dword_q3_4015), + .Q(com_tlm_u_tlm_rx_data_snk_latch_1st_dword_q4_4085), + .R(plm_link_up_i) + ); + FDRE com_tlm_u_tlm_rx_data_snk_pwr_mgmt_mode_on ( + .CE(com_lnk_rsof_n_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmmt_ppm_suspend_req_n_i), + .Q(com_tlm_u_tlm_rx_data_snk_pwr_mgmt_mode_on_4016), + .R(plm_link_up_i) + ); + MUXCY_L com_tlm_u_tlm_rx_data_snk_un4_cur_byte_ct_cry_0 ( + .CI(com_tlm_u_tlm_rx_data_snk_GND_4100), + .DI(com_tlm_u_tlm_rx_data_snk_VCC_4101), + .LO(com_tlm_u_tlm_rx_data_snk_un4_cur_byte_ct_cry_0_4017), + .S(com_tlm_u_tlm_rx_data_snk_un4_cur_byte_ct_cry_0_sf_4113) + ); + MUXCY_L com_tlm_u_tlm_rx_data_snk_un4_cur_byte_ct_cry_1 ( + .CI(com_tlm_u_tlm_rx_data_snk_un4_cur_byte_ct_cry_0_4017), + .DI(com_tlm_u_tlm_rx_data_snk_GND_4100), + .LO(com_tlm_u_tlm_rx_data_snk_un4_cur_byte_ct_cry_1_4018), + .S(com_tlm_u_tlm_rx_data_snk_un4_cur_byte_ct_axb_1_4112) + ); + XORCY com_tlm_u_tlm_rx_data_snk_un4_cur_byte_ct_s_1 ( + .CI(com_tlm_u_tlm_rx_data_snk_un4_cur_byte_ct_cry_0_4017), + .LI(com_tlm_u_tlm_rx_data_snk_un4_cur_byte_ct_axb_1_4112), + .O(com_tlm_u_tlm_rx_data_snk_un4_cur_byte_ct_s_1_4038) + ); + MUXCY_L com_tlm_u_tlm_rx_data_snk_un4_cur_byte_ct_cry_2 ( + .CI(com_tlm_u_tlm_rx_data_snk_un4_cur_byte_ct_cry_1_4018), + .DI(com_tlm_u_tlm_rx_data_snk_cur_length_0__2), + .LO(com_tlm_u_tlm_rx_data_snk_un4_cur_byte_ct_cry_2_4019), + .S(com_tlm_u_tlm_rx_data_snk_un4_cur_byte_ct_axb_2_4111) + ); + XORCY com_tlm_u_tlm_rx_data_snk_un4_cur_byte_ct_s_2 ( + .CI(com_tlm_u_tlm_rx_data_snk_un4_cur_byte_ct_cry_1_4018), + .LI(com_tlm_u_tlm_rx_data_snk_un4_cur_byte_ct_axb_2_4111), + .O(com_tlm_u_tlm_rx_data_snk_un4_cur_byte_ct_s_2_4037) + ); + MUXCY_L com_tlm_u_tlm_rx_data_snk_un4_cur_byte_ct_cry_3 ( + .CI(com_tlm_u_tlm_rx_data_snk_un4_cur_byte_ct_cry_2_4019), + .DI(com_tlm_u_tlm_rx_data_snk_VCC_4101), + .LO(com_tlm_u_tlm_rx_data_snk_un4_cur_byte_ct_cry_3_4020), + .S(com_tlm_u_tlm_rx_data_snk_un4_cur_byte_ct_s_3_sf_4110) + ); + XORCY com_tlm_u_tlm_rx_data_snk_un4_cur_byte_ct_s_3 ( + .CI(com_tlm_u_tlm_rx_data_snk_un4_cur_byte_ct_cry_2_4019), + .LI(com_tlm_u_tlm_rx_data_snk_un4_cur_byte_ct_s_3_sf_4110), + .O(com_tlm_u_tlm_rx_data_snk_un4_cur_byte_ct_s_3_4036) + ); + MUXCY_L com_tlm_u_tlm_rx_data_snk_un4_cur_byte_ct_cry_4 ( + .CI(com_tlm_u_tlm_rx_data_snk_un4_cur_byte_ct_cry_3_4020), + .DI(com_tlm_u_tlm_rx_data_snk_VCC_4101), + .LO(com_tlm_u_tlm_rx_data_snk_un4_cur_byte_ct_cry_4_4021), + .S(com_tlm_u_tlm_rx_data_snk_un4_cur_byte_ct_s_4_sf_4109) + ); + XORCY com_tlm_u_tlm_rx_data_snk_un4_cur_byte_ct_s_4 ( + .CI(com_tlm_u_tlm_rx_data_snk_un4_cur_byte_ct_cry_3_4020), + .LI(com_tlm_u_tlm_rx_data_snk_un4_cur_byte_ct_s_4_sf_4109), + .O(com_tlm_u_tlm_rx_data_snk_un4_cur_byte_ct_s_4_4046) + ); + MUXCY_L com_tlm_u_tlm_rx_data_snk_un4_cur_byte_ct_cry_5 ( + .CI(com_tlm_u_tlm_rx_data_snk_un4_cur_byte_ct_cry_4_4021), + .DI(com_tlm_u_tlm_rx_data_snk_VCC_4101), + .LO(com_tlm_u_tlm_rx_data_snk_un4_cur_byte_ct_cry_5_4022), + .S(com_tlm_u_tlm_rx_data_snk_un4_cur_byte_ct_s_5_sf_4108) + ); + XORCY com_tlm_u_tlm_rx_data_snk_un4_cur_byte_ct_s_5 ( + .CI(com_tlm_u_tlm_rx_data_snk_un4_cur_byte_ct_cry_4_4021), + .LI(com_tlm_u_tlm_rx_data_snk_un4_cur_byte_ct_s_5_sf_4108), + .O(com_tlm_u_tlm_rx_data_snk_un4_cur_byte_ct_s_5_4045) + ); + MUXCY_L com_tlm_u_tlm_rx_data_snk_un4_cur_byte_ct_cry_6 ( + .CI(com_tlm_u_tlm_rx_data_snk_un4_cur_byte_ct_cry_5_4022), + .DI(com_tlm_u_tlm_rx_data_snk_VCC_4101), + .LO(com_tlm_u_tlm_rx_data_snk_un4_cur_byte_ct_cry_6_4023), + .S(com_tlm_u_tlm_rx_data_snk_un4_cur_byte_ct_s_6_sf_4107) + ); + XORCY com_tlm_u_tlm_rx_data_snk_un4_cur_byte_ct_s_6 ( + .CI(com_tlm_u_tlm_rx_data_snk_un4_cur_byte_ct_cry_5_4022), + .LI(com_tlm_u_tlm_rx_data_snk_un4_cur_byte_ct_s_6_sf_4107), + .O(com_tlm_u_tlm_rx_data_snk_un4_cur_byte_ct_s_6_4044) + ); + MUXCY_L com_tlm_u_tlm_rx_data_snk_un4_cur_byte_ct_cry_7 ( + .CI(com_tlm_u_tlm_rx_data_snk_un4_cur_byte_ct_cry_6_4023), + .DI(com_tlm_u_tlm_rx_data_snk_VCC_4101), + .LO(com_tlm_u_tlm_rx_data_snk_un4_cur_byte_ct_cry_7_4024), + .S(com_tlm_u_tlm_rx_data_snk_un4_cur_byte_ct_s_7_sf_4106) + ); + XORCY com_tlm_u_tlm_rx_data_snk_un4_cur_byte_ct_s_7 ( + .CI(com_tlm_u_tlm_rx_data_snk_un4_cur_byte_ct_cry_6_4023), + .LI(com_tlm_u_tlm_rx_data_snk_un4_cur_byte_ct_s_7_sf_4106), + .O(com_tlm_u_tlm_rx_data_snk_un4_cur_byte_ct_s_7_4043) + ); + MUXCY_L com_tlm_u_tlm_rx_data_snk_un4_cur_byte_ct_cry_8 ( + .CI(com_tlm_u_tlm_rx_data_snk_un4_cur_byte_ct_cry_7_4024), + .DI(com_tlm_u_tlm_rx_data_snk_VCC_4101), + .LO(com_tlm_u_tlm_rx_data_snk_un4_cur_byte_ct_cry_8_4025), + .S(com_tlm_u_tlm_rx_data_snk_un4_cur_byte_ct_s_8_sf_4105) + ); + XORCY com_tlm_u_tlm_rx_data_snk_un4_cur_byte_ct_s_8 ( + .CI(com_tlm_u_tlm_rx_data_snk_un4_cur_byte_ct_cry_7_4024), + .LI(com_tlm_u_tlm_rx_data_snk_un4_cur_byte_ct_s_8_sf_4105), + .O(com_tlm_u_tlm_rx_data_snk_un4_cur_byte_ct_s_8_4042) + ); + MUXCY_L com_tlm_u_tlm_rx_data_snk_un4_cur_byte_ct_cry_9 ( + .CI(com_tlm_u_tlm_rx_data_snk_un4_cur_byte_ct_cry_8_4025), + .DI(com_tlm_u_tlm_rx_data_snk_VCC_4101), + .LO(com_tlm_u_tlm_rx_data_snk_un4_cur_byte_ct_cry_9_4026), + .S(com_tlm_u_tlm_rx_data_snk_un4_cur_byte_ct_s_9_sf_4104) + ); + XORCY com_tlm_u_tlm_rx_data_snk_un4_cur_byte_ct_s_9 ( + .CI(com_tlm_u_tlm_rx_data_snk_un4_cur_byte_ct_cry_8_4025), + .LI(com_tlm_u_tlm_rx_data_snk_un4_cur_byte_ct_s_9_sf_4104), + .O(com_tlm_u_tlm_rx_data_snk_un4_cur_byte_ct_s_9_4041) + ); + MUXCY_L com_tlm_u_tlm_rx_data_snk_un4_cur_byte_ct_cry_10 ( + .CI(com_tlm_u_tlm_rx_data_snk_un4_cur_byte_ct_cry_9_4026), + .DI(com_tlm_u_tlm_rx_data_snk_VCC_4101), + .LO(com_tlm_u_tlm_rx_data_snk_un4_cur_byte_ct_cry_10_4027), + .S(com_tlm_u_tlm_rx_data_snk_un4_cur_byte_ct_s_10_sf_4103) + ); + XORCY com_tlm_u_tlm_rx_data_snk_un4_cur_byte_ct_s_10 ( + .CI(com_tlm_u_tlm_rx_data_snk_un4_cur_byte_ct_cry_9_4026), + .LI(com_tlm_u_tlm_rx_data_snk_un4_cur_byte_ct_s_10_sf_4103), + .O(com_tlm_u_tlm_rx_data_snk_un4_cur_byte_ct_s_10_4040) + ); + XORCY com_tlm_u_tlm_rx_data_snk_un4_cur_byte_ct_s_11 ( + .CI(com_tlm_u_tlm_rx_data_snk_un4_cur_byte_ct_cry_10_4027), + .LI(com_tlm_u_tlm_rx_data_snk_un4_cur_byte_ct_s_11_sf_4029), + .O(com_tlm_u_tlm_rx_data_snk_un4_cur_byte_ct_s_11_4039) + ); + FDR com_tlm_u_tlm_rx_data_snk_latch_1st_dword_q1 ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_latch_2nd_dword), + .Q(com_tlm_u_tlm_rx_data_snk_latch_1st_dword_q1_4028), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_rx_data_snk_bar_src_rdy_o ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_sof_q_4_), + .Q(com_tlm_u_tlm_rx_ds_bar_src_rdy), + .R(plm_link_up_i) + ); + defparam com_tlm_u_tlm_rx_data_snk_cur_rem_0_sqmuxa_0_a2_0_a2_0_a2.INIT = 4'h4; + LUT2 com_tlm_u_tlm_rx_data_snk_cur_rem_0_sqmuxa_0_a2_0_a2_0_a2 ( + .I0(com_lnk_reof_n), + .I1(plm_link_up_1), + .O(com_tlm_u_tlm_rx_data_snk_cur_rem_0_sqmuxa) + ); + defparam com_tlm_u_tlm_rx_data_snk_packet_ip_3_i_0_0_a2.INIT = 4'h2; + LUT2 com_tlm_u_tlm_rx_data_snk_packet_ip_3_i_0_0_a2 ( + .I0(com_lnk_rsof_n), + .I1(com_tlm_u_tlm_rx_data_snk_packet_ip_4048), + .O(com_tlm_u_tlm_rx_data_snk_N_36490) + ); + defparam com_tlm_u_tlm_rx_data_snk_un1_eof_q_2_1.INIT = 4'h1; + LUT2 com_tlm_u_tlm_rx_data_snk_un1_eof_q_2_1 ( + .I0(com_tlm_u_tlm_rx_data_snk_malformed), + .I1(com_tlm_u_tlm_rx_data_snk_tlp_ur), + .O(com_tlm_u_tlm_rx_data_snk_un1_eof_q_2_1_4031) + ); + defparam com_tlm_u_tlm_rx_data_snk_first_be_missing_0_0_a2_0_.INIT = 4'h4; + LUT2 com_tlm_u_tlm_rx_data_snk_first_be_missing_0_0_a2_0_ ( + .I0(com_lnk_rd[0]), + .I1(com_lnk_rd[1]), + .O(com_tlm_u_tlm_rx_data_snk_N_36447) + ); + defparam com_tlm_u_tlm_rx_data_snk_un1_cur_fulltype_oh37_0_0_o3_0.INIT = 4'h1; + LUT2 com_tlm_u_tlm_rx_data_snk_un1_cur_fulltype_oh37_0_0_o3_0 ( + .I0(com_lnk_rd_5077[56]), + .I1(com_lnk_rd_5077[61]), + .O(com_tlm_u_tlm_rx_data_snk_N_36409_i) + ); + defparam com_tlm_u_tlm_rx_data_snk_cur_fulltype_mem12_0_0_o2.INIT = 4'h1; + LUT2 com_tlm_u_tlm_rx_data_snk_cur_fulltype_mem12_0_0_o2 ( + .I0(com_lnk_rd_5077[57]), + .I1(com_lnk_rd_5077[59]), + .O(com_tlm_u_tlm_rx_data_snk_N_36407_i) + ); + defparam com_tlm_u_tlm_rx_data_snk_un1_cur_fulltype_oh37_0_0_o3.INIT = 4'h1; + LUT2 com_tlm_u_tlm_rx_data_snk_un1_cur_fulltype_oh37_0_0_o3 ( + .I0(com_lnk_rd_5077[58]), + .I1(com_lnk_rd_5077[60]), + .O(com_tlm_u_tlm_rx_data_snk_N_36393_i) + ); + defparam com_tlm_u_tlm_rx_data_snk_latch_1st_dword_q1c.INIT = 4'h1; + LUT2 com_tlm_u_tlm_rx_data_snk_latch_1st_dword_q1c ( + .I0(com_lnk_rsof_n), + .I1(com_lnk_rsrc_rdy_n), + .O(com_tlm_u_tlm_rx_data_snk_latch_2nd_dword) + ); + defparam com_tlm_u_tlm_rx_data_snk_un4_cur_byte_ct_s_11_sf.INIT = 4'h1; + LUT1 com_tlm_u_tlm_rx_data_snk_un4_cur_byte_ct_s_11_sf ( + .I0(com_tlm_u_tlm_rx_data_snk_cur_length_9__14), + .O(com_tlm_u_tlm_rx_data_snk_un4_cur_byte_ct_s_11_sf_4029) + ); + defparam com_tlm_u_tlm_rx_data_snk_N_9484_i.INIT = 4'hE; + LUT2 com_tlm_u_tlm_rx_data_snk_N_9484_i ( + .I0(com_tlm_u_tlm_rx_data_snk_eof_q_2__4074), + .I1(com_tlm_u_tlm_rx_ds_eof), + .O(com_tlm_u_tlm_rx_data_snk_N_9484_i_4030) + ); + defparam com_tlm_u_tlm_rx_data_snk_last_be_missing_i_0_1_.INIT = 8'h01; + LUT3 com_tlm_u_tlm_rx_data_snk_last_be_missing_i_0_1_ ( + .I0(com_tlm_u_tlm_rx_data_snk_N_36443_i), + .I1(com_lnk_rd[6]), + .I2(com_lnk_rd_5077[7]), + .O(com_tlm_u_tlm_rx_data_snk_N_14696_i) + ); + defparam com_tlm_u_tlm_rx_data_snk_un1_src_rdy_o.INIT = 8'h40; + LUT3 com_tlm_u_tlm_rx_data_snk_un1_src_rdy_o ( + .I0(com_tlm_u_tlm_rx_ds_dsc), + .I1(com_tlm_u_tlm_rx_ds_eof), + .I2(com_tlm_u_tlm_rx_ds_src_rdy), + .O(com_tlm_u_tlm_rx_wen_aux_oq_3) + ); + defparam com_tlm_u_tlm_rx_data_snk_un1_cur_fulltype_oh37_0_0_o2.INIT = 8'h2A; + LUT3 com_tlm_u_tlm_rx_data_snk_un1_cur_fulltype_oh37_0_0_o2 ( + .I0(com_tlm_u_tlm_rx_data_snk_N_36393_i), + .I1(com_lnk_rd_5077[56]), + .I2(com_lnk_rd_5077[62]), + .O(com_tlm_u_tlm_rx_data_snk_N_36395_i) + ); + defparam com_tlm_u_tlm_rx_data_snk_first_be_missing_i_0_1_.INIT = 16'h1110; + LUT4 com_tlm_u_tlm_rx_data_snk_first_be_missing_i_0_1_ ( + .I0(com_lnk_rd[0]), + .I1(com_lnk_rd[1]), + .I2(com_lnk_rd[2]), + .I3(com_lnk_rd[3]), + .O(com_tlm_u_tlm_rx_data_snk_N_14699_i) + ); + defparam com_tlm_u_tlm_rx_data_snk_cur_length1_2_0_a2_0_a2_0_a2_0_a2_4.INIT = 16'h0001; + LUT4 com_tlm_u_tlm_rx_data_snk_cur_length1_2_0_a2_0_a2_0_a2_0_a2_4 ( + .I0(com_lnk_rd_5077[34]), + .I1(com_lnk_rd_5077[35]), + .I2(com_lnk_rd_5077[36]), + .I3(com_lnk_rd_5077[37]), + .O(com_tlm_u_tlm_rx_data_snk_cur_length1_2_0_a2_0_a2_0_a2_0_a2_4_4052) + ); + defparam com_tlm_u_tlm_rx_data_snk_cur_length1_2_0_a2_0_a2_0_a2_0_a2_5.INIT = 16'h0002; + LUT4_L com_tlm_u_tlm_rx_data_snk_cur_length1_2_0_a2_0_a2_0_a2_0_a2_5 ( + .I0(com_lnk_rd_5077[32]), + .I1(com_lnk_rd_5077[33]), + .I2(com_lnk_rd_5077[38]), + .I3(com_lnk_rd_5077[39]), + .LO(com_tlm_u_tlm_rx_data_snk_cur_length1_2_0_a2_0_a2_0_a2_0_a2_5_4051) + ); + defparam com_tlm_u_tlm_rx_data_snk_first_be_missing_0_0_0_.INIT = 16'h5455; + LUT4 com_tlm_u_tlm_rx_data_snk_first_be_missing_0_0_0_ ( + .I0(com_tlm_u_tlm_rx_data_snk_N_36447), + .I1(com_lnk_rd[0]), + .I2(com_lnk_rd[2]), + .I3(com_lnk_rd[3]), + .O(com_tlm_u_tlm_rx_data_snk_first_be_missing_0_0[0]) + ); + defparam com_tlm_u_tlm_rx_data_snk_last_be_missing_i_0_0_.INIT = 8'h0E; + LUT3 com_tlm_u_tlm_rx_data_snk_last_be_missing_i_0_0_ ( + .I0(com_tlm_u_tlm_rx_data_snk_N_36390_i), + .I1(com_lnk_rd[6]), + .I2(com_lnk_rd_5077[7]), + .O(com_tlm_u_tlm_rx_data_snk_N_14694_i) + ); + defparam com_tlm_u_tlm_rx_data_snk_cur_fulltype_oh40_0_a2_0_a2_1.INIT = 8'h08; + LUT3 com_tlm_u_tlm_rx_data_snk_cur_fulltype_oh40_0_a2_0_a2_1 ( + .I0(com_tlm_u_tlm_rx_data_snk_N_36393_i), + .I1(com_lnk_rd_5077[57]), + .I2(com_lnk_rd_5077[61]), + .O(com_tlm_u_tlm_rx_data_snk_cur_fulltype_oh40_1) + ); + defparam com_tlm_u_tlm_rx_data_snk_next_cur_drop_2.INIT = 16'h0100; + LUT4 com_tlm_u_tlm_rx_data_snk_next_cur_drop_2 ( + .I0(com_tlm_u_tlm_rx_data_snk_cur_hp_msg_detect), + .I1(com_tlm_u_tlm_rx_data_snk_cur_pm_msg_detect), + .I2(com_tlm_u_tlm_rx_data_snk_tlp_uc), + .I3(com_tlm_u_tlm_rx_data_snk_un1_eof_q_2_1_4031), + .O(com_tlm_u_tlm_rx_data_snk_N_9481) + ); + defparam com_tlm_u_tlm_rx_data_snk_cur_byte_ct_6_1_a2_0_a2_0_a3_1_3_.INIT = 8'h08; + LUT3 com_tlm_u_tlm_rx_data_snk_cur_byte_ct_6_1_a2_0_a2_0_a3_1_3_ ( + .I0(com_tlm_u_tlm_rx_data_snk_N_36382_i), + .I1(com_tlm_u_tlm_rx_data_snk_N_36397_i), + .I2(com_tlm_u_tlm_rx_data_snk_cur_fulltype[6]), + .O(com_tlm_u_tlm_rx_data_snk_N_36645_1) + ); + defparam com_tlm_u_tlm_rx_data_snk_src_rdy_o_8_u_0_am.INIT = 8'h8C; + LUT3 com_tlm_u_tlm_rx_data_snk_src_rdy_o_8_u_0_am ( + .I0(com_tlm_u_tlm_rx_data_snk_sof_q_5__4070), + .I1(com_tlm_u_tlm_rx_data_snk_src_rdy_q_5__4076), + .I2(com_tlm_u_tlm_rx_ds_eof), + .O(com_tlm_u_tlm_rx_data_snk_src_rdy_o_8_u_0_am_4033) + ); + defparam com_tlm_u_tlm_rx_data_snk_src_rdy_o_8_u_0_bm.INIT = 8'h4C; + LUT3 com_tlm_u_tlm_rx_data_snk_src_rdy_o_8_u_0_bm ( + .I0(com_tlm_u_tlm_rx_data_snk_rem_q_4_), + .I1(com_tlm_u_tlm_rx_data_snk_src_rdy_q_4_), + .I2(com_tlm_u_tlm_rx_ds_eof), + .O(com_tlm_u_tlm_rx_data_snk_src_rdy_o_8_u_0_bm_4032) + ); + MUXF5 com_tlm_u_tlm_rx_data_snk_src_rdy_o_8_u_0 ( + .I0(com_tlm_u_tlm_rx_data_snk_src_rdy_o_8_u_0_am_4033), + .I1(com_tlm_u_tlm_rx_data_snk_src_rdy_o_8_u_0_bm_4032), + .O(com_tlm_u_tlm_rx_data_snk_src_rdy_o_8), + .S(com_tlm_u_tlm_rx_data_snk_remove_lastword_4050) + ); + defparam com_tlm_u_tlm_rx_data_snk_dsc_o_5_0_am.INIT = 8'hEC; + LUT3 com_tlm_u_tlm_rx_data_snk_dsc_o_5_0_am ( + .I0(com_tlm_u_tlm_rx_data_snk_cur_drop_4034), + .I1(com_tlm_u_tlm_rx_data_snk_dsc_q_5__4075), + .I2(com_tlm_u_tlm_rx_data_snk_eof_q_5__4072), + .O(com_tlm_u_tlm_rx_data_snk_dsc_o_5_0_am_4035) + ); + MUXF5 com_tlm_u_tlm_rx_data_snk_dsc_o_5_0 ( + .I0(com_tlm_u_tlm_rx_data_snk_dsc_o_5_0_am_4035), + .I1(com_tlm_u_tlm_rx_data_snk_dsc_o_5_0_bm_4067), + .O(com_tlm_u_tlm_rx_data_snk_dsc_o_5), + .S(com_tlm_u_tlm_rx_data_snk_remove_lastword_4050) + ); + defparam com_tlm_u_tlm_rx_data_snk_cur_byte_ct_6_1_a2_0_a2_0_a2_3_.INIT = 8'h20; + LUT3_L com_tlm_u_tlm_rx_data_snk_cur_byte_ct_6_1_a2_0_a2_0_a2_3_ ( + .I0(com_tlm_u_tlm_rx_data_snk_N_36645_1), + .I1(com_tlm_u_tlm_rx_data_snk_cur_length1_4087), + .I2(com_tlm_u_tlm_rx_data_snk_un4_cur_byte_ct_s_3_4036), + .LO(com_tlm_u_tlm_rx_data_snk_cur_byte_ct_6_3_) + ); + defparam com_tlm_u_tlm_rx_data_snk_N_36623_i.INIT = 16'hDFD5; + LUT4_L com_tlm_u_tlm_rx_data_snk_N_36623_i ( + .I0(com_tlm_u_tlm_rx_data_snk_N_36645_1), + .I1(com_tlm_u_tlm_rx_data_snk_cur_byte_ct_1dw[2]), + .I2(com_tlm_u_tlm_rx_data_snk_cur_length1_4087), + .I3(com_tlm_u_tlm_rx_data_snk_un4_cur_byte_ct_s_2_4037), + .LO(com_tlm_u_tlm_rx_data_snk_N_36623_i_4068) + ); + defparam com_tlm_u_tlm_rx_data_snk_cur_byte_ct_6_2_a2_0_a2_0_a2_1_.INIT = 16'h8A80; + LUT4_L com_tlm_u_tlm_rx_data_snk_cur_byte_ct_6_2_a2_0_a2_0_a2_1_ ( + .I0(com_tlm_u_tlm_rx_data_snk_N_36645_1), + .I1(com_tlm_u_tlm_rx_data_snk_cur_byte_ct_1dw[1]), + .I2(com_tlm_u_tlm_rx_data_snk_cur_length1_4087), + .I3(com_tlm_u_tlm_rx_data_snk_un4_cur_byte_ct_s_1_4038), + .LO(com_tlm_u_tlm_rx_data_snk_cur_byte_ct_6_1_) + ); + defparam com_tlm_u_tlm_rx_data_snk_cur_byte_ct_6_2_a2_0_a2_0_a2_0_.INIT = 16'h88A0; + LUT4_L com_tlm_u_tlm_rx_data_snk_cur_byte_ct_6_2_a2_0_a2_0_a2_0_ ( + .I0(com_tlm_u_tlm_rx_data_snk_N_36645_1), + .I1(com_tlm_u_tlm_rx_data_snk_cur_byte_ct_1dw[0]), + .I2(com_tlm_u_tlm_rx_data_snk_cur_bytes_missing[0]), + .I3(com_tlm_u_tlm_rx_data_snk_cur_length1_4087), + .LO(com_tlm_u_tlm_rx_data_snk_cur_byte_ct_6_0_) + ); + defparam com_tlm_u_tlm_rx_data_snk_cur_bytes_missing_1_p4.INIT = 16'hC0E8; + LUT4_L com_tlm_u_tlm_rx_data_snk_cur_bytes_missing_1_p4 ( + .I0(com_tlm_u_tlm_rx_data_snk_N_14694_i), + .I1(com_tlm_u_tlm_rx_data_snk_N_14696_i), + .I2(com_tlm_u_tlm_rx_data_snk_N_14699_i), + .I3(com_tlm_u_tlm_rx_data_snk_first_be_missing_0_0[0]), + .LO(com_tlm_u_tlm_rx_data_snk_cur_bytes_missing_1[2]) + ); + defparam com_tlm_u_tlm_rx_data_snk_cur_bytes_missing_1_axbxc1.INIT = 16'h3C96; + LUT4_L com_tlm_u_tlm_rx_data_snk_cur_bytes_missing_1_axbxc1 ( + .I0(com_tlm_u_tlm_rx_data_snk_N_14694_i), + .I1(com_tlm_u_tlm_rx_data_snk_N_14696_i), + .I2(com_tlm_u_tlm_rx_data_snk_N_14699_i), + .I3(com_tlm_u_tlm_rx_data_snk_first_be_missing_0_0[0]), + .LO(com_tlm_u_tlm_rx_data_snk_cur_bytes_missing_1[1]) + ); + defparam com_tlm_u_tlm_rx_data_snk_cur_bytes_missing_1_axb0.INIT = 4'h9; + LUT2_L com_tlm_u_tlm_rx_data_snk_cur_bytes_missing_1_axb0 ( + .I0(com_tlm_u_tlm_rx_data_snk_N_14694_i), + .I1(com_tlm_u_tlm_rx_data_snk_first_be_missing_0_0[0]), + .LO(com_tlm_u_tlm_rx_data_snk_cur_bytes_missing_1_axb0_4069) + ); + defparam com_tlm_u_tlm_rx_data_snk_cur_byte_ct_6_1_a2_0_a2_0_a2_11_.INIT = 8'h20; + LUT3_L com_tlm_u_tlm_rx_data_snk_cur_byte_ct_6_1_a2_0_a2_0_a2_11_ ( + .I0(com_tlm_u_tlm_rx_data_snk_N_36645_1), + .I1(com_tlm_u_tlm_rx_data_snk_cur_length1_4087), + .I2(com_tlm_u_tlm_rx_data_snk_un4_cur_byte_ct_s_11_4039), + .LO(com_tlm_u_tlm_rx_data_snk_cur_byte_ct_6_11_) + ); + defparam com_tlm_u_tlm_rx_data_snk_cur_byte_ct_6_1_a2_0_a2_0_a2_10_.INIT = 8'h20; + LUT3_L com_tlm_u_tlm_rx_data_snk_cur_byte_ct_6_1_a2_0_a2_0_a2_10_ ( + .I0(com_tlm_u_tlm_rx_data_snk_N_36645_1), + .I1(com_tlm_u_tlm_rx_data_snk_cur_length1_4087), + .I2(com_tlm_u_tlm_rx_data_snk_un4_cur_byte_ct_s_10_4040), + .LO(com_tlm_u_tlm_rx_data_snk_cur_byte_ct_6_10_) + ); + defparam com_tlm_u_tlm_rx_data_snk_cur_byte_ct_6_1_a2_0_a2_0_a2_9_.INIT = 8'h20; + LUT3_L com_tlm_u_tlm_rx_data_snk_cur_byte_ct_6_1_a2_0_a2_0_a2_9_ ( + .I0(com_tlm_u_tlm_rx_data_snk_N_36645_1), + .I1(com_tlm_u_tlm_rx_data_snk_cur_length1_4087), + .I2(com_tlm_u_tlm_rx_data_snk_un4_cur_byte_ct_s_9_4041), + .LO(com_tlm_u_tlm_rx_data_snk_cur_byte_ct_6_9_) + ); + defparam com_tlm_u_tlm_rx_data_snk_cur_byte_ct_6_1_a2_0_a2_0_a2_8_.INIT = 8'h20; + LUT3_L com_tlm_u_tlm_rx_data_snk_cur_byte_ct_6_1_a2_0_a2_0_a2_8_ ( + .I0(com_tlm_u_tlm_rx_data_snk_N_36645_1), + .I1(com_tlm_u_tlm_rx_data_snk_cur_length1_4087), + .I2(com_tlm_u_tlm_rx_data_snk_un4_cur_byte_ct_s_8_4042), + .LO(com_tlm_u_tlm_rx_data_snk_cur_byte_ct_6_8_) + ); + defparam com_tlm_u_tlm_rx_data_snk_cur_byte_ct_6_1_a2_0_a2_0_a2_7_.INIT = 8'h20; + LUT3_L com_tlm_u_tlm_rx_data_snk_cur_byte_ct_6_1_a2_0_a2_0_a2_7_ ( + .I0(com_tlm_u_tlm_rx_data_snk_N_36645_1), + .I1(com_tlm_u_tlm_rx_data_snk_cur_length1_4087), + .I2(com_tlm_u_tlm_rx_data_snk_un4_cur_byte_ct_s_7_4043), + .LO(com_tlm_u_tlm_rx_data_snk_cur_byte_ct_6_7_) + ); + defparam com_tlm_u_tlm_rx_data_snk_cur_byte_ct_6_1_a2_0_a2_0_a2_6_.INIT = 8'h20; + LUT3_L com_tlm_u_tlm_rx_data_snk_cur_byte_ct_6_1_a2_0_a2_0_a2_6_ ( + .I0(com_tlm_u_tlm_rx_data_snk_N_36645_1), + .I1(com_tlm_u_tlm_rx_data_snk_cur_length1_4087), + .I2(com_tlm_u_tlm_rx_data_snk_un4_cur_byte_ct_s_6_4044), + .LO(com_tlm_u_tlm_rx_data_snk_cur_byte_ct_6_6_) + ); + defparam com_tlm_u_tlm_rx_data_snk_cur_byte_ct_6_1_a2_0_a2_0_a2_5_.INIT = 8'h20; + LUT3_L com_tlm_u_tlm_rx_data_snk_cur_byte_ct_6_1_a2_0_a2_0_a2_5_ ( + .I0(com_tlm_u_tlm_rx_data_snk_N_36645_1), + .I1(com_tlm_u_tlm_rx_data_snk_cur_length1_4087), + .I2(com_tlm_u_tlm_rx_data_snk_un4_cur_byte_ct_s_5_4045), + .LO(com_tlm_u_tlm_rx_data_snk_cur_byte_ct_6_5_) + ); + defparam com_tlm_u_tlm_rx_data_snk_cur_byte_ct_6_1_a2_0_a2_0_a2_4_.INIT = 8'h20; + LUT3_L com_tlm_u_tlm_rx_data_snk_cur_byte_ct_6_1_a2_0_a2_0_a2_4_ ( + .I0(com_tlm_u_tlm_rx_data_snk_N_36645_1), + .I1(com_tlm_u_tlm_rx_data_snk_cur_length1_4087), + .I2(com_tlm_u_tlm_rx_data_snk_un4_cur_byte_ct_s_4_4046), + .LO(com_tlm_u_tlm_rx_data_snk_cur_byte_ct_6_4_) + ); + defparam com_tlm_u_tlm_rx_data_snk_ds_eof_i.INIT = 4'h1; + LUT1_L com_tlm_u_tlm_rx_data_snk_ds_eof_i ( + .I0(com_tlm_u_tlm_rx_ds_eof), + .LO(com_tlm_u_tlm_rx_ds_eof_i) + ); + defparam com_tlm_u_tlm_rx_data_snk_ds_np_i.INIT = 4'h1; + LUT1_L com_tlm_u_tlm_rx_data_snk_ds_np_i ( + .I0(com_tlm_u_tlm_rx_ds_np), + .LO(com_tlm_u_tlm_rx_data_snk_ds_np_i_4047) + ); + defparam com_tlm_u_tlm_rx_data_snk_sof_q_3_0_a2_0_a2_0_a2_1_.INIT = 4'h2; + LUT2_L com_tlm_u_tlm_rx_data_snk_sof_q_3_0_a2_0_a2_0_a2_1_ ( + .I0(com_tlm_u_tlm_rx_data_snk_latch_2nd_dword), + .I1(com_tlm_u_tlm_rx_data_snk_packet_ip_4048), + .LO(com_tlm_u_tlm_rx_data_snk_sof_q_3[1]) + ); + defparam com_tlm_u_tlm_rx_data_snk_cur_np_2_0_a2_0_a2_0_a2.INIT = 8'h01; + LUT3_L com_tlm_u_tlm_rx_data_snk_cur_np_2_0_a2_0_a2_0_a2 ( + .I0(com_tlm_u_tlm_rx_data_snk_cur_fulltype_oh_0__4094), + .I1(com_tlm_u_tlm_rx_data_snk_cur_fulltype_oh_1_), + .I2(com_tlm_u_tlm_rx_data_snk_cur_fulltype_oh_5__4092), + .LO(com_tlm_u_tlm_rx_data_snk_cur_np_2) + ); + defparam com_tlm_u_tlm_rx_data_snk_cur_tc0_2_0_a2_0_a2.INIT = 8'h01; + LUT3_L com_tlm_u_tlm_rx_data_snk_cur_tc0_2_0_a2_0_a2 ( + .I0(com_lnk_rd_5077[52]), + .I1(com_lnk_rd_5077[53]), + .I2(com_lnk_rd_5077[54]), + .LO(com_tlm_u_tlm_rx_data_snk_cur_tc0_2) + ); + defparam com_tlm_u_tlm_rx_data_snk_cur_cpl_ep_6_0_a2_0_a2_0_a2.INIT = 4'h8; + LUT2_L com_tlm_u_tlm_rx_data_snk_cur_cpl_ep_6_0_a2_0_a2_0_a2 ( + .I0(com_tlm_u_tlm_rx_data_snk_cur_ep_4079), + .I1(com_tlm_u_tlm_rx_data_snk_cur_fulltype_oh_0__4094), + .LO(com_tlm_u_tlm_rx_data_snk_cur_cpl_ep_6) + ); + defparam com_tlm_u_tlm_rx_data_snk_dsc_q_3_0_a2_0_a2_0_a2_1_.INIT = 4'h2; + LUT2_L com_tlm_u_tlm_rx_data_snk_dsc_q_3_0_a2_0_a2_0_a2_1_ ( + .I0(com_tlm_u_tlm_rx_data_snk_N_36411_i), + .I1(com_lnk_rsrc_dsc_n), + .LO(com_tlm_u_tlm_rx_data_snk_dsc_q_3[1]) + ); + defparam com_tlm_u_tlm_rx_data_snk_eof_nd_q_3_0_a2_0_a2_0_a2_1_.INIT = 4'h8; + LUT2_L com_tlm_u_tlm_rx_data_snk_eof_nd_q_3_0_a2_0_a2_0_a2_1_ ( + .I0(com_tlm_u_tlm_rx_data_snk_N_36411_i), + .I1(com_lnk_rsrc_dsc_n), + .LO(com_tlm_u_tlm_rx_data_snk_eof_nd_q_3[1]) + ); + defparam com_tlm_u_tlm_rx_data_snk_err_tlp_malformed_o_3.INIT = 4'h8; + LUT2_L com_tlm_u_tlm_rx_data_snk_err_tlp_malformed_o_3 ( + .I0(com_tlm_u_tlm_rx_data_snk_eof_nd_q_4_), + .I1(com_tlm_u_tlm_rx_data_snk_malformed), + .LO(com_tlm_u_tlm_rx_data_snk_err_tlp_malformed_o_3_4049) + ); + defparam com_tlm_u_tlm_rx_data_snk_cur_lower_addr_22_0_a3_0_a2_0_a2_1_.INIT = 4'h8; + LUT2_L com_tlm_u_tlm_rx_data_snk_cur_lower_addr_22_0_a3_0_a2_0_a2_1_ ( + .I0(com_tlm_u_tlm_rx_data_snk_cur_first_be_adj[1]), + .I1(com_tlm_u_tlm_rx_data_snk_cur_fulltype_mem_4089), + .LO(com_tlm_u_tlm_rx_data_snk_cur_lower_addr_22[1]) + ); + defparam com_tlm_u_tlm_rx_data_snk_cur_lower_addr_22_0_a3_0_a2_0_a2_0_.INIT = 4'h8; + LUT2_L com_tlm_u_tlm_rx_data_snk_cur_lower_addr_22_0_a3_0_a2_0_a2_0_ ( + .I0(com_tlm_u_tlm_rx_data_snk_cur_first_be_adj[0]), + .I1(com_tlm_u_tlm_rx_data_snk_cur_fulltype_mem_4089), + .LO(com_tlm_u_tlm_rx_data_snk_cur_lower_addr_22[0]) + ); + defparam com_tlm_u_tlm_rx_data_snk_packet_ip_3_i_0_0.INIT = 4'h4; + LUT2_L com_tlm_u_tlm_rx_data_snk_packet_ip_3_i_0_0 ( + .I0(com_tlm_u_tlm_rx_data_snk_N_36490), + .I1(com_lnk_reof_n), + .LO(com_tlm_u_tlm_rx_data_snk_N_13361_i) + ); + defparam com_tlm_u_tlm_rx_data_snk_src_rdy_q_3_i_0_0_1_.INIT = 4'h1; + LUT2_L com_tlm_u_tlm_rx_data_snk_src_rdy_q_3_i_0_0_1_ ( + .I0(com_tlm_u_tlm_rx_data_snk_N_36490), + .I1(com_lnk_rsrc_rdy_n), + .LO(com_tlm_u_tlm_rx_data_snk_N_13363_i) + ); + defparam com_tlm_u_tlm_rx_data_snk_eof_o_5_0.INIT = 8'hAC; + LUT3_L com_tlm_u_tlm_rx_data_snk_eof_o_5_0 ( + .I0(com_tlm_u_tlm_rx_data_snk_eof_o_3), + .I1(com_tlm_u_tlm_rx_data_snk_eof_q_5__4072), + .I2(com_tlm_u_tlm_rx_data_snk_remove_lastword_4050), + .LO(com_tlm_u_tlm_rx_data_snk_eof_o_5) + ); + defparam com_tlm_u_tlm_rx_data_snk_rem_o_5_0.INIT = 8'hAC; + LUT3_L com_tlm_u_tlm_rx_data_snk_rem_o_5_0 ( + .I0(com_tlm_u_tlm_rx_data_snk_rem_q_4_), + .I1(com_tlm_u_tlm_rx_data_snk_rem_q_5__4071), + .I2(com_tlm_u_tlm_rx_data_snk_remove_lastword_4050), + .LO(com_tlm_u_tlm_rx_data_snk_rem_o_5) + ); + defparam com_tlm_u_tlm_rx_data_snk_cur_cpl_abort_6_0_a2_0_a2.INIT = 16'h0200; + LUT4_L com_tlm_u_tlm_rx_data_snk_cur_cpl_abort_6_0_a2_0_a2 ( + .I0(com_tlm_u_tlm_rx_data_snk_cur_fulltype_oh_0__4094), + .I1(com_tlm_u_tlm_rx_data_snk_cur_tag[5]), + .I2(com_tlm_u_tlm_rx_data_snk_cur_tag[6]), + .I3(com_tlm_u_tlm_rx_data_snk_cur_tag[7]), + .LO(com_tlm_u_tlm_rx_data_snk_cur_cpl_abort_6) + ); + defparam com_tlm_u_tlm_rx_data_snk_cur_cpl_ur_6_0_a2_0_a2.INIT = 16'h0008; + LUT4_L com_tlm_u_tlm_rx_data_snk_cur_cpl_ur_6_0_a2_0_a2 ( + .I0(com_tlm_u_tlm_rx_data_snk_cur_fulltype_oh_0__4094), + .I1(com_tlm_u_tlm_rx_data_snk_cur_tag[5]), + .I2(com_tlm_u_tlm_rx_data_snk_cur_tag[6]), + .I3(com_tlm_u_tlm_rx_data_snk_cur_tag[7]), + .LO(com_tlm_u_tlm_rx_data_snk_cur_cpl_ur_6) + ); + defparam com_tlm_u_tlm_rx_data_snk_remove_lastword_6_0_a2_0_a2_0_a2.INIT = 16'h2000; + LUT4_L com_tlm_u_tlm_rx_data_snk_remove_lastword_6_0_a2_0_a2_0_a2 ( + .I0(cfg_cfg_5072[508]), + .I1(com_tlm_u_tlm_rx_data_snk_cur_rem_4081), + .I2(com_tlm_u_tlm_rx_data_snk_cur_td_q_4078), + .I3(com_tlm_u_tlm_rx_data_snk_eof_q_2__4074), + .LO(com_tlm_u_tlm_rx_data_snk_remove_lastword_6) + ); + defparam com_tlm_u_tlm_rx_data_snk_cur_length1_2_0_a2_0_a2_0_a2_0_a2.INIT = 16'h1000; + LUT4_L com_tlm_u_tlm_rx_data_snk_cur_length1_2_0_a2_0_a2_0_a2_0_a2 ( + .I0(com_lnk_rd_5077[40]), + .I1(com_lnk_rd_5077[41]), + .I2(com_tlm_u_tlm_rx_data_snk_cur_length1_2_0_a2_0_a2_0_a2_0_a2_4_4052), + .I3(com_tlm_u_tlm_rx_data_snk_cur_length1_2_0_a2_0_a2_0_a2_0_a2_5_4051), + .LO(com_tlm_u_tlm_rx_data_snk_cur_length1_2) + ); + defparam com_tlm_u_tlm_rx_data_snk_cur_fulltype_6412_0_0.INIT = 16'h0200; + LUT4_L com_tlm_u_tlm_rx_data_snk_cur_fulltype_6412_0_0 ( + .I0(com_tlm_u_tlm_rx_data_snk_N_36395_i), + .I1(com_lnk_rd_5077[57]), + .I2(com_lnk_rd_5077[59]), + .I3(com_lnk_rd_5077[61]), + .LO(com_tlm_u_tlm_rx_data_snk_N_9480_i) + ); + defparam com_tlm_u_tlm_rx_data_snk_err_tlp_ur_o_3.INIT = 8'h20; + LUT3_L com_tlm_u_tlm_rx_data_snk_err_tlp_ur_o_3 ( + .I0(com_tlm_u_tlm_rx_data_snk_eof_nd_q_4_), + .I1(com_tlm_u_tlm_rx_data_snk_malformed), + .I2(com_tlm_u_tlm_rx_data_snk_tlp_ur), + .LO(com_tlm_u_tlm_rx_data_snk_err_tlp_ur_o_3_4053) + ); + defparam com_tlm_u_tlm_rx_data_snk_N_68789_i.INIT = 4'h1; + LUT1_L com_tlm_u_tlm_rx_data_snk_N_68789_i ( + .I0(com_tlm_u_tlm_rx_data_snk_first_be_missing_0_0[0]), + .LO(com_tlm_u_tlm_rx_data_snk_N_68789_i_4054) + ); + defparam com_tlm_u_tlm_rx_data_snk_N_69055_i.INIT = 16'hDEFC; + LUT4_L com_tlm_u_tlm_rx_data_snk_N_69055_i ( + .I0(cfg_cfg_5072[508]), + .I1(com_lnk_reof_n), + .I2(com_lnk_rrem[0]), + .I3(com_tlm_u_tlm_rx_data_snk_cur_td_4080), + .LO(com_tlm_u_tlm_rx_data_snk_N_69055_i_4055) + ); + defparam com_tlm_u_tlm_rx_data_snk_fc_use_cpl_o_5.INIT = 8'h40; + LUT3_L com_tlm_u_tlm_rx_data_snk_fc_use_cpl_o_5 ( + .I0(com_tlm_u_tlm_rx_data_snk_dsc_q_4_), + .I1(com_tlm_u_tlm_rx_data_snk_eof_o_3), + .I2(com_tlm_u_tlm_rx_ds_cpl), + .LO(com_tlm_u_tlm_rx_data_snk_fc_use_cpl_o_5_4056) + ); + defparam com_tlm_u_tlm_rx_data_snk_fc_use_np_o_5.INIT = 8'h40; + LUT3_L com_tlm_u_tlm_rx_data_snk_fc_use_np_o_5 ( + .I0(com_tlm_u_tlm_rx_data_snk_dsc_q_4_), + .I1(com_tlm_u_tlm_rx_data_snk_eof_o_3), + .I2(com_tlm_u_tlm_rx_ds_np), + .LO(com_tlm_u_tlm_rx_data_snk_fc_use_np_o_5_4057) + ); + defparam com_tlm_u_tlm_rx_data_snk_fc_use_p_o_5.INIT = 16'h0004; + LUT4_L com_tlm_u_tlm_rx_data_snk_fc_use_p_o_5 ( + .I0(com_tlm_u_tlm_rx_data_snk_dsc_q_4_), + .I1(com_tlm_u_tlm_rx_data_snk_eof_o_3), + .I2(com_tlm_u_tlm_rx_ds_cpl), + .I3(com_tlm_u_tlm_rx_ds_np), + .LO(com_tlm_u_tlm_rx_data_snk_fc_use_p_o_5_4058) + ); + defparam com_tlm_u_tlm_rx_data_snk_cur_fulltype_mem12_0_0.INIT = 4'h8; + LUT2_L com_tlm_u_tlm_rx_data_snk_cur_fulltype_mem12_0_0 ( + .I0(com_tlm_u_tlm_rx_data_snk_N_36395_i), + .I1(com_tlm_u_tlm_rx_data_snk_N_36407_i), + .LO(com_tlm_u_tlm_rx_data_snk_cur_fulltype_mem12_i_i) + ); + defparam com_tlm_u_tlm_rx_data_snk_cur_lower_addr_15_i_0_0_6_.INIT = 16'hC840; + LUT4_L com_tlm_u_tlm_rx_data_snk_cur_lower_addr_15_i_0_0_6_ ( + .I0(com_tlm_u_tlm_rx_data_snk_cur_fulltype_64_4088), + .I1(com_tlm_u_tlm_rx_data_snk_cur_fulltype_mem_4089), + .I2(com_tlm_u_tlm_rx_data_snk_lower_addr32_in_q[6]), + .I3(com_tlm_u_tlm_rx_data_snk_lower_addr64_in_q[6]), + .LO(com_tlm_u_tlm_rx_data_snk_N_21331_i) + ); + defparam com_tlm_u_tlm_rx_data_snk_cur_lower_addr_15_i_0_0_5_.INIT = 16'hC840; + LUT4_L com_tlm_u_tlm_rx_data_snk_cur_lower_addr_15_i_0_0_5_ ( + .I0(com_tlm_u_tlm_rx_data_snk_cur_fulltype_64_4088), + .I1(com_tlm_u_tlm_rx_data_snk_cur_fulltype_mem_4089), + .I2(com_tlm_u_tlm_rx_data_snk_lower_addr32_in_q[5]), + .I3(com_tlm_u_tlm_rx_data_snk_lower_addr64_in_q[5]), + .LO(com_tlm_u_tlm_rx_data_snk_N_21329_i) + ); + defparam com_tlm_u_tlm_rx_data_snk_cur_lower_addr_15_i_0_0_4_.INIT = 16'hC840; + LUT4_L com_tlm_u_tlm_rx_data_snk_cur_lower_addr_15_i_0_0_4_ ( + .I0(com_tlm_u_tlm_rx_data_snk_cur_fulltype_64_4088), + .I1(com_tlm_u_tlm_rx_data_snk_cur_fulltype_mem_4089), + .I2(com_tlm_u_tlm_rx_data_snk_lower_addr32_in_q[4]), + .I3(com_tlm_u_tlm_rx_data_snk_lower_addr64_in_q[4]), + .LO(com_tlm_u_tlm_rx_data_snk_N_21327_i) + ); + defparam com_tlm_u_tlm_rx_data_snk_cur_lower_addr_15_i_0_0_3_.INIT = 16'hC840; + LUT4_L com_tlm_u_tlm_rx_data_snk_cur_lower_addr_15_i_0_0_3_ ( + .I0(com_tlm_u_tlm_rx_data_snk_cur_fulltype_64_4088), + .I1(com_tlm_u_tlm_rx_data_snk_cur_fulltype_mem_4089), + .I2(com_tlm_u_tlm_rx_data_snk_lower_addr32_in_q[3]), + .I3(com_tlm_u_tlm_rx_data_snk_lower_addr64_in_q[3]), + .LO(com_tlm_u_tlm_rx_data_snk_N_21325_i) + ); + defparam com_tlm_u_tlm_rx_data_snk_cur_lower_addr_15_i_0_0_2_.INIT = 16'hC840; + LUT4_L com_tlm_u_tlm_rx_data_snk_cur_lower_addr_15_i_0_0_2_ ( + .I0(com_tlm_u_tlm_rx_data_snk_cur_fulltype_64_4088), + .I1(com_tlm_u_tlm_rx_data_snk_cur_fulltype_mem_4089), + .I2(com_tlm_u_tlm_rx_data_snk_lower_addr32_in_q[2]), + .I3(com_tlm_u_tlm_rx_data_snk_lower_addr64_in_q[2]), + .LO(com_tlm_u_tlm_rx_data_snk_N_21323_i) + ); + defparam com_tlm_u_tlm_rx_data_snk_fc_unuse_o_5.INIT = 8'h10; + LUT3_L com_tlm_u_tlm_rx_data_snk_fc_unuse_o_5 ( + .I0(com_tlm_u_tlm_rx_data_snk_N_9481), + .I1(com_tlm_u_tlm_rx_data_snk_dsc_q_4_), + .I2(com_tlm_u_tlm_rx_data_snk_eof_o_3), + .LO(com_tlm_u_tlm_rx_data_snk_fc_unuse_o_5_4059) + ); + defparam com_tlm_u_tlm_rx_data_snk_un1_cur_fulltype_oh37_0_0.INIT = 16'h008A; + LUT4_L com_tlm_u_tlm_rx_data_snk_un1_cur_fulltype_oh37_0_0 ( + .I0(com_tlm_u_tlm_rx_data_snk_N_36395_i), + .I1(com_tlm_u_tlm_rx_data_snk_N_36409_i), + .I2(com_lnk_rd_5077[57]), + .I3(com_lnk_rd_5077[59]), + .LO(com_tlm_u_tlm_rx_data_snk_N_9476_i) + ); + defparam com_tlm_u_tlm_rx_data_snk_cur_fulltype_oh35_i_a2_0_a2.INIT = 8'h20; + LUT3_L com_tlm_u_tlm_rx_data_snk_cur_fulltype_oh35_i_a2_0_a2 ( + .I0(com_tlm_u_tlm_rx_data_snk_N_36569_1), + .I1(com_lnk_rd_5077[56]), + .I2(com_lnk_rd_5077[62]), + .LO(com_tlm_u_tlm_rx_data_snk_cur_fulltype_oh35_i_a2_0_a2_4091) + ); + defparam com_tlm_u_tlm_rx_data_snk_cur_fulltype_oh40_0_a2_0_a2.INIT = 4'h8; + LUT2_L com_tlm_u_tlm_rx_data_snk_cur_fulltype_oh40_0_a2_0_a2 ( + .I0(com_lnk_rd_5077[59]), + .I1(com_tlm_u_tlm_rx_data_snk_cur_fulltype_oh40_1), + .LO(com_tlm_u_tlm_rx_data_snk_cur_fulltype_oh40) + ); + defparam com_tlm_u_tlm_rx_data_snk_stat_tlp_cpl_abort_o_5.INIT = 16'h0800; + LUT4_L com_tlm_u_tlm_rx_data_snk_stat_tlp_cpl_abort_o_5 ( + .I0(com_tlm_u_tlm_rx_data_snk_N_9481), + .I1(com_tlm_u_tlm_rx_data_snk_cur_cpl_abort_4061), + .I2(com_tlm_u_tlm_rx_data_snk_dsc_q_4_), + .I3(com_tlm_u_tlm_rx_data_snk_eof_o_3), + .LO(com_tlm_u_tlm_rx_data_snk_stat_tlp_cpl_abort_o_5_4060) + ); + defparam com_tlm_u_tlm_rx_data_snk_stat_tlp_cpl_ep_o_5.INIT = 16'h0800; + LUT4_L com_tlm_u_tlm_rx_data_snk_stat_tlp_cpl_ep_o_5 ( + .I0(com_tlm_u_tlm_rx_data_snk_N_9481), + .I1(com_tlm_u_tlm_rx_data_snk_cur_cpl_ep_4063), + .I2(com_tlm_u_tlm_rx_data_snk_dsc_q_4_), + .I3(com_tlm_u_tlm_rx_data_snk_eof_o_3), + .LO(com_tlm_u_tlm_rx_data_snk_stat_tlp_cpl_ep_o_5_4062) + ); + defparam com_tlm_u_tlm_rx_data_snk_stat_tlp_cpl_ur_o_5.INIT = 16'h0800; + LUT4_L com_tlm_u_tlm_rx_data_snk_stat_tlp_cpl_ur_o_5 ( + .I0(com_tlm_u_tlm_rx_data_snk_N_9481), + .I1(com_tlm_u_tlm_rx_data_snk_cur_cpl_ur_4065), + .I2(com_tlm_u_tlm_rx_data_snk_dsc_q_4_), + .I3(com_tlm_u_tlm_rx_data_snk_eof_o_3), + .LO(com_tlm_u_tlm_rx_data_snk_stat_tlp_cpl_ur_o_5_4064) + ); + defparam com_tlm_u_tlm_rx_data_snk_stat_tlp_ep_o_5.INIT = 16'h0800; + LUT4_L com_tlm_u_tlm_rx_data_snk_stat_tlp_ep_o_5 ( + .I0(com_tlm_u_tlm_rx_data_snk_N_9481), + .I1(com_tlm_u_tlm_rx_data_snk_cur_ep_q_4077), + .I2(com_tlm_u_tlm_rx_data_snk_dsc_q_4_), + .I3(com_tlm_u_tlm_rx_data_snk_eof_o_3), + .LO(com_tlm_u_tlm_rx_data_snk_stat_tlp_ep_o_5_4066) + ); + defparam com_tlm_u_tlm_rx_data_snk_d_mux_1_i_0_0_47_.INIT = 8'hC4; + LUT3_L com_tlm_u_tlm_rx_data_snk_d_mux_1_i_0_0_47_ ( + .I0(cfg_cfg_5072[508]), + .I1(com_lnk_rd_5077[47]), + .I2(com_lnk_rsof_n), + .LO(com_tlm_u_tlm_rx_data_snk_N_13365_i) + ); + defparam com_tlm_u_tlm_rx_data_snk_cur_fulltype_oh35_i_a2_0_a2_1.INIT = 8'h02; + LUT3 com_tlm_u_tlm_rx_data_snk_cur_fulltype_oh35_i_a2_0_a2_1 ( + .I0(com_tlm_u_tlm_rx_data_snk_N_36393_i), + .I1(com_lnk_rd_5077[59]), + .I2(com_lnk_rd_5077[57]), + .O(com_tlm_u_tlm_rx_data_snk_N_36569_1) + ); + defparam com_tlm_u_tlm_rx_data_snk_dsc_o_5_0_bm.INIT = 8'hAE; + LUT3 com_tlm_u_tlm_rx_data_snk_dsc_o_5_0_bm ( + .I0(com_tlm_u_tlm_rx_data_snk_dsc_q_4_), + .I1(com_tlm_u_tlm_rx_data_snk_eof_o_3), + .I2(com_tlm_u_tlm_rx_data_snk_N_9481), + .O(com_tlm_u_tlm_rx_data_snk_dsc_o_5_0_bm_4067) + ); + FD com_tlm_u_tlm_rx_data_snk_d_o_62_DOUT_0_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_d_o_62_N_6), + .Q(com_tlm_u_tlm_rx_ds_d[9]) + ); + FD com_tlm_u_tlm_rx_data_snk_d_o_61_DOUT_0_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_d_o_61_N_6), + .Q(com_tlm_u_tlm_rx_ds_d[8]) + ); + FD com_tlm_u_tlm_rx_data_snk_d_o_60_DOUT_0_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_d_o_60_N_6), + .Q(com_tlm_u_tlm_rx_ds_d[7]) + ); + FD com_tlm_u_tlm_rx_data_snk_d_o_59_DOUT_0_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_d_o_59_N_6), + .Q(com_tlm_u_tlm_rx_ds_d[6]) + ); + FD com_tlm_u_tlm_rx_data_snk_d_o_58_DOUT_0_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_d_o_58_N_6), + .Q(com_tlm_u_tlm_rx_ds_d[5]) + ); + FD com_tlm_u_tlm_rx_data_snk_d_o_57_DOUT_0_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_d_o_57_N_6), + .Q(com_tlm_u_tlm_rx_ds_d[4]) + ); + FD com_tlm_u_tlm_rx_data_snk_d_o_56_DOUT_0_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_d_o_56_N_6), + .Q(com_tlm_u_tlm_rx_ds_d[3]) + ); + FD com_tlm_u_tlm_rx_data_snk_d_o_55_DOUT_0_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_d_o_55_N_6), + .Q(com_tlm_u_tlm_rx_ds_d[2]) + ); + FD com_tlm_u_tlm_rx_data_snk_d_o_54_DOUT_0_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_d_o_54_N_6), + .Q(com_tlm_u_tlm_rx_ds_d[1]) + ); + FD com_tlm_u_tlm_rx_data_snk_d_o_53_DOUT_0_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_d_o_53_N_6), + .Q(com_tlm_u_tlm_rx_ds_d[0]) + ); + FD com_tlm_u_tlm_rx_data_snk_d_o_52_DOUT_0_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_d_o_52_N_6), + .Q(com_tlm_u_tlm_rx_ds_d[24]) + ); + FD com_tlm_u_tlm_rx_data_snk_d_o_51_DOUT_0_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_d_o_51_N_6), + .Q(com_tlm_u_tlm_rx_ds_d[23]) + ); + FD com_tlm_u_tlm_rx_data_snk_d_o_50_DOUT_0_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_d_o_50_N_6), + .Q(com_tlm_u_tlm_rx_ds_d[22]) + ); + FD com_tlm_u_tlm_rx_data_snk_d_o_49_DOUT_0_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_d_o_49_N_6), + .Q(com_tlm_u_tlm_rx_ds_d[21]) + ); + FD com_tlm_u_tlm_rx_data_snk_d_o_48_DOUT_0_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_d_o_48_N_6), + .Q(com_tlm_u_tlm_rx_ds_d[20]) + ); + FD com_tlm_u_tlm_rx_data_snk_d_o_47_DOUT_0_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_d_o_47_N_6), + .Q(com_tlm_u_tlm_rx_ds_d[19]) + ); + FD com_tlm_u_tlm_rx_data_snk_d_o_46_DOUT_0_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_d_o_46_N_6), + .Q(com_tlm_u_tlm_rx_ds_d[18]) + ); + FD com_tlm_u_tlm_rx_data_snk_d_o_45_DOUT_0_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_d_o_45_N_6), + .Q(com_tlm_u_tlm_rx_ds_d[17]) + ); + FD com_tlm_u_tlm_rx_data_snk_d_o_44_DOUT_0_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_d_o_44_N_6), + .Q(com_tlm_u_tlm_rx_ds_d[16]) + ); + FD com_tlm_u_tlm_rx_data_snk_d_o_43_DOUT_0_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_d_o_43_N_6), + .Q(com_tlm_u_tlm_rx_ds_d[15]) + ); + FD com_tlm_u_tlm_rx_data_snk_d_o_42_DOUT_0_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_d_o_42_N_6), + .Q(com_tlm_u_tlm_rx_ds_d[14]) + ); + FD com_tlm_u_tlm_rx_data_snk_d_o_41_DOUT_0_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_d_o_41_N_6), + .Q(com_tlm_u_tlm_rx_ds_d[13]) + ); + FD com_tlm_u_tlm_rx_data_snk_d_o_40_DOUT_0_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_d_o_40_N_6), + .Q(com_tlm_u_tlm_rx_ds_d[12]) + ); + FD com_tlm_u_tlm_rx_data_snk_d_o_39_DOUT_0_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_d_o_39_N_6), + .Q(com_tlm_u_tlm_rx_ds_d[11]) + ); + FD com_tlm_u_tlm_rx_data_snk_d_o_38_DOUT_0_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_d_o_38_N_6), + .Q(com_tlm_u_tlm_rx_ds_d[10]) + ); + FD com_tlm_u_tlm_rx_data_snk_d_o_37_DOUT_0_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_d_o_37_N_6), + .Q(com_tlm_u_tlm_rx_ds_d[39]) + ); + FD com_tlm_u_tlm_rx_data_snk_d_o_36_DOUT_0_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_d_o_36_N_6), + .Q(com_tlm_u_tlm_rx_ds_d[38]) + ); + FD com_tlm_u_tlm_rx_data_snk_d_o_35_DOUT_0_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_d_o_35_N_6), + .Q(com_tlm_u_tlm_rx_ds_d[37]) + ); + FD com_tlm_u_tlm_rx_data_snk_d_o_34_DOUT_0_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_d_o_34_N_6), + .Q(com_tlm_u_tlm_rx_ds_d[36]) + ); + FD com_tlm_u_tlm_rx_data_snk_d_o_33_DOUT_0_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_d_o_33_N_6), + .Q(com_tlm_u_tlm_rx_ds_d[35]) + ); + FD com_tlm_u_tlm_rx_data_snk_d_o_32_DOUT_0_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_d_o_32_N_6), + .Q(com_tlm_u_tlm_rx_ds_d[34]) + ); + FD com_tlm_u_tlm_rx_data_snk_d_o_31_DOUT_0_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_d_o_31_N_6), + .Q(com_tlm_u_tlm_rx_ds_d[33]) + ); + FD com_tlm_u_tlm_rx_data_snk_d_o_30_DOUT_0_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_d_o_30_N_6), + .Q(com_tlm_u_tlm_rx_ds_d[32]) + ); + FD com_tlm_u_tlm_rx_data_snk_d_o_29_DOUT_0_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_d_o_29_N_6), + .Q(com_tlm_u_tlm_rx_ds_d[31]) + ); + FD com_tlm_u_tlm_rx_data_snk_d_o_28_DOUT_0_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_d_o_28_N_6), + .Q(com_tlm_u_tlm_rx_ds_d[30]) + ); + FD com_tlm_u_tlm_rx_data_snk_d_o_27_DOUT_0_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_d_o_27_N_6), + .Q(com_tlm_u_tlm_rx_ds_d[29]) + ); + FD com_tlm_u_tlm_rx_data_snk_d_o_26_DOUT_0_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_d_o_26_N_6), + .Q(com_tlm_u_tlm_rx_ds_d[28]) + ); + FD com_tlm_u_tlm_rx_data_snk_d_o_25_DOUT_0_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_d_o_25_N_6), + .Q(com_tlm_u_tlm_rx_ds_d[27]) + ); + FD com_tlm_u_tlm_rx_data_snk_d_o_24_DOUT_0_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_d_o_24_N_6), + .Q(com_tlm_u_tlm_rx_ds_d[26]) + ); + FD com_tlm_u_tlm_rx_data_snk_d_o_23_DOUT_0_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_d_o_23_N_6), + .Q(com_tlm_u_tlm_rx_ds_d[25]) + ); + FD com_tlm_u_tlm_rx_data_snk_d_o_22_DOUT_0_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_d_o_22_N_6), + .Q(com_tlm_u_tlm_rx_ds_d[54]) + ); + FD com_tlm_u_tlm_rx_data_snk_d_o_21_DOUT_0_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_d_o_21_N_6), + .Q(com_tlm_u_tlm_rx_ds_d[53]) + ); + FD com_tlm_u_tlm_rx_data_snk_d_o_20_DOUT_0_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_d_o_20_N_6), + .Q(com_tlm_u_tlm_rx_ds_d[52]) + ); + FD com_tlm_u_tlm_rx_data_snk_d_o_19_DOUT_0_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_d_o_19_N_6), + .Q(com_tlm_u_tlm_rx_ds_d[51]) + ); + FD com_tlm_u_tlm_rx_data_snk_d_o_18_DOUT_0_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_d_o_18_N_6), + .Q(com_tlm_u_tlm_rx_ds_d[50]) + ); + FD com_tlm_u_tlm_rx_data_snk_d_o_17_DOUT_0_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_d_o_17_N_6), + .Q(com_tlm_u_tlm_rx_ds_d[49]) + ); + FD com_tlm_u_tlm_rx_data_snk_d_o_16_DOUT_0_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_d_o_16_N_6), + .Q(com_tlm_u_tlm_rx_ds_d[48]) + ); + FD com_tlm_u_tlm_rx_data_snk_d_o_15_DOUT_0_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_d_o_15_N_6), + .Q(com_tlm_u_tlm_rx_ds_d[47]) + ); + FD com_tlm_u_tlm_rx_data_snk_d_o_14_DOUT_0_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_d_o_14_N_6), + .Q(com_tlm_u_tlm_rx_ds_d[46]) + ); + FD com_tlm_u_tlm_rx_data_snk_d_o_13_DOUT_0_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_d_o_13_N_6), + .Q(com_tlm_u_tlm_rx_ds_d[45]) + ); + FD com_tlm_u_tlm_rx_data_snk_d_o_12_DOUT_0_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_d_o_12_N_6), + .Q(com_tlm_u_tlm_rx_ds_d[44]) + ); + FD com_tlm_u_tlm_rx_data_snk_d_o_11_DOUT_0_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_d_o_11_N_6), + .Q(com_tlm_u_tlm_rx_ds_d[43]) + ); + FD com_tlm_u_tlm_rx_data_snk_d_o_10_DOUT_0_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_d_o_10_N_6), + .Q(com_tlm_u_tlm_rx_ds_d[42]) + ); + FD com_tlm_u_tlm_rx_data_snk_d_o_9_DOUT_0_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_d_o_9_N_6), + .Q(com_tlm_u_tlm_rx_ds_d[41]) + ); + FD com_tlm_u_tlm_rx_data_snk_d_o_8_DOUT_0_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_d_o_8_N_6), + .Q(com_tlm_u_tlm_rx_ds_d[40]) + ); + FD com_tlm_u_tlm_rx_data_snk_dsc_q_DOUT_0_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_dsc_q_N_6), + .Q(com_tlm_u_tlm_rx_data_snk_dsc_q_4_) + ); + FD com_tlm_u_tlm_rx_data_snk_eof_nd_q_DOUT_0_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_eof_nd_q_N_6), + .Q(com_tlm_u_tlm_rx_data_snk_eof_nd_q_4_) + ); + FD com_tlm_u_tlm_rx_data_snk_d_o_7_DOUT_0_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_d_o_7_N_6), + .Q(com_tlm_u_tlm_rx_ds_d[63]) + ); + FD com_tlm_u_tlm_rx_data_snk_d_o_6_DOUT_0_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_d_o_6_N_6), + .Q(com_tlm_u_tlm_rx_ds_d[62]) + ); + FD com_tlm_u_tlm_rx_data_snk_d_o_5_DOUT_0_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_d_o_5_N_6), + .Q(com_tlm_u_tlm_rx_ds_d[61]) + ); + FD com_tlm_u_tlm_rx_data_snk_d_o_4_DOUT_0_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_d_o_4_N_6), + .Q(com_tlm_u_tlm_rx_ds_d[60]) + ); + FD com_tlm_u_tlm_rx_data_snk_d_o_3_DOUT_0_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_d_o_3_N_6), + .Q(com_tlm_u_tlm_rx_ds_d[59]) + ); + FD com_tlm_u_tlm_rx_data_snk_d_o_2_DOUT_0_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_d_o_2_N_6), + .Q(com_tlm_u_tlm_rx_ds_d[58]) + ); + FD com_tlm_u_tlm_rx_data_snk_d_o_1_DOUT_0_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_d_o_1_N_6), + .Q(com_tlm_u_tlm_rx_ds_d[57]) + ); + FD com_tlm_u_tlm_rx_data_snk_d_o_0_DOUT_0_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_d_o_0_N_6), + .Q(com_tlm_u_tlm_rx_ds_d[56]) + ); + FD com_tlm_u_tlm_rx_data_snk_d_o_DOUT_0_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_d_o_N_6), + .Q(com_tlm_u_tlm_rx_ds_d[55]) + ); + FD com_tlm_u_tlm_rx_data_snk_sof_q_DOUT_0_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_sof_q_N_6), + .Q(com_tlm_u_tlm_rx_data_snk_sof_q_4_) + ); + FD com_tlm_u_tlm_rx_data_snk_rem_q_DOUT_0_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_rem_q_N_6), + .Q(com_tlm_u_tlm_rx_data_snk_rem_q_4_) + ); + FD com_tlm_u_tlm_rx_data_snk_src_rdy_q_DOUT_0_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_src_rdy_q_N_6), + .Q(com_tlm_u_tlm_rx_data_snk_src_rdy_q_4_) + ); + FDE com_tlm_u_tlm_rx_data_snk_cur_byte_ct_3_ ( + .CE(com_tlm_u_tlm_rx_data_snk_latch_1st_dword_q2), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_cur_byte_ct_6_3_), + .Q(com_tlm_u_tlm_rx_data_snk_cur_byte_ct[3]) + ); + FDE com_tlm_u_tlm_rx_data_snk_cur_byte_ct_2_ ( + .CE(com_tlm_u_tlm_rx_data_snk_latch_1st_dword_q2), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_N_36623_i_4068), + .Q(com_tlm_u_tlm_rx_data_snk_cur_byte_ct[2]) + ); + FDE com_tlm_u_tlm_rx_data_snk_cur_byte_ct_1_ ( + .CE(com_tlm_u_tlm_rx_data_snk_latch_1st_dword_q2), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_cur_byte_ct_6_1_), + .Q(com_tlm_u_tlm_rx_data_snk_cur_byte_ct[1]) + ); + FDE com_tlm_u_tlm_rx_data_snk_cur_byte_ct_0_ ( + .CE(com_tlm_u_tlm_rx_data_snk_latch_1st_dword_q2), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_cur_byte_ct_6_0_), + .Q(com_tlm_u_tlm_rx_data_snk_cur_byte_ct[0]) + ); + FDE com_tlm_u_tlm_rx_data_snk_cur_bytes_missing_2_ ( + .CE(com_tlm_u_tlm_rx_data_snk_latch_2nd_dword), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_cur_bytes_missing_1[2]), + .Q(com_tlm_u_tlm_rx_data_snk_cur_bytes_missing[2]) + ); + FDE com_tlm_u_tlm_rx_data_snk_cur_bytes_missing_1_ ( + .CE(com_tlm_u_tlm_rx_data_snk_latch_2nd_dword), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_cur_bytes_missing_1[1]), + .Q(com_tlm_u_tlm_rx_data_snk_cur_bytes_missing[1]) + ); + FDE com_tlm_u_tlm_rx_data_snk_cur_bytes_missing_0_ ( + .CE(com_tlm_u_tlm_rx_data_snk_latch_2nd_dword), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_cur_bytes_missing_1_axb0_4069), + .Q(com_tlm_u_tlm_rx_data_snk_cur_bytes_missing[0]) + ); + FDE com_tlm_u_tlm_rx_data_snk_cur_byte_ct_11_ ( + .CE(com_tlm_u_tlm_rx_data_snk_latch_1st_dword_q2), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_cur_byte_ct_6_11_), + .Q(com_tlm_u_tlm_rx_data_snk_cur_byte_ct[11]) + ); + FDE com_tlm_u_tlm_rx_data_snk_cur_byte_ct_10_ ( + .CE(com_tlm_u_tlm_rx_data_snk_latch_1st_dword_q2), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_cur_byte_ct_6_10_), + .Q(com_tlm_u_tlm_rx_data_snk_cur_byte_ct[10]) + ); + FDE com_tlm_u_tlm_rx_data_snk_cur_byte_ct_9_ ( + .CE(com_tlm_u_tlm_rx_data_snk_latch_1st_dword_q2), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_cur_byte_ct_6_9_), + .Q(com_tlm_u_tlm_rx_data_snk_cur_byte_ct[9]) + ); + FDE com_tlm_u_tlm_rx_data_snk_cur_byte_ct_8_ ( + .CE(com_tlm_u_tlm_rx_data_snk_latch_1st_dword_q2), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_cur_byte_ct_6_8_), + .Q(com_tlm_u_tlm_rx_data_snk_cur_byte_ct[8]) + ); + FDE com_tlm_u_tlm_rx_data_snk_cur_byte_ct_7_ ( + .CE(com_tlm_u_tlm_rx_data_snk_latch_1st_dword_q2), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_cur_byte_ct_6_7_), + .Q(com_tlm_u_tlm_rx_data_snk_cur_byte_ct[7]) + ); + FDE com_tlm_u_tlm_rx_data_snk_cur_byte_ct_6_ ( + .CE(com_tlm_u_tlm_rx_data_snk_latch_1st_dword_q2), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_cur_byte_ct_6_6_), + .Q(com_tlm_u_tlm_rx_data_snk_cur_byte_ct[6]) + ); + FDE com_tlm_u_tlm_rx_data_snk_cur_byte_ct_5_ ( + .CE(com_tlm_u_tlm_rx_data_snk_latch_1st_dword_q2), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_cur_byte_ct_6_5_), + .Q(com_tlm_u_tlm_rx_data_snk_cur_byte_ct[5]) + ); + FDE com_tlm_u_tlm_rx_data_snk_cur_byte_ct_4_ ( + .CE(com_tlm_u_tlm_rx_data_snk_latch_1st_dword_q2), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_cur_byte_ct_6_4_), + .Q(com_tlm_u_tlm_rx_data_snk_cur_byte_ct[4]) + ); + FD com_tlm_u_tlm_rx_data_snk_sof_q_5_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_sof_q_4_), + .Q(com_tlm_u_tlm_rx_data_snk_sof_q_5__4070) + ); + FD com_tlm_u_tlm_rx_data_snk_rem_q_5_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_rem_q_4_), + .Q(com_tlm_u_tlm_rx_data_snk_rem_q_5__4071) + ); + FD com_tlm_u_tlm_rx_data_snk_eof_q_5_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_eof_o_3), + .Q(com_tlm_u_tlm_rx_data_snk_eof_q_5__4072) + ); + FD com_tlm_u_tlm_rx_data_snk_eof_q_4_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_eof_q_3__4083), + .Q(com_tlm_u_tlm_rx_data_snk_eof_o_3) + ); + FD com_tlm_u_tlm_rx_data_snk_eof_q_3_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_eof_q_2__4074), + .Q(com_tlm_u_tlm_rx_data_snk_eof_q_3__4083) + ); + FD com_tlm_u_tlm_rx_data_snk_eof_q_2_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_eof_q_1__4073), + .Q(com_tlm_u_tlm_rx_data_snk_eof_q_2__4074) + ); + FD com_tlm_u_tlm_rx_data_snk_dsc_q_5_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_dsc_q_4_), + .Q(com_tlm_u_tlm_rx_data_snk_dsc_q_5__4075) + ); + FD com_tlm_u_tlm_rx_data_snk_lower_addr64_in_q_6_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_lnk_rd[6]), + .Q(com_tlm_u_tlm_rx_data_snk_lower_addr64_in_q[6]) + ); + FD com_tlm_u_tlm_rx_data_snk_lower_addr64_in_q_5_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_lnk_rd[5]), + .Q(com_tlm_u_tlm_rx_data_snk_lower_addr64_in_q[5]) + ); + FD com_tlm_u_tlm_rx_data_snk_lower_addr64_in_q_4_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_lnk_rd[4]), + .Q(com_tlm_u_tlm_rx_data_snk_lower_addr64_in_q[4]) + ); + FD com_tlm_u_tlm_rx_data_snk_lower_addr64_in_q_3_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_lnk_rd[3]), + .Q(com_tlm_u_tlm_rx_data_snk_lower_addr64_in_q[3]) + ); + FD com_tlm_u_tlm_rx_data_snk_lower_addr64_in_q_2_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_lnk_rd[2]), + .Q(com_tlm_u_tlm_rx_data_snk_lower_addr64_in_q[2]) + ); + FD com_tlm_u_tlm_rx_data_snk_lower_addr32_in_q_6_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_lnk_rd_5077[38]), + .Q(com_tlm_u_tlm_rx_data_snk_lower_addr32_in_q[6]) + ); + FD com_tlm_u_tlm_rx_data_snk_lower_addr32_in_q_5_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_lnk_rd_5077[37]), + .Q(com_tlm_u_tlm_rx_data_snk_lower_addr32_in_q[5]) + ); + FD com_tlm_u_tlm_rx_data_snk_lower_addr32_in_q_4_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_lnk_rd_5077[36]), + .Q(com_tlm_u_tlm_rx_data_snk_lower_addr32_in_q[4]) + ); + FD com_tlm_u_tlm_rx_data_snk_lower_addr32_in_q_3_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_lnk_rd_5077[35]), + .Q(com_tlm_u_tlm_rx_data_snk_lower_addr32_in_q[3]) + ); + FD com_tlm_u_tlm_rx_data_snk_lower_addr32_in_q_2_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_lnk_rd_5077[34]), + .Q(com_tlm_u_tlm_rx_data_snk_lower_addr32_in_q[2]) + ); + FD com_tlm_u_tlm_rx_data_snk_src_rdy_q_5_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_src_rdy_q_4_), + .Q(com_tlm_u_tlm_rx_data_snk_src_rdy_q_5__4076) + ); + FDE com_tlm_u_tlm_rx_data_snk_cur_cpl ( + .CE(com_tlm_u_tlm_rx_data_snk_latch_1st_dword_q2), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_cur_fulltype_oh_0__4094), + .Q(com_tlm_u_tlm_rx_data_snk_cur_cpl_4084) + ); + FDE com_tlm_u_tlm_rx_data_snk_bar_o_6_ ( + .CE(com_tlm_u_tlm_rx_data_snk_sof_q_4_), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmmt_rbar_hit[6]), + .Q(com_tlm_u_tlm_rx_ds_bar[6]) + ); + FDE com_tlm_u_tlm_rx_data_snk_bar_o_5_ ( + .CE(com_tlm_u_tlm_rx_data_snk_sof_q_4_), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmmt_rbar_hit[5]), + .Q(com_tlm_u_tlm_rx_ds_bar[5]) + ); + FDE com_tlm_u_tlm_rx_data_snk_bar_o_4_ ( + .CE(com_tlm_u_tlm_rx_data_snk_sof_q_4_), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmmt_rbar_hit[4]), + .Q(com_tlm_u_tlm_rx_ds_bar[4]) + ); + FDE com_tlm_u_tlm_rx_data_snk_bar_o_3_ ( + .CE(com_tlm_u_tlm_rx_data_snk_sof_q_4_), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmmt_rbar_hit[3]), + .Q(com_tlm_u_tlm_rx_ds_bar[3]) + ); + FDE com_tlm_u_tlm_rx_data_snk_bar_o_2_ ( + .CE(com_tlm_u_tlm_rx_data_snk_sof_q_4_), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmmt_rbar_hit[2]), + .Q(com_tlm_u_tlm_rx_ds_bar[2]) + ); + FDE com_tlm_u_tlm_rx_data_snk_bar_o_1_ ( + .CE(com_tlm_u_tlm_rx_data_snk_sof_q_4_), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmmt_rbar_hit[1]), + .Q(com_tlm_u_tlm_rx_ds_bar[1]) + ); + FDE com_tlm_u_tlm_rx_data_snk_bar_o_0_ ( + .CE(com_tlm_u_tlm_rx_data_snk_sof_q_4_), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmmt_rbar_hit[0]), + .Q(com_tlm_u_tlm_rx_ds_bar[0]) + ); + FDE com_tlm_u_tlm_rx_data_snk_cur_cpl_header_fmt_28_ ( + .CE(com_tlm_u_tlm_rx_data_snk_latch_1st_dword_q2), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_cur_tc[2]), + .Q(com_tlm_u_tlm_rx_data_snk_cur_cpl_header_fmt[28]) + ); + FDE com_tlm_u_tlm_rx_data_snk_cur_cpl_header_fmt_27_ ( + .CE(com_tlm_u_tlm_rx_data_snk_latch_1st_dword_q2), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_cur_tc[1]), + .Q(com_tlm_u_tlm_rx_data_snk_cur_cpl_header_fmt[27]) + ); + FDE com_tlm_u_tlm_rx_data_snk_cur_cpl_header_fmt_26_ ( + .CE(com_tlm_u_tlm_rx_data_snk_latch_1st_dword_q2), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_cur_tc[0]), + .Q(com_tlm_u_tlm_rx_data_snk_cur_cpl_header_fmt[26]) + ); + FDE com_tlm_u_tlm_rx_data_snk_cur_cpl_header_fmt_25_ ( + .CE(com_tlm_u_tlm_rx_data_snk_latch_1st_dword_q2), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_cur_attr[1]), + .Q(com_tlm_u_tlm_rx_data_snk_cur_cpl_header_fmt[25]) + ); + FDE com_tlm_u_tlm_rx_data_snk_cur_cpl_header_fmt_24_ ( + .CE(com_tlm_u_tlm_rx_data_snk_latch_1st_dword_q2), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_cur_attr[0]), + .Q(com_tlm_u_tlm_rx_data_snk_cur_cpl_header_fmt[24]) + ); + FDE com_tlm_u_tlm_rx_data_snk_cur_cpl_header_fmt_23_ ( + .CE(com_tlm_u_tlm_rx_data_snk_latch_1st_dword_q2), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_cur_req_id[15]), + .Q(com_tlm_u_tlm_rx_data_snk_cur_cpl_header_fmt[23]) + ); + FDE com_tlm_u_tlm_rx_data_snk_cur_cpl_header_fmt_22_ ( + .CE(com_tlm_u_tlm_rx_data_snk_latch_1st_dword_q2), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_cur_req_id[14]), + .Q(com_tlm_u_tlm_rx_data_snk_cur_cpl_header_fmt[22]) + ); + FDE com_tlm_u_tlm_rx_data_snk_cur_cpl_header_fmt_21_ ( + .CE(com_tlm_u_tlm_rx_data_snk_latch_1st_dword_q2), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_cur_req_id[13]), + .Q(com_tlm_u_tlm_rx_data_snk_cur_cpl_header_fmt[21]) + ); + FDE com_tlm_u_tlm_rx_data_snk_cur_cpl_header_fmt_20_ ( + .CE(com_tlm_u_tlm_rx_data_snk_latch_1st_dword_q2), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_cur_req_id[12]), + .Q(com_tlm_u_tlm_rx_data_snk_cur_cpl_header_fmt[20]) + ); + FDE com_tlm_u_tlm_rx_data_snk_cur_cpl_header_fmt_19_ ( + .CE(com_tlm_u_tlm_rx_data_snk_latch_1st_dword_q2), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_cur_req_id[11]), + .Q(com_tlm_u_tlm_rx_data_snk_cur_cpl_header_fmt[19]) + ); + FDE com_tlm_u_tlm_rx_data_snk_cur_cpl_header_fmt_18_ ( + .CE(com_tlm_u_tlm_rx_data_snk_latch_1st_dword_q2), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_cur_req_id[10]), + .Q(com_tlm_u_tlm_rx_data_snk_cur_cpl_header_fmt[18]) + ); + FDE com_tlm_u_tlm_rx_data_snk_cur_cpl_header_fmt_17_ ( + .CE(com_tlm_u_tlm_rx_data_snk_latch_1st_dword_q2), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_cur_req_id[9]), + .Q(com_tlm_u_tlm_rx_data_snk_cur_cpl_header_fmt[17]) + ); + FDE com_tlm_u_tlm_rx_data_snk_cur_cpl_header_fmt_16_ ( + .CE(com_tlm_u_tlm_rx_data_snk_latch_1st_dword_q2), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_cur_req_id[8]), + .Q(com_tlm_u_tlm_rx_data_snk_cur_cpl_header_fmt[16]) + ); + FDE com_tlm_u_tlm_rx_data_snk_cur_cpl_header_fmt_15_ ( + .CE(com_tlm_u_tlm_rx_data_snk_latch_1st_dword_q2), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_cur_req_id[7]), + .Q(com_tlm_u_tlm_rx_data_snk_cur_cpl_header_fmt[15]) + ); + FDE com_tlm_u_tlm_rx_data_snk_cur_cpl_header_fmt_14_ ( + .CE(com_tlm_u_tlm_rx_data_snk_latch_1st_dword_q2), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_cur_req_id[6]), + .Q(com_tlm_u_tlm_rx_data_snk_cur_cpl_header_fmt[14]) + ); + FDE com_tlm_u_tlm_rx_data_snk_cur_cpl_header_fmt_13_ ( + .CE(com_tlm_u_tlm_rx_data_snk_latch_1st_dword_q2), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_cur_req_id[5]), + .Q(com_tlm_u_tlm_rx_data_snk_cur_cpl_header_fmt[13]) + ); + FDE com_tlm_u_tlm_rx_data_snk_cur_cpl_header_fmt_12_ ( + .CE(com_tlm_u_tlm_rx_data_snk_latch_1st_dword_q2), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_cur_req_id[4]), + .Q(com_tlm_u_tlm_rx_data_snk_cur_cpl_header_fmt[12]) + ); + FDE com_tlm_u_tlm_rx_data_snk_cur_cpl_header_fmt_11_ ( + .CE(com_tlm_u_tlm_rx_data_snk_latch_1st_dword_q2), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_cur_req_id[3]), + .Q(com_tlm_u_tlm_rx_data_snk_cur_cpl_header_fmt[11]) + ); + FDE com_tlm_u_tlm_rx_data_snk_cur_cpl_header_fmt_10_ ( + .CE(com_tlm_u_tlm_rx_data_snk_latch_1st_dword_q2), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_cur_req_id[2]), + .Q(com_tlm_u_tlm_rx_data_snk_cur_cpl_header_fmt[10]) + ); + FDE com_tlm_u_tlm_rx_data_snk_cur_cpl_header_fmt_9_ ( + .CE(com_tlm_u_tlm_rx_data_snk_latch_1st_dword_q2), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_cur_req_id[1]), + .Q(com_tlm_u_tlm_rx_data_snk_cur_cpl_header_fmt[9]) + ); + FDE com_tlm_u_tlm_rx_data_snk_cur_cpl_header_fmt_8_ ( + .CE(com_tlm_u_tlm_rx_data_snk_latch_1st_dword_q2), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_cur_req_id[0]), + .Q(com_tlm_u_tlm_rx_data_snk_cur_cpl_header_fmt[8]) + ); + FDE com_tlm_u_tlm_rx_data_snk_cur_cpl_header_fmt_7_ ( + .CE(com_tlm_u_tlm_rx_data_snk_latch_1st_dword_q2), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_cur_tag[7]), + .Q(com_tlm_u_tlm_rx_data_snk_cur_cpl_header_fmt[7]) + ); + FDE com_tlm_u_tlm_rx_data_snk_cur_cpl_header_fmt_6_ ( + .CE(com_tlm_u_tlm_rx_data_snk_latch_1st_dword_q2), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_cur_tag[6]), + .Q(com_tlm_u_tlm_rx_data_snk_cur_cpl_header_fmt[6]) + ); + FDE com_tlm_u_tlm_rx_data_snk_cur_cpl_header_fmt_5_ ( + .CE(com_tlm_u_tlm_rx_data_snk_latch_1st_dword_q2), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_cur_tag[5]), + .Q(com_tlm_u_tlm_rx_data_snk_cur_cpl_header_fmt[5]) + ); + FDE com_tlm_u_tlm_rx_data_snk_cur_cpl_header_fmt_4_ ( + .CE(com_tlm_u_tlm_rx_data_snk_latch_1st_dword_q2), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_cur_tag[4]), + .Q(com_tlm_u_tlm_rx_data_snk_cur_cpl_header_fmt[4]) + ); + FDE com_tlm_u_tlm_rx_data_snk_cur_cpl_header_fmt_3_ ( + .CE(com_tlm_u_tlm_rx_data_snk_latch_1st_dword_q2), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_cur_tag[3]), + .Q(com_tlm_u_tlm_rx_data_snk_cur_cpl_header_fmt[3]) + ); + FDE com_tlm_u_tlm_rx_data_snk_cur_cpl_header_fmt_2_ ( + .CE(com_tlm_u_tlm_rx_data_snk_latch_1st_dword_q2), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_cur_tag[2]), + .Q(com_tlm_u_tlm_rx_data_snk_cur_cpl_header_fmt[2]) + ); + FDE com_tlm_u_tlm_rx_data_snk_cur_cpl_header_fmt_1_ ( + .CE(com_tlm_u_tlm_rx_data_snk_latch_1st_dword_q2), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_cur_tag[1]), + .Q(com_tlm_u_tlm_rx_data_snk_cur_cpl_header_fmt[1]) + ); + FDE com_tlm_u_tlm_rx_data_snk_cur_cpl_header_fmt_0_ ( + .CE(com_tlm_u_tlm_rx_data_snk_latch_1st_dword_q2), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_cur_tag[0]), + .Q(com_tlm_u_tlm_rx_data_snk_cur_cpl_header_fmt[0]) + ); + FDE com_tlm_u_tlm_rx_data_snk_cur_ep_q ( + .CE(com_tlm_u_tlm_rx_data_snk_latch_1st_dword_q2), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_cur_ep_4079), + .Q(com_tlm_u_tlm_rx_data_snk_cur_ep_q_4077) + ); + FDE com_tlm_u_tlm_rx_data_snk_cur_td_q ( + .CE(com_tlm_u_tlm_rx_data_snk_latch_1st_dword_q2), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_cur_td_4080), + .Q(com_tlm_u_tlm_rx_data_snk_cur_td_q_4078) + ); + FDE com_tlm_u_tlm_rx_data_snk_cur_attr_1_ ( + .CE(com_tlm_u_tlm_rx_data_snk_latch_2nd_dword), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_lnk_rd_5077[45]), + .Q(com_tlm_u_tlm_rx_data_snk_cur_attr[1]) + ); + FDE com_tlm_u_tlm_rx_data_snk_cur_attr_0_ ( + .CE(com_tlm_u_tlm_rx_data_snk_latch_2nd_dword), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_lnk_rd_5077[44]), + .Q(com_tlm_u_tlm_rx_data_snk_cur_attr[0]) + ); + FDE com_tlm_u_tlm_rx_data_snk_cur_ep ( + .CE(com_tlm_u_tlm_rx_data_snk_latch_2nd_dword), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_lnk_rd_5077[46]), + .Q(com_tlm_u_tlm_rx_data_snk_cur_ep_4079) + ); + FDE com_tlm_u_tlm_rx_data_snk_cur_length_9_ ( + .CE(com_tlm_u_tlm_rx_data_snk_latch_2nd_dword), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_lnk_rd_5077[41]), + .Q(com_tlm_u_tlm_rx_data_snk_cur_length_9__14) + ); + FDE com_tlm_u_tlm_rx_data_snk_cur_length_8_ ( + .CE(com_tlm_u_tlm_rx_data_snk_latch_2nd_dword), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_lnk_rd_5077[40]), + .Q(com_tlm_u_tlm_rx_data_snk_cur_length_8__12) + ); + FDE com_tlm_u_tlm_rx_data_snk_cur_length_7_ ( + .CE(com_tlm_u_tlm_rx_data_snk_latch_2nd_dword), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_lnk_rd_5077[39]), + .Q(com_tlm_u_tlm_rx_data_snk_cur_length[7]) + ); + FDE com_tlm_u_tlm_rx_data_snk_cur_length_6_ ( + .CE(com_tlm_u_tlm_rx_data_snk_latch_2nd_dword), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_lnk_rd_5077[38]), + .Q(com_tlm_u_tlm_rx_data_snk_cur_length[6]) + ); + FDE com_tlm_u_tlm_rx_data_snk_cur_length_5_ ( + .CE(com_tlm_u_tlm_rx_data_snk_latch_2nd_dword), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_lnk_rd_5077[37]), + .Q(com_tlm_u_tlm_rx_data_snk_cur_length[5]) + ); + FDE com_tlm_u_tlm_rx_data_snk_cur_length_4_ ( + .CE(com_tlm_u_tlm_rx_data_snk_latch_2nd_dword), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_lnk_rd_5077[36]), + .Q(com_tlm_u_tlm_rx_data_snk_cur_length_4__10) + ); + FDE com_tlm_u_tlm_rx_data_snk_cur_length_3_ ( + .CE(com_tlm_u_tlm_rx_data_snk_latch_2nd_dword), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_lnk_rd_5077[35]), + .Q(com_tlm_u_tlm_rx_data_snk_cur_length_3__8) + ); + FDE com_tlm_u_tlm_rx_data_snk_cur_length_2_ ( + .CE(com_tlm_u_tlm_rx_data_snk_latch_2nd_dword), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_lnk_rd_5077[34]), + .Q(com_tlm_u_tlm_rx_data_snk_cur_length_2__6) + ); + FDE com_tlm_u_tlm_rx_data_snk_cur_length_1_ ( + .CE(com_tlm_u_tlm_rx_data_snk_latch_2nd_dword), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_lnk_rd_5077[33]), + .Q(com_tlm_u_tlm_rx_data_snk_cur_length_1__4) + ); + FDE com_tlm_u_tlm_rx_data_snk_cur_length_0_ ( + .CE(com_tlm_u_tlm_rx_data_snk_latch_2nd_dword), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_lnk_rd_5077[32]), + .Q(com_tlm_u_tlm_rx_data_snk_cur_length_0__2) + ); + FDE com_tlm_u_tlm_rx_data_snk_cur_tc_2_ ( + .CE(com_tlm_u_tlm_rx_data_snk_latch_2nd_dword), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_lnk_rd_5077[54]), + .Q(com_tlm_u_tlm_rx_data_snk_cur_tc[2]) + ); + FDE com_tlm_u_tlm_rx_data_snk_cur_tc_1_ ( + .CE(com_tlm_u_tlm_rx_data_snk_latch_2nd_dword), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_lnk_rd_5077[53]), + .Q(com_tlm_u_tlm_rx_data_snk_cur_tc[1]) + ); + FDE com_tlm_u_tlm_rx_data_snk_cur_tc_0_ ( + .CE(com_tlm_u_tlm_rx_data_snk_latch_2nd_dword), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_lnk_rd_5077[52]), + .Q(com_tlm_u_tlm_rx_data_snk_cur_tc[0]) + ); + FDE com_tlm_u_tlm_rx_data_snk_cur_td ( + .CE(com_tlm_u_tlm_rx_data_snk_latch_2nd_dword), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_lnk_rd_5077[47]), + .Q(com_tlm_u_tlm_rx_data_snk_cur_td_4080) + ); + FDE com_tlm_u_tlm_rx_data_snk_cur_cpl_stat_2_ ( + .CE(com_tlm_u_tlm_rx_data_snk_latch_2nd_dword), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_lnk_rd_5077[15]), + .Q(com_tlm_u_tlm_rx_data_snk_cur_tag[7]) + ); + FDE com_tlm_u_tlm_rx_data_snk_cur_cpl_stat_1_ ( + .CE(com_tlm_u_tlm_rx_data_snk_latch_2nd_dword), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_lnk_rd_5077[14]), + .Q(com_tlm_u_tlm_rx_data_snk_cur_tag[6]) + ); + FDE com_tlm_u_tlm_rx_data_snk_cur_cpl_stat_0_ ( + .CE(com_tlm_u_tlm_rx_data_snk_latch_2nd_dword), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_lnk_rd_5077[13]), + .Q(com_tlm_u_tlm_rx_data_snk_cur_tag[5]) + ); + FDE com_tlm_u_tlm_rx_data_snk_cur_msgcode_7_ ( + .CE(com_tlm_u_tlm_rx_data_snk_latch_2nd_dword), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_lnk_rd_5077[7]), + .Q(com_tlm_u_tlm_rx_data_snk_cur_msgcode[7]) + ); + FDE com_tlm_u_tlm_rx_data_snk_cur_msgcode_6_ ( + .CE(com_tlm_u_tlm_rx_data_snk_latch_2nd_dword), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_lnk_rd[6]), + .Q(com_tlm_u_tlm_rx_data_snk_cur_msgcode[6]) + ); + FDE com_tlm_u_tlm_rx_data_snk_cur_msgcode_5_ ( + .CE(com_tlm_u_tlm_rx_data_snk_latch_2nd_dword), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_lnk_rd[5]), + .Q(com_tlm_u_tlm_rx_data_snk_cur_msgcode[5]) + ); + FDE com_tlm_u_tlm_rx_data_snk_cur_msgcode_4_ ( + .CE(com_tlm_u_tlm_rx_data_snk_latch_2nd_dword), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_lnk_rd[4]), + .Q(com_tlm_u_tlm_rx_data_snk_cur_msgcode[4]) + ); + FDE com_tlm_u_tlm_rx_data_snk_cur_msgcode_3_ ( + .CE(com_tlm_u_tlm_rx_data_snk_latch_2nd_dword), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_lnk_rd[3]), + .Q(com_tlm_u_tlm_rx_data_snk_cur_msgcode[3]) + ); + FDE com_tlm_u_tlm_rx_data_snk_cur_msgcode_2_ ( + .CE(com_tlm_u_tlm_rx_data_snk_latch_2nd_dword), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_lnk_rd[2]), + .Q(com_tlm_u_tlm_rx_data_snk_cur_msgcode[2]) + ); + FDE com_tlm_u_tlm_rx_data_snk_cur_msgcode_1_ ( + .CE(com_tlm_u_tlm_rx_data_snk_latch_2nd_dword), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_lnk_rd[1]), + .Q(com_tlm_u_tlm_rx_data_snk_cur_msgcode[1]) + ); + FDE com_tlm_u_tlm_rx_data_snk_cur_msgcode_0_ ( + .CE(com_tlm_u_tlm_rx_data_snk_latch_2nd_dword), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_lnk_rd[0]), + .Q(com_tlm_u_tlm_rx_data_snk_cur_msgcode[0]) + ); + FDE com_tlm_u_tlm_rx_data_snk_cur_req_id_15_ ( + .CE(com_tlm_u_tlm_rx_data_snk_latch_2nd_dword), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_lnk_rd_5077[31]), + .Q(com_tlm_u_tlm_rx_data_snk_cur_req_id[15]) + ); + FDE com_tlm_u_tlm_rx_data_snk_cur_req_id_14_ ( + .CE(com_tlm_u_tlm_rx_data_snk_latch_2nd_dword), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_lnk_rd_5077[30]), + .Q(com_tlm_u_tlm_rx_data_snk_cur_req_id[14]) + ); + FDE com_tlm_u_tlm_rx_data_snk_cur_req_id_13_ ( + .CE(com_tlm_u_tlm_rx_data_snk_latch_2nd_dword), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_lnk_rd_5077[29]), + .Q(com_tlm_u_tlm_rx_data_snk_cur_req_id[13]) + ); + FDE com_tlm_u_tlm_rx_data_snk_cur_req_id_12_ ( + .CE(com_tlm_u_tlm_rx_data_snk_latch_2nd_dword), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_lnk_rd_5077[28]), + .Q(com_tlm_u_tlm_rx_data_snk_cur_req_id[12]) + ); + FDE com_tlm_u_tlm_rx_data_snk_cur_req_id_11_ ( + .CE(com_tlm_u_tlm_rx_data_snk_latch_2nd_dword), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_lnk_rd_5077[27]), + .Q(com_tlm_u_tlm_rx_data_snk_cur_req_id[11]) + ); + FDE com_tlm_u_tlm_rx_data_snk_cur_req_id_10_ ( + .CE(com_tlm_u_tlm_rx_data_snk_latch_2nd_dword), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_lnk_rd_5077[26]), + .Q(com_tlm_u_tlm_rx_data_snk_cur_req_id[10]) + ); + FDE com_tlm_u_tlm_rx_data_snk_cur_req_id_9_ ( + .CE(com_tlm_u_tlm_rx_data_snk_latch_2nd_dword), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_lnk_rd_5077[25]), + .Q(com_tlm_u_tlm_rx_data_snk_cur_req_id[9]) + ); + FDE com_tlm_u_tlm_rx_data_snk_cur_req_id_8_ ( + .CE(com_tlm_u_tlm_rx_data_snk_latch_2nd_dword), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_lnk_rd_5077[24]), + .Q(com_tlm_u_tlm_rx_data_snk_cur_req_id[8]) + ); + FDE com_tlm_u_tlm_rx_data_snk_cur_req_id_7_ ( + .CE(com_tlm_u_tlm_rx_data_snk_latch_2nd_dword), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_lnk_rd_5077[23]), + .Q(com_tlm_u_tlm_rx_data_snk_cur_req_id[7]) + ); + FDE com_tlm_u_tlm_rx_data_snk_cur_req_id_6_ ( + .CE(com_tlm_u_tlm_rx_data_snk_latch_2nd_dword), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_lnk_rd_5077[22]), + .Q(com_tlm_u_tlm_rx_data_snk_cur_req_id[6]) + ); + FDE com_tlm_u_tlm_rx_data_snk_cur_req_id_5_ ( + .CE(com_tlm_u_tlm_rx_data_snk_latch_2nd_dword), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_lnk_rd_5077[21]), + .Q(com_tlm_u_tlm_rx_data_snk_cur_req_id[5]) + ); + FDE com_tlm_u_tlm_rx_data_snk_cur_req_id_4_ ( + .CE(com_tlm_u_tlm_rx_data_snk_latch_2nd_dword), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_lnk_rd_5077[20]), + .Q(com_tlm_u_tlm_rx_data_snk_cur_req_id[4]) + ); + FDE com_tlm_u_tlm_rx_data_snk_cur_req_id_3_ ( + .CE(com_tlm_u_tlm_rx_data_snk_latch_2nd_dword), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_lnk_rd_5077[19]), + .Q(com_tlm_u_tlm_rx_data_snk_cur_req_id[3]) + ); + FDE com_tlm_u_tlm_rx_data_snk_cur_req_id_2_ ( + .CE(com_tlm_u_tlm_rx_data_snk_latch_2nd_dword), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_lnk_rd_5077[18]), + .Q(com_tlm_u_tlm_rx_data_snk_cur_req_id[2]) + ); + FDE com_tlm_u_tlm_rx_data_snk_cur_req_id_1_ ( + .CE(com_tlm_u_tlm_rx_data_snk_latch_2nd_dword), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_lnk_rd_5077[17]), + .Q(com_tlm_u_tlm_rx_data_snk_cur_req_id[1]) + ); + FDE com_tlm_u_tlm_rx_data_snk_cur_req_id_0_ ( + .CE(com_tlm_u_tlm_rx_data_snk_latch_2nd_dword), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_lnk_rd_5077[16]), + .Q(com_tlm_u_tlm_rx_data_snk_cur_req_id[0]) + ); + FDE com_tlm_u_tlm_rx_data_snk_cur_tag_4_ ( + .CE(com_tlm_u_tlm_rx_data_snk_latch_2nd_dword), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_lnk_rd_5077[12]), + .Q(com_tlm_u_tlm_rx_data_snk_cur_tag[4]) + ); + FDE com_tlm_u_tlm_rx_data_snk_cur_tag_3_ ( + .CE(com_tlm_u_tlm_rx_data_snk_latch_2nd_dword), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_lnk_rd_5077[11]), + .Q(com_tlm_u_tlm_rx_data_snk_cur_tag[3]) + ); + FDE com_tlm_u_tlm_rx_data_snk_cur_tag_2_ ( + .CE(com_tlm_u_tlm_rx_data_snk_latch_2nd_dword), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_lnk_rd_5077[10]), + .Q(com_tlm_u_tlm_rx_data_snk_cur_tag[2]) + ); + FDE com_tlm_u_tlm_rx_data_snk_cur_tag_1_ ( + .CE(com_tlm_u_tlm_rx_data_snk_latch_2nd_dword), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_lnk_rd_5077[9]), + .Q(com_tlm_u_tlm_rx_data_snk_cur_tag[1]) + ); + FDE com_tlm_u_tlm_rx_data_snk_cur_tag_0_ ( + .CE(com_tlm_u_tlm_rx_data_snk_latch_2nd_dword), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_lnk_rd_5077[8]), + .Q(com_tlm_u_tlm_rx_data_snk_cur_tag[0]) + ); + FDE com_tlm_u_tlm_rx_data_snk_cur_rem ( + .CE(com_tlm_u_tlm_rx_data_snk_cur_rem_0_sqmuxa), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_lnk_rrem[0]), + .Q(com_tlm_u_tlm_rx_data_snk_cur_rem_4081) + ); + FDE com_tlm_u_tlm_rx_data_snk_cur_np ( + .CE(com_tlm_u_tlm_rx_data_snk_latch_1st_dword_q2), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_cur_np_2), + .Q(com_tlm_u_tlm_rx_data_snk_cur_np_4086) + ); + FDE com_tlm_u_tlm_rx_data_snk_cur_tc0 ( + .CE(com_tlm_u_tlm_rx_data_snk_latch_2nd_dword), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_cur_tc0_2), + .Q(com_tlm_u_tlm_rx_data_snk_cur_tc0_4082) + ); + FDE com_tlm_u_tlm_rx_data_snk_fc_use_data_o_5_ ( + .CE(com_tlm_u_tlm_rx_data_snk_cur_data_credits_vld), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_cur_data_credits[5]), + .Q(com_tlm_u_tlm_rx_fc_use_data[5]) + ); + FDE com_tlm_u_tlm_rx_data_snk_fc_use_data_o_4_ ( + .CE(com_tlm_u_tlm_rx_data_snk_cur_data_credits_vld), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_cur_data_credits[4]), + .Q(com_tlm_u_tlm_rx_fc_use_data[4]) + ); + FDE com_tlm_u_tlm_rx_data_snk_fc_use_data_o_3_ ( + .CE(com_tlm_u_tlm_rx_data_snk_cur_data_credits_vld), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_cur_data_credits[3]), + .Q(com_tlm_u_tlm_rx_fc_use_data[3]) + ); + FDE com_tlm_u_tlm_rx_data_snk_fc_use_data_o_2_ ( + .CE(com_tlm_u_tlm_rx_data_snk_cur_data_credits_vld), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_cur_data_credits[2]), + .Q(com_tlm_u_tlm_rx_fc_use_data[2]) + ); + FDE com_tlm_u_tlm_rx_data_snk_fc_use_data_o_1_ ( + .CE(com_tlm_u_tlm_rx_data_snk_cur_data_credits_vld), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_cur_data_credits[1]), + .Q(com_tlm_u_tlm_rx_fc_use_data[1]) + ); + FDE com_tlm_u_tlm_rx_data_snk_fc_use_data_o_0_ ( + .CE(com_tlm_u_tlm_rx_data_snk_cur_data_credits_vld), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_cur_data_credits[0]), + .Q(com_tlm_u_tlm_rx_fc_use_data[0]) + ); + FDE com_tlm_u_tlm_rx_data_snk_err_tlp_cpl_header_o_47_ ( + .CE(com_tlm_u_tlm_rx_data_snk_eof_q_3__4083), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_cur_lower_addr[6]), + .Q(com_cmmt_err_tlp_hdr[47]) + ); + FDE com_tlm_u_tlm_rx_data_snk_err_tlp_cpl_header_o_46_ ( + .CE(com_tlm_u_tlm_rx_data_snk_eof_q_3__4083), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_cur_lower_addr[5]), + .Q(com_cmmt_err_tlp_hdr[46]) + ); + FDE com_tlm_u_tlm_rx_data_snk_err_tlp_cpl_header_o_45_ ( + .CE(com_tlm_u_tlm_rx_data_snk_eof_q_3__4083), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_cur_lower_addr[4]), + .Q(com_cmmt_err_tlp_hdr[45]) + ); + FDE com_tlm_u_tlm_rx_data_snk_err_tlp_cpl_header_o_44_ ( + .CE(com_tlm_u_tlm_rx_data_snk_eof_q_3__4083), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_cur_lower_addr[3]), + .Q(com_cmmt_err_tlp_hdr[44]) + ); + FDE com_tlm_u_tlm_rx_data_snk_err_tlp_cpl_header_o_43_ ( + .CE(com_tlm_u_tlm_rx_data_snk_eof_q_3__4083), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_cur_lower_addr[2]), + .Q(com_cmmt_err_tlp_hdr[43]) + ); + FDE com_tlm_u_tlm_rx_data_snk_err_tlp_cpl_header_o_42_ ( + .CE(com_tlm_u_tlm_rx_data_snk_eof_q_3__4083), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_cur_lower_addr[1]), + .Q(com_cmmt_err_tlp_hdr[42]) + ); + FDE com_tlm_u_tlm_rx_data_snk_err_tlp_cpl_header_o_41_ ( + .CE(com_tlm_u_tlm_rx_data_snk_eof_q_3__4083), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_cur_lower_addr[0]), + .Q(com_cmmt_err_tlp_hdr[41]) + ); + FDE com_tlm_u_tlm_rx_data_snk_err_tlp_cpl_header_o_40_ ( + .CE(com_tlm_u_tlm_rx_data_snk_eof_q_3__4083), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_cur_byte_ct[11]), + .Q(com_cmmt_err_tlp_hdr[40]) + ); + FDE com_tlm_u_tlm_rx_data_snk_err_tlp_cpl_header_o_39_ ( + .CE(com_tlm_u_tlm_rx_data_snk_eof_q_3__4083), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_cur_byte_ct[10]), + .Q(com_cmmt_err_tlp_hdr[39]) + ); + FDE com_tlm_u_tlm_rx_data_snk_err_tlp_cpl_header_o_38_ ( + .CE(com_tlm_u_tlm_rx_data_snk_eof_q_3__4083), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_cur_byte_ct[9]), + .Q(com_cmmt_err_tlp_hdr[38]) + ); + FDE com_tlm_u_tlm_rx_data_snk_err_tlp_cpl_header_o_37_ ( + .CE(com_tlm_u_tlm_rx_data_snk_eof_q_3__4083), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_cur_byte_ct[8]), + .Q(com_cmmt_err_tlp_hdr[37]) + ); + FDE com_tlm_u_tlm_rx_data_snk_err_tlp_cpl_header_o_36_ ( + .CE(com_tlm_u_tlm_rx_data_snk_eof_q_3__4083), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_cur_byte_ct[7]), + .Q(com_cmmt_err_tlp_hdr[36]) + ); + FDE com_tlm_u_tlm_rx_data_snk_err_tlp_cpl_header_o_35_ ( + .CE(com_tlm_u_tlm_rx_data_snk_eof_q_3__4083), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_cur_byte_ct[6]), + .Q(com_cmmt_err_tlp_hdr[35]) + ); + FDE com_tlm_u_tlm_rx_data_snk_err_tlp_cpl_header_o_34_ ( + .CE(com_tlm_u_tlm_rx_data_snk_eof_q_3__4083), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_cur_byte_ct[5]), + .Q(com_cmmt_err_tlp_hdr[34]) + ); + FDE com_tlm_u_tlm_rx_data_snk_err_tlp_cpl_header_o_33_ ( + .CE(com_tlm_u_tlm_rx_data_snk_eof_q_3__4083), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_cur_byte_ct[4]), + .Q(com_cmmt_err_tlp_hdr[33]) + ); + FDE com_tlm_u_tlm_rx_data_snk_err_tlp_cpl_header_o_32_ ( + .CE(com_tlm_u_tlm_rx_data_snk_eof_q_3__4083), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_cur_byte_ct[3]), + .Q(com_cmmt_err_tlp_hdr[32]) + ); + FDE com_tlm_u_tlm_rx_data_snk_err_tlp_cpl_header_o_31_ ( + .CE(com_tlm_u_tlm_rx_data_snk_eof_q_3__4083), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_cur_byte_ct[2]), + .Q(com_cmmt_err_tlp_hdr[31]) + ); + FDE com_tlm_u_tlm_rx_data_snk_err_tlp_cpl_header_o_30_ ( + .CE(com_tlm_u_tlm_rx_data_snk_eof_q_3__4083), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_cur_byte_ct[1]), + .Q(com_cmmt_err_tlp_hdr[30]) + ); + FDE com_tlm_u_tlm_rx_data_snk_err_tlp_cpl_header_o_29_ ( + .CE(com_tlm_u_tlm_rx_data_snk_eof_q_3__4083), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_cur_byte_ct[0]), + .Q(com_cmmt_err_tlp_hdr[29]) + ); + FDE com_tlm_u_tlm_rx_data_snk_err_tlp_cpl_header_o_28_ ( + .CE(com_tlm_u_tlm_rx_data_snk_eof_q_3__4083), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_cur_cpl_header_fmt[28]), + .Q(com_cmmt_err_tlp_hdr[28]) + ); + FDE com_tlm_u_tlm_rx_data_snk_err_tlp_cpl_header_o_27_ ( + .CE(com_tlm_u_tlm_rx_data_snk_eof_q_3__4083), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_cur_cpl_header_fmt[27]), + .Q(com_cmmt_err_tlp_hdr[27]) + ); + FDE com_tlm_u_tlm_rx_data_snk_err_tlp_cpl_header_o_26_ ( + .CE(com_tlm_u_tlm_rx_data_snk_eof_q_3__4083), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_cur_cpl_header_fmt[26]), + .Q(com_cmmt_err_tlp_hdr[26]) + ); + FDE com_tlm_u_tlm_rx_data_snk_err_tlp_cpl_header_o_25_ ( + .CE(com_tlm_u_tlm_rx_data_snk_eof_q_3__4083), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_cur_cpl_header_fmt[25]), + .Q(com_cmmt_err_tlp_hdr[25]) + ); + FDE com_tlm_u_tlm_rx_data_snk_err_tlp_cpl_header_o_24_ ( + .CE(com_tlm_u_tlm_rx_data_snk_eof_q_3__4083), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_cur_cpl_header_fmt[24]), + .Q(com_cmmt_err_tlp_hdr[24]) + ); + FDE com_tlm_u_tlm_rx_data_snk_err_tlp_cpl_header_o_23_ ( + .CE(com_tlm_u_tlm_rx_data_snk_eof_q_3__4083), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_cur_cpl_header_fmt[23]), + .Q(com_cmmt_err_tlp_hdr[23]) + ); + FDE com_tlm_u_tlm_rx_data_snk_err_tlp_cpl_header_o_22_ ( + .CE(com_tlm_u_tlm_rx_data_snk_eof_q_3__4083), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_cur_cpl_header_fmt[22]), + .Q(com_cmmt_err_tlp_hdr[22]) + ); + FDE com_tlm_u_tlm_rx_data_snk_err_tlp_cpl_header_o_21_ ( + .CE(com_tlm_u_tlm_rx_data_snk_eof_q_3__4083), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_cur_cpl_header_fmt[21]), + .Q(com_cmmt_err_tlp_hdr[21]) + ); + FDE com_tlm_u_tlm_rx_data_snk_err_tlp_cpl_header_o_20_ ( + .CE(com_tlm_u_tlm_rx_data_snk_eof_q_3__4083), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_cur_cpl_header_fmt[20]), + .Q(com_cmmt_err_tlp_hdr[20]) + ); + FDE com_tlm_u_tlm_rx_data_snk_err_tlp_cpl_header_o_19_ ( + .CE(com_tlm_u_tlm_rx_data_snk_eof_q_3__4083), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_cur_cpl_header_fmt[19]), + .Q(com_cmmt_err_tlp_hdr[19]) + ); + FDE com_tlm_u_tlm_rx_data_snk_err_tlp_cpl_header_o_18_ ( + .CE(com_tlm_u_tlm_rx_data_snk_eof_q_3__4083), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_cur_cpl_header_fmt[18]), + .Q(com_cmmt_err_tlp_hdr[18]) + ); + FDE com_tlm_u_tlm_rx_data_snk_err_tlp_cpl_header_o_17_ ( + .CE(com_tlm_u_tlm_rx_data_snk_eof_q_3__4083), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_cur_cpl_header_fmt[17]), + .Q(com_cmmt_err_tlp_hdr[17]) + ); + FDE com_tlm_u_tlm_rx_data_snk_err_tlp_cpl_header_o_16_ ( + .CE(com_tlm_u_tlm_rx_data_snk_eof_q_3__4083), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_cur_cpl_header_fmt[16]), + .Q(com_cmmt_err_tlp_hdr[16]) + ); + FDE com_tlm_u_tlm_rx_data_snk_err_tlp_cpl_header_o_15_ ( + .CE(com_tlm_u_tlm_rx_data_snk_eof_q_3__4083), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_cur_cpl_header_fmt[15]), + .Q(com_cmmt_err_tlp_hdr[15]) + ); + FDE com_tlm_u_tlm_rx_data_snk_err_tlp_cpl_header_o_14_ ( + .CE(com_tlm_u_tlm_rx_data_snk_eof_q_3__4083), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_cur_cpl_header_fmt[14]), + .Q(com_cmmt_err_tlp_hdr[14]) + ); + FDE com_tlm_u_tlm_rx_data_snk_err_tlp_cpl_header_o_13_ ( + .CE(com_tlm_u_tlm_rx_data_snk_eof_q_3__4083), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_cur_cpl_header_fmt[13]), + .Q(com_cmmt_err_tlp_hdr[13]) + ); + FDE com_tlm_u_tlm_rx_data_snk_err_tlp_cpl_header_o_12_ ( + .CE(com_tlm_u_tlm_rx_data_snk_eof_q_3__4083), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_cur_cpl_header_fmt[12]), + .Q(com_cmmt_err_tlp_hdr[12]) + ); + FDE com_tlm_u_tlm_rx_data_snk_err_tlp_cpl_header_o_11_ ( + .CE(com_tlm_u_tlm_rx_data_snk_eof_q_3__4083), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_cur_cpl_header_fmt[11]), + .Q(com_cmmt_err_tlp_hdr[11]) + ); + FDE com_tlm_u_tlm_rx_data_snk_err_tlp_cpl_header_o_10_ ( + .CE(com_tlm_u_tlm_rx_data_snk_eof_q_3__4083), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_cur_cpl_header_fmt[10]), + .Q(com_cmmt_err_tlp_hdr[10]) + ); + FDE com_tlm_u_tlm_rx_data_snk_err_tlp_cpl_header_o_9_ ( + .CE(com_tlm_u_tlm_rx_data_snk_eof_q_3__4083), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_cur_cpl_header_fmt[9]), + .Q(com_cmmt_err_tlp_hdr[9]) + ); + FDE com_tlm_u_tlm_rx_data_snk_err_tlp_cpl_header_o_8_ ( + .CE(com_tlm_u_tlm_rx_data_snk_eof_q_3__4083), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_cur_cpl_header_fmt[8]), + .Q(com_cmmt_err_tlp_hdr[8]) + ); + FDE com_tlm_u_tlm_rx_data_snk_err_tlp_cpl_header_o_7_ ( + .CE(com_tlm_u_tlm_rx_data_snk_eof_q_3__4083), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_cur_cpl_header_fmt[7]), + .Q(com_cmmt_err_tlp_hdr[7]) + ); + FDE com_tlm_u_tlm_rx_data_snk_err_tlp_cpl_header_o_6_ ( + .CE(com_tlm_u_tlm_rx_data_snk_eof_q_3__4083), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_cur_cpl_header_fmt[6]), + .Q(com_cmmt_err_tlp_hdr[6]) + ); + FDE com_tlm_u_tlm_rx_data_snk_err_tlp_cpl_header_o_5_ ( + .CE(com_tlm_u_tlm_rx_data_snk_eof_q_3__4083), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_cur_cpl_header_fmt[5]), + .Q(com_cmmt_err_tlp_hdr[5]) + ); + FDE com_tlm_u_tlm_rx_data_snk_err_tlp_cpl_header_o_4_ ( + .CE(com_tlm_u_tlm_rx_data_snk_eof_q_3__4083), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_cur_cpl_header_fmt[4]), + .Q(com_cmmt_err_tlp_hdr[4]) + ); + FDE com_tlm_u_tlm_rx_data_snk_err_tlp_cpl_header_o_3_ ( + .CE(com_tlm_u_tlm_rx_data_snk_eof_q_3__4083), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_cur_cpl_header_fmt[3]), + .Q(com_cmmt_err_tlp_hdr[3]) + ); + FDE com_tlm_u_tlm_rx_data_snk_err_tlp_cpl_header_o_2_ ( + .CE(com_tlm_u_tlm_rx_data_snk_eof_q_3__4083), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_cur_cpl_header_fmt[2]), + .Q(com_cmmt_err_tlp_hdr[2]) + ); + FDE com_tlm_u_tlm_rx_data_snk_err_tlp_cpl_header_o_1_ ( + .CE(com_tlm_u_tlm_rx_data_snk_eof_q_3__4083), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_cur_cpl_header_fmt[1]), + .Q(com_cmmt_err_tlp_hdr[1]) + ); + FDE com_tlm_u_tlm_rx_data_snk_err_tlp_cpl_header_o_0_ ( + .CE(com_tlm_u_tlm_rx_data_snk_eof_q_3__4083), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_cur_cpl_header_fmt[0]), + .Q(com_cmmt_err_tlp_hdr[0]) + ); + FDE com_tlm_u_tlm_rx_data_snk_cfg_o ( + .CE(com_tlm_u_tlm_rx_data_snk_latch_1st_dword_q4_4085), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_cur_cfg), + .Q(com_tlm_u_tlm_rx_ds_cfg) + ); + FDE com_tlm_u_tlm_rx_data_snk_cpl_o ( + .CE(com_tlm_u_tlm_rx_data_snk_latch_1st_dword_q4_4085), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_cur_cpl_4084), + .Q(com_tlm_u_tlm_rx_ds_cpl) + ); + FDE com_tlm_u_tlm_rx_data_snk_np_o ( + .CE(com_tlm_u_tlm_rx_data_snk_latch_1st_dword_q4_4085), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_cur_np_4086), + .Q(com_tlm_u_tlm_rx_ds_np) + ); + FDE com_tlm_u_tlm_rx_data_snk_cur_lower_addr_1_ ( + .CE(com_tlm_u_tlm_rx_data_snk_latch_3rd_dword_q1), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_cur_lower_addr_22[1]), + .Q(com_tlm_u_tlm_rx_data_snk_cur_lower_addr[1]) + ); + FDE com_tlm_u_tlm_rx_data_snk_cur_lower_addr_0_ ( + .CE(com_tlm_u_tlm_rx_data_snk_latch_3rd_dword_q1), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_cur_lower_addr_22[0]), + .Q(com_tlm_u_tlm_rx_data_snk_cur_lower_addr[0]) + ); + FDE com_tlm_u_tlm_rx_data_snk_cur_length1 ( + .CE(com_tlm_u_tlm_rx_data_snk_latch_2nd_dword), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_cur_length1_2), + .Q(com_tlm_u_tlm_rx_data_snk_cur_length1_4087) + ); + FDE com_tlm_u_tlm_rx_data_snk_cur_fulltype_64 ( + .CE(com_tlm_u_tlm_rx_data_snk_latch_2nd_dword), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_N_9480_i), + .Q(com_tlm_u_tlm_rx_data_snk_cur_fulltype_64_4088) + ); + FDE com_tlm_u_tlm_rx_data_snk_cur_fulltype_mem ( + .CE(com_tlm_u_tlm_rx_data_snk_latch_2nd_dword), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_cur_fulltype_mem12_i_i), + .Q(com_tlm_u_tlm_rx_data_snk_cur_fulltype_mem_4089) + ); + FDE com_tlm_u_tlm_rx_data_snk_cur_lower_addr_6_ ( + .CE(com_tlm_u_tlm_rx_data_snk_latch_3rd_dword_q1), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_N_21331_i), + .Q(com_tlm_u_tlm_rx_data_snk_cur_lower_addr[6]) + ); + FDE com_tlm_u_tlm_rx_data_snk_cur_lower_addr_5_ ( + .CE(com_tlm_u_tlm_rx_data_snk_latch_3rd_dword_q1), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_N_21329_i), + .Q(com_tlm_u_tlm_rx_data_snk_cur_lower_addr[5]) + ); + FDE com_tlm_u_tlm_rx_data_snk_cur_lower_addr_4_ ( + .CE(com_tlm_u_tlm_rx_data_snk_latch_3rd_dword_q1), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_N_21327_i), + .Q(com_tlm_u_tlm_rx_data_snk_cur_lower_addr[4]) + ); + FDE com_tlm_u_tlm_rx_data_snk_cur_lower_addr_3_ ( + .CE(com_tlm_u_tlm_rx_data_snk_latch_3rd_dword_q1), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_N_21325_i), + .Q(com_tlm_u_tlm_rx_data_snk_cur_lower_addr[3]) + ); + FDE com_tlm_u_tlm_rx_data_snk_cur_lower_addr_2_ ( + .CE(com_tlm_u_tlm_rx_data_snk_latch_3rd_dword_q1), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_N_21323_i), + .Q(com_tlm_u_tlm_rx_data_snk_cur_lower_addr[2]) + ); + FDE com_tlm_u_tlm_rx_data_snk_cur_fulltype_oh_7_ ( + .CE(com_tlm_u_tlm_rx_data_snk_latch_2nd_dword), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_N_9476_i), + .Q(com_tlm_u_tlm_rx_data_snk_cur_fulltype_oh_7__4090) + ); + FDE com_tlm_u_tlm_rx_data_snk_cur_fulltype_oh_5_ ( + .CE(com_tlm_u_tlm_rx_data_snk_latch_2nd_dword), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_cur_fulltype_oh35_i_a2_0_a2_4091), + .Q(com_tlm_u_tlm_rx_data_snk_cur_fulltype_oh_5__4092) + ); + FDE com_tlm_u_tlm_rx_data_snk_cur_fulltype_oh_3_ ( + .CE(com_tlm_u_tlm_rx_data_snk_latch_2nd_dword), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_cur_fulltype_oh37), + .Q(com_tlm_u_tlm_rx_data_snk_cur_fulltype_oh_3__4093) + ); + FDE com_tlm_u_tlm_rx_data_snk_cur_fulltype_oh_0_ ( + .CE(com_tlm_u_tlm_rx_data_snk_latch_2nd_dword), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_cur_fulltype_oh40), + .Q(com_tlm_u_tlm_rx_data_snk_cur_fulltype_oh_0__4094) + ); + SRL16 com_tlm_u_tlm_rx_data_snk_d_o_62_I_1 ( + .D(com_lnk_rd_5077[9]), + .Q(com_tlm_u_tlm_rx_data_snk_d_o_62_N_6), + .CLK(NlwRenamedSig_OI_trn_clk), + .A0(com_tlm_u_tlm_rx_data_snk_GND_4100), + .A1(com_tlm_u_tlm_rx_data_snk_GND_4100), + .A2(com_tlm_u_tlm_rx_data_snk_VCC_4101), + .A3(com_tlm_u_tlm_rx_data_snk_GND_4100) + ); + SRL16 com_tlm_u_tlm_rx_data_snk_d_o_61_I_1 ( + .D(com_lnk_rd_5077[8]), + .Q(com_tlm_u_tlm_rx_data_snk_d_o_61_N_6), + .CLK(NlwRenamedSig_OI_trn_clk), + .A0(com_tlm_u_tlm_rx_data_snk_GND_4100), + .A1(com_tlm_u_tlm_rx_data_snk_GND_4100), + .A2(com_tlm_u_tlm_rx_data_snk_VCC_4101), + .A3(com_tlm_u_tlm_rx_data_snk_GND_4100) + ); + SRL16 com_tlm_u_tlm_rx_data_snk_d_o_60_I_1 ( + .D(com_lnk_rd_5077[7]), + .Q(com_tlm_u_tlm_rx_data_snk_d_o_60_N_6), + .CLK(NlwRenamedSig_OI_trn_clk), + .A0(com_tlm_u_tlm_rx_data_snk_GND_4100), + .A1(com_tlm_u_tlm_rx_data_snk_GND_4100), + .A2(com_tlm_u_tlm_rx_data_snk_VCC_4101), + .A3(com_tlm_u_tlm_rx_data_snk_GND_4100) + ); + SRL16 com_tlm_u_tlm_rx_data_snk_d_o_59_I_1 ( + .D(com_tlm_u_tlm_rx_data_snk_lower_addr64_in_q[6]), + .Q(com_tlm_u_tlm_rx_data_snk_d_o_59_N_6), + .CLK(NlwRenamedSig_OI_trn_clk), + .A0(com_tlm_u_tlm_rx_data_snk_VCC_4101), + .A1(com_tlm_u_tlm_rx_data_snk_VCC_4101), + .A2(com_tlm_u_tlm_rx_data_snk_GND_4100), + .A3(com_tlm_u_tlm_rx_data_snk_GND_4100) + ); + SRL16 com_tlm_u_tlm_rx_data_snk_d_o_58_I_1 ( + .D(com_tlm_u_tlm_rx_data_snk_lower_addr64_in_q[5]), + .Q(com_tlm_u_tlm_rx_data_snk_d_o_58_N_6), + .CLK(NlwRenamedSig_OI_trn_clk), + .A0(com_tlm_u_tlm_rx_data_snk_VCC_4101), + .A1(com_tlm_u_tlm_rx_data_snk_VCC_4101), + .A2(com_tlm_u_tlm_rx_data_snk_GND_4100), + .A3(com_tlm_u_tlm_rx_data_snk_GND_4100) + ); + SRL16 com_tlm_u_tlm_rx_data_snk_d_o_57_I_1 ( + .D(com_tlm_u_tlm_rx_data_snk_lower_addr64_in_q[4]), + .Q(com_tlm_u_tlm_rx_data_snk_d_o_57_N_6), + .CLK(NlwRenamedSig_OI_trn_clk), + .A0(com_tlm_u_tlm_rx_data_snk_VCC_4101), + .A1(com_tlm_u_tlm_rx_data_snk_VCC_4101), + .A2(com_tlm_u_tlm_rx_data_snk_GND_4100), + .A3(com_tlm_u_tlm_rx_data_snk_GND_4100) + ); + SRL16 com_tlm_u_tlm_rx_data_snk_d_o_56_I_1 ( + .D(com_tlm_u_tlm_rx_data_snk_lower_addr64_in_q[3]), + .Q(com_tlm_u_tlm_rx_data_snk_d_o_56_N_6), + .CLK(NlwRenamedSig_OI_trn_clk), + .A0(com_tlm_u_tlm_rx_data_snk_VCC_4101), + .A1(com_tlm_u_tlm_rx_data_snk_VCC_4101), + .A2(com_tlm_u_tlm_rx_data_snk_GND_4100), + .A3(com_tlm_u_tlm_rx_data_snk_GND_4100) + ); + SRL16 com_tlm_u_tlm_rx_data_snk_d_o_55_I_1 ( + .D(com_tlm_u_tlm_rx_data_snk_lower_addr64_in_q[2]), + .Q(com_tlm_u_tlm_rx_data_snk_d_o_55_N_6), + .CLK(NlwRenamedSig_OI_trn_clk), + .A0(com_tlm_u_tlm_rx_data_snk_VCC_4101), + .A1(com_tlm_u_tlm_rx_data_snk_VCC_4101), + .A2(com_tlm_u_tlm_rx_data_snk_GND_4100), + .A3(com_tlm_u_tlm_rx_data_snk_GND_4100) + ); + SRL16 com_tlm_u_tlm_rx_data_snk_d_o_54_I_1 ( + .D(com_lnk_rd[1]), + .Q(com_tlm_u_tlm_rx_data_snk_d_o_54_N_6), + .CLK(NlwRenamedSig_OI_trn_clk), + .A0(com_tlm_u_tlm_rx_data_snk_GND_4100), + .A1(com_tlm_u_tlm_rx_data_snk_GND_4100), + .A2(com_tlm_u_tlm_rx_data_snk_VCC_4101), + .A3(com_tlm_u_tlm_rx_data_snk_GND_4100) + ); + SRL16 com_tlm_u_tlm_rx_data_snk_d_o_53_I_1 ( + .D(com_lnk_rd[0]), + .Q(com_tlm_u_tlm_rx_data_snk_d_o_53_N_6), + .CLK(NlwRenamedSig_OI_trn_clk), + .A0(com_tlm_u_tlm_rx_data_snk_GND_4100), + .A1(com_tlm_u_tlm_rx_data_snk_GND_4100), + .A2(com_tlm_u_tlm_rx_data_snk_VCC_4101), + .A3(com_tlm_u_tlm_rx_data_snk_GND_4100) + ); + SRL16 com_tlm_u_tlm_rx_data_snk_d_o_52_I_1 ( + .D(com_lnk_rd_5077[24]), + .Q(com_tlm_u_tlm_rx_data_snk_d_o_52_N_6), + .CLK(NlwRenamedSig_OI_trn_clk), + .A0(com_tlm_u_tlm_rx_data_snk_GND_4100), + .A1(com_tlm_u_tlm_rx_data_snk_GND_4100), + .A2(com_tlm_u_tlm_rx_data_snk_VCC_4101), + .A3(com_tlm_u_tlm_rx_data_snk_GND_4100) + ); + SRL16 com_tlm_u_tlm_rx_data_snk_d_o_51_I_1 ( + .D(com_lnk_rd_5077[23]), + .Q(com_tlm_u_tlm_rx_data_snk_d_o_51_N_6), + .CLK(NlwRenamedSig_OI_trn_clk), + .A0(com_tlm_u_tlm_rx_data_snk_GND_4100), + .A1(com_tlm_u_tlm_rx_data_snk_GND_4100), + .A2(com_tlm_u_tlm_rx_data_snk_VCC_4101), + .A3(com_tlm_u_tlm_rx_data_snk_GND_4100) + ); + SRL16 com_tlm_u_tlm_rx_data_snk_d_o_50_I_1 ( + .D(com_lnk_rd_5077[22]), + .Q(com_tlm_u_tlm_rx_data_snk_d_o_50_N_6), + .CLK(NlwRenamedSig_OI_trn_clk), + .A0(com_tlm_u_tlm_rx_data_snk_GND_4100), + .A1(com_tlm_u_tlm_rx_data_snk_GND_4100), + .A2(com_tlm_u_tlm_rx_data_snk_VCC_4101), + .A3(com_tlm_u_tlm_rx_data_snk_GND_4100) + ); + SRL16 com_tlm_u_tlm_rx_data_snk_d_o_49_I_1 ( + .D(com_lnk_rd_5077[21]), + .Q(com_tlm_u_tlm_rx_data_snk_d_o_49_N_6), + .CLK(NlwRenamedSig_OI_trn_clk), + .A0(com_tlm_u_tlm_rx_data_snk_GND_4100), + .A1(com_tlm_u_tlm_rx_data_snk_GND_4100), + .A2(com_tlm_u_tlm_rx_data_snk_VCC_4101), + .A3(com_tlm_u_tlm_rx_data_snk_GND_4100) + ); + SRL16 com_tlm_u_tlm_rx_data_snk_d_o_48_I_1 ( + .D(com_lnk_rd_5077[20]), + .Q(com_tlm_u_tlm_rx_data_snk_d_o_48_N_6), + .CLK(NlwRenamedSig_OI_trn_clk), + .A0(com_tlm_u_tlm_rx_data_snk_GND_4100), + .A1(com_tlm_u_tlm_rx_data_snk_GND_4100), + .A2(com_tlm_u_tlm_rx_data_snk_VCC_4101), + .A3(com_tlm_u_tlm_rx_data_snk_GND_4100) + ); + SRL16 com_tlm_u_tlm_rx_data_snk_d_o_47_I_1 ( + .D(com_lnk_rd_5077[19]), + .Q(com_tlm_u_tlm_rx_data_snk_d_o_47_N_6), + .CLK(NlwRenamedSig_OI_trn_clk), + .A0(com_tlm_u_tlm_rx_data_snk_GND_4100), + .A1(com_tlm_u_tlm_rx_data_snk_GND_4100), + .A2(com_tlm_u_tlm_rx_data_snk_VCC_4101), + .A3(com_tlm_u_tlm_rx_data_snk_GND_4100) + ); + SRL16 com_tlm_u_tlm_rx_data_snk_d_o_46_I_1 ( + .D(com_lnk_rd_5077[18]), + .Q(com_tlm_u_tlm_rx_data_snk_d_o_46_N_6), + .CLK(NlwRenamedSig_OI_trn_clk), + .A0(com_tlm_u_tlm_rx_data_snk_GND_4100), + .A1(com_tlm_u_tlm_rx_data_snk_GND_4100), + .A2(com_tlm_u_tlm_rx_data_snk_VCC_4101), + .A3(com_tlm_u_tlm_rx_data_snk_GND_4100) + ); + SRL16 com_tlm_u_tlm_rx_data_snk_d_o_45_I_1 ( + .D(com_lnk_rd_5077[17]), + .Q(com_tlm_u_tlm_rx_data_snk_d_o_45_N_6), + .CLK(NlwRenamedSig_OI_trn_clk), + .A0(com_tlm_u_tlm_rx_data_snk_GND_4100), + .A1(com_tlm_u_tlm_rx_data_snk_GND_4100), + .A2(com_tlm_u_tlm_rx_data_snk_VCC_4101), + .A3(com_tlm_u_tlm_rx_data_snk_GND_4100) + ); + SRL16 com_tlm_u_tlm_rx_data_snk_d_o_44_I_1 ( + .D(com_lnk_rd_5077[16]), + .Q(com_tlm_u_tlm_rx_data_snk_d_o_44_N_6), + .CLK(NlwRenamedSig_OI_trn_clk), + .A0(com_tlm_u_tlm_rx_data_snk_GND_4100), + .A1(com_tlm_u_tlm_rx_data_snk_GND_4100), + .A2(com_tlm_u_tlm_rx_data_snk_VCC_4101), + .A3(com_tlm_u_tlm_rx_data_snk_GND_4100) + ); + SRL16 com_tlm_u_tlm_rx_data_snk_d_o_43_I_1 ( + .D(com_lnk_rd_5077[15]), + .Q(com_tlm_u_tlm_rx_data_snk_d_o_43_N_6), + .CLK(NlwRenamedSig_OI_trn_clk), + .A0(com_tlm_u_tlm_rx_data_snk_GND_4100), + .A1(com_tlm_u_tlm_rx_data_snk_GND_4100), + .A2(com_tlm_u_tlm_rx_data_snk_VCC_4101), + .A3(com_tlm_u_tlm_rx_data_snk_GND_4100) + ); + SRL16 com_tlm_u_tlm_rx_data_snk_d_o_42_I_1 ( + .D(com_lnk_rd_5077[14]), + .Q(com_tlm_u_tlm_rx_data_snk_d_o_42_N_6), + .CLK(NlwRenamedSig_OI_trn_clk), + .A0(com_tlm_u_tlm_rx_data_snk_GND_4100), + .A1(com_tlm_u_tlm_rx_data_snk_GND_4100), + .A2(com_tlm_u_tlm_rx_data_snk_VCC_4101), + .A3(com_tlm_u_tlm_rx_data_snk_GND_4100) + ); + SRL16 com_tlm_u_tlm_rx_data_snk_d_o_41_I_1 ( + .D(com_lnk_rd_5077[13]), + .Q(com_tlm_u_tlm_rx_data_snk_d_o_41_N_6), + .CLK(NlwRenamedSig_OI_trn_clk), + .A0(com_tlm_u_tlm_rx_data_snk_GND_4100), + .A1(com_tlm_u_tlm_rx_data_snk_GND_4100), + .A2(com_tlm_u_tlm_rx_data_snk_VCC_4101), + .A3(com_tlm_u_tlm_rx_data_snk_GND_4100) + ); + SRL16 com_tlm_u_tlm_rx_data_snk_d_o_40_I_1 ( + .D(com_lnk_rd_5077[12]), + .Q(com_tlm_u_tlm_rx_data_snk_d_o_40_N_6), + .CLK(NlwRenamedSig_OI_trn_clk), + .A0(com_tlm_u_tlm_rx_data_snk_GND_4100), + .A1(com_tlm_u_tlm_rx_data_snk_GND_4100), + .A2(com_tlm_u_tlm_rx_data_snk_VCC_4101), + .A3(com_tlm_u_tlm_rx_data_snk_GND_4100) + ); + SRL16 com_tlm_u_tlm_rx_data_snk_d_o_39_I_1 ( + .D(com_lnk_rd_5077[11]), + .Q(com_tlm_u_tlm_rx_data_snk_d_o_39_N_6), + .CLK(NlwRenamedSig_OI_trn_clk), + .A0(com_tlm_u_tlm_rx_data_snk_GND_4100), + .A1(com_tlm_u_tlm_rx_data_snk_GND_4100), + .A2(com_tlm_u_tlm_rx_data_snk_VCC_4101), + .A3(com_tlm_u_tlm_rx_data_snk_GND_4100) + ); + SRL16 com_tlm_u_tlm_rx_data_snk_d_o_38_I_1 ( + .D(com_lnk_rd_5077[10]), + .Q(com_tlm_u_tlm_rx_data_snk_d_o_38_N_6), + .CLK(NlwRenamedSig_OI_trn_clk), + .A0(com_tlm_u_tlm_rx_data_snk_GND_4100), + .A1(com_tlm_u_tlm_rx_data_snk_GND_4100), + .A2(com_tlm_u_tlm_rx_data_snk_VCC_4101), + .A3(com_tlm_u_tlm_rx_data_snk_GND_4100) + ); + SRL16 com_tlm_u_tlm_rx_data_snk_d_o_37_I_1 ( + .D(com_lnk_rd_5077[39]), + .Q(com_tlm_u_tlm_rx_data_snk_d_o_37_N_6), + .CLK(NlwRenamedSig_OI_trn_clk), + .A0(com_tlm_u_tlm_rx_data_snk_GND_4100), + .A1(com_tlm_u_tlm_rx_data_snk_GND_4100), + .A2(com_tlm_u_tlm_rx_data_snk_VCC_4101), + .A3(com_tlm_u_tlm_rx_data_snk_GND_4100) + ); + SRL16 com_tlm_u_tlm_rx_data_snk_d_o_36_I_1 ( + .D(com_tlm_u_tlm_rx_data_snk_lower_addr32_in_q[6]), + .Q(com_tlm_u_tlm_rx_data_snk_d_o_36_N_6), + .CLK(NlwRenamedSig_OI_trn_clk), + .A0(com_tlm_u_tlm_rx_data_snk_VCC_4101), + .A1(com_tlm_u_tlm_rx_data_snk_VCC_4101), + .A2(com_tlm_u_tlm_rx_data_snk_GND_4100), + .A3(com_tlm_u_tlm_rx_data_snk_GND_4100) + ); + SRL16 com_tlm_u_tlm_rx_data_snk_d_o_35_I_1 ( + .D(com_tlm_u_tlm_rx_data_snk_lower_addr32_in_q[5]), + .Q(com_tlm_u_tlm_rx_data_snk_d_o_35_N_6), + .CLK(NlwRenamedSig_OI_trn_clk), + .A0(com_tlm_u_tlm_rx_data_snk_VCC_4101), + .A1(com_tlm_u_tlm_rx_data_snk_VCC_4101), + .A2(com_tlm_u_tlm_rx_data_snk_GND_4100), + .A3(com_tlm_u_tlm_rx_data_snk_GND_4100) + ); + SRL16 com_tlm_u_tlm_rx_data_snk_d_o_34_I_1 ( + .D(com_tlm_u_tlm_rx_data_snk_lower_addr32_in_q[4]), + .Q(com_tlm_u_tlm_rx_data_snk_d_o_34_N_6), + .CLK(NlwRenamedSig_OI_trn_clk), + .A0(com_tlm_u_tlm_rx_data_snk_VCC_4101), + .A1(com_tlm_u_tlm_rx_data_snk_VCC_4101), + .A2(com_tlm_u_tlm_rx_data_snk_GND_4100), + .A3(com_tlm_u_tlm_rx_data_snk_GND_4100) + ); + SRL16 com_tlm_u_tlm_rx_data_snk_d_o_33_I_1 ( + .D(com_tlm_u_tlm_rx_data_snk_lower_addr32_in_q[3]), + .Q(com_tlm_u_tlm_rx_data_snk_d_o_33_N_6), + .CLK(NlwRenamedSig_OI_trn_clk), + .A0(com_tlm_u_tlm_rx_data_snk_VCC_4101), + .A1(com_tlm_u_tlm_rx_data_snk_VCC_4101), + .A2(com_tlm_u_tlm_rx_data_snk_GND_4100), + .A3(com_tlm_u_tlm_rx_data_snk_GND_4100) + ); + SRL16 com_tlm_u_tlm_rx_data_snk_d_o_32_I_1 ( + .D(com_tlm_u_tlm_rx_data_snk_lower_addr32_in_q[2]), + .Q(com_tlm_u_tlm_rx_data_snk_d_o_32_N_6), + .CLK(NlwRenamedSig_OI_trn_clk), + .A0(com_tlm_u_tlm_rx_data_snk_VCC_4101), + .A1(com_tlm_u_tlm_rx_data_snk_VCC_4101), + .A2(com_tlm_u_tlm_rx_data_snk_GND_4100), + .A3(com_tlm_u_tlm_rx_data_snk_GND_4100) + ); + SRL16 com_tlm_u_tlm_rx_data_snk_d_o_31_I_1 ( + .D(com_lnk_rd_5077[33]), + .Q(com_tlm_u_tlm_rx_data_snk_d_o_31_N_6), + .CLK(NlwRenamedSig_OI_trn_clk), + .A0(com_tlm_u_tlm_rx_data_snk_GND_4100), + .A1(com_tlm_u_tlm_rx_data_snk_GND_4100), + .A2(com_tlm_u_tlm_rx_data_snk_VCC_4101), + .A3(com_tlm_u_tlm_rx_data_snk_GND_4100) + ); + SRL16 com_tlm_u_tlm_rx_data_snk_d_o_30_I_1 ( + .D(com_lnk_rd_5077[32]), + .Q(com_tlm_u_tlm_rx_data_snk_d_o_30_N_6), + .CLK(NlwRenamedSig_OI_trn_clk), + .A0(com_tlm_u_tlm_rx_data_snk_GND_4100), + .A1(com_tlm_u_tlm_rx_data_snk_GND_4100), + .A2(com_tlm_u_tlm_rx_data_snk_VCC_4101), + .A3(com_tlm_u_tlm_rx_data_snk_GND_4100) + ); + SRL16 com_tlm_u_tlm_rx_data_snk_d_o_29_I_1 ( + .D(com_lnk_rd_5077[31]), + .Q(com_tlm_u_tlm_rx_data_snk_d_o_29_N_6), + .CLK(NlwRenamedSig_OI_trn_clk), + .A0(com_tlm_u_tlm_rx_data_snk_GND_4100), + .A1(com_tlm_u_tlm_rx_data_snk_GND_4100), + .A2(com_tlm_u_tlm_rx_data_snk_VCC_4101), + .A3(com_tlm_u_tlm_rx_data_snk_GND_4100) + ); + SRL16 com_tlm_u_tlm_rx_data_snk_d_o_28_I_1 ( + .D(com_lnk_rd_5077[30]), + .Q(com_tlm_u_tlm_rx_data_snk_d_o_28_N_6), + .CLK(NlwRenamedSig_OI_trn_clk), + .A0(com_tlm_u_tlm_rx_data_snk_GND_4100), + .A1(com_tlm_u_tlm_rx_data_snk_GND_4100), + .A2(com_tlm_u_tlm_rx_data_snk_VCC_4101), + .A3(com_tlm_u_tlm_rx_data_snk_GND_4100) + ); + SRL16 com_tlm_u_tlm_rx_data_snk_d_o_27_I_1 ( + .D(com_lnk_rd_5077[29]), + .Q(com_tlm_u_tlm_rx_data_snk_d_o_27_N_6), + .CLK(NlwRenamedSig_OI_trn_clk), + .A0(com_tlm_u_tlm_rx_data_snk_GND_4100), + .A1(com_tlm_u_tlm_rx_data_snk_GND_4100), + .A2(com_tlm_u_tlm_rx_data_snk_VCC_4101), + .A3(com_tlm_u_tlm_rx_data_snk_GND_4100) + ); + SRL16 com_tlm_u_tlm_rx_data_snk_d_o_26_I_1 ( + .D(com_lnk_rd_5077[28]), + .Q(com_tlm_u_tlm_rx_data_snk_d_o_26_N_6), + .CLK(NlwRenamedSig_OI_trn_clk), + .A0(com_tlm_u_tlm_rx_data_snk_GND_4100), + .A1(com_tlm_u_tlm_rx_data_snk_GND_4100), + .A2(com_tlm_u_tlm_rx_data_snk_VCC_4101), + .A3(com_tlm_u_tlm_rx_data_snk_GND_4100) + ); + SRL16 com_tlm_u_tlm_rx_data_snk_d_o_25_I_1 ( + .D(com_lnk_rd_5077[27]), + .Q(com_tlm_u_tlm_rx_data_snk_d_o_25_N_6), + .CLK(NlwRenamedSig_OI_trn_clk), + .A0(com_tlm_u_tlm_rx_data_snk_GND_4100), + .A1(com_tlm_u_tlm_rx_data_snk_GND_4100), + .A2(com_tlm_u_tlm_rx_data_snk_VCC_4101), + .A3(com_tlm_u_tlm_rx_data_snk_GND_4100) + ); + SRL16 com_tlm_u_tlm_rx_data_snk_d_o_24_I_1 ( + .D(com_lnk_rd_5077[26]), + .Q(com_tlm_u_tlm_rx_data_snk_d_o_24_N_6), + .CLK(NlwRenamedSig_OI_trn_clk), + .A0(com_tlm_u_tlm_rx_data_snk_GND_4100), + .A1(com_tlm_u_tlm_rx_data_snk_GND_4100), + .A2(com_tlm_u_tlm_rx_data_snk_VCC_4101), + .A3(com_tlm_u_tlm_rx_data_snk_GND_4100) + ); + SRL16 com_tlm_u_tlm_rx_data_snk_d_o_23_I_1 ( + .D(com_lnk_rd_5077[25]), + .Q(com_tlm_u_tlm_rx_data_snk_d_o_23_N_6), + .CLK(NlwRenamedSig_OI_trn_clk), + .A0(com_tlm_u_tlm_rx_data_snk_GND_4100), + .A1(com_tlm_u_tlm_rx_data_snk_GND_4100), + .A2(com_tlm_u_tlm_rx_data_snk_VCC_4101), + .A3(com_tlm_u_tlm_rx_data_snk_GND_4100) + ); + SRL16 com_tlm_u_tlm_rx_data_snk_d_o_22_I_1 ( + .D(com_lnk_rd_5077[54]), + .Q(com_tlm_u_tlm_rx_data_snk_d_o_22_N_6), + .CLK(NlwRenamedSig_OI_trn_clk), + .A0(com_tlm_u_tlm_rx_data_snk_GND_4100), + .A1(com_tlm_u_tlm_rx_data_snk_GND_4100), + .A2(com_tlm_u_tlm_rx_data_snk_VCC_4101), + .A3(com_tlm_u_tlm_rx_data_snk_GND_4100) + ); + SRL16 com_tlm_u_tlm_rx_data_snk_d_o_21_I_1 ( + .D(com_lnk_rd_5077[53]), + .Q(com_tlm_u_tlm_rx_data_snk_d_o_21_N_6), + .CLK(NlwRenamedSig_OI_trn_clk), + .A0(com_tlm_u_tlm_rx_data_snk_GND_4100), + .A1(com_tlm_u_tlm_rx_data_snk_GND_4100), + .A2(com_tlm_u_tlm_rx_data_snk_VCC_4101), + .A3(com_tlm_u_tlm_rx_data_snk_GND_4100) + ); + SRL16 com_tlm_u_tlm_rx_data_snk_d_o_20_I_1 ( + .D(com_lnk_rd_5077[52]), + .Q(com_tlm_u_tlm_rx_data_snk_d_o_20_N_6), + .CLK(NlwRenamedSig_OI_trn_clk), + .A0(com_tlm_u_tlm_rx_data_snk_GND_4100), + .A1(com_tlm_u_tlm_rx_data_snk_GND_4100), + .A2(com_tlm_u_tlm_rx_data_snk_VCC_4101), + .A3(com_tlm_u_tlm_rx_data_snk_GND_4100) + ); + SRL16 com_tlm_u_tlm_rx_data_snk_d_o_19_I_1 ( + .D(com_lnk_rd_5077[51]), + .Q(com_tlm_u_tlm_rx_data_snk_d_o_19_N_6), + .CLK(NlwRenamedSig_OI_trn_clk), + .A0(com_tlm_u_tlm_rx_data_snk_GND_4100), + .A1(com_tlm_u_tlm_rx_data_snk_GND_4100), + .A2(com_tlm_u_tlm_rx_data_snk_VCC_4101), + .A3(com_tlm_u_tlm_rx_data_snk_GND_4100) + ); + SRL16 com_tlm_u_tlm_rx_data_snk_d_o_18_I_1 ( + .D(com_lnk_rd_5077[50]), + .Q(com_tlm_u_tlm_rx_data_snk_d_o_18_N_6), + .CLK(NlwRenamedSig_OI_trn_clk), + .A0(com_tlm_u_tlm_rx_data_snk_GND_4100), + .A1(com_tlm_u_tlm_rx_data_snk_GND_4100), + .A2(com_tlm_u_tlm_rx_data_snk_VCC_4101), + .A3(com_tlm_u_tlm_rx_data_snk_GND_4100) + ); + SRL16 com_tlm_u_tlm_rx_data_snk_d_o_17_I_1 ( + .D(com_lnk_rd_5077[49]), + .Q(com_tlm_u_tlm_rx_data_snk_d_o_17_N_6), + .CLK(NlwRenamedSig_OI_trn_clk), + .A0(com_tlm_u_tlm_rx_data_snk_GND_4100), + .A1(com_tlm_u_tlm_rx_data_snk_GND_4100), + .A2(com_tlm_u_tlm_rx_data_snk_VCC_4101), + .A3(com_tlm_u_tlm_rx_data_snk_GND_4100) + ); + SRL16 com_tlm_u_tlm_rx_data_snk_d_o_16_I_1 ( + .D(com_lnk_rd_5077[48]), + .Q(com_tlm_u_tlm_rx_data_snk_d_o_16_N_6), + .CLK(NlwRenamedSig_OI_trn_clk), + .A0(com_tlm_u_tlm_rx_data_snk_GND_4100), + .A1(com_tlm_u_tlm_rx_data_snk_GND_4100), + .A2(com_tlm_u_tlm_rx_data_snk_VCC_4101), + .A3(com_tlm_u_tlm_rx_data_snk_GND_4100) + ); + SRL16 com_tlm_u_tlm_rx_data_snk_d_o_15_I_1 ( + .D(com_tlm_u_tlm_rx_data_snk_N_13365_i), + .Q(com_tlm_u_tlm_rx_data_snk_d_o_15_N_6), + .CLK(NlwRenamedSig_OI_trn_clk), + .A0(com_tlm_u_tlm_rx_data_snk_GND_4100), + .A1(com_tlm_u_tlm_rx_data_snk_GND_4100), + .A2(com_tlm_u_tlm_rx_data_snk_VCC_4101), + .A3(com_tlm_u_tlm_rx_data_snk_GND_4100) + ); + SRL16 com_tlm_u_tlm_rx_data_snk_d_o_14_I_1 ( + .D(com_lnk_rd_5077[46]), + .Q(com_tlm_u_tlm_rx_data_snk_d_o_14_N_6), + .CLK(NlwRenamedSig_OI_trn_clk), + .A0(com_tlm_u_tlm_rx_data_snk_GND_4100), + .A1(com_tlm_u_tlm_rx_data_snk_GND_4100), + .A2(com_tlm_u_tlm_rx_data_snk_VCC_4101), + .A3(com_tlm_u_tlm_rx_data_snk_GND_4100) + ); + SRL16 com_tlm_u_tlm_rx_data_snk_d_o_13_I_1 ( + .D(com_lnk_rd_5077[45]), + .Q(com_tlm_u_tlm_rx_data_snk_d_o_13_N_6), + .CLK(NlwRenamedSig_OI_trn_clk), + .A0(com_tlm_u_tlm_rx_data_snk_GND_4100), + .A1(com_tlm_u_tlm_rx_data_snk_GND_4100), + .A2(com_tlm_u_tlm_rx_data_snk_VCC_4101), + .A3(com_tlm_u_tlm_rx_data_snk_GND_4100) + ); + SRL16 com_tlm_u_tlm_rx_data_snk_d_o_12_I_1 ( + .D(com_lnk_rd_5077[44]), + .Q(com_tlm_u_tlm_rx_data_snk_d_o_12_N_6), + .CLK(NlwRenamedSig_OI_trn_clk), + .A0(com_tlm_u_tlm_rx_data_snk_GND_4100), + .A1(com_tlm_u_tlm_rx_data_snk_GND_4100), + .A2(com_tlm_u_tlm_rx_data_snk_VCC_4101), + .A3(com_tlm_u_tlm_rx_data_snk_GND_4100) + ); + SRL16 com_tlm_u_tlm_rx_data_snk_d_o_11_I_1 ( + .D(com_lnk_rd_5077[43]), + .Q(com_tlm_u_tlm_rx_data_snk_d_o_11_N_6), + .CLK(NlwRenamedSig_OI_trn_clk), + .A0(com_tlm_u_tlm_rx_data_snk_GND_4100), + .A1(com_tlm_u_tlm_rx_data_snk_GND_4100), + .A2(com_tlm_u_tlm_rx_data_snk_VCC_4101), + .A3(com_tlm_u_tlm_rx_data_snk_GND_4100) + ); + SRL16 com_tlm_u_tlm_rx_data_snk_d_o_10_I_1 ( + .D(com_lnk_rd_5077[42]), + .Q(com_tlm_u_tlm_rx_data_snk_d_o_10_N_6), + .CLK(NlwRenamedSig_OI_trn_clk), + .A0(com_tlm_u_tlm_rx_data_snk_GND_4100), + .A1(com_tlm_u_tlm_rx_data_snk_GND_4100), + .A2(com_tlm_u_tlm_rx_data_snk_VCC_4101), + .A3(com_tlm_u_tlm_rx_data_snk_GND_4100) + ); + SRL16 com_tlm_u_tlm_rx_data_snk_d_o_9_I_1 ( + .D(com_lnk_rd_5077[41]), + .Q(com_tlm_u_tlm_rx_data_snk_d_o_9_N_6), + .CLK(NlwRenamedSig_OI_trn_clk), + .A0(com_tlm_u_tlm_rx_data_snk_GND_4100), + .A1(com_tlm_u_tlm_rx_data_snk_GND_4100), + .A2(com_tlm_u_tlm_rx_data_snk_VCC_4101), + .A3(com_tlm_u_tlm_rx_data_snk_GND_4100) + ); + SRL16 com_tlm_u_tlm_rx_data_snk_d_o_8_I_1 ( + .D(com_lnk_rd_5077[40]), + .Q(com_tlm_u_tlm_rx_data_snk_d_o_8_N_6), + .CLK(NlwRenamedSig_OI_trn_clk), + .A0(com_tlm_u_tlm_rx_data_snk_GND_4100), + .A1(com_tlm_u_tlm_rx_data_snk_GND_4100), + .A2(com_tlm_u_tlm_rx_data_snk_VCC_4101), + .A3(com_tlm_u_tlm_rx_data_snk_GND_4100) + ); + SRL16 com_tlm_u_tlm_rx_data_snk_dsc_q_I_1 ( + .D(com_tlm_u_tlm_rx_data_snk_dsc_q_1__4095), + .Q(com_tlm_u_tlm_rx_data_snk_dsc_q_N_6), + .CLK(NlwRenamedSig_OI_trn_clk), + .A0(com_tlm_u_tlm_rx_data_snk_VCC_4101), + .A1(com_tlm_u_tlm_rx_data_snk_GND_4100), + .A2(com_tlm_u_tlm_rx_data_snk_GND_4100), + .A3(com_tlm_u_tlm_rx_data_snk_GND_4100) + ); + SRL16 com_tlm_u_tlm_rx_data_snk_eof_nd_q_I_1 ( + .D(com_tlm_u_tlm_rx_data_snk_eof_nd_q_1__4096), + .Q(com_tlm_u_tlm_rx_data_snk_eof_nd_q_N_6), + .CLK(NlwRenamedSig_OI_trn_clk), + .A0(com_tlm_u_tlm_rx_data_snk_VCC_4101), + .A1(com_tlm_u_tlm_rx_data_snk_GND_4100), + .A2(com_tlm_u_tlm_rx_data_snk_GND_4100), + .A3(com_tlm_u_tlm_rx_data_snk_GND_4100) + ); + SRL16 com_tlm_u_tlm_rx_data_snk_d_o_7_I_1 ( + .D(com_lnk_rd_5077[63]), + .Q(com_tlm_u_tlm_rx_data_snk_d_o_7_N_6), + .CLK(NlwRenamedSig_OI_trn_clk), + .A0(com_tlm_u_tlm_rx_data_snk_GND_4100), + .A1(com_tlm_u_tlm_rx_data_snk_GND_4100), + .A2(com_tlm_u_tlm_rx_data_snk_VCC_4101), + .A3(com_tlm_u_tlm_rx_data_snk_GND_4100) + ); + SRL16 com_tlm_u_tlm_rx_data_snk_d_o_6_I_1 ( + .D(com_lnk_rd_5077[62]), + .Q(com_tlm_u_tlm_rx_data_snk_d_o_6_N_6), + .CLK(NlwRenamedSig_OI_trn_clk), + .A0(com_tlm_u_tlm_rx_data_snk_GND_4100), + .A1(com_tlm_u_tlm_rx_data_snk_GND_4100), + .A2(com_tlm_u_tlm_rx_data_snk_VCC_4101), + .A3(com_tlm_u_tlm_rx_data_snk_GND_4100) + ); + SRL16 com_tlm_u_tlm_rx_data_snk_d_o_5_I_1 ( + .D(com_lnk_rd_5077[61]), + .Q(com_tlm_u_tlm_rx_data_snk_d_o_5_N_6), + .CLK(NlwRenamedSig_OI_trn_clk), + .A0(com_tlm_u_tlm_rx_data_snk_GND_4100), + .A1(com_tlm_u_tlm_rx_data_snk_GND_4100), + .A2(com_tlm_u_tlm_rx_data_snk_VCC_4101), + .A3(com_tlm_u_tlm_rx_data_snk_GND_4100) + ); + SRL16 com_tlm_u_tlm_rx_data_snk_d_o_4_I_1 ( + .D(com_lnk_rd_5077[60]), + .Q(com_tlm_u_tlm_rx_data_snk_d_o_4_N_6), + .CLK(NlwRenamedSig_OI_trn_clk), + .A0(com_tlm_u_tlm_rx_data_snk_GND_4100), + .A1(com_tlm_u_tlm_rx_data_snk_GND_4100), + .A2(com_tlm_u_tlm_rx_data_snk_VCC_4101), + .A3(com_tlm_u_tlm_rx_data_snk_GND_4100) + ); + SRL16 com_tlm_u_tlm_rx_data_snk_d_o_3_I_1 ( + .D(com_lnk_rd_5077[59]), + .Q(com_tlm_u_tlm_rx_data_snk_d_o_3_N_6), + .CLK(NlwRenamedSig_OI_trn_clk), + .A0(com_tlm_u_tlm_rx_data_snk_GND_4100), + .A1(com_tlm_u_tlm_rx_data_snk_GND_4100), + .A2(com_tlm_u_tlm_rx_data_snk_VCC_4101), + .A3(com_tlm_u_tlm_rx_data_snk_GND_4100) + ); + SRL16 com_tlm_u_tlm_rx_data_snk_d_o_2_I_1 ( + .D(com_lnk_rd_5077[58]), + .Q(com_tlm_u_tlm_rx_data_snk_d_o_2_N_6), + .CLK(NlwRenamedSig_OI_trn_clk), + .A0(com_tlm_u_tlm_rx_data_snk_GND_4100), + .A1(com_tlm_u_tlm_rx_data_snk_GND_4100), + .A2(com_tlm_u_tlm_rx_data_snk_VCC_4101), + .A3(com_tlm_u_tlm_rx_data_snk_GND_4100) + ); + SRL16 com_tlm_u_tlm_rx_data_snk_d_o_1_I_1 ( + .D(com_lnk_rd_5077[57]), + .Q(com_tlm_u_tlm_rx_data_snk_d_o_1_N_6), + .CLK(NlwRenamedSig_OI_trn_clk), + .A0(com_tlm_u_tlm_rx_data_snk_GND_4100), + .A1(com_tlm_u_tlm_rx_data_snk_GND_4100), + .A2(com_tlm_u_tlm_rx_data_snk_VCC_4101), + .A3(com_tlm_u_tlm_rx_data_snk_GND_4100) + ); + SRL16 com_tlm_u_tlm_rx_data_snk_d_o_0_I_1 ( + .D(com_lnk_rd_5077[56]), + .Q(com_tlm_u_tlm_rx_data_snk_d_o_0_N_6), + .CLK(NlwRenamedSig_OI_trn_clk), + .A0(com_tlm_u_tlm_rx_data_snk_GND_4100), + .A1(com_tlm_u_tlm_rx_data_snk_GND_4100), + .A2(com_tlm_u_tlm_rx_data_snk_VCC_4101), + .A3(com_tlm_u_tlm_rx_data_snk_GND_4100) + ); + SRL16 com_tlm_u_tlm_rx_data_snk_d_o_I_1 ( + .D(com_lnk_rd_5077[55]), + .Q(com_tlm_u_tlm_rx_data_snk_d_o_N_6), + .CLK(NlwRenamedSig_OI_trn_clk), + .A0(com_tlm_u_tlm_rx_data_snk_GND_4100), + .A1(com_tlm_u_tlm_rx_data_snk_GND_4100), + .A2(com_tlm_u_tlm_rx_data_snk_VCC_4101), + .A3(com_tlm_u_tlm_rx_data_snk_GND_4100) + ); + SRL16 com_tlm_u_tlm_rx_data_snk_sof_q_I_1 ( + .D(com_tlm_u_tlm_rx_data_snk_sof_q_1__4097), + .Q(com_tlm_u_tlm_rx_data_snk_sof_q_N_6), + .CLK(NlwRenamedSig_OI_trn_clk), + .A0(com_tlm_u_tlm_rx_data_snk_VCC_4101), + .A1(com_tlm_u_tlm_rx_data_snk_GND_4100), + .A2(com_tlm_u_tlm_rx_data_snk_GND_4100), + .A3(com_tlm_u_tlm_rx_data_snk_GND_4100) + ); + SRL16 com_tlm_u_tlm_rx_data_snk_rem_q_I_1 ( + .D(com_tlm_u_tlm_rx_data_snk_rem_q_1__4098), + .Q(com_tlm_u_tlm_rx_data_snk_rem_q_N_6), + .CLK(NlwRenamedSig_OI_trn_clk), + .A0(com_tlm_u_tlm_rx_data_snk_VCC_4101), + .A1(com_tlm_u_tlm_rx_data_snk_GND_4100), + .A2(com_tlm_u_tlm_rx_data_snk_GND_4100), + .A3(com_tlm_u_tlm_rx_data_snk_GND_4100) + ); + SRL16 com_tlm_u_tlm_rx_data_snk_src_rdy_q_I_1 ( + .D(com_tlm_u_tlm_rx_data_snk_src_rdy_q_1__4099), + .Q(com_tlm_u_tlm_rx_data_snk_src_rdy_q_N_6), + .CLK(NlwRenamedSig_OI_trn_clk), + .A0(com_tlm_u_tlm_rx_data_snk_VCC_4101), + .A1(com_tlm_u_tlm_rx_data_snk_GND_4100), + .A2(com_tlm_u_tlm_rx_data_snk_GND_4100), + .A3(com_tlm_u_tlm_rx_data_snk_GND_4100) + ); + defparam com_tlm_u_tlm_rx_data_snk_next_cur_drop.INIT = 4'h4; + LUT2_L com_tlm_u_tlm_rx_data_snk_next_cur_drop ( + .I0(com_tlm_u_tlm_rx_data_snk_N_9481), + .I1(com_tlm_u_tlm_rx_data_snk_eof_o_3), + .LO(com_tlm_u_tlm_rx_data_snk_next_cur_drop_4102) + ); + defparam com_tlm_u_tlm_rx_data_snk_un4_cur_byte_ct_s_10_sf.INIT = 4'h1; + LUT1 com_tlm_u_tlm_rx_data_snk_un4_cur_byte_ct_s_10_sf ( + .I0(com_tlm_u_tlm_rx_data_snk_cur_length_8__12), + .O(com_tlm_u_tlm_rx_data_snk_un4_cur_byte_ct_s_10_sf_4103) + ); + defparam com_tlm_u_tlm_rx_data_snk_un4_cur_byte_ct_s_9_sf.INIT = 4'h1; + LUT1 com_tlm_u_tlm_rx_data_snk_un4_cur_byte_ct_s_9_sf ( + .I0(com_tlm_u_tlm_rx_data_snk_cur_length[7]), + .O(com_tlm_u_tlm_rx_data_snk_un4_cur_byte_ct_s_9_sf_4104) + ); + defparam com_tlm_u_tlm_rx_data_snk_un4_cur_byte_ct_s_8_sf.INIT = 4'h1; + LUT1 com_tlm_u_tlm_rx_data_snk_un4_cur_byte_ct_s_8_sf ( + .I0(com_tlm_u_tlm_rx_data_snk_cur_length[6]), + .O(com_tlm_u_tlm_rx_data_snk_un4_cur_byte_ct_s_8_sf_4105) + ); + defparam com_tlm_u_tlm_rx_data_snk_un4_cur_byte_ct_s_7_sf.INIT = 4'h1; + LUT1 com_tlm_u_tlm_rx_data_snk_un4_cur_byte_ct_s_7_sf ( + .I0(com_tlm_u_tlm_rx_data_snk_cur_length[5]), + .O(com_tlm_u_tlm_rx_data_snk_un4_cur_byte_ct_s_7_sf_4106) + ); + defparam com_tlm_u_tlm_rx_data_snk_un4_cur_byte_ct_s_6_sf.INIT = 4'h1; + LUT1 com_tlm_u_tlm_rx_data_snk_un4_cur_byte_ct_s_6_sf ( + .I0(com_tlm_u_tlm_rx_data_snk_cur_length_4__10), + .O(com_tlm_u_tlm_rx_data_snk_un4_cur_byte_ct_s_6_sf_4107) + ); + defparam com_tlm_u_tlm_rx_data_snk_un4_cur_byte_ct_s_5_sf.INIT = 4'h1; + LUT1 com_tlm_u_tlm_rx_data_snk_un4_cur_byte_ct_s_5_sf ( + .I0(com_tlm_u_tlm_rx_data_snk_cur_length_3__8), + .O(com_tlm_u_tlm_rx_data_snk_un4_cur_byte_ct_s_5_sf_4108) + ); + defparam com_tlm_u_tlm_rx_data_snk_un4_cur_byte_ct_s_4_sf.INIT = 4'h1; + LUT1 com_tlm_u_tlm_rx_data_snk_un4_cur_byte_ct_s_4_sf ( + .I0(com_tlm_u_tlm_rx_data_snk_cur_length_2__6), + .O(com_tlm_u_tlm_rx_data_snk_un4_cur_byte_ct_s_4_sf_4109) + ); + defparam com_tlm_u_tlm_rx_data_snk_un4_cur_byte_ct_s_3_sf.INIT = 4'h1; + LUT1 com_tlm_u_tlm_rx_data_snk_un4_cur_byte_ct_s_3_sf ( + .I0(com_tlm_u_tlm_rx_data_snk_cur_length_1__4), + .O(com_tlm_u_tlm_rx_data_snk_un4_cur_byte_ct_s_3_sf_4110) + ); + defparam com_tlm_u_tlm_rx_data_snk_un4_cur_byte_ct_axb_2.INIT = 4'h9; + LUT2 com_tlm_u_tlm_rx_data_snk_un4_cur_byte_ct_axb_2 ( + .I0(com_tlm_u_tlm_rx_data_snk_cur_bytes_missing[2]), + .I1(com_tlm_u_tlm_rx_data_snk_cur_length_0__2), + .O(com_tlm_u_tlm_rx_data_snk_un4_cur_byte_ct_axb_2_4111) + ); + defparam com_tlm_u_tlm_rx_data_snk_un4_cur_byte_ct_axb_1.INIT = 4'h1; + LUT1 com_tlm_u_tlm_rx_data_snk_un4_cur_byte_ct_axb_1 ( + .I0(com_tlm_u_tlm_rx_data_snk_cur_bytes_missing[1]), + .O(com_tlm_u_tlm_rx_data_snk_un4_cur_byte_ct_axb_1_4112) + ); + defparam com_tlm_u_tlm_rx_data_snk_un4_cur_byte_ct_cry_0_sf.INIT = 4'h2; + LUT1 com_tlm_u_tlm_rx_data_snk_un4_cur_byte_ct_cry_0_sf ( + .I0(com_tlm_u_tlm_rx_data_snk_cur_bytes_missing[0]), + .O(com_tlm_u_tlm_rx_data_snk_un4_cur_byte_ct_cry_0_sf_4113) + ); + VCC com_tlm_u_tlm_rx_data_snk_malformed_checks_VCC ( + .P(com_tlm_u_tlm_rx_data_snk_malformed_checks_VCC_4140) + ); + GND com_tlm_u_tlm_rx_data_snk_malformed_checks_GND ( + .G(com_tlm_u_tlm_rx_data_snk_malformed_checks_GND_4131) + ); + FDRE com_tlm_u_tlm_rx_data_snk_malformed_checks_word_ct_0_ ( + .CE(com_tlm_u_tlm_rx_data_snk_malformed_checks_delay_ct_i_4205), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_malformed_checks_word_ct_d_i[0]), + .Q(com_tlm_u_tlm_rx_data_snk_malformed_checks_word_ct[0]), + .R(plm_link_up_i) + ); + FDRE com_tlm_u_tlm_rx_data_snk_malformed_checks_word_ct_1_ ( + .CE(com_tlm_u_tlm_rx_data_snk_malformed_checks_delay_ct_i_4205), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_malformed_checks_un4_word_ct_s_1_4132), + .Q(com_tlm_u_tlm_rx_data_snk_malformed_checks_word_ct[1]), + .R(plm_link_up_i) + ); + FDRE com_tlm_u_tlm_rx_data_snk_malformed_checks_word_ct_2_ ( + .CE(com_tlm_u_tlm_rx_data_snk_malformed_checks_delay_ct_i_4205), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_malformed_checks_un4_word_ct_s_2_4134), + .Q(com_tlm_u_tlm_rx_data_snk_malformed_checks_word_ct[2]), + .R(plm_link_up_i) + ); + FDRE com_tlm_u_tlm_rx_data_snk_malformed_checks_word_ct_3_ ( + .CE(com_tlm_u_tlm_rx_data_snk_malformed_checks_delay_ct_i_4205), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_malformed_checks_un4_word_ct_s_3_4136), + .Q(com_tlm_u_tlm_rx_data_snk_malformed_checks_word_ct[3]), + .R(plm_link_up_i) + ); + FDRE com_tlm_u_tlm_rx_data_snk_malformed_checks_word_ct_4_ ( + .CE(com_tlm_u_tlm_rx_data_snk_malformed_checks_delay_ct_i_4205), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_malformed_checks_un4_word_ct_s_4_4138), + .Q(com_tlm_u_tlm_rx_data_snk_malformed_checks_word_ct[4]), + .R(plm_link_up_i) + ); + FDRE com_tlm_u_tlm_rx_data_snk_malformed_checks_word_ct_5_ ( + .CE(com_tlm_u_tlm_rx_data_snk_malformed_checks_delay_ct_i_4205), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_malformed_checks_un4_word_ct_s_5_4141), + .Q(com_tlm_u_tlm_rx_data_snk_malformed_checks_word_ct[5]), + .R(plm_link_up_i) + ); + FDRE com_tlm_u_tlm_rx_data_snk_malformed_checks_word_ct_6_ ( + .CE(com_tlm_u_tlm_rx_data_snk_malformed_checks_delay_ct_i_4205), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_malformed_checks_un4_word_ct_s_6_4143), + .Q(com_tlm_u_tlm_rx_data_snk_malformed_checks_word_ct[6]), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_rx_data_snk_malformed_checks_malformed_min ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_malformed_checks_N_9208_i_i), + .Q(com_tlm_u_tlm_rx_data_snk_malformed_checks_malformed_min_4167), + .R(plm_link_up_i) + ); + FDRE com_tlm_u_tlm_rx_data_snk_malformed_checks_malformed_maxsize ( + .CE(com_tlm_u_tlm_rx_data_snk_latch_1st_dword_q1_4028), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_malformed_checks_N_69316_i_4191), + .Q(com_tlm_u_tlm_rx_data_snk_malformed_checks_malformed_maxsize_4177), + .R(plm_link_up_i) + ); + FDS com_tlm_u_tlm_rx_data_snk_malformed_checks_max_length_5_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_N_3355_i), + .Q(com_tlm_u_tlm_rx_data_snk_malformed_checks_max_length[5]), + .S(plm_link_up_i) + ); + FDR com_tlm_u_tlm_rx_data_snk_malformed_checks_max_length_6_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_lat_d[2]), + .Q(com_tlm_u_tlm_rx_data_snk_malformed_checks_max_length[6]), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_rx_data_snk_malformed_checks_max_length_7_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_N_3419_i_i), + .Q(com_tlm_u_tlm_rx_data_snk_malformed_checks_max_length[7]), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_rx_data_snk_malformed_checks_malformed_over ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_malformed_checks_N_24200_i), + .Q(com_tlm_u_tlm_rx_data_snk_malformed_checks_malformed_over_4190), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_rx_data_snk_malformed_checks_malformed_eof ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_malformed_checks_N_24198_i), + .Q(com_tlm_u_tlm_rx_data_snk_malformed_checks_malformed_eof_4168), + .R(plm_link_up_i) + ); + FDRE com_tlm_u_tlm_rx_data_snk_malformed_checks_ur_pwr_mgmt ( + .CE(com_tlm_u_tlm_rx_data_snk_latch_1st_dword_q1_4028), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_malformed_checks_N_11860_i), + .Q(com_tlm_u_tlm_rx_data_snk_malformed_checks_ur_pwr_mgmt_4115), + .R(plm_link_up_i) + ); + FDRSE com_tlm_u_tlm_rx_data_snk_malformed_checks_type_1dw ( + .CE(com_tlm_u_tlm_rx_data_snk_latch_1st_dword_q1_4028), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_malformed_checks_GND_4131), + .Q(com_tlm_u_tlm_rx_data_snk_malformed_checks_type_1dw_4150), + .R(plm_link_up_i), + .S(com_tlm_u_tlm_rx_data_snk_malformed_checks_N_11858_i) + ); + FDRE com_tlm_u_tlm_rx_data_snk_malformed_checks_malformed_message ( + .CE(com_tlm_u_tlm_rx_data_snk_latch_1st_dword_q1_4028), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_malformed_checks_N_67910_i_4206), + .Q(com_tlm_u_tlm_rx_data_snk_malformed_checks_malformed_message_4151), + .R(plm_link_up_i) + ); + FDRE com_tlm_u_tlm_rx_data_snk_malformed_checks_malformed_fulltype ( + .CE(com_tlm_u_tlm_rx_data_snk_latch_1st_dword_q1_4028), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_malformed_checks_N_67836_i_4184), + .Q(com_tlm_u_tlm_rx_data_snk_malformed_checks_malformed_fulltype_4178), + .R(plm_link_up_i) + ); + FDRE com_tlm_u_tlm_rx_data_snk_malformed_checks_malformed_tc ( + .CE(com_tlm_u_tlm_rx_data_snk_latch_1st_dword_q1_4028), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_malformed_checks_N_68324_i_4182), + .Q(com_tlm_u_tlm_rx_data_snk_malformed_checks_malformed_tc_4176), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_rx_data_snk_malformed_checks_malformed_rem ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_malformed_checks_malformed_rem_3_4181), + .Q(com_tlm_u_tlm_rx_data_snk_malformed_checks_malformed_rem_4166), + .R(plm_link_up_i) + ); + FDRSE com_tlm_u_tlm_rx_data_snk_malformed_checks_cfg1_ip ( + .CE(com_tlm_u_tlm_rx_data_snk_latch_1st_dword_q1_4028), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_malformed_checks_GND_4131), + .Q(com_tlm_u_tlm_rx_data_snk_malformed_checks_cfg1_ip_4173), + .R(plm_link_up_i), + .S(com_tlm_u_tlm_rx_data_snk_malformed_checks_cfg1_ip_0_sqmuxa) + ); + FDRSE com_tlm_u_tlm_rx_data_snk_malformed_checks_cfg0_ip ( + .CE(com_tlm_u_tlm_rx_data_snk_latch_1st_dword_q1_4028), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_malformed_checks_GND_4131), + .Q(com_tlm_u_tlm_rx_data_snk_malformed_checks_cfg0_ip_4174), + .R(plm_link_up_i), + .S(com_tlm_u_tlm_rx_data_snk_malformed_checks_cfg0_ip_0_sqmuxa) + ); + FDRE com_tlm_u_tlm_rx_data_snk_malformed_checks_uc_pwr_mgmt ( + .CE(com_tlm_u_tlm_rx_data_snk_latch_1st_dword_q1_4028), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_malformed_checks_uc_pwr_mgmt_7), + .Q(com_tlm_u_tlm_rx_data_snk_malformed_checks_uc_pwr_mgmt_4116), + .R(plm_link_up_i) + ); + FDRE com_tlm_u_tlm_rx_data_snk_malformed_checks_malformed_fmt ( + .CE(com_tlm_u_tlm_rx_data_snk_latch_1st_dword_q2), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_malformed_checks_N_68230_i_4175), + .Q(com_tlm_u_tlm_rx_data_snk_malformed_checks_malformed_fmt_4164), + .R(plm_link_up_i) + ); + FDRE com_tlm_u_tlm_rx_data_snk_malformed_checks_cfg_o ( + .CE(com_tlm_u_tlm_rx_data_snk_latch_3rd_dword_q1), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_malformed_checks_N_50796_i_4170), + .Q(com_tlm_u_tlm_rx_data_snk_cur_cfg), + .R(plm_link_up_i) + ); + FDRE com_tlm_u_tlm_rx_data_snk_malformed_checks_is_usr_ext_ap ( + .CE(com_tlm_u_tlm_rx_data_snk_sof_q_1__4097), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_malformed_checks_N_21383_i), + .Q(com_tlm_u_tlm_rx_data_snk_malformed_checks_is_usr_ext_ap_4172), + .R(plm_link_up_i) + ); + FDRE com_tlm_u_tlm_rx_data_snk_malformed_checks_length_1dw ( + .CE(com_tlm_u_tlm_rx_data_snk_latch_1st_dword_q1_4028), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_malformed_checks_length_1dw_3), + .Q(com_tlm_u_tlm_rx_data_snk_malformed_checks_length_1dw_4152), + .R(plm_link_up_i) + ); + FDRE com_tlm_u_tlm_rx_data_snk_malformed_checks_is_usr_leg_ap ( + .CE(com_tlm_u_tlm_rx_data_snk_sof_q_1__4097), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_malformed_checks_is_usr_leg_ap_3), + .Q(com_tlm_u_tlm_rx_data_snk_malformed_checks_is_usr_leg_ap_4171), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_rx_data_snk_malformed_checks_sof_q4 ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_malformed_checks_sof_q3_4114), + .Q(com_tlm_u_tlm_rx_data_snk_cur_data_credits_vld), + .R(plm_link_up_i) + ); + FDRE com_tlm_u_tlm_rx_data_snk_malformed_checks_malformed_len ( + .CE(com_tlm_u_tlm_rx_data_snk_eof_q_1__4073), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_malformed_checks_N_36604_i_4165), + .Q(com_tlm_u_tlm_rx_data_snk_malformed_checks_malformed_len_4163), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_rx_data_snk_malformed_checks_sof_q3 ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_latch_3rd_dword_q1), + .Q(com_tlm_u_tlm_rx_data_snk_malformed_checks_sof_q3_4114), + .R(plm_link_up_i) + ); + FDRSE com_tlm_u_tlm_rx_data_snk_malformed_checks_tlp_ur_o ( + .CE(com_tlm_u_tlm_rx_data_snk_sof_q_4_), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_malformed_checks_GND_4131), + .Q(com_tlm_u_tlm_rx_data_snk_tlp_ur), + .R(plm_link_up_i), + .S(com_tlm_u_tlm_rx_data_snk_malformed_checks_tlp_ur_o_0_sqmuxa) + ); + FDRSE com_tlm_u_tlm_rx_data_snk_malformed_checks_tlp_uc_o ( + .CE(com_tlm_u_tlm_rx_data_snk_sof_q_4_), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_malformed_checks_GND_4131), + .Q(com_tlm_u_tlm_rx_data_snk_tlp_uc), + .R(plm_link_up_i), + .S(com_tlm_u_tlm_rx_data_snk_malformed_checks_tlp_uc_o_0_sqmuxa) + ); + FDRE com_tlm_u_tlm_rx_data_snk_malformed_checks_ur_format ( + .CE(com_tlm_u_tlm_rx_data_snk_latch_1st_dword_q2), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_malformed_checks_ur_pwr_mgmt_4115), + .Q(com_tlm_u_tlm_rx_data_snk_malformed_checks_ur_format_4147), + .R(plm_link_up_i) + ); + FDRE com_tlm_u_tlm_rx_data_snk_malformed_checks_uc_format ( + .CE(com_tlm_u_tlm_rx_data_snk_latch_1st_dword_q2), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_malformed_checks_uc_pwr_mgmt_4116), + .Q(com_tlm_u_tlm_rx_data_snk_malformed_checks_uc_format_4146), + .R(plm_link_up_i) + ); + FDRE com_tlm_u_tlm_rx_data_snk_malformed_checks_malformed_o ( + .CE(com_tlm_u_tlm_rx_data_snk_malformed_checks_eof_q2_4145), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_malformed_checks_N_50795_i_4162), + .Q(com_tlm_u_tlm_rx_data_snk_malformed), + .R(plm_link_up_i) + ); + FDRE com_tlm_u_tlm_rx_data_snk_malformed_checks_hp_msg_detect_o ( + .CE(com_tlm_u_tlm_rx_data_snk_latch_1st_dword_q2), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_malformed_checks_msgcode_hotplug_4202), + .Q(com_tlm_u_tlm_rx_data_snk_cur_hp_msg_detect), + .R(plm_link_up_i) + ); + MUXCY_L com_tlm_u_tlm_rx_data_snk_malformed_checks_un6_malformed_maxsize_cry_0 ( + .CI(com_tlm_u_tlm_rx_data_snk_malformed_checks_GND_4131), + .DI(com_tlm_u_tlm_rx_data_snk_malformed_checks_VCC_4140), + .LO(com_tlm_u_tlm_rx_data_snk_malformed_checks_un6_malformed_maxsize_cry_0_4117), + .S(N_6356_i_3) + ); + MUXCY_L com_tlm_u_tlm_rx_data_snk_malformed_checks_un6_malformed_maxsize_cry_1 ( + .CI(com_tlm_u_tlm_rx_data_snk_malformed_checks_un6_malformed_maxsize_cry_0_4117), + .DI(com_tlm_u_tlm_rx_data_snk_malformed_checks_VCC_4140), + .LO(com_tlm_u_tlm_rx_data_snk_malformed_checks_un6_malformed_maxsize_cry_1_4118), + .S(N_6357_i_5) + ); + MUXCY_L com_tlm_u_tlm_rx_data_snk_malformed_checks_un6_malformed_maxsize_cry_2 ( + .CI(com_tlm_u_tlm_rx_data_snk_malformed_checks_un6_malformed_maxsize_cry_1_4118), + .DI(com_tlm_u_tlm_rx_data_snk_malformed_checks_VCC_4140), + .LO(com_tlm_u_tlm_rx_data_snk_malformed_checks_un6_malformed_maxsize_cry_2_4119), + .S(N_6358_i_7) + ); + MUXCY_L com_tlm_u_tlm_rx_data_snk_malformed_checks_un6_malformed_maxsize_cry_3 ( + .CI(com_tlm_u_tlm_rx_data_snk_malformed_checks_un6_malformed_maxsize_cry_2_4119), + .DI(com_tlm_u_tlm_rx_data_snk_malformed_checks_VCC_4140), + .LO(com_tlm_u_tlm_rx_data_snk_malformed_checks_un6_malformed_maxsize_cry_3_4120), + .S(N_6359_i_9) + ); + MUXCY_L com_tlm_u_tlm_rx_data_snk_malformed_checks_un6_malformed_maxsize_cry_4 ( + .CI(com_tlm_u_tlm_rx_data_snk_malformed_checks_un6_malformed_maxsize_cry_3_4120), + .DI(com_tlm_u_tlm_rx_data_snk_malformed_checks_VCC_4140), + .LO(com_tlm_u_tlm_rx_data_snk_malformed_checks_un6_malformed_maxsize_cry_4_4121), + .S(N_6360_i_11) + ); + MUXCY_L com_tlm_u_tlm_rx_data_snk_malformed_checks_un6_malformed_maxsize_cry_5 ( + .CI(com_tlm_u_tlm_rx_data_snk_malformed_checks_un6_malformed_maxsize_cry_4_4121), + .DI(com_tlm_u_tlm_rx_data_snk_cur_length[5]), + .LO(com_tlm_u_tlm_rx_data_snk_malformed_checks_un6_malformed_maxsize_cry_5_4122), + .S(com_tlm_u_tlm_rx_data_snk_malformed_checks_un6_malformed_maxsize_axb_5_i_4219) + ); + MUXCY_L com_tlm_u_tlm_rx_data_snk_malformed_checks_un6_malformed_maxsize_cry_6 ( + .CI(com_tlm_u_tlm_rx_data_snk_malformed_checks_un6_malformed_maxsize_cry_5_4122), + .DI(com_tlm_u_tlm_rx_data_snk_cur_length[6]), + .LO(com_tlm_u_tlm_rx_data_snk_malformed_checks_un6_malformed_maxsize_cry_6_4123), + .S(com_tlm_u_tlm_rx_data_snk_malformed_checks_un6_malformed_maxsize_axb_6_i_4218) + ); + MUXCY_L com_tlm_u_tlm_rx_data_snk_malformed_checks_un6_malformed_maxsize_cry_7 ( + .CI(com_tlm_u_tlm_rx_data_snk_malformed_checks_un6_malformed_maxsize_cry_6_4123), + .DI(com_tlm_u_tlm_rx_data_snk_cur_length[7]), + .LO(com_tlm_u_tlm_rx_data_snk_malformed_checks_un6_malformed_maxsize_cry_7_4124), + .S(com_tlm_u_tlm_rx_data_snk_malformed_checks_un6_malformed_maxsize_axb_7_i_4217) + ); + MUXCY_L com_tlm_u_tlm_rx_data_snk_malformed_checks_un6_malformed_maxsize_cry_8 ( + .CI(com_tlm_u_tlm_rx_data_snk_malformed_checks_un6_malformed_maxsize_cry_7_4124), + .DI(com_tlm_u_tlm_rx_data_snk_malformed_checks_VCC_4140), + .LO(com_tlm_u_tlm_rx_data_snk_malformed_checks_un6_malformed_maxsize_cry_8_4125), + .S(N_6364_i_13) + ); + MUXCY com_tlm_u_tlm_rx_data_snk_malformed_checks_un6_malformed_maxsize_cry_9 ( + .CI(com_tlm_u_tlm_rx_data_snk_malformed_checks_un6_malformed_maxsize_cry_8_4125), + .DI(com_tlm_u_tlm_rx_data_snk_malformed_checks_VCC_4140), + .O(com_tlm_u_tlm_rx_data_snk_malformed_checks_un6_malformed_maxsize_cry_9_4192), + .S(N_6365_i_15) + ); + MUXCY_L com_tlm_u_tlm_rx_data_snk_malformed_checks_un1_data_credits_o_cry_0 ( + .CI(com_tlm_u_tlm_rx_data_snk_malformed_checks_N_36605_i_4149), + .DI(com_tlm_u_tlm_rx_data_snk_malformed_checks_GND_4131), + .LO(com_tlm_u_tlm_rx_data_snk_malformed_checks_un1_data_credits_o_cry_0_4126), + .S(com_tlm_u_tlm_rx_data_snk_malformed_checks_un1_data_credits_o_axb_0_4216) + ); + XORCY com_tlm_u_tlm_rx_data_snk_malformed_checks_un1_data_credits_o_s_0 ( + .CI(com_tlm_u_tlm_rx_data_snk_malformed_checks_N_36605_i_4149), + .LI(com_tlm_u_tlm_rx_data_snk_malformed_checks_un1_data_credits_o_axb_0_4216), + .O(com_tlm_u_tlm_rx_data_snk_malformed_checks_un1_data_credits_o_s_0_4159) + ); + MUXCY_L com_tlm_u_tlm_rx_data_snk_malformed_checks_un1_data_credits_o_cry_1 ( + .CI(com_tlm_u_tlm_rx_data_snk_malformed_checks_un1_data_credits_o_cry_0_4126), + .DI(com_tlm_u_tlm_rx_data_snk_malformed_checks_GND_4131), + .LO(com_tlm_u_tlm_rx_data_snk_malformed_checks_un1_data_credits_o_cry_1_4127), + .S(com_tlm_u_tlm_rx_data_snk_malformed_checks_un1_data_credits_o_axb_1_4215) + ); + XORCY com_tlm_u_tlm_rx_data_snk_malformed_checks_un1_data_credits_o_s_1 ( + .CI(com_tlm_u_tlm_rx_data_snk_malformed_checks_un1_data_credits_o_cry_0_4126), + .LI(com_tlm_u_tlm_rx_data_snk_malformed_checks_un1_data_credits_o_axb_1_4215), + .O(com_tlm_u_tlm_rx_data_snk_malformed_checks_un1_data_credits_o_s_1_4158) + ); + MUXCY_L com_tlm_u_tlm_rx_data_snk_malformed_checks_un1_data_credits_o_cry_2 ( + .CI(com_tlm_u_tlm_rx_data_snk_malformed_checks_un1_data_credits_o_cry_1_4127), + .DI(com_tlm_u_tlm_rx_data_snk_malformed_checks_GND_4131), + .LO(com_tlm_u_tlm_rx_data_snk_malformed_checks_un1_data_credits_o_cry_2_4128), + .S(com_tlm_u_tlm_rx_data_snk_malformed_checks_un1_data_credits_o_axb_2_4214) + ); + XORCY com_tlm_u_tlm_rx_data_snk_malformed_checks_un1_data_credits_o_s_2 ( + .CI(com_tlm_u_tlm_rx_data_snk_malformed_checks_un1_data_credits_o_cry_1_4127), + .LI(com_tlm_u_tlm_rx_data_snk_malformed_checks_un1_data_credits_o_axb_2_4214), + .O(com_tlm_u_tlm_rx_data_snk_malformed_checks_un1_data_credits_o_s_2_4157) + ); + MUXCY_L com_tlm_u_tlm_rx_data_snk_malformed_checks_un1_data_credits_o_cry_3 ( + .CI(com_tlm_u_tlm_rx_data_snk_malformed_checks_un1_data_credits_o_cry_2_4128), + .DI(com_tlm_u_tlm_rx_data_snk_malformed_checks_GND_4131), + .LO(com_tlm_u_tlm_rx_data_snk_malformed_checks_un1_data_credits_o_cry_3_4129), + .S(com_tlm_u_tlm_rx_data_snk_malformed_checks_un1_data_credits_o_axb_3_4213) + ); + XORCY com_tlm_u_tlm_rx_data_snk_malformed_checks_un1_data_credits_o_s_3 ( + .CI(com_tlm_u_tlm_rx_data_snk_malformed_checks_un1_data_credits_o_cry_2_4128), + .LI(com_tlm_u_tlm_rx_data_snk_malformed_checks_un1_data_credits_o_axb_3_4213), + .O(com_tlm_u_tlm_rx_data_snk_malformed_checks_un1_data_credits_o_s_3_4156) + ); + MUXCY_L com_tlm_u_tlm_rx_data_snk_malformed_checks_un1_data_credits_o_cry_4 ( + .CI(com_tlm_u_tlm_rx_data_snk_malformed_checks_un1_data_credits_o_cry_3_4129), + .DI(com_tlm_u_tlm_rx_data_snk_malformed_checks_GND_4131), + .LO(com_tlm_u_tlm_rx_data_snk_malformed_checks_un1_data_credits_o_cry_4_4130), + .S(com_tlm_u_tlm_rx_data_snk_malformed_checks_un1_data_credits_o_axb_4_4212) + ); + XORCY com_tlm_u_tlm_rx_data_snk_malformed_checks_un1_data_credits_o_s_4 ( + .CI(com_tlm_u_tlm_rx_data_snk_malformed_checks_un1_data_credits_o_cry_3_4129), + .LI(com_tlm_u_tlm_rx_data_snk_malformed_checks_un1_data_credits_o_axb_4_4212), + .O(com_tlm_u_tlm_rx_data_snk_malformed_checks_un1_data_credits_o_s_4_4161) + ); + XORCY com_tlm_u_tlm_rx_data_snk_malformed_checks_un1_data_credits_o_s_5 ( + .CI(com_tlm_u_tlm_rx_data_snk_malformed_checks_un1_data_credits_o_cry_4_4130), + .LI(com_tlm_u_tlm_rx_data_snk_malformed_checks_un1_data_credits_o_axb_5_4148), + .O(com_tlm_u_tlm_rx_data_snk_malformed_checks_un1_data_credits_o_s_5_4160) + ); + MUXCY_L com_tlm_u_tlm_rx_data_snk_malformed_checks_un4_word_ct_cry_0 ( + .CI(com_tlm_u_tlm_rx_data_snk_malformed_checks_GND_4131), + .DI(com_tlm_u_tlm_rx_data_snk_malformed_checks_VCC_4140), + .LO(com_tlm_u_tlm_rx_data_snk_malformed_checks_un4_word_ct_cry_0_4133), + .S(com_tlm_u_tlm_rx_data_snk_malformed_checks_word_ct_d_i[0]) + ); + MUXCY_L com_tlm_u_tlm_rx_data_snk_malformed_checks_un4_word_ct_cry_1 ( + .CI(com_tlm_u_tlm_rx_data_snk_malformed_checks_un4_word_ct_cry_0_4133), + .DI(com_tlm_u_tlm_rx_data_snk_malformed_checks_VCC_4140), + .LO(com_tlm_u_tlm_rx_data_snk_malformed_checks_un4_word_ct_cry_1_4135), + .S(com_tlm_u_tlm_rx_data_snk_malformed_checks_word_ct_d_i[1]) + ); + XORCY com_tlm_u_tlm_rx_data_snk_malformed_checks_un4_word_ct_s_1 ( + .CI(com_tlm_u_tlm_rx_data_snk_malformed_checks_un4_word_ct_cry_0_4133), + .LI(com_tlm_u_tlm_rx_data_snk_malformed_checks_word_ct_d_i[1]), + .O(com_tlm_u_tlm_rx_data_snk_malformed_checks_un4_word_ct_s_1_4132) + ); + MUXCY_L com_tlm_u_tlm_rx_data_snk_malformed_checks_un4_word_ct_cry_2 ( + .CI(com_tlm_u_tlm_rx_data_snk_malformed_checks_un4_word_ct_cry_1_4135), + .DI(com_tlm_u_tlm_rx_data_snk_malformed_checks_VCC_4140), + .LO(com_tlm_u_tlm_rx_data_snk_malformed_checks_un4_word_ct_cry_2_4137), + .S(com_tlm_u_tlm_rx_data_snk_malformed_checks_word_ct_d_i[2]) + ); + XORCY com_tlm_u_tlm_rx_data_snk_malformed_checks_un4_word_ct_s_2 ( + .CI(com_tlm_u_tlm_rx_data_snk_malformed_checks_un4_word_ct_cry_1_4135), + .LI(com_tlm_u_tlm_rx_data_snk_malformed_checks_word_ct_d_i[2]), + .O(com_tlm_u_tlm_rx_data_snk_malformed_checks_un4_word_ct_s_2_4134) + ); + MUXCY_L com_tlm_u_tlm_rx_data_snk_malformed_checks_un4_word_ct_cry_3 ( + .CI(com_tlm_u_tlm_rx_data_snk_malformed_checks_un4_word_ct_cry_2_4137), + .DI(com_tlm_u_tlm_rx_data_snk_malformed_checks_VCC_4140), + .LO(com_tlm_u_tlm_rx_data_snk_malformed_checks_un4_word_ct_cry_3_4139), + .S(com_tlm_u_tlm_rx_data_snk_malformed_checks_word_ct_d_i[3]) + ); + XORCY com_tlm_u_tlm_rx_data_snk_malformed_checks_un4_word_ct_s_3 ( + .CI(com_tlm_u_tlm_rx_data_snk_malformed_checks_un4_word_ct_cry_2_4137), + .LI(com_tlm_u_tlm_rx_data_snk_malformed_checks_word_ct_d_i[3]), + .O(com_tlm_u_tlm_rx_data_snk_malformed_checks_un4_word_ct_s_3_4136) + ); + MUXCY_L com_tlm_u_tlm_rx_data_snk_malformed_checks_un4_word_ct_cry_4 ( + .CI(com_tlm_u_tlm_rx_data_snk_malformed_checks_un4_word_ct_cry_3_4139), + .DI(com_tlm_u_tlm_rx_data_snk_malformed_checks_VCC_4140), + .LO(com_tlm_u_tlm_rx_data_snk_malformed_checks_un4_word_ct_cry_4_4142), + .S(com_tlm_u_tlm_rx_data_snk_malformed_checks_word_ct_d_i[4]) + ); + XORCY com_tlm_u_tlm_rx_data_snk_malformed_checks_un4_word_ct_s_4 ( + .CI(com_tlm_u_tlm_rx_data_snk_malformed_checks_un4_word_ct_cry_3_4139), + .LI(com_tlm_u_tlm_rx_data_snk_malformed_checks_word_ct_d_i[4]), + .O(com_tlm_u_tlm_rx_data_snk_malformed_checks_un4_word_ct_s_4_4138) + ); + MUXCY_L com_tlm_u_tlm_rx_data_snk_malformed_checks_un4_word_ct_cry_5 ( + .CI(com_tlm_u_tlm_rx_data_snk_malformed_checks_un4_word_ct_cry_4_4142), + .DI(com_tlm_u_tlm_rx_data_snk_malformed_checks_VCC_4140), + .LO(com_tlm_u_tlm_rx_data_snk_malformed_checks_un4_word_ct_cry_5_4144), + .S(com_tlm_u_tlm_rx_data_snk_malformed_checks_word_ct_d_i[5]) + ); + XORCY com_tlm_u_tlm_rx_data_snk_malformed_checks_un4_word_ct_s_5 ( + .CI(com_tlm_u_tlm_rx_data_snk_malformed_checks_un4_word_ct_cry_4_4142), + .LI(com_tlm_u_tlm_rx_data_snk_malformed_checks_word_ct_d_i[5]), + .O(com_tlm_u_tlm_rx_data_snk_malformed_checks_un4_word_ct_s_5_4141) + ); + XORCY com_tlm_u_tlm_rx_data_snk_malformed_checks_un4_word_ct_s_6 ( + .CI(com_tlm_u_tlm_rx_data_snk_malformed_checks_un4_word_ct_cry_5_4144), + .LI(com_tlm_u_tlm_rx_data_snk_malformed_checks_word_ct_d_i[6]), + .O(com_tlm_u_tlm_rx_data_snk_malformed_checks_un4_word_ct_s_6_4143) + ); + FDR com_tlm_u_tlm_rx_data_snk_malformed_checks_delay_ct ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_malformed_checks_delay_ctc_i), + .Q(com_tlm_u_tlm_rx_data_snk_malformed_checks_delay_ct_4211), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_rx_data_snk_malformed_checks_load_aperture_q ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_sof_q_1__4097), + .Q(com_tlm_u_tlm_rx_data_snk_latch_3rd_dword_q1), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_rx_data_snk_malformed_checks_eof_q2 ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_eof_q_1__4073), + .Q(com_tlm_u_tlm_rx_data_snk_malformed_checks_eof_q2_4145), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_rx_data_snk_malformed_checks_eval_formats_q ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_latch_1st_dword_q1_4028), + .Q(com_tlm_u_tlm_rx_data_snk_latch_1st_dword_q2), + .R(plm_link_up_i) + ); + defparam com_tlm_u_tlm_rx_data_snk_malformed_checks_tlp_uc_o_0_sqmuxa_0_a2.INIT = 4'h8; + LUT2 com_tlm_u_tlm_rx_data_snk_malformed_checks_tlp_uc_o_0_sqmuxa_0_a2 ( + .I0(com_tlm_u_tlm_rx_data_snk_malformed_checks_uc_format_4146), + .I1(com_tlm_u_tlm_rx_data_snk_sof_q_4_), + .O(com_tlm_u_tlm_rx_data_snk_malformed_checks_tlp_uc_o_0_sqmuxa) + ); + defparam com_tlm_u_tlm_rx_data_snk_malformed_checks_tlp_ur_o_0_sqmuxa_0_a2.INIT = 4'h8; + LUT2 com_tlm_u_tlm_rx_data_snk_malformed_checks_tlp_ur_o_0_sqmuxa_0_a2 ( + .I0(com_tlm_u_tlm_rx_data_snk_malformed_checks_ur_format_4147), + .I1(com_tlm_u_tlm_rx_data_snk_sof_q_4_), + .O(com_tlm_u_tlm_rx_data_snk_malformed_checks_tlp_ur_o_0_sqmuxa) + ); + defparam com_tlm_u_tlm_rx_data_snk_malformed_checks_malformed_fulltype16_0_0_0_o3.INIT = 4'h1; + LUT2 com_tlm_u_tlm_rx_data_snk_malformed_checks_malformed_fulltype16_0_0_0_o3 ( + .I0(com_tlm_u_tlm_rx_data_snk_malformed_checks_cur_fulltype[1]), + .I1(com_tlm_u_tlm_rx_data_snk_malformed_checks_cur_fulltype[2]), + .O(com_tlm_u_tlm_rx_data_snk_N_36382_i) + ); + defparam com_tlm_u_tlm_rx_data_snk_malformed_checks_type_1dw_0_sqmuxa_i_0_0_o2.INIT = 4'h1; + LUT2 com_tlm_u_tlm_rx_data_snk_malformed_checks_type_1dw_0_sqmuxa_i_0_0_o2 ( + .I0(com_tlm_u_tlm_rx_data_snk_malformed_checks_cur_fulltype[3]), + .I1(com_tlm_u_tlm_rx_data_snk_malformed_checks_cur_fulltype[4]), + .O(com_tlm_u_tlm_rx_data_snk_N_36397_i) + ); + defparam com_tlm_u_tlm_rx_data_snk_malformed_checks_un1_reset_i_1_0_i_0_o3.INIT = 4'h8; + LUT2 com_tlm_u_tlm_rx_data_snk_malformed_checks_un1_reset_i_1_0_i_0_o3 ( + .I0(com_tlm_u_tlm_rx_data_snk_cur_fulltype[6]), + .I1(com_tlm_u_tlm_rx_data_snk_cur_length_0__2), + .O(com_tlm_u_tlm_rx_data_snk_malformed_checks_N_36402_i) + ); + defparam com_tlm_u_tlm_rx_data_snk_malformed_checks_ur_pwr_mgmt_7_i_0_0_o3.INIT = 4'h1; + LUT2 com_tlm_u_tlm_rx_data_snk_malformed_checks_ur_pwr_mgmt_7_i_0_0_o3 ( + .I0(com_tlm_u_tlm_rx_data_snk_malformed_checks_fulltype_in_0__4197), + .I1(com_tlm_u_tlm_rx_data_snk_malformed_checks_fulltype_in_5__4196), + .O(com_tlm_u_tlm_rx_data_snk_malformed_checks_N_36412_i) + ); + defparam com_tlm_u_tlm_rx_data_snk_malformed_checks_cfg1_ip_0_sqmuxa_0_a2_0_a2_0_a2_2.INIT = 4'h4; + LUT2 com_tlm_u_tlm_rx_data_snk_malformed_checks_cfg1_ip_0_sqmuxa_0_a2_0_a2_0_a2_2 ( + .I0(com_tlm_u_tlm_rx_data_snk_malformed_checks_cur_fulltype[1]), + .I1(com_tlm_u_tlm_rx_data_snk_malformed_checks_cur_fulltype[2]), + .O(com_tlm_u_tlm_rx_data_snk_malformed_checks_cfg1_ip_0_sqmuxa_2) + ); + defparam com_tlm_u_tlm_rx_data_snk_malformed_checks_malformed_message_6_0_0_0_x3.INIT = 4'h6; + LUT2_L com_tlm_u_tlm_rx_data_snk_malformed_checks_malformed_message_6_0_0_0_x3 ( + .I0(com_tlm_u_tlm_rx_data_snk_malformed_checks_cur_fulltype[1]), + .I1(com_tlm_u_tlm_rx_data_snk_malformed_checks_msgcode_routing[1]), + .LO(com_tlm_u_tlm_rx_data_snk_malformed_checks_N_36403_i_0) + ); + defparam com_tlm_u_tlm_rx_data_snk_malformed_checks_type_1dw_0_sqmuxa_i_0_0_o2_0.INIT = 4'h8; + LUT2 com_tlm_u_tlm_rx_data_snk_malformed_checks_type_1dw_0_sqmuxa_i_0_0_o2_0 ( + .I0(com_tlm_u_tlm_rx_data_snk_latch_1st_dword_q1_4028), + .I1(plm_link_up_1), + .O(com_tlm_u_tlm_rx_data_snk_malformed_checks_N_36398_i) + ); + defparam com_tlm_u_tlm_rx_data_snk_malformed_checks_msgcode_sigdef16_0_0_o3.INIT = 4'h2; + LUT2 com_tlm_u_tlm_rx_data_snk_malformed_checks_msgcode_sigdef16_0_0_o3 ( + .I0(com_lnk_rd[4]), + .I1(com_lnk_rd[5]), + .O(com_tlm_u_tlm_rx_data_snk_N_36390_i) + ); + defparam com_tlm_u_tlm_rx_data_snk_malformed_checks_msgcode_hotplug12_0_0_o2_1.INIT = 4'h1; + LUT2 com_tlm_u_tlm_rx_data_snk_malformed_checks_msgcode_hotplug12_0_0_o2_1 ( + .I0(com_lnk_rd[4]), + .I1(com_lnk_rd[5]), + .O(com_tlm_u_tlm_rx_data_snk_N_36443_i) + ); + defparam com_tlm_u_tlm_rx_data_snk_malformed_checks_un1_data_credits_o_axb_5.INIT = 4'h2; + LUT1 com_tlm_u_tlm_rx_data_snk_malformed_checks_un1_data_credits_o_axb_5 ( + .I0(com_tlm_u_tlm_rx_data_snk_cur_length[7]), + .O(com_tlm_u_tlm_rx_data_snk_malformed_checks_un1_data_credits_o_axb_5_4148) + ); + defparam com_tlm_u_tlm_rx_data_snk_malformed_checks_malformed_maxsize_3_0_0_a2_0_2.INIT = 4'h1; + LUT2 com_tlm_u_tlm_rx_data_snk_malformed_checks_malformed_maxsize_3_0_0_a2_0_2 ( + .I0(com_tlm_u_tlm_rx_data_snk_cur_length_3__8), + .I1(com_tlm_u_tlm_rx_data_snk_cur_length_8__12), + .O(com_tlm_u_tlm_rx_data_snk_malformed_checks_N_36455_2) + ); + defparam com_tlm_u_tlm_rx_data_snk_malformed_checks_check_int_un1_msgcode_routing19_0_0_o3.INIT = 8'h01; + LUT3 com_tlm_u_tlm_rx_data_snk_malformed_checks_check_int_un1_msgcode_routing19_0_0_o3 ( + .I0(com_lnk_rd[0]), + .I1(com_lnk_rd[1]), + .I2(com_lnk_rd[3]), + .O(com_tlm_u_tlm_rx_data_snk_malformed_checks_N_36392_i) + ); + defparam com_tlm_u_tlm_rx_data_snk_malformed_checks_msgcode_hotplug12_0_0_o2_0.INIT = 8'h07; + LUT3 com_tlm_u_tlm_rx_data_snk_malformed_checks_msgcode_hotplug12_0_0_o2_0 ( + .I0(com_lnk_rd[2]), + .I1(com_lnk_rd[3]), + .I2(com_lnk_rd_5077[7]), + .O(N_36431_i) + ); + defparam com_tlm_u_tlm_rx_data_snk_malformed_checks_ismsgany17_0_a2_0_o3_0_.INIT = 8'h40; + LUT3 com_tlm_u_tlm_rx_data_snk_malformed_checks_ismsgany17_0_a2_0_o3_0_ ( + .I0(com_lnk_rd_5077[59]), + .I1(com_lnk_rd_5077[60]), + .I2(com_lnk_rd_5077[61]), + .O(com_tlm_u_tlm_rx_data_snk_malformed_checks_N_36385_i) + ); + defparam com_tlm_u_tlm_rx_data_snk_malformed_checks_N_36605_i.INIT = 4'hE; + LUT2 com_tlm_u_tlm_rx_data_snk_malformed_checks_N_36605_i ( + .I0(com_tlm_u_tlm_rx_data_snk_cur_length_0__2), + .I1(com_tlm_u_tlm_rx_data_snk_cur_length_1__4), + .O(com_tlm_u_tlm_rx_data_snk_malformed_checks_N_36605_i_4149) + ); + defparam com_tlm_u_tlm_rx_data_snk_malformed_checks_check_int_un1_msgcode_routing19_0_0_1.INIT = 16'h0001; + LUT4 com_tlm_u_tlm_rx_data_snk_malformed_checks_check_int_un1_msgcode_routing19_0_0_1 ( + .I0(com_lnk_rd[2]), + .I1(com_lnk_rd[5]), + .I2(com_lnk_rd[6]), + .I3(com_lnk_rd_5077[7]), + .O(com_tlm_u_tlm_rx_data_snk_malformed_checks_N_9487_i_1) + ); + defparam com_tlm_u_tlm_rx_data_snk_malformed_checks_N_9208_i_0_0_0_o2.INIT = 8'h10; + LUT3 com_tlm_u_tlm_rx_data_snk_malformed_checks_N_9208_i_0_0_0_o2 ( + .I0(com_lnk_reof_n), + .I1(com_lnk_rsrc_rdy_n), + .I2(com_tlm_u_tlm_rx_data_snk_packet_ip_4048), + .O(com_tlm_u_tlm_rx_data_snk_N_36411_i) + ); + defparam com_tlm_u_tlm_rx_data_snk_malformed_checks_malformed_eof_3_i_0_a2_0_4.INIT = 16'h0001; + LUT4_L com_tlm_u_tlm_rx_data_snk_malformed_checks_malformed_eof_3_i_0_a2_0_4 ( + .I0(com_tlm_u_tlm_rx_data_snk_malformed_checks_word_ct[0]), + .I1(com_tlm_u_tlm_rx_data_snk_malformed_checks_word_ct[1]), + .I2(com_tlm_u_tlm_rx_data_snk_malformed_checks_word_ct[4]), + .I3(com_tlm_u_tlm_rx_data_snk_malformed_checks_word_ct[5]), + .LO(com_tlm_u_tlm_rx_data_snk_malformed_checks_malformed_eof_3_i_0_a2_0_4_4195) + ); + defparam com_tlm_u_tlm_rx_data_snk_malformed_checks_malformed_over_3_i_0_o3_4.INIT = 16'h8000; + LUT4_L com_tlm_u_tlm_rx_data_snk_malformed_checks_malformed_over_3_i_0_o3_4 ( + .I0(com_tlm_u_tlm_rx_data_snk_malformed_checks_word_ct[0]), + .I1(com_tlm_u_tlm_rx_data_snk_malformed_checks_word_ct[4]), + .I2(com_tlm_u_tlm_rx_data_snk_malformed_checks_word_ct[5]), + .I3(com_tlm_u_tlm_rx_data_snk_malformed_checks_word_ct[6]), + .LO(com_tlm_u_tlm_rx_data_snk_malformed_checks_malformed_over_3_i_0_o3_4_4153) + ); + defparam com_tlm_u_tlm_rx_data_snk_malformed_checks_malformed_maxsize_3_0_0_a2_0_1_3.INIT = 16'h0001; + LUT4_L com_tlm_u_tlm_rx_data_snk_malformed_checks_malformed_maxsize_3_0_0_a2_0_1_3 ( + .I0(com_tlm_u_tlm_rx_data_snk_cur_length_2__6), + .I1(com_tlm_u_tlm_rx_data_snk_cur_length[5]), + .I2(com_tlm_u_tlm_rx_data_snk_cur_length[6]), + .I3(com_tlm_u_tlm_rx_data_snk_cur_length[7]), + .LO(com_tlm_u_tlm_rx_data_snk_malformed_checks_malformed_maxsize_3_0_0_a2_0_1_3_4154) + ); + defparam com_tlm_u_tlm_rx_data_snk_malformed_checks_uc_pwr_mgmt_7_0_a2_0_a2_0_a2_1.INIT = 16'h0400; + LUT4_L com_tlm_u_tlm_rx_data_snk_malformed_checks_uc_pwr_mgmt_7_0_a2_0_a2_0_a2_1 ( + .I0(com_tlm_u_tlm_rx_data_snk_malformed_checks_cur_fulltype[2]), + .I1(com_tlm_u_tlm_rx_data_snk_malformed_checks_cur_fulltype[3]), + .I2(com_tlm_u_tlm_rx_data_snk_malformed_checks_fulltype_in_5__4196), + .I3(com_tlm_u_tlm_rx_data_snk_pwr_mgmt_mode_on_4016), + .LO(com_tlm_u_tlm_rx_data_snk_malformed_checks_uc_pwr_mgmt_7_0_a2_0_a2_0_a2_1_4180) + ); + defparam com_tlm_u_tlm_rx_data_snk_malformed_checks_msgcode_vendef12_0_a2_0_a2_1_0.INIT = 16'h8000; + LUT4_L com_tlm_u_tlm_rx_data_snk_malformed_checks_msgcode_vendef12_0_a2_0_a2_1_0 ( + .I0(com_lnk_rd[1]), + .I1(com_lnk_rd[2]), + .I2(com_lnk_rd[4]), + .I3(com_lnk_rd[6]), + .LO(com_tlm_u_tlm_rx_data_snk_malformed_checks_msgcode_vendef12_0_a2_0_a2_1) + ); + defparam com_tlm_u_tlm_rx_data_snk_malformed_checks_malformed_fmt_3_i_0_2.INIT = 16'h4C5F; + LUT4_L com_tlm_u_tlm_rx_data_snk_malformed_checks_malformed_fmt_3_i_0_2 ( + .I0(com_tlm_u_tlm_rx_data_snk_cur_fulltype_oh_1_), + .I1(com_tlm_u_tlm_rx_data_snk_malformed_checks_length_1dw_4152), + .I2(com_tlm_u_tlm_rx_data_snk_malformed_checks_malformed_message_4151), + .I3(com_tlm_u_tlm_rx_data_snk_malformed_checks_type_1dw_4150), + .LO(com_tlm_u_tlm_rx_data_snk_malformed_checks_malformed_fmt_3_i_0_2_4179) + ); + defparam com_tlm_u_tlm_rx_data_snk_malformed_checks_is_usr_leg_ap_3_0_a2_0_a2_0_a2_0_a2_2.INIT = 16'h0001; + LUT4 com_tlm_u_tlm_rx_data_snk_malformed_checks_is_usr_leg_ap_3_0_a2_0_a2_0_a2_0_a2_2 ( + .I0(com_lnk_rd_5077[40]), + .I1(com_lnk_rd_5077[41]), + .I2(com_lnk_rd_5077[42]), + .I3(com_lnk_rd_5077[43]), + .O(com_tlm_u_tlm_rx_data_snk_malformed_checks_is_usr_leg_ap_3_0_a2_0_a2_0_a2_0_a2_2_4169) + ); + defparam com_tlm_u_tlm_rx_data_snk_malformed_checks_ur_pwr_mgmt_7_i_0_0_0.INIT = 16'h1500; + LUT4 com_tlm_u_tlm_rx_data_snk_malformed_checks_ur_pwr_mgmt_7_i_0_0_0 ( + .I0(com_tlm_u_tlm_rx_data_snk_malformed_checks_cur_fulltype[2]), + .I1(com_tlm_u_tlm_rx_data_snk_cur_fulltype[6]), + .I2(com_tlm_u_tlm_rx_data_snk_malformed_checks_fulltype_in_0__4197), + .I3(com_tlm_u_tlm_rx_data_snk_pwr_mgmt_mode_on_4016), + .O(com_tlm_u_tlm_rx_data_snk_malformed_checks_ur_pwr_mgmt_7_i_0_0_0_4189) + ); + defparam com_tlm_u_tlm_rx_data_snk_malformed_checks_msgcode_sigdef16_0_0_0.INIT = 16'h0007; + LUT4 com_tlm_u_tlm_rx_data_snk_malformed_checks_msgcode_sigdef16_0_0_0 ( + .I0(com_lnk_rd[2]), + .I1(com_lnk_rd[4]), + .I2(com_lnk_rd[6]), + .I3(com_lnk_rd_5077[7]), + .O(com_tlm_u_tlm_rx_data_snk_malformed_checks_msgcode_sigdef16_0_0_0_4187) + ); + defparam com_tlm_u_tlm_rx_data_snk_malformed_checks_check_int_msgcode_routing18_0_0_m2_0.INIT = 8'h7E; + LUT3 com_tlm_u_tlm_rx_data_snk_malformed_checks_check_int_msgcode_routing18_0_0_m2_0 ( + .I0(com_lnk_rd[0]), + .I1(com_lnk_rd[3]), + .I2(com_lnk_rd[4]), + .O(com_tlm_u_tlm_rx_data_snk_malformed_checks_N_36436) + ); + defparam com_tlm_u_tlm_rx_data_snk_malformed_checks_word_ct_d_1_0_0_.INIT = 16'h707F; + LUT4 com_tlm_u_tlm_rx_data_snk_malformed_checks_word_ct_d_1_0_0_ ( + .I0(com_tlm_u_tlm_rx_data_snk_cur_fulltype[6]), + .I1(com_tlm_u_tlm_rx_data_snk_cur_length_1__4), + .I2(com_tlm_u_tlm_rx_data_snk_latch_1st_dword_q1_4028), + .I3(com_tlm_u_tlm_rx_data_snk_malformed_checks_word_ct[0]), + .O(com_tlm_u_tlm_rx_data_snk_malformed_checks_word_ct_d_i[0]) + ); + defparam com_tlm_u_tlm_rx_data_snk_malformed_checks_fulltype_tc012_i_0_a2_0.INIT = 16'h0008; + LUT4 com_tlm_u_tlm_rx_data_snk_malformed_checks_fulltype_tc012_i_0_a2_0 ( + .I0(com_tlm_u_tlm_rx_data_snk_N_36407_i), + .I1(com_lnk_rd_5077[58]), + .I2(com_lnk_rd_5077[60]), + .I3(com_lnk_rd_5077[61]), + .O(com_tlm_u_tlm_rx_data_snk_malformed_checks_N_36516) + ); + defparam com_tlm_u_tlm_rx_data_snk_malformed_checks_malformed_over_3_i_0_o3.INIT = 16'h8000; + LUT4 com_tlm_u_tlm_rx_data_snk_malformed_checks_malformed_over_3_i_0_o3 ( + .I0(com_tlm_u_tlm_rx_data_snk_malformed_checks_malformed_over_3_i_0_o3_4_4153), + .I1(com_tlm_u_tlm_rx_data_snk_malformed_checks_word_ct[1]), + .I2(com_tlm_u_tlm_rx_data_snk_malformed_checks_word_ct[2]), + .I3(com_tlm_u_tlm_rx_data_snk_malformed_checks_word_ct[3]), + .O(com_tlm_u_tlm_rx_data_snk_malformed_checks_N_36439_i) + ); + defparam com_tlm_u_tlm_rx_data_snk_malformed_checks_cfg0_ip_0_sqmuxa_0_a2_0_a2_0_a2.INIT = 16'h8000; + LUT4 com_tlm_u_tlm_rx_data_snk_malformed_checks_cfg0_ip_0_sqmuxa_0_a2_0_a2_0_a2 ( + .I0(com_tlm_u_tlm_rx_data_snk_N_36397_i), + .I1(com_tlm_u_tlm_rx_data_snk_malformed_checks_N_36398_i), + .I2(com_tlm_u_tlm_rx_data_snk_malformed_checks_N_36412_i), + .I3(com_tlm_u_tlm_rx_data_snk_malformed_checks_cfg1_ip_0_sqmuxa_2), + .O(com_tlm_u_tlm_rx_data_snk_malformed_checks_cfg0_ip_0_sqmuxa) + ); + defparam com_tlm_u_tlm_rx_data_snk_malformed_checks_malformed_message_6_0_0_0_a2_0.INIT = 16'h00D0; + LUT4_L com_tlm_u_tlm_rx_data_snk_malformed_checks_malformed_message_6_0_0_0_a2_0 ( + .I0(com_tlm_u_tlm_rx_data_snk_N_36382_i), + .I1(com_tlm_u_tlm_rx_data_snk_malformed_checks_fulltype_in_0__4197), + .I2(com_tlm_u_tlm_rx_data_snk_malformed_checks_msgcode_vendef_4207), + .I3(com_tlm_u_tlm_rx_data_snk_malformed_checks_routing_vendef_4199), + .LO(com_tlm_u_tlm_rx_data_snk_malformed_checks_N_36450) + ); + defparam com_tlm_u_tlm_rx_data_snk_malformed_checks_malformed_fulltype16_0_0_0_a2_4.INIT = 8'h40; + LUT3_L com_tlm_u_tlm_rx_data_snk_malformed_checks_malformed_fulltype16_0_0_0_a2_4 ( + .I0(com_tlm_u_tlm_rx_data_snk_malformed_checks_cur_fulltype[2]), + .I1(com_tlm_u_tlm_rx_data_snk_cur_fulltype[6]), + .I2(com_tlm_u_tlm_rx_data_snk_malformed_checks_cfg1_ip_0_sqmuxa_1), + .LO(com_tlm_u_tlm_rx_data_snk_malformed_checks_N_36479) + ); + defparam com_tlm_u_tlm_rx_data_snk_malformed_checks_malformed_maxsize_3_0_0_a2_0_1.INIT = 8'h10; + LUT3 com_tlm_u_tlm_rx_data_snk_malformed_checks_malformed_maxsize_3_0_0_a2_0_1 ( + .I0(com_tlm_u_tlm_rx_data_snk_cur_length_4__10), + .I1(com_tlm_u_tlm_rx_data_snk_cur_length_9__14), + .I2(com_tlm_u_tlm_rx_data_snk_malformed_checks_malformed_maxsize_3_0_0_a2_0_1_3_4154), + .O(com_tlm_u_tlm_rx_data_snk_malformed_checks_N_36455_1) + ); + defparam com_tlm_u_tlm_rx_data_snk_malformed_checks_N_9208_i_0_0_0_32079.INIT = 8'hD4; + LUT3 com_tlm_u_tlm_rx_data_snk_malformed_checks_N_9208_i_0_0_0_32079 ( + .I0(com_lnk_rrem[0]), + .I1(com_tlm_u_tlm_rx_data_snk_cur_td_4080), + .I2(com_tlm_u_tlm_rx_data_snk_malformed_checks_fulltype_in_5__4196), + .O(com_tlm_u_tlm_rx_data_snk_malformed_checks_N_9208_i_0_0_0_32079_4194) + ); + defparam com_tlm_u_tlm_rx_data_snk_malformed_checks_type_1dw_0_sqmuxa_i_0_0_32148.INIT = 8'h46; + LUT3 com_tlm_u_tlm_rx_data_snk_malformed_checks_type_1dw_0_sqmuxa_i_0_0_32148 ( + .I0(com_tlm_u_tlm_rx_data_snk_malformed_checks_cur_fulltype[1]), + .I1(com_tlm_u_tlm_rx_data_snk_malformed_checks_cur_fulltype[2]), + .I2(com_tlm_u_tlm_rx_data_snk_malformed_checks_fulltype_in_0__4197), + .O(com_tlm_u_tlm_rx_data_snk_malformed_checks_type_1dw_0_sqmuxa_i_0_0_32148_4155) + ); + defparam com_tlm_u_tlm_rx_data_snk_malformed_checks_msgcode_sigdef16_0_0_32156.INIT = 16'h3380; + LUT4 com_tlm_u_tlm_rx_data_snk_malformed_checks_msgcode_sigdef16_0_0_32156 ( + .I0(com_lnk_rd[1]), + .I1(com_lnk_rd[3]), + .I2(com_lnk_rd[4]), + .I3(com_lnk_rd[5]), + .O(com_tlm_u_tlm_rx_data_snk_malformed_checks_msgcode_sigdef16_0_0_32156_4188) + ); + defparam com_tlm_u_tlm_rx_data_snk_malformed_checks_malformed_maxsize_3_0_0_a2_0_1_4.INIT = 16'h0008; + LUT4 com_tlm_u_tlm_rx_data_snk_malformed_checks_malformed_maxsize_3_0_0_a2_0_1_4 ( + .I0(com_tlm_u_tlm_rx_data_snk_malformed_checks_N_36455_2), + .I1(com_tlm_u_tlm_rx_data_snk_cur_fulltype[6]), + .I2(com_tlm_u_tlm_rx_data_snk_cur_length_0__2), + .I3(com_tlm_u_tlm_rx_data_snk_cur_length_1__4), + .O(com_tlm_u_tlm_rx_data_snk_malformed_checks_malformed_maxsize_3_0_0_a2_0_1_4193) + ); + defparam com_tlm_u_tlm_rx_data_snk_malformed_checks_msgd_check_64_msgcode_dmatch_4_0_x2_0_o3_0_1.INIT = 16'h0020; + LUT4_L com_tlm_u_tlm_rx_data_snk_malformed_checks_msgd_check_64_msgcode_dmatch_4_0_x2_0_o3_0_1 ( + .I0(com_tlm_u_tlm_rx_data_snk_N_36390_i), + .I1(com_lnk_rd[2]), + .I2(com_lnk_rd[6]), + .I3(com_lnk_rd_5077[7]), + .LO(com_tlm_u_tlm_rx_data_snk_malformed_checks_msgcode_dmatch_4_0_x2_0_o3_0_1) + ); + defparam com_tlm_u_tlm_rx_data_snk_malformed_checks_malformed_message_6_0_0_0_1.INIT = 16'hFF41; + LUT4 com_tlm_u_tlm_rx_data_snk_malformed_checks_malformed_message_6_0_0_0_1 ( + .I0(com_tlm_u_tlm_rx_data_snk_malformed_checks_N_36403_i_0), + .I1(com_tlm_u_tlm_rx_data_snk_malformed_checks_cur_fulltype[2]), + .I2(com_tlm_u_tlm_rx_data_snk_malformed_checks_msgcode_routing[2]), + .I3(com_tlm_u_tlm_rx_data_snk_malformed_checks_msgcode_vendef_4207), + .O(com_tlm_u_tlm_rx_data_snk_malformed_checks_malformed_message_6_0_0_0_1_4208) + ); + defparam com_tlm_u_tlm_rx_data_snk_malformed_checks_cfg1_ip_0_sqmuxa_0_a2_0_a2_0_a2.INIT = 16'h0080; + LUT4 com_tlm_u_tlm_rx_data_snk_malformed_checks_cfg1_ip_0_sqmuxa_0_a2_0_a2_0_a2 ( + .I0(com_tlm_u_tlm_rx_data_snk_malformed_checks_N_36398_i), + .I1(com_tlm_u_tlm_rx_data_snk_malformed_checks_cfg1_ip_0_sqmuxa_1), + .I2(com_tlm_u_tlm_rx_data_snk_malformed_checks_cfg1_ip_0_sqmuxa_2), + .I3(com_tlm_u_tlm_rx_data_snk_malformed_checks_fulltype_in_5__4196), + .O(com_tlm_u_tlm_rx_data_snk_malformed_checks_cfg1_ip_0_sqmuxa) + ); + defparam com_tlm_u_tlm_rx_data_snk_malformed_checks_malformed_fulltype16_0_0_0_32147.INIT = 16'hF107; + LUT4 com_tlm_u_tlm_rx_data_snk_malformed_checks_malformed_fulltype16_0_0_0_32147 ( + .I0(com_tlm_u_tlm_rx_data_snk_malformed_checks_cur_fulltype[1]), + .I1(com_tlm_u_tlm_rx_data_snk_malformed_checks_cur_fulltype[2]), + .I2(com_tlm_u_tlm_rx_data_snk_malformed_checks_cur_fulltype[4]), + .I3(com_tlm_u_tlm_rx_data_snk_malformed_checks_fulltype_in_5__4196), + .O(com_tlm_u_tlm_rx_data_snk_malformed_checks_malformed_fulltype16_0_0_0_32147_4186) + ); + defparam com_tlm_u_tlm_rx_data_snk_malformed_checks_malformed_fulltype16_0_0_0_0.INIT = 16'h0545; + LUT4_L com_tlm_u_tlm_rx_data_snk_malformed_checks_malformed_fulltype16_0_0_0_0 ( + .I0(com_tlm_u_tlm_rx_data_snk_malformed_checks_N_36479), + .I1(com_tlm_u_tlm_rx_data_snk_malformed_checks_cur_fulltype[1]), + .I2(com_tlm_u_tlm_rx_data_snk_malformed_checks_cur_fulltype[3]), + .I3(com_tlm_u_tlm_rx_data_snk_malformed_checks_cur_fulltype[4]), + .LO(com_tlm_u_tlm_rx_data_snk_malformed_checks_malformed_fulltype16_0_0_0_0_4185) + ); + defparam com_tlm_u_tlm_rx_data_snk_malformed_checks_fulltype_tc012_i_0_0.INIT = 16'h5515; + LUT4_L com_tlm_u_tlm_rx_data_snk_malformed_checks_fulltype_tc012_i_0_0 ( + .I0(com_tlm_u_tlm_rx_data_snk_malformed_checks_N_36516), + .I1(com_tlm_u_tlm_rx_data_snk_N_36569_1), + .I2(com_lnk_rd_5077[56]), + .I3(com_lnk_rd_5077[62]), + .LO(com_tlm_u_tlm_rx_data_snk_malformed_checks_fulltype_tc012_i_0_0_4183) + ); + defparam com_tlm_u_tlm_rx_data_snk_malformed_checks_type_1dw_0_sqmuxa_i_0_0.INIT = 16'h0080; + LUT4 com_tlm_u_tlm_rx_data_snk_malformed_checks_type_1dw_0_sqmuxa_i_0_0 ( + .I0(com_tlm_u_tlm_rx_data_snk_N_36397_i), + .I1(com_tlm_u_tlm_rx_data_snk_malformed_checks_N_36398_i), + .I2(com_tlm_u_tlm_rx_data_snk_malformed_checks_type_1dw_0_sqmuxa_i_0_0_32148_4155), + .I3(com_tlm_u_tlm_rx_data_snk_malformed_checks_fulltype_in_5__4196), + .O(com_tlm_u_tlm_rx_data_snk_malformed_checks_N_11858_i) + ); + defparam com_tlm_u_tlm_rx_data_snk_malformed_checks_delay_ctc.INIT = 16'hE080; + LUT4_L com_tlm_u_tlm_rx_data_snk_malformed_checks_delay_ctc ( + .I0(com_tlm_u_tlm_rx_data_snk_malformed_checks_N_36402_i), + .I1(com_tlm_u_tlm_rx_data_snk_cur_td_4080), + .I2(com_tlm_u_tlm_rx_data_snk_latch_1st_dword_q1_4028), + .I3(com_tlm_u_tlm_rx_data_snk_malformed_checks_fulltype_in_5__4196), + .LO(com_tlm_u_tlm_rx_data_snk_malformed_checks_delay_ctc_i) + ); + defparam com_tlm_u_tlm_rx_data_snk_malformed_checks_un11_data_credits_o_1_a2_0_a2_3_.INIT = 4'h8; + LUT2_L com_tlm_u_tlm_rx_data_snk_malformed_checks_un11_data_credits_o_1_a2_0_a2_3_ ( + .I0(com_tlm_u_tlm_rx_data_snk_malformed_checks_un1_data_credits_o_s_3_4156), + .I1(com_tlm_u_tlm_rx_data_snk_cur_fulltype[6]), + .LO(com_tlm_u_tlm_rx_data_snk_malformed_checks_N_36601) + ); + defparam com_tlm_u_tlm_rx_data_snk_malformed_checks_un11_data_credits_o_1_a2_0_a2_2_.INIT = 4'h8; + LUT2_L com_tlm_u_tlm_rx_data_snk_malformed_checks_un11_data_credits_o_1_a2_0_a2_2_ ( + .I0(com_tlm_u_tlm_rx_data_snk_malformed_checks_un1_data_credits_o_s_2_4157), + .I1(com_tlm_u_tlm_rx_data_snk_cur_fulltype[6]), + .LO(com_tlm_u_tlm_rx_data_snk_malformed_checks_N_36600) + ); + defparam com_tlm_u_tlm_rx_data_snk_malformed_checks_un11_data_credits_o_1_a2_0_a2_1_.INIT = 4'h8; + LUT2_L com_tlm_u_tlm_rx_data_snk_malformed_checks_un11_data_credits_o_1_a2_0_a2_1_ ( + .I0(com_tlm_u_tlm_rx_data_snk_malformed_checks_un1_data_credits_o_s_1_4158), + .I1(com_tlm_u_tlm_rx_data_snk_cur_fulltype[6]), + .LO(com_tlm_u_tlm_rx_data_snk_malformed_checks_N_36599) + ); + defparam com_tlm_u_tlm_rx_data_snk_malformed_checks_un11_data_credits_o_1_a2_0_a2_0_.INIT = 4'h8; + LUT2_L com_tlm_u_tlm_rx_data_snk_malformed_checks_un11_data_credits_o_1_a2_0_a2_0_ ( + .I0(com_tlm_u_tlm_rx_data_snk_malformed_checks_un1_data_credits_o_s_0_4159), + .I1(com_tlm_u_tlm_rx_data_snk_cur_fulltype[6]), + .LO(com_tlm_u_tlm_rx_data_snk_malformed_checks_N_36598) + ); + defparam com_tlm_u_tlm_rx_data_snk_malformed_checks_un11_data_credits_o_1_a2_0_a2_5_.INIT = 4'h8; + LUT2_L com_tlm_u_tlm_rx_data_snk_malformed_checks_un11_data_credits_o_1_a2_0_a2_5_ ( + .I0(com_tlm_u_tlm_rx_data_snk_malformed_checks_un1_data_credits_o_s_5_4160), + .I1(com_tlm_u_tlm_rx_data_snk_cur_fulltype[6]), + .LO(com_tlm_u_tlm_rx_data_snk_malformed_checks_N_36603) + ); + defparam com_tlm_u_tlm_rx_data_snk_malformed_checks_un11_data_credits_o_1_a2_0_a2_4_.INIT = 4'h8; + LUT2_L com_tlm_u_tlm_rx_data_snk_malformed_checks_un11_data_credits_o_1_a2_0_a2_4_ ( + .I0(com_tlm_u_tlm_rx_data_snk_malformed_checks_un1_data_credits_o_s_4_4161), + .I1(com_tlm_u_tlm_rx_data_snk_cur_fulltype[6]), + .LO(com_tlm_u_tlm_rx_data_snk_malformed_checks_N_36602) + ); + defparam com_tlm_u_tlm_rx_data_snk_malformed_checks_N_50795_i.INIT = 4'hE; + LUT2_L com_tlm_u_tlm_rx_data_snk_malformed_checks_N_50795_i ( + .I0(com_tlm_u_tlm_rx_data_snk_malformed_checks_malformed_fmt_4164), + .I1(com_tlm_u_tlm_rx_data_snk_malformed_checks_malformed_len_4163), + .LO(com_tlm_u_tlm_rx_data_snk_malformed_checks_N_50795_i_4162) + ); + defparam com_tlm_u_tlm_rx_data_snk_malformed_checks_N_36604_i.INIT = 16'hFFFE; + LUT4_L com_tlm_u_tlm_rx_data_snk_malformed_checks_N_36604_i ( + .I0(com_tlm_u_tlm_rx_data_snk_malformed_checks_malformed_eof_4168), + .I1(com_tlm_u_tlm_rx_data_snk_malformed_checks_malformed_min_4167), + .I2(com_tlm_u_tlm_rx_data_snk_malformed_checks_malformed_over_4190), + .I3(com_tlm_u_tlm_rx_data_snk_malformed_checks_malformed_rem_4166), + .LO(com_tlm_u_tlm_rx_data_snk_malformed_checks_N_36604_i_4165) + ); + defparam com_tlm_u_tlm_rx_data_snk_malformed_checks_msgcode_vendef12_0_a2_0_a2.INIT = 16'h0800; + LUT4_L com_tlm_u_tlm_rx_data_snk_malformed_checks_msgcode_vendef12_0_a2_0_a2 ( + .I0(com_lnk_rd[3]), + .I1(com_lnk_rd[5]), + .I2(com_lnk_rd_5077[7]), + .I3(com_tlm_u_tlm_rx_data_snk_malformed_checks_msgcode_vendef12_0_a2_0_a2_1), + .LO(com_tlm_u_tlm_rx_data_snk_malformed_checks_msgcode_vendef12) + ); + defparam com_tlm_u_tlm_rx_data_snk_malformed_checks_is_usr_leg_ap_3_0_a2_0_a2_0_a2_0_a2.INIT = 16'h8000; + LUT4_L com_tlm_u_tlm_rx_data_snk_malformed_checks_is_usr_leg_ap_3_0_a2_0_a2_0_a2_0_a2 ( + .I0(cfg_cfg_5072[502]), + .I1(com_lnk_rd_5077[38]), + .I2(com_lnk_rd_5077[39]), + .I3(com_tlm_u_tlm_rx_data_snk_malformed_checks_is_usr_leg_ap_3_0_a2_0_a2_0_a2_0_a2_2_4169), + .LO(com_tlm_u_tlm_rx_data_snk_malformed_checks_is_usr_leg_ap_3) + ); + defparam com_tlm_u_tlm_rx_data_snk_malformed_checks_length_1dw_3_0_a2_0_a2.INIT = 16'h0080; + LUT4_L com_tlm_u_tlm_rx_data_snk_malformed_checks_length_1dw_3_0_a2_0_a2 ( + .I0(com_tlm_u_tlm_rx_data_snk_malformed_checks_N_36455_1), + .I1(com_tlm_u_tlm_rx_data_snk_malformed_checks_N_36455_2), + .I2(com_tlm_u_tlm_rx_data_snk_cur_length_0__2), + .I3(com_tlm_u_tlm_rx_data_snk_cur_length_1__4), + .LO(com_tlm_u_tlm_rx_data_snk_malformed_checks_length_1dw_3) + ); + defparam com_tlm_u_tlm_rx_data_snk_malformed_checks_N_68320_i.INIT = 8'h1C; + LUT3_L com_tlm_u_tlm_rx_data_snk_malformed_checks_N_68320_i ( + .I0(com_lnk_rd_5077[56]), + .I1(com_lnk_rd_5077[57]), + .I2(com_lnk_rd_5077[58]), + .LO(com_tlm_u_tlm_rx_data_snk_malformed_checks_N_68320_i_4198) + ); + defparam com_tlm_u_tlm_rx_data_snk_malformed_checks_is_usr_ext_ap_3_i_0_0_0.INIT = 8'hA8; + LUT3_L com_tlm_u_tlm_rx_data_snk_malformed_checks_is_usr_ext_ap_3_i_0_0_0 ( + .I0(cfg_cfg_5072[503]), + .I1(com_lnk_rd_5077[42]), + .I2(com_lnk_rd_5077[43]), + .LO(com_tlm_u_tlm_rx_data_snk_malformed_checks_N_21383_i) + ); + defparam com_tlm_u_tlm_rx_data_snk_malformed_checks_N_50796_i.INIT = 16'hCCCE; + LUT4_L com_tlm_u_tlm_rx_data_snk_malformed_checks_N_50796_i ( + .I0(com_tlm_u_tlm_rx_data_snk_malformed_checks_cfg0_ip_4174), + .I1(com_tlm_u_tlm_rx_data_snk_malformed_checks_cfg1_ip_4173), + .I2(com_tlm_u_tlm_rx_data_snk_malformed_checks_is_usr_ext_ap_4172), + .I3(com_tlm_u_tlm_rx_data_snk_malformed_checks_is_usr_leg_ap_4171), + .LO(com_tlm_u_tlm_rx_data_snk_malformed_checks_N_50796_i_4170) + ); + defparam com_tlm_u_tlm_rx_data_snk_malformed_checks_N_68230_i.INIT = 16'hFFFD; + LUT4_L com_tlm_u_tlm_rx_data_snk_malformed_checks_N_68230_i ( + .I0(com_tlm_u_tlm_rx_data_snk_malformed_checks_malformed_fmt_3_i_0_2_4179), + .I1(com_tlm_u_tlm_rx_data_snk_malformed_checks_malformed_fulltype_4178), + .I2(com_tlm_u_tlm_rx_data_snk_malformed_checks_malformed_maxsize_4177), + .I3(com_tlm_u_tlm_rx_data_snk_malformed_checks_malformed_tc_4176), + .LO(com_tlm_u_tlm_rx_data_snk_malformed_checks_N_68230_i_4175) + ); + defparam com_tlm_u_tlm_rx_data_snk_malformed_checks_uc_pwr_mgmt_7_0_a2_0_a2_0_a2.INIT = 8'h20; + LUT3_L com_tlm_u_tlm_rx_data_snk_malformed_checks_uc_pwr_mgmt_7_0_a2_0_a2_0_a2 ( + .I0(com_tlm_u_tlm_rx_data_snk_malformed_checks_cur_fulltype[1]), + .I1(com_tlm_u_tlm_rx_data_snk_malformed_checks_cur_fulltype[4]), + .I2(com_tlm_u_tlm_rx_data_snk_malformed_checks_uc_pwr_mgmt_7_0_a2_0_a2_0_a2_1_4180), + .LO(com_tlm_u_tlm_rx_data_snk_malformed_checks_uc_pwr_mgmt_7) + ); + defparam com_tlm_u_tlm_rx_data_snk_malformed_checks_malformed_rem_3.INIT = 16'h6996; + LUT4_L com_tlm_u_tlm_rx_data_snk_malformed_checks_malformed_rem_3 ( + .I0(com_tlm_u_tlm_rx_data_snk_malformed_checks_N_36402_i), + .I1(com_lnk_rrem[0]), + .I2(com_tlm_u_tlm_rx_data_snk_cur_td_4080), + .I3(com_tlm_u_tlm_rx_data_snk_malformed_checks_fulltype_in_5__4196), + .LO(com_tlm_u_tlm_rx_data_snk_malformed_checks_malformed_rem_3_4181) + ); + defparam com_tlm_u_tlm_rx_data_snk_malformed_checks_N_68324_i.INIT = 16'h3230; + LUT4_L com_tlm_u_tlm_rx_data_snk_malformed_checks_N_68324_i ( + .I0(com_tlm_u_tlm_rx_data_snk_cur_fulltype_oh_1_), + .I1(com_tlm_u_tlm_rx_data_snk_cur_tc0_4082), + .I2(com_tlm_u_tlm_rx_data_snk_malformed_checks_fulltype_tc0_4201), + .I3(com_tlm_u_tlm_rx_data_snk_malformed_checks_msgcode_sigdef_4204), + .LO(com_tlm_u_tlm_rx_data_snk_malformed_checks_N_68324_i_4182) + ); + defparam com_tlm_u_tlm_rx_data_snk_malformed_checks_N_68107_i.INIT = 16'h90FF; + LUT4_L com_tlm_u_tlm_rx_data_snk_malformed_checks_N_68107_i ( + .I0(com_lnk_rd_5077[56]), + .I1(com_lnk_rd_5077[59]), + .I2(com_tlm_u_tlm_rx_data_snk_cur_fulltype_oh40_1), + .I3(com_tlm_u_tlm_rx_data_snk_malformed_checks_fulltype_tc012_i_0_0_4183), + .LO(com_tlm_u_tlm_rx_data_snk_malformed_checks_N_68107_i_4200) + ); + defparam com_tlm_u_tlm_rx_data_snk_malformed_checks_msgcode_hotplug12_0_0.INIT = 16'h8000; + LUT4_L com_tlm_u_tlm_rx_data_snk_malformed_checks_msgcode_hotplug12_0_0 ( + .I0(N_36400_i), + .I1(N_36431_i), + .I2(com_tlm_u_tlm_rx_data_snk_N_36443_i), + .I3(com_lnk_rd[6]), + .LO(com_tlm_u_tlm_rx_data_snk_malformed_checks_N_9491_i) + ); + defparam com_tlm_u_tlm_rx_data_snk_malformed_checks_N_67836_i.INIT = 16'hD5FF; + LUT4_L com_tlm_u_tlm_rx_data_snk_malformed_checks_N_67836_i ( + .I0(com_tlm_u_tlm_rx_data_snk_malformed_checks_malformed_fulltype16_0_0_0_32147_4186), + .I1(com_tlm_u_tlm_rx_data_snk_malformed_checks_cur_fulltype[1]), + .I2(com_tlm_u_tlm_rx_data_snk_malformed_checks_cfg1_ip_0_sqmuxa_1), + .I3(com_tlm_u_tlm_rx_data_snk_malformed_checks_malformed_fulltype16_0_0_0_0_4185), + .LO(com_tlm_u_tlm_rx_data_snk_malformed_checks_N_67836_i_4184) + ); + defparam com_tlm_u_tlm_rx_data_snk_malformed_checks_msgd_check_64_msgcode_dmatch_4_0_x2_0_x3.INIT = 16'hC60A; + LUT4_L com_tlm_u_tlm_rx_data_snk_malformed_checks_msgd_check_64_msgcode_dmatch_4_0_x2_0_x3 ( + .I0(com_tlm_u_tlm_rx_data_snk_malformed_checks_N_36385_i), + .I1(com_tlm_u_tlm_rx_data_snk_malformed_checks_N_36392_i), + .I2(com_lnk_rd_5077[62]), + .I3(com_tlm_u_tlm_rx_data_snk_malformed_checks_msgcode_dmatch_4_0_x2_0_o3_0_1), + .LO(com_tlm_u_tlm_rx_data_snk_malformed_checks_N_36442_i_0) + ); + defparam com_tlm_u_tlm_rx_data_snk_malformed_checks_msgcode_sigdef16_0_0.INIT = 16'h4C00; + LUT4_L com_tlm_u_tlm_rx_data_snk_malformed_checks_msgcode_sigdef16_0_0 ( + .I0(com_tlm_u_tlm_rx_data_snk_N_36447), + .I1(com_tlm_u_tlm_rx_data_snk_malformed_checks_msgcode_sigdef16_0_0_32156_4188), + .I2(com_lnk_rd[4]), + .I3(com_tlm_u_tlm_rx_data_snk_malformed_checks_msgcode_sigdef16_0_0_0_4187), + .LO(com_tlm_u_tlm_rx_data_snk_malformed_checks_N_9488_i) + ); + defparam com_tlm_u_tlm_rx_data_snk_malformed_checks_ur_pwr_mgmt_7_i_0_0.INIT = 16'h8A00; + LUT4_L com_tlm_u_tlm_rx_data_snk_malformed_checks_ur_pwr_mgmt_7_i_0_0 ( + .I0(com_tlm_u_tlm_rx_data_snk_N_36397_i), + .I1(com_tlm_u_tlm_rx_data_snk_malformed_checks_N_36412_i), + .I2(com_tlm_u_tlm_rx_data_snk_malformed_checks_cur_fulltype[1]), + .I3(com_tlm_u_tlm_rx_data_snk_malformed_checks_ur_pwr_mgmt_7_i_0_0_0_4189), + .LO(com_tlm_u_tlm_rx_data_snk_malformed_checks_N_11860_i) + ); + defparam com_tlm_u_tlm_rx_data_snk_malformed_checks_malformed_over_3_i_0.INIT = 16'h3302; + LUT4_L com_tlm_u_tlm_rx_data_snk_malformed_checks_malformed_over_3_i_0 ( + .I0(com_tlm_u_tlm_rx_data_snk_malformed_checks_N_36439_i), + .I1(com_tlm_u_tlm_rx_data_snk_latch_1st_dword_q1_4028), + .I2(com_tlm_u_tlm_rx_data_snk_malformed_checks_delay_ct_4211), + .I3(com_tlm_u_tlm_rx_data_snk_malformed_checks_malformed_over_4190), + .LO(com_tlm_u_tlm_rx_data_snk_malformed_checks_N_24200_i) + ); + defparam com_tlm_u_tlm_rx_data_snk_malformed_checks_N_69316_i.INIT = 16'hECA0; + LUT4_L com_tlm_u_tlm_rx_data_snk_malformed_checks_N_69316_i ( + .I0(com_tlm_u_tlm_rx_data_snk_malformed_checks_N_36455_1), + .I1(com_tlm_u_tlm_rx_data_snk_cur_fulltype[6]), + .I2(com_tlm_u_tlm_rx_data_snk_malformed_checks_malformed_maxsize_3_0_0_a2_0_1_4193), + .I3(com_tlm_u_tlm_rx_data_snk_malformed_checks_un6_malformed_maxsize_cry_9_4192), + .LO(com_tlm_u_tlm_rx_data_snk_malformed_checks_N_69316_i_4191) + ); + defparam com_tlm_u_tlm_rx_data_snk_malformed_checks_N_9208_i_0_0_0.INIT = 8'h80; + LUT3_L com_tlm_u_tlm_rx_data_snk_malformed_checks_N_9208_i_0_0_0 ( + .I0(com_tlm_u_tlm_rx_data_snk_N_36411_i), + .I1(com_tlm_u_tlm_rx_data_snk_malformed_checks_N_9208_i_0_0_0_32079_4194), + .I2(com_tlm_u_tlm_rx_data_snk_sof_q_1__4097), + .LO(com_tlm_u_tlm_rx_data_snk_malformed_checks_N_9208_i_i) + ); + defparam com_tlm_u_tlm_rx_data_snk_malformed_checks_word_ct_d_1_0_6_.INIT = 16'h707F; + LUT4_L com_tlm_u_tlm_rx_data_snk_malformed_checks_word_ct_d_1_0_6_ ( + .I0(com_tlm_u_tlm_rx_data_snk_cur_fulltype[6]), + .I1(com_tlm_u_tlm_rx_data_snk_cur_length[7]), + .I2(com_tlm_u_tlm_rx_data_snk_latch_1st_dword_q1_4028), + .I3(com_tlm_u_tlm_rx_data_snk_malformed_checks_word_ct[6]), + .LO(com_tlm_u_tlm_rx_data_snk_malformed_checks_word_ct_d_i[6]) + ); + defparam com_tlm_u_tlm_rx_data_snk_malformed_checks_word_ct_d_1_0_5_.INIT = 16'h707F; + LUT4_L com_tlm_u_tlm_rx_data_snk_malformed_checks_word_ct_d_1_0_5_ ( + .I0(com_tlm_u_tlm_rx_data_snk_cur_fulltype[6]), + .I1(com_tlm_u_tlm_rx_data_snk_cur_length[6]), + .I2(com_tlm_u_tlm_rx_data_snk_latch_1st_dword_q1_4028), + .I3(com_tlm_u_tlm_rx_data_snk_malformed_checks_word_ct[5]), + .LO(com_tlm_u_tlm_rx_data_snk_malformed_checks_word_ct_d_i[5]) + ); + defparam com_tlm_u_tlm_rx_data_snk_malformed_checks_word_ct_d_1_0_4_.INIT = 16'h707F; + LUT4_L com_tlm_u_tlm_rx_data_snk_malformed_checks_word_ct_d_1_0_4_ ( + .I0(com_tlm_u_tlm_rx_data_snk_cur_fulltype[6]), + .I1(com_tlm_u_tlm_rx_data_snk_cur_length[5]), + .I2(com_tlm_u_tlm_rx_data_snk_latch_1st_dword_q1_4028), + .I3(com_tlm_u_tlm_rx_data_snk_malformed_checks_word_ct[4]), + .LO(com_tlm_u_tlm_rx_data_snk_malformed_checks_word_ct_d_i[4]) + ); + defparam com_tlm_u_tlm_rx_data_snk_malformed_checks_word_ct_d_1_0_3_.INIT = 16'h707F; + LUT4_L com_tlm_u_tlm_rx_data_snk_malformed_checks_word_ct_d_1_0_3_ ( + .I0(com_tlm_u_tlm_rx_data_snk_cur_fulltype[6]), + .I1(com_tlm_u_tlm_rx_data_snk_cur_length_4__10), + .I2(com_tlm_u_tlm_rx_data_snk_latch_1st_dword_q1_4028), + .I3(com_tlm_u_tlm_rx_data_snk_malformed_checks_word_ct[3]), + .LO(com_tlm_u_tlm_rx_data_snk_malformed_checks_word_ct_d_i[3]) + ); + defparam com_tlm_u_tlm_rx_data_snk_malformed_checks_word_ct_d_1_0_2_.INIT = 16'h707F; + LUT4_L com_tlm_u_tlm_rx_data_snk_malformed_checks_word_ct_d_1_0_2_ ( + .I0(com_tlm_u_tlm_rx_data_snk_cur_fulltype[6]), + .I1(com_tlm_u_tlm_rx_data_snk_cur_length_3__8), + .I2(com_tlm_u_tlm_rx_data_snk_latch_1st_dword_q1_4028), + .I3(com_tlm_u_tlm_rx_data_snk_malformed_checks_word_ct[2]), + .LO(com_tlm_u_tlm_rx_data_snk_malformed_checks_word_ct_d_i[2]) + ); + defparam com_tlm_u_tlm_rx_data_snk_malformed_checks_word_ct_d_1_0_1_.INIT = 16'h707F; + LUT4_L com_tlm_u_tlm_rx_data_snk_malformed_checks_word_ct_d_1_0_1_ ( + .I0(com_tlm_u_tlm_rx_data_snk_cur_fulltype[6]), + .I1(com_tlm_u_tlm_rx_data_snk_cur_length_2__6), + .I2(com_tlm_u_tlm_rx_data_snk_latch_1st_dword_q1_4028), + .I3(com_tlm_u_tlm_rx_data_snk_malformed_checks_word_ct[1]), + .LO(com_tlm_u_tlm_rx_data_snk_malformed_checks_word_ct_d_i[1]) + ); + defparam com_tlm_u_tlm_rx_data_snk_malformed_checks_check_int_msgcode_routing18_0_0.INIT = 8'h02; + LUT3_L com_tlm_u_tlm_rx_data_snk_malformed_checks_check_int_msgcode_routing18_0_0 ( + .I0(com_tlm_u_tlm_rx_data_snk_malformed_checks_N_9487_i_1), + .I1(com_tlm_u_tlm_rx_data_snk_malformed_checks_N_36436), + .I2(com_lnk_rd[1]), + .LO(com_tlm_u_tlm_rx_data_snk_malformed_checks_msgcode_routing18_i_i) + ); + defparam com_tlm_u_tlm_rx_data_snk_malformed_checks_check_int_un1_msgcode_routing19_0_0.INIT = 16'h88A0; + LUT4_L com_tlm_u_tlm_rx_data_snk_malformed_checks_check_int_un1_msgcode_routing19_0_0 ( + .I0(com_tlm_u_tlm_rx_data_snk_malformed_checks_N_9487_i_1), + .I1(N_36389_i), + .I2(com_tlm_u_tlm_rx_data_snk_malformed_checks_N_36392_i), + .I3(com_lnk_rd[4]), + .LO(com_tlm_u_tlm_rx_data_snk_malformed_checks_N_9487_i) + ); + defparam com_tlm_u_tlm_rx_data_snk_malformed_checks_un1_fulltype_i_3_0_a2_0_a2.INIT = 16'h0080; + LUT4_L com_tlm_u_tlm_rx_data_snk_malformed_checks_un1_fulltype_i_3_0_a2_0_a2 ( + .I0(com_tlm_u_tlm_rx_data_snk_N_36393_i), + .I1(com_tlm_u_tlm_rx_data_snk_N_36409_i), + .I2(com_lnk_rd_5077[57]), + .I3(com_lnk_rd_5077[59]), + .LO(com_tlm_u_tlm_rx_data_snk_cur_fulltype_oh37) + ); + defparam com_tlm_u_tlm_rx_data_snk_malformed_checks_malformed_eof_3_i_0_1.INIT = 16'h0002; + LUT4 com_tlm_u_tlm_rx_data_snk_malformed_checks_malformed_eof_3_i_0_1 ( + .I0(com_tlm_u_tlm_rx_data_snk_malformed_checks_malformed_eof_3_i_0_a2_0_4_4195), + .I1(com_tlm_u_tlm_rx_data_snk_malformed_checks_word_ct[2]), + .I2(com_tlm_u_tlm_rx_data_snk_malformed_checks_word_ct[3]), + .I3(com_tlm_u_tlm_rx_data_snk_malformed_checks_word_ct[6]), + .O(com_tlm_u_tlm_rx_data_snk_malformed_checks_malformed_eof_3_i_0_1_4210) + ); + defparam com_tlm_u_tlm_rx_data_snk_malformed_checks_N_67910_i_1.INIT = 16'h7BFF; + LUT4 com_tlm_u_tlm_rx_data_snk_malformed_checks_N_67910_i_1 ( + .I0(com_tlm_u_tlm_rx_data_snk_malformed_checks_fulltype_in_0__4197), + .I1(com_tlm_u_tlm_rx_data_snk_malformed_checks_msgcode_dmatch_4203), + .I2(com_tlm_u_tlm_rx_data_snk_malformed_checks_msgcode_routing[0]), + .I3(com_tlm_u_tlm_rx_data_snk_malformed_checks_msgcode_sigdef_4204), + .O(com_tlm_u_tlm_rx_data_snk_malformed_checks_N_67910_i_1_4209) + ); + defparam com_tlm_u_tlm_rx_data_snk_malformed_checks_cfg1_ip_0_sqmuxa_0_a2_0_a2_0_a2_1.INIT = 8'h02; + LUT3 com_tlm_u_tlm_rx_data_snk_malformed_checks_cfg1_ip_0_sqmuxa_0_a2_0_a2_0_a2_1 ( + .I0(com_tlm_u_tlm_rx_data_snk_malformed_checks_fulltype_in_0__4197), + .I1(com_tlm_u_tlm_rx_data_snk_malformed_checks_cur_fulltype[4]), + .I2(com_tlm_u_tlm_rx_data_snk_malformed_checks_cur_fulltype[3]), + .O(com_tlm_u_tlm_rx_data_snk_malformed_checks_cfg1_ip_0_sqmuxa_1) + ); + defparam com_tlm_u_tlm_rx_data_snk_malformed_checks_msgcode_hotplug12_0_0_o2.INIT = 8'h15; + LUT3 com_tlm_u_tlm_rx_data_snk_malformed_checks_msgcode_hotplug12_0_0_o2 ( + .I0(com_tlm_u_tlm_rx_data_snk_N_36447), + .I1(com_lnk_rd[3]), + .I2(com_lnk_rd[0]), + .O(N_36400_i) + ); + FDE com_tlm_u_tlm_rx_data_snk_malformed_checks_data_credits_o_3_ ( + .CE(com_tlm_u_tlm_rx_data_snk_latch_3rd_dword_q1), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_malformed_checks_N_36601), + .Q(com_tlm_u_tlm_rx_data_snk_cur_data_credits[3]) + ); + FDE com_tlm_u_tlm_rx_data_snk_malformed_checks_data_credits_o_2_ ( + .CE(com_tlm_u_tlm_rx_data_snk_latch_3rd_dword_q1), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_malformed_checks_N_36600), + .Q(com_tlm_u_tlm_rx_data_snk_cur_data_credits[2]) + ); + FDE com_tlm_u_tlm_rx_data_snk_malformed_checks_data_credits_o_1_ ( + .CE(com_tlm_u_tlm_rx_data_snk_latch_3rd_dword_q1), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_malformed_checks_N_36599), + .Q(com_tlm_u_tlm_rx_data_snk_cur_data_credits[1]) + ); + FDE com_tlm_u_tlm_rx_data_snk_malformed_checks_data_credits_o_0_ ( + .CE(com_tlm_u_tlm_rx_data_snk_latch_3rd_dword_q1), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_malformed_checks_N_36598), + .Q(com_tlm_u_tlm_rx_data_snk_cur_data_credits[0]) + ); + FDE com_tlm_u_tlm_rx_data_snk_malformed_checks_data_credits_o_5_ ( + .CE(com_tlm_u_tlm_rx_data_snk_latch_3rd_dword_q1), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_malformed_checks_N_36603), + .Q(com_tlm_u_tlm_rx_data_snk_cur_data_credits[5]) + ); + FDE com_tlm_u_tlm_rx_data_snk_malformed_checks_data_credits_o_4_ ( + .CE(com_tlm_u_tlm_rx_data_snk_latch_3rd_dword_q1), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_malformed_checks_N_36602), + .Q(com_tlm_u_tlm_rx_data_snk_cur_data_credits[4]) + ); + FDE com_tlm_u_tlm_rx_data_snk_malformed_checks_fulltype_in_6_ ( + .CE(com_tlm_u_tlm_rx_data_snk_latch_2nd_dword), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_lnk_rd_5077[62]), + .Q(com_tlm_u_tlm_rx_data_snk_cur_fulltype[6]) + ); + FDE com_tlm_u_tlm_rx_data_snk_malformed_checks_fulltype_in_5_ ( + .CE(com_tlm_u_tlm_rx_data_snk_latch_2nd_dword), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_lnk_rd_5077[61]), + .Q(com_tlm_u_tlm_rx_data_snk_malformed_checks_fulltype_in_5__4196) + ); + FDE com_tlm_u_tlm_rx_data_snk_malformed_checks_fulltype_in_4_ ( + .CE(com_tlm_u_tlm_rx_data_snk_latch_2nd_dword), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_lnk_rd_5077[60]), + .Q(com_tlm_u_tlm_rx_data_snk_malformed_checks_cur_fulltype[4]) + ); + FDE com_tlm_u_tlm_rx_data_snk_malformed_checks_fulltype_in_3_ ( + .CE(com_tlm_u_tlm_rx_data_snk_latch_2nd_dword), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_lnk_rd_5077[59]), + .Q(com_tlm_u_tlm_rx_data_snk_malformed_checks_cur_fulltype[3]) + ); + FDE com_tlm_u_tlm_rx_data_snk_malformed_checks_fulltype_in_2_ ( + .CE(com_tlm_u_tlm_rx_data_snk_latch_2nd_dword), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_lnk_rd_5077[58]), + .Q(com_tlm_u_tlm_rx_data_snk_malformed_checks_cur_fulltype[2]) + ); + FDE com_tlm_u_tlm_rx_data_snk_malformed_checks_fulltype_in_1_ ( + .CE(com_tlm_u_tlm_rx_data_snk_latch_2nd_dword), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_lnk_rd_5077[57]), + .Q(com_tlm_u_tlm_rx_data_snk_malformed_checks_cur_fulltype[1]) + ); + FDE com_tlm_u_tlm_rx_data_snk_malformed_checks_fulltype_in_0_ ( + .CE(com_tlm_u_tlm_rx_data_snk_latch_2nd_dword), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_lnk_rd_5077[56]), + .Q(com_tlm_u_tlm_rx_data_snk_malformed_checks_fulltype_in_0__4197) + ); + FDE com_tlm_u_tlm_rx_data_snk_malformed_checks_ismsgany ( + .CE(com_tlm_u_tlm_rx_data_snk_latch_2nd_dword), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_malformed_checks_N_36385_i), + .Q(com_tlm_u_tlm_rx_data_snk_cur_fulltype_oh_1_) + ); + FDE com_tlm_u_tlm_rx_data_snk_malformed_checks_msgcode_vendef ( + .CE(com_tlm_u_tlm_rx_data_snk_latch_2nd_dword), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_malformed_checks_msgcode_vendef12), + .Q(com_tlm_u_tlm_rx_data_snk_malformed_checks_msgcode_vendef_4207) + ); + FDE com_tlm_u_tlm_rx_data_snk_malformed_checks_routing_vendef ( + .CE(com_tlm_u_tlm_rx_data_snk_latch_2nd_dword), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_malformed_checks_N_68320_i_4198), + .Q(com_tlm_u_tlm_rx_data_snk_malformed_checks_routing_vendef_4199) + ); + FDE com_tlm_u_tlm_rx_data_snk_malformed_checks_fulltype_tc0 ( + .CE(com_tlm_u_tlm_rx_data_snk_latch_2nd_dword), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_malformed_checks_N_68107_i_4200), + .Q(com_tlm_u_tlm_rx_data_snk_malformed_checks_fulltype_tc0_4201) + ); + FDE com_tlm_u_tlm_rx_data_snk_malformed_checks_msgcode_hotplug ( + .CE(com_tlm_u_tlm_rx_data_snk_latch_2nd_dword), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_malformed_checks_N_9491_i), + .Q(com_tlm_u_tlm_rx_data_snk_malformed_checks_msgcode_hotplug_4202) + ); + FDE com_tlm_u_tlm_rx_data_snk_malformed_checks_msgcode_dmatch ( + .CE(com_tlm_u_tlm_rx_data_snk_latch_2nd_dword), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_malformed_checks_N_36442_i_0), + .Q(com_tlm_u_tlm_rx_data_snk_malformed_checks_msgcode_dmatch_4203) + ); + FDE com_tlm_u_tlm_rx_data_snk_malformed_checks_msgcode_sigdef ( + .CE(com_tlm_u_tlm_rx_data_snk_latch_2nd_dword), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_malformed_checks_N_9488_i), + .Q(com_tlm_u_tlm_rx_data_snk_malformed_checks_msgcode_sigdef_4204) + ); + FDE com_tlm_u_tlm_rx_data_snk_malformed_checks_msgcode_routing_2_ ( + .CE(com_tlm_u_tlm_rx_data_snk_latch_2nd_dword), + .C(NlwRenamedSig_OI_trn_clk), + .D(N_14707_i), + .Q(com_tlm_u_tlm_rx_data_snk_malformed_checks_msgcode_routing[2]) + ); + FDE com_tlm_u_tlm_rx_data_snk_malformed_checks_msgcode_routing_1_ ( + .CE(com_tlm_u_tlm_rx_data_snk_latch_2nd_dword), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_malformed_checks_msgcode_routing18_i_i), + .Q(com_tlm_u_tlm_rx_data_snk_malformed_checks_msgcode_routing[1]) + ); + FDE com_tlm_u_tlm_rx_data_snk_malformed_checks_msgcode_routing_0_ ( + .CE(com_tlm_u_tlm_rx_data_snk_latch_2nd_dword), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_malformed_checks_N_9487_i), + .Q(com_tlm_u_tlm_rx_data_snk_malformed_checks_msgcode_routing[0]) + ); + INV com_tlm_u_tlm_rx_data_snk_malformed_checks_delay_ct_i ( + .I(com_tlm_u_tlm_rx_data_snk_malformed_checks_delay_ct_4211), + .O(com_tlm_u_tlm_rx_data_snk_malformed_checks_delay_ct_i_4205) + ); + defparam com_tlm_u_tlm_rx_data_snk_malformed_checks_N_67910_i.INIT = 16'hAFEF; + LUT4_L com_tlm_u_tlm_rx_data_snk_malformed_checks_N_67910_i ( + .I0(com_tlm_u_tlm_rx_data_snk_malformed_checks_N_36450), + .I1(com_tlm_u_tlm_rx_data_snk_malformed_checks_N_67910_i_1_4209), + .I2(com_tlm_u_tlm_rx_data_snk_malformed_checks_malformed_message_6_0_0_0_1_4208), + .I3(com_tlm_u_tlm_rx_data_snk_malformed_checks_msgcode_vendef_4207), + .LO(com_tlm_u_tlm_rx_data_snk_malformed_checks_N_67910_i_4206) + ); + defparam com_tlm_u_tlm_rx_data_snk_malformed_checks_malformed_eof_3_i_0.INIT = 16'h1013; + LUT4_L com_tlm_u_tlm_rx_data_snk_malformed_checks_malformed_eof_3_i_0 ( + .I0(com_tlm_u_tlm_rx_data_snk_malformed_checks_N_36439_i), + .I1(com_tlm_u_tlm_rx_data_snk_latch_1st_dword_q1_4028), + .I2(com_tlm_u_tlm_rx_data_snk_malformed_checks_delay_ct_4211), + .I3(com_tlm_u_tlm_rx_data_snk_malformed_checks_malformed_eof_3_i_0_1_4210), + .LO(com_tlm_u_tlm_rx_data_snk_malformed_checks_N_24198_i) + ); + defparam com_tlm_u_tlm_rx_data_snk_malformed_checks_un1_data_credits_o_axb_4.INIT = 4'h2; + LUT1 com_tlm_u_tlm_rx_data_snk_malformed_checks_un1_data_credits_o_axb_4 ( + .I0(com_tlm_u_tlm_rx_data_snk_cur_length[6]), + .O(com_tlm_u_tlm_rx_data_snk_malformed_checks_un1_data_credits_o_axb_4_4212) + ); + defparam com_tlm_u_tlm_rx_data_snk_malformed_checks_un1_data_credits_o_axb_3.INIT = 4'h2; + LUT1 com_tlm_u_tlm_rx_data_snk_malformed_checks_un1_data_credits_o_axb_3 ( + .I0(com_tlm_u_tlm_rx_data_snk_cur_length[5]), + .O(com_tlm_u_tlm_rx_data_snk_malformed_checks_un1_data_credits_o_axb_3_4213) + ); + defparam com_tlm_u_tlm_rx_data_snk_malformed_checks_un1_data_credits_o_axb_2.INIT = 4'h2; + LUT1 com_tlm_u_tlm_rx_data_snk_malformed_checks_un1_data_credits_o_axb_2 ( + .I0(com_tlm_u_tlm_rx_data_snk_cur_length_4__10), + .O(com_tlm_u_tlm_rx_data_snk_malformed_checks_un1_data_credits_o_axb_2_4214) + ); + defparam com_tlm_u_tlm_rx_data_snk_malformed_checks_un1_data_credits_o_axb_1.INIT = 4'h2; + LUT1 com_tlm_u_tlm_rx_data_snk_malformed_checks_un1_data_credits_o_axb_1 ( + .I0(com_tlm_u_tlm_rx_data_snk_cur_length_3__8), + .O(com_tlm_u_tlm_rx_data_snk_malformed_checks_un1_data_credits_o_axb_1_4215) + ); + defparam com_tlm_u_tlm_rx_data_snk_malformed_checks_un1_data_credits_o_axb_0.INIT = 4'h2; + LUT1 com_tlm_u_tlm_rx_data_snk_malformed_checks_un1_data_credits_o_axb_0 ( + .I0(com_tlm_u_tlm_rx_data_snk_cur_length_2__6), + .O(com_tlm_u_tlm_rx_data_snk_malformed_checks_un1_data_credits_o_axb_0_4216) + ); + defparam com_tlm_u_tlm_rx_data_snk_malformed_checks_un6_malformed_maxsize_axb_7_i.INIT = 4'h9; + LUT2 com_tlm_u_tlm_rx_data_snk_malformed_checks_un6_malformed_maxsize_axb_7_i ( + .I0(com_tlm_u_tlm_rx_data_snk_cur_length[7]), + .I1(com_tlm_u_tlm_rx_data_snk_malformed_checks_max_length[7]), + .O(com_tlm_u_tlm_rx_data_snk_malformed_checks_un6_malformed_maxsize_axb_7_i_4217) + ); + defparam com_tlm_u_tlm_rx_data_snk_malformed_checks_un6_malformed_maxsize_axb_6_i.INIT = 4'h9; + LUT2 com_tlm_u_tlm_rx_data_snk_malformed_checks_un6_malformed_maxsize_axb_6_i ( + .I0(com_tlm_u_tlm_rx_data_snk_cur_length[6]), + .I1(com_tlm_u_tlm_rx_data_snk_malformed_checks_max_length[6]), + .O(com_tlm_u_tlm_rx_data_snk_malformed_checks_un6_malformed_maxsize_axb_6_i_4218) + ); + defparam com_tlm_u_tlm_rx_data_snk_malformed_checks_un6_malformed_maxsize_axb_5_i.INIT = 4'h9; + LUT2 com_tlm_u_tlm_rx_data_snk_malformed_checks_un6_malformed_maxsize_axb_5_i ( + .I0(com_tlm_u_tlm_rx_data_snk_cur_length[5]), + .I1(com_tlm_u_tlm_rx_data_snk_malformed_checks_max_length[5]), + .O(com_tlm_u_tlm_rx_data_snk_malformed_checks_un6_malformed_maxsize_axb_5_i_4219) + ); + FDRE com_tlm_u_tlm_rx_data_snk_pwr_mgmt_cur_pm_turn_off ( + .CE(com_tlm_u_tlm_rx_data_snk_latch_1st_dword_q1_4028), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_pwr_mgmt_cur_pm_turn_off_6), + .Q(com_tlm_u_tlm_rx_data_snk_pwr_mgmt_cur_pm_turn_off_4227), + .R(plm_link_up_i) + ); + FDRE com_tlm_u_tlm_rx_data_snk_pwr_mgmt_cur_pm_set_slot_pwr ( + .CE(com_tlm_u_tlm_rx_data_snk_latch_1st_dword_q1_4028), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_pwr_mgmt_cur_pm_set_slot_pwr_6), + .Q(com_tlm_u_tlm_rx_data_snk_pwr_mgmt_cur_pm_set_slot_pwr_4225), + .R(plm_link_up_i) + ); + FDRE com_tlm_u_tlm_rx_data_snk_pwr_mgmt_cur_pm_as_nak_l1 ( + .CE(com_tlm_u_tlm_rx_data_snk_latch_1st_dword_q1_4028), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_pwr_mgmt_cur_pm_as_nak_l1_6), + .Q(com_tlm_u_tlm_rx_data_snk_pwr_mgmt_cur_pm_as_nak_l1_4223), + .R(plm_link_up_i) + ); + FDRE com_tlm_u_tlm_rx_data_snk_pwr_mgmt_pm_turn_off_o ( + .CE(com_tlm_u_tlm_rx_data_snk_pwr_mgmt_un1_act_pwr_mgmt_i_1_i_4229), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_pwr_mgmt_pm_turn_off_o_5_4226), + .Q(com_cmmt_rpm_turn_off), + .R(plm_link_up_i) + ); + FDRE com_tlm_u_tlm_rx_data_snk_pwr_mgmt_pm_set_slot_pwr_o ( + .CE(com_tlm_u_tlm_rx_data_snk_pwr_mgmt_un1_act_pwr_mgmt_i_1_i_4229), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_pwr_mgmt_pm_set_slot_pwr_o_5_4224), + .Q(com_cmmt_rpm_set_slot_pwr), + .R(plm_link_up_i) + ); + FDRE com_tlm_u_tlm_rx_data_snk_pwr_mgmt_pm_as_nak_l1_o ( + .CE(com_tlm_u_tlm_rx_data_snk_pwr_mgmt_un1_act_pwr_mgmt_i_1_i_4229), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_pwr_mgmt_pm_as_nak_l1_o_5_4222), + .Q(com_cmmt_rpm_as_nak_l1), + .R(plm_link_up_i) + ); + FDRE com_tlm_u_tlm_rx_data_snk_pwr_mgmt_pm_msg_detect_o ( + .CE(com_tlm_u_tlm_rx_data_snk_latch_1st_dword_q2), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_pwr_mgmt_N_9485_i_4221), + .Q(com_tlm_u_tlm_rx_data_snk_cur_pm_msg_detect), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_rx_data_snk_pwr_mgmt_act_pwr_mgmt_q1 ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_pwr_mgmt_un1_eof_q_2), + .Q(com_tlm_u_tlm_rx_data_snk_pwr_mgmt_act_pwr_mgmt_q1_4230), + .R(plm_link_up_i) + ); + defparam com_tlm_u_tlm_rx_data_snk_pwr_mgmt_cur_pm_as_nak_l1_6_0_a2_0_a2_0_a2_2_1_0.INIT = 4'h1; + LUT2_L com_tlm_u_tlm_rx_data_snk_pwr_mgmt_cur_pm_as_nak_l1_6_0_a2_0_a2_0_a2_2_1_0 ( + .I0(com_tlm_u_tlm_rx_data_snk_cur_msgcode[1]), + .I1(com_tlm_u_tlm_rx_data_snk_cur_msgcode[5]), + .LO(com_tlm_u_tlm_rx_data_snk_pwr_mgmt_cur_pm_as_nak_l1_6_0_a2_0_a2_0_a2_2_1_0_4220) + ); + defparam com_tlm_u_tlm_rx_data_snk_pwr_mgmt_cur_pm_turn_off_6_0_a2_0_a2_0_a2_1.INIT = 4'h1; + LUT2 com_tlm_u_tlm_rx_data_snk_pwr_mgmt_cur_pm_turn_off_6_0_a2_0_a2_0_a2_1 ( + .I0(com_tlm_u_tlm_rx_data_snk_cur_msgcode[2]), + .I1(com_tlm_u_tlm_rx_data_snk_cur_msgcode[6]), + .O(com_tlm_u_tlm_rx_data_snk_pwr_mgmt_cur_pm_turn_off_6_0_a2_0_a2_0_a2_1_4228) + ); + defparam com_tlm_u_tlm_rx_data_snk_pwr_mgmt_act_pwr_mgmt_q1c.INIT = 4'h8; + LUT2 com_tlm_u_tlm_rx_data_snk_pwr_mgmt_act_pwr_mgmt_q1c ( + .I0(com_tlm_u_tlm_rx_data_snk_eof_q_3__4083), + .I1(com_tlm_u_tlm_rx_data_snk_un1_eof_q_2_1_4031), + .O(com_tlm_u_tlm_rx_data_snk_pwr_mgmt_un1_eof_q_2) + ); + defparam com_tlm_u_tlm_rx_data_snk_pwr_mgmt_cur_pm_as_nak_l1_6_0_a2_0_a2_0_a2_2_1.INIT = 16'h0800; + LUT4 com_tlm_u_tlm_rx_data_snk_pwr_mgmt_cur_pm_as_nak_l1_6_0_a2_0_a2_0_a2_2_1 ( + .I0(com_tlm_u_tlm_rx_data_snk_cur_fulltype_oh_1_), + .I1(com_tlm_u_tlm_rx_data_snk_cur_msgcode[4]), + .I2(com_tlm_u_tlm_rx_data_snk_cur_msgcode[7]), + .I3(com_tlm_u_tlm_rx_data_snk_pwr_mgmt_cur_pm_as_nak_l1_6_0_a2_0_a2_0_a2_2_1_0_4220), + .O(com_tlm_u_tlm_rx_data_snk_pwr_mgmt_cur_pm_as_nak_l1_6_2_0_1) + ); + defparam com_tlm_u_tlm_rx_data_snk_pwr_mgmt_cur_pm_set_slot_pwr_6_0_a2_0_a2_0_a2_1.INIT = 8'h10; + LUT3 com_tlm_u_tlm_rx_data_snk_pwr_mgmt_cur_pm_set_slot_pwr_6_0_a2_0_a2_0_a2_1 ( + .I0(com_tlm_u_tlm_rx_data_snk_cur_msgcode[0]), + .I1(com_tlm_u_tlm_rx_data_snk_cur_msgcode[3]), + .I2(com_tlm_u_tlm_rx_data_snk_pwr_mgmt_cur_pm_as_nak_l1_6_2_0_1), + .O(com_tlm_u_tlm_rx_data_snk_pwr_mgmt_cur_pm_set_slot_pwr_6_1) + ); + defparam com_tlm_u_tlm_rx_data_snk_pwr_mgmt_N_9485_i.INIT = 8'hFE; + LUT3_L com_tlm_u_tlm_rx_data_snk_pwr_mgmt_N_9485_i ( + .I0(com_tlm_u_tlm_rx_data_snk_pwr_mgmt_cur_pm_as_nak_l1_4223), + .I1(com_tlm_u_tlm_rx_data_snk_pwr_mgmt_cur_pm_set_slot_pwr_4225), + .I2(com_tlm_u_tlm_rx_data_snk_pwr_mgmt_cur_pm_turn_off_4227), + .LO(com_tlm_u_tlm_rx_data_snk_pwr_mgmt_N_9485_i_4221) + ); + defparam com_tlm_u_tlm_rx_data_snk_pwr_mgmt_pm_as_nak_l1_o_5.INIT = 4'h8; + LUT2_L com_tlm_u_tlm_rx_data_snk_pwr_mgmt_pm_as_nak_l1_o_5 ( + .I0(com_tlm_u_tlm_rx_data_snk_pwr_mgmt_cur_pm_as_nak_l1_4223), + .I1(com_tlm_u_tlm_rx_data_snk_pwr_mgmt_un1_eof_q_2), + .LO(com_tlm_u_tlm_rx_data_snk_pwr_mgmt_pm_as_nak_l1_o_5_4222) + ); + defparam com_tlm_u_tlm_rx_data_snk_pwr_mgmt_pm_set_slot_pwr_o_5.INIT = 4'h8; + LUT2_L com_tlm_u_tlm_rx_data_snk_pwr_mgmt_pm_set_slot_pwr_o_5 ( + .I0(com_tlm_u_tlm_rx_data_snk_pwr_mgmt_cur_pm_set_slot_pwr_4225), + .I1(com_tlm_u_tlm_rx_data_snk_pwr_mgmt_un1_eof_q_2), + .LO(com_tlm_u_tlm_rx_data_snk_pwr_mgmt_pm_set_slot_pwr_o_5_4224) + ); + defparam com_tlm_u_tlm_rx_data_snk_pwr_mgmt_pm_turn_off_o_5.INIT = 4'h8; + LUT2_L com_tlm_u_tlm_rx_data_snk_pwr_mgmt_pm_turn_off_o_5 ( + .I0(com_tlm_u_tlm_rx_data_snk_pwr_mgmt_cur_pm_turn_off_4227), + .I1(com_tlm_u_tlm_rx_data_snk_pwr_mgmt_un1_eof_q_2), + .LO(com_tlm_u_tlm_rx_data_snk_pwr_mgmt_pm_turn_off_o_5_4226) + ); + defparam com_tlm_u_tlm_rx_data_snk_pwr_mgmt_cur_pm_as_nak_l1_6_0_a2_0_a2_0_a2.INIT = 8'h20; + LUT3_L com_tlm_u_tlm_rx_data_snk_pwr_mgmt_cur_pm_as_nak_l1_6_0_a2_0_a2_0_a2 ( + .I0(com_tlm_u_tlm_rx_data_snk_cur_msgcode[2]), + .I1(com_tlm_u_tlm_rx_data_snk_cur_msgcode[6]), + .I2(com_tlm_u_tlm_rx_data_snk_pwr_mgmt_cur_pm_set_slot_pwr_6_1), + .LO(com_tlm_u_tlm_rx_data_snk_pwr_mgmt_cur_pm_as_nak_l1_6) + ); + defparam com_tlm_u_tlm_rx_data_snk_pwr_mgmt_cur_pm_set_slot_pwr_6_0_a2_0_a2_0_a2.INIT = 8'h40; + LUT3_L com_tlm_u_tlm_rx_data_snk_pwr_mgmt_cur_pm_set_slot_pwr_6_0_a2_0_a2_0_a2 ( + .I0(com_tlm_u_tlm_rx_data_snk_cur_msgcode[2]), + .I1(com_tlm_u_tlm_rx_data_snk_cur_msgcode[6]), + .I2(com_tlm_u_tlm_rx_data_snk_pwr_mgmt_cur_pm_set_slot_pwr_6_1), + .LO(com_tlm_u_tlm_rx_data_snk_pwr_mgmt_cur_pm_set_slot_pwr_6) + ); + defparam com_tlm_u_tlm_rx_data_snk_pwr_mgmt_cur_pm_turn_off_6_0_a2_0_a2_0_a2.INIT = 16'h8000; + LUT4_L com_tlm_u_tlm_rx_data_snk_pwr_mgmt_cur_pm_turn_off_6_0_a2_0_a2_0_a2 ( + .I0(com_tlm_u_tlm_rx_data_snk_cur_msgcode[0]), + .I1(com_tlm_u_tlm_rx_data_snk_cur_msgcode[3]), + .I2(com_tlm_u_tlm_rx_data_snk_pwr_mgmt_cur_pm_as_nak_l1_6_2_0_1), + .I3(com_tlm_u_tlm_rx_data_snk_pwr_mgmt_cur_pm_turn_off_6_0_a2_0_a2_0_a2_1_4228), + .LO(com_tlm_u_tlm_rx_data_snk_pwr_mgmt_cur_pm_turn_off_6) + ); + defparam com_tlm_u_tlm_rx_data_snk_pwr_mgmt_un1_act_pwr_mgmt_i_1_i.INIT = 8'hEA; + LUT3 com_tlm_u_tlm_rx_data_snk_pwr_mgmt_un1_act_pwr_mgmt_i_1_i ( + .I0(com_tlm_u_tlm_rx_data_snk_pwr_mgmt_act_pwr_mgmt_q1_4230), + .I1(com_tlm_u_tlm_rx_data_snk_un1_eof_q_2_1_4031), + .I2(com_tlm_u_tlm_rx_data_snk_eof_q_3__4083), + .O(com_tlm_u_tlm_rx_data_snk_pwr_mgmt_un1_act_pwr_mgmt_i_1_i_4229) + ); + FDE com_tlm_u_tlm_rx_data_snk_pwr_mgmt_pm_set_slot_pwr_data_o_9_ ( + .CE(com_tlm_u_tlm_rx_data_snk_latch_3rd_dword_q1), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_lnk_rd_5077[41]), + .Q(com_cmmt_rpm_set_slot_pwr_data[9]) + ); + FDE com_tlm_u_tlm_rx_data_snk_pwr_mgmt_pm_set_slot_pwr_data_o_8_ ( + .CE(com_tlm_u_tlm_rx_data_snk_latch_3rd_dword_q1), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_lnk_rd_5077[40]), + .Q(com_cmmt_rpm_set_slot_pwr_data[8]) + ); + FDE com_tlm_u_tlm_rx_data_snk_pwr_mgmt_pm_set_slot_pwr_data_o_7_ ( + .CE(com_tlm_u_tlm_rx_data_snk_latch_3rd_dword_q1), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_lnk_rd_5077[39]), + .Q(com_cmmt_rpm_set_slot_pwr_data[7]) + ); + FDE com_tlm_u_tlm_rx_data_snk_pwr_mgmt_pm_set_slot_pwr_data_o_6_ ( + .CE(com_tlm_u_tlm_rx_data_snk_latch_3rd_dword_q1), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_lnk_rd_5077[38]), + .Q(com_cmmt_rpm_set_slot_pwr_data[6]) + ); + FDE com_tlm_u_tlm_rx_data_snk_pwr_mgmt_pm_set_slot_pwr_data_o_5_ ( + .CE(com_tlm_u_tlm_rx_data_snk_latch_3rd_dword_q1), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_lnk_rd_5077[37]), + .Q(com_cmmt_rpm_set_slot_pwr_data[5]) + ); + FDE com_tlm_u_tlm_rx_data_snk_pwr_mgmt_pm_set_slot_pwr_data_o_4_ ( + .CE(com_tlm_u_tlm_rx_data_snk_latch_3rd_dword_q1), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_lnk_rd_5077[36]), + .Q(com_cmmt_rpm_set_slot_pwr_data[4]) + ); + FDE com_tlm_u_tlm_rx_data_snk_pwr_mgmt_pm_set_slot_pwr_data_o_3_ ( + .CE(com_tlm_u_tlm_rx_data_snk_latch_3rd_dword_q1), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_lnk_rd_5077[35]), + .Q(com_cmmt_rpm_set_slot_pwr_data[3]) + ); + FDE com_tlm_u_tlm_rx_data_snk_pwr_mgmt_pm_set_slot_pwr_data_o_2_ ( + .CE(com_tlm_u_tlm_rx_data_snk_latch_3rd_dword_q1), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_lnk_rd_5077[34]), + .Q(com_cmmt_rpm_set_slot_pwr_data[2]) + ); + FDE com_tlm_u_tlm_rx_data_snk_pwr_mgmt_pm_set_slot_pwr_data_o_1_ ( + .CE(com_tlm_u_tlm_rx_data_snk_latch_3rd_dword_q1), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_lnk_rd_5077[33]), + .Q(com_cmmt_rpm_set_slot_pwr_data[1]) + ); + FDE com_tlm_u_tlm_rx_data_snk_pwr_mgmt_pm_set_slot_pwr_data_o_0_ ( + .CE(com_tlm_u_tlm_rx_data_snk_latch_3rd_dword_q1), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_lnk_rd_5077[32]), + .Q(com_cmmt_rpm_set_slot_pwr_data[0]) + ); + FDR com_tlm_u_tlm_rx_data_snk_bar_hit_check_rmem32_o ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_bar_hit_check_rmem32_o_5), + .Q(com_cmmt_mem32), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_rx_data_snk_bar_hit_check_rmem64_o ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_bar_hit_check_rmem64_o_5), + .Q(com_cmmt_mem64), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_rx_data_snk_bar_hit_check_rio_o ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_bar_hit_check_rio_o_5), + .Q(com_cmmt_rio), + .R(plm_link_up_i) + ); + defparam com_tlm_u_tlm_rx_data_snk_bar_hit_check_raddr_d_i_0_o3_55_.INIT = 4'h1; + LUT2 com_tlm_u_tlm_rx_data_snk_bar_hit_check_raddr_d_i_0_o3_55_ ( + .I0(com_tlm_u_tlm_rx_data_snk_cur_fulltype_oh_0__4094), + .I1(com_tlm_u_tlm_rx_data_snk_cur_fulltype_oh_7__4090), + .O(com_tlm_u_tlm_rx_data_snk_bar_hit_check_raddr_d_i_0_o3[55]) + ); + defparam com_tlm_u_tlm_rx_data_snk_bar_hit_check_rio_o_5_0_a2_0_a2_0_a2.INIT = 4'h8; + LUT2_L com_tlm_u_tlm_rx_data_snk_bar_hit_check_rio_o_5_0_a2_0_a2_0_a2 ( + .I0(com_tlm_u_tlm_rx_data_snk_cur_fulltype_oh_3__4093), + .I1(com_tlm_u_tlm_rx_data_snk_sof_q_1__4097), + .LO(com_tlm_u_tlm_rx_data_snk_bar_hit_check_rio_o_5) + ); + defparam com_tlm_u_tlm_rx_data_snk_bar_hit_check_rmem64_o_5_0_a3_0_a2_0_a2.INIT = 8'h80; + LUT3_L com_tlm_u_tlm_rx_data_snk_bar_hit_check_rmem64_o_5_0_a3_0_a2_0_a2 ( + .I0(com_tlm_u_tlm_rx_data_snk_cur_fulltype_64_4088), + .I1(com_tlm_u_tlm_rx_data_snk_cur_fulltype_mem_4089), + .I2(com_tlm_u_tlm_rx_data_snk_sof_q_1__4097), + .LO(com_tlm_u_tlm_rx_data_snk_bar_hit_check_rmem64_o_5) + ); + defparam com_tlm_u_tlm_rx_data_snk_bar_hit_check_rmem32_o_5_0_a3_0_a2_0_a2.INIT = 8'h40; + LUT3_L com_tlm_u_tlm_rx_data_snk_bar_hit_check_rmem32_o_5_0_a3_0_a2_0_a2 ( + .I0(com_tlm_u_tlm_rx_data_snk_cur_fulltype_64_4088), + .I1(com_tlm_u_tlm_rx_data_snk_cur_fulltype_mem_4089), + .I2(com_tlm_u_tlm_rx_data_snk_sof_q_1__4097), + .LO(com_tlm_u_tlm_rx_data_snk_bar_hit_check_rmem32_o_5) + ); + defparam com_tlm_u_tlm_rx_data_snk_bar_hit_N_68321_i.INIT = 16'hF444; + LUT4_L com_tlm_u_tlm_rx_data_snk_bar_hit_N_68321_i ( + .I0(com_tlm_u_tlm_rx_data_snk_bar_hit_check_raddr_d_i_0_o3[55]), + .I1(com_lnk_rd_5077[63]), + .I2(com_tlm_u_tlm_rx_data_snk_cur_fulltype_oh_1_), + .I3(com_tlm_u_tlm_rx_data_snk_cur_req_id[15]), + .LO(com_tlm_u_tlm_rx_data_snk_bar_hit_N_68321_i_4231) + ); + defparam com_tlm_u_tlm_rx_data_snk_bar_hit_N_68311_i.INIT = 16'hF444; + LUT4_L com_tlm_u_tlm_rx_data_snk_bar_hit_N_68311_i ( + .I0(com_tlm_u_tlm_rx_data_snk_bar_hit_check_raddr_d_i_0_o3[55]), + .I1(com_lnk_rd_5077[62]), + .I2(com_tlm_u_tlm_rx_data_snk_cur_fulltype_oh_1_), + .I3(com_tlm_u_tlm_rx_data_snk_cur_req_id[14]), + .LO(com_tlm_u_tlm_rx_data_snk_bar_hit_N_68311_i_4232) + ); + defparam com_tlm_u_tlm_rx_data_snk_bar_hit_N_68312_i.INIT = 16'hF444; + LUT4_L com_tlm_u_tlm_rx_data_snk_bar_hit_N_68312_i ( + .I0(com_tlm_u_tlm_rx_data_snk_bar_hit_check_raddr_d_i_0_o3[55]), + .I1(com_lnk_rd_5077[61]), + .I2(com_tlm_u_tlm_rx_data_snk_cur_fulltype_oh_1_), + .I3(com_tlm_u_tlm_rx_data_snk_cur_req_id[13]), + .LO(com_tlm_u_tlm_rx_data_snk_bar_hit_N_68312_i_4233) + ); + defparam com_tlm_u_tlm_rx_data_snk_bar_hit_N_68313_i.INIT = 16'hF444; + LUT4_L com_tlm_u_tlm_rx_data_snk_bar_hit_N_68313_i ( + .I0(com_tlm_u_tlm_rx_data_snk_bar_hit_check_raddr_d_i_0_o3[55]), + .I1(com_lnk_rd_5077[60]), + .I2(com_tlm_u_tlm_rx_data_snk_cur_fulltype_oh_1_), + .I3(com_tlm_u_tlm_rx_data_snk_cur_req_id[12]), + .LO(com_tlm_u_tlm_rx_data_snk_bar_hit_N_68313_i_4234) + ); + defparam com_tlm_u_tlm_rx_data_snk_bar_hit_N_68314_i.INIT = 16'hF444; + LUT4_L com_tlm_u_tlm_rx_data_snk_bar_hit_N_68314_i ( + .I0(com_tlm_u_tlm_rx_data_snk_bar_hit_check_raddr_d_i_0_o3[55]), + .I1(com_lnk_rd_5077[59]), + .I2(com_tlm_u_tlm_rx_data_snk_cur_fulltype_oh_1_), + .I3(com_tlm_u_tlm_rx_data_snk_cur_req_id[11]), + .LO(com_tlm_u_tlm_rx_data_snk_bar_hit_N_68314_i_4235) + ); + defparam com_tlm_u_tlm_rx_data_snk_bar_hit_N_68315_i.INIT = 16'hF444; + LUT4_L com_tlm_u_tlm_rx_data_snk_bar_hit_N_68315_i ( + .I0(com_tlm_u_tlm_rx_data_snk_bar_hit_check_raddr_d_i_0_o3[55]), + .I1(com_lnk_rd_5077[58]), + .I2(com_tlm_u_tlm_rx_data_snk_cur_fulltype_oh_1_), + .I3(com_tlm_u_tlm_rx_data_snk_cur_req_id[10]), + .LO(com_tlm_u_tlm_rx_data_snk_bar_hit_N_68315_i_4236) + ); + defparam com_tlm_u_tlm_rx_data_snk_bar_hit_N_68316_i.INIT = 16'hF444; + LUT4_L com_tlm_u_tlm_rx_data_snk_bar_hit_N_68316_i ( + .I0(com_tlm_u_tlm_rx_data_snk_bar_hit_check_raddr_d_i_0_o3[55]), + .I1(com_lnk_rd_5077[57]), + .I2(com_tlm_u_tlm_rx_data_snk_cur_fulltype_oh_1_), + .I3(com_tlm_u_tlm_rx_data_snk_cur_req_id[9]), + .LO(com_tlm_u_tlm_rx_data_snk_bar_hit_N_68316_i_4237) + ); + defparam com_tlm_u_tlm_rx_data_snk_bar_hit_N_68317_i.INIT = 16'hF444; + LUT4_L com_tlm_u_tlm_rx_data_snk_bar_hit_N_68317_i ( + .I0(com_tlm_u_tlm_rx_data_snk_bar_hit_check_raddr_d_i_0_o3[55]), + .I1(com_lnk_rd_5077[56]), + .I2(com_tlm_u_tlm_rx_data_snk_cur_fulltype_oh_1_), + .I3(com_tlm_u_tlm_rx_data_snk_cur_req_id[8]), + .LO(com_tlm_u_tlm_rx_data_snk_bar_hit_N_68317_i_4238) + ); + defparam com_tlm_u_tlm_rx_data_snk_bar_hit_N_68307_i.INIT = 16'hF444; + LUT4_L com_tlm_u_tlm_rx_data_snk_bar_hit_N_68307_i ( + .I0(com_tlm_u_tlm_rx_data_snk_bar_hit_check_raddr_d_i_0_o3[55]), + .I1(com_lnk_rd_5077[55]), + .I2(com_tlm_u_tlm_rx_data_snk_cur_fulltype_oh_1_), + .I3(com_tlm_u_tlm_rx_data_snk_cur_req_id[7]), + .LO(com_tlm_u_tlm_rx_data_snk_bar_hit_N_68307_i_4239) + ); + defparam com_tlm_u_tlm_rx_data_snk_bar_hit_N_68308_i.INIT = 16'hF444; + LUT4_L com_tlm_u_tlm_rx_data_snk_bar_hit_N_68308_i ( + .I0(com_tlm_u_tlm_rx_data_snk_bar_hit_check_raddr_d_i_0_o3[55]), + .I1(com_lnk_rd_5077[54]), + .I2(com_tlm_u_tlm_rx_data_snk_cur_fulltype_oh_1_), + .I3(com_tlm_u_tlm_rx_data_snk_cur_req_id[6]), + .LO(com_tlm_u_tlm_rx_data_snk_bar_hit_N_68308_i_4240) + ); + defparam com_tlm_u_tlm_rx_data_snk_bar_hit_N_68309_i.INIT = 16'hF444; + LUT4_L com_tlm_u_tlm_rx_data_snk_bar_hit_N_68309_i ( + .I0(com_tlm_u_tlm_rx_data_snk_bar_hit_check_raddr_d_i_0_o3[55]), + .I1(com_lnk_rd_5077[53]), + .I2(com_tlm_u_tlm_rx_data_snk_cur_fulltype_oh_1_), + .I3(com_tlm_u_tlm_rx_data_snk_cur_req_id[5]), + .LO(com_tlm_u_tlm_rx_data_snk_bar_hit_N_68309_i_4241) + ); + defparam com_tlm_u_tlm_rx_data_snk_bar_hit_N_68310_i.INIT = 16'hF444; + LUT4_L com_tlm_u_tlm_rx_data_snk_bar_hit_N_68310_i ( + .I0(com_tlm_u_tlm_rx_data_snk_bar_hit_check_raddr_d_i_0_o3[55]), + .I1(com_lnk_rd_5077[52]), + .I2(com_tlm_u_tlm_rx_data_snk_cur_fulltype_oh_1_), + .I3(com_tlm_u_tlm_rx_data_snk_cur_req_id[4]), + .LO(com_tlm_u_tlm_rx_data_snk_bar_hit_N_68310_i_4242) + ); + defparam com_tlm_u_tlm_rx_data_snk_bar_hit_N_68322_i.INIT = 16'hF444; + LUT4_L com_tlm_u_tlm_rx_data_snk_bar_hit_N_68322_i ( + .I0(com_tlm_u_tlm_rx_data_snk_bar_hit_check_raddr_d_i_0_o3[55]), + .I1(com_lnk_rd_5077[51]), + .I2(com_tlm_u_tlm_rx_data_snk_cur_fulltype_oh_1_), + .I3(com_tlm_u_tlm_rx_data_snk_cur_req_id[3]), + .LO(com_tlm_u_tlm_rx_data_snk_bar_hit_N_68322_i_4243) + ); + defparam com_tlm_u_tlm_rx_data_snk_bar_hit_N_68323_i.INIT = 16'hF444; + LUT4_L com_tlm_u_tlm_rx_data_snk_bar_hit_N_68323_i ( + .I0(com_tlm_u_tlm_rx_data_snk_bar_hit_check_raddr_d_i_0_o3[55]), + .I1(com_lnk_rd_5077[50]), + .I2(com_tlm_u_tlm_rx_data_snk_cur_fulltype_oh_1_), + .I3(com_tlm_u_tlm_rx_data_snk_cur_req_id[2]), + .LO(com_tlm_u_tlm_rx_data_snk_bar_hit_N_68323_i_4244) + ); + defparam com_tlm_u_tlm_rx_data_snk_bar_hit_N_68318_i.INIT = 16'hF444; + LUT4_L com_tlm_u_tlm_rx_data_snk_bar_hit_N_68318_i ( + .I0(com_tlm_u_tlm_rx_data_snk_bar_hit_check_raddr_d_i_0_o3[55]), + .I1(com_lnk_rd_5077[49]), + .I2(com_tlm_u_tlm_rx_data_snk_cur_fulltype_oh_1_), + .I3(com_tlm_u_tlm_rx_data_snk_cur_req_id[1]), + .LO(com_tlm_u_tlm_rx_data_snk_bar_hit_N_68318_i_4245) + ); + defparam com_tlm_u_tlm_rx_data_snk_bar_hit_N_68319_i.INIT = 16'hF444; + LUT4_L com_tlm_u_tlm_rx_data_snk_bar_hit_N_68319_i ( + .I0(com_tlm_u_tlm_rx_data_snk_bar_hit_check_raddr_d_i_0_o3[55]), + .I1(com_lnk_rd_5077[48]), + .I2(com_tlm_u_tlm_rx_data_snk_cur_fulltype_oh_1_), + .I3(com_tlm_u_tlm_rx_data_snk_cur_req_id[0]), + .LO(com_tlm_u_tlm_rx_data_snk_bar_hit_N_68319_i_4246) + ); + defparam com_tlm_u_tlm_rx_data_snk_bar_hit_un18_check_raddr_d_0_a2_0_a2_47_.INIT = 4'h8; + LUT2_L com_tlm_u_tlm_rx_data_snk_bar_hit_un18_check_raddr_d_0_a2_0_a2_47_ ( + .I0(com_lnk_rd_5077[47]), + .I1(com_tlm_u_tlm_rx_data_snk_cur_fulltype_oh_7__4090), + .LO(com_tlm_u_tlm_rx_data_snk_bar_hit_un18_check_raddr_d_0_a2_0_a2[47]) + ); + defparam com_tlm_u_tlm_rx_data_snk_bar_hit_un18_check_raddr_d_0_a2_0_a2_46_.INIT = 4'h8; + LUT2_L com_tlm_u_tlm_rx_data_snk_bar_hit_un18_check_raddr_d_0_a2_0_a2_46_ ( + .I0(com_lnk_rd_5077[46]), + .I1(com_tlm_u_tlm_rx_data_snk_cur_fulltype_oh_7__4090), + .LO(com_tlm_u_tlm_rx_data_snk_bar_hit_un18_check_raddr_d_0_a2_0_a2[46]) + ); + defparam com_tlm_u_tlm_rx_data_snk_bar_hit_un18_check_raddr_d_0_a2_0_a2_45_.INIT = 4'h8; + LUT2_L com_tlm_u_tlm_rx_data_snk_bar_hit_un18_check_raddr_d_0_a2_0_a2_45_ ( + .I0(com_lnk_rd_5077[45]), + .I1(com_tlm_u_tlm_rx_data_snk_cur_fulltype_oh_7__4090), + .LO(com_tlm_u_tlm_rx_data_snk_bar_hit_un18_check_raddr_d_0_a2_0_a2[45]) + ); + defparam com_tlm_u_tlm_rx_data_snk_bar_hit_un18_check_raddr_d_0_a2_0_a2_44_.INIT = 4'h8; + LUT2_L com_tlm_u_tlm_rx_data_snk_bar_hit_un18_check_raddr_d_0_a2_0_a2_44_ ( + .I0(com_lnk_rd_5077[44]), + .I1(com_tlm_u_tlm_rx_data_snk_cur_fulltype_oh_7__4090), + .LO(com_tlm_u_tlm_rx_data_snk_bar_hit_un18_check_raddr_d_0_a2_0_a2[44]) + ); + defparam com_tlm_u_tlm_rx_data_snk_bar_hit_un18_check_raddr_d_0_a2_0_a2_43_.INIT = 4'h8; + LUT2_L com_tlm_u_tlm_rx_data_snk_bar_hit_un18_check_raddr_d_0_a2_0_a2_43_ ( + .I0(com_lnk_rd_5077[43]), + .I1(com_tlm_u_tlm_rx_data_snk_cur_fulltype_oh_7__4090), + .LO(com_tlm_u_tlm_rx_data_snk_bar_hit_un18_check_raddr_d_0_a2_0_a2[43]) + ); + defparam com_tlm_u_tlm_rx_data_snk_bar_hit_un18_check_raddr_d_0_a2_0_a2_42_.INIT = 4'h8; + LUT2_L com_tlm_u_tlm_rx_data_snk_bar_hit_un18_check_raddr_d_0_a2_0_a2_42_ ( + .I0(com_lnk_rd_5077[42]), + .I1(com_tlm_u_tlm_rx_data_snk_cur_fulltype_oh_7__4090), + .LO(com_tlm_u_tlm_rx_data_snk_bar_hit_un18_check_raddr_d_0_a2_0_a2[42]) + ); + defparam com_tlm_u_tlm_rx_data_snk_bar_hit_un18_check_raddr_d_0_a2_0_a2_41_.INIT = 4'h8; + LUT2_L com_tlm_u_tlm_rx_data_snk_bar_hit_un18_check_raddr_d_0_a2_0_a2_41_ ( + .I0(com_lnk_rd_5077[41]), + .I1(com_tlm_u_tlm_rx_data_snk_cur_fulltype_oh_7__4090), + .LO(com_tlm_u_tlm_rx_data_snk_bar_hit_un18_check_raddr_d_0_a2_0_a2[41]) + ); + defparam com_tlm_u_tlm_rx_data_snk_bar_hit_un18_check_raddr_d_0_a2_0_a2_40_.INIT = 4'h8; + LUT2_L com_tlm_u_tlm_rx_data_snk_bar_hit_un18_check_raddr_d_0_a2_0_a2_40_ ( + .I0(com_lnk_rd_5077[40]), + .I1(com_tlm_u_tlm_rx_data_snk_cur_fulltype_oh_7__4090), + .LO(com_tlm_u_tlm_rx_data_snk_bar_hit_un18_check_raddr_d_0_a2_0_a2[40]) + ); + defparam com_tlm_u_tlm_rx_data_snk_bar_hit_un18_check_raddr_d_0_a2_0_a2_39_.INIT = 4'h8; + LUT2_L com_tlm_u_tlm_rx_data_snk_bar_hit_un18_check_raddr_d_0_a2_0_a2_39_ ( + .I0(com_lnk_rd_5077[39]), + .I1(com_tlm_u_tlm_rx_data_snk_cur_fulltype_oh_7__4090), + .LO(com_tlm_u_tlm_rx_data_snk_bar_hit_un18_check_raddr_d_0_a2_0_a2[39]) + ); + defparam com_tlm_u_tlm_rx_data_snk_bar_hit_un18_check_raddr_d_0_a2_0_a2_38_.INIT = 4'h8; + LUT2_L com_tlm_u_tlm_rx_data_snk_bar_hit_un18_check_raddr_d_0_a2_0_a2_38_ ( + .I0(com_lnk_rd_5077[38]), + .I1(com_tlm_u_tlm_rx_data_snk_cur_fulltype_oh_7__4090), + .LO(com_tlm_u_tlm_rx_data_snk_bar_hit_un18_check_raddr_d_0_a2_0_a2[38]) + ); + defparam com_tlm_u_tlm_rx_data_snk_bar_hit_un18_check_raddr_d_0_a2_0_a2_37_.INIT = 4'h8; + LUT2_L com_tlm_u_tlm_rx_data_snk_bar_hit_un18_check_raddr_d_0_a2_0_a2_37_ ( + .I0(com_lnk_rd_5077[37]), + .I1(com_tlm_u_tlm_rx_data_snk_cur_fulltype_oh_7__4090), + .LO(com_tlm_u_tlm_rx_data_snk_bar_hit_un18_check_raddr_d_0_a2_0_a2[37]) + ); + defparam com_tlm_u_tlm_rx_data_snk_bar_hit_un18_check_raddr_d_0_a2_0_a2_36_.INIT = 4'h8; + LUT2_L com_tlm_u_tlm_rx_data_snk_bar_hit_un18_check_raddr_d_0_a2_0_a2_36_ ( + .I0(com_lnk_rd_5077[36]), + .I1(com_tlm_u_tlm_rx_data_snk_cur_fulltype_oh_7__4090), + .LO(com_tlm_u_tlm_rx_data_snk_bar_hit_un18_check_raddr_d_0_a2_0_a2[36]) + ); + defparam com_tlm_u_tlm_rx_data_snk_bar_hit_un18_check_raddr_d_0_a2_0_a2_35_.INIT = 4'h8; + LUT2_L com_tlm_u_tlm_rx_data_snk_bar_hit_un18_check_raddr_d_0_a2_0_a2_35_ ( + .I0(com_lnk_rd_5077[35]), + .I1(com_tlm_u_tlm_rx_data_snk_cur_fulltype_oh_7__4090), + .LO(com_tlm_u_tlm_rx_data_snk_bar_hit_un18_check_raddr_d_0_a2_0_a2[35]) + ); + defparam com_tlm_u_tlm_rx_data_snk_bar_hit_un18_check_raddr_d_0_a2_0_a2_34_.INIT = 4'h8; + LUT2_L com_tlm_u_tlm_rx_data_snk_bar_hit_un18_check_raddr_d_0_a2_0_a2_34_ ( + .I0(com_lnk_rd_5077[34]), + .I1(com_tlm_u_tlm_rx_data_snk_cur_fulltype_oh_7__4090), + .LO(com_tlm_u_tlm_rx_data_snk_bar_hit_un18_check_raddr_d_0_a2_0_a2[34]) + ); + defparam com_tlm_u_tlm_rx_data_snk_bar_hit_un18_check_raddr_d_0_a2_0_a2_33_.INIT = 4'h8; + LUT2_L com_tlm_u_tlm_rx_data_snk_bar_hit_un18_check_raddr_d_0_a2_0_a2_33_ ( + .I0(com_lnk_rd_5077[33]), + .I1(com_tlm_u_tlm_rx_data_snk_cur_fulltype_oh_7__4090), + .LO(com_tlm_u_tlm_rx_data_snk_bar_hit_un18_check_raddr_d_0_a2_0_a2[33]) + ); + defparam com_tlm_u_tlm_rx_data_snk_bar_hit_un18_check_raddr_d_0_a2_0_a2_32_.INIT = 4'h8; + LUT2_L com_tlm_u_tlm_rx_data_snk_bar_hit_un18_check_raddr_d_0_a2_0_a2_32_ ( + .I0(com_lnk_rd_5077[32]), + .I1(com_tlm_u_tlm_rx_data_snk_cur_fulltype_oh_7__4090), + .LO(com_tlm_u_tlm_rx_data_snk_bar_hit_un18_check_raddr_d_0_a2_0_a2[32]) + ); + defparam com_tlm_u_tlm_rx_data_snk_bar_hit_un18_check_raddr_d_0_a2_0_a2_31_.INIT = 4'h8; + LUT2_L com_tlm_u_tlm_rx_data_snk_bar_hit_un18_check_raddr_d_0_a2_0_a2_31_ ( + .I0(com_lnk_rd_5077[31]), + .I1(com_tlm_u_tlm_rx_data_snk_cur_fulltype_oh_7__4090), + .LO(com_tlm_u_tlm_rx_data_snk_bar_hit_un18_check_raddr_d_0_a2_0_a2[31]) + ); + defparam com_tlm_u_tlm_rx_data_snk_bar_hit_un18_check_raddr_d_0_a2_0_a2_30_.INIT = 4'h8; + LUT2_L com_tlm_u_tlm_rx_data_snk_bar_hit_un18_check_raddr_d_0_a2_0_a2_30_ ( + .I0(com_lnk_rd_5077[30]), + .I1(com_tlm_u_tlm_rx_data_snk_cur_fulltype_oh_7__4090), + .LO(com_tlm_u_tlm_rx_data_snk_bar_hit_un18_check_raddr_d_0_a2_0_a2[30]) + ); + defparam com_tlm_u_tlm_rx_data_snk_bar_hit_un18_check_raddr_d_0_a2_0_a2_29_.INIT = 4'h8; + LUT2_L com_tlm_u_tlm_rx_data_snk_bar_hit_un18_check_raddr_d_0_a2_0_a2_29_ ( + .I0(com_lnk_rd_5077[29]), + .I1(com_tlm_u_tlm_rx_data_snk_cur_fulltype_oh_7__4090), + .LO(com_tlm_u_tlm_rx_data_snk_bar_hit_un18_check_raddr_d_0_a2_0_a2[29]) + ); + defparam com_tlm_u_tlm_rx_data_snk_bar_hit_un18_check_raddr_d_0_a2_0_a2_28_.INIT = 4'h8; + LUT2_L com_tlm_u_tlm_rx_data_snk_bar_hit_un18_check_raddr_d_0_a2_0_a2_28_ ( + .I0(com_lnk_rd_5077[28]), + .I1(com_tlm_u_tlm_rx_data_snk_cur_fulltype_oh_7__4090), + .LO(com_tlm_u_tlm_rx_data_snk_bar_hit_un18_check_raddr_d_0_a2_0_a2[28]) + ); + defparam com_tlm_u_tlm_rx_data_snk_bar_hit_un18_check_raddr_d_0_a2_0_a2_27_.INIT = 4'h8; + LUT2_L com_tlm_u_tlm_rx_data_snk_bar_hit_un18_check_raddr_d_0_a2_0_a2_27_ ( + .I0(com_lnk_rd_5077[27]), + .I1(com_tlm_u_tlm_rx_data_snk_cur_fulltype_oh_7__4090), + .LO(com_tlm_u_tlm_rx_data_snk_bar_hit_un18_check_raddr_d_0_a2_0_a2[27]) + ); + defparam com_tlm_u_tlm_rx_data_snk_bar_hit_un18_check_raddr_d_0_a2_0_a2_26_.INIT = 4'h8; + LUT2_L com_tlm_u_tlm_rx_data_snk_bar_hit_un18_check_raddr_d_0_a2_0_a2_26_ ( + .I0(com_lnk_rd_5077[26]), + .I1(com_tlm_u_tlm_rx_data_snk_cur_fulltype_oh_7__4090), + .LO(com_tlm_u_tlm_rx_data_snk_bar_hit_un18_check_raddr_d_0_a2_0_a2[26]) + ); + defparam com_tlm_u_tlm_rx_data_snk_bar_hit_un18_check_raddr_d_0_a2_0_a2_25_.INIT = 4'h8; + LUT2_L com_tlm_u_tlm_rx_data_snk_bar_hit_un18_check_raddr_d_0_a2_0_a2_25_ ( + .I0(com_lnk_rd_5077[25]), + .I1(com_tlm_u_tlm_rx_data_snk_cur_fulltype_oh_7__4090), + .LO(com_tlm_u_tlm_rx_data_snk_bar_hit_un18_check_raddr_d_0_a2_0_a2[25]) + ); + defparam com_tlm_u_tlm_rx_data_snk_bar_hit_un18_check_raddr_d_0_a2_0_a2_24_.INIT = 4'h8; + LUT2_L com_tlm_u_tlm_rx_data_snk_bar_hit_un18_check_raddr_d_0_a2_0_a2_24_ ( + .I0(com_lnk_rd_5077[24]), + .I1(com_tlm_u_tlm_rx_data_snk_cur_fulltype_oh_7__4090), + .LO(com_tlm_u_tlm_rx_data_snk_bar_hit_un18_check_raddr_d_0_a2_0_a2[24]) + ); + defparam com_tlm_u_tlm_rx_data_snk_bar_hit_un18_check_raddr_d_0_a2_0_a2_23_.INIT = 4'h8; + LUT2_L com_tlm_u_tlm_rx_data_snk_bar_hit_un18_check_raddr_d_0_a2_0_a2_23_ ( + .I0(com_lnk_rd_5077[23]), + .I1(com_tlm_u_tlm_rx_data_snk_cur_fulltype_oh_7__4090), + .LO(com_tlm_u_tlm_rx_data_snk_bar_hit_un18_check_raddr_d_0_a2_0_a2[23]) + ); + defparam com_tlm_u_tlm_rx_data_snk_bar_hit_un18_check_raddr_d_0_a2_0_a2_22_.INIT = 4'h8; + LUT2_L com_tlm_u_tlm_rx_data_snk_bar_hit_un18_check_raddr_d_0_a2_0_a2_22_ ( + .I0(com_lnk_rd_5077[22]), + .I1(com_tlm_u_tlm_rx_data_snk_cur_fulltype_oh_7__4090), + .LO(com_tlm_u_tlm_rx_data_snk_bar_hit_un18_check_raddr_d_0_a2_0_a2[22]) + ); + defparam com_tlm_u_tlm_rx_data_snk_bar_hit_un18_check_raddr_d_0_a2_0_a2_21_.INIT = 4'h8; + LUT2_L com_tlm_u_tlm_rx_data_snk_bar_hit_un18_check_raddr_d_0_a2_0_a2_21_ ( + .I0(com_lnk_rd_5077[21]), + .I1(com_tlm_u_tlm_rx_data_snk_cur_fulltype_oh_7__4090), + .LO(com_tlm_u_tlm_rx_data_snk_bar_hit_un18_check_raddr_d_0_a2_0_a2[21]) + ); + defparam com_tlm_u_tlm_rx_data_snk_bar_hit_un18_check_raddr_d_0_a2_0_a2_20_.INIT = 4'h8; + LUT2_L com_tlm_u_tlm_rx_data_snk_bar_hit_un18_check_raddr_d_0_a2_0_a2_20_ ( + .I0(com_lnk_rd_5077[20]), + .I1(com_tlm_u_tlm_rx_data_snk_cur_fulltype_oh_7__4090), + .LO(com_tlm_u_tlm_rx_data_snk_bar_hit_un18_check_raddr_d_0_a2_0_a2[20]) + ); + defparam com_tlm_u_tlm_rx_data_snk_bar_hit_un18_check_raddr_d_0_a2_0_a2_19_.INIT = 4'h8; + LUT2_L com_tlm_u_tlm_rx_data_snk_bar_hit_un18_check_raddr_d_0_a2_0_a2_19_ ( + .I0(com_lnk_rd_5077[19]), + .I1(com_tlm_u_tlm_rx_data_snk_cur_fulltype_oh_7__4090), + .LO(com_tlm_u_tlm_rx_data_snk_bar_hit_un18_check_raddr_d_0_a2_0_a2[19]) + ); + defparam com_tlm_u_tlm_rx_data_snk_bar_hit_un18_check_raddr_d_0_a2_0_a2_18_.INIT = 4'h8; + LUT2_L com_tlm_u_tlm_rx_data_snk_bar_hit_un18_check_raddr_d_0_a2_0_a2_18_ ( + .I0(com_lnk_rd_5077[18]), + .I1(com_tlm_u_tlm_rx_data_snk_cur_fulltype_oh_7__4090), + .LO(com_tlm_u_tlm_rx_data_snk_bar_hit_un18_check_raddr_d_0_a2_0_a2[18]) + ); + defparam com_tlm_u_tlm_rx_data_snk_bar_hit_un18_check_raddr_d_0_a2_0_a2_17_.INIT = 4'h8; + LUT2_L com_tlm_u_tlm_rx_data_snk_bar_hit_un18_check_raddr_d_0_a2_0_a2_17_ ( + .I0(com_lnk_rd_5077[17]), + .I1(com_tlm_u_tlm_rx_data_snk_cur_fulltype_oh_7__4090), + .LO(com_tlm_u_tlm_rx_data_snk_bar_hit_un18_check_raddr_d_0_a2_0_a2[17]) + ); + defparam com_tlm_u_tlm_rx_data_snk_bar_hit_un18_check_raddr_d_0_a2_0_a2_16_.INIT = 4'h8; + LUT2_L com_tlm_u_tlm_rx_data_snk_bar_hit_un18_check_raddr_d_0_a2_0_a2_16_ ( + .I0(com_lnk_rd_5077[16]), + .I1(com_tlm_u_tlm_rx_data_snk_cur_fulltype_oh_7__4090), + .LO(com_tlm_u_tlm_rx_data_snk_bar_hit_un18_check_raddr_d_0_a2_0_a2[16]) + ); + defparam com_tlm_u_tlm_rx_data_snk_bar_hit_un18_check_raddr_d_0_a2_0_a2_15_.INIT = 4'h8; + LUT2_L com_tlm_u_tlm_rx_data_snk_bar_hit_un18_check_raddr_d_0_a2_0_a2_15_ ( + .I0(com_lnk_rd_5077[15]), + .I1(com_tlm_u_tlm_rx_data_snk_cur_fulltype_oh_7__4090), + .LO(com_tlm_u_tlm_rx_data_snk_bar_hit_un18_check_raddr_d_0_a2_0_a2[15]) + ); + defparam com_tlm_u_tlm_rx_data_snk_bar_hit_un18_check_raddr_d_0_a2_0_a2_14_.INIT = 4'h8; + LUT2_L com_tlm_u_tlm_rx_data_snk_bar_hit_un18_check_raddr_d_0_a2_0_a2_14_ ( + .I0(com_lnk_rd_5077[14]), + .I1(com_tlm_u_tlm_rx_data_snk_cur_fulltype_oh_7__4090), + .LO(com_tlm_u_tlm_rx_data_snk_bar_hit_un18_check_raddr_d_0_a2_0_a2[14]) + ); + defparam com_tlm_u_tlm_rx_data_snk_bar_hit_un18_check_raddr_d_0_a2_0_a2_13_.INIT = 4'h8; + LUT2_L com_tlm_u_tlm_rx_data_snk_bar_hit_un18_check_raddr_d_0_a2_0_a2_13_ ( + .I0(com_lnk_rd_5077[13]), + .I1(com_tlm_u_tlm_rx_data_snk_cur_fulltype_oh_7__4090), + .LO(com_tlm_u_tlm_rx_data_snk_bar_hit_un18_check_raddr_d_0_a2_0_a2[13]) + ); + defparam com_tlm_u_tlm_rx_data_snk_bar_hit_un18_check_raddr_d_0_a2_0_a2_12_.INIT = 4'h8; + LUT2_L com_tlm_u_tlm_rx_data_snk_bar_hit_un18_check_raddr_d_0_a2_0_a2_12_ ( + .I0(com_lnk_rd_5077[12]), + .I1(com_tlm_u_tlm_rx_data_snk_cur_fulltype_oh_7__4090), + .LO(com_tlm_u_tlm_rx_data_snk_bar_hit_un18_check_raddr_d_0_a2_0_a2[12]) + ); + defparam com_tlm_u_tlm_rx_data_snk_bar_hit_un18_check_raddr_d_0_a2_0_a2_11_.INIT = 4'h8; + LUT2_L com_tlm_u_tlm_rx_data_snk_bar_hit_un18_check_raddr_d_0_a2_0_a2_11_ ( + .I0(com_lnk_rd_5077[11]), + .I1(com_tlm_u_tlm_rx_data_snk_cur_fulltype_oh_7__4090), + .LO(com_tlm_u_tlm_rx_data_snk_bar_hit_un18_check_raddr_d_0_a2_0_a2[11]) + ); + defparam com_tlm_u_tlm_rx_data_snk_bar_hit_un18_check_raddr_d_0_a2_0_a2_10_.INIT = 4'h8; + LUT2_L com_tlm_u_tlm_rx_data_snk_bar_hit_un18_check_raddr_d_0_a2_0_a2_10_ ( + .I0(com_lnk_rd_5077[10]), + .I1(com_tlm_u_tlm_rx_data_snk_cur_fulltype_oh_7__4090), + .LO(com_tlm_u_tlm_rx_data_snk_bar_hit_un18_check_raddr_d_0_a2_0_a2[10]) + ); + defparam com_tlm_u_tlm_rx_data_snk_bar_hit_un18_check_raddr_d_0_a2_0_a2_9_.INIT = 4'h8; + LUT2_L com_tlm_u_tlm_rx_data_snk_bar_hit_un18_check_raddr_d_0_a2_0_a2_9_ ( + .I0(com_lnk_rd_5077[9]), + .I1(com_tlm_u_tlm_rx_data_snk_cur_fulltype_oh_7__4090), + .LO(com_tlm_u_tlm_rx_data_snk_bar_hit_un18_check_raddr_d_0_a2_0_a2[9]) + ); + defparam com_tlm_u_tlm_rx_data_snk_bar_hit_un18_check_raddr_d_0_a2_0_a2_8_.INIT = 4'h8; + LUT2_L com_tlm_u_tlm_rx_data_snk_bar_hit_un18_check_raddr_d_0_a2_0_a2_8_ ( + .I0(com_lnk_rd_5077[8]), + .I1(com_tlm_u_tlm_rx_data_snk_cur_fulltype_oh_7__4090), + .LO(com_tlm_u_tlm_rx_data_snk_bar_hit_un18_check_raddr_d_0_a2_0_a2[8]) + ); + defparam com_tlm_u_tlm_rx_data_snk_bar_hit_un18_check_raddr_d_0_a2_0_a2_7_.INIT = 4'h8; + LUT2_L com_tlm_u_tlm_rx_data_snk_bar_hit_un18_check_raddr_d_0_a2_0_a2_7_ ( + .I0(com_lnk_rd_5077[7]), + .I1(com_tlm_u_tlm_rx_data_snk_cur_fulltype_oh_7__4090), + .LO(com_tlm_u_tlm_rx_data_snk_bar_hit_un18_check_raddr_d_0_a2_0_a2[7]) + ); + defparam com_tlm_u_tlm_rx_data_snk_bar_hit_un18_check_raddr_d_0_a2_0_a2_6_.INIT = 4'h8; + LUT2_L com_tlm_u_tlm_rx_data_snk_bar_hit_un18_check_raddr_d_0_a2_0_a2_6_ ( + .I0(com_lnk_rd[6]), + .I1(com_tlm_u_tlm_rx_data_snk_cur_fulltype_oh_7__4090), + .LO(com_tlm_u_tlm_rx_data_snk_bar_hit_un18_check_raddr_d_0_a2_0_a2[6]) + ); + defparam com_tlm_u_tlm_rx_data_snk_bar_hit_un18_check_raddr_d_0_a2_0_a2_5_.INIT = 4'h8; + LUT2_L com_tlm_u_tlm_rx_data_snk_bar_hit_un18_check_raddr_d_0_a2_0_a2_5_ ( + .I0(com_lnk_rd[5]), + .I1(com_tlm_u_tlm_rx_data_snk_cur_fulltype_oh_7__4090), + .LO(com_tlm_u_tlm_rx_data_snk_bar_hit_un18_check_raddr_d_0_a2_0_a2[5]) + ); + defparam com_tlm_u_tlm_rx_data_snk_bar_hit_un18_check_raddr_d_0_a2_0_a2_4_.INIT = 4'h8; + LUT2_L com_tlm_u_tlm_rx_data_snk_bar_hit_un18_check_raddr_d_0_a2_0_a2_4_ ( + .I0(com_lnk_rd[4]), + .I1(com_tlm_u_tlm_rx_data_snk_cur_fulltype_oh_7__4090), + .LO(com_tlm_u_tlm_rx_data_snk_bar_hit_un18_check_raddr_d_0_a2_0_a2[4]) + ); + FDE com_tlm_u_tlm_rx_data_snk_bar_hit_check_raddr_o_63_ ( + .CE(com_tlm_u_tlm_rx_data_snk_sof_q_1__4097), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_bar_hit_N_68321_i_4231), + .Q(com_cmmt_raddr[63]) + ); + FDE com_tlm_u_tlm_rx_data_snk_bar_hit_check_raddr_o_62_ ( + .CE(com_tlm_u_tlm_rx_data_snk_sof_q_1__4097), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_bar_hit_N_68311_i_4232), + .Q(com_cmmt_raddr[62]) + ); + FDE com_tlm_u_tlm_rx_data_snk_bar_hit_check_raddr_o_61_ ( + .CE(com_tlm_u_tlm_rx_data_snk_sof_q_1__4097), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_bar_hit_N_68312_i_4233), + .Q(com_cmmt_raddr[61]) + ); + FDE com_tlm_u_tlm_rx_data_snk_bar_hit_check_raddr_o_60_ ( + .CE(com_tlm_u_tlm_rx_data_snk_sof_q_1__4097), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_bar_hit_N_68313_i_4234), + .Q(com_cmmt_raddr[60]) + ); + FDE com_tlm_u_tlm_rx_data_snk_bar_hit_check_raddr_o_59_ ( + .CE(com_tlm_u_tlm_rx_data_snk_sof_q_1__4097), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_bar_hit_N_68314_i_4235), + .Q(com_cmmt_raddr[59]) + ); + FDE com_tlm_u_tlm_rx_data_snk_bar_hit_check_raddr_o_58_ ( + .CE(com_tlm_u_tlm_rx_data_snk_sof_q_1__4097), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_bar_hit_N_68315_i_4236), + .Q(com_cmmt_raddr[58]) + ); + FDE com_tlm_u_tlm_rx_data_snk_bar_hit_check_raddr_o_57_ ( + .CE(com_tlm_u_tlm_rx_data_snk_sof_q_1__4097), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_bar_hit_N_68316_i_4237), + .Q(com_cmmt_raddr[57]) + ); + FDE com_tlm_u_tlm_rx_data_snk_bar_hit_check_raddr_o_56_ ( + .CE(com_tlm_u_tlm_rx_data_snk_sof_q_1__4097), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_bar_hit_N_68317_i_4238), + .Q(com_cmmt_raddr[56]) + ); + FDE com_tlm_u_tlm_rx_data_snk_bar_hit_check_raddr_o_55_ ( + .CE(com_tlm_u_tlm_rx_data_snk_sof_q_1__4097), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_bar_hit_N_68307_i_4239), + .Q(com_cmmt_raddr[55]) + ); + FDE com_tlm_u_tlm_rx_data_snk_bar_hit_check_raddr_o_54_ ( + .CE(com_tlm_u_tlm_rx_data_snk_sof_q_1__4097), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_bar_hit_N_68308_i_4240), + .Q(com_cmmt_raddr[54]) + ); + FDE com_tlm_u_tlm_rx_data_snk_bar_hit_check_raddr_o_53_ ( + .CE(com_tlm_u_tlm_rx_data_snk_sof_q_1__4097), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_bar_hit_N_68309_i_4241), + .Q(com_cmmt_raddr[53]) + ); + FDE com_tlm_u_tlm_rx_data_snk_bar_hit_check_raddr_o_52_ ( + .CE(com_tlm_u_tlm_rx_data_snk_sof_q_1__4097), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_bar_hit_N_68310_i_4242), + .Q(com_cmmt_raddr[52]) + ); + FDE com_tlm_u_tlm_rx_data_snk_bar_hit_check_raddr_o_51_ ( + .CE(com_tlm_u_tlm_rx_data_snk_sof_q_1__4097), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_bar_hit_N_68322_i_4243), + .Q(com_cmmt_raddr[51]) + ); + FDE com_tlm_u_tlm_rx_data_snk_bar_hit_check_raddr_o_50_ ( + .CE(com_tlm_u_tlm_rx_data_snk_sof_q_1__4097), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_bar_hit_N_68323_i_4244), + .Q(com_cmmt_raddr[50]) + ); + FDE com_tlm_u_tlm_rx_data_snk_bar_hit_check_raddr_o_49_ ( + .CE(com_tlm_u_tlm_rx_data_snk_sof_q_1__4097), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_bar_hit_N_68318_i_4245), + .Q(com_cmmt_raddr[49]) + ); + FDE com_tlm_u_tlm_rx_data_snk_bar_hit_check_raddr_o_48_ ( + .CE(com_tlm_u_tlm_rx_data_snk_sof_q_1__4097), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_bar_hit_N_68319_i_4246), + .Q(com_cmmt_raddr[48]) + ); + FDE com_tlm_u_tlm_rx_data_snk_bar_hit_check_raddr_o_47_ ( + .CE(com_tlm_u_tlm_rx_data_snk_sof_q_1__4097), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_bar_hit_un18_check_raddr_d_0_a2_0_a2[47]), + .Q(com_cmmt_raddr[47]) + ); + FDE com_tlm_u_tlm_rx_data_snk_bar_hit_check_raddr_o_46_ ( + .CE(com_tlm_u_tlm_rx_data_snk_sof_q_1__4097), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_bar_hit_un18_check_raddr_d_0_a2_0_a2[46]), + .Q(com_cmmt_raddr[46]) + ); + FDE com_tlm_u_tlm_rx_data_snk_bar_hit_check_raddr_o_45_ ( + .CE(com_tlm_u_tlm_rx_data_snk_sof_q_1__4097), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_bar_hit_un18_check_raddr_d_0_a2_0_a2[45]), + .Q(com_cmmt_raddr[45]) + ); + FDE com_tlm_u_tlm_rx_data_snk_bar_hit_check_raddr_o_44_ ( + .CE(com_tlm_u_tlm_rx_data_snk_sof_q_1__4097), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_bar_hit_un18_check_raddr_d_0_a2_0_a2[44]), + .Q(com_cmmt_raddr[44]) + ); + FDE com_tlm_u_tlm_rx_data_snk_bar_hit_check_raddr_o_43_ ( + .CE(com_tlm_u_tlm_rx_data_snk_sof_q_1__4097), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_bar_hit_un18_check_raddr_d_0_a2_0_a2[43]), + .Q(com_cmmt_raddr[43]) + ); + FDE com_tlm_u_tlm_rx_data_snk_bar_hit_check_raddr_o_42_ ( + .CE(com_tlm_u_tlm_rx_data_snk_sof_q_1__4097), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_bar_hit_un18_check_raddr_d_0_a2_0_a2[42]), + .Q(com_cmmt_raddr[42]) + ); + FDE com_tlm_u_tlm_rx_data_snk_bar_hit_check_raddr_o_41_ ( + .CE(com_tlm_u_tlm_rx_data_snk_sof_q_1__4097), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_bar_hit_un18_check_raddr_d_0_a2_0_a2[41]), + .Q(com_cmmt_raddr[41]) + ); + FDE com_tlm_u_tlm_rx_data_snk_bar_hit_check_raddr_o_40_ ( + .CE(com_tlm_u_tlm_rx_data_snk_sof_q_1__4097), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_bar_hit_un18_check_raddr_d_0_a2_0_a2[40]), + .Q(com_cmmt_raddr[40]) + ); + FDE com_tlm_u_tlm_rx_data_snk_bar_hit_check_raddr_o_39_ ( + .CE(com_tlm_u_tlm_rx_data_snk_sof_q_1__4097), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_bar_hit_un18_check_raddr_d_0_a2_0_a2[39]), + .Q(com_cmmt_raddr[39]) + ); + FDE com_tlm_u_tlm_rx_data_snk_bar_hit_check_raddr_o_38_ ( + .CE(com_tlm_u_tlm_rx_data_snk_sof_q_1__4097), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_bar_hit_un18_check_raddr_d_0_a2_0_a2[38]), + .Q(com_cmmt_raddr[38]) + ); + FDE com_tlm_u_tlm_rx_data_snk_bar_hit_check_raddr_o_37_ ( + .CE(com_tlm_u_tlm_rx_data_snk_sof_q_1__4097), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_bar_hit_un18_check_raddr_d_0_a2_0_a2[37]), + .Q(com_cmmt_raddr[37]) + ); + FDE com_tlm_u_tlm_rx_data_snk_bar_hit_check_raddr_o_36_ ( + .CE(com_tlm_u_tlm_rx_data_snk_sof_q_1__4097), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_bar_hit_un18_check_raddr_d_0_a2_0_a2[36]), + .Q(com_cmmt_raddr[36]) + ); + FDE com_tlm_u_tlm_rx_data_snk_bar_hit_check_raddr_o_35_ ( + .CE(com_tlm_u_tlm_rx_data_snk_sof_q_1__4097), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_bar_hit_un18_check_raddr_d_0_a2_0_a2[35]), + .Q(com_cmmt_raddr[35]) + ); + FDE com_tlm_u_tlm_rx_data_snk_bar_hit_check_raddr_o_34_ ( + .CE(com_tlm_u_tlm_rx_data_snk_sof_q_1__4097), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_bar_hit_un18_check_raddr_d_0_a2_0_a2[34]), + .Q(com_cmmt_raddr[34]) + ); + FDE com_tlm_u_tlm_rx_data_snk_bar_hit_check_raddr_o_33_ ( + .CE(com_tlm_u_tlm_rx_data_snk_sof_q_1__4097), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_bar_hit_un18_check_raddr_d_0_a2_0_a2[33]), + .Q(com_cmmt_raddr[33]) + ); + FDE com_tlm_u_tlm_rx_data_snk_bar_hit_check_raddr_o_32_ ( + .CE(com_tlm_u_tlm_rx_data_snk_sof_q_1__4097), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_bar_hit_un18_check_raddr_d_0_a2_0_a2[32]), + .Q(com_cmmt_raddr[32]) + ); + FDE com_tlm_u_tlm_rx_data_snk_bar_hit_check_raddr_o_31_ ( + .CE(com_tlm_u_tlm_rx_data_snk_sof_q_1__4097), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_bar_hit_un18_check_raddr_d_0_a2_0_a2[31]), + .Q(com_cmmt_raddr[31]) + ); + FDE com_tlm_u_tlm_rx_data_snk_bar_hit_check_raddr_o_30_ ( + .CE(com_tlm_u_tlm_rx_data_snk_sof_q_1__4097), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_bar_hit_un18_check_raddr_d_0_a2_0_a2[30]), + .Q(com_cmmt_raddr[30]) + ); + FDE com_tlm_u_tlm_rx_data_snk_bar_hit_check_raddr_o_29_ ( + .CE(com_tlm_u_tlm_rx_data_snk_sof_q_1__4097), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_bar_hit_un18_check_raddr_d_0_a2_0_a2[29]), + .Q(com_cmmt_raddr[29]) + ); + FDE com_tlm_u_tlm_rx_data_snk_bar_hit_check_raddr_o_28_ ( + .CE(com_tlm_u_tlm_rx_data_snk_sof_q_1__4097), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_bar_hit_un18_check_raddr_d_0_a2_0_a2[28]), + .Q(com_cmmt_raddr[28]) + ); + FDE com_tlm_u_tlm_rx_data_snk_bar_hit_check_raddr_o_27_ ( + .CE(com_tlm_u_tlm_rx_data_snk_sof_q_1__4097), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_bar_hit_un18_check_raddr_d_0_a2_0_a2[27]), + .Q(com_cmmt_raddr[27]) + ); + FDE com_tlm_u_tlm_rx_data_snk_bar_hit_check_raddr_o_26_ ( + .CE(com_tlm_u_tlm_rx_data_snk_sof_q_1__4097), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_bar_hit_un18_check_raddr_d_0_a2_0_a2[26]), + .Q(com_cmmt_raddr[26]) + ); + FDE com_tlm_u_tlm_rx_data_snk_bar_hit_check_raddr_o_25_ ( + .CE(com_tlm_u_tlm_rx_data_snk_sof_q_1__4097), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_bar_hit_un18_check_raddr_d_0_a2_0_a2[25]), + .Q(com_cmmt_raddr[25]) + ); + FDE com_tlm_u_tlm_rx_data_snk_bar_hit_check_raddr_o_24_ ( + .CE(com_tlm_u_tlm_rx_data_snk_sof_q_1__4097), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_bar_hit_un18_check_raddr_d_0_a2_0_a2[24]), + .Q(com_cmmt_raddr[24]) + ); + FDE com_tlm_u_tlm_rx_data_snk_bar_hit_check_raddr_o_23_ ( + .CE(com_tlm_u_tlm_rx_data_snk_sof_q_1__4097), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_bar_hit_un18_check_raddr_d_0_a2_0_a2[23]), + .Q(com_cmmt_raddr[23]) + ); + FDE com_tlm_u_tlm_rx_data_snk_bar_hit_check_raddr_o_22_ ( + .CE(com_tlm_u_tlm_rx_data_snk_sof_q_1__4097), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_bar_hit_un18_check_raddr_d_0_a2_0_a2[22]), + .Q(com_cmmt_raddr[22]) + ); + FDE com_tlm_u_tlm_rx_data_snk_bar_hit_check_raddr_o_21_ ( + .CE(com_tlm_u_tlm_rx_data_snk_sof_q_1__4097), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_bar_hit_un18_check_raddr_d_0_a2_0_a2[21]), + .Q(com_cmmt_raddr[21]) + ); + FDE com_tlm_u_tlm_rx_data_snk_bar_hit_check_raddr_o_20_ ( + .CE(com_tlm_u_tlm_rx_data_snk_sof_q_1__4097), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_bar_hit_un18_check_raddr_d_0_a2_0_a2[20]), + .Q(com_cmmt_raddr[20]) + ); + FDE com_tlm_u_tlm_rx_data_snk_bar_hit_check_raddr_o_19_ ( + .CE(com_tlm_u_tlm_rx_data_snk_sof_q_1__4097), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_bar_hit_un18_check_raddr_d_0_a2_0_a2[19]), + .Q(com_cmmt_raddr[19]) + ); + FDE com_tlm_u_tlm_rx_data_snk_bar_hit_check_raddr_o_18_ ( + .CE(com_tlm_u_tlm_rx_data_snk_sof_q_1__4097), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_bar_hit_un18_check_raddr_d_0_a2_0_a2[18]), + .Q(com_cmmt_raddr[18]) + ); + FDE com_tlm_u_tlm_rx_data_snk_bar_hit_check_raddr_o_17_ ( + .CE(com_tlm_u_tlm_rx_data_snk_sof_q_1__4097), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_bar_hit_un18_check_raddr_d_0_a2_0_a2[17]), + .Q(com_cmmt_raddr[17]) + ); + FDE com_tlm_u_tlm_rx_data_snk_bar_hit_check_raddr_o_16_ ( + .CE(com_tlm_u_tlm_rx_data_snk_sof_q_1__4097), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_bar_hit_un18_check_raddr_d_0_a2_0_a2[16]), + .Q(com_cmmt_raddr[16]) + ); + FDE com_tlm_u_tlm_rx_data_snk_bar_hit_check_raddr_o_15_ ( + .CE(com_tlm_u_tlm_rx_data_snk_sof_q_1__4097), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_bar_hit_un18_check_raddr_d_0_a2_0_a2[15]), + .Q(com_cmmt_raddr[15]) + ); + FDE com_tlm_u_tlm_rx_data_snk_bar_hit_check_raddr_o_14_ ( + .CE(com_tlm_u_tlm_rx_data_snk_sof_q_1__4097), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_bar_hit_un18_check_raddr_d_0_a2_0_a2[14]), + .Q(com_cmmt_raddr[14]) + ); + FDE com_tlm_u_tlm_rx_data_snk_bar_hit_check_raddr_o_13_ ( + .CE(com_tlm_u_tlm_rx_data_snk_sof_q_1__4097), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_bar_hit_un18_check_raddr_d_0_a2_0_a2[13]), + .Q(com_cmmt_raddr[13]) + ); + FDE com_tlm_u_tlm_rx_data_snk_bar_hit_check_raddr_o_12_ ( + .CE(com_tlm_u_tlm_rx_data_snk_sof_q_1__4097), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_bar_hit_un18_check_raddr_d_0_a2_0_a2[12]), + .Q(com_cmmt_raddr[12]) + ); + FDE com_tlm_u_tlm_rx_data_snk_bar_hit_check_raddr_o_11_ ( + .CE(com_tlm_u_tlm_rx_data_snk_sof_q_1__4097), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_bar_hit_un18_check_raddr_d_0_a2_0_a2[11]), + .Q(com_cmmt_raddr[11]) + ); + FDE com_tlm_u_tlm_rx_data_snk_bar_hit_check_raddr_o_10_ ( + .CE(com_tlm_u_tlm_rx_data_snk_sof_q_1__4097), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_bar_hit_un18_check_raddr_d_0_a2_0_a2[10]), + .Q(com_cmmt_raddr[10]) + ); + FDE com_tlm_u_tlm_rx_data_snk_bar_hit_check_raddr_o_9_ ( + .CE(com_tlm_u_tlm_rx_data_snk_sof_q_1__4097), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_bar_hit_un18_check_raddr_d_0_a2_0_a2[9]), + .Q(com_cmmt_raddr[9]) + ); + FDE com_tlm_u_tlm_rx_data_snk_bar_hit_check_raddr_o_8_ ( + .CE(com_tlm_u_tlm_rx_data_snk_sof_q_1__4097), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_bar_hit_un18_check_raddr_d_0_a2_0_a2[8]), + .Q(com_cmmt_raddr[8]) + ); + FDE com_tlm_u_tlm_rx_data_snk_bar_hit_check_raddr_o_7_ ( + .CE(com_tlm_u_tlm_rx_data_snk_sof_q_1__4097), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_bar_hit_un18_check_raddr_d_0_a2_0_a2[7]), + .Q(com_cmmt_raddr[7]) + ); + FDE com_tlm_u_tlm_rx_data_snk_bar_hit_check_raddr_o_6_ ( + .CE(com_tlm_u_tlm_rx_data_snk_sof_q_1__4097), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_bar_hit_un18_check_raddr_d_0_a2_0_a2[6]), + .Q(com_cmmt_raddr[6]) + ); + FDE com_tlm_u_tlm_rx_data_snk_bar_hit_check_raddr_o_5_ ( + .CE(com_tlm_u_tlm_rx_data_snk_sof_q_1__4097), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_bar_hit_un18_check_raddr_d_0_a2_0_a2[5]), + .Q(com_cmmt_raddr[5]) + ); + FDE com_tlm_u_tlm_rx_data_snk_bar_hit_check_raddr_o_4_ ( + .CE(com_tlm_u_tlm_rx_data_snk_sof_q_1__4097), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_bar_hit_un18_check_raddr_d_0_a2_0_a2[4]), + .Q(com_cmmt_raddr[4]) + ); + GND com_tlm_u_tlm_rx_fc_src_GND ( + .G(com_tlm_u_tlm_rx_fc_src_GND_4247) + ); + FDRE com_tlm_u_tlm_rx_fc_src_lnk_tfc_src_rdy_o_1 ( + .CE(com_tlm_u_tlm_rx_fc_src_N_68915_i_4250), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_fc_src_N_18216_i), + .Q(com_tlm_u_tlm_rx_fc_src_lnk_tfc_src_rdy), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_rx_fc_src_fc_update_en_o ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_fc_src_N_13880_i), + .Q(com_tlm_aspm_ok), + .R(plm_link_up_i) + ); + FDRSE com_tlm_u_tlm_rx_fc_src_np_vld ( + .CE(com_tlm_u_tlm_rx_fc_src_un1_initFC_st_10_0_a2_0_a2_0_a2_4277), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_fc_src_GND_4247), + .Q(com_tlm_u_tlm_rx_fc_src_np_vld_4276), + .R(plm_link_up_i), + .S(com_tlm_u_tlm_rx_fc_send_state_0_sqmuxa_0) + ); + FDRSE com_tlm_u_tlm_rx_fc_src_p_vld ( + .CE(com_tlm_u_tlm_rx_fc_src_lnk_tfc_src_rdy_o_0_sqmuxa_i_i_a2_0_a2_4249), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_fc_src_GND_4247), + .Q(com_tlm_u_tlm_rx_fc_src_p_vld_4278), + .R(plm_link_up_i), + .S(com_tlm_u_tlm_rx_fc_send_state_0_sqmuxa) + ); + FDRE com_tlm_u_tlm_rx_fc_src_p_pending ( + .CE(com_tlm_u_tlm_rx_fc_src_N_42600_i_4282), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_fc_src_lnk_tfc_data_o_0_sqmuxa), + .Q(com_tlm_u_tlm_rx_fc_src_p_pending_4254), + .R(plm_link_up_i) + ); + FDRE com_tlm_u_tlm_rx_fc_src_np_pending ( + .CE(com_tlm_u_tlm_rx_fc_src_N_42600_i_4282), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_fc_src_np_pending_6), + .Q(com_tlm_u_tlm_rx_fc_src_np_pending_4253), + .R(plm_link_up_i) + ); + FDRE com_tlm_u_tlm_rx_fc_src_init_pending ( + .CE(com_tlm_u_tlm_rx_fc_src_N_42600_i_4282), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_fc_src_initFC_st_i[0]), + .Q(com_tlm_u_tlm_rx_fc_src_init_pending_4248), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_rx_fc_src_fc_req_p_dst_rdy_o ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_fc_src_N_41451_i), + .Q(com_tlm_u_tlm_rx_fc_req_p_dst_rdy), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_rx_fc_src_fc_req_np_dst_rdy_o ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_fc_src_N_41449_i), + .Q(com_tlm_u_tlm_rx_fc_req_np_dst_rdy), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_rx_fc_src_fc_sched_p_o ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_fc_src_fc_sched_p_o_5), + .Q(com_tlm_u_tlm_rx_fc_sched_p), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_rx_fc_src_fc_sched_np_o ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_fc_src_fc_sched_np_o_5), + .Q(com_tlm_u_tlm_rx_fc_sched_np), + .R(plm_link_up_i) + ); + FDRSE com_tlm_u_tlm_rx_fc_src_init2_seq_det ( + .CE(com_tlm_u_tlm_rx_fc_src_initFC_st[4]), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_fc_src_GND_4247), + .Q(com_tlm_u_tlm_rx_fc_src_init2_seq_det_4255), + .R(plm_link_up_i), + .S(com_link_status[2]) + ); + FDRE com_tlm_u_tlm_rx_fc_src_initFC_st_6_ ( + .CE(com_tlm_u_tlm_rx_fc_src_N_68006_i_4251), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_fc_src_initFC_st[5]), + .Q(com_tlm_u_tlm_rx_fc_src_initFC_st[6]), + .R(plm_link_up_i) + ); + FDRE com_tlm_u_tlm_rx_fc_src_initFC_st_5_ ( + .CE(com_tlm_u_tlm_rx_fc_src_N_68006_i_4251), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_fc_src_initFC_st[4]), + .Q(com_tlm_u_tlm_rx_fc_src_initFC_st[5]), + .R(plm_link_up_i) + ); + FDRE com_tlm_u_tlm_rx_fc_src_initFC_st_4_ ( + .CE(com_tlm_u_tlm_rx_fc_src_N_68006_i_4251), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_fc_src_initFC_stc_0_i), + .Q(com_tlm_u_tlm_rx_fc_src_initFC_st[4]), + .R(plm_link_up_i) + ); + FDRE com_tlm_u_tlm_rx_fc_src_initFC_st_3_ ( + .CE(com_tlm_u_tlm_rx_fc_src_N_68006_i_4251), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_fc_src_initFC_st[2]), + .Q(com_tlm_u_tlm_rx_fc_src_initFC_st[3]), + .R(plm_link_up_i) + ); + FDRE com_tlm_u_tlm_rx_fc_src_initFC_st_2_ ( + .CE(com_tlm_u_tlm_rx_fc_src_N_68006_i_4251), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_fc_src_initFC_st[1]), + .Q(com_tlm_u_tlm_rx_fc_src_initFC_st[2]), + .R(plm_link_up_i) + ); + FDRE com_tlm_u_tlm_rx_fc_src_initFC_st_1_ ( + .CE(com_tlm_u_tlm_rx_fc_src_N_68006_i_4251), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_fc_src_initFC_stc_4252), + .Q(com_tlm_u_tlm_rx_fc_src_initFC_st[1]), + .R(plm_link_up_i) + ); + FDSE com_tlm_u_tlm_rx_fc_src_initFC_st_0_ ( + .CE(com_tlm_u_tlm_rx_fc_src_N_68006_i_4251), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_fc_src_N_42461), + .Q(com_tlm_u_tlm_rx_fc_src_initFC_st[0]), + .S(plm_link_up_i) + ); + defparam com_tlm_u_tlm_rx_fc_src_lnk_tfc_data_o_11_i_0_0_o2_0_.INIT = 4'h1; + LUT2 com_tlm_u_tlm_rx_fc_src_lnk_tfc_data_o_11_i_0_0_o2_0_ ( + .I0(com_tlm_u_tlm_rx_fc_src_initFC_st[3]), + .I1(com_tlm_u_tlm_rx_fc_src_initFC_st[6]), + .O(com_tlm_u_tlm_rx_fc_src_N_41729_i) + ); + defparam com_tlm_u_tlm_rx_fc_src_fc_req_p_dst_rdy_o_7_0_a2_0_a2_i_o2.INIT = 4'h2; + LUT2 com_tlm_u_tlm_rx_fc_src_fc_req_p_dst_rdy_o_7_0_a2_0_a2_i_o2 ( + .I0(com_tlm_u_tlm_rx_fc_src_initFC_st[0]), + .I1(com_tlm_u_tlm_rx_fc_src_p_vld_4278), + .O(com_tlm_u_tlm_rx_fc_src_N_41806_i) + ); + defparam com_tlm_u_tlm_rx_fc_src_un1_lnk_tfc_dst_rdy_i_0_o2_i_a2.INIT = 4'h4; + LUT2 com_tlm_u_tlm_rx_fc_src_un1_lnk_tfc_dst_rdy_i_0_o2_i_a2 ( + .I0(com_lnk_tfc_dst_rdy_n), + .I1(com_tlm_u_tlm_rx_fc_src_lnk_tfc_src_rdy), + .O(com_un1_lnk_tfc_dst_rdy_i_0_o2_i_a2) + ); + defparam com_tlm_u_tlm_rx_fc_src_lnk_tfc_data_o_11_0_i_m2_i_m2_i_m4_0_0_.INIT = 8'hE2; + LUT3 com_tlm_u_tlm_rx_fc_src_lnk_tfc_data_o_11_0_i_m2_i_m2_i_m4_0_0_ ( + .I0(com_tlm_u_tlm_rx_fc_src_npd[0]), + .I1(com_tlm_u_tlm_rx_fc_src_p_vld_4278), + .I2(com_tlm_u_tlm_rx_fc_src_pd[0]), + .O(com_tlm_u_tlm_rx_fc_src_N_51505) + ); + defparam com_tlm_u_tlm_rx_fc_src_lnk_tfc_data_o_11_0_i_m2_i_m2_i_m4_0_1_.INIT = 8'hE2; + LUT3 com_tlm_u_tlm_rx_fc_src_lnk_tfc_data_o_11_0_i_m2_i_m2_i_m4_0_1_ ( + .I0(com_tlm_u_tlm_rx_fc_src_npd[1]), + .I1(com_tlm_u_tlm_rx_fc_src_p_vld_4278), + .I2(com_tlm_u_tlm_rx_fc_src_pd[1]), + .O(com_tlm_u_tlm_rx_fc_src_N_51506) + ); + defparam com_tlm_u_tlm_rx_fc_src_lnk_tfc_data_o_11_0_i_m2_i_m2_i_m4_0_2_.INIT = 8'hE2; + LUT3 com_tlm_u_tlm_rx_fc_src_lnk_tfc_data_o_11_0_i_m2_i_m2_i_m4_0_2_ ( + .I0(com_tlm_u_tlm_rx_fc_src_npd[2]), + .I1(com_tlm_u_tlm_rx_fc_src_p_vld_4278), + .I2(com_tlm_u_tlm_rx_fc_src_pd[2]), + .O(com_tlm_u_tlm_rx_fc_src_N_51507) + ); + defparam com_tlm_u_tlm_rx_fc_src_lnk_tfc_data_o_11_0_i_m2_i_m2_i_m4_0_3_.INIT = 8'hE2; + LUT3 com_tlm_u_tlm_rx_fc_src_lnk_tfc_data_o_11_0_i_m2_i_m2_i_m4_0_3_ ( + .I0(com_tlm_u_tlm_rx_fc_src_npd[3]), + .I1(com_tlm_u_tlm_rx_fc_src_p_vld_4278), + .I2(com_tlm_u_tlm_rx_fc_src_pd[3]), + .O(com_tlm_u_tlm_rx_fc_src_N_51508) + ); + defparam com_tlm_u_tlm_rx_fc_src_lnk_tfc_data_o_11_0_i_m2_i_m2_i_m4_0_4_.INIT = 8'hE2; + LUT3 com_tlm_u_tlm_rx_fc_src_lnk_tfc_data_o_11_0_i_m2_i_m2_i_m4_0_4_ ( + .I0(com_tlm_u_tlm_rx_fc_src_npd[4]), + .I1(com_tlm_u_tlm_rx_fc_src_p_vld_4278), + .I2(com_tlm_u_tlm_rx_fc_src_pd[4]), + .O(com_tlm_u_tlm_rx_fc_src_N_51509) + ); + defparam com_tlm_u_tlm_rx_fc_src_lnk_tfc_data_o_11_0_i_m2_i_m2_i_m4_0_6_.INIT = 8'hE2; + LUT3 com_tlm_u_tlm_rx_fc_src_lnk_tfc_data_o_11_0_i_m2_i_m2_i_m4_0_6_ ( + .I0(com_tlm_u_tlm_rx_fc_src_npd[6]), + .I1(com_tlm_u_tlm_rx_fc_src_p_vld_4278), + .I2(com_tlm_u_tlm_rx_fc_src_pd[6]), + .O(com_tlm_u_tlm_rx_fc_src_N_51511) + ); + defparam com_tlm_u_tlm_rx_fc_src_lnk_tfc_data_o_11_0_i_m2_i_m2_i_m4_0_7_.INIT = 8'hE2; + LUT3 com_tlm_u_tlm_rx_fc_src_lnk_tfc_data_o_11_0_i_m2_i_m2_i_m4_0_7_ ( + .I0(com_tlm_u_tlm_rx_fc_src_npd[7]), + .I1(com_tlm_u_tlm_rx_fc_src_p_vld_4278), + .I2(com_tlm_u_tlm_rx_fc_src_pd[7]), + .O(com_tlm_u_tlm_rx_fc_src_N_51512) + ); + defparam com_tlm_u_tlm_rx_fc_src_lnk_tfc_data_o_11_0_i_m2_i_m2_i_m4_0_8_.INIT = 8'hE2; + LUT3 com_tlm_u_tlm_rx_fc_src_lnk_tfc_data_o_11_0_i_m2_i_m2_i_m4_0_8_ ( + .I0(com_tlm_u_tlm_rx_fc_src_npd[8]), + .I1(com_tlm_u_tlm_rx_fc_src_p_vld_4278), + .I2(com_tlm_u_tlm_rx_fc_src_pd[8]), + .O(com_tlm_u_tlm_rx_fc_src_N_51513) + ); + defparam com_tlm_u_tlm_rx_fc_src_lnk_tfc_data_o_11_0_i_m2_i_m2_i_m4_0_9_.INIT = 8'hE2; + LUT3 com_tlm_u_tlm_rx_fc_src_lnk_tfc_data_o_11_0_i_m2_i_m2_i_m4_0_9_ ( + .I0(com_tlm_u_tlm_rx_fc_src_npd[9]), + .I1(com_tlm_u_tlm_rx_fc_src_p_vld_4278), + .I2(com_tlm_u_tlm_rx_fc_src_pd[9]), + .O(com_tlm_u_tlm_rx_fc_src_N_51514) + ); + defparam com_tlm_u_tlm_rx_fc_src_lnk_tfc_data_o_11_0_i_m2_i_m2_i_m4_0_10_.INIT = 8'hE2; + LUT3 com_tlm_u_tlm_rx_fc_src_lnk_tfc_data_o_11_0_i_m2_i_m2_i_m4_0_10_ ( + .I0(com_tlm_u_tlm_rx_fc_src_npd[10]), + .I1(com_tlm_u_tlm_rx_fc_src_p_vld_4278), + .I2(com_tlm_u_tlm_rx_fc_src_pd[10]), + .O(com_tlm_u_tlm_rx_fc_src_N_51515) + ); + defparam com_tlm_u_tlm_rx_fc_src_lnk_tfc_data_o_11_0_i_m2_i_m2_i_m4_0_11_.INIT = 8'hE2; + LUT3 com_tlm_u_tlm_rx_fc_src_lnk_tfc_data_o_11_0_i_m2_i_m2_i_m4_0_11_ ( + .I0(com_tlm_u_tlm_rx_fc_src_npd[11]), + .I1(com_tlm_u_tlm_rx_fc_src_p_vld_4278), + .I2(com_tlm_u_tlm_rx_fc_src_pd[11]), + .O(com_tlm_u_tlm_rx_fc_src_N_51516) + ); + defparam com_tlm_u_tlm_rx_fc_src_lnk_tfc_header_o_11_0_i_m2_i_m2_i_m4_0_0_.INIT = 8'hE2; + LUT3 com_tlm_u_tlm_rx_fc_src_lnk_tfc_header_o_11_0_i_m2_i_m2_i_m4_0_0_ ( + .I0(com_tlm_u_tlm_rx_fc_src_nph[0]), + .I1(com_tlm_u_tlm_rx_fc_src_p_vld_4278), + .I2(com_tlm_u_tlm_rx_fc_src_ph[0]), + .O(com_tlm_u_tlm_rx_fc_src_N_51517) + ); + defparam com_tlm_u_tlm_rx_fc_src_lnk_tfc_header_o_11_0_i_m2_i_m2_i_m4_0_1_.INIT = 8'hE2; + LUT3 com_tlm_u_tlm_rx_fc_src_lnk_tfc_header_o_11_0_i_m2_i_m2_i_m4_0_1_ ( + .I0(com_tlm_u_tlm_rx_fc_src_nph[1]), + .I1(com_tlm_u_tlm_rx_fc_src_p_vld_4278), + .I2(com_tlm_u_tlm_rx_fc_src_ph[1]), + .O(com_tlm_u_tlm_rx_fc_src_N_51518) + ); + defparam com_tlm_u_tlm_rx_fc_src_lnk_tfc_header_o_11_0_i_m2_i_m2_i_m4_0_2_.INIT = 8'hE2; + LUT3 com_tlm_u_tlm_rx_fc_src_lnk_tfc_header_o_11_0_i_m2_i_m2_i_m4_0_2_ ( + .I0(com_tlm_u_tlm_rx_fc_src_nph[2]), + .I1(com_tlm_u_tlm_rx_fc_src_p_vld_4278), + .I2(com_tlm_u_tlm_rx_fc_src_ph[2]), + .O(com_tlm_u_tlm_rx_fc_src_N_51519) + ); + defparam com_tlm_u_tlm_rx_fc_src_lnk_tfc_header_o_11_0_i_m2_i_m2_i_m4_0_3_.INIT = 8'hE2; + LUT3 com_tlm_u_tlm_rx_fc_src_lnk_tfc_header_o_11_0_i_m2_i_m2_i_m4_0_3_ ( + .I0(com_tlm_u_tlm_rx_fc_src_nph[3]), + .I1(com_tlm_u_tlm_rx_fc_src_p_vld_4278), + .I2(com_tlm_u_tlm_rx_fc_src_ph[3]), + .O(com_tlm_u_tlm_rx_fc_src_N_51520) + ); + defparam com_tlm_u_tlm_rx_fc_src_lnk_tfc_header_o_11_0_i_m2_i_m2_i_m4_0_4_.INIT = 8'hE2; + LUT3 com_tlm_u_tlm_rx_fc_src_lnk_tfc_header_o_11_0_i_m2_i_m2_i_m4_0_4_ ( + .I0(com_tlm_u_tlm_rx_fc_src_nph[4]), + .I1(com_tlm_u_tlm_rx_fc_src_p_vld_4278), + .I2(com_tlm_u_tlm_rx_fc_src_ph[4]), + .O(com_tlm_u_tlm_rx_fc_src_N_51521) + ); + defparam com_tlm_u_tlm_rx_fc_src_lnk_tfc_header_o_11_0_i_m2_i_m2_i_m4_0_5_.INIT = 8'hE2; + LUT3 com_tlm_u_tlm_rx_fc_src_lnk_tfc_header_o_11_0_i_m2_i_m2_i_m4_0_5_ ( + .I0(com_tlm_u_tlm_rx_fc_src_nph[5]), + .I1(com_tlm_u_tlm_rx_fc_src_p_vld_4278), + .I2(com_tlm_u_tlm_rx_fc_src_ph[5]), + .O(com_tlm_u_tlm_rx_fc_src_N_51522) + ); + defparam com_tlm_u_tlm_rx_fc_src_lnk_tfc_header_o_11_0_i_m2_i_m2_i_m4_0_6_.INIT = 8'hE2; + LUT3 com_tlm_u_tlm_rx_fc_src_lnk_tfc_header_o_11_0_i_m2_i_m2_i_m4_0_6_ ( + .I0(com_tlm_u_tlm_rx_fc_src_nph[6]), + .I1(com_tlm_u_tlm_rx_fc_src_p_vld_4278), + .I2(com_tlm_u_tlm_rx_fc_src_ph[6]), + .O(com_tlm_u_tlm_rx_fc_src_N_51523) + ); + defparam com_tlm_u_tlm_rx_fc_src_lnk_tfc_header_o_11_0_i_m2_i_m2_i_m4_0_7_.INIT = 8'hE2; + LUT3 com_tlm_u_tlm_rx_fc_src_lnk_tfc_header_o_11_0_i_m2_i_m2_i_m4_0_7_ ( + .I0(com_tlm_u_tlm_rx_fc_src_nph[7]), + .I1(com_tlm_u_tlm_rx_fc_src_p_vld_4278), + .I2(com_tlm_u_tlm_rx_fc_src_ph[7]), + .O(com_tlm_u_tlm_rx_fc_src_N_51524) + ); + defparam com_tlm_u_tlm_rx_fc_src_lnk_tfc_data_o_11_0_i_m2_i_m2_i_m4_0_5_.INIT = 8'hE2; + LUT3 com_tlm_u_tlm_rx_fc_src_lnk_tfc_data_o_11_0_i_m2_i_m2_i_m4_0_5_ ( + .I0(com_tlm_u_tlm_rx_fc_src_npd[5]), + .I1(com_tlm_u_tlm_rx_fc_src_p_vld_4278), + .I2(com_tlm_u_tlm_rx_fc_src_pd[5]), + .O(com_tlm_u_tlm_rx_fc_src_N_51510) + ); + defparam com_tlm_u_tlm_rx_fc_src_lnk_tfc_data_o_11_i_0_0_a3_0_0_.INIT = 8'h54; + LUT3 com_tlm_u_tlm_rx_fc_src_lnk_tfc_data_o_11_i_0_0_a3_0_0_ ( + .I0(com_tlm_u_tlm_rx_fc_src_initFC_st[0]), + .I1(com_tlm_u_tlm_rx_fc_src_initFC_st[2]), + .I2(com_tlm_u_tlm_rx_fc_src_initFC_st[5]), + .O(com_tlm_u_tlm_rx_fc_src_N_43114) + ); + defparam com_tlm_u_tlm_rx_fc_src_lnk_tfc_data_o_11_i_0_0_a3_0_.INIT = 8'h01; + LUT3 com_tlm_u_tlm_rx_fc_src_lnk_tfc_data_o_11_i_0_0_a3_0_ ( + .I0(com_tlm_u_tlm_rx_fc_src_initFC_st[0]), + .I1(com_tlm_u_tlm_rx_fc_src_initFC_st[2]), + .I2(com_tlm_u_tlm_rx_fc_src_initFC_st[5]), + .O(com_tlm_u_tlm_rx_fc_src_N_43113) + ); + defparam com_tlm_u_tlm_rx_fc_src_lnk_tfc_src_rdy_o_7_f0_i_0_0_a2.INIT = 16'hAAA8; + LUT4 com_tlm_u_tlm_rx_fc_src_lnk_tfc_src_rdy_o_7_f0_i_0_0_a2 ( + .I0(com_lnk_tfc_sent_n), + .I1(com_tlm_u_tlm_rx_fc_src_init_pending_4248), + .I2(com_tlm_u_tlm_rx_fc_src_np_pending_4253), + .I3(com_tlm_u_tlm_rx_fc_src_p_pending_4254), + .O(com_tlm_u_tlm_rx_fc_src_N_42600) + ); + defparam com_tlm_u_tlm_rx_fc_src_lnk_tfc_src_rdy_o_0_sqmuxa_i_i_a2_0_a2.INIT = 4'h4; + LUT2 com_tlm_u_tlm_rx_fc_src_lnk_tfc_src_rdy_o_0_sqmuxa_i_i_a2_0_a2 ( + .I0(com_tlm_u_tlm_rx_fc_src_N_42600), + .I1(com_tlm_u_tlm_rx_fc_src_initFC_st[0]), + .O(com_tlm_u_tlm_rx_fc_src_lnk_tfc_src_rdy_o_0_sqmuxa_i_i_a2_0_a2_4249) + ); + defparam com_tlm_u_tlm_rx_fc_src_lnk_tfc_data_o_11_i_0_0_5_32162.INIT = 16'hF351; + LUT4_L com_tlm_u_tlm_rx_fc_src_lnk_tfc_data_o_11_i_0_0_5_32162 ( + .I0(com_tlm_u_tlm_rx_fc_src_N_43113), + .I1(com_tlm_u_tlm_rx_fc_src_N_43114), + .I2(com_tlm_u_tlm_rx_fc_req_npd[5]), + .I3(com_tlm_u_tlm_rx_fc_req_pd[5]), + .LO(com_tlm_u_tlm_rx_fc_src_lnk_tfc_data_o_11_i_0_0_5_32162_4262) + ); + defparam com_tlm_u_tlm_rx_fc_src_lnk_tfc_header_o_11_3_a2_i_0_7_32163.INIT = 16'hF351; + LUT4_L com_tlm_u_tlm_rx_fc_src_lnk_tfc_header_o_11_3_a2_i_0_7_32163 ( + .I0(com_tlm_u_tlm_rx_fc_src_N_43113), + .I1(com_tlm_u_tlm_rx_fc_src_N_43114), + .I2(com_tlm_u_tlm_rx_fc_req_nph[7]), + .I3(com_tlm_u_tlm_rx_fc_req_ph[7]), + .LO(com_tlm_u_tlm_rx_fc_src_lnk_tfc_header_o_11_3_a2_i_0_7_32163_4268) + ); + defparam com_tlm_u_tlm_rx_fc_src_lnk_tfc_data_o_11_i_0_0_8_32164.INIT = 16'hF351; + LUT4_L com_tlm_u_tlm_rx_fc_src_lnk_tfc_data_o_11_i_0_0_8_32164 ( + .I0(com_tlm_u_tlm_rx_fc_src_N_43113), + .I1(com_tlm_u_tlm_rx_fc_src_N_43114), + .I2(com_tlm_u_tlm_rx_fc_req_npd[8]), + .I3(com_tlm_u_tlm_rx_fc_req_pd[8]), + .LO(com_tlm_u_tlm_rx_fc_src_lnk_tfc_data_o_11_i_0_0_8_32164_4259) + ); + defparam com_tlm_u_tlm_rx_fc_src_lnk_tfc_data_o_11_i_0_0_7_32165.INIT = 16'hF351; + LUT4_L com_tlm_u_tlm_rx_fc_src_lnk_tfc_data_o_11_i_0_0_7_32165 ( + .I0(com_tlm_u_tlm_rx_fc_src_N_43113), + .I1(com_tlm_u_tlm_rx_fc_src_N_43114), + .I2(com_tlm_u_tlm_rx_fc_req_npd[7]), + .I3(com_tlm_u_tlm_rx_fc_req_pd[7]), + .LO(com_tlm_u_tlm_rx_fc_src_lnk_tfc_data_o_11_i_0_0_7_32165_4260) + ); + defparam com_tlm_u_tlm_rx_fc_src_lnk_tfc_data_o_11_i_0_0_6_32166.INIT = 16'hF351; + LUT4_L com_tlm_u_tlm_rx_fc_src_lnk_tfc_data_o_11_i_0_0_6_32166 ( + .I0(com_tlm_u_tlm_rx_fc_src_N_43113), + .I1(com_tlm_u_tlm_rx_fc_src_N_43114), + .I2(com_tlm_u_tlm_rx_fc_req_npd[6]), + .I3(com_tlm_u_tlm_rx_fc_req_pd[6]), + .LO(com_tlm_u_tlm_rx_fc_src_lnk_tfc_data_o_11_i_0_0_6_32166_4261) + ); + defparam com_tlm_u_tlm_rx_fc_src_lnk_tfc_data_o_11_i_0_0_4_32167.INIT = 16'hF351; + LUT4_L com_tlm_u_tlm_rx_fc_src_lnk_tfc_data_o_11_i_0_0_4_32167 ( + .I0(com_tlm_u_tlm_rx_fc_src_N_43113), + .I1(com_tlm_u_tlm_rx_fc_src_N_43114), + .I2(com_tlm_u_tlm_rx_fc_req_npd[4]), + .I3(com_tlm_u_tlm_rx_fc_req_pd[4]), + .LO(com_tlm_u_tlm_rx_fc_src_lnk_tfc_data_o_11_i_0_0_4_32167_4263) + ); + defparam com_tlm_u_tlm_rx_fc_src_lnk_tfc_data_o_11_i_0_0_3_32168.INIT = 16'hF351; + LUT4_L com_tlm_u_tlm_rx_fc_src_lnk_tfc_data_o_11_i_0_0_3_32168 ( + .I0(com_tlm_u_tlm_rx_fc_src_N_43113), + .I1(com_tlm_u_tlm_rx_fc_src_N_43114), + .I2(com_tlm_u_tlm_rx_fc_req_npd[3]), + .I3(com_tlm_u_tlm_rx_fc_req_pd[3]), + .LO(com_tlm_u_tlm_rx_fc_src_lnk_tfc_data_o_11_i_0_0_3_32168_4264) + ); + defparam com_tlm_u_tlm_rx_fc_src_lnk_tfc_data_o_11_i_0_0_2_32169.INIT = 16'hF351; + LUT4_L com_tlm_u_tlm_rx_fc_src_lnk_tfc_data_o_11_i_0_0_2_32169 ( + .I0(com_tlm_u_tlm_rx_fc_src_N_43113), + .I1(com_tlm_u_tlm_rx_fc_src_N_43114), + .I2(com_tlm_u_tlm_rx_fc_req_npd[2]), + .I3(com_tlm_u_tlm_rx_fc_req_pd[2]), + .LO(com_tlm_u_tlm_rx_fc_src_lnk_tfc_data_o_11_i_0_0_2_32169_4265) + ); + defparam com_tlm_u_tlm_rx_fc_src_lnk_tfc_data_o_11_i_0_0_1_32170.INIT = 16'hF351; + LUT4_L com_tlm_u_tlm_rx_fc_src_lnk_tfc_data_o_11_i_0_0_1_32170 ( + .I0(com_tlm_u_tlm_rx_fc_src_N_43113), + .I1(com_tlm_u_tlm_rx_fc_src_N_43114), + .I2(com_tlm_u_tlm_rx_fc_req_npd[1]), + .I3(com_tlm_u_tlm_rx_fc_req_pd[1]), + .LO(com_tlm_u_tlm_rx_fc_src_lnk_tfc_data_o_11_i_0_0_1_32170_4266) + ); + defparam com_tlm_u_tlm_rx_fc_src_lnk_tfc_data_o_11_i_0_0_0_32171.INIT = 16'hF351; + LUT4_L com_tlm_u_tlm_rx_fc_src_lnk_tfc_data_o_11_i_0_0_0_32171 ( + .I0(com_tlm_u_tlm_rx_fc_src_N_43113), + .I1(com_tlm_u_tlm_rx_fc_src_N_43114), + .I2(com_tlm_u_tlm_rx_fc_req_npd[0]), + .I3(com_tlm_u_tlm_rx_fc_req_pd[0]), + .LO(com_tlm_u_tlm_rx_fc_src_lnk_tfc_data_o_11_i_0_0_0_32171_4267) + ); + defparam com_tlm_u_tlm_rx_fc_src_lnk_tfc_header_o_11_3_a2_i_0_4_32172.INIT = 16'hF351; + LUT4_L com_tlm_u_tlm_rx_fc_src_lnk_tfc_header_o_11_3_a2_i_0_4_32172 ( + .I0(com_tlm_u_tlm_rx_fc_src_N_43113), + .I1(com_tlm_u_tlm_rx_fc_src_N_43114), + .I2(com_tlm_u_tlm_rx_fc_req_nph[4]), + .I3(com_tlm_u_tlm_rx_fc_req_ph[4]), + .LO(com_tlm_u_tlm_rx_fc_src_lnk_tfc_header_o_11_3_a2_i_0_4_32172_4271) + ); + defparam com_tlm_u_tlm_rx_fc_src_lnk_tfc_header_o_11_3_a2_i_0_3_32173.INIT = 16'hF351; + LUT4_L com_tlm_u_tlm_rx_fc_src_lnk_tfc_header_o_11_3_a2_i_0_3_32173 ( + .I0(com_tlm_u_tlm_rx_fc_src_N_43113), + .I1(com_tlm_u_tlm_rx_fc_src_N_43114), + .I2(com_tlm_u_tlm_rx_fc_req_nph[3]), + .I3(com_tlm_u_tlm_rx_fc_req_ph[3]), + .LO(com_tlm_u_tlm_rx_fc_src_lnk_tfc_header_o_11_3_a2_i_0_3_32173_4272) + ); + defparam com_tlm_u_tlm_rx_fc_src_lnk_tfc_header_o_11_3_a2_i_0_2_32174.INIT = 16'hF351; + LUT4_L com_tlm_u_tlm_rx_fc_src_lnk_tfc_header_o_11_3_a2_i_0_2_32174 ( + .I0(com_tlm_u_tlm_rx_fc_src_N_43113), + .I1(com_tlm_u_tlm_rx_fc_src_N_43114), + .I2(com_tlm_u_tlm_rx_fc_req_nph[2]), + .I3(com_tlm_u_tlm_rx_fc_req_ph[2]), + .LO(com_tlm_u_tlm_rx_fc_src_lnk_tfc_header_o_11_3_a2_i_0_2_32174_4273) + ); + defparam com_tlm_u_tlm_rx_fc_src_lnk_tfc_header_o_11_i_0_0_6_32176.INIT = 16'hF351; + LUT4_L com_tlm_u_tlm_rx_fc_src_lnk_tfc_header_o_11_i_0_0_6_32176 ( + .I0(com_tlm_u_tlm_rx_fc_src_N_43113), + .I1(com_tlm_u_tlm_rx_fc_src_N_43114), + .I2(com_tlm_u_tlm_rx_fc_req_nph[6]), + .I3(com_tlm_u_tlm_rx_fc_req_ph[6]), + .LO(com_tlm_u_tlm_rx_fc_src_lnk_tfc_header_o_11_i_0_0_6_32176_4269) + ); + defparam com_tlm_u_tlm_rx_fc_src_lnk_tfc_header_o_11_i_0_0_5_32177.INIT = 16'hF351; + LUT4_L com_tlm_u_tlm_rx_fc_src_lnk_tfc_header_o_11_i_0_0_5_32177 ( + .I0(com_tlm_u_tlm_rx_fc_src_N_43113), + .I1(com_tlm_u_tlm_rx_fc_src_N_43114), + .I2(com_tlm_u_tlm_rx_fc_req_nph[5]), + .I3(com_tlm_u_tlm_rx_fc_req_ph[5]), + .LO(com_tlm_u_tlm_rx_fc_src_lnk_tfc_header_o_11_i_0_0_5_32177_4270) + ); + defparam com_tlm_u_tlm_rx_fc_src_lnk_tfc_header_o_11_i_0_0_1_32178.INIT = 16'hF351; + LUT4_L com_tlm_u_tlm_rx_fc_src_lnk_tfc_header_o_11_i_0_0_1_32178 ( + .I0(com_tlm_u_tlm_rx_fc_src_N_43113), + .I1(com_tlm_u_tlm_rx_fc_src_N_43114), + .I2(com_tlm_u_tlm_rx_fc_req_nph[1]), + .I3(com_tlm_u_tlm_rx_fc_req_ph[1]), + .LO(com_tlm_u_tlm_rx_fc_src_lnk_tfc_header_o_11_i_0_0_1_32178_4274) + ); + defparam com_tlm_u_tlm_rx_fc_src_lnk_tfc_header_o_11_i_0_0_0_32179.INIT = 16'hF351; + LUT4_L com_tlm_u_tlm_rx_fc_src_lnk_tfc_header_o_11_i_0_0_0_32179 ( + .I0(com_tlm_u_tlm_rx_fc_src_N_43113), + .I1(com_tlm_u_tlm_rx_fc_src_N_43114), + .I2(com_tlm_u_tlm_rx_fc_req_nph[0]), + .I3(com_tlm_u_tlm_rx_fc_req_ph[0]), + .LO(com_tlm_u_tlm_rx_fc_src_lnk_tfc_header_o_11_i_0_0_0_32179_4275) + ); + defparam com_tlm_u_tlm_rx_fc_src_lnk_tfc_data_o_11_i_0_0_11_32180.INIT = 16'hF351; + LUT4_L com_tlm_u_tlm_rx_fc_src_lnk_tfc_data_o_11_i_0_0_11_32180 ( + .I0(com_tlm_u_tlm_rx_fc_src_N_43113), + .I1(com_tlm_u_tlm_rx_fc_src_N_43114), + .I2(com_tlm_u_tlm_rx_fc_req_npd[11]), + .I3(com_tlm_u_tlm_rx_fc_req_pd[11]), + .LO(com_tlm_u_tlm_rx_fc_src_lnk_tfc_data_o_11_i_0_0_11_32180_4256) + ); + defparam com_tlm_u_tlm_rx_fc_src_lnk_tfc_data_o_11_i_0_0_10_32181.INIT = 16'hF351; + LUT4_L com_tlm_u_tlm_rx_fc_src_lnk_tfc_data_o_11_i_0_0_10_32181 ( + .I0(com_tlm_u_tlm_rx_fc_src_N_43113), + .I1(com_tlm_u_tlm_rx_fc_src_N_43114), + .I2(com_tlm_u_tlm_rx_fc_req_npd[10]), + .I3(com_tlm_u_tlm_rx_fc_req_pd[10]), + .LO(com_tlm_u_tlm_rx_fc_src_lnk_tfc_data_o_11_i_0_0_10_32181_4257) + ); + defparam com_tlm_u_tlm_rx_fc_src_lnk_tfc_data_o_11_i_0_0_9_32182.INIT = 16'hF351; + LUT4_L com_tlm_u_tlm_rx_fc_src_lnk_tfc_data_o_11_i_0_0_9_32182 ( + .I0(com_tlm_u_tlm_rx_fc_src_N_43113), + .I1(com_tlm_u_tlm_rx_fc_src_N_43114), + .I2(com_tlm_u_tlm_rx_fc_req_npd[9]), + .I3(com_tlm_u_tlm_rx_fc_req_pd[9]), + .LO(com_tlm_u_tlm_rx_fc_src_lnk_tfc_data_o_11_i_0_0_9_32182_4258) + ); + defparam com_tlm_u_tlm_rx_fc_src_N_68915_i.INIT = 4'hD; + LUT2 com_tlm_u_tlm_rx_fc_src_N_68915_i ( + .I0(com_tlm_u_tlm_rx_fc_src_N_42600), + .I1(com_un1_lnk_tfc_dst_rdy_i_0_o2_i_a2), + .O(com_tlm_u_tlm_rx_fc_src_N_68915_i_4250) + ); + defparam com_tlm_u_tlm_rx_fc_src_N_68006_i.INIT = 8'hDF; + LUT3 com_tlm_u_tlm_rx_fc_src_N_68006_i ( + .I0(com_tlm_u_tlm_rx_fc_src_N_42600), + .I1(com_tlm_u_tlm_rx_fc_src_initFC_st[0]), + .I2(plm_link_up_1), + .O(com_tlm_u_tlm_rx_fc_src_N_68006_i_4251) + ); + defparam com_tlm_u_tlm_rx_fc_src_initFC_st_4_0_i_0_a2_0_.INIT = 16'h0001; + LUT4_L com_tlm_u_tlm_rx_fc_src_initFC_st_4_0_i_0_a2_0_ ( + .I0(com_tlm_u_tlm_rx_fc_src_N_41811_i), + .I1(com_link_status[1]), + .I2(com_link_status[2]), + .I3(com_tlm_u_tlm_rx_fc_src_init2_seq_det_4255), + .LO(com_tlm_u_tlm_rx_fc_src_N_42461) + ); + defparam com_tlm_u_tlm_rx_fc_src_initFC_stc.INIT = 4'h4; + LUT2_L com_tlm_u_tlm_rx_fc_src_initFC_stc ( + .I0(com_tlm_u_tlm_rx_fc_src_N_41811_i), + .I1(com_link_status[1]), + .LO(com_tlm_u_tlm_rx_fc_src_initFC_stc_4252) + ); + defparam com_tlm_u_tlm_rx_fc_src_initFC_stc_0.INIT = 16'h1110; + LUT4_L com_tlm_u_tlm_rx_fc_src_initFC_stc_0 ( + .I0(com_tlm_u_tlm_rx_fc_src_N_41811_i), + .I1(com_link_status[1]), + .I2(com_link_status[2]), + .I3(com_tlm_u_tlm_rx_fc_src_init2_seq_det_4255), + .LO(com_tlm_u_tlm_rx_fc_src_initFC_stc_0_i) + ); + defparam com_tlm_u_tlm_rx_fc_src_N_51187_i.INIT = 4'h1; + LUT1_L com_tlm_u_tlm_rx_fc_src_N_51187_i ( + .I0(com_un1_lnk_tfc_dst_rdy_i_0_o2_i_a2), + .LO(com_N_51187_i) + ); + defparam com_tlm_u_tlm_rx_fc_src_aspm_ok_i.INIT = 4'h1; + LUT1_L com_tlm_u_tlm_rx_fc_src_aspm_ok_i ( + .I0(com_tlm_aspm_ok), + .LO(com_tlm_u_tlm_rx_aspm_ok_i) + ); + defparam com_tlm_u_tlm_rx_fc_src_fc_sched_np_o_5_0_a2_0_a2_0_a2.INIT = 4'h4; + LUT2_L com_tlm_u_tlm_rx_fc_src_fc_sched_np_o_5_0_a2_0_a2_0_a2 ( + .I0(com_lnk_tfc_sent_n), + .I1(com_tlm_u_tlm_rx_fc_src_np_pending_4253), + .LO(com_tlm_u_tlm_rx_fc_src_fc_sched_np_o_5) + ); + defparam com_tlm_u_tlm_rx_fc_src_fc_sched_p_o_5_0_a2_0_a2_0_a2.INIT = 4'h4; + LUT2_L com_tlm_u_tlm_rx_fc_src_fc_sched_p_o_5_0_a2_0_a2_0_a2 ( + .I0(com_lnk_tfc_sent_n), + .I1(com_tlm_u_tlm_rx_fc_src_p_pending_4254), + .LO(com_tlm_u_tlm_rx_fc_src_fc_sched_p_o_5) + ); + defparam com_tlm_u_tlm_rx_fc_src_fc_req_np_dst_rdy_o_7_0_a2_0_a2_i.INIT = 8'h02; + LUT3_L com_tlm_u_tlm_rx_fc_src_fc_req_np_dst_rdy_o_7_0_a2_0_a2_i ( + .I0(com_tlm_u_tlm_rx_fc_src_initFC_st[0]), + .I1(com_tlm_u_tlm_rx_fc_src_np_vld_4276), + .I2(com_tlm_u_tlm_rx_fc_send_state_0_sqmuxa_0), + .LO(com_tlm_u_tlm_rx_fc_src_N_41449_i) + ); + defparam com_tlm_u_tlm_rx_fc_src_fc_req_p_dst_rdy_o_7_0_a2_0_a2_i.INIT = 4'h2; + LUT2_L com_tlm_u_tlm_rx_fc_src_fc_req_p_dst_rdy_o_7_0_a2_0_a2_i ( + .I0(com_tlm_u_tlm_rx_fc_src_N_41806_i), + .I1(com_tlm_u_tlm_rx_fc_send_state_0_sqmuxa), + .LO(com_tlm_u_tlm_rx_fc_src_N_41451_i) + ); + defparam com_tlm_u_tlm_rx_fc_src_np_pending_6_0_a2_0_a2_0_a2.INIT = 4'h8; + LUT2_L com_tlm_u_tlm_rx_fc_src_np_pending_6_0_a2_0_a2_0_a2 ( + .I0(com_tlm_u_tlm_rx_fc_src_N_41806_i), + .I1(com_tlm_u_tlm_rx_fc_src_np_vld_4276), + .LO(com_tlm_u_tlm_rx_fc_src_np_pending_6) + ); + defparam com_tlm_u_tlm_rx_fc_src_lnk_tfc_data_o_0_sqmuxa_0_a2_0_a2_0_a2.INIT = 4'h8; + LUT2_L com_tlm_u_tlm_rx_fc_src_lnk_tfc_data_o_0_sqmuxa_0_a2_0_a2_0_a2 ( + .I0(com_tlm_u_tlm_rx_fc_src_initFC_st[0]), + .I1(com_tlm_u_tlm_rx_fc_src_p_vld_4278), + .LO(com_tlm_u_tlm_rx_fc_src_lnk_tfc_data_o_0_sqmuxa) + ); + defparam com_tlm_u_tlm_rx_fc_src_fc_update_en_o_3_i_0_0_0.INIT = 16'h5150; + LUT4_L com_tlm_u_tlm_rx_fc_src_fc_update_en_o_3_i_0_0_0 ( + .I0(com_link_status[1]), + .I1(com_link_status[2]), + .I2(com_tlm_aspm_ok), + .I3(com_tlm_u_tlm_rx_fc_src_init2_seq_det_4255), + .LO(com_tlm_u_tlm_rx_fc_src_N_13880_i) + ); + defparam com_tlm_u_tlm_rx_fc_src_lnk_tfc_data_o_11_i_0_0_11_.INIT = 16'h80A0; + LUT4_L com_tlm_u_tlm_rx_fc_src_lnk_tfc_data_o_11_i_0_0_11_ ( + .I0(com_tlm_u_tlm_rx_fc_src_N_41729_i), + .I1(com_tlm_u_tlm_rx_fc_src_N_51516), + .I2(com_tlm_u_tlm_rx_fc_src_lnk_tfc_data_o_11_i_0_0_11_32180_4256), + .I3(com_tlm_u_tlm_rx_fc_src_initFC_st[0]), + .LO(com_tlm_u_tlm_rx_fc_src_N_12919_i) + ); + defparam com_tlm_u_tlm_rx_fc_src_lnk_tfc_data_o_11_i_0_0_10_.INIT = 16'h80A0; + LUT4_L com_tlm_u_tlm_rx_fc_src_lnk_tfc_data_o_11_i_0_0_10_ ( + .I0(com_tlm_u_tlm_rx_fc_src_N_41729_i), + .I1(com_tlm_u_tlm_rx_fc_src_N_51515), + .I2(com_tlm_u_tlm_rx_fc_src_lnk_tfc_data_o_11_i_0_0_10_32181_4257), + .I3(com_tlm_u_tlm_rx_fc_src_initFC_st[0]), + .LO(com_tlm_u_tlm_rx_fc_src_N_12917_i) + ); + defparam com_tlm_u_tlm_rx_fc_src_lnk_tfc_data_o_11_i_0_0_9_.INIT = 16'h80A0; + LUT4_L com_tlm_u_tlm_rx_fc_src_lnk_tfc_data_o_11_i_0_0_9_ ( + .I0(com_tlm_u_tlm_rx_fc_src_N_41729_i), + .I1(com_tlm_u_tlm_rx_fc_src_N_51514), + .I2(com_tlm_u_tlm_rx_fc_src_lnk_tfc_data_o_11_i_0_0_9_32182_4258), + .I3(com_tlm_u_tlm_rx_fc_src_initFC_st[0]), + .LO(com_tlm_u_tlm_rx_fc_src_N_12915_i) + ); + defparam com_tlm_u_tlm_rx_fc_src_lnk_tfc_data_o_11_i_0_0_8_.INIT = 16'h80A0; + LUT4_L com_tlm_u_tlm_rx_fc_src_lnk_tfc_data_o_11_i_0_0_8_ ( + .I0(com_tlm_u_tlm_rx_fc_src_N_41729_i), + .I1(com_tlm_u_tlm_rx_fc_src_N_51513), + .I2(com_tlm_u_tlm_rx_fc_src_lnk_tfc_data_o_11_i_0_0_8_32164_4259), + .I3(com_tlm_u_tlm_rx_fc_src_initFC_st[0]), + .LO(com_tlm_u_tlm_rx_fc_src_N_12913_i) + ); + defparam com_tlm_u_tlm_rx_fc_src_lnk_tfc_data_o_11_i_0_0_7_.INIT = 16'h80A0; + LUT4_L com_tlm_u_tlm_rx_fc_src_lnk_tfc_data_o_11_i_0_0_7_ ( + .I0(com_tlm_u_tlm_rx_fc_src_N_41729_i), + .I1(com_tlm_u_tlm_rx_fc_src_N_51512), + .I2(com_tlm_u_tlm_rx_fc_src_lnk_tfc_data_o_11_i_0_0_7_32165_4260), + .I3(com_tlm_u_tlm_rx_fc_src_initFC_st[0]), + .LO(com_tlm_u_tlm_rx_fc_src_N_12911_i) + ); + defparam com_tlm_u_tlm_rx_fc_src_lnk_tfc_data_o_11_i_0_0_6_.INIT = 16'h80A0; + LUT4_L com_tlm_u_tlm_rx_fc_src_lnk_tfc_data_o_11_i_0_0_6_ ( + .I0(com_tlm_u_tlm_rx_fc_src_N_41729_i), + .I1(com_tlm_u_tlm_rx_fc_src_N_51511), + .I2(com_tlm_u_tlm_rx_fc_src_lnk_tfc_data_o_11_i_0_0_6_32166_4261), + .I3(com_tlm_u_tlm_rx_fc_src_initFC_st[0]), + .LO(com_tlm_u_tlm_rx_fc_src_N_12909_i) + ); + defparam com_tlm_u_tlm_rx_fc_src_lnk_tfc_data_o_11_i_0_0_5_.INIT = 16'h80A0; + LUT4_L com_tlm_u_tlm_rx_fc_src_lnk_tfc_data_o_11_i_0_0_5_ ( + .I0(com_tlm_u_tlm_rx_fc_src_N_41729_i), + .I1(com_tlm_u_tlm_rx_fc_src_N_51510), + .I2(com_tlm_u_tlm_rx_fc_src_lnk_tfc_data_o_11_i_0_0_5_32162_4262), + .I3(com_tlm_u_tlm_rx_fc_src_initFC_st[0]), + .LO(com_tlm_u_tlm_rx_fc_src_N_12907_i) + ); + defparam com_tlm_u_tlm_rx_fc_src_lnk_tfc_data_o_11_i_0_0_4_.INIT = 16'h80A0; + LUT4_L com_tlm_u_tlm_rx_fc_src_lnk_tfc_data_o_11_i_0_0_4_ ( + .I0(com_tlm_u_tlm_rx_fc_src_N_41729_i), + .I1(com_tlm_u_tlm_rx_fc_src_N_51509), + .I2(com_tlm_u_tlm_rx_fc_src_lnk_tfc_data_o_11_i_0_0_4_32167_4263), + .I3(com_tlm_u_tlm_rx_fc_src_initFC_st[0]), + .LO(com_tlm_u_tlm_rx_fc_src_N_12905_i) + ); + defparam com_tlm_u_tlm_rx_fc_src_lnk_tfc_data_o_11_i_0_0_3_.INIT = 16'h80A0; + LUT4_L com_tlm_u_tlm_rx_fc_src_lnk_tfc_data_o_11_i_0_0_3_ ( + .I0(com_tlm_u_tlm_rx_fc_src_N_41729_i), + .I1(com_tlm_u_tlm_rx_fc_src_N_51508), + .I2(com_tlm_u_tlm_rx_fc_src_lnk_tfc_data_o_11_i_0_0_3_32168_4264), + .I3(com_tlm_u_tlm_rx_fc_src_initFC_st[0]), + .LO(com_tlm_u_tlm_rx_fc_src_N_12903_i) + ); + defparam com_tlm_u_tlm_rx_fc_src_lnk_tfc_data_o_11_i_0_0_2_.INIT = 16'h80A0; + LUT4_L com_tlm_u_tlm_rx_fc_src_lnk_tfc_data_o_11_i_0_0_2_ ( + .I0(com_tlm_u_tlm_rx_fc_src_N_41729_i), + .I1(com_tlm_u_tlm_rx_fc_src_N_51507), + .I2(com_tlm_u_tlm_rx_fc_src_lnk_tfc_data_o_11_i_0_0_2_32169_4265), + .I3(com_tlm_u_tlm_rx_fc_src_initFC_st[0]), + .LO(com_tlm_u_tlm_rx_fc_src_N_12901_i) + ); + defparam com_tlm_u_tlm_rx_fc_src_lnk_tfc_data_o_11_i_0_0_1_.INIT = 16'h80A0; + LUT4_L com_tlm_u_tlm_rx_fc_src_lnk_tfc_data_o_11_i_0_0_1_ ( + .I0(com_tlm_u_tlm_rx_fc_src_N_41729_i), + .I1(com_tlm_u_tlm_rx_fc_src_N_51506), + .I2(com_tlm_u_tlm_rx_fc_src_lnk_tfc_data_o_11_i_0_0_1_32170_4266), + .I3(com_tlm_u_tlm_rx_fc_src_initFC_st[0]), + .LO(com_tlm_u_tlm_rx_fc_src_N_12899_i) + ); + defparam com_tlm_u_tlm_rx_fc_src_lnk_tfc_data_o_11_i_0_0_0_.INIT = 16'h80A0; + LUT4_L com_tlm_u_tlm_rx_fc_src_lnk_tfc_data_o_11_i_0_0_0_ ( + .I0(com_tlm_u_tlm_rx_fc_src_N_41729_i), + .I1(com_tlm_u_tlm_rx_fc_src_N_51505), + .I2(com_tlm_u_tlm_rx_fc_src_lnk_tfc_data_o_11_i_0_0_0_32171_4267), + .I3(com_tlm_u_tlm_rx_fc_src_initFC_st[0]), + .LO(com_tlm_u_tlm_rx_fc_src_N_12897_i) + ); + defparam com_tlm_u_tlm_rx_fc_src_lnk_tfc_header_o_11_3_a2_i_0_7_.INIT = 16'h80A0; + LUT4_L com_tlm_u_tlm_rx_fc_src_lnk_tfc_header_o_11_3_a2_i_0_7_ ( + .I0(com_tlm_u_tlm_rx_fc_src_N_41729_i), + .I1(com_tlm_u_tlm_rx_fc_src_N_51524), + .I2(com_tlm_u_tlm_rx_fc_src_lnk_tfc_header_o_11_3_a2_i_0_7_32163_4268), + .I3(com_tlm_u_tlm_rx_fc_src_initFC_st[0]), + .LO(com_tlm_u_tlm_rx_fc_src_N_34413_i) + ); + defparam com_tlm_u_tlm_rx_fc_src_lnk_tfc_header_o_11_i_0_0_6_.INIT = 16'h80A0; + LUT4_L com_tlm_u_tlm_rx_fc_src_lnk_tfc_header_o_11_i_0_0_6_ ( + .I0(com_tlm_u_tlm_rx_fc_src_N_41729_i), + .I1(com_tlm_u_tlm_rx_fc_src_N_51523), + .I2(com_tlm_u_tlm_rx_fc_src_lnk_tfc_header_o_11_i_0_0_6_32176_4269), + .I3(com_tlm_u_tlm_rx_fc_src_initFC_st[0]), + .LO(com_tlm_u_tlm_rx_fc_src_N_12930_i) + ); + defparam com_tlm_u_tlm_rx_fc_src_lnk_tfc_header_o_11_i_0_0_5_.INIT = 16'h80A0; + LUT4_L com_tlm_u_tlm_rx_fc_src_lnk_tfc_header_o_11_i_0_0_5_ ( + .I0(com_tlm_u_tlm_rx_fc_src_N_41729_i), + .I1(com_tlm_u_tlm_rx_fc_src_N_51522), + .I2(com_tlm_u_tlm_rx_fc_src_lnk_tfc_header_o_11_i_0_0_5_32177_4270), + .I3(com_tlm_u_tlm_rx_fc_src_initFC_st[0]), + .LO(com_tlm_u_tlm_rx_fc_src_N_12928_i) + ); + defparam com_tlm_u_tlm_rx_fc_src_lnk_tfc_header_o_11_3_a2_i_0_4_.INIT = 16'h80A0; + LUT4_L com_tlm_u_tlm_rx_fc_src_lnk_tfc_header_o_11_3_a2_i_0_4_ ( + .I0(com_tlm_u_tlm_rx_fc_src_N_41729_i), + .I1(com_tlm_u_tlm_rx_fc_src_N_51521), + .I2(com_tlm_u_tlm_rx_fc_src_lnk_tfc_header_o_11_3_a2_i_0_4_32172_4271), + .I3(com_tlm_u_tlm_rx_fc_src_initFC_st[0]), + .LO(com_tlm_u_tlm_rx_fc_src_N_34411_i) + ); + defparam com_tlm_u_tlm_rx_fc_src_lnk_tfc_header_o_11_3_a2_i_0_3_.INIT = 16'h80A0; + LUT4_L com_tlm_u_tlm_rx_fc_src_lnk_tfc_header_o_11_3_a2_i_0_3_ ( + .I0(com_tlm_u_tlm_rx_fc_src_N_41729_i), + .I1(com_tlm_u_tlm_rx_fc_src_N_51520), + .I2(com_tlm_u_tlm_rx_fc_src_lnk_tfc_header_o_11_3_a2_i_0_3_32173_4272), + .I3(com_tlm_u_tlm_rx_fc_src_initFC_st[0]), + .LO(com_tlm_u_tlm_rx_fc_src_N_34409_i) + ); + defparam com_tlm_u_tlm_rx_fc_src_lnk_tfc_header_o_11_3_a2_i_0_2_.INIT = 16'h80A0; + LUT4_L com_tlm_u_tlm_rx_fc_src_lnk_tfc_header_o_11_3_a2_i_0_2_ ( + .I0(com_tlm_u_tlm_rx_fc_src_N_41729_i), + .I1(com_tlm_u_tlm_rx_fc_src_N_51519), + .I2(com_tlm_u_tlm_rx_fc_src_lnk_tfc_header_o_11_3_a2_i_0_2_32174_4273), + .I3(com_tlm_u_tlm_rx_fc_src_initFC_st[0]), + .LO(com_tlm_u_tlm_rx_fc_src_N_34407_i) + ); + defparam com_tlm_u_tlm_rx_fc_src_lnk_tfc_header_o_11_i_0_0_1_.INIT = 16'h80A0; + LUT4_L com_tlm_u_tlm_rx_fc_src_lnk_tfc_header_o_11_i_0_0_1_ ( + .I0(com_tlm_u_tlm_rx_fc_src_N_41729_i), + .I1(com_tlm_u_tlm_rx_fc_src_N_51518), + .I2(com_tlm_u_tlm_rx_fc_src_lnk_tfc_header_o_11_i_0_0_1_32178_4274), + .I3(com_tlm_u_tlm_rx_fc_src_initFC_st[0]), + .LO(com_tlm_u_tlm_rx_fc_src_N_12923_i) + ); + defparam com_tlm_u_tlm_rx_fc_src_lnk_tfc_header_o_11_i_0_0_0_.INIT = 16'h80A0; + LUT4_L com_tlm_u_tlm_rx_fc_src_lnk_tfc_header_o_11_i_0_0_0_ ( + .I0(com_tlm_u_tlm_rx_fc_src_N_41729_i), + .I1(com_tlm_u_tlm_rx_fc_src_N_51517), + .I2(com_tlm_u_tlm_rx_fc_src_lnk_tfc_header_o_11_i_0_0_0_32179_4275), + .I3(com_tlm_u_tlm_rx_fc_src_initFC_st[0]), + .LO(com_tlm_u_tlm_rx_fc_src_N_12921_i) + ); + defparam com_tlm_u_tlm_rx_fc_src_un1_initFC_st_2_0_a2_0_a2_0_a2.INIT = 8'h01; + LUT3_L com_tlm_u_tlm_rx_fc_src_un1_initFC_st_2_0_a2_0_a2_0_a2 ( + .I0(com_tlm_u_tlm_rx_fc_src_initFC_st[1]), + .I1(com_tlm_u_tlm_rx_fc_src_initFC_st[2]), + .I2(com_tlm_u_tlm_rx_fc_src_initFC_st[3]), + .LO(com_tlm_u_tlm_rx_fc_src_un1_initFC_st_2_0_a2_0_a2_0_a2_4279) + ); + defparam com_tlm_u_tlm_rx_fc_src_N_41729_i_i.INIT = 4'h1; + LUT1_L com_tlm_u_tlm_rx_fc_src_N_41729_i_i ( + .I0(com_tlm_u_tlm_rx_fc_src_N_41729_i), + .LO(com_tlm_u_tlm_rx_fc_src_N_41729_i_i_4280) + ); + defparam com_tlm_u_tlm_rx_fc_src_N_68992_i.INIT = 8'hFE; + LUT3_L com_tlm_u_tlm_rx_fc_src_N_68992_i ( + .I0(com_tlm_u_tlm_rx_fc_src_N_41806_i), + .I1(com_tlm_u_tlm_rx_fc_src_initFC_st[2]), + .I2(com_tlm_u_tlm_rx_fc_src_initFC_st[5]), + .LO(com_tlm_u_tlm_rx_fc_src_N_68992_i_4281) + ); + defparam com_tlm_u_tlm_rx_fc_src_lnk_tfc_src_rdy_o_7_f0_i_0_0.INIT = 8'h31; + LUT3_L com_tlm_u_tlm_rx_fc_src_lnk_tfc_src_rdy_o_7_f0_i_0_0 ( + .I0(com_tlm_u_tlm_rx_fc_src_N_41806_i), + .I1(com_tlm_u_tlm_rx_fc_src_N_42600), + .I2(com_tlm_u_tlm_rx_fc_src_np_vld_4276), + .LO(com_tlm_u_tlm_rx_fc_src_N_18216_i) + ); + defparam com_tlm_u_tlm_rx_fc_src_initFC_nst_1_sqmuxa_i_0_0_o4.INIT = 8'h01; + LUT3 com_tlm_u_tlm_rx_fc_src_initFC_nst_1_sqmuxa_i_0_0_o4 ( + .I0(com_tlm_u_tlm_rx_fc_src_initFC_st[0]), + .I1(com_tlm_u_tlm_rx_fc_src_initFC_st[6]), + .I2(com_tlm_u_tlm_rx_fc_src_initFC_st[3]), + .O(com_tlm_u_tlm_rx_fc_src_N_41811_i) + ); + defparam com_tlm_u_tlm_rx_fc_src_un1_initFC_st_10_0_a2_0_a2_0_a2.INIT = 8'h10; + LUT3 com_tlm_u_tlm_rx_fc_src_un1_initFC_st_10_0_a2_0_a2_0_a2 ( + .I0(com_tlm_u_tlm_rx_fc_src_N_42600), + .I1(com_tlm_u_tlm_rx_fc_src_p_vld_4278), + .I2(com_tlm_u_tlm_rx_fc_src_initFC_st[0]), + .O(com_tlm_u_tlm_rx_fc_src_un1_initFC_st_10_0_a2_0_a2_0_a2_4277) + ); + FDE com_tlm_u_tlm_rx_fc_src_pd_11_ ( + .CE(com_tlm_u_tlm_rx_fc_send_state_0_sqmuxa), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_fc_req_pd[11]), + .Q(com_tlm_u_tlm_rx_fc_src_pd[11]) + ); + FDE com_tlm_u_tlm_rx_fc_src_pd_10_ ( + .CE(com_tlm_u_tlm_rx_fc_send_state_0_sqmuxa), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_fc_req_pd[10]), + .Q(com_tlm_u_tlm_rx_fc_src_pd[10]) + ); + FDE com_tlm_u_tlm_rx_fc_src_pd_9_ ( + .CE(com_tlm_u_tlm_rx_fc_send_state_0_sqmuxa), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_fc_req_pd[9]), + .Q(com_tlm_u_tlm_rx_fc_src_pd[9]) + ); + FDE com_tlm_u_tlm_rx_fc_src_pd_8_ ( + .CE(com_tlm_u_tlm_rx_fc_send_state_0_sqmuxa), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_fc_req_pd[8]), + .Q(com_tlm_u_tlm_rx_fc_src_pd[8]) + ); + FDE com_tlm_u_tlm_rx_fc_src_pd_7_ ( + .CE(com_tlm_u_tlm_rx_fc_send_state_0_sqmuxa), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_fc_req_pd[7]), + .Q(com_tlm_u_tlm_rx_fc_src_pd[7]) + ); + FDE com_tlm_u_tlm_rx_fc_src_pd_6_ ( + .CE(com_tlm_u_tlm_rx_fc_send_state_0_sqmuxa), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_fc_req_pd[6]), + .Q(com_tlm_u_tlm_rx_fc_src_pd[6]) + ); + FDE com_tlm_u_tlm_rx_fc_src_pd_5_ ( + .CE(com_tlm_u_tlm_rx_fc_send_state_0_sqmuxa), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_fc_req_pd[5]), + .Q(com_tlm_u_tlm_rx_fc_src_pd[5]) + ); + FDE com_tlm_u_tlm_rx_fc_src_pd_4_ ( + .CE(com_tlm_u_tlm_rx_fc_send_state_0_sqmuxa), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_fc_req_pd[4]), + .Q(com_tlm_u_tlm_rx_fc_src_pd[4]) + ); + FDE com_tlm_u_tlm_rx_fc_src_pd_3_ ( + .CE(com_tlm_u_tlm_rx_fc_send_state_0_sqmuxa), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_fc_req_pd[3]), + .Q(com_tlm_u_tlm_rx_fc_src_pd[3]) + ); + FDE com_tlm_u_tlm_rx_fc_src_pd_2_ ( + .CE(com_tlm_u_tlm_rx_fc_send_state_0_sqmuxa), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_fc_req_pd[2]), + .Q(com_tlm_u_tlm_rx_fc_src_pd[2]) + ); + FDE com_tlm_u_tlm_rx_fc_src_pd_1_ ( + .CE(com_tlm_u_tlm_rx_fc_send_state_0_sqmuxa), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_fc_req_pd[1]), + .Q(com_tlm_u_tlm_rx_fc_src_pd[1]) + ); + FDE com_tlm_u_tlm_rx_fc_src_pd_0_ ( + .CE(com_tlm_u_tlm_rx_fc_send_state_0_sqmuxa), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_fc_req_pd[0]), + .Q(com_tlm_u_tlm_rx_fc_src_pd[0]) + ); + FDE com_tlm_u_tlm_rx_fc_src_ph_7_ ( + .CE(com_tlm_u_tlm_rx_fc_send_state_0_sqmuxa), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_fc_req_ph[7]), + .Q(com_tlm_u_tlm_rx_fc_src_ph[7]) + ); + FDE com_tlm_u_tlm_rx_fc_src_ph_6_ ( + .CE(com_tlm_u_tlm_rx_fc_send_state_0_sqmuxa), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_fc_req_ph[6]), + .Q(com_tlm_u_tlm_rx_fc_src_ph[6]) + ); + FDE com_tlm_u_tlm_rx_fc_src_ph_5_ ( + .CE(com_tlm_u_tlm_rx_fc_send_state_0_sqmuxa), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_fc_req_ph[5]), + .Q(com_tlm_u_tlm_rx_fc_src_ph[5]) + ); + FDE com_tlm_u_tlm_rx_fc_src_ph_4_ ( + .CE(com_tlm_u_tlm_rx_fc_send_state_0_sqmuxa), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_fc_req_ph[4]), + .Q(com_tlm_u_tlm_rx_fc_src_ph[4]) + ); + FDE com_tlm_u_tlm_rx_fc_src_ph_3_ ( + .CE(com_tlm_u_tlm_rx_fc_send_state_0_sqmuxa), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_fc_req_ph[3]), + .Q(com_tlm_u_tlm_rx_fc_src_ph[3]) + ); + FDE com_tlm_u_tlm_rx_fc_src_ph_2_ ( + .CE(com_tlm_u_tlm_rx_fc_send_state_0_sqmuxa), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_fc_req_ph[2]), + .Q(com_tlm_u_tlm_rx_fc_src_ph[2]) + ); + FDE com_tlm_u_tlm_rx_fc_src_ph_1_ ( + .CE(com_tlm_u_tlm_rx_fc_send_state_0_sqmuxa), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_fc_req_ph[1]), + .Q(com_tlm_u_tlm_rx_fc_src_ph[1]) + ); + FDE com_tlm_u_tlm_rx_fc_src_ph_0_ ( + .CE(com_tlm_u_tlm_rx_fc_send_state_0_sqmuxa), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_fc_req_ph[0]), + .Q(com_tlm_u_tlm_rx_fc_src_ph[0]) + ); + FDE com_tlm_u_tlm_rx_fc_src_npd_11_ ( + .CE(com_tlm_u_tlm_rx_fc_send_state_0_sqmuxa_0), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_fc_req_npd[11]), + .Q(com_tlm_u_tlm_rx_fc_src_npd[11]) + ); + FDE com_tlm_u_tlm_rx_fc_src_npd_10_ ( + .CE(com_tlm_u_tlm_rx_fc_send_state_0_sqmuxa_0), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_fc_req_npd[10]), + .Q(com_tlm_u_tlm_rx_fc_src_npd[10]) + ); + FDE com_tlm_u_tlm_rx_fc_src_npd_9_ ( + .CE(com_tlm_u_tlm_rx_fc_send_state_0_sqmuxa_0), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_fc_req_npd[9]), + .Q(com_tlm_u_tlm_rx_fc_src_npd[9]) + ); + FDE com_tlm_u_tlm_rx_fc_src_npd_8_ ( + .CE(com_tlm_u_tlm_rx_fc_send_state_0_sqmuxa_0), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_fc_req_npd[8]), + .Q(com_tlm_u_tlm_rx_fc_src_npd[8]) + ); + FDE com_tlm_u_tlm_rx_fc_src_npd_7_ ( + .CE(com_tlm_u_tlm_rx_fc_send_state_0_sqmuxa_0), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_fc_req_npd[7]), + .Q(com_tlm_u_tlm_rx_fc_src_npd[7]) + ); + FDE com_tlm_u_tlm_rx_fc_src_npd_6_ ( + .CE(com_tlm_u_tlm_rx_fc_send_state_0_sqmuxa_0), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_fc_req_npd[6]), + .Q(com_tlm_u_tlm_rx_fc_src_npd[6]) + ); + FDE com_tlm_u_tlm_rx_fc_src_npd_5_ ( + .CE(com_tlm_u_tlm_rx_fc_send_state_0_sqmuxa_0), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_fc_req_npd[5]), + .Q(com_tlm_u_tlm_rx_fc_src_npd[5]) + ); + FDE com_tlm_u_tlm_rx_fc_src_npd_4_ ( + .CE(com_tlm_u_tlm_rx_fc_send_state_0_sqmuxa_0), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_fc_req_npd[4]), + .Q(com_tlm_u_tlm_rx_fc_src_npd[4]) + ); + FDE com_tlm_u_tlm_rx_fc_src_npd_3_ ( + .CE(com_tlm_u_tlm_rx_fc_send_state_0_sqmuxa_0), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_fc_req_npd[3]), + .Q(com_tlm_u_tlm_rx_fc_src_npd[3]) + ); + FDE com_tlm_u_tlm_rx_fc_src_npd_2_ ( + .CE(com_tlm_u_tlm_rx_fc_send_state_0_sqmuxa_0), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_fc_req_npd[2]), + .Q(com_tlm_u_tlm_rx_fc_src_npd[2]) + ); + FDE com_tlm_u_tlm_rx_fc_src_npd_1_ ( + .CE(com_tlm_u_tlm_rx_fc_send_state_0_sqmuxa_0), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_fc_req_npd[1]), + .Q(com_tlm_u_tlm_rx_fc_src_npd[1]) + ); + FDE com_tlm_u_tlm_rx_fc_src_npd_0_ ( + .CE(com_tlm_u_tlm_rx_fc_send_state_0_sqmuxa_0), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_fc_req_npd[0]), + .Q(com_tlm_u_tlm_rx_fc_src_npd[0]) + ); + FDE com_tlm_u_tlm_rx_fc_src_nph_7_ ( + .CE(com_tlm_u_tlm_rx_fc_send_state_0_sqmuxa_0), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_fc_req_nph[7]), + .Q(com_tlm_u_tlm_rx_fc_src_nph[7]) + ); + FDE com_tlm_u_tlm_rx_fc_src_nph_6_ ( + .CE(com_tlm_u_tlm_rx_fc_send_state_0_sqmuxa_0), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_fc_req_nph[6]), + .Q(com_tlm_u_tlm_rx_fc_src_nph[6]) + ); + FDE com_tlm_u_tlm_rx_fc_src_nph_5_ ( + .CE(com_tlm_u_tlm_rx_fc_send_state_0_sqmuxa_0), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_fc_req_nph[5]), + .Q(com_tlm_u_tlm_rx_fc_src_nph[5]) + ); + FDE com_tlm_u_tlm_rx_fc_src_nph_4_ ( + .CE(com_tlm_u_tlm_rx_fc_send_state_0_sqmuxa_0), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_fc_req_nph[4]), + .Q(com_tlm_u_tlm_rx_fc_src_nph[4]) + ); + FDE com_tlm_u_tlm_rx_fc_src_nph_3_ ( + .CE(com_tlm_u_tlm_rx_fc_send_state_0_sqmuxa_0), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_fc_req_nph[3]), + .Q(com_tlm_u_tlm_rx_fc_src_nph[3]) + ); + FDE com_tlm_u_tlm_rx_fc_src_nph_2_ ( + .CE(com_tlm_u_tlm_rx_fc_send_state_0_sqmuxa_0), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_fc_req_nph[2]), + .Q(com_tlm_u_tlm_rx_fc_src_nph[2]) + ); + FDE com_tlm_u_tlm_rx_fc_src_nph_1_ ( + .CE(com_tlm_u_tlm_rx_fc_send_state_0_sqmuxa_0), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_fc_req_nph[1]), + .Q(com_tlm_u_tlm_rx_fc_src_nph[1]) + ); + FDE com_tlm_u_tlm_rx_fc_src_nph_0_ ( + .CE(com_tlm_u_tlm_rx_fc_send_state_0_sqmuxa_0), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_fc_req_nph[0]), + .Q(com_tlm_u_tlm_rx_fc_src_nph[0]) + ); + FDE com_tlm_u_tlm_rx_fc_src_lnk_tfc_data_o_1_11_ ( + .CE(com_tlm_u_tlm_rx_fc_src_N_42600_i_4282), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_fc_src_N_12919_i), + .Q(com_lnk_tfc_data[11]) + ); + FDE com_tlm_u_tlm_rx_fc_src_lnk_tfc_data_o_1_10_ ( + .CE(com_tlm_u_tlm_rx_fc_src_N_42600_i_4282), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_fc_src_N_12917_i), + .Q(com_lnk_tfc_data[10]) + ); + FDE com_tlm_u_tlm_rx_fc_src_lnk_tfc_data_o_1_9_ ( + .CE(com_tlm_u_tlm_rx_fc_src_N_42600_i_4282), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_fc_src_N_12915_i), + .Q(com_lnk_tfc_data[9]) + ); + FDE com_tlm_u_tlm_rx_fc_src_lnk_tfc_data_o_1_8_ ( + .CE(com_tlm_u_tlm_rx_fc_src_N_42600_i_4282), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_fc_src_N_12913_i), + .Q(com_lnk_tfc_data[8]) + ); + FDE com_tlm_u_tlm_rx_fc_src_lnk_tfc_data_o_1_7_ ( + .CE(com_tlm_u_tlm_rx_fc_src_N_42600_i_4282), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_fc_src_N_12911_i), + .Q(com_lnk_tfc_data[7]) + ); + FDE com_tlm_u_tlm_rx_fc_src_lnk_tfc_data_o_1_6_ ( + .CE(com_tlm_u_tlm_rx_fc_src_N_42600_i_4282), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_fc_src_N_12909_i), + .Q(com_lnk_tfc_data[6]) + ); + FDE com_tlm_u_tlm_rx_fc_src_lnk_tfc_data_o_1_5_ ( + .CE(com_tlm_u_tlm_rx_fc_src_N_42600_i_4282), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_fc_src_N_12907_i), + .Q(com_lnk_tfc_data[5]) + ); + FDE com_tlm_u_tlm_rx_fc_src_lnk_tfc_data_o_1_4_ ( + .CE(com_tlm_u_tlm_rx_fc_src_N_42600_i_4282), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_fc_src_N_12905_i), + .Q(com_lnk_tfc_data[4]) + ); + FDE com_tlm_u_tlm_rx_fc_src_lnk_tfc_data_o_1_3_ ( + .CE(com_tlm_u_tlm_rx_fc_src_N_42600_i_4282), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_fc_src_N_12903_i), + .Q(com_lnk_tfc_data[3]) + ); + FDE com_tlm_u_tlm_rx_fc_src_lnk_tfc_data_o_1_2_ ( + .CE(com_tlm_u_tlm_rx_fc_src_N_42600_i_4282), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_fc_src_N_12901_i), + .Q(com_lnk_tfc_data[2]) + ); + FDE com_tlm_u_tlm_rx_fc_src_lnk_tfc_data_o_1_1_ ( + .CE(com_tlm_u_tlm_rx_fc_src_N_42600_i_4282), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_fc_src_N_12899_i), + .Q(com_lnk_tfc_data[1]) + ); + FDE com_tlm_u_tlm_rx_fc_src_lnk_tfc_data_o_1_0_ ( + .CE(com_tlm_u_tlm_rx_fc_src_N_42600_i_4282), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_fc_src_N_12897_i), + .Q(com_lnk_tfc_data[0]) + ); + FDE com_tlm_u_tlm_rx_fc_src_lnk_tfc_header_o_1_7_ ( + .CE(com_tlm_u_tlm_rx_fc_src_N_42600_i_4282), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_fc_src_N_34413_i), + .Q(com_lnk_tfc_header[7]) + ); + FDE com_tlm_u_tlm_rx_fc_src_lnk_tfc_header_o_1_6_ ( + .CE(com_tlm_u_tlm_rx_fc_src_N_42600_i_4282), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_fc_src_N_12930_i), + .Q(com_lnk_tfc_header[6]) + ); + FDE com_tlm_u_tlm_rx_fc_src_lnk_tfc_header_o_1_5_ ( + .CE(com_tlm_u_tlm_rx_fc_src_N_42600_i_4282), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_fc_src_N_12928_i), + .Q(com_lnk_tfc_header[5]) + ); + FDE com_tlm_u_tlm_rx_fc_src_lnk_tfc_header_o_1_4_ ( + .CE(com_tlm_u_tlm_rx_fc_src_N_42600_i_4282), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_fc_src_N_34411_i), + .Q(com_lnk_tfc_header[4]) + ); + FDE com_tlm_u_tlm_rx_fc_src_lnk_tfc_header_o_1_3_ ( + .CE(com_tlm_u_tlm_rx_fc_src_N_42600_i_4282), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_fc_src_N_34409_i), + .Q(com_lnk_tfc_header[3]) + ); + FDE com_tlm_u_tlm_rx_fc_src_lnk_tfc_header_o_1_2_ ( + .CE(com_tlm_u_tlm_rx_fc_src_N_42600_i_4282), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_fc_src_N_34407_i), + .Q(com_lnk_tfc_header[2]) + ); + FDE com_tlm_u_tlm_rx_fc_src_lnk_tfc_header_o_1_1_ ( + .CE(com_tlm_u_tlm_rx_fc_src_N_42600_i_4282), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_fc_src_N_12923_i), + .Q(com_lnk_tfc_header[1]) + ); + FDE com_tlm_u_tlm_rx_fc_src_lnk_tfc_header_o_1_0_ ( + .CE(com_tlm_u_tlm_rx_fc_src_N_42600_i_4282), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_fc_src_N_12921_i), + .Q(com_lnk_tfc_header[0]) + ); + FDE com_tlm_u_tlm_rx_fc_src_lnk_tfc_type_o_1_3_ ( + .CE(com_tlm_u_tlm_rx_fc_src_N_42600_i_4282), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_fc_src_un1_initFC_st_2_0_a2_0_a2_0_a2_4279), + .Q(com_lnk_tfc_type[3]) + ); + FDE com_tlm_u_tlm_rx_fc_src_lnk_tfc_type_o_1_2_ ( + .CE(com_tlm_u_tlm_rx_fc_src_N_42600_i_4282), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_fc_src_initFC_st_i[0]), + .Q(com_lnk_tfc_type[2]) + ); + FDE com_tlm_u_tlm_rx_fc_src_lnk_tfc_type_o_1_1_ ( + .CE(com_tlm_u_tlm_rx_fc_src_N_42600_i_4282), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_fc_src_N_41729_i_i_4280), + .Q(com_lnk_tfc_type[1]) + ); + FDE com_tlm_u_tlm_rx_fc_src_lnk_tfc_type_o_1_0_ ( + .CE(com_tlm_u_tlm_rx_fc_src_N_42600_i_4282), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_fc_src_N_68992_i_4281), + .Q(com_lnk_tfc_type[0]) + ); + INV com_tlm_u_tlm_rx_fc_src_initFC_st_i_0_ ( + .I(com_tlm_u_tlm_rx_fc_src_initFC_st[0]), + .O(com_tlm_u_tlm_rx_fc_src_initFC_st_i[0]) + ); + INV com_tlm_u_tlm_rx_fc_src_N_42600_i ( + .I(com_tlm_u_tlm_rx_fc_src_N_42600), + .O(com_tlm_u_tlm_rx_fc_src_N_42600_i_4282) + ); + VCC com_cmm_VCC ( + .P(com_cmm_VCC_4283) + ); + GND com_cmm_GND ( + .G(com_cmm_GND_4284) + ); + FDS com_cmm_rst ( + .C(NlwRenamedSig_OI_trn_clk), + .D(trn_reset_n_i), + .Q(com_cmm_rst_267), + .S(plm_link_up_i) + ); + INV com_cmm_rst_i ( + .I(com_cmm_rst_267), + .O(com_cmm_rst_i_4285) + ); + INV com_cmm_cfg_intr_rdy_i ( + .I(com_cmm_cfg_intr_rdy), + .O(cfg_interrupt_rdy_n) + ); + VCC com_cmm_u_cmm_intr_VCC ( + .P(com_cmm_u_cmm_intr_VCC_4309) + ); + GND com_cmm_u_cmm_intr_GND ( + .G(com_cmm_u_cmm_intr_GND_4308) + ); + MUXCY_L com_cmm_u_cmm_intr_un5_msi_64_0 ( + .CI(com_cmm_u_cmm_intr_VCC_4309), + .DI(com_cmm_u_cmm_intr_GND_4308), + .LO(com_cmm_u_cmm_intr_un5_msi_64_0_4286), + .S(com_cmm_u_cmm_intr_un5_msi_64_0_and_4307) + ); + MUXCY_L com_cmm_u_cmm_intr_un5_msi_64_1 ( + .CI(com_cmm_u_cmm_intr_un5_msi_64_0_4286), + .DI(com_cmm_u_cmm_intr_GND_4308), + .LO(com_cmm_u_cmm_intr_un5_msi_64_1_4287), + .S(com_cmm_u_cmm_intr_un5_msi_64_1_and_4306) + ); + MUXCY_L com_cmm_u_cmm_intr_un5_msi_64_2 ( + .CI(com_cmm_u_cmm_intr_un5_msi_64_1_4287), + .DI(com_cmm_u_cmm_intr_GND_4308), + .LO(com_cmm_u_cmm_intr_un5_msi_64_2_4288), + .S(com_cmm_u_cmm_intr_un5_msi_64_2_and_4305) + ); + MUXCY_L com_cmm_u_cmm_intr_un5_msi_64_3 ( + .CI(com_cmm_u_cmm_intr_un5_msi_64_2_4288), + .DI(com_cmm_u_cmm_intr_GND_4308), + .LO(com_cmm_u_cmm_intr_un5_msi_64_3_4289), + .S(com_cmm_u_cmm_intr_un5_msi_64_3_and_4304) + ); + MUXCY_L com_cmm_u_cmm_intr_un5_msi_64_4 ( + .CI(com_cmm_u_cmm_intr_un5_msi_64_3_4289), + .DI(com_cmm_u_cmm_intr_GND_4308), + .LO(com_cmm_u_cmm_intr_un5_msi_64_4_4290), + .S(com_cmm_u_cmm_intr_un5_msi_64_4_and_4303) + ); + MUXCY_L com_cmm_u_cmm_intr_un5_msi_64_5 ( + .CI(com_cmm_u_cmm_intr_un5_msi_64_4_4290), + .DI(com_cmm_u_cmm_intr_GND_4308), + .LO(com_cmm_u_cmm_intr_un5_msi_64_5_4291), + .S(com_cmm_u_cmm_intr_un5_msi_64_5_and_4302) + ); + MUXCY_L com_cmm_u_cmm_intr_un5_msi_64_6 ( + .CI(com_cmm_u_cmm_intr_un5_msi_64_5_4291), + .DI(com_cmm_u_cmm_intr_GND_4308), + .LO(com_cmm_u_cmm_intr_un5_msi_64_6_4292), + .S(com_cmm_u_cmm_intr_un5_msi_64_6_and_4301) + ); + MUXCY com_cmm_u_cmm_intr_un5_msi_64_7 ( + .CI(com_cmm_u_cmm_intr_un5_msi_64_6_4292), + .DI(com_cmm_u_cmm_intr_GND_4308), + .O(com_cmm_u_cmm_intr_un5_msi_64_7_4293), + .S(com_cmm_u_cmm_intr_un5_msi_64_7_and_4300) + ); + defparam com_cmm_u_cmm_intr_signaledint_0_a2.INIT = 4'h8; + LUT2 com_cmm_u_cmm_intr_signaledint_0_a2 ( + .I0(com_cmm_gnt_intr), + .I1(com_cmm_u_cmm_intr_state[2]), + .O(com_cmm_signaledint) + ); + defparam com_cmm_u_cmm_intr_un1_intr_rdy_0_a2.INIT = 4'h4; + LUT2 com_cmm_u_cmm_intr_un1_intr_rdy_0_a2 ( + .I0(com_cmm_req_intr), + .I1(com_cmm_u_cmm_intr_state[0]), + .O(com_cmm_cfg_intr_rdy) + ); + defparam com_cmm_u_cmm_intr_next_state_0_i_a2_0_1_3_.INIT = 4'h8; + LUT2 com_cmm_u_cmm_intr_next_state_0_i_a2_0_1_3_ ( + .I0(com_cmm_u_cmm_intr_intr_req_q_4299), + .I1(com_cmm_u_cmm_intr_state[0]), + .O(com_cmm_u_cmm_intr_N_149_1) + ); + defparam com_cmm_u_cmm_intr_next_state_0_i_a2_0_0_2_.INIT = 4'h4; + LUT2 com_cmm_u_cmm_intr_next_state_0_i_a2_0_0_2_ ( + .I0(com_cmm_u_cmm_intr_intr_req_q_4299), + .I1(com_cmm_u_cmm_intr_state[0]), + .O(com_cmm_u_cmm_intr_next_state_0_i_a2_0_0[2]) + ); + defparam com_cmm_u_cmm_intr_next_state_i_m3_i_o2_0_.INIT = 8'h01; + LUT3 com_cmm_u_cmm_intr_next_state_i_m3_i_o2_0_ ( + .I0(com_cmm_u_cmm_intr_state[1]), + .I1(com_cmm_u_cmm_intr_state[2]), + .I2(com_cmm_u_cmm_intr_state[3]), + .O(com_cmm_u_cmm_intr_next_state_i_m3_i_o2[0]) + ); + defparam com_cmm_u_cmm_intr_next_state_0_i_a2_0_0_3_.INIT = 4'h2; + LUT2 com_cmm_u_cmm_intr_next_state_0_i_a2_0_0_3_ ( + .I0(com_cmm_u_cmm_intr_N_149_1), + .I1(com_cmm_msi_control_1[0]), + .O(com_cmm_u_cmm_intr_next_state_0_i_a2_0_0[3]) + ); + defparam com_cmm_u_cmm_intr_intr_req.INIT = 16'h4405; + LUT4 com_cmm_u_cmm_intr_intr_req ( + .I0(cfg_interrupt_n), + .I1(NlwRenamedSig_OI_cfg_command_2_), + .I2(NlwRenamedSig_OI_cfg_command_10_), + .I3(com_cmm_msi_control_1[0]), + .O(com_cmm_u_cmm_intr_intr_req_4298) + ); + defparam com_cmm_u_cmm_intr_next_state_i_m3_i_o2_0_0_.INIT = 4'h2; + LUT2 com_cmm_u_cmm_intr_next_state_i_m3_i_o2_0_0_ ( + .I0(com_cmm_u_cmm_intr_intr_req_4298), + .I1(com_cmm_msi_control_1[0]), + .O(com_cmm_u_cmm_intr_N_139_i) + ); + defparam com_cmm_u_cmm_intr_state_i_0_.INIT = 4'h1; + LUT1_L com_cmm_u_cmm_intr_state_i_0_ ( + .I0(com_cmm_u_cmm_intr_state[0]), + .LO(com_cmm_u_cmm_intr_state_i[0]) + ); + defparam com_cmm_u_cmm_intr_N_264_i.INIT = 16'h7530; + LUT4_L com_cmm_u_cmm_intr_N_264_i ( + .I0(com_cmm_gnt_intr), + .I1(com_cmm_u_cmm_intr_intr_req_4298), + .I2(com_cmm_u_cmm_intr_next_state_0_i_a2_0_0[3]), + .I3(com_cmm_u_cmm_intr_state[3]), + .LO(com_cmm_u_cmm_intr_N_264_i_4294) + ); + defparam com_cmm_u_cmm_intr_N_263_i.INIT = 16'hB3A0; + LUT4_L com_cmm_u_cmm_intr_N_263_i ( + .I0(com_cmm_u_cmm_intr_N_139_i), + .I1(com_cmm_gnt_intr), + .I2(com_cmm_u_cmm_intr_next_state_0_i_a2_0_0[2]), + .I3(com_cmm_u_cmm_intr_state[2]), + .LO(com_cmm_u_cmm_intr_N_263_i_4295) + ); + defparam com_cmm_u_cmm_intr_N_262_i.INIT = 16'hB3A0; + LUT4_L com_cmm_u_cmm_intr_N_262_i ( + .I0(com_cmm_u_cmm_intr_N_149_1), + .I1(com_cmm_gnt_intr), + .I2(com_cmm_msi_control_1[0]), + .I3(com_cmm_u_cmm_intr_state[1]), + .LO(com_cmm_u_cmm_intr_N_262_i_4296) + ); + defparam com_cmm_u_cmm_intr_next_state_i_m3_i_m2_0_.INIT = 16'hB874; + LUT4_L com_cmm_u_cmm_intr_next_state_i_m3_i_m2_0_ ( + .I0(com_cmm_u_cmm_intr_N_139_i), + .I1(com_cmm_u_cmm_intr_next_state_i_m3_i_o2[0]), + .I2(com_cmm_gnt_intr), + .I3(com_cmm_u_cmm_intr_intr_req_q_4299), + .LO(com_cmm_u_cmm_intr_next_state_i_m3_i_m2[0]) + ); + defparam com_cmm_u_cmm_intr_N_265_i.INIT = 16'hF0F8; + LUT4_L com_cmm_u_cmm_intr_N_265_i ( + .I0(com_cmm_VCC_4283), + .I1(com_cmm_u_cmm_intr_state[1]), + .I2(com_cmm_u_cmm_intr_state[3]), + .I3(com_cmm_u_cmm_intr_un5_msi_64_7_4293), + .LO(com_cmm_u_cmm_intr_N_265_i_4297) + ); + FDC com_cmm_u_cmm_intr_intr_req_valid ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_intr_state_i[0]), + .Q(com_cmm_req_intr), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_intr_state_3_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_intr_N_264_i_4294), + .Q(com_cmm_u_cmm_intr_state[3]), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_intr_state_2_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_intr_N_263_i_4295), + .Q(com_cmm_u_cmm_intr_state[2]), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_intr_state_1_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_intr_N_262_i_4296), + .Q(com_cmm_u_cmm_intr_state[1]), + .CLR(com_cmm_rst_267) + ); + FDP com_cmm_u_cmm_intr_state_0_ ( + .PRE(com_cmm_rst_267), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_intr_next_state_i_m3_i_m2[0]), + .Q(com_cmm_u_cmm_intr_state[0]) + ); + FDC com_cmm_u_cmm_intr_intr_req_type_1_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_intr_state[1]), + .Q(com_cmm_intr_req_type[1]), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_intr_intr_req_type_0_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_intr_N_265_i_4297), + .Q(com_cmm_intr_req_type[0]), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_intr_intr_req_q ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_intr_intr_req_4298), + .Q(com_cmm_u_cmm_intr_intr_req_q_4299), + .CLR(com_cmm_rst_267) + ); + defparam com_cmm_u_cmm_intr_un5_msi_64_7_and.INIT = 16'h0001; + LUT4 com_cmm_u_cmm_intr_un5_msi_64_7_and ( + .I0(com_cmm_msi_haddr[28]), + .I1(com_cmm_msi_haddr[29]), + .I2(com_cmm_msi_haddr[30]), + .I3(com_cmm_msi_haddr[31]), + .O(com_cmm_u_cmm_intr_un5_msi_64_7_and_4300) + ); + defparam com_cmm_u_cmm_intr_un5_msi_64_6_and.INIT = 16'h0001; + LUT4 com_cmm_u_cmm_intr_un5_msi_64_6_and ( + .I0(com_cmm_msi_haddr[24]), + .I1(com_cmm_msi_haddr[25]), + .I2(com_cmm_msi_haddr[26]), + .I3(com_cmm_msi_haddr[27]), + .O(com_cmm_u_cmm_intr_un5_msi_64_6_and_4301) + ); + defparam com_cmm_u_cmm_intr_un5_msi_64_5_and.INIT = 16'h0001; + LUT4 com_cmm_u_cmm_intr_un5_msi_64_5_and ( + .I0(com_cmm_msi_haddr[20]), + .I1(com_cmm_msi_haddr[21]), + .I2(com_cmm_msi_haddr[22]), + .I3(com_cmm_msi_haddr[23]), + .O(com_cmm_u_cmm_intr_un5_msi_64_5_and_4302) + ); + defparam com_cmm_u_cmm_intr_un5_msi_64_4_and.INIT = 16'h0001; + LUT4 com_cmm_u_cmm_intr_un5_msi_64_4_and ( + .I0(com_cmm_msi_haddr[16]), + .I1(com_cmm_msi_haddr[17]), + .I2(com_cmm_msi_haddr[18]), + .I3(com_cmm_msi_haddr[19]), + .O(com_cmm_u_cmm_intr_un5_msi_64_4_and_4303) + ); + defparam com_cmm_u_cmm_intr_un5_msi_64_3_and.INIT = 16'h0001; + LUT4 com_cmm_u_cmm_intr_un5_msi_64_3_and ( + .I0(com_cmm_msi_haddr[12]), + .I1(com_cmm_msi_haddr[13]), + .I2(com_cmm_msi_haddr[14]), + .I3(com_cmm_msi_haddr[15]), + .O(com_cmm_u_cmm_intr_un5_msi_64_3_and_4304) + ); + defparam com_cmm_u_cmm_intr_un5_msi_64_2_and.INIT = 16'h0001; + LUT4 com_cmm_u_cmm_intr_un5_msi_64_2_and ( + .I0(com_cmm_msi_haddr[8]), + .I1(com_cmm_msi_haddr[9]), + .I2(com_cmm_msi_haddr[10]), + .I3(com_cmm_msi_haddr[11]), + .O(com_cmm_u_cmm_intr_un5_msi_64_2_and_4305) + ); + defparam com_cmm_u_cmm_intr_un5_msi_64_1_and.INIT = 16'h0001; + LUT4 com_cmm_u_cmm_intr_un5_msi_64_1_and ( + .I0(com_cmm_msi_haddr[4]), + .I1(com_cmm_msi_haddr[5]), + .I2(com_cmm_msi_haddr[6]), + .I3(com_cmm_msi_haddr[7]), + .O(com_cmm_u_cmm_intr_un5_msi_64_1_and_4306) + ); + defparam com_cmm_u_cmm_intr_un5_msi_64_0_and.INIT = 16'h0001; + LUT4 com_cmm_u_cmm_intr_un5_msi_64_0_and ( + .I0(com_cmm_msi_haddr[0]), + .I1(com_cmm_msi_haddr[1]), + .I2(com_cmm_msi_haddr[2]), + .I3(com_cmm_msi_haddr[3]), + .O(com_cmm_u_cmm_intr_un5_msi_64_0_and_4307) + ); + FDRE com_cmm_u_rx_pkt_proc_bdf_err_rd_pack ( + .CE(com_cmm_u_rx_pkt_proc_dw1_enable), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_rx_pkt_proc_N_68201_i_4316), + .Q(com_cmm_bdf_err_rd_pack), + .R(com_cmm_rst_267) + ); + FDRE com_cmm_u_rx_pkt_proc_posnd_wr_pack ( + .CE(com_cmm_u_rx_pkt_proc_N_14881_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_rx_pkt_proc_N_68112_i_4314), + .Q(com_cmm_posnd_wr_pack), + .R(com_cmm_rst_267) + ); + FDRE com_cmm_u_rx_pkt_proc_device_0_ ( + .CE(com_cmm_u_rx_pkt_proc_un1_dw1_enable_2_0_a2_0_a2_0_a2_0_a2_4310), + .C(NlwRenamedSig_OI_trn_clk), + .D(NlwRenamedSig_OI_trn_rd[51]), + .Q(NlwRenamedSig_OI_cfg_device_number[0]), + .R(com_cmm_rst_267) + ); + FDRE com_cmm_u_rx_pkt_proc_device_1_ ( + .CE(com_cmm_u_rx_pkt_proc_un1_dw1_enable_2_0_a2_0_a2_0_a2_0_a2_4310), + .C(NlwRenamedSig_OI_trn_clk), + .D(NlwRenamedSig_OI_trn_rd[52]), + .Q(NlwRenamedSig_OI_cfg_device_number[1]), + .R(com_cmm_rst_267) + ); + FDRE com_cmm_u_rx_pkt_proc_device_2_ ( + .CE(com_cmm_u_rx_pkt_proc_un1_dw1_enable_2_0_a2_0_a2_0_a2_0_a2_4310), + .C(NlwRenamedSig_OI_trn_clk), + .D(NlwRenamedSig_OI_trn_rd[53]), + .Q(NlwRenamedSig_OI_cfg_device_number[2]), + .R(com_cmm_rst_267) + ); + FDRE com_cmm_u_rx_pkt_proc_device_3_ ( + .CE(com_cmm_u_rx_pkt_proc_un1_dw1_enable_2_0_a2_0_a2_0_a2_0_a2_4310), + .C(NlwRenamedSig_OI_trn_clk), + .D(NlwRenamedSig_OI_trn_rd[54]), + .Q(NlwRenamedSig_OI_cfg_device_number[3]), + .R(com_cmm_rst_267) + ); + FDRE com_cmm_u_rx_pkt_proc_device_4_ ( + .CE(com_cmm_u_rx_pkt_proc_un1_dw1_enable_2_0_a2_0_a2_0_a2_0_a2_4310), + .C(NlwRenamedSig_OI_trn_clk), + .D(NlwRenamedSig_OI_trn_rd[55]), + .Q(NlwRenamedSig_OI_cfg_device_number[4]), + .R(com_cmm_rst_267) + ); + FDRE com_cmm_u_rx_pkt_proc_bus_0_ ( + .CE(com_cmm_u_rx_pkt_proc_un1_dw1_enable_2_0_a2_0_a2_0_a2_0_a2_4310), + .C(NlwRenamedSig_OI_trn_clk), + .D(NlwRenamedSig_OI_trn_rd[56]), + .Q(NlwRenamedSig_OI_cfg_bus_number[0]), + .R(com_cmm_rst_267) + ); + FDRE com_cmm_u_rx_pkt_proc_bus_1_ ( + .CE(com_cmm_u_rx_pkt_proc_un1_dw1_enable_2_0_a2_0_a2_0_a2_0_a2_4310), + .C(NlwRenamedSig_OI_trn_clk), + .D(NlwRenamedSig_OI_trn_rd[57]), + .Q(NlwRenamedSig_OI_cfg_bus_number[1]), + .R(com_cmm_rst_267) + ); + FDRE com_cmm_u_rx_pkt_proc_bus_2_ ( + .CE(com_cmm_u_rx_pkt_proc_un1_dw1_enable_2_0_a2_0_a2_0_a2_0_a2_4310), + .C(NlwRenamedSig_OI_trn_clk), + .D(NlwRenamedSig_OI_trn_rd[58]), + .Q(NlwRenamedSig_OI_cfg_bus_number[2]), + .R(com_cmm_rst_267) + ); + FDRE com_cmm_u_rx_pkt_proc_bus_3_ ( + .CE(com_cmm_u_rx_pkt_proc_un1_dw1_enable_2_0_a2_0_a2_0_a2_0_a2_4310), + .C(NlwRenamedSig_OI_trn_clk), + .D(NlwRenamedSig_OI_trn_rd[59]), + .Q(NlwRenamedSig_OI_cfg_bus_number[3]), + .R(com_cmm_rst_267) + ); + FDRE com_cmm_u_rx_pkt_proc_bus_4_ ( + .CE(com_cmm_u_rx_pkt_proc_un1_dw1_enable_2_0_a2_0_a2_0_a2_0_a2_4310), + .C(NlwRenamedSig_OI_trn_clk), + .D(NlwRenamedSig_OI_trn_rd[60]), + .Q(NlwRenamedSig_OI_cfg_bus_number[4]), + .R(com_cmm_rst_267) + ); + FDRE com_cmm_u_rx_pkt_proc_bus_5_ ( + .CE(com_cmm_u_rx_pkt_proc_un1_dw1_enable_2_0_a2_0_a2_0_a2_0_a2_4310), + .C(NlwRenamedSig_OI_trn_clk), + .D(NlwRenamedSig_OI_trn_rd[61]), + .Q(NlwRenamedSig_OI_cfg_bus_number[5]), + .R(com_cmm_rst_267) + ); + FDRE com_cmm_u_rx_pkt_proc_bus_6_ ( + .CE(com_cmm_u_rx_pkt_proc_un1_dw1_enable_2_0_a2_0_a2_0_a2_0_a2_4310), + .C(NlwRenamedSig_OI_trn_clk), + .D(NlwRenamedSig_OI_trn_rd[62]), + .Q(NlwRenamedSig_OI_cfg_bus_number[6]), + .R(com_cmm_rst_267) + ); + FDRE com_cmm_u_rx_pkt_proc_bus_7_ ( + .CE(com_cmm_u_rx_pkt_proc_un1_dw1_enable_2_0_a2_0_a2_0_a2_0_a2_4310), + .C(NlwRenamedSig_OI_trn_clk), + .D(NlwRenamedSig_OI_trn_rd[63]), + .Q(NlwRenamedSig_OI_cfg_bus_number[7]), + .R(com_cmm_rst_267) + ); + FDRE com_cmm_u_rx_pkt_proc_type1_type0_bar ( + .CE(com_cmm_u_rx_pkt_proc_idle_enable), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_rx_pkt_proc_type1_type0_bar_3), + .Q(com_cmm_type1_type0_bar), + .R(com_cmm_rst_267) + ); + FDRE com_cmm_u_rx_pkt_proc_cfg_wr ( + .CE(com_cmm_u_rx_pkt_proc_idle_enable), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_rx_pkt_proc_cfg_wr_3), + .Q(com_cmm_cfg_wr), + .R(com_cmm_rst_267) + ); + FDRE com_cmm_u_rx_pkt_proc_cfg_rd ( + .CE(com_cmm_u_rx_pkt_proc_idle_enable), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_rx_pkt_proc_cfg_rd_3), + .Q(com_cmm_cfg_rd), + .R(com_cmm_rst_267) + ); + FDRE com_cmm_u_rx_pkt_proc_tag_0_ ( + .CE(com_cmm_u_rx_pkt_proc_idle_enable), + .C(NlwRenamedSig_OI_trn_clk), + .D(NlwRenamedSig_OI_trn_rd[8]), + .Q(com_cmm_tag[0]), + .R(com_cmm_rst_267) + ); + FDRE com_cmm_u_rx_pkt_proc_tag_1_ ( + .CE(com_cmm_u_rx_pkt_proc_idle_enable), + .C(NlwRenamedSig_OI_trn_clk), + .D(NlwRenamedSig_OI_trn_rd[9]), + .Q(com_cmm_tag[1]), + .R(com_cmm_rst_267) + ); + FDRE com_cmm_u_rx_pkt_proc_tag_2_ ( + .CE(com_cmm_u_rx_pkt_proc_idle_enable), + .C(NlwRenamedSig_OI_trn_clk), + .D(NlwRenamedSig_OI_trn_rd[10]), + .Q(com_cmm_tag[2]), + .R(com_cmm_rst_267) + ); + FDRE com_cmm_u_rx_pkt_proc_tag_3_ ( + .CE(com_cmm_u_rx_pkt_proc_idle_enable), + .C(NlwRenamedSig_OI_trn_clk), + .D(NlwRenamedSig_OI_trn_rd[11]), + .Q(com_cmm_tag[3]), + .R(com_cmm_rst_267) + ); + FDRE com_cmm_u_rx_pkt_proc_tag_4_ ( + .CE(com_cmm_u_rx_pkt_proc_idle_enable), + .C(NlwRenamedSig_OI_trn_clk), + .D(NlwRenamedSig_OI_trn_rd[12]), + .Q(com_cmm_tag[4]), + .R(com_cmm_rst_267) + ); + FDRE com_cmm_u_rx_pkt_proc_tag_5_ ( + .CE(com_cmm_u_rx_pkt_proc_idle_enable), + .C(NlwRenamedSig_OI_trn_clk), + .D(NlwRenamedSig_OI_trn_rd[13]), + .Q(com_cmm_tag[5]), + .R(com_cmm_rst_267) + ); + FDRE com_cmm_u_rx_pkt_proc_tag_6_ ( + .CE(com_cmm_u_rx_pkt_proc_idle_enable), + .C(NlwRenamedSig_OI_trn_clk), + .D(NlwRenamedSig_OI_trn_rd[14]), + .Q(com_cmm_tag[6]), + .R(com_cmm_rst_267) + ); + FDRE com_cmm_u_rx_pkt_proc_tag_7_ ( + .CE(com_cmm_u_rx_pkt_proc_idle_enable), + .C(NlwRenamedSig_OI_trn_clk), + .D(NlwRenamedSig_OI_trn_rd[15]), + .Q(com_cmm_tag[7]), + .R(com_cmm_rst_267) + ); + FDRE com_cmm_u_rx_pkt_proc_req_id_0_ ( + .CE(com_cmm_u_rx_pkt_proc_idle_enable), + .C(NlwRenamedSig_OI_trn_clk), + .D(NlwRenamedSig_OI_trn_rd[16]), + .Q(com_cmm_req_id[0]), + .R(com_cmm_rst_267) + ); + FDRE com_cmm_u_rx_pkt_proc_req_id_1_ ( + .CE(com_cmm_u_rx_pkt_proc_idle_enable), + .C(NlwRenamedSig_OI_trn_clk), + .D(NlwRenamedSig_OI_trn_rd[17]), + .Q(com_cmm_req_id[1]), + .R(com_cmm_rst_267) + ); + FDRE com_cmm_u_rx_pkt_proc_req_id_2_ ( + .CE(com_cmm_u_rx_pkt_proc_idle_enable), + .C(NlwRenamedSig_OI_trn_clk), + .D(NlwRenamedSig_OI_trn_rd[18]), + .Q(com_cmm_req_id[2]), + .R(com_cmm_rst_267) + ); + FDRE com_cmm_u_rx_pkt_proc_req_id_3_ ( + .CE(com_cmm_u_rx_pkt_proc_idle_enable), + .C(NlwRenamedSig_OI_trn_clk), + .D(NlwRenamedSig_OI_trn_rd[19]), + .Q(com_cmm_req_id[3]), + .R(com_cmm_rst_267) + ); + FDRE com_cmm_u_rx_pkt_proc_req_id_4_ ( + .CE(com_cmm_u_rx_pkt_proc_idle_enable), + .C(NlwRenamedSig_OI_trn_clk), + .D(NlwRenamedSig_OI_trn_rd[20]), + .Q(com_cmm_req_id[4]), + .R(com_cmm_rst_267) + ); + FDRE com_cmm_u_rx_pkt_proc_req_id_5_ ( + .CE(com_cmm_u_rx_pkt_proc_idle_enable), + .C(NlwRenamedSig_OI_trn_clk), + .D(NlwRenamedSig_OI_trn_rd[21]), + .Q(com_cmm_req_id[5]), + .R(com_cmm_rst_267) + ); + FDRE com_cmm_u_rx_pkt_proc_req_id_6_ ( + .CE(com_cmm_u_rx_pkt_proc_idle_enable), + .C(NlwRenamedSig_OI_trn_clk), + .D(NlwRenamedSig_OI_trn_rd[22]), + .Q(com_cmm_req_id[6]), + .R(com_cmm_rst_267) + ); + FDRE com_cmm_u_rx_pkt_proc_req_id_7_ ( + .CE(com_cmm_u_rx_pkt_proc_idle_enable), + .C(NlwRenamedSig_OI_trn_clk), + .D(NlwRenamedSig_OI_trn_rd[23]), + .Q(com_cmm_req_id[7]), + .R(com_cmm_rst_267) + ); + FDRE com_cmm_u_rx_pkt_proc_req_id_8_ ( + .CE(com_cmm_u_rx_pkt_proc_idle_enable), + .C(NlwRenamedSig_OI_trn_clk), + .D(NlwRenamedSig_OI_trn_rd[24]), + .Q(com_cmm_req_id[8]), + .R(com_cmm_rst_267) + ); + FDRE com_cmm_u_rx_pkt_proc_req_id_9_ ( + .CE(com_cmm_u_rx_pkt_proc_idle_enable), + .C(NlwRenamedSig_OI_trn_clk), + .D(NlwRenamedSig_OI_trn_rd[25]), + .Q(com_cmm_req_id[9]), + .R(com_cmm_rst_267) + ); + FDRE com_cmm_u_rx_pkt_proc_req_id_10_ ( + .CE(com_cmm_u_rx_pkt_proc_idle_enable), + .C(NlwRenamedSig_OI_trn_clk), + .D(NlwRenamedSig_OI_trn_rd[26]), + .Q(com_cmm_req_id[10]), + .R(com_cmm_rst_267) + ); + FDRE com_cmm_u_rx_pkt_proc_req_id_11_ ( + .CE(com_cmm_u_rx_pkt_proc_idle_enable), + .C(NlwRenamedSig_OI_trn_clk), + .D(NlwRenamedSig_OI_trn_rd[27]), + .Q(com_cmm_req_id[11]), + .R(com_cmm_rst_267) + ); + FDRE com_cmm_u_rx_pkt_proc_req_id_12_ ( + .CE(com_cmm_u_rx_pkt_proc_idle_enable), + .C(NlwRenamedSig_OI_trn_clk), + .D(NlwRenamedSig_OI_trn_rd[28]), + .Q(com_cmm_req_id[12]), + .R(com_cmm_rst_267) + ); + FDRE com_cmm_u_rx_pkt_proc_req_id_13_ ( + .CE(com_cmm_u_rx_pkt_proc_idle_enable), + .C(NlwRenamedSig_OI_trn_clk), + .D(NlwRenamedSig_OI_trn_rd[29]), + .Q(com_cmm_req_id[13]), + .R(com_cmm_rst_267) + ); + FDRE com_cmm_u_rx_pkt_proc_req_id_14_ ( + .CE(com_cmm_u_rx_pkt_proc_idle_enable), + .C(NlwRenamedSig_OI_trn_clk), + .D(NlwRenamedSig_OI_trn_rd[30]), + .Q(com_cmm_req_id[14]), + .R(com_cmm_rst_267) + ); + FDRE com_cmm_u_rx_pkt_proc_req_id_15_ ( + .CE(com_cmm_u_rx_pkt_proc_idle_enable), + .C(NlwRenamedSig_OI_trn_clk), + .D(NlwRenamedSig_OI_trn_rd[31]), + .Q(com_cmm_req_id[15]), + .R(com_cmm_rst_267) + ); + FDRE com_cmm_u_rx_pkt_proc_cfg_be_0_ ( + .CE(com_cmm_u_rx_pkt_proc_idle_enable), + .C(NlwRenamedSig_OI_trn_clk), + .D(NlwRenamedSig_OI_trn_rd[0]), + .Q(com_cmm_cfg_be[0]), + .R(com_cmm_rst_267) + ); + FDRE com_cmm_u_rx_pkt_proc_cfg_be_1_ ( + .CE(com_cmm_u_rx_pkt_proc_idle_enable), + .C(NlwRenamedSig_OI_trn_clk), + .D(NlwRenamedSig_OI_trn_rd[1]), + .Q(com_cmm_cfg_be[1]), + .R(com_cmm_rst_267) + ); + FDRE com_cmm_u_rx_pkt_proc_cfg_be_2_ ( + .CE(com_cmm_u_rx_pkt_proc_idle_enable), + .C(NlwRenamedSig_OI_trn_clk), + .D(NlwRenamedSig_OI_trn_rd[2]), + .Q(com_cmm_cfg_be[2]), + .R(com_cmm_rst_267) + ); + FDRE com_cmm_u_rx_pkt_proc_cfg_be_3_ ( + .CE(com_cmm_u_rx_pkt_proc_idle_enable), + .C(NlwRenamedSig_OI_trn_clk), + .D(NlwRenamedSig_OI_trn_rd[3]), + .Q(com_cmm_cfg_be[3]), + .R(com_cmm_rst_267) + ); + FDRE com_cmm_u_rx_pkt_proc_attr_0_ ( + .CE(com_cmm_u_rx_pkt_proc_idle_enable), + .C(NlwRenamedSig_OI_trn_clk), + .D(NlwRenamedSig_OI_trn_rd[44]), + .Q(com_cmm_attr[0]), + .R(com_cmm_rst_267) + ); + FDRE com_cmm_u_rx_pkt_proc_attr_1_ ( + .CE(com_cmm_u_rx_pkt_proc_idle_enable), + .C(NlwRenamedSig_OI_trn_clk), + .D(NlwRenamedSig_OI_trn_rd[45]), + .Q(com_cmm_attr[1]), + .R(com_cmm_rst_267) + ); + FDRE com_cmm_u_rx_pkt_proc_ecrc ( + .CE(com_cmmt_rsrc_rdy), + .C(NlwRenamedSig_OI_trn_clk), + .D(NlwRenamedSig_OI_trn_rd[47]), + .Q(com_cmm_u_rx_pkt_proc_ecrc_4313), + .R(com_cmm_rst_267) + ); + defparam com_cmm_u_rx_pkt_proc_dw1_enable_0_a3_0_a2_0_a2.INIT = 4'h8; + LUT2 com_cmm_u_rx_pkt_proc_dw1_enable_0_a3_0_a2_0_a2 ( + .I0(com_cmm_u_rx_pkt_proc_state[1]), + .I1(com_cmmt_rsrc_rdy), + .O(com_cmm_u_rx_pkt_proc_dw1_enable) + ); + defparam com_cmm_u_rx_pkt_proc_nxt_req_valid_iv_i_0_0_o4.INIT = 4'h8; + LUT2 com_cmm_u_rx_pkt_proc_nxt_req_valid_iv_i_0_0_o4 ( + .I0(com_cmm_gnt_cfgctrl), + .I1(com_cmm_req_cfgctrl), + .O(com_cmm_N_41751_i) + ); + defparam com_cmm_u_rx_pkt_proc_idle_enable_0_a2_0_a2_0_a2.INIT = 4'h8; + LUT2 com_cmm_u_rx_pkt_proc_idle_enable_0_a2_0_a2_0_a2 ( + .I0(com_cmm_u_rx_pkt_proc_state[0]), + .I1(com_cmmt_rsrc_rdy), + .O(com_cmm_u_rx_pkt_proc_idle_enable) + ); + defparam com_cmm_u_rx_pkt_proc_un1_dw1_enable_2_0_a2_0_a2_0_a2_0_o3.INIT = 4'h2; + LUT2 com_cmm_u_rx_pkt_proc_un1_dw1_enable_2_0_a2_0_a2_0_a2_0_o3 ( + .I0(com_cmm_cfg_wr), + .I1(com_cmm_posnd_wr_pack), + .O(com_cmm_N_48846_i) + ); + defparam com_cmm_u_rx_pkt_proc_bdf_err_rd_pack_3_i_o3_0.INIT = 4'h1; + LUT2_L com_cmm_u_rx_pkt_proc_bdf_err_rd_pack_3_i_o3_0 ( + .I0(NlwRenamedSig_OI_trn_rd[32]), + .I1(NlwRenamedSig_OI_trn_rd[33]), + .LO(com_cmm_u_rx_pkt_proc_bdf_err_rd_pack_3_i_o3_0_4311) + ); + defparam com_cmm_u_rx_pkt_proc_nxt_req_valid_iv_i_0_0_a2.INIT = 8'h70; + LUT3 com_cmm_u_rx_pkt_proc_nxt_req_valid_iv_i_0_0_a2 ( + .I0(com_cmm_cfg_wr), + .I1(com_cmm_u_rx_pkt_proc_ecrc_4313), + .I2(com_cmm_u_rx_pkt_proc_state[1]), + .O(com_cmm_u_rx_pkt_proc_N_42531) + ); + defparam com_cmm_u_rx_pkt_proc_un1_cmmt_rsrc_rdy_n_1_i_0_0.INIT = 8'hE0; + LUT3 com_cmm_u_rx_pkt_proc_un1_cmmt_rsrc_rdy_n_1_i_0_0 ( + .I0(com_cmm_u_rx_pkt_proc_state[0]), + .I1(com_cmm_u_rx_pkt_proc_state[1]), + .I2(com_cmmt_rsrc_rdy), + .O(com_cmm_u_rx_pkt_proc_N_14881_i) + ); + defparam com_cmm_u_rx_pkt_proc_posnd_wr_pack_6_i_i_o2.INIT = 8'h01; + LUT3 com_cmm_u_rx_pkt_proc_posnd_wr_pack_6_i_i_o2 ( + .I0(NlwRenamedSig_OI_trn_rd[48]), + .I1(NlwRenamedSig_OI_trn_rd[49]), + .I2(NlwRenamedSig_OI_trn_rd[50]), + .O(com_cmm_u_rx_pkt_proc_N_32324_i) + ); + defparam com_cmm_u_rx_pkt_proc_bdf_err_rd_pack_3_i_0_o4_0.INIT = 16'h0001; + LUT4 com_cmm_u_rx_pkt_proc_bdf_err_rd_pack_3_i_0_o4_0 ( + .I0(NlwRenamedSig_OI_trn_rd[36]), + .I1(NlwRenamedSig_OI_trn_rd[37]), + .I2(NlwRenamedSig_OI_trn_rd[38]), + .I3(NlwRenamedSig_OI_trn_rd[39]), + .O(com_cmm_u_rx_pkt_proc_bdf_err_rd_pack_3_i_0_o4_0_4319) + ); + defparam com_cmm_u_rx_pkt_proc_cfg_rd_3_0_a2_0_a2_0_a2_2.INIT = 16'h0001; + LUT4 com_cmm_u_rx_pkt_proc_cfg_rd_3_0_a2_0_a2_0_a2_2 ( + .I0(NlwRenamedSig_OI_trn_rd[57]), + .I1(NlwRenamedSig_OI_trn_rd[59]), + .I2(NlwRenamedSig_OI_trn_rd[60]), + .I3(NlwRenamedSig_OI_trn_rd[61]), + .O(com_cmm_u_rx_pkt_proc_N_45877_2) + ); + defparam com_cmm_u_rx_pkt_proc_un1_state_1_i_0_0.INIT = 16'h0501; + LUT4 com_cmm_u_rx_pkt_proc_un1_state_1_i_0_0 ( + .I0(com_cmm_u_rx_pkt_proc_state[0]), + .I1(com_cmm_u_rx_pkt_proc_state[1]), + .I2(com_cmm_u_rx_pkt_proc_state[2]), + .I3(com_cmmt_rsrc_rdy), + .O(com_cmm_u_rx_pkt_proc_N_14883_i) + ); + defparam com_cmm_u_rx_pkt_proc_bdf_err_rd_pack_3_i_0_2.INIT = 16'h0001; + LUT4_L com_cmm_u_rx_pkt_proc_bdf_err_rd_pack_3_i_0_2 ( + .I0(NlwRenamedSig_OI_trn_rd[41]), + .I1(NlwRenamedSig_OI_trn_rd[42]), + .I2(NlwRenamedSig_OI_trn_rd[43]), + .I3(NlwRenamedSig_OI_trn_rd[44]), + .LO(com_cmm_u_rx_pkt_proc_bdf_err_rd_pack_3_i_0_2_4312) + ); + defparam com_cmm_u_rx_pkt_proc_un1_dw1_enable_2_0_a2_0_a2_0_a2_0_a2.INIT = 8'h80; + LUT3 com_cmm_u_rx_pkt_proc_un1_dw1_enable_2_0_a2_0_a2_0_a2_0_a2 ( + .I0(com_cmm_u_rx_pkt_proc_N_32324_i), + .I1(com_cmm_N_48846_i), + .I2(com_cmm_u_rx_pkt_proc_dw1_enable), + .O(com_cmm_u_rx_pkt_proc_un1_dw1_enable_2_0_a2_0_a2_0_a2_0_a2_4310) + ); + defparam com_cmm_u_rx_pkt_proc_bdf_err_rd_pack_3_i_0_a2_2.INIT = 16'hD000; + LUT4_L com_cmm_u_rx_pkt_proc_bdf_err_rd_pack_3_i_0_a2_2 ( + .I0(com_cmm_u_rx_pkt_proc_bdf_err_rd_pack_3_i_o3_0_4311), + .I1(NlwRenamedSig_OI_trn_rd[34]), + .I2(NlwRenamedSig_OI_trn_rd[35]), + .I3(NlwRenamedSig_OI_trn_rd[40]), + .LO(com_cmm_u_rx_pkt_proc_N_42861) + ); + defparam com_cmm_u_rx_pkt_proc_cfg_wr_3_0_a2_0_a2_0_a2.INIT = 8'h80; + LUT3 com_cmm_u_rx_pkt_proc_cfg_wr_3_0_a2_0_a2_0_a2 ( + .I0(com_cmm_u_rx_pkt_proc_N_45877_2), + .I1(NlwRenamedSig_OI_trn_rd[58]), + .I2(NlwRenamedSig_OI_trn_rd[62]), + .O(com_cmm_u_rx_pkt_proc_cfg_wr_3) + ); + defparam com_cmm_u_rx_pkt_proc_bdf_err_rd_pack_3_i_0_3.INIT = 8'h4C; + LUT3 com_cmm_u_rx_pkt_proc_bdf_err_rd_pack_3_i_0_3 ( + .I0(com_cmm_cfg_rd), + .I1(com_cmm_u_rx_pkt_proc_bdf_err_rd_pack_3_i_0_2_4312), + .I2(NlwRenamedSig_OI_trn_rd[50]), + .O(com_cmm_u_rx_pkt_proc_bdf_err_rd_pack_3_i_0_3_4318) + ); + defparam com_cmm_u_rx_pkt_proc_bdf_err_rd_pack_3_i_0_4.INIT = 16'h1115; + LUT4_L com_cmm_u_rx_pkt_proc_bdf_err_rd_pack_3_i_0_4 ( + .I0(com_cmm_u_rx_pkt_proc_N_42861), + .I1(com_cmm_cfg_rd), + .I2(NlwRenamedSig_OI_trn_rd[48]), + .I3(NlwRenamedSig_OI_trn_rd[49]), + .LO(com_cmm_u_rx_pkt_proc_bdf_err_rd_pack_3_i_0_4_4317) + ); + defparam com_cmm_u_rx_pkt_proc_posnd_wr_pack_6_i_i_0_0.INIT = 16'hFF0B; + LUT4 com_cmm_u_rx_pkt_proc_posnd_wr_pack_6_i_i_0_0 ( + .I0(com_cmm_u_rx_pkt_proc_N_32324_i), + .I1(com_cmm_cfg_wr), + .I2(com_cmm_posnd_wr_pack), + .I3(com_cmm_u_rx_pkt_proc_state[0]), + .O(com_cmm_u_rx_pkt_proc_posnd_wr_pack_6_i_i_0_0_4315) + ); + defparam com_cmm_u_rx_pkt_proc_N_68003_i.INIT = 16'hFEFC; + LUT4_L com_cmm_u_rx_pkt_proc_N_68003_i ( + .I0(com_cmm_u_rx_pkt_proc_N_42531), + .I1(com_cmm_u_rx_pkt_proc_N_42532), + .I2(com_cmm_u_rx_pkt_proc_state[2]), + .I3(com_cmmt_rsrc_rdy), + .LO(com_cmm_u_rx_pkt_proc_N_68003_i_4320) + ); + defparam com_cmm_u_rx_pkt_proc_next_state_0_sqmuxa_3_0_a2_0_a2_0_a2.INIT = 8'h80; + LUT3_L com_cmm_u_rx_pkt_proc_next_state_0_sqmuxa_3_0_a2_0_a2_0_a2 ( + .I0(com_cmm_cfg_wr), + .I1(com_cmm_u_rx_pkt_proc_dw1_enable), + .I2(com_cmm_u_rx_pkt_proc_ecrc_4313), + .LO(com_cmm_u_rx_pkt_proc_next_state_0_sqmuxa_3) + ); + defparam com_cmm_u_rx_pkt_proc_state_idle_3_i_i_0.INIT = 16'hA0EC; + LUT4_L com_cmm_u_rx_pkt_proc_state_idle_3_i_i_0 ( + .I0(com_cmm_N_41751_i), + .I1(com_cmm_u_rx_pkt_proc_state[0]), + .I2(com_cmmt_rdst_rdy_n), + .I3(com_cmmt_rsrc_rdy), + .LO(com_cmm_u_rx_pkt_proc_N_32102_i) + ); + defparam com_cmm_u_rx_pkt_proc_cfg_rd_3_0_a2_0_a2_0_a2.INIT = 8'h08; + LUT3_L com_cmm_u_rx_pkt_proc_cfg_rd_3_0_a2_0_a2_0_a2 ( + .I0(com_cmm_u_rx_pkt_proc_N_45877_2), + .I1(NlwRenamedSig_OI_trn_rd[58]), + .I2(NlwRenamedSig_OI_trn_rd[62]), + .LO(com_cmm_u_rx_pkt_proc_cfg_rd_3) + ); + defparam com_cmm_u_rx_pkt_proc_type1_type0_bar_3_0_a2_0_a2_0_a2.INIT = 8'h80; + LUT3_L com_cmm_u_rx_pkt_proc_type1_type0_bar_3_0_a2_0_a2_0_a2 ( + .I0(com_cmm_u_rx_pkt_proc_N_45877_2), + .I1(NlwRenamedSig_OI_trn_rd[56]), + .I2(NlwRenamedSig_OI_trn_rd[58]), + .LO(com_cmm_u_rx_pkt_proc_type1_type0_bar_3) + ); + defparam com_cmm_u_rx_pkt_proc_nxt_cfg_wr_data_0_a2_0_a2_0_a2_31_.INIT = 4'h8; + LUT2_L com_cmm_u_rx_pkt_proc_nxt_cfg_wr_data_0_a2_0_a2_0_a2_31_ ( + .I0(com_cmm_cfg_wr), + .I1(NlwRenamedSig_OI_trn_rd[31]), + .LO(com_cmm_u_rx_pkt_proc_nxt_cfg_wr_data[31]) + ); + defparam com_cmm_u_rx_pkt_proc_nxt_cfg_wr_data_0_a2_0_a2_0_a2_30_.INIT = 4'h8; + LUT2_L com_cmm_u_rx_pkt_proc_nxt_cfg_wr_data_0_a2_0_a2_0_a2_30_ ( + .I0(com_cmm_cfg_wr), + .I1(NlwRenamedSig_OI_trn_rd[30]), + .LO(com_cmm_u_rx_pkt_proc_nxt_cfg_wr_data[30]) + ); + defparam com_cmm_u_rx_pkt_proc_nxt_cfg_wr_data_0_a2_0_a2_0_a2_29_.INIT = 4'h8; + LUT2_L com_cmm_u_rx_pkt_proc_nxt_cfg_wr_data_0_a2_0_a2_0_a2_29_ ( + .I0(com_cmm_cfg_wr), + .I1(NlwRenamedSig_OI_trn_rd[29]), + .LO(com_cmm_u_rx_pkt_proc_nxt_cfg_wr_data[29]) + ); + defparam com_cmm_u_rx_pkt_proc_nxt_cfg_wr_data_0_a2_0_a2_0_a2_28_.INIT = 4'h8; + LUT2_L com_cmm_u_rx_pkt_proc_nxt_cfg_wr_data_0_a2_0_a2_0_a2_28_ ( + .I0(com_cmm_cfg_wr), + .I1(NlwRenamedSig_OI_trn_rd[28]), + .LO(com_cmm_u_rx_pkt_proc_nxt_cfg_wr_data[28]) + ); + defparam com_cmm_u_rx_pkt_proc_nxt_cfg_wr_data_0_a2_0_a2_0_a2_27_.INIT = 4'h8; + LUT2_L com_cmm_u_rx_pkt_proc_nxt_cfg_wr_data_0_a2_0_a2_0_a2_27_ ( + .I0(com_cmm_cfg_wr), + .I1(NlwRenamedSig_OI_trn_rd[27]), + .LO(com_cmm_u_rx_pkt_proc_nxt_cfg_wr_data[27]) + ); + defparam com_cmm_u_rx_pkt_proc_nxt_cfg_wr_data_0_a2_0_a2_0_a2_26_.INIT = 4'h8; + LUT2_L com_cmm_u_rx_pkt_proc_nxt_cfg_wr_data_0_a2_0_a2_0_a2_26_ ( + .I0(com_cmm_cfg_wr), + .I1(NlwRenamedSig_OI_trn_rd[26]), + .LO(com_cmm_u_rx_pkt_proc_nxt_cfg_wr_data[26]) + ); + defparam com_cmm_u_rx_pkt_proc_nxt_cfg_wr_data_0_a2_0_a2_0_a2_25_.INIT = 4'h8; + LUT2_L com_cmm_u_rx_pkt_proc_nxt_cfg_wr_data_0_a2_0_a2_0_a2_25_ ( + .I0(com_cmm_cfg_wr), + .I1(NlwRenamedSig_OI_trn_rd[25]), + .LO(com_cmm_u_rx_pkt_proc_nxt_cfg_wr_data[25]) + ); + defparam com_cmm_u_rx_pkt_proc_nxt_cfg_wr_data_0_a2_0_a2_0_a2_24_.INIT = 4'h8; + LUT2_L com_cmm_u_rx_pkt_proc_nxt_cfg_wr_data_0_a2_0_a2_0_a2_24_ ( + .I0(com_cmm_cfg_wr), + .I1(NlwRenamedSig_OI_trn_rd[24]), + .LO(com_cmm_u_rx_pkt_proc_nxt_cfg_wr_data[24]) + ); + defparam com_cmm_u_rx_pkt_proc_nxt_cfg_wr_data_0_a2_0_a2_0_a2_23_.INIT = 4'h8; + LUT2_L com_cmm_u_rx_pkt_proc_nxt_cfg_wr_data_0_a2_0_a2_0_a2_23_ ( + .I0(com_cmm_cfg_wr), + .I1(NlwRenamedSig_OI_trn_rd[23]), + .LO(com_cmm_u_rx_pkt_proc_nxt_cfg_wr_data[23]) + ); + defparam com_cmm_u_rx_pkt_proc_nxt_cfg_wr_data_0_a2_0_a2_0_a2_22_.INIT = 4'h8; + LUT2_L com_cmm_u_rx_pkt_proc_nxt_cfg_wr_data_0_a2_0_a2_0_a2_22_ ( + .I0(com_cmm_cfg_wr), + .I1(NlwRenamedSig_OI_trn_rd[22]), + .LO(com_cmm_u_rx_pkt_proc_nxt_cfg_wr_data[22]) + ); + defparam com_cmm_u_rx_pkt_proc_nxt_cfg_wr_data_0_a2_0_a2_0_a2_21_.INIT = 4'h8; + LUT2_L com_cmm_u_rx_pkt_proc_nxt_cfg_wr_data_0_a2_0_a2_0_a2_21_ ( + .I0(com_cmm_cfg_wr), + .I1(NlwRenamedSig_OI_trn_rd[21]), + .LO(com_cmm_u_rx_pkt_proc_nxt_cfg_wr_data[21]) + ); + defparam com_cmm_u_rx_pkt_proc_nxt_cfg_wr_data_0_a2_0_a2_0_a2_20_.INIT = 4'h8; + LUT2_L com_cmm_u_rx_pkt_proc_nxt_cfg_wr_data_0_a2_0_a2_0_a2_20_ ( + .I0(com_cmm_cfg_wr), + .I1(NlwRenamedSig_OI_trn_rd[20]), + .LO(com_cmm_u_rx_pkt_proc_nxt_cfg_wr_data[20]) + ); + defparam com_cmm_u_rx_pkt_proc_nxt_cfg_wr_data_0_a2_0_a2_0_a2_19_.INIT = 4'h8; + LUT2_L com_cmm_u_rx_pkt_proc_nxt_cfg_wr_data_0_a2_0_a2_0_a2_19_ ( + .I0(com_cmm_cfg_wr), + .I1(NlwRenamedSig_OI_trn_rd[19]), + .LO(com_cmm_u_rx_pkt_proc_nxt_cfg_wr_data[19]) + ); + defparam com_cmm_u_rx_pkt_proc_nxt_cfg_wr_data_0_a2_0_a2_0_a2_18_.INIT = 4'h8; + LUT2_L com_cmm_u_rx_pkt_proc_nxt_cfg_wr_data_0_a2_0_a2_0_a2_18_ ( + .I0(com_cmm_cfg_wr), + .I1(NlwRenamedSig_OI_trn_rd[18]), + .LO(com_cmm_u_rx_pkt_proc_nxt_cfg_wr_data[18]) + ); + defparam com_cmm_u_rx_pkt_proc_nxt_cfg_wr_data_0_a2_0_a2_0_a2_17_.INIT = 4'h8; + LUT2_L com_cmm_u_rx_pkt_proc_nxt_cfg_wr_data_0_a2_0_a2_0_a2_17_ ( + .I0(com_cmm_cfg_wr), + .I1(NlwRenamedSig_OI_trn_rd[17]), + .LO(com_cmm_u_rx_pkt_proc_nxt_cfg_wr_data[17]) + ); + defparam com_cmm_u_rx_pkt_proc_nxt_cfg_wr_data_0_a2_0_a2_0_a2_16_.INIT = 4'h8; + LUT2_L com_cmm_u_rx_pkt_proc_nxt_cfg_wr_data_0_a2_0_a2_0_a2_16_ ( + .I0(com_cmm_cfg_wr), + .I1(NlwRenamedSig_OI_trn_rd[16]), + .LO(com_cmm_u_rx_pkt_proc_nxt_cfg_wr_data[16]) + ); + defparam com_cmm_u_rx_pkt_proc_nxt_cfg_wr_data_0_a2_0_a2_0_a2_15_.INIT = 4'h8; + LUT2_L com_cmm_u_rx_pkt_proc_nxt_cfg_wr_data_0_a2_0_a2_0_a2_15_ ( + .I0(com_cmm_cfg_wr), + .I1(NlwRenamedSig_OI_trn_rd[15]), + .LO(com_cmm_u_rx_pkt_proc_nxt_cfg_wr_data[15]) + ); + defparam com_cmm_u_rx_pkt_proc_nxt_cfg_wr_data_0_a2_0_a2_0_a2_14_.INIT = 4'h8; + LUT2_L com_cmm_u_rx_pkt_proc_nxt_cfg_wr_data_0_a2_0_a2_0_a2_14_ ( + .I0(com_cmm_cfg_wr), + .I1(NlwRenamedSig_OI_trn_rd[14]), + .LO(com_cmm_u_rx_pkt_proc_nxt_cfg_wr_data[14]) + ); + defparam com_cmm_u_rx_pkt_proc_nxt_cfg_wr_data_0_a2_0_a2_0_a2_13_.INIT = 4'h8; + LUT2_L com_cmm_u_rx_pkt_proc_nxt_cfg_wr_data_0_a2_0_a2_0_a2_13_ ( + .I0(com_cmm_cfg_wr), + .I1(NlwRenamedSig_OI_trn_rd[13]), + .LO(com_cmm_u_rx_pkt_proc_nxt_cfg_wr_data[13]) + ); + defparam com_cmm_u_rx_pkt_proc_nxt_cfg_wr_data_0_a2_0_a2_0_a2_12_.INIT = 4'h8; + LUT2_L com_cmm_u_rx_pkt_proc_nxt_cfg_wr_data_0_a2_0_a2_0_a2_12_ ( + .I0(com_cmm_cfg_wr), + .I1(NlwRenamedSig_OI_trn_rd[12]), + .LO(com_cmm_u_rx_pkt_proc_nxt_cfg_wr_data[12]) + ); + defparam com_cmm_u_rx_pkt_proc_nxt_cfg_wr_data_0_a2_0_a2_0_a2_11_.INIT = 4'h8; + LUT2_L com_cmm_u_rx_pkt_proc_nxt_cfg_wr_data_0_a2_0_a2_0_a2_11_ ( + .I0(com_cmm_cfg_wr), + .I1(NlwRenamedSig_OI_trn_rd[11]), + .LO(com_cmm_u_rx_pkt_proc_nxt_cfg_wr_data[11]) + ); + defparam com_cmm_u_rx_pkt_proc_nxt_cfg_wr_data_0_a2_0_a2_0_a2_10_.INIT = 4'h8; + LUT2_L com_cmm_u_rx_pkt_proc_nxt_cfg_wr_data_0_a2_0_a2_0_a2_10_ ( + .I0(com_cmm_cfg_wr), + .I1(NlwRenamedSig_OI_trn_rd[10]), + .LO(com_cmm_u_rx_pkt_proc_nxt_cfg_wr_data[10]) + ); + defparam com_cmm_u_rx_pkt_proc_nxt_cfg_wr_data_0_a2_0_a2_0_a2_9_.INIT = 4'h8; + LUT2_L com_cmm_u_rx_pkt_proc_nxt_cfg_wr_data_0_a2_0_a2_0_a2_9_ ( + .I0(com_cmm_cfg_wr), + .I1(NlwRenamedSig_OI_trn_rd[9]), + .LO(com_cmm_u_rx_pkt_proc_nxt_cfg_wr_data[9]) + ); + defparam com_cmm_u_rx_pkt_proc_nxt_cfg_wr_data_0_a2_0_a2_0_a2_8_.INIT = 4'h8; + LUT2_L com_cmm_u_rx_pkt_proc_nxt_cfg_wr_data_0_a2_0_a2_0_a2_8_ ( + .I0(com_cmm_cfg_wr), + .I1(NlwRenamedSig_OI_trn_rd[8]), + .LO(com_cmm_u_rx_pkt_proc_nxt_cfg_wr_data[8]) + ); + defparam com_cmm_u_rx_pkt_proc_nxt_cfg_wr_data_0_a2_0_a2_0_a2_7_.INIT = 4'h8; + LUT2_L com_cmm_u_rx_pkt_proc_nxt_cfg_wr_data_0_a2_0_a2_0_a2_7_ ( + .I0(com_cmm_cfg_wr), + .I1(NlwRenamedSig_OI_trn_rd[7]), + .LO(com_cmm_u_rx_pkt_proc_nxt_cfg_wr_data[7]) + ); + defparam com_cmm_u_rx_pkt_proc_nxt_cfg_wr_data_0_a2_0_a2_0_a2_6_.INIT = 4'h8; + LUT2_L com_cmm_u_rx_pkt_proc_nxt_cfg_wr_data_0_a2_0_a2_0_a2_6_ ( + .I0(com_cmm_cfg_wr), + .I1(NlwRenamedSig_OI_trn_rd[6]), + .LO(com_cmm_u_rx_pkt_proc_nxt_cfg_wr_data[6]) + ); + defparam com_cmm_u_rx_pkt_proc_nxt_cfg_wr_data_0_a2_0_a2_0_a2_5_.INIT = 4'h8; + LUT2_L com_cmm_u_rx_pkt_proc_nxt_cfg_wr_data_0_a2_0_a2_0_a2_5_ ( + .I0(com_cmm_cfg_wr), + .I1(NlwRenamedSig_OI_trn_rd[5]), + .LO(com_cmm_u_rx_pkt_proc_nxt_cfg_wr_data[5]) + ); + defparam com_cmm_u_rx_pkt_proc_nxt_cfg_wr_data_0_a2_0_a2_0_a2_4_.INIT = 4'h8; + LUT2_L com_cmm_u_rx_pkt_proc_nxt_cfg_wr_data_0_a2_0_a2_0_a2_4_ ( + .I0(com_cmm_cfg_wr), + .I1(NlwRenamedSig_OI_trn_rd[4]), + .LO(com_cmm_u_rx_pkt_proc_nxt_cfg_wr_data[4]) + ); + defparam com_cmm_u_rx_pkt_proc_nxt_cfg_wr_data_0_a2_0_a2_0_a2_3_.INIT = 4'h8; + LUT2_L com_cmm_u_rx_pkt_proc_nxt_cfg_wr_data_0_a2_0_a2_0_a2_3_ ( + .I0(com_cmm_cfg_wr), + .I1(NlwRenamedSig_OI_trn_rd[3]), + .LO(com_cmm_u_rx_pkt_proc_nxt_cfg_wr_data[3]) + ); + defparam com_cmm_u_rx_pkt_proc_nxt_cfg_wr_data_0_a2_0_a2_0_a2_2_.INIT = 4'h8; + LUT2_L com_cmm_u_rx_pkt_proc_nxt_cfg_wr_data_0_a2_0_a2_0_a2_2_ ( + .I0(com_cmm_cfg_wr), + .I1(NlwRenamedSig_OI_trn_rd[2]), + .LO(com_cmm_u_rx_pkt_proc_nxt_cfg_wr_data[2]) + ); + defparam com_cmm_u_rx_pkt_proc_nxt_cfg_wr_data_0_a2_0_a2_0_a2_1_.INIT = 4'h8; + LUT2_L com_cmm_u_rx_pkt_proc_nxt_cfg_wr_data_0_a2_0_a2_0_a2_1_ ( + .I0(com_cmm_cfg_wr), + .I1(NlwRenamedSig_OI_trn_rd[1]), + .LO(com_cmm_u_rx_pkt_proc_nxt_cfg_wr_data[1]) + ); + defparam com_cmm_u_rx_pkt_proc_nxt_cfg_wr_data_0_a2_0_a2_0_a2_0_.INIT = 4'h8; + LUT2_L com_cmm_u_rx_pkt_proc_nxt_cfg_wr_data_0_a2_0_a2_0_a2_0_ ( + .I0(com_cmm_cfg_wr), + .I1(NlwRenamedSig_OI_trn_rd[0]), + .LO(com_cmm_u_rx_pkt_proc_nxt_cfg_wr_data[0]) + ); + defparam com_cmm_u_rx_pkt_proc_N_68909_i.INIT = 4'hE; + LUT2_L com_cmm_u_rx_pkt_proc_N_68909_i ( + .I0(com_cmm_u_rx_pkt_proc_N_42531), + .I1(com_cmm_u_rx_pkt_proc_N_42532), + .LO(com_cmm_u_rx_pkt_proc_N_68909_i_4321) + ); + defparam com_cmm_u_rx_pkt_proc_N_68112_i.INIT = 16'hB333; + LUT4_L com_cmm_u_rx_pkt_proc_N_68112_i ( + .I0(com_cmm_u_rx_pkt_proc_cfg_wr_3), + .I1(com_cmm_u_rx_pkt_proc_posnd_wr_pack_6_i_i_0_0_4315), + .I2(com_cmm_u_rx_pkt_proc_state[0]), + .I3(NlwRenamedSig_OI_trn_rd[46]), + .LO(com_cmm_u_rx_pkt_proc_N_68112_i_4314) + ); + defparam com_cmm_u_rx_pkt_proc_N_68201_i.INIT = 16'h7F3F; + LUT4_L com_cmm_u_rx_pkt_proc_N_68201_i ( + .I0(com_cmm_u_rx_pkt_proc_bdf_err_rd_pack_3_i_0_o4_0_4319), + .I1(com_cmm_u_rx_pkt_proc_bdf_err_rd_pack_3_i_0_3_4318), + .I2(com_cmm_u_rx_pkt_proc_bdf_err_rd_pack_3_i_0_4_4317), + .I3(NlwRenamedSig_OI_trn_rd[40]), + .LO(com_cmm_u_rx_pkt_proc_N_68201_i_4316) + ); + defparam com_cmm_u_rx_pkt_proc_nxt_req_valid_iv_i_0_0_a2_0.INIT = 8'h2A; + LUT3 com_cmm_u_rx_pkt_proc_nxt_req_valid_iv_i_0_0_a2_0 ( + .I0(com_cmmt_rdst_rdy_n), + .I1(com_cmm_req_cfgctrl), + .I2(com_cmm_gnt_cfgctrl), + .O(com_cmm_u_rx_pkt_proc_N_42532) + ); + FDC com_cmm_u_rx_pkt_proc_state_3_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_rx_pkt_proc_N_68003_i_4320), + .Q(com_cmmt_rdst_rdy_n), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_rx_pkt_proc_state_2_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_rx_pkt_proc_next_state_0_sqmuxa_3), + .Q(com_cmm_u_rx_pkt_proc_state[2]), + .CLR(com_cmm_rst_267) + ); + FDCE com_cmm_u_rx_pkt_proc_state_1_ ( + .CE(com_cmmt_rsrc_rdy), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_rx_pkt_proc_state[0]), + .Q(com_cmm_u_rx_pkt_proc_state[1]), + .CLR(com_cmm_rst_267) + ); + FDP com_cmm_u_rx_pkt_proc_state_0_ ( + .PRE(com_cmm_rst_267), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_rx_pkt_proc_N_32102_i), + .Q(com_cmm_u_rx_pkt_proc_state[0]) + ); + FDCE com_cmm_u_rx_pkt_proc_cfg_addr_9_ ( + .CE(com_cmm_u_rx_pkt_proc_dw1_enable), + .C(NlwRenamedSig_OI_trn_clk), + .D(NlwRenamedSig_OI_trn_rd[43]), + .Q(com_cmm_cfg_addr[9]), + .CLR(com_cmm_rst_267) + ); + FDCE com_cmm_u_rx_pkt_proc_cfg_addr_8_ ( + .CE(com_cmm_u_rx_pkt_proc_dw1_enable), + .C(NlwRenamedSig_OI_trn_clk), + .D(NlwRenamedSig_OI_trn_rd[42]), + .Q(com_cmm_cfg_addr[8]), + .CLR(com_cmm_rst_267) + ); + FDCE com_cmm_u_rx_pkt_proc_cfg_addr_7_ ( + .CE(com_cmm_u_rx_pkt_proc_dw1_enable), + .C(NlwRenamedSig_OI_trn_clk), + .D(NlwRenamedSig_OI_trn_rd[41]), + .Q(com_cmm_cfg_addr[7]), + .CLR(com_cmm_rst_267) + ); + FDCE com_cmm_u_rx_pkt_proc_cfg_addr_6_ ( + .CE(com_cmm_u_rx_pkt_proc_dw1_enable), + .C(NlwRenamedSig_OI_trn_clk), + .D(NlwRenamedSig_OI_trn_rd[40]), + .Q(com_cmm_cfg_addr[6]), + .CLR(com_cmm_rst_267) + ); + FDCE com_cmm_u_rx_pkt_proc_cfg_addr_5_ ( + .CE(com_cmm_u_rx_pkt_proc_dw1_enable), + .C(NlwRenamedSig_OI_trn_clk), + .D(NlwRenamedSig_OI_trn_rd[39]), + .Q(com_cmm_cfg_addr[5]), + .CLR(com_cmm_rst_267) + ); + FDCE com_cmm_u_rx_pkt_proc_cfg_addr_4_ ( + .CE(com_cmm_u_rx_pkt_proc_dw1_enable), + .C(NlwRenamedSig_OI_trn_clk), + .D(NlwRenamedSig_OI_trn_rd[38]), + .Q(com_cmm_cfg_addr[4]), + .CLR(com_cmm_rst_267) + ); + FDCE com_cmm_u_rx_pkt_proc_cfg_addr_3_ ( + .CE(com_cmm_u_rx_pkt_proc_dw1_enable), + .C(NlwRenamedSig_OI_trn_clk), + .D(NlwRenamedSig_OI_trn_rd[37]), + .Q(com_cmm_cfg_addr[3]), + .CLR(com_cmm_rst_267) + ); + FDCE com_cmm_u_rx_pkt_proc_cfg_addr_2_ ( + .CE(com_cmm_u_rx_pkt_proc_dw1_enable), + .C(NlwRenamedSig_OI_trn_clk), + .D(NlwRenamedSig_OI_trn_rd[36]), + .Q(com_cmm_cfg_addr[2]), + .CLR(com_cmm_rst_267) + ); + FDCE com_cmm_u_rx_pkt_proc_cfg_addr_1_ ( + .CE(com_cmm_u_rx_pkt_proc_dw1_enable), + .C(NlwRenamedSig_OI_trn_clk), + .D(NlwRenamedSig_OI_trn_rd[35]), + .Q(com_cmm_cfg_addr[1]), + .CLR(com_cmm_rst_267) + ); + FDCE com_cmm_u_rx_pkt_proc_cfg_addr_0_ ( + .CE(com_cmm_u_rx_pkt_proc_dw1_enable), + .C(NlwRenamedSig_OI_trn_clk), + .D(NlwRenamedSig_OI_trn_rd[34]), + .Q(com_cmm_cfg_addr[0]), + .CLR(com_cmm_rst_267) + ); + FDCE com_cmm_u_rx_pkt_proc_cfg_wr_data_31_ ( + .CE(com_cmm_u_rx_pkt_proc_dw1_enable), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_rx_pkt_proc_nxt_cfg_wr_data[31]), + .Q(com_cmm_cfg_wr_data_31_), + .CLR(com_cmm_rst_267) + ); + FDCE com_cmm_u_rx_pkt_proc_cfg_wr_data_30_ ( + .CE(com_cmm_u_rx_pkt_proc_dw1_enable), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_rx_pkt_proc_nxt_cfg_wr_data[30]), + .Q(com_cmm_cfg_wr_data_30_), + .CLR(com_cmm_rst_267) + ); + FDCE com_cmm_u_rx_pkt_proc_cfg_wr_data_29_ ( + .CE(com_cmm_u_rx_pkt_proc_dw1_enable), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_rx_pkt_proc_nxt_cfg_wr_data[29]), + .Q(com_cmm_cfg_wr_data_29_), + .CLR(com_cmm_rst_267) + ); + FDCE com_cmm_u_rx_pkt_proc_cfg_wr_data_28_ ( + .CE(com_cmm_u_rx_pkt_proc_dw1_enable), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_rx_pkt_proc_nxt_cfg_wr_data[28]), + .Q(com_cmm_cfg_wr_data_28_), + .CLR(com_cmm_rst_267) + ); + FDCE com_cmm_u_rx_pkt_proc_cfg_wr_data_27_ ( + .CE(com_cmm_u_rx_pkt_proc_dw1_enable), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_rx_pkt_proc_nxt_cfg_wr_data[27]), + .Q(com_cmm_cfg_wr_data[27]), + .CLR(com_cmm_rst_267) + ); + FDCE com_cmm_u_rx_pkt_proc_cfg_wr_data_26_ ( + .CE(com_cmm_u_rx_pkt_proc_dw1_enable), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_rx_pkt_proc_nxt_cfg_wr_data[26]), + .Q(com_cmm_cfg_wr_data[26]), + .CLR(com_cmm_rst_267) + ); + FDCE com_cmm_u_rx_pkt_proc_cfg_wr_data_25_ ( + .CE(com_cmm_u_rx_pkt_proc_dw1_enable), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_rx_pkt_proc_nxt_cfg_wr_data[25]), + .Q(com_cmm_cfg_wr_data[25]), + .CLR(com_cmm_rst_267) + ); + FDCE com_cmm_u_rx_pkt_proc_cfg_wr_data_24_ ( + .CE(com_cmm_u_rx_pkt_proc_dw1_enable), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_rx_pkt_proc_nxt_cfg_wr_data[24]), + .Q(com_cmm_cfg_wr_data[24]), + .CLR(com_cmm_rst_267) + ); + FDCE com_cmm_u_rx_pkt_proc_cfg_wr_data_23_ ( + .CE(com_cmm_u_rx_pkt_proc_dw1_enable), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_rx_pkt_proc_nxt_cfg_wr_data[23]), + .Q(com_cmm_cfg_wr_data_23_), + .CLR(com_cmm_rst_267) + ); + FDCE com_cmm_u_rx_pkt_proc_cfg_wr_data_22_ ( + .CE(com_cmm_u_rx_pkt_proc_dw1_enable), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_rx_pkt_proc_nxt_cfg_wr_data[22]), + .Q(com_cmm_cfg_wr_data_22_), + .CLR(com_cmm_rst_267) + ); + FDCE com_cmm_u_rx_pkt_proc_cfg_wr_data_21_ ( + .CE(com_cmm_u_rx_pkt_proc_dw1_enable), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_rx_pkt_proc_nxt_cfg_wr_data[21]), + .Q(com_cmm_cfg_wr_data_21_), + .CLR(com_cmm_rst_267) + ); + FDCE com_cmm_u_rx_pkt_proc_cfg_wr_data_20_ ( + .CE(com_cmm_u_rx_pkt_proc_dw1_enable), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_rx_pkt_proc_nxt_cfg_wr_data[20]), + .Q(com_cmm_cfg_wr_data_20_), + .CLR(com_cmm_rst_267) + ); + FDCE com_cmm_u_rx_pkt_proc_cfg_wr_data_19_ ( + .CE(com_cmm_u_rx_pkt_proc_dw1_enable), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_rx_pkt_proc_nxt_cfg_wr_data[19]), + .Q(com_cmm_cfg_wr_data_19_), + .CLR(com_cmm_rst_267) + ); + FDCE com_cmm_u_rx_pkt_proc_cfg_wr_data_18_ ( + .CE(com_cmm_u_rx_pkt_proc_dw1_enable), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_rx_pkt_proc_nxt_cfg_wr_data[18]), + .Q(com_cmm_cfg_wr_data_18_), + .CLR(com_cmm_rst_267) + ); + FDCE com_cmm_u_rx_pkt_proc_cfg_wr_data_17_ ( + .CE(com_cmm_u_rx_pkt_proc_dw1_enable), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_rx_pkt_proc_nxt_cfg_wr_data[17]), + .Q(com_cmm_cfg_wr_data_17_), + .CLR(com_cmm_rst_267) + ); + FDCE com_cmm_u_rx_pkt_proc_cfg_wr_data_16_ ( + .CE(com_cmm_u_rx_pkt_proc_dw1_enable), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_rx_pkt_proc_nxt_cfg_wr_data[16]), + .Q(com_cmm_cfg_wr_data_16_), + .CLR(com_cmm_rst_267) + ); + FDCE com_cmm_u_rx_pkt_proc_cfg_wr_data_15_ ( + .CE(com_cmm_u_rx_pkt_proc_dw1_enable), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_rx_pkt_proc_nxt_cfg_wr_data[15]), + .Q(com_cmm_cfg_wr_data_15_), + .CLR(com_cmm_rst_267) + ); + FDCE com_cmm_u_rx_pkt_proc_cfg_wr_data_14_ ( + .CE(com_cmm_u_rx_pkt_proc_dw1_enable), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_rx_pkt_proc_nxt_cfg_wr_data[14]), + .Q(com_cmm_cfg_wr_data_14_), + .CLR(com_cmm_rst_267) + ); + FDCE com_cmm_u_rx_pkt_proc_cfg_wr_data_13_ ( + .CE(com_cmm_u_rx_pkt_proc_dw1_enable), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_rx_pkt_proc_nxt_cfg_wr_data[13]), + .Q(com_cmm_cfg_wr_data_13_), + .CLR(com_cmm_rst_267) + ); + FDCE com_cmm_u_rx_pkt_proc_cfg_wr_data_12_ ( + .CE(com_cmm_u_rx_pkt_proc_dw1_enable), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_rx_pkt_proc_nxt_cfg_wr_data[12]), + .Q(com_cmm_cfg_wr_data_12_), + .CLR(com_cmm_rst_267) + ); + FDCE com_cmm_u_rx_pkt_proc_cfg_wr_data_11_ ( + .CE(com_cmm_u_rx_pkt_proc_dw1_enable), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_rx_pkt_proc_nxt_cfg_wr_data[11]), + .Q(com_cmm_cfg_wr_data_11_), + .CLR(com_cmm_rst_267) + ); + FDCE com_cmm_u_rx_pkt_proc_cfg_wr_data_10_ ( + .CE(com_cmm_u_rx_pkt_proc_dw1_enable), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_rx_pkt_proc_nxt_cfg_wr_data[10]), + .Q(com_cmm_cfg_wr_data_10_), + .CLR(com_cmm_rst_267) + ); + FDCE com_cmm_u_rx_pkt_proc_cfg_wr_data_9_ ( + .CE(com_cmm_u_rx_pkt_proc_dw1_enable), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_rx_pkt_proc_nxt_cfg_wr_data[9]), + .Q(com_cmm_cfg_wr_data_9_), + .CLR(com_cmm_rst_267) + ); + FDCE com_cmm_u_rx_pkt_proc_cfg_wr_data_8_ ( + .CE(com_cmm_u_rx_pkt_proc_dw1_enable), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_rx_pkt_proc_nxt_cfg_wr_data[8]), + .Q(com_cmm_cfg_wr_data_8_), + .CLR(com_cmm_rst_267) + ); + FDCE com_cmm_u_rx_pkt_proc_cfg_wr_data_7_ ( + .CE(com_cmm_u_rx_pkt_proc_dw1_enable), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_rx_pkt_proc_nxt_cfg_wr_data[7]), + .Q(com_cmm_cfg_wr_data_7_), + .CLR(com_cmm_rst_267) + ); + FDCE com_cmm_u_rx_pkt_proc_cfg_wr_data_6_ ( + .CE(com_cmm_u_rx_pkt_proc_dw1_enable), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_rx_pkt_proc_nxt_cfg_wr_data[6]), + .Q(com_cmm_cfg_wr_data_6_), + .CLR(com_cmm_rst_267) + ); + FDCE com_cmm_u_rx_pkt_proc_cfg_wr_data_5_ ( + .CE(com_cmm_u_rx_pkt_proc_dw1_enable), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_rx_pkt_proc_nxt_cfg_wr_data[5]), + .Q(com_cmm_cfg_wr_data_5_), + .CLR(com_cmm_rst_267) + ); + FDCE com_cmm_u_rx_pkt_proc_cfg_wr_data_4_ ( + .CE(com_cmm_u_rx_pkt_proc_dw1_enable), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_rx_pkt_proc_nxt_cfg_wr_data[4]), + .Q(com_cmm_cfg_wr_data_4_), + .CLR(com_cmm_rst_267) + ); + FDCE com_cmm_u_rx_pkt_proc_cfg_wr_data_3_ ( + .CE(com_cmm_u_rx_pkt_proc_dw1_enable), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_rx_pkt_proc_nxt_cfg_wr_data[3]), + .Q(com_cmm_cfg_wr_data_3_), + .CLR(com_cmm_rst_267) + ); + FDCE com_cmm_u_rx_pkt_proc_cfg_wr_data_2_ ( + .CE(com_cmm_u_rx_pkt_proc_dw1_enable), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_rx_pkt_proc_nxt_cfg_wr_data[2]), + .Q(com_cmm_cfg_wr_data_2_), + .CLR(com_cmm_rst_267) + ); + FDCE com_cmm_u_rx_pkt_proc_cfg_wr_data_1_ ( + .CE(com_cmm_u_rx_pkt_proc_dw1_enable), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_rx_pkt_proc_nxt_cfg_wr_data[1]), + .Q(com_cmm_cfg_wr_data_1_), + .CLR(com_cmm_rst_267) + ); + FDCE com_cmm_u_rx_pkt_proc_cfg_wr_data_0_ ( + .CE(com_cmm_u_rx_pkt_proc_dw1_enable), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_rx_pkt_proc_nxt_cfg_wr_data[0]), + .Q(com_cmm_cfg_wr_data_0_), + .CLR(com_cmm_rst_267) + ); + FDCE com_cmm_u_rx_pkt_proc_req_valid ( + .CE(com_cmm_u_rx_pkt_proc_N_14883_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_rx_pkt_proc_N_68909_i_4321), + .Q(com_cmm_req_valid), + .CLR(com_cmm_rst_267) + ); + FDRE com_cmm_u_tx_pkt_proc_TLP_data_reg_0_ ( + .CE(com_cmm_u_tx_pkt_proc_N_49941_i_4357), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_tx_pkt_proc_TLP_data_reg_10_0_), + .Q(com_TLP_data_reg_0_), + .R(com_cmm_rst_267) + ); + FDRE com_cmm_u_tx_pkt_proc_TLP_data_reg_1_ ( + .CE(com_cmm_u_tx_pkt_proc_N_49941_i_4357), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_tx_pkt_proc_TLP_data_reg_10_1_), + .Q(com_TLP_data_reg_1_), + .R(com_cmm_rst_267) + ); + FDRE com_cmm_u_tx_pkt_proc_TLP_data_reg_2_ ( + .CE(com_cmm_u_tx_pkt_proc_N_49941_i_4357), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_tx_pkt_proc_TLP_data_reg_10_2_), + .Q(com_TLP_data_reg_2_), + .R(com_cmm_rst_267) + ); + FDRE com_cmm_u_tx_pkt_proc_TLP_data_reg_3_ ( + .CE(com_cmm_u_tx_pkt_proc_N_49941_i_4357), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_tx_pkt_proc_TLP_data_reg_10_3_), + .Q(com_TLP_data_reg_3_), + .R(com_cmm_rst_267) + ); + FDRE com_cmm_u_tx_pkt_proc_TLP_data_reg_4_ ( + .CE(com_cmm_u_tx_pkt_proc_N_49941_i_4357), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_tx_pkt_proc_TLP_data_reg_10_4_), + .Q(com_TLP_data_reg_4_), + .R(com_cmm_rst_267) + ); + FDRE com_cmm_u_tx_pkt_proc_TLP_data_reg_5_ ( + .CE(com_cmm_u_tx_pkt_proc_N_49941_i_4357), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_tx_pkt_proc_TLP_data_reg_10_5_), + .Q(com_TLP_data_reg_5_), + .R(com_cmm_rst_267) + ); + FDRE com_cmm_u_tx_pkt_proc_TLP_data_reg_6_ ( + .CE(com_cmm_u_tx_pkt_proc_N_49941_i_4357), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_tx_pkt_proc_TLP_data_reg_10_6_), + .Q(com_TLP_data_reg_6_), + .R(com_cmm_rst_267) + ); + FDRE com_cmm_u_tx_pkt_proc_TLP_data_reg_7_ ( + .CE(com_cmm_u_tx_pkt_proc_N_49941_i_4357), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_tx_pkt_proc_TLP_data_reg_10_7_), + .Q(com_TLP_data_reg_7_), + .R(com_cmm_rst_267) + ); + FDRE com_cmm_u_tx_pkt_proc_TLP_data_reg_8_ ( + .CE(com_cmm_u_tx_pkt_proc_N_49941_i_4357), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_tx_pkt_proc_TLP_data_reg_10_8_), + .Q(com_TLP_data_reg_8_), + .R(com_cmm_rst_267) + ); + FDRE com_cmm_u_tx_pkt_proc_TLP_data_reg_9_ ( + .CE(com_cmm_u_tx_pkt_proc_N_49941_i_4357), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_tx_pkt_proc_TLP_data_reg_10_9_), + .Q(com_TLP_data_reg_9_), + .R(com_cmm_rst_267) + ); + FDRE com_cmm_u_tx_pkt_proc_TLP_data_reg_10_ ( + .CE(com_cmm_u_tx_pkt_proc_N_49941_i_4357), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_tx_pkt_proc_TLP_data_reg_10_10_), + .Q(com_TLP_data_reg_10_), + .R(com_cmm_rst_267) + ); + FDRE com_cmm_u_tx_pkt_proc_TLP_data_reg_11_ ( + .CE(com_cmm_u_tx_pkt_proc_N_49941_i_4357), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_tx_pkt_proc_TLP_data_reg_10_11_), + .Q(com_TLP_data_reg_11_), + .R(com_cmm_rst_267) + ); + FDRE com_cmm_u_tx_pkt_proc_TLP_data_reg_12_ ( + .CE(com_cmm_u_tx_pkt_proc_N_49941_i_4357), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_tx_pkt_proc_TLP_data_reg_10_12_), + .Q(com_cmm_u_tx_pkt_proc_TLP_data_reg_12__4349), + .R(com_cmm_rst_267) + ); + FDRE com_cmm_u_tx_pkt_proc_TLP_data_reg_13_ ( + .CE(com_cmm_u_tx_pkt_proc_N_49941_i_4357), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_tx_pkt_proc_TLP_data_reg_10_13_), + .Q(com_cmm_u_tx_pkt_proc_TLP_data_reg_13__4350), + .R(com_cmm_rst_267) + ); + FDRE com_cmm_u_tx_pkt_proc_TLP_data_reg_14_ ( + .CE(com_cmm_u_tx_pkt_proc_N_49941_i_4357), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_tx_pkt_proc_TLP_data_reg_10_14_), + .Q(com_TLP_data_reg_14_), + .R(com_cmm_rst_267) + ); + FDRE com_cmm_u_tx_pkt_proc_TLP_data_reg_15_ ( + .CE(com_cmm_u_tx_pkt_proc_N_49941_i_4357), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_tx_pkt_proc_TLP_data_reg_10_15_), + .Q(com_TLP_data_reg_15_), + .R(com_cmm_rst_267) + ); + FDRE com_cmm_u_tx_pkt_proc_TLP_data_reg_16_ ( + .CE(com_cmm_u_tx_pkt_proc_N_49941_i_4357), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_tx_pkt_proc_N_28304_i), + .Q(com_TLP_data_reg_16_), + .R(com_cmm_rst_267) + ); + FDRE com_cmm_u_tx_pkt_proc_TLP_data_reg_17_ ( + .CE(com_cmm_u_tx_pkt_proc_N_49941_i_4357), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_tx_pkt_proc_N_28306_i), + .Q(com_TLP_data_reg_17_), + .R(com_cmm_rst_267) + ); + FDRE com_cmm_u_tx_pkt_proc_TLP_data_reg_18_ ( + .CE(com_cmm_u_tx_pkt_proc_N_49941_i_4357), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_tx_pkt_proc_N_28308_i), + .Q(com_TLP_data_reg_18_), + .R(com_cmm_rst_267) + ); + FDRE com_cmm_u_tx_pkt_proc_TLP_data_reg_19_ ( + .CE(com_cmm_u_tx_pkt_proc_N_49941_i_4357), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_tx_pkt_proc_N_28310_i), + .Q(com_TLP_data_reg_19_), + .R(com_cmm_rst_267) + ); + FDRE com_cmm_u_tx_pkt_proc_TLP_data_reg_20_ ( + .CE(com_cmm_u_tx_pkt_proc_N_49941_i_4357), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_tx_pkt_proc_N_28312_i), + .Q(com_cmm_u_tx_pkt_proc_TLP_data_reg_20__4351), + .R(com_cmm_rst_267) + ); + FDRE com_cmm_u_tx_pkt_proc_TLP_data_reg_21_ ( + .CE(com_cmm_u_tx_pkt_proc_N_49941_i_4357), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_tx_pkt_proc_N_28314_i), + .Q(com_cmm_u_tx_pkt_proc_TLP_data_reg_21__4352), + .R(com_cmm_rst_267) + ); + FDRE com_cmm_u_tx_pkt_proc_TLP_data_reg_22_ ( + .CE(com_cmm_u_tx_pkt_proc_N_49941_i_4357), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_tx_pkt_proc_N_28316_i), + .Q(com_cmm_u_tx_pkt_proc_TLP_data_reg_22__4353), + .R(com_cmm_rst_267) + ); + FDRE com_cmm_u_tx_pkt_proc_TLP_data_reg_23_ ( + .CE(com_cmm_u_tx_pkt_proc_N_49941_i_4357), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_tx_pkt_proc_N_28318_i), + .Q(com_TLP_data_reg_23_), + .R(com_cmm_rst_267) + ); + FDRE com_cmm_u_tx_pkt_proc_TLP_data_reg_24_ ( + .CE(com_cmm_u_tx_pkt_proc_N_49941_i_4357), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_tx_pkt_proc_N_28320_i), + .Q(com_cmm_u_tx_pkt_proc_TLP_data_reg_24__4354), + .R(com_cmm_rst_267) + ); + FDRE com_cmm_u_tx_pkt_proc_TLP_data_reg_25_ ( + .CE(com_cmm_u_tx_pkt_proc_N_49941_i_4357), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_tx_pkt_proc_N_28322_i), + .Q(com_TLP_data_reg_25_), + .R(com_cmm_rst_267) + ); + FDRE com_cmm_u_tx_pkt_proc_TLP_data_reg_26_ ( + .CE(com_cmm_u_tx_pkt_proc_N_49941_i_4357), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_tx_pkt_proc_N_28324_i), + .Q(com_cmm_u_tx_pkt_proc_TLP_data_reg_26__4355), + .R(com_cmm_rst_267) + ); + FDRE com_cmm_u_tx_pkt_proc_TLP_data_reg_27_ ( + .CE(com_cmm_u_tx_pkt_proc_N_49941_i_4357), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_tx_pkt_proc_N_28326_i), + .Q(com_TLP_data_reg_27_), + .R(com_cmm_rst_267) + ); + FDRE com_cmm_u_tx_pkt_proc_TLP_data_reg_28_ ( + .CE(com_cmm_u_tx_pkt_proc_N_49941_i_4357), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_tx_pkt_proc_N_28328_i), + .Q(com_cmm_u_tx_pkt_proc_TLP_data_reg_28__4356), + .R(com_cmm_rst_267) + ); + FDRE com_cmm_u_tx_pkt_proc_TLP_data_reg_29_ ( + .CE(com_cmm_u_tx_pkt_proc_N_49941_i_4357), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_tx_pkt_proc_N_28330_i), + .Q(com_TLP_data_reg_29_), + .R(com_cmm_rst_267) + ); + FDRE com_cmm_u_tx_pkt_proc_TLP_data_reg_30_ ( + .CE(com_cmm_u_tx_pkt_proc_N_49941_i_4357), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_tx_pkt_proc_N_28332_i), + .Q(com_TLP_data_reg_30_), + .R(com_cmm_rst_267) + ); + FDRE com_cmm_u_tx_pkt_proc_TLP_data_reg_31_ ( + .CE(com_cmm_u_tx_pkt_proc_N_49941_i_4357), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_tx_pkt_proc_N_28334_i), + .Q(com_TLP_data_reg_31_), + .R(com_cmm_rst_267) + ); + FDRE com_cmm_u_tx_pkt_proc_TLP_data_reg_32_ ( + .CE(com_cmm_u_tx_pkt_proc_N_49941_i_4357), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_tx_pkt_proc_TLP_data_reg_10_32_), + .Q(com_cmm_u_tx_pkt_proc_TLP_data_reg_32__4322), + .R(com_cmm_rst_267) + ); + FDRE com_cmm_u_tx_pkt_proc_TLP_data_reg_33_ ( + .CE(com_cmm_u_tx_pkt_proc_N_49941_i_4357), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_tx_pkt_proc_TLP_data_reg_10_33_), + .Q(com_cmm_u_tx_pkt_proc_TLP_data_reg_33__4323), + .R(com_cmm_rst_267) + ); + FDRE com_cmm_u_tx_pkt_proc_TLP_data_reg_34_ ( + .CE(com_cmm_u_tx_pkt_proc_N_49941_i_4357), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_tx_pkt_proc_TLP_data_reg_10_34_), + .Q(com_cmm_u_tx_pkt_proc_TLP_data_reg_34__4324), + .R(com_cmm_rst_267) + ); + FDRE com_cmm_u_tx_pkt_proc_TLP_data_reg_35_ ( + .CE(com_cmm_u_tx_pkt_proc_N_49941_i_4357), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_tx_pkt_proc_TLP_data_reg_10_35_), + .Q(com_cmm_u_tx_pkt_proc_TLP_data_reg_35__4325), + .R(com_cmm_rst_267) + ); + FDRE com_cmm_u_tx_pkt_proc_TLP_data_reg_36_ ( + .CE(com_cmm_u_tx_pkt_proc_N_49941_i_4357), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_tx_pkt_proc_TLP_data_reg_10_36_), + .Q(com_cmm_u_tx_pkt_proc_TLP_data_reg_36__4326), + .R(com_cmm_rst_267) + ); + FDRE com_cmm_u_tx_pkt_proc_TLP_data_reg_37_ ( + .CE(com_cmm_u_tx_pkt_proc_N_49941_i_4357), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_tx_pkt_proc_TLP_data_reg_10_37_), + .Q(com_cmm_u_tx_pkt_proc_TLP_data_reg_37__4327), + .R(com_cmm_rst_267) + ); + FDRE com_cmm_u_tx_pkt_proc_TLP_data_reg_38_ ( + .CE(com_cmm_u_tx_pkt_proc_N_49941_i_4357), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_tx_pkt_proc_TLP_data_reg_10_38_), + .Q(com_cmm_u_tx_pkt_proc_TLP_data_reg_38__4328), + .R(com_cmm_rst_267) + ); + FDRE com_cmm_u_tx_pkt_proc_TLP_data_reg_39_ ( + .CE(com_cmm_u_tx_pkt_proc_N_49941_i_4357), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_tx_pkt_proc_TLP_data_reg_10_39_), + .Q(com_cmm_u_tx_pkt_proc_TLP_data_reg_39__4329), + .R(com_cmm_rst_267) + ); + FDRE com_cmm_u_tx_pkt_proc_TLP_data_reg_40_ ( + .CE(com_cmm_u_tx_pkt_proc_N_49941_i_4357), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_tx_pkt_proc_TLP_data_reg_10_40_), + .Q(com_cmm_u_tx_pkt_proc_TLP_data_reg_40__4330), + .R(com_cmm_rst_267) + ); + FDRE com_cmm_u_tx_pkt_proc_TLP_data_reg_41_ ( + .CE(com_cmm_u_tx_pkt_proc_N_49941_i_4357), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_tx_pkt_proc_TLP_data_reg_10_41_), + .Q(com_cmm_u_tx_pkt_proc_TLP_data_reg_41__4331), + .R(com_cmm_rst_267) + ); + FDRE com_cmm_u_tx_pkt_proc_TLP_data_reg_42_ ( + .CE(com_cmm_u_tx_pkt_proc_N_49941_i_4357), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_tx_pkt_proc_TLP_data_reg_10_42_), + .Q(com_cmm_u_tx_pkt_proc_TLP_data_reg_42__4332), + .R(com_cmm_rst_267) + ); + FDRE com_cmm_u_tx_pkt_proc_TLP_data_reg_43_ ( + .CE(com_cmm_u_tx_pkt_proc_N_49941_i_4357), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_tx_pkt_proc_TLP_data_reg_10_43_), + .Q(com_cmm_u_tx_pkt_proc_TLP_data_reg_43__4333), + .R(com_cmm_rst_267) + ); + FDRE com_cmm_u_tx_pkt_proc_TLP_data_reg_44_ ( + .CE(com_cmm_u_tx_pkt_proc_N_49941_i_4357), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_tx_pkt_proc_TLP_data_reg_10_44_), + .Q(com_TLP_data_reg_44_), + .R(com_cmm_rst_267) + ); + FDRE com_cmm_u_tx_pkt_proc_TLP_data_reg_45_ ( + .CE(com_cmm_u_tx_pkt_proc_N_49941_i_4357), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_tx_pkt_proc_TLP_data_reg_10_45_), + .Q(com_cmm_u_tx_pkt_proc_TLP_data_reg_45__4334), + .R(com_cmm_rst_267) + ); + FDRE com_cmm_u_tx_pkt_proc_TLP_data_reg_46_ ( + .CE(com_cmm_u_tx_pkt_proc_N_49941_i_4357), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_tx_pkt_proc_TLP_data_reg_10_46_), + .Q(com_TLP_data_reg_46_), + .R(com_cmm_rst_267) + ); + FDRE com_cmm_u_tx_pkt_proc_TLP_data_reg_47_ ( + .CE(com_cmm_u_tx_pkt_proc_N_49941_i_4357), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_tx_pkt_proc_TLP_data_reg_10_47_), + .Q(com_cmm_u_tx_pkt_proc_TLP_data_reg_47__4335), + .R(com_cmm_rst_267) + ); + FDRE com_cmm_u_tx_pkt_proc_TLP_data_reg_48_ ( + .CE(com_cmm_u_tx_pkt_proc_N_49941_i_4357), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_tx_pkt_proc_TLP_data_reg_10_48_), + .Q(com_TLP_data_reg_48_), + .R(com_cmm_rst_267) + ); + FDRE com_cmm_u_tx_pkt_proc_TLP_data_reg_49_ ( + .CE(com_cmm_u_tx_pkt_proc_N_49941_i_4357), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_tx_pkt_proc_TLP_data_reg_10_49_), + .Q(com_TLP_data_reg_49_), + .R(com_cmm_rst_267) + ); + FDRE com_cmm_u_tx_pkt_proc_TLP_data_reg_50_ ( + .CE(com_cmm_u_tx_pkt_proc_N_49941_i_4357), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_tx_pkt_proc_TLP_data_reg_10_50_), + .Q(com_TLP_data_reg_50_), + .R(com_cmm_rst_267) + ); + FDRE com_cmm_u_tx_pkt_proc_TLP_data_reg_51_ ( + .CE(com_cmm_u_tx_pkt_proc_N_49941_i_4357), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_tx_pkt_proc_TLP_data_reg_10_51_), + .Q(com_cmm_u_tx_pkt_proc_TLP_data_reg_51__4336), + .R(com_cmm_rst_267) + ); + FDRE com_cmm_u_tx_pkt_proc_TLP_data_reg_52_ ( + .CE(com_cmm_u_tx_pkt_proc_N_49941_i_4357), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_tx_pkt_proc_TLP_data_reg_10_52_), + .Q(com_cmm_u_tx_pkt_proc_TLP_data_reg_52__4337), + .R(com_cmm_rst_267) + ); + FDRE com_cmm_u_tx_pkt_proc_TLP_data_reg_53_ ( + .CE(com_cmm_u_tx_pkt_proc_N_49941_i_4357), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_tx_pkt_proc_TLP_data_reg_10_53_), + .Q(com_cmm_u_tx_pkt_proc_TLP_data_reg_53__4338), + .R(com_cmm_rst_267) + ); + FDRE com_cmm_u_tx_pkt_proc_TLP_data_reg_54_ ( + .CE(com_cmm_u_tx_pkt_proc_N_49941_i_4357), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_tx_pkt_proc_TLP_data_reg_10_54_), + .Q(com_cmm_u_tx_pkt_proc_TLP_data_reg_54__4339), + .R(com_cmm_rst_267) + ); + FDRE com_cmm_u_tx_pkt_proc_TLP_data_reg_55_ ( + .CE(com_cmm_u_tx_pkt_proc_N_49941_i_4357), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_tx_pkt_proc_TLP_data_reg_10_55_), + .Q(com_cmm_u_tx_pkt_proc_TLP_data_reg_55__4340), + .R(com_cmm_rst_267) + ); + FDRE com_cmm_u_tx_pkt_proc_TLP_data_reg_56_ ( + .CE(com_cmm_u_tx_pkt_proc_N_49941_i_4357), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_tx_pkt_proc_TLP_data_reg_10_56_), + .Q(com_cmm_u_tx_pkt_proc_TLP_data_reg_56__4341), + .R(com_cmm_rst_267) + ); + FDRE com_cmm_u_tx_pkt_proc_TLP_data_reg_57_ ( + .CE(com_cmm_u_tx_pkt_proc_N_49941_i_4357), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_tx_pkt_proc_TLP_data_reg_10_57_), + .Q(com_cmm_u_tx_pkt_proc_TLP_data_reg_57__4342), + .R(com_cmm_rst_267) + ); + FDRE com_cmm_u_tx_pkt_proc_TLP_data_reg_58_ ( + .CE(com_cmm_u_tx_pkt_proc_N_49941_i_4357), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_tx_pkt_proc_TLP_data_reg_10_58_), + .Q(com_cmm_u_tx_pkt_proc_TLP_data_reg_58__4343), + .R(com_cmm_rst_267) + ); + FDRE com_cmm_u_tx_pkt_proc_TLP_data_reg_59_ ( + .CE(com_cmm_u_tx_pkt_proc_N_49941_i_4357), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_tx_pkt_proc_TLP_data_reg_10_59_), + .Q(com_cmm_u_tx_pkt_proc_TLP_data_reg_59__4344), + .R(com_cmm_rst_267) + ); + FDRE com_cmm_u_tx_pkt_proc_TLP_data_reg_60_ ( + .CE(com_cmm_u_tx_pkt_proc_N_49941_i_4357), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_tx_pkt_proc_TLP_data_reg_10_60_), + .Q(com_cmm_u_tx_pkt_proc_TLP_data_reg_60__4345), + .R(com_cmm_rst_267) + ); + FDRE com_cmm_u_tx_pkt_proc_TLP_data_reg_61_ ( + .CE(com_cmm_u_tx_pkt_proc_N_49941_i_4357), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_tx_pkt_proc_TLP_data_reg_10_61_), + .Q(com_cmm_u_tx_pkt_proc_TLP_data_reg_61__4346), + .R(com_cmm_rst_267) + ); + FDRE com_cmm_u_tx_pkt_proc_TLP_data_reg_62_ ( + .CE(com_cmm_u_tx_pkt_proc_N_49941_i_4357), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_tx_pkt_proc_TLP_data_reg_10_62_), + .Q(com_cmm_u_tx_pkt_proc_TLP_data_reg_62__4347), + .R(com_cmm_rst_267) + ); + FDRE com_cmm_u_tx_pkt_proc_TLP_data_reg_63_ ( + .CE(com_cmm_u_tx_pkt_proc_N_49941_i_4357), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_tx_pkt_proc_TLP_data_reg_10_63_), + .Q(com_cmm_u_tx_pkt_proc_TLP_data_reg_63__4348), + .R(com_cmm_rst_267) + ); + defparam com_cmm_u_tx_pkt_proc_cmmt_trem_n_0_sqmuxa_0_a2_0_a3_0_a2_0_a3.INIT = 4'h8; + LUT2 com_cmm_u_tx_pkt_proc_cmmt_trem_n_0_sqmuxa_0_a2_0_a3_0_a2_0_a3 ( + .I0(com_req_pkt_tx), + .I1(com_state_0_), + .O(com_cmmt_trem_n_0_sqmuxa) + ); + defparam com_cmm_u_tx_pkt_proc_next_state_0_i_0_0_0_o3_2_.INIT = 4'h8; + LUT2 com_cmm_u_tx_pkt_proc_next_state_0_i_0_0_0_o3_2_ ( + .I0(com_tlp_data_0_), + .I1(com_tlp_data_29_), + .O(com_cmm_u_tx_pkt_proc_N_48955_i) + ); + defparam com_cmm_u_tx_pkt_proc_cmmt_td_0_i_m2_i_m2_i_m2_i_m3_0_0_.INIT = 8'hAC; + LUT3 com_cmm_u_tx_pkt_proc_cmmt_td_0_i_m2_i_m2_i_m2_i_m3_0_0_ ( + .I0(com_cmm_tlp_data_32_), + .I1(com_cmm_u_tx_pkt_proc_TLP_data_reg_32__4322), + .I2(com_state_0_), + .O(com_N_51600) + ); + defparam com_cmm_u_tx_pkt_proc_cmmt_td_0_i_m2_i_m2_i_m2_i_m3_0_1_.INIT = 8'hAC; + LUT3 com_cmm_u_tx_pkt_proc_cmmt_td_0_i_m2_i_m2_i_m2_i_m3_0_1_ ( + .I0(com_cmm_tlp_data_33_), + .I1(com_cmm_u_tx_pkt_proc_TLP_data_reg_33__4323), + .I2(com_state_0_), + .O(com_N_51601) + ); + defparam com_cmm_u_tx_pkt_proc_cmmt_td_0_i_m2_i_m2_i_m2_i_m3_0_2_.INIT = 8'hAC; + LUT3 com_cmm_u_tx_pkt_proc_cmmt_td_0_i_m2_i_m2_i_m2_i_m3_0_2_ ( + .I0(com_cmm_tlp_data_34_), + .I1(com_cmm_u_tx_pkt_proc_TLP_data_reg_34__4324), + .I2(com_state_0_), + .O(com_N_51602) + ); + defparam com_cmm_u_tx_pkt_proc_cmmt_td_0_i_m2_i_m2_i_m2_i_m3_0_3_.INIT = 8'hAC; + LUT3 com_cmm_u_tx_pkt_proc_cmmt_td_0_i_m2_i_m2_i_m2_i_m3_0_3_ ( + .I0(com_cmm_tlp_data_35_), + .I1(com_cmm_u_tx_pkt_proc_TLP_data_reg_35__4325), + .I2(com_state_0_), + .O(com_N_51603) + ); + defparam com_cmm_u_tx_pkt_proc_cmmt_td_0_i_m2_i_m2_i_m2_i_m3_0_4_.INIT = 8'hAC; + LUT3 com_cmm_u_tx_pkt_proc_cmmt_td_0_i_m2_i_m2_i_m2_i_m3_0_4_ ( + .I0(com_cmm_tlp_data_36_), + .I1(com_cmm_u_tx_pkt_proc_TLP_data_reg_36__4326), + .I2(com_state_0_), + .O(com_N_51604) + ); + defparam com_cmm_u_tx_pkt_proc_cmmt_td_0_i_m2_i_m2_i_m2_i_m3_0_5_.INIT = 8'hAC; + LUT3 com_cmm_u_tx_pkt_proc_cmmt_td_0_i_m2_i_m2_i_m2_i_m3_0_5_ ( + .I0(com_cmm_tlp_data_37_), + .I1(com_cmm_u_tx_pkt_proc_TLP_data_reg_37__4327), + .I2(com_state_0_), + .O(com_N_51605) + ); + defparam com_cmm_u_tx_pkt_proc_cmmt_td_0_i_m2_i_m2_i_m2_i_m3_0_6_.INIT = 8'hAC; + LUT3 com_cmm_u_tx_pkt_proc_cmmt_td_0_i_m2_i_m2_i_m2_i_m3_0_6_ ( + .I0(com_cmm_tlp_data_38_), + .I1(com_cmm_u_tx_pkt_proc_TLP_data_reg_38__4328), + .I2(com_state_0_), + .O(com_N_51606) + ); + defparam com_cmm_u_tx_pkt_proc_cmmt_td_0_i_m2_i_m2_i_m2_i_m3_0_7_.INIT = 8'hAC; + LUT3 com_cmm_u_tx_pkt_proc_cmmt_td_0_i_m2_i_m2_i_m2_i_m3_0_7_ ( + .I0(com_cmm_tlp_data_39_), + .I1(com_cmm_u_tx_pkt_proc_TLP_data_reg_39__4329), + .I2(com_state_0_), + .O(com_N_51607) + ); + defparam com_cmm_u_tx_pkt_proc_cmmt_td_0_i_m2_i_m2_i_m2_i_m3_0_8_.INIT = 8'hAC; + LUT3 com_cmm_u_tx_pkt_proc_cmmt_td_0_i_m2_i_m2_i_m2_i_m3_0_8_ ( + .I0(com_cmm_tlp_data_40_), + .I1(com_cmm_u_tx_pkt_proc_TLP_data_reg_40__4330), + .I2(com_state_0_), + .O(com_N_51608) + ); + defparam com_cmm_u_tx_pkt_proc_cmmt_td_0_i_m2_i_m2_i_m2_i_m3_0_9_.INIT = 8'hAC; + LUT3 com_cmm_u_tx_pkt_proc_cmmt_td_0_i_m2_i_m2_i_m2_i_m3_0_9_ ( + .I0(com_cmm_tlp_data_41_), + .I1(com_cmm_u_tx_pkt_proc_TLP_data_reg_41__4331), + .I2(com_state_0_), + .O(com_N_51609) + ); + defparam com_cmm_u_tx_pkt_proc_cmmt_td_0_i_m2_i_m2_i_m2_i_m3_0_10_.INIT = 8'hAC; + LUT3 com_cmm_u_tx_pkt_proc_cmmt_td_0_i_m2_i_m2_i_m2_i_m3_0_10_ ( + .I0(com_cmm_tlp_data_42_), + .I1(com_cmm_u_tx_pkt_proc_TLP_data_reg_42__4332), + .I2(com_state_0_), + .O(com_N_51610) + ); + defparam com_cmm_u_tx_pkt_proc_cmmt_td_0_i_m2_i_m2_i_m2_i_m3_0_11_.INIT = 8'hAC; + LUT3 com_cmm_u_tx_pkt_proc_cmmt_td_0_i_m2_i_m2_i_m2_i_m3_0_11_ ( + .I0(com_cmm_tlp_data_43_), + .I1(com_cmm_u_tx_pkt_proc_TLP_data_reg_43__4333), + .I2(com_state_0_), + .O(com_N_51611) + ); + defparam com_cmm_u_tx_pkt_proc_cmmt_td_0_i_m2_i_m2_i_m2_i_m3_0_13_.INIT = 8'hAC; + LUT3 com_cmm_u_tx_pkt_proc_cmmt_td_0_i_m2_i_m2_i_m2_i_m3_0_13_ ( + .I0(com_cmm_tlp_data_45_), + .I1(com_cmm_u_tx_pkt_proc_TLP_data_reg_45__4334), + .I2(com_state_0_), + .O(com_N_51612) + ); + defparam com_cmm_u_tx_pkt_proc_cmmt_td_0_i_m2_i_m2_i_m2_i_m3_0_15_.INIT = 8'hAC; + LUT3 com_cmm_u_tx_pkt_proc_cmmt_td_0_i_m2_i_m2_i_m2_i_m3_0_15_ ( + .I0(com_cmm_tlp_data_47_), + .I1(com_cmm_u_tx_pkt_proc_TLP_data_reg_47__4335), + .I2(com_state_0_), + .O(com_N_51613) + ); + defparam com_cmm_u_tx_pkt_proc_cmmt_td_0_i_m2_i_m2_i_m2_i_m3_0_19_.INIT = 8'hAC; + LUT3 com_cmm_u_tx_pkt_proc_cmmt_td_0_i_m2_i_m2_i_m2_i_m3_0_19_ ( + .I0(com_cmm_tlp_data_51_), + .I1(com_cmm_u_tx_pkt_proc_TLP_data_reg_51__4336), + .I2(com_state_0_), + .O(com_N_51614) + ); + defparam com_cmm_u_tx_pkt_proc_cmmt_td_0_i_m2_i_m2_i_m2_i_m3_0_20_.INIT = 8'hAC; + LUT3 com_cmm_u_tx_pkt_proc_cmmt_td_0_i_m2_i_m2_i_m2_i_m3_0_20_ ( + .I0(com_cmm_tlp_data_52_), + .I1(com_cmm_u_tx_pkt_proc_TLP_data_reg_52__4337), + .I2(com_state_0_), + .O(com_N_51615) + ); + defparam com_cmm_u_tx_pkt_proc_cmmt_td_0_i_m2_i_m2_i_m2_i_m3_0_21_.INIT = 8'hAC; + LUT3 com_cmm_u_tx_pkt_proc_cmmt_td_0_i_m2_i_m2_i_m2_i_m3_0_21_ ( + .I0(com_cmm_tlp_data_53_), + .I1(com_cmm_u_tx_pkt_proc_TLP_data_reg_53__4338), + .I2(com_state_0_), + .O(com_N_51616) + ); + defparam com_cmm_u_tx_pkt_proc_cmmt_td_0_i_m2_i_m2_i_m2_i_m3_0_22_.INIT = 8'hAC; + LUT3 com_cmm_u_tx_pkt_proc_cmmt_td_0_i_m2_i_m2_i_m2_i_m3_0_22_ ( + .I0(com_cmm_tlp_data_54_), + .I1(com_cmm_u_tx_pkt_proc_TLP_data_reg_54__4339), + .I2(com_state_0_), + .O(com_N_51617) + ); + defparam com_cmm_u_tx_pkt_proc_cmmt_td_0_i_m2_i_m2_i_m2_i_m3_0_23_.INIT = 8'hAC; + LUT3 com_cmm_u_tx_pkt_proc_cmmt_td_0_i_m2_i_m2_i_m2_i_m3_0_23_ ( + .I0(com_cmm_tlp_data_55_), + .I1(com_cmm_u_tx_pkt_proc_TLP_data_reg_55__4340), + .I2(com_state_0_), + .O(com_N_51618) + ); + defparam com_cmm_u_tx_pkt_proc_cmmt_td_0_i_m2_i_m2_i_m2_i_m3_0_24_.INIT = 8'hAC; + LUT3 com_cmm_u_tx_pkt_proc_cmmt_td_0_i_m2_i_m2_i_m2_i_m3_0_24_ ( + .I0(com_cmm_tlp_data_56_), + .I1(com_cmm_u_tx_pkt_proc_TLP_data_reg_56__4341), + .I2(com_state_0_), + .O(com_N_51619) + ); + defparam com_cmm_u_tx_pkt_proc_cmmt_td_0_i_m2_i_m2_i_m2_i_m3_0_25_.INIT = 8'hAC; + LUT3 com_cmm_u_tx_pkt_proc_cmmt_td_0_i_m2_i_m2_i_m2_i_m3_0_25_ ( + .I0(com_cmm_tlp_data_57_), + .I1(com_cmm_u_tx_pkt_proc_TLP_data_reg_57__4342), + .I2(com_state_0_), + .O(com_N_51620) + ); + defparam com_cmm_u_tx_pkt_proc_cmmt_td_0_i_m2_i_m2_i_m2_i_m3_0_26_.INIT = 8'hAC; + LUT3 com_cmm_u_tx_pkt_proc_cmmt_td_0_i_m2_i_m2_i_m2_i_m3_0_26_ ( + .I0(com_cmm_tlp_data_58_), + .I1(com_cmm_u_tx_pkt_proc_TLP_data_reg_58__4343), + .I2(com_state_0_), + .O(com_N_51621) + ); + defparam com_cmm_u_tx_pkt_proc_cmmt_td_0_i_m2_i_m2_i_m2_i_m3_0_27_.INIT = 8'hAC; + LUT3 com_cmm_u_tx_pkt_proc_cmmt_td_0_i_m2_i_m2_i_m2_i_m3_0_27_ ( + .I0(com_cmm_tlp_data_59_), + .I1(com_cmm_u_tx_pkt_proc_TLP_data_reg_59__4344), + .I2(com_state_0_), + .O(com_N_51622) + ); + defparam com_cmm_u_tx_pkt_proc_cmmt_td_0_i_m2_i_m2_i_m2_i_m3_0_28_.INIT = 8'hAC; + LUT3 com_cmm_u_tx_pkt_proc_cmmt_td_0_i_m2_i_m2_i_m2_i_m3_0_28_ ( + .I0(com_cmm_tlp_data_60_), + .I1(com_cmm_u_tx_pkt_proc_TLP_data_reg_60__4345), + .I2(com_state_0_), + .O(com_N_51623) + ); + defparam com_cmm_u_tx_pkt_proc_cmmt_td_0_i_m2_i_m2_i_m2_i_m3_0_29_.INIT = 8'hAC; + LUT3 com_cmm_u_tx_pkt_proc_cmmt_td_0_i_m2_i_m2_i_m2_i_m3_0_29_ ( + .I0(com_cmm_tlp_data_61_), + .I1(com_cmm_u_tx_pkt_proc_TLP_data_reg_61__4346), + .I2(com_state_0_), + .O(com_N_51624) + ); + defparam com_cmm_u_tx_pkt_proc_cmmt_td_0_i_m2_i_m2_i_m2_i_m3_0_30_.INIT = 8'hAC; + LUT3 com_cmm_u_tx_pkt_proc_cmmt_td_0_i_m2_i_m2_i_m2_i_m3_0_30_ ( + .I0(com_cmm_tlp_data_62_), + .I1(com_cmm_u_tx_pkt_proc_TLP_data_reg_62__4347), + .I2(com_state_0_), + .O(com_N_51625) + ); + defparam com_cmm_u_tx_pkt_proc_cmmt_td_0_i_m2_i_m2_i_m2_i_m3_0_31_.INIT = 8'hAC; + LUT3 com_cmm_u_tx_pkt_proc_cmmt_td_0_i_m2_i_m2_i_m2_i_m3_0_31_ ( + .I0(com_cmm_tlp_data_63_), + .I1(com_cmm_u_tx_pkt_proc_TLP_data_reg_63__4348), + .I2(com_state_0_), + .O(com_N_51626) + ); + defparam com_cmm_u_tx_pkt_proc_cmmt_td_0_i_m2_i_m2_i_m2_i_m3_0_44_.INIT = 8'hAC; + LUT3 com_cmm_u_tx_pkt_proc_cmmt_td_0_i_m2_i_m2_i_m2_i_m3_0_44_ ( + .I0(com_cmm_tlp_data_12_), + .I1(com_cmm_u_tx_pkt_proc_TLP_data_reg_12__4349), + .I2(com_state_0_), + .O(com_N_51627) + ); + defparam com_cmm_u_tx_pkt_proc_cmmt_td_0_i_m2_i_m2_i_m2_i_m3_0_45_.INIT = 8'hAC; + LUT3 com_cmm_u_tx_pkt_proc_cmmt_td_0_i_m2_i_m2_i_m2_i_m3_0_45_ ( + .I0(com_cmm_tlp_data_13_), + .I1(com_cmm_u_tx_pkt_proc_TLP_data_reg_13__4350), + .I2(com_state_0_), + .O(com_N_51628) + ); + defparam com_cmm_u_tx_pkt_proc_cmmt_td_0_i_m2_i_m2_i_m2_i_m3_0_52_.INIT = 8'hAC; + LUT3 com_cmm_u_tx_pkt_proc_cmmt_td_0_i_m2_i_m2_i_m2_i_m3_0_52_ ( + .I0(com_cmm_tlp_data_20_), + .I1(com_cmm_u_tx_pkt_proc_TLP_data_reg_20__4351), + .I2(com_state_0_), + .O(com_N_51629) + ); + defparam com_cmm_u_tx_pkt_proc_cmmt_td_0_i_m2_i_m2_i_m2_i_m3_0_53_.INIT = 8'hAC; + LUT3 com_cmm_u_tx_pkt_proc_cmmt_td_0_i_m2_i_m2_i_m2_i_m3_0_53_ ( + .I0(com_cmm_tlp_data_21_), + .I1(com_cmm_u_tx_pkt_proc_TLP_data_reg_21__4352), + .I2(com_state_0_), + .O(com_N_51630) + ); + defparam com_cmm_u_tx_pkt_proc_cmmt_td_0_i_m2_i_m2_i_m2_i_m3_0_54_.INIT = 8'hAC; + LUT3 com_cmm_u_tx_pkt_proc_cmmt_td_0_i_m2_i_m2_i_m2_i_m3_0_54_ ( + .I0(com_cmm_tlp_data_22_), + .I1(com_cmm_u_tx_pkt_proc_TLP_data_reg_22__4353), + .I2(com_state_0_), + .O(com_N_51631) + ); + defparam com_cmm_u_tx_pkt_proc_cmmt_td_0_i_m2_i_m2_i_m2_i_m3_0_56_.INIT = 8'hAC; + LUT3 com_cmm_u_tx_pkt_proc_cmmt_td_0_i_m2_i_m2_i_m2_i_m3_0_56_ ( + .I0(com_cmm_tlp_data_24_), + .I1(com_cmm_u_tx_pkt_proc_TLP_data_reg_24__4354), + .I2(com_state_0_), + .O(com_N_51632) + ); + defparam com_cmm_u_tx_pkt_proc_cmmt_td_0_i_m2_i_m2_i_m2_i_m3_0_58_.INIT = 8'hAC; + LUT3 com_cmm_u_tx_pkt_proc_cmmt_td_0_i_m2_i_m2_i_m2_i_m3_0_58_ ( + .I0(com_cmm_tlp_data_26_), + .I1(com_cmm_u_tx_pkt_proc_TLP_data_reg_26__4355), + .I2(com_state_0_), + .O(com_N_51633) + ); + defparam com_cmm_u_tx_pkt_proc_cmmt_td_0_i_m2_i_m2_i_m2_i_m3_0_60_.INIT = 8'hAC; + LUT3 com_cmm_u_tx_pkt_proc_cmmt_td_0_i_m2_i_m2_i_m2_i_m3_0_60_ ( + .I0(com_cmm_tlp_data_28_), + .I1(com_cmm_u_tx_pkt_proc_TLP_data_reg_28__4356), + .I2(com_state_0_), + .O(com_cmmt_td_0_i_m2_i_m2_i_m2_i_m3_0[60]) + ); + defparam com_cmm_u_tx_pkt_proc_next_state_0_i_0_0_0_o2_2_.INIT = 8'h2A; + LUT3 com_cmm_u_tx_pkt_proc_next_state_0_i_0_0_0_o2_2_ ( + .I0(com_N_48836_i), + .I1(com_state_2_), + .I2(com_cmmt_tdst_rdy), + .O(com_cmm_u_tx_pkt_proc_N_48856_i) + ); + defparam com_cmm_u_tx_pkt_proc_next_state_0_i_0_0_0_a2_0_.INIT = 16'h0004; + LUT4 com_cmm_u_tx_pkt_proc_next_state_0_i_0_0_0_a2_0_ ( + .I0(com_gnt_pkt_tx), + .I1(com_state_0_), + .I2(com_cmm_u_tx_pkt_proc_state[1]), + .I3(com_cmmt_tdst_rdy), + .O(com_cmm_u_tx_pkt_proc_N_49512) + ); + defparam com_cmm_u_tx_pkt_proc_next_state_0_i_0_0_0_a2_0_1_0_.INIT = 8'h10; + LUT3 com_cmm_u_tx_pkt_proc_next_state_0_i_0_0_0_a2_0_1_0_ ( + .I0(com_gnt_pkt_tx), + .I1(com_state_2_), + .I2(com_cmmt_tdst_rdy), + .O(com_cmm_u_tx_pkt_proc_next_state_0_i_0_0_0_a2_0_1[0]) + ); + defparam com_cmm_u_tx_pkt_proc_cmmt_td_0_i_0_62_.INIT = 16'h4450; + LUT4 com_cmm_u_tx_pkt_proc_cmmt_td_0_i_0_62_ ( + .I0(com_N_48843_i), + .I1(com_tlp_data_0_), + .I2(com_TLP_data_reg_30_), + .I3(com_state_0_), + .O(com_N_39480_i) + ); + defparam com_cmm_u_tx_pkt_proc_N_49941_i.INIT = 8'hF1; + LUT3 com_cmm_u_tx_pkt_proc_N_49941_i ( + .I0(com_cmm_u_tx_pkt_proc_state[1]), + .I1(com_state_2_), + .I2(com_cmmt_tdst_rdy), + .O(com_cmm_u_tx_pkt_proc_N_49941_i_4357) + ); + defparam com_cmm_u_tx_pkt_proc_grant_reg_iv_0_0_0_a2.INIT = 8'h0B; + LUT3 com_cmm_u_tx_pkt_proc_grant_reg_iv_0_0_0_a2 ( + .I0(com_cmm_u_tx_pkt_proc_N_48955_i), + .I1(com_cmm_u_tx_pkt_proc_state[1]), + .I2(com_state_2_), + .O(com_grant_reg_iv_0_0_0_a2) + ); + defparam com_cmm_u_tx_pkt_proc_next_state_0_i_0_0_0_0_2_.INIT = 8'h51; + LUT3 com_cmm_u_tx_pkt_proc_next_state_0_i_0_0_0_0_2_ ( + .I0(com_state_0_), + .I1(com_cmm_u_tx_pkt_proc_state[1]), + .I2(com_cmmt_tdst_rdy), + .O(com_cmm_u_tx_pkt_proc_next_state_0_i_0_0_0_0[2]) + ); + defparam com_cmm_u_tx_pkt_proc_grant_reg_iv_0_0_0.INIT = 4'h4; + LUT2_L com_cmm_u_tx_pkt_proc_grant_reg_iv_0_0_0 ( + .I0(com_grant_reg_iv_0_0_0_a2), + .I1(com_cmmt_tdst_rdy), + .LO(com_cmm_u_tx_pkt_proc_N_8850_i) + ); + defparam com_cmm_u_tx_pkt_proc_next_state_0_i_0_0_0_2_.INIT = 16'hA080; + LUT4_L com_cmm_u_tx_pkt_proc_next_state_0_i_0_0_0_2_ ( + .I0(com_cmm_u_tx_pkt_proc_N_48856_i), + .I1(com_cmm_u_tx_pkt_proc_N_48955_i), + .I2(com_cmm_u_tx_pkt_proc_next_state_0_i_0_0_0_0[2]), + .I3(com_state_2_), + .LO(com_cmm_u_tx_pkt_proc_N_13621_i) + ); + defparam com_cmm_u_tx_pkt_proc_N_68961_i.INIT = 8'hAC; + LUT3_L com_cmm_u_tx_pkt_proc_N_68961_i ( + .I0(com_cmmt_trem_n_0_sqmuxa), + .I1(com_cmm_u_tx_pkt_proc_state[1]), + .I2(com_cmmt_tdst_rdy), + .LO(com_cmm_u_tx_pkt_proc_N_68961_i_4358) + ); + defparam com_cmm_u_tx_pkt_proc_N_68152_i.INIT = 16'hFFEC; + LUT4_L com_cmm_u_tx_pkt_proc_N_68152_i ( + .I0(com_N_48843_i), + .I1(com_cmm_u_tx_pkt_proc_N_49512), + .I2(com_cmm_u_tx_pkt_proc_next_state_0_i_0_0_0_a2_0_1[0]), + .I3(com_state_4_), + .LO(com_cmm_u_tx_pkt_proc_N_68152_i_4359) + ); + defparam com_cmm_u_tx_pkt_proc_N_39480_i_i.INIT = 4'h1; + LUT1_L com_cmm_u_tx_pkt_proc_N_39480_i_i ( + .I0(com_N_39480_i), + .LO(com_N_39480_i_i) + ); + defparam com_cmm_u_tx_pkt_proc_N_68483_i.INIT = 4'hB; + LUT2_L com_cmm_u_tx_pkt_proc_N_68483_i ( + .I0(com_N_48843_i), + .I1(com_cmmt_td_0_i_m2_i_m2_i_m2_i_m3_0[60]), + .LO(com_N_68483_i) + ); + defparam com_cmm_u_tx_pkt_proc_TLP_data_reg_10_0_a2_0_a2_0_a2_0_a2_63_.INIT = 4'h8; + LUT2_L com_cmm_u_tx_pkt_proc_TLP_data_reg_10_0_a2_0_a2_0_a2_0_a2_63_ ( + .I0(com_cmm_tlp_data_127_), + .I1(com_state_0_), + .LO(com_cmm_u_tx_pkt_proc_TLP_data_reg_10_63_) + ); + defparam com_cmm_u_tx_pkt_proc_TLP_data_reg_10_0_a2_0_a2_0_a2_0_a2_62_.INIT = 4'h8; + LUT2_L com_cmm_u_tx_pkt_proc_TLP_data_reg_10_0_a2_0_a2_0_a2_0_a2_62_ ( + .I0(com_cmm_tlp_data_126_), + .I1(com_state_0_), + .LO(com_cmm_u_tx_pkt_proc_TLP_data_reg_10_62_) + ); + defparam com_cmm_u_tx_pkt_proc_TLP_data_reg_10_0_a2_0_a2_0_a2_0_a2_61_.INIT = 4'h8; + LUT2_L com_cmm_u_tx_pkt_proc_TLP_data_reg_10_0_a2_0_a2_0_a2_0_a2_61_ ( + .I0(com_cmm_tlp_data_125_), + .I1(com_state_0_), + .LO(com_cmm_u_tx_pkt_proc_TLP_data_reg_10_61_) + ); + defparam com_cmm_u_tx_pkt_proc_TLP_data_reg_10_0_a2_0_a2_0_a2_0_a2_60_.INIT = 4'h8; + LUT2_L com_cmm_u_tx_pkt_proc_TLP_data_reg_10_0_a2_0_a2_0_a2_0_a2_60_ ( + .I0(com_cmm_tlp_data_124_), + .I1(com_state_0_), + .LO(com_cmm_u_tx_pkt_proc_TLP_data_reg_10_60_) + ); + defparam com_cmm_u_tx_pkt_proc_TLP_data_reg_10_0_a2_0_a2_0_a2_0_a2_59_.INIT = 4'h8; + LUT2_L com_cmm_u_tx_pkt_proc_TLP_data_reg_10_0_a2_0_a2_0_a2_0_a2_59_ ( + .I0(com_cmm_tlp_data_123_), + .I1(com_state_0_), + .LO(com_cmm_u_tx_pkt_proc_TLP_data_reg_10_59_) + ); + defparam com_cmm_u_tx_pkt_proc_TLP_data_reg_10_0_a2_0_a2_0_a2_0_a2_58_.INIT = 4'h8; + LUT2_L com_cmm_u_tx_pkt_proc_TLP_data_reg_10_0_a2_0_a2_0_a2_0_a2_58_ ( + .I0(com_cmm_tlp_data_122_), + .I1(com_state_0_), + .LO(com_cmm_u_tx_pkt_proc_TLP_data_reg_10_58_) + ); + defparam com_cmm_u_tx_pkt_proc_TLP_data_reg_10_0_a2_0_a2_0_a2_0_a2_57_.INIT = 4'h8; + LUT2_L com_cmm_u_tx_pkt_proc_TLP_data_reg_10_0_a2_0_a2_0_a2_0_a2_57_ ( + .I0(com_cmm_tlp_data_121_), + .I1(com_state_0_), + .LO(com_cmm_u_tx_pkt_proc_TLP_data_reg_10_57_) + ); + defparam com_cmm_u_tx_pkt_proc_TLP_data_reg_10_0_a2_0_a2_0_a2_0_a2_56_.INIT = 4'h8; + LUT2_L com_cmm_u_tx_pkt_proc_TLP_data_reg_10_0_a2_0_a2_0_a2_0_a2_56_ ( + .I0(com_cmm_tlp_data_120_), + .I1(com_state_0_), + .LO(com_cmm_u_tx_pkt_proc_TLP_data_reg_10_56_) + ); + defparam com_cmm_u_tx_pkt_proc_TLP_data_reg_10_0_a2_0_a2_0_a2_0_a2_55_.INIT = 4'h8; + LUT2_L com_cmm_u_tx_pkt_proc_TLP_data_reg_10_0_a2_0_a2_0_a2_0_a2_55_ ( + .I0(com_cmm_tlp_data_119_), + .I1(com_state_0_), + .LO(com_cmm_u_tx_pkt_proc_TLP_data_reg_10_55_) + ); + defparam com_cmm_u_tx_pkt_proc_TLP_data_reg_10_0_a2_0_a2_0_a2_0_a2_54_.INIT = 4'h8; + LUT2_L com_cmm_u_tx_pkt_proc_TLP_data_reg_10_0_a2_0_a2_0_a2_0_a2_54_ ( + .I0(com_cmm_tlp_data_118_), + .I1(com_state_0_), + .LO(com_cmm_u_tx_pkt_proc_TLP_data_reg_10_54_) + ); + defparam com_cmm_u_tx_pkt_proc_TLP_data_reg_10_0_a2_0_a2_0_a2_0_a2_53_.INIT = 4'h8; + LUT2_L com_cmm_u_tx_pkt_proc_TLP_data_reg_10_0_a2_0_a2_0_a2_0_a2_53_ ( + .I0(com_cmm_tlp_data_117_), + .I1(com_state_0_), + .LO(com_cmm_u_tx_pkt_proc_TLP_data_reg_10_53_) + ); + defparam com_cmm_u_tx_pkt_proc_TLP_data_reg_10_0_a2_0_a2_0_a2_0_a2_52_.INIT = 4'h8; + LUT2_L com_cmm_u_tx_pkt_proc_TLP_data_reg_10_0_a2_0_a2_0_a2_0_a2_52_ ( + .I0(com_cmm_tlp_data_116_), + .I1(com_state_0_), + .LO(com_cmm_u_tx_pkt_proc_TLP_data_reg_10_52_) + ); + defparam com_cmm_u_tx_pkt_proc_TLP_data_reg_10_0_a2_0_a2_0_a2_0_a2_51_.INIT = 4'h8; + LUT2_L com_cmm_u_tx_pkt_proc_TLP_data_reg_10_0_a2_0_a2_0_a2_0_a2_51_ ( + .I0(com_cmm_tlp_data_115_), + .I1(com_state_0_), + .LO(com_cmm_u_tx_pkt_proc_TLP_data_reg_10_51_) + ); + defparam com_cmm_u_tx_pkt_proc_TLP_data_reg_10_0_a2_0_a2_0_a2_0_a2_50_.INIT = 4'h8; + LUT2_L com_cmm_u_tx_pkt_proc_TLP_data_reg_10_0_a2_0_a2_0_a2_0_a2_50_ ( + .I0(com_cmm_tlp_data_114_), + .I1(com_state_0_), + .LO(com_cmm_u_tx_pkt_proc_TLP_data_reg_10_50_) + ); + defparam com_cmm_u_tx_pkt_proc_TLP_data_reg_10_0_a2_0_a2_0_a2_0_a2_49_.INIT = 4'h8; + LUT2_L com_cmm_u_tx_pkt_proc_TLP_data_reg_10_0_a2_0_a2_0_a2_0_a2_49_ ( + .I0(com_cmm_tlp_data_113_), + .I1(com_state_0_), + .LO(com_cmm_u_tx_pkt_proc_TLP_data_reg_10_49_) + ); + defparam com_cmm_u_tx_pkt_proc_TLP_data_reg_10_0_a2_0_a2_0_a2_0_a2_48_.INIT = 4'h8; + LUT2_L com_cmm_u_tx_pkt_proc_TLP_data_reg_10_0_a2_0_a2_0_a2_0_a2_48_ ( + .I0(com_cmm_tlp_data_112_), + .I1(com_state_0_), + .LO(com_cmm_u_tx_pkt_proc_TLP_data_reg_10_48_) + ); + defparam com_cmm_u_tx_pkt_proc_TLP_data_reg_10_0_a2_0_a2_0_a2_0_a2_47_.INIT = 4'h8; + LUT2_L com_cmm_u_tx_pkt_proc_TLP_data_reg_10_0_a2_0_a2_0_a2_0_a2_47_ ( + .I0(com_cmm_tlp_data_111_), + .I1(com_state_0_), + .LO(com_cmm_u_tx_pkt_proc_TLP_data_reg_10_47_) + ); + defparam com_cmm_u_tx_pkt_proc_TLP_data_reg_10_0_a2_0_a2_0_a2_0_a2_46_.INIT = 4'h8; + LUT2_L com_cmm_u_tx_pkt_proc_TLP_data_reg_10_0_a2_0_a2_0_a2_0_a2_46_ ( + .I0(com_cmm_tlp_data_110_), + .I1(com_state_0_), + .LO(com_cmm_u_tx_pkt_proc_TLP_data_reg_10_46_) + ); + defparam com_cmm_u_tx_pkt_proc_TLP_data_reg_10_0_a2_0_a2_0_a2_0_a2_45_.INIT = 4'h8; + LUT2_L com_cmm_u_tx_pkt_proc_TLP_data_reg_10_0_a2_0_a2_0_a2_0_a2_45_ ( + .I0(com_cmm_tlp_data_109_), + .I1(com_state_0_), + .LO(com_cmm_u_tx_pkt_proc_TLP_data_reg_10_45_) + ); + defparam com_cmm_u_tx_pkt_proc_TLP_data_reg_10_0_a2_0_a2_0_a2_0_a2_44_.INIT = 4'h8; + LUT2_L com_cmm_u_tx_pkt_proc_TLP_data_reg_10_0_a2_0_a2_0_a2_0_a2_44_ ( + .I0(com_cmm_tlp_data_108_), + .I1(com_state_0_), + .LO(com_cmm_u_tx_pkt_proc_TLP_data_reg_10_44_) + ); + defparam com_cmm_u_tx_pkt_proc_TLP_data_reg_10_0_a2_0_a2_0_a2_0_a2_43_.INIT = 4'h8; + LUT2_L com_cmm_u_tx_pkt_proc_TLP_data_reg_10_0_a2_0_a2_0_a2_0_a2_43_ ( + .I0(com_cmm_tlp_data_107_), + .I1(com_state_0_), + .LO(com_cmm_u_tx_pkt_proc_TLP_data_reg_10_43_) + ); + defparam com_cmm_u_tx_pkt_proc_TLP_data_reg_10_0_a2_0_a2_0_a2_0_a2_42_.INIT = 4'h8; + LUT2_L com_cmm_u_tx_pkt_proc_TLP_data_reg_10_0_a2_0_a2_0_a2_0_a2_42_ ( + .I0(com_cmm_tlp_data_106_), + .I1(com_state_0_), + .LO(com_cmm_u_tx_pkt_proc_TLP_data_reg_10_42_) + ); + defparam com_cmm_u_tx_pkt_proc_TLP_data_reg_10_0_a2_0_a2_0_a2_0_a2_41_.INIT = 4'h8; + LUT2_L com_cmm_u_tx_pkt_proc_TLP_data_reg_10_0_a2_0_a2_0_a2_0_a2_41_ ( + .I0(com_cmm_tlp_data_105_), + .I1(com_state_0_), + .LO(com_cmm_u_tx_pkt_proc_TLP_data_reg_10_41_) + ); + defparam com_cmm_u_tx_pkt_proc_TLP_data_reg_10_0_a2_0_a2_0_a2_0_a2_40_.INIT = 4'h8; + LUT2_L com_cmm_u_tx_pkt_proc_TLP_data_reg_10_0_a2_0_a2_0_a2_0_a2_40_ ( + .I0(com_cmm_tlp_data_104_), + .I1(com_state_0_), + .LO(com_cmm_u_tx_pkt_proc_TLP_data_reg_10_40_) + ); + defparam com_cmm_u_tx_pkt_proc_TLP_data_reg_10_0_a2_0_a2_0_a2_0_a2_39_.INIT = 4'h8; + LUT2_L com_cmm_u_tx_pkt_proc_TLP_data_reg_10_0_a2_0_a2_0_a2_0_a2_39_ ( + .I0(com_cmm_tlp_data_103_), + .I1(com_state_0_), + .LO(com_cmm_u_tx_pkt_proc_TLP_data_reg_10_39_) + ); + defparam com_cmm_u_tx_pkt_proc_TLP_data_reg_10_0_a2_0_a2_0_a2_0_a2_38_.INIT = 4'h8; + LUT2_L com_cmm_u_tx_pkt_proc_TLP_data_reg_10_0_a2_0_a2_0_a2_0_a2_38_ ( + .I0(com_cmm_tlp_data_102_), + .I1(com_state_0_), + .LO(com_cmm_u_tx_pkt_proc_TLP_data_reg_10_38_) + ); + defparam com_cmm_u_tx_pkt_proc_TLP_data_reg_10_0_a2_0_a2_0_a2_0_a2_37_.INIT = 4'h8; + LUT2_L com_cmm_u_tx_pkt_proc_TLP_data_reg_10_0_a2_0_a2_0_a2_0_a2_37_ ( + .I0(com_cmm_tlp_data_101_), + .I1(com_state_0_), + .LO(com_cmm_u_tx_pkt_proc_TLP_data_reg_10_37_) + ); + defparam com_cmm_u_tx_pkt_proc_TLP_data_reg_10_0_a2_0_a2_0_a2_0_a2_36_.INIT = 4'h8; + LUT2_L com_cmm_u_tx_pkt_proc_TLP_data_reg_10_0_a2_0_a2_0_a2_0_a2_36_ ( + .I0(com_cmm_tlp_data_100_), + .I1(com_state_0_), + .LO(com_cmm_u_tx_pkt_proc_TLP_data_reg_10_36_) + ); + defparam com_cmm_u_tx_pkt_proc_TLP_data_reg_10_0_a2_0_a2_0_a2_0_a2_35_.INIT = 4'h8; + LUT2_L com_cmm_u_tx_pkt_proc_TLP_data_reg_10_0_a2_0_a2_0_a2_0_a2_35_ ( + .I0(com_cmm_tlp_data_99_), + .I1(com_state_0_), + .LO(com_cmm_u_tx_pkt_proc_TLP_data_reg_10_35_) + ); + defparam com_cmm_u_tx_pkt_proc_TLP_data_reg_10_0_a2_0_a2_0_a2_0_a2_34_.INIT = 4'h8; + LUT2_L com_cmm_u_tx_pkt_proc_TLP_data_reg_10_0_a2_0_a2_0_a2_0_a2_34_ ( + .I0(com_cmm_tlp_data_98_), + .I1(com_state_0_), + .LO(com_cmm_u_tx_pkt_proc_TLP_data_reg_10_34_) + ); + defparam com_cmm_u_tx_pkt_proc_TLP_data_reg_10_0_a2_0_a2_0_a2_0_a2_33_.INIT = 4'h8; + LUT2_L com_cmm_u_tx_pkt_proc_TLP_data_reg_10_0_a2_0_a2_0_a2_0_a2_33_ ( + .I0(com_cmm_tlp_data_97_), + .I1(com_state_0_), + .LO(com_cmm_u_tx_pkt_proc_TLP_data_reg_10_33_) + ); + defparam com_cmm_u_tx_pkt_proc_TLP_data_reg_10_0_a2_0_a2_0_a2_0_a2_32_.INIT = 4'h8; + LUT2_L com_cmm_u_tx_pkt_proc_TLP_data_reg_10_0_a2_0_a2_0_a2_0_a2_32_ ( + .I0(com_cmm_tlp_data_96_), + .I1(com_state_0_), + .LO(com_cmm_u_tx_pkt_proc_TLP_data_reg_10_32_) + ); + defparam com_cmm_u_tx_pkt_proc_TLP_data_reg_10_i_0_0_31_.INIT = 16'h88A0; + LUT4_L com_cmm_u_tx_pkt_proc_TLP_data_reg_10_i_0_0_31_ ( + .I0(com_cmm_u_tx_pkt_proc_N_48856_i), + .I1(com_cmm_msi_data[7]), + .I2(com_cmm_tlp_data_95_), + .I3(com_cmm_u_tx_pkt_proc_state[1]), + .LO(com_cmm_u_tx_pkt_proc_N_28334_i) + ); + defparam com_cmm_u_tx_pkt_proc_TLP_data_reg_10_i_0_0_30_.INIT = 16'h88A0; + LUT4_L com_cmm_u_tx_pkt_proc_TLP_data_reg_10_i_0_0_30_ ( + .I0(com_cmm_u_tx_pkt_proc_N_48856_i), + .I1(com_cmm_msi_data[6]), + .I2(com_cmm_tlp_data_94_), + .I3(com_cmm_u_tx_pkt_proc_state[1]), + .LO(com_cmm_u_tx_pkt_proc_N_28332_i) + ); + defparam com_cmm_u_tx_pkt_proc_TLP_data_reg_10_i_0_0_29_.INIT = 16'h88A0; + LUT4_L com_cmm_u_tx_pkt_proc_TLP_data_reg_10_i_0_0_29_ ( + .I0(com_cmm_u_tx_pkt_proc_N_48856_i), + .I1(com_cmm_msi_data[5]), + .I2(com_cmm_tlp_data_93_), + .I3(com_cmm_u_tx_pkt_proc_state[1]), + .LO(com_cmm_u_tx_pkt_proc_N_28330_i) + ); + defparam com_cmm_u_tx_pkt_proc_TLP_data_reg_10_i_0_0_28_.INIT = 16'h88A0; + LUT4_L com_cmm_u_tx_pkt_proc_TLP_data_reg_10_i_0_0_28_ ( + .I0(com_cmm_u_tx_pkt_proc_N_48856_i), + .I1(com_cmm_msi_data[4]), + .I2(com_cmm_tlp_data_92_), + .I3(com_cmm_u_tx_pkt_proc_state[1]), + .LO(com_cmm_u_tx_pkt_proc_N_28328_i) + ); + defparam com_cmm_u_tx_pkt_proc_TLP_data_reg_10_i_0_0_27_.INIT = 16'h88A0; + LUT4_L com_cmm_u_tx_pkt_proc_TLP_data_reg_10_i_0_0_27_ ( + .I0(com_cmm_u_tx_pkt_proc_N_48856_i), + .I1(com_cmm_msi_data[3]), + .I2(com_cmm_tlp_data_91_), + .I3(com_cmm_u_tx_pkt_proc_state[1]), + .LO(com_cmm_u_tx_pkt_proc_N_28326_i) + ); + defparam com_cmm_u_tx_pkt_proc_TLP_data_reg_10_i_0_0_26_.INIT = 16'h88A0; + LUT4_L com_cmm_u_tx_pkt_proc_TLP_data_reg_10_i_0_0_26_ ( + .I0(com_cmm_u_tx_pkt_proc_N_48856_i), + .I1(com_cmm_msi_data[2]), + .I2(com_cmm_tlp_data_90_), + .I3(com_cmm_u_tx_pkt_proc_state[1]), + .LO(com_cmm_u_tx_pkt_proc_N_28324_i) + ); + defparam com_cmm_u_tx_pkt_proc_TLP_data_reg_10_i_0_0_25_.INIT = 16'h88A0; + LUT4_L com_cmm_u_tx_pkt_proc_TLP_data_reg_10_i_0_0_25_ ( + .I0(com_cmm_u_tx_pkt_proc_N_48856_i), + .I1(com_cmm_msi_data[1]), + .I2(com_cmm_tlp_data_89_), + .I3(com_cmm_u_tx_pkt_proc_state[1]), + .LO(com_cmm_u_tx_pkt_proc_N_28322_i) + ); + defparam com_cmm_u_tx_pkt_proc_TLP_data_reg_10_i_0_0_24_.INIT = 16'h88A0; + LUT4_L com_cmm_u_tx_pkt_proc_TLP_data_reg_10_i_0_0_24_ ( + .I0(com_cmm_u_tx_pkt_proc_N_48856_i), + .I1(com_cmm_msi_data[0]), + .I2(com_cmm_tlp_data_88_), + .I3(com_cmm_u_tx_pkt_proc_state[1]), + .LO(com_cmm_u_tx_pkt_proc_N_28320_i) + ); + defparam com_cmm_u_tx_pkt_proc_TLP_data_reg_10_i_0_0_23_.INIT = 16'h88A0; + LUT4_L com_cmm_u_tx_pkt_proc_TLP_data_reg_10_i_0_0_23_ ( + .I0(com_cmm_u_tx_pkt_proc_N_48856_i), + .I1(com_cmm_msi_data[15]), + .I2(com_cmm_tlp_data_87_), + .I3(com_cmm_u_tx_pkt_proc_state[1]), + .LO(com_cmm_u_tx_pkt_proc_N_28318_i) + ); + defparam com_cmm_u_tx_pkt_proc_TLP_data_reg_10_i_0_0_22_.INIT = 16'h88A0; + LUT4_L com_cmm_u_tx_pkt_proc_TLP_data_reg_10_i_0_0_22_ ( + .I0(com_cmm_u_tx_pkt_proc_N_48856_i), + .I1(com_cmm_msi_data[14]), + .I2(com_cmm_tlp_data_86_), + .I3(com_cmm_u_tx_pkt_proc_state[1]), + .LO(com_cmm_u_tx_pkt_proc_N_28316_i) + ); + defparam com_cmm_u_tx_pkt_proc_TLP_data_reg_10_i_0_0_21_.INIT = 16'h88A0; + LUT4_L com_cmm_u_tx_pkt_proc_TLP_data_reg_10_i_0_0_21_ ( + .I0(com_cmm_u_tx_pkt_proc_N_48856_i), + .I1(com_cmm_msi_data[13]), + .I2(com_cmm_tlp_data_85_), + .I3(com_cmm_u_tx_pkt_proc_state[1]), + .LO(com_cmm_u_tx_pkt_proc_N_28314_i) + ); + defparam com_cmm_u_tx_pkt_proc_TLP_data_reg_10_i_0_0_20_.INIT = 16'h88A0; + LUT4_L com_cmm_u_tx_pkt_proc_TLP_data_reg_10_i_0_0_20_ ( + .I0(com_cmm_u_tx_pkt_proc_N_48856_i), + .I1(com_cmm_msi_data[12]), + .I2(com_cmm_tlp_data_84_), + .I3(com_cmm_u_tx_pkt_proc_state[1]), + .LO(com_cmm_u_tx_pkt_proc_N_28312_i) + ); + defparam com_cmm_u_tx_pkt_proc_TLP_data_reg_10_i_0_0_19_.INIT = 16'h88A0; + LUT4_L com_cmm_u_tx_pkt_proc_TLP_data_reg_10_i_0_0_19_ ( + .I0(com_cmm_u_tx_pkt_proc_N_48856_i), + .I1(com_cmm_msi_data[11]), + .I2(com_cmm_tlp_data_83_), + .I3(com_cmm_u_tx_pkt_proc_state[1]), + .LO(com_cmm_u_tx_pkt_proc_N_28310_i) + ); + defparam com_cmm_u_tx_pkt_proc_TLP_data_reg_10_i_0_0_18_.INIT = 16'h88A0; + LUT4_L com_cmm_u_tx_pkt_proc_TLP_data_reg_10_i_0_0_18_ ( + .I0(com_cmm_u_tx_pkt_proc_N_48856_i), + .I1(com_cmm_msi_data[10]), + .I2(com_cmm_tlp_data_82_), + .I3(com_cmm_u_tx_pkt_proc_state[1]), + .LO(com_cmm_u_tx_pkt_proc_N_28308_i) + ); + defparam com_cmm_u_tx_pkt_proc_TLP_data_reg_10_i_0_0_17_.INIT = 16'h88A0; + LUT4_L com_cmm_u_tx_pkt_proc_TLP_data_reg_10_i_0_0_17_ ( + .I0(com_cmm_u_tx_pkt_proc_N_48856_i), + .I1(com_cmm_msi_data[9]), + .I2(com_cmm_tlp_data_81_), + .I3(com_cmm_u_tx_pkt_proc_state[1]), + .LO(com_cmm_u_tx_pkt_proc_N_28306_i) + ); + defparam com_cmm_u_tx_pkt_proc_TLP_data_reg_10_i_0_0_16_.INIT = 16'h88A0; + LUT4_L com_cmm_u_tx_pkt_proc_TLP_data_reg_10_i_0_0_16_ ( + .I0(com_cmm_u_tx_pkt_proc_N_48856_i), + .I1(com_cmm_msi_data[8]), + .I2(com_cmm_tlp_data_80_), + .I3(com_cmm_u_tx_pkt_proc_state[1]), + .LO(com_cmm_u_tx_pkt_proc_N_28304_i) + ); + defparam com_cmm_u_tx_pkt_proc_TLP_data_reg_10_0_a2_0_a2_0_a2_0_a2_15_.INIT = 4'h8; + LUT2_L com_cmm_u_tx_pkt_proc_TLP_data_reg_10_0_a2_0_a2_0_a2_0_a2_15_ ( + .I0(com_cmm_tlp_data_79_), + .I1(com_state_0_), + .LO(com_cmm_u_tx_pkt_proc_TLP_data_reg_10_15_) + ); + defparam com_cmm_u_tx_pkt_proc_TLP_data_reg_10_0_a2_0_a2_0_a2_0_a2_14_.INIT = 4'h8; + LUT2_L com_cmm_u_tx_pkt_proc_TLP_data_reg_10_0_a2_0_a2_0_a2_0_a2_14_ ( + .I0(com_cmm_tlp_data_78_), + .I1(com_state_0_), + .LO(com_cmm_u_tx_pkt_proc_TLP_data_reg_10_14_) + ); + defparam com_cmm_u_tx_pkt_proc_TLP_data_reg_10_0_a2_0_a2_0_a2_0_a2_13_.INIT = 4'h8; + LUT2_L com_cmm_u_tx_pkt_proc_TLP_data_reg_10_0_a2_0_a2_0_a2_0_a2_13_ ( + .I0(com_cmm_tlp_data_77_), + .I1(com_state_0_), + .LO(com_cmm_u_tx_pkt_proc_TLP_data_reg_10_13_) + ); + defparam com_cmm_u_tx_pkt_proc_TLP_data_reg_10_0_a2_0_a2_0_a2_0_a2_12_.INIT = 4'h8; + LUT2_L com_cmm_u_tx_pkt_proc_TLP_data_reg_10_0_a2_0_a2_0_a2_0_a2_12_ ( + .I0(com_cmm_tlp_data_76_), + .I1(com_state_0_), + .LO(com_cmm_u_tx_pkt_proc_TLP_data_reg_10_12_) + ); + defparam com_cmm_u_tx_pkt_proc_TLP_data_reg_10_0_a2_0_a2_0_a2_0_a2_11_.INIT = 4'h8; + LUT2_L com_cmm_u_tx_pkt_proc_TLP_data_reg_10_0_a2_0_a2_0_a2_0_a2_11_ ( + .I0(com_cmm_tlp_data_75_), + .I1(com_state_0_), + .LO(com_cmm_u_tx_pkt_proc_TLP_data_reg_10_11_) + ); + defparam com_cmm_u_tx_pkt_proc_TLP_data_reg_10_0_a2_0_a2_0_a2_0_a2_10_.INIT = 4'h8; + LUT2_L com_cmm_u_tx_pkt_proc_TLP_data_reg_10_0_a2_0_a2_0_a2_0_a2_10_ ( + .I0(com_cmm_tlp_data_74_), + .I1(com_state_0_), + .LO(com_cmm_u_tx_pkt_proc_TLP_data_reg_10_10_) + ); + defparam com_cmm_u_tx_pkt_proc_TLP_data_reg_10_0_a2_0_a2_0_a2_0_a2_9_.INIT = 4'h8; + LUT2_L com_cmm_u_tx_pkt_proc_TLP_data_reg_10_0_a2_0_a2_0_a2_0_a2_9_ ( + .I0(com_cmm_tlp_data_73_), + .I1(com_state_0_), + .LO(com_cmm_u_tx_pkt_proc_TLP_data_reg_10_9_) + ); + defparam com_cmm_u_tx_pkt_proc_TLP_data_reg_10_0_a2_0_a2_0_a2_0_a2_8_.INIT = 4'h8; + LUT2_L com_cmm_u_tx_pkt_proc_TLP_data_reg_10_0_a2_0_a2_0_a2_0_a2_8_ ( + .I0(com_cmm_tlp_data_72_), + .I1(com_state_0_), + .LO(com_cmm_u_tx_pkt_proc_TLP_data_reg_10_8_) + ); + defparam com_cmm_u_tx_pkt_proc_TLP_data_reg_10_0_a2_0_a2_0_a2_0_a2_7_.INIT = 4'h8; + LUT2_L com_cmm_u_tx_pkt_proc_TLP_data_reg_10_0_a2_0_a2_0_a2_0_a2_7_ ( + .I0(com_cmm_tlp_data_71_), + .I1(com_state_0_), + .LO(com_cmm_u_tx_pkt_proc_TLP_data_reg_10_7_) + ); + defparam com_cmm_u_tx_pkt_proc_TLP_data_reg_10_0_a2_0_a2_0_a2_0_a2_6_.INIT = 4'h8; + LUT2_L com_cmm_u_tx_pkt_proc_TLP_data_reg_10_0_a2_0_a2_0_a2_0_a2_6_ ( + .I0(com_cmm_tlp_data_70_), + .I1(com_state_0_), + .LO(com_cmm_u_tx_pkt_proc_TLP_data_reg_10_6_) + ); + defparam com_cmm_u_tx_pkt_proc_TLP_data_reg_10_0_a2_0_a2_0_a2_0_a2_5_.INIT = 4'h8; + LUT2_L com_cmm_u_tx_pkt_proc_TLP_data_reg_10_0_a2_0_a2_0_a2_0_a2_5_ ( + .I0(com_cmm_tlp_data_69_), + .I1(com_state_0_), + .LO(com_cmm_u_tx_pkt_proc_TLP_data_reg_10_5_) + ); + defparam com_cmm_u_tx_pkt_proc_TLP_data_reg_10_0_a2_0_a2_0_a2_0_a2_4_.INIT = 4'h8; + LUT2_L com_cmm_u_tx_pkt_proc_TLP_data_reg_10_0_a2_0_a2_0_a2_0_a2_4_ ( + .I0(com_cmm_tlp_data_68_), + .I1(com_state_0_), + .LO(com_cmm_u_tx_pkt_proc_TLP_data_reg_10_4_) + ); + defparam com_cmm_u_tx_pkt_proc_TLP_data_reg_10_0_a2_0_a2_0_a2_0_a2_3_.INIT = 4'h8; + LUT2_L com_cmm_u_tx_pkt_proc_TLP_data_reg_10_0_a2_0_a2_0_a2_0_a2_3_ ( + .I0(com_cmm_tlp_data_67_), + .I1(com_state_0_), + .LO(com_cmm_u_tx_pkt_proc_TLP_data_reg_10_3_) + ); + defparam com_cmm_u_tx_pkt_proc_TLP_data_reg_10_0_a2_0_a2_0_a2_0_a2_2_.INIT = 4'h8; + LUT2_L com_cmm_u_tx_pkt_proc_TLP_data_reg_10_0_a2_0_a2_0_a2_0_a2_2_ ( + .I0(com_cmm_tlp_data_66_), + .I1(com_state_0_), + .LO(com_cmm_u_tx_pkt_proc_TLP_data_reg_10_2_) + ); + defparam com_cmm_u_tx_pkt_proc_TLP_data_reg_10_0_a2_0_a2_0_a2_0_a2_1_.INIT = 4'h8; + LUT2_L com_cmm_u_tx_pkt_proc_TLP_data_reg_10_0_a2_0_a2_0_a2_0_a2_1_ ( + .I0(com_cmm_tlp_data_65_), + .I1(com_state_0_), + .LO(com_cmm_u_tx_pkt_proc_TLP_data_reg_10_1_) + ); + defparam com_cmm_u_tx_pkt_proc_TLP_data_reg_10_0_a2_0_a2_0_a2_0_a2_0_.INIT = 4'h8; + LUT2_L com_cmm_u_tx_pkt_proc_TLP_data_reg_10_0_a2_0_a2_0_a2_0_a2_0_ ( + .I0(com_cmm_tlp_data_64_), + .I1(com_state_0_), + .LO(com_cmm_u_tx_pkt_proc_TLP_data_reg_10_0_) + ); + FDC com_cmm_u_tx_pkt_proc_state_3_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_tx_pkt_proc_N_8850_i), + .Q(com_gnt_pkt_tx), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_tx_pkt_proc_state_2_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_tx_pkt_proc_N_13621_i), + .Q(com_state_2_), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_tx_pkt_proc_state_1_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_tx_pkt_proc_N_68961_i_4358), + .Q(com_cmm_u_tx_pkt_proc_state[1]), + .CLR(com_cmm_rst_267) + ); + FDP com_cmm_u_tx_pkt_proc_state_0_ ( + .PRE(com_cmm_rst_267), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_tx_pkt_proc_N_68152_i_4359), + .Q(com_state_0_) + ); + FDC com_cmm_u_tx_pkt_proc_state_4_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_gnt_pkt_tx), + .Q(com_state_4_), + .CLR(com_cmm_rst_267) + ); + defparam com_cmm_u_cfg_ctrl_next_state11_1_0_a2_0_a2_0_a2.INIT = 4'h1; + LUT2 com_cmm_u_cfg_ctrl_next_state11_1_0_a2_0_a2_0_a2 ( + .I0(com_cmm_bdf_err_rd_pack), + .I1(com_cmm_type1_type0_bar), + .O(com_cmm_next_state11_1) + ); + defparam com_cmm_u_cfg_ctrl_next_state_0_i_0_0_a2_0_1_1_.INIT = 4'h8; + LUT2 com_cmm_u_cfg_ctrl_next_state_0_i_0_0_a2_0_1_1_ ( + .I0(com_cmm_req_valid), + .I1(com_cmm_u_cfg_ctrl_state[0]), + .O(com_cmm_u_cfg_ctrl_N_49600_1) + ); + defparam com_cmm_u_cfg_ctrl_next_state_0_i_0_0_0_o3_2_.INIT = 4'h1; + LUT2_L com_cmm_u_cfg_ctrl_next_state_0_i_0_0_0_o3_2_ ( + .I0(com_cmm_cfg_rd), + .I1(com_cmm_cfg_wr), + .LO(com_cmm_u_cfg_ctrl_next_state_0_i_0_0_0_o3[2]) + ); + defparam com_cmm_u_cfg_ctrl_wrdata_0_a2_0_a2_0_a2_0_a2_5_.INIT = 4'h8; + LUT2 com_cmm_u_cfg_ctrl_wrdata_0_a2_0_a2_0_a2_0_a2_5_ ( + .I0(com_cmm_cfg_wr_data_29_), + .I1(com_cmm_state_1_), + .O(com_cmm_tlm2cfg_wrdata_5_) + ); + defparam com_cmm_u_cfg_ctrl_wrdata_0_a2_0_a2_0_a2_0_a2_6_.INIT = 4'h8; + LUT2 com_cmm_u_cfg_ctrl_wrdata_0_a2_0_a2_0_a2_0_a2_6_ ( + .I0(com_cmm_cfg_wr_data_30_), + .I1(com_cmm_state_1_), + .O(com_cmm_tlm2cfg_wrdata_6_) + ); + defparam com_cmm_u_cfg_ctrl_wrdata_0_a2_0_a2_0_a2_0_a2_7_.INIT = 4'h8; + LUT2 com_cmm_u_cfg_ctrl_wrdata_0_a2_0_a2_0_a2_0_a2_7_ ( + .I0(com_cmm_cfg_wr_data_31_), + .I1(com_cmm_state_1_), + .O(com_cmm_tlm2cfg_wrdata_7_) + ); + defparam com_cmm_u_cfg_ctrl_wrdata_0_a2_0_a2_0_a2_0_a2_0_a2_4_.INIT = 4'h8; + LUT2 com_cmm_u_cfg_ctrl_wrdata_0_a2_0_a2_0_a2_0_a2_0_a2_4_ ( + .I0(com_cmm_cfg_wr_data_28_), + .I1(com_cmm_state_1_), + .O(com_cmm_tlm2cfg_wrdata_4_) + ); + defparam com_cmm_u_cfg_ctrl_wrdata_0_a2_0_a2_0_a2_0_a2_0_a3_0_a2_0_a2_3_.INIT = 4'h8; + LUT2 com_cmm_u_cfg_ctrl_wrdata_0_a2_0_a2_0_a2_0_a2_0_a3_0_a2_0_a2_3_ ( + .I0(com_cmm_cfg_wr_data[27]), + .I1(com_cmm_state_1_), + .O(com_cmm_tlm2cfg_wrdata_3_) + ); + defparam com_cmm_u_cfg_ctrl_wrdata_0_a2_0_a2_0_a2_0_a3_0_a2_0_a2_2_.INIT = 4'h8; + LUT2 com_cmm_u_cfg_ctrl_wrdata_0_a2_0_a2_0_a2_0_a3_0_a2_0_a2_2_ ( + .I0(com_cmm_cfg_wr_data[26]), + .I1(com_cmm_state_1_), + .O(com_cmm_tlm2cfg_wrdata_2_) + ); + defparam com_cmm_u_cfg_ctrl_wrdata_0_a4_0_a2_0_a2_0_a3_0_a2_0_a2_1_.INIT = 4'h8; + LUT2 com_cmm_u_cfg_ctrl_wrdata_0_a4_0_a2_0_a2_0_a3_0_a2_0_a2_1_ ( + .I0(com_cmm_cfg_wr_data[25]), + .I1(com_cmm_state_1_), + .O(com_cmm_tlm2cfg_wrdata_1_) + ); + defparam com_cmm_u_cfg_ctrl_wrdata_0_a2_0_a2_0_a3_0_a2_0_a2_0_.INIT = 4'h8; + LUT2 com_cmm_u_cfg_ctrl_wrdata_0_a2_0_a2_0_a3_0_a2_0_a2_0_ ( + .I0(com_cmm_cfg_wr_data[24]), + .I1(com_cmm_state_1_), + .O(com_cmm_tlm2cfg_wrdata_0_) + ); + defparam com_cmm_u_cfg_ctrl_next_state_0_i_0_0_0_o2_2_.INIT = 16'h2F3F; + LUT4 com_cmm_u_cfg_ctrl_next_state_0_i_0_0_0_o2_2_ ( + .I0(com_cmm_u_cfg_ctrl_next_state_0_i_0_0_0_o3[2]), + .I1(com_cmm_posnd_wr_pack), + .I2(com_cmm_state_1_), + .I3(com_cmm_state_6_), + .O(com_cmm_u_cfg_ctrl_N_28302_i_i) + ); + defparam com_cmm_u_cfg_ctrl_N_67939_i.INIT = 16'hDFDD; + LUT4_L com_cmm_u_cfg_ctrl_N_67939_i ( + .I0(com_cmm_u_cfg_ctrl_N_28302_i_i), + .I1(com_cmm_u_cfg_ctrl_N_49544), + .I2(com_cmm_gnt_cfgctrl), + .I3(com_cmm_req_cfgctrl), + .LO(com_cmm_u_cfg_ctrl_N_67939_i_4360) + ); + defparam com_cmm_u_cfg_ctrl_N_69000_i.INIT = 16'hEAC0; + LUT4_L com_cmm_u_cfg_ctrl_N_69000_i ( + .I0(com_cmm_u_cfg_ctrl_N_28302_i_i), + .I1(com_cmm_u_cfg_ctrl_N_49600_1), + .I2(com_cmm_next_state11_1), + .I3(com_cmm_state_1_), + .LO(com_cmm_u_cfg_ctrl_N_69000_i_4361) + ); + defparam com_cmm_u_cfg_ctrl_N_68910_i.INIT = 8'hBA; + LUT3_L com_cmm_u_cfg_ctrl_N_68910_i ( + .I0(com_cmm_N_41751_i), + .I1(com_cmm_req_valid), + .I2(com_cmm_u_cfg_ctrl_state[0]), + .LO(com_cmm_u_cfg_ctrl_N_68910_i_4362) + ); + defparam com_cmm_u_cfg_ctrl_wrdata_0_a2_0_a2_0_a2_16_.INIT = 4'h8; + LUT2_L com_cmm_u_cfg_ctrl_wrdata_0_a2_0_a2_0_a2_16_ ( + .I0(com_cmm_cfg_wr_data_8_), + .I1(com_cmm_state_1_), + .LO(com_cmm_tlm2cfg_wrdata_16_) + ); + defparam com_cmm_u_cfg_ctrl_next_state_0_i_0_0_0_a2_0_2_.INIT = 8'hA8; + LUT3 com_cmm_u_cfg_ctrl_next_state_0_i_0_0_0_a2_0_2_ ( + .I0(com_cmm_u_cfg_ctrl_N_49600_1), + .I1(com_cmm_type1_type0_bar), + .I2(com_cmm_bdf_err_rd_pack), + .O(com_cmm_u_cfg_ctrl_N_49544) + ); + FDC com_cmm_u_cfg_ctrl_state_2_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cfg_ctrl_N_67939_i_4360), + .Q(com_cmm_req_cfgctrl), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cfg_ctrl_state_1_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cfg_ctrl_N_69000_i_4361), + .Q(com_cmm_state_1_), + .CLR(com_cmm_rst_267) + ); + FDP com_cmm_u_cfg_ctrl_state_0_ ( + .PRE(com_cmm_rst_267), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cfg_ctrl_N_68910_i_4362), + .Q(com_cmm_u_cfg_ctrl_state[0]) + ); + FDCE com_cmm_u_cfg_ctrl_cfg_rd_data_31_ ( + .CE(com_cmm_u_cfg_ctrl_N_28302_i_i_i_4363), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_cfg2tlm_rddata[31]), + .Q(com_cmm_cfg_rd_data[31]), + .CLR(com_cmm_rst_267) + ); + FDCE com_cmm_u_cfg_ctrl_cfg_rd_data_30_ ( + .CE(com_cmm_u_cfg_ctrl_N_28302_i_i_i_4363), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_cfg2tlm_rddata[30]), + .Q(com_cmm_cfg_rd_data[30]), + .CLR(com_cmm_rst_267) + ); + FDCE com_cmm_u_cfg_ctrl_cfg_rd_data_29_ ( + .CE(com_cmm_u_cfg_ctrl_N_28302_i_i_i_4363), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_cfg2tlm_rddata[29]), + .Q(com_cmm_cfg_rd_data[29]), + .CLR(com_cmm_rst_267) + ); + FDCE com_cmm_u_cfg_ctrl_cfg_rd_data_28_ ( + .CE(com_cmm_u_cfg_ctrl_N_28302_i_i_i_4363), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_cfg2tlm_rddata[28]), + .Q(com_cmm_cfg_rd_data[28]), + .CLR(com_cmm_rst_267) + ); + FDCE com_cmm_u_cfg_ctrl_cfg_rd_data_27_ ( + .CE(com_cmm_u_cfg_ctrl_N_28302_i_i_i_4363), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_cfg2tlm_rddata[27]), + .Q(com_cmm_cfg_rd_data[27]), + .CLR(com_cmm_rst_267) + ); + FDCE com_cmm_u_cfg_ctrl_cfg_rd_data_26_ ( + .CE(com_cmm_u_cfg_ctrl_N_28302_i_i_i_4363), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_cfg2tlm_rddata[26]), + .Q(com_cmm_cfg_rd_data[26]), + .CLR(com_cmm_rst_267) + ); + FDCE com_cmm_u_cfg_ctrl_cfg_rd_data_25_ ( + .CE(com_cmm_u_cfg_ctrl_N_28302_i_i_i_4363), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_cfg2tlm_rddata[25]), + .Q(com_cmm_cfg_rd_data[25]), + .CLR(com_cmm_rst_267) + ); + FDCE com_cmm_u_cfg_ctrl_cfg_rd_data_24_ ( + .CE(com_cmm_u_cfg_ctrl_N_28302_i_i_i_4363), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_cfg2tlm_rddata[24]), + .Q(com_cmm_cfg_rd_data[24]), + .CLR(com_cmm_rst_267) + ); + FDCE com_cmm_u_cfg_ctrl_cfg_rd_data_23_ ( + .CE(com_cmm_u_cfg_ctrl_N_28302_i_i_i_4363), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_cfg2tlm_rddata[23]), + .Q(com_cmm_cfg_rd_data[23]), + .CLR(com_cmm_rst_267) + ); + FDCE com_cmm_u_cfg_ctrl_cfg_rd_data_22_ ( + .CE(com_cmm_u_cfg_ctrl_N_28302_i_i_i_4363), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_cfg2tlm_rddata[22]), + .Q(com_cmm_cfg_rd_data[22]), + .CLR(com_cmm_rst_267) + ); + FDCE com_cmm_u_cfg_ctrl_cfg_rd_data_21_ ( + .CE(com_cmm_u_cfg_ctrl_N_28302_i_i_i_4363), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_cfg2tlm_rddata[21]), + .Q(com_cmm_cfg_rd_data[21]), + .CLR(com_cmm_rst_267) + ); + FDCE com_cmm_u_cfg_ctrl_cfg_rd_data_20_ ( + .CE(com_cmm_u_cfg_ctrl_N_28302_i_i_i_4363), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_cfg2tlm_rddata[20]), + .Q(com_cmm_cfg_rd_data[20]), + .CLR(com_cmm_rst_267) + ); + FDCE com_cmm_u_cfg_ctrl_cfg_rd_data_19_ ( + .CE(com_cmm_u_cfg_ctrl_N_28302_i_i_i_4363), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_cfg2tlm_rddata[19]), + .Q(com_cmm_cfg_rd_data[19]), + .CLR(com_cmm_rst_267) + ); + FDCE com_cmm_u_cfg_ctrl_cfg_rd_data_18_ ( + .CE(com_cmm_u_cfg_ctrl_N_28302_i_i_i_4363), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_cfg2tlm_rddata[18]), + .Q(com_cmm_cfg_rd_data[18]), + .CLR(com_cmm_rst_267) + ); + FDCE com_cmm_u_cfg_ctrl_cfg_rd_data_17_ ( + .CE(com_cmm_u_cfg_ctrl_N_28302_i_i_i_4363), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_cfg2tlm_rddata[17]), + .Q(com_cmm_cfg_rd_data[17]), + .CLR(com_cmm_rst_267) + ); + FDCE com_cmm_u_cfg_ctrl_cfg_rd_data_16_ ( + .CE(com_cmm_u_cfg_ctrl_N_28302_i_i_i_4363), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_cfg2tlm_rddata[16]), + .Q(com_cmm_cfg_rd_data[16]), + .CLR(com_cmm_rst_267) + ); + FDCE com_cmm_u_cfg_ctrl_cfg_rd_data_15_ ( + .CE(com_cmm_u_cfg_ctrl_N_28302_i_i_i_4363), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_cfg2tlm_rddata[15]), + .Q(com_cmm_cfg_rd_data[15]), + .CLR(com_cmm_rst_267) + ); + FDCE com_cmm_u_cfg_ctrl_cfg_rd_data_14_ ( + .CE(com_cmm_u_cfg_ctrl_N_28302_i_i_i_4363), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_cfg2tlm_rddata[14]), + .Q(com_cmm_cfg_rd_data[14]), + .CLR(com_cmm_rst_267) + ); + FDCE com_cmm_u_cfg_ctrl_cfg_rd_data_13_ ( + .CE(com_cmm_u_cfg_ctrl_N_28302_i_i_i_4363), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_cfg2tlm_rddata[13]), + .Q(com_cmm_cfg_rd_data[13]), + .CLR(com_cmm_rst_267) + ); + FDCE com_cmm_u_cfg_ctrl_cfg_rd_data_12_ ( + .CE(com_cmm_u_cfg_ctrl_N_28302_i_i_i_4363), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_cfg2tlm_rddata[12]), + .Q(com_cmm_cfg_rd_data[12]), + .CLR(com_cmm_rst_267) + ); + FDCE com_cmm_u_cfg_ctrl_cfg_rd_data_11_ ( + .CE(com_cmm_u_cfg_ctrl_N_28302_i_i_i_4363), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_cfg2tlm_rddata[11]), + .Q(com_cmm_cfg_rd_data[11]), + .CLR(com_cmm_rst_267) + ); + FDCE com_cmm_u_cfg_ctrl_cfg_rd_data_10_ ( + .CE(com_cmm_u_cfg_ctrl_N_28302_i_i_i_4363), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_cfg2tlm_rddata[10]), + .Q(com_cmm_cfg_rd_data[10]), + .CLR(com_cmm_rst_267) + ); + FDCE com_cmm_u_cfg_ctrl_cfg_rd_data_9_ ( + .CE(com_cmm_u_cfg_ctrl_N_28302_i_i_i_4363), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_cfg2tlm_rddata[9]), + .Q(com_cmm_cfg_rd_data[9]), + .CLR(com_cmm_rst_267) + ); + FDCE com_cmm_u_cfg_ctrl_cfg_rd_data_8_ ( + .CE(com_cmm_u_cfg_ctrl_N_28302_i_i_i_4363), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_cfg2tlm_rddata[8]), + .Q(com_cmm_cfg_rd_data[8]), + .CLR(com_cmm_rst_267) + ); + FDCE com_cmm_u_cfg_ctrl_cfg_rd_data_7_ ( + .CE(com_cmm_u_cfg_ctrl_N_28302_i_i_i_4363), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_cfg2tlm_rddata[7]), + .Q(com_cmm_cfg_rd_data[7]), + .CLR(com_cmm_rst_267) + ); + FDCE com_cmm_u_cfg_ctrl_cfg_rd_data_6_ ( + .CE(com_cmm_u_cfg_ctrl_N_28302_i_i_i_4363), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_cfg2tlm_rddata[6]), + .Q(com_cmm_cfg_rd_data[6]), + .CLR(com_cmm_rst_267) + ); + FDCE com_cmm_u_cfg_ctrl_cfg_rd_data_5_ ( + .CE(com_cmm_u_cfg_ctrl_N_28302_i_i_i_4363), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_cfg2tlm_rddata[5]), + .Q(com_cmm_cfg_rd_data[5]), + .CLR(com_cmm_rst_267) + ); + FDCE com_cmm_u_cfg_ctrl_cfg_rd_data_4_ ( + .CE(com_cmm_u_cfg_ctrl_N_28302_i_i_i_4363), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_cfg2tlm_rddata[4]), + .Q(com_cmm_cfg_rd_data[4]), + .CLR(com_cmm_rst_267) + ); + FDCE com_cmm_u_cfg_ctrl_cfg_rd_data_3_ ( + .CE(com_cmm_u_cfg_ctrl_N_28302_i_i_i_4363), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_cfg2tlm_rddata[3]), + .Q(com_cmm_cfg_rd_data[3]), + .CLR(com_cmm_rst_267) + ); + FDCE com_cmm_u_cfg_ctrl_cfg_rd_data_2_ ( + .CE(com_cmm_u_cfg_ctrl_N_28302_i_i_i_4363), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_cfg2tlm_rddata[2]), + .Q(com_cmm_cfg_rd_data[2]), + .CLR(com_cmm_rst_267) + ); + FDCE com_cmm_u_cfg_ctrl_cfg_rd_data_1_ ( + .CE(com_cmm_u_cfg_ctrl_N_28302_i_i_i_4363), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_cfg2tlm_rddata[1]), + .Q(com_cmm_cfg_rd_data[1]), + .CLR(com_cmm_rst_267) + ); + FDCE com_cmm_u_cfg_ctrl_cfg_rd_data_0_ ( + .CE(com_cmm_u_cfg_ctrl_N_28302_i_i_i_4363), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_cfg2tlm_rddata[0]), + .Q(com_cmm_cfg_rd_data[0]), + .CLR(com_cmm_rst_267) + ); + INV com_cmm_u_cfg_ctrl_N_28302_i_i_i ( + .I(com_cmm_u_cfg_ctrl_N_28302_i_i), + .O(com_cmm_u_cfg_ctrl_N_28302_i_i_i_4363) + ); + VCC com_cmm_u_cmm_decoder_VCC ( + .P(com_cmm_u_cmm_decoder_VCC_4448) + ); + GND com_cmm_u_cmm_decoder_GND ( + .G(com_cmm_u_cmm_decoder_GND_4478) + ); + MUXCY_L com_cmm_u_cmm_decoder_un10_bar45_64_hit_low_0_I_1 ( + .CI(com_cmm_u_cmm_decoder_VCC_4448), + .DI(com_cmm_u_cmm_decoder_GND_4478), + .LO(com_cmm_u_cmm_decoder_data_tmp_14[0]), + .S(com_cmm_u_cmm_decoder_N_107_13) + ); + MUXCY_L com_cmm_u_cmm_decoder_un10_bar45_64_hit_low_0_I_10 ( + .CI(com_cmm_u_cmm_decoder_data_tmp_14[0]), + .DI(com_cmm_u_cmm_decoder_GND_4478), + .LO(com_cmm_u_cmm_decoder_data_tmp_15[1]), + .S(com_cmm_u_cmm_decoder_N_27_9) + ); + MUXCY_L com_cmm_u_cmm_decoder_un10_bar45_64_hit_low_0_I_19 ( + .CI(com_cmm_u_cmm_decoder_data_tmp_15[1]), + .DI(com_cmm_u_cmm_decoder_GND_4478), + .LO(com_cmm_u_cmm_decoder_data_tmp_15[2]), + .S(com_cmm_u_cmm_decoder_N_3_9) + ); + MUXCY_L com_cmm_u_cmm_decoder_un10_bar45_64_hit_low_0_I_37 ( + .CI(com_cmm_u_cmm_decoder_data_tmp_14[10]), + .DI(com_cmm_u_cmm_decoder_GND_4478), + .LO(com_cmm_u_cmm_decoder_data_tmp_14[11]), + .S(com_cmm_u_cmm_decoder_N_19_9) + ); + MUXCY_L com_cmm_u_cmm_decoder_un10_bar45_64_hit_low_0_I_46 ( + .CI(com_cmm_u_cmm_decoder_data_tmp_15[4]), + .DI(com_cmm_u_cmm_decoder_GND_4478), + .LO(com_cmm_u_cmm_decoder_data_tmp_15[5]), + .S(com_cmm_u_cmm_decoder_N_59_9) + ); + MUXCY_L com_cmm_u_cmm_decoder_un10_bar45_64_hit_low_0_I_55 ( + .CI(com_cmm_u_cmm_decoder_data_tmp_15[5]), + .DI(com_cmm_u_cmm_decoder_GND_4478), + .LO(com_cmm_u_cmm_decoder_data_tmp_15[6]), + .S(com_cmm_u_cmm_decoder_N_35_9) + ); + MUXCY_L com_cmm_u_cmm_decoder_un10_bar45_64_hit_low_0_I_64 ( + .CI(com_cmm_u_cmm_decoder_data_tmp_14[11]), + .DI(com_cmm_u_cmm_decoder_GND_4478), + .LO(com_cmm_u_cmm_decoder_data_tmp_14[12]), + .S(com_cmm_u_cmm_decoder_N_11_10) + ); + MUXCY_L com_cmm_u_cmm_decoder_un10_bar45_64_hit_low_0_I_73 ( + .CI(com_cmm_u_cmm_decoder_data_tmp_15[6]), + .DI(com_cmm_u_cmm_decoder_GND_4478), + .LO(com_cmm_u_cmm_decoder_data_tmp_15[7]), + .S(com_cmm_u_cmm_decoder_N_51_9) + ); + MUXCY_L com_cmm_u_cmm_decoder_un10_bar45_64_hit_low_0_I_82 ( + .CI(com_cmm_u_cmm_decoder_data_tmp_15[8]), + .DI(com_cmm_u_cmm_decoder_GND_4478), + .LO(com_cmm_u_cmm_decoder_data_tmp_15[9]), + .S(com_cmm_u_cmm_decoder_N_91_9) + ); + MUXCY_L com_cmm_u_cmm_decoder_un10_bar45_64_hit_low_0_I_91 ( + .CI(com_cmm_u_cmm_decoder_data_tmp_15[9]), + .DI(com_cmm_u_cmm_decoder_GND_4478), + .LO(com_cmm_u_cmm_decoder_data_tmp_14[10]), + .S(com_cmm_u_cmm_decoder_N_67_9) + ); + MUXCY_L com_cmm_u_cmm_decoder_un10_bar45_64_hit_low_0_I_100 ( + .CI(com_cmm_u_cmm_decoder_data_tmp_15[7]), + .DI(com_cmm_u_cmm_decoder_GND_4478), + .LO(com_cmm_u_cmm_decoder_data_tmp_15[8]), + .S(com_cmm_u_cmm_decoder_N_43_9) + ); + MUXCY_L com_cmm_u_cmm_decoder_un10_bar45_64_hit_low_0_I_109 ( + .CI(com_cmm_u_cmm_decoder_data_tmp_15[2]), + .DI(com_cmm_u_cmm_decoder_GND_4478), + .LO(com_cmm_u_cmm_decoder_data_tmp_15[3]), + .S(com_cmm_u_cmm_decoder_N_83_9) + ); + MUXCY_L com_cmm_u_cmm_decoder_un10_bar45_64_hit_low_0_I_118 ( + .CI(com_cmm_u_cmm_decoder_data_tmp_14[12]), + .DI(com_cmm_u_cmm_decoder_GND_4478), + .LO(com_cmm_u_cmm_decoder_data_tmp_3[13]), + .S(com_cmm_u_cmm_decoder_N_99_3) + ); + MUXCY_L com_cmm_u_cmm_decoder_un10_bar45_64_hit_low_0_I_127 ( + .CI(com_cmm_u_cmm_decoder_data_tmp_3[13]), + .DI(com_cmm_u_cmm_decoder_GND_4478), + .LO(com_cmm_u_cmm_decoder_data_tmp[14]), + .S(com_cmm_u_cmm_decoder_N_11) + ); + MUXCY_L com_cmm_u_cmm_decoder_un10_bar45_64_hit_low_0_I_136 ( + .CI(com_cmm_u_cmm_decoder_data_tmp_15[3]), + .DI(com_cmm_u_cmm_decoder_GND_4478), + .LO(com_cmm_u_cmm_decoder_data_tmp_15[4]), + .S(com_cmm_u_cmm_decoder_N_75_9) + ); + MUXCY_L com_cmm_u_cmm_decoder_un10_bar34_64_hit_low_0_I_1 ( + .CI(com_cmm_u_cmm_decoder_VCC_4448), + .DI(com_cmm_u_cmm_decoder_GND_4478), + .LO(com_cmm_u_cmm_decoder_data_tmp_13[0]), + .S(com_cmm_u_cmm_decoder_N_123) + ); + MUXCY_L com_cmm_u_cmm_decoder_un10_bar34_64_hit_low_0_I_10 ( + .CI(com_cmm_u_cmm_decoder_data_tmp_13[0]), + .DI(com_cmm_u_cmm_decoder_GND_4478), + .LO(com_cmm_u_cmm_decoder_data_tmp_14[1]), + .S(com_cmm_u_cmm_decoder_N_115) + ); + MUXCY_L com_cmm_u_cmm_decoder_un10_bar34_64_hit_low_0_I_19 ( + .CI(com_cmm_u_cmm_decoder_data_tmp_14[1]), + .DI(com_cmm_u_cmm_decoder_GND_4478), + .LO(com_cmm_u_cmm_decoder_data_tmp_14[2]), + .S(com_cmm_u_cmm_decoder_N_107) + ); + MUXCY_L com_cmm_u_cmm_decoder_un10_bar34_64_hit_low_0_I_37 ( + .CI(com_cmm_u_cmm_decoder_data_tmp_13[10]), + .DI(com_cmm_u_cmm_decoder_GND_4478), + .LO(com_cmm_u_cmm_decoder_data_tmp_13[11]), + .S(com_cmm_u_cmm_decoder_N_91) + ); + MUXCY_L com_cmm_u_cmm_decoder_un10_bar34_64_hit_low_0_I_46 ( + .CI(com_cmm_u_cmm_decoder_data_tmp_14[4]), + .DI(com_cmm_u_cmm_decoder_GND_4478), + .LO(com_cmm_u_cmm_decoder_data_tmp_14[5]), + .S(com_cmm_u_cmm_decoder_N_83) + ); + MUXCY_L com_cmm_u_cmm_decoder_un10_bar34_64_hit_low_0_I_55 ( + .CI(com_cmm_u_cmm_decoder_data_tmp_14[5]), + .DI(com_cmm_u_cmm_decoder_GND_4478), + .LO(com_cmm_u_cmm_decoder_data_tmp_14[6]), + .S(com_cmm_u_cmm_decoder_N_75) + ); + MUXCY_L com_cmm_u_cmm_decoder_un10_bar34_64_hit_low_0_I_64 ( + .CI(com_cmm_u_cmm_decoder_data_tmp_13[11]), + .DI(com_cmm_u_cmm_decoder_GND_4478), + .LO(com_cmm_u_cmm_decoder_data_tmp_13[12]), + .S(com_cmm_u_cmm_decoder_N_67) + ); + MUXCY_L com_cmm_u_cmm_decoder_un10_bar34_64_hit_low_0_I_73 ( + .CI(com_cmm_u_cmm_decoder_data_tmp_14[6]), + .DI(com_cmm_u_cmm_decoder_GND_4478), + .LO(com_cmm_u_cmm_decoder_data_tmp_14[7]), + .S(com_cmm_u_cmm_decoder_N_59) + ); + MUXCY_L com_cmm_u_cmm_decoder_un10_bar34_64_hit_low_0_I_82 ( + .CI(com_cmm_u_cmm_decoder_data_tmp_14[8]), + .DI(com_cmm_u_cmm_decoder_GND_4478), + .LO(com_cmm_u_cmm_decoder_data_tmp_14[9]), + .S(com_cmm_u_cmm_decoder_N_51) + ); + MUXCY_L com_cmm_u_cmm_decoder_un10_bar34_64_hit_low_0_I_91 ( + .CI(com_cmm_u_cmm_decoder_data_tmp_14[9]), + .DI(com_cmm_u_cmm_decoder_GND_4478), + .LO(com_cmm_u_cmm_decoder_data_tmp_13[10]), + .S(com_cmm_u_cmm_decoder_N_43) + ); + MUXCY_L com_cmm_u_cmm_decoder_un10_bar34_64_hit_low_0_I_100 ( + .CI(com_cmm_u_cmm_decoder_data_tmp_14[7]), + .DI(com_cmm_u_cmm_decoder_GND_4478), + .LO(com_cmm_u_cmm_decoder_data_tmp_14[8]), + .S(com_cmm_u_cmm_decoder_N_35) + ); + MUXCY_L com_cmm_u_cmm_decoder_un10_bar34_64_hit_low_0_I_109 ( + .CI(com_cmm_u_cmm_decoder_data_tmp_14[2]), + .DI(com_cmm_u_cmm_decoder_GND_4478), + .LO(com_cmm_u_cmm_decoder_data_tmp_14[3]), + .S(com_cmm_u_cmm_decoder_N_27) + ); + MUXCY_L com_cmm_u_cmm_decoder_un10_bar34_64_hit_low_0_I_118 ( + .CI(com_cmm_u_cmm_decoder_data_tmp_13[12]), + .DI(com_cmm_u_cmm_decoder_GND_4478), + .LO(com_cmm_u_cmm_decoder_data_tmp_2[13]), + .S(com_cmm_u_cmm_decoder_N_19) + ); + MUXCY_L com_cmm_u_cmm_decoder_un10_bar34_64_hit_low_0_I_127 ( + .CI(com_cmm_u_cmm_decoder_data_tmp_2[13]), + .DI(com_cmm_u_cmm_decoder_GND_4478), + .LO(com_cmm_u_cmm_decoder_data_tmp_0[14]), + .S(com_cmm_u_cmm_decoder_N_11_0) + ); + MUXCY_L com_cmm_u_cmm_decoder_un10_bar34_64_hit_low_0_I_136 ( + .CI(com_cmm_u_cmm_decoder_data_tmp_14[3]), + .DI(com_cmm_u_cmm_decoder_GND_4478), + .LO(com_cmm_u_cmm_decoder_data_tmp_14[4]), + .S(com_cmm_u_cmm_decoder_N_3) + ); + MUXCY_L com_cmm_u_cmm_decoder_un10_bar23_64_hit_low_0_I_1 ( + .CI(com_cmm_u_cmm_decoder_VCC_4448), + .DI(com_cmm_u_cmm_decoder_GND_4478), + .LO(com_cmm_u_cmm_decoder_data_tmp_12[0]), + .S(com_cmm_u_cmm_decoder_N_123_0) + ); + MUXCY_L com_cmm_u_cmm_decoder_un10_bar23_64_hit_low_0_I_10 ( + .CI(com_cmm_u_cmm_decoder_data_tmp_12[0]), + .DI(com_cmm_u_cmm_decoder_GND_4478), + .LO(com_cmm_u_cmm_decoder_data_tmp_13[1]), + .S(com_cmm_u_cmm_decoder_N_115_0) + ); + MUXCY_L com_cmm_u_cmm_decoder_un10_bar23_64_hit_low_0_I_19 ( + .CI(com_cmm_u_cmm_decoder_data_tmp_13[1]), + .DI(com_cmm_u_cmm_decoder_GND_4478), + .LO(com_cmm_u_cmm_decoder_data_tmp_13[2]), + .S(com_cmm_u_cmm_decoder_N_107_0) + ); + MUXCY_L com_cmm_u_cmm_decoder_un10_bar23_64_hit_low_0_I_37 ( + .CI(com_cmm_u_cmm_decoder_data_tmp_12[10]), + .DI(com_cmm_u_cmm_decoder_GND_4478), + .LO(com_cmm_u_cmm_decoder_data_tmp_12[11]), + .S(com_cmm_u_cmm_decoder_N_91_0) + ); + MUXCY_L com_cmm_u_cmm_decoder_un10_bar23_64_hit_low_0_I_46 ( + .CI(com_cmm_u_cmm_decoder_data_tmp_13[4]), + .DI(com_cmm_u_cmm_decoder_GND_4478), + .LO(com_cmm_u_cmm_decoder_data_tmp_13[5]), + .S(com_cmm_u_cmm_decoder_N_83_0) + ); + MUXCY_L com_cmm_u_cmm_decoder_un10_bar23_64_hit_low_0_I_55 ( + .CI(com_cmm_u_cmm_decoder_data_tmp_13[5]), + .DI(com_cmm_u_cmm_decoder_GND_4478), + .LO(com_cmm_u_cmm_decoder_data_tmp_13[6]), + .S(com_cmm_u_cmm_decoder_N_75_0) + ); + MUXCY_L com_cmm_u_cmm_decoder_un10_bar23_64_hit_low_0_I_64 ( + .CI(com_cmm_u_cmm_decoder_data_tmp_12[11]), + .DI(com_cmm_u_cmm_decoder_GND_4478), + .LO(com_cmm_u_cmm_decoder_data_tmp_12[12]), + .S(com_cmm_u_cmm_decoder_N_67_0) + ); + MUXCY_L com_cmm_u_cmm_decoder_un10_bar23_64_hit_low_0_I_73 ( + .CI(com_cmm_u_cmm_decoder_data_tmp_13[6]), + .DI(com_cmm_u_cmm_decoder_GND_4478), + .LO(com_cmm_u_cmm_decoder_data_tmp_13[7]), + .S(com_cmm_u_cmm_decoder_N_59_0) + ); + MUXCY_L com_cmm_u_cmm_decoder_un10_bar23_64_hit_low_0_I_82 ( + .CI(com_cmm_u_cmm_decoder_data_tmp_13[8]), + .DI(com_cmm_u_cmm_decoder_GND_4478), + .LO(com_cmm_u_cmm_decoder_data_tmp_13[9]), + .S(com_cmm_u_cmm_decoder_N_51_0) + ); + MUXCY_L com_cmm_u_cmm_decoder_un10_bar23_64_hit_low_0_I_91 ( + .CI(com_cmm_u_cmm_decoder_data_tmp_13[9]), + .DI(com_cmm_u_cmm_decoder_GND_4478), + .LO(com_cmm_u_cmm_decoder_data_tmp_12[10]), + .S(com_cmm_u_cmm_decoder_N_43_0) + ); + MUXCY_L com_cmm_u_cmm_decoder_un10_bar23_64_hit_low_0_I_100 ( + .CI(com_cmm_u_cmm_decoder_data_tmp_13[7]), + .DI(com_cmm_u_cmm_decoder_GND_4478), + .LO(com_cmm_u_cmm_decoder_data_tmp_13[8]), + .S(com_cmm_u_cmm_decoder_N_35_0) + ); + MUXCY_L com_cmm_u_cmm_decoder_un10_bar23_64_hit_low_0_I_109 ( + .CI(com_cmm_u_cmm_decoder_data_tmp_13[2]), + .DI(com_cmm_u_cmm_decoder_GND_4478), + .LO(com_cmm_u_cmm_decoder_data_tmp_13[3]), + .S(com_cmm_u_cmm_decoder_N_27_0) + ); + MUXCY_L com_cmm_u_cmm_decoder_un10_bar23_64_hit_low_0_I_118 ( + .CI(com_cmm_u_cmm_decoder_data_tmp_12[12]), + .DI(com_cmm_u_cmm_decoder_GND_4478), + .LO(com_cmm_u_cmm_decoder_data_tmp_1[13]), + .S(com_cmm_u_cmm_decoder_N_19_0) + ); + MUXCY_L com_cmm_u_cmm_decoder_un10_bar23_64_hit_low_0_I_127 ( + .CI(com_cmm_u_cmm_decoder_data_tmp_1[13]), + .DI(com_cmm_u_cmm_decoder_GND_4478), + .LO(com_cmm_u_cmm_decoder_data_tmp_1[14]), + .S(com_cmm_u_cmm_decoder_N_11_1) + ); + MUXCY_L com_cmm_u_cmm_decoder_un10_bar23_64_hit_low_0_I_136 ( + .CI(com_cmm_u_cmm_decoder_data_tmp_13[3]), + .DI(com_cmm_u_cmm_decoder_GND_4478), + .LO(com_cmm_u_cmm_decoder_data_tmp_13[4]), + .S(com_cmm_u_cmm_decoder_N_3_0) + ); + MUXCY_L com_cmm_u_cmm_decoder_un10_bar12_64_hit_low_0_I_1 ( + .CI(com_cmm_u_cmm_decoder_VCC_4448), + .DI(com_cmm_u_cmm_decoder_GND_4478), + .LO(com_cmm_u_cmm_decoder_data_tmp_11[0]), + .S(com_cmm_u_cmm_decoder_N_123_1) + ); + MUXCY_L com_cmm_u_cmm_decoder_un10_bar12_64_hit_low_0_I_10 ( + .CI(com_cmm_u_cmm_decoder_data_tmp_11[0]), + .DI(com_cmm_u_cmm_decoder_GND_4478), + .LO(com_cmm_u_cmm_decoder_data_tmp_12[1]), + .S(com_cmm_u_cmm_decoder_N_115_1) + ); + MUXCY_L com_cmm_u_cmm_decoder_un10_bar12_64_hit_low_0_I_19 ( + .CI(com_cmm_u_cmm_decoder_data_tmp_12[1]), + .DI(com_cmm_u_cmm_decoder_GND_4478), + .LO(com_cmm_u_cmm_decoder_data_tmp_12[2]), + .S(com_cmm_u_cmm_decoder_N_107_1) + ); + MUXCY_L com_cmm_u_cmm_decoder_un10_bar12_64_hit_low_0_I_37 ( + .CI(com_cmm_u_cmm_decoder_data_tmp_11[10]), + .DI(com_cmm_u_cmm_decoder_GND_4478), + .LO(com_cmm_u_cmm_decoder_data_tmp_11[11]), + .S(com_cmm_u_cmm_decoder_N_91_1) + ); + MUXCY_L com_cmm_u_cmm_decoder_un10_bar12_64_hit_low_0_I_46 ( + .CI(com_cmm_u_cmm_decoder_data_tmp_12[4]), + .DI(com_cmm_u_cmm_decoder_GND_4478), + .LO(com_cmm_u_cmm_decoder_data_tmp_12[5]), + .S(com_cmm_u_cmm_decoder_N_83_1) + ); + MUXCY_L com_cmm_u_cmm_decoder_un10_bar12_64_hit_low_0_I_55 ( + .CI(com_cmm_u_cmm_decoder_data_tmp_12[5]), + .DI(com_cmm_u_cmm_decoder_GND_4478), + .LO(com_cmm_u_cmm_decoder_data_tmp_12[6]), + .S(com_cmm_u_cmm_decoder_N_75_1) + ); + MUXCY_L com_cmm_u_cmm_decoder_un10_bar12_64_hit_low_0_I_64 ( + .CI(com_cmm_u_cmm_decoder_data_tmp_11[11]), + .DI(com_cmm_u_cmm_decoder_GND_4478), + .LO(com_cmm_u_cmm_decoder_data_tmp_11[12]), + .S(com_cmm_u_cmm_decoder_N_67_1) + ); + MUXCY_L com_cmm_u_cmm_decoder_un10_bar12_64_hit_low_0_I_73 ( + .CI(com_cmm_u_cmm_decoder_data_tmp_12[6]), + .DI(com_cmm_u_cmm_decoder_GND_4478), + .LO(com_cmm_u_cmm_decoder_data_tmp_12[7]), + .S(com_cmm_u_cmm_decoder_N_59_1) + ); + MUXCY_L com_cmm_u_cmm_decoder_un10_bar12_64_hit_low_0_I_82 ( + .CI(com_cmm_u_cmm_decoder_data_tmp_12[8]), + .DI(com_cmm_u_cmm_decoder_GND_4478), + .LO(com_cmm_u_cmm_decoder_data_tmp_12[9]), + .S(com_cmm_u_cmm_decoder_N_51_1) + ); + MUXCY_L com_cmm_u_cmm_decoder_un10_bar12_64_hit_low_0_I_91 ( + .CI(com_cmm_u_cmm_decoder_data_tmp_12[9]), + .DI(com_cmm_u_cmm_decoder_GND_4478), + .LO(com_cmm_u_cmm_decoder_data_tmp_11[10]), + .S(com_cmm_u_cmm_decoder_N_43_1) + ); + MUXCY_L com_cmm_u_cmm_decoder_un10_bar12_64_hit_low_0_I_100 ( + .CI(com_cmm_u_cmm_decoder_data_tmp_12[7]), + .DI(com_cmm_u_cmm_decoder_GND_4478), + .LO(com_cmm_u_cmm_decoder_data_tmp_12[8]), + .S(com_cmm_u_cmm_decoder_N_35_1) + ); + MUXCY_L com_cmm_u_cmm_decoder_un10_bar12_64_hit_low_0_I_109 ( + .CI(com_cmm_u_cmm_decoder_data_tmp_12[2]), + .DI(com_cmm_u_cmm_decoder_GND_4478), + .LO(com_cmm_u_cmm_decoder_data_tmp_12[3]), + .S(com_cmm_u_cmm_decoder_N_27_1) + ); + MUXCY_L com_cmm_u_cmm_decoder_un10_bar12_64_hit_low_0_I_118 ( + .CI(com_cmm_u_cmm_decoder_data_tmp_11[12]), + .DI(com_cmm_u_cmm_decoder_GND_4478), + .LO(com_cmm_u_cmm_decoder_data_tmp_0[13]), + .S(com_cmm_u_cmm_decoder_N_19_1) + ); + MUXCY_L com_cmm_u_cmm_decoder_un10_bar12_64_hit_low_0_I_127 ( + .CI(com_cmm_u_cmm_decoder_data_tmp_0[13]), + .DI(com_cmm_u_cmm_decoder_GND_4478), + .LO(com_cmm_u_cmm_decoder_data_tmp_2[14]), + .S(com_cmm_u_cmm_decoder_N_11_2) + ); + MUXCY_L com_cmm_u_cmm_decoder_un10_bar12_64_hit_low_0_I_136 ( + .CI(com_cmm_u_cmm_decoder_data_tmp_12[3]), + .DI(com_cmm_u_cmm_decoder_GND_4478), + .LO(com_cmm_u_cmm_decoder_data_tmp_12[4]), + .S(com_cmm_u_cmm_decoder_N_3_1) + ); + MUXCY_L com_cmm_u_cmm_decoder_un10_bar01_64_hit_low_0_I_1 ( + .CI(com_cmm_u_cmm_decoder_VCC_4448), + .DI(com_cmm_u_cmm_decoder_GND_4478), + .LO(com_cmm_u_cmm_decoder_data_tmp_10[0]), + .S(com_cmm_u_cmm_decoder_N_123_2) + ); + MUXCY_L com_cmm_u_cmm_decoder_un10_bar01_64_hit_low_0_I_10 ( + .CI(com_cmm_u_cmm_decoder_data_tmp_10[0]), + .DI(com_cmm_u_cmm_decoder_GND_4478), + .LO(com_cmm_u_cmm_decoder_data_tmp_11[1]), + .S(com_cmm_u_cmm_decoder_N_115_2) + ); + MUXCY_L com_cmm_u_cmm_decoder_un10_bar01_64_hit_low_0_I_19 ( + .CI(com_cmm_u_cmm_decoder_data_tmp_11[1]), + .DI(com_cmm_u_cmm_decoder_GND_4478), + .LO(com_cmm_u_cmm_decoder_data_tmp_11[2]), + .S(com_cmm_u_cmm_decoder_N_107_2) + ); + MUXCY_L com_cmm_u_cmm_decoder_un10_bar01_64_hit_low_0_I_37 ( + .CI(com_cmm_u_cmm_decoder_data_tmp_10[10]), + .DI(com_cmm_u_cmm_decoder_GND_4478), + .LO(com_cmm_u_cmm_decoder_data_tmp_10[11]), + .S(com_cmm_u_cmm_decoder_N_91_2) + ); + MUXCY_L com_cmm_u_cmm_decoder_un10_bar01_64_hit_low_0_I_46 ( + .CI(com_cmm_u_cmm_decoder_data_tmp_11[4]), + .DI(com_cmm_u_cmm_decoder_GND_4478), + .LO(com_cmm_u_cmm_decoder_data_tmp_11[5]), + .S(com_cmm_u_cmm_decoder_N_83_2) + ); + MUXCY_L com_cmm_u_cmm_decoder_un10_bar01_64_hit_low_0_I_55 ( + .CI(com_cmm_u_cmm_decoder_data_tmp_11[5]), + .DI(com_cmm_u_cmm_decoder_GND_4478), + .LO(com_cmm_u_cmm_decoder_data_tmp_11[6]), + .S(com_cmm_u_cmm_decoder_N_75_2) + ); + MUXCY_L com_cmm_u_cmm_decoder_un10_bar01_64_hit_low_0_I_64 ( + .CI(com_cmm_u_cmm_decoder_data_tmp_10[11]), + .DI(com_cmm_u_cmm_decoder_GND_4478), + .LO(com_cmm_u_cmm_decoder_data_tmp_10[12]), + .S(com_cmm_u_cmm_decoder_N_67_2) + ); + MUXCY_L com_cmm_u_cmm_decoder_un10_bar01_64_hit_low_0_I_73 ( + .CI(com_cmm_u_cmm_decoder_data_tmp_11[6]), + .DI(com_cmm_u_cmm_decoder_GND_4478), + .LO(com_cmm_u_cmm_decoder_data_tmp_11[7]), + .S(com_cmm_u_cmm_decoder_N_59_2) + ); + MUXCY_L com_cmm_u_cmm_decoder_un10_bar01_64_hit_low_0_I_82 ( + .CI(com_cmm_u_cmm_decoder_data_tmp_11[8]), + .DI(com_cmm_u_cmm_decoder_GND_4478), + .LO(com_cmm_u_cmm_decoder_data_tmp_11[9]), + .S(com_cmm_u_cmm_decoder_N_51_2) + ); + MUXCY_L com_cmm_u_cmm_decoder_un10_bar01_64_hit_low_0_I_91 ( + .CI(com_cmm_u_cmm_decoder_data_tmp_11[9]), + .DI(com_cmm_u_cmm_decoder_GND_4478), + .LO(com_cmm_u_cmm_decoder_data_tmp_10[10]), + .S(com_cmm_u_cmm_decoder_N_43_2) + ); + MUXCY_L com_cmm_u_cmm_decoder_un10_bar01_64_hit_low_0_I_100 ( + .CI(com_cmm_u_cmm_decoder_data_tmp_11[7]), + .DI(com_cmm_u_cmm_decoder_GND_4478), + .LO(com_cmm_u_cmm_decoder_data_tmp_11[8]), + .S(com_cmm_u_cmm_decoder_N_35_2) + ); + MUXCY_L com_cmm_u_cmm_decoder_un10_bar01_64_hit_low_0_I_109 ( + .CI(com_cmm_u_cmm_decoder_data_tmp_11[2]), + .DI(com_cmm_u_cmm_decoder_GND_4478), + .LO(com_cmm_u_cmm_decoder_data_tmp_11[3]), + .S(com_cmm_u_cmm_decoder_N_27_2) + ); + MUXCY_L com_cmm_u_cmm_decoder_un10_bar01_64_hit_low_0_I_118 ( + .CI(com_cmm_u_cmm_decoder_data_tmp_10[12]), + .DI(com_cmm_u_cmm_decoder_GND_4478), + .LO(com_cmm_u_cmm_decoder_data_tmp[13]), + .S(com_cmm_u_cmm_decoder_N_19_2) + ); + MUXCY_L com_cmm_u_cmm_decoder_un10_bar01_64_hit_low_0_I_127 ( + .CI(com_cmm_u_cmm_decoder_data_tmp[13]), + .DI(com_cmm_u_cmm_decoder_GND_4478), + .LO(com_cmm_u_cmm_decoder_data_tmp_3[14]), + .S(com_cmm_u_cmm_decoder_N_11_3) + ); + MUXCY_L com_cmm_u_cmm_decoder_un10_bar01_64_hit_low_0_I_136 ( + .CI(com_cmm_u_cmm_decoder_data_tmp_11[3]), + .DI(com_cmm_u_cmm_decoder_GND_4478), + .LO(com_cmm_u_cmm_decoder_data_tmp_11[4]), + .S(com_cmm_u_cmm_decoder_N_3_2) + ); + MUXCY_L com_cmm_u_cmm_decoder_un9_bar45_64_hit_high_0_I_1 ( + .CI(com_cmm_u_cmm_decoder_VCC_4448), + .DI(com_cmm_u_cmm_decoder_GND_4478), + .LO(com_cmm_u_cmm_decoder_data_tmp_9[0]), + .S(com_cmm_u_cmm_decoder_N_107_3) + ); + MUXCY_L com_cmm_u_cmm_decoder_un9_bar45_64_hit_high_0_I_19 ( + .CI(com_cmm_u_cmm_decoder_data_tmp_10[8]), + .DI(com_cmm_u_cmm_decoder_GND_4478), + .LO(com_cmm_u_cmm_decoder_data_tmp_10[9]), + .S(com_cmm_u_cmm_decoder_N_91_3) + ); + MUXCY_L com_cmm_u_cmm_decoder_un9_bar45_64_hit_high_0_I_28 ( + .CI(com_cmm_u_cmm_decoder_data_tmp_10[2]), + .DI(com_cmm_u_cmm_decoder_GND_4478), + .LO(com_cmm_u_cmm_decoder_data_tmp_10[3]), + .S(com_cmm_u_cmm_decoder_N_83_3) + ); + MUXCY_L com_cmm_u_cmm_decoder_un9_bar45_64_hit_high_0_I_37 ( + .CI(com_cmm_u_cmm_decoder_data_tmp_10[3]), + .DI(com_cmm_u_cmm_decoder_GND_4478), + .LO(com_cmm_u_cmm_decoder_data_tmp_10[4]), + .S(com_cmm_u_cmm_decoder_N_75_3) + ); + MUXCY_L com_cmm_u_cmm_decoder_un9_bar45_64_hit_high_0_I_46 ( + .CI(com_cmm_u_cmm_decoder_data_tmp_10[9]), + .DI(com_cmm_u_cmm_decoder_GND_4478), + .LO(com_cmm_u_cmm_decoder_data_tmp_9[10]), + .S(com_cmm_u_cmm_decoder_N_67_3) + ); + MUXCY_L com_cmm_u_cmm_decoder_un9_bar45_64_hit_high_0_I_55 ( + .CI(com_cmm_u_cmm_decoder_data_tmp_10[4]), + .DI(com_cmm_u_cmm_decoder_GND_4478), + .LO(com_cmm_u_cmm_decoder_data_tmp_10[5]), + .S(com_cmm_u_cmm_decoder_N_59_3) + ); + MUXCY_L com_cmm_u_cmm_decoder_un9_bar45_64_hit_high_0_I_64 ( + .CI(com_cmm_u_cmm_decoder_data_tmp_10[6]), + .DI(com_cmm_u_cmm_decoder_GND_4478), + .LO(com_cmm_u_cmm_decoder_data_tmp_10[7]), + .S(com_cmm_u_cmm_decoder_N_51_3) + ); + MUXCY_L com_cmm_u_cmm_decoder_un9_bar45_64_hit_high_0_I_73 ( + .CI(com_cmm_u_cmm_decoder_data_tmp_10[7]), + .DI(com_cmm_u_cmm_decoder_GND_4478), + .LO(com_cmm_u_cmm_decoder_data_tmp_10[8]), + .S(com_cmm_u_cmm_decoder_N_43_3) + ); + MUXCY_L com_cmm_u_cmm_decoder_un9_bar45_64_hit_high_0_I_82 ( + .CI(com_cmm_u_cmm_decoder_data_tmp_10[5]), + .DI(com_cmm_u_cmm_decoder_GND_4478), + .LO(com_cmm_u_cmm_decoder_data_tmp_10[6]), + .S(com_cmm_u_cmm_decoder_N_35_3) + ); + MUXCY_L com_cmm_u_cmm_decoder_un9_bar45_64_hit_high_0_I_91 ( + .CI(com_cmm_u_cmm_decoder_data_tmp_9[0]), + .DI(com_cmm_u_cmm_decoder_GND_4478), + .LO(com_cmm_u_cmm_decoder_data_tmp_10[1]), + .S(com_cmm_u_cmm_decoder_N_27_3) + ); + MUXCY_L com_cmm_u_cmm_decoder_un9_bar45_64_hit_high_0_I_100 ( + .CI(com_cmm_u_cmm_decoder_data_tmp_9[10]), + .DI(com_cmm_u_cmm_decoder_GND_4478), + .LO(com_cmm_u_cmm_decoder_data_tmp_9[11]), + .S(com_cmm_u_cmm_decoder_N_19_3) + ); + MUXCY_L com_cmm_u_cmm_decoder_un9_bar45_64_hit_high_0_I_109 ( + .CI(com_cmm_u_cmm_decoder_data_tmp_9[11]), + .DI(com_cmm_u_cmm_decoder_GND_4478), + .LO(com_cmm_u_cmm_decoder_data_tmp[12]), + .S(com_cmm_u_cmm_decoder_N_11_4) + ); + MUXCY_L com_cmm_u_cmm_decoder_un9_bar45_64_hit_high_0_I_118 ( + .CI(com_cmm_u_cmm_decoder_data_tmp_10[1]), + .DI(com_cmm_u_cmm_decoder_GND_4478), + .LO(com_cmm_u_cmm_decoder_data_tmp_10[2]), + .S(com_cmm_u_cmm_decoder_N_3_3) + ); + MUXCY_L com_cmm_u_cmm_decoder_bar0_eq_raddr_3_0_I_1 ( + .CI(com_cmm_u_cmm_decoder_VCC_4448), + .DI(com_cmm_u_cmm_decoder_GND_4478), + .LO(com_cmm_u_cmm_decoder_data_tmp_8[0]), + .S(com_cmm_u_cmm_decoder_N_107_4) + ); + MUXCY_L com_cmm_u_cmm_decoder_bar0_eq_raddr_3_0_I_19 ( + .CI(com_cmm_u_cmm_decoder_data_tmp_9[8]), + .DI(com_cmm_u_cmm_decoder_GND_4478), + .LO(com_cmm_u_cmm_decoder_data_tmp_9[9]), + .S(com_cmm_u_cmm_decoder_N_91_4) + ); + MUXCY_L com_cmm_u_cmm_decoder_bar0_eq_raddr_3_0_I_28 ( + .CI(com_cmm_u_cmm_decoder_data_tmp_9[2]), + .DI(com_cmm_u_cmm_decoder_GND_4478), + .LO(com_cmm_u_cmm_decoder_data_tmp_9[3]), + .S(com_cmm_u_cmm_decoder_N_83_4) + ); + MUXCY_L com_cmm_u_cmm_decoder_bar0_eq_raddr_3_0_I_37 ( + .CI(com_cmm_u_cmm_decoder_data_tmp_9[3]), + .DI(com_cmm_u_cmm_decoder_GND_4478), + .LO(com_cmm_u_cmm_decoder_data_tmp_9[4]), + .S(com_cmm_u_cmm_decoder_N_75_4) + ); + MUXCY_L com_cmm_u_cmm_decoder_bar0_eq_raddr_3_0_I_46 ( + .CI(com_cmm_u_cmm_decoder_data_tmp_9[9]), + .DI(com_cmm_u_cmm_decoder_GND_4478), + .LO(com_cmm_u_cmm_decoder_data_tmp_8[10]), + .S(com_cmm_u_cmm_decoder_N_67_4) + ); + MUXCY_L com_cmm_u_cmm_decoder_bar0_eq_raddr_3_0_I_55 ( + .CI(com_cmm_u_cmm_decoder_data_tmp_9[4]), + .DI(com_cmm_u_cmm_decoder_GND_4478), + .LO(com_cmm_u_cmm_decoder_data_tmp_9[5]), + .S(com_cmm_u_cmm_decoder_N_59_4) + ); + MUXCY_L com_cmm_u_cmm_decoder_bar0_eq_raddr_3_0_I_64 ( + .CI(com_cmm_u_cmm_decoder_data_tmp_9[6]), + .DI(com_cmm_u_cmm_decoder_GND_4478), + .LO(com_cmm_u_cmm_decoder_data_tmp_9[7]), + .S(com_cmm_u_cmm_decoder_N_51_4) + ); + MUXCY_L com_cmm_u_cmm_decoder_bar0_eq_raddr_3_0_I_73 ( + .CI(com_cmm_u_cmm_decoder_data_tmp_9[7]), + .DI(com_cmm_u_cmm_decoder_GND_4478), + .LO(com_cmm_u_cmm_decoder_data_tmp_9[8]), + .S(com_cmm_u_cmm_decoder_N_43_4) + ); + MUXCY_L com_cmm_u_cmm_decoder_bar0_eq_raddr_3_0_I_82 ( + .CI(com_cmm_u_cmm_decoder_data_tmp_9[5]), + .DI(com_cmm_u_cmm_decoder_GND_4478), + .LO(com_cmm_u_cmm_decoder_data_tmp_9[6]), + .S(com_cmm_u_cmm_decoder_N_35_4) + ); + MUXCY_L com_cmm_u_cmm_decoder_bar0_eq_raddr_3_0_I_91 ( + .CI(com_cmm_u_cmm_decoder_data_tmp_8[0]), + .DI(com_cmm_u_cmm_decoder_GND_4478), + .LO(com_cmm_u_cmm_decoder_data_tmp_9[1]), + .S(com_cmm_u_cmm_decoder_N_27_4) + ); + MUXCY_L com_cmm_u_cmm_decoder_bar0_eq_raddr_3_0_I_100 ( + .CI(com_cmm_u_cmm_decoder_data_tmp_8[10]), + .DI(com_cmm_u_cmm_decoder_GND_4478), + .LO(com_cmm_u_cmm_decoder_data_tmp_8[11]), + .S(com_cmm_u_cmm_decoder_N_19_4) + ); + MUXCY_L com_cmm_u_cmm_decoder_bar0_eq_raddr_3_0_I_109 ( + .CI(com_cmm_u_cmm_decoder_data_tmp_8[11]), + .DI(com_cmm_u_cmm_decoder_GND_4478), + .LO(com_cmm_u_cmm_decoder_data_tmp_0[12]), + .S(com_cmm_u_cmm_decoder_N_11_5) + ); + MUXCY_L com_cmm_u_cmm_decoder_bar0_eq_raddr_3_0_I_118 ( + .CI(com_cmm_u_cmm_decoder_data_tmp_9[1]), + .DI(com_cmm_u_cmm_decoder_GND_4478), + .LO(com_cmm_u_cmm_decoder_data_tmp_9[2]), + .S(com_cmm_u_cmm_decoder_N_3_4) + ); + MUXCY_L com_cmm_u_cmm_decoder_bar1_eq_raddr_3_0_I_1 ( + .CI(com_cmm_u_cmm_decoder_VCC_4448), + .DI(com_cmm_u_cmm_decoder_GND_4478), + .LO(com_cmm_u_cmm_decoder_data_tmp_7[0]), + .S(com_cmm_u_cmm_decoder_N_107_5) + ); + MUXCY_L com_cmm_u_cmm_decoder_bar1_eq_raddr_3_0_I_19 ( + .CI(com_cmm_u_cmm_decoder_data_tmp_8[8]), + .DI(com_cmm_u_cmm_decoder_GND_4478), + .LO(com_cmm_u_cmm_decoder_data_tmp_8[9]), + .S(com_cmm_u_cmm_decoder_N_91_5) + ); + MUXCY_L com_cmm_u_cmm_decoder_bar1_eq_raddr_3_0_I_28 ( + .CI(com_cmm_u_cmm_decoder_data_tmp_8[2]), + .DI(com_cmm_u_cmm_decoder_GND_4478), + .LO(com_cmm_u_cmm_decoder_data_tmp_8[3]), + .S(com_cmm_u_cmm_decoder_N_83_5) + ); + MUXCY_L com_cmm_u_cmm_decoder_bar1_eq_raddr_3_0_I_37 ( + .CI(com_cmm_u_cmm_decoder_data_tmp_8[3]), + .DI(com_cmm_u_cmm_decoder_GND_4478), + .LO(com_cmm_u_cmm_decoder_data_tmp_8[4]), + .S(com_cmm_u_cmm_decoder_N_75_5) + ); + MUXCY_L com_cmm_u_cmm_decoder_bar1_eq_raddr_3_0_I_46 ( + .CI(com_cmm_u_cmm_decoder_data_tmp_8[9]), + .DI(com_cmm_u_cmm_decoder_GND_4478), + .LO(com_cmm_u_cmm_decoder_data_tmp_7[10]), + .S(com_cmm_u_cmm_decoder_N_67_5) + ); + MUXCY_L com_cmm_u_cmm_decoder_bar1_eq_raddr_3_0_I_55 ( + .CI(com_cmm_u_cmm_decoder_data_tmp_8[4]), + .DI(com_cmm_u_cmm_decoder_GND_4478), + .LO(com_cmm_u_cmm_decoder_data_tmp_8[5]), + .S(com_cmm_u_cmm_decoder_N_59_5) + ); + MUXCY_L com_cmm_u_cmm_decoder_bar1_eq_raddr_3_0_I_64 ( + .CI(com_cmm_u_cmm_decoder_data_tmp_8[6]), + .DI(com_cmm_u_cmm_decoder_GND_4478), + .LO(com_cmm_u_cmm_decoder_data_tmp_8[7]), + .S(com_cmm_u_cmm_decoder_N_51_5) + ); + MUXCY_L com_cmm_u_cmm_decoder_bar1_eq_raddr_3_0_I_73 ( + .CI(com_cmm_u_cmm_decoder_data_tmp_8[7]), + .DI(com_cmm_u_cmm_decoder_GND_4478), + .LO(com_cmm_u_cmm_decoder_data_tmp_8[8]), + .S(com_cmm_u_cmm_decoder_N_43_5) + ); + MUXCY_L com_cmm_u_cmm_decoder_bar1_eq_raddr_3_0_I_82 ( + .CI(com_cmm_u_cmm_decoder_data_tmp_8[5]), + .DI(com_cmm_u_cmm_decoder_GND_4478), + .LO(com_cmm_u_cmm_decoder_data_tmp_8[6]), + .S(com_cmm_u_cmm_decoder_N_35_5) + ); + MUXCY_L com_cmm_u_cmm_decoder_bar1_eq_raddr_3_0_I_91 ( + .CI(com_cmm_u_cmm_decoder_data_tmp_7[0]), + .DI(com_cmm_u_cmm_decoder_GND_4478), + .LO(com_cmm_u_cmm_decoder_data_tmp_8[1]), + .S(com_cmm_u_cmm_decoder_N_27_5) + ); + MUXCY_L com_cmm_u_cmm_decoder_bar1_eq_raddr_3_0_I_100 ( + .CI(com_cmm_u_cmm_decoder_data_tmp_7[10]), + .DI(com_cmm_u_cmm_decoder_GND_4478), + .LO(com_cmm_u_cmm_decoder_data_tmp_7[11]), + .S(com_cmm_u_cmm_decoder_N_19_5) + ); + MUXCY_L com_cmm_u_cmm_decoder_bar1_eq_raddr_3_0_I_109 ( + .CI(com_cmm_u_cmm_decoder_data_tmp_7[11]), + .DI(com_cmm_u_cmm_decoder_GND_4478), + .LO(com_cmm_u_cmm_decoder_data_tmp_1[12]), + .S(com_cmm_u_cmm_decoder_N_11_6) + ); + MUXCY_L com_cmm_u_cmm_decoder_bar1_eq_raddr_3_0_I_118 ( + .CI(com_cmm_u_cmm_decoder_data_tmp_8[1]), + .DI(com_cmm_u_cmm_decoder_GND_4478), + .LO(com_cmm_u_cmm_decoder_data_tmp_8[2]), + .S(com_cmm_u_cmm_decoder_N_3_5) + ); + MUXCY_L com_cmm_u_cmm_decoder_bar2_eq_raddr_3_0_I_1 ( + .CI(com_cmm_u_cmm_decoder_VCC_4448), + .DI(com_cmm_u_cmm_decoder_GND_4478), + .LO(com_cmm_u_cmm_decoder_data_tmp_6[0]), + .S(com_cmm_u_cmm_decoder_N_107_6) + ); + MUXCY_L com_cmm_u_cmm_decoder_bar2_eq_raddr_3_0_I_19 ( + .CI(com_cmm_u_cmm_decoder_data_tmp_7[8]), + .DI(com_cmm_u_cmm_decoder_GND_4478), + .LO(com_cmm_u_cmm_decoder_data_tmp_7[9]), + .S(com_cmm_u_cmm_decoder_N_91_6) + ); + MUXCY_L com_cmm_u_cmm_decoder_bar2_eq_raddr_3_0_I_28 ( + .CI(com_cmm_u_cmm_decoder_data_tmp_7[2]), + .DI(com_cmm_u_cmm_decoder_GND_4478), + .LO(com_cmm_u_cmm_decoder_data_tmp_7[3]), + .S(com_cmm_u_cmm_decoder_N_83_6) + ); + MUXCY_L com_cmm_u_cmm_decoder_bar2_eq_raddr_3_0_I_37 ( + .CI(com_cmm_u_cmm_decoder_data_tmp_7[3]), + .DI(com_cmm_u_cmm_decoder_GND_4478), + .LO(com_cmm_u_cmm_decoder_data_tmp_7[4]), + .S(com_cmm_u_cmm_decoder_N_75_6) + ); + MUXCY_L com_cmm_u_cmm_decoder_bar2_eq_raddr_3_0_I_46 ( + .CI(com_cmm_u_cmm_decoder_data_tmp_7[9]), + .DI(com_cmm_u_cmm_decoder_GND_4478), + .LO(com_cmm_u_cmm_decoder_data_tmp_6[10]), + .S(com_cmm_u_cmm_decoder_N_67_6) + ); + MUXCY_L com_cmm_u_cmm_decoder_bar2_eq_raddr_3_0_I_55 ( + .CI(com_cmm_u_cmm_decoder_data_tmp_7[4]), + .DI(com_cmm_u_cmm_decoder_GND_4478), + .LO(com_cmm_u_cmm_decoder_data_tmp_7[5]), + .S(com_cmm_u_cmm_decoder_N_59_6) + ); + MUXCY_L com_cmm_u_cmm_decoder_bar2_eq_raddr_3_0_I_64 ( + .CI(com_cmm_u_cmm_decoder_data_tmp_7[6]), + .DI(com_cmm_u_cmm_decoder_GND_4478), + .LO(com_cmm_u_cmm_decoder_data_tmp_7[7]), + .S(com_cmm_u_cmm_decoder_N_51_6) + ); + MUXCY_L com_cmm_u_cmm_decoder_bar2_eq_raddr_3_0_I_73 ( + .CI(com_cmm_u_cmm_decoder_data_tmp_7[7]), + .DI(com_cmm_u_cmm_decoder_GND_4478), + .LO(com_cmm_u_cmm_decoder_data_tmp_7[8]), + .S(com_cmm_u_cmm_decoder_N_43_6) + ); + MUXCY_L com_cmm_u_cmm_decoder_bar2_eq_raddr_3_0_I_82 ( + .CI(com_cmm_u_cmm_decoder_data_tmp_7[5]), + .DI(com_cmm_u_cmm_decoder_GND_4478), + .LO(com_cmm_u_cmm_decoder_data_tmp_7[6]), + .S(com_cmm_u_cmm_decoder_N_35_6) + ); + MUXCY_L com_cmm_u_cmm_decoder_bar2_eq_raddr_3_0_I_91 ( + .CI(com_cmm_u_cmm_decoder_data_tmp_6[0]), + .DI(com_cmm_u_cmm_decoder_GND_4478), + .LO(com_cmm_u_cmm_decoder_data_tmp_7[1]), + .S(com_cmm_u_cmm_decoder_N_27_6) + ); + MUXCY_L com_cmm_u_cmm_decoder_bar2_eq_raddr_3_0_I_100 ( + .CI(com_cmm_u_cmm_decoder_data_tmp_6[10]), + .DI(com_cmm_u_cmm_decoder_GND_4478), + .LO(com_cmm_u_cmm_decoder_data_tmp_6[11]), + .S(com_cmm_u_cmm_decoder_N_19_6) + ); + MUXCY_L com_cmm_u_cmm_decoder_bar2_eq_raddr_3_0_I_109 ( + .CI(com_cmm_u_cmm_decoder_data_tmp_6[11]), + .DI(com_cmm_u_cmm_decoder_GND_4478), + .LO(com_cmm_u_cmm_decoder_data_tmp_2[12]), + .S(com_cmm_u_cmm_decoder_N_11_7) + ); + MUXCY_L com_cmm_u_cmm_decoder_bar2_eq_raddr_3_0_I_118 ( + .CI(com_cmm_u_cmm_decoder_data_tmp_7[1]), + .DI(com_cmm_u_cmm_decoder_GND_4478), + .LO(com_cmm_u_cmm_decoder_data_tmp_7[2]), + .S(com_cmm_u_cmm_decoder_N_3_6) + ); + MUXCY_L com_cmm_u_cmm_decoder_bar3_eq_raddr_3_0_I_1 ( + .CI(com_cmm_u_cmm_decoder_VCC_4448), + .DI(com_cmm_u_cmm_decoder_GND_4478), + .LO(com_cmm_u_cmm_decoder_data_tmp_5[0]), + .S(com_cmm_u_cmm_decoder_N_107_7) + ); + MUXCY_L com_cmm_u_cmm_decoder_bar3_eq_raddr_3_0_I_19 ( + .CI(com_cmm_u_cmm_decoder_data_tmp_6[8]), + .DI(com_cmm_u_cmm_decoder_GND_4478), + .LO(com_cmm_u_cmm_decoder_data_tmp_6[9]), + .S(com_cmm_u_cmm_decoder_N_91_7) + ); + MUXCY_L com_cmm_u_cmm_decoder_bar3_eq_raddr_3_0_I_28 ( + .CI(com_cmm_u_cmm_decoder_data_tmp_6[2]), + .DI(com_cmm_u_cmm_decoder_GND_4478), + .LO(com_cmm_u_cmm_decoder_data_tmp_6[3]), + .S(com_cmm_u_cmm_decoder_N_83_7) + ); + MUXCY_L com_cmm_u_cmm_decoder_bar3_eq_raddr_3_0_I_37 ( + .CI(com_cmm_u_cmm_decoder_data_tmp_6[3]), + .DI(com_cmm_u_cmm_decoder_GND_4478), + .LO(com_cmm_u_cmm_decoder_data_tmp_6[4]), + .S(com_cmm_u_cmm_decoder_N_75_7) + ); + MUXCY_L com_cmm_u_cmm_decoder_bar3_eq_raddr_3_0_I_46 ( + .CI(com_cmm_u_cmm_decoder_data_tmp_6[9]), + .DI(com_cmm_u_cmm_decoder_GND_4478), + .LO(com_cmm_u_cmm_decoder_data_tmp_5[10]), + .S(com_cmm_u_cmm_decoder_N_67_7) + ); + MUXCY_L com_cmm_u_cmm_decoder_bar3_eq_raddr_3_0_I_55 ( + .CI(com_cmm_u_cmm_decoder_data_tmp_6[4]), + .DI(com_cmm_u_cmm_decoder_GND_4478), + .LO(com_cmm_u_cmm_decoder_data_tmp_6[5]), + .S(com_cmm_u_cmm_decoder_N_59_7) + ); + MUXCY_L com_cmm_u_cmm_decoder_bar3_eq_raddr_3_0_I_64 ( + .CI(com_cmm_u_cmm_decoder_data_tmp_6[6]), + .DI(com_cmm_u_cmm_decoder_GND_4478), + .LO(com_cmm_u_cmm_decoder_data_tmp_6[7]), + .S(com_cmm_u_cmm_decoder_N_51_7) + ); + MUXCY_L com_cmm_u_cmm_decoder_bar3_eq_raddr_3_0_I_73 ( + .CI(com_cmm_u_cmm_decoder_data_tmp_6[7]), + .DI(com_cmm_u_cmm_decoder_GND_4478), + .LO(com_cmm_u_cmm_decoder_data_tmp_6[8]), + .S(com_cmm_u_cmm_decoder_N_43_7) + ); + MUXCY_L com_cmm_u_cmm_decoder_bar3_eq_raddr_3_0_I_82 ( + .CI(com_cmm_u_cmm_decoder_data_tmp_6[5]), + .DI(com_cmm_u_cmm_decoder_GND_4478), + .LO(com_cmm_u_cmm_decoder_data_tmp_6[6]), + .S(com_cmm_u_cmm_decoder_N_35_7) + ); + MUXCY_L com_cmm_u_cmm_decoder_bar3_eq_raddr_3_0_I_91 ( + .CI(com_cmm_u_cmm_decoder_data_tmp_5[0]), + .DI(com_cmm_u_cmm_decoder_GND_4478), + .LO(com_cmm_u_cmm_decoder_data_tmp_6[1]), + .S(com_cmm_u_cmm_decoder_N_27_7) + ); + MUXCY_L com_cmm_u_cmm_decoder_bar3_eq_raddr_3_0_I_100 ( + .CI(com_cmm_u_cmm_decoder_data_tmp_5[10]), + .DI(com_cmm_u_cmm_decoder_GND_4478), + .LO(com_cmm_u_cmm_decoder_data_tmp_5[11]), + .S(com_cmm_u_cmm_decoder_N_19_7) + ); + MUXCY_L com_cmm_u_cmm_decoder_bar3_eq_raddr_3_0_I_109 ( + .CI(com_cmm_u_cmm_decoder_data_tmp_5[11]), + .DI(com_cmm_u_cmm_decoder_GND_4478), + .LO(com_cmm_u_cmm_decoder_data_tmp_3[12]), + .S(com_cmm_u_cmm_decoder_N_11_8) + ); + MUXCY_L com_cmm_u_cmm_decoder_bar3_eq_raddr_3_0_I_118 ( + .CI(com_cmm_u_cmm_decoder_data_tmp_6[1]), + .DI(com_cmm_u_cmm_decoder_GND_4478), + .LO(com_cmm_u_cmm_decoder_data_tmp_6[2]), + .S(com_cmm_u_cmm_decoder_N_3_7) + ); + MUXCY_L com_cmm_u_cmm_decoder_bar4_eq_raddr_3_0_I_1 ( + .CI(com_cmm_u_cmm_decoder_VCC_4448), + .DI(com_cmm_u_cmm_decoder_GND_4478), + .LO(com_cmm_u_cmm_decoder_data_tmp_4[0]), + .S(com_cmm_u_cmm_decoder_N_107_8) + ); + MUXCY_L com_cmm_u_cmm_decoder_bar4_eq_raddr_3_0_I_19 ( + .CI(com_cmm_u_cmm_decoder_data_tmp_5[8]), + .DI(com_cmm_u_cmm_decoder_GND_4478), + .LO(com_cmm_u_cmm_decoder_data_tmp_5[9]), + .S(com_cmm_u_cmm_decoder_N_91_8) + ); + MUXCY_L com_cmm_u_cmm_decoder_bar4_eq_raddr_3_0_I_28 ( + .CI(com_cmm_u_cmm_decoder_data_tmp_5[2]), + .DI(com_cmm_u_cmm_decoder_GND_4478), + .LO(com_cmm_u_cmm_decoder_data_tmp_5[3]), + .S(com_cmm_u_cmm_decoder_N_83_8) + ); + MUXCY_L com_cmm_u_cmm_decoder_bar4_eq_raddr_3_0_I_37 ( + .CI(com_cmm_u_cmm_decoder_data_tmp_5[3]), + .DI(com_cmm_u_cmm_decoder_GND_4478), + .LO(com_cmm_u_cmm_decoder_data_tmp_5[4]), + .S(com_cmm_u_cmm_decoder_N_75_8) + ); + MUXCY_L com_cmm_u_cmm_decoder_bar4_eq_raddr_3_0_I_46 ( + .CI(com_cmm_u_cmm_decoder_data_tmp_5[9]), + .DI(com_cmm_u_cmm_decoder_GND_4478), + .LO(com_cmm_u_cmm_decoder_data_tmp_4[10]), + .S(com_cmm_u_cmm_decoder_N_67_8) + ); + MUXCY_L com_cmm_u_cmm_decoder_bar4_eq_raddr_3_0_I_55 ( + .CI(com_cmm_u_cmm_decoder_data_tmp_5[4]), + .DI(com_cmm_u_cmm_decoder_GND_4478), + .LO(com_cmm_u_cmm_decoder_data_tmp_5[5]), + .S(com_cmm_u_cmm_decoder_N_59_8) + ); + MUXCY_L com_cmm_u_cmm_decoder_bar4_eq_raddr_3_0_I_64 ( + .CI(com_cmm_u_cmm_decoder_data_tmp_5[6]), + .DI(com_cmm_u_cmm_decoder_GND_4478), + .LO(com_cmm_u_cmm_decoder_data_tmp_5[7]), + .S(com_cmm_u_cmm_decoder_N_51_8) + ); + MUXCY_L com_cmm_u_cmm_decoder_bar4_eq_raddr_3_0_I_73 ( + .CI(com_cmm_u_cmm_decoder_data_tmp_5[7]), + .DI(com_cmm_u_cmm_decoder_GND_4478), + .LO(com_cmm_u_cmm_decoder_data_tmp_5[8]), + .S(com_cmm_u_cmm_decoder_N_43_8) + ); + MUXCY_L com_cmm_u_cmm_decoder_bar4_eq_raddr_3_0_I_82 ( + .CI(com_cmm_u_cmm_decoder_data_tmp_5[5]), + .DI(com_cmm_u_cmm_decoder_GND_4478), + .LO(com_cmm_u_cmm_decoder_data_tmp_5[6]), + .S(com_cmm_u_cmm_decoder_N_35_8) + ); + MUXCY_L com_cmm_u_cmm_decoder_bar4_eq_raddr_3_0_I_91 ( + .CI(com_cmm_u_cmm_decoder_data_tmp_4[0]), + .DI(com_cmm_u_cmm_decoder_GND_4478), + .LO(com_cmm_u_cmm_decoder_data_tmp_5[1]), + .S(com_cmm_u_cmm_decoder_N_27_8) + ); + MUXCY_L com_cmm_u_cmm_decoder_bar4_eq_raddr_3_0_I_100 ( + .CI(com_cmm_u_cmm_decoder_data_tmp_4[10]), + .DI(com_cmm_u_cmm_decoder_GND_4478), + .LO(com_cmm_u_cmm_decoder_data_tmp_4[11]), + .S(com_cmm_u_cmm_decoder_N_19_8) + ); + MUXCY_L com_cmm_u_cmm_decoder_bar4_eq_raddr_3_0_I_109 ( + .CI(com_cmm_u_cmm_decoder_data_tmp_4[11]), + .DI(com_cmm_u_cmm_decoder_GND_4478), + .LO(com_cmm_u_cmm_decoder_data_tmp_4[12]), + .S(com_cmm_u_cmm_decoder_N_11_9) + ); + MUXCY_L com_cmm_u_cmm_decoder_bar4_eq_raddr_3_0_I_118 ( + .CI(com_cmm_u_cmm_decoder_data_tmp_5[1]), + .DI(com_cmm_u_cmm_decoder_GND_4478), + .LO(com_cmm_u_cmm_decoder_data_tmp_5[2]), + .S(com_cmm_u_cmm_decoder_N_3_8) + ); + MUXCY_L com_cmm_u_cmm_decoder_bar5_eq_raddr_3_0_I_19 ( + .CI(com_cmm_u_cmm_decoder_data_tmp_4[8]), + .DI(com_cmm_u_cmm_decoder_GND_4478), + .LO(com_cmm_u_cmm_decoder_data_tmp_4[9]), + .S(com_cmm_u_cmm_decoder_I_19_sf) + ); + MUXCY_L com_cmm_u_cmm_decoder_bar5_eq_raddr_3_0_I_28 ( + .CI(com_cmm_u_cmm_decoder_data_tmp_4[2]), + .DI(com_cmm_u_cmm_decoder_GND_4478), + .LO(com_cmm_u_cmm_decoder_data_tmp_4[3]), + .S(com_cmm_u_cmm_decoder_I_28_sf) + ); + MUXCY_L com_cmm_u_cmm_decoder_bar5_eq_raddr_3_0_I_37 ( + .CI(com_cmm_u_cmm_decoder_data_tmp_4[3]), + .DI(com_cmm_u_cmm_decoder_GND_4478), + .LO(com_cmm_u_cmm_decoder_data_tmp_4[4]), + .S(com_cmm_u_cmm_decoder_I_37_sf) + ); + MUXCY_L com_cmm_u_cmm_decoder_bar5_eq_raddr_3_0_I_46 ( + .CI(com_cmm_u_cmm_decoder_data_tmp_4[9]), + .DI(com_cmm_u_cmm_decoder_GND_4478), + .LO(com_cmm_u_cmm_decoder_data_tmp_3[10]), + .S(com_cmm_u_cmm_decoder_I_46_sf) + ); + MUXCY_L com_cmm_u_cmm_decoder_bar5_eq_raddr_3_0_I_55 ( + .CI(com_cmm_u_cmm_decoder_data_tmp_4[4]), + .DI(com_cmm_u_cmm_decoder_GND_4478), + .LO(com_cmm_u_cmm_decoder_data_tmp_4[5]), + .S(com_cmm_u_cmm_decoder_I_55_sf) + ); + MUXCY_L com_cmm_u_cmm_decoder_bar5_eq_raddr_3_0_I_64 ( + .CI(com_cmm_u_cmm_decoder_data_tmp_4[6]), + .DI(com_cmm_u_cmm_decoder_GND_4478), + .LO(com_cmm_u_cmm_decoder_data_tmp_4[7]), + .S(com_cmm_u_cmm_decoder_I_64_sf) + ); + MUXCY_L com_cmm_u_cmm_decoder_bar5_eq_raddr_3_0_I_73 ( + .CI(com_cmm_u_cmm_decoder_data_tmp_4[7]), + .DI(com_cmm_u_cmm_decoder_GND_4478), + .LO(com_cmm_u_cmm_decoder_data_tmp_4[8]), + .S(com_cmm_u_cmm_decoder_I_73_sf) + ); + MUXCY_L com_cmm_u_cmm_decoder_bar5_eq_raddr_3_0_I_82 ( + .CI(com_cmm_u_cmm_decoder_data_tmp_4[5]), + .DI(com_cmm_u_cmm_decoder_GND_4478), + .LO(com_cmm_u_cmm_decoder_data_tmp_4[6]), + .S(com_cmm_u_cmm_decoder_I_82_sf) + ); + MUXCY_L com_cmm_u_cmm_decoder_bar5_eq_raddr_3_0_I_91 ( + .CI(com_cmm_u_cmm_decoder_N_107_13), + .DI(com_cmm_u_cmm_decoder_GND_4478), + .LO(com_cmm_u_cmm_decoder_data_tmp_4[1]), + .S(com_cmm_u_cmm_decoder_I_91_sf) + ); + MUXCY_L com_cmm_u_cmm_decoder_bar5_eq_raddr_3_0_I_100 ( + .CI(com_cmm_u_cmm_decoder_data_tmp_3[10]), + .DI(com_cmm_u_cmm_decoder_GND_4478), + .LO(com_cmm_u_cmm_decoder_data_tmp_3[11]), + .S(com_cmm_u_cmm_decoder_I_100_sf) + ); + MUXCY_L com_cmm_u_cmm_decoder_bar5_eq_raddr_3_0_I_109 ( + .CI(com_cmm_u_cmm_decoder_data_tmp_3[11]), + .DI(com_cmm_u_cmm_decoder_GND_4478), + .LO(com_cmm_u_cmm_decoder_data_tmp_5[12]), + .S(com_cmm_u_cmm_decoder_I_109_sf) + ); + MUXCY_L com_cmm_u_cmm_decoder_bar5_eq_raddr_3_0_I_118 ( + .CI(com_cmm_u_cmm_decoder_data_tmp_4[1]), + .DI(com_cmm_u_cmm_decoder_GND_4478), + .LO(com_cmm_u_cmm_decoder_data_tmp_4[2]), + .S(com_cmm_u_cmm_decoder_I_118_sf) + ); + MUXCY_L com_cmm_u_cmm_decoder_bar6_eq_raddr_3_0_I_1 ( + .CI(com_cmm_u_cmm_decoder_VCC_4448), + .DI(com_cmm_u_cmm_decoder_GND_4478), + .LO(com_cmm_u_cmm_decoder_data_tmp_3[0]), + .S(com_cmm_u_cmm_decoder_N_81) + ); + MUXCY_L com_cmm_u_cmm_decoder_bar6_eq_raddr_3_0_I_10 ( + .CI(com_cmm_u_cmm_decoder_data_tmp_3[8]), + .DI(com_cmm_u_cmm_decoder_GND_4478), + .LO(com_cmm_u_cmm_decoder_data_tmp[9]), + .S(com_cmm_u_cmm_decoder_N_73) + ); + MUXCY_L com_cmm_u_cmm_decoder_bar6_eq_raddr_3_0_I_19 ( + .CI(com_cmm_u_cmm_decoder_data_tmp_3[1]), + .DI(com_cmm_u_cmm_decoder_GND_4478), + .LO(com_cmm_u_cmm_decoder_data_tmp_3[2]), + .S(com_cmm_u_cmm_decoder_N_65) + ); + MUXCY_L com_cmm_u_cmm_decoder_bar6_eq_raddr_3_0_I_28 ( + .CI(com_cmm_u_cmm_decoder_data_tmp_3[2]), + .DI(com_cmm_u_cmm_decoder_GND_4478), + .LO(com_cmm_u_cmm_decoder_data_tmp_3[3]), + .S(com_cmm_u_cmm_decoder_N_57) + ); + MUXCY_L com_cmm_u_cmm_decoder_bar6_eq_raddr_3_0_I_37 ( + .CI(com_cmm_u_cmm_decoder_data_tmp_3[4]), + .DI(com_cmm_u_cmm_decoder_GND_4478), + .LO(com_cmm_u_cmm_decoder_data_tmp_3[5]), + .S(com_cmm_u_cmm_decoder_N_49) + ); + MUXCY_L com_cmm_u_cmm_decoder_bar6_eq_raddr_3_0_I_46 ( + .CI(com_cmm_u_cmm_decoder_data_tmp_3[7]), + .DI(com_cmm_u_cmm_decoder_GND_4478), + .LO(com_cmm_u_cmm_decoder_data_tmp_3[8]), + .S(com_cmm_u_cmm_decoder_N_41) + ); + MUXCY_L com_cmm_u_cmm_decoder_bar6_eq_raddr_3_0_I_55 ( + .CI(com_cmm_u_cmm_decoder_data_tmp_3[5]), + .DI(com_cmm_u_cmm_decoder_GND_4478), + .LO(com_cmm_u_cmm_decoder_data_tmp_3[6]), + .S(com_cmm_u_cmm_decoder_N_33) + ); + MUXCY_L com_cmm_u_cmm_decoder_bar6_eq_raddr_3_0_I_64 ( + .CI(com_cmm_u_cmm_decoder_data_tmp_3[6]), + .DI(com_cmm_u_cmm_decoder_GND_4478), + .LO(com_cmm_u_cmm_decoder_data_tmp_3[7]), + .S(com_cmm_u_cmm_decoder_N_25) + ); + MUXCY_L com_cmm_u_cmm_decoder_bar6_eq_raddr_3_0_I_73 ( + .CI(com_cmm_u_cmm_decoder_data_tmp_3[0]), + .DI(com_cmm_u_cmm_decoder_GND_4478), + .LO(com_cmm_u_cmm_decoder_data_tmp_3[1]), + .S(com_cmm_u_cmm_decoder_N_17) + ); + MUXCY_L com_cmm_u_cmm_decoder_bar6_eq_raddr_3_0_I_82 ( + .CI(com_cmm_u_cmm_decoder_data_tmp_3[3]), + .DI(com_cmm_u_cmm_decoder_GND_4478), + .LO(com_cmm_u_cmm_decoder_data_tmp_3[4]), + .S(com_cmm_u_cmm_decoder_N_9) + ); + MUXCY_L com_cmm_u_cmm_decoder_un9_bar01_64_hit_high_0_I_1 ( + .CI(com_cmm_u_cmm_decoder_VCC_4448), + .DI(com_cmm_u_cmm_decoder_GND_4478), + .LO(com_cmm_u_cmm_decoder_data_tmp_2[0]), + .S(com_cmm_u_cmm_decoder_N_107_9) + ); + MUXCY_L com_cmm_u_cmm_decoder_un9_bar01_64_hit_high_0_I_19 ( + .CI(com_cmm_u_cmm_decoder_data_tmp_2[8]), + .DI(com_cmm_u_cmm_decoder_GND_4478), + .LO(com_cmm_u_cmm_decoder_data_tmp_3[9]), + .S(com_cmm_u_cmm_decoder_N_91_10) + ); + MUXCY_L com_cmm_u_cmm_decoder_un9_bar01_64_hit_high_0_I_28 ( + .CI(com_cmm_u_cmm_decoder_data_tmp_2[2]), + .DI(com_cmm_u_cmm_decoder_GND_4478), + .LO(com_cmm_u_cmm_decoder_data_tmp_2[3]), + .S(com_cmm_u_cmm_decoder_N_83_10) + ); + MUXCY_L com_cmm_u_cmm_decoder_un9_bar01_64_hit_high_0_I_37 ( + .CI(com_cmm_u_cmm_decoder_data_tmp_2[3]), + .DI(com_cmm_u_cmm_decoder_GND_4478), + .LO(com_cmm_u_cmm_decoder_data_tmp_2[4]), + .S(com_cmm_u_cmm_decoder_N_75_10) + ); + MUXCY_L com_cmm_u_cmm_decoder_un9_bar01_64_hit_high_0_I_46 ( + .CI(com_cmm_u_cmm_decoder_data_tmp_3[9]), + .DI(com_cmm_u_cmm_decoder_GND_4478), + .LO(com_cmm_u_cmm_decoder_data_tmp_2[10]), + .S(com_cmm_u_cmm_decoder_N_67_10) + ); + MUXCY_L com_cmm_u_cmm_decoder_un9_bar01_64_hit_high_0_I_55 ( + .CI(com_cmm_u_cmm_decoder_data_tmp_2[4]), + .DI(com_cmm_u_cmm_decoder_GND_4478), + .LO(com_cmm_u_cmm_decoder_data_tmp_2[5]), + .S(com_cmm_u_cmm_decoder_N_59_10) + ); + MUXCY_L com_cmm_u_cmm_decoder_un9_bar01_64_hit_high_0_I_64 ( + .CI(com_cmm_u_cmm_decoder_data_tmp_2[6]), + .DI(com_cmm_u_cmm_decoder_GND_4478), + .LO(com_cmm_u_cmm_decoder_data_tmp_2[7]), + .S(com_cmm_u_cmm_decoder_N_51_10) + ); + MUXCY_L com_cmm_u_cmm_decoder_un9_bar01_64_hit_high_0_I_73 ( + .CI(com_cmm_u_cmm_decoder_data_tmp_2[7]), + .DI(com_cmm_u_cmm_decoder_GND_4478), + .LO(com_cmm_u_cmm_decoder_data_tmp_2[8]), + .S(com_cmm_u_cmm_decoder_N_43_10) + ); + MUXCY_L com_cmm_u_cmm_decoder_un9_bar01_64_hit_high_0_I_82 ( + .CI(com_cmm_u_cmm_decoder_data_tmp_2[5]), + .DI(com_cmm_u_cmm_decoder_GND_4478), + .LO(com_cmm_u_cmm_decoder_data_tmp_2[6]), + .S(com_cmm_u_cmm_decoder_N_35_10) + ); + MUXCY_L com_cmm_u_cmm_decoder_un9_bar01_64_hit_high_0_I_91 ( + .CI(com_cmm_u_cmm_decoder_data_tmp_2[0]), + .DI(com_cmm_u_cmm_decoder_GND_4478), + .LO(com_cmm_u_cmm_decoder_data_tmp_2[1]), + .S(com_cmm_u_cmm_decoder_N_27_10) + ); + MUXCY_L com_cmm_u_cmm_decoder_un9_bar01_64_hit_high_0_I_100 ( + .CI(com_cmm_u_cmm_decoder_data_tmp_2[10]), + .DI(com_cmm_u_cmm_decoder_GND_4478), + .LO(com_cmm_u_cmm_decoder_data_tmp_2[11]), + .S(com_cmm_u_cmm_decoder_N_19_10) + ); + MUXCY_L com_cmm_u_cmm_decoder_un9_bar01_64_hit_high_0_I_109 ( + .CI(com_cmm_u_cmm_decoder_data_tmp_2[11]), + .DI(com_cmm_u_cmm_decoder_GND_4478), + .LO(com_cmm_u_cmm_decoder_data_tmp_6[12]), + .S(com_cmm_u_cmm_decoder_N_11_11) + ); + MUXCY_L com_cmm_u_cmm_decoder_un9_bar01_64_hit_high_0_I_118 ( + .CI(com_cmm_u_cmm_decoder_data_tmp_2[1]), + .DI(com_cmm_u_cmm_decoder_GND_4478), + .LO(com_cmm_u_cmm_decoder_data_tmp_2[2]), + .S(com_cmm_u_cmm_decoder_N_3_10) + ); + MUXCY_L com_cmm_u_cmm_decoder_un9_bar12_64_hit_high_0_I_1 ( + .CI(com_cmm_u_cmm_decoder_VCC_4448), + .DI(com_cmm_u_cmm_decoder_GND_4478), + .LO(com_cmm_u_cmm_decoder_data_tmp_1[0]), + .S(com_cmm_u_cmm_decoder_N_107_10) + ); + MUXCY_L com_cmm_u_cmm_decoder_un9_bar12_64_hit_high_0_I_19 ( + .CI(com_cmm_u_cmm_decoder_data_tmp_1[8]), + .DI(com_cmm_u_cmm_decoder_GND_4478), + .LO(com_cmm_u_cmm_decoder_data_tmp_2[9]), + .S(com_cmm_u_cmm_decoder_N_91_11) + ); + MUXCY_L com_cmm_u_cmm_decoder_un9_bar12_64_hit_high_0_I_28 ( + .CI(com_cmm_u_cmm_decoder_data_tmp_1[2]), + .DI(com_cmm_u_cmm_decoder_GND_4478), + .LO(com_cmm_u_cmm_decoder_data_tmp_1[3]), + .S(com_cmm_u_cmm_decoder_N_83_11) + ); + MUXCY_L com_cmm_u_cmm_decoder_un9_bar12_64_hit_high_0_I_37 ( + .CI(com_cmm_u_cmm_decoder_data_tmp_1[3]), + .DI(com_cmm_u_cmm_decoder_GND_4478), + .LO(com_cmm_u_cmm_decoder_data_tmp_1[4]), + .S(com_cmm_u_cmm_decoder_N_75_11) + ); + MUXCY_L com_cmm_u_cmm_decoder_un9_bar12_64_hit_high_0_I_46 ( + .CI(com_cmm_u_cmm_decoder_data_tmp_2[9]), + .DI(com_cmm_u_cmm_decoder_GND_4478), + .LO(com_cmm_u_cmm_decoder_data_tmp_1[10]), + .S(com_cmm_u_cmm_decoder_N_67_11) + ); + MUXCY_L com_cmm_u_cmm_decoder_un9_bar12_64_hit_high_0_I_55 ( + .CI(com_cmm_u_cmm_decoder_data_tmp_1[4]), + .DI(com_cmm_u_cmm_decoder_GND_4478), + .LO(com_cmm_u_cmm_decoder_data_tmp_1[5]), + .S(com_cmm_u_cmm_decoder_N_59_11) + ); + MUXCY_L com_cmm_u_cmm_decoder_un9_bar12_64_hit_high_0_I_64 ( + .CI(com_cmm_u_cmm_decoder_data_tmp_1[6]), + .DI(com_cmm_u_cmm_decoder_GND_4478), + .LO(com_cmm_u_cmm_decoder_data_tmp_1[7]), + .S(com_cmm_u_cmm_decoder_N_51_11) + ); + MUXCY_L com_cmm_u_cmm_decoder_un9_bar12_64_hit_high_0_I_73 ( + .CI(com_cmm_u_cmm_decoder_data_tmp_1[7]), + .DI(com_cmm_u_cmm_decoder_GND_4478), + .LO(com_cmm_u_cmm_decoder_data_tmp_1[8]), + .S(com_cmm_u_cmm_decoder_N_43_11) + ); + MUXCY_L com_cmm_u_cmm_decoder_un9_bar12_64_hit_high_0_I_82 ( + .CI(com_cmm_u_cmm_decoder_data_tmp_1[5]), + .DI(com_cmm_u_cmm_decoder_GND_4478), + .LO(com_cmm_u_cmm_decoder_data_tmp_1[6]), + .S(com_cmm_u_cmm_decoder_N_35_11) + ); + MUXCY_L com_cmm_u_cmm_decoder_un9_bar12_64_hit_high_0_I_91 ( + .CI(com_cmm_u_cmm_decoder_data_tmp_1[0]), + .DI(com_cmm_u_cmm_decoder_GND_4478), + .LO(com_cmm_u_cmm_decoder_data_tmp_1[1]), + .S(com_cmm_u_cmm_decoder_N_27_11) + ); + MUXCY_L com_cmm_u_cmm_decoder_un9_bar12_64_hit_high_0_I_100 ( + .CI(com_cmm_u_cmm_decoder_data_tmp_1[10]), + .DI(com_cmm_u_cmm_decoder_GND_4478), + .LO(com_cmm_u_cmm_decoder_data_tmp_1[11]), + .S(com_cmm_u_cmm_decoder_N_19_11) + ); + MUXCY_L com_cmm_u_cmm_decoder_un9_bar12_64_hit_high_0_I_109 ( + .CI(com_cmm_u_cmm_decoder_data_tmp_1[11]), + .DI(com_cmm_u_cmm_decoder_GND_4478), + .LO(com_cmm_u_cmm_decoder_data_tmp_7[12]), + .S(com_cmm_u_cmm_decoder_N_11_12) + ); + MUXCY_L com_cmm_u_cmm_decoder_un9_bar12_64_hit_high_0_I_118 ( + .CI(com_cmm_u_cmm_decoder_data_tmp_1[1]), + .DI(com_cmm_u_cmm_decoder_GND_4478), + .LO(com_cmm_u_cmm_decoder_data_tmp_1[2]), + .S(com_cmm_u_cmm_decoder_N_3_11) + ); + MUXCY_L com_cmm_u_cmm_decoder_un9_bar23_64_hit_high_0_I_1 ( + .CI(com_cmm_u_cmm_decoder_VCC_4448), + .DI(com_cmm_u_cmm_decoder_GND_4478), + .LO(com_cmm_u_cmm_decoder_data_tmp_0[0]), + .S(com_cmm_u_cmm_decoder_N_107_11) + ); + MUXCY_L com_cmm_u_cmm_decoder_un9_bar23_64_hit_high_0_I_19 ( + .CI(com_cmm_u_cmm_decoder_data_tmp_0[8]), + .DI(com_cmm_u_cmm_decoder_GND_4478), + .LO(com_cmm_u_cmm_decoder_data_tmp_1[9]), + .S(com_cmm_u_cmm_decoder_N_91_12) + ); + MUXCY_L com_cmm_u_cmm_decoder_un9_bar23_64_hit_high_0_I_28 ( + .CI(com_cmm_u_cmm_decoder_data_tmp_0[2]), + .DI(com_cmm_u_cmm_decoder_GND_4478), + .LO(com_cmm_u_cmm_decoder_data_tmp_0[3]), + .S(com_cmm_u_cmm_decoder_N_83_12) + ); + MUXCY_L com_cmm_u_cmm_decoder_un9_bar23_64_hit_high_0_I_37 ( + .CI(com_cmm_u_cmm_decoder_data_tmp_0[3]), + .DI(com_cmm_u_cmm_decoder_GND_4478), + .LO(com_cmm_u_cmm_decoder_data_tmp_0[4]), + .S(com_cmm_u_cmm_decoder_N_75_12) + ); + MUXCY_L com_cmm_u_cmm_decoder_un9_bar23_64_hit_high_0_I_46 ( + .CI(com_cmm_u_cmm_decoder_data_tmp_1[9]), + .DI(com_cmm_u_cmm_decoder_GND_4478), + .LO(com_cmm_u_cmm_decoder_data_tmp_0[10]), + .S(com_cmm_u_cmm_decoder_N_67_12) + ); + MUXCY_L com_cmm_u_cmm_decoder_un9_bar23_64_hit_high_0_I_55 ( + .CI(com_cmm_u_cmm_decoder_data_tmp_0[4]), + .DI(com_cmm_u_cmm_decoder_GND_4478), + .LO(com_cmm_u_cmm_decoder_data_tmp_0[5]), + .S(com_cmm_u_cmm_decoder_N_59_12) + ); + MUXCY_L com_cmm_u_cmm_decoder_un9_bar23_64_hit_high_0_I_64 ( + .CI(com_cmm_u_cmm_decoder_data_tmp_0[6]), + .DI(com_cmm_u_cmm_decoder_GND_4478), + .LO(com_cmm_u_cmm_decoder_data_tmp_0[7]), + .S(com_cmm_u_cmm_decoder_N_51_12) + ); + MUXCY_L com_cmm_u_cmm_decoder_un9_bar23_64_hit_high_0_I_73 ( + .CI(com_cmm_u_cmm_decoder_data_tmp_0[7]), + .DI(com_cmm_u_cmm_decoder_GND_4478), + .LO(com_cmm_u_cmm_decoder_data_tmp_0[8]), + .S(com_cmm_u_cmm_decoder_N_43_12) + ); + MUXCY_L com_cmm_u_cmm_decoder_un9_bar23_64_hit_high_0_I_82 ( + .CI(com_cmm_u_cmm_decoder_data_tmp_0[5]), + .DI(com_cmm_u_cmm_decoder_GND_4478), + .LO(com_cmm_u_cmm_decoder_data_tmp_0[6]), + .S(com_cmm_u_cmm_decoder_N_35_12) + ); + MUXCY_L com_cmm_u_cmm_decoder_un9_bar23_64_hit_high_0_I_91 ( + .CI(com_cmm_u_cmm_decoder_data_tmp_0[0]), + .DI(com_cmm_u_cmm_decoder_GND_4478), + .LO(com_cmm_u_cmm_decoder_data_tmp_0[1]), + .S(com_cmm_u_cmm_decoder_N_27_12) + ); + MUXCY_L com_cmm_u_cmm_decoder_un9_bar23_64_hit_high_0_I_100 ( + .CI(com_cmm_u_cmm_decoder_data_tmp_0[10]), + .DI(com_cmm_u_cmm_decoder_GND_4478), + .LO(com_cmm_u_cmm_decoder_data_tmp_0[11]), + .S(com_cmm_u_cmm_decoder_N_19_12) + ); + MUXCY_L com_cmm_u_cmm_decoder_un9_bar23_64_hit_high_0_I_109 ( + .CI(com_cmm_u_cmm_decoder_data_tmp_0[11]), + .DI(com_cmm_u_cmm_decoder_GND_4478), + .LO(com_cmm_u_cmm_decoder_data_tmp_8[12]), + .S(com_cmm_u_cmm_decoder_N_11_13) + ); + MUXCY_L com_cmm_u_cmm_decoder_un9_bar23_64_hit_high_0_I_118 ( + .CI(com_cmm_u_cmm_decoder_data_tmp_0[1]), + .DI(com_cmm_u_cmm_decoder_GND_4478), + .LO(com_cmm_u_cmm_decoder_data_tmp_0[2]), + .S(com_cmm_u_cmm_decoder_N_3_12) + ); + MUXCY_L com_cmm_u_cmm_decoder_un9_bar34_64_hit_high_0_I_1 ( + .CI(com_cmm_u_cmm_decoder_VCC_4448), + .DI(com_cmm_u_cmm_decoder_GND_4478), + .LO(com_cmm_u_cmm_decoder_data_tmp[0]), + .S(com_cmm_u_cmm_decoder_N_107_12) + ); + MUXCY_L com_cmm_u_cmm_decoder_un9_bar34_64_hit_high_0_I_19 ( + .CI(com_cmm_u_cmm_decoder_data_tmp[8]), + .DI(com_cmm_u_cmm_decoder_GND_4478), + .LO(com_cmm_u_cmm_decoder_data_tmp_0[9]), + .S(com_cmm_u_cmm_decoder_N_91_13) + ); + MUXCY_L com_cmm_u_cmm_decoder_un9_bar34_64_hit_high_0_I_28 ( + .CI(com_cmm_u_cmm_decoder_data_tmp[2]), + .DI(com_cmm_u_cmm_decoder_GND_4478), + .LO(com_cmm_u_cmm_decoder_data_tmp[3]), + .S(com_cmm_u_cmm_decoder_N_83_13) + ); + MUXCY_L com_cmm_u_cmm_decoder_un9_bar34_64_hit_high_0_I_37 ( + .CI(com_cmm_u_cmm_decoder_data_tmp[3]), + .DI(com_cmm_u_cmm_decoder_GND_4478), + .LO(com_cmm_u_cmm_decoder_data_tmp[4]), + .S(com_cmm_u_cmm_decoder_N_75_13) + ); + MUXCY_L com_cmm_u_cmm_decoder_un9_bar34_64_hit_high_0_I_46 ( + .CI(com_cmm_u_cmm_decoder_data_tmp_0[9]), + .DI(com_cmm_u_cmm_decoder_GND_4478), + .LO(com_cmm_u_cmm_decoder_data_tmp[10]), + .S(com_cmm_u_cmm_decoder_N_67_13) + ); + MUXCY_L com_cmm_u_cmm_decoder_un9_bar34_64_hit_high_0_I_55 ( + .CI(com_cmm_u_cmm_decoder_data_tmp[4]), + .DI(com_cmm_u_cmm_decoder_GND_4478), + .LO(com_cmm_u_cmm_decoder_data_tmp[5]), + .S(com_cmm_u_cmm_decoder_N_59_13) + ); + MUXCY_L com_cmm_u_cmm_decoder_un9_bar34_64_hit_high_0_I_64 ( + .CI(com_cmm_u_cmm_decoder_data_tmp[6]), + .DI(com_cmm_u_cmm_decoder_GND_4478), + .LO(com_cmm_u_cmm_decoder_data_tmp[7]), + .S(com_cmm_u_cmm_decoder_N_51_13) + ); + MUXCY_L com_cmm_u_cmm_decoder_un9_bar34_64_hit_high_0_I_73 ( + .CI(com_cmm_u_cmm_decoder_data_tmp[7]), + .DI(com_cmm_u_cmm_decoder_GND_4478), + .LO(com_cmm_u_cmm_decoder_data_tmp[8]), + .S(com_cmm_u_cmm_decoder_N_43_13) + ); + MUXCY_L com_cmm_u_cmm_decoder_un9_bar34_64_hit_high_0_I_82 ( + .CI(com_cmm_u_cmm_decoder_data_tmp[5]), + .DI(com_cmm_u_cmm_decoder_GND_4478), + .LO(com_cmm_u_cmm_decoder_data_tmp[6]), + .S(com_cmm_u_cmm_decoder_N_35_13) + ); + MUXCY_L com_cmm_u_cmm_decoder_un9_bar34_64_hit_high_0_I_91 ( + .CI(com_cmm_u_cmm_decoder_data_tmp[0]), + .DI(com_cmm_u_cmm_decoder_GND_4478), + .LO(com_cmm_u_cmm_decoder_data_tmp[1]), + .S(com_cmm_u_cmm_decoder_N_27_13) + ); + MUXCY_L com_cmm_u_cmm_decoder_un9_bar34_64_hit_high_0_I_100 ( + .CI(com_cmm_u_cmm_decoder_data_tmp[10]), + .DI(com_cmm_u_cmm_decoder_GND_4478), + .LO(com_cmm_u_cmm_decoder_data_tmp[11]), + .S(com_cmm_u_cmm_decoder_N_19_13) + ); + MUXCY_L com_cmm_u_cmm_decoder_un9_bar34_64_hit_high_0_I_109 ( + .CI(com_cmm_u_cmm_decoder_data_tmp[11]), + .DI(com_cmm_u_cmm_decoder_GND_4478), + .LO(com_cmm_u_cmm_decoder_data_tmp_9[12]), + .S(com_cmm_u_cmm_decoder_N_11_14) + ); + MUXCY_L com_cmm_u_cmm_decoder_un9_bar34_64_hit_high_0_I_118 ( + .CI(com_cmm_u_cmm_decoder_data_tmp[1]), + .DI(com_cmm_u_cmm_decoder_GND_4478), + .LO(com_cmm_u_cmm_decoder_data_tmp[2]), + .S(com_cmm_u_cmm_decoder_N_3_13) + ); + MUXCY_L com_cmm_u_cmm_decoder_un11_bar34_64_hit_low_0 ( + .CI(com_cmm_u_cmm_decoder_VCC_4448), + .DI(com_cmm_u_cmm_decoder_GND_4478), + .LO(com_cmm_u_cmm_decoder_un11_bar34_64_hit_low_0_4364), + .S(com_cmm_u_cmm_decoder_un11_bar4_32_hit_nc_0) + ); + MUXCY_L com_cmm_u_cmm_decoder_un11_bar34_64_hit_low_1 ( + .CI(com_cmm_u_cmm_decoder_un11_bar34_64_hit_low_0_4364), + .DI(com_cmm_u_cmm_decoder_GND_4478), + .LO(com_cmm_u_cmm_decoder_un11_bar34_64_hit_low_1_4365), + .S(com_cmm_u_cmm_decoder_un11_bar4_32_hit_nc_1_and) + ); + MUXCY_L com_cmm_u_cmm_decoder_un11_bar34_64_hit_low_2 ( + .CI(com_cmm_u_cmm_decoder_un11_bar34_64_hit_low_1_4365), + .DI(com_cmm_u_cmm_decoder_GND_4478), + .LO(com_cmm_u_cmm_decoder_un11_bar34_64_hit_low_2_4366), + .S(com_cmm_u_cmm_decoder_un11_bar4_32_hit_nc_2_and) + ); + MUXCY_L com_cmm_u_cmm_decoder_un11_bar34_64_hit_low_3 ( + .CI(com_cmm_u_cmm_decoder_un11_bar34_64_hit_low_2_4366), + .DI(com_cmm_u_cmm_decoder_GND_4478), + .LO(com_cmm_u_cmm_decoder_un11_bar34_64_hit_low_3_4367), + .S(com_cmm_u_cmm_decoder_un11_bar4_32_hit_nc_3_and) + ); + MUXCY_L com_cmm_u_cmm_decoder_un11_bar34_64_hit_low_4 ( + .CI(com_cmm_u_cmm_decoder_un11_bar34_64_hit_low_3_4367), + .DI(com_cmm_u_cmm_decoder_GND_4478), + .LO(com_cmm_u_cmm_decoder_un11_bar34_64_hit_low_4_4368), + .S(com_cmm_u_cmm_decoder_un11_bar4_32_hit_nc_4_and) + ); + MUXCY_L com_cmm_u_cmm_decoder_un11_bar34_64_hit_low_5 ( + .CI(com_cmm_u_cmm_decoder_un11_bar34_64_hit_low_4_4368), + .DI(com_cmm_u_cmm_decoder_GND_4478), + .LO(com_cmm_u_cmm_decoder_un11_bar34_64_hit_low_5_4369), + .S(com_cmm_u_cmm_decoder_un11_bar4_32_hit_nc_5_and) + ); + MUXCY_L com_cmm_u_cmm_decoder_un11_bar34_64_hit_low_6 ( + .CI(com_cmm_u_cmm_decoder_un11_bar34_64_hit_low_5_4369), + .DI(com_cmm_u_cmm_decoder_GND_4478), + .LO(com_cmm_u_cmm_decoder_un11_bar34_64_hit_low_6_4370), + .S(com_cmm_u_cmm_decoder_un11_bar4_32_hit_nc_6_and) + ); + MUXCY com_cmm_u_cmm_decoder_un11_bar34_64_hit_low_7 ( + .CI(com_cmm_u_cmm_decoder_un11_bar34_64_hit_low_6_4370), + .DI(com_cmm_u_cmm_decoder_GND_4478), + .O(com_cmm_u_cmm_decoder_un11_bar34_64_hit_low_7_4470), + .S(com_cmm_u_cmm_decoder_un11_bar4_32_hit_nc_7_and) + ); + MUXCY_L com_cmm_u_cmm_decoder_un11_bar5_32_hit_nc_0 ( + .CI(com_cmm_u_cmm_decoder_VCC_4448), + .DI(com_cmm_u_cmm_decoder_GND_4478), + .LO(com_cmm_u_cmm_decoder_un11_bar5_32_hit_nc_0_4371), + .S(com_cmm_u_cmm_decoder_un11_bar5_32_hit_nc_0_and) + ); + MUXCY_L com_cmm_u_cmm_decoder_un11_bar5_32_hit_nc_1 ( + .CI(com_cmm_u_cmm_decoder_un11_bar5_32_hit_nc_0_4371), + .DI(com_cmm_u_cmm_decoder_GND_4478), + .LO(com_cmm_u_cmm_decoder_un11_bar5_32_hit_nc_1_4372), + .S(com_cmm_u_cmm_decoder_un11_bar5_32_hit_nc_1_and) + ); + MUXCY_L com_cmm_u_cmm_decoder_un11_bar5_32_hit_nc_2 ( + .CI(com_cmm_u_cmm_decoder_un11_bar5_32_hit_nc_1_4372), + .DI(com_cmm_u_cmm_decoder_GND_4478), + .LO(com_cmm_u_cmm_decoder_un11_bar5_32_hit_nc_2_4373), + .S(com_cmm_u_cmm_decoder_un11_bar5_32_hit_nc_2_and) + ); + MUXCY_L com_cmm_u_cmm_decoder_un11_bar5_32_hit_nc_3 ( + .CI(com_cmm_u_cmm_decoder_un11_bar5_32_hit_nc_2_4373), + .DI(com_cmm_u_cmm_decoder_GND_4478), + .LO(com_cmm_u_cmm_decoder_un11_bar5_32_hit_nc_3_4374), + .S(com_cmm_u_cmm_decoder_un11_bar5_32_hit_nc_3_and) + ); + MUXCY_L com_cmm_u_cmm_decoder_un11_bar5_32_hit_nc_4 ( + .CI(com_cmm_u_cmm_decoder_un11_bar5_32_hit_nc_3_4374), + .DI(com_cmm_u_cmm_decoder_GND_4478), + .LO(com_cmm_u_cmm_decoder_un11_bar5_32_hit_nc_4_4375), + .S(com_cmm_u_cmm_decoder_un11_bar5_32_hit_nc_4_and) + ); + MUXCY_L com_cmm_u_cmm_decoder_un11_bar5_32_hit_nc_5 ( + .CI(com_cmm_u_cmm_decoder_un11_bar5_32_hit_nc_4_4375), + .DI(com_cmm_u_cmm_decoder_GND_4478), + .LO(com_cmm_u_cmm_decoder_un11_bar5_32_hit_nc_5_4376), + .S(com_cmm_u_cmm_decoder_un11_bar5_32_hit_nc_5_and) + ); + MUXCY_L com_cmm_u_cmm_decoder_un11_bar5_32_hit_nc_6 ( + .CI(com_cmm_u_cmm_decoder_un11_bar5_32_hit_nc_5_4376), + .DI(com_cmm_u_cmm_decoder_GND_4478), + .LO(com_cmm_u_cmm_decoder_un11_bar5_32_hit_nc_6_4377), + .S(com_cmm_u_cmm_decoder_un11_bar5_32_hit_nc_6_and) + ); + MUXCY com_cmm_u_cmm_decoder_un11_bar5_32_hit_nc_7 ( + .CI(com_cmm_u_cmm_decoder_un11_bar5_32_hit_nc_6_4377), + .DI(com_cmm_u_cmm_decoder_GND_4478), + .O(com_cmm_u_cmm_decoder_un11_bar5_32_hit_nc_7_4469), + .S(com_cmm_u_cmm_decoder_un11_bar5_32_hit_nc_7_and) + ); + MUXCY_L com_cmm_u_cmm_decoder_un11_bar4_32_hit_nc_1 ( + .CI(com_cmm_u_cmm_decoder_un11_bar4_32_hit_nc_0), + .DI(com_cmm_u_cmm_decoder_GND_4478), + .LO(com_cmm_u_cmm_decoder_un11_bar4_32_hit_nc_1_4378), + .S(com_cmm_u_cmm_decoder_un11_bar4_32_hit_nc_1_sf_4517) + ); + MUXCY_L com_cmm_u_cmm_decoder_un11_bar4_32_hit_nc_2 ( + .CI(com_cmm_u_cmm_decoder_un11_bar4_32_hit_nc_1_4378), + .DI(com_cmm_u_cmm_decoder_GND_4478), + .LO(com_cmm_u_cmm_decoder_un11_bar4_32_hit_nc_2_4379), + .S(com_cmm_u_cmm_decoder_un11_bar4_32_hit_nc_2_sf_4516) + ); + MUXCY_L com_cmm_u_cmm_decoder_un11_bar4_32_hit_nc_3 ( + .CI(com_cmm_u_cmm_decoder_un11_bar4_32_hit_nc_2_4379), + .DI(com_cmm_u_cmm_decoder_GND_4478), + .LO(com_cmm_u_cmm_decoder_un11_bar4_32_hit_nc_3_4380), + .S(com_cmm_u_cmm_decoder_un11_bar4_32_hit_nc_3_sf_4515) + ); + MUXCY_L com_cmm_u_cmm_decoder_un11_bar4_32_hit_nc_4 ( + .CI(com_cmm_u_cmm_decoder_un11_bar4_32_hit_nc_3_4380), + .DI(com_cmm_u_cmm_decoder_GND_4478), + .LO(com_cmm_u_cmm_decoder_un11_bar4_32_hit_nc_4_4381), + .S(com_cmm_u_cmm_decoder_un11_bar4_32_hit_nc_4_sf_4514) + ); + MUXCY_L com_cmm_u_cmm_decoder_un11_bar4_32_hit_nc_5 ( + .CI(com_cmm_u_cmm_decoder_un11_bar4_32_hit_nc_4_4381), + .DI(com_cmm_u_cmm_decoder_GND_4478), + .LO(com_cmm_u_cmm_decoder_un11_bar4_32_hit_nc_5_4382), + .S(com_cmm_u_cmm_decoder_un11_bar4_32_hit_nc_5_sf_4513) + ); + MUXCY_L com_cmm_u_cmm_decoder_un11_bar4_32_hit_nc_6 ( + .CI(com_cmm_u_cmm_decoder_un11_bar4_32_hit_nc_5_4382), + .DI(com_cmm_u_cmm_decoder_GND_4478), + .LO(com_cmm_u_cmm_decoder_un11_bar4_32_hit_nc_6_4383), + .S(com_cmm_u_cmm_decoder_un11_bar4_32_hit_nc_6_sf_4512) + ); + MUXCY_L com_cmm_u_cmm_decoder_un11_bar4_32_hit_nc_7 ( + .CI(com_cmm_u_cmm_decoder_un11_bar4_32_hit_nc_6_4383), + .DI(com_cmm_u_cmm_decoder_GND_4478), + .LO(com_cmm_u_cmm_decoder_un11_bar4_32_hit_nc_7_4384), + .S(com_cmm_u_cmm_decoder_un11_bar4_32_hit_nc_7_sf_4511) + ); + MUXCY com_cmm_u_cmm_decoder_un11_bar4_32_hit_nc_8 ( + .CI(com_cmm_u_cmm_decoder_un11_bar4_32_hit_nc_7_4384), + .DI(com_cmm_u_cmm_decoder_GND_4478), + .O(com_cmm_u_cmm_decoder_un11_bar4_32_hit_nc_8_4461), + .S(cfg_cfg_i_224_) + ); + MUXCY_L com_cmm_u_cmm_decoder_un11_bar3_32_hit_nc_0 ( + .CI(com_cmm_u_cmm_decoder_VCC_4448), + .DI(com_cmm_u_cmm_decoder_GND_4478), + .LO(com_cmm_u_cmm_decoder_un11_bar3_32_hit_nc_0_4385), + .S(com_cmm_u_cmm_decoder_un11_bar3_32_hit_nc_0_and) + ); + MUXCY_L com_cmm_u_cmm_decoder_un11_bar3_32_hit_nc_1 ( + .CI(com_cmm_u_cmm_decoder_un11_bar3_32_hit_nc_0_4385), + .DI(com_cmm_u_cmm_decoder_GND_4478), + .LO(com_cmm_u_cmm_decoder_un11_bar3_32_hit_nc_1_4386), + .S(com_cmm_u_cmm_decoder_un11_bar3_32_hit_nc_1_and) + ); + MUXCY_L com_cmm_u_cmm_decoder_un11_bar3_32_hit_nc_2 ( + .CI(com_cmm_u_cmm_decoder_un11_bar3_32_hit_nc_1_4386), + .DI(com_cmm_u_cmm_decoder_GND_4478), + .LO(com_cmm_u_cmm_decoder_un11_bar3_32_hit_nc_2_4387), + .S(com_cmm_u_cmm_decoder_un11_bar3_32_hit_nc_2_and) + ); + MUXCY_L com_cmm_u_cmm_decoder_un11_bar3_32_hit_nc_3 ( + .CI(com_cmm_u_cmm_decoder_un11_bar3_32_hit_nc_2_4387), + .DI(com_cmm_u_cmm_decoder_GND_4478), + .LO(com_cmm_u_cmm_decoder_un11_bar3_32_hit_nc_3_4388), + .S(com_cmm_u_cmm_decoder_un11_bar3_32_hit_nc_3_and) + ); + MUXCY_L com_cmm_u_cmm_decoder_un11_bar3_32_hit_nc_4 ( + .CI(com_cmm_u_cmm_decoder_un11_bar3_32_hit_nc_3_4388), + .DI(com_cmm_u_cmm_decoder_GND_4478), + .LO(com_cmm_u_cmm_decoder_un11_bar3_32_hit_nc_4_4389), + .S(com_cmm_u_cmm_decoder_un11_bar3_32_hit_nc_4_and) + ); + MUXCY_L com_cmm_u_cmm_decoder_un11_bar3_32_hit_nc_5 ( + .CI(com_cmm_u_cmm_decoder_un11_bar3_32_hit_nc_4_4389), + .DI(com_cmm_u_cmm_decoder_GND_4478), + .LO(com_cmm_u_cmm_decoder_un11_bar3_32_hit_nc_5_4390), + .S(com_cmm_u_cmm_decoder_un11_bar3_32_hit_nc_5_and) + ); + MUXCY_L com_cmm_u_cmm_decoder_un11_bar3_32_hit_nc_6 ( + .CI(com_cmm_u_cmm_decoder_un11_bar3_32_hit_nc_5_4390), + .DI(com_cmm_u_cmm_decoder_GND_4478), + .LO(com_cmm_u_cmm_decoder_un11_bar3_32_hit_nc_6_4391), + .S(com_cmm_u_cmm_decoder_un11_bar3_32_hit_nc_6_and) + ); + MUXCY com_cmm_u_cmm_decoder_un11_bar3_32_hit_nc_7 ( + .CI(com_cmm_u_cmm_decoder_un11_bar3_32_hit_nc_6_4391), + .DI(com_cmm_u_cmm_decoder_GND_4478), + .O(com_cmm_u_cmm_decoder_un11_bar3_32_hit_nc_7_4471), + .S(com_cmm_u_cmm_decoder_un11_bar3_32_hit_nc_7_and) + ); + MUXCY_L com_cmm_u_cmm_decoder_un11_bar2_32_hit_nc_0 ( + .CI(com_cmm_u_cmm_decoder_VCC_4448), + .DI(com_cmm_u_cmm_decoder_GND_4478), + .LO(com_cmm_u_cmm_decoder_un11_bar2_32_hit_nc_0_4392), + .S(com_cmm_u_cmm_decoder_un11_bar2_32_hit_nc_0_and) + ); + MUXCY_L com_cmm_u_cmm_decoder_un11_bar2_32_hit_nc_1 ( + .CI(com_cmm_u_cmm_decoder_un11_bar2_32_hit_nc_0_4392), + .DI(com_cmm_u_cmm_decoder_GND_4478), + .LO(com_cmm_u_cmm_decoder_un11_bar2_32_hit_nc_1_4393), + .S(com_cmm_u_cmm_decoder_un11_bar2_32_hit_nc_1_and) + ); + MUXCY_L com_cmm_u_cmm_decoder_un11_bar2_32_hit_nc_2 ( + .CI(com_cmm_u_cmm_decoder_un11_bar2_32_hit_nc_1_4393), + .DI(com_cmm_u_cmm_decoder_GND_4478), + .LO(com_cmm_u_cmm_decoder_un11_bar2_32_hit_nc_2_4394), + .S(com_cmm_u_cmm_decoder_un11_bar2_32_hit_nc_2_and) + ); + MUXCY_L com_cmm_u_cmm_decoder_un11_bar2_32_hit_nc_3 ( + .CI(com_cmm_u_cmm_decoder_un11_bar2_32_hit_nc_2_4394), + .DI(com_cmm_u_cmm_decoder_GND_4478), + .LO(com_cmm_u_cmm_decoder_un11_bar2_32_hit_nc_3_4395), + .S(com_cmm_u_cmm_decoder_un11_bar2_32_hit_nc_3_and) + ); + MUXCY_L com_cmm_u_cmm_decoder_un11_bar2_32_hit_nc_4 ( + .CI(com_cmm_u_cmm_decoder_un11_bar2_32_hit_nc_3_4395), + .DI(com_cmm_u_cmm_decoder_GND_4478), + .LO(com_cmm_u_cmm_decoder_un11_bar2_32_hit_nc_4_4396), + .S(com_cmm_u_cmm_decoder_un11_bar2_32_hit_nc_4_and) + ); + MUXCY_L com_cmm_u_cmm_decoder_un11_bar2_32_hit_nc_5 ( + .CI(com_cmm_u_cmm_decoder_un11_bar2_32_hit_nc_4_4396), + .DI(com_cmm_u_cmm_decoder_GND_4478), + .LO(com_cmm_u_cmm_decoder_un11_bar2_32_hit_nc_5_4397), + .S(com_cmm_u_cmm_decoder_un11_bar2_32_hit_nc_5_and) + ); + MUXCY_L com_cmm_u_cmm_decoder_un11_bar2_32_hit_nc_6 ( + .CI(com_cmm_u_cmm_decoder_un11_bar2_32_hit_nc_5_4397), + .DI(com_cmm_u_cmm_decoder_GND_4478), + .LO(com_cmm_u_cmm_decoder_un11_bar2_32_hit_nc_6_4398), + .S(com_cmm_u_cmm_decoder_un11_bar2_32_hit_nc_6_and) + ); + MUXCY com_cmm_u_cmm_decoder_un11_bar2_32_hit_nc_7 ( + .CI(com_cmm_u_cmm_decoder_un11_bar2_32_hit_nc_6_4398), + .DI(com_cmm_u_cmm_decoder_GND_4478), + .O(com_cmm_u_cmm_decoder_un11_bar2_32_hit_nc_7_4472), + .S(com_cmm_u_cmm_decoder_un11_bar2_32_hit_nc_7_and) + ); + MUXCY_L com_cmm_u_cmm_decoder_un11_bar1_32_hit_nc_0 ( + .CI(com_cmm_u_cmm_decoder_VCC_4448), + .DI(com_cmm_u_cmm_decoder_GND_4478), + .LO(com_cmm_u_cmm_decoder_un11_bar1_32_hit_nc_0_4399), + .S(com_cmm_u_cmm_decoder_un11_bar1_32_hit_nc_0_and) + ); + MUXCY_L com_cmm_u_cmm_decoder_un11_bar1_32_hit_nc_1 ( + .CI(com_cmm_u_cmm_decoder_un11_bar1_32_hit_nc_0_4399), + .DI(com_cmm_u_cmm_decoder_GND_4478), + .LO(com_cmm_u_cmm_decoder_un11_bar1_32_hit_nc_1_4400), + .S(com_cmm_u_cmm_decoder_un11_bar1_32_hit_nc_1_and) + ); + MUXCY_L com_cmm_u_cmm_decoder_un11_bar1_32_hit_nc_2 ( + .CI(com_cmm_u_cmm_decoder_un11_bar1_32_hit_nc_1_4400), + .DI(com_cmm_u_cmm_decoder_GND_4478), + .LO(com_cmm_u_cmm_decoder_un11_bar1_32_hit_nc_2_4401), + .S(com_cmm_u_cmm_decoder_un11_bar1_32_hit_nc_2_and) + ); + MUXCY_L com_cmm_u_cmm_decoder_un11_bar1_32_hit_nc_3 ( + .CI(com_cmm_u_cmm_decoder_un11_bar1_32_hit_nc_2_4401), + .DI(com_cmm_u_cmm_decoder_GND_4478), + .LO(com_cmm_u_cmm_decoder_un11_bar1_32_hit_nc_3_4402), + .S(com_cmm_u_cmm_decoder_un11_bar1_32_hit_nc_3_and) + ); + MUXCY_L com_cmm_u_cmm_decoder_un11_bar1_32_hit_nc_4 ( + .CI(com_cmm_u_cmm_decoder_un11_bar1_32_hit_nc_3_4402), + .DI(com_cmm_u_cmm_decoder_GND_4478), + .LO(com_cmm_u_cmm_decoder_un11_bar1_32_hit_nc_4_4403), + .S(com_cmm_u_cmm_decoder_un11_bar1_32_hit_nc_4_and) + ); + MUXCY_L com_cmm_u_cmm_decoder_un11_bar1_32_hit_nc_5 ( + .CI(com_cmm_u_cmm_decoder_un11_bar1_32_hit_nc_4_4403), + .DI(com_cmm_u_cmm_decoder_GND_4478), + .LO(com_cmm_u_cmm_decoder_un11_bar1_32_hit_nc_5_4404), + .S(com_cmm_u_cmm_decoder_un11_bar1_32_hit_nc_5_and) + ); + MUXCY_L com_cmm_u_cmm_decoder_un11_bar1_32_hit_nc_6 ( + .CI(com_cmm_u_cmm_decoder_un11_bar1_32_hit_nc_5_4404), + .DI(com_cmm_u_cmm_decoder_GND_4478), + .LO(com_cmm_u_cmm_decoder_un11_bar1_32_hit_nc_6_4405), + .S(com_cmm_u_cmm_decoder_un11_bar1_32_hit_nc_6_and) + ); + MUXCY com_cmm_u_cmm_decoder_un11_bar1_32_hit_nc_7 ( + .CI(com_cmm_u_cmm_decoder_un11_bar1_32_hit_nc_6_4405), + .DI(com_cmm_u_cmm_decoder_GND_4478), + .O(com_cmm_u_cmm_decoder_un11_bar1_32_hit_nc_7_4473), + .S(com_cmm_u_cmm_decoder_un11_bar1_32_hit_nc_7_and) + ); + MUXCY_L com_cmm_u_cmm_decoder_un18_bar4_32_hit_nc_0 ( + .CI(com_cmm_u_cmm_decoder_VCC_4448), + .DI(com_cmm_u_cmm_decoder_GND_4478), + .LO(com_cmm_u_cmm_decoder_un18_bar4_32_hit_nc_0_4406), + .S(com_cmm_u_cmm_decoder_un18_bar4_32_hit_nc_0_and) + ); + MUXCY_L com_cmm_u_cmm_decoder_un18_bar4_32_hit_nc_1 ( + .CI(com_cmm_u_cmm_decoder_un18_bar4_32_hit_nc_0_4406), + .DI(com_cmm_u_cmm_decoder_GND_4478), + .LO(com_cmm_u_cmm_decoder_un18_bar4_32_hit_nc_1_4407), + .S(com_cmm_u_cmm_decoder_un18_bar4_32_hit_nc_1_and) + ); + MUXCY_L com_cmm_u_cmm_decoder_un18_bar4_32_hit_nc_2 ( + .CI(com_cmm_u_cmm_decoder_un18_bar4_32_hit_nc_1_4407), + .DI(com_cmm_u_cmm_decoder_GND_4478), + .LO(com_cmm_u_cmm_decoder_un18_bar4_32_hit_nc_2_4408), + .S(com_cmm_u_cmm_decoder_un18_bar4_32_hit_nc_2_and) + ); + MUXCY_L com_cmm_u_cmm_decoder_un18_bar4_32_hit_nc_3 ( + .CI(com_cmm_u_cmm_decoder_un18_bar4_32_hit_nc_2_4408), + .DI(com_cmm_u_cmm_decoder_GND_4478), + .LO(com_cmm_u_cmm_decoder_un18_bar4_32_hit_nc_3_4409), + .S(com_cmm_u_cmm_decoder_un18_bar4_32_hit_nc_3_and) + ); + MUXCY_L com_cmm_u_cmm_decoder_un18_bar4_32_hit_nc_4 ( + .CI(com_cmm_u_cmm_decoder_un18_bar4_32_hit_nc_3_4409), + .DI(com_cmm_u_cmm_decoder_GND_4478), + .LO(com_cmm_u_cmm_decoder_un18_bar4_32_hit_nc_4_4410), + .S(com_cmm_u_cmm_decoder_un18_bar4_32_hit_nc_4_and) + ); + MUXCY_L com_cmm_u_cmm_decoder_un18_bar4_32_hit_nc_5 ( + .CI(com_cmm_u_cmm_decoder_un18_bar4_32_hit_nc_4_4410), + .DI(com_cmm_u_cmm_decoder_GND_4478), + .LO(com_cmm_u_cmm_decoder_un18_bar4_32_hit_nc_5_4411), + .S(com_cmm_u_cmm_decoder_un18_bar4_32_hit_nc_5_and) + ); + MUXCY_L com_cmm_u_cmm_decoder_un18_bar4_32_hit_nc_6 ( + .CI(com_cmm_u_cmm_decoder_un18_bar4_32_hit_nc_5_4411), + .DI(com_cmm_u_cmm_decoder_GND_4478), + .LO(com_cmm_u_cmm_decoder_un18_bar4_32_hit_nc_6_4412), + .S(com_cmm_u_cmm_decoder_un18_bar4_32_hit_nc_6_and) + ); + MUXCY com_cmm_u_cmm_decoder_un18_bar4_32_hit_nc_7 ( + .CI(com_cmm_u_cmm_decoder_un18_bar4_32_hit_nc_6_4412), + .DI(com_cmm_u_cmm_decoder_GND_4478), + .O(com_cmm_u_cmm_decoder_un18_bar4_32_hit_nc_7_4460), + .S(com_cmm_u_cmm_decoder_un18_bar4_32_hit_nc_7_and) + ); + MUXCY_L com_cmm_u_cmm_decoder_un18_bar3_32_hit_nc_0 ( + .CI(com_cmm_u_cmm_decoder_VCC_4448), + .DI(com_cmm_u_cmm_decoder_GND_4478), + .LO(com_cmm_u_cmm_decoder_un18_bar3_32_hit_nc_0_4413), + .S(com_cmm_u_cmm_decoder_un18_bar3_32_hit_nc_0_and) + ); + MUXCY_L com_cmm_u_cmm_decoder_un18_bar3_32_hit_nc_1 ( + .CI(com_cmm_u_cmm_decoder_un18_bar3_32_hit_nc_0_4413), + .DI(com_cmm_u_cmm_decoder_GND_4478), + .LO(com_cmm_u_cmm_decoder_un18_bar3_32_hit_nc_1_4414), + .S(com_cmm_u_cmm_decoder_un18_bar3_32_hit_nc_1_and) + ); + MUXCY_L com_cmm_u_cmm_decoder_un18_bar3_32_hit_nc_2 ( + .CI(com_cmm_u_cmm_decoder_un18_bar3_32_hit_nc_1_4414), + .DI(com_cmm_u_cmm_decoder_GND_4478), + .LO(com_cmm_u_cmm_decoder_un18_bar3_32_hit_nc_2_4415), + .S(com_cmm_u_cmm_decoder_un18_bar3_32_hit_nc_2_and) + ); + MUXCY_L com_cmm_u_cmm_decoder_un18_bar3_32_hit_nc_3 ( + .CI(com_cmm_u_cmm_decoder_un18_bar3_32_hit_nc_2_4415), + .DI(com_cmm_u_cmm_decoder_GND_4478), + .LO(com_cmm_u_cmm_decoder_un18_bar3_32_hit_nc_3_4416), + .S(com_cmm_u_cmm_decoder_un18_bar3_32_hit_nc_3_and) + ); + MUXCY_L com_cmm_u_cmm_decoder_un18_bar3_32_hit_nc_4 ( + .CI(com_cmm_u_cmm_decoder_un18_bar3_32_hit_nc_3_4416), + .DI(com_cmm_u_cmm_decoder_GND_4478), + .LO(com_cmm_u_cmm_decoder_un18_bar3_32_hit_nc_4_4417), + .S(com_cmm_u_cmm_decoder_un18_bar3_32_hit_nc_4_and) + ); + MUXCY_L com_cmm_u_cmm_decoder_un18_bar3_32_hit_nc_5 ( + .CI(com_cmm_u_cmm_decoder_un18_bar3_32_hit_nc_4_4417), + .DI(com_cmm_u_cmm_decoder_GND_4478), + .LO(com_cmm_u_cmm_decoder_un18_bar3_32_hit_nc_5_4418), + .S(com_cmm_u_cmm_decoder_un18_bar3_32_hit_nc_5_and) + ); + MUXCY_L com_cmm_u_cmm_decoder_un18_bar3_32_hit_nc_6 ( + .CI(com_cmm_u_cmm_decoder_un18_bar3_32_hit_nc_5_4418), + .DI(com_cmm_u_cmm_decoder_GND_4478), + .LO(com_cmm_u_cmm_decoder_un18_bar3_32_hit_nc_6_4419), + .S(com_cmm_u_cmm_decoder_un18_bar3_32_hit_nc_6_and) + ); + MUXCY com_cmm_u_cmm_decoder_un18_bar3_32_hit_nc_7 ( + .CI(com_cmm_u_cmm_decoder_un18_bar3_32_hit_nc_6_4419), + .DI(com_cmm_u_cmm_decoder_GND_4478), + .O(com_cmm_u_cmm_decoder_un18_bar3_32_hit_nc_7_4463), + .S(com_cmm_u_cmm_decoder_un18_bar3_32_hit_nc_7_and) + ); + MUXCY_L com_cmm_u_cmm_decoder_un18_bar2_32_hit_nc_0 ( + .CI(com_cmm_u_cmm_decoder_VCC_4448), + .DI(com_cmm_u_cmm_decoder_GND_4478), + .LO(com_cmm_u_cmm_decoder_un18_bar2_32_hit_nc_0_4420), + .S(com_cmm_u_cmm_decoder_un18_bar2_32_hit_nc_0_and) + ); + MUXCY_L com_cmm_u_cmm_decoder_un18_bar2_32_hit_nc_1 ( + .CI(com_cmm_u_cmm_decoder_un18_bar2_32_hit_nc_0_4420), + .DI(com_cmm_u_cmm_decoder_GND_4478), + .LO(com_cmm_u_cmm_decoder_un18_bar2_32_hit_nc_1_4421), + .S(com_cmm_u_cmm_decoder_un18_bar2_32_hit_nc_1_and) + ); + MUXCY_L com_cmm_u_cmm_decoder_un18_bar2_32_hit_nc_2 ( + .CI(com_cmm_u_cmm_decoder_un18_bar2_32_hit_nc_1_4421), + .DI(com_cmm_u_cmm_decoder_GND_4478), + .LO(com_cmm_u_cmm_decoder_un18_bar2_32_hit_nc_2_4422), + .S(com_cmm_u_cmm_decoder_un18_bar2_32_hit_nc_2_and) + ); + MUXCY_L com_cmm_u_cmm_decoder_un18_bar2_32_hit_nc_3 ( + .CI(com_cmm_u_cmm_decoder_un18_bar2_32_hit_nc_2_4422), + .DI(com_cmm_u_cmm_decoder_GND_4478), + .LO(com_cmm_u_cmm_decoder_un18_bar2_32_hit_nc_3_4423), + .S(com_cmm_u_cmm_decoder_un18_bar2_32_hit_nc_3_and) + ); + MUXCY_L com_cmm_u_cmm_decoder_un18_bar2_32_hit_nc_4 ( + .CI(com_cmm_u_cmm_decoder_un18_bar2_32_hit_nc_3_4423), + .DI(com_cmm_u_cmm_decoder_GND_4478), + .LO(com_cmm_u_cmm_decoder_un18_bar2_32_hit_nc_4_4424), + .S(com_cmm_u_cmm_decoder_un18_bar2_32_hit_nc_4_and) + ); + MUXCY_L com_cmm_u_cmm_decoder_un18_bar2_32_hit_nc_5 ( + .CI(com_cmm_u_cmm_decoder_un18_bar2_32_hit_nc_4_4424), + .DI(com_cmm_u_cmm_decoder_GND_4478), + .LO(com_cmm_u_cmm_decoder_un18_bar2_32_hit_nc_5_4425), + .S(com_cmm_u_cmm_decoder_un18_bar2_32_hit_nc_5_and) + ); + MUXCY_L com_cmm_u_cmm_decoder_un18_bar2_32_hit_nc_6 ( + .CI(com_cmm_u_cmm_decoder_un18_bar2_32_hit_nc_5_4425), + .DI(com_cmm_u_cmm_decoder_GND_4478), + .LO(com_cmm_u_cmm_decoder_un18_bar2_32_hit_nc_6_4426), + .S(com_cmm_u_cmm_decoder_un18_bar2_32_hit_nc_6_and) + ); + MUXCY com_cmm_u_cmm_decoder_un18_bar2_32_hit_nc_7 ( + .CI(com_cmm_u_cmm_decoder_un18_bar2_32_hit_nc_6_4426), + .DI(com_cmm_u_cmm_decoder_GND_4478), + .O(com_cmm_u_cmm_decoder_un18_bar2_32_hit_nc_7_4465), + .S(com_cmm_u_cmm_decoder_un18_bar2_32_hit_nc_7_and) + ); + MUXCY_L com_cmm_u_cmm_decoder_un18_bar1_32_hit_nc_0 ( + .CI(com_cmm_u_cmm_decoder_VCC_4448), + .DI(com_cmm_u_cmm_decoder_GND_4478), + .LO(com_cmm_u_cmm_decoder_un18_bar1_32_hit_nc_0_4427), + .S(com_cmm_u_cmm_decoder_un18_bar1_32_hit_nc_0_and) + ); + MUXCY_L com_cmm_u_cmm_decoder_un18_bar1_32_hit_nc_1 ( + .CI(com_cmm_u_cmm_decoder_un18_bar1_32_hit_nc_0_4427), + .DI(com_cmm_u_cmm_decoder_GND_4478), + .LO(com_cmm_u_cmm_decoder_un18_bar1_32_hit_nc_1_4428), + .S(com_cmm_u_cmm_decoder_un18_bar1_32_hit_nc_1_and) + ); + MUXCY_L com_cmm_u_cmm_decoder_un18_bar1_32_hit_nc_2 ( + .CI(com_cmm_u_cmm_decoder_un18_bar1_32_hit_nc_1_4428), + .DI(com_cmm_u_cmm_decoder_GND_4478), + .LO(com_cmm_u_cmm_decoder_un18_bar1_32_hit_nc_2_4429), + .S(com_cmm_u_cmm_decoder_un18_bar1_32_hit_nc_2_and) + ); + MUXCY_L com_cmm_u_cmm_decoder_un18_bar1_32_hit_nc_3 ( + .CI(com_cmm_u_cmm_decoder_un18_bar1_32_hit_nc_2_4429), + .DI(com_cmm_u_cmm_decoder_GND_4478), + .LO(com_cmm_u_cmm_decoder_un18_bar1_32_hit_nc_3_4430), + .S(com_cmm_u_cmm_decoder_un18_bar1_32_hit_nc_3_and) + ); + MUXCY_L com_cmm_u_cmm_decoder_un18_bar1_32_hit_nc_4 ( + .CI(com_cmm_u_cmm_decoder_un18_bar1_32_hit_nc_3_4430), + .DI(com_cmm_u_cmm_decoder_GND_4478), + .LO(com_cmm_u_cmm_decoder_un18_bar1_32_hit_nc_4_4431), + .S(com_cmm_u_cmm_decoder_un18_bar1_32_hit_nc_4_and) + ); + MUXCY_L com_cmm_u_cmm_decoder_un18_bar1_32_hit_nc_5 ( + .CI(com_cmm_u_cmm_decoder_un18_bar1_32_hit_nc_4_4431), + .DI(com_cmm_u_cmm_decoder_GND_4478), + .LO(com_cmm_u_cmm_decoder_un18_bar1_32_hit_nc_5_4432), + .S(com_cmm_u_cmm_decoder_un18_bar1_32_hit_nc_5_and) + ); + MUXCY_L com_cmm_u_cmm_decoder_un18_bar1_32_hit_nc_6 ( + .CI(com_cmm_u_cmm_decoder_un18_bar1_32_hit_nc_5_4432), + .DI(com_cmm_u_cmm_decoder_GND_4478), + .LO(com_cmm_u_cmm_decoder_un18_bar1_32_hit_nc_6_4433), + .S(com_cmm_u_cmm_decoder_un18_bar1_32_hit_nc_6_and) + ); + MUXCY com_cmm_u_cmm_decoder_un18_bar1_32_hit_nc_7 ( + .CI(com_cmm_u_cmm_decoder_un18_bar1_32_hit_nc_6_4433), + .DI(com_cmm_u_cmm_decoder_GND_4478), + .O(com_cmm_u_cmm_decoder_un18_bar1_32_hit_nc_7_4467), + .S(com_cmm_u_cmm_decoder_un18_bar1_32_hit_nc_7_and) + ); + MUXCY_L com_cmm_u_cmm_decoder_un18_bar0_32_hit_nc_0 ( + .CI(com_cmm_u_cmm_decoder_VCC_4448), + .DI(com_cmm_u_cmm_decoder_GND_4478), + .LO(com_cmm_u_cmm_decoder_un18_bar0_32_hit_nc_0_4434), + .S(com_cmm_u_cmm_decoder_un18_bar0_32_hit_nc_0_and) + ); + MUXCY_L com_cmm_u_cmm_decoder_un18_bar0_32_hit_nc_1 ( + .CI(com_cmm_u_cmm_decoder_un18_bar0_32_hit_nc_0_4434), + .DI(com_cmm_u_cmm_decoder_GND_4478), + .LO(com_cmm_u_cmm_decoder_un18_bar0_32_hit_nc_1_4435), + .S(com_cmm_u_cmm_decoder_un18_bar0_32_hit_nc_1_and) + ); + MUXCY_L com_cmm_u_cmm_decoder_un18_bar0_32_hit_nc_2 ( + .CI(com_cmm_u_cmm_decoder_un18_bar0_32_hit_nc_1_4435), + .DI(com_cmm_u_cmm_decoder_GND_4478), + .LO(com_cmm_u_cmm_decoder_un18_bar0_32_hit_nc_2_4436), + .S(com_cmm_u_cmm_decoder_un18_bar0_32_hit_nc_2_and) + ); + MUXCY_L com_cmm_u_cmm_decoder_un18_bar0_32_hit_nc_3 ( + .CI(com_cmm_u_cmm_decoder_un18_bar0_32_hit_nc_2_4436), + .DI(com_cmm_u_cmm_decoder_GND_4478), + .LO(com_cmm_u_cmm_decoder_un18_bar0_32_hit_nc_3_4437), + .S(com_cmm_u_cmm_decoder_un18_bar0_32_hit_nc_3_and) + ); + MUXCY_L com_cmm_u_cmm_decoder_un18_bar0_32_hit_nc_4 ( + .CI(com_cmm_u_cmm_decoder_un18_bar0_32_hit_nc_3_4437), + .DI(com_cmm_u_cmm_decoder_GND_4478), + .LO(com_cmm_u_cmm_decoder_un18_bar0_32_hit_nc_4_4438), + .S(com_cmm_u_cmm_decoder_un18_bar0_32_hit_nc_4_and) + ); + MUXCY_L com_cmm_u_cmm_decoder_un18_bar0_32_hit_nc_5 ( + .CI(com_cmm_u_cmm_decoder_un18_bar0_32_hit_nc_4_4438), + .DI(com_cmm_u_cmm_decoder_GND_4478), + .LO(com_cmm_u_cmm_decoder_un18_bar0_32_hit_nc_5_4439), + .S(com_cmm_u_cmm_decoder_un18_bar0_32_hit_nc_5_and) + ); + MUXCY_L com_cmm_u_cmm_decoder_un18_bar0_32_hit_nc_6 ( + .CI(com_cmm_u_cmm_decoder_un18_bar0_32_hit_nc_5_4439), + .DI(com_cmm_u_cmm_decoder_GND_4478), + .LO(com_cmm_u_cmm_decoder_un18_bar0_32_hit_nc_6_4440), + .S(com_cmm_u_cmm_decoder_un18_bar0_32_hit_nc_6_and) + ); + MUXCY com_cmm_u_cmm_decoder_un18_bar0_32_hit_nc_7 ( + .CI(com_cmm_u_cmm_decoder_un18_bar0_32_hit_nc_6_4440), + .DI(com_cmm_u_cmm_decoder_GND_4478), + .O(com_cmm_u_cmm_decoder_un18_bar0_32_hit_nc_7_4457), + .S(com_cmm_u_cmm_decoder_un18_bar0_32_hit_nc_7_and) + ); + MUXCY_L com_cmm_u_cmm_decoder_un11_bar0_32_hit_nc_0 ( + .CI(com_cmm_u_cmm_decoder_VCC_4448), + .DI(com_cmm_u_cmm_decoder_GND_4478), + .LO(com_cmm_u_cmm_decoder_un11_bar0_32_hit_nc_0_4441), + .S(com_cmm_u_cmm_decoder_un11_bar0_32_hit_nc_0_and) + ); + MUXCY_L com_cmm_u_cmm_decoder_un11_bar0_32_hit_nc_1 ( + .CI(com_cmm_u_cmm_decoder_un11_bar0_32_hit_nc_0_4441), + .DI(com_cmm_u_cmm_decoder_GND_4478), + .LO(com_cmm_u_cmm_decoder_un11_bar0_32_hit_nc_1_4442), + .S(com_cmm_u_cmm_decoder_un11_bar0_32_hit_nc_1_and) + ); + MUXCY_L com_cmm_u_cmm_decoder_un11_bar0_32_hit_nc_2 ( + .CI(com_cmm_u_cmm_decoder_un11_bar0_32_hit_nc_1_4442), + .DI(com_cmm_u_cmm_decoder_GND_4478), + .LO(com_cmm_u_cmm_decoder_un11_bar0_32_hit_nc_2_4443), + .S(com_cmm_u_cmm_decoder_un11_bar0_32_hit_nc_2_and) + ); + MUXCY_L com_cmm_u_cmm_decoder_un11_bar0_32_hit_nc_3 ( + .CI(com_cmm_u_cmm_decoder_un11_bar0_32_hit_nc_2_4443), + .DI(com_cmm_u_cmm_decoder_GND_4478), + .LO(com_cmm_u_cmm_decoder_un11_bar0_32_hit_nc_3_4444), + .S(com_cmm_u_cmm_decoder_un11_bar0_32_hit_nc_3_and) + ); + MUXCY_L com_cmm_u_cmm_decoder_un11_bar0_32_hit_nc_4 ( + .CI(com_cmm_u_cmm_decoder_un11_bar0_32_hit_nc_3_4444), + .DI(com_cmm_u_cmm_decoder_GND_4478), + .LO(com_cmm_u_cmm_decoder_un11_bar0_32_hit_nc_4_4445), + .S(com_cmm_u_cmm_decoder_un11_bar0_32_hit_nc_4_and) + ); + MUXCY_L com_cmm_u_cmm_decoder_un11_bar0_32_hit_nc_5 ( + .CI(com_cmm_u_cmm_decoder_un11_bar0_32_hit_nc_4_4445), + .DI(com_cmm_u_cmm_decoder_GND_4478), + .LO(com_cmm_u_cmm_decoder_un11_bar0_32_hit_nc_5_4446), + .S(com_cmm_u_cmm_decoder_un11_bar0_32_hit_nc_5_and) + ); + MUXCY_L com_cmm_u_cmm_decoder_un11_bar0_32_hit_nc_6 ( + .CI(com_cmm_u_cmm_decoder_un11_bar0_32_hit_nc_5_4446), + .DI(com_cmm_u_cmm_decoder_GND_4478), + .LO(com_cmm_u_cmm_decoder_un11_bar0_32_hit_nc_6_4447), + .S(com_cmm_u_cmm_decoder_un11_bar0_32_hit_nc_6_and) + ); + MUXCY com_cmm_u_cmm_decoder_un11_bar0_32_hit_nc_7 ( + .CI(com_cmm_u_cmm_decoder_un11_bar0_32_hit_nc_6_4447), + .DI(com_cmm_u_cmm_decoder_GND_4478), + .O(com_cmm_u_cmm_decoder_un11_bar0_32_hit_nc_7_4459), + .S(com_cmm_u_cmm_decoder_un11_bar0_32_hit_nc_7_and) + ); + MUXCY_L com_cmm_u_cmm_decoder_un7_bar6_32_hit_nc_0 ( + .CI(com_cmm_u_cmm_decoder_VCC_4448), + .DI(com_cmm_u_cmm_decoder_GND_4478), + .LO(com_cmm_u_cmm_decoder_un7_bar6_32_hit_nc_0_4449), + .S(com_cmm_u_cmm_decoder_un7_bar6_32_hit_nc_0_and_4510) + ); + MUXCY_L com_cmm_u_cmm_decoder_un7_bar6_32_hit_nc_1 ( + .CI(com_cmm_u_cmm_decoder_un7_bar6_32_hit_nc_0_4449), + .DI(com_cmm_u_cmm_decoder_GND_4478), + .LO(com_cmm_u_cmm_decoder_un7_bar6_32_hit_nc_1_4450), + .S(com_cmm_u_cmm_decoder_un7_bar6_32_hit_nc_1_and) + ); + MUXCY_L com_cmm_u_cmm_decoder_un7_bar6_32_hit_nc_2 ( + .CI(com_cmm_u_cmm_decoder_un7_bar6_32_hit_nc_1_4450), + .DI(com_cmm_u_cmm_decoder_GND_4478), + .LO(com_cmm_u_cmm_decoder_un7_bar6_32_hit_nc_2_4451), + .S(com_cmm_u_cmm_decoder_un7_bar6_32_hit_nc_2_and) + ); + MUXCY_L com_cmm_u_cmm_decoder_un7_bar6_32_hit_nc_3 ( + .CI(com_cmm_u_cmm_decoder_un7_bar6_32_hit_nc_2_4451), + .DI(com_cmm_u_cmm_decoder_GND_4478), + .LO(com_cmm_u_cmm_decoder_un7_bar6_32_hit_nc_3_4452), + .S(com_cmm_u_cmm_decoder_un7_bar6_32_hit_nc_3_and) + ); + MUXCY_L com_cmm_u_cmm_decoder_un7_bar6_32_hit_nc_4 ( + .CI(com_cmm_u_cmm_decoder_un7_bar6_32_hit_nc_3_4452), + .DI(com_cmm_u_cmm_decoder_GND_4478), + .LO(com_cmm_u_cmm_decoder_un7_bar6_32_hit_nc_4_4453), + .S(com_cmm_u_cmm_decoder_un7_bar6_32_hit_nc_4_and) + ); + MUXCY_L com_cmm_u_cmm_decoder_un7_bar6_32_hit_nc_5 ( + .CI(com_cmm_u_cmm_decoder_un7_bar6_32_hit_nc_4_4453), + .DI(com_cmm_u_cmm_decoder_GND_4478), + .LO(com_cmm_u_cmm_decoder_un7_bar6_32_hit_nc_5_4454), + .S(com_cmm_u_cmm_decoder_un7_bar6_32_hit_nc_5_and) + ); + MUXCY com_cmm_u_cmm_decoder_un7_bar6_32_hit_nc_6 ( + .CI(com_cmm_u_cmm_decoder_un7_bar6_32_hit_nc_5_4454), + .DI(com_cmm_u_cmm_decoder_GND_4478), + .O(com_cmm_u_cmm_decoder_un7_bar6_32_hit_nc_6_4456), + .S(cfg_cfg_i_351_) + ); + defparam com_cmm_u_cmm_decoder_bar5_32_hit_nc_3_i_0_0_o3_0.INIT = 4'h8; + LUT2 com_cmm_u_cmm_decoder_bar5_32_hit_nc_3_i_0_0_o3_0 ( + .I0(NlwRenamedSig_OI_cfg_command_0_), + .I1(com_cmmt_rio), + .O(com_cmm_u_cmm_decoder_bar5_32_hit_nc_3_i_0_0_o3_0_4455) + ); + defparam com_cmm_u_cmm_decoder_un18_bar3_32_hit_nc_0_and_0_a2_0_a2_0_a2_0_a2_1.INIT = 4'h1; + LUT2 com_cmm_u_cmm_decoder_un18_bar3_32_hit_nc_0_and_0_a2_0_a2_0_a2_0_a2_1 ( + .I0(com_cmm_bar4_reg[0]), + .I1(com_cmm_bar4_reg[1]), + .O(com_cmm_u_cmm_decoder_un18_bar3_32_hit_nc_0_and_1) + ); + defparam com_cmm_u_cmm_decoder_bar4_32_hit_nc_3_i_0_0_0_o2.INIT = 4'h1; + LUT2 com_cmm_u_cmm_decoder_bar4_32_hit_nc_3_i_0_0_0_o2 ( + .I0(com_cmm_pme_pmcsr[0]), + .I1(com_cmm_pme_pmcsr[1]), + .O(com_cmm_u_cmm_decoder_N_48989_i) + ); + defparam com_cmm_u_cmm_decoder_un11_bar2_32_hit_nc_0_and_0_a2_0_a2_0_o3.INIT = 4'h1; + LUT2 com_cmm_u_cmm_decoder_un11_bar2_32_hit_nc_0_and_0_a2_0_a2_0_o3 ( + .I0(cfg_cfg_5072[128]), + .I1(cfg_cfg_5072[129]), + .O(com_cmm_N_48884_i) + ); + defparam com_cmm_u_cmm_decoder_un11_bar1_32_hit_nc_0_and_0_a2_0_a2_0_a2_0_o3.INIT = 4'h1; + LUT2 com_cmm_u_cmm_decoder_un11_bar1_32_hit_nc_0_and_0_a2_0_a2_0_a2_0_o3 ( + .I0(cfg_cfg_5072[96]), + .I1(cfg_cfg_5072[97]), + .O(com_cmm_N_48883_i) + ); + defparam com_cmm_u_cmm_decoder_un18_bar2_32_hit_nc_0_and_0_a2_0_a2_0_a2_1.INIT = 4'h1; + LUT2_L com_cmm_u_cmm_decoder_un18_bar2_32_hit_nc_0_and_0_a2_0_a2_0_a2_1 ( + .I0(com_cmm_bar3_reg[0]), + .I1(com_cmm_bar3_reg[1]), + .LO(com_cmm_u_cmm_decoder_un18_bar2_32_hit_nc_0_and_1) + ); + defparam com_cmm_u_cmm_decoder_bar23_64_hit_high_3_0_a2_0_a2_0_a2_1.INIT = 4'h1; + LUT2_L com_cmm_u_cmm_decoder_bar23_64_hit_high_3_0_a2_0_a2_0_a2_1 ( + .I0(com_cmm_bar2_reg[0]), + .I1(com_cmm_bar2_reg[1]), + .LO(com_cmm_u_cmm_decoder_bar23_64_hit_high_3_1) + ); + defparam com_cmm_u_cmm_decoder_un18_bar0_32_hit_nc_0_and_0_a2_0_a2_0_a2_1.INIT = 4'h1; + LUT2_L com_cmm_u_cmm_decoder_un18_bar0_32_hit_nc_0_and_0_a2_0_a2_0_a2_1 ( + .I0(com_cmm_bar1_reg[0]), + .I1(com_cmm_bar1_reg[1]), + .LO(com_cmm_u_cmm_decoder_un18_bar0_32_hit_nc_0_and_1) + ); + defparam com_cmm_u_cmm_decoder_bar5_32_hit_nc_3_i_0_0_o3.INIT = 4'h8; + LUT2 com_cmm_u_cmm_decoder_bar5_32_hit_nc_3_i_0_0_o3 ( + .I0(NlwRenamedSig_OI_cfg_command_1_), + .I1(com_cmmt_mem32), + .O(com_cmm_u_cmm_decoder_N_44866_i) + ); + defparam com_cmm_u_cmm_decoder_un9_bar34_64_hit_high_0_I_95.INIT = 8'h6C; + LUT3_L com_cmm_u_cmm_decoder_un9_bar34_64_hit_high_0_I_95 ( + .I0(cfg_cfg_5072[167]), + .I1(com_cmm_bar3_reg[7]), + .I2(com_cmmt_raddr[7]), + .LO(com_cmm_u_cmm_decoder_N_30_7) + ); + defparam com_cmm_u_cmm_decoder_un9_bar34_64_hit_high_0_I_5.INIT = 8'h6C; + LUT3_L com_cmm_u_cmm_decoder_un9_bar34_64_hit_high_0_I_5 ( + .I0(cfg_cfg_5072[165]), + .I1(com_cmm_bar3_reg[5]), + .I2(com_cmmt_raddr[5]), + .LO(com_cmm_u_cmm_decoder_N_110_5) + ); + defparam com_cmm_u_cmm_decoder_un9_bar23_64_hit_high_0_I_95.INIT = 8'h6C; + LUT3_L com_cmm_u_cmm_decoder_un9_bar23_64_hit_high_0_I_95 ( + .I0(cfg_cfg_5072[135]), + .I1(com_cmm_bar2_reg[7]), + .I2(com_cmmt_raddr[7]), + .LO(com_cmm_u_cmm_decoder_N_30_6) + ); + defparam com_cmm_u_cmm_decoder_un9_bar23_64_hit_high_0_I_5.INIT = 8'h6C; + LUT3_L com_cmm_u_cmm_decoder_un9_bar23_64_hit_high_0_I_5 ( + .I0(cfg_cfg_5072[133]), + .I1(com_cmm_bar2_reg[5]), + .I2(com_cmmt_raddr[5]), + .LO(com_cmm_u_cmm_decoder_N_110_4) + ); + defparam com_cmm_u_cmm_decoder_un9_bar12_64_hit_high_0_I_95.INIT = 8'h6C; + LUT3_L com_cmm_u_cmm_decoder_un9_bar12_64_hit_high_0_I_95 ( + .I0(cfg_cfg_5072[103]), + .I1(com_cmm_bar1_reg[7]), + .I2(com_cmmt_raddr[7]), + .LO(com_cmm_u_cmm_decoder_N_30_5) + ); + defparam com_cmm_u_cmm_decoder_un9_bar12_64_hit_high_0_I_5.INIT = 8'h6C; + LUT3_L com_cmm_u_cmm_decoder_un9_bar12_64_hit_high_0_I_5 ( + .I0(cfg_cfg_5072[101]), + .I1(com_cmm_bar1_reg[5]), + .I2(com_cmmt_raddr[5]), + .LO(com_cmm_u_cmm_decoder_N_110_3) + ); + defparam com_cmm_u_cmm_decoder_un10_bar01_64_hit_low_0_I_32.INIT = 8'h6C; + LUT3_L com_cmm_u_cmm_decoder_un10_bar01_64_hit_low_0_I_32 ( + .I0(cfg_cfg_5072[96]), + .I1(com_cmm_bar1_reg[0]), + .I2(com_cmmt_raddr[32]), + .LO(com_cmm_u_cmm_decoder_N_102_9) + ); + defparam com_cmm_u_cmm_decoder_un10_bar12_64_hit_low_0_I_32.INIT = 8'h6C; + LUT3_L com_cmm_u_cmm_decoder_un10_bar12_64_hit_low_0_I_32 ( + .I0(cfg_cfg_5072[128]), + .I1(com_cmm_bar2_reg[0]), + .I2(com_cmmt_raddr[32]), + .LO(com_cmm_u_cmm_decoder_N_102_10) + ); + defparam com_cmm_u_cmm_decoder_un10_bar23_64_hit_low_0_I_32.INIT = 8'h6C; + LUT3_L com_cmm_u_cmm_decoder_un10_bar23_64_hit_low_0_I_32 ( + .I0(cfg_cfg_5072[160]), + .I1(com_cmm_bar3_reg[0]), + .I2(com_cmmt_raddr[32]), + .LO(com_cmm_u_cmm_decoder_N_102_11) + ); + defparam com_cmm_u_cmm_decoder_un9_bar34_64_hit_high_0_I_122.INIT = 8'h6C; + LUT3_L com_cmm_u_cmm_decoder_un9_bar34_64_hit_high_0_I_122 ( + .I0(cfg_cfg_5072[169]), + .I1(com_cmm_bar3_reg[9]), + .I2(com_cmmt_raddr[9]), + .LO(com_cmm_u_cmm_decoder_N_6_8) + ); + defparam com_cmm_u_cmm_decoder_un9_bar34_64_hit_high_0_I_113.INIT = 8'h6C; + LUT3_L com_cmm_u_cmm_decoder_un9_bar34_64_hit_high_0_I_113 ( + .I0(cfg_cfg_5072[189]), + .I1(com_cmm_bar3_reg[29]), + .I2(com_cmmt_raddr[29]), + .LO(com_cmm_u_cmm_decoder_N_14_9) + ); + defparam com_cmm_u_cmm_decoder_un9_bar34_64_hit_high_0_I_104.INIT = 8'h6C; + LUT3_L com_cmm_u_cmm_decoder_un9_bar34_64_hit_high_0_I_104 ( + .I0(cfg_cfg_5072[187]), + .I1(com_cmm_bar3_reg[27]), + .I2(com_cmmt_raddr[27]), + .LO(com_cmm_u_cmm_decoder_N_22_8) + ); + defparam com_cmm_u_cmm_decoder_un9_bar34_64_hit_high_0_I_86.INIT = 8'h6C; + LUT3_L com_cmm_u_cmm_decoder_un9_bar34_64_hit_high_0_I_86 ( + .I0(cfg_cfg_5072[177]), + .I1(com_cmm_bar3_reg[17]), + .I2(com_cmmt_raddr[17]), + .LO(com_cmm_u_cmm_decoder_N_38_8) + ); + defparam com_cmm_u_cmm_decoder_un9_bar34_64_hit_high_0_I_77.INIT = 8'h6C; + LUT3_L com_cmm_u_cmm_decoder_un9_bar34_64_hit_high_0_I_77 ( + .I0(cfg_cfg_5072[181]), + .I1(com_cmm_bar3_reg[21]), + .I2(com_cmmt_raddr[21]), + .LO(com_cmm_u_cmm_decoder_N_46_8) + ); + defparam com_cmm_u_cmm_decoder_un9_bar34_64_hit_high_0_I_68.INIT = 8'h6C; + LUT3_L com_cmm_u_cmm_decoder_un9_bar34_64_hit_high_0_I_68 ( + .I0(cfg_cfg_5072[179]), + .I1(com_cmm_bar3_reg[19]), + .I2(com_cmmt_raddr[19]), + .LO(com_cmm_u_cmm_decoder_N_54_8) + ); + defparam com_cmm_u_cmm_decoder_un9_bar34_64_hit_high_0_I_59.INIT = 8'h6C; + LUT3_L com_cmm_u_cmm_decoder_un9_bar34_64_hit_high_0_I_59 ( + .I0(cfg_cfg_5072[175]), + .I1(com_cmm_bar3_reg[15]), + .I2(com_cmmt_raddr[15]), + .LO(com_cmm_u_cmm_decoder_N_62_8) + ); + defparam com_cmm_u_cmm_decoder_un9_bar34_64_hit_high_0_I_50.INIT = 8'h6C; + LUT3_L com_cmm_u_cmm_decoder_un9_bar34_64_hit_high_0_I_50 ( + .I0(cfg_cfg_5072[185]), + .I1(com_cmm_bar3_reg[25]), + .I2(com_cmmt_raddr[25]), + .LO(com_cmm_u_cmm_decoder_N_70_8) + ); + defparam com_cmm_u_cmm_decoder_un9_bar34_64_hit_high_0_I_41.INIT = 8'h6C; + LUT3_L com_cmm_u_cmm_decoder_un9_bar34_64_hit_high_0_I_41 ( + .I0(cfg_cfg_5072[173]), + .I1(com_cmm_bar3_reg[13]), + .I2(com_cmmt_raddr[13]), + .LO(com_cmm_u_cmm_decoder_N_78_8) + ); + defparam com_cmm_u_cmm_decoder_un9_bar34_64_hit_high_0_I_32.INIT = 8'h6C; + LUT3_L com_cmm_u_cmm_decoder_un9_bar34_64_hit_high_0_I_32 ( + .I0(cfg_cfg_5072[171]), + .I1(com_cmm_bar3_reg[11]), + .I2(com_cmmt_raddr[11]), + .LO(com_cmm_u_cmm_decoder_N_86_8) + ); + defparam com_cmm_u_cmm_decoder_un9_bar34_64_hit_high_0_I_23.INIT = 8'h6C; + LUT3_L com_cmm_u_cmm_decoder_un9_bar34_64_hit_high_0_I_23 ( + .I0(cfg_cfg_5072[183]), + .I1(com_cmm_bar3_reg[23]), + .I2(com_cmmt_raddr[23]), + .LO(com_cmm_u_cmm_decoder_N_94_8) + ); + defparam com_cmm_u_cmm_decoder_un9_bar34_64_hit_high_0_I_14.INIT = 8'h6C; + LUT3_L com_cmm_u_cmm_decoder_un9_bar34_64_hit_high_0_I_14 ( + .I0(cfg_cfg_5072[191]), + .I1(com_cmm_bar3_reg[31]), + .I2(com_cmmt_raddr[31]), + .LO(com_cmm_u_cmm_decoder_N_102_3) + ); + defparam com_cmm_u_cmm_decoder_un9_bar23_64_hit_high_0_I_122.INIT = 8'h6C; + LUT3_L com_cmm_u_cmm_decoder_un9_bar23_64_hit_high_0_I_122 ( + .I0(cfg_cfg_5072[137]), + .I1(com_cmm_bar2_reg[9]), + .I2(com_cmmt_raddr[9]), + .LO(com_cmm_u_cmm_decoder_N_6_7) + ); + defparam com_cmm_u_cmm_decoder_un9_bar23_64_hit_high_0_I_113.INIT = 8'h6C; + LUT3_L com_cmm_u_cmm_decoder_un9_bar23_64_hit_high_0_I_113 ( + .I0(cfg_cfg_5072[157]), + .I1(com_cmm_bar2_reg[29]), + .I2(com_cmmt_raddr[29]), + .LO(com_cmm_u_cmm_decoder_N_14_8) + ); + defparam com_cmm_u_cmm_decoder_un9_bar23_64_hit_high_0_I_104.INIT = 8'h6C; + LUT3_L com_cmm_u_cmm_decoder_un9_bar23_64_hit_high_0_I_104 ( + .I0(cfg_cfg_5072[155]), + .I1(com_cmm_bar2_reg[27]), + .I2(com_cmmt_raddr[27]), + .LO(com_cmm_u_cmm_decoder_N_22_7) + ); + defparam com_cmm_u_cmm_decoder_un9_bar23_64_hit_high_0_I_86.INIT = 8'h6C; + LUT3_L com_cmm_u_cmm_decoder_un9_bar23_64_hit_high_0_I_86 ( + .I0(cfg_cfg_5072[145]), + .I1(com_cmm_bar2_reg[17]), + .I2(com_cmmt_raddr[17]), + .LO(com_cmm_u_cmm_decoder_N_38_7) + ); + defparam com_cmm_u_cmm_decoder_un9_bar23_64_hit_high_0_I_77.INIT = 8'h6C; + LUT3_L com_cmm_u_cmm_decoder_un9_bar23_64_hit_high_0_I_77 ( + .I0(cfg_cfg_5072[149]), + .I1(com_cmm_bar2_reg[21]), + .I2(com_cmmt_raddr[21]), + .LO(com_cmm_u_cmm_decoder_N_46_7) + ); + defparam com_cmm_u_cmm_decoder_un9_bar23_64_hit_high_0_I_68.INIT = 8'h6C; + LUT3_L com_cmm_u_cmm_decoder_un9_bar23_64_hit_high_0_I_68 ( + .I0(cfg_cfg_5072[147]), + .I1(com_cmm_bar2_reg[19]), + .I2(com_cmmt_raddr[19]), + .LO(com_cmm_u_cmm_decoder_N_54_7) + ); + defparam com_cmm_u_cmm_decoder_un9_bar23_64_hit_high_0_I_59.INIT = 8'h6C; + LUT3_L com_cmm_u_cmm_decoder_un9_bar23_64_hit_high_0_I_59 ( + .I0(cfg_cfg_5072[143]), + .I1(com_cmm_bar2_reg[15]), + .I2(com_cmmt_raddr[15]), + .LO(com_cmm_u_cmm_decoder_N_62_7) + ); + defparam com_cmm_u_cmm_decoder_un9_bar23_64_hit_high_0_I_50.INIT = 8'h6C; + LUT3_L com_cmm_u_cmm_decoder_un9_bar23_64_hit_high_0_I_50 ( + .I0(cfg_cfg_5072[153]), + .I1(com_cmm_bar2_reg[25]), + .I2(com_cmmt_raddr[25]), + .LO(com_cmm_u_cmm_decoder_N_70_7) + ); + defparam com_cmm_u_cmm_decoder_un9_bar23_64_hit_high_0_I_41.INIT = 8'h6C; + LUT3_L com_cmm_u_cmm_decoder_un9_bar23_64_hit_high_0_I_41 ( + .I0(cfg_cfg_5072[141]), + .I1(com_cmm_bar2_reg[13]), + .I2(com_cmmt_raddr[13]), + .LO(com_cmm_u_cmm_decoder_N_78_7) + ); + defparam com_cmm_u_cmm_decoder_un9_bar23_64_hit_high_0_I_32.INIT = 8'h6C; + LUT3_L com_cmm_u_cmm_decoder_un9_bar23_64_hit_high_0_I_32 ( + .I0(cfg_cfg_5072[139]), + .I1(com_cmm_bar2_reg[11]), + .I2(com_cmmt_raddr[11]), + .LO(com_cmm_u_cmm_decoder_N_86_7) + ); + defparam com_cmm_u_cmm_decoder_un9_bar23_64_hit_high_0_I_23.INIT = 8'h6C; + LUT3_L com_cmm_u_cmm_decoder_un9_bar23_64_hit_high_0_I_23 ( + .I0(cfg_cfg_5072[151]), + .I1(com_cmm_bar2_reg[23]), + .I2(com_cmmt_raddr[23]), + .LO(com_cmm_u_cmm_decoder_N_94_7) + ); + defparam com_cmm_u_cmm_decoder_un9_bar23_64_hit_high_0_I_14.INIT = 8'h6C; + LUT3_L com_cmm_u_cmm_decoder_un9_bar23_64_hit_high_0_I_14 ( + .I0(cfg_cfg_5072[159]), + .I1(com_cmm_bar2_reg[31]), + .I2(com_cmmt_raddr[31]), + .LO(com_cmm_u_cmm_decoder_N_102_4) + ); + defparam com_cmm_u_cmm_decoder_un9_bar12_64_hit_high_0_I_122.INIT = 8'h6C; + LUT3_L com_cmm_u_cmm_decoder_un9_bar12_64_hit_high_0_I_122 ( + .I0(cfg_cfg_5072[105]), + .I1(com_cmm_bar1_reg[9]), + .I2(com_cmmt_raddr[9]), + .LO(com_cmm_u_cmm_decoder_N_6_6) + ); + defparam com_cmm_u_cmm_decoder_un9_bar12_64_hit_high_0_I_113.INIT = 8'h6C; + LUT3_L com_cmm_u_cmm_decoder_un9_bar12_64_hit_high_0_I_113 ( + .I0(cfg_cfg_5072[125]), + .I1(com_cmm_bar1_reg[29]), + .I2(com_cmmt_raddr[29]), + .LO(com_cmm_u_cmm_decoder_N_14_7) + ); + defparam com_cmm_u_cmm_decoder_un9_bar12_64_hit_high_0_I_104.INIT = 8'h6C; + LUT3_L com_cmm_u_cmm_decoder_un9_bar12_64_hit_high_0_I_104 ( + .I0(cfg_cfg_5072[123]), + .I1(com_cmm_bar1_reg[27]), + .I2(com_cmmt_raddr[27]), + .LO(com_cmm_u_cmm_decoder_N_22_6) + ); + defparam com_cmm_u_cmm_decoder_un9_bar12_64_hit_high_0_I_86.INIT = 8'h6C; + LUT3_L com_cmm_u_cmm_decoder_un9_bar12_64_hit_high_0_I_86 ( + .I0(cfg_cfg_5072[113]), + .I1(com_cmm_bar1_reg[17]), + .I2(com_cmmt_raddr[17]), + .LO(com_cmm_u_cmm_decoder_N_38_6) + ); + defparam com_cmm_u_cmm_decoder_un9_bar12_64_hit_high_0_I_77.INIT = 8'h6C; + LUT3_L com_cmm_u_cmm_decoder_un9_bar12_64_hit_high_0_I_77 ( + .I0(cfg_cfg_5072[117]), + .I1(com_cmm_bar1_reg[21]), + .I2(com_cmmt_raddr[21]), + .LO(com_cmm_u_cmm_decoder_N_46_6) + ); + defparam com_cmm_u_cmm_decoder_un9_bar12_64_hit_high_0_I_68.INIT = 8'h6C; + LUT3_L com_cmm_u_cmm_decoder_un9_bar12_64_hit_high_0_I_68 ( + .I0(cfg_cfg_5072[115]), + .I1(com_cmm_bar1_reg[19]), + .I2(com_cmmt_raddr[19]), + .LO(com_cmm_u_cmm_decoder_N_54_6) + ); + defparam com_cmm_u_cmm_decoder_un9_bar12_64_hit_high_0_I_59.INIT = 8'h6C; + LUT3_L com_cmm_u_cmm_decoder_un9_bar12_64_hit_high_0_I_59 ( + .I0(cfg_cfg_5072[111]), + .I1(com_cmm_bar1_reg[15]), + .I2(com_cmmt_raddr[15]), + .LO(com_cmm_u_cmm_decoder_N_62_6) + ); + defparam com_cmm_u_cmm_decoder_un9_bar12_64_hit_high_0_I_50.INIT = 8'h6C; + LUT3_L com_cmm_u_cmm_decoder_un9_bar12_64_hit_high_0_I_50 ( + .I0(cfg_cfg_5072[121]), + .I1(com_cmm_bar1_reg[25]), + .I2(com_cmmt_raddr[25]), + .LO(com_cmm_u_cmm_decoder_N_70_6) + ); + defparam com_cmm_u_cmm_decoder_un9_bar12_64_hit_high_0_I_41.INIT = 8'h6C; + LUT3_L com_cmm_u_cmm_decoder_un9_bar12_64_hit_high_0_I_41 ( + .I0(cfg_cfg_5072[109]), + .I1(com_cmm_bar1_reg[13]), + .I2(com_cmmt_raddr[13]), + .LO(com_cmm_u_cmm_decoder_N_78_6) + ); + defparam com_cmm_u_cmm_decoder_un9_bar12_64_hit_high_0_I_32.INIT = 8'h6C; + LUT3_L com_cmm_u_cmm_decoder_un9_bar12_64_hit_high_0_I_32 ( + .I0(cfg_cfg_5072[107]), + .I1(com_cmm_bar1_reg[11]), + .I2(com_cmmt_raddr[11]), + .LO(com_cmm_u_cmm_decoder_N_86_6) + ); + defparam com_cmm_u_cmm_decoder_un9_bar12_64_hit_high_0_I_23.INIT = 8'h6C; + LUT3_L com_cmm_u_cmm_decoder_un9_bar12_64_hit_high_0_I_23 ( + .I0(cfg_cfg_5072[119]), + .I1(com_cmm_bar1_reg[23]), + .I2(com_cmmt_raddr[23]), + .LO(com_cmm_u_cmm_decoder_N_94_6) + ); + defparam com_cmm_u_cmm_decoder_un9_bar12_64_hit_high_0_I_14.INIT = 8'h6C; + LUT3_L com_cmm_u_cmm_decoder_un9_bar12_64_hit_high_0_I_14 ( + .I0(cfg_cfg_5072[127]), + .I1(com_cmm_bar1_reg[31]), + .I2(com_cmmt_raddr[31]), + .LO(com_cmm_u_cmm_decoder_N_102_5) + ); + defparam com_cmm_u_cmm_decoder_un9_bar01_64_hit_high_0_I_122.INIT = 8'h6C; + LUT3_L com_cmm_u_cmm_decoder_un9_bar01_64_hit_high_0_I_122 ( + .I0(cfg_cfg_5072[73]), + .I1(com_cmm_bar0_reg_9_), + .I2(com_cmmt_raddr[9]), + .LO(com_cmm_u_cmm_decoder_N_6_5) + ); + defparam com_cmm_u_cmm_decoder_un9_bar01_64_hit_high_0_I_113.INIT = 8'h6C; + LUT3_L com_cmm_u_cmm_decoder_un9_bar01_64_hit_high_0_I_113 ( + .I0(cfg_cfg_5072[93]), + .I1(com_cmm_bar0_reg_29_), + .I2(com_cmmt_raddr[29]), + .LO(com_cmm_u_cmm_decoder_N_14_6) + ); + defparam com_cmm_u_cmm_decoder_un9_bar01_64_hit_high_0_I_104.INIT = 8'h6C; + LUT3_L com_cmm_u_cmm_decoder_un9_bar01_64_hit_high_0_I_104 ( + .I0(cfg_cfg_5072[91]), + .I1(com_cmm_bar0_reg_27_), + .I2(com_cmmt_raddr[27]), + .LO(com_cmm_u_cmm_decoder_N_22_5) + ); + defparam com_cmm_u_cmm_decoder_un9_bar01_64_hit_high_0_I_95.INIT = 8'h6C; + LUT3_L com_cmm_u_cmm_decoder_un9_bar01_64_hit_high_0_I_95 ( + .I0(cfg_cfg_5072[71]), + .I1(com_cmm_bar0_reg_7_), + .I2(com_cmmt_raddr[7]), + .LO(com_cmm_u_cmm_decoder_N_30_4) + ); + defparam com_cmm_u_cmm_decoder_un9_bar01_64_hit_high_0_I_86.INIT = 8'h6C; + LUT3_L com_cmm_u_cmm_decoder_un9_bar01_64_hit_high_0_I_86 ( + .I0(cfg_cfg_5072[81]), + .I1(com_cmm_bar0_reg_17_), + .I2(com_cmmt_raddr[17]), + .LO(com_cmm_u_cmm_decoder_N_38_5) + ); + defparam com_cmm_u_cmm_decoder_un9_bar01_64_hit_high_0_I_77.INIT = 8'h6C; + LUT3_L com_cmm_u_cmm_decoder_un9_bar01_64_hit_high_0_I_77 ( + .I0(cfg_cfg_5072[85]), + .I1(com_cmm_bar0_reg_21_), + .I2(com_cmmt_raddr[21]), + .LO(com_cmm_u_cmm_decoder_N_46_5) + ); + defparam com_cmm_u_cmm_decoder_un9_bar01_64_hit_high_0_I_68.INIT = 8'h6C; + LUT3_L com_cmm_u_cmm_decoder_un9_bar01_64_hit_high_0_I_68 ( + .I0(cfg_cfg_5072[83]), + .I1(com_cmm_bar0_reg_19_), + .I2(com_cmmt_raddr[19]), + .LO(com_cmm_u_cmm_decoder_N_54_5) + ); + defparam com_cmm_u_cmm_decoder_un9_bar01_64_hit_high_0_I_59.INIT = 8'h6C; + LUT3_L com_cmm_u_cmm_decoder_un9_bar01_64_hit_high_0_I_59 ( + .I0(cfg_cfg_5072[79]), + .I1(com_cmm_bar0_reg_15_), + .I2(com_cmmt_raddr[15]), + .LO(com_cmm_u_cmm_decoder_N_62_5) + ); + defparam com_cmm_u_cmm_decoder_un9_bar01_64_hit_high_0_I_50.INIT = 8'h6C; + LUT3_L com_cmm_u_cmm_decoder_un9_bar01_64_hit_high_0_I_50 ( + .I0(cfg_cfg_5072[89]), + .I1(com_cmm_bar0_reg_25_), + .I2(com_cmmt_raddr[25]), + .LO(com_cmm_u_cmm_decoder_N_70_5) + ); + defparam com_cmm_u_cmm_decoder_un9_bar01_64_hit_high_0_I_41.INIT = 8'h6C; + LUT3_L com_cmm_u_cmm_decoder_un9_bar01_64_hit_high_0_I_41 ( + .I0(cfg_cfg_5072[77]), + .I1(com_cmm_bar0_reg_13_), + .I2(com_cmmt_raddr[13]), + .LO(com_cmm_u_cmm_decoder_N_78_5) + ); + defparam com_cmm_u_cmm_decoder_un9_bar01_64_hit_high_0_I_32.INIT = 8'h6C; + LUT3_L com_cmm_u_cmm_decoder_un9_bar01_64_hit_high_0_I_32 ( + .I0(cfg_cfg_5072[75]), + .I1(com_cmm_bar0_reg_11_), + .I2(com_cmmt_raddr[11]), + .LO(com_cmm_u_cmm_decoder_N_86_5) + ); + defparam com_cmm_u_cmm_decoder_un9_bar01_64_hit_high_0_I_23.INIT = 8'h6C; + LUT3_L com_cmm_u_cmm_decoder_un9_bar01_64_hit_high_0_I_23 ( + .I0(cfg_cfg_5072[87]), + .I1(com_cmm_bar0_reg_23_), + .I2(com_cmmt_raddr[23]), + .LO(com_cmm_u_cmm_decoder_N_94_5) + ); + defparam com_cmm_u_cmm_decoder_un9_bar01_64_hit_high_0_I_14.INIT = 8'h6C; + LUT3_L com_cmm_u_cmm_decoder_un9_bar01_64_hit_high_0_I_14 ( + .I0(cfg_cfg_5072[95]), + .I1(com_cmm_bar0_reg_31_), + .I2(com_cmmt_raddr[31]), + .LO(com_cmm_u_cmm_decoder_N_102_6) + ); + defparam com_cmm_u_cmm_decoder_un9_bar01_64_hit_high_0_I_5.INIT = 8'h6C; + LUT3_L com_cmm_u_cmm_decoder_un9_bar01_64_hit_high_0_I_5 ( + .I0(cfg_cfg_5072[69]), + .I1(com_cmm_bar0_reg_5_), + .I2(com_cmmt_raddr[5]), + .LO(com_cmm_u_cmm_decoder_N_110_2) + ); + defparam com_cmm_u_cmm_decoder_bar6_eq_raddr_3_0_I_86.INIT = 8'h6C; + LUT3_L com_cmm_u_cmm_decoder_bar6_eq_raddr_3_0_I_86 ( + .I0(cfg_cfg_5072[340]), + .I1(com_cmm_xrom_reg_20_), + .I2(com_cmmt_raddr[52]), + .LO(com_cmm_u_cmm_decoder_N_12) + ); + defparam com_cmm_u_cmm_decoder_bar6_eq_raddr_3_0_I_77.INIT = 8'h6C; + LUT3_L com_cmm_u_cmm_decoder_bar6_eq_raddr_3_0_I_77 ( + .I0(cfg_cfg_5072[334]), + .I1(com_cmm_xrom_reg_14_), + .I2(com_cmmt_raddr[46]), + .LO(com_cmm_u_cmm_decoder_N_20) + ); + defparam com_cmm_u_cmm_decoder_bar6_eq_raddr_3_0_I_68.INIT = 8'h6C; + LUT3_L com_cmm_u_cmm_decoder_bar6_eq_raddr_3_0_I_68 ( + .I0(cfg_cfg_5072[346]), + .I1(com_cmm_xrom_reg_26_), + .I2(com_cmmt_raddr[58]), + .LO(com_cmm_u_cmm_decoder_N_28) + ); + defparam com_cmm_u_cmm_decoder_bar6_eq_raddr_3_0_I_59.INIT = 8'h6C; + LUT3_L com_cmm_u_cmm_decoder_bar6_eq_raddr_3_0_I_59 ( + .I0(cfg_cfg_5072[344]), + .I1(com_cmm_xrom_reg_24_), + .I2(com_cmmt_raddr[56]), + .LO(com_cmm_u_cmm_decoder_N_36) + ); + defparam com_cmm_u_cmm_decoder_bar6_eq_raddr_3_0_I_50.INIT = 8'h6C; + LUT3_L com_cmm_u_cmm_decoder_bar6_eq_raddr_3_0_I_50 ( + .I0(cfg_cfg_5072[348]), + .I1(com_cmm_xrom_reg_28_), + .I2(com_cmmt_raddr[60]), + .LO(com_cmm_u_cmm_decoder_N_44) + ); + defparam com_cmm_u_cmm_decoder_bar6_eq_raddr_3_0_I_41.INIT = 8'h6C; + LUT3_L com_cmm_u_cmm_decoder_bar6_eq_raddr_3_0_I_41 ( + .I0(cfg_cfg_5072[342]), + .I1(com_cmm_xrom_reg_22_), + .I2(com_cmmt_raddr[54]), + .LO(com_cmm_u_cmm_decoder_N_52) + ); + defparam com_cmm_u_cmm_decoder_bar6_eq_raddr_3_0_I_32.INIT = 8'h6C; + LUT3_L com_cmm_u_cmm_decoder_bar6_eq_raddr_3_0_I_32 ( + .I0(cfg_cfg_5072[338]), + .I1(com_cmm_xrom_reg_18_), + .I2(com_cmmt_raddr[50]), + .LO(com_cmm_u_cmm_decoder_N_60) + ); + defparam com_cmm_u_cmm_decoder_bar6_eq_raddr_3_0_I_23.INIT = 8'h6C; + LUT3_L com_cmm_u_cmm_decoder_bar6_eq_raddr_3_0_I_23 ( + .I0(cfg_cfg_5072[336]), + .I1(com_cmm_xrom_reg_16_), + .I2(com_cmmt_raddr[48]), + .LO(com_cmm_u_cmm_decoder_N_68) + ); + defparam com_cmm_u_cmm_decoder_bar6_eq_raddr_3_0_I_14.INIT = 8'h6C; + LUT3_L com_cmm_u_cmm_decoder_bar6_eq_raddr_3_0_I_14 ( + .I0(cfg_cfg_5072[350]), + .I1(com_cmm_xrom_reg_30_), + .I2(com_cmmt_raddr[62]), + .LO(com_cmm_u_cmm_decoder_N_76) + ); + defparam com_cmm_u_cmm_decoder_bar6_eq_raddr_3_0_I_5.INIT = 8'h6C; + LUT3_L com_cmm_u_cmm_decoder_bar6_eq_raddr_3_0_I_5 ( + .I0(cfg_cfg_5072[332]), + .I1(com_cmm_xrom_reg_12_), + .I2(com_cmmt_raddr[44]), + .LO(com_cmm_u_cmm_decoder_N_84) + ); + defparam com_cmm_u_cmm_decoder_bar5_eq_raddr_3_0_I_122.INIT = 8'h6C; + LUT3_L com_cmm_u_cmm_decoder_bar5_eq_raddr_3_0_I_122 ( + .I0(cfg_cfg_5072[233]), + .I1(com_cmm_bar5_reg[9]), + .I2(com_cmmt_raddr[41]), + .LO(com_cmm_u_cmm_decoder_N_6_9) + ); + defparam com_cmm_u_cmm_decoder_bar5_eq_raddr_3_0_I_113.INIT = 8'h6C; + LUT3_L com_cmm_u_cmm_decoder_bar5_eq_raddr_3_0_I_113 ( + .I0(cfg_cfg_5072[253]), + .I1(com_cmm_bar5_reg[29]), + .I2(com_cmmt_raddr[61]), + .LO(com_cmm_u_cmm_decoder_N_14_10) + ); + defparam com_cmm_u_cmm_decoder_bar5_eq_raddr_3_0_I_104.INIT = 8'h6C; + LUT3_L com_cmm_u_cmm_decoder_bar5_eq_raddr_3_0_I_104 ( + .I0(cfg_cfg_5072[251]), + .I1(com_cmm_bar5_reg[27]), + .I2(com_cmmt_raddr[59]), + .LO(com_cmm_u_cmm_decoder_N_22_9) + ); + defparam com_cmm_u_cmm_decoder_bar5_eq_raddr_3_0_I_95.INIT = 8'h6C; + LUT3_L com_cmm_u_cmm_decoder_bar5_eq_raddr_3_0_I_95 ( + .I0(cfg_cfg_5072[231]), + .I1(com_cmm_bar5_reg[7]), + .I2(com_cmmt_raddr[39]), + .LO(com_cmm_u_cmm_decoder_N_30_8) + ); + defparam com_cmm_u_cmm_decoder_bar5_eq_raddr_3_0_I_86.INIT = 8'h6C; + LUT3_L com_cmm_u_cmm_decoder_bar5_eq_raddr_3_0_I_86 ( + .I0(cfg_cfg_5072[241]), + .I1(com_cmm_bar5_reg[17]), + .I2(com_cmmt_raddr[49]), + .LO(com_cmm_u_cmm_decoder_N_38_9) + ); + defparam com_cmm_u_cmm_decoder_bar5_eq_raddr_3_0_I_77.INIT = 8'h6C; + LUT3_L com_cmm_u_cmm_decoder_bar5_eq_raddr_3_0_I_77 ( + .I0(cfg_cfg_5072[245]), + .I1(com_cmm_bar5_reg[21]), + .I2(com_cmmt_raddr[53]), + .LO(com_cmm_u_cmm_decoder_N_46_9) + ); + defparam com_cmm_u_cmm_decoder_bar5_eq_raddr_3_0_I_68.INIT = 8'h6C; + LUT3_L com_cmm_u_cmm_decoder_bar5_eq_raddr_3_0_I_68 ( + .I0(cfg_cfg_5072[243]), + .I1(com_cmm_bar5_reg[19]), + .I2(com_cmmt_raddr[51]), + .LO(com_cmm_u_cmm_decoder_N_54_9) + ); + defparam com_cmm_u_cmm_decoder_bar5_eq_raddr_3_0_I_59.INIT = 8'h6C; + LUT3_L com_cmm_u_cmm_decoder_bar5_eq_raddr_3_0_I_59 ( + .I0(cfg_cfg_5072[239]), + .I1(com_cmm_bar5_reg[15]), + .I2(com_cmmt_raddr[47]), + .LO(com_cmm_u_cmm_decoder_N_62_9) + ); + defparam com_cmm_u_cmm_decoder_bar5_eq_raddr_3_0_I_50.INIT = 8'h6C; + LUT3_L com_cmm_u_cmm_decoder_bar5_eq_raddr_3_0_I_50 ( + .I0(cfg_cfg_5072[249]), + .I1(com_cmm_bar5_reg[25]), + .I2(com_cmmt_raddr[57]), + .LO(com_cmm_u_cmm_decoder_N_70_9) + ); + defparam com_cmm_u_cmm_decoder_bar5_eq_raddr_3_0_I_41.INIT = 8'h6C; + LUT3_L com_cmm_u_cmm_decoder_bar5_eq_raddr_3_0_I_41 ( + .I0(cfg_cfg_5072[237]), + .I1(com_cmm_bar5_reg[13]), + .I2(com_cmmt_raddr[45]), + .LO(com_cmm_u_cmm_decoder_N_78_9) + ); + defparam com_cmm_u_cmm_decoder_bar5_eq_raddr_3_0_I_32.INIT = 8'h6C; + LUT3_L com_cmm_u_cmm_decoder_bar5_eq_raddr_3_0_I_32 ( + .I0(cfg_cfg_5072[235]), + .I1(com_cmm_bar5_reg[11]), + .I2(com_cmmt_raddr[43]), + .LO(com_cmm_u_cmm_decoder_N_86_9) + ); + defparam com_cmm_u_cmm_decoder_bar5_eq_raddr_3_0_I_23.INIT = 8'h6C; + LUT3_L com_cmm_u_cmm_decoder_bar5_eq_raddr_3_0_I_23 ( + .I0(cfg_cfg_5072[247]), + .I1(com_cmm_bar5_reg[23]), + .I2(com_cmmt_raddr[55]), + .LO(com_cmm_u_cmm_decoder_N_94_9) + ); + defparam com_cmm_u_cmm_decoder_bar5_eq_raddr_3_0_I_14.INIT = 8'h6C; + LUT3_L com_cmm_u_cmm_decoder_bar5_eq_raddr_3_0_I_14 ( + .I0(cfg_cfg_5072[255]), + .I1(com_cmm_bar5_reg[31]), + .I2(com_cmmt_raddr[63]), + .LO(com_cmm_u_cmm_decoder_N_102_14) + ); + defparam com_cmm_u_cmm_decoder_bar5_eq_raddr_3_0_I_5.INIT = 8'h6C; + LUT3_L com_cmm_u_cmm_decoder_bar5_eq_raddr_3_0_I_5 ( + .I0(cfg_cfg_5072[229]), + .I1(com_cmm_bar5_reg[5]), + .I2(com_cmmt_raddr[37]), + .LO(com_cmm_u_cmm_decoder_N_110_6) + ); + defparam com_cmm_u_cmm_decoder_bar4_eq_raddr_3_0_I_123.INIT = 8'h6C; + LUT3 com_cmm_u_cmm_decoder_bar4_eq_raddr_3_0_I_123 ( + .I0(cfg_cfg_5072[200]), + .I1(com_cmm_bar4_reg[8]), + .I2(com_cmmt_raddr[40]), + .O(com_cmm_u_cmm_decoder_N_7) + ); + defparam com_cmm_u_cmm_decoder_bar4_eq_raddr_3_0_I_122.INIT = 8'h6C; + LUT3 com_cmm_u_cmm_decoder_bar4_eq_raddr_3_0_I_122 ( + .I0(cfg_cfg_5072[201]), + .I1(com_cmm_bar4_reg[9]), + .I2(com_cmmt_raddr[41]), + .O(com_cmm_u_cmm_decoder_N_6) + ); + defparam com_cmm_u_cmm_decoder_bar4_eq_raddr_3_0_I_114.INIT = 8'h6C; + LUT3 com_cmm_u_cmm_decoder_bar4_eq_raddr_3_0_I_114 ( + .I0(cfg_cfg_5072[220]), + .I1(com_cmm_bar4_reg[28]), + .I2(com_cmmt_raddr[60]), + .O(com_cmm_u_cmm_decoder_N_15) + ); + defparam com_cmm_u_cmm_decoder_bar4_eq_raddr_3_0_I_113.INIT = 8'h6C; + LUT3 com_cmm_u_cmm_decoder_bar4_eq_raddr_3_0_I_113 ( + .I0(cfg_cfg_5072[221]), + .I1(com_cmm_bar4_reg[29]), + .I2(com_cmmt_raddr[61]), + .O(com_cmm_u_cmm_decoder_N_14_0) + ); + defparam com_cmm_u_cmm_decoder_bar4_eq_raddr_3_0_I_105.INIT = 8'h6C; + LUT3 com_cmm_u_cmm_decoder_bar4_eq_raddr_3_0_I_105 ( + .I0(cfg_cfg_5072[218]), + .I1(com_cmm_bar4_reg[26]), + .I2(com_cmmt_raddr[58]), + .O(com_cmm_u_cmm_decoder_N_23) + ); + defparam com_cmm_u_cmm_decoder_bar4_eq_raddr_3_0_I_104.INIT = 8'h6C; + LUT3 com_cmm_u_cmm_decoder_bar4_eq_raddr_3_0_I_104 ( + .I0(cfg_cfg_5072[219]), + .I1(com_cmm_bar4_reg[27]), + .I2(com_cmmt_raddr[59]), + .O(com_cmm_u_cmm_decoder_N_22) + ); + defparam com_cmm_u_cmm_decoder_bar4_eq_raddr_3_0_I_96.INIT = 8'h6C; + LUT3 com_cmm_u_cmm_decoder_bar4_eq_raddr_3_0_I_96 ( + .I0(cfg_cfg_5072[198]), + .I1(com_cmm_bar4_reg[6]), + .I2(com_cmmt_raddr[38]), + .O(com_cmm_u_cmm_decoder_N_31) + ); + defparam com_cmm_u_cmm_decoder_bar4_eq_raddr_3_0_I_95.INIT = 8'h6C; + LUT3 com_cmm_u_cmm_decoder_bar4_eq_raddr_3_0_I_95 ( + .I0(cfg_cfg_5072[199]), + .I1(com_cmm_bar4_reg[7]), + .I2(com_cmmt_raddr[39]), + .O(com_cmm_u_cmm_decoder_N_30) + ); + defparam com_cmm_u_cmm_decoder_bar4_eq_raddr_3_0_I_86.INIT = 8'h6C; + LUT3 com_cmm_u_cmm_decoder_bar4_eq_raddr_3_0_I_86 ( + .I0(cfg_cfg_5072[209]), + .I1(com_cmm_bar4_reg[17]), + .I2(com_cmmt_raddr[49]), + .O(com_cmm_u_cmm_decoder_N_38) + ); + defparam com_cmm_u_cmm_decoder_bar4_eq_raddr_3_0_I_78.INIT = 8'h6C; + LUT3 com_cmm_u_cmm_decoder_bar4_eq_raddr_3_0_I_78 ( + .I0(cfg_cfg_5072[212]), + .I1(com_cmm_bar4_reg[20]), + .I2(com_cmmt_raddr[52]), + .O(com_cmm_u_cmm_decoder_N_47) + ); + defparam com_cmm_u_cmm_decoder_bar4_eq_raddr_3_0_I_77.INIT = 8'h6C; + LUT3 com_cmm_u_cmm_decoder_bar4_eq_raddr_3_0_I_77 ( + .I0(cfg_cfg_5072[213]), + .I1(com_cmm_bar4_reg[21]), + .I2(com_cmmt_raddr[53]), + .O(com_cmm_u_cmm_decoder_N_46) + ); + defparam com_cmm_u_cmm_decoder_bar4_eq_raddr_3_0_I_68.INIT = 8'h6C; + LUT3 com_cmm_u_cmm_decoder_bar4_eq_raddr_3_0_I_68 ( + .I0(cfg_cfg_5072[211]), + .I1(com_cmm_bar4_reg[19]), + .I2(com_cmmt_raddr[51]), + .O(com_cmm_u_cmm_decoder_N_54) + ); + defparam com_cmm_u_cmm_decoder_bar4_eq_raddr_3_0_I_60.INIT = 8'h6C; + LUT3 com_cmm_u_cmm_decoder_bar4_eq_raddr_3_0_I_60 ( + .I0(cfg_cfg_5072[206]), + .I1(com_cmm_bar4_reg[14]), + .I2(com_cmmt_raddr[46]), + .O(com_cmm_u_cmm_decoder_N_63) + ); + defparam com_cmm_u_cmm_decoder_bar4_eq_raddr_3_0_I_59.INIT = 8'h6C; + LUT3 com_cmm_u_cmm_decoder_bar4_eq_raddr_3_0_I_59 ( + .I0(cfg_cfg_5072[207]), + .I1(com_cmm_bar4_reg[15]), + .I2(com_cmmt_raddr[47]), + .O(com_cmm_u_cmm_decoder_N_62) + ); + defparam com_cmm_u_cmm_decoder_bar4_eq_raddr_3_0_I_51.INIT = 8'h6C; + LUT3 com_cmm_u_cmm_decoder_bar4_eq_raddr_3_0_I_51 ( + .I0(cfg_cfg_5072[216]), + .I1(com_cmm_bar4_reg[24]), + .I2(com_cmmt_raddr[56]), + .O(com_cmm_u_cmm_decoder_N_71) + ); + defparam com_cmm_u_cmm_decoder_bar4_eq_raddr_3_0_I_50.INIT = 8'h6C; + LUT3 com_cmm_u_cmm_decoder_bar4_eq_raddr_3_0_I_50 ( + .I0(cfg_cfg_5072[217]), + .I1(com_cmm_bar4_reg[25]), + .I2(com_cmmt_raddr[57]), + .O(com_cmm_u_cmm_decoder_N_70) + ); + defparam com_cmm_u_cmm_decoder_bar4_eq_raddr_3_0_I_32.INIT = 8'h6C; + LUT3 com_cmm_u_cmm_decoder_bar4_eq_raddr_3_0_I_32 ( + .I0(cfg_cfg_5072[203]), + .I1(com_cmm_bar4_reg[11]), + .I2(com_cmmt_raddr[43]), + .O(com_cmm_u_cmm_decoder_N_86) + ); + defparam com_cmm_u_cmm_decoder_bar4_eq_raddr_3_0_I_23.INIT = 8'h6C; + LUT3 com_cmm_u_cmm_decoder_bar4_eq_raddr_3_0_I_23 ( + .I0(cfg_cfg_5072[215]), + .I1(com_cmm_bar4_reg[23]), + .I2(com_cmmt_raddr[55]), + .O(com_cmm_u_cmm_decoder_N_94) + ); + defparam com_cmm_u_cmm_decoder_bar4_eq_raddr_3_0_I_14.INIT = 8'h6C; + LUT3 com_cmm_u_cmm_decoder_bar4_eq_raddr_3_0_I_14 ( + .I0(cfg_cfg_5072[223]), + .I1(com_cmm_bar4_reg[31]), + .I2(com_cmmt_raddr[63]), + .O(com_cmm_u_cmm_decoder_N_102) + ); + defparam com_cmm_u_cmm_decoder_bar4_eq_raddr_3_0_I_6.INIT = 8'h6C; + LUT3 com_cmm_u_cmm_decoder_bar4_eq_raddr_3_0_I_6 ( + .I0(cfg_cfg_5072[196]), + .I1(com_cmm_bar4_reg[4]), + .I2(com_cmmt_raddr[36]), + .O(com_cmm_u_cmm_decoder_N_111) + ); + defparam com_cmm_u_cmm_decoder_bar3_eq_raddr_3_0_I_122.INIT = 8'h6C; + LUT3 com_cmm_u_cmm_decoder_bar3_eq_raddr_3_0_I_122 ( + .I0(cfg_cfg_5072[169]), + .I1(com_cmm_bar3_reg[9]), + .I2(com_cmmt_raddr[41]), + .O(com_cmm_u_cmm_decoder_N_6_0) + ); + defparam com_cmm_u_cmm_decoder_bar3_eq_raddr_3_0_I_114.INIT = 8'h6C; + LUT3 com_cmm_u_cmm_decoder_bar3_eq_raddr_3_0_I_114 ( + .I0(cfg_cfg_5072[188]), + .I1(com_cmm_bar3_reg[28]), + .I2(com_cmmt_raddr[60]), + .O(com_cmm_u_cmm_decoder_N_15_0) + ); + defparam com_cmm_u_cmm_decoder_bar3_eq_raddr_3_0_I_113.INIT = 8'h6C; + LUT3 com_cmm_u_cmm_decoder_bar3_eq_raddr_3_0_I_113 ( + .I0(cfg_cfg_5072[189]), + .I1(com_cmm_bar3_reg[29]), + .I2(com_cmmt_raddr[61]), + .O(com_cmm_u_cmm_decoder_N_14_1) + ); + defparam com_cmm_u_cmm_decoder_bar3_eq_raddr_3_0_I_104.INIT = 8'h6C; + LUT3 com_cmm_u_cmm_decoder_bar3_eq_raddr_3_0_I_104 ( + .I0(cfg_cfg_5072[187]), + .I1(com_cmm_bar3_reg[27]), + .I2(com_cmmt_raddr[59]), + .O(com_cmm_u_cmm_decoder_N_22_0) + ); + defparam com_cmm_u_cmm_decoder_bar3_eq_raddr_3_0_I_95.INIT = 8'h6C; + LUT3 com_cmm_u_cmm_decoder_bar3_eq_raddr_3_0_I_95 ( + .I0(cfg_cfg_5072[167]), + .I1(com_cmm_bar3_reg[7]), + .I2(com_cmmt_raddr[39]), + .O(com_cmm_u_cmm_decoder_N_30_0) + ); + defparam com_cmm_u_cmm_decoder_bar3_eq_raddr_3_0_I_86.INIT = 8'h6C; + LUT3 com_cmm_u_cmm_decoder_bar3_eq_raddr_3_0_I_86 ( + .I0(cfg_cfg_5072[177]), + .I1(com_cmm_bar3_reg[17]), + .I2(com_cmmt_raddr[49]), + .O(com_cmm_u_cmm_decoder_N_38_0) + ); + defparam com_cmm_u_cmm_decoder_bar3_eq_raddr_3_0_I_78.INIT = 8'h6C; + LUT3 com_cmm_u_cmm_decoder_bar3_eq_raddr_3_0_I_78 ( + .I0(cfg_cfg_5072[180]), + .I1(com_cmm_bar3_reg[20]), + .I2(com_cmmt_raddr[52]), + .O(com_cmm_u_cmm_decoder_N_47_0) + ); + defparam com_cmm_u_cmm_decoder_bar3_eq_raddr_3_0_I_77.INIT = 8'h6C; + LUT3 com_cmm_u_cmm_decoder_bar3_eq_raddr_3_0_I_77 ( + .I0(cfg_cfg_5072[181]), + .I1(com_cmm_bar3_reg[21]), + .I2(com_cmmt_raddr[53]), + .O(com_cmm_u_cmm_decoder_N_46_0) + ); + defparam com_cmm_u_cmm_decoder_bar3_eq_raddr_3_0_I_68.INIT = 8'h6C; + LUT3 com_cmm_u_cmm_decoder_bar3_eq_raddr_3_0_I_68 ( + .I0(cfg_cfg_5072[179]), + .I1(com_cmm_bar3_reg[19]), + .I2(com_cmmt_raddr[51]), + .O(com_cmm_u_cmm_decoder_N_54_0) + ); + defparam com_cmm_u_cmm_decoder_bar3_eq_raddr_3_0_I_60.INIT = 8'h6C; + LUT3 com_cmm_u_cmm_decoder_bar3_eq_raddr_3_0_I_60 ( + .I0(cfg_cfg_5072[174]), + .I1(com_cmm_bar3_reg[14]), + .I2(com_cmmt_raddr[46]), + .O(com_cmm_u_cmm_decoder_N_63_0) + ); + defparam com_cmm_u_cmm_decoder_bar3_eq_raddr_3_0_I_59.INIT = 8'h6C; + LUT3 com_cmm_u_cmm_decoder_bar3_eq_raddr_3_0_I_59 ( + .I0(cfg_cfg_5072[175]), + .I1(com_cmm_bar3_reg[15]), + .I2(com_cmmt_raddr[47]), + .O(com_cmm_u_cmm_decoder_N_62_0) + ); + defparam com_cmm_u_cmm_decoder_bar3_eq_raddr_3_0_I_50.INIT = 8'h6C; + LUT3 com_cmm_u_cmm_decoder_bar3_eq_raddr_3_0_I_50 ( + .I0(cfg_cfg_5072[185]), + .I1(com_cmm_bar3_reg[25]), + .I2(com_cmmt_raddr[57]), + .O(com_cmm_u_cmm_decoder_N_70_0) + ); + defparam com_cmm_u_cmm_decoder_bar3_eq_raddr_3_0_I_42.INIT = 8'h6C; + LUT3 com_cmm_u_cmm_decoder_bar3_eq_raddr_3_0_I_42 ( + .I0(cfg_cfg_5072[172]), + .I1(com_cmm_bar3_reg[12]), + .I2(com_cmmt_raddr[44]), + .O(com_cmm_u_cmm_decoder_N_79) + ); + defparam com_cmm_u_cmm_decoder_bar3_eq_raddr_3_0_I_41.INIT = 8'h6C; + LUT3 com_cmm_u_cmm_decoder_bar3_eq_raddr_3_0_I_41 ( + .I0(cfg_cfg_5072[173]), + .I1(com_cmm_bar3_reg[13]), + .I2(com_cmmt_raddr[45]), + .O(com_cmm_u_cmm_decoder_N_78_0) + ); + defparam com_cmm_u_cmm_decoder_bar3_eq_raddr_3_0_I_32.INIT = 8'h6C; + LUT3 com_cmm_u_cmm_decoder_bar3_eq_raddr_3_0_I_32 ( + .I0(cfg_cfg_5072[171]), + .I1(com_cmm_bar3_reg[11]), + .I2(com_cmmt_raddr[43]), + .O(com_cmm_u_cmm_decoder_N_86_0) + ); + defparam com_cmm_u_cmm_decoder_bar3_eq_raddr_3_0_I_23.INIT = 8'h6C; + LUT3 com_cmm_u_cmm_decoder_bar3_eq_raddr_3_0_I_23 ( + .I0(cfg_cfg_5072[183]), + .I1(com_cmm_bar3_reg[23]), + .I2(com_cmmt_raddr[55]), + .O(com_cmm_u_cmm_decoder_N_94_0) + ); + defparam com_cmm_u_cmm_decoder_bar3_eq_raddr_3_0_I_14.INIT = 8'h6C; + LUT3 com_cmm_u_cmm_decoder_bar3_eq_raddr_3_0_I_14 ( + .I0(cfg_cfg_5072[191]), + .I1(com_cmm_bar3_reg[31]), + .I2(com_cmmt_raddr[63]), + .O(com_cmm_u_cmm_decoder_N_102_0) + ); + defparam com_cmm_u_cmm_decoder_bar3_eq_raddr_3_0_I_6.INIT = 8'h6C; + LUT3 com_cmm_u_cmm_decoder_bar3_eq_raddr_3_0_I_6 ( + .I0(cfg_cfg_5072[164]), + .I1(com_cmm_bar3_reg[4]), + .I2(com_cmmt_raddr[36]), + .O(com_cmm_u_cmm_decoder_N_111_0) + ); + defparam com_cmm_u_cmm_decoder_bar3_eq_raddr_3_0_I_5.INIT = 8'h6C; + LUT3 com_cmm_u_cmm_decoder_bar3_eq_raddr_3_0_I_5 ( + .I0(cfg_cfg_5072[165]), + .I1(com_cmm_bar3_reg[5]), + .I2(com_cmmt_raddr[37]), + .O(com_cmm_u_cmm_decoder_N_110) + ); + defparam com_cmm_u_cmm_decoder_bar2_eq_raddr_3_0_I_123.INIT = 8'h6C; + LUT3 com_cmm_u_cmm_decoder_bar2_eq_raddr_3_0_I_123 ( + .I0(cfg_cfg_5072[136]), + .I1(com_cmm_bar2_reg[8]), + .I2(com_cmmt_raddr[40]), + .O(com_cmm_u_cmm_decoder_N_7_0) + ); + defparam com_cmm_u_cmm_decoder_bar2_eq_raddr_3_0_I_122.INIT = 8'h6C; + LUT3 com_cmm_u_cmm_decoder_bar2_eq_raddr_3_0_I_122 ( + .I0(cfg_cfg_5072[137]), + .I1(com_cmm_bar2_reg[9]), + .I2(com_cmmt_raddr[41]), + .O(com_cmm_u_cmm_decoder_N_6_1) + ); + defparam com_cmm_u_cmm_decoder_bar2_eq_raddr_3_0_I_114.INIT = 8'h6C; + LUT3 com_cmm_u_cmm_decoder_bar2_eq_raddr_3_0_I_114 ( + .I0(cfg_cfg_5072[156]), + .I1(com_cmm_bar2_reg[28]), + .I2(com_cmmt_raddr[60]), + .O(com_cmm_u_cmm_decoder_N_15_1) + ); + defparam com_cmm_u_cmm_decoder_bar2_eq_raddr_3_0_I_113.INIT = 8'h6C; + LUT3 com_cmm_u_cmm_decoder_bar2_eq_raddr_3_0_I_113 ( + .I0(cfg_cfg_5072[157]), + .I1(com_cmm_bar2_reg[29]), + .I2(com_cmmt_raddr[61]), + .O(com_cmm_u_cmm_decoder_N_14_2) + ); + defparam com_cmm_u_cmm_decoder_bar2_eq_raddr_3_0_I_104.INIT = 8'h6C; + LUT3 com_cmm_u_cmm_decoder_bar2_eq_raddr_3_0_I_104 ( + .I0(cfg_cfg_5072[155]), + .I1(com_cmm_bar2_reg[27]), + .I2(com_cmmt_raddr[59]), + .O(com_cmm_u_cmm_decoder_N_22_1) + ); + defparam com_cmm_u_cmm_decoder_bar2_eq_raddr_3_0_I_96.INIT = 8'h6C; + LUT3 com_cmm_u_cmm_decoder_bar2_eq_raddr_3_0_I_96 ( + .I0(cfg_cfg_5072[134]), + .I1(com_cmm_bar2_reg[6]), + .I2(com_cmmt_raddr[38]), + .O(com_cmm_u_cmm_decoder_N_31_0) + ); + defparam com_cmm_u_cmm_decoder_bar2_eq_raddr_3_0_I_86.INIT = 8'h6C; + LUT3 com_cmm_u_cmm_decoder_bar2_eq_raddr_3_0_I_86 ( + .I0(cfg_cfg_5072[145]), + .I1(com_cmm_bar2_reg[17]), + .I2(com_cmmt_raddr[49]), + .O(com_cmm_u_cmm_decoder_N_38_1) + ); + defparam com_cmm_u_cmm_decoder_bar2_eq_raddr_3_0_I_77.INIT = 8'h6C; + LUT3 com_cmm_u_cmm_decoder_bar2_eq_raddr_3_0_I_77 ( + .I0(cfg_cfg_5072[149]), + .I1(com_cmm_bar2_reg[21]), + .I2(com_cmmt_raddr[53]), + .O(com_cmm_u_cmm_decoder_N_46_1) + ); + defparam com_cmm_u_cmm_decoder_bar2_eq_raddr_3_0_I_68.INIT = 8'h6C; + LUT3 com_cmm_u_cmm_decoder_bar2_eq_raddr_3_0_I_68 ( + .I0(cfg_cfg_5072[147]), + .I1(com_cmm_bar2_reg[19]), + .I2(com_cmmt_raddr[51]), + .O(com_cmm_u_cmm_decoder_N_54_1) + ); + defparam com_cmm_u_cmm_decoder_bar2_eq_raddr_3_0_I_60.INIT = 8'h6C; + LUT3 com_cmm_u_cmm_decoder_bar2_eq_raddr_3_0_I_60 ( + .I0(cfg_cfg_5072[142]), + .I1(com_cmm_bar2_reg[14]), + .I2(com_cmmt_raddr[46]), + .O(com_cmm_u_cmm_decoder_N_63_1) + ); + defparam com_cmm_u_cmm_decoder_bar2_eq_raddr_3_0_I_59.INIT = 8'h6C; + LUT3 com_cmm_u_cmm_decoder_bar2_eq_raddr_3_0_I_59 ( + .I0(cfg_cfg_5072[143]), + .I1(com_cmm_bar2_reg[15]), + .I2(com_cmmt_raddr[47]), + .O(com_cmm_u_cmm_decoder_N_62_1) + ); + defparam com_cmm_u_cmm_decoder_bar2_eq_raddr_3_0_I_50.INIT = 8'h6C; + LUT3 com_cmm_u_cmm_decoder_bar2_eq_raddr_3_0_I_50 ( + .I0(cfg_cfg_5072[153]), + .I1(com_cmm_bar2_reg[25]), + .I2(com_cmmt_raddr[57]), + .O(com_cmm_u_cmm_decoder_N_70_1) + ); + defparam com_cmm_u_cmm_decoder_bar2_eq_raddr_3_0_I_42.INIT = 8'h6C; + LUT3 com_cmm_u_cmm_decoder_bar2_eq_raddr_3_0_I_42 ( + .I0(cfg_cfg_5072[140]), + .I1(com_cmm_bar2_reg[12]), + .I2(com_cmmt_raddr[44]), + .O(com_cmm_u_cmm_decoder_N_79_0) + ); + defparam com_cmm_u_cmm_decoder_bar2_eq_raddr_3_0_I_41.INIT = 8'h6C; + LUT3 com_cmm_u_cmm_decoder_bar2_eq_raddr_3_0_I_41 ( + .I0(cfg_cfg_5072[141]), + .I1(com_cmm_bar2_reg[13]), + .I2(com_cmmt_raddr[45]), + .O(com_cmm_u_cmm_decoder_N_78_1) + ); + defparam com_cmm_u_cmm_decoder_bar2_eq_raddr_3_0_I_32.INIT = 8'h6C; + LUT3 com_cmm_u_cmm_decoder_bar2_eq_raddr_3_0_I_32 ( + .I0(cfg_cfg_5072[139]), + .I1(com_cmm_bar2_reg[11]), + .I2(com_cmmt_raddr[43]), + .O(com_cmm_u_cmm_decoder_N_86_1) + ); + defparam com_cmm_u_cmm_decoder_bar2_eq_raddr_3_0_I_23.INIT = 8'h6C; + LUT3 com_cmm_u_cmm_decoder_bar2_eq_raddr_3_0_I_23 ( + .I0(cfg_cfg_5072[151]), + .I1(com_cmm_bar2_reg[23]), + .I2(com_cmmt_raddr[55]), + .O(com_cmm_u_cmm_decoder_N_94_1) + ); + defparam com_cmm_u_cmm_decoder_bar2_eq_raddr_3_0_I_14.INIT = 8'h6C; + LUT3 com_cmm_u_cmm_decoder_bar2_eq_raddr_3_0_I_14 ( + .I0(cfg_cfg_5072[159]), + .I1(com_cmm_bar2_reg[31]), + .I2(com_cmmt_raddr[63]), + .O(com_cmm_u_cmm_decoder_N_102_1) + ); + defparam com_cmm_u_cmm_decoder_bar2_eq_raddr_3_0_I_6.INIT = 8'h6C; + LUT3 com_cmm_u_cmm_decoder_bar2_eq_raddr_3_0_I_6 ( + .I0(cfg_cfg_5072[132]), + .I1(com_cmm_bar2_reg[4]), + .I2(com_cmmt_raddr[36]), + .O(com_cmm_u_cmm_decoder_N_111_1) + ); + defparam com_cmm_u_cmm_decoder_bar1_eq_raddr_3_0_I_122.INIT = 8'h6C; + LUT3 com_cmm_u_cmm_decoder_bar1_eq_raddr_3_0_I_122 ( + .I0(cfg_cfg_5072[105]), + .I1(com_cmm_bar1_reg[9]), + .I2(com_cmmt_raddr[41]), + .O(com_cmm_u_cmm_decoder_N_6_2) + ); + defparam com_cmm_u_cmm_decoder_bar1_eq_raddr_3_0_I_114.INIT = 8'h6C; + LUT3 com_cmm_u_cmm_decoder_bar1_eq_raddr_3_0_I_114 ( + .I0(cfg_cfg_5072[124]), + .I1(com_cmm_bar1_reg[28]), + .I2(com_cmmt_raddr[60]), + .O(com_cmm_u_cmm_decoder_N_15_2) + ); + defparam com_cmm_u_cmm_decoder_bar1_eq_raddr_3_0_I_113.INIT = 8'h6C; + LUT3 com_cmm_u_cmm_decoder_bar1_eq_raddr_3_0_I_113 ( + .I0(cfg_cfg_5072[125]), + .I1(com_cmm_bar1_reg[29]), + .I2(com_cmmt_raddr[61]), + .O(com_cmm_u_cmm_decoder_N_14_3) + ); + defparam com_cmm_u_cmm_decoder_bar1_eq_raddr_3_0_I_104.INIT = 8'h6C; + LUT3 com_cmm_u_cmm_decoder_bar1_eq_raddr_3_0_I_104 ( + .I0(cfg_cfg_5072[123]), + .I1(com_cmm_bar1_reg[27]), + .I2(com_cmmt_raddr[59]), + .O(com_cmm_u_cmm_decoder_N_22_2) + ); + defparam com_cmm_u_cmm_decoder_bar1_eq_raddr_3_0_I_96.INIT = 8'h6C; + LUT3 com_cmm_u_cmm_decoder_bar1_eq_raddr_3_0_I_96 ( + .I0(cfg_cfg_5072[102]), + .I1(com_cmm_bar1_reg[6]), + .I2(com_cmmt_raddr[38]), + .O(com_cmm_u_cmm_decoder_N_31_1) + ); + defparam com_cmm_u_cmm_decoder_bar1_eq_raddr_3_0_I_95.INIT = 8'h6C; + LUT3 com_cmm_u_cmm_decoder_bar1_eq_raddr_3_0_I_95 ( + .I0(cfg_cfg_5072[103]), + .I1(com_cmm_bar1_reg[7]), + .I2(com_cmmt_raddr[39]), + .O(com_cmm_u_cmm_decoder_N_30_1) + ); + defparam com_cmm_u_cmm_decoder_bar1_eq_raddr_3_0_I_86.INIT = 8'h6C; + LUT3 com_cmm_u_cmm_decoder_bar1_eq_raddr_3_0_I_86 ( + .I0(cfg_cfg_5072[113]), + .I1(com_cmm_bar1_reg[17]), + .I2(com_cmmt_raddr[49]), + .O(com_cmm_u_cmm_decoder_N_38_2) + ); + defparam com_cmm_u_cmm_decoder_bar1_eq_raddr_3_0_I_78.INIT = 8'h6C; + LUT3 com_cmm_u_cmm_decoder_bar1_eq_raddr_3_0_I_78 ( + .I0(cfg_cfg_5072[116]), + .I1(com_cmm_bar1_reg[20]), + .I2(com_cmmt_raddr[52]), + .O(com_cmm_u_cmm_decoder_N_47_1) + ); + defparam com_cmm_u_cmm_decoder_bar1_eq_raddr_3_0_I_77.INIT = 8'h6C; + LUT3 com_cmm_u_cmm_decoder_bar1_eq_raddr_3_0_I_77 ( + .I0(cfg_cfg_5072[117]), + .I1(com_cmm_bar1_reg[21]), + .I2(com_cmmt_raddr[53]), + .O(com_cmm_u_cmm_decoder_N_46_2) + ); + defparam com_cmm_u_cmm_decoder_bar1_eq_raddr_3_0_I_68.INIT = 8'h6C; + LUT3 com_cmm_u_cmm_decoder_bar1_eq_raddr_3_0_I_68 ( + .I0(cfg_cfg_5072[115]), + .I1(com_cmm_bar1_reg[19]), + .I2(com_cmmt_raddr[51]), + .O(com_cmm_u_cmm_decoder_N_54_2) + ); + defparam com_cmm_u_cmm_decoder_bar1_eq_raddr_3_0_I_60.INIT = 8'h6C; + LUT3 com_cmm_u_cmm_decoder_bar1_eq_raddr_3_0_I_60 ( + .I0(cfg_cfg_5072[110]), + .I1(com_cmm_bar1_reg[14]), + .I2(com_cmmt_raddr[46]), + .O(com_cmm_u_cmm_decoder_N_63_2) + ); + defparam com_cmm_u_cmm_decoder_bar1_eq_raddr_3_0_I_59.INIT = 8'h6C; + LUT3 com_cmm_u_cmm_decoder_bar1_eq_raddr_3_0_I_59 ( + .I0(cfg_cfg_5072[111]), + .I1(com_cmm_bar1_reg[15]), + .I2(com_cmmt_raddr[47]), + .O(com_cmm_u_cmm_decoder_N_62_2) + ); + defparam com_cmm_u_cmm_decoder_bar1_eq_raddr_3_0_I_50.INIT = 8'h6C; + LUT3 com_cmm_u_cmm_decoder_bar1_eq_raddr_3_0_I_50 ( + .I0(cfg_cfg_5072[121]), + .I1(com_cmm_bar1_reg[25]), + .I2(com_cmmt_raddr[57]), + .O(com_cmm_u_cmm_decoder_N_70_2) + ); + defparam com_cmm_u_cmm_decoder_bar1_eq_raddr_3_0_I_41.INIT = 8'h6C; + LUT3 com_cmm_u_cmm_decoder_bar1_eq_raddr_3_0_I_41 ( + .I0(cfg_cfg_5072[109]), + .I1(com_cmm_bar1_reg[13]), + .I2(com_cmmt_raddr[45]), + .O(com_cmm_u_cmm_decoder_N_78_2) + ); + defparam com_cmm_u_cmm_decoder_bar1_eq_raddr_3_0_I_32.INIT = 8'h6C; + LUT3 com_cmm_u_cmm_decoder_bar1_eq_raddr_3_0_I_32 ( + .I0(cfg_cfg_5072[107]), + .I1(com_cmm_bar1_reg[11]), + .I2(com_cmmt_raddr[43]), + .O(com_cmm_u_cmm_decoder_N_86_2) + ); + defparam com_cmm_u_cmm_decoder_bar1_eq_raddr_3_0_I_23.INIT = 8'h6C; + LUT3 com_cmm_u_cmm_decoder_bar1_eq_raddr_3_0_I_23 ( + .I0(cfg_cfg_5072[119]), + .I1(com_cmm_bar1_reg[23]), + .I2(com_cmmt_raddr[55]), + .O(com_cmm_u_cmm_decoder_N_94_2) + ); + defparam com_cmm_u_cmm_decoder_bar1_eq_raddr_3_0_I_14.INIT = 8'h6C; + LUT3 com_cmm_u_cmm_decoder_bar1_eq_raddr_3_0_I_14 ( + .I0(cfg_cfg_5072[127]), + .I1(com_cmm_bar1_reg[31]), + .I2(com_cmmt_raddr[63]), + .O(com_cmm_u_cmm_decoder_N_102_2) + ); + defparam com_cmm_u_cmm_decoder_bar1_eq_raddr_3_0_I_6.INIT = 8'h6C; + LUT3 com_cmm_u_cmm_decoder_bar1_eq_raddr_3_0_I_6 ( + .I0(cfg_cfg_5072[100]), + .I1(com_cmm_bar1_reg[4]), + .I2(com_cmmt_raddr[36]), + .O(com_cmm_u_cmm_decoder_N_111_2) + ); + defparam com_cmm_u_cmm_decoder_bar0_eq_raddr_3_0_I_122.INIT = 8'h6C; + LUT3_L com_cmm_u_cmm_decoder_bar0_eq_raddr_3_0_I_122 ( + .I0(cfg_cfg_5072[73]), + .I1(com_cmm_bar0_reg_9_), + .I2(com_cmmt_raddr[41]), + .LO(com_cmm_u_cmm_decoder_N_6_4) + ); + defparam com_cmm_u_cmm_decoder_bar0_eq_raddr_3_0_I_113.INIT = 8'h6C; + LUT3_L com_cmm_u_cmm_decoder_bar0_eq_raddr_3_0_I_113 ( + .I0(cfg_cfg_5072[93]), + .I1(com_cmm_bar0_reg_29_), + .I2(com_cmmt_raddr[61]), + .LO(com_cmm_u_cmm_decoder_N_14_5) + ); + defparam com_cmm_u_cmm_decoder_bar0_eq_raddr_3_0_I_104.INIT = 8'h6C; + LUT3_L com_cmm_u_cmm_decoder_bar0_eq_raddr_3_0_I_104 ( + .I0(cfg_cfg_5072[91]), + .I1(com_cmm_bar0_reg_27_), + .I2(com_cmmt_raddr[59]), + .LO(com_cmm_u_cmm_decoder_N_22_4) + ); + defparam com_cmm_u_cmm_decoder_bar0_eq_raddr_3_0_I_95.INIT = 8'h6C; + LUT3_L com_cmm_u_cmm_decoder_bar0_eq_raddr_3_0_I_95 ( + .I0(cfg_cfg_5072[71]), + .I1(com_cmm_bar0_reg_7_), + .I2(com_cmmt_raddr[39]), + .LO(com_cmm_u_cmm_decoder_N_30_3) + ); + defparam com_cmm_u_cmm_decoder_bar0_eq_raddr_3_0_I_86.INIT = 8'h6C; + LUT3_L com_cmm_u_cmm_decoder_bar0_eq_raddr_3_0_I_86 ( + .I0(cfg_cfg_5072[81]), + .I1(com_cmm_bar0_reg_17_), + .I2(com_cmmt_raddr[49]), + .LO(com_cmm_u_cmm_decoder_N_38_4) + ); + defparam com_cmm_u_cmm_decoder_bar0_eq_raddr_3_0_I_77.INIT = 8'h6C; + LUT3_L com_cmm_u_cmm_decoder_bar0_eq_raddr_3_0_I_77 ( + .I0(cfg_cfg_5072[85]), + .I1(com_cmm_bar0_reg_21_), + .I2(com_cmmt_raddr[53]), + .LO(com_cmm_u_cmm_decoder_N_46_4) + ); + defparam com_cmm_u_cmm_decoder_bar0_eq_raddr_3_0_I_68.INIT = 8'h6C; + LUT3_L com_cmm_u_cmm_decoder_bar0_eq_raddr_3_0_I_68 ( + .I0(cfg_cfg_5072[83]), + .I1(com_cmm_bar0_reg_19_), + .I2(com_cmmt_raddr[51]), + .LO(com_cmm_u_cmm_decoder_N_54_4) + ); + defparam com_cmm_u_cmm_decoder_bar0_eq_raddr_3_0_I_59.INIT = 8'h6C; + LUT3_L com_cmm_u_cmm_decoder_bar0_eq_raddr_3_0_I_59 ( + .I0(cfg_cfg_5072[79]), + .I1(com_cmm_bar0_reg_15_), + .I2(com_cmmt_raddr[47]), + .LO(com_cmm_u_cmm_decoder_N_62_4) + ); + defparam com_cmm_u_cmm_decoder_bar0_eq_raddr_3_0_I_50.INIT = 8'h6C; + LUT3_L com_cmm_u_cmm_decoder_bar0_eq_raddr_3_0_I_50 ( + .I0(cfg_cfg_5072[89]), + .I1(com_cmm_bar0_reg_25_), + .I2(com_cmmt_raddr[57]), + .LO(com_cmm_u_cmm_decoder_N_70_4) + ); + defparam com_cmm_u_cmm_decoder_bar0_eq_raddr_3_0_I_41.INIT = 8'h6C; + LUT3_L com_cmm_u_cmm_decoder_bar0_eq_raddr_3_0_I_41 ( + .I0(cfg_cfg_5072[77]), + .I1(com_cmm_bar0_reg_13_), + .I2(com_cmmt_raddr[45]), + .LO(com_cmm_u_cmm_decoder_N_78_4) + ); + defparam com_cmm_u_cmm_decoder_bar0_eq_raddr_3_0_I_32.INIT = 8'h6C; + LUT3_L com_cmm_u_cmm_decoder_bar0_eq_raddr_3_0_I_32 ( + .I0(cfg_cfg_5072[75]), + .I1(com_cmm_bar0_reg_11_), + .I2(com_cmmt_raddr[43]), + .LO(com_cmm_u_cmm_decoder_N_86_4) + ); + defparam com_cmm_u_cmm_decoder_bar0_eq_raddr_3_0_I_23.INIT = 8'h6C; + LUT3_L com_cmm_u_cmm_decoder_bar0_eq_raddr_3_0_I_23 ( + .I0(cfg_cfg_5072[87]), + .I1(com_cmm_bar0_reg_23_), + .I2(com_cmmt_raddr[55]), + .LO(com_cmm_u_cmm_decoder_N_94_4) + ); + defparam com_cmm_u_cmm_decoder_bar0_eq_raddr_3_0_I_14.INIT = 8'h6C; + LUT3_L com_cmm_u_cmm_decoder_bar0_eq_raddr_3_0_I_14 ( + .I0(cfg_cfg_5072[95]), + .I1(com_cmm_bar0_reg_31_), + .I2(com_cmmt_raddr[63]), + .LO(com_cmm_u_cmm_decoder_N_102_7) + ); + defparam com_cmm_u_cmm_decoder_bar0_eq_raddr_3_0_I_5.INIT = 8'h6C; + LUT3_L com_cmm_u_cmm_decoder_bar0_eq_raddr_3_0_I_5 ( + .I0(cfg_cfg_5072[69]), + .I1(com_cmm_bar0_reg_5_), + .I2(com_cmmt_raddr[37]), + .LO(com_cmm_u_cmm_decoder_N_110_1) + ); + defparam com_cmm_u_cmm_decoder_un9_bar45_64_hit_high_0_I_122.INIT = 8'h6C; + LUT3_L com_cmm_u_cmm_decoder_un9_bar45_64_hit_high_0_I_122 ( + .I0(cfg_cfg_5072[201]), + .I1(com_cmm_bar4_reg[9]), + .I2(com_cmmt_raddr[9]), + .LO(com_cmm_u_cmm_decoder_N_6_3) + ); + defparam com_cmm_u_cmm_decoder_un9_bar45_64_hit_high_0_I_113.INIT = 8'h6C; + LUT3_L com_cmm_u_cmm_decoder_un9_bar45_64_hit_high_0_I_113 ( + .I0(cfg_cfg_5072[221]), + .I1(com_cmm_bar4_reg[29]), + .I2(com_cmmt_raddr[29]), + .LO(com_cmm_u_cmm_decoder_N_14_4) + ); + defparam com_cmm_u_cmm_decoder_un9_bar45_64_hit_high_0_I_104.INIT = 8'h6C; + LUT3_L com_cmm_u_cmm_decoder_un9_bar45_64_hit_high_0_I_104 ( + .I0(cfg_cfg_5072[219]), + .I1(com_cmm_bar4_reg[27]), + .I2(com_cmmt_raddr[27]), + .LO(com_cmm_u_cmm_decoder_N_22_3) + ); + defparam com_cmm_u_cmm_decoder_un9_bar45_64_hit_high_0_I_95.INIT = 8'h6C; + LUT3_L com_cmm_u_cmm_decoder_un9_bar45_64_hit_high_0_I_95 ( + .I0(cfg_cfg_5072[199]), + .I1(com_cmm_bar4_reg[7]), + .I2(com_cmmt_raddr[7]), + .LO(com_cmm_u_cmm_decoder_N_30_2) + ); + defparam com_cmm_u_cmm_decoder_un9_bar45_64_hit_high_0_I_86.INIT = 8'h6C; + LUT3_L com_cmm_u_cmm_decoder_un9_bar45_64_hit_high_0_I_86 ( + .I0(cfg_cfg_5072[209]), + .I1(com_cmm_bar4_reg[17]), + .I2(com_cmmt_raddr[17]), + .LO(com_cmm_u_cmm_decoder_N_38_3) + ); + defparam com_cmm_u_cmm_decoder_un9_bar45_64_hit_high_0_I_77.INIT = 8'h6C; + LUT3_L com_cmm_u_cmm_decoder_un9_bar45_64_hit_high_0_I_77 ( + .I0(cfg_cfg_5072[213]), + .I1(com_cmm_bar4_reg[21]), + .I2(com_cmmt_raddr[21]), + .LO(com_cmm_u_cmm_decoder_N_46_3) + ); + defparam com_cmm_u_cmm_decoder_un9_bar45_64_hit_high_0_I_68.INIT = 8'h6C; + LUT3_L com_cmm_u_cmm_decoder_un9_bar45_64_hit_high_0_I_68 ( + .I0(cfg_cfg_5072[211]), + .I1(com_cmm_bar4_reg[19]), + .I2(com_cmmt_raddr[19]), + .LO(com_cmm_u_cmm_decoder_N_54_3) + ); + defparam com_cmm_u_cmm_decoder_un9_bar45_64_hit_high_0_I_59.INIT = 8'h6C; + LUT3_L com_cmm_u_cmm_decoder_un9_bar45_64_hit_high_0_I_59 ( + .I0(cfg_cfg_5072[207]), + .I1(com_cmm_bar4_reg[15]), + .I2(com_cmmt_raddr[15]), + .LO(com_cmm_u_cmm_decoder_N_62_3) + ); + defparam com_cmm_u_cmm_decoder_un9_bar45_64_hit_high_0_I_50.INIT = 8'h6C; + LUT3_L com_cmm_u_cmm_decoder_un9_bar45_64_hit_high_0_I_50 ( + .I0(cfg_cfg_5072[217]), + .I1(com_cmm_bar4_reg[25]), + .I2(com_cmmt_raddr[25]), + .LO(com_cmm_u_cmm_decoder_N_70_3) + ); + defparam com_cmm_u_cmm_decoder_un9_bar45_64_hit_high_0_I_41.INIT = 8'h6C; + LUT3_L com_cmm_u_cmm_decoder_un9_bar45_64_hit_high_0_I_41 ( + .I0(cfg_cfg_5072[205]), + .I1(com_cmm_bar4_reg[13]), + .I2(com_cmmt_raddr[13]), + .LO(com_cmm_u_cmm_decoder_N_78_3) + ); + defparam com_cmm_u_cmm_decoder_un9_bar45_64_hit_high_0_I_32.INIT = 8'h6C; + LUT3_L com_cmm_u_cmm_decoder_un9_bar45_64_hit_high_0_I_32 ( + .I0(cfg_cfg_5072[203]), + .I1(com_cmm_bar4_reg[11]), + .I2(com_cmmt_raddr[11]), + .LO(com_cmm_u_cmm_decoder_N_86_3) + ); + defparam com_cmm_u_cmm_decoder_un9_bar45_64_hit_high_0_I_23.INIT = 8'h6C; + LUT3_L com_cmm_u_cmm_decoder_un9_bar45_64_hit_high_0_I_23 ( + .I0(cfg_cfg_5072[215]), + .I1(com_cmm_bar4_reg[23]), + .I2(com_cmmt_raddr[23]), + .LO(com_cmm_u_cmm_decoder_N_94_3) + ); + defparam com_cmm_u_cmm_decoder_un9_bar45_64_hit_high_0_I_14.INIT = 8'h6C; + LUT3_L com_cmm_u_cmm_decoder_un9_bar45_64_hit_high_0_I_14 ( + .I0(cfg_cfg_5072[223]), + .I1(com_cmm_bar4_reg[31]), + .I2(com_cmmt_raddr[31]), + .LO(com_cmm_u_cmm_decoder_N_102_8) + ); + defparam com_cmm_u_cmm_decoder_un9_bar45_64_hit_high_0_I_5.INIT = 8'h6C; + LUT3_L com_cmm_u_cmm_decoder_un9_bar45_64_hit_high_0_I_5 ( + .I0(cfg_cfg_5072[197]), + .I1(com_cmm_bar4_reg[5]), + .I2(com_cmmt_raddr[5]), + .LO(com_cmm_u_cmm_decoder_N_110_0) + ); + defparam com_cmm_u_cmm_decoder_un10_bar34_64_hit_low_0_I_32.INIT = 8'h6C; + LUT3_L com_cmm_u_cmm_decoder_un10_bar34_64_hit_low_0_I_32 ( + .I0(cfg_cfg_5072[192]), + .I1(com_cmm_bar4_reg[0]), + .I2(com_cmmt_raddr[32]), + .LO(com_cmm_u_cmm_decoder_N_102_12) + ); + defparam com_cmm_u_cmm_decoder_un10_bar45_64_hit_low_0_I_131.INIT = 8'h6C; + LUT3_L com_cmm_u_cmm_decoder_un10_bar45_64_hit_low_0_I_131 ( + .I0(cfg_cfg_5072[226]), + .I1(com_cmm_bar5_reg[2]), + .I2(com_cmmt_raddr[34]), + .LO(com_cmm_u_cmm_decoder_N_14) + ); + defparam com_cmm_u_cmm_decoder_un10_bar45_64_hit_low_0_I_32.INIT = 8'h6C; + LUT3_L com_cmm_u_cmm_decoder_un10_bar45_64_hit_low_0_I_32 ( + .I0(cfg_cfg_5072[224]), + .I1(com_cmm_bar5_reg[0]), + .I2(com_cmmt_raddr[32]), + .LO(com_cmm_u_cmm_decoder_N_102_13) + ); + defparam com_cmm_u_cmm_decoder_bar45_64_hit_high_3_0_a2_0_a2_0_a2_0_a2_0.INIT = 4'h8; + LUT2 com_cmm_u_cmm_decoder_bar45_64_hit_high_3_0_a2_0_a2_0_a2_0_a2_0 ( + .I0(com_cmm_bar4_reg[2]), + .I1(com_cmm_u_cmm_decoder_un18_bar3_32_hit_nc_0_and_1), + .O(com_cmm_u_cmm_decoder_N_45436) + ); + defparam com_cmm_u_cmm_decoder_un11_bar34_64_hit_low_5_and_0_a2_0_a2_0_a2.INIT = 16'h0001; + LUT4 com_cmm_u_cmm_decoder_un11_bar34_64_hit_low_5_and_0_a2_0_a2_0_a2 ( + .I0(cfg_cfg_5072[212]), + .I1(cfg_cfg_5072[213]), + .I2(cfg_cfg_5072[214]), + .I3(cfg_cfg_5072[215]), + .O(com_cmm_u_cmm_decoder_un11_bar4_32_hit_nc_5_and) + ); + defparam com_cmm_u_cmm_decoder_un11_bar34_64_hit_low_3_and_0_a2_0_a2_0_a2.INIT = 16'h0001; + LUT4 com_cmm_u_cmm_decoder_un11_bar34_64_hit_low_3_and_0_a2_0_a2_0_a2 ( + .I0(cfg_cfg_5072[204]), + .I1(cfg_cfg_5072[205]), + .I2(cfg_cfg_5072[206]), + .I3(cfg_cfg_5072[207]), + .O(com_cmm_u_cmm_decoder_un11_bar4_32_hit_nc_3_and) + ); + defparam com_cmm_u_cmm_decoder_un11_bar34_64_hit_low_4_and_0_a2_0_a2_0_a2.INIT = 16'h0001; + LUT4 com_cmm_u_cmm_decoder_un11_bar34_64_hit_low_4_and_0_a2_0_a2_0_a2 ( + .I0(cfg_cfg_5072[208]), + .I1(cfg_cfg_5072[209]), + .I2(cfg_cfg_5072[210]), + .I3(cfg_cfg_5072[211]), + .O(com_cmm_u_cmm_decoder_un11_bar4_32_hit_nc_4_and) + ); + defparam com_cmm_u_cmm_decoder_un11_bar34_64_hit_low_2_and_0_a2_0_a2_0_a2.INIT = 16'h0001; + LUT4 com_cmm_u_cmm_decoder_un11_bar34_64_hit_low_2_and_0_a2_0_a2_0_a2 ( + .I0(cfg_cfg_5072[200]), + .I1(cfg_cfg_5072[201]), + .I2(cfg_cfg_5072[202]), + .I3(cfg_cfg_5072[203]), + .O(com_cmm_u_cmm_decoder_un11_bar4_32_hit_nc_2_and) + ); + defparam com_cmm_u_cmm_decoder_un11_bar34_64_hit_low_7_and_0_a2_0_a2_0_a2.INIT = 16'h0001; + LUT4 com_cmm_u_cmm_decoder_un11_bar34_64_hit_low_7_and_0_a2_0_a2_0_a2 ( + .I0(cfg_cfg_5072[220]), + .I1(cfg_cfg_5072[221]), + .I2(cfg_cfg_5072[222]), + .I3(cfg_cfg_5072[223]), + .O(com_cmm_u_cmm_decoder_un11_bar4_32_hit_nc_7_and) + ); + defparam com_cmm_u_cmm_decoder_un11_bar34_64_hit_low_6_and_0_a2_0_a2.INIT = 16'h0001; + LUT4 com_cmm_u_cmm_decoder_un11_bar34_64_hit_low_6_and_0_a2_0_a2 ( + .I0(cfg_cfg_5072[216]), + .I1(cfg_cfg_5072[217]), + .I2(cfg_cfg_5072[218]), + .I3(cfg_cfg_5072[219]), + .O(com_cmm_u_cmm_decoder_un11_bar4_32_hit_nc_6_and) + ); + defparam com_cmm_u_cmm_decoder_un11_bar34_64_hit_low_0_and_0_a2_0_a2_0_a2.INIT = 16'h0001; + LUT4 com_cmm_u_cmm_decoder_un11_bar34_64_hit_low_0_and_0_a2_0_a2_0_a2 ( + .I0(cfg_cfg_5072[192]), + .I1(cfg_cfg_5072[193]), + .I2(cfg_cfg_5072[194]), + .I3(cfg_cfg_5072[195]), + .O(com_cmm_u_cmm_decoder_un11_bar4_32_hit_nc_0) + ); + defparam com_cmm_u_cmm_decoder_un11_bar34_64_hit_low_1_and_0_a2_0_a2_0_a2_0_a2.INIT = 16'h0001; + LUT4 com_cmm_u_cmm_decoder_un11_bar34_64_hit_low_1_and_0_a2_0_a2_0_a2_0_a2 ( + .I0(cfg_cfg_5072[196]), + .I1(cfg_cfg_5072[197]), + .I2(cfg_cfg_5072[198]), + .I3(cfg_cfg_5072[199]), + .O(com_cmm_u_cmm_decoder_un11_bar4_32_hit_nc_1_and) + ); + defparam com_cmm_u_cmm_decoder_bar45_64_hit_low_3_0_a2_0_a2_0_a2_0.INIT = 8'h80; + LUT3 com_cmm_u_cmm_decoder_bar45_64_hit_low_3_0_a2_0_a2_0_a2_0 ( + .I0(com_cmm_u_cmm_decoder_N_48989_i), + .I1(NlwRenamedSig_OI_cfg_command_1_), + .I2(com_cmmt_mem64), + .O(com_cmm_u_cmm_decoder_bar23_64_hit_low_3_0_a2_0_a2_0) + ); + defparam com_cmm_u_cmm_decoder_bar01_64_hit_high_3_0_a2_0_a2_0_a2_0.INIT = 8'h10; + LUT3 com_cmm_u_cmm_decoder_bar01_64_hit_high_3_0_a2_0_a2_0_a2_0 ( + .I0(com_cmm_bar0_reg_0_), + .I1(com_cmm_bar0_reg_1_), + .I2(com_cmm_bar0_reg_2_), + .O(com_cmm_u_cmm_decoder_N_45440) + ); + defparam com_cmm_u_cmm_decoder_bar_hit_7_0_a2_0_4_.INIT = 16'h0777; + LUT4_L com_cmm_u_cmm_decoder_bar_hit_7_0_a2_0_4_ ( + .I0(com_cmm_u_cmm_decoder_bar4_32_hit_nc_4494), + .I1(com_cmm_u_cmm_decoder_bar4_eq_raddr_4487), + .I2(com_cmm_u_cmm_decoder_bar45_64_hit_high_4489), + .I3(com_cmm_u_cmm_decoder_bar45_64_hit_low_4498), + .LO(com_cmm_u_cmm_decoder_bar_hit_7_0_a2_0[4]) + ); + defparam com_cmm_u_cmm_decoder_bar_hit_6_0_a2_0_3_.INIT = 16'h0777; + LUT4_L com_cmm_u_cmm_decoder_bar_hit_6_0_a2_0_3_ ( + .I0(com_cmm_u_cmm_decoder_bar3_32_hit_nc_4495), + .I1(com_cmm_u_cmm_decoder_bar3_eq_raddr_4479), + .I2(com_cmm_u_cmm_decoder_bar34_64_hit_high_4490), + .I3(com_cmm_u_cmm_decoder_bar34_64_hit_low_4499), + .LO(com_cmm_u_cmm_decoder_bar_hit_6_0_a2_0[3]) + ); + defparam com_cmm_u_cmm_decoder_bar_hit_5_0_a2_0_2_.INIT = 16'h0777; + LUT4_L com_cmm_u_cmm_decoder_bar_hit_5_0_a2_0_2_ ( + .I0(com_cmm_u_cmm_decoder_bar2_32_hit_nc_4496), + .I1(com_cmm_u_cmm_decoder_bar2_eq_raddr_4480), + .I2(com_cmm_u_cmm_decoder_bar23_64_hit_high_4491), + .I3(com_cmm_u_cmm_decoder_bar23_64_hit_low_4500), + .LO(com_cmm_u_cmm_decoder_bar_hit_5_0_a2_0[2]) + ); + defparam com_cmm_u_cmm_decoder_bar_hit_4_0_a2_0_1_.INIT = 16'h0777; + LUT4_L com_cmm_u_cmm_decoder_bar_hit_4_0_a2_0_1_ ( + .I0(com_cmm_u_cmm_decoder_bar1_32_hit_nc_4497), + .I1(com_cmm_u_cmm_decoder_bar1_eq_raddr_4481), + .I2(com_cmm_u_cmm_decoder_bar12_64_hit_high_4492), + .I3(com_cmm_u_cmm_decoder_bar12_64_hit_low_4501), + .LO(com_cmm_u_cmm_decoder_bar_hit_4_0_a2_0[1]) + ); + defparam com_cmm_u_cmm_decoder_bar5_32_hit_nc_3_i_0_0_m2_0.INIT = 8'h35; + LUT3 com_cmm_u_cmm_decoder_bar5_32_hit_nc_3_i_0_0_m2_0 ( + .I0(com_cmm_u_cmm_decoder_N_44866_i), + .I1(com_cmm_u_cmm_decoder_bar5_32_hit_nc_3_i_0_0_o3_0_4455), + .I2(cfg_cfg_5072[224]), + .O(com_cmm_u_cmm_decoder_N_44997) + ); + defparam com_cmm_u_cmm_decoder_bar5_eq_raddr_3_0_I_126.INIT = 16'h0903; + LUT4 com_cmm_u_cmm_decoder_bar5_eq_raddr_3_0_I_126 ( + .I0(cfg_cfg_5072[232]), + .I1(com_cmm_bar5_reg[8]), + .I2(com_cmm_u_cmm_decoder_N_6_9), + .I3(com_cmmt_raddr[40]), + .O(com_cmm_u_cmm_decoder_N_3_9) + ); + defparam com_cmm_u_cmm_decoder_bar5_eq_raddr_3_0_I_117.INIT = 16'h0903; + LUT4 com_cmm_u_cmm_decoder_bar5_eq_raddr_3_0_I_117 ( + .I0(cfg_cfg_5072[252]), + .I1(com_cmm_bar5_reg[28]), + .I2(com_cmm_u_cmm_decoder_N_14_10), + .I3(com_cmmt_raddr[60]), + .O(com_cmm_u_cmm_decoder_N_11_10) + ); + defparam com_cmm_u_cmm_decoder_bar5_eq_raddr_3_0_I_108.INIT = 16'h0903; + LUT4 com_cmm_u_cmm_decoder_bar5_eq_raddr_3_0_I_108 ( + .I0(cfg_cfg_5072[250]), + .I1(com_cmm_bar5_reg[26]), + .I2(com_cmm_u_cmm_decoder_N_22_9), + .I3(com_cmmt_raddr[58]), + .O(com_cmm_u_cmm_decoder_N_19_9) + ); + defparam com_cmm_u_cmm_decoder_bar5_eq_raddr_3_0_I_99.INIT = 16'h0903; + LUT4 com_cmm_u_cmm_decoder_bar5_eq_raddr_3_0_I_99 ( + .I0(cfg_cfg_5072[230]), + .I1(com_cmm_bar5_reg[6]), + .I2(com_cmm_u_cmm_decoder_N_30_8), + .I3(com_cmmt_raddr[38]), + .O(com_cmm_u_cmm_decoder_N_27_9) + ); + defparam com_cmm_u_cmm_decoder_bar5_eq_raddr_3_0_I_90.INIT = 16'h0903; + LUT4 com_cmm_u_cmm_decoder_bar5_eq_raddr_3_0_I_90 ( + .I0(cfg_cfg_5072[240]), + .I1(com_cmm_bar5_reg[16]), + .I2(com_cmm_u_cmm_decoder_N_38_9), + .I3(com_cmmt_raddr[48]), + .O(com_cmm_u_cmm_decoder_N_35_9) + ); + defparam com_cmm_u_cmm_decoder_bar5_eq_raddr_3_0_I_81.INIT = 16'h0903; + LUT4 com_cmm_u_cmm_decoder_bar5_eq_raddr_3_0_I_81 ( + .I0(cfg_cfg_5072[244]), + .I1(com_cmm_bar5_reg[20]), + .I2(com_cmm_u_cmm_decoder_N_46_9), + .I3(com_cmmt_raddr[52]), + .O(com_cmm_u_cmm_decoder_N_43_9) + ); + defparam com_cmm_u_cmm_decoder_bar5_eq_raddr_3_0_I_72.INIT = 16'h0903; + LUT4 com_cmm_u_cmm_decoder_bar5_eq_raddr_3_0_I_72 ( + .I0(cfg_cfg_5072[242]), + .I1(com_cmm_bar5_reg[18]), + .I2(com_cmm_u_cmm_decoder_N_54_9), + .I3(com_cmmt_raddr[50]), + .O(com_cmm_u_cmm_decoder_N_51_9) + ); + defparam com_cmm_u_cmm_decoder_bar5_eq_raddr_3_0_I_63.INIT = 16'h0903; + LUT4 com_cmm_u_cmm_decoder_bar5_eq_raddr_3_0_I_63 ( + .I0(cfg_cfg_5072[238]), + .I1(com_cmm_bar5_reg[14]), + .I2(com_cmm_u_cmm_decoder_N_62_9), + .I3(com_cmmt_raddr[46]), + .O(com_cmm_u_cmm_decoder_N_59_9) + ); + defparam com_cmm_u_cmm_decoder_bar5_eq_raddr_3_0_I_54.INIT = 16'h0903; + LUT4 com_cmm_u_cmm_decoder_bar5_eq_raddr_3_0_I_54 ( + .I0(cfg_cfg_5072[248]), + .I1(com_cmm_bar5_reg[24]), + .I2(com_cmm_u_cmm_decoder_N_70_9), + .I3(com_cmmt_raddr[56]), + .O(com_cmm_u_cmm_decoder_N_67_9) + ); + defparam com_cmm_u_cmm_decoder_bar5_eq_raddr_3_0_I_45.INIT = 16'h0903; + LUT4 com_cmm_u_cmm_decoder_bar5_eq_raddr_3_0_I_45 ( + .I0(cfg_cfg_5072[236]), + .I1(com_cmm_bar5_reg[12]), + .I2(com_cmm_u_cmm_decoder_N_78_9), + .I3(com_cmmt_raddr[44]), + .O(com_cmm_u_cmm_decoder_N_75_9) + ); + defparam com_cmm_u_cmm_decoder_bar5_eq_raddr_3_0_I_36.INIT = 16'h0903; + LUT4 com_cmm_u_cmm_decoder_bar5_eq_raddr_3_0_I_36 ( + .I0(cfg_cfg_5072[234]), + .I1(com_cmm_bar5_reg[10]), + .I2(com_cmm_u_cmm_decoder_N_86_9), + .I3(com_cmmt_raddr[42]), + .O(com_cmm_u_cmm_decoder_N_83_9) + ); + defparam com_cmm_u_cmm_decoder_bar5_eq_raddr_3_0_I_27.INIT = 16'h0903; + LUT4 com_cmm_u_cmm_decoder_bar5_eq_raddr_3_0_I_27 ( + .I0(cfg_cfg_5072[246]), + .I1(com_cmm_bar5_reg[22]), + .I2(com_cmm_u_cmm_decoder_N_94_9), + .I3(com_cmmt_raddr[54]), + .O(com_cmm_u_cmm_decoder_N_91_9) + ); + defparam com_cmm_u_cmm_decoder_bar5_eq_raddr_3_0_I_18.INIT = 16'h0903; + LUT4 com_cmm_u_cmm_decoder_bar5_eq_raddr_3_0_I_18 ( + .I0(cfg_cfg_5072[254]), + .I1(com_cmm_bar5_reg[30]), + .I2(com_cmm_u_cmm_decoder_N_102_14), + .I3(com_cmmt_raddr[62]), + .O(com_cmm_u_cmm_decoder_N_99_3) + ); + defparam com_cmm_u_cmm_decoder_bar5_eq_raddr_3_0_I_9.INIT = 16'h0903; + LUT4 com_cmm_u_cmm_decoder_bar5_eq_raddr_3_0_I_9 ( + .I0(cfg_cfg_5072[228]), + .I1(com_cmm_bar5_reg[4]), + .I2(com_cmm_u_cmm_decoder_N_110_6), + .I3(com_cmmt_raddr[36]), + .O(com_cmm_u_cmm_decoder_N_107_13) + ); + defparam com_cmm_u_cmm_decoder_bar0_32_hit_nc_3_i_0_0_0.INIT = 16'hC088; + LUT4 com_cmm_u_cmm_decoder_bar0_32_hit_nc_3_i_0_0_0 ( + .I0(com_cmm_u_cmm_decoder_N_44866_i), + .I1(com_cmm_u_cmm_decoder_N_48989_i), + .I2(com_cmm_u_cmm_decoder_bar5_32_hit_nc_3_i_0_0_o3_0_4455), + .I3(cfg_cfg_5072[64]), + .O(com_cmm_u_cmm_decoder_bar0_32_hit_nc_3_i_0_0_0_4458) + ); + defparam com_cmm_u_cmm_decoder_bar4_32_hit_nc_3_i_0_0_0_1.INIT = 16'hCA00; + LUT4 com_cmm_u_cmm_decoder_bar4_32_hit_nc_3_i_0_0_0_1 ( + .I0(com_cmm_u_cmm_decoder_N_44866_i), + .I1(com_cmm_u_cmm_decoder_bar5_32_hit_nc_3_i_0_0_o3_0_4455), + .I2(cfg_cfg_5072[192]), + .I3(com_cmm_u_cmm_decoder_bar4_32_hit_nc_3_i_0_0_0_0_4474), + .O(com_cmm_u_cmm_decoder_bar4_32_hit_nc_3_i_0_0_0_1_4462) + ); + defparam com_cmm_u_cmm_decoder_bar3_32_hit_nc_3_i_0_1.INIT = 16'hCA00; + LUT4 com_cmm_u_cmm_decoder_bar3_32_hit_nc_3_i_0_1 ( + .I0(com_cmm_u_cmm_decoder_N_44866_i), + .I1(com_cmm_u_cmm_decoder_bar5_32_hit_nc_3_i_0_0_o3_0_4455), + .I2(cfg_cfg_5072[160]), + .I3(com_cmm_u_cmm_decoder_bar3_32_hit_nc_3_i_0_0_4475), + .O(com_cmm_u_cmm_decoder_bar3_32_hit_nc_3_i_0_1_4464) + ); + defparam com_cmm_u_cmm_decoder_bar1_32_hit_nc_3_i_0_0_1.INIT = 16'hCA00; + LUT4 com_cmm_u_cmm_decoder_bar1_32_hit_nc_3_i_0_0_1 ( + .I0(com_cmm_u_cmm_decoder_N_44866_i), + .I1(com_cmm_u_cmm_decoder_bar5_32_hit_nc_3_i_0_0_o3_0_4455), + .I2(cfg_cfg_5072[96]), + .I3(com_cmm_u_cmm_decoder_bar1_32_hit_nc_3_i_0_0_0_4476), + .O(com_cmm_u_cmm_decoder_bar1_32_hit_nc_3_i_0_0_1_4468) + ); + defparam com_cmm_u_cmm_decoder_bar2_32_hit_nc_3_i_0_0_1.INIT = 16'hCA00; + LUT4 com_cmm_u_cmm_decoder_bar2_32_hit_nc_3_i_0_0_1 ( + .I0(com_cmm_u_cmm_decoder_N_44866_i), + .I1(com_cmm_u_cmm_decoder_bar5_32_hit_nc_3_i_0_0_o3_0_4455), + .I2(cfg_cfg_5072[128]), + .I3(com_cmm_u_cmm_decoder_bar2_32_hit_nc_3_i_0_0_0_4477), + .O(com_cmm_u_cmm_decoder_bar2_32_hit_nc_3_i_0_0_1_4466) + ); + defparam com_cmm_u_cmm_decoder_bar1_eq_raddr_3_0_I_87.INIT = 8'h6C; + LUT3 com_cmm_u_cmm_decoder_bar1_eq_raddr_3_0_I_87 ( + .I0(cfg_cfg_5072[112]), + .I1(com_cmm_bar1_reg[16]), + .I2(com_cmmt_raddr[48]), + .O(com_cmm_u_cmm_decoder_N_39_1) + ); + defparam com_cmm_u_cmm_decoder_bar2_eq_raddr_3_0_I_87.INIT = 8'h6C; + LUT3 com_cmm_u_cmm_decoder_bar2_eq_raddr_3_0_I_87 ( + .I0(cfg_cfg_5072[144]), + .I1(com_cmm_bar2_reg[16]), + .I2(com_cmmt_raddr[48]), + .O(com_cmm_u_cmm_decoder_N_39_0) + ); + defparam com_cmm_u_cmm_decoder_bar3_eq_raddr_3_0_I_87.INIT = 8'h6C; + LUT3 com_cmm_u_cmm_decoder_bar3_eq_raddr_3_0_I_87 ( + .I0(cfg_cfg_5072[176]), + .I1(com_cmm_bar3_reg[16]), + .I2(com_cmmt_raddr[48]), + .O(com_cmm_u_cmm_decoder_N_39) + ); + defparam com_cmm_u_cmm_decoder_bar4_eq_raddr_3_0_I_41.INIT = 8'h6C; + LUT3 com_cmm_u_cmm_decoder_bar4_eq_raddr_3_0_I_41 ( + .I0(cfg_cfg_5072[205]), + .I1(com_cmm_bar4_reg[13]), + .I2(com_cmmt_raddr[45]), + .O(com_cmm_u_cmm_decoder_N_78) + ); + defparam com_cmm_u_cmm_decoder_bar6_32_hit_nc_3_0_a2_0_a2_0_a2.INIT = 16'h0800; + LUT4_L com_cmm_u_cmm_decoder_bar6_32_hit_nc_3_0_a2_0_a2_0_a2 ( + .I0(com_cmm_u_cmm_decoder_N_44866_i), + .I1(com_cmm_u_cmm_decoder_N_48989_i), + .I2(com_cmm_u_cmm_decoder_un7_bar6_32_hit_nc_6_4456), + .I3(com_cmm_xrom_reg_0_), + .LO(com_cmm_u_cmm_decoder_bar6_32_hit_nc_3) + ); + defparam com_cmm_u_cmm_decoder_bar5_32_hit_nc_3_i_0_0.INIT = 16'h0010; + LUT4_L com_cmm_u_cmm_decoder_bar5_32_hit_nc_3_i_0_0 ( + .I0(com_cmm_u_cmm_decoder_N_44997), + .I1(com_cmm_u_cmm_decoder_N_45436), + .I2(com_cmm_u_cmm_decoder_N_48989_i), + .I3(com_cmm_u_cmm_decoder_un11_bar5_32_hit_nc_7_4469), + .LO(com_cmm_u_cmm_decoder_N_15070_i) + ); + defparam com_cmm_u_cmm_decoder_bar0_32_hit_nc_3_i_0_0.INIT = 16'h0C04; + LUT4_L com_cmm_u_cmm_decoder_bar0_32_hit_nc_3_i_0_0 ( + .I0(com_cmm_u_cmm_decoder_N_45440), + .I1(com_cmm_u_cmm_decoder_bar0_32_hit_nc_3_i_0_0_0_4458), + .I2(com_cmm_u_cmm_decoder_un11_bar0_32_hit_nc_7_4459), + .I3(com_cmm_u_cmm_decoder_un18_bar0_32_hit_nc_7_4457), + .LO(com_cmm_u_cmm_decoder_N_15260_i) + ); + defparam com_cmm_u_cmm_decoder_bar45_64_hit_high_3_0_a2_0_a2_0_a2_0_a2.INIT = 8'h08; + LUT3_L com_cmm_u_cmm_decoder_bar45_64_hit_high_3_0_a2_0_a2_0_a2_0_a2 ( + .I0(com_cmm_u_cmm_decoder_N_45436), + .I1(com_cmm_u_cmm_decoder_I_10), + .I2(com_cmm_u_cmm_decoder_un11_bar34_64_hit_low_7_4470), + .LO(com_cmm_u_cmm_decoder_bar45_64_hit_high_3) + ); + defparam com_cmm_u_cmm_decoder_bar34_64_hit_high_3_0_a2_0_a2.INIT = 8'h08; + LUT3_L com_cmm_u_cmm_decoder_bar34_64_hit_high_3_0_a2_0_a2 ( + .I0(com_cmm_u_cmm_decoder_N_49545), + .I1(com_cmm_u_cmm_decoder_I_10_0), + .I2(com_cmm_u_cmm_decoder_un11_bar3_32_hit_nc_7_4471), + .LO(com_cmm_u_cmm_decoder_bar34_64_hit_high_3) + ); + defparam com_cmm_u_cmm_decoder_bar23_64_hit_high_3_0_a2_0_a2_0_a2.INIT = 8'h08; + LUT3_L com_cmm_u_cmm_decoder_bar23_64_hit_high_3_0_a2_0_a2_0_a2 ( + .I0(com_cmm_u_cmm_decoder_N_45577), + .I1(com_cmm_u_cmm_decoder_I_10_1), + .I2(com_cmm_u_cmm_decoder_un11_bar2_32_hit_nc_7_4472), + .LO(com_cmm_u_cmm_decoder_bar23_64_hit_high_3) + ); + defparam com_cmm_u_cmm_decoder_bar12_64_hit_high_3_0_a2_0_a2_0_a2.INIT = 8'h08; + LUT3_L com_cmm_u_cmm_decoder_bar12_64_hit_high_3_0_a2_0_a2_0_a2 ( + .I0(com_cmm_u_cmm_decoder_N_45442), + .I1(com_cmm_u_cmm_decoder_I_10_2), + .I2(com_cmm_u_cmm_decoder_un11_bar1_32_hit_nc_7_4473), + .LO(com_cmm_u_cmm_decoder_bar12_64_hit_high_3) + ); + defparam com_cmm_u_cmm_decoder_bar01_64_hit_high_3_0_a2_0_a2_0_a2.INIT = 8'h08; + LUT3_L com_cmm_u_cmm_decoder_bar01_64_hit_high_3_0_a2_0_a2_0_a2 ( + .I0(com_cmm_u_cmm_decoder_N_45440), + .I1(com_cmm_u_cmm_decoder_I_10_3), + .I2(com_cmm_u_cmm_decoder_un11_bar0_32_hit_nc_7_4459), + .LO(com_cmm_u_cmm_decoder_bar01_64_hit_high_3) + ); + defparam com_cmm_u_cmm_decoder_bar4_32_hit_nc_3_i_0_0_0.INIT = 16'h0C04; + LUT4_L com_cmm_u_cmm_decoder_bar4_32_hit_nc_3_i_0_0_0 ( + .I0(com_cmm_u_cmm_decoder_N_45436), + .I1(com_cmm_u_cmm_decoder_bar4_32_hit_nc_3_i_0_0_0_1_4462), + .I2(com_cmm_u_cmm_decoder_un11_bar4_32_hit_nc_8_4461), + .I3(com_cmm_u_cmm_decoder_un18_bar4_32_hit_nc_7_4460), + .LO(com_cmm_u_cmm_decoder_N_15075_i) + ); + defparam com_cmm_u_cmm_decoder_bar3_32_hit_nc_3_i_0.INIT = 16'h0C04; + LUT4_L com_cmm_u_cmm_decoder_bar3_32_hit_nc_3_i_0 ( + .I0(com_cmm_u_cmm_decoder_N_49545), + .I1(com_cmm_u_cmm_decoder_bar3_32_hit_nc_3_i_0_1_4464), + .I2(com_cmm_u_cmm_decoder_un11_bar3_32_hit_nc_7_4471), + .I3(com_cmm_u_cmm_decoder_un18_bar3_32_hit_nc_7_4463), + .LO(com_cmm_u_cmm_decoder_N_28971_i) + ); + defparam com_cmm_u_cmm_decoder_bar2_32_hit_nc_3_i_0_0.INIT = 16'h0C04; + LUT4_L com_cmm_u_cmm_decoder_bar2_32_hit_nc_3_i_0_0 ( + .I0(com_cmm_u_cmm_decoder_N_45577), + .I1(com_cmm_u_cmm_decoder_bar2_32_hit_nc_3_i_0_0_1_4466), + .I2(com_cmm_u_cmm_decoder_un11_bar2_32_hit_nc_7_4472), + .I3(com_cmm_u_cmm_decoder_un18_bar2_32_hit_nc_7_4465), + .LO(com_cmm_u_cmm_decoder_N_15266_i) + ); + defparam com_cmm_u_cmm_decoder_bar1_32_hit_nc_3_i_0_0.INIT = 16'h0C04; + LUT4_L com_cmm_u_cmm_decoder_bar1_32_hit_nc_3_i_0_0 ( + .I0(com_cmm_u_cmm_decoder_N_45442), + .I1(com_cmm_u_cmm_decoder_bar1_32_hit_nc_3_i_0_0_1_4468), + .I2(com_cmm_u_cmm_decoder_un11_bar1_32_hit_nc_7_4473), + .I3(com_cmm_u_cmm_decoder_un18_bar1_32_hit_nc_7_4467), + .LO(com_cmm_u_cmm_decoder_N_15264_i) + ); + defparam com_cmm_u_cmm_decoder_bar45_64_hit_low_3_0_a2_0_a2_0_a2.INIT = 8'h08; + LUT3_L com_cmm_u_cmm_decoder_bar45_64_hit_low_3_0_a2_0_a2_0_a2 ( + .I0(com_cmm_u_cmm_decoder_bar23_64_hit_low_3_0_a2_0_a2_0), + .I1(com_cmm_u_cmm_decoder_I_28_1), + .I2(com_cmm_u_cmm_decoder_un11_bar5_32_hit_nc_7_4469), + .LO(com_cmm_u_cmm_decoder_bar45_64_hit_low_3) + ); + defparam com_cmm_u_cmm_decoder_bar34_64_hit_low_3_0_a2_0_a2_0_a2.INIT = 8'h08; + LUT3_L com_cmm_u_cmm_decoder_bar34_64_hit_low_3_0_a2_0_a2_0_a2 ( + .I0(com_cmm_u_cmm_decoder_bar23_64_hit_low_3_0_a2_0_a2_0), + .I1(com_cmm_u_cmm_decoder_I_28_2), + .I2(com_cmm_u_cmm_decoder_un11_bar34_64_hit_low_7_4470), + .LO(com_cmm_u_cmm_decoder_bar34_64_hit_low_3) + ); + defparam com_cmm_u_cmm_decoder_bar23_64_hit_low_3_0_a2_0_a2.INIT = 8'h08; + LUT3_L com_cmm_u_cmm_decoder_bar23_64_hit_low_3_0_a2_0_a2 ( + .I0(com_cmm_u_cmm_decoder_bar23_64_hit_low_3_0_a2_0_a2_0), + .I1(com_cmm_u_cmm_decoder_I_28_3), + .I2(com_cmm_u_cmm_decoder_un11_bar3_32_hit_nc_7_4471), + .LO(com_cmm_u_cmm_decoder_bar23_64_hit_low_3) + ); + defparam com_cmm_u_cmm_decoder_bar12_64_hit_low_3_0_a2_0_a2_0_a2.INIT = 8'h08; + LUT3_L com_cmm_u_cmm_decoder_bar12_64_hit_low_3_0_a2_0_a2_0_a2 ( + .I0(com_cmm_u_cmm_decoder_bar23_64_hit_low_3_0_a2_0_a2_0), + .I1(com_cmm_u_cmm_decoder_I_28_4), + .I2(com_cmm_u_cmm_decoder_un11_bar2_32_hit_nc_7_4472), + .LO(com_cmm_u_cmm_decoder_bar12_64_hit_low_3) + ); + defparam com_cmm_u_cmm_decoder_bar01_64_hit_low_3_0_a2_0_a2_0_a2.INIT = 8'h08; + LUT3_L com_cmm_u_cmm_decoder_bar01_64_hit_low_3_0_a2_0_a2_0_a2 ( + .I0(com_cmm_u_cmm_decoder_bar23_64_hit_low_3_0_a2_0_a2_0), + .I1(com_cmm_u_cmm_decoder_I_28_5), + .I2(com_cmm_u_cmm_decoder_un11_bar1_32_hit_nc_7_4473), + .LO(com_cmm_u_cmm_decoder_bar01_64_hit_low_3) + ); + defparam com_cmm_u_cmm_decoder_bar6_32_hit.INIT = 4'h8; + LUT2_L com_cmm_u_cmm_decoder_bar6_32_hit ( + .I0(com_cmm_u_cmm_decoder_bar6_32_hit_nc_4483), + .I1(com_cmm_u_cmm_decoder_bar6_eq_raddr_4485), + .LO(com_cmm_u_cmm_decoder_bar6_32_hit_4503) + ); + defparam com_cmm_u_cmm_decoder_N_15042_i.INIT = 16'hF888; + LUT4_L com_cmm_u_cmm_decoder_N_15042_i ( + .I0(com_cmm_u_cmm_decoder_bar5_32_hit_nc_4484), + .I1(com_cmm_u_cmm_decoder_bar5_eq_raddr_4486), + .I2(com_cmm_u_cmm_decoder_bar45_64_hit_high_4489), + .I3(com_cmm_u_cmm_decoder_bar45_64_hit_low_4498), + .LO(com_cmm_u_cmm_decoder_N_15042_i_4504) + ); + defparam com_cmm_u_cmm_decoder_N_15043_i.INIT = 8'h8F; + LUT3_L com_cmm_u_cmm_decoder_N_15043_i ( + .I0(com_cmm_u_cmm_decoder_bar34_64_hit_high_4490), + .I1(com_cmm_u_cmm_decoder_bar34_64_hit_low_4499), + .I2(com_cmm_u_cmm_decoder_bar_hit_7_0_a2_0[4]), + .LO(com_cmm_u_cmm_decoder_N_15043_i_4505) + ); + defparam com_cmm_u_cmm_decoder_N_15044_i.INIT = 8'h8F; + LUT3_L com_cmm_u_cmm_decoder_N_15044_i ( + .I0(com_cmm_u_cmm_decoder_bar23_64_hit_high_4491), + .I1(com_cmm_u_cmm_decoder_bar23_64_hit_low_4500), + .I2(com_cmm_u_cmm_decoder_bar_hit_6_0_a2_0[3]), + .LO(com_cmm_u_cmm_decoder_N_15044_i_4506) + ); + defparam com_cmm_u_cmm_decoder_N_15045_i.INIT = 8'h8F; + LUT3_L com_cmm_u_cmm_decoder_N_15045_i ( + .I0(com_cmm_u_cmm_decoder_bar12_64_hit_high_4492), + .I1(com_cmm_u_cmm_decoder_bar12_64_hit_low_4501), + .I2(com_cmm_u_cmm_decoder_bar_hit_5_0_a2_0[2]), + .LO(com_cmm_u_cmm_decoder_N_15045_i_4507) + ); + defparam com_cmm_u_cmm_decoder_N_15046_i.INIT = 8'h8F; + LUT3_L com_cmm_u_cmm_decoder_N_15046_i ( + .I0(com_cmm_u_cmm_decoder_bar01_64_hit_high_4493), + .I1(com_cmm_u_cmm_decoder_bar01_64_hit_low_4502), + .I2(com_cmm_u_cmm_decoder_bar_hit_4_0_a2_0[1]), + .LO(com_cmm_u_cmm_decoder_N_15046_i_4508) + ); + defparam com_cmm_u_cmm_decoder_N_15047_i.INIT = 16'hF888; + LUT4_L com_cmm_u_cmm_decoder_N_15047_i ( + .I0(com_cmm_u_cmm_decoder_bar01_64_hit_high_4493), + .I1(com_cmm_u_cmm_decoder_bar01_64_hit_low_4502), + .I2(com_cmm_u_cmm_decoder_bar0_32_hit_nc_4488), + .I3(com_cmm_u_cmm_decoder_bar0_eq_raddr_4482), + .LO(com_cmm_u_cmm_decoder_N_15047_i_4509) + ); + defparam com_cmm_u_cmm_decoder_bar4_32_hit_nc_3_i_0_0_0_0.INIT = 8'h01; + LUT3_L com_cmm_u_cmm_decoder_bar4_32_hit_nc_3_i_0_0_0_0 ( + .I0(com_cmm_u_cmm_decoder_N_49545), + .I1(com_cmm_pme_pmcsr[1]), + .I2(com_cmm_pme_pmcsr[0]), + .LO(com_cmm_u_cmm_decoder_bar4_32_hit_nc_3_i_0_0_0_0_4474) + ); + defparam com_cmm_u_cmm_decoder_bar3_32_hit_nc_3_i_0_0.INIT = 8'h01; + LUT3_L com_cmm_u_cmm_decoder_bar3_32_hit_nc_3_i_0_0 ( + .I0(com_cmm_u_cmm_decoder_N_45577), + .I1(com_cmm_pme_pmcsr[1]), + .I2(com_cmm_pme_pmcsr[0]), + .LO(com_cmm_u_cmm_decoder_bar3_32_hit_nc_3_i_0_0_4475) + ); + defparam com_cmm_u_cmm_decoder_bar1_32_hit_nc_3_i_0_0_0.INIT = 8'h01; + LUT3_L com_cmm_u_cmm_decoder_bar1_32_hit_nc_3_i_0_0_0 ( + .I0(com_cmm_u_cmm_decoder_N_45440), + .I1(com_cmm_pme_pmcsr[1]), + .I2(com_cmm_pme_pmcsr[0]), + .LO(com_cmm_u_cmm_decoder_bar1_32_hit_nc_3_i_0_0_0_4476) + ); + defparam com_cmm_u_cmm_decoder_bar2_32_hit_nc_3_i_0_0_0.INIT = 8'h01; + LUT3_L com_cmm_u_cmm_decoder_bar2_32_hit_nc_3_i_0_0_0 ( + .I0(com_cmm_u_cmm_decoder_N_45442), + .I1(com_cmm_pme_pmcsr[1]), + .I2(com_cmm_pme_pmcsr[0]), + .LO(com_cmm_u_cmm_decoder_bar2_32_hit_nc_3_i_0_0_0_4477) + ); + defparam com_cmm_u_cmm_decoder_bar34_64_hit_high_3_0_a2_0_a2_0.INIT = 8'h02; + LUT3 com_cmm_u_cmm_decoder_bar34_64_hit_high_3_0_a2_0_a2_0 ( + .I0(com_cmm_bar3_reg[2]), + .I1(com_cmm_bar3_reg[1]), + .I2(com_cmm_bar3_reg[0]), + .O(com_cmm_u_cmm_decoder_N_49545) + ); + defparam com_cmm_u_cmm_decoder_bar23_64_hit_high_3_0_a2_0_a2_0_a2_0.INIT = 8'h02; + LUT3 com_cmm_u_cmm_decoder_bar23_64_hit_high_3_0_a2_0_a2_0_a2_0 ( + .I0(com_cmm_bar2_reg[2]), + .I1(com_cmm_bar2_reg[1]), + .I2(com_cmm_bar2_reg[0]), + .O(com_cmm_u_cmm_decoder_N_45577) + ); + defparam com_cmm_u_cmm_decoder_bar12_64_hit_high_3_0_a2_0_a2_0_a2_0.INIT = 8'h02; + LUT3 com_cmm_u_cmm_decoder_bar12_64_hit_high_3_0_a2_0_a2_0_a2_0 ( + .I0(com_cmm_bar1_reg[2]), + .I1(com_cmm_bar1_reg[1]), + .I2(com_cmm_bar1_reg[0]), + .O(com_cmm_u_cmm_decoder_N_45442) + ); + MUXCY com_cmm_u_cmm_decoder_un9_bar34_64_hit_high_0_I_10 ( + .CI(com_cmm_u_cmm_decoder_data_tmp_9[12]), + .DI(com_cmm_u_cmm_decoder_GND_4478), + .O(com_cmm_u_cmm_decoder_I_10_0), + .S(com_cmm_u_cmm_decoder_N_99) + ); + MUXCY com_cmm_u_cmm_decoder_un9_bar23_64_hit_high_0_I_10 ( + .CI(com_cmm_u_cmm_decoder_data_tmp_8[12]), + .DI(com_cmm_u_cmm_decoder_GND_4478), + .O(com_cmm_u_cmm_decoder_I_10_1), + .S(com_cmm_u_cmm_decoder_N_99_0) + ); + MUXCY com_cmm_u_cmm_decoder_un9_bar12_64_hit_high_0_I_10 ( + .CI(com_cmm_u_cmm_decoder_data_tmp_7[12]), + .DI(com_cmm_u_cmm_decoder_GND_4478), + .O(com_cmm_u_cmm_decoder_I_10_2), + .S(com_cmm_u_cmm_decoder_N_99_1) + ); + MUXCY com_cmm_u_cmm_decoder_un9_bar01_64_hit_high_0_I_10 ( + .CI(com_cmm_u_cmm_decoder_data_tmp_6[12]), + .DI(com_cmm_u_cmm_decoder_GND_4478), + .O(com_cmm_u_cmm_decoder_I_10_3), + .S(com_cmm_u_cmm_decoder_N_99_2) + ); + MUXCY com_cmm_u_cmm_decoder_bar6_eq_raddr_3_0_I_91 ( + .CI(com_cmm_u_cmm_decoder_data_tmp[9]), + .DI(com_cmm_u_cmm_decoder_GND_4478), + .O(com_cmm_u_cmm_decoder_bar6_eq_raddr_3), + .S(com_cmm_u_cmm_decoder_N_7_i) + ); + MUXCY com_cmm_u_cmm_decoder_bar5_eq_raddr_3_0_I_10 ( + .CI(com_cmm_u_cmm_decoder_data_tmp_5[12]), + .DI(com_cmm_u_cmm_decoder_GND_4478), + .O(com_cmm_u_cmm_decoder_bar5_eq_raddr_3), + .S(com_cmm_u_cmm_decoder_I_10_sf) + ); + MUXCY com_cmm_u_cmm_decoder_bar4_eq_raddr_3_0_I_10 ( + .CI(com_cmm_u_cmm_decoder_data_tmp_4[12]), + .DI(com_cmm_u_cmm_decoder_GND_4478), + .O(com_cmm_u_cmm_decoder_bar4_eq_raddr_3), + .S(com_cmm_u_cmm_decoder_N_99_4) + ); + MUXCY com_cmm_u_cmm_decoder_bar3_eq_raddr_3_0_I_10 ( + .CI(com_cmm_u_cmm_decoder_data_tmp_3[12]), + .DI(com_cmm_u_cmm_decoder_GND_4478), + .O(com_cmm_u_cmm_decoder_bar3_eq_raddr_3), + .S(com_cmm_u_cmm_decoder_N_99_5) + ); + MUXCY com_cmm_u_cmm_decoder_bar2_eq_raddr_3_0_I_10 ( + .CI(com_cmm_u_cmm_decoder_data_tmp_2[12]), + .DI(com_cmm_u_cmm_decoder_GND_4478), + .O(com_cmm_u_cmm_decoder_bar2_eq_raddr_3), + .S(com_cmm_u_cmm_decoder_N_99_6) + ); + MUXCY com_cmm_u_cmm_decoder_bar1_eq_raddr_3_0_I_10 ( + .CI(com_cmm_u_cmm_decoder_data_tmp_1[12]), + .DI(com_cmm_u_cmm_decoder_GND_4478), + .O(com_cmm_u_cmm_decoder_bar1_eq_raddr_3), + .S(com_cmm_u_cmm_decoder_N_99_7) + ); + MUXCY com_cmm_u_cmm_decoder_bar0_eq_raddr_3_0_I_10 ( + .CI(com_cmm_u_cmm_decoder_data_tmp_0[12]), + .DI(com_cmm_u_cmm_decoder_GND_4478), + .O(com_cmm_u_cmm_decoder_bar0_eq_raddr_3), + .S(com_cmm_u_cmm_decoder_N_99_8) + ); + MUXCY com_cmm_u_cmm_decoder_un9_bar45_64_hit_high_0_I_10 ( + .CI(com_cmm_u_cmm_decoder_data_tmp[12]), + .DI(com_cmm_u_cmm_decoder_GND_4478), + .O(com_cmm_u_cmm_decoder_I_10), + .S(com_cmm_u_cmm_decoder_N_99_9) + ); + MUXCY com_cmm_u_cmm_decoder_un10_bar01_64_hit_low_0_I_28 ( + .CI(com_cmm_u_cmm_decoder_data_tmp_3[14]), + .DI(com_cmm_u_cmm_decoder_GND_4478), + .O(com_cmm_u_cmm_decoder_I_28_5), + .S(com_cmm_u_cmm_decoder_N_99_10) + ); + MUXCY com_cmm_u_cmm_decoder_un10_bar12_64_hit_low_0_I_28 ( + .CI(com_cmm_u_cmm_decoder_data_tmp_2[14]), + .DI(com_cmm_u_cmm_decoder_GND_4478), + .O(com_cmm_u_cmm_decoder_I_28_4), + .S(com_cmm_u_cmm_decoder_N_99_11) + ); + MUXCY com_cmm_u_cmm_decoder_un10_bar23_64_hit_low_0_I_28 ( + .CI(com_cmm_u_cmm_decoder_data_tmp_1[14]), + .DI(com_cmm_u_cmm_decoder_GND_4478), + .O(com_cmm_u_cmm_decoder_I_28_3), + .S(com_cmm_u_cmm_decoder_N_99_12) + ); + MUXCY com_cmm_u_cmm_decoder_un10_bar34_64_hit_low_0_I_28 ( + .CI(com_cmm_u_cmm_decoder_data_tmp_0[14]), + .DI(com_cmm_u_cmm_decoder_GND_4478), + .O(com_cmm_u_cmm_decoder_I_28_2), + .S(com_cmm_u_cmm_decoder_N_99_13) + ); + MUXCY com_cmm_u_cmm_decoder_un10_bar45_64_hit_low_0_I_28 ( + .CI(com_cmm_u_cmm_decoder_data_tmp[14]), + .DI(com_cmm_u_cmm_decoder_GND_4478), + .O(com_cmm_u_cmm_decoder_I_28_1), + .S(com_cmm_u_cmm_decoder_N_99_14) + ); + FDC com_cmm_u_cmm_decoder_bar3_eq_raddr ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_decoder_bar3_eq_raddr_3), + .Q(com_cmm_u_cmm_decoder_bar3_eq_raddr_4479), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_decoder_bar2_eq_raddr ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_decoder_bar2_eq_raddr_3), + .Q(com_cmm_u_cmm_decoder_bar2_eq_raddr_4480), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_decoder_bar1_eq_raddr ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_decoder_bar1_eq_raddr_3), + .Q(com_cmm_u_cmm_decoder_bar1_eq_raddr_4481), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_decoder_bar0_eq_raddr ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_decoder_bar0_eq_raddr_3), + .Q(com_cmm_u_cmm_decoder_bar0_eq_raddr_4482), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_decoder_bar6_32_hit_nc ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_decoder_bar6_32_hit_nc_3), + .Q(com_cmm_u_cmm_decoder_bar6_32_hit_nc_4483), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_decoder_bar5_32_hit_nc ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_decoder_N_15070_i), + .Q(com_cmm_u_cmm_decoder_bar5_32_hit_nc_4484), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_decoder_bar6_eq_raddr ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_decoder_bar6_eq_raddr_3), + .Q(com_cmm_u_cmm_decoder_bar6_eq_raddr_4485), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_decoder_bar5_eq_raddr ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_decoder_bar5_eq_raddr_3), + .Q(com_cmm_u_cmm_decoder_bar5_eq_raddr_4486), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_decoder_bar4_eq_raddr ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_decoder_bar4_eq_raddr_3), + .Q(com_cmm_u_cmm_decoder_bar4_eq_raddr_4487), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_decoder_bar0_32_hit_nc ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_decoder_N_15260_i), + .Q(com_cmm_u_cmm_decoder_bar0_32_hit_nc_4488), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_decoder_bar45_64_hit_high ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_decoder_bar45_64_hit_high_3), + .Q(com_cmm_u_cmm_decoder_bar45_64_hit_high_4489), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_decoder_bar34_64_hit_high ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_decoder_bar34_64_hit_high_3), + .Q(com_cmm_u_cmm_decoder_bar34_64_hit_high_4490), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_decoder_bar23_64_hit_high ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_decoder_bar23_64_hit_high_3), + .Q(com_cmm_u_cmm_decoder_bar23_64_hit_high_4491), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_decoder_bar12_64_hit_high ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_decoder_bar12_64_hit_high_3), + .Q(com_cmm_u_cmm_decoder_bar12_64_hit_high_4492), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_decoder_bar01_64_hit_high ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_decoder_bar01_64_hit_high_3), + .Q(com_cmm_u_cmm_decoder_bar01_64_hit_high_4493), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_decoder_bar4_32_hit_nc ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_decoder_N_15075_i), + .Q(com_cmm_u_cmm_decoder_bar4_32_hit_nc_4494), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_decoder_bar3_32_hit_nc ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_decoder_N_28971_i), + .Q(com_cmm_u_cmm_decoder_bar3_32_hit_nc_4495), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_decoder_bar2_32_hit_nc ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_decoder_N_15266_i), + .Q(com_cmm_u_cmm_decoder_bar2_32_hit_nc_4496), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_decoder_bar1_32_hit_nc ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_decoder_N_15264_i), + .Q(com_cmm_u_cmm_decoder_bar1_32_hit_nc_4497), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_decoder_bar45_64_hit_low ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_decoder_bar45_64_hit_low_3), + .Q(com_cmm_u_cmm_decoder_bar45_64_hit_low_4498), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_decoder_bar34_64_hit_low ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_decoder_bar34_64_hit_low_3), + .Q(com_cmm_u_cmm_decoder_bar34_64_hit_low_4499), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_decoder_bar23_64_hit_low ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_decoder_bar23_64_hit_low_3), + .Q(com_cmm_u_cmm_decoder_bar23_64_hit_low_4500), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_decoder_bar12_64_hit_low ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_decoder_bar12_64_hit_low_3), + .Q(com_cmm_u_cmm_decoder_bar12_64_hit_low_4501), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_decoder_bar01_64_hit_low ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_decoder_bar01_64_hit_low_3), + .Q(com_cmm_u_cmm_decoder_bar01_64_hit_low_4502), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_decoder_bar_hit_6_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_decoder_bar6_32_hit_4503), + .Q(com_cmmt_rbar_hit[6]), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_decoder_bar_hit_5_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_decoder_N_15042_i_4504), + .Q(com_cmmt_rbar_hit[5]), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_decoder_bar_hit_4_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_decoder_N_15043_i_4505), + .Q(com_cmmt_rbar_hit[4]), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_decoder_bar_hit_3_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_decoder_N_15044_i_4506), + .Q(com_cmmt_rbar_hit[3]), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_decoder_bar_hit_2_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_decoder_N_15045_i_4507), + .Q(com_cmmt_rbar_hit[2]), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_decoder_bar_hit_1_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_decoder_N_15046_i_4508), + .Q(com_cmmt_rbar_hit[1]), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_decoder_bar_hit_0_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_decoder_N_15047_i_4509), + .Q(com_cmmt_rbar_hit[0]), + .CLR(com_cmm_rst_267) + ); + defparam com_cmm_u_cmm_decoder_un10_bar45_64_hit_low_0_I_36.INIT = 16'h0903; + LUT4 com_cmm_u_cmm_decoder_un10_bar45_64_hit_low_0_I_36 ( + .I0(cfg_cfg_5072[227]), + .I1(com_cmm_bar5_reg[3]), + .I2(com_cmm_u_cmm_decoder_N_102_13), + .I3(com_cmmt_raddr[35]), + .O(com_cmm_u_cmm_decoder_N_99_14) + ); + defparam com_cmm_u_cmm_decoder_un10_bar34_64_hit_low_0_I_36.INIT = 16'h0903; + LUT4 com_cmm_u_cmm_decoder_un10_bar34_64_hit_low_0_I_36 ( + .I0(cfg_cfg_5072[194]), + .I1(com_cmm_bar4_reg[2]), + .I2(com_cmm_u_cmm_decoder_N_102_12), + .I3(com_cmmt_raddr[34]), + .O(com_cmm_u_cmm_decoder_N_99_13) + ); + defparam com_cmm_u_cmm_decoder_un10_bar23_64_hit_low_0_I_36.INIT = 16'h0903; + LUT4 com_cmm_u_cmm_decoder_un10_bar23_64_hit_low_0_I_36 ( + .I0(cfg_cfg_5072[162]), + .I1(com_cmm_bar3_reg[2]), + .I2(com_cmm_u_cmm_decoder_N_102_11), + .I3(com_cmmt_raddr[34]), + .O(com_cmm_u_cmm_decoder_N_99_12) + ); + defparam com_cmm_u_cmm_decoder_un10_bar12_64_hit_low_0_I_36.INIT = 16'h0903; + LUT4 com_cmm_u_cmm_decoder_un10_bar12_64_hit_low_0_I_36 ( + .I0(cfg_cfg_5072[130]), + .I1(com_cmm_bar2_reg[2]), + .I2(com_cmm_u_cmm_decoder_N_102_10), + .I3(com_cmmt_raddr[34]), + .O(com_cmm_u_cmm_decoder_N_99_11) + ); + defparam com_cmm_u_cmm_decoder_un10_bar01_64_hit_low_0_I_36.INIT = 16'h0903; + LUT4 com_cmm_u_cmm_decoder_un10_bar01_64_hit_low_0_I_36 ( + .I0(cfg_cfg_5072[98]), + .I1(com_cmm_bar1_reg[2]), + .I2(com_cmm_u_cmm_decoder_N_102_9), + .I3(com_cmmt_raddr[34]), + .O(com_cmm_u_cmm_decoder_N_99_10) + ); + defparam com_cmm_u_cmm_decoder_un9_bar45_64_hit_high_0_I_18.INIT = 16'h0903; + LUT4 com_cmm_u_cmm_decoder_un9_bar45_64_hit_high_0_I_18 ( + .I0(cfg_cfg_5072[222]), + .I1(com_cmm_bar4_reg[30]), + .I2(com_cmm_u_cmm_decoder_N_102_8), + .I3(com_cmmt_raddr[30]), + .O(com_cmm_u_cmm_decoder_N_99_9) + ); + defparam com_cmm_u_cmm_decoder_bar0_eq_raddr_3_0_I_18.INIT = 16'h0903; + LUT4 com_cmm_u_cmm_decoder_bar0_eq_raddr_3_0_I_18 ( + .I0(cfg_cfg_5072[94]), + .I1(com_cmm_bar0_reg_30_), + .I2(com_cmm_u_cmm_decoder_N_102_7), + .I3(com_cmmt_raddr[62]), + .O(com_cmm_u_cmm_decoder_N_99_8) + ); + defparam com_cmm_u_cmm_decoder_bar1_eq_raddr_3_0_I_18.INIT = 16'h0903; + LUT4 com_cmm_u_cmm_decoder_bar1_eq_raddr_3_0_I_18 ( + .I0(cfg_cfg_5072[126]), + .I1(com_cmm_bar1_reg[30]), + .I2(com_cmm_u_cmm_decoder_N_102_2), + .I3(com_cmmt_raddr[62]), + .O(com_cmm_u_cmm_decoder_N_99_7) + ); + defparam com_cmm_u_cmm_decoder_bar2_eq_raddr_3_0_I_18.INIT = 16'h0903; + LUT4 com_cmm_u_cmm_decoder_bar2_eq_raddr_3_0_I_18 ( + .I0(cfg_cfg_5072[158]), + .I1(com_cmm_bar2_reg[30]), + .I2(com_cmm_u_cmm_decoder_N_102_1), + .I3(com_cmmt_raddr[62]), + .O(com_cmm_u_cmm_decoder_N_99_6) + ); + defparam com_cmm_u_cmm_decoder_bar3_eq_raddr_3_0_I_18.INIT = 16'h0903; + LUT4 com_cmm_u_cmm_decoder_bar3_eq_raddr_3_0_I_18 ( + .I0(cfg_cfg_5072[190]), + .I1(com_cmm_bar3_reg[30]), + .I2(com_cmm_u_cmm_decoder_N_102_0), + .I3(com_cmmt_raddr[62]), + .O(com_cmm_u_cmm_decoder_N_99_5) + ); + defparam com_cmm_u_cmm_decoder_bar4_eq_raddr_3_0_I_18.INIT = 16'h0903; + LUT4 com_cmm_u_cmm_decoder_bar4_eq_raddr_3_0_I_18 ( + .I0(cfg_cfg_5072[222]), + .I1(com_cmm_bar4_reg[30]), + .I2(com_cmm_u_cmm_decoder_N_102), + .I3(com_cmmt_raddr[62]), + .O(com_cmm_u_cmm_decoder_N_99_4) + ); + defparam com_cmm_u_cmm_decoder_bar5_eq_raddr_3_0_I_10_sf.INIT = 4'h2; + LUT1 com_cmm_u_cmm_decoder_bar5_eq_raddr_3_0_I_10_sf ( + .I0(com_cmm_u_cmm_decoder_N_99_3), + .O(com_cmm_u_cmm_decoder_I_10_sf) + ); + defparam com_cmm_u_cmm_decoder_bar6_eq_raddr_3_0_N_7_i.INIT = 8'h93; + LUT3 com_cmm_u_cmm_decoder_bar6_eq_raddr_3_0_N_7_i ( + .I0(cfg_cfg_5072[351]), + .I1(com_cmm_xrom_reg_31_), + .I2(com_cmmt_raddr[63]), + .O(com_cmm_u_cmm_decoder_N_7_i) + ); + defparam com_cmm_u_cmm_decoder_un9_bar01_64_hit_high_0_I_18.INIT = 16'h0903; + LUT4 com_cmm_u_cmm_decoder_un9_bar01_64_hit_high_0_I_18 ( + .I0(cfg_cfg_5072[94]), + .I1(com_cmm_bar0_reg_30_), + .I2(com_cmm_u_cmm_decoder_N_102_6), + .I3(com_cmmt_raddr[30]), + .O(com_cmm_u_cmm_decoder_N_99_2) + ); + defparam com_cmm_u_cmm_decoder_un9_bar12_64_hit_high_0_I_18.INIT = 16'h0903; + LUT4 com_cmm_u_cmm_decoder_un9_bar12_64_hit_high_0_I_18 ( + .I0(cfg_cfg_5072[126]), + .I1(com_cmm_bar1_reg[30]), + .I2(com_cmm_u_cmm_decoder_N_102_5), + .I3(com_cmmt_raddr[30]), + .O(com_cmm_u_cmm_decoder_N_99_1) + ); + defparam com_cmm_u_cmm_decoder_un9_bar23_64_hit_high_0_I_18.INIT = 16'h0903; + LUT4 com_cmm_u_cmm_decoder_un9_bar23_64_hit_high_0_I_18 ( + .I0(cfg_cfg_5072[158]), + .I1(com_cmm_bar2_reg[30]), + .I2(com_cmm_u_cmm_decoder_N_102_4), + .I3(com_cmmt_raddr[30]), + .O(com_cmm_u_cmm_decoder_N_99_0) + ); + defparam com_cmm_u_cmm_decoder_un9_bar34_64_hit_high_0_I_18.INIT = 16'h0903; + LUT4 com_cmm_u_cmm_decoder_un9_bar34_64_hit_high_0_I_18 ( + .I0(cfg_cfg_5072[190]), + .I1(com_cmm_bar3_reg[30]), + .I2(com_cmm_u_cmm_decoder_N_102_3), + .I3(com_cmmt_raddr[30]), + .O(com_cmm_u_cmm_decoder_N_99) + ); + defparam com_cmm_u_cmm_decoder_un7_bar6_32_hit_nc_5_and_0_a2_0_a2_0_a2.INIT = 16'h0001; + LUT4 com_cmm_u_cmm_decoder_un7_bar6_32_hit_nc_5_and_0_a2_0_a2_0_a2 ( + .I0(cfg_cfg_5072[347]), + .I1(cfg_cfg_5072[348]), + .I2(cfg_cfg_5072[349]), + .I3(cfg_cfg_5072[350]), + .O(com_cmm_u_cmm_decoder_un7_bar6_32_hit_nc_5_and) + ); + defparam com_cmm_u_cmm_decoder_un7_bar6_32_hit_nc_4_and_0_a2_0_a2_0_a2.INIT = 16'h0001; + LUT4 com_cmm_u_cmm_decoder_un7_bar6_32_hit_nc_4_and_0_a2_0_a2_0_a2 ( + .I0(cfg_cfg_5072[343]), + .I1(cfg_cfg_5072[344]), + .I2(cfg_cfg_5072[345]), + .I3(cfg_cfg_5072[346]), + .O(com_cmm_u_cmm_decoder_un7_bar6_32_hit_nc_4_and) + ); + defparam com_cmm_u_cmm_decoder_un7_bar6_32_hit_nc_3_and_0_a2_0_a2_0_a2.INIT = 16'h0001; + LUT4 com_cmm_u_cmm_decoder_un7_bar6_32_hit_nc_3_and_0_a2_0_a2_0_a2 ( + .I0(cfg_cfg_5072[339]), + .I1(cfg_cfg_5072[340]), + .I2(cfg_cfg_5072[341]), + .I3(cfg_cfg_5072[342]), + .O(com_cmm_u_cmm_decoder_un7_bar6_32_hit_nc_3_and) + ); + defparam com_cmm_u_cmm_decoder_un7_bar6_32_hit_nc_2_and_0_a2_0_a2_0_a2.INIT = 16'h0001; + LUT4 com_cmm_u_cmm_decoder_un7_bar6_32_hit_nc_2_and_0_a2_0_a2_0_a2 ( + .I0(cfg_cfg_5072[335]), + .I1(cfg_cfg_5072[336]), + .I2(cfg_cfg_5072[337]), + .I3(cfg_cfg_5072[338]), + .O(com_cmm_u_cmm_decoder_un7_bar6_32_hit_nc_2_and) + ); + defparam com_cmm_u_cmm_decoder_un7_bar6_32_hit_nc_1_and_0_a2_0_a2_0_a2.INIT = 16'h0001; + LUT4 com_cmm_u_cmm_decoder_un7_bar6_32_hit_nc_1_and_0_a2_0_a2_0_a2 ( + .I0(cfg_cfg_5072[331]), + .I1(cfg_cfg_5072[332]), + .I2(cfg_cfg_5072[333]), + .I3(cfg_cfg_5072[334]), + .O(com_cmm_u_cmm_decoder_un7_bar6_32_hit_nc_1_and) + ); + defparam com_cmm_u_cmm_decoder_un7_bar6_32_hit_nc_0_and.INIT = 16'h0001; + LUT4 com_cmm_u_cmm_decoder_un7_bar6_32_hit_nc_0_and ( + .I0(cfg_cfg_5072[327]), + .I1(cfg_cfg_5072[328]), + .I2(cfg_cfg_5072[329]), + .I3(cfg_cfg_5072[330]), + .O(com_cmm_u_cmm_decoder_un7_bar6_32_hit_nc_0_and_4510) + ); + defparam com_cmm_u_cmm_decoder_un11_bar0_32_hit_nc_7_and_0_a2_0_a2_0_a2.INIT = 16'h0001; + LUT4 com_cmm_u_cmm_decoder_un11_bar0_32_hit_nc_7_and_0_a2_0_a2_0_a2 ( + .I0(cfg_cfg_5072[92]), + .I1(cfg_cfg_5072[93]), + .I2(cfg_cfg_5072[94]), + .I3(cfg_cfg_5072[95]), + .O(com_cmm_u_cmm_decoder_un11_bar0_32_hit_nc_7_and) + ); + defparam com_cmm_u_cmm_decoder_un11_bar0_32_hit_nc_6_and_0_a2_0_a2.INIT = 16'h0001; + LUT4 com_cmm_u_cmm_decoder_un11_bar0_32_hit_nc_6_and_0_a2_0_a2 ( + .I0(cfg_cfg_5072[88]), + .I1(cfg_cfg_5072[89]), + .I2(cfg_cfg_5072[90]), + .I3(cfg_cfg_5072[91]), + .O(com_cmm_u_cmm_decoder_un11_bar0_32_hit_nc_6_and) + ); + defparam com_cmm_u_cmm_decoder_un11_bar0_32_hit_nc_5_and_0_a2_0_a2.INIT = 16'h0001; + LUT4 com_cmm_u_cmm_decoder_un11_bar0_32_hit_nc_5_and_0_a2_0_a2 ( + .I0(cfg_cfg_5072[84]), + .I1(cfg_cfg_5072[85]), + .I2(cfg_cfg_5072[86]), + .I3(cfg_cfg_5072[87]), + .O(com_cmm_u_cmm_decoder_un11_bar0_32_hit_nc_5_and) + ); + defparam com_cmm_u_cmm_decoder_un11_bar0_32_hit_nc_4_and_0_a2_0_a2_0_a2.INIT = 16'h0001; + LUT4 com_cmm_u_cmm_decoder_un11_bar0_32_hit_nc_4_and_0_a2_0_a2_0_a2 ( + .I0(cfg_cfg_5072[80]), + .I1(cfg_cfg_5072[81]), + .I2(cfg_cfg_5072[82]), + .I3(cfg_cfg_5072[83]), + .O(com_cmm_u_cmm_decoder_un11_bar0_32_hit_nc_4_and) + ); + defparam com_cmm_u_cmm_decoder_un11_bar0_32_hit_nc_3_and_0_a2_0_a2_0_a2.INIT = 16'h0001; + LUT4 com_cmm_u_cmm_decoder_un11_bar0_32_hit_nc_3_and_0_a2_0_a2_0_a2 ( + .I0(cfg_cfg_5072[76]), + .I1(cfg_cfg_5072[77]), + .I2(cfg_cfg_5072[78]), + .I3(cfg_cfg_5072[79]), + .O(com_cmm_u_cmm_decoder_un11_bar0_32_hit_nc_3_and) + ); + defparam com_cmm_u_cmm_decoder_un11_bar0_32_hit_nc_2_and_0_a2_0_a2_0_a2.INIT = 16'h0001; + LUT4 com_cmm_u_cmm_decoder_un11_bar0_32_hit_nc_2_and_0_a2_0_a2_0_a2 ( + .I0(cfg_cfg_5072[72]), + .I1(cfg_cfg_5072[73]), + .I2(cfg_cfg_5072[74]), + .I3(cfg_cfg_5072[75]), + .O(com_cmm_u_cmm_decoder_un11_bar0_32_hit_nc_2_and) + ); + defparam com_cmm_u_cmm_decoder_un11_bar0_32_hit_nc_1_and_0_a2_0_a2_0_a2_0_a2.INIT = 16'h0001; + LUT4 com_cmm_u_cmm_decoder_un11_bar0_32_hit_nc_1_and_0_a2_0_a2_0_a2_0_a2 ( + .I0(cfg_cfg_5072[68]), + .I1(cfg_cfg_5072[69]), + .I2(cfg_cfg_5072[70]), + .I3(cfg_cfg_5072[71]), + .O(com_cmm_u_cmm_decoder_un11_bar0_32_hit_nc_1_and) + ); + defparam com_cmm_u_cmm_decoder_un11_bar0_32_hit_nc_0_and_0_a2_0_a2_0_a2_0_a2.INIT = 16'h0001; + LUT4 com_cmm_u_cmm_decoder_un11_bar0_32_hit_nc_0_and_0_a2_0_a2_0_a2_0_a2 ( + .I0(cfg_cfg_5072[64]), + .I1(cfg_cfg_5072[65]), + .I2(cfg_cfg_5072[66]), + .I3(cfg_cfg_5072[67]), + .O(com_cmm_u_cmm_decoder_un11_bar0_32_hit_nc_0_and) + ); + defparam com_cmm_u_cmm_decoder_un18_bar0_32_hit_nc_7_and_0_a2_0_a2_0_a2.INIT = 16'h0001; + LUT4 com_cmm_u_cmm_decoder_un18_bar0_32_hit_nc_7_and_0_a2_0_a2_0_a2 ( + .I0(com_cmm_bar1_reg[28]), + .I1(com_cmm_bar1_reg[29]), + .I2(com_cmm_bar1_reg[30]), + .I3(com_cmm_bar1_reg[31]), + .O(com_cmm_u_cmm_decoder_un18_bar0_32_hit_nc_7_and) + ); + defparam com_cmm_u_cmm_decoder_un18_bar0_32_hit_nc_6_and_0_a2_0_a2_0_a2.INIT = 16'h0001; + LUT4 com_cmm_u_cmm_decoder_un18_bar0_32_hit_nc_6_and_0_a2_0_a2_0_a2 ( + .I0(com_cmm_bar1_reg[24]), + .I1(com_cmm_bar1_reg[25]), + .I2(com_cmm_bar1_reg[26]), + .I3(com_cmm_bar1_reg[27]), + .O(com_cmm_u_cmm_decoder_un18_bar0_32_hit_nc_6_and) + ); + defparam com_cmm_u_cmm_decoder_un18_bar0_32_hit_nc_5_and_0_a2_0_a2_0_a2.INIT = 16'h0001; + LUT4 com_cmm_u_cmm_decoder_un18_bar0_32_hit_nc_5_and_0_a2_0_a2_0_a2 ( + .I0(com_cmm_bar1_reg[20]), + .I1(com_cmm_bar1_reg[21]), + .I2(com_cmm_bar1_reg[22]), + .I3(com_cmm_bar1_reg[23]), + .O(com_cmm_u_cmm_decoder_un18_bar0_32_hit_nc_5_and) + ); + defparam com_cmm_u_cmm_decoder_un18_bar0_32_hit_nc_4_and_0_a2_0_a2_0_a2.INIT = 16'h0001; + LUT4 com_cmm_u_cmm_decoder_un18_bar0_32_hit_nc_4_and_0_a2_0_a2_0_a2 ( + .I0(com_cmm_bar1_reg[16]), + .I1(com_cmm_bar1_reg[17]), + .I2(com_cmm_bar1_reg[18]), + .I3(com_cmm_bar1_reg[19]), + .O(com_cmm_u_cmm_decoder_un18_bar0_32_hit_nc_4_and) + ); + defparam com_cmm_u_cmm_decoder_un18_bar0_32_hit_nc_3_and_0_a2_0_a2_0_a2.INIT = 16'h0001; + LUT4 com_cmm_u_cmm_decoder_un18_bar0_32_hit_nc_3_and_0_a2_0_a2_0_a2 ( + .I0(com_cmm_bar1_reg[12]), + .I1(com_cmm_bar1_reg[13]), + .I2(com_cmm_bar1_reg[14]), + .I3(com_cmm_bar1_reg[15]), + .O(com_cmm_u_cmm_decoder_un18_bar0_32_hit_nc_3_and) + ); + defparam com_cmm_u_cmm_decoder_un18_bar0_32_hit_nc_2_and_0_a2_0_a2_0_a2.INIT = 16'h0001; + LUT4 com_cmm_u_cmm_decoder_un18_bar0_32_hit_nc_2_and_0_a2_0_a2_0_a2 ( + .I0(com_cmm_bar1_reg[8]), + .I1(com_cmm_bar1_reg[9]), + .I2(com_cmm_bar1_reg[10]), + .I3(com_cmm_bar1_reg[11]), + .O(com_cmm_u_cmm_decoder_un18_bar0_32_hit_nc_2_and) + ); + defparam com_cmm_u_cmm_decoder_un18_bar0_32_hit_nc_1_and_0_a2_0_a2_0_a2.INIT = 16'h0001; + LUT4 com_cmm_u_cmm_decoder_un18_bar0_32_hit_nc_1_and_0_a2_0_a2_0_a2 ( + .I0(com_cmm_bar1_reg[4]), + .I1(com_cmm_bar1_reg[5]), + .I2(com_cmm_bar1_reg[6]), + .I3(com_cmm_bar1_reg[7]), + .O(com_cmm_u_cmm_decoder_un18_bar0_32_hit_nc_1_and) + ); + defparam com_cmm_u_cmm_decoder_un18_bar0_32_hit_nc_0_and_0_a2_0_a2_0_a2.INIT = 8'h10; + LUT3 com_cmm_u_cmm_decoder_un18_bar0_32_hit_nc_0_and_0_a2_0_a2_0_a2 ( + .I0(com_cmm_bar1_reg[2]), + .I1(com_cmm_bar1_reg[3]), + .I2(com_cmm_u_cmm_decoder_un18_bar0_32_hit_nc_0_and_1), + .O(com_cmm_u_cmm_decoder_un18_bar0_32_hit_nc_0_and) + ); + defparam com_cmm_u_cmm_decoder_un18_bar1_32_hit_nc_7_and_0_a2_0_a2_0_a2.INIT = 16'h0001; + LUT4 com_cmm_u_cmm_decoder_un18_bar1_32_hit_nc_7_and_0_a2_0_a2_0_a2 ( + .I0(com_cmm_bar2_reg[28]), + .I1(com_cmm_bar2_reg[29]), + .I2(com_cmm_bar2_reg[30]), + .I3(com_cmm_bar2_reg[31]), + .O(com_cmm_u_cmm_decoder_un18_bar1_32_hit_nc_7_and) + ); + defparam com_cmm_u_cmm_decoder_un18_bar1_32_hit_nc_6_and_0_a2_0_a2_0_a2.INIT = 16'h0001; + LUT4 com_cmm_u_cmm_decoder_un18_bar1_32_hit_nc_6_and_0_a2_0_a2_0_a2 ( + .I0(com_cmm_bar2_reg[24]), + .I1(com_cmm_bar2_reg[25]), + .I2(com_cmm_bar2_reg[26]), + .I3(com_cmm_bar2_reg[27]), + .O(com_cmm_u_cmm_decoder_un18_bar1_32_hit_nc_6_and) + ); + defparam com_cmm_u_cmm_decoder_un18_bar1_32_hit_nc_5_and_0_a2_0_a2_0_a2.INIT = 16'h0001; + LUT4 com_cmm_u_cmm_decoder_un18_bar1_32_hit_nc_5_and_0_a2_0_a2_0_a2 ( + .I0(com_cmm_bar2_reg[20]), + .I1(com_cmm_bar2_reg[21]), + .I2(com_cmm_bar2_reg[22]), + .I3(com_cmm_bar2_reg[23]), + .O(com_cmm_u_cmm_decoder_un18_bar1_32_hit_nc_5_and) + ); + defparam com_cmm_u_cmm_decoder_un18_bar1_32_hit_nc_4_and_0_a2_0_a2_0_a2.INIT = 16'h0001; + LUT4 com_cmm_u_cmm_decoder_un18_bar1_32_hit_nc_4_and_0_a2_0_a2_0_a2 ( + .I0(com_cmm_bar2_reg[16]), + .I1(com_cmm_bar2_reg[17]), + .I2(com_cmm_bar2_reg[18]), + .I3(com_cmm_bar2_reg[19]), + .O(com_cmm_u_cmm_decoder_un18_bar1_32_hit_nc_4_and) + ); + defparam com_cmm_u_cmm_decoder_un18_bar1_32_hit_nc_3_and_0_a2_0_a2_0_a2.INIT = 16'h0001; + LUT4 com_cmm_u_cmm_decoder_un18_bar1_32_hit_nc_3_and_0_a2_0_a2_0_a2 ( + .I0(com_cmm_bar2_reg[12]), + .I1(com_cmm_bar2_reg[13]), + .I2(com_cmm_bar2_reg[14]), + .I3(com_cmm_bar2_reg[15]), + .O(com_cmm_u_cmm_decoder_un18_bar1_32_hit_nc_3_and) + ); + defparam com_cmm_u_cmm_decoder_un18_bar1_32_hit_nc_2_and_0_a2_0_a2_0_a2.INIT = 16'h0001; + LUT4 com_cmm_u_cmm_decoder_un18_bar1_32_hit_nc_2_and_0_a2_0_a2_0_a2 ( + .I0(com_cmm_bar2_reg[8]), + .I1(com_cmm_bar2_reg[9]), + .I2(com_cmm_bar2_reg[10]), + .I3(com_cmm_bar2_reg[11]), + .O(com_cmm_u_cmm_decoder_un18_bar1_32_hit_nc_2_and) + ); + defparam com_cmm_u_cmm_decoder_un18_bar1_32_hit_nc_1_and_0_a2_0_a2_0_a2.INIT = 16'h0001; + LUT4 com_cmm_u_cmm_decoder_un18_bar1_32_hit_nc_1_and_0_a2_0_a2_0_a2 ( + .I0(com_cmm_bar2_reg[4]), + .I1(com_cmm_bar2_reg[5]), + .I2(com_cmm_bar2_reg[6]), + .I3(com_cmm_bar2_reg[7]), + .O(com_cmm_u_cmm_decoder_un18_bar1_32_hit_nc_1_and) + ); + defparam com_cmm_u_cmm_decoder_un18_bar1_32_hit_nc_0_and_0_a2_0_a2.INIT = 8'h10; + LUT3 com_cmm_u_cmm_decoder_un18_bar1_32_hit_nc_0_and_0_a2_0_a2 ( + .I0(com_cmm_bar2_reg[2]), + .I1(com_cmm_bar2_reg[3]), + .I2(com_cmm_u_cmm_decoder_bar23_64_hit_high_3_1), + .O(com_cmm_u_cmm_decoder_un18_bar1_32_hit_nc_0_and) + ); + defparam com_cmm_u_cmm_decoder_un18_bar2_32_hit_nc_7_and_0_a2_0_a2_0_a2.INIT = 16'h0001; + LUT4 com_cmm_u_cmm_decoder_un18_bar2_32_hit_nc_7_and_0_a2_0_a2_0_a2 ( + .I0(com_cmm_bar3_reg[28]), + .I1(com_cmm_bar3_reg[29]), + .I2(com_cmm_bar3_reg[30]), + .I3(com_cmm_bar3_reg[31]), + .O(com_cmm_u_cmm_decoder_un18_bar2_32_hit_nc_7_and) + ); + defparam com_cmm_u_cmm_decoder_un18_bar2_32_hit_nc_6_and_0_a2_0_a2_0_a2.INIT = 16'h0001; + LUT4 com_cmm_u_cmm_decoder_un18_bar2_32_hit_nc_6_and_0_a2_0_a2_0_a2 ( + .I0(com_cmm_bar3_reg[24]), + .I1(com_cmm_bar3_reg[25]), + .I2(com_cmm_bar3_reg[26]), + .I3(com_cmm_bar3_reg[27]), + .O(com_cmm_u_cmm_decoder_un18_bar2_32_hit_nc_6_and) + ); + defparam com_cmm_u_cmm_decoder_un18_bar2_32_hit_nc_5_and_0_a2_0_a2_0_a2.INIT = 16'h0001; + LUT4 com_cmm_u_cmm_decoder_un18_bar2_32_hit_nc_5_and_0_a2_0_a2_0_a2 ( + .I0(com_cmm_bar3_reg[20]), + .I1(com_cmm_bar3_reg[21]), + .I2(com_cmm_bar3_reg[22]), + .I3(com_cmm_bar3_reg[23]), + .O(com_cmm_u_cmm_decoder_un18_bar2_32_hit_nc_5_and) + ); + defparam com_cmm_u_cmm_decoder_un18_bar2_32_hit_nc_4_and_0_a2_0_a2_0_a2.INIT = 16'h0001; + LUT4 com_cmm_u_cmm_decoder_un18_bar2_32_hit_nc_4_and_0_a2_0_a2_0_a2 ( + .I0(com_cmm_bar3_reg[16]), + .I1(com_cmm_bar3_reg[17]), + .I2(com_cmm_bar3_reg[18]), + .I3(com_cmm_bar3_reg[19]), + .O(com_cmm_u_cmm_decoder_un18_bar2_32_hit_nc_4_and) + ); + defparam com_cmm_u_cmm_decoder_un18_bar2_32_hit_nc_3_and_0_a2_0_a2_0_a2.INIT = 16'h0001; + LUT4 com_cmm_u_cmm_decoder_un18_bar2_32_hit_nc_3_and_0_a2_0_a2_0_a2 ( + .I0(com_cmm_bar3_reg[12]), + .I1(com_cmm_bar3_reg[13]), + .I2(com_cmm_bar3_reg[14]), + .I3(com_cmm_bar3_reg[15]), + .O(com_cmm_u_cmm_decoder_un18_bar2_32_hit_nc_3_and) + ); + defparam com_cmm_u_cmm_decoder_un18_bar2_32_hit_nc_2_and_0_a2_0_a2_0_a2.INIT = 16'h0001; + LUT4 com_cmm_u_cmm_decoder_un18_bar2_32_hit_nc_2_and_0_a2_0_a2_0_a2 ( + .I0(com_cmm_bar3_reg[8]), + .I1(com_cmm_bar3_reg[9]), + .I2(com_cmm_bar3_reg[10]), + .I3(com_cmm_bar3_reg[11]), + .O(com_cmm_u_cmm_decoder_un18_bar2_32_hit_nc_2_and) + ); + defparam com_cmm_u_cmm_decoder_un18_bar2_32_hit_nc_1_and_0_a2.INIT = 16'h0001; + LUT4 com_cmm_u_cmm_decoder_un18_bar2_32_hit_nc_1_and_0_a2 ( + .I0(com_cmm_bar3_reg[4]), + .I1(com_cmm_bar3_reg[5]), + .I2(com_cmm_bar3_reg[6]), + .I3(com_cmm_bar3_reg[7]), + .O(com_cmm_u_cmm_decoder_un18_bar2_32_hit_nc_1_and) + ); + defparam com_cmm_u_cmm_decoder_un18_bar2_32_hit_nc_0_and_0_a2_0_a2_0_a2.INIT = 8'h10; + LUT3 com_cmm_u_cmm_decoder_un18_bar2_32_hit_nc_0_and_0_a2_0_a2_0_a2 ( + .I0(com_cmm_bar3_reg[2]), + .I1(com_cmm_bar3_reg[3]), + .I2(com_cmm_u_cmm_decoder_un18_bar2_32_hit_nc_0_and_1), + .O(com_cmm_u_cmm_decoder_un18_bar2_32_hit_nc_0_and) + ); + defparam com_cmm_u_cmm_decoder_un18_bar3_32_hit_nc_7_and_0_a2_0_a2_0_a2_0_a2.INIT = 16'h0001; + LUT4 com_cmm_u_cmm_decoder_un18_bar3_32_hit_nc_7_and_0_a2_0_a2_0_a2_0_a2 ( + .I0(com_cmm_bar4_reg[28]), + .I1(com_cmm_bar4_reg[29]), + .I2(com_cmm_bar4_reg[30]), + .I3(com_cmm_bar4_reg[31]), + .O(com_cmm_u_cmm_decoder_un18_bar3_32_hit_nc_7_and) + ); + defparam com_cmm_u_cmm_decoder_un18_bar3_32_hit_nc_6_and_0_a2_0_a2_0_a2_0_a2.INIT = 16'h0001; + LUT4 com_cmm_u_cmm_decoder_un18_bar3_32_hit_nc_6_and_0_a2_0_a2_0_a2_0_a2 ( + .I0(com_cmm_bar4_reg[24]), + .I1(com_cmm_bar4_reg[25]), + .I2(com_cmm_bar4_reg[26]), + .I3(com_cmm_bar4_reg[27]), + .O(com_cmm_u_cmm_decoder_un18_bar3_32_hit_nc_6_and) + ); + defparam com_cmm_u_cmm_decoder_un18_bar3_32_hit_nc_5_and_0_a2_0_a2_0_a2.INIT = 16'h0001; + LUT4 com_cmm_u_cmm_decoder_un18_bar3_32_hit_nc_5_and_0_a2_0_a2_0_a2 ( + .I0(com_cmm_bar4_reg[20]), + .I1(com_cmm_bar4_reg[21]), + .I2(com_cmm_bar4_reg[22]), + .I3(com_cmm_bar4_reg[23]), + .O(com_cmm_u_cmm_decoder_un18_bar3_32_hit_nc_5_and) + ); + defparam com_cmm_u_cmm_decoder_un18_bar3_32_hit_nc_4_and_0_a2_0_a2_0_a2_0_a2.INIT = 16'h0001; + LUT4 com_cmm_u_cmm_decoder_un18_bar3_32_hit_nc_4_and_0_a2_0_a2_0_a2_0_a2 ( + .I0(com_cmm_bar4_reg[16]), + .I1(com_cmm_bar4_reg[17]), + .I2(com_cmm_bar4_reg[18]), + .I3(com_cmm_bar4_reg[19]), + .O(com_cmm_u_cmm_decoder_un18_bar3_32_hit_nc_4_and) + ); + defparam com_cmm_u_cmm_decoder_un18_bar3_32_hit_nc_3_and_0_a2_0_a2_0_a2_0_a2.INIT = 16'h0001; + LUT4 com_cmm_u_cmm_decoder_un18_bar3_32_hit_nc_3_and_0_a2_0_a2_0_a2_0_a2 ( + .I0(com_cmm_bar4_reg[12]), + .I1(com_cmm_bar4_reg[13]), + .I2(com_cmm_bar4_reg[14]), + .I3(com_cmm_bar4_reg[15]), + .O(com_cmm_u_cmm_decoder_un18_bar3_32_hit_nc_3_and) + ); + defparam com_cmm_u_cmm_decoder_un18_bar3_32_hit_nc_2_and_0_a2_0_a2_0_a2_0_a2.INIT = 16'h0001; + LUT4 com_cmm_u_cmm_decoder_un18_bar3_32_hit_nc_2_and_0_a2_0_a2_0_a2_0_a2 ( + .I0(com_cmm_bar4_reg[8]), + .I1(com_cmm_bar4_reg[9]), + .I2(com_cmm_bar4_reg[10]), + .I3(com_cmm_bar4_reg[11]), + .O(com_cmm_u_cmm_decoder_un18_bar3_32_hit_nc_2_and) + ); + defparam com_cmm_u_cmm_decoder_un18_bar3_32_hit_nc_1_and_0_a2_0_a2_0_a2.INIT = 16'h0001; + LUT4 com_cmm_u_cmm_decoder_un18_bar3_32_hit_nc_1_and_0_a2_0_a2_0_a2 ( + .I0(com_cmm_bar4_reg[4]), + .I1(com_cmm_bar4_reg[5]), + .I2(com_cmm_bar4_reg[6]), + .I3(com_cmm_bar4_reg[7]), + .O(com_cmm_u_cmm_decoder_un18_bar3_32_hit_nc_1_and) + ); + defparam com_cmm_u_cmm_decoder_un18_bar3_32_hit_nc_0_and_0_a2_0_a2_0_a2_0_a2.INIT = 8'h10; + LUT3 com_cmm_u_cmm_decoder_un18_bar3_32_hit_nc_0_and_0_a2_0_a2_0_a2_0_a2 ( + .I0(com_cmm_bar4_reg[2]), + .I1(com_cmm_bar4_reg[3]), + .I2(com_cmm_u_cmm_decoder_un18_bar3_32_hit_nc_0_and_1), + .O(com_cmm_u_cmm_decoder_un18_bar3_32_hit_nc_0_and) + ); + defparam com_cmm_u_cmm_decoder_un18_bar4_32_hit_nc_7_and_0_a2.INIT = 16'h0001; + LUT4 com_cmm_u_cmm_decoder_un18_bar4_32_hit_nc_7_and_0_a2 ( + .I0(com_cmm_bar5_reg[28]), + .I1(com_cmm_bar5_reg[29]), + .I2(com_cmm_bar5_reg[30]), + .I3(com_cmm_bar5_reg[31]), + .O(com_cmm_u_cmm_decoder_un18_bar4_32_hit_nc_7_and) + ); + defparam com_cmm_u_cmm_decoder_un18_bar4_32_hit_nc_6_and_0_a2_0_a2_0_a2.INIT = 16'h0001; + LUT4 com_cmm_u_cmm_decoder_un18_bar4_32_hit_nc_6_and_0_a2_0_a2_0_a2 ( + .I0(com_cmm_bar5_reg[24]), + .I1(com_cmm_bar5_reg[25]), + .I2(com_cmm_bar5_reg[26]), + .I3(com_cmm_bar5_reg[27]), + .O(com_cmm_u_cmm_decoder_un18_bar4_32_hit_nc_6_and) + ); + defparam com_cmm_u_cmm_decoder_un18_bar4_32_hit_nc_5_and_0_a2_0_a2_0_a2.INIT = 16'h0001; + LUT4 com_cmm_u_cmm_decoder_un18_bar4_32_hit_nc_5_and_0_a2_0_a2_0_a2 ( + .I0(com_cmm_bar5_reg[20]), + .I1(com_cmm_bar5_reg[21]), + .I2(com_cmm_bar5_reg[22]), + .I3(com_cmm_bar5_reg[23]), + .O(com_cmm_u_cmm_decoder_un18_bar4_32_hit_nc_5_and) + ); + defparam com_cmm_u_cmm_decoder_un18_bar4_32_hit_nc_4_and_0_a2_0_a2_0_a2.INIT = 16'h0001; + LUT4 com_cmm_u_cmm_decoder_un18_bar4_32_hit_nc_4_and_0_a2_0_a2_0_a2 ( + .I0(com_cmm_bar5_reg[16]), + .I1(com_cmm_bar5_reg[17]), + .I2(com_cmm_bar5_reg[18]), + .I3(com_cmm_bar5_reg[19]), + .O(com_cmm_u_cmm_decoder_un18_bar4_32_hit_nc_4_and) + ); + defparam com_cmm_u_cmm_decoder_un18_bar4_32_hit_nc_3_and_0_a2_0_a2_0_a2.INIT = 16'h0001; + LUT4 com_cmm_u_cmm_decoder_un18_bar4_32_hit_nc_3_and_0_a2_0_a2_0_a2 ( + .I0(com_cmm_bar5_reg[12]), + .I1(com_cmm_bar5_reg[13]), + .I2(com_cmm_bar5_reg[14]), + .I3(com_cmm_bar5_reg[15]), + .O(com_cmm_u_cmm_decoder_un18_bar4_32_hit_nc_3_and) + ); + defparam com_cmm_u_cmm_decoder_un18_bar4_32_hit_nc_2_and_0_a2_0_a2_0_a2.INIT = 16'h0001; + LUT4 com_cmm_u_cmm_decoder_un18_bar4_32_hit_nc_2_and_0_a2_0_a2_0_a2 ( + .I0(com_cmm_bar5_reg[8]), + .I1(com_cmm_bar5_reg[9]), + .I2(com_cmm_bar5_reg[10]), + .I3(com_cmm_bar5_reg[11]), + .O(com_cmm_u_cmm_decoder_un18_bar4_32_hit_nc_2_and) + ); + defparam com_cmm_u_cmm_decoder_un18_bar4_32_hit_nc_1_and_0_a2_0_a2_0_a2.INIT = 16'h0001; + LUT4 com_cmm_u_cmm_decoder_un18_bar4_32_hit_nc_1_and_0_a2_0_a2_0_a2 ( + .I0(com_cmm_bar5_reg[4]), + .I1(com_cmm_bar5_reg[5]), + .I2(com_cmm_bar5_reg[6]), + .I3(com_cmm_bar5_reg[7]), + .O(com_cmm_u_cmm_decoder_un18_bar4_32_hit_nc_1_and) + ); + defparam com_cmm_u_cmm_decoder_un18_bar4_32_hit_nc_0_and_0_a2_0_a2.INIT = 16'h0001; + LUT4 com_cmm_u_cmm_decoder_un18_bar4_32_hit_nc_0_and_0_a2_0_a2 ( + .I0(com_cmm_bar5_reg[0]), + .I1(com_cmm_bar5_reg[1]), + .I2(com_cmm_bar5_reg[2]), + .I3(com_cmm_bar5_reg[3]), + .O(com_cmm_u_cmm_decoder_un18_bar4_32_hit_nc_0_and) + ); + defparam com_cmm_u_cmm_decoder_un11_bar1_32_hit_nc_7_and_0_a2_0_a2_0_a2.INIT = 16'h0001; + LUT4 com_cmm_u_cmm_decoder_un11_bar1_32_hit_nc_7_and_0_a2_0_a2_0_a2 ( + .I0(cfg_cfg_5072[124]), + .I1(cfg_cfg_5072[125]), + .I2(cfg_cfg_5072[126]), + .I3(cfg_cfg_5072[127]), + .O(com_cmm_u_cmm_decoder_un11_bar1_32_hit_nc_7_and) + ); + defparam com_cmm_u_cmm_decoder_un11_bar1_32_hit_nc_6_and_0_a2_0_a2.INIT = 16'h0001; + LUT4 com_cmm_u_cmm_decoder_un11_bar1_32_hit_nc_6_and_0_a2_0_a2 ( + .I0(cfg_cfg_5072[120]), + .I1(cfg_cfg_5072[121]), + .I2(cfg_cfg_5072[122]), + .I3(cfg_cfg_5072[123]), + .O(com_cmm_u_cmm_decoder_un11_bar1_32_hit_nc_6_and) + ); + defparam com_cmm_u_cmm_decoder_un11_bar1_32_hit_nc_5_and_0_a2_0_a2.INIT = 16'h0001; + LUT4 com_cmm_u_cmm_decoder_un11_bar1_32_hit_nc_5_and_0_a2_0_a2 ( + .I0(cfg_cfg_5072[116]), + .I1(cfg_cfg_5072[117]), + .I2(cfg_cfg_5072[118]), + .I3(cfg_cfg_5072[119]), + .O(com_cmm_u_cmm_decoder_un11_bar1_32_hit_nc_5_and) + ); + defparam com_cmm_u_cmm_decoder_un11_bar1_32_hit_nc_4_and_0_a2_0_a2_0_a2.INIT = 16'h0001; + LUT4 com_cmm_u_cmm_decoder_un11_bar1_32_hit_nc_4_and_0_a2_0_a2_0_a2 ( + .I0(cfg_cfg_5072[112]), + .I1(cfg_cfg_5072[113]), + .I2(cfg_cfg_5072[114]), + .I3(cfg_cfg_5072[115]), + .O(com_cmm_u_cmm_decoder_un11_bar1_32_hit_nc_4_and) + ); + defparam com_cmm_u_cmm_decoder_un11_bar1_32_hit_nc_3_and_0_a2_0_a2_0_a2.INIT = 16'h0001; + LUT4 com_cmm_u_cmm_decoder_un11_bar1_32_hit_nc_3_and_0_a2_0_a2_0_a2 ( + .I0(cfg_cfg_5072[108]), + .I1(cfg_cfg_5072[109]), + .I2(cfg_cfg_5072[110]), + .I3(cfg_cfg_5072[111]), + .O(com_cmm_u_cmm_decoder_un11_bar1_32_hit_nc_3_and) + ); + defparam com_cmm_u_cmm_decoder_un11_bar1_32_hit_nc_2_and_0_a2_0_a2_0_a2.INIT = 16'h0001; + LUT4 com_cmm_u_cmm_decoder_un11_bar1_32_hit_nc_2_and_0_a2_0_a2_0_a2 ( + .I0(cfg_cfg_5072[104]), + .I1(cfg_cfg_5072[105]), + .I2(cfg_cfg_5072[106]), + .I3(cfg_cfg_5072[107]), + .O(com_cmm_u_cmm_decoder_un11_bar1_32_hit_nc_2_and) + ); + defparam com_cmm_u_cmm_decoder_un11_bar1_32_hit_nc_1_and_0_a2_0_a2_0_a2_0_a2.INIT = 16'h0001; + LUT4 com_cmm_u_cmm_decoder_un11_bar1_32_hit_nc_1_and_0_a2_0_a2_0_a2_0_a2 ( + .I0(cfg_cfg_5072[100]), + .I1(cfg_cfg_5072[101]), + .I2(cfg_cfg_5072[102]), + .I3(cfg_cfg_5072[103]), + .O(com_cmm_u_cmm_decoder_un11_bar1_32_hit_nc_1_and) + ); + defparam com_cmm_u_cmm_decoder_un11_bar1_32_hit_nc_0_and_0_a2_0_a2_0_a2_0_a2.INIT = 8'h02; + LUT3 com_cmm_u_cmm_decoder_un11_bar1_32_hit_nc_0_and_0_a2_0_a2_0_a2_0_a2 ( + .I0(com_cmm_N_48883_i), + .I1(cfg_cfg_5072[98]), + .I2(cfg_cfg_5072[99]), + .O(com_cmm_u_cmm_decoder_un11_bar1_32_hit_nc_0_and) + ); + defparam com_cmm_u_cmm_decoder_un11_bar2_32_hit_nc_7_and_0_a2_0_a2_0_a2.INIT = 16'h0001; + LUT4 com_cmm_u_cmm_decoder_un11_bar2_32_hit_nc_7_and_0_a2_0_a2_0_a2 ( + .I0(cfg_cfg_5072[156]), + .I1(cfg_cfg_5072[157]), + .I2(cfg_cfg_5072[158]), + .I3(cfg_cfg_5072[159]), + .O(com_cmm_u_cmm_decoder_un11_bar2_32_hit_nc_7_and) + ); + defparam com_cmm_u_cmm_decoder_un11_bar2_32_hit_nc_6_and_0_a2_0_a2.INIT = 16'h0001; + LUT4 com_cmm_u_cmm_decoder_un11_bar2_32_hit_nc_6_and_0_a2_0_a2 ( + .I0(cfg_cfg_5072[152]), + .I1(cfg_cfg_5072[153]), + .I2(cfg_cfg_5072[154]), + .I3(cfg_cfg_5072[155]), + .O(com_cmm_u_cmm_decoder_un11_bar2_32_hit_nc_6_and) + ); + defparam com_cmm_u_cmm_decoder_un11_bar2_32_hit_nc_5_and_0_a2_0_a2_0_a2.INIT = 16'h0001; + LUT4 com_cmm_u_cmm_decoder_un11_bar2_32_hit_nc_5_and_0_a2_0_a2_0_a2 ( + .I0(cfg_cfg_5072[148]), + .I1(cfg_cfg_5072[149]), + .I2(cfg_cfg_5072[150]), + .I3(cfg_cfg_5072[151]), + .O(com_cmm_u_cmm_decoder_un11_bar2_32_hit_nc_5_and) + ); + defparam com_cmm_u_cmm_decoder_un11_bar2_32_hit_nc_4_and_0_a2_0_a2_0_a2.INIT = 16'h0001; + LUT4 com_cmm_u_cmm_decoder_un11_bar2_32_hit_nc_4_and_0_a2_0_a2_0_a2 ( + .I0(cfg_cfg_5072[144]), + .I1(cfg_cfg_5072[145]), + .I2(cfg_cfg_5072[146]), + .I3(cfg_cfg_5072[147]), + .O(com_cmm_u_cmm_decoder_un11_bar2_32_hit_nc_4_and) + ); + defparam com_cmm_u_cmm_decoder_un11_bar2_32_hit_nc_3_and_0_a2_0_a2_0_a2.INIT = 16'h0001; + LUT4 com_cmm_u_cmm_decoder_un11_bar2_32_hit_nc_3_and_0_a2_0_a2_0_a2 ( + .I0(cfg_cfg_5072[140]), + .I1(cfg_cfg_5072[141]), + .I2(cfg_cfg_5072[142]), + .I3(cfg_cfg_5072[143]), + .O(com_cmm_u_cmm_decoder_un11_bar2_32_hit_nc_3_and) + ); + defparam com_cmm_u_cmm_decoder_un11_bar2_32_hit_nc_2_and_0_a2_0_a2_0_a2.INIT = 16'h0001; + LUT4 com_cmm_u_cmm_decoder_un11_bar2_32_hit_nc_2_and_0_a2_0_a2_0_a2 ( + .I0(cfg_cfg_5072[136]), + .I1(cfg_cfg_5072[137]), + .I2(cfg_cfg_5072[138]), + .I3(cfg_cfg_5072[139]), + .O(com_cmm_u_cmm_decoder_un11_bar2_32_hit_nc_2_and) + ); + defparam com_cmm_u_cmm_decoder_un11_bar2_32_hit_nc_1_and_0_a2_0_a2_0_a2_0_a2.INIT = 16'h0001; + LUT4 com_cmm_u_cmm_decoder_un11_bar2_32_hit_nc_1_and_0_a2_0_a2_0_a2_0_a2 ( + .I0(cfg_cfg_5072[132]), + .I1(cfg_cfg_5072[133]), + .I2(cfg_cfg_5072[134]), + .I3(cfg_cfg_5072[135]), + .O(com_cmm_u_cmm_decoder_un11_bar2_32_hit_nc_1_and) + ); + defparam com_cmm_u_cmm_decoder_un11_bar2_32_hit_nc_0_and_0_a2_0_a2_0_a2.INIT = 8'h02; + LUT3 com_cmm_u_cmm_decoder_un11_bar2_32_hit_nc_0_and_0_a2_0_a2_0_a2 ( + .I0(com_cmm_N_48884_i), + .I1(cfg_cfg_5072[130]), + .I2(cfg_cfg_5072[131]), + .O(com_cmm_u_cmm_decoder_un11_bar2_32_hit_nc_0_and) + ); + defparam com_cmm_u_cmm_decoder_un11_bar3_32_hit_nc_7_and_0_a2_0_a2_0_a2.INIT = 16'h0001; + LUT4 com_cmm_u_cmm_decoder_un11_bar3_32_hit_nc_7_and_0_a2_0_a2_0_a2 ( + .I0(cfg_cfg_5072[188]), + .I1(cfg_cfg_5072[189]), + .I2(cfg_cfg_5072[190]), + .I3(cfg_cfg_5072[191]), + .O(com_cmm_u_cmm_decoder_un11_bar3_32_hit_nc_7_and) + ); + defparam com_cmm_u_cmm_decoder_un11_bar3_32_hit_nc_6_and_0_a2_0_a2.INIT = 16'h0001; + LUT4 com_cmm_u_cmm_decoder_un11_bar3_32_hit_nc_6_and_0_a2_0_a2 ( + .I0(cfg_cfg_5072[184]), + .I1(cfg_cfg_5072[185]), + .I2(cfg_cfg_5072[186]), + .I3(cfg_cfg_5072[187]), + .O(com_cmm_u_cmm_decoder_un11_bar3_32_hit_nc_6_and) + ); + defparam com_cmm_u_cmm_decoder_un11_bar3_32_hit_nc_5_and_0_a2_0_a2.INIT = 16'h0001; + LUT4 com_cmm_u_cmm_decoder_un11_bar3_32_hit_nc_5_and_0_a2_0_a2 ( + .I0(cfg_cfg_5072[180]), + .I1(cfg_cfg_5072[181]), + .I2(cfg_cfg_5072[182]), + .I3(cfg_cfg_5072[183]), + .O(com_cmm_u_cmm_decoder_un11_bar3_32_hit_nc_5_and) + ); + defparam com_cmm_u_cmm_decoder_un11_bar3_32_hit_nc_4_and_0_a2_0_a2_0_a2.INIT = 16'h0001; + LUT4 com_cmm_u_cmm_decoder_un11_bar3_32_hit_nc_4_and_0_a2_0_a2_0_a2 ( + .I0(cfg_cfg_5072[176]), + .I1(cfg_cfg_5072[177]), + .I2(cfg_cfg_5072[178]), + .I3(cfg_cfg_5072[179]), + .O(com_cmm_u_cmm_decoder_un11_bar3_32_hit_nc_4_and) + ); + defparam com_cmm_u_cmm_decoder_un11_bar3_32_hit_nc_3_and_0_a2_0_a2_0_a2.INIT = 16'h0001; + LUT4 com_cmm_u_cmm_decoder_un11_bar3_32_hit_nc_3_and_0_a2_0_a2_0_a2 ( + .I0(cfg_cfg_5072[172]), + .I1(cfg_cfg_5072[173]), + .I2(cfg_cfg_5072[174]), + .I3(cfg_cfg_5072[175]), + .O(com_cmm_u_cmm_decoder_un11_bar3_32_hit_nc_3_and) + ); + defparam com_cmm_u_cmm_decoder_un11_bar3_32_hit_nc_2_and_0_a2_0_a2_0_a2.INIT = 16'h0001; + LUT4 com_cmm_u_cmm_decoder_un11_bar3_32_hit_nc_2_and_0_a2_0_a2_0_a2 ( + .I0(cfg_cfg_5072[168]), + .I1(cfg_cfg_5072[169]), + .I2(cfg_cfg_5072[170]), + .I3(cfg_cfg_5072[171]), + .O(com_cmm_u_cmm_decoder_un11_bar3_32_hit_nc_2_and) + ); + defparam com_cmm_u_cmm_decoder_un11_bar3_32_hit_nc_1_and_0_a2_0_a2_0_a2_0_a2.INIT = 16'h0001; + LUT4 com_cmm_u_cmm_decoder_un11_bar3_32_hit_nc_1_and_0_a2_0_a2_0_a2_0_a2 ( + .I0(cfg_cfg_5072[164]), + .I1(cfg_cfg_5072[165]), + .I2(cfg_cfg_5072[166]), + .I3(cfg_cfg_5072[167]), + .O(com_cmm_u_cmm_decoder_un11_bar3_32_hit_nc_1_and) + ); + defparam com_cmm_u_cmm_decoder_un11_bar3_32_hit_nc_0_and_0_a2_0_a2_0_a2.INIT = 16'h0001; + LUT4 com_cmm_u_cmm_decoder_un11_bar3_32_hit_nc_0_and_0_a2_0_a2_0_a2 ( + .I0(cfg_cfg_5072[160]), + .I1(cfg_cfg_5072[161]), + .I2(cfg_cfg_5072[162]), + .I3(cfg_cfg_5072[163]), + .O(com_cmm_u_cmm_decoder_un11_bar3_32_hit_nc_0_and) + ); + defparam com_cmm_u_cmm_decoder_un11_bar4_32_hit_nc_7_sf.INIT = 4'h2; + LUT1 com_cmm_u_cmm_decoder_un11_bar4_32_hit_nc_7_sf ( + .I0(com_cmm_u_cmm_decoder_un11_bar4_32_hit_nc_7_and), + .O(com_cmm_u_cmm_decoder_un11_bar4_32_hit_nc_7_sf_4511) + ); + defparam com_cmm_u_cmm_decoder_un11_bar4_32_hit_nc_6_sf.INIT = 4'h2; + LUT1 com_cmm_u_cmm_decoder_un11_bar4_32_hit_nc_6_sf ( + .I0(com_cmm_u_cmm_decoder_un11_bar4_32_hit_nc_6_and), + .O(com_cmm_u_cmm_decoder_un11_bar4_32_hit_nc_6_sf_4512) + ); + defparam com_cmm_u_cmm_decoder_un11_bar4_32_hit_nc_5_sf.INIT = 4'h2; + LUT1 com_cmm_u_cmm_decoder_un11_bar4_32_hit_nc_5_sf ( + .I0(com_cmm_u_cmm_decoder_un11_bar4_32_hit_nc_5_and), + .O(com_cmm_u_cmm_decoder_un11_bar4_32_hit_nc_5_sf_4513) + ); + defparam com_cmm_u_cmm_decoder_un11_bar4_32_hit_nc_4_sf.INIT = 4'h2; + LUT1 com_cmm_u_cmm_decoder_un11_bar4_32_hit_nc_4_sf ( + .I0(com_cmm_u_cmm_decoder_un11_bar4_32_hit_nc_4_and), + .O(com_cmm_u_cmm_decoder_un11_bar4_32_hit_nc_4_sf_4514) + ); + defparam com_cmm_u_cmm_decoder_un11_bar4_32_hit_nc_3_sf.INIT = 4'h2; + LUT1 com_cmm_u_cmm_decoder_un11_bar4_32_hit_nc_3_sf ( + .I0(com_cmm_u_cmm_decoder_un11_bar4_32_hit_nc_3_and), + .O(com_cmm_u_cmm_decoder_un11_bar4_32_hit_nc_3_sf_4515) + ); + defparam com_cmm_u_cmm_decoder_un11_bar4_32_hit_nc_2_sf.INIT = 4'h2; + LUT1 com_cmm_u_cmm_decoder_un11_bar4_32_hit_nc_2_sf ( + .I0(com_cmm_u_cmm_decoder_un11_bar4_32_hit_nc_2_and), + .O(com_cmm_u_cmm_decoder_un11_bar4_32_hit_nc_2_sf_4516) + ); + defparam com_cmm_u_cmm_decoder_un11_bar4_32_hit_nc_1_sf.INIT = 4'h2; + LUT1 com_cmm_u_cmm_decoder_un11_bar4_32_hit_nc_1_sf ( + .I0(com_cmm_u_cmm_decoder_un11_bar4_32_hit_nc_1_and), + .O(com_cmm_u_cmm_decoder_un11_bar4_32_hit_nc_1_sf_4517) + ); + defparam com_cmm_u_cmm_decoder_un11_bar5_32_hit_nc_7_and_0_a2_0_a2_0_a2.INIT = 16'h0001; + LUT4 com_cmm_u_cmm_decoder_un11_bar5_32_hit_nc_7_and_0_a2_0_a2_0_a2 ( + .I0(cfg_cfg_5072[252]), + .I1(cfg_cfg_5072[253]), + .I2(cfg_cfg_5072[254]), + .I3(cfg_cfg_5072[255]), + .O(com_cmm_u_cmm_decoder_un11_bar5_32_hit_nc_7_and) + ); + defparam com_cmm_u_cmm_decoder_un11_bar5_32_hit_nc_6_and_0_a2_0_a2.INIT = 16'h0001; + LUT4 com_cmm_u_cmm_decoder_un11_bar5_32_hit_nc_6_and_0_a2_0_a2 ( + .I0(cfg_cfg_5072[248]), + .I1(cfg_cfg_5072[249]), + .I2(cfg_cfg_5072[250]), + .I3(cfg_cfg_5072[251]), + .O(com_cmm_u_cmm_decoder_un11_bar5_32_hit_nc_6_and) + ); + defparam com_cmm_u_cmm_decoder_un11_bar5_32_hit_nc_5_and_0_a2_0_a2_0_a2.INIT = 16'h0001; + LUT4 com_cmm_u_cmm_decoder_un11_bar5_32_hit_nc_5_and_0_a2_0_a2_0_a2 ( + .I0(cfg_cfg_5072[244]), + .I1(cfg_cfg_5072[245]), + .I2(cfg_cfg_5072[246]), + .I3(cfg_cfg_5072[247]), + .O(com_cmm_u_cmm_decoder_un11_bar5_32_hit_nc_5_and) + ); + defparam com_cmm_u_cmm_decoder_un11_bar5_32_hit_nc_4_and_0_a2_0_a2_0_a2.INIT = 16'h0001; + LUT4 com_cmm_u_cmm_decoder_un11_bar5_32_hit_nc_4_and_0_a2_0_a2_0_a2 ( + .I0(cfg_cfg_5072[240]), + .I1(cfg_cfg_5072[241]), + .I2(cfg_cfg_5072[242]), + .I3(cfg_cfg_5072[243]), + .O(com_cmm_u_cmm_decoder_un11_bar5_32_hit_nc_4_and) + ); + defparam com_cmm_u_cmm_decoder_un11_bar5_32_hit_nc_3_and_0_a2_0_a2_0_a2.INIT = 16'h0001; + LUT4 com_cmm_u_cmm_decoder_un11_bar5_32_hit_nc_3_and_0_a2_0_a2_0_a2 ( + .I0(cfg_cfg_5072[236]), + .I1(cfg_cfg_5072[237]), + .I2(cfg_cfg_5072[238]), + .I3(cfg_cfg_5072[239]), + .O(com_cmm_u_cmm_decoder_un11_bar5_32_hit_nc_3_and) + ); + defparam com_cmm_u_cmm_decoder_un11_bar5_32_hit_nc_2_and_0_a2_0_a2_0_a2.INIT = 16'h0001; + LUT4 com_cmm_u_cmm_decoder_un11_bar5_32_hit_nc_2_and_0_a2_0_a2_0_a2 ( + .I0(cfg_cfg_5072[232]), + .I1(cfg_cfg_5072[233]), + .I2(cfg_cfg_5072[234]), + .I3(cfg_cfg_5072[235]), + .O(com_cmm_u_cmm_decoder_un11_bar5_32_hit_nc_2_and) + ); + defparam com_cmm_u_cmm_decoder_un11_bar5_32_hit_nc_1_and_0_a2_0_a2_0_a2_0_a2.INIT = 16'h0001; + LUT4 com_cmm_u_cmm_decoder_un11_bar5_32_hit_nc_1_and_0_a2_0_a2_0_a2_0_a2 ( + .I0(cfg_cfg_5072[228]), + .I1(cfg_cfg_5072[229]), + .I2(cfg_cfg_5072[230]), + .I3(cfg_cfg_5072[231]), + .O(com_cmm_u_cmm_decoder_un11_bar5_32_hit_nc_1_and) + ); + defparam com_cmm_u_cmm_decoder_un11_bar5_32_hit_nc_0_and_0_a2_0_a2.INIT = 16'h0001; + LUT4 com_cmm_u_cmm_decoder_un11_bar5_32_hit_nc_0_and_0_a2_0_a2 ( + .I0(cfg_cfg_5072[224]), + .I1(cfg_cfg_5072[225]), + .I2(cfg_cfg_5072[226]), + .I3(cfg_cfg_5072[227]), + .O(com_cmm_u_cmm_decoder_un11_bar5_32_hit_nc_0_and) + ); + defparam com_cmm_u_cmm_decoder_un9_bar34_64_hit_high_0_I_126.INIT = 16'h0903; + LUT4 com_cmm_u_cmm_decoder_un9_bar34_64_hit_high_0_I_126 ( + .I0(cfg_cfg_5072[168]), + .I1(com_cmm_bar3_reg[8]), + .I2(com_cmm_u_cmm_decoder_N_6_8), + .I3(com_cmmt_raddr[8]), + .O(com_cmm_u_cmm_decoder_N_3_13) + ); + defparam com_cmm_u_cmm_decoder_un9_bar34_64_hit_high_0_I_117.INIT = 16'h0903; + LUT4 com_cmm_u_cmm_decoder_un9_bar34_64_hit_high_0_I_117 ( + .I0(cfg_cfg_5072[188]), + .I1(com_cmm_bar3_reg[28]), + .I2(com_cmm_u_cmm_decoder_N_14_9), + .I3(com_cmmt_raddr[28]), + .O(com_cmm_u_cmm_decoder_N_11_14) + ); + defparam com_cmm_u_cmm_decoder_un9_bar34_64_hit_high_0_I_108.INIT = 16'h0903; + LUT4 com_cmm_u_cmm_decoder_un9_bar34_64_hit_high_0_I_108 ( + .I0(cfg_cfg_5072[186]), + .I1(com_cmm_bar3_reg[26]), + .I2(com_cmm_u_cmm_decoder_N_22_8), + .I3(com_cmmt_raddr[26]), + .O(com_cmm_u_cmm_decoder_N_19_13) + ); + defparam com_cmm_u_cmm_decoder_un9_bar34_64_hit_high_0_I_99.INIT = 16'h0903; + LUT4 com_cmm_u_cmm_decoder_un9_bar34_64_hit_high_0_I_99 ( + .I0(cfg_cfg_5072[166]), + .I1(com_cmm_bar3_reg[6]), + .I2(com_cmm_u_cmm_decoder_N_30_7), + .I3(com_cmmt_raddr[6]), + .O(com_cmm_u_cmm_decoder_N_27_13) + ); + defparam com_cmm_u_cmm_decoder_un9_bar34_64_hit_high_0_I_90.INIT = 16'h0903; + LUT4 com_cmm_u_cmm_decoder_un9_bar34_64_hit_high_0_I_90 ( + .I0(cfg_cfg_5072[176]), + .I1(com_cmm_bar3_reg[16]), + .I2(com_cmm_u_cmm_decoder_N_38_8), + .I3(com_cmmt_raddr[16]), + .O(com_cmm_u_cmm_decoder_N_35_13) + ); + defparam com_cmm_u_cmm_decoder_un9_bar34_64_hit_high_0_I_81.INIT = 16'h0903; + LUT4 com_cmm_u_cmm_decoder_un9_bar34_64_hit_high_0_I_81 ( + .I0(cfg_cfg_5072[180]), + .I1(com_cmm_bar3_reg[20]), + .I2(com_cmm_u_cmm_decoder_N_46_8), + .I3(com_cmmt_raddr[20]), + .O(com_cmm_u_cmm_decoder_N_43_13) + ); + defparam com_cmm_u_cmm_decoder_un9_bar34_64_hit_high_0_I_72.INIT = 16'h0903; + LUT4 com_cmm_u_cmm_decoder_un9_bar34_64_hit_high_0_I_72 ( + .I0(cfg_cfg_5072[178]), + .I1(com_cmm_bar3_reg[18]), + .I2(com_cmm_u_cmm_decoder_N_54_8), + .I3(com_cmmt_raddr[18]), + .O(com_cmm_u_cmm_decoder_N_51_13) + ); + defparam com_cmm_u_cmm_decoder_un9_bar34_64_hit_high_0_I_63.INIT = 16'h0903; + LUT4 com_cmm_u_cmm_decoder_un9_bar34_64_hit_high_0_I_63 ( + .I0(cfg_cfg_5072[174]), + .I1(com_cmm_bar3_reg[14]), + .I2(com_cmm_u_cmm_decoder_N_62_8), + .I3(com_cmmt_raddr[14]), + .O(com_cmm_u_cmm_decoder_N_59_13) + ); + defparam com_cmm_u_cmm_decoder_un9_bar34_64_hit_high_0_I_54.INIT = 16'h0903; + LUT4 com_cmm_u_cmm_decoder_un9_bar34_64_hit_high_0_I_54 ( + .I0(cfg_cfg_5072[184]), + .I1(com_cmm_bar3_reg[24]), + .I2(com_cmm_u_cmm_decoder_N_70_8), + .I3(com_cmmt_raddr[24]), + .O(com_cmm_u_cmm_decoder_N_67_13) + ); + defparam com_cmm_u_cmm_decoder_un9_bar34_64_hit_high_0_I_45.INIT = 16'h0903; + LUT4 com_cmm_u_cmm_decoder_un9_bar34_64_hit_high_0_I_45 ( + .I0(cfg_cfg_5072[172]), + .I1(com_cmm_bar3_reg[12]), + .I2(com_cmm_u_cmm_decoder_N_78_8), + .I3(com_cmmt_raddr[12]), + .O(com_cmm_u_cmm_decoder_N_75_13) + ); + defparam com_cmm_u_cmm_decoder_un9_bar34_64_hit_high_0_I_36.INIT = 16'h0903; + LUT4 com_cmm_u_cmm_decoder_un9_bar34_64_hit_high_0_I_36 ( + .I0(cfg_cfg_5072[170]), + .I1(com_cmm_bar3_reg[10]), + .I2(com_cmm_u_cmm_decoder_N_86_8), + .I3(com_cmmt_raddr[10]), + .O(com_cmm_u_cmm_decoder_N_83_13) + ); + defparam com_cmm_u_cmm_decoder_un9_bar34_64_hit_high_0_I_27.INIT = 16'h0903; + LUT4 com_cmm_u_cmm_decoder_un9_bar34_64_hit_high_0_I_27 ( + .I0(cfg_cfg_5072[182]), + .I1(com_cmm_bar3_reg[22]), + .I2(com_cmm_u_cmm_decoder_N_94_8), + .I3(com_cmmt_raddr[22]), + .O(com_cmm_u_cmm_decoder_N_91_13) + ); + defparam com_cmm_u_cmm_decoder_un9_bar34_64_hit_high_0_I_9.INIT = 16'h0903; + LUT4 com_cmm_u_cmm_decoder_un9_bar34_64_hit_high_0_I_9 ( + .I0(cfg_cfg_5072[164]), + .I1(com_cmm_bar3_reg[4]), + .I2(com_cmm_u_cmm_decoder_N_110_5), + .I3(com_cmmt_raddr[4]), + .O(com_cmm_u_cmm_decoder_N_107_12) + ); + defparam com_cmm_u_cmm_decoder_un9_bar23_64_hit_high_0_I_126.INIT = 16'h0903; + LUT4 com_cmm_u_cmm_decoder_un9_bar23_64_hit_high_0_I_126 ( + .I0(cfg_cfg_5072[136]), + .I1(com_cmm_bar2_reg[8]), + .I2(com_cmm_u_cmm_decoder_N_6_7), + .I3(com_cmmt_raddr[8]), + .O(com_cmm_u_cmm_decoder_N_3_12) + ); + defparam com_cmm_u_cmm_decoder_un9_bar23_64_hit_high_0_I_117.INIT = 16'h0903; + LUT4 com_cmm_u_cmm_decoder_un9_bar23_64_hit_high_0_I_117 ( + .I0(cfg_cfg_5072[156]), + .I1(com_cmm_bar2_reg[28]), + .I2(com_cmm_u_cmm_decoder_N_14_8), + .I3(com_cmmt_raddr[28]), + .O(com_cmm_u_cmm_decoder_N_11_13) + ); + defparam com_cmm_u_cmm_decoder_un9_bar23_64_hit_high_0_I_108.INIT = 16'h0903; + LUT4 com_cmm_u_cmm_decoder_un9_bar23_64_hit_high_0_I_108 ( + .I0(cfg_cfg_5072[154]), + .I1(com_cmm_bar2_reg[26]), + .I2(com_cmm_u_cmm_decoder_N_22_7), + .I3(com_cmmt_raddr[26]), + .O(com_cmm_u_cmm_decoder_N_19_12) + ); + defparam com_cmm_u_cmm_decoder_un9_bar23_64_hit_high_0_I_99.INIT = 16'h0903; + LUT4 com_cmm_u_cmm_decoder_un9_bar23_64_hit_high_0_I_99 ( + .I0(cfg_cfg_5072[134]), + .I1(com_cmm_bar2_reg[6]), + .I2(com_cmm_u_cmm_decoder_N_30_6), + .I3(com_cmmt_raddr[6]), + .O(com_cmm_u_cmm_decoder_N_27_12) + ); + defparam com_cmm_u_cmm_decoder_un9_bar23_64_hit_high_0_I_90.INIT = 16'h0903; + LUT4 com_cmm_u_cmm_decoder_un9_bar23_64_hit_high_0_I_90 ( + .I0(cfg_cfg_5072[144]), + .I1(com_cmm_bar2_reg[16]), + .I2(com_cmm_u_cmm_decoder_N_38_7), + .I3(com_cmmt_raddr[16]), + .O(com_cmm_u_cmm_decoder_N_35_12) + ); + defparam com_cmm_u_cmm_decoder_un9_bar23_64_hit_high_0_I_81.INIT = 16'h0903; + LUT4 com_cmm_u_cmm_decoder_un9_bar23_64_hit_high_0_I_81 ( + .I0(cfg_cfg_5072[148]), + .I1(com_cmm_bar2_reg[20]), + .I2(com_cmm_u_cmm_decoder_N_46_7), + .I3(com_cmmt_raddr[20]), + .O(com_cmm_u_cmm_decoder_N_43_12) + ); + defparam com_cmm_u_cmm_decoder_un9_bar23_64_hit_high_0_I_72.INIT = 16'h0903; + LUT4 com_cmm_u_cmm_decoder_un9_bar23_64_hit_high_0_I_72 ( + .I0(cfg_cfg_5072[146]), + .I1(com_cmm_bar2_reg[18]), + .I2(com_cmm_u_cmm_decoder_N_54_7), + .I3(com_cmmt_raddr[18]), + .O(com_cmm_u_cmm_decoder_N_51_12) + ); + defparam com_cmm_u_cmm_decoder_un9_bar23_64_hit_high_0_I_63.INIT = 16'h0903; + LUT4 com_cmm_u_cmm_decoder_un9_bar23_64_hit_high_0_I_63 ( + .I0(cfg_cfg_5072[142]), + .I1(com_cmm_bar2_reg[14]), + .I2(com_cmm_u_cmm_decoder_N_62_7), + .I3(com_cmmt_raddr[14]), + .O(com_cmm_u_cmm_decoder_N_59_12) + ); + defparam com_cmm_u_cmm_decoder_un9_bar23_64_hit_high_0_I_54.INIT = 16'h0903; + LUT4 com_cmm_u_cmm_decoder_un9_bar23_64_hit_high_0_I_54 ( + .I0(cfg_cfg_5072[152]), + .I1(com_cmm_bar2_reg[24]), + .I2(com_cmm_u_cmm_decoder_N_70_7), + .I3(com_cmmt_raddr[24]), + .O(com_cmm_u_cmm_decoder_N_67_12) + ); + defparam com_cmm_u_cmm_decoder_un9_bar23_64_hit_high_0_I_45.INIT = 16'h0903; + LUT4 com_cmm_u_cmm_decoder_un9_bar23_64_hit_high_0_I_45 ( + .I0(cfg_cfg_5072[140]), + .I1(com_cmm_bar2_reg[12]), + .I2(com_cmm_u_cmm_decoder_N_78_7), + .I3(com_cmmt_raddr[12]), + .O(com_cmm_u_cmm_decoder_N_75_12) + ); + defparam com_cmm_u_cmm_decoder_un9_bar23_64_hit_high_0_I_36.INIT = 16'h0903; + LUT4 com_cmm_u_cmm_decoder_un9_bar23_64_hit_high_0_I_36 ( + .I0(cfg_cfg_5072[138]), + .I1(com_cmm_bar2_reg[10]), + .I2(com_cmm_u_cmm_decoder_N_86_7), + .I3(com_cmmt_raddr[10]), + .O(com_cmm_u_cmm_decoder_N_83_12) + ); + defparam com_cmm_u_cmm_decoder_un9_bar23_64_hit_high_0_I_27.INIT = 16'h0903; + LUT4 com_cmm_u_cmm_decoder_un9_bar23_64_hit_high_0_I_27 ( + .I0(cfg_cfg_5072[150]), + .I1(com_cmm_bar2_reg[22]), + .I2(com_cmm_u_cmm_decoder_N_94_7), + .I3(com_cmmt_raddr[22]), + .O(com_cmm_u_cmm_decoder_N_91_12) + ); + defparam com_cmm_u_cmm_decoder_un9_bar23_64_hit_high_0_I_9.INIT = 16'h0903; + LUT4 com_cmm_u_cmm_decoder_un9_bar23_64_hit_high_0_I_9 ( + .I0(cfg_cfg_5072[132]), + .I1(com_cmm_bar2_reg[4]), + .I2(com_cmm_u_cmm_decoder_N_110_4), + .I3(com_cmmt_raddr[4]), + .O(com_cmm_u_cmm_decoder_N_107_11) + ); + defparam com_cmm_u_cmm_decoder_un9_bar12_64_hit_high_0_I_126.INIT = 16'h0903; + LUT4 com_cmm_u_cmm_decoder_un9_bar12_64_hit_high_0_I_126 ( + .I0(cfg_cfg_5072[104]), + .I1(com_cmm_bar1_reg[8]), + .I2(com_cmm_u_cmm_decoder_N_6_6), + .I3(com_cmmt_raddr[8]), + .O(com_cmm_u_cmm_decoder_N_3_11) + ); + defparam com_cmm_u_cmm_decoder_un9_bar12_64_hit_high_0_I_117.INIT = 16'h0903; + LUT4 com_cmm_u_cmm_decoder_un9_bar12_64_hit_high_0_I_117 ( + .I0(cfg_cfg_5072[124]), + .I1(com_cmm_bar1_reg[28]), + .I2(com_cmm_u_cmm_decoder_N_14_7), + .I3(com_cmmt_raddr[28]), + .O(com_cmm_u_cmm_decoder_N_11_12) + ); + defparam com_cmm_u_cmm_decoder_un9_bar12_64_hit_high_0_I_108.INIT = 16'h0903; + LUT4 com_cmm_u_cmm_decoder_un9_bar12_64_hit_high_0_I_108 ( + .I0(cfg_cfg_5072[122]), + .I1(com_cmm_bar1_reg[26]), + .I2(com_cmm_u_cmm_decoder_N_22_6), + .I3(com_cmmt_raddr[26]), + .O(com_cmm_u_cmm_decoder_N_19_11) + ); + defparam com_cmm_u_cmm_decoder_un9_bar12_64_hit_high_0_I_99.INIT = 16'h0903; + LUT4 com_cmm_u_cmm_decoder_un9_bar12_64_hit_high_0_I_99 ( + .I0(cfg_cfg_5072[102]), + .I1(com_cmm_bar1_reg[6]), + .I2(com_cmm_u_cmm_decoder_N_30_5), + .I3(com_cmmt_raddr[6]), + .O(com_cmm_u_cmm_decoder_N_27_11) + ); + defparam com_cmm_u_cmm_decoder_un9_bar12_64_hit_high_0_I_90.INIT = 16'h0903; + LUT4 com_cmm_u_cmm_decoder_un9_bar12_64_hit_high_0_I_90 ( + .I0(cfg_cfg_5072[112]), + .I1(com_cmm_bar1_reg[16]), + .I2(com_cmm_u_cmm_decoder_N_38_6), + .I3(com_cmmt_raddr[16]), + .O(com_cmm_u_cmm_decoder_N_35_11) + ); + defparam com_cmm_u_cmm_decoder_un9_bar12_64_hit_high_0_I_81.INIT = 16'h0903; + LUT4 com_cmm_u_cmm_decoder_un9_bar12_64_hit_high_0_I_81 ( + .I0(cfg_cfg_5072[116]), + .I1(com_cmm_bar1_reg[20]), + .I2(com_cmm_u_cmm_decoder_N_46_6), + .I3(com_cmmt_raddr[20]), + .O(com_cmm_u_cmm_decoder_N_43_11) + ); + defparam com_cmm_u_cmm_decoder_un9_bar12_64_hit_high_0_I_72.INIT = 16'h0903; + LUT4 com_cmm_u_cmm_decoder_un9_bar12_64_hit_high_0_I_72 ( + .I0(cfg_cfg_5072[114]), + .I1(com_cmm_bar1_reg[18]), + .I2(com_cmm_u_cmm_decoder_N_54_6), + .I3(com_cmmt_raddr[18]), + .O(com_cmm_u_cmm_decoder_N_51_11) + ); + defparam com_cmm_u_cmm_decoder_un9_bar12_64_hit_high_0_I_63.INIT = 16'h0903; + LUT4 com_cmm_u_cmm_decoder_un9_bar12_64_hit_high_0_I_63 ( + .I0(cfg_cfg_5072[110]), + .I1(com_cmm_bar1_reg[14]), + .I2(com_cmm_u_cmm_decoder_N_62_6), + .I3(com_cmmt_raddr[14]), + .O(com_cmm_u_cmm_decoder_N_59_11) + ); + defparam com_cmm_u_cmm_decoder_un9_bar12_64_hit_high_0_I_54.INIT = 16'h0903; + LUT4 com_cmm_u_cmm_decoder_un9_bar12_64_hit_high_0_I_54 ( + .I0(cfg_cfg_5072[120]), + .I1(com_cmm_bar1_reg[24]), + .I2(com_cmm_u_cmm_decoder_N_70_6), + .I3(com_cmmt_raddr[24]), + .O(com_cmm_u_cmm_decoder_N_67_11) + ); + defparam com_cmm_u_cmm_decoder_un9_bar12_64_hit_high_0_I_45.INIT = 16'h0903; + LUT4 com_cmm_u_cmm_decoder_un9_bar12_64_hit_high_0_I_45 ( + .I0(cfg_cfg_5072[108]), + .I1(com_cmm_bar1_reg[12]), + .I2(com_cmm_u_cmm_decoder_N_78_6), + .I3(com_cmmt_raddr[12]), + .O(com_cmm_u_cmm_decoder_N_75_11) + ); + defparam com_cmm_u_cmm_decoder_un9_bar12_64_hit_high_0_I_36.INIT = 16'h0903; + LUT4 com_cmm_u_cmm_decoder_un9_bar12_64_hit_high_0_I_36 ( + .I0(cfg_cfg_5072[106]), + .I1(com_cmm_bar1_reg[10]), + .I2(com_cmm_u_cmm_decoder_N_86_6), + .I3(com_cmmt_raddr[10]), + .O(com_cmm_u_cmm_decoder_N_83_11) + ); + defparam com_cmm_u_cmm_decoder_un9_bar12_64_hit_high_0_I_27.INIT = 16'h0903; + LUT4 com_cmm_u_cmm_decoder_un9_bar12_64_hit_high_0_I_27 ( + .I0(cfg_cfg_5072[118]), + .I1(com_cmm_bar1_reg[22]), + .I2(com_cmm_u_cmm_decoder_N_94_6), + .I3(com_cmmt_raddr[22]), + .O(com_cmm_u_cmm_decoder_N_91_11) + ); + defparam com_cmm_u_cmm_decoder_un9_bar12_64_hit_high_0_I_9.INIT = 16'h0903; + LUT4 com_cmm_u_cmm_decoder_un9_bar12_64_hit_high_0_I_9 ( + .I0(cfg_cfg_5072[100]), + .I1(com_cmm_bar1_reg[4]), + .I2(com_cmm_u_cmm_decoder_N_110_3), + .I3(com_cmmt_raddr[4]), + .O(com_cmm_u_cmm_decoder_N_107_10) + ); + defparam com_cmm_u_cmm_decoder_un9_bar01_64_hit_high_0_I_126.INIT = 16'h0903; + LUT4 com_cmm_u_cmm_decoder_un9_bar01_64_hit_high_0_I_126 ( + .I0(cfg_cfg_5072[72]), + .I1(com_cmm_bar0_reg_8_), + .I2(com_cmm_u_cmm_decoder_N_6_5), + .I3(com_cmmt_raddr[8]), + .O(com_cmm_u_cmm_decoder_N_3_10) + ); + defparam com_cmm_u_cmm_decoder_un9_bar01_64_hit_high_0_I_117.INIT = 16'h0903; + LUT4 com_cmm_u_cmm_decoder_un9_bar01_64_hit_high_0_I_117 ( + .I0(cfg_cfg_5072[92]), + .I1(com_cmm_bar0_reg_28_), + .I2(com_cmm_u_cmm_decoder_N_14_6), + .I3(com_cmmt_raddr[28]), + .O(com_cmm_u_cmm_decoder_N_11_11) + ); + defparam com_cmm_u_cmm_decoder_un9_bar01_64_hit_high_0_I_108.INIT = 16'h0903; + LUT4 com_cmm_u_cmm_decoder_un9_bar01_64_hit_high_0_I_108 ( + .I0(cfg_cfg_5072[90]), + .I1(com_cmm_bar0_reg_26_), + .I2(com_cmm_u_cmm_decoder_N_22_5), + .I3(com_cmmt_raddr[26]), + .O(com_cmm_u_cmm_decoder_N_19_10) + ); + defparam com_cmm_u_cmm_decoder_un9_bar01_64_hit_high_0_I_99.INIT = 16'h0903; + LUT4 com_cmm_u_cmm_decoder_un9_bar01_64_hit_high_0_I_99 ( + .I0(cfg_cfg_5072[70]), + .I1(com_cmm_bar0_reg_6_), + .I2(com_cmm_u_cmm_decoder_N_30_4), + .I3(com_cmmt_raddr[6]), + .O(com_cmm_u_cmm_decoder_N_27_10) + ); + defparam com_cmm_u_cmm_decoder_un9_bar01_64_hit_high_0_I_90.INIT = 16'h0903; + LUT4 com_cmm_u_cmm_decoder_un9_bar01_64_hit_high_0_I_90 ( + .I0(cfg_cfg_5072[80]), + .I1(com_cmm_bar0_reg_16_), + .I2(com_cmm_u_cmm_decoder_N_38_5), + .I3(com_cmmt_raddr[16]), + .O(com_cmm_u_cmm_decoder_N_35_10) + ); + defparam com_cmm_u_cmm_decoder_un9_bar01_64_hit_high_0_I_81.INIT = 16'h0903; + LUT4 com_cmm_u_cmm_decoder_un9_bar01_64_hit_high_0_I_81 ( + .I0(cfg_cfg_5072[84]), + .I1(com_cmm_bar0_reg_20_), + .I2(com_cmm_u_cmm_decoder_N_46_5), + .I3(com_cmmt_raddr[20]), + .O(com_cmm_u_cmm_decoder_N_43_10) + ); + defparam com_cmm_u_cmm_decoder_un9_bar01_64_hit_high_0_I_72.INIT = 16'h0903; + LUT4 com_cmm_u_cmm_decoder_un9_bar01_64_hit_high_0_I_72 ( + .I0(cfg_cfg_5072[82]), + .I1(com_cmm_bar0_reg_18_), + .I2(com_cmm_u_cmm_decoder_N_54_5), + .I3(com_cmmt_raddr[18]), + .O(com_cmm_u_cmm_decoder_N_51_10) + ); + defparam com_cmm_u_cmm_decoder_un9_bar01_64_hit_high_0_I_63.INIT = 16'h0903; + LUT4 com_cmm_u_cmm_decoder_un9_bar01_64_hit_high_0_I_63 ( + .I0(cfg_cfg_5072[78]), + .I1(com_cmm_bar0_reg_14_), + .I2(com_cmm_u_cmm_decoder_N_62_5), + .I3(com_cmmt_raddr[14]), + .O(com_cmm_u_cmm_decoder_N_59_10) + ); + defparam com_cmm_u_cmm_decoder_un9_bar01_64_hit_high_0_I_54.INIT = 16'h0903; + LUT4 com_cmm_u_cmm_decoder_un9_bar01_64_hit_high_0_I_54 ( + .I0(cfg_cfg_5072[88]), + .I1(com_cmm_bar0_reg_24_), + .I2(com_cmm_u_cmm_decoder_N_70_5), + .I3(com_cmmt_raddr[24]), + .O(com_cmm_u_cmm_decoder_N_67_10) + ); + defparam com_cmm_u_cmm_decoder_un9_bar01_64_hit_high_0_I_45.INIT = 16'h0903; + LUT4 com_cmm_u_cmm_decoder_un9_bar01_64_hit_high_0_I_45 ( + .I0(cfg_cfg_5072[76]), + .I1(com_cmm_bar0_reg_12_), + .I2(com_cmm_u_cmm_decoder_N_78_5), + .I3(com_cmmt_raddr[12]), + .O(com_cmm_u_cmm_decoder_N_75_10) + ); + defparam com_cmm_u_cmm_decoder_un9_bar01_64_hit_high_0_I_36.INIT = 16'h0903; + LUT4 com_cmm_u_cmm_decoder_un9_bar01_64_hit_high_0_I_36 ( + .I0(cfg_cfg_5072[74]), + .I1(com_cmm_bar0_reg_10_), + .I2(com_cmm_u_cmm_decoder_N_86_5), + .I3(com_cmmt_raddr[10]), + .O(com_cmm_u_cmm_decoder_N_83_10) + ); + defparam com_cmm_u_cmm_decoder_un9_bar01_64_hit_high_0_I_27.INIT = 16'h0903; + LUT4 com_cmm_u_cmm_decoder_un9_bar01_64_hit_high_0_I_27 ( + .I0(cfg_cfg_5072[86]), + .I1(com_cmm_bar0_reg_22_), + .I2(com_cmm_u_cmm_decoder_N_94_5), + .I3(com_cmmt_raddr[22]), + .O(com_cmm_u_cmm_decoder_N_91_10) + ); + defparam com_cmm_u_cmm_decoder_un9_bar01_64_hit_high_0_I_9.INIT = 16'h0903; + LUT4 com_cmm_u_cmm_decoder_un9_bar01_64_hit_high_0_I_9 ( + .I0(cfg_cfg_5072[68]), + .I1(com_cmm_bar0_reg_4_), + .I2(com_cmm_u_cmm_decoder_N_110_2), + .I3(com_cmmt_raddr[4]), + .O(com_cmm_u_cmm_decoder_N_107_9) + ); + defparam com_cmm_u_cmm_decoder_bar6_eq_raddr_3_0_I_90.INIT = 16'h2103; + LUT4 com_cmm_u_cmm_decoder_bar6_eq_raddr_3_0_I_90 ( + .I0(cfg_cfg_5072[339]), + .I1(com_cmm_u_cmm_decoder_N_12), + .I2(com_cmm_xrom_reg_19_), + .I3(com_cmmt_raddr[51]), + .O(com_cmm_u_cmm_decoder_N_9) + ); + defparam com_cmm_u_cmm_decoder_bar6_eq_raddr_3_0_I_81.INIT = 16'h2103; + LUT4 com_cmm_u_cmm_decoder_bar6_eq_raddr_3_0_I_81 ( + .I0(cfg_cfg_5072[333]), + .I1(com_cmm_u_cmm_decoder_N_20), + .I2(com_cmm_xrom_reg_13_), + .I3(com_cmmt_raddr[45]), + .O(com_cmm_u_cmm_decoder_N_17) + ); + defparam com_cmm_u_cmm_decoder_bar6_eq_raddr_3_0_I_72.INIT = 16'h2103; + LUT4 com_cmm_u_cmm_decoder_bar6_eq_raddr_3_0_I_72 ( + .I0(cfg_cfg_5072[345]), + .I1(com_cmm_u_cmm_decoder_N_28), + .I2(com_cmm_xrom_reg_25_), + .I3(com_cmmt_raddr[57]), + .O(com_cmm_u_cmm_decoder_N_25) + ); + defparam com_cmm_u_cmm_decoder_bar6_eq_raddr_3_0_I_63.INIT = 16'h2103; + LUT4 com_cmm_u_cmm_decoder_bar6_eq_raddr_3_0_I_63 ( + .I0(cfg_cfg_5072[343]), + .I1(com_cmm_u_cmm_decoder_N_36), + .I2(com_cmm_xrom_reg_23_), + .I3(com_cmmt_raddr[55]), + .O(com_cmm_u_cmm_decoder_N_33) + ); + defparam com_cmm_u_cmm_decoder_bar6_eq_raddr_3_0_I_54.INIT = 16'h2103; + LUT4 com_cmm_u_cmm_decoder_bar6_eq_raddr_3_0_I_54 ( + .I0(cfg_cfg_5072[347]), + .I1(com_cmm_u_cmm_decoder_N_44), + .I2(com_cmm_xrom_reg_27_), + .I3(com_cmmt_raddr[59]), + .O(com_cmm_u_cmm_decoder_N_41) + ); + defparam com_cmm_u_cmm_decoder_bar6_eq_raddr_3_0_I_45.INIT = 16'h2103; + LUT4 com_cmm_u_cmm_decoder_bar6_eq_raddr_3_0_I_45 ( + .I0(cfg_cfg_5072[341]), + .I1(com_cmm_u_cmm_decoder_N_52), + .I2(com_cmm_xrom_reg_21_), + .I3(com_cmmt_raddr[53]), + .O(com_cmm_u_cmm_decoder_N_49) + ); + defparam com_cmm_u_cmm_decoder_bar6_eq_raddr_3_0_I_36.INIT = 16'h2103; + LUT4 com_cmm_u_cmm_decoder_bar6_eq_raddr_3_0_I_36 ( + .I0(cfg_cfg_5072[337]), + .I1(com_cmm_u_cmm_decoder_N_60), + .I2(com_cmm_xrom_reg_17_), + .I3(com_cmmt_raddr[49]), + .O(com_cmm_u_cmm_decoder_N_57) + ); + defparam com_cmm_u_cmm_decoder_bar6_eq_raddr_3_0_I_27.INIT = 16'h2103; + LUT4 com_cmm_u_cmm_decoder_bar6_eq_raddr_3_0_I_27 ( + .I0(cfg_cfg_5072[335]), + .I1(com_cmm_u_cmm_decoder_N_68), + .I2(com_cmm_xrom_reg_15_), + .I3(com_cmmt_raddr[47]), + .O(com_cmm_u_cmm_decoder_N_65) + ); + defparam com_cmm_u_cmm_decoder_bar6_eq_raddr_3_0_I_18.INIT = 16'h2103; + LUT4 com_cmm_u_cmm_decoder_bar6_eq_raddr_3_0_I_18 ( + .I0(cfg_cfg_5072[349]), + .I1(com_cmm_u_cmm_decoder_N_76), + .I2(com_cmm_xrom_reg_29_), + .I3(com_cmmt_raddr[61]), + .O(com_cmm_u_cmm_decoder_N_73) + ); + defparam com_cmm_u_cmm_decoder_bar6_eq_raddr_3_0_I_9.INIT = 16'h2103; + LUT4 com_cmm_u_cmm_decoder_bar6_eq_raddr_3_0_I_9 ( + .I0(cfg_cfg_5072[331]), + .I1(com_cmm_u_cmm_decoder_N_84), + .I2(com_cmm_xrom_reg_11_), + .I3(com_cmmt_raddr[43]), + .O(com_cmm_u_cmm_decoder_N_81) + ); + defparam com_cmm_u_cmm_decoder_bar5_eq_raddr_3_0_I_118_sf.INIT = 4'h2; + LUT1 com_cmm_u_cmm_decoder_bar5_eq_raddr_3_0_I_118_sf ( + .I0(com_cmm_u_cmm_decoder_N_3_9), + .O(com_cmm_u_cmm_decoder_I_118_sf) + ); + defparam com_cmm_u_cmm_decoder_bar5_eq_raddr_3_0_I_109_sf.INIT = 4'h2; + LUT1 com_cmm_u_cmm_decoder_bar5_eq_raddr_3_0_I_109_sf ( + .I0(com_cmm_u_cmm_decoder_N_11_10), + .O(com_cmm_u_cmm_decoder_I_109_sf) + ); + defparam com_cmm_u_cmm_decoder_bar5_eq_raddr_3_0_I_100_sf.INIT = 4'h2; + LUT1 com_cmm_u_cmm_decoder_bar5_eq_raddr_3_0_I_100_sf ( + .I0(com_cmm_u_cmm_decoder_N_19_9), + .O(com_cmm_u_cmm_decoder_I_100_sf) + ); + defparam com_cmm_u_cmm_decoder_bar5_eq_raddr_3_0_I_91_sf.INIT = 4'h2; + LUT1 com_cmm_u_cmm_decoder_bar5_eq_raddr_3_0_I_91_sf ( + .I0(com_cmm_u_cmm_decoder_N_27_9), + .O(com_cmm_u_cmm_decoder_I_91_sf) + ); + defparam com_cmm_u_cmm_decoder_bar5_eq_raddr_3_0_I_82_sf.INIT = 4'h2; + LUT1 com_cmm_u_cmm_decoder_bar5_eq_raddr_3_0_I_82_sf ( + .I0(com_cmm_u_cmm_decoder_N_35_9), + .O(com_cmm_u_cmm_decoder_I_82_sf) + ); + defparam com_cmm_u_cmm_decoder_bar5_eq_raddr_3_0_I_73_sf.INIT = 4'h2; + LUT1 com_cmm_u_cmm_decoder_bar5_eq_raddr_3_0_I_73_sf ( + .I0(com_cmm_u_cmm_decoder_N_43_9), + .O(com_cmm_u_cmm_decoder_I_73_sf) + ); + defparam com_cmm_u_cmm_decoder_bar5_eq_raddr_3_0_I_64_sf.INIT = 4'h2; + LUT1 com_cmm_u_cmm_decoder_bar5_eq_raddr_3_0_I_64_sf ( + .I0(com_cmm_u_cmm_decoder_N_51_9), + .O(com_cmm_u_cmm_decoder_I_64_sf) + ); + defparam com_cmm_u_cmm_decoder_bar5_eq_raddr_3_0_I_55_sf.INIT = 4'h2; + LUT1 com_cmm_u_cmm_decoder_bar5_eq_raddr_3_0_I_55_sf ( + .I0(com_cmm_u_cmm_decoder_N_59_9), + .O(com_cmm_u_cmm_decoder_I_55_sf) + ); + defparam com_cmm_u_cmm_decoder_bar5_eq_raddr_3_0_I_46_sf.INIT = 4'h2; + LUT1 com_cmm_u_cmm_decoder_bar5_eq_raddr_3_0_I_46_sf ( + .I0(com_cmm_u_cmm_decoder_N_67_9), + .O(com_cmm_u_cmm_decoder_I_46_sf) + ); + defparam com_cmm_u_cmm_decoder_bar5_eq_raddr_3_0_I_37_sf.INIT = 4'h2; + LUT1 com_cmm_u_cmm_decoder_bar5_eq_raddr_3_0_I_37_sf ( + .I0(com_cmm_u_cmm_decoder_N_75_9), + .O(com_cmm_u_cmm_decoder_I_37_sf) + ); + defparam com_cmm_u_cmm_decoder_bar5_eq_raddr_3_0_I_28_sf.INIT = 4'h2; + LUT1 com_cmm_u_cmm_decoder_bar5_eq_raddr_3_0_I_28_sf ( + .I0(com_cmm_u_cmm_decoder_N_83_9), + .O(com_cmm_u_cmm_decoder_I_28_sf) + ); + defparam com_cmm_u_cmm_decoder_bar5_eq_raddr_3_0_I_19_sf.INIT = 4'h2; + LUT1 com_cmm_u_cmm_decoder_bar5_eq_raddr_3_0_I_19_sf ( + .I0(com_cmm_u_cmm_decoder_N_91_9), + .O(com_cmm_u_cmm_decoder_I_19_sf) + ); + defparam com_cmm_u_cmm_decoder_bar4_eq_raddr_3_0_I_126.INIT = 4'h1; + LUT2 com_cmm_u_cmm_decoder_bar4_eq_raddr_3_0_I_126 ( + .I0(com_cmm_u_cmm_decoder_N_6), + .I1(com_cmm_u_cmm_decoder_N_7), + .O(com_cmm_u_cmm_decoder_N_3_8) + ); + defparam com_cmm_u_cmm_decoder_bar4_eq_raddr_3_0_I_117.INIT = 4'h1; + LUT2 com_cmm_u_cmm_decoder_bar4_eq_raddr_3_0_I_117 ( + .I0(com_cmm_u_cmm_decoder_N_14_0), + .I1(com_cmm_u_cmm_decoder_N_15), + .O(com_cmm_u_cmm_decoder_N_11_9) + ); + defparam com_cmm_u_cmm_decoder_bar4_eq_raddr_3_0_I_108.INIT = 4'h1; + LUT2 com_cmm_u_cmm_decoder_bar4_eq_raddr_3_0_I_108 ( + .I0(com_cmm_u_cmm_decoder_N_22), + .I1(com_cmm_u_cmm_decoder_N_23), + .O(com_cmm_u_cmm_decoder_N_19_8) + ); + defparam com_cmm_u_cmm_decoder_bar4_eq_raddr_3_0_I_99.INIT = 4'h1; + LUT2 com_cmm_u_cmm_decoder_bar4_eq_raddr_3_0_I_99 ( + .I0(com_cmm_u_cmm_decoder_N_30), + .I1(com_cmm_u_cmm_decoder_N_31), + .O(com_cmm_u_cmm_decoder_N_27_8) + ); + defparam com_cmm_u_cmm_decoder_bar4_eq_raddr_3_0_I_90.INIT = 16'h0903; + LUT4 com_cmm_u_cmm_decoder_bar4_eq_raddr_3_0_I_90 ( + .I0(cfg_cfg_5072[208]), + .I1(com_cmm_bar4_reg[16]), + .I2(com_cmm_u_cmm_decoder_N_38), + .I3(com_cmmt_raddr[48]), + .O(com_cmm_u_cmm_decoder_N_35_8) + ); + defparam com_cmm_u_cmm_decoder_bar4_eq_raddr_3_0_I_81.INIT = 4'h1; + LUT2 com_cmm_u_cmm_decoder_bar4_eq_raddr_3_0_I_81 ( + .I0(com_cmm_u_cmm_decoder_N_46), + .I1(com_cmm_u_cmm_decoder_N_47), + .O(com_cmm_u_cmm_decoder_N_43_8) + ); + defparam com_cmm_u_cmm_decoder_bar4_eq_raddr_3_0_I_72.INIT = 16'h0903; + LUT4 com_cmm_u_cmm_decoder_bar4_eq_raddr_3_0_I_72 ( + .I0(cfg_cfg_5072[210]), + .I1(com_cmm_bar4_reg[18]), + .I2(com_cmm_u_cmm_decoder_N_54), + .I3(com_cmmt_raddr[50]), + .O(com_cmm_u_cmm_decoder_N_51_8) + ); + defparam com_cmm_u_cmm_decoder_bar4_eq_raddr_3_0_I_63.INIT = 4'h1; + LUT2 com_cmm_u_cmm_decoder_bar4_eq_raddr_3_0_I_63 ( + .I0(com_cmm_u_cmm_decoder_N_62), + .I1(com_cmm_u_cmm_decoder_N_63), + .O(com_cmm_u_cmm_decoder_N_59_8) + ); + defparam com_cmm_u_cmm_decoder_bar4_eq_raddr_3_0_I_54.INIT = 4'h1; + LUT2 com_cmm_u_cmm_decoder_bar4_eq_raddr_3_0_I_54 ( + .I0(com_cmm_u_cmm_decoder_N_70), + .I1(com_cmm_u_cmm_decoder_N_71), + .O(com_cmm_u_cmm_decoder_N_67_8) + ); + defparam com_cmm_u_cmm_decoder_bar4_eq_raddr_3_0_I_45.INIT = 16'h0903; + LUT4 com_cmm_u_cmm_decoder_bar4_eq_raddr_3_0_I_45 ( + .I0(cfg_cfg_5072[204]), + .I1(com_cmm_bar4_reg[12]), + .I2(com_cmm_u_cmm_decoder_N_78), + .I3(com_cmmt_raddr[44]), + .O(com_cmm_u_cmm_decoder_N_75_8) + ); + defparam com_cmm_u_cmm_decoder_bar4_eq_raddr_3_0_I_36.INIT = 16'h0903; + LUT4 com_cmm_u_cmm_decoder_bar4_eq_raddr_3_0_I_36 ( + .I0(cfg_cfg_5072[202]), + .I1(com_cmm_bar4_reg[10]), + .I2(com_cmm_u_cmm_decoder_N_86), + .I3(com_cmmt_raddr[42]), + .O(com_cmm_u_cmm_decoder_N_83_8) + ); + defparam com_cmm_u_cmm_decoder_bar4_eq_raddr_3_0_I_27.INIT = 16'h0903; + LUT4 com_cmm_u_cmm_decoder_bar4_eq_raddr_3_0_I_27 ( + .I0(cfg_cfg_5072[214]), + .I1(com_cmm_bar4_reg[22]), + .I2(com_cmm_u_cmm_decoder_N_94), + .I3(com_cmmt_raddr[54]), + .O(com_cmm_u_cmm_decoder_N_91_8) + ); + defparam com_cmm_u_cmm_decoder_bar4_eq_raddr_3_0_I_9.INIT = 16'h0903; + LUT4 com_cmm_u_cmm_decoder_bar4_eq_raddr_3_0_I_9 ( + .I0(cfg_cfg_5072[197]), + .I1(com_cmm_bar4_reg[5]), + .I2(com_cmm_u_cmm_decoder_N_111), + .I3(com_cmmt_raddr[37]), + .O(com_cmm_u_cmm_decoder_N_107_8) + ); + defparam com_cmm_u_cmm_decoder_bar3_eq_raddr_3_0_I_126.INIT = 16'h0903; + LUT4 com_cmm_u_cmm_decoder_bar3_eq_raddr_3_0_I_126 ( + .I0(cfg_cfg_5072[168]), + .I1(com_cmm_bar3_reg[8]), + .I2(com_cmm_u_cmm_decoder_N_6_0), + .I3(com_cmmt_raddr[40]), + .O(com_cmm_u_cmm_decoder_N_3_7) + ); + defparam com_cmm_u_cmm_decoder_bar3_eq_raddr_3_0_I_117.INIT = 4'h1; + LUT2 com_cmm_u_cmm_decoder_bar3_eq_raddr_3_0_I_117 ( + .I0(com_cmm_u_cmm_decoder_N_14_1), + .I1(com_cmm_u_cmm_decoder_N_15_0), + .O(com_cmm_u_cmm_decoder_N_11_8) + ); + defparam com_cmm_u_cmm_decoder_bar3_eq_raddr_3_0_I_108.INIT = 16'h0903; + LUT4 com_cmm_u_cmm_decoder_bar3_eq_raddr_3_0_I_108 ( + .I0(cfg_cfg_5072[186]), + .I1(com_cmm_bar3_reg[26]), + .I2(com_cmm_u_cmm_decoder_N_22_0), + .I3(com_cmmt_raddr[58]), + .O(com_cmm_u_cmm_decoder_N_19_7) + ); + defparam com_cmm_u_cmm_decoder_bar3_eq_raddr_3_0_I_99.INIT = 16'h0903; + LUT4 com_cmm_u_cmm_decoder_bar3_eq_raddr_3_0_I_99 ( + .I0(cfg_cfg_5072[166]), + .I1(com_cmm_bar3_reg[6]), + .I2(com_cmm_u_cmm_decoder_N_30_0), + .I3(com_cmmt_raddr[38]), + .O(com_cmm_u_cmm_decoder_N_27_7) + ); + defparam com_cmm_u_cmm_decoder_bar3_eq_raddr_3_0_I_90.INIT = 4'h1; + LUT2 com_cmm_u_cmm_decoder_bar3_eq_raddr_3_0_I_90 ( + .I0(com_cmm_u_cmm_decoder_N_38_0), + .I1(com_cmm_u_cmm_decoder_N_39), + .O(com_cmm_u_cmm_decoder_N_35_7) + ); + defparam com_cmm_u_cmm_decoder_bar3_eq_raddr_3_0_I_81.INIT = 4'h1; + LUT2 com_cmm_u_cmm_decoder_bar3_eq_raddr_3_0_I_81 ( + .I0(com_cmm_u_cmm_decoder_N_46_0), + .I1(com_cmm_u_cmm_decoder_N_47_0), + .O(com_cmm_u_cmm_decoder_N_43_7) + ); + defparam com_cmm_u_cmm_decoder_bar3_eq_raddr_3_0_I_72.INIT = 16'h0903; + LUT4 com_cmm_u_cmm_decoder_bar3_eq_raddr_3_0_I_72 ( + .I0(cfg_cfg_5072[178]), + .I1(com_cmm_bar3_reg[18]), + .I2(com_cmm_u_cmm_decoder_N_54_0), + .I3(com_cmmt_raddr[50]), + .O(com_cmm_u_cmm_decoder_N_51_7) + ); + defparam com_cmm_u_cmm_decoder_bar3_eq_raddr_3_0_I_63.INIT = 4'h1; + LUT2 com_cmm_u_cmm_decoder_bar3_eq_raddr_3_0_I_63 ( + .I0(com_cmm_u_cmm_decoder_N_62_0), + .I1(com_cmm_u_cmm_decoder_N_63_0), + .O(com_cmm_u_cmm_decoder_N_59_7) + ); + defparam com_cmm_u_cmm_decoder_bar3_eq_raddr_3_0_I_54.INIT = 16'h0903; + LUT4 com_cmm_u_cmm_decoder_bar3_eq_raddr_3_0_I_54 ( + .I0(cfg_cfg_5072[184]), + .I1(com_cmm_bar3_reg[24]), + .I2(com_cmm_u_cmm_decoder_N_70_0), + .I3(com_cmmt_raddr[56]), + .O(com_cmm_u_cmm_decoder_N_67_7) + ); + defparam com_cmm_u_cmm_decoder_bar3_eq_raddr_3_0_I_45.INIT = 4'h1; + LUT2 com_cmm_u_cmm_decoder_bar3_eq_raddr_3_0_I_45 ( + .I0(com_cmm_u_cmm_decoder_N_78_0), + .I1(com_cmm_u_cmm_decoder_N_79), + .O(com_cmm_u_cmm_decoder_N_75_7) + ); + defparam com_cmm_u_cmm_decoder_bar3_eq_raddr_3_0_I_36.INIT = 16'h0903; + LUT4 com_cmm_u_cmm_decoder_bar3_eq_raddr_3_0_I_36 ( + .I0(cfg_cfg_5072[170]), + .I1(com_cmm_bar3_reg[10]), + .I2(com_cmm_u_cmm_decoder_N_86_0), + .I3(com_cmmt_raddr[42]), + .O(com_cmm_u_cmm_decoder_N_83_7) + ); + defparam com_cmm_u_cmm_decoder_bar3_eq_raddr_3_0_I_27.INIT = 16'h0903; + LUT4 com_cmm_u_cmm_decoder_bar3_eq_raddr_3_0_I_27 ( + .I0(cfg_cfg_5072[182]), + .I1(com_cmm_bar3_reg[22]), + .I2(com_cmm_u_cmm_decoder_N_94_0), + .I3(com_cmmt_raddr[54]), + .O(com_cmm_u_cmm_decoder_N_91_7) + ); + defparam com_cmm_u_cmm_decoder_bar3_eq_raddr_3_0_I_9.INIT = 4'h1; + LUT2 com_cmm_u_cmm_decoder_bar3_eq_raddr_3_0_I_9 ( + .I0(com_cmm_u_cmm_decoder_N_110), + .I1(com_cmm_u_cmm_decoder_N_111_0), + .O(com_cmm_u_cmm_decoder_N_107_7) + ); + defparam com_cmm_u_cmm_decoder_bar2_eq_raddr_3_0_I_126.INIT = 4'h1; + LUT2 com_cmm_u_cmm_decoder_bar2_eq_raddr_3_0_I_126 ( + .I0(com_cmm_u_cmm_decoder_N_6_1), + .I1(com_cmm_u_cmm_decoder_N_7_0), + .O(com_cmm_u_cmm_decoder_N_3_6) + ); + defparam com_cmm_u_cmm_decoder_bar2_eq_raddr_3_0_I_117.INIT = 4'h1; + LUT2 com_cmm_u_cmm_decoder_bar2_eq_raddr_3_0_I_117 ( + .I0(com_cmm_u_cmm_decoder_N_14_2), + .I1(com_cmm_u_cmm_decoder_N_15_1), + .O(com_cmm_u_cmm_decoder_N_11_7) + ); + defparam com_cmm_u_cmm_decoder_bar2_eq_raddr_3_0_I_108.INIT = 16'h0903; + LUT4 com_cmm_u_cmm_decoder_bar2_eq_raddr_3_0_I_108 ( + .I0(cfg_cfg_5072[154]), + .I1(com_cmm_bar2_reg[26]), + .I2(com_cmm_u_cmm_decoder_N_22_1), + .I3(com_cmmt_raddr[58]), + .O(com_cmm_u_cmm_decoder_N_19_6) + ); + defparam com_cmm_u_cmm_decoder_bar2_eq_raddr_3_0_I_99.INIT = 16'h0903; + LUT4 com_cmm_u_cmm_decoder_bar2_eq_raddr_3_0_I_99 ( + .I0(cfg_cfg_5072[135]), + .I1(com_cmm_bar2_reg[7]), + .I2(com_cmm_u_cmm_decoder_N_31_0), + .I3(com_cmmt_raddr[39]), + .O(com_cmm_u_cmm_decoder_N_27_6) + ); + defparam com_cmm_u_cmm_decoder_bar2_eq_raddr_3_0_I_90.INIT = 4'h1; + LUT2 com_cmm_u_cmm_decoder_bar2_eq_raddr_3_0_I_90 ( + .I0(com_cmm_u_cmm_decoder_N_38_1), + .I1(com_cmm_u_cmm_decoder_N_39_0), + .O(com_cmm_u_cmm_decoder_N_35_6) + ); + defparam com_cmm_u_cmm_decoder_bar2_eq_raddr_3_0_I_81.INIT = 16'h0903; + LUT4 com_cmm_u_cmm_decoder_bar2_eq_raddr_3_0_I_81 ( + .I0(cfg_cfg_5072[148]), + .I1(com_cmm_bar2_reg[20]), + .I2(com_cmm_u_cmm_decoder_N_46_1), + .I3(com_cmmt_raddr[52]), + .O(com_cmm_u_cmm_decoder_N_43_6) + ); + defparam com_cmm_u_cmm_decoder_bar2_eq_raddr_3_0_I_72.INIT = 16'h0903; + LUT4 com_cmm_u_cmm_decoder_bar2_eq_raddr_3_0_I_72 ( + .I0(cfg_cfg_5072[146]), + .I1(com_cmm_bar2_reg[18]), + .I2(com_cmm_u_cmm_decoder_N_54_1), + .I3(com_cmmt_raddr[50]), + .O(com_cmm_u_cmm_decoder_N_51_6) + ); + defparam com_cmm_u_cmm_decoder_bar2_eq_raddr_3_0_I_63.INIT = 4'h1; + LUT2 com_cmm_u_cmm_decoder_bar2_eq_raddr_3_0_I_63 ( + .I0(com_cmm_u_cmm_decoder_N_62_1), + .I1(com_cmm_u_cmm_decoder_N_63_1), + .O(com_cmm_u_cmm_decoder_N_59_6) + ); + defparam com_cmm_u_cmm_decoder_bar2_eq_raddr_3_0_I_54.INIT = 16'h0903; + LUT4 com_cmm_u_cmm_decoder_bar2_eq_raddr_3_0_I_54 ( + .I0(cfg_cfg_5072[152]), + .I1(com_cmm_bar2_reg[24]), + .I2(com_cmm_u_cmm_decoder_N_70_1), + .I3(com_cmmt_raddr[56]), + .O(com_cmm_u_cmm_decoder_N_67_6) + ); + defparam com_cmm_u_cmm_decoder_bar2_eq_raddr_3_0_I_45.INIT = 4'h1; + LUT2 com_cmm_u_cmm_decoder_bar2_eq_raddr_3_0_I_45 ( + .I0(com_cmm_u_cmm_decoder_N_78_1), + .I1(com_cmm_u_cmm_decoder_N_79_0), + .O(com_cmm_u_cmm_decoder_N_75_6) + ); + defparam com_cmm_u_cmm_decoder_bar2_eq_raddr_3_0_I_36.INIT = 16'h0903; + LUT4 com_cmm_u_cmm_decoder_bar2_eq_raddr_3_0_I_36 ( + .I0(cfg_cfg_5072[138]), + .I1(com_cmm_bar2_reg[10]), + .I2(com_cmm_u_cmm_decoder_N_86_1), + .I3(com_cmmt_raddr[42]), + .O(com_cmm_u_cmm_decoder_N_83_6) + ); + defparam com_cmm_u_cmm_decoder_bar2_eq_raddr_3_0_I_27.INIT = 16'h0903; + LUT4 com_cmm_u_cmm_decoder_bar2_eq_raddr_3_0_I_27 ( + .I0(cfg_cfg_5072[150]), + .I1(com_cmm_bar2_reg[22]), + .I2(com_cmm_u_cmm_decoder_N_94_1), + .I3(com_cmmt_raddr[54]), + .O(com_cmm_u_cmm_decoder_N_91_6) + ); + defparam com_cmm_u_cmm_decoder_bar2_eq_raddr_3_0_I_9.INIT = 16'h0903; + LUT4 com_cmm_u_cmm_decoder_bar2_eq_raddr_3_0_I_9 ( + .I0(cfg_cfg_5072[133]), + .I1(com_cmm_bar2_reg[5]), + .I2(com_cmm_u_cmm_decoder_N_111_1), + .I3(com_cmmt_raddr[37]), + .O(com_cmm_u_cmm_decoder_N_107_6) + ); + defparam com_cmm_u_cmm_decoder_bar1_eq_raddr_3_0_I_126.INIT = 16'h0903; + LUT4 com_cmm_u_cmm_decoder_bar1_eq_raddr_3_0_I_126 ( + .I0(cfg_cfg_5072[104]), + .I1(com_cmm_bar1_reg[8]), + .I2(com_cmm_u_cmm_decoder_N_6_2), + .I3(com_cmmt_raddr[40]), + .O(com_cmm_u_cmm_decoder_N_3_5) + ); + defparam com_cmm_u_cmm_decoder_bar1_eq_raddr_3_0_I_117.INIT = 4'h1; + LUT2 com_cmm_u_cmm_decoder_bar1_eq_raddr_3_0_I_117 ( + .I0(com_cmm_u_cmm_decoder_N_14_3), + .I1(com_cmm_u_cmm_decoder_N_15_2), + .O(com_cmm_u_cmm_decoder_N_11_6) + ); + defparam com_cmm_u_cmm_decoder_bar1_eq_raddr_3_0_I_108.INIT = 16'h0903; + LUT4 com_cmm_u_cmm_decoder_bar1_eq_raddr_3_0_I_108 ( + .I0(cfg_cfg_5072[122]), + .I1(com_cmm_bar1_reg[26]), + .I2(com_cmm_u_cmm_decoder_N_22_2), + .I3(com_cmmt_raddr[58]), + .O(com_cmm_u_cmm_decoder_N_19_5) + ); + defparam com_cmm_u_cmm_decoder_bar1_eq_raddr_3_0_I_99.INIT = 4'h1; + LUT2 com_cmm_u_cmm_decoder_bar1_eq_raddr_3_0_I_99 ( + .I0(com_cmm_u_cmm_decoder_N_30_1), + .I1(com_cmm_u_cmm_decoder_N_31_1), + .O(com_cmm_u_cmm_decoder_N_27_5) + ); + defparam com_cmm_u_cmm_decoder_bar1_eq_raddr_3_0_I_90.INIT = 4'h1; + LUT2 com_cmm_u_cmm_decoder_bar1_eq_raddr_3_0_I_90 ( + .I0(com_cmm_u_cmm_decoder_N_38_2), + .I1(com_cmm_u_cmm_decoder_N_39_1), + .O(com_cmm_u_cmm_decoder_N_35_5) + ); + defparam com_cmm_u_cmm_decoder_bar1_eq_raddr_3_0_I_81.INIT = 4'h1; + LUT2 com_cmm_u_cmm_decoder_bar1_eq_raddr_3_0_I_81 ( + .I0(com_cmm_u_cmm_decoder_N_46_2), + .I1(com_cmm_u_cmm_decoder_N_47_1), + .O(com_cmm_u_cmm_decoder_N_43_5) + ); + defparam com_cmm_u_cmm_decoder_bar1_eq_raddr_3_0_I_72.INIT = 16'h0903; + LUT4 com_cmm_u_cmm_decoder_bar1_eq_raddr_3_0_I_72 ( + .I0(cfg_cfg_5072[114]), + .I1(com_cmm_bar1_reg[18]), + .I2(com_cmm_u_cmm_decoder_N_54_2), + .I3(com_cmmt_raddr[50]), + .O(com_cmm_u_cmm_decoder_N_51_5) + ); + defparam com_cmm_u_cmm_decoder_bar1_eq_raddr_3_0_I_63.INIT = 4'h1; + LUT2 com_cmm_u_cmm_decoder_bar1_eq_raddr_3_0_I_63 ( + .I0(com_cmm_u_cmm_decoder_N_62_2), + .I1(com_cmm_u_cmm_decoder_N_63_2), + .O(com_cmm_u_cmm_decoder_N_59_5) + ); + defparam com_cmm_u_cmm_decoder_bar1_eq_raddr_3_0_I_54.INIT = 16'h0903; + LUT4 com_cmm_u_cmm_decoder_bar1_eq_raddr_3_0_I_54 ( + .I0(cfg_cfg_5072[120]), + .I1(com_cmm_bar1_reg[24]), + .I2(com_cmm_u_cmm_decoder_N_70_2), + .I3(com_cmmt_raddr[56]), + .O(com_cmm_u_cmm_decoder_N_67_5) + ); + defparam com_cmm_u_cmm_decoder_bar1_eq_raddr_3_0_I_45.INIT = 16'h0903; + LUT4 com_cmm_u_cmm_decoder_bar1_eq_raddr_3_0_I_45 ( + .I0(cfg_cfg_5072[108]), + .I1(com_cmm_bar1_reg[12]), + .I2(com_cmm_u_cmm_decoder_N_78_2), + .I3(com_cmmt_raddr[44]), + .O(com_cmm_u_cmm_decoder_N_75_5) + ); + defparam com_cmm_u_cmm_decoder_bar1_eq_raddr_3_0_I_36.INIT = 16'h0903; + LUT4 com_cmm_u_cmm_decoder_bar1_eq_raddr_3_0_I_36 ( + .I0(cfg_cfg_5072[106]), + .I1(com_cmm_bar1_reg[10]), + .I2(com_cmm_u_cmm_decoder_N_86_2), + .I3(com_cmmt_raddr[42]), + .O(com_cmm_u_cmm_decoder_N_83_5) + ); + defparam com_cmm_u_cmm_decoder_bar1_eq_raddr_3_0_I_27.INIT = 16'h0903; + LUT4 com_cmm_u_cmm_decoder_bar1_eq_raddr_3_0_I_27 ( + .I0(cfg_cfg_5072[118]), + .I1(com_cmm_bar1_reg[22]), + .I2(com_cmm_u_cmm_decoder_N_94_2), + .I3(com_cmmt_raddr[54]), + .O(com_cmm_u_cmm_decoder_N_91_5) + ); + defparam com_cmm_u_cmm_decoder_bar1_eq_raddr_3_0_I_9.INIT = 16'h0903; + LUT4 com_cmm_u_cmm_decoder_bar1_eq_raddr_3_0_I_9 ( + .I0(cfg_cfg_5072[101]), + .I1(com_cmm_bar1_reg[5]), + .I2(com_cmm_u_cmm_decoder_N_111_2), + .I3(com_cmmt_raddr[37]), + .O(com_cmm_u_cmm_decoder_N_107_5) + ); + defparam com_cmm_u_cmm_decoder_bar0_eq_raddr_3_0_I_126.INIT = 16'h0903; + LUT4 com_cmm_u_cmm_decoder_bar0_eq_raddr_3_0_I_126 ( + .I0(cfg_cfg_5072[72]), + .I1(com_cmm_bar0_reg_8_), + .I2(com_cmm_u_cmm_decoder_N_6_4), + .I3(com_cmmt_raddr[40]), + .O(com_cmm_u_cmm_decoder_N_3_4) + ); + defparam com_cmm_u_cmm_decoder_bar0_eq_raddr_3_0_I_117.INIT = 16'h0903; + LUT4 com_cmm_u_cmm_decoder_bar0_eq_raddr_3_0_I_117 ( + .I0(cfg_cfg_5072[92]), + .I1(com_cmm_bar0_reg_28_), + .I2(com_cmm_u_cmm_decoder_N_14_5), + .I3(com_cmmt_raddr[60]), + .O(com_cmm_u_cmm_decoder_N_11_5) + ); + defparam com_cmm_u_cmm_decoder_bar0_eq_raddr_3_0_I_108.INIT = 16'h0903; + LUT4 com_cmm_u_cmm_decoder_bar0_eq_raddr_3_0_I_108 ( + .I0(cfg_cfg_5072[90]), + .I1(com_cmm_bar0_reg_26_), + .I2(com_cmm_u_cmm_decoder_N_22_4), + .I3(com_cmmt_raddr[58]), + .O(com_cmm_u_cmm_decoder_N_19_4) + ); + defparam com_cmm_u_cmm_decoder_bar0_eq_raddr_3_0_I_99.INIT = 16'h0903; + LUT4 com_cmm_u_cmm_decoder_bar0_eq_raddr_3_0_I_99 ( + .I0(cfg_cfg_5072[70]), + .I1(com_cmm_bar0_reg_6_), + .I2(com_cmm_u_cmm_decoder_N_30_3), + .I3(com_cmmt_raddr[38]), + .O(com_cmm_u_cmm_decoder_N_27_4) + ); + defparam com_cmm_u_cmm_decoder_bar0_eq_raddr_3_0_I_90.INIT = 16'h0903; + LUT4 com_cmm_u_cmm_decoder_bar0_eq_raddr_3_0_I_90 ( + .I0(cfg_cfg_5072[80]), + .I1(com_cmm_bar0_reg_16_), + .I2(com_cmm_u_cmm_decoder_N_38_4), + .I3(com_cmmt_raddr[48]), + .O(com_cmm_u_cmm_decoder_N_35_4) + ); + defparam com_cmm_u_cmm_decoder_bar0_eq_raddr_3_0_I_81.INIT = 16'h0903; + LUT4 com_cmm_u_cmm_decoder_bar0_eq_raddr_3_0_I_81 ( + .I0(cfg_cfg_5072[84]), + .I1(com_cmm_bar0_reg_20_), + .I2(com_cmm_u_cmm_decoder_N_46_4), + .I3(com_cmmt_raddr[52]), + .O(com_cmm_u_cmm_decoder_N_43_4) + ); + defparam com_cmm_u_cmm_decoder_bar0_eq_raddr_3_0_I_72.INIT = 16'h0903; + LUT4 com_cmm_u_cmm_decoder_bar0_eq_raddr_3_0_I_72 ( + .I0(cfg_cfg_5072[82]), + .I1(com_cmm_bar0_reg_18_), + .I2(com_cmm_u_cmm_decoder_N_54_4), + .I3(com_cmmt_raddr[50]), + .O(com_cmm_u_cmm_decoder_N_51_4) + ); + defparam com_cmm_u_cmm_decoder_bar0_eq_raddr_3_0_I_63.INIT = 16'h0903; + LUT4 com_cmm_u_cmm_decoder_bar0_eq_raddr_3_0_I_63 ( + .I0(cfg_cfg_5072[78]), + .I1(com_cmm_bar0_reg_14_), + .I2(com_cmm_u_cmm_decoder_N_62_4), + .I3(com_cmmt_raddr[46]), + .O(com_cmm_u_cmm_decoder_N_59_4) + ); + defparam com_cmm_u_cmm_decoder_bar0_eq_raddr_3_0_I_54.INIT = 16'h0903; + LUT4 com_cmm_u_cmm_decoder_bar0_eq_raddr_3_0_I_54 ( + .I0(cfg_cfg_5072[88]), + .I1(com_cmm_bar0_reg_24_), + .I2(com_cmm_u_cmm_decoder_N_70_4), + .I3(com_cmmt_raddr[56]), + .O(com_cmm_u_cmm_decoder_N_67_4) + ); + defparam com_cmm_u_cmm_decoder_bar0_eq_raddr_3_0_I_45.INIT = 16'h0903; + LUT4 com_cmm_u_cmm_decoder_bar0_eq_raddr_3_0_I_45 ( + .I0(cfg_cfg_5072[76]), + .I1(com_cmm_bar0_reg_12_), + .I2(com_cmm_u_cmm_decoder_N_78_4), + .I3(com_cmmt_raddr[44]), + .O(com_cmm_u_cmm_decoder_N_75_4) + ); + defparam com_cmm_u_cmm_decoder_bar0_eq_raddr_3_0_I_36.INIT = 16'h0903; + LUT4 com_cmm_u_cmm_decoder_bar0_eq_raddr_3_0_I_36 ( + .I0(cfg_cfg_5072[74]), + .I1(com_cmm_bar0_reg_10_), + .I2(com_cmm_u_cmm_decoder_N_86_4), + .I3(com_cmmt_raddr[42]), + .O(com_cmm_u_cmm_decoder_N_83_4) + ); + defparam com_cmm_u_cmm_decoder_bar0_eq_raddr_3_0_I_27.INIT = 16'h0903; + LUT4 com_cmm_u_cmm_decoder_bar0_eq_raddr_3_0_I_27 ( + .I0(cfg_cfg_5072[86]), + .I1(com_cmm_bar0_reg_22_), + .I2(com_cmm_u_cmm_decoder_N_94_4), + .I3(com_cmmt_raddr[54]), + .O(com_cmm_u_cmm_decoder_N_91_4) + ); + defparam com_cmm_u_cmm_decoder_bar0_eq_raddr_3_0_I_9.INIT = 16'h0903; + LUT4 com_cmm_u_cmm_decoder_bar0_eq_raddr_3_0_I_9 ( + .I0(cfg_cfg_5072[68]), + .I1(com_cmm_bar0_reg_4_), + .I2(com_cmm_u_cmm_decoder_N_110_1), + .I3(com_cmmt_raddr[36]), + .O(com_cmm_u_cmm_decoder_N_107_4) + ); + defparam com_cmm_u_cmm_decoder_un9_bar45_64_hit_high_0_I_126.INIT = 16'h0903; + LUT4 com_cmm_u_cmm_decoder_un9_bar45_64_hit_high_0_I_126 ( + .I0(cfg_cfg_5072[200]), + .I1(com_cmm_bar4_reg[8]), + .I2(com_cmm_u_cmm_decoder_N_6_3), + .I3(com_cmmt_raddr[8]), + .O(com_cmm_u_cmm_decoder_N_3_3) + ); + defparam com_cmm_u_cmm_decoder_un9_bar45_64_hit_high_0_I_117.INIT = 16'h0903; + LUT4 com_cmm_u_cmm_decoder_un9_bar45_64_hit_high_0_I_117 ( + .I0(cfg_cfg_5072[220]), + .I1(com_cmm_bar4_reg[28]), + .I2(com_cmm_u_cmm_decoder_N_14_4), + .I3(com_cmmt_raddr[28]), + .O(com_cmm_u_cmm_decoder_N_11_4) + ); + defparam com_cmm_u_cmm_decoder_un9_bar45_64_hit_high_0_I_108.INIT = 16'h0903; + LUT4 com_cmm_u_cmm_decoder_un9_bar45_64_hit_high_0_I_108 ( + .I0(cfg_cfg_5072[218]), + .I1(com_cmm_bar4_reg[26]), + .I2(com_cmm_u_cmm_decoder_N_22_3), + .I3(com_cmmt_raddr[26]), + .O(com_cmm_u_cmm_decoder_N_19_3) + ); + defparam com_cmm_u_cmm_decoder_un9_bar45_64_hit_high_0_I_99.INIT = 16'h0903; + LUT4 com_cmm_u_cmm_decoder_un9_bar45_64_hit_high_0_I_99 ( + .I0(cfg_cfg_5072[198]), + .I1(com_cmm_bar4_reg[6]), + .I2(com_cmm_u_cmm_decoder_N_30_2), + .I3(com_cmmt_raddr[6]), + .O(com_cmm_u_cmm_decoder_N_27_3) + ); + defparam com_cmm_u_cmm_decoder_un9_bar45_64_hit_high_0_I_90.INIT = 16'h0903; + LUT4 com_cmm_u_cmm_decoder_un9_bar45_64_hit_high_0_I_90 ( + .I0(cfg_cfg_5072[208]), + .I1(com_cmm_bar4_reg[16]), + .I2(com_cmm_u_cmm_decoder_N_38_3), + .I3(com_cmmt_raddr[16]), + .O(com_cmm_u_cmm_decoder_N_35_3) + ); + defparam com_cmm_u_cmm_decoder_un9_bar45_64_hit_high_0_I_81.INIT = 16'h0903; + LUT4 com_cmm_u_cmm_decoder_un9_bar45_64_hit_high_0_I_81 ( + .I0(cfg_cfg_5072[212]), + .I1(com_cmm_bar4_reg[20]), + .I2(com_cmm_u_cmm_decoder_N_46_3), + .I3(com_cmmt_raddr[20]), + .O(com_cmm_u_cmm_decoder_N_43_3) + ); + defparam com_cmm_u_cmm_decoder_un9_bar45_64_hit_high_0_I_72.INIT = 16'h0903; + LUT4 com_cmm_u_cmm_decoder_un9_bar45_64_hit_high_0_I_72 ( + .I0(cfg_cfg_5072[210]), + .I1(com_cmm_bar4_reg[18]), + .I2(com_cmm_u_cmm_decoder_N_54_3), + .I3(com_cmmt_raddr[18]), + .O(com_cmm_u_cmm_decoder_N_51_3) + ); + defparam com_cmm_u_cmm_decoder_un9_bar45_64_hit_high_0_I_63.INIT = 16'h0903; + LUT4 com_cmm_u_cmm_decoder_un9_bar45_64_hit_high_0_I_63 ( + .I0(cfg_cfg_5072[206]), + .I1(com_cmm_bar4_reg[14]), + .I2(com_cmm_u_cmm_decoder_N_62_3), + .I3(com_cmmt_raddr[14]), + .O(com_cmm_u_cmm_decoder_N_59_3) + ); + defparam com_cmm_u_cmm_decoder_un9_bar45_64_hit_high_0_I_54.INIT = 16'h0903; + LUT4 com_cmm_u_cmm_decoder_un9_bar45_64_hit_high_0_I_54 ( + .I0(cfg_cfg_5072[216]), + .I1(com_cmm_bar4_reg[24]), + .I2(com_cmm_u_cmm_decoder_N_70_3), + .I3(com_cmmt_raddr[24]), + .O(com_cmm_u_cmm_decoder_N_67_3) + ); + defparam com_cmm_u_cmm_decoder_un9_bar45_64_hit_high_0_I_45.INIT = 16'h0903; + LUT4 com_cmm_u_cmm_decoder_un9_bar45_64_hit_high_0_I_45 ( + .I0(cfg_cfg_5072[204]), + .I1(com_cmm_bar4_reg[12]), + .I2(com_cmm_u_cmm_decoder_N_78_3), + .I3(com_cmmt_raddr[12]), + .O(com_cmm_u_cmm_decoder_N_75_3) + ); + defparam com_cmm_u_cmm_decoder_un9_bar45_64_hit_high_0_I_36.INIT = 16'h0903; + LUT4 com_cmm_u_cmm_decoder_un9_bar45_64_hit_high_0_I_36 ( + .I0(cfg_cfg_5072[202]), + .I1(com_cmm_bar4_reg[10]), + .I2(com_cmm_u_cmm_decoder_N_86_3), + .I3(com_cmmt_raddr[10]), + .O(com_cmm_u_cmm_decoder_N_83_3) + ); + defparam com_cmm_u_cmm_decoder_un9_bar45_64_hit_high_0_I_27.INIT = 16'h0903; + LUT4 com_cmm_u_cmm_decoder_un9_bar45_64_hit_high_0_I_27 ( + .I0(cfg_cfg_5072[214]), + .I1(com_cmm_bar4_reg[22]), + .I2(com_cmm_u_cmm_decoder_N_94_3), + .I3(com_cmmt_raddr[22]), + .O(com_cmm_u_cmm_decoder_N_91_3) + ); + defparam com_cmm_u_cmm_decoder_un9_bar45_64_hit_high_0_I_9.INIT = 16'h0903; + LUT4 com_cmm_u_cmm_decoder_un9_bar45_64_hit_high_0_I_9 ( + .I0(cfg_cfg_5072[196]), + .I1(com_cmm_bar4_reg[4]), + .I2(com_cmm_u_cmm_decoder_N_110_0), + .I3(com_cmmt_raddr[4]), + .O(com_cmm_u_cmm_decoder_N_107_3) + ); + defparam com_cmm_u_cmm_decoder_un10_bar01_64_hit_low_0_I_144.INIT = 16'h0903; + LUT4 com_cmm_u_cmm_decoder_un10_bar01_64_hit_low_0_I_144 ( + .I0(cfg_cfg_5072[108]), + .I1(com_cmm_bar1_reg[12]), + .I2(com_cmm_u_cmm_decoder_N_86_2), + .I3(com_cmmt_raddr[44]), + .O(com_cmm_u_cmm_decoder_N_3_2) + ); + defparam com_cmm_u_cmm_decoder_un10_bar01_64_hit_low_0_I_135.INIT = 16'h0903; + LUT4 com_cmm_u_cmm_decoder_un10_bar01_64_hit_low_0_I_135 ( + .I0(cfg_cfg_5072[97]), + .I1(com_cmm_bar1_reg[1]), + .I2(com_cmm_u_cmm_decoder_N_102_2), + .I3(com_cmmt_raddr[33]), + .O(com_cmm_u_cmm_decoder_N_11_3) + ); + defparam com_cmm_u_cmm_decoder_un10_bar01_64_hit_low_0_I_126.INIT = 16'h0903; + LUT4 com_cmm_u_cmm_decoder_un10_bar01_64_hit_low_0_I_126 ( + .I0(cfg_cfg_5072[126]), + .I1(com_cmm_bar1_reg[30]), + .I2(com_cmm_u_cmm_decoder_N_14_3), + .I3(com_cmmt_raddr[62]), + .O(com_cmm_u_cmm_decoder_N_19_2) + ); + defparam com_cmm_u_cmm_decoder_un10_bar01_64_hit_low_0_I_117.INIT = 16'h0903; + LUT4 com_cmm_u_cmm_decoder_un10_bar01_64_hit_low_0_I_117 ( + .I0(cfg_cfg_5072[106]), + .I1(com_cmm_bar1_reg[10]), + .I2(com_cmm_u_cmm_decoder_N_6_2), + .I3(com_cmmt_raddr[42]), + .O(com_cmm_u_cmm_decoder_N_27_2) + ); + defparam com_cmm_u_cmm_decoder_un10_bar01_64_hit_low_0_I_108.INIT = 4'h1; + LUT2 com_cmm_u_cmm_decoder_un10_bar01_64_hit_low_0_I_108 ( + .I0(com_cmm_u_cmm_decoder_N_47_1), + .I1(com_cmm_u_cmm_decoder_N_54_2), + .O(com_cmm_u_cmm_decoder_N_35_2) + ); + defparam com_cmm_u_cmm_decoder_un10_bar01_64_hit_low_0_I_99.INIT = 16'h0903; + LUT4 com_cmm_u_cmm_decoder_un10_bar01_64_hit_low_0_I_99 ( + .I0(cfg_cfg_5072[120]), + .I1(com_cmm_bar1_reg[24]), + .I2(com_cmm_u_cmm_decoder_N_94_2), + .I3(com_cmmt_raddr[56]), + .O(com_cmm_u_cmm_decoder_N_43_2) + ); + defparam com_cmm_u_cmm_decoder_un10_bar01_64_hit_low_0_I_90.INIT = 16'h0903; + LUT4 com_cmm_u_cmm_decoder_un10_bar01_64_hit_low_0_I_90 ( + .I0(cfg_cfg_5072[118]), + .I1(com_cmm_bar1_reg[22]), + .I2(com_cmm_u_cmm_decoder_N_46_2), + .I3(com_cmmt_raddr[54]), + .O(com_cmm_u_cmm_decoder_N_51_2) + ); + defparam com_cmm_u_cmm_decoder_un10_bar01_64_hit_low_0_I_81.INIT = 16'h0903; + LUT4 com_cmm_u_cmm_decoder_un10_bar01_64_hit_low_0_I_81 ( + .I0(cfg_cfg_5072[114]), + .I1(com_cmm_bar1_reg[18]), + .I2(com_cmm_u_cmm_decoder_N_38_2), + .I3(com_cmmt_raddr[50]), + .O(com_cmm_u_cmm_decoder_N_59_2) + ); + defparam com_cmm_u_cmm_decoder_un10_bar01_64_hit_low_0_I_72.INIT = 4'h1; + LUT2 com_cmm_u_cmm_decoder_un10_bar01_64_hit_low_0_I_72 ( + .I0(com_cmm_u_cmm_decoder_N_15_2), + .I1(com_cmm_u_cmm_decoder_N_22_2), + .O(com_cmm_u_cmm_decoder_N_67_2) + ); + defparam com_cmm_u_cmm_decoder_un10_bar01_64_hit_low_0_I_63.INIT = 4'h1; + LUT2 com_cmm_u_cmm_decoder_un10_bar01_64_hit_low_0_I_63 ( + .I0(com_cmm_u_cmm_decoder_N_39_1), + .I1(com_cmm_u_cmm_decoder_N_62_2), + .O(com_cmm_u_cmm_decoder_N_75_2) + ); + defparam com_cmm_u_cmm_decoder_un10_bar01_64_hit_low_0_I_54.INIT = 4'h1; + LUT2 com_cmm_u_cmm_decoder_un10_bar01_64_hit_low_0_I_54 ( + .I0(com_cmm_u_cmm_decoder_N_63_2), + .I1(com_cmm_u_cmm_decoder_N_78_2), + .O(com_cmm_u_cmm_decoder_N_83_2) + ); + defparam com_cmm_u_cmm_decoder_un10_bar01_64_hit_low_0_I_45.INIT = 16'h0903; + LUT4 com_cmm_u_cmm_decoder_un10_bar01_64_hit_low_0_I_45 ( + .I0(cfg_cfg_5072[122]), + .I1(com_cmm_bar1_reg[26]), + .I2(com_cmm_u_cmm_decoder_N_70_2), + .I3(com_cmmt_raddr[58]), + .O(com_cmm_u_cmm_decoder_N_91_2) + ); + defparam com_cmm_u_cmm_decoder_un10_bar01_64_hit_low_0_I_27.INIT = 16'h0903; + LUT4 com_cmm_u_cmm_decoder_un10_bar01_64_hit_low_0_I_27 ( + .I0(cfg_cfg_5072[104]), + .I1(com_cmm_bar1_reg[8]), + .I2(com_cmm_u_cmm_decoder_N_30_1), + .I3(com_cmmt_raddr[40]), + .O(com_cmm_u_cmm_decoder_N_107_2) + ); + defparam com_cmm_u_cmm_decoder_un10_bar01_64_hit_low_0_I_18.INIT = 16'h0903; + LUT4 com_cmm_u_cmm_decoder_un10_bar01_64_hit_low_0_I_18 ( + .I0(cfg_cfg_5072[101]), + .I1(com_cmm_bar1_reg[5]), + .I2(com_cmm_u_cmm_decoder_N_31_1), + .I3(com_cmmt_raddr[37]), + .O(com_cmm_u_cmm_decoder_N_115_2) + ); + defparam com_cmm_u_cmm_decoder_un10_bar01_64_hit_low_0_I_9.INIT = 16'h0903; + LUT4 com_cmm_u_cmm_decoder_un10_bar01_64_hit_low_0_I_9 ( + .I0(cfg_cfg_5072[99]), + .I1(com_cmm_bar1_reg[3]), + .I2(com_cmm_u_cmm_decoder_N_111_2), + .I3(com_cmmt_raddr[35]), + .O(com_cmm_u_cmm_decoder_N_123_2) + ); + defparam com_cmm_u_cmm_decoder_un10_bar12_64_hit_low_0_I_144.INIT = 4'h1; + LUT2 com_cmm_u_cmm_decoder_un10_bar12_64_hit_low_0_I_144 ( + .I0(com_cmm_u_cmm_decoder_N_79_0), + .I1(com_cmm_u_cmm_decoder_N_86_1), + .O(com_cmm_u_cmm_decoder_N_3_1) + ); + defparam com_cmm_u_cmm_decoder_un10_bar12_64_hit_low_0_I_135.INIT = 16'h0903; + LUT4 com_cmm_u_cmm_decoder_un10_bar12_64_hit_low_0_I_135 ( + .I0(cfg_cfg_5072[129]), + .I1(com_cmm_bar2_reg[1]), + .I2(com_cmm_u_cmm_decoder_N_102_1), + .I3(com_cmmt_raddr[33]), + .O(com_cmm_u_cmm_decoder_N_11_2) + ); + defparam com_cmm_u_cmm_decoder_un10_bar12_64_hit_low_0_I_126.INIT = 16'h0903; + LUT4 com_cmm_u_cmm_decoder_un10_bar12_64_hit_low_0_I_126 ( + .I0(cfg_cfg_5072[158]), + .I1(com_cmm_bar2_reg[30]), + .I2(com_cmm_u_cmm_decoder_N_14_2), + .I3(com_cmmt_raddr[62]), + .O(com_cmm_u_cmm_decoder_N_19_1) + ); + defparam com_cmm_u_cmm_decoder_un10_bar12_64_hit_low_0_I_117.INIT = 16'h0903; + LUT4 com_cmm_u_cmm_decoder_un10_bar12_64_hit_low_0_I_117 ( + .I0(cfg_cfg_5072[138]), + .I1(com_cmm_bar2_reg[10]), + .I2(com_cmm_u_cmm_decoder_N_6_1), + .I3(com_cmmt_raddr[42]), + .O(com_cmm_u_cmm_decoder_N_27_1) + ); + defparam com_cmm_u_cmm_decoder_un10_bar12_64_hit_low_0_I_108.INIT = 16'h0903; + LUT4 com_cmm_u_cmm_decoder_un10_bar12_64_hit_low_0_I_108 ( + .I0(cfg_cfg_5072[148]), + .I1(com_cmm_bar2_reg[20]), + .I2(com_cmm_u_cmm_decoder_N_54_1), + .I3(com_cmmt_raddr[52]), + .O(com_cmm_u_cmm_decoder_N_35_1) + ); + defparam com_cmm_u_cmm_decoder_un10_bar12_64_hit_low_0_I_99.INIT = 16'h0903; + LUT4 com_cmm_u_cmm_decoder_un10_bar12_64_hit_low_0_I_99 ( + .I0(cfg_cfg_5072[152]), + .I1(com_cmm_bar2_reg[24]), + .I2(com_cmm_u_cmm_decoder_N_94_1), + .I3(com_cmmt_raddr[56]), + .O(com_cmm_u_cmm_decoder_N_43_1) + ); + defparam com_cmm_u_cmm_decoder_un10_bar12_64_hit_low_0_I_90.INIT = 16'h0903; + LUT4 com_cmm_u_cmm_decoder_un10_bar12_64_hit_low_0_I_90 ( + .I0(cfg_cfg_5072[150]), + .I1(com_cmm_bar2_reg[22]), + .I2(com_cmm_u_cmm_decoder_N_46_1), + .I3(com_cmmt_raddr[54]), + .O(com_cmm_u_cmm_decoder_N_51_1) + ); + defparam com_cmm_u_cmm_decoder_un10_bar12_64_hit_low_0_I_81.INIT = 16'h0903; + LUT4 com_cmm_u_cmm_decoder_un10_bar12_64_hit_low_0_I_81 ( + .I0(cfg_cfg_5072[146]), + .I1(com_cmm_bar2_reg[18]), + .I2(com_cmm_u_cmm_decoder_N_38_1), + .I3(com_cmmt_raddr[50]), + .O(com_cmm_u_cmm_decoder_N_59_1) + ); + defparam com_cmm_u_cmm_decoder_un10_bar12_64_hit_low_0_I_72.INIT = 4'h1; + LUT2 com_cmm_u_cmm_decoder_un10_bar12_64_hit_low_0_I_72 ( + .I0(com_cmm_u_cmm_decoder_N_15_1), + .I1(com_cmm_u_cmm_decoder_N_22_1), + .O(com_cmm_u_cmm_decoder_N_67_1) + ); + defparam com_cmm_u_cmm_decoder_un10_bar12_64_hit_low_0_I_63.INIT = 4'h1; + LUT2 com_cmm_u_cmm_decoder_un10_bar12_64_hit_low_0_I_63 ( + .I0(com_cmm_u_cmm_decoder_N_39_0), + .I1(com_cmm_u_cmm_decoder_N_62_1), + .O(com_cmm_u_cmm_decoder_N_75_1) + ); + defparam com_cmm_u_cmm_decoder_un10_bar12_64_hit_low_0_I_54.INIT = 4'h1; + LUT2 com_cmm_u_cmm_decoder_un10_bar12_64_hit_low_0_I_54 ( + .I0(com_cmm_u_cmm_decoder_N_63_1), + .I1(com_cmm_u_cmm_decoder_N_78_1), + .O(com_cmm_u_cmm_decoder_N_83_1) + ); + defparam com_cmm_u_cmm_decoder_un10_bar12_64_hit_low_0_I_45.INIT = 16'h0903; + LUT4 com_cmm_u_cmm_decoder_un10_bar12_64_hit_low_0_I_45 ( + .I0(cfg_cfg_5072[154]), + .I1(com_cmm_bar2_reg[26]), + .I2(com_cmm_u_cmm_decoder_N_70_1), + .I3(com_cmmt_raddr[58]), + .O(com_cmm_u_cmm_decoder_N_91_1) + ); + defparam com_cmm_u_cmm_decoder_un10_bar12_64_hit_low_0_I_27.INIT = 16'h0903; + LUT4 com_cmm_u_cmm_decoder_un10_bar12_64_hit_low_0_I_27 ( + .I0(cfg_cfg_5072[135]), + .I1(com_cmm_bar2_reg[7]), + .I2(com_cmm_u_cmm_decoder_N_7_0), + .I3(com_cmmt_raddr[39]), + .O(com_cmm_u_cmm_decoder_N_107_1) + ); + defparam com_cmm_u_cmm_decoder_un10_bar12_64_hit_low_0_I_18.INIT = 16'h0903; + LUT4 com_cmm_u_cmm_decoder_un10_bar12_64_hit_low_0_I_18 ( + .I0(cfg_cfg_5072[133]), + .I1(com_cmm_bar2_reg[5]), + .I2(com_cmm_u_cmm_decoder_N_31_0), + .I3(com_cmmt_raddr[37]), + .O(com_cmm_u_cmm_decoder_N_115_1) + ); + defparam com_cmm_u_cmm_decoder_un10_bar12_64_hit_low_0_I_9.INIT = 16'h0903; + LUT4 com_cmm_u_cmm_decoder_un10_bar12_64_hit_low_0_I_9 ( + .I0(cfg_cfg_5072[131]), + .I1(com_cmm_bar2_reg[3]), + .I2(com_cmm_u_cmm_decoder_N_111_1), + .I3(com_cmmt_raddr[35]), + .O(com_cmm_u_cmm_decoder_N_123_1) + ); + defparam com_cmm_u_cmm_decoder_un10_bar23_64_hit_low_0_I_144.INIT = 4'h1; + LUT2 com_cmm_u_cmm_decoder_un10_bar23_64_hit_low_0_I_144 ( + .I0(com_cmm_u_cmm_decoder_N_79), + .I1(com_cmm_u_cmm_decoder_N_86_0), + .O(com_cmm_u_cmm_decoder_N_3_0) + ); + defparam com_cmm_u_cmm_decoder_un10_bar23_64_hit_low_0_I_135.INIT = 16'h0903; + LUT4 com_cmm_u_cmm_decoder_un10_bar23_64_hit_low_0_I_135 ( + .I0(cfg_cfg_5072[161]), + .I1(com_cmm_bar3_reg[1]), + .I2(com_cmm_u_cmm_decoder_N_102_0), + .I3(com_cmmt_raddr[33]), + .O(com_cmm_u_cmm_decoder_N_11_1) + ); + defparam com_cmm_u_cmm_decoder_un10_bar23_64_hit_low_0_I_126.INIT = 16'h0903; + LUT4 com_cmm_u_cmm_decoder_un10_bar23_64_hit_low_0_I_126 ( + .I0(cfg_cfg_5072[190]), + .I1(com_cmm_bar3_reg[30]), + .I2(com_cmm_u_cmm_decoder_N_14_1), + .I3(com_cmmt_raddr[62]), + .O(com_cmm_u_cmm_decoder_N_19_0) + ); + defparam com_cmm_u_cmm_decoder_un10_bar23_64_hit_low_0_I_117.INIT = 16'h0903; + LUT4 com_cmm_u_cmm_decoder_un10_bar23_64_hit_low_0_I_117 ( + .I0(cfg_cfg_5072[170]), + .I1(com_cmm_bar3_reg[10]), + .I2(com_cmm_u_cmm_decoder_N_6_0), + .I3(com_cmmt_raddr[42]), + .O(com_cmm_u_cmm_decoder_N_27_0) + ); + defparam com_cmm_u_cmm_decoder_un10_bar23_64_hit_low_0_I_108.INIT = 4'h1; + LUT2 com_cmm_u_cmm_decoder_un10_bar23_64_hit_low_0_I_108 ( + .I0(com_cmm_u_cmm_decoder_N_47_0), + .I1(com_cmm_u_cmm_decoder_N_54_0), + .O(com_cmm_u_cmm_decoder_N_35_0) + ); + defparam com_cmm_u_cmm_decoder_un10_bar23_64_hit_low_0_I_99.INIT = 16'h0903; + LUT4 com_cmm_u_cmm_decoder_un10_bar23_64_hit_low_0_I_99 ( + .I0(cfg_cfg_5072[184]), + .I1(com_cmm_bar3_reg[24]), + .I2(com_cmm_u_cmm_decoder_N_94_0), + .I3(com_cmmt_raddr[56]), + .O(com_cmm_u_cmm_decoder_N_43_0) + ); + defparam com_cmm_u_cmm_decoder_un10_bar23_64_hit_low_0_I_90.INIT = 16'h0903; + LUT4 com_cmm_u_cmm_decoder_un10_bar23_64_hit_low_0_I_90 ( + .I0(cfg_cfg_5072[182]), + .I1(com_cmm_bar3_reg[22]), + .I2(com_cmm_u_cmm_decoder_N_46_0), + .I3(com_cmmt_raddr[54]), + .O(com_cmm_u_cmm_decoder_N_51_0) + ); + defparam com_cmm_u_cmm_decoder_un10_bar23_64_hit_low_0_I_81.INIT = 16'h0903; + LUT4 com_cmm_u_cmm_decoder_un10_bar23_64_hit_low_0_I_81 ( + .I0(cfg_cfg_5072[178]), + .I1(com_cmm_bar3_reg[18]), + .I2(com_cmm_u_cmm_decoder_N_38_0), + .I3(com_cmmt_raddr[50]), + .O(com_cmm_u_cmm_decoder_N_59_0) + ); + defparam com_cmm_u_cmm_decoder_un10_bar23_64_hit_low_0_I_72.INIT = 4'h1; + LUT2 com_cmm_u_cmm_decoder_un10_bar23_64_hit_low_0_I_72 ( + .I0(com_cmm_u_cmm_decoder_N_15_0), + .I1(com_cmm_u_cmm_decoder_N_22_0), + .O(com_cmm_u_cmm_decoder_N_67_0) + ); + defparam com_cmm_u_cmm_decoder_un10_bar23_64_hit_low_0_I_63.INIT = 4'h1; + LUT2 com_cmm_u_cmm_decoder_un10_bar23_64_hit_low_0_I_63 ( + .I0(com_cmm_u_cmm_decoder_N_39), + .I1(com_cmm_u_cmm_decoder_N_62_0), + .O(com_cmm_u_cmm_decoder_N_75_0) + ); + defparam com_cmm_u_cmm_decoder_un10_bar23_64_hit_low_0_I_54.INIT = 4'h1; + LUT2 com_cmm_u_cmm_decoder_un10_bar23_64_hit_low_0_I_54 ( + .I0(com_cmm_u_cmm_decoder_N_63_0), + .I1(com_cmm_u_cmm_decoder_N_78_0), + .O(com_cmm_u_cmm_decoder_N_83_0) + ); + defparam com_cmm_u_cmm_decoder_un10_bar23_64_hit_low_0_I_45.INIT = 16'h0903; + LUT4 com_cmm_u_cmm_decoder_un10_bar23_64_hit_low_0_I_45 ( + .I0(cfg_cfg_5072[186]), + .I1(com_cmm_bar3_reg[26]), + .I2(com_cmm_u_cmm_decoder_N_70_0), + .I3(com_cmmt_raddr[58]), + .O(com_cmm_u_cmm_decoder_N_91_0) + ); + defparam com_cmm_u_cmm_decoder_un10_bar23_64_hit_low_0_I_27.INIT = 16'h0903; + LUT4 com_cmm_u_cmm_decoder_un10_bar23_64_hit_low_0_I_27 ( + .I0(cfg_cfg_5072[168]), + .I1(com_cmm_bar3_reg[8]), + .I2(com_cmm_u_cmm_decoder_N_30_0), + .I3(com_cmmt_raddr[40]), + .O(com_cmm_u_cmm_decoder_N_107_0) + ); + defparam com_cmm_u_cmm_decoder_un10_bar23_64_hit_low_0_I_18.INIT = 16'h0903; + LUT4 com_cmm_u_cmm_decoder_un10_bar23_64_hit_low_0_I_18 ( + .I0(cfg_cfg_5072[166]), + .I1(com_cmm_bar3_reg[6]), + .I2(com_cmm_u_cmm_decoder_N_110), + .I3(com_cmmt_raddr[38]), + .O(com_cmm_u_cmm_decoder_N_115_0) + ); + defparam com_cmm_u_cmm_decoder_un10_bar23_64_hit_low_0_I_9.INIT = 16'h0903; + LUT4 com_cmm_u_cmm_decoder_un10_bar23_64_hit_low_0_I_9 ( + .I0(cfg_cfg_5072[163]), + .I1(com_cmm_bar3_reg[3]), + .I2(com_cmm_u_cmm_decoder_N_111_0), + .I3(com_cmmt_raddr[35]), + .O(com_cmm_u_cmm_decoder_N_123_0) + ); + defparam com_cmm_u_cmm_decoder_un10_bar34_64_hit_low_0_I_144.INIT = 16'h0903; + LUT4 com_cmm_u_cmm_decoder_un10_bar34_64_hit_low_0_I_144 ( + .I0(cfg_cfg_5072[204]), + .I1(com_cmm_bar4_reg[12]), + .I2(com_cmm_u_cmm_decoder_N_86), + .I3(com_cmmt_raddr[44]), + .O(com_cmm_u_cmm_decoder_N_3) + ); + defparam com_cmm_u_cmm_decoder_un10_bar34_64_hit_low_0_I_135.INIT = 16'h0903; + LUT4 com_cmm_u_cmm_decoder_un10_bar34_64_hit_low_0_I_135 ( + .I0(cfg_cfg_5072[193]), + .I1(com_cmm_bar4_reg[1]), + .I2(com_cmm_u_cmm_decoder_N_102), + .I3(com_cmmt_raddr[33]), + .O(com_cmm_u_cmm_decoder_N_11_0) + ); + defparam com_cmm_u_cmm_decoder_un10_bar34_64_hit_low_0_I_126.INIT = 16'h0903; + LUT4 com_cmm_u_cmm_decoder_un10_bar34_64_hit_low_0_I_126 ( + .I0(cfg_cfg_5072[222]), + .I1(com_cmm_bar4_reg[30]), + .I2(com_cmm_u_cmm_decoder_N_14_0), + .I3(com_cmmt_raddr[62]), + .O(com_cmm_u_cmm_decoder_N_19) + ); + defparam com_cmm_u_cmm_decoder_un10_bar34_64_hit_low_0_I_117.INIT = 16'h0903; + LUT4 com_cmm_u_cmm_decoder_un10_bar34_64_hit_low_0_I_117 ( + .I0(cfg_cfg_5072[202]), + .I1(com_cmm_bar4_reg[10]), + .I2(com_cmm_u_cmm_decoder_N_6), + .I3(com_cmmt_raddr[42]), + .O(com_cmm_u_cmm_decoder_N_27) + ); + defparam com_cmm_u_cmm_decoder_un10_bar34_64_hit_low_0_I_108.INIT = 4'h1; + LUT2 com_cmm_u_cmm_decoder_un10_bar34_64_hit_low_0_I_108 ( + .I0(com_cmm_u_cmm_decoder_N_47), + .I1(com_cmm_u_cmm_decoder_N_54), + .O(com_cmm_u_cmm_decoder_N_35) + ); + defparam com_cmm_u_cmm_decoder_un10_bar34_64_hit_low_0_I_99.INIT = 4'h1; + LUT2 com_cmm_u_cmm_decoder_un10_bar34_64_hit_low_0_I_99 ( + .I0(com_cmm_u_cmm_decoder_N_71), + .I1(com_cmm_u_cmm_decoder_N_94), + .O(com_cmm_u_cmm_decoder_N_43) + ); + defparam com_cmm_u_cmm_decoder_un10_bar34_64_hit_low_0_I_90.INIT = 16'h0903; + LUT4 com_cmm_u_cmm_decoder_un10_bar34_64_hit_low_0_I_90 ( + .I0(cfg_cfg_5072[214]), + .I1(com_cmm_bar4_reg[22]), + .I2(com_cmm_u_cmm_decoder_N_46), + .I3(com_cmmt_raddr[54]), + .O(com_cmm_u_cmm_decoder_N_51) + ); + defparam com_cmm_u_cmm_decoder_un10_bar34_64_hit_low_0_I_81.INIT = 16'h0903; + LUT4 com_cmm_u_cmm_decoder_un10_bar34_64_hit_low_0_I_81 ( + .I0(cfg_cfg_5072[210]), + .I1(com_cmm_bar4_reg[18]), + .I2(com_cmm_u_cmm_decoder_N_38), + .I3(com_cmmt_raddr[50]), + .O(com_cmm_u_cmm_decoder_N_59) + ); + defparam com_cmm_u_cmm_decoder_un10_bar34_64_hit_low_0_I_72.INIT = 4'h1; + LUT2 com_cmm_u_cmm_decoder_un10_bar34_64_hit_low_0_I_72 ( + .I0(com_cmm_u_cmm_decoder_N_15), + .I1(com_cmm_u_cmm_decoder_N_22), + .O(com_cmm_u_cmm_decoder_N_67) + ); + defparam com_cmm_u_cmm_decoder_un10_bar34_64_hit_low_0_I_63.INIT = 16'h0903; + LUT4 com_cmm_u_cmm_decoder_un10_bar34_64_hit_low_0_I_63 ( + .I0(cfg_cfg_5072[208]), + .I1(com_cmm_bar4_reg[16]), + .I2(com_cmm_u_cmm_decoder_N_62), + .I3(com_cmmt_raddr[48]), + .O(com_cmm_u_cmm_decoder_N_75) + ); + defparam com_cmm_u_cmm_decoder_un10_bar34_64_hit_low_0_I_54.INIT = 4'h1; + LUT2 com_cmm_u_cmm_decoder_un10_bar34_64_hit_low_0_I_54 ( + .I0(com_cmm_u_cmm_decoder_N_63), + .I1(com_cmm_u_cmm_decoder_N_78), + .O(com_cmm_u_cmm_decoder_N_83) + ); + defparam com_cmm_u_cmm_decoder_un10_bar34_64_hit_low_0_I_45.INIT = 4'h1; + LUT2 com_cmm_u_cmm_decoder_un10_bar34_64_hit_low_0_I_45 ( + .I0(com_cmm_u_cmm_decoder_N_23), + .I1(com_cmm_u_cmm_decoder_N_70), + .O(com_cmm_u_cmm_decoder_N_91) + ); + defparam com_cmm_u_cmm_decoder_un10_bar34_64_hit_low_0_I_27.INIT = 4'h1; + LUT2 com_cmm_u_cmm_decoder_un10_bar34_64_hit_low_0_I_27 ( + .I0(com_cmm_u_cmm_decoder_N_7), + .I1(com_cmm_u_cmm_decoder_N_30), + .O(com_cmm_u_cmm_decoder_N_107) + ); + defparam com_cmm_u_cmm_decoder_un10_bar34_64_hit_low_0_I_18.INIT = 16'h0903; + LUT4 com_cmm_u_cmm_decoder_un10_bar34_64_hit_low_0_I_18 ( + .I0(cfg_cfg_5072[197]), + .I1(com_cmm_bar4_reg[5]), + .I2(com_cmm_u_cmm_decoder_N_31), + .I3(com_cmmt_raddr[37]), + .O(com_cmm_u_cmm_decoder_N_115) + ); + defparam com_cmm_u_cmm_decoder_un10_bar34_64_hit_low_0_I_9.INIT = 16'h0903; + LUT4 com_cmm_u_cmm_decoder_un10_bar34_64_hit_low_0_I_9 ( + .I0(cfg_cfg_5072[195]), + .I1(com_cmm_bar4_reg[3]), + .I2(com_cmm_u_cmm_decoder_N_111), + .I3(com_cmmt_raddr[35]), + .O(com_cmm_u_cmm_decoder_N_123) + ); + defparam com_cmm_u_cmm_decoder_un10_bar45_64_hit_low_0_I_135.INIT = 16'h0903; + LUT4 com_cmm_u_cmm_decoder_un10_bar45_64_hit_low_0_I_135 ( + .I0(cfg_cfg_5072[225]), + .I1(com_cmm_bar5_reg[1]), + .I2(com_cmm_u_cmm_decoder_N_14), + .I3(com_cmmt_raddr[33]), + .O(com_cmm_u_cmm_decoder_N_11) + ); + VCC com_cmm_u_cmm_cfgspace_VCC ( + .P(com_cmm_u_cmm_cfgspace_VCC_4787) + ); + FDR com_cmm_u_cmm_cfgspace_low_addr_01_q_0_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_cfgspace_low_addr_01[0]), + .Q(com_cmm_u_cmm_cfgspace_low_addr_01_q[0]), + .R(com_cmm_u_cmm_cfgspace_N_9426_i_4518) + ); + FDR com_cmm_u_cmm_cfgspace_low_addr_01_q_1_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_cfgspace_low_addr_01[1]), + .Q(com_cmm_u_cmm_cfgspace_low_addr_01_q[1]), + .R(com_cmm_u_cmm_cfgspace_N_9426_i_4518) + ); + FDR com_cmm_u_cmm_cfgspace_low_addr_01_q_2_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_cfgspace_low_addr_01[2]), + .Q(com_cmm_u_cmm_cfgspace_low_addr_01_q[2]), + .R(com_cmm_u_cmm_cfgspace_N_9426_i_4518) + ); + FDR com_cmm_u_cmm_cfgspace_low_addr_01_q_3_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_cfgspace_low_addr_01[3]), + .Q(com_cmm_u_cmm_cfgspace_low_addr_01_q[3]), + .R(com_cmm_u_cmm_cfgspace_N_9426_i_4518) + ); + FDR com_cmm_u_cmm_cfgspace_low_addr_01_q_4_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_cfgspace_low_addr_01[4]), + .Q(com_cmm_u_cmm_cfgspace_low_addr_01_q[4]), + .R(com_cmm_u_cmm_cfgspace_N_9426_i_4518) + ); + FDR com_cmm_u_cmm_cfgspace_low_addr_01_q_5_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_cfgspace_low_addr_01[5]), + .Q(com_cmm_u_cmm_cfgspace_low_addr_01_q[5]), + .R(com_cmm_u_cmm_cfgspace_N_9426_i_4518) + ); + FDR com_cmm_u_cmm_cfgspace_low_addr_01_q_6_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_cfgspace_low_addr_01[6]), + .Q(com_cmm_u_cmm_cfgspace_low_addr_01_q[6]), + .R(com_cmm_u_cmm_cfgspace_N_9426_i_4518) + ); + FDR com_cmm_u_cmm_cfgspace_low_addr_01_q_7_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_cfgspace_low_addr_01[7]), + .Q(com_cmm_u_cmm_cfgspace_low_addr_01_q[7]), + .R(com_cmm_u_cmm_cfgspace_N_9426_i_4518) + ); + FDR com_cmm_u_cmm_cfgspace_low_addr_01_q_8_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_cfgspace_low_addr_01[8]), + .Q(com_cmm_u_cmm_cfgspace_low_addr_01_q[8]), + .R(com_cmm_u_cmm_cfgspace_N_9426_i_4518) + ); + FDR com_cmm_u_cmm_cfgspace_low_addr_01_q_9_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_cfgspace_low_addr_01[9]), + .Q(com_cmm_u_cmm_cfgspace_low_addr_01_q[9]), + .R(com_cmm_u_cmm_cfgspace_N_9426_i_4518) + ); + FDR com_cmm_u_cmm_cfgspace_low_addr_01_q_10_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_cfgspace_low_addr_01[10]), + .Q(com_cmm_u_cmm_cfgspace_low_addr_01_q[10]), + .R(com_cmm_u_cmm_cfgspace_N_9426_i_4518) + ); + FDR com_cmm_u_cmm_cfgspace_low_addr_01_q_11_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_cfgspace_low_addr_01[11]), + .Q(com_cmm_u_cmm_cfgspace_low_addr_01_q[11]), + .R(com_cmm_u_cmm_cfgspace_N_9426_i_4518) + ); + FDR com_cmm_u_cmm_cfgspace_low_addr_01_q_12_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_cfgspace_low_addr_01[12]), + .Q(com_cmm_u_cmm_cfgspace_low_addr_01_q[12]), + .R(com_cmm_u_cmm_cfgspace_N_9426_i_4518) + ); + FDR com_cmm_u_cmm_cfgspace_low_addr_01_q_13_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_cfgspace_low_addr_01[13]), + .Q(com_cmm_u_cmm_cfgspace_low_addr_01_q[13]), + .R(com_cmm_u_cmm_cfgspace_N_9426_i_4518) + ); + FDR com_cmm_u_cmm_cfgspace_low_addr_01_q_14_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_cfgspace_low_addr_01[14]), + .Q(com_cmm_u_cmm_cfgspace_low_addr_01_q[14]), + .R(com_cmm_u_cmm_cfgspace_N_9426_i_4518) + ); + FDR com_cmm_u_cmm_cfgspace_low_addr_01_q_15_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_cfgspace_low_addr_01[15]), + .Q(com_cmm_u_cmm_cfgspace_low_addr_01_q[15]), + .R(com_cmm_u_cmm_cfgspace_N_9426_i_4518) + ); + FDR com_cmm_u_cmm_cfgspace_low_addr_01_q_16_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_cfgspace_low_addr_01[16]), + .Q(com_cmm_u_cmm_cfgspace_low_addr_01_q[16]), + .R(com_cmm_u_cmm_cfgspace_N_9426_i_4518) + ); + FDR com_cmm_u_cmm_cfgspace_low_addr_01_q_17_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_cfgspace_low_addr_01[17]), + .Q(com_cmm_u_cmm_cfgspace_low_addr_01_q[17]), + .R(com_cmm_u_cmm_cfgspace_N_9426_i_4518) + ); + FDR com_cmm_u_cmm_cfgspace_low_addr_01_q_18_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_cfgspace_low_addr_01[18]), + .Q(com_cmm_u_cmm_cfgspace_low_addr_01_q[18]), + .R(com_cmm_u_cmm_cfgspace_N_9426_i_4518) + ); + FDR com_cmm_u_cmm_cfgspace_low_addr_01_q_19_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_cfgspace_low_addr_01[19]), + .Q(com_cmm_u_cmm_cfgspace_low_addr_01_q[19]), + .R(com_cmm_u_cmm_cfgspace_N_9426_i_4518) + ); + FDR com_cmm_u_cmm_cfgspace_low_addr_01_q_20_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_cfgspace_low_addr_01[20]), + .Q(com_cmm_u_cmm_cfgspace_low_addr_01_q[20]), + .R(com_cmm_u_cmm_cfgspace_N_9426_i_4518) + ); + FDR com_cmm_u_cmm_cfgspace_low_addr_01_q_21_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_cfgspace_low_addr_01[21]), + .Q(com_cmm_u_cmm_cfgspace_low_addr_01_q[21]), + .R(com_cmm_u_cmm_cfgspace_N_9426_i_4518) + ); + FDR com_cmm_u_cmm_cfgspace_low_addr_01_q_22_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_cfgspace_low_addr_01[22]), + .Q(com_cmm_u_cmm_cfgspace_low_addr_01_q[22]), + .R(com_cmm_u_cmm_cfgspace_N_9426_i_4518) + ); + FDR com_cmm_u_cmm_cfgspace_low_addr_01_q_23_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_cfgspace_low_addr_01[23]), + .Q(com_cmm_u_cmm_cfgspace_low_addr_01_q[23]), + .R(com_cmm_u_cmm_cfgspace_N_9426_i_4518) + ); + FDR com_cmm_u_cmm_cfgspace_low_addr_01_q_24_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_cfgspace_low_addr_01[24]), + .Q(com_cmm_u_cmm_cfgspace_low_addr_01_q[24]), + .R(com_cmm_u_cmm_cfgspace_N_9426_i_4518) + ); + FDR com_cmm_u_cmm_cfgspace_low_addr_01_q_25_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_cfgspace_low_addr_01[25]), + .Q(com_cmm_u_cmm_cfgspace_low_addr_01_q[25]), + .R(com_cmm_u_cmm_cfgspace_N_9426_i_4518) + ); + FDR com_cmm_u_cmm_cfgspace_low_addr_01_q_26_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_cfgspace_low_addr_01[26]), + .Q(com_cmm_u_cmm_cfgspace_low_addr_01_q[26]), + .R(com_cmm_u_cmm_cfgspace_N_9426_i_4518) + ); + FDR com_cmm_u_cmm_cfgspace_low_addr_01_q_27_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_cfgspace_low_addr_01[27]), + .Q(com_cmm_u_cmm_cfgspace_low_addr_01_q[27]), + .R(com_cmm_u_cmm_cfgspace_N_9426_i_4518) + ); + FDR com_cmm_u_cmm_cfgspace_low_addr_01_q_28_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_cfgspace_low_addr_01[28]), + .Q(com_cmm_u_cmm_cfgspace_low_addr_01_q[28]), + .R(com_cmm_u_cmm_cfgspace_N_9426_i_4518) + ); + FDR com_cmm_u_cmm_cfgspace_low_addr_01_q_29_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_cfgspace_low_addr_01[29]), + .Q(com_cmm_u_cmm_cfgspace_low_addr_01_q[29]), + .R(com_cmm_u_cmm_cfgspace_N_9426_i_4518) + ); + FDR com_cmm_u_cmm_cfgspace_low_addr_01_q_30_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_cfgspace_low_addr_01[30]), + .Q(com_cmm_u_cmm_cfgspace_low_addr_01_q[30]), + .R(com_cmm_u_cmm_cfgspace_N_9426_i_4518) + ); + FDR com_cmm_u_cmm_cfgspace_low_addr_01_q_31_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_cfgspace_low_addr_01[31]), + .Q(com_cmm_u_cmm_cfgspace_low_addr_01_q[31]), + .R(com_cmm_u_cmm_cfgspace_N_9426_i_4518) + ); + FDR com_cmm_u_cmm_cfgspace_sel_encodex_en ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_cfgspace_N_68098_i_4735), + .Q(com_cmm_u_cmm_cfgspace_sel_encodex_en_4519), + .R(com_cmm_rst_267) + ); + FDR com_cmm_u_cmm_cfgspace_low_addr_03_q_0_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_cfgspace_low_addr_03_q_4[0]), + .Q(com_cmm_u_cmm_cfgspace_low_addr_03_q[0]), + .R(com_cmm_u_cmm_cfgspace_N_9426_i_4518) + ); + FDR com_cmm_u_cmm_cfgspace_low_addr_03_q_1_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_cfgspace_low_addr_03_q_4[1]), + .Q(com_cmm_u_cmm_cfgspace_low_addr_03_q[1]), + .R(com_cmm_u_cmm_cfgspace_N_9426_i_4518) + ); + FDR com_cmm_u_cmm_cfgspace_low_addr_03_q_2_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_cfgspace_low_addr_03_q_4[2]), + .Q(com_cmm_u_cmm_cfgspace_low_addr_03_q[2]), + .R(com_cmm_u_cmm_cfgspace_N_9426_i_4518) + ); + FDR com_cmm_u_cmm_cfgspace_low_addr_03_q_3_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_cfgspace_low_addr_03_q_4[3]), + .Q(com_cmm_u_cmm_cfgspace_low_addr_03_q[3]), + .R(com_cmm_u_cmm_cfgspace_N_9426_i_4518) + ); + FDR com_cmm_u_cmm_cfgspace_low_addr_03_q_4_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_cfgspace_low_addr_03_q_4[4]), + .Q(com_cmm_u_cmm_cfgspace_low_addr_03_q[4]), + .R(com_cmm_u_cmm_cfgspace_N_9426_i_4518) + ); + FDR com_cmm_u_cmm_cfgspace_low_addr_03_q_5_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_cfgspace_low_addr_03_q_4[5]), + .Q(com_cmm_u_cmm_cfgspace_low_addr_03_q[5]), + .R(com_cmm_u_cmm_cfgspace_N_9426_i_4518) + ); + FDR com_cmm_u_cmm_cfgspace_low_addr_03_q_6_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_cfgspace_low_addr_03_q_4[6]), + .Q(com_cmm_u_cmm_cfgspace_low_addr_03_q[6]), + .R(com_cmm_u_cmm_cfgspace_N_9426_i_4518) + ); + FDR com_cmm_u_cmm_cfgspace_low_addr_03_q_7_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_cfgspace_low_addr_03_q_4[7]), + .Q(com_cmm_u_cmm_cfgspace_low_addr_03_q[7]), + .R(com_cmm_u_cmm_cfgspace_N_9426_i_4518) + ); + FDR com_cmm_u_cmm_cfgspace_low_addr_03_q_8_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_cfgspace_low_addr_03_q_4[8]), + .Q(com_cmm_u_cmm_cfgspace_low_addr_03_q[8]), + .R(com_cmm_u_cmm_cfgspace_N_9426_i_4518) + ); + FDR com_cmm_u_cmm_cfgspace_low_addr_03_q_9_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_cfgspace_low_addr_03_q_4[9]), + .Q(com_cmm_u_cmm_cfgspace_low_addr_03_q[9]), + .R(com_cmm_u_cmm_cfgspace_N_9426_i_4518) + ); + FDR com_cmm_u_cmm_cfgspace_low_addr_03_q_10_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_cfgspace_low_addr_03_q_4[10]), + .Q(com_cmm_u_cmm_cfgspace_low_addr_03_q[10]), + .R(com_cmm_u_cmm_cfgspace_N_9426_i_4518) + ); + FDR com_cmm_u_cmm_cfgspace_low_addr_03_q_11_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_cfgspace_low_addr_03_q_4[11]), + .Q(com_cmm_u_cmm_cfgspace_low_addr_03_q[11]), + .R(com_cmm_u_cmm_cfgspace_N_9426_i_4518) + ); + FDR com_cmm_u_cmm_cfgspace_low_addr_03_q_12_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_cfgspace_low_addr_03_q_4[12]), + .Q(com_cmm_u_cmm_cfgspace_low_addr_03_q[12]), + .R(com_cmm_u_cmm_cfgspace_N_9426_i_4518) + ); + FDR com_cmm_u_cmm_cfgspace_low_addr_03_q_13_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_cfgspace_low_addr_03_q_4[13]), + .Q(com_cmm_u_cmm_cfgspace_low_addr_03_q[13]), + .R(com_cmm_u_cmm_cfgspace_N_9426_i_4518) + ); + FDR com_cmm_u_cmm_cfgspace_low_addr_03_q_14_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_cfgspace_low_addr_03_q_4[14]), + .Q(com_cmm_u_cmm_cfgspace_low_addr_03_q[14]), + .R(com_cmm_u_cmm_cfgspace_N_9426_i_4518) + ); + FDR com_cmm_u_cmm_cfgspace_low_addr_03_q_15_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_cfgspace_low_addr_03_q_4[15]), + .Q(com_cmm_u_cmm_cfgspace_low_addr_03_q[15]), + .R(com_cmm_u_cmm_cfgspace_N_9426_i_4518) + ); + FDR com_cmm_u_cmm_cfgspace_low_addr_03_q_16_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_cfgspace_low_addr_03_q_4[16]), + .Q(com_cmm_u_cmm_cfgspace_low_addr_03_q[16]), + .R(com_cmm_u_cmm_cfgspace_N_9426_i_4518) + ); + FDR com_cmm_u_cmm_cfgspace_low_addr_03_q_17_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_cfgspace_low_addr_03_q_4[17]), + .Q(com_cmm_u_cmm_cfgspace_low_addr_03_q[17]), + .R(com_cmm_u_cmm_cfgspace_N_9426_i_4518) + ); + FDR com_cmm_u_cmm_cfgspace_low_addr_03_q_18_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_cfgspace_low_addr_03_q_4[18]), + .Q(com_cmm_u_cmm_cfgspace_low_addr_03_q[18]), + .R(com_cmm_u_cmm_cfgspace_N_9426_i_4518) + ); + FDR com_cmm_u_cmm_cfgspace_low_addr_03_q_19_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_cfgspace_low_addr_03_q_4[19]), + .Q(com_cmm_u_cmm_cfgspace_low_addr_03_q[19]), + .R(com_cmm_u_cmm_cfgspace_N_9426_i_4518) + ); + FDR com_cmm_u_cmm_cfgspace_low_addr_03_q_20_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_cfgspace_low_addr_03_q_4[20]), + .Q(com_cmm_u_cmm_cfgspace_low_addr_03_q[20]), + .R(com_cmm_u_cmm_cfgspace_N_9426_i_4518) + ); + FDR com_cmm_u_cmm_cfgspace_low_addr_03_q_21_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_cfgspace_low_addr_03_q_4[21]), + .Q(com_cmm_u_cmm_cfgspace_low_addr_03_q[21]), + .R(com_cmm_u_cmm_cfgspace_N_9426_i_4518) + ); + FDR com_cmm_u_cmm_cfgspace_low_addr_03_q_22_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_cfgspace_low_addr_03_q_4[22]), + .Q(com_cmm_u_cmm_cfgspace_low_addr_03_q[22]), + .R(com_cmm_u_cmm_cfgspace_N_9426_i_4518) + ); + FDR com_cmm_u_cmm_cfgspace_low_addr_03_q_23_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_cfgspace_low_addr_03_q_4[23]), + .Q(com_cmm_u_cmm_cfgspace_low_addr_03_q[23]), + .R(com_cmm_u_cmm_cfgspace_N_9426_i_4518) + ); + FDR com_cmm_u_cmm_cfgspace_low_addr_03_q_24_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_cfgspace_low_addr_03_q_4[24]), + .Q(com_cmm_u_cmm_cfgspace_low_addr_03_q[24]), + .R(com_cmm_u_cmm_cfgspace_N_9426_i_4518) + ); + FDR com_cmm_u_cmm_cfgspace_low_addr_03_q_25_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_cfgspace_low_addr_03_q_4[25]), + .Q(com_cmm_u_cmm_cfgspace_low_addr_03_q[25]), + .R(com_cmm_u_cmm_cfgspace_N_9426_i_4518) + ); + FDR com_cmm_u_cmm_cfgspace_low_addr_03_q_26_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_cfgspace_low_addr_03_q_4[26]), + .Q(com_cmm_u_cmm_cfgspace_low_addr_03_q[26]), + .R(com_cmm_u_cmm_cfgspace_N_9426_i_4518) + ); + FDR com_cmm_u_cmm_cfgspace_low_addr_03_q_27_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_cfgspace_low_addr_03_q_4[27]), + .Q(com_cmm_u_cmm_cfgspace_low_addr_03_q[27]), + .R(com_cmm_u_cmm_cfgspace_N_9426_i_4518) + ); + FDR com_cmm_u_cmm_cfgspace_low_addr_03_q_28_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_cfgspace_low_addr_03_q_4[28]), + .Q(com_cmm_u_cmm_cfgspace_low_addr_03_q[28]), + .R(com_cmm_u_cmm_cfgspace_N_9426_i_4518) + ); + FDR com_cmm_u_cmm_cfgspace_low_addr_03_q_29_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_cfgspace_low_addr_03_q_4[29]), + .Q(com_cmm_u_cmm_cfgspace_low_addr_03_q[29]), + .R(com_cmm_u_cmm_cfgspace_N_9426_i_4518) + ); + FDR com_cmm_u_cmm_cfgspace_low_addr_03_q_30_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_cfgspace_low_addr_03_q_4[30]), + .Q(com_cmm_u_cmm_cfgspace_low_addr_03_q[30]), + .R(com_cmm_u_cmm_cfgspace_N_9426_i_4518) + ); + FDR com_cmm_u_cmm_cfgspace_low_addr_03_q_31_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_cfgspace_low_addr_03_q_4[31]), + .Q(com_cmm_u_cmm_cfgspace_low_addr_03_q[31]), + .R(com_cmm_u_cmm_cfgspace_N_9426_i_4518) + ); + FDR com_cmm_u_cmm_cfgspace_low_addr_02_q_0_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_cfgspace_low_addr_02[0]), + .Q(com_cmm_u_cmm_cfgspace_low_addr_02_q[0]), + .R(com_cmm_u_cmm_cfgspace_N_9426_i_4518) + ); + FDR com_cmm_u_cmm_cfgspace_low_addr_02_q_1_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_cfgspace_low_addr_02[1]), + .Q(com_cmm_u_cmm_cfgspace_low_addr_02_q[1]), + .R(com_cmm_u_cmm_cfgspace_N_9426_i_4518) + ); + FDR com_cmm_u_cmm_cfgspace_low_addr_02_q_2_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_cfgspace_low_addr_02[2]), + .Q(com_cmm_u_cmm_cfgspace_low_addr_02_q[2]), + .R(com_cmm_u_cmm_cfgspace_N_9426_i_4518) + ); + FDR com_cmm_u_cmm_cfgspace_low_addr_02_q_3_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_cfgspace_low_addr_02[3]), + .Q(com_cmm_u_cmm_cfgspace_low_addr_02_q[3]), + .R(com_cmm_u_cmm_cfgspace_N_9426_i_4518) + ); + FDR com_cmm_u_cmm_cfgspace_low_addr_02_q_4_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_cfgspace_low_addr_02[4]), + .Q(com_cmm_u_cmm_cfgspace_low_addr_02_q[4]), + .R(com_cmm_u_cmm_cfgspace_N_9426_i_4518) + ); + FDR com_cmm_u_cmm_cfgspace_low_addr_02_q_5_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_cfgspace_low_addr_02[5]), + .Q(com_cmm_u_cmm_cfgspace_low_addr_02_q[5]), + .R(com_cmm_u_cmm_cfgspace_N_9426_i_4518) + ); + FDR com_cmm_u_cmm_cfgspace_low_addr_02_q_6_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_cfgspace_low_addr_02[6]), + .Q(com_cmm_u_cmm_cfgspace_low_addr_02_q[6]), + .R(com_cmm_u_cmm_cfgspace_N_9426_i_4518) + ); + FDR com_cmm_u_cmm_cfgspace_low_addr_02_q_7_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_cfgspace_low_addr_02[7]), + .Q(com_cmm_u_cmm_cfgspace_low_addr_02_q[7]), + .R(com_cmm_u_cmm_cfgspace_N_9426_i_4518) + ); + FDR com_cmm_u_cmm_cfgspace_low_addr_02_q_8_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_cfgspace_low_addr_02[8]), + .Q(com_cmm_u_cmm_cfgspace_low_addr_02_q[8]), + .R(com_cmm_u_cmm_cfgspace_N_9426_i_4518) + ); + FDR com_cmm_u_cmm_cfgspace_low_addr_02_q_9_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_cfgspace_low_addr_02[9]), + .Q(com_cmm_u_cmm_cfgspace_low_addr_02_q[9]), + .R(com_cmm_u_cmm_cfgspace_N_9426_i_4518) + ); + FDR com_cmm_u_cmm_cfgspace_low_addr_02_q_10_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_cfgspace_low_addr_02[10]), + .Q(com_cmm_u_cmm_cfgspace_low_addr_02_q[10]), + .R(com_cmm_u_cmm_cfgspace_N_9426_i_4518) + ); + FDR com_cmm_u_cmm_cfgspace_low_addr_02_q_11_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_cfgspace_low_addr_02[11]), + .Q(com_cmm_u_cmm_cfgspace_low_addr_02_q[11]), + .R(com_cmm_u_cmm_cfgspace_N_9426_i_4518) + ); + FDR com_cmm_u_cmm_cfgspace_low_addr_02_q_12_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_cfgspace_low_addr_02[12]), + .Q(com_cmm_u_cmm_cfgspace_low_addr_02_q[12]), + .R(com_cmm_u_cmm_cfgspace_N_9426_i_4518) + ); + FDR com_cmm_u_cmm_cfgspace_low_addr_02_q_13_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_cfgspace_low_addr_02[13]), + .Q(com_cmm_u_cmm_cfgspace_low_addr_02_q[13]), + .R(com_cmm_u_cmm_cfgspace_N_9426_i_4518) + ); + FDR com_cmm_u_cmm_cfgspace_low_addr_02_q_14_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_cfgspace_low_addr_02[14]), + .Q(com_cmm_u_cmm_cfgspace_low_addr_02_q[14]), + .R(com_cmm_u_cmm_cfgspace_N_9426_i_4518) + ); + FDR com_cmm_u_cmm_cfgspace_low_addr_02_q_15_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_cfgspace_low_addr_02[15]), + .Q(com_cmm_u_cmm_cfgspace_low_addr_02_q[15]), + .R(com_cmm_u_cmm_cfgspace_N_9426_i_4518) + ); + FDR com_cmm_u_cmm_cfgspace_low_addr_02_q_16_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_cfgspace_low_addr_02[16]), + .Q(com_cmm_u_cmm_cfgspace_low_addr_02_q[16]), + .R(com_cmm_u_cmm_cfgspace_N_9426_i_4518) + ); + FDR com_cmm_u_cmm_cfgspace_low_addr_02_q_17_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_cfgspace_low_addr_02[17]), + .Q(com_cmm_u_cmm_cfgspace_low_addr_02_q[17]), + .R(com_cmm_u_cmm_cfgspace_N_9426_i_4518) + ); + FDR com_cmm_u_cmm_cfgspace_low_addr_02_q_18_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_cfgspace_low_addr_02[18]), + .Q(com_cmm_u_cmm_cfgspace_low_addr_02_q[18]), + .R(com_cmm_u_cmm_cfgspace_N_9426_i_4518) + ); + FDR com_cmm_u_cmm_cfgspace_low_addr_02_q_19_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_cfgspace_low_addr_02[19]), + .Q(com_cmm_u_cmm_cfgspace_low_addr_02_q[19]), + .R(com_cmm_u_cmm_cfgspace_N_9426_i_4518) + ); + FDR com_cmm_u_cmm_cfgspace_low_addr_02_q_20_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_cfgspace_low_addr_02[20]), + .Q(com_cmm_u_cmm_cfgspace_low_addr_02_q[20]), + .R(com_cmm_u_cmm_cfgspace_N_9426_i_4518) + ); + FDR com_cmm_u_cmm_cfgspace_low_addr_02_q_21_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_cfgspace_low_addr_02[21]), + .Q(com_cmm_u_cmm_cfgspace_low_addr_02_q[21]), + .R(com_cmm_u_cmm_cfgspace_N_9426_i_4518) + ); + FDR com_cmm_u_cmm_cfgspace_low_addr_02_q_22_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_cfgspace_low_addr_02[22]), + .Q(com_cmm_u_cmm_cfgspace_low_addr_02_q[22]), + .R(com_cmm_u_cmm_cfgspace_N_9426_i_4518) + ); + FDR com_cmm_u_cmm_cfgspace_low_addr_02_q_23_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_cfgspace_low_addr_02[23]), + .Q(com_cmm_u_cmm_cfgspace_low_addr_02_q[23]), + .R(com_cmm_u_cmm_cfgspace_N_9426_i_4518) + ); + FDR com_cmm_u_cmm_cfgspace_low_addr_02_q_24_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_cfgspace_low_addr_02[24]), + .Q(com_cmm_u_cmm_cfgspace_low_addr_02_q[24]), + .R(com_cmm_u_cmm_cfgspace_N_9426_i_4518) + ); + FDR com_cmm_u_cmm_cfgspace_low_addr_02_q_25_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_cfgspace_low_addr_02[25]), + .Q(com_cmm_u_cmm_cfgspace_low_addr_02_q[25]), + .R(com_cmm_u_cmm_cfgspace_N_9426_i_4518) + ); + FDR com_cmm_u_cmm_cfgspace_low_addr_02_q_26_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_cfgspace_low_addr_02[26]), + .Q(com_cmm_u_cmm_cfgspace_low_addr_02_q[26]), + .R(com_cmm_u_cmm_cfgspace_N_9426_i_4518) + ); + FDR com_cmm_u_cmm_cfgspace_low_addr_02_q_27_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_cfgspace_low_addr_02[27]), + .Q(com_cmm_u_cmm_cfgspace_low_addr_02_q[27]), + .R(com_cmm_u_cmm_cfgspace_N_9426_i_4518) + ); + FDR com_cmm_u_cmm_cfgspace_low_addr_02_q_28_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_cfgspace_low_addr_02[28]), + .Q(com_cmm_u_cmm_cfgspace_low_addr_02_q[28]), + .R(com_cmm_u_cmm_cfgspace_N_9426_i_4518) + ); + FDR com_cmm_u_cmm_cfgspace_low_addr_02_q_29_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_cfgspace_low_addr_02[29]), + .Q(com_cmm_u_cmm_cfgspace_low_addr_02_q[29]), + .R(com_cmm_u_cmm_cfgspace_N_9426_i_4518) + ); + FDR com_cmm_u_cmm_cfgspace_low_addr_02_q_30_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_cfgspace_low_addr_02[30]), + .Q(com_cmm_u_cmm_cfgspace_low_addr_02_q[30]), + .R(com_cmm_u_cmm_cfgspace_N_9426_i_4518) + ); + FDR com_cmm_u_cmm_cfgspace_low_addr_02_q_31_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_cfgspace_low_addr_02[31]), + .Q(com_cmm_u_cmm_cfgspace_low_addr_02_q[31]), + .R(com_cmm_u_cmm_cfgspace_N_9426_i_4518) + ); + FDR com_cmm_u_cmm_cfgspace_low_addr_00_q_0_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_cfgspace_N_15295_i), + .Q(com_cmm_u_cmm_cfgspace_low_addr_00_q[0]), + .R(com_cmm_u_cmm_cfgspace_N_9426_i_4518) + ); + FDR com_cmm_u_cmm_cfgspace_low_addr_00_q_1_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_cfgspace_N_43731_i), + .Q(com_cmm_u_cmm_cfgspace_low_addr_00_q[1]), + .R(com_cmm_u_cmm_cfgspace_N_9426_i_4518) + ); + FDR com_cmm_u_cmm_cfgspace_low_addr_00_q_2_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_cfgspace_N_68202_i_4731), + .Q(com_cmm_u_cmm_cfgspace_low_addr_00_q[2]), + .R(com_cmm_u_cmm_cfgspace_N_9426_i_4518) + ); + FDR com_cmm_u_cmm_cfgspace_low_addr_00_q_3_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_cfgspace_N_68203_i_4728), + .Q(com_cmm_u_cmm_cfgspace_low_addr_00_q[3]), + .R(com_cmm_u_cmm_cfgspace_N_9426_i_4518) + ); + FDR com_cmm_u_cmm_cfgspace_low_addr_00_q_4_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_cfgspace_N_68204_i_4725), + .Q(com_cmm_u_cmm_cfgspace_low_addr_00_q[4]), + .R(com_cmm_u_cmm_cfgspace_N_9426_i_4518) + ); + FDR com_cmm_u_cmm_cfgspace_low_addr_00_q_5_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_cfgspace_N_68205_i_4722), + .Q(com_cmm_u_cmm_cfgspace_low_addr_00_q[5]), + .R(com_cmm_u_cmm_cfgspace_N_9426_i_4518) + ); + FDR com_cmm_u_cmm_cfgspace_low_addr_00_q_6_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_cfgspace_N_68206_i_4719), + .Q(com_cmm_u_cmm_cfgspace_low_addr_00_q[6]), + .R(com_cmm_u_cmm_cfgspace_N_9426_i_4518) + ); + FDR com_cmm_u_cmm_cfgspace_low_addr_00_q_7_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_cfgspace_N_68207_i_4716), + .Q(com_cmm_u_cmm_cfgspace_low_addr_00_q[7]), + .R(com_cmm_u_cmm_cfgspace_N_9426_i_4518) + ); + FDR com_cmm_u_cmm_cfgspace_low_addr_00_q_8_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_cfgspace_N_68208_i_4713), + .Q(com_cmm_u_cmm_cfgspace_low_addr_00_q[8]), + .R(com_cmm_u_cmm_cfgspace_N_9426_i_4518) + ); + FDR com_cmm_u_cmm_cfgspace_low_addr_00_q_9_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_cfgspace_N_68209_i_4710), + .Q(com_cmm_u_cmm_cfgspace_low_addr_00_q[9]), + .R(com_cmm_u_cmm_cfgspace_N_9426_i_4518) + ); + FDR com_cmm_u_cmm_cfgspace_low_addr_00_q_10_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_cfgspace_N_68210_i_4707), + .Q(com_cmm_u_cmm_cfgspace_low_addr_00_q[10]), + .R(com_cmm_u_cmm_cfgspace_N_9426_i_4518) + ); + FDR com_cmm_u_cmm_cfgspace_low_addr_00_q_11_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_cfgspace_N_68191_i_4706), + .Q(com_cmm_u_cmm_cfgspace_low_addr_00_q[11]), + .R(com_cmm_u_cmm_cfgspace_N_9426_i_4518) + ); + FDR com_cmm_u_cmm_cfgspace_low_addr_00_q_12_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_cfgspace_N_68182_i_4705), + .Q(com_cmm_u_cmm_cfgspace_low_addr_00_q[12]), + .R(com_cmm_u_cmm_cfgspace_N_9426_i_4518) + ); + FDR com_cmm_u_cmm_cfgspace_low_addr_00_q_13_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_cfgspace_N_68183_i_4704), + .Q(com_cmm_u_cmm_cfgspace_low_addr_00_q[13]), + .R(com_cmm_u_cmm_cfgspace_N_9426_i_4518) + ); + FDR com_cmm_u_cmm_cfgspace_low_addr_00_q_14_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_cfgspace_N_68184_i_4703), + .Q(com_cmm_u_cmm_cfgspace_low_addr_00_q[14]), + .R(com_cmm_u_cmm_cfgspace_N_9426_i_4518) + ); + FDR com_cmm_u_cmm_cfgspace_low_addr_00_q_15_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_cfgspace_N_43745_i), + .Q(com_cmm_u_cmm_cfgspace_low_addr_00_q[15]), + .R(com_cmm_u_cmm_cfgspace_N_9426_i_4518) + ); + FDR com_cmm_u_cmm_cfgspace_low_addr_00_q_16_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_cfgspace_N_43747_i), + .Q(com_cmm_u_cmm_cfgspace_low_addr_00_q[16]), + .R(com_cmm_u_cmm_cfgspace_N_9426_i_4518) + ); + FDR com_cmm_u_cmm_cfgspace_low_addr_00_q_17_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_cfgspace_N_68225_i_4696), + .Q(com_cmm_u_cmm_cfgspace_low_addr_00_q[17]), + .R(com_cmm_u_cmm_cfgspace_N_9426_i_4518) + ); + FDR com_cmm_u_cmm_cfgspace_low_addr_00_q_18_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_cfgspace_N_68212_i_4692), + .Q(com_cmm_u_cmm_cfgspace_low_addr_00_q[18]), + .R(com_cmm_u_cmm_cfgspace_N_9426_i_4518) + ); + FDR com_cmm_u_cmm_cfgspace_low_addr_00_q_19_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_cfgspace_N_68227_i_4688), + .Q(com_cmm_u_cmm_cfgspace_low_addr_00_q[19]), + .R(com_cmm_u_cmm_cfgspace_N_9426_i_4518) + ); + FDR com_cmm_u_cmm_cfgspace_low_addr_00_q_20_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_cfgspace_N_43750_i), + .Q(com_cmm_u_cmm_cfgspace_low_addr_00_q[20]), + .R(com_cmm_u_cmm_cfgspace_N_9426_i_4518) + ); + FDR com_cmm_u_cmm_cfgspace_low_addr_00_q_21_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_cfgspace_N_68214_i_4683), + .Q(com_cmm_u_cmm_cfgspace_low_addr_00_q[21]), + .R(com_cmm_u_cmm_cfgspace_N_9426_i_4518) + ); + FDR com_cmm_u_cmm_cfgspace_low_addr_00_q_22_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_cfgspace_N_43753_i), + .Q(com_cmm_u_cmm_cfgspace_low_addr_00_q[22]), + .R(com_cmm_u_cmm_cfgspace_N_9426_i_4518) + ); + FDR com_cmm_u_cmm_cfgspace_low_addr_00_q_23_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_cfgspace_N_43755_i), + .Q(com_cmm_u_cmm_cfgspace_low_addr_00_q[23]), + .R(com_cmm_u_cmm_cfgspace_N_9426_i_4518) + ); + FDR com_cmm_u_cmm_cfgspace_low_addr_00_q_24_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_cfgspace_N_43757_i), + .Q(com_cmm_u_cmm_cfgspace_low_addr_00_q[24]), + .R(com_cmm_u_cmm_cfgspace_N_9426_i_4518) + ); + FDR com_cmm_u_cmm_cfgspace_low_addr_00_q_25_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_cfgspace_N_43759_i), + .Q(com_cmm_u_cmm_cfgspace_low_addr_00_q[25]), + .R(com_cmm_u_cmm_cfgspace_N_9426_i_4518) + ); + FDR com_cmm_u_cmm_cfgspace_low_addr_00_q_26_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_cfgspace_N_43761_i), + .Q(com_cmm_u_cmm_cfgspace_low_addr_00_q[26]), + .R(com_cmm_u_cmm_cfgspace_N_9426_i_4518) + ); + FDR com_cmm_u_cmm_cfgspace_low_addr_00_q_27_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_cfgspace_N_43763_i), + .Q(com_cmm_u_cmm_cfgspace_low_addr_00_q[27]), + .R(com_cmm_u_cmm_cfgspace_N_9426_i_4518) + ); + FDR com_cmm_u_cmm_cfgspace_low_addr_00_q_28_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_cfgspace_N_43765_i), + .Q(com_cmm_u_cmm_cfgspace_low_addr_00_q[28]), + .R(com_cmm_u_cmm_cfgspace_N_9426_i_4518) + ); + FDR com_cmm_u_cmm_cfgspace_low_addr_00_q_29_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_cfgspace_N_68226_i_4673), + .Q(com_cmm_u_cmm_cfgspace_low_addr_00_q[29]), + .R(com_cmm_u_cmm_cfgspace_N_9426_i_4518) + ); + FDR com_cmm_u_cmm_cfgspace_low_addr_00_q_30_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_cfgspace_N_43767_i), + .Q(com_cmm_u_cmm_cfgspace_low_addr_00_q[30]), + .R(com_cmm_u_cmm_cfgspace_N_9426_i_4518) + ); + FDR com_cmm_u_cmm_cfgspace_low_addr_00_q_31_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_cfgspace_N_21770_i), + .Q(com_cmm_u_cmm_cfgspace_low_addr_00_q[31]), + .R(com_cmm_u_cmm_cfgspace_N_9426_i_4518) + ); + FDR com_cmm_u_cmm_cfgspace_sel_xencode_0_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_cfgspace_N_68388_i_4670), + .Q(com_cmm_u_cmm_cfgspace_sel_xencode[0]), + .R(com_cmm_rst_267) + ); + FDR com_cmm_u_cmm_cfgspace_sel_xencode_1_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_cfgspace_N_68389_i_4669), + .Q(com_cmm_u_cmm_cfgspace_sel_xencode[1]), + .R(com_cmm_rst_267) + ); + FDRS com_cmm_u_cmm_cfgspace_sel_encodex_0_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_cfgspace_N_68390_i_4741), + .Q(com_cmm_u_cmm_cfgspace_sel_encodex[0]), + .R(com_cmm_rst_267), + .S(com_cmm_u_cmm_cfgspace_N_68712_i_4740) + ); + FDRS com_cmm_u_cmm_cfgspace_sel_encodex_1_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_cfgspace_N_68391_i_4738), + .Q(com_cmm_u_cmm_cfgspace_sel_encodex[1]), + .R(com_cmm_rst_267), + .S(com_cmm_u_cmm_cfgspace_N_68712_i_4740) + ); + FDRS com_cmm_u_cmm_cfgspace_sel_encodex_2_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_cfgspace_N_68392_i_4739), + .Q(com_cmm_u_cmm_cfgspace_sel_encodex[2]), + .R(com_cmm_rst_267), + .S(com_cmm_u_cmm_cfgspace_N_68712_i_4740) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_02_2_0_a2_0_a2_0_a2_1_15_.INIT = 4'h2; + LUT2 com_cmm_u_cmm_cfgspace_low_addr_02_2_0_a2_0_a2_0_a2_1_15_ ( + .I0(cfg_cfg_5072[482]), + .I1(com_cmm_u_cmm_cfgspace_sel_encodex[1]), + .O(com_cmm_u_cmm_cfgspace_N_49913_1) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_00_i_0_a2_3_1_1_.INIT = 4'h2; + LUT2 com_cmm_u_cmm_cfgspace_low_addr_00_i_0_a2_3_1_1_ ( + .I0(com_cmm_u_cmm_cfgspace_sel_encodex[1]), + .I1(com_cmm_u_cmm_cfgspace_sel_encodex[2]), + .O(com_cmm_u_cmm_cfgspace_N_50137_1) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_00_i_0_i_0_a2_0_1_11_.INIT = 4'h4; + LUT2 com_cmm_u_cmm_cfgspace_low_addr_00_i_0_i_0_a2_0_1_11_ ( + .I0(com_cmm_u_cmm_cfgspace_sel_encodex[1]), + .I1(com_cmm_u_cmm_cfgspace_sel_encodex[2]), + .O(com_cmm_u_cmm_cfgspace_N_50187_1) + ); + defparam com_cmm_u_cmm_cfgspace_x3gio_pmcsr_pme_pmcsr_21_0_a2_0_a2_0_a2_0_a2_1_14_.INIT = 4'h1; + LUT2 com_cmm_u_cmm_cfgspace_x3gio_pmcsr_pme_pmcsr_21_0_a2_0_a2_0_a2_0_a2_1_14_ ( + .I0(com_cmm_u_cmm_cfgspace_pme_pmcsr[12]), + .I1(com_cmm_rst_267), + .O(com_cmm_u_cmm_cfgspace_pme_pmcsr_21_1[14]) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_00_i_0_o3_1_.INIT = 4'h2; + LUT2 com_cmm_u_cmm_cfgspace_low_addr_00_i_0_o3_1_ ( + .I0(cfg_cfg_5072[1]), + .I1(com_cmm_u_cmm_cfgspace_sel_encodex[2]), + .O(com_cmm_u_cmm_cfgspace_low_addr_00_i_0_o3[1]) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_01_2_0_a2_0_a2_0_a2_0_a3_24_.INIT = 4'h1; + LUT2 com_cmm_u_cmm_cfgspace_low_addr_01_2_0_a2_0_a2_0_a2_0_a3_24_ ( + .I0(com_cmm_u_cmm_cfgspace_pme_pmcsr[12]), + .I1(com_cmm_u_cmm_cfgspace_sel_encodex[1]), + .O(com_cmm_u_cmm_cfgspace_N_50497) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_00_0_0_0_a3_0_12_.INIT = 4'h1; + LUT2 com_cmm_u_cmm_cfgspace_low_addr_00_0_0_0_a3_0_12_ ( + .I0(com_cmm_u_cmm_cfgspace_sel_encodex[0]), + .I1(com_cmm_u_cmm_cfgspace_sel_encodex[1]), + .O(com_cmm_u_cmm_cfgspace_N_50495) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_00_0_0_i_a3_0_0_a3_15_.INIT = 4'h4; + LUT2 com_cmm_u_cmm_cfgspace_low_addr_00_0_0_i_a3_0_0_a3_15_ ( + .I0(com_cmm_u_cmm_cfgspace_sel_encodex[0]), + .I1(com_cmm_u_cmm_cfgspace_sel_encodex[1]), + .O(com_cmm_u_cmm_cfgspace_N_50490) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_00_0_0_0_a3_12_.INIT = 4'h2; + LUT2 com_cmm_u_cmm_cfgspace_low_addr_00_0_0_0_a3_12_ ( + .I0(com_cmm_u_cmm_cfgspace_sel_encodex[0]), + .I1(com_cmm_u_cmm_cfgspace_sel_encodex[2]), + .O(com_cmm_u_cmm_cfgspace_N_50489) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_00_0_0_i_a3_2_a2_15_.INIT = 4'h4; + LUT2 com_cmm_u_cmm_cfgspace_low_addr_00_0_0_i_a3_2_a2_15_ ( + .I0(com_cmm_u_cmm_cfgspace_sel_encodex[0]), + .I1(com_cmm_u_cmm_cfgspace_sel_encodex[2]), + .O(com_cmm_u_cmm_cfgspace_N_50453) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_00_0_0_i_a3_1_0_a2_15_.INIT = 4'h8; + LUT2 com_cmm_u_cmm_cfgspace_low_addr_00_0_0_i_a3_1_0_a2_15_ ( + .I0(com_cmm_u_cmm_cfgspace_sel_encodex[0]), + .I1(com_cmm_u_cmm_cfgspace_sel_encodex[1]), + .O(com_cmm_u_cmm_cfgspace_N_50452) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_00_i_a3_0_a2_20_.INIT = 4'h8; + LUT2 com_cmm_u_cmm_cfgspace_low_addr_00_i_a3_0_a2_20_ ( + .I0(com_cmm_u_cmm_cfgspace_sel_encodex[0]), + .I1(com_cmm_u_cmm_cfgspace_sel_encodex[2]), + .O(com_cmm_u_cmm_cfgspace_N_50450) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_00_i_0_a2_0_27_.INIT = 4'h8; + LUT2 com_cmm_u_cmm_cfgspace_low_addr_00_i_0_a2_0_27_ ( + .I0(com_cmm_u_cmm_cfgspace_sel_encodex[1]), + .I1(com_cmm_u_cmm_cfgspace_sel_encodex[2]), + .O(com_cmm_u_cmm_cfgspace_N_50144) + ); + defparam com_cmm_u_cmm_cfgspace_decoder_sel_addr_0_o3_0_0_.INIT = 4'h1; + LUT2 com_cmm_u_cmm_cfgspace_decoder_sel_addr_0_o3_0_0_ ( + .I0(com_cmm_u_cmm_cfgspace_state_1__4780), + .I1(com_cmm_u_cmm_cfgspace_state_2__4779), + .O(com_cmm_u_cmm_cfgspace_N_28511_i) + ); + defparam com_cmm_u_cmm_cfgspace_sel_encodex_en_3_i_0_a2_2_1_0.INIT = 4'h1; + LUT2 com_cmm_u_cmm_cfgspace_sel_encodex_en_3_i_0_a2_2_1_0 ( + .I0(cfg_dwaddr_5069[5]), + .I1(cfg_dwaddr_5069[7]), + .O(com_cmm_u_cmm_cfgspace_sel_encodex_en_3_i_0_a2_2_1_0_4526) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_01_1_0_1_.INIT = 8'hCA; + LUT3_L com_cmm_u_cmm_cfgspace_low_addr_01_1_0_1_ ( + .I0(NlwRenamedSig_OI_cfg_command_1_), + .I1(com_cmm_bar5_reg[1]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex[1]), + .LO(com_cmm_u_cmm_cfgspace_N_3935) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_01_1_0_8_.INIT = 8'hCA; + LUT3_L com_cmm_u_cmm_cfgspace_low_addr_01_1_0_8_ ( + .I0(NlwRenamedSig_OI_cfg_command_8_), + .I1(com_cmm_bar5_reg[8]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex[1]), + .LO(com_cmm_u_cmm_cfgspace_N_3942) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_01_1_0_19_.INIT = 8'hCA; + LUT3_L com_cmm_u_cmm_cfgspace_low_addr_01_1_0_19_ ( + .I0(NlwRenamedSig_OI_cfg_status_3_), + .I1(com_cmm_bar5_reg[19]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex[1]), + .LO(com_cmm_u_cmm_cfgspace_N_3953) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_01_1_0_24_.INIT = 8'hCA; + LUT3 com_cmm_u_cmm_cfgspace_low_addr_01_1_0_24_ ( + .I0(NlwRenamedSig_OI_cfg_status_8_), + .I1(com_cmm_bar5_reg[24]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex[1]), + .O(com_cmm_u_cmm_cfgspace_N_3958) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_01_1_0_27_.INIT = 8'hCA; + LUT3 com_cmm_u_cmm_cfgspace_low_addr_01_1_0_27_ ( + .I0(NlwRenamedSig_OI_cfg_status_11_), + .I1(com_cmm_bar5_reg[27]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex[1]), + .O(com_cmm_u_cmm_cfgspace_N_3961) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_01_1_0_28_.INIT = 8'hCA; + LUT3 com_cmm_u_cmm_cfgspace_low_addr_01_1_0_28_ ( + .I0(NlwRenamedSig_OI_cfg_status_12_), + .I1(com_cmm_bar5_reg[28]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex[1]), + .O(com_cmm_u_cmm_cfgspace_N_3962) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_01_1_0_29_.INIT = 8'hCA; + LUT3 com_cmm_u_cmm_cfgspace_low_addr_01_1_0_29_ ( + .I0(NlwRenamedSig_OI_cfg_status_13_), + .I1(com_cmm_bar5_reg[29]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex[1]), + .O(com_cmm_u_cmm_cfgspace_N_3963) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_01_1_0_30_.INIT = 8'hCA; + LUT3 com_cmm_u_cmm_cfgspace_low_addr_01_1_0_30_ ( + .I0(NlwRenamedSig_OI_cfg_status_14_), + .I1(com_cmm_bar5_reg[30]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex[1]), + .O(com_cmm_u_cmm_cfgspace_N_3964) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_01_1_0_31_.INIT = 8'hCA; + LUT3 com_cmm_u_cmm_cfgspace_low_addr_01_1_0_31_ ( + .I0(NlwRenamedSig_OI_cfg_status_15_), + .I1(com_cmm_bar5_reg[31]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex[1]), + .O(com_cmm_u_cmm_cfgspace_N_3965) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_01_2_0_11_.INIT = 8'hAC; + LUT3_L com_cmm_u_cmm_cfgspace_low_addr_01_2_0_11_ ( + .I0(cfg_cfg_5072[411]), + .I1(com_cmm_u_cmm_cfgspace_pme_pmcsr[11]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex[1]), + .LO(com_cmm_u_cmm_cfgspace_N_3977) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_01_2_0_12_.INIT = 8'hE2; + LUT3_L com_cmm_u_cmm_cfgspace_low_addr_01_2_0_12_ ( + .I0(com_cmm_u_cmm_cfgspace_pme_pmcsr[12]), + .I1(com_cmm_u_cmm_cfgspace_sel_encodex[1]), + .I2(com_cmm_u_cmm_cfgspace_x_lcap[0]), + .LO(com_cmm_u_cmm_cfgspace_N_3978) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_01_2_0_13_.INIT = 8'hE2; + LUT3_L com_cmm_u_cmm_cfgspace_low_addr_01_2_0_13_ ( + .I0(com_cmm_u_cmm_cfgspace_pme_pmcsr[13]), + .I1(com_cmm_u_cmm_cfgspace_sel_encodex[1]), + .I2(com_cmm_u_cmm_cfgspace_x_lcap[0]), + .LO(com_cmm_u_cmm_cfgspace_N_3979) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_01_2_0_14_.INIT = 8'hE2; + LUT3_L com_cmm_u_cmm_cfgspace_low_addr_01_2_0_14_ ( + .I0(com_cmm_u_cmm_cfgspace_pme_pmcsr[14]), + .I1(com_cmm_u_cmm_cfgspace_sel_encodex[1]), + .I2(com_cmm_u_cmm_cfgspace_x_lcap[0]), + .LO(com_cmm_u_cmm_cfgspace_N_3980) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_01_2_0_15_.INIT = 8'hE2; + LUT3_L com_cmm_u_cmm_cfgspace_low_addr_01_2_0_15_ ( + .I0(com_cmm_u_cmm_cfgspace_pme_pmcsr[15]), + .I1(com_cmm_u_cmm_cfgspace_sel_encodex[1]), + .I2(com_cmm_u_cmm_cfgspace_x_lcap[0]), + .LO(com_cmm_u_cmm_cfgspace_N_3981) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_01_5_0_0_.INIT = 8'hAC; + LUT3_L com_cmm_u_cmm_cfgspace_low_addr_01_5_0_0_ ( + .I0(cfg_cfg_5072[656]), + .I1(com_cmm_msi_data[0]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex[1]), + .LO(com_cmm_u_cmm_cfgspace_N_4062) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_01_5_0_1_.INIT = 8'hAC; + LUT3_L com_cmm_u_cmm_cfgspace_low_addr_01_5_0_1_ ( + .I0(cfg_cfg_5072[657]), + .I1(com_cmm_msi_data[1]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex[1]), + .LO(com_cmm_u_cmm_cfgspace_N_4063) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_01_5_0_2_.INIT = 8'hAC; + LUT3_L com_cmm_u_cmm_cfgspace_low_addr_01_5_0_2_ ( + .I0(cfg_cfg_5072[658]), + .I1(com_cmm_msi_data[2]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex[1]), + .LO(com_cmm_u_cmm_cfgspace_N_4064) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_01_5_0_3_.INIT = 8'hAC; + LUT3_L com_cmm_u_cmm_cfgspace_low_addr_01_5_0_3_ ( + .I0(cfg_cfg_5072[659]), + .I1(com_cmm_msi_data[3]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex[1]), + .LO(com_cmm_u_cmm_cfgspace_N_4065) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_01_5_0_4_.INIT = 8'hAC; + LUT3_L com_cmm_u_cmm_cfgspace_low_addr_01_5_0_4_ ( + .I0(cfg_cfg_5072[660]), + .I1(com_cmm_msi_data[4]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex[1]), + .LO(com_cmm_u_cmm_cfgspace_N_4066) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_01_5_0_5_.INIT = 8'hAC; + LUT3_L com_cmm_u_cmm_cfgspace_low_addr_01_5_0_5_ ( + .I0(cfg_cfg_5072[661]), + .I1(com_cmm_msi_data[5]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex[1]), + .LO(com_cmm_u_cmm_cfgspace_N_4067) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_01_5_0_6_.INIT = 8'hAC; + LUT3_L com_cmm_u_cmm_cfgspace_low_addr_01_5_0_6_ ( + .I0(cfg_cfg_5072[662]), + .I1(com_cmm_msi_data[6]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex[1]), + .LO(com_cmm_u_cmm_cfgspace_N_4068) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_01_5_0_7_.INIT = 8'hAC; + LUT3_L com_cmm_u_cmm_cfgspace_low_addr_01_5_0_7_ ( + .I0(cfg_cfg_5072[663]), + .I1(com_cmm_msi_data[7]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex[1]), + .LO(com_cmm_u_cmm_cfgspace_N_4069) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_01_5_0_8_.INIT = 8'hAC; + LUT3_L com_cmm_u_cmm_cfgspace_low_addr_01_5_0_8_ ( + .I0(cfg_cfg_5072[664]), + .I1(com_cmm_msi_data[8]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex[1]), + .LO(com_cmm_u_cmm_cfgspace_N_4070) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_01_5_0_9_.INIT = 8'hAC; + LUT3_L com_cmm_u_cmm_cfgspace_low_addr_01_5_0_9_ ( + .I0(cfg_cfg_5072[665]), + .I1(com_cmm_msi_data[9]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex[1]), + .LO(com_cmm_u_cmm_cfgspace_N_4071) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_01_5_0_10_.INIT = 8'hAC; + LUT3_L com_cmm_u_cmm_cfgspace_low_addr_01_5_0_10_ ( + .I0(cfg_cfg_5072[666]), + .I1(com_cmm_msi_data[10]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex[1]), + .LO(com_cmm_u_cmm_cfgspace_N_4072) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_01_5_0_11_.INIT = 8'hAC; + LUT3_L com_cmm_u_cmm_cfgspace_low_addr_01_5_0_11_ ( + .I0(cfg_cfg_5072[667]), + .I1(com_cmm_msi_data[11]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex[1]), + .LO(com_cmm_u_cmm_cfgspace_N_4073) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_01_5_0_12_.INIT = 8'hAC; + LUT3_L com_cmm_u_cmm_cfgspace_low_addr_01_5_0_12_ ( + .I0(cfg_cfg_5072[668]), + .I1(com_cmm_msi_data[12]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex[1]), + .LO(com_cmm_u_cmm_cfgspace_N_4074) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_01_5_0_13_.INIT = 8'hAC; + LUT3_L com_cmm_u_cmm_cfgspace_low_addr_01_5_0_13_ ( + .I0(cfg_cfg_5072[669]), + .I1(com_cmm_msi_data[13]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex[1]), + .LO(com_cmm_u_cmm_cfgspace_N_4075) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_01_5_0_14_.INIT = 8'hAC; + LUT3_L com_cmm_u_cmm_cfgspace_low_addr_01_5_0_14_ ( + .I0(cfg_cfg_5072[670]), + .I1(com_cmm_msi_data[14]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex[1]), + .LO(com_cmm_u_cmm_cfgspace_N_4076) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_01_5_0_15_.INIT = 8'hAC; + LUT3_L com_cmm_u_cmm_cfgspace_low_addr_01_5_0_15_ ( + .I0(cfg_cfg_5072[671]), + .I1(com_cmm_msi_data[15]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex[1]), + .LO(com_cmm_u_cmm_cfgspace_N_4077) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_02_1_0_0_.INIT = 8'hCA; + LUT3_L com_cmm_u_cmm_cfgspace_low_addr_02_1_0_0_ ( + .I0(cfg_cfg_5072[32]), + .I1(cfg_cfg_5072[256]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex[1]), + .LO(com_cmm_u_cmm_cfgspace_N_4206) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_02_1_0_1_.INIT = 8'hCA; + LUT3_L com_cmm_u_cmm_cfgspace_low_addr_02_1_0_1_ ( + .I0(cfg_cfg_5072[33]), + .I1(cfg_cfg_5072[257]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex[1]), + .LO(com_cmm_u_cmm_cfgspace_N_4207) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_02_1_0_3_.INIT = 8'hCA; + LUT3_L com_cmm_u_cmm_cfgspace_low_addr_02_1_0_3_ ( + .I0(cfg_cfg_5072[35]), + .I1(cfg_cfg_5072[259]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex[1]), + .LO(com_cmm_u_cmm_cfgspace_N_4209) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_02_1_0_6_.INIT = 8'hCA; + LUT3_L com_cmm_u_cmm_cfgspace_low_addr_02_1_0_6_ ( + .I0(cfg_cfg_5072[38]), + .I1(cfg_cfg_5072[262]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex[1]), + .LO(com_cmm_u_cmm_cfgspace_N_4212) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_02_1_0_8_.INIT = 8'hCA; + LUT3 com_cmm_u_cmm_cfgspace_low_addr_02_1_0_8_ ( + .I0(cfg_cfg_5072[40]), + .I1(cfg_cfg_5072[264]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex[1]), + .O(com_cmm_u_cmm_cfgspace_N_4214) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_02_1_0_9_.INIT = 8'hCA; + LUT3 com_cmm_u_cmm_cfgspace_low_addr_02_1_0_9_ ( + .I0(cfg_cfg_5072[41]), + .I1(cfg_cfg_5072[265]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex[1]), + .O(com_cmm_u_cmm_cfgspace_N_4215) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_02_1_0_10_.INIT = 8'hCA; + LUT3 com_cmm_u_cmm_cfgspace_low_addr_02_1_0_10_ ( + .I0(cfg_cfg_5072[42]), + .I1(cfg_cfg_5072[266]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex[1]), + .O(com_cmm_u_cmm_cfgspace_N_4216) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_02_1_0_13_.INIT = 8'hCA; + LUT3 com_cmm_u_cmm_cfgspace_low_addr_02_1_0_13_ ( + .I0(cfg_cfg_5072[45]), + .I1(cfg_cfg_5072[269]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex[1]), + .O(com_cmm_u_cmm_cfgspace_N_4219) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_02_1_0_15_.INIT = 8'hCA; + LUT3 com_cmm_u_cmm_cfgspace_low_addr_02_1_0_15_ ( + .I0(cfg_cfg_5072[47]), + .I1(cfg_cfg_5072[271]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex[1]), + .O(com_cmm_u_cmm_cfgspace_N_4221) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_02_1_0_20_.INIT = 8'hCA; + LUT3_L com_cmm_u_cmm_cfgspace_low_addr_02_1_0_20_ ( + .I0(cfg_cfg_5072[52]), + .I1(cfg_cfg_5072[276]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex[1]), + .LO(com_cmm_u_cmm_cfgspace_N_4226) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_02_1_0_28_.INIT = 8'hCA; + LUT3_L com_cmm_u_cmm_cfgspace_low_addr_02_1_0_28_ ( + .I0(cfg_cfg_5072[60]), + .I1(cfg_cfg_5072[284]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex[1]), + .LO(com_cmm_u_cmm_cfgspace_N_4234) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_02_5_0_0_.INIT = 8'hCA; + LUT3_L com_cmm_u_cmm_cfgspace_low_addr_02_5_0_0_ ( + .I0(cfg_cfg_5072[424]), + .I1(cfg_cfg_5072[688]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex[1]), + .LO(com_cmm_u_cmm_cfgspace_N_4334) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_02_5_0_1_.INIT = 8'hCA; + LUT3_L com_cmm_u_cmm_cfgspace_low_addr_02_5_0_1_ ( + .I0(cfg_cfg_5072[425]), + .I1(cfg_cfg_5072[689]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex[1]), + .LO(com_cmm_u_cmm_cfgspace_N_4335) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_02_5_0_2_.INIT = 8'hCA; + LUT3_L com_cmm_u_cmm_cfgspace_low_addr_02_5_0_2_ ( + .I0(cfg_cfg_5072[426]), + .I1(cfg_cfg_5072[690]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex[1]), + .LO(com_cmm_u_cmm_cfgspace_N_4336) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_02_5_0_3_.INIT = 8'hCA; + LUT3_L com_cmm_u_cmm_cfgspace_low_addr_02_5_0_3_ ( + .I0(cfg_cfg_5072[427]), + .I1(cfg_cfg_5072[691]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex[1]), + .LO(com_cmm_u_cmm_cfgspace_N_4337) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_02_5_0_4_.INIT = 8'hCA; + LUT3_L com_cmm_u_cmm_cfgspace_low_addr_02_5_0_4_ ( + .I0(cfg_cfg_5072[428]), + .I1(cfg_cfg_5072[692]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex[1]), + .LO(com_cmm_u_cmm_cfgspace_N_4338) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_02_5_0_5_.INIT = 8'hCA; + LUT3_L com_cmm_u_cmm_cfgspace_low_addr_02_5_0_5_ ( + .I0(cfg_cfg_5072[429]), + .I1(cfg_cfg_5072[693]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex[1]), + .LO(com_cmm_u_cmm_cfgspace_N_4339) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_02_5_0_6_.INIT = 8'hCA; + LUT3_L com_cmm_u_cmm_cfgspace_low_addr_02_5_0_6_ ( + .I0(cfg_cfg_5072[430]), + .I1(cfg_cfg_5072[694]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex[1]), + .LO(com_cmm_u_cmm_cfgspace_N_4340) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_02_5_0_14_.INIT = 8'hCA; + LUT3_L com_cmm_u_cmm_cfgspace_low_addr_02_5_0_14_ ( + .I0(cfg_cfg_5072[502]), + .I1(cfg_cfg_5072[702]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex[1]), + .LO(com_cmm_u_cmm_cfgspace_N_4348) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_02_5_0_15_.INIT = 8'hCA; + LUT3_L com_cmm_u_cmm_cfgspace_low_addr_02_5_0_15_ ( + .I0(cfg_cfg_5072[502]), + .I1(cfg_cfg_5072[703]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex[1]), + .LO(com_cmm_u_cmm_cfgspace_N_4349) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_02_5_0_16_.INIT = 8'hCA; + LUT3_L com_cmm_u_cmm_cfgspace_low_addr_02_5_0_16_ ( + .I0(cfg_cfg_5072[352]), + .I1(cfg_cfg_5072[704]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex[1]), + .LO(com_cmm_u_cmm_cfgspace_N_4350) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_02_5_0_17_.INIT = 8'hCA; + LUT3_L com_cmm_u_cmm_cfgspace_low_addr_02_5_0_17_ ( + .I0(cfg_cfg_5072[353]), + .I1(cfg_cfg_5072[705]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex[1]), + .LO(com_cmm_u_cmm_cfgspace_N_4351) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_02_5_0_18_.INIT = 8'hCA; + LUT3_L com_cmm_u_cmm_cfgspace_low_addr_02_5_0_18_ ( + .I0(cfg_cfg_5072[354]), + .I1(cfg_cfg_5072[706]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex[1]), + .LO(com_cmm_u_cmm_cfgspace_N_4352) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_02_5_0_19_.INIT = 8'hCA; + LUT3_L com_cmm_u_cmm_cfgspace_low_addr_02_5_0_19_ ( + .I0(cfg_cfg_5072[355]), + .I1(cfg_cfg_5072[707]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex[1]), + .LO(com_cmm_u_cmm_cfgspace_N_4353) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_02_5_0_20_.INIT = 8'hCA; + LUT3_L com_cmm_u_cmm_cfgspace_low_addr_02_5_0_20_ ( + .I0(cfg_cfg_5072[356]), + .I1(cfg_cfg_5072[708]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex[1]), + .LO(com_cmm_u_cmm_cfgspace_N_4354) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_02_5_0_21_.INIT = 8'hCA; + LUT3_L com_cmm_u_cmm_cfgspace_low_addr_02_5_0_21_ ( + .I0(cfg_cfg_5072[357]), + .I1(cfg_cfg_5072[709]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex[1]), + .LO(com_cmm_u_cmm_cfgspace_N_4355) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_02_5_0_22_.INIT = 8'hCA; + LUT3_L com_cmm_u_cmm_cfgspace_low_addr_02_5_0_22_ ( + .I0(cfg_cfg_5072[358]), + .I1(cfg_cfg_5072[710]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex[1]), + .LO(com_cmm_u_cmm_cfgspace_N_4356) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_02_5_0_23_.INIT = 8'hCA; + LUT3_L com_cmm_u_cmm_cfgspace_low_addr_02_5_0_23_ ( + .I0(cfg_cfg_5072[359]), + .I1(cfg_cfg_5072[711]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex[1]), + .LO(com_cmm_u_cmm_cfgspace_N_4357) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_02_5_0_24_.INIT = 8'hCA; + LUT3_L com_cmm_u_cmm_cfgspace_low_addr_02_5_0_24_ ( + .I0(cfg_cfg_5072[360]), + .I1(cfg_cfg_5072[712]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex[1]), + .LO(com_cmm_u_cmm_cfgspace_N_4358) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_02_5_0_25_.INIT = 8'hCA; + LUT3_L com_cmm_u_cmm_cfgspace_low_addr_02_5_0_25_ ( + .I0(cfg_cfg_5072[361]), + .I1(cfg_cfg_5072[713]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex[1]), + .LO(com_cmm_u_cmm_cfgspace_N_4359) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_02_5_0_26_.INIT = 8'hCA; + LUT3_L com_cmm_u_cmm_cfgspace_low_addr_02_5_0_26_ ( + .I0(cfg_cfg_5072[362]), + .I1(cfg_cfg_5072[714]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex[1]), + .LO(com_cmm_u_cmm_cfgspace_N_4360) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_02_5_0_27_.INIT = 8'hCA; + LUT3_L com_cmm_u_cmm_cfgspace_low_addr_02_5_0_27_ ( + .I0(cfg_cfg_5072[363]), + .I1(cfg_cfg_5072[715]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex[1]), + .LO(com_cmm_u_cmm_cfgspace_N_4361) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_02_5_0_28_.INIT = 8'hCA; + LUT3_L com_cmm_u_cmm_cfgspace_low_addr_02_5_0_28_ ( + .I0(cfg_cfg_5072[364]), + .I1(cfg_cfg_5072[716]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex[1]), + .LO(com_cmm_u_cmm_cfgspace_N_4362) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_02_5_0_29_.INIT = 8'hCA; + LUT3_L com_cmm_u_cmm_cfgspace_low_addr_02_5_0_29_ ( + .I0(cfg_cfg_5072[365]), + .I1(cfg_cfg_5072[717]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex[1]), + .LO(com_cmm_u_cmm_cfgspace_N_4363) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_02_5_0_30_.INIT = 8'hCA; + LUT3_L com_cmm_u_cmm_cfgspace_low_addr_02_5_0_30_ ( + .I0(cfg_cfg_5072[366]), + .I1(cfg_cfg_5072[718]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex[1]), + .LO(com_cmm_u_cmm_cfgspace_N_4364) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_02_5_0_31_.INIT = 8'hCA; + LUT3_L com_cmm_u_cmm_cfgspace_low_addr_02_5_0_31_ ( + .I0(cfg_cfg_5072[367]), + .I1(cfg_cfg_5072[719]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex[1]), + .LO(com_cmm_u_cmm_cfgspace_N_4365) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_03_q_4_1_0_2_.INIT = 8'hAC; + LUT3_L com_cmm_u_cmm_cfgspace_low_addr_03_q_4_1_0_2_ ( + .I0(cfg_cfg_5072[290]), + .I1(com_cmm_u_cmm_cfgspace_cache_line[2]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex[1]), + .LO(com_cmm_u_cmm_cfgspace_N_4432) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_03_q_4_1_0_3_.INIT = 8'hAC; + LUT3_L com_cmm_u_cmm_cfgspace_low_addr_03_q_4_1_0_3_ ( + .I0(cfg_cfg_5072[291]), + .I1(com_cmm_u_cmm_cfgspace_cache_line[3]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex[1]), + .LO(com_cmm_u_cmm_cfgspace_N_4433) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_03_q_4_1_0_4_.INIT = 8'hAC; + LUT3_L com_cmm_u_cmm_cfgspace_low_addr_03_q_4_1_0_4_ ( + .I0(cfg_cfg_5072[292]), + .I1(com_cmm_u_cmm_cfgspace_cache_line[4]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex[1]), + .LO(com_cmm_u_cmm_cfgspace_N_4434) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_03_q_4_1_0_5_.INIT = 8'hAC; + LUT3_L com_cmm_u_cmm_cfgspace_low_addr_03_q_4_1_0_5_ ( + .I0(cfg_cfg_5072[293]), + .I1(com_cmm_u_cmm_cfgspace_cache_line[5]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex[1]), + .LO(com_cmm_u_cmm_cfgspace_N_4435) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_03_q_4_1_0_6_.INIT = 8'hAC; + LUT3_L com_cmm_u_cmm_cfgspace_low_addr_03_q_4_1_0_6_ ( + .I0(cfg_cfg_5072[294]), + .I1(com_cmm_u_cmm_cfgspace_cache_line[6]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex[1]), + .LO(com_cmm_u_cmm_cfgspace_N_4436) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_03_q_4_1_0_7_.INIT = 8'hAC; + LUT3_L com_cmm_u_cmm_cfgspace_low_addr_03_q_4_1_0_7_ ( + .I0(cfg_cfg_5072[295]), + .I1(com_cmm_u_cmm_cfgspace_cache_line[7]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex[1]), + .LO(com_cmm_u_cmm_cfgspace_N_4437) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_03_q_4_4_0_0_.INIT = 8'hCA; + LUT3_L com_cmm_u_cmm_cfgspace_low_addr_03_q_4_4_0_0_ ( + .I0(com_cmm_bar3_reg[0]), + .I1(com_cmm_u_cmm_cfgspace_int_line[0]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex[1]), + .LO(com_cmm_u_cmm_cfgspace_N_4526) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_03_q_4_4_0_1_.INIT = 8'hCA; + LUT3_L com_cmm_u_cmm_cfgspace_low_addr_03_q_4_4_0_1_ ( + .I0(com_cmm_bar3_reg[1]), + .I1(com_cmm_u_cmm_cfgspace_int_line[1]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex[1]), + .LO(com_cmm_u_cmm_cfgspace_N_4527) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_03_q_4_4_0_2_.INIT = 8'hCA; + LUT3_L com_cmm_u_cmm_cfgspace_low_addr_03_q_4_4_0_2_ ( + .I0(com_cmm_bar3_reg[2]), + .I1(com_cmm_u_cmm_cfgspace_int_line[2]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex[1]), + .LO(com_cmm_u_cmm_cfgspace_N_4528) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_03_q_4_4_0_3_.INIT = 8'hCA; + LUT3_L com_cmm_u_cmm_cfgspace_low_addr_03_q_4_4_0_3_ ( + .I0(com_cmm_bar3_reg[3]), + .I1(com_cmm_u_cmm_cfgspace_int_line[3]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex[1]), + .LO(com_cmm_u_cmm_cfgspace_N_4529) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_03_q_4_4_0_4_.INIT = 8'hCA; + LUT3_L com_cmm_u_cmm_cfgspace_low_addr_03_q_4_4_0_4_ ( + .I0(com_cmm_bar3_reg[4]), + .I1(com_cmm_u_cmm_cfgspace_int_line[4]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex[1]), + .LO(com_cmm_u_cmm_cfgspace_N_4530) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_03_q_4_4_0_5_.INIT = 8'hCA; + LUT3_L com_cmm_u_cmm_cfgspace_low_addr_03_q_4_4_0_5_ ( + .I0(com_cmm_bar3_reg[5]), + .I1(com_cmm_u_cmm_cfgspace_int_line[5]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex[1]), + .LO(com_cmm_u_cmm_cfgspace_N_4531) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_03_q_4_4_0_6_.INIT = 8'hCA; + LUT3_L com_cmm_u_cmm_cfgspace_low_addr_03_q_4_4_0_6_ ( + .I0(com_cmm_bar3_reg[6]), + .I1(com_cmm_u_cmm_cfgspace_int_line[6]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex[1]), + .LO(com_cmm_u_cmm_cfgspace_N_4532) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_03_q_4_4_0_7_.INIT = 8'hCA; + LUT3_L com_cmm_u_cmm_cfgspace_low_addr_03_q_4_4_0_7_ ( + .I0(com_cmm_bar3_reg[7]), + .I1(com_cmm_u_cmm_cfgspace_int_line[7]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex[1]), + .LO(com_cmm_u_cmm_cfgspace_N_4533) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_00_0_0_m3_0_13_.INIT = 8'hAC; + LUT3 com_cmm_u_cmm_cfgspace_low_addr_00_0_0_m3_0_13_ ( + .I0(NlwRenamedSig_OI_cfg_dcommand[13]), + .I1(com_cmm_bar4_reg[13]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex[2]), + .O(com_cmm_u_cmm_cfgspace_N_48992) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_00_0_0_0_m3_0_12_.INIT = 8'hAC; + LUT3 com_cmm_u_cmm_cfgspace_low_addr_00_0_0_0_m3_0_12_ ( + .I0(NlwRenamedSig_OI_cfg_dcommand[12]), + .I1(com_cmm_bar4_reg[12]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex[2]), + .O(com_cmm_u_cmm_cfgspace_N_48993) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_02_1_0_7_.INIT = 8'hCA; + LUT3_L com_cmm_u_cmm_cfgspace_low_addr_02_1_0_7_ ( + .I0(cfg_cfg_5072[39]), + .I1(cfg_cfg_5072[263]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex[1]), + .LO(com_cmm_u_cmm_cfgspace_N_4213) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_02_5_0_7_.INIT = 8'hCA; + LUT3_L com_cmm_u_cmm_cfgspace_low_addr_02_5_0_7_ ( + .I0(cfg_cfg_5072[431]), + .I1(cfg_cfg_5072[695]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex[1]), + .LO(com_cmm_u_cmm_cfgspace_N_4341) + ); + defparam com_cmm_u_cmm_cfgspace_N_9426_i.INIT = 4'hB; + LUT2 com_cmm_u_cmm_cfgspace_N_9426_i ( + .I0(com_cmm_rst_267), + .I1(com_cmm_u_cmm_cfgspace_sel_encodex_en_4519), + .O(com_cmm_u_cmm_cfgspace_N_9426_i_4518) + ); + defparam com_cmm_u_cmm_cfgspace_x3gio_msidata_msi_data12_0_a2_0_o3_i_o3.INIT = 8'h80; + LUT3 com_cmm_u_cmm_cfgspace_x3gio_msidata_msi_data12_0_a2_0_o3_i_o3 ( + .I0(com_cmm_N_48846_i), + .I1(com_cmm_state_1_), + .I2(com_cmm_state_6_), + .O(com_cmm_u_cmm_cfgspace_N_48848_i) + ); + defparam com_cmm_u_cmm_cfgspace_sel_encodex_en_3_i_0_o4_0.INIT = 8'h80; + LUT3 com_cmm_u_cmm_cfgspace_sel_encodex_en_3_i_0_o4_0 ( + .I0(com_cmm_cfg_addr[2]), + .I1(com_cmm_cfg_addr[3]), + .I2(com_cmm_cfg_addr[4]), + .O(com_cmm_u_cmm_cfgspace_sel_encodex_en_3_i_0_o4_0_4633) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_00_i_0_a2_1_1_.INIT = 4'h2; + LUT2_L com_cmm_u_cmm_cfgspace_low_addr_00_i_0_a2_1_1_ ( + .I0(com_cmm_u_cmm_cfgspace_N_50187_1), + .I1(com_cmm_msi_haddr[1]), + .LO(com_cmm_u_cmm_cfgspace_N_50135) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_00_0_a3_2_0_a2_2_.INIT = 4'h2; + LUT2 com_cmm_u_cmm_cfgspace_low_addr_00_0_a3_2_0_a2_2_ ( + .I0(com_cmm_u_cmm_cfgspace_N_50450), + .I1(com_cmm_u_cmm_cfgspace_sel_encodex[1]), + .O(com_cmm_u_cmm_cfgspace_N_50455) + ); + defparam com_cmm_u_cmm_cfgspace_x3gio_decodepipe_l_sel_x3_3_i_0_0_a3_1.INIT = 4'h2; + LUT2 com_cmm_u_cmm_cfgspace_x3gio_decodepipe_l_sel_x3_3_i_0_0_a3_1 ( + .I0(com_cmm_u_cmm_cfgspace_N_28511_i), + .I1(com_cmm_cfg_rd), + .O(com_cmm_u_cmm_cfgspace_N_50520_1) + ); + defparam com_cmm_u_cmm_cfgspace_x3gio_bar4_bar4_reg_8_1_0_0_o3_0_0_.INIT = 8'h10; + LUT3 com_cmm_u_cmm_cfgspace_x3gio_bar4_bar4_reg_8_1_0_0_o3_0_0_ ( + .I0(cfg_cfg_5072[160]), + .I1(cfg_cfg_5072[161]), + .I2(cfg_cfg_5072[162]), + .O(com_cmm_u_cmm_cfgspace_N_48894_i) + ); + defparam com_cmm_u_cmm_cfgspace_x3gio_bar5_bar5_reg_8_1_0_0_o3_0_.INIT = 8'h10; + LUT3 com_cmm_u_cmm_cfgspace_x3gio_bar5_bar5_reg_8_1_0_0_o3_0_ ( + .I0(cfg_cfg_5072[192]), + .I1(cfg_cfg_5072[193]), + .I2(cfg_cfg_5072[194]), + .O(com_cmm_u_cmm_cfgspace_N_48893_i) + ); + defparam com_cmm_u_cmm_cfgspace_x3gio_bar2_bar2_reg_8_1_0_0_o3_0_.INIT = 4'h8; + LUT2 com_cmm_u_cmm_cfgspace_x3gio_bar2_bar2_reg_8_1_0_0_o3_0_ ( + .I0(com_cmm_N_48883_i), + .I1(cfg_cfg_5072[98]), + .O(com_cmm_u_cmm_cfgspace_N_48892_i) + ); + defparam com_cmm_u_cmm_cfgspace_x3gio_bar3_bar3_reg_8_1_0_0_o3_0_.INIT = 4'h8; + LUT2 com_cmm_u_cmm_cfgspace_x3gio_bar3_bar3_reg_8_1_0_0_o3_0_ ( + .I0(com_cmm_N_48884_i), + .I1(cfg_cfg_5072[130]), + .O(com_cmm_u_cmm_cfgspace_N_48891_i) + ); + defparam com_cmm_u_cmm_cfgspace_x3gio_bar1_bar1_reg_8_1_0_0_o3_0_.INIT = 8'h10; + LUT3 com_cmm_u_cmm_cfgspace_x3gio_bar1_bar1_reg_8_1_0_0_o3_0_ ( + .I0(cfg_cfg_5072[64]), + .I1(cfg_cfg_5072[65]), + .I2(cfg_cfg_5072[66]), + .O(com_cmm_u_cmm_cfgspace_N_48888_i) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_00_i_a3_0_0_a2_1_.INIT = 4'h8; + LUT2 com_cmm_u_cmm_cfgspace_low_addr_00_i_a3_0_0_a2_1_ ( + .I0(com_cmm_u_cmm_cfgspace_N_50495), + .I1(com_cmm_u_cmm_cfgspace_sel_encodex[2]), + .O(com_cmm_u_cmm_cfgspace_N_50458) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_00_i_a3_1_a2_1_.INIT = 4'h8; + LUT2 com_cmm_u_cmm_cfgspace_low_addr_00_i_a3_1_a2_1_ ( + .I0(com_cmm_u_cmm_cfgspace_N_50489), + .I1(com_cmm_u_cmm_cfgspace_sel_encodex[1]), + .O(com_cmm_u_cmm_cfgspace_N_50457) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_00_0_a3_3_0_a2_2_.INIT = 4'h8; + LUT2 com_cmm_u_cmm_cfgspace_low_addr_00_0_a3_3_0_a2_2_ ( + .I0(com_cmm_u_cmm_cfgspace_N_50490), + .I1(com_cmm_u_cmm_cfgspace_sel_encodex[2]), + .O(com_cmm_u_cmm_cfgspace_N_50456) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_00_0_a3_1_0_a2_2_.INIT = 4'h2; + LUT2 com_cmm_u_cmm_cfgspace_low_addr_00_0_a3_1_0_a2_2_ ( + .I0(com_cmm_u_cmm_cfgspace_N_50490), + .I1(com_cmm_u_cmm_cfgspace_sel_encodex[2]), + .O(com_cmm_u_cmm_cfgspace_N_50454) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_00_0_a3_0_0_a2_2_.INIT = 4'h2; + LUT2 com_cmm_u_cmm_cfgspace_low_addr_00_0_a3_0_0_a2_2_ ( + .I0(com_cmm_u_cmm_cfgspace_N_50495), + .I1(com_cmm_u_cmm_cfgspace_sel_encodex[2]), + .O(com_cmm_u_cmm_cfgspace_N_50451) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_00_i_0_0_a2_1_31_.INIT = 4'h2; + LUT2 com_cmm_u_cmm_cfgspace_low_addr_00_i_0_0_a2_1_31_ ( + .I0(com_cmm_u_cmm_cfgspace_N_50490), + .I1(com_cmm_bar4_reg[31]), + .O(com_cmm_u_cmm_cfgspace_N_45565) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_00_i_a2_1_30_.INIT = 4'h2; + LUT2 com_cmm_u_cmm_cfgspace_low_addr_00_i_a2_1_30_ ( + .I0(com_cmm_u_cmm_cfgspace_N_50490), + .I1(com_cmm_bar4_reg[30]), + .O(com_cmm_u_cmm_cfgspace_N_45361) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_00_i_a2_1_28_.INIT = 4'h2; + LUT2 com_cmm_u_cmm_cfgspace_low_addr_00_i_a2_1_28_ ( + .I0(com_cmm_u_cmm_cfgspace_N_50490), + .I1(com_cmm_bar4_reg[28]), + .O(com_cmm_u_cmm_cfgspace_N_45355) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_00_i_a2_1_26_.INIT = 4'h2; + LUT2 com_cmm_u_cmm_cfgspace_low_addr_00_i_a2_1_26_ ( + .I0(com_cmm_u_cmm_cfgspace_N_50490), + .I1(com_cmm_bar4_reg[26]), + .O(com_cmm_u_cmm_cfgspace_N_45343) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_00_i_a2_1_25_.INIT = 4'h2; + LUT2 com_cmm_u_cmm_cfgspace_low_addr_00_i_a2_1_25_ ( + .I0(com_cmm_u_cmm_cfgspace_N_50490), + .I1(com_cmm_bar4_reg[25]), + .O(com_cmm_u_cmm_cfgspace_N_45337) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_00_i_a2_1_24_.INIT = 4'h2; + LUT2 com_cmm_u_cmm_cfgspace_low_addr_00_i_a2_1_24_ ( + .I0(com_cmm_u_cmm_cfgspace_N_50490), + .I1(com_cmm_bar4_reg[24]), + .O(com_cmm_u_cmm_cfgspace_N_45331) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_00_i_a2_1_23_.INIT = 4'h2; + LUT2 com_cmm_u_cmm_cfgspace_low_addr_00_i_a2_1_23_ ( + .I0(com_cmm_u_cmm_cfgspace_N_50490), + .I1(com_cmm_bar4_reg[23]), + .O(com_cmm_u_cmm_cfgspace_N_45325) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_00_i_a2_1_22_.INIT = 4'h2; + LUT2 com_cmm_u_cmm_cfgspace_low_addr_00_i_a2_1_22_ ( + .I0(com_cmm_u_cmm_cfgspace_N_50490), + .I1(com_cmm_bar4_reg[22]), + .O(com_cmm_u_cmm_cfgspace_N_45319) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_00_i_a2_2_20_.INIT = 4'h2; + LUT2 com_cmm_u_cmm_cfgspace_low_addr_00_i_a2_2_20_ ( + .I0(com_cmm_u_cmm_cfgspace_N_50490), + .I1(com_cmm_bar4_reg[20]), + .O(com_cmm_u_cmm_cfgspace_N_45306) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_00_i_0_0_a2_1_0_.INIT = 8'h02; + LUT3_L com_cmm_u_cmm_cfgspace_low_addr_00_i_0_0_a2_1_0_ ( + .I0(com_cmm_u_cmm_cfgspace_N_50144), + .I1(NlwRenamedSig_OI_cfg_dcommand[0]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex[0]), + .LO(com_cmm_u_cmm_cfgspace_N_42543) + ); + defparam com_cmm_u_cmm_cfgspace_sel_encodex_en_3_i_0_a2_4_1.INIT = 16'h0001; + LUT4 com_cmm_u_cmm_cfgspace_sel_encodex_en_3_i_0_a2_4_1 ( + .I0(com_cmm_cfg_addr[5]), + .I1(com_cmm_cfg_addr[7]), + .I2(com_cmm_cfg_addr[8]), + .I3(com_cmm_cfg_addr[9]), + .O(com_cmm_u_cmm_cfgspace_N_42636_1) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_00_i_i_0_a2_0_29_.INIT = 8'h80; + LUT3 com_cmm_u_cmm_cfgspace_low_addr_00_i_i_0_a2_0_29_ ( + .I0(com_cmm_u_cmm_cfgspace_N_50450), + .I1(cfg_cfg_5072[503]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex[1]), + .O(com_cmm_u_cmm_cfgspace_N_45970) + ); + defparam com_cmm_u_cmm_cfgspace_decoder_sel_addr_0_0_0_o3_0_.INIT = 8'h02; + LUT3 com_cmm_u_cmm_cfgspace_decoder_sel_addr_0_0_0_o3_0_ ( + .I0(com_cmm_u_cmm_cfgspace_N_28511_i), + .I1(com_cmm_u_cmm_cfgspace_cfg2ulm_valid), + .I2(com_cmm_u_cmm_cfgspace_state_0__4782), + .O(com_cmm_u_cmm_cfgspace_N_48842_i) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_00_i_0_0_a2_0_.INIT = 16'h02A2; + LUT4 com_cmm_u_cmm_cfgspace_low_addr_00_i_0_0_a2_0_ ( + .I0(com_cmm_u_cmm_cfgspace_N_50137_1), + .I1(com_cmm_bar4_reg[0]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex[0]), + .I3(com_cmm_xrom_reg_0_), + .O(com_cmm_u_cmm_cfgspace_N_42541) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_00_i_i_0_a2_29_.INIT = 16'hA088; + LUT4 com_cmm_u_cmm_cfgspace_low_addr_00_i_i_0_a2_29_ ( + .I0(com_cmm_u_cmm_cfgspace_N_50495), + .I1(cfg_cfg_5072[29]), + .I2(cfg_cfg_5072[525]), + .I3(com_cmm_u_cmm_cfgspace_sel_encodex[2]), + .O(com_cmm_u_cmm_cfgspace_N_45969) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_00_i_0_a2_27_.INIT = 16'h3500; + LUT4 com_cmm_u_cmm_cfgspace_low_addr_00_i_0_a2_27_ ( + .I0(cfg_cfg_5072[523]), + .I1(com_cmm_msi_haddr[27]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex[0]), + .I3(com_cmm_u_cmm_cfgspace_sel_encodex[2]), + .O(com_cmm_u_cmm_cfgspace_N_50143) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_00_i_0_a2_0_16_.INIT = 16'h0A22; + LUT4 com_cmm_u_cmm_cfgspace_low_addr_00_i_0_a2_0_16_ ( + .I0(com_cmm_u_cmm_cfgspace_N_50495), + .I1(cfg_cfg_5072[16]), + .I2(cfg_cfg_5072[512]), + .I3(com_cmm_u_cmm_cfgspace_sel_encodex[2]), + .O(com_cmm_u_cmm_cfgspace_N_50139) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_00_i_0_a2_16_.INIT = 16'h220A; + LUT4 com_cmm_u_cmm_cfgspace_low_addr_00_i_0_a2_16_ ( + .I0(com_cmm_u_cmm_cfgspace_N_50490), + .I1(NlwRenamedSig_OI_cfg_dstatus_0_), + .I2(com_cmm_bar4_reg[16]), + .I3(com_cmm_u_cmm_cfgspace_sel_encodex[2]), + .O(com_cmm_u_cmm_cfgspace_N_50138) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_02_6_0_11_.INIT = 16'hA00C; + LUT4 com_cmm_u_cmm_cfgspace_low_addr_02_6_0_11_ ( + .I0(cfg_cfg_5072[699]), + .I1(com_cmm_bar2_reg[11]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex[1]), + .I3(com_cmm_u_cmm_cfgspace_sel_encodex[2]), + .O(com_cmm_u_cmm_cfgspace_N_4377) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_02_6_0_12_.INIT = 16'hA00C; + LUT4 com_cmm_u_cmm_cfgspace_low_addr_02_6_0_12_ ( + .I0(cfg_cfg_5072[700]), + .I1(com_cmm_bar2_reg[12]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex[1]), + .I3(com_cmm_u_cmm_cfgspace_sel_encodex[2]), + .O(com_cmm_u_cmm_cfgspace_N_4378) + ); + defparam com_cmm_u_cmm_cfgspace_x3gio_decodepipe_h_sel_0x_3_0_0_0_a2_0.INIT = 4'h2; + LUT2 com_cmm_u_cmm_cfgspace_x3gio_decodepipe_h_sel_0x_3_0_0_0_a2_0 ( + .I0(com_cmm_u_cmm_cfgspace_N_48842_i), + .I1(com_cmm_state_1_), + .O(com_cmm_u_cmm_cfgspace_N_49170) + ); + defparam com_cmm_u_cmm_cfgspace_decoder_sel_addr_0_0_a3_0_a3_0_.INIT = 4'h8; + LUT2 com_cmm_u_cmm_cfgspace_decoder_sel_addr_0_0_a3_0_a3_0_ ( + .I0(com_cmm_u_cmm_cfgspace_N_48842_i), + .I1(com_cmm_state_1_), + .O(com_cmm_u_cmm_cfgspace_N_50491) + ); + defparam com_cmm_u_cmm_cfgspace_x3gio_decodepipe_h_sel_1x_3_0_0_a3_0_a3.INIT = 4'h2; + LUT2 com_cmm_u_cmm_cfgspace_x3gio_decodepipe_h_sel_1x_3_0_0_a3_0_a3 ( + .I0(com_cmm_u_cmm_cfgspace_N_42636_1), + .I1(com_cmm_cfg_addr[6]), + .O(com_cmm_u_cmm_cfgspace_N_50496) + ); + defparam com_cmm_u_cmm_cfgspace_x3gio_dsts_N_44850_i_0_o3.INIT = 4'h8; + LUT2 com_cmm_u_cmm_cfgspace_x3gio_dsts_N_44850_i_0_o3 ( + .I0(com_cmm_u_cmm_cfgspace_N_48848_i), + .I1(com_cmm_u_cmm_cfgspace_sel_6x_4753), + .O(com_cmm_u_cmm_cfgspace_N_48874_i) + ); + defparam com_cmm_u_cmm_cfgspace_x3gio_decodepipe_l_sel_x0_3_i_0_0_a3.INIT = 16'h222A; + LUT4 com_cmm_u_cmm_cfgspace_x3gio_decodepipe_l_sel_x0_3_i_0_0_a3 ( + .I0(com_cmm_u_cmm_cfgspace_N_28511_i), + .I1(com_cmm_state_1_), + .I2(com_cmm_u_cmm_cfgspace_state_4__4778), + .I3(com_cmm_u_cmm_cfgspace_state_5__4777), + .O(com_cmm_u_cmm_cfgspace_N_50484) + ); + defparam com_cmm_u_cmm_cfgspace_x3gio_bar0_bar0_reg18_0_a2_0_a2_0_o3.INIT = 4'h8; + LUT2 com_cmm_u_cmm_cfgspace_x3gio_bar0_bar0_reg18_0_a2_0_a2_0_o3 ( + .I0(com_cmm_u_cmm_cfgspace_N_48848_i), + .I1(com_cmm_u_cmm_cfgspace_sel_1x_4758), + .O(com_cmm_u_cmm_cfgspace_N_44842_i) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_01_3_0_am_0_.INIT = 8'hCA; + LUT3 com_cmm_u_cmm_cfgspace_low_addr_01_3_0_am_0_ ( + .I0(NlwRenamedSig_OI_cfg_command_0_), + .I1(com_cmm_bar5_reg[0]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex_1[1]), + .O(com_cmm_u_cmm_cfgspace_low_addr_01_3_0_am_0__4521) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_01_3_0_bm_0_.INIT = 8'hE2; + LUT3 com_cmm_u_cmm_cfgspace_low_addr_01_3_0_bm_0_ ( + .I0(com_cmm_pme_pmcsr[0]), + .I1(com_cmm_u_cmm_cfgspace_sel_encodex_1[1]), + .I2(com_cmm_u_cmm_cfgspace_x_lcap[0]), + .O(com_cmm_u_cmm_cfgspace_low_addr_01_3_0_bm_0__4520) + ); + MUXF5 com_cmm_u_cmm_cfgspace_low_addr_01_3_0_0_ ( + .I0(com_cmm_u_cmm_cfgspace_low_addr_01_3_0_am_0__4521), + .I1(com_cmm_u_cmm_cfgspace_low_addr_01_3_0_bm_0__4520), + .O(com_cmm_u_cmm_cfgspace_N_3998), + .S(com_cmm_u_cmm_cfgspace_sel_encodex_2[2]) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_01_3_0_am_10_.INIT = 8'hCA; + LUT3 com_cmm_u_cmm_cfgspace_low_addr_01_3_0_am_10_ ( + .I0(NlwRenamedSig_OI_cfg_command_10_), + .I1(com_cmm_bar5_reg[10]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex_1[1]), + .O(com_cmm_u_cmm_cfgspace_low_addr_01_3_0_am_10__4523) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_01_3_0_bm_10_.INIT = 8'hAC; + LUT3 com_cmm_u_cmm_cfgspace_low_addr_01_3_0_bm_10_ ( + .I0(cfg_cfg_5072[410]), + .I1(com_cmm_u_cmm_cfgspace_pme_pmcsr[10]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex_1[1]), + .O(com_cmm_u_cmm_cfgspace_low_addr_01_3_0_bm_10__4522) + ); + MUXF5 com_cmm_u_cmm_cfgspace_low_addr_01_3_0_10_ ( + .I0(com_cmm_u_cmm_cfgspace_low_addr_01_3_0_am_10__4523), + .I1(com_cmm_u_cmm_cfgspace_low_addr_01_3_0_bm_10__4522), + .O(com_cmm_u_cmm_cfgspace_N_4008), + .S(com_cmm_u_cmm_cfgspace_sel_encodex_2[2]) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_01_6_0_0_.INIT = 16'hAA0C; + LUT4_L com_cmm_u_cmm_cfgspace_low_addr_01_6_0_0_ ( + .I0(com_cmm_u_cmm_cfgspace_N_4062), + .I1(com_cmm_bar1_reg[0]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex_1[1]), + .I3(com_cmm_u_cmm_cfgspace_sel_encodex[2]), + .LO(com_cmm_u_cmm_cfgspace_N_4094) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_01_6_0_10_.INIT = 16'hAA0C; + LUT4 com_cmm_u_cmm_cfgspace_low_addr_01_6_0_10_ ( + .I0(com_cmm_u_cmm_cfgspace_N_4072), + .I1(com_cmm_bar1_reg[10]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex_1[1]), + .I3(com_cmm_u_cmm_cfgspace_sel_encodex[2]), + .O(com_cmm_u_cmm_cfgspace_N_4104) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_02_3_0_am_16_.INIT = 8'hCA; + LUT3 com_cmm_u_cmm_cfgspace_low_addr_02_3_0_am_16_ ( + .I0(cfg_cfg_5072[48]), + .I1(cfg_cfg_5072[272]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex_1[1]), + .O(com_cmm_u_cmm_cfgspace_low_addr_02_3_0_am_16__4525) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_02_3_0_bm_16_.INIT = 8'hB8; + LUT3 com_cmm_u_cmm_cfgspace_low_addr_02_3_0_bm_16_ ( + .I0(NlwRenamedSig_OI_cfg_lstatus_4_), + .I1(com_cmm_u_cmm_cfgspace_sel_encodex_1[1]), + .I2(com_cmm_msi_control_1[0]), + .O(com_cmm_u_cmm_cfgspace_low_addr_02_3_0_bm_16__4524) + ); + MUXF5 com_cmm_u_cmm_cfgspace_low_addr_02_3_0_16_ ( + .I0(com_cmm_u_cmm_cfgspace_low_addr_02_3_0_am_16__4525), + .I1(com_cmm_u_cmm_cfgspace_low_addr_02_3_0_bm_16__4524), + .O(com_cmm_u_cmm_cfgspace_N_4286), + .S(com_cmm_u_cmm_cfgspace_sel_encodex_2[2]) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_02_6_0_14_.INIT = 16'hAA0C; + LUT4 com_cmm_u_cmm_cfgspace_low_addr_02_6_0_14_ ( + .I0(com_cmm_u_cmm_cfgspace_N_4348), + .I1(com_cmm_bar2_reg[14]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex_1[1]), + .I3(com_cmm_u_cmm_cfgspace_sel_encodex[2]), + .O(com_cmm_u_cmm_cfgspace_N_4380) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_02_6_0_16_.INIT = 16'hAA0C; + LUT4 com_cmm_u_cmm_cfgspace_low_addr_02_6_0_16_ ( + .I0(com_cmm_u_cmm_cfgspace_N_4350), + .I1(com_cmm_bar2_reg[16]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex_1[1]), + .I3(com_cmm_u_cmm_cfgspace_sel_encodex[2]), + .O(com_cmm_u_cmm_cfgspace_N_4382) + ); + defparam com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_am_0_.INIT = 8'hCA; + LUT3 com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_am_0_ ( + .I0(com_cmm_u_cmm_cfgspace_low_addr_00_q[0]), + .I1(com_cmm_u_cmm_cfgspace_low_addr_02_q[0]), + .I2(com_cmm_u_cmm_cfgspace_sel_xencode[1]), + .O(com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_am[0]) + ); + defparam com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_bm_0_.INIT = 8'hCA; + LUT3 com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_bm_0_ ( + .I0(com_cmm_u_cmm_cfgspace_low_addr_01_q[0]), + .I1(com_cmm_u_cmm_cfgspace_low_addr_03_q[0]), + .I2(com_cmm_u_cmm_cfgspace_sel_xencode[1]), + .O(com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_bm[0]) + ); + MUXF5 com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_0_ ( + .I0(com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_am[0]), + .I1(com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_bm[0]), + .O(com_cmm_u_cmm_cfgspace_decoder_read_data[0]), + .S(com_cmm_u_cmm_cfgspace_sel_xencode[0]) + ); + defparam com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_am_1_.INIT = 8'hCA; + LUT3 com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_am_1_ ( + .I0(com_cmm_u_cmm_cfgspace_low_addr_00_q[1]), + .I1(com_cmm_u_cmm_cfgspace_low_addr_02_q[1]), + .I2(com_cmm_u_cmm_cfgspace_sel_xencode[1]), + .O(com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_am[1]) + ); + defparam com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_bm_1_.INIT = 8'hCA; + LUT3 com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_bm_1_ ( + .I0(com_cmm_u_cmm_cfgspace_low_addr_01_q[1]), + .I1(com_cmm_u_cmm_cfgspace_low_addr_03_q[1]), + .I2(com_cmm_u_cmm_cfgspace_sel_xencode[1]), + .O(com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_bm[1]) + ); + MUXF5 com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_1_ ( + .I0(com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_am[1]), + .I1(com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_bm[1]), + .O(com_cmm_u_cmm_cfgspace_decoder_read_data[1]), + .S(com_cmm_u_cmm_cfgspace_sel_xencode[0]) + ); + defparam com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_am_2_.INIT = 8'hCA; + LUT3 com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_am_2_ ( + .I0(com_cmm_u_cmm_cfgspace_low_addr_00_q[2]), + .I1(com_cmm_u_cmm_cfgspace_low_addr_02_q[2]), + .I2(com_cmm_u_cmm_cfgspace_sel_xencode[1]), + .O(com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_am[2]) + ); + defparam com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_bm_2_.INIT = 8'hCA; + LUT3 com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_bm_2_ ( + .I0(com_cmm_u_cmm_cfgspace_low_addr_01_q[2]), + .I1(com_cmm_u_cmm_cfgspace_low_addr_03_q[2]), + .I2(com_cmm_u_cmm_cfgspace_sel_xencode[1]), + .O(com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_bm[2]) + ); + MUXF5 com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_2_ ( + .I0(com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_am[2]), + .I1(com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_bm[2]), + .O(com_cmm_u_cmm_cfgspace_decoder_read_data[2]), + .S(com_cmm_u_cmm_cfgspace_sel_xencode[0]) + ); + defparam com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_am_3_.INIT = 8'hCA; + LUT3 com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_am_3_ ( + .I0(com_cmm_u_cmm_cfgspace_low_addr_00_q[3]), + .I1(com_cmm_u_cmm_cfgspace_low_addr_02_q[3]), + .I2(com_cmm_u_cmm_cfgspace_sel_xencode[1]), + .O(com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_am[3]) + ); + defparam com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_bm_3_.INIT = 8'hCA; + LUT3 com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_bm_3_ ( + .I0(com_cmm_u_cmm_cfgspace_low_addr_01_q[3]), + .I1(com_cmm_u_cmm_cfgspace_low_addr_03_q[3]), + .I2(com_cmm_u_cmm_cfgspace_sel_xencode[1]), + .O(com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_bm[3]) + ); + MUXF5 com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_3_ ( + .I0(com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_am[3]), + .I1(com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_bm[3]), + .O(com_cmm_u_cmm_cfgspace_decoder_read_data[3]), + .S(com_cmm_u_cmm_cfgspace_sel_xencode[0]) + ); + defparam com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_am_4_.INIT = 8'hCA; + LUT3 com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_am_4_ ( + .I0(com_cmm_u_cmm_cfgspace_low_addr_00_q[4]), + .I1(com_cmm_u_cmm_cfgspace_low_addr_02_q[4]), + .I2(com_cmm_u_cmm_cfgspace_sel_xencode[1]), + .O(com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_am[4]) + ); + defparam com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_bm_4_.INIT = 8'hCA; + LUT3 com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_bm_4_ ( + .I0(com_cmm_u_cmm_cfgspace_low_addr_01_q[4]), + .I1(com_cmm_u_cmm_cfgspace_low_addr_03_q[4]), + .I2(com_cmm_u_cmm_cfgspace_sel_xencode[1]), + .O(com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_bm[4]) + ); + MUXF5 com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_4_ ( + .I0(com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_am[4]), + .I1(com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_bm[4]), + .O(com_cmm_u_cmm_cfgspace_decoder_read_data[4]), + .S(com_cmm_u_cmm_cfgspace_sel_xencode[0]) + ); + defparam com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_am_5_.INIT = 8'hCA; + LUT3 com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_am_5_ ( + .I0(com_cmm_u_cmm_cfgspace_low_addr_00_q[5]), + .I1(com_cmm_u_cmm_cfgspace_low_addr_02_q[5]), + .I2(com_cmm_u_cmm_cfgspace_sel_xencode[1]), + .O(com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_am[5]) + ); + defparam com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_bm_5_.INIT = 8'hCA; + LUT3 com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_bm_5_ ( + .I0(com_cmm_u_cmm_cfgspace_low_addr_01_q[5]), + .I1(com_cmm_u_cmm_cfgspace_low_addr_03_q[5]), + .I2(com_cmm_u_cmm_cfgspace_sel_xencode[1]), + .O(com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_bm[5]) + ); + MUXF5 com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_5_ ( + .I0(com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_am[5]), + .I1(com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_bm[5]), + .O(com_cmm_u_cmm_cfgspace_decoder_read_data[5]), + .S(com_cmm_u_cmm_cfgspace_sel_xencode[0]) + ); + defparam com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_am_6_.INIT = 8'hCA; + LUT3 com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_am_6_ ( + .I0(com_cmm_u_cmm_cfgspace_low_addr_00_q[6]), + .I1(com_cmm_u_cmm_cfgspace_low_addr_02_q[6]), + .I2(com_cmm_u_cmm_cfgspace_sel_xencode[1]), + .O(com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_am[6]) + ); + defparam com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_bm_6_.INIT = 8'hCA; + LUT3 com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_bm_6_ ( + .I0(com_cmm_u_cmm_cfgspace_low_addr_01_q[6]), + .I1(com_cmm_u_cmm_cfgspace_low_addr_03_q[6]), + .I2(com_cmm_u_cmm_cfgspace_sel_xencode[1]), + .O(com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_bm[6]) + ); + MUXF5 com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_6_ ( + .I0(com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_am[6]), + .I1(com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_bm[6]), + .O(com_cmm_u_cmm_cfgspace_decoder_read_data[6]), + .S(com_cmm_u_cmm_cfgspace_sel_xencode[0]) + ); + defparam com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_am_7_.INIT = 8'hCA; + LUT3 com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_am_7_ ( + .I0(com_cmm_u_cmm_cfgspace_low_addr_00_q[7]), + .I1(com_cmm_u_cmm_cfgspace_low_addr_02_q[7]), + .I2(com_cmm_u_cmm_cfgspace_sel_xencode[1]), + .O(com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_am[7]) + ); + defparam com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_bm_7_.INIT = 8'hCA; + LUT3 com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_bm_7_ ( + .I0(com_cmm_u_cmm_cfgspace_low_addr_01_q[7]), + .I1(com_cmm_u_cmm_cfgspace_low_addr_03_q[7]), + .I2(com_cmm_u_cmm_cfgspace_sel_xencode[1]), + .O(com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_bm[7]) + ); + MUXF5 com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_7_ ( + .I0(com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_am[7]), + .I1(com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_bm[7]), + .O(com_cmm_u_cmm_cfgspace_decoder_read_data[7]), + .S(com_cmm_u_cmm_cfgspace_sel_xencode[0]) + ); + defparam com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_am_8_.INIT = 8'hCA; + LUT3 com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_am_8_ ( + .I0(com_cmm_u_cmm_cfgspace_low_addr_00_q[8]), + .I1(com_cmm_u_cmm_cfgspace_low_addr_02_q[8]), + .I2(com_cmm_u_cmm_cfgspace_sel_xencode[1]), + .O(com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_am[8]) + ); + defparam com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_bm_8_.INIT = 8'hCA; + LUT3 com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_bm_8_ ( + .I0(com_cmm_u_cmm_cfgspace_low_addr_01_q[8]), + .I1(com_cmm_u_cmm_cfgspace_low_addr_03_q[8]), + .I2(com_cmm_u_cmm_cfgspace_sel_xencode[1]), + .O(com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_bm[8]) + ); + MUXF5 com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_8_ ( + .I0(com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_am[8]), + .I1(com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_bm[8]), + .O(com_cmm_u_cmm_cfgspace_decoder_read_data[8]), + .S(com_cmm_u_cmm_cfgspace_sel_xencode[0]) + ); + defparam com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_am_9_.INIT = 8'hCA; + LUT3 com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_am_9_ ( + .I0(com_cmm_u_cmm_cfgspace_low_addr_00_q[9]), + .I1(com_cmm_u_cmm_cfgspace_low_addr_02_q[9]), + .I2(com_cmm_u_cmm_cfgspace_sel_xencode[1]), + .O(com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_am[9]) + ); + defparam com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_bm_9_.INIT = 8'hCA; + LUT3 com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_bm_9_ ( + .I0(com_cmm_u_cmm_cfgspace_low_addr_01_q[9]), + .I1(com_cmm_u_cmm_cfgspace_low_addr_03_q[9]), + .I2(com_cmm_u_cmm_cfgspace_sel_xencode[1]), + .O(com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_bm[9]) + ); + MUXF5 com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_9_ ( + .I0(com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_am[9]), + .I1(com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_bm[9]), + .O(com_cmm_u_cmm_cfgspace_decoder_read_data[9]), + .S(com_cmm_u_cmm_cfgspace_sel_xencode[0]) + ); + defparam com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_am_10_.INIT = 8'hCA; + LUT3 com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_am_10_ ( + .I0(com_cmm_u_cmm_cfgspace_low_addr_00_q[10]), + .I1(com_cmm_u_cmm_cfgspace_low_addr_02_q[10]), + .I2(com_cmm_u_cmm_cfgspace_sel_xencode[1]), + .O(com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_am[10]) + ); + defparam com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_bm_10_.INIT = 8'hCA; + LUT3 com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_bm_10_ ( + .I0(com_cmm_u_cmm_cfgspace_low_addr_01_q[10]), + .I1(com_cmm_u_cmm_cfgspace_low_addr_03_q[10]), + .I2(com_cmm_u_cmm_cfgspace_sel_xencode[1]), + .O(com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_bm[10]) + ); + MUXF5 com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_10_ ( + .I0(com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_am[10]), + .I1(com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_bm[10]), + .O(com_cmm_u_cmm_cfgspace_decoder_read_data[10]), + .S(com_cmm_u_cmm_cfgspace_sel_xencode[0]) + ); + defparam com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_am_11_.INIT = 8'hCA; + LUT3 com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_am_11_ ( + .I0(com_cmm_u_cmm_cfgspace_low_addr_00_q[11]), + .I1(com_cmm_u_cmm_cfgspace_low_addr_02_q[11]), + .I2(com_cmm_u_cmm_cfgspace_sel_xencode[1]), + .O(com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_am[11]) + ); + defparam com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_bm_11_.INIT = 8'hCA; + LUT3 com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_bm_11_ ( + .I0(com_cmm_u_cmm_cfgspace_low_addr_01_q[11]), + .I1(com_cmm_u_cmm_cfgspace_low_addr_03_q[11]), + .I2(com_cmm_u_cmm_cfgspace_sel_xencode[1]), + .O(com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_bm[11]) + ); + MUXF5 com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_11_ ( + .I0(com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_am[11]), + .I1(com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_bm[11]), + .O(com_cmm_u_cmm_cfgspace_decoder_read_data[11]), + .S(com_cmm_u_cmm_cfgspace_sel_xencode[0]) + ); + defparam com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_am_12_.INIT = 8'hCA; + LUT3 com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_am_12_ ( + .I0(com_cmm_u_cmm_cfgspace_low_addr_00_q[12]), + .I1(com_cmm_u_cmm_cfgspace_low_addr_02_q[12]), + .I2(com_cmm_u_cmm_cfgspace_sel_xencode[1]), + .O(com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_am[12]) + ); + defparam com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_bm_12_.INIT = 8'hCA; + LUT3 com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_bm_12_ ( + .I0(com_cmm_u_cmm_cfgspace_low_addr_01_q[12]), + .I1(com_cmm_u_cmm_cfgspace_low_addr_03_q[12]), + .I2(com_cmm_u_cmm_cfgspace_sel_xencode[1]), + .O(com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_bm[12]) + ); + MUXF5 com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_12_ ( + .I0(com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_am[12]), + .I1(com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_bm[12]), + .O(com_cmm_u_cmm_cfgspace_decoder_read_data[12]), + .S(com_cmm_u_cmm_cfgspace_sel_xencode[0]) + ); + defparam com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_am_13_.INIT = 8'hCA; + LUT3 com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_am_13_ ( + .I0(com_cmm_u_cmm_cfgspace_low_addr_00_q[13]), + .I1(com_cmm_u_cmm_cfgspace_low_addr_02_q[13]), + .I2(com_cmm_u_cmm_cfgspace_sel_xencode[1]), + .O(com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_am[13]) + ); + defparam com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_bm_13_.INIT = 8'hCA; + LUT3 com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_bm_13_ ( + .I0(com_cmm_u_cmm_cfgspace_low_addr_01_q[13]), + .I1(com_cmm_u_cmm_cfgspace_low_addr_03_q[13]), + .I2(com_cmm_u_cmm_cfgspace_sel_xencode[1]), + .O(com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_bm[13]) + ); + MUXF5 com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_13_ ( + .I0(com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_am[13]), + .I1(com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_bm[13]), + .O(com_cmm_u_cmm_cfgspace_decoder_read_data[13]), + .S(com_cmm_u_cmm_cfgspace_sel_xencode[0]) + ); + defparam com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_am_14_.INIT = 8'hCA; + LUT3 com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_am_14_ ( + .I0(com_cmm_u_cmm_cfgspace_low_addr_00_q[14]), + .I1(com_cmm_u_cmm_cfgspace_low_addr_02_q[14]), + .I2(com_cmm_u_cmm_cfgspace_sel_xencode[1]), + .O(com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_am[14]) + ); + defparam com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_bm_14_.INIT = 8'hCA; + LUT3 com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_bm_14_ ( + .I0(com_cmm_u_cmm_cfgspace_low_addr_01_q[14]), + .I1(com_cmm_u_cmm_cfgspace_low_addr_03_q[14]), + .I2(com_cmm_u_cmm_cfgspace_sel_xencode[1]), + .O(com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_bm[14]) + ); + MUXF5 com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_14_ ( + .I0(com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_am[14]), + .I1(com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_bm[14]), + .O(com_cmm_u_cmm_cfgspace_decoder_read_data[14]), + .S(com_cmm_u_cmm_cfgspace_sel_xencode[0]) + ); + defparam com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_am_15_.INIT = 8'hCA; + LUT3 com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_am_15_ ( + .I0(com_cmm_u_cmm_cfgspace_low_addr_00_q[15]), + .I1(com_cmm_u_cmm_cfgspace_low_addr_02_q[15]), + .I2(com_cmm_u_cmm_cfgspace_sel_xencode[1]), + .O(com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_am[15]) + ); + defparam com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_bm_15_.INIT = 8'hCA; + LUT3 com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_bm_15_ ( + .I0(com_cmm_u_cmm_cfgspace_low_addr_01_q[15]), + .I1(com_cmm_u_cmm_cfgspace_low_addr_03_q[15]), + .I2(com_cmm_u_cmm_cfgspace_sel_xencode[1]), + .O(com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_bm[15]) + ); + MUXF5 com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_15_ ( + .I0(com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_am[15]), + .I1(com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_bm[15]), + .O(com_cmm_u_cmm_cfgspace_decoder_read_data[15]), + .S(com_cmm_u_cmm_cfgspace_sel_xencode[0]) + ); + defparam com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_am_16_.INIT = 8'hCA; + LUT3 com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_am_16_ ( + .I0(com_cmm_u_cmm_cfgspace_low_addr_00_q[16]), + .I1(com_cmm_u_cmm_cfgspace_low_addr_02_q[16]), + .I2(com_cmm_u_cmm_cfgspace_sel_xencode[1]), + .O(com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_am[16]) + ); + defparam com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_bm_16_.INIT = 8'hCA; + LUT3 com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_bm_16_ ( + .I0(com_cmm_u_cmm_cfgspace_low_addr_01_q[16]), + .I1(com_cmm_u_cmm_cfgspace_low_addr_03_q[16]), + .I2(com_cmm_u_cmm_cfgspace_sel_xencode[1]), + .O(com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_bm[16]) + ); + MUXF5 com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_16_ ( + .I0(com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_am[16]), + .I1(com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_bm[16]), + .O(com_cmm_u_cmm_cfgspace_decoder_read_data[16]), + .S(com_cmm_u_cmm_cfgspace_sel_xencode[0]) + ); + defparam com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_am_17_.INIT = 8'hCA; + LUT3 com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_am_17_ ( + .I0(com_cmm_u_cmm_cfgspace_low_addr_00_q[17]), + .I1(com_cmm_u_cmm_cfgspace_low_addr_02_q[17]), + .I2(com_cmm_u_cmm_cfgspace_sel_xencode[1]), + .O(com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_am[17]) + ); + defparam com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_bm_17_.INIT = 8'hCA; + LUT3 com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_bm_17_ ( + .I0(com_cmm_u_cmm_cfgspace_low_addr_01_q[17]), + .I1(com_cmm_u_cmm_cfgspace_low_addr_03_q[17]), + .I2(com_cmm_u_cmm_cfgspace_sel_xencode[1]), + .O(com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_bm[17]) + ); + MUXF5 com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_17_ ( + .I0(com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_am[17]), + .I1(com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_bm[17]), + .O(com_cmm_u_cmm_cfgspace_decoder_read_data[17]), + .S(com_cmm_u_cmm_cfgspace_sel_xencode[0]) + ); + defparam com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_am_18_.INIT = 8'hCA; + LUT3 com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_am_18_ ( + .I0(com_cmm_u_cmm_cfgspace_low_addr_00_q[18]), + .I1(com_cmm_u_cmm_cfgspace_low_addr_02_q[18]), + .I2(com_cmm_u_cmm_cfgspace_sel_xencode[1]), + .O(com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_am[18]) + ); + defparam com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_bm_18_.INIT = 8'hCA; + LUT3 com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_bm_18_ ( + .I0(com_cmm_u_cmm_cfgspace_low_addr_01_q[18]), + .I1(com_cmm_u_cmm_cfgspace_low_addr_03_q[18]), + .I2(com_cmm_u_cmm_cfgspace_sel_xencode[1]), + .O(com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_bm[18]) + ); + MUXF5 com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_18_ ( + .I0(com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_am[18]), + .I1(com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_bm[18]), + .O(com_cmm_u_cmm_cfgspace_decoder_read_data[18]), + .S(com_cmm_u_cmm_cfgspace_sel_xencode[0]) + ); + defparam com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_am_19_.INIT = 8'hCA; + LUT3 com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_am_19_ ( + .I0(com_cmm_u_cmm_cfgspace_low_addr_00_q[19]), + .I1(com_cmm_u_cmm_cfgspace_low_addr_02_q[19]), + .I2(com_cmm_u_cmm_cfgspace_sel_xencode[1]), + .O(com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_am[19]) + ); + defparam com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_bm_19_.INIT = 8'hCA; + LUT3 com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_bm_19_ ( + .I0(com_cmm_u_cmm_cfgspace_low_addr_01_q[19]), + .I1(com_cmm_u_cmm_cfgspace_low_addr_03_q[19]), + .I2(com_cmm_u_cmm_cfgspace_sel_xencode[1]), + .O(com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_bm[19]) + ); + MUXF5 com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_19_ ( + .I0(com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_am[19]), + .I1(com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_bm[19]), + .O(com_cmm_u_cmm_cfgspace_decoder_read_data[19]), + .S(com_cmm_u_cmm_cfgspace_sel_xencode[0]) + ); + defparam com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_am_20_.INIT = 8'hCA; + LUT3 com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_am_20_ ( + .I0(com_cmm_u_cmm_cfgspace_low_addr_00_q[20]), + .I1(com_cmm_u_cmm_cfgspace_low_addr_02_q[20]), + .I2(com_cmm_u_cmm_cfgspace_sel_xencode[1]), + .O(com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_am[20]) + ); + defparam com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_bm_20_.INIT = 8'hCA; + LUT3 com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_bm_20_ ( + .I0(com_cmm_u_cmm_cfgspace_low_addr_01_q[20]), + .I1(com_cmm_u_cmm_cfgspace_low_addr_03_q[20]), + .I2(com_cmm_u_cmm_cfgspace_sel_xencode[1]), + .O(com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_bm[20]) + ); + MUXF5 com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_20_ ( + .I0(com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_am[20]), + .I1(com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_bm[20]), + .O(com_cmm_u_cmm_cfgspace_decoder_read_data[20]), + .S(com_cmm_u_cmm_cfgspace_sel_xencode[0]) + ); + defparam com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_am_21_.INIT = 8'hCA; + LUT3 com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_am_21_ ( + .I0(com_cmm_u_cmm_cfgspace_low_addr_00_q[21]), + .I1(com_cmm_u_cmm_cfgspace_low_addr_02_q[21]), + .I2(com_cmm_u_cmm_cfgspace_sel_xencode[1]), + .O(com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_am[21]) + ); + defparam com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_bm_21_.INIT = 8'hCA; + LUT3 com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_bm_21_ ( + .I0(com_cmm_u_cmm_cfgspace_low_addr_01_q[21]), + .I1(com_cmm_u_cmm_cfgspace_low_addr_03_q[21]), + .I2(com_cmm_u_cmm_cfgspace_sel_xencode[1]), + .O(com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_bm[21]) + ); + MUXF5 com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_21_ ( + .I0(com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_am[21]), + .I1(com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_bm[21]), + .O(com_cmm_u_cmm_cfgspace_decoder_read_data[21]), + .S(com_cmm_u_cmm_cfgspace_sel_xencode[0]) + ); + defparam com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_am_22_.INIT = 8'hCA; + LUT3 com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_am_22_ ( + .I0(com_cmm_u_cmm_cfgspace_low_addr_00_q[22]), + .I1(com_cmm_u_cmm_cfgspace_low_addr_02_q[22]), + .I2(com_cmm_u_cmm_cfgspace_sel_xencode[1]), + .O(com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_am[22]) + ); + defparam com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_bm_22_.INIT = 8'hCA; + LUT3 com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_bm_22_ ( + .I0(com_cmm_u_cmm_cfgspace_low_addr_01_q[22]), + .I1(com_cmm_u_cmm_cfgspace_low_addr_03_q[22]), + .I2(com_cmm_u_cmm_cfgspace_sel_xencode[1]), + .O(com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_bm[22]) + ); + MUXF5 com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_22_ ( + .I0(com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_am[22]), + .I1(com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_bm[22]), + .O(com_cmm_u_cmm_cfgspace_decoder_read_data[22]), + .S(com_cmm_u_cmm_cfgspace_sel_xencode[0]) + ); + defparam com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_am_23_.INIT = 8'hCA; + LUT3 com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_am_23_ ( + .I0(com_cmm_u_cmm_cfgspace_low_addr_00_q[23]), + .I1(com_cmm_u_cmm_cfgspace_low_addr_02_q[23]), + .I2(com_cmm_u_cmm_cfgspace_sel_xencode[1]), + .O(com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_am[23]) + ); + defparam com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_bm_23_.INIT = 8'hCA; + LUT3 com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_bm_23_ ( + .I0(com_cmm_u_cmm_cfgspace_low_addr_01_q[23]), + .I1(com_cmm_u_cmm_cfgspace_low_addr_03_q[23]), + .I2(com_cmm_u_cmm_cfgspace_sel_xencode[1]), + .O(com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_bm[23]) + ); + MUXF5 com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_23_ ( + .I0(com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_am[23]), + .I1(com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_bm[23]), + .O(com_cmm_u_cmm_cfgspace_decoder_read_data[23]), + .S(com_cmm_u_cmm_cfgspace_sel_xencode[0]) + ); + defparam com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_am_24_.INIT = 8'hCA; + LUT3 com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_am_24_ ( + .I0(com_cmm_u_cmm_cfgspace_low_addr_00_q[24]), + .I1(com_cmm_u_cmm_cfgspace_low_addr_02_q[24]), + .I2(com_cmm_u_cmm_cfgspace_sel_xencode[1]), + .O(com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_am[24]) + ); + defparam com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_bm_24_.INIT = 8'hCA; + LUT3 com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_bm_24_ ( + .I0(com_cmm_u_cmm_cfgspace_low_addr_01_q[24]), + .I1(com_cmm_u_cmm_cfgspace_low_addr_03_q[24]), + .I2(com_cmm_u_cmm_cfgspace_sel_xencode[1]), + .O(com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_bm[24]) + ); + MUXF5 com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_24_ ( + .I0(com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_am[24]), + .I1(com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_bm[24]), + .O(com_cmm_u_cmm_cfgspace_decoder_read_data[24]), + .S(com_cmm_u_cmm_cfgspace_sel_xencode[0]) + ); + defparam com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_am_25_.INIT = 8'hCA; + LUT3 com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_am_25_ ( + .I0(com_cmm_u_cmm_cfgspace_low_addr_00_q[25]), + .I1(com_cmm_u_cmm_cfgspace_low_addr_02_q[25]), + .I2(com_cmm_u_cmm_cfgspace_sel_xencode[1]), + .O(com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_am[25]) + ); + defparam com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_bm_25_.INIT = 8'hCA; + LUT3 com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_bm_25_ ( + .I0(com_cmm_u_cmm_cfgspace_low_addr_01_q[25]), + .I1(com_cmm_u_cmm_cfgspace_low_addr_03_q[25]), + .I2(com_cmm_u_cmm_cfgspace_sel_xencode[1]), + .O(com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_bm[25]) + ); + MUXF5 com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_25_ ( + .I0(com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_am[25]), + .I1(com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_bm[25]), + .O(com_cmm_u_cmm_cfgspace_decoder_read_data[25]), + .S(com_cmm_u_cmm_cfgspace_sel_xencode[0]) + ); + defparam com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_am_26_.INIT = 8'hCA; + LUT3 com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_am_26_ ( + .I0(com_cmm_u_cmm_cfgspace_low_addr_00_q[26]), + .I1(com_cmm_u_cmm_cfgspace_low_addr_02_q[26]), + .I2(com_cmm_u_cmm_cfgspace_sel_xencode[1]), + .O(com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_am[26]) + ); + defparam com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_bm_26_.INIT = 8'hCA; + LUT3 com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_bm_26_ ( + .I0(com_cmm_u_cmm_cfgspace_low_addr_01_q[26]), + .I1(com_cmm_u_cmm_cfgspace_low_addr_03_q[26]), + .I2(com_cmm_u_cmm_cfgspace_sel_xencode[1]), + .O(com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_bm[26]) + ); + MUXF5 com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_26_ ( + .I0(com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_am[26]), + .I1(com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_bm[26]), + .O(com_cmm_u_cmm_cfgspace_decoder_read_data[26]), + .S(com_cmm_u_cmm_cfgspace_sel_xencode[0]) + ); + defparam com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_am_27_.INIT = 8'hCA; + LUT3 com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_am_27_ ( + .I0(com_cmm_u_cmm_cfgspace_low_addr_00_q[27]), + .I1(com_cmm_u_cmm_cfgspace_low_addr_02_q[27]), + .I2(com_cmm_u_cmm_cfgspace_sel_xencode[1]), + .O(com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_am[27]) + ); + defparam com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_bm_27_.INIT = 8'hCA; + LUT3 com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_bm_27_ ( + .I0(com_cmm_u_cmm_cfgspace_low_addr_01_q[27]), + .I1(com_cmm_u_cmm_cfgspace_low_addr_03_q[27]), + .I2(com_cmm_u_cmm_cfgspace_sel_xencode[1]), + .O(com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_bm[27]) + ); + MUXF5 com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_27_ ( + .I0(com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_am[27]), + .I1(com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_bm[27]), + .O(com_cmm_u_cmm_cfgspace_decoder_read_data[27]), + .S(com_cmm_u_cmm_cfgspace_sel_xencode[0]) + ); + defparam com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_am_28_.INIT = 8'hCA; + LUT3 com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_am_28_ ( + .I0(com_cmm_u_cmm_cfgspace_low_addr_00_q[28]), + .I1(com_cmm_u_cmm_cfgspace_low_addr_02_q[28]), + .I2(com_cmm_u_cmm_cfgspace_sel_xencode[1]), + .O(com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_am[28]) + ); + defparam com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_bm_28_.INIT = 8'hCA; + LUT3 com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_bm_28_ ( + .I0(com_cmm_u_cmm_cfgspace_low_addr_01_q[28]), + .I1(com_cmm_u_cmm_cfgspace_low_addr_03_q[28]), + .I2(com_cmm_u_cmm_cfgspace_sel_xencode[1]), + .O(com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_bm[28]) + ); + MUXF5 com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_28_ ( + .I0(com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_am[28]), + .I1(com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_bm[28]), + .O(com_cmm_u_cmm_cfgspace_decoder_read_data[28]), + .S(com_cmm_u_cmm_cfgspace_sel_xencode[0]) + ); + defparam com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_am_29_.INIT = 8'hCA; + LUT3 com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_am_29_ ( + .I0(com_cmm_u_cmm_cfgspace_low_addr_00_q[29]), + .I1(com_cmm_u_cmm_cfgspace_low_addr_02_q[29]), + .I2(com_cmm_u_cmm_cfgspace_sel_xencode[1]), + .O(com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_am[29]) + ); + defparam com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_bm_29_.INIT = 8'hCA; + LUT3 com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_bm_29_ ( + .I0(com_cmm_u_cmm_cfgspace_low_addr_01_q[29]), + .I1(com_cmm_u_cmm_cfgspace_low_addr_03_q[29]), + .I2(com_cmm_u_cmm_cfgspace_sel_xencode[1]), + .O(com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_bm[29]) + ); + MUXF5 com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_29_ ( + .I0(com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_am[29]), + .I1(com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_bm[29]), + .O(com_cmm_u_cmm_cfgspace_decoder_read_data[29]), + .S(com_cmm_u_cmm_cfgspace_sel_xencode[0]) + ); + defparam com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_am_30_.INIT = 8'hCA; + LUT3 com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_am_30_ ( + .I0(com_cmm_u_cmm_cfgspace_low_addr_00_q[30]), + .I1(com_cmm_u_cmm_cfgspace_low_addr_02_q[30]), + .I2(com_cmm_u_cmm_cfgspace_sel_xencode[1]), + .O(com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_am[30]) + ); + defparam com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_bm_30_.INIT = 8'hCA; + LUT3 com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_bm_30_ ( + .I0(com_cmm_u_cmm_cfgspace_low_addr_01_q[30]), + .I1(com_cmm_u_cmm_cfgspace_low_addr_03_q[30]), + .I2(com_cmm_u_cmm_cfgspace_sel_xencode[1]), + .O(com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_bm[30]) + ); + MUXF5 com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_30_ ( + .I0(com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_am[30]), + .I1(com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_bm[30]), + .O(com_cmm_u_cmm_cfgspace_decoder_read_data[30]), + .S(com_cmm_u_cmm_cfgspace_sel_xencode[0]) + ); + defparam com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_am_31_.INIT = 8'hCA; + LUT3 com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_am_31_ ( + .I0(com_cmm_u_cmm_cfgspace_low_addr_00_q[31]), + .I1(com_cmm_u_cmm_cfgspace_low_addr_02_q[31]), + .I2(com_cmm_u_cmm_cfgspace_sel_xencode[1]), + .O(com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_am[31]) + ); + defparam com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_bm_31_.INIT = 8'hCA; + LUT3 com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_bm_31_ ( + .I0(com_cmm_u_cmm_cfgspace_low_addr_01_q[31]), + .I1(com_cmm_u_cmm_cfgspace_low_addr_03_q[31]), + .I2(com_cmm_u_cmm_cfgspace_sel_xencode[1]), + .O(com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_bm[31]) + ); + MUXF5 com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_31_ ( + .I0(com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_am[31]), + .I1(com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_bm[31]), + .O(com_cmm_u_cmm_cfgspace_decoder_read_data[31]), + .S(com_cmm_u_cmm_cfgspace_sel_xencode[0]) + ); + defparam com_cmm_u_cmm_cfgspace_data_scale_5_i_m2_i_m4_i_m3_0_am_0_.INIT = 8'hCA; + LUT3 com_cmm_u_cmm_cfgspace_data_scale_5_i_m2_i_m4_i_m3_0_am_0_ ( + .I0(cfg_cfg_5072[568]), + .I1(cfg_cfg_5072[632]), + .I2(com_cmm_u_cmm_cfgspace_pme_pmcsr[11]), + .O(com_cmm_u_cmm_cfgspace_data_scale_5_i_m2_i_m4_i_m3_0_am[0]) + ); + defparam com_cmm_u_cmm_cfgspace_data_scale_5_i_m2_i_m4_i_m3_0_bm_0_.INIT = 8'hCA; + LUT3 com_cmm_u_cmm_cfgspace_data_scale_5_i_m2_i_m4_i_m3_0_bm_0_ ( + .I0(cfg_cfg_5072[584]), + .I1(cfg_cfg_5072[648]), + .I2(com_cmm_u_cmm_cfgspace_pme_pmcsr[11]), + .O(com_cmm_u_cmm_cfgspace_data_scale_5_i_m2_i_m4_i_m3_0_bm[0]) + ); + MUXF5 com_cmm_u_cmm_cfgspace_data_scale_5_i_m2_i_m4_i_m3_0_0_ ( + .I0(com_cmm_u_cmm_cfgspace_data_scale_5_i_m2_i_m4_i_m3_0_am[0]), + .I1(com_cmm_u_cmm_cfgspace_data_scale_5_i_m2_i_m4_i_m3_0_bm[0]), + .O(com_cmm_u_cmm_cfgspace_N_51531), + .S(com_cmm_u_cmm_cfgspace_pme_pmcsr[9]) + ); + defparam com_cmm_u_cmm_cfgspace_data_scale_5_i_m2_i_m4_i_m3_0_am_1_.INIT = 8'hCA; + LUT3 com_cmm_u_cmm_cfgspace_data_scale_5_i_m2_i_m4_i_m3_0_am_1_ ( + .I0(cfg_cfg_5072[569]), + .I1(cfg_cfg_5072[633]), + .I2(com_cmm_u_cmm_cfgspace_pme_pmcsr[11]), + .O(com_cmm_u_cmm_cfgspace_data_scale_5_i_m2_i_m4_i_m3_0_am[1]) + ); + defparam com_cmm_u_cmm_cfgspace_data_scale_5_i_m2_i_m4_i_m3_0_bm_1_.INIT = 8'hCA; + LUT3 com_cmm_u_cmm_cfgspace_data_scale_5_i_m2_i_m4_i_m3_0_bm_1_ ( + .I0(cfg_cfg_5072[585]), + .I1(cfg_cfg_5072[649]), + .I2(com_cmm_u_cmm_cfgspace_pme_pmcsr[11]), + .O(com_cmm_u_cmm_cfgspace_data_scale_5_i_m2_i_m4_i_m3_0_bm[1]) + ); + MUXF5 com_cmm_u_cmm_cfgspace_data_scale_5_i_m2_i_m4_i_m3_0_1_ ( + .I0(com_cmm_u_cmm_cfgspace_data_scale_5_i_m2_i_m4_i_m3_0_am[1]), + .I1(com_cmm_u_cmm_cfgspace_data_scale_5_i_m2_i_m4_i_m3_0_bm[1]), + .O(com_cmm_u_cmm_cfgspace_N_51532), + .S(com_cmm_u_cmm_cfgspace_pme_pmcsr[9]) + ); + defparam com_cmm_u_cmm_cfgspace_pme_data_5_i_m2_i_m4_i_m3_0_am_0_.INIT = 8'hCA; + LUT3 com_cmm_u_cmm_cfgspace_pme_data_5_i_m2_i_m4_i_m3_0_am_0_ ( + .I0(cfg_cfg_5072[560]), + .I1(cfg_cfg_5072[624]), + .I2(com_cmm_u_cmm_cfgspace_pme_pmcsr[11]), + .O(com_cmm_u_cmm_cfgspace_pme_data_5_i_m2_i_m4_i_m3_0_am[0]) + ); + defparam com_cmm_u_cmm_cfgspace_pme_data_5_i_m2_i_m4_i_m3_0_bm_0_.INIT = 8'hCA; + LUT3 com_cmm_u_cmm_cfgspace_pme_data_5_i_m2_i_m4_i_m3_0_bm_0_ ( + .I0(cfg_cfg_5072[576]), + .I1(cfg_cfg_5072[640]), + .I2(com_cmm_u_cmm_cfgspace_pme_pmcsr[11]), + .O(com_cmm_u_cmm_cfgspace_pme_data_5_i_m2_i_m4_i_m3_0_bm[0]) + ); + MUXF5 com_cmm_u_cmm_cfgspace_pme_data_5_i_m2_i_m4_i_m3_0_0_ ( + .I0(com_cmm_u_cmm_cfgspace_pme_data_5_i_m2_i_m4_i_m3_0_am[0]), + .I1(com_cmm_u_cmm_cfgspace_pme_data_5_i_m2_i_m4_i_m3_0_bm[0]), + .O(com_cmm_u_cmm_cfgspace_N_51549), + .S(com_cmm_u_cmm_cfgspace_pme_pmcsr[9]) + ); + defparam com_cmm_u_cmm_cfgspace_pme_data_5_i_m2_i_m4_i_m3_0_am_1_.INIT = 8'hCA; + LUT3 com_cmm_u_cmm_cfgspace_pme_data_5_i_m2_i_m4_i_m3_0_am_1_ ( + .I0(cfg_cfg_5072[561]), + .I1(cfg_cfg_5072[625]), + .I2(com_cmm_u_cmm_cfgspace_pme_pmcsr[11]), + .O(com_cmm_u_cmm_cfgspace_pme_data_5_i_m2_i_m4_i_m3_0_am[1]) + ); + defparam com_cmm_u_cmm_cfgspace_pme_data_5_i_m2_i_m4_i_m3_0_bm_1_.INIT = 8'hCA; + LUT3 com_cmm_u_cmm_cfgspace_pme_data_5_i_m2_i_m4_i_m3_0_bm_1_ ( + .I0(cfg_cfg_5072[577]), + .I1(cfg_cfg_5072[641]), + .I2(com_cmm_u_cmm_cfgspace_pme_pmcsr[11]), + .O(com_cmm_u_cmm_cfgspace_pme_data_5_i_m2_i_m4_i_m3_0_bm[1]) + ); + MUXF5 com_cmm_u_cmm_cfgspace_pme_data_5_i_m2_i_m4_i_m3_0_1_ ( + .I0(com_cmm_u_cmm_cfgspace_pme_data_5_i_m2_i_m4_i_m3_0_am[1]), + .I1(com_cmm_u_cmm_cfgspace_pme_data_5_i_m2_i_m4_i_m3_0_bm[1]), + .O(com_cmm_u_cmm_cfgspace_N_51550), + .S(com_cmm_u_cmm_cfgspace_pme_pmcsr[9]) + ); + defparam com_cmm_u_cmm_cfgspace_pme_data_5_i_m2_i_m4_i_m3_0_am_2_.INIT = 8'hCA; + LUT3 com_cmm_u_cmm_cfgspace_pme_data_5_i_m2_i_m4_i_m3_0_am_2_ ( + .I0(cfg_cfg_5072[562]), + .I1(cfg_cfg_5072[626]), + .I2(com_cmm_u_cmm_cfgspace_pme_pmcsr[11]), + .O(com_cmm_u_cmm_cfgspace_pme_data_5_i_m2_i_m4_i_m3_0_am[2]) + ); + defparam com_cmm_u_cmm_cfgspace_pme_data_5_i_m2_i_m4_i_m3_0_bm_2_.INIT = 8'hCA; + LUT3 com_cmm_u_cmm_cfgspace_pme_data_5_i_m2_i_m4_i_m3_0_bm_2_ ( + .I0(cfg_cfg_5072[578]), + .I1(cfg_cfg_5072[642]), + .I2(com_cmm_u_cmm_cfgspace_pme_pmcsr[11]), + .O(com_cmm_u_cmm_cfgspace_pme_data_5_i_m2_i_m4_i_m3_0_bm[2]) + ); + MUXF5 com_cmm_u_cmm_cfgspace_pme_data_5_i_m2_i_m4_i_m3_0_2_ ( + .I0(com_cmm_u_cmm_cfgspace_pme_data_5_i_m2_i_m4_i_m3_0_am[2]), + .I1(com_cmm_u_cmm_cfgspace_pme_data_5_i_m2_i_m4_i_m3_0_bm[2]), + .O(com_cmm_u_cmm_cfgspace_N_51551), + .S(com_cmm_u_cmm_cfgspace_pme_pmcsr[9]) + ); + defparam com_cmm_u_cmm_cfgspace_pme_data_5_i_m2_i_m4_i_m3_0_am_3_.INIT = 8'hCA; + LUT3 com_cmm_u_cmm_cfgspace_pme_data_5_i_m2_i_m4_i_m3_0_am_3_ ( + .I0(cfg_cfg_5072[563]), + .I1(cfg_cfg_5072[627]), + .I2(com_cmm_u_cmm_cfgspace_pme_pmcsr[11]), + .O(com_cmm_u_cmm_cfgspace_pme_data_5_i_m2_i_m4_i_m3_0_am[3]) + ); + defparam com_cmm_u_cmm_cfgspace_pme_data_5_i_m2_i_m4_i_m3_0_bm_3_.INIT = 8'hCA; + LUT3 com_cmm_u_cmm_cfgspace_pme_data_5_i_m2_i_m4_i_m3_0_bm_3_ ( + .I0(cfg_cfg_5072[579]), + .I1(cfg_cfg_5072[643]), + .I2(com_cmm_u_cmm_cfgspace_pme_pmcsr[11]), + .O(com_cmm_u_cmm_cfgspace_pme_data_5_i_m2_i_m4_i_m3_0_bm[3]) + ); + MUXF5 com_cmm_u_cmm_cfgspace_pme_data_5_i_m2_i_m4_i_m3_0_3_ ( + .I0(com_cmm_u_cmm_cfgspace_pme_data_5_i_m2_i_m4_i_m3_0_am[3]), + .I1(com_cmm_u_cmm_cfgspace_pme_data_5_i_m2_i_m4_i_m3_0_bm[3]), + .O(com_cmm_u_cmm_cfgspace_N_51552), + .S(com_cmm_u_cmm_cfgspace_pme_pmcsr[9]) + ); + defparam com_cmm_u_cmm_cfgspace_pme_data_5_i_m2_i_m4_i_m3_0_am_4_.INIT = 8'hCA; + LUT3 com_cmm_u_cmm_cfgspace_pme_data_5_i_m2_i_m4_i_m3_0_am_4_ ( + .I0(cfg_cfg_5072[564]), + .I1(cfg_cfg_5072[628]), + .I2(com_cmm_u_cmm_cfgspace_pme_pmcsr[11]), + .O(com_cmm_u_cmm_cfgspace_pme_data_5_i_m2_i_m4_i_m3_0_am[4]) + ); + defparam com_cmm_u_cmm_cfgspace_pme_data_5_i_m2_i_m4_i_m3_0_bm_4_.INIT = 8'hCA; + LUT3 com_cmm_u_cmm_cfgspace_pme_data_5_i_m2_i_m4_i_m3_0_bm_4_ ( + .I0(cfg_cfg_5072[580]), + .I1(cfg_cfg_5072[644]), + .I2(com_cmm_u_cmm_cfgspace_pme_pmcsr[11]), + .O(com_cmm_u_cmm_cfgspace_pme_data_5_i_m2_i_m4_i_m3_0_bm[4]) + ); + MUXF5 com_cmm_u_cmm_cfgspace_pme_data_5_i_m2_i_m4_i_m3_0_4_ ( + .I0(com_cmm_u_cmm_cfgspace_pme_data_5_i_m2_i_m4_i_m3_0_am[4]), + .I1(com_cmm_u_cmm_cfgspace_pme_data_5_i_m2_i_m4_i_m3_0_bm[4]), + .O(com_cmm_u_cmm_cfgspace_N_51553), + .S(com_cmm_u_cmm_cfgspace_pme_pmcsr[9]) + ); + defparam com_cmm_u_cmm_cfgspace_pme_data_5_i_m2_i_m4_i_m3_0_am_5_.INIT = 8'hCA; + LUT3 com_cmm_u_cmm_cfgspace_pme_data_5_i_m2_i_m4_i_m3_0_am_5_ ( + .I0(cfg_cfg_5072[565]), + .I1(cfg_cfg_5072[629]), + .I2(com_cmm_u_cmm_cfgspace_pme_pmcsr[11]), + .O(com_cmm_u_cmm_cfgspace_pme_data_5_i_m2_i_m4_i_m3_0_am[5]) + ); + defparam com_cmm_u_cmm_cfgspace_pme_data_5_i_m2_i_m4_i_m3_0_bm_5_.INIT = 8'hCA; + LUT3 com_cmm_u_cmm_cfgspace_pme_data_5_i_m2_i_m4_i_m3_0_bm_5_ ( + .I0(cfg_cfg_5072[581]), + .I1(cfg_cfg_5072[645]), + .I2(com_cmm_u_cmm_cfgspace_pme_pmcsr[11]), + .O(com_cmm_u_cmm_cfgspace_pme_data_5_i_m2_i_m4_i_m3_0_bm[5]) + ); + MUXF5 com_cmm_u_cmm_cfgspace_pme_data_5_i_m2_i_m4_i_m3_0_5_ ( + .I0(com_cmm_u_cmm_cfgspace_pme_data_5_i_m2_i_m4_i_m3_0_am[5]), + .I1(com_cmm_u_cmm_cfgspace_pme_data_5_i_m2_i_m4_i_m3_0_bm[5]), + .O(com_cmm_u_cmm_cfgspace_N_51554), + .S(com_cmm_u_cmm_cfgspace_pme_pmcsr[9]) + ); + defparam com_cmm_u_cmm_cfgspace_pme_data_5_i_m2_i_m4_i_m3_0_am_6_.INIT = 8'hCA; + LUT3 com_cmm_u_cmm_cfgspace_pme_data_5_i_m2_i_m4_i_m3_0_am_6_ ( + .I0(cfg_cfg_5072[566]), + .I1(cfg_cfg_5072[630]), + .I2(com_cmm_u_cmm_cfgspace_pme_pmcsr[11]), + .O(com_cmm_u_cmm_cfgspace_pme_data_5_i_m2_i_m4_i_m3_0_am[6]) + ); + defparam com_cmm_u_cmm_cfgspace_pme_data_5_i_m2_i_m4_i_m3_0_bm_6_.INIT = 8'hCA; + LUT3 com_cmm_u_cmm_cfgspace_pme_data_5_i_m2_i_m4_i_m3_0_bm_6_ ( + .I0(cfg_cfg_5072[582]), + .I1(cfg_cfg_5072[646]), + .I2(com_cmm_u_cmm_cfgspace_pme_pmcsr[11]), + .O(com_cmm_u_cmm_cfgspace_pme_data_5_i_m2_i_m4_i_m3_0_bm[6]) + ); + MUXF5 com_cmm_u_cmm_cfgspace_pme_data_5_i_m2_i_m4_i_m3_0_6_ ( + .I0(com_cmm_u_cmm_cfgspace_pme_data_5_i_m2_i_m4_i_m3_0_am[6]), + .I1(com_cmm_u_cmm_cfgspace_pme_data_5_i_m2_i_m4_i_m3_0_bm[6]), + .O(com_cmm_u_cmm_cfgspace_N_51555), + .S(com_cmm_u_cmm_cfgspace_pme_pmcsr[9]) + ); + defparam com_cmm_u_cmm_cfgspace_pme_data_5_i_m2_i_m4_i_m3_0_am_7_.INIT = 8'hCA; + LUT3 com_cmm_u_cmm_cfgspace_pme_data_5_i_m2_i_m4_i_m3_0_am_7_ ( + .I0(cfg_cfg_5072[567]), + .I1(cfg_cfg_5072[631]), + .I2(com_cmm_u_cmm_cfgspace_pme_pmcsr[11]), + .O(com_cmm_u_cmm_cfgspace_pme_data_5_i_m2_i_m4_i_m3_0_am[7]) + ); + defparam com_cmm_u_cmm_cfgspace_pme_data_5_i_m2_i_m4_i_m3_0_bm_7_.INIT = 8'hCA; + LUT3 com_cmm_u_cmm_cfgspace_pme_data_5_i_m2_i_m4_i_m3_0_bm_7_ ( + .I0(cfg_cfg_5072[583]), + .I1(cfg_cfg_5072[647]), + .I2(com_cmm_u_cmm_cfgspace_pme_pmcsr[11]), + .O(com_cmm_u_cmm_cfgspace_pme_data_5_i_m2_i_m4_i_m3_0_bm[7]) + ); + MUXF5 com_cmm_u_cmm_cfgspace_pme_data_5_i_m2_i_m4_i_m3_0_7_ ( + .I0(com_cmm_u_cmm_cfgspace_pme_data_5_i_m2_i_m4_i_m3_0_am[7]), + .I1(com_cmm_u_cmm_cfgspace_pme_data_5_i_m2_i_m4_i_m3_0_bm[7]), + .O(com_cmm_u_cmm_cfgspace_N_51556), + .S(com_cmm_u_cmm_cfgspace_pme_pmcsr[9]) + ); + defparam com_cmm_u_cmm_cfgspace_data_scale_4_i_m2_i_m4_i_m3_0_am_0_.INIT = 8'hCA; + LUT3 com_cmm_u_cmm_cfgspace_data_scale_4_i_m2_i_m4_i_m3_0_am_0_ ( + .I0(cfg_cfg_5072[536]), + .I1(cfg_cfg_5072[552]), + .I2(com_cmm_u_cmm_cfgspace_pme_pmcsr[9]), + .O(com_cmm_u_cmm_cfgspace_data_scale_4_i_m2_i_m4_i_m3_0_am[0]) + ); + defparam com_cmm_u_cmm_cfgspace_data_scale_4_i_m2_i_m4_i_m3_0_bm_0_.INIT = 8'hCA; + LUT3 com_cmm_u_cmm_cfgspace_data_scale_4_i_m2_i_m4_i_m3_0_bm_0_ ( + .I0(cfg_cfg_5072[600]), + .I1(cfg_cfg_5072[616]), + .I2(com_cmm_u_cmm_cfgspace_pme_pmcsr[9]), + .O(com_cmm_u_cmm_cfgspace_data_scale_4_i_m2_i_m4_i_m3_0_bm[0]) + ); + MUXF5 com_cmm_u_cmm_cfgspace_data_scale_4_i_m2_i_m4_i_m3_0_0_ ( + .I0(com_cmm_u_cmm_cfgspace_data_scale_4_i_m2_i_m4_i_m3_0_am[0]), + .I1(com_cmm_u_cmm_cfgspace_data_scale_4_i_m2_i_m4_i_m3_0_bm[0]), + .O(com_cmm_u_cmm_cfgspace_N_51561), + .S(com_cmm_u_cmm_cfgspace_pme_pmcsr[11]) + ); + defparam com_cmm_u_cmm_cfgspace_data_scale_4_i_m2_i_m4_i_m3_0_am_1_.INIT = 8'hCA; + LUT3 com_cmm_u_cmm_cfgspace_data_scale_4_i_m2_i_m4_i_m3_0_am_1_ ( + .I0(cfg_cfg_5072[537]), + .I1(cfg_cfg_5072[553]), + .I2(com_cmm_u_cmm_cfgspace_pme_pmcsr[9]), + .O(com_cmm_u_cmm_cfgspace_data_scale_4_i_m2_i_m4_i_m3_0_am[1]) + ); + defparam com_cmm_u_cmm_cfgspace_data_scale_4_i_m2_i_m4_i_m3_0_bm_1_.INIT = 8'hCA; + LUT3 com_cmm_u_cmm_cfgspace_data_scale_4_i_m2_i_m4_i_m3_0_bm_1_ ( + .I0(cfg_cfg_5072[601]), + .I1(cfg_cfg_5072[617]), + .I2(com_cmm_u_cmm_cfgspace_pme_pmcsr[9]), + .O(com_cmm_u_cmm_cfgspace_data_scale_4_i_m2_i_m4_i_m3_0_bm[1]) + ); + MUXF5 com_cmm_u_cmm_cfgspace_data_scale_4_i_m2_i_m4_i_m3_0_1_ ( + .I0(com_cmm_u_cmm_cfgspace_data_scale_4_i_m2_i_m4_i_m3_0_am[1]), + .I1(com_cmm_u_cmm_cfgspace_data_scale_4_i_m2_i_m4_i_m3_0_bm[1]), + .O(com_cmm_u_cmm_cfgspace_N_51562), + .S(com_cmm_u_cmm_cfgspace_pme_pmcsr[11]) + ); + defparam com_cmm_u_cmm_cfgspace_pme_data_4_i_m2_i_m4_i_m3_0_am_0_.INIT = 8'hCA; + LUT3 com_cmm_u_cmm_cfgspace_pme_data_4_i_m2_i_m4_i_m3_0_am_0_ ( + .I0(cfg_cfg_5072[528]), + .I1(cfg_cfg_5072[544]), + .I2(com_cmm_u_cmm_cfgspace_pme_pmcsr[9]), + .O(com_cmm_u_cmm_cfgspace_pme_data_4_i_m2_i_m4_i_m3_0_am[0]) + ); + defparam com_cmm_u_cmm_cfgspace_pme_data_4_i_m2_i_m4_i_m3_0_bm_0_.INIT = 8'hCA; + LUT3 com_cmm_u_cmm_cfgspace_pme_data_4_i_m2_i_m4_i_m3_0_bm_0_ ( + .I0(cfg_cfg_5072[592]), + .I1(cfg_cfg_5072[608]), + .I2(com_cmm_u_cmm_cfgspace_pme_pmcsr[9]), + .O(com_cmm_u_cmm_cfgspace_pme_data_4_i_m2_i_m4_i_m3_0_bm[0]) + ); + MUXF5 com_cmm_u_cmm_cfgspace_pme_data_4_i_m2_i_m4_i_m3_0_0_ ( + .I0(com_cmm_u_cmm_cfgspace_pme_data_4_i_m2_i_m4_i_m3_0_am[0]), + .I1(com_cmm_u_cmm_cfgspace_pme_data_4_i_m2_i_m4_i_m3_0_bm[0]), + .O(com_cmm_u_cmm_cfgspace_N_51579), + .S(com_cmm_u_cmm_cfgspace_pme_pmcsr[11]) + ); + defparam com_cmm_u_cmm_cfgspace_pme_data_4_i_m2_i_m4_i_m3_0_am_1_.INIT = 8'hCA; + LUT3 com_cmm_u_cmm_cfgspace_pme_data_4_i_m2_i_m4_i_m3_0_am_1_ ( + .I0(cfg_cfg_5072[529]), + .I1(cfg_cfg_5072[545]), + .I2(com_cmm_u_cmm_cfgspace_pme_pmcsr[9]), + .O(com_cmm_u_cmm_cfgspace_pme_data_4_i_m2_i_m4_i_m3_0_am[1]) + ); + defparam com_cmm_u_cmm_cfgspace_pme_data_4_i_m2_i_m4_i_m3_0_bm_1_.INIT = 8'hCA; + LUT3 com_cmm_u_cmm_cfgspace_pme_data_4_i_m2_i_m4_i_m3_0_bm_1_ ( + .I0(cfg_cfg_5072[593]), + .I1(cfg_cfg_5072[609]), + .I2(com_cmm_u_cmm_cfgspace_pme_pmcsr[9]), + .O(com_cmm_u_cmm_cfgspace_pme_data_4_i_m2_i_m4_i_m3_0_bm[1]) + ); + MUXF5 com_cmm_u_cmm_cfgspace_pme_data_4_i_m2_i_m4_i_m3_0_1_ ( + .I0(com_cmm_u_cmm_cfgspace_pme_data_4_i_m2_i_m4_i_m3_0_am[1]), + .I1(com_cmm_u_cmm_cfgspace_pme_data_4_i_m2_i_m4_i_m3_0_bm[1]), + .O(com_cmm_u_cmm_cfgspace_N_51580), + .S(com_cmm_u_cmm_cfgspace_pme_pmcsr[11]) + ); + defparam com_cmm_u_cmm_cfgspace_pme_data_4_i_m2_i_m4_i_m3_0_am_2_.INIT = 8'hCA; + LUT3 com_cmm_u_cmm_cfgspace_pme_data_4_i_m2_i_m4_i_m3_0_am_2_ ( + .I0(cfg_cfg_5072[530]), + .I1(cfg_cfg_5072[546]), + .I2(com_cmm_u_cmm_cfgspace_pme_pmcsr[9]), + .O(com_cmm_u_cmm_cfgspace_pme_data_4_i_m2_i_m4_i_m3_0_am[2]) + ); + defparam com_cmm_u_cmm_cfgspace_pme_data_4_i_m2_i_m4_i_m3_0_bm_2_.INIT = 8'hCA; + LUT3 com_cmm_u_cmm_cfgspace_pme_data_4_i_m2_i_m4_i_m3_0_bm_2_ ( + .I0(cfg_cfg_5072[594]), + .I1(cfg_cfg_5072[610]), + .I2(com_cmm_u_cmm_cfgspace_pme_pmcsr[9]), + .O(com_cmm_u_cmm_cfgspace_pme_data_4_i_m2_i_m4_i_m3_0_bm[2]) + ); + MUXF5 com_cmm_u_cmm_cfgspace_pme_data_4_i_m2_i_m4_i_m3_0_2_ ( + .I0(com_cmm_u_cmm_cfgspace_pme_data_4_i_m2_i_m4_i_m3_0_am[2]), + .I1(com_cmm_u_cmm_cfgspace_pme_data_4_i_m2_i_m4_i_m3_0_bm[2]), + .O(com_cmm_u_cmm_cfgspace_N_51581), + .S(com_cmm_u_cmm_cfgspace_pme_pmcsr[11]) + ); + defparam com_cmm_u_cmm_cfgspace_pme_data_4_i_m2_i_m4_i_m3_0_am_3_.INIT = 8'hCA; + LUT3 com_cmm_u_cmm_cfgspace_pme_data_4_i_m2_i_m4_i_m3_0_am_3_ ( + .I0(cfg_cfg_5072[531]), + .I1(cfg_cfg_5072[547]), + .I2(com_cmm_u_cmm_cfgspace_pme_pmcsr[9]), + .O(com_cmm_u_cmm_cfgspace_pme_data_4_i_m2_i_m4_i_m3_0_am[3]) + ); + defparam com_cmm_u_cmm_cfgspace_pme_data_4_i_m2_i_m4_i_m3_0_bm_3_.INIT = 8'hCA; + LUT3 com_cmm_u_cmm_cfgspace_pme_data_4_i_m2_i_m4_i_m3_0_bm_3_ ( + .I0(cfg_cfg_5072[595]), + .I1(cfg_cfg_5072[611]), + .I2(com_cmm_u_cmm_cfgspace_pme_pmcsr[9]), + .O(com_cmm_u_cmm_cfgspace_pme_data_4_i_m2_i_m4_i_m3_0_bm[3]) + ); + MUXF5 com_cmm_u_cmm_cfgspace_pme_data_4_i_m2_i_m4_i_m3_0_3_ ( + .I0(com_cmm_u_cmm_cfgspace_pme_data_4_i_m2_i_m4_i_m3_0_am[3]), + .I1(com_cmm_u_cmm_cfgspace_pme_data_4_i_m2_i_m4_i_m3_0_bm[3]), + .O(com_cmm_u_cmm_cfgspace_N_51582), + .S(com_cmm_u_cmm_cfgspace_pme_pmcsr[11]) + ); + defparam com_cmm_u_cmm_cfgspace_pme_data_4_i_m2_i_m4_i_m3_0_am_4_.INIT = 8'hCA; + LUT3 com_cmm_u_cmm_cfgspace_pme_data_4_i_m2_i_m4_i_m3_0_am_4_ ( + .I0(cfg_cfg_5072[532]), + .I1(cfg_cfg_5072[548]), + .I2(com_cmm_u_cmm_cfgspace_pme_pmcsr[9]), + .O(com_cmm_u_cmm_cfgspace_pme_data_4_i_m2_i_m4_i_m3_0_am[4]) + ); + defparam com_cmm_u_cmm_cfgspace_pme_data_4_i_m2_i_m4_i_m3_0_bm_4_.INIT = 8'hCA; + LUT3 com_cmm_u_cmm_cfgspace_pme_data_4_i_m2_i_m4_i_m3_0_bm_4_ ( + .I0(cfg_cfg_5072[596]), + .I1(cfg_cfg_5072[612]), + .I2(com_cmm_u_cmm_cfgspace_pme_pmcsr[9]), + .O(com_cmm_u_cmm_cfgspace_pme_data_4_i_m2_i_m4_i_m3_0_bm[4]) + ); + MUXF5 com_cmm_u_cmm_cfgspace_pme_data_4_i_m2_i_m4_i_m3_0_4_ ( + .I0(com_cmm_u_cmm_cfgspace_pme_data_4_i_m2_i_m4_i_m3_0_am[4]), + .I1(com_cmm_u_cmm_cfgspace_pme_data_4_i_m2_i_m4_i_m3_0_bm[4]), + .O(com_cmm_u_cmm_cfgspace_N_51583), + .S(com_cmm_u_cmm_cfgspace_pme_pmcsr[11]) + ); + defparam com_cmm_u_cmm_cfgspace_pme_data_4_i_m2_i_m4_i_m3_0_am_5_.INIT = 8'hCA; + LUT3 com_cmm_u_cmm_cfgspace_pme_data_4_i_m2_i_m4_i_m3_0_am_5_ ( + .I0(cfg_cfg_5072[533]), + .I1(cfg_cfg_5072[549]), + .I2(com_cmm_u_cmm_cfgspace_pme_pmcsr[9]), + .O(com_cmm_u_cmm_cfgspace_pme_data_4_i_m2_i_m4_i_m3_0_am[5]) + ); + defparam com_cmm_u_cmm_cfgspace_pme_data_4_i_m2_i_m4_i_m3_0_bm_5_.INIT = 8'hCA; + LUT3 com_cmm_u_cmm_cfgspace_pme_data_4_i_m2_i_m4_i_m3_0_bm_5_ ( + .I0(cfg_cfg_5072[597]), + .I1(cfg_cfg_5072[613]), + .I2(com_cmm_u_cmm_cfgspace_pme_pmcsr[9]), + .O(com_cmm_u_cmm_cfgspace_pme_data_4_i_m2_i_m4_i_m3_0_bm[5]) + ); + MUXF5 com_cmm_u_cmm_cfgspace_pme_data_4_i_m2_i_m4_i_m3_0_5_ ( + .I0(com_cmm_u_cmm_cfgspace_pme_data_4_i_m2_i_m4_i_m3_0_am[5]), + .I1(com_cmm_u_cmm_cfgspace_pme_data_4_i_m2_i_m4_i_m3_0_bm[5]), + .O(com_cmm_u_cmm_cfgspace_N_51584), + .S(com_cmm_u_cmm_cfgspace_pme_pmcsr[11]) + ); + defparam com_cmm_u_cmm_cfgspace_pme_data_4_i_m2_i_m4_i_m3_0_am_6_.INIT = 8'hCA; + LUT3 com_cmm_u_cmm_cfgspace_pme_data_4_i_m2_i_m4_i_m3_0_am_6_ ( + .I0(cfg_cfg_5072[534]), + .I1(cfg_cfg_5072[550]), + .I2(com_cmm_u_cmm_cfgspace_pme_pmcsr[9]), + .O(com_cmm_u_cmm_cfgspace_pme_data_4_i_m2_i_m4_i_m3_0_am[6]) + ); + defparam com_cmm_u_cmm_cfgspace_pme_data_4_i_m2_i_m4_i_m3_0_bm_6_.INIT = 8'hCA; + LUT3 com_cmm_u_cmm_cfgspace_pme_data_4_i_m2_i_m4_i_m3_0_bm_6_ ( + .I0(cfg_cfg_5072[598]), + .I1(cfg_cfg_5072[614]), + .I2(com_cmm_u_cmm_cfgspace_pme_pmcsr[9]), + .O(com_cmm_u_cmm_cfgspace_pme_data_4_i_m2_i_m4_i_m3_0_bm[6]) + ); + MUXF5 com_cmm_u_cmm_cfgspace_pme_data_4_i_m2_i_m4_i_m3_0_6_ ( + .I0(com_cmm_u_cmm_cfgspace_pme_data_4_i_m2_i_m4_i_m3_0_am[6]), + .I1(com_cmm_u_cmm_cfgspace_pme_data_4_i_m2_i_m4_i_m3_0_bm[6]), + .O(com_cmm_u_cmm_cfgspace_N_51585), + .S(com_cmm_u_cmm_cfgspace_pme_pmcsr[11]) + ); + defparam com_cmm_u_cmm_cfgspace_pme_data_4_i_m2_i_m4_i_m3_0_am_7_.INIT = 8'hCA; + LUT3 com_cmm_u_cmm_cfgspace_pme_data_4_i_m2_i_m4_i_m3_0_am_7_ ( + .I0(cfg_cfg_5072[535]), + .I1(cfg_cfg_5072[551]), + .I2(com_cmm_u_cmm_cfgspace_pme_pmcsr[9]), + .O(com_cmm_u_cmm_cfgspace_pme_data_4_i_m2_i_m4_i_m3_0_am[7]) + ); + defparam com_cmm_u_cmm_cfgspace_pme_data_4_i_m2_i_m4_i_m3_0_bm_7_.INIT = 8'hCA; + LUT3 com_cmm_u_cmm_cfgspace_pme_data_4_i_m2_i_m4_i_m3_0_bm_7_ ( + .I0(cfg_cfg_5072[599]), + .I1(cfg_cfg_5072[615]), + .I2(com_cmm_u_cmm_cfgspace_pme_pmcsr[9]), + .O(com_cmm_u_cmm_cfgspace_pme_data_4_i_m2_i_m4_i_m3_0_bm[7]) + ); + MUXF5 com_cmm_u_cmm_cfgspace_pme_data_4_i_m2_i_m4_i_m3_0_7_ ( + .I0(com_cmm_u_cmm_cfgspace_pme_data_4_i_m2_i_m4_i_m3_0_am[7]), + .I1(com_cmm_u_cmm_cfgspace_pme_data_4_i_m2_i_m4_i_m3_0_bm[7]), + .O(com_cmm_u_cmm_cfgspace_N_51586), + .S(com_cmm_u_cmm_cfgspace_pme_pmcsr[11]) + ); + defparam com_cmm_u_cmm_cfgspace_sel_encodex_en_3_i_0_a2_2_1.INIT = 16'h0100; + LUT4 com_cmm_u_cmm_cfgspace_sel_encodex_en_3_i_0_a2_2_1 ( + .I0(com_cmm_u_cmm_cfgspace_N_48842_i), + .I1(cfg_dwaddr_5069[8]), + .I2(cfg_dwaddr_5069[9]), + .I3(com_cmm_u_cmm_cfgspace_sel_encodex_en_3_i_0_a2_2_1_0_4526), + .O(com_cmm_u_cmm_cfgspace_N_42634_1) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_00_i_0_0_0_32087.INIT = 16'h5551; + LUT4_L com_cmm_u_cmm_cfgspace_low_addr_00_i_0_0_0_32087 ( + .I0(com_cmm_u_cmm_cfgspace_N_42543), + .I1(com_cmm_u_cmm_cfgspace_N_50495), + .I2(cfg_cfg_5072[0]), + .I3(com_cmm_u_cmm_cfgspace_sel_encodex[2]), + .LO(com_cmm_u_cmm_cfgspace_low_addr_00_i_0_0_0_32087_4788) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_00_i_0_0_31_32089.INIT = 16'hCAFF; + LUT4 com_cmm_u_cmm_cfgspace_low_addr_00_i_0_0_31_32089 ( + .I0(cfg_cfg_5072[527]), + .I1(com_cmm_msi_haddr[31]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex[0]), + .I3(com_cmm_u_cmm_cfgspace_sel_encodex[2]), + .O(com_cmm_u_cmm_cfgspace_low_addr_00_i_0_0_31_32089_4634) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_00_i_30_32094.INIT = 16'hCAFF; + LUT4 com_cmm_u_cmm_cfgspace_low_addr_00_i_30_32094 ( + .I0(cfg_cfg_5072[526]), + .I1(com_cmm_msi_haddr[30]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex[0]), + .I3(com_cmm_u_cmm_cfgspace_sel_encodex[2]), + .O(com_cmm_u_cmm_cfgspace_low_addr_00_i_30_32094_4636) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_00_i_28_32099.INIT = 16'hCAFF; + LUT4 com_cmm_u_cmm_cfgspace_low_addr_00_i_28_32099 ( + .I0(cfg_cfg_5072[524]), + .I1(com_cmm_msi_haddr[28]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex[0]), + .I3(com_cmm_u_cmm_cfgspace_sel_encodex[2]), + .O(com_cmm_u_cmm_cfgspace_low_addr_00_i_28_32099_4638) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_00_i_26_32104.INIT = 16'hCAFF; + LUT4 com_cmm_u_cmm_cfgspace_low_addr_00_i_26_32104 ( + .I0(cfg_cfg_5072[522]), + .I1(com_cmm_msi_haddr[26]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex[0]), + .I3(com_cmm_u_cmm_cfgspace_sel_encodex[2]), + .O(com_cmm_u_cmm_cfgspace_low_addr_00_i_26_32104_4640) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_00_i_25_32109.INIT = 16'hCAFF; + LUT4 com_cmm_u_cmm_cfgspace_low_addr_00_i_25_32109 ( + .I0(cfg_cfg_5072[521]), + .I1(com_cmm_msi_haddr[25]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex[0]), + .I3(com_cmm_u_cmm_cfgspace_sel_encodex[2]), + .O(com_cmm_u_cmm_cfgspace_low_addr_00_i_25_32109_4642) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_00_i_24_32114.INIT = 16'hCAFF; + LUT4 com_cmm_u_cmm_cfgspace_low_addr_00_i_24_32114 ( + .I0(cfg_cfg_5072[520]), + .I1(com_cmm_msi_haddr[24]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex[0]), + .I3(com_cmm_u_cmm_cfgspace_sel_encodex[2]), + .O(com_cmm_u_cmm_cfgspace_low_addr_00_i_24_32114_4644) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_00_i_23_32119.INIT = 16'hCAFF; + LUT4 com_cmm_u_cmm_cfgspace_low_addr_00_i_23_32119 ( + .I0(cfg_cfg_5072[519]), + .I1(com_cmm_msi_haddr[23]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex[0]), + .I3(com_cmm_u_cmm_cfgspace_sel_encodex[2]), + .O(com_cmm_u_cmm_cfgspace_low_addr_00_i_23_32119_4646) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_00_i_22_32124.INIT = 16'hCAFF; + LUT4 com_cmm_u_cmm_cfgspace_low_addr_00_i_22_32124 ( + .I0(cfg_cfg_5072[518]), + .I1(com_cmm_msi_haddr[22]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex[0]), + .I3(com_cmm_u_cmm_cfgspace_sel_encodex[2]), + .O(com_cmm_u_cmm_cfgspace_low_addr_00_i_22_32124_4648) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_00_i_20_32129.INIT = 16'hCAFF; + LUT4 com_cmm_u_cmm_cfgspace_low_addr_00_i_20_32129 ( + .I0(cfg_cfg_5072[516]), + .I1(com_cmm_msi_haddr[20]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex[0]), + .I3(com_cmm_u_cmm_cfgspace_sel_encodex[2]), + .O(com_cmm_u_cmm_cfgspace_low_addr_00_i_20_32129_4650) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_00_0_0_i_15_32134.INIT = 16'hEF2F; + LUT4 com_cmm_u_cmm_cfgspace_low_addr_00_0_0_i_15_32134 ( + .I0(com_cmm_bar4_reg[15]), + .I1(com_cmm_u_cmm_cfgspace_sel_encodex[0]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex_1[1]), + .I3(com_cmm_xrom_reg_15_), + .O(com_cmm_u_cmm_cfgspace_low_addr_00_0_0_i_15_32134_4702) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_00_i_0_0_1_.INIT = 16'h1151; + LUT4_L com_cmm_u_cmm_cfgspace_low_addr_00_i_0_0_1_ ( + .I0(com_cmm_u_cmm_cfgspace_N_50135), + .I1(com_cmm_u_cmm_cfgspace_N_50489), + .I2(com_cmm_bar0_reg_1_), + .I3(com_cmm_u_cmm_cfgspace_sel_encodex_1[1]), + .LO(com_cmm_u_cmm_cfgspace_low_addr_00_i_0_0[1]) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_00_i_0_1_1_.INIT = 16'hF351; + LUT4 com_cmm_u_cmm_cfgspace_low_addr_00_i_0_1_1_ ( + .I0(com_cmm_u_cmm_cfgspace_N_50137_1), + .I1(com_cmm_u_cmm_cfgspace_N_50453), + .I2(NlwRenamedSig_OI_cfg_dcommand[1]), + .I3(com_cmm_bar4_reg[1]), + .O(com_cmm_u_cmm_cfgspace_low_addr_00_i_0_1_1__4734) + ); + defparam com_cmm_u_cmm_cfgspace_sel_encodex_en_3_i_0_a2_4_2.INIT = 16'h0002; + LUT4 com_cmm_u_cmm_cfgspace_sel_encodex_en_3_i_0_a2_4_2 ( + .I0(com_cmm_u_cmm_cfgspace_N_42636_1), + .I1(com_cmm_cfg_addr[2]), + .I2(com_cmm_cfg_addr[3]), + .I3(com_cmm_cfg_addr[4]), + .O(com_cmm_u_cmm_cfgspace_sel_encodex_en_3_i_0_a2_4_2_4652) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_00_i_0_1_27_.INIT = 16'hEF2F; + LUT4 com_cmm_u_cmm_cfgspace_low_addr_00_i_0_1_27_ ( + .I0(com_cmm_bar4_reg[27]), + .I1(com_cmm_u_cmm_cfgspace_sel_encodex[0]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex_1[1]), + .I3(com_cmm_xrom_reg_27_), + .O(com_cmm_u_cmm_cfgspace_low_addr_00_i_0_1_27__4677) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_00_0_0_0_0_0_14_.INIT = 16'h153F; + LUT4_L com_cmm_u_cmm_cfgspace_low_addr_00_0_0_0_0_0_14_ ( + .I0(com_cmm_u_cmm_cfgspace_N_50187_1), + .I1(com_cmm_u_cmm_cfgspace_N_50453), + .I2(NlwRenamedSig_OI_cfg_dcommand[14]), + .I3(com_cmm_msi_haddr[14]), + .LO(com_cmm_u_cmm_cfgspace_low_addr_00_0_0_0_0_0[14]) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_00_i_0_i_0_0_11_.INIT = 16'h153F; + LUT4_L com_cmm_u_cmm_cfgspace_low_addr_00_i_0_i_0_0_11_ ( + .I0(com_cmm_u_cmm_cfgspace_N_50187_1), + .I1(com_cmm_u_cmm_cfgspace_N_50453), + .I2(NlwRenamedSig_OI_cfg_dcommand[11]), + .I3(com_cmm_msi_haddr[11]), + .LO(com_cmm_u_cmm_cfgspace_low_addr_00_i_0_i_0_0[11]) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_02_3_0_am_11_.INIT = 8'hCA; + LUT3 com_cmm_u_cmm_cfgspace_low_addr_02_3_0_am_11_ ( + .I0(cfg_cfg_5072[43]), + .I1(cfg_cfg_5072[267]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex_1[1]), + .O(com_cmm_u_cmm_cfgspace_low_addr_02_3_0_am_11__4528) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_02_3_0_bm_11_.INIT = 8'h0D; + LUT3 com_cmm_u_cmm_cfgspace_low_addr_02_3_0_bm_11_ ( + .I0(cfg_cfg_5072[482]), + .I1(cfg_cfg_5072[486]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex_1[1]), + .O(com_cmm_u_cmm_cfgspace_low_addr_02_3_0_bm_11__4527) + ); + MUXF5 com_cmm_u_cmm_cfgspace_low_addr_02_3_0_11_ ( + .I0(com_cmm_u_cmm_cfgspace_low_addr_02_3_0_am_11__4528), + .I1(com_cmm_u_cmm_cfgspace_low_addr_02_3_0_bm_11__4527), + .O(com_cmm_u_cmm_cfgspace_N_4281), + .S(com_cmm_u_cmm_cfgspace_sel_encodex_2[2]) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_02_3_0_am_12_.INIT = 8'hCA; + LUT3 com_cmm_u_cmm_cfgspace_low_addr_02_3_0_am_12_ ( + .I0(cfg_cfg_5072[44]), + .I1(cfg_cfg_5072[268]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex_1[1]), + .O(com_cmm_u_cmm_cfgspace_low_addr_02_3_0_am_12__4530) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_02_3_0_bm_12_.INIT = 8'h0D; + LUT3 com_cmm_u_cmm_cfgspace_low_addr_02_3_0_bm_12_ ( + .I0(cfg_cfg_5072[482]), + .I1(cfg_cfg_5072[487]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex_1[1]), + .O(com_cmm_u_cmm_cfgspace_low_addr_02_3_0_bm_12__4529) + ); + MUXF5 com_cmm_u_cmm_cfgspace_low_addr_02_3_0_12_ ( + .I0(com_cmm_u_cmm_cfgspace_low_addr_02_3_0_am_12__4530), + .I1(com_cmm_u_cmm_cfgspace_low_addr_02_3_0_bm_12__4529), + .O(com_cmm_u_cmm_cfgspace_N_4282), + .S(com_cmm_u_cmm_cfgspace_sel_encodex_2[2]) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_02_3_0_am_14_.INIT = 8'hCA; + LUT3 com_cmm_u_cmm_cfgspace_low_addr_02_3_0_am_14_ ( + .I0(cfg_cfg_5072[46]), + .I1(cfg_cfg_5072[270]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex_1[1]), + .O(com_cmm_u_cmm_cfgspace_low_addr_02_3_0_am_14__4532) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_02_3_0_bm_14_.INIT = 8'h0D; + LUT3 com_cmm_u_cmm_cfgspace_low_addr_02_3_0_bm_14_ ( + .I0(cfg_cfg_5072[482]), + .I1(cfg_cfg_5072[489]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex_1[1]), + .O(com_cmm_u_cmm_cfgspace_low_addr_02_3_0_bm_14__4531) + ); + MUXF5 com_cmm_u_cmm_cfgspace_low_addr_02_3_0_14_ ( + .I0(com_cmm_u_cmm_cfgspace_low_addr_02_3_0_am_14__4532), + .I1(com_cmm_u_cmm_cfgspace_low_addr_02_3_0_bm_14__4531), + .O(com_cmm_u_cmm_cfgspace_N_4284), + .S(com_cmm_u_cmm_cfgspace_sel_encodex_2[2]) + ); + defparam com_cmm_u_cmm_cfgspace_x3gio_decodepipe_l_sel_x0_3_i_0_0_m3_1.INIT = 8'hE4; + LUT3 com_cmm_u_cmm_cfgspace_x3gio_decodepipe_l_sel_x0_3_i_0_0_m3_1 ( + .I0(com_cmm_u_cmm_cfgspace_N_48842_i), + .I1(cfg_dwaddr_5069[1]), + .I2(com_cmm_cfg_addr[1]), + .O(com_cmm_u_cmm_cfgspace_N_48849) + ); + defparam com_cmm_u_cmm_cfgspace_x3gio_msidata_msi_data12_0_a2_0_a2.INIT = 8'h80; + LUT3 com_cmm_u_cmm_cfgspace_x3gio_msidata_msi_data12_0_a2_0_a2 ( + .I0(com_cmm_u_cmm_cfgspace_N_48848_i), + .I1(com_cmm_u_cmm_cfgspace_sel_5x_4754), + .I2(com_cmm_u_cmm_cfgspace_sel_x4_4772), + .O(com_cmm_u_cmm_cfgspace_msi_data12) + ); + defparam com_cmm_u_cmm_cfgspace_x3gio_msihaddr_msi_haddr12_0_a2_0_a2_0_a2.INIT = 8'h80; + LUT3 com_cmm_u_cmm_cfgspace_x3gio_msihaddr_msi_haddr12_0_a2_0_a2_0_a2 ( + .I0(com_cmm_u_cmm_cfgspace_N_48848_i), + .I1(com_cmm_u_cmm_cfgspace_sel_5x_4754), + .I2(com_cmm_u_cmm_cfgspace_sel_x0_4760), + .O(com_cmm_u_cmm_cfgspace_msi_haddr12) + ); + defparam com_cmm_u_cmm_cfgspace_x3gio_msihaddr_msi_haddr46_0_a2_0_a2_0_a2.INIT = 8'h80; + LUT3 com_cmm_u_cmm_cfgspace_x3gio_msihaddr_msi_haddr46_0_a2_0_a2_0_a2 ( + .I0(com_cmm_u_cmm_cfgspace_N_48848_i), + .I1(com_cmm_u_cmm_cfgspace_sel_5x_4754), + .I2(com_cmm_u_cmm_cfgspace_sel_x3_4773), + .O(com_cmm_u_cmm_cfgspace_msi_haddr46) + ); + defparam com_cmm_u_cmm_cfgspace_x3gio_msihaddr_msi_haddr35_0_a2_0_a2_0_a2.INIT = 8'h80; + LUT3 com_cmm_u_cmm_cfgspace_x3gio_msihaddr_msi_haddr35_0_a2_0_a2_0_a2 ( + .I0(com_cmm_u_cmm_cfgspace_N_48848_i), + .I1(com_cmm_u_cmm_cfgspace_sel_5x_4754), + .I2(com_cmm_u_cmm_cfgspace_sel_x2_4774), + .O(com_cmm_u_cmm_cfgspace_msi_haddr35) + ); + defparam com_cmm_u_cmm_cfgspace_x3gio_msidata_msi_data22_0_a2_0_a2_0_a2.INIT = 8'h80; + LUT3 com_cmm_u_cmm_cfgspace_x3gio_msidata_msi_data22_0_a2_0_a2_0_a2 ( + .I0(com_cmm_u_cmm_cfgspace_N_48848_i), + .I1(com_cmm_u_cmm_cfgspace_sel_5x_4754), + .I2(com_cmm_u_cmm_cfgspace_sel_x5_4771), + .O(com_cmm_u_cmm_cfgspace_msi_data22) + ); + defparam com_cmm_u_cmm_cfgspace_x3gio_msihaddr_msi_haddr23_0_a2_0_a2.INIT = 8'h80; + LUT3 com_cmm_u_cmm_cfgspace_x3gio_msihaddr_msi_haddr23_0_a2_0_a2 ( + .I0(com_cmm_u_cmm_cfgspace_N_48848_i), + .I1(com_cmm_u_cmm_cfgspace_sel_5x_4754), + .I2(com_cmm_u_cmm_cfgspace_sel_x1_4775), + .O(com_cmm_u_cmm_cfgspace_msi_haddr23) + ); + defparam com_cmm_u_cmm_cfgspace_x3gio_xrom_xrom_reg_9_0_0_0_o3_12_.INIT = 8'h80; + LUT3 com_cmm_u_cmm_cfgspace_x3gio_xrom_xrom_reg_9_0_0_0_o3_12_ ( + .I0(com_cmm_u_cmm_cfgspace_N_48848_i), + .I1(com_cmm_u_cmm_cfgspace_sel_3x_4756), + .I2(com_cmm_u_cmm_cfgspace_sel_x1_4775), + .O(com_cmm_u_cmm_cfgspace_N_48953_i) + ); + defparam com_cmm_u_cmm_cfgspace_x3gio_bar4_bar4_reg_8_1_0_0_o3_0_.INIT = 8'h80; + LUT3 com_cmm_u_cmm_cfgspace_x3gio_bar4_bar4_reg_8_1_0_0_o3_0_ ( + .I0(com_cmm_u_cmm_cfgspace_N_48848_i), + .I1(com_cmm_u_cmm_cfgspace_sel_2x_4757), + .I2(com_cmm_u_cmm_cfgspace_sel_x0_4760), + .O(com_cmm_u_cmm_cfgspace_N_48868_i) + ); + defparam com_cmm_u_cmm_cfgspace_x_dcmd_18_i_0_0_0_o3_3_.INIT = 8'h80; + LUT3 com_cmm_u_cmm_cfgspace_x_dcmd_18_i_0_0_0_o3_3_ ( + .I0(com_cmm_u_cmm_cfgspace_N_48848_i), + .I1(com_cmm_u_cmm_cfgspace_sel_6x_4753), + .I2(com_cmm_u_cmm_cfgspace_sel_x0_4760), + .O(com_cmm_u_cmm_cfgspace_x_dcmd_18_i_0_0_0_o3[3]) + ); + defparam com_cmm_u_cmm_cfgspace_x3gio_xrom_xrom_reg_12_0_0_o3_16_.INIT = 8'h80; + LUT3 com_cmm_u_cmm_cfgspace_x3gio_xrom_xrom_reg_12_0_0_o3_16_ ( + .I0(com_cmm_u_cmm_cfgspace_N_48848_i), + .I1(com_cmm_u_cmm_cfgspace_sel_3x_4756), + .I2(com_cmm_u_cmm_cfgspace_sel_x2_4774), + .O(com_cmm_u_cmm_cfgspace_N_48863_i) + ); + defparam com_cmm_u_cmm_cfgspace_x3gio_lcmd_x_lcmd22_0_a2_0_a2_0_a2.INIT = 4'h8; + LUT2 com_cmm_u_cmm_cfgspace_x3gio_lcmd_x_lcmd22_0_a2_0_a2_0_a2 ( + .I0(com_cmm_u_cmm_cfgspace_N_48874_i), + .I1(com_cmm_u_cmm_cfgspace_sel_x8_4768), + .O(com_cmm_u_cmm_cfgspace_x_lcmd22) + ); + defparam com_cmm_u_cmm_cfgspace_x3gio_dsts_x_dsts_9_iv_0_0_0_a2_0_1_3_.INIT = 4'h8; + LUT2 com_cmm_u_cmm_cfgspace_x3gio_dsts_x_dsts_9_iv_0_0_0_a2_0_1_3_ ( + .I0(com_cmm_u_cmm_cfgspace_N_48874_i), + .I1(com_cmm_u_cmm_cfgspace_sel_x2_4774), + .O(com_cmm_u_cmm_cfgspace_N_45410_1) + ); + defparam com_cmm_u_cmm_cfgspace_x3gio_status_status_6_iv_0_0_0_a2_0_1_15_.INIT = 8'h80; + LUT3 com_cmm_u_cmm_cfgspace_x3gio_status_status_6_iv_0_0_0_a2_0_1_15_ ( + .I0(com_cmm_u_cmm_cfgspace_N_48848_i), + .I1(com_cmm_u_cmm_cfgspace_sel_0x_4759), + .I2(com_cmm_u_cmm_cfgspace_sel_x7_4769), + .O(com_cmm_u_cmm_cfgspace_N_45424_1) + ); + defparam com_cmm_u_cmm_cfgspace_x3gio_pmcsr_pme_pmcsr_21_0_i_o3_0_.INIT = 8'h80; + LUT3 com_cmm_u_cmm_cfgspace_x3gio_pmcsr_pme_pmcsr_21_0_i_o3_0_ ( + .I0(com_cmm_u_cmm_cfgspace_N_48848_i), + .I1(com_cmm_u_cmm_cfgspace_sel_4x_4755), + .I2(com_cmm_u_cmm_cfgspace_sel_x4_4772), + .O(com_cmm_u_cmm_cfgspace_pme_pmcsr_21_0_i_o3[0]) + ); + defparam com_cmm_u_cmm_cfgspace_x3gio_pmcsr_pme_pmcsr_21_0_0_i_o3_9_.INIT = 8'h80; + LUT3 com_cmm_u_cmm_cfgspace_x3gio_pmcsr_pme_pmcsr_21_0_0_i_o3_9_ ( + .I0(com_cmm_u_cmm_cfgspace_N_48848_i), + .I1(com_cmm_u_cmm_cfgspace_sel_4x_4755), + .I2(com_cmm_u_cmm_cfgspace_sel_x5_4771), + .O(N_44884_i) + ); + defparam com_cmm_u_cmm_cfgspace_x3gio_xrom_xrom_reg_15_0_0_0_o3_24_.INIT = 8'h80; + LUT3 com_cmm_u_cmm_cfgspace_x3gio_xrom_xrom_reg_15_0_0_0_o3_24_ ( + .I0(com_cmm_u_cmm_cfgspace_N_48848_i), + .I1(com_cmm_u_cmm_cfgspace_sel_3x_4756), + .I2(com_cmm_u_cmm_cfgspace_sel_x3_4773), + .O(com_cmm_u_cmm_cfgspace_N_44871_i) + ); + defparam com_cmm_u_cmm_cfgspace_x3gio_bar3_bar3_reg_8_1_0_o3_0_.INIT = 4'h8; + LUT2 com_cmm_u_cmm_cfgspace_x3gio_bar3_bar3_reg_8_1_0_o3_0_ ( + .I0(com_cmm_u_cmm_cfgspace_N_44842_i), + .I1(com_cmm_u_cmm_cfgspace_sel_xc_4764), + .O(com_cmm_u_cmm_cfgspace_N_44858_i) + ); + defparam com_cmm_u_cmm_cfgspace_x3gio_bar2_bar2_reg_8_1_0_o3_0_.INIT = 4'h8; + LUT2 com_cmm_u_cmm_cfgspace_x3gio_bar2_bar2_reg_8_1_0_o3_0_ ( + .I0(com_cmm_u_cmm_cfgspace_N_44842_i), + .I1(com_cmm_u_cmm_cfgspace_sel_x8_4768), + .O(com_cmm_u_cmm_cfgspace_N_44857_i) + ); + defparam com_cmm_u_cmm_cfgspace_x3gio_bar1_bar1_reg_8_1_0_o3_0_.INIT = 4'h8; + LUT2 com_cmm_u_cmm_cfgspace_x3gio_bar1_bar1_reg_8_1_0_o3_0_ ( + .I0(com_cmm_u_cmm_cfgspace_N_44842_i), + .I1(com_cmm_u_cmm_cfgspace_sel_x4_4772), + .O(com_cmm_u_cmm_cfgspace_N_44856_i) + ); + defparam com_cmm_u_cmm_cfgspace_x3gio_bar5_bar5_reg_8_1_0_o3_0_.INIT = 8'h80; + LUT3 com_cmm_u_cmm_cfgspace_x3gio_bar5_bar5_reg_8_1_0_o3_0_ ( + .I0(com_cmm_u_cmm_cfgspace_N_48848_i), + .I1(com_cmm_u_cmm_cfgspace_sel_2x_4757), + .I2(com_cmm_u_cmm_cfgspace_sel_x4_4772), + .O(com_cmm_u_cmm_cfgspace_N_44854_i) + ); + defparam com_cmm_u_cmm_cfgspace_x3gio_bar3_bar3_reg70_0_a2_0_a2_0_a2.INIT = 4'h8; + LUT2 com_cmm_u_cmm_cfgspace_x3gio_bar3_bar3_reg70_0_a2_0_a2_0_a2 ( + .I0(com_cmm_u_cmm_cfgspace_N_44842_i), + .I1(com_cmm_u_cmm_cfgspace_sel_xf_4761), + .O(com_cmm_u_cmm_cfgspace_bar3_reg70) + ); + defparam com_cmm_u_cmm_cfgspace_x3gio_bar3_bar3_reg58_0_a2_0_a2_0_a2.INIT = 4'h8; + LUT2 com_cmm_u_cmm_cfgspace_x3gio_bar3_bar3_reg58_0_a2_0_a2_0_a2 ( + .I0(com_cmm_u_cmm_cfgspace_N_44842_i), + .I1(com_cmm_u_cmm_cfgspace_sel_xe_4762), + .O(com_cmm_u_cmm_cfgspace_bar3_reg58) + ); + defparam com_cmm_u_cmm_cfgspace_x3gio_bar3_bar3_reg45_0_a2_0_a2_0_a2.INIT = 4'h8; + LUT2 com_cmm_u_cmm_cfgspace_x3gio_bar3_bar3_reg45_0_a2_0_a2_0_a2 ( + .I0(com_cmm_u_cmm_cfgspace_N_44842_i), + .I1(com_cmm_u_cmm_cfgspace_sel_xd_4763), + .O(com_cmm_u_cmm_cfgspace_bar3_reg45) + ); + defparam com_cmm_u_cmm_cfgspace_x3gio_bar2_bar2_reg70_0_a2_0_a2_0_a2.INIT = 4'h8; + LUT2 com_cmm_u_cmm_cfgspace_x3gio_bar2_bar2_reg70_0_a2_0_a2_0_a2 ( + .I0(com_cmm_u_cmm_cfgspace_N_44842_i), + .I1(com_cmm_u_cmm_cfgspace_sel_xb_4765), + .O(com_cmm_u_cmm_cfgspace_bar2_reg70) + ); + defparam com_cmm_u_cmm_cfgspace_x3gio_bar2_bar2_reg58_0_a2_0_a2_0_a2.INIT = 4'h8; + LUT2 com_cmm_u_cmm_cfgspace_x3gio_bar2_bar2_reg58_0_a2_0_a2_0_a2 ( + .I0(com_cmm_u_cmm_cfgspace_N_44842_i), + .I1(com_cmm_u_cmm_cfgspace_sel_xa_4766), + .O(com_cmm_u_cmm_cfgspace_bar2_reg58) + ); + defparam com_cmm_u_cmm_cfgspace_x3gio_bar2_bar2_reg45_0_a2_0_a2_0_a2.INIT = 4'h8; + LUT2 com_cmm_u_cmm_cfgspace_x3gio_bar2_bar2_reg45_0_a2_0_a2_0_a2 ( + .I0(com_cmm_u_cmm_cfgspace_N_44842_i), + .I1(com_cmm_u_cmm_cfgspace_sel_x9_4767), + .O(com_cmm_u_cmm_cfgspace_bar2_reg45) + ); + defparam com_cmm_u_cmm_cfgspace_x3gio_bar1_bar1_reg45_0_a2_0_a2_0_a2.INIT = 4'h8; + LUT2 com_cmm_u_cmm_cfgspace_x3gio_bar1_bar1_reg45_0_a2_0_a2_0_a2 ( + .I0(com_cmm_u_cmm_cfgspace_N_44842_i), + .I1(com_cmm_u_cmm_cfgspace_sel_x5_4771), + .O(com_cmm_u_cmm_cfgspace_bar1_reg45) + ); + defparam com_cmm_u_cmm_cfgspace_x3gio_bar0_bar0_reg44_0_a2_0_a2_0_a2.INIT = 4'h8; + LUT2 com_cmm_u_cmm_cfgspace_x3gio_bar0_bar0_reg44_0_a2_0_a2_0_a2 ( + .I0(com_cmm_u_cmm_cfgspace_N_44842_i), + .I1(com_cmm_u_cmm_cfgspace_sel_x2_4774), + .O(com_cmm_u_cmm_cfgspace_bar0_reg44) + ); + defparam com_cmm_u_cmm_cfgspace_x3gio_bar0_bar0_reg31_0_a2_0_a2_0_a2.INIT = 4'h8; + LUT2 com_cmm_u_cmm_cfgspace_x3gio_bar0_bar0_reg31_0_a2_0_a2_0_a2 ( + .I0(com_cmm_u_cmm_cfgspace_N_44842_i), + .I1(com_cmm_u_cmm_cfgspace_sel_x1_4775), + .O(com_cmm_u_cmm_cfgspace_bar0_reg31) + ); + defparam com_cmm_u_cmm_cfgspace_x3gio_bar5_bar5_reg58_0_a2_0_a2.INIT = 8'h80; + LUT3 com_cmm_u_cmm_cfgspace_x3gio_bar5_bar5_reg58_0_a2_0_a2 ( + .I0(com_cmm_u_cmm_cfgspace_N_48848_i), + .I1(com_cmm_u_cmm_cfgspace_sel_2x_4757), + .I2(com_cmm_u_cmm_cfgspace_sel_x6_4770), + .O(com_cmm_u_cmm_cfgspace_bar5_reg58) + ); + defparam com_cmm_u_cmm_cfgspace_x3gio_bar1_bar1_reg58_0_a2_0_a2.INIT = 4'h8; + LUT2 com_cmm_u_cmm_cfgspace_x3gio_bar1_bar1_reg58_0_a2_0_a2 ( + .I0(com_cmm_u_cmm_cfgspace_N_44842_i), + .I1(com_cmm_u_cmm_cfgspace_sel_x6_4770), + .O(com_cmm_u_cmm_cfgspace_bar1_reg58) + ); + defparam com_cmm_u_cmm_cfgspace_x3gio_msiladdr_msi_laddr51_0_a2_0_a2_0_a2.INIT = 8'h80; + LUT3 com_cmm_u_cmm_cfgspace_x3gio_msiladdr_msi_laddr51_0_a2_0_a2_0_a2 ( + .I0(com_cmm_u_cmm_cfgspace_N_48848_i), + .I1(com_cmm_u_cmm_cfgspace_sel_4x_4755), + .I2(com_cmm_u_cmm_cfgspace_sel_xf_4761), + .O(com_cmm_u_cmm_cfgspace_msi_laddr51) + ); + defparam com_cmm_u_cmm_cfgspace_x3gio_msiladdr_msi_laddr40_0_a2_0_a2_0_a2.INIT = 8'h80; + LUT3 com_cmm_u_cmm_cfgspace_x3gio_msiladdr_msi_laddr40_0_a2_0_a2_0_a2 ( + .I0(com_cmm_u_cmm_cfgspace_N_48848_i), + .I1(com_cmm_u_cmm_cfgspace_sel_4x_4755), + .I2(com_cmm_u_cmm_cfgspace_sel_xe_4762), + .O(com_cmm_u_cmm_cfgspace_msi_laddr40) + ); + defparam com_cmm_u_cmm_cfgspace_x3gio_msiladdr_msi_laddr28_0_a2_0_a2_0_a2.INIT = 8'h80; + LUT3 com_cmm_u_cmm_cfgspace_x3gio_msiladdr_msi_laddr28_0_a2_0_a2_0_a2 ( + .I0(com_cmm_u_cmm_cfgspace_N_48848_i), + .I1(com_cmm_u_cmm_cfgspace_sel_4x_4755), + .I2(com_cmm_u_cmm_cfgspace_sel_xd_4763), + .O(com_cmm_u_cmm_cfgspace_msi_laddr28) + ); + defparam com_cmm_u_cmm_cfgspace_x3gio_msictrl_msi_control27_0_a2_0_a2_0_a2.INIT = 8'h80; + LUT3 com_cmm_u_cmm_cfgspace_x3gio_msictrl_msi_control27_0_a2_0_a2_0_a2 ( + .I0(com_cmm_u_cmm_cfgspace_N_48848_i), + .I1(com_cmm_u_cmm_cfgspace_sel_4x_4755), + .I2(com_cmm_u_cmm_cfgspace_sel_xa_4766), + .O(com_cmm_u_cmm_cfgspace_msi_control27) + ); + defparam com_cmm_u_cmm_cfgspace_x3gio_bar5_bar5_reg45_0_a2_0_a2_0_a2.INIT = 8'h80; + LUT3 com_cmm_u_cmm_cfgspace_x3gio_bar5_bar5_reg45_0_a2_0_a2_0_a2 ( + .I0(com_cmm_u_cmm_cfgspace_N_48848_i), + .I1(com_cmm_u_cmm_cfgspace_sel_2x_4757), + .I2(com_cmm_u_cmm_cfgspace_sel_x5_4771), + .O(com_cmm_u_cmm_cfgspace_bar5_reg45) + ); + defparam com_cmm_u_cmm_cfgspace_x3gio_bar4_bar4_reg58_0_a2_0_a2_0_a2.INIT = 8'h80; + LUT3 com_cmm_u_cmm_cfgspace_x3gio_bar4_bar4_reg58_0_a2_0_a2_0_a2 ( + .I0(com_cmm_u_cmm_cfgspace_N_48848_i), + .I1(com_cmm_u_cmm_cfgspace_sel_2x_4757), + .I2(com_cmm_u_cmm_cfgspace_sel_x2_4774), + .O(com_cmm_u_cmm_cfgspace_bar4_reg58) + ); + defparam com_cmm_u_cmm_cfgspace_x3gio_command_command93_0_a2_0_a2_0_a2.INIT = 8'h80; + LUT3 com_cmm_u_cmm_cfgspace_x3gio_command_command93_0_a2_0_a2_0_a2 ( + .I0(com_cmm_u_cmm_cfgspace_N_48848_i), + .I1(com_cmm_u_cmm_cfgspace_sel_0x_4759), + .I2(com_cmm_u_cmm_cfgspace_sel_x5_4771), + .O(com_cmm_u_cmm_cfgspace_command93) + ); + defparam com_cmm_u_cmm_cfgspace_x3gio_bar4_bar4_reg70_0_a2_0_a2_0_a2.INIT = 8'h80; + LUT3 com_cmm_u_cmm_cfgspace_x3gio_bar4_bar4_reg70_0_a2_0_a2_0_a2 ( + .I0(com_cmm_u_cmm_cfgspace_N_48848_i), + .I1(com_cmm_u_cmm_cfgspace_sel_2x_4757), + .I2(com_cmm_u_cmm_cfgspace_sel_x3_4773), + .O(com_cmm_u_cmm_cfgspace_bar4_reg70) + ); + defparam com_cmm_u_cmm_cfgspace_x3gio_bar0_bar0_reg56_0_a2_0_a2_0_a2.INIT = 4'h8; + LUT2 com_cmm_u_cmm_cfgspace_x3gio_bar0_bar0_reg56_0_a2_0_a2_0_a2 ( + .I0(com_cmm_u_cmm_cfgspace_N_44842_i), + .I1(com_cmm_u_cmm_cfgspace_sel_x3_4773), + .O(com_cmm_u_cmm_cfgspace_bar0_reg56) + ); + defparam com_cmm_u_cmm_cfgspace_x3gio_bar4_bar4_reg45_0_a2_0_a2_0_a2.INIT = 8'h80; + LUT3 com_cmm_u_cmm_cfgspace_x3gio_bar4_bar4_reg45_0_a2_0_a2_0_a2 ( + .I0(com_cmm_u_cmm_cfgspace_N_48848_i), + .I1(com_cmm_u_cmm_cfgspace_sel_2x_4757), + .I2(com_cmm_u_cmm_cfgspace_sel_x1_4775), + .O(com_cmm_u_cmm_cfgspace_bar4_reg45) + ); + defparam com_cmm_u_cmm_cfgspace_x3gio_msiladdr_msi_laddr16_0_a2_0_a2_0_a2.INIT = 8'h80; + LUT3 com_cmm_u_cmm_cfgspace_x3gio_msiladdr_msi_laddr16_0_a2_0_a2_0_a2 ( + .I0(com_cmm_u_cmm_cfgspace_N_48848_i), + .I1(com_cmm_u_cmm_cfgspace_sel_4x_4755), + .I2(com_cmm_u_cmm_cfgspace_sel_xc_4764), + .O(com_cmm_u_cmm_cfgspace_msi_laddr16) + ); + defparam com_cmm_u_cmm_cfgspace_x3gio_intline_int_line8_0_a2_0_a2_0_a2.INIT = 8'h80; + LUT3 com_cmm_u_cmm_cfgspace_x3gio_intline_int_line8_0_a2_0_a2_0_a2 ( + .I0(com_cmm_u_cmm_cfgspace_N_48848_i), + .I1(com_cmm_u_cmm_cfgspace_sel_3x_4756), + .I2(com_cmm_u_cmm_cfgspace_sel_xc_4764), + .O(com_cmm_u_cmm_cfgspace_int_line8) + ); + defparam com_cmm_u_cmm_cfgspace_x3gio_bar5_bar5_reg70_0_a2_0_a2_0_a2.INIT = 8'h80; + LUT3 com_cmm_u_cmm_cfgspace_x3gio_bar5_bar5_reg70_0_a2_0_a2_0_a2 ( + .I0(com_cmm_u_cmm_cfgspace_N_48848_i), + .I1(com_cmm_u_cmm_cfgspace_sel_2x_4757), + .I2(com_cmm_u_cmm_cfgspace_sel_x7_4769), + .O(com_cmm_u_cmm_cfgspace_bar5_reg70) + ); + defparam com_cmm_u_cmm_cfgspace_x3gio_bar1_bar1_reg70_0_a2_0_a2_0_a2.INIT = 4'h8; + LUT2 com_cmm_u_cmm_cfgspace_x3gio_bar1_bar1_reg70_0_a2_0_a2_0_a2 ( + .I0(com_cmm_u_cmm_cfgspace_N_44842_i), + .I1(com_cmm_u_cmm_cfgspace_sel_x7_4769), + .O(com_cmm_u_cmm_cfgspace_bar1_reg70) + ); + defparam com_cmm_u_cmm_cfgspace_x3gio_bar0_bar0_reg18_0_a2_0_a2_0_a2.INIT = 4'h8; + LUT2 com_cmm_u_cmm_cfgspace_x3gio_bar0_bar0_reg18_0_a2_0_a2_0_a2 ( + .I0(com_cmm_u_cmm_cfgspace_N_44842_i), + .I1(com_cmm_u_cmm_cfgspace_sel_x0_4760), + .O(com_cmm_u_cmm_cfgspace_bar0_reg18) + ); + defparam com_cmm_u_cmm_cfgspace_x3gio_cacheline_cache_line8_0_a2_0_a2_0_a2.INIT = 8'h80; + LUT3 com_cmm_u_cmm_cfgspace_x3gio_cacheline_cache_line8_0_a2_0_a2_0_a2 ( + .I0(com_cmm_u_cmm_cfgspace_N_48848_i), + .I1(com_cmm_u_cmm_cfgspace_sel_0x_4759), + .I2(com_cmm_u_cmm_cfgspace_sel_xc_4764), + .O(com_cmm_u_cmm_cfgspace_cache_line8) + ); + defparam com_cmm_u_cmm_cfgspace_x3gio_command_command67_0_a2_0_a2.INIT = 8'h80; + LUT3 com_cmm_u_cmm_cfgspace_x3gio_command_command67_0_a2_0_a2 ( + .I0(com_cmm_u_cmm_cfgspace_N_48848_i), + .I1(com_cmm_u_cmm_cfgspace_sel_0x_4759), + .I2(com_cmm_u_cmm_cfgspace_sel_x4_4772), + .O(com_cmm_u_cmm_cfgspace_command67) + ); + defparam com_cmm_u_cmm_cfgspace_cfg2ulm_rddata_0_a2_0_a2_0_a2_25_.INIT = 4'h8; + LUT2 com_cmm_u_cmm_cfgspace_cfg2ulm_rddata_0_a2_0_a2_0_a2_25_ ( + .I0(com_cmm_u_cmm_cfgspace_cfg2ulm_valid), + .I1(com_cmm_u_cmm_cfgspace_decoder_read_data[25]), + .O(cfg_do_5066[25]) + ); + defparam com_cmm_u_cmm_cfgspace_cfg2ulm_rddata_0_a2_0_a2_0_a2_24_.INIT = 4'h8; + LUT2 com_cmm_u_cmm_cfgspace_cfg2ulm_rddata_0_a2_0_a2_0_a2_24_ ( + .I0(com_cmm_u_cmm_cfgspace_cfg2ulm_valid), + .I1(com_cmm_u_cmm_cfgspace_decoder_read_data[24]), + .O(cfg_do_5066[24]) + ); + defparam com_cmm_u_cmm_cfgspace_cfg2ulm_rddata_0_a2_0_a2_0_a2_23_.INIT = 4'h8; + LUT2 com_cmm_u_cmm_cfgspace_cfg2ulm_rddata_0_a2_0_a2_0_a2_23_ ( + .I0(com_cmm_u_cmm_cfgspace_cfg2ulm_valid), + .I1(com_cmm_u_cmm_cfgspace_decoder_read_data[23]), + .O(cfg_do_5066[23]) + ); + defparam com_cmm_u_cmm_cfgspace_cfg2ulm_rddata_0_a2_0_a2_0_a2_22_.INIT = 4'h8; + LUT2 com_cmm_u_cmm_cfgspace_cfg2ulm_rddata_0_a2_0_a2_0_a2_22_ ( + .I0(com_cmm_u_cmm_cfgspace_cfg2ulm_valid), + .I1(com_cmm_u_cmm_cfgspace_decoder_read_data[22]), + .O(cfg_do_5066[22]) + ); + defparam com_cmm_u_cmm_cfgspace_cfg2ulm_rddata_0_a2_0_a2_0_a2_21_.INIT = 4'h8; + LUT2 com_cmm_u_cmm_cfgspace_cfg2ulm_rddata_0_a2_0_a2_0_a2_21_ ( + .I0(com_cmm_u_cmm_cfgspace_cfg2ulm_valid), + .I1(com_cmm_u_cmm_cfgspace_decoder_read_data[21]), + .O(cfg_do_5066[21]) + ); + defparam com_cmm_u_cmm_cfgspace_cfg2ulm_rddata_0_a2_0_a2_0_a2_20_.INIT = 4'h8; + LUT2 com_cmm_u_cmm_cfgspace_cfg2ulm_rddata_0_a2_0_a2_0_a2_20_ ( + .I0(com_cmm_u_cmm_cfgspace_cfg2ulm_valid), + .I1(com_cmm_u_cmm_cfgspace_decoder_read_data[20]), + .O(cfg_do_5066[20]) + ); + defparam com_cmm_u_cmm_cfgspace_cfg2ulm_rddata_0_a2_0_a2_0_a2_19_.INIT = 4'h8; + LUT2 com_cmm_u_cmm_cfgspace_cfg2ulm_rddata_0_a2_0_a2_0_a2_19_ ( + .I0(com_cmm_u_cmm_cfgspace_cfg2ulm_valid), + .I1(com_cmm_u_cmm_cfgspace_decoder_read_data[19]), + .O(cfg_do_5066[19]) + ); + defparam com_cmm_u_cmm_cfgspace_cfg2ulm_rddata_0_a2_0_a2_0_a2_18_.INIT = 4'h8; + LUT2 com_cmm_u_cmm_cfgspace_cfg2ulm_rddata_0_a2_0_a2_0_a2_18_ ( + .I0(com_cmm_u_cmm_cfgspace_cfg2ulm_valid), + .I1(com_cmm_u_cmm_cfgspace_decoder_read_data[18]), + .O(cfg_do_5066[18]) + ); + defparam com_cmm_u_cmm_cfgspace_cfg2ulm_rddata_0_a2_0_a2_0_a2_17_.INIT = 4'h8; + LUT2 com_cmm_u_cmm_cfgspace_cfg2ulm_rddata_0_a2_0_a2_0_a2_17_ ( + .I0(com_cmm_u_cmm_cfgspace_cfg2ulm_valid), + .I1(com_cmm_u_cmm_cfgspace_decoder_read_data[17]), + .O(cfg_do_5066[17]) + ); + defparam com_cmm_u_cmm_cfgspace_cfg2ulm_rddata_0_a2_0_a2_0_a2_16_.INIT = 4'h8; + LUT2 com_cmm_u_cmm_cfgspace_cfg2ulm_rddata_0_a2_0_a2_0_a2_16_ ( + .I0(com_cmm_u_cmm_cfgspace_cfg2ulm_valid), + .I1(com_cmm_u_cmm_cfgspace_decoder_read_data[16]), + .O(cfg_do_5066[16]) + ); + defparam com_cmm_u_cmm_cfgspace_cfg2ulm_rddata_0_a2_0_a2_0_a2_15_.INIT = 4'h8; + LUT2 com_cmm_u_cmm_cfgspace_cfg2ulm_rddata_0_a2_0_a2_0_a2_15_ ( + .I0(com_cmm_u_cmm_cfgspace_cfg2ulm_valid), + .I1(com_cmm_u_cmm_cfgspace_decoder_read_data[15]), + .O(cfg_do_5066[15]) + ); + defparam com_cmm_u_cmm_cfgspace_cfg2ulm_rddata_0_a2_0_a2_0_a2_14_.INIT = 4'h8; + LUT2 com_cmm_u_cmm_cfgspace_cfg2ulm_rddata_0_a2_0_a2_0_a2_14_ ( + .I0(com_cmm_u_cmm_cfgspace_cfg2ulm_valid), + .I1(com_cmm_u_cmm_cfgspace_decoder_read_data[14]), + .O(cfg_do_5066[14]) + ); + defparam com_cmm_u_cmm_cfgspace_cfg2ulm_rddata_0_a2_0_a2_0_a2_13_.INIT = 4'h8; + LUT2 com_cmm_u_cmm_cfgspace_cfg2ulm_rddata_0_a2_0_a2_0_a2_13_ ( + .I0(com_cmm_u_cmm_cfgspace_cfg2ulm_valid), + .I1(com_cmm_u_cmm_cfgspace_decoder_read_data[13]), + .O(cfg_do_5066[13]) + ); + defparam com_cmm_u_cmm_cfgspace_cfg2ulm_rddata_0_a2_0_a2_0_a2_12_.INIT = 4'h8; + LUT2 com_cmm_u_cmm_cfgspace_cfg2ulm_rddata_0_a2_0_a2_0_a2_12_ ( + .I0(com_cmm_u_cmm_cfgspace_cfg2ulm_valid), + .I1(com_cmm_u_cmm_cfgspace_decoder_read_data[12]), + .O(cfg_do_5066[12]) + ); + defparam com_cmm_u_cmm_cfgspace_cfg2ulm_rddata_0_a2_0_a2_0_a2_11_.INIT = 4'h8; + LUT2 com_cmm_u_cmm_cfgspace_cfg2ulm_rddata_0_a2_0_a2_0_a2_11_ ( + .I0(com_cmm_u_cmm_cfgspace_cfg2ulm_valid), + .I1(com_cmm_u_cmm_cfgspace_decoder_read_data[11]), + .O(cfg_do_5066[11]) + ); + defparam com_cmm_u_cmm_cfgspace_cfg2ulm_rddata_0_a2_0_a2_0_a2_10_.INIT = 4'h8; + LUT2 com_cmm_u_cmm_cfgspace_cfg2ulm_rddata_0_a2_0_a2_0_a2_10_ ( + .I0(com_cmm_u_cmm_cfgspace_cfg2ulm_valid), + .I1(com_cmm_u_cmm_cfgspace_decoder_read_data[10]), + .O(cfg_do_5066[10]) + ); + defparam com_cmm_u_cmm_cfgspace_cfg2ulm_rddata_0_a2_0_a2_0_a2_9_.INIT = 4'h8; + LUT2 com_cmm_u_cmm_cfgspace_cfg2ulm_rddata_0_a2_0_a2_0_a2_9_ ( + .I0(com_cmm_u_cmm_cfgspace_cfg2ulm_valid), + .I1(com_cmm_u_cmm_cfgspace_decoder_read_data[9]), + .O(cfg_do_5066[9]) + ); + defparam com_cmm_u_cmm_cfgspace_cfg2ulm_rddata_0_a2_0_a2_0_a2_8_.INIT = 4'h8; + LUT2 com_cmm_u_cmm_cfgspace_cfg2ulm_rddata_0_a2_0_a2_0_a2_8_ ( + .I0(com_cmm_u_cmm_cfgspace_cfg2ulm_valid), + .I1(com_cmm_u_cmm_cfgspace_decoder_read_data[8]), + .O(cfg_do_5066[8]) + ); + defparam com_cmm_u_cmm_cfgspace_cfg2ulm_rddata_0_a2_0_a2_31_.INIT = 4'h8; + LUT2 com_cmm_u_cmm_cfgspace_cfg2ulm_rddata_0_a2_0_a2_31_ ( + .I0(com_cmm_u_cmm_cfgspace_cfg2ulm_valid), + .I1(com_cmm_u_cmm_cfgspace_decoder_read_data[31]), + .O(cfg_do_5066[31]) + ); + defparam com_cmm_u_cmm_cfgspace_cfg2ulm_rddata_0_a2_0_a2_30_.INIT = 4'h8; + LUT2 com_cmm_u_cmm_cfgspace_cfg2ulm_rddata_0_a2_0_a2_30_ ( + .I0(com_cmm_u_cmm_cfgspace_cfg2ulm_valid), + .I1(com_cmm_u_cmm_cfgspace_decoder_read_data[30]), + .O(cfg_do_5066[30]) + ); + defparam com_cmm_u_cmm_cfgspace_cfg2ulm_rddata_0_a2_0_a2_29_.INIT = 4'h8; + LUT2 com_cmm_u_cmm_cfgspace_cfg2ulm_rddata_0_a2_0_a2_29_ ( + .I0(com_cmm_u_cmm_cfgspace_cfg2ulm_valid), + .I1(com_cmm_u_cmm_cfgspace_decoder_read_data[29]), + .O(cfg_do_5066[29]) + ); + defparam com_cmm_u_cmm_cfgspace_cfg2ulm_rddata_0_a2_0_a2_28_.INIT = 4'h8; + LUT2 com_cmm_u_cmm_cfgspace_cfg2ulm_rddata_0_a2_0_a2_28_ ( + .I0(com_cmm_u_cmm_cfgspace_cfg2ulm_valid), + .I1(com_cmm_u_cmm_cfgspace_decoder_read_data[28]), + .O(cfg_do_5066[28]) + ); + defparam com_cmm_u_cmm_cfgspace_cfg2ulm_rddata_0_a2_0_a2_27_.INIT = 4'h8; + LUT2 com_cmm_u_cmm_cfgspace_cfg2ulm_rddata_0_a2_0_a2_27_ ( + .I0(com_cmm_u_cmm_cfgspace_cfg2ulm_valid), + .I1(com_cmm_u_cmm_cfgspace_decoder_read_data[27]), + .O(cfg_do_5066[27]) + ); + defparam com_cmm_u_cmm_cfgspace_cfg2ulm_rddata_0_a2_0_a2_26_.INIT = 4'h8; + LUT2 com_cmm_u_cmm_cfgspace_cfg2ulm_rddata_0_a2_0_a2_26_ ( + .I0(com_cmm_u_cmm_cfgspace_cfg2ulm_valid), + .I1(com_cmm_u_cmm_cfgspace_decoder_read_data[26]), + .O(cfg_do_5066[26]) + ); + defparam com_cmm_u_cmm_cfgspace_cfg2ulm_rddata_0_a2_0_a2_7_.INIT = 4'h8; + LUT2 com_cmm_u_cmm_cfgspace_cfg2ulm_rddata_0_a2_0_a2_7_ ( + .I0(com_cmm_u_cmm_cfgspace_cfg2ulm_valid), + .I1(com_cmm_u_cmm_cfgspace_decoder_read_data[7]), + .O(cfg_do_5066[7]) + ); + defparam com_cmm_u_cmm_cfgspace_cfg2ulm_rddata_0_a2_0_a2_6_.INIT = 4'h8; + LUT2 com_cmm_u_cmm_cfgspace_cfg2ulm_rddata_0_a2_0_a2_6_ ( + .I0(com_cmm_u_cmm_cfgspace_cfg2ulm_valid), + .I1(com_cmm_u_cmm_cfgspace_decoder_read_data[6]), + .O(cfg_do_5066[6]) + ); + defparam com_cmm_u_cmm_cfgspace_cfg2ulm_rddata_0_a2_0_a2_5_.INIT = 4'h8; + LUT2 com_cmm_u_cmm_cfgspace_cfg2ulm_rddata_0_a2_0_a2_5_ ( + .I0(com_cmm_u_cmm_cfgspace_cfg2ulm_valid), + .I1(com_cmm_u_cmm_cfgspace_decoder_read_data[5]), + .O(cfg_do_5066[5]) + ); + defparam com_cmm_u_cmm_cfgspace_cfg2ulm_rddata_0_a2_0_a2_4_.INIT = 4'h8; + LUT2 com_cmm_u_cmm_cfgspace_cfg2ulm_rddata_0_a2_0_a2_4_ ( + .I0(com_cmm_u_cmm_cfgspace_cfg2ulm_valid), + .I1(com_cmm_u_cmm_cfgspace_decoder_read_data[4]), + .O(cfg_do_5066[4]) + ); + defparam com_cmm_u_cmm_cfgspace_cfg2ulm_rddata_0_a2_0_a2_3_.INIT = 4'h8; + LUT2 com_cmm_u_cmm_cfgspace_cfg2ulm_rddata_0_a2_0_a2_3_ ( + .I0(com_cmm_u_cmm_cfgspace_cfg2ulm_valid), + .I1(com_cmm_u_cmm_cfgspace_decoder_read_data[3]), + .O(cfg_do_5066[3]) + ); + defparam com_cmm_u_cmm_cfgspace_cfg2ulm_rddata_0_a2_0_a2_2_.INIT = 4'h8; + LUT2 com_cmm_u_cmm_cfgspace_cfg2ulm_rddata_0_a2_0_a2_2_ ( + .I0(com_cmm_u_cmm_cfgspace_cfg2ulm_valid), + .I1(com_cmm_u_cmm_cfgspace_decoder_read_data[2]), + .O(cfg_do_5066[2]) + ); + defparam com_cmm_u_cmm_cfgspace_cfg2ulm_rddata_0_a2_0_a2_1_.INIT = 4'h8; + LUT2 com_cmm_u_cmm_cfgspace_cfg2ulm_rddata_0_a2_0_a2_1_ ( + .I0(com_cmm_u_cmm_cfgspace_cfg2ulm_valid), + .I1(com_cmm_u_cmm_cfgspace_decoder_read_data[1]), + .O(cfg_do_5066[1]) + ); + defparam com_cmm_u_cmm_cfgspace_cfg2ulm_rddata_0_a2_0_a2_0_.INIT = 4'h8; + LUT2 com_cmm_u_cmm_cfgspace_cfg2ulm_rddata_0_a2_0_a2_0_ ( + .I0(com_cmm_u_cmm_cfgspace_cfg2ulm_valid), + .I1(com_cmm_u_cmm_cfgspace_decoder_read_data[0]), + .O(cfg_do_5066[0]) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_01_7_0_am_16_.INIT = 16'hC808; + LUT4 com_cmm_u_cmm_cfgspace_low_addr_01_7_0_am_16_ ( + .I0(com_cmm_bar5_reg[16]), + .I1(com_cmm_u_cmm_cfgspace_sel_encodex_1[1]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex[2]), + .I3(com_cmm_u_cmm_cfgspace_x_lcap[0]), + .O(com_cmm_u_cmm_cfgspace_low_addr_01_7_0_am_16__4534) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_01_7_0_bm_16_.INIT = 16'hA00C; + LUT4 com_cmm_u_cmm_cfgspace_low_addr_01_7_0_bm_16_ ( + .I0(cfg_cfg_5072[672]), + .I1(com_cmm_bar1_reg[16]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex_1[1]), + .I3(com_cmm_u_cmm_cfgspace_sel_encodex[2]), + .O(com_cmm_u_cmm_cfgspace_low_addr_01_7_0_bm_16__4533) + ); + MUXF5 com_cmm_u_cmm_cfgspace_low_addr_01_7_0_16_ ( + .I0(com_cmm_u_cmm_cfgspace_low_addr_01_7_0_am_16__4534), + .I1(com_cmm_u_cmm_cfgspace_low_addr_01_7_0_bm_16__4533), + .O(com_cmm_u_cmm_cfgspace_low_addr_01[16]), + .S(com_cmm_u_cmm_cfgspace_sel_encodex_1[0]) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_01_7_0_am_17_.INIT = 16'hC808; + LUT4 com_cmm_u_cmm_cfgspace_low_addr_01_7_0_am_17_ ( + .I0(com_cmm_bar5_reg[17]), + .I1(com_cmm_u_cmm_cfgspace_sel_encodex_1[1]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex[2]), + .I3(com_cmm_u_cmm_cfgspace_x_lcap[0]), + .O(com_cmm_u_cmm_cfgspace_low_addr_01_7_0_am_17__4536) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_01_7_0_bm_17_.INIT = 16'hA00C; + LUT4 com_cmm_u_cmm_cfgspace_low_addr_01_7_0_bm_17_ ( + .I0(cfg_cfg_5072[673]), + .I1(com_cmm_bar1_reg[17]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex_1[1]), + .I3(com_cmm_u_cmm_cfgspace_sel_encodex[2]), + .O(com_cmm_u_cmm_cfgspace_low_addr_01_7_0_bm_17__4535) + ); + MUXF5 com_cmm_u_cmm_cfgspace_low_addr_01_7_0_17_ ( + .I0(com_cmm_u_cmm_cfgspace_low_addr_01_7_0_am_17__4536), + .I1(com_cmm_u_cmm_cfgspace_low_addr_01_7_0_bm_17__4535), + .O(com_cmm_u_cmm_cfgspace_low_addr_01[17]), + .S(com_cmm_u_cmm_cfgspace_sel_encodex_1[0]) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_01_7_0_am_18_.INIT = 16'hA0C0; + LUT4 com_cmm_u_cmm_cfgspace_low_addr_01_7_0_am_18_ ( + .I0(cfg_cfg_5072[418]), + .I1(com_cmm_bar5_reg[18]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex_1[1]), + .I3(com_cmm_u_cmm_cfgspace_sel_encodex[2]), + .O(com_cmm_u_cmm_cfgspace_low_addr_01_7_0_am_18__4538) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_01_7_0_bm_18_.INIT = 16'hA00C; + LUT4 com_cmm_u_cmm_cfgspace_low_addr_01_7_0_bm_18_ ( + .I0(cfg_cfg_5072[674]), + .I1(com_cmm_bar1_reg[18]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex_1[1]), + .I3(com_cmm_u_cmm_cfgspace_sel_encodex[2]), + .O(com_cmm_u_cmm_cfgspace_low_addr_01_7_0_bm_18__4537) + ); + MUXF5 com_cmm_u_cmm_cfgspace_low_addr_01_7_0_18_ ( + .I0(com_cmm_u_cmm_cfgspace_low_addr_01_7_0_am_18__4538), + .I1(com_cmm_u_cmm_cfgspace_low_addr_01_7_0_bm_18__4537), + .O(com_cmm_u_cmm_cfgspace_low_addr_01[18]), + .S(com_cmm_u_cmm_cfgspace_sel_encodex_1[0]) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_01_7_0_am_20_.INIT = 16'hA0CF; + LUT4 com_cmm_u_cmm_cfgspace_low_addr_01_7_0_am_20_ ( + .I0(cfg_cfg_5072[420]), + .I1(com_cmm_bar5_reg[20]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex_1[1]), + .I3(com_cmm_u_cmm_cfgspace_sel_encodex[2]), + .O(com_cmm_u_cmm_cfgspace_low_addr_01_7_0_am_20__4540) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_01_7_0_bm_20_.INIT = 16'hA00C; + LUT4 com_cmm_u_cmm_cfgspace_low_addr_01_7_0_bm_20_ ( + .I0(cfg_cfg_5072[676]), + .I1(com_cmm_bar1_reg[20]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex_1[1]), + .I3(com_cmm_u_cmm_cfgspace_sel_encodex[2]), + .O(com_cmm_u_cmm_cfgspace_low_addr_01_7_0_bm_20__4539) + ); + MUXF5 com_cmm_u_cmm_cfgspace_low_addr_01_7_0_20_ ( + .I0(com_cmm_u_cmm_cfgspace_low_addr_01_7_0_am_20__4540), + .I1(com_cmm_u_cmm_cfgspace_low_addr_01_7_0_bm_20__4539), + .O(com_cmm_u_cmm_cfgspace_low_addr_01[20]), + .S(com_cmm_u_cmm_cfgspace_sel_encodex_1[0]) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_01_7_0_am_21_.INIT = 16'hA0C0; + LUT4 com_cmm_u_cmm_cfgspace_low_addr_01_7_0_am_21_ ( + .I0(cfg_cfg_5072[421]), + .I1(com_cmm_bar5_reg[21]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex_1[1]), + .I3(com_cmm_u_cmm_cfgspace_sel_encodex[2]), + .O(com_cmm_u_cmm_cfgspace_low_addr_01_7_0_am_21__4542) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_01_7_0_bm_21_.INIT = 16'hA00C; + LUT4 com_cmm_u_cmm_cfgspace_low_addr_01_7_0_bm_21_ ( + .I0(cfg_cfg_5072[677]), + .I1(com_cmm_bar1_reg[21]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex_1[1]), + .I3(com_cmm_u_cmm_cfgspace_sel_encodex[2]), + .O(com_cmm_u_cmm_cfgspace_low_addr_01_7_0_bm_21__4541) + ); + MUXF5 com_cmm_u_cmm_cfgspace_low_addr_01_7_0_21_ ( + .I0(com_cmm_u_cmm_cfgspace_low_addr_01_7_0_am_21__4542), + .I1(com_cmm_u_cmm_cfgspace_low_addr_01_7_0_bm_21__4541), + .O(com_cmm_u_cmm_cfgspace_low_addr_01[21]), + .S(com_cmm_u_cmm_cfgspace_sel_encodex_1[0]) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_01_7_0_am_22_.INIT = 16'hA0C0; + LUT4 com_cmm_u_cmm_cfgspace_low_addr_01_7_0_am_22_ ( + .I0(cfg_cfg_5072[422]), + .I1(com_cmm_bar5_reg[22]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex_1[1]), + .I3(com_cmm_u_cmm_cfgspace_sel_encodex[2]), + .O(com_cmm_u_cmm_cfgspace_low_addr_01_7_0_am_22__4544) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_01_7_0_bm_22_.INIT = 16'hA00C; + LUT4 com_cmm_u_cmm_cfgspace_low_addr_01_7_0_bm_22_ ( + .I0(cfg_cfg_5072[678]), + .I1(com_cmm_bar1_reg[22]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex_1[1]), + .I3(com_cmm_u_cmm_cfgspace_sel_encodex[2]), + .O(com_cmm_u_cmm_cfgspace_low_addr_01_7_0_bm_22__4543) + ); + MUXF5 com_cmm_u_cmm_cfgspace_low_addr_01_7_0_22_ ( + .I0(com_cmm_u_cmm_cfgspace_low_addr_01_7_0_am_22__4544), + .I1(com_cmm_u_cmm_cfgspace_low_addr_01_7_0_bm_22__4543), + .O(com_cmm_u_cmm_cfgspace_low_addr_01[22]), + .S(com_cmm_u_cmm_cfgspace_sel_encodex_1[0]) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_01_7_0_am_23_.INIT = 16'hA0C0; + LUT4 com_cmm_u_cmm_cfgspace_low_addr_01_7_0_am_23_ ( + .I0(cfg_cfg_5072[423]), + .I1(com_cmm_bar5_reg[23]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex_1[1]), + .I3(com_cmm_u_cmm_cfgspace_sel_encodex[2]), + .O(com_cmm_u_cmm_cfgspace_low_addr_01_7_0_am_23__4546) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_01_7_0_bm_23_.INIT = 16'hA00C; + LUT4 com_cmm_u_cmm_cfgspace_low_addr_01_7_0_bm_23_ ( + .I0(cfg_cfg_5072[679]), + .I1(com_cmm_bar1_reg[23]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex_1[1]), + .I3(com_cmm_u_cmm_cfgspace_sel_encodex[2]), + .O(com_cmm_u_cmm_cfgspace_low_addr_01_7_0_bm_23__4545) + ); + MUXF5 com_cmm_u_cmm_cfgspace_low_addr_01_7_0_23_ ( + .I0(com_cmm_u_cmm_cfgspace_low_addr_01_7_0_am_23__4546), + .I1(com_cmm_u_cmm_cfgspace_low_addr_01_7_0_bm_23__4545), + .O(com_cmm_u_cmm_cfgspace_low_addr_01[23]), + .S(com_cmm_u_cmm_cfgspace_sel_encodex_1[0]) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_am_8_.INIT = 16'h0CA0; + LUT4 com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_am_8_ ( + .I0(cfg_cfg_5072[296]), + .I1(com_cmm_msi_laddr[8]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex_1[1]), + .I3(com_cmm_u_cmm_cfgspace_sel_encodex[2]), + .O(com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_am[8]) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_bm_8_.INIT = 16'h3E0E; + LUT4 com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_bm_8_ ( + .I0(com_cmm_bar3_reg[8]), + .I1(com_cmm_u_cmm_cfgspace_sel_encodex_1[1]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex[2]), + .I3(com_cmm_u_cmm_cfgspace_x_dcap[8]), + .O(com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_bm[8]) + ); + MUXF5 com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_8_ ( + .I0(com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_am[8]), + .I1(com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_bm[8]), + .O(com_cmm_u_cmm_cfgspace_low_addr_03_q_4[8]), + .S(com_cmm_u_cmm_cfgspace_sel_encodex_1[0]) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_am_9_.INIT = 16'h0CA0; + LUT4 com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_am_9_ ( + .I0(cfg_cfg_5072[297]), + .I1(com_cmm_msi_laddr[9]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex_1[1]), + .I3(com_cmm_u_cmm_cfgspace_sel_encodex[2]), + .O(com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_am[9]) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_bm_9_.INIT = 16'h3202; + LUT4 com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_bm_9_ ( + .I0(com_cmm_bar3_reg[9]), + .I1(com_cmm_u_cmm_cfgspace_sel_encodex_1[1]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex[2]), + .I3(com_cmm_u_cmm_cfgspace_x_dcap[9]), + .O(com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_bm[9]) + ); + MUXF5 com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_9_ ( + .I0(com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_am[9]), + .I1(com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_bm[9]), + .O(com_cmm_u_cmm_cfgspace_low_addr_03_q_4[9]), + .S(com_cmm_u_cmm_cfgspace_sel_encodex_1[0]) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_am_10_.INIT = 16'h0CA0; + LUT4 com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_am_10_ ( + .I0(cfg_cfg_5072[298]), + .I1(com_cmm_msi_laddr[10]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex_1[1]), + .I3(com_cmm_u_cmm_cfgspace_sel_encodex[2]), + .O(com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_am[10]) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_bm_10_.INIT = 16'h3202; + LUT4 com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_bm_10_ ( + .I0(com_cmm_bar3_reg[10]), + .I1(com_cmm_u_cmm_cfgspace_sel_encodex_1[1]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex[2]), + .I3(com_cmm_u_cmm_cfgspace_x_dcap[10]), + .O(com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_bm[10]) + ); + MUXF5 com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_10_ ( + .I0(com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_am[10]), + .I1(com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_bm[10]), + .O(com_cmm_u_cmm_cfgspace_low_addr_03_q_4[10]), + .S(com_cmm_u_cmm_cfgspace_sel_encodex_1[0]) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_am_11_.INIT = 16'h0CA0; + LUT4 com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_am_11_ ( + .I0(cfg_cfg_5072[299]), + .I1(com_cmm_msi_laddr[11]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex_1[1]), + .I3(com_cmm_u_cmm_cfgspace_sel_encodex[2]), + .O(com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_am[11]) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_bm_11_.INIT = 16'h3202; + LUT4 com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_bm_11_ ( + .I0(com_cmm_bar3_reg[11]), + .I1(com_cmm_u_cmm_cfgspace_sel_encodex_1[1]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex[2]), + .I3(com_cmm_u_cmm_cfgspace_x_dcap[11]), + .O(com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_bm[11]) + ); + MUXF5 com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_11_ ( + .I0(com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_am[11]), + .I1(com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_bm[11]), + .O(com_cmm_u_cmm_cfgspace_low_addr_03_q_4[11]), + .S(com_cmm_u_cmm_cfgspace_sel_encodex_1[0]) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_am_12_.INIT = 16'h0CA0; + LUT4 com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_am_12_ ( + .I0(cfg_cfg_5072[300]), + .I1(com_cmm_msi_laddr[12]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex_1[1]), + .I3(com_cmm_u_cmm_cfgspace_sel_encodex[2]), + .O(com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_am[12]) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_bm_12_.INIT = 16'h3202; + LUT4 com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_bm_12_ ( + .I0(com_cmm_bar3_reg[12]), + .I1(com_cmm_u_cmm_cfgspace_sel_encodex_1[1]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex[2]), + .I3(com_cmm_u_cmm_cfgspace_x_dcap[12]), + .O(com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_bm[12]) + ); + MUXF5 com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_12_ ( + .I0(com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_am[12]), + .I1(com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_bm[12]), + .O(com_cmm_u_cmm_cfgspace_low_addr_03_q_4[12]), + .S(com_cmm_u_cmm_cfgspace_sel_encodex_1[0]) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_am_13_.INIT = 16'h0CA0; + LUT4 com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_am_13_ ( + .I0(cfg_cfg_5072[301]), + .I1(com_cmm_msi_laddr[13]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex_1[1]), + .I3(com_cmm_u_cmm_cfgspace_sel_encodex[2]), + .O(com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_am[13]) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_bm_13_.INIT = 16'h3202; + LUT4 com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_bm_13_ ( + .I0(com_cmm_bar3_reg[13]), + .I1(com_cmm_u_cmm_cfgspace_sel_encodex_1[1]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex[2]), + .I3(com_cmm_u_cmm_cfgspace_x_dcap[13]), + .O(com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_bm[13]) + ); + MUXF5 com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_13_ ( + .I0(com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_am[13]), + .I1(com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_bm[13]), + .O(com_cmm_u_cmm_cfgspace_low_addr_03_q_4[13]), + .S(com_cmm_u_cmm_cfgspace_sel_encodex_1[0]) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_am_14_.INIT = 16'h0CA0; + LUT4 com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_am_14_ ( + .I0(cfg_cfg_5072[302]), + .I1(com_cmm_msi_laddr[14]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex_1[1]), + .I3(com_cmm_u_cmm_cfgspace_sel_encodex[2]), + .O(com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_am[14]) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_bm_14_.INIT = 16'h3202; + LUT4 com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_bm_14_ ( + .I0(com_cmm_bar3_reg[14]), + .I1(com_cmm_u_cmm_cfgspace_sel_encodex_1[1]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex[2]), + .I3(com_cmm_u_cmm_cfgspace_x_dcap[14]), + .O(com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_bm[14]) + ); + MUXF5 com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_14_ ( + .I0(com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_am[14]), + .I1(com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_bm[14]), + .O(com_cmm_u_cmm_cfgspace_low_addr_03_q_4[14]), + .S(com_cmm_u_cmm_cfgspace_sel_encodex_1[0]) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_am_15_.INIT = 16'h0CA0; + LUT4 com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_am_15_ ( + .I0(cfg_cfg_5072[303]), + .I1(com_cmm_msi_laddr[15]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex_1[1]), + .I3(com_cmm_u_cmm_cfgspace_sel_encodex[2]), + .O(com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_am[15]) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_bm_15_.INIT = 16'h3202; + LUT4 com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_bm_15_ ( + .I0(com_cmm_bar3_reg[15]), + .I1(com_cmm_u_cmm_cfgspace_sel_encodex_1[1]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex[2]), + .I3(com_cmm_u_cmm_cfgspace_x_dcap[15]), + .O(com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_bm[15]) + ); + MUXF5 com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_15_ ( + .I0(com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_am[15]), + .I1(com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_bm[15]), + .O(com_cmm_u_cmm_cfgspace_low_addr_03_q_4[15]), + .S(com_cmm_u_cmm_cfgspace_sel_encodex_1[0]) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_am_16_.INIT = 16'h0CA0; + LUT4 com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_am_16_ ( + .I0(cfg_cfg_5072[304]), + .I1(com_cmm_msi_laddr[16]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex_1[1]), + .I3(com_cmm_u_cmm_cfgspace_sel_encodex[2]), + .O(com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_am[16]) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_bm_16_.INIT = 16'h3202; + LUT4 com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_bm_16_ ( + .I0(com_cmm_bar3_reg[16]), + .I1(com_cmm_u_cmm_cfgspace_sel_encodex_1[1]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex[2]), + .I3(com_cmm_u_cmm_cfgspace_x_dcap[16]), + .O(com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_bm[16]) + ); + MUXF5 com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_16_ ( + .I0(com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_am[16]), + .I1(com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_bm[16]), + .O(com_cmm_u_cmm_cfgspace_low_addr_03_q_4[16]), + .S(com_cmm_u_cmm_cfgspace_sel_encodex_1[0]) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_am_17_.INIT = 16'h0CA0; + LUT4 com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_am_17_ ( + .I0(cfg_cfg_5072[305]), + .I1(com_cmm_msi_laddr[17]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex_1[1]), + .I3(com_cmm_u_cmm_cfgspace_sel_encodex[2]), + .O(com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_am[17]) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_bm_17_.INIT = 16'h3202; + LUT4 com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_bm_17_ ( + .I0(com_cmm_bar3_reg[17]), + .I1(com_cmm_u_cmm_cfgspace_sel_encodex_1[1]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex[2]), + .I3(com_cmm_u_cmm_cfgspace_x_dcap[17]), + .O(com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_bm[17]) + ); + MUXF5 com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_17_ ( + .I0(com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_am[17]), + .I1(com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_bm[17]), + .O(com_cmm_u_cmm_cfgspace_low_addr_03_q_4[17]), + .S(com_cmm_u_cmm_cfgspace_sel_encodex_1[0]) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_am_18_.INIT = 16'h0CA0; + LUT4 com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_am_18_ ( + .I0(cfg_cfg_5072[306]), + .I1(com_cmm_msi_laddr[18]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex_1[1]), + .I3(com_cmm_u_cmm_cfgspace_sel_encodex[2]), + .O(com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_am[18]) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_bm_18_.INIT = 16'h3202; + LUT4 com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_bm_18_ ( + .I0(com_cmm_bar3_reg[18]), + .I1(com_cmm_u_cmm_cfgspace_sel_encodex_1[1]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex[2]), + .I3(com_cmm_u_cmm_cfgspace_x_dcap[18]), + .O(com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_bm[18]) + ); + MUXF5 com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_18_ ( + .I0(com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_am[18]), + .I1(com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_bm[18]), + .O(com_cmm_u_cmm_cfgspace_low_addr_03_q_4[18]), + .S(com_cmm_u_cmm_cfgspace_sel_encodex_1[0]) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_am_19_.INIT = 16'h0CA0; + LUT4 com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_am_19_ ( + .I0(cfg_cfg_5072[307]), + .I1(com_cmm_msi_laddr[19]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex_1[1]), + .I3(com_cmm_u_cmm_cfgspace_sel_encodex[2]), + .O(com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_am[19]) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_bm_19_.INIT = 16'h3202; + LUT4 com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_bm_19_ ( + .I0(com_cmm_bar3_reg[19]), + .I1(com_cmm_u_cmm_cfgspace_sel_encodex_1[1]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex[2]), + .I3(com_cmm_u_cmm_cfgspace_x_dcap[19]), + .O(com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_bm[19]) + ); + MUXF5 com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_19_ ( + .I0(com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_am[19]), + .I1(com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_bm[19]), + .O(com_cmm_u_cmm_cfgspace_low_addr_03_q_4[19]), + .S(com_cmm_u_cmm_cfgspace_sel_encodex_1[0]) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_am_20_.INIT = 16'h0CA0; + LUT4 com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_am_20_ ( + .I0(cfg_cfg_5072[308]), + .I1(com_cmm_msi_laddr[20]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex_1[1]), + .I3(com_cmm_u_cmm_cfgspace_sel_encodex[2]), + .O(com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_am[20]) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_bm_20_.INIT = 16'h3202; + LUT4 com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_bm_20_ ( + .I0(com_cmm_bar3_reg[20]), + .I1(com_cmm_u_cmm_cfgspace_sel_encodex_1[1]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex[2]), + .I3(com_cmm_u_cmm_cfgspace_x_dcap[20]), + .O(com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_bm[20]) + ); + MUXF5 com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_20_ ( + .I0(com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_am[20]), + .I1(com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_bm[20]), + .O(com_cmm_u_cmm_cfgspace_low_addr_03_q_4[20]), + .S(com_cmm_u_cmm_cfgspace_sel_encodex_1[0]) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_am_21_.INIT = 16'h0CA0; + LUT4 com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_am_21_ ( + .I0(cfg_cfg_5072[309]), + .I1(com_cmm_msi_laddr[21]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex_1[1]), + .I3(com_cmm_u_cmm_cfgspace_sel_encodex[2]), + .O(com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_am[21]) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_bm_21_.INIT = 16'h3202; + LUT4 com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_bm_21_ ( + .I0(com_cmm_bar3_reg[21]), + .I1(com_cmm_u_cmm_cfgspace_sel_encodex_1[1]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex[2]), + .I3(com_cmm_u_cmm_cfgspace_x_dcap[21]), + .O(com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_bm[21]) + ); + MUXF5 com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_21_ ( + .I0(com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_am[21]), + .I1(com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_bm[21]), + .O(com_cmm_u_cmm_cfgspace_low_addr_03_q_4[21]), + .S(com_cmm_u_cmm_cfgspace_sel_encodex_1[0]) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_am_22_.INIT = 16'h0CA0; + LUT4 com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_am_22_ ( + .I0(cfg_cfg_5072[310]), + .I1(com_cmm_msi_laddr[22]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex_1[1]), + .I3(com_cmm_u_cmm_cfgspace_sel_encodex_1[2]), + .O(com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_am[22]) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_bm_22_.INIT = 16'h3202; + LUT4 com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_bm_22_ ( + .I0(com_cmm_bar3_reg[22]), + .I1(com_cmm_u_cmm_cfgspace_sel_encodex_1[1]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex_1[2]), + .I3(com_cmm_u_cmm_cfgspace_x_dcap[22]), + .O(com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_bm[22]) + ); + MUXF5 com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_22_ ( + .I0(com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_am[22]), + .I1(com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_bm[22]), + .O(com_cmm_u_cmm_cfgspace_low_addr_03_q_4[22]), + .S(com_cmm_u_cmm_cfgspace_sel_encodex_1[0]) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_am_23_.INIT = 16'h0CA0; + LUT4 com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_am_23_ ( + .I0(cfg_cfg_5072[311]), + .I1(com_cmm_msi_laddr[23]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex_1[1]), + .I3(com_cmm_u_cmm_cfgspace_sel_encodex_1[2]), + .O(com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_am[23]) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_bm_23_.INIT = 16'h3202; + LUT4 com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_bm_23_ ( + .I0(com_cmm_bar3_reg[23]), + .I1(com_cmm_u_cmm_cfgspace_sel_encodex_1[1]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex_1[2]), + .I3(com_cmm_u_cmm_cfgspace_x_dcap[23]), + .O(com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_bm[23]) + ); + MUXF5 com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_23_ ( + .I0(com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_am[23]), + .I1(com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_bm[23]), + .O(com_cmm_u_cmm_cfgspace_low_addr_03_q_4[23]), + .S(com_cmm_u_cmm_cfgspace_sel_encodex_1[0]) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_am_24_.INIT = 16'h0CA0; + LUT4 com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_am_24_ ( + .I0(cfg_cfg_5072[312]), + .I1(com_cmm_msi_laddr[24]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex_1[1]), + .I3(com_cmm_u_cmm_cfgspace_sel_encodex_1[2]), + .O(com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_am[24]) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_bm_24_.INIT = 16'h3202; + LUT4 com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_bm_24_ ( + .I0(com_cmm_bar3_reg[24]), + .I1(com_cmm_u_cmm_cfgspace_sel_encodex_1[1]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex_1[2]), + .I3(com_cmm_u_cmm_cfgspace_x_dcap[24]), + .O(com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_bm[24]) + ); + MUXF5 com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_24_ ( + .I0(com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_am[24]), + .I1(com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_bm[24]), + .O(com_cmm_u_cmm_cfgspace_low_addr_03_q_4[24]), + .S(com_cmm_u_cmm_cfgspace_sel_encodex_1[0]) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_am_25_.INIT = 16'h0CA0; + LUT4 com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_am_25_ ( + .I0(cfg_cfg_5072[313]), + .I1(com_cmm_msi_laddr[25]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex_1[1]), + .I3(com_cmm_u_cmm_cfgspace_sel_encodex_1[2]), + .O(com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_am[25]) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_bm_25_.INIT = 16'h3202; + LUT4 com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_bm_25_ ( + .I0(com_cmm_bar3_reg[25]), + .I1(com_cmm_u_cmm_cfgspace_sel_encodex_1[1]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex_1[2]), + .I3(com_cmm_u_cmm_cfgspace_x_dcap[25]), + .O(com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_bm[25]) + ); + MUXF5 com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_25_ ( + .I0(com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_am[25]), + .I1(com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_bm[25]), + .O(com_cmm_u_cmm_cfgspace_low_addr_03_q_4[25]), + .S(com_cmm_u_cmm_cfgspace_sel_encodex_1[0]) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_am_26_.INIT = 16'h0CA0; + LUT4 com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_am_26_ ( + .I0(cfg_cfg_5072[314]), + .I1(com_cmm_msi_laddr[26]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex_1[1]), + .I3(com_cmm_u_cmm_cfgspace_sel_encodex_1[2]), + .O(com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_am[26]) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_bm_26_.INIT = 16'h3202; + LUT4 com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_bm_26_ ( + .I0(com_cmm_bar3_reg[26]), + .I1(com_cmm_u_cmm_cfgspace_sel_encodex_1[1]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex_1[2]), + .I3(com_cmm_u_cmm_cfgspace_x_dcap[26]), + .O(com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_bm[26]) + ); + MUXF5 com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_26_ ( + .I0(com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_am[26]), + .I1(com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_bm[26]), + .O(com_cmm_u_cmm_cfgspace_low_addr_03_q_4[26]), + .S(com_cmm_u_cmm_cfgspace_sel_encodex_1[0]) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_am_27_.INIT = 16'h0CA0; + LUT4 com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_am_27_ ( + .I0(cfg_cfg_5072[315]), + .I1(com_cmm_msi_laddr[27]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex_1[1]), + .I3(com_cmm_u_cmm_cfgspace_sel_encodex_1[2]), + .O(com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_am[27]) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_bm_27_.INIT = 16'h3202; + LUT4 com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_bm_27_ ( + .I0(com_cmm_bar3_reg[27]), + .I1(com_cmm_u_cmm_cfgspace_sel_encodex_1[1]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex_1[2]), + .I3(com_cmm_u_cmm_cfgspace_x_dcap[27]), + .O(com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_bm[27]) + ); + MUXF5 com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_27_ ( + .I0(com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_am[27]), + .I1(com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_bm[27]), + .O(com_cmm_u_cmm_cfgspace_low_addr_03_q_4[27]), + .S(com_cmm_u_cmm_cfgspace_sel_encodex_1[0]) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_am_28_.INIT = 16'h0CA0; + LUT4 com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_am_28_ ( + .I0(cfg_cfg_5072[316]), + .I1(com_cmm_msi_laddr[28]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex_1[1]), + .I3(com_cmm_u_cmm_cfgspace_sel_encodex_1[2]), + .O(com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_am[28]) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_bm_28_.INIT = 16'h3202; + LUT4 com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_bm_28_ ( + .I0(com_cmm_bar3_reg[28]), + .I1(com_cmm_u_cmm_cfgspace_sel_encodex_1[1]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex_1[2]), + .I3(com_cmm_u_cmm_cfgspace_x_dcap[28]), + .O(com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_bm[28]) + ); + MUXF5 com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_28_ ( + .I0(com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_am[28]), + .I1(com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_bm[28]), + .O(com_cmm_u_cmm_cfgspace_low_addr_03_q_4[28]), + .S(com_cmm_u_cmm_cfgspace_sel_encodex_1[0]) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_am_29_.INIT = 16'h0CA0; + LUT4 com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_am_29_ ( + .I0(cfg_cfg_5072[317]), + .I1(com_cmm_msi_laddr[29]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex_1[1]), + .I3(com_cmm_u_cmm_cfgspace_sel_encodex_1[2]), + .O(com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_am[29]) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_bm_29_.INIT = 16'h3202; + LUT4 com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_bm_29_ ( + .I0(com_cmm_bar3_reg[29]), + .I1(com_cmm_u_cmm_cfgspace_sel_encodex_1[1]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex_1[2]), + .I3(com_cmm_u_cmm_cfgspace_x_dcap[29]), + .O(com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_bm[29]) + ); + MUXF5 com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_29_ ( + .I0(com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_am[29]), + .I1(com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_bm[29]), + .O(com_cmm_u_cmm_cfgspace_low_addr_03_q_4[29]), + .S(com_cmm_u_cmm_cfgspace_sel_encodex_1[0]) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_am_30_.INIT = 16'h0CA0; + LUT4 com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_am_30_ ( + .I0(cfg_cfg_5072[318]), + .I1(com_cmm_msi_laddr[30]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex_1[1]), + .I3(com_cmm_u_cmm_cfgspace_sel_encodex_1[2]), + .O(com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_am[30]) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_bm_30_.INIT = 16'h3202; + LUT4 com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_bm_30_ ( + .I0(com_cmm_bar3_reg[30]), + .I1(com_cmm_u_cmm_cfgspace_sel_encodex_1[1]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex_1[2]), + .I3(com_cmm_u_cmm_cfgspace_x_dcap[30]), + .O(com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_bm[30]) + ); + MUXF5 com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_30_ ( + .I0(com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_am[30]), + .I1(com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_bm[30]), + .O(com_cmm_u_cmm_cfgspace_low_addr_03_q_4[30]), + .S(com_cmm_u_cmm_cfgspace_sel_encodex_1[0]) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_am_31_.INIT = 16'h0CA0; + LUT4 com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_am_31_ ( + .I0(cfg_cfg_5072[319]), + .I1(com_cmm_msi_laddr[31]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex_1[1]), + .I3(com_cmm_u_cmm_cfgspace_sel_encodex_1[2]), + .O(com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_am[31]) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_bm_31_.INIT = 16'h3202; + LUT4 com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_bm_31_ ( + .I0(com_cmm_bar3_reg[31]), + .I1(com_cmm_u_cmm_cfgspace_sel_encodex_1[1]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex_1[2]), + .I3(com_cmm_u_cmm_cfgspace_x_dcap[31]), + .O(com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_bm[31]) + ); + MUXF5 com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_31_ ( + .I0(com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_am[31]), + .I1(com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_bm[31]), + .O(com_cmm_u_cmm_cfgspace_low_addr_03_q_4[31]), + .S(com_cmm_u_cmm_cfgspace_sel_encodex_1[0]) + ); + defparam com_cmm_u_cmm_cfgspace_next_state_0_i_0_0_a2_1_0_.INIT = 16'h1F00; + LUT4 com_cmm_u_cmm_cfgspace_next_state_0_i_0_0_a2_1_0_ ( + .I0(com_cmm_N_48846_i), + .I1(com_cmm_cfg_rd), + .I2(com_cmm_state_1_), + .I3(com_cmm_u_cmm_cfgspace_state_0__4782), + .O(com_cmm_u_cmm_cfgspace_N_42538_1) + ); + defparam com_cmm_u_cmm_cfgspace_x3gio_decodepipe_h_sel_0x_3_0_0_a3_i_o2.INIT = 4'h2; + LUT2 com_cmm_u_cmm_cfgspace_x3gio_decodepipe_h_sel_0x_3_0_0_a3_i_o2 ( + .I0(com_cmm_u_cmm_cfgspace_N_42634_1), + .I1(cfg_dwaddr_5069[6]), + .O(com_cmm_u_cmm_cfgspace_N_48930_i) + ); + defparam com_cmm_u_cmm_cfgspace_xrom_reg_0_sqmuxa_0_a2_0_a2_0_a2.INIT = 16'h8000; + LUT4 com_cmm_u_cmm_cfgspace_xrom_reg_0_sqmuxa_0_a2_0_a2_0_a2 ( + .I0(com_cmm_u_cmm_cfgspace_N_48848_i), + .I1(cfg_cfg_5072[320]), + .I2(com_cmm_u_cmm_cfgspace_sel_3x_4756), + .I3(com_cmm_u_cmm_cfgspace_sel_x0_4760), + .O(com_cmm_u_cmm_cfgspace_xrom_reg_0_sqmuxa) + ); + defparam com_cmm_u_cmm_cfgspace_sel_encodex_en_3_i_0_a2_2.INIT = 16'h0002; + LUT4 com_cmm_u_cmm_cfgspace_sel_encodex_en_3_i_0_a2_2 ( + .I0(com_cmm_u_cmm_cfgspace_N_42634_1), + .I1(cfg_dwaddr_5069[2]), + .I2(cfg_dwaddr_5069[3]), + .I3(cfg_dwaddr_5069[4]), + .O(com_cmm_u_cmm_cfgspace_N_42634) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_00_i_0_0_31_32088.INIT = 8'h51; + LUT3 com_cmm_u_cmm_cfgspace_low_addr_00_i_0_0_31_32088 ( + .I0(com_cmm_u_cmm_cfgspace_N_50144), + .I1(com_cmm_u_cmm_cfgspace_N_50498), + .I2(com_cmm_bar0_reg_31_), + .O(com_cmm_u_cmm_cfgspace_low_addr_00_i_0_0_31_32088_4635) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_00_i_30_32093.INIT = 8'h51; + LUT3 com_cmm_u_cmm_cfgspace_low_addr_00_i_30_32093 ( + .I0(com_cmm_u_cmm_cfgspace_N_50144), + .I1(com_cmm_u_cmm_cfgspace_N_50498), + .I2(com_cmm_bar0_reg_30_), + .O(com_cmm_u_cmm_cfgspace_low_addr_00_i_30_32093_4637) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_00_i_28_32098.INIT = 8'h51; + LUT3 com_cmm_u_cmm_cfgspace_low_addr_00_i_28_32098 ( + .I0(com_cmm_u_cmm_cfgspace_N_50144), + .I1(com_cmm_u_cmm_cfgspace_N_50498), + .I2(com_cmm_bar0_reg_28_), + .O(com_cmm_u_cmm_cfgspace_low_addr_00_i_28_32098_4639) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_00_i_26_32103.INIT = 8'h51; + LUT3 com_cmm_u_cmm_cfgspace_low_addr_00_i_26_32103 ( + .I0(com_cmm_u_cmm_cfgspace_N_50144), + .I1(com_cmm_u_cmm_cfgspace_N_50498), + .I2(com_cmm_bar0_reg_26_), + .O(com_cmm_u_cmm_cfgspace_low_addr_00_i_26_32103_4641) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_00_i_25_32108.INIT = 8'h51; + LUT3 com_cmm_u_cmm_cfgspace_low_addr_00_i_25_32108 ( + .I0(com_cmm_u_cmm_cfgspace_N_50144), + .I1(com_cmm_u_cmm_cfgspace_N_50498), + .I2(com_cmm_bar0_reg_25_), + .O(com_cmm_u_cmm_cfgspace_low_addr_00_i_25_32108_4643) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_00_i_24_32113.INIT = 8'h51; + LUT3 com_cmm_u_cmm_cfgspace_low_addr_00_i_24_32113 ( + .I0(com_cmm_u_cmm_cfgspace_N_50144), + .I1(com_cmm_u_cmm_cfgspace_N_50498), + .I2(com_cmm_bar0_reg_24_), + .O(com_cmm_u_cmm_cfgspace_low_addr_00_i_24_32113_4645) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_00_i_23_32118.INIT = 8'h51; + LUT3 com_cmm_u_cmm_cfgspace_low_addr_00_i_23_32118 ( + .I0(com_cmm_u_cmm_cfgspace_N_50144), + .I1(com_cmm_u_cmm_cfgspace_N_50498), + .I2(com_cmm_bar0_reg_23_), + .O(com_cmm_u_cmm_cfgspace_low_addr_00_i_23_32118_4647) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_00_i_22_32123.INIT = 8'h51; + LUT3 com_cmm_u_cmm_cfgspace_low_addr_00_i_22_32123 ( + .I0(com_cmm_u_cmm_cfgspace_N_50144), + .I1(com_cmm_u_cmm_cfgspace_N_50498), + .I2(com_cmm_bar0_reg_22_), + .O(com_cmm_u_cmm_cfgspace_low_addr_00_i_22_32123_4649) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_00_i_20_32128.INIT = 8'h51; + LUT3 com_cmm_u_cmm_cfgspace_low_addr_00_i_20_32128 ( + .I0(com_cmm_u_cmm_cfgspace_N_50144), + .I1(com_cmm_u_cmm_cfgspace_N_50498), + .I2(com_cmm_bar0_reg_20_), + .O(com_cmm_u_cmm_cfgspace_low_addr_00_i_20_32128_4651) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_00_0_0_i_15_32133.INIT = 8'h51; + LUT3_L com_cmm_u_cmm_cfgspace_low_addr_00_0_0_i_15_32133 ( + .I0(com_cmm_u_cmm_cfgspace_N_50453), + .I1(com_cmm_u_cmm_cfgspace_N_50498), + .I2(com_cmm_bar0_reg_15_), + .LO(com_cmm_u_cmm_cfgspace_low_addr_00_0_0_i_15_32133_4632) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_00_i_0_3_27_.INIT = 16'hF531; + LUT4_L com_cmm_u_cmm_cfgspace_low_addr_00_i_0_3_27_ ( + .I0(com_cmm_u_cmm_cfgspace_N_50451), + .I1(com_cmm_u_cmm_cfgspace_N_50498), + .I2(cfg_cfg_5072[27]), + .I3(com_cmm_bar0_reg_27_), + .LO(com_cmm_u_cmm_cfgspace_low_addr_00_i_0_3[27]) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_00_0_0_0_0_1_14_.INIT = 16'h5070; + LUT4 com_cmm_u_cmm_cfgspace_low_addr_00_0_0_0_0_1_14_ ( + .I0(com_cmm_u_cmm_cfgspace_N_50495), + .I1(cfg_cfg_5072[14]), + .I2(com_cmm_u_cmm_cfgspace_low_addr_00_0_0_0_0_0[14]), + .I3(com_cmm_u_cmm_cfgspace_sel_encodex_1[2]), + .O(com_cmm_u_cmm_cfgspace_low_addr_00_0_0_0_0_1[14]) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_00_0_0_0_0_2_14_.INIT = 16'h57F7; + LUT4 com_cmm_u_cmm_cfgspace_low_addr_00_0_0_0_0_2_14_ ( + .I0(com_cmm_u_cmm_cfgspace_N_50489), + .I1(com_cmm_bar0_reg_14_), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex_1[1]), + .I3(com_cmm_xrom_reg_14_), + .O(com_cmm_u_cmm_cfgspace_low_addr_00_0_0_0_0_2[14]) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_00_i_0_i_0_1_11_.INIT = 16'h5070; + LUT4 com_cmm_u_cmm_cfgspace_low_addr_00_i_0_i_0_1_11_ ( + .I0(com_cmm_u_cmm_cfgspace_N_50495), + .I1(cfg_cfg_5072[11]), + .I2(com_cmm_u_cmm_cfgspace_low_addr_00_i_0_i_0_0[11]), + .I3(com_cmm_u_cmm_cfgspace_sel_encodex_1[2]), + .O(com_cmm_u_cmm_cfgspace_low_addr_00_i_0_i_0_1[11]) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_00_i_0_i_0_2_11_.INIT = 16'h57F7; + LUT4 com_cmm_u_cmm_cfgspace_low_addr_00_i_0_i_0_2_11_ ( + .I0(com_cmm_u_cmm_cfgspace_N_50489), + .I1(com_cmm_bar0_reg_11_), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex_1[1]), + .I3(com_cmm_xrom_reg_11_), + .O(com_cmm_u_cmm_cfgspace_low_addr_00_i_0_i_0_2[11]) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_00_0_0_0_13_.INIT = 16'h135F; + LUT4 com_cmm_u_cmm_cfgspace_low_addr_00_0_0_0_13_ ( + .I0(com_cmm_u_cmm_cfgspace_N_48992), + .I1(com_cmm_u_cmm_cfgspace_N_50457), + .I2(com_cmm_u_cmm_cfgspace_N_50490), + .I3(com_cmm_xrom_reg_13_), + .O(com_cmm_u_cmm_cfgspace_low_addr_00_0_0_0[13]) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_00_0_0_1_13_.INIT = 16'h153F; + LUT4_L com_cmm_u_cmm_cfgspace_low_addr_00_0_0_1_13_ ( + .I0(com_cmm_u_cmm_cfgspace_N_50455), + .I1(com_cmm_u_cmm_cfgspace_N_50498), + .I2(com_cmm_bar0_reg_13_), + .I3(com_cmm_msi_haddr[13]), + .LO(com_cmm_u_cmm_cfgspace_low_addr_00_0_0_1[13]) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_00_0_0_0_0_12_.INIT = 16'h135F; + LUT4 com_cmm_u_cmm_cfgspace_low_addr_00_0_0_0_0_12_ ( + .I0(com_cmm_u_cmm_cfgspace_N_48993), + .I1(com_cmm_u_cmm_cfgspace_N_50457), + .I2(com_cmm_u_cmm_cfgspace_N_50490), + .I3(com_cmm_xrom_reg_12_), + .O(com_cmm_u_cmm_cfgspace_low_addr_00_0_0_0_0[12]) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_00_0_0_0_1_12_.INIT = 16'h153F; + LUT4_L com_cmm_u_cmm_cfgspace_low_addr_00_0_0_0_1_12_ ( + .I0(com_cmm_u_cmm_cfgspace_N_50455), + .I1(com_cmm_u_cmm_cfgspace_N_50498), + .I2(com_cmm_bar0_reg_12_), + .I3(com_cmm_msi_haddr[12]), + .LO(com_cmm_u_cmm_cfgspace_low_addr_00_0_0_0_1[12]) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_00_i_i_0_2_29_.INIT = 16'h153F; + LUT4_L com_cmm_u_cmm_cfgspace_low_addr_00_i_i_0_2_29_ ( + .I0(com_cmm_u_cmm_cfgspace_N_50455), + .I1(com_cmm_u_cmm_cfgspace_N_50498), + .I2(com_cmm_bar0_reg_29_), + .I3(com_cmm_msi_haddr[29]), + .LO(com_cmm_u_cmm_cfgspace_low_addr_00_i_i_0_2_29__4674) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_00_0_0_10_.INIT = 16'h153F; + LUT4 com_cmm_u_cmm_cfgspace_low_addr_00_0_0_10_ ( + .I0(com_cmm_u_cmm_cfgspace_N_50455), + .I1(com_cmm_u_cmm_cfgspace_N_50498), + .I2(com_cmm_bar0_reg_10_), + .I3(com_cmm_msi_haddr[10]), + .O(com_cmm_u_cmm_cfgspace_low_addr_00_0_0_10__4709) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_00_0_1_10_.INIT = 16'h135F; + LUT4_L com_cmm_u_cmm_cfgspace_low_addr_00_0_1_10_ ( + .I0(com_cmm_u_cmm_cfgspace_N_50451), + .I1(com_cmm_u_cmm_cfgspace_N_50456), + .I2(cfg_cfg_5072[10]), + .I3(NlwRenamedSig_OI_cfg_dcommand[10]), + .LO(com_cmm_u_cmm_cfgspace_low_addr_00_0_1_10__4708) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_00_0_0_6_.INIT = 16'h153F; + LUT4 com_cmm_u_cmm_cfgspace_low_addr_00_0_0_6_ ( + .I0(com_cmm_u_cmm_cfgspace_N_50455), + .I1(com_cmm_u_cmm_cfgspace_N_50498), + .I2(com_cmm_bar0_reg_6_), + .I3(com_cmm_msi_haddr[6]), + .O(com_cmm_u_cmm_cfgspace_low_addr_00_0_0_6__4721) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_00_0_1_6_.INIT = 16'h135F; + LUT4_L com_cmm_u_cmm_cfgspace_low_addr_00_0_1_6_ ( + .I0(com_cmm_u_cmm_cfgspace_N_50451), + .I1(com_cmm_u_cmm_cfgspace_N_50456), + .I2(cfg_cfg_5072[6]), + .I3(NlwRenamedSig_OI_cfg_dcommand[6]), + .LO(com_cmm_u_cmm_cfgspace_low_addr_00_0_1_6__4720) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_00_0_0_3_.INIT = 16'h153F; + LUT4 com_cmm_u_cmm_cfgspace_low_addr_00_0_0_3_ ( + .I0(com_cmm_u_cmm_cfgspace_N_50455), + .I1(com_cmm_u_cmm_cfgspace_N_50498), + .I2(com_cmm_u_cmm_cfgspace_bar0_reg[3]), + .I3(com_cmm_msi_haddr[3]), + .O(com_cmm_u_cmm_cfgspace_low_addr_00_0_0_3__4730) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_00_0_1_3_.INIT = 16'h135F; + LUT4_L com_cmm_u_cmm_cfgspace_low_addr_00_0_1_3_ ( + .I0(com_cmm_u_cmm_cfgspace_N_50451), + .I1(com_cmm_u_cmm_cfgspace_N_50456), + .I2(cfg_cfg_5072[3]), + .I3(NlwRenamedSig_OI_cfg_dcommand[3]), + .LO(com_cmm_u_cmm_cfgspace_low_addr_00_0_1_3__4729) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_00_0_0_5_.INIT = 16'h153F; + LUT4 com_cmm_u_cmm_cfgspace_low_addr_00_0_0_5_ ( + .I0(com_cmm_u_cmm_cfgspace_N_50455), + .I1(com_cmm_u_cmm_cfgspace_N_50498), + .I2(com_cmm_bar0_reg_5_), + .I3(com_cmm_msi_haddr[5]), + .O(com_cmm_u_cmm_cfgspace_low_addr_00_0_0_5__4724) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_00_0_1_5_.INIT = 16'h135F; + LUT4_L com_cmm_u_cmm_cfgspace_low_addr_00_0_1_5_ ( + .I0(com_cmm_u_cmm_cfgspace_N_50451), + .I1(com_cmm_u_cmm_cfgspace_N_50456), + .I2(cfg_cfg_5072[5]), + .I3(NlwRenamedSig_OI_cfg_dcommand[5]), + .LO(com_cmm_u_cmm_cfgspace_low_addr_00_0_1_5__4723) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_00_0_0_9_.INIT = 16'h153F; + LUT4 com_cmm_u_cmm_cfgspace_low_addr_00_0_0_9_ ( + .I0(com_cmm_u_cmm_cfgspace_N_50455), + .I1(com_cmm_u_cmm_cfgspace_N_50498), + .I2(com_cmm_bar0_reg_9_), + .I3(com_cmm_msi_haddr[9]), + .O(com_cmm_u_cmm_cfgspace_low_addr_00_0_0_9__4712) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_00_0_1_9_.INIT = 16'h135F; + LUT4_L com_cmm_u_cmm_cfgspace_low_addr_00_0_1_9_ ( + .I0(com_cmm_u_cmm_cfgspace_N_50451), + .I1(com_cmm_u_cmm_cfgspace_N_50456), + .I2(cfg_cfg_5072[9]), + .I3(NlwRenamedSig_OI_cfg_dcommand[9]), + .LO(com_cmm_u_cmm_cfgspace_low_addr_00_0_1_9__4711) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_00_0_0_7_.INIT = 16'h153F; + LUT4 com_cmm_u_cmm_cfgspace_low_addr_00_0_0_7_ ( + .I0(com_cmm_u_cmm_cfgspace_N_50455), + .I1(com_cmm_u_cmm_cfgspace_N_50498), + .I2(com_cmm_bar0_reg_7_), + .I3(com_cmm_msi_haddr[7]), + .O(com_cmm_u_cmm_cfgspace_low_addr_00_0_0_7__4718) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_00_0_1_7_.INIT = 16'h135F; + LUT4_L com_cmm_u_cmm_cfgspace_low_addr_00_0_1_7_ ( + .I0(com_cmm_u_cmm_cfgspace_N_50451), + .I1(com_cmm_u_cmm_cfgspace_N_50456), + .I2(cfg_cfg_5072[7]), + .I3(NlwRenamedSig_OI_cfg_dcommand[7]), + .LO(com_cmm_u_cmm_cfgspace_low_addr_00_0_1_7__4717) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_00_0_0_8_.INIT = 16'h153F; + LUT4 com_cmm_u_cmm_cfgspace_low_addr_00_0_0_8_ ( + .I0(com_cmm_u_cmm_cfgspace_N_50455), + .I1(com_cmm_u_cmm_cfgspace_N_50498), + .I2(com_cmm_bar0_reg_8_), + .I3(com_cmm_msi_haddr[8]), + .O(com_cmm_u_cmm_cfgspace_low_addr_00_0_0_8__4715) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_00_0_1_8_.INIT = 16'h135F; + LUT4_L com_cmm_u_cmm_cfgspace_low_addr_00_0_1_8_ ( + .I0(com_cmm_u_cmm_cfgspace_N_50451), + .I1(com_cmm_u_cmm_cfgspace_N_50456), + .I2(cfg_cfg_5072[8]), + .I3(NlwRenamedSig_OI_cfg_dcommand[8]), + .LO(com_cmm_u_cmm_cfgspace_low_addr_00_0_1_8__4714) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_00_0_0_2_.INIT = 16'h153F; + LUT4 com_cmm_u_cmm_cfgspace_low_addr_00_0_0_2_ ( + .I0(com_cmm_u_cmm_cfgspace_N_50455), + .I1(com_cmm_u_cmm_cfgspace_N_50498), + .I2(com_cmm_bar0_reg_2_), + .I3(com_cmm_msi_haddr[2]), + .O(com_cmm_u_cmm_cfgspace_low_addr_00_0_0_2__4733) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_00_0_1_2_.INIT = 16'h135F; + LUT4_L com_cmm_u_cmm_cfgspace_low_addr_00_0_1_2_ ( + .I0(com_cmm_u_cmm_cfgspace_N_50451), + .I1(com_cmm_u_cmm_cfgspace_N_50456), + .I2(cfg_cfg_5072[2]), + .I3(NlwRenamedSig_OI_cfg_dcommand[2]), + .LO(com_cmm_u_cmm_cfgspace_low_addr_00_0_1_2__4732) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_00_0_0_4_.INIT = 16'h153F; + LUT4 com_cmm_u_cmm_cfgspace_low_addr_00_0_0_4_ ( + .I0(com_cmm_u_cmm_cfgspace_N_50455), + .I1(com_cmm_u_cmm_cfgspace_N_50498), + .I2(com_cmm_bar0_reg_4_), + .I3(com_cmm_msi_haddr[4]), + .O(com_cmm_u_cmm_cfgspace_low_addr_00_0_0_4__4727) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_00_0_1_4_.INIT = 16'h135F; + LUT4_L com_cmm_u_cmm_cfgspace_low_addr_00_0_1_4_ ( + .I0(com_cmm_u_cmm_cfgspace_N_50451), + .I1(com_cmm_u_cmm_cfgspace_N_50456), + .I2(cfg_cfg_5072[4]), + .I3(NlwRenamedSig_OI_cfg_dcommand[4]), + .LO(com_cmm_u_cmm_cfgspace_low_addr_00_0_1_4__4726) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_00_0_0_21_.INIT = 16'h153F; + LUT4 com_cmm_u_cmm_cfgspace_low_addr_00_0_0_21_ ( + .I0(com_cmm_u_cmm_cfgspace_N_50457), + .I1(com_cmm_u_cmm_cfgspace_N_50458), + .I2(cfg_cfg_5072[517]), + .I3(com_cmm_xrom_reg_21_), + .O(com_cmm_u_cmm_cfgspace_low_addr_00_0_0_21__4686) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_00_0_1_21_.INIT = 16'h153F; + LUT4 com_cmm_u_cmm_cfgspace_low_addr_00_0_1_21_ ( + .I0(com_cmm_u_cmm_cfgspace_N_50455), + .I1(com_cmm_u_cmm_cfgspace_N_50498), + .I2(com_cmm_bar0_reg_21_), + .I3(com_cmm_msi_haddr[21]), + .O(com_cmm_u_cmm_cfgspace_low_addr_00_0_1_21__4685) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_00_0_2_21_.INIT = 16'h135F; + LUT4_L com_cmm_u_cmm_cfgspace_low_addr_00_0_2_21_ ( + .I0(com_cmm_u_cmm_cfgspace_N_50451), + .I1(com_cmm_u_cmm_cfgspace_N_50456), + .I2(cfg_cfg_5072[21]), + .I3(NlwRenamedSig_OI_cfg_dstatus_5_), + .LO(com_cmm_u_cmm_cfgspace_low_addr_00_0_2_21__4684) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_00_i_i_0_0_17_.INIT = 16'h153F; + LUT4 com_cmm_u_cmm_cfgspace_low_addr_00_i_i_0_0_17_ ( + .I0(com_cmm_u_cmm_cfgspace_N_50457), + .I1(com_cmm_u_cmm_cfgspace_N_50458), + .I2(cfg_cfg_5072[513]), + .I3(com_cmm_xrom_reg_17_), + .O(com_cmm_u_cmm_cfgspace_low_addr_00_i_i_0_0_17__4699) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_00_i_i_0_1_17_.INIT = 16'h153F; + LUT4 com_cmm_u_cmm_cfgspace_low_addr_00_i_i_0_1_17_ ( + .I0(com_cmm_u_cmm_cfgspace_N_50455), + .I1(com_cmm_u_cmm_cfgspace_N_50498), + .I2(com_cmm_bar0_reg_17_), + .I3(com_cmm_msi_haddr[17]), + .O(com_cmm_u_cmm_cfgspace_low_addr_00_i_i_0_1_17__4698) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_00_i_i_0_2_17_.INIT = 16'h135F; + LUT4_L com_cmm_u_cmm_cfgspace_low_addr_00_i_i_0_2_17_ ( + .I0(com_cmm_u_cmm_cfgspace_N_50451), + .I1(com_cmm_u_cmm_cfgspace_N_50456), + .I2(cfg_cfg_5072[17]), + .I3(NlwRenamedSig_OI_cfg_dstatus_1_), + .LO(com_cmm_u_cmm_cfgspace_low_addr_00_i_i_0_2_17__4697) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_00_0_0_18_.INIT = 16'h153F; + LUT4 com_cmm_u_cmm_cfgspace_low_addr_00_0_0_18_ ( + .I0(com_cmm_u_cmm_cfgspace_N_50457), + .I1(com_cmm_u_cmm_cfgspace_N_50458), + .I2(cfg_cfg_5072[514]), + .I3(com_cmm_xrom_reg_18_), + .O(com_cmm_u_cmm_cfgspace_low_addr_00_0_0_18__4695) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_00_0_1_18_.INIT = 16'h153F; + LUT4 com_cmm_u_cmm_cfgspace_low_addr_00_0_1_18_ ( + .I0(com_cmm_u_cmm_cfgspace_N_50455), + .I1(com_cmm_u_cmm_cfgspace_N_50498), + .I2(com_cmm_bar0_reg_18_), + .I3(com_cmm_msi_haddr[18]), + .O(com_cmm_u_cmm_cfgspace_low_addr_00_0_1_18__4694) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_00_0_2_18_.INIT = 16'h135F; + LUT4_L com_cmm_u_cmm_cfgspace_low_addr_00_0_2_18_ ( + .I0(com_cmm_u_cmm_cfgspace_N_50451), + .I1(com_cmm_u_cmm_cfgspace_N_50456), + .I2(cfg_cfg_5072[18]), + .I3(NlwRenamedSig_OI_cfg_dstatus_2_), + .LO(com_cmm_u_cmm_cfgspace_low_addr_00_0_2_18__4693) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_00_i_i_0_0_19_.INIT = 16'h153F; + LUT4 com_cmm_u_cmm_cfgspace_low_addr_00_i_i_0_0_19_ ( + .I0(com_cmm_u_cmm_cfgspace_N_50457), + .I1(com_cmm_u_cmm_cfgspace_N_50458), + .I2(cfg_cfg_5072[515]), + .I3(com_cmm_xrom_reg_19_), + .O(com_cmm_u_cmm_cfgspace_low_addr_00_i_i_0_0_19__4691) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_00_i_i_0_1_19_.INIT = 16'h153F; + LUT4 com_cmm_u_cmm_cfgspace_low_addr_00_i_i_0_1_19_ ( + .I0(com_cmm_u_cmm_cfgspace_N_50455), + .I1(com_cmm_u_cmm_cfgspace_N_50498), + .I2(com_cmm_bar0_reg_19_), + .I3(com_cmm_msi_haddr[19]), + .O(com_cmm_u_cmm_cfgspace_low_addr_00_i_i_0_1_19__4690) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_00_i_i_0_2_19_.INIT = 16'h135F; + LUT4_L com_cmm_u_cmm_cfgspace_low_addr_00_i_i_0_2_19_ ( + .I0(com_cmm_u_cmm_cfgspace_N_50451), + .I1(com_cmm_u_cmm_cfgspace_N_50456), + .I2(cfg_cfg_5072[19]), + .I3(NlwRenamedSig_OI_cfg_dstatus_3_), + .LO(com_cmm_u_cmm_cfgspace_low_addr_00_i_i_0_2_19__4689) + ); + defparam com_cmm_u_cmm_cfgspace_x3gio_decodepipe_l_sel_x4_3_i_0_0_o2.INIT = 16'h3210; + LUT4 com_cmm_u_cmm_cfgspace_x3gio_decodepipe_l_sel_x4_3_i_0_0_o2 ( + .I0(com_cmm_u_cmm_cfgspace_N_48842_i), + .I1(com_cmm_u_cmm_cfgspace_N_50484), + .I2(cfg_dwaddr_5069[0]), + .I3(com_cmm_cfg_addr[0]), + .O(com_cmm_u_cmm_cfgspace_N_48876_i) + ); + defparam com_cmm_u_cmm_cfgspace_x3gio_decodepipe_l_sel_x0_3_i_0_0_o2.INIT = 16'h0123; + LUT4 com_cmm_u_cmm_cfgspace_x3gio_decodepipe_l_sel_x0_3_i_0_0_o2 ( + .I0(com_cmm_u_cmm_cfgspace_N_48842_i), + .I1(com_cmm_u_cmm_cfgspace_N_50484), + .I2(cfg_dwaddr_5069[0]), + .I3(com_cmm_cfg_addr[0]), + .O(com_cmm_u_cmm_cfgspace_N_48875_i) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_01_7_0_am_1_.INIT = 16'h0CAA; + LUT4 com_cmm_u_cmm_cfgspace_low_addr_01_7_0_am_1_ ( + .I0(com_cmm_u_cmm_cfgspace_N_3935), + .I1(com_cmm_pme_pmcsr[1]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex_1[1]), + .I3(com_cmm_u_cmm_cfgspace_sel_encodex_1[2]), + .O(com_cmm_u_cmm_cfgspace_low_addr_01_7_0_am_1__4548) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_01_7_0_bm_1_.INIT = 16'hAA0C; + LUT4 com_cmm_u_cmm_cfgspace_low_addr_01_7_0_bm_1_ ( + .I0(com_cmm_u_cmm_cfgspace_N_4063), + .I1(com_cmm_bar1_reg[1]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex_1[1]), + .I3(com_cmm_u_cmm_cfgspace_sel_encodex_1[2]), + .O(com_cmm_u_cmm_cfgspace_low_addr_01_7_0_bm_1__4547) + ); + MUXF5 com_cmm_u_cmm_cfgspace_low_addr_01_7_0_1_ ( + .I0(com_cmm_u_cmm_cfgspace_low_addr_01_7_0_am_1__4548), + .I1(com_cmm_u_cmm_cfgspace_low_addr_01_7_0_bm_1__4547), + .O(com_cmm_u_cmm_cfgspace_low_addr_01[1]), + .S(com_cmm_u_cmm_cfgspace_sel_encodex_1[0]) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_01_7_0_am_2_.INIT = 16'h00CA; + LUT4 com_cmm_u_cmm_cfgspace_low_addr_01_7_0_am_2_ ( + .I0(NlwRenamedSig_OI_cfg_command_2_), + .I1(com_cmm_bar5_reg[2]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex_1[1]), + .I3(com_cmm_u_cmm_cfgspace_sel_encodex_1[2]), + .O(com_cmm_u_cmm_cfgspace_low_addr_01_7_0_am_2__4550) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_01_7_0_bm_2_.INIT = 16'hAA0C; + LUT4 com_cmm_u_cmm_cfgspace_low_addr_01_7_0_bm_2_ ( + .I0(com_cmm_u_cmm_cfgspace_N_4064), + .I1(com_cmm_bar1_reg[2]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex_1[1]), + .I3(com_cmm_u_cmm_cfgspace_sel_encodex_1[2]), + .O(com_cmm_u_cmm_cfgspace_low_addr_01_7_0_bm_2__4549) + ); + MUXF5 com_cmm_u_cmm_cfgspace_low_addr_01_7_0_2_ ( + .I0(com_cmm_u_cmm_cfgspace_low_addr_01_7_0_am_2__4550), + .I1(com_cmm_u_cmm_cfgspace_low_addr_01_7_0_bm_2__4549), + .O(com_cmm_u_cmm_cfgspace_low_addr_01[2]), + .S(com_cmm_u_cmm_cfgspace_sel_encodex_1[0]) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_01_7_0_bm_3_.INIT = 16'hAA0C; + LUT4 com_cmm_u_cmm_cfgspace_low_addr_01_7_0_bm_3_ ( + .I0(com_cmm_u_cmm_cfgspace_N_4065), + .I1(com_cmm_bar1_reg[3]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex_1[1]), + .I3(com_cmm_u_cmm_cfgspace_sel_encodex_1[2]), + .O(com_cmm_u_cmm_cfgspace_low_addr_01_7_0_bm_3__4551) + ); + MUXF5 com_cmm_u_cmm_cfgspace_low_addr_01_7_0_3_ ( + .I0(com_cmm_u_cmm_cfgspace_low_addr_01_7_0_am_0[3]), + .I1(com_cmm_u_cmm_cfgspace_low_addr_01_7_0_bm_3__4551), + .O(com_cmm_u_cmm_cfgspace_low_addr_01[3]), + .S(com_cmm_u_cmm_cfgspace_sel_encodex_1[0]) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_01_7_0_am_4_.INIT = 16'hC808; + LUT4 com_cmm_u_cmm_cfgspace_low_addr_01_7_0_am_4_ ( + .I0(com_cmm_bar5_reg[4]), + .I1(com_cmm_u_cmm_cfgspace_sel_encodex_1[1]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex_1[2]), + .I3(com_cmm_u_cmm_cfgspace_x_lcap[0]), + .O(com_cmm_u_cmm_cfgspace_low_addr_01_7_0_am_4__4553) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_01_7_0_bm_4_.INIT = 16'hAA0C; + LUT4 com_cmm_u_cmm_cfgspace_low_addr_01_7_0_bm_4_ ( + .I0(com_cmm_u_cmm_cfgspace_N_4066), + .I1(com_cmm_bar1_reg[4]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex_1[1]), + .I3(com_cmm_u_cmm_cfgspace_sel_encodex_1[2]), + .O(com_cmm_u_cmm_cfgspace_low_addr_01_7_0_bm_4__4552) + ); + MUXF5 com_cmm_u_cmm_cfgspace_low_addr_01_7_0_4_ ( + .I0(com_cmm_u_cmm_cfgspace_low_addr_01_7_0_am_4__4553), + .I1(com_cmm_u_cmm_cfgspace_low_addr_01_7_0_bm_4__4552), + .O(com_cmm_u_cmm_cfgspace_low_addr_01[4]), + .S(com_cmm_u_cmm_cfgspace_sel_encodex_1[0]) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_01_7_0_am_5_.INIT = 8'h08; + LUT3 com_cmm_u_cmm_cfgspace_low_addr_01_7_0_am_5_ ( + .I0(com_cmm_bar5_reg[5]), + .I1(com_cmm_u_cmm_cfgspace_sel_encodex_1[1]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex_1[2]), + .O(com_cmm_u_cmm_cfgspace_low_addr_01_7_0_am_5__4555) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_01_7_0_bm_5_.INIT = 16'hAA0C; + LUT4 com_cmm_u_cmm_cfgspace_low_addr_01_7_0_bm_5_ ( + .I0(com_cmm_u_cmm_cfgspace_N_4067), + .I1(com_cmm_bar1_reg[5]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex_1[1]), + .I3(com_cmm_u_cmm_cfgspace_sel_encodex_1[2]), + .O(com_cmm_u_cmm_cfgspace_low_addr_01_7_0_bm_5__4554) + ); + MUXF5 com_cmm_u_cmm_cfgspace_low_addr_01_7_0_5_ ( + .I0(com_cmm_u_cmm_cfgspace_low_addr_01_7_0_am_5__4555), + .I1(com_cmm_u_cmm_cfgspace_low_addr_01_7_0_bm_5__4554), + .O(com_cmm_u_cmm_cfgspace_low_addr_01[5]), + .S(com_cmm_u_cmm_cfgspace_sel_encodex_1[0]) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_01_7_0_am_6_.INIT = 16'h00CA; + LUT4 com_cmm_u_cmm_cfgspace_low_addr_01_7_0_am_6_ ( + .I0(NlwRenamedSig_OI_cfg_command_6_), + .I1(com_cmm_bar5_reg[6]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex_1[1]), + .I3(com_cmm_u_cmm_cfgspace_sel_encodex_1[2]), + .O(com_cmm_u_cmm_cfgspace_low_addr_01_7_0_am_6__4557) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_01_7_0_bm_6_.INIT = 16'hAAFC; + LUT4 com_cmm_u_cmm_cfgspace_low_addr_01_7_0_bm_6_ ( + .I0(com_cmm_u_cmm_cfgspace_N_4068), + .I1(com_cmm_bar1_reg[6]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex_1[1]), + .I3(com_cmm_u_cmm_cfgspace_sel_encodex_1[2]), + .O(com_cmm_u_cmm_cfgspace_low_addr_01_7_0_bm_6__4556) + ); + MUXF5 com_cmm_u_cmm_cfgspace_low_addr_01_7_0_6_ ( + .I0(com_cmm_u_cmm_cfgspace_low_addr_01_7_0_am_6__4557), + .I1(com_cmm_u_cmm_cfgspace_low_addr_01_7_0_bm_6__4556), + .O(com_cmm_u_cmm_cfgspace_low_addr_01[6]), + .S(com_cmm_u_cmm_cfgspace_sel_encodex_1[0]) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_01_7_0_am_7_.INIT = 8'h08; + LUT3 com_cmm_u_cmm_cfgspace_low_addr_01_7_0_am_7_ ( + .I0(com_cmm_bar5_reg[7]), + .I1(com_cmm_u_cmm_cfgspace_sel_encodex_1[1]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex_1[2]), + .O(com_cmm_u_cmm_cfgspace_low_addr_01_7_0_am_7__4559) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_01_7_0_bm_7_.INIT = 16'hAA0C; + LUT4 com_cmm_u_cmm_cfgspace_low_addr_01_7_0_bm_7_ ( + .I0(com_cmm_u_cmm_cfgspace_N_4069), + .I1(com_cmm_bar1_reg[7]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex_2[1]), + .I3(com_cmm_u_cmm_cfgspace_sel_encodex_1[2]), + .O(com_cmm_u_cmm_cfgspace_low_addr_01_7_0_bm_7__4558) + ); + MUXF5 com_cmm_u_cmm_cfgspace_low_addr_01_7_0_7_ ( + .I0(com_cmm_u_cmm_cfgspace_low_addr_01_7_0_am_7__4559), + .I1(com_cmm_u_cmm_cfgspace_low_addr_01_7_0_bm_7__4558), + .O(com_cmm_u_cmm_cfgspace_low_addr_01[7]), + .S(com_cmm_u_cmm_cfgspace_sel_encodex_1[0]) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_01_7_0_am_8_.INIT = 16'h0CAA; + LUT4 com_cmm_u_cmm_cfgspace_low_addr_01_7_0_am_8_ ( + .I0(com_cmm_u_cmm_cfgspace_N_3942), + .I1(com_cmm_u_cmm_cfgspace_pme_pmcsr[8]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex_2[1]), + .I3(com_cmm_u_cmm_cfgspace_sel_encodex_1[2]), + .O(com_cmm_u_cmm_cfgspace_low_addr_01_7_0_am_8__4561) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_01_7_0_bm_8_.INIT = 16'hAA0C; + LUT4 com_cmm_u_cmm_cfgspace_low_addr_01_7_0_bm_8_ ( + .I0(com_cmm_u_cmm_cfgspace_N_4070), + .I1(com_cmm_bar1_reg[8]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex_2[1]), + .I3(com_cmm_u_cmm_cfgspace_sel_encodex_1[2]), + .O(com_cmm_u_cmm_cfgspace_low_addr_01_7_0_bm_8__4560) + ); + MUXF5 com_cmm_u_cmm_cfgspace_low_addr_01_7_0_8_ ( + .I0(com_cmm_u_cmm_cfgspace_low_addr_01_7_0_am_8__4561), + .I1(com_cmm_u_cmm_cfgspace_low_addr_01_7_0_bm_8__4560), + .O(com_cmm_u_cmm_cfgspace_low_addr_01[8]), + .S(com_cmm_u_cmm_cfgspace_sel_encodex_1[0]) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_01_7_0_am_9_.INIT = 16'h0CA0; + LUT4 com_cmm_u_cmm_cfgspace_low_addr_01_7_0_am_9_ ( + .I0(com_cmm_bar5_reg[9]), + .I1(com_cmm_u_cmm_cfgspace_pme_pmcsr[9]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex_2[1]), + .I3(com_cmm_u_cmm_cfgspace_sel_encodex_1[2]), + .O(com_cmm_u_cmm_cfgspace_low_addr_01_7_0_am_9__4563) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_01_7_0_bm_9_.INIT = 16'hAA0C; + LUT4 com_cmm_u_cmm_cfgspace_low_addr_01_7_0_bm_9_ ( + .I0(com_cmm_u_cmm_cfgspace_N_4071), + .I1(com_cmm_bar1_reg[9]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex_2[1]), + .I3(com_cmm_u_cmm_cfgspace_sel_encodex_1[2]), + .O(com_cmm_u_cmm_cfgspace_low_addr_01_7_0_bm_9__4562) + ); + MUXF5 com_cmm_u_cmm_cfgspace_low_addr_01_7_0_9_ ( + .I0(com_cmm_u_cmm_cfgspace_low_addr_01_7_0_am_9__4563), + .I1(com_cmm_u_cmm_cfgspace_low_addr_01_7_0_bm_9__4562), + .O(com_cmm_u_cmm_cfgspace_low_addr_01[9]), + .S(com_cmm_u_cmm_cfgspace_sel_encodex_1[0]) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_01_7_0_am_11_.INIT = 16'hAAC0; + LUT4 com_cmm_u_cmm_cfgspace_low_addr_01_7_0_am_11_ ( + .I0(com_cmm_u_cmm_cfgspace_N_3977), + .I1(com_cmm_bar5_reg[11]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex_2[1]), + .I3(com_cmm_u_cmm_cfgspace_sel_encodex_1[2]), + .O(com_cmm_u_cmm_cfgspace_low_addr_01_7_0_am_11__4565) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_01_7_0_bm_11_.INIT = 16'hAA0C; + LUT4 com_cmm_u_cmm_cfgspace_low_addr_01_7_0_bm_11_ ( + .I0(com_cmm_u_cmm_cfgspace_N_4073), + .I1(com_cmm_bar1_reg[11]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex_2[1]), + .I3(com_cmm_u_cmm_cfgspace_sel_encodex_1[2]), + .O(com_cmm_u_cmm_cfgspace_low_addr_01_7_0_bm_11__4564) + ); + MUXF5 com_cmm_u_cmm_cfgspace_low_addr_01_7_0_11_ ( + .I0(com_cmm_u_cmm_cfgspace_low_addr_01_7_0_am_11__4565), + .I1(com_cmm_u_cmm_cfgspace_low_addr_01_7_0_bm_11__4564), + .O(com_cmm_u_cmm_cfgspace_low_addr_01[11]), + .S(com_cmm_u_cmm_cfgspace_sel_encodex_1[0]) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_01_7_0_am_12_.INIT = 16'hAAC0; + LUT4 com_cmm_u_cmm_cfgspace_low_addr_01_7_0_am_12_ ( + .I0(com_cmm_u_cmm_cfgspace_N_3978), + .I1(com_cmm_bar5_reg[12]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex_2[1]), + .I3(com_cmm_u_cmm_cfgspace_sel_encodex_1[2]), + .O(com_cmm_u_cmm_cfgspace_low_addr_01_7_0_am_12__4567) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_01_7_0_bm_12_.INIT = 16'hAA0C; + LUT4 com_cmm_u_cmm_cfgspace_low_addr_01_7_0_bm_12_ ( + .I0(com_cmm_u_cmm_cfgspace_N_4074), + .I1(com_cmm_bar1_reg[12]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex_2[1]), + .I3(com_cmm_u_cmm_cfgspace_sel_encodex_1[2]), + .O(com_cmm_u_cmm_cfgspace_low_addr_01_7_0_bm_12__4566) + ); + MUXF5 com_cmm_u_cmm_cfgspace_low_addr_01_7_0_12_ ( + .I0(com_cmm_u_cmm_cfgspace_low_addr_01_7_0_am_12__4567), + .I1(com_cmm_u_cmm_cfgspace_low_addr_01_7_0_bm_12__4566), + .O(com_cmm_u_cmm_cfgspace_low_addr_01[12]), + .S(com_cmm_u_cmm_cfgspace_sel_encodex_1[0]) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_01_7_0_am_13_.INIT = 16'hAAC0; + LUT4 com_cmm_u_cmm_cfgspace_low_addr_01_7_0_am_13_ ( + .I0(com_cmm_u_cmm_cfgspace_N_3979), + .I1(com_cmm_bar5_reg[13]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex_2[1]), + .I3(com_cmm_u_cmm_cfgspace_sel_encodex_1[2]), + .O(com_cmm_u_cmm_cfgspace_low_addr_01_7_0_am_13__4569) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_01_7_0_bm_13_.INIT = 16'hAA0C; + LUT4 com_cmm_u_cmm_cfgspace_low_addr_01_7_0_bm_13_ ( + .I0(com_cmm_u_cmm_cfgspace_N_4075), + .I1(com_cmm_bar1_reg[13]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex_2[1]), + .I3(com_cmm_u_cmm_cfgspace_sel_encodex_1[2]), + .O(com_cmm_u_cmm_cfgspace_low_addr_01_7_0_bm_13__4568) + ); + MUXF5 com_cmm_u_cmm_cfgspace_low_addr_01_7_0_13_ ( + .I0(com_cmm_u_cmm_cfgspace_low_addr_01_7_0_am_13__4569), + .I1(com_cmm_u_cmm_cfgspace_low_addr_01_7_0_bm_13__4568), + .O(com_cmm_u_cmm_cfgspace_low_addr_01[13]), + .S(com_cmm_u_cmm_cfgspace_sel_encodex_1[0]) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_01_7_0_am_14_.INIT = 16'hAAC0; + LUT4 com_cmm_u_cmm_cfgspace_low_addr_01_7_0_am_14_ ( + .I0(com_cmm_u_cmm_cfgspace_N_3980), + .I1(com_cmm_bar5_reg[14]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex_2[1]), + .I3(com_cmm_u_cmm_cfgspace_sel_encodex_1[2]), + .O(com_cmm_u_cmm_cfgspace_low_addr_01_7_0_am_14__4571) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_01_7_0_bm_14_.INIT = 16'hAA0C; + LUT4 com_cmm_u_cmm_cfgspace_low_addr_01_7_0_bm_14_ ( + .I0(com_cmm_u_cmm_cfgspace_N_4076), + .I1(com_cmm_bar1_reg[14]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex_2[1]), + .I3(com_cmm_u_cmm_cfgspace_sel_encodex_1[2]), + .O(com_cmm_u_cmm_cfgspace_low_addr_01_7_0_bm_14__4570) + ); + MUXF5 com_cmm_u_cmm_cfgspace_low_addr_01_7_0_14_ ( + .I0(com_cmm_u_cmm_cfgspace_low_addr_01_7_0_am_14__4571), + .I1(com_cmm_u_cmm_cfgspace_low_addr_01_7_0_bm_14__4570), + .O(com_cmm_u_cmm_cfgspace_low_addr_01[14]), + .S(com_cmm_u_cmm_cfgspace_sel_encodex_1[0]) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_01_7_0_am_15_.INIT = 16'hAAC0; + LUT4 com_cmm_u_cmm_cfgspace_low_addr_01_7_0_am_15_ ( + .I0(com_cmm_u_cmm_cfgspace_N_3981), + .I1(com_cmm_bar5_reg[15]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex_2[1]), + .I3(com_cmm_u_cmm_cfgspace_sel_encodex_1[2]), + .O(com_cmm_u_cmm_cfgspace_low_addr_01_7_0_am_15__4573) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_01_7_0_bm_15_.INIT = 16'hAA0C; + LUT4 com_cmm_u_cmm_cfgspace_low_addr_01_7_0_bm_15_ ( + .I0(com_cmm_u_cmm_cfgspace_N_4077), + .I1(com_cmm_bar1_reg[15]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex_2[1]), + .I3(com_cmm_u_cmm_cfgspace_sel_encodex_1[2]), + .O(com_cmm_u_cmm_cfgspace_low_addr_01_7_0_bm_15__4572) + ); + MUXF5 com_cmm_u_cmm_cfgspace_low_addr_01_7_0_15_ ( + .I0(com_cmm_u_cmm_cfgspace_low_addr_01_7_0_am_15__4573), + .I1(com_cmm_u_cmm_cfgspace_low_addr_01_7_0_bm_15__4572), + .O(com_cmm_u_cmm_cfgspace_low_addr_01[15]), + .S(com_cmm_u_cmm_cfgspace_sel_encodex_1[0]) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_01_7_0_am_19_.INIT = 16'hC0AA; + LUT4 com_cmm_u_cmm_cfgspace_low_addr_01_7_0_am_19_ ( + .I0(com_cmm_u_cmm_cfgspace_N_3953), + .I1(cfg_cfg_5072[419]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex_2[1]), + .I3(com_cmm_u_cmm_cfgspace_sel_encodex_1[2]), + .O(com_cmm_u_cmm_cfgspace_low_addr_01_7_0_am_19__4575) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_01_7_0_bm_19_.INIT = 16'hA00C; + LUT4 com_cmm_u_cmm_cfgspace_low_addr_01_7_0_bm_19_ ( + .I0(cfg_cfg_5072[675]), + .I1(com_cmm_bar1_reg[19]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex_2[1]), + .I3(com_cmm_u_cmm_cfgspace_sel_encodex_1[2]), + .O(com_cmm_u_cmm_cfgspace_low_addr_01_7_0_bm_19__4574) + ); + MUXF5 com_cmm_u_cmm_cfgspace_low_addr_01_7_0_19_ ( + .I0(com_cmm_u_cmm_cfgspace_low_addr_01_7_0_am_19__4575), + .I1(com_cmm_u_cmm_cfgspace_low_addr_01_7_0_bm_19__4574), + .O(com_cmm_u_cmm_cfgspace_low_addr_01[19]), + .S(com_cmm_u_cmm_cfgspace_sel_encodex_1[0]) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_02_7_0_am_0_.INIT = 16'hCFAA; + LUT4 com_cmm_u_cmm_cfgspace_low_addr_02_7_0_am_0_ ( + .I0(com_cmm_u_cmm_cfgspace_N_4206), + .I1(NlwRenamedSig_OI_cfg_lcommand_0_), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex_2[1]), + .I3(com_cmm_u_cmm_cfgspace_sel_encodex_1[2]), + .O(com_cmm_u_cmm_cfgspace_low_addr_02_7_0_am_0__4577) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_02_7_0_bm_0_.INIT = 16'hAA0C; + LUT4 com_cmm_u_cmm_cfgspace_low_addr_02_7_0_bm_0_ ( + .I0(com_cmm_u_cmm_cfgspace_N_4334), + .I1(com_cmm_bar2_reg[0]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex_2[1]), + .I3(com_cmm_u_cmm_cfgspace_sel_encodex_1[2]), + .O(com_cmm_u_cmm_cfgspace_low_addr_02_7_0_bm_0__4576) + ); + MUXF5 com_cmm_u_cmm_cfgspace_low_addr_02_7_0_0_ ( + .I0(com_cmm_u_cmm_cfgspace_low_addr_02_7_0_am_0__4577), + .I1(com_cmm_u_cmm_cfgspace_low_addr_02_7_0_bm_0__4576), + .O(com_cmm_u_cmm_cfgspace_low_addr_02[0]), + .S(com_cmm_u_cmm_cfgspace_sel_encodex_1[0]) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_02_7_0_am_1_.INIT = 16'hC0AA; + LUT4 com_cmm_u_cmm_cfgspace_low_addr_02_7_0_am_1_ ( + .I0(com_cmm_u_cmm_cfgspace_N_4207), + .I1(NlwRenamedSig_OI_cfg_lcommand_1_), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex_2[1]), + .I3(com_cmm_u_cmm_cfgspace_sel_encodex_1[2]), + .O(com_cmm_u_cmm_cfgspace_low_addr_02_7_0_am_1__4579) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_02_7_0_bm_1_.INIT = 16'hAA0C; + LUT4 com_cmm_u_cmm_cfgspace_low_addr_02_7_0_bm_1_ ( + .I0(com_cmm_u_cmm_cfgspace_N_4335), + .I1(com_cmm_bar2_reg[1]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex_2[1]), + .I3(com_cmm_u_cmm_cfgspace_sel_encodex_1[2]), + .O(com_cmm_u_cmm_cfgspace_low_addr_02_7_0_bm_1__4578) + ); + MUXF5 com_cmm_u_cmm_cfgspace_low_addr_02_7_0_1_ ( + .I0(com_cmm_u_cmm_cfgspace_low_addr_02_7_0_am_1__4579), + .I1(com_cmm_u_cmm_cfgspace_low_addr_02_7_0_bm_1__4578), + .O(com_cmm_u_cmm_cfgspace_low_addr_02[1]), + .S(com_cmm_u_cmm_cfgspace_sel_encodex_1[0]) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_02_7_0_am_2_.INIT = 16'h0FCA; + LUT4 com_cmm_u_cmm_cfgspace_low_addr_02_7_0_am_2_ ( + .I0(cfg_cfg_5072[34]), + .I1(cfg_cfg_5072[258]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex_2[1]), + .I3(com_cmm_u_cmm_cfgspace_sel_encodex_1[2]), + .O(com_cmm_u_cmm_cfgspace_low_addr_02_7_0_am_2__4581) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_02_7_0_bm_2_.INIT = 16'hAA0C; + LUT4 com_cmm_u_cmm_cfgspace_low_addr_02_7_0_bm_2_ ( + .I0(com_cmm_u_cmm_cfgspace_N_4336), + .I1(com_cmm_bar2_reg[2]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex_2[1]), + .I3(com_cmm_u_cmm_cfgspace_sel_encodex_1[2]), + .O(com_cmm_u_cmm_cfgspace_low_addr_02_7_0_bm_2__4580) + ); + MUXF5 com_cmm_u_cmm_cfgspace_low_addr_02_7_0_2_ ( + .I0(com_cmm_u_cmm_cfgspace_low_addr_02_7_0_am_2__4581), + .I1(com_cmm_u_cmm_cfgspace_low_addr_02_7_0_bm_2__4580), + .O(com_cmm_u_cmm_cfgspace_low_addr_02[2]), + .S(com_cmm_u_cmm_cfgspace_sel_encodex_1[0]) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_02_7_0_am_3_.INIT = 16'hC0AA; + LUT4 com_cmm_u_cmm_cfgspace_low_addr_02_7_0_am_3_ ( + .I0(com_cmm_u_cmm_cfgspace_N_4209), + .I1(NlwRenamedSig_OI_cfg_lcommand_3_), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex_2[1]), + .I3(com_cmm_u_cmm_cfgspace_sel_encodex_1[2]), + .O(com_cmm_u_cmm_cfgspace_low_addr_02_7_0_am_3__4583) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_02_7_0_bm_3_.INIT = 16'hAA0C; + LUT4 com_cmm_u_cmm_cfgspace_low_addr_02_7_0_bm_3_ ( + .I0(com_cmm_u_cmm_cfgspace_N_4337), + .I1(com_cmm_bar2_reg[3]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex_2[1]), + .I3(com_cmm_u_cmm_cfgspace_sel_encodex_1[2]), + .O(com_cmm_u_cmm_cfgspace_low_addr_02_7_0_bm_3__4582) + ); + MUXF5 com_cmm_u_cmm_cfgspace_low_addr_02_7_0_3_ ( + .I0(com_cmm_u_cmm_cfgspace_low_addr_02_7_0_am_3__4583), + .I1(com_cmm_u_cmm_cfgspace_low_addr_02_7_0_bm_3__4582), + .O(com_cmm_u_cmm_cfgspace_low_addr_02[3]), + .S(com_cmm_u_cmm_cfgspace_sel_encodex_1[0]) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_02_7_0_am_4_.INIT = 16'h00CA; + LUT4 com_cmm_u_cmm_cfgspace_low_addr_02_7_0_am_4_ ( + .I0(cfg_cfg_5072[36]), + .I1(cfg_cfg_5072[260]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex_2[1]), + .I3(com_cmm_u_cmm_cfgspace_sel_encodex_1[2]), + .O(com_cmm_u_cmm_cfgspace_low_addr_02_7_0_am_4__4585) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_02_7_0_bm_4_.INIT = 16'hAA0C; + LUT4 com_cmm_u_cmm_cfgspace_low_addr_02_7_0_bm_4_ ( + .I0(com_cmm_u_cmm_cfgspace_N_4338), + .I1(com_cmm_bar2_reg[4]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex_2[1]), + .I3(com_cmm_u_cmm_cfgspace_sel_encodex_1[2]), + .O(com_cmm_u_cmm_cfgspace_low_addr_02_7_0_bm_4__4584) + ); + MUXF5 com_cmm_u_cmm_cfgspace_low_addr_02_7_0_4_ ( + .I0(com_cmm_u_cmm_cfgspace_low_addr_02_7_0_am_4__4585), + .I1(com_cmm_u_cmm_cfgspace_low_addr_02_7_0_bm_4__4584), + .O(com_cmm_u_cmm_cfgspace_low_addr_02[4]), + .S(com_cmm_u_cmm_cfgspace_sel_encodex_1[0]) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_02_7_0_am_5_.INIT = 16'h00CA; + LUT4 com_cmm_u_cmm_cfgspace_low_addr_02_7_0_am_5_ ( + .I0(cfg_cfg_5072[37]), + .I1(cfg_cfg_5072[261]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex_2[1]), + .I3(com_cmm_u_cmm_cfgspace_sel_encodex_1[2]), + .O(com_cmm_u_cmm_cfgspace_low_addr_02_7_0_am_5__4587) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_02_7_0_bm_5_.INIT = 16'hAA0C; + LUT4 com_cmm_u_cmm_cfgspace_low_addr_02_7_0_bm_5_ ( + .I0(com_cmm_u_cmm_cfgspace_N_4339), + .I1(com_cmm_bar2_reg[5]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex_2[1]), + .I3(com_cmm_u_cmm_cfgspace_sel_encodex_1[2]), + .O(com_cmm_u_cmm_cfgspace_low_addr_02_7_0_bm_5__4586) + ); + MUXF5 com_cmm_u_cmm_cfgspace_low_addr_02_7_0_5_ ( + .I0(com_cmm_u_cmm_cfgspace_low_addr_02_7_0_am_5__4587), + .I1(com_cmm_u_cmm_cfgspace_low_addr_02_7_0_bm_5__4586), + .O(com_cmm_u_cmm_cfgspace_low_addr_02[5]), + .S(com_cmm_u_cmm_cfgspace_sel_encodex_1[0]) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_02_7_0_am_6_.INIT = 16'hC0AA; + LUT4 com_cmm_u_cmm_cfgspace_low_addr_02_7_0_am_6_ ( + .I0(com_cmm_u_cmm_cfgspace_N_4212), + .I1(NlwRenamedSig_OI_cfg_lcommand_6_), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex_2[1]), + .I3(com_cmm_u_cmm_cfgspace_sel_encodex_1[2]), + .O(com_cmm_u_cmm_cfgspace_low_addr_02_7_0_am_6__4589) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_02_7_0_bm_6_.INIT = 16'hAA0C; + LUT4 com_cmm_u_cmm_cfgspace_low_addr_02_7_0_bm_6_ ( + .I0(com_cmm_u_cmm_cfgspace_N_4340), + .I1(com_cmm_bar2_reg[6]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex_2[1]), + .I3(com_cmm_u_cmm_cfgspace_sel_encodex_1[2]), + .O(com_cmm_u_cmm_cfgspace_low_addr_02_7_0_bm_6__4588) + ); + MUXF5 com_cmm_u_cmm_cfgspace_low_addr_02_7_0_6_ ( + .I0(com_cmm_u_cmm_cfgspace_low_addr_02_7_0_am_6__4589), + .I1(com_cmm_u_cmm_cfgspace_low_addr_02_7_0_bm_6__4588), + .O(com_cmm_u_cmm_cfgspace_low_addr_02[6]), + .S(com_cmm_u_cmm_cfgspace_sel_encodex_1[0]) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_02_7_0_am_17_.INIT = 16'h00CA; + LUT4 com_cmm_u_cmm_cfgspace_low_addr_02_7_0_am_17_ ( + .I0(cfg_cfg_5072[49]), + .I1(cfg_cfg_5072[273]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex_2[1]), + .I3(com_cmm_u_cmm_cfgspace_sel_encodex_1[2]), + .O(com_cmm_u_cmm_cfgspace_low_addr_02_7_0_am_17__4591) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_02_7_0_bm_17_.INIT = 16'hAA0C; + LUT4 com_cmm_u_cmm_cfgspace_low_addr_02_7_0_bm_17_ ( + .I0(com_cmm_u_cmm_cfgspace_N_4351), + .I1(com_cmm_bar2_reg[17]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex_2[1]), + .I3(com_cmm_u_cmm_cfgspace_sel_encodex_1[2]), + .O(com_cmm_u_cmm_cfgspace_low_addr_02_7_0_bm_17__4590) + ); + MUXF5 com_cmm_u_cmm_cfgspace_low_addr_02_7_0_17_ ( + .I0(com_cmm_u_cmm_cfgspace_low_addr_02_7_0_am_17__4591), + .I1(com_cmm_u_cmm_cfgspace_low_addr_02_7_0_bm_17__4590), + .O(com_cmm_u_cmm_cfgspace_low_addr_02[17]), + .S(com_cmm_u_cmm_cfgspace_sel_encodex_1[0]) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_02_7_0_am_18_.INIT = 16'h00CA; + LUT4 com_cmm_u_cmm_cfgspace_low_addr_02_7_0_am_18_ ( + .I0(cfg_cfg_5072[50]), + .I1(cfg_cfg_5072[274]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex_2[1]), + .I3(com_cmm_u_cmm_cfgspace_sel_encodex_1[2]), + .O(com_cmm_u_cmm_cfgspace_low_addr_02_7_0_am_18__4593) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_02_7_0_bm_18_.INIT = 16'hAA0C; + LUT4 com_cmm_u_cmm_cfgspace_low_addr_02_7_0_bm_18_ ( + .I0(com_cmm_u_cmm_cfgspace_N_4352), + .I1(com_cmm_bar2_reg[18]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex_2[1]), + .I3(com_cmm_u_cmm_cfgspace_sel_encodex_1[2]), + .O(com_cmm_u_cmm_cfgspace_low_addr_02_7_0_bm_18__4592) + ); + MUXF5 com_cmm_u_cmm_cfgspace_low_addr_02_7_0_18_ ( + .I0(com_cmm_u_cmm_cfgspace_low_addr_02_7_0_am_18__4593), + .I1(com_cmm_u_cmm_cfgspace_low_addr_02_7_0_bm_18__4592), + .O(com_cmm_u_cmm_cfgspace_low_addr_02[18]), + .S(com_cmm_u_cmm_cfgspace_sel_encodex_1[0]) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_02_7_0_am_19_.INIT = 16'h00CA; + LUT4 com_cmm_u_cmm_cfgspace_low_addr_02_7_0_am_19_ ( + .I0(cfg_cfg_5072[51]), + .I1(cfg_cfg_5072[275]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex_2[1]), + .I3(com_cmm_u_cmm_cfgspace_sel_encodex_1[2]), + .O(com_cmm_u_cmm_cfgspace_low_addr_02_7_0_am_19__4595) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_02_7_0_bm_19_.INIT = 16'hAA0C; + LUT4 com_cmm_u_cmm_cfgspace_low_addr_02_7_0_bm_19_ ( + .I0(com_cmm_u_cmm_cfgspace_N_4353), + .I1(com_cmm_bar2_reg[19]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex_2[1]), + .I3(com_cmm_u_cmm_cfgspace_sel_encodex_1[2]), + .O(com_cmm_u_cmm_cfgspace_low_addr_02_7_0_bm_19__4594) + ); + MUXF5 com_cmm_u_cmm_cfgspace_low_addr_02_7_0_19_ ( + .I0(com_cmm_u_cmm_cfgspace_low_addr_02_7_0_am_19__4595), + .I1(com_cmm_u_cmm_cfgspace_low_addr_02_7_0_bm_19__4594), + .O(com_cmm_u_cmm_cfgspace_low_addr_02[19]), + .S(com_cmm_u_cmm_cfgspace_sel_encodex_1[0]) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_02_7_0_am_20_.INIT = 16'hC0AA; + LUT4 com_cmm_u_cmm_cfgspace_low_addr_02_7_0_am_20_ ( + .I0(com_cmm_u_cmm_cfgspace_N_4226), + .I1(NlwRenamedSig_OI_cfg_lstatus_4_), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex_2[1]), + .I3(com_cmm_u_cmm_cfgspace_sel_encodex_1[2]), + .O(com_cmm_u_cmm_cfgspace_low_addr_02_7_0_am_20__4597) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_02_7_0_bm_20_.INIT = 16'hAA0C; + LUT4 com_cmm_u_cmm_cfgspace_low_addr_02_7_0_bm_20_ ( + .I0(com_cmm_u_cmm_cfgspace_N_4354), + .I1(com_cmm_bar2_reg[20]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex_2[1]), + .I3(com_cmm_u_cmm_cfgspace_sel_encodex_1[2]), + .O(com_cmm_u_cmm_cfgspace_low_addr_02_7_0_bm_20__4596) + ); + MUXF5 com_cmm_u_cmm_cfgspace_low_addr_02_7_0_20_ ( + .I0(com_cmm_u_cmm_cfgspace_low_addr_02_7_0_am_20__4597), + .I1(com_cmm_u_cmm_cfgspace_low_addr_02_7_0_bm_20__4596), + .O(com_cmm_u_cmm_cfgspace_low_addr_02[20]), + .S(com_cmm_u_cmm_cfgspace_sel_encodex_1[0]) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_02_7_0_am_21_.INIT = 16'h00CA; + LUT4 com_cmm_u_cmm_cfgspace_low_addr_02_7_0_am_21_ ( + .I0(cfg_cfg_5072[53]), + .I1(cfg_cfg_5072[277]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex_2[1]), + .I3(com_cmm_u_cmm_cfgspace_sel_encodex_2[2]), + .O(com_cmm_u_cmm_cfgspace_low_addr_02_7_0_am_21__4599) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_02_7_0_bm_21_.INIT = 16'hAA0C; + LUT4 com_cmm_u_cmm_cfgspace_low_addr_02_7_0_bm_21_ ( + .I0(com_cmm_u_cmm_cfgspace_N_4355), + .I1(com_cmm_bar2_reg[21]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex_2[1]), + .I3(com_cmm_u_cmm_cfgspace_sel_encodex_2[2]), + .O(com_cmm_u_cmm_cfgspace_low_addr_02_7_0_bm_21__4598) + ); + MUXF5 com_cmm_u_cmm_cfgspace_low_addr_02_7_0_21_ ( + .I0(com_cmm_u_cmm_cfgspace_low_addr_02_7_0_am_21__4599), + .I1(com_cmm_u_cmm_cfgspace_low_addr_02_7_0_bm_21__4598), + .O(com_cmm_u_cmm_cfgspace_low_addr_02[21]), + .S(com_cmm_u_cmm_cfgspace_sel_encodex_1[0]) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_02_7_0_am_22_.INIT = 16'h00CA; + LUT4 com_cmm_u_cmm_cfgspace_low_addr_02_7_0_am_22_ ( + .I0(cfg_cfg_5072[54]), + .I1(cfg_cfg_5072[278]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex_2[1]), + .I3(com_cmm_u_cmm_cfgspace_sel_encodex_2[2]), + .O(com_cmm_u_cmm_cfgspace_low_addr_02_7_0_am_22__4601) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_02_7_0_bm_22_.INIT = 16'hAA0C; + LUT4 com_cmm_u_cmm_cfgspace_low_addr_02_7_0_bm_22_ ( + .I0(com_cmm_u_cmm_cfgspace_N_4356), + .I1(com_cmm_bar2_reg[22]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex_2[1]), + .I3(com_cmm_u_cmm_cfgspace_sel_encodex_2[2]), + .O(com_cmm_u_cmm_cfgspace_low_addr_02_7_0_bm_22__4600) + ); + MUXF5 com_cmm_u_cmm_cfgspace_low_addr_02_7_0_22_ ( + .I0(com_cmm_u_cmm_cfgspace_low_addr_02_7_0_am_22__4601), + .I1(com_cmm_u_cmm_cfgspace_low_addr_02_7_0_bm_22__4600), + .O(com_cmm_u_cmm_cfgspace_low_addr_02[22]), + .S(com_cmm_u_cmm_cfgspace_sel_encodex[0]) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_02_7_0_am_23_.INIT = 16'h0FCA; + LUT4 com_cmm_u_cmm_cfgspace_low_addr_02_7_0_am_23_ ( + .I0(cfg_cfg_5072[55]), + .I1(cfg_cfg_5072[279]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex_2[1]), + .I3(com_cmm_u_cmm_cfgspace_sel_encodex_2[2]), + .O(com_cmm_u_cmm_cfgspace_low_addr_02_7_0_am_23__4603) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_02_7_0_bm_23_.INIT = 16'hAA0C; + LUT4 com_cmm_u_cmm_cfgspace_low_addr_02_7_0_bm_23_ ( + .I0(com_cmm_u_cmm_cfgspace_N_4357), + .I1(com_cmm_bar2_reg[23]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex_2[1]), + .I3(com_cmm_u_cmm_cfgspace_sel_encodex_2[2]), + .O(com_cmm_u_cmm_cfgspace_low_addr_02_7_0_bm_23__4602) + ); + MUXF5 com_cmm_u_cmm_cfgspace_low_addr_02_7_0_23_ ( + .I0(com_cmm_u_cmm_cfgspace_low_addr_02_7_0_am_23__4603), + .I1(com_cmm_u_cmm_cfgspace_low_addr_02_7_0_bm_23__4602), + .O(com_cmm_u_cmm_cfgspace_low_addr_02[23]), + .S(com_cmm_u_cmm_cfgspace_sel_encodex[0]) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_02_7_0_am_24_.INIT = 16'h00CA; + LUT4 com_cmm_u_cmm_cfgspace_low_addr_02_7_0_am_24_ ( + .I0(cfg_cfg_5072[56]), + .I1(cfg_cfg_5072[280]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex_2[1]), + .I3(com_cmm_u_cmm_cfgspace_sel_encodex_2[2]), + .O(com_cmm_u_cmm_cfgspace_low_addr_02_7_0_am_24__4605) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_02_7_0_bm_24_.INIT = 16'hAA0C; + LUT4 com_cmm_u_cmm_cfgspace_low_addr_02_7_0_bm_24_ ( + .I0(com_cmm_u_cmm_cfgspace_N_4358), + .I1(com_cmm_bar2_reg[24]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex_2[1]), + .I3(com_cmm_u_cmm_cfgspace_sel_encodex_2[2]), + .O(com_cmm_u_cmm_cfgspace_low_addr_02_7_0_bm_24__4604) + ); + MUXF5 com_cmm_u_cmm_cfgspace_low_addr_02_7_0_24_ ( + .I0(com_cmm_u_cmm_cfgspace_low_addr_02_7_0_am_24__4605), + .I1(com_cmm_u_cmm_cfgspace_low_addr_02_7_0_bm_24__4604), + .O(com_cmm_u_cmm_cfgspace_low_addr_02[24]), + .S(com_cmm_u_cmm_cfgspace_sel_encodex[0]) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_02_7_0_am_25_.INIT = 16'h00CA; + LUT4 com_cmm_u_cmm_cfgspace_low_addr_02_7_0_am_25_ ( + .I0(cfg_cfg_5072[57]), + .I1(cfg_cfg_5072[281]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex_2[1]), + .I3(com_cmm_u_cmm_cfgspace_sel_encodex_2[2]), + .O(com_cmm_u_cmm_cfgspace_low_addr_02_7_0_am_25__4607) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_02_7_0_bm_25_.INIT = 16'hAA0C; + LUT4 com_cmm_u_cmm_cfgspace_low_addr_02_7_0_bm_25_ ( + .I0(com_cmm_u_cmm_cfgspace_N_4359), + .I1(com_cmm_bar2_reg[25]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex_2[1]), + .I3(com_cmm_u_cmm_cfgspace_sel_encodex_2[2]), + .O(com_cmm_u_cmm_cfgspace_low_addr_02_7_0_bm_25__4606) + ); + MUXF5 com_cmm_u_cmm_cfgspace_low_addr_02_7_0_25_ ( + .I0(com_cmm_u_cmm_cfgspace_low_addr_02_7_0_am_25__4607), + .I1(com_cmm_u_cmm_cfgspace_low_addr_02_7_0_bm_25__4606), + .O(com_cmm_u_cmm_cfgspace_low_addr_02[25]), + .S(com_cmm_u_cmm_cfgspace_sel_encodex[0]) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_02_7_0_am_26_.INIT = 16'h00CA; + LUT4 com_cmm_u_cmm_cfgspace_low_addr_02_7_0_am_26_ ( + .I0(cfg_cfg_5072[58]), + .I1(cfg_cfg_5072[282]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex_2[1]), + .I3(com_cmm_u_cmm_cfgspace_sel_encodex_2[2]), + .O(com_cmm_u_cmm_cfgspace_low_addr_02_7_0_am_26__4609) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_02_7_0_bm_26_.INIT = 16'hAA0C; + LUT4 com_cmm_u_cmm_cfgspace_low_addr_02_7_0_bm_26_ ( + .I0(com_cmm_u_cmm_cfgspace_N_4360), + .I1(com_cmm_bar2_reg[26]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex_2[1]), + .I3(com_cmm_u_cmm_cfgspace_sel_encodex_2[2]), + .O(com_cmm_u_cmm_cfgspace_low_addr_02_7_0_bm_26__4608) + ); + MUXF5 com_cmm_u_cmm_cfgspace_low_addr_02_7_0_26_ ( + .I0(com_cmm_u_cmm_cfgspace_low_addr_02_7_0_am_26__4609), + .I1(com_cmm_u_cmm_cfgspace_low_addr_02_7_0_bm_26__4608), + .O(com_cmm_u_cmm_cfgspace_low_addr_02[26]), + .S(com_cmm_u_cmm_cfgspace_sel_encodex[0]) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_02_7_0_am_27_.INIT = 16'h00CA; + LUT4 com_cmm_u_cmm_cfgspace_low_addr_02_7_0_am_27_ ( + .I0(cfg_cfg_5072[59]), + .I1(cfg_cfg_5072[283]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex_2[1]), + .I3(com_cmm_u_cmm_cfgspace_sel_encodex_2[2]), + .O(com_cmm_u_cmm_cfgspace_low_addr_02_7_0_am_27__4611) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_02_7_0_bm_27_.INIT = 16'hAA0C; + LUT4 com_cmm_u_cmm_cfgspace_low_addr_02_7_0_bm_27_ ( + .I0(com_cmm_u_cmm_cfgspace_N_4361), + .I1(com_cmm_bar2_reg[27]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex_2[1]), + .I3(com_cmm_u_cmm_cfgspace_sel_encodex_2[2]), + .O(com_cmm_u_cmm_cfgspace_low_addr_02_7_0_bm_27__4610) + ); + MUXF5 com_cmm_u_cmm_cfgspace_low_addr_02_7_0_27_ ( + .I0(com_cmm_u_cmm_cfgspace_low_addr_02_7_0_am_27__4611), + .I1(com_cmm_u_cmm_cfgspace_low_addr_02_7_0_bm_27__4610), + .O(com_cmm_u_cmm_cfgspace_low_addr_02[27]), + .S(com_cmm_u_cmm_cfgspace_sel_encodex[0]) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_02_7_0_am_28_.INIT = 16'hC0AA; + LUT4 com_cmm_u_cmm_cfgspace_low_addr_02_7_0_am_28_ ( + .I0(com_cmm_u_cmm_cfgspace_N_4234), + .I1(NlwRenamedSig_OI_cfg_lstatus_12_), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex_2[1]), + .I3(com_cmm_u_cmm_cfgspace_sel_encodex_2[2]), + .O(com_cmm_u_cmm_cfgspace_low_addr_02_7_0_am_28__4613) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_02_7_0_bm_28_.INIT = 16'hAA0C; + LUT4 com_cmm_u_cmm_cfgspace_low_addr_02_7_0_bm_28_ ( + .I0(com_cmm_u_cmm_cfgspace_N_4362), + .I1(com_cmm_bar2_reg[28]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex_2[1]), + .I3(com_cmm_u_cmm_cfgspace_sel_encodex_2[2]), + .O(com_cmm_u_cmm_cfgspace_low_addr_02_7_0_bm_28__4612) + ); + MUXF5 com_cmm_u_cmm_cfgspace_low_addr_02_7_0_28_ ( + .I0(com_cmm_u_cmm_cfgspace_low_addr_02_7_0_am_28__4613), + .I1(com_cmm_u_cmm_cfgspace_low_addr_02_7_0_bm_28__4612), + .O(com_cmm_u_cmm_cfgspace_low_addr_02[28]), + .S(com_cmm_u_cmm_cfgspace_sel_encodex[0]) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_02_7_0_am_29_.INIT = 16'h00CA; + LUT4 com_cmm_u_cmm_cfgspace_low_addr_02_7_0_am_29_ ( + .I0(cfg_cfg_5072[61]), + .I1(cfg_cfg_5072[285]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex_2[1]), + .I3(com_cmm_u_cmm_cfgspace_sel_encodex_2[2]), + .O(com_cmm_u_cmm_cfgspace_low_addr_02_7_0_am_29__4615) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_02_7_0_bm_29_.INIT = 16'hAA0C; + LUT4 com_cmm_u_cmm_cfgspace_low_addr_02_7_0_bm_29_ ( + .I0(com_cmm_u_cmm_cfgspace_N_4363), + .I1(com_cmm_bar2_reg[29]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex_2[1]), + .I3(com_cmm_u_cmm_cfgspace_sel_encodex_2[2]), + .O(com_cmm_u_cmm_cfgspace_low_addr_02_7_0_bm_29__4614) + ); + MUXF5 com_cmm_u_cmm_cfgspace_low_addr_02_7_0_29_ ( + .I0(com_cmm_u_cmm_cfgspace_low_addr_02_7_0_am_29__4615), + .I1(com_cmm_u_cmm_cfgspace_low_addr_02_7_0_bm_29__4614), + .O(com_cmm_u_cmm_cfgspace_low_addr_02[29]), + .S(com_cmm_u_cmm_cfgspace_sel_encodex[0]) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_02_7_0_am_30_.INIT = 16'h00CA; + LUT4 com_cmm_u_cmm_cfgspace_low_addr_02_7_0_am_30_ ( + .I0(cfg_cfg_5072[62]), + .I1(cfg_cfg_5072[286]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex_2[1]), + .I3(com_cmm_u_cmm_cfgspace_sel_encodex_2[2]), + .O(com_cmm_u_cmm_cfgspace_low_addr_02_7_0_am_30__4617) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_02_7_0_bm_30_.INIT = 16'hAA0C; + LUT4 com_cmm_u_cmm_cfgspace_low_addr_02_7_0_bm_30_ ( + .I0(com_cmm_u_cmm_cfgspace_N_4364), + .I1(com_cmm_bar2_reg[30]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex_2[1]), + .I3(com_cmm_u_cmm_cfgspace_sel_encodex_2[2]), + .O(com_cmm_u_cmm_cfgspace_low_addr_02_7_0_bm_30__4616) + ); + MUXF5 com_cmm_u_cmm_cfgspace_low_addr_02_7_0_30_ ( + .I0(com_cmm_u_cmm_cfgspace_low_addr_02_7_0_am_30__4617), + .I1(com_cmm_u_cmm_cfgspace_low_addr_02_7_0_bm_30__4616), + .O(com_cmm_u_cmm_cfgspace_low_addr_02[30]), + .S(com_cmm_u_cmm_cfgspace_sel_encodex[0]) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_02_7_0_am_31_.INIT = 16'h00CA; + LUT4 com_cmm_u_cmm_cfgspace_low_addr_02_7_0_am_31_ ( + .I0(cfg_cfg_5072[63]), + .I1(cfg_cfg_5072[287]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex_2[1]), + .I3(com_cmm_u_cmm_cfgspace_sel_encodex_2[2]), + .O(com_cmm_u_cmm_cfgspace_low_addr_02_7_0_am_31__4619) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_02_7_0_bm_31_.INIT = 16'hAA0C; + LUT4 com_cmm_u_cmm_cfgspace_low_addr_02_7_0_bm_31_ ( + .I0(com_cmm_u_cmm_cfgspace_N_4365), + .I1(com_cmm_bar2_reg[31]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex_2[1]), + .I3(com_cmm_u_cmm_cfgspace_sel_encodex_2[2]), + .O(com_cmm_u_cmm_cfgspace_low_addr_02_7_0_bm_31__4618) + ); + MUXF5 com_cmm_u_cmm_cfgspace_low_addr_02_7_0_31_ ( + .I0(com_cmm_u_cmm_cfgspace_low_addr_02_7_0_am_31__4619), + .I1(com_cmm_u_cmm_cfgspace_low_addr_02_7_0_bm_31__4618), + .O(com_cmm_u_cmm_cfgspace_low_addr_02[31]), + .S(com_cmm_u_cmm_cfgspace_sel_encodex[0]) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_am_0_.INIT = 16'h00AC; + LUT4 com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_am_0_ ( + .I0(cfg_cfg_5072[288]), + .I1(com_cmm_u_cmm_cfgspace_cache_line[0]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex_2[1]), + .I3(com_cmm_u_cmm_cfgspace_sel_encodex_2[2]), + .O(com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_am[0]) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_bm_0_.INIT = 16'h3A0A; + LUT4 com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_bm_0_ ( + .I0(com_cmm_u_cmm_cfgspace_N_4526), + .I1(com_cmm_u_cmm_cfgspace_sel_encodex_2[1]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex_2[2]), + .I3(com_cmm_u_cmm_cfgspace_x_dcap[0]), + .O(com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_bm[0]) + ); + MUXF5 com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_0_ ( + .I0(com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_am[0]), + .I1(com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_bm[0]), + .O(com_cmm_u_cmm_cfgspace_low_addr_03_q_4[0]), + .S(com_cmm_u_cmm_cfgspace_sel_encodex[0]) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_am_1_.INIT = 16'h00AC; + LUT4 com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_am_1_ ( + .I0(cfg_cfg_5072[289]), + .I1(com_cmm_u_cmm_cfgspace_cache_line[1]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex_2[1]), + .I3(com_cmm_u_cmm_cfgspace_sel_encodex_2[2]), + .O(com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_am[1]) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_bm_1_.INIT = 16'h3A0A; + LUT4 com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_bm_1_ ( + .I0(com_cmm_u_cmm_cfgspace_N_4527), + .I1(com_cmm_u_cmm_cfgspace_sel_encodex_2[1]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex_2[2]), + .I3(com_cmm_u_cmm_cfgspace_x_dcap[1]), + .O(com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_bm[1]) + ); + MUXF5 com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_1_ ( + .I0(com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_am[1]), + .I1(com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_bm[1]), + .O(com_cmm_u_cmm_cfgspace_low_addr_03_q_4[1]), + .S(com_cmm_u_cmm_cfgspace_sel_encodex[0]) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_am_2_.INIT = 16'h0CAA; + LUT4 com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_am_2_ ( + .I0(com_cmm_u_cmm_cfgspace_N_4432), + .I1(com_cmm_msi_laddr[2]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex_2[1]), + .I3(com_cmm_u_cmm_cfgspace_sel_encodex_2[2]), + .O(com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_am[2]) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_bm_2_.INIT = 16'h3A0A; + LUT4 com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_bm_2_ ( + .I0(com_cmm_u_cmm_cfgspace_N_4528), + .I1(com_cmm_u_cmm_cfgspace_sel_encodex_2[1]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex_2[2]), + .I3(com_cmm_u_cmm_cfgspace_x_dcap[2]), + .O(com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_bm[2]) + ); + MUXF5 com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_2_ ( + .I0(com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_am[2]), + .I1(com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_bm[2]), + .O(com_cmm_u_cmm_cfgspace_low_addr_03_q_4[2]), + .S(com_cmm_u_cmm_cfgspace_sel_encodex[0]) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_am_3_.INIT = 16'h0CAA; + LUT4 com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_am_3_ ( + .I0(com_cmm_u_cmm_cfgspace_N_4433), + .I1(com_cmm_msi_laddr[3]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex_2[1]), + .I3(com_cmm_u_cmm_cfgspace_sel_encodex_2[2]), + .O(com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_am[3]) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_bm_3_.INIT = 16'h3A0A; + LUT4 com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_bm_3_ ( + .I0(com_cmm_u_cmm_cfgspace_N_4529), + .I1(com_cmm_u_cmm_cfgspace_sel_encodex_2[1]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex_2[2]), + .I3(com_cmm_u_cmm_cfgspace_x_dcap[3]), + .O(com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_bm[3]) + ); + MUXF5 com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_3_ ( + .I0(com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_am[3]), + .I1(com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_bm[3]), + .O(com_cmm_u_cmm_cfgspace_low_addr_03_q_4[3]), + .S(com_cmm_u_cmm_cfgspace_sel_encodex[0]) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_am_4_.INIT = 16'h0CAA; + LUT4 com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_am_4_ ( + .I0(com_cmm_u_cmm_cfgspace_N_4434), + .I1(com_cmm_msi_laddr[4]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex_2[1]), + .I3(com_cmm_u_cmm_cfgspace_sel_encodex_2[2]), + .O(com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_am[4]) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_bm_4_.INIT = 16'h3A0A; + LUT4 com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_bm_4_ ( + .I0(com_cmm_u_cmm_cfgspace_N_4530), + .I1(com_cmm_u_cmm_cfgspace_sel_encodex_2[1]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex_2[2]), + .I3(com_cmm_u_cmm_cfgspace_x_dcap[4]), + .O(com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_bm[4]) + ); + MUXF5 com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_4_ ( + .I0(com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_am[4]), + .I1(com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_bm[4]), + .O(com_cmm_u_cmm_cfgspace_low_addr_03_q_4[4]), + .S(com_cmm_u_cmm_cfgspace_sel_encodex[0]) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_am_5_.INIT = 16'h0CAA; + LUT4 com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_am_5_ ( + .I0(com_cmm_u_cmm_cfgspace_N_4435), + .I1(com_cmm_msi_laddr[5]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex_2[1]), + .I3(com_cmm_u_cmm_cfgspace_sel_encodex_2[2]), + .O(com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_am[5]) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_bm_5_.INIT = 16'h3A0A; + LUT4 com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_bm_5_ ( + .I0(com_cmm_u_cmm_cfgspace_N_4531), + .I1(com_cmm_u_cmm_cfgspace_sel_encodex_2[1]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex_2[2]), + .I3(com_cmm_u_cmm_cfgspace_x_dcap[5]), + .O(com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_bm[5]) + ); + MUXF5 com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_5_ ( + .I0(com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_am[5]), + .I1(com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_bm[5]), + .O(com_cmm_u_cmm_cfgspace_low_addr_03_q_4[5]), + .S(com_cmm_u_cmm_cfgspace_sel_encodex[0]) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_am_6_.INIT = 16'h0CAA; + LUT4 com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_am_6_ ( + .I0(com_cmm_u_cmm_cfgspace_N_4436), + .I1(com_cmm_msi_laddr[6]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex_2[1]), + .I3(com_cmm_u_cmm_cfgspace_sel_encodex_2[2]), + .O(com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_am[6]) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_bm_6_.INIT = 16'h3A0A; + LUT4 com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_bm_6_ ( + .I0(com_cmm_u_cmm_cfgspace_N_4532), + .I1(com_cmm_u_cmm_cfgspace_sel_encodex_2[1]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex_2[2]), + .I3(com_cmm_u_cmm_cfgspace_x_dcap[6]), + .O(com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_bm[6]) + ); + MUXF5 com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_6_ ( + .I0(com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_am[6]), + .I1(com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_bm[6]), + .O(com_cmm_u_cmm_cfgspace_low_addr_03_q_4[6]), + .S(com_cmm_u_cmm_cfgspace_sel_encodex[0]) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_am_7_.INIT = 16'h0CAA; + LUT4 com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_am_7_ ( + .I0(com_cmm_u_cmm_cfgspace_N_4437), + .I1(com_cmm_msi_laddr[7]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex_2[1]), + .I3(com_cmm_u_cmm_cfgspace_sel_encodex_2[2]), + .O(com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_am[7]) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_bm_7_.INIT = 16'h3A0A; + LUT4 com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_bm_7_ ( + .I0(com_cmm_u_cmm_cfgspace_N_4533), + .I1(com_cmm_u_cmm_cfgspace_sel_encodex_2[1]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex_2[2]), + .I3(com_cmm_u_cmm_cfgspace_x_dcap[7]), + .O(com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_bm[7]) + ); + MUXF5 com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_7_ ( + .I0(com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_am[7]), + .I1(com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_bm[7]), + .O(com_cmm_u_cmm_cfgspace_low_addr_03_q_4[7]), + .S(com_cmm_u_cmm_cfgspace_sel_encodex[0]) + ); + MUXF6 com_cmm_u_cmm_cfgspace_pme_data_6_i_m2_i_m4_i_m3_0_0_ ( + .I0(com_cmm_u_cmm_cfgspace_N_51579), + .I1(com_cmm_u_cmm_cfgspace_N_51549), + .O(com_cmm_u_cmm_cfgspace_N_51589), + .S(com_cmm_u_cmm_cfgspace_pme_pmcsr[10]) + ); + MUXF6 com_cmm_u_cmm_cfgspace_pme_data_6_i_m2_i_m4_i_m3_0_3_ ( + .I0(com_cmm_u_cmm_cfgspace_N_51582), + .I1(com_cmm_u_cmm_cfgspace_N_51552), + .O(com_cmm_u_cmm_cfgspace_N_51592), + .S(com_cmm_u_cmm_cfgspace_pme_pmcsr[10]) + ); + MUXF6 com_cmm_u_cmm_cfgspace_pme_data_6_i_m2_i_m4_i_m3_0_4_ ( + .I0(com_cmm_u_cmm_cfgspace_N_51583), + .I1(com_cmm_u_cmm_cfgspace_N_51553), + .O(com_cmm_u_cmm_cfgspace_N_51593), + .S(com_cmm_u_cmm_cfgspace_pme_pmcsr[10]) + ); + MUXF6 com_cmm_u_cmm_cfgspace_pme_data_6_i_m2_i_m4_i_m3_0_5_ ( + .I0(com_cmm_u_cmm_cfgspace_N_51584), + .I1(com_cmm_u_cmm_cfgspace_N_51554), + .O(com_cmm_u_cmm_cfgspace_N_51594), + .S(com_cmm_u_cmm_cfgspace_pme_pmcsr[10]) + ); + MUXF6 com_cmm_u_cmm_cfgspace_pme_data_6_i_m2_i_m4_i_m3_0_6_ ( + .I0(com_cmm_u_cmm_cfgspace_N_51585), + .I1(com_cmm_u_cmm_cfgspace_N_51555), + .O(com_cmm_u_cmm_cfgspace_N_51595), + .S(com_cmm_u_cmm_cfgspace_pme_pmcsr[10]) + ); + MUXF6 com_cmm_u_cmm_cfgspace_pme_data_6_i_m2_i_m4_i_m3_0_7_ ( + .I0(com_cmm_u_cmm_cfgspace_N_51586), + .I1(com_cmm_u_cmm_cfgspace_N_51556), + .O(com_cmm_u_cmm_cfgspace_N_51596), + .S(com_cmm_u_cmm_cfgspace_pme_pmcsr[10]) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_02_7_0_am_7_.INIT = 16'hC0AA; + LUT4 com_cmm_u_cmm_cfgspace_low_addr_02_7_0_am_7_ ( + .I0(com_cmm_u_cmm_cfgspace_N_4213), + .I1(NlwRenamedSig_OI_cfg_lcommand_7_), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex_2[1]), + .I3(com_cmm_u_cmm_cfgspace_sel_encodex_2[2]), + .O(com_cmm_u_cmm_cfgspace_low_addr_02_7_0_am_7__4621) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_02_7_0_bm_7_.INIT = 16'hAA0C; + LUT4 com_cmm_u_cmm_cfgspace_low_addr_02_7_0_bm_7_ ( + .I0(com_cmm_u_cmm_cfgspace_N_4341), + .I1(com_cmm_bar2_reg[7]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex_2[1]), + .I3(com_cmm_u_cmm_cfgspace_sel_encodex_2[2]), + .O(com_cmm_u_cmm_cfgspace_low_addr_02_7_0_bm_7__4620) + ); + MUXF5 com_cmm_u_cmm_cfgspace_low_addr_02_7_0_7_ ( + .I0(com_cmm_u_cmm_cfgspace_low_addr_02_7_0_am_7__4621), + .I1(com_cmm_u_cmm_cfgspace_low_addr_02_7_0_bm_7__4620), + .O(com_cmm_u_cmm_cfgspace_low_addr_02[7]), + .S(com_cmm_u_cmm_cfgspace_sel_encodex[0]) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_00_i_0_1_16_.INIT = 16'h1101; + LUT4_L com_cmm_u_cmm_cfgspace_low_addr_00_i_0_1_16_ ( + .I0(com_cmm_u_cmm_cfgspace_N_50138), + .I1(com_cmm_u_cmm_cfgspace_N_50139), + .I2(com_cmm_u_cmm_cfgspace_N_50457), + .I3(com_cmm_xrom_reg_16_), + .LO(com_cmm_u_cmm_cfgspace_low_addr_00_i_0_1_16__4700) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_00_i_i_0_1_29_.INIT = 16'h0111; + LUT4 com_cmm_u_cmm_cfgspace_low_addr_00_i_i_0_1_29_ ( + .I0(com_cmm_u_cmm_cfgspace_N_45969), + .I1(com_cmm_u_cmm_cfgspace_N_45970), + .I2(com_cmm_u_cmm_cfgspace_N_50457), + .I3(com_cmm_xrom_reg_29_), + .O(com_cmm_u_cmm_cfgspace_low_addr_00_i_i_0_1_29__4675) + ); + defparam com_cmm_u_cmm_cfgspace_x_dcmd_1_sqmuxa_1_0_a2_0_a2_0_a2_0_a2.INIT = 4'h2; + LUT2 com_cmm_u_cmm_cfgspace_x_dcmd_1_sqmuxa_1_0_a2_0_a2_0_a2_0_a2 ( + .I0(com_cmm_u_cmm_cfgspace_N_48878_i), + .I1(com_cmm_rst_267), + .O(com_cmm_u_cmm_cfgspace_x_dcmd_1_sqmuxa_1) + ); + defparam com_cmm_u_cmm_cfgspace_x3gio_decodepipe_h_sel_3x_3_0_0_a2_1.INIT = 4'h2; + LUT2 com_cmm_u_cmm_cfgspace_x3gio_decodepipe_h_sel_3x_3_0_0_a2_1 ( + .I0(com_cmm_u_cmm_cfgspace_N_48930_i), + .I1(cfg_dwaddr_5069[4]), + .O(com_cmm_u_cmm_cfgspace_N_50466_2) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_02_7_0_am_8_.INIT = 16'hC0AA; + LUT4 com_cmm_u_cmm_cfgspace_low_addr_02_7_0_am_8_ ( + .I0(com_cmm_u_cmm_cfgspace_N_4214), + .I1(com_cmm_u_cmm_cfgspace_N_49913_1), + .I2(cfg_cfg_5072[483]), + .I3(com_cmm_u_cmm_cfgspace_sel_encodex_2[2]), + .O(com_cmm_u_cmm_cfgspace_low_addr_02_7_0_am_8__4623) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_02_7_0_bm_8_.INIT = 16'hA00C; + LUT4 com_cmm_u_cmm_cfgspace_low_addr_02_7_0_bm_8_ ( + .I0(cfg_cfg_5072[696]), + .I1(com_cmm_bar2_reg[8]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex_2[1]), + .I3(com_cmm_u_cmm_cfgspace_sel_encodex_2[2]), + .O(com_cmm_u_cmm_cfgspace_low_addr_02_7_0_bm_8__4622) + ); + MUXF5 com_cmm_u_cmm_cfgspace_low_addr_02_7_0_8_ ( + .I0(com_cmm_u_cmm_cfgspace_low_addr_02_7_0_am_8__4623), + .I1(com_cmm_u_cmm_cfgspace_low_addr_02_7_0_bm_8__4622), + .O(com_cmm_u_cmm_cfgspace_low_addr_02[8]), + .S(com_cmm_u_cmm_cfgspace_sel_encodex[0]) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_02_7_0_am_9_.INIT = 16'hC0AA; + LUT4 com_cmm_u_cmm_cfgspace_low_addr_02_7_0_am_9_ ( + .I0(com_cmm_u_cmm_cfgspace_N_4215), + .I1(com_cmm_u_cmm_cfgspace_N_49913_1), + .I2(cfg_cfg_5072[484]), + .I3(com_cmm_u_cmm_cfgspace_sel_encodex_2[2]), + .O(com_cmm_u_cmm_cfgspace_low_addr_02_7_0_am_9__4625) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_02_7_0_bm_9_.INIT = 16'hA00C; + LUT4 com_cmm_u_cmm_cfgspace_low_addr_02_7_0_bm_9_ ( + .I0(cfg_cfg_5072[697]), + .I1(com_cmm_bar2_reg[9]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex_2[1]), + .I3(com_cmm_u_cmm_cfgspace_sel_encodex_2[2]), + .O(com_cmm_u_cmm_cfgspace_low_addr_02_7_0_bm_9__4624) + ); + MUXF5 com_cmm_u_cmm_cfgspace_low_addr_02_7_0_9_ ( + .I0(com_cmm_u_cmm_cfgspace_low_addr_02_7_0_am_9__4625), + .I1(com_cmm_u_cmm_cfgspace_low_addr_02_7_0_bm_9__4624), + .O(com_cmm_u_cmm_cfgspace_low_addr_02[9]), + .S(com_cmm_u_cmm_cfgspace_sel_encodex[0]) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_02_7_0_am_10_.INIT = 16'hC0AA; + LUT4 com_cmm_u_cmm_cfgspace_low_addr_02_7_0_am_10_ ( + .I0(com_cmm_u_cmm_cfgspace_N_4216), + .I1(com_cmm_u_cmm_cfgspace_N_49913_1), + .I2(cfg_cfg_5072[485]), + .I3(com_cmm_u_cmm_cfgspace_sel_encodex_2[2]), + .O(com_cmm_u_cmm_cfgspace_low_addr_02_7_0_am_10__4627) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_02_7_0_bm_10_.INIT = 16'hA00C; + LUT4 com_cmm_u_cmm_cfgspace_low_addr_02_7_0_bm_10_ ( + .I0(cfg_cfg_5072[698]), + .I1(com_cmm_bar2_reg[10]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex_2[1]), + .I3(com_cmm_u_cmm_cfgspace_sel_encodex_2[2]), + .O(com_cmm_u_cmm_cfgspace_low_addr_02_7_0_bm_10__4626) + ); + MUXF5 com_cmm_u_cmm_cfgspace_low_addr_02_7_0_10_ ( + .I0(com_cmm_u_cmm_cfgspace_low_addr_02_7_0_am_10__4627), + .I1(com_cmm_u_cmm_cfgspace_low_addr_02_7_0_bm_10__4626), + .O(com_cmm_u_cmm_cfgspace_low_addr_02[10]), + .S(com_cmm_u_cmm_cfgspace_sel_encodex[0]) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_02_7_0_am_13_.INIT = 16'hC0AA; + LUT4 com_cmm_u_cmm_cfgspace_low_addr_02_7_0_am_13_ ( + .I0(com_cmm_u_cmm_cfgspace_N_4219), + .I1(com_cmm_u_cmm_cfgspace_N_49913_1), + .I2(cfg_cfg_5072[488]), + .I3(com_cmm_u_cmm_cfgspace_sel_encodex_2[2]), + .O(com_cmm_u_cmm_cfgspace_low_addr_02_7_0_am_13__4629) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_02_7_0_bm_13_.INIT = 16'hA00C; + LUT4 com_cmm_u_cmm_cfgspace_low_addr_02_7_0_bm_13_ ( + .I0(cfg_cfg_5072[701]), + .I1(com_cmm_bar2_reg[13]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex_2[1]), + .I3(com_cmm_u_cmm_cfgspace_sel_encodex_2[2]), + .O(com_cmm_u_cmm_cfgspace_low_addr_02_7_0_bm_13__4628) + ); + MUXF5 com_cmm_u_cmm_cfgspace_low_addr_02_7_0_13_ ( + .I0(com_cmm_u_cmm_cfgspace_low_addr_02_7_0_am_13__4629), + .I1(com_cmm_u_cmm_cfgspace_low_addr_02_7_0_bm_13__4628), + .O(com_cmm_u_cmm_cfgspace_low_addr_02[13]), + .S(com_cmm_u_cmm_cfgspace_sel_encodex[0]) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_02_7_0_am_15_.INIT = 16'hC0AA; + LUT4 com_cmm_u_cmm_cfgspace_low_addr_02_7_0_am_15_ ( + .I0(com_cmm_u_cmm_cfgspace_N_4221), + .I1(com_cmm_u_cmm_cfgspace_N_49913_1), + .I2(cfg_cfg_5072[490]), + .I3(com_cmm_u_cmm_cfgspace_sel_encodex_2[2]), + .O(com_cmm_u_cmm_cfgspace_low_addr_02_7_0_am_15__4631) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_02_7_0_bm_15_.INIT = 16'hAA0C; + LUT4 com_cmm_u_cmm_cfgspace_low_addr_02_7_0_bm_15_ ( + .I0(com_cmm_u_cmm_cfgspace_N_4349), + .I1(com_cmm_bar2_reg[15]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex_2[1]), + .I3(com_cmm_u_cmm_cfgspace_sel_encodex_2[2]), + .O(com_cmm_u_cmm_cfgspace_low_addr_02_7_0_bm_15__4630) + ); + MUXF5 com_cmm_u_cmm_cfgspace_low_addr_02_7_0_15_ ( + .I0(com_cmm_u_cmm_cfgspace_low_addr_02_7_0_am_15__4631), + .I1(com_cmm_u_cmm_cfgspace_low_addr_02_7_0_bm_15__4630), + .O(com_cmm_u_cmm_cfgspace_low_addr_02[15]), + .S(com_cmm_u_cmm_cfgspace_sel_encodex[0]) + ); + defparam com_cmm_u_cmm_cfgspace_x3gio_decodepipe_h_sel_6x_3_0_0_0_a2_0_1.INIT = 8'h80; + LUT3 com_cmm_u_cmm_cfgspace_x3gio_decodepipe_h_sel_6x_3_0_0_0_a2_0_1 ( + .I0(com_cmm_u_cmm_cfgspace_N_50491), + .I1(com_cmm_u_cmm_cfgspace_N_50496), + .I2(com_cmm_cfg_addr[4]), + .O(com_cmm_u_cmm_cfgspace_N_49177_1) + ); + defparam com_cmm_u_cmm_cfgspace_x3gio_decodepipe_h_sel_3x_3_0_0_a2_0.INIT = 16'h8000; + LUT4 com_cmm_u_cmm_cfgspace_x3gio_decodepipe_h_sel_3x_3_0_0_a2_0 ( + .I0(com_cmm_u_cmm_cfgspace_N_43088_1), + .I1(com_cmm_u_cmm_cfgspace_N_50491), + .I2(com_cmm_cfg_addr[2]), + .I3(com_cmm_cfg_addr[3]), + .O(com_cmm_u_cmm_cfgspace_N_42097) + ); + defparam com_cmm_u_cmm_cfgspace_x3gio_decodepipe_h_sel_5x_3_0_0_0_a3.INIT = 16'h0800; + LUT4_L com_cmm_u_cmm_cfgspace_x3gio_decodepipe_h_sel_5x_3_0_0_0_a3 ( + .I0(com_cmm_u_cmm_cfgspace_N_48930_i), + .I1(cfg_dwaddr_5069[2]), + .I2(cfg_dwaddr_5069[3]), + .I3(cfg_dwaddr_5069[4]), + .LO(com_cmm_u_cmm_cfgspace_N_50463) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_00_0_0_i_15_32135.INIT = 16'h08AA; + LUT4_L com_cmm_u_cmm_cfgspace_low_addr_00_0_0_i_15_32135 ( + .I0(com_cmm_u_cmm_cfgspace_low_addr_00_0_0_i_15_32133_4632), + .I1(com_cmm_msi_haddr[15]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex_2[1]), + .I3(com_cmm_u_cmm_cfgspace_sel_encodex_2[2]), + .LO(com_cmm_u_cmm_cfgspace_low_addr_00_0_0_i_15_32135_4701) + ); + defparam com_cmm_u_cmm_cfgspace_sel_encodex_en_3_i_0_32190.INIT = 16'h55F7; + LUT4 com_cmm_u_cmm_cfgspace_sel_encodex_en_3_i_0_32190 ( + .I0(com_cmm_u_cmm_cfgspace_N_48842_i), + .I1(com_cmm_u_cmm_cfgspace_N_50496), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex_en_3_i_0_o4_0_4633), + .I3(com_cmm_u_cmm_cfgspace_sel_encodex_en_3_i_0_a2_4_2_4652), + .O(com_cmm_u_cmm_cfgspace_sel_encodex_en_3_i_0_32190_4736) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_01_2_0_a2_0_a2_0_a2_0_a2_26_.INIT = 16'h88A0; + LUT4_L com_cmm_u_cmm_cfgspace_low_addr_01_2_0_a2_0_a2_0_a2_0_a2_26_ ( + .I0(com_cmm_u_cmm_cfgspace_N_50497), + .I1(com_cmm_u_cmm_cfgspace_N_51551), + .I2(com_cmm_u_cmm_cfgspace_N_51581), + .I3(com_cmm_u_cmm_cfgspace_pme_pmcsr[10]), + .LO(com_cmm_u_cmm_cfgspace_N_50220) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_01_2_0_a2_0_a2_0_a2_0_a2_25_.INIT = 16'h88A0; + LUT4_L com_cmm_u_cmm_cfgspace_low_addr_01_2_0_a2_0_a2_0_a2_0_a2_25_ ( + .I0(com_cmm_u_cmm_cfgspace_N_50497), + .I1(com_cmm_u_cmm_cfgspace_N_51550), + .I2(com_cmm_u_cmm_cfgspace_N_51580), + .I3(com_cmm_u_cmm_cfgspace_pme_pmcsr[10]), + .LO(com_cmm_u_cmm_cfgspace_N_50219) + ); + defparam com_cmm_u_cmm_cfgspace_x3gio_pmcsr_pme_pmcsr_21_0_0_i_0_m3_0_12_.INIT = 8'hE4; + LUT3_L com_cmm_u_cmm_cfgspace_x3gio_pmcsr_pme_pmcsr_21_0_0_i_0_m3_0_12_ ( + .I0(N_44884_i), + .I1(com_cmm_u_cmm_cfgspace_pme_pmcsr[12]), + .I2(com_cmm_state_1_), + .LO(com_cmm_u_cmm_cfgspace_N_49015) + ); + defparam com_cmm_u_cmm_cfgspace_x_dcmd_18_1_i_0_0_m3_0_8_.INIT = 8'hE4; + LUT3_L com_cmm_u_cmm_cfgspace_x_dcmd_18_1_i_0_0_m3_0_8_ ( + .I0(com_cmm_u_cmm_cfgspace_N_48878_i), + .I1(NlwRenamedSig_OI_cfg_dcommand[8]), + .I2(com_cmm_u_cmm_cfgspace_x_dcap[5]), + .LO(com_cmm_u_cmm_cfgspace_N_49117) + ); + defparam com_cmm_u_cmm_cfgspace_N_68712_i.INIT = 16'hE444; + LUT4 com_cmm_u_cmm_cfgspace_N_68712_i ( + .I0(com_cmm_u_cmm_cfgspace_N_48842_i), + .I1(cfg_dwaddr_5069[6]), + .I2(com_cmm_cfg_addr[6]), + .I3(com_cmm_state_1_), + .O(com_cmm_u_cmm_cfgspace_N_68712_i_4740) + ); + defparam com_cmm_u_cmm_cfgspace_x3gio_decodepipe_h_sel_6x_3_0_0_0_a2.INIT = 8'h80; + LUT3_L com_cmm_u_cmm_cfgspace_x3gio_decodepipe_h_sel_6x_3_0_0_0_a2 ( + .I0(com_cmm_u_cmm_cfgspace_N_48973_i), + .I1(cfg_dwaddr_5069[3]), + .I2(cfg_dwaddr_5069[4]), + .LO(com_cmm_u_cmm_cfgspace_N_49176) + ); + defparam com_cmm_u_cmm_cfgspace_x3gio_decodepipe_h_sel_1x_3_0_0_0_a2.INIT = 16'h0080; + LUT4 com_cmm_u_cmm_cfgspace_x3gio_decodepipe_h_sel_1x_3_0_0_0_a2 ( + .I0(com_cmm_u_cmm_cfgspace_N_43088_1), + .I1(com_cmm_u_cmm_cfgspace_N_50491), + .I2(com_cmm_cfg_addr[2]), + .I3(com_cmm_cfg_addr[3]), + .O(com_cmm_u_cmm_cfgspace_N_49172) + ); + defparam com_cmm_u_cmm_cfgspace_x3gio_decodepipe_h_sel_2x_3_0_0_0_a2.INIT = 16'h0800; + LUT4 com_cmm_u_cmm_cfgspace_x3gio_decodepipe_h_sel_2x_3_0_0_0_a2 ( + .I0(com_cmm_u_cmm_cfgspace_N_43088_1), + .I1(com_cmm_u_cmm_cfgspace_N_50491), + .I2(com_cmm_cfg_addr[2]), + .I3(com_cmm_cfg_addr[3]), + .O(com_cmm_u_cmm_cfgspace_N_49173) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_00_i_0_0_31_32092.INIT = 16'hC040; + LUT4_L com_cmm_u_cmm_cfgspace_low_addr_00_i_0_0_31_32092 ( + .I0(com_cmm_u_cmm_cfgspace_N_50451), + .I1(com_cmm_u_cmm_cfgspace_low_addr_00_i_0_0_31_32088_4635), + .I2(com_cmm_u_cmm_cfgspace_low_addr_00_i_0_0_31_32089_4634), + .I3(cfg_cfg_5072[31]), + .LO(com_cmm_u_cmm_cfgspace_low_addr_00_i_0_0_31_32092_4671) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_00_i_30_32097.INIT = 16'hC040; + LUT4_L com_cmm_u_cmm_cfgspace_low_addr_00_i_30_32097 ( + .I0(com_cmm_u_cmm_cfgspace_N_50451), + .I1(com_cmm_u_cmm_cfgspace_low_addr_00_i_30_32093_4637), + .I2(com_cmm_u_cmm_cfgspace_low_addr_00_i_30_32094_4636), + .I3(cfg_cfg_5072[30]), + .LO(com_cmm_u_cmm_cfgspace_low_addr_00_i_30_32097_4672) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_00_i_28_32102.INIT = 16'hC040; + LUT4_L com_cmm_u_cmm_cfgspace_low_addr_00_i_28_32102 ( + .I0(com_cmm_u_cmm_cfgspace_N_50451), + .I1(com_cmm_u_cmm_cfgspace_low_addr_00_i_28_32098_4639), + .I2(com_cmm_u_cmm_cfgspace_low_addr_00_i_28_32099_4638), + .I3(cfg_cfg_5072[28]), + .LO(com_cmm_u_cmm_cfgspace_low_addr_00_i_28_32102_4676) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_00_i_26_32107.INIT = 16'hC040; + LUT4_L com_cmm_u_cmm_cfgspace_low_addr_00_i_26_32107 ( + .I0(com_cmm_u_cmm_cfgspace_N_50451), + .I1(com_cmm_u_cmm_cfgspace_low_addr_00_i_26_32103_4641), + .I2(com_cmm_u_cmm_cfgspace_low_addr_00_i_26_32104_4640), + .I3(cfg_cfg_5072[26]), + .LO(com_cmm_u_cmm_cfgspace_low_addr_00_i_26_32107_4678) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_00_i_25_32112.INIT = 16'hC040; + LUT4_L com_cmm_u_cmm_cfgspace_low_addr_00_i_25_32112 ( + .I0(com_cmm_u_cmm_cfgspace_N_50451), + .I1(com_cmm_u_cmm_cfgspace_low_addr_00_i_25_32108_4643), + .I2(com_cmm_u_cmm_cfgspace_low_addr_00_i_25_32109_4642), + .I3(cfg_cfg_5072[25]), + .LO(com_cmm_u_cmm_cfgspace_low_addr_00_i_25_32112_4679) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_00_i_24_32117.INIT = 16'hC040; + LUT4_L com_cmm_u_cmm_cfgspace_low_addr_00_i_24_32117 ( + .I0(com_cmm_u_cmm_cfgspace_N_50451), + .I1(com_cmm_u_cmm_cfgspace_low_addr_00_i_24_32113_4645), + .I2(com_cmm_u_cmm_cfgspace_low_addr_00_i_24_32114_4644), + .I3(cfg_cfg_5072[24]), + .LO(com_cmm_u_cmm_cfgspace_low_addr_00_i_24_32117_4680) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_00_i_23_32122.INIT = 16'hC040; + LUT4_L com_cmm_u_cmm_cfgspace_low_addr_00_i_23_32122 ( + .I0(com_cmm_u_cmm_cfgspace_N_50451), + .I1(com_cmm_u_cmm_cfgspace_low_addr_00_i_23_32118_4647), + .I2(com_cmm_u_cmm_cfgspace_low_addr_00_i_23_32119_4646), + .I3(cfg_cfg_5072[23]), + .LO(com_cmm_u_cmm_cfgspace_low_addr_00_i_23_32122_4681) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_00_i_22_32127.INIT = 16'hC040; + LUT4_L com_cmm_u_cmm_cfgspace_low_addr_00_i_22_32127 ( + .I0(com_cmm_u_cmm_cfgspace_N_50451), + .I1(com_cmm_u_cmm_cfgspace_low_addr_00_i_22_32123_4649), + .I2(com_cmm_u_cmm_cfgspace_low_addr_00_i_22_32124_4648), + .I3(cfg_cfg_5072[22]), + .LO(com_cmm_u_cmm_cfgspace_low_addr_00_i_22_32127_4682) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_00_i_20_32132.INIT = 16'hC040; + LUT4_L com_cmm_u_cmm_cfgspace_low_addr_00_i_20_32132 ( + .I0(com_cmm_u_cmm_cfgspace_N_50451), + .I1(com_cmm_u_cmm_cfgspace_low_addr_00_i_20_32128_4651), + .I2(com_cmm_u_cmm_cfgspace_low_addr_00_i_20_32129_4650), + .I3(cfg_cfg_5072[20]), + .LO(com_cmm_u_cmm_cfgspace_low_addr_00_i_20_32132_4687) + ); + defparam com_cmm_u_cmm_cfgspace_sel_encodex_en_3_i_0_32188.INIT = 16'h5111; + LUT4_L com_cmm_u_cmm_cfgspace_sel_encodex_en_3_i_0_32188 ( + .I0(com_cmm_u_cmm_cfgspace_N_42634), + .I1(com_cmm_u_cmm_cfgspace_N_48930_i), + .I2(cfg_dwaddr_5069[3]), + .I3(cfg_dwaddr_5069[4]), + .LO(com_cmm_u_cmm_cfgspace_sel_encodex_en_3_i_0_32188_4737) + ); + defparam com_cmm_u_cmm_cfgspace_x3gio_bar4_bar4_reg_8_1_0_0_0_0_1_.INIT = 16'h4FCF; + LUT4_L com_cmm_u_cmm_cfgspace_x3gio_bar4_bar4_reg_8_1_0_0_0_0_1_ ( + .I0(com_cmm_u_cmm_cfgspace_N_48868_i), + .I1(com_cmm_u_cmm_cfgspace_N_48894_i), + .I2(cfg_cfg_5072[193]), + .I3(com_cmm_cfg_wr_data[25]), + .LO(com_cmm_u_cmm_cfgspace_bar4_reg_8_1_0_0_0_0[1]) + ); + defparam com_cmm_u_cmm_cfgspace_x3gio_bar4_bar4_reg_8_1_0_0_0_2_.INIT = 16'h4FCF; + LUT4_L com_cmm_u_cmm_cfgspace_x3gio_bar4_bar4_reg_8_1_0_0_0_2_ ( + .I0(com_cmm_u_cmm_cfgspace_N_48868_i), + .I1(com_cmm_u_cmm_cfgspace_N_48894_i), + .I2(cfg_cfg_5072[194]), + .I3(com_cmm_cfg_wr_data[26]), + .LO(com_cmm_u_cmm_cfgspace_bar4_reg_8_1_0_0_0_2_) + ); + defparam com_cmm_u_cmm_cfgspace_x3gio_bar4_bar4_reg_8_1_0_0_0_0_.INIT = 16'h4FCF; + LUT4_L com_cmm_u_cmm_cfgspace_x3gio_bar4_bar4_reg_8_1_0_0_0_0_ ( + .I0(com_cmm_u_cmm_cfgspace_N_48868_i), + .I1(com_cmm_u_cmm_cfgspace_N_48894_i), + .I2(cfg_cfg_5072[192]), + .I3(com_cmm_cfg_wr_data[24]), + .LO(com_cmm_u_cmm_cfgspace_bar4_reg_8_1_0_0_0_0_) + ); + defparam com_cmm_u_cmm_cfgspace_x3gio_bar4_bar4_reg_8_1_0_0_0_3_.INIT = 16'h4FCF; + LUT4_L com_cmm_u_cmm_cfgspace_x3gio_bar4_bar4_reg_8_1_0_0_0_3_ ( + .I0(com_cmm_u_cmm_cfgspace_N_48868_i), + .I1(com_cmm_u_cmm_cfgspace_N_48894_i), + .I2(cfg_cfg_5072[195]), + .I3(com_cmm_cfg_wr_data[27]), + .LO(com_cmm_u_cmm_cfgspace_bar4_reg_8_1_0_0_0_3_) + ); + defparam com_cmm_u_cmm_cfgspace_x3gio_bar5_bar5_reg_8_1_0_0_0_2_.INIT = 16'h4FCF; + LUT4_L com_cmm_u_cmm_cfgspace_x3gio_bar5_bar5_reg_8_1_0_0_0_2_ ( + .I0(com_cmm_u_cmm_cfgspace_N_44854_i), + .I1(com_cmm_u_cmm_cfgspace_N_48893_i), + .I2(cfg_cfg_5072[226]), + .I3(com_cmm_cfg_wr_data[26]), + .LO(com_cmm_u_cmm_cfgspace_bar5_reg_8_1_0_0_0[2]) + ); + defparam com_cmm_u_cmm_cfgspace_x3gio_bar5_bar5_reg_8_1_0_0_0_0_.INIT = 16'h4FCF; + LUT4_L com_cmm_u_cmm_cfgspace_x3gio_bar5_bar5_reg_8_1_0_0_0_0_ ( + .I0(com_cmm_u_cmm_cfgspace_N_44854_i), + .I1(com_cmm_u_cmm_cfgspace_N_48893_i), + .I2(cfg_cfg_5072[224]), + .I3(com_cmm_cfg_wr_data[24]), + .LO(com_cmm_u_cmm_cfgspace_bar5_reg_8_1_0_0_0[0]) + ); + defparam com_cmm_u_cmm_cfgspace_x3gio_bar5_bar5_reg_8_1_0_0_0_1_.INIT = 16'h4FCF; + LUT4_L com_cmm_u_cmm_cfgspace_x3gio_bar5_bar5_reg_8_1_0_0_0_1_ ( + .I0(com_cmm_u_cmm_cfgspace_N_44854_i), + .I1(com_cmm_u_cmm_cfgspace_N_48893_i), + .I2(cfg_cfg_5072[225]), + .I3(com_cmm_cfg_wr_data[25]), + .LO(com_cmm_u_cmm_cfgspace_bar5_reg_8_1_0_0_0[1]) + ); + defparam com_cmm_u_cmm_cfgspace_x3gio_bar5_bar5_reg_8_1_0_0_0_3_.INIT = 16'h4FCF; + LUT4_L com_cmm_u_cmm_cfgspace_x3gio_bar5_bar5_reg_8_1_0_0_0_3_ ( + .I0(com_cmm_u_cmm_cfgspace_N_44854_i), + .I1(com_cmm_u_cmm_cfgspace_N_48893_i), + .I2(cfg_cfg_5072[227]), + .I3(com_cmm_cfg_wr_data[27]), + .LO(com_cmm_u_cmm_cfgspace_bar5_reg_8_1_0_0_0[3]) + ); + defparam com_cmm_u_cmm_cfgspace_x3gio_bar1_bar1_reg_8_1_0_0_0_0_.INIT = 16'h4FCF; + LUT4_L com_cmm_u_cmm_cfgspace_x3gio_bar1_bar1_reg_8_1_0_0_0_0_ ( + .I0(com_cmm_u_cmm_cfgspace_N_44856_i), + .I1(com_cmm_u_cmm_cfgspace_N_48888_i), + .I2(cfg_cfg_5072[96]), + .I3(com_cmm_cfg_wr_data[24]), + .LO(com_cmm_u_cmm_cfgspace_bar1_reg_8_1_0_0_0[0]) + ); + defparam com_cmm_u_cmm_cfgspace_x3gio_bar3_bar3_reg_8_1_0_0_0_2_.INIT = 16'h4FCF; + LUT4_L com_cmm_u_cmm_cfgspace_x3gio_bar3_bar3_reg_8_1_0_0_0_2_ ( + .I0(com_cmm_u_cmm_cfgspace_N_44858_i), + .I1(com_cmm_u_cmm_cfgspace_N_48891_i), + .I2(cfg_cfg_5072[162]), + .I3(com_cmm_cfg_wr_data[26]), + .LO(com_cmm_u_cmm_cfgspace_bar3_reg_8_1_0_0_0_2_) + ); + defparam com_cmm_u_cmm_cfgspace_x3gio_bar1_bar1_reg_8_1_0_0_0_2_.INIT = 16'h4FCF; + LUT4_L com_cmm_u_cmm_cfgspace_x3gio_bar1_bar1_reg_8_1_0_0_0_2_ ( + .I0(com_cmm_u_cmm_cfgspace_N_44856_i), + .I1(com_cmm_u_cmm_cfgspace_N_48888_i), + .I2(cfg_cfg_5072[98]), + .I3(com_cmm_cfg_wr_data[26]), + .LO(com_cmm_u_cmm_cfgspace_bar1_reg_8_1_0_0_0[2]) + ); + defparam com_cmm_u_cmm_cfgspace_x3gio_bar2_bar2_reg_8_1_0_0_0_1_.INIT = 16'h4FCF; + LUT4_L com_cmm_u_cmm_cfgspace_x3gio_bar2_bar2_reg_8_1_0_0_0_1_ ( + .I0(com_cmm_u_cmm_cfgspace_N_44857_i), + .I1(com_cmm_u_cmm_cfgspace_N_48892_i), + .I2(cfg_cfg_5072[129]), + .I3(com_cmm_cfg_wr_data[25]), + .LO(com_cmm_u_cmm_cfgspace_bar2_reg_8_1_0_0_0[1]) + ); + defparam com_cmm_u_cmm_cfgspace_x3gio_bar2_bar2_reg_8_1_0_0_0_0_.INIT = 16'h4FCF; + LUT4_L com_cmm_u_cmm_cfgspace_x3gio_bar2_bar2_reg_8_1_0_0_0_0_ ( + .I0(com_cmm_u_cmm_cfgspace_N_44857_i), + .I1(com_cmm_u_cmm_cfgspace_N_48892_i), + .I2(cfg_cfg_5072[128]), + .I3(com_cmm_cfg_wr_data[24]), + .LO(com_cmm_u_cmm_cfgspace_bar2_reg_8_1_0_0_0[0]) + ); + defparam com_cmm_u_cmm_cfgspace_x3gio_bar3_bar3_reg_8_1_0_0_0_0_3_.INIT = 16'h4FCF; + LUT4_L com_cmm_u_cmm_cfgspace_x3gio_bar3_bar3_reg_8_1_0_0_0_0_3_ ( + .I0(com_cmm_u_cmm_cfgspace_N_44858_i), + .I1(com_cmm_u_cmm_cfgspace_N_48891_i), + .I2(cfg_cfg_5072[163]), + .I3(com_cmm_cfg_wr_data[27]), + .LO(com_cmm_u_cmm_cfgspace_bar3_reg_8_1_0_0_0_0_3_) + ); + defparam com_cmm_u_cmm_cfgspace_x3gio_bar3_bar3_reg_8_1_0_0_0_0_1_.INIT = 16'h4FCF; + LUT4_L com_cmm_u_cmm_cfgspace_x3gio_bar3_bar3_reg_8_1_0_0_0_0_1_ ( + .I0(com_cmm_u_cmm_cfgspace_N_44858_i), + .I1(com_cmm_u_cmm_cfgspace_N_48891_i), + .I2(cfg_cfg_5072[161]), + .I3(com_cmm_cfg_wr_data[25]), + .LO(com_cmm_u_cmm_cfgspace_bar3_reg_8_1_0_0_0_0_1_) + ); + defparam com_cmm_u_cmm_cfgspace_x3gio_bar2_bar2_reg_8_1_0_0_0_0_3_.INIT = 16'h4FCF; + LUT4_L com_cmm_u_cmm_cfgspace_x3gio_bar2_bar2_reg_8_1_0_0_0_0_3_ ( + .I0(com_cmm_u_cmm_cfgspace_N_44857_i), + .I1(com_cmm_u_cmm_cfgspace_N_48892_i), + .I2(cfg_cfg_5072[131]), + .I3(com_cmm_cfg_wr_data[27]), + .LO(com_cmm_u_cmm_cfgspace_bar2_reg_8_1_0_0_0_0[3]) + ); + defparam com_cmm_u_cmm_cfgspace_x3gio_bar1_bar1_reg_8_1_0_0_0_1_.INIT = 16'h4FCF; + LUT4_L com_cmm_u_cmm_cfgspace_x3gio_bar1_bar1_reg_8_1_0_0_0_1_ ( + .I0(com_cmm_u_cmm_cfgspace_N_44856_i), + .I1(com_cmm_u_cmm_cfgspace_N_48888_i), + .I2(cfg_cfg_5072[97]), + .I3(com_cmm_cfg_wr_data[25]), + .LO(com_cmm_u_cmm_cfgspace_bar1_reg_8_1_0_0_0[1]) + ); + defparam com_cmm_u_cmm_cfgspace_x3gio_bar1_bar1_reg_8_1_0_0_0_0_3_.INIT = 16'h4FCF; + LUT4_L com_cmm_u_cmm_cfgspace_x3gio_bar1_bar1_reg_8_1_0_0_0_0_3_ ( + .I0(com_cmm_u_cmm_cfgspace_N_44856_i), + .I1(com_cmm_u_cmm_cfgspace_N_48888_i), + .I2(cfg_cfg_5072[99]), + .I3(com_cmm_cfg_wr_data[27]), + .LO(com_cmm_u_cmm_cfgspace_bar1_reg_8_1_0_0_0_0[3]) + ); + defparam com_cmm_u_cmm_cfgspace_x3gio_bar2_bar2_reg_8_1_0_0_0_2_.INIT = 16'h4FCF; + LUT4_L com_cmm_u_cmm_cfgspace_x3gio_bar2_bar2_reg_8_1_0_0_0_2_ ( + .I0(com_cmm_u_cmm_cfgspace_N_44857_i), + .I1(com_cmm_u_cmm_cfgspace_N_48892_i), + .I2(cfg_cfg_5072[130]), + .I3(com_cmm_cfg_wr_data[26]), + .LO(com_cmm_u_cmm_cfgspace_bar2_reg_8_1_0_0_0[2]) + ); + defparam com_cmm_u_cmm_cfgspace_x3gio_bar3_bar3_reg_8_1_0_0_0_0_.INIT = 16'h4FCF; + LUT4_L com_cmm_u_cmm_cfgspace_x3gio_bar3_bar3_reg_8_1_0_0_0_0_ ( + .I0(com_cmm_u_cmm_cfgspace_N_44858_i), + .I1(com_cmm_u_cmm_cfgspace_N_48891_i), + .I2(cfg_cfg_5072[160]), + .I3(com_cmm_cfg_wr_data[24]), + .LO(com_cmm_u_cmm_cfgspace_bar3_reg_8_1_0_0_0_0_) + ); + defparam com_cmm_u_cmm_cfgspace_x3gio_decodepipe_h_sel_0x_3_0_0_0_0.INIT = 16'h1333; + LUT4 com_cmm_u_cmm_cfgspace_x3gio_decodepipe_h_sel_0x_3_0_0_0_0 ( + .I0(com_cmm_u_cmm_cfgspace_N_48842_i), + .I1(com_cmm_u_cmm_cfgspace_N_49170), + .I2(com_cmm_u_cmm_cfgspace_N_50496), + .I3(com_cmm_u_cmm_cfgspace_sel_encodex_en_3_i_0_a2_4_2_4652), + .O(com_cmm_u_cmm_cfgspace_sel_0x_3_0_0_0_0) + ); + defparam com_cmm_u_cmm_cfgspace_x3gio_decodepipe_h_sel_4x_3_0_0_0_a3.INIT = 8'h20; + LUT3_L com_cmm_u_cmm_cfgspace_x3gio_decodepipe_h_sel_4x_3_0_0_0_a3 ( + .I0(com_cmm_u_cmm_cfgspace_N_48973_i), + .I1(cfg_dwaddr_5069[3]), + .I2(cfg_dwaddr_5069[4]), + .LO(com_cmm_u_cmm_cfgspace_N_50464) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_01_7_0_am_24_.INIT = 16'hC0AA; + LUT4 com_cmm_u_cmm_cfgspace_low_addr_01_7_0_am_24_ ( + .I0(com_cmm_u_cmm_cfgspace_N_3958), + .I1(com_cmm_u_cmm_cfgspace_N_50497), + .I2(com_cmm_u_cmm_cfgspace_N_51589), + .I3(com_cmm_u_cmm_cfgspace_sel_encodex_2[2]), + .O(com_cmm_u_cmm_cfgspace_low_addr_01_7_0_am_24__4654) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_01_7_0_bm_24_.INIT = 16'hA00C; + LUT4 com_cmm_u_cmm_cfgspace_low_addr_01_7_0_bm_24_ ( + .I0(cfg_cfg_5072[680]), + .I1(com_cmm_bar1_reg[24]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex_2[1]), + .I3(com_cmm_u_cmm_cfgspace_sel_encodex_2[2]), + .O(com_cmm_u_cmm_cfgspace_low_addr_01_7_0_bm_24__4653) + ); + MUXF5 com_cmm_u_cmm_cfgspace_low_addr_01_7_0_24_ ( + .I0(com_cmm_u_cmm_cfgspace_low_addr_01_7_0_am_24__4654), + .I1(com_cmm_u_cmm_cfgspace_low_addr_01_7_0_bm_24__4653), + .O(com_cmm_u_cmm_cfgspace_low_addr_01[24]), + .S(com_cmm_u_cmm_cfgspace_sel_encodex[0]) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_01_7_0_am_25_.INIT = 16'hAAC0; + LUT4 com_cmm_u_cmm_cfgspace_low_addr_01_7_0_am_25_ ( + .I0(com_cmm_u_cmm_cfgspace_N_50219), + .I1(com_cmm_bar5_reg[25]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex_2[1]), + .I3(com_cmm_u_cmm_cfgspace_sel_encodex_2[2]), + .O(com_cmm_u_cmm_cfgspace_low_addr_01_7_0_am_25__4656) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_01_7_0_bm_25_.INIT = 16'hA00C; + LUT4 com_cmm_u_cmm_cfgspace_low_addr_01_7_0_bm_25_ ( + .I0(cfg_cfg_5072[681]), + .I1(com_cmm_bar1_reg[25]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex_2[1]), + .I3(com_cmm_u_cmm_cfgspace_sel_encodex_2[2]), + .O(com_cmm_u_cmm_cfgspace_low_addr_01_7_0_bm_25__4655) + ); + MUXF5 com_cmm_u_cmm_cfgspace_low_addr_01_7_0_25_ ( + .I0(com_cmm_u_cmm_cfgspace_low_addr_01_7_0_am_25__4656), + .I1(com_cmm_u_cmm_cfgspace_low_addr_01_7_0_bm_25__4655), + .O(com_cmm_u_cmm_cfgspace_low_addr_01[25]), + .S(com_cmm_u_cmm_cfgspace_sel_encodex[0]) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_01_7_0_am_26_.INIT = 16'hAAC0; + LUT4 com_cmm_u_cmm_cfgspace_low_addr_01_7_0_am_26_ ( + .I0(com_cmm_u_cmm_cfgspace_N_50220), + .I1(com_cmm_bar5_reg[26]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex_2[1]), + .I3(com_cmm_u_cmm_cfgspace_sel_encodex_2[2]), + .O(com_cmm_u_cmm_cfgspace_low_addr_01_7_0_am_26__4658) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_01_7_0_bm_26_.INIT = 16'hA00C; + LUT4 com_cmm_u_cmm_cfgspace_low_addr_01_7_0_bm_26_ ( + .I0(cfg_cfg_5072[682]), + .I1(com_cmm_bar1_reg[26]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex_2[1]), + .I3(com_cmm_u_cmm_cfgspace_sel_encodex_2[2]), + .O(com_cmm_u_cmm_cfgspace_low_addr_01_7_0_bm_26__4657) + ); + MUXF5 com_cmm_u_cmm_cfgspace_low_addr_01_7_0_26_ ( + .I0(com_cmm_u_cmm_cfgspace_low_addr_01_7_0_am_26__4658), + .I1(com_cmm_u_cmm_cfgspace_low_addr_01_7_0_bm_26__4657), + .O(com_cmm_u_cmm_cfgspace_low_addr_01[26]), + .S(com_cmm_u_cmm_cfgspace_sel_encodex[0]) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_01_7_0_am_27_.INIT = 16'hC0AA; + LUT4 com_cmm_u_cmm_cfgspace_low_addr_01_7_0_am_27_ ( + .I0(com_cmm_u_cmm_cfgspace_N_3961), + .I1(com_cmm_u_cmm_cfgspace_N_50497), + .I2(com_cmm_u_cmm_cfgspace_N_51592), + .I3(com_cmm_u_cmm_cfgspace_sel_encodex_2[2]), + .O(com_cmm_u_cmm_cfgspace_low_addr_01_7_0_am_27__4660) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_01_7_0_bm_27_.INIT = 16'hA00C; + LUT4 com_cmm_u_cmm_cfgspace_low_addr_01_7_0_bm_27_ ( + .I0(cfg_cfg_5072[683]), + .I1(com_cmm_bar1_reg[27]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex_2[1]), + .I3(com_cmm_u_cmm_cfgspace_sel_encodex_2[2]), + .O(com_cmm_u_cmm_cfgspace_low_addr_01_7_0_bm_27__4659) + ); + MUXF5 com_cmm_u_cmm_cfgspace_low_addr_01_7_0_27_ ( + .I0(com_cmm_u_cmm_cfgspace_low_addr_01_7_0_am_27__4660), + .I1(com_cmm_u_cmm_cfgspace_low_addr_01_7_0_bm_27__4659), + .O(com_cmm_u_cmm_cfgspace_low_addr_01[27]), + .S(com_cmm_u_cmm_cfgspace_sel_encodex[0]) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_01_7_0_am_28_.INIT = 16'hC0AA; + LUT4 com_cmm_u_cmm_cfgspace_low_addr_01_7_0_am_28_ ( + .I0(com_cmm_u_cmm_cfgspace_N_3962), + .I1(com_cmm_u_cmm_cfgspace_N_50497), + .I2(com_cmm_u_cmm_cfgspace_N_51593), + .I3(com_cmm_u_cmm_cfgspace_sel_encodex_2[2]), + .O(com_cmm_u_cmm_cfgspace_low_addr_01_7_0_am_28__4662) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_01_7_0_bm_28_.INIT = 16'hA00C; + LUT4 com_cmm_u_cmm_cfgspace_low_addr_01_7_0_bm_28_ ( + .I0(cfg_cfg_5072[684]), + .I1(com_cmm_bar1_reg[28]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex_2[1]), + .I3(com_cmm_u_cmm_cfgspace_sel_encodex_2[2]), + .O(com_cmm_u_cmm_cfgspace_low_addr_01_7_0_bm_28__4661) + ); + MUXF5 com_cmm_u_cmm_cfgspace_low_addr_01_7_0_28_ ( + .I0(com_cmm_u_cmm_cfgspace_low_addr_01_7_0_am_28__4662), + .I1(com_cmm_u_cmm_cfgspace_low_addr_01_7_0_bm_28__4661), + .O(com_cmm_u_cmm_cfgspace_low_addr_01[28]), + .S(com_cmm_u_cmm_cfgspace_sel_encodex[0]) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_01_7_0_am_29_.INIT = 16'hC0AA; + LUT4 com_cmm_u_cmm_cfgspace_low_addr_01_7_0_am_29_ ( + .I0(com_cmm_u_cmm_cfgspace_N_3963), + .I1(com_cmm_u_cmm_cfgspace_N_50497), + .I2(com_cmm_u_cmm_cfgspace_N_51594), + .I3(com_cmm_u_cmm_cfgspace_sel_encodex_2[2]), + .O(com_cmm_u_cmm_cfgspace_low_addr_01_7_0_am_29__4664) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_01_7_0_bm_29_.INIT = 16'hA00C; + LUT4 com_cmm_u_cmm_cfgspace_low_addr_01_7_0_bm_29_ ( + .I0(cfg_cfg_5072[685]), + .I1(com_cmm_bar1_reg[29]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex_2[1]), + .I3(com_cmm_u_cmm_cfgspace_sel_encodex_2[2]), + .O(com_cmm_u_cmm_cfgspace_low_addr_01_7_0_bm_29__4663) + ); + MUXF5 com_cmm_u_cmm_cfgspace_low_addr_01_7_0_29_ ( + .I0(com_cmm_u_cmm_cfgspace_low_addr_01_7_0_am_29__4664), + .I1(com_cmm_u_cmm_cfgspace_low_addr_01_7_0_bm_29__4663), + .O(com_cmm_u_cmm_cfgspace_low_addr_01[29]), + .S(com_cmm_u_cmm_cfgspace_sel_encodex[0]) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_01_7_0_am_30_.INIT = 16'hC0AA; + LUT4 com_cmm_u_cmm_cfgspace_low_addr_01_7_0_am_30_ ( + .I0(com_cmm_u_cmm_cfgspace_N_3964), + .I1(com_cmm_u_cmm_cfgspace_N_50497), + .I2(com_cmm_u_cmm_cfgspace_N_51595), + .I3(com_cmm_u_cmm_cfgspace_sel_encodex_2[2]), + .O(com_cmm_u_cmm_cfgspace_low_addr_01_7_0_am_30__4666) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_01_7_0_bm_30_.INIT = 16'hA00C; + LUT4 com_cmm_u_cmm_cfgspace_low_addr_01_7_0_bm_30_ ( + .I0(cfg_cfg_5072[686]), + .I1(com_cmm_bar1_reg[30]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex_2[1]), + .I3(com_cmm_u_cmm_cfgspace_sel_encodex_2[2]), + .O(com_cmm_u_cmm_cfgspace_low_addr_01_7_0_bm_30__4665) + ); + MUXF5 com_cmm_u_cmm_cfgspace_low_addr_01_7_0_30_ ( + .I0(com_cmm_u_cmm_cfgspace_low_addr_01_7_0_am_30__4666), + .I1(com_cmm_u_cmm_cfgspace_low_addr_01_7_0_bm_30__4665), + .O(com_cmm_u_cmm_cfgspace_low_addr_01[30]), + .S(com_cmm_u_cmm_cfgspace_sel_encodex[0]) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_01_7_0_am_31_.INIT = 16'hC0AA; + LUT4 com_cmm_u_cmm_cfgspace_low_addr_01_7_0_am_31_ ( + .I0(com_cmm_u_cmm_cfgspace_N_3965), + .I1(com_cmm_u_cmm_cfgspace_N_50497), + .I2(com_cmm_u_cmm_cfgspace_N_51596), + .I3(com_cmm_u_cmm_cfgspace_sel_encodex_2[2]), + .O(com_cmm_u_cmm_cfgspace_low_addr_01_7_0_am_31__4668) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_01_7_0_bm_31_.INIT = 16'hA00C; + LUT4 com_cmm_u_cmm_cfgspace_low_addr_01_7_0_bm_31_ ( + .I0(cfg_cfg_5072[687]), + .I1(com_cmm_bar1_reg[31]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex_2[1]), + .I3(com_cmm_u_cmm_cfgspace_sel_encodex_2[2]), + .O(com_cmm_u_cmm_cfgspace_low_addr_01_7_0_bm_31__4667) + ); + MUXF5 com_cmm_u_cmm_cfgspace_low_addr_01_7_0_31_ ( + .I0(com_cmm_u_cmm_cfgspace_low_addr_01_7_0_am_31__4668), + .I1(com_cmm_u_cmm_cfgspace_low_addr_01_7_0_bm_31__4667), + .O(com_cmm_u_cmm_cfgspace_low_addr_01[31]), + .S(com_cmm_u_cmm_cfgspace_sel_encodex[0]) + ); + defparam com_cmm_u_cmm_cfgspace_x3gio_decodepipe_h_N_68405_i.INIT = 16'hAEAA; + LUT4_L com_cmm_u_cmm_cfgspace_x3gio_decodepipe_h_N_68405_i ( + .I0(com_cmm_u_cmm_cfgspace_N_49176), + .I1(com_cmm_u_cmm_cfgspace_N_49177_1), + .I2(com_cmm_cfg_addr[2]), + .I3(com_cmm_cfg_addr[3]), + .LO(com_cmm_u_cmm_cfgspace_N_68405_i) + ); + defparam com_cmm_u_cmm_cfgspace_x3gio_decodepipe_h_N_68711_i.INIT = 16'hCCEC; + LUT4_L com_cmm_u_cmm_cfgspace_x3gio_decodepipe_h_N_68711_i ( + .I0(com_cmm_u_cmm_cfgspace_N_49177_1), + .I1(com_cmm_u_cmm_cfgspace_N_50463), + .I2(com_cmm_cfg_addr[2]), + .I3(com_cmm_cfg_addr[3]), + .LO(com_cmm_u_cmm_cfgspace_N_68711_i) + ); + defparam com_cmm_u_cmm_cfgspace_x3gio_decodepipe_h_N_68404_i.INIT = 16'hCCCE; + LUT4_L com_cmm_u_cmm_cfgspace_x3gio_decodepipe_h_N_68404_i ( + .I0(com_cmm_u_cmm_cfgspace_N_49177_1), + .I1(com_cmm_u_cmm_cfgspace_N_50464), + .I2(com_cmm_cfg_addr[2]), + .I3(com_cmm_cfg_addr[3]), + .LO(com_cmm_u_cmm_cfgspace_N_68404_i) + ); + defparam com_cmm_u_cmm_cfgspace_x3gio_decodepipe_h_N_68336_i.INIT = 16'hEAAA; + LUT4_L com_cmm_u_cmm_cfgspace_x3gio_decodepipe_h_N_68336_i ( + .I0(com_cmm_u_cmm_cfgspace_N_42097), + .I1(com_cmm_u_cmm_cfgspace_N_50466_2), + .I2(cfg_dwaddr_5069[2]), + .I3(cfg_dwaddr_5069[3]), + .LO(com_cmm_u_cmm_cfgspace_N_68336_i) + ); + defparam com_cmm_u_cmm_cfgspace_x3gio_decodepipe_h_N_68403_i.INIT = 16'hCCEC; + LUT4_L com_cmm_u_cmm_cfgspace_x3gio_decodepipe_h_N_68403_i ( + .I0(com_cmm_u_cmm_cfgspace_N_48973_i), + .I1(com_cmm_u_cmm_cfgspace_N_49173), + .I2(cfg_dwaddr_5069[3]), + .I3(cfg_dwaddr_5069[4]), + .LO(com_cmm_u_cmm_cfgspace_N_68403_i) + ); + defparam com_cmm_u_cmm_cfgspace_x3gio_decodepipe_h_N_68402_i.INIT = 16'hAAEA; + LUT4_L com_cmm_u_cmm_cfgspace_x3gio_decodepipe_h_N_68402_i ( + .I0(com_cmm_u_cmm_cfgspace_N_49172), + .I1(com_cmm_u_cmm_cfgspace_N_50466_2), + .I2(cfg_dwaddr_5069[2]), + .I3(cfg_dwaddr_5069[3]), + .LO(com_cmm_u_cmm_cfgspace_N_68402_i) + ); + defparam com_cmm_u_cmm_cfgspace_x3gio_decodepipe_h_N_68101_i.INIT = 16'h02FF; + LUT4_L com_cmm_u_cmm_cfgspace_x3gio_decodepipe_h_N_68101_i ( + .I0(com_cmm_u_cmm_cfgspace_N_48973_i), + .I1(cfg_dwaddr_5069[3]), + .I2(cfg_dwaddr_5069[4]), + .I3(com_cmm_u_cmm_cfgspace_sel_0x_3_0_0_0_0), + .LO(com_cmm_u_cmm_cfgspace_N_68101_i) + ); + defparam com_cmm_u_cmm_cfgspace_x3gio_decodepipe_l_sel_x0_3_i_0_0.INIT = 16'h4404; + LUT4_L com_cmm_u_cmm_cfgspace_x3gio_decodepipe_l_sel_x0_3_i_0_0 ( + .I0(com_cmm_u_cmm_cfgspace_N_48849), + .I1(com_cmm_u_cmm_cfgspace_N_48875_i), + .I2(com_cmm_u_cmm_cfgspace_N_50520_1), + .I3(com_cmm_cfg_be[0]), + .LO(com_cmm_u_cmm_cfgspace_N_28239_i) + ); + defparam com_cmm_u_cmm_cfgspace_x3gio_decodepipe_l_sel_xf_3_i_0_0.INIT = 16'h8808; + LUT4_L com_cmm_u_cmm_cfgspace_x3gio_decodepipe_l_sel_xf_3_i_0_0 ( + .I0(com_cmm_u_cmm_cfgspace_N_48849), + .I1(com_cmm_u_cmm_cfgspace_N_48876_i), + .I2(com_cmm_u_cmm_cfgspace_N_50520_1), + .I3(com_cmm_cfg_be[3]), + .LO(com_cmm_u_cmm_cfgspace_N_28269_i) + ); + defparam com_cmm_u_cmm_cfgspace_x3gio_decodepipe_l_sel_xe_3_i_0_0.INIT = 16'h8808; + LUT4_L com_cmm_u_cmm_cfgspace_x3gio_decodepipe_l_sel_xe_3_i_0_0 ( + .I0(com_cmm_u_cmm_cfgspace_N_48849), + .I1(com_cmm_u_cmm_cfgspace_N_48876_i), + .I2(com_cmm_u_cmm_cfgspace_N_50520_1), + .I3(com_cmm_cfg_be[2]), + .LO(com_cmm_u_cmm_cfgspace_N_28267_i) + ); + defparam com_cmm_u_cmm_cfgspace_x3gio_decodepipe_l_sel_xd_3_i_0_0.INIT = 16'h8808; + LUT4_L com_cmm_u_cmm_cfgspace_x3gio_decodepipe_l_sel_xd_3_i_0_0 ( + .I0(com_cmm_u_cmm_cfgspace_N_48849), + .I1(com_cmm_u_cmm_cfgspace_N_48876_i), + .I2(com_cmm_u_cmm_cfgspace_N_50520_1), + .I3(com_cmm_cfg_be[1]), + .LO(com_cmm_u_cmm_cfgspace_N_28265_i) + ); + defparam com_cmm_u_cmm_cfgspace_x3gio_decodepipe_l_sel_xc_3_i_0_0.INIT = 16'h8808; + LUT4_L com_cmm_u_cmm_cfgspace_x3gio_decodepipe_l_sel_xc_3_i_0_0 ( + .I0(com_cmm_u_cmm_cfgspace_N_48849), + .I1(com_cmm_u_cmm_cfgspace_N_48876_i), + .I2(com_cmm_u_cmm_cfgspace_N_50520_1), + .I3(com_cmm_cfg_be[0]), + .LO(com_cmm_u_cmm_cfgspace_N_28263_i) + ); + defparam com_cmm_u_cmm_cfgspace_x3gio_decodepipe_l_sel_xb_3_i_0_0.INIT = 16'h8808; + LUT4_L com_cmm_u_cmm_cfgspace_x3gio_decodepipe_l_sel_xb_3_i_0_0 ( + .I0(com_cmm_u_cmm_cfgspace_N_48849), + .I1(com_cmm_u_cmm_cfgspace_N_48875_i), + .I2(com_cmm_u_cmm_cfgspace_N_50520_1), + .I3(com_cmm_cfg_be[3]), + .LO(com_cmm_u_cmm_cfgspace_N_28261_i) + ); + defparam com_cmm_u_cmm_cfgspace_x3gio_decodepipe_l_sel_xa_3_i_0_0.INIT = 16'h8808; + LUT4_L com_cmm_u_cmm_cfgspace_x3gio_decodepipe_l_sel_xa_3_i_0_0 ( + .I0(com_cmm_u_cmm_cfgspace_N_48849), + .I1(com_cmm_u_cmm_cfgspace_N_48875_i), + .I2(com_cmm_u_cmm_cfgspace_N_50520_1), + .I3(com_cmm_cfg_be[2]), + .LO(com_cmm_u_cmm_cfgspace_N_28259_i) + ); + defparam com_cmm_u_cmm_cfgspace_x3gio_decodepipe_l_sel_x9_3_i_0_0.INIT = 16'h8808; + LUT4_L com_cmm_u_cmm_cfgspace_x3gio_decodepipe_l_sel_x9_3_i_0_0 ( + .I0(com_cmm_u_cmm_cfgspace_N_48849), + .I1(com_cmm_u_cmm_cfgspace_N_48875_i), + .I2(com_cmm_u_cmm_cfgspace_N_50520_1), + .I3(com_cmm_cfg_be[1]), + .LO(com_cmm_u_cmm_cfgspace_N_28257_i) + ); + defparam com_cmm_u_cmm_cfgspace_x3gio_decodepipe_l_sel_x8_3_i_0_0.INIT = 16'h8808; + LUT4_L com_cmm_u_cmm_cfgspace_x3gio_decodepipe_l_sel_x8_3_i_0_0 ( + .I0(com_cmm_u_cmm_cfgspace_N_48849), + .I1(com_cmm_u_cmm_cfgspace_N_48875_i), + .I2(com_cmm_u_cmm_cfgspace_N_50520_1), + .I3(com_cmm_cfg_be[0]), + .LO(com_cmm_u_cmm_cfgspace_N_28255_i) + ); + defparam com_cmm_u_cmm_cfgspace_x3gio_decodepipe_l_sel_x7_3_i_0_0.INIT = 16'h4404; + LUT4_L com_cmm_u_cmm_cfgspace_x3gio_decodepipe_l_sel_x7_3_i_0_0 ( + .I0(com_cmm_u_cmm_cfgspace_N_48849), + .I1(com_cmm_u_cmm_cfgspace_N_48876_i), + .I2(com_cmm_u_cmm_cfgspace_N_50520_1), + .I3(com_cmm_cfg_be[3]), + .LO(com_cmm_u_cmm_cfgspace_N_28253_i) + ); + defparam com_cmm_u_cmm_cfgspace_x3gio_decodepipe_l_sel_x6_3_i_0_0.INIT = 16'h4404; + LUT4_L com_cmm_u_cmm_cfgspace_x3gio_decodepipe_l_sel_x6_3_i_0_0 ( + .I0(com_cmm_u_cmm_cfgspace_N_48849), + .I1(com_cmm_u_cmm_cfgspace_N_48876_i), + .I2(com_cmm_u_cmm_cfgspace_N_50520_1), + .I3(com_cmm_cfg_be[2]), + .LO(com_cmm_u_cmm_cfgspace_N_28251_i) + ); + defparam com_cmm_u_cmm_cfgspace_x3gio_decodepipe_l_sel_x5_3_i_0_0.INIT = 16'h4404; + LUT4_L com_cmm_u_cmm_cfgspace_x3gio_decodepipe_l_sel_x5_3_i_0_0 ( + .I0(com_cmm_u_cmm_cfgspace_N_48849), + .I1(com_cmm_u_cmm_cfgspace_N_48876_i), + .I2(com_cmm_u_cmm_cfgspace_N_50520_1), + .I3(com_cmm_cfg_be[1]), + .LO(com_cmm_u_cmm_cfgspace_N_28249_i) + ); + defparam com_cmm_u_cmm_cfgspace_x3gio_decodepipe_l_sel_x4_3_i_0_0.INIT = 16'h4404; + LUT4_L com_cmm_u_cmm_cfgspace_x3gio_decodepipe_l_sel_x4_3_i_0_0 ( + .I0(com_cmm_u_cmm_cfgspace_N_48849), + .I1(com_cmm_u_cmm_cfgspace_N_48876_i), + .I2(com_cmm_u_cmm_cfgspace_N_50520_1), + .I3(com_cmm_cfg_be[0]), + .LO(com_cmm_u_cmm_cfgspace_N_28247_i) + ); + defparam com_cmm_u_cmm_cfgspace_x3gio_decodepipe_l_sel_x3_3_i_0_0.INIT = 16'h4404; + LUT4_L com_cmm_u_cmm_cfgspace_x3gio_decodepipe_l_sel_x3_3_i_0_0 ( + .I0(com_cmm_u_cmm_cfgspace_N_48849), + .I1(com_cmm_u_cmm_cfgspace_N_48875_i), + .I2(com_cmm_u_cmm_cfgspace_N_50520_1), + .I3(com_cmm_cfg_be[3]), + .LO(com_cmm_u_cmm_cfgspace_N_28245_i) + ); + defparam com_cmm_u_cmm_cfgspace_x3gio_decodepipe_l_sel_x2_3_i_0_0.INIT = 16'h4404; + LUT4_L com_cmm_u_cmm_cfgspace_x3gio_decodepipe_l_sel_x2_3_i_0_0 ( + .I0(com_cmm_u_cmm_cfgspace_N_48849), + .I1(com_cmm_u_cmm_cfgspace_N_48875_i), + .I2(com_cmm_u_cmm_cfgspace_N_50520_1), + .I3(com_cmm_cfg_be[2]), + .LO(com_cmm_u_cmm_cfgspace_N_28243_i) + ); + defparam com_cmm_u_cmm_cfgspace_x3gio_decodepipe_l_sel_x1_3_i_0_0.INIT = 16'h4404; + LUT4_L com_cmm_u_cmm_cfgspace_x3gio_decodepipe_l_sel_x1_3_i_0_0 ( + .I0(com_cmm_u_cmm_cfgspace_N_48849), + .I1(com_cmm_u_cmm_cfgspace_N_48875_i), + .I2(com_cmm_u_cmm_cfgspace_N_50520_1), + .I3(com_cmm_cfg_be[1]), + .LO(com_cmm_u_cmm_cfgspace_N_28241_i) + ); + defparam com_cmm_u_cmm_cfgspace_x3gio_pmcsr_pme_pmcsr_21_0_0_i_0_1_.INIT = 16'h00D8; + LUT4_L com_cmm_u_cmm_cfgspace_x3gio_pmcsr_pme_pmcsr_21_0_0_i_0_1_ ( + .I0(com_cmm_u_cmm_cfgspace_pme_pmcsr_21_0_i_o3[0]), + .I1(com_cmm_cfg_wr_data[25]), + .I2(com_cmm_pme_pmcsr[1]), + .I3(com_cmm_rst_267), + .LO(com_cmm_u_cmm_cfgspace_N_43646_i) + ); + defparam com_cmm_u_cmm_cfgspace_x3gio_pmcsr_pme_pmcsr_21_0_i_0_0_.INIT = 16'h00D8; + LUT4_L com_cmm_u_cmm_cfgspace_x3gio_pmcsr_pme_pmcsr_21_0_i_0_0_ ( + .I0(com_cmm_u_cmm_cfgspace_pme_pmcsr_21_0_i_o3[0]), + .I1(com_cmm_cfg_wr_data[24]), + .I2(com_cmm_pme_pmcsr[0]), + .I3(com_cmm_rst_267), + .LO(com_cmm_u_cmm_cfgspace_N_43644_i) + ); + defparam com_cmm_u_cmm_cfgspace_x3gio_status_status_18_iv_0_0_0_12_.INIT = 16'hFF4C; + LUT4_L com_cmm_u_cmm_cfgspace_x3gio_status_status_18_iv_0_0_0_12_ ( + .I0(com_cmm_u_cmm_cfgspace_N_45424_1), + .I1(NlwRenamedSig_OI_cfg_status_12_), + .I2(com_cmm_cfg_wr_data_4_), + .I3(com_cmm_u_cmm_cfgspace_set_receivedtargetabort_4749), + .LO(com_cmm_u_cmm_cfgspace_N_8858_i) + ); + defparam com_cmm_u_cmm_cfgspace_x3gio_status_status_22_iv_0_11_.INIT = 16'hFF4C; + LUT4_L com_cmm_u_cmm_cfgspace_x3gio_status_status_22_iv_0_11_ ( + .I0(com_cmm_u_cmm_cfgspace_N_45424_1), + .I1(NlwRenamedSig_OI_cfg_status_11_), + .I2(com_cmm_cfg_wr_data_3_), + .I3(com_cmm_u_cmm_cfgspace_set_signaledtargetabort_4746), + .LO(com_cmm_u_cmm_cfgspace_N_8857_i) + ); + defparam com_cmm_u_cmm_cfgspace_x3gio_status_status_28_iv_0_8_.INIT = 16'hFF4C; + LUT4_L com_cmm_u_cmm_cfgspace_x3gio_status_status_28_iv_0_8_ ( + .I0(com_cmm_u_cmm_cfgspace_N_45424_1), + .I1(NlwRenamedSig_OI_cfg_status_8_), + .I2(com_cmm_cfg_wr_data_0_), + .I3(com_cmm_u_cmm_cfgspace_set_masterdataparityerror_4751), + .LO(com_cmm_u_cmm_cfgspace_N_8856_i) + ); + defparam com_cmm_u_cmm_cfgspace_x3gio_pmcsr_pme_pmcsr_20_iv_0_0_0_15_.INIT = 16'hFF70; + LUT4_L com_cmm_u_cmm_cfgspace_x3gio_pmcsr_pme_pmcsr_20_iv_0_0_0_15_ ( + .I0(N_44884_i), + .I1(com_cmm_cfg_wr_data_23_), + .I2(com_cmm_u_cmm_cfgspace_pme_pmcsr[15]), + .I3(com_cmm_u_cmm_cfgspace_set_signaledpme_4748), + .LO(com_cmm_u_cmm_cfgspace_N_8855_i) + ); + defparam com_cmm_u_cmm_cfgspace_x3gio_pmcsr_pme_pmcsr_21_0_a2_0_a2_0_a2_0_a2_14_.INIT = 16'hAC00; + LUT4_L com_cmm_u_cmm_cfgspace_x3gio_pmcsr_pme_pmcsr_21_0_a2_0_a2_0_a2_0_a2_14_ ( + .I0(com_cmm_u_cmm_cfgspace_N_51532), + .I1(com_cmm_u_cmm_cfgspace_N_51562), + .I2(com_cmm_u_cmm_cfgspace_pme_pmcsr[10]), + .I3(com_cmm_u_cmm_cfgspace_pme_pmcsr_21_1[14]), + .LO(com_cmm_u_cmm_cfgspace_pme_pmcsr_21[14]) + ); + defparam com_cmm_u_cmm_cfgspace_x3gio_pmcsr_pme_pmcsr_21_0_a2_0_a2_0_a2_0_a2_13_.INIT = 16'hAC00; + LUT4_L com_cmm_u_cmm_cfgspace_x3gio_pmcsr_pme_pmcsr_21_0_a2_0_a2_0_a2_0_a2_13_ ( + .I0(com_cmm_u_cmm_cfgspace_N_51531), + .I1(com_cmm_u_cmm_cfgspace_N_51561), + .I2(com_cmm_u_cmm_cfgspace_pme_pmcsr[10]), + .I3(com_cmm_u_cmm_cfgspace_pme_pmcsr_21_1[14]), + .LO(com_cmm_u_cmm_cfgspace_pme_pmcsr_21[13]) + ); + defparam com_cmm_u_cmm_cfgspace_x3gio_pmcsr_pme_pmcsr_21_0_0_i_0_12_.INIT = 16'h00C4; + LUT4_L com_cmm_u_cmm_cfgspace_x3gio_pmcsr_pme_pmcsr_21_0_0_i_0_12_ ( + .I0(N_44884_i), + .I1(com_cmm_u_cmm_cfgspace_N_49015), + .I2(com_cmm_cfg_wr_data_20_), + .I3(com_cmm_rst_267), + .LO(com_cmm_u_cmm_cfgspace_N_40379_i) + ); + defparam com_cmm_u_cmm_cfgspace_x3gio_pmcsr_pme_pmcsr_21_i_i_i_11_.INIT = 16'h00D8; + LUT4_L com_cmm_u_cmm_cfgspace_x3gio_pmcsr_pme_pmcsr_21_i_i_i_11_ ( + .I0(N_44884_i), + .I1(com_cmm_cfg_wr_data_19_), + .I2(com_cmm_u_cmm_cfgspace_pme_pmcsr[11]), + .I3(com_cmm_rst_267), + .LO(com_cmm_u_cmm_cfgspace_N_44495_i) + ); + defparam com_cmm_u_cmm_cfgspace_x3gio_pmcsr_pme_pmcsr_21_0_0_i_10_.INIT = 16'h00D8; + LUT4_L com_cmm_u_cmm_cfgspace_x3gio_pmcsr_pme_pmcsr_21_0_0_i_10_ ( + .I0(N_44884_i), + .I1(com_cmm_cfg_wr_data_18_), + .I2(com_cmm_u_cmm_cfgspace_pme_pmcsr[10]), + .I3(com_cmm_rst_267), + .LO(com_cmm_u_cmm_cfgspace_N_43650_i) + ); + defparam com_cmm_u_cmm_cfgspace_x3gio_pmcsr_pme_pmcsr_21_0_0_i_9_.INIT = 16'h00D8; + LUT4_L com_cmm_u_cmm_cfgspace_x3gio_pmcsr_pme_pmcsr_21_0_0_i_9_ ( + .I0(N_44884_i), + .I1(com_cmm_cfg_wr_data_17_), + .I2(com_cmm_u_cmm_cfgspace_pme_pmcsr[9]), + .I3(com_cmm_rst_267), + .LO(com_cmm_u_cmm_cfgspace_N_43648_i) + ); + defparam com_cmm_u_cmm_cfgspace_next_state_0_sqmuxa_i_0_0_0.INIT = 16'hE000; + LUT4_L com_cmm_u_cmm_cfgspace_next_state_0_sqmuxa_i_0_0_0 ( + .I0(com_cmm_N_48846_i), + .I1(com_cmm_cfg_rd), + .I2(com_cmm_state_1_), + .I3(com_cmm_u_cmm_cfgspace_state_0__4782), + .LO(com_cmm_u_cmm_cfgspace_N_14826_i) + ); + defparam com_cmm_u_cmm_cfgspace_next_state_1_sqmuxa_i_0_0_0.INIT = 4'h2; + LUT2_L com_cmm_u_cmm_cfgspace_next_state_1_sqmuxa_i_0_0_0 ( + .I0(com_cmm_u_cmm_cfgspace_N_42538_1), + .I1(cfg_rd_en_n), + .LO(com_cmm_u_cmm_cfgspace_N_14828_i) + ); + defparam com_cmm_u_cmm_cfgspace_N_68102_i.INIT = 16'hFFF8; + LUT4_L com_cmm_u_cmm_cfgspace_N_68102_i ( + .I0(com_cmm_u_cmm_cfgspace_N_42538_1), + .I1(cfg_rd_en_n), + .I2(com_cmm_u_cmm_cfgspace_cfg2ulm_valid), + .I3(com_cmm_state_6_), + .LO(com_cmm_u_cmm_cfgspace_N_68102_i_4781) + ); + defparam com_cmm_u_cmm_cfgspace_x3gio_dsts_x_dsts_9_iv_0_0_0_3_.INIT = 16'hFF4C; + LUT4_L com_cmm_u_cmm_cfgspace_x3gio_dsts_x_dsts_9_iv_0_0_0_3_ ( + .I0(com_cmm_u_cmm_cfgspace_N_45410_1), + .I1(NlwRenamedSig_OI_cfg_dstatus_3_), + .I2(com_cmm_cfg_wr_data_11_), + .I3(com_cmm_u_cmm_cfgspace_set_unsupportedreq_4742), + .LO(com_cmm_u_cmm_cfgspace_N_8854_i) + ); + defparam com_cmm_u_cmm_cfgspace_x3gio_dsts_x_dsts_13_iv_0_0_0_2_.INIT = 16'hFF4C; + LUT4_L com_cmm_u_cmm_cfgspace_x3gio_dsts_x_dsts_13_iv_0_0_0_2_ ( + .I0(com_cmm_u_cmm_cfgspace_N_45410_1), + .I1(NlwRenamedSig_OI_cfg_dstatus_2_), + .I2(com_cmm_cfg_wr_data_10_), + .I3(com_cmm_u_cmm_cfgspace_set_detectedfatal_4744), + .LO(com_cmm_u_cmm_cfgspace_N_8853_i) + ); + defparam com_cmm_u_cmm_cfgspace_x3gio_dsts_x_dsts_17_iv_0_0_0_1_.INIT = 16'hFF4C; + LUT4_L com_cmm_u_cmm_cfgspace_x3gio_dsts_x_dsts_17_iv_0_0_0_1_ ( + .I0(com_cmm_u_cmm_cfgspace_N_45410_1), + .I1(NlwRenamedSig_OI_cfg_dstatus_1_), + .I2(com_cmm_cfg_wr_data_9_), + .I3(com_cmm_u_cmm_cfgspace_set_detectednonfatal_4743), + .LO(com_cmm_u_cmm_cfgspace_N_8852_i) + ); + defparam com_cmm_u_cmm_cfgspace_x3gio_dsts_x_dsts_21_iv_0_0_0_0_.INIT = 16'hFF4C; + LUT4_L com_cmm_u_cmm_cfgspace_x3gio_dsts_x_dsts_21_iv_0_0_0_0_ ( + .I0(com_cmm_u_cmm_cfgspace_N_45410_1), + .I1(NlwRenamedSig_OI_cfg_dstatus_0_), + .I2(com_cmm_cfg_wr_data_8_), + .I3(com_cmm_u_cmm_cfgspace_set_detectedcorrectable_4745), + .LO(com_cmm_u_cmm_cfgspace_N_8851_i) + ); + defparam com_cmm_u_cmm_cfgspace_x3gio_status_status_6_iv_0_0_0_15_.INIT = 16'hFF4C; + LUT4_L com_cmm_u_cmm_cfgspace_x3gio_status_status_6_iv_0_0_0_15_ ( + .I0(com_cmm_u_cmm_cfgspace_N_45424_1), + .I1(NlwRenamedSig_OI_cfg_status_15_), + .I2(com_cmm_cfg_wr_data_7_), + .I3(com_cmm_u_cmm_cfgspace_set_detectedparityerror_4752), + .LO(com_cmm_u_cmm_cfgspace_N_8861_i) + ); + defparam com_cmm_u_cmm_cfgspace_x3gio_status_status_10_iv_0_0_0_14_.INIT = 16'hFF4C; + LUT4_L com_cmm_u_cmm_cfgspace_x3gio_status_status_10_iv_0_0_0_14_ ( + .I0(com_cmm_u_cmm_cfgspace_N_45424_1), + .I1(NlwRenamedSig_OI_cfg_status_14_), + .I2(com_cmm_cfg_wr_data_6_), + .I3(com_cmm_u_cmm_cfgspace_set_signaledsystemerror_4747), + .LO(com_cmm_u_cmm_cfgspace_N_8860_i) + ); + defparam com_cmm_u_cmm_cfgspace_x3gio_status_status_14_iv_0_0_0_13_.INIT = 16'hFF4C; + LUT4_L com_cmm_u_cmm_cfgspace_x3gio_status_status_14_iv_0_0_0_13_ ( + .I0(com_cmm_u_cmm_cfgspace_N_45424_1), + .I1(NlwRenamedSig_OI_cfg_status_13_), + .I2(com_cmm_cfg_wr_data_5_), + .I3(com_cmm_u_cmm_cfgspace_set_receivedmasterabort_4750), + .LO(com_cmm_u_cmm_cfgspace_N_8859_i) + ); + defparam com_cmm_u_cmm_cfgspace_x3gio_bar1_N_68143_i.INIT = 16'h40FF; + LUT4_L com_cmm_u_cmm_cfgspace_x3gio_bar1_N_68143_i ( + .I0(com_cmm_u_cmm_cfgspace_N_44856_i), + .I1(com_cmm_u_cmm_cfgspace_N_48888_i), + .I2(com_cmm_bar1_reg[3]), + .I3(com_cmm_u_cmm_cfgspace_bar1_reg_8_1_0_0_0_0[3]), + .LO(com_cmm_u_cmm_cfgspace_N_68143_i) + ); + defparam com_cmm_u_cmm_cfgspace_x3gio_bar1_N_68008_i.INIT = 16'h40FF; + LUT4_L com_cmm_u_cmm_cfgspace_x3gio_bar1_N_68008_i ( + .I0(com_cmm_u_cmm_cfgspace_N_44856_i), + .I1(com_cmm_u_cmm_cfgspace_N_48888_i), + .I2(com_cmm_bar1_reg[2]), + .I3(com_cmm_u_cmm_cfgspace_bar1_reg_8_1_0_0_0[2]), + .LO(com_cmm_u_cmm_cfgspace_N_68008_i) + ); + defparam com_cmm_u_cmm_cfgspace_x3gio_bar1_N_68142_i.INIT = 16'h40FF; + LUT4_L com_cmm_u_cmm_cfgspace_x3gio_bar1_N_68142_i ( + .I0(com_cmm_u_cmm_cfgspace_N_44856_i), + .I1(com_cmm_u_cmm_cfgspace_N_48888_i), + .I2(com_cmm_bar1_reg[1]), + .I3(com_cmm_u_cmm_cfgspace_bar1_reg_8_1_0_0_0[1]), + .LO(com_cmm_u_cmm_cfgspace_N_68142_i) + ); + defparam com_cmm_u_cmm_cfgspace_x3gio_bar1_N_68007_i.INIT = 16'h40FF; + LUT4_L com_cmm_u_cmm_cfgspace_x3gio_bar1_N_68007_i ( + .I0(com_cmm_u_cmm_cfgspace_N_44856_i), + .I1(com_cmm_u_cmm_cfgspace_N_48888_i), + .I2(com_cmm_bar1_reg[0]), + .I3(com_cmm_u_cmm_cfgspace_bar1_reg_8_1_0_0_0[0]), + .LO(com_cmm_u_cmm_cfgspace_N_68007_i) + ); + defparam com_cmm_u_cmm_cfgspace_x3gio_bar2_N_68145_i.INIT = 16'h40FF; + LUT4_L com_cmm_u_cmm_cfgspace_x3gio_bar2_N_68145_i ( + .I0(com_cmm_u_cmm_cfgspace_N_44857_i), + .I1(com_cmm_u_cmm_cfgspace_N_48892_i), + .I2(com_cmm_bar2_reg[3]), + .I3(com_cmm_u_cmm_cfgspace_bar2_reg_8_1_0_0_0_0[3]), + .LO(com_cmm_u_cmm_cfgspace_N_68145_i) + ); + defparam com_cmm_u_cmm_cfgspace_x3gio_bar2_N_68010_i.INIT = 16'h40FF; + LUT4_L com_cmm_u_cmm_cfgspace_x3gio_bar2_N_68010_i ( + .I0(com_cmm_u_cmm_cfgspace_N_44857_i), + .I1(com_cmm_u_cmm_cfgspace_N_48892_i), + .I2(com_cmm_bar2_reg[2]), + .I3(com_cmm_u_cmm_cfgspace_bar2_reg_8_1_0_0_0[2]), + .LO(com_cmm_u_cmm_cfgspace_N_68010_i) + ); + defparam com_cmm_u_cmm_cfgspace_x3gio_bar2_N_68144_i.INIT = 16'h40FF; + LUT4_L com_cmm_u_cmm_cfgspace_x3gio_bar2_N_68144_i ( + .I0(com_cmm_u_cmm_cfgspace_N_44857_i), + .I1(com_cmm_u_cmm_cfgspace_N_48892_i), + .I2(com_cmm_bar2_reg[1]), + .I3(com_cmm_u_cmm_cfgspace_bar2_reg_8_1_0_0_0[1]), + .LO(com_cmm_u_cmm_cfgspace_N_68144_i) + ); + defparam com_cmm_u_cmm_cfgspace_x3gio_bar2_N_68009_i.INIT = 16'h40FF; + LUT4_L com_cmm_u_cmm_cfgspace_x3gio_bar2_N_68009_i ( + .I0(com_cmm_u_cmm_cfgspace_N_44857_i), + .I1(com_cmm_u_cmm_cfgspace_N_48892_i), + .I2(com_cmm_bar2_reg[0]), + .I3(com_cmm_u_cmm_cfgspace_bar2_reg_8_1_0_0_0[0]), + .LO(com_cmm_u_cmm_cfgspace_N_68009_i) + ); + defparam com_cmm_u_cmm_cfgspace_x3gio_bar3_N_68147_i.INIT = 16'h40FF; + LUT4_L com_cmm_u_cmm_cfgspace_x3gio_bar3_N_68147_i ( + .I0(com_cmm_u_cmm_cfgspace_N_44858_i), + .I1(com_cmm_u_cmm_cfgspace_N_48891_i), + .I2(com_cmm_bar3_reg[3]), + .I3(com_cmm_u_cmm_cfgspace_bar3_reg_8_1_0_0_0_0_3_), + .LO(com_cmm_u_cmm_cfgspace_N_68147_i) + ); + defparam com_cmm_u_cmm_cfgspace_x3gio_bar3_N_68012_i.INIT = 16'h40FF; + LUT4_L com_cmm_u_cmm_cfgspace_x3gio_bar3_N_68012_i ( + .I0(com_cmm_u_cmm_cfgspace_N_44858_i), + .I1(com_cmm_u_cmm_cfgspace_N_48891_i), + .I2(com_cmm_bar3_reg[2]), + .I3(com_cmm_u_cmm_cfgspace_bar3_reg_8_1_0_0_0_2_), + .LO(com_cmm_u_cmm_cfgspace_N_68012_i) + ); + defparam com_cmm_u_cmm_cfgspace_x3gio_bar3_N_68146_i.INIT = 16'h40FF; + LUT4_L com_cmm_u_cmm_cfgspace_x3gio_bar3_N_68146_i ( + .I0(com_cmm_u_cmm_cfgspace_N_44858_i), + .I1(com_cmm_u_cmm_cfgspace_N_48891_i), + .I2(com_cmm_bar3_reg[1]), + .I3(com_cmm_u_cmm_cfgspace_bar3_reg_8_1_0_0_0_0_1_), + .LO(com_cmm_u_cmm_cfgspace_N_68146_i) + ); + defparam com_cmm_u_cmm_cfgspace_x3gio_bar3_N_68011_i.INIT = 16'h40FF; + LUT4_L com_cmm_u_cmm_cfgspace_x3gio_bar3_N_68011_i ( + .I0(com_cmm_u_cmm_cfgspace_N_44858_i), + .I1(com_cmm_u_cmm_cfgspace_N_48891_i), + .I2(com_cmm_bar3_reg[0]), + .I3(com_cmm_u_cmm_cfgspace_bar3_reg_8_1_0_0_0_0_), + .LO(com_cmm_u_cmm_cfgspace_N_68011_i) + ); + defparam com_cmm_u_cmm_cfgspace_x3gio_bar4_N_68151_i.INIT = 16'h40FF; + LUT4_L com_cmm_u_cmm_cfgspace_x3gio_bar4_N_68151_i ( + .I0(com_cmm_u_cmm_cfgspace_N_48868_i), + .I1(com_cmm_u_cmm_cfgspace_N_48894_i), + .I2(com_cmm_bar4_reg[3]), + .I3(com_cmm_u_cmm_cfgspace_bar4_reg_8_1_0_0_0_3_), + .LO(com_cmm_u_cmm_cfgspace_N_68151_i) + ); + defparam com_cmm_u_cmm_cfgspace_x3gio_bar4_N_68150_i.INIT = 16'h40FF; + LUT4_L com_cmm_u_cmm_cfgspace_x3gio_bar4_N_68150_i ( + .I0(com_cmm_u_cmm_cfgspace_N_48868_i), + .I1(com_cmm_u_cmm_cfgspace_N_48894_i), + .I2(com_cmm_bar4_reg[2]), + .I3(com_cmm_u_cmm_cfgspace_bar4_reg_8_1_0_0_0_2_), + .LO(com_cmm_u_cmm_cfgspace_N_68150_i) + ); + defparam com_cmm_u_cmm_cfgspace_x3gio_bar4_N_68149_i.INIT = 16'h40FF; + LUT4_L com_cmm_u_cmm_cfgspace_x3gio_bar4_N_68149_i ( + .I0(com_cmm_u_cmm_cfgspace_N_48868_i), + .I1(com_cmm_u_cmm_cfgspace_N_48894_i), + .I2(com_cmm_bar4_reg[1]), + .I3(com_cmm_u_cmm_cfgspace_bar4_reg_8_1_0_0_0_0[1]), + .LO(com_cmm_u_cmm_cfgspace_N_68149_i) + ); + defparam com_cmm_u_cmm_cfgspace_x3gio_bar4_N_68148_i.INIT = 16'h40FF; + LUT4_L com_cmm_u_cmm_cfgspace_x3gio_bar4_N_68148_i ( + .I0(com_cmm_u_cmm_cfgspace_N_48868_i), + .I1(com_cmm_u_cmm_cfgspace_N_48894_i), + .I2(com_cmm_bar4_reg[0]), + .I3(com_cmm_u_cmm_cfgspace_bar4_reg_8_1_0_0_0_0_), + .LO(com_cmm_u_cmm_cfgspace_N_68148_i) + ); + defparam com_cmm_u_cmm_cfgspace_x3gio_bar5_N_68141_i.INIT = 16'h40FF; + LUT4_L com_cmm_u_cmm_cfgspace_x3gio_bar5_N_68141_i ( + .I0(com_cmm_u_cmm_cfgspace_N_44854_i), + .I1(com_cmm_u_cmm_cfgspace_N_48893_i), + .I2(com_cmm_bar5_reg[3]), + .I3(com_cmm_u_cmm_cfgspace_bar5_reg_8_1_0_0_0[3]), + .LO(com_cmm_u_cmm_cfgspace_N_68141_i) + ); + defparam com_cmm_u_cmm_cfgspace_x3gio_bar5_N_68140_i.INIT = 16'h40FF; + LUT4_L com_cmm_u_cmm_cfgspace_x3gio_bar5_N_68140_i ( + .I0(com_cmm_u_cmm_cfgspace_N_44854_i), + .I1(com_cmm_u_cmm_cfgspace_N_48893_i), + .I2(com_cmm_bar5_reg[2]), + .I3(com_cmm_u_cmm_cfgspace_bar5_reg_8_1_0_0_0[2]), + .LO(com_cmm_u_cmm_cfgspace_N_68140_i) + ); + defparam com_cmm_u_cmm_cfgspace_x3gio_bar5_N_68139_i.INIT = 16'h40FF; + LUT4_L com_cmm_u_cmm_cfgspace_x3gio_bar5_N_68139_i ( + .I0(com_cmm_u_cmm_cfgspace_N_44854_i), + .I1(com_cmm_u_cmm_cfgspace_N_48893_i), + .I2(com_cmm_bar5_reg[1]), + .I3(com_cmm_u_cmm_cfgspace_bar5_reg_8_1_0_0_0[1]), + .LO(com_cmm_u_cmm_cfgspace_N_68139_i) + ); + defparam com_cmm_u_cmm_cfgspace_x3gio_bar5_N_68138_i.INIT = 16'h40FF; + LUT4_L com_cmm_u_cmm_cfgspace_x3gio_bar5_N_68138_i ( + .I0(com_cmm_u_cmm_cfgspace_N_44854_i), + .I1(com_cmm_u_cmm_cfgspace_N_48893_i), + .I2(com_cmm_bar5_reg[0]), + .I3(com_cmm_u_cmm_cfgspace_bar5_reg_8_1_0_0_0[0]), + .LO(com_cmm_u_cmm_cfgspace_N_68138_i) + ); + defparam com_cmm_u_cmm_cfgspace_N_68512_i.INIT = 16'hFFE4; + LUT4_L com_cmm_u_cmm_cfgspace_N_68512_i ( + .I0(com_cmm_u_cmm_cfgspace_x_dcmd_18_i_0_0_0_o3[3]), + .I1(NlwRenamedSig_OI_cfg_dcommand[4]), + .I2(com_cmm_cfg_wr_data_28_), + .I3(com_cmm_rst_267), + .LO(com_cmm_u_cmm_cfgspace_N_68512_i_4784) + ); + defparam com_cmm_u_cmm_cfgspace_x_dcmd_18_i_0_0_0_3_.INIT = 16'h00E4; + LUT4_L com_cmm_u_cmm_cfgspace_x_dcmd_18_i_0_0_0_3_ ( + .I0(com_cmm_u_cmm_cfgspace_x_dcmd_18_i_0_0_0_o3[3]), + .I1(NlwRenamedSig_OI_cfg_dcommand[3]), + .I2(com_cmm_cfg_wr_data[27]), + .I3(com_cmm_rst_267), + .LO(com_cmm_u_cmm_cfgspace_N_20148_i) + ); + defparam com_cmm_u_cmm_cfgspace_x_dcmd_18_1_0_i_0_2_.INIT = 16'h00E4; + LUT4_L com_cmm_u_cmm_cfgspace_x_dcmd_18_1_0_i_0_2_ ( + .I0(com_cmm_u_cmm_cfgspace_x_dcmd_18_i_0_0_0_o3[3]), + .I1(NlwRenamedSig_OI_cfg_dcommand[2]), + .I2(com_cmm_cfg_wr_data[26]), + .I3(com_cmm_rst_267), + .LO(com_cmm_u_cmm_cfgspace_N_43713_i) + ); + defparam com_cmm_u_cmm_cfgspace_x_dcmd_18_i_0_0_1_.INIT = 16'h00E4; + LUT4_L com_cmm_u_cmm_cfgspace_x_dcmd_18_i_0_0_1_ ( + .I0(com_cmm_u_cmm_cfgspace_x_dcmd_18_i_0_0_0_o3[3]), + .I1(NlwRenamedSig_OI_cfg_dcommand[1]), + .I2(com_cmm_cfg_wr_data[25]), + .I3(com_cmm_rst_267), + .LO(com_cmm_u_cmm_cfgspace_N_29858_i) + ); + defparam com_cmm_u_cmm_cfgspace_x_dcmd_18_i_i_i_0_0_.INIT = 16'h00E4; + LUT4_L com_cmm_u_cmm_cfgspace_x_dcmd_18_i_i_i_0_0_ ( + .I0(com_cmm_u_cmm_cfgspace_x_dcmd_18_i_0_0_0_o3[3]), + .I1(NlwRenamedSig_OI_cfg_dcommand[0]), + .I2(com_cmm_cfg_wr_data[24]), + .I3(com_cmm_rst_267), + .LO(com_cmm_u_cmm_cfgspace_N_43947_i) + ); + defparam com_cmm_u_cmm_cfgspace_x_dcmd_18_i_0_14_.INIT = 16'h00E4; + LUT4_L com_cmm_u_cmm_cfgspace_x_dcmd_18_i_0_14_ ( + .I0(com_cmm_u_cmm_cfgspace_N_48878_i), + .I1(NlwRenamedSig_OI_cfg_dcommand[14]), + .I2(com_cmm_cfg_wr_data_22_), + .I3(com_cmm_rst_267), + .LO(com_cmm_u_cmm_cfgspace_N_29864_i) + ); + defparam com_cmm_u_cmm_cfgspace_N_68560_i.INIT = 16'hFFE4; + LUT4_L com_cmm_u_cmm_cfgspace_N_68560_i ( + .I0(com_cmm_u_cmm_cfgspace_N_48878_i), + .I1(NlwRenamedSig_OI_cfg_dcommand[13]), + .I2(com_cmm_cfg_wr_data_21_), + .I3(com_cmm_rst_267), + .LO(com_cmm_u_cmm_cfgspace_N_68560_i_4785) + ); + defparam com_cmm_u_cmm_cfgspace_x_dcmd_18_1_i_0_0_12_.INIT = 16'h00E4; + LUT4_L com_cmm_u_cmm_cfgspace_x_dcmd_18_1_i_0_0_12_ ( + .I0(com_cmm_u_cmm_cfgspace_N_48878_i), + .I1(NlwRenamedSig_OI_cfg_dcommand[12]), + .I2(com_cmm_cfg_wr_data_20_), + .I3(com_cmm_rst_267), + .LO(com_cmm_u_cmm_cfgspace_N_32900_i) + ); + defparam com_cmm_u_cmm_cfgspace_N_68513_i.INIT = 16'hFFE4; + LUT4_L com_cmm_u_cmm_cfgspace_N_68513_i ( + .I0(com_cmm_u_cmm_cfgspace_N_48878_i), + .I1(NlwRenamedSig_OI_cfg_dcommand[11]), + .I2(com_cmm_cfg_wr_data_19_), + .I3(com_cmm_rst_267), + .LO(com_cmm_u_cmm_cfgspace_N_68513_i_4786) + ); + defparam com_cmm_u_cmm_cfgspace_x_dcmd_18_i_0_9_.INIT = 16'h00E4; + LUT4_L com_cmm_u_cmm_cfgspace_x_dcmd_18_i_0_9_ ( + .I0(com_cmm_u_cmm_cfgspace_N_48878_i), + .I1(NlwRenamedSig_OI_cfg_dcommand[9]), + .I2(com_cmm_cfg_wr_data_17_), + .I3(com_cmm_rst_267), + .LO(com_cmm_u_cmm_cfgspace_N_29862_i) + ); + defparam com_cmm_u_cmm_cfgspace_x_dcmd_18_1_i_0_0_8_.INIT = 16'h00C4; + LUT4_L com_cmm_u_cmm_cfgspace_x_dcmd_18_1_i_0_0_8_ ( + .I0(com_cmm_u_cmm_cfgspace_N_48878_i), + .I1(com_cmm_u_cmm_cfgspace_N_49117), + .I2(com_cmm_cfg_wr_data_16_), + .I3(com_cmm_rst_267), + .LO(com_cmm_u_cmm_cfgspace_N_29860_i) + ); + defparam com_cmm_u_cmm_cfgspace_x_dcmd_18_i_0_0_0_7_.INIT = 16'h00E4; + LUT4_L com_cmm_u_cmm_cfgspace_x_dcmd_18_i_0_0_0_7_ ( + .I0(com_cmm_u_cmm_cfgspace_x_dcmd_18_i_0_0_0_o3[3]), + .I1(NlwRenamedSig_OI_cfg_dcommand[7]), + .I2(com_cmm_cfg_wr_data_31_), + .I3(com_cmm_rst_267), + .LO(com_cmm_u_cmm_cfgspace_N_20154_i) + ); + defparam com_cmm_u_cmm_cfgspace_x_dcmd_18_i_0_0_0_6_.INIT = 16'h00E4; + LUT4_L com_cmm_u_cmm_cfgspace_x_dcmd_18_i_0_0_0_6_ ( + .I0(com_cmm_u_cmm_cfgspace_x_dcmd_18_i_0_0_0_o3[3]), + .I1(NlwRenamedSig_OI_cfg_dcommand[6]), + .I2(com_cmm_cfg_wr_data_30_), + .I3(com_cmm_rst_267), + .LO(com_cmm_u_cmm_cfgspace_N_20152_i) + ); + defparam com_cmm_u_cmm_cfgspace_x_dcmd_18_i_0_0_0_5_.INIT = 16'h00E4; + LUT4_L com_cmm_u_cmm_cfgspace_x_dcmd_18_i_0_0_0_5_ ( + .I0(com_cmm_u_cmm_cfgspace_x_dcmd_18_i_0_0_0_o3[3]), + .I1(NlwRenamedSig_OI_cfg_dcommand[5]), + .I2(com_cmm_cfg_wr_data_29_), + .I3(com_cmm_rst_267), + .LO(com_cmm_u_cmm_cfgspace_N_20150_i) + ); + defparam com_cmm_u_cmm_cfgspace_cfg2tlm_rddata_0_a2_0_a2_0_a2_31_.INIT = 4'h8; + LUT2_L com_cmm_u_cmm_cfgspace_cfg2tlm_rddata_0_a2_0_a2_0_a2_31_ ( + .I0(com_cmm_u_cmm_cfgspace_decoder_read_data[31]), + .I1(com_cmm_state_6_), + .LO(com_cmm_cfg2tlm_rddata[31]) + ); + defparam com_cmm_u_cmm_cfgspace_cfg2tlm_rddata_0_a2_0_a2_0_a2_30_.INIT = 4'h8; + LUT2_L com_cmm_u_cmm_cfgspace_cfg2tlm_rddata_0_a2_0_a2_0_a2_30_ ( + .I0(com_cmm_u_cmm_cfgspace_decoder_read_data[30]), + .I1(com_cmm_state_6_), + .LO(com_cmm_cfg2tlm_rddata[30]) + ); + defparam com_cmm_u_cmm_cfgspace_cfg2tlm_rddata_0_a2_0_a2_0_a2_29_.INIT = 4'h8; + LUT2_L com_cmm_u_cmm_cfgspace_cfg2tlm_rddata_0_a2_0_a2_0_a2_29_ ( + .I0(com_cmm_u_cmm_cfgspace_decoder_read_data[29]), + .I1(com_cmm_state_6_), + .LO(com_cmm_cfg2tlm_rddata[29]) + ); + defparam com_cmm_u_cmm_cfgspace_cfg2tlm_rddata_0_a2_0_a2_0_a2_28_.INIT = 4'h8; + LUT2_L com_cmm_u_cmm_cfgspace_cfg2tlm_rddata_0_a2_0_a2_0_a2_28_ ( + .I0(com_cmm_u_cmm_cfgspace_decoder_read_data[28]), + .I1(com_cmm_state_6_), + .LO(com_cmm_cfg2tlm_rddata[28]) + ); + defparam com_cmm_u_cmm_cfgspace_cfg2tlm_rddata_0_a2_0_a2_0_a2_27_.INIT = 4'h8; + LUT2_L com_cmm_u_cmm_cfgspace_cfg2tlm_rddata_0_a2_0_a2_0_a2_27_ ( + .I0(com_cmm_u_cmm_cfgspace_decoder_read_data[27]), + .I1(com_cmm_state_6_), + .LO(com_cmm_cfg2tlm_rddata[27]) + ); + defparam com_cmm_u_cmm_cfgspace_cfg2tlm_rddata_0_a2_0_a2_0_a2_26_.INIT = 4'h8; + LUT2_L com_cmm_u_cmm_cfgspace_cfg2tlm_rddata_0_a2_0_a2_0_a2_26_ ( + .I0(com_cmm_u_cmm_cfgspace_decoder_read_data[26]), + .I1(com_cmm_state_6_), + .LO(com_cmm_cfg2tlm_rddata[26]) + ); + defparam com_cmm_u_cmm_cfgspace_cfg2tlm_rddata_0_a2_0_a2_0_a2_25_.INIT = 4'h8; + LUT2_L com_cmm_u_cmm_cfgspace_cfg2tlm_rddata_0_a2_0_a2_0_a2_25_ ( + .I0(com_cmm_u_cmm_cfgspace_decoder_read_data[25]), + .I1(com_cmm_state_6_), + .LO(com_cmm_cfg2tlm_rddata[25]) + ); + defparam com_cmm_u_cmm_cfgspace_cfg2tlm_rddata_0_a2_0_a2_0_a2_24_.INIT = 4'h8; + LUT2_L com_cmm_u_cmm_cfgspace_cfg2tlm_rddata_0_a2_0_a2_0_a2_24_ ( + .I0(com_cmm_u_cmm_cfgspace_decoder_read_data[24]), + .I1(com_cmm_state_6_), + .LO(com_cmm_cfg2tlm_rddata[24]) + ); + defparam com_cmm_u_cmm_cfgspace_cfg2tlm_rddata_0_a2_0_a2_0_a2_23_.INIT = 4'h8; + LUT2_L com_cmm_u_cmm_cfgspace_cfg2tlm_rddata_0_a2_0_a2_0_a2_23_ ( + .I0(com_cmm_u_cmm_cfgspace_decoder_read_data[23]), + .I1(com_cmm_state_6_), + .LO(com_cmm_cfg2tlm_rddata[23]) + ); + defparam com_cmm_u_cmm_cfgspace_cfg2tlm_rddata_0_a2_0_a2_0_a2_22_.INIT = 4'h8; + LUT2_L com_cmm_u_cmm_cfgspace_cfg2tlm_rddata_0_a2_0_a2_0_a2_22_ ( + .I0(com_cmm_u_cmm_cfgspace_decoder_read_data[22]), + .I1(com_cmm_state_6_), + .LO(com_cmm_cfg2tlm_rddata[22]) + ); + defparam com_cmm_u_cmm_cfgspace_cfg2tlm_rddata_0_a2_0_a2_0_a2_21_.INIT = 4'h8; + LUT2_L com_cmm_u_cmm_cfgspace_cfg2tlm_rddata_0_a2_0_a2_0_a2_21_ ( + .I0(com_cmm_u_cmm_cfgspace_decoder_read_data[21]), + .I1(com_cmm_state_6_), + .LO(com_cmm_cfg2tlm_rddata[21]) + ); + defparam com_cmm_u_cmm_cfgspace_cfg2tlm_rddata_0_a2_0_a2_0_a2_20_.INIT = 4'h8; + LUT2_L com_cmm_u_cmm_cfgspace_cfg2tlm_rddata_0_a2_0_a2_0_a2_20_ ( + .I0(com_cmm_u_cmm_cfgspace_decoder_read_data[20]), + .I1(com_cmm_state_6_), + .LO(com_cmm_cfg2tlm_rddata[20]) + ); + defparam com_cmm_u_cmm_cfgspace_cfg2tlm_rddata_0_a2_0_a2_0_a2_19_.INIT = 4'h8; + LUT2_L com_cmm_u_cmm_cfgspace_cfg2tlm_rddata_0_a2_0_a2_0_a2_19_ ( + .I0(com_cmm_u_cmm_cfgspace_decoder_read_data[19]), + .I1(com_cmm_state_6_), + .LO(com_cmm_cfg2tlm_rddata[19]) + ); + defparam com_cmm_u_cmm_cfgspace_cfg2tlm_rddata_0_a2_0_a2_0_a2_18_.INIT = 4'h8; + LUT2_L com_cmm_u_cmm_cfgspace_cfg2tlm_rddata_0_a2_0_a2_0_a2_18_ ( + .I0(com_cmm_u_cmm_cfgspace_decoder_read_data[18]), + .I1(com_cmm_state_6_), + .LO(com_cmm_cfg2tlm_rddata[18]) + ); + defparam com_cmm_u_cmm_cfgspace_cfg2tlm_rddata_0_a2_0_a2_0_a2_17_.INIT = 4'h8; + LUT2_L com_cmm_u_cmm_cfgspace_cfg2tlm_rddata_0_a2_0_a2_0_a2_17_ ( + .I0(com_cmm_u_cmm_cfgspace_decoder_read_data[17]), + .I1(com_cmm_state_6_), + .LO(com_cmm_cfg2tlm_rddata[17]) + ); + defparam com_cmm_u_cmm_cfgspace_cfg2tlm_rddata_0_a2_0_a2_0_a2_16_.INIT = 4'h8; + LUT2_L com_cmm_u_cmm_cfgspace_cfg2tlm_rddata_0_a2_0_a2_0_a2_16_ ( + .I0(com_cmm_u_cmm_cfgspace_decoder_read_data[16]), + .I1(com_cmm_state_6_), + .LO(com_cmm_cfg2tlm_rddata[16]) + ); + defparam com_cmm_u_cmm_cfgspace_cfg2tlm_rddata_0_a2_0_a2_0_a2_15_.INIT = 4'h8; + LUT2_L com_cmm_u_cmm_cfgspace_cfg2tlm_rddata_0_a2_0_a2_0_a2_15_ ( + .I0(com_cmm_u_cmm_cfgspace_decoder_read_data[15]), + .I1(com_cmm_state_6_), + .LO(com_cmm_cfg2tlm_rddata[15]) + ); + defparam com_cmm_u_cmm_cfgspace_cfg2tlm_rddata_0_a2_0_a2_0_a2_14_.INIT = 4'h8; + LUT2_L com_cmm_u_cmm_cfgspace_cfg2tlm_rddata_0_a2_0_a2_0_a2_14_ ( + .I0(com_cmm_u_cmm_cfgspace_decoder_read_data[14]), + .I1(com_cmm_state_6_), + .LO(com_cmm_cfg2tlm_rddata[14]) + ); + defparam com_cmm_u_cmm_cfgspace_cfg2tlm_rddata_0_a2_0_a2_0_a2_13_.INIT = 4'h8; + LUT2_L com_cmm_u_cmm_cfgspace_cfg2tlm_rddata_0_a2_0_a2_0_a2_13_ ( + .I0(com_cmm_u_cmm_cfgspace_decoder_read_data[13]), + .I1(com_cmm_state_6_), + .LO(com_cmm_cfg2tlm_rddata[13]) + ); + defparam com_cmm_u_cmm_cfgspace_cfg2tlm_rddata_0_a2_0_a2_0_a2_12_.INIT = 4'h8; + LUT2_L com_cmm_u_cmm_cfgspace_cfg2tlm_rddata_0_a2_0_a2_0_a2_12_ ( + .I0(com_cmm_u_cmm_cfgspace_decoder_read_data[12]), + .I1(com_cmm_state_6_), + .LO(com_cmm_cfg2tlm_rddata[12]) + ); + defparam com_cmm_u_cmm_cfgspace_cfg2tlm_rddata_0_a2_0_a2_0_a2_11_.INIT = 4'h8; + LUT2_L com_cmm_u_cmm_cfgspace_cfg2tlm_rddata_0_a2_0_a2_0_a2_11_ ( + .I0(com_cmm_u_cmm_cfgspace_decoder_read_data[11]), + .I1(com_cmm_state_6_), + .LO(com_cmm_cfg2tlm_rddata[11]) + ); + defparam com_cmm_u_cmm_cfgspace_cfg2tlm_rddata_0_a2_0_a2_0_a2_10_.INIT = 4'h8; + LUT2_L com_cmm_u_cmm_cfgspace_cfg2tlm_rddata_0_a2_0_a2_0_a2_10_ ( + .I0(com_cmm_u_cmm_cfgspace_decoder_read_data[10]), + .I1(com_cmm_state_6_), + .LO(com_cmm_cfg2tlm_rddata[10]) + ); + defparam com_cmm_u_cmm_cfgspace_cfg2tlm_rddata_0_a2_0_a2_0_a2_9_.INIT = 4'h8; + LUT2_L com_cmm_u_cmm_cfgspace_cfg2tlm_rddata_0_a2_0_a2_0_a2_9_ ( + .I0(com_cmm_u_cmm_cfgspace_decoder_read_data[9]), + .I1(com_cmm_state_6_), + .LO(com_cmm_cfg2tlm_rddata[9]) + ); + defparam com_cmm_u_cmm_cfgspace_cfg2tlm_rddata_0_a2_0_a2_0_a2_8_.INIT = 4'h8; + LUT2_L com_cmm_u_cmm_cfgspace_cfg2tlm_rddata_0_a2_0_a2_0_a2_8_ ( + .I0(com_cmm_u_cmm_cfgspace_decoder_read_data[8]), + .I1(com_cmm_state_6_), + .LO(com_cmm_cfg2tlm_rddata[8]) + ); + defparam com_cmm_u_cmm_cfgspace_cfg2tlm_rddata_0_a2_0_a2_7_.INIT = 4'h8; + LUT2_L com_cmm_u_cmm_cfgspace_cfg2tlm_rddata_0_a2_0_a2_7_ ( + .I0(com_cmm_u_cmm_cfgspace_decoder_read_data[7]), + .I1(com_cmm_state_6_), + .LO(com_cmm_cfg2tlm_rddata[7]) + ); + defparam com_cmm_u_cmm_cfgspace_cfg2tlm_rddata_0_a2_0_a2_6_.INIT = 4'h8; + LUT2_L com_cmm_u_cmm_cfgspace_cfg2tlm_rddata_0_a2_0_a2_6_ ( + .I0(com_cmm_u_cmm_cfgspace_decoder_read_data[6]), + .I1(com_cmm_state_6_), + .LO(com_cmm_cfg2tlm_rddata[6]) + ); + defparam com_cmm_u_cmm_cfgspace_cfg2tlm_rddata_0_a2_0_a2_5_.INIT = 4'h8; + LUT2_L com_cmm_u_cmm_cfgspace_cfg2tlm_rddata_0_a2_0_a2_5_ ( + .I0(com_cmm_u_cmm_cfgspace_decoder_read_data[5]), + .I1(com_cmm_state_6_), + .LO(com_cmm_cfg2tlm_rddata[5]) + ); + defparam com_cmm_u_cmm_cfgspace_cfg2tlm_rddata_0_a2_0_a2_4_.INIT = 4'h8; + LUT2_L com_cmm_u_cmm_cfgspace_cfg2tlm_rddata_0_a2_0_a2_4_ ( + .I0(com_cmm_u_cmm_cfgspace_decoder_read_data[4]), + .I1(com_cmm_state_6_), + .LO(com_cmm_cfg2tlm_rddata[4]) + ); + defparam com_cmm_u_cmm_cfgspace_cfg2tlm_rddata_0_a2_0_a2_3_.INIT = 4'h8; + LUT2_L com_cmm_u_cmm_cfgspace_cfg2tlm_rddata_0_a2_0_a2_3_ ( + .I0(com_cmm_u_cmm_cfgspace_decoder_read_data[3]), + .I1(com_cmm_state_6_), + .LO(com_cmm_cfg2tlm_rddata[3]) + ); + defparam com_cmm_u_cmm_cfgspace_cfg2tlm_rddata_0_a2_0_a2_0_a2_2_.INIT = 4'h8; + LUT2_L com_cmm_u_cmm_cfgspace_cfg2tlm_rddata_0_a2_0_a2_0_a2_2_ ( + .I0(com_cmm_u_cmm_cfgspace_decoder_read_data[2]), + .I1(com_cmm_state_6_), + .LO(com_cmm_cfg2tlm_rddata[2]) + ); + defparam com_cmm_u_cmm_cfgspace_cfg2tlm_rddata_0_a2_0_a2_0_a2_1_.INIT = 4'h8; + LUT2_L com_cmm_u_cmm_cfgspace_cfg2tlm_rddata_0_a2_0_a2_0_a2_1_ ( + .I0(com_cmm_u_cmm_cfgspace_decoder_read_data[1]), + .I1(com_cmm_state_6_), + .LO(com_cmm_cfg2tlm_rddata[1]) + ); + defparam com_cmm_u_cmm_cfgspace_cfg2tlm_rddata_0_a2_0_a2_0_a2_0_.INIT = 4'h8; + LUT2_L com_cmm_u_cmm_cfgspace_cfg2tlm_rddata_0_a2_0_a2_0_a2_0_ ( + .I0(com_cmm_u_cmm_cfgspace_decoder_read_data[0]), + .I1(com_cmm_state_6_), + .LO(com_cmm_cfg2tlm_rddata[0]) + ); + defparam com_cmm_u_cmm_cfgspace_N_68392_i.INIT = 16'hE444; + LUT4_L com_cmm_u_cmm_cfgspace_N_68392_i ( + .I0(com_cmm_u_cmm_cfgspace_N_48842_i), + .I1(cfg_dwaddr_5069[4]), + .I2(com_cmm_cfg_addr[4]), + .I3(com_cmm_state_1_), + .LO(com_cmm_u_cmm_cfgspace_N_68392_i_4739) + ); + defparam com_cmm_u_cmm_cfgspace_N_68391_i.INIT = 16'hE444; + LUT4_L com_cmm_u_cmm_cfgspace_N_68391_i ( + .I0(com_cmm_u_cmm_cfgspace_N_48842_i), + .I1(cfg_dwaddr_5069[3]), + .I2(com_cmm_cfg_addr[3]), + .I3(com_cmm_state_1_), + .LO(com_cmm_u_cmm_cfgspace_N_68391_i_4738) + ); + defparam com_cmm_u_cmm_cfgspace_N_68390_i.INIT = 16'hE444; + LUT4_L com_cmm_u_cmm_cfgspace_N_68390_i ( + .I0(com_cmm_u_cmm_cfgspace_N_48842_i), + .I1(cfg_dwaddr_5069[2]), + .I2(com_cmm_cfg_addr[2]), + .I3(com_cmm_state_1_), + .LO(com_cmm_u_cmm_cfgspace_N_68390_i_4741) + ); + defparam com_cmm_u_cmm_cfgspace_N_68389_i.INIT = 16'hE444; + LUT4_L com_cmm_u_cmm_cfgspace_N_68389_i ( + .I0(com_cmm_u_cmm_cfgspace_N_48842_i), + .I1(cfg_dwaddr_5069[1]), + .I2(com_cmm_cfg_addr[1]), + .I3(com_cmm_state_1_), + .LO(com_cmm_u_cmm_cfgspace_N_68389_i_4669) + ); + defparam com_cmm_u_cmm_cfgspace_N_68388_i.INIT = 16'hE444; + LUT4_L com_cmm_u_cmm_cfgspace_N_68388_i ( + .I0(com_cmm_u_cmm_cfgspace_N_48842_i), + .I1(cfg_dwaddr_5069[0]), + .I2(com_cmm_cfg_addr[0]), + .I3(com_cmm_state_1_), + .LO(com_cmm_u_cmm_cfgspace_N_68388_i_4670) + ); + defparam com_cmm_u_cmm_cfgspace_x3gio_xrom_N_68355_i.INIT = 16'hD580; + LUT4_L com_cmm_u_cmm_cfgspace_x3gio_xrom_N_68355_i ( + .I0(com_cmm_u_cmm_cfgspace_N_44871_i), + .I1(cfg_cfg_5072[351]), + .I2(com_cmm_cfg_wr_data_7_), + .I3(com_cmm_xrom_reg_31_), + .LO(com_cmm_u_cmm_cfgspace_N_68355_i) + ); + defparam com_cmm_u_cmm_cfgspace_x3gio_xrom_N_68335_i.INIT = 16'hD580; + LUT4_L com_cmm_u_cmm_cfgspace_x3gio_xrom_N_68335_i ( + .I0(com_cmm_u_cmm_cfgspace_N_44871_i), + .I1(cfg_cfg_5072[350]), + .I2(com_cmm_cfg_wr_data_6_), + .I3(com_cmm_xrom_reg_30_), + .LO(com_cmm_u_cmm_cfgspace_N_68335_i) + ); + defparam com_cmm_u_cmm_cfgspace_x3gio_xrom_N_68334_i.INIT = 16'hD580; + LUT4_L com_cmm_u_cmm_cfgspace_x3gio_xrom_N_68334_i ( + .I0(com_cmm_u_cmm_cfgspace_N_44871_i), + .I1(cfg_cfg_5072[349]), + .I2(com_cmm_cfg_wr_data_5_), + .I3(com_cmm_xrom_reg_29_), + .LO(com_cmm_u_cmm_cfgspace_N_68334_i) + ); + defparam com_cmm_u_cmm_cfgspace_x3gio_xrom_N_68333_i.INIT = 16'hD580; + LUT4_L com_cmm_u_cmm_cfgspace_x3gio_xrom_N_68333_i ( + .I0(com_cmm_u_cmm_cfgspace_N_44871_i), + .I1(cfg_cfg_5072[348]), + .I2(com_cmm_cfg_wr_data_4_), + .I3(com_cmm_xrom_reg_28_), + .LO(com_cmm_u_cmm_cfgspace_N_68333_i) + ); + defparam com_cmm_u_cmm_cfgspace_x3gio_xrom_N_68332_i.INIT = 16'hD580; + LUT4_L com_cmm_u_cmm_cfgspace_x3gio_xrom_N_68332_i ( + .I0(com_cmm_u_cmm_cfgspace_N_44871_i), + .I1(cfg_cfg_5072[347]), + .I2(com_cmm_cfg_wr_data_3_), + .I3(com_cmm_xrom_reg_27_), + .LO(com_cmm_u_cmm_cfgspace_N_68332_i) + ); + defparam com_cmm_u_cmm_cfgspace_x3gio_xrom_N_68354_i.INIT = 16'hD580; + LUT4_L com_cmm_u_cmm_cfgspace_x3gio_xrom_N_68354_i ( + .I0(com_cmm_u_cmm_cfgspace_N_44871_i), + .I1(cfg_cfg_5072[346]), + .I2(com_cmm_cfg_wr_data_2_), + .I3(com_cmm_xrom_reg_26_), + .LO(com_cmm_u_cmm_cfgspace_N_68354_i) + ); + defparam com_cmm_u_cmm_cfgspace_x3gio_xrom_N_68353_i.INIT = 16'hD580; + LUT4_L com_cmm_u_cmm_cfgspace_x3gio_xrom_N_68353_i ( + .I0(com_cmm_u_cmm_cfgspace_N_44871_i), + .I1(cfg_cfg_5072[345]), + .I2(com_cmm_cfg_wr_data_1_), + .I3(com_cmm_xrom_reg_25_), + .LO(com_cmm_u_cmm_cfgspace_N_68353_i) + ); + defparam com_cmm_u_cmm_cfgspace_x3gio_xrom_N_68352_i.INIT = 16'hD580; + LUT4_L com_cmm_u_cmm_cfgspace_x3gio_xrom_N_68352_i ( + .I0(com_cmm_u_cmm_cfgspace_N_44871_i), + .I1(cfg_cfg_5072[344]), + .I2(com_cmm_cfg_wr_data_0_), + .I3(com_cmm_xrom_reg_24_), + .LO(com_cmm_u_cmm_cfgspace_N_68352_i) + ); + defparam com_cmm_u_cmm_cfgspace_x3gio_xrom_N_68401_i.INIT = 16'hD580; + LUT4_L com_cmm_u_cmm_cfgspace_x3gio_xrom_N_68401_i ( + .I0(com_cmm_u_cmm_cfgspace_N_48863_i), + .I1(cfg_cfg_5072[343]), + .I2(com_cmm_cfg_wr_data_15_), + .I3(com_cmm_xrom_reg_23_), + .LO(com_cmm_u_cmm_cfgspace_N_68401_i) + ); + defparam com_cmm_u_cmm_cfgspace_x3gio_xrom_N_68400_i.INIT = 16'hD580; + LUT4_L com_cmm_u_cmm_cfgspace_x3gio_xrom_N_68400_i ( + .I0(com_cmm_u_cmm_cfgspace_N_48863_i), + .I1(cfg_cfg_5072[342]), + .I2(com_cmm_cfg_wr_data_14_), + .I3(com_cmm_xrom_reg_22_), + .LO(com_cmm_u_cmm_cfgspace_N_68400_i) + ); + defparam com_cmm_u_cmm_cfgspace_x3gio_xrom_N_68399_i.INIT = 16'hD580; + LUT4_L com_cmm_u_cmm_cfgspace_x3gio_xrom_N_68399_i ( + .I0(com_cmm_u_cmm_cfgspace_N_48863_i), + .I1(cfg_cfg_5072[341]), + .I2(com_cmm_cfg_wr_data_13_), + .I3(com_cmm_xrom_reg_21_), + .LO(com_cmm_u_cmm_cfgspace_N_68399_i) + ); + defparam com_cmm_u_cmm_cfgspace_x3gio_xrom_N_68398_i.INIT = 16'hD580; + LUT4_L com_cmm_u_cmm_cfgspace_x3gio_xrom_N_68398_i ( + .I0(com_cmm_u_cmm_cfgspace_N_48863_i), + .I1(cfg_cfg_5072[340]), + .I2(com_cmm_cfg_wr_data_12_), + .I3(com_cmm_xrom_reg_20_), + .LO(com_cmm_u_cmm_cfgspace_N_68398_i) + ); + defparam com_cmm_u_cmm_cfgspace_x3gio_xrom_N_68397_i.INIT = 16'hD580; + LUT4_L com_cmm_u_cmm_cfgspace_x3gio_xrom_N_68397_i ( + .I0(com_cmm_u_cmm_cfgspace_N_48863_i), + .I1(cfg_cfg_5072[339]), + .I2(com_cmm_cfg_wr_data_11_), + .I3(com_cmm_xrom_reg_19_), + .LO(com_cmm_u_cmm_cfgspace_N_68397_i) + ); + defparam com_cmm_u_cmm_cfgspace_x3gio_xrom_N_68396_i.INIT = 16'hD580; + LUT4_L com_cmm_u_cmm_cfgspace_x3gio_xrom_N_68396_i ( + .I0(com_cmm_u_cmm_cfgspace_N_48863_i), + .I1(cfg_cfg_5072[338]), + .I2(com_cmm_cfg_wr_data_10_), + .I3(com_cmm_xrom_reg_18_), + .LO(com_cmm_u_cmm_cfgspace_N_68396_i) + ); + defparam com_cmm_u_cmm_cfgspace_x3gio_xrom_N_68395_i.INIT = 16'hD580; + LUT4_L com_cmm_u_cmm_cfgspace_x3gio_xrom_N_68395_i ( + .I0(com_cmm_u_cmm_cfgspace_N_48863_i), + .I1(cfg_cfg_5072[337]), + .I2(com_cmm_cfg_wr_data_9_), + .I3(com_cmm_xrom_reg_17_), + .LO(com_cmm_u_cmm_cfgspace_N_68395_i) + ); + defparam com_cmm_u_cmm_cfgspace_x3gio_xrom_N_68394_i.INIT = 16'hD580; + LUT4_L com_cmm_u_cmm_cfgspace_x3gio_xrom_N_68394_i ( + .I0(com_cmm_u_cmm_cfgspace_N_48863_i), + .I1(cfg_cfg_5072[336]), + .I2(com_cmm_cfg_wr_data_8_), + .I3(com_cmm_xrom_reg_16_), + .LO(com_cmm_u_cmm_cfgspace_N_68394_i) + ); + defparam com_cmm_u_cmm_cfgspace_x3gio_xrom_N_68351_i.INIT = 16'hD580; + LUT4_L com_cmm_u_cmm_cfgspace_x3gio_xrom_N_68351_i ( + .I0(com_cmm_u_cmm_cfgspace_N_48953_i), + .I1(cfg_cfg_5072[335]), + .I2(com_cmm_cfg_wr_data_23_), + .I3(com_cmm_xrom_reg_15_), + .LO(com_cmm_u_cmm_cfgspace_N_68351_i) + ); + defparam com_cmm_u_cmm_cfgspace_x3gio_xrom_N_68350_i.INIT = 16'hD580; + LUT4_L com_cmm_u_cmm_cfgspace_x3gio_xrom_N_68350_i ( + .I0(com_cmm_u_cmm_cfgspace_N_48953_i), + .I1(cfg_cfg_5072[334]), + .I2(com_cmm_cfg_wr_data_22_), + .I3(com_cmm_xrom_reg_14_), + .LO(com_cmm_u_cmm_cfgspace_N_68350_i) + ); + defparam com_cmm_u_cmm_cfgspace_x3gio_xrom_N_68349_i.INIT = 16'hD580; + LUT4_L com_cmm_u_cmm_cfgspace_x3gio_xrom_N_68349_i ( + .I0(com_cmm_u_cmm_cfgspace_N_48953_i), + .I1(cfg_cfg_5072[333]), + .I2(com_cmm_cfg_wr_data_21_), + .I3(com_cmm_xrom_reg_13_), + .LO(com_cmm_u_cmm_cfgspace_N_68349_i) + ); + defparam com_cmm_u_cmm_cfgspace_x3gio_xrom_N_68393_i.INIT = 16'hD580; + LUT4_L com_cmm_u_cmm_cfgspace_x3gio_xrom_N_68393_i ( + .I0(com_cmm_u_cmm_cfgspace_N_48953_i), + .I1(cfg_cfg_5072[332]), + .I2(com_cmm_cfg_wr_data_20_), + .I3(com_cmm_xrom_reg_12_), + .LO(com_cmm_u_cmm_cfgspace_N_68393_i) + ); + defparam com_cmm_u_cmm_cfgspace_x3gio_xrom_N_68348_i.INIT = 16'hD580; + LUT4_L com_cmm_u_cmm_cfgspace_x3gio_xrom_N_68348_i ( + .I0(com_cmm_u_cmm_cfgspace_N_48953_i), + .I1(cfg_cfg_5072[331]), + .I2(com_cmm_cfg_wr_data_19_), + .I3(com_cmm_xrom_reg_11_), + .LO(com_cmm_u_cmm_cfgspace_N_68348_i) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_00_i_0_0_31_.INIT = 16'h5010; + LUT4_L com_cmm_u_cmm_cfgspace_low_addr_00_i_0_0_31_ ( + .I0(com_cmm_u_cmm_cfgspace_N_45565), + .I1(com_cmm_u_cmm_cfgspace_N_50452), + .I2(com_cmm_u_cmm_cfgspace_low_addr_00_i_0_0_31_32092_4671), + .I3(com_cmm_xrom_reg_31_), + .LO(com_cmm_u_cmm_cfgspace_N_21770_i) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_00_i_30_.INIT = 16'h5010; + LUT4_L com_cmm_u_cmm_cfgspace_low_addr_00_i_30_ ( + .I0(com_cmm_u_cmm_cfgspace_N_45361), + .I1(com_cmm_u_cmm_cfgspace_N_50452), + .I2(com_cmm_u_cmm_cfgspace_low_addr_00_i_30_32097_4672), + .I3(com_cmm_xrom_reg_30_), + .LO(com_cmm_u_cmm_cfgspace_N_43767_i) + ); + defparam com_cmm_u_cmm_cfgspace_N_68226_i.INIT = 16'h8FFF; + LUT4_L com_cmm_u_cmm_cfgspace_N_68226_i ( + .I0(com_cmm_u_cmm_cfgspace_N_50454), + .I1(com_cmm_bar4_reg[29]), + .I2(com_cmm_u_cmm_cfgspace_low_addr_00_i_i_0_1_29__4675), + .I3(com_cmm_u_cmm_cfgspace_low_addr_00_i_i_0_2_29__4674), + .LO(com_cmm_u_cmm_cfgspace_N_68226_i_4673) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_00_i_28_.INIT = 16'h5010; + LUT4_L com_cmm_u_cmm_cfgspace_low_addr_00_i_28_ ( + .I0(com_cmm_u_cmm_cfgspace_N_45355), + .I1(com_cmm_u_cmm_cfgspace_N_50452), + .I2(com_cmm_u_cmm_cfgspace_low_addr_00_i_28_32102_4676), + .I3(com_cmm_xrom_reg_28_), + .LO(com_cmm_u_cmm_cfgspace_N_43765_i) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_00_i_0_27_.INIT = 16'h1000; + LUT4_L com_cmm_u_cmm_cfgspace_low_addr_00_i_0_27_ ( + .I0(com_cmm_u_cmm_cfgspace_N_50143), + .I1(com_cmm_u_cmm_cfgspace_N_50144), + .I2(com_cmm_u_cmm_cfgspace_low_addr_00_i_0_1_27__4677), + .I3(com_cmm_u_cmm_cfgspace_low_addr_00_i_0_3[27]), + .LO(com_cmm_u_cmm_cfgspace_N_43763_i) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_00_i_26_.INIT = 16'h5010; + LUT4_L com_cmm_u_cmm_cfgspace_low_addr_00_i_26_ ( + .I0(com_cmm_u_cmm_cfgspace_N_45343), + .I1(com_cmm_u_cmm_cfgspace_N_50452), + .I2(com_cmm_u_cmm_cfgspace_low_addr_00_i_26_32107_4678), + .I3(com_cmm_xrom_reg_26_), + .LO(com_cmm_u_cmm_cfgspace_N_43761_i) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_00_i_25_.INIT = 16'h5010; + LUT4_L com_cmm_u_cmm_cfgspace_low_addr_00_i_25_ ( + .I0(com_cmm_u_cmm_cfgspace_N_45337), + .I1(com_cmm_u_cmm_cfgspace_N_50452), + .I2(com_cmm_u_cmm_cfgspace_low_addr_00_i_25_32112_4679), + .I3(com_cmm_xrom_reg_25_), + .LO(com_cmm_u_cmm_cfgspace_N_43759_i) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_00_i_24_.INIT = 16'h5010; + LUT4_L com_cmm_u_cmm_cfgspace_low_addr_00_i_24_ ( + .I0(com_cmm_u_cmm_cfgspace_N_45331), + .I1(com_cmm_u_cmm_cfgspace_N_50452), + .I2(com_cmm_u_cmm_cfgspace_low_addr_00_i_24_32117_4680), + .I3(com_cmm_xrom_reg_24_), + .LO(com_cmm_u_cmm_cfgspace_N_43757_i) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_00_i_23_.INIT = 16'h5010; + LUT4_L com_cmm_u_cmm_cfgspace_low_addr_00_i_23_ ( + .I0(com_cmm_u_cmm_cfgspace_N_45325), + .I1(com_cmm_u_cmm_cfgspace_N_50452), + .I2(com_cmm_u_cmm_cfgspace_low_addr_00_i_23_32122_4681), + .I3(com_cmm_xrom_reg_23_), + .LO(com_cmm_u_cmm_cfgspace_N_43755_i) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_00_i_22_.INIT = 16'h5010; + LUT4_L com_cmm_u_cmm_cfgspace_low_addr_00_i_22_ ( + .I0(com_cmm_u_cmm_cfgspace_N_45319), + .I1(com_cmm_u_cmm_cfgspace_N_50452), + .I2(com_cmm_u_cmm_cfgspace_low_addr_00_i_22_32127_4682), + .I3(com_cmm_xrom_reg_22_), + .LO(com_cmm_u_cmm_cfgspace_N_43753_i) + ); + defparam com_cmm_u_cmm_cfgspace_N_68214_i.INIT = 16'hBFFF; + LUT4_L com_cmm_u_cmm_cfgspace_N_68214_i ( + .I0(com_cmm_u_cmm_cfgspace_N_45314), + .I1(com_cmm_u_cmm_cfgspace_low_addr_00_0_0_21__4686), + .I2(com_cmm_u_cmm_cfgspace_low_addr_00_0_1_21__4685), + .I3(com_cmm_u_cmm_cfgspace_low_addr_00_0_2_21__4684), + .LO(com_cmm_u_cmm_cfgspace_N_68214_i_4683) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_00_i_20_.INIT = 16'h5010; + LUT4_L com_cmm_u_cmm_cfgspace_low_addr_00_i_20_ ( + .I0(com_cmm_u_cmm_cfgspace_N_45306), + .I1(com_cmm_u_cmm_cfgspace_N_50452), + .I2(com_cmm_u_cmm_cfgspace_low_addr_00_i_20_32132_4687), + .I3(com_cmm_xrom_reg_20_), + .LO(com_cmm_u_cmm_cfgspace_N_43750_i) + ); + defparam com_cmm_u_cmm_cfgspace_N_68227_i.INIT = 16'hBFFF; + LUT4_L com_cmm_u_cmm_cfgspace_N_68227_i ( + .I0(com_cmm_u_cmm_cfgspace_N_45979), + .I1(com_cmm_u_cmm_cfgspace_low_addr_00_i_i_0_0_19__4691), + .I2(com_cmm_u_cmm_cfgspace_low_addr_00_i_i_0_1_19__4690), + .I3(com_cmm_u_cmm_cfgspace_low_addr_00_i_i_0_2_19__4689), + .LO(com_cmm_u_cmm_cfgspace_N_68227_i_4688) + ); + defparam com_cmm_u_cmm_cfgspace_N_68212_i.INIT = 16'hBFFF; + LUT4_L com_cmm_u_cmm_cfgspace_N_68212_i ( + .I0(com_cmm_u_cmm_cfgspace_N_45300), + .I1(com_cmm_u_cmm_cfgspace_low_addr_00_0_0_18__4695), + .I2(com_cmm_u_cmm_cfgspace_low_addr_00_0_1_18__4694), + .I3(com_cmm_u_cmm_cfgspace_low_addr_00_0_2_18__4693), + .LO(com_cmm_u_cmm_cfgspace_N_68212_i_4692) + ); + defparam com_cmm_u_cmm_cfgspace_N_68225_i.INIT = 16'hBFFF; + LUT4_L com_cmm_u_cmm_cfgspace_N_68225_i ( + .I0(com_cmm_u_cmm_cfgspace_N_45965), + .I1(com_cmm_u_cmm_cfgspace_low_addr_00_i_i_0_0_17__4699), + .I2(com_cmm_u_cmm_cfgspace_low_addr_00_i_i_0_1_17__4698), + .I3(com_cmm_u_cmm_cfgspace_low_addr_00_i_i_0_2_17__4697), + .LO(com_cmm_u_cmm_cfgspace_N_68225_i_4696) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_00_i_0_16_.INIT = 16'h5100; + LUT4_L com_cmm_u_cmm_cfgspace_low_addr_00_i_0_16_ ( + .I0(com_cmm_u_cmm_cfgspace_N_50140), + .I1(com_cmm_u_cmm_cfgspace_N_50498), + .I2(com_cmm_bar0_reg_16_), + .I3(com_cmm_u_cmm_cfgspace_low_addr_00_i_0_1_16__4700), + .LO(com_cmm_u_cmm_cfgspace_N_43747_i) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_00_0_0_i_15_.INIT = 16'hC040; + LUT4_L com_cmm_u_cmm_cfgspace_low_addr_00_0_0_i_15_ ( + .I0(com_cmm_u_cmm_cfgspace_N_50495), + .I1(com_cmm_u_cmm_cfgspace_low_addr_00_0_0_i_15_32134_4702), + .I2(com_cmm_u_cmm_cfgspace_low_addr_00_0_0_i_15_32135_4701), + .I3(cfg_cfg_5072[15]), + .LO(com_cmm_u_cmm_cfgspace_N_43745_i) + ); + defparam com_cmm_u_cmm_cfgspace_N_68184_i.INIT = 16'h8FFF; + LUT4_L com_cmm_u_cmm_cfgspace_N_68184_i ( + .I0(com_cmm_u_cmm_cfgspace_N_50454), + .I1(com_cmm_bar4_reg[14]), + .I2(com_cmm_u_cmm_cfgspace_low_addr_00_0_0_0_0_1[14]), + .I3(com_cmm_u_cmm_cfgspace_low_addr_00_0_0_0_0_2[14]), + .LO(com_cmm_u_cmm_cfgspace_N_68184_i_4703) + ); + defparam com_cmm_u_cmm_cfgspace_N_68183_i.INIT = 16'h8FFF; + LUT4_L com_cmm_u_cmm_cfgspace_N_68183_i ( + .I0(com_cmm_u_cmm_cfgspace_N_50451), + .I1(cfg_cfg_5072[13]), + .I2(com_cmm_u_cmm_cfgspace_low_addr_00_0_0_0[13]), + .I3(com_cmm_u_cmm_cfgspace_low_addr_00_0_0_1[13]), + .LO(com_cmm_u_cmm_cfgspace_N_68183_i_4704) + ); + defparam com_cmm_u_cmm_cfgspace_N_68182_i.INIT = 16'h8FFF; + LUT4_L com_cmm_u_cmm_cfgspace_N_68182_i ( + .I0(com_cmm_u_cmm_cfgspace_N_50451), + .I1(cfg_cfg_5072[12]), + .I2(com_cmm_u_cmm_cfgspace_low_addr_00_0_0_0_0[12]), + .I3(com_cmm_u_cmm_cfgspace_low_addr_00_0_0_0_1[12]), + .LO(com_cmm_u_cmm_cfgspace_N_68182_i_4705) + ); + defparam com_cmm_u_cmm_cfgspace_N_68191_i.INIT = 16'h8FFF; + LUT4_L com_cmm_u_cmm_cfgspace_N_68191_i ( + .I0(com_cmm_u_cmm_cfgspace_N_50454), + .I1(com_cmm_bar4_reg[11]), + .I2(com_cmm_u_cmm_cfgspace_low_addr_00_i_0_i_0_1[11]), + .I3(com_cmm_u_cmm_cfgspace_low_addr_00_i_0_i_0_2[11]), + .LO(com_cmm_u_cmm_cfgspace_N_68191_i_4706) + ); + defparam com_cmm_u_cmm_cfgspace_N_68210_i.INIT = 16'h8FFF; + LUT4_L com_cmm_u_cmm_cfgspace_N_68210_i ( + .I0(com_cmm_u_cmm_cfgspace_N_50454), + .I1(com_cmm_bar4_reg[10]), + .I2(com_cmm_u_cmm_cfgspace_low_addr_00_0_0_10__4709), + .I3(com_cmm_u_cmm_cfgspace_low_addr_00_0_1_10__4708), + .LO(com_cmm_u_cmm_cfgspace_N_68210_i_4707) + ); + defparam com_cmm_u_cmm_cfgspace_N_68209_i.INIT = 16'h8FFF; + LUT4_L com_cmm_u_cmm_cfgspace_N_68209_i ( + .I0(com_cmm_u_cmm_cfgspace_N_50454), + .I1(com_cmm_bar4_reg[9]), + .I2(com_cmm_u_cmm_cfgspace_low_addr_00_0_0_9__4712), + .I3(com_cmm_u_cmm_cfgspace_low_addr_00_0_1_9__4711), + .LO(com_cmm_u_cmm_cfgspace_N_68209_i_4710) + ); + defparam com_cmm_u_cmm_cfgspace_N_68208_i.INIT = 16'h8FFF; + LUT4_L com_cmm_u_cmm_cfgspace_N_68208_i ( + .I0(com_cmm_u_cmm_cfgspace_N_50454), + .I1(com_cmm_bar4_reg[8]), + .I2(com_cmm_u_cmm_cfgspace_low_addr_00_0_0_8__4715), + .I3(com_cmm_u_cmm_cfgspace_low_addr_00_0_1_8__4714), + .LO(com_cmm_u_cmm_cfgspace_N_68208_i_4713) + ); + defparam com_cmm_u_cmm_cfgspace_N_68207_i.INIT = 16'h8FFF; + LUT4_L com_cmm_u_cmm_cfgspace_N_68207_i ( + .I0(com_cmm_u_cmm_cfgspace_N_50454), + .I1(com_cmm_bar4_reg[7]), + .I2(com_cmm_u_cmm_cfgspace_low_addr_00_0_0_7__4718), + .I3(com_cmm_u_cmm_cfgspace_low_addr_00_0_1_7__4717), + .LO(com_cmm_u_cmm_cfgspace_N_68207_i_4716) + ); + defparam com_cmm_u_cmm_cfgspace_N_68206_i.INIT = 16'h8FFF; + LUT4_L com_cmm_u_cmm_cfgspace_N_68206_i ( + .I0(com_cmm_u_cmm_cfgspace_N_50454), + .I1(com_cmm_bar4_reg[6]), + .I2(com_cmm_u_cmm_cfgspace_low_addr_00_0_0_6__4721), + .I3(com_cmm_u_cmm_cfgspace_low_addr_00_0_1_6__4720), + .LO(com_cmm_u_cmm_cfgspace_N_68206_i_4719) + ); + defparam com_cmm_u_cmm_cfgspace_N_68205_i.INIT = 16'h8FFF; + LUT4_L com_cmm_u_cmm_cfgspace_N_68205_i ( + .I0(com_cmm_u_cmm_cfgspace_N_50454), + .I1(com_cmm_bar4_reg[5]), + .I2(com_cmm_u_cmm_cfgspace_low_addr_00_0_0_5__4724), + .I3(com_cmm_u_cmm_cfgspace_low_addr_00_0_1_5__4723), + .LO(com_cmm_u_cmm_cfgspace_N_68205_i_4722) + ); + defparam com_cmm_u_cmm_cfgspace_N_68204_i.INIT = 16'h8FFF; + LUT4_L com_cmm_u_cmm_cfgspace_N_68204_i ( + .I0(com_cmm_u_cmm_cfgspace_N_50454), + .I1(com_cmm_bar4_reg[4]), + .I2(com_cmm_u_cmm_cfgspace_low_addr_00_0_0_4__4727), + .I3(com_cmm_u_cmm_cfgspace_low_addr_00_0_1_4__4726), + .LO(com_cmm_u_cmm_cfgspace_N_68204_i_4725) + ); + defparam com_cmm_u_cmm_cfgspace_N_68203_i.INIT = 16'h8FFF; + LUT4_L com_cmm_u_cmm_cfgspace_N_68203_i ( + .I0(com_cmm_u_cmm_cfgspace_N_50454), + .I1(com_cmm_bar4_reg[3]), + .I2(com_cmm_u_cmm_cfgspace_low_addr_00_0_0_3__4730), + .I3(com_cmm_u_cmm_cfgspace_low_addr_00_0_1_3__4729), + .LO(com_cmm_u_cmm_cfgspace_N_68203_i_4728) + ); + defparam com_cmm_u_cmm_cfgspace_N_68202_i.INIT = 16'h8FFF; + LUT4_L com_cmm_u_cmm_cfgspace_N_68202_i ( + .I0(com_cmm_u_cmm_cfgspace_N_50454), + .I1(com_cmm_bar4_reg[2]), + .I2(com_cmm_u_cmm_cfgspace_low_addr_00_0_0_2__4733), + .I3(com_cmm_u_cmm_cfgspace_low_addr_00_0_1_2__4732), + .LO(com_cmm_u_cmm_cfgspace_N_68202_i_4731) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_00_i_0_1_.INIT = 16'hD000; + LUT4_L com_cmm_u_cmm_cfgspace_low_addr_00_i_0_1_ ( + .I0(com_cmm_u_cmm_cfgspace_N_50495), + .I1(com_cmm_u_cmm_cfgspace_low_addr_00_i_0_o3[1]), + .I2(com_cmm_u_cmm_cfgspace_low_addr_00_i_0_0[1]), + .I3(com_cmm_u_cmm_cfgspace_low_addr_00_i_0_1_1__4734), + .LO(com_cmm_u_cmm_cfgspace_N_43731_i) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_02_7_0_16_.INIT = 8'hCA; + LUT3_L com_cmm_u_cmm_cfgspace_low_addr_02_7_0_16_ ( + .I0(com_cmm_u_cmm_cfgspace_N_4286), + .I1(com_cmm_u_cmm_cfgspace_N_4382), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex[0]), + .LO(com_cmm_u_cmm_cfgspace_low_addr_02[16]) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_02_7_0_14_.INIT = 8'hCA; + LUT3_L com_cmm_u_cmm_cfgspace_low_addr_02_7_0_14_ ( + .I0(com_cmm_u_cmm_cfgspace_N_4284), + .I1(com_cmm_u_cmm_cfgspace_N_4380), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex[0]), + .LO(com_cmm_u_cmm_cfgspace_low_addr_02[14]) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_02_7_0_12_.INIT = 8'hCA; + LUT3_L com_cmm_u_cmm_cfgspace_low_addr_02_7_0_12_ ( + .I0(com_cmm_u_cmm_cfgspace_N_4282), + .I1(com_cmm_u_cmm_cfgspace_N_4378), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex[0]), + .LO(com_cmm_u_cmm_cfgspace_low_addr_02[12]) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_02_7_0_11_.INIT = 8'hCA; + LUT3_L com_cmm_u_cmm_cfgspace_low_addr_02_7_0_11_ ( + .I0(com_cmm_u_cmm_cfgspace_N_4281), + .I1(com_cmm_u_cmm_cfgspace_N_4377), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex[0]), + .LO(com_cmm_u_cmm_cfgspace_low_addr_02[11]) + ); + defparam com_cmm_u_cmm_cfgspace_N_68098_i.INIT = 16'hEFFF; + LUT4_L com_cmm_u_cmm_cfgspace_N_68098_i ( + .I0(com_cmm_u_cmm_cfgspace_N_48973_i), + .I1(com_cmm_u_cmm_cfgspace_N_49170), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex_en_3_i_0_32188_4737), + .I3(com_cmm_u_cmm_cfgspace_sel_encodex_en_3_i_0_32190_4736), + .LO(com_cmm_u_cmm_cfgspace_N_68098_i_4735) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_01_7_0_10_.INIT = 8'hCA; + LUT3_L com_cmm_u_cmm_cfgspace_low_addr_01_7_0_10_ ( + .I0(com_cmm_u_cmm_cfgspace_N_4008), + .I1(com_cmm_u_cmm_cfgspace_N_4104), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex[0]), + .LO(com_cmm_u_cmm_cfgspace_low_addr_01[10]) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_01_7_0_0_.INIT = 8'hCA; + LUT3_L com_cmm_u_cmm_cfgspace_low_addr_01_7_0_0_ ( + .I0(com_cmm_u_cmm_cfgspace_N_3998), + .I1(com_cmm_u_cmm_cfgspace_N_4094), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex[0]), + .LO(com_cmm_u_cmm_cfgspace_low_addr_01[0]) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_00_i_0_0_1_0_.INIT = 16'h3050; + LUT4 com_cmm_u_cmm_cfgspace_low_addr_00_i_0_0_1_0_ ( + .I0(com_cmm_bar0_reg_0_), + .I1(com_cmm_msi_haddr[0]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex[0]), + .I3(com_cmm_u_cmm_cfgspace_sel_encodex_2[2]), + .O(com_cmm_u_cmm_cfgspace_low_addr_00_i_0_0_1[0]) + ); + FDRS com_cmm_u_cmm_cfgspace_sel_encodex_1_1_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_cfgspace_N_68391_i_4738), + .Q(com_cmm_u_cmm_cfgspace_sel_encodex_1[1]), + .R(com_cmm_rst_267), + .S(com_cmm_u_cmm_cfgspace_N_68712_i_4740) + ); + FDRS com_cmm_u_cmm_cfgspace_sel_encodex_2_1_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_cfgspace_N_68391_i_4738), + .Q(com_cmm_u_cmm_cfgspace_sel_encodex_2[1]), + .R(com_cmm_rst_267), + .S(com_cmm_u_cmm_cfgspace_N_68712_i_4740) + ); + FDRS com_cmm_u_cmm_cfgspace_sel_encodex_1_2_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_cfgspace_N_68392_i_4739), + .Q(com_cmm_u_cmm_cfgspace_sel_encodex_1[2]), + .R(com_cmm_rst_267), + .S(com_cmm_u_cmm_cfgspace_N_68712_i_4740) + ); + FDRS com_cmm_u_cmm_cfgspace_sel_encodex_2_2_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_cfgspace_N_68392_i_4739), + .Q(com_cmm_u_cmm_cfgspace_sel_encodex_2[2]), + .R(com_cmm_rst_267), + .S(com_cmm_u_cmm_cfgspace_N_68712_i_4740) + ); + FDRS com_cmm_u_cmm_cfgspace_sel_encodex_1_0_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_cfgspace_N_68390_i_4741), + .Q(com_cmm_u_cmm_cfgspace_sel_encodex_1[0]), + .R(com_cmm_rst_267), + .S(com_cmm_u_cmm_cfgspace_N_68712_i_4740) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_00_0_a3_5_a3_2_.INIT = 8'h10; + LUT3 com_cmm_u_cmm_cfgspace_low_addr_00_0_a3_5_a3_2_ ( + .I0(com_cmm_u_cmm_cfgspace_sel_encodex[1]), + .I1(com_cmm_u_cmm_cfgspace_sel_encodex[2]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex[0]), + .O(com_cmm_u_cmm_cfgspace_N_50498) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_00_i_0_a2_1_16_.INIT = 8'h10; + LUT3 com_cmm_u_cmm_cfgspace_low_addr_00_i_0_a2_1_16_ ( + .I0(com_cmm_msi_haddr[16]), + .I1(com_cmm_u_cmm_cfgspace_sel_encodex[1]), + .I2(com_cmm_u_cmm_cfgspace_N_50450), + .O(com_cmm_u_cmm_cfgspace_N_50140) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_00_i_i_0_a2_3_19_.INIT = 8'h20; + LUT3 com_cmm_u_cmm_cfgspace_low_addr_00_i_i_0_a2_3_19_ ( + .I0(com_cmm_bar4_reg[19]), + .I1(com_cmm_u_cmm_cfgspace_sel_encodex[2]), + .I2(com_cmm_u_cmm_cfgspace_N_50490), + .O(com_cmm_u_cmm_cfgspace_N_45979) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_00_i_i_0_a2_2_17_.INIT = 8'h20; + LUT3 com_cmm_u_cmm_cfgspace_low_addr_00_i_i_0_a2_2_17_ ( + .I0(com_cmm_bar4_reg[17]), + .I1(com_cmm_u_cmm_cfgspace_sel_encodex[2]), + .I2(com_cmm_u_cmm_cfgspace_N_50490), + .O(com_cmm_u_cmm_cfgspace_N_45965) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_00_0_a2_3_21_.INIT = 8'h20; + LUT3 com_cmm_u_cmm_cfgspace_low_addr_00_0_a2_3_21_ ( + .I0(com_cmm_bar4_reg[21]), + .I1(com_cmm_u_cmm_cfgspace_sel_encodex[2]), + .I2(com_cmm_u_cmm_cfgspace_N_50490), + .O(com_cmm_u_cmm_cfgspace_N_45314) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_00_0_a2_3_18_.INIT = 8'h20; + LUT3 com_cmm_u_cmm_cfgspace_low_addr_00_0_a2_3_18_ ( + .I0(com_cmm_bar4_reg[18]), + .I1(com_cmm_u_cmm_cfgspace_sel_encodex[2]), + .I2(com_cmm_u_cmm_cfgspace_N_50490), + .O(com_cmm_u_cmm_cfgspace_N_45300) + ); + defparam com_cmm_u_cmm_cfgspace_x3gio_decodepipe_h_sel_0x_3_0_0_a4_1_0_a2.INIT = 8'h10; + LUT3 com_cmm_u_cmm_cfgspace_x3gio_decodepipe_h_sel_0x_3_0_0_a4_1_0_a2 ( + .I0(com_cmm_cfg_addr[4]), + .I1(com_cmm_cfg_addr[6]), + .I2(com_cmm_u_cmm_cfgspace_N_42636_1), + .O(com_cmm_u_cmm_cfgspace_N_43088_1) + ); + defparam com_cmm_u_cmm_cfgspace_x_dcmd_18_i_0_o3_i_o3_9_.INIT = 8'h80; + LUT3 com_cmm_u_cmm_cfgspace_x_dcmd_18_i_0_o3_i_o3_9_ ( + .I0(com_cmm_u_cmm_cfgspace_sel_x1_4775), + .I1(com_cmm_u_cmm_cfgspace_sel_6x_4753), + .I2(com_cmm_u_cmm_cfgspace_N_48848_i), + .O(com_cmm_u_cmm_cfgspace_N_48878_i) + ); + defparam com_cmm_u_cmm_cfgspace_sel_encodex_en_3_i_0_a2_1_i_o2.INIT = 8'h10; + LUT3 com_cmm_u_cmm_cfgspace_sel_encodex_en_3_i_0_a2_1_i_o2 ( + .I0(cfg_dwaddr_5069[2]), + .I1(cfg_dwaddr_5069[6]), + .I2(com_cmm_u_cmm_cfgspace_N_42634_1), + .O(com_cmm_u_cmm_cfgspace_N_48973_i) + ); + FDC com_cmm_u_cmm_cfgspace_set_unsupportedreq ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_unsupportedreq), + .Q(com_cmm_u_cmm_cfgspace_set_unsupportedreq_4742), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_cfgspace_set_transaction_pending ( + .C(NlwRenamedSig_OI_trn_clk), + .D(cfg_trn_pending_n_i), + .Q(com_cmm_u_cmm_cfgspace_set_transaction_pending_4783), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_cfgspace_set_detectednonfatal ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_detectednonfatal), + .Q(com_cmm_u_cmm_cfgspace_set_detectednonfatal_4743), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_cfgspace_set_detectedfatal ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_detectedfatal), + .Q(com_cmm_u_cmm_cfgspace_set_detectedfatal_4744), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_cfgspace_set_detectedcorrectable ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_detectedcorrectable), + .Q(com_cmm_u_cmm_cfgspace_set_detectedcorrectable_4745), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_cfgspace_set_signaledtargetabort ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_signaledtargetabort), + .Q(com_cmm_u_cmm_cfgspace_set_signaledtargetabort_4746), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_cfgspace_set_signaledsystemerror ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_signaledsystemerror), + .Q(com_cmm_u_cmm_cfgspace_set_signaledsystemerror_4747), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_cfgspace_set_signaledpme ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_pme_sent), + .Q(com_cmm_u_cmm_cfgspace_set_signaledpme_4748), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_cfgspace_set_signaledint ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_signaledint), + .Q(com_cmm_u_cmm_cfgspace_set_signaledint_4776), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_cfgspace_set_receivedtargetabort ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_receivedtargetabort), + .Q(com_cmm_u_cmm_cfgspace_set_receivedtargetabort_4749), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_cfgspace_set_receivedmasterabort ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_receivedmasterabort), + .Q(com_cmm_u_cmm_cfgspace_set_receivedmasterabort_4750), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_cfgspace_set_masterdataparityerror ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_masterdataparityerror), + .Q(com_cmm_u_cmm_cfgspace_set_masterdataparityerror_4751), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_cfgspace_set_detectedparityerror ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_detectedparityerror), + .Q(com_cmm_u_cmm_cfgspace_set_detectedparityerror_4752), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_cfgspace_sel_6x ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_cfgspace_N_68405_i), + .Q(com_cmm_u_cmm_cfgspace_sel_6x_4753), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_cfgspace_sel_5x ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_cfgspace_N_68711_i), + .Q(com_cmm_u_cmm_cfgspace_sel_5x_4754), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_cfgspace_sel_4x ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_cfgspace_N_68404_i), + .Q(com_cmm_u_cmm_cfgspace_sel_4x_4755), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_cfgspace_sel_3x ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_cfgspace_N_68336_i), + .Q(com_cmm_u_cmm_cfgspace_sel_3x_4756), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_cfgspace_sel_2x ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_cfgspace_N_68403_i), + .Q(com_cmm_u_cmm_cfgspace_sel_2x_4757), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_cfgspace_sel_1x ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_cfgspace_N_68402_i), + .Q(com_cmm_u_cmm_cfgspace_sel_1x_4758), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_cfgspace_sel_0x ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_cfgspace_N_68101_i), + .Q(com_cmm_u_cmm_cfgspace_sel_0x_4759), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_cfgspace_sel_x0 ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_cfgspace_N_28239_i), + .Q(com_cmm_u_cmm_cfgspace_sel_x0_4760), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_cfgspace_sel_xf ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_cfgspace_N_28269_i), + .Q(com_cmm_u_cmm_cfgspace_sel_xf_4761), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_cfgspace_sel_xe ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_cfgspace_N_28267_i), + .Q(com_cmm_u_cmm_cfgspace_sel_xe_4762), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_cfgspace_sel_xd ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_cfgspace_N_28265_i), + .Q(com_cmm_u_cmm_cfgspace_sel_xd_4763), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_cfgspace_sel_xc ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_cfgspace_N_28263_i), + .Q(com_cmm_u_cmm_cfgspace_sel_xc_4764), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_cfgspace_sel_xb ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_cfgspace_N_28261_i), + .Q(com_cmm_u_cmm_cfgspace_sel_xb_4765), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_cfgspace_sel_xa ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_cfgspace_N_28259_i), + .Q(com_cmm_u_cmm_cfgspace_sel_xa_4766), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_cfgspace_sel_x9 ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_cfgspace_N_28257_i), + .Q(com_cmm_u_cmm_cfgspace_sel_x9_4767), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_cfgspace_sel_x8 ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_cfgspace_N_28255_i), + .Q(com_cmm_u_cmm_cfgspace_sel_x8_4768), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_cfgspace_sel_x7 ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_cfgspace_N_28253_i), + .Q(com_cmm_u_cmm_cfgspace_sel_x7_4769), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_cfgspace_sel_x6 ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_cfgspace_N_28251_i), + .Q(com_cmm_u_cmm_cfgspace_sel_x6_4770), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_cfgspace_sel_x5 ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_cfgspace_N_28249_i), + .Q(com_cmm_u_cmm_cfgspace_sel_x5_4771), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_cfgspace_sel_x4 ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_cfgspace_N_28247_i), + .Q(com_cmm_u_cmm_cfgspace_sel_x4_4772), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_cfgspace_sel_x3 ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_cfgspace_N_28245_i), + .Q(com_cmm_u_cmm_cfgspace_sel_x3_4773), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_cfgspace_sel_x2 ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_cfgspace_N_28243_i), + .Q(com_cmm_u_cmm_cfgspace_sel_x2_4774), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_cfgspace_sel_x1 ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_cfgspace_N_28241_i), + .Q(com_cmm_u_cmm_cfgspace_sel_x1_4775), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_cfgspace_pme_pmcsr_1_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_cfgspace_N_43646_i), + .Q(com_cmm_pme_pmcsr[1]), + .CLR(trn_reset_n_i) + ); + FDC com_cmm_u_cmm_cfgspace_pme_pmcsr_0_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_cfgspace_N_43644_i), + .Q(com_cmm_pme_pmcsr[0]), + .CLR(trn_reset_n_i) + ); + FDC com_cmm_u_cmm_cfgspace_status_1_12_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_cfgspace_N_8858_i), + .Q(NlwRenamedSig_OI_cfg_status_12_), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_cfgspace_status_1_11_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_cfgspace_N_8857_i), + .Q(NlwRenamedSig_OI_cfg_status_11_), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_cfgspace_status_1_10_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_cfgspace_N_8856_i), + .Q(NlwRenamedSig_OI_cfg_status_8_), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_cfgspace_status_1_9_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_cfgspace_set_signaledint_4776), + .Q(NlwRenamedSig_OI_cfg_status_3_), + .CLR(com_cmm_rst_267) + ); + FDCE com_cmm_u_cmm_cfgspace_pme_pmcsr_15_ ( + .CE(com_cmm_rst_i_4285), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_cfgspace_N_8855_i), + .Q(com_cmm_u_cmm_cfgspace_pme_pmcsr[15]), + .CLR(trn_reset_n_i) + ); + FDC com_cmm_u_cmm_cfgspace_pme_pmcsr_14_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_cfgspace_pme_pmcsr_21[14]), + .Q(com_cmm_u_cmm_cfgspace_pme_pmcsr[14]), + .CLR(trn_reset_n_i) + ); + FDC com_cmm_u_cmm_cfgspace_pme_pmcsr_13_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_cfgspace_pme_pmcsr_21[13]), + .Q(com_cmm_u_cmm_cfgspace_pme_pmcsr[13]), + .CLR(trn_reset_n_i) + ); + FDC com_cmm_u_cmm_cfgspace_pme_pmcsr_12_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_cfgspace_N_40379_i), + .Q(com_cmm_u_cmm_cfgspace_pme_pmcsr[12]), + .CLR(trn_reset_n_i) + ); + FDC com_cmm_u_cmm_cfgspace_pme_pmcsr_11_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_cfgspace_N_44495_i), + .Q(com_cmm_u_cmm_cfgspace_pme_pmcsr[11]), + .CLR(trn_reset_n_i) + ); + FDC com_cmm_u_cmm_cfgspace_pme_pmcsr_10_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_cfgspace_N_43650_i), + .Q(com_cmm_u_cmm_cfgspace_pme_pmcsr[10]), + .CLR(trn_reset_n_i) + ); + FDC com_cmm_u_cmm_cfgspace_pme_pmcsr_9_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_cfgspace_N_43648_i), + .Q(com_cmm_u_cmm_cfgspace_pme_pmcsr[9]), + .CLR(trn_reset_n_i) + ); + FDCE com_cmm_u_cmm_cfgspace_pme_pmcsr_8_ ( + .CE(G_2996_0_a2_0_a2_0_a2_268), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_cfg_wr_data_16_), + .Q(com_cmm_u_cmm_cfgspace_pme_pmcsr[8]), + .CLR(trn_reset_n_i) + ); + FDC com_cmm_u_cmm_cfgspace_state_6_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_cfgspace_state_5__4777), + .Q(com_cmm_state_6_), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_cfgspace_state_5_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_cfgspace_state_4__4778), + .Q(com_cmm_u_cmm_cfgspace_state_5__4777), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_cfgspace_state_4_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_cfgspace_N_14826_i), + .Q(com_cmm_u_cmm_cfgspace_state_4__4778), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_cfgspace_state_3_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_cfgspace_state_2__4779), + .Q(com_cmm_u_cmm_cfgspace_cfg2ulm_valid), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_cfgspace_state_2_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_cfgspace_state_1__4780), + .Q(com_cmm_u_cmm_cfgspace_state_2__4779), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_cfgspace_state_1_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_cfgspace_N_14828_i), + .Q(com_cmm_u_cmm_cfgspace_state_1__4780), + .CLR(com_cmm_rst_267) + ); + FDP com_cmm_u_cmm_cfgspace_state_0_ ( + .PRE(com_cmm_rst_267), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_cfgspace_N_68102_i_4781), + .Q(com_cmm_u_cmm_cfgspace_state_0__4782) + ); + FDC com_cmm_u_cmm_cfgspace_x_dsts_1_5_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_cfgspace_set_transaction_pending_4783), + .Q(NlwRenamedSig_OI_cfg_dstatus_5_), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_cfgspace_x_dsts_1_3_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_cfgspace_N_8854_i), + .Q(NlwRenamedSig_OI_cfg_dstatus_3_), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_cfgspace_x_dsts_1_2_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_cfgspace_N_8853_i), + .Q(NlwRenamedSig_OI_cfg_dstatus_2_), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_cfgspace_x_dsts_1_1_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_cfgspace_N_8852_i), + .Q(NlwRenamedSig_OI_cfg_dstatus_1_), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_cfgspace_x_dsts_1_0_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_cfgspace_N_8851_i), + .Q(NlwRenamedSig_OI_cfg_dstatus_0_), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_cfgspace_status_1_15_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_cfgspace_N_8861_i), + .Q(NlwRenamedSig_OI_cfg_status_15_), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_cfgspace_status_1_14_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_cfgspace_N_8860_i), + .Q(NlwRenamedSig_OI_cfg_status_14_), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_cfgspace_status_1_13_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_cfgspace_N_8859_i), + .Q(NlwRenamedSig_OI_cfg_status_13_), + .CLR(com_cmm_rst_267) + ); + FDCE com_cmm_u_cmm_cfgspace_bar1_reg_14_ ( + .CE(com_cmm_u_cmm_cfgspace_bar1_reg45), + .C(NlwRenamedSig_OI_trn_clk), + .D(I_4195_0_a2_0_a2_0_a2_231), + .Q(com_cmm_bar1_reg[14]), + .CLR(com_cmm_rst_267) + ); + FDCE com_cmm_u_cmm_cfgspace_bar1_reg_13_ ( + .CE(com_cmm_u_cmm_cfgspace_bar1_reg45), + .C(NlwRenamedSig_OI_trn_clk), + .D(I_4200_0_a2_0_a2_230), + .Q(com_cmm_bar1_reg[13]), + .CLR(com_cmm_rst_267) + ); + FDCE com_cmm_u_cmm_cfgspace_bar1_reg_12_ ( + .CE(com_cmm_u_cmm_cfgspace_bar1_reg45), + .C(NlwRenamedSig_OI_trn_clk), + .D(I_4205_0_a2_0_a2_0_a2_0_a2_229), + .Q(com_cmm_bar1_reg[12]), + .CLR(com_cmm_rst_267) + ); + FDCE com_cmm_u_cmm_cfgspace_bar1_reg_11_ ( + .CE(com_cmm_u_cmm_cfgspace_bar1_reg45), + .C(NlwRenamedSig_OI_trn_clk), + .D(I_4210_0_a2_0_a2_0_a2_228), + .Q(com_cmm_bar1_reg[11]), + .CLR(com_cmm_rst_267) + ); + FDCE com_cmm_u_cmm_cfgspace_bar1_reg_10_ ( + .CE(com_cmm_u_cmm_cfgspace_bar1_reg45), + .C(NlwRenamedSig_OI_trn_clk), + .D(I_4215_0_a2_0_a2_0_a2_227), + .Q(com_cmm_bar1_reg[10]), + .CLR(com_cmm_rst_267) + ); + FDCE com_cmm_u_cmm_cfgspace_bar1_reg_9_ ( + .CE(com_cmm_u_cmm_cfgspace_bar1_reg45), + .C(NlwRenamedSig_OI_trn_clk), + .D(I_4220_0_a2_0_a2_0_a2_226), + .Q(com_cmm_bar1_reg[9]), + .CLR(com_cmm_rst_267) + ); + FDCE com_cmm_u_cmm_cfgspace_bar1_reg_8_ ( + .CE(com_cmm_u_cmm_cfgspace_bar1_reg45), + .C(NlwRenamedSig_OI_trn_clk), + .D(I_4225_0_a2_0_a2_0_a2_225), + .Q(com_cmm_bar1_reg[8]), + .CLR(com_cmm_rst_267) + ); + FDCE com_cmm_u_cmm_cfgspace_bar1_reg_7_ ( + .CE(com_cmm_u_cmm_cfgspace_N_44856_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(I_4230_0_a2_0_a2_0_a2_0_a2_224), + .Q(com_cmm_bar1_reg[7]), + .CLR(com_cmm_rst_267) + ); + FDCE com_cmm_u_cmm_cfgspace_bar1_reg_6_ ( + .CE(com_cmm_u_cmm_cfgspace_N_44856_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(I_4235_0_a2_0_a2_0_a2_0_a2_223), + .Q(com_cmm_bar1_reg[6]), + .CLR(com_cmm_rst_267) + ); + FDCE com_cmm_u_cmm_cfgspace_bar1_reg_5_ ( + .CE(com_cmm_u_cmm_cfgspace_N_44856_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(I_4240_0_a2_0_a2_0_a2_0_a2_222), + .Q(com_cmm_bar1_reg[5]), + .CLR(com_cmm_rst_267) + ); + FDCE com_cmm_u_cmm_cfgspace_bar1_reg_4_ ( + .CE(com_cmm_u_cmm_cfgspace_N_44856_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(I_4245_0_a2_0_a2_0_a2_0_a2_221), + .Q(com_cmm_bar1_reg[4]), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_cfgspace_bar1_reg_3_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_cfgspace_N_68143_i), + .Q(com_cmm_bar1_reg[3]), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_cfgspace_bar1_reg_2_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_cfgspace_N_68008_i), + .Q(com_cmm_bar1_reg[2]), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_cfgspace_bar1_reg_1_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_cfgspace_N_68142_i), + .Q(com_cmm_bar1_reg[1]), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_cfgspace_bar1_reg_0_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_cfgspace_N_68007_i), + .Q(com_cmm_bar1_reg[0]), + .CLR(com_cmm_rst_267) + ); + FDCE com_cmm_u_cmm_cfgspace_bar1_reg_29_ ( + .CE(com_cmm_u_cmm_cfgspace_bar1_reg70), + .C(NlwRenamedSig_OI_trn_clk), + .D(I_4250_0_a2_0_a2_0_a2_220), + .Q(com_cmm_bar1_reg[29]), + .CLR(com_cmm_rst_267) + ); + FDCE com_cmm_u_cmm_cfgspace_bar1_reg_28_ ( + .CE(com_cmm_u_cmm_cfgspace_bar1_reg70), + .C(NlwRenamedSig_OI_trn_clk), + .D(I_4255_0_a2_0_a2_0_a2_219), + .Q(com_cmm_bar1_reg[28]), + .CLR(com_cmm_rst_267) + ); + FDCE com_cmm_u_cmm_cfgspace_bar1_reg_27_ ( + .CE(com_cmm_u_cmm_cfgspace_bar1_reg70), + .C(NlwRenamedSig_OI_trn_clk), + .D(I_4260_0_a2_0_a2_0_a2_218), + .Q(com_cmm_bar1_reg[27]), + .CLR(com_cmm_rst_267) + ); + FDCE com_cmm_u_cmm_cfgspace_bar1_reg_26_ ( + .CE(com_cmm_u_cmm_cfgspace_bar1_reg70), + .C(NlwRenamedSig_OI_trn_clk), + .D(I_4265_0_a2_0_a2_217), + .Q(com_cmm_bar1_reg[26]), + .CLR(com_cmm_rst_267) + ); + FDCE com_cmm_u_cmm_cfgspace_bar1_reg_25_ ( + .CE(com_cmm_u_cmm_cfgspace_bar1_reg70), + .C(NlwRenamedSig_OI_trn_clk), + .D(I_4270_0_a2_0_a2_216), + .Q(com_cmm_bar1_reg[25]), + .CLR(com_cmm_rst_267) + ); + FDCE com_cmm_u_cmm_cfgspace_bar1_reg_24_ ( + .CE(com_cmm_u_cmm_cfgspace_bar1_reg70), + .C(NlwRenamedSig_OI_trn_clk), + .D(I_4275_0_a2_0_a2_215), + .Q(com_cmm_bar1_reg[24]), + .CLR(com_cmm_rst_267) + ); + FDCE com_cmm_u_cmm_cfgspace_bar1_reg_23_ ( + .CE(com_cmm_u_cmm_cfgspace_bar1_reg58), + .C(NlwRenamedSig_OI_trn_clk), + .D(I_4280_0_a2_0_a2_214), + .Q(com_cmm_bar1_reg[23]), + .CLR(com_cmm_rst_267) + ); + FDCE com_cmm_u_cmm_cfgspace_bar1_reg_22_ ( + .CE(com_cmm_u_cmm_cfgspace_bar1_reg58), + .C(NlwRenamedSig_OI_trn_clk), + .D(I_4285_0_a2_0_a2_0_a2_213), + .Q(com_cmm_bar1_reg[22]), + .CLR(com_cmm_rst_267) + ); + FDCE com_cmm_u_cmm_cfgspace_bar1_reg_21_ ( + .CE(com_cmm_u_cmm_cfgspace_bar1_reg58), + .C(NlwRenamedSig_OI_trn_clk), + .D(I_4290_0_a2_0_a2_0_a2_212), + .Q(com_cmm_bar1_reg[21]), + .CLR(com_cmm_rst_267) + ); + FDCE com_cmm_u_cmm_cfgspace_bar1_reg_20_ ( + .CE(com_cmm_u_cmm_cfgspace_bar1_reg58), + .C(NlwRenamedSig_OI_trn_clk), + .D(I_4295_0_a2_0_a2_0_a2_0_a2_211), + .Q(com_cmm_bar1_reg[20]), + .CLR(com_cmm_rst_267) + ); + FDCE com_cmm_u_cmm_cfgspace_bar1_reg_19_ ( + .CE(com_cmm_u_cmm_cfgspace_bar1_reg58), + .C(NlwRenamedSig_OI_trn_clk), + .D(I_4300_0_a2_0_a2_0_a2_210), + .Q(com_cmm_bar1_reg[19]), + .CLR(com_cmm_rst_267) + ); + FDCE com_cmm_u_cmm_cfgspace_bar1_reg_18_ ( + .CE(com_cmm_u_cmm_cfgspace_bar1_reg58), + .C(NlwRenamedSig_OI_trn_clk), + .D(I_4305_0_a2_0_a2_0_a2_0_a2_209), + .Q(com_cmm_bar1_reg[18]), + .CLR(com_cmm_rst_267) + ); + FDCE com_cmm_u_cmm_cfgspace_bar1_reg_17_ ( + .CE(com_cmm_u_cmm_cfgspace_bar1_reg58), + .C(NlwRenamedSig_OI_trn_clk), + .D(I_4310_0_a2_0_a2_0_a2_208), + .Q(com_cmm_bar1_reg[17]), + .CLR(com_cmm_rst_267) + ); + FDCE com_cmm_u_cmm_cfgspace_bar1_reg_16_ ( + .CE(com_cmm_u_cmm_cfgspace_bar1_reg58), + .C(NlwRenamedSig_OI_trn_clk), + .D(I_4315_0_a2_0_a2_0_a2_207), + .Q(com_cmm_bar1_reg[16]), + .CLR(com_cmm_rst_267) + ); + FDCE com_cmm_u_cmm_cfgspace_bar1_reg_15_ ( + .CE(com_cmm_u_cmm_cfgspace_bar1_reg45), + .C(NlwRenamedSig_OI_trn_clk), + .D(I_4320_0_a2_0_a2_0_a2_206), + .Q(com_cmm_bar1_reg[15]), + .CLR(com_cmm_rst_267) + ); + FDCE com_cmm_u_cmm_cfgspace_bar2_reg_12_ ( + .CE(com_cmm_u_cmm_cfgspace_bar2_reg45), + .C(NlwRenamedSig_OI_trn_clk), + .D(I_4325_0_a2_0_a2_0_a2_0_a2_205), + .Q(com_cmm_bar2_reg[12]), + .CLR(com_cmm_rst_267) + ); + FDCE com_cmm_u_cmm_cfgspace_bar2_reg_11_ ( + .CE(com_cmm_u_cmm_cfgspace_bar2_reg45), + .C(NlwRenamedSig_OI_trn_clk), + .D(I_4330_0_a2_0_a2_0_a2_204), + .Q(com_cmm_bar2_reg[11]), + .CLR(com_cmm_rst_267) + ); + FDCE com_cmm_u_cmm_cfgspace_bar2_reg_10_ ( + .CE(com_cmm_u_cmm_cfgspace_bar2_reg45), + .C(NlwRenamedSig_OI_trn_clk), + .D(I_4335_0_a2_0_a2_0_a2_203), + .Q(com_cmm_bar2_reg[10]), + .CLR(com_cmm_rst_267) + ); + FDCE com_cmm_u_cmm_cfgspace_bar2_reg_9_ ( + .CE(com_cmm_u_cmm_cfgspace_bar2_reg45), + .C(NlwRenamedSig_OI_trn_clk), + .D(I_4340_0_a2_0_a2_0_a2_202), + .Q(com_cmm_bar2_reg[9]), + .CLR(com_cmm_rst_267) + ); + FDCE com_cmm_u_cmm_cfgspace_bar2_reg_8_ ( + .CE(com_cmm_u_cmm_cfgspace_bar2_reg45), + .C(NlwRenamedSig_OI_trn_clk), + .D(I_4345_0_a2_0_a2_0_a2_201), + .Q(com_cmm_bar2_reg[8]), + .CLR(com_cmm_rst_267) + ); + FDCE com_cmm_u_cmm_cfgspace_bar2_reg_7_ ( + .CE(com_cmm_u_cmm_cfgspace_N_44857_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(I_4350_0_a2_0_a2_0_a2_0_a2_200), + .Q(com_cmm_bar2_reg[7]), + .CLR(com_cmm_rst_267) + ); + FDCE com_cmm_u_cmm_cfgspace_bar2_reg_6_ ( + .CE(com_cmm_u_cmm_cfgspace_N_44857_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(I_4355_0_a2_0_a2_0_a2_0_a2_199), + .Q(com_cmm_bar2_reg[6]), + .CLR(com_cmm_rst_267) + ); + FDCE com_cmm_u_cmm_cfgspace_bar2_reg_5_ ( + .CE(com_cmm_u_cmm_cfgspace_N_44857_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(I_4360_0_a2_0_a2_0_a2_0_a2_198), + .Q(com_cmm_bar2_reg[5]), + .CLR(com_cmm_rst_267) + ); + FDCE com_cmm_u_cmm_cfgspace_bar2_reg_4_ ( + .CE(com_cmm_u_cmm_cfgspace_N_44857_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(I_4365_0_a2_0_a2_0_a2_0_a2_197), + .Q(com_cmm_bar2_reg[4]), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_cfgspace_bar2_reg_3_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_cfgspace_N_68145_i), + .Q(com_cmm_bar2_reg[3]), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_cfgspace_bar2_reg_2_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_cfgspace_N_68010_i), + .Q(com_cmm_bar2_reg[2]), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_cfgspace_bar2_reg_1_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_cfgspace_N_68144_i), + .Q(com_cmm_bar2_reg[1]), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_cfgspace_bar2_reg_0_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_cfgspace_N_68009_i), + .Q(com_cmm_bar2_reg[0]), + .CLR(com_cmm_rst_267) + ); + FDCE com_cmm_u_cmm_cfgspace_bar1_reg_31_ ( + .CE(com_cmm_u_cmm_cfgspace_bar1_reg70), + .C(NlwRenamedSig_OI_trn_clk), + .D(I_4370_0_a2_0_a2_0_a2_196), + .Q(com_cmm_bar1_reg[31]), + .CLR(com_cmm_rst_267) + ); + FDCE com_cmm_u_cmm_cfgspace_bar1_reg_30_ ( + .CE(com_cmm_u_cmm_cfgspace_bar1_reg70), + .C(NlwRenamedSig_OI_trn_clk), + .D(I_4375_0_a2_0_a2_0_a2_195), + .Q(com_cmm_bar1_reg[30]), + .CLR(com_cmm_rst_267) + ); + FDCE com_cmm_u_cmm_cfgspace_bar2_reg_27_ ( + .CE(com_cmm_u_cmm_cfgspace_bar2_reg70), + .C(NlwRenamedSig_OI_trn_clk), + .D(I_4380_0_a2_0_a2_0_a2_194), + .Q(com_cmm_bar2_reg[27]), + .CLR(com_cmm_rst_267) + ); + FDCE com_cmm_u_cmm_cfgspace_bar2_reg_26_ ( + .CE(com_cmm_u_cmm_cfgspace_bar2_reg70), + .C(NlwRenamedSig_OI_trn_clk), + .D(I_4385_0_a2_0_a2_193), + .Q(com_cmm_bar2_reg[26]), + .CLR(com_cmm_rst_267) + ); + FDCE com_cmm_u_cmm_cfgspace_bar2_reg_25_ ( + .CE(com_cmm_u_cmm_cfgspace_bar2_reg70), + .C(NlwRenamedSig_OI_trn_clk), + .D(I_4390_0_a2_0_a2_192), + .Q(com_cmm_bar2_reg[25]), + .CLR(com_cmm_rst_267) + ); + FDCE com_cmm_u_cmm_cfgspace_bar2_reg_24_ ( + .CE(com_cmm_u_cmm_cfgspace_bar2_reg70), + .C(NlwRenamedSig_OI_trn_clk), + .D(I_4395_0_a2_0_a2_191), + .Q(com_cmm_bar2_reg[24]), + .CLR(com_cmm_rst_267) + ); + FDCE com_cmm_u_cmm_cfgspace_bar2_reg_23_ ( + .CE(com_cmm_u_cmm_cfgspace_bar2_reg58), + .C(NlwRenamedSig_OI_trn_clk), + .D(I_4400_0_a2_0_a2_190), + .Q(com_cmm_bar2_reg[23]), + .CLR(com_cmm_rst_267) + ); + FDCE com_cmm_u_cmm_cfgspace_bar2_reg_22_ ( + .CE(com_cmm_u_cmm_cfgspace_bar2_reg58), + .C(NlwRenamedSig_OI_trn_clk), + .D(I_4405_0_a2_0_a2_0_a2_189), + .Q(com_cmm_bar2_reg[22]), + .CLR(com_cmm_rst_267) + ); + FDCE com_cmm_u_cmm_cfgspace_bar2_reg_21_ ( + .CE(com_cmm_u_cmm_cfgspace_bar2_reg58), + .C(NlwRenamedSig_OI_trn_clk), + .D(I_4410_0_a2_0_a2_0_a2_188), + .Q(com_cmm_bar2_reg[21]), + .CLR(com_cmm_rst_267) + ); + FDCE com_cmm_u_cmm_cfgspace_bar2_reg_20_ ( + .CE(com_cmm_u_cmm_cfgspace_bar2_reg58), + .C(NlwRenamedSig_OI_trn_clk), + .D(I_4415_0_a2_0_a2_0_a2_0_a2_187), + .Q(com_cmm_bar2_reg[20]), + .CLR(com_cmm_rst_267) + ); + FDCE com_cmm_u_cmm_cfgspace_bar2_reg_19_ ( + .CE(com_cmm_u_cmm_cfgspace_bar2_reg58), + .C(NlwRenamedSig_OI_trn_clk), + .D(I_4420_0_a2_0_a2_0_a2_186), + .Q(com_cmm_bar2_reg[19]), + .CLR(com_cmm_rst_267) + ); + FDCE com_cmm_u_cmm_cfgspace_bar2_reg_18_ ( + .CE(com_cmm_u_cmm_cfgspace_bar2_reg58), + .C(NlwRenamedSig_OI_trn_clk), + .D(I_4425_0_a2_0_a2_0_a2_0_a2_185), + .Q(com_cmm_bar2_reg[18]), + .CLR(com_cmm_rst_267) + ); + FDCE com_cmm_u_cmm_cfgspace_bar2_reg_17_ ( + .CE(com_cmm_u_cmm_cfgspace_bar2_reg58), + .C(NlwRenamedSig_OI_trn_clk), + .D(I_4430_0_a2_0_a2_0_a2_184), + .Q(com_cmm_bar2_reg[17]), + .CLR(com_cmm_rst_267) + ); + FDCE com_cmm_u_cmm_cfgspace_bar2_reg_16_ ( + .CE(com_cmm_u_cmm_cfgspace_bar2_reg58), + .C(NlwRenamedSig_OI_trn_clk), + .D(I_4435_0_a2_0_a2_0_a2_183), + .Q(com_cmm_bar2_reg[16]), + .CLR(com_cmm_rst_267) + ); + FDCE com_cmm_u_cmm_cfgspace_bar2_reg_15_ ( + .CE(com_cmm_u_cmm_cfgspace_bar2_reg45), + .C(NlwRenamedSig_OI_trn_clk), + .D(I_4440_0_a2_0_a2_0_a2_182), + .Q(com_cmm_bar2_reg[15]), + .CLR(com_cmm_rst_267) + ); + FDCE com_cmm_u_cmm_cfgspace_bar2_reg_14_ ( + .CE(com_cmm_u_cmm_cfgspace_bar2_reg45), + .C(NlwRenamedSig_OI_trn_clk), + .D(I_4445_0_a2_0_a2_0_a2_181), + .Q(com_cmm_bar2_reg[14]), + .CLR(com_cmm_rst_267) + ); + FDCE com_cmm_u_cmm_cfgspace_bar2_reg_13_ ( + .CE(com_cmm_u_cmm_cfgspace_bar2_reg45), + .C(NlwRenamedSig_OI_trn_clk), + .D(I_4450_0_a2_0_a2_180), + .Q(com_cmm_bar2_reg[13]), + .CLR(com_cmm_rst_267) + ); + FDCE com_cmm_u_cmm_cfgspace_bar3_reg_10_ ( + .CE(com_cmm_u_cmm_cfgspace_bar3_reg45), + .C(NlwRenamedSig_OI_trn_clk), + .D(I_4455_0_a2_0_a2_0_a2_179), + .Q(com_cmm_bar3_reg[10]), + .CLR(com_cmm_rst_267) + ); + FDCE com_cmm_u_cmm_cfgspace_bar3_reg_9_ ( + .CE(com_cmm_u_cmm_cfgspace_bar3_reg45), + .C(NlwRenamedSig_OI_trn_clk), + .D(I_4460_0_a2_0_a2_0_a2_178), + .Q(com_cmm_bar3_reg[9]), + .CLR(com_cmm_rst_267) + ); + FDCE com_cmm_u_cmm_cfgspace_bar3_reg_8_ ( + .CE(com_cmm_u_cmm_cfgspace_bar3_reg45), + .C(NlwRenamedSig_OI_trn_clk), + .D(I_4465_0_a2_0_a2_0_a2_177), + .Q(com_cmm_bar3_reg[8]), + .CLR(com_cmm_rst_267) + ); + FDCE com_cmm_u_cmm_cfgspace_bar3_reg_7_ ( + .CE(com_cmm_u_cmm_cfgspace_N_44858_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(I_4470_0_a2_0_a2_0_a2_0_a2_176), + .Q(com_cmm_bar3_reg[7]), + .CLR(com_cmm_rst_267) + ); + FDCE com_cmm_u_cmm_cfgspace_bar3_reg_6_ ( + .CE(com_cmm_u_cmm_cfgspace_N_44858_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(I_4475_0_a2_0_a2_0_a2_0_a2_175), + .Q(com_cmm_bar3_reg[6]), + .CLR(com_cmm_rst_267) + ); + FDCE com_cmm_u_cmm_cfgspace_bar3_reg_5_ ( + .CE(com_cmm_u_cmm_cfgspace_N_44858_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(I_4480_0_a2_0_a2_0_a2_0_a2_174), + .Q(com_cmm_bar3_reg[5]), + .CLR(com_cmm_rst_267) + ); + FDCE com_cmm_u_cmm_cfgspace_bar3_reg_4_ ( + .CE(com_cmm_u_cmm_cfgspace_N_44858_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(I_4485_0_a2_0_a2_0_a2_0_a2_173), + .Q(com_cmm_bar3_reg[4]), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_cfgspace_bar3_reg_3_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_cfgspace_N_68147_i), + .Q(com_cmm_bar3_reg[3]), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_cfgspace_bar3_reg_2_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_cfgspace_N_68012_i), + .Q(com_cmm_bar3_reg[2]), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_cfgspace_bar3_reg_1_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_cfgspace_N_68146_i), + .Q(com_cmm_bar3_reg[1]), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_cfgspace_bar3_reg_0_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_cfgspace_N_68011_i), + .Q(com_cmm_bar3_reg[0]), + .CLR(com_cmm_rst_267) + ); + FDCE com_cmm_u_cmm_cfgspace_bar2_reg_31_ ( + .CE(com_cmm_u_cmm_cfgspace_bar2_reg70), + .C(NlwRenamedSig_OI_trn_clk), + .D(I_4490_0_a2_0_a2_0_a2_172), + .Q(com_cmm_bar2_reg[31]), + .CLR(com_cmm_rst_267) + ); + FDCE com_cmm_u_cmm_cfgspace_bar2_reg_30_ ( + .CE(com_cmm_u_cmm_cfgspace_bar2_reg70), + .C(NlwRenamedSig_OI_trn_clk), + .D(I_4495_0_a2_0_a2_0_a2_171), + .Q(com_cmm_bar2_reg[30]), + .CLR(com_cmm_rst_267) + ); + FDCE com_cmm_u_cmm_cfgspace_bar2_reg_29_ ( + .CE(com_cmm_u_cmm_cfgspace_bar2_reg70), + .C(NlwRenamedSig_OI_trn_clk), + .D(I_4500_0_a2_0_a2_0_a2_170), + .Q(com_cmm_bar2_reg[29]), + .CLR(com_cmm_rst_267) + ); + FDCE com_cmm_u_cmm_cfgspace_bar2_reg_28_ ( + .CE(com_cmm_u_cmm_cfgspace_bar2_reg70), + .C(NlwRenamedSig_OI_trn_clk), + .D(I_4505_0_a2_0_a2_0_a2_169), + .Q(com_cmm_bar2_reg[28]), + .CLR(com_cmm_rst_267) + ); + FDCE com_cmm_u_cmm_cfgspace_bar3_reg_25_ ( + .CE(com_cmm_u_cmm_cfgspace_bar3_reg70), + .C(NlwRenamedSig_OI_trn_clk), + .D(I_4510_0_a2_0_a2_168), + .Q(com_cmm_bar3_reg[25]), + .CLR(com_cmm_rst_267) + ); + FDCE com_cmm_u_cmm_cfgspace_bar3_reg_24_ ( + .CE(com_cmm_u_cmm_cfgspace_bar3_reg70), + .C(NlwRenamedSig_OI_trn_clk), + .D(I_4515_0_a2_0_a2_167), + .Q(com_cmm_bar3_reg[24]), + .CLR(com_cmm_rst_267) + ); + FDCE com_cmm_u_cmm_cfgspace_bar3_reg_23_ ( + .CE(com_cmm_u_cmm_cfgspace_bar3_reg58), + .C(NlwRenamedSig_OI_trn_clk), + .D(I_4520_0_a2_0_a2_166), + .Q(com_cmm_bar3_reg[23]), + .CLR(com_cmm_rst_267) + ); + FDCE com_cmm_u_cmm_cfgspace_bar3_reg_22_ ( + .CE(com_cmm_u_cmm_cfgspace_bar3_reg58), + .C(NlwRenamedSig_OI_trn_clk), + .D(I_4525_0_a2_0_a2_0_a2_165), + .Q(com_cmm_bar3_reg[22]), + .CLR(com_cmm_rst_267) + ); + FDCE com_cmm_u_cmm_cfgspace_bar3_reg_21_ ( + .CE(com_cmm_u_cmm_cfgspace_bar3_reg58), + .C(NlwRenamedSig_OI_trn_clk), + .D(I_4530_0_a2_0_a2_0_a2_164), + .Q(com_cmm_bar3_reg[21]), + .CLR(com_cmm_rst_267) + ); + FDCE com_cmm_u_cmm_cfgspace_bar3_reg_20_ ( + .CE(com_cmm_u_cmm_cfgspace_bar3_reg58), + .C(NlwRenamedSig_OI_trn_clk), + .D(I_4535_0_a2_0_a2_0_a2_0_a2_163), + .Q(com_cmm_bar3_reg[20]), + .CLR(com_cmm_rst_267) + ); + FDCE com_cmm_u_cmm_cfgspace_bar3_reg_19_ ( + .CE(com_cmm_u_cmm_cfgspace_bar3_reg58), + .C(NlwRenamedSig_OI_trn_clk), + .D(I_4540_0_a2_0_a2_0_a2_162), + .Q(com_cmm_bar3_reg[19]), + .CLR(com_cmm_rst_267) + ); + FDCE com_cmm_u_cmm_cfgspace_bar3_reg_18_ ( + .CE(com_cmm_u_cmm_cfgspace_bar3_reg58), + .C(NlwRenamedSig_OI_trn_clk), + .D(I_4545_0_a2_0_a2_0_a2_0_a2_161), + .Q(com_cmm_bar3_reg[18]), + .CLR(com_cmm_rst_267) + ); + FDCE com_cmm_u_cmm_cfgspace_bar3_reg_17_ ( + .CE(com_cmm_u_cmm_cfgspace_bar3_reg58), + .C(NlwRenamedSig_OI_trn_clk), + .D(I_4550_0_a2_0_a2_0_a2_160), + .Q(com_cmm_bar3_reg[17]), + .CLR(com_cmm_rst_267) + ); + FDCE com_cmm_u_cmm_cfgspace_bar3_reg_16_ ( + .CE(com_cmm_u_cmm_cfgspace_bar3_reg58), + .C(NlwRenamedSig_OI_trn_clk), + .D(I_4555_0_a2_0_a2_0_a2_159), + .Q(com_cmm_bar3_reg[16]), + .CLR(com_cmm_rst_267) + ); + FDCE com_cmm_u_cmm_cfgspace_bar3_reg_15_ ( + .CE(com_cmm_u_cmm_cfgspace_bar3_reg45), + .C(NlwRenamedSig_OI_trn_clk), + .D(I_4560_0_a2_0_a2_0_a2_158), + .Q(com_cmm_bar3_reg[15]), + .CLR(com_cmm_rst_267) + ); + FDCE com_cmm_u_cmm_cfgspace_bar3_reg_14_ ( + .CE(com_cmm_u_cmm_cfgspace_bar3_reg45), + .C(NlwRenamedSig_OI_trn_clk), + .D(I_4565_0_a2_0_a2_0_a2_157), + .Q(com_cmm_bar3_reg[14]), + .CLR(com_cmm_rst_267) + ); + FDCE com_cmm_u_cmm_cfgspace_bar3_reg_13_ ( + .CE(com_cmm_u_cmm_cfgspace_bar3_reg45), + .C(NlwRenamedSig_OI_trn_clk), + .D(I_4570_0_a2_0_a2_156), + .Q(com_cmm_bar3_reg[13]), + .CLR(com_cmm_rst_267) + ); + FDCE com_cmm_u_cmm_cfgspace_bar3_reg_12_ ( + .CE(com_cmm_u_cmm_cfgspace_bar3_reg45), + .C(NlwRenamedSig_OI_trn_clk), + .D(I_4575_0_a2_0_a2_0_a2_0_a2_155), + .Q(com_cmm_bar3_reg[12]), + .CLR(com_cmm_rst_267) + ); + FDCE com_cmm_u_cmm_cfgspace_bar3_reg_11_ ( + .CE(com_cmm_u_cmm_cfgspace_bar3_reg45), + .C(NlwRenamedSig_OI_trn_clk), + .D(I_4580_0_a2_0_a2_0_a2_154), + .Q(com_cmm_bar3_reg[11]), + .CLR(com_cmm_rst_267) + ); + FDCE com_cmm_u_cmm_cfgspace_bar4_reg_8_ ( + .CE(com_cmm_u_cmm_cfgspace_bar4_reg45), + .C(NlwRenamedSig_OI_trn_clk), + .D(I_4585_0_a2_0_a2_0_a2_153), + .Q(com_cmm_bar4_reg[8]), + .CLR(com_cmm_rst_267) + ); + FDCE com_cmm_u_cmm_cfgspace_bar4_reg_7_ ( + .CE(com_cmm_u_cmm_cfgspace_N_48868_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(I_4590_0_a2_0_a2_0_a2_0_a2_152), + .Q(com_cmm_bar4_reg[7]), + .CLR(com_cmm_rst_267) + ); + FDCE com_cmm_u_cmm_cfgspace_bar4_reg_6_ ( + .CE(com_cmm_u_cmm_cfgspace_N_48868_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(I_4595_0_a2_0_a2_0_a2_0_a2_151), + .Q(com_cmm_bar4_reg[6]), + .CLR(com_cmm_rst_267) + ); + FDCE com_cmm_u_cmm_cfgspace_bar4_reg_5_ ( + .CE(com_cmm_u_cmm_cfgspace_N_48868_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(I_4600_0_a2_0_a2_0_a2_0_a2_150), + .Q(com_cmm_bar4_reg[5]), + .CLR(com_cmm_rst_267) + ); + FDCE com_cmm_u_cmm_cfgspace_bar4_reg_4_ ( + .CE(com_cmm_u_cmm_cfgspace_N_48868_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(I_4605_0_a2_0_a2_0_a2_0_a2_149), + .Q(com_cmm_bar4_reg[4]), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_cfgspace_bar4_reg_3_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_cfgspace_N_68151_i), + .Q(com_cmm_bar4_reg[3]), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_cfgspace_bar4_reg_2_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_cfgspace_N_68150_i), + .Q(com_cmm_bar4_reg[2]), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_cfgspace_bar4_reg_1_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_cfgspace_N_68149_i), + .Q(com_cmm_bar4_reg[1]), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_cfgspace_bar4_reg_0_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_cfgspace_N_68148_i), + .Q(com_cmm_bar4_reg[0]), + .CLR(com_cmm_rst_267) + ); + FDCE com_cmm_u_cmm_cfgspace_bar3_reg_31_ ( + .CE(com_cmm_u_cmm_cfgspace_bar3_reg70), + .C(NlwRenamedSig_OI_trn_clk), + .D(I_4610_0_a2_0_a2_0_a2_148), + .Q(com_cmm_bar3_reg[31]), + .CLR(com_cmm_rst_267) + ); + FDCE com_cmm_u_cmm_cfgspace_bar3_reg_30_ ( + .CE(com_cmm_u_cmm_cfgspace_bar3_reg70), + .C(NlwRenamedSig_OI_trn_clk), + .D(I_4615_0_a2_0_a2_0_a2_147), + .Q(com_cmm_bar3_reg[30]), + .CLR(com_cmm_rst_267) + ); + FDCE com_cmm_u_cmm_cfgspace_bar3_reg_29_ ( + .CE(com_cmm_u_cmm_cfgspace_bar3_reg70), + .C(NlwRenamedSig_OI_trn_clk), + .D(I_4620_0_a2_0_a2_0_a2_146), + .Q(com_cmm_bar3_reg[29]), + .CLR(com_cmm_rst_267) + ); + FDCE com_cmm_u_cmm_cfgspace_bar3_reg_28_ ( + .CE(com_cmm_u_cmm_cfgspace_bar3_reg70), + .C(NlwRenamedSig_OI_trn_clk), + .D(I_4625_0_a2_0_a2_0_a2_145), + .Q(com_cmm_bar3_reg[28]), + .CLR(com_cmm_rst_267) + ); + FDCE com_cmm_u_cmm_cfgspace_bar3_reg_27_ ( + .CE(com_cmm_u_cmm_cfgspace_bar3_reg70), + .C(NlwRenamedSig_OI_trn_clk), + .D(I_4630_0_a2_0_a2_0_a2_144), + .Q(com_cmm_bar3_reg[27]), + .CLR(com_cmm_rst_267) + ); + FDCE com_cmm_u_cmm_cfgspace_bar3_reg_26_ ( + .CE(com_cmm_u_cmm_cfgspace_bar3_reg70), + .C(NlwRenamedSig_OI_trn_clk), + .D(I_4635_0_a2_0_a2_143), + .Q(com_cmm_bar3_reg[26]), + .CLR(com_cmm_rst_267) + ); + FDCE com_cmm_u_cmm_cfgspace_bar4_reg_23_ ( + .CE(com_cmm_u_cmm_cfgspace_bar4_reg58), + .C(NlwRenamedSig_OI_trn_clk), + .D(I_4640_0_a2_0_a2_142), + .Q(com_cmm_bar4_reg[23]), + .CLR(com_cmm_rst_267) + ); + FDCE com_cmm_u_cmm_cfgspace_bar4_reg_22_ ( + .CE(com_cmm_u_cmm_cfgspace_bar4_reg58), + .C(NlwRenamedSig_OI_trn_clk), + .D(I_4645_0_a2_0_a2_0_a2_141), + .Q(com_cmm_bar4_reg[22]), + .CLR(com_cmm_rst_267) + ); + FDCE com_cmm_u_cmm_cfgspace_bar4_reg_21_ ( + .CE(com_cmm_u_cmm_cfgspace_bar4_reg58), + .C(NlwRenamedSig_OI_trn_clk), + .D(I_4650_0_a2_0_a2_0_a2_140), + .Q(com_cmm_bar4_reg[21]), + .CLR(com_cmm_rst_267) + ); + FDCE com_cmm_u_cmm_cfgspace_bar4_reg_20_ ( + .CE(com_cmm_u_cmm_cfgspace_bar4_reg58), + .C(NlwRenamedSig_OI_trn_clk), + .D(I_4655_0_a2_0_a2_0_a2_0_a2_139), + .Q(com_cmm_bar4_reg[20]), + .CLR(com_cmm_rst_267) + ); + FDCE com_cmm_u_cmm_cfgspace_bar4_reg_19_ ( + .CE(com_cmm_u_cmm_cfgspace_bar4_reg58), + .C(NlwRenamedSig_OI_trn_clk), + .D(I_4660_0_a2_0_a2_0_a2_138), + .Q(com_cmm_bar4_reg[19]), + .CLR(com_cmm_rst_267) + ); + FDCE com_cmm_u_cmm_cfgspace_bar4_reg_18_ ( + .CE(com_cmm_u_cmm_cfgspace_bar4_reg58), + .C(NlwRenamedSig_OI_trn_clk), + .D(I_4665_0_a2_0_a2_0_a2_0_a2_137), + .Q(com_cmm_bar4_reg[18]), + .CLR(com_cmm_rst_267) + ); + FDCE com_cmm_u_cmm_cfgspace_bar4_reg_17_ ( + .CE(com_cmm_u_cmm_cfgspace_bar4_reg58), + .C(NlwRenamedSig_OI_trn_clk), + .D(I_4670_0_a2_0_a2_0_a2_136), + .Q(com_cmm_bar4_reg[17]), + .CLR(com_cmm_rst_267) + ); + FDCE com_cmm_u_cmm_cfgspace_bar4_reg_16_ ( + .CE(com_cmm_u_cmm_cfgspace_bar4_reg58), + .C(NlwRenamedSig_OI_trn_clk), + .D(I_4675_0_a2_0_a2_0_a2_135), + .Q(com_cmm_bar4_reg[16]), + .CLR(com_cmm_rst_267) + ); + FDCE com_cmm_u_cmm_cfgspace_bar4_reg_15_ ( + .CE(com_cmm_u_cmm_cfgspace_bar4_reg45), + .C(NlwRenamedSig_OI_trn_clk), + .D(I_4680_0_a2_0_a2_0_a2_134), + .Q(com_cmm_bar4_reg[15]), + .CLR(com_cmm_rst_267) + ); + FDCE com_cmm_u_cmm_cfgspace_bar4_reg_14_ ( + .CE(com_cmm_u_cmm_cfgspace_bar4_reg45), + .C(NlwRenamedSig_OI_trn_clk), + .D(I_4685_0_a2_0_a2_0_a2_133), + .Q(com_cmm_bar4_reg[14]), + .CLR(com_cmm_rst_267) + ); + FDCE com_cmm_u_cmm_cfgspace_bar4_reg_13_ ( + .CE(com_cmm_u_cmm_cfgspace_bar4_reg45), + .C(NlwRenamedSig_OI_trn_clk), + .D(I_4690_0_a2_0_a2_132), + .Q(com_cmm_bar4_reg[13]), + .CLR(com_cmm_rst_267) + ); + FDCE com_cmm_u_cmm_cfgspace_bar4_reg_12_ ( + .CE(com_cmm_u_cmm_cfgspace_bar4_reg45), + .C(NlwRenamedSig_OI_trn_clk), + .D(I_4695_0_a2_0_a2_0_a2_0_a2_131), + .Q(com_cmm_bar4_reg[12]), + .CLR(com_cmm_rst_267) + ); + FDCE com_cmm_u_cmm_cfgspace_bar4_reg_11_ ( + .CE(com_cmm_u_cmm_cfgspace_bar4_reg45), + .C(NlwRenamedSig_OI_trn_clk), + .D(I_4700_0_a2_0_a2_0_a2_130), + .Q(com_cmm_bar4_reg[11]), + .CLR(com_cmm_rst_267) + ); + FDCE com_cmm_u_cmm_cfgspace_bar4_reg_10_ ( + .CE(com_cmm_u_cmm_cfgspace_bar4_reg45), + .C(NlwRenamedSig_OI_trn_clk), + .D(I_4705_0_a2_0_a2_0_a2_129), + .Q(com_cmm_bar4_reg[10]), + .CLR(com_cmm_rst_267) + ); + FDCE com_cmm_u_cmm_cfgspace_bar4_reg_9_ ( + .CE(com_cmm_u_cmm_cfgspace_bar4_reg45), + .C(NlwRenamedSig_OI_trn_clk), + .D(I_4710_0_a2_0_a2_0_a2_128), + .Q(com_cmm_bar4_reg[9]), + .CLR(com_cmm_rst_267) + ); + FDCE com_cmm_u_cmm_cfgspace_bar5_reg_6_ ( + .CE(com_cmm_u_cmm_cfgspace_N_44854_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(I_4715_0_a2_0_a2_0_a2_0_a2_127), + .Q(com_cmm_bar5_reg[6]), + .CLR(com_cmm_rst_267) + ); + FDCE com_cmm_u_cmm_cfgspace_bar5_reg_5_ ( + .CE(com_cmm_u_cmm_cfgspace_N_44854_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(I_4720_0_a2_0_a2_0_a2_0_a2_126), + .Q(com_cmm_bar5_reg[5]), + .CLR(com_cmm_rst_267) + ); + FDCE com_cmm_u_cmm_cfgspace_bar5_reg_4_ ( + .CE(com_cmm_u_cmm_cfgspace_N_44854_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(I_4725_0_a2_0_a2_0_a2_0_a2_125), + .Q(com_cmm_bar5_reg[4]), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_cfgspace_bar5_reg_3_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_cfgspace_N_68141_i), + .Q(com_cmm_bar5_reg[3]), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_cfgspace_bar5_reg_2_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_cfgspace_N_68140_i), + .Q(com_cmm_bar5_reg[2]), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_cfgspace_bar5_reg_1_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_cfgspace_N_68139_i), + .Q(com_cmm_bar5_reg[1]), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_cfgspace_bar5_reg_0_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_cfgspace_N_68138_i), + .Q(com_cmm_bar5_reg[0]), + .CLR(com_cmm_rst_267) + ); + FDCE com_cmm_u_cmm_cfgspace_bar4_reg_31_ ( + .CE(com_cmm_u_cmm_cfgspace_bar4_reg70), + .C(NlwRenamedSig_OI_trn_clk), + .D(I_4730_0_a2_0_a2_0_a2_124), + .Q(com_cmm_bar4_reg[31]), + .CLR(com_cmm_rst_267) + ); + FDCE com_cmm_u_cmm_cfgspace_bar4_reg_30_ ( + .CE(com_cmm_u_cmm_cfgspace_bar4_reg70), + .C(NlwRenamedSig_OI_trn_clk), + .D(I_4735_0_a2_0_a2_0_a2_123), + .Q(com_cmm_bar4_reg[30]), + .CLR(com_cmm_rst_267) + ); + FDCE com_cmm_u_cmm_cfgspace_bar4_reg_29_ ( + .CE(com_cmm_u_cmm_cfgspace_bar4_reg70), + .C(NlwRenamedSig_OI_trn_clk), + .D(I_4740_0_a2_0_a2_0_a2_122), + .Q(com_cmm_bar4_reg[29]), + .CLR(com_cmm_rst_267) + ); + FDCE com_cmm_u_cmm_cfgspace_bar4_reg_28_ ( + .CE(com_cmm_u_cmm_cfgspace_bar4_reg70), + .C(NlwRenamedSig_OI_trn_clk), + .D(I_4745_0_a2_0_a2_0_a2_121), + .Q(com_cmm_bar4_reg[28]), + .CLR(com_cmm_rst_267) + ); + FDCE com_cmm_u_cmm_cfgspace_bar4_reg_27_ ( + .CE(com_cmm_u_cmm_cfgspace_bar4_reg70), + .C(NlwRenamedSig_OI_trn_clk), + .D(I_4750_0_a2_0_a2_0_a2_120), + .Q(com_cmm_bar4_reg[27]), + .CLR(com_cmm_rst_267) + ); + FDCE com_cmm_u_cmm_cfgspace_bar4_reg_26_ ( + .CE(com_cmm_u_cmm_cfgspace_bar4_reg70), + .C(NlwRenamedSig_OI_trn_clk), + .D(I_4755_0_a2_0_a2_119), + .Q(com_cmm_bar4_reg[26]), + .CLR(com_cmm_rst_267) + ); + FDCE com_cmm_u_cmm_cfgspace_bar4_reg_25_ ( + .CE(com_cmm_u_cmm_cfgspace_bar4_reg70), + .C(NlwRenamedSig_OI_trn_clk), + .D(I_4760_0_a2_0_a2_118), + .Q(com_cmm_bar4_reg[25]), + .CLR(com_cmm_rst_267) + ); + FDCE com_cmm_u_cmm_cfgspace_bar4_reg_24_ ( + .CE(com_cmm_u_cmm_cfgspace_bar4_reg70), + .C(NlwRenamedSig_OI_trn_clk), + .D(I_4765_0_a2_0_a2_117), + .Q(com_cmm_bar4_reg[24]), + .CLR(com_cmm_rst_267) + ); + FDCE com_cmm_u_cmm_cfgspace_bar5_reg_21_ ( + .CE(com_cmm_u_cmm_cfgspace_bar5_reg58), + .C(NlwRenamedSig_OI_trn_clk), + .D(I_4770_0_a2_0_a2_0_a2_0_a2_116), + .Q(com_cmm_bar5_reg[21]), + .CLR(com_cmm_rst_267) + ); + FDCE com_cmm_u_cmm_cfgspace_bar5_reg_20_ ( + .CE(com_cmm_u_cmm_cfgspace_bar5_reg58), + .C(NlwRenamedSig_OI_trn_clk), + .D(I_4775_0_a2_0_a2_0_a2_0_a2_115), + .Q(com_cmm_bar5_reg[20]), + .CLR(com_cmm_rst_267) + ); + FDCE com_cmm_u_cmm_cfgspace_bar5_reg_19_ ( + .CE(com_cmm_u_cmm_cfgspace_bar5_reg58), + .C(NlwRenamedSig_OI_trn_clk), + .D(I_4780_0_a2_0_a2_0_a2_0_a2_114), + .Q(com_cmm_bar5_reg[19]), + .CLR(com_cmm_rst_267) + ); + FDCE com_cmm_u_cmm_cfgspace_bar5_reg_18_ ( + .CE(com_cmm_u_cmm_cfgspace_bar5_reg58), + .C(NlwRenamedSig_OI_trn_clk), + .D(I_4785_0_a2_0_a2_0_a2_0_a2_113), + .Q(com_cmm_bar5_reg[18]), + .CLR(com_cmm_rst_267) + ); + FDCE com_cmm_u_cmm_cfgspace_bar5_reg_17_ ( + .CE(com_cmm_u_cmm_cfgspace_bar5_reg58), + .C(NlwRenamedSig_OI_trn_clk), + .D(I_4790_0_a2_0_a2_0_a2_0_a2_112), + .Q(com_cmm_bar5_reg[17]), + .CLR(com_cmm_rst_267) + ); + FDCE com_cmm_u_cmm_cfgspace_bar5_reg_16_ ( + .CE(com_cmm_u_cmm_cfgspace_bar5_reg58), + .C(NlwRenamedSig_OI_trn_clk), + .D(I_4795_0_a2_0_a2_0_a2_0_a2_111), + .Q(com_cmm_bar5_reg[16]), + .CLR(com_cmm_rst_267) + ); + FDCE com_cmm_u_cmm_cfgspace_bar5_reg_15_ ( + .CE(com_cmm_u_cmm_cfgspace_bar5_reg45), + .C(NlwRenamedSig_OI_trn_clk), + .D(I_4800_0_a2_0_a2_0_a2_110), + .Q(com_cmm_bar5_reg[15]), + .CLR(com_cmm_rst_267) + ); + FDCE com_cmm_u_cmm_cfgspace_bar5_reg_14_ ( + .CE(com_cmm_u_cmm_cfgspace_bar5_reg45), + .C(NlwRenamedSig_OI_trn_clk), + .D(I_4805_0_a2_0_a2_0_a2_109), + .Q(com_cmm_bar5_reg[14]), + .CLR(com_cmm_rst_267) + ); + FDCE com_cmm_u_cmm_cfgspace_bar5_reg_13_ ( + .CE(com_cmm_u_cmm_cfgspace_bar5_reg45), + .C(NlwRenamedSig_OI_trn_clk), + .D(I_4810_0_a2_0_a2_108), + .Q(com_cmm_bar5_reg[13]), + .CLR(com_cmm_rst_267) + ); + FDCE com_cmm_u_cmm_cfgspace_bar5_reg_12_ ( + .CE(com_cmm_u_cmm_cfgspace_bar5_reg45), + .C(NlwRenamedSig_OI_trn_clk), + .D(I_4815_0_a2_0_a2_0_a2_0_a2_107), + .Q(com_cmm_bar5_reg[12]), + .CLR(com_cmm_rst_267) + ); + FDCE com_cmm_u_cmm_cfgspace_bar5_reg_11_ ( + .CE(com_cmm_u_cmm_cfgspace_bar5_reg45), + .C(NlwRenamedSig_OI_trn_clk), + .D(I_4820_0_a2_0_a2_0_a2_106), + .Q(com_cmm_bar5_reg[11]), + .CLR(com_cmm_rst_267) + ); + FDCE com_cmm_u_cmm_cfgspace_bar5_reg_10_ ( + .CE(com_cmm_u_cmm_cfgspace_bar5_reg45), + .C(NlwRenamedSig_OI_trn_clk), + .D(I_4825_0_a2_0_a2_0_a2_105), + .Q(com_cmm_bar5_reg[10]), + .CLR(com_cmm_rst_267) + ); + FDCE com_cmm_u_cmm_cfgspace_bar5_reg_9_ ( + .CE(com_cmm_u_cmm_cfgspace_bar5_reg45), + .C(NlwRenamedSig_OI_trn_clk), + .D(I_4830_0_a2_0_a2_0_a2_104), + .Q(com_cmm_bar5_reg[9]), + .CLR(com_cmm_rst_267) + ); + FDCE com_cmm_u_cmm_cfgspace_bar5_reg_8_ ( + .CE(com_cmm_u_cmm_cfgspace_bar5_reg45), + .C(NlwRenamedSig_OI_trn_clk), + .D(I_4835_0_a2_0_a2_0_a2_103), + .Q(com_cmm_bar5_reg[8]), + .CLR(com_cmm_rst_267) + ); + FDCE com_cmm_u_cmm_cfgspace_bar5_reg_7_ ( + .CE(com_cmm_u_cmm_cfgspace_N_44854_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(I_4840_0_a2_0_a2_0_a2_0_a2_102), + .Q(com_cmm_bar5_reg[7]), + .CLR(com_cmm_rst_267) + ); + FDP com_cmm_u_cmm_cfgspace_x_dcmd_1_4_ ( + .PRE(trn_reset_n_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_cfgspace_N_68512_i_4784), + .Q(NlwRenamedSig_OI_cfg_dcommand[4]) + ); + FDC com_cmm_u_cmm_cfgspace_x_dcmd_1_3_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_cfgspace_N_20148_i), + .Q(NlwRenamedSig_OI_cfg_dcommand[3]), + .CLR(trn_reset_n_i) + ); + FDC com_cmm_u_cmm_cfgspace_x_dcmd_1_2_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_cfgspace_N_43713_i), + .Q(NlwRenamedSig_OI_cfg_dcommand[2]), + .CLR(trn_reset_n_i) + ); + FDC com_cmm_u_cmm_cfgspace_x_dcmd_1_1_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_cfgspace_N_29858_i), + .Q(NlwRenamedSig_OI_cfg_dcommand[1]), + .CLR(trn_reset_n_i) + ); + FDC com_cmm_u_cmm_cfgspace_x_dcmd_1_0_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_cfgspace_N_43947_i), + .Q(NlwRenamedSig_OI_cfg_dcommand[0]), + .CLR(trn_reset_n_i) + ); + FDCE com_cmm_u_cmm_cfgspace_bar5_reg_31_ ( + .CE(com_cmm_u_cmm_cfgspace_bar5_reg70), + .C(NlwRenamedSig_OI_trn_clk), + .D(I_4845_0_a2_0_a2_0_a2_101), + .Q(com_cmm_bar5_reg[31]), + .CLR(com_cmm_rst_267) + ); + FDCE com_cmm_u_cmm_cfgspace_bar5_reg_30_ ( + .CE(com_cmm_u_cmm_cfgspace_bar5_reg70), + .C(NlwRenamedSig_OI_trn_clk), + .D(I_4850_0_a2_0_a2_0_a2_100), + .Q(com_cmm_bar5_reg[30]), + .CLR(com_cmm_rst_267) + ); + FDCE com_cmm_u_cmm_cfgspace_bar5_reg_29_ ( + .CE(com_cmm_u_cmm_cfgspace_bar5_reg70), + .C(NlwRenamedSig_OI_trn_clk), + .D(I_4855_0_a2_0_a2_0_a2_99), + .Q(com_cmm_bar5_reg[29]), + .CLR(com_cmm_rst_267) + ); + FDCE com_cmm_u_cmm_cfgspace_bar5_reg_28_ ( + .CE(com_cmm_u_cmm_cfgspace_bar5_reg70), + .C(NlwRenamedSig_OI_trn_clk), + .D(I_4860_0_a2_0_a2_0_a2_98), + .Q(com_cmm_bar5_reg[28]), + .CLR(com_cmm_rst_267) + ); + FDCE com_cmm_u_cmm_cfgspace_bar5_reg_27_ ( + .CE(com_cmm_u_cmm_cfgspace_bar5_reg70), + .C(NlwRenamedSig_OI_trn_clk), + .D(I_4865_0_a2_0_a2_0_a2_97), + .Q(com_cmm_bar5_reg[27]), + .CLR(com_cmm_rst_267) + ); + FDCE com_cmm_u_cmm_cfgspace_bar5_reg_26_ ( + .CE(com_cmm_u_cmm_cfgspace_bar5_reg70), + .C(NlwRenamedSig_OI_trn_clk), + .D(I_4870_0_a2_0_a2_96), + .Q(com_cmm_bar5_reg[26]), + .CLR(com_cmm_rst_267) + ); + FDCE com_cmm_u_cmm_cfgspace_bar5_reg_25_ ( + .CE(com_cmm_u_cmm_cfgspace_bar5_reg70), + .C(NlwRenamedSig_OI_trn_clk), + .D(I_4875_0_a2_0_a2_95), + .Q(com_cmm_bar5_reg[25]), + .CLR(com_cmm_rst_267) + ); + FDCE com_cmm_u_cmm_cfgspace_bar5_reg_24_ ( + .CE(com_cmm_u_cmm_cfgspace_bar5_reg70), + .C(NlwRenamedSig_OI_trn_clk), + .D(I_4880_0_a2_0_a2_0_a2_94), + .Q(com_cmm_bar5_reg[24]), + .CLR(com_cmm_rst_267) + ); + FDCE com_cmm_u_cmm_cfgspace_bar5_reg_23_ ( + .CE(com_cmm_u_cmm_cfgspace_bar5_reg58), + .C(NlwRenamedSig_OI_trn_clk), + .D(I_4885_0_a2_0_a2_93), + .Q(com_cmm_bar5_reg[23]), + .CLR(com_cmm_rst_267) + ); + FDCE com_cmm_u_cmm_cfgspace_bar5_reg_22_ ( + .CE(com_cmm_u_cmm_cfgspace_bar5_reg58), + .C(NlwRenamedSig_OI_trn_clk), + .D(I_4890_0_a2_0_a2_0_a2_0_a2_92), + .Q(com_cmm_bar5_reg[22]), + .CLR(com_cmm_rst_267) + ); + FDCE com_cmm_u_cmm_cfgspace_msi_haddr_4_ ( + .CE(com_cmm_u_cmm_cfgspace_msi_haddr12), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_cfg_wr_data_28_), + .Q(com_cmm_msi_haddr[4]), + .CLR(com_cmm_rst_267) + ); + FDCE com_cmm_u_cmm_cfgspace_msi_haddr_3_ ( + .CE(com_cmm_u_cmm_cfgspace_msi_haddr12), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_cfg_wr_data[27]), + .Q(com_cmm_msi_haddr[3]), + .CLR(com_cmm_rst_267) + ); + FDCE com_cmm_u_cmm_cfgspace_msi_haddr_2_ ( + .CE(com_cmm_u_cmm_cfgspace_msi_haddr12), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_cfg_wr_data[26]), + .Q(com_cmm_msi_haddr[2]), + .CLR(com_cmm_rst_267) + ); + FDCE com_cmm_u_cmm_cfgspace_msi_haddr_1_ ( + .CE(com_cmm_u_cmm_cfgspace_msi_haddr12), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_cfg_wr_data[25]), + .Q(com_cmm_msi_haddr[1]), + .CLR(com_cmm_rst_267) + ); + FDCE com_cmm_u_cmm_cfgspace_msi_haddr_0_ ( + .CE(com_cmm_u_cmm_cfgspace_msi_haddr12), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_cfg_wr_data[24]), + .Q(com_cmm_msi_haddr[0]), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_cfgspace_x_dcmd_1_14_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_cfgspace_N_29864_i), + .Q(NlwRenamedSig_OI_cfg_dcommand[14]), + .CLR(trn_reset_n_i) + ); + FDP com_cmm_u_cmm_cfgspace_x_dcmd_1_13_ ( + .PRE(trn_reset_n_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_cfgspace_N_68560_i_4785), + .Q(NlwRenamedSig_OI_cfg_dcommand[13]) + ); + FDC com_cmm_u_cmm_cfgspace_x_dcmd_1_12_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_cfgspace_N_32900_i), + .Q(NlwRenamedSig_OI_cfg_dcommand[12]), + .CLR(trn_reset_n_i) + ); + FDP com_cmm_u_cmm_cfgspace_x_dcmd_1_11_ ( + .PRE(trn_reset_n_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_cfgspace_N_68513_i_4786), + .Q(NlwRenamedSig_OI_cfg_dcommand[11]) + ); + FDCE com_cmm_u_cmm_cfgspace_x_dcmd_1_10_ ( + .CE(com_cmm_u_cmm_cfgspace_x_dcmd_1_sqmuxa_1), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_cfg_wr_data_18_), + .Q(NlwRenamedSig_OI_cfg_dcommand[10]), + .CLR(trn_reset_n_i) + ); + FDC com_cmm_u_cmm_cfgspace_x_dcmd_1_9_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_cfgspace_N_29862_i), + .Q(NlwRenamedSig_OI_cfg_dcommand[9]), + .CLR(trn_reset_n_i) + ); + FDC com_cmm_u_cmm_cfgspace_x_dcmd_1_8_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_cfgspace_N_29860_i), + .Q(NlwRenamedSig_OI_cfg_dcommand[8]), + .CLR(trn_reset_n_i) + ); + FDC com_cmm_u_cmm_cfgspace_x_dcmd_1_7_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_cfgspace_N_20154_i), + .Q(NlwRenamedSig_OI_cfg_dcommand[7]), + .CLR(trn_reset_n_i) + ); + FDC com_cmm_u_cmm_cfgspace_x_dcmd_1_6_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_cfgspace_N_20152_i), + .Q(NlwRenamedSig_OI_cfg_dcommand[6]), + .CLR(trn_reset_n_i) + ); + FDC com_cmm_u_cmm_cfgspace_x_dcmd_1_5_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_cfgspace_N_20150_i), + .Q(NlwRenamedSig_OI_cfg_dcommand[5]), + .CLR(trn_reset_n_i) + ); + FDCE com_cmm_u_cmm_cfgspace_msi_haddr_19_ ( + .CE(com_cmm_u_cmm_cfgspace_msi_haddr35), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_cfg_wr_data_11_), + .Q(com_cmm_msi_haddr[19]), + .CLR(com_cmm_rst_267) + ); + FDCE com_cmm_u_cmm_cfgspace_msi_haddr_18_ ( + .CE(com_cmm_u_cmm_cfgspace_msi_haddr35), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_cfg_wr_data_10_), + .Q(com_cmm_msi_haddr[18]), + .CLR(com_cmm_rst_267) + ); + FDCE com_cmm_u_cmm_cfgspace_msi_haddr_17_ ( + .CE(com_cmm_u_cmm_cfgspace_msi_haddr35), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_cfg_wr_data_9_), + .Q(com_cmm_msi_haddr[17]), + .CLR(com_cmm_rst_267) + ); + FDCE com_cmm_u_cmm_cfgspace_msi_haddr_16_ ( + .CE(com_cmm_u_cmm_cfgspace_msi_haddr35), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_cfg_wr_data_8_), + .Q(com_cmm_msi_haddr[16]), + .CLR(com_cmm_rst_267) + ); + FDCE com_cmm_u_cmm_cfgspace_msi_haddr_15_ ( + .CE(com_cmm_u_cmm_cfgspace_msi_haddr23), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_cfg_wr_data_23_), + .Q(com_cmm_msi_haddr[15]), + .CLR(com_cmm_rst_267) + ); + FDCE com_cmm_u_cmm_cfgspace_msi_haddr_14_ ( + .CE(com_cmm_u_cmm_cfgspace_msi_haddr23), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_cfg_wr_data_22_), + .Q(com_cmm_msi_haddr[14]), + .CLR(com_cmm_rst_267) + ); + FDCE com_cmm_u_cmm_cfgspace_msi_haddr_13_ ( + .CE(com_cmm_u_cmm_cfgspace_msi_haddr23), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_cfg_wr_data_21_), + .Q(com_cmm_msi_haddr[13]), + .CLR(com_cmm_rst_267) + ); + FDCE com_cmm_u_cmm_cfgspace_msi_haddr_12_ ( + .CE(com_cmm_u_cmm_cfgspace_msi_haddr23), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_cfg_wr_data_20_), + .Q(com_cmm_msi_haddr[12]), + .CLR(com_cmm_rst_267) + ); + FDCE com_cmm_u_cmm_cfgspace_msi_haddr_11_ ( + .CE(com_cmm_u_cmm_cfgspace_msi_haddr23), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_cfg_wr_data_19_), + .Q(com_cmm_msi_haddr[11]), + .CLR(com_cmm_rst_267) + ); + FDCE com_cmm_u_cmm_cfgspace_msi_haddr_10_ ( + .CE(com_cmm_u_cmm_cfgspace_msi_haddr23), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_cfg_wr_data_18_), + .Q(com_cmm_msi_haddr[10]), + .CLR(com_cmm_rst_267) + ); + FDCE com_cmm_u_cmm_cfgspace_msi_haddr_9_ ( + .CE(com_cmm_u_cmm_cfgspace_msi_haddr23), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_cfg_wr_data_17_), + .Q(com_cmm_msi_haddr[9]), + .CLR(com_cmm_rst_267) + ); + FDCE com_cmm_u_cmm_cfgspace_msi_haddr_8_ ( + .CE(com_cmm_u_cmm_cfgspace_msi_haddr23), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_cfg_wr_data_16_), + .Q(com_cmm_msi_haddr[8]), + .CLR(com_cmm_rst_267) + ); + FDCE com_cmm_u_cmm_cfgspace_msi_haddr_7_ ( + .CE(com_cmm_u_cmm_cfgspace_msi_haddr12), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_cfg_wr_data_31_), + .Q(com_cmm_msi_haddr[7]), + .CLR(com_cmm_rst_267) + ); + FDCE com_cmm_u_cmm_cfgspace_msi_haddr_6_ ( + .CE(com_cmm_u_cmm_cfgspace_msi_haddr12), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_cfg_wr_data_30_), + .Q(com_cmm_msi_haddr[6]), + .CLR(com_cmm_rst_267) + ); + FDCE com_cmm_u_cmm_cfgspace_msi_haddr_5_ ( + .CE(com_cmm_u_cmm_cfgspace_msi_haddr12), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_cfg_wr_data_29_), + .Q(com_cmm_msi_haddr[5]), + .CLR(com_cmm_rst_267) + ); + FDCE com_cmm_u_cmm_cfgspace_msi_data_2_ ( + .CE(com_cmm_u_cmm_cfgspace_msi_data12), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_cfg_wr_data[26]), + .Q(com_cmm_msi_data[2]), + .CLR(com_cmm_rst_267) + ); + FDCE com_cmm_u_cmm_cfgspace_msi_data_1_ ( + .CE(com_cmm_u_cmm_cfgspace_msi_data12), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_cfg_wr_data[25]), + .Q(com_cmm_msi_data[1]), + .CLR(com_cmm_rst_267) + ); + FDCE com_cmm_u_cmm_cfgspace_msi_data_0_ ( + .CE(com_cmm_u_cmm_cfgspace_msi_data12), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_cfg_wr_data[24]), + .Q(com_cmm_msi_data[0]), + .CLR(com_cmm_rst_267) + ); + FDCE com_cmm_u_cmm_cfgspace_msi_haddr_31_ ( + .CE(com_cmm_u_cmm_cfgspace_msi_haddr46), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_cfg_wr_data_7_), + .Q(com_cmm_msi_haddr[31]), + .CLR(com_cmm_rst_267) + ); + FDCE com_cmm_u_cmm_cfgspace_msi_haddr_30_ ( + .CE(com_cmm_u_cmm_cfgspace_msi_haddr46), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_cfg_wr_data_6_), + .Q(com_cmm_msi_haddr[30]), + .CLR(com_cmm_rst_267) + ); + FDCE com_cmm_u_cmm_cfgspace_msi_haddr_29_ ( + .CE(com_cmm_u_cmm_cfgspace_msi_haddr46), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_cfg_wr_data_5_), + .Q(com_cmm_msi_haddr[29]), + .CLR(com_cmm_rst_267) + ); + FDCE com_cmm_u_cmm_cfgspace_msi_haddr_28_ ( + .CE(com_cmm_u_cmm_cfgspace_msi_haddr46), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_cfg_wr_data_4_), + .Q(com_cmm_msi_haddr[28]), + .CLR(com_cmm_rst_267) + ); + FDCE com_cmm_u_cmm_cfgspace_msi_haddr_27_ ( + .CE(com_cmm_u_cmm_cfgspace_msi_haddr46), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_cfg_wr_data_3_), + .Q(com_cmm_msi_haddr[27]), + .CLR(com_cmm_rst_267) + ); + FDCE com_cmm_u_cmm_cfgspace_msi_haddr_26_ ( + .CE(com_cmm_u_cmm_cfgspace_msi_haddr46), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_cfg_wr_data_2_), + .Q(com_cmm_msi_haddr[26]), + .CLR(com_cmm_rst_267) + ); + FDCE com_cmm_u_cmm_cfgspace_msi_haddr_25_ ( + .CE(com_cmm_u_cmm_cfgspace_msi_haddr46), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_cfg_wr_data_1_), + .Q(com_cmm_msi_haddr[25]), + .CLR(com_cmm_rst_267) + ); + FDCE com_cmm_u_cmm_cfgspace_msi_haddr_24_ ( + .CE(com_cmm_u_cmm_cfgspace_msi_haddr46), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_cfg_wr_data_0_), + .Q(com_cmm_msi_haddr[24]), + .CLR(com_cmm_rst_267) + ); + FDCE com_cmm_u_cmm_cfgspace_msi_haddr_23_ ( + .CE(com_cmm_u_cmm_cfgspace_msi_haddr35), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_cfg_wr_data_15_), + .Q(com_cmm_msi_haddr[23]), + .CLR(com_cmm_rst_267) + ); + FDCE com_cmm_u_cmm_cfgspace_msi_haddr_22_ ( + .CE(com_cmm_u_cmm_cfgspace_msi_haddr35), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_cfg_wr_data_14_), + .Q(com_cmm_msi_haddr[22]), + .CLR(com_cmm_rst_267) + ); + FDCE com_cmm_u_cmm_cfgspace_msi_haddr_21_ ( + .CE(com_cmm_u_cmm_cfgspace_msi_haddr35), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_cfg_wr_data_13_), + .Q(com_cmm_msi_haddr[21]), + .CLR(com_cmm_rst_267) + ); + FDCE com_cmm_u_cmm_cfgspace_msi_haddr_20_ ( + .CE(com_cmm_u_cmm_cfgspace_msi_haddr35), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_cfg_wr_data_12_), + .Q(com_cmm_msi_haddr[20]), + .CLR(com_cmm_rst_267) + ); + FDCE com_cmm_u_cmm_cfgspace_x_lcmd_1_4_ ( + .CE(com_cmm_u_cmm_cfgspace_x_lcmd22), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_cfg_wr_data[25]), + .Q(NlwRenamedSig_OI_cfg_lcommand_1_), + .CLR(com_cmm_rst_267) + ); + FDCE com_cmm_u_cmm_cfgspace_x_lcmd_1_3_ ( + .CE(com_cmm_u_cmm_cfgspace_x_lcmd22), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_cfg_wr_data[24]), + .Q(NlwRenamedSig_OI_cfg_lcommand_0_), + .CLR(com_cmm_rst_267) + ); + FDCE com_cmm_u_cmm_cfgspace_msi_data_15_ ( + .CE(com_cmm_u_cmm_cfgspace_msi_data22), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_cfg_wr_data_23_), + .Q(com_cmm_msi_data[15]), + .CLR(com_cmm_rst_267) + ); + FDCE com_cmm_u_cmm_cfgspace_msi_data_14_ ( + .CE(com_cmm_u_cmm_cfgspace_msi_data22), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_cfg_wr_data_22_), + .Q(com_cmm_msi_data[14]), + .CLR(com_cmm_rst_267) + ); + FDCE com_cmm_u_cmm_cfgspace_msi_data_13_ ( + .CE(com_cmm_u_cmm_cfgspace_msi_data22), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_cfg_wr_data_21_), + .Q(com_cmm_msi_data[13]), + .CLR(com_cmm_rst_267) + ); + FDCE com_cmm_u_cmm_cfgspace_msi_data_12_ ( + .CE(com_cmm_u_cmm_cfgspace_msi_data22), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_cfg_wr_data_20_), + .Q(com_cmm_msi_data[12]), + .CLR(com_cmm_rst_267) + ); + FDCE com_cmm_u_cmm_cfgspace_msi_data_11_ ( + .CE(com_cmm_u_cmm_cfgspace_msi_data22), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_cfg_wr_data_19_), + .Q(com_cmm_msi_data[11]), + .CLR(com_cmm_rst_267) + ); + FDCE com_cmm_u_cmm_cfgspace_msi_data_10_ ( + .CE(com_cmm_u_cmm_cfgspace_msi_data22), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_cfg_wr_data_18_), + .Q(com_cmm_msi_data[10]), + .CLR(com_cmm_rst_267) + ); + FDCE com_cmm_u_cmm_cfgspace_msi_data_9_ ( + .CE(com_cmm_u_cmm_cfgspace_msi_data22), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_cfg_wr_data_17_), + .Q(com_cmm_msi_data[9]), + .CLR(com_cmm_rst_267) + ); + FDCE com_cmm_u_cmm_cfgspace_msi_data_8_ ( + .CE(com_cmm_u_cmm_cfgspace_msi_data22), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_cfg_wr_data_16_), + .Q(com_cmm_msi_data[8]), + .CLR(com_cmm_rst_267) + ); + FDCE com_cmm_u_cmm_cfgspace_msi_data_7_ ( + .CE(com_cmm_u_cmm_cfgspace_msi_data12), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_cfg_wr_data_31_), + .Q(com_cmm_msi_data[7]), + .CLR(com_cmm_rst_267) + ); + FDCE com_cmm_u_cmm_cfgspace_msi_data_6_ ( + .CE(com_cmm_u_cmm_cfgspace_msi_data12), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_cfg_wr_data_30_), + .Q(com_cmm_msi_data[6]), + .CLR(com_cmm_rst_267) + ); + FDCE com_cmm_u_cmm_cfgspace_msi_data_5_ ( + .CE(com_cmm_u_cmm_cfgspace_msi_data12), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_cfg_wr_data_29_), + .Q(com_cmm_msi_data[5]), + .CLR(com_cmm_rst_267) + ); + FDCE com_cmm_u_cmm_cfgspace_msi_data_4_ ( + .CE(com_cmm_u_cmm_cfgspace_msi_data12), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_cfg_wr_data_28_), + .Q(com_cmm_msi_data[4]), + .CLR(com_cmm_rst_267) + ); + FDCE com_cmm_u_cmm_cfgspace_msi_data_3_ ( + .CE(com_cmm_u_cmm_cfgspace_msi_data12), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_cfg_wr_data[27]), + .Q(com_cmm_msi_data[3]), + .CLR(com_cmm_rst_267) + ); + FDCE com_cmm_u_cmm_cfgspace_bar0_reg_5_ ( + .CE(com_cmm_u_cmm_cfgspace_bar0_reg18), + .C(NlwRenamedSig_OI_trn_clk), + .D(I_4895_0_a2_0_a2_0_a2_0_a2_91), + .Q(com_cmm_bar0_reg_5_), + .CLR(com_cmm_rst_267) + ); + FDCE com_cmm_u_cmm_cfgspace_bar0_reg_4_ ( + .CE(com_cmm_u_cmm_cfgspace_bar0_reg18), + .C(NlwRenamedSig_OI_trn_clk), + .D(I_4900_0_a2_0_a2_0_a2_0_a2_90), + .Q(com_cmm_bar0_reg_4_), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_cfgspace_bar0_reg_3_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(cfg_cfg_5072[67]), + .Q(com_cmm_u_cmm_cfgspace_bar0_reg[3]), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_cfgspace_bar0_reg_2_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(cfg_cfg_5072[66]), + .Q(com_cmm_bar0_reg_2_), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_cfgspace_bar0_reg_1_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(cfg_cfg_5072[65]), + .Q(com_cmm_bar0_reg_1_), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_cfgspace_bar0_reg_0_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(cfg_cfg_5072[64]), + .Q(com_cmm_bar0_reg_0_), + .CLR(com_cmm_rst_267) + ); + FDCE com_cmm_u_cmm_cfgspace_command_1_10_ ( + .CE(com_cmm_u_cmm_cfgspace_command93), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_cfg_wr_data_18_), + .Q(NlwRenamedSig_OI_cfg_command_10_), + .CLR(com_cmm_rst_267) + ); + FDCE com_cmm_u_cmm_cfgspace_command_1_9_ ( + .CE(com_cmm_u_cmm_cfgspace_command93), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_cfg_wr_data_16_), + .Q(NlwRenamedSig_OI_cfg_command_8_), + .CLR(com_cmm_rst_267) + ); + FDCE com_cmm_u_cmm_cfgspace_command_1_8_ ( + .CE(com_cmm_u_cmm_cfgspace_command67), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_cfg_wr_data_30_), + .Q(NlwRenamedSig_OI_cfg_command_6_), + .CLR(com_cmm_rst_267) + ); + FDCE com_cmm_u_cmm_cfgspace_command_1_7_ ( + .CE(com_cmm_u_cmm_cfgspace_command67), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_cfg_wr_data[26]), + .Q(NlwRenamedSig_OI_cfg_command_2_), + .CLR(com_cmm_rst_267) + ); + FDCE com_cmm_u_cmm_cfgspace_command_1_6_ ( + .CE(com_cmm_u_cmm_cfgspace_command67), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_cfg_wr_data[25]), + .Q(NlwRenamedSig_OI_cfg_command_1_), + .CLR(com_cmm_rst_267) + ); + FDCE com_cmm_u_cmm_cfgspace_command_1_5_ ( + .CE(com_cmm_u_cmm_cfgspace_command67), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_cfg_wr_data[24]), + .Q(NlwRenamedSig_OI_cfg_command_0_), + .CLR(com_cmm_rst_267) + ); + FDCE com_cmm_u_cmm_cfgspace_x_lcmd_1_7_ ( + .CE(com_cmm_u_cmm_cfgspace_x_lcmd22), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_cfg_wr_data_31_), + .Q(NlwRenamedSig_OI_cfg_lcommand_7_), + .CLR(com_cmm_rst_267) + ); + FDCE com_cmm_u_cmm_cfgspace_x_lcmd_1_6_ ( + .CE(com_cmm_u_cmm_cfgspace_x_lcmd22), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_cfg_wr_data_30_), + .Q(NlwRenamedSig_OI_cfg_lcommand_6_), + .CLR(com_cmm_rst_267) + ); + FDCE com_cmm_u_cmm_cfgspace_x_lcmd_1_5_ ( + .CE(com_cmm_u_cmm_cfgspace_x_lcmd22), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_cfg_wr_data[27]), + .Q(NlwRenamedSig_OI_cfg_lcommand_3_), + .CLR(com_cmm_rst_267) + ); + FDCE com_cmm_u_cmm_cfgspace_bar0_reg_20_ ( + .CE(com_cmm_u_cmm_cfgspace_bar0_reg44), + .C(NlwRenamedSig_OI_trn_clk), + .D(I_4905_0_a2_0_a2_0_a2_0_a2_89), + .Q(com_cmm_bar0_reg_20_), + .CLR(com_cmm_rst_267) + ); + FDCE com_cmm_u_cmm_cfgspace_bar0_reg_19_ ( + .CE(com_cmm_u_cmm_cfgspace_bar0_reg44), + .C(NlwRenamedSig_OI_trn_clk), + .D(I_4910_0_a2_0_a2_0_a2_88), + .Q(com_cmm_bar0_reg_19_), + .CLR(com_cmm_rst_267) + ); + FDCE com_cmm_u_cmm_cfgspace_bar0_reg_18_ ( + .CE(com_cmm_u_cmm_cfgspace_bar0_reg44), + .C(NlwRenamedSig_OI_trn_clk), + .D(I_4915_0_a2_0_a2_0_a2_0_a2_87), + .Q(com_cmm_bar0_reg_18_), + .CLR(com_cmm_rst_267) + ); + FDCE com_cmm_u_cmm_cfgspace_bar0_reg_17_ ( + .CE(com_cmm_u_cmm_cfgspace_bar0_reg44), + .C(NlwRenamedSig_OI_trn_clk), + .D(I_4920_0_a2_0_a2_0_a2_86), + .Q(com_cmm_bar0_reg_17_), + .CLR(com_cmm_rst_267) + ); + FDCE com_cmm_u_cmm_cfgspace_bar0_reg_16_ ( + .CE(com_cmm_u_cmm_cfgspace_bar0_reg44), + .C(NlwRenamedSig_OI_trn_clk), + .D(I_4925_0_a2_0_a2_0_a2_85), + .Q(com_cmm_bar0_reg_16_), + .CLR(com_cmm_rst_267) + ); + FDCE com_cmm_u_cmm_cfgspace_bar0_reg_15_ ( + .CE(com_cmm_u_cmm_cfgspace_bar0_reg31), + .C(NlwRenamedSig_OI_trn_clk), + .D(I_4930_0_a2_0_a2_0_a2_84), + .Q(com_cmm_bar0_reg_15_), + .CLR(com_cmm_rst_267) + ); + FDCE com_cmm_u_cmm_cfgspace_bar0_reg_14_ ( + .CE(com_cmm_u_cmm_cfgspace_bar0_reg31), + .C(NlwRenamedSig_OI_trn_clk), + .D(I_4935_0_a2_0_a2_0_a2_83), + .Q(com_cmm_bar0_reg_14_), + .CLR(com_cmm_rst_267) + ); + FDCE com_cmm_u_cmm_cfgspace_bar0_reg_13_ ( + .CE(com_cmm_u_cmm_cfgspace_bar0_reg31), + .C(NlwRenamedSig_OI_trn_clk), + .D(I_4940_0_a2_0_a2_82), + .Q(com_cmm_bar0_reg_13_), + .CLR(com_cmm_rst_267) + ); + FDCE com_cmm_u_cmm_cfgspace_bar0_reg_12_ ( + .CE(com_cmm_u_cmm_cfgspace_bar0_reg31), + .C(NlwRenamedSig_OI_trn_clk), + .D(I_4945_0_a2_0_a2_0_a2_0_a2_81), + .Q(com_cmm_bar0_reg_12_), + .CLR(com_cmm_rst_267) + ); + FDCE com_cmm_u_cmm_cfgspace_bar0_reg_11_ ( + .CE(com_cmm_u_cmm_cfgspace_bar0_reg31), + .C(NlwRenamedSig_OI_trn_clk), + .D(I_4950_0_a2_0_a2_0_a2_80), + .Q(com_cmm_bar0_reg_11_), + .CLR(com_cmm_rst_267) + ); + FDCE com_cmm_u_cmm_cfgspace_bar0_reg_10_ ( + .CE(com_cmm_u_cmm_cfgspace_bar0_reg31), + .C(NlwRenamedSig_OI_trn_clk), + .D(I_4955_0_a2_0_a2_0_a2_79), + .Q(com_cmm_bar0_reg_10_), + .CLR(com_cmm_rst_267) + ); + FDCE com_cmm_u_cmm_cfgspace_bar0_reg_9_ ( + .CE(com_cmm_u_cmm_cfgspace_bar0_reg31), + .C(NlwRenamedSig_OI_trn_clk), + .D(I_4960_0_a2_0_a2_0_a2_78), + .Q(com_cmm_bar0_reg_9_), + .CLR(com_cmm_rst_267) + ); + FDCE com_cmm_u_cmm_cfgspace_bar0_reg_8_ ( + .CE(com_cmm_u_cmm_cfgspace_bar0_reg31), + .C(NlwRenamedSig_OI_trn_clk), + .D(I_4965_0_a2_0_a2_0_a2_77), + .Q(com_cmm_bar0_reg_8_), + .CLR(com_cmm_rst_267) + ); + FDCE com_cmm_u_cmm_cfgspace_bar0_reg_7_ ( + .CE(com_cmm_u_cmm_cfgspace_bar0_reg18), + .C(NlwRenamedSig_OI_trn_clk), + .D(I_4970_0_a2_0_a2_0_a2_0_a2_76), + .Q(com_cmm_bar0_reg_7_), + .CLR(com_cmm_rst_267) + ); + FDCE com_cmm_u_cmm_cfgspace_bar0_reg_6_ ( + .CE(com_cmm_u_cmm_cfgspace_bar0_reg18), + .C(NlwRenamedSig_OI_trn_clk), + .D(I_4975_0_a2_0_a2_0_a2_0_a2_75), + .Q(com_cmm_bar0_reg_6_), + .CLR(com_cmm_rst_267) + ); + FDCE com_cmm_u_cmm_cfgspace_msi_laddr_1_5_ ( + .CE(com_cmm_u_cmm_cfgspace_msi_laddr16), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_cfg_wr_data_29_), + .Q(com_cmm_msi_laddr[5]), + .CLR(com_cmm_rst_267) + ); + FDCE com_cmm_u_cmm_cfgspace_msi_laddr_1_4_ ( + .CE(com_cmm_u_cmm_cfgspace_msi_laddr16), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_cfg_wr_data_28_), + .Q(com_cmm_msi_laddr[4]), + .CLR(com_cmm_rst_267) + ); + FDCE com_cmm_u_cmm_cfgspace_msi_laddr_1_3_ ( + .CE(com_cmm_u_cmm_cfgspace_msi_laddr16), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_cfg_wr_data[27]), + .Q(com_cmm_msi_laddr[3]), + .CLR(com_cmm_rst_267) + ); + FDCE com_cmm_u_cmm_cfgspace_msi_laddr_1_2_ ( + .CE(com_cmm_u_cmm_cfgspace_msi_laddr16), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_cfg_wr_data[26]), + .Q(com_cmm_msi_laddr[2]), + .CLR(com_cmm_rst_267) + ); + FDCE com_cmm_u_cmm_cfgspace_bar0_reg_31_ ( + .CE(com_cmm_u_cmm_cfgspace_bar0_reg56), + .C(NlwRenamedSig_OI_trn_clk), + .D(I_4980_0_a2_0_a2_0_a2_74), + .Q(com_cmm_bar0_reg_31_), + .CLR(com_cmm_rst_267) + ); + FDCE com_cmm_u_cmm_cfgspace_bar0_reg_30_ ( + .CE(com_cmm_u_cmm_cfgspace_bar0_reg56), + .C(NlwRenamedSig_OI_trn_clk), + .D(I_4985_0_a2_0_a2_0_a2_73), + .Q(com_cmm_bar0_reg_30_), + .CLR(com_cmm_rst_267) + ); + FDCE com_cmm_u_cmm_cfgspace_bar0_reg_29_ ( + .CE(com_cmm_u_cmm_cfgspace_bar0_reg56), + .C(NlwRenamedSig_OI_trn_clk), + .D(I_4990_0_a2_0_a2_0_a2_72), + .Q(com_cmm_bar0_reg_29_), + .CLR(com_cmm_rst_267) + ); + FDCE com_cmm_u_cmm_cfgspace_bar0_reg_28_ ( + .CE(com_cmm_u_cmm_cfgspace_bar0_reg56), + .C(NlwRenamedSig_OI_trn_clk), + .D(I_4995_0_a2_0_a2_0_a2_71), + .Q(com_cmm_bar0_reg_28_), + .CLR(com_cmm_rst_267) + ); + FDCE com_cmm_u_cmm_cfgspace_bar0_reg_27_ ( + .CE(com_cmm_u_cmm_cfgspace_bar0_reg56), + .C(NlwRenamedSig_OI_trn_clk), + .D(I_5000_0_a2_0_a2_0_a2_70), + .Q(com_cmm_bar0_reg_27_), + .CLR(com_cmm_rst_267) + ); + FDCE com_cmm_u_cmm_cfgspace_bar0_reg_26_ ( + .CE(com_cmm_u_cmm_cfgspace_bar0_reg56), + .C(NlwRenamedSig_OI_trn_clk), + .D(I_5005_0_a2_0_a2_69), + .Q(com_cmm_bar0_reg_26_), + .CLR(com_cmm_rst_267) + ); + FDCE com_cmm_u_cmm_cfgspace_bar0_reg_25_ ( + .CE(com_cmm_u_cmm_cfgspace_bar0_reg56), + .C(NlwRenamedSig_OI_trn_clk), + .D(I_5010_0_a2_0_a2_68), + .Q(com_cmm_bar0_reg_25_), + .CLR(com_cmm_rst_267) + ); + FDCE com_cmm_u_cmm_cfgspace_bar0_reg_24_ ( + .CE(com_cmm_u_cmm_cfgspace_bar0_reg56), + .C(NlwRenamedSig_OI_trn_clk), + .D(I_5015_0_a2_0_a2_67), + .Q(com_cmm_bar0_reg_24_), + .CLR(com_cmm_rst_267) + ); + FDCE com_cmm_u_cmm_cfgspace_bar0_reg_23_ ( + .CE(com_cmm_u_cmm_cfgspace_bar0_reg44), + .C(NlwRenamedSig_OI_trn_clk), + .D(I_5020_0_a2_0_a2_66), + .Q(com_cmm_bar0_reg_23_), + .CLR(com_cmm_rst_267) + ); + FDCE com_cmm_u_cmm_cfgspace_bar0_reg_22_ ( + .CE(com_cmm_u_cmm_cfgspace_bar0_reg44), + .C(NlwRenamedSig_OI_trn_clk), + .D(I_5025_0_a2_0_a2_0_a2_65), + .Q(com_cmm_bar0_reg_22_), + .CLR(com_cmm_rst_267) + ); + FDCE com_cmm_u_cmm_cfgspace_bar0_reg_21_ ( + .CE(com_cmm_u_cmm_cfgspace_bar0_reg44), + .C(NlwRenamedSig_OI_trn_clk), + .D(I_5030_0_a2_0_a2_0_a2_64), + .Q(com_cmm_bar0_reg_21_), + .CLR(com_cmm_rst_267) + ); + FDCE com_cmm_u_cmm_cfgspace_msi_laddr_1_20_ ( + .CE(com_cmm_u_cmm_cfgspace_msi_laddr40), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_cfg_wr_data_12_), + .Q(com_cmm_msi_laddr[20]), + .CLR(com_cmm_rst_267) + ); + FDCE com_cmm_u_cmm_cfgspace_msi_laddr_1_19_ ( + .CE(com_cmm_u_cmm_cfgspace_msi_laddr40), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_cfg_wr_data_11_), + .Q(com_cmm_msi_laddr[19]), + .CLR(com_cmm_rst_267) + ); + FDCE com_cmm_u_cmm_cfgspace_msi_laddr_1_18_ ( + .CE(com_cmm_u_cmm_cfgspace_msi_laddr40), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_cfg_wr_data_10_), + .Q(com_cmm_msi_laddr[18]), + .CLR(com_cmm_rst_267) + ); + FDCE com_cmm_u_cmm_cfgspace_msi_laddr_1_17_ ( + .CE(com_cmm_u_cmm_cfgspace_msi_laddr40), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_cfg_wr_data_9_), + .Q(com_cmm_msi_laddr[17]), + .CLR(com_cmm_rst_267) + ); + FDCE com_cmm_u_cmm_cfgspace_msi_laddr_1_16_ ( + .CE(com_cmm_u_cmm_cfgspace_msi_laddr40), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_cfg_wr_data_8_), + .Q(com_cmm_msi_laddr[16]), + .CLR(com_cmm_rst_267) + ); + FDCE com_cmm_u_cmm_cfgspace_msi_laddr_1_15_ ( + .CE(com_cmm_u_cmm_cfgspace_msi_laddr28), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_cfg_wr_data_23_), + .Q(com_cmm_msi_laddr[15]), + .CLR(com_cmm_rst_267) + ); + FDCE com_cmm_u_cmm_cfgspace_msi_laddr_1_14_ ( + .CE(com_cmm_u_cmm_cfgspace_msi_laddr28), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_cfg_wr_data_22_), + .Q(com_cmm_msi_laddr[14]), + .CLR(com_cmm_rst_267) + ); + FDCE com_cmm_u_cmm_cfgspace_msi_laddr_1_13_ ( + .CE(com_cmm_u_cmm_cfgspace_msi_laddr28), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_cfg_wr_data_21_), + .Q(com_cmm_msi_laddr[13]), + .CLR(com_cmm_rst_267) + ); + FDCE com_cmm_u_cmm_cfgspace_msi_laddr_1_12_ ( + .CE(com_cmm_u_cmm_cfgspace_msi_laddr28), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_cfg_wr_data_20_), + .Q(com_cmm_msi_laddr[12]), + .CLR(com_cmm_rst_267) + ); + FDCE com_cmm_u_cmm_cfgspace_msi_laddr_1_11_ ( + .CE(com_cmm_u_cmm_cfgspace_msi_laddr28), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_cfg_wr_data_19_), + .Q(com_cmm_msi_laddr[11]), + .CLR(com_cmm_rst_267) + ); + FDCE com_cmm_u_cmm_cfgspace_msi_laddr_1_10_ ( + .CE(com_cmm_u_cmm_cfgspace_msi_laddr28), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_cfg_wr_data_18_), + .Q(com_cmm_msi_laddr[10]), + .CLR(com_cmm_rst_267) + ); + FDCE com_cmm_u_cmm_cfgspace_msi_laddr_1_9_ ( + .CE(com_cmm_u_cmm_cfgspace_msi_laddr28), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_cfg_wr_data_17_), + .Q(com_cmm_msi_laddr[9]), + .CLR(com_cmm_rst_267) + ); + FDCE com_cmm_u_cmm_cfgspace_msi_laddr_1_8_ ( + .CE(com_cmm_u_cmm_cfgspace_msi_laddr28), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_cfg_wr_data_16_), + .Q(com_cmm_msi_laddr[8]), + .CLR(com_cmm_rst_267) + ); + FDCE com_cmm_u_cmm_cfgspace_msi_laddr_1_7_ ( + .CE(com_cmm_u_cmm_cfgspace_msi_laddr16), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_cfg_wr_data_31_), + .Q(com_cmm_msi_laddr[7]), + .CLR(com_cmm_rst_267) + ); + FDCE com_cmm_u_cmm_cfgspace_msi_laddr_1_6_ ( + .CE(com_cmm_u_cmm_cfgspace_msi_laddr16), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_cfg_wr_data_30_), + .Q(com_cmm_msi_laddr[6]), + .CLR(com_cmm_rst_267) + ); + FDCE com_cmm_u_cmm_cfgspace_msi_laddr_1_31_ ( + .CE(com_cmm_u_cmm_cfgspace_msi_laddr51), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_cfg_wr_data_7_), + .Q(com_cmm_msi_laddr[31]), + .CLR(com_cmm_rst_267) + ); + FDCE com_cmm_u_cmm_cfgspace_msi_laddr_1_30_ ( + .CE(com_cmm_u_cmm_cfgspace_msi_laddr51), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_cfg_wr_data_6_), + .Q(com_cmm_msi_laddr[30]), + .CLR(com_cmm_rst_267) + ); + FDCE com_cmm_u_cmm_cfgspace_msi_laddr_1_29_ ( + .CE(com_cmm_u_cmm_cfgspace_msi_laddr51), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_cfg_wr_data_5_), + .Q(com_cmm_msi_laddr[29]), + .CLR(com_cmm_rst_267) + ); + FDCE com_cmm_u_cmm_cfgspace_msi_laddr_1_28_ ( + .CE(com_cmm_u_cmm_cfgspace_msi_laddr51), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_cfg_wr_data_4_), + .Q(com_cmm_msi_laddr[28]), + .CLR(com_cmm_rst_267) + ); + FDCE com_cmm_u_cmm_cfgspace_msi_laddr_1_27_ ( + .CE(com_cmm_u_cmm_cfgspace_msi_laddr51), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_cfg_wr_data_3_), + .Q(com_cmm_msi_laddr[27]), + .CLR(com_cmm_rst_267) + ); + FDCE com_cmm_u_cmm_cfgspace_msi_laddr_1_26_ ( + .CE(com_cmm_u_cmm_cfgspace_msi_laddr51), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_cfg_wr_data_2_), + .Q(com_cmm_msi_laddr[26]), + .CLR(com_cmm_rst_267) + ); + FDCE com_cmm_u_cmm_cfgspace_msi_laddr_1_25_ ( + .CE(com_cmm_u_cmm_cfgspace_msi_laddr51), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_cfg_wr_data_1_), + .Q(com_cmm_msi_laddr[25]), + .CLR(com_cmm_rst_267) + ); + FDCE com_cmm_u_cmm_cfgspace_msi_laddr_1_24_ ( + .CE(com_cmm_u_cmm_cfgspace_msi_laddr51), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_cfg_wr_data_0_), + .Q(com_cmm_msi_laddr[24]), + .CLR(com_cmm_rst_267) + ); + FDCE com_cmm_u_cmm_cfgspace_msi_laddr_1_23_ ( + .CE(com_cmm_u_cmm_cfgspace_msi_laddr40), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_cfg_wr_data_15_), + .Q(com_cmm_msi_laddr[23]), + .CLR(com_cmm_rst_267) + ); + FDCE com_cmm_u_cmm_cfgspace_msi_laddr_1_22_ ( + .CE(com_cmm_u_cmm_cfgspace_msi_laddr40), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_cfg_wr_data_14_), + .Q(com_cmm_msi_laddr[22]), + .CLR(com_cmm_rst_267) + ); + FDCE com_cmm_u_cmm_cfgspace_msi_laddr_1_21_ ( + .CE(com_cmm_u_cmm_cfgspace_msi_laddr40), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_cfg_wr_data_13_), + .Q(com_cmm_msi_laddr[21]), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_cfgspace_x_dcap_8_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(cfg_cfg_5072[376]), + .Q(com_cmm_u_cmm_cfgspace_x_dcap[8]), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_cfgspace_x_dcap_7_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(cfg_cfg_5072[375]), + .Q(com_cmm_u_cmm_cfgspace_x_dcap[7]), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_cfgspace_x_dcap_6_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(cfg_cfg_5072[374]), + .Q(com_cmm_u_cmm_cfgspace_x_dcap[6]), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_cfgspace_x_dcap_5_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(cfg_cfg_5072[373]), + .Q(com_cmm_u_cmm_cfgspace_x_dcap[5]), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_cfgspace_x_dcap_4_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(cfg_cfg_5072[372]), + .Q(com_cmm_u_cmm_cfgspace_x_dcap[4]), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_cfgspace_x_dcap_3_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(cfg_cfg_5072[371]), + .Q(com_cmm_u_cmm_cfgspace_x_dcap[3]), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_cfgspace_x_dcap_2_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(cfg_cfg_5072[370]), + .Q(com_cmm_u_cmm_cfgspace_x_dcap[2]), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_cfgspace_x_dcap_1_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(cfg_cfg_5072[369]), + .Q(com_cmm_u_cmm_cfgspace_x_dcap[1]), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_cfgspace_x_dcap_0_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(cfg_cfg_5072[368]), + .Q(com_cmm_u_cmm_cfgspace_x_dcap[0]), + .CLR(com_cmm_rst_267) + ); + FDCE com_cmm_u_cmm_cfgspace_x_dcap_23_ ( + .CE(com_cmmt_rpm_set_slot_pwr), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmmt_rpm_set_slot_pwr_data[5]), + .Q(com_cmm_u_cmm_cfgspace_x_dcap[23]), + .CLR(com_cmm_rst_267) + ); + FDCE com_cmm_u_cmm_cfgspace_x_dcap_22_ ( + .CE(com_cmmt_rpm_set_slot_pwr), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmmt_rpm_set_slot_pwr_data[4]), + .Q(com_cmm_u_cmm_cfgspace_x_dcap[22]), + .CLR(com_cmm_rst_267) + ); + FDCE com_cmm_u_cmm_cfgspace_x_dcap_21_ ( + .CE(com_cmmt_rpm_set_slot_pwr), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmmt_rpm_set_slot_pwr_data[3]), + .Q(com_cmm_u_cmm_cfgspace_x_dcap[21]), + .CLR(com_cmm_rst_267) + ); + FDCE com_cmm_u_cmm_cfgspace_x_dcap_20_ ( + .CE(com_cmmt_rpm_set_slot_pwr), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmmt_rpm_set_slot_pwr_data[2]), + .Q(com_cmm_u_cmm_cfgspace_x_dcap[20]), + .CLR(com_cmm_rst_267) + ); + FDCE com_cmm_u_cmm_cfgspace_x_dcap_19_ ( + .CE(com_cmmt_rpm_set_slot_pwr), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmmt_rpm_set_slot_pwr_data[1]), + .Q(com_cmm_u_cmm_cfgspace_x_dcap[19]), + .CLR(com_cmm_rst_267) + ); + FDCE com_cmm_u_cmm_cfgspace_x_dcap_18_ ( + .CE(com_cmmt_rpm_set_slot_pwr), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmmt_rpm_set_slot_pwr_data[0]), + .Q(com_cmm_u_cmm_cfgspace_x_dcap[18]), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_cfgspace_x_dcap_17_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(cfg_cfg_5072[385]), + .Q(com_cmm_u_cmm_cfgspace_x_dcap[17]), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_cfgspace_x_dcap_16_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(cfg_cfg_5072[384]), + .Q(com_cmm_u_cmm_cfgspace_x_dcap[16]), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_cfgspace_x_dcap_15_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(cfg_cfg_5072[383]), + .Q(com_cmm_u_cmm_cfgspace_x_dcap[15]), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_cfgspace_x_dcap_14_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(cfg_cfg_5072[382]), + .Q(com_cmm_u_cmm_cfgspace_x_dcap[14]), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_cfgspace_x_dcap_13_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(cfg_cfg_5072[381]), + .Q(com_cmm_u_cmm_cfgspace_x_dcap[13]), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_cfgspace_x_dcap_12_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(cfg_cfg_5072[380]), + .Q(com_cmm_u_cmm_cfgspace_x_dcap[12]), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_cfgspace_x_dcap_11_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(cfg_cfg_5072[379]), + .Q(com_cmm_u_cmm_cfgspace_x_dcap[11]), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_cfgspace_x_dcap_10_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(cfg_cfg_5072[378]), + .Q(com_cmm_u_cmm_cfgspace_x_dcap[10]), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_cfgspace_x_dcap_9_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(cfg_cfg_5072[377]), + .Q(com_cmm_u_cmm_cfgspace_x_dcap[9]), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_cfgspace_x_dcap_31_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(cfg_cfg_5072[399]), + .Q(com_cmm_u_cmm_cfgspace_x_dcap[31]), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_cfgspace_x_dcap_30_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(cfg_cfg_5072[398]), + .Q(com_cmm_u_cmm_cfgspace_x_dcap[30]), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_cfgspace_x_dcap_29_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(cfg_cfg_5072[397]), + .Q(com_cmm_u_cmm_cfgspace_x_dcap[29]), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_cfgspace_x_dcap_28_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(cfg_cfg_5072[396]), + .Q(com_cmm_u_cmm_cfgspace_x_dcap[28]), + .CLR(com_cmm_rst_267) + ); + FDCE com_cmm_u_cmm_cfgspace_x_dcap_27_ ( + .CE(com_cmmt_rpm_set_slot_pwr), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmmt_rpm_set_slot_pwr_data[9]), + .Q(com_cmm_u_cmm_cfgspace_x_dcap[27]), + .CLR(com_cmm_rst_267) + ); + FDCE com_cmm_u_cmm_cfgspace_x_dcap_26_ ( + .CE(com_cmmt_rpm_set_slot_pwr), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmmt_rpm_set_slot_pwr_data[8]), + .Q(com_cmm_u_cmm_cfgspace_x_dcap[26]), + .CLR(com_cmm_rst_267) + ); + FDCE com_cmm_u_cmm_cfgspace_x_dcap_25_ ( + .CE(com_cmmt_rpm_set_slot_pwr), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmmt_rpm_set_slot_pwr_data[7]), + .Q(com_cmm_u_cmm_cfgspace_x_dcap[25]), + .CLR(com_cmm_rst_267) + ); + FDCE com_cmm_u_cmm_cfgspace_x_dcap_24_ ( + .CE(com_cmmt_rpm_set_slot_pwr), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmmt_rpm_set_slot_pwr_data[6]), + .Q(com_cmm_u_cmm_cfgspace_x_dcap[24]), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_cfgspace_x_lsts_1_12_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(cfg_cfg_5072[504]), + .Q(NlwRenamedSig_OI_cfg_lstatus_12_), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_cfgspace_x_lsts_1_2_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_cfgspace_x_lcap[0]), + .Q(NlwRenamedSig_OI_cfg_lstatus_4_), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_cfgspace_set_l1exit_lat_2_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_cfgspace_VCC_4787), + .Q(com_cmm_u_cmm_cfgspace_x_lcap[0]), + .CLR(com_cmm_rst_267) + ); + FDCE com_cmm_u_cmm_cfgspace_cache_line_7_ ( + .CE(com_cmm_u_cmm_cfgspace_cache_line8), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_tlm2cfg_wrdata_7_), + .Q(com_cmm_u_cmm_cfgspace_cache_line[7]), + .CLR(com_cmm_rst_267) + ); + FDCE com_cmm_u_cmm_cfgspace_cache_line_6_ ( + .CE(com_cmm_u_cmm_cfgspace_cache_line8), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_tlm2cfg_wrdata_6_), + .Q(com_cmm_u_cmm_cfgspace_cache_line[6]), + .CLR(com_cmm_rst_267) + ); + FDCE com_cmm_u_cmm_cfgspace_cache_line_5_ ( + .CE(com_cmm_u_cmm_cfgspace_cache_line8), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_tlm2cfg_wrdata_5_), + .Q(com_cmm_u_cmm_cfgspace_cache_line[5]), + .CLR(com_cmm_rst_267) + ); + FDCE com_cmm_u_cmm_cfgspace_cache_line_4_ ( + .CE(com_cmm_u_cmm_cfgspace_cache_line8), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_tlm2cfg_wrdata_4_), + .Q(com_cmm_u_cmm_cfgspace_cache_line[4]), + .CLR(com_cmm_rst_267) + ); + FDCE com_cmm_u_cmm_cfgspace_cache_line_3_ ( + .CE(com_cmm_u_cmm_cfgspace_cache_line8), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_tlm2cfg_wrdata_3_), + .Q(com_cmm_u_cmm_cfgspace_cache_line[3]), + .CLR(com_cmm_rst_267) + ); + FDCE com_cmm_u_cmm_cfgspace_cache_line_2_ ( + .CE(com_cmm_u_cmm_cfgspace_cache_line8), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_tlm2cfg_wrdata_2_), + .Q(com_cmm_u_cmm_cfgspace_cache_line[2]), + .CLR(com_cmm_rst_267) + ); + FDCE com_cmm_u_cmm_cfgspace_cache_line_1_ ( + .CE(com_cmm_u_cmm_cfgspace_cache_line8), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_tlm2cfg_wrdata_1_), + .Q(com_cmm_u_cmm_cfgspace_cache_line[1]), + .CLR(com_cmm_rst_267) + ); + FDCE com_cmm_u_cmm_cfgspace_cache_line_0_ ( + .CE(com_cmm_u_cmm_cfgspace_cache_line8), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_tlm2cfg_wrdata_0_), + .Q(com_cmm_u_cmm_cfgspace_cache_line[0]), + .CLR(com_cmm_rst_267) + ); + FDPE com_cmm_u_cmm_cfgspace_int_line_7_ ( + .PRE(com_cmm_rst_267), + .CE(com_cmm_u_cmm_cfgspace_int_line8), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_tlm2cfg_wrdata_7_), + .Q(com_cmm_u_cmm_cfgspace_int_line[7]) + ); + FDPE com_cmm_u_cmm_cfgspace_int_line_6_ ( + .PRE(com_cmm_rst_267), + .CE(com_cmm_u_cmm_cfgspace_int_line8), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_tlm2cfg_wrdata_6_), + .Q(com_cmm_u_cmm_cfgspace_int_line[6]) + ); + FDPE com_cmm_u_cmm_cfgspace_int_line_5_ ( + .PRE(com_cmm_rst_267), + .CE(com_cmm_u_cmm_cfgspace_int_line8), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_tlm2cfg_wrdata_5_), + .Q(com_cmm_u_cmm_cfgspace_int_line[5]) + ); + FDPE com_cmm_u_cmm_cfgspace_int_line_4_ ( + .PRE(com_cmm_rst_267), + .CE(com_cmm_u_cmm_cfgspace_int_line8), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_tlm2cfg_wrdata_4_), + .Q(com_cmm_u_cmm_cfgspace_int_line[4]) + ); + FDPE com_cmm_u_cmm_cfgspace_int_line_3_ ( + .PRE(com_cmm_rst_267), + .CE(com_cmm_u_cmm_cfgspace_int_line8), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_tlm2cfg_wrdata_3_), + .Q(com_cmm_u_cmm_cfgspace_int_line[3]) + ); + FDPE com_cmm_u_cmm_cfgspace_int_line_2_ ( + .PRE(com_cmm_rst_267), + .CE(com_cmm_u_cmm_cfgspace_int_line8), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_tlm2cfg_wrdata_2_), + .Q(com_cmm_u_cmm_cfgspace_int_line[2]) + ); + FDPE com_cmm_u_cmm_cfgspace_int_line_1_ ( + .PRE(com_cmm_rst_267), + .CE(com_cmm_u_cmm_cfgspace_int_line8), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_tlm2cfg_wrdata_1_), + .Q(com_cmm_u_cmm_cfgspace_int_line[1]) + ); + FDPE com_cmm_u_cmm_cfgspace_int_line_0_ ( + .PRE(com_cmm_rst_267), + .CE(com_cmm_u_cmm_cfgspace_int_line8), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_tlm2cfg_wrdata_0_), + .Q(com_cmm_u_cmm_cfgspace_int_line[0]) + ); + FDCE com_cmm_u_cmm_cfgspace_msi_control_1_0_ ( + .CE(com_cmm_u_cmm_cfgspace_msi_control27), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_tlm2cfg_wrdata_16_), + .Q(com_cmm_msi_control_1[0]), + .CLR(com_cmm_rst_267) + ); + FDCE com_cmm_u_cmm_cfgspace_xrom_reg_1_0_ ( + .CE(com_cmm_u_cmm_cfgspace_xrom_reg_0_sqmuxa), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_tlm2cfg_wrdata_0_), + .Q(com_cmm_xrom_reg_0_), + .CLR(com_cmm_rst_267) + ); + FDCE com_cmm_u_cmm_cfgspace_xrom_reg_1_31_ ( + .CE(cfg_cfg_5072[320]), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_cfgspace_N_68355_i), + .Q(com_cmm_xrom_reg_31_), + .CLR(com_cmm_rst_267) + ); + FDCE com_cmm_u_cmm_cfgspace_xrom_reg_1_30_ ( + .CE(cfg_cfg_5072[320]), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_cfgspace_N_68335_i), + .Q(com_cmm_xrom_reg_30_), + .CLR(com_cmm_rst_267) + ); + FDCE com_cmm_u_cmm_cfgspace_xrom_reg_1_29_ ( + .CE(cfg_cfg_5072[320]), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_cfgspace_N_68334_i), + .Q(com_cmm_xrom_reg_29_), + .CLR(com_cmm_rst_267) + ); + FDCE com_cmm_u_cmm_cfgspace_xrom_reg_1_28_ ( + .CE(cfg_cfg_5072[320]), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_cfgspace_N_68333_i), + .Q(com_cmm_xrom_reg_28_), + .CLR(com_cmm_rst_267) + ); + FDCE com_cmm_u_cmm_cfgspace_xrom_reg_1_27_ ( + .CE(cfg_cfg_5072[320]), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_cfgspace_N_68332_i), + .Q(com_cmm_xrom_reg_27_), + .CLR(com_cmm_rst_267) + ); + FDCE com_cmm_u_cmm_cfgspace_xrom_reg_1_26_ ( + .CE(cfg_cfg_5072[320]), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_cfgspace_N_68354_i), + .Q(com_cmm_xrom_reg_26_), + .CLR(com_cmm_rst_267) + ); + FDCE com_cmm_u_cmm_cfgspace_xrom_reg_1_25_ ( + .CE(cfg_cfg_5072[320]), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_cfgspace_N_68353_i), + .Q(com_cmm_xrom_reg_25_), + .CLR(com_cmm_rst_267) + ); + FDCE com_cmm_u_cmm_cfgspace_xrom_reg_1_24_ ( + .CE(cfg_cfg_5072[320]), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_cfgspace_N_68352_i), + .Q(com_cmm_xrom_reg_24_), + .CLR(com_cmm_rst_267) + ); + FDCE com_cmm_u_cmm_cfgspace_xrom_reg_1_23_ ( + .CE(cfg_cfg_5072[320]), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_cfgspace_N_68401_i), + .Q(com_cmm_xrom_reg_23_), + .CLR(com_cmm_rst_267) + ); + FDCE com_cmm_u_cmm_cfgspace_xrom_reg_1_22_ ( + .CE(cfg_cfg_5072[320]), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_cfgspace_N_68400_i), + .Q(com_cmm_xrom_reg_22_), + .CLR(com_cmm_rst_267) + ); + FDCE com_cmm_u_cmm_cfgspace_xrom_reg_1_21_ ( + .CE(cfg_cfg_5072[320]), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_cfgspace_N_68399_i), + .Q(com_cmm_xrom_reg_21_), + .CLR(com_cmm_rst_267) + ); + FDCE com_cmm_u_cmm_cfgspace_xrom_reg_1_20_ ( + .CE(cfg_cfg_5072[320]), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_cfgspace_N_68398_i), + .Q(com_cmm_xrom_reg_20_), + .CLR(com_cmm_rst_267) + ); + FDCE com_cmm_u_cmm_cfgspace_xrom_reg_1_19_ ( + .CE(cfg_cfg_5072[320]), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_cfgspace_N_68397_i), + .Q(com_cmm_xrom_reg_19_), + .CLR(com_cmm_rst_267) + ); + FDCE com_cmm_u_cmm_cfgspace_xrom_reg_1_18_ ( + .CE(cfg_cfg_5072[320]), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_cfgspace_N_68396_i), + .Q(com_cmm_xrom_reg_18_), + .CLR(com_cmm_rst_267) + ); + FDCE com_cmm_u_cmm_cfgspace_xrom_reg_1_17_ ( + .CE(cfg_cfg_5072[320]), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_cfgspace_N_68395_i), + .Q(com_cmm_xrom_reg_17_), + .CLR(com_cmm_rst_267) + ); + FDCE com_cmm_u_cmm_cfgspace_xrom_reg_1_16_ ( + .CE(cfg_cfg_5072[320]), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_cfgspace_N_68394_i), + .Q(com_cmm_xrom_reg_16_), + .CLR(com_cmm_rst_267) + ); + FDCE com_cmm_u_cmm_cfgspace_xrom_reg_1_15_ ( + .CE(cfg_cfg_5072[320]), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_cfgspace_N_68351_i), + .Q(com_cmm_xrom_reg_15_), + .CLR(com_cmm_rst_267) + ); + FDCE com_cmm_u_cmm_cfgspace_xrom_reg_1_14_ ( + .CE(cfg_cfg_5072[320]), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_cfgspace_N_68350_i), + .Q(com_cmm_xrom_reg_14_), + .CLR(com_cmm_rst_267) + ); + FDCE com_cmm_u_cmm_cfgspace_xrom_reg_1_13_ ( + .CE(cfg_cfg_5072[320]), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_cfgspace_N_68349_i), + .Q(com_cmm_xrom_reg_13_), + .CLR(com_cmm_rst_267) + ); + FDCE com_cmm_u_cmm_cfgspace_xrom_reg_1_12_ ( + .CE(cfg_cfg_5072[320]), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_cfgspace_N_68393_i), + .Q(com_cmm_xrom_reg_12_), + .CLR(com_cmm_rst_267) + ); + FDCE com_cmm_u_cmm_cfgspace_xrom_reg_1_11_ ( + .CE(cfg_cfg_5072[320]), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_cfgspace_N_68348_i), + .Q(com_cmm_xrom_reg_11_), + .CLR(com_cmm_rst_267) + ); + INV com_cmm_u_cmm_cfgspace_cfg2ulm_valid_i ( + .I(com_cmm_u_cmm_cfgspace_cfg2ulm_valid), + .O(cfg_rd_wr_done_n) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_01_7_0_am_0_3_.INIT = 8'h38; + LUT3 com_cmm_u_cmm_cfgspace_low_addr_01_7_0_am_0_3_ ( + .I0(com_cmm_bar5_reg[3]), + .I1(com_cmm_u_cmm_cfgspace_sel_encodex_1[1]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex_1[2]), + .O(com_cmm_u_cmm_cfgspace_low_addr_01_7_0_am_0[3]) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_00_i_0_0_0_.INIT = 16'h4404; + LUT4_L com_cmm_u_cmm_cfgspace_low_addr_00_i_0_0_0_ ( + .I0(com_cmm_u_cmm_cfgspace_N_42541), + .I1(com_cmm_u_cmm_cfgspace_low_addr_00_i_0_0_0_32087_4788), + .I2(com_cmm_u_cmm_cfgspace_low_addr_00_i_0_0_1[0]), + .I3(com_cmm_u_cmm_cfgspace_sel_encodex_2[1]), + .LO(com_cmm_u_cmm_cfgspace_N_15295_i) + ); + defparam com_cmm_u_cmm_errman_reg_detectedcorrectable_3_i_0_0_a2_1.INIT = 4'h4; + LUT2 com_cmm_u_cmm_errman_reg_detectedcorrectable_3_i_0_0_a2_1 ( + .I0(com_replay_timer_expire), + .I1(com_replay_timer_expire_pre), + .O(com_replay_vld) + ); + defparam com_cmm_u_cmm_errman_reg_detectedcorrectable_3_i_0_0_a2_0.INIT = 4'h8; + LUT2 com_cmm_u_cmm_errman_reg_detectedcorrectable_3_i_0_0_a2_0 ( + .I0(cmmp_receiver_err), + .I1(plm_link_up_1), + .O(com_cmm_u_cmm_errman_reg_detectedcorrectable_3_i_0_0_a2_0_4794) + ); + defparam com_cmm_u_cmm_errman_cfg_is_np_and_cpl_abort_0_a3_0_a2_0_a2_0_a2.INIT = 4'h4; + LUT2 com_cmm_u_cmm_errman_cfg_is_np_and_cpl_abort_0_a3_0_a2_0_a2_0_a2 ( + .I0(cfg_err_cpl_abort_n), + .I1(cfg_err_posted_n), + .O(com_cmm_u_cmm_errman_cfg_is_np_and_cpl_abort) + ); + defparam com_cmm_u_cmm_errman_ns_fsm_0_i_0_0_0_a2_0_1_1_.INIT = 4'h1; + LUT2 com_cmm_u_cmm_errman_ns_fsm_0_i_0_0_0_a2_0_1_1_ ( + .I0(com_cmm_u_cmm_errman_cs_fsm[3]), + .I1(com_cmm_u_cmm_errman_send_cplu_4817), + .O(com_cmm_u_cmm_errman_N_49573_1) + ); + defparam com_cmm_u_cmm_errman_ns_fsm_0_i_0_0_0_o3_0_2_.INIT = 4'h8; + LUT2 com_cmm_u_cmm_errman_ns_fsm_0_i_0_0_0_o3_0_2_ ( + .I0(com_cmm_u_cmm_errman_cs_fsm[0]), + .I1(com_cmm_u_cmm_errman_cs_fsm[1]), + .O(com_cmm_u_cmm_errman_N_48984_i) + ); + defparam com_cmm_u_cmm_errman_N_44904_i_0_o3.INIT = 4'h8; + LUT2 com_cmm_u_cmm_errman_N_44904_i_0_o3 ( + .I0(com_cmm_gnt_errman), + .I1(com_cmm_u_cmm_errman_cs_is_cplt_4807), + .O(com_cmm_u_cmm_errman_N_48948_i) + ); + defparam com_cmm_u_cmm_errman_ns_fsm_0_i_0_0_0_o3_0_1_.INIT = 4'h1; + LUT2 com_cmm_u_cmm_errman_ns_fsm_0_i_0_0_0_o3_0_1_ ( + .I0(com_cmm_u_cmm_errman_send_cplt_4802), + .I1(com_cmm_u_cmm_errman_send_ftl_4815), + .O(com_cmm_u_cmm_errman_N_48944_i) + ); + defparam com_cmm_u_cmm_errman_ns_fsm_0_i_0_0_0_o3_1_.INIT = 4'h1; + LUT2 com_cmm_u_cmm_errman_ns_fsm_0_i_0_0_0_o3_1_ ( + .I0(com_cmm_u_cmm_errman_cs_fsm[0]), + .I1(com_cmm_u_cmm_errman_cs_fsm[2]), + .O(com_cmm_u_cmm_errman_N_48916_i) + ); + defparam com_cmm_u_cmm_errman_N_44864_i_0_o3.INIT = 4'h8; + LUT2 com_cmm_u_cmm_errman_N_44864_i_0_o3 ( + .I0(com_cmm_gnt_errman), + .I1(com_cmm_u_cmm_errman_cs_is_ftl_4805), + .O(N_48877_i) + ); + defparam com_cmm_u_cmm_errman_request_9_i_0_0_0_0_a2_2_.INIT = 4'h4; + LUT2 com_cmm_u_cmm_errman_request_9_i_0_0_0_0_a2_2_ ( + .I0(com_cmm_u_cmm_errman_cs_fsm[1]), + .I1(com_cmm_u_cmm_errman_cs_fsm[2]), + .O(com_cmm_u_cmm_errman_N_49488) + ); + defparam com_cmm_u_cmm_errman_cor_num_axb0.INIT = 4'h9; + LUT2 com_cmm_u_cmm_errman_cor_num_axb0 ( + .I0(com_cmm_u_cmm_errman_cor_num_int[0]), + .I1(com_cmm_u_cmm_errman_reg_decr_cor), + .O(com_cmm_u_cmm_errman_cor_num_i[0]) + ); + defparam com_cmm_u_cmm_errman_reg_detectedcorrectable_3_i_0_0_a2.INIT = 8'h51; + LUT3 com_cmm_u_cmm_errman_reg_detectedcorrectable_3_i_0_0_a2 ( + .I0(com_N_38451), + .I1(com_rx_tlp_range_err_n), + .I2(com_rx_tlp_tsn_err_crc_or_ferr), + .O(com_cmm_u_cmm_errman_reg_detectedcorrectable_3_i_0_0_a2_4796) + ); + defparam com_cmm_u_cmm_errman_cs_is_ftl29_0_a2_0_a3_0_a3_0_a3.INIT = 8'h02; + LUT3 com_cmm_u_cmm_errman_cs_is_ftl29_0_a2_0_a3_0_a3_0_a3 ( + .I0(com_cmm_u_cmm_errman_cs_fsm[0]), + .I1(com_cmm_u_cmm_errman_cs_fsm[1]), + .I2(com_cmm_u_cmm_errman_cs_fsm[2]), + .O(com_cmm_u_cmm_errman_cs_is_ftl29) + ); + defparam com_cmm_u_cmm_errman_un1_cmmt_err_tlp_ur_i_0_0_0_a2.INIT = 8'h15; + LUT3 com_cmm_u_cmm_errman_un1_cmmt_err_tlp_ur_i_0_0_0_a2 ( + .I0(NlwRenamedSig_OI_cfg_command_8_), + .I1(NlwRenamedSig_OI_cfg_dcommand[1]), + .I2(NlwRenamedSig_OI_cfg_dcommand[3]), + .O(com_cmm_u_cmm_errman_N_49554) + ); + defparam com_cmm_u_cmm_errman_request_9_i_0_0_0_0_a2_0_2_.INIT = 4'h2; + LUT2 com_cmm_u_cmm_errman_request_9_i_0_0_0_0_a2_0_2_ ( + .I0(com_cmm_u_cmm_errman_N_48984_i), + .I1(com_cmm_u_cmm_errman_cs_fsm[2]), + .O(com_cmm_u_cmm_errman_cs_is_ftl31) + ); + defparam com_cmm_u_cmm_errman_nfl_num_axb0.INIT = 8'h95; + LUT3 com_cmm_u_cmm_errman_nfl_num_axb0 ( + .I0(com_cmm_u_cmm_errman_reg_decr_nfl), + .I1(com_cmm_u_cmm_errman_to_incr_0ro), + .I2(com_cmm_u_cmm_pm_dev_power_state_eq_d0), + .O(com_cmm_u_cmm_errman_nfl_num_i[0]) + ); + defparam com_cmm_u_cmm_errman_send_ftl_3_0_a2.INIT = 16'h0001; + LUT4 com_cmm_u_cmm_errman_send_ftl_3_0_a2 ( + .I0(com_cmm_u_cmm_errman_cnt_ftl[0]), + .I1(com_cmm_u_cmm_errman_cnt_ftl[1]), + .I2(com_cmm_u_cmm_errman_cnt_ftl[2]), + .I3(com_cmm_u_cmm_errman_cnt_ftl[3]), + .O(com_cmm_u_cmm_errman_send_ftl_3_0_a2_4791) + ); + defparam com_cmm_u_cmm_errman_send_cor_3_0_a2.INIT = 16'h0001; + LUT4 com_cmm_u_cmm_errman_send_cor_3_0_a2 ( + .I0(com_cmm_u_cmm_errman_cnt_cor[0]), + .I1(com_cmm_u_cmm_errman_cnt_cor[1]), + .I2(com_cmm_u_cmm_errman_cnt_cor[2]), + .I3(com_cmm_u_cmm_errman_cnt_cor[3]), + .O(com_cmm_u_cmm_errman_send_cor_3_0_a2_4790) + ); + defparam com_cmm_u_cmm_errman_send_nfl_3_0_a2.INIT = 16'h0001; + LUT4 com_cmm_u_cmm_errman_send_nfl_3_0_a2 ( + .I0(com_cmm_u_cmm_errman_cnt_nfl[0]), + .I1(com_cmm_u_cmm_errman_cnt_nfl[1]), + .I2(com_cmm_u_cmm_errman_cnt_nfl[2]), + .I3(com_cmm_u_cmm_errman_cnt_nfl[3]), + .O(com_cmm_u_cmm_errman_un1_reg_uflow_3_0) + ); + defparam com_cmm_u_cmm_errman_send_cplt_3_0_a2.INIT = 16'h0001; + LUT4 com_cmm_u_cmm_errman_send_cplt_3_0_a2 ( + .I0(com_cmm_u_cmm_errman_cnt_cplt[0]), + .I1(com_cmm_u_cmm_errman_cnt_cplt[1]), + .I2(com_cmm_u_cmm_errman_cnt_cplt[2]), + .I3(com_cmm_u_cmm_errman_cnt_cplt[3]), + .O(com_cmm_u_cmm_errman_un1_reg_uflow_3_1) + ); + defparam com_cmm_u_cmm_errman_send_cplu_3_0_a2.INIT = 16'h0001; + LUT4 com_cmm_u_cmm_errman_send_cplu_3_0_a2 ( + .I0(com_cmm_u_cmm_errman_cnt_cplu[0]), + .I1(com_cmm_u_cmm_errman_cnt_cplu[1]), + .I2(com_cmm_u_cmm_errman_cnt_cplu[2]), + .I3(com_cmm_u_cmm_errman_cnt_cplu[3]), + .O(com_cmm_u_cmm_errman_un1_reg_uflow_3) + ); + defparam com_cmm_u_cmm_errman_ns_fsm_0_i_0_0_0_a2_1_1_2_.INIT = 16'h1110; + LUT4 com_cmm_u_cmm_errman_ns_fsm_0_i_0_0_0_a2_1_1_2_ ( + .I0(com_cmm_u_cmm_errman_cs_fsm[0]), + .I1(com_cmm_u_cmm_errman_cs_fsm[1]), + .I2(com_cmm_u_cmm_errman_send_cor_4804), + .I3(com_cmm_u_cmm_errman_send_nfl_4813), + .O(com_cmm_u_cmm_errman_ns_fsm_0_i_0_0_0_a2_1_1[2]) + ); + defparam com_cmm_u_cmm_errman_reg_detectedcorrectable_3_i_0_0_1.INIT = 16'h8808; + LUT4 com_cmm_u_cmm_errman_reg_detectedcorrectable_3_i_0_0_1 ( + .I0(cfg_err_cor_n), + .I1(com_cmml_bad_dllp_err_n), + .I2(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_num[2]), + .I3(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_num_2_q[0]), + .O(com_cmm_u_cmm_errman_reg_detectedcorrectable_3_i_0_0_1_4793) + ); + defparam com_cmm_u_cmm_errman_ns_fsm_0_i_0_0_0_a2_1_0_0_.INIT = 8'h02; + LUT3_L com_cmm_u_cmm_errman_ns_fsm_0_i_0_0_0_a2_1_0_0_ ( + .I0(com_cmm_u_cmm_errman_N_48916_i), + .I1(com_cmm_u_cmm_errman_cs_fsm[1]), + .I2(com_cmm_u_cmm_errman_cs_fsm[3]), + .LO(com_cmm_u_cmm_errman_ns_fsm_0_i_0_0_0_a2_1[0]) + ); + defparam com_cmm_u_cmm_errman_ns_fsm_0_i_0_0_0_a2_2_.INIT = 16'h08A8; + LUT4 com_cmm_u_cmm_errman_ns_fsm_0_i_0_0_0_a2_2_ ( + .I0(com_cmm_gnt_errman), + .I1(com_cmm_u_cmm_errman_cs_fsm[0]), + .I2(com_cmm_u_cmm_errman_cs_fsm[1]), + .I3(com_cmm_u_cmm_errman_cs_fsm[2]), + .O(com_cmm_u_cmm_errman_N_49569) + ); + defparam com_cmm_u_cmm_errman_ns_fsm_0_i_0_0_0_a3_0_.INIT = 16'h3032; + LUT4 com_cmm_u_cmm_errman_ns_fsm_0_i_0_0_0_a3_0_ ( + .I0(com_cmm_u_cmm_errman_send_cor_4804), + .I1(com_cmm_u_cmm_errman_send_cplt_4802), + .I2(com_cmm_u_cmm_errman_send_ftl_4815), + .I3(com_cmm_u_cmm_errman_send_nfl_4813), + .O(com_cmm_u_cmm_errman_N_50749) + ); + defparam com_cmm_u_cmm_errman_nfl_num_c1.INIT = 8'h2A; + LUT3 com_cmm_u_cmm_errman_nfl_num_c1 ( + .I0(com_cmm_u_cmm_errman_reg_decr_nfl), + .I1(com_cmm_u_cmm_errman_to_incr_0ro), + .I2(com_cmm_u_cmm_pm_dev_power_state_eq_d0), + .O(com_cmm_u_cmm_errman_nfl_num_c1_4789) + ); + defparam com_cmm_u_cmm_errman_ns_fsm_0_i_0_0_0_a2_1_2_.INIT = 8'h80; + LUT3_L com_cmm_u_cmm_errman_ns_fsm_0_i_0_0_0_a2_1_2_ ( + .I0(com_cmm_u_cmm_errman_N_48944_i), + .I1(com_cmm_u_cmm_errman_N_49573_1), + .I2(com_cmm_u_cmm_errman_ns_fsm_0_i_0_0_0_a2_1_1[2]), + .LO(com_cmm_u_cmm_errman_N_49571) + ); + defparam com_cmm_u_cmm_errman_ns_fsm_0_i_0_0_0_0_1_.INIT = 16'hC507; + LUT4 com_cmm_u_cmm_errman_ns_fsm_0_i_0_0_0_0_1_ ( + .I0(com_cmm_gnt_errman), + .I1(com_cmm_u_cmm_errman_cs_fsm[0]), + .I2(com_cmm_u_cmm_errman_cs_fsm[1]), + .I3(com_cmm_u_cmm_errman_cs_fsm[2]), + .O(com_cmm_u_cmm_errman_ns_fsm_0_i_0_0_0_0[1]) + ); + defparam com_cmm_u_cmm_errman_reg_detectednonfatal_3_i_0_0_0_1.INIT = 16'h0888; + LUT4_L com_cmm_u_cmm_errman_reg_detectednonfatal_3_i_0_0_0_1 ( + .I0(cfg_err_cpl_timeout_n), + .I1(cfg_err_ecrc_n), + .I2(com_cmmt_err_tlp_p_cpl), + .I3(com_cmmt_err_tlp_ur), + .LO(com_cmm_u_cmm_errman_reg_detectednonfatal_3_i_0_0_0_1_4792) + ); + defparam com_cmm_u_cmm_errman_ns_fsm_0_i_0_0_0_0_0_.INIT = 16'hCBBB; + LUT4 com_cmm_u_cmm_errman_ns_fsm_0_i_0_0_0_0_0_ ( + .I0(com_cmm_gnt_errman), + .I1(com_cmm_u_cmm_errman_cs_fsm[0]), + .I2(com_cmm_u_cmm_errman_cs_fsm[1]), + .I3(com_cmm_u_cmm_errman_cs_fsm[2]), + .O(com_cmm_u_cmm_errman_ns_fsm_0_i_0_0_0_0[0]) + ); + defparam com_cmm_u_cmm_errman_cor_num_i_1_.INIT = 8'h63; + LUT3 com_cmm_u_cmm_errman_cor_num_i_1_ ( + .I0(com_cmm_u_cmm_errman_cor_num_int[0]), + .I1(com_cmm_u_cmm_errman_cor_num_int[1]), + .I2(com_cmm_u_cmm_errman_reg_decr_cor), + .O(com_cmm_u_cmm_errman_cor_num_i[1]) + ); + defparam com_cmm_u_cmm_errman_cor_num_axbxc2.INIT = 16'hE1F0; + LUT4 com_cmm_u_cmm_errman_cor_num_axbxc2 ( + .I0(com_cmm_u_cmm_errman_cor_num_int[0]), + .I1(com_cmm_u_cmm_errman_cor_num_int[1]), + .I2(com_cmm_u_cmm_errman_cor_num_int[2]), + .I3(com_cmm_u_cmm_errman_reg_decr_cor), + .O(com_cmm_u_cmm_errman_cor_num[2]) + ); + defparam com_cmm_u_cmm_errman_nfl_num_i_1_.INIT = 8'h95; + LUT3 com_cmm_u_cmm_errman_nfl_num_i_1_ ( + .I0(com_cmm_u_cmm_errman_nfl_num_c1_4789), + .I1(com_cmm_u_cmm_errman_to_incr_1ro), + .I2(com_cmm_u_cmm_pm_dev_power_state_eq_d0), + .O(com_cmm_u_cmm_errman_nfl_num_i[1]) + ); + defparam com_cmm_u_cmm_errman_nfl_num_axbxc2.INIT = 16'hD2AA; + LUT4 com_cmm_u_cmm_errman_nfl_num_axbxc2 ( + .I0(com_cmm_u_cmm_errman_nfl_num_c1_4789), + .I1(com_cmm_u_cmm_errman_to_incr_1ro), + .I2(com_cmm_u_cmm_errman_to_incr_2ro), + .I3(com_cmm_u_cmm_pm_dev_power_state_eq_d0), + .O(com_cmm_u_cmm_errman_nfl_num[2]) + ); + defparam com_cmm_u_cmm_errman_un1_reg_uflow_3_i.INIT = 4'h1; + LUT1_L com_cmm_u_cmm_errman_un1_reg_uflow_3_i ( + .I0(com_cmm_u_cmm_errman_un1_reg_uflow_3_1), + .LO(com_cmm_u_cmm_errman_un1_reg_uflow_3_i_1_4801) + ); + defparam com_cmm_u_cmm_errman_N_51019_i.INIT = 4'h1; + LUT1_L com_cmm_u_cmm_errman_N_51019_i ( + .I0(com_cmm_u_cmm_errman_send_cor_3_0_a2_4790), + .LO(com_cmm_u_cmm_errman_N_51019_i_4803) + ); + defparam com_cmm_u_cmm_errman_request_9_i_i_i_0_a2_0_a2_0_.INIT = 4'h2; + LUT2_L com_cmm_u_cmm_errman_request_9_i_i_i_0_a2_0_a2_0_ ( + .I0(com_cmm_u_cmm_errman_N_49488), + .I1(com_cmm_u_cmm_errman_cs_fsm[0]), + .LO(com_cmm_u_cmm_errman_cs_is_ftl32) + ); + defparam com_cmm_u_cmm_errman_cs_is_ftl33_0_a2_0_a2_0_a2_0_a2.INIT = 8'h20; + LUT3_L com_cmm_u_cmm_errman_cs_is_ftl33_0_a2_0_a2_0_a2_0_a2 ( + .I0(com_cmm_u_cmm_errman_cs_fsm[0]), + .I1(com_cmm_u_cmm_errman_cs_fsm[1]), + .I2(com_cmm_u_cmm_errman_cs_fsm[2]), + .LO(com_cmm_u_cmm_errman_cs_is_ftl33) + ); + defparam com_cmm_u_cmm_errman_N_68759_i.INIT = 16'hF111; + LUT4_L com_cmm_u_cmm_errman_N_68759_i ( + .I0(cfg_err_posted_n), + .I1(cfg_err_ur_n), + .I2(com_cmmt_err_tlp_p_cpl), + .I3(com_cmmt_err_tlp_ur), + .LO(com_cmm_u_cmm_errman_N_68759_i_4810) + ); + defparam com_cmm_u_cmm_errman_reg_masterdataparityerror_3.INIT = 8'hA8; + LUT3_L com_cmm_u_cmm_errman_reg_masterdataparityerror_3 ( + .I0(NlwRenamedSig_OI_cfg_command_6_), + .I1(com_cmmt_stat_tlp_rx_cpl_ep), + .I2(com_cmmt_stat_tlp_tx_wr_ep), + .LO(com_cmm_u_cmm_errman_reg_masterdataparityerror_3_4811) + ); + defparam com_cmm_u_cmm_errman_un1_reg_uflow_3_i_0.INIT = 4'h1; + LUT1_L com_cmm_u_cmm_errman_un1_reg_uflow_3_i_0 ( + .I0(com_cmm_u_cmm_errman_un1_reg_uflow_3_0), + .LO(com_cmm_u_cmm_errman_un1_reg_uflow_3_i_0_4812) + ); + defparam com_cmm_u_cmm_errman_N_51043_i.INIT = 4'h1; + LUT1_L com_cmm_u_cmm_errman_N_51043_i ( + .I0(com_cmm_u_cmm_errman_send_ftl_3_0_a2_4791), + .LO(com_cmm_u_cmm_errman_N_51043_i_4814) + ); + defparam com_cmm_u_cmm_errman_un1_reg_uflow_3_i_1.INIT = 4'h1; + LUT1_L com_cmm_u_cmm_errman_un1_reg_uflow_3_i_1 ( + .I0(com_cmm_u_cmm_errman_un1_reg_uflow_3), + .LO(com_cmm_u_cmm_errman_un1_reg_uflow_3_i_4816) + ); + defparam com_cmm_u_cmm_errman_N_68187_i.INIT = 16'h13FF; + LUT4_L com_cmm_u_cmm_errman_N_68187_i ( + .I0(cfg_err_cpl_abort_n), + .I1(cfg_err_posted_n), + .I2(cfg_err_ur_n), + .I3(com_cmm_u_cmm_errman_reg_detectednonfatal_3_i_0_0_0_1_4792), + .LO(com_cmm_u_cmm_errman_N_68187_i_4818) + ); + defparam com_cmm_u_cmm_errman_N_67919_i.INIT = 16'hFFEF; + LUT4_L com_cmm_u_cmm_errman_N_67919_i ( + .I0(com_cmm_u_cmm_errman_reg_detectedcorrectable_3_i_0_0_a2_4796), + .I1(com_cmm_u_cmm_errman_reg_detectedcorrectable_3_i_0_0_a2_0_4794), + .I2(com_cmm_u_cmm_errman_reg_detectedcorrectable_3_i_0_0_1_4793), + .I3(com_replay_vld), + .LO(com_cmm_u_cmm_errman_N_67919_i_4819) + ); + defparam com_cmm_u_cmm_errman_request_9_i_i_i_0_i_0_.INIT = 8'h14; + LUT3_L com_cmm_u_cmm_errman_request_9_i_i_i_0_i_0_ ( + .I0(com_cmm_u_cmm_errman_cs_fsm[0]), + .I1(com_cmm_u_cmm_errman_cs_fsm[1]), + .I2(com_cmm_u_cmm_errman_cs_fsm[2]), + .LO(com_cmm_u_cmm_errman_N_47879_i) + ); + defparam com_cmm_u_cmm_errman_reg_cfg_wr_hdr_6_i_0_0_4_.INIT = 4'h8; + LUT2_L com_cmm_u_cmm_errman_reg_cfg_wr_hdr_6_i_0_0_4_ ( + .I0(com_cmm_u_cmm_errman_N_49807), + .I1(cfg_err_tlp_cpl_header_5070[4]), + .LO(com_cmm_u_cmm_errman_N_32752_i) + ); + defparam com_cmm_u_cmm_errman_reg_cfg_wr_hdr_6_i_0_0_3_.INIT = 4'h8; + LUT2_L com_cmm_u_cmm_errman_reg_cfg_wr_hdr_6_i_0_0_3_ ( + .I0(com_cmm_u_cmm_errman_N_49807), + .I1(cfg_err_tlp_cpl_header_5070[3]), + .LO(com_cmm_u_cmm_errman_N_32750_i) + ); + defparam com_cmm_u_cmm_errman_reg_cfg_wr_hdr_6_i_0_0_2_.INIT = 4'h8; + LUT2_L com_cmm_u_cmm_errman_reg_cfg_wr_hdr_6_i_0_0_2_ ( + .I0(com_cmm_u_cmm_errman_N_49807), + .I1(cfg_err_tlp_cpl_header_5070[2]), + .LO(com_cmm_u_cmm_errman_N_32748_i) + ); + defparam com_cmm_u_cmm_errman_reg_cfg_wr_hdr_6_i_0_0_1_.INIT = 4'h8; + LUT2_L com_cmm_u_cmm_errman_reg_cfg_wr_hdr_6_i_0_0_1_ ( + .I0(com_cmm_u_cmm_errman_N_49807), + .I1(cfg_err_tlp_cpl_header_5070[1]), + .LO(com_cmm_u_cmm_errman_N_32746_i) + ); + defparam com_cmm_u_cmm_errman_reg_cfg_wr_hdr_6_i_0_0_0_.INIT = 4'h8; + LUT2_L com_cmm_u_cmm_errman_reg_cfg_wr_hdr_6_i_0_0_0_ ( + .I0(com_cmm_u_cmm_errman_N_49807), + .I1(cfg_err_tlp_cpl_header_5070[0]), + .LO(com_cmm_u_cmm_errman_N_32744_i) + ); + defparam com_cmm_u_cmm_errman_reg_cfg_rp_4_axbxc1.INIT = 8'h78; + LUT3_L com_cmm_u_cmm_errman_reg_cfg_rp_4_axbxc1 ( + .I0(com_cmm_u_cmm_errman_N_48933_i), + .I1(com_cmm_u_cmm_errman_reg_cfg_rp[0]), + .I2(com_cmm_u_cmm_errman_reg_cfg_rp[1]), + .LO(com_cmm_u_cmm_errman_reg_cfg_rp_4[1]) + ); + defparam com_cmm_u_cmm_errman_reg_cfg_rp_4_axbxc0.INIT = 4'h6; + LUT2_L com_cmm_u_cmm_errman_reg_cfg_rp_4_axbxc0 ( + .I0(com_cmm_u_cmm_errman_N_48933_i), + .I1(com_cmm_u_cmm_errman_reg_cfg_rp[0]), + .LO(com_cmm_u_cmm_errman_reg_cfg_rp_4[0]) + ); + defparam com_cmm_u_cmm_errman_reg_cmt_rp_4_axbxc1.INIT = 8'h78; + LUT3_L com_cmm_u_cmm_errman_reg_cmt_rp_4_axbxc1 ( + .I0(com_cmm_u_cmm_errman_N_48948_i), + .I1(com_cmm_u_cmm_errman_reg_cmt_rp[0]), + .I2(com_cmm_u_cmm_errman_reg_cmt_rp[1]), + .LO(com_cmm_u_cmm_errman_reg_cmt_rp_4[1]) + ); + defparam com_cmm_u_cmm_errman_reg_cmt_rp_4_axbxc0.INIT = 4'h6; + LUT2_L com_cmm_u_cmm_errman_reg_cmt_rp_4_axbxc0 ( + .I0(com_cmm_u_cmm_errman_N_48948_i), + .I1(com_cmm_u_cmm_errman_reg_cmt_rp[0]), + .LO(com_cmm_u_cmm_errman_reg_cmt_rp_4[0]) + ); + defparam com_cmm_u_cmm_errman_un1_cs_fsm_1_0_a2_0_a2_0_a2_0_a2.INIT = 8'h80; + LUT3_L com_cmm_u_cmm_errman_un1_cs_fsm_1_0_a2_0_a2_0_a2_0_a2 ( + .I0(com_cmm_u_cmm_errman_cs_fsm[0]), + .I1(com_cmm_u_cmm_errman_cs_fsm[1]), + .I2(com_cmm_u_cmm_errman_cs_fsm[2]), + .LO(com_cmm_u_cmm_errman_un1_cs_fsm_1_0_a2_0_a2_0_a2_0_a2_4820) + ); + defparam com_cmm_u_cmm_errman_N_68159_i.INIT = 16'hFDFC; + LUT4_L com_cmm_u_cmm_errman_N_68159_i ( + .I0(com_cmm_u_cmm_errman_N_48984_i), + .I1(com_cmm_u_cmm_errman_N_49569), + .I2(com_cmm_u_cmm_errman_N_49571), + .I3(com_cmm_u_cmm_errman_cs_fsm[2]), + .LO(com_cmm_u_cmm_errman_N_68159_i_4821) + ); + defparam com_cmm_u_cmm_errman_N_68160_i.INIT = 16'h20FF; + LUT4_L com_cmm_u_cmm_errman_N_68160_i ( + .I0(com_cmm_u_cmm_errman_N_48916_i), + .I1(com_cmm_u_cmm_errman_N_48944_i), + .I2(com_cmm_u_cmm_errman_N_49573_1), + .I3(com_cmm_u_cmm_errman_ns_fsm_0_i_0_0_0_0[1]), + .LO(com_cmm_u_cmm_errman_N_68160_i_4822) + ); + defparam com_cmm_u_cmm_errman_N_68198_i.INIT = 16'hF3B3; + LUT4_L com_cmm_u_cmm_errman_N_68198_i ( + .I0(com_cmm_u_cmm_errman_N_50749), + .I1(com_cmm_u_cmm_errman_ns_fsm_0_i_0_0_0_0[0]), + .I2(com_cmm_u_cmm_errman_ns_fsm_0_i_0_0_0_a2_1[0]), + .I3(com_cmm_u_cmm_errman_send_cplu_4817), + .LO(com_cmm_u_cmm_errman_N_68198_i_4823) + ); + defparam com_cmm_u_cmm_errman_N_68481_i.INIT = 4'hE; + LUT2_L com_cmm_u_cmm_errman_N_68481_i ( + .I0(com_cmm_u_cmm_errman_N_49488), + .I1(com_cmm_u_cmm_errman_cs_is_ftl31), + .LO(com_cmm_u_cmm_errman_N_68481_i_4824) + ); + defparam com_cmm_u_cmm_errman_N_68617_i.INIT = 8'hF2; + LUT3_L com_cmm_u_cmm_errman_N_68617_i ( + .I0(com_cmm_u_cmm_errman_cs_fsm[0]), + .I1(com_cmm_u_cmm_errman_cs_fsm[1]), + .I2(com_cmm_u_cmm_errman_cs_is_ftl30), + .LO(com_cmm_u_cmm_errman_N_68617_i_4825) + ); + defparam com_cmm_u_cmm_errman_reg_cfg_wr_hdr_6_i_0_0_19_.INIT = 4'h8; + LUT2_L com_cmm_u_cmm_errman_reg_cfg_wr_hdr_6_i_0_0_19_ ( + .I0(com_cmm_u_cmm_errman_N_49807), + .I1(cfg_err_tlp_cpl_header_5070[19]), + .LO(com_cmm_u_cmm_errman_N_32782_i) + ); + defparam com_cmm_u_cmm_errman_reg_cfg_wr_hdr_6_i_0_0_18_.INIT = 4'h8; + LUT2_L com_cmm_u_cmm_errman_reg_cfg_wr_hdr_6_i_0_0_18_ ( + .I0(com_cmm_u_cmm_errman_N_49807), + .I1(cfg_err_tlp_cpl_header_5070[18]), + .LO(com_cmm_u_cmm_errman_N_32780_i) + ); + defparam com_cmm_u_cmm_errman_reg_cfg_wr_hdr_6_i_0_0_17_.INIT = 4'h8; + LUT2_L com_cmm_u_cmm_errman_reg_cfg_wr_hdr_6_i_0_0_17_ ( + .I0(com_cmm_u_cmm_errman_N_49807), + .I1(cfg_err_tlp_cpl_header_5070[17]), + .LO(com_cmm_u_cmm_errman_N_32778_i) + ); + defparam com_cmm_u_cmm_errman_reg_cfg_wr_hdr_6_i_0_0_16_.INIT = 4'h8; + LUT2_L com_cmm_u_cmm_errman_reg_cfg_wr_hdr_6_i_0_0_16_ ( + .I0(com_cmm_u_cmm_errman_N_49807), + .I1(cfg_err_tlp_cpl_header_5070[16]), + .LO(com_cmm_u_cmm_errman_N_32776_i) + ); + defparam com_cmm_u_cmm_errman_reg_cfg_wr_hdr_6_i_0_0_15_.INIT = 4'h8; + LUT2_L com_cmm_u_cmm_errman_reg_cfg_wr_hdr_6_i_0_0_15_ ( + .I0(com_cmm_u_cmm_errman_N_49807), + .I1(cfg_err_tlp_cpl_header_5070[15]), + .LO(com_cmm_u_cmm_errman_N_32774_i) + ); + defparam com_cmm_u_cmm_errman_reg_cfg_wr_hdr_6_i_0_0_14_.INIT = 4'h8; + LUT2_L com_cmm_u_cmm_errman_reg_cfg_wr_hdr_6_i_0_0_14_ ( + .I0(com_cmm_u_cmm_errman_N_49807), + .I1(cfg_err_tlp_cpl_header_5070[14]), + .LO(com_cmm_u_cmm_errman_N_32772_i) + ); + defparam com_cmm_u_cmm_errman_reg_cfg_wr_hdr_6_i_0_0_13_.INIT = 4'h8; + LUT2_L com_cmm_u_cmm_errman_reg_cfg_wr_hdr_6_i_0_0_13_ ( + .I0(com_cmm_u_cmm_errman_N_49807), + .I1(cfg_err_tlp_cpl_header_5070[13]), + .LO(com_cmm_u_cmm_errman_N_32770_i) + ); + defparam com_cmm_u_cmm_errman_reg_cfg_wr_hdr_6_i_0_0_12_.INIT = 4'h8; + LUT2_L com_cmm_u_cmm_errman_reg_cfg_wr_hdr_6_i_0_0_12_ ( + .I0(com_cmm_u_cmm_errman_N_49807), + .I1(cfg_err_tlp_cpl_header_5070[12]), + .LO(com_cmm_u_cmm_errman_N_32768_i) + ); + defparam com_cmm_u_cmm_errman_reg_cfg_wr_hdr_6_i_0_0_11_.INIT = 4'h8; + LUT2_L com_cmm_u_cmm_errman_reg_cfg_wr_hdr_6_i_0_0_11_ ( + .I0(com_cmm_u_cmm_errman_N_49807), + .I1(cfg_err_tlp_cpl_header_5070[11]), + .LO(com_cmm_u_cmm_errman_N_32766_i) + ); + defparam com_cmm_u_cmm_errman_reg_cfg_wr_hdr_6_i_0_0_10_.INIT = 4'h8; + LUT2_L com_cmm_u_cmm_errman_reg_cfg_wr_hdr_6_i_0_0_10_ ( + .I0(com_cmm_u_cmm_errman_N_49807), + .I1(cfg_err_tlp_cpl_header_5070[10]), + .LO(com_cmm_u_cmm_errman_N_32764_i) + ); + defparam com_cmm_u_cmm_errman_reg_cfg_wr_hdr_6_i_0_0_9_.INIT = 4'h8; + LUT2_L com_cmm_u_cmm_errman_reg_cfg_wr_hdr_6_i_0_0_9_ ( + .I0(com_cmm_u_cmm_errman_N_49807), + .I1(cfg_err_tlp_cpl_header_5070[9]), + .LO(com_cmm_u_cmm_errman_N_32762_i) + ); + defparam com_cmm_u_cmm_errman_reg_cfg_wr_hdr_6_i_0_0_8_.INIT = 4'h8; + LUT2_L com_cmm_u_cmm_errman_reg_cfg_wr_hdr_6_i_0_0_8_ ( + .I0(com_cmm_u_cmm_errman_N_49807), + .I1(cfg_err_tlp_cpl_header_5070[8]), + .LO(com_cmm_u_cmm_errman_N_32760_i) + ); + defparam com_cmm_u_cmm_errman_reg_cfg_wr_hdr_6_i_0_0_7_.INIT = 4'h8; + LUT2_L com_cmm_u_cmm_errman_reg_cfg_wr_hdr_6_i_0_0_7_ ( + .I0(com_cmm_u_cmm_errman_N_49807), + .I1(cfg_err_tlp_cpl_header_5070[7]), + .LO(com_cmm_u_cmm_errman_N_32758_i) + ); + defparam com_cmm_u_cmm_errman_reg_cfg_wr_hdr_6_i_0_0_6_.INIT = 4'h8; + LUT2_L com_cmm_u_cmm_errman_reg_cfg_wr_hdr_6_i_0_0_6_ ( + .I0(com_cmm_u_cmm_errman_N_49807), + .I1(cfg_err_tlp_cpl_header_5070[6]), + .LO(com_cmm_u_cmm_errman_N_32756_i) + ); + defparam com_cmm_u_cmm_errman_reg_cfg_wr_hdr_6_i_0_0_5_.INIT = 4'h8; + LUT2_L com_cmm_u_cmm_errman_reg_cfg_wr_hdr_6_i_0_0_5_ ( + .I0(com_cmm_u_cmm_errman_N_49807), + .I1(cfg_err_tlp_cpl_header_5070[5]), + .LO(com_cmm_u_cmm_errman_N_32754_i) + ); + defparam com_cmm_u_cmm_errman_reg_cfg_wr_hdr_6_i_0_0_34_.INIT = 4'h8; + LUT2_L com_cmm_u_cmm_errman_reg_cfg_wr_hdr_6_i_0_0_34_ ( + .I0(com_cmm_u_cmm_errman_N_49807), + .I1(cfg_err_tlp_cpl_header_5070[34]), + .LO(com_cmm_u_cmm_errman_N_32812_i) + ); + defparam com_cmm_u_cmm_errman_reg_cfg_wr_hdr_6_i_0_0_33_.INIT = 4'h8; + LUT2_L com_cmm_u_cmm_errman_reg_cfg_wr_hdr_6_i_0_0_33_ ( + .I0(com_cmm_u_cmm_errman_N_49807), + .I1(cfg_err_tlp_cpl_header_5070[33]), + .LO(com_cmm_u_cmm_errman_N_32810_i) + ); + defparam com_cmm_u_cmm_errman_reg_cfg_wr_hdr_6_i_0_0_32_.INIT = 4'h8; + LUT2_L com_cmm_u_cmm_errman_reg_cfg_wr_hdr_6_i_0_0_32_ ( + .I0(com_cmm_u_cmm_errman_N_49807), + .I1(cfg_err_tlp_cpl_header_5070[32]), + .LO(com_cmm_u_cmm_errman_N_32808_i) + ); + defparam com_cmm_u_cmm_errman_reg_cfg_wr_hdr_6_i_0_0_31_.INIT = 4'h8; + LUT2_L com_cmm_u_cmm_errman_reg_cfg_wr_hdr_6_i_0_0_31_ ( + .I0(com_cmm_u_cmm_errman_N_49807), + .I1(cfg_err_tlp_cpl_header_5070[31]), + .LO(com_cmm_u_cmm_errman_N_32806_i) + ); + defparam com_cmm_u_cmm_errman_reg_cfg_wr_hdr_6_i_0_0_30_.INIT = 4'h8; + LUT2_L com_cmm_u_cmm_errman_reg_cfg_wr_hdr_6_i_0_0_30_ ( + .I0(com_cmm_u_cmm_errman_N_49807), + .I1(cfg_err_tlp_cpl_header_5070[30]), + .LO(com_cmm_u_cmm_errman_N_32804_i) + ); + defparam com_cmm_u_cmm_errman_reg_cfg_wr_hdr_6_i_0_0_29_.INIT = 4'h8; + LUT2_L com_cmm_u_cmm_errman_reg_cfg_wr_hdr_6_i_0_0_29_ ( + .I0(com_cmm_u_cmm_errman_N_49807), + .I1(cfg_err_tlp_cpl_header_5070[29]), + .LO(com_cmm_u_cmm_errman_N_32802_i) + ); + defparam com_cmm_u_cmm_errman_reg_cfg_wr_hdr_6_i_0_0_28_.INIT = 4'h8; + LUT2_L com_cmm_u_cmm_errman_reg_cfg_wr_hdr_6_i_0_0_28_ ( + .I0(com_cmm_u_cmm_errman_N_49807), + .I1(cfg_err_tlp_cpl_header_5070[28]), + .LO(com_cmm_u_cmm_errman_N_32800_i) + ); + defparam com_cmm_u_cmm_errman_reg_cfg_wr_hdr_6_i_0_0_27_.INIT = 4'h8; + LUT2_L com_cmm_u_cmm_errman_reg_cfg_wr_hdr_6_i_0_0_27_ ( + .I0(com_cmm_u_cmm_errman_N_49807), + .I1(cfg_err_tlp_cpl_header_5070[27]), + .LO(com_cmm_u_cmm_errman_N_32798_i) + ); + defparam com_cmm_u_cmm_errman_reg_cfg_wr_hdr_6_i_0_0_26_.INIT = 4'h8; + LUT2_L com_cmm_u_cmm_errman_reg_cfg_wr_hdr_6_i_0_0_26_ ( + .I0(com_cmm_u_cmm_errman_N_49807), + .I1(cfg_err_tlp_cpl_header_5070[26]), + .LO(com_cmm_u_cmm_errman_N_32796_i) + ); + defparam com_cmm_u_cmm_errman_reg_cfg_wr_hdr_6_i_0_0_25_.INIT = 4'h8; + LUT2_L com_cmm_u_cmm_errman_reg_cfg_wr_hdr_6_i_0_0_25_ ( + .I0(com_cmm_u_cmm_errman_N_49807), + .I1(cfg_err_tlp_cpl_header_5070[25]), + .LO(com_cmm_u_cmm_errman_N_32794_i) + ); + defparam com_cmm_u_cmm_errman_reg_cfg_wr_hdr_6_i_0_0_24_.INIT = 4'h8; + LUT2_L com_cmm_u_cmm_errman_reg_cfg_wr_hdr_6_i_0_0_24_ ( + .I0(com_cmm_u_cmm_errman_N_49807), + .I1(cfg_err_tlp_cpl_header_5070[24]), + .LO(com_cmm_u_cmm_errman_N_32792_i) + ); + defparam com_cmm_u_cmm_errman_reg_cfg_wr_hdr_6_i_0_0_23_.INIT = 4'h8; + LUT2_L com_cmm_u_cmm_errman_reg_cfg_wr_hdr_6_i_0_0_23_ ( + .I0(com_cmm_u_cmm_errman_N_49807), + .I1(cfg_err_tlp_cpl_header_5070[23]), + .LO(com_cmm_u_cmm_errman_N_32790_i) + ); + defparam com_cmm_u_cmm_errman_reg_cfg_wr_hdr_6_i_0_0_22_.INIT = 4'h8; + LUT2_L com_cmm_u_cmm_errman_reg_cfg_wr_hdr_6_i_0_0_22_ ( + .I0(com_cmm_u_cmm_errman_N_49807), + .I1(cfg_err_tlp_cpl_header_5070[22]), + .LO(com_cmm_u_cmm_errman_N_32788_i) + ); + defparam com_cmm_u_cmm_errman_reg_cfg_wr_hdr_6_i_0_0_21_.INIT = 4'h8; + LUT2_L com_cmm_u_cmm_errman_reg_cfg_wr_hdr_6_i_0_0_21_ ( + .I0(com_cmm_u_cmm_errman_N_49807), + .I1(cfg_err_tlp_cpl_header_5070[21]), + .LO(com_cmm_u_cmm_errman_N_32786_i) + ); + defparam com_cmm_u_cmm_errman_reg_cfg_wr_hdr_6_i_0_0_20_.INIT = 4'h8; + LUT2_L com_cmm_u_cmm_errman_reg_cfg_wr_hdr_6_i_0_0_20_ ( + .I0(com_cmm_u_cmm_errman_N_49807), + .I1(cfg_err_tlp_cpl_header_5070[20]), + .LO(com_cmm_u_cmm_errman_N_32784_i) + ); + defparam com_cmm_u_cmm_errman_reg_cfg_wr_hdr20_0_a2_0_a2_0_a2_0_a2.INIT = 4'h8; + LUT2_L com_cmm_u_cmm_errman_reg_cfg_wr_hdr20_0_a2_0_a2_0_a2_0_a2 ( + .I0(cfg_err_ur_n), + .I1(com_cmm_u_cmm_errman_cfg_is_np_and_cpl_abort), + .LO(com_cmm_u_cmm_errman_reg_cfg_wr_hdr20) + ); + defparam com_cmm_u_cmm_errman_cfg_is_np_and_ur_0_a2_0_a2_0_a2_0_a2.INIT = 4'h2; + LUT2_L com_cmm_u_cmm_errman_cfg_is_np_and_ur_0_a2_0_a2_0_a2_0_a2 ( + .I0(cfg_err_posted_n), + .I1(cfg_err_ur_n), + .LO(com_cmm_u_cmm_errman_cfg_is_np_and_ur) + ); + defparam com_cmm_u_cmm_errman_reg_cfg_wr_hdr_6_i_0_0_47_.INIT = 4'h8; + LUT2_L com_cmm_u_cmm_errman_reg_cfg_wr_hdr_6_i_0_0_47_ ( + .I0(com_cmm_u_cmm_errman_N_49807), + .I1(cfg_err_tlp_cpl_header_5070[47]), + .LO(com_cmm_u_cmm_errman_N_32838_i) + ); + defparam com_cmm_u_cmm_errman_reg_cfg_wr_hdr_6_i_0_0_46_.INIT = 4'h8; + LUT2_L com_cmm_u_cmm_errman_reg_cfg_wr_hdr_6_i_0_0_46_ ( + .I0(com_cmm_u_cmm_errman_N_49807), + .I1(cfg_err_tlp_cpl_header_5070[46]), + .LO(com_cmm_u_cmm_errman_N_32836_i) + ); + defparam com_cmm_u_cmm_errman_reg_cfg_wr_hdr_6_i_0_0_45_.INIT = 4'h8; + LUT2_L com_cmm_u_cmm_errman_reg_cfg_wr_hdr_6_i_0_0_45_ ( + .I0(com_cmm_u_cmm_errman_N_49807), + .I1(cfg_err_tlp_cpl_header_5070[45]), + .LO(com_cmm_u_cmm_errman_N_32834_i) + ); + defparam com_cmm_u_cmm_errman_reg_cfg_wr_hdr_6_i_0_0_44_.INIT = 4'h8; + LUT2_L com_cmm_u_cmm_errman_reg_cfg_wr_hdr_6_i_0_0_44_ ( + .I0(com_cmm_u_cmm_errman_N_49807), + .I1(cfg_err_tlp_cpl_header_5070[44]), + .LO(com_cmm_u_cmm_errman_N_32832_i) + ); + defparam com_cmm_u_cmm_errman_reg_cfg_wr_hdr_6_i_0_0_43_.INIT = 4'h8; + LUT2_L com_cmm_u_cmm_errman_reg_cfg_wr_hdr_6_i_0_0_43_ ( + .I0(com_cmm_u_cmm_errman_N_49807), + .I1(cfg_err_tlp_cpl_header_5070[43]), + .LO(com_cmm_u_cmm_errman_N_32830_i) + ); + defparam com_cmm_u_cmm_errman_reg_cfg_wr_hdr_6_i_0_0_42_.INIT = 4'h8; + LUT2_L com_cmm_u_cmm_errman_reg_cfg_wr_hdr_6_i_0_0_42_ ( + .I0(com_cmm_u_cmm_errman_N_49807), + .I1(cfg_err_tlp_cpl_header_5070[42]), + .LO(com_cmm_u_cmm_errman_N_32828_i) + ); + defparam com_cmm_u_cmm_errman_reg_cfg_wr_hdr_6_i_0_0_41_.INIT = 4'h8; + LUT2_L com_cmm_u_cmm_errman_reg_cfg_wr_hdr_6_i_0_0_41_ ( + .I0(com_cmm_u_cmm_errman_N_49807), + .I1(cfg_err_tlp_cpl_header_5070[41]), + .LO(com_cmm_u_cmm_errman_N_32826_i) + ); + defparam com_cmm_u_cmm_errman_reg_cfg_wr_hdr_6_i_0_0_40_.INIT = 4'h8; + LUT2_L com_cmm_u_cmm_errman_reg_cfg_wr_hdr_6_i_0_0_40_ ( + .I0(com_cmm_u_cmm_errman_N_49807), + .I1(cfg_err_tlp_cpl_header_5070[40]), + .LO(com_cmm_u_cmm_errman_N_32824_i) + ); + defparam com_cmm_u_cmm_errman_reg_cfg_wr_hdr_6_i_0_0_39_.INIT = 4'h8; + LUT2_L com_cmm_u_cmm_errman_reg_cfg_wr_hdr_6_i_0_0_39_ ( + .I0(com_cmm_u_cmm_errman_N_49807), + .I1(cfg_err_tlp_cpl_header_5070[39]), + .LO(com_cmm_u_cmm_errman_N_32822_i) + ); + defparam com_cmm_u_cmm_errman_reg_cfg_wr_hdr_6_i_0_0_38_.INIT = 4'h8; + LUT2_L com_cmm_u_cmm_errman_reg_cfg_wr_hdr_6_i_0_0_38_ ( + .I0(com_cmm_u_cmm_errman_N_49807), + .I1(cfg_err_tlp_cpl_header_5070[38]), + .LO(com_cmm_u_cmm_errman_N_32820_i) + ); + defparam com_cmm_u_cmm_errman_reg_cfg_wr_hdr_6_i_0_0_37_.INIT = 4'h8; + LUT2_L com_cmm_u_cmm_errman_reg_cfg_wr_hdr_6_i_0_0_37_ ( + .I0(com_cmm_u_cmm_errman_N_49807), + .I1(cfg_err_tlp_cpl_header_5070[37]), + .LO(com_cmm_u_cmm_errman_N_32818_i) + ); + defparam com_cmm_u_cmm_errman_reg_cfg_wr_hdr_6_i_0_0_36_.INIT = 4'h8; + LUT2_L com_cmm_u_cmm_errman_reg_cfg_wr_hdr_6_i_0_0_36_ ( + .I0(com_cmm_u_cmm_errman_N_49807), + .I1(cfg_err_tlp_cpl_header_5070[36]), + .LO(com_cmm_u_cmm_errman_N_32816_i) + ); + defparam com_cmm_u_cmm_errman_reg_cfg_wr_hdr_6_i_0_0_35_.INIT = 4'h8; + LUT2_L com_cmm_u_cmm_errman_reg_cfg_wr_hdr_6_i_0_0_35_ ( + .I0(com_cmm_u_cmm_errman_N_49807), + .I1(cfg_err_tlp_cpl_header_5070[35]), + .LO(com_cmm_u_cmm_errman_N_32814_i) + ); + defparam com_cmm_u_cmm_errman_N_68444_i.INIT = 16'hECA0; + LUT4_L com_cmm_u_cmm_errman_N_68444_i ( + .I0(com_cmm_u_cmm_errman_cfg_rd_hdr[14]), + .I1(com_cmm_u_cmm_errman_cmt_rd_hdr[14]), + .I2(com_cmm_u_cmm_errman_cs_is_ftl29), + .I3(com_cmm_u_cmm_errman_cs_is_ftl30), + .LO(com_cmm_u_cmm_errman_N_68444_i_4826) + ); + defparam com_cmm_u_cmm_errman_N_68443_i.INIT = 16'hECA0; + LUT4_L com_cmm_u_cmm_errman_N_68443_i ( + .I0(com_cmm_u_cmm_errman_cfg_rd_hdr[13]), + .I1(com_cmm_u_cmm_errman_cmt_rd_hdr[13]), + .I2(com_cmm_u_cmm_errman_cs_is_ftl29), + .I3(com_cmm_u_cmm_errman_cs_is_ftl30), + .LO(com_cmm_u_cmm_errman_N_68443_i_4827) + ); + defparam com_cmm_u_cmm_errman_N_68442_i.INIT = 16'hECA0; + LUT4_L com_cmm_u_cmm_errman_N_68442_i ( + .I0(com_cmm_u_cmm_errman_cfg_rd_hdr[12]), + .I1(com_cmm_u_cmm_errman_cmt_rd_hdr[12]), + .I2(com_cmm_u_cmm_errman_cs_is_ftl29), + .I3(com_cmm_u_cmm_errman_cs_is_ftl30), + .LO(com_cmm_u_cmm_errman_N_68442_i_4828) + ); + defparam com_cmm_u_cmm_errman_N_68441_i.INIT = 16'hECA0; + LUT4_L com_cmm_u_cmm_errman_N_68441_i ( + .I0(com_cmm_u_cmm_errman_cfg_rd_hdr[11]), + .I1(com_cmm_u_cmm_errman_cmt_rd_hdr[11]), + .I2(com_cmm_u_cmm_errman_cs_is_ftl29), + .I3(com_cmm_u_cmm_errman_cs_is_ftl30), + .LO(com_cmm_u_cmm_errman_N_68441_i_4829) + ); + defparam com_cmm_u_cmm_errman_N_68440_i.INIT = 16'hECA0; + LUT4_L com_cmm_u_cmm_errman_N_68440_i ( + .I0(com_cmm_u_cmm_errman_cfg_rd_hdr[10]), + .I1(com_cmm_u_cmm_errman_cmt_rd_hdr[10]), + .I2(com_cmm_u_cmm_errman_cs_is_ftl29), + .I3(com_cmm_u_cmm_errman_cs_is_ftl30), + .LO(com_cmm_u_cmm_errman_N_68440_i_4830) + ); + defparam com_cmm_u_cmm_errman_N_68439_i.INIT = 16'hECA0; + LUT4_L com_cmm_u_cmm_errman_N_68439_i ( + .I0(com_cmm_u_cmm_errman_cfg_rd_hdr[9]), + .I1(com_cmm_u_cmm_errman_cmt_rd_hdr[9]), + .I2(com_cmm_u_cmm_errman_cs_is_ftl29), + .I3(com_cmm_u_cmm_errman_cs_is_ftl30), + .LO(com_cmm_u_cmm_errman_N_68439_i_4831) + ); + defparam com_cmm_u_cmm_errman_N_68438_i.INIT = 16'hECA0; + LUT4_L com_cmm_u_cmm_errman_N_68438_i ( + .I0(com_cmm_u_cmm_errman_cfg_rd_hdr[8]), + .I1(com_cmm_u_cmm_errman_cmt_rd_hdr[8]), + .I2(com_cmm_u_cmm_errman_cs_is_ftl29), + .I3(com_cmm_u_cmm_errman_cs_is_ftl30), + .LO(com_cmm_u_cmm_errman_N_68438_i_4832) + ); + defparam com_cmm_u_cmm_errman_N_68437_i.INIT = 16'hECA0; + LUT4_L com_cmm_u_cmm_errman_N_68437_i ( + .I0(com_cmm_u_cmm_errman_cfg_rd_hdr[7]), + .I1(com_cmm_u_cmm_errman_cmt_rd_hdr[7]), + .I2(com_cmm_u_cmm_errman_cs_is_ftl29), + .I3(com_cmm_u_cmm_errman_cs_is_ftl30), + .LO(com_cmm_u_cmm_errman_N_68437_i_4833) + ); + defparam com_cmm_u_cmm_errman_N_68436_i.INIT = 16'hECA0; + LUT4_L com_cmm_u_cmm_errman_N_68436_i ( + .I0(com_cmm_u_cmm_errman_cfg_rd_hdr[6]), + .I1(com_cmm_u_cmm_errman_cmt_rd_hdr[6]), + .I2(com_cmm_u_cmm_errman_cs_is_ftl29), + .I3(com_cmm_u_cmm_errman_cs_is_ftl30), + .LO(com_cmm_u_cmm_errman_N_68436_i_4834) + ); + defparam com_cmm_u_cmm_errman_N_68435_i.INIT = 16'hECA0; + LUT4_L com_cmm_u_cmm_errman_N_68435_i ( + .I0(com_cmm_u_cmm_errman_cfg_rd_hdr[5]), + .I1(com_cmm_u_cmm_errman_cmt_rd_hdr[5]), + .I2(com_cmm_u_cmm_errman_cs_is_ftl29), + .I3(com_cmm_u_cmm_errman_cs_is_ftl30), + .LO(com_cmm_u_cmm_errman_N_68435_i_4835) + ); + defparam com_cmm_u_cmm_errman_N_68434_i.INIT = 16'hECA0; + LUT4_L com_cmm_u_cmm_errman_N_68434_i ( + .I0(com_cmm_u_cmm_errman_cfg_rd_hdr[4]), + .I1(com_cmm_u_cmm_errman_cmt_rd_hdr[4]), + .I2(com_cmm_u_cmm_errman_cs_is_ftl29), + .I3(com_cmm_u_cmm_errman_cs_is_ftl30), + .LO(com_cmm_u_cmm_errman_N_68434_i_4836) + ); + defparam com_cmm_u_cmm_errman_N_68433_i.INIT = 16'hECA0; + LUT4_L com_cmm_u_cmm_errman_N_68433_i ( + .I0(com_cmm_u_cmm_errman_cfg_rd_hdr[3]), + .I1(com_cmm_u_cmm_errman_cmt_rd_hdr[3]), + .I2(com_cmm_u_cmm_errman_cs_is_ftl29), + .I3(com_cmm_u_cmm_errman_cs_is_ftl30), + .LO(com_cmm_u_cmm_errman_N_68433_i_4837) + ); + defparam com_cmm_u_cmm_errman_N_68432_i.INIT = 16'hECA0; + LUT4_L com_cmm_u_cmm_errman_N_68432_i ( + .I0(com_cmm_u_cmm_errman_cfg_rd_hdr[2]), + .I1(com_cmm_u_cmm_errman_cmt_rd_hdr[2]), + .I2(com_cmm_u_cmm_errman_cs_is_ftl29), + .I3(com_cmm_u_cmm_errman_cs_is_ftl30), + .LO(com_cmm_u_cmm_errman_N_68432_i_4838) + ); + defparam com_cmm_u_cmm_errman_N_68431_i.INIT = 16'hECA0; + LUT4_L com_cmm_u_cmm_errman_N_68431_i ( + .I0(com_cmm_u_cmm_errman_cfg_rd_hdr[1]), + .I1(com_cmm_u_cmm_errman_cmt_rd_hdr[1]), + .I2(com_cmm_u_cmm_errman_cs_is_ftl29), + .I3(com_cmm_u_cmm_errman_cs_is_ftl30), + .LO(com_cmm_u_cmm_errman_N_68431_i_4839) + ); + defparam com_cmm_u_cmm_errman_N_68430_i.INIT = 16'hECA0; + LUT4_L com_cmm_u_cmm_errman_N_68430_i ( + .I0(com_cmm_u_cmm_errman_cfg_rd_hdr[0]), + .I1(com_cmm_u_cmm_errman_cmt_rd_hdr[0]), + .I2(com_cmm_u_cmm_errman_cs_is_ftl29), + .I3(com_cmm_u_cmm_errman_cs_is_ftl30), + .LO(com_cmm_u_cmm_errman_N_68430_i_4840) + ); + defparam com_cmm_u_cmm_errman_N_68459_i.INIT = 16'hECA0; + LUT4_L com_cmm_u_cmm_errman_N_68459_i ( + .I0(com_cmm_u_cmm_errman_cfg_rd_hdr[29]), + .I1(com_cmm_u_cmm_errman_cmt_rd_hdr[29]), + .I2(com_cmm_u_cmm_errman_cs_is_ftl29), + .I3(com_cmm_u_cmm_errman_cs_is_ftl30), + .LO(com_cmm_u_cmm_errman_N_68459_i_4841) + ); + defparam com_cmm_u_cmm_errman_N_68458_i.INIT = 16'hECA0; + LUT4_L com_cmm_u_cmm_errman_N_68458_i ( + .I0(com_cmm_u_cmm_errman_cfg_rd_hdr[28]), + .I1(com_cmm_u_cmm_errman_cmt_rd_hdr[28]), + .I2(com_cmm_u_cmm_errman_cs_is_ftl29), + .I3(com_cmm_u_cmm_errman_cs_is_ftl30), + .LO(com_cmm_u_cmm_errman_N_68458_i_4842) + ); + defparam com_cmm_u_cmm_errman_N_68457_i.INIT = 16'hECA0; + LUT4_L com_cmm_u_cmm_errman_N_68457_i ( + .I0(com_cmm_u_cmm_errman_cfg_rd_hdr[27]), + .I1(com_cmm_u_cmm_errman_cmt_rd_hdr[27]), + .I2(com_cmm_u_cmm_errman_cs_is_ftl29), + .I3(com_cmm_u_cmm_errman_cs_is_ftl30), + .LO(com_cmm_u_cmm_errman_N_68457_i_4843) + ); + defparam com_cmm_u_cmm_errman_N_68456_i.INIT = 16'hECA0; + LUT4_L com_cmm_u_cmm_errman_N_68456_i ( + .I0(com_cmm_u_cmm_errman_cfg_rd_hdr[26]), + .I1(com_cmm_u_cmm_errman_cmt_rd_hdr[26]), + .I2(com_cmm_u_cmm_errman_cs_is_ftl29), + .I3(com_cmm_u_cmm_errman_cs_is_ftl30), + .LO(com_cmm_u_cmm_errman_N_68456_i_4844) + ); + defparam com_cmm_u_cmm_errman_N_68455_i.INIT = 16'hECA0; + LUT4_L com_cmm_u_cmm_errman_N_68455_i ( + .I0(com_cmm_u_cmm_errman_cfg_rd_hdr[25]), + .I1(com_cmm_u_cmm_errman_cmt_rd_hdr[25]), + .I2(com_cmm_u_cmm_errman_cs_is_ftl29), + .I3(com_cmm_u_cmm_errman_cs_is_ftl30), + .LO(com_cmm_u_cmm_errman_N_68455_i_4845) + ); + defparam com_cmm_u_cmm_errman_N_68454_i.INIT = 16'hECA0; + LUT4_L com_cmm_u_cmm_errman_N_68454_i ( + .I0(com_cmm_u_cmm_errman_cfg_rd_hdr[24]), + .I1(com_cmm_u_cmm_errman_cmt_rd_hdr[24]), + .I2(com_cmm_u_cmm_errman_cs_is_ftl29), + .I3(com_cmm_u_cmm_errman_cs_is_ftl30), + .LO(com_cmm_u_cmm_errman_N_68454_i_4846) + ); + defparam com_cmm_u_cmm_errman_N_68453_i.INIT = 16'hECA0; + LUT4_L com_cmm_u_cmm_errman_N_68453_i ( + .I0(com_cmm_u_cmm_errman_cfg_rd_hdr[23]), + .I1(com_cmm_u_cmm_errman_cmt_rd_hdr[23]), + .I2(com_cmm_u_cmm_errman_cs_is_ftl29), + .I3(com_cmm_u_cmm_errman_cs_is_ftl30), + .LO(com_cmm_u_cmm_errman_N_68453_i_4847) + ); + defparam com_cmm_u_cmm_errman_N_68452_i.INIT = 16'hECA0; + LUT4_L com_cmm_u_cmm_errman_N_68452_i ( + .I0(com_cmm_u_cmm_errman_cfg_rd_hdr[22]), + .I1(com_cmm_u_cmm_errman_cmt_rd_hdr[22]), + .I2(com_cmm_u_cmm_errman_cs_is_ftl29), + .I3(com_cmm_u_cmm_errman_cs_is_ftl30), + .LO(com_cmm_u_cmm_errman_N_68452_i_4848) + ); + defparam com_cmm_u_cmm_errman_N_68451_i.INIT = 16'hECA0; + LUT4_L com_cmm_u_cmm_errman_N_68451_i ( + .I0(com_cmm_u_cmm_errman_cfg_rd_hdr[21]), + .I1(com_cmm_u_cmm_errman_cmt_rd_hdr[21]), + .I2(com_cmm_u_cmm_errman_cs_is_ftl29), + .I3(com_cmm_u_cmm_errman_cs_is_ftl30), + .LO(com_cmm_u_cmm_errman_N_68451_i_4849) + ); + defparam com_cmm_u_cmm_errman_N_68450_i.INIT = 16'hECA0; + LUT4_L com_cmm_u_cmm_errman_N_68450_i ( + .I0(com_cmm_u_cmm_errman_cfg_rd_hdr[20]), + .I1(com_cmm_u_cmm_errman_cmt_rd_hdr[20]), + .I2(com_cmm_u_cmm_errman_cs_is_ftl29), + .I3(com_cmm_u_cmm_errman_cs_is_ftl30), + .LO(com_cmm_u_cmm_errman_N_68450_i_4850) + ); + defparam com_cmm_u_cmm_errman_N_68449_i.INIT = 16'hECA0; + LUT4_L com_cmm_u_cmm_errman_N_68449_i ( + .I0(com_cmm_u_cmm_errman_cfg_rd_hdr[19]), + .I1(com_cmm_u_cmm_errman_cmt_rd_hdr[19]), + .I2(com_cmm_u_cmm_errman_cs_is_ftl29), + .I3(com_cmm_u_cmm_errman_cs_is_ftl30), + .LO(com_cmm_u_cmm_errman_N_68449_i_4851) + ); + defparam com_cmm_u_cmm_errman_N_68448_i.INIT = 16'hECA0; + LUT4_L com_cmm_u_cmm_errman_N_68448_i ( + .I0(com_cmm_u_cmm_errman_cfg_rd_hdr[18]), + .I1(com_cmm_u_cmm_errman_cmt_rd_hdr[18]), + .I2(com_cmm_u_cmm_errman_cs_is_ftl29), + .I3(com_cmm_u_cmm_errman_cs_is_ftl30), + .LO(com_cmm_u_cmm_errman_N_68448_i_4852) + ); + defparam com_cmm_u_cmm_errman_N_68447_i.INIT = 16'hECA0; + LUT4_L com_cmm_u_cmm_errman_N_68447_i ( + .I0(com_cmm_u_cmm_errman_cfg_rd_hdr[17]), + .I1(com_cmm_u_cmm_errman_cmt_rd_hdr[17]), + .I2(com_cmm_u_cmm_errman_cs_is_ftl29), + .I3(com_cmm_u_cmm_errman_cs_is_ftl30), + .LO(com_cmm_u_cmm_errman_N_68447_i_4853) + ); + defparam com_cmm_u_cmm_errman_N_68446_i.INIT = 16'hECA0; + LUT4_L com_cmm_u_cmm_errman_N_68446_i ( + .I0(com_cmm_u_cmm_errman_cfg_rd_hdr[16]), + .I1(com_cmm_u_cmm_errman_cmt_rd_hdr[16]), + .I2(com_cmm_u_cmm_errman_cs_is_ftl29), + .I3(com_cmm_u_cmm_errman_cs_is_ftl30), + .LO(com_cmm_u_cmm_errman_N_68446_i_4854) + ); + defparam com_cmm_u_cmm_errman_N_68445_i.INIT = 16'hECA0; + LUT4_L com_cmm_u_cmm_errman_N_68445_i ( + .I0(com_cmm_u_cmm_errman_cfg_rd_hdr[15]), + .I1(com_cmm_u_cmm_errman_cmt_rd_hdr[15]), + .I2(com_cmm_u_cmm_errman_cs_is_ftl29), + .I3(com_cmm_u_cmm_errman_cs_is_ftl30), + .LO(com_cmm_u_cmm_errman_N_68445_i_4855) + ); + defparam com_cmm_u_cmm_errman_N_68474_i.INIT = 16'hECA0; + LUT4_L com_cmm_u_cmm_errman_N_68474_i ( + .I0(com_cmm_u_cmm_errman_cfg_rd_hdr[44]), + .I1(com_cmm_u_cmm_errman_cmt_rd_hdr[44]), + .I2(com_cmm_u_cmm_errman_cs_is_ftl29), + .I3(com_cmm_u_cmm_errman_cs_is_ftl30), + .LO(com_cmm_u_cmm_errman_N_68474_i_4856) + ); + defparam com_cmm_u_cmm_errman_N_68473_i.INIT = 16'hECA0; + LUT4_L com_cmm_u_cmm_errman_N_68473_i ( + .I0(com_cmm_u_cmm_errman_cfg_rd_hdr[43]), + .I1(com_cmm_u_cmm_errman_cmt_rd_hdr[43]), + .I2(com_cmm_u_cmm_errman_cs_is_ftl29), + .I3(com_cmm_u_cmm_errman_cs_is_ftl30), + .LO(com_cmm_u_cmm_errman_N_68473_i_4857) + ); + defparam com_cmm_u_cmm_errman_N_68472_i.INIT = 16'hECA0; + LUT4_L com_cmm_u_cmm_errman_N_68472_i ( + .I0(com_cmm_u_cmm_errman_cfg_rd_hdr[42]), + .I1(com_cmm_u_cmm_errman_cmt_rd_hdr[42]), + .I2(com_cmm_u_cmm_errman_cs_is_ftl29), + .I3(com_cmm_u_cmm_errman_cs_is_ftl30), + .LO(com_cmm_u_cmm_errman_N_68472_i_4858) + ); + defparam com_cmm_u_cmm_errman_N_68471_i.INIT = 16'hECA0; + LUT4_L com_cmm_u_cmm_errman_N_68471_i ( + .I0(com_cmm_u_cmm_errman_cfg_rd_hdr[41]), + .I1(com_cmm_u_cmm_errman_cmt_rd_hdr[41]), + .I2(com_cmm_u_cmm_errman_cs_is_ftl29), + .I3(com_cmm_u_cmm_errman_cs_is_ftl30), + .LO(com_cmm_u_cmm_errman_N_68471_i_4859) + ); + defparam com_cmm_u_cmm_errman_N_68470_i.INIT = 16'hECA0; + LUT4_L com_cmm_u_cmm_errman_N_68470_i ( + .I0(com_cmm_u_cmm_errman_cfg_rd_hdr[40]), + .I1(com_cmm_u_cmm_errman_cmt_rd_hdr[40]), + .I2(com_cmm_u_cmm_errman_cs_is_ftl29), + .I3(com_cmm_u_cmm_errman_cs_is_ftl30), + .LO(com_cmm_u_cmm_errman_N_68470_i_4860) + ); + defparam com_cmm_u_cmm_errman_N_68469_i.INIT = 16'hECA0; + LUT4_L com_cmm_u_cmm_errman_N_68469_i ( + .I0(com_cmm_u_cmm_errman_cfg_rd_hdr[39]), + .I1(com_cmm_u_cmm_errman_cmt_rd_hdr[39]), + .I2(com_cmm_u_cmm_errman_cs_is_ftl29), + .I3(com_cmm_u_cmm_errman_cs_is_ftl30), + .LO(com_cmm_u_cmm_errman_N_68469_i_4861) + ); + defparam com_cmm_u_cmm_errman_N_68468_i.INIT = 16'hECA0; + LUT4_L com_cmm_u_cmm_errman_N_68468_i ( + .I0(com_cmm_u_cmm_errman_cfg_rd_hdr[38]), + .I1(com_cmm_u_cmm_errman_cmt_rd_hdr[38]), + .I2(com_cmm_u_cmm_errman_cs_is_ftl29), + .I3(com_cmm_u_cmm_errman_cs_is_ftl30), + .LO(com_cmm_u_cmm_errman_N_68468_i_4862) + ); + defparam com_cmm_u_cmm_errman_N_68467_i.INIT = 16'hECA0; + LUT4_L com_cmm_u_cmm_errman_N_68467_i ( + .I0(com_cmm_u_cmm_errman_cfg_rd_hdr[37]), + .I1(com_cmm_u_cmm_errman_cmt_rd_hdr[37]), + .I2(com_cmm_u_cmm_errman_cs_is_ftl29), + .I3(com_cmm_u_cmm_errman_cs_is_ftl30), + .LO(com_cmm_u_cmm_errman_N_68467_i_4863) + ); + defparam com_cmm_u_cmm_errman_N_68466_i.INIT = 16'hECA0; + LUT4_L com_cmm_u_cmm_errman_N_68466_i ( + .I0(com_cmm_u_cmm_errman_cfg_rd_hdr[36]), + .I1(com_cmm_u_cmm_errman_cmt_rd_hdr[36]), + .I2(com_cmm_u_cmm_errman_cs_is_ftl29), + .I3(com_cmm_u_cmm_errman_cs_is_ftl30), + .LO(com_cmm_u_cmm_errman_N_68466_i_4864) + ); + defparam com_cmm_u_cmm_errman_N_68465_i.INIT = 16'hECA0; + LUT4_L com_cmm_u_cmm_errman_N_68465_i ( + .I0(com_cmm_u_cmm_errman_cfg_rd_hdr[35]), + .I1(com_cmm_u_cmm_errman_cmt_rd_hdr[35]), + .I2(com_cmm_u_cmm_errman_cs_is_ftl29), + .I3(com_cmm_u_cmm_errman_cs_is_ftl30), + .LO(com_cmm_u_cmm_errman_N_68465_i_4865) + ); + defparam com_cmm_u_cmm_errman_N_68464_i.INIT = 16'hECA0; + LUT4_L com_cmm_u_cmm_errman_N_68464_i ( + .I0(com_cmm_u_cmm_errman_cfg_rd_hdr[34]), + .I1(com_cmm_u_cmm_errman_cmt_rd_hdr[34]), + .I2(com_cmm_u_cmm_errman_cs_is_ftl29), + .I3(com_cmm_u_cmm_errman_cs_is_ftl30), + .LO(com_cmm_u_cmm_errman_N_68464_i_4866) + ); + defparam com_cmm_u_cmm_errman_N_68463_i.INIT = 16'hECA0; + LUT4_L com_cmm_u_cmm_errman_N_68463_i ( + .I0(com_cmm_u_cmm_errman_cfg_rd_hdr[33]), + .I1(com_cmm_u_cmm_errman_cmt_rd_hdr[33]), + .I2(com_cmm_u_cmm_errman_cs_is_ftl29), + .I3(com_cmm_u_cmm_errman_cs_is_ftl30), + .LO(com_cmm_u_cmm_errman_N_68463_i_4867) + ); + defparam com_cmm_u_cmm_errman_N_68462_i.INIT = 16'hECA0; + LUT4_L com_cmm_u_cmm_errman_N_68462_i ( + .I0(com_cmm_u_cmm_errman_cfg_rd_hdr[32]), + .I1(com_cmm_u_cmm_errman_cmt_rd_hdr[32]), + .I2(com_cmm_u_cmm_errman_cs_is_ftl29), + .I3(com_cmm_u_cmm_errman_cs_is_ftl30), + .LO(com_cmm_u_cmm_errman_N_68462_i_4868) + ); + defparam com_cmm_u_cmm_errman_N_68461_i.INIT = 16'hECA0; + LUT4_L com_cmm_u_cmm_errman_N_68461_i ( + .I0(com_cmm_u_cmm_errman_cfg_rd_hdr[31]), + .I1(com_cmm_u_cmm_errman_cmt_rd_hdr[31]), + .I2(com_cmm_u_cmm_errman_cs_is_ftl29), + .I3(com_cmm_u_cmm_errman_cs_is_ftl30), + .LO(com_cmm_u_cmm_errman_N_68461_i_4869) + ); + defparam com_cmm_u_cmm_errman_N_68460_i.INIT = 16'hECA0; + LUT4_L com_cmm_u_cmm_errman_N_68460_i ( + .I0(com_cmm_u_cmm_errman_cfg_rd_hdr[30]), + .I1(com_cmm_u_cmm_errman_cmt_rd_hdr[30]), + .I2(com_cmm_u_cmm_errman_cs_is_ftl29), + .I3(com_cmm_u_cmm_errman_cs_is_ftl30), + .LO(com_cmm_u_cmm_errman_N_68460_i_4870) + ); + defparam com_cmm_u_cmm_errman_reg_cmt_wr_hdr_5_0_a2_0_a2_0_a2_0_a2_9_.INIT = 4'h8; + LUT2_L com_cmm_u_cmm_errman_reg_cmt_wr_hdr_5_0_a2_0_a2_0_a2_0_a2_9_ ( + .I0(com_cmm_u_cmm_errman_N_48855_i), + .I1(com_cmmt_err_tlp_hdr[9]), + .LO(com_cmm_u_cmm_errman_reg_cmt_wr_hdr_5[9]) + ); + defparam com_cmm_u_cmm_errman_reg_cmt_wr_hdr_5_0_a2_0_a2_0_a2_0_a2_8_.INIT = 4'h8; + LUT2_L com_cmm_u_cmm_errman_reg_cmt_wr_hdr_5_0_a2_0_a2_0_a2_0_a2_8_ ( + .I0(com_cmm_u_cmm_errman_N_48855_i), + .I1(com_cmmt_err_tlp_hdr[8]), + .LO(com_cmm_u_cmm_errman_reg_cmt_wr_hdr_5[8]) + ); + defparam com_cmm_u_cmm_errman_reg_cmt_wr_hdr_5_0_a2_0_a2_0_a2_0_a2_7_.INIT = 4'h8; + LUT2_L com_cmm_u_cmm_errman_reg_cmt_wr_hdr_5_0_a2_0_a2_0_a2_0_a2_7_ ( + .I0(com_cmm_u_cmm_errman_N_48855_i), + .I1(com_cmmt_err_tlp_hdr[7]), + .LO(com_cmm_u_cmm_errman_reg_cmt_wr_hdr_5[7]) + ); + defparam com_cmm_u_cmm_errman_reg_cmt_wr_hdr_5_0_a2_0_a2_0_a2_0_a2_6_.INIT = 4'h8; + LUT2_L com_cmm_u_cmm_errman_reg_cmt_wr_hdr_5_0_a2_0_a2_0_a2_0_a2_6_ ( + .I0(com_cmm_u_cmm_errman_N_48855_i), + .I1(com_cmmt_err_tlp_hdr[6]), + .LO(com_cmm_u_cmm_errman_reg_cmt_wr_hdr_5[6]) + ); + defparam com_cmm_u_cmm_errman_reg_cmt_wr_hdr_5_0_a2_0_a2_0_a2_0_a2_5_.INIT = 4'h8; + LUT2_L com_cmm_u_cmm_errman_reg_cmt_wr_hdr_5_0_a2_0_a2_0_a2_0_a2_5_ ( + .I0(com_cmm_u_cmm_errman_N_48855_i), + .I1(com_cmmt_err_tlp_hdr[5]), + .LO(com_cmm_u_cmm_errman_reg_cmt_wr_hdr_5[5]) + ); + defparam com_cmm_u_cmm_errman_reg_cmt_wr_hdr_5_0_a2_0_a2_0_a2_0_a2_4_.INIT = 4'h8; + LUT2_L com_cmm_u_cmm_errman_reg_cmt_wr_hdr_5_0_a2_0_a2_0_a2_0_a2_4_ ( + .I0(com_cmm_u_cmm_errman_N_48855_i), + .I1(com_cmmt_err_tlp_hdr[4]), + .LO(com_cmm_u_cmm_errman_reg_cmt_wr_hdr_5[4]) + ); + defparam com_cmm_u_cmm_errman_reg_cmt_wr_hdr_5_0_a2_0_a2_0_a2_0_a2_3_.INIT = 4'h8; + LUT2_L com_cmm_u_cmm_errman_reg_cmt_wr_hdr_5_0_a2_0_a2_0_a2_0_a2_3_ ( + .I0(com_cmm_u_cmm_errman_N_48855_i), + .I1(com_cmmt_err_tlp_hdr[3]), + .LO(com_cmm_u_cmm_errman_reg_cmt_wr_hdr_5[3]) + ); + defparam com_cmm_u_cmm_errman_reg_cmt_wr_hdr_5_0_a2_0_a2_0_a2_0_a2_2_.INIT = 4'h8; + LUT2_L com_cmm_u_cmm_errman_reg_cmt_wr_hdr_5_0_a2_0_a2_0_a2_0_a2_2_ ( + .I0(com_cmm_u_cmm_errman_N_48855_i), + .I1(com_cmmt_err_tlp_hdr[2]), + .LO(com_cmm_u_cmm_errman_reg_cmt_wr_hdr_5[2]) + ); + defparam com_cmm_u_cmm_errman_reg_cmt_wr_hdr_5_0_a2_0_a2_0_a2_0_a2_1_.INIT = 4'h8; + LUT2_L com_cmm_u_cmm_errman_reg_cmt_wr_hdr_5_0_a2_0_a2_0_a2_0_a2_1_ ( + .I0(com_cmm_u_cmm_errman_N_48855_i), + .I1(com_cmmt_err_tlp_hdr[1]), + .LO(com_cmm_u_cmm_errman_reg_cmt_wr_hdr_5[1]) + ); + defparam com_cmm_u_cmm_errman_reg_cmt_wr_hdr_5_0_a2_0_a2_0_a2_0_a2_0_.INIT = 4'h8; + LUT2_L com_cmm_u_cmm_errman_reg_cmt_wr_hdr_5_0_a2_0_a2_0_a2_0_a2_0_ ( + .I0(com_cmm_u_cmm_errman_N_48855_i), + .I1(com_cmmt_err_tlp_hdr[0]), + .LO(com_cmm_u_cmm_errman_reg_cmt_wr_hdr_5[0]) + ); + defparam com_cmm_u_cmm_errman_N_68479_i.INIT = 16'hECA0; + LUT4_L com_cmm_u_cmm_errman_N_68479_i ( + .I0(com_cmm_u_cmm_errman_cfg_rd_hdr[49]), + .I1(com_cmm_u_cmm_errman_cmt_rd_hdr[49]), + .I2(com_cmm_u_cmm_errman_cs_is_ftl29), + .I3(com_cmm_u_cmm_errman_cs_is_ftl30), + .LO(com_cmm_u_cmm_errman_N_68479_i_4871) + ); + defparam com_cmm_u_cmm_errman_N_68478_i.INIT = 16'hECA0; + LUT4_L com_cmm_u_cmm_errman_N_68478_i ( + .I0(com_cmm_u_cmm_errman_cfg_rd_hdr[48]), + .I1(com_cmm_u_cmm_errman_cmt_rd_hdr[48]), + .I2(com_cmm_u_cmm_errman_cs_is_ftl29), + .I3(com_cmm_u_cmm_errman_cs_is_ftl30), + .LO(com_cmm_u_cmm_errman_N_68478_i_4872) + ); + defparam com_cmm_u_cmm_errman_N_68477_i.INIT = 16'hECA0; + LUT4_L com_cmm_u_cmm_errman_N_68477_i ( + .I0(com_cmm_u_cmm_errman_cfg_rd_hdr[47]), + .I1(com_cmm_u_cmm_errman_cmt_rd_hdr[47]), + .I2(com_cmm_u_cmm_errman_cs_is_ftl29), + .I3(com_cmm_u_cmm_errman_cs_is_ftl30), + .LO(com_cmm_u_cmm_errman_N_68477_i_4873) + ); + defparam com_cmm_u_cmm_errman_N_68476_i.INIT = 16'hECA0; + LUT4_L com_cmm_u_cmm_errman_N_68476_i ( + .I0(com_cmm_u_cmm_errman_cfg_rd_hdr[46]), + .I1(com_cmm_u_cmm_errman_cmt_rd_hdr[46]), + .I2(com_cmm_u_cmm_errman_cs_is_ftl29), + .I3(com_cmm_u_cmm_errman_cs_is_ftl30), + .LO(com_cmm_u_cmm_errman_N_68476_i_4874) + ); + defparam com_cmm_u_cmm_errman_N_68475_i.INIT = 16'hECA0; + LUT4_L com_cmm_u_cmm_errman_N_68475_i ( + .I0(com_cmm_u_cmm_errman_cfg_rd_hdr[45]), + .I1(com_cmm_u_cmm_errman_cmt_rd_hdr[45]), + .I2(com_cmm_u_cmm_errman_cs_is_ftl29), + .I3(com_cmm_u_cmm_errman_cs_is_ftl30), + .LO(com_cmm_u_cmm_errman_N_68475_i_4875) + ); + defparam com_cmm_u_cmm_errman_reg_cmt_wr_hdr_5_0_a2_0_a2_0_a2_0_a2_24_.INIT = 4'h8; + LUT2_L com_cmm_u_cmm_errman_reg_cmt_wr_hdr_5_0_a2_0_a2_0_a2_0_a2_24_ ( + .I0(com_cmm_u_cmm_errman_N_48855_i), + .I1(com_cmmt_err_tlp_hdr[24]), + .LO(com_cmm_u_cmm_errman_reg_cmt_wr_hdr_5[24]) + ); + defparam com_cmm_u_cmm_errman_reg_cmt_wr_hdr_5_0_a2_0_a2_0_a2_0_a2_23_.INIT = 4'h8; + LUT2_L com_cmm_u_cmm_errman_reg_cmt_wr_hdr_5_0_a2_0_a2_0_a2_0_a2_23_ ( + .I0(com_cmm_u_cmm_errman_N_48855_i), + .I1(com_cmmt_err_tlp_hdr[23]), + .LO(com_cmm_u_cmm_errman_reg_cmt_wr_hdr_5[23]) + ); + defparam com_cmm_u_cmm_errman_reg_cmt_wr_hdr_5_0_a2_0_a2_0_a2_0_a2_22_.INIT = 4'h8; + LUT2_L com_cmm_u_cmm_errman_reg_cmt_wr_hdr_5_0_a2_0_a2_0_a2_0_a2_22_ ( + .I0(com_cmm_u_cmm_errman_N_48855_i), + .I1(com_cmmt_err_tlp_hdr[22]), + .LO(com_cmm_u_cmm_errman_reg_cmt_wr_hdr_5[22]) + ); + defparam com_cmm_u_cmm_errman_reg_cmt_wr_hdr_5_0_a2_0_a2_0_a2_0_a2_21_.INIT = 4'h8; + LUT2_L com_cmm_u_cmm_errman_reg_cmt_wr_hdr_5_0_a2_0_a2_0_a2_0_a2_21_ ( + .I0(com_cmm_u_cmm_errman_N_48855_i), + .I1(com_cmmt_err_tlp_hdr[21]), + .LO(com_cmm_u_cmm_errman_reg_cmt_wr_hdr_5[21]) + ); + defparam com_cmm_u_cmm_errman_reg_cmt_wr_hdr_5_0_a2_0_a2_0_a2_0_a2_20_.INIT = 4'h8; + LUT2_L com_cmm_u_cmm_errman_reg_cmt_wr_hdr_5_0_a2_0_a2_0_a2_0_a2_20_ ( + .I0(com_cmm_u_cmm_errman_N_48855_i), + .I1(com_cmmt_err_tlp_hdr[20]), + .LO(com_cmm_u_cmm_errman_reg_cmt_wr_hdr_5[20]) + ); + defparam com_cmm_u_cmm_errman_reg_cmt_wr_hdr_5_0_a2_0_a2_0_a2_0_a2_19_.INIT = 4'h8; + LUT2_L com_cmm_u_cmm_errman_reg_cmt_wr_hdr_5_0_a2_0_a2_0_a2_0_a2_19_ ( + .I0(com_cmm_u_cmm_errman_N_48855_i), + .I1(com_cmmt_err_tlp_hdr[19]), + .LO(com_cmm_u_cmm_errman_reg_cmt_wr_hdr_5[19]) + ); + defparam com_cmm_u_cmm_errman_reg_cmt_wr_hdr_5_0_a2_0_a2_0_a2_0_a2_18_.INIT = 4'h8; + LUT2_L com_cmm_u_cmm_errman_reg_cmt_wr_hdr_5_0_a2_0_a2_0_a2_0_a2_18_ ( + .I0(com_cmm_u_cmm_errman_N_48855_i), + .I1(com_cmmt_err_tlp_hdr[18]), + .LO(com_cmm_u_cmm_errman_reg_cmt_wr_hdr_5[18]) + ); + defparam com_cmm_u_cmm_errman_reg_cmt_wr_hdr_5_0_a2_0_a2_0_a2_0_a2_17_.INIT = 4'h8; + LUT2_L com_cmm_u_cmm_errman_reg_cmt_wr_hdr_5_0_a2_0_a2_0_a2_0_a2_17_ ( + .I0(com_cmm_u_cmm_errman_N_48855_i), + .I1(com_cmmt_err_tlp_hdr[17]), + .LO(com_cmm_u_cmm_errman_reg_cmt_wr_hdr_5[17]) + ); + defparam com_cmm_u_cmm_errman_reg_cmt_wr_hdr_5_0_a2_0_a2_0_a2_0_a2_16_.INIT = 4'h8; + LUT2_L com_cmm_u_cmm_errman_reg_cmt_wr_hdr_5_0_a2_0_a2_0_a2_0_a2_16_ ( + .I0(com_cmm_u_cmm_errman_N_48855_i), + .I1(com_cmmt_err_tlp_hdr[16]), + .LO(com_cmm_u_cmm_errman_reg_cmt_wr_hdr_5[16]) + ); + defparam com_cmm_u_cmm_errman_reg_cmt_wr_hdr_5_0_a2_0_a2_0_a2_0_a2_15_.INIT = 4'h8; + LUT2_L com_cmm_u_cmm_errman_reg_cmt_wr_hdr_5_0_a2_0_a2_0_a2_0_a2_15_ ( + .I0(com_cmm_u_cmm_errman_N_48855_i), + .I1(com_cmmt_err_tlp_hdr[15]), + .LO(com_cmm_u_cmm_errman_reg_cmt_wr_hdr_5[15]) + ); + defparam com_cmm_u_cmm_errman_reg_cmt_wr_hdr_5_0_a2_0_a2_0_a2_0_a2_14_.INIT = 4'h8; + LUT2_L com_cmm_u_cmm_errman_reg_cmt_wr_hdr_5_0_a2_0_a2_0_a2_0_a2_14_ ( + .I0(com_cmm_u_cmm_errman_N_48855_i), + .I1(com_cmmt_err_tlp_hdr[14]), + .LO(com_cmm_u_cmm_errman_reg_cmt_wr_hdr_5[14]) + ); + defparam com_cmm_u_cmm_errman_reg_cmt_wr_hdr_5_0_a2_0_a2_0_a2_0_a2_13_.INIT = 4'h8; + LUT2_L com_cmm_u_cmm_errman_reg_cmt_wr_hdr_5_0_a2_0_a2_0_a2_0_a2_13_ ( + .I0(com_cmm_u_cmm_errman_N_48855_i), + .I1(com_cmmt_err_tlp_hdr[13]), + .LO(com_cmm_u_cmm_errman_reg_cmt_wr_hdr_5[13]) + ); + defparam com_cmm_u_cmm_errman_reg_cmt_wr_hdr_5_0_a2_0_a2_0_a2_0_a2_12_.INIT = 4'h8; + LUT2_L com_cmm_u_cmm_errman_reg_cmt_wr_hdr_5_0_a2_0_a2_0_a2_0_a2_12_ ( + .I0(com_cmm_u_cmm_errman_N_48855_i), + .I1(com_cmmt_err_tlp_hdr[12]), + .LO(com_cmm_u_cmm_errman_reg_cmt_wr_hdr_5[12]) + ); + defparam com_cmm_u_cmm_errman_reg_cmt_wr_hdr_5_0_a2_0_a2_0_a2_0_a2_11_.INIT = 4'h8; + LUT2_L com_cmm_u_cmm_errman_reg_cmt_wr_hdr_5_0_a2_0_a2_0_a2_0_a2_11_ ( + .I0(com_cmm_u_cmm_errman_N_48855_i), + .I1(com_cmmt_err_tlp_hdr[11]), + .LO(com_cmm_u_cmm_errman_reg_cmt_wr_hdr_5[11]) + ); + defparam com_cmm_u_cmm_errman_reg_cmt_wr_hdr_5_0_a2_0_a2_0_a2_0_a2_10_.INIT = 4'h8; + LUT2_L com_cmm_u_cmm_errman_reg_cmt_wr_hdr_5_0_a2_0_a2_0_a2_0_a2_10_ ( + .I0(com_cmm_u_cmm_errman_N_48855_i), + .I1(com_cmmt_err_tlp_hdr[10]), + .LO(com_cmm_u_cmm_errman_reg_cmt_wr_hdr_5[10]) + ); + defparam com_cmm_u_cmm_errman_reg_cmt_wr_hdr_5_0_a2_0_a2_0_a2_0_a2_39_.INIT = 4'h8; + LUT2_L com_cmm_u_cmm_errman_reg_cmt_wr_hdr_5_0_a2_0_a2_0_a2_0_a2_39_ ( + .I0(com_cmm_u_cmm_errman_N_48855_i), + .I1(com_cmmt_err_tlp_hdr[39]), + .LO(com_cmm_u_cmm_errman_reg_cmt_wr_hdr_5[39]) + ); + defparam com_cmm_u_cmm_errman_reg_cmt_wr_hdr_5_0_a2_0_a2_0_a2_0_a2_38_.INIT = 4'h8; + LUT2_L com_cmm_u_cmm_errman_reg_cmt_wr_hdr_5_0_a2_0_a2_0_a2_0_a2_38_ ( + .I0(com_cmm_u_cmm_errman_N_48855_i), + .I1(com_cmmt_err_tlp_hdr[38]), + .LO(com_cmm_u_cmm_errman_reg_cmt_wr_hdr_5[38]) + ); + defparam com_cmm_u_cmm_errman_reg_cmt_wr_hdr_5_0_a2_0_a2_0_a2_0_a2_37_.INIT = 4'h8; + LUT2_L com_cmm_u_cmm_errman_reg_cmt_wr_hdr_5_0_a2_0_a2_0_a2_0_a2_37_ ( + .I0(com_cmm_u_cmm_errman_N_48855_i), + .I1(com_cmmt_err_tlp_hdr[37]), + .LO(com_cmm_u_cmm_errman_reg_cmt_wr_hdr_5[37]) + ); + defparam com_cmm_u_cmm_errman_reg_cmt_wr_hdr_5_0_a2_0_a2_0_a2_0_a2_36_.INIT = 4'h8; + LUT2_L com_cmm_u_cmm_errman_reg_cmt_wr_hdr_5_0_a2_0_a2_0_a2_0_a2_36_ ( + .I0(com_cmm_u_cmm_errman_N_48855_i), + .I1(com_cmmt_err_tlp_hdr[36]), + .LO(com_cmm_u_cmm_errman_reg_cmt_wr_hdr_5[36]) + ); + defparam com_cmm_u_cmm_errman_reg_cmt_wr_hdr_5_0_a2_0_a2_0_a2_0_a2_35_.INIT = 4'h8; + LUT2_L com_cmm_u_cmm_errman_reg_cmt_wr_hdr_5_0_a2_0_a2_0_a2_0_a2_35_ ( + .I0(com_cmm_u_cmm_errman_N_48855_i), + .I1(com_cmmt_err_tlp_hdr[35]), + .LO(com_cmm_u_cmm_errman_reg_cmt_wr_hdr_5[35]) + ); + defparam com_cmm_u_cmm_errman_reg_cmt_wr_hdr_5_0_a2_0_a2_0_a2_0_a2_34_.INIT = 4'h8; + LUT2_L com_cmm_u_cmm_errman_reg_cmt_wr_hdr_5_0_a2_0_a2_0_a2_0_a2_34_ ( + .I0(com_cmm_u_cmm_errman_N_48855_i), + .I1(com_cmmt_err_tlp_hdr[34]), + .LO(com_cmm_u_cmm_errman_reg_cmt_wr_hdr_5[34]) + ); + defparam com_cmm_u_cmm_errman_reg_cmt_wr_hdr_5_0_a2_0_a2_0_a2_0_a2_33_.INIT = 4'h8; + LUT2_L com_cmm_u_cmm_errman_reg_cmt_wr_hdr_5_0_a2_0_a2_0_a2_0_a2_33_ ( + .I0(com_cmm_u_cmm_errman_N_48855_i), + .I1(com_cmmt_err_tlp_hdr[33]), + .LO(com_cmm_u_cmm_errman_reg_cmt_wr_hdr_5[33]) + ); + defparam com_cmm_u_cmm_errman_reg_cmt_wr_hdr_5_0_a2_0_a2_0_a2_0_a2_32_.INIT = 4'h8; + LUT2_L com_cmm_u_cmm_errman_reg_cmt_wr_hdr_5_0_a2_0_a2_0_a2_0_a2_32_ ( + .I0(com_cmm_u_cmm_errman_N_48855_i), + .I1(com_cmmt_err_tlp_hdr[32]), + .LO(com_cmm_u_cmm_errman_reg_cmt_wr_hdr_5[32]) + ); + defparam com_cmm_u_cmm_errman_reg_cmt_wr_hdr_5_0_a2_0_a2_0_a2_0_a2_31_.INIT = 4'h8; + LUT2_L com_cmm_u_cmm_errman_reg_cmt_wr_hdr_5_0_a2_0_a2_0_a2_0_a2_31_ ( + .I0(com_cmm_u_cmm_errman_N_48855_i), + .I1(com_cmmt_err_tlp_hdr[31]), + .LO(com_cmm_u_cmm_errman_reg_cmt_wr_hdr_5[31]) + ); + defparam com_cmm_u_cmm_errman_reg_cmt_wr_hdr_5_0_a2_0_a2_0_a2_0_a2_30_.INIT = 4'h8; + LUT2_L com_cmm_u_cmm_errman_reg_cmt_wr_hdr_5_0_a2_0_a2_0_a2_0_a2_30_ ( + .I0(com_cmm_u_cmm_errman_N_48855_i), + .I1(com_cmmt_err_tlp_hdr[30]), + .LO(com_cmm_u_cmm_errman_reg_cmt_wr_hdr_5[30]) + ); + defparam com_cmm_u_cmm_errman_reg_cmt_wr_hdr_5_0_a2_0_a2_0_a2_0_a2_29_.INIT = 4'h8; + LUT2_L com_cmm_u_cmm_errman_reg_cmt_wr_hdr_5_0_a2_0_a2_0_a2_0_a2_29_ ( + .I0(com_cmm_u_cmm_errman_N_48855_i), + .I1(com_cmmt_err_tlp_hdr[29]), + .LO(com_cmm_u_cmm_errman_reg_cmt_wr_hdr_5[29]) + ); + defparam com_cmm_u_cmm_errman_reg_cmt_wr_hdr_5_0_a2_0_a2_0_a2_0_a2_28_.INIT = 4'h8; + LUT2_L com_cmm_u_cmm_errman_reg_cmt_wr_hdr_5_0_a2_0_a2_0_a2_0_a2_28_ ( + .I0(com_cmm_u_cmm_errman_N_48855_i), + .I1(com_cmmt_err_tlp_hdr[28]), + .LO(com_cmm_u_cmm_errman_reg_cmt_wr_hdr_5[28]) + ); + defparam com_cmm_u_cmm_errman_reg_cmt_wr_hdr_5_0_a2_0_a2_0_a2_0_a2_27_.INIT = 4'h8; + LUT2_L com_cmm_u_cmm_errman_reg_cmt_wr_hdr_5_0_a2_0_a2_0_a2_0_a2_27_ ( + .I0(com_cmm_u_cmm_errman_N_48855_i), + .I1(com_cmmt_err_tlp_hdr[27]), + .LO(com_cmm_u_cmm_errman_reg_cmt_wr_hdr_5[27]) + ); + defparam com_cmm_u_cmm_errman_reg_cmt_wr_hdr_5_0_a2_0_a2_0_a2_0_a2_26_.INIT = 4'h8; + LUT2_L com_cmm_u_cmm_errman_reg_cmt_wr_hdr_5_0_a2_0_a2_0_a2_0_a2_26_ ( + .I0(com_cmm_u_cmm_errman_N_48855_i), + .I1(com_cmmt_err_tlp_hdr[26]), + .LO(com_cmm_u_cmm_errman_reg_cmt_wr_hdr_5[26]) + ); + defparam com_cmm_u_cmm_errman_reg_cmt_wr_hdr_5_0_a2_0_a2_0_a2_0_a2_25_.INIT = 4'h8; + LUT2_L com_cmm_u_cmm_errman_reg_cmt_wr_hdr_5_0_a2_0_a2_0_a2_0_a2_25_ ( + .I0(com_cmm_u_cmm_errman_N_48855_i), + .I1(com_cmmt_err_tlp_hdr[25]), + .LO(com_cmm_u_cmm_errman_reg_cmt_wr_hdr_5[25]) + ); + defparam com_cmm_u_cmm_errman_reg_cfg_wp_4_axbxc1.INIT = 8'h6C; + LUT3_L com_cmm_u_cmm_errman_reg_cfg_wp_4_axbxc1 ( + .I0(com_cmm_u_cmm_errman_reg_cfg_wp[0]), + .I1(com_cmm_u_cmm_errman_reg_cfg_wp[1]), + .I2(com_cmm_u_cmm_errman_reg_incr_cplu_4809), + .LO(com_cmm_u_cmm_errman_reg_cfg_wp_4[1]) + ); + defparam com_cmm_u_cmm_errman_reg_cfg_wp_4_axbxc0.INIT = 4'h6; + LUT2_L com_cmm_u_cmm_errman_reg_cfg_wp_4_axbxc0 ( + .I0(com_cmm_u_cmm_errman_reg_cfg_wp[0]), + .I1(com_cmm_u_cmm_errman_reg_incr_cplu_4809), + .LO(com_cmm_u_cmm_errman_reg_cfg_wp_4[0]) + ); + defparam com_cmm_u_cmm_errman_reg_cmt_wp_4_axbxc1.INIT = 8'h6C; + LUT3_L com_cmm_u_cmm_errman_reg_cmt_wp_4_axbxc1 ( + .I0(com_cmm_u_cmm_errman_reg_cmt_wp[0]), + .I1(com_cmm_u_cmm_errman_reg_cmt_wp[1]), + .I2(com_cmm_u_cmm_errman_reg_cmt_wr_hdr[48]), + .LO(com_cmm_u_cmm_errman_reg_cmt_wp_4[1]) + ); + defparam com_cmm_u_cmm_errman_reg_cmt_wp_4_axbxc0.INIT = 4'h6; + LUT2_L com_cmm_u_cmm_errman_reg_cmt_wp_4_axbxc0 ( + .I0(com_cmm_u_cmm_errman_reg_cmt_wp[0]), + .I1(com_cmm_u_cmm_errman_reg_cmt_wr_hdr[48]), + .LO(com_cmm_u_cmm_errman_reg_cmt_wp_4[0]) + ); + defparam com_cmm_u_cmm_errman_reg_cmt_wr_hdr_5_0_a2_0_a2_0_a2_0_a2_47_.INIT = 4'h8; + LUT2_L com_cmm_u_cmm_errman_reg_cmt_wr_hdr_5_0_a2_0_a2_0_a2_0_a2_47_ ( + .I0(com_cmm_u_cmm_errman_N_48855_i), + .I1(com_cmmt_err_tlp_hdr[47]), + .LO(com_cmm_u_cmm_errman_reg_cmt_wr_hdr_5[47]) + ); + defparam com_cmm_u_cmm_errman_reg_cmt_wr_hdr_5_0_a2_0_a2_0_a2_0_a2_46_.INIT = 4'h8; + LUT2_L com_cmm_u_cmm_errman_reg_cmt_wr_hdr_5_0_a2_0_a2_0_a2_0_a2_46_ ( + .I0(com_cmm_u_cmm_errman_N_48855_i), + .I1(com_cmmt_err_tlp_hdr[46]), + .LO(com_cmm_u_cmm_errman_reg_cmt_wr_hdr_5[46]) + ); + defparam com_cmm_u_cmm_errman_reg_cmt_wr_hdr_5_0_a2_0_a2_0_a2_0_a2_45_.INIT = 4'h8; + LUT2_L com_cmm_u_cmm_errman_reg_cmt_wr_hdr_5_0_a2_0_a2_0_a2_0_a2_45_ ( + .I0(com_cmm_u_cmm_errman_N_48855_i), + .I1(com_cmmt_err_tlp_hdr[45]), + .LO(com_cmm_u_cmm_errman_reg_cmt_wr_hdr_5[45]) + ); + defparam com_cmm_u_cmm_errman_reg_cmt_wr_hdr_5_0_a2_0_a2_0_a2_0_a2_44_.INIT = 4'h8; + LUT2_L com_cmm_u_cmm_errman_reg_cmt_wr_hdr_5_0_a2_0_a2_0_a2_0_a2_44_ ( + .I0(com_cmm_u_cmm_errman_N_48855_i), + .I1(com_cmmt_err_tlp_hdr[44]), + .LO(com_cmm_u_cmm_errman_reg_cmt_wr_hdr_5[44]) + ); + defparam com_cmm_u_cmm_errman_reg_cmt_wr_hdr_5_0_a2_0_a2_0_a2_0_a2_43_.INIT = 4'h8; + LUT2_L com_cmm_u_cmm_errman_reg_cmt_wr_hdr_5_0_a2_0_a2_0_a2_0_a2_43_ ( + .I0(com_cmm_u_cmm_errman_N_48855_i), + .I1(com_cmmt_err_tlp_hdr[43]), + .LO(com_cmm_u_cmm_errman_reg_cmt_wr_hdr_5[43]) + ); + defparam com_cmm_u_cmm_errman_reg_cmt_wr_hdr_5_0_a2_0_a2_0_a2_0_a2_42_.INIT = 4'h8; + LUT2_L com_cmm_u_cmm_errman_reg_cmt_wr_hdr_5_0_a2_0_a2_0_a2_0_a2_42_ ( + .I0(com_cmm_u_cmm_errman_N_48855_i), + .I1(com_cmmt_err_tlp_hdr[42]), + .LO(com_cmm_u_cmm_errman_reg_cmt_wr_hdr_5[42]) + ); + defparam com_cmm_u_cmm_errman_reg_cmt_wr_hdr_5_0_a2_0_a2_0_a2_0_a2_41_.INIT = 4'h8; + LUT2_L com_cmm_u_cmm_errman_reg_cmt_wr_hdr_5_0_a2_0_a2_0_a2_0_a2_41_ ( + .I0(com_cmm_u_cmm_errman_N_48855_i), + .I1(com_cmmt_err_tlp_hdr[41]), + .LO(com_cmm_u_cmm_errman_reg_cmt_wr_hdr_5[41]) + ); + defparam com_cmm_u_cmm_errman_reg_cmt_wr_hdr_5_0_a2_0_a2_0_a2_0_a2_40_.INIT = 4'h8; + LUT2_L com_cmm_u_cmm_errman_reg_cmt_wr_hdr_5_0_a2_0_a2_0_a2_0_a2_40_ ( + .I0(com_cmm_u_cmm_errman_N_48855_i), + .I1(com_cmmt_err_tlp_hdr[40]), + .LO(com_cmm_u_cmm_errman_reg_cmt_wr_hdr_5[40]) + ); + defparam com_cmm_u_cmm_errman_N_42551_i.INIT = 4'h1; + LUT1_L com_cmm_u_cmm_errman_N_42551_i ( + .I0(com_cmm_u_cmm_errman_reg_detectedcorrectable_3_i_0_0_a2_4796), + .LO(com_cmm_u_cmm_errman_N_42551_i_4795) + ); + defparam com_cmm_u_cmm_errman_replay_vld_i.INIT = 4'h1; + LUT1_L com_cmm_u_cmm_errman_replay_vld_i ( + .I0(com_replay_vld), + .LO(com_cmm_u_cmm_errman_replay_vld_i_4797) + ); + defparam com_cmm_u_cmm_errman_un1_cmmt_err_tlp_ur_i_0_0_0.INIT = 8'h40; + LUT3_L com_cmm_u_cmm_errman_un1_cmmt_err_tlp_ur_i_0_0_0 ( + .I0(com_cmm_u_cmm_errman_N_49554), + .I1(com_cmmt_err_tlp_p_cpl), + .I2(com_cmmt_err_tlp_ur), + .LO(com_cmm_u_cmm_errman_N_15818_i) + ); + defparam com_cmm_u_cmm_errman_N_68760_i.INIT = 8'hFE; + LUT3_L com_cmm_u_cmm_errman_N_68760_i ( + .I0(com_cmm_u_cmm_errman_N_49554), + .I1(cfg_err_posted_n), + .I2(cfg_err_ur_n), + .LO(com_cmm_u_cmm_errman_N_68760_i_4798) + ); + defparam com_cmm_u_cmm_errman_N_68492_i.INIT = 8'hF1; + LUT3_L com_cmm_u_cmm_errman_N_68492_i ( + .I0(NlwRenamedSig_OI_cfg_command_8_), + .I1(NlwRenamedSig_OI_cfg_dcommand[1]), + .I2(cfg_err_ecrc_n), + .LO(com_cmm_u_cmm_errman_N_68492_i_4799) + ); + defparam com_cmm_u_cmm_errman_N_68491_i.INIT = 8'hF1; + LUT3_L com_cmm_u_cmm_errman_N_68491_i ( + .I0(NlwRenamedSig_OI_cfg_command_8_), + .I1(NlwRenamedSig_OI_cfg_dcommand[1]), + .I2(cfg_err_cpl_timeout_n), + .LO(com_cmm_u_cmm_errman_N_68491_i_4800) + ); + defparam com_cmm_u_cmm_errman_reg_signaledsystemerror_9_i_0_0_0_1.INIT = 16'h0007; + LUT4_L com_cmm_u_cmm_errman_reg_signaledsystemerror_9_i_0_0_0_1 ( + .I0(com_cmm_N_48927_i), + .I1(NlwRenamedSig_OI_cfg_dcommand[3]), + .I2(com_cmm_u_cmm_errman_cs_is_cplu_4806), + .I3(com_cmm_u_cmm_errman_cs_is_ftl_4805), + .LO(com_cmm_u_cmm_errman_reg_signaledsystemerror_9_i_0_0_0_1_4876) + ); + defparam com_cmm_u_cmm_errman_request_9_0_i_0_0_a3_1_.INIT = 8'h02; + LUT3 com_cmm_u_cmm_errman_request_9_0_i_0_0_a3_1_ ( + .I0(com_cmm_u_cmm_errman_cs_fsm[1]), + .I1(com_cmm_u_cmm_errman_cs_fsm[2]), + .I2(com_cmm_u_cmm_errman_cs_fsm[0]), + .O(com_cmm_u_cmm_errman_cs_is_ftl30) + ); + FDC com_cmm_u_cmm_errman_reg_detectedparityerror ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmmt_stat_tlp_rx_ep), + .Q(com_cmm_detectedparityerror), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_errman_reg_receivedtargetabort ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmmt_stat_tlp_rx_cpl_abort), + .Q(com_cmm_receivedtargetabort), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_errman_reg_receivedmasterabort ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmmt_stat_tlp_rx_cpl_ur), + .Q(com_cmm_receivedmasterabort), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_errman_reg_signaledtargetabort ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_cfg_is_np_and_cpl_abort), + .Q(com_cmm_signaledtargetabort), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_errman_send_cplt ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_un1_reg_uflow_3_i_1_4801), + .Q(com_cmm_u_cmm_errman_send_cplt_4802), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_errman_send_cor ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_N_51019_i_4803), + .Q(com_cmm_u_cmm_errman_send_cor_4804), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_errman_reg_detectedfatal ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_N_96_2_i), + .Q(com_cmm_detectedfatal), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_errman_cs_is_nfl ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_cs_is_ftl32), + .Q(com_cmm_u_cmm_errman_cs_is_nfl_4877), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_errman_cs_is_ftl ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_cs_is_ftl31), + .Q(com_cmm_u_cmm_errman_cs_is_ftl_4805), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_errman_cs_is_cplu ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_cs_is_ftl29), + .Q(com_cmm_u_cmm_errman_cs_is_cplu_4806), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_errman_cs_is_cplt ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_cs_is_ftl30), + .Q(com_cmm_u_cmm_errman_cs_is_cplt_4807), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_errman_cs_is_cor ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_cs_is_ftl33), + .Q(com_cmm_u_cmm_errman_cs_is_cor_4808), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_errman_reg_incr_cplu ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_N_49807), + .Q(com_cmm_u_cmm_errman_reg_incr_cplu_4809), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_errman_reg_unsupportedreq ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_N_68759_i_4810), + .Q(com_cmm_unsupportedreq), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_errman_reg_masterdataparityerror ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_reg_masterdataparityerror_3_4811), + .Q(com_cmm_masterdataparityerror), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_errman_send_nfl ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_un1_reg_uflow_3_i_0_4812), + .Q(com_cmm_u_cmm_errman_send_nfl_4813), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_errman_send_ftl ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_N_51043_i_4814), + .Q(com_cmm_u_cmm_errman_send_ftl_4815), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_errman_send_cplu ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_un1_reg_uflow_3_i_4816), + .Q(com_cmm_u_cmm_errman_send_cplu_4817), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_errman_reg_signaledsystemerror ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_N_15633_i), + .Q(com_cmm_signaledsystemerror), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_errman_reg_detectednonfatal ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_N_68187_i_4818), + .Q(com_cmm_detectednonfatal), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_errman_reg_detectedcorrectable ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_N_67919_i_4819), + .Q(com_cmm_detectedcorrectable), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_errman_request_0_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_N_47879_i), + .Q(com_cmm_req_errman[0]), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_errman_reg_cfg_wr_hdr_4_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_N_32752_i), + .Q(com_cmm_u_cmm_errman_reg_cfg_wr_hdr[4]), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_errman_reg_cfg_wr_hdr_3_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_N_32750_i), + .Q(com_cmm_u_cmm_errman_reg_cfg_wr_hdr[3]), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_errman_reg_cfg_wr_hdr_2_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_N_32748_i), + .Q(com_cmm_u_cmm_errman_reg_cfg_wr_hdr[2]), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_errman_reg_cfg_wr_hdr_1_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_N_32746_i), + .Q(com_cmm_u_cmm_errman_reg_cfg_wr_hdr[1]), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_errman_reg_cfg_wr_hdr_0_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_N_32744_i), + .Q(com_cmm_u_cmm_errman_reg_cfg_wr_hdr[0]), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_errman_reg_cfg_rp_1_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_reg_cfg_rp_4[1]), + .Q(com_cmm_u_cmm_errman_reg_cfg_rp[1]), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_errman_reg_cfg_rp_0_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_reg_cfg_rp_4[0]), + .Q(com_cmm_u_cmm_errman_reg_cfg_rp[0]), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_errman_reg_cmt_rp_1_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_reg_cmt_rp_4[1]), + .Q(com_cmm_u_cmm_errman_reg_cmt_rp[1]), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_errman_reg_cmt_rp_0_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_reg_cmt_rp_4[0]), + .Q(com_cmm_u_cmm_errman_reg_cmt_rp[0]), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_errman_cs_fsm_3_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_un1_cs_fsm_1_0_a2_0_a2_0_a2_0_a2_4820), + .Q(com_cmm_u_cmm_errman_cs_fsm[3]), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_errman_cs_fsm_2_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_N_68159_i_4821), + .Q(com_cmm_u_cmm_errman_cs_fsm[2]), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_errman_cs_fsm_1_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_N_68160_i_4822), + .Q(com_cmm_u_cmm_errman_cs_fsm[1]), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_errman_cs_fsm_0_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_N_68198_i_4823), + .Q(com_cmm_u_cmm_errman_cs_fsm[0]), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_errman_request_2_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_N_68481_i_4824), + .Q(com_cmm_req_errman[2]), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_errman_request_1_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_N_68617_i_4825), + .Q(com_cmm_req_errman[1]), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_errman_reg_cfg_wr_hdr_19_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_N_32782_i), + .Q(com_cmm_u_cmm_errman_reg_cfg_wr_hdr[19]), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_errman_reg_cfg_wr_hdr_18_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_N_32780_i), + .Q(com_cmm_u_cmm_errman_reg_cfg_wr_hdr[18]), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_errman_reg_cfg_wr_hdr_17_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_N_32778_i), + .Q(com_cmm_u_cmm_errman_reg_cfg_wr_hdr[17]), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_errman_reg_cfg_wr_hdr_16_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_N_32776_i), + .Q(com_cmm_u_cmm_errman_reg_cfg_wr_hdr[16]), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_errman_reg_cfg_wr_hdr_15_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_N_32774_i), + .Q(com_cmm_u_cmm_errman_reg_cfg_wr_hdr[15]), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_errman_reg_cfg_wr_hdr_14_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_N_32772_i), + .Q(com_cmm_u_cmm_errman_reg_cfg_wr_hdr[14]), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_errman_reg_cfg_wr_hdr_13_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_N_32770_i), + .Q(com_cmm_u_cmm_errman_reg_cfg_wr_hdr[13]), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_errman_reg_cfg_wr_hdr_12_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_N_32768_i), + .Q(com_cmm_u_cmm_errman_reg_cfg_wr_hdr[12]), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_errman_reg_cfg_wr_hdr_11_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_N_32766_i), + .Q(com_cmm_u_cmm_errman_reg_cfg_wr_hdr[11]), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_errman_reg_cfg_wr_hdr_10_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_N_32764_i), + .Q(com_cmm_u_cmm_errman_reg_cfg_wr_hdr[10]), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_errman_reg_cfg_wr_hdr_9_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_N_32762_i), + .Q(com_cmm_u_cmm_errman_reg_cfg_wr_hdr[9]), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_errman_reg_cfg_wr_hdr_8_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_N_32760_i), + .Q(com_cmm_u_cmm_errman_reg_cfg_wr_hdr[8]), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_errman_reg_cfg_wr_hdr_7_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_N_32758_i), + .Q(com_cmm_u_cmm_errman_reg_cfg_wr_hdr[7]), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_errman_reg_cfg_wr_hdr_6_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_N_32756_i), + .Q(com_cmm_u_cmm_errman_reg_cfg_wr_hdr[6]), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_errman_reg_cfg_wr_hdr_5_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_N_32754_i), + .Q(com_cmm_u_cmm_errman_reg_cfg_wr_hdr[5]), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_errman_reg_cfg_wr_hdr_34_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_N_32812_i), + .Q(com_cmm_u_cmm_errman_reg_cfg_wr_hdr[34]), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_errman_reg_cfg_wr_hdr_33_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_N_32810_i), + .Q(com_cmm_u_cmm_errman_reg_cfg_wr_hdr[33]), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_errman_reg_cfg_wr_hdr_32_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_N_32808_i), + .Q(com_cmm_u_cmm_errman_reg_cfg_wr_hdr[32]), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_errman_reg_cfg_wr_hdr_31_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_N_32806_i), + .Q(com_cmm_u_cmm_errman_reg_cfg_wr_hdr[31]), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_errman_reg_cfg_wr_hdr_30_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_N_32804_i), + .Q(com_cmm_u_cmm_errman_reg_cfg_wr_hdr[30]), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_errman_reg_cfg_wr_hdr_29_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_N_32802_i), + .Q(com_cmm_u_cmm_errman_reg_cfg_wr_hdr[29]), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_errman_reg_cfg_wr_hdr_28_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_N_32800_i), + .Q(com_cmm_u_cmm_errman_reg_cfg_wr_hdr[28]), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_errman_reg_cfg_wr_hdr_27_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_N_32798_i), + .Q(com_cmm_u_cmm_errman_reg_cfg_wr_hdr[27]), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_errman_reg_cfg_wr_hdr_26_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_N_32796_i), + .Q(com_cmm_u_cmm_errman_reg_cfg_wr_hdr[26]), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_errman_reg_cfg_wr_hdr_25_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_N_32794_i), + .Q(com_cmm_u_cmm_errman_reg_cfg_wr_hdr[25]), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_errman_reg_cfg_wr_hdr_24_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_N_32792_i), + .Q(com_cmm_u_cmm_errman_reg_cfg_wr_hdr[24]), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_errman_reg_cfg_wr_hdr_23_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_N_32790_i), + .Q(com_cmm_u_cmm_errman_reg_cfg_wr_hdr[23]), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_errman_reg_cfg_wr_hdr_22_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_N_32788_i), + .Q(com_cmm_u_cmm_errman_reg_cfg_wr_hdr[22]), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_errman_reg_cfg_wr_hdr_21_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_N_32786_i), + .Q(com_cmm_u_cmm_errman_reg_cfg_wr_hdr[21]), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_errman_reg_cfg_wr_hdr_20_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_N_32784_i), + .Q(com_cmm_u_cmm_errman_reg_cfg_wr_hdr[20]), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_errman_reg_cfg_wr_hdr_49_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_reg_cfg_wr_hdr20), + .Q(com_cmm_u_cmm_errman_reg_cfg_wr_hdr[49]), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_errman_reg_cfg_wr_hdr_48_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_cfg_is_np_and_ur), + .Q(com_cmm_u_cmm_errman_reg_cfg_wr_hdr[48]), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_errman_reg_cfg_wr_hdr_47_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_N_32838_i), + .Q(com_cmm_u_cmm_errman_reg_cfg_wr_hdr[47]), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_errman_reg_cfg_wr_hdr_46_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_N_32836_i), + .Q(com_cmm_u_cmm_errman_reg_cfg_wr_hdr[46]), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_errman_reg_cfg_wr_hdr_45_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_N_32834_i), + .Q(com_cmm_u_cmm_errman_reg_cfg_wr_hdr[45]), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_errman_reg_cfg_wr_hdr_44_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_N_32832_i), + .Q(com_cmm_u_cmm_errman_reg_cfg_wr_hdr[44]), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_errman_reg_cfg_wr_hdr_43_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_N_32830_i), + .Q(com_cmm_u_cmm_errman_reg_cfg_wr_hdr[43]), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_errman_reg_cfg_wr_hdr_42_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_N_32828_i), + .Q(com_cmm_u_cmm_errman_reg_cfg_wr_hdr[42]), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_errman_reg_cfg_wr_hdr_41_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_N_32826_i), + .Q(com_cmm_u_cmm_errman_reg_cfg_wr_hdr[41]), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_errman_reg_cfg_wr_hdr_40_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_N_32824_i), + .Q(com_cmm_u_cmm_errman_reg_cfg_wr_hdr[40]), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_errman_reg_cfg_wr_hdr_39_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_N_32822_i), + .Q(com_cmm_u_cmm_errman_reg_cfg_wr_hdr[39]), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_errman_reg_cfg_wr_hdr_38_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_N_32820_i), + .Q(com_cmm_u_cmm_errman_reg_cfg_wr_hdr[38]), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_errman_reg_cfg_wr_hdr_37_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_N_32818_i), + .Q(com_cmm_u_cmm_errman_reg_cfg_wr_hdr[37]), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_errman_reg_cfg_wr_hdr_36_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_N_32816_i), + .Q(com_cmm_u_cmm_errman_reg_cfg_wr_hdr[36]), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_errman_reg_cfg_wr_hdr_35_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_N_32814_i), + .Q(com_cmm_u_cmm_errman_reg_cfg_wr_hdr[35]), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_errman_request_data_14_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_N_68444_i_4826), + .Q(com_cmm_data_errmanager[14]), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_errman_request_data_13_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_N_68443_i_4827), + .Q(com_cmm_data_errmanager[13]), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_errman_request_data_12_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_N_68442_i_4828), + .Q(com_cmm_data_errmanager[12]), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_errman_request_data_11_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_N_68441_i_4829), + .Q(com_cmm_data_errmanager[11]), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_errman_request_data_10_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_N_68440_i_4830), + .Q(com_cmm_data_errmanager[10]), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_errman_request_data_9_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_N_68439_i_4831), + .Q(com_cmm_data_errmanager[9]), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_errman_request_data_8_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_N_68438_i_4832), + .Q(com_cmm_data_errmanager[8]), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_errman_request_data_7_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_N_68437_i_4833), + .Q(com_cmm_data_errmanager[7]), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_errman_request_data_6_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_N_68436_i_4834), + .Q(com_cmm_data_errmanager[6]), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_errman_request_data_5_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_N_68435_i_4835), + .Q(com_cmm_data_errmanager[5]), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_errman_request_data_4_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_N_68434_i_4836), + .Q(com_cmm_data_errmanager[4]), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_errman_request_data_3_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_N_68433_i_4837), + .Q(com_cmm_data_errmanager[3]), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_errman_request_data_2_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_N_68432_i_4838), + .Q(com_cmm_data_errmanager[2]), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_errman_request_data_1_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_N_68431_i_4839), + .Q(com_cmm_data_errmanager[1]), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_errman_request_data_0_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_N_68430_i_4840), + .Q(com_cmm_data_errmanager[0]), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_errman_request_data_29_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_N_68459_i_4841), + .Q(com_cmm_data_errmanager[29]), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_errman_request_data_28_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_N_68458_i_4842), + .Q(com_cmm_data_errmanager[28]), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_errman_request_data_27_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_N_68457_i_4843), + .Q(com_cmm_data_errmanager[27]), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_errman_request_data_26_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_N_68456_i_4844), + .Q(com_cmm_data_errmanager[26]), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_errman_request_data_25_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_N_68455_i_4845), + .Q(com_cmm_data_errmanager[25]), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_errman_request_data_24_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_N_68454_i_4846), + .Q(com_cmm_data_errmanager[24]), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_errman_request_data_23_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_N_68453_i_4847), + .Q(com_cmm_data_errmanager[23]), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_errman_request_data_22_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_N_68452_i_4848), + .Q(com_cmm_data_errmanager[22]), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_errman_request_data_21_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_N_68451_i_4849), + .Q(com_cmm_data_errmanager[21]), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_errman_request_data_20_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_N_68450_i_4850), + .Q(com_cmm_data_errmanager[20]), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_errman_request_data_19_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_N_68449_i_4851), + .Q(com_cmm_data_errmanager[19]), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_errman_request_data_18_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_N_68448_i_4852), + .Q(com_cmm_data_errmanager[18]), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_errman_request_data_17_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_N_68447_i_4853), + .Q(com_cmm_data_errmanager[17]), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_errman_request_data_16_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_N_68446_i_4854), + .Q(com_cmm_data_errmanager[16]), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_errman_request_data_15_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_N_68445_i_4855), + .Q(com_cmm_data_errmanager[15]), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_errman_request_data_44_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_N_68474_i_4856), + .Q(com_cmm_data_errmanager[44]), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_errman_request_data_43_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_N_68473_i_4857), + .Q(com_cmm_data_errmanager[43]), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_errman_request_data_42_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_N_68472_i_4858), + .Q(com_cmm_data_errmanager[42]), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_errman_request_data_41_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_N_68471_i_4859), + .Q(com_cmm_data_errmanager[41]), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_errman_request_data_40_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_N_68470_i_4860), + .Q(com_cmm_data_errmanager[40]), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_errman_request_data_39_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_N_68469_i_4861), + .Q(com_cmm_data_errmanager[39]), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_errman_request_data_38_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_N_68468_i_4862), + .Q(com_cmm_data_errmanager[38]), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_errman_request_data_37_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_N_68467_i_4863), + .Q(com_cmm_data_errmanager[37]), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_errman_request_data_36_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_N_68466_i_4864), + .Q(com_cmm_data_errmanager[36]), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_errman_request_data_35_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_N_68465_i_4865), + .Q(com_cmm_data_errmanager[35]), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_errman_request_data_34_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_N_68464_i_4866), + .Q(com_cmm_data_errmanager[34]), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_errman_request_data_33_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_N_68463_i_4867), + .Q(com_cmm_data_errmanager[33]), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_errman_request_data_32_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_N_68462_i_4868), + .Q(com_cmm_data_errmanager[32]), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_errman_request_data_31_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_N_68461_i_4869), + .Q(com_cmm_data_errmanager[31]), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_errman_request_data_30_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_N_68460_i_4870), + .Q(com_cmm_data_errmanager[30]), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_errman_reg_cmt_wr_hdr_9_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_reg_cmt_wr_hdr_5[9]), + .Q(com_cmm_u_cmm_errman_reg_cmt_wr_hdr[9]), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_errman_reg_cmt_wr_hdr_8_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_reg_cmt_wr_hdr_5[8]), + .Q(com_cmm_u_cmm_errman_reg_cmt_wr_hdr[8]), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_errman_reg_cmt_wr_hdr_7_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_reg_cmt_wr_hdr_5[7]), + .Q(com_cmm_u_cmm_errman_reg_cmt_wr_hdr[7]), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_errman_reg_cmt_wr_hdr_6_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_reg_cmt_wr_hdr_5[6]), + .Q(com_cmm_u_cmm_errman_reg_cmt_wr_hdr[6]), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_errman_reg_cmt_wr_hdr_5_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_reg_cmt_wr_hdr_5[5]), + .Q(com_cmm_u_cmm_errman_reg_cmt_wr_hdr[5]), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_errman_reg_cmt_wr_hdr_4_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_reg_cmt_wr_hdr_5[4]), + .Q(com_cmm_u_cmm_errman_reg_cmt_wr_hdr[4]), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_errman_reg_cmt_wr_hdr_3_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_reg_cmt_wr_hdr_5[3]), + .Q(com_cmm_u_cmm_errman_reg_cmt_wr_hdr[3]), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_errman_reg_cmt_wr_hdr_2_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_reg_cmt_wr_hdr_5[2]), + .Q(com_cmm_u_cmm_errman_reg_cmt_wr_hdr[2]), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_errman_reg_cmt_wr_hdr_1_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_reg_cmt_wr_hdr_5[1]), + .Q(com_cmm_u_cmm_errman_reg_cmt_wr_hdr[1]), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_errman_reg_cmt_wr_hdr_0_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_reg_cmt_wr_hdr_5[0]), + .Q(com_cmm_u_cmm_errman_reg_cmt_wr_hdr[0]), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_errman_request_data_49_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_N_68479_i_4871), + .Q(com_cmm_data_errmanager[49]), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_errman_request_data_48_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_N_68478_i_4872), + .Q(com_cmm_data_errmanager[48]), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_errman_request_data_47_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_N_68477_i_4873), + .Q(com_cmm_data_errmanager[47]), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_errman_request_data_46_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_N_68476_i_4874), + .Q(com_cmm_data_errmanager[46]), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_errman_request_data_45_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_N_68475_i_4875), + .Q(com_cmm_data_errmanager[45]), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_errman_reg_cmt_wr_hdr_24_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_reg_cmt_wr_hdr_5[24]), + .Q(com_cmm_u_cmm_errman_reg_cmt_wr_hdr[24]), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_errman_reg_cmt_wr_hdr_23_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_reg_cmt_wr_hdr_5[23]), + .Q(com_cmm_u_cmm_errman_reg_cmt_wr_hdr[23]), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_errman_reg_cmt_wr_hdr_22_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_reg_cmt_wr_hdr_5[22]), + .Q(com_cmm_u_cmm_errman_reg_cmt_wr_hdr[22]), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_errman_reg_cmt_wr_hdr_21_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_reg_cmt_wr_hdr_5[21]), + .Q(com_cmm_u_cmm_errman_reg_cmt_wr_hdr[21]), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_errman_reg_cmt_wr_hdr_20_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_reg_cmt_wr_hdr_5[20]), + .Q(com_cmm_u_cmm_errman_reg_cmt_wr_hdr[20]), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_errman_reg_cmt_wr_hdr_19_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_reg_cmt_wr_hdr_5[19]), + .Q(com_cmm_u_cmm_errman_reg_cmt_wr_hdr[19]), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_errman_reg_cmt_wr_hdr_18_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_reg_cmt_wr_hdr_5[18]), + .Q(com_cmm_u_cmm_errman_reg_cmt_wr_hdr[18]), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_errman_reg_cmt_wr_hdr_17_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_reg_cmt_wr_hdr_5[17]), + .Q(com_cmm_u_cmm_errman_reg_cmt_wr_hdr[17]), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_errman_reg_cmt_wr_hdr_16_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_reg_cmt_wr_hdr_5[16]), + .Q(com_cmm_u_cmm_errman_reg_cmt_wr_hdr[16]), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_errman_reg_cmt_wr_hdr_15_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_reg_cmt_wr_hdr_5[15]), + .Q(com_cmm_u_cmm_errman_reg_cmt_wr_hdr[15]), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_errman_reg_cmt_wr_hdr_14_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_reg_cmt_wr_hdr_5[14]), + .Q(com_cmm_u_cmm_errman_reg_cmt_wr_hdr[14]), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_errman_reg_cmt_wr_hdr_13_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_reg_cmt_wr_hdr_5[13]), + .Q(com_cmm_u_cmm_errman_reg_cmt_wr_hdr[13]), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_errman_reg_cmt_wr_hdr_12_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_reg_cmt_wr_hdr_5[12]), + .Q(com_cmm_u_cmm_errman_reg_cmt_wr_hdr[12]), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_errman_reg_cmt_wr_hdr_11_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_reg_cmt_wr_hdr_5[11]), + .Q(com_cmm_u_cmm_errman_reg_cmt_wr_hdr[11]), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_errman_reg_cmt_wr_hdr_10_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_reg_cmt_wr_hdr_5[10]), + .Q(com_cmm_u_cmm_errman_reg_cmt_wr_hdr[10]), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_errman_reg_cmt_wr_hdr_39_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_reg_cmt_wr_hdr_5[39]), + .Q(com_cmm_u_cmm_errman_reg_cmt_wr_hdr[39]), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_errman_reg_cmt_wr_hdr_38_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_reg_cmt_wr_hdr_5[38]), + .Q(com_cmm_u_cmm_errman_reg_cmt_wr_hdr[38]), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_errman_reg_cmt_wr_hdr_37_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_reg_cmt_wr_hdr_5[37]), + .Q(com_cmm_u_cmm_errman_reg_cmt_wr_hdr[37]), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_errman_reg_cmt_wr_hdr_36_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_reg_cmt_wr_hdr_5[36]), + .Q(com_cmm_u_cmm_errman_reg_cmt_wr_hdr[36]), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_errman_reg_cmt_wr_hdr_35_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_reg_cmt_wr_hdr_5[35]), + .Q(com_cmm_u_cmm_errman_reg_cmt_wr_hdr[35]), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_errman_reg_cmt_wr_hdr_34_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_reg_cmt_wr_hdr_5[34]), + .Q(com_cmm_u_cmm_errman_reg_cmt_wr_hdr[34]), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_errman_reg_cmt_wr_hdr_33_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_reg_cmt_wr_hdr_5[33]), + .Q(com_cmm_u_cmm_errman_reg_cmt_wr_hdr[33]), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_errman_reg_cmt_wr_hdr_32_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_reg_cmt_wr_hdr_5[32]), + .Q(com_cmm_u_cmm_errman_reg_cmt_wr_hdr[32]), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_errman_reg_cmt_wr_hdr_31_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_reg_cmt_wr_hdr_5[31]), + .Q(com_cmm_u_cmm_errman_reg_cmt_wr_hdr[31]), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_errman_reg_cmt_wr_hdr_30_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_reg_cmt_wr_hdr_5[30]), + .Q(com_cmm_u_cmm_errman_reg_cmt_wr_hdr[30]), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_errman_reg_cmt_wr_hdr_29_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_reg_cmt_wr_hdr_5[29]), + .Q(com_cmm_u_cmm_errman_reg_cmt_wr_hdr[29]), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_errman_reg_cmt_wr_hdr_28_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_reg_cmt_wr_hdr_5[28]), + .Q(com_cmm_u_cmm_errman_reg_cmt_wr_hdr[28]), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_errman_reg_cmt_wr_hdr_27_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_reg_cmt_wr_hdr_5[27]), + .Q(com_cmm_u_cmm_errman_reg_cmt_wr_hdr[27]), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_errman_reg_cmt_wr_hdr_26_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_reg_cmt_wr_hdr_5[26]), + .Q(com_cmm_u_cmm_errman_reg_cmt_wr_hdr[26]), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_errman_reg_cmt_wr_hdr_25_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_reg_cmt_wr_hdr_5[25]), + .Q(com_cmm_u_cmm_errman_reg_cmt_wr_hdr[25]), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_errman_reg_cfg_wp_1_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_reg_cfg_wp_4[1]), + .Q(com_cmm_u_cmm_errman_reg_cfg_wp[1]), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_errman_reg_cfg_wp_0_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_reg_cfg_wp_4[0]), + .Q(com_cmm_u_cmm_errman_reg_cfg_wp[0]), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_errman_reg_cmt_wp_1_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_reg_cmt_wp_4[1]), + .Q(com_cmm_u_cmm_errman_reg_cmt_wp[1]), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_errman_reg_cmt_wp_0_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_reg_cmt_wp_4[0]), + .Q(com_cmm_u_cmm_errman_reg_cmt_wp[0]), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_errman_reg_cmt_wr_hdr_48_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_N_48855_i), + .Q(com_cmm_u_cmm_errman_reg_cmt_wr_hdr[48]), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_errman_reg_cmt_wr_hdr_47_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_reg_cmt_wr_hdr_5[47]), + .Q(com_cmm_u_cmm_errman_reg_cmt_wr_hdr[47]), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_errman_reg_cmt_wr_hdr_46_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_reg_cmt_wr_hdr_5[46]), + .Q(com_cmm_u_cmm_errman_reg_cmt_wr_hdr[46]), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_errman_reg_cmt_wr_hdr_45_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_reg_cmt_wr_hdr_5[45]), + .Q(com_cmm_u_cmm_errman_reg_cmt_wr_hdr[45]), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_errman_reg_cmt_wr_hdr_44_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_reg_cmt_wr_hdr_5[44]), + .Q(com_cmm_u_cmm_errman_reg_cmt_wr_hdr[44]), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_errman_reg_cmt_wr_hdr_43_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_reg_cmt_wr_hdr_5[43]), + .Q(com_cmm_u_cmm_errman_reg_cmt_wr_hdr[43]), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_errman_reg_cmt_wr_hdr_42_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_reg_cmt_wr_hdr_5[42]), + .Q(com_cmm_u_cmm_errman_reg_cmt_wr_hdr[42]), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_errman_reg_cmt_wr_hdr_41_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_reg_cmt_wr_hdr_5[41]), + .Q(com_cmm_u_cmm_errman_reg_cmt_wr_hdr[41]), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_errman_reg_cmt_wr_hdr_40_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_reg_cmt_wr_hdr_5[40]), + .Q(com_cmm_u_cmm_errman_reg_cmt_wr_hdr[40]), + .CLR(com_cmm_rst_267) + ); + INV com_cmm_u_cmm_errman_cor_num_i_2_ ( + .I(com_cmm_u_cmm_errman_cor_num[2]), + .O(com_cmm_u_cmm_errman_cor_num_i[2]) + ); + INV com_cmm_u_cmm_errman_nfl_num_i_2_ ( + .I(com_cmm_u_cmm_errman_nfl_num[2]), + .O(com_cmm_u_cmm_errman_nfl_num_i[2]) + ); + defparam com_cmm_u_cmm_errman_reg_signaledsystemerror_9_i_0_0_0.INIT = 16'h8088; + LUT4_L com_cmm_u_cmm_errman_reg_signaledsystemerror_9_i_0_0_0 ( + .I0(NlwRenamedSig_OI_cfg_command_8_), + .I1(com_cmm_gnt_errman), + .I2(com_cmm_u_cmm_errman_cs_is_nfl_4877), + .I3(com_cmm_u_cmm_errman_reg_signaledsystemerror_9_i_0_0_0_1_4876), + .LO(com_cmm_u_cmm_errman_N_15633_i) + ); + FDR com_cmm_u_cmm_errman_wtd_cor_reg_decr_cor ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_wtd_cor_N_48971_i_0), + .Q(com_cmm_u_cmm_errman_reg_decr_cor), + .R(com_cmm_rst_267) + ); + FDR com_cmm_u_cmm_errman_wtd_cor_reg_inc_dec_b ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_wtd_cor_N_50354_i_4878), + .Q(com_cmm_u_cmm_errman_cor_add_sub_b), + .R(com_cmm_rst_267) + ); + FDS com_cmm_u_cmm_errman_wtd_cor_add_input_two_n_d ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_replay_vld_i_4797), + .Q(com_cmm_u_cmm_errman_wtd_cor_add_input_two_n_d_262), + .S(com_cmm_rst_267) + ); + FDS com_cmm_u_cmm_errman_wtd_cor_add_input_three_n_d ( + .C(NlwRenamedSig_OI_trn_clk), + .D(N_38550_i), + .Q(com_cmm_u_cmm_errman_wtd_cor_add_input_three_n_d_261), + .S(com_cmm_rst_267) + ); + FDS com_cmm_u_cmm_errman_wtd_cor_add_input_six_n_d ( + .C(NlwRenamedSig_OI_trn_clk), + .D(cfg_err_cor_n), + .Q(com_cmm_u_cmm_errman_wtd_cor_add_input_six_n_d_260), + .S(com_cmm_rst_267) + ); + FDS com_cmm_u_cmm_errman_wtd_cor_add_input_four_n_d ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmml_bad_dllp_err_n), + .Q(com_cmm_u_cmm_errman_wtd_cor_add_input_four_n_d_244), + .S(com_cmm_rst_267) + ); + FDS com_cmm_u_cmm_errman_wtd_cor_add_input_five_n_d ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_N_42551_i_4795), + .Q(com_cmm_u_cmm_errman_wtd_cor_add_input_five_n_d_243), + .S(com_cmm_rst_267) + ); + FDR com_cmm_u_cmm_errman_wtd_cor_add_input_one_d ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_reg_detectedcorrectable_3_i_0_0_a2_0_4794), + .Q(com_cmm_u_cmm_errman_wtd_cor_add_input_one_d_259), + .R(com_cmm_rst_267) + ); + FDR com_cmm_u_cmm_errman_wtd_cor_to_incr_0_dreg_0_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(N_62724_i_245), + .Q(com_cmm_u_cmm_errman_cor_num_int[0]), + .R(com_cmm_rst_267) + ); + FDR com_cmm_u_cmm_errman_wtd_cor_to_incr_0_dreg_1_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_wtd_cor_to_incr_0df1), + .Q(com_cmm_u_cmm_errman_cor_num_int[1]), + .R(com_cmm_rst_267) + ); + FDR com_cmm_u_cmm_errman_wtd_cor_to_incr_0_dreg_2_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_wtd_cor_to_incr_0df2), + .Q(com_cmm_u_cmm_errman_cor_num_int[2]), + .R(com_cmm_rst_267) + ); + defparam com_cmm_u_cmm_errman_wtd_cor_un4_reg_inc_dec_b_0_a2_0_a2_0_o3_0_2.INIT = 16'h8000; + LUT4 com_cmm_u_cmm_errman_wtd_cor_un4_reg_inc_dec_b_0_a2_0_a2_0_o3_0_2 ( + .I0(com_cmm_u_cmm_errman_wtd_cor_add_input_five_n_d_243), + .I1(com_cmm_u_cmm_errman_wtd_cor_add_input_four_n_d_244), + .I2(com_cmm_u_cmm_errman_wtd_cor_add_input_six_n_d_260), + .I3(com_cmm_u_cmm_errman_wtd_cor_add_input_three_n_d_261), + .O(com_cmm_u_cmm_errman_wtd_cor_un4_reg_inc_dec_b_0_a2_0_a2_0_o3_0_2_4879) + ); + defparam com_cmm_u_cmm_errman_wtd_cor_N_50354_i.INIT = 16'h7FFF; + LUT4_L com_cmm_u_cmm_errman_wtd_cor_N_50354_i ( + .I0(m10_263), + .I1(com_cmm_gnt_errman), + .I2(com_cmm_u_cmm_errman_cs_is_cor_4808), + .I3(com_cmm_u_cmm_errman_wtd_cor_un4_reg_inc_dec_b_0_a2_0_a2_0_o3_0_2_4879), + .LO(com_cmm_u_cmm_errman_wtd_cor_N_50354_i_4878) + ); + defparam com_cmm_u_cmm_errman_wtd_cor_reg_decr_cor_4_0_x3_0_x3_0_x3.INIT = 16'h6AC0; + LUT4_L com_cmm_u_cmm_errman_wtd_cor_reg_decr_cor_4_0_x3_0_x3_0_x3 ( + .I0(m10_263), + .I1(com_cmm_gnt_errman), + .I2(com_cmm_u_cmm_errman_cs_is_cor_4808), + .I3(com_cmm_u_cmm_errman_wtd_cor_un4_reg_inc_dec_b_0_a2_0_a2_0_o3_0_2_4879), + .LO(com_cmm_u_cmm_errman_wtd_cor_N_48971_i_0) + ); + VCC com_cmm_u_cmm_errman_cor_cntr_VCC ( + .P(com_cmm_u_cmm_errman_cor_cntr_VCC_4886) + ); + GND com_cmm_u_cmm_errman_cor_cntr_GND ( + .G(com_cmm_u_cmm_errman_cor_cntr_GND_4882) + ); + MUXCY_L com_cmm_u_cmm_errman_cor_cntr_un14_reg_cnt_cry_0 ( + .CI(com_cmm_u_cmm_errman_cor_cntr_GND_4882), + .DI(com_cmm_u_cmm_errman_cor_cntr_N_20762_i), + .LO(com_cmm_u_cmm_errman_cor_cntr_un14_reg_cnt_cry_0_4880), + .S(com_cmm_u_cmm_errman_cor_cntr_un14_reg_cnt_axb_0_4897) + ); + MUXCY_L com_cmm_u_cmm_errman_cor_cntr_un14_reg_cnt_cry_1 ( + .CI(com_cmm_u_cmm_errman_cor_cntr_un14_reg_cnt_cry_0_4880), + .DI(com_cmm_u_cmm_errman_cor_cntr_N_20764_i), + .LO(com_cmm_u_cmm_errman_cor_cntr_un14_reg_cnt_cry_1_4881), + .S(com_cmm_u_cmm_errman_cor_cntr_un14_reg_cnt_axb_1_4908) + ); + XORCY com_cmm_u_cmm_errman_cor_cntr_un14_reg_cnt_s_1 ( + .CI(com_cmm_u_cmm_errman_cor_cntr_un14_reg_cnt_cry_0_4880), + .LI(com_cmm_u_cmm_errman_cor_cntr_un14_reg_cnt_axb_1_4908), + .O(com_cmm_u_cmm_errman_cor_cntr_un14_reg_cnt_s_1_4894) + ); + MUXCY_L com_cmm_u_cmm_errman_cor_cntr_un14_reg_cnt_cry_2 ( + .CI(com_cmm_u_cmm_errman_cor_cntr_un14_reg_cnt_cry_1_4881), + .DI(com_cmm_u_cmm_errman_cor_cntr_N_20766_i), + .LO(com_cmm_u_cmm_errman_cor_cntr_un14_reg_cnt_cry_2_4883), + .S(com_cmm_u_cmm_errman_cor_cntr_un14_reg_cnt_axb_2_4907) + ); + XORCY com_cmm_u_cmm_errman_cor_cntr_un14_reg_cnt_s_2 ( + .CI(com_cmm_u_cmm_errman_cor_cntr_un14_reg_cnt_cry_1_4881), + .LI(com_cmm_u_cmm_errman_cor_cntr_un14_reg_cnt_axb_2_4907), + .O(com_cmm_u_cmm_errman_cor_cntr_un14_reg_cnt_s_2_4892) + ); + MUXCY com_cmm_u_cmm_errman_cor_cntr_un14_reg_cnt_cry_3 ( + .CI(com_cmm_u_cmm_errman_cor_cntr_un14_reg_cnt_cry_2_4883), + .DI(com_cmm_u_cmm_errman_cor_cntr_GND_4882), + .O(com_cmm_u_cmm_errman_cor_cntr_un14_reg_cnt_cry_3_4888), + .S(com_cmm_u_cmm_errman_cor_cntr_un14_reg_cnt_axb_3_4905) + ); + XORCY com_cmm_u_cmm_errman_cor_cntr_un14_reg_cnt_s_3 ( + .CI(com_cmm_u_cmm_errman_cor_cntr_un14_reg_cnt_cry_2_4883), + .LI(com_cmm_u_cmm_errman_cor_cntr_un14_reg_cnt_axb_3_4905), + .O(com_cmm_u_cmm_errman_cor_cntr_un14_reg_cnt_s_3_4890) + ); + MUXCY_L com_cmm_u_cmm_errman_cor_cntr_un25_reg_cnt_cry_0 ( + .CI(com_cmm_u_cmm_errman_cor_cntr_VCC_4886), + .DI(com_cmm_u_cmm_errman_cor_num_i[0]), + .LO(com_cmm_u_cmm_errman_cor_cntr_un25_reg_cnt_cry_0_4884), + .S(com_cmm_u_cmm_errman_cor_cntr_un25_reg_cnt_axb_0_4896) + ); + MUXCY_L com_cmm_u_cmm_errman_cor_cntr_un25_reg_cnt_cry_1 ( + .CI(com_cmm_u_cmm_errman_cor_cntr_un25_reg_cnt_cry_0_4884), + .DI(com_cmm_u_cmm_errman_cor_num_i[1]), + .LO(com_cmm_u_cmm_errman_cor_cntr_un25_reg_cnt_cry_1_4885), + .S(com_cmm_u_cmm_errman_cor_cntr_un25_reg_cnt_axb_1_4904) + ); + XORCY com_cmm_u_cmm_errman_cor_cntr_un25_reg_cnt_s_1 ( + .CI(com_cmm_u_cmm_errman_cor_cntr_un25_reg_cnt_cry_0_4884), + .LI(com_cmm_u_cmm_errman_cor_cntr_un25_reg_cnt_axb_1_4904), + .O(com_cmm_u_cmm_errman_cor_cntr_un25_reg_cnt_s_1_4895) + ); + MUXCY_L com_cmm_u_cmm_errman_cor_cntr_un25_reg_cnt_cry_2 ( + .CI(com_cmm_u_cmm_errman_cor_cntr_un25_reg_cnt_cry_1_4885), + .DI(com_cmm_u_cmm_errman_cor_num_i[2]), + .LO(com_cmm_u_cmm_errman_cor_cntr_un25_reg_cnt_cry_2_4887), + .S(com_cmm_u_cmm_errman_cor_cntr_un25_reg_cnt_axb_2_4903) + ); + XORCY com_cmm_u_cmm_errman_cor_cntr_un25_reg_cnt_s_2 ( + .CI(com_cmm_u_cmm_errman_cor_cntr_un25_reg_cnt_cry_1_4885), + .LI(com_cmm_u_cmm_errman_cor_cntr_un25_reg_cnt_axb_2_4903), + .O(com_cmm_u_cmm_errman_cor_cntr_un25_reg_cnt_s_2_4893) + ); + MUXCY_L com_cmm_u_cmm_errman_cor_cntr_un25_reg_cnt_cry_3 ( + .CI(com_cmm_u_cmm_errman_cor_cntr_un25_reg_cnt_cry_2_4887), + .DI(com_cmm_u_cmm_errman_cor_cntr_VCC_4886), + .LO(com_cmm_u_cmm_errman_cor_cntr_un25_reg_cnt_cry_3_4901), + .S(com_cmm_u_cmm_errman_cor_cntr_un25_reg_cnt_axb_3_i_i_4902) + ); + XORCY com_cmm_u_cmm_errman_cor_cntr_un25_reg_cnt_s_3 ( + .CI(com_cmm_u_cmm_errman_cor_cntr_un25_reg_cnt_cry_2_4887), + .LI(com_cmm_u_cmm_errman_cor_cntr_un25_reg_cnt_axb_3_i_i_4902), + .O(com_cmm_u_cmm_errman_cor_cntr_un25_reg_cnt_s_3_4891) + ); + defparam com_cmm_u_cmm_errman_cor_cntr_oflow_0_a2_0_a2.INIT = 4'h8; + LUT2 com_cmm_u_cmm_errman_cor_cntr_oflow_0_a2_0_a2 ( + .I0(com_cmm_u_cmm_errman_cor_cntr_reg_extra_4899), + .I1(com_cmm_u_cmm_errman_cor_cntr_reg_inc_dec_b_4898), + .O(com_cmm_u_cmm_errman_cor_cntr_oflow) + ); + defparam com_cmm_u_cmm_errman_cor_cntr_un14_reg_cnt_axb_0.INIT = 4'h9; + LUT2 com_cmm_u_cmm_errman_cor_cntr_un14_reg_cnt_axb_0 ( + .I0(com_cmm_u_cmm_errman_cor_cntr_N_20762_i), + .I1(com_cmm_u_cmm_errman_cor_num_i[0]), + .O(com_cmm_u_cmm_errman_cor_cntr_un14_reg_cnt_axb_0_4897) + ); + defparam com_cmm_u_cmm_errman_cor_cntr_cnt_f0_i_0_0_2_.INIT = 8'h0E; + LUT3 com_cmm_u_cmm_errman_cor_cntr_cnt_f0_i_0_0_2_ ( + .I0(com_cmm_u_cmm_errman_cor_cntr_oflow), + .I1(com_cmm_u_cmm_errman_cor_cntr_reg_cnt[2]), + .I2(com_cmm_u_cmm_errman_cor_cntr_reg_uflow_4906), + .O(com_cmm_u_cmm_errman_cor_cntr_N_20766_i) + ); + defparam com_cmm_u_cmm_errman_cor_cntr_cnt_f0_i_0_0_1_.INIT = 8'h0E; + LUT3 com_cmm_u_cmm_errman_cor_cntr_cnt_f0_i_0_0_1_ ( + .I0(com_cmm_u_cmm_errman_cor_cntr_oflow), + .I1(com_cmm_u_cmm_errman_cor_cntr_reg_cnt[1]), + .I2(com_cmm_u_cmm_errman_cor_cntr_reg_uflow_4906), + .O(com_cmm_u_cmm_errman_cor_cntr_N_20764_i) + ); + defparam com_cmm_u_cmm_errman_cor_cntr_cnt_f0_i_0_0_0_.INIT = 8'h0E; + LUT3 com_cmm_u_cmm_errman_cor_cntr_cnt_f0_i_0_0_0_ ( + .I0(com_cmm_u_cmm_errman_cor_cntr_oflow), + .I1(com_cmm_u_cmm_errman_cor_cntr_reg_cnt[0]), + .I2(com_cmm_u_cmm_errman_cor_cntr_reg_uflow_4906), + .O(com_cmm_u_cmm_errman_cor_cntr_N_20762_i) + ); + defparam com_cmm_u_cmm_errman_cor_cntr_un25_reg_cnt_axb_0.INIT = 4'h6; + LUT2 com_cmm_u_cmm_errman_cor_cntr_un25_reg_cnt_axb_0 ( + .I0(com_cmm_u_cmm_errman_cor_cntr_N_20762_i), + .I1(com_cmm_u_cmm_errman_cor_num_i[0]), + .O(com_cmm_u_cmm_errman_cor_cntr_un25_reg_cnt_axb_0_4896) + ); + defparam com_cmm_u_cmm_errman_cor_cntr_reg_uflow_3_i_a2_0.INIT = 8'h21; + LUT3 com_cmm_u_cmm_errman_cor_cntr_reg_uflow_3_i_a2_0 ( + .I0(com_cmm_u_cmm_errman_cor_num_int[0]), + .I1(com_cmm_u_cmm_errman_cor_num_int[1]), + .I2(com_cmm_u_cmm_errman_reg_decr_cor), + .O(com_cmm_u_cmm_errman_cor_cntr_reg_uflow_3_i_a2_0_4889) + ); + defparam com_cmm_u_cmm_errman_cor_cntr_reg_extra_6_u_0_a2_0_a2_0_a2_0_a2.INIT = 16'hC808; + LUT4_L com_cmm_u_cmm_errman_cor_cntr_reg_extra_6_u_0_a2_0_a2_0_a2_0_a2 ( + .I0(com_cmm_u_cmm_errman_cor_cntr_un25_reg_cnt_s_4_4900), + .I1(NlwRenamedSig_OI_cfg_dcommand[0]), + .I2(com_cmm_u_cmm_errman_cor_add_sub_b), + .I3(com_cmm_u_cmm_errman_cor_cntr_un14_reg_cnt_cry_3_4888), + .LO(com_cmm_u_cmm_errman_cor_cntr_reg_extra_6) + ); + defparam com_cmm_u_cmm_errman_cor_cntr_reg_uflow_3_i.INIT = 16'h2202; + LUT4_L com_cmm_u_cmm_errman_cor_cntr_reg_uflow_3_i ( + .I0(com_cmm_u_cmm_errman_send_cor_3_0_a2_4790), + .I1(com_cmm_u_cmm_errman_cor_add_sub_b), + .I2(com_cmm_u_cmm_errman_cor_cntr_reg_uflow_3_i_a2_0_4889), + .I3(com_cmm_u_cmm_errman_cor_num[2]), + .LO(com_cmm_u_cmm_errman_cor_cntr_N_15408_i) + ); + defparam com_cmm_u_cmm_errman_cor_cntr_reg_cnt_6_0_a2_0_a2_0_a2_0_a2_3_.INIT = 16'hC808; + LUT4_L com_cmm_u_cmm_errman_cor_cntr_reg_cnt_6_0_a2_0_a2_0_a2_0_a2_3_ ( + .I0(com_cmm_u_cmm_errman_cor_cntr_un25_reg_cnt_s_3_4891), + .I1(NlwRenamedSig_OI_cfg_dcommand[0]), + .I2(com_cmm_u_cmm_errman_cor_add_sub_b), + .I3(com_cmm_u_cmm_errman_cor_cntr_un14_reg_cnt_s_3_4890), + .LO(com_cmm_u_cmm_errman_cor_cntr_reg_cnt_6[3]) + ); + defparam com_cmm_u_cmm_errman_cor_cntr_reg_cnt_6_0_a2_0_a2_0_a2_0_a2_2_.INIT = 16'hC808; + LUT4_L com_cmm_u_cmm_errman_cor_cntr_reg_cnt_6_0_a2_0_a2_0_a2_0_a2_2_ ( + .I0(com_cmm_u_cmm_errman_cor_cntr_un25_reg_cnt_s_2_4893), + .I1(NlwRenamedSig_OI_cfg_dcommand[0]), + .I2(com_cmm_u_cmm_errman_cor_add_sub_b), + .I3(com_cmm_u_cmm_errman_cor_cntr_un14_reg_cnt_s_2_4892), + .LO(com_cmm_u_cmm_errman_cor_cntr_reg_cnt_6[2]) + ); + defparam com_cmm_u_cmm_errman_cor_cntr_reg_cnt_6_0_a2_0_a2_0_a2_0_a2_1_.INIT = 16'hC808; + LUT4_L com_cmm_u_cmm_errman_cor_cntr_reg_cnt_6_0_a2_0_a2_0_a2_0_a2_1_ ( + .I0(com_cmm_u_cmm_errman_cor_cntr_un25_reg_cnt_s_1_4895), + .I1(NlwRenamedSig_OI_cfg_dcommand[0]), + .I2(com_cmm_u_cmm_errman_cor_add_sub_b), + .I3(com_cmm_u_cmm_errman_cor_cntr_un14_reg_cnt_s_1_4894), + .LO(com_cmm_u_cmm_errman_cor_cntr_reg_cnt_6[1]) + ); + defparam com_cmm_u_cmm_errman_cor_cntr_reg_cnt_6_0_a2_0_a2_0_a2_0_a2_0_.INIT = 16'h80A2; + LUT4_L com_cmm_u_cmm_errman_cor_cntr_reg_cnt_6_0_a2_0_a2_0_a2_0_a2_0_ ( + .I0(NlwRenamedSig_OI_cfg_dcommand[0]), + .I1(com_cmm_u_cmm_errman_cor_add_sub_b), + .I2(com_cmm_u_cmm_errman_cor_cntr_un14_reg_cnt_axb_0_4897), + .I3(com_cmm_u_cmm_errman_cor_cntr_un25_reg_cnt_axb_0_4896), + .LO(com_cmm_u_cmm_errman_cor_cntr_reg_cnt_6[0]) + ); + defparam com_cmm_u_cmm_errman_cor_cntr_reg_count_7_f0_i_0_0_3_.INIT = 16'h00A8; + LUT4_L com_cmm_u_cmm_errman_cor_cntr_reg_count_7_f0_i_0_0_3_ ( + .I0(NlwRenamedSig_OI_cfg_dcommand[0]), + .I1(com_cmm_u_cmm_errman_cor_cntr_oflow), + .I2(com_cmm_u_cmm_errman_cor_cntr_reg_cnt[3]), + .I3(com_cmm_u_cmm_errman_cor_cntr_reg_uflow_4906), + .LO(com_cmm_u_cmm_errman_cor_cntr_N_20776_i) + ); + defparam com_cmm_u_cmm_errman_cor_cntr_reg_count_7_f0_i_0_0_2_.INIT = 16'h00A8; + LUT4_L com_cmm_u_cmm_errman_cor_cntr_reg_count_7_f0_i_0_0_2_ ( + .I0(NlwRenamedSig_OI_cfg_dcommand[0]), + .I1(com_cmm_u_cmm_errman_cor_cntr_oflow), + .I2(com_cmm_u_cmm_errman_cor_cntr_reg_cnt[2]), + .I3(com_cmm_u_cmm_errman_cor_cntr_reg_uflow_4906), + .LO(com_cmm_u_cmm_errman_cor_cntr_N_20774_i) + ); + defparam com_cmm_u_cmm_errman_cor_cntr_reg_count_7_f0_i_0_0_1_.INIT = 16'h00A8; + LUT4_L com_cmm_u_cmm_errman_cor_cntr_reg_count_7_f0_i_0_0_1_ ( + .I0(NlwRenamedSig_OI_cfg_dcommand[0]), + .I1(com_cmm_u_cmm_errman_cor_cntr_oflow), + .I2(com_cmm_u_cmm_errman_cor_cntr_reg_cnt[1]), + .I3(com_cmm_u_cmm_errman_cor_cntr_reg_uflow_4906), + .LO(com_cmm_u_cmm_errman_cor_cntr_N_20772_i) + ); + defparam com_cmm_u_cmm_errman_cor_cntr_reg_count_7_f0_i_0_0_0_.INIT = 16'h00A8; + LUT4_L com_cmm_u_cmm_errman_cor_cntr_reg_count_7_f0_i_0_0_0_ ( + .I0(NlwRenamedSig_OI_cfg_dcommand[0]), + .I1(com_cmm_u_cmm_errman_cor_cntr_oflow), + .I2(com_cmm_u_cmm_errman_cor_cntr_reg_cnt[0]), + .I3(com_cmm_u_cmm_errman_cor_cntr_reg_uflow_4906), + .LO(com_cmm_u_cmm_errman_cor_cntr_N_20770_i) + ); + FDC com_cmm_u_cmm_errman_cor_cntr_reg_inc_dec_b ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_cor_add_sub_b), + .Q(com_cmm_u_cmm_errman_cor_cntr_reg_inc_dec_b_4898), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_errman_cor_cntr_reg_extra ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_cor_cntr_reg_extra_6), + .Q(com_cmm_u_cmm_errman_cor_cntr_reg_extra_4899), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_errman_cor_cntr_reg_uflow ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_cor_cntr_N_15408_i), + .Q(com_cmm_u_cmm_errman_cor_cntr_reg_uflow_4906), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_errman_cor_cntr_reg_cnt_3_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_cor_cntr_reg_cnt_6[3]), + .Q(com_cmm_u_cmm_errman_cor_cntr_reg_cnt[3]), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_errman_cor_cntr_reg_cnt_2_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_cor_cntr_reg_cnt_6[2]), + .Q(com_cmm_u_cmm_errman_cor_cntr_reg_cnt[2]), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_errman_cor_cntr_reg_cnt_1_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_cor_cntr_reg_cnt_6[1]), + .Q(com_cmm_u_cmm_errman_cor_cntr_reg_cnt[1]), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_errman_cor_cntr_reg_cnt_0_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_cor_cntr_reg_cnt_6[0]), + .Q(com_cmm_u_cmm_errman_cor_cntr_reg_cnt[0]), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_errman_cor_cntr_reg_count_3_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_cor_cntr_N_20776_i), + .Q(com_cmm_u_cmm_errman_cnt_cor[3]), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_errman_cor_cntr_reg_count_2_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_cor_cntr_N_20774_i), + .Q(com_cmm_u_cmm_errman_cnt_cor[2]), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_errman_cor_cntr_reg_count_1_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_cor_cntr_N_20772_i), + .Q(com_cmm_u_cmm_errman_cnt_cor[1]), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_errman_cor_cntr_reg_count_0_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_cor_cntr_N_20770_i), + .Q(com_cmm_u_cmm_errman_cnt_cor[0]), + .CLR(com_cmm_rst_267) + ); + defparam com_cmm_u_cmm_errman_cor_cntr_un25_reg_cnt_s_4.INIT = 4'h1; + LUT1_L com_cmm_u_cmm_errman_cor_cntr_un25_reg_cnt_s_4 ( + .I0(com_cmm_u_cmm_errman_cor_cntr_un25_reg_cnt_cry_3_4901), + .LO(com_cmm_u_cmm_errman_cor_cntr_un25_reg_cnt_s_4_4900) + ); + defparam com_cmm_u_cmm_errman_cor_cntr_un25_reg_cnt_axb_3_i_i.INIT = 8'hF1; + LUT3 com_cmm_u_cmm_errman_cor_cntr_un25_reg_cnt_axb_3_i_i ( + .I0(com_cmm_u_cmm_errman_cor_cntr_oflow), + .I1(com_cmm_u_cmm_errman_cor_cntr_reg_cnt[3]), + .I2(com_cmm_u_cmm_errman_cor_cntr_reg_uflow_4906), + .O(com_cmm_u_cmm_errman_cor_cntr_un25_reg_cnt_axb_3_i_i_4902) + ); + defparam com_cmm_u_cmm_errman_cor_cntr_un25_reg_cnt_axb_2.INIT = 4'h9; + LUT2 com_cmm_u_cmm_errman_cor_cntr_un25_reg_cnt_axb_2 ( + .I0(com_cmm_u_cmm_errman_cor_cntr_N_20766_i), + .I1(com_cmm_u_cmm_errman_cor_num[2]), + .O(com_cmm_u_cmm_errman_cor_cntr_un25_reg_cnt_axb_2_4903) + ); + defparam com_cmm_u_cmm_errman_cor_cntr_un25_reg_cnt_axb_1.INIT = 16'h96A5; + LUT4 com_cmm_u_cmm_errman_cor_cntr_un25_reg_cnt_axb_1 ( + .I0(com_cmm_u_cmm_errman_cor_cntr_N_20764_i), + .I1(com_cmm_u_cmm_errman_cor_num_int[0]), + .I2(com_cmm_u_cmm_errman_cor_num_int[1]), + .I3(com_cmm_u_cmm_errman_reg_decr_cor), + .O(com_cmm_u_cmm_errman_cor_cntr_un25_reg_cnt_axb_1_4904) + ); + defparam com_cmm_u_cmm_errman_cor_cntr_un14_reg_cnt_axb_3.INIT = 8'h0E; + LUT3 com_cmm_u_cmm_errman_cor_cntr_un14_reg_cnt_axb_3 ( + .I0(com_cmm_u_cmm_errman_cor_cntr_oflow), + .I1(com_cmm_u_cmm_errman_cor_cntr_reg_cnt[3]), + .I2(com_cmm_u_cmm_errman_cor_cntr_reg_uflow_4906), + .O(com_cmm_u_cmm_errman_cor_cntr_un14_reg_cnt_axb_3_4905) + ); + defparam com_cmm_u_cmm_errman_cor_cntr_un14_reg_cnt_axb_2.INIT = 4'h6; + LUT2 com_cmm_u_cmm_errman_cor_cntr_un14_reg_cnt_axb_2 ( + .I0(com_cmm_u_cmm_errman_cor_cntr_N_20766_i), + .I1(com_cmm_u_cmm_errman_cor_num[2]), + .O(com_cmm_u_cmm_errman_cor_cntr_un14_reg_cnt_axb_2_4907) + ); + defparam com_cmm_u_cmm_errman_cor_cntr_un14_reg_cnt_axb_1.INIT = 16'h695A; + LUT4 com_cmm_u_cmm_errman_cor_cntr_un14_reg_cnt_axb_1 ( + .I0(com_cmm_u_cmm_errman_cor_cntr_N_20764_i), + .I1(com_cmm_u_cmm_errman_cor_num_int[0]), + .I2(com_cmm_u_cmm_errman_cor_num_int[1]), + .I3(com_cmm_u_cmm_errman_reg_decr_cor), + .O(com_cmm_u_cmm_errman_cor_cntr_un14_reg_cnt_axb_1_4908) + ); + FDR com_cmm_u_cmm_errman_wtd_nfl_reg_decr_cor ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_wtd_nfl_N_48974_i_0), + .Q(com_cmm_u_cmm_errman_reg_decr_nfl), + .R(com_cmm_rst_267) + ); + FDR com_cmm_u_cmm_errman_wtd_nfl_reg_inc_dec_b ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_wtd_nfl_un4_reg_inc_dec_b_i_4909), + .Q(com_cmm_u_cmm_errman_nfl_add_sub_b), + .R(com_cmm_rst_267) + ); + FDS com_cmm_u_cmm_errman_wtd_nfl_add_input_two_n_d ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_N_68491_i_4800), + .Q(com_cmm_u_cmm_errman_wtd_nfl_add_input_two_n_d_239), + .S(com_cmm_rst_267) + ); + FDS com_cmm_u_cmm_errman_wtd_nfl_add_input_four_n_d ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_N_68492_i_4799), + .Q(com_cmm_u_cmm_errman_wtd_nfl_add_input_four_n_d_237), + .S(com_cmm_rst_267) + ); + FDS com_cmm_u_cmm_errman_wtd_nfl_add_input_five_n_d ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_N_68760_i_4798), + .Q(com_cmm_u_cmm_errman_wtd_nfl_add_input_five_n_d_236), + .S(com_cmm_rst_267) + ); + FDR com_cmm_u_cmm_errman_wtd_nfl_add_input_one_d ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_N_15818_i), + .Q(com_cmm_u_cmm_errman_wtd_nfl_add_input_one_d_238), + .R(com_cmm_rst_267) + ); + FDR com_cmm_u_cmm_errman_wtd_nfl_to_incr_0_dreg_0_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(N_6_i_240), + .Q(com_cmm_u_cmm_errman_to_incr_0ro), + .R(com_cmm_rst_267) + ); + FDR com_cmm_u_cmm_errman_wtd_nfl_to_incr_0_dreg_1_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_wtd_nfl_to_incr_0df1), + .Q(com_cmm_u_cmm_errman_to_incr_1ro), + .R(com_cmm_rst_267) + ); + FDR com_cmm_u_cmm_errman_wtd_nfl_to_incr_0_dreg_2_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_wtd_nfl_to_incr_0df2), + .Q(com_cmm_u_cmm_errman_to_incr_2ro), + .R(com_cmm_rst_267) + ); + defparam com_cmm_u_cmm_errman_wtd_nfl_un4_reg_inc_dec_b_0_a2_0_a2_0_a2_0_o3_0.INIT = 16'h0800; + LUT4 com_cmm_u_cmm_errman_wtd_nfl_un4_reg_inc_dec_b_0_a2_0_a2_0_a2_0_o3_0 ( + .I0(com_cmm_u_cmm_errman_wtd_nfl_add_input_five_n_d_236), + .I1(com_cmm_u_cmm_errman_wtd_nfl_add_input_four_n_d_237), + .I2(com_cmm_u_cmm_errman_wtd_nfl_add_input_one_d_238), + .I3(com_cmm_u_cmm_errman_wtd_nfl_add_input_two_n_d_239), + .O(com_cmm_u_cmm_errman_wtd_nfl_N_48970_i) + ); + defparam com_cmm_u_cmm_errman_wtd_nfl_un4_reg_inc_dec_b_i.INIT = 8'h7F; + LUT3_L com_cmm_u_cmm_errman_wtd_nfl_un4_reg_inc_dec_b_i ( + .I0(com_cmm_u_cmm_errman_wtd_nfl_N_48970_i), + .I1(com_cmm_gnt_errman), + .I2(com_cmm_u_cmm_errman_cs_is_nfl_4877), + .LO(com_cmm_u_cmm_errman_wtd_nfl_un4_reg_inc_dec_b_i_4909) + ); + defparam com_cmm_u_cmm_errman_wtd_nfl_reg_decr_cor_4_0_x3_0_x3_0_x3_0_x3.INIT = 8'h6A; + LUT3_L com_cmm_u_cmm_errman_wtd_nfl_reg_decr_cor_4_0_x3_0_x3_0_x3_0_x3 ( + .I0(com_cmm_u_cmm_errman_wtd_nfl_N_48970_i), + .I1(com_cmm_gnt_errman), + .I2(com_cmm_u_cmm_errman_cs_is_nfl_4877), + .LO(com_cmm_u_cmm_errman_wtd_nfl_N_48974_i_0) + ); + VCC com_cmm_u_cmm_errman_nfl_cntr_VCC ( + .P(com_cmm_u_cmm_errman_nfl_cntr_VCC_4916) + ); + GND com_cmm_u_cmm_errman_nfl_cntr_GND ( + .G(com_cmm_u_cmm_errman_nfl_cntr_GND_4912) + ); + MUXCY_L com_cmm_u_cmm_errman_nfl_cntr_un14_reg_cnt_cry_0 ( + .CI(com_cmm_u_cmm_errman_nfl_cntr_GND_4912), + .DI(com_cmm_u_cmm_errman_nfl_cntr_N_22217_i), + .LO(com_cmm_u_cmm_errman_nfl_cntr_un14_reg_cnt_cry_0_4910), + .S(com_cmm_u_cmm_errman_nfl_cntr_un14_reg_cnt[0]) + ); + MUXCY_L com_cmm_u_cmm_errman_nfl_cntr_un14_reg_cnt_cry_1 ( + .CI(com_cmm_u_cmm_errman_nfl_cntr_un14_reg_cnt_cry_0_4910), + .DI(com_cmm_u_cmm_errman_nfl_cntr_N_22219_i), + .LO(com_cmm_u_cmm_errman_nfl_cntr_un14_reg_cnt_cry_1_4911), + .S(com_cmm_u_cmm_errman_nfl_cntr_un14_reg_cnt_axb_1_4929) + ); + XORCY com_cmm_u_cmm_errman_nfl_cntr_un14_reg_cnt_s_1 ( + .CI(com_cmm_u_cmm_errman_nfl_cntr_un14_reg_cnt_cry_0_4910), + .LI(com_cmm_u_cmm_errman_nfl_cntr_un14_reg_cnt_axb_1_4929), + .O(com_cmm_u_cmm_errman_nfl_cntr_un14_reg_cnt[1]) + ); + MUXCY_L com_cmm_u_cmm_errman_nfl_cntr_un14_reg_cnt_cry_2 ( + .CI(com_cmm_u_cmm_errman_nfl_cntr_un14_reg_cnt_cry_1_4911), + .DI(com_cmm_u_cmm_errman_nfl_cntr_N_22221_i), + .LO(com_cmm_u_cmm_errman_nfl_cntr_un14_reg_cnt_cry_2_4913), + .S(com_cmm_u_cmm_errman_nfl_cntr_un14_reg_cnt_axb_2_4928) + ); + XORCY com_cmm_u_cmm_errman_nfl_cntr_un14_reg_cnt_s_2 ( + .CI(com_cmm_u_cmm_errman_nfl_cntr_un14_reg_cnt_cry_1_4911), + .LI(com_cmm_u_cmm_errman_nfl_cntr_un14_reg_cnt_axb_2_4928), + .O(com_cmm_u_cmm_errman_nfl_cntr_un14_reg_cnt[2]) + ); + MUXCY com_cmm_u_cmm_errman_nfl_cntr_un14_reg_cnt_cry_3 ( + .CI(com_cmm_u_cmm_errman_nfl_cntr_un14_reg_cnt_cry_2_4913), + .DI(com_cmm_u_cmm_errman_nfl_cntr_GND_4912), + .O(com_cmm_u_cmm_errman_nfl_cntr_un14_reg_cnt[4]), + .S(com_cmm_u_cmm_errman_nfl_cntr_un14_reg_cnt_axb_3_4927) + ); + XORCY com_cmm_u_cmm_errman_nfl_cntr_un14_reg_cnt_s_3 ( + .CI(com_cmm_u_cmm_errman_nfl_cntr_un14_reg_cnt_cry_2_4913), + .LI(com_cmm_u_cmm_errman_nfl_cntr_un14_reg_cnt_axb_3_4927), + .O(com_cmm_u_cmm_errman_nfl_cntr_un14_reg_cnt[3]) + ); + MUXCY_L com_cmm_u_cmm_errman_nfl_cntr_un25_reg_cnt_cry_0 ( + .CI(com_cmm_u_cmm_errman_nfl_cntr_VCC_4916), + .DI(com_cmm_u_cmm_errman_nfl_num_i[0]), + .LO(com_cmm_u_cmm_errman_nfl_cntr_un25_reg_cnt_cry_0_4914), + .S(com_cmm_u_cmm_errman_nfl_cntr_un25_reg_cnt_axb_0_4919) + ); + MUXCY_L com_cmm_u_cmm_errman_nfl_cntr_un25_reg_cnt_cry_1 ( + .CI(com_cmm_u_cmm_errman_nfl_cntr_un25_reg_cnt_cry_0_4914), + .DI(com_cmm_u_cmm_errman_nfl_num_i[1]), + .LO(com_cmm_u_cmm_errman_nfl_cntr_un25_reg_cnt_cry_1_4915), + .S(com_cmm_u_cmm_errman_nfl_cntr_un25_reg_cnt_axb_1_4926) + ); + XORCY com_cmm_u_cmm_errman_nfl_cntr_un25_reg_cnt_s_1 ( + .CI(com_cmm_u_cmm_errman_nfl_cntr_un25_reg_cnt_cry_0_4914), + .LI(com_cmm_u_cmm_errman_nfl_cntr_un25_reg_cnt_axb_1_4926), + .O(com_cmm_u_cmm_errman_nfl_cntr_un25_reg_cnt[1]) + ); + MUXCY_L com_cmm_u_cmm_errman_nfl_cntr_un25_reg_cnt_cry_2 ( + .CI(com_cmm_u_cmm_errman_nfl_cntr_un25_reg_cnt_cry_1_4915), + .DI(com_cmm_u_cmm_errman_nfl_num_i[2]), + .LO(com_cmm_u_cmm_errman_nfl_cntr_un25_reg_cnt_cry_2_4917), + .S(com_cmm_u_cmm_errman_nfl_cntr_un25_reg_cnt_axb_2_4925) + ); + XORCY com_cmm_u_cmm_errman_nfl_cntr_un25_reg_cnt_s_2 ( + .CI(com_cmm_u_cmm_errman_nfl_cntr_un25_reg_cnt_cry_1_4915), + .LI(com_cmm_u_cmm_errman_nfl_cntr_un25_reg_cnt_axb_2_4925), + .O(com_cmm_u_cmm_errman_nfl_cntr_un25_reg_cnt[2]) + ); + MUXCY_L com_cmm_u_cmm_errman_nfl_cntr_un25_reg_cnt_cry_3 ( + .CI(com_cmm_u_cmm_errman_nfl_cntr_un25_reg_cnt_cry_2_4917), + .DI(com_cmm_u_cmm_errman_nfl_cntr_VCC_4916), + .LO(com_cmm_u_cmm_errman_nfl_cntr_un25_reg_cnt_cry_3_4923), + .S(com_cmm_u_cmm_errman_nfl_cntr_un25_reg_cnt_axb_3_i_i_4924) + ); + XORCY com_cmm_u_cmm_errman_nfl_cntr_un25_reg_cnt_s_3 ( + .CI(com_cmm_u_cmm_errman_nfl_cntr_un25_reg_cnt_cry_2_4917), + .LI(com_cmm_u_cmm_errman_nfl_cntr_un25_reg_cnt_axb_3_i_i_4924), + .O(com_cmm_u_cmm_errman_nfl_cntr_un25_reg_cnt[3]) + ); + defparam com_cmm_u_cmm_errman_nfl_cntr_cnt_f0_i_0_.INIT = 16'h00EA; + LUT4 com_cmm_u_cmm_errman_nfl_cntr_cnt_f0_i_0_ ( + .I0(com_cmm_u_cmm_errman_nfl_cntr_reg_cnt[0]), + .I1(com_cmm_u_cmm_errman_nfl_cntr_reg_extra_4921), + .I2(com_cmm_u_cmm_errman_nfl_cntr_reg_inc_dec_b_4920), + .I3(com_cmm_u_cmm_errman_nfl_cntr_reg_uflow_4922), + .O(com_cmm_u_cmm_errman_nfl_cntr_N_22217_i) + ); + defparam com_cmm_u_cmm_errman_nfl_cntr_cnt_f0_i_1_.INIT = 16'h00EA; + LUT4 com_cmm_u_cmm_errman_nfl_cntr_cnt_f0_i_1_ ( + .I0(com_cmm_u_cmm_errman_nfl_cntr_reg_cnt[1]), + .I1(com_cmm_u_cmm_errman_nfl_cntr_reg_extra_4921), + .I2(com_cmm_u_cmm_errman_nfl_cntr_reg_inc_dec_b_4920), + .I3(com_cmm_u_cmm_errman_nfl_cntr_reg_uflow_4922), + .O(com_cmm_u_cmm_errman_nfl_cntr_N_22219_i) + ); + defparam com_cmm_u_cmm_errman_nfl_cntr_cnt_f0_i_2_.INIT = 16'h00EA; + LUT4 com_cmm_u_cmm_errman_nfl_cntr_cnt_f0_i_2_ ( + .I0(com_cmm_u_cmm_errman_nfl_cntr_reg_cnt[2]), + .I1(com_cmm_u_cmm_errman_nfl_cntr_reg_extra_4921), + .I2(com_cmm_u_cmm_errman_nfl_cntr_reg_inc_dec_b_4920), + .I3(com_cmm_u_cmm_errman_nfl_cntr_reg_uflow_4922), + .O(com_cmm_u_cmm_errman_nfl_cntr_N_22221_i) + ); + defparam com_cmm_u_cmm_errman_nfl_cntr_cnt_f0_i_3_.INIT = 16'h00EA; + LUT4 com_cmm_u_cmm_errman_nfl_cntr_cnt_f0_i_3_ ( + .I0(com_cmm_u_cmm_errman_nfl_cntr_reg_cnt[3]), + .I1(com_cmm_u_cmm_errman_nfl_cntr_reg_extra_4921), + .I2(com_cmm_u_cmm_errman_nfl_cntr_reg_inc_dec_b_4920), + .I3(com_cmm_u_cmm_errman_nfl_cntr_reg_uflow_4922), + .O(com_cmm_u_cmm_errman_nfl_cntr_un25_reg_cnt_axb_3_i) + ); + defparam com_cmm_u_cmm_errman_nfl_cntr_un14_reg_cnt_axb_0.INIT = 4'h9; + LUT2 com_cmm_u_cmm_errman_nfl_cntr_un14_reg_cnt_axb_0 ( + .I0(com_cmm_u_cmm_errman_nfl_cntr_N_22217_i), + .I1(com_cmm_u_cmm_errman_nfl_num_i[0]), + .O(com_cmm_u_cmm_errman_nfl_cntr_un14_reg_cnt[0]) + ); + defparam com_cmm_u_cmm_errman_nfl_cntr_un25_reg_cnt_axb_0.INIT = 4'h6; + LUT2 com_cmm_u_cmm_errman_nfl_cntr_un25_reg_cnt_axb_0 ( + .I0(com_cmm_u_cmm_errman_nfl_cntr_N_22217_i), + .I1(com_cmm_u_cmm_errman_nfl_num_i[0]), + .O(com_cmm_u_cmm_errman_nfl_cntr_un25_reg_cnt_axb_0_4919) + ); + defparam com_cmm_u_cmm_errman_nfl_cntr_reg_uflow_3_i_a2_0.INIT = 16'h8444; + LUT4 com_cmm_u_cmm_errman_nfl_cntr_reg_uflow_3_i_a2_0 ( + .I0(com_cmm_u_cmm_errman_nfl_num_c1_4789), + .I1(com_cmm_u_cmm_errman_nfl_num_i[0]), + .I2(com_cmm_u_cmm_errman_to_incr_1ro), + .I3(com_cmm_u_cmm_pm_dev_power_state_eq_d0), + .O(com_cmm_u_cmm_errman_nfl_cntr_reg_uflow_3_i_a2_0_4918) + ); + defparam com_cmm_u_cmm_errman_nfl_cntr_reg_extra_6_0_u_i_m2_0.INIT = 8'hD8; + LUT3_L com_cmm_u_cmm_errman_nfl_cntr_reg_extra_6_0_u_i_m2_0 ( + .I0(com_cmm_u_cmm_errman_nfl_add_sub_b), + .I1(com_cmm_u_cmm_errman_nfl_cntr_un14_reg_cnt[4]), + .I2(com_cmm_u_cmm_errman_nfl_cntr_un25_reg_cnt[4]), + .LO(com_cmm_u_cmm_errman_nfl_cntr_reg_extra_6_0_u_i_m2_0_1) + ); + defparam com_cmm_u_cmm_errman_nfl_cntr_reg_uflow_3_i.INIT = 16'h5010; + LUT4_L com_cmm_u_cmm_errman_nfl_cntr_reg_uflow_3_i ( + .I0(com_cmm_u_cmm_errman_nfl_add_sub_b), + .I1(com_cmm_u_cmm_errman_nfl_cntr_reg_uflow_3_i_a2_0_4918), + .I2(com_cmm_u_cmm_errman_un1_reg_uflow_3_0), + .I3(com_cmm_u_cmm_errman_nfl_num[2]), + .LO(com_cmm_u_cmm_errman_nfl_cntr_N_15453_i) + ); + defparam com_cmm_u_cmm_errman_nfl_cntr_reg_cnt_6_0_i_m2_0_3_.INIT = 8'hD8; + LUT3_L com_cmm_u_cmm_errman_nfl_cntr_reg_cnt_6_0_i_m2_0_3_ ( + .I0(com_cmm_u_cmm_errman_nfl_add_sub_b), + .I1(com_cmm_u_cmm_errman_nfl_cntr_un14_reg_cnt[3]), + .I2(com_cmm_u_cmm_errman_nfl_cntr_un25_reg_cnt[3]), + .LO(com_cmm_u_cmm_errman_nfl_cntr_reg_cnt_6_0_i_m2_0_1[3]) + ); + defparam com_cmm_u_cmm_errman_nfl_cntr_reg_cnt_6_0_i_m2_0_2_.INIT = 8'hD8; + LUT3_L com_cmm_u_cmm_errman_nfl_cntr_reg_cnt_6_0_i_m2_0_2_ ( + .I0(com_cmm_u_cmm_errman_nfl_add_sub_b), + .I1(com_cmm_u_cmm_errman_nfl_cntr_un14_reg_cnt[2]), + .I2(com_cmm_u_cmm_errman_nfl_cntr_un25_reg_cnt[2]), + .LO(com_cmm_u_cmm_errman_nfl_cntr_reg_cnt_6_0_i_m2_0_1[2]) + ); + defparam com_cmm_u_cmm_errman_nfl_cntr_reg_cnt_6_0_i_m2_0_1_.INIT = 8'hD8; + LUT3_L com_cmm_u_cmm_errman_nfl_cntr_reg_cnt_6_0_i_m2_0_1_ ( + .I0(com_cmm_u_cmm_errman_nfl_add_sub_b), + .I1(com_cmm_u_cmm_errman_nfl_cntr_un14_reg_cnt[1]), + .I2(com_cmm_u_cmm_errman_nfl_cntr_un25_reg_cnt[1]), + .LO(com_cmm_u_cmm_errman_nfl_cntr_reg_cnt_6_0_i_m2_0_1[1]) + ); + defparam com_cmm_u_cmm_errman_nfl_cntr_reg_cnt_6_0_i_m2_0_0_.INIT = 8'h8D; + LUT3_L com_cmm_u_cmm_errman_nfl_cntr_reg_cnt_6_0_i_m2_0_0_ ( + .I0(com_cmm_u_cmm_errman_nfl_add_sub_b), + .I1(com_cmm_u_cmm_errman_nfl_cntr_un14_reg_cnt[0]), + .I2(com_cmm_u_cmm_errman_nfl_cntr_un25_reg_cnt_axb_0_4919), + .LO(com_cmm_u_cmm_errman_nfl_cntr_reg_cnt_6_0_i_m2_0_1[0]) + ); + FDC com_cmm_u_cmm_errman_nfl_cntr_reg_inc_dec_b ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_nfl_add_sub_b), + .Q(com_cmm_u_cmm_errman_nfl_cntr_reg_inc_dec_b_4920), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_errman_nfl_cntr_reg_extra ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_nfl_cntr_reg_extra_6_0_u_i_m2_0_1), + .Q(com_cmm_u_cmm_errman_nfl_cntr_reg_extra_4921), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_errman_nfl_cntr_reg_uflow ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_nfl_cntr_N_15453_i), + .Q(com_cmm_u_cmm_errman_nfl_cntr_reg_uflow_4922), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_errman_nfl_cntr_reg_count_3_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_nfl_cntr_un25_reg_cnt_axb_3_i), + .Q(com_cmm_u_cmm_errman_cnt_nfl[3]), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_errman_nfl_cntr_reg_count_2_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_nfl_cntr_N_22221_i), + .Q(com_cmm_u_cmm_errman_cnt_nfl[2]), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_errman_nfl_cntr_reg_count_1_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_nfl_cntr_N_22219_i), + .Q(com_cmm_u_cmm_errman_cnt_nfl[1]), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_errman_nfl_cntr_reg_count_0_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_nfl_cntr_N_22217_i), + .Q(com_cmm_u_cmm_errman_cnt_nfl[0]), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_errman_nfl_cntr_reg_cnt_3_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_nfl_cntr_reg_cnt_6_0_i_m2_0_1[3]), + .Q(com_cmm_u_cmm_errman_nfl_cntr_reg_cnt[3]), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_errman_nfl_cntr_reg_cnt_2_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_nfl_cntr_reg_cnt_6_0_i_m2_0_1[2]), + .Q(com_cmm_u_cmm_errman_nfl_cntr_reg_cnt[2]), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_errman_nfl_cntr_reg_cnt_1_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_nfl_cntr_reg_cnt_6_0_i_m2_0_1[1]), + .Q(com_cmm_u_cmm_errman_nfl_cntr_reg_cnt[1]), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_errman_nfl_cntr_reg_cnt_0_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_nfl_cntr_reg_cnt_6_0_i_m2_0_1[0]), + .Q(com_cmm_u_cmm_errman_nfl_cntr_reg_cnt[0]), + .CLR(com_cmm_rst_267) + ); + defparam com_cmm_u_cmm_errman_nfl_cntr_un25_reg_cnt_s_4.INIT = 4'h1; + LUT1_L com_cmm_u_cmm_errman_nfl_cntr_un25_reg_cnt_s_4 ( + .I0(com_cmm_u_cmm_errman_nfl_cntr_un25_reg_cnt_cry_3_4923), + .LO(com_cmm_u_cmm_errman_nfl_cntr_un25_reg_cnt[4]) + ); + defparam com_cmm_u_cmm_errman_nfl_cntr_un25_reg_cnt_axb_3_i_i.INIT = 4'h1; + LUT1 com_cmm_u_cmm_errman_nfl_cntr_un25_reg_cnt_axb_3_i_i ( + .I0(com_cmm_u_cmm_errman_nfl_cntr_un25_reg_cnt_axb_3_i), + .O(com_cmm_u_cmm_errman_nfl_cntr_un25_reg_cnt_axb_3_i_i_4924) + ); + defparam com_cmm_u_cmm_errman_nfl_cntr_un25_reg_cnt_axb_2.INIT = 4'h9; + LUT2 com_cmm_u_cmm_errman_nfl_cntr_un25_reg_cnt_axb_2 ( + .I0(com_cmm_u_cmm_errman_nfl_cntr_N_22221_i), + .I1(com_cmm_u_cmm_errman_nfl_num[2]), + .O(com_cmm_u_cmm_errman_nfl_cntr_un25_reg_cnt_axb_2_4925) + ); + defparam com_cmm_u_cmm_errman_nfl_cntr_un25_reg_cnt_axb_1.INIT = 16'h6999; + LUT4 com_cmm_u_cmm_errman_nfl_cntr_un25_reg_cnt_axb_1 ( + .I0(com_cmm_u_cmm_errman_nfl_cntr_N_22219_i), + .I1(com_cmm_u_cmm_errman_nfl_num_c1_4789), + .I2(com_cmm_u_cmm_errman_to_incr_1ro), + .I3(com_cmm_u_cmm_pm_dev_power_state_eq_d0), + .O(com_cmm_u_cmm_errman_nfl_cntr_un25_reg_cnt_axb_1_4926) + ); + defparam com_cmm_u_cmm_errman_nfl_cntr_un14_reg_cnt_axb_3.INIT = 4'h2; + LUT1 com_cmm_u_cmm_errman_nfl_cntr_un14_reg_cnt_axb_3 ( + .I0(com_cmm_u_cmm_errman_nfl_cntr_un25_reg_cnt_axb_3_i), + .O(com_cmm_u_cmm_errman_nfl_cntr_un14_reg_cnt_axb_3_4927) + ); + defparam com_cmm_u_cmm_errman_nfl_cntr_un14_reg_cnt_axb_2.INIT = 4'h6; + LUT2 com_cmm_u_cmm_errman_nfl_cntr_un14_reg_cnt_axb_2 ( + .I0(com_cmm_u_cmm_errman_nfl_cntr_N_22221_i), + .I1(com_cmm_u_cmm_errman_nfl_num[2]), + .O(com_cmm_u_cmm_errman_nfl_cntr_un14_reg_cnt_axb_2_4928) + ); + defparam com_cmm_u_cmm_errman_nfl_cntr_un14_reg_cnt_axb_1.INIT = 16'h9666; + LUT4 com_cmm_u_cmm_errman_nfl_cntr_un14_reg_cnt_axb_1 ( + .I0(com_cmm_u_cmm_errman_nfl_cntr_N_22219_i), + .I1(com_cmm_u_cmm_errman_nfl_num_c1_4789), + .I2(com_cmm_u_cmm_errman_to_incr_1ro), + .I3(com_cmm_u_cmm_pm_dev_power_state_eq_d0), + .O(com_cmm_u_cmm_errman_nfl_cntr_un14_reg_cnt_axb_1_4929) + ); + defparam com_cmm_u_cmm_errman_wtd_ftl_N_50356_i.INIT = 16'hFF7F; + LUT4_L com_cmm_u_cmm_errman_wtd_ftl_N_50356_i ( + .I0(N_48877_i), + .I1(N_50488), + .I2(com_cmml_protocol_err_n), + .I3(com_tlm_cmmt_err_tlp_malformed), + .LO(com_cmm_u_cmm_errman_wtd_ftl_N_50356_i_4930) + ); + defparam com_cmm_u_cmm_errman_wtd_ftl_N_96_2_i.INIT = 8'hF7; + LUT3_L com_cmm_u_cmm_errman_wtd_ftl_N_96_2_i ( + .I0(N_50488), + .I1(com_cmml_protocol_err_n), + .I2(com_tlm_cmmt_err_tlp_malformed), + .LO(com_cmm_u_cmm_errman_N_96_2_i) + ); + FDC com_cmm_u_cmm_errman_wtd_ftl_reg_inc_dec_b ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_wtd_ftl_N_50356_i_4930), + .Q(com_cmm_u_cmm_errman_ftl_add_sub_b), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_errman_wtd_ftl_reg_ftl_num_2_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_wtd_ftl_to_incrdf2), + .Q(com_cmm_u_cmm_errman_ftl_num[2]), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_errman_wtd_ftl_reg_ftl_num_1_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(N_13_i), + .Q(com_cmm_u_cmm_errman_ftl_num[1]), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_errman_wtd_ftl_reg_ftl_num_0_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(N_5_i), + .Q(com_cmm_u_cmm_errman_ftl_num[0]), + .CLR(com_cmm_rst_267) + ); + INV com_cmm_u_cmm_errman_wtd_ftl_ftl_num_i_2_ ( + .I(com_cmm_u_cmm_errman_ftl_num[2]), + .O(com_cmm_u_cmm_errman_ftl_num_i[2]) + ); + INV com_cmm_u_cmm_errman_wtd_ftl_ftl_num_i_1_ ( + .I(com_cmm_u_cmm_errman_ftl_num[1]), + .O(com_cmm_u_cmm_errman_ftl_num_i[1]) + ); + INV com_cmm_u_cmm_errman_wtd_ftl_ftl_num_i_0_ ( + .I(com_cmm_u_cmm_errman_ftl_num[0]), + .O(com_cmm_u_cmm_errman_ftl_num_i[0]) + ); + VCC com_cmm_u_cmm_errman_ftl_cntr_VCC ( + .P(com_cmm_u_cmm_errman_ftl_cntr_VCC_4933) + ); + GND com_cmm_u_cmm_errman_ftl_cntr_GND ( + .G(com_cmm_u_cmm_errman_ftl_cntr_GND_4937) + ); + MUXCY_L com_cmm_u_cmm_errman_ftl_cntr_un25_reg_cnt_cry_0 ( + .CI(com_cmm_u_cmm_errman_ftl_cntr_VCC_4933), + .DI(com_cmm_u_cmm_errman_ftl_num_i[0]), + .LO(com_cmm_u_cmm_errman_ftl_cntr_un25_reg_cnt_cry_0_4931), + .S(com_cmm_u_cmm_errman_ftl_cntr_un25_reg_cnt_axb_0_4942) + ); + MUXCY_L com_cmm_u_cmm_errman_ftl_cntr_un25_reg_cnt_cry_1 ( + .CI(com_cmm_u_cmm_errman_ftl_cntr_un25_reg_cnt_cry_0_4931), + .DI(com_cmm_u_cmm_errman_ftl_num_i[1]), + .LO(com_cmm_u_cmm_errman_ftl_cntr_un25_reg_cnt_cry_1_4932), + .S(com_cmm_u_cmm_errman_ftl_cntr_un25_reg_cnt_axb_1_4952) + ); + XORCY com_cmm_u_cmm_errman_ftl_cntr_un25_reg_cnt_s_1 ( + .CI(com_cmm_u_cmm_errman_ftl_cntr_un25_reg_cnt_cry_0_4931), + .LI(com_cmm_u_cmm_errman_ftl_cntr_un25_reg_cnt_axb_1_4952), + .O(com_cmm_u_cmm_errman_ftl_cntr_un25_reg_cnt_s_1_0) + ); + MUXCY_L com_cmm_u_cmm_errman_ftl_cntr_un25_reg_cnt_cry_2 ( + .CI(com_cmm_u_cmm_errman_ftl_cntr_un25_reg_cnt_cry_1_4932), + .DI(com_cmm_u_cmm_errman_ftl_num_i[2]), + .LO(com_cmm_u_cmm_errman_ftl_cntr_un25_reg_cnt_cry_2_4934), + .S(com_cmm_u_cmm_errman_ftl_cntr_un25_reg_cnt_axb_2_4951) + ); + XORCY com_cmm_u_cmm_errman_ftl_cntr_un25_reg_cnt_s_2 ( + .CI(com_cmm_u_cmm_errman_ftl_cntr_un25_reg_cnt_cry_1_4932), + .LI(com_cmm_u_cmm_errman_ftl_cntr_un25_reg_cnt_axb_2_4951), + .O(com_cmm_u_cmm_errman_ftl_cntr_un25_reg_cnt_s_2_0) + ); + MUXCY_L com_cmm_u_cmm_errman_ftl_cntr_un25_reg_cnt_cry_3 ( + .CI(com_cmm_u_cmm_errman_ftl_cntr_un25_reg_cnt_cry_2_4934), + .DI(com_cmm_u_cmm_errman_ftl_cntr_VCC_4933), + .LO(com_cmm_u_cmm_errman_ftl_cntr_un25_reg_cnt_cry_3_4945), + .S(com_cmm_u_cmm_errman_ftl_cntr_un25_reg_cnt_axb_3_i_i_4949) + ); + XORCY com_cmm_u_cmm_errman_ftl_cntr_un25_reg_cnt_s_3 ( + .CI(com_cmm_u_cmm_errman_ftl_cntr_un25_reg_cnt_cry_2_4934), + .LI(com_cmm_u_cmm_errman_ftl_cntr_un25_reg_cnt_axb_3_i_i_4949), + .O(com_cmm_u_cmm_errman_ftl_cntr_un25_reg_cnt_s_3_0) + ); + MUXCY_L com_cmm_u_cmm_errman_ftl_cntr_un14_reg_cnt_cry_0 ( + .CI(com_cmm_u_cmm_errman_ftl_cntr_GND_4937), + .DI(com_cmm_u_cmm_errman_ftl_cntr_N_22232_i), + .LO(com_cmm_u_cmm_errman_ftl_cntr_un14_reg_cnt_cry_0_4935), + .S(com_cmm_u_cmm_errman_ftl_cntr_un14_reg_cnt_axb_0_4941) + ); + MUXCY_L com_cmm_u_cmm_errman_ftl_cntr_un14_reg_cnt_cry_1 ( + .CI(com_cmm_u_cmm_errman_ftl_cntr_un14_reg_cnt_cry_0_4935), + .DI(com_cmm_u_cmm_errman_ftl_cntr_N_22234_i), + .LO(com_cmm_u_cmm_errman_ftl_cntr_un14_reg_cnt_cry_1_4936), + .S(com_cmm_u_cmm_errman_ftl_cntr_un14_reg_cnt_axb_1_4948) + ); + XORCY com_cmm_u_cmm_errman_ftl_cntr_un14_reg_cnt_s_1 ( + .CI(com_cmm_u_cmm_errman_ftl_cntr_un14_reg_cnt_cry_0_4935), + .LI(com_cmm_u_cmm_errman_ftl_cntr_un14_reg_cnt_axb_1_4948), + .O(com_cmm_u_cmm_errman_ftl_cntr_un14_reg_cnt_s_1_0) + ); + MUXCY_L com_cmm_u_cmm_errman_ftl_cntr_un14_reg_cnt_cry_2 ( + .CI(com_cmm_u_cmm_errman_ftl_cntr_un14_reg_cnt_cry_1_4936), + .DI(com_cmm_u_cmm_errman_ftl_cntr_N_22236_i), + .LO(com_cmm_u_cmm_errman_ftl_cntr_un14_reg_cnt_cry_2_4938), + .S(com_cmm_u_cmm_errman_ftl_cntr_un14_reg_cnt_axb_2_4947) + ); + XORCY com_cmm_u_cmm_errman_ftl_cntr_un14_reg_cnt_s_2 ( + .CI(com_cmm_u_cmm_errman_ftl_cntr_un14_reg_cnt_cry_1_4936), + .LI(com_cmm_u_cmm_errman_ftl_cntr_un14_reg_cnt_axb_2_4947), + .O(com_cmm_u_cmm_errman_ftl_cntr_un14_reg_cnt_s_2_0) + ); + MUXCY com_cmm_u_cmm_errman_ftl_cntr_un14_reg_cnt_cry_3 ( + .CI(com_cmm_u_cmm_errman_ftl_cntr_un14_reg_cnt_cry_2_4938), + .DI(com_cmm_u_cmm_errman_ftl_cntr_GND_4937), + .O(com_cmm_u_cmm_errman_ftl_cntr_un14_reg_cnt_cry_3_4939), + .S(com_cmm_u_cmm_errman_ftl_cntr_un14_reg_cnt_axb_3_4946) + ); + XORCY com_cmm_u_cmm_errman_ftl_cntr_un14_reg_cnt_s_3 ( + .CI(com_cmm_u_cmm_errman_ftl_cntr_un14_reg_cnt_cry_2_4938), + .LI(com_cmm_u_cmm_errman_ftl_cntr_un14_reg_cnt_axb_3_4946), + .O(com_cmm_u_cmm_errman_ftl_cntr_un14_reg_cnt_s_3_0) + ); + defparam com_cmm_u_cmm_errman_ftl_cntr_reg_cnt_6_i_0_0_0_a2_0_.INIT = 4'h1; + LUT2 com_cmm_u_cmm_errman_ftl_cntr_reg_cnt_6_i_0_0_0_a2_0_ ( + .I0(NlwRenamedSig_OI_cfg_command_8_), + .I1(NlwRenamedSig_OI_cfg_dcommand[2]), + .O(com_cmm_u_cmm_errman_ftl_cntr_N_49548) + ); + defparam com_cmm_u_cmm_errman_ftl_cntr_oflow_0_a2_0_a2.INIT = 4'h8; + LUT2 com_cmm_u_cmm_errman_ftl_cntr_oflow_0_a2_0_a2 ( + .I0(com_cmm_u_cmm_errman_ftl_cntr_reg_extra_4944), + .I1(com_cmm_u_cmm_errman_ftl_cntr_reg_inc_dec_b_4943), + .O(com_cmm_u_cmm_errman_ftl_cntr_oflow) + ); + defparam com_cmm_u_cmm_errman_ftl_cntr_un14_reg_cnt_axb_0.INIT = 4'h6; + LUT2 com_cmm_u_cmm_errman_ftl_cntr_un14_reg_cnt_axb_0 ( + .I0(com_cmm_u_cmm_errman_ftl_cntr_N_22232_i), + .I1(com_cmm_u_cmm_errman_ftl_num[0]), + .O(com_cmm_u_cmm_errman_ftl_cntr_un14_reg_cnt_axb_0_4941) + ); + defparam com_cmm_u_cmm_errman_ftl_cntr_reg_uflow_3_i_a2_0.INIT = 4'h1; + LUT2 com_cmm_u_cmm_errman_ftl_cntr_reg_uflow_3_i_a2_0 ( + .I0(com_cmm_u_cmm_errman_ftl_num[0]), + .I1(com_cmm_u_cmm_errman_ftl_num[1]), + .O(com_cmm_u_cmm_errman_ftl_cntr_reg_uflow_3_i_a2_0_4940) + ); + defparam com_cmm_u_cmm_errman_ftl_cntr_cnt_f0_i_0_0_0_2_.INIT = 8'h0E; + LUT3 com_cmm_u_cmm_errman_ftl_cntr_cnt_f0_i_0_0_0_2_ ( + .I0(com_cmm_u_cmm_errman_ftl_cntr_oflow), + .I1(com_cmm_u_cmm_errman_ftl_cntr_reg_cnt[2]), + .I2(com_cmm_u_cmm_errman_ftl_cntr_reg_uflow_4950), + .O(com_cmm_u_cmm_errman_ftl_cntr_N_22236_i) + ); + defparam com_cmm_u_cmm_errman_ftl_cntr_cnt_f0_i_0_0_0_1_.INIT = 8'h0E; + LUT3 com_cmm_u_cmm_errman_ftl_cntr_cnt_f0_i_0_0_0_1_ ( + .I0(com_cmm_u_cmm_errman_ftl_cntr_oflow), + .I1(com_cmm_u_cmm_errman_ftl_cntr_reg_cnt[1]), + .I2(com_cmm_u_cmm_errman_ftl_cntr_reg_uflow_4950), + .O(com_cmm_u_cmm_errman_ftl_cntr_N_22234_i) + ); + defparam com_cmm_u_cmm_errman_ftl_cntr_cnt_f0_i_0_0_0_0_.INIT = 8'h0E; + LUT3 com_cmm_u_cmm_errman_ftl_cntr_cnt_f0_i_0_0_0_0_ ( + .I0(com_cmm_u_cmm_errman_ftl_cntr_oflow), + .I1(com_cmm_u_cmm_errman_ftl_cntr_reg_cnt[0]), + .I2(com_cmm_u_cmm_errman_ftl_cntr_reg_uflow_4950), + .O(com_cmm_u_cmm_errman_ftl_cntr_N_22232_i) + ); + defparam com_cmm_u_cmm_errman_ftl_cntr_reg_extra_6_u_i_0_0_0.INIT = 16'h5404; + LUT4_L com_cmm_u_cmm_errman_ftl_cntr_reg_extra_6_u_i_0_0_0 ( + .I0(com_cmm_u_cmm_errman_ftl_cntr_N_49548), + .I1(com_cmm_u_cmm_errman_ftl_cntr_un25_reg_cnt_s_4_0), + .I2(com_cmm_u_cmm_errman_ftl_add_sub_b), + .I3(com_cmm_u_cmm_errman_ftl_cntr_un14_reg_cnt_cry_3_4939), + .LO(com_cmm_u_cmm_errman_ftl_cntr_N_15651_i) + ); + defparam com_cmm_u_cmm_errman_ftl_cntr_reg_uflow_3_i.INIT = 16'h2202; + LUT4_L com_cmm_u_cmm_errman_ftl_cntr_reg_uflow_3_i ( + .I0(com_cmm_u_cmm_errman_send_ftl_3_0_a2_4791), + .I1(com_cmm_u_cmm_errman_ftl_add_sub_b), + .I2(com_cmm_u_cmm_errman_ftl_cntr_reg_uflow_3_i_a2_0_4940), + .I3(com_cmm_u_cmm_errman_ftl_num[2]), + .LO(com_cmm_u_cmm_errman_ftl_cntr_N_15539_i) + ); + defparam com_cmm_u_cmm_errman_ftl_cntr_reg_cnt_6_i_0_0_0_3_.INIT = 16'h5404; + LUT4_L com_cmm_u_cmm_errman_ftl_cntr_reg_cnt_6_i_0_0_0_3_ ( + .I0(com_cmm_u_cmm_errman_ftl_cntr_N_49548), + .I1(com_cmm_u_cmm_errman_ftl_cntr_un25_reg_cnt_s_3_0), + .I2(com_cmm_u_cmm_errman_ftl_add_sub_b), + .I3(com_cmm_u_cmm_errman_ftl_cntr_un14_reg_cnt_s_3_0), + .LO(com_cmm_u_cmm_errman_ftl_cntr_N_15649_i) + ); + defparam com_cmm_u_cmm_errman_ftl_cntr_reg_cnt_6_i_0_0_0_2_.INIT = 16'h5404; + LUT4_L com_cmm_u_cmm_errman_ftl_cntr_reg_cnt_6_i_0_0_0_2_ ( + .I0(com_cmm_u_cmm_errman_ftl_cntr_N_49548), + .I1(com_cmm_u_cmm_errman_ftl_cntr_un25_reg_cnt_s_2_0), + .I2(com_cmm_u_cmm_errman_ftl_add_sub_b), + .I3(com_cmm_u_cmm_errman_ftl_cntr_un14_reg_cnt_s_2_0), + .LO(com_cmm_u_cmm_errman_ftl_cntr_N_15647_i) + ); + defparam com_cmm_u_cmm_errman_ftl_cntr_reg_cnt_6_i_0_0_0_1_.INIT = 16'h5404; + LUT4_L com_cmm_u_cmm_errman_ftl_cntr_reg_cnt_6_i_0_0_0_1_ ( + .I0(com_cmm_u_cmm_errman_ftl_cntr_N_49548), + .I1(com_cmm_u_cmm_errman_ftl_cntr_un25_reg_cnt_s_1_0), + .I2(com_cmm_u_cmm_errman_ftl_add_sub_b), + .I3(com_cmm_u_cmm_errman_ftl_cntr_un14_reg_cnt_s_1_0), + .LO(com_cmm_u_cmm_errman_ftl_cntr_N_15645_i) + ); + defparam com_cmm_u_cmm_errman_ftl_cntr_reg_cnt_6_i_0_0_0_0_.INIT = 16'h4051; + LUT4_L com_cmm_u_cmm_errman_ftl_cntr_reg_cnt_6_i_0_0_0_0_ ( + .I0(com_cmm_u_cmm_errman_ftl_cntr_N_49548), + .I1(com_cmm_u_cmm_errman_ftl_add_sub_b), + .I2(com_cmm_u_cmm_errman_ftl_cntr_un14_reg_cnt_axb_0_4941), + .I3(com_cmm_u_cmm_errman_ftl_cntr_un25_reg_cnt_axb_0_4942), + .LO(com_cmm_u_cmm_errman_ftl_cntr_N_15643_i) + ); + defparam com_cmm_u_cmm_errman_ftl_cntr_reg_count_7_f0_i_0_0_0_3_.INIT = 16'h0054; + LUT4_L com_cmm_u_cmm_errman_ftl_cntr_reg_count_7_f0_i_0_0_0_3_ ( + .I0(com_cmm_u_cmm_errman_ftl_cntr_N_49548), + .I1(com_cmm_u_cmm_errman_ftl_cntr_oflow), + .I2(com_cmm_u_cmm_errman_ftl_cntr_reg_cnt[3]), + .I3(com_cmm_u_cmm_errman_ftl_cntr_reg_uflow_4950), + .LO(com_cmm_u_cmm_errman_ftl_cntr_N_22246_i) + ); + defparam com_cmm_u_cmm_errman_ftl_cntr_reg_count_7_f0_i_0_0_0_2_.INIT = 16'h0054; + LUT4_L com_cmm_u_cmm_errman_ftl_cntr_reg_count_7_f0_i_0_0_0_2_ ( + .I0(com_cmm_u_cmm_errman_ftl_cntr_N_49548), + .I1(com_cmm_u_cmm_errman_ftl_cntr_oflow), + .I2(com_cmm_u_cmm_errman_ftl_cntr_reg_cnt[2]), + .I3(com_cmm_u_cmm_errman_ftl_cntr_reg_uflow_4950), + .LO(com_cmm_u_cmm_errman_ftl_cntr_N_22244_i) + ); + defparam com_cmm_u_cmm_errman_ftl_cntr_reg_count_7_f0_i_0_0_0_1_.INIT = 16'h0054; + LUT4_L com_cmm_u_cmm_errman_ftl_cntr_reg_count_7_f0_i_0_0_0_1_ ( + .I0(com_cmm_u_cmm_errman_ftl_cntr_N_49548), + .I1(com_cmm_u_cmm_errman_ftl_cntr_oflow), + .I2(com_cmm_u_cmm_errman_ftl_cntr_reg_cnt[1]), + .I3(com_cmm_u_cmm_errman_ftl_cntr_reg_uflow_4950), + .LO(com_cmm_u_cmm_errman_ftl_cntr_N_22242_i) + ); + defparam com_cmm_u_cmm_errman_ftl_cntr_reg_count_7_f0_i_0_0_0_0_.INIT = 16'h0054; + LUT4_L com_cmm_u_cmm_errman_ftl_cntr_reg_count_7_f0_i_0_0_0_0_ ( + .I0(com_cmm_u_cmm_errman_ftl_cntr_N_49548), + .I1(com_cmm_u_cmm_errman_ftl_cntr_oflow), + .I2(com_cmm_u_cmm_errman_ftl_cntr_reg_cnt[0]), + .I3(com_cmm_u_cmm_errman_ftl_cntr_reg_uflow_4950), + .LO(com_cmm_u_cmm_errman_ftl_cntr_N_22240_i) + ); + defparam com_cmm_u_cmm_errman_ftl_cntr_un25_reg_cnt_axb_0.INIT = 4'h6; + LUT2 com_cmm_u_cmm_errman_ftl_cntr_un25_reg_cnt_axb_0 ( + .I0(com_cmm_u_cmm_errman_ftl_cntr_N_22232_i), + .I1(com_cmm_u_cmm_errman_ftl_num_i[0]), + .O(com_cmm_u_cmm_errman_ftl_cntr_un25_reg_cnt_axb_0_4942) + ); + FDC com_cmm_u_cmm_errman_ftl_cntr_reg_inc_dec_b ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_ftl_add_sub_b), + .Q(com_cmm_u_cmm_errman_ftl_cntr_reg_inc_dec_b_4943), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_errman_ftl_cntr_reg_extra ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_ftl_cntr_N_15651_i), + .Q(com_cmm_u_cmm_errman_ftl_cntr_reg_extra_4944), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_errman_ftl_cntr_reg_uflow ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_ftl_cntr_N_15539_i), + .Q(com_cmm_u_cmm_errman_ftl_cntr_reg_uflow_4950), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_errman_ftl_cntr_reg_cnt_3_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_ftl_cntr_N_15649_i), + .Q(com_cmm_u_cmm_errman_ftl_cntr_reg_cnt[3]), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_errman_ftl_cntr_reg_cnt_2_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_ftl_cntr_N_15647_i), + .Q(com_cmm_u_cmm_errman_ftl_cntr_reg_cnt[2]), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_errman_ftl_cntr_reg_cnt_1_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_ftl_cntr_N_15645_i), + .Q(com_cmm_u_cmm_errman_ftl_cntr_reg_cnt[1]), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_errman_ftl_cntr_reg_cnt_0_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_ftl_cntr_N_15643_i), + .Q(com_cmm_u_cmm_errman_ftl_cntr_reg_cnt[0]), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_errman_ftl_cntr_reg_count_3_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_ftl_cntr_N_22246_i), + .Q(com_cmm_u_cmm_errman_cnt_ftl[3]), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_errman_ftl_cntr_reg_count_2_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_ftl_cntr_N_22244_i), + .Q(com_cmm_u_cmm_errman_cnt_ftl[2]), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_errman_ftl_cntr_reg_count_1_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_ftl_cntr_N_22242_i), + .Q(com_cmm_u_cmm_errman_cnt_ftl[1]), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_errman_ftl_cntr_reg_count_0_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_ftl_cntr_N_22240_i), + .Q(com_cmm_u_cmm_errman_cnt_ftl[0]), + .CLR(com_cmm_rst_267) + ); + defparam com_cmm_u_cmm_errman_ftl_cntr_un25_reg_cnt_s_4.INIT = 4'h1; + LUT1_L com_cmm_u_cmm_errman_ftl_cntr_un25_reg_cnt_s_4 ( + .I0(com_cmm_u_cmm_errman_ftl_cntr_un25_reg_cnt_cry_3_4945), + .LO(com_cmm_u_cmm_errman_ftl_cntr_un25_reg_cnt_s_4_0) + ); + defparam com_cmm_u_cmm_errman_ftl_cntr_un14_reg_cnt_axb_3.INIT = 8'h0E; + LUT3 com_cmm_u_cmm_errman_ftl_cntr_un14_reg_cnt_axb_3 ( + .I0(com_cmm_u_cmm_errman_ftl_cntr_oflow), + .I1(com_cmm_u_cmm_errman_ftl_cntr_reg_cnt[3]), + .I2(com_cmm_u_cmm_errman_ftl_cntr_reg_uflow_4950), + .O(com_cmm_u_cmm_errman_ftl_cntr_un14_reg_cnt_axb_3_4946) + ); + defparam com_cmm_u_cmm_errman_ftl_cntr_un14_reg_cnt_axb_2.INIT = 4'h6; + LUT2 com_cmm_u_cmm_errman_ftl_cntr_un14_reg_cnt_axb_2 ( + .I0(com_cmm_u_cmm_errman_ftl_cntr_N_22236_i), + .I1(com_cmm_u_cmm_errman_ftl_num[2]), + .O(com_cmm_u_cmm_errman_ftl_cntr_un14_reg_cnt_axb_2_4947) + ); + defparam com_cmm_u_cmm_errman_ftl_cntr_un14_reg_cnt_axb_1.INIT = 4'h6; + LUT2 com_cmm_u_cmm_errman_ftl_cntr_un14_reg_cnt_axb_1 ( + .I0(com_cmm_u_cmm_errman_ftl_cntr_N_22234_i), + .I1(com_cmm_u_cmm_errman_ftl_num[1]), + .O(com_cmm_u_cmm_errman_ftl_cntr_un14_reg_cnt_axb_1_4948) + ); + defparam com_cmm_u_cmm_errman_ftl_cntr_un25_reg_cnt_axb_3_i_i.INIT = 8'hF1; + LUT3 com_cmm_u_cmm_errman_ftl_cntr_un25_reg_cnt_axb_3_i_i ( + .I0(com_cmm_u_cmm_errman_ftl_cntr_oflow), + .I1(com_cmm_u_cmm_errman_ftl_cntr_reg_cnt[3]), + .I2(com_cmm_u_cmm_errman_ftl_cntr_reg_uflow_4950), + .O(com_cmm_u_cmm_errman_ftl_cntr_un25_reg_cnt_axb_3_i_i_4949) + ); + defparam com_cmm_u_cmm_errman_ftl_cntr_un25_reg_cnt_axb_2.INIT = 4'h9; + LUT2 com_cmm_u_cmm_errman_ftl_cntr_un25_reg_cnt_axb_2 ( + .I0(com_cmm_u_cmm_errman_ftl_cntr_N_22236_i), + .I1(com_cmm_u_cmm_errman_ftl_num[2]), + .O(com_cmm_u_cmm_errman_ftl_cntr_un25_reg_cnt_axb_2_4951) + ); + defparam com_cmm_u_cmm_errman_ftl_cntr_un25_reg_cnt_axb_1.INIT = 4'h9; + LUT2 com_cmm_u_cmm_errman_ftl_cntr_un25_reg_cnt_axb_1 ( + .I0(com_cmm_u_cmm_errman_ftl_cntr_N_22234_i), + .I1(com_cmm_u_cmm_errman_ftl_num[1]), + .O(com_cmm_u_cmm_errman_ftl_cntr_un25_reg_cnt_axb_1_4952) + ); + defparam com_cmm_u_cmm_errman_wtd_cplt_mod_add_sub_b23_i_0_i_a2_0_a2_0_o3.INIT = 4'h4; + LUT2 com_cmm_u_cmm_errman_wtd_cplt_mod_add_sub_b23_i_0_i_a2_0_a2_0_o3 ( + .I0(com_cmmt_err_tlp_p_cpl), + .I1(com_cmmt_err_tlp_ur), + .O(com_cmm_u_cmm_errman_N_48855_i) + ); + defparam com_cmm_u_cmm_errman_wtd_cplt_N_50359_i.INIT = 4'hB; + LUT2_L com_cmm_u_cmm_errman_wtd_cplt_N_50359_i ( + .I0(com_cmm_u_cmm_errman_N_48855_i), + .I1(com_cmm_u_cmm_errman_N_48948_i), + .LO(com_cmm_u_cmm_errman_wtd_cplt_N_50359_i_4953) + ); + defparam com_cmm_u_cmm_errman_wtd_cplt_mod_to_incr_0_x2_i_x3_i_x3_0_x3_0_x3_0_.INIT = 4'h6; + LUT2_L com_cmm_u_cmm_errman_wtd_cplt_mod_to_incr_0_x2_i_x3_i_x3_0_x3_0_x3_0_ ( + .I0(com_cmm_u_cmm_errman_N_48855_i), + .I1(com_cmm_u_cmm_errman_N_48948_i), + .LO(com_cmm_u_cmm_errman_wtd_cplt_N_48966_i_0) + ); + FDC com_cmm_u_cmm_errman_wtd_cplt_reg_inc_dec_b ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_wtd_cplt_N_50359_i_4953), + .Q(com_cmm_u_cmm_errman_cplt_add_sub_b), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_errman_wtd_cplt_reg_cpl_num_0_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_wtd_cplt_N_48966_i_0), + .Q(com_cmm_u_cmm_errman_cplt_num[0]), + .CLR(com_cmm_rst_267) + ); + defparam com_cmm_u_cmm_errman_cplt_cntr_un14_reg_cnt_p4.INIT = 16'h8000; + LUT4 com_cmm_u_cmm_errman_cplt_cntr_un14_reg_cnt_p4 ( + .I0(com_cmm_u_cmm_errman_cplt_cntr_N_22256_i), + .I1(com_cmm_u_cmm_errman_cplt_cntr_un25_reg_cnt_axb1_i), + .I2(com_cmm_u_cmm_errman_cplt_cntr_un25_reg_cnt_axb2_i), + .I3(com_cmm_u_cmm_errman_cplt_num[0]), + .O(com_cmm_u_cmm_errman_cplt_cntr_un14_reg_cnt_p4_4956) + ); + defparam com_cmm_u_cmm_errman_cplt_cntr_un14_reg_cnt_p4_0.INIT = 4'h8; + LUT2_L com_cmm_u_cmm_errman_cplt_cntr_un14_reg_cnt_p4_0 ( + .I0(com_cmm_u_cmm_errman_cplt_cntr_un14_reg_cnt_p4_4956), + .I1(com_cmm_u_cmm_errman_cplt_cntr_un25_reg_cnt_axb3_i), + .LO(com_cmm_u_cmm_errman_cplt_cntr_un14_reg_cnt[4]) + ); + defparam com_cmm_u_cmm_errman_cplt_cntr_un25_reg_cnt_p4.INIT = 16'hFEFF; + LUT4 com_cmm_u_cmm_errman_cplt_cntr_un25_reg_cnt_p4 ( + .I0(com_cmm_u_cmm_errman_cplt_cntr_N_22256_i), + .I1(com_cmm_u_cmm_errman_cplt_cntr_un25_reg_cnt_axb1_i), + .I2(com_cmm_u_cmm_errman_cplt_cntr_un25_reg_cnt_axb2_i), + .I3(com_cmm_u_cmm_errman_cplt_num[0]), + .O(com_cmm_u_cmm_errman_cplt_cntr_un25_reg_cnt_p4_4955) + ); + defparam com_cmm_u_cmm_errman_cplt_cntr_cnt_f0_i_0_.INIT = 16'h00EA; + LUT4 com_cmm_u_cmm_errman_cplt_cntr_cnt_f0_i_0_ ( + .I0(com_cmm_u_cmm_errman_cplt_cntr_reg_cnt[0]), + .I1(com_cmm_u_cmm_errman_cplt_cntr_reg_extra_4958), + .I2(com_cmm_u_cmm_errman_cplt_cntr_reg_inc_dec_b_4957), + .I3(com_cmm_u_cmm_errman_cplt_cntr_reg_uflow_4959), + .O(com_cmm_u_cmm_errman_cplt_cntr_N_22256_i) + ); + defparam com_cmm_u_cmm_errman_cplt_cntr_cnt_f0_i_1_.INIT = 16'h00EA; + LUT4 com_cmm_u_cmm_errman_cplt_cntr_cnt_f0_i_1_ ( + .I0(com_cmm_u_cmm_errman_cplt_cntr_reg_cnt[1]), + .I1(com_cmm_u_cmm_errman_cplt_cntr_reg_extra_4958), + .I2(com_cmm_u_cmm_errman_cplt_cntr_reg_inc_dec_b_4957), + .I3(com_cmm_u_cmm_errman_cplt_cntr_reg_uflow_4959), + .O(com_cmm_u_cmm_errman_cplt_cntr_un25_reg_cnt_axb1_i) + ); + defparam com_cmm_u_cmm_errman_cplt_cntr_cnt_f0_i_2_.INIT = 16'h00EA; + LUT4 com_cmm_u_cmm_errman_cplt_cntr_cnt_f0_i_2_ ( + .I0(com_cmm_u_cmm_errman_cplt_cntr_reg_cnt[2]), + .I1(com_cmm_u_cmm_errman_cplt_cntr_reg_extra_4958), + .I2(com_cmm_u_cmm_errman_cplt_cntr_reg_inc_dec_b_4957), + .I3(com_cmm_u_cmm_errman_cplt_cntr_reg_uflow_4959), + .O(com_cmm_u_cmm_errman_cplt_cntr_un25_reg_cnt_axb2_i) + ); + defparam com_cmm_u_cmm_errman_cplt_cntr_cnt_f0_i_3_.INIT = 16'h00EA; + LUT4 com_cmm_u_cmm_errman_cplt_cntr_cnt_f0_i_3_ ( + .I0(com_cmm_u_cmm_errman_cplt_cntr_reg_cnt[3]), + .I1(com_cmm_u_cmm_errman_cplt_cntr_reg_extra_4958), + .I2(com_cmm_u_cmm_errman_cplt_cntr_reg_inc_dec_b_4957), + .I3(com_cmm_u_cmm_errman_cplt_cntr_reg_uflow_4959), + .O(com_cmm_u_cmm_errman_cplt_cntr_un25_reg_cnt_axb3_i) + ); + defparam com_cmm_u_cmm_errman_cplt_cntr_un25_reg_cnt_c1.INIT = 4'h4; + LUT2_L com_cmm_u_cmm_errman_cplt_cntr_un25_reg_cnt_c1 ( + .I0(com_cmm_u_cmm_errman_cplt_cntr_N_22256_i), + .I1(com_cmm_u_cmm_errman_cplt_num[0]), + .LO(com_cmm_u_cmm_errman_cplt_cntr_un25_reg_cnt_c1_4954) + ); + defparam com_cmm_u_cmm_errman_cplt_cntr_reg_cnt_6_0_i_m2_0_am_2_.INIT = 8'hD2; + LUT3 com_cmm_u_cmm_errman_cplt_cntr_reg_cnt_6_0_i_m2_0_am_2_ ( + .I0(com_cmm_u_cmm_errman_cplt_cntr_un25_reg_cnt_c1_4954), + .I1(com_cmm_u_cmm_errman_cplt_cntr_un25_reg_cnt_axb1_i), + .I2(com_cmm_u_cmm_errman_cplt_cntr_un25_reg_cnt_axb2_i), + .O(com_cmm_u_cmm_errman_cplt_cntr_reg_cnt_6_0_i_m2_0_am[2]) + ); + defparam com_cmm_u_cmm_errman_cplt_cntr_reg_cnt_6_0_i_m2_0_bm_2_.INIT = 16'h78F0; + LUT4 com_cmm_u_cmm_errman_cplt_cntr_reg_cnt_6_0_i_m2_0_bm_2_ ( + .I0(com_cmm_u_cmm_errman_cplt_cntr_N_22256_i), + .I1(com_cmm_u_cmm_errman_cplt_cntr_un25_reg_cnt_axb1_i), + .I2(com_cmm_u_cmm_errman_cplt_cntr_un25_reg_cnt_axb2_i), + .I3(com_cmm_u_cmm_errman_cplt_num[0]), + .O(com_cmm_u_cmm_errman_cplt_cntr_reg_cnt_6_0_i_m2_0_bm[2]) + ); + MUXF5 com_cmm_u_cmm_errman_cplt_cntr_reg_cnt_6_0_i_m2_0_2_ ( + .I0(com_cmm_u_cmm_errman_cplt_cntr_reg_cnt_6_0_i_m2_0_am[2]), + .I1(com_cmm_u_cmm_errman_cplt_cntr_reg_cnt_6_0_i_m2_0_bm[2]), + .O(com_cmm_u_cmm_errman_cplt_cntr_reg_cnt_6_0_i_m2_0_0[2]), + .S(com_cmm_u_cmm_errman_cplt_add_sub_b) + ); + defparam com_cmm_u_cmm_errman_cplt_cntr_reg_extra_6_0_u_i_m2_0.INIT = 16'h888D; + LUT4_L com_cmm_u_cmm_errman_cplt_cntr_reg_extra_6_0_u_i_m2_0 ( + .I0(com_cmm_u_cmm_errman_cplt_add_sub_b), + .I1(com_cmm_u_cmm_errman_cplt_cntr_un14_reg_cnt[4]), + .I2(com_cmm_u_cmm_errman_cplt_cntr_un25_reg_cnt_axb3_i), + .I3(com_cmm_u_cmm_errman_cplt_cntr_un25_reg_cnt_p4_4955), + .LO(com_cmm_u_cmm_errman_cplt_cntr_reg_extra_6_0_u_i_m2_0_0) + ); + defparam com_cmm_u_cmm_errman_cplt_cntr_reg_uflow_3_0_a2.INIT = 8'h40; + LUT3_L com_cmm_u_cmm_errman_cplt_cntr_reg_uflow_3_0_a2 ( + .I0(com_cmm_u_cmm_errman_cplt_add_sub_b), + .I1(com_cmm_u_cmm_errman_un1_reg_uflow_3_1), + .I2(com_cmm_u_cmm_errman_cplt_num[0]), + .LO(com_cmm_u_cmm_errman_cplt_cntr_reg_uflow_3) + ); + defparam com_cmm_u_cmm_errman_cplt_cntr_reg_cnt_6_0_i_m2_0_3_.INIT = 16'h782D; + LUT4_L com_cmm_u_cmm_errman_cplt_cntr_reg_cnt_6_0_i_m2_0_3_ ( + .I0(com_cmm_u_cmm_errman_cplt_add_sub_b), + .I1(com_cmm_u_cmm_errman_cplt_cntr_un14_reg_cnt_p4_4956), + .I2(com_cmm_u_cmm_errman_cplt_cntr_un25_reg_cnt_axb3_i), + .I3(com_cmm_u_cmm_errman_cplt_cntr_un25_reg_cnt_p4_4955), + .LO(com_cmm_u_cmm_errman_cplt_cntr_reg_cnt_6_0_i_m2_0_0[3]) + ); + defparam com_cmm_u_cmm_errman_cplt_cntr_reg_cnt_6_0_i_m2_0_1_.INIT = 16'h69F0; + LUT4_L com_cmm_u_cmm_errman_cplt_cntr_reg_cnt_6_0_i_m2_0_1_ ( + .I0(com_cmm_u_cmm_errman_cplt_cntr_N_22256_i), + .I1(com_cmm_u_cmm_errman_cplt_add_sub_b), + .I2(com_cmm_u_cmm_errman_cplt_cntr_un25_reg_cnt_axb1_i), + .I3(com_cmm_u_cmm_errman_cplt_num[0]), + .LO(com_cmm_u_cmm_errman_cplt_cntr_reg_cnt_6_0_i_m2_0_0[1]) + ); + defparam com_cmm_u_cmm_errman_cplt_cntr_reg_cnt_6_0_i_m2_0_0_.INIT = 4'h6; + LUT2_L com_cmm_u_cmm_errman_cplt_cntr_reg_cnt_6_0_i_m2_0_0_ ( + .I0(com_cmm_u_cmm_errman_cplt_cntr_N_22256_i), + .I1(com_cmm_u_cmm_errman_cplt_num[0]), + .LO(com_cmm_u_cmm_errman_cplt_cntr_reg_cnt_6_0_i_m2_0_0[0]) + ); + FDC com_cmm_u_cmm_errman_cplt_cntr_reg_inc_dec_b ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_cplt_add_sub_b), + .Q(com_cmm_u_cmm_errman_cplt_cntr_reg_inc_dec_b_4957), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_errman_cplt_cntr_reg_extra ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_cplt_cntr_reg_extra_6_0_u_i_m2_0_0), + .Q(com_cmm_u_cmm_errman_cplt_cntr_reg_extra_4958), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_errman_cplt_cntr_reg_uflow ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_cplt_cntr_reg_uflow_3), + .Q(com_cmm_u_cmm_errman_cplt_cntr_reg_uflow_4959), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_errman_cplt_cntr_reg_cnt_3_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_cplt_cntr_reg_cnt_6_0_i_m2_0_0[3]), + .Q(com_cmm_u_cmm_errman_cplt_cntr_reg_cnt[3]), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_errman_cplt_cntr_reg_cnt_2_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_cplt_cntr_reg_cnt_6_0_i_m2_0_0[2]), + .Q(com_cmm_u_cmm_errman_cplt_cntr_reg_cnt[2]), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_errman_cplt_cntr_reg_cnt_1_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_cplt_cntr_reg_cnt_6_0_i_m2_0_0[1]), + .Q(com_cmm_u_cmm_errman_cplt_cntr_reg_cnt[1]), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_errman_cplt_cntr_reg_cnt_0_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_cplt_cntr_reg_cnt_6_0_i_m2_0_0[0]), + .Q(com_cmm_u_cmm_errman_cplt_cntr_reg_cnt[0]), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_errman_cplt_cntr_reg_count_3_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_cplt_cntr_un25_reg_cnt_axb3_i), + .Q(com_cmm_u_cmm_errman_cnt_cplt[3]), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_errman_cplt_cntr_reg_count_2_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_cplt_cntr_un25_reg_cnt_axb2_i), + .Q(com_cmm_u_cmm_errman_cnt_cplt[2]), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_errman_cplt_cntr_reg_count_1_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_cplt_cntr_un25_reg_cnt_axb1_i), + .Q(com_cmm_u_cmm_errman_cnt_cplt[1]), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_errman_cplt_cntr_reg_count_0_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_cplt_cntr_N_22256_i), + .Q(com_cmm_u_cmm_errman_cnt_cplt[0]), + .CLR(com_cmm_rst_267) + ); + defparam com_cmm_u_cmm_errman_wtd_cplu_mod_add_sub_b23_i_0_0_0_o2.INIT = 4'h8; + LUT2 com_cmm_u_cmm_errman_wtd_cplu_mod_add_sub_b23_i_0_0_0_o2 ( + .I0(com_cmm_gnt_errman), + .I1(com_cmm_u_cmm_errman_cs_is_cplu_4806), + .O(com_cmm_u_cmm_errman_N_48933_i) + ); + defparam com_cmm_u_cmm_errman_wtd_cplu_mod_add_sub_b23_i_0_0_0_a2.INIT = 8'h4C; + LUT3 com_cmm_u_cmm_errman_wtd_cplu_mod_add_sub_b23_i_0_0_0_a2 ( + .I0(cfg_err_cpl_abort_n), + .I1(cfg_err_posted_n), + .I2(cfg_err_ur_n), + .O(com_cmm_u_cmm_errman_N_49807) + ); + defparam com_cmm_u_cmm_errman_wtd_cplu_N_68722_i.INIT = 4'hD; + LUT2_L com_cmm_u_cmm_errman_wtd_cplu_N_68722_i ( + .I0(com_cmm_u_cmm_errman_N_48933_i), + .I1(com_cmm_u_cmm_errman_N_49807), + .LO(com_cmm_u_cmm_errman_wtd_cplu_N_68722_i_4960) + ); + defparam com_cmm_u_cmm_errman_wtd_cplu_mod_to_incr_0_x2_i_0_0_0_.INIT = 4'h6; + LUT2_L com_cmm_u_cmm_errman_wtd_cplu_mod_to_incr_0_x2_i_0_0_0_ ( + .I0(com_cmm_u_cmm_errman_N_48933_i), + .I1(com_cmm_u_cmm_errman_N_49807), + .LO(com_cmm_u_cmm_errman_wtd_cplu_N_32847_i) + ); + FDC com_cmm_u_cmm_errman_wtd_cplu_reg_inc_dec_b ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_wtd_cplu_N_68722_i_4960), + .Q(com_cmm_u_cmm_errman_cplu_add_sub_b), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_errman_wtd_cplu_reg_cpl_num_0_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_wtd_cplu_N_32847_i), + .Q(com_cmm_u_cmm_errman_cplu_num[0]), + .CLR(com_cmm_rst_267) + ); + defparam com_cmm_u_cmm_errman_cplu_cntr_un14_reg_cnt_p4.INIT = 16'h8000; + LUT4 com_cmm_u_cmm_errman_cplu_cntr_un14_reg_cnt_p4 ( + .I0(com_cmm_u_cmm_errman_cplu_cntr_N_22271_i), + .I1(com_cmm_u_cmm_errman_cplu_cntr_un25_reg_cnt_axb1_i), + .I2(com_cmm_u_cmm_errman_cplu_cntr_un25_reg_cnt_axb2_i), + .I3(com_cmm_u_cmm_errman_cplu_num[0]), + .O(com_cmm_u_cmm_errman_cplu_cntr_un14_reg_cnt_p4_4962) + ); + defparam com_cmm_u_cmm_errman_cplu_cntr_un14_reg_cnt_p4_0.INIT = 4'h8; + LUT2_L com_cmm_u_cmm_errman_cplu_cntr_un14_reg_cnt_p4_0 ( + .I0(com_cmm_u_cmm_errman_cplu_cntr_un14_reg_cnt_p4_4962), + .I1(com_cmm_u_cmm_errman_cplu_cntr_un25_reg_cnt_axb3_i), + .LO(com_cmm_u_cmm_errman_cplu_cntr_un14_reg_cnt[4]) + ); + defparam com_cmm_u_cmm_errman_cplu_cntr_un25_reg_cnt_p4.INIT = 16'hFEFF; + LUT4 com_cmm_u_cmm_errman_cplu_cntr_un25_reg_cnt_p4 ( + .I0(com_cmm_u_cmm_errman_cplu_cntr_N_22271_i), + .I1(com_cmm_u_cmm_errman_cplu_cntr_un25_reg_cnt_axb1_i), + .I2(com_cmm_u_cmm_errman_cplu_cntr_un25_reg_cnt_axb2_i), + .I3(com_cmm_u_cmm_errman_cplu_num[0]), + .O(com_cmm_u_cmm_errman_cplu_cntr_un25_reg_cnt_p4_4961) + ); + defparam com_cmm_u_cmm_errman_cplu_cntr_cnt_f0_i_0_.INIT = 16'h00EA; + LUT4 com_cmm_u_cmm_errman_cplu_cntr_cnt_f0_i_0_ ( + .I0(com_cmm_u_cmm_errman_cplu_cntr_reg_cnt[0]), + .I1(com_cmm_u_cmm_errman_cplu_cntr_reg_extra_4966), + .I2(com_cmm_u_cmm_errman_cplu_cntr_reg_inc_dec_b_4964), + .I3(com_cmm_u_cmm_errman_cplu_cntr_reg_uflow_4963), + .O(com_cmm_u_cmm_errman_cplu_cntr_N_22271_i) + ); + defparam com_cmm_u_cmm_errman_cplu_cntr_cnt_f0_i_1_.INIT = 16'h00EA; + LUT4 com_cmm_u_cmm_errman_cplu_cntr_cnt_f0_i_1_ ( + .I0(com_cmm_u_cmm_errman_cplu_cntr_reg_cnt[1]), + .I1(com_cmm_u_cmm_errman_cplu_cntr_reg_extra_4966), + .I2(com_cmm_u_cmm_errman_cplu_cntr_reg_inc_dec_b_4964), + .I3(com_cmm_u_cmm_errman_cplu_cntr_reg_uflow_4963), + .O(com_cmm_u_cmm_errman_cplu_cntr_un25_reg_cnt_axb1_i) + ); + defparam com_cmm_u_cmm_errman_cplu_cntr_cnt_f0_i_2_.INIT = 16'h00EA; + LUT4 com_cmm_u_cmm_errman_cplu_cntr_cnt_f0_i_2_ ( + .I0(com_cmm_u_cmm_errman_cplu_cntr_reg_cnt[2]), + .I1(com_cmm_u_cmm_errman_cplu_cntr_reg_extra_4966), + .I2(com_cmm_u_cmm_errman_cplu_cntr_reg_inc_dec_b_4964), + .I3(com_cmm_u_cmm_errman_cplu_cntr_reg_uflow_4963), + .O(com_cmm_u_cmm_errman_cplu_cntr_un25_reg_cnt_axb2_i) + ); + defparam com_cmm_u_cmm_errman_cplu_cntr_cnt_f0_i_3_.INIT = 16'h00EA; + LUT4 com_cmm_u_cmm_errman_cplu_cntr_cnt_f0_i_3_ ( + .I0(com_cmm_u_cmm_errman_cplu_cntr_reg_cnt[3]), + .I1(com_cmm_u_cmm_errman_cplu_cntr_reg_extra_4966), + .I2(com_cmm_u_cmm_errman_cplu_cntr_reg_inc_dec_b_4964), + .I3(com_cmm_u_cmm_errman_cplu_cntr_reg_uflow_4963), + .O(com_cmm_u_cmm_errman_cplu_cntr_un25_reg_cnt_axb3_i) + ); + defparam com_cmm_u_cmm_errman_cplu_cntr_un25_reg_cnt_c1.INIT = 4'h4; + LUT2_L com_cmm_u_cmm_errman_cplu_cntr_un25_reg_cnt_c1 ( + .I0(com_cmm_u_cmm_errman_cplu_cntr_N_22271_i), + .I1(com_cmm_u_cmm_errman_cplu_num[0]), + .LO(com_cmm_u_cmm_errman_cplu_cntr_un25_reg_cnt_c1_0) + ); + defparam com_cmm_u_cmm_errman_cplu_cntr_reg_cnt_6_0_i_m2_0_am_2_.INIT = 8'hD2; + LUT3 com_cmm_u_cmm_errman_cplu_cntr_reg_cnt_6_0_i_m2_0_am_2_ ( + .I0(com_cmm_u_cmm_errman_cplu_cntr_un25_reg_cnt_c1_0), + .I1(com_cmm_u_cmm_errman_cplu_cntr_un25_reg_cnt_axb1_i), + .I2(com_cmm_u_cmm_errman_cplu_cntr_un25_reg_cnt_axb2_i), + .O(com_cmm_u_cmm_errman_cplu_cntr_reg_cnt_6_0_i_m2_0_am_0[2]) + ); + defparam com_cmm_u_cmm_errman_cplu_cntr_reg_cnt_6_0_i_m2_0_bm_2_.INIT = 16'h78F0; + LUT4 com_cmm_u_cmm_errman_cplu_cntr_reg_cnt_6_0_i_m2_0_bm_2_ ( + .I0(com_cmm_u_cmm_errman_cplu_cntr_N_22271_i), + .I1(com_cmm_u_cmm_errman_cplu_cntr_un25_reg_cnt_axb1_i), + .I2(com_cmm_u_cmm_errman_cplu_cntr_un25_reg_cnt_axb2_i), + .I3(com_cmm_u_cmm_errman_cplu_num[0]), + .O(com_cmm_u_cmm_errman_cplu_cntr_reg_cnt_6_0_i_m2_0_bm_0[2]) + ); + MUXF5 com_cmm_u_cmm_errman_cplu_cntr_reg_cnt_6_0_i_m2_0_2_ ( + .I0(com_cmm_u_cmm_errman_cplu_cntr_reg_cnt_6_0_i_m2_0_am_0[2]), + .I1(com_cmm_u_cmm_errman_cplu_cntr_reg_cnt_6_0_i_m2_0_bm_0[2]), + .O(com_cmm_u_cmm_errman_cplu_cntr_reg_cnt_6_0_i_m2_0[2]), + .S(com_cmm_u_cmm_errman_cplu_add_sub_b) + ); + defparam com_cmm_u_cmm_errman_cplu_cntr_reg_uflow_3_0_a2.INIT = 8'h40; + LUT3_L com_cmm_u_cmm_errman_cplu_cntr_reg_uflow_3_0_a2 ( + .I0(com_cmm_u_cmm_errman_cplu_add_sub_b), + .I1(com_cmm_u_cmm_errman_un1_reg_uflow_3), + .I2(com_cmm_u_cmm_errman_cplu_num[0]), + .LO(com_cmm_u_cmm_errman_cplu_cntr_reg_uflow_3) + ); + defparam com_cmm_u_cmm_errman_cplu_cntr_reg_extra_6_0_u_i_m2_0.INIT = 16'h888D; + LUT4_L com_cmm_u_cmm_errman_cplu_cntr_reg_extra_6_0_u_i_m2_0 ( + .I0(com_cmm_u_cmm_errman_cplu_add_sub_b), + .I1(com_cmm_u_cmm_errman_cplu_cntr_un14_reg_cnt[4]), + .I2(com_cmm_u_cmm_errman_cplu_cntr_un25_reg_cnt_axb3_i), + .I3(com_cmm_u_cmm_errman_cplu_cntr_un25_reg_cnt_p4_4961), + .LO(com_cmm_u_cmm_errman_cplu_cntr_reg_extra_6_0_u_i_m2_0_4965) + ); + defparam com_cmm_u_cmm_errman_cplu_cntr_reg_cnt_6_0_i_m2_0_3_.INIT = 16'h782D; + LUT4_L com_cmm_u_cmm_errman_cplu_cntr_reg_cnt_6_0_i_m2_0_3_ ( + .I0(com_cmm_u_cmm_errman_cplu_add_sub_b), + .I1(com_cmm_u_cmm_errman_cplu_cntr_un14_reg_cnt_p4_4962), + .I2(com_cmm_u_cmm_errman_cplu_cntr_un25_reg_cnt_axb3_i), + .I3(com_cmm_u_cmm_errman_cplu_cntr_un25_reg_cnt_p4_4961), + .LO(com_cmm_u_cmm_errman_cplu_cntr_reg_cnt_6_0_i_m2_0[3]) + ); + defparam com_cmm_u_cmm_errman_cplu_cntr_reg_cnt_6_0_i_m2_0_1_.INIT = 16'h69F0; + LUT4_L com_cmm_u_cmm_errman_cplu_cntr_reg_cnt_6_0_i_m2_0_1_ ( + .I0(com_cmm_u_cmm_errman_cplu_cntr_N_22271_i), + .I1(com_cmm_u_cmm_errman_cplu_add_sub_b), + .I2(com_cmm_u_cmm_errman_cplu_cntr_un25_reg_cnt_axb1_i), + .I3(com_cmm_u_cmm_errman_cplu_num[0]), + .LO(com_cmm_u_cmm_errman_cplu_cntr_reg_cnt_6_0_i_m2_0[1]) + ); + defparam com_cmm_u_cmm_errman_cplu_cntr_reg_cnt_6_0_i_m2_0_0_.INIT = 4'h6; + LUT2_L com_cmm_u_cmm_errman_cplu_cntr_reg_cnt_6_0_i_m2_0_0_ ( + .I0(com_cmm_u_cmm_errman_cplu_cntr_N_22271_i), + .I1(com_cmm_u_cmm_errman_cplu_num[0]), + .LO(com_cmm_u_cmm_errman_cplu_cntr_reg_cnt_6_0_i_m2_0[0]) + ); + FDC com_cmm_u_cmm_errman_cplu_cntr_reg_uflow ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_cplu_cntr_reg_uflow_3), + .Q(com_cmm_u_cmm_errman_cplu_cntr_reg_uflow_4963), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_errman_cplu_cntr_reg_inc_dec_b ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_cplu_add_sub_b), + .Q(com_cmm_u_cmm_errman_cplu_cntr_reg_inc_dec_b_4964), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_errman_cplu_cntr_reg_extra ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_cplu_cntr_reg_extra_6_0_u_i_m2_0_4965), + .Q(com_cmm_u_cmm_errman_cplu_cntr_reg_extra_4966), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_errman_cplu_cntr_reg_count_1_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_cplu_cntr_un25_reg_cnt_axb1_i), + .Q(com_cmm_u_cmm_errman_cnt_cplu[1]), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_errman_cplu_cntr_reg_count_0_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_cplu_cntr_N_22271_i), + .Q(com_cmm_u_cmm_errman_cnt_cplu[0]), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_errman_cplu_cntr_reg_cnt_3_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_cplu_cntr_reg_cnt_6_0_i_m2_0[3]), + .Q(com_cmm_u_cmm_errman_cplu_cntr_reg_cnt[3]), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_errman_cplu_cntr_reg_cnt_2_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_cplu_cntr_reg_cnt_6_0_i_m2_0[2]), + .Q(com_cmm_u_cmm_errman_cplu_cntr_reg_cnt[2]), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_errman_cplu_cntr_reg_cnt_1_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_cplu_cntr_reg_cnt_6_0_i_m2_0[1]), + .Q(com_cmm_u_cmm_errman_cplu_cntr_reg_cnt[1]), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_errman_cplu_cntr_reg_cnt_0_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_cplu_cntr_reg_cnt_6_0_i_m2_0[0]), + .Q(com_cmm_u_cmm_errman_cplu_cntr_reg_cnt[0]), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_errman_cplu_cntr_reg_count_3_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_cplu_cntr_un25_reg_cnt_axb3_i), + .Q(com_cmm_u_cmm_errman_cnt_cplu[3]), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_errman_cplu_cntr_reg_count_2_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_cplu_cntr_un25_reg_cnt_axb2_i), + .Q(com_cmm_u_cmm_errman_cnt_cplu[2]), + .CLR(com_cmm_rst_267) + ); + VCC com_cmm_u_cmm_errman_cmt_hdr_buf_VCC ( + .P(com_cmm_u_cmm_errman_cmt_hdr_buf_VCC_4967) + ); + GND com_cmm_u_cmm_errman_cmt_hdr_buf_GND ( + .G(com_cmm_u_cmm_errman_cmt_hdr_buf_GND_4968) + ); + RAM16X1D com_cmm_u_cmm_errman_cmt_hdr_buf_lutram_data_I_1 ( + .DPO(com_cmm_u_cmm_errman_cmt_hdr_buf_lutram_data[40]), + .WCLK(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_reg_cmt_wr_hdr[40]), + .A0(com_cmm_u_cmm_errman_reg_cmt_wp[0]), + .A1(com_cmm_u_cmm_errman_reg_cmt_wp[1]), + .A2(com_cmm_u_cmm_errman_cmt_hdr_buf_GND_4968), + .A3(com_cmm_u_cmm_errman_cmt_hdr_buf_GND_4968), + .DPRA0(com_cmm_u_cmm_errman_reg_cmt_rp[0]), + .DPRA1(com_cmm_u_cmm_errman_reg_cmt_rp[1]), + .DPRA2(com_cmm_u_cmm_errman_cmt_hdr_buf_GND_4968), + .DPRA3(com_cmm_u_cmm_errman_cmt_hdr_buf_GND_4968), + .SPO(NLW_com_cmm_u_cmm_errman_cmt_hdr_buf_lutram_data_I_1_SPO_UNCONNECTED), + .WE(com_cmm_u_cmm_errman_reg_cmt_wr_hdr[48]) + ); + RAM16X1D com_cmm_u_cmm_errman_cmt_hdr_buf_lutram_data_I_2 ( + .DPO(com_cmm_u_cmm_errman_cmt_hdr_buf_lutram_data[27]), + .WCLK(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_reg_cmt_wr_hdr[27]), + .A0(com_cmm_u_cmm_errman_reg_cmt_wp[0]), + .A1(com_cmm_u_cmm_errman_reg_cmt_wp[1]), + .A2(com_cmm_u_cmm_errman_cmt_hdr_buf_GND_4968), + .A3(com_cmm_u_cmm_errman_cmt_hdr_buf_GND_4968), + .DPRA0(com_cmm_u_cmm_errman_reg_cmt_rp[0]), + .DPRA1(com_cmm_u_cmm_errman_reg_cmt_rp[1]), + .DPRA2(com_cmm_u_cmm_errman_cmt_hdr_buf_GND_4968), + .DPRA3(com_cmm_u_cmm_errman_cmt_hdr_buf_GND_4968), + .SPO(NLW_com_cmm_u_cmm_errman_cmt_hdr_buf_lutram_data_I_2_SPO_UNCONNECTED), + .WE(com_cmm_u_cmm_errman_reg_cmt_wr_hdr[48]) + ); + RAM16X1D com_cmm_u_cmm_errman_cmt_hdr_buf_lutram_data_I_3 ( + .DPO(com_cmm_u_cmm_errman_cmt_hdr_buf_lutram_data[1]), + .WCLK(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_reg_cmt_wr_hdr[1]), + .A0(com_cmm_u_cmm_errman_reg_cmt_wp[0]), + .A1(com_cmm_u_cmm_errman_reg_cmt_wp[1]), + .A2(com_cmm_u_cmm_errman_cmt_hdr_buf_GND_4968), + .A3(com_cmm_u_cmm_errman_cmt_hdr_buf_GND_4968), + .DPRA0(com_cmm_u_cmm_errman_reg_cmt_rp[0]), + .DPRA1(com_cmm_u_cmm_errman_reg_cmt_rp[1]), + .DPRA2(com_cmm_u_cmm_errman_cmt_hdr_buf_GND_4968), + .DPRA3(com_cmm_u_cmm_errman_cmt_hdr_buf_GND_4968), + .SPO(NLW_com_cmm_u_cmm_errman_cmt_hdr_buf_lutram_data_I_3_SPO_UNCONNECTED), + .WE(com_cmm_u_cmm_errman_reg_cmt_wr_hdr[48]) + ); + RAM16X1D com_cmm_u_cmm_errman_cmt_hdr_buf_lutram_data_I_4 ( + .DPO(com_cmm_u_cmm_errman_cmt_hdr_buf_lutram_data[5]), + .WCLK(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_reg_cmt_wr_hdr[5]), + .A0(com_cmm_u_cmm_errman_reg_cmt_wp[0]), + .A1(com_cmm_u_cmm_errman_reg_cmt_wp[1]), + .A2(com_cmm_u_cmm_errman_cmt_hdr_buf_GND_4968), + .A3(com_cmm_u_cmm_errman_cmt_hdr_buf_GND_4968), + .DPRA0(com_cmm_u_cmm_errman_reg_cmt_rp[0]), + .DPRA1(com_cmm_u_cmm_errman_reg_cmt_rp[1]), + .DPRA2(com_cmm_u_cmm_errman_cmt_hdr_buf_GND_4968), + .DPRA3(com_cmm_u_cmm_errman_cmt_hdr_buf_GND_4968), + .SPO(NLW_com_cmm_u_cmm_errman_cmt_hdr_buf_lutram_data_I_4_SPO_UNCONNECTED), + .WE(com_cmm_u_cmm_errman_reg_cmt_wr_hdr[48]) + ); + RAM16X1D com_cmm_u_cmm_errman_cmt_hdr_buf_lutram_data_I_5 ( + .DPO(com_cmm_u_cmm_errman_cmt_hdr_buf_lutram_data[30]), + .WCLK(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_reg_cmt_wr_hdr[30]), + .A0(com_cmm_u_cmm_errman_reg_cmt_wp[0]), + .A1(com_cmm_u_cmm_errman_reg_cmt_wp[1]), + .A2(com_cmm_u_cmm_errman_cmt_hdr_buf_GND_4968), + .A3(com_cmm_u_cmm_errman_cmt_hdr_buf_GND_4968), + .DPRA0(com_cmm_u_cmm_errman_reg_cmt_rp[0]), + .DPRA1(com_cmm_u_cmm_errman_reg_cmt_rp[1]), + .DPRA2(com_cmm_u_cmm_errman_cmt_hdr_buf_GND_4968), + .DPRA3(com_cmm_u_cmm_errman_cmt_hdr_buf_GND_4968), + .SPO(NLW_com_cmm_u_cmm_errman_cmt_hdr_buf_lutram_data_I_5_SPO_UNCONNECTED), + .WE(com_cmm_u_cmm_errman_reg_cmt_wr_hdr[48]) + ); + RAM16X1D com_cmm_u_cmm_errman_cmt_hdr_buf_lutram_data_I_6 ( + .DPO(com_cmm_u_cmm_errman_cmt_hdr_buf_lutram_data[43]), + .WCLK(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_reg_cmt_wr_hdr[43]), + .A0(com_cmm_u_cmm_errman_reg_cmt_wp[0]), + .A1(com_cmm_u_cmm_errman_reg_cmt_wp[1]), + .A2(com_cmm_u_cmm_errman_cmt_hdr_buf_GND_4968), + .A3(com_cmm_u_cmm_errman_cmt_hdr_buf_GND_4968), + .DPRA0(com_cmm_u_cmm_errman_reg_cmt_rp[0]), + .DPRA1(com_cmm_u_cmm_errman_reg_cmt_rp[1]), + .DPRA2(com_cmm_u_cmm_errman_cmt_hdr_buf_GND_4968), + .DPRA3(com_cmm_u_cmm_errman_cmt_hdr_buf_GND_4968), + .SPO(NLW_com_cmm_u_cmm_errman_cmt_hdr_buf_lutram_data_I_6_SPO_UNCONNECTED), + .WE(com_cmm_u_cmm_errman_reg_cmt_wr_hdr[48]) + ); + RAM16X1D com_cmm_u_cmm_errman_cmt_hdr_buf_lutram_data_I_7 ( + .DPO(com_cmm_u_cmm_errman_cmt_hdr_buf_lutram_data[16]), + .WCLK(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_reg_cmt_wr_hdr[16]), + .A0(com_cmm_u_cmm_errman_reg_cmt_wp[0]), + .A1(com_cmm_u_cmm_errman_reg_cmt_wp[1]), + .A2(com_cmm_u_cmm_errman_cmt_hdr_buf_GND_4968), + .A3(com_cmm_u_cmm_errman_cmt_hdr_buf_GND_4968), + .DPRA0(com_cmm_u_cmm_errman_reg_cmt_rp[0]), + .DPRA1(com_cmm_u_cmm_errman_reg_cmt_rp[1]), + .DPRA2(com_cmm_u_cmm_errman_cmt_hdr_buf_GND_4968), + .DPRA3(com_cmm_u_cmm_errman_cmt_hdr_buf_GND_4968), + .SPO(NLW_com_cmm_u_cmm_errman_cmt_hdr_buf_lutram_data_I_7_SPO_UNCONNECTED), + .WE(com_cmm_u_cmm_errman_reg_cmt_wr_hdr[48]) + ); + RAM16X1D com_cmm_u_cmm_errman_cmt_hdr_buf_lutram_data_I_8 ( + .DPO(com_cmm_u_cmm_errman_cmt_hdr_buf_lutram_data[29]), + .WCLK(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_reg_cmt_wr_hdr[29]), + .A0(com_cmm_u_cmm_errman_reg_cmt_wp[0]), + .A1(com_cmm_u_cmm_errman_reg_cmt_wp[1]), + .A2(com_cmm_u_cmm_errman_cmt_hdr_buf_GND_4968), + .A3(com_cmm_u_cmm_errman_cmt_hdr_buf_GND_4968), + .DPRA0(com_cmm_u_cmm_errman_reg_cmt_rp[0]), + .DPRA1(com_cmm_u_cmm_errman_reg_cmt_rp[1]), + .DPRA2(com_cmm_u_cmm_errman_cmt_hdr_buf_GND_4968), + .DPRA3(com_cmm_u_cmm_errman_cmt_hdr_buf_GND_4968), + .SPO(NLW_com_cmm_u_cmm_errman_cmt_hdr_buf_lutram_data_I_8_SPO_UNCONNECTED), + .WE(com_cmm_u_cmm_errman_reg_cmt_wr_hdr[48]) + ); + RAM16X1D com_cmm_u_cmm_errman_cmt_hdr_buf_lutram_data_I_9 ( + .DPO(com_cmm_u_cmm_errman_cmt_hdr_buf_lutram_data[42]), + .WCLK(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_reg_cmt_wr_hdr[42]), + .A0(com_cmm_u_cmm_errman_reg_cmt_wp[0]), + .A1(com_cmm_u_cmm_errman_reg_cmt_wp[1]), + .A2(com_cmm_u_cmm_errman_cmt_hdr_buf_GND_4968), + .A3(com_cmm_u_cmm_errman_cmt_hdr_buf_GND_4968), + .DPRA0(com_cmm_u_cmm_errman_reg_cmt_rp[0]), + .DPRA1(com_cmm_u_cmm_errman_reg_cmt_rp[1]), + .DPRA2(com_cmm_u_cmm_errman_cmt_hdr_buf_GND_4968), + .DPRA3(com_cmm_u_cmm_errman_cmt_hdr_buf_GND_4968), + .SPO(NLW_com_cmm_u_cmm_errman_cmt_hdr_buf_lutram_data_I_9_SPO_UNCONNECTED), + .WE(com_cmm_u_cmm_errman_reg_cmt_wr_hdr[48]) + ); + RAM16X1D com_cmm_u_cmm_errman_cmt_hdr_buf_lutram_data_I_10 ( + .DPO(com_cmm_u_cmm_errman_cmt_hdr_buf_lutram_data[15]), + .WCLK(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_reg_cmt_wr_hdr[15]), + .A0(com_cmm_u_cmm_errman_reg_cmt_wp[0]), + .A1(com_cmm_u_cmm_errman_reg_cmt_wp[1]), + .A2(com_cmm_u_cmm_errman_cmt_hdr_buf_GND_4968), + .A3(com_cmm_u_cmm_errman_cmt_hdr_buf_GND_4968), + .DPRA0(com_cmm_u_cmm_errman_reg_cmt_rp[0]), + .DPRA1(com_cmm_u_cmm_errman_reg_cmt_rp[1]), + .DPRA2(com_cmm_u_cmm_errman_cmt_hdr_buf_GND_4968), + .DPRA3(com_cmm_u_cmm_errman_cmt_hdr_buf_GND_4968), + .SPO(NLW_com_cmm_u_cmm_errman_cmt_hdr_buf_lutram_data_I_10_SPO_UNCONNECTED), + .WE(com_cmm_u_cmm_errman_reg_cmt_wr_hdr[48]) + ); + RAM16X1D com_cmm_u_cmm_errman_cmt_hdr_buf_lutram_data_I_11 ( + .DPO(com_cmm_u_cmm_errman_cmt_hdr_buf_lutram_data[18]), + .WCLK(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_reg_cmt_wr_hdr[18]), + .A0(com_cmm_u_cmm_errman_reg_cmt_wp[0]), + .A1(com_cmm_u_cmm_errman_reg_cmt_wp[1]), + .A2(com_cmm_u_cmm_errman_cmt_hdr_buf_GND_4968), + .A3(com_cmm_u_cmm_errman_cmt_hdr_buf_GND_4968), + .DPRA0(com_cmm_u_cmm_errman_reg_cmt_rp[0]), + .DPRA1(com_cmm_u_cmm_errman_reg_cmt_rp[1]), + .DPRA2(com_cmm_u_cmm_errman_cmt_hdr_buf_GND_4968), + .DPRA3(com_cmm_u_cmm_errman_cmt_hdr_buf_GND_4968), + .SPO(NLW_com_cmm_u_cmm_errman_cmt_hdr_buf_lutram_data_I_11_SPO_UNCONNECTED), + .WE(com_cmm_u_cmm_errman_reg_cmt_wr_hdr[48]) + ); + RAM16X1D com_cmm_u_cmm_errman_cmt_hdr_buf_lutram_data_I_12 ( + .DPO(com_cmm_u_cmm_errman_cmt_hdr_buf_lutram_data[32]), + .WCLK(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_reg_cmt_wr_hdr[32]), + .A0(com_cmm_u_cmm_errman_reg_cmt_wp[0]), + .A1(com_cmm_u_cmm_errman_reg_cmt_wp[1]), + .A2(com_cmm_u_cmm_errman_cmt_hdr_buf_GND_4968), + .A3(com_cmm_u_cmm_errman_cmt_hdr_buf_GND_4968), + .DPRA0(com_cmm_u_cmm_errman_reg_cmt_rp[0]), + .DPRA1(com_cmm_u_cmm_errman_reg_cmt_rp[1]), + .DPRA2(com_cmm_u_cmm_errman_cmt_hdr_buf_GND_4968), + .DPRA3(com_cmm_u_cmm_errman_cmt_hdr_buf_GND_4968), + .SPO(NLW_com_cmm_u_cmm_errman_cmt_hdr_buf_lutram_data_I_12_SPO_UNCONNECTED), + .WE(com_cmm_u_cmm_errman_reg_cmt_wr_hdr[48]) + ); + RAM16X1D com_cmm_u_cmm_errman_cmt_hdr_buf_lutram_data_I_13 ( + .DPO(com_cmm_u_cmm_errman_cmt_hdr_buf_lutram_data[45]), + .WCLK(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_reg_cmt_wr_hdr[45]), + .A0(com_cmm_u_cmm_errman_reg_cmt_wp[0]), + .A1(com_cmm_u_cmm_errman_reg_cmt_wp[1]), + .A2(com_cmm_u_cmm_errman_cmt_hdr_buf_GND_4968), + .A3(com_cmm_u_cmm_errman_cmt_hdr_buf_GND_4968), + .DPRA0(com_cmm_u_cmm_errman_reg_cmt_rp[0]), + .DPRA1(com_cmm_u_cmm_errman_reg_cmt_rp[1]), + .DPRA2(com_cmm_u_cmm_errman_cmt_hdr_buf_GND_4968), + .DPRA3(com_cmm_u_cmm_errman_cmt_hdr_buf_GND_4968), + .SPO(NLW_com_cmm_u_cmm_errman_cmt_hdr_buf_lutram_data_I_13_SPO_UNCONNECTED), + .WE(com_cmm_u_cmm_errman_reg_cmt_wr_hdr[48]) + ); + RAM16X1D com_cmm_u_cmm_errman_cmt_hdr_buf_lutram_data_I_14 ( + .DPO(com_cmm_u_cmm_errman_cmt_hdr_buf_lutram_data[28]), + .WCLK(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_reg_cmt_wr_hdr[28]), + .A0(com_cmm_u_cmm_errman_reg_cmt_wp[0]), + .A1(com_cmm_u_cmm_errman_reg_cmt_wp[1]), + .A2(com_cmm_u_cmm_errman_cmt_hdr_buf_GND_4968), + .A3(com_cmm_u_cmm_errman_cmt_hdr_buf_GND_4968), + .DPRA0(com_cmm_u_cmm_errman_reg_cmt_rp[0]), + .DPRA1(com_cmm_u_cmm_errman_reg_cmt_rp[1]), + .DPRA2(com_cmm_u_cmm_errman_cmt_hdr_buf_GND_4968), + .DPRA3(com_cmm_u_cmm_errman_cmt_hdr_buf_GND_4968), + .SPO(NLW_com_cmm_u_cmm_errman_cmt_hdr_buf_lutram_data_I_14_SPO_UNCONNECTED), + .WE(com_cmm_u_cmm_errman_reg_cmt_wr_hdr[48]) + ); + RAM16X1D com_cmm_u_cmm_errman_cmt_hdr_buf_lutram_data_I_15 ( + .DPO(com_cmm_u_cmm_errman_cmt_hdr_buf_lutram_data[0]), + .WCLK(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_reg_cmt_wr_hdr[0]), + .A0(com_cmm_u_cmm_errman_reg_cmt_wp[0]), + .A1(com_cmm_u_cmm_errman_reg_cmt_wp[1]), + .A2(com_cmm_u_cmm_errman_cmt_hdr_buf_GND_4968), + .A3(com_cmm_u_cmm_errman_cmt_hdr_buf_GND_4968), + .DPRA0(com_cmm_u_cmm_errman_reg_cmt_rp[0]), + .DPRA1(com_cmm_u_cmm_errman_reg_cmt_rp[1]), + .DPRA2(com_cmm_u_cmm_errman_cmt_hdr_buf_GND_4968), + .DPRA3(com_cmm_u_cmm_errman_cmt_hdr_buf_GND_4968), + .SPO(NLW_com_cmm_u_cmm_errman_cmt_hdr_buf_lutram_data_I_15_SPO_UNCONNECTED), + .WE(com_cmm_u_cmm_errman_reg_cmt_wr_hdr[48]) + ); + RAM16X1D com_cmm_u_cmm_errman_cmt_hdr_buf_lutram_data_I_16 ( + .DPO(com_cmm_u_cmm_errman_cmt_hdr_buf_lutram_data[4]), + .WCLK(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_reg_cmt_wr_hdr[4]), + .A0(com_cmm_u_cmm_errman_reg_cmt_wp[0]), + .A1(com_cmm_u_cmm_errman_reg_cmt_wp[1]), + .A2(com_cmm_u_cmm_errman_cmt_hdr_buf_GND_4968), + .A3(com_cmm_u_cmm_errman_cmt_hdr_buf_GND_4968), + .DPRA0(com_cmm_u_cmm_errman_reg_cmt_rp[0]), + .DPRA1(com_cmm_u_cmm_errman_reg_cmt_rp[1]), + .DPRA2(com_cmm_u_cmm_errman_cmt_hdr_buf_GND_4968), + .DPRA3(com_cmm_u_cmm_errman_cmt_hdr_buf_GND_4968), + .SPO(NLW_com_cmm_u_cmm_errman_cmt_hdr_buf_lutram_data_I_16_SPO_UNCONNECTED), + .WE(com_cmm_u_cmm_errman_reg_cmt_wr_hdr[48]) + ); + RAM16X1D com_cmm_u_cmm_errman_cmt_hdr_buf_lutram_data_I_17 ( + .DPO(com_cmm_u_cmm_errman_cmt_hdr_buf_lutram_data[8]), + .WCLK(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_reg_cmt_wr_hdr[8]), + .A0(com_cmm_u_cmm_errman_reg_cmt_wp[0]), + .A1(com_cmm_u_cmm_errman_reg_cmt_wp[1]), + .A2(com_cmm_u_cmm_errman_cmt_hdr_buf_GND_4968), + .A3(com_cmm_u_cmm_errman_cmt_hdr_buf_GND_4968), + .DPRA0(com_cmm_u_cmm_errman_reg_cmt_rp[0]), + .DPRA1(com_cmm_u_cmm_errman_reg_cmt_rp[1]), + .DPRA2(com_cmm_u_cmm_errman_cmt_hdr_buf_GND_4968), + .DPRA3(com_cmm_u_cmm_errman_cmt_hdr_buf_GND_4968), + .SPO(NLW_com_cmm_u_cmm_errman_cmt_hdr_buf_lutram_data_I_17_SPO_UNCONNECTED), + .WE(com_cmm_u_cmm_errman_reg_cmt_wr_hdr[48]) + ); + RAM16X1D com_cmm_u_cmm_errman_cmt_hdr_buf_lutram_data_I_18 ( + .DPO(com_cmm_u_cmm_errman_cmt_hdr_buf_lutram_data[2]), + .WCLK(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_reg_cmt_wr_hdr[2]), + .A0(com_cmm_u_cmm_errman_reg_cmt_wp[0]), + .A1(com_cmm_u_cmm_errman_reg_cmt_wp[1]), + .A2(com_cmm_u_cmm_errman_cmt_hdr_buf_GND_4968), + .A3(com_cmm_u_cmm_errman_cmt_hdr_buf_GND_4968), + .DPRA0(com_cmm_u_cmm_errman_reg_cmt_rp[0]), + .DPRA1(com_cmm_u_cmm_errman_reg_cmt_rp[1]), + .DPRA2(com_cmm_u_cmm_errman_cmt_hdr_buf_GND_4968), + .DPRA3(com_cmm_u_cmm_errman_cmt_hdr_buf_GND_4968), + .SPO(NLW_com_cmm_u_cmm_errman_cmt_hdr_buf_lutram_data_I_18_SPO_UNCONNECTED), + .WE(com_cmm_u_cmm_errman_reg_cmt_wr_hdr[48]) + ); + RAM16X1D com_cmm_u_cmm_errman_cmt_hdr_buf_lutram_data_I_19 ( + .DPO(com_cmm_u_cmm_errman_cmt_hdr_buf_lutram_data[3]), + .WCLK(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_reg_cmt_wr_hdr[3]), + .A0(com_cmm_u_cmm_errman_reg_cmt_wp[0]), + .A1(com_cmm_u_cmm_errman_reg_cmt_wp[1]), + .A2(com_cmm_u_cmm_errman_cmt_hdr_buf_GND_4968), + .A3(com_cmm_u_cmm_errman_cmt_hdr_buf_GND_4968), + .DPRA0(com_cmm_u_cmm_errman_reg_cmt_rp[0]), + .DPRA1(com_cmm_u_cmm_errman_reg_cmt_rp[1]), + .DPRA2(com_cmm_u_cmm_errman_cmt_hdr_buf_GND_4968), + .DPRA3(com_cmm_u_cmm_errman_cmt_hdr_buf_GND_4968), + .SPO(NLW_com_cmm_u_cmm_errman_cmt_hdr_buf_lutram_data_I_19_SPO_UNCONNECTED), + .WE(com_cmm_u_cmm_errman_reg_cmt_wr_hdr[48]) + ); + RAM16X1D com_cmm_u_cmm_errman_cmt_hdr_buf_lutram_data_I_20 ( + .DPO(com_cmm_u_cmm_errman_cmt_hdr_buf_lutram_data[7]), + .WCLK(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_reg_cmt_wr_hdr[7]), + .A0(com_cmm_u_cmm_errman_reg_cmt_wp[0]), + .A1(com_cmm_u_cmm_errman_reg_cmt_wp[1]), + .A2(com_cmm_u_cmm_errman_cmt_hdr_buf_GND_4968), + .A3(com_cmm_u_cmm_errman_cmt_hdr_buf_GND_4968), + .DPRA0(com_cmm_u_cmm_errman_reg_cmt_rp[0]), + .DPRA1(com_cmm_u_cmm_errman_reg_cmt_rp[1]), + .DPRA2(com_cmm_u_cmm_errman_cmt_hdr_buf_GND_4968), + .DPRA3(com_cmm_u_cmm_errman_cmt_hdr_buf_GND_4968), + .SPO(NLW_com_cmm_u_cmm_errman_cmt_hdr_buf_lutram_data_I_20_SPO_UNCONNECTED), + .WE(com_cmm_u_cmm_errman_reg_cmt_wr_hdr[48]) + ); + RAM16X1D com_cmm_u_cmm_errman_cmt_hdr_buf_lutram_data_I_21 ( + .DPO(com_cmm_u_cmm_errman_cmt_hdr_buf_lutram_data[20]), + .WCLK(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_reg_cmt_wr_hdr[20]), + .A0(com_cmm_u_cmm_errman_reg_cmt_wp[0]), + .A1(com_cmm_u_cmm_errman_reg_cmt_wp[1]), + .A2(com_cmm_u_cmm_errman_cmt_hdr_buf_GND_4968), + .A3(com_cmm_u_cmm_errman_cmt_hdr_buf_GND_4968), + .DPRA0(com_cmm_u_cmm_errman_reg_cmt_rp[0]), + .DPRA1(com_cmm_u_cmm_errman_reg_cmt_rp[1]), + .DPRA2(com_cmm_u_cmm_errman_cmt_hdr_buf_GND_4968), + .DPRA3(com_cmm_u_cmm_errman_cmt_hdr_buf_GND_4968), + .SPO(NLW_com_cmm_u_cmm_errman_cmt_hdr_buf_lutram_data_I_21_SPO_UNCONNECTED), + .WE(com_cmm_u_cmm_errman_reg_cmt_wr_hdr[48]) + ); + RAM16X1D com_cmm_u_cmm_errman_cmt_hdr_buf_lutram_data_I_22 ( + .DPO(com_cmm_u_cmm_errman_cmt_hdr_buf_lutram_data[33]), + .WCLK(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_reg_cmt_wr_hdr[33]), + .A0(com_cmm_u_cmm_errman_reg_cmt_wp[0]), + .A1(com_cmm_u_cmm_errman_reg_cmt_wp[1]), + .A2(com_cmm_u_cmm_errman_cmt_hdr_buf_GND_4968), + .A3(com_cmm_u_cmm_errman_cmt_hdr_buf_GND_4968), + .DPRA0(com_cmm_u_cmm_errman_reg_cmt_rp[0]), + .DPRA1(com_cmm_u_cmm_errman_reg_cmt_rp[1]), + .DPRA2(com_cmm_u_cmm_errman_cmt_hdr_buf_GND_4968), + .DPRA3(com_cmm_u_cmm_errman_cmt_hdr_buf_GND_4968), + .SPO(NLW_com_cmm_u_cmm_errman_cmt_hdr_buf_lutram_data_I_22_SPO_UNCONNECTED), + .WE(com_cmm_u_cmm_errman_reg_cmt_wr_hdr[48]) + ); + RAM16X1D com_cmm_u_cmm_errman_cmt_hdr_buf_lutram_data_I_23 ( + .DPO(com_cmm_u_cmm_errman_cmt_hdr_buf_lutram_data[46]), + .WCLK(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_reg_cmt_wr_hdr[46]), + .A0(com_cmm_u_cmm_errman_reg_cmt_wp[0]), + .A1(com_cmm_u_cmm_errman_reg_cmt_wp[1]), + .A2(com_cmm_u_cmm_errman_cmt_hdr_buf_GND_4968), + .A3(com_cmm_u_cmm_errman_cmt_hdr_buf_GND_4968), + .DPRA0(com_cmm_u_cmm_errman_reg_cmt_rp[0]), + .DPRA1(com_cmm_u_cmm_errman_reg_cmt_rp[1]), + .DPRA2(com_cmm_u_cmm_errman_cmt_hdr_buf_GND_4968), + .DPRA3(com_cmm_u_cmm_errman_cmt_hdr_buf_GND_4968), + .SPO(NLW_com_cmm_u_cmm_errman_cmt_hdr_buf_lutram_data_I_23_SPO_UNCONNECTED), + .WE(com_cmm_u_cmm_errman_reg_cmt_wr_hdr[48]) + ); + RAM16X1D com_cmm_u_cmm_errman_cmt_hdr_buf_lutram_data_I_24 ( + .DPO(com_cmm_u_cmm_errman_cmt_hdr_buf_lutram_data[9]), + .WCLK(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_reg_cmt_wr_hdr[9]), + .A0(com_cmm_u_cmm_errman_reg_cmt_wp[0]), + .A1(com_cmm_u_cmm_errman_reg_cmt_wp[1]), + .A2(com_cmm_u_cmm_errman_cmt_hdr_buf_GND_4968), + .A3(com_cmm_u_cmm_errman_cmt_hdr_buf_GND_4968), + .DPRA0(com_cmm_u_cmm_errman_reg_cmt_rp[0]), + .DPRA1(com_cmm_u_cmm_errman_reg_cmt_rp[1]), + .DPRA2(com_cmm_u_cmm_errman_cmt_hdr_buf_GND_4968), + .DPRA3(com_cmm_u_cmm_errman_cmt_hdr_buf_GND_4968), + .SPO(NLW_com_cmm_u_cmm_errman_cmt_hdr_buf_lutram_data_I_24_SPO_UNCONNECTED), + .WE(com_cmm_u_cmm_errman_reg_cmt_wr_hdr[48]) + ); + RAM16X1D com_cmm_u_cmm_errman_cmt_hdr_buf_lutram_data_I_25 ( + .DPO(com_cmm_u_cmm_errman_cmt_hdr_buf_lutram_data[41]), + .WCLK(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_reg_cmt_wr_hdr[41]), + .A0(com_cmm_u_cmm_errman_reg_cmt_wp[0]), + .A1(com_cmm_u_cmm_errman_reg_cmt_wp[1]), + .A2(com_cmm_u_cmm_errman_cmt_hdr_buf_GND_4968), + .A3(com_cmm_u_cmm_errman_cmt_hdr_buf_GND_4968), + .DPRA0(com_cmm_u_cmm_errman_reg_cmt_rp[0]), + .DPRA1(com_cmm_u_cmm_errman_reg_cmt_rp[1]), + .DPRA2(com_cmm_u_cmm_errman_cmt_hdr_buf_GND_4968), + .DPRA3(com_cmm_u_cmm_errman_cmt_hdr_buf_GND_4968), + .SPO(NLW_com_cmm_u_cmm_errman_cmt_hdr_buf_lutram_data_I_25_SPO_UNCONNECTED), + .WE(com_cmm_u_cmm_errman_reg_cmt_wr_hdr[48]) + ); + RAM16X1D com_cmm_u_cmm_errman_cmt_hdr_buf_lutram_data_I_26 ( + .DPO(com_cmm_u_cmm_errman_cmt_hdr_buf_lutram_data[14]), + .WCLK(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_reg_cmt_wr_hdr[14]), + .A0(com_cmm_u_cmm_errman_reg_cmt_wp[0]), + .A1(com_cmm_u_cmm_errman_reg_cmt_wp[1]), + .A2(com_cmm_u_cmm_errman_cmt_hdr_buf_GND_4968), + .A3(com_cmm_u_cmm_errman_cmt_hdr_buf_GND_4968), + .DPRA0(com_cmm_u_cmm_errman_reg_cmt_rp[0]), + .DPRA1(com_cmm_u_cmm_errman_reg_cmt_rp[1]), + .DPRA2(com_cmm_u_cmm_errman_cmt_hdr_buf_GND_4968), + .DPRA3(com_cmm_u_cmm_errman_cmt_hdr_buf_GND_4968), + .SPO(NLW_com_cmm_u_cmm_errman_cmt_hdr_buf_lutram_data_I_26_SPO_UNCONNECTED), + .WE(com_cmm_u_cmm_errman_reg_cmt_wr_hdr[48]) + ); + RAM16X1D com_cmm_u_cmm_errman_cmt_hdr_buf_lutram_data_I_27 ( + .DPO(com_cmm_u_cmm_errman_cmt_hdr_buf_lutram_data[19]), + .WCLK(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_reg_cmt_wr_hdr[19]), + .A0(com_cmm_u_cmm_errman_reg_cmt_wp[0]), + .A1(com_cmm_u_cmm_errman_reg_cmt_wp[1]), + .A2(com_cmm_u_cmm_errman_cmt_hdr_buf_GND_4968), + .A3(com_cmm_u_cmm_errman_cmt_hdr_buf_GND_4968), + .DPRA0(com_cmm_u_cmm_errman_reg_cmt_rp[0]), + .DPRA1(com_cmm_u_cmm_errman_reg_cmt_rp[1]), + .DPRA2(com_cmm_u_cmm_errman_cmt_hdr_buf_GND_4968), + .DPRA3(com_cmm_u_cmm_errman_cmt_hdr_buf_GND_4968), + .SPO(NLW_com_cmm_u_cmm_errman_cmt_hdr_buf_lutram_data_I_27_SPO_UNCONNECTED), + .WE(com_cmm_u_cmm_errman_reg_cmt_wr_hdr[48]) + ); + RAM16X1D com_cmm_u_cmm_errman_cmt_hdr_buf_lutram_data_I_28 ( + .DPO(com_cmm_u_cmm_errman_cmt_hdr_buf_lutram_data[6]), + .WCLK(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_reg_cmt_wr_hdr[6]), + .A0(com_cmm_u_cmm_errman_reg_cmt_wp[0]), + .A1(com_cmm_u_cmm_errman_reg_cmt_wp[1]), + .A2(com_cmm_u_cmm_errman_cmt_hdr_buf_GND_4968), + .A3(com_cmm_u_cmm_errman_cmt_hdr_buf_GND_4968), + .DPRA0(com_cmm_u_cmm_errman_reg_cmt_rp[0]), + .DPRA1(com_cmm_u_cmm_errman_reg_cmt_rp[1]), + .DPRA2(com_cmm_u_cmm_errman_cmt_hdr_buf_GND_4968), + .DPRA3(com_cmm_u_cmm_errman_cmt_hdr_buf_GND_4968), + .SPO(NLW_com_cmm_u_cmm_errman_cmt_hdr_buf_lutram_data_I_28_SPO_UNCONNECTED), + .WE(com_cmm_u_cmm_errman_reg_cmt_wr_hdr[48]) + ); + RAM16X1D com_cmm_u_cmm_errman_cmt_hdr_buf_lutram_data_I_29 ( + .DPO(com_cmm_u_cmm_errman_cmt_hdr_buf_lutram_data[11]), + .WCLK(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_reg_cmt_wr_hdr[11]), + .A0(com_cmm_u_cmm_errman_reg_cmt_wp[0]), + .A1(com_cmm_u_cmm_errman_reg_cmt_wp[1]), + .A2(com_cmm_u_cmm_errman_cmt_hdr_buf_GND_4968), + .A3(com_cmm_u_cmm_errman_cmt_hdr_buf_GND_4968), + .DPRA0(com_cmm_u_cmm_errman_reg_cmt_rp[0]), + .DPRA1(com_cmm_u_cmm_errman_reg_cmt_rp[1]), + .DPRA2(com_cmm_u_cmm_errman_cmt_hdr_buf_GND_4968), + .DPRA3(com_cmm_u_cmm_errman_cmt_hdr_buf_GND_4968), + .SPO(NLW_com_cmm_u_cmm_errman_cmt_hdr_buf_lutram_data_I_29_SPO_UNCONNECTED), + .WE(com_cmm_u_cmm_errman_reg_cmt_wr_hdr[48]) + ); + RAM16X1D com_cmm_u_cmm_errman_cmt_hdr_buf_lutram_data_I_30 ( + .DPO(com_cmm_u_cmm_errman_cmt_hdr_buf_lutram_data[24]), + .WCLK(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_reg_cmt_wr_hdr[24]), + .A0(com_cmm_u_cmm_errman_reg_cmt_wp[0]), + .A1(com_cmm_u_cmm_errman_reg_cmt_wp[1]), + .A2(com_cmm_u_cmm_errman_cmt_hdr_buf_GND_4968), + .A3(com_cmm_u_cmm_errman_cmt_hdr_buf_GND_4968), + .DPRA0(com_cmm_u_cmm_errman_reg_cmt_rp[0]), + .DPRA1(com_cmm_u_cmm_errman_reg_cmt_rp[1]), + .DPRA2(com_cmm_u_cmm_errman_cmt_hdr_buf_GND_4968), + .DPRA3(com_cmm_u_cmm_errman_cmt_hdr_buf_GND_4968), + .SPO(NLW_com_cmm_u_cmm_errman_cmt_hdr_buf_lutram_data_I_30_SPO_UNCONNECTED), + .WE(com_cmm_u_cmm_errman_reg_cmt_wr_hdr[48]) + ); + RAM16X1D com_cmm_u_cmm_errman_cmt_hdr_buf_lutram_data_I_31 ( + .DPO(com_cmm_u_cmm_errman_cmt_hdr_buf_lutram_data[39]), + .WCLK(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_reg_cmt_wr_hdr[39]), + .A0(com_cmm_u_cmm_errman_reg_cmt_wp[0]), + .A1(com_cmm_u_cmm_errman_reg_cmt_wp[1]), + .A2(com_cmm_u_cmm_errman_cmt_hdr_buf_GND_4968), + .A3(com_cmm_u_cmm_errman_cmt_hdr_buf_GND_4968), + .DPRA0(com_cmm_u_cmm_errman_reg_cmt_rp[0]), + .DPRA1(com_cmm_u_cmm_errman_reg_cmt_rp[1]), + .DPRA2(com_cmm_u_cmm_errman_cmt_hdr_buf_GND_4968), + .DPRA3(com_cmm_u_cmm_errman_cmt_hdr_buf_GND_4968), + .SPO(NLW_com_cmm_u_cmm_errman_cmt_hdr_buf_lutram_data_I_31_SPO_UNCONNECTED), + .WE(com_cmm_u_cmm_errman_reg_cmt_wr_hdr[48]) + ); + RAM16X1D com_cmm_u_cmm_errman_cmt_hdr_buf_lutram_data_I_32 ( + .DPO(com_cmm_u_cmm_errman_cmt_hdr_buf_lutram_data[12]), + .WCLK(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_reg_cmt_wr_hdr[12]), + .A0(com_cmm_u_cmm_errman_reg_cmt_wp[0]), + .A1(com_cmm_u_cmm_errman_reg_cmt_wp[1]), + .A2(com_cmm_u_cmm_errman_cmt_hdr_buf_GND_4968), + .A3(com_cmm_u_cmm_errman_cmt_hdr_buf_GND_4968), + .DPRA0(com_cmm_u_cmm_errman_reg_cmt_rp[0]), + .DPRA1(com_cmm_u_cmm_errman_reg_cmt_rp[1]), + .DPRA2(com_cmm_u_cmm_errman_cmt_hdr_buf_GND_4968), + .DPRA3(com_cmm_u_cmm_errman_cmt_hdr_buf_GND_4968), + .SPO(NLW_com_cmm_u_cmm_errman_cmt_hdr_buf_lutram_data_I_32_SPO_UNCONNECTED), + .WE(com_cmm_u_cmm_errman_reg_cmt_wr_hdr[48]) + ); + RAM16X1D com_cmm_u_cmm_errman_cmt_hdr_buf_lutram_data_I_33 ( + .DPO(com_cmm_u_cmm_errman_cmt_hdr_buf_lutram_data[25]), + .WCLK(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_reg_cmt_wr_hdr[25]), + .A0(com_cmm_u_cmm_errman_reg_cmt_wp[0]), + .A1(com_cmm_u_cmm_errman_reg_cmt_wp[1]), + .A2(com_cmm_u_cmm_errman_cmt_hdr_buf_GND_4968), + .A3(com_cmm_u_cmm_errman_cmt_hdr_buf_GND_4968), + .DPRA0(com_cmm_u_cmm_errman_reg_cmt_rp[0]), + .DPRA1(com_cmm_u_cmm_errman_reg_cmt_rp[1]), + .DPRA2(com_cmm_u_cmm_errman_cmt_hdr_buf_GND_4968), + .DPRA3(com_cmm_u_cmm_errman_cmt_hdr_buf_GND_4968), + .SPO(NLW_com_cmm_u_cmm_errman_cmt_hdr_buf_lutram_data_I_33_SPO_UNCONNECTED), + .WE(com_cmm_u_cmm_errman_reg_cmt_wr_hdr[48]) + ); + RAM16X1D com_cmm_u_cmm_errman_cmt_hdr_buf_lutram_data_I_34 ( + .DPO(com_cmm_u_cmm_errman_cmt_hdr_buf_lutram_data[38]), + .WCLK(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_reg_cmt_wr_hdr[38]), + .A0(com_cmm_u_cmm_errman_reg_cmt_wp[0]), + .A1(com_cmm_u_cmm_errman_reg_cmt_wp[1]), + .A2(com_cmm_u_cmm_errman_cmt_hdr_buf_GND_4968), + .A3(com_cmm_u_cmm_errman_cmt_hdr_buf_GND_4968), + .DPRA0(com_cmm_u_cmm_errman_reg_cmt_rp[0]), + .DPRA1(com_cmm_u_cmm_errman_reg_cmt_rp[1]), + .DPRA2(com_cmm_u_cmm_errman_cmt_hdr_buf_GND_4968), + .DPRA3(com_cmm_u_cmm_errman_cmt_hdr_buf_GND_4968), + .SPO(NLW_com_cmm_u_cmm_errman_cmt_hdr_buf_lutram_data_I_34_SPO_UNCONNECTED), + .WE(com_cmm_u_cmm_errman_reg_cmt_wr_hdr[48]) + ); + RAM16X1D com_cmm_u_cmm_errman_cmt_hdr_buf_lutram_data_I_35 ( + .DPO(com_cmm_u_cmm_errman_cmt_hdr_buf_lutram_data[13]), + .WCLK(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_reg_cmt_wr_hdr[13]), + .A0(com_cmm_u_cmm_errman_reg_cmt_wp[0]), + .A1(com_cmm_u_cmm_errman_reg_cmt_wp[1]), + .A2(com_cmm_u_cmm_errman_cmt_hdr_buf_GND_4968), + .A3(com_cmm_u_cmm_errman_cmt_hdr_buf_GND_4968), + .DPRA0(com_cmm_u_cmm_errman_reg_cmt_rp[0]), + .DPRA1(com_cmm_u_cmm_errman_reg_cmt_rp[1]), + .DPRA2(com_cmm_u_cmm_errman_cmt_hdr_buf_GND_4968), + .DPRA3(com_cmm_u_cmm_errman_cmt_hdr_buf_GND_4968), + .SPO(NLW_com_cmm_u_cmm_errman_cmt_hdr_buf_lutram_data_I_35_SPO_UNCONNECTED), + .WE(com_cmm_u_cmm_errman_reg_cmt_wr_hdr[48]) + ); + RAM16X1D com_cmm_u_cmm_errman_cmt_hdr_buf_lutram_data_I_36 ( + .DPO(com_cmm_u_cmm_errman_cmt_hdr_buf_lutram_data[26]), + .WCLK(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_reg_cmt_wr_hdr[26]), + .A0(com_cmm_u_cmm_errman_reg_cmt_wp[0]), + .A1(com_cmm_u_cmm_errman_reg_cmt_wp[1]), + .A2(com_cmm_u_cmm_errman_cmt_hdr_buf_GND_4968), + .A3(com_cmm_u_cmm_errman_cmt_hdr_buf_GND_4968), + .DPRA0(com_cmm_u_cmm_errman_reg_cmt_rp[0]), + .DPRA1(com_cmm_u_cmm_errman_reg_cmt_rp[1]), + .DPRA2(com_cmm_u_cmm_errman_cmt_hdr_buf_GND_4968), + .DPRA3(com_cmm_u_cmm_errman_cmt_hdr_buf_GND_4968), + .SPO(NLW_com_cmm_u_cmm_errman_cmt_hdr_buf_lutram_data_I_36_SPO_UNCONNECTED), + .WE(com_cmm_u_cmm_errman_reg_cmt_wr_hdr[48]) + ); + RAM16X1D com_cmm_u_cmm_errman_cmt_hdr_buf_lutram_data_I_37 ( + .DPO(com_cmm_u_cmm_errman_cmt_hdr_buf_lutram_data[22]), + .WCLK(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_reg_cmt_wr_hdr[22]), + .A0(com_cmm_u_cmm_errman_reg_cmt_wp[0]), + .A1(com_cmm_u_cmm_errman_reg_cmt_wp[1]), + .A2(com_cmm_u_cmm_errman_cmt_hdr_buf_GND_4968), + .A3(com_cmm_u_cmm_errman_cmt_hdr_buf_GND_4968), + .DPRA0(com_cmm_u_cmm_errman_reg_cmt_rp[0]), + .DPRA1(com_cmm_u_cmm_errman_reg_cmt_rp[1]), + .DPRA2(com_cmm_u_cmm_errman_cmt_hdr_buf_GND_4968), + .DPRA3(com_cmm_u_cmm_errman_cmt_hdr_buf_GND_4968), + .SPO(NLW_com_cmm_u_cmm_errman_cmt_hdr_buf_lutram_data_I_37_SPO_UNCONNECTED), + .WE(com_cmm_u_cmm_errman_reg_cmt_wr_hdr[48]) + ); + RAM16X1D com_cmm_u_cmm_errman_cmt_hdr_buf_lutram_data_I_38 ( + .DPO(com_cmm_u_cmm_errman_cmt_hdr_buf_lutram_data[49]), + .WCLK(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_cmt_hdr_buf_GND_4968), + .A0(com_cmm_u_cmm_errman_reg_cmt_wp[0]), + .A1(com_cmm_u_cmm_errman_reg_cmt_wp[1]), + .A2(com_cmm_u_cmm_errman_cmt_hdr_buf_GND_4968), + .A3(com_cmm_u_cmm_errman_cmt_hdr_buf_GND_4968), + .DPRA0(com_cmm_u_cmm_errman_reg_cmt_rp[0]), + .DPRA1(com_cmm_u_cmm_errman_reg_cmt_rp[1]), + .DPRA2(com_cmm_u_cmm_errman_cmt_hdr_buf_GND_4968), + .DPRA3(com_cmm_u_cmm_errman_cmt_hdr_buf_GND_4968), + .SPO(NLW_com_cmm_u_cmm_errman_cmt_hdr_buf_lutram_data_I_38_SPO_UNCONNECTED), + .WE(com_cmm_u_cmm_errman_reg_cmt_wr_hdr[48]) + ); + RAM16X1D com_cmm_u_cmm_errman_cmt_hdr_buf_lutram_data_I_39 ( + .DPO(com_cmm_u_cmm_errman_cmt_hdr_buf_lutram_data[23]), + .WCLK(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_reg_cmt_wr_hdr[23]), + .A0(com_cmm_u_cmm_errman_reg_cmt_wp[0]), + .A1(com_cmm_u_cmm_errman_reg_cmt_wp[1]), + .A2(com_cmm_u_cmm_errman_cmt_hdr_buf_GND_4968), + .A3(com_cmm_u_cmm_errman_cmt_hdr_buf_GND_4968), + .DPRA0(com_cmm_u_cmm_errman_reg_cmt_rp[0]), + .DPRA1(com_cmm_u_cmm_errman_reg_cmt_rp[1]), + .DPRA2(com_cmm_u_cmm_errman_cmt_hdr_buf_GND_4968), + .DPRA3(com_cmm_u_cmm_errman_cmt_hdr_buf_GND_4968), + .SPO(NLW_com_cmm_u_cmm_errman_cmt_hdr_buf_lutram_data_I_39_SPO_UNCONNECTED), + .WE(com_cmm_u_cmm_errman_reg_cmt_wr_hdr[48]) + ); + RAM16X1D com_cmm_u_cmm_errman_cmt_hdr_buf_lutram_data_I_40 ( + .DPO(com_cmm_u_cmm_errman_cmt_hdr_buf_lutram_data[36]), + .WCLK(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_reg_cmt_wr_hdr[36]), + .A0(com_cmm_u_cmm_errman_reg_cmt_wp[0]), + .A1(com_cmm_u_cmm_errman_reg_cmt_wp[1]), + .A2(com_cmm_u_cmm_errman_cmt_hdr_buf_GND_4968), + .A3(com_cmm_u_cmm_errman_cmt_hdr_buf_GND_4968), + .DPRA0(com_cmm_u_cmm_errman_reg_cmt_rp[0]), + .DPRA1(com_cmm_u_cmm_errman_reg_cmt_rp[1]), + .DPRA2(com_cmm_u_cmm_errman_cmt_hdr_buf_GND_4968), + .DPRA3(com_cmm_u_cmm_errman_cmt_hdr_buf_GND_4968), + .SPO(NLW_com_cmm_u_cmm_errman_cmt_hdr_buf_lutram_data_I_40_SPO_UNCONNECTED), + .WE(com_cmm_u_cmm_errman_reg_cmt_wr_hdr[48]) + ); + RAM16X1D com_cmm_u_cmm_errman_cmt_hdr_buf_lutram_data_I_41 ( + .DPO(com_cmm_u_cmm_errman_cmt_hdr_buf_lutram_data[10]), + .WCLK(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_reg_cmt_wr_hdr[10]), + .A0(com_cmm_u_cmm_errman_reg_cmt_wp[0]), + .A1(com_cmm_u_cmm_errman_reg_cmt_wp[1]), + .A2(com_cmm_u_cmm_errman_cmt_hdr_buf_GND_4968), + .A3(com_cmm_u_cmm_errman_cmt_hdr_buf_GND_4968), + .DPRA0(com_cmm_u_cmm_errman_reg_cmt_rp[0]), + .DPRA1(com_cmm_u_cmm_errman_reg_cmt_rp[1]), + .DPRA2(com_cmm_u_cmm_errman_cmt_hdr_buf_GND_4968), + .DPRA3(com_cmm_u_cmm_errman_cmt_hdr_buf_GND_4968), + .SPO(NLW_com_cmm_u_cmm_errman_cmt_hdr_buf_lutram_data_I_41_SPO_UNCONNECTED), + .WE(com_cmm_u_cmm_errman_reg_cmt_wr_hdr[48]) + ); + RAM16X1D com_cmm_u_cmm_errman_cmt_hdr_buf_lutram_data_I_42 ( + .DPO(com_cmm_u_cmm_errman_cmt_hdr_buf_lutram_data[31]), + .WCLK(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_reg_cmt_wr_hdr[31]), + .A0(com_cmm_u_cmm_errman_reg_cmt_wp[0]), + .A1(com_cmm_u_cmm_errman_reg_cmt_wp[1]), + .A2(com_cmm_u_cmm_errman_cmt_hdr_buf_GND_4968), + .A3(com_cmm_u_cmm_errman_cmt_hdr_buf_GND_4968), + .DPRA0(com_cmm_u_cmm_errman_reg_cmt_rp[0]), + .DPRA1(com_cmm_u_cmm_errman_reg_cmt_rp[1]), + .DPRA2(com_cmm_u_cmm_errman_cmt_hdr_buf_GND_4968), + .DPRA3(com_cmm_u_cmm_errman_cmt_hdr_buf_GND_4968), + .SPO(NLW_com_cmm_u_cmm_errman_cmt_hdr_buf_lutram_data_I_42_SPO_UNCONNECTED), + .WE(com_cmm_u_cmm_errman_reg_cmt_wr_hdr[48]) + ); + RAM16X1D com_cmm_u_cmm_errman_cmt_hdr_buf_lutram_data_I_43 ( + .DPO(com_cmm_u_cmm_errman_cmt_hdr_buf_lutram_data[44]), + .WCLK(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_reg_cmt_wr_hdr[44]), + .A0(com_cmm_u_cmm_errman_reg_cmt_wp[0]), + .A1(com_cmm_u_cmm_errman_reg_cmt_wp[1]), + .A2(com_cmm_u_cmm_errman_cmt_hdr_buf_GND_4968), + .A3(com_cmm_u_cmm_errman_cmt_hdr_buf_GND_4968), + .DPRA0(com_cmm_u_cmm_errman_reg_cmt_rp[0]), + .DPRA1(com_cmm_u_cmm_errman_reg_cmt_rp[1]), + .DPRA2(com_cmm_u_cmm_errman_cmt_hdr_buf_GND_4968), + .DPRA3(com_cmm_u_cmm_errman_cmt_hdr_buf_GND_4968), + .SPO(NLW_com_cmm_u_cmm_errman_cmt_hdr_buf_lutram_data_I_43_SPO_UNCONNECTED), + .WE(com_cmm_u_cmm_errman_reg_cmt_wr_hdr[48]) + ); + RAM16X1D com_cmm_u_cmm_errman_cmt_hdr_buf_lutram_data_I_44 ( + .DPO(com_cmm_u_cmm_errman_cmt_hdr_buf_lutram_data[17]), + .WCLK(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_reg_cmt_wr_hdr[17]), + .A0(com_cmm_u_cmm_errman_reg_cmt_wp[0]), + .A1(com_cmm_u_cmm_errman_reg_cmt_wp[1]), + .A2(com_cmm_u_cmm_errman_cmt_hdr_buf_GND_4968), + .A3(com_cmm_u_cmm_errman_cmt_hdr_buf_GND_4968), + .DPRA0(com_cmm_u_cmm_errman_reg_cmt_rp[0]), + .DPRA1(com_cmm_u_cmm_errman_reg_cmt_rp[1]), + .DPRA2(com_cmm_u_cmm_errman_cmt_hdr_buf_GND_4968), + .DPRA3(com_cmm_u_cmm_errman_cmt_hdr_buf_GND_4968), + .SPO(NLW_com_cmm_u_cmm_errman_cmt_hdr_buf_lutram_data_I_44_SPO_UNCONNECTED), + .WE(com_cmm_u_cmm_errman_reg_cmt_wr_hdr[48]) + ); + RAM16X1D com_cmm_u_cmm_errman_cmt_hdr_buf_lutram_data_I_45 ( + .DPO(com_cmm_u_cmm_errman_cmt_hdr_buf_lutram_data[21]), + .WCLK(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_reg_cmt_wr_hdr[21]), + .A0(com_cmm_u_cmm_errman_reg_cmt_wp[0]), + .A1(com_cmm_u_cmm_errman_reg_cmt_wp[1]), + .A2(com_cmm_u_cmm_errman_cmt_hdr_buf_GND_4968), + .A3(com_cmm_u_cmm_errman_cmt_hdr_buf_GND_4968), + .DPRA0(com_cmm_u_cmm_errman_reg_cmt_rp[0]), + .DPRA1(com_cmm_u_cmm_errman_reg_cmt_rp[1]), + .DPRA2(com_cmm_u_cmm_errman_cmt_hdr_buf_GND_4968), + .DPRA3(com_cmm_u_cmm_errman_cmt_hdr_buf_GND_4968), + .SPO(NLW_com_cmm_u_cmm_errman_cmt_hdr_buf_lutram_data_I_45_SPO_UNCONNECTED), + .WE(com_cmm_u_cmm_errman_reg_cmt_wr_hdr[48]) + ); + RAM16X1D com_cmm_u_cmm_errman_cmt_hdr_buf_lutram_data_I_46 ( + .DPO(com_cmm_u_cmm_errman_cmt_hdr_buf_lutram_data[34]), + .WCLK(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_reg_cmt_wr_hdr[34]), + .A0(com_cmm_u_cmm_errman_reg_cmt_wp[0]), + .A1(com_cmm_u_cmm_errman_reg_cmt_wp[1]), + .A2(com_cmm_u_cmm_errman_cmt_hdr_buf_GND_4968), + .A3(com_cmm_u_cmm_errman_cmt_hdr_buf_GND_4968), + .DPRA0(com_cmm_u_cmm_errman_reg_cmt_rp[0]), + .DPRA1(com_cmm_u_cmm_errman_reg_cmt_rp[1]), + .DPRA2(com_cmm_u_cmm_errman_cmt_hdr_buf_GND_4968), + .DPRA3(com_cmm_u_cmm_errman_cmt_hdr_buf_GND_4968), + .SPO(NLW_com_cmm_u_cmm_errman_cmt_hdr_buf_lutram_data_I_46_SPO_UNCONNECTED), + .WE(com_cmm_u_cmm_errman_reg_cmt_wr_hdr[48]) + ); + RAM16X1D com_cmm_u_cmm_errman_cmt_hdr_buf_lutram_data_I_47 ( + .DPO(com_cmm_u_cmm_errman_cmt_hdr_buf_lutram_data[47]), + .WCLK(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_reg_cmt_wr_hdr[47]), + .A0(com_cmm_u_cmm_errman_reg_cmt_wp[0]), + .A1(com_cmm_u_cmm_errman_reg_cmt_wp[1]), + .A2(com_cmm_u_cmm_errman_cmt_hdr_buf_GND_4968), + .A3(com_cmm_u_cmm_errman_cmt_hdr_buf_GND_4968), + .DPRA0(com_cmm_u_cmm_errman_reg_cmt_rp[0]), + .DPRA1(com_cmm_u_cmm_errman_reg_cmt_rp[1]), + .DPRA2(com_cmm_u_cmm_errman_cmt_hdr_buf_GND_4968), + .DPRA3(com_cmm_u_cmm_errman_cmt_hdr_buf_GND_4968), + .SPO(NLW_com_cmm_u_cmm_errman_cmt_hdr_buf_lutram_data_I_47_SPO_UNCONNECTED), + .WE(com_cmm_u_cmm_errman_reg_cmt_wr_hdr[48]) + ); + RAM16X1D com_cmm_u_cmm_errman_cmt_hdr_buf_lutram_data_I_48 ( + .DPO(com_cmm_u_cmm_errman_cmt_hdr_buf_lutram_data[35]), + .WCLK(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_reg_cmt_wr_hdr[35]), + .A0(com_cmm_u_cmm_errman_reg_cmt_wp[0]), + .A1(com_cmm_u_cmm_errman_reg_cmt_wp[1]), + .A2(com_cmm_u_cmm_errman_cmt_hdr_buf_GND_4968), + .A3(com_cmm_u_cmm_errman_cmt_hdr_buf_GND_4968), + .DPRA0(com_cmm_u_cmm_errman_reg_cmt_rp[0]), + .DPRA1(com_cmm_u_cmm_errman_reg_cmt_rp[1]), + .DPRA2(com_cmm_u_cmm_errman_cmt_hdr_buf_GND_4968), + .DPRA3(com_cmm_u_cmm_errman_cmt_hdr_buf_GND_4968), + .SPO(NLW_com_cmm_u_cmm_errman_cmt_hdr_buf_lutram_data_I_48_SPO_UNCONNECTED), + .WE(com_cmm_u_cmm_errman_reg_cmt_wr_hdr[48]) + ); + RAM16X1D com_cmm_u_cmm_errman_cmt_hdr_buf_lutram_data_I_49 ( + .DPO(com_cmm_u_cmm_errman_cmt_hdr_buf_lutram_data[48]), + .WCLK(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_cmt_hdr_buf_VCC_4967), + .A0(com_cmm_u_cmm_errman_reg_cmt_wp[0]), + .A1(com_cmm_u_cmm_errman_reg_cmt_wp[1]), + .A2(com_cmm_u_cmm_errman_cmt_hdr_buf_GND_4968), + .A3(com_cmm_u_cmm_errman_cmt_hdr_buf_GND_4968), + .DPRA0(com_cmm_u_cmm_errman_reg_cmt_rp[0]), + .DPRA1(com_cmm_u_cmm_errman_reg_cmt_rp[1]), + .DPRA2(com_cmm_u_cmm_errman_cmt_hdr_buf_GND_4968), + .DPRA3(com_cmm_u_cmm_errman_cmt_hdr_buf_GND_4968), + .SPO(NLW_com_cmm_u_cmm_errman_cmt_hdr_buf_lutram_data_I_49_SPO_UNCONNECTED), + .WE(com_cmm_u_cmm_errman_reg_cmt_wr_hdr[48]) + ); + RAM16X1D com_cmm_u_cmm_errman_cmt_hdr_buf_lutram_data_I_50 ( + .DPO(com_cmm_u_cmm_errman_cmt_hdr_buf_lutram_data[37]), + .WCLK(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_reg_cmt_wr_hdr[37]), + .A0(com_cmm_u_cmm_errman_reg_cmt_wp[0]), + .A1(com_cmm_u_cmm_errman_reg_cmt_wp[1]), + .A2(com_cmm_u_cmm_errman_cmt_hdr_buf_GND_4968), + .A3(com_cmm_u_cmm_errman_cmt_hdr_buf_GND_4968), + .DPRA0(com_cmm_u_cmm_errman_reg_cmt_rp[0]), + .DPRA1(com_cmm_u_cmm_errman_reg_cmt_rp[1]), + .DPRA2(com_cmm_u_cmm_errman_cmt_hdr_buf_GND_4968), + .DPRA3(com_cmm_u_cmm_errman_cmt_hdr_buf_GND_4968), + .SPO(NLW_com_cmm_u_cmm_errman_cmt_hdr_buf_lutram_data_I_50_SPO_UNCONNECTED), + .WE(com_cmm_u_cmm_errman_reg_cmt_wr_hdr[48]) + ); + FDC com_cmm_u_cmm_errman_cmt_hdr_buf_reg_rdata_8_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_cmt_hdr_buf_lutram_data[8]), + .Q(com_cmm_u_cmm_errman_cmt_rd_hdr[8]), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_errman_cmt_hdr_buf_reg_rdata_7_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_cmt_hdr_buf_lutram_data[7]), + .Q(com_cmm_u_cmm_errman_cmt_rd_hdr[7]), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_errman_cmt_hdr_buf_reg_rdata_6_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_cmt_hdr_buf_lutram_data[6]), + .Q(com_cmm_u_cmm_errman_cmt_rd_hdr[6]), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_errman_cmt_hdr_buf_reg_rdata_5_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_cmt_hdr_buf_lutram_data[5]), + .Q(com_cmm_u_cmm_errman_cmt_rd_hdr[5]), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_errman_cmt_hdr_buf_reg_rdata_4_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_cmt_hdr_buf_lutram_data[4]), + .Q(com_cmm_u_cmm_errman_cmt_rd_hdr[4]), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_errman_cmt_hdr_buf_reg_rdata_3_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_cmt_hdr_buf_lutram_data[3]), + .Q(com_cmm_u_cmm_errman_cmt_rd_hdr[3]), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_errman_cmt_hdr_buf_reg_rdata_2_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_cmt_hdr_buf_lutram_data[2]), + .Q(com_cmm_u_cmm_errman_cmt_rd_hdr[2]), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_errman_cmt_hdr_buf_reg_rdata_1_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_cmt_hdr_buf_lutram_data[1]), + .Q(com_cmm_u_cmm_errman_cmt_rd_hdr[1]), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_errman_cmt_hdr_buf_reg_rdata_0_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_cmt_hdr_buf_lutram_data[0]), + .Q(com_cmm_u_cmm_errman_cmt_rd_hdr[0]), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_errman_cmt_hdr_buf_reg_rdata_23_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_cmt_hdr_buf_lutram_data[23]), + .Q(com_cmm_u_cmm_errman_cmt_rd_hdr[23]), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_errman_cmt_hdr_buf_reg_rdata_22_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_cmt_hdr_buf_lutram_data[22]), + .Q(com_cmm_u_cmm_errman_cmt_rd_hdr[22]), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_errman_cmt_hdr_buf_reg_rdata_21_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_cmt_hdr_buf_lutram_data[21]), + .Q(com_cmm_u_cmm_errman_cmt_rd_hdr[21]), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_errman_cmt_hdr_buf_reg_rdata_20_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_cmt_hdr_buf_lutram_data[20]), + .Q(com_cmm_u_cmm_errman_cmt_rd_hdr[20]), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_errman_cmt_hdr_buf_reg_rdata_19_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_cmt_hdr_buf_lutram_data[19]), + .Q(com_cmm_u_cmm_errman_cmt_rd_hdr[19]), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_errman_cmt_hdr_buf_reg_rdata_18_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_cmt_hdr_buf_lutram_data[18]), + .Q(com_cmm_u_cmm_errman_cmt_rd_hdr[18]), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_errman_cmt_hdr_buf_reg_rdata_17_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_cmt_hdr_buf_lutram_data[17]), + .Q(com_cmm_u_cmm_errman_cmt_rd_hdr[17]), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_errman_cmt_hdr_buf_reg_rdata_16_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_cmt_hdr_buf_lutram_data[16]), + .Q(com_cmm_u_cmm_errman_cmt_rd_hdr[16]), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_errman_cmt_hdr_buf_reg_rdata_15_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_cmt_hdr_buf_lutram_data[15]), + .Q(com_cmm_u_cmm_errman_cmt_rd_hdr[15]), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_errman_cmt_hdr_buf_reg_rdata_14_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_cmt_hdr_buf_lutram_data[14]), + .Q(com_cmm_u_cmm_errman_cmt_rd_hdr[14]), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_errman_cmt_hdr_buf_reg_rdata_13_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_cmt_hdr_buf_lutram_data[13]), + .Q(com_cmm_u_cmm_errman_cmt_rd_hdr[13]), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_errman_cmt_hdr_buf_reg_rdata_12_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_cmt_hdr_buf_lutram_data[12]), + .Q(com_cmm_u_cmm_errman_cmt_rd_hdr[12]), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_errman_cmt_hdr_buf_reg_rdata_11_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_cmt_hdr_buf_lutram_data[11]), + .Q(com_cmm_u_cmm_errman_cmt_rd_hdr[11]), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_errman_cmt_hdr_buf_reg_rdata_10_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_cmt_hdr_buf_lutram_data[10]), + .Q(com_cmm_u_cmm_errman_cmt_rd_hdr[10]), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_errman_cmt_hdr_buf_reg_rdata_9_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_cmt_hdr_buf_lutram_data[9]), + .Q(com_cmm_u_cmm_errman_cmt_rd_hdr[9]), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_errman_cmt_hdr_buf_reg_rdata_38_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_cmt_hdr_buf_lutram_data[38]), + .Q(com_cmm_u_cmm_errman_cmt_rd_hdr[38]), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_errman_cmt_hdr_buf_reg_rdata_37_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_cmt_hdr_buf_lutram_data[37]), + .Q(com_cmm_u_cmm_errman_cmt_rd_hdr[37]), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_errman_cmt_hdr_buf_reg_rdata_36_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_cmt_hdr_buf_lutram_data[36]), + .Q(com_cmm_u_cmm_errman_cmt_rd_hdr[36]), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_errman_cmt_hdr_buf_reg_rdata_35_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_cmt_hdr_buf_lutram_data[35]), + .Q(com_cmm_u_cmm_errman_cmt_rd_hdr[35]), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_errman_cmt_hdr_buf_reg_rdata_34_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_cmt_hdr_buf_lutram_data[34]), + .Q(com_cmm_u_cmm_errman_cmt_rd_hdr[34]), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_errman_cmt_hdr_buf_reg_rdata_33_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_cmt_hdr_buf_lutram_data[33]), + .Q(com_cmm_u_cmm_errman_cmt_rd_hdr[33]), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_errman_cmt_hdr_buf_reg_rdata_32_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_cmt_hdr_buf_lutram_data[32]), + .Q(com_cmm_u_cmm_errman_cmt_rd_hdr[32]), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_errman_cmt_hdr_buf_reg_rdata_31_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_cmt_hdr_buf_lutram_data[31]), + .Q(com_cmm_u_cmm_errman_cmt_rd_hdr[31]), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_errman_cmt_hdr_buf_reg_rdata_30_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_cmt_hdr_buf_lutram_data[30]), + .Q(com_cmm_u_cmm_errman_cmt_rd_hdr[30]), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_errman_cmt_hdr_buf_reg_rdata_29_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_cmt_hdr_buf_lutram_data[29]), + .Q(com_cmm_u_cmm_errman_cmt_rd_hdr[29]), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_errman_cmt_hdr_buf_reg_rdata_28_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_cmt_hdr_buf_lutram_data[28]), + .Q(com_cmm_u_cmm_errman_cmt_rd_hdr[28]), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_errman_cmt_hdr_buf_reg_rdata_27_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_cmt_hdr_buf_lutram_data[27]), + .Q(com_cmm_u_cmm_errman_cmt_rd_hdr[27]), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_errman_cmt_hdr_buf_reg_rdata_26_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_cmt_hdr_buf_lutram_data[26]), + .Q(com_cmm_u_cmm_errman_cmt_rd_hdr[26]), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_errman_cmt_hdr_buf_reg_rdata_25_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_cmt_hdr_buf_lutram_data[25]), + .Q(com_cmm_u_cmm_errman_cmt_rd_hdr[25]), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_errman_cmt_hdr_buf_reg_rdata_24_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_cmt_hdr_buf_lutram_data[24]), + .Q(com_cmm_u_cmm_errman_cmt_rd_hdr[24]), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_errman_cmt_hdr_buf_reg_rdata_49_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_cmt_hdr_buf_lutram_data[49]), + .Q(com_cmm_u_cmm_errman_cmt_rd_hdr[49]), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_errman_cmt_hdr_buf_reg_rdata_48_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_cmt_hdr_buf_lutram_data[48]), + .Q(com_cmm_u_cmm_errman_cmt_rd_hdr[48]), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_errman_cmt_hdr_buf_reg_rdata_47_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_cmt_hdr_buf_lutram_data[47]), + .Q(com_cmm_u_cmm_errman_cmt_rd_hdr[47]), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_errman_cmt_hdr_buf_reg_rdata_46_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_cmt_hdr_buf_lutram_data[46]), + .Q(com_cmm_u_cmm_errman_cmt_rd_hdr[46]), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_errman_cmt_hdr_buf_reg_rdata_45_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_cmt_hdr_buf_lutram_data[45]), + .Q(com_cmm_u_cmm_errman_cmt_rd_hdr[45]), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_errman_cmt_hdr_buf_reg_rdata_44_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_cmt_hdr_buf_lutram_data[44]), + .Q(com_cmm_u_cmm_errman_cmt_rd_hdr[44]), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_errman_cmt_hdr_buf_reg_rdata_43_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_cmt_hdr_buf_lutram_data[43]), + .Q(com_cmm_u_cmm_errman_cmt_rd_hdr[43]), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_errman_cmt_hdr_buf_reg_rdata_42_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_cmt_hdr_buf_lutram_data[42]), + .Q(com_cmm_u_cmm_errman_cmt_rd_hdr[42]), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_errman_cmt_hdr_buf_reg_rdata_41_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_cmt_hdr_buf_lutram_data[41]), + .Q(com_cmm_u_cmm_errman_cmt_rd_hdr[41]), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_errman_cmt_hdr_buf_reg_rdata_40_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_cmt_hdr_buf_lutram_data[40]), + .Q(com_cmm_u_cmm_errman_cmt_rd_hdr[40]), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_errman_cmt_hdr_buf_reg_rdata_39_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_cmt_hdr_buf_lutram_data[39]), + .Q(com_cmm_u_cmm_errman_cmt_rd_hdr[39]), + .CLR(com_cmm_rst_267) + ); + GND com_cmm_u_cmm_errman_cfg_hdr_buf_GND ( + .G(com_cmm_u_cmm_errman_cfg_hdr_buf_GND_4969) + ); + RAM16X1D com_cmm_u_cmm_errman_cfg_hdr_buf_lutram_data_I_1 ( + .DPO(com_cmm_u_cmm_errman_cfg_hdr_buf_lutram_data[40]), + .WCLK(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_reg_cfg_wr_hdr[40]), + .A0(com_cmm_u_cmm_errman_reg_cfg_wp[0]), + .A1(com_cmm_u_cmm_errman_reg_cfg_wp[1]), + .A2(com_cmm_u_cmm_errman_cfg_hdr_buf_GND_4969), + .A3(com_cmm_u_cmm_errman_cfg_hdr_buf_GND_4969), + .DPRA0(com_cmm_u_cmm_errman_reg_cfg_rp[0]), + .DPRA1(com_cmm_u_cmm_errman_reg_cfg_rp[1]), + .DPRA2(com_cmm_u_cmm_errman_cfg_hdr_buf_GND_4969), + .DPRA3(com_cmm_u_cmm_errman_cfg_hdr_buf_GND_4969), + .SPO(NLW_com_cmm_u_cmm_errman_cfg_hdr_buf_lutram_data_I_1_SPO_UNCONNECTED), + .WE(com_cmm_u_cmm_errman_reg_incr_cplu_4809) + ); + RAM16X1D com_cmm_u_cmm_errman_cfg_hdr_buf_lutram_data_I_2 ( + .DPO(com_cmm_u_cmm_errman_cfg_hdr_buf_lutram_data[27]), + .WCLK(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_reg_cfg_wr_hdr[27]), + .A0(com_cmm_u_cmm_errman_reg_cfg_wp[0]), + .A1(com_cmm_u_cmm_errman_reg_cfg_wp[1]), + .A2(com_cmm_u_cmm_errman_cfg_hdr_buf_GND_4969), + .A3(com_cmm_u_cmm_errman_cfg_hdr_buf_GND_4969), + .DPRA0(com_cmm_u_cmm_errman_reg_cfg_rp[0]), + .DPRA1(com_cmm_u_cmm_errman_reg_cfg_rp[1]), + .DPRA2(com_cmm_u_cmm_errman_cfg_hdr_buf_GND_4969), + .DPRA3(com_cmm_u_cmm_errman_cfg_hdr_buf_GND_4969), + .SPO(NLW_com_cmm_u_cmm_errman_cfg_hdr_buf_lutram_data_I_2_SPO_UNCONNECTED), + .WE(com_cmm_u_cmm_errman_reg_incr_cplu_4809) + ); + RAM16X1D com_cmm_u_cmm_errman_cfg_hdr_buf_lutram_data_I_3 ( + .DPO(com_cmm_u_cmm_errman_cfg_hdr_buf_lutram_data[1]), + .WCLK(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_reg_cfg_wr_hdr[1]), + .A0(com_cmm_u_cmm_errman_reg_cfg_wp[0]), + .A1(com_cmm_u_cmm_errman_reg_cfg_wp[1]), + .A2(com_cmm_u_cmm_errman_cfg_hdr_buf_GND_4969), + .A3(com_cmm_u_cmm_errman_cfg_hdr_buf_GND_4969), + .DPRA0(com_cmm_u_cmm_errman_reg_cfg_rp[0]), + .DPRA1(com_cmm_u_cmm_errman_reg_cfg_rp[1]), + .DPRA2(com_cmm_u_cmm_errman_cfg_hdr_buf_GND_4969), + .DPRA3(com_cmm_u_cmm_errman_cfg_hdr_buf_GND_4969), + .SPO(NLW_com_cmm_u_cmm_errman_cfg_hdr_buf_lutram_data_I_3_SPO_UNCONNECTED), + .WE(com_cmm_u_cmm_errman_reg_incr_cplu_4809) + ); + RAM16X1D com_cmm_u_cmm_errman_cfg_hdr_buf_lutram_data_I_4 ( + .DPO(com_cmm_u_cmm_errman_cfg_hdr_buf_lutram_data[5]), + .WCLK(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_reg_cfg_wr_hdr[5]), + .A0(com_cmm_u_cmm_errman_reg_cfg_wp[0]), + .A1(com_cmm_u_cmm_errman_reg_cfg_wp[1]), + .A2(com_cmm_u_cmm_errman_cfg_hdr_buf_GND_4969), + .A3(com_cmm_u_cmm_errman_cfg_hdr_buf_GND_4969), + .DPRA0(com_cmm_u_cmm_errman_reg_cfg_rp[0]), + .DPRA1(com_cmm_u_cmm_errman_reg_cfg_rp[1]), + .DPRA2(com_cmm_u_cmm_errman_cfg_hdr_buf_GND_4969), + .DPRA3(com_cmm_u_cmm_errman_cfg_hdr_buf_GND_4969), + .SPO(NLW_com_cmm_u_cmm_errman_cfg_hdr_buf_lutram_data_I_4_SPO_UNCONNECTED), + .WE(com_cmm_u_cmm_errman_reg_incr_cplu_4809) + ); + RAM16X1D com_cmm_u_cmm_errman_cfg_hdr_buf_lutram_data_I_5 ( + .DPO(com_cmm_u_cmm_errman_cfg_hdr_buf_lutram_data[30]), + .WCLK(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_reg_cfg_wr_hdr[30]), + .A0(com_cmm_u_cmm_errman_reg_cfg_wp[0]), + .A1(com_cmm_u_cmm_errman_reg_cfg_wp[1]), + .A2(com_cmm_u_cmm_errman_cfg_hdr_buf_GND_4969), + .A3(com_cmm_u_cmm_errman_cfg_hdr_buf_GND_4969), + .DPRA0(com_cmm_u_cmm_errman_reg_cfg_rp[0]), + .DPRA1(com_cmm_u_cmm_errman_reg_cfg_rp[1]), + .DPRA2(com_cmm_u_cmm_errman_cfg_hdr_buf_GND_4969), + .DPRA3(com_cmm_u_cmm_errman_cfg_hdr_buf_GND_4969), + .SPO(NLW_com_cmm_u_cmm_errman_cfg_hdr_buf_lutram_data_I_5_SPO_UNCONNECTED), + .WE(com_cmm_u_cmm_errman_reg_incr_cplu_4809) + ); + RAM16X1D com_cmm_u_cmm_errman_cfg_hdr_buf_lutram_data_I_6 ( + .DPO(com_cmm_u_cmm_errman_cfg_hdr_buf_lutram_data[43]), + .WCLK(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_reg_cfg_wr_hdr[43]), + .A0(com_cmm_u_cmm_errman_reg_cfg_wp[0]), + .A1(com_cmm_u_cmm_errman_reg_cfg_wp[1]), + .A2(com_cmm_u_cmm_errman_cfg_hdr_buf_GND_4969), + .A3(com_cmm_u_cmm_errman_cfg_hdr_buf_GND_4969), + .DPRA0(com_cmm_u_cmm_errman_reg_cfg_rp[0]), + .DPRA1(com_cmm_u_cmm_errman_reg_cfg_rp[1]), + .DPRA2(com_cmm_u_cmm_errman_cfg_hdr_buf_GND_4969), + .DPRA3(com_cmm_u_cmm_errman_cfg_hdr_buf_GND_4969), + .SPO(NLW_com_cmm_u_cmm_errman_cfg_hdr_buf_lutram_data_I_6_SPO_UNCONNECTED), + .WE(com_cmm_u_cmm_errman_reg_incr_cplu_4809) + ); + RAM16X1D com_cmm_u_cmm_errman_cfg_hdr_buf_lutram_data_I_7 ( + .DPO(com_cmm_u_cmm_errman_cfg_hdr_buf_lutram_data[16]), + .WCLK(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_reg_cfg_wr_hdr[16]), + .A0(com_cmm_u_cmm_errman_reg_cfg_wp[0]), + .A1(com_cmm_u_cmm_errman_reg_cfg_wp[1]), + .A2(com_cmm_u_cmm_errman_cfg_hdr_buf_GND_4969), + .A3(com_cmm_u_cmm_errman_cfg_hdr_buf_GND_4969), + .DPRA0(com_cmm_u_cmm_errman_reg_cfg_rp[0]), + .DPRA1(com_cmm_u_cmm_errman_reg_cfg_rp[1]), + .DPRA2(com_cmm_u_cmm_errman_cfg_hdr_buf_GND_4969), + .DPRA3(com_cmm_u_cmm_errman_cfg_hdr_buf_GND_4969), + .SPO(NLW_com_cmm_u_cmm_errman_cfg_hdr_buf_lutram_data_I_7_SPO_UNCONNECTED), + .WE(com_cmm_u_cmm_errman_reg_incr_cplu_4809) + ); + RAM16X1D com_cmm_u_cmm_errman_cfg_hdr_buf_lutram_data_I_8 ( + .DPO(com_cmm_u_cmm_errman_cfg_hdr_buf_lutram_data[29]), + .WCLK(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_reg_cfg_wr_hdr[29]), + .A0(com_cmm_u_cmm_errman_reg_cfg_wp[0]), + .A1(com_cmm_u_cmm_errman_reg_cfg_wp[1]), + .A2(com_cmm_u_cmm_errman_cfg_hdr_buf_GND_4969), + .A3(com_cmm_u_cmm_errman_cfg_hdr_buf_GND_4969), + .DPRA0(com_cmm_u_cmm_errman_reg_cfg_rp[0]), + .DPRA1(com_cmm_u_cmm_errman_reg_cfg_rp[1]), + .DPRA2(com_cmm_u_cmm_errman_cfg_hdr_buf_GND_4969), + .DPRA3(com_cmm_u_cmm_errman_cfg_hdr_buf_GND_4969), + .SPO(NLW_com_cmm_u_cmm_errman_cfg_hdr_buf_lutram_data_I_8_SPO_UNCONNECTED), + .WE(com_cmm_u_cmm_errman_reg_incr_cplu_4809) + ); + RAM16X1D com_cmm_u_cmm_errman_cfg_hdr_buf_lutram_data_I_9 ( + .DPO(com_cmm_u_cmm_errman_cfg_hdr_buf_lutram_data[42]), + .WCLK(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_reg_cfg_wr_hdr[42]), + .A0(com_cmm_u_cmm_errman_reg_cfg_wp[0]), + .A1(com_cmm_u_cmm_errman_reg_cfg_wp[1]), + .A2(com_cmm_u_cmm_errman_cfg_hdr_buf_GND_4969), + .A3(com_cmm_u_cmm_errman_cfg_hdr_buf_GND_4969), + .DPRA0(com_cmm_u_cmm_errman_reg_cfg_rp[0]), + .DPRA1(com_cmm_u_cmm_errman_reg_cfg_rp[1]), + .DPRA2(com_cmm_u_cmm_errman_cfg_hdr_buf_GND_4969), + .DPRA3(com_cmm_u_cmm_errman_cfg_hdr_buf_GND_4969), + .SPO(NLW_com_cmm_u_cmm_errman_cfg_hdr_buf_lutram_data_I_9_SPO_UNCONNECTED), + .WE(com_cmm_u_cmm_errman_reg_incr_cplu_4809) + ); + RAM16X1D com_cmm_u_cmm_errman_cfg_hdr_buf_lutram_data_I_10 ( + .DPO(com_cmm_u_cmm_errman_cfg_hdr_buf_lutram_data[15]), + .WCLK(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_reg_cfg_wr_hdr[15]), + .A0(com_cmm_u_cmm_errman_reg_cfg_wp[0]), + .A1(com_cmm_u_cmm_errman_reg_cfg_wp[1]), + .A2(com_cmm_u_cmm_errman_cfg_hdr_buf_GND_4969), + .A3(com_cmm_u_cmm_errman_cfg_hdr_buf_GND_4969), + .DPRA0(com_cmm_u_cmm_errman_reg_cfg_rp[0]), + .DPRA1(com_cmm_u_cmm_errman_reg_cfg_rp[1]), + .DPRA2(com_cmm_u_cmm_errman_cfg_hdr_buf_GND_4969), + .DPRA3(com_cmm_u_cmm_errman_cfg_hdr_buf_GND_4969), + .SPO(NLW_com_cmm_u_cmm_errman_cfg_hdr_buf_lutram_data_I_10_SPO_UNCONNECTED), + .WE(com_cmm_u_cmm_errman_reg_incr_cplu_4809) + ); + RAM16X1D com_cmm_u_cmm_errman_cfg_hdr_buf_lutram_data_I_11 ( + .DPO(com_cmm_u_cmm_errman_cfg_hdr_buf_lutram_data[18]), + .WCLK(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_reg_cfg_wr_hdr[18]), + .A0(com_cmm_u_cmm_errman_reg_cfg_wp[0]), + .A1(com_cmm_u_cmm_errman_reg_cfg_wp[1]), + .A2(com_cmm_u_cmm_errman_cfg_hdr_buf_GND_4969), + .A3(com_cmm_u_cmm_errman_cfg_hdr_buf_GND_4969), + .DPRA0(com_cmm_u_cmm_errman_reg_cfg_rp[0]), + .DPRA1(com_cmm_u_cmm_errman_reg_cfg_rp[1]), + .DPRA2(com_cmm_u_cmm_errman_cfg_hdr_buf_GND_4969), + .DPRA3(com_cmm_u_cmm_errman_cfg_hdr_buf_GND_4969), + .SPO(NLW_com_cmm_u_cmm_errman_cfg_hdr_buf_lutram_data_I_11_SPO_UNCONNECTED), + .WE(com_cmm_u_cmm_errman_reg_incr_cplu_4809) + ); + RAM16X1D com_cmm_u_cmm_errman_cfg_hdr_buf_lutram_data_I_12 ( + .DPO(com_cmm_u_cmm_errman_cfg_hdr_buf_lutram_data[32]), + .WCLK(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_reg_cfg_wr_hdr[32]), + .A0(com_cmm_u_cmm_errman_reg_cfg_wp[0]), + .A1(com_cmm_u_cmm_errman_reg_cfg_wp[1]), + .A2(com_cmm_u_cmm_errman_cfg_hdr_buf_GND_4969), + .A3(com_cmm_u_cmm_errman_cfg_hdr_buf_GND_4969), + .DPRA0(com_cmm_u_cmm_errman_reg_cfg_rp[0]), + .DPRA1(com_cmm_u_cmm_errman_reg_cfg_rp[1]), + .DPRA2(com_cmm_u_cmm_errman_cfg_hdr_buf_GND_4969), + .DPRA3(com_cmm_u_cmm_errman_cfg_hdr_buf_GND_4969), + .SPO(NLW_com_cmm_u_cmm_errman_cfg_hdr_buf_lutram_data_I_12_SPO_UNCONNECTED), + .WE(com_cmm_u_cmm_errman_reg_incr_cplu_4809) + ); + RAM16X1D com_cmm_u_cmm_errman_cfg_hdr_buf_lutram_data_I_13 ( + .DPO(com_cmm_u_cmm_errman_cfg_hdr_buf_lutram_data[45]), + .WCLK(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_reg_cfg_wr_hdr[45]), + .A0(com_cmm_u_cmm_errman_reg_cfg_wp[0]), + .A1(com_cmm_u_cmm_errman_reg_cfg_wp[1]), + .A2(com_cmm_u_cmm_errman_cfg_hdr_buf_GND_4969), + .A3(com_cmm_u_cmm_errman_cfg_hdr_buf_GND_4969), + .DPRA0(com_cmm_u_cmm_errman_reg_cfg_rp[0]), + .DPRA1(com_cmm_u_cmm_errman_reg_cfg_rp[1]), + .DPRA2(com_cmm_u_cmm_errman_cfg_hdr_buf_GND_4969), + .DPRA3(com_cmm_u_cmm_errman_cfg_hdr_buf_GND_4969), + .SPO(NLW_com_cmm_u_cmm_errman_cfg_hdr_buf_lutram_data_I_13_SPO_UNCONNECTED), + .WE(com_cmm_u_cmm_errman_reg_incr_cplu_4809) + ); + RAM16X1D com_cmm_u_cmm_errman_cfg_hdr_buf_lutram_data_I_14 ( + .DPO(com_cmm_u_cmm_errman_cfg_hdr_buf_lutram_data[28]), + .WCLK(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_reg_cfg_wr_hdr[28]), + .A0(com_cmm_u_cmm_errman_reg_cfg_wp[0]), + .A1(com_cmm_u_cmm_errman_reg_cfg_wp[1]), + .A2(com_cmm_u_cmm_errman_cfg_hdr_buf_GND_4969), + .A3(com_cmm_u_cmm_errman_cfg_hdr_buf_GND_4969), + .DPRA0(com_cmm_u_cmm_errman_reg_cfg_rp[0]), + .DPRA1(com_cmm_u_cmm_errman_reg_cfg_rp[1]), + .DPRA2(com_cmm_u_cmm_errman_cfg_hdr_buf_GND_4969), + .DPRA3(com_cmm_u_cmm_errman_cfg_hdr_buf_GND_4969), + .SPO(NLW_com_cmm_u_cmm_errman_cfg_hdr_buf_lutram_data_I_14_SPO_UNCONNECTED), + .WE(com_cmm_u_cmm_errman_reg_incr_cplu_4809) + ); + RAM16X1D com_cmm_u_cmm_errman_cfg_hdr_buf_lutram_data_I_15 ( + .DPO(com_cmm_u_cmm_errman_cfg_hdr_buf_lutram_data[0]), + .WCLK(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_reg_cfg_wr_hdr[0]), + .A0(com_cmm_u_cmm_errman_reg_cfg_wp[0]), + .A1(com_cmm_u_cmm_errman_reg_cfg_wp[1]), + .A2(com_cmm_u_cmm_errman_cfg_hdr_buf_GND_4969), + .A3(com_cmm_u_cmm_errman_cfg_hdr_buf_GND_4969), + .DPRA0(com_cmm_u_cmm_errman_reg_cfg_rp[0]), + .DPRA1(com_cmm_u_cmm_errman_reg_cfg_rp[1]), + .DPRA2(com_cmm_u_cmm_errman_cfg_hdr_buf_GND_4969), + .DPRA3(com_cmm_u_cmm_errman_cfg_hdr_buf_GND_4969), + .SPO(NLW_com_cmm_u_cmm_errman_cfg_hdr_buf_lutram_data_I_15_SPO_UNCONNECTED), + .WE(com_cmm_u_cmm_errman_reg_incr_cplu_4809) + ); + RAM16X1D com_cmm_u_cmm_errman_cfg_hdr_buf_lutram_data_I_16 ( + .DPO(com_cmm_u_cmm_errman_cfg_hdr_buf_lutram_data[4]), + .WCLK(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_reg_cfg_wr_hdr[4]), + .A0(com_cmm_u_cmm_errman_reg_cfg_wp[0]), + .A1(com_cmm_u_cmm_errman_reg_cfg_wp[1]), + .A2(com_cmm_u_cmm_errman_cfg_hdr_buf_GND_4969), + .A3(com_cmm_u_cmm_errman_cfg_hdr_buf_GND_4969), + .DPRA0(com_cmm_u_cmm_errman_reg_cfg_rp[0]), + .DPRA1(com_cmm_u_cmm_errman_reg_cfg_rp[1]), + .DPRA2(com_cmm_u_cmm_errman_cfg_hdr_buf_GND_4969), + .DPRA3(com_cmm_u_cmm_errman_cfg_hdr_buf_GND_4969), + .SPO(NLW_com_cmm_u_cmm_errman_cfg_hdr_buf_lutram_data_I_16_SPO_UNCONNECTED), + .WE(com_cmm_u_cmm_errman_reg_incr_cplu_4809) + ); + RAM16X1D com_cmm_u_cmm_errman_cfg_hdr_buf_lutram_data_I_17 ( + .DPO(com_cmm_u_cmm_errman_cfg_hdr_buf_lutram_data[8]), + .WCLK(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_reg_cfg_wr_hdr[8]), + .A0(com_cmm_u_cmm_errman_reg_cfg_wp[0]), + .A1(com_cmm_u_cmm_errman_reg_cfg_wp[1]), + .A2(com_cmm_u_cmm_errman_cfg_hdr_buf_GND_4969), + .A3(com_cmm_u_cmm_errman_cfg_hdr_buf_GND_4969), + .DPRA0(com_cmm_u_cmm_errman_reg_cfg_rp[0]), + .DPRA1(com_cmm_u_cmm_errman_reg_cfg_rp[1]), + .DPRA2(com_cmm_u_cmm_errman_cfg_hdr_buf_GND_4969), + .DPRA3(com_cmm_u_cmm_errman_cfg_hdr_buf_GND_4969), + .SPO(NLW_com_cmm_u_cmm_errman_cfg_hdr_buf_lutram_data_I_17_SPO_UNCONNECTED), + .WE(com_cmm_u_cmm_errman_reg_incr_cplu_4809) + ); + RAM16X1D com_cmm_u_cmm_errman_cfg_hdr_buf_lutram_data_I_18 ( + .DPO(com_cmm_u_cmm_errman_cfg_hdr_buf_lutram_data[2]), + .WCLK(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_reg_cfg_wr_hdr[2]), + .A0(com_cmm_u_cmm_errman_reg_cfg_wp[0]), + .A1(com_cmm_u_cmm_errman_reg_cfg_wp[1]), + .A2(com_cmm_u_cmm_errman_cfg_hdr_buf_GND_4969), + .A3(com_cmm_u_cmm_errman_cfg_hdr_buf_GND_4969), + .DPRA0(com_cmm_u_cmm_errman_reg_cfg_rp[0]), + .DPRA1(com_cmm_u_cmm_errman_reg_cfg_rp[1]), + .DPRA2(com_cmm_u_cmm_errman_cfg_hdr_buf_GND_4969), + .DPRA3(com_cmm_u_cmm_errman_cfg_hdr_buf_GND_4969), + .SPO(NLW_com_cmm_u_cmm_errman_cfg_hdr_buf_lutram_data_I_18_SPO_UNCONNECTED), + .WE(com_cmm_u_cmm_errman_reg_incr_cplu_4809) + ); + RAM16X1D com_cmm_u_cmm_errman_cfg_hdr_buf_lutram_data_I_19 ( + .DPO(com_cmm_u_cmm_errman_cfg_hdr_buf_lutram_data[3]), + .WCLK(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_reg_cfg_wr_hdr[3]), + .A0(com_cmm_u_cmm_errman_reg_cfg_wp[0]), + .A1(com_cmm_u_cmm_errman_reg_cfg_wp[1]), + .A2(com_cmm_u_cmm_errman_cfg_hdr_buf_GND_4969), + .A3(com_cmm_u_cmm_errman_cfg_hdr_buf_GND_4969), + .DPRA0(com_cmm_u_cmm_errman_reg_cfg_rp[0]), + .DPRA1(com_cmm_u_cmm_errman_reg_cfg_rp[1]), + .DPRA2(com_cmm_u_cmm_errman_cfg_hdr_buf_GND_4969), + .DPRA3(com_cmm_u_cmm_errman_cfg_hdr_buf_GND_4969), + .SPO(NLW_com_cmm_u_cmm_errman_cfg_hdr_buf_lutram_data_I_19_SPO_UNCONNECTED), + .WE(com_cmm_u_cmm_errman_reg_incr_cplu_4809) + ); + RAM16X1D com_cmm_u_cmm_errman_cfg_hdr_buf_lutram_data_I_20 ( + .DPO(com_cmm_u_cmm_errman_cfg_hdr_buf_lutram_data[7]), + .WCLK(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_reg_cfg_wr_hdr[7]), + .A0(com_cmm_u_cmm_errman_reg_cfg_wp[0]), + .A1(com_cmm_u_cmm_errman_reg_cfg_wp[1]), + .A2(com_cmm_u_cmm_errman_cfg_hdr_buf_GND_4969), + .A3(com_cmm_u_cmm_errman_cfg_hdr_buf_GND_4969), + .DPRA0(com_cmm_u_cmm_errman_reg_cfg_rp[0]), + .DPRA1(com_cmm_u_cmm_errman_reg_cfg_rp[1]), + .DPRA2(com_cmm_u_cmm_errman_cfg_hdr_buf_GND_4969), + .DPRA3(com_cmm_u_cmm_errman_cfg_hdr_buf_GND_4969), + .SPO(NLW_com_cmm_u_cmm_errman_cfg_hdr_buf_lutram_data_I_20_SPO_UNCONNECTED), + .WE(com_cmm_u_cmm_errman_reg_incr_cplu_4809) + ); + RAM16X1D com_cmm_u_cmm_errman_cfg_hdr_buf_lutram_data_I_21 ( + .DPO(com_cmm_u_cmm_errman_cfg_hdr_buf_lutram_data[20]), + .WCLK(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_reg_cfg_wr_hdr[20]), + .A0(com_cmm_u_cmm_errman_reg_cfg_wp[0]), + .A1(com_cmm_u_cmm_errman_reg_cfg_wp[1]), + .A2(com_cmm_u_cmm_errman_cfg_hdr_buf_GND_4969), + .A3(com_cmm_u_cmm_errman_cfg_hdr_buf_GND_4969), + .DPRA0(com_cmm_u_cmm_errman_reg_cfg_rp[0]), + .DPRA1(com_cmm_u_cmm_errman_reg_cfg_rp[1]), + .DPRA2(com_cmm_u_cmm_errman_cfg_hdr_buf_GND_4969), + .DPRA3(com_cmm_u_cmm_errman_cfg_hdr_buf_GND_4969), + .SPO(NLW_com_cmm_u_cmm_errman_cfg_hdr_buf_lutram_data_I_21_SPO_UNCONNECTED), + .WE(com_cmm_u_cmm_errman_reg_incr_cplu_4809) + ); + RAM16X1D com_cmm_u_cmm_errman_cfg_hdr_buf_lutram_data_I_22 ( + .DPO(com_cmm_u_cmm_errman_cfg_hdr_buf_lutram_data[33]), + .WCLK(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_reg_cfg_wr_hdr[33]), + .A0(com_cmm_u_cmm_errman_reg_cfg_wp[0]), + .A1(com_cmm_u_cmm_errman_reg_cfg_wp[1]), + .A2(com_cmm_u_cmm_errman_cfg_hdr_buf_GND_4969), + .A3(com_cmm_u_cmm_errman_cfg_hdr_buf_GND_4969), + .DPRA0(com_cmm_u_cmm_errman_reg_cfg_rp[0]), + .DPRA1(com_cmm_u_cmm_errman_reg_cfg_rp[1]), + .DPRA2(com_cmm_u_cmm_errman_cfg_hdr_buf_GND_4969), + .DPRA3(com_cmm_u_cmm_errman_cfg_hdr_buf_GND_4969), + .SPO(NLW_com_cmm_u_cmm_errman_cfg_hdr_buf_lutram_data_I_22_SPO_UNCONNECTED), + .WE(com_cmm_u_cmm_errman_reg_incr_cplu_4809) + ); + RAM16X1D com_cmm_u_cmm_errman_cfg_hdr_buf_lutram_data_I_23 ( + .DPO(com_cmm_u_cmm_errman_cfg_hdr_buf_lutram_data[46]), + .WCLK(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_reg_cfg_wr_hdr[46]), + .A0(com_cmm_u_cmm_errman_reg_cfg_wp[0]), + .A1(com_cmm_u_cmm_errman_reg_cfg_wp[1]), + .A2(com_cmm_u_cmm_errman_cfg_hdr_buf_GND_4969), + .A3(com_cmm_u_cmm_errman_cfg_hdr_buf_GND_4969), + .DPRA0(com_cmm_u_cmm_errman_reg_cfg_rp[0]), + .DPRA1(com_cmm_u_cmm_errman_reg_cfg_rp[1]), + .DPRA2(com_cmm_u_cmm_errman_cfg_hdr_buf_GND_4969), + .DPRA3(com_cmm_u_cmm_errman_cfg_hdr_buf_GND_4969), + .SPO(NLW_com_cmm_u_cmm_errman_cfg_hdr_buf_lutram_data_I_23_SPO_UNCONNECTED), + .WE(com_cmm_u_cmm_errman_reg_incr_cplu_4809) + ); + RAM16X1D com_cmm_u_cmm_errman_cfg_hdr_buf_lutram_data_I_24 ( + .DPO(com_cmm_u_cmm_errman_cfg_hdr_buf_lutram_data[9]), + .WCLK(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_reg_cfg_wr_hdr[9]), + .A0(com_cmm_u_cmm_errman_reg_cfg_wp[0]), + .A1(com_cmm_u_cmm_errman_reg_cfg_wp[1]), + .A2(com_cmm_u_cmm_errman_cfg_hdr_buf_GND_4969), + .A3(com_cmm_u_cmm_errman_cfg_hdr_buf_GND_4969), + .DPRA0(com_cmm_u_cmm_errman_reg_cfg_rp[0]), + .DPRA1(com_cmm_u_cmm_errman_reg_cfg_rp[1]), + .DPRA2(com_cmm_u_cmm_errman_cfg_hdr_buf_GND_4969), + .DPRA3(com_cmm_u_cmm_errman_cfg_hdr_buf_GND_4969), + .SPO(NLW_com_cmm_u_cmm_errman_cfg_hdr_buf_lutram_data_I_24_SPO_UNCONNECTED), + .WE(com_cmm_u_cmm_errman_reg_incr_cplu_4809) + ); + RAM16X1D com_cmm_u_cmm_errman_cfg_hdr_buf_lutram_data_I_25 ( + .DPO(com_cmm_u_cmm_errman_cfg_hdr_buf_lutram_data[41]), + .WCLK(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_reg_cfg_wr_hdr[41]), + .A0(com_cmm_u_cmm_errman_reg_cfg_wp[0]), + .A1(com_cmm_u_cmm_errman_reg_cfg_wp[1]), + .A2(com_cmm_u_cmm_errman_cfg_hdr_buf_GND_4969), + .A3(com_cmm_u_cmm_errman_cfg_hdr_buf_GND_4969), + .DPRA0(com_cmm_u_cmm_errman_reg_cfg_rp[0]), + .DPRA1(com_cmm_u_cmm_errman_reg_cfg_rp[1]), + .DPRA2(com_cmm_u_cmm_errman_cfg_hdr_buf_GND_4969), + .DPRA3(com_cmm_u_cmm_errman_cfg_hdr_buf_GND_4969), + .SPO(NLW_com_cmm_u_cmm_errman_cfg_hdr_buf_lutram_data_I_25_SPO_UNCONNECTED), + .WE(com_cmm_u_cmm_errman_reg_incr_cplu_4809) + ); + RAM16X1D com_cmm_u_cmm_errman_cfg_hdr_buf_lutram_data_I_26 ( + .DPO(com_cmm_u_cmm_errman_cfg_hdr_buf_lutram_data[14]), + .WCLK(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_reg_cfg_wr_hdr[14]), + .A0(com_cmm_u_cmm_errman_reg_cfg_wp[0]), + .A1(com_cmm_u_cmm_errman_reg_cfg_wp[1]), + .A2(com_cmm_u_cmm_errman_cfg_hdr_buf_GND_4969), + .A3(com_cmm_u_cmm_errman_cfg_hdr_buf_GND_4969), + .DPRA0(com_cmm_u_cmm_errman_reg_cfg_rp[0]), + .DPRA1(com_cmm_u_cmm_errman_reg_cfg_rp[1]), + .DPRA2(com_cmm_u_cmm_errman_cfg_hdr_buf_GND_4969), + .DPRA3(com_cmm_u_cmm_errman_cfg_hdr_buf_GND_4969), + .SPO(NLW_com_cmm_u_cmm_errman_cfg_hdr_buf_lutram_data_I_26_SPO_UNCONNECTED), + .WE(com_cmm_u_cmm_errman_reg_incr_cplu_4809) + ); + RAM16X1D com_cmm_u_cmm_errman_cfg_hdr_buf_lutram_data_I_27 ( + .DPO(com_cmm_u_cmm_errman_cfg_hdr_buf_lutram_data[19]), + .WCLK(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_reg_cfg_wr_hdr[19]), + .A0(com_cmm_u_cmm_errman_reg_cfg_wp[0]), + .A1(com_cmm_u_cmm_errman_reg_cfg_wp[1]), + .A2(com_cmm_u_cmm_errman_cfg_hdr_buf_GND_4969), + .A3(com_cmm_u_cmm_errman_cfg_hdr_buf_GND_4969), + .DPRA0(com_cmm_u_cmm_errman_reg_cfg_rp[0]), + .DPRA1(com_cmm_u_cmm_errman_reg_cfg_rp[1]), + .DPRA2(com_cmm_u_cmm_errman_cfg_hdr_buf_GND_4969), + .DPRA3(com_cmm_u_cmm_errman_cfg_hdr_buf_GND_4969), + .SPO(NLW_com_cmm_u_cmm_errman_cfg_hdr_buf_lutram_data_I_27_SPO_UNCONNECTED), + .WE(com_cmm_u_cmm_errman_reg_incr_cplu_4809) + ); + RAM16X1D com_cmm_u_cmm_errman_cfg_hdr_buf_lutram_data_I_28 ( + .DPO(com_cmm_u_cmm_errman_cfg_hdr_buf_lutram_data[6]), + .WCLK(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_reg_cfg_wr_hdr[6]), + .A0(com_cmm_u_cmm_errman_reg_cfg_wp[0]), + .A1(com_cmm_u_cmm_errman_reg_cfg_wp[1]), + .A2(com_cmm_u_cmm_errman_cfg_hdr_buf_GND_4969), + .A3(com_cmm_u_cmm_errman_cfg_hdr_buf_GND_4969), + .DPRA0(com_cmm_u_cmm_errman_reg_cfg_rp[0]), + .DPRA1(com_cmm_u_cmm_errman_reg_cfg_rp[1]), + .DPRA2(com_cmm_u_cmm_errman_cfg_hdr_buf_GND_4969), + .DPRA3(com_cmm_u_cmm_errman_cfg_hdr_buf_GND_4969), + .SPO(NLW_com_cmm_u_cmm_errman_cfg_hdr_buf_lutram_data_I_28_SPO_UNCONNECTED), + .WE(com_cmm_u_cmm_errman_reg_incr_cplu_4809) + ); + RAM16X1D com_cmm_u_cmm_errman_cfg_hdr_buf_lutram_data_I_29 ( + .DPO(com_cmm_u_cmm_errman_cfg_hdr_buf_lutram_data[11]), + .WCLK(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_reg_cfg_wr_hdr[11]), + .A0(com_cmm_u_cmm_errman_reg_cfg_wp[0]), + .A1(com_cmm_u_cmm_errman_reg_cfg_wp[1]), + .A2(com_cmm_u_cmm_errman_cfg_hdr_buf_GND_4969), + .A3(com_cmm_u_cmm_errman_cfg_hdr_buf_GND_4969), + .DPRA0(com_cmm_u_cmm_errman_reg_cfg_rp[0]), + .DPRA1(com_cmm_u_cmm_errman_reg_cfg_rp[1]), + .DPRA2(com_cmm_u_cmm_errman_cfg_hdr_buf_GND_4969), + .DPRA3(com_cmm_u_cmm_errman_cfg_hdr_buf_GND_4969), + .SPO(NLW_com_cmm_u_cmm_errman_cfg_hdr_buf_lutram_data_I_29_SPO_UNCONNECTED), + .WE(com_cmm_u_cmm_errman_reg_incr_cplu_4809) + ); + RAM16X1D com_cmm_u_cmm_errman_cfg_hdr_buf_lutram_data_I_30 ( + .DPO(com_cmm_u_cmm_errman_cfg_hdr_buf_lutram_data[24]), + .WCLK(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_reg_cfg_wr_hdr[24]), + .A0(com_cmm_u_cmm_errman_reg_cfg_wp[0]), + .A1(com_cmm_u_cmm_errman_reg_cfg_wp[1]), + .A2(com_cmm_u_cmm_errman_cfg_hdr_buf_GND_4969), + .A3(com_cmm_u_cmm_errman_cfg_hdr_buf_GND_4969), + .DPRA0(com_cmm_u_cmm_errman_reg_cfg_rp[0]), + .DPRA1(com_cmm_u_cmm_errman_reg_cfg_rp[1]), + .DPRA2(com_cmm_u_cmm_errman_cfg_hdr_buf_GND_4969), + .DPRA3(com_cmm_u_cmm_errman_cfg_hdr_buf_GND_4969), + .SPO(NLW_com_cmm_u_cmm_errman_cfg_hdr_buf_lutram_data_I_30_SPO_UNCONNECTED), + .WE(com_cmm_u_cmm_errman_reg_incr_cplu_4809) + ); + RAM16X1D com_cmm_u_cmm_errman_cfg_hdr_buf_lutram_data_I_31 ( + .DPO(com_cmm_u_cmm_errman_cfg_hdr_buf_lutram_data[39]), + .WCLK(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_reg_cfg_wr_hdr[39]), + .A0(com_cmm_u_cmm_errman_reg_cfg_wp[0]), + .A1(com_cmm_u_cmm_errman_reg_cfg_wp[1]), + .A2(com_cmm_u_cmm_errman_cfg_hdr_buf_GND_4969), + .A3(com_cmm_u_cmm_errman_cfg_hdr_buf_GND_4969), + .DPRA0(com_cmm_u_cmm_errman_reg_cfg_rp[0]), + .DPRA1(com_cmm_u_cmm_errman_reg_cfg_rp[1]), + .DPRA2(com_cmm_u_cmm_errman_cfg_hdr_buf_GND_4969), + .DPRA3(com_cmm_u_cmm_errman_cfg_hdr_buf_GND_4969), + .SPO(NLW_com_cmm_u_cmm_errman_cfg_hdr_buf_lutram_data_I_31_SPO_UNCONNECTED), + .WE(com_cmm_u_cmm_errman_reg_incr_cplu_4809) + ); + RAM16X1D com_cmm_u_cmm_errman_cfg_hdr_buf_lutram_data_I_32 ( + .DPO(com_cmm_u_cmm_errman_cfg_hdr_buf_lutram_data[12]), + .WCLK(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_reg_cfg_wr_hdr[12]), + .A0(com_cmm_u_cmm_errman_reg_cfg_wp[0]), + .A1(com_cmm_u_cmm_errman_reg_cfg_wp[1]), + .A2(com_cmm_u_cmm_errman_cfg_hdr_buf_GND_4969), + .A3(com_cmm_u_cmm_errman_cfg_hdr_buf_GND_4969), + .DPRA0(com_cmm_u_cmm_errman_reg_cfg_rp[0]), + .DPRA1(com_cmm_u_cmm_errman_reg_cfg_rp[1]), + .DPRA2(com_cmm_u_cmm_errman_cfg_hdr_buf_GND_4969), + .DPRA3(com_cmm_u_cmm_errman_cfg_hdr_buf_GND_4969), + .SPO(NLW_com_cmm_u_cmm_errman_cfg_hdr_buf_lutram_data_I_32_SPO_UNCONNECTED), + .WE(com_cmm_u_cmm_errman_reg_incr_cplu_4809) + ); + RAM16X1D com_cmm_u_cmm_errman_cfg_hdr_buf_lutram_data_I_33 ( + .DPO(com_cmm_u_cmm_errman_cfg_hdr_buf_lutram_data[25]), + .WCLK(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_reg_cfg_wr_hdr[25]), + .A0(com_cmm_u_cmm_errman_reg_cfg_wp[0]), + .A1(com_cmm_u_cmm_errman_reg_cfg_wp[1]), + .A2(com_cmm_u_cmm_errman_cfg_hdr_buf_GND_4969), + .A3(com_cmm_u_cmm_errman_cfg_hdr_buf_GND_4969), + .DPRA0(com_cmm_u_cmm_errman_reg_cfg_rp[0]), + .DPRA1(com_cmm_u_cmm_errman_reg_cfg_rp[1]), + .DPRA2(com_cmm_u_cmm_errman_cfg_hdr_buf_GND_4969), + .DPRA3(com_cmm_u_cmm_errman_cfg_hdr_buf_GND_4969), + .SPO(NLW_com_cmm_u_cmm_errman_cfg_hdr_buf_lutram_data_I_33_SPO_UNCONNECTED), + .WE(com_cmm_u_cmm_errman_reg_incr_cplu_4809) + ); + RAM16X1D com_cmm_u_cmm_errman_cfg_hdr_buf_lutram_data_I_34 ( + .DPO(com_cmm_u_cmm_errman_cfg_hdr_buf_lutram_data[38]), + .WCLK(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_reg_cfg_wr_hdr[38]), + .A0(com_cmm_u_cmm_errman_reg_cfg_wp[0]), + .A1(com_cmm_u_cmm_errman_reg_cfg_wp[1]), + .A2(com_cmm_u_cmm_errman_cfg_hdr_buf_GND_4969), + .A3(com_cmm_u_cmm_errman_cfg_hdr_buf_GND_4969), + .DPRA0(com_cmm_u_cmm_errman_reg_cfg_rp[0]), + .DPRA1(com_cmm_u_cmm_errman_reg_cfg_rp[1]), + .DPRA2(com_cmm_u_cmm_errman_cfg_hdr_buf_GND_4969), + .DPRA3(com_cmm_u_cmm_errman_cfg_hdr_buf_GND_4969), + .SPO(NLW_com_cmm_u_cmm_errman_cfg_hdr_buf_lutram_data_I_34_SPO_UNCONNECTED), + .WE(com_cmm_u_cmm_errman_reg_incr_cplu_4809) + ); + RAM16X1D com_cmm_u_cmm_errman_cfg_hdr_buf_lutram_data_I_35 ( + .DPO(com_cmm_u_cmm_errman_cfg_hdr_buf_lutram_data[13]), + .WCLK(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_reg_cfg_wr_hdr[13]), + .A0(com_cmm_u_cmm_errman_reg_cfg_wp[0]), + .A1(com_cmm_u_cmm_errman_reg_cfg_wp[1]), + .A2(com_cmm_u_cmm_errman_cfg_hdr_buf_GND_4969), + .A3(com_cmm_u_cmm_errman_cfg_hdr_buf_GND_4969), + .DPRA0(com_cmm_u_cmm_errman_reg_cfg_rp[0]), + .DPRA1(com_cmm_u_cmm_errman_reg_cfg_rp[1]), + .DPRA2(com_cmm_u_cmm_errman_cfg_hdr_buf_GND_4969), + .DPRA3(com_cmm_u_cmm_errman_cfg_hdr_buf_GND_4969), + .SPO(NLW_com_cmm_u_cmm_errman_cfg_hdr_buf_lutram_data_I_35_SPO_UNCONNECTED), + .WE(com_cmm_u_cmm_errman_reg_incr_cplu_4809) + ); + RAM16X1D com_cmm_u_cmm_errman_cfg_hdr_buf_lutram_data_I_36 ( + .DPO(com_cmm_u_cmm_errman_cfg_hdr_buf_lutram_data[26]), + .WCLK(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_reg_cfg_wr_hdr[26]), + .A0(com_cmm_u_cmm_errman_reg_cfg_wp[0]), + .A1(com_cmm_u_cmm_errman_reg_cfg_wp[1]), + .A2(com_cmm_u_cmm_errman_cfg_hdr_buf_GND_4969), + .A3(com_cmm_u_cmm_errman_cfg_hdr_buf_GND_4969), + .DPRA0(com_cmm_u_cmm_errman_reg_cfg_rp[0]), + .DPRA1(com_cmm_u_cmm_errman_reg_cfg_rp[1]), + .DPRA2(com_cmm_u_cmm_errman_cfg_hdr_buf_GND_4969), + .DPRA3(com_cmm_u_cmm_errman_cfg_hdr_buf_GND_4969), + .SPO(NLW_com_cmm_u_cmm_errman_cfg_hdr_buf_lutram_data_I_36_SPO_UNCONNECTED), + .WE(com_cmm_u_cmm_errman_reg_incr_cplu_4809) + ); + RAM16X1D com_cmm_u_cmm_errman_cfg_hdr_buf_lutram_data_I_37 ( + .DPO(com_cmm_u_cmm_errman_cfg_hdr_buf_lutram_data[22]), + .WCLK(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_reg_cfg_wr_hdr[22]), + .A0(com_cmm_u_cmm_errman_reg_cfg_wp[0]), + .A1(com_cmm_u_cmm_errman_reg_cfg_wp[1]), + .A2(com_cmm_u_cmm_errman_cfg_hdr_buf_GND_4969), + .A3(com_cmm_u_cmm_errman_cfg_hdr_buf_GND_4969), + .DPRA0(com_cmm_u_cmm_errman_reg_cfg_rp[0]), + .DPRA1(com_cmm_u_cmm_errman_reg_cfg_rp[1]), + .DPRA2(com_cmm_u_cmm_errman_cfg_hdr_buf_GND_4969), + .DPRA3(com_cmm_u_cmm_errman_cfg_hdr_buf_GND_4969), + .SPO(NLW_com_cmm_u_cmm_errman_cfg_hdr_buf_lutram_data_I_37_SPO_UNCONNECTED), + .WE(com_cmm_u_cmm_errman_reg_incr_cplu_4809) + ); + RAM16X1D com_cmm_u_cmm_errman_cfg_hdr_buf_lutram_data_I_38 ( + .DPO(com_cmm_u_cmm_errman_cfg_hdr_buf_lutram_data[49]), + .WCLK(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_reg_cfg_wr_hdr[49]), + .A0(com_cmm_u_cmm_errman_reg_cfg_wp[0]), + .A1(com_cmm_u_cmm_errman_reg_cfg_wp[1]), + .A2(com_cmm_u_cmm_errman_cfg_hdr_buf_GND_4969), + .A3(com_cmm_u_cmm_errman_cfg_hdr_buf_GND_4969), + .DPRA0(com_cmm_u_cmm_errman_reg_cfg_rp[0]), + .DPRA1(com_cmm_u_cmm_errman_reg_cfg_rp[1]), + .DPRA2(com_cmm_u_cmm_errman_cfg_hdr_buf_GND_4969), + .DPRA3(com_cmm_u_cmm_errman_cfg_hdr_buf_GND_4969), + .SPO(NLW_com_cmm_u_cmm_errman_cfg_hdr_buf_lutram_data_I_38_SPO_UNCONNECTED), + .WE(com_cmm_u_cmm_errman_reg_incr_cplu_4809) + ); + RAM16X1D com_cmm_u_cmm_errman_cfg_hdr_buf_lutram_data_I_39 ( + .DPO(com_cmm_u_cmm_errman_cfg_hdr_buf_lutram_data[23]), + .WCLK(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_reg_cfg_wr_hdr[23]), + .A0(com_cmm_u_cmm_errman_reg_cfg_wp[0]), + .A1(com_cmm_u_cmm_errman_reg_cfg_wp[1]), + .A2(com_cmm_u_cmm_errman_cfg_hdr_buf_GND_4969), + .A3(com_cmm_u_cmm_errman_cfg_hdr_buf_GND_4969), + .DPRA0(com_cmm_u_cmm_errman_reg_cfg_rp[0]), + .DPRA1(com_cmm_u_cmm_errman_reg_cfg_rp[1]), + .DPRA2(com_cmm_u_cmm_errman_cfg_hdr_buf_GND_4969), + .DPRA3(com_cmm_u_cmm_errman_cfg_hdr_buf_GND_4969), + .SPO(NLW_com_cmm_u_cmm_errman_cfg_hdr_buf_lutram_data_I_39_SPO_UNCONNECTED), + .WE(com_cmm_u_cmm_errman_reg_incr_cplu_4809) + ); + RAM16X1D com_cmm_u_cmm_errman_cfg_hdr_buf_lutram_data_I_40 ( + .DPO(com_cmm_u_cmm_errman_cfg_hdr_buf_lutram_data[36]), + .WCLK(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_reg_cfg_wr_hdr[36]), + .A0(com_cmm_u_cmm_errman_reg_cfg_wp[0]), + .A1(com_cmm_u_cmm_errman_reg_cfg_wp[1]), + .A2(com_cmm_u_cmm_errman_cfg_hdr_buf_GND_4969), + .A3(com_cmm_u_cmm_errman_cfg_hdr_buf_GND_4969), + .DPRA0(com_cmm_u_cmm_errman_reg_cfg_rp[0]), + .DPRA1(com_cmm_u_cmm_errman_reg_cfg_rp[1]), + .DPRA2(com_cmm_u_cmm_errman_cfg_hdr_buf_GND_4969), + .DPRA3(com_cmm_u_cmm_errman_cfg_hdr_buf_GND_4969), + .SPO(NLW_com_cmm_u_cmm_errman_cfg_hdr_buf_lutram_data_I_40_SPO_UNCONNECTED), + .WE(com_cmm_u_cmm_errman_reg_incr_cplu_4809) + ); + RAM16X1D com_cmm_u_cmm_errman_cfg_hdr_buf_lutram_data_I_41 ( + .DPO(com_cmm_u_cmm_errman_cfg_hdr_buf_lutram_data[10]), + .WCLK(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_reg_cfg_wr_hdr[10]), + .A0(com_cmm_u_cmm_errman_reg_cfg_wp[0]), + .A1(com_cmm_u_cmm_errman_reg_cfg_wp[1]), + .A2(com_cmm_u_cmm_errman_cfg_hdr_buf_GND_4969), + .A3(com_cmm_u_cmm_errman_cfg_hdr_buf_GND_4969), + .DPRA0(com_cmm_u_cmm_errman_reg_cfg_rp[0]), + .DPRA1(com_cmm_u_cmm_errman_reg_cfg_rp[1]), + .DPRA2(com_cmm_u_cmm_errman_cfg_hdr_buf_GND_4969), + .DPRA3(com_cmm_u_cmm_errman_cfg_hdr_buf_GND_4969), + .SPO(NLW_com_cmm_u_cmm_errman_cfg_hdr_buf_lutram_data_I_41_SPO_UNCONNECTED), + .WE(com_cmm_u_cmm_errman_reg_incr_cplu_4809) + ); + RAM16X1D com_cmm_u_cmm_errman_cfg_hdr_buf_lutram_data_I_42 ( + .DPO(com_cmm_u_cmm_errman_cfg_hdr_buf_lutram_data[31]), + .WCLK(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_reg_cfg_wr_hdr[31]), + .A0(com_cmm_u_cmm_errman_reg_cfg_wp[0]), + .A1(com_cmm_u_cmm_errman_reg_cfg_wp[1]), + .A2(com_cmm_u_cmm_errman_cfg_hdr_buf_GND_4969), + .A3(com_cmm_u_cmm_errman_cfg_hdr_buf_GND_4969), + .DPRA0(com_cmm_u_cmm_errman_reg_cfg_rp[0]), + .DPRA1(com_cmm_u_cmm_errman_reg_cfg_rp[1]), + .DPRA2(com_cmm_u_cmm_errman_cfg_hdr_buf_GND_4969), + .DPRA3(com_cmm_u_cmm_errman_cfg_hdr_buf_GND_4969), + .SPO(NLW_com_cmm_u_cmm_errman_cfg_hdr_buf_lutram_data_I_42_SPO_UNCONNECTED), + .WE(com_cmm_u_cmm_errman_reg_incr_cplu_4809) + ); + RAM16X1D com_cmm_u_cmm_errman_cfg_hdr_buf_lutram_data_I_43 ( + .DPO(com_cmm_u_cmm_errman_cfg_hdr_buf_lutram_data[44]), + .WCLK(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_reg_cfg_wr_hdr[44]), + .A0(com_cmm_u_cmm_errman_reg_cfg_wp[0]), + .A1(com_cmm_u_cmm_errman_reg_cfg_wp[1]), + .A2(com_cmm_u_cmm_errman_cfg_hdr_buf_GND_4969), + .A3(com_cmm_u_cmm_errman_cfg_hdr_buf_GND_4969), + .DPRA0(com_cmm_u_cmm_errman_reg_cfg_rp[0]), + .DPRA1(com_cmm_u_cmm_errman_reg_cfg_rp[1]), + .DPRA2(com_cmm_u_cmm_errman_cfg_hdr_buf_GND_4969), + .DPRA3(com_cmm_u_cmm_errman_cfg_hdr_buf_GND_4969), + .SPO(NLW_com_cmm_u_cmm_errman_cfg_hdr_buf_lutram_data_I_43_SPO_UNCONNECTED), + .WE(com_cmm_u_cmm_errman_reg_incr_cplu_4809) + ); + RAM16X1D com_cmm_u_cmm_errman_cfg_hdr_buf_lutram_data_I_44 ( + .DPO(com_cmm_u_cmm_errman_cfg_hdr_buf_lutram_data[17]), + .WCLK(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_reg_cfg_wr_hdr[17]), + .A0(com_cmm_u_cmm_errman_reg_cfg_wp[0]), + .A1(com_cmm_u_cmm_errman_reg_cfg_wp[1]), + .A2(com_cmm_u_cmm_errman_cfg_hdr_buf_GND_4969), + .A3(com_cmm_u_cmm_errman_cfg_hdr_buf_GND_4969), + .DPRA0(com_cmm_u_cmm_errman_reg_cfg_rp[0]), + .DPRA1(com_cmm_u_cmm_errman_reg_cfg_rp[1]), + .DPRA2(com_cmm_u_cmm_errman_cfg_hdr_buf_GND_4969), + .DPRA3(com_cmm_u_cmm_errman_cfg_hdr_buf_GND_4969), + .SPO(NLW_com_cmm_u_cmm_errman_cfg_hdr_buf_lutram_data_I_44_SPO_UNCONNECTED), + .WE(com_cmm_u_cmm_errman_reg_incr_cplu_4809) + ); + RAM16X1D com_cmm_u_cmm_errman_cfg_hdr_buf_lutram_data_I_45 ( + .DPO(com_cmm_u_cmm_errman_cfg_hdr_buf_lutram_data[21]), + .WCLK(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_reg_cfg_wr_hdr[21]), + .A0(com_cmm_u_cmm_errman_reg_cfg_wp[0]), + .A1(com_cmm_u_cmm_errman_reg_cfg_wp[1]), + .A2(com_cmm_u_cmm_errman_cfg_hdr_buf_GND_4969), + .A3(com_cmm_u_cmm_errman_cfg_hdr_buf_GND_4969), + .DPRA0(com_cmm_u_cmm_errman_reg_cfg_rp[0]), + .DPRA1(com_cmm_u_cmm_errman_reg_cfg_rp[1]), + .DPRA2(com_cmm_u_cmm_errman_cfg_hdr_buf_GND_4969), + .DPRA3(com_cmm_u_cmm_errman_cfg_hdr_buf_GND_4969), + .SPO(NLW_com_cmm_u_cmm_errman_cfg_hdr_buf_lutram_data_I_45_SPO_UNCONNECTED), + .WE(com_cmm_u_cmm_errman_reg_incr_cplu_4809) + ); + RAM16X1D com_cmm_u_cmm_errman_cfg_hdr_buf_lutram_data_I_46 ( + .DPO(com_cmm_u_cmm_errman_cfg_hdr_buf_lutram_data[34]), + .WCLK(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_reg_cfg_wr_hdr[34]), + .A0(com_cmm_u_cmm_errman_reg_cfg_wp[0]), + .A1(com_cmm_u_cmm_errman_reg_cfg_wp[1]), + .A2(com_cmm_u_cmm_errman_cfg_hdr_buf_GND_4969), + .A3(com_cmm_u_cmm_errman_cfg_hdr_buf_GND_4969), + .DPRA0(com_cmm_u_cmm_errman_reg_cfg_rp[0]), + .DPRA1(com_cmm_u_cmm_errman_reg_cfg_rp[1]), + .DPRA2(com_cmm_u_cmm_errman_cfg_hdr_buf_GND_4969), + .DPRA3(com_cmm_u_cmm_errman_cfg_hdr_buf_GND_4969), + .SPO(NLW_com_cmm_u_cmm_errman_cfg_hdr_buf_lutram_data_I_46_SPO_UNCONNECTED), + .WE(com_cmm_u_cmm_errman_reg_incr_cplu_4809) + ); + RAM16X1D com_cmm_u_cmm_errman_cfg_hdr_buf_lutram_data_I_47 ( + .DPO(com_cmm_u_cmm_errman_cfg_hdr_buf_lutram_data[47]), + .WCLK(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_reg_cfg_wr_hdr[47]), + .A0(com_cmm_u_cmm_errman_reg_cfg_wp[0]), + .A1(com_cmm_u_cmm_errman_reg_cfg_wp[1]), + .A2(com_cmm_u_cmm_errman_cfg_hdr_buf_GND_4969), + .A3(com_cmm_u_cmm_errman_cfg_hdr_buf_GND_4969), + .DPRA0(com_cmm_u_cmm_errman_reg_cfg_rp[0]), + .DPRA1(com_cmm_u_cmm_errman_reg_cfg_rp[1]), + .DPRA2(com_cmm_u_cmm_errman_cfg_hdr_buf_GND_4969), + .DPRA3(com_cmm_u_cmm_errman_cfg_hdr_buf_GND_4969), + .SPO(NLW_com_cmm_u_cmm_errman_cfg_hdr_buf_lutram_data_I_47_SPO_UNCONNECTED), + .WE(com_cmm_u_cmm_errman_reg_incr_cplu_4809) + ); + RAM16X1D com_cmm_u_cmm_errman_cfg_hdr_buf_lutram_data_I_48 ( + .DPO(com_cmm_u_cmm_errman_cfg_hdr_buf_lutram_data[35]), + .WCLK(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_reg_cfg_wr_hdr[35]), + .A0(com_cmm_u_cmm_errman_reg_cfg_wp[0]), + .A1(com_cmm_u_cmm_errman_reg_cfg_wp[1]), + .A2(com_cmm_u_cmm_errman_cfg_hdr_buf_GND_4969), + .A3(com_cmm_u_cmm_errman_cfg_hdr_buf_GND_4969), + .DPRA0(com_cmm_u_cmm_errman_reg_cfg_rp[0]), + .DPRA1(com_cmm_u_cmm_errman_reg_cfg_rp[1]), + .DPRA2(com_cmm_u_cmm_errman_cfg_hdr_buf_GND_4969), + .DPRA3(com_cmm_u_cmm_errman_cfg_hdr_buf_GND_4969), + .SPO(NLW_com_cmm_u_cmm_errman_cfg_hdr_buf_lutram_data_I_48_SPO_UNCONNECTED), + .WE(com_cmm_u_cmm_errman_reg_incr_cplu_4809) + ); + RAM16X1D com_cmm_u_cmm_errman_cfg_hdr_buf_lutram_data_I_49 ( + .DPO(com_cmm_u_cmm_errman_cfg_hdr_buf_lutram_data[48]), + .WCLK(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_reg_cfg_wr_hdr[48]), + .A0(com_cmm_u_cmm_errman_reg_cfg_wp[0]), + .A1(com_cmm_u_cmm_errman_reg_cfg_wp[1]), + .A2(com_cmm_u_cmm_errman_cfg_hdr_buf_GND_4969), + .A3(com_cmm_u_cmm_errman_cfg_hdr_buf_GND_4969), + .DPRA0(com_cmm_u_cmm_errman_reg_cfg_rp[0]), + .DPRA1(com_cmm_u_cmm_errman_reg_cfg_rp[1]), + .DPRA2(com_cmm_u_cmm_errman_cfg_hdr_buf_GND_4969), + .DPRA3(com_cmm_u_cmm_errman_cfg_hdr_buf_GND_4969), + .SPO(NLW_com_cmm_u_cmm_errman_cfg_hdr_buf_lutram_data_I_49_SPO_UNCONNECTED), + .WE(com_cmm_u_cmm_errman_reg_incr_cplu_4809) + ); + RAM16X1D com_cmm_u_cmm_errman_cfg_hdr_buf_lutram_data_I_50 ( + .DPO(com_cmm_u_cmm_errman_cfg_hdr_buf_lutram_data[37]), + .WCLK(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_reg_cfg_wr_hdr[37]), + .A0(com_cmm_u_cmm_errman_reg_cfg_wp[0]), + .A1(com_cmm_u_cmm_errman_reg_cfg_wp[1]), + .A2(com_cmm_u_cmm_errman_cfg_hdr_buf_GND_4969), + .A3(com_cmm_u_cmm_errman_cfg_hdr_buf_GND_4969), + .DPRA0(com_cmm_u_cmm_errman_reg_cfg_rp[0]), + .DPRA1(com_cmm_u_cmm_errman_reg_cfg_rp[1]), + .DPRA2(com_cmm_u_cmm_errman_cfg_hdr_buf_GND_4969), + .DPRA3(com_cmm_u_cmm_errman_cfg_hdr_buf_GND_4969), + .SPO(NLW_com_cmm_u_cmm_errman_cfg_hdr_buf_lutram_data_I_50_SPO_UNCONNECTED), + .WE(com_cmm_u_cmm_errman_reg_incr_cplu_4809) + ); + FDC com_cmm_u_cmm_errman_cfg_hdr_buf_reg_rdata_3_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_cfg_hdr_buf_lutram_data[3]), + .Q(com_cmm_u_cmm_errman_cfg_rd_hdr[3]), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_errman_cfg_hdr_buf_reg_rdata_2_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_cfg_hdr_buf_lutram_data[2]), + .Q(com_cmm_u_cmm_errman_cfg_rd_hdr[2]), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_errman_cfg_hdr_buf_reg_rdata_1_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_cfg_hdr_buf_lutram_data[1]), + .Q(com_cmm_u_cmm_errman_cfg_rd_hdr[1]), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_errman_cfg_hdr_buf_reg_rdata_0_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_cfg_hdr_buf_lutram_data[0]), + .Q(com_cmm_u_cmm_errman_cfg_rd_hdr[0]), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_errman_cfg_hdr_buf_reg_rdata_18_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_cfg_hdr_buf_lutram_data[18]), + .Q(com_cmm_u_cmm_errman_cfg_rd_hdr[18]), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_errman_cfg_hdr_buf_reg_rdata_17_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_cfg_hdr_buf_lutram_data[17]), + .Q(com_cmm_u_cmm_errman_cfg_rd_hdr[17]), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_errman_cfg_hdr_buf_reg_rdata_16_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_cfg_hdr_buf_lutram_data[16]), + .Q(com_cmm_u_cmm_errman_cfg_rd_hdr[16]), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_errman_cfg_hdr_buf_reg_rdata_15_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_cfg_hdr_buf_lutram_data[15]), + .Q(com_cmm_u_cmm_errman_cfg_rd_hdr[15]), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_errman_cfg_hdr_buf_reg_rdata_14_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_cfg_hdr_buf_lutram_data[14]), + .Q(com_cmm_u_cmm_errman_cfg_rd_hdr[14]), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_errman_cfg_hdr_buf_reg_rdata_13_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_cfg_hdr_buf_lutram_data[13]), + .Q(com_cmm_u_cmm_errman_cfg_rd_hdr[13]), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_errman_cfg_hdr_buf_reg_rdata_12_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_cfg_hdr_buf_lutram_data[12]), + .Q(com_cmm_u_cmm_errman_cfg_rd_hdr[12]), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_errman_cfg_hdr_buf_reg_rdata_11_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_cfg_hdr_buf_lutram_data[11]), + .Q(com_cmm_u_cmm_errman_cfg_rd_hdr[11]), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_errman_cfg_hdr_buf_reg_rdata_10_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_cfg_hdr_buf_lutram_data[10]), + .Q(com_cmm_u_cmm_errman_cfg_rd_hdr[10]), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_errman_cfg_hdr_buf_reg_rdata_9_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_cfg_hdr_buf_lutram_data[9]), + .Q(com_cmm_u_cmm_errman_cfg_rd_hdr[9]), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_errman_cfg_hdr_buf_reg_rdata_8_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_cfg_hdr_buf_lutram_data[8]), + .Q(com_cmm_u_cmm_errman_cfg_rd_hdr[8]), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_errman_cfg_hdr_buf_reg_rdata_7_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_cfg_hdr_buf_lutram_data[7]), + .Q(com_cmm_u_cmm_errman_cfg_rd_hdr[7]), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_errman_cfg_hdr_buf_reg_rdata_6_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_cfg_hdr_buf_lutram_data[6]), + .Q(com_cmm_u_cmm_errman_cfg_rd_hdr[6]), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_errman_cfg_hdr_buf_reg_rdata_5_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_cfg_hdr_buf_lutram_data[5]), + .Q(com_cmm_u_cmm_errman_cfg_rd_hdr[5]), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_errman_cfg_hdr_buf_reg_rdata_4_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_cfg_hdr_buf_lutram_data[4]), + .Q(com_cmm_u_cmm_errman_cfg_rd_hdr[4]), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_errman_cfg_hdr_buf_reg_rdata_33_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_cfg_hdr_buf_lutram_data[33]), + .Q(com_cmm_u_cmm_errman_cfg_rd_hdr[33]), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_errman_cfg_hdr_buf_reg_rdata_32_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_cfg_hdr_buf_lutram_data[32]), + .Q(com_cmm_u_cmm_errman_cfg_rd_hdr[32]), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_errman_cfg_hdr_buf_reg_rdata_31_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_cfg_hdr_buf_lutram_data[31]), + .Q(com_cmm_u_cmm_errman_cfg_rd_hdr[31]), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_errman_cfg_hdr_buf_reg_rdata_30_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_cfg_hdr_buf_lutram_data[30]), + .Q(com_cmm_u_cmm_errman_cfg_rd_hdr[30]), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_errman_cfg_hdr_buf_reg_rdata_29_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_cfg_hdr_buf_lutram_data[29]), + .Q(com_cmm_u_cmm_errman_cfg_rd_hdr[29]), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_errman_cfg_hdr_buf_reg_rdata_28_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_cfg_hdr_buf_lutram_data[28]), + .Q(com_cmm_u_cmm_errman_cfg_rd_hdr[28]), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_errman_cfg_hdr_buf_reg_rdata_27_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_cfg_hdr_buf_lutram_data[27]), + .Q(com_cmm_u_cmm_errman_cfg_rd_hdr[27]), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_errman_cfg_hdr_buf_reg_rdata_26_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_cfg_hdr_buf_lutram_data[26]), + .Q(com_cmm_u_cmm_errman_cfg_rd_hdr[26]), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_errman_cfg_hdr_buf_reg_rdata_25_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_cfg_hdr_buf_lutram_data[25]), + .Q(com_cmm_u_cmm_errman_cfg_rd_hdr[25]), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_errman_cfg_hdr_buf_reg_rdata_24_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_cfg_hdr_buf_lutram_data[24]), + .Q(com_cmm_u_cmm_errman_cfg_rd_hdr[24]), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_errman_cfg_hdr_buf_reg_rdata_23_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_cfg_hdr_buf_lutram_data[23]), + .Q(com_cmm_u_cmm_errman_cfg_rd_hdr[23]), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_errman_cfg_hdr_buf_reg_rdata_22_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_cfg_hdr_buf_lutram_data[22]), + .Q(com_cmm_u_cmm_errman_cfg_rd_hdr[22]), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_errman_cfg_hdr_buf_reg_rdata_21_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_cfg_hdr_buf_lutram_data[21]), + .Q(com_cmm_u_cmm_errman_cfg_rd_hdr[21]), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_errman_cfg_hdr_buf_reg_rdata_20_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_cfg_hdr_buf_lutram_data[20]), + .Q(com_cmm_u_cmm_errman_cfg_rd_hdr[20]), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_errman_cfg_hdr_buf_reg_rdata_19_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_cfg_hdr_buf_lutram_data[19]), + .Q(com_cmm_u_cmm_errman_cfg_rd_hdr[19]), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_errman_cfg_hdr_buf_reg_rdata_48_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_cfg_hdr_buf_lutram_data[48]), + .Q(com_cmm_u_cmm_errman_cfg_rd_hdr[48]), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_errman_cfg_hdr_buf_reg_rdata_47_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_cfg_hdr_buf_lutram_data[47]), + .Q(com_cmm_u_cmm_errman_cfg_rd_hdr[47]), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_errman_cfg_hdr_buf_reg_rdata_46_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_cfg_hdr_buf_lutram_data[46]), + .Q(com_cmm_u_cmm_errman_cfg_rd_hdr[46]), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_errman_cfg_hdr_buf_reg_rdata_45_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_cfg_hdr_buf_lutram_data[45]), + .Q(com_cmm_u_cmm_errman_cfg_rd_hdr[45]), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_errman_cfg_hdr_buf_reg_rdata_44_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_cfg_hdr_buf_lutram_data[44]), + .Q(com_cmm_u_cmm_errman_cfg_rd_hdr[44]), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_errman_cfg_hdr_buf_reg_rdata_43_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_cfg_hdr_buf_lutram_data[43]), + .Q(com_cmm_u_cmm_errman_cfg_rd_hdr[43]), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_errman_cfg_hdr_buf_reg_rdata_42_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_cfg_hdr_buf_lutram_data[42]), + .Q(com_cmm_u_cmm_errman_cfg_rd_hdr[42]), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_errman_cfg_hdr_buf_reg_rdata_41_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_cfg_hdr_buf_lutram_data[41]), + .Q(com_cmm_u_cmm_errman_cfg_rd_hdr[41]), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_errman_cfg_hdr_buf_reg_rdata_40_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_cfg_hdr_buf_lutram_data[40]), + .Q(com_cmm_u_cmm_errman_cfg_rd_hdr[40]), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_errman_cfg_hdr_buf_reg_rdata_39_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_cfg_hdr_buf_lutram_data[39]), + .Q(com_cmm_u_cmm_errman_cfg_rd_hdr[39]), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_errman_cfg_hdr_buf_reg_rdata_38_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_cfg_hdr_buf_lutram_data[38]), + .Q(com_cmm_u_cmm_errman_cfg_rd_hdr[38]), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_errman_cfg_hdr_buf_reg_rdata_37_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_cfg_hdr_buf_lutram_data[37]), + .Q(com_cmm_u_cmm_errman_cfg_rd_hdr[37]), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_errman_cfg_hdr_buf_reg_rdata_36_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_cfg_hdr_buf_lutram_data[36]), + .Q(com_cmm_u_cmm_errman_cfg_rd_hdr[36]), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_errman_cfg_hdr_buf_reg_rdata_35_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_cfg_hdr_buf_lutram_data[35]), + .Q(com_cmm_u_cmm_errman_cfg_rd_hdr[35]), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_errman_cfg_hdr_buf_reg_rdata_34_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_cfg_hdr_buf_lutram_data[34]), + .Q(com_cmm_u_cmm_errman_cfg_rd_hdr[34]), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_errman_cfg_hdr_buf_reg_rdata_49_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_cfg_hdr_buf_lutram_data[49]), + .Q(com_cmm_u_cmm_errman_cfg_rd_hdr[49]), + .CLR(com_cmm_rst_267) + ); + VCC com_cmm_u_cmm_pm_VCC ( + .P(com_cmm_u_cmm_pm_VCC_4995) + ); + GND com_cmm_u_cmm_pm_GND ( + .G(com_cmm_u_cmm_pm_GND_4970) + ); + MUXCY_L com_cmm_u_cmm_pm_inactivity_timer_cry_0_ ( + .CI(com_cmm_u_cmm_pm_inactivity_timer24), + .DI(com_cmm_u_cmm_pm_GND_4970), + .LO(com_cmm_u_cmm_pm_inactivity_timer_cry[0]), + .S(com_cmm_u_cmm_pm_inactivity_timer_qxu[0]) + ); + XORCY com_cmm_u_cmm_pm_inactivity_timer_s_0_ ( + .CI(com_cmm_u_cmm_pm_inactivity_timer24), + .LI(com_cmm_u_cmm_pm_inactivity_timer_qxu[0]), + .O(com_cmm_u_cmm_pm_inactivity_timer_s[0]) + ); + MUXCY_L com_cmm_u_cmm_pm_inactivity_timer_cry_1_ ( + .CI(com_cmm_u_cmm_pm_inactivity_timer_cry[0]), + .DI(com_cmm_u_cmm_pm_GND_4970), + .LO(com_cmm_u_cmm_pm_inactivity_timer_cry[1]), + .S(com_cmm_u_cmm_pm_inactivity_timer_qxu[1]) + ); + XORCY com_cmm_u_cmm_pm_inactivity_timer_s_1_ ( + .CI(com_cmm_u_cmm_pm_inactivity_timer_cry[0]), + .LI(com_cmm_u_cmm_pm_inactivity_timer_qxu[1]), + .O(com_cmm_u_cmm_pm_inactivity_timer_s[1]) + ); + MUXCY_L com_cmm_u_cmm_pm_inactivity_timer_cry_2_ ( + .CI(com_cmm_u_cmm_pm_inactivity_timer_cry[1]), + .DI(com_cmm_u_cmm_pm_GND_4970), + .LO(com_cmm_u_cmm_pm_inactivity_timer_cry[2]), + .S(com_cmm_u_cmm_pm_inactivity_timer_qxu[2]) + ); + XORCY com_cmm_u_cmm_pm_inactivity_timer_s_2_ ( + .CI(com_cmm_u_cmm_pm_inactivity_timer_cry[1]), + .LI(com_cmm_u_cmm_pm_inactivity_timer_qxu[2]), + .O(com_cmm_u_cmm_pm_inactivity_timer_s[2]) + ); + MUXCY_L com_cmm_u_cmm_pm_inactivity_timer_cry_3_ ( + .CI(com_cmm_u_cmm_pm_inactivity_timer_cry[2]), + .DI(com_cmm_u_cmm_pm_GND_4970), + .LO(com_cmm_u_cmm_pm_inactivity_timer_cry[3]), + .S(com_cmm_u_cmm_pm_inactivity_timer_qxu[3]) + ); + XORCY com_cmm_u_cmm_pm_inactivity_timer_s_3_ ( + .CI(com_cmm_u_cmm_pm_inactivity_timer_cry[2]), + .LI(com_cmm_u_cmm_pm_inactivity_timer_qxu[3]), + .O(com_cmm_u_cmm_pm_inactivity_timer_s[3]) + ); + MUXCY_L com_cmm_u_cmm_pm_inactivity_timer_cry_4_ ( + .CI(com_cmm_u_cmm_pm_inactivity_timer_cry[3]), + .DI(com_cmm_u_cmm_pm_GND_4970), + .LO(com_cmm_u_cmm_pm_inactivity_timer_cry[4]), + .S(com_cmm_u_cmm_pm_inactivity_timer_qxu[4]) + ); + XORCY com_cmm_u_cmm_pm_inactivity_timer_s_4_ ( + .CI(com_cmm_u_cmm_pm_inactivity_timer_cry[3]), + .LI(com_cmm_u_cmm_pm_inactivity_timer_qxu[4]), + .O(com_cmm_u_cmm_pm_inactivity_timer_s[4]) + ); + MUXCY_L com_cmm_u_cmm_pm_inactivity_timer_cry_5_ ( + .CI(com_cmm_u_cmm_pm_inactivity_timer_cry[4]), + .DI(com_cmm_u_cmm_pm_GND_4970), + .LO(com_cmm_u_cmm_pm_inactivity_timer_cry[5]), + .S(com_cmm_u_cmm_pm_inactivity_timer_qxu[5]) + ); + XORCY com_cmm_u_cmm_pm_inactivity_timer_s_5_ ( + .CI(com_cmm_u_cmm_pm_inactivity_timer_cry[4]), + .LI(com_cmm_u_cmm_pm_inactivity_timer_qxu[5]), + .O(com_cmm_u_cmm_pm_inactivity_timer_s[5]) + ); + MUXCY_L com_cmm_u_cmm_pm_inactivity_timer_cry_6_ ( + .CI(com_cmm_u_cmm_pm_inactivity_timer_cry[5]), + .DI(com_cmm_u_cmm_pm_GND_4970), + .LO(com_cmm_u_cmm_pm_inactivity_timer_cry[6]), + .S(com_cmm_u_cmm_pm_inactivity_timer_qxu[6]) + ); + XORCY com_cmm_u_cmm_pm_inactivity_timer_s_6_ ( + .CI(com_cmm_u_cmm_pm_inactivity_timer_cry[5]), + .LI(com_cmm_u_cmm_pm_inactivity_timer_qxu[6]), + .O(com_cmm_u_cmm_pm_inactivity_timer_s[6]) + ); + MUXCY_L com_cmm_u_cmm_pm_inactivity_timer_cry_7_ ( + .CI(com_cmm_u_cmm_pm_inactivity_timer_cry[6]), + .DI(com_cmm_u_cmm_pm_GND_4970), + .LO(com_cmm_u_cmm_pm_inactivity_timer_cry[7]), + .S(com_cmm_u_cmm_pm_inactivity_timer_qxu[7]) + ); + XORCY com_cmm_u_cmm_pm_inactivity_timer_s_7_ ( + .CI(com_cmm_u_cmm_pm_inactivity_timer_cry[6]), + .LI(com_cmm_u_cmm_pm_inactivity_timer_qxu[7]), + .O(com_cmm_u_cmm_pm_inactivity_timer_s[7]) + ); + XORCY com_cmm_u_cmm_pm_inactivity_timer_s_8_ ( + .CI(com_cmm_u_cmm_pm_inactivity_timer_cry[7]), + .LI(com_cmm_u_cmm_pm_inactivity_timer_qxu[8]), + .O(com_cmm_u_cmm_pm_inactivity_timer_s[8]) + ); + defparam com_cmm_u_cmm_pm_st_pm_next_0_0_0_iv_1_i_0_0_a2_19_.INIT = 4'h8; + LUT2 com_cmm_u_cmm_pm_st_pm_next_0_0_0_iv_1_i_0_0_a2_19_ ( + .I0(com_cmm_u_cmm_pm_st_pm_18__4998), + .I1(com_cmml_suspend_ok), + .O(com_cmm_u_cmm_pm_N_42575) + ); + defparam com_cmm_u_cmm_pm_st_pm_next_0_0_0_iv_1_i_0_a2_14_.INIT = 4'h8; + LUT2 com_cmm_u_cmm_pm_st_pm_next_0_0_0_iv_1_i_0_a2_14_ ( + .I0(com_st_pm[13]), + .I1(com_cmml_rpm_ra), + .O(com_cmm_u_cmm_pm_N_42882) + ); + defparam com_cmm_u_cmm_pm_un1_cmml_suspend_now_n21_i_0_0_a2_1.INIT = 4'h8; + LUT2 com_cmm_u_cmm_pm_un1_cmml_suspend_now_n21_i_0_0_a2_1 ( + .I0(com_cmm_u_cmm_pm_inactivity_timer[8]), + .I1(com_cmm_u_cmm_pm_st_pm_24__4991), + .O(com_cmm_u_cmm_pm_N_42574) + ); + defparam com_cmm_u_cmm_pm_inactivity_timer24_0_a2_0_a2_0_a2.INIT = 4'h4; + LUT2 com_cmm_u_cmm_pm_inactivity_timer24_0_a2_0_a2_0_a2 ( + .I0(com_cmm_u_cmm_pm_inactivity_timer[8]), + .I1(com_cmm_u_cmm_pm_st_pm_24__4991), + .O(com_cmm_u_cmm_pm_inactivity_timer24) + ); + defparam com_cmm_u_cmm_pm_un1_cmml_suspend_now_n21_i_0_0_o4_0.INIT = 4'h2; + LUT2 com_cmm_u_cmm_pm_un1_cmml_suspend_now_n21_i_0_0_o4_0 ( + .I0(com_cmm_cmm_arb_pend_req_n), + .I1(com_cmmt_rpm_turn_off), + .O(com_cmm_u_cmm_pm_N_41807_i) + ); + defparam com_cmm_u_cmm_pm_st_pm_next_0_0_0_iv_i_0_0_0_o3_30_.INIT = 4'h1; + LUT2 com_cmm_u_cmm_pm_st_pm_next_0_0_0_iv_i_0_0_0_o3_30_ ( + .I0(com_cmm_u_cmm_pm_st_pm_24__4991), + .I1(com_cmm_u_cmm_pm_st_pm_28__4984), + .O(com_cmm_u_cmm_pm_N_48910_i) + ); + defparam com_cmm_u_cmm_pm_un1_cmmt_ppm_suspend_req_n_comb_0_sqmuxa_i_0_o4.INIT = 4'h1; + LUT2 com_cmm_u_cmm_pm_un1_cmmt_ppm_suspend_req_n_comb_0_sqmuxa_i_0_o4 ( + .I0(com_cmm_u_cmm_pm_cfg_pcie_link_state[0]), + .I1(com_cmm_u_cmm_pm_enable_cmm_tx[1]), + .O(com_cmm_u_cmm_pm_N_41785_i) + ); + defparam com_cmm_u_cmm_pm_un1_cmml_suspend_now_n21_i_0_0_o4.INIT = 4'h1; + LUT2 com_cmm_u_cmm_pm_un1_cmml_suspend_now_n21_i_0_0_o4 ( + .I0(com_cmm_u_cmm_pm_st_pm_17__5000), + .I1(com_cmm_u_cmm_pm_st_pm_27__4986), + .O(com_N_41769_i) + ); + defparam com_cmm_u_cmm_pm_pme_sent13_0_a2_0_a2_0_a2.INIT = 4'h8; + LUT2 com_cmm_u_cmm_pm_pme_sent13_0_a2_0_a2_0_a2 ( + .I0(com_cmm_gnt_pm), + .I1(com_cmm_pme_ack_bar), + .O(com_cmm_u_cmm_pm_pme_sent13) + ); + defparam com_cmm_u_cmm_pm_st_pm_next86_0_o2_i_a2_0_o3.INIT = 4'h2; + LUT2 com_cmm_u_cmm_pm_st_pm_next86_0_o2_i_a2_0_o3 ( + .I0(cfg_cfg_5072[523]), + .I1(cfg_pm_wake_n), + .O(com_cmm_u_cmm_pm_N_48889_i) + ); + defparam com_cmm_u_cmm_pm_st_pm_next_0_0_0_iv_i_i_i_a2_21_.INIT = 4'h8; + LUT2 com_cmm_u_cmm_pm_st_pm_next_0_0_0_iv_i_i_i_a2_21_ ( + .I0(com_cmm_u_cmm_pm_N_48889_i), + .I1(com_cmm_u_cmm_pm_enable_cmm_tx[1]), + .O(com_cmm_u_cmm_pm_N_50013) + ); + defparam com_cmm_u_cmm_pm_st_pm_next_0_0_0_iv_0_a2_i_0_a2_1_.INIT = 8'h20; + LUT3 com_cmm_u_cmm_pm_st_pm_next_0_0_0_iv_0_a2_i_0_a2_1_ ( + .I0(com_st_pm[13]), + .I1(com_cmml_rpm_ra), + .I2(com_cmmt_rpm_as_nak_l1), + .O(com_cmm_u_cmm_pm_N_42886) + ); + defparam com_cmm_u_cmm_pm_st_pm_next_0_0_0_iv_1_i_0_0_a2_3_9_.INIT = 16'h8000; + LUT4 com_cmm_u_cmm_pm_st_pm_next_0_0_0_iv_1_i_0_0_a2_3_9_ ( + .I0(com_cmm_cmm_arb_pend_req_n), + .I1(com_cmm_u_cmm_pm_enable_cmm_tx[1]), + .I2(com_cmml_suspend_ok), + .I3(com_cmmt_aspm_suspend_req), + .O(com_cmm_u_cmm_pm_N_49797_3) + ); + defparam com_cmm_u_cmm_pm_un936_st_pm_next_m_0_a2_0_a2_0_a2_0_a2_6_0_.INIT = 16'h0001; + LUT4_L com_cmm_u_cmm_pm_un936_st_pm_next_m_0_a2_0_a2_0_a2_0_a2_6_0_ ( + .I0(com_cmm_u_cmm_pm_st_pm_8__4980), + .I1(com_cmm_u_cmm_pm_st_pm_16__4977), + .I2(com_cmm_u_cmm_pm_st_pm_19__4996), + .I3(com_cmm_u_cmm_pm_st_pm_23__4992), + .LO(com_cmm_u_cmm_pm_un936_st_pm_next_m_0_a2_0_a2_0_a2_0_a2_6[0]) + ); + defparam com_cmm_u_cmm_pm_un936_st_pm_next_m_0_a2_0_a2_0_a2_0_a2_7_0_.INIT = 16'h0001; + LUT4 com_cmm_u_cmm_pm_un936_st_pm_next_m_0_a2_0_a2_0_a2_0_a2_7_0_ ( + .I0(com_cmm_u_cmm_pm_st_pm_0__4975), + .I1(com_cmm_u_cmm_pm_st_pm_6__4982), + .I2(com_cmm_u_cmm_pm_st_pm_18__4998), + .I3(com_cmm_u_cmm_pm_st_pm_30__5005), + .O(com_cmm_u_cmm_pm_un936_st_pm_next_m_0_a2_0_a2_0_a2_0_a2_7[0]) + ); + defparam com_cmm_u_cmm_pm_un936_st_pm_next_m_0_a2_0_a2_0_a2_0_a2_9_0_.INIT = 16'h0100; + LUT4_L com_cmm_u_cmm_pm_un936_st_pm_next_m_0_a2_0_a2_0_a2_0_a2_9_0_ ( + .I0(com_cmm_u_cmm_pm_st_pm_10__4979), + .I1(com_cmm_u_cmm_pm_st_pm_14__4978), + .I2(com_cmm_u_cmm_pm_st_pm_21__4994), + .I3(com_cmm_u_cmm_pm_un936_st_pm_next_m_0_a2_0_a2_0_a2_0_a2_6[0]), + .LO(com_cmm_u_cmm_pm_un936_st_pm_next_m_0_a2_0_a2_0_a2_0_a2_9[0]) + ); + defparam com_cmm_u_cmm_pm_un1_cmmt_ppm_suspend_req_n_comb_0_sqmuxa_i_0_0.INIT = 16'h1357; + LUT4_L com_cmm_u_cmm_pm_un1_cmmt_ppm_suspend_req_n_comb_0_sqmuxa_i_0_0 ( + .I0(com_cmm_u_cmm_pm_N_48889_i), + .I1(com_cmm_u_cmm_pm_cfg_pcie_link_state[0]), + .I2(com_cmm_u_cmm_pm_enable_cmm_tx[1]), + .I3(com_cmmt_rpm_turn_off), + .LO(com_cmm_u_cmm_pm_un1_cmmt_ppm_suspend_req_n_comb_0_sqmuxa_i_0_0_4971) + ); + defparam com_cmm_u_cmm_pm_st_pm_next_0_0_0_iv_0_a2_i_0_0_1_.INIT = 16'h070F; + LUT4 com_cmm_u_cmm_pm_st_pm_next_0_0_0_iv_0_a2_i_0_0_1_ ( + .I0(com_cmm_cmm_arb_pend_req_n), + .I1(com_cmm_u_cmm_pm_dev_power_state_eq_d0), + .I2(com_cmm_u_cmm_pm_st_pm_0__4975), + .I3(com_cmm_u_cmm_pm_st_pm_25__4989), + .O(com_cmm_u_cmm_pm_st_pm_next_0_0_0_iv_0_a2_i_0_0[1]) + ); + defparam com_cmm_u_cmm_pm_un936_st_pm_next_m_0_a2_0_a2_0_a2_0_a2_12_0_.INIT = 16'h8000; + LUT4 com_cmm_u_cmm_pm_un936_st_pm_next_m_0_a2_0_a2_0_a2_0_a2_12_0_ ( + .I0(com_cmm_u_cmm_pm_N_41785_i), + .I1(com_cmm_N_48915_i), + .I2(com_cmm_u_cmm_pm_un936_st_pm_next_m_0_a2_0_a2_0_a2_0_a2_7[0]), + .I3(com_cmm_u_cmm_pm_un936_st_pm_next_m_0_a2_0_a2_0_a2_0_a2_9[0]), + .O(com_cmm_u_cmm_pm_un936_st_pm_next_m_0_a2_0_a2_0_a2_0_a2_12[0]) + ); + defparam com_cmm_u_cmm_pm_st_pm_next_0_0_0_iv_0_a2_i_0_2_1_.INIT = 16'h1500; + LUT4 com_cmm_u_cmm_pm_st_pm_next_0_0_0_iv_0_a2_i_0_2_1_ ( + .I0(com_cmm_u_cmm_pm_N_42886), + .I1(com_cmm_u_cmm_pm_dev_power_state_eq_d0), + .I2(com_cmm_u_cmm_pm_pme_sent13), + .I3(com_cmm_u_cmm_pm_st_pm_next_0_0_0_iv_0_a2_i_0_0[1]), + .O(com_cmm_u_cmm_pm_st_pm_next_0_0_0_iv_0_a2_i_0_2[1]) + ); + defparam com_cmm_u_cmm_pm_N_68005_i.INIT = 16'hFCFD; + LUT4 com_cmm_u_cmm_pm_N_68005_i ( + .I0(com_cmm_u_cmm_pm_N_41807_i), + .I1(com_cmm_u_cmm_pm_un1_cmml_suspend_now_n21_i_0_0_a2_0_4973), + .I2(com_cmm_u_cmm_pm_N_42574), + .I3(com_cmm_u_cmm_pm_N_48910_i), + .O(com_cmm_u_cmm_pm_N_68005_i_5002) + ); + defparam com_cmm_u_cmm_pm_N_42917_i.INIT = 8'hFD; + LUT3_L com_cmm_u_cmm_pm_N_42917_i ( + .I0(com_cmm_N_48915_i), + .I1(com_cmm_u_cmm_pm_cfg_pcie_link_state[0]), + .I2(com_cmm_u_cmm_pm_st_pm_24__4991), + .LO(com_cmm_N_42917_i) + ); + defparam com_cmm_u_cmm_pm_N_68083_i.INIT = 16'h0F4F; + LUT4_L com_cmm_u_cmm_pm_N_68083_i ( + .I0(com_cmm_u_cmm_pm_N_48889_i), + .I1(com_cmm_u_cmm_pm_cfg_pcie_link_state[0]), + .I2(com_cmm_u_cmm_pm_st_pm_next_0_0_0_iv_0_a2_i_0_2[1]), + .I3(com_cmmt_rpm_turn_off), + .LO(com_cmm_u_cmm_pm_N_68083_i_4974) + ); + defparam com_cmm_u_cmm_pm_un936_st_pm_next_m_0_a2_0_a2_0_a2_0_a2_0_.INIT = 16'h0800; + LUT4_L com_cmm_u_cmm_pm_un936_st_pm_next_m_0_a2_0_a2_0_a2_0_a2_0_ ( + .I0(com_N_42763), + .I1(com_cmm_u_cmm_pm_N_48910_i), + .I2(com_cmm_u_cmm_pm_st_pm_25__4989), + .I3(com_cmm_u_cmm_pm_un936_st_pm_next_m_0_a2_0_a2_0_a2_0_a2_12[0]), + .LO(com_cmm_u_cmm_pm_st_pm_next[0]) + ); + defparam com_cmm_u_cmm_pm_N_68956_i.INIT = 16'h8F88; + LUT4_L com_cmm_u_cmm_pm_N_68956_i ( + .I0(com_cmm_u_cmm_pm_N_41807_i), + .I1(com_cmm_u_cmm_pm_N_42574), + .I2(com_cmm_u_cmm_pm_dev_power_state_eq_d0), + .I3(com_cmm_u_cmm_pm_pme_sent13), + .LO(com_cmm_u_cmm_pm_N_68956_i_4976) + ); + defparam com_cmm_u_cmm_pm_st_pm_next_0_0_0_iv_1_i_0_a2_0_13_.INIT = 8'h02; + LUT3_L com_cmm_u_cmm_pm_st_pm_next_0_0_0_iv_1_i_0_a2_0_13_ ( + .I0(com_st_pm[13]), + .I1(com_cmml_rpm_ra), + .I2(com_cmmt_rpm_as_nak_l1), + .LO(com_cmm_u_cmm_pm_N_42928) + ); + defparam com_cmm_u_cmm_pm_st_pm_next_0_0_0_iv_0_0_0_10_.INIT = 16'hFF10; + LUT4_L com_cmm_u_cmm_pm_st_pm_next_0_0_0_iv_0_0_0_10_ ( + .I0(com_cmm_u_cmm_pm_N_48889_i), + .I1(com_cmm_u_cmm_pm_N_49797_3), + .I2(com_cmm_u_cmm_pm_enable_cmm_tx[1]), + .I3(com_cmm_u_cmm_pm_st_pm_10__4979), + .LO(com_cmm_u_cmm_pm_N_9229_i) + ); + defparam com_cmm_u_cmm_pm_st_pm_next_0_0_0_iv_1_i_0_0_a2_9_.INIT = 4'h4; + LUT2_L com_cmm_u_cmm_pm_st_pm_next_0_0_0_iv_1_i_0_0_a2_9_ ( + .I0(com_cmm_u_cmm_pm_N_48889_i), + .I1(com_cmm_u_cmm_pm_N_49797_3), + .LO(com_cmm_u_cmm_pm_N_49797) + ); + defparam com_cmm_u_cmm_pm_N_69020_i.INIT = 8'hCE; + LUT3_L com_cmm_u_cmm_pm_N_69020_i ( + .I0(com_cmm_u_cmm_pm_st_pm_6__4982), + .I1(com_cmm_u_cmm_pm_st_pm_16__4977), + .I2(com_cmmt_ppm_suspend_ok), + .LO(com_cmm_u_cmm_pm_N_69020_i_4981) + ); + defparam com_cmm_u_cmm_pm_N_68912_i.INIT = 16'hECA0; + LUT4_L com_cmm_u_cmm_pm_N_68912_i ( + .I0(com_cmm_u_cmm_pm_N_41807_i), + .I1(com_cmm_u_cmm_pm_st_pm_27__4986), + .I2(com_cmm_u_cmm_pm_st_pm_28__4984), + .I3(com_cmml_rpm_ra), + .LO(com_cmm_u_cmm_pm_N_68912_i_4983) + ); + defparam com_cmm_u_cmm_pm_N_68913_i.INIT = 16'h88F8; + LUT4_L com_cmm_u_cmm_pm_N_68913_i ( + .I0(com_cmm_gnt_pm), + .I1(com_cmm_st_pm[26]), + .I2(com_cmm_u_cmm_pm_st_pm_27__4986), + .I3(com_cmml_rpm_ra), + .LO(com_cmm_u_cmm_pm_N_68913_i_4985) + ); + defparam com_cmm_u_cmm_pm_N_68929_i.INIT = 16'h7530; + LUT4_L com_cmm_u_cmm_pm_N_68929_i ( + .I0(cfg_turnoff_ok_n), + .I1(com_cmm_gnt_pm), + .I2(com_cmm_st_pm[26]), + .I3(com_cmm_u_cmm_pm_st_pm_30__5005), + .LO(com_cmm_u_cmm_pm_N_68929_i_4987) + ); + defparam com_cmm_u_cmm_pm_N_68977_i.INIT = 16'h3F11; + LUT4_L com_cmm_u_cmm_pm_N_68977_i ( + .I0(com_cmm_u_cmm_pm_N_48910_i), + .I1(com_cmm_cmm_arb_pend_req_n), + .I2(com_cmm_u_cmm_pm_dev_power_state_eq_d0), + .I3(com_cmm_u_cmm_pm_st_pm_25__4989), + .LO(com_cmm_u_cmm_pm_N_68977_i_4988) + ); + defparam com_cmm_u_cmm_pm_st_pm_next_3_sqmuxa_i_i_a2_0_a2_0_a2.INIT = 4'h8; + LUT2_L com_cmm_u_cmm_pm_st_pm_next_3_sqmuxa_i_i_a2_0_a2_0_a2 ( + .I0(com_cmm_u_cmm_pm_N_41807_i), + .I1(com_cmm_u_cmm_pm_inactivity_timer24), + .LO(com_cmm_u_cmm_pm_st_pm_next_3_sqmuxa_i_i_a2_0_a2_0_a2_4990) + ); + defparam com_cmm_u_cmm_pm_N_68970_i.INIT = 16'h8F88; + LUT4_L com_cmm_u_cmm_pm_N_68970_i ( + .I0(com_cmm_u_cmm_pm_N_48889_i), + .I1(com_cmm_u_cmm_pm_cfg_pcie_link_state[0]), + .I2(com_cmm_gnt_pm), + .I3(com_cmm_pme_ack_bar), + .LO(com_cmm_u_cmm_pm_N_68970_i_4993) + ); + defparam com_cmm_u_cmm_pm_N_68911_i.INIT = 16'hA0EC; + LUT4_L com_cmm_u_cmm_pm_N_68911_i ( + .I0(com_cmm_u_cmm_pm_st_pm_17__5000), + .I1(com_cmm_u_cmm_pm_st_pm_18__4998), + .I2(com_cmml_rpm_ra), + .I3(com_cmml_suspend_ok), + .LO(com_cmm_u_cmm_pm_N_68911_i_4997) + ); + defparam com_cmm_u_cmm_pm_N_68928_i.INIT = 16'hAE0C; + LUT4_L com_cmm_u_cmm_pm_N_68928_i ( + .I0(com_cmm_u_cmm_pm_st_pm_6__4982), + .I1(com_cmm_u_cmm_pm_st_pm_17__5000), + .I2(com_cmml_rpm_ra), + .I3(com_cmmt_ppm_suspend_ok), + .LO(com_cmm_u_cmm_pm_N_68928_i_4999) + ); + defparam com_cmm_u_cmm_pm_st_pm_i_17_.INIT = 4'h1; + LUT1_L com_cmm_u_cmm_pm_st_pm_i_17_ ( + .I0(com_cmm_u_cmm_pm_st_pm_17__5000), + .LO(com_st_pm_i[17]) + ); + defparam com_cmm_u_cmm_pm_cmml_suspend_now_n_i.INIT = 4'h1; + LUT1_L com_cmm_u_cmm_pm_cmml_suspend_now_n_i ( + .I0(com_cmml_suspend_now_n), + .LO(com_cmml_suspend_now_n_i) + ); + defparam com_cmm_u_cmm_pm_cmmt_ppm_suspend_req_n_i.INIT = 4'h1; + LUT1_L com_cmm_u_cmm_pm_cmmt_ppm_suspend_req_n_i ( + .I0(com_cmmt_ppm_suspend_req_n), + .LO(com_cmmt_ppm_suspend_req_n_i) + ); + defparam com_cmm_u_cmm_pm_N_42573_i.INIT = 4'h1; + LUT1_L com_cmm_u_cmm_pm_N_42573_i ( + .I0(com_cmm_u_cmm_pm_un1_cmml_suspend_now_n21_i_0_0_a2_0_4973), + .LO(com_cmm_u_cmm_pm_N_42573_i_5003) + ); + defparam com_cmm_u_cmm_pm_N_67956_i_1.INIT = 16'h7350; + LUT4_L com_cmm_u_cmm_pm_N_67956_i_1 ( + .I0(com_cmm_u_cmm_pm_N_48889_i), + .I1(com_cmm_u_cmm_pm_N_48910_i), + .I2(com_cmm_u_cmm_pm_cfg_pcie_link_state[0]), + .I3(com_cmm_cmm_arb_pend_req_n), + .LO(com_cmm_u_cmm_pm_N_67956_i_1_5006) + ); + defparam com_cmm_u_cmm_pm_N_68064_i_1.INIT = 16'h0D0F; + LUT4 com_cmm_u_cmm_pm_N_68064_i_1 ( + .I0(com_cmm_cmm_arb_pend_req_n), + .I1(com_cmm_pme_ack_bar), + .I2(com_cmm_u_cmm_pm_pme_sent13), + .I3(com_cmm_u_cmm_pm_st_pm_25__4989), + .O(com_cmm_u_cmm_pm_N_68064_i_1_4972) + ); + defparam com_cmm_u_cmm_pm_N_68064_i.INIT = 16'h20FF; + LUT4 com_cmm_u_cmm_pm_N_68064_i ( + .I0(com_cmm_u_cmm_pm_N_41785_i), + .I1(com_cmm_u_cmm_pm_N_68064_i_1_4972), + .I2(com_cmm_u_cmm_pm_dev_power_state_eq_d0), + .I3(com_cmm_u_cmm_pm_un1_cmmt_ppm_suspend_req_n_comb_0_sqmuxa_i_0_0_4971), + .O(com_cmm_u_cmm_pm_N_68064_i_5001) + ); + defparam com_cmm_u_cmm_pm_un1_cmml_suspend_now_n21_i_0_0_a2_0.INIT = 8'hA8; + LUT3 com_cmm_u_cmm_pm_un1_cmml_suspend_now_n21_i_0_0_a2_0 ( + .I0(com_cmml_rpm_ra), + .I1(com_cmm_u_cmm_pm_st_pm_27__4986), + .I2(com_cmm_u_cmm_pm_st_pm_17__5000), + .O(com_cmm_u_cmm_pm_un1_cmml_suspend_now_n21_i_0_0_a2_0_4973) + ); + FDC com_cmm_u_cmm_pm_inactivity_timer_8_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_pm_inactivity_timer_s[8]), + .Q(com_cmm_u_cmm_pm_inactivity_timer[8]), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_pm_inactivity_timer_7_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_pm_inactivity_timer_s[7]), + .Q(com_cmm_u_cmm_pm_inactivity_timer[7]), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_pm_inactivity_timer_6_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_pm_inactivity_timer_s[6]), + .Q(com_cmm_u_cmm_pm_inactivity_timer[6]), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_pm_inactivity_timer_5_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_pm_inactivity_timer_s[5]), + .Q(com_cmm_u_cmm_pm_inactivity_timer[5]), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_pm_inactivity_timer_4_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_pm_inactivity_timer_s[4]), + .Q(com_cmm_u_cmm_pm_inactivity_timer[4]), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_pm_inactivity_timer_3_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_pm_inactivity_timer_s[3]), + .Q(com_cmm_u_cmm_pm_inactivity_timer[3]), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_pm_inactivity_timer_2_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_pm_inactivity_timer_s[2]), + .Q(com_cmm_u_cmm_pm_inactivity_timer[2]), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_pm_inactivity_timer_1_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_pm_inactivity_timer_s[1]), + .Q(com_cmm_u_cmm_pm_inactivity_timer[1]), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_pm_inactivity_timer_0_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_pm_inactivity_timer_s[0]), + .Q(com_cmm_u_cmm_pm_inactivity_timer[0]), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_pm_pme_sent ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_pm_pme_sent13), + .Q(com_cmm_pme_sent), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_pm_st_pm_1_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_pm_N_68083_i_4974), + .Q(com_cmm_u_cmm_pm_cfg_pcie_link_state[0]), + .CLR(com_cmm_rst_267) + ); + FDP com_cmm_u_cmm_pm_st_pm_0_ ( + .PRE(com_cmm_rst_267), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_pm_st_pm_next[0]), + .Q(com_cmm_u_cmm_pm_st_pm_0__4975) + ); + FDC com_cmm_u_cmm_pm_st_pm_16_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_pm_N_68956_i_4976), + .Q(com_cmm_u_cmm_pm_st_pm_16__4977), + .CLR(com_cmm_rst_267) + ); + FDCE com_cmm_u_cmm_pm_st_pm_14_ ( + .CE(com_cmm_u_cmm_pm_N_42882), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_pm_VCC_4995), + .Q(com_cmm_u_cmm_pm_st_pm_14__4978), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_pm_st_pm_13_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_pm_N_42928), + .Q(com_st_pm[13]), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_pm_st_pm_10_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_pm_N_9229_i), + .Q(com_cmm_u_cmm_pm_st_pm_10__4979), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_pm_st_pm_9_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_pm_N_49797), + .Q(com_cmm_u_cmm_pm_enable_cmm_tx[1]), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_pm_st_pm_8_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_pm_st_pm_8__4980), + .Q(com_cmm_u_cmm_pm_st_pm_8__4980), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_pm_st_pm_6_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_pm_N_69020_i_4981), + .Q(com_cmm_u_cmm_pm_st_pm_6__4982), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_pm_st_pm_30_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_pm_N_67956_i_5004), + .Q(com_cmm_u_cmm_pm_st_pm_30__5005), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_pm_st_pm_28_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_pm_N_68912_i_4983), + .Q(com_cmm_u_cmm_pm_st_pm_28__4984), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_pm_st_pm_27_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_pm_N_68913_i_4985), + .Q(com_cmm_u_cmm_pm_st_pm_27__4986), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_pm_st_pm_26_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_pm_N_68929_i_4987), + .Q(com_cmm_st_pm[26]), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_pm_st_pm_25_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_pm_N_68977_i_4988), + .Q(com_cmm_u_cmm_pm_st_pm_25__4989), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_pm_st_pm_24_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_pm_st_pm_next_3_sqmuxa_i_i_a2_0_a2_0_a2_4990), + .Q(com_cmm_u_cmm_pm_st_pm_24__4991), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_pm_st_pm_23_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_pm_st_pm_23__4992), + .Q(com_cmm_u_cmm_pm_st_pm_23__4992), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_pm_st_pm_22_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_pm_N_68970_i_4993), + .Q(com_cmm_pme_ack_bar), + .CLR(com_cmm_rst_267) + ); + FDCE com_cmm_u_cmm_pm_st_pm_21_ ( + .CE(com_cmm_u_cmm_pm_N_50013), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_pm_VCC_4995), + .Q(com_cmm_u_cmm_pm_st_pm_21__4994), + .CLR(com_cmm_rst_267) + ); + FDCE com_cmm_u_cmm_pm_st_pm_19_ ( + .CE(com_cmm_u_cmm_pm_N_42575), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_pm_VCC_4995), + .Q(com_cmm_u_cmm_pm_st_pm_19__4996), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_pm_st_pm_18_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_pm_N_68911_i_4997), + .Q(com_cmm_u_cmm_pm_st_pm_18__4998), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_pm_st_pm_17_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_pm_N_68928_i_4999), + .Q(com_cmm_u_cmm_pm_st_pm_17__5000), + .CLR(com_cmm_rst_267) + ); + FDPE com_cmm_u_cmm_pm_cmmt_ppm_suspend_req_n ( + .PRE(com_cmm_rst_267), + .CE(com_cmm_u_cmm_pm_N_68064_i_5001), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_pm_N_41785_i), + .Q(com_cmmt_ppm_suspend_req_n) + ); + FDPE com_cmm_u_cmm_pm_cmml_suspend_now_n ( + .PRE(com_cmm_rst_267), + .CE(com_cmm_u_cmm_pm_N_68005_i_5002), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_pm_N_42573_i_5003), + .Q(com_cmml_suspend_now_n) + ); + INV com_cmm_u_cmm_pm_cfg_pcie_link_state_i_0_ ( + .I(com_cmm_u_cmm_pm_cfg_pcie_link_state[0]), + .O(cfg_pcie_link_state_n_5071[0]) + ); + INV com_cmm_u_cmm_pm_enable_cmm_tx_i_1_ ( + .I(com_cmm_u_cmm_pm_enable_cmm_tx[1]), + .O(cfg_pcie_link_state_n_5071[1]) + ); + INV com_cmm_u_cmm_pm_st_pm_i_30_ ( + .I(com_cmm_u_cmm_pm_st_pm_30__5005), + .O(cfg_to_turnoff_n) + ); + defparam com_cmm_u_cmm_pm_N_67956_i.INIT = 16'hECA0; + LUT4_L com_cmm_u_cmm_pm_N_67956_i ( + .I0(cfg_turnoff_ok_n), + .I1(com_cmm_u_cmm_pm_N_67956_i_1_5006), + .I2(com_cmm_u_cmm_pm_st_pm_30__5005), + .I3(com_cmmt_rpm_turn_off), + .LO(com_cmm_u_cmm_pm_N_67956_i_5004) + ); + defparam com_cmm_u_cmm_pm_inactivity_timer_qxu_0_0_.INIT = 4'h8; + LUT2_L com_cmm_u_cmm_pm_inactivity_timer_qxu_0_0_ ( + .I0(com_cmm_u_cmm_pm_inactivity_timer24), + .I1(com_cmm_u_cmm_pm_inactivity_timer[0]), + .LO(com_cmm_u_cmm_pm_inactivity_timer_qxu[0]) + ); + defparam com_cmm_u_cmm_pm_inactivity_timer_qxu_0_1_.INIT = 4'h8; + LUT2_L com_cmm_u_cmm_pm_inactivity_timer_qxu_0_1_ ( + .I0(com_cmm_u_cmm_pm_inactivity_timer24), + .I1(com_cmm_u_cmm_pm_inactivity_timer[1]), + .LO(com_cmm_u_cmm_pm_inactivity_timer_qxu[1]) + ); + defparam com_cmm_u_cmm_pm_inactivity_timer_qxu_0_2_.INIT = 4'h8; + LUT2_L com_cmm_u_cmm_pm_inactivity_timer_qxu_0_2_ ( + .I0(com_cmm_u_cmm_pm_inactivity_timer24), + .I1(com_cmm_u_cmm_pm_inactivity_timer[2]), + .LO(com_cmm_u_cmm_pm_inactivity_timer_qxu[2]) + ); + defparam com_cmm_u_cmm_pm_inactivity_timer_qxu_0_3_.INIT = 4'h8; + LUT2_L com_cmm_u_cmm_pm_inactivity_timer_qxu_0_3_ ( + .I0(com_cmm_u_cmm_pm_inactivity_timer24), + .I1(com_cmm_u_cmm_pm_inactivity_timer[3]), + .LO(com_cmm_u_cmm_pm_inactivity_timer_qxu[3]) + ); + defparam com_cmm_u_cmm_pm_inactivity_timer_qxu_0_4_.INIT = 4'h8; + LUT2_L com_cmm_u_cmm_pm_inactivity_timer_qxu_0_4_ ( + .I0(com_cmm_u_cmm_pm_inactivity_timer24), + .I1(com_cmm_u_cmm_pm_inactivity_timer[4]), + .LO(com_cmm_u_cmm_pm_inactivity_timer_qxu[4]) + ); + defparam com_cmm_u_cmm_pm_inactivity_timer_qxu_0_5_.INIT = 4'h8; + LUT2_L com_cmm_u_cmm_pm_inactivity_timer_qxu_0_5_ ( + .I0(com_cmm_u_cmm_pm_inactivity_timer24), + .I1(com_cmm_u_cmm_pm_inactivity_timer[5]), + .LO(com_cmm_u_cmm_pm_inactivity_timer_qxu[5]) + ); + defparam com_cmm_u_cmm_pm_inactivity_timer_qxu_0_6_.INIT = 4'h8; + LUT2_L com_cmm_u_cmm_pm_inactivity_timer_qxu_0_6_ ( + .I0(com_cmm_u_cmm_pm_inactivity_timer24), + .I1(com_cmm_u_cmm_pm_inactivity_timer[6]), + .LO(com_cmm_u_cmm_pm_inactivity_timer_qxu[6]) + ); + defparam com_cmm_u_cmm_pm_inactivity_timer_qxu_0_7_.INIT = 4'h8; + LUT2_L com_cmm_u_cmm_pm_inactivity_timer_qxu_0_7_ ( + .I0(com_cmm_u_cmm_pm_inactivity_timer24), + .I1(com_cmm_u_cmm_pm_inactivity_timer[7]), + .LO(com_cmm_u_cmm_pm_inactivity_timer_qxu[7]) + ); + defparam com_cmm_u_cmm_pm_inactivity_timer_qxu_0_8_.INIT = 4'h8; + LUT2_L com_cmm_u_cmm_pm_inactivity_timer_qxu_0_8_ ( + .I0(com_cmm_u_cmm_pm_inactivity_timer24), + .I1(com_cmm_u_cmm_pm_inactivity_timer[8]), + .LO(com_cmm_u_cmm_pm_inactivity_timer_qxu[8]) + ); + FDR com_cmm_u_cmm_arbiter_req_errman_d_0_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_req_errman[0]), + .Q(com_cmm_u_cmm_arbiter_req_errman_d[0]), + .R(com_cmm_u_cmm_arbiter_N_67934_i_5008) + ); + FDR com_cmm_u_cmm_arbiter_req_errman_d_1_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_req_errman[1]), + .Q(com_cmm_u_cmm_arbiter_req_errman_d[1]), + .R(com_cmm_u_cmm_arbiter_N_67934_i_5008) + ); + FDR com_cmm_u_cmm_arbiter_req_errman_d_2_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_req_errman[2]), + .Q(com_cmm_u_cmm_arbiter_req_errman_d[2]), + .R(com_cmm_u_cmm_arbiter_N_67934_i_5008) + ); + FDR com_cmm_u_cmm_arbiter_req_arbiter_0_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_arbiter_N_68969_i_5013), + .Q(com_cmm_req_arbiter[0]), + .R(com_cmm_rst_267) + ); + FDR com_cmm_u_cmm_arbiter_req_arbiter_1_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_arbiter_N_31258_i), + .Q(com_cmm_req_arbiter[1]), + .R(com_cmm_rst_267) + ); + FDR com_cmm_u_cmm_arbiter_req_arbiter_2_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_arbiter_N_31260_i), + .Q(com_cmm_req_arbiter[2]), + .R(com_cmm_rst_267) + ); + FDR com_cmm_u_cmm_arbiter_req_arbiter_3_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_arbiter_N_31243_i), + .Q(com_cmm_req_arbiter[3]), + .R(com_cmm_rst_267) + ); + FDS com_cmm_u_cmm_arbiter_cmm_arb_pend_req_n ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_arbiter_N_69018_i_5011), + .Q(com_cmm_cmm_arb_pend_req_n), + .S(com_cmm_rst_267) + ); + defparam com_cmm_u_cmm_arbiter_ns_fsm_0_0_0_a3_0_a2_2_.INIT = 4'h2; + LUT2 com_cmm_u_cmm_arbiter_ns_fsm_0_0_0_a3_0_a2_2_ ( + .I0(com_cmm_u_cmm_arbiter_cs_fsm[0]), + .I1(com_cmm_u_cmm_arbiter_cs_fsm[2]), + .O(com_cmm_u_cmm_arbiter_N_50129) + ); + defparam com_cmm_u_cmm_arbiter_N_41753_i_0_o3.INIT = 4'h1; + LUT2 com_cmm_u_cmm_arbiter_N_41753_i_0_o3 ( + .I0(com_cmm_u_cmm_arbiter_cs_fsm[1]), + .I1(com_cmm_u_cmm_arbiter_cs_fsm[3]), + .O(com_cmm_u_cmm_arbiter_N_48890_i) + ); + defparam com_cmm_u_cmm_arbiter_ns_fsm_0_0_0_0_o3_2_.INIT = 4'h1; + LUT2 com_cmm_u_cmm_arbiter_ns_fsm_0_0_0_0_o3_2_ ( + .I0(com_cmm_req_cfgctrl), + .I1(com_cmm_req_intr), + .O(com_cmm_u_cmm_arbiter_N_48922_i) + ); + defparam com_cmm_u_cmm_arbiter_req_arbiter_6_i_0_0_o3_3_.INIT = 4'h8; + LUT2 com_cmm_u_cmm_arbiter_req_arbiter_6_i_0_0_o3_3_ ( + .I0(com_cmm_u_cmm_arbiter_cs_fsm[1]), + .I1(com_cmm_u_cmm_arbiter_cs_fsm[2]), + .O(com_cmm_u_cmm_arbiter_N_48959_i) + ); + defparam com_cmm_u_cmm_arbiter_ns_fsm_0_i_0_o4_i_o3_0_.INIT = 4'h1; + LUT2 com_cmm_u_cmm_arbiter_ns_fsm_0_i_0_o4_i_o3_0_ ( + .I0(com_cmm_pme_ack_bar), + .I1(com_cmm_st_pm[26]), + .O(com_cmm_N_48915_i) + ); + defparam com_cmm_u_cmm_arbiter_ns_fsm_0_0_0_0_a2_2_.INIT = 8'h01; + LUT3 com_cmm_u_cmm_arbiter_ns_fsm_0_0_0_0_a2_2_ ( + .I0(com_cmm_u_cmm_arbiter_N_48922_i), + .I1(com_cmm_u_cmm_arbiter_cs_fsm[0]), + .I2(com_cmm_u_cmm_arbiter_cs_fsm[1]), + .O(com_cmm_u_cmm_arbiter_N_49490) + ); + defparam com_cmm_u_cmm_arbiter_ns_fsm_i_i_0_0_a2_3_.INIT = 8'h0B; + LUT3_L com_cmm_u_cmm_arbiter_ns_fsm_i_i_0_0_a2_3_ ( + .I0(com_cmm_req_cfgctrl), + .I1(com_cmm_req_intr), + .I2(com_cmm_u_cmm_arbiter_cs_fsm[3]), + .LO(com_cmm_u_cmm_arbiter_N_49665) + ); + defparam com_cmm_u_cmm_arbiter_ns_fsm_i_i_i_i_a2_1_0_a2_1_.INIT = 4'h2; + LUT2 com_cmm_u_cmm_arbiter_ns_fsm_i_i_i_i_a2_1_0_a2_1_ ( + .I0(com_cmm_u_cmm_arbiter_N_48890_i), + .I1(com_cmm_u_cmm_arbiter_cs_fsm[0]), + .O(com_cmm_u_cmm_arbiter_N_42901_1) + ); + defparam com_cmm_u_cmm_arbiter_req_arbiter_6_i_0_i_a2_0_0_.INIT = 16'h4500; + LUT4 com_cmm_u_cmm_arbiter_req_arbiter_6_i_0_i_a2_0_0_ ( + .I0(com_cmm_gnt_arbiter), + .I1(com_cmm_u_cmm_arbiter_cs_fsm[0]), + .I2(com_cmm_u_cmm_arbiter_cs_fsm[3]), + .I3(com_cmm_u_cmm_arbiter_req_errman_d[0]), + .O(com_cmm_u_cmm_arbiter_N_49662) + ); + defparam com_cmm_u_cmm_arbiter_ns_fsm_i_i_i_i_a2_0_1_.INIT = 8'h10; + LUT3 com_cmm_u_cmm_arbiter_ns_fsm_i_i_i_i_a2_0_1_ ( + .I0(com_cmm_gnt_arbiter), + .I1(com_cmm_u_cmm_arbiter_cs_fsm[0]), + .I2(com_cmm_u_cmm_arbiter_cs_fsm[1]), + .O(com_cmm_u_cmm_arbiter_N_42902) + ); + defparam com_cmm_u_cmm_arbiter_req_errman_d8_i_o3_1.INIT = 8'h01; + LUT3 com_cmm_u_cmm_arbiter_req_errman_d8_i_o3_1 ( + .I0(com_cmm_req_errman[0]), + .I1(com_cmm_req_errman[1]), + .I2(com_cmm_req_errman[2]), + .O(com_cmm_u_cmm_arbiter_N_31558_i) + ); + defparam com_cmm_u_cmm_arbiter_req_errman_d8_i_0_0_1.INIT = 16'h0103; + LUT4 com_cmm_u_cmm_arbiter_req_errman_d8_i_0_0_1 ( + .I0(com_cmm_gnt_arbiter), + .I1(com_cmm_gnt_intr), + .I2(com_cmm_rst_267), + .I3(com_cmm_u_cmm_arbiter_cs_fsm[1]), + .O(com_cmm_u_cmm_arbiter_req_errman_d8_i_0_0_1_5007) + ); + defparam com_cmm_u_cmm_arbiter_req_arbiter_6_i_0_o2_1_.INIT = 8'h07; + LUT3 com_cmm_u_cmm_arbiter_req_arbiter_6_i_0_o2_1_ ( + .I0(com_cmm_u_cmm_arbiter_N_48890_i), + .I1(com_cmm_u_cmm_arbiter_N_50129), + .I2(com_cmm_gnt_arbiter), + .O(com_cmm_u_cmm_arbiter_N_42044_i) + ); + defparam com_cmm_u_cmm_arbiter_req_arbiter_6_i_0_i_o3_0_0_.INIT = 8'h31; + LUT3_L com_cmm_u_cmm_arbiter_req_arbiter_6_i_0_i_o3_0_0_ ( + .I0(com_cmm_u_cmm_arbiter_N_48890_i), + .I1(com_cmm_u_cmm_arbiter_N_48959_i), + .I2(com_cmm_u_cmm_arbiter_cs_fsm[2]), + .LO(com_cmm_u_cmm_arbiter_req_arbiter_6_i_0_i_o3_0[0]) + ); + defparam com_cmm_u_cmm_arbiter_ns_fsm_0_i_0_0_0_32141.INIT = 16'hA0FB; + LUT4 com_cmm_u_cmm_arbiter_ns_fsm_0_i_0_0_0_32141 ( + .I0(com_cmm_gnt_arbiter), + .I1(com_cmm_u_cmm_arbiter_cs_fsm[0]), + .I2(com_cmm_u_cmm_arbiter_cs_fsm[1]), + .I3(com_cmm_u_cmm_arbiter_cs_fsm[2]), + .O(com_cmm_u_cmm_arbiter_ns_fsm_0_i_0_0_0_32141_5010) + ); + defparam com_cmm_u_cmm_arbiter_ns_fsm_0_0_0_0_2_32149.INIT = 16'hC02B; + LUT4 com_cmm_u_cmm_arbiter_ns_fsm_0_0_0_0_2_32149 ( + .I0(com_cmm_gnt_arbiter), + .I1(com_cmm_u_cmm_arbiter_cs_fsm[0]), + .I2(com_cmm_u_cmm_arbiter_cs_fsm[1]), + .I3(com_cmm_u_cmm_arbiter_cs_fsm[2]), + .O(com_cmm_u_cmm_arbiter_ns_fsm_0_0_0_0_2_32149_5016) + ); + defparam com_cmm_u_cmm_arbiter_ns_fsm_0_i_0_0_a2_0_.INIT = 16'h00E4; + LUT4 com_cmm_u_cmm_arbiter_ns_fsm_0_i_0_0_a2_0_ ( + .I0(com_cmm_u_cmm_arbiter_N_48890_i), + .I1(com_cmm_gnt_arbiter), + .I2(com_cmm_req_cfgctrl), + .I3(com_cmm_u_cmm_arbiter_cs_fsm[0]), + .O(com_cmm_u_cmm_arbiter_N_49666) + ); + defparam com_cmm_u_cmm_arbiter_req_arbiter_6_i_0_1_32144.INIT = 16'hEFC8; + LUT4 com_cmm_u_cmm_arbiter_req_arbiter_6_i_0_1_32144 ( + .I0(com_cmm_u_cmm_arbiter_cs_fsm[0]), + .I1(com_cmm_u_cmm_arbiter_cs_fsm[1]), + .I2(com_cmm_u_cmm_arbiter_cs_fsm[3]), + .I3(com_cmm_u_cmm_arbiter_req_errman_d[1]), + .O(com_cmm_u_cmm_arbiter_req_arbiter_6_i_0_1_32144_5012) + ); + defparam com_cmm_u_cmm_arbiter_ns_fsm_i_i_i_i_a2_1_.INIT = 16'h4C00; + LUT4_L com_cmm_u_cmm_arbiter_ns_fsm_i_i_i_i_a2_1_ ( + .I0(com_cmm_u_cmm_arbiter_N_31558_i), + .I1(com_cmm_u_cmm_arbiter_N_42901_1), + .I2(com_cmm_N_48915_i), + .I3(com_cmm_u_cmm_arbiter_N_48922_i), + .LO(com_cmm_u_cmm_arbiter_N_42901) + ); + defparam com_cmm_u_cmm_arbiter_ns_fsm_0_i_0_0_a2_1_0_.INIT = 16'h0008; + LUT4_L com_cmm_u_cmm_arbiter_ns_fsm_0_i_0_0_a2_1_0_ ( + .I0(com_cmm_u_cmm_arbiter_N_31558_i), + .I1(com_cmm_u_cmm_arbiter_N_42901_1), + .I2(com_cmm_N_48915_i), + .I3(com_cmm_req_intr), + .LO(com_cmm_u_cmm_arbiter_N_49668) + ); + defparam com_cmm_u_cmm_arbiter_req_errman_d8_i_0_0_3.INIT = 16'h0100; + LUT4_L com_cmm_u_cmm_arbiter_req_errman_d8_i_0_0_3 ( + .I0(com_cmm_u_cmm_arbiter_N_49490), + .I1(com_cmm_u_cmm_arbiter_cs_fsm[0]), + .I2(com_cmm_u_cmm_arbiter_cs_fsm[2]), + .I3(com_cmm_u_cmm_arbiter_req_errman_d8_i_0_0_1_5007), + .LO(com_cmm_u_cmm_arbiter_req_errman_d8_i_0_0_3_5009) + ); + defparam com_cmm_u_cmm_arbiter_N_67934_i.INIT = 16'h32FF; + LUT4 com_cmm_u_cmm_arbiter_N_67934_i ( + .I0(com_cmm_u_cmm_arbiter_N_31558_i), + .I1(com_cmm_u_cmm_arbiter_cs_fsm[1]), + .I2(com_cmm_u_cmm_arbiter_cs_fsm[3]), + .I3(com_cmm_u_cmm_arbiter_req_errman_d8_i_0_0_3_5009), + .O(com_cmm_u_cmm_arbiter_N_67934_i_5008) + ); + defparam com_cmm_u_cmm_arbiter_ns_fsm_0_sqmuxa_4_0_a2_0_a2_0_a2.INIT = 8'h80; + LUT3_L com_cmm_u_cmm_arbiter_ns_fsm_0_sqmuxa_4_0_a2_0_a2_0_a2 ( + .I0(com_cmm_u_cmm_arbiter_N_48890_i), + .I1(com_cmm_u_cmm_arbiter_N_50129), + .I2(com_cmm_gnt_arbiter), + .LO(com_cmm_u_cmm_arbiter_ns_fsm_0_sqmuxa_4) + ); + defparam com_cmm_u_cmm_arbiter_ns_fsm_0_sqmuxa_2_0_a2_0_a2_0_a2.INIT = 8'h20; + LUT3_L com_cmm_u_cmm_arbiter_ns_fsm_0_sqmuxa_2_0_a2_0_a2_0_a2 ( + .I0(com_cmm_gnt_arbiter), + .I1(com_cmm_u_cmm_arbiter_cs_fsm[0]), + .I2(com_cmm_u_cmm_arbiter_cs_fsm[3]), + .LO(com_cmm_u_cmm_arbiter_ns_fsm_0_sqmuxa_2) + ); + defparam com_cmm_u_cmm_arbiter_ns_fsm_0_a4_0_0_a2_0_a2_0_a2_2_.INIT = 16'h0020; + LUT4_L com_cmm_u_cmm_arbiter_ns_fsm_0_a4_0_0_a2_0_a2_0_a2_2_ ( + .I0(com_cmm_gnt_arbiter), + .I1(com_cmm_u_cmm_arbiter_cs_fsm[0]), + .I2(com_cmm_u_cmm_arbiter_cs_fsm[1]), + .I3(com_cmm_u_cmm_arbiter_cs_fsm[2]), + .LO(com_cmm_u_cmm_arbiter_ns_fsm_0_a4_0_0_a2_0_a2_0_a2[2]) + ); + defparam com_cmm_u_cmm_arbiter_ns_fsm_0_sqmuxa_0_a2_0_a2_0_a2.INIT = 16'h8000; + LUT4_L com_cmm_u_cmm_arbiter_ns_fsm_0_sqmuxa_0_a2_0_a2_0_a2 ( + .I0(com_cmm_gnt_arbiter), + .I1(com_cmm_u_cmm_arbiter_cs_fsm[0]), + .I2(com_cmm_u_cmm_arbiter_cs_fsm[1]), + .I3(com_cmm_u_cmm_arbiter_cs_fsm[2]), + .LO(com_cmm_u_cmm_arbiter_ns_fsm_0_sqmuxa) + ); + defparam com_cmm_u_cmm_arbiter_ns_fsm_i_i_0_0_3_.INIT = 16'h0001; + LUT4_L com_cmm_u_cmm_arbiter_ns_fsm_i_i_0_0_3_ ( + .I0(com_cmm_u_cmm_arbiter_N_49665), + .I1(com_cmm_u_cmm_arbiter_cs_fsm[0]), + .I2(com_cmm_u_cmm_arbiter_cs_fsm[1]), + .I3(com_cmm_u_cmm_arbiter_cs_fsm[2]), + .LO(com_cmm_u_cmm_arbiter_N_31275_i) + ); + defparam com_cmm_u_cmm_arbiter_N_68065_i.INIT = 16'hFFFE; + LUT4_L com_cmm_u_cmm_arbiter_N_68065_i ( + .I0(com_cmm_u_cmm_arbiter_N_42901), + .I1(com_cmm_u_cmm_arbiter_N_42902), + .I2(com_cmm_gnt_intr), + .I3(com_cmm_u_cmm_arbiter_cs_fsm[2]), + .LO(com_cmm_u_cmm_arbiter_N_68065_i_5014) + ); + defparam com_cmm_u_cmm_arbiter_N_67938_i.INIT = 16'hFFEF; + LUT4_L com_cmm_u_cmm_arbiter_N_67938_i ( + .I0(com_cmm_u_cmm_arbiter_N_49666), + .I1(com_cmm_u_cmm_arbiter_N_49668), + .I2(com_cmm_u_cmm_arbiter_ns_fsm_0_i_0_0_0_32141_5010), + .I3(com_cmm_gnt_intr), + .LO(com_cmm_u_cmm_arbiter_N_67938_i_5015) + ); + defparam com_cmm_u_cmm_arbiter_N_69018_i.INIT = 16'h2A79; + LUT4_L com_cmm_u_cmm_arbiter_N_69018_i ( + .I0(com_cmm_u_cmm_arbiter_cs_fsm[0]), + .I1(com_cmm_u_cmm_arbiter_cs_fsm[1]), + .I2(com_cmm_u_cmm_arbiter_cs_fsm[2]), + .I3(com_cmm_u_cmm_arbiter_cs_fsm[3]), + .LO(com_cmm_u_cmm_arbiter_N_69018_i_5011) + ); + defparam com_cmm_u_cmm_arbiter_req_arbiter_6_i_0_0_3_.INIT = 16'h2300; + LUT4_L com_cmm_u_cmm_arbiter_req_arbiter_6_i_0_0_3_ ( + .I0(com_cmm_u_cmm_arbiter_N_48959_i), + .I1(com_cmm_gnt_arbiter), + .I2(com_cmm_u_cmm_arbiter_cs_fsm[0]), + .I3(com_cmm_u_cmm_arbiter_cs_fsm[3]), + .LO(com_cmm_u_cmm_arbiter_N_31243_i) + ); + defparam com_cmm_u_cmm_arbiter_req_arbiter_6_i_0_1_.INIT = 16'hA020; + LUT4_L com_cmm_u_cmm_arbiter_req_arbiter_6_i_0_1_ ( + .I0(com_cmm_u_cmm_arbiter_N_42044_i), + .I1(com_cmm_u_cmm_arbiter_N_50129), + .I2(com_cmm_u_cmm_arbiter_req_arbiter_6_i_0_1_32144_5012), + .I3(com_cmm_u_cmm_arbiter_req_errman_d[1]), + .LO(com_cmm_u_cmm_arbiter_N_31258_i) + ); + defparam com_cmm_u_cmm_arbiter_N_68969_i.INIT = 16'hABAA; + LUT4_L com_cmm_u_cmm_arbiter_N_68969_i ( + .I0(com_cmm_u_cmm_arbiter_N_49662), + .I1(com_cmm_u_cmm_arbiter_req_arbiter_6_i_0_i_o3_0[0]), + .I2(com_cmm_gnt_arbiter), + .I3(com_cmm_u_cmm_arbiter_cs_fsm[0]), + .LO(com_cmm_u_cmm_arbiter_N_68969_i_5013) + ); + defparam com_cmm_u_cmm_arbiter_req_arbiter_6_i_0_1_2_.INIT = 16'h2570; + LUT4 com_cmm_u_cmm_arbiter_req_arbiter_6_i_0_1_2_ ( + .I0(com_cmm_u_cmm_arbiter_cs_fsm[0]), + .I1(com_cmm_u_cmm_arbiter_cs_fsm[1]), + .I2(com_cmm_u_cmm_arbiter_cs_fsm[2]), + .I3(com_cmm_u_cmm_arbiter_cs_fsm[3]), + .O(com_cmm_u_cmm_arbiter_req_arbiter_6_i_0_1[2]) + ); + defparam com_cmm_u_cmm_arbiter_ns_fsm_0_0_0_0_1_2_.INIT = 16'h00F2; + LUT4 com_cmm_u_cmm_arbiter_ns_fsm_0_0_0_0_1_2_ ( + .I0(com_cmm_u_cmm_arbiter_N_31558_i), + .I1(com_cmm_N_48915_i), + .I2(com_cmm_u_cmm_arbiter_cs_fsm[0]), + .I3(com_cmm_u_cmm_arbiter_cs_fsm[3]), + .O(com_cmm_u_cmm_arbiter_ns_fsm_0_0_0_0_1[2]) + ); + FDC com_cmm_u_cmm_arbiter_gnt_cfgctrl ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_arbiter_ns_fsm_0_sqmuxa_4), + .Q(com_cmm_gnt_cfgctrl), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_arbiter_gnt_intr ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_arbiter_ns_fsm_0_sqmuxa_2), + .Q(com_cmm_gnt_intr), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_arbiter_gnt_errman ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_arbiter_ns_fsm_0_a4_0_0_a2_0_a2_0_a2[2]), + .Q(com_cmm_gnt_errman), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_arbiter_gnt_pm ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_arbiter_ns_fsm_0_sqmuxa), + .Q(com_cmm_gnt_pm), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_arbiter_cs_fsm_3_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_arbiter_N_31275_i), + .Q(com_cmm_u_cmm_arbiter_cs_fsm[3]), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_arbiter_cs_fsm_2_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_arbiter_N_8978_i), + .Q(com_cmm_u_cmm_arbiter_cs_fsm[2]), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_arbiter_cs_fsm_1_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_arbiter_N_68065_i_5014), + .Q(com_cmm_u_cmm_arbiter_cs_fsm[1]), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_arbiter_cs_fsm_0_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_arbiter_N_67938_i_5015), + .Q(com_cmm_u_cmm_arbiter_cs_fsm[0]), + .CLR(com_cmm_rst_267) + ); + defparam com_cmm_u_cmm_arbiter_ns_fsm_0_0_0_0_2_.INIT = 16'h4440; + LUT4_L com_cmm_u_cmm_arbiter_ns_fsm_0_0_0_0_2_ ( + .I0(com_cmm_u_cmm_arbiter_N_49490), + .I1(com_cmm_u_cmm_arbiter_ns_fsm_0_0_0_0_2_32149_5016), + .I2(com_cmm_u_cmm_arbiter_cs_fsm[1]), + .I3(com_cmm_u_cmm_arbiter_ns_fsm_0_0_0_0_1[2]), + .LO(com_cmm_u_cmm_arbiter_N_8978_i) + ); + defparam com_cmm_u_cmm_arbiter_req_arbiter_6_i_0_2_.INIT = 16'h8A08; + LUT4_L com_cmm_u_cmm_arbiter_req_arbiter_6_i_0_2_ ( + .I0(com_cmm_u_cmm_arbiter_N_42044_i), + .I1(com_cmm_u_cmm_arbiter_cs_fsm[2]), + .I2(com_cmm_u_cmm_arbiter_req_arbiter_6_i_0_1[2]), + .I3(com_cmm_u_cmm_arbiter_req_errman_d[2]), + .LO(com_cmm_u_cmm_arbiter_N_31260_i) + ); + FDR com_cmm_u_cmm_dataproducer_req_gnt_state_0_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_dataproducer_N_14865_i), + .Q(com_cmm_u_cmm_dataproducer_req_gnt_state[0]), + .R(com_cmm_rst_267) + ); + FDR com_cmm_u_cmm_dataproducer_req_gnt_state_1_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_dataproducer_N_14855_i), + .Q(com_cmm_u_cmm_dataproducer_req_gnt_state[1]), + .R(com_cmm_rst_267) + ); + FDRE com_cmm_u_cmm_dataproducer_req_gnt_code_0_ ( + .CE(com_cmm_u_cmm_dataproducer_N_9377_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_dataproducer_N_14857_i), + .Q(com_cmm_u_cmm_dataproducer_req_gnt_code_0__295), + .R(com_cmm_rst_267) + ); + FDRE com_cmm_u_cmm_dataproducer_req_gnt_code_1_ ( + .CE(com_cmm_u_cmm_dataproducer_N_9377_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_dataproducer_N_14859_i), + .Q(com_cmm_u_cmm_dataproducer_req_gnt_code[1]), + .R(com_cmm_rst_267) + ); + FDRE com_cmm_u_cmm_dataproducer_req_gnt_code_2_ ( + .CE(com_cmm_u_cmm_dataproducer_N_9377_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_dataproducer_N_14861_i), + .Q(com_cmm_u_cmm_dataproducer_req_gnt_code[2]), + .R(com_cmm_rst_267) + ); + FDRE com_cmm_u_cmm_dataproducer_req_gnt_code_3_ ( + .CE(com_cmm_u_cmm_dataproducer_N_9377_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_dataproducer_N_14863_i), + .Q(com_cmm_u_cmm_dataproducer_req_gnt_code_3__234), + .R(com_cmm_rst_267) + ); + defparam com_cmm_u_cmm_dataproducer_req_gnt_code_8_i_0_0_0_o3_3_.INIT = 4'h1; + LUT2 com_cmm_u_cmm_dataproducer_req_gnt_code_8_i_0_0_0_o3_3_ ( + .I0(com_cmm_req_arbiter[1]), + .I1(com_cmm_req_arbiter[2]), + .O(com_cmm_u_cmm_dataproducer_N_48988_i) + ); + defparam com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_ss0_0_o2_i_a4_0_a3_0_1.INIT = 4'h2; + LUT2 com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_ss0_0_o2_i_a4_0_a3_0_1 ( + .I0(com_cmm_cfg_rd), + .I1(com_cmm_u_cmm_dataproducer_req_gnt_code[1]), + .O(com_cmm_u_cmm_dataproducer_N_50468_1) + ); + defparam com_cmm_u_cmm_dataproducer_byte_07_27_0_1_iv_i_0_0_0_a3_1_0_.INIT = 4'h4; + LUT2 com_cmm_u_cmm_dataproducer_byte_07_27_0_1_iv_i_0_0_0_a3_1_0_ ( + .I0(com_cmm_pme_ack_bar), + .I1(com_cmm_u_cmm_dataproducer_req_gnt_code[1]), + .O(N_50505_1) + ); + defparam com_cmm_u_cmm_dataproducer_byte_06_21_0_a2_0_a2_0_a2_0_o3_7_.INIT = 4'h4; + LUT2 com_cmm_u_cmm_dataproducer_byte_06_21_0_a2_0_a2_0_a2_0_o3_7_ ( + .I0(com_cmm_data_errmanager[48]), + .I1(com_cmm_data_errmanager[49]), + .O(com_cmm_N_48927_i) + ); + defparam com_cmm_u_cmm_dataproducer_byte_07_27_0_1_iv_0_i_0_0_a2_4_.INIT = 4'h2; + LUT2 com_cmm_u_cmm_dataproducer_byte_07_27_0_1_iv_0_i_0_0_a2_4_ ( + .I0(com_cmm_u_cmm_dataproducer_req_gnt_code[2]), + .I1(com_cmm_u_cmm_dataproducer_req_gnt_code_3__234), + .O(N_49663) + ); + defparam com_cmm_u_cmm_dataproducer_byte_07_27_0_1_iv_i_0_0_0_a2_5_.INIT = 4'h4; + LUT2 com_cmm_u_cmm_dataproducer_byte_07_27_0_1_iv_i_0_0_0_a2_5_ ( + .I0(com_cmm_u_cmm_dataproducer_req_gnt_code[1]), + .I1(com_cmm_u_cmm_dataproducer_req_gnt_code[2]), + .O(N_49558) + ); + defparam com_cmm_u_cmm_dataproducer_byte_07_27_0_1_iv_i_0_0_0_a2_1_.INIT = 8'h02; + LUT3 com_cmm_u_cmm_dataproducer_byte_07_27_0_1_iv_i_0_0_0_a2_1_ ( + .I0(N_49663), + .I1(com_cmm_u_cmm_dataproducer_req_gnt_code_0__295), + .I2(com_cmm_u_cmm_dataproducer_req_gnt_code[1]), + .O(com_cmm_u_cmm_dataproducer_N_49551) + ); + defparam com_cmm_u_cmm_dataproducer_byte_07_27_0_1_iv_i_0_i_i_a2_2_.INIT = 16'hE000; + LUT4 com_cmm_u_cmm_dataproducer_byte_07_27_0_1_iv_i_0_i_i_a2_2_ ( + .I0(com_cmm_u_cmm_dataproducer_req_gnt_code_0__295), + .I1(com_cmm_u_cmm_dataproducer_req_gnt_code[1]), + .I2(com_cmm_u_cmm_dataproducer_req_gnt_code[2]), + .I3(com_cmm_u_cmm_dataproducer_req_gnt_code_3__234), + .O(com_cmm_u_cmm_dataproducer_N_50006) + ); + defparam com_cmm_u_cmm_dataproducer_byte_07_27_0_1_iv_i_i_i_a2_3_.INIT = 8'h80; + LUT3 com_cmm_u_cmm_dataproducer_byte_07_27_0_1_iv_i_i_i_a2_3_ ( + .I0(com_cmm_u_cmm_dataproducer_req_gnt_code_0__295), + .I1(com_cmm_u_cmm_dataproducer_req_gnt_code[1]), + .I2(com_cmm_u_cmm_dataproducer_req_gnt_code[2]), + .O(com_cmm_u_cmm_dataproducer_N_50011) + ); + defparam com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_sn_m5_i_0_i_i_a3.INIT = 8'h80; + LUT3 com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_sn_m5_i_0_i_i_a3 ( + .I0(com_cmm_u_cmm_dataproducer_req_gnt_code[1]), + .I1(com_cmm_u_cmm_dataproducer_req_gnt_code[2]), + .I2(com_cmm_u_cmm_dataproducer_req_gnt_code_3__234), + .O(com_cmm_u_cmm_dataproducer_N_50471) + ); + defparam com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_ss0_0_o2_i_a4_0_a3_0_2.INIT = 8'h02; + LUT3 com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_ss0_0_o2_i_a4_0_a3_0_2 ( + .I0(com_cmm_req_valid), + .I1(com_cmm_u_cmm_dataproducer_req_gnt_code[2]), + .I2(com_cmm_u_cmm_dataproducer_req_gnt_code_3__234), + .O(com_cmm_u_cmm_dataproducer_N_50468_2) + ); + defparam com_cmm_u_cmm_dataproducer_byte_01_20_i_0_i_a2_i_o3_4_.INIT = 8'h02; + LUT3 com_cmm_u_cmm_dataproducer_byte_01_20_i_0_i_a2_i_o3_4_ ( + .I0(com_cmm_u_cmm_dataproducer_req_gnt_code[1]), + .I1(com_cmm_u_cmm_dataproducer_req_gnt_code[2]), + .I2(com_cmm_u_cmm_dataproducer_req_gnt_code_3__234), + .O(com_cmm_u_cmm_dataproducer_N_48879_i) + ); + defparam com_cmm_u_cmm_dataproducer_byte_00_19_i_i_0_0_i_a2_5_.INIT = 8'h4C; + LUT3 com_cmm_u_cmm_dataproducer_byte_00_19_i_i_0_0_i_a2_5_ ( + .I0(com_cmm_u_cmm_dataproducer_req_gnt_code[1]), + .I1(com_cmm_u_cmm_dataproducer_req_gnt_code[2]), + .I2(com_cmm_u_cmm_dataproducer_req_gnt_code_3__234), + .O(com_cmm_u_cmm_dataproducer_byte_00_19_i_i_0_0_i_a2[5]) + ); + defparam com_cmm_u_cmm_dataproducer_req_gnt_code_8_i_0_0_0_o3_2_.INIT = 8'h08; + LUT3 com_cmm_u_cmm_dataproducer_req_gnt_code_8_i_0_0_0_o3_2_ ( + .I0(com_cmm_req_arbiter[3]), + .I1(com_cmm_u_cmm_dataproducer_pcie_link_state_d[0]), + .I2(com_cmm_u_cmm_dataproducer_req_gnt_state[1]), + .O(com_cmm_u_cmm_dataproducer_req_gnt_code_8_i_0_0_0_o3[2]) + ); + defparam com_cmm_u_cmm_dataproducer_byte_07_27_0_1_iv_i_0_i_i_a2_0_2_.INIT = 8'h02; + LUT3 com_cmm_u_cmm_dataproducer_byte_07_27_0_1_iv_i_0_i_i_a2_0_2_ ( + .I0(com_cmm_u_cmm_dataproducer_req_gnt_code_0__295), + .I1(com_cmm_u_cmm_dataproducer_req_gnt_code[1]), + .I2(com_cmm_u_cmm_dataproducer_req_gnt_code[2]), + .O(com_cmm_u_cmm_dataproducer_N_50007) + ); + defparam com_cmm_u_cmm_dataproducer_req_gnt_code_8_i_0_0_0_1_3_.INIT = 16'h000E; + LUT4 com_cmm_u_cmm_dataproducer_req_gnt_code_8_i_0_0_0_1_3_ ( + .I0(com_cmm_req_arbiter[3]), + .I1(com_cmm_req_cfgctrl), + .I2(com_cmm_u_cmm_dataproducer_req_gnt_state[0]), + .I3(com_cmm_u_cmm_dataproducer_req_gnt_state[1]), + .O(com_cmm_u_cmm_dataproducer_req_gnt_code_8_i_0_0_0_1[3]) + ); + defparam com_cmm_u_cmm_dataproducer_un1_nxt_req_gnt_state36_1_0_0_0_0.INIT = 16'h00AC; + LUT4 com_cmm_u_cmm_dataproducer_un1_nxt_req_gnt_state36_1_0_0_0_0 ( + .I0(com_gnt_pkt_tx), + .I1(com_cmm_u_cmm_dataproducer_pcie_link_state_d[0]), + .I2(com_cmm_u_cmm_dataproducer_req_gnt_state[0]), + .I3(com_cmm_u_cmm_dataproducer_req_gnt_state[1]), + .O(com_cmm_u_cmm_dataproducer_N_9377_i) + ); + defparam com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_a2_0_a2_0_a2_2_1_.INIT = 4'h8; + LUT2 com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_a2_0_a2_0_a2_2_1_ ( + .I0(com_cmm_u_cmm_dataproducer_N_50468_1), + .I1(com_cmm_u_cmm_dataproducer_N_50468_2), + .O(com_cmm_u_cmm_dataproducer_N_50468_3) + ); + defparam com_cmm_u_cmm_dataproducer_byte_01_20_i_0_i_a2_i_o2_4_.INIT = 8'h28; + LUT3 com_cmm_u_cmm_dataproducer_byte_01_20_i_0_i_a2_i_o2_4_ ( + .I0(com_cmm_u_cmm_dataproducer_N_48879_i), + .I1(com_cmm_data_errmanager[48]), + .I2(com_cmm_data_errmanager[49]), + .O(com_cmm_u_cmm_dataproducer_N_48969_i) + ); + defparam com_cmm_u_cmm_dataproducer_byte_07_27_0_1_iv_i_0_0_0_o2_0_.INIT = 16'h1555; + LUT4 com_cmm_u_cmm_dataproducer_byte_07_27_0_1_iv_i_0_0_0_o2_0_ ( + .I0(com_cmm_u_cmm_dataproducer_N_50471), + .I1(N_50505_1), + .I2(com_cmm_u_cmm_dataproducer_req_gnt_code_0__295), + .I3(com_cmm_u_cmm_dataproducer_req_gnt_code[2]), + .O(com_cmm_u_cmm_dataproducer_N_48950_i) + ); + defparam com_cmm_u_cmm_dataproducer_byte_08_17_3_0_0_0_a3_0_0_.INIT = 4'h2; + LUT2 com_cmm_u_cmm_dataproducer_byte_08_17_3_0_0_0_a3_0_0_ ( + .I0(com_cmm_u_cmm_dataproducer_N_50471), + .I1(com_cmm_u_cmm_dataproducer_req_gnt_code_0__295), + .O(com_cmm_u_cmm_dataproducer_N_50482) + ); + defparam com_cmm_u_cmm_dataproducer_byte_08_17_3_0_0_0_a3_0_.INIT = 4'h8; + LUT2 com_cmm_u_cmm_dataproducer_byte_08_17_3_0_0_0_a3_0_ ( + .I0(com_cmm_u_cmm_dataproducer_N_50471), + .I1(com_cmm_u_cmm_dataproducer_req_gnt_code_0__295), + .O(com_cmm_u_cmm_dataproducer_N_50481) + ); + defparam com_cmm_u_cmm_dataproducer_N_3727_i_0_a2_0_a3_i_0_i_a3.INIT = 16'h020E; + LUT4 com_cmm_u_cmm_dataproducer_N_3727_i_0_a2_0_a3_i_0_i_a3 ( + .I0(com_cmm_u_cmm_dataproducer_req_gnt_code_0__295), + .I1(com_cmm_u_cmm_dataproducer_req_gnt_code[1]), + .I2(com_cmm_u_cmm_dataproducer_req_gnt_code[2]), + .I3(com_cmm_u_cmm_dataproducer_req_gnt_code_3__234), + .O(com_cmm_u_cmm_dataproducer_N_3727_i_0_a2_0_a3_i_0_i_a3_5050) + ); + defparam com_cmm_u_cmm_dataproducer_byte_07_27_0_1_iv_i_0_0_0_a2_1_5_.INIT = 4'h8; + LUT2_L com_cmm_u_cmm_dataproducer_byte_07_27_0_1_iv_i_0_0_0_a2_1_5_ ( + .I0(com_cmm_u_cmm_dataproducer_N_48879_i), + .I1(com_cmm_data_errmanager[34]), + .LO(com_cmm_u_cmm_dataproducer_N_49560) + ); + defparam com_cmm_u_cmm_dataproducer_byte_04_17_i_0_0_0_a2_0_.INIT = 16'h0D01; + LUT4 com_cmm_u_cmm_dataproducer_byte_04_17_i_0_0_0_a2_0_ ( + .I0(com_cmm_u_cmm_dataproducer_req_gnt_code_0__295), + .I1(com_cmm_u_cmm_dataproducer_req_gnt_code[1]), + .I2(com_cmm_u_cmm_dataproducer_req_gnt_code[2]), + .I3(com_cmm_u_cmm_dataproducer_req_gnt_code_3__234), + .O(com_cmm_u_cmm_dataproducer_byte_04_17_i_0_0_0_a2[0]) + ); + defparam com_cmm_u_cmm_dataproducer_byte_07_27_0_1_iv_i_0_0_0_a2_0_0_.INIT = 4'h8; + LUT2 com_cmm_u_cmm_dataproducer_byte_07_27_0_1_iv_i_0_0_0_a2_0_0_ ( + .I0(com_cmm_u_cmm_dataproducer_N_48879_i), + .I1(com_cmm_data_errmanager[29]), + .O(com_cmm_u_cmm_dataproducer_N_49550) + ); + defparam com_cmm_u_cmm_dataproducer_byte_06_21_iv_i_0_0_0_a2_5_.INIT = 4'h8; + LUT2_L com_cmm_u_cmm_dataproducer_byte_06_21_iv_i_0_0_0_a2_5_ ( + .I0(com_cmm_u_cmm_dataproducer_N_50007), + .I1(com_cmm_u_cmm_dataproducer_req_gnt_code_3__234), + .LO(com_cmm_u_cmm_dataproducer_N_49561) + ); + defparam com_cmm_u_cmm_dataproducer_byte_11_17_m0_0_a2_i_0_0_o2_0_.INIT = 16'h800C; + LUT4 com_cmm_u_cmm_dataproducer_byte_11_17_m0_0_a2_i_0_0_o2_0_ ( + .I0(com_cmm_u_cmm_dataproducer_req_gnt_code_0__295), + .I1(com_cmm_u_cmm_dataproducer_req_gnt_code[1]), + .I2(com_cmm_u_cmm_dataproducer_req_gnt_code[2]), + .I3(com_cmm_u_cmm_dataproducer_req_gnt_code_3__234), + .O(com_cmm_u_cmm_dataproducer_byte_11_17_m0_0_a2_i_0_0_o2[0]) + ); + defparam com_cmm_u_cmm_dataproducer_req_gnt_state_4s2_i_0_0_0_a2_0.INIT = 16'h0002; + LUT4_L com_cmm_u_cmm_dataproducer_req_gnt_state_4s2_i_0_0_0_a2_0 ( + .I0(com_cmm_u_cmm_dataproducer_N_48988_i), + .I1(com_cmm_req_arbiter[0]), + .I2(com_cmm_req_arbiter[3]), + .I3(com_cmm_u_cmm_dataproducer_req_gnt_state[0]), + .LO(com_cmm_u_cmm_dataproducer_N_49542) + ); + defparam com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_sn_m5_i_0_i_i_a2.INIT = 16'h8000; + LUT4 com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_sn_m5_i_0_i_i_a2 ( + .I0(com_cmm_u_cmm_dataproducer_N_50468_1), + .I1(com_cmm_u_cmm_dataproducer_N_50468_2), + .I2(com_cmm_req_cfgctrl), + .I3(com_cmm_u_cmm_dataproducer_req_gnt_code_0__295), + .O(com_cmm_u_cmm_dataproducer_N_50009) + ); + defparam com_cmm_u_cmm_dataproducer_byte_10_17_i_i_0_0_a2_0_3_.INIT = 4'h8; + LUT2_L com_cmm_u_cmm_dataproducer_byte_10_17_i_i_0_0_a2_0_3_ ( + .I0(com_cmm_u_cmm_dataproducer_N_50482), + .I1(com_cmm_msi_laddr[11]), + .LO(com_cmm_u_cmm_dataproducer_N_49681) + ); + defparam com_cmm_u_cmm_dataproducer_byte_10_17_i_i_0_0_a2_3_.INIT = 16'h88A0; + LUT4 com_cmm_u_cmm_dataproducer_byte_10_17_i_i_0_0_a2_3_ ( + .I0(com_cmm_u_cmm_dataproducer_N_3727_i_0_a2_0_a3_i_0_i_a3_5050), + .I1(com_cmm_data_errmanager[3]), + .I2(com_cmm_tag[3]), + .I3(com_cmm_u_cmm_dataproducer_req_gnt_code[1]), + .O(com_cmm_u_cmm_dataproducer_N_49680) + ); + defparam com_cmm_u_cmm_dataproducer_byte_10_17_i_i_0_0_a2_0_7_.INIT = 4'h8; + LUT2_L com_cmm_u_cmm_dataproducer_byte_10_17_i_i_0_0_a2_0_7_ ( + .I0(com_cmm_u_cmm_dataproducer_N_50482), + .I1(com_cmm_msi_laddr[15]), + .LO(com_cmm_u_cmm_dataproducer_N_49678) + ); + defparam com_cmm_u_cmm_dataproducer_byte_10_17_i_i_0_0_a2_7_.INIT = 16'h88A0; + LUT4 com_cmm_u_cmm_dataproducer_byte_10_17_i_i_0_0_a2_7_ ( + .I0(com_cmm_u_cmm_dataproducer_N_3727_i_0_a2_0_a3_i_0_i_a3_5050), + .I1(com_cmm_data_errmanager[7]), + .I2(com_cmm_tag[7]), + .I3(com_cmm_u_cmm_dataproducer_req_gnt_code[1]), + .O(com_cmm_u_cmm_dataproducer_N_49677) + ); + defparam com_cmm_u_cmm_dataproducer_byte_10_17_3_0_0_0_a2_0_6_.INIT = 4'h8; + LUT2_L com_cmm_u_cmm_dataproducer_byte_10_17_3_0_0_0_a2_0_6_ ( + .I0(com_cmm_u_cmm_dataproducer_N_50482), + .I1(com_cmm_msi_laddr[14]), + .LO(com_cmm_u_cmm_dataproducer_N_49304) + ); + defparam com_cmm_u_cmm_dataproducer_byte_10_17_3_0_0_0_a2_6_.INIT = 16'h88A0; + LUT4 com_cmm_u_cmm_dataproducer_byte_10_17_3_0_0_0_a2_6_ ( + .I0(com_cmm_u_cmm_dataproducer_N_3727_i_0_a2_0_a3_i_0_i_a3_5050), + .I1(com_cmm_data_errmanager[6]), + .I2(com_cmm_tag[6]), + .I3(com_cmm_u_cmm_dataproducer_req_gnt_code[1]), + .O(com_cmm_u_cmm_dataproducer_N_49303) + ); + defparam com_cmm_u_cmm_dataproducer_byte_10_17_1_0_0_a2_0_5_.INIT = 4'h8; + LUT2_L com_cmm_u_cmm_dataproducer_byte_10_17_1_0_0_a2_0_5_ ( + .I0(com_cmm_u_cmm_dataproducer_N_50482), + .I1(com_cmm_msi_laddr[13]), + .LO(com_cmm_u_cmm_dataproducer_N_49301) + ); + defparam com_cmm_u_cmm_dataproducer_byte_10_17_1_0_0_a2_5_.INIT = 16'h88A0; + LUT4 com_cmm_u_cmm_dataproducer_byte_10_17_1_0_0_a2_5_ ( + .I0(com_cmm_u_cmm_dataproducer_N_3727_i_0_a2_0_a3_i_0_i_a3_5050), + .I1(com_cmm_data_errmanager[5]), + .I2(com_cmm_tag[5]), + .I3(com_cmm_u_cmm_dataproducer_req_gnt_code[1]), + .O(com_cmm_u_cmm_dataproducer_N_49300) + ); + defparam com_cmm_u_cmm_dataproducer_byte_10_17_1_0_0_a2_0_4_.INIT = 4'h8; + LUT2_L com_cmm_u_cmm_dataproducer_byte_10_17_1_0_0_a2_0_4_ ( + .I0(com_cmm_u_cmm_dataproducer_N_50482), + .I1(com_cmm_msi_laddr[12]), + .LO(com_cmm_u_cmm_dataproducer_N_49298) + ); + defparam com_cmm_u_cmm_dataproducer_byte_10_17_1_0_0_a2_4_.INIT = 16'h88A0; + LUT4 com_cmm_u_cmm_dataproducer_byte_10_17_1_0_0_a2_4_ ( + .I0(com_cmm_u_cmm_dataproducer_N_3727_i_0_a2_0_a3_i_0_i_a3_5050), + .I1(com_cmm_data_errmanager[4]), + .I2(com_cmm_tag[4]), + .I3(com_cmm_u_cmm_dataproducer_req_gnt_code[1]), + .O(com_cmm_u_cmm_dataproducer_N_49297) + ); + defparam com_cmm_u_cmm_dataproducer_byte_10_17_3_0_0_0_a2_0_2_.INIT = 4'h8; + LUT2_L com_cmm_u_cmm_dataproducer_byte_10_17_3_0_0_0_a2_0_2_ ( + .I0(com_cmm_u_cmm_dataproducer_N_50482), + .I1(com_cmm_msi_laddr[10]), + .LO(com_cmm_u_cmm_dataproducer_N_49295) + ); + defparam com_cmm_u_cmm_dataproducer_byte_10_17_3_0_0_0_a2_2_.INIT = 16'h88A0; + LUT4 com_cmm_u_cmm_dataproducer_byte_10_17_3_0_0_0_a2_2_ ( + .I0(com_cmm_u_cmm_dataproducer_N_3727_i_0_a2_0_a3_i_0_i_a3_5050), + .I1(com_cmm_data_errmanager[2]), + .I2(com_cmm_tag[2]), + .I3(com_cmm_u_cmm_dataproducer_req_gnt_code[1]), + .O(com_cmm_u_cmm_dataproducer_N_49294) + ); + defparam com_cmm_u_cmm_dataproducer_byte_10_17_3_0_0_0_a2_0_1_.INIT = 4'h8; + LUT2_L com_cmm_u_cmm_dataproducer_byte_10_17_3_0_0_0_a2_0_1_ ( + .I0(com_cmm_u_cmm_dataproducer_N_50482), + .I1(com_cmm_msi_laddr[9]), + .LO(com_cmm_u_cmm_dataproducer_N_49292) + ); + defparam com_cmm_u_cmm_dataproducer_byte_10_17_3_0_0_0_a2_1_.INIT = 16'h88A0; + LUT4 com_cmm_u_cmm_dataproducer_byte_10_17_3_0_0_0_a2_1_ ( + .I0(com_cmm_u_cmm_dataproducer_N_3727_i_0_a2_0_a3_i_0_i_a3_5050), + .I1(com_cmm_data_errmanager[1]), + .I2(com_cmm_tag[1]), + .I3(com_cmm_u_cmm_dataproducer_req_gnt_code[1]), + .O(com_cmm_u_cmm_dataproducer_N_49291) + ); + defparam com_cmm_u_cmm_dataproducer_byte_10_17_3_0_0_0_a2_0_0_.INIT = 4'h8; + LUT2_L com_cmm_u_cmm_dataproducer_byte_10_17_3_0_0_0_a2_0_0_ ( + .I0(com_cmm_u_cmm_dataproducer_N_50482), + .I1(com_cmm_msi_laddr[8]), + .LO(com_cmm_u_cmm_dataproducer_N_49289) + ); + defparam com_cmm_u_cmm_dataproducer_byte_10_17_3_0_0_0_a2_0_.INIT = 16'h88A0; + LUT4 com_cmm_u_cmm_dataproducer_byte_10_17_3_0_0_0_a2_0_ ( + .I0(com_cmm_u_cmm_dataproducer_N_3727_i_0_a2_0_a3_i_0_i_a3_5050), + .I1(com_cmm_data_errmanager[0]), + .I2(com_cmm_tag[0]), + .I3(com_cmm_u_cmm_dataproducer_req_gnt_code[1]), + .O(com_cmm_u_cmm_dataproducer_N_49288) + ); + defparam com_cmm_u_cmm_dataproducer_byte_09_17_3_0_0_0_a2_1_7_.INIT = 4'h8; + LUT2_L com_cmm_u_cmm_dataproducer_byte_09_17_3_0_0_0_a2_1_7_ ( + .I0(com_cmm_u_cmm_dataproducer_N_50482), + .I1(com_cmm_msi_laddr[23]), + .LO(com_cmm_u_cmm_dataproducer_N_49287) + ); + defparam com_cmm_u_cmm_dataproducer_byte_09_17_3_0_0_0_a2_7_.INIT = 16'h88A0; + LUT4 com_cmm_u_cmm_dataproducer_byte_09_17_3_0_0_0_a2_7_ ( + .I0(com_cmm_u_cmm_dataproducer_N_3727_i_0_a2_0_a3_i_0_i_a3_5050), + .I1(com_cmm_data_errmanager[15]), + .I2(com_cmm_req_id[7]), + .I3(com_cmm_u_cmm_dataproducer_req_gnt_code[1]), + .O(com_cmm_u_cmm_dataproducer_N_49285) + ); + defparam com_cmm_u_cmm_dataproducer_byte_09_17_3_0_0_0_a2_1_6_.INIT = 4'h8; + LUT2_L com_cmm_u_cmm_dataproducer_byte_09_17_3_0_0_0_a2_1_6_ ( + .I0(com_cmm_u_cmm_dataproducer_N_50482), + .I1(com_cmm_msi_laddr[22]), + .LO(com_cmm_u_cmm_dataproducer_N_49284) + ); + defparam com_cmm_u_cmm_dataproducer_byte_09_17_3_0_0_0_a2_6_.INIT = 16'h88A0; + LUT4 com_cmm_u_cmm_dataproducer_byte_09_17_3_0_0_0_a2_6_ ( + .I0(com_cmm_u_cmm_dataproducer_N_3727_i_0_a2_0_a3_i_0_i_a3_5050), + .I1(com_cmm_data_errmanager[14]), + .I2(com_cmm_req_id[6]), + .I3(com_cmm_u_cmm_dataproducer_req_gnt_code[1]), + .O(com_cmm_u_cmm_dataproducer_N_49282) + ); + defparam com_cmm_u_cmm_dataproducer_byte_09_17_3_0_0_0_a2_1_5_.INIT = 4'h8; + LUT2_L com_cmm_u_cmm_dataproducer_byte_09_17_3_0_0_0_a2_1_5_ ( + .I0(com_cmm_u_cmm_dataproducer_N_50482), + .I1(com_cmm_msi_laddr[21]), + .LO(com_cmm_u_cmm_dataproducer_N_49281) + ); + defparam com_cmm_u_cmm_dataproducer_byte_09_17_3_0_0_0_a2_5_.INIT = 16'h88A0; + LUT4 com_cmm_u_cmm_dataproducer_byte_09_17_3_0_0_0_a2_5_ ( + .I0(com_cmm_u_cmm_dataproducer_N_3727_i_0_a2_0_a3_i_0_i_a3_5050), + .I1(com_cmm_data_errmanager[13]), + .I2(com_cmm_req_id[5]), + .I3(com_cmm_u_cmm_dataproducer_req_gnt_code[1]), + .O(com_cmm_u_cmm_dataproducer_N_49279) + ); + defparam com_cmm_u_cmm_dataproducer_byte_09_17_3_0_0_0_a2_1_4_.INIT = 4'h8; + LUT2_L com_cmm_u_cmm_dataproducer_byte_09_17_3_0_0_0_a2_1_4_ ( + .I0(com_cmm_u_cmm_dataproducer_N_50482), + .I1(com_cmm_msi_laddr[20]), + .LO(com_cmm_u_cmm_dataproducer_N_49278) + ); + defparam com_cmm_u_cmm_dataproducer_byte_09_17_3_0_0_0_a2_4_.INIT = 16'h88A0; + LUT4 com_cmm_u_cmm_dataproducer_byte_09_17_3_0_0_0_a2_4_ ( + .I0(com_cmm_u_cmm_dataproducer_N_3727_i_0_a2_0_a3_i_0_i_a3_5050), + .I1(com_cmm_data_errmanager[12]), + .I2(com_cmm_req_id[4]), + .I3(com_cmm_u_cmm_dataproducer_req_gnt_code[1]), + .O(com_cmm_u_cmm_dataproducer_N_49276) + ); + defparam com_cmm_u_cmm_dataproducer_byte_09_17_3_0_0_0_a2_1_3_.INIT = 4'h8; + LUT2_L com_cmm_u_cmm_dataproducer_byte_09_17_3_0_0_0_a2_1_3_ ( + .I0(com_cmm_u_cmm_dataproducer_N_50482), + .I1(com_cmm_msi_laddr[19]), + .LO(com_cmm_u_cmm_dataproducer_N_49275) + ); + defparam com_cmm_u_cmm_dataproducer_byte_09_17_3_0_0_0_a2_3_.INIT = 16'h88A0; + LUT4 com_cmm_u_cmm_dataproducer_byte_09_17_3_0_0_0_a2_3_ ( + .I0(com_cmm_u_cmm_dataproducer_N_3727_i_0_a2_0_a3_i_0_i_a3_5050), + .I1(com_cmm_data_errmanager[11]), + .I2(com_cmm_req_id[3]), + .I3(com_cmm_u_cmm_dataproducer_req_gnt_code[1]), + .O(com_cmm_u_cmm_dataproducer_N_49273) + ); + defparam com_cmm_u_cmm_dataproducer_byte_09_17_3_0_0_0_a2_1_2_.INIT = 4'h8; + LUT2_L com_cmm_u_cmm_dataproducer_byte_09_17_3_0_0_0_a2_1_2_ ( + .I0(com_cmm_u_cmm_dataproducer_N_50482), + .I1(com_cmm_msi_laddr[18]), + .LO(com_cmm_u_cmm_dataproducer_N_49272) + ); + defparam com_cmm_u_cmm_dataproducer_byte_09_17_3_0_0_0_a2_2_.INIT = 16'h88A0; + LUT4 com_cmm_u_cmm_dataproducer_byte_09_17_3_0_0_0_a2_2_ ( + .I0(com_cmm_u_cmm_dataproducer_N_3727_i_0_a2_0_a3_i_0_i_a3_5050), + .I1(com_cmm_data_errmanager[10]), + .I2(com_cmm_req_id[2]), + .I3(com_cmm_u_cmm_dataproducer_req_gnt_code[1]), + .O(com_cmm_u_cmm_dataproducer_N_49270) + ); + defparam com_cmm_u_cmm_dataproducer_byte_09_17_3_0_0_0_a2_1_1_.INIT = 4'h8; + LUT2_L com_cmm_u_cmm_dataproducer_byte_09_17_3_0_0_0_a2_1_1_ ( + .I0(com_cmm_u_cmm_dataproducer_N_50482), + .I1(com_cmm_msi_laddr[17]), + .LO(com_cmm_u_cmm_dataproducer_N_49269) + ); + defparam com_cmm_u_cmm_dataproducer_byte_09_17_3_0_0_0_a2_1_.INIT = 16'h88A0; + LUT4 com_cmm_u_cmm_dataproducer_byte_09_17_3_0_0_0_a2_1_ ( + .I0(com_cmm_u_cmm_dataproducer_N_3727_i_0_a2_0_a3_i_0_i_a3_5050), + .I1(com_cmm_data_errmanager[9]), + .I2(com_cmm_req_id[1]), + .I3(com_cmm_u_cmm_dataproducer_req_gnt_code[1]), + .O(com_cmm_u_cmm_dataproducer_N_49267) + ); + defparam com_cmm_u_cmm_dataproducer_byte_09_17_3_0_0_0_a2_0_0_.INIT = 4'h8; + LUT2_L com_cmm_u_cmm_dataproducer_byte_09_17_3_0_0_0_a2_0_0_ ( + .I0(com_cmm_u_cmm_dataproducer_N_50482), + .I1(com_cmm_msi_laddr[16]), + .LO(com_cmm_u_cmm_dataproducer_N_49265) + ); + defparam com_cmm_u_cmm_dataproducer_byte_09_17_3_0_0_0_a2_0_.INIT = 16'h88A0; + LUT4 com_cmm_u_cmm_dataproducer_byte_09_17_3_0_0_0_a2_0_ ( + .I0(com_cmm_u_cmm_dataproducer_N_3727_i_0_a2_0_a3_i_0_i_a3_5050), + .I1(com_cmm_data_errmanager[8]), + .I2(com_cmm_req_id[0]), + .I3(com_cmm_u_cmm_dataproducer_req_gnt_code[1]), + .O(com_cmm_u_cmm_dataproducer_N_49264) + ); + defparam com_cmm_u_cmm_dataproducer_byte_08_17_3_0_0_0_a2_1_7_.INIT = 4'h8; + LUT2_L com_cmm_u_cmm_dataproducer_byte_08_17_3_0_0_0_a2_1_7_ ( + .I0(com_cmm_u_cmm_dataproducer_N_50482), + .I1(com_cmm_msi_laddr[31]), + .LO(com_cmm_u_cmm_dataproducer_N_49263) + ); + defparam com_cmm_u_cmm_dataproducer_byte_08_17_3_0_0_0_a2_7_.INIT = 16'h88A0; + LUT4 com_cmm_u_cmm_dataproducer_byte_08_17_3_0_0_0_a2_7_ ( + .I0(com_cmm_u_cmm_dataproducer_N_3727_i_0_a2_0_a3_i_0_i_a3_5050), + .I1(com_cmm_data_errmanager[23]), + .I2(com_cmm_req_id[15]), + .I3(com_cmm_u_cmm_dataproducer_req_gnt_code[1]), + .O(com_cmm_u_cmm_dataproducer_N_49261) + ); + defparam com_cmm_u_cmm_dataproducer_byte_08_17_3_0_0_0_a2_1_6_.INIT = 4'h8; + LUT2_L com_cmm_u_cmm_dataproducer_byte_08_17_3_0_0_0_a2_1_6_ ( + .I0(com_cmm_u_cmm_dataproducer_N_50482), + .I1(com_cmm_msi_laddr[30]), + .LO(com_cmm_u_cmm_dataproducer_N_49260) + ); + defparam com_cmm_u_cmm_dataproducer_byte_08_17_3_0_0_0_a2_6_.INIT = 16'h88A0; + LUT4 com_cmm_u_cmm_dataproducer_byte_08_17_3_0_0_0_a2_6_ ( + .I0(com_cmm_u_cmm_dataproducer_N_3727_i_0_a2_0_a3_i_0_i_a3_5050), + .I1(com_cmm_data_errmanager[22]), + .I2(com_cmm_req_id[14]), + .I3(com_cmm_u_cmm_dataproducer_req_gnt_code[1]), + .O(com_cmm_u_cmm_dataproducer_N_49258) + ); + defparam com_cmm_u_cmm_dataproducer_byte_08_17_3_0_0_0_a2_1_5_.INIT = 4'h8; + LUT2_L com_cmm_u_cmm_dataproducer_byte_08_17_3_0_0_0_a2_1_5_ ( + .I0(com_cmm_u_cmm_dataproducer_N_50482), + .I1(com_cmm_msi_laddr[29]), + .LO(com_cmm_u_cmm_dataproducer_N_49257) + ); + defparam com_cmm_u_cmm_dataproducer_byte_08_17_3_0_0_0_a2_5_.INIT = 16'h88A0; + LUT4 com_cmm_u_cmm_dataproducer_byte_08_17_3_0_0_0_a2_5_ ( + .I0(com_cmm_u_cmm_dataproducer_N_3727_i_0_a2_0_a3_i_0_i_a3_5050), + .I1(com_cmm_data_errmanager[21]), + .I2(com_cmm_req_id[13]), + .I3(com_cmm_u_cmm_dataproducer_req_gnt_code[1]), + .O(com_cmm_u_cmm_dataproducer_N_49255) + ); + defparam com_cmm_u_cmm_dataproducer_byte_08_17_3_0_0_0_a2_1_4_.INIT = 4'h8; + LUT2_L com_cmm_u_cmm_dataproducer_byte_08_17_3_0_0_0_a2_1_4_ ( + .I0(com_cmm_u_cmm_dataproducer_N_50482), + .I1(com_cmm_msi_laddr[28]), + .LO(com_cmm_u_cmm_dataproducer_N_49254) + ); + defparam com_cmm_u_cmm_dataproducer_byte_08_17_3_0_0_0_a2_4_.INIT = 16'h88A0; + LUT4 com_cmm_u_cmm_dataproducer_byte_08_17_3_0_0_0_a2_4_ ( + .I0(com_cmm_u_cmm_dataproducer_N_3727_i_0_a2_0_a3_i_0_i_a3_5050), + .I1(com_cmm_data_errmanager[20]), + .I2(com_cmm_req_id[12]), + .I3(com_cmm_u_cmm_dataproducer_req_gnt_code[1]), + .O(com_cmm_u_cmm_dataproducer_N_49252) + ); + defparam com_cmm_u_cmm_dataproducer_byte_08_17_3_0_0_0_a2_0_3_.INIT = 4'h8; + LUT2_L com_cmm_u_cmm_dataproducer_byte_08_17_3_0_0_0_a2_0_3_ ( + .I0(com_cmm_u_cmm_dataproducer_N_50482), + .I1(com_cmm_msi_laddr[27]), + .LO(com_cmm_u_cmm_dataproducer_N_49250) + ); + defparam com_cmm_u_cmm_dataproducer_byte_08_17_3_0_0_0_a2_3_.INIT = 16'h88A0; + LUT4 com_cmm_u_cmm_dataproducer_byte_08_17_3_0_0_0_a2_3_ ( + .I0(com_cmm_u_cmm_dataproducer_N_3727_i_0_a2_0_a3_i_0_i_a3_5050), + .I1(com_cmm_data_errmanager[19]), + .I2(com_cmm_req_id[11]), + .I3(com_cmm_u_cmm_dataproducer_req_gnt_code[1]), + .O(com_cmm_u_cmm_dataproducer_N_49249) + ); + defparam com_cmm_u_cmm_dataproducer_byte_08_17_3_0_0_0_a2_1_2_.INIT = 4'h8; + LUT2_L com_cmm_u_cmm_dataproducer_byte_08_17_3_0_0_0_a2_1_2_ ( + .I0(com_cmm_u_cmm_dataproducer_N_50482), + .I1(com_cmm_msi_laddr[26]), + .LO(com_cmm_u_cmm_dataproducer_N_49248) + ); + defparam com_cmm_u_cmm_dataproducer_byte_08_17_3_0_0_0_a2_2_.INIT = 16'h88A0; + LUT4 com_cmm_u_cmm_dataproducer_byte_08_17_3_0_0_0_a2_2_ ( + .I0(com_cmm_u_cmm_dataproducer_N_3727_i_0_a2_0_a3_i_0_i_a3_5050), + .I1(com_cmm_data_errmanager[18]), + .I2(com_cmm_req_id[10]), + .I3(com_cmm_u_cmm_dataproducer_req_gnt_code[1]), + .O(com_cmm_u_cmm_dataproducer_N_49246) + ); + defparam com_cmm_u_cmm_dataproducer_byte_08_17_3_0_0_0_a2_1_1_.INIT = 4'h8; + LUT2_L com_cmm_u_cmm_dataproducer_byte_08_17_3_0_0_0_a2_1_1_ ( + .I0(com_cmm_u_cmm_dataproducer_N_50482), + .I1(com_cmm_msi_laddr[25]), + .LO(com_cmm_u_cmm_dataproducer_N_49245) + ); + defparam com_cmm_u_cmm_dataproducer_byte_08_17_3_0_0_0_a2_1_.INIT = 16'h88A0; + LUT4 com_cmm_u_cmm_dataproducer_byte_08_17_3_0_0_0_a2_1_ ( + .I0(com_cmm_u_cmm_dataproducer_N_3727_i_0_a2_0_a3_i_0_i_a3_5050), + .I1(com_cmm_data_errmanager[17]), + .I2(com_cmm_req_id[9]), + .I3(com_cmm_u_cmm_dataproducer_req_gnt_code[1]), + .O(com_cmm_u_cmm_dataproducer_N_49243) + ); + defparam com_cmm_u_cmm_dataproducer_byte_08_17_3_0_0_0_a2_1_0_.INIT = 4'h8; + LUT2_L com_cmm_u_cmm_dataproducer_byte_08_17_3_0_0_0_a2_1_0_ ( + .I0(com_cmm_u_cmm_dataproducer_N_50482), + .I1(com_cmm_msi_laddr[24]), + .LO(com_cmm_u_cmm_dataproducer_N_49242) + ); + defparam com_cmm_u_cmm_dataproducer_byte_08_17_3_0_0_0_a2_0_.INIT = 16'h88A0; + LUT4 com_cmm_u_cmm_dataproducer_byte_08_17_3_0_0_0_a2_0_ ( + .I0(com_cmm_u_cmm_dataproducer_N_3727_i_0_a2_0_a3_i_0_i_a3_5050), + .I1(com_cmm_data_errmanager[16]), + .I2(com_cmm_req_id[8]), + .I3(com_cmm_u_cmm_dataproducer_req_gnt_code[1]), + .O(com_cmm_u_cmm_dataproducer_N_49240) + ); + defparam com_cmm_u_cmm_dataproducer_byte_11_17_m0_0_2_.INIT = 8'hD8; + LUT3_L com_cmm_u_cmm_dataproducer_byte_11_17_m0_0_2_ ( + .I0(com_cmm_u_cmm_dataproducer_byte_11_17_m0_0_a2_i_0_0_o2[0]), + .I1(com_cmm_msi_haddr[2]), + .I2(com_cmm_msi_laddr[2]), + .LO(com_cmm_u_cmm_dataproducer_byte_11_17_m0[2]) + ); + defparam com_cmm_u_cmm_dataproducer_byte_11_17_m0_0_3_.INIT = 8'hD8; + LUT3_L com_cmm_u_cmm_dataproducer_byte_11_17_m0_0_3_ ( + .I0(com_cmm_u_cmm_dataproducer_byte_11_17_m0_0_a2_i_0_0_o2[0]), + .I1(com_cmm_msi_haddr[3]), + .I2(com_cmm_msi_laddr[3]), + .LO(com_cmm_u_cmm_dataproducer_byte_11_17_m0[3]) + ); + defparam com_cmm_u_cmm_dataproducer_byte_11_17_m0_0_4_.INIT = 8'hD8; + LUT3_L com_cmm_u_cmm_dataproducer_byte_11_17_m0_0_4_ ( + .I0(com_cmm_u_cmm_dataproducer_byte_11_17_m0_0_a2_i_0_0_o2[0]), + .I1(com_cmm_msi_haddr[4]), + .I2(com_cmm_msi_laddr[4]), + .LO(com_cmm_u_cmm_dataproducer_byte_11_17_m0[4]) + ); + defparam com_cmm_u_cmm_dataproducer_byte_11_17_m0_0_5_.INIT = 8'hD8; + LUT3_L com_cmm_u_cmm_dataproducer_byte_11_17_m0_0_5_ ( + .I0(com_cmm_u_cmm_dataproducer_byte_11_17_m0_0_a2_i_0_0_o2[0]), + .I1(com_cmm_msi_haddr[5]), + .I2(com_cmm_msi_laddr[5]), + .LO(com_cmm_u_cmm_dataproducer_byte_11_17_m0[5]) + ); + defparam com_cmm_u_cmm_dataproducer_byte_11_17_m0_0_6_.INIT = 8'hD8; + LUT3_L com_cmm_u_cmm_dataproducer_byte_11_17_m0_0_6_ ( + .I0(com_cmm_u_cmm_dataproducer_byte_11_17_m0_0_a2_i_0_0_o2[0]), + .I1(com_cmm_msi_haddr[6]), + .I2(com_cmm_msi_laddr[6]), + .LO(com_cmm_u_cmm_dataproducer_byte_11_17_m0[6]) + ); + defparam com_cmm_u_cmm_dataproducer_byte_11_17_0_am_1_.INIT = 4'h8; + LUT2 com_cmm_u_cmm_dataproducer_byte_11_17_0_am_1_ ( + .I0(com_cmm_u_cmm_dataproducer_byte_11_17_m0_0_a2_i_0_0_o2[0]), + .I1(com_cmm_data_errmanager[42]), + .O(com_cmm_u_cmm_dataproducer_byte_11_17_0_am[1]) + ); + defparam com_cmm_u_cmm_dataproducer_byte_11_17_0_bm_1_.INIT = 8'hE0; + LUT3 com_cmm_u_cmm_dataproducer_byte_11_17_0_bm_1_ ( + .I0(com_cmm_u_cmm_dataproducer_N_48879_i), + .I1(com_cmm_u_cmm_dataproducer_N_50481), + .I2(com_cmm_msi_haddr[1]), + .O(com_cmm_u_cmm_dataproducer_byte_11_17_0_bm[1]) + ); + MUXF5 com_cmm_u_cmm_dataproducer_byte_11_17_0_1_ ( + .I0(com_cmm_u_cmm_dataproducer_byte_11_17_0_am[1]), + .I1(com_cmm_u_cmm_dataproducer_byte_11_17_0_bm[1]), + .O(com_cmm_u_cmm_dataproducer_byte_11_17[1]), + .S(com_cmm_u_cmm_dataproducer_N_50471) + ); + defparam com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_am_2_.INIT = 16'h8000; + LUT4 com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_am_2_ ( + .I0(com_cmm_u_cmm_dataproducer_N_50468_3), + .I1(com_cmm_req_cfgctrl), + .I2(com_cmm_cfg_rd_data[26]), + .I3(com_cmm_u_cmm_dataproducer_req_gnt_code_0__295), + .O(com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_am[2]) + ); + defparam com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_bm_2_.INIT = 4'h8; + LUT2 com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_bm_2_ ( + .I0(com_cmm_msi_laddr[2]), + .I1(com_cmm_u_cmm_dataproducer_req_gnt_code_0__295), + .O(com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_bm[2]) + ); + MUXF5 com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_2_ ( + .I0(com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_am[2]), + .I1(com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_bm[2]), + .O(com_cmm_u_cmm_dataproducer_bytes_12_to_15_17[2]), + .S(com_cmm_u_cmm_dataproducer_N_50471) + ); + defparam com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_am_3_.INIT = 16'h8000; + LUT4 com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_am_3_ ( + .I0(com_cmm_u_cmm_dataproducer_N_50468_3), + .I1(com_cmm_req_cfgctrl), + .I2(com_cmm_cfg_rd_data[27]), + .I3(com_cmm_u_cmm_dataproducer_req_gnt_code_0__295), + .O(com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_am[3]) + ); + defparam com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_bm_3_.INIT = 4'h8; + LUT2 com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_bm_3_ ( + .I0(com_cmm_msi_laddr[3]), + .I1(com_cmm_u_cmm_dataproducer_req_gnt_code_0__295), + .O(com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_bm[3]) + ); + MUXF5 com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_3_ ( + .I0(com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_am[3]), + .I1(com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_bm[3]), + .O(com_cmm_u_cmm_dataproducer_bytes_12_to_15_17[3]), + .S(com_cmm_u_cmm_dataproducer_N_50471) + ); + defparam com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_am_4_.INIT = 16'h8000; + LUT4 com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_am_4_ ( + .I0(com_cmm_u_cmm_dataproducer_N_50468_3), + .I1(com_cmm_req_cfgctrl), + .I2(com_cmm_cfg_rd_data[28]), + .I3(com_cmm_u_cmm_dataproducer_req_gnt_code_0__295), + .O(com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_am[4]) + ); + defparam com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_bm_4_.INIT = 4'h8; + LUT2 com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_bm_4_ ( + .I0(com_cmm_msi_laddr[4]), + .I1(com_cmm_u_cmm_dataproducer_req_gnt_code_0__295), + .O(com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_bm[4]) + ); + MUXF5 com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_4_ ( + .I0(com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_am[4]), + .I1(com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_bm[4]), + .O(com_cmm_u_cmm_dataproducer_bytes_12_to_15_17[4]), + .S(com_cmm_u_cmm_dataproducer_N_50471) + ); + defparam com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_am_5_.INIT = 16'h8000; + LUT4 com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_am_5_ ( + .I0(com_cmm_u_cmm_dataproducer_N_50468_3), + .I1(com_cmm_req_cfgctrl), + .I2(com_cmm_cfg_rd_data[29]), + .I3(com_cmm_u_cmm_dataproducer_req_gnt_code_0__295), + .O(com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_am[5]) + ); + defparam com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_bm_5_.INIT = 4'h8; + LUT2 com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_bm_5_ ( + .I0(com_cmm_msi_laddr[5]), + .I1(com_cmm_u_cmm_dataproducer_req_gnt_code_0__295), + .O(com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_bm[5]) + ); + MUXF5 com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_5_ ( + .I0(com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_am[5]), + .I1(com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_bm[5]), + .O(com_cmm_u_cmm_dataproducer_bytes_12_to_15_17[5]), + .S(com_cmm_u_cmm_dataproducer_N_50471) + ); + defparam com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_am_6_.INIT = 16'h8000; + LUT4 com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_am_6_ ( + .I0(com_cmm_u_cmm_dataproducer_N_50468_3), + .I1(com_cmm_req_cfgctrl), + .I2(com_cmm_cfg_rd_data[30]), + .I3(com_cmm_u_cmm_dataproducer_req_gnt_code_0__295), + .O(com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_am[6]) + ); + defparam com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_bm_6_.INIT = 4'h8; + LUT2 com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_bm_6_ ( + .I0(com_cmm_msi_laddr[6]), + .I1(com_cmm_u_cmm_dataproducer_req_gnt_code_0__295), + .O(com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_bm[6]) + ); + MUXF5 com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_6_ ( + .I0(com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_am[6]), + .I1(com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_bm[6]), + .O(com_cmm_u_cmm_dataproducer_bytes_12_to_15_17[6]), + .S(com_cmm_u_cmm_dataproducer_N_50471) + ); + defparam com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_am_7_.INIT = 16'h8000; + LUT4 com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_am_7_ ( + .I0(com_cmm_u_cmm_dataproducer_N_50468_3), + .I1(com_cmm_req_cfgctrl), + .I2(com_cmm_cfg_rd_data[31]), + .I3(com_cmm_u_cmm_dataproducer_req_gnt_code_0__295), + .O(com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_am[7]) + ); + defparam com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_bm_7_.INIT = 4'h8; + LUT2 com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_bm_7_ ( + .I0(com_cmm_msi_laddr[7]), + .I1(com_cmm_u_cmm_dataproducer_req_gnt_code_0__295), + .O(com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_bm[7]) + ); + MUXF5 com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_7_ ( + .I0(com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_am[7]), + .I1(com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_bm[7]), + .O(com_cmm_u_cmm_dataproducer_bytes_12_to_15_17[7]), + .S(com_cmm_u_cmm_dataproducer_N_50471) + ); + defparam com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_am_8_.INIT = 16'h8000; + LUT4 com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_am_8_ ( + .I0(com_cmm_u_cmm_dataproducer_N_50468_3), + .I1(com_cmm_req_cfgctrl), + .I2(com_cmm_cfg_rd_data[16]), + .I3(com_cmm_u_cmm_dataproducer_req_gnt_code_0__295), + .O(com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_am[8]) + ); + defparam com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_bm_8_.INIT = 4'h8; + LUT2 com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_bm_8_ ( + .I0(com_cmm_msi_laddr[8]), + .I1(com_cmm_u_cmm_dataproducer_req_gnt_code_0__295), + .O(com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_bm[8]) + ); + MUXF5 com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_8_ ( + .I0(com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_am[8]), + .I1(com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_bm[8]), + .O(com_cmm_u_cmm_dataproducer_bytes_12_to_15_17[8]), + .S(com_cmm_u_cmm_dataproducer_N_50471) + ); + defparam com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_am_9_.INIT = 16'h8000; + LUT4 com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_am_9_ ( + .I0(com_cmm_u_cmm_dataproducer_N_50468_3), + .I1(com_cmm_req_cfgctrl), + .I2(com_cmm_cfg_rd_data[17]), + .I3(com_cmm_u_cmm_dataproducer_req_gnt_code_0__295), + .O(com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_am[9]) + ); + defparam com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_bm_9_.INIT = 4'h8; + LUT2 com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_bm_9_ ( + .I0(com_cmm_msi_laddr[9]), + .I1(com_cmm_u_cmm_dataproducer_req_gnt_code_0__295), + .O(com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_bm[9]) + ); + MUXF5 com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_9_ ( + .I0(com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_am[9]), + .I1(com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_bm[9]), + .O(com_cmm_u_cmm_dataproducer_bytes_12_to_15_17[9]), + .S(com_cmm_u_cmm_dataproducer_N_50471) + ); + defparam com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_am_10_.INIT = 16'h8000; + LUT4 com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_am_10_ ( + .I0(com_cmm_u_cmm_dataproducer_N_50468_3), + .I1(com_cmm_req_cfgctrl), + .I2(com_cmm_cfg_rd_data[18]), + .I3(com_cmm_u_cmm_dataproducer_req_gnt_code_0__295), + .O(com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_am[10]) + ); + defparam com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_bm_10_.INIT = 4'h8; + LUT2 com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_bm_10_ ( + .I0(com_cmm_msi_laddr[10]), + .I1(com_cmm_u_cmm_dataproducer_req_gnt_code_0__295), + .O(com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_bm[10]) + ); + MUXF5 com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_10_ ( + .I0(com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_am[10]), + .I1(com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_bm[10]), + .O(com_cmm_u_cmm_dataproducer_bytes_12_to_15_17[10]), + .S(com_cmm_u_cmm_dataproducer_N_50471) + ); + defparam com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_am_11_.INIT = 16'h8000; + LUT4 com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_am_11_ ( + .I0(com_cmm_u_cmm_dataproducer_N_50468_3), + .I1(com_cmm_req_cfgctrl), + .I2(com_cmm_cfg_rd_data[19]), + .I3(com_cmm_u_cmm_dataproducer_req_gnt_code_0__295), + .O(com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_am[11]) + ); + defparam com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_bm_11_.INIT = 4'h8; + LUT2 com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_bm_11_ ( + .I0(com_cmm_msi_laddr[11]), + .I1(com_cmm_u_cmm_dataproducer_req_gnt_code_0__295), + .O(com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_bm[11]) + ); + MUXF5 com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_11_ ( + .I0(com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_am[11]), + .I1(com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_bm[11]), + .O(com_cmm_u_cmm_dataproducer_bytes_12_to_15_17[11]), + .S(com_cmm_u_cmm_dataproducer_N_50471) + ); + defparam com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_am_12_.INIT = 16'h8000; + LUT4 com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_am_12_ ( + .I0(com_cmm_u_cmm_dataproducer_N_50468_3), + .I1(com_cmm_req_cfgctrl), + .I2(com_cmm_cfg_rd_data[20]), + .I3(com_cmm_u_cmm_dataproducer_req_gnt_code_0__295), + .O(com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_am[12]) + ); + defparam com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_bm_12_.INIT = 4'h8; + LUT2 com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_bm_12_ ( + .I0(com_cmm_msi_laddr[12]), + .I1(com_cmm_u_cmm_dataproducer_req_gnt_code_0__295), + .O(com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_bm[12]) + ); + MUXF5 com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_12_ ( + .I0(com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_am[12]), + .I1(com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_bm[12]), + .O(com_cmm_u_cmm_dataproducer_bytes_12_to_15_17[12]), + .S(com_cmm_u_cmm_dataproducer_N_50471) + ); + defparam com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_am_13_.INIT = 16'h8000; + LUT4 com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_am_13_ ( + .I0(com_cmm_u_cmm_dataproducer_N_50468_3), + .I1(com_cmm_req_cfgctrl), + .I2(com_cmm_cfg_rd_data[21]), + .I3(com_cmm_u_cmm_dataproducer_req_gnt_code_0__295), + .O(com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_am[13]) + ); + defparam com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_bm_13_.INIT = 4'h8; + LUT2 com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_bm_13_ ( + .I0(com_cmm_msi_laddr[13]), + .I1(com_cmm_u_cmm_dataproducer_req_gnt_code_0__295), + .O(com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_bm[13]) + ); + MUXF5 com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_13_ ( + .I0(com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_am[13]), + .I1(com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_bm[13]), + .O(com_cmm_u_cmm_dataproducer_bytes_12_to_15_17[13]), + .S(com_cmm_u_cmm_dataproducer_N_50471) + ); + defparam com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_am_14_.INIT = 16'h8000; + LUT4 com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_am_14_ ( + .I0(com_cmm_u_cmm_dataproducer_N_50468_3), + .I1(com_cmm_req_cfgctrl), + .I2(com_cmm_cfg_rd_data[22]), + .I3(com_cmm_u_cmm_dataproducer_req_gnt_code_0__295), + .O(com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_am[14]) + ); + defparam com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_bm_14_.INIT = 4'h8; + LUT2 com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_bm_14_ ( + .I0(com_cmm_msi_laddr[14]), + .I1(com_cmm_u_cmm_dataproducer_req_gnt_code_0__295), + .O(com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_bm[14]) + ); + MUXF5 com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_14_ ( + .I0(com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_am[14]), + .I1(com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_bm[14]), + .O(com_cmm_u_cmm_dataproducer_bytes_12_to_15_17[14]), + .S(com_cmm_u_cmm_dataproducer_N_50471) + ); + defparam com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_am_15_.INIT = 16'h8000; + LUT4 com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_am_15_ ( + .I0(com_cmm_u_cmm_dataproducer_N_50468_3), + .I1(com_cmm_req_cfgctrl), + .I2(com_cmm_cfg_rd_data[23]), + .I3(com_cmm_u_cmm_dataproducer_req_gnt_code_0__295), + .O(com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_am[15]) + ); + defparam com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_bm_15_.INIT = 4'h8; + LUT2 com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_bm_15_ ( + .I0(com_cmm_msi_laddr[15]), + .I1(com_cmm_u_cmm_dataproducer_req_gnt_code_0__295), + .O(com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_bm[15]) + ); + MUXF5 com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_15_ ( + .I0(com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_am[15]), + .I1(com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_bm[15]), + .O(com_cmm_u_cmm_dataproducer_bytes_12_to_15_17[15]), + .S(com_cmm_u_cmm_dataproducer_N_50471) + ); + defparam com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_am_16_.INIT = 16'h8000; + LUT4 com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_am_16_ ( + .I0(com_cmm_u_cmm_dataproducer_N_50468_3), + .I1(com_cmm_req_cfgctrl), + .I2(com_cmm_cfg_rd_data[8]), + .I3(com_cmm_u_cmm_dataproducer_req_gnt_code_0__295), + .O(com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_am[16]) + ); + defparam com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_bm_16_.INIT = 8'hCA; + LUT3 com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_bm_16_ ( + .I0(com_cmm_msi_data[8]), + .I1(com_cmm_msi_laddr[16]), + .I2(com_cmm_u_cmm_dataproducer_req_gnt_code_0__295), + .O(com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_bm[16]) + ); + MUXF5 com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_16_ ( + .I0(com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_am[16]), + .I1(com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_bm[16]), + .O(com_cmm_u_cmm_dataproducer_bytes_12_to_15_17[16]), + .S(com_cmm_u_cmm_dataproducer_N_50471) + ); + defparam com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_am_17_.INIT = 16'h8000; + LUT4 com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_am_17_ ( + .I0(com_cmm_u_cmm_dataproducer_N_50468_3), + .I1(com_cmm_req_cfgctrl), + .I2(com_cmm_cfg_rd_data[9]), + .I3(com_cmm_u_cmm_dataproducer_req_gnt_code_0__295), + .O(com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_am[17]) + ); + defparam com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_bm_17_.INIT = 8'hCA; + LUT3 com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_bm_17_ ( + .I0(com_cmm_msi_data[9]), + .I1(com_cmm_msi_laddr[17]), + .I2(com_cmm_u_cmm_dataproducer_req_gnt_code_0__295), + .O(com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_bm[17]) + ); + MUXF5 com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_17_ ( + .I0(com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_am[17]), + .I1(com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_bm[17]), + .O(com_cmm_u_cmm_dataproducer_bytes_12_to_15_17[17]), + .S(com_cmm_u_cmm_dataproducer_N_50471) + ); + defparam com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_am_18_.INIT = 16'h8000; + LUT4 com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_am_18_ ( + .I0(com_cmm_u_cmm_dataproducer_N_50468_3), + .I1(com_cmm_req_cfgctrl), + .I2(com_cmm_cfg_rd_data[10]), + .I3(com_cmm_u_cmm_dataproducer_req_gnt_code_0__295), + .O(com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_am[18]) + ); + defparam com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_bm_18_.INIT = 8'hCA; + LUT3 com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_bm_18_ ( + .I0(com_cmm_msi_data[10]), + .I1(com_cmm_msi_laddr[18]), + .I2(com_cmm_u_cmm_dataproducer_req_gnt_code_0__295), + .O(com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_bm[18]) + ); + MUXF5 com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_18_ ( + .I0(com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_am[18]), + .I1(com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_bm[18]), + .O(com_cmm_u_cmm_dataproducer_bytes_12_to_15_17[18]), + .S(com_cmm_u_cmm_dataproducer_N_50471) + ); + defparam com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_am_19_.INIT = 16'h8000; + LUT4 com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_am_19_ ( + .I0(com_cmm_u_cmm_dataproducer_N_50468_3), + .I1(com_cmm_req_cfgctrl), + .I2(com_cmm_cfg_rd_data[11]), + .I3(com_cmm_u_cmm_dataproducer_req_gnt_code_0__295), + .O(com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_am[19]) + ); + defparam com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_bm_19_.INIT = 8'hCA; + LUT3 com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_bm_19_ ( + .I0(com_cmm_msi_data[11]), + .I1(com_cmm_msi_laddr[19]), + .I2(com_cmm_u_cmm_dataproducer_req_gnt_code_0__295), + .O(com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_bm[19]) + ); + MUXF5 com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_19_ ( + .I0(com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_am[19]), + .I1(com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_bm[19]), + .O(com_cmm_u_cmm_dataproducer_bytes_12_to_15_17[19]), + .S(com_cmm_u_cmm_dataproducer_N_50471) + ); + defparam com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_am_20_.INIT = 16'h8000; + LUT4 com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_am_20_ ( + .I0(com_cmm_u_cmm_dataproducer_N_50468_3), + .I1(com_cmm_req_cfgctrl), + .I2(com_cmm_cfg_rd_data[12]), + .I3(com_cmm_u_cmm_dataproducer_req_gnt_code_0__295), + .O(com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_am[20]) + ); + defparam com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_bm_20_.INIT = 8'hCA; + LUT3 com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_bm_20_ ( + .I0(com_cmm_msi_data[12]), + .I1(com_cmm_msi_laddr[20]), + .I2(com_cmm_u_cmm_dataproducer_req_gnt_code_0__295), + .O(com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_bm[20]) + ); + MUXF5 com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_20_ ( + .I0(com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_am[20]), + .I1(com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_bm[20]), + .O(com_cmm_u_cmm_dataproducer_bytes_12_to_15_17[20]), + .S(com_cmm_u_cmm_dataproducer_N_50471) + ); + defparam com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_am_21_.INIT = 16'h8000; + LUT4 com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_am_21_ ( + .I0(com_cmm_u_cmm_dataproducer_N_50468_3), + .I1(com_cmm_req_cfgctrl), + .I2(com_cmm_cfg_rd_data[13]), + .I3(com_cmm_u_cmm_dataproducer_req_gnt_code_0__295), + .O(com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_am[21]) + ); + defparam com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_bm_21_.INIT = 8'hCA; + LUT3 com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_bm_21_ ( + .I0(com_cmm_msi_data[13]), + .I1(com_cmm_msi_laddr[21]), + .I2(com_cmm_u_cmm_dataproducer_req_gnt_code_0__295), + .O(com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_bm[21]) + ); + MUXF5 com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_21_ ( + .I0(com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_am[21]), + .I1(com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_bm[21]), + .O(com_cmm_u_cmm_dataproducer_bytes_12_to_15_17[21]), + .S(com_cmm_u_cmm_dataproducer_N_50471) + ); + defparam com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_am_22_.INIT = 16'h8000; + LUT4 com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_am_22_ ( + .I0(com_cmm_u_cmm_dataproducer_N_50468_3), + .I1(com_cmm_req_cfgctrl), + .I2(com_cmm_cfg_rd_data[14]), + .I3(com_cmm_u_cmm_dataproducer_req_gnt_code_0__295), + .O(com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_am[22]) + ); + defparam com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_bm_22_.INIT = 8'hCA; + LUT3 com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_bm_22_ ( + .I0(com_cmm_msi_data[14]), + .I1(com_cmm_msi_laddr[22]), + .I2(com_cmm_u_cmm_dataproducer_req_gnt_code_0__295), + .O(com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_bm[22]) + ); + MUXF5 com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_22_ ( + .I0(com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_am[22]), + .I1(com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_bm[22]), + .O(com_cmm_u_cmm_dataproducer_bytes_12_to_15_17[22]), + .S(com_cmm_u_cmm_dataproducer_N_50471) + ); + defparam com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_am_23_.INIT = 16'h8000; + LUT4 com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_am_23_ ( + .I0(com_cmm_u_cmm_dataproducer_N_50468_3), + .I1(com_cmm_req_cfgctrl), + .I2(com_cmm_cfg_rd_data[15]), + .I3(com_cmm_u_cmm_dataproducer_req_gnt_code_0__295), + .O(com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_am[23]) + ); + defparam com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_bm_23_.INIT = 8'hCA; + LUT3 com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_bm_23_ ( + .I0(com_cmm_msi_data[15]), + .I1(com_cmm_msi_laddr[23]), + .I2(com_cmm_u_cmm_dataproducer_req_gnt_code_0__295), + .O(com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_bm[23]) + ); + MUXF5 com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_23_ ( + .I0(com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_am[23]), + .I1(com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_bm[23]), + .O(com_cmm_u_cmm_dataproducer_bytes_12_to_15_17[23]), + .S(com_cmm_u_cmm_dataproducer_N_50471) + ); + defparam com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_am_24_.INIT = 16'h8000; + LUT4 com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_am_24_ ( + .I0(com_cmm_u_cmm_dataproducer_N_50468_3), + .I1(com_cmm_req_cfgctrl), + .I2(com_cmm_cfg_rd_data[0]), + .I3(com_cmm_u_cmm_dataproducer_req_gnt_code_0__295), + .O(com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_am[24]) + ); + defparam com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_bm_24_.INIT = 8'hCA; + LUT3 com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_bm_24_ ( + .I0(com_cmm_msi_data[0]), + .I1(com_cmm_msi_laddr[24]), + .I2(com_cmm_u_cmm_dataproducer_req_gnt_code_0__295), + .O(com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_bm[24]) + ); + MUXF5 com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_24_ ( + .I0(com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_am[24]), + .I1(com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_bm[24]), + .O(com_cmm_u_cmm_dataproducer_bytes_12_to_15_17[24]), + .S(com_cmm_u_cmm_dataproducer_N_50471) + ); + defparam com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_am_25_.INIT = 16'h8000; + LUT4 com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_am_25_ ( + .I0(com_cmm_u_cmm_dataproducer_N_50468_3), + .I1(com_cmm_req_cfgctrl), + .I2(com_cmm_cfg_rd_data[1]), + .I3(com_cmm_u_cmm_dataproducer_req_gnt_code_0__295), + .O(com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_am[25]) + ); + defparam com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_bm_25_.INIT = 8'hCA; + LUT3 com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_bm_25_ ( + .I0(com_cmm_msi_data[1]), + .I1(com_cmm_msi_laddr[25]), + .I2(com_cmm_u_cmm_dataproducer_req_gnt_code_0__295), + .O(com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_bm[25]) + ); + MUXF5 com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_25_ ( + .I0(com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_am[25]), + .I1(com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_bm[25]), + .O(com_cmm_u_cmm_dataproducer_bytes_12_to_15_17[25]), + .S(com_cmm_u_cmm_dataproducer_N_50471) + ); + defparam com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_am_26_.INIT = 16'h8000; + LUT4 com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_am_26_ ( + .I0(com_cmm_u_cmm_dataproducer_N_50468_3), + .I1(com_cmm_req_cfgctrl), + .I2(com_cmm_cfg_rd_data[2]), + .I3(com_cmm_u_cmm_dataproducer_req_gnt_code_0__295), + .O(com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_am[26]) + ); + defparam com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_bm_26_.INIT = 8'hCA; + LUT3 com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_bm_26_ ( + .I0(com_cmm_msi_data[2]), + .I1(com_cmm_msi_laddr[26]), + .I2(com_cmm_u_cmm_dataproducer_req_gnt_code_0__295), + .O(com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_bm[26]) + ); + MUXF5 com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_26_ ( + .I0(com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_am[26]), + .I1(com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_bm[26]), + .O(com_cmm_u_cmm_dataproducer_bytes_12_to_15_17[26]), + .S(com_cmm_u_cmm_dataproducer_N_50471) + ); + defparam com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_am_27_.INIT = 16'h8000; + LUT4 com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_am_27_ ( + .I0(com_cmm_u_cmm_dataproducer_N_50468_3), + .I1(com_cmm_req_cfgctrl), + .I2(com_cmm_cfg_rd_data[3]), + .I3(com_cmm_u_cmm_dataproducer_req_gnt_code_0__295), + .O(com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_am[27]) + ); + defparam com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_bm_27_.INIT = 8'hCA; + LUT3 com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_bm_27_ ( + .I0(com_cmm_msi_data[3]), + .I1(com_cmm_msi_laddr[27]), + .I2(com_cmm_u_cmm_dataproducer_req_gnt_code_0__295), + .O(com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_bm[27]) + ); + MUXF5 com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_27_ ( + .I0(com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_am[27]), + .I1(com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_bm[27]), + .O(com_cmm_u_cmm_dataproducer_bytes_12_to_15_17[27]), + .S(com_cmm_u_cmm_dataproducer_N_50471) + ); + defparam com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_am_28_.INIT = 16'h8000; + LUT4 com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_am_28_ ( + .I0(com_cmm_u_cmm_dataproducer_N_50468_3), + .I1(com_cmm_req_cfgctrl), + .I2(com_cmm_cfg_rd_data[4]), + .I3(com_cmm_u_cmm_dataproducer_req_gnt_code_0__295), + .O(com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_am[28]) + ); + defparam com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_bm_28_.INIT = 8'hCA; + LUT3 com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_bm_28_ ( + .I0(com_cmm_msi_data[4]), + .I1(com_cmm_msi_laddr[28]), + .I2(com_cmm_u_cmm_dataproducer_req_gnt_code_0__295), + .O(com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_bm[28]) + ); + MUXF5 com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_28_ ( + .I0(com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_am[28]), + .I1(com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_bm[28]), + .O(com_cmm_u_cmm_dataproducer_bytes_12_to_15_17[28]), + .S(com_cmm_u_cmm_dataproducer_N_50471) + ); + defparam com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_am_29_.INIT = 16'h8000; + LUT4 com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_am_29_ ( + .I0(com_cmm_u_cmm_dataproducer_N_50468_3), + .I1(com_cmm_req_cfgctrl), + .I2(com_cmm_cfg_rd_data[5]), + .I3(com_cmm_u_cmm_dataproducer_req_gnt_code_0__295), + .O(com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_am[29]) + ); + defparam com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_bm_29_.INIT = 8'hCA; + LUT3 com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_bm_29_ ( + .I0(com_cmm_msi_data[5]), + .I1(com_cmm_msi_laddr[29]), + .I2(com_cmm_u_cmm_dataproducer_req_gnt_code_0__295), + .O(com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_bm[29]) + ); + MUXF5 com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_29_ ( + .I0(com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_am[29]), + .I1(com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_bm[29]), + .O(com_cmm_u_cmm_dataproducer_bytes_12_to_15_17[29]), + .S(com_cmm_u_cmm_dataproducer_N_50471) + ); + defparam com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_am_30_.INIT = 16'h8000; + LUT4 com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_am_30_ ( + .I0(com_cmm_u_cmm_dataproducer_N_50468_3), + .I1(com_cmm_req_cfgctrl), + .I2(com_cmm_cfg_rd_data[6]), + .I3(com_cmm_u_cmm_dataproducer_req_gnt_code_0__295), + .O(com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_am[30]) + ); + defparam com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_bm_30_.INIT = 8'hCA; + LUT3 com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_bm_30_ ( + .I0(com_cmm_msi_data[6]), + .I1(com_cmm_msi_laddr[30]), + .I2(com_cmm_u_cmm_dataproducer_req_gnt_code_0__295), + .O(com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_bm[30]) + ); + MUXF5 com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_30_ ( + .I0(com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_am[30]), + .I1(com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_bm[30]), + .O(com_cmm_u_cmm_dataproducer_bytes_12_to_15_17[30]), + .S(com_cmm_u_cmm_dataproducer_N_50471) + ); + defparam com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_am_31_.INIT = 16'h8000; + LUT4 com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_am_31_ ( + .I0(com_cmm_u_cmm_dataproducer_N_50468_3), + .I1(com_cmm_req_cfgctrl), + .I2(com_cmm_cfg_rd_data[7]), + .I3(com_cmm_u_cmm_dataproducer_req_gnt_code_0__295), + .O(com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_am[31]) + ); + defparam com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_bm_31_.INIT = 8'hCA; + LUT3 com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_bm_31_ ( + .I0(com_cmm_msi_data[7]), + .I1(com_cmm_msi_laddr[31]), + .I2(com_cmm_u_cmm_dataproducer_req_gnt_code_0__295), + .O(com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_bm[31]) + ); + MUXF5 com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_31_ ( + .I0(com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_am[31]), + .I1(com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_bm[31]), + .O(com_cmm_u_cmm_dataproducer_bytes_12_to_15_17[31]), + .S(com_cmm_u_cmm_dataproducer_N_50471) + ); + defparam com_cmm_u_cmm_dataproducer_nxt_req_gnt_state38_0_a2_0_a2_0_a2_0_a2.INIT = 4'h8; + LUT2_L com_cmm_u_cmm_dataproducer_nxt_req_gnt_state38_0_a2_0_a2_0_a2_0_a2 ( + .I0(com_cmm_u_cmm_dataproducer_req_gnt_state[0]), + .I1(com_cmm_u_cmm_dataproducer_req_gnt_state[1]), + .LO(com_cmm_u_cmm_dataproducer_nxt_req_gnt_state38) + ); + defparam com_cmm_u_cmm_dataproducer_N_68506_i.INIT = 16'hCCEC; + LUT4_L com_cmm_u_cmm_dataproducer_N_68506_i ( + .I0(com_cmm_u_cmm_dataproducer_N_48879_i), + .I1(com_cmm_u_cmm_dataproducer_N_49561), + .I2(com_cmm_data_errmanager[48]), + .I3(com_cmm_data_errmanager[49]), + .LO(com_cmm_u_cmm_dataproducer_N_68506_i_5017) + ); + defparam com_cmm_u_cmm_dataproducer_N_49557_i.INIT = 4'h1; + LUT1_L com_cmm_u_cmm_dataproducer_N_49557_i ( + .I0(com_cmm_u_cmm_dataproducer_byte_04_17_i_0_0_0_a2[0]), + .LO(com_cmm_u_cmm_dataproducer_N_49557_i_5018) + ); + defparam com_cmm_u_cmm_dataproducer_byte_06_21_0_a2_0_a2_0_a2_0_a2_7_.INIT = 4'h8; + LUT2_L com_cmm_u_cmm_dataproducer_byte_06_21_0_a2_0_a2_0_a2_0_a2_7_ ( + .I0(com_cmm_u_cmm_dataproducer_N_48879_i), + .I1(com_cmm_N_48927_i), + .LO(com_cmm_u_cmm_dataproducer_byte_06_21_7_) + ); + defparam com_cmm_u_cmm_dataproducer_N_68167_i.INIT = 16'hFEFC; + LUT4_L com_cmm_u_cmm_dataproducer_N_68167_i ( + .I0(com_cmm_u_cmm_dataproducer_N_48879_i), + .I1(com_cmm_u_cmm_dataproducer_N_50006), + .I2(com_cmm_u_cmm_dataproducer_N_50007), + .I3(com_cmm_data_errmanager[31]), + .LO(com_cmm_u_cmm_dataproducer_N_68167_i_5019) + ); + defparam com_cmm_u_cmm_dataproducer_N_68156_i.INIT = 16'hFBF3; + LUT4_L com_cmm_u_cmm_dataproducer_N_68156_i ( + .I0(com_cmm_u_cmm_dataproducer_N_48879_i), + .I1(com_cmm_u_cmm_dataproducer_N_48950_i), + .I2(com_cmm_u_cmm_dataproducer_N_49551), + .I3(com_cmm_data_errmanager[30]), + .LO(com_cmm_u_cmm_dataproducer_N_68156_i_5020) + ); + defparam com_cmm_u_cmm_dataproducer_N_68155_i.INIT = 16'hDDFD; + LUT4_L com_cmm_u_cmm_dataproducer_N_68155_i ( + .I0(com_cmm_u_cmm_dataproducer_N_48950_i), + .I1(com_cmm_u_cmm_dataproducer_N_49550), + .I2(N_49558), + .I3(com_cmm_u_cmm_dataproducer_req_gnt_code_3__234), + .LO(com_cmm_u_cmm_dataproducer_N_68155_i_5021) + ); + defparam com_cmm_u_cmm_dataproducer_N_68125_i.INIT = 16'hFEEE; + LUT4_L com_cmm_u_cmm_dataproducer_N_68125_i ( + .I0(com_cmm_u_cmm_dataproducer_N_49267), + .I1(com_cmm_u_cmm_dataproducer_N_49269), + .I2(com_cmm_u_cmm_dataproducer_N_50481), + .I3(com_cmm_msi_haddr[17]), + .LO(com_cmm_u_cmm_dataproducer_N_68125_i_5022) + ); + defparam com_cmm_u_cmm_dataproducer_N_68124_i.INIT = 16'hFEEE; + LUT4_L com_cmm_u_cmm_dataproducer_N_68124_i ( + .I0(com_cmm_u_cmm_dataproducer_N_49264), + .I1(com_cmm_u_cmm_dataproducer_N_49265), + .I2(com_cmm_u_cmm_dataproducer_N_50481), + .I3(com_cmm_msi_haddr[16]), + .LO(com_cmm_u_cmm_dataproducer_N_68124_i_5023) + ); + defparam com_cmm_u_cmm_dataproducer_N_68123_i.INIT = 16'hFEEE; + LUT4_L com_cmm_u_cmm_dataproducer_N_68123_i ( + .I0(com_cmm_u_cmm_dataproducer_N_49261), + .I1(com_cmm_u_cmm_dataproducer_N_49263), + .I2(com_cmm_u_cmm_dataproducer_N_50481), + .I3(com_cmm_msi_haddr[31]), + .LO(com_cmm_u_cmm_dataproducer_N_68123_i_5024) + ); + defparam com_cmm_u_cmm_dataproducer_N_68122_i.INIT = 16'hFEEE; + LUT4_L com_cmm_u_cmm_dataproducer_N_68122_i ( + .I0(com_cmm_u_cmm_dataproducer_N_49258), + .I1(com_cmm_u_cmm_dataproducer_N_49260), + .I2(com_cmm_u_cmm_dataproducer_N_50481), + .I3(com_cmm_msi_haddr[30]), + .LO(com_cmm_u_cmm_dataproducer_N_68122_i_5025) + ); + defparam com_cmm_u_cmm_dataproducer_N_68121_i.INIT = 16'hFEEE; + LUT4_L com_cmm_u_cmm_dataproducer_N_68121_i ( + .I0(com_cmm_u_cmm_dataproducer_N_49255), + .I1(com_cmm_u_cmm_dataproducer_N_49257), + .I2(com_cmm_u_cmm_dataproducer_N_50481), + .I3(com_cmm_msi_haddr[29]), + .LO(com_cmm_u_cmm_dataproducer_N_68121_i_5026) + ); + defparam com_cmm_u_cmm_dataproducer_N_68120_i.INIT = 16'hFEEE; + LUT4_L com_cmm_u_cmm_dataproducer_N_68120_i ( + .I0(com_cmm_u_cmm_dataproducer_N_49252), + .I1(com_cmm_u_cmm_dataproducer_N_49254), + .I2(com_cmm_u_cmm_dataproducer_N_50481), + .I3(com_cmm_msi_haddr[28]), + .LO(com_cmm_u_cmm_dataproducer_N_68120_i_5027) + ); + defparam com_cmm_u_cmm_dataproducer_N_68119_i.INIT = 16'hFEEE; + LUT4_L com_cmm_u_cmm_dataproducer_N_68119_i ( + .I0(com_cmm_u_cmm_dataproducer_N_49249), + .I1(com_cmm_u_cmm_dataproducer_N_49250), + .I2(com_cmm_u_cmm_dataproducer_N_50481), + .I3(com_cmm_msi_haddr[27]), + .LO(com_cmm_u_cmm_dataproducer_N_68119_i_5028) + ); + defparam com_cmm_u_cmm_dataproducer_N_68118_i.INIT = 16'hFEEE; + LUT4_L com_cmm_u_cmm_dataproducer_N_68118_i ( + .I0(com_cmm_u_cmm_dataproducer_N_49246), + .I1(com_cmm_u_cmm_dataproducer_N_49248), + .I2(com_cmm_u_cmm_dataproducer_N_50481), + .I3(com_cmm_msi_haddr[26]), + .LO(com_cmm_u_cmm_dataproducer_N_68118_i_5029) + ); + defparam com_cmm_u_cmm_dataproducer_N_68117_i.INIT = 16'hFEEE; + LUT4_L com_cmm_u_cmm_dataproducer_N_68117_i ( + .I0(com_cmm_u_cmm_dataproducer_N_49243), + .I1(com_cmm_u_cmm_dataproducer_N_49245), + .I2(com_cmm_u_cmm_dataproducer_N_50481), + .I3(com_cmm_msi_haddr[25]), + .LO(com_cmm_u_cmm_dataproducer_N_68117_i_5030) + ); + defparam com_cmm_u_cmm_dataproducer_N_68116_i.INIT = 16'hFEEE; + LUT4_L com_cmm_u_cmm_dataproducer_N_68116_i ( + .I0(com_cmm_u_cmm_dataproducer_N_49240), + .I1(com_cmm_u_cmm_dataproducer_N_49242), + .I2(com_cmm_u_cmm_dataproducer_N_50481), + .I3(com_cmm_msi_haddr[24]), + .LO(com_cmm_u_cmm_dataproducer_N_68116_i_5031) + ); + defparam com_cmm_u_cmm_dataproducer_byte_07_27_0_0_a2_0_a2_0_a2_0_a2_7_.INIT = 4'h8; + LUT2_L com_cmm_u_cmm_dataproducer_byte_07_27_0_0_a2_0_a2_0_a2_0_a2_7_ ( + .I0(com_cmm_u_cmm_dataproducer_N_48879_i), + .I1(com_cmm_data_errmanager[36]), + .LO(com_cmm_u_cmm_dataproducer_byte_07_27[7]) + ); + defparam com_cmm_u_cmm_dataproducer_byte_07_27_0_0_a2_0_a2_0_a2_0_a2_6_.INIT = 4'h8; + LUT2_L com_cmm_u_cmm_dataproducer_byte_07_27_0_0_a2_0_a2_0_a2_0_a2_6_ ( + .I0(com_cmm_u_cmm_dataproducer_N_48879_i), + .I1(com_cmm_data_errmanager[35]), + .LO(com_cmm_u_cmm_dataproducer_byte_07_27[6]) + ); + defparam com_cmm_u_cmm_dataproducer_N_68158_i.INIT = 16'hEEFE; + LUT4_L com_cmm_u_cmm_dataproducer_N_68158_i ( + .I0(N_49558), + .I1(com_cmm_u_cmm_dataproducer_N_49560), + .I2(N_49663), + .I3(com_cmm_u_cmm_dataproducer_req_gnt_code_0__295), + .LO(com_cmm_u_cmm_dataproducer_N_68158_i_5032) + ); + defparam com_cmm_u_cmm_dataproducer_N_68561_i.INIT = 16'hAAEA; + LUT4_L com_cmm_u_cmm_dataproducer_N_68561_i ( + .I0(N_49663), + .I1(com_cmm_data_errmanager[33]), + .I2(com_cmm_u_cmm_dataproducer_req_gnt_code[1]), + .I3(com_cmm_u_cmm_dataproducer_req_gnt_code_3__234), + .LO(com_cmm_u_cmm_dataproducer_N_68561_i_5033) + ); + defparam com_cmm_u_cmm_dataproducer_N_68168_i.INIT = 16'hFEFC; + LUT4_L com_cmm_u_cmm_dataproducer_N_68168_i ( + .I0(com_cmm_u_cmm_dataproducer_N_48879_i), + .I1(com_cmm_u_cmm_dataproducer_N_50011), + .I2(com_cmm_u_cmm_dataproducer_N_50471), + .I3(com_cmm_data_errmanager[32]), + .LO(com_cmm_u_cmm_dataproducer_N_68168_i_5034) + ); + defparam com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_a2_0_a2_0_a2_0_.INIT = 4'h8; + LUT2_L com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_a2_0_a2_0_a2_0_ ( + .I0(com_cmm_u_cmm_dataproducer_N_50009), + .I1(com_cmm_cfg_rd_data[24]), + .LO(com_cmm_u_cmm_dataproducer_bytes_12_to_15_17[0]) + ); + defparam com_cmm_u_cmm_dataproducer_N_68164_i.INIT = 16'hFEEE; + LUT4_L com_cmm_u_cmm_dataproducer_N_68164_i ( + .I0(com_cmm_u_cmm_dataproducer_N_49677), + .I1(com_cmm_u_cmm_dataproducer_N_49678), + .I2(com_cmm_u_cmm_dataproducer_N_50481), + .I3(com_cmm_msi_haddr[15]), + .LO(com_cmm_u_cmm_dataproducer_N_68164_i_5035) + ); + defparam com_cmm_u_cmm_dataproducer_N_68137_i.INIT = 16'hFEEE; + LUT4_L com_cmm_u_cmm_dataproducer_N_68137_i ( + .I0(com_cmm_u_cmm_dataproducer_N_49303), + .I1(com_cmm_u_cmm_dataproducer_N_49304), + .I2(com_cmm_u_cmm_dataproducer_N_50481), + .I3(com_cmm_msi_haddr[14]), + .LO(com_cmm_u_cmm_dataproducer_N_68137_i_5036) + ); + defparam com_cmm_u_cmm_dataproducer_N_68136_i.INIT = 16'hFEEE; + LUT4_L com_cmm_u_cmm_dataproducer_N_68136_i ( + .I0(com_cmm_u_cmm_dataproducer_N_49300), + .I1(com_cmm_u_cmm_dataproducer_N_49301), + .I2(com_cmm_u_cmm_dataproducer_N_50481), + .I3(com_cmm_msi_haddr[13]), + .LO(com_cmm_u_cmm_dataproducer_N_68136_i_5037) + ); + defparam com_cmm_u_cmm_dataproducer_N_68135_i.INIT = 16'hFEEE; + LUT4_L com_cmm_u_cmm_dataproducer_N_68135_i ( + .I0(com_cmm_u_cmm_dataproducer_N_49297), + .I1(com_cmm_u_cmm_dataproducer_N_49298), + .I2(com_cmm_u_cmm_dataproducer_N_50481), + .I3(com_cmm_msi_haddr[12]), + .LO(com_cmm_u_cmm_dataproducer_N_68135_i_5038) + ); + defparam com_cmm_u_cmm_dataproducer_N_68165_i.INIT = 16'hFEEE; + LUT4_L com_cmm_u_cmm_dataproducer_N_68165_i ( + .I0(com_cmm_u_cmm_dataproducer_N_49680), + .I1(com_cmm_u_cmm_dataproducer_N_49681), + .I2(com_cmm_u_cmm_dataproducer_N_50481), + .I3(com_cmm_msi_haddr[11]), + .LO(com_cmm_u_cmm_dataproducer_N_68165_i_5039) + ); + defparam com_cmm_u_cmm_dataproducer_N_68134_i.INIT = 16'hFEEE; + LUT4_L com_cmm_u_cmm_dataproducer_N_68134_i ( + .I0(com_cmm_u_cmm_dataproducer_N_49294), + .I1(com_cmm_u_cmm_dataproducer_N_49295), + .I2(com_cmm_u_cmm_dataproducer_N_50481), + .I3(com_cmm_msi_haddr[10]), + .LO(com_cmm_u_cmm_dataproducer_N_68134_i_5040) + ); + defparam com_cmm_u_cmm_dataproducer_N_68133_i.INIT = 16'hFEEE; + LUT4_L com_cmm_u_cmm_dataproducer_N_68133_i ( + .I0(com_cmm_u_cmm_dataproducer_N_49291), + .I1(com_cmm_u_cmm_dataproducer_N_49292), + .I2(com_cmm_u_cmm_dataproducer_N_50481), + .I3(com_cmm_msi_haddr[9]), + .LO(com_cmm_u_cmm_dataproducer_N_68133_i_5041) + ); + defparam com_cmm_u_cmm_dataproducer_N_68132_i.INIT = 16'hFEEE; + LUT4_L com_cmm_u_cmm_dataproducer_N_68132_i ( + .I0(com_cmm_u_cmm_dataproducer_N_49288), + .I1(com_cmm_u_cmm_dataproducer_N_49289), + .I2(com_cmm_u_cmm_dataproducer_N_50481), + .I3(com_cmm_msi_haddr[8]), + .LO(com_cmm_u_cmm_dataproducer_N_68132_i_5042) + ); + defparam com_cmm_u_cmm_dataproducer_N_68131_i.INIT = 16'hFEEE; + LUT4_L com_cmm_u_cmm_dataproducer_N_68131_i ( + .I0(com_cmm_u_cmm_dataproducer_N_49285), + .I1(com_cmm_u_cmm_dataproducer_N_49287), + .I2(com_cmm_u_cmm_dataproducer_N_50481), + .I3(com_cmm_msi_haddr[23]), + .LO(com_cmm_u_cmm_dataproducer_N_68131_i_5043) + ); + defparam com_cmm_u_cmm_dataproducer_N_68130_i.INIT = 16'hFEEE; + LUT4_L com_cmm_u_cmm_dataproducer_N_68130_i ( + .I0(com_cmm_u_cmm_dataproducer_N_49282), + .I1(com_cmm_u_cmm_dataproducer_N_49284), + .I2(com_cmm_u_cmm_dataproducer_N_50481), + .I3(com_cmm_msi_haddr[22]), + .LO(com_cmm_u_cmm_dataproducer_N_68130_i_5044) + ); + defparam com_cmm_u_cmm_dataproducer_N_68129_i.INIT = 16'hFEEE; + LUT4_L com_cmm_u_cmm_dataproducer_N_68129_i ( + .I0(com_cmm_u_cmm_dataproducer_N_49279), + .I1(com_cmm_u_cmm_dataproducer_N_49281), + .I2(com_cmm_u_cmm_dataproducer_N_50481), + .I3(com_cmm_msi_haddr[21]), + .LO(com_cmm_u_cmm_dataproducer_N_68129_i_5045) + ); + defparam com_cmm_u_cmm_dataproducer_N_68128_i.INIT = 16'hFEEE; + LUT4_L com_cmm_u_cmm_dataproducer_N_68128_i ( + .I0(com_cmm_u_cmm_dataproducer_N_49276), + .I1(com_cmm_u_cmm_dataproducer_N_49278), + .I2(com_cmm_u_cmm_dataproducer_N_50481), + .I3(com_cmm_msi_haddr[20]), + .LO(com_cmm_u_cmm_dataproducer_N_68128_i_5046) + ); + defparam com_cmm_u_cmm_dataproducer_N_68127_i.INIT = 16'hFEEE; + LUT4_L com_cmm_u_cmm_dataproducer_N_68127_i ( + .I0(com_cmm_u_cmm_dataproducer_N_49273), + .I1(com_cmm_u_cmm_dataproducer_N_49275), + .I2(com_cmm_u_cmm_dataproducer_N_50481), + .I3(com_cmm_msi_haddr[19]), + .LO(com_cmm_u_cmm_dataproducer_N_68127_i_5047) + ); + defparam com_cmm_u_cmm_dataproducer_N_68126_i.INIT = 16'hFEEE; + LUT4_L com_cmm_u_cmm_dataproducer_N_68126_i ( + .I0(com_cmm_u_cmm_dataproducer_N_49270), + .I1(com_cmm_u_cmm_dataproducer_N_49272), + .I2(com_cmm_u_cmm_dataproducer_N_50481), + .I3(com_cmm_msi_haddr[18]), + .LO(com_cmm_u_cmm_dataproducer_N_68126_i_5048) + ); + defparam com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_a2_0_a2_0_a2_1_.INIT = 16'h8000; + LUT4_L com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_a2_0_a2_0_a2_1_ ( + .I0(com_cmm_u_cmm_dataproducer_N_50468_3), + .I1(com_cmm_req_cfgctrl), + .I2(com_cmm_cfg_rd_data[25]), + .I3(com_cmm_u_cmm_dataproducer_req_gnt_code_0__295), + .LO(com_cmm_u_cmm_dataproducer_bytes_12_to_15_17[1]) + ); + defparam com_cmm_u_cmm_dataproducer_byte_04_17_i_0_0_0_2_.INIT = 4'h4; + LUT2_L com_cmm_u_cmm_dataproducer_byte_04_17_i_0_0_0_2_ ( + .I0(com_cmm_u_cmm_dataproducer_byte_04_17_i_0_0_0_a2[0]), + .I1(NlwRenamedSig_OI_cfg_bus_number[2]), + .LO(com_cmm_u_cmm_dataproducer_N_16336_i) + ); + defparam com_cmm_u_cmm_dataproducer_byte_04_17_i_0_0_0_1_.INIT = 4'h4; + LUT2_L com_cmm_u_cmm_dataproducer_byte_04_17_i_0_0_0_1_ ( + .I0(com_cmm_u_cmm_dataproducer_byte_04_17_i_0_0_0_a2[0]), + .I1(NlwRenamedSig_OI_cfg_bus_number[1]), + .LO(com_cmm_u_cmm_dataproducer_N_16334_i) + ); + defparam com_cmm_u_cmm_dataproducer_byte_04_17_i_0_0_0_0_.INIT = 4'h4; + LUT2_L com_cmm_u_cmm_dataproducer_byte_04_17_i_0_0_0_0_ ( + .I0(com_cmm_u_cmm_dataproducer_byte_04_17_i_0_0_0_a2[0]), + .I1(NlwRenamedSig_OI_cfg_bus_number[0]), + .LO(com_cmm_u_cmm_dataproducer_N_16332_i) + ); + defparam com_cmm_u_cmm_dataproducer_byte_01_20_i_0_i_a2_i_6_.INIT = 4'h8; + LUT2_L com_cmm_u_cmm_dataproducer_byte_01_20_i_0_i_a2_i_6_ ( + .I0(com_cmm_u_cmm_dataproducer_N_48969_i), + .I1(com_cmm_data_errmanager[28]), + .LO(com_cmm_u_cmm_dataproducer_N_48188_i) + ); + defparam com_cmm_u_cmm_dataproducer_byte_01_20_i_0_i_a2_i_5_.INIT = 4'h8; + LUT2_L com_cmm_u_cmm_dataproducer_byte_01_20_i_0_i_a2_i_5_ ( + .I0(com_cmm_u_cmm_dataproducer_N_48969_i), + .I1(com_cmm_data_errmanager[27]), + .LO(com_cmm_u_cmm_dataproducer_N_48186_i) + ); + defparam com_cmm_u_cmm_dataproducer_byte_01_20_i_0_i_a2_i_4_.INIT = 4'h8; + LUT2_L com_cmm_u_cmm_dataproducer_byte_01_20_i_0_i_a2_i_4_ ( + .I0(com_cmm_u_cmm_dataproducer_N_48969_i), + .I1(com_cmm_data_errmanager[26]), + .LO(com_cmm_u_cmm_dataproducer_N_48184_i) + ); + defparam com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_sn_N_68623_i.INIT = 4'hE; + LUT2_L com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_sn_N_68623_i ( + .I0(com_cmm_u_cmm_dataproducer_N_50009), + .I1(com_cmm_u_cmm_dataproducer_N_50471), + .LO(com_cmm_u_cmm_dataproducer_N_68623_i) + ); + defparam com_cmm_u_cmm_dataproducer_N_68507_i.INIT = 8'hEA; + LUT3_L com_cmm_u_cmm_dataproducer_N_68507_i ( + .I0(com_cmm_u_cmm_dataproducer_byte_00_19_i_i_0_0_i_a2[5]), + .I1(com_cmm_u_cmm_dataproducer_req_gnt_code_0__295), + .I2(com_cmm_u_cmm_dataproducer_req_gnt_code[2]), + .LO(com_cmm_u_cmm_dataproducer_N_68507_i_5049) + ); + defparam com_cmm_u_cmm_dataproducer_N_68429_i.INIT = 16'hEAC0; + LUT4_L com_cmm_u_cmm_dataproducer_N_68429_i ( + .I0(com_cmm_u_cmm_dataproducer_N_48969_i), + .I1(com_cmm_u_cmm_dataproducer_N_50007), + .I2(com_cmm_attr[1]), + .I3(com_cmm_data_errmanager[25]), + .LO(com_cmm_u_cmm_dataproducer_N_68429_i_5051) + ); + defparam com_cmm_u_cmm_dataproducer_N_68428_i.INIT = 16'hEAC0; + LUT4_L com_cmm_u_cmm_dataproducer_N_68428_i ( + .I0(com_cmm_u_cmm_dataproducer_N_48969_i), + .I1(com_cmm_u_cmm_dataproducer_N_50007), + .I2(com_cmm_attr[0]), + .I3(com_cmm_data_errmanager[24]), + .LO(com_cmm_u_cmm_dataproducer_N_68428_i_5052) + ); + defparam com_cmm_u_cmm_dataproducer_byte_11_17_0_4_.INIT = 16'hEA40; + LUT4_L com_cmm_u_cmm_dataproducer_byte_11_17_0_4_ ( + .I0(com_cmm_u_cmm_dataproducer_N_50471), + .I1(com_cmm_u_cmm_dataproducer_byte_11_17_m0_0_a2_i_0_0_o2[0]), + .I2(com_cmm_data_errmanager[45]), + .I3(com_cmm_u_cmm_dataproducer_byte_11_17_m0[4]), + .LO(com_cmm_u_cmm_dataproducer_byte_11_17[4]) + ); + defparam com_cmm_u_cmm_dataproducer_byte_11_17_0_3_.INIT = 16'hEA40; + LUT4_L com_cmm_u_cmm_dataproducer_byte_11_17_0_3_ ( + .I0(com_cmm_u_cmm_dataproducer_N_50471), + .I1(com_cmm_u_cmm_dataproducer_byte_11_17_m0_0_a2_i_0_0_o2[0]), + .I2(com_cmm_data_errmanager[44]), + .I3(com_cmm_u_cmm_dataproducer_byte_11_17_m0[3]), + .LO(com_cmm_u_cmm_dataproducer_byte_11_17[3]) + ); + defparam com_cmm_u_cmm_dataproducer_byte_11_17_0_2_.INIT = 16'hEA40; + LUT4_L com_cmm_u_cmm_dataproducer_byte_11_17_0_2_ ( + .I0(com_cmm_u_cmm_dataproducer_N_50471), + .I1(com_cmm_u_cmm_dataproducer_byte_11_17_m0_0_a2_i_0_0_o2[0]), + .I2(com_cmm_data_errmanager[43]), + .I3(com_cmm_u_cmm_dataproducer_byte_11_17_m0[2]), + .LO(com_cmm_u_cmm_dataproducer_byte_11_17[2]) + ); + defparam com_cmm_u_cmm_dataproducer_byte_11_17_0_0_.INIT = 16'hC840; + LUT4_L com_cmm_u_cmm_dataproducer_byte_11_17_0_0_ ( + .I0(com_cmm_u_cmm_dataproducer_N_50471), + .I1(com_cmm_u_cmm_dataproducer_byte_11_17_m0_0_a2_i_0_0_o2[0]), + .I2(com_cmm_data_errmanager[41]), + .I3(com_cmm_msi_haddr[0]), + .LO(com_cmm_u_cmm_dataproducer_byte_11_17[0]) + ); + defparam com_cmm_u_cmm_dataproducer_byte_05_17_i_0_0_0_7_.INIT = 4'h4; + LUT2_L com_cmm_u_cmm_dataproducer_byte_05_17_i_0_0_0_7_ ( + .I0(com_cmm_u_cmm_dataproducer_byte_04_17_i_0_0_0_a2[0]), + .I1(NlwRenamedSig_OI_cfg_device_number[4]), + .LO(com_cmm_u_cmm_dataproducer_N_16356_i) + ); + defparam com_cmm_u_cmm_dataproducer_byte_05_17_i_0_0_0_6_.INIT = 4'h4; + LUT2_L com_cmm_u_cmm_dataproducer_byte_05_17_i_0_0_0_6_ ( + .I0(com_cmm_u_cmm_dataproducer_byte_04_17_i_0_0_0_a2[0]), + .I1(NlwRenamedSig_OI_cfg_device_number[3]), + .LO(com_cmm_u_cmm_dataproducer_N_16354_i) + ); + defparam com_cmm_u_cmm_dataproducer_byte_05_17_i_0_0_0_5_.INIT = 4'h4; + LUT2_L com_cmm_u_cmm_dataproducer_byte_05_17_i_0_0_0_5_ ( + .I0(com_cmm_u_cmm_dataproducer_byte_04_17_i_0_0_0_a2[0]), + .I1(NlwRenamedSig_OI_cfg_device_number[2]), + .LO(com_cmm_u_cmm_dataproducer_N_16352_i) + ); + defparam com_cmm_u_cmm_dataproducer_byte_05_17_i_0_0_0_4_.INIT = 4'h4; + LUT2_L com_cmm_u_cmm_dataproducer_byte_05_17_i_0_0_0_4_ ( + .I0(com_cmm_u_cmm_dataproducer_byte_04_17_i_0_0_0_a2[0]), + .I1(NlwRenamedSig_OI_cfg_device_number[1]), + .LO(com_cmm_u_cmm_dataproducer_N_16350_i) + ); + defparam com_cmm_u_cmm_dataproducer_byte_05_17_i_0_0_0_3_.INIT = 4'h4; + LUT2_L com_cmm_u_cmm_dataproducer_byte_05_17_i_0_0_0_3_ ( + .I0(com_cmm_u_cmm_dataproducer_byte_04_17_i_0_0_0_a2[0]), + .I1(NlwRenamedSig_OI_cfg_device_number[0]), + .LO(com_cmm_u_cmm_dataproducer_N_16348_i) + ); + defparam com_cmm_u_cmm_dataproducer_byte_04_17_i_0_0_0_7_.INIT = 4'h4; + LUT2_L com_cmm_u_cmm_dataproducer_byte_04_17_i_0_0_0_7_ ( + .I0(com_cmm_u_cmm_dataproducer_byte_04_17_i_0_0_0_a2[0]), + .I1(NlwRenamedSig_OI_cfg_bus_number[7]), + .LO(com_cmm_u_cmm_dataproducer_N_16346_i) + ); + defparam com_cmm_u_cmm_dataproducer_byte_04_17_i_0_0_0_6_.INIT = 4'h4; + LUT2_L com_cmm_u_cmm_dataproducer_byte_04_17_i_0_0_0_6_ ( + .I0(com_cmm_u_cmm_dataproducer_byte_04_17_i_0_0_0_a2[0]), + .I1(NlwRenamedSig_OI_cfg_bus_number[6]), + .LO(com_cmm_u_cmm_dataproducer_N_16344_i) + ); + defparam com_cmm_u_cmm_dataproducer_byte_04_17_i_0_0_0_5_.INIT = 4'h4; + LUT2_L com_cmm_u_cmm_dataproducer_byte_04_17_i_0_0_0_5_ ( + .I0(com_cmm_u_cmm_dataproducer_byte_04_17_i_0_0_0_a2[0]), + .I1(NlwRenamedSig_OI_cfg_bus_number[5]), + .LO(com_cmm_u_cmm_dataproducer_N_16342_i) + ); + defparam com_cmm_u_cmm_dataproducer_byte_04_17_i_0_0_0_4_.INIT = 4'h4; + LUT2_L com_cmm_u_cmm_dataproducer_byte_04_17_i_0_0_0_4_ ( + .I0(com_cmm_u_cmm_dataproducer_byte_04_17_i_0_0_0_a2[0]), + .I1(NlwRenamedSig_OI_cfg_bus_number[4]), + .LO(com_cmm_u_cmm_dataproducer_N_16340_i) + ); + defparam com_cmm_u_cmm_dataproducer_byte_04_17_i_0_0_0_3_.INIT = 4'h4; + LUT2_L com_cmm_u_cmm_dataproducer_byte_04_17_i_0_0_0_3_ ( + .I0(com_cmm_u_cmm_dataproducer_byte_04_17_i_0_0_0_a2[0]), + .I1(NlwRenamedSig_OI_cfg_bus_number[3]), + .LO(com_cmm_u_cmm_dataproducer_N_16338_i) + ); + defparam com_cmm_u_cmm_dataproducer_byte_06_21_0_a2_0_a2_0_a2_0_a2_3_.INIT = 4'h8; + LUT2_L com_cmm_u_cmm_dataproducer_byte_06_21_0_a2_0_a2_0_a2_0_a2_3_ ( + .I0(com_cmm_u_cmm_dataproducer_N_48879_i), + .I1(com_cmm_data_errmanager[40]), + .LO(com_cmm_u_cmm_dataproducer_byte_06_21_3_) + ); + defparam com_cmm_u_cmm_dataproducer_byte_06_21_0_a2_0_a2_0_a2_0_a2_2_.INIT = 4'h8; + LUT2_L com_cmm_u_cmm_dataproducer_byte_06_21_0_a2_0_a2_0_a2_0_a2_2_ ( + .I0(com_cmm_u_cmm_dataproducer_N_48879_i), + .I1(com_cmm_data_errmanager[39]), + .LO(com_cmm_u_cmm_dataproducer_byte_06_21_2_) + ); + defparam com_cmm_u_cmm_dataproducer_byte_06_21_0_a2_0_a2_0_a2_0_a2_1_.INIT = 4'h8; + LUT2_L com_cmm_u_cmm_dataproducer_byte_06_21_0_a2_0_a2_0_a2_0_a2_1_ ( + .I0(com_cmm_u_cmm_dataproducer_N_48879_i), + .I1(com_cmm_data_errmanager[38]), + .LO(com_cmm_u_cmm_dataproducer_byte_06_21_1_) + ); + defparam com_cmm_u_cmm_dataproducer_byte_06_21_0_a2_0_a2_0_a2_0_a2_0_.INIT = 4'h8; + LUT2_L com_cmm_u_cmm_dataproducer_byte_06_21_0_a2_0_a2_0_a2_0_a2_0_ ( + .I0(com_cmm_u_cmm_dataproducer_N_48879_i), + .I1(com_cmm_data_errmanager[37]), + .LO(com_cmm_u_cmm_dataproducer_byte_06_21_0_) + ); + defparam com_cmm_u_cmm_dataproducer_byte_11_17_0_a2_0_a2_0_a2_0_a2_7_.INIT = 16'hA280; + LUT4_L com_cmm_u_cmm_dataproducer_byte_11_17_0_a2_0_a2_0_a2_0_a2_7_ ( + .I0(com_cmm_u_cmm_dataproducer_N_50471), + .I1(com_cmm_u_cmm_dataproducer_byte_11_17_m0_0_a2_i_0_0_o2[0]), + .I2(com_cmm_msi_haddr[7]), + .I3(com_cmm_msi_laddr[7]), + .LO(com_cmm_u_cmm_dataproducer_byte_11_17[7]) + ); + defparam com_cmm_u_cmm_dataproducer_byte_11_17_0_6_.INIT = 16'hEA40; + LUT4_L com_cmm_u_cmm_dataproducer_byte_11_17_0_6_ ( + .I0(com_cmm_u_cmm_dataproducer_N_50471), + .I1(com_cmm_u_cmm_dataproducer_byte_11_17_m0_0_a2_i_0_0_o2[0]), + .I2(com_cmm_data_errmanager[47]), + .I3(com_cmm_u_cmm_dataproducer_byte_11_17_m0[6]), + .LO(com_cmm_u_cmm_dataproducer_byte_11_17[6]) + ); + defparam com_cmm_u_cmm_dataproducer_byte_11_17_0_5_.INIT = 16'hEA40; + LUT4_L com_cmm_u_cmm_dataproducer_byte_11_17_0_5_ ( + .I0(com_cmm_u_cmm_dataproducer_N_50471), + .I1(com_cmm_u_cmm_dataproducer_byte_11_17_m0_0_a2_i_0_0_o2[0]), + .I2(com_cmm_data_errmanager[46]), + .I3(com_cmm_u_cmm_dataproducer_byte_11_17_m0[5]), + .LO(com_cmm_u_cmm_dataproducer_byte_11_17[5]) + ); + defparam com_cmm_u_cmm_dataproducer_req_gnt_code_8_i_0_0_0_2_.INIT = 8'h0E; + LUT3_L com_cmm_u_cmm_dataproducer_req_gnt_code_8_i_0_0_0_2_ ( + .I0(com_cmm_u_cmm_dataproducer_req_gnt_code_8_i_0_0_0_o3[2]), + .I1(com_cmm_req_arbiter[2]), + .I2(com_cmm_u_cmm_dataproducer_req_gnt_state[0]), + .LO(com_cmm_u_cmm_dataproducer_N_14861_i) + ); + defparam com_cmm_u_cmm_dataproducer_req_gnt_code_8_i_0_0_0_1_.INIT = 16'h00D8; + LUT4_L com_cmm_u_cmm_dataproducer_req_gnt_code_8_i_0_0_0_1_ ( + .I0(com_cmm_u_cmm_dataproducer_req_gnt_code_8_i_0_0_0_o3[2]), + .I1(com_cmm_intr_req_type[1]), + .I2(com_cmm_req_arbiter[1]), + .I3(com_cmm_u_cmm_dataproducer_req_gnt_state[0]), + .LO(com_cmm_u_cmm_dataproducer_N_14859_i) + ); + defparam com_cmm_u_cmm_dataproducer_req_gnt_code_8_i_0_0_0_0_.INIT = 16'h00D8; + LUT4_L com_cmm_u_cmm_dataproducer_req_gnt_code_8_i_0_0_0_0_ ( + .I0(com_cmm_u_cmm_dataproducer_req_gnt_code_8_i_0_0_0_o3[2]), + .I1(com_cmm_intr_req_type[0]), + .I2(com_cmm_req_arbiter[0]), + .I3(com_cmm_u_cmm_dataproducer_req_gnt_state[0]), + .LO(com_cmm_u_cmm_dataproducer_N_14857_i) + ); + defparam com_cmm_u_cmm_dataproducer_req_gnt_state_4_ss0_i_0_0_0.INIT = 8'hC8; + LUT3_L com_cmm_u_cmm_dataproducer_req_gnt_state_4_ss0_i_0_0_0 ( + .I0(com_gnt_pkt_tx), + .I1(com_cmm_u_cmm_dataproducer_req_gnt_state[0]), + .I2(com_cmm_u_cmm_dataproducer_req_gnt_state[1]), + .LO(com_cmm_u_cmm_dataproducer_N_14855_i) + ); + defparam com_cmm_u_cmm_dataproducer_req_gnt_state_4s2_i_0_0_0.INIT = 16'h0054; + LUT4_L com_cmm_u_cmm_dataproducer_req_gnt_state_4s2_i_0_0_0 ( + .I0(com_cmm_u_cmm_dataproducer_N_49542), + .I1(com_cmm_u_cmm_dataproducer_pcie_link_state_d[0]), + .I2(com_cmm_u_cmm_dataproducer_req_gnt_state[0]), + .I3(com_cmm_u_cmm_dataproducer_req_gnt_state[1]), + .LO(com_cmm_u_cmm_dataproducer_N_14865_i) + ); + defparam com_cmm_u_cmm_dataproducer_req_gnt_code_8_i_0_0_0_1_0_3_.INIT = 16'h7F5F; + LUT4_L com_cmm_u_cmm_dataproducer_req_gnt_code_8_i_0_0_0_1_0_3_ ( + .I0(com_cmm_u_cmm_dataproducer_N_48988_i), + .I1(com_cmm_posnd_wr_pack), + .I2(com_cmm_req_arbiter[0]), + .I3(com_cmm_next_state11_1), + .LO(com_cmm_u_cmm_dataproducer_req_gnt_code_8_i_0_0_0_1_0[3]) + ); + FDC com_cmm_u_cmm_dataproducer_pcie_link_state_d_0_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_N_42917_i), + .Q(com_cmm_u_cmm_dataproducer_pcie_link_state_d[0]), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_dataproducer_gnt_arbiter ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_dataproducer_nxt_req_gnt_state38), + .Q(com_cmm_gnt_arbiter), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_dataproducer_byte_06_5_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_dataproducer_N_68506_i_5017), + .Q(com_cmm_tlp_data_45_), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_dataproducer_reg_req_pkt_tx ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_dataproducer_N_49557_i_5018), + .Q(com_req_pkt_tx), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_dataproducer_byte_06_7_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_dataproducer_byte_06_21_7_), + .Q(com_cmm_tlp_data_47_), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_dataproducer_byte_07_2_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_dataproducer_N_68167_i_5019), + .Q(com_cmm_tlp_data_34_), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_dataproducer_byte_07_1_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_dataproducer_N_68156_i_5020), + .Q(com_cmm_tlp_data_33_), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_dataproducer_byte_07_0_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_dataproducer_N_68155_i_5021), + .Q(com_cmm_tlp_data_32_), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_dataproducer_byte_09_1_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_dataproducer_N_68125_i_5022), + .Q(com_cmm_tlp_data_81_), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_dataproducer_byte_09_0_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_dataproducer_N_68124_i_5023), + .Q(com_cmm_tlp_data_80_), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_dataproducer_byte_08_7_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_dataproducer_N_68123_i_5024), + .Q(com_cmm_tlp_data_95_), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_dataproducer_byte_08_6_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_dataproducer_N_68122_i_5025), + .Q(com_cmm_tlp_data_94_), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_dataproducer_byte_08_5_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_dataproducer_N_68121_i_5026), + .Q(com_cmm_tlp_data_93_), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_dataproducer_byte_08_4_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_dataproducer_N_68120_i_5027), + .Q(com_cmm_tlp_data_92_), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_dataproducer_byte_08_3_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_dataproducer_N_68119_i_5028), + .Q(com_cmm_tlp_data_91_), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_dataproducer_byte_08_2_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_dataproducer_N_68118_i_5029), + .Q(com_cmm_tlp_data_90_), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_dataproducer_byte_08_1_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_dataproducer_N_68117_i_5030), + .Q(com_cmm_tlp_data_89_), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_dataproducer_byte_08_0_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_dataproducer_N_68116_i_5031), + .Q(com_cmm_tlp_data_88_), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_dataproducer_byte_07_7_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_dataproducer_byte_07_27[7]), + .Q(com_cmm_tlp_data_39_), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_dataproducer_byte_07_6_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_dataproducer_byte_07_27[6]), + .Q(com_cmm_tlp_data_38_), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_dataproducer_byte_07_5_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_dataproducer_N_68158_i_5032), + .Q(com_cmm_tlp_data_37_), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_dataproducer_byte_07_4_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_dataproducer_N_68561_i_5033), + .Q(com_cmm_tlp_data_36_), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_dataproducer_byte_07_3_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_dataproducer_N_68168_i_5034), + .Q(com_cmm_tlp_data_35_), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_dataproducer_bytes_12_to_15_0_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_dataproducer_bytes_12_to_15_17[0]), + .Q(com_cmm_tlp_data_96_), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_dataproducer_byte_10_7_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_dataproducer_N_68164_i_5035), + .Q(com_cmm_tlp_data_79_), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_dataproducer_byte_10_6_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_dataproducer_N_68137_i_5036), + .Q(com_cmm_tlp_data_78_), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_dataproducer_byte_10_5_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_dataproducer_N_68136_i_5037), + .Q(com_cmm_tlp_data_77_), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_dataproducer_byte_10_4_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_dataproducer_N_68135_i_5038), + .Q(com_cmm_tlp_data_76_), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_dataproducer_byte_10_3_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_dataproducer_N_68165_i_5039), + .Q(com_cmm_tlp_data_75_), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_dataproducer_byte_10_2_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_dataproducer_N_68134_i_5040), + .Q(com_cmm_tlp_data_74_), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_dataproducer_byte_10_1_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_dataproducer_N_68133_i_5041), + .Q(com_cmm_tlp_data_73_), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_dataproducer_byte_10_0_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_dataproducer_N_68132_i_5042), + .Q(com_cmm_tlp_data_72_), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_dataproducer_byte_09_7_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_dataproducer_N_68131_i_5043), + .Q(com_cmm_tlp_data_87_), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_dataproducer_byte_09_6_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_dataproducer_N_68130_i_5044), + .Q(com_cmm_tlp_data_86_), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_dataproducer_byte_09_5_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_dataproducer_N_68129_i_5045), + .Q(com_cmm_tlp_data_85_), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_dataproducer_byte_09_4_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_dataproducer_N_68128_i_5046), + .Q(com_cmm_tlp_data_84_), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_dataproducer_byte_09_3_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_dataproducer_N_68127_i_5047), + .Q(com_cmm_tlp_data_83_), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_dataproducer_byte_09_2_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_dataproducer_N_68126_i_5048), + .Q(com_cmm_tlp_data_82_), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_dataproducer_bytes_12_to_15_15_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_dataproducer_bytes_12_to_15_17[15]), + .Q(com_cmm_tlp_data_111_), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_dataproducer_bytes_12_to_15_14_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_dataproducer_bytes_12_to_15_17[14]), + .Q(com_cmm_tlp_data_110_), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_dataproducer_bytes_12_to_15_13_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_dataproducer_bytes_12_to_15_17[13]), + .Q(com_cmm_tlp_data_109_), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_dataproducer_bytes_12_to_15_12_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_dataproducer_bytes_12_to_15_17[12]), + .Q(com_cmm_tlp_data_108_), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_dataproducer_bytes_12_to_15_11_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_dataproducer_bytes_12_to_15_17[11]), + .Q(com_cmm_tlp_data_107_), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_dataproducer_bytes_12_to_15_10_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_dataproducer_bytes_12_to_15_17[10]), + .Q(com_cmm_tlp_data_106_), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_dataproducer_bytes_12_to_15_9_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_dataproducer_bytes_12_to_15_17[9]), + .Q(com_cmm_tlp_data_105_), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_dataproducer_bytes_12_to_15_8_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_dataproducer_bytes_12_to_15_17[8]), + .Q(com_cmm_tlp_data_104_), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_dataproducer_bytes_12_to_15_7_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_dataproducer_bytes_12_to_15_17[7]), + .Q(com_cmm_tlp_data_103_), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_dataproducer_bytes_12_to_15_6_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_dataproducer_bytes_12_to_15_17[6]), + .Q(com_cmm_tlp_data_102_), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_dataproducer_bytes_12_to_15_5_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_dataproducer_bytes_12_to_15_17[5]), + .Q(com_cmm_tlp_data_101_), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_dataproducer_bytes_12_to_15_4_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_dataproducer_bytes_12_to_15_17[4]), + .Q(com_cmm_tlp_data_100_), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_dataproducer_bytes_12_to_15_3_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_dataproducer_bytes_12_to_15_17[3]), + .Q(com_cmm_tlp_data_99_), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_dataproducer_bytes_12_to_15_2_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_dataproducer_bytes_12_to_15_17[2]), + .Q(com_cmm_tlp_data_98_), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_dataproducer_bytes_12_to_15_1_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_dataproducer_bytes_12_to_15_17[1]), + .Q(com_cmm_tlp_data_97_), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_dataproducer_bytes_12_to_15_30_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_dataproducer_bytes_12_to_15_17[30]), + .Q(com_cmm_tlp_data_126_), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_dataproducer_bytes_12_to_15_29_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_dataproducer_bytes_12_to_15_17[29]), + .Q(com_cmm_tlp_data_125_), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_dataproducer_bytes_12_to_15_28_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_dataproducer_bytes_12_to_15_17[28]), + .Q(com_cmm_tlp_data_124_), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_dataproducer_bytes_12_to_15_27_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_dataproducer_bytes_12_to_15_17[27]), + .Q(com_cmm_tlp_data_123_), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_dataproducer_bytes_12_to_15_26_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_dataproducer_bytes_12_to_15_17[26]), + .Q(com_cmm_tlp_data_122_), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_dataproducer_bytes_12_to_15_25_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_dataproducer_bytes_12_to_15_17[25]), + .Q(com_cmm_tlp_data_121_), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_dataproducer_bytes_12_to_15_24_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_dataproducer_bytes_12_to_15_17[24]), + .Q(com_cmm_tlp_data_120_), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_dataproducer_bytes_12_to_15_23_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_dataproducer_bytes_12_to_15_17[23]), + .Q(com_cmm_tlp_data_119_), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_dataproducer_bytes_12_to_15_22_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_dataproducer_bytes_12_to_15_17[22]), + .Q(com_cmm_tlp_data_118_), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_dataproducer_bytes_12_to_15_21_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_dataproducer_bytes_12_to_15_17[21]), + .Q(com_cmm_tlp_data_117_), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_dataproducer_bytes_12_to_15_20_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_dataproducer_bytes_12_to_15_17[20]), + .Q(com_cmm_tlp_data_116_), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_dataproducer_bytes_12_to_15_19_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_dataproducer_bytes_12_to_15_17[19]), + .Q(com_cmm_tlp_data_115_), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_dataproducer_bytes_12_to_15_18_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_dataproducer_bytes_12_to_15_17[18]), + .Q(com_cmm_tlp_data_114_), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_dataproducer_bytes_12_to_15_17[17]), + .Q(com_cmm_tlp_data_113_), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_dataproducer_bytes_12_to_15_16_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_dataproducer_bytes_12_to_15_17[16]), + .Q(com_cmm_tlp_data_112_), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_dataproducer_byte_04_2_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_dataproducer_N_16336_i), + .Q(com_cmm_tlp_data_58_), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_dataproducer_byte_04_1_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_dataproducer_N_16334_i), + .Q(com_cmm_tlp_data_57_), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_dataproducer_byte_04_0_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_dataproducer_N_16332_i), + .Q(com_cmm_tlp_data_56_), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_dataproducer_byte_01_6_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_dataproducer_N_48188_i), + .Q(com_cmm_tlp_data_22_), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_dataproducer_byte_01_5_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_dataproducer_N_48186_i), + .Q(com_cmm_tlp_data_21_), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_dataproducer_byte_01_4_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_dataproducer_N_48184_i), + .Q(com_cmm_tlp_data_20_), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_dataproducer_byte_03_0_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_dataproducer_N_68623_i), + .Q(com_tlp_data_0_), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_dataproducer_byte_00_5_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_dataproducer_N_68507_i_5049), + .Q(com_tlp_data_29_), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_dataproducer_byte_00_4_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_dataproducer_byte_00_19_i_i_0_0_i_a2[5]), + .Q(com_cmm_tlp_data_28_), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_dataproducer_byte_00_2_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(N_68622_i_235), + .Q(com_cmm_tlp_data_26_), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_dataproducer_byte_00_1_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_dataproducer_N_3727_i_0_a2_0_a3_i_0_i_a3_5050), + .Q(com_tlp_data_27_), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_dataproducer_byte_00_0_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_dataproducer_byte_00_1_sqmuxa_1), + .Q(com_cmm_tlp_data_24_), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_dataproducer_byte_02_5_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_dataproducer_N_68429_i_5051), + .Q(com_cmm_tlp_data_13_), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_dataproducer_byte_02_4_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_dataproducer_N_68428_i_5052), + .Q(com_cmm_tlp_data_12_), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_dataproducer_bytes_12_to_15_31_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_dataproducer_bytes_12_to_15_17[31]), + .Q(com_cmm_tlp_data_127_), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_dataproducer_byte_11_4_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_dataproducer_byte_11_17[4]), + .Q(com_cmm_tlp_data_68_), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_dataproducer_byte_11_3_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_dataproducer_byte_11_17[3]), + .Q(com_cmm_tlp_data_67_), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_dataproducer_byte_11_2_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_dataproducer_byte_11_17[2]), + .Q(com_cmm_tlp_data_66_), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_dataproducer_byte_11_1_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_dataproducer_byte_11_17[1]), + .Q(com_cmm_tlp_data_65_), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_dataproducer_byte_11_0_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_dataproducer_byte_11_17[0]), + .Q(com_cmm_tlp_data_64_), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_dataproducer_byte_05_7_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_dataproducer_N_16356_i), + .Q(com_cmm_tlp_data_55_), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_dataproducer_byte_05_6_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_dataproducer_N_16354_i), + .Q(com_cmm_tlp_data_54_), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_dataproducer_byte_05_5_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_dataproducer_N_16352_i), + .Q(com_cmm_tlp_data_53_), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_dataproducer_byte_05_4_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_dataproducer_N_16350_i), + .Q(com_cmm_tlp_data_52_), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_dataproducer_byte_05_3_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_dataproducer_N_16348_i), + .Q(com_cmm_tlp_data_51_), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_dataproducer_byte_04_7_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_dataproducer_N_16346_i), + .Q(com_cmm_tlp_data_63_), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_dataproducer_byte_04_6_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_dataproducer_N_16344_i), + .Q(com_cmm_tlp_data_62_), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_dataproducer_byte_04_5_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_dataproducer_N_16342_i), + .Q(com_cmm_tlp_data_61_), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_dataproducer_byte_04_4_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_dataproducer_N_16340_i), + .Q(com_cmm_tlp_data_60_), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_dataproducer_byte_04_3_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_dataproducer_N_16338_i), + .Q(com_cmm_tlp_data_59_), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_dataproducer_byte_06_3_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_dataproducer_byte_06_21_3_), + .Q(com_cmm_tlp_data_43_), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_dataproducer_byte_06_2_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_dataproducer_byte_06_21_2_), + .Q(com_cmm_tlp_data_42_), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_dataproducer_byte_06_1_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_dataproducer_byte_06_21_1_), + .Q(com_cmm_tlp_data_41_), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_dataproducer_byte_06_0_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_dataproducer_byte_06_21_0_), + .Q(com_cmm_tlp_data_40_), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_dataproducer_byte_11_7_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_dataproducer_byte_11_17[7]), + .Q(com_cmm_tlp_data_71_), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_dataproducer_byte_11_6_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_dataproducer_byte_11_17[6]), + .Q(com_cmm_tlp_data_70_), + .CLR(com_cmm_rst_267) + ); + FDC com_cmm_u_cmm_dataproducer_byte_11_5_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_dataproducer_byte_11_17[5]), + .Q(com_cmm_tlp_data_69_), + .CLR(com_cmm_rst_267) + ); + defparam com_cmm_u_cmm_dataproducer_req_gnt_code_8_i_0_0_0_3_.INIT = 16'h80D0; + LUT4_L com_cmm_u_cmm_dataproducer_req_gnt_code_8_i_0_0_0_3_ ( + .I0(com_cmm_req_arbiter[3]), + .I1(com_cmm_u_cmm_dataproducer_pcie_link_state_d[0]), + .I2(com_cmm_u_cmm_dataproducer_req_gnt_code_8_i_0_0_0_1[3]), + .I3(com_cmm_u_cmm_dataproducer_req_gnt_code_8_i_0_0_0_1_0[3]), + .LO(com_cmm_u_cmm_dataproducer_N_14863_i) + ); +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/pci_exp_4_lane_64b_dsport.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/pci_exp_4_lane_64b_dsport.v new file mode 100644 index 0000000..72eb8f1 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/pci_exp_4_lane_64b_dsport.v @@ -0,0 +1,187893 @@ +/************************************************************************** + * PCI Express Downstream Port - Netlist Simulation Model + *************************************************************************/ +// Copyright(C) 2008 by Xilinx, Inc. All rights reserved. +// This text/file contains proprietary, confidential +// information of Xilinx, Inc., is distributed under license +// from Xilinx, Inc., and may be used, copied and/or +// disclosed only pursuant to the terms of a valid license +// agreement with Xilinx, Inc. Xilinx hereby grants you +// a license to use this text/file solely for design, simulation, +// implementation and creation of design files limited +// to Xilinx devices or technologies. Use with non-Xilinx +// devices or technologies is expressly prohibited and +// immediately terminates your license unless covered by +// a separate agreement. +// +// Xilinx is providing this design, code, or information +// "as is" solely for use in developing programs and +// solutions for Xilinx devices. By providing this design, +// code, or information as one possible implementation of +// this feature, application or standard, Xilinx is making no +// representation that this implementation is free from any +// claims of infringement. You are responsible for +// obtaining any rights you may require for your implementation. +// Xilinx expressly disclaims any warranty whatsoever with +// respect to the adequacy of the implementation, including +// but not limited to any warranties or representations that this +// implementation is free from claims of infringement, implied +// warranties of merchantability or fitness for a particular +// purpose. +// +// Xilinx products are not intended for use in life support +// appliances, devices, or systems. Use in such applications are +// expressly prohibited. +// +// This copyright and support notice must be retained as part +// of this text at all times. (c) Copyright 1995-2008 Xilinx, Inc. +// All rights reserved. +//////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995-2008 Xilinx, Inc. All rights reserved. +//////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor: Xilinx +// \ \ \/ Version: I.31 +// \ \ Application: netgen +// / / Filename: pci_exp_4_lane_64b_dsport.v +// /___/ /\ Timestamp: Mon Jun 12 16:54:23 2006 +// \ \ / \ +// \___\/\___\ +// +// Command : -sim -ofmt verilog -ne -w -insert_glbl false -tm pci_exp_4_lane_64b_dsport pci_exp_4_lane_64b_dsport.ngc +// Device : 4vfx40ff672-10 +// Input file : pci_exp_4_lane_64b_dsport.ngc +// Output file : pci_exp_4_lane_64b_dsport.v +// # of Modules : 1 +// Design Name : pci_exp_4_lane_64b_dsport +// Xilinx : /build/xfndry/I.31/rtf +// +// Purpose: +// This verilog netlist is a verification model and uses simulation +// primitives which may not represent the true implementation of the +// device, however the netlist is functionally correct and should not +// be modified. This file cannot be synthesized and should only be used +// with supported simulation tools. +// +// Reference: +// Development System Reference Guide, Chapter 23 +// Synthesis and Simulation Design Guide, Chapter 6 +// +//////////////////////////////////////////////////////////////////////////////// + +`timescale 1 ns/1 ps + +module pci_exp_4_lane_64b_dsport ( + cfg_turnoff_ok_n, cfg_to_turnoff_n, trn_rdst_rdy_n, trn_tdst_dsc_n, cfg_err_posted_n, trn_tdst_rdy_n, cfg_trn_pending_n, cfg_err_cpl_timeout_n, +trn_rnp_ok_n, trn_reof_n, trn_terrfwd_n, cfg_interrupt_n, cfg_interrupt_rdy_n, cfg_err_ur_n, cfg_rd_en_n, trn_reset_n, cfg_err_ecrc_n, +cfg_err_cpl_abort_n, trn_rsrc_dsc_n, trn_clk, cfg_wr_en_n, trn_rerrfwd_n, trn_lnk_up_n, trn_rsof_n, trn_teof_n, cfg_rd_wr_done_n, trn_rsrc_rdy_n, +trn_tsrc_dsc_n, cfg_err_cor_n, sys_reset_n, trn_tsrc_rdy_n, sys_clk, cfg_err_cpl_unexpect_n, trn_tsof_n, cfg_pm_wake_n, cfg_byte_en_n, trn_rfc_ph_av, +trn_rd, trn_td, cfg_err_tlp_cpl_header, trn_rbar_hit_n, trn_rfc_cpld_av, cfg_lcommand, cfg_dstatus, trn_rrem_n, cfg_status, trn_rfc_cplh_av, +cfg_command, pci_exp_txn, pci_exp_txp, trn_trem_n, cfg_cfg, cfg_di, cfg_do, cfg_bus_number, cfg_device_number, cfg_dwaddr, trn_rfc_npd_av, +cfg_dcommand, trn_rfc_nph_av, cfg_pcie_link_state_n, cfg_function_number, cfg_lstatus, pci_exp_rxn, pci_exp_rxp, trn_rfc_pd_av, trn_tbuf_av +); + input cfg_turnoff_ok_n; + output cfg_to_turnoff_n; + input trn_rdst_rdy_n; + output trn_tdst_dsc_n; + input cfg_err_posted_n; + output trn_tdst_rdy_n; + input cfg_trn_pending_n; + input cfg_err_cpl_timeout_n; + input trn_rnp_ok_n; + output trn_reof_n; + input trn_terrfwd_n; + input cfg_interrupt_n; + output cfg_interrupt_rdy_n; + input cfg_err_ur_n; + input cfg_rd_en_n; + output trn_reset_n; + input cfg_err_ecrc_n; + input cfg_err_cpl_abort_n; + output trn_rsrc_dsc_n; + output trn_clk; + input cfg_wr_en_n; + output trn_rerrfwd_n; + output trn_lnk_up_n; + output trn_rsof_n; + input trn_teof_n; + output cfg_rd_wr_done_n; + output trn_rsrc_rdy_n; + input trn_tsrc_dsc_n; + input cfg_err_cor_n; + input sys_reset_n; + input trn_tsrc_rdy_n; + input sys_clk; + input cfg_err_cpl_unexpect_n; + input trn_tsof_n; + input cfg_pm_wake_n; + input [3 : 0] cfg_byte_en_n; + output [7 : 0] trn_rfc_ph_av; + output [63 : 0] trn_rd; + input [63 : 0] trn_td; + input [47 : 0] cfg_err_tlp_cpl_header; + output [6 : 0] trn_rbar_hit_n; + output [11 : 0] trn_rfc_cpld_av; + output [15 : 0] cfg_lcommand; + output [15 : 0] cfg_dstatus; + output [7 : 0] trn_rrem_n; + output [15 : 0] cfg_status; + output [7 : 0] trn_rfc_cplh_av; + output [15 : 0] cfg_command; + output [3 : 0] pci_exp_txn; + output [3 : 0] pci_exp_txp; + input [7 : 0] trn_trem_n; + input [1023 : 0] cfg_cfg; + input [31 : 0] cfg_di; + output [31 : 0] cfg_do; + output [7 : 0] cfg_bus_number; + output [4 : 0] cfg_device_number; + input [9 : 0] cfg_dwaddr; + output [11 : 0] trn_rfc_npd_av; + output [15 : 0] cfg_dcommand; + output [7 : 0] trn_rfc_nph_av; + output [2 : 0] cfg_pcie_link_state_n; + output [2 : 0] cfg_function_number; + output [15 : 0] cfg_lstatus; + input [3 : 0] pci_exp_rxn; + input [3 : 0] pci_exp_rxp; + output [11 : 0] trn_rfc_pd_av; + output [4 : 0] trn_tbuf_av; + wire NlwRenamedSig_OI_trn_clk; + wire NlwRenamedSig_OI_trn_reset_n; + wire NlwRenamedSig_OI_trn_lnk_up_n; + wire NlwRenamedSig_OI_cfg_status_4_; + wire NlwRenamedSig_OI_cfg_status_3_; + wire NlwRenamedSig_OI_cfg_status_8_; + wire NlwRenamedSig_OI_cfg_status_11_; + wire NlwRenamedSig_OI_cfg_status_12_; + wire NlwRenamedSig_OI_cfg_status_13_; + wire NlwRenamedSig_OI_cfg_status_14_; + wire NlwRenamedSig_OI_cfg_status_15_; + wire NlwRenamedSig_OI_cfg_command_0_; + wire NlwRenamedSig_OI_cfg_command_1_; + wire NlwRenamedSig_OI_cfg_command_2_; + wire NlwRenamedSig_OI_cfg_command_6_; + wire NlwRenamedSig_OI_cfg_command_8_; + wire NlwRenamedSig_OI_cfg_command_10_; + wire NlwRenamedSig_OI_cfg_dstatus_0_; + wire NlwRenamedSig_OI_cfg_dstatus_1_; + wire NlwRenamedSig_OI_cfg_dstatus_2_; + wire NlwRenamedSig_OI_cfg_dstatus_3_; + wire NlwRenamedSig_OI_cfg_dstatus_5_; + wire NlwRenamedSig_OI_cfg_lstatus_0_; + wire NlwRenamedSig_OI_cfg_lstatus_4_; + wire NlwRenamedSig_OI_cfg_lstatus_6_; + wire NlwRenamedSig_OI_cfg_lstatus_12_; + wire NlwRenamedSig_OI_cfg_lcommand_0_; + wire NlwRenamedSig_OI_cfg_lcommand_1_; + wire NlwRenamedSig_OI_cfg_lcommand_3_; + wire NlwRenamedSig_OI_cfg_lcommand_6_; + wire NlwRenamedSig_OI_cfg_lcommand_7_; + wire sys_clkz; + wire com_tlm_u_tlm_rx_data_snk_cur_length_0__2; + wire N_6610_i_3; + wire com_tlm_u_tlm_rx_data_snk_cur_length_1__4; + wire N_6611_i_5; + wire com_tlm_u_tlm_rx_data_snk_cur_length_2__6; + wire N_6612_i_7; + wire com_tlm_u_tlm_rx_data_snk_cur_length_3__8; + wire N_6613_i_9; + wire com_tlm_u_tlm_rx_data_snk_cur_length_4__10; + wire N_6614_i_11; + wire com_tlm_u_tlm_rx_data_snk_cur_length_8__12; + wire N_6618_i_13; + wire com_tlm_u_tlm_rx_data_snk_cur_length_9__14; + wire N_6619_i_15; + wire cfg_cfg_i_224_; + wire cfg_cfg_i_351_; + wire N_71018_i_16; + wire N_71026_i_17; + wire plm_link_up_2; + wire plm_link_up_0; + wire N_29556_i_1; + wire N_29556_i_0; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_5; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_3; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_4; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_2; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_3; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_1; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_2; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_0; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_1; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0; + wire N_14477_i; + wire N_14477_i_i_18; + wire I_5336_i_0_i_a3_0_a2_19; + wire N_60904_i_20; + wire N_22672_i; + wire N_22672_i_i_21; + wire N_22527_i; + wire N_22527_i_i_22; + wire N_14480_i; + wire N_14480_i_i_23; + wire N_28800_i; + wire N_28800_i_i_24; + wire N_22977_i; + wire N_22977_i_i_25; + wire N_15212_i; + wire N_15212_i_i_26; + wire N_28802_i; + wire N_28802_i_i_27; + wire N_22826; + wire N_22826_i_28; + wire N_15205_i; + wire N_15205_i_i_29; + wire I_5033_0_a2_0_a2_0_a3_0_a2_30; + wire N_60997_i_31; + wire I_5039_0_a2_0_a2_0_a3_0_a2_32; + wire N_60983_i_33; + wire I_5045_0_a2_0_a2_0_a3_0_a2_34; + wire N_61022_i_35; + wire I_5051_0_a2_0_a3_0_a2_36; + wire N_60976_i_37; + wire I_5129_0_a2_0_a2_0_a3_0_a2_38; + wire N_61091_i_39; + wire I_5135_0_a2_0_a2_0_a3_0_a2_40; + wire N_61134_i_41; + wire I_5141_0_a2_0_a2_0_a3_0_a2_42; + wire N_61135_i_43; + wire I_5147_0_a2_0_a2_0_a3_0_a2_44; + wire N_61136_i_45; + wire I_5377_0_a2_0_a2_0_a3_0_a2_46; + wire N_61092_i_47; + wire I_5383_0_a2_0_a2_0_a3_0_a2_48; + wire N_61137_i_49; + wire I_5389_0_a2_0_a2_0_a3_0_a2_50; + wire N_61138_i_51; + wire I_5395_0_a2_0_a2_0_a3_0_a2_52; + wire N_61139_i_53; + wire plm_link_up; + wire plm_link_up_i; + wire G_40016_54; + wire G_39751_55; + wire mgt_clk; + wire plm_rst; + wire G_40019_56; + wire G_40021_57; + wire G_39720_58; + wire G_40023_59; + wire G_39722_60; + wire G_40025_61; + wire G_39731_62; + wire G_39710_63; + wire G_39714_64; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_i_65; + wire G_39716_66; + wire plm_fsm_rc_counter_ts2_2_reg_rx_expired_67; + wire N_56155_i; + wire N_29556_i; + wire N_60915_i_68; + wire plm_fsm_rc_counter_ts2_0_reg_rx_expired_69; + wire N_56156_i; + wire N_60905_i_70; + wire plm_fsm_cc_counter0_reg_rx_expired_71; + wire N_56513_i; + wire N_15208_i_i_72; + wire plm_fsm_cc_counter2_reg_rx_expired_73; + wire N_28971_i_i_74; + wire plm_fsm_rl_counter0_reg_rx_expired_75; + wire plm_fsm_reg_state_13__76; + wire N_59396_1; + wire N_15210_i_i_77; + wire plm_fsm_cc_counter3_reg_rx_expired_78; + wire N_22826_1_0; + wire N_22825_i_79; + wire N_12128_1; + wire d16_i_m3_0_6_; + wire G_250_80; + wire G_470_81; + wire d64_i_m3_0_25_; + wire N_39_1; + wire N_3_1; + wire N_12123_1; + wire N_24; + wire N_51_1; + wire N_10_1; + wire N_12034_1; + wire c64_0_a2_0_a2_26_; + wire N_11858_1; + wire N_11847_1; + wire N_12061_1; + wire plm_fsm_pa_counter3_reg_rx_expired_82; + wire N_59114_2; + wire N_22668_i_1; + wire N_22668_i_i_83; + wire plm_fsm_pa_counter1_reg_rx_expired_84; + wire N_14474_i_1; + wire N_14474_1_i; + wire N_14474_i_i_85; + wire plm_rx2_link_pad; + wire plm_fsm_pa_counter2_reg_rx_expired_86; + wire N_59117_1; + wire N_22524_i_i_87; + wire N_129; + wire G_426_88; + wire com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_7_; + wire N_218; + wire N_175; + wire G_443_89; + wire d64_i_m2_i_m3_0_36_; + wire d64_i_m3_0_17_; + wire d64_i_m3_0_1_; + wire N_90; + wire d64_i_m3_0_18_; + wire d64_i_m3_0_4_; + wire d64_i_m3_0_3_; + wire N_108; + wire N_11870_1; + wire d64_i_m3_0_35_; + wire d64_i_m3_0_12_; + wire G_124_90; + wire G_386_0_91; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d64_16__92; + wire d16_i_m3_i_m3_0_0_; + wire G_319_93; + wire N_11961_1; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d64_19__94; + wire d16_i_m3_0_3_; + wire G_302_95; + wire N_12127_1; + wire G_469_96; + wire N_12088; + wire d64_i_m3_0_37_; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_initial_64_97; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d64_5__98; + wire N_140_1; + wire G_287_99; + wire plm_scr1_reg_lfsr_one_12__100; + wire plm_scr1_reg_lfsr_one_11__101; + wire plm_scr1_reg_lfsr_one_0__102; + wire G_417_103; + wire plm_tsi0_reg_dec7_6_; + wire plm_tsi0_reg_dec7_13_; + wire plm_tsi1_reg_dec8_7_; + wire plm_tsi1_reg_dec7_6_; + wire plm_tsi1_reg_dec7_13_; + wire plm_tsi0_reg_dec8_7_; + wire plm_tsi3_reg_dec8_7_; + wire plm_tsi3_reg_dec7_6_; + wire plm_tsi3_reg_dec7_13_; + wire plm_tsi2_reg_dec8_7_; + wire plm_tsi2_reg_dec7_6_; + wire plm_tsi2_reg_dec7_13_; + wire plm_tsi0_reg_dec8_0_; + wire plm_tsi1_reg_dec8_0_; + wire plm_tsi2_reg_dec8_0_; + wire plm_tsi3_reg_dec8_0_; + wire com_cmm_u_cmm_errman_wtd_cor_add_input_five_n_d_104; + wire com_cmm_u_cmm_errman_wtd_cor_add_input_three_n_d_105; + wire com_cmm_u_cmm_errman_wtd_cor_add_input_two_n_d_106; + wire m25_am_1_107; + wire m25_am_108; + wire com_cmm_u_cmm_errman_wtd_cor_add_input_one_d_109; + wire com_cmm_u_cmm_errman_wtd_cor_add_input_six_n_d_110; + wire m5_2_0_0_0_39292_111; + wire N_85925_i_112; + wire N_86751_i_113; + wire N_56980; + wire N_56983; + wire m16_i_0_0_4_114; + wire N_17347_i; + wire trn_tsof_n_i; + wire trn_terrfwd_n_i; + wire plm_dfm_deframe1_dword_empty; + wire plm_dfm_deframe1_qwfsm_reg_state_1__115; + wire plm_dfm_deframe1_qwfsm_reg_state_0__116; + wire m10_3_0_0_a3_117; + wire plm_dfm_deframe1_qwfsm_reg_state_7__118; + wire N_87771_i_119; + wire plm_dfm_deframe1_qwfsm_reg_state_6__120; + wire N_87770_i_121; + wire N_150; + wire N_201_i; + wire N_154_i_122; + wire N_2766; + wire N_202_i; + wire N_16_i_123; + wire com_cmm_cfg_wr_data_14_; + wire I_4983_0_a2_0_a2_0_a2_124; + wire com_cmm_cfg_wr_data_15_; + wire I_4978_0_a2_0_a2_0_a2_125; + wire com_cmm_cfg_wr_data_0_; + wire I_4973_0_a2_0_a2_0_a2_126; + wire com_cmm_cfg_wr_data_1_; + wire I_4968_0_a2_0_a2_0_a2_127; + wire com_cmm_cfg_wr_data_2_; + wire I_4963_0_a2_0_a2_0_a2_128; + wire com_cmm_cfg_wr_data_3_; + wire I_4958_0_a2_0_a2_0_a2_129; + wire com_cmm_cfg_wr_data_4_; + wire I_4953_0_a2_0_a2_0_a2_130; + wire com_cmm_cfg_wr_data_5_; + wire I_4948_0_a2_0_a2_0_a2_131; + wire com_cmm_cfg_wr_data_6_; + wire I_4943_0_a2_0_a2_0_a2_132; + wire com_cmm_cfg_wr_data_7_; + wire I_4938_0_a2_0_a2_0_a2_133; + wire com_cmm_cfg_wr_data_31_; + wire I_4933_0_a2_0_a2_0_a2_0_a2_134; + wire com_cmm_cfg_wr_data_16_; + wire I_4928_0_a2_0_a2_0_a2_135; + wire com_cmm_cfg_wr_data_17_; + wire I_4923_0_a2_0_a2_0_a2_136; + wire com_cmm_cfg_wr_data_18_; + wire I_4918_0_a2_0_a2_0_a2_137; + wire com_cmm_cfg_wr_data_19_; + wire I_4913_0_a2_0_a2_0_a2_138; + wire com_cmm_cfg_wr_data_20_; + wire I_4908_0_a2_0_a2_0_a2_0_a2_139; + wire com_cmm_cfg_wr_data_21_; + wire I_4903_0_a2_0_a2_0_a2_0_a2_140; + wire com_cmm_cfg_wr_data_22_; + wire I_4898_0_a2_0_a2_0_a2_0_a2_141; + wire com_cmm_cfg_wr_data_23_; + wire I_4893_0_a2_0_a2_0_a2_0_a2_142; + wire com_cmm_cfg_wr_data_8_; + wire I_4888_0_a2_0_a2_0_a2_0_a2_143; + wire com_cmm_cfg_wr_data_9_; + wire I_4883_0_a2_0_a2_0_a2_0_a2_144; + wire com_cmm_cfg_wr_data_10_; + wire I_4878_0_a2_0_a2_0_a2_0_a2_145; + wire com_cmm_cfg_wr_data_11_; + wire I_4873_0_a2_0_a2_0_a2_0_a2_146; + wire com_cmm_cfg_wr_data_12_; + wire I_4868_0_a2_0_a2_0_a2_147; + wire com_cmm_cfg_wr_data_13_; + wire I_4863_0_a2_0_a2_0_a2_148; + wire com_cmm_cfg_wr_data_28_; + wire I_4858_0_a2_0_a2_0_a2_0_a2_149; + wire com_cmm_cfg_wr_data_29_; + wire I_4853_0_a2_0_a2_0_a2_0_a2_150; + wire com_cmm_cfg_wr_data_30_; + wire I_4848_0_a2_0_a2_0_a2_0_a2_151; + wire I_4843_0_a2_0_a2_0_a2_152; + wire I_4838_0_a2_0_a2_0_a2_153; + wire I_4833_0_a2_0_a2_0_a2_154; + wire I_4828_0_a2_0_a2_0_a2_155; + wire I_4823_0_a2_0_a2_0_a2_156; + wire I_4818_0_a2_0_a2_0_a2_157; + wire I_4813_0_a2_0_a2_0_a2_158; + wire I_4808_0_a2_0_a2_0_a2_159; + wire I_4803_0_a2_0_a2_0_a2_160; + wire I_4798_0_a2_0_a2_0_a2_161; + wire I_4793_0_a2_0_a2_0_a2_162; + wire I_4788_0_a2_0_a2_0_a2_0_a2_163; + wire I_4783_0_a2_0_a2_0_a2_0_a2_164; + wire I_4778_0_a2_0_a2_0_a2_0_a2_165; + wire I_4773_0_a2_0_a2_0_a2_0_a2_166; + wire I_4768_0_a2_0_a2_0_a2_0_a2_167; + wire I_4763_0_a2_0_a2_0_a2_0_a2_168; + wire I_4758_0_a2_0_a2_0_a2_0_a2_169; + wire I_4753_0_a2_0_a2_0_a2_0_a2_170; + wire I_4748_0_a2_0_a2_0_a2_171; + wire I_4743_0_a2_0_a2_0_a2_172; + wire I_4738_0_a2_0_a2_0_a2_173; + wire I_4733_0_a2_0_a2_0_a2_174; + wire I_4728_0_a2_0_a2_0_a2_175; + wire I_4723_0_a2_0_a2_0_a2_176; + wire I_4718_0_a2_0_a2_0_a2_177; + wire I_4713_0_a2_0_a2_0_a2_178; + wire I_4708_0_a2_0_a2_0_a2_179; + wire I_4703_0_a2_0_a2_0_a2_180; + wire I_4698_0_a2_0_a2_0_a2_0_a2_181; + wire I_4693_0_a2_0_a2_0_a2_0_a2_182; + wire I_4688_0_a2_0_a2_0_a2_0_a2_183; + wire I_4683_0_a2_0_a2_0_a2_0_a2_184; + wire I_4678_0_a2_0_a2_0_a2_0_a2_185; + wire I_4673_0_a2_0_a2_0_a2_186; + wire I_4668_0_a2_0_a2_0_a2_0_a2_187; + wire I_4663_0_a2_0_a2_0_a2_0_a2_188; + wire I_4658_0_a2_0_a2_0_a2_0_a2_189; + wire I_4653_0_a2_0_a2_0_a2_0_a2_190; + wire I_4648_0_a2_0_a2_0_a2_0_a2_191; + wire I_4643_0_a2_0_a2_0_a2_0_a2_192; + wire I_4638_0_a2_0_a2_0_a2_0_a2_193; + wire I_4633_0_a2_0_a2_0_a2_0_a2_194; + wire I_4628_0_a2_0_a2_0_a2_195; + wire I_4623_0_a2_0_a2_0_a2_196; + wire I_4618_0_a2_0_a2_0_a2_197; + wire I_4613_0_a2_0_a2_0_a2_198; + wire I_4608_0_a2_0_a2_0_a2_199; + wire I_4603_0_a2_0_a2_0_a2_200; + wire I_4598_0_a2_0_a2_0_a2_201; + wire I_4593_0_a2_0_a2_0_a2_202; + wire I_4588_0_a2_0_a2_0_a2_203; + wire I_4583_0_a2_0_a2_0_a2_204; + wire I_4578_0_a2_0_a2_0_a2_0_a2_205; + wire I_4573_0_a2_0_a2_0_a2_0_a2_206; + wire I_4568_0_a2_0_a2_0_a2_0_a2_207; + wire I_4563_0_a2_0_a2_0_a2_0_a2_208; + wire I_4558_0_a2_0_a2_0_a2_209; + wire I_4553_0_a2_0_a2_0_a2_210; + wire I_4548_0_a2_0_a2_0_a2_211; + wire I_4543_0_a2_0_a2_0_a2_0_a2_212; + wire I_4538_0_a2_0_a2_0_a2_0_a2_213; + wire I_4533_0_a2_0_a2_0_a2_0_a2_214; + wire I_4528_0_a2_0_a2_0_a2_0_a2_215; + wire I_4523_0_a2_0_a2_0_a2_0_a2_216; + wire I_4518_0_a2_0_a2_0_a2_0_a2_217; + wire I_4513_0_a2_0_a2_0_a2_0_a2_218; + wire I_4508_0_a2_0_a2_0_a2_219; + wire I_4503_0_a2_0_a2_0_a2_220; + wire I_4498_0_a2_0_a2_0_a2_221; + wire I_4493_0_a2_0_a2_0_a2_222; + wire I_4488_0_a2_0_a2_0_a2_223; + wire I_4483_0_a2_0_a2_0_a2_224; + wire I_4478_0_a2_0_a2_0_a2_225; + wire I_4473_0_a2_0_a2_0_a2_226; + wire I_4468_0_a2_0_a2_0_a2_227; + wire I_4463_0_a2_0_a2_0_a2_228; + wire I_4458_0_a2_0_a2_0_a2_0_a2_229; + wire I_4453_0_a2_0_a2_0_a2_0_a2_230; + wire I_4448_0_a2_0_a2_0_a2_0_a2_231; + wire I_4443_0_a2_0_a2_0_a2_0_a2_232; + wire I_4438_0_a2_0_a2_0_a2_233; + wire I_4433_0_a2_0_a2_0_a2_234; + wire I_4428_0_a2_0_a2_0_a2_235; + wire I_4423_0_a2_0_a2_0_a2_236; + wire I_4418_0_a2_0_a2_0_a2_0_a2_237; + wire I_4413_0_a2_0_a2_0_a2_0_a2_238; + wire I_4408_0_a2_0_a2_0_a2_0_a2_239; + wire I_4403_0_a2_0_a2_0_a2_0_a2_240; + wire I_4398_0_a2_0_a2_0_a2_0_a2_241; + wire I_4393_0_a2_0_a2_0_a2_0_a2_242; + wire I_4388_0_a2_0_a2_0_a2_243; + wire I_4383_0_a2_0_a2_0_a2_244; + wire I_4378_0_a2_0_a2_0_a2_245; + wire I_4373_0_a2_0_a2_0_a2_246; + wire I_4368_0_a2_0_a2_0_a2_247; + wire I_4363_0_a2_0_a2_0_a2_248; + wire I_4358_0_a2_0_a2_0_a2_249; + wire I_4353_0_a2_0_a2_0_a2_250; + wire I_4348_0_a2_0_a2_0_a2_251; + wire I_4343_0_a2_0_a2_0_a2_252; + wire I_4338_0_a2_0_a2_0_a2_0_a2_253; + wire I_4333_0_a2_0_a2_0_a2_0_a2_254; + wire I_4328_0_a2_0_a2_0_a2_0_a2_255; + wire I_4323_0_a2_0_a2_0_a2_0_a2_256; + wire I_4318_0_a2_0_a2_0_a2_257; + wire I_4313_0_a2_0_a2_0_a2_258; + wire I_4308_0_a2_0_a2_0_a2_259; + wire I_4303_0_a2_0_a2_0_a2_260; + wire I_4298_0_a2_0_a2_0_a2_0_a2_261; + wire I_4293_0_a2_0_a2_0_a2_0_a2_262; + wire I_4288_0_a2_0_a2_0_a2_0_a2_263; + wire I_4283_0_a2_0_a2_0_a2_0_a2_264; + wire I_4278_0_a2_0_a2_0_a2_0_a2_265; + wire I_4273_0_a2_0_a2_0_a2_0_a2_266; + wire I_4268_0_a2_0_a2_0_a2_267; + wire I_4263_0_a2_0_a2_0_a2_268; + wire I_4258_0_a2_0_a2_0_a2_269; + wire I_4253_0_a2_0_a2_0_a2_270; + wire I_4248_0_a2_0_a2_0_a2_271; + wire I_4243_0_a2_0_a2_0_a2_272; + wire I_4238_0_a2_0_a2_0_a2_273; + wire I_4233_0_a2_0_a2_0_a2_274; + wire I_4228_0_a2_0_a2_0_a2_275; + wire I_4223_0_a2_0_a2_0_a2_276; + wire I_4218_0_a2_0_a2_0_a2_277; + wire I_4213_0_a2_0_a2_0_a2_278; + wire I_4208_0_a2_0_a2_0_a2_0_a2_279; + wire I_4203_0_a2_0_a2_0_a2_0_a2_280; + wire I_4198_0_a2_0_a2_0_a2_0_a2_281; + wire I_4193_0_a2_0_a2_0_a2_0_a2_282; + wire I_4188_0_a2_0_a2_0_a2_283; + wire I_4183_0_a2_0_a2_0_a2_284; + wire I_4178_0_a2_0_a2_0_a2_285; + wire I_4173_0_a2_0_a2_0_a2_286; + wire I_4168_0_a2_0_a2_0_a2_0_a2_287; + wire I_4163_0_a2_0_a2_0_a2_0_a2_288; + wire I_4158_0_a2_0_a2_0_a2_0_a2_289; + wire I_4153_0_a2_0_a2_0_a2_0_a2_290; + wire I_4148_0_a2_0_a2_0_a2_0_a2_291; + wire N_56022_i; + wire com_tlm_cmmt_err_rbuf_overflow; + wire com_tlm_cmmt_err_tlp_malformed; + wire m4_1_292; + wire N_5_i; + wire N_57661; + wire m12_0_39395_293; + wire N_13_i; + wire N_56469_i; + wire com_cmm_u_cmm_errman_wtd_ftl_to_incrdf2; + wire m4_3_0_0_0_0_a2_0_294; + wire N_86294_i_295; + wire cfg_trn_pending_n_i; + wire com_cmm_u_cmm_errman_wtd_nfl_add_input_five_n_d_296; + wire com_cmm_u_cmm_errman_wtd_nfl_add_input_four_n_d_297; + wire com_cmm_u_cmm_errman_wtd_nfl_add_input_one_d_298; + wire com_cmm_u_cmm_errman_wtd_nfl_add_input_two_n_d_299; + wire N_6_i_300; + wire com_cmm_u_cmm_errman_wtd_nfl_to_incr_0df1; + wire com_cmm_u_cmm_errman_wtd_nfl_to_incr_0df2; + wire m7_0_301; + wire m3_0_302; + wire m24_303; + wire N_78313_i_304; + wire m13_0_305; + wire m17_1_306; + wire com_cmm_u_cmm_errman_wtd_cor_to_incr_0df1; + wire N_19_1; + wire d64_i_m3_0_6_; + wire d64_i_m3_0_47_; + wire N_19; + wire I_5354_0_a2_i_i_a3_0_a2_307; + wire I_5318_i_0_i_a3_0_a2_308; + wire N_56029_i; + wire plm_fsm_rc_counter_ts2_1_reg_rx_expired_309; + wire plm_rx1_ts2_c; + wire N_15208_i; + wire plm_fsm_cc_counter1_reg_rx_expired_310; + wire N_28971_i; + wire N_15210_i; + wire m25_bm_311; + wire com_cmm_u_cmm_errman_wtd_cor_to_incr_0df2; + wire N_22825; + wire N_56043_i; + wire N_56124_i; + wire plm_fsm_rl_counter3_reg_rx_expired_312; + wire N_56030_i; + wire N_56125_i; + wire plm_fsm_rl_counter2_reg_rx_expired_313; + wire N_56126_i; + wire plm_fsm_rl_counter1_reg_rx_expired_314; + wire plm_fsm_rc_counter_ts1_2_reg_rx_expired_315; + wire plm_rx2_ts1_c; + wire plm_fsm_rc_counter_ts1_1_reg_rx_expired_316; + wire plm_rx1_ts1_c; + wire plm_fsm_rc_counter_ts1_3_reg_rx_expired_317; + wire plm_rx3_ts1_c; + wire N_56052_i; + wire plm_fsm_rc_counter_ts1_0_reg_rx_expired_318; + wire plm_rx0_ts1_c; + wire plm_fsm_rc_counter_ts2_3_reg_rx_expired_319; + wire plm_rx2_ts2_c; + wire plm_rx0_ts2_c; + wire m12_0_o3_0_320; + wire G_372_1_321; + wire N_14; + wire G_372_322; + wire N_64; + wire G_7_323; + wire d64_i_m3_0_21_; + wire G_473_324; + wire G_374_0_325; + wire N_3; + wire N_33; + wire G_4_326; + wire G_479_327; + wire N_41; + wire N_160_1; + wire G_403_328; + wire N_12; + wire N_12071_1; + wire G_413_329; + wire G_460_1_1_330; + wire N_11843_1; + wire d64_i_m2_i_m3_0_59_; + wire G_370_331; + wire N_141_1; + wire G_2_332; + wire d64_i_m3_0_7_; + wire G_485_333; + wire N_11978_1; + wire N_12047_1; + wire d16_i_m3_0_2_; + wire G_386_334; + wire N_36; + wire G_24_335; + wire G_373_336; + wire G_9_337; + wire G_14_338; + wire c64_0_a2_0_a2_1_; + wire G_393_339; + wire N_58_1; + wire G_3_340; + wire N_12175_1; + wire d64_i_m3_i_m3_0_60_; + wire G_499_341; + wire N_12029_1; + wire G_371_342; + wire N_32; + wire G_378_343; + wire N_30; + wire G_404_344; + wire N_91_1; + wire N_11848_1; + wire G_460_345; + wire G_5_346; + wire G_465_347; + wire N_56103_i; + wire N_57268; + wire m16_i_0_0_2_348; + wire N_9901; + wire N_47431_i; + wire N_56042_i_1; + wire plm_rx3_ts2_c; + wire I_5184_i_0_0_0_o2_4_349; + wire I_5184_i_0_0_0_o2_5_350; + wire N_9903; + wire N_56053_i; + wire com_cmm_rst_351; + wire G_2710_0_a2_0_a2_0_a2_0_a2_352; + wire N_9900; + wire N_55989_i; + wire I_5202_i_0_0_0_o3_4_353; + wire I_5202_i_0_0_0_o3_5_354; + wire N_9902; + wire c64_0_a2_0_a2_2_; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d64_15__355; + wire G_459_356; + wire d64_i_m3_0_20_; + wire G_380_357; + wire G_298_358; + wire N_12045_1; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d64_30__359; + wire G_387_360; + wire G_297_361; + wire N_12129_1; + wire G_388_362; + wire G_368_363; + wire d64_i_m3_0_15_; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d64_4__364; + wire G_487_365; + wire G_486_2_366; + wire G_486_367; + wire G_249_368; + wire N_11969_1; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d64_29__369; + wire G_401_0_370; + wire N_12048_1; + wire d16_i_m3_i_m3_0_15_; + wire G_401_371; + wire N_112_1; + wire c64_0_a2_0_a2_17_; + wire G_389_372; + wire N_12128_2; + wire N_12149_1; + wire G_491_373; + wire N_11977_2; + wire N_12105_1; + wire N_31590_i_0; + wire N_31587_i_0; + wire G_484_374; + wire m16_i_0_0_1_375; + wire N_114; + wire N_130; + wire G_522_376; + wire N_133; + wire G_127_377; + wire G_392_378; + wire G_149_379; + wire G_397_380; + wire N_136; + wire G_112_381; + wire N_12083_1; + wire G_425_382; + wire G_453_2_383; + wire N_118; + wire G_111_384; + wire G_453_385; + wire G_452_2_386; + wire N_180; + wire com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_29_; + wire G_452_387; + wire G_450_2_388; + wire N_176; + wire com_llm_llm_rx_top_rx_data_61_; + wire G_450_389; + wire N_232; + wire N_11897; + wire com_llm_llm_tx_top_tx_dllp_td_27_; + wire com_llm_llm_tx_top_tx_dllp_td_28_; + wire N_12090; + wire N_12109_1; + wire com_llm_llm_tx_top_tx_dllp_td_25_; + wire com_llm_llm_tx_top_tx_dllp_td_26_; + wire com_llm_llm_tx_top_tx_dllp_td_40_; + wire N_12109; + wire G_462_1_1; + wire N_220; + wire N_12120; + wire N_177; + wire com_llm_llm_tx_top_tx_dllp_td_38_; + wire N_12082; + wire N_179; + wire N_219; + wire com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_39_; + wire G_442_390; + wire d64_i_m3_0_33_; + wire d64_i_m2_i_m3_0_27_; + wire d64_i_m3_0_52_; + wire G_486_1_391; + wire d64_i_m3_0_0_; + wire d64_i_m3_0_23_; + wire d64_i_m2_i_m3_0_26_; + wire G_429_392; + wire d16_i_m3_0_8_; + wire d16_i_m3_i_m3_0_14_; + wire N_11972_1; + wire d16_i_m3_i_m3_0_13_; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d64_22__393; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d64_18__394; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d64_24__395; + wire G_251_396; + wire d64_i_m3_0_13_; + wire c64_0_a2_0_a2_10_; + wire G_156_397; + wire d64_i_m3_0_11_; + wire d64_i_m3_0_14_; + wire G_121_398; + wire d64_i_m3_0_16_; + wire N_142; + wire d64_i_m3_i_m3_0_49_; + wire G_70_399; + wire N_75_1; + wire d64_i_m3_0_19_; + wire N_75; + wire d64_i_m3_0_34_; + wire N_77; + wire N_78; + wire d64_i_m3_0_8_; + wire d64_i_m3_i_m3_0_30_; + wire N_79; + wire N_90_1; + wire N_89; + wire N_92_1; + wire N_92; + wire N_107_1; + wire N_107; + wire N_112; + wire d64_i_m3_0_29_; + wire d64_i_m3_0_58_; + wire d64_i_m3_0_5_; + wire d64_i_m3_0_24_; + wire N_37; + wire G_36_0_400; + wire c64_0_a2_0_a2_3_; + wire N_40; + wire N_42_1; + wire N_42; + wire N_51; + wire d64_i_m3_0_22_; + wire d64_i_m3_0_28_; + wire N_53; + wire N_55; + wire d64_i_m3_0_55_; + wire N_57; + wire N_58; + wire N_12033_1; + wire N_60; + wire N_61; + wire N_62; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d64_28__401; + wire N_35_1; + wire c64_0_a2_0_a2_27_; + wire N_15; + wire d64_i_m3_0_9_; + wire d64_i_m3_i_m3_0_31_; + wire N_23; + wire c64_0_a2_0_a2_23_; + wire N_87_1; + wire N_22; + wire N_12116_1; + wire d64_i_m3_i_m3_0_48_; + wire N_52; + wire d64_i_m3_0_2_; + wire d64_i_m3_0_10_; + wire G_6_402; + wire N_59; + wire N_11845_1; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d64_20__403; + wire G_122_404; + wire N_65_1; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d64_7__405; + wire N_65; + wire G_145_406; + wire G_11_1_407; + wire G_11_408; + wire N_66; + wire N_87; + wire N_11842_1; + wire G_15_409; + wire N_50; + wire N_63; + wire N_91; + wire G_299_410; + wire G_301_411; + wire G_303_412; + wire N_11963_1; + wire G_305_413; + wire G_308_414; + wire G_313_415; + wire G_314_416; + wire G_375_417; + wire G_390_418; + wire G_471_419; + wire N_197; + wire com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_30_; + wire com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_35_; + wire G_513_420; + wire G_407_421; + wire G_427_422; + wire N_198; + wire com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_3_; + wire com_llm_llm_rx_top_rx_data_62_; + wire G_510_423; + wire N_22668_i; + wire N_14474_i; + wire N_56123_i; + wire N_56496_i; + wire plm_fsm_pa_counter0_reg_rx_expired_424; + wire plm_fsm_reg_state_1__425; + wire N_22524_i; + wire N_196; + wire com_llm_llm_tx_top_tx_dllp_td_30_; + wire com_llm_llm_tx_top_tx_dllp_td_35_; + wire N_12170; + wire N_184; + wire N_12181; + wire N_67; + wire N_12076; + wire com_cmml_protocol_err_n; + wire com_tlm_cmmt_err_flow_control; + wire N_58537; + wire com_cmm_pme_ack_bar; + wire N_12007_1_0; + wire plm_scr2_reg_lfsr_two_15__426; + wire G_349_427; + wire N_11867_1; + wire G_514_428; + wire G_457_1_429; + wire N_199_1; + wire G_457_430; + wire G_202_431; + wire com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_36_; + wire com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_49_; + wire com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_50_; + wire G_440_432; + wire G_203_433; + wire com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_4_; + wire com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_17_; + wire com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_18_; + wire G_439_434; + wire N_204; + wire N_217_1; + wire N_12182; + wire N_215; + wire N_12103; + wire N_12121; + wire N_181; + wire N_12124; + wire com_llm_llm_tx_top_tx_dllp_td_24_; + wire N_12165; + wire com_llm_llm_tx_top_tx_dllp_td_29_; + wire com_llm_llm_tx_top_tx_dllp_td_34_; + wire com_llm_llm_tx_top_tx_dllp_td_52_; + wire com_llm_llm_tx_top_tx_dllp_td_55_; + wire G_237_435; + wire com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_55_; + wire N_31577_i_0; + wire N_117; + wire N_12054_1; + wire N_12084_1; + wire N_12101_1; + wire G_454_436; + wire G_165_437; + wire G_461_438; + wire G_241_439; + wire com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_23_; + wire N_31578_i_0; + wire G_150_440; + wire G_468_441; + wire N_132; + wire N_189; + wire G_467_442; + wire N_146; + wire G_394_443; + wire G_391_0_444; + wire G_50_0_445; + wire d64_i_m3_0_42_; + wire G_84_0_446; + wire d64_i_m3_0_39_; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d64_26__447; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_13__448; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_45__449; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_start_high_latch_q_450; + wire N_31580_i; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_21__451; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_start_high_latch_452; + wire G_409_0_m3_0_453; + wire N_56031_i; + wire N_31638; + wire N_31643; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d64_23__454; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_0__455; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_32__456; + wire N_31629; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d64_8__457; + wire N_31794; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d64_0__458; + wire N_31640; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d64_21__459; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d64_27__460; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_12__461; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_44__462; + wire N_31762; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d64_31__463; + wire d64_i_m3_i_m3_0_62_; + wire d64_i_m3_0_50_; + wire d64_i_m3_0_44_; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d64_12__464; + wire d64_i_m3_0_54_; + wire d64_i_m3_0_57_; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d64_25__465; + wire d64_i_m3_0_41_; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d64_9__466; + wire N_113_1; + wire d64_i_m3_0_46_; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d64_14__467; + wire N_11862_1; + wire d64_i_m3_0_45_; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d64_13__468; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_14__469; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_46__470; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d64_17__471; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_6__472; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_38__473; + wire d64_i_m3_0_38_; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d64_6__474; + wire d64_i_m3_0_43_; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d64_11__475; + wire N_12127_2; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_2__476; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_34__477; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_3__478; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_35__479; + wire d64_i_m3_i_m3_0_61_; + wire com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_8_; + wire com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_15_; + wire com_llm_llm_rx_top_rx_data_57_; + wire com_llm_llm_rx_top_rx_data_58_; + wire com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_25_; + wire com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_26_; + wire com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_40_; + wire com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_47_; + wire G_482_480; + wire G_475_481; + wire plm_scr2_reg_lfsr_two_0__482; + wire plm_scr2_reg_lfsr_two_11__483; + wire plm_scr2_reg_lfsr_two_13__484; + wire plm_des2_reg_lfsr_two_0__485; + wire plm_des2_reg_lfsr_two_11__486; + wire plm_des2_reg_lfsr_two_13__487; + wire plm_des2_reg_lfsr_two_15__488; + wire G_351_489; + wire plm_scr0_reg_lfsr_two_0__490; + wire plm_scr0_reg_lfsr_two_11__491; + wire plm_scr0_reg_lfsr_two_13__492; + wire plm_scr0_reg_lfsr_two_15__493; + wire G_353_494; + wire N_12074_1; + wire plm_scr3_reg_lfsr_one_1__495; + wire plm_scr3_reg_lfsr_one_15__496; + wire G_329_497; + wire plm_scr3_reg_lfsr_one_3__498; + wire plm_scr3_reg_lfsr_one_13__499; + wire G_330_500; + wire N_12078_1; + wire plm_des1_reg_lfsr_one_1__501; + wire plm_des1_reg_lfsr_one_15__502; + wire G_331_503; + wire plm_des1_reg_lfsr_one_3__504; + wire plm_des1_reg_lfsr_one_13__505; + wire G_332_506; + wire N_12075_1; + wire plm_scr1_reg_lfsr_one_1__507; + wire plm_scr1_reg_lfsr_one_15__508; + wire G_333_509; + wire plm_scr1_reg_lfsr_one_3__510; + wire plm_scr1_reg_lfsr_one_13__511; + wire G_334_512; + wire N_12072_1; + wire plm_des3_reg_lfsr_one_1__513; + wire plm_des3_reg_lfsr_one_15__514; + wire G_335_515; + wire plm_des3_reg_lfsr_one_3__516; + wire plm_des3_reg_lfsr_one_13__517; + wire G_336_518; + wire N_12079_1; + wire plm_des2_reg_lfsr_one_1__519; + wire plm_des2_reg_lfsr_one_15__520; + wire G_337_521; + wire plm_des2_reg_lfsr_one_3__522; + wire plm_des2_reg_lfsr_one_13__523; + wire G_338_524; + wire plm_des3_reg_lfsr_two_0__525; + wire plm_des3_reg_lfsr_two_11__526; + wire plm_des3_reg_lfsr_two_13__527; + wire plm_des3_reg_lfsr_two_15__528; + wire G_339_529; + wire plm_des0_reg_lfsr_two_0__530; + wire plm_des0_reg_lfsr_two_11__531; + wire plm_des0_reg_lfsr_two_13__532; + wire plm_des0_reg_lfsr_two_15__533; + wire G_341_534; + wire N_12001_1; + wire plm_scr1_reg_lfsr_two_13__535; + wire plm_scr1_reg_lfsr_two_15__536; + wire G_343_537; + wire plm_scr3_reg_lfsr_two_0__538; + wire plm_scr3_reg_lfsr_two_11__539; + wire plm_scr3_reg_lfsr_two_13__540; + wire plm_scr3_reg_lfsr_two_15__541; + wire G_345_542; + wire plm_des1_reg_lfsr_two_0__543; + wire plm_des1_reg_lfsr_two_11__544; + wire plm_des1_reg_lfsr_two_13__545; + wire plm_des1_reg_lfsr_two_15__546; + wire G_347_547; + wire com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_1_; + wire com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_9_; + wire com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_16_; + wire G_279_548; + wire com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_33_; + wire com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_41_; + wire com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_48_; + wire G_280_549; + wire G_285_550; + wire G_286_551; + wire G_288_552; + wire G_290_553; + wire G_295_554; + wire N_12081_1; + wire plm_scr2_reg_lfsr_one_1__555; + wire plm_scr2_reg_lfsr_one_15__556; + wire G_323_557; + wire plm_scr2_reg_lfsr_one_3__558; + wire plm_scr2_reg_lfsr_one_13__559; + wire G_324_560; + wire plm_des0_reg_lfsr_one_0__561; + wire plm_des0_reg_lfsr_one_1__562; + wire plm_des0_reg_lfsr_one_11__563; + wire plm_des0_reg_lfsr_one_15__564; + wire G_325_565; + wire plm_des0_reg_lfsr_one_3__566; + wire plm_des0_reg_lfsr_one_13__567; + wire G_326_568; + wire N_12080_1; + wire plm_scr0_reg_lfsr_one_1__569; + wire plm_scr0_reg_lfsr_one_15__570; + wire G_327_571; + wire plm_scr0_reg_lfsr_one_3__572; + wire plm_scr0_reg_lfsr_one_13__573; + wire G_328_574; + wire N_11894_1; + wire G_236_575; + wire com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_24_; + wire com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_34_; + wire N_11899_1; + wire com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_2_; + wire G_255_576; + wire G_256_577; + wire com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_38_; + wire com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_53_; + wire G_259_578; + wire com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_6_; + wire com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_21_; + wire G_260_579; + wire com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_32_; + wire G_274_580; + wire com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_42_; + wire com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_44_; + wire com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_45_; + wire com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_10_; + wire com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_12_; + wire com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_13_; + wire N_11881_1; + wire G_204_581; + wire G_205_582; + wire N_212_1; + wire N_212; + wire G_207_583; + wire com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_14_; + wire com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_22_; + wire N_230; + wire N_231; + wire com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_54_; + wire G_227_584; + wire N_11888_1; + wire G_228_585; + wire N_11891_1; + wire G_233_586; + wire N_202_1; + wire N_173; + wire N_174_1; + wire N_174; + wire N_190; + wire N_11945_1; + wire N_200; + wire N_202; + wire G_151_587; + wire N_162; + wire N_163; + wire N_11871_1; + wire G_159_588; + wire N_165_1; + wire N_165; + wire N_11872_1; + wire G_161_589; + wire N_11876_1; + wire G_166_590; + wire N_135; + wire N_148; + wire N_11903_1; + wire G_245_591; + wire com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_46_; + wire G_222_592; + wire N_11975_1; + wire G_317_593; + wire com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_0_; + wire G_273_594; + wire N_31583_i_0; + wire G_316_595; + wire com_llm_llm_rx_top_rx_data_59_; + wire G_264_596; + wire com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_27_; + wire G_262_597; + wire plm_fsm_pc_counter2_reg_rx_expired_598; + wire plm_fsm_reg_state_2__599; + wire plm_fsm_pc_counter0_reg_rx_expired_600; + wire plm_fsm_pc_counter1_reg_rx_expired_601; + wire plm_fsm_pc_counter3_reg_rx_expired_602; + wire plm_fsm_reg_state_16__603; + wire plm_fsm_ri_counter3_reg_rx_expired_604; + wire plm_rx3_idl_c; + wire plm_fsm_ri_counter2_reg_rx_expired_605; + wire plm_rx2_idl_c; + wire plm_fsm_ri_counter1_reg_rx_expired_606; + wire plm_rx1_idl_c; + wire plm_fsm_ci_counter3_reg_rx_expired_607; + wire plm_fsm_reg_state_11__608; + wire plm_fsm_ci_counter2_reg_rx_expired_609; + wire plm_fsm_ci_counter1_reg_rx_expired_610; + wire plm_fsm_ri_counter0_reg_rx_expired_611; + wire plm_rx0_idl_c; + wire plm_fsm_ci_counter0_reg_rx_expired_612; + wire N_11916_1; + wire com_llm_llm_tx_top_tx_dllp_td_33_; + wire N_11916; + wire com_llm_llm_tx_top_tx_dllp_td_32_; + wire com_llm_llm_tx_top_tx_dllp_td_41_; + wire N_11906; + wire com_llm_llm_tx_top_tx_dllp_td_39_; + wire com_llm_llm_tx_top_tx_dllp_td_54_; + wire com_llm_llm_tx_top_tx_dllp_td_43_; + wire com_llm_llm_tx_top_tx_dllp_td_45_; + wire com_llm_llm_tx_top_tx_dllp_td_48_; + wire com_llm_llm_tx_top_tx_dllp_td_44_; + wire N_11936_1; + wire com_llm_llm_tx_top_tx_dllp_td_49_; + wire N_11936; + wire N_11933; + wire N_71; + wire N_70; + wire N_69; + wire N_49; + wire N_48; + wire N_47; + wire N_45; + wire N_44; + wire N_11864; + wire N_119; + wire N_103; + wire N_98; + wire N_97; + wire N_96; + wire N_94; + wire N_85; + wire N_83; + wire N_81_1; + wire N_81; + wire N_72; + wire N_221; + wire N_11934_1; + wire N_11885; + wire N_11884_1; + wire N_11884; + wire N_11877_1; + wire N_11877; + wire N_187; + wire N_186_1; + wire N_186; + wire N_185; + wire N_183; + wire N_182; + wire N_167; + wire N_12086; + wire N_11970_1; + wire N_11970; + wire N_11941; + wire N_11934; + wire N_11928; + wire N_11927_1; + wire N_11925; + wire N_11924_1; + wire N_11924; + wire N_11923; + wire N_11919; + wire N_222; + wire G_253_613; + wire G_252_614; + wire G_234_615; + wire com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_43_; + wire com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_11_; + wire com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_19_; + wire com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_51_; + wire N_194; + wire N_193; + wire N_191; + wire com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_37_; + wire com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_52_; + wire com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_5_; + wire com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_20_; + wire N_172; + wire G_164_616; + wire N_159; + wire N_157; + wire N_147; + wire N_137; + wire N_134; + wire com_llm_llm_tx_top_tx_dllp_td_42_; + wire com_llm_llm_tx_top_tx_dllp_td_53_; + wire N_11878; + wire N_82; + wire N_99; + wire N_11850; + wire N_188; + wire N_206; + wire N_223; + wire N_11926; + wire N_12043; + wire N_11947; + wire N_93; + wire N_95; + wire N_12156; + wire N_102; + wire N_12173; + wire N_11949; + wire N_11940_1; + wire N_11940; + wire N_11939_1; + wire N_11939; + wire N_11927; + wire N_152; + wire N_151; + wire N_143; + wire N_11851; + wire N_109; + wire N_104; + wire N_100; + wire N_86; + wire N_84; + wire N_80; + wire N_73; + wire N_68; + wire N_46; + wire N_43; + wire N_11973_1; + wire N_11973; + wire N_237_1; + wire N_237; + wire G_235_617; + wire N_11929_2; + wire G_271_618; + wire G_398_619; + wire plm_des3_reg_lfsr_one_12__620; + wire G_414_621; + wire plm_des0_reg_lfsr_one_12__622; + wire G_415_623; + wire plm_des1_reg_lfsr_one_12__624; + wire G_420_625; + wire plm_des3_reg_lfsr_two_3__626; + wire plm_des3_reg_lfsr_two_12__627; + wire plm_des3_reg_lfsr_two_14__628; + wire N_49072_i_0; + wire plm_rx1_lane_pad; + wire plm_rx1_link_pad; + wire plm_rx3_lane_pad; + wire plm_rx3_link_pad; + wire com_cmm_u_cmm_errman_wtd_cor_add_input_four_n_d_629; + wire m10_630; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_d64_c_q_2__631; + wire N_105; + wire N_11855; + wire N_11962; + wire N_12040; + wire N_12041; + wire N_12042; + wire N_12064; + wire N_12095; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_d64_c_q_5__632; + wire N_12099; + wire N_12104; + wire N_12167; + wire N_12169; + wire N_12147_1; + wire N_12088_1; + wire com_llm_llm_tx_top_tx_dllp_td_31_; + wire plm_rx0_lane_pad; + wire plm_rx0_link_pad; + wire com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_31_; + wire com_llm_llm_rx_top_rx_data_63_; + wire N_11904_1; + wire com_llm_llm_rx_top_rx_data_56_; + wire N_11901_1; + wire N_11902_1; + wire plm_scr1_reg_lfsr_two_0__633; + wire plm_scr1_reg_lfsr_two_11__634; + wire plm_des3_reg_lfsr_one_0__635; + wire plm_des3_reg_lfsr_one_11__636; + wire plm_scr3_reg_lfsr_one_0__637; + wire plm_scr3_reg_lfsr_one_11__638; + wire plm_des1_reg_lfsr_one_0__639; + wire plm_des1_reg_lfsr_one_11__640; + wire plm_des2_reg_lfsr_one_0__641; + wire plm_des2_reg_lfsr_one_11__642; + wire plm_scr0_reg_lfsr_one_0__643; + wire plm_scr0_reg_lfsr_one_11__644; + wire plm_scr2_reg_lfsr_one_0__645; + wire plm_scr2_reg_lfsr_one_11__646; + wire plm_des0_reg_lfsr_two_1__647; + wire plm_des0_reg_lfsr_two_2__648; + wire N_49163_i_0; + wire plm_des0_reg_lfsr_two_14__649; + wire N_49162_i_0; + wire plm_des0_reg_lfsr_one_14__650; + wire N_49160_i_0; + wire plm_des0_reg_lfsr_two_4__651; + wire N_49159_i_0; + wire plm_des1_reg_lfsr_two_14__652; + wire N_49152_i_0; + wire plm_des1_reg_lfsr_one_14__653; + wire N_49150_i_0; + wire plm_des1_reg_lfsr_two_4__654; + wire N_49149_i_0; + wire plm_des2_reg_lfsr_two_14__655; + wire N_49141_i_0; + wire plm_des2_reg_lfsr_one_14__656; + wire N_49139_i_0; + wire plm_des3_reg_lfsr_one_14__657; + wire N_49118_i_0; + wire plm_des1_reg_lfsr_two_1__658; + wire plm_des1_reg_lfsr_two_2__659; + wire N_49108_i_0; + wire plm_des3_reg_lfsr_two_4__660; + wire N_49107_i_0; + wire N_49085_i_0; + wire plm_des3_reg_lfsr_two_2__661; + wire N_49083_i_0; + wire plm_des2_reg_lfsr_two_1__662; + wire plm_des2_reg_lfsr_two_2__663; + wire N_49082_i_0; + wire plm_des2_reg_lfsr_two_4__664; + wire N_49081_i_0; + wire com_llm_llm_rx_top_rx_data_34_; + wire plm_scr0_reg_lfsr_two_1__665; + wire plm_scr0_reg_lfsr_two_2__666; + wire N_21118_i_0; + wire plm_scr2_reg_lfsr_two_14__667; + wire N_20991_i_0; + wire plm_scr2_reg_lfsr_two_1__668; + wire plm_scr2_reg_lfsr_two_12__669; + wire N_20990_i_0; + wire plm_scr2_reg_lfsr_two_3__670; + wire N_20989_i_0; + wire plm_scr2_reg_lfsr_two_4__671; + wire N_20988_i_0; + wire plm_scr3_reg_lfsr_two_1__672; + wire plm_scr3_reg_lfsr_two_2__673; + wire N_20852_i_0; + wire plm_scr2_reg_lfsr_two_2__674; + wire N_13591_i_0; + wire plm_scr2_reg_lfsr_one_14__675; + wire N_13489_i_0; + wire plm_scr1_reg_lfsr_two_14__676; + wire G_500_677; + wire G_477_678; + wire plm_scr1_reg_lfsr_two_1__679; + wire plm_scr1_reg_lfsr_two_2__680; + wire G_436_681; + wire plm_scr0_reg_lfsr_two_3__682; + wire plm_scr0_reg_lfsr_two_14__683; + wire G_410_684; + wire G_395_685; + wire plm_scr1_reg_lfsr_two_3__686; + wire G_366_687; + wire plm_scr0_reg_lfsr_one_14__688; + wire G_359_689; + wire plm_scr1_reg_lfsr_one_14__690; + wire G_357_691; + wire plm_scr3_reg_lfsr_one_14__692; + wire G_355_693; + wire plm_scr0_reg_lfsr_two_4__694; + wire G_354_695; + wire plm_scr1_reg_lfsr_two_4__696; + wire G_344_697; + wire G_294_698; + wire G_293_699; + wire G_272_700; + wire com_cmm_u_cmm_pm_dev_power_state_eq_d0; + wire plm_link_up_1; + wire l0_exit_reason_0_0_0_a2_2; + wire N_57535_i; + wire phy_tframe_l; + wire phy_tframe_h; + wire phy_tctrl_l; + wire phy_tctrl_h; + wire phy_rctrl_l; + wire phy_rctrl_h; + wire phy_rferr_l_n; + wire phy_rferr_h_n; + wire phy_rframe_l; + wire phy_rframe_h; + wire cmmp_receiver_err; + wire plm_link_l0; + wire N_62716_i; + wire phy_tstall_n_i; + wire trn_reset_n_i; + wire plm_frm_atomic; + wire plm_tx2_link_pad; + wire plm_tx0_link_pad; + wire plm_tx2_lane_pad; + wire plm_tx0_lane_pad; + wire plm_N_55932_i; + wire plm_N_3288; + wire plm_reg_sym_sent_6_; + wire plm_reg_sym_sent_5_; + wire plm_reg_sym_sent_0_; + wire plm_rx3_inverted; + wire plm_reg_ts1_1_2; + wire plm_reg_ts2_1_2; + wire plm_reg_rx_idl_1_2; + wire plm_rx3_linkctrl_0_; + wire plm_rx3_linkctrl_3_; + wire plm_rx2_lane_pad; + wire plm_rx2_inverted; + wire plm_reg_ts1_1_1; + wire plm_reg_ts2_1_1; + wire plm_reg_rx_idl_1_1; + wire plm_rx2_linkctrl_0_; + wire plm_rx2_linkctrl_3_; + wire plm_rx1_inverted; + wire plm_reg_ts1_1_0; + wire plm_reg_ts2_1_0; + wire plm_reg_rx_idl_1_0; + wire plm_rx1_linkctrl_0_; + wire plm_rx1_linkctrl_3_; + wire plm_rx0_inverted; + wire plm_reg_ts1_1; + wire plm_reg_ts2_1; + wire plm_reg_rx_idl_1; + wire plm_rx0_linkctrl_0_; + wire plm_rx0_linkctrl_3_; + wire plm_N_14376_i; + wire plm_N_14392_i; + wire plm_reg_dis; + wire plm_reg_disdes; + wire plm_VCC_701; + wire plm_chb_done; + wire plm_rx_clear_cs; + wire plm_N_11062_i; + wire plm_rx3_polarity; + wire plm_rx2_polarity; + wire plm_rx1_polarity; + wire plm_tx1_txinhibit; + wire plm_GND_702; + wire plm_rx0_polarity; + wire plm_N_61233_i_703; + wire plm_noscramble; + wire plm_phy_rbad_dfrm_l; + wire plm_phy_rbad_dfrm_h; + wire plm_un2_tstall_n_0_a2_0_704; + wire plm_reg_raw_tstall_d3_705; + wire plm_reg_raw_tstall_d2_706; + wire plm_raw_tstall; + wire plm_reg_raw_tstall_d1_707; + wire plm_un3_tstall_n_0_m3_0_708; + wire plm_phy_tstall_n; + wire plm_phy_cke_3_709; + wire plm_phy_cke_2_710; + wire plm_phy_cke_1_711; + wire plm_phy_cke_0_712; + wire plm_phy_cke; + wire plm_v4f_mgt_gt3_drdy; + wire plm_v4f_mgt_gt3_den; + wire plm_v4f_mgt_gt3_dwe; + wire plm_v4f_mgt_gt2_drdy; + wire plm_v4f_mgt_gt2_den; + wire plm_v4f_mgt_gt2_dwe; + wire plm_v4f_mgt_gt1_drdy; + wire plm_v4f_mgt_gt1_den; + wire plm_v4f_mgt_gt1_dwe; + wire plm_v4f_mgt_gt0_drdy; + wire plm_v4f_mgt_gt0_den; + wire plm_v4f_mgt_gt0_dwe; + wire plm_v4f_mgt_cal_clk; + wire plm_v4f_mgt_rx0_sigdet_n_async; + wire plm_v4f_mgt_rx0_sigdet_n_temp; + wire plm_v4f_mgt_rx1_sigdet_n_async; + wire plm_v4f_mgt_rx1_sigdet_n_temp; + wire plm_v4f_mgt_rx2_sigdet_n_async; + wire plm_v4f_mgt_rx2_sigdet_n_temp; + wire plm_v4f_mgt_rx3_sigdet_n_async; + wire plm_v4f_mgt_rx3_sigdet_n_temp; + wire plm_v4f_mgt_pma_txlock1; + wire plm_v4f_mgt_pma_txlock0; + wire plm_v4f_mgt_N_438_i; + wire plm_v4f_mgt_reset_delay_reg_tx_pcs_init_3_1; + wire plm_v4f_mgt_reg_tx_sync_5_i_0_o4_0; + wire plm_v4f_mgt_bond_success_713; + wire plm_v4f_mgt_reset_delay_reg_tx_sync_5_i_0_0_714; + wire plm_v4f_mgt_reset_delay_reg_tx_pcs_init_5_i_o2_0_o2_0_715; + wire plm_v4f_mgt_sys_init_n_0_a2_0_716; + wire plm_v4f_mgt_pma_txlock3; + wire plm_v4f_mgt_pma_txlock2; + wire plm_v4f_mgt_N_871_i; + wire plm_v4f_mgt_N_860_i; + wire plm_v4f_mgt_reset_delay_reg_tx_sync_5_i_0_a2_1_0; + wire plm_v4f_mgt_reset_delay_reg_tx_pcs_init_5_i_o2_0_o2_1_717; + wire plm_v4f_mgt_N_882_1; + wire plm_v4f_mgt_reset_delay_reg_tx_pcs_init_5_i_o2_0_o2_2_718; + wire plm_v4f_mgt_N_863_i; + wire plm_v4f_mgt_pma_rxlock3; + wire plm_v4f_mgt_pma_rxlock2; + wire plm_v4f_mgt_pma_rxlock1; + wire plm_v4f_mgt_pma_rxlock0; + wire plm_v4f_mgt_reset_delay_reg_tx_sync_5_i_0_3_719; + wire plm_v4f_mgt_reset_delay_reg_tx_sync_5_i_0_1_720; + wire plm_v4f_mgt_N_866_i; + wire plm_v4f_mgt_G_860_721; + wire plm_v4f_mgt_G_939_722; + wire plm_v4f_mgt_G_858_723; + wire plm_v4f_mgt_G_937_724; + wire plm_v4f_mgt_G_856_725; + wire plm_v4f_mgt_G_935_726; + wire plm_v4f_mgt_G_854_727; + wire plm_v4f_mgt_G_933_728; + wire plm_v4f_mgt_G_852_729; + wire plm_v4f_mgt_G_931_730; + wire plm_v4f_mgt_G_850_731; + wire plm_v4f_mgt_G_929_732; + wire plm_v4f_mgt_G_848_733; + wire plm_v4f_mgt_G_927_734; + wire plm_v4f_mgt_G_846_735; + wire plm_v4f_mgt_G_925_736; + wire plm_v4f_mgt_G_844_737; + wire plm_v4f_mgt_G_923_738; + wire plm_v4f_mgt_G_842_739; + wire plm_v4f_mgt_G_921_740; + wire plm_v4f_mgt_G_835_741; + wire plm_v4f_mgt_G_919_742; + wire plm_v4f_mgt_G_917_743; + wire plm_v4f_mgt_reg_phy_clk_toggle_i_744; + wire plm_v4f_mgt_reg_phy_clk_toggle_745; + wire plm_v4f_mgt_reg_mgt_clk_sample_746; + wire plm_v4f_mgt_reg_mgtdiv2_clk_sample_747; + wire plm_v4f_mgt_delta_detect_mgtdiv2_cke_reg_mgtdiv2_cke_phase1_3_748; + wire plm_v4f_mgt_reg_mgtdiv2_cke_phase1_749; + wire plm_v4f_mgt_mgtdiv2_clk; + wire plm_v4f_mgt_reg_mgtdiv2_clk_toggle_i_750; + wire plm_v4f_mgt_reg_mgtdiv2_clk_toggle_751; + wire plm_v4f_mgt_N_886_i; + wire plm_v4f_mgt_reg_rx3_pcs_init_752; + wire plm_v4f_mgt_N_885_i; + wire plm_v4f_mgt_reg_rx2_pcs_init_753; + wire plm_v4f_mgt_N_884_i; + wire plm_v4f_mgt_reg_rx1_pcs_init_754; + wire plm_v4f_mgt_N_883_i; + wire plm_v4f_mgt_reg_rx0_pcs_init_755; + wire plm_v4f_mgt_N_444_i; + wire plm_v4f_mgt_reg_tx_sync_756; + wire plm_v4f_mgt_sys_init_n_i_757; + wire plm_v4f_mgt_N_870_i; + wire plm_v4f_mgt_reg_tx_pcs_init_758; + wire plm_v4f_mgt_un3_reg_pma_cnt_axbxc2_759; + wire plm_v4f_mgt_un3_reg_pma_cnt_axbxc1_760; + wire plm_v4f_mgt_un3_reg_dcm_cnt_axbxc3_761; + wire plm_v4f_mgt_un3_reg_dcm_cnt_axbxc2_762; + wire plm_v4f_mgt_un3_reg_dcm_cnt_axbxc1_763; + wire plm_v4f_mgt_un3_reg_pma_cnt_axbxc3_764; + wire plm_v4f_mgt_dcm_delay_reg_dcm9_765; + wire plm_v4f_mgt_reg_dcm_766; + wire plm_v4f_mgt_pma_delay_reg_pma9_767; + wire plm_v4f_mgt_special_clk; + wire plm_v4f_mgt_reg_pma_768; + wire plm_v4f_mgt_sys_rst_n_i; + wire plm_v4f_mgt_dcm_lock_i_769; + wire plm_v4f_mgt_dcm_lock; + wire plm_v4f_mgt_clk_sel_by_4_i; + wire plm_v4f_mgt_N_2600_i; + wire plm_v4f_mgt_G_862_770; + wire plm_v4f_mgt_reg_tee0_dlyline_N_7; + wire plm_v4f_mgt_reg_tee1_dlyline_N_7; + wire plm_v4f_mgt_reg_tee2_dlyline_N_7; + wire plm_v4f_mgt_delta_detect_reg_phase1_3_771; + wire plm_v4f_mgt_dcm_clkf; + wire plm_v4f_mgt_dcm_clkd; + wire plm_v4f_mgt_dcm_clk0; + wire plm_v4f_mgt_rx3_enter_elecidle; + wire plm_v4f_mgt_rx2_enter_elecidle; + wire plm_v4f_mgt_rx1_enter_elecidle; + wire plm_v4f_mgt_pipe_phystatus; + wire plm_v4f_mgt_rx0_enter_elecidle; + wire plm_v4f_mgt_gt11_by4_GND_772; + wire plm_v4f_mgt_gt11_by4_VCC_773; + wire plm_v4f_mgt_for_v1_4_cal_inst0_N_1829_i_774; + wire plm_v4f_mgt_for_v1_4_cal_inst0_sd_state_0__775; + wire plm_v4f_mgt_for_v1_4_cal_inst0_sd_req_776; + wire plm_v4f_mgt_for_v1_4_cal_inst0_cb_statec_i_i_777; + wire plm_v4f_mgt_for_v1_4_cal_inst0_cb_statec_i; + wire plm_v4f_mgt_for_v1_4_cal_inst0_N_1816_i_778; + wire plm_v4f_mgt_for_v1_4_cal_inst0_N_1828_i_779; + wire plm_v4f_mgt_for_v1_4_cal_inst0_N_1827_i_780; + wire plm_v4f_mgt_for_v1_4_cal_inst0_N_1661_i; + wire plm_v4f_mgt_for_v1_4_cal_inst0_N_1015_i; + wire plm_v4f_mgt_for_v1_4_cal_inst0_N_1662_i; + wire plm_v4f_mgt_for_v1_4_cal_inst0_N_2448_i_781; + wire plm_v4f_mgt_for_v1_4_cal_inst0_sd_state_13__782; + wire plm_v4f_mgt_for_v1_4_cal_inst0_sd_state_12__783; + wire plm_v4f_mgt_for_v1_4_cal_inst0_sd_next_state_0_sqmuxa_3; + wire plm_v4f_mgt_for_v1_4_cal_inst0_sd_state_11__784; + wire plm_v4f_mgt_for_v1_4_cal_inst0_N_1686_i_785; + wire plm_v4f_mgt_for_v1_4_cal_inst0_sd_state_10__786; + wire plm_v4f_mgt_for_v1_4_cal_inst0_sd_state_9__787; + wire plm_v4f_mgt_for_v1_4_cal_inst0_sd_next_state_0_sqmuxa_2; + wire plm_v4f_mgt_for_v1_4_cal_inst0_N_2449_i_788; + wire plm_v4f_mgt_for_v1_4_cal_inst0_sd_state_8__789; + wire plm_v4f_mgt_for_v1_4_cal_inst0_sd_state_7__790; + wire plm_v4f_mgt_for_v1_4_cal_inst0_N_1688_i_791; + wire plm_v4f_mgt_for_v1_4_cal_inst0_sd_state_6__792; + wire plm_v4f_mgt_for_v1_4_cal_inst0_sd_state_5__793; + wire plm_v4f_mgt_for_v1_4_cal_inst0_sd_next_state_0_sqmuxa_1; + wire plm_v4f_mgt_for_v1_4_cal_inst0_sd_state_4__794; + wire plm_v4f_mgt_for_v1_4_cal_inst0_N_1689_i; + wire plm_v4f_mgt_for_v1_4_cal_inst0_sd_state_3__795; + wire plm_v4f_mgt_for_v1_4_cal_inst0_sd_drp_done_796; + wire plm_v4f_mgt_for_v1_4_cal_inst0_drp_next_state_0_sqmuxa; + wire plm_v4f_mgt_for_v1_4_cal_inst0_N_2393_i_797; + wire plm_v4f_mgt_for_v1_4_cal_inst0_drp_state_3__798; + wire plm_v4f_mgt_for_v1_4_cal_inst0_drp_state_1__799; + wire plm_v4f_mgt_for_v1_4_cal_inst0_drp_next_state_0_sqmuxa_1; + wire plm_v4f_mgt_for_v1_4_cal_inst0_sd_write_800; + wire plm_v4f_mgt_for_v1_4_cal_inst0_N_1013_i; + wire plm_v4f_mgt_for_v1_4_cal_inst0_sd_read_801; + wire plm_v4f_mgt_for_v1_4_cal_inst0_N_2439_i_802; + wire plm_v4f_mgt_for_v1_4_cal_inst0_drp_state_4__803; + wire plm_v4f_mgt_for_v1_4_cal_inst0_drp_state_0__804; + wire plm_v4f_mgt_for_v1_4_cal_inst0_sd_req_3_0_a2_0_a2_805; + wire plm_v4f_mgt_for_v1_4_cal_inst0_gt_drdy_r_806; + wire plm_v4f_mgt_for_v1_4_cal_inst0_N_2438_i_807; + wire plm_v4f_mgt_for_v1_4_cal_inst0_GND_808; + wire plm_v4f_mgt_for_v1_4_cal_inst0_N_2450_i_809; + wire plm_v4f_mgt_for_v1_4_cal_inst0_N_1642_i; + wire plm_v4f_mgt_for_v1_4_cal_inst0_gt_do_r_4_i_m2_0_a2_0_a2_2_15_; + wire plm_v4f_mgt_for_v1_4_cal_inst0_gt_do_r_4_i_m2_0_a2_0_a2_2_14_; + wire plm_v4f_mgt_for_v1_4_cal_inst0_gt_do_r_4_i_m2_0_a2_0_a2_2_13_; + wire plm_v4f_mgt_for_v1_4_cal_inst0_gt_do_r_4_i_m2_0_a2_0_a2_12__810; + wire plm_v4f_mgt_for_v1_4_cal_inst0_gt_do_r_4_i_m2_0_a2_0_a2_2_11_; + wire plm_v4f_mgt_for_v1_4_cal_inst0_gt_do_r_4_i_m2_0_a2_0_a2_2_10_; + wire plm_v4f_mgt_for_v1_4_cal_inst0_gt_do_r_4_i_m2_0_a2_0_a2_2_9_; + wire plm_v4f_mgt_for_v1_4_cal_inst0_gt_do_r_4_i_m2_0_a2_0_a2_2_8_; + wire plm_v4f_mgt_for_v1_4_cal_inst0_gt_do_r_4_i_m2_0_a2_0_a2_2_7_; + wire plm_v4f_mgt_for_v1_4_cal_inst0_gt_do_r_4_i_m2_0_a2_0_a2_2_6_; + wire plm_v4f_mgt_for_v1_4_cal_inst0_gt_do_r_4_i_m2_0_a2_0_a2_2_5_; + wire plm_v4f_mgt_for_v1_4_cal_inst0_gt_do_r_4_i_m2_0_a2_0_a2_2_4_; + wire plm_v4f_mgt_for_v1_4_cal_inst0_gt_do_r_4_i_m2_0_a2_0_a2_2_3_; + wire plm_v4f_mgt_for_v1_4_cal_inst0_gt_do_r_4_i_m2_0_a2_0_a2_2_2_; + wire plm_v4f_mgt_for_v1_4_cal_inst0_gt_do_r_4_i_m2_0_a2_0_a2_1__811; + wire plm_v4f_mgt_for_v1_4_cal_inst0_gt_do_r_4_i_m2_0_a2_0_a2_2_0_; + wire plm_v4f_mgt_for_v1_4_cal_inst0_N_260_i; + wire plm_v4f_mgt_for_v1_4_cal_inst0_VCC_812; + wire plm_v4f_mgt_for_v1_4_cal_inst0_N_1788_i_813; + wire plm_v4f_mgt_for_v1_4_cal_inst0_N_1662_i_i_814; + wire plm_v4f_mgt_for_v1_4_cal_inst1_GND_815; + wire plm_v4f_mgt_for_v1_4_cal_inst1_N_1780_i_816; + wire plm_v4f_mgt_for_v1_4_cal_inst1_sd_req_817; + wire plm_v4f_mgt_for_v1_4_cal_inst1_cb_statec_i_i_818; + wire plm_v4f_mgt_for_v1_4_cal_inst1_cb_statec_i; + wire plm_v4f_mgt_for_v1_4_cal_inst1_N_1810_i_819; + wire plm_v4f_mgt_for_v1_4_cal_inst1_N_1779_i_820; + wire plm_v4f_mgt_for_v1_4_cal_inst1_N_1778_i_821; + wire plm_v4f_mgt_for_v1_4_cal_inst1_N_997_i; + wire plm_v4f_mgt_for_v1_4_cal_inst1_N_1663_i; + wire plm_v4f_mgt_for_v1_4_cal_inst1_N_2451_i_822; + wire plm_v4f_mgt_for_v1_4_cal_inst1_sd_next_state_0_sqmuxa_3; + wire plm_v4f_mgt_for_v1_4_cal_inst1_N_1680_i_823; + wire plm_v4f_mgt_for_v1_4_cal_inst1_sd_next_state_0_sqmuxa_2; + wire plm_v4f_mgt_for_v1_4_cal_inst1_N_2453_i_824; + wire plm_v4f_mgt_for_v1_4_cal_inst1_N_2452_i_825; + wire plm_v4f_mgt_for_v1_4_cal_inst1_N_1682_i_826; + wire plm_v4f_mgt_for_v1_4_cal_inst1_sd_next_state_0_sqmuxa_1; + wire plm_v4f_mgt_for_v1_4_cal_inst1_N_1683_i_827; + wire plm_v4f_mgt_for_v1_4_cal_inst1_sd_next_state_0_sqmuxa; + wire plm_v4f_mgt_for_v1_4_cal_inst1_N_2456_i_828; + wire plm_v4f_mgt_for_v1_4_cal_inst1_N_2454_i_829; + wire plm_v4f_mgt_for_v1_4_cal_inst1_sd_drp_done_830; + wire plm_v4f_mgt_for_v1_4_cal_inst1_drp_next_state_0_sqmuxa; + wire plm_v4f_mgt_for_v1_4_cal_inst1_N_2394_i_831; + wire plm_v4f_mgt_for_v1_4_cal_inst1_drp_state_3__832; + wire plm_v4f_mgt_for_v1_4_cal_inst1_drp_state_1__833; + wire plm_v4f_mgt_for_v1_4_cal_inst1_drp_next_state_0_sqmuxa_1; + wire plm_v4f_mgt_for_v1_4_cal_inst1_sd_write_834; + wire plm_v4f_mgt_for_v1_4_cal_inst1_N_995_i; + wire plm_v4f_mgt_for_v1_4_cal_inst1_sd_read_835; + wire plm_v4f_mgt_for_v1_4_cal_inst1_N_2442_i_836; + wire plm_v4f_mgt_for_v1_4_cal_inst1_drp_state_4__837; + wire plm_v4f_mgt_for_v1_4_cal_inst1_drp_state_0__838; + wire plm_v4f_mgt_for_v1_4_cal_inst1_sd_req_3_0_a2_0_a2_0; + wire plm_v4f_mgt_for_v1_4_cal_inst1_gt_drdy_r_839; + wire plm_v4f_mgt_for_v1_4_cal_inst1_N_2455_i_840; + wire plm_v4f_mgt_for_v1_4_cal_inst1_N_2457_i_841; + wire plm_v4f_mgt_for_v1_4_cal_inst1_N_1643_i; + wire plm_v4f_mgt_for_v1_4_cal_inst1_gt_do_r_4_i_m2_0_a2_0_a2_1_15_; + wire plm_v4f_mgt_for_v1_4_cal_inst1_gt_do_r_4_i_m2_0_a2_0_a2_1_14_; + wire plm_v4f_mgt_for_v1_4_cal_inst1_gt_do_r_4_i_m2_0_a2_0_a2_1_13_; + wire plm_v4f_mgt_for_v1_4_cal_inst1_gt_do_r_4_i_m2_0_a2_0_a2_0_12_; + wire plm_v4f_mgt_for_v1_4_cal_inst1_gt_do_r_4_i_m2_0_a2_0_a2_1_11_; + wire plm_v4f_mgt_for_v1_4_cal_inst1_gt_do_r_4_i_m2_0_a2_0_a2_1_10_; + wire plm_v4f_mgt_for_v1_4_cal_inst1_gt_do_r_4_i_m2_0_a2_0_a2_1_9_; + wire plm_v4f_mgt_for_v1_4_cal_inst1_gt_do_r_4_i_m2_0_a2_0_a2_1_8_; + wire plm_v4f_mgt_for_v1_4_cal_inst1_gt_do_r_4_i_m2_0_a2_0_a2_1_7_; + wire plm_v4f_mgt_for_v1_4_cal_inst1_gt_do_r_4_i_m2_0_a2_0_a2_1_6_; + wire plm_v4f_mgt_for_v1_4_cal_inst1_gt_do_r_4_i_m2_0_a2_0_a2_1_5_; + wire plm_v4f_mgt_for_v1_4_cal_inst1_gt_do_r_4_i_m2_0_a2_0_a2_1_4_; + wire plm_v4f_mgt_for_v1_4_cal_inst1_gt_do_r_4_i_m2_0_a2_0_a2_1_3_; + wire plm_v4f_mgt_for_v1_4_cal_inst1_gt_do_r_4_i_m2_0_a2_0_a2_1_2_; + wire plm_v4f_mgt_for_v1_4_cal_inst1_gt_do_r_4_i_m2_0_a2_0_a2_0_1_; + wire plm_v4f_mgt_for_v1_4_cal_inst1_gt_do_r_4_i_m2_0_a2_0_a2_1_0_; + wire plm_v4f_mgt_for_v1_4_cal_inst1_N_1540_i; + wire plm_v4f_mgt_for_v1_4_cal_inst1_VCC_842; + wire plm_v4f_mgt_for_v1_4_cal_inst1_N_1768_i_843; + wire plm_v4f_mgt_for_v1_4_cal_inst1_N_1663_i_i_844; + wire plm_v4f_mgt_for_v1_4_cal_inst2_N_1755_i_845; + wire plm_v4f_mgt_for_v1_4_cal_inst2_sd_req_846; + wire plm_v4f_mgt_for_v1_4_cal_inst2_cb_statec_i_i_847; + wire plm_v4f_mgt_for_v1_4_cal_inst2_cb_statec_i; + wire plm_v4f_mgt_for_v1_4_cal_inst2_N_1804_i_848; + wire plm_v4f_mgt_for_v1_4_cal_inst2_N_1754_i_849; + wire plm_v4f_mgt_for_v1_4_cal_inst2_N_1753_i_850; + wire plm_v4f_mgt_for_v1_4_cal_inst2_N_979_i; + wire plm_v4f_mgt_for_v1_4_cal_inst2_N_1657_i; + wire plm_v4f_mgt_for_v1_4_cal_inst2_N_2458_i_851; + wire plm_v4f_mgt_for_v1_4_cal_inst2_sd_next_state_0_sqmuxa_3; + wire plm_v4f_mgt_for_v1_4_cal_inst2_N_1675_i_852; + wire plm_v4f_mgt_for_v1_4_cal_inst2_sd_next_state_0_sqmuxa_2; + wire plm_v4f_mgt_for_v1_4_cal_inst2_N_2460_i_853; + wire plm_v4f_mgt_for_v1_4_cal_inst2_N_2459_i_854; + wire plm_v4f_mgt_for_v1_4_cal_inst2_N_1677_i_855; + wire plm_v4f_mgt_for_v1_4_cal_inst2_sd_next_state_0_sqmuxa_1; + wire plm_v4f_mgt_for_v1_4_cal_inst2_N_1678_i_856; + wire plm_v4f_mgt_for_v1_4_cal_inst2_sd_next_state_0_sqmuxa; + wire plm_v4f_mgt_for_v1_4_cal_inst2_N_2463_i_857; + wire plm_v4f_mgt_for_v1_4_cal_inst2_N_2461_i_858; + wire plm_v4f_mgt_for_v1_4_cal_inst2_sd_drp_done_859; + wire plm_v4f_mgt_for_v1_4_cal_inst2_drp_next_state_0_sqmuxa; + wire plm_v4f_mgt_for_v1_4_cal_inst2_N_2395_i_860; + wire plm_v4f_mgt_for_v1_4_cal_inst2_drp_state_3__861; + wire plm_v4f_mgt_for_v1_4_cal_inst2_drp_state_1__862; + wire plm_v4f_mgt_for_v1_4_cal_inst2_drp_next_state_0_sqmuxa_1; + wire plm_v4f_mgt_for_v1_4_cal_inst2_sd_write_863; + wire plm_v4f_mgt_for_v1_4_cal_inst2_N_977_i; + wire plm_v4f_mgt_for_v1_4_cal_inst2_sd_read_864; + wire plm_v4f_mgt_for_v1_4_cal_inst2_N_2445_i_865; + wire plm_v4f_mgt_for_v1_4_cal_inst2_drp_state_4__866; + wire plm_v4f_mgt_for_v1_4_cal_inst2_drp_state_0__867; + wire plm_v4f_mgt_for_v1_4_cal_inst2_sd_req_3_0_a2_0_a2_1; + wire plm_v4f_mgt_for_v1_4_cal_inst2_gt_drdy_r_868; + wire plm_v4f_mgt_for_v1_4_cal_inst2_N_2462_i_869; + wire plm_v4f_mgt_for_v1_4_cal_inst2_N_2464_i_870; + wire plm_v4f_mgt_for_v1_4_cal_inst2_N_1644_i; + wire plm_v4f_mgt_for_v1_4_cal_inst2_gt_do_r_4_i_m2_0_a2_0_a2_0_15_; + wire plm_v4f_mgt_for_v1_4_cal_inst2_gt_do_r_4_i_m2_0_a2_0_a2_0_14_; + wire plm_v4f_mgt_for_v1_4_cal_inst2_gt_do_r_4_i_m2_0_a2_0_a2_0_13_; + wire plm_v4f_mgt_for_v1_4_cal_inst2_gt_do_r_4_i_m2_0_a2_0_a2_1_12_; + wire plm_v4f_mgt_for_v1_4_cal_inst2_gt_do_r_4_i_m2_0_a2_0_a2_0_11_; + wire plm_v4f_mgt_for_v1_4_cal_inst2_gt_do_r_4_i_m2_0_a2_0_a2_0_10_; + wire plm_v4f_mgt_for_v1_4_cal_inst2_gt_do_r_4_i_m2_0_a2_0_a2_0_9_; + wire plm_v4f_mgt_for_v1_4_cal_inst2_gt_do_r_4_i_m2_0_a2_0_a2_0_8_; + wire plm_v4f_mgt_for_v1_4_cal_inst2_gt_do_r_4_i_m2_0_a2_0_a2_0_7_; + wire plm_v4f_mgt_for_v1_4_cal_inst2_gt_do_r_4_i_m2_0_a2_0_a2_0_6_; + wire plm_v4f_mgt_for_v1_4_cal_inst2_gt_do_r_4_i_m2_0_a2_0_a2_0_5_; + wire plm_v4f_mgt_for_v1_4_cal_inst2_gt_do_r_4_i_m2_0_a2_0_a2_0_4_; + wire plm_v4f_mgt_for_v1_4_cal_inst2_gt_do_r_4_i_m2_0_a2_0_a2_0_3_; + wire plm_v4f_mgt_for_v1_4_cal_inst2_gt_do_r_4_i_m2_0_a2_0_a2_0_2_; + wire plm_v4f_mgt_for_v1_4_cal_inst2_gt_do_r_4_i_m2_0_a2_0_a2_1_1_; + wire plm_v4f_mgt_for_v1_4_cal_inst2_gt_do_r_4_i_m2_0_a2_0_a2_0_0_; + wire plm_v4f_mgt_for_v1_4_cal_inst2_N_1532_i; + wire plm_v4f_mgt_for_v1_4_cal_inst2_VCC_871; + wire plm_v4f_mgt_for_v1_4_cal_inst2_N_1743_i_872; + wire plm_v4f_mgt_for_v1_4_cal_inst2_N_1664_i_i_873; + wire plm_v4f_mgt_for_v1_4_cal_inst3_N_1730_i_874; + wire plm_v4f_mgt_for_v1_4_cal_inst3_sd_req_875; + wire plm_v4f_mgt_for_v1_4_cal_inst3_cb_statec_i_i_876; + wire plm_v4f_mgt_for_v1_4_cal_inst3_cb_statec_i; + wire plm_v4f_mgt_for_v1_4_cal_inst3_N_1798_i_877; + wire plm_v4f_mgt_for_v1_4_cal_inst3_N_1729_i_878; + wire plm_v4f_mgt_for_v1_4_cal_inst3_N_1728_i_879; + wire plm_v4f_mgt_for_v1_4_cal_inst3_N_1381_i; + wire plm_v4f_mgt_for_v1_4_cal_inst3_N_1665_i; + wire plm_v4f_mgt_for_v1_4_cal_inst3_N_2465_i_880; + wire plm_v4f_mgt_for_v1_4_cal_inst3_sd_next_state_0_sqmuxa_3; + wire plm_v4f_mgt_for_v1_4_cal_inst3_N_1670_i_881; + wire plm_v4f_mgt_for_v1_4_cal_inst3_sd_next_state_0_sqmuxa_2; + wire plm_v4f_mgt_for_v1_4_cal_inst3_N_2467_i_882; + wire plm_v4f_mgt_for_v1_4_cal_inst3_N_2466_i_883; + wire plm_v4f_mgt_for_v1_4_cal_inst3_N_1672_i_884; + wire plm_v4f_mgt_for_v1_4_cal_inst3_sd_next_state_0_sqmuxa_1; + wire plm_v4f_mgt_for_v1_4_cal_inst3_N_1673_i_885; + wire plm_v4f_mgt_for_v1_4_cal_inst3_sd_next_state_0_sqmuxa; + wire plm_v4f_mgt_for_v1_4_cal_inst3_N_2471_i_886; + wire plm_v4f_mgt_for_v1_4_cal_inst3_N_2468_i_887; + wire plm_v4f_mgt_for_v1_4_cal_inst3_sd_drp_done_888; + wire plm_v4f_mgt_for_v1_4_cal_inst3_drp_next_state_0_sqmuxa; + wire plm_v4f_mgt_for_v1_4_cal_inst3_N_2396_i_889; + wire plm_v4f_mgt_for_v1_4_cal_inst3_drp_state_3__890; + wire plm_v4f_mgt_for_v1_4_cal_inst3_drp_state_1__891; + wire plm_v4f_mgt_for_v1_4_cal_inst3_drp_next_state_0_sqmuxa_1; + wire plm_v4f_mgt_for_v1_4_cal_inst3_sd_write_892; + wire plm_v4f_mgt_for_v1_4_cal_inst3_N_1379_i; + wire plm_v4f_mgt_for_v1_4_cal_inst3_sd_read_893; + wire plm_v4f_mgt_for_v1_4_cal_inst3_N_2470_i_894; + wire plm_v4f_mgt_for_v1_4_cal_inst3_drp_state_4__895; + wire plm_v4f_mgt_for_v1_4_cal_inst3_drp_state_0__896; + wire plm_v4f_mgt_for_v1_4_cal_inst3_sd_req_3_0_a2_0_a2_2; + wire plm_v4f_mgt_for_v1_4_cal_inst3_gt_drdy_r_897; + wire plm_v4f_mgt_for_v1_4_cal_inst3_N_2469_i_898; + wire plm_v4f_mgt_for_v1_4_cal_inst3_N_2472_i_899; + wire plm_v4f_mgt_for_v1_4_cal_inst3_N_1645_i; + wire plm_v4f_mgt_for_v1_4_cal_inst3_gt_do_r_4_i_m2_0_a2_0_a2_15__900; + wire plm_v4f_mgt_for_v1_4_cal_inst3_gt_do_r_4_i_m2_0_a2_0_a2_14__901; + wire plm_v4f_mgt_for_v1_4_cal_inst3_gt_do_r_4_i_m2_0_a2_0_a2_13__902; + wire plm_v4f_mgt_for_v1_4_cal_inst3_gt_do_r_4_i_m2_0_a2_0_a2_2_12_; + wire plm_v4f_mgt_for_v1_4_cal_inst3_gt_do_r_4_i_m2_0_a2_0_a2_11__903; + wire plm_v4f_mgt_for_v1_4_cal_inst3_gt_do_r_4_i_m2_0_a2_0_a2_10__904; + wire plm_v4f_mgt_for_v1_4_cal_inst3_gt_do_r_4_i_m2_0_a2_0_a2_9__905; + wire plm_v4f_mgt_for_v1_4_cal_inst3_gt_do_r_4_i_m2_0_a2_0_a2_8__906; + wire plm_v4f_mgt_for_v1_4_cal_inst3_gt_do_r_4_i_m2_0_a2_0_a2_7__907; + wire plm_v4f_mgt_for_v1_4_cal_inst3_gt_do_r_4_i_m2_0_a2_0_a2_6__908; + wire plm_v4f_mgt_for_v1_4_cal_inst3_gt_do_r_4_i_m2_0_a2_0_a2_5__909; + wire plm_v4f_mgt_for_v1_4_cal_inst3_gt_do_r_4_i_m2_0_a2_0_a2_4__910; + wire plm_v4f_mgt_for_v1_4_cal_inst3_gt_do_r_4_i_m2_0_a2_0_a2_3__911; + wire plm_v4f_mgt_for_v1_4_cal_inst3_gt_do_r_4_i_m2_0_a2_0_a2_2__912; + wire plm_v4f_mgt_for_v1_4_cal_inst3_gt_do_r_4_i_m2_0_a2_0_a2_2_1_; + wire plm_v4f_mgt_for_v1_4_cal_inst3_gt_do_r_4_i_m2_0_a2_0_a2_0__913; + wire plm_v4f_mgt_for_v1_4_cal_inst3_N_1524_i; + wire plm_v4f_mgt_for_v1_4_cal_inst3_VCC_914; + wire plm_v4f_mgt_for_v1_4_cal_inst3_N_1718_i_915; + wire plm_v4f_mgt_for_v1_4_cal_inst3_N_1665_i_i_916; + wire plm_des0_one_adv2_1_15__917; + wire plm_des0_one_adv2_1_13__918; + wire plm_des0_two_adv2_0_15__919; + wire plm_des0_two_adv2_1_14__920; + wire plm_des0_two_adv2_1_12__921; + wire plm_des0_two_adv2_1_1__922; + wire plm_des0_two_adv2_1_7__923; + wire plm_des0_one_adv2_1_6__924; + wire plm_des0_one_adv2_1_9__925; + wire plm_des0_one_adv2_1_5__926; + wire plm_des0_two_adv2_1_10__927; + wire plm_des0_two_adv2_1_8__928; + wire plm_des0_two_adv2_1_6__929; + wire plm_des0_two_adv2_0_4__930; + wire plm_des0_m1_0_a2_0_a3_0_a2_0_a2; + wire plm_des0_N_86080_i; + wire plm_des0_N_14320_i; + wire plm_des0_N_14319_i; + wire plm_des0_N_14273_i; + wire plm_des0_N_14272_i; + wire plm_des0_N_49067_i; + wire plm_des0_reg_lfsr_one_12_iv_i_0_0_a2_0_12_; + wire plm_des0_reg_lfsr_one_12_iv_i_0_0_a2_0_10_; + wire plm_des0_reg_lfsr_one_12_iv_i_0_0_a2_0_9_; + wire plm_des0_reg_lfsr_one_12_iv_i_0_0_a2_0_8_; + wire plm_des0_reg_lfsr_one_12_iv_i_0_0_a2_0_7_; + wire plm_des0_reg_lfsr_one_12_iv_i_0_0_a2_0_6_; + wire plm_des0_reg_lfsr_one_12_iv_i_0_0_a2_0_5_; + wire plm_des0_reg_lfsr_two_12_iv_i_0_0_a2_0_15_; + wire plm_des0_reg_lfsr_two_12_iv_i_0_0_a2_0_14_; + wire plm_des0_reg_lfsr_two_12_iv_i_0_0_a2_0_13_; + wire plm_des0_two_adv2_12__931; + wire plm_des0_reg_lfsr_two_12_iv_i_0_0_a2_0_11_; + wire plm_des0_two_adv2_10__932; + wire plm_des0_reg_lfsr_two_12_iv_0_0_0_a2_0_0_9_; + wire plm_des0_reg_lfsr_two_12_iv_0_0_0_a2_0_0_8_; + wire plm_des0_two_adv2_7__933; + wire plm_des0_two_adv2_6__934; + wire plm_des0_N_49056_i; + wire plm_des0_reg_lfsr_two_12_iv_0_0_0_a2_0_0_5_; + wire plm_des0_reg_lfsr_two_12_iv_i_0_0_a2_0_4_; + wire plm_des0_reg_lfsr_two_12_iv_0_0_0_a2_0_0_3_; + wire plm_des0_reg_lfsr_two_12_iv_i_0_0_a2_0_2_; + wire plm_des0_reg_lfsr_two_12_iv_i_0_0_a2_0_1_; + wire plm_des0_reg_lfsr_two_12_iv_i_0_0_a2_0_0_; + wire plm_des0_N_49079_i_0; + wire plm_des0_N_49059_i; + wire plm_des0_N_85316_i; + wire plm_des0_N_85317_i; + wire plm_des0_N_49180_i_0_i; + wire plm_des0_N_49178_i_0_i; + wire plm_des0_N_49176_i_0_i; + wire plm_des0_N_49174_i_0_i; + wire plm_des0_N_49172_i_0_i; + wire plm_des0_N_49170_i_0_i; + wire plm_des0_N_49168_i_0_i; + wire plm_des0_N_49166_i_0_i; + wire plm_des0_N_87707_i; + wire plm_des0_N_87706_i; + wire plm_des0_N_87705_i; + wire plm_des0_N_85339_i; + wire plm_des0_N_87704_i; + wire plm_des0_N_85338_i; + wire plm_des0_reg_lfsr_one_10__935; + wire plm_des0_N_85337_i; + wire plm_des0_reg_lfsr_one_9__936; + wire plm_des0_N_85336_i; + wire plm_des0_reg_lfsr_one_8__937; + wire plm_des0_N_85335_i; + wire plm_des0_reg_lfsr_one_7__938; + wire plm_des0_N_85334_i; + wire plm_des0_reg_lfsr_one_6__939; + wire plm_des0_N_85333_i; + wire plm_des0_reg_lfsr_one_5__940; + wire plm_des0_N_87703_i; + wire plm_des0_reg_lfsr_one_4__941; + wire plm_des0_N_85332_i; + wire plm_des0_N_87702_i; + wire plm_des0_reg_lfsr_one_2__942; + wire plm_des0_N_87701_i; + wire plm_des0_N_87664_i; + wire plm_des0_N_85347_i; + wire plm_des0_N_85346_i; + wire plm_des0_N_85345_i; + wire plm_des0_N_9511_i; + wire plm_des0_reg_lfsr_two_12__943; + wire plm_des0_N_85344_i; + wire plm_des0_N_9513_i; + wire plm_des0_reg_lfsr_two_10__944; + wire plm_des0_N_9514_i; + wire plm_des0_reg_lfsr_two_9__945; + wire plm_des0_N_9515_i; + wire plm_des0_reg_lfsr_two_8__946; + wire plm_des0_N_9516_i; + wire plm_des0_reg_lfsr_two_7__947; + wire plm_des0_N_9517_i; + wire plm_des0_reg_lfsr_two_6__948; + wire plm_des0_N_9518_i; + wire plm_des0_reg_lfsr_two_5__949; + wire plm_des0_N_85343_i; + wire plm_des0_N_9520_i; + wire plm_des0_reg_lfsr_two_3__950; + wire plm_des0_N_85342_i; + wire plm_des0_N_85341_i; + wire plm_des0_reg_lfsr_one32_i; + wire plm_des0_N_85340_i; + wire plm_des1_one_adv2_1_15__951; + wire plm_des1_one_adv2_1_13__952; + wire plm_des1_two_adv2_1_14__953; + wire plm_des1_two_adv2_1_12__954; + wire plm_des1_two_adv2_1_1__955; + wire plm_des1_two_adv2_1_7__956; + wire plm_des1_one_adv2_1_6__957; + wire plm_des1_one_adv2_1_5__958; + wire plm_des1_one_adv2_1_9__959; + wire plm_des1_two_adv2_1_10__960; + wire plm_des1_two_adv2_1_8__961; + wire plm_des1_two_adv2_1_6__962; + wire plm_des1_m1_0_a2_0_a3_0_a2_0_a2_0; + wire plm_des1_N_86081_i; + wire plm_des1_N_14233_i; + wire plm_des1_N_14232_i; + wire plm_des1_N_14199_i; + wire plm_des1_N_14198_i; + wire plm_des1_N_49066_i; + wire plm_des1_reg_lfsr_one_12_iv_i_0_0_a2_0_0_12_; + wire plm_des1_reg_lfsr_one_12_iv_i_0_0_a2_0_0_10_; + wire plm_des1_reg_lfsr_one_12_iv_i_0_0_a2_0_0_9_; + wire plm_des1_reg_lfsr_one_12_iv_i_0_0_a2_0_0_8_; + wire plm_des1_reg_lfsr_one_12_iv_i_0_0_a2_0_0_7_; + wire plm_des1_reg_lfsr_one_12_iv_i_0_0_a2_0_0_6_; + wire plm_des1_reg_lfsr_one_12_iv_i_0_0_a2_0_0_5_; + wire plm_des1_two_adv2_15__963; + wire plm_des1_reg_lfsr_two_12_iv_i_0_0_a2_0_0_14_; + wire plm_des1_reg_lfsr_two_12_iv_i_0_0_a2_0_0_13_; + wire plm_des1_two_adv2_12__964; + wire plm_des1_reg_lfsr_two_12_iv_i_0_0_a2_0_0_11_; + wire plm_des1_two_adv2_10__965; + wire plm_des1_reg_lfsr_two_12_iv_0_0_0_a2_0_9_; + wire plm_des1_reg_lfsr_two_12_iv_0_0_0_a2_0_8_; + wire plm_des1_two_adv2_7__966; + wire plm_des1_two_adv2_6__967; + wire plm_des1_N_49057_i; + wire plm_des1_reg_lfsr_two_12_iv_0_0_0_a2_0_5_; + wire plm_des1_reg_lfsr_two_12_iv_i_0_0_a2_0_0_4_; + wire plm_des1_reg_lfsr_two_12_iv_0_0_0_a2_0_3_; + wire plm_des1_reg_lfsr_two_12_iv_i_0_0_a2_0_0_2_; + wire plm_des1_reg_lfsr_two_12_iv_i_0_0_a2_0_0_1_; + wire plm_des1_reg_lfsr_two_12_iv_i_0_0_a2_0_0_0_; + wire plm_des1_N_49078_i_0; + wire plm_des1_N_49060_i; + wire plm_des1_N_85318_i; + wire plm_des1_N_85319_i; + wire plm_des1_N_49196_i_0_i; + wire plm_des1_N_49194_i_0_i; + wire plm_des1_N_49192_i_0_i; + wire plm_des1_N_49190_i_0_i; + wire plm_des1_N_49188_i_0_i; + wire plm_des1_N_49186_i_0_i; + wire plm_des1_N_49184_i_0_i; + wire plm_des1_N_49182_i_0_i; + wire plm_des1_N_87696_i; + wire plm_des1_N_87695_i; + wire plm_des1_N_87694_i; + wire plm_des1_N_85355_i; + wire plm_des1_N_87693_i; + wire plm_des1_N_85354_i; + wire plm_des1_reg_lfsr_one_10__968; + wire plm_des1_N_85353_i; + wire plm_des1_reg_lfsr_one_9__969; + wire plm_des1_N_85352_i; + wire plm_des1_reg_lfsr_one_8__970; + wire plm_des1_N_85351_i; + wire plm_des1_reg_lfsr_one_7__971; + wire plm_des1_N_85350_i; + wire plm_des1_reg_lfsr_one_6__972; + wire plm_des1_N_85349_i; + wire plm_des1_reg_lfsr_one_5__973; + wire plm_des1_N_87692_i; + wire plm_des1_reg_lfsr_one_4__974; + wire plm_des1_N_85348_i; + wire plm_des1_N_87691_i; + wire plm_des1_reg_lfsr_one_2__975; + wire plm_des1_N_87690_i; + wire plm_des1_N_87689_i; + wire plm_des1_N_85363_i; + wire plm_des1_N_85362_i; + wire plm_des1_N_85361_i; + wire plm_des1_N_9543_i; + wire plm_des1_reg_lfsr_two_12__976; + wire plm_des1_N_85360_i; + wire plm_des1_N_9545_i; + wire plm_des1_reg_lfsr_two_10__977; + wire plm_des1_N_9546_i; + wire plm_des1_reg_lfsr_two_9__978; + wire plm_des1_N_9547_i; + wire plm_des1_reg_lfsr_two_8__979; + wire plm_des1_N_9548_i; + wire plm_des1_reg_lfsr_two_7__980; + wire plm_des1_N_9549_i; + wire plm_des1_reg_lfsr_two_6__981; + wire plm_des1_N_9550_i; + wire plm_des1_reg_lfsr_two_5__982; + wire plm_des1_N_85359_i; + wire plm_des1_N_9552_i; + wire plm_des1_reg_lfsr_two_3__983; + wire plm_des1_N_85358_i; + wire plm_des1_N_85357_i; + wire plm_des1_reg_lfsr_one32_i; + wire plm_des1_N_85356_i; + wire plm_des2_one_adv2_1_15__984; + wire plm_des2_one_adv2_1_13__985; + wire plm_des2_two_adv2_1_14__986; + wire plm_des2_two_adv2_1_12__987; + wire plm_des2_two_adv2_1_1__988; + wire plm_des2_two_adv2_1_7__989; + wire plm_des2_one_adv2_1_6__990; + wire plm_des2_one_adv2_1_5__991; + wire plm_des2_one_adv2_1_9__992; + wire plm_des2_two_adv2_1_10__993; + wire plm_des2_two_adv2_1_8__994; + wire plm_des2_two_adv2_1_6__995; + wire plm_des2_m1_0_a2_0_a3_0_a2_0_a2_1; + wire plm_des2_N_86082_i; + wire plm_des2_N_14165_i; + wire plm_des2_N_14164_i; + wire plm_des2_N_14131_i; + wire plm_des2_N_14130_i; + wire plm_des2_N_49065_i; + wire plm_des2_reg_lfsr_one_12_iv_i_0_a2_0_12_; + wire plm_des2_reg_lfsr_one_12_iv_i_0_a2_0_10_; + wire plm_des2_reg_lfsr_one_12_iv_i_0_a2_0_9_; + wire plm_des2_reg_lfsr_one_12_iv_i_0_a2_0_8_; + wire plm_des2_reg_lfsr_one_12_iv_i_0_a2_0_7_; + wire plm_des2_reg_lfsr_one_12_iv_i_0_a2_0_6_; + wire plm_des2_reg_lfsr_one_12_iv_i_0_a2_0_5_; + wire plm_des2_two_adv2_15__996; + wire plm_des2_reg_lfsr_two_12_iv_i_0_a2_0_14_; + wire plm_des2_reg_lfsr_two_12_iv_i_0_a2_0_13_; + wire plm_des2_two_adv2_12__997; + wire plm_des2_reg_lfsr_two_12_iv_i_0_a2_0_11_; + wire plm_des2_two_adv2_10__998; + wire plm_des2_reg_lfsr_two_12_iv_0_0_a2_0_0_9_; + wire plm_des2_reg_lfsr_two_12_iv_0_0_a2_0_0_8_; + wire plm_des2_two_adv2_7__999; + wire plm_des2_two_adv2_6__1000; + wire plm_des2_N_49058_i; + wire plm_des2_reg_lfsr_two_12_iv_0_0_a2_0_0_5_; + wire plm_des2_reg_lfsr_two_12_iv_i_0_a2_0_4_; + wire plm_des2_reg_lfsr_two_12_iv_i_0_a2_0_2_; + wire plm_des2_reg_lfsr_two_12_iv_i_0_a2_0_1_; + wire plm_des2_reg_lfsr_two_12_iv_i_0_a2_0_0_; + wire plm_des2_N_49077_i_0; + wire plm_des2_N_49061_i; + wire plm_des2_N_49208_i_0_i; + wire plm_des2_N_49206_i_0_i; + wire plm_des2_N_49204_i_0_i; + wire plm_des2_N_49202_i_0_i; + wire plm_des2_N_49200_i_0_i; + wire plm_des2_N_49198_i_0_i; + wire plm_des2_N_85320_i; + wire plm_des2_N_85321_i; + wire plm_des2_N_49212_i_0_i; + wire plm_des2_N_49210_i_0_i; + wire plm_des2_N_87684_i; + wire plm_des2_N_87683_i; + wire plm_des2_N_87682_i; + wire plm_des2_N_85371_i; + wire plm_des2_reg_lfsr_one_12__1001; + wire plm_des2_N_87681_i; + wire plm_des2_N_85370_i; + wire plm_des2_reg_lfsr_one_10__1002; + wire plm_des2_N_85369_i; + wire plm_des2_reg_lfsr_one_9__1003; + wire plm_des2_N_85368_i; + wire plm_des2_reg_lfsr_one_8__1004; + wire plm_des2_N_85367_i; + wire plm_des2_reg_lfsr_one_7__1005; + wire plm_des2_N_85366_i; + wire plm_des2_reg_lfsr_one_6__1006; + wire plm_des2_N_85365_i; + wire plm_des2_reg_lfsr_one_5__1007; + wire plm_des2_N_87680_i; + wire plm_des2_reg_lfsr_one_4__1008; + wire plm_des2_N_85364_i; + wire plm_des2_N_87679_i; + wire plm_des2_reg_lfsr_one_2__1009; + wire plm_des2_N_87678_i; + wire plm_des2_N_87665_i; + wire plm_des2_N_85379_i; + wire plm_des2_N_85378_i; + wire plm_des2_N_85377_i; + wire plm_des2_N_9575_i; + wire plm_des2_reg_lfsr_two_12__1010; + wire plm_des2_N_85376_i; + wire plm_des2_N_9577_i; + wire plm_des2_reg_lfsr_two_10__1011; + wire plm_des2_N_9578_i; + wire plm_des2_reg_lfsr_two_9__1012; + wire plm_des2_N_9579_i; + wire plm_des2_reg_lfsr_two_8__1013; + wire plm_des2_N_9580_i; + wire plm_des2_reg_lfsr_two_7__1014; + wire plm_des2_N_9581_i; + wire plm_des2_reg_lfsr_two_6__1015; + wire plm_des2_N_9582_i; + wire plm_des2_reg_lfsr_two_5__1016; + wire plm_des2_N_85375_i; + wire plm_des2_N_9584_i; + wire plm_des2_reg_lfsr_two_3__1017; + wire plm_des2_N_85374_i; + wire plm_des2_N_85373_i; + wire plm_des2_reg_lfsr_one32_i; + wire plm_des2_N_85372_i; + wire plm_des3_one_adv2_1_15__1018; + wire plm_des3_one_adv2_1_13__1019; + wire plm_des3_two_adv2_1_12__1020; + wire plm_des3_two_adv2_1_1__1021; + wire plm_des3_one_adv2_1_6__1022; + wire plm_des3_one_adv2_1_9__1023; + wire plm_des3_one_adv2_1_5__1024; + wire plm_des3_two_adv2_1_10__1025; + wire plm_des3_two_adv2_1_8__1026; + wire plm_des3_two_adv2_1_6__1027; + wire plm_des3_m1_0_a2_0_a3_0_a2_0_a2_2; + wire plm_des3_N_86083_i; + wire plm_des3_N_14095_i; + wire plm_des3_N_14094_i; + wire plm_des3_N_14058_i; + wire plm_des3_N_14057_i; + wire plm_des3_N_49064_i; + wire plm_des3_reg_lfsr_one_12_iv_i_0_a2_0_0_12_; + wire plm_des3_reg_lfsr_one_12_iv_i_0_0_a2_0_1_10_; + wire plm_des3_reg_lfsr_one_12_iv_i_0_0_a2_0_1_9_; + wire plm_des3_reg_lfsr_one_12_iv_i_0_0_a2_0_1_8_; + wire plm_des3_reg_lfsr_one_12_iv_i_0_a2_0_0_7_; + wire plm_des3_reg_lfsr_one_12_iv_i_0_0_a2_0_1_6_; + wire plm_des3_reg_lfsr_one_12_iv_i_0_0_a2_0_1_5_; + wire plm_des3_two_adv2_15__1028; + wire plm_des3_two_adv2_1_14__1029; + wire plm_des3_reg_lfsr_two_12_iv_i_0_a2_0_0_13_; + wire plm_des3_two_adv2_12__1030; + wire plm_des3_reg_lfsr_two_12_iv_i_0_a2_0_0_11_; + wire plm_des3_two_adv2_10__1031; + wire plm_des3_reg_lfsr_two_12_iv_0_0_a2_0_9_; + wire plm_des3_reg_lfsr_two_12_iv_0_0_a2_0_8_; + wire plm_des3_two_adv2_7__1032; + wire plm_des3_two_adv2_6__1033; + wire plm_des3_N_49055_i; + wire plm_des3_reg_lfsr_two_12_iv_0_0_a2_0_5_; + wire plm_des3_reg_lfsr_two_12_iv_i_0_a2_0_0_4_; + wire plm_des3_reg_lfsr_two_12_iv_i_0_a2_0_0_2_; + wire plm_des3_reg_lfsr_two_12_iv_i_0_a2_0_0_1_; + wire plm_des3_reg_lfsr_two_12_iv_i_0_a2_0_0_0_; + wire plm_des3_N_49080_i_0; + wire plm_des3_N_49062_i; + wire plm_des3_N_85322_i; + wire plm_des3_N_85323_i; + wire plm_des3_N_49228_i_0_i; + wire plm_des3_N_49226_i_0_i; + wire plm_des3_N_49224_i_0_i; + wire plm_des3_N_49222_i_0_i; + wire plm_des3_N_49220_i_0_i; + wire plm_des3_N_49218_i_0_i; + wire plm_des3_N_49216_i_0_i; + wire plm_des3_N_49214_i_0_i; + wire plm_des3_N_87674_i; + wire plm_des3_N_87673_i; + wire plm_des3_N_87672_i; + wire plm_des3_N_85387_i; + wire plm_des3_N_87671_i; + wire plm_des3_N_85386_i; + wire plm_des3_reg_lfsr_one_10__1034; + wire plm_des3_N_85385_i; + wire plm_des3_reg_lfsr_one_9__1035; + wire plm_des3_N_85384_i; + wire plm_des3_reg_lfsr_one_8__1036; + wire plm_des3_N_85383_i; + wire plm_des3_reg_lfsr_one_7__1037; + wire plm_des3_N_85382_i; + wire plm_des3_reg_lfsr_one_6__1038; + wire plm_des3_N_85381_i; + wire plm_des3_reg_lfsr_one_5__1039; + wire plm_des3_N_87670_i; + wire plm_des3_reg_lfsr_one_4__1040; + wire plm_des3_N_85380_i; + wire plm_des3_N_87669_i; + wire plm_des3_reg_lfsr_one_2__1041; + wire plm_des3_N_87667_i; + wire plm_des3_N_87666_i; + wire plm_des3_N_85395_i; + wire plm_des3_N_85394_i; + wire plm_des3_N_85393_i; + wire plm_des3_N_9607_i; + wire plm_des3_N_85392_i; + wire plm_des3_N_48875_i; + wire plm_des3_reg_lfsr_two_10__1042; + wire plm_des3_N_9610_i; + wire plm_des3_reg_lfsr_two_9__1043; + wire plm_des3_N_9611_i; + wire plm_des3_reg_lfsr_two_8__1044; + wire plm_des3_N_9612_i; + wire plm_des3_reg_lfsr_two_7__1045; + wire plm_des3_N_9613_i; + wire plm_des3_reg_lfsr_two_6__1046; + wire plm_des3_N_9614_i; + wire plm_des3_reg_lfsr_two_5__1047; + wire plm_des3_N_85391_i; + wire plm_des3_N_9616_i; + wire plm_des3_N_85390_i; + wire plm_des3_N_85389_i; + wire plm_des3_reg_lfsr_two_1__1048; + wire plm_des3_reg_lfsr_one32_i; + wire plm_des3_N_85388_i; + wire plm_scr0_one_adv2_1_15__1049; + wire plm_scr0_one_adv2_1_13__1050; + wire plm_scr0_one_adv2_1_11__1051; + wire plm_scr0_two_adv2_1_14__1052; + wire plm_scr0_two_adv2_1_12__1053; + wire plm_scr0_two_adv2_1_1__1054; + wire plm_scr0_two_adv2_1_7__1055; + wire plm_scr0_one_adv2_1_6__1056; + wire plm_scr0_one_adv2_1_9__1057; + wire plm_scr0_two_adv2_1_10__1058; + wire plm_scr0_two_adv2_1_4__1059; + wire plm_scr0_reg_tx_data_12_2_bm_2_7_; + wire plm_scr0_reg_tx_data_12_2_am_2_7_; + wire plm_scr0_reg_tx_data_12_sn_m2; + wire plm_scr0_reg_tx_data_12_2_bm_2_0_; + wire plm_scr0_reg_tx_data_12_2_am_2_0_; + wire plm_scr0_reg_lfsr_one_12_iv_i_a2_12_; + wire plm_scr0_reg_lfsr_one_12_iv_i_a2_0_10_; + wire plm_scr0_reg_lfsr_one_12_iv_i_a2_0_9_; + wire plm_scr0_reg_lfsr_one_12_iv_i_a2_0_8_; + wire plm_scr0_reg_lfsr_one_12_iv_i_a2_7_; + wire plm_scr0_reg_lfsr_one_12_iv_i_a2_0_6_; + wire plm_scr0_reg_lfsr_one_12_iv_i_a2_5_; + wire plm_scr0_reg_lfsr_one_12_iv_i_a2_3_; + wire plm_scr0_two_adv2_15__1060; + wire plm_scr0_reg_lfsr_two_12_iv_i_a2_0_14_; + wire plm_scr0_reg_lfsr_two_12_iv_i_a2_0_13_; + wire plm_scr0_two_adv2_12__1061; + wire plm_scr0_reg_lfsr_two_12_iv_i_a2_0_11_; + wire plm_scr0_two_adv2_10__1062; + wire plm_scr0_reg_lfsr_two_12_iv_0_a2_0_9_; + wire plm_scr0_two_adv2_8__1063; + wire plm_scr0_two_adv2_7__1064; + wire plm_scr0_two_adv2_6__1065; + wire plm_scr0_N_21117_i; + wire plm_scr0_N_21114_i; + wire plm_scr0_reg_lfsr_two_12_iv_0_a2_0_5_; + wire plm_scr0_reg_lfsr_two_12_iv_i_a2_0_4_; + wire plm_scr0_reg_lfsr_two_12_iv_0_a2_0_3_; + wire plm_scr0_reg_lfsr_two_12_iv_i_a2_0_2_; + wire plm_scr0_reg_lfsr_two_12_iv_i_a2_0_1_; + wire plm_scr0_reg_lfsr_two_12_iv_i_a2_0_0_; + wire plm_scr0_N_21115_i; + wire plm_scr0_reg_lfsr_one29_0_a4; + wire plm_scr0_N_14358_i; + wire plm_scr0_N_14357_i; + wire plm_scr0_N_87816_i; + wire plm_scr0_N_87815_i; + wire plm_scr0_N_87814_i; + wire plm_scr0_N_85423_i; + wire plm_scr0_reg_lfsr_one_12__1066; + wire plm_scr0_N_87813_i; + wire plm_scr0_N_85422_i; + wire plm_scr0_reg_lfsr_one_10__1067; + wire plm_scr0_N_85421_i; + wire plm_scr0_reg_lfsr_one_9__1068; + wire plm_scr0_N_85420_i; + wire plm_scr0_reg_lfsr_one_8__1069; + wire plm_scr0_N_85419_i; + wire plm_scr0_reg_lfsr_one_7__1070; + wire plm_scr0_N_85418_i; + wire plm_scr0_reg_lfsr_one_6__1071; + wire plm_scr0_N_85417_i; + wire plm_scr0_reg_lfsr_one_5__1072; + wire plm_scr0_reg_lfsr_one_4__1073; + wire plm_scr0_N_85416_i; + wire plm_scr0_N_87812_i; + wire plm_scr0_reg_lfsr_one_2__1074; + wire plm_scr0_N_87811_i; + wire plm_scr0_N_87810_i; + wire plm_scr0_N_85435_i; + wire plm_scr0_N_85434_i; + wire plm_scr0_N_85433_i; + wire plm_scr0_N_9639_i; + wire plm_scr0_reg_lfsr_two_12__1075; + wire plm_scr0_N_85432_i; + wire plm_scr0_N_9641_i; + wire plm_scr0_reg_lfsr_two_10__1076; + wire plm_scr0_N_9642_i; + wire plm_scr0_reg_lfsr_two_9__1077; + wire plm_scr0_N_9643_i; + wire plm_scr0_reg_lfsr_two_8__1078; + wire plm_scr0_N_9644_i; + wire plm_scr0_reg_lfsr_two_7__1079; + wire plm_scr0_N_9645_i; + wire plm_scr0_reg_lfsr_two_6__1080; + wire plm_scr0_N_9646_i; + wire plm_scr0_reg_lfsr_two_5__1081; + wire plm_scr0_N_85428_i; + wire plm_scr0_N_9648_i; + wire plm_scr0_N_85426_i; + wire plm_scr0_N_85425_i; + wire plm_scr0_reg_lfsr_one32_i; + wire plm_scr0_N_85424_i; + wire plm_scr1_one_adv2_1_13__1082; + wire plm_scr1_one_adv2_1_11__1083; + wire plm_scr1_one_adv2_1_15__1084; + wire plm_scr1_two_adv2_1_1__1085; + wire plm_scr1_two_adv2_1_12__1086; + wire plm_scr1_two_adv2_1_14__1087; + wire plm_scr1_two_adv2_0_15__1088; + wire plm_scr1_two_adv2_1_7__1089; + wire plm_scr1_one_adv2_1_6__1090; + wire plm_scr1_one_adv2_1_9__1091; + wire plm_scr1_one_adv2_1_5__1092; + wire plm_scr1_two_adv2_0_4__1093; + wire plm_scr1_two_adv2_1_10__1094; + wire plm_scr1_reg_tx_data_12_2_bm_1_7_; + wire plm_scr1_reg_tx_data_12_2_am_1_7_; + wire plm_scr1_reg_tx_data_12_sn_m2_0; + wire plm_scr1_reg_tx_data_12_2_bm_1_0_; + wire plm_scr1_reg_tx_data_12_2_am_1_0_; + wire plm_scr1_one_adv2_m_12__1095; + wire plm_scr1_one_adv2_m_10__1096; + wire plm_scr1_one_adv2_m_9__1097; + wire plm_scr1_one_adv2_m_8__1098; + wire plm_scr1_one_adv2_m_7__1099; + wire plm_scr1_one_adv2_m_6__1100; + wire plm_scr1_one_adv2_m_3__1101; + wire plm_scr1_two_adv2_m_15__1102; + wire plm_scr1_two_adv2_m_14__1103; + wire plm_scr1_two_adv2_m_13__1104; + wire plm_scr1_two_adv2_12__1105; + wire plm_scr1_two_adv2_m_11__1106; + wire plm_scr1_two_adv2_10__1107; + wire plm_scr1_two_adv2_m_9__1108; + wire plm_scr1_two_adv2_8__1109; + wire plm_scr1_two_adv2_7__1110; + wire plm_scr1_two_adv2_6__1111; + wire plm_scr1_reg_lfsr_one29; + wire plm_scr1_two_adv2_m_5__1112; + wire plm_scr1_two_adv2_m_4__1113; + wire plm_scr1_un1_reg_skp_2_1114; + wire plm_scr1_two_adv2_m_3__1115; + wire plm_scr1_two_adv2_m_2__1116; + wire plm_scr1_two_adv2_m_1__1117; + wire plm_scr1_un1_reg_lfsr_one37_i; + wire plm_scr1_un1_reg_com_1_1118; + wire plm_scr1_two_adv2_m_0__1119; + wire plm_scr1_reg_tx_data_6_15_; + wire plm_scr1_N_13597_i_0_i; + wire plm_scr1_N_13595_i_0_i; + wire plm_scr1_N_13593_i_0_i; + wire plm_scr1_N_13519_i_0_i; + wire plm_scr1_reg_tx_data_6_10_; + wire plm_scr1_reg_tx_data_6_9_; + wire plm_scr1_N_13517_i_0_i; + wire plm_scr1_reg_lfsr_one_12_15_; + wire plm_scr1_reg_lfsr_one_12_14_; + wire plm_scr1_reg_lfsr_one_12_13_; + wire plm_scr1_N_9687_i; + wire plm_scr1_reg_lfsr_one_12_11_; + wire plm_scr1_N_9689_i; + wire plm_scr1_reg_lfsr_one_10__1120; + wire plm_scr1_N_9690_i; + wire plm_scr1_reg_lfsr_one_9__1121; + wire plm_scr1_N_9691_i; + wire plm_scr1_reg_lfsr_one_8__1122; + wire plm_scr1_N_9692_i; + wire plm_scr1_reg_lfsr_one_7__1123; + wire plm_scr1_N_9693_i; + wire plm_scr1_reg_lfsr_one_6__1124; + wire plm_scr1_N_9694_i; + wire plm_scr1_reg_lfsr_one_5__1125; + wire plm_scr1_reg_lfsr_one_12_4_; + wire plm_scr1_reg_lfsr_one_4__1126; + wire plm_scr1_N_9696_i; + wire plm_scr1_reg_lfsr_one_12_2_; + wire plm_scr1_reg_lfsr_one_2__1127; + wire plm_scr1_reg_lfsr_one_12_1_; + wire plm_scr1_reg_lfsr_one_12_0_; + wire plm_scr1_N_9668_i; + wire plm_scr1_N_9669_i; + wire plm_scr1_N_9670_i; + wire plm_scr1_N_9671_i; + wire plm_scr1_reg_lfsr_two_12__1128; + wire plm_scr1_N_9672_i; + wire plm_scr1_N_9673_i; + wire plm_scr1_reg_lfsr_two_10__1129; + wire plm_scr1_N_9674_i; + wire plm_scr1_reg_lfsr_two_9__1130; + wire plm_scr1_N_9675_i; + wire plm_scr1_reg_lfsr_two_8__1131; + wire plm_scr1_N_9676_i; + wire plm_scr1_reg_lfsr_two_7__1132; + wire plm_scr1_N_9677_i; + wire plm_scr1_reg_lfsr_two_6__1133; + wire plm_scr1_N_9678_i; + wire plm_scr1_reg_lfsr_two_5__1134; + wire plm_scr1_N_9679_i; + wire plm_scr1_N_9680_i; + wire plm_scr1_N_9681_i; + wire plm_scr1_N_9682_i; + wire plm_scr1_reg_lfsr_one32_i; + wire plm_scr1_N_9683_i; + wire plm_scr2_one_adv2_1_11__1135; + wire plm_scr2_one_adv2_1_13__1136; + wire plm_scr2_two_adv2_1_12__1137; + wire plm_scr2_one_adv2_1_6__1138; + wire plm_scr2_one_adv2_1_9__1139; + wire plm_scr2_two_adv2_1_10__1140; + wire plm_scr2_one_adv2_8__1141; + wire plm_scr2_one_adv2_1_5__1142; + wire plm_scr2_reg_tx_data_12_2_bm_0_7_; + wire plm_scr2_reg_tx_data_12_2_am_0_7_; + wire plm_scr2_reg_tx_data_12_sn_m2_1; + wire plm_scr2_reg_tx_data_12_2_bm_0_0_; + wire plm_scr2_reg_tx_data_12_2_am_0_0_; + wire plm_scr2_one_adv2_15__1143; + wire plm_scr2_one_adv2_14__1144; + wire plm_scr2_reg_lfsr_one_12_iv_i_a2_0_12_; + wire plm_scr2_reg_lfsr_one_12_iv_i_a2_0_0_10_; + wire plm_scr2_reg_lfsr_one_12_iv_i_a2_0_0_9_; + wire plm_scr2_reg_lfsr_one_12_iv_i_a2_0_0_8_; + wire plm_scr2_reg_lfsr_one_12_iv_i_a2_0_7_; + wire plm_scr2_reg_lfsr_one_12_iv_i_a2_0_0_6_; + wire plm_scr2_reg_lfsr_one_12_iv_i_a2_0_5_; + wire plm_scr2_reg_lfsr_one_12_iv_i_a2_0_3_; + wire plm_scr2_two_adv2_15__1145; + wire plm_scr2_two_adv2_1_14__1146; + wire plm_scr2_one_adv2_13__1147; + wire plm_scr2_reg_lfsr_two_12_iv_i_a2_0_0_13_; + wire plm_scr2_two_adv2_12__1148; + wire plm_scr2_one_adv2_12__1149; + wire plm_scr2_one_adv2_11__1150; + wire plm_scr2_reg_lfsr_two_12_iv_i_a2_0_0_11_; + wire plm_scr2_two_adv2_10__1151; + wire plm_scr2_one_adv2_10__1152; + wire plm_scr2_one_adv2_9__1153; + wire plm_scr2_reg_lfsr_two_12_iv_0_a2_0_0_9_; + wire plm_scr2_two_adv2_8__1154; + wire plm_scr2_two_adv2_7__1155; + wire plm_scr2_one_adv2_7__1156; + wire plm_scr2_two_adv2_6__1157; + wire plm_scr2_one_adv2_6__1158; + wire plm_scr2_N_25901_i; + wire plm_scr2_N_20985_i; + wire plm_scr2_two_adv2_5__1159; + wire plm_scr2_one_adv2_4__1160; + wire plm_scr2_reg_lfsr_two_12_iv_i_a2_0_0_4_; + wire plm_scr2_one_adv2_3__1161; + wire plm_scr2_reg_lfsr_two_12_iv_0_a2_0_0_3_; + wire plm_scr2_one_adv2_2__1162; + wire plm_scr2_reg_lfsr_two_12_iv_i_a2_0_0_2_; + wire plm_scr2_one_adv2_1__1163; + wire plm_scr2_reg_lfsr_two_12_iv_i_a2_0_0_1_; + wire plm_scr2_one_adv2_0__1164; + wire plm_scr2_reg_lfsr_two_12_iv_i_a2_0_0_0_; + wire plm_scr2_N_20984_i; + wire plm_scr2_reg_lfsr_one29_0_a4_0_a2; + wire plm_scr2_N_13503_i_0_i; + wire plm_scr2_reg_tx_data_12_7_; + wire plm_scr2_N_13525_i; + wire plm_scr2_N_13524_i; + wire plm_scr2_N_13523_i; + wire plm_scr2_N_13522_i; + wire plm_scr2_N_13521_i; + wire plm_scr2_N_13520_i; + wire plm_scr2_reg_tx_data_12_0_; + wire plm_scr2_N_13515_i_0_i; + wire plm_scr2_N_13513_i_0_i; + wire plm_scr2_N_13511_i_0_i; + wire plm_scr2_N_13509_i_0_i; + wire plm_scr2_N_13507_i_0_i; + wire plm_scr2_N_13505_i_0_i; + wire plm_scr2_N_87798_i; + wire plm_scr2_N_87828_i; + wire plm_scr2_N_13589_i; + wire plm_scr2_N_85443_i; + wire plm_scr2_reg_lfsr_one_12__1165; + wire plm_scr2_N_87827_i; + wire plm_scr2_N_85442_i; + wire plm_scr2_reg_lfsr_one_10__1166; + wire plm_scr2_N_85441_i; + wire plm_scr2_reg_lfsr_one_9__1167; + wire plm_scr2_N_85440_i; + wire plm_scr2_reg_lfsr_one_8__1168; + wire plm_scr2_N_85439_i; + wire plm_scr2_reg_lfsr_one_7__1169; + wire plm_scr2_N_85438_i; + wire plm_scr2_reg_lfsr_one_6__1170; + wire plm_scr2_N_85437_i; + wire plm_scr2_reg_lfsr_one_5__1171; + wire plm_scr2_N_87826_i; + wire plm_scr2_reg_lfsr_one_4__1172; + wire plm_scr2_N_85436_i; + wire plm_scr2_N_87825_i; + wire plm_scr2_reg_lfsr_one_2__1173; + wire plm_scr2_N_87824_i; + wire plm_scr2_N_85455_i; + wire plm_scr2_N_85454_i; + wire plm_scr2_N_85453_i; + wire plm_scr2_N_9703_i; + wire plm_scr2_N_85452_i; + wire plm_scr2_N_9705_i; + wire plm_scr2_N_9706_i; + wire plm_scr2_N_9707_i; + wire plm_scr2_N_9708_i; + wire plm_scr2_N_9709_i; + wire plm_scr2_N_9710_i; + wire plm_scr2_N_85448_i; + wire plm_scr2_N_9712_i; + wire plm_scr2_N_85446_i; + wire plm_scr2_N_85445_i; + wire plm_scr2_reg_lfsr_one32_i; + wire plm_scr2_N_85444_i; + wire plm_scr3_one_adv2_1_11__1174; + wire plm_scr3_one_adv2_1_15__1175; + wire plm_scr3_one_adv2_1_13__1176; + wire plm_scr3_two_adv2_1_14__1177; + wire plm_scr3_two_adv2_1_12__1178; + wire plm_scr3_two_adv2_1_7__1179; + wire plm_scr3_two_adv2_1_1__1180; + wire plm_scr3_one_adv2_1_6__1181; + wire plm_scr3_one_adv2_1_9__1182; + wire plm_scr3_two_adv2_1_8__1183; + wire plm_scr3_two_adv2_1_4__1184; + wire plm_scr3_two_adv2_1_6__1185; + wire plm_scr3_reg_tx_data_12_sn_m2_2; + wire plm_scr3_reg_lfsr_one_12_iv_i_a2_1_12_; + wire plm_scr3_reg_lfsr_one_12_iv_i_a2_1_7_; + wire plm_scr3_reg_lfsr_one_12_iv_i_a2_1_5_; + wire plm_scr3_reg_lfsr_one_12_iv_i_a2_1_3_; + wire plm_scr3_two_adv2_15__1186; + wire plm_scr3_reg_lfsr_two_12_iv_i_a2_0_1_13_; + wire plm_scr3_two_adv2_12__1187; + wire plm_scr3_reg_lfsr_two_12_iv_i_a2_0_1_11_; + wire plm_scr3_two_adv2_10__1188; + wire plm_scr3_reg_lfsr_two_12_iv_0_a2_0_1_9_; + wire plm_scr3_reg_lfsr_two_12_iv_0_a2_0_0_8_; + wire plm_scr3_two_adv2_7__1189; + wire plm_scr3_two_adv2_6__1190; + wire plm_scr3_N_20851_i; + wire plm_scr3_N_20848_i; + wire plm_scr3_reg_lfsr_two_12_iv_0_a2_0_0_5_; + wire plm_scr3_reg_lfsr_two_12_iv_i_a2_0_1_4_; + wire plm_scr3_reg_lfsr_two_12_iv_0_a2_0_1_3_; + wire plm_scr3_reg_lfsr_two_12_iv_i_a2_0_1_2_; + wire plm_scr3_reg_lfsr_two_12_iv_i_a2_0_1_1_; + wire plm_scr3_reg_lfsr_two_12_iv_i_a2_0_1_0_; + wire plm_scr3_N_20849_i; + wire plm_scr3_reg_lfsr_one29_0_a4_0; + wire plm_scr3_N_14391_i; + wire plm_scr3_N_14375_i; + wire plm_scr3_N_87839_i; + wire plm_scr3_N_87838_i; + wire plm_scr3_N_87837_i; + wire plm_scr3_N_85463_i; + wire plm_scr3_reg_lfsr_one_12__1191; + wire plm_scr3_N_87836_i; + wire plm_scr3_N_85462_i; + wire plm_scr3_reg_lfsr_one_10__1192; + wire plm_scr3_N_85461_i; + wire plm_scr3_reg_lfsr_one_9__1193; + wire plm_scr3_N_85460_i; + wire plm_scr3_reg_lfsr_one_8__1194; + wire plm_scr3_N_85459_i; + wire plm_scr3_reg_lfsr_one_7__1195; + wire plm_scr3_N_85458_i; + wire plm_scr3_reg_lfsr_one_6__1196; + wire plm_scr3_N_85457_i; + wire plm_scr3_reg_lfsr_one_5__1197; + wire plm_scr3_reg_lfsr_one_4__1198; + wire plm_scr3_N_85456_i; + wire plm_scr3_N_87835_i; + wire plm_scr3_reg_lfsr_one_2__1199; + wire plm_scr3_N_87834_i; + wire plm_scr3_N_87833_i; + wire plm_scr3_N_85475_i; + wire plm_scr3_N_85474_i; + wire plm_scr3_reg_lfsr_two_14__1200; + wire plm_scr3_N_85473_i; + wire plm_scr3_N_9735_i; + wire plm_scr3_reg_lfsr_two_12__1201; + wire plm_scr3_N_85472_i; + wire plm_scr3_N_9737_i; + wire plm_scr3_reg_lfsr_two_10__1202; + wire plm_scr3_N_9738_i; + wire plm_scr3_reg_lfsr_two_9__1203; + wire plm_scr3_N_9739_i; + wire plm_scr3_reg_lfsr_two_8__1204; + wire plm_scr3_N_9740_i; + wire plm_scr3_reg_lfsr_two_7__1205; + wire plm_scr3_N_9741_i; + wire plm_scr3_reg_lfsr_two_6__1206; + wire plm_scr3_N_9742_i; + wire plm_scr3_reg_lfsr_two_5__1207; + wire plm_scr3_N_85468_i; + wire plm_scr3_reg_lfsr_two_4__1208; + wire plm_scr3_N_9744_i; + wire plm_scr3_reg_lfsr_two_3__1209; + wire plm_scr3_N_85466_i; + wire plm_scr3_N_85465_i; + wire plm_scr3_reg_lfsr_one32_i; + wire plm_scr3_N_85464_i; + wire plm_tsi0_un2_com_data_jog0_1210; + wire plm_tsi0_idle_pair_0_a2_0_a2_0_a3_0_a2_12_1211; + wire plm_tsi0_ts1_inv1_jog1_1_5_1212; + wire plm_tsi0_ts1_inv1_jog1_1_4_1213; + wire plm_tsi0_ts2_inv0_jog1_1_5_1214; + wire plm_tsi0_ts2_inv0_jog1_1_4_1215; + wire plm_tsi0_ts2_inv1_jog1_1_5_1216; + wire plm_tsi0_ts2_inv1_jog1_1_4_1217; + wire plm_tsi0_ts1_inv0_jog0_1_5_1218; + wire plm_tsi0_ts1_inv0_jog0_1_4_1219; + wire plm_tsi0_com_data_jog1_2; + wire plm_tsi0_com_data_jog1_1_1220; + wire plm_tsi0_idle_pair_0_a2_0_a2_0_a3_0_a2_13_1221; + wire plm_tsi0_idle_pair_0_a2_0_a2_0_a3_0_a2_11_1222; + wire plm_tsi0_idle_pair_0_a2_0_a2_0_a3_0_a2_10_1223; + wire plm_tsi0_idle_pair_0_a2_0_a2_0_a3_0_a2_9_1224; + wire plm_tsi0_ts1_inv1_jog1_1_1225; + wire plm_tsi0_ts2_inv1_jog1_1_1226; + wire plm_tsi0_ts1_inv0_jog0_1_1227; + wire plm_tsi0_ts2_inv0_jog1_1_1228; + wire plm_tsi0_com_data_jog0_1229; + wire plm_tsi0_reg_capture_ts2_3_0; + wire plm_tsi0_reg_capture_ts1_3_0; + wire plm_tsi0_ts2_inv1_jog1_1230; + wire plm_tsi0_ts2_inv0_jog1_1231; + wire plm_tsi0_ts1_inv1_jog1_1232; + wire plm_tsi0_ts1_inv0_jog1_1233; + wire plm_tsi0_reg_capture_inv_3_5907; + wire plm_tsi0_reg_capture_inv_3_5906; + wire plm_tsi0_un7_reg_ts2_timer_axbxc3_1234; + wire plm_tsi0_un2_recent_ts2_1235; + wire plm_tsi0_reg_ts2_timer_0_sqmuxa_1236; + wire plm_tsi0_un7_reg_ts1_timer_axbxc3_1237; + wire plm_tsi0_un2_recent_ts1_1238; + wire plm_tsi0_reg_ts1_timer_0_sqmuxa_1239; + wire plm_tsi0_reg_dec8_13__1240; + wire plm_tsi0_reg_rx_idl_c_3; + wire plm_tsi0_idle_pair; + wire plm_tsi0_reg_ts2_c_3; + wire plm_tsi0_reg_ts1_c_3; + wire plm_tsi0_N_11393_i; + wire plm_tsi0_N_11394_i; + wire plm_tsi0_reg_capture_ts2_1241; + wire plm_tsi0_N_11395_i; + wire plm_tsi0_reg_capture_ts1_1242; + wire plm_tsi0_N_11397_i; + wire plm_tsi0_reg_capture_jog_1243; + wire plm_tsi0_N_11396_i; + wire plm_tsi0_reg_dec8_6__1244; + wire plm_tsi0_reg_dec8_5__1245; + wire plm_tsi0_reg_dec2_1__1246; + wire plm_tsi0_reg_dec3_1__1247; + wire plm_tsi0_reg_dec7_5__1248; + wire plm_tsi0_reg_dec4_2__1249; + wire plm_tsi0_reg_dec5_2__1250; + wire plm_tsi0_reg_dec4_1__1251; + wire plm_tsi0_reg_dec5_1__1252; + wire plm_tsi0_reg_dec2_11__1253; + wire plm_tsi0_reg_dec3_11__1254; + wire plm_tsi0_reg_dec2_10__1255; + wire plm_tsi0_reg_dec3_10__1256; + wire plm_tsi0_reg_dec2_9__1257; + wire plm_tsi0_reg_dec3_9__1258; + wire plm_tsi0_reg_dec2_8__1259; + wire plm_tsi0_reg_dec3_8__1260; + wire plm_tsi0_reg_dec2_4__1261; + wire plm_tsi0_reg_dec3_4__1262; + wire plm_tsi0_reg_dec2_3__1263; + wire plm_tsi0_reg_dec3_3__1264; + wire plm_tsi0_reg_dec2_2__1265; + wire plm_tsi0_reg_dec3_2__1266; + wire plm_tsi0_reg_dec7_12__1267; + wire plm_tsi0_reg_dec4_11__1268; + wire plm_tsi0_reg_dec5_11__1269; + wire plm_tsi0_reg_dec4_10__1270; + wire plm_tsi0_reg_dec5_10__1271; + wire plm_tsi0_reg_dec4_9__1272; + wire plm_tsi0_reg_dec5_9__1273; + wire plm_tsi0_reg_dec4_8__1274; + wire plm_tsi0_reg_dec5_8__1275; + wire plm_tsi0_reg_dec4_4__1276; + wire plm_tsi0_reg_dec5_4__1277; + wire plm_tsi0_reg_dec4_3__1278; + wire plm_tsi0_reg_dec5_3__1279; + wire plm_tsi0_reg_capture_inv_1280; + wire plm_tsi0_reg_lane_pad_3; + wire plm_tsi0_reg_link_pad_3; + wire plm_tsi0_reg_linkctrl_3_3_; + wire plm_tsi0_reg_capture_now_1281; + wire plm_tsi0_reg_linkctrl_3_0_; + wire plm_tsi0_reg_dec8_0_N_6; + wire plm_tsi0_reg_dec1_2_N_6; + wire plm_tsi0_reg_dec1_1_N_6; + wire plm_tsi0_reg_dec1_0_N_6; + wire plm_tsi0_reg_dec1_N_6; + wire plm_tsi0_reg_dec7_0_N_6; + wire plm_tsi0_GND_1282; + wire plm_tsi0_VCC_1283; + wire plm_tsi1_un2_com_data_jog0_0; + wire plm_tsi1_idle_pair_0_a2_0_a2_0_a3_0_a2_12_1284; + wire plm_tsi1_ts2_inv0_jog0_1_5_1285; + wire plm_tsi1_ts2_inv0_jog0_1_4_1286; + wire plm_tsi1_ts2_inv1_jog0_1_5_1287; + wire plm_tsi1_ts2_inv1_jog0_1_4_1288; + wire plm_tsi1_ts1_inv0_jog1_1_5_1289; + wire plm_tsi1_ts1_inv0_jog1_1_4_1290; + wire plm_tsi1_ts1_inv1_jog1_1_5_1291; + wire plm_tsi1_ts1_inv1_jog1_1_4_1292; + wire plm_tsi1_ts1_inv0_jog1_1_1293; + wire plm_tsi1_com_data_jog1_1_1294; + wire plm_tsi1_com_data_jog0_2; + wire plm_tsi1_idle_pair_0_a2_0_a2_0_a3_0_a2_13_1295; + wire plm_tsi1_idle_pair_0_a2_0_a2_0_a3_0_a2_11_1296; + wire plm_tsi1_idle_pair_0_a2_0_a2_0_a3_0_a2_10_1297; + wire plm_tsi1_idle_pair_0_a2_0_a2_0_a3_0_a2_9_1298; + wire plm_tsi1_ts1_inv1_jog1_1_1299; + wire plm_tsi1_ts2_inv1_jog0_1_1300; + wire plm_tsi1_com_data_jog0_1301; + wire plm_tsi1_ts2_inv0_jog0_1_1302; + wire plm_tsi1_ts2_inv0_jog0_0_1303; + wire plm_tsi1_ts2_inv1_jog1_1304; + wire plm_tsi1_ts2_inv0_jog1_1305; + wire plm_tsi1_ts1_inv1_jog1_1306; + wire plm_tsi1_reg_capture_inv_3_5894; + wire plm_tsi1_ts1_inv0_jog1_1307; + wire plm_tsi1_ts1_inv0_jog0_1308; + wire plm_tsi1_reg_capture_inv_3_5893; + wire plm_tsi1_reg_capture_ts2_3; + wire plm_tsi1_un7_reg_ts2_timer_axbxc3_0; + wire plm_tsi1_un2_recent_ts2_0; + wire plm_tsi1_reg_ts2_timer_0_sqmuxa_1309; + wire plm_tsi1_un7_reg_ts1_timer_axbxc3_0; + wire plm_tsi1_un2_recent_ts1_0; + wire plm_tsi1_reg_ts1_timer_0_sqmuxa_1310; + wire plm_tsi1_reg_dec8_13__1311; + wire plm_tsi1_idle_pair; + wire plm_tsi1_reg_ts2_c_3; + wire plm_tsi1_reg_ts1_c_3; + wire plm_tsi1_N_11384_i; + wire plm_tsi1_N_11385_i; + wire plm_tsi1_N_11387_i; + wire plm_tsi1_reg_capture_jog_1312; + wire plm_tsi1_N_11386_i; + wire plm_tsi1_reg_rx_idl_c_3; + wire plm_tsi1_reg_capture_ts2_1313; + wire plm_tsi1_reg_capture_ts1_1314; + wire plm_tsi1_N_11383_i; + wire plm_tsi1_reg_dec8_6__1315; + wire plm_tsi1_reg_dec8_5__1316; + wire plm_tsi1_reg_dec7_5__1317; + wire plm_tsi1_reg_dec4_1__1318; + wire plm_tsi1_reg_dec5_1__1319; + wire plm_tsi1_reg_dec2_11__1320; + wire plm_tsi1_reg_dec3_11__1321; + wire plm_tsi1_reg_dec2_10__1322; + wire plm_tsi1_reg_dec3_10__1323; + wire plm_tsi1_reg_dec2_9__1324; + wire plm_tsi1_reg_dec3_9__1325; + wire plm_tsi1_reg_dec2_8__1326; + wire plm_tsi1_reg_dec3_8__1327; + wire plm_tsi1_reg_dec2_4__1328; + wire plm_tsi1_reg_dec3_4__1329; + wire plm_tsi1_reg_dec2_3__1330; + wire plm_tsi1_reg_dec3_3__1331; + wire plm_tsi1_reg_dec2_2__1332; + wire plm_tsi1_reg_dec3_2__1333; + wire plm_tsi1_reg_dec2_1__1334; + wire plm_tsi1_reg_dec3_1__1335; + wire plm_tsi1_reg_dec7_12__1336; + wire plm_tsi1_reg_dec4_11__1337; + wire plm_tsi1_reg_dec5_11__1338; + wire plm_tsi1_reg_dec4_10__1339; + wire plm_tsi1_reg_dec5_10__1340; + wire plm_tsi1_reg_dec4_9__1341; + wire plm_tsi1_reg_dec5_9__1342; + wire plm_tsi1_reg_dec4_8__1343; + wire plm_tsi1_reg_dec5_8__1344; + wire plm_tsi1_reg_dec4_4__1345; + wire plm_tsi1_reg_dec5_4__1346; + wire plm_tsi1_reg_dec4_3__1347; + wire plm_tsi1_reg_dec5_3__1348; + wire plm_tsi1_reg_dec4_2__1349; + wire plm_tsi1_reg_dec5_2__1350; + wire plm_tsi1_reg_capture_inv_1351; + wire plm_tsi1_reg_lane_pad_3; + wire plm_tsi1_reg_link_pad_3; + wire plm_tsi1_reg_linkctrl_3_3_; + wire plm_tsi1_reg_capture_now_1352; + wire plm_tsi1_reg_linkctrl_3_0_; + wire plm_tsi1_reg_dec8_0_N_6; + wire plm_tsi1_reg_dec6_N_6; + wire plm_tsi1_reg_dec1_2_N_6; + wire plm_tsi1_reg_dec1_1_N_6; + wire plm_tsi1_reg_dec1_0_N_6; + wire plm_tsi1_reg_dec1_N_6; + wire plm_tsi1_reg_dec8_N_6; + wire plm_tsi1_reg_dec7_0_N_6; + wire plm_tsi1_GND_1353; + wire plm_tsi1_VCC_1354; + wire plm_tsi1_reg_dec5_N_6; + wire plm_tsi2_un2_com_data_jog0_1; + wire plm_tsi2_idle_pair_0_a2_0_a3_0_a2_12_1355; + wire plm_tsi2_ts2_inv1_jog1_1_5_1356; + wire plm_tsi2_ts2_inv1_jog1_1_4_1357; + wire plm_tsi2_ts1_inv0_jog0_1_5_1358; + wire plm_tsi2_ts1_inv0_jog0_1_4_1359; + wire plm_tsi2_ts1_inv1_jog0_1_5_1360; + wire plm_tsi2_ts1_inv1_jog0_1_4_1361; + wire plm_tsi2_ts2_inv0_jog0_1_5_1362; + wire plm_tsi2_ts2_inv0_jog0_1_4_1363; + wire plm_tsi2_com_data_jog1_1_1364; + wire plm_tsi2_com_data_jog0_2; + wire plm_tsi2_ts1_inv0_jog0_1_1365; + wire plm_tsi2_idle_pair_0_a2_0_a3_0_a2_13_1366; + wire plm_tsi2_idle_pair_0_a2_0_a3_0_a2_11_1367; + wire plm_tsi2_idle_pair_0_a2_0_a3_0_a2_10_1368; + wire plm_tsi2_idle_pair_0_a2_0_a3_0_a2_9_1369; + wire plm_tsi2_ts1_inv1_jog0_1_1370; + wire plm_tsi2_ts2_inv1_jog1_1_1371; + wire plm_tsi2_com_data_jog0_1372; + wire plm_tsi2_ts2_inv0_jog0_1_1373; + wire plm_tsi2_ts2_inv0_jog0_0_1374; + wire plm_tsi2_reg_capture_ts2_3_0; + wire plm_tsi2_ts1_inv0_jog0_1375; + wire plm_tsi2_ts2_inv1_jog1_1376; + wire plm_tsi2_ts2_inv0_jog1_1377; + wire plm_tsi2_ts1_inv1_jog1_1378; + wire plm_tsi2_ts1_inv0_jog1_1379; + wire plm_tsi2_reg_capture_inv_3_5881; + wire plm_tsi2_reg_capture_inv_3_5880; + wire plm_tsi2_un7_reg_ts1_timer_axbxc3_1; + wire plm_tsi2_un2_recent_ts1_1; + wire plm_tsi2_reg_ts1_timer_0_sqmuxa_1380; + wire plm_tsi2_un7_reg_ts2_timer_axbxc3_1; + wire plm_tsi2_un2_recent_ts2_1; + wire plm_tsi2_reg_ts2_timer_0_sqmuxa_1381; + wire plm_tsi2_reg_dec8_13__1382; + wire plm_tsi2_idle_pair; + wire plm_tsi2_reg_ts2_c_3; + wire plm_tsi2_reg_ts1_c_3; + wire plm_tsi2_N_11373_i; + wire plm_tsi2_N_11374_i; + wire plm_tsi2_reg_capture_ts2_1383; + wire plm_tsi2_N_11375_i; + wire plm_tsi2_reg_capture_ts1_1384; + wire plm_tsi2_N_11377_i; + wire plm_tsi2_reg_capture_jog_1385; + wire plm_tsi2_N_11376_i; + wire plm_tsi2_reg_rx_idl_c_3; + wire plm_tsi2_reg_dec8_6__1386; + wire plm_tsi2_reg_dec8_5__1387; + wire plm_tsi2_reg_dec7_5__1388; + wire plm_tsi2_reg_dec2_11__1389; + wire plm_tsi2_reg_dec3_11__1390; + wire plm_tsi2_reg_dec2_10__1391; + wire plm_tsi2_reg_dec3_10__1392; + wire plm_tsi2_reg_dec2_9__1393; + wire plm_tsi2_reg_dec3_9__1394; + wire plm_tsi2_reg_dec2_8__1395; + wire plm_tsi2_reg_dec3_8__1396; + wire plm_tsi2_reg_dec2_4__1397; + wire plm_tsi2_reg_dec3_4__1398; + wire plm_tsi2_reg_dec2_3__1399; + wire plm_tsi2_reg_dec3_3__1400; + wire plm_tsi2_reg_dec2_2__1401; + wire plm_tsi2_reg_dec3_2__1402; + wire plm_tsi2_reg_dec2_1__1403; + wire plm_tsi2_reg_dec3_1__1404; + wire plm_tsi2_reg_dec7_12__1405; + wire plm_tsi2_reg_dec4_11__1406; + wire plm_tsi2_reg_dec5_11__1407; + wire plm_tsi2_reg_dec4_10__1408; + wire plm_tsi2_reg_dec5_10__1409; + wire plm_tsi2_reg_dec4_9__1410; + wire plm_tsi2_reg_dec5_9__1411; + wire plm_tsi2_reg_dec4_8__1412; + wire plm_tsi2_reg_dec5_8__1413; + wire plm_tsi2_reg_dec4_4__1414; + wire plm_tsi2_reg_dec5_4__1415; + wire plm_tsi2_reg_dec4_3__1416; + wire plm_tsi2_reg_dec5_3__1417; + wire plm_tsi2_reg_dec4_2__1418; + wire plm_tsi2_reg_dec5_2__1419; + wire plm_tsi2_reg_dec4_1__1420; + wire plm_tsi2_reg_dec5_1__1421; + wire plm_tsi2_reg_capture_inv_1422; + wire plm_tsi2_reg_lane_pad_3; + wire plm_tsi2_reg_link_pad_3; + wire plm_tsi2_reg_linkctrl_3_3_; + wire plm_tsi2_reg_capture_now_1423; + wire plm_tsi2_reg_linkctrl_3_0_; + wire plm_tsi2_reg_dec8_0_N_6; + wire plm_tsi2_reg_dec6_N_6; + wire plm_tsi2_reg_dec1_2_N_6; + wire plm_tsi2_reg_dec1_1_N_6; + wire plm_tsi2_reg_dec1_0_N_6; + wire plm_tsi2_reg_dec1_N_6; + wire plm_tsi2_reg_dec8_N_6; + wire plm_tsi2_reg_dec7_0_N_6; + wire plm_tsi2_reg_dec7_N_6; + wire plm_tsi2_GND_1424; + wire plm_tsi2_VCC_1425; + wire plm_tsi2_reg_dec5_N_6; + wire plm_tsi3_un2_com_data_jog0_2; + wire plm_tsi3_idle_pair_0_a2_0_a2_0_a3_0_a2_12_1426; + wire plm_tsi3_ts2_inv0_jog0_1_5_1427; + wire plm_tsi3_ts2_inv0_jog0_1_4_1428; + wire plm_tsi3_ts2_inv1_jog0_1_5_1429; + wire plm_tsi3_ts2_inv1_jog0_1_4_1430; + wire plm_tsi3_ts1_inv0_jog1_1_5_1431; + wire plm_tsi3_ts1_inv0_jog1_1_4_1432; + wire plm_tsi3_ts1_inv1_jog1_1_5_1433; + wire plm_tsi3_ts1_inv1_jog1_1_4_1434; + wire plm_tsi3_com_data_jog1_2; + wire plm_tsi3_com_data_jog1_1_1435; + wire plm_tsi3_idle_pair_0_a2_0_a2_0_a3_0_a2_13_1436; + wire plm_tsi3_idle_pair_0_a2_0_a2_0_a3_0_a2_11_1437; + wire plm_tsi3_idle_pair_0_a2_0_a2_0_a3_0_a2_10_1438; + wire plm_tsi3_idle_pair_0_a2_0_a2_0_a3_0_a2_9_1439; + wire plm_tsi3_ts1_inv1_jog1_1_1440; + wire plm_tsi3_ts2_inv1_jog0_1_1441; + wire plm_tsi3_ts1_inv0_jog1_1_1442; + wire plm_tsi3_ts2_inv0_jog0_1_1443; + wire plm_tsi3_com_data_jog0_1444; + wire plm_tsi3_reg_capture_ts2_3_0; + wire plm_tsi3_reg_capture_ts1_3_0; + wire plm_tsi3_ts2_inv1_jog1_1445; + wire plm_tsi3_ts2_inv0_jog1_1446; + wire plm_tsi3_ts1_inv1_jog1_1447; + wire plm_tsi3_ts1_inv0_jog1_1448; + wire plm_tsi3_reg_capture_inv_3_5868; + wire plm_tsi3_reg_capture_inv_3_5867; + wire plm_tsi3_un7_reg_ts1_timer_axbxc3_2; + wire plm_tsi3_un2_recent_ts1_2; + wire plm_tsi3_reg_ts1_timer_0_sqmuxa_1449; + wire plm_tsi3_un7_reg_ts2_timer_axbxc3_2; + wire plm_tsi3_un2_recent_ts2_2; + wire plm_tsi3_reg_ts2_timer_0_sqmuxa_1450; + wire plm_tsi3_reg_dec8_13__1451; + wire plm_tsi3_reg_ts2_c_3; + wire plm_tsi3_reg_ts1_c_3; + wire plm_tsi3_reg_rx_idl_c_3; + wire plm_tsi3_idle_pair; + wire plm_tsi3_N_11363_i; + wire plm_tsi3_N_11364_i; + wire plm_tsi3_reg_capture_ts2_1452; + wire plm_tsi3_N_11365_i; + wire plm_tsi3_reg_capture_ts1_1453; + wire plm_tsi3_N_11367_i; + wire plm_tsi3_reg_capture_jog_1454; + wire plm_tsi3_N_11366_i; + wire plm_tsi3_reg_dec8_6__1455; + wire plm_tsi3_reg_dec8_5__1456; + wire plm_tsi3_reg_dec7_5__1457; + wire plm_tsi3_reg_dec2_11__1458; + wire plm_tsi3_reg_dec3_11__1459; + wire plm_tsi3_reg_dec2_10__1460; + wire plm_tsi3_reg_dec3_10__1461; + wire plm_tsi3_reg_dec2_9__1462; + wire plm_tsi3_reg_dec3_9__1463; + wire plm_tsi3_reg_dec2_8__1464; + wire plm_tsi3_reg_dec3_8__1465; + wire plm_tsi3_reg_dec2_4__1466; + wire plm_tsi3_reg_dec3_4__1467; + wire plm_tsi3_reg_dec2_3__1468; + wire plm_tsi3_reg_dec3_3__1469; + wire plm_tsi3_reg_dec2_2__1470; + wire plm_tsi3_reg_dec3_2__1471; + wire plm_tsi3_reg_dec2_1__1472; + wire plm_tsi3_reg_dec3_1__1473; + wire plm_tsi3_reg_dec7_12__1474; + wire plm_tsi3_reg_dec4_11__1475; + wire plm_tsi3_reg_dec5_11__1476; + wire plm_tsi3_reg_dec4_10__1477; + wire plm_tsi3_reg_dec5_10__1478; + wire plm_tsi3_reg_dec4_9__1479; + wire plm_tsi3_reg_dec5_9__1480; + wire plm_tsi3_reg_dec4_8__1481; + wire plm_tsi3_reg_dec5_8__1482; + wire plm_tsi3_reg_dec4_4__1483; + wire plm_tsi3_reg_dec5_4__1484; + wire plm_tsi3_reg_dec4_3__1485; + wire plm_tsi3_reg_dec5_3__1486; + wire plm_tsi3_reg_dec4_2__1487; + wire plm_tsi3_reg_dec5_2__1488; + wire plm_tsi3_reg_dec4_1__1489; + wire plm_tsi3_reg_dec5_1__1490; + wire plm_tsi3_reg_capture_inv_1491; + wire plm_tsi3_reg_lane_pad_3; + wire plm_tsi3_reg_link_pad_3; + wire plm_tsi3_reg_linkctrl_3_3_; + wire plm_tsi3_reg_capture_now_1492; + wire plm_tsi3_reg_linkctrl_3_0_; + wire plm_tsi3_reg_dec8_0_N_6; + wire plm_tsi3_reg_dec6_N_6; + wire plm_tsi3_reg_dec1_2_N_6; + wire plm_tsi3_reg_dec1_1_N_6; + wire plm_tsi3_reg_dec1_0_N_6; + wire plm_tsi3_reg_dec1_N_6; + wire plm_tsi3_reg_dec8_N_6; + wire plm_tsi3_reg_dec7_0_N_6; + wire plm_tsi3_reg_dec5_N_6; + wire plm_tsi3_GND_1493; + wire plm_tsi3_VCC_1494; + wire plm_tsi3_reg_dec7_N_6; + wire plm_dfm_det_d0_i; + wire plm_dfm_N_58721; + wire plm_dfm_N_58722; + wire plm_dfm_by4_prec_rcverr; + wire plm_dfm_by1_prec_rcverr; + wire plm_dfm_N_38113; + wire plm_dfm_N_38141; + wire plm_dfm_N_9858_i_0_m2_0_1495; + wire plm_dfm_prec_rcverr_i_m3_0_1496; + wire plm_dfm_prel_out_i_m3_0_31__1497; + wire plm_dfm_prel_out_i_m3_0_30__1498; + wire plm_dfm_prel_out_i_m3_0_29__1499; + wire plm_dfm_prel_out_i_m3_0_28__1500; + wire plm_dfm_prel_out_i_m3_0_20__1501; + wire plm_dfm_prel_out_i_m3_0_19__1502; + wire plm_dfm_prel_out_i_m3_0_18__1503; + wire plm_dfm_prel_out_i_m3_0_17__1504; + wire plm_dfm_prel_out_i_m3_0_16__1505; + wire plm_dfm_prel_out_i_m3_0_15__1506; + wire plm_dfm_prel_out_i_m3_0_14__1507; + wire plm_dfm_prel_out_i_m3_0_13__1508; + wire plm_dfm_prel_out_i_m3_0_12__1509; + wire plm_dfm_prel_out_i_m3_0_11__1510; + wire plm_dfm_prel_out_i_m3_0_10__1511; + wire plm_dfm_prel_out_i_m3_0_9__1512; + wire plm_dfm_prel_out_i_m3_0_8__1513; + wire plm_dfm_prel_out_i_m3_0_7__1514; + wire plm_dfm_prel_out_i_m3_0_6__1515; + wire plm_dfm_prel_out_i_m3_0_5__1516; + wire plm_dfm_prel_out_i_m3_0_4__1517; + wire plm_dfm_prel_out_i_m3_0_3__1518; + wire plm_dfm_prel_out_i_m3_0_2__1519; + wire plm_dfm_prel_out_i_m3_0_1__1520; + wire plm_dfm_prel_out_i_m3_0_0__1521; + wire plm_dfm_reg_phy_rframe_h_3; + wire plm_dfm_reg_phy_rframe_l_3; + wire plm_dfm_reg_phy_rbad_dfrm_h_3; + wire plm_dfm_reg_phy_rbad_dfrm_l_3; + wire plm_dfm_un4_reg_phy_ferr_h_n_i; + wire plm_dfm_un4_reg_phy_ferr_l_n_i; + wire plm_dfm_ns_phy_rctrl_l_iv_0_m2_0_1522; + wire plm_dfm_N_20788_i_1523; + wire plm_dfm_deframe1_N_35550_i; + wire plm_dfm_deframe1_N_35534_i; + wire plm_dfm_deframe1_N_35534_i_i; + wire plm_dfm_deframe1_N_35527_i; + wire plm_dfm_deframe1_N_35528_i; + wire plm_dfm_deframe1_N_35545_i; + wire plm_dfm_deframe1_reg_phi1; + wire plm_dfm_deframe1_N_87731_i; + wire plm_dfm_deframe1_high0; + wire plm_dfm_deframe1_high1; + wire plm_dfm_deframe1_high2; + wire plm_dfm_deframe1_high3; + wire plm_dfm_deframe1_ferr; + wire plm_dfm_deframe1_N_22418_i; + wire plm_dfm_deframe1_push1; + wire plm_dfm_deframe1_N_55957_i; + wire plm_dfm_deframe1_reg_det_d3_1524; + wire plm_dfm_deframe1_reg_det_d1_1525; + wire plm_dfm_deframe1_reg_det_d2_1526; + wire plm_dfm_deframe1_N_61202_i; + wire plm_dfm_deframe1_N_20140_i; + wire plm_dfm_deframe1_N_20138_i; + wire plm_dfm_deframe1_N_20136_i; + wire plm_dfm_deframe1_N_20134_i; + wire plm_dfm_deframe1_N_61203_i; + wire plm_dfm_deframe1_reg_dat_1_sqmuxa; + wire plm_dfm_deframe1_reg_dat_1_sqmuxa_1; + wire plm_dfm_deframe1_N_61205_i; + wire plm_dfm_deframe1_det_d0_i_i_1527; + wire plm_dfm_deframe1_dwfsm_reg_ferr_40_i_i_0_a2_1_0; + wire plm_dfm_deframe1_dwfsm_ns_fsm_framing_iv_i_i_0_a2_1_1528; + wire plm_dfm_deframe1_dwfsm_ns_fsm_errored_iv_0_0_0_1529; + wire plm_dfm_deframe1_dwfsm_N_35599_1; + wire plm_dfm_deframe1_dwfsm_ns_fsm_framing_iv_i_i_0_0_1530; + wire plm_dfm_deframe1_dwfsm_ns_fsm_framing_iv_i_i_0_a2_3_1531; + wire plm_dfm_deframe1_dwfsm_ns_fsm_framing_iv_i_i_0_a2_0_1532; + wire plm_dfm_deframe1_dwfsm_ns_fsm_framing_iv_i_i_0_a2_1533; + wire plm_dfm_deframe1_dwfsm_ns_fsm_errored_iv_0_0_1_1534; + wire plm_dfm_deframe1_dwfsm_N_35606_1; + wire plm_dfm_deframe1_dwfsm_reg_ferr_40_i_i_0_0; + wire plm_dfm_deframe1_dwfsm_ns_fsm_framing_iv_i_i_0_o4_1535; + wire plm_dfm_deframe1_dwfsm_N_22408_i; + wire plm_dfm_deframe1_dwfsm_reg_fsm_framing_1536; + wire plm_dfm_deframe1_dwfsm_N_9422_i; + wire plm_dfm_deframe1_dwfsm_reg_fsm_errored_1537; + wire plm_dfm_deframe1_dwfsm_N_22412_i; + wire plm_dfm_deframe1_dwfsm_N_22416_i; + wire plm_dfm_deframe1_dwfsm_reg_high60; + wire plm_dfm_deframe1_dwfsm_reg_high59; + wire plm_dfm_deframe1_dwfsm_reg_high58; + wire plm_dfm_deframe1_dwfsm_N_9772_i; + wire plm_dfm_deframe1_dwfsm_N_22414_i; + wire plm_dfm_deframe1_dwbuf_GND_1538; + wire plm_dfm_deframe1_dwbuf_un1_reg_cnt_1_cry_0_1539; + wire plm_dfm_deframe1_dwbuf_un1_reg_cnt_1_cry_1_1540; + wire plm_dfm_deframe1_dwbuf_un1_reg_cnt_1_cry_2_1541; + wire plm_dfm_deframe1_dwbuf_N_87784_i_1542; + wire plm_dfm_deframe1_dwbuf_N_87783_i_1543; + wire plm_dfm_deframe1_dwbuf_reg_wp0_4_p4; + wire plm_dfm_deframe1_dwbuf_reg_rp_4_p4; + wire plm_dfm_deframe1_dwbuf_reg_wp3_4_p4; + wire plm_dfm_deframe1_dwbuf_reg_wp2_4_p4; + wire plm_dfm_deframe1_dwbuf_reg_wp1_4_p4; + wire plm_dfm_deframe1_dwbuf_reg_empty_8_0_i_0; + wire plm_dfm_deframe1_dwbuf_un1_reg_empty19_0_o2_i_1_1544; + wire plm_dfm_deframe1_dwbuf_un1_reg_cnt_1_s_3_1545; + wire plm_dfm_deframe1_dwbuf_un1_reg_cnt_1_s_2_1546; + wire plm_dfm_deframe1_dwbuf_un1_reg_cnt_1_s_1_1547; + wire plm_dfm_deframe1_dwbuf_un1_reg_cnt_1_axb_0_1548; + wire plm_dfm_deframe1_dwbuf_N_35515_i; + wire plm_dfm_deframe1_dwbuf_N_35458_i; + wire plm_dfm_deframe1_dwbuf_reg_empty_1549; + wire plm_dfm_deframe1_dwbuf_un1_reg_cnt_1_axb_1_1550; + wire plm_dfm_deframe1_dwbuf_un1_reg_cnt_1_axb_2_1551; + wire plm_dfm_deframe1_dwbuf_un1_reg_cnt_1_axb_3_1552; + wire plm_dfm_deframe1_dwbuf_N_35533_i; + wire plm_dfm_deframe1_qwfsm_N_35544_i; + wire plm_dfm_deframe1_qwfsm_dword_pop_0_i_o2_0_o2_0_1553; + wire plm_dfm_deframe1_qwfsm_N_35555_i; + wire plm_dfm_deframe1_qwfsm_N_35536_i; + wire plm_dfm_deframe1_qwfsm_nxt_state_6_sqmuxa_0_a2_0_a2_0_1554; + wire plm_dfm_deframe1_qwfsm_N_35588_1; + wire plm_dfm_deframe1_qwfsm_N_35590_1; + wire plm_dfm_deframe1_qwfsm_N_35531_i; + wire plm_dfm_deframe1_qwfsm_reg_phi0_1555; + wire plm_dfm_deframe1_qwfsm_nxt_state_6_sqmuxa_1; + wire plm_dfm_deframe1_qwfsm_nxt_state_6_sqmuxa; + wire plm_dfm_deframe1_qwfsm_N_20723_i; + wire plm_dfm_deframe1_qwfsm_N_20725_i; + wire plm_dfm_deframe1_qwfsm_N_20721_i; + wire plm_dfm_deframe1_qwfsm_N_20680_i; + wire plm_dfm_deframe1_qwfsm_N_20689_i; + wire plm_dfm_deframe1_qwfsm_N_20691_i; + wire plm_dfm_deframe1_qwfsm_N_20693_i; + wire plm_dfm_deframe1_qwfsm_N_20695_i; + wire plm_dfm_deframe1_qwfsm_N_20697_i; + wire plm_dfm_deframe1_qwfsm_N_20699_i; + wire plm_dfm_deframe1_qwfsm_N_20701_i; + wire plm_dfm_deframe1_qwfsm_N_20703_i; + wire plm_dfm_deframe1_qwfsm_N_20678_i; + wire plm_dfm_deframe1_qwfsm_N_20676_i; + wire plm_dfm_deframe1_qwfsm_N_20674_i; + wire plm_dfm_deframe1_qwfsm_N_20672_i; + wire plm_dfm_deframe1_qwfsm_N_20670_i; + wire plm_dfm_deframe1_qwfsm_N_20668_i; + wire plm_dfm_deframe1_qwfsm_N_20666_i; + wire plm_dfm_deframe1_qwfsm_N_20664_i; + wire plm_dfm_deframe1_qwfsm_N_20662_i; + wire plm_dfm_deframe1_qwfsm_N_20660_i; + wire plm_dfm_deframe1_qwfsm_N_20658_i; + wire plm_dfm_deframe1_qwfsm_N_20656_i; + wire plm_dfm_deframe1_qwfsm_N_20654_i; + wire plm_dfm_deframe1_qwfsm_N_20652_i; + wire plm_dfm_deframe1_qwfsm_N_20650_i; + wire plm_dfm_deframe1_qwfsm_N_20648_i; + wire plm_dfm_deframe1_qwfsm_N_87743_i; + wire plm_dfm_deframe1_qwfsm_N_87742_i; + wire plm_dfm_deframe1_qwfsm_N_87741_i; + wire plm_dfm_deframe1_qwfsm_N_87740_i; + wire plm_dfm_deframe1_qwfsm_N_87739_i; + wire plm_dfm_deframe1_qwfsm_N_87738_i; + wire plm_dfm_deframe1_qwfsm_N_87737_i; + wire plm_dfm_deframe1_qwfsm_N_87736_i; + wire plm_dfm_deframe1_qwfsm_N_87769_i; + wire plm_dfm_deframe1_qwfsm_N_20686_i; + wire plm_dfm_deframe4_reg_o_dat_1_sqmuxa_1; + wire plm_dfm_deframe4_reg_o_edbedg15; + wire plm_dfm_deframe4_reg_o_edbedg16; + wire plm_dfm_deframe4_N_11335; + wire plm_dfm_deframe4_N_14414_i; + wire plm_dfm_deframe4_reg_df_dat_m_24__1556; + wire plm_dfm_deframe4_reg_df_dat_m_27__1557; + wire plm_dfm_deframe4_reg_df_dat_m_28__1558; + wire plm_dfm_deframe4_reg_df_dat_m_26__1559; + wire plm_dfm_deframe4_dh_dat_m_0_29__1560; + wire plm_dfm_deframe4_dh_dat_m_0_31__1561; + wire plm_dfm_deframe4_dh_valid; + wire plm_dfm_deframe4_reg_df_dat_m_30__1562; + wire plm_dfm_deframe4_reg_df_dat_m_25__1563; + wire plm_dfm_deframe4_N_11342; + wire plm_dfm_deframe4_N_11332; + wire plm_dfm_deframe4_det_d0_0_a2_0_a2_0_a3_0_a2_3_1564; + wire plm_dfm_deframe4_N_61405; + wire plm_dfm_deframe4_N_61402; + wire plm_dfm_deframe4_N_56145_i; + wire plm_dfm_deframe4_N_56146_i; + wire plm_dfm_deframe4_N_61403; + wire plm_dfm_deframe4_N_85591_1; + wire plm_dfm_deframe4_N_85588_1; + wire plm_dfm_deframe4_N_61404; + wire plm_dfm_deframe4_N_55905_i; + wire plm_dfm_deframe4_dl_valid; + wire plm_dfm_deframe4_reg_df_valid_1565; + wire plm_dfm_deframe4_N_61204_i_1566; + wire plm_dfm_deframe4_N_85591_i; + wire plm_dfm_deframe4_N_85590_i; + wire plm_dfm_deframe4_N_85589_i; + wire plm_dfm_deframe4_N_85588_i; + wire plm_dfm_deframe4_N_9810_i; + wire plm_dfm_deframe4_N_9811_i; + wire plm_dfm_deframe4_N_9812_i; + wire plm_dfm_deframe4_N_9813_i; + wire plm_dfm_deframe4_N_9814_i; + wire plm_dfm_deframe4_N_9815_i; + wire plm_dfm_deframe4_N_9816_i; + wire plm_dfm_deframe4_N_9817_i; + wire plm_dfm_deframe4_N_9818_i; + wire plm_dfm_deframe4_N_9819_i; + wire plm_dfm_deframe4_N_9820_i; + wire plm_dfm_deframe4_N_9821_i; + wire plm_dfm_deframe4_N_9822_i; + wire plm_dfm_deframe4_N_9795_i; + wire plm_dfm_deframe4_N_9796_i; + wire plm_dfm_deframe4_N_9797_i; + wire plm_dfm_deframe4_N_9798_i; + wire plm_dfm_deframe4_N_9799_i; + wire plm_dfm_deframe4_N_9800_i; + wire plm_dfm_deframe4_N_9801_i; + wire plm_dfm_deframe4_N_9802_i; + wire plm_dfm_deframe4_N_9803_i; + wire plm_dfm_deframe4_N_9804_i; + wire plm_dfm_deframe4_N_9805_i; + wire plm_dfm_deframe4_N_9806_i; + wire plm_dfm_deframe4_N_9807_i; + wire plm_dfm_deframe4_N_9808_i; + wire plm_dfm_deframe4_N_9809_i; + wire plm_dfm_deframe4_N_9845_i; + wire plm_dfm_deframe4_N_9846_i; + wire plm_dfm_deframe4_N_9847_i; + wire plm_dfm_deframe4_N_9848_i; + wire plm_dfm_deframe4_N_9849_i; + wire plm_dfm_deframe4_N_9850_i; + wire plm_dfm_deframe4_N_9851_i; + wire plm_dfm_deframe4_N_9852_i; + wire plm_dfm_deframe4_N_9853_i; + wire plm_dfm_deframe4_N_9854_i; + wire plm_dfm_deframe4_N_9855_i; + wire plm_dfm_deframe4_N_9791_i; + wire plm_dfm_deframe4_N_9792_i; + wire plm_dfm_deframe4_N_9793_i; + wire plm_dfm_deframe4_N_9794_i; + wire plm_dfm_deframe4_N_9830_i; + wire plm_dfm_deframe4_N_9831_i; + wire plm_dfm_deframe4_N_9832_i; + wire plm_dfm_deframe4_N_9833_i; + wire plm_dfm_deframe4_N_9834_i; + wire plm_dfm_deframe4_N_9835_i; + wire plm_dfm_deframe4_N_9836_i; + wire plm_dfm_deframe4_N_9837_i; + wire plm_dfm_deframe4_N_9838_i; + wire plm_dfm_deframe4_N_9839_i; + wire plm_dfm_deframe4_N_9840_i; + wire plm_dfm_deframe4_N_9841_i; + wire plm_dfm_deframe4_N_9842_i; + wire plm_dfm_deframe4_N_9843_i; + wire plm_dfm_deframe4_N_9844_i; + wire plm_dfm_deframe4_N_9824_i; + wire plm_dfm_deframe4_N_9825_i; + wire plm_dfm_deframe4_N_9826_i; + wire plm_dfm_deframe4_N_9827_i; + wire plm_dfm_deframe4_N_9828_i; + wire plm_dfm_deframe4_N_9829_i; + wire plm_dfm_deframe4_frm4hi_half_N_14411_i; + wire plm_dfm_deframe4_frm4hi_half_reg_o_edbedg_2_sqmuxa_1_1567; + wire plm_dfm_deframe4_frm4hi_half_m4_i_0_1; + wire plm_dfm_deframe4_frm4hi_half_N_14419; + wire plm_dfm_deframe4_frm4hi_half_un1_di_valid_m_1568; + wire plm_dfm_deframe4_frm4hi_half_N_14422; + wire plm_dfm_deframe4_frm4hi_half_N_10101; + wire plm_dfm_deframe4_frm4hi_half_reg_o_edbedg_1_sqmuxa_1_1569; + wire plm_dfm_deframe4_frm4hi_half_o_edbedg_sn_m1_39370_1570; + wire plm_dfm_deframe4_frm4hi_half_N_11343; + wire plm_dfm_deframe4_frm4hi_half_N_11340; + wire plm_dfm_deframe4_frm4hi_half_reg_o_edbedg70; + wire plm_dfm_deframe4_frm4hi_half_reg_o_edbedg68; + wire plm_dfm_deframe4_frm4hi_half_o_edbedg_sn_N_2; + wire plm_dfm_deframe4_frm4hi_half_N_14421; + wire plm_dfm_deframe4_frm4hi_half_N_14418_i; + wire plm_dfm_deframe4_frm4hi_half_m4_i_0_0; + wire plm_dfm_deframe4_frm4lo_half_reg_o_edbedg10; + wire plm_dfm_deframe4_frm4lo_half_reg_o_edbedg11; + wire plm_dfm_deframe4_frm4lo_half_reg_o_edbedg_2_sqmuxa_1_1571; + wire plm_dfm_deframe4_frm4lo_half_reg_o_edbedg_1_sqmuxa_1_1572; + wire plm_dfm_deframe4_frm4lo_half_reg_do_cmd_1_sqmuxa_2_1573; + wire plm_dfm_deframe4_frm4lo_half_reg_do_cmd_1_sqmuxa_1_1574; + wire plm_dfm_deframe4_frm4lo_half_o_edbedg_sn_m1_0_1575; + wire plm_dfm_deframe4_frm4lo_half_N_11334; + wire plm_dfm_deframe4_frm4lo_half_N_11333; + wire plm_dfm_deframe4_frm4lo_half_un1_di_valid_m_1576; + wire plm_dfm_deframe4_frm4lo_half_o_edbedg_sn_N_2; + wire plm_dfm_deframe4_frm4lo_half_reg_o_edbedg70; + wire plm_dfm_deframe4_frm4lo_half_reg_o_edbedg68; + wire plm_dfm_deframe4_frm4lo_half_un1_reg_do_cmd_0_sqmuxa_1_sn_i; + wire plm_dfm_deframe4_frm4lo_half_N_15_1; + wire plm_dfm_deframe4_frm4lo_half_N_6336; + wire plm_dfm_deframe4_frm4lo_half_N_11330; + wire plm_sym_un6_reg_count_cry_0_1577; + wire plm_sym_un6_reg_count_cry_1_1578; + wire plm_sym_un6_reg_count_cry_2_1579; + wire plm_sym_un6_reg_count_cry_3_1580; + wire plm_sym_un6_reg_count_cry_4_1581; + wire plm_sym_un6_reg_count_cry_5_1582; + wire plm_sym_un6_reg_count_cry_6_1583; + wire plm_sym_un6_reg_count_cry_7_1584; + wire plm_sym_un6_reg_count_cry_8_1585; + wire plm_sym_VCC_1586; + wire plm_sym_un6_reg_count_cry_9_1587; + wire plm_sym_un6_reg_count_cry_10_1588; + wire plm_sym_GND_1589; + wire plm_sym_un1_reg_outstanding_ccs_1_cry_0_1590; + wire plm_sym_un1_reg_outstanding_ccs_1_cry_1_1591; + wire plm_sym_un1_reg_outstanding_ccs_1_cry_2_1592; + wire plm_sym_un6_reg_count_s_11_sf_1593; + wire plm_sym_sym_symbol_14_; + wire plm_sym_sym_symbol_2_; + wire plm_sym_sym_symbol_10_; + wire plm_sym_sym_symbol_13_; + wire plm_sym_sym_symbol_15_; + wire plm_sym_sym_symbol_11_; + wire plm_sym_sym_symbol_6_; + wire plm_sym_sym_symbol_5_; + wire plm_sym_sym_symbol_3_; + wire plm_sym_N_56230_i; + wire plm_sym_sym_symbol_0_; + wire plm_sym_N_61369; + wire plm_sym_insert_ccs_8_1594; + wire plm_sym_insert_ccs_7_1595; + wire plm_sym_insert_ccs_6_1596; + wire plm_sym_N_10027; + wire plm_sym_N_10147; + wire plm_sym_N_61382; + wire plm_sym_N_9419_1; + wire plm_sym_N_58988; + wire plm_sym_N_36437_1_i; + wire plm_sym_reg_tx0_raw_char_8_i_0_0_0_0_39382; + wire plm_sym_reg_tx0_raw_char_8_i_0_0_0_0_39381; + wire plm_sym_un1_reg_outstanding_ccs_1_axb_3_1597; + wire plm_sym_un1_reg_outstanding_ccs_1_axb_2_1598; + wire plm_sym_un1_reg_outstanding_ccs_1_axb_1_1599; + wire plm_sym_frm_dispatched_ccs_1600; + wire plm_sym_N_56624; + wire plm_sym_N_58960; + wire plm_sym_N_56623; + wire plm_sym_N_55945_i; + wire plm_sym_N_56524; + wire plm_sym_N_58963; + wire plm_sym_N_58961; + wire plm_sym_N_38074; + wire plm_sym_N_56525; + wire plm_sym_N_56625; + wire plm_sym_N_58230; + wire plm_sym_N_56526; + wire plm_sym_N_58228; + wire plm_sym_N_58226; + wire plm_sym_N_58224; + wire plm_sym_N_59366; + wire plm_sym_N_58965; + wire plm_sym_N_36431_1_i; + wire plm_sym_N_36433_1_i; + wire plm_sym_N_36435_1_i; + wire plm_sym_N_85603_1; + wire plm_sym_N_36447_1_i; + wire plm_sym_N_55888_i; + wire plm_sym_N_36449_1_i; + wire plm_sym_un6_reg_count_s_11_1601; + wire plm_sym_un6_reg_count_s_10_1602; + wire plm_sym_un6_reg_count_s_9_sf_1603; + wire plm_sym_un6_reg_count_s_8_sf_1604; + wire plm_sym_un6_reg_count_s_7_1605; + wire plm_sym_un6_reg_count_s_6_1606; + wire plm_sym_un6_reg_count_s_5_1607; + wire plm_sym_un6_reg_count_s_4_1608; + wire plm_sym_un6_reg_count_s_3_1609; + wire plm_sym_un6_reg_count_s_2_1610; + wire plm_sym_un6_reg_count_s_1_1611; + wire plm_sym_N_61348; + wire plm_sym_N_59407; + wire plm_sym_N_61309; + wire plm_sym_N_58232; + wire plm_sym_N_56928_i; + wire plm_sym_N_58223; + wire plm_sym_N_58978; + wire plm_sym_sym_symbol_1_; + wire plm_sym_insert_ccs_1612; + wire plm_sym_reg_frm_atomic_1613; + wire plm_sym_N_85608_i; + wire plm_sym_N_85609_i; + wire plm_sym_N_85640_i; + wire plm_sym_N_85610_i; + wire plm_sym_un1_reg_outstanding_ccs_1_s_3_1614; + wire plm_sym_un1_reg_outstanding_ccs_1_s_2_1615; + wire plm_sym_un1_reg_outstanding_ccs_1_s_1_1616; + wire plm_sym_un1_reg_outstanding_ccs_1_axb_0_1617; + wire plm_sym_N_85639_i; + wire plm_sym_N_85604_i; + wire plm_sym_N_87198_i; + wire plm_sym_N_51828_i; + wire plm_sym_N_53136_i; + wire plm_sym_N_51826_i; + wire plm_sym_N_51824_i; + wire plm_sym_N_53134_i; + wire plm_sym_N_51822_i; + wire plm_sym_N_85560_i; + wire plm_sym_N_53132_i; + wire plm_sym_N_85562_i; + wire plm_sym_N_85605_i; + wire plm_sym_N_85606_i; + wire plm_sym_N_85607_i; + wire plm_sym_N_85638_i; + wire plm_sym_N_87225_i; + wire plm_sym_N_51838_i; + wire plm_sym_N_51836_i; + wire plm_sym_N_51834_i; + wire plm_sym_N_51832_i; + wire plm_sym_N_53138_i; + wire plm_sym_N_51830_i; + wire plm_sym_N_85561_i; + wire plm_sym_N_87567_i; + wire plm_sym_N_87486_i; + wire plm_sym_N_85601_i; + wire plm_sym_N_85602_i; + wire plm_sym_N_87094_i; + wire plm_sym_N_85603_i; + wire plm_sym_N_87224_i; + wire plm_sym_N_51850_i; + wire plm_sym_N_51848_i; + wire plm_sym_N_51846_i; + wire plm_sym_N_51844_i; + wire plm_sym_N_51842_i; + wire plm_sym_N_51840_i; + wire plm_sym_N_87475_i; + wire plm_sym_N_53140_i; + wire plm_sym_N_87478_i; + wire plm_sym_N_85633_i; + wire plm_sym_N_85634_i; + wire plm_sym_N_85635_i; + wire plm_sym_N_85636_i; + wire plm_sym_N_85637_i; + wire plm_sym_N_51860_i; + wire plm_sym_N_51858_i; + wire plm_sym_N_51856_i; + wire plm_sym_N_51854_i; + wire plm_sym_N_53142_i; + wire plm_sym_N_51852_i; + wire plm_sym_N_87476_i; + wire plm_sym_N_87568_i; + wire plm_sym_N_87479_i; + wire plm_sym_N_85627_i; + wire plm_sym_N_85628_i; + wire plm_sym_N_85629_i; + wire plm_sym_N_85630_i; + wire plm_sym_N_85631_i; + wire plm_sym_N_85632_i; + wire plm_sym_N_87196_i; + wire plm_sym_N_53144_i; + wire plm_sym_N_36576_i; + wire plm_sym_reg_count_5_11__1618; + wire plm_sym_reg_count_5_10__1619; + wire plm_sym_un6_reg_count_s_9_1620; + wire plm_sym_un6_reg_count_s_8_1621; + wire plm_sym_reg_count_5_7__1622; + wire plm_sym_reg_count_5_6__1623; + wire plm_sym_reg_count_5_5__1624; + wire plm_sym_reg_count_5_4__1625; + wire plm_sym_reg_count_5_3__1626; + wire plm_sym_reg_count_5_2__1627; + wire plm_sym_reg_count_5_1__1628; + wire plm_sym_reg_count_5_0__1629; + wire plm_sym_N_54688_i; + wire plm_sym_N_36574_i; + wire plm_sym_N_54690_i; + wire plm_sym_N_36578_i; + wire plm_sym_N_87227_i; + wire plm_sym_N_87195_i; + wire plm_sym_N_87226_i; + wire plm_sym_un6_reg_count_s_10_sf_1630; + wire plm_sym_un6_reg_count_s_7_sf_1631; + wire plm_sym_un6_reg_count_s_6_sf_1632; + wire plm_sym_un6_reg_count_s_5_sf_1633; + wire plm_sym_un6_reg_count_s_4_sf_1634; + wire plm_sym_un6_reg_count_s_3_sf_1635; + wire plm_sym_un6_reg_count_s_2_sf_1636; + wire plm_sym_un6_reg_count_s_1_sf_1637; + wire plm_sym_sym_gen_N_3303_i; + wire plm_sym_sym_gen_N_214; + wire plm_sym_sym_gen_N_116; + wire plm_sym_sym_gen_N_126; + wire plm_sym_sym_gen_N_3311; + wire plm_sym_sym_gen_N_139; + wire plm_sym_sym_gen_N_111_i; + wire plm_sym_sym_gen_reg_rom_out_27_6_; + wire plm_sym_sym_gen_N_10508_i_1638; + wire plm_sym_sym_gen_reg_rom_out_27_4_; + wire plm_sym_sym_gen_reg_rom_out_27_3_; + wire plm_sym_sym_gen_reg_rom_out_27_2_; + wire plm_sym_sym_gen_reg_rom_out_27_1_; + wire plm_sym_sym_gen_reg_rom_out_27_0_; + wire plm_sym_sym_gen_N_10520_i_1639; + wire plm_sym_sym_gen_N_10521_i_1640; + wire plm_sym_sym_gen_N_10522_i_1641; + wire plm_sym_sym_gen_reg_rom_out_27_24_; + wire plm_sym_sym_gen_reg_rom_out_27_23_; + wire plm_sym_sym_gen_reg_rom_out_27_22_; + wire plm_sym_sym_gen_reg_rom_out_27_9_; + wire plm_sym_sym_gen_N_202_i_i_1642; + wire plm_sym_sym_gen_next_addr45; + wire plm_sym_sym_gen_next_addr44; + wire plm_sym_sym_gen_next_addr43; + wire plm_sym_sym_gen_next_addr40; + wire plm_sym_sym_gen_next_addr39; + wire plm_sym_sym_gen_reg_rom_out_27_32_; + wire plm_sym_sym_gen_reg_rom_out_27_31_; + wire plm_sym_sym_gen_reg_rom_out_27_30_; + wire plm_sym_sym_gen_reg_rom_out_27_29_; + wire plm_sym_sym_gen_reg_rom_out_27_28_; + wire plm_frm_reg_byp3; + wire plm_frm_reg_byp1; + wire plm_frm_N_61321; + wire plm_frm_N_56427_i_0; + wire plm_frm_N_55890; + wire plm_frm_N_61354; + wire plm_frm_N_61329; + wire plm_frm_N_57641; + wire plm_frm_reg_frm0_char_3_0_0_8_; + wire plm_frm_N_57598; + wire plm_frm_reg_frm0_char_3_i_0_11_; + wire plm_frm_N_57619; + wire plm_frm_reg_frm0_char_3_0_0_9_; + wire plm_frm_N_57605; + wire plm_frm_reg_frm0_char_3_0_0_14_; + wire plm_frm_N_57640; + wire plm_frm_reg_frm0_char_3_i_0_10_; + wire plm_frm_N_57612; + wire plm_frm_reg_frm0_char_3_i_0_12_; + wire plm_frm_N_57626; + wire plm_frm_reg_frm0_char_3_0_0_6_; + wire plm_frm_N_57584; + wire plm_frm_reg_frm0_char_3_i_0_4_; + wire plm_frm_N_57569; + wire plm_frm_N_58402; + wire plm_frm_reg_frm0_char_3_i_0_3_; + wire plm_frm_N_57562; + wire plm_frm_N_58409; + wire plm_frm_reg_frm0_char_3_0_0_0_; + wire plm_frm_N_57555; + wire plm_frm_N_56240_i; + wire plm_frm_reg_frm_atomic_3_i_o3_0; + wire plm_frm_N_51332_i; + wire plm_frm_N_55915_i; + wire plm_frm_N_51330_i; + wire plm_frm_N_55877_i; + wire plm_frm_reg_frm_atomic_3_i_0; + wire plm_frm_reg_frm_atomic_3_i_o3; + wire plm_frm_reg_frm0_char_3_0_3_6_; + wire plm_frm_reg_frm0_char_3_0_2_6_; + wire plm_frm_N_57573; + wire plm_frm_reg_frm0_char_3_i_3_4_; + wire plm_frm_reg_frm0_char_3_i_2_4_; + wire plm_frm_reg_frm0_char_3_i_3_3_; + wire plm_frm_reg_frm0_char_3_i_2_3_; + wire plm_frm_reg_frm0_char_3_0_3_0_; + wire plm_frm_reg_frm0_char_3_0_2_0_; + wire plm_frm_N_57627; + wire plm_frm_N_61390; + wire plm_frm_N_58415; + wire plm_frm_reg_frm0_char_3_0_3_14_; + wire plm_frm_reg_frm0_char_3_0_2_14_; + wire plm_frm_reg_frm0_char_3_i_3_12_; + wire plm_frm_reg_frm0_char_3_i_2_12_; + wire plm_frm_reg_frm0_char_3_i_3_11_; + wire plm_frm_reg_frm0_char_3_i_2_11_; + wire plm_frm_reg_frm0_char_3_i_3_10_; + wire plm_frm_reg_frm0_char_3_i_2_10_; + wire plm_frm_reg_frm0_char_3_0_3_9_; + wire plm_frm_reg_frm0_char_3_0_2_9_; + wire plm_frm_reg_frm0_char_3_0_3_8_; + wire plm_frm_reg_frm0_char_3_0_2_8_; + wire plm_frm_N_57634_1; + wire plm_frm_reg_d1_idleflag_hh_3_4; + wire plm_frm_reg_d1_idleflag_hh_3_0; + wire plm_frm_reg_d1_idleflag_hl_3_4; + wire plm_frm_reg_d1_idleflag_hl_3_0; + wire plm_frm_reg_d1_idleflag_lh_3_4; + wire plm_frm_reg_d1_idleflag_lh_3_0; + wire plm_frm_reg_d1_idleflag_ll_3_4; + wire plm_frm_reg_d1_idleflag_ll_3_0; + wire plm_frm_N_57042_i; + wire plm_frm_N_57648; + wire plm_frm_N_56105_i; + wire plm_frm_N_61261; + wire plm_frm_N_63791_i; + wire plm_frm_N_55866_i_0; + wire plm_frm_N_57040_i; + wire plm_frm_d1_end_h_1643; + wire plm_frm_N_56109_i; + wire plm_frm_N_63777_i; + wire plm_frm_N_57655; + wire plm_frm_N_56005_i; + wire plm_frm_N_55867_i_0; + wire plm_frm_N_61385; + wire plm_frm_N_61332; + wire plm_frm_reg_frm0_char_3_0_0_5_; + wire plm_frm_reg_frm0_char_3_0_4_5_; + wire plm_frm_reg_frm0_char_3_0_4_1_5_; + wire plm_frm_reg_frm0_char_3_0_0_7_; + wire plm_frm_N_61368; + wire plm_frm_N_61365; + wire plm_frm_reg_frm0_char_3_0_4_7_; + wire plm_frm_reg_frm0_char_3_0_4_1_7_; + wire plm_frm_N_61367; + wire plm_frm_N_61366; + wire plm_frm_N_55996_i; + wire plm_frm_N_51380_i; + wire plm_frm_N_85680_i; + wire plm_frm_N_85679_i; + wire plm_frm_N_85678_i; + wire plm_frm_N_51364_i; + wire plm_frm_N_51362_i; + wire plm_frm_N_14936_i; + wire plm_frm_N_85688_i; + wire plm_frm_N_85675_i; + wire plm_frm_N_85687_i; + wire plm_frm_N_52046_i; + wire plm_frm_N_58309_i; + wire plm_frm_by4_frm1_char_1_; + wire plm_frm_by4_frm1_char_0_; + wire plm_frm_N_87088_i; + wire plm_frm_N_58376_i; + wire plm_frm_N_86003_i; + wire plm_frm_N_55875_i; + wire plm_frm_N_85686_i; + wire plm_frm_N_51375_i; + wire plm_frm_N_51373_i; + wire plm_frm_N_51371_i; + wire plm_frm_N_85682_i; + wire plm_frm_N_85681_i; + wire plm_frm_by4_frm2_char_1_; + wire plm_frm_by4_frm2_char_0_; + wire plm_frm_N_51878_i; + wire plm_frm_N_51341_i; + wire plm_frm_N_51880_i; + wire plm_frm_N_86982_i; + wire plm_frm_N_86981_i; + wire plm_frm_N_86980_i; + wire plm_frm_N_51339_i; + wire plm_frm_N_51337_i; + wire plm_frm_N_86973_i; + wire plm_frm_by4_frm1_char_6_; + wire plm_frm_N_86974_i; + wire plm_frm_N_58311_i; + wire plm_frm_N_58310_i; + wire plm_frm_by4_frm3_char_0_; + wire plm_frm_N_51874_i; + wire plm_frm_N_51350_i; + wire plm_frm_N_51876_i; + wire plm_frm_N_86985_i; + wire plm_frm_N_86984_i; + wire plm_frm_N_86983_i; + wire plm_frm_N_51348_i; + wire plm_frm_N_51346_i; + wire plm_frm_N_86971_i; + wire plm_frm_by4_frm2_char_6_; + wire plm_frm_N_86972_i; + wire plm_frm_N_58314_i; + wire plm_frm_N_58313_i; + wire plm_frm_N_58312_i; + wire plm_frm_N_51870_i; + wire plm_frm_N_51359_i; + wire plm_frm_N_51872_i; + wire plm_frm_N_86988_i; + wire plm_frm_N_86987_i; + wire plm_frm_N_86986_i; + wire plm_frm_N_51357_i; + wire plm_frm_N_51355_i; + wire plm_frm_N_86969_i; + wire plm_frm_by4_frm3_char_6_; + wire plm_frm_N_86970_i; + wire plm_frm_N_58317_i; + wire plm_frm_N_58316_i; + wire plm_frm_N_58315_i; + wire plm_frm_by4_frm3_char_1_; + wire plm_frm_reg_d0_tctrl_h_1644; + wire plm_frm_reg_d1_tctrl_h_1645; + wire plm_frm_reg_d0_tctrl_l_1646; + wire plm_frm_reg_d1_tctrl_l_1647; + wire plm_frm_reg_d0_tframe_h_1648; + wire plm_frm_reg_d0_tframe_l_1649; + wire plm_frm_reg_d1_tframe_h_1650; + wire plm_frm_reg_d2_tframe_h_1651; + wire plm_frm_reg_d1_tframe_l_1652; + wire plm_frm_reg_d2_tframe_l_1653; + wire plm_frm_reg_d1_idleflag_hh_3; + wire plm_frm_reg_d1_idleflag_hh_1654; + wire plm_frm_reg_d1_idleflag_hl_3; + wire plm_frm_reg_d1_idleflag_hl_1655; + wire plm_frm_reg_d1_idleflag_lh_3; + wire plm_frm_reg_d1_idleflag_lh_1656; + wire plm_frm_reg_d1_idleflag_ll_3; + wire plm_frm_reg_d1_idleflag_ll_1657; + wire plm_frm_N_55314_i; + wire plm_frm_reg_d2_idle_h_1658; + wire plm_frm_N_57067_i; + wire plm_frm_reg_d2_idle_l_1659; + wire plm_frm_N_58272; + wire plm_frm_reg_d2_charisk_0__1660; + wire plm_frm_N_51384_i; + wire plm_frm_reg_d2_charisk_7__1661; + wire plm_frm_N_51382_i; + wire plm_frm_reg_d2_charisk_4__1662; + wire plm_frm_N_51388_i; + wire plm_frm_reg_d2_charisk_3__1663; + wire plm_frm_N_87072_i; + wire plm_frm_N_51438_i; + wire plm_frm_N_87033_i; + wire plm_frm_N_51436_i; + wire plm_frm_N_51434_i; + wire plm_frm_N_87073_i; + wire plm_frm_N_87034_i; + wire plm_frm_N_87035_i; + wire plm_frm_N_51432_i; + wire plm_frm_N_51430_i; + wire plm_frm_N_51428_i; + wire plm_frm_N_51426_i; + wire plm_frm_N_51424_i; + wire plm_frm_N_51422_i; + wire plm_frm_N_51420_i; + wire plm_frm_N_51418_i; + wire plm_frm_N_51416_i; + wire plm_frm_N_51414_i; + wire plm_frm_N_51412_i; + wire plm_frm_N_51410_i; + wire plm_frm_N_51408_i; + wire plm_frm_N_51406_i; + wire plm_frm_N_51404_i; + wire plm_frm_N_51402_i; + wire plm_frm_N_51400_i; + wire plm_frm_N_51398_i; + wire plm_frm_N_51396_i; + wire plm_frm_N_51394_i; + wire plm_frm_N_51392_i; + wire plm_frm_N_51390_i; + wire plm_frm_N_9897_i; + wire plm_frm_N_9899_i; + wire plm_frm_N_9882_i; + wire plm_frm_N_51488_i; + wire plm_frm_N_9884_i; + wire plm_frm_N_51486_i; + wire plm_frm_N_51484_i; + wire plm_frm_N_9885_i; + wire plm_frm_N_9886_i; + wire plm_frm_N_9887_i; + wire plm_frm_N_51482_i; + wire plm_frm_N_51480_i; + wire plm_frm_N_51478_i; + wire plm_frm_N_51476_i; + wire plm_frm_N_51474_i; + wire plm_frm_N_51472_i; + wire plm_frm_N_51470_i; + wire plm_frm_N_51468_i; + wire plm_frm_N_51466_i; + wire plm_frm_N_51464_i; + wire plm_frm_N_51462_i; + wire plm_frm_N_51460_i; + wire plm_frm_N_51458_i; + wire plm_frm_N_51456_i; + wire plm_frm_N_51454_i; + wire plm_frm_N_51452_i; + wire plm_frm_N_51450_i; + wire plm_frm_N_51448_i; + wire plm_frm_N_51446_i; + wire plm_frm_N_51444_i; + wire plm_frm_N_51442_i; + wire plm_frm_N_51440_i; + wire plm_frm_N_87025_i; + wire plm_frm_N_85671_i; + wire plm_frm_N_85671_i_1; + wire plm_frm_N_85690_i; + wire plm_frm_N_85690_i_1; + wire plm_frm_N_61353; + wire plm_frm_N_14937_1_i; + wire plm_frm_frame4_N_58253; + wire plm_frm_frame4_N_51496_i; + wire plm_frm_frame4_N_51494_i; + wire plm_fsm_reg_tx_expired; + wire plm_fsm_N_61249_i; + wire plm_fsm_reg_tx_count_4_; + wire plm_fsm_reg_tx_count_10_; + wire plm_fsm_N_58715_1; + wire plm_fsm_N_58716_1; + wire plm_fsm_N_58717_1; + wire plm_fsm_N_58718_1; + wire plm_fsm_N_59110_1; + wire plm_fsm_N_59112_1; + wire plm_fsm_reg_tx_count_6_10_; + wire plm_fsm_reg_tx_count_6_4_; + wire plm_fsm_ri_cntrout3; + wire plm_fsm_ri_cntrout1; + wire plm_fsm_ci_cntrout3; + wire plm_fsm_ci_cntrout1; + wire plm_fsm_cc_cntrout1; + wire plm_fsm_rc_cntrout_ts2_3; + wire plm_fsm_rc_cntrout_ts2_2; + wire plm_fsm_rl_extdout; + wire plm_fsm_rl_cntrout0; + wire plm_fsm_rc_cntrout_ts1_3; + wire plm_fsm_rc_cntrout_ts1_2; + wire plm_fsm_rc_cntrout_ts1_1; + wire plm_fsm_rl_cntrout3; + wire plm_fsm_rl_cntrout2; + wire plm_fsm_rl_cntrout1; + wire plm_fsm_pa_cntrout3; + wire plm_fsm_pa_cntrout2; + wire plm_fsm_pa_cntrout1; + wire plm_fsm_pa_cntrout0; + wire plm_fsm_reg_noscramble54_0_o3_i_o3_1; + wire plm_fsm_cc_cntrout3; + wire plm_fsm_cc_cntrout2; + wire plm_fsm_N_47404_i_0_o3_4_1664; + wire plm_fsm_N_47404_i_0_o3_0_1665; + wire plm_fsm_un2_ri_reconfig_0_1666; + wire plm_fsm_un1_reg_state_18_i_0_0_0_2_1_1_1667; + wire plm_fsm_reg_123_link_pad_8_1; + wire plm_fsm_rc_cntrout_ts2_1; + wire plm_fsm_rc_cntrout_ts2_0; + wire plm_fsm_reg_rx_clear_cs273_0; + wire plm_fsm_hr_restart_0_0_0_a2_2_0_1668; + wire plm_fsm_un3_clw0_newv_NE_3_1669; + wire plm_fsm_un3_clw0_newv_NE_1_1670; + wire plm_fsm_N_56421_i_0; + wire plm_fsm_un3_xl_clw0_newv_NE_3_1671; + wire plm_fsm_un3_xl_clw0_newv_NE_1_1672; + wire plm_fsm_N_56419_i_0; + wire plm_fsm_un3_clw3_newv_NE_3_1673; + wire plm_fsm_un3_clw2_newv_NE_3_1674; + wire plm_fsm_un3_clw1_newv_NE_3_1675; + wire plm_fsm_N_56214_i; + wire plm_fsm_N_45455_1; + wire plm_fsm_N_56931_i; + wire plm_fsm_ri_idle_data_i_o3_0_1676; + wire plm_fsm_ri_cntrout2; + wire plm_fsm_ri_cntrout0; + wire plm_fsm_ci_idle_data_i_o3_0_1677; + wire plm_fsm_ci_cntrout2; + wire plm_fsm_ci_cntrout0; + wire plm_fsm_un2_ruined_by4_NE_3_1678; + wire plm_fsm_un2_ruined_by4_NE_2_1679; + wire plm_fsm_un2_ruined_by4_NE_1_1680; + wire plm_fsm_un2_ruined_by4_NE_0_1681; + wire plm_fsm_un4_ruined_by4_NE_3_1682; + wire plm_fsm_un4_ruined_by4_NE_2_1683; + wire plm_fsm_un4_ruined_by4_NE_1_1684; + wire plm_fsm_un4_ruined_by4_NE_0_1685; + wire plm_fsm_un6_ruined_by4_NE_3_1686; + wire plm_fsm_un6_ruined_by4_NE_2_1687; + wire plm_fsm_un6_ruined_by4_NE_1_1688; + wire plm_fsm_un6_ruined_by4_NE_0_1689; + wire plm_fsm_un1_linklanematch0_NE_3_1690; + wire plm_fsm_un1_linklanematch0_NE_2_1691; + wire plm_fsm_un1_linklanematch0_NE_1_1692; + wire plm_fsm_un1_linklanematch0_NE_0_1693; + wire plm_fsm_l0_exit_reason_0_0_0_1_1694; + wire plm_fsm_N_57532; + wire plm_fsm_hr_restart_0_0_0_1_1695; + wire plm_fsm_N_57538; + wire plm_fsm_reg_rx_clear_cs273; + wire plm_fsm_un3_xl_clw2_newv_NE_2_1696; + wire plm_fsm_un3_xl_clw2_newv_NE_1_1697; + wire plm_fsm_un3_xl_clw2_newv_NE_0_1698; + wire plm_fsm_un3_clw3_newv_NE_2_1699; + wire plm_fsm_un3_clw3_newv_NE_1_1700; + wire plm_fsm_un3_clw3_newv_NE_0_1701; + wire plm_fsm_N_36967; + wire plm_fsm_cc_cntrout0; + wire plm_fsm_un1_reg_state_14_1702; + wire plm_fsm_N_38077_i; + wire plm_fsm_N_14931_i; + wire plm_fsm_un3_clw1_newv_NE_4_1703; + wire plm_fsm_un3_clw1_newv_NE_2_1704; + wire plm_fsm_un3_clw1_newv_NE_1_1705; + wire plm_fsm_un3_clw1_newv_NE_0_1706; + wire plm_fsm_un3_clw2_newv_NE_4_1707; + wire plm_fsm_un3_clw2_newv_NE_2_1708; + wire plm_fsm_un3_clw2_newv_NE_1_1709; + wire plm_fsm_un3_clw2_newv_NE_0_1710; + wire plm_fsm_un1_rc_cntrout_ts1_0_1_i; + wire plm_fsm_reg_rx_clear_cs_98_0_0_1_iv_0_1; + wire plm_fsm_N_63496; + wire plm_fsm_un3_clw0_newv_NE_5_1711; + wire plm_fsm_un3_clw0_newv_NE_4_1712; + wire plm_fsm_un3_clw0_newv_NE_0_1713; + wire plm_fsm_un3_xl_clw2_newv_NE_6_1714; + wire plm_fsm_un3_xl_clw0_newv_NE_5_1715; + wire plm_fsm_un3_xl_clw0_newv_NE_4_1716; + wire plm_fsm_un3_xl_clw0_newv_NE_0_1717; + wire plm_fsm_N_47001_i; + wire plm_fsm_un1_reg_state_18_i_0_0_o3_2_0_1718; + wire plm_fsm_N_56359_i; + wire plm_fsm_N_36833_i; + wire plm_fsm_N_37129_7; + wire plm_fsm_N_56117_i; + wire plm_fsm_un3_clw3_newv_NE_6_1719; + wire plm_fsm_un3_clw3_newv_NE_4_1720; + wire plm_fsm_N_55908_i; + wire plm_fsm_reg_rx_clear_cs_5_sqmuxa_2_1_1_1721; + wire plm_fsm_reg_rx_clear_cs_0_sqmuxa_10_2; + wire plm_fsm_N_11044; + wire plm_fsm_un1_reg_rx_clear_cs_0_sqmuxa_2_2_0_a2_0_0_1722; + wire plm_fsm_reg_rx_clear_cs21; + wire plm_fsm_N_11053; + wire plm_fsm_good_by4_1; + wire plm_fsm_reg_rx_clear_cs_98_0_0_1_iv_0_3; + wire plm_fsm_reg_rx_clear_cs_98_0_0_1_iv_0_4; + wire plm_fsm_N_56333_i; + wire plm_fsm_reg_state_1_sqmuxa_6_1723; + wire plm_fsm_reg_state_4_sqmuxa_2_1_1724; + wire plm_fsm_cls_timeout; + wire plm_fsm_reg_rx_clear_cs_2_sqmuxa_1_1_1725; + wire plm_fsm_N_36844_i; + wire plm_fsm_N_56187_i; + wire plm_fsm_N_63249; + wire plm_fsm_N_56470_i; + wire plm_fsm_N_55883_i; + wire plm_fsm_N_61287_2; + wire plm_fsm_reg_rx_clear_cs_1_sqmuxa_3_1726; + wire plm_fsm_reg_rx_clear_cs_1_sqmuxa_1727; + wire plm_fsm_N_58786; + wire plm_fsm_reg_state_4_sqmuxa_1_1_1728; + wire plm_fsm_reg_state_2_sqmuxa_2_1_1729; + wire plm_fsm_un1_reg_rx_clear_cs_0_sqmuxa_2_2_0_1_1730; + wire plm_fsm_N_21906; + wire plm_fsm_reg_rx_clear_cs_3_sqmuxa_4_1731; + wire plm_fsm_reg_rx_clear_cs230; + wire plm_fsm_reg_state_141_0_0_1_iv_0_0_; + wire plm_fsm_reg_rx_clear_cs_2_sqmuxa_11_1_0_o2_0_0_0_0_1732; + wire plm_fsm_N_58784; + wire plm_fsm_un1_reg_state_18_i_0_0_0_a2_0_1_1733; + wire plm_fsm_N_61287_1; + wire plm_fsm_reg_rx_clear_cs389_i_0_i2_0_0_a2_0_i_o3_0_a2_0_0; + wire plm_fsm_N_61287_4; + wire plm_fsm_N_61232_1; + wire plm_fsm_reg_state_1_sqmuxa_11_1734; + wire plm_fsm_reg_rx_clear_cs_0_sqmuxa_7; + wire plm_fsm_reg_rx_clear_cs_98_0_0_1_iv_0_9; + wire plm_fsm_reg_rx_clear_cs_98_0_0_1_iv_0_5; + wire plm_fsm_N_57049_i; + wire plm_fsm_un1_reg_rx_clear_cs_0_sqmuxa_2_2_0_4_1735; + wire plm_fsm_un1_reg_state_4_i; + wire plm_fsm_reg_state_141_0_0_1_iv_0_39432; + wire plm_fsm_N_9373_1; + wire plm_fsm_xl_ruined_by4_m; + wire plm_fsm_reg_rx_clear_cs_1_sqmuxa_2_1736; + wire plm_fsm_reg_rx_clear_cs_98_0_0_1_iv_0_14; + wire plm_fsm_reg_rx_clear_cs_98_0_0_1_iv_0_10; + wire plm_fsm_reg_123_link_pad_36_sn_m2_0_a2_1; + wire plm_fsm_N_55846_i; + wire plm_fsm_N_61272; + wire plm_fsm_N_56480_i; + wire plm_fsm_un1_reg_state_18_i_0_0_o3_2_1_1737; + wire plm_fsm_un1_reg_state_18_i_0_0_o3_2_39428_1738; + wire plm_fsm_N_58424; + wire plm_fsm_reg_rx_clear_cs_4_sqmuxa_1_1739; + wire plm_fsm_N_63492; + wire plm_fsm_N_11035_2; + wire plm_fsm_N_11035_1; + wire plm_fsm_ruined_by4_0_1740; + wire plm_fsm_N_85506_1; + wire plm_fsm_N_11048; + wire plm_fsm_N_58423; + wire plm_fsm_reg_123_link_pad_36_2_0_bm; + wire plm_fsm_reg_123_link_pad_36_2_0_am; + wire plm_fsm_good_by1; + wire plm_fsm_reg_state_141_0_0_1_iv_0_9_; + wire plm_fsm_N_36528_i; + wire plm_fsm_reg_state_141_0_0_1_iv_8_39434; + wire plm_fsm_N_61331; + wire plm_fsm_N_36409_i; + wire plm_fsm_N_60908; + wire plm_fsm_N_47451_i; + wire plm_fsm_N_36977_1_i_i; + wire plm_fsm_N_59392_1; + wire plm_fsm_N_63481; + wire plm_fsm_N_60902; + wire plm_fsm_un1_rx0_lane_pad; + wire plm_fsm_N_38052; + wire plm_fsm_reg_state_5_sqmuxa_1_1741; + wire plm_fsm_pc_timeout_1; + wire plm_fsm_reg_state_141_0_0_1_iv_2_39429; + wire plm_fsm_N_63256; + wire plm_fsm_N_14639; + wire plm_fsm_N_55942_i; + wire plm_fsm_N_54682_2_i; + wire plm_fsm_reg_rx_clear_cs_2_sqmuxa_8_1742; + wire plm_fsm_reg_state_2_sqmuxa_9_1743; + wire plm_fsm_reg_state_3_sqmuxa_5_1_1744; + wire plm_fsm_xl_cls_timeout; + wire plm_fsm_reg_state_1_sqmuxa_2_1745; + wire plm_fsm_reg_state1140; + wire plm_fsm_reg_state_2_sqmuxa_8_1746; + wire plm_fsm_reg_state_141_0_0_1_iv_0_18_; + wire plm_fsm_N_10498; + wire plm_fsm_hr_timeout; + wire plm_fsm_reg_rx_clear_cs_5_sqmuxa_2_1_1747; + wire plm_fsm_reg_rx_clear_cs_0_sqmuxa_5_1748; + wire plm_fsm_reg_rx_clear_cs_0_sqmuxa_3_1749; + wire plm_fsm_N_62888; + wire plm_fsm_reg_rx_clear_cs_3_sqmuxa_3_1_1750; + wire plm_fsm_reg_state_0_sqmuxa_8_i_0_1751; + wire plm_fsm_reg_rx_clear_cs_1_sqmuxa_1_0_1752; + wire plm_fsm_rc_timeout; + wire plm_fsm_rc_cntrout_ts1_0; + wire plm_fsm_reg_state_1_sqmuxa_4_i_0_1753; + wire plm_fsm_l0_exit_reason_i; + wire plm_fsm_hr_restart_i; + wire plm_fsm_ri_idle_data_0_i_1754; + wire plm_fsm_reg_state_2_sqmuxa_3_1_1755; + wire plm_fsm_ci_timeout; + wire plm_fsm_N_61287_1_0; + wire plm_fsm_N_3265_1_0; + wire plm_fsm_N_58729; + wire plm_fsm_N_11039; + wire plm_fsm_reg_123_lane_pad_35_iv_0; + wire plm_fsm_N_5866_1_0; + wire plm_fsm_un1_reg_state_15_i_0_0_0_1756; + wire plm_fsm_reg_rx_clear_cs_4_sqmuxa_1_0; + wire plm_fsm_N_59392; + wire plm_fsm_N_59391; + wire plm_fsm_reg_rx_clear_cs_1_sqmuxa_5_1757; + wire plm_fsm_N_5868; + wire plm_fsm_N_5866; + wire plm_fsm_un1_reg_state_22_i_0_0_0_1_1758; + wire plm_fsm_N_85520_1; + wire plm_fsm_N_61276_1; + wire plm_fsm_N_60900; + wire plm_fsm_N_58420; + wire plm_fsm_N_57051; + wire plm_fsm_N_47500_i_0; + wire plm_fsm_N_7175_1; + wire plm_fsm_reg_rx_clear_cs_98_0_0_1_iv_0_21; + wire plm_fsm_reg_rx_clear_cs_0_sqmuxa_11_1759; + wire plm_fsm_reg_rx_clear_cs_98_0_0_1_iv_0_21_1; + wire plm_fsm_reg_rx_clear_cs_98_0_0_1_iv_0_18; + wire plm_fsm_reg_rx_clear_cs_98_0_0_1_iv_0_15; + wire plm_fsm_N_60908_2; + wire plm_fsm_N_9911; + wire plm_fsm_N_54760_i; + wire plm_fsm_reg_rx_clear_cs_2_sqmuxa_10_1_i_0_i_a3_i_1_1760; + wire plm_fsm_N_60908_1; + wire plm_fsm_N_9904; + wire plm_fsm_pc_cntrout3; + wire plm_fsm_pc_cntrout2; + wire plm_fsm_pc_cntrout1; + wire plm_fsm_pc_cntrout0; + wire plm_fsm_N_61291; + wire plm_fsm_un3_xl_clw3_newv_NE_1_1761; + wire plm_fsm_un3_xl_clw3_newv_NE_0_1762; + wire plm_fsm_N_58785; + wire plm_fsm_un3_xl_clw3_newv_NE_3_1763; + wire plm_fsm_un3_xl_clw3_newv_NE_2_1764; + wire plm_fsm_reg_rx_clear_cs_2_sqmuxa_11_1_0_o2_0_0_0_a2_0_1_1765; + wire plm_fsm_un3_xl_clw1_newv_NE_3_1766; + wire plm_fsm_un3_xl_clw1_newv_NE_0_1767; + wire plm_fsm_N_58787; + wire plm_fsm_un3_xl_clw1_newv_NE_2_1768; + wire plm_fsm_un3_xl_clw1_newv_NE_1_1769; + wire plm_fsm_reg_rx_clear_cs_2_sqmuxa_11_1_0_o2_0_0_0_a2_2_1_1770; + wire plm_fsm_un3_xl_clw2_newv_NE_4_1771; + wire plm_fsm_un3_xl_clw2_newv_NE_4_1_1772; + wire plm_fsm_N_45455_1_i_1773; + wire plm_fsm_N_56131_i; + wire plm_fsm_N_55934_i; + wire plm_fsm_un1_reg_state_4_i_i_1774; + wire plm_fsm_N_56356_i; + wire plm_fsm_N_63251; + wire plm_fsm_reg_state_3_sqmuxa_4_1775; + wire plm_fsm_N_38054; + wire plm_fsm_reg_rx_clear_cs230_1; + wire plm_fsm_N_11041; + wire plm_fsm_N_14468_i; + wire plm_fsm_N_9373_i; + wire plm_fsm_N_10369_i; + wire plm_fsm_N_10368_i; + wire plm_fsm_reg_state_8__1776; + wire plm_fsm_N_85499_i; + wire plm_fsm_reg_state_7__1777; + wire plm_fsm_N_87557_i; + wire plm_fsm_reg_state_6__1778; + wire plm_fsm_N_10496_i; + wire plm_fsm_reg_state_5__1779; + wire plm_fsm_N_10497_i; + wire plm_fsm_reg_state_4__1780; + wire plm_fsm_N_10366_i; + wire plm_fsm_reg_state_3__1781; + wire plm_fsm_N_10365_i; + wire plm_fsm_N_87545_i; + wire plm_fsm_N_10364_i; + wire plm_fsm_reg_state_0__1782; + wire plm_fsm_N_85511_i; + wire plm_fsm_reg_state_24__1783; + wire plm_fsm_reg_state_23__1784; + wire plm_fsm_N_10485_i; + wire plm_fsm_reg_state_22__1785; + wire plm_fsm_N_10486_i; + wire plm_fsm_reg_state_21__1786; + wire plm_fsm_N_10487_i; + wire plm_fsm_reg_state_20__1787; + wire plm_fsm_N_10488_i; + wire plm_fsm_reg_state_19__1788; + wire plm_fsm_N_10489_i; + wire plm_fsm_reg_state_18__1789; + wire plm_fsm_N_10491_i; + wire plm_fsm_N_10373_i; + wire plm_fsm_N_10492_i; + wire plm_fsm_reg_state_15__1790; + wire plm_fsm_N_10493_i; + wire plm_fsm_reg_state_14__1791; + wire plm_fsm_N_10494_i; + wire plm_fsm_N_85497_i; + wire plm_fsm_N_10371_i; + wire plm_fsm_N_85478_i; + wire plm_fsm_reg_state_10__1792; + wire plm_fsm_reg_send_command_28_2_; + wire plm_fsm_N_3265_i; + wire plm_fsm_reg_send_command_28_0_; + wire plm_fsm_N_61244_i; + wire plm_fsm_N_61243_i; + wire plm_fsm_N_60884_i_1793; + wire plm_fsm_N_60679_i_1794; + wire plm_fsm_reg_state_9__1795; + wire plm_fsm_VCC_1796; + wire plm_fsm_reg_link_mode_1797; + wire plm_fsm_un1_reg_state_8_0_a2_1798; + wire plm_fsm_reg_noscramble_27; + wire plm_fsm_N_87223_i_1799; + wire plm_fsm_reg_rl_throw_a_bone_1800; + wire plm_fsm_reg_rx0_polarity_3; + wire plm_fsm_reg_rx1_polarity_3; + wire plm_fsm_reg_rx2_polarity_3; + wire plm_fsm_reg_fix_polarity_1801; + wire plm_fsm_reg_rx3_polarity_3; + wire plm_fsm_N_60883_i_1802; + wire plm_fsm_N_9912_i; + wire plm_fsm_N_85500_i_1803; + wire plm_fsm_N_15478_i; + wire plm_fsm_N_9435_i; + wire plm_fsm_N_47658_i; + wire plm_fsm_N_15218_i; + wire plm_fsm_N_56513_i_i_1804; + wire plm_fsm_N_10374_i; + wire plm_fsm_N_63400; + wire plm_fsm_N_21891_i; + wire plm_fsm_dq_timer_GND_1805; + wire plm_fsm_dq_timer_N_63726; + wire plm_fsm_dq_timer_N_63725; + wire plm_fsm_dq_timer_N_63724; + wire plm_fsm_dq_timer_N_63723; + wire plm_fsm_pa_timer_GND_1806; + wire plm_fsm_pa_timer_N_63727; + wire plm_fsm_pa_timer_N_63250; + wire plm_fsm_pa_counter0_VCC_1807; + wire plm_fsm_pa_counter0_un1_reg_rx_count_0_a2_5; + wire plm_fsm_pa_counter0_un1_reg_rx_count_0_a2_4; + wire plm_fsm_pa_counter0_un1_reg_tx_count_0_a2_8; + wire plm_fsm_pa_counter0_un1_reg_tx_count_0_a2_7; + wire plm_fsm_pa_counter0_un1_reg_tx_count_0_a2_6; + wire plm_fsm_pa_counter0_N_59124; + wire plm_fsm_pa_counter0_un1_enable_1_i_1808; + wire plm_fsm_pa_counter0_N_61004_i_1809; + wire plm_fsm_pa_counter0_un1_reg_rx_expired_1_i; + wire plm_fsm_pa_counter0_reg_expired_5; + wire plm_fsm_pa_counter0_N_60995_i; + wire plm_fsm_pa_counter0_reg_tx_expired_1810; + wire plm_fsm_pa_counter0_N_60994_i; + wire plm_fsm_pa_counter0_N_28855_i; + wire plm_fsm_pa_counter0_un1_enable_1; + wire plm_fsm_pa_counter1_VCC_1811; + wire plm_fsm_pa_counter1_N_59122; + wire plm_fsm_pa_counter1_un1_reg_rx_count_0_a2_5; + wire plm_fsm_pa_counter1_un1_reg_rx_count_0_a2_4; + wire plm_fsm_pa_counter1_un1_reg_tx_count_0_a2_8; + wire plm_fsm_pa_counter1_un1_reg_tx_count_0_a2_7; + wire plm_fsm_pa_counter1_un1_reg_tx_count_0_a2_6; + wire plm_fsm_pa_counter1_N_59121; + wire plm_fsm_pa_counter1_un1_enable_1_i_1812; + wire plm_fsm_pa_counter1_N_61005_i_1813; + wire plm_fsm_pa_counter1_un1_reg_rx_expired_1_i; + wire plm_fsm_pa_counter1_reg_expired_5; + wire plm_fsm_pa_counter1_N_60992_i; + wire plm_fsm_pa_counter1_reg_tx_expired_1814; + wire plm_fsm_pa_counter1_N_60991_i; + wire plm_fsm_pa_counter1_N_28853_i; + wire plm_fsm_pa_counter1_un1_enable_1; + wire plm_fsm_pa_counter2_VCC_1815; + wire plm_fsm_pa_counter2_N_59119; + wire plm_fsm_pa_counter2_un1_reg_rx_count_0_a2_5; + wire plm_fsm_pa_counter2_un1_reg_rx_count_0_a2_4; + wire plm_fsm_pa_counter2_un1_reg_tx_count_0_a2_8; + wire plm_fsm_pa_counter2_un1_reg_tx_count_0_a2_7; + wire plm_fsm_pa_counter2_un1_reg_tx_count_0_a2_6; + wire plm_fsm_pa_counter2_N_59118; + wire plm_fsm_pa_counter2_un1_enable_1_i_1816; + wire plm_fsm_pa_counter2_N_61006_i_1817; + wire plm_fsm_pa_counter2_un1_reg_rx_expired_1_i; + wire plm_fsm_pa_counter2_reg_expired_5; + wire plm_fsm_pa_counter2_N_60989_i; + wire plm_fsm_pa_counter2_reg_tx_expired_1818; + wire plm_fsm_pa_counter2_N_60988_i; + wire plm_fsm_pa_counter2_N_28851_i; + wire plm_fsm_pa_counter2_un1_enable_1; + wire plm_fsm_pa_counter3_VCC_1819; + wire plm_fsm_pa_counter3_N_59116; + wire plm_fsm_pa_counter3_un1_reg_rx_count_0_a2_5; + wire plm_fsm_pa_counter3_un1_reg_rx_count_0_a2_4; + wire plm_fsm_pa_counter3_un1_reg_tx_count_0_a2_8; + wire plm_fsm_pa_counter3_un1_reg_tx_count_0_a2_7; + wire plm_fsm_pa_counter3_un1_reg_tx_count_0_a2_6; + wire plm_fsm_pa_counter3_N_59115; + wire plm_fsm_pa_counter3_un1_enable_1_i_1820; + wire plm_fsm_pa_counter3_N_61007_i_1821; + wire plm_fsm_pa_counter3_un1_reg_rx_expired_1_i; + wire plm_fsm_pa_counter3_reg_expired_5; + wire plm_fsm_pa_counter3_N_60986_i; + wire plm_fsm_pa_counter3_reg_tx_expired_1822; + wire plm_fsm_pa_counter3_N_60985_i; + wire plm_fsm_pa_counter3_N_28849_i; + wire plm_fsm_pa_counter3_un1_enable_1; + wire plm_fsm_pc_timer_GND_1823; + wire plm_fsm_pc_timer_N_63721; + wire plm_fsm_pc_counter0_VCC_1824; + wire plm_fsm_pc_counter0_un1_reg_tx_count_0_a2_0_a3_5; + wire plm_fsm_pc_counter0_un1_reg_tx_count_0_a2_0_a3_4; + wire plm_fsm_pc_counter0_un1_reg_rx_count_0_a2_5; + wire plm_fsm_pc_counter0_un1_reg_rx_count_0_a2_4; + wire plm_fsm_pc_counter0_un1_enable_1_i_1825; + wire plm_fsm_pc_counter0_N_61023_i_1826; + wire plm_fsm_pc_counter0_un1_rx_ts1_i; + wire plm_fsm_pc_counter0_reg_expired_5; + wire plm_fsm_pc_counter0_reg_oneshot_1827; + wire plm_fsm_pc_counter0_N_61034_i; + wire plm_fsm_pc_counter0_un1_enable_2_i_1828; + wire plm_fsm_pc_counter0_reg_tx_expired_1829; + wire plm_fsm_pc_counter0_N_61035_i; + wire plm_fsm_pc_counter0_un1_enable_0_a2_0_a2_0_a3_0_a2_6; + wire plm_fsm_pc_counter0_N_87190_i_1830; + wire plm_fsm_pc_counter0_un1_reg_tx_count17; + wire plm_fsm_pc_counter0_un1_enable_1; + wire plm_fsm_pc_counter1_VCC_1831; + wire plm_fsm_pc_counter1_un1_reg_tx_count_0_a2_5; + wire plm_fsm_pc_counter1_un1_reg_tx_count_0_a2_4; + wire plm_fsm_pc_counter1_un1_reg_rx_count_0_a2_5; + wire plm_fsm_pc_counter1_un1_reg_rx_count_0_a2_4; + wire plm_fsm_pc_counter1_un1_enable_1_i_1832; + wire plm_fsm_pc_counter1_N_61024_i_1833; + wire plm_fsm_pc_counter1_un1_rx_ts1_i; + wire plm_fsm_pc_counter1_reg_expired_5; + wire plm_fsm_pc_counter1_reg_oneshot_1834; + wire plm_fsm_pc_counter1_N_61031_i; + wire plm_fsm_pc_counter1_un1_enable_2_i_1835; + wire plm_fsm_pc_counter1_reg_tx_expired_1836; + wire plm_fsm_pc_counter1_N_61033_i; + wire plm_fsm_pc_counter1_un1_enable_0_a2_0_a2_0_a3_0_a2_7; + wire plm_fsm_pc_counter1_N_87194_i_1837; + wire plm_fsm_pc_counter1_un1_reg_tx_count17; + wire plm_fsm_pc_counter1_un1_enable_1; + wire plm_fsm_pc_counter2_VCC_1838; + wire plm_fsm_pc_counter2_un1_reg_tx_count_0_a2_5; + wire plm_fsm_pc_counter2_un1_reg_tx_count_0_a2_4; + wire plm_fsm_pc_counter2_un1_reg_rx_count_0_a2_5; + wire plm_fsm_pc_counter2_un1_reg_rx_count_0_a2_4; + wire plm_fsm_pc_counter2_un1_enable_1_i_1839; + wire plm_fsm_pc_counter2_N_61025_i_1840; + wire plm_fsm_pc_counter2_un1_rx_ts1_i; + wire plm_fsm_pc_counter2_reg_expired_5; + wire plm_fsm_pc_counter2_reg_oneshot_1841; + wire plm_fsm_pc_counter2_N_61029_i; + wire plm_fsm_pc_counter2_un1_enable_2_i_1842; + wire plm_fsm_pc_counter2_reg_tx_expired_1843; + wire plm_fsm_pc_counter2_N_61039_i; + wire plm_fsm_pc_counter2_un1_enable_0_a3_0_a2_0_a3_0_a2; + wire plm_fsm_pc_counter2_N_87189_i_1844; + wire plm_fsm_pc_counter2_un1_reg_tx_count17; + wire plm_fsm_pc_counter2_un1_enable_1; + wire plm_fsm_pc_counter3_VCC_1845; + wire plm_fsm_pc_counter3_un1_reg_tx_count_0_a2_5; + wire plm_fsm_pc_counter3_un1_reg_tx_count_0_a2_4; + wire plm_fsm_pc_counter3_un1_reg_rx_count_0_a2_5; + wire plm_fsm_pc_counter3_un1_reg_rx_count_0_a2_4; + wire plm_fsm_pc_counter3_un1_enable_1_i_1846; + wire plm_fsm_pc_counter3_N_61026_i_1847; + wire plm_fsm_pc_counter3_un1_rx_ts1_i; + wire plm_fsm_pc_counter3_reg_expired_5; + wire plm_fsm_pc_counter3_reg_oneshot_1848; + wire plm_fsm_pc_counter3_N_61027_i; + wire plm_fsm_pc_counter3_un1_enable_2_i_1849; + wire plm_fsm_pc_counter3_reg_tx_expired_1850; + wire plm_fsm_pc_counter3_N_61028_i; + wire plm_fsm_pc_counter3_un1_enable_0_a2_0_a2_0_a3_0_a2_8; + wire plm_fsm_pc_counter3_N_87193_i_1851; + wire plm_fsm_pc_counter3_un1_reg_tx_count17; + wire plm_fsm_pc_counter3_un1_enable_1; + wire plm_fsm_cls_timer_GND_1852; + wire plm_fsm_cls_timer_N_63732; + wire plm_fsm_cls_timer_N_38051; + wire plm_fsm_cla_timer_GND_1853; + wire plm_fsm_cla_timer_N_63731; + wire plm_fsm_cla_timer_un1_expired_2ms_0_a2_0_a3_0_1854; + wire plm_fsm_cla_timer_N_63742; + wire plm_fsm_cla_timer_N_63740; + wire plm_fsm_cla_timer_N_63730; + wire plm_fsm_cla_timer_un1_reg_state_1_i_i_1855; + wire plm_fsm_clw_timer_GND_1856; + wire plm_fsm_clw_timer_N_63717; + wire plm_fsm_clw_timer_un1_expired_2ms_0_a2_0_a3_0_1857; + wire plm_fsm_clw_timer_N_63719; + wire plm_fsm_clw_timer_N_63718; + wire plm_fsm_clw_timer_N_63716; + wire plm_fsm_cc_timer_GND_1858; + wire plm_fsm_cc_timer_N_63744; + wire plm_fsm_cc_timer_N_63745; + wire plm_fsm_cc_timer_un1_expired_2ms_0_a2_0_a3_1_1859; + wire plm_fsm_cc_timer_un1_expired_2ms_0_a2_0_a3_0_1860; + wire plm_fsm_cc_timer_N_63743; + wire plm_fsm_cc_counter0_VCC_1861; + wire plm_fsm_cc_counter0_un1_reg_tx_count_0_a3_5; + wire plm_fsm_cc_counter0_un1_reg_tx_count_0_a3_4; + wire plm_fsm_cc_counter0_un1_reg_rx_count_0_a3_5; + wire plm_fsm_cc_counter0_un1_reg_rx_count_0_a3_4; + wire plm_fsm_cc_counter0_N_29090_i_i_1862; + wire plm_fsm_cc_counter0_N_87485_i_1863; + wire plm_fsm_cc_counter0_N_87489_i; + wire plm_fsm_cc_counter0_N_28777_i; + wire plm_fsm_cc_counter0_N_87221_i; + wire plm_fsm_cc_counter0_reg_oneshot_1864; + wire plm_fsm_cc_counter0_N_87211_i; + wire plm_fsm_cc_counter0_N_87204_i_1865; + wire plm_fsm_cc_counter0_reg_tx_expired_1866; + wire plm_fsm_cc_counter0_N_87210_i_1867; + wire plm_fsm_cc_counter0_N_56149_i; + wire plm_fsm_cc_counter0_N_29090_i; + wire plm_fsm_cc_counter1_VCC_1868; + wire plm_fsm_cc_counter1_un1_reg_tx_count_0_a2_0_a3_5; + wire plm_fsm_cc_counter1_un1_reg_tx_count_0_a2_0_a3_4; + wire plm_fsm_cc_counter1_un1_reg_rx_count_0_a3_5; + wire plm_fsm_cc_counter1_un1_reg_rx_count_0_a3_4; + wire plm_fsm_cc_counter1_N_29088_i_i_1869; + wire plm_fsm_cc_counter1_N_87484_i_1870; + wire plm_fsm_cc_counter1_N_87480_i; + wire plm_fsm_cc_counter1_N_28775_i; + wire plm_fsm_cc_counter1_N_87220_i; + wire plm_fsm_cc_counter1_reg_oneshot_1871; + wire plm_fsm_cc_counter1_N_87209_i; + wire plm_fsm_cc_counter1_N_87218_i_1872; + wire plm_fsm_cc_counter1_reg_tx_expired_1873; + wire plm_fsm_cc_counter1_N_87208_i_1874; + wire plm_fsm_cc_counter1_N_56152_i; + wire plm_fsm_cc_counter1_N_29088_i; + wire plm_fsm_cc_counter2_VCC_1875; + wire plm_fsm_cc_counter2_un1_reg_tx_count_0_a2_0_a3_5; + wire plm_fsm_cc_counter2_un1_reg_tx_count_0_a2_0_a3_4; + wire plm_fsm_cc_counter2_un1_reg_rx_count_0_a3_5; + wire plm_fsm_cc_counter2_un1_reg_rx_count_0_a3_4; + wire plm_fsm_cc_counter2_N_29086_i_i_1876; + wire plm_fsm_cc_counter2_N_87483_i_1877; + wire plm_fsm_cc_counter2_N_87481_i; + wire plm_fsm_cc_counter2_N_28773_i; + wire plm_fsm_cc_counter2_reg_oneshot_1878; + wire plm_fsm_cc_counter2_N_87555_i; + wire plm_fsm_cc_counter2_N_87212_i_1879; + wire plm_fsm_cc_counter2_reg_tx_expired_1880; + wire plm_fsm_cc_counter2_N_87219_i; + wire plm_fsm_cc_counter2_un1_enable_i_o2_0_0; + wire plm_fsm_cc_counter2_N_87207_i_1881; + wire plm_fsm_cc_counter2_N_56150_i; + wire plm_fsm_cc_counter2_N_29086_i; + wire plm_fsm_cc_counter3_VCC_1882; + wire plm_fsm_cc_counter3_un1_reg_tx_count_0_a2_0_a3_5; + wire plm_fsm_cc_counter3_un1_reg_tx_count_0_a2_0_a3_4; + wire plm_fsm_cc_counter3_un1_reg_rx_count_0_a3_5; + wire plm_fsm_cc_counter3_un1_reg_rx_count_0_a3_4; + wire plm_fsm_cc_counter3_N_29084_i_i_1883; + wire plm_fsm_cc_counter3_N_87482_i_1884; + wire plm_fsm_cc_counter3_N_87546_i; + wire plm_fsm_cc_counter3_N_28771_i; + wire plm_fsm_cc_counter3_N_28823_i_i; + wire plm_fsm_cc_counter3_reg_oneshot_1885; + wire plm_fsm_cc_counter3_N_87206_i; + wire plm_fsm_cc_counter3_N_87213_i_1886; + wire plm_fsm_cc_counter3_reg_tx_expired_1887; + wire plm_fsm_cc_counter3_N_87205_i_1888; + wire plm_fsm_cc_counter3_N_56151_i; + wire plm_fsm_cc_counter3_N_29084_i; + wire plm_fsm_ci_timer_GND_1889; + wire plm_fsm_ci_timer_N_63736; + wire plm_fsm_ci_timer_N_63737; + wire plm_fsm_ci_timer_un1_expired_2ms_1_1890; + wire plm_fsm_ci_timer_un1_expired_2ms_0_1891; + wire plm_fsm_ci_timer_N_63735; + wire plm_fsm_ci_counter0_VCC_1892; + wire plm_fsm_ci_counter0_un1_reg_tx_count_0_a2_5; + wire plm_fsm_ci_counter0_un1_reg_tx_count_0_a2_4; + wire plm_fsm_ci_counter0_un1_reg_rx_count_0_a2_5; + wire plm_fsm_ci_counter0_un1_reg_rx_count_0_a2_4; + wire plm_fsm_ci_counter0_N_61093_i_1893; + wire plm_fsm_ci_counter0_N_61102_i; + wire plm_fsm_ci_counter0_reg_expired_5; + wire plm_fsm_ci_counter0_N_61219_i; + wire plm_fsm_ci_counter0_reg_oneshot_1894; + wire plm_fsm_ci_counter0_N_61153_i; + wire plm_fsm_ci_counter0_N_61064_i_1895; + wire plm_fsm_ci_counter0_reg_tx_expired_1896; + wire plm_fsm_ci_counter0_N_61223_i_1897; + wire plm_fsm_ci_counter0_N_87181_i_1898; + wire plm_fsm_ci_counter0_reg_tx_count17_0_a2_0_a2_0_a3_0_a2_0; + wire plm_fsm_ci_counter0_un1_enable_1_0_a2_0_a2_0_a3_0_a2_5; + wire plm_fsm_ci_counter1_VCC_1899; + wire plm_fsm_ci_counter1_un1_reg_tx_count_0_a2_5; + wire plm_fsm_ci_counter1_un1_reg_tx_count_0_a2_4; + wire plm_fsm_ci_counter1_un1_reg_rx_count_0_a2_5; + wire plm_fsm_ci_counter1_un1_reg_rx_count_0_a2_4; + wire plm_fsm_ci_counter1_N_61094_i_1900; + wire plm_fsm_ci_counter1_N_61152_i; + wire plm_fsm_ci_counter1_reg_expired_5; + wire plm_fsm_ci_counter1_reg_oneshot_1901; + wire plm_fsm_ci_counter1_N_61151_i; + wire plm_fsm_ci_counter1_N_61063_i_1902; + wire plm_fsm_ci_counter1_reg_tx_expired_1903; + wire plm_fsm_ci_counter1_N_61221_i; + wire plm_fsm_ci_counter1_un1_enable_0_a2_0_a2_0_a3_0_a2_0; + wire plm_fsm_ci_counter1_N_61224_i_1904; + wire plm_fsm_ci_counter1_N_87180_i_1905; + wire plm_fsm_ci_counter1_reg_tx_count17_0_a2_0_a2_0_a3_0_a2_2; + wire plm_fsm_ci_counter1_un1_enable_1_0_a2_0_a2_0_a3_0_a2_4; + wire plm_fsm_ci_counter2_VCC_1906; + wire plm_fsm_ci_counter2_un1_reg_tx_count_0_a2_0_a3_5; + wire plm_fsm_ci_counter2_un1_reg_tx_count_0_a2_0_a3_4; + wire plm_fsm_ci_counter2_un1_reg_rx_count_0_a2_5; + wire plm_fsm_ci_counter2_un1_reg_rx_count_0_a2_4; + wire plm_fsm_ci_counter2_N_61095_i_1907; + wire plm_fsm_ci_counter2_N_61150_i; + wire plm_fsm_ci_counter2_reg_expired_5; + wire plm_fsm_ci_counter2_reg_oneshot_1908; + wire plm_fsm_ci_counter2_N_61149_i; + wire plm_fsm_ci_counter2_N_61106_i_1909; + wire plm_fsm_ci_counter2_reg_tx_expired_1910; + wire plm_fsm_ci_counter2_N_61217_i; + wire plm_fsm_ci_counter2_un1_enable_0_a2_0_a2_0_a3_0_a2_3; + wire plm_fsm_ci_counter2_N_61225_i_1911; + wire plm_fsm_ci_counter2_N_87179_i_1912; + wire plm_fsm_ci_counter2_reg_tx_count17_0_a2_0_a2_0_a2_0_a3_0_a2; + wire plm_fsm_ci_counter2_un1_enable_1_0_a2_0_a2_0_a3_0_a2_3; + wire plm_fsm_ci_counter3_VCC_1913; + wire plm_fsm_ci_counter3_un1_reg_tx_count_0_a2_0_a3_5; + wire plm_fsm_ci_counter3_un1_reg_tx_count_0_a2_0_a3_4; + wire plm_fsm_ci_counter3_un1_reg_rx_count_0_a2_5; + wire plm_fsm_ci_counter3_un1_reg_rx_count_0_a2_4; + wire plm_fsm_ci_counter3_N_61096_i_1914; + wire plm_fsm_ci_counter3_N_61148_i; + wire plm_fsm_ci_counter3_reg_expired_5; + wire plm_fsm_ci_counter3_reg_oneshot_1915; + wire plm_fsm_ci_counter3_N_61147_i; + wire plm_fsm_ci_counter3_N_61104_i_1916; + wire plm_fsm_ci_counter3_reg_tx_expired_1917; + wire plm_fsm_ci_counter3_N_61215_i; + wire plm_fsm_ci_counter3_un1_enable_0_a2_0_a2_0_a3_0_a2_5; + wire plm_fsm_ci_counter3_N_61226_i_1918; + wire plm_fsm_ci_counter3_N_87178_i_1919; + wire plm_fsm_ci_counter3_reg_tx_count17_0_a2_0_a2_0_a2_0_a3_0_a2_0; + wire plm_fsm_ci_counter3_un1_enable_1_0_a2_0_a2_0_a3_0_a2_2; + wire plm_fsm_rl_timer_GND_1920; + wire plm_fsm_rl_timer_N_63713; + wire plm_fsm_rl_timer_N_38053; + wire plm_fsm_rl_counterx_VCC_1921; + wire plm_fsm_rl_counterx_un1_reg_rx_count_0_a2_5; + wire plm_fsm_rl_counterx_un1_reg_rx_count_0_a2_4; + wire plm_fsm_rl_counterx_un1_reg_tx_count_0_a2_8; + wire plm_fsm_rl_counterx_un1_reg_tx_count_0_a2_7; + wire plm_fsm_rl_counterx_un1_reg_tx_count_0_a2_6; + wire plm_fsm_rl_counterx_N_61242_i_1922; + wire plm_fsm_rl_counterx_reg_expired_5; + wire plm_fsm_rl_counterx_N_61251_i; + wire plm_fsm_rl_counterx_reg_tx_expired_1923; + wire plm_fsm_rl_counterx_N_61250_i; + wire plm_fsm_rl_counterx_reg_rx_expired_1924; + wire plm_fsm_rl_counterx_N_61252_i; + wire plm_fsm_rl_counterx_un1_enable_1_i_1925; + wire plm_fsm_rl_counterx_un1_reg_rx_expired_0_a2_0_a2_0_a3_0_a2; + wire plm_fsm_rl_counterx_un1_enable_1; + wire plm_fsm_rl_counter0_VCC_1926; + wire plm_fsm_rl_counter0_un1_reg_rx_count_0_a2_5; + wire plm_fsm_rl_counter0_un1_reg_rx_count_0_a2_4; + wire plm_fsm_rl_counter0_N_59396; + wire plm_fsm_rl_counter0_N_59397; + wire plm_fsm_rl_counter0_N_59398; + wire plm_fsm_rl_counter0_un1_reg_rx_expired_1_i; + wire plm_fsm_rl_counter0_reg_expired_5; + wire plm_fsm_rl_counter0_N_61248_i; + wire plm_fsm_rl_counter0_N_36497_i; + wire plm_fsm_rl_counter1_VCC_1927; + wire plm_fsm_rl_counter1_un1_reg_rx_count_0_a2_5; + wire plm_fsm_rl_counter1_un1_reg_rx_count_0_a2_4; + wire plm_fsm_rl_counter1_N_59395; + wire plm_fsm_rl_counter1_N_59394; + wire plm_fsm_rl_counter1_un1_reg_rx_expired_1_i; + wire plm_fsm_rl_counter1_reg_expired_5; + wire plm_fsm_rl_counter1_N_61247_i; + wire plm_fsm_rl_counter1_N_36495_i; + wire plm_fsm_rl_counter2_VCC_1928; + wire plm_fsm_rl_counter2_un1_reg_rx_count_0_a2_5; + wire plm_fsm_rl_counter2_un1_reg_rx_count_0_a2_4; + wire plm_fsm_rl_counter2_N_58375; + wire plm_fsm_rl_counter2_N_58374; + wire plm_fsm_rl_counter2_un1_reg_rx_expired_1_i; + wire plm_fsm_rl_counter2_reg_expired_5; + wire plm_fsm_rl_counter2_N_61246_i; + wire plm_fsm_rl_counter2_N_11166_i; + wire plm_fsm_rl_counter3_VCC_1929; + wire plm_fsm_rl_counter3_un1_reg_rx_count_0_a2_5; + wire plm_fsm_rl_counter3_un1_reg_rx_count_0_a2_4; + wire plm_fsm_rl_counter3_N_58372; + wire plm_fsm_rl_counter3_N_58371; + wire plm_fsm_rl_counter3_N_61008_i; + wire plm_fsm_rl_counter3_reg_expired_5; + wire plm_fsm_rl_counter3_N_61245_i; + wire plm_fsm_rl_counter3_N_11159_i; + wire plm_fsm_rc_timer_GND_1930; + wire plm_fsm_rc_timer_expired_0_1931; + wire plm_fsm_rc_counter_ts1_0_VCC_1932; + wire plm_fsm_rc_counter_ts1_0_un1_reg_tx_count_0_a2_0_a3_5; + wire plm_fsm_rc_counter_ts1_0_un1_reg_tx_count_0_a2_0_a3_4; + wire plm_fsm_rc_counter_ts1_0_un1_reg_rx_count_0_a2_0_a3_5; + wire plm_fsm_rc_counter_ts1_0_un1_reg_rx_count_0_a2_0_a3_4; + wire plm_fsm_rc_counter_ts1_0_N_58806_1; + wire plm_fsm_rc_counter_ts1_0_N_60924_i_1933; + wire plm_fsm_rc_counter_ts1_0_N_60925_i_1934; + wire plm_fsm_rc_counter_ts1_0_N_60907_i; + wire plm_fsm_rc_counter_ts1_0_reg_expired_5_0_a2_i_i_a3_0_a2; + wire plm_fsm_rc_counter_ts1_0_N_60965_i; + wire plm_fsm_rc_counter_ts1_0_reg_oneshot_1935; + wire plm_fsm_rc_counter_ts1_0_N_60964_i; + wire plm_fsm_rc_counter_ts1_0_N_60949_i_1936; + wire plm_fsm_rc_counter_ts1_0_reg_tx_expired_1937; + wire plm_fsm_rc_counter_ts1_0_N_85508_i_1938; + wire plm_fsm_rc_counter_ts1_0_un1_enable_1_0_a2_i_o2_i_a3_0_a2_6; + wire plm_fsm_rc_counter_ts1_0_un1_enable_1_0_a2_i_i_a3_0_a2_1939; + wire plm_fsm_rc_counter_ts1_1_VCC_1940; + wire plm_fsm_rc_counter_ts1_1_un1_reg_tx_count_0_a2_0_a3_5; + wire plm_fsm_rc_counter_ts1_1_un1_reg_tx_count_0_a2_0_a3_4; + wire plm_fsm_rc_counter_ts1_1_un1_reg_rx_count_0_a2_0_a3_5; + wire plm_fsm_rc_counter_ts1_1_un1_reg_rx_count_0_a2_0_a3_4; + wire plm_fsm_rc_counter_ts1_1_N_59109_1; + wire plm_fsm_rc_counter_ts1_1_N_60923_i_1941; + wire plm_fsm_rc_counter_ts1_1_N_60926_i_1942; + wire plm_fsm_rc_counter_ts1_1_N_60909_i; + wire plm_fsm_rc_counter_ts1_1_reg_expired_5_0_a2_i_i_a3_0_a2_0; + wire plm_fsm_rc_counter_ts1_1_N_60963_i; + wire plm_fsm_rc_counter_ts1_1_reg_oneshot_1943; + wire plm_fsm_rc_counter_ts1_1_N_60962_i; + wire plm_fsm_rc_counter_ts1_1_N_60947_i_1944; + wire plm_fsm_rc_counter_ts1_1_reg_tx_expired_1945; + wire plm_fsm_rc_counter_ts1_1_N_85658_i_1946; + wire plm_fsm_rc_counter_ts1_1_un1_enable_1_0_a2_i_o2_i_a3_0_a2_5; + wire plm_fsm_rc_counter_ts1_1_un1_enable_1_0_a2_i_i_a3_0_a2_0; + wire plm_fsm_rc_counter_ts1_2_VCC_1947; + wire plm_fsm_rc_counter_ts1_2_un1_reg_tx_count_0_a2_0_a3_5; + wire plm_fsm_rc_counter_ts1_2_un1_reg_tx_count_0_a2_0_a3_4; + wire plm_fsm_rc_counter_ts1_2_un1_reg_rx_count_0_a2_0_a3_5; + wire plm_fsm_rc_counter_ts1_2_un1_reg_rx_count_0_a2_0_a3_4; + wire plm_fsm_rc_counter_ts1_2_N_59107_1; + wire plm_fsm_rc_counter_ts1_2_N_60922_i_1948; + wire plm_fsm_rc_counter_ts1_2_N_60927_i_1949; + wire plm_fsm_rc_counter_ts1_2_N_60914_i; + wire plm_fsm_rc_counter_ts1_2_reg_expired_5_0_a2_i_i_a3_0_a2_1; + wire plm_fsm_rc_counter_ts1_2_reg_oneshot_1950; + wire plm_fsm_rc_counter_ts1_2_N_60960_i; + wire plm_fsm_rc_counter_ts1_2_N_60945_i_1951; + wire plm_fsm_rc_counter_ts1_2_reg_tx_expired_1952; + wire plm_fsm_rc_counter_ts1_2_N_60961_i; + wire plm_fsm_rc_counter_ts1_2_un1_enable_0_a2_i_i_a3_0_a2; + wire plm_fsm_rc_counter_ts1_2_N_85532_i_1953; + wire plm_fsm_rc_counter_ts1_2_un1_enable_1_0_a2_i_o2_i_a3_0_a2_4; + wire plm_fsm_rc_counter_ts1_2_un1_enable_1_0_a2_i_i_a3_0_a2_1; + wire plm_fsm_rc_counter_ts1_3_VCC_1954; + wire plm_fsm_rc_counter_ts1_3_un1_reg_tx_count_0_a2_0_a3_5; + wire plm_fsm_rc_counter_ts1_3_un1_reg_tx_count_0_a2_0_a3_4; + wire plm_fsm_rc_counter_ts1_3_un1_reg_rx_count_0_a2_0_a3_5; + wire plm_fsm_rc_counter_ts1_3_un1_reg_rx_count_0_a2_0_a3_4; + wire plm_fsm_rc_counter_ts1_3_N_59105_1; + wire plm_fsm_rc_counter_ts1_3_N_60921_i_1955; + wire plm_fsm_rc_counter_ts1_3_N_60928_i_1956; + wire plm_fsm_rc_counter_ts1_3_N_60913_i; + wire plm_fsm_rc_counter_ts1_3_reg_expired_5_0_a2_i_i_a3_0_a2_2; + wire plm_fsm_rc_counter_ts1_3_N_60959_i; + wire plm_fsm_rc_counter_ts1_3_reg_oneshot_1957; + wire plm_fsm_rc_counter_ts1_3_N_60958_i; + wire plm_fsm_rc_counter_ts1_3_N_60943_i_1958; + wire plm_fsm_rc_counter_ts1_3_reg_tx_expired_1959; + wire plm_fsm_rc_counter_ts1_3_N_85659_i_1960; + wire plm_fsm_rc_counter_ts1_3_un1_enable_1_0_a2_i_o2_i_a3_0_a2_3; + wire plm_fsm_rc_counter_ts1_3_un1_enable_1_0_a2_i_i_a3_0_a2_2; + wire plm_fsm_rc_counter_ts2_0_VCC_1961; + wire plm_fsm_rc_counter_ts2_0_un1_reg_tx_count_0_a2_0_a3_5; + wire plm_fsm_rc_counter_ts2_0_un1_reg_tx_count_0_a2_0_a3_4; + wire plm_fsm_rc_counter_ts2_0_un1_reg_rx_count_0_a2_0_a3_5; + wire plm_fsm_rc_counter_ts2_0_un1_reg_rx_count_0_a2_0_a3_4; + wire plm_fsm_rc_counter_ts2_0_N_60920_i_1962; + wire plm_fsm_rc_counter_ts2_0_N_60929_i_1963; + wire plm_fsm_rc_counter_ts2_0_N_60906_i; + wire plm_fsm_rc_counter_ts2_0_reg_expired_5_0_a2_i_i_a3_0_a2_3; + wire plm_fsm_rc_counter_ts2_0_N_60957_i; + wire plm_fsm_rc_counter_ts2_0_reg_oneshot_1964; + wire plm_fsm_rc_counter_ts2_0_N_60956_i; + wire plm_fsm_rc_counter_ts2_0_N_60941_i_1965; + wire plm_fsm_rc_counter_ts2_0_reg_tx_expired_1966; + wire plm_fsm_rc_counter_ts2_0_N_87192_i_1967; + wire plm_fsm_rc_counter_ts2_0_un1_enable_1_0_a2_i_o2_i_a3_0_a2_2; + wire plm_fsm_rc_counter_ts2_0_un1_enable_1_0_a2_i_i_a3_0_a2_3; + wire plm_fsm_rc_counter_ts2_1_VCC_1968; + wire plm_fsm_rc_counter_ts2_1_un1_reg_tx_count_0_a2_0_a3_5; + wire plm_fsm_rc_counter_ts2_1_un1_reg_tx_count_0_a2_0_a3_4; + wire plm_fsm_rc_counter_ts2_1_un1_reg_rx_count_0_a2_0_a3_5; + wire plm_fsm_rc_counter_ts2_1_un1_reg_rx_count_0_a2_0_a3_4; + wire plm_fsm_rc_counter_ts2_1_N_60919_i_1969; + wire plm_fsm_rc_counter_ts2_1_N_60930_i_1970; + wire plm_fsm_rc_counter_ts2_1_N_60934_i; + wire plm_fsm_rc_counter_ts2_1_reg_expired_5_0_a2_i_i_a3_0_a2_4; + wire plm_fsm_rc_counter_ts2_1_N_60955_i; + wire plm_fsm_rc_counter_ts2_1_reg_oneshot_1971; + wire plm_fsm_rc_counter_ts2_1_N_60954_i; + wire plm_fsm_rc_counter_ts2_1_N_60939_i_1972; + wire plm_fsm_rc_counter_ts2_1_reg_tx_expired_1973; + wire plm_fsm_rc_counter_ts2_1_N_87191_i_1974; + wire plm_fsm_rc_counter_ts2_1_un1_enable_1_0_a2_i_o2_i_a3_0_a2_1; + wire plm_fsm_rc_counter_ts2_1_un1_enable_1_0_a2_i_i_a3_0_a2_4; + wire plm_fsm_rc_counter_ts2_2_VCC_1975; + wire plm_fsm_rc_counter_ts2_2_un1_reg_tx_count_0_a2_0_a3_5; + wire plm_fsm_rc_counter_ts2_2_un1_reg_tx_count_0_a2_0_a3_4; + wire plm_fsm_rc_counter_ts2_2_un1_reg_rx_count_0_a2_0_a3_5; + wire plm_fsm_rc_counter_ts2_2_un1_reg_rx_count_0_a2_0_a3_4; + wire plm_fsm_rc_counter_ts2_2_N_60917_i_1976; + wire plm_fsm_rc_counter_ts2_2_N_60931_i_1977; + wire plm_fsm_rc_counter_ts2_2_N_60933_i; + wire plm_fsm_rc_counter_ts2_2_reg_expired_5_0_a2_i_i_a3_0_a2_5; + wire plm_fsm_rc_counter_ts2_2_reg_oneshot_1978; + wire plm_fsm_rc_counter_ts2_2_N_60952_i; + wire plm_fsm_rc_counter_ts2_2_N_60918_i_1979; + wire plm_fsm_rc_counter_ts2_2_reg_tx_expired_1980; + wire plm_fsm_rc_counter_ts2_2_N_60953_i; + wire plm_fsm_rc_counter_ts2_2_un1_enable_0_a2_i_i_a3_0_a2_0; + wire plm_fsm_rc_counter_ts2_2_N_87234_i_1981; + wire plm_fsm_rc_counter_ts2_2_un1_enable_1_0_a2_i_o2_i_a3_0_a2_0; + wire plm_fsm_rc_counter_ts2_2_un1_enable_1_0_a2_i_i_a3_0_a2_5; + wire plm_fsm_rc_counter_ts2_3_VCC_1982; + wire plm_fsm_rc_counter_ts2_3_un1_reg_tx_count_0_a2_0_a3_5; + wire plm_fsm_rc_counter_ts2_3_un1_reg_tx_count_0_a2_0_a3_4; + wire plm_fsm_rc_counter_ts2_3_un1_reg_rx_count_0_a2_0_a3_5; + wire plm_fsm_rc_counter_ts2_3_un1_reg_rx_count_0_a2_0_a3_4; + wire plm_fsm_rc_counter_ts2_3_N_60916_i_1983; + wire plm_fsm_rc_counter_ts2_3_N_60932_i_1984; + wire plm_fsm_rc_counter_ts2_3_N_11106_i; + wire plm_fsm_rc_counter_ts2_3_reg_expired_5_0_a2_i_i_a3_0_a2_6; + wire plm_fsm_rc_counter_ts2_3_N_60951_i; + wire plm_fsm_rc_counter_ts2_3_reg_oneshot_1985; + wire plm_fsm_rc_counter_ts2_3_N_60950_i; + wire plm_fsm_rc_counter_ts2_3_N_60936_i_1986; + wire plm_fsm_rc_counter_ts2_3_reg_tx_expired_1987; + wire plm_fsm_rc_counter_ts2_3_N_87551_i_1988; + wire plm_fsm_rc_counter_ts2_3_un1_enable_1_0_a2_i_o2_i_a3_0_a2_1989; + wire plm_fsm_rc_counter_ts2_3_un1_enable_1_0_a2_i_i_a3_0_a2_6; + wire plm_fsm_ri_timer_GND_1990; + wire plm_fsm_ri_timer_N_63707; + wire plm_fsm_ri_timer_un1_expired_2ms_0_1991; + wire plm_fsm_ri_timer_N_63709; + wire plm_fsm_ri_timer_N_63708; + wire plm_fsm_ri_timer_N_63706; + wire plm_fsm_ri_counter0_VCC_1992; + wire plm_fsm_ri_counter0_un1_reg_tx_count_0_a3_5; + wire plm_fsm_ri_counter0_un1_reg_tx_count_0_a3_4; + wire plm_fsm_ri_counter0_un1_reg_rx_count_0_a2_5; + wire plm_fsm_ri_counter0_un1_reg_rx_count_0_a2_4; + wire plm_fsm_ri_counter0_N_61227_i_1993; + wire plm_fsm_ri_counter0_N_61097_i_1994; + wire plm_fsm_ri_counter0_N_61101_i; + wire plm_fsm_ri_counter0_reg_expired_5; + wire plm_fsm_ri_counter0_reg_oneshot_1995; + wire plm_fsm_ri_counter0_N_61146_i; + wire plm_fsm_ri_counter0_N_61055_i_1996; + wire plm_fsm_ri_counter0_reg_tx_expired_1997; + wire plm_fsm_ri_counter0_N_61222_i; + wire plm_fsm_ri_counter0_un1_enable_0_a2_0_a2_0_a3_0_a2; + wire plm_fsm_ri_counter0_N_87177_i_1998; + wire plm_fsm_ri_counter0_reg_tx_count17_0_a2_0_a2_0_a3_0_a2_3; + wire plm_fsm_ri_counter0_un1_enable_1_0_a2_0_a2_0_a3_0_a2_1; + wire plm_fsm_ri_counter1_VCC_1999; + wire plm_fsm_ri_counter1_un1_reg_tx_count_0_a2_5; + wire plm_fsm_ri_counter1_un1_reg_tx_count_0_a2_4; + wire plm_fsm_ri_counter1_un1_reg_rx_count_0_a2_5; + wire plm_fsm_ri_counter1_un1_reg_rx_count_0_a2_4; + wire plm_fsm_ri_counter1_N_61228_i_2000; + wire plm_fsm_ri_counter1_N_61098_i_2001; + wire plm_fsm_ri_counter1_N_61145_i; + wire plm_fsm_ri_counter1_reg_expired_5; + wire plm_fsm_ri_counter1_reg_oneshot_2002; + wire plm_fsm_ri_counter1_N_61144_i; + wire plm_fsm_ri_counter1_N_61062_i_2003; + wire plm_fsm_ri_counter1_reg_tx_expired_2004; + wire plm_fsm_ri_counter1_N_61220_i; + wire plm_fsm_ri_counter1_un1_enable_0_a2_0_a2_0_a3_0_a2_1; + wire plm_fsm_ri_counter1_N_87176_i_2005; + wire plm_fsm_ri_counter1_reg_tx_count17_0_a2_0_a2_0_a3_0_a2; + wire plm_fsm_ri_counter1_un1_enable_1_0_a2_0_a2_0_a3_0_a2_0; + wire plm_fsm_ri_counter2_VCC_2006; + wire plm_fsm_ri_counter2_un1_reg_tx_count_0_a2_0_a3_5; + wire plm_fsm_ri_counter2_un1_reg_tx_count_0_a2_0_a3_4; + wire plm_fsm_ri_counter2_un1_reg_rx_count_0_a2_5; + wire plm_fsm_ri_counter2_un1_reg_rx_count_0_a2_4; + wire plm_fsm_ri_counter2_N_61229_i_2007; + wire plm_fsm_ri_counter2_N_61099_i_2008; + wire plm_fsm_ri_counter2_N_61143_i; + wire plm_fsm_ri_counter2_reg_expired_5; + wire plm_fsm_ri_counter2_reg_oneshot_2009; + wire plm_fsm_ri_counter2_N_61142_i; + wire plm_fsm_ri_counter2_N_61060_i_2010; + wire plm_fsm_ri_counter2_reg_tx_expired_2011; + wire plm_fsm_ri_counter2_N_61216_i; + wire plm_fsm_ri_counter2_un1_enable_0_a2_0_a2_0_a3_0_a2_4; + wire plm_fsm_ri_counter2_N_87175_i_2012; + wire plm_fsm_ri_counter2_reg_tx_count17_0_a2_0_a2_0_a3_0_a2_1; + wire plm_fsm_ri_counter2_un1_enable_1_0_a2_0_a2_0_a3_0_a2_2013; + wire plm_fsm_ri_counter3_VCC_2014; + wire plm_fsm_ri_counter3_un1_reg_tx_count_0_a2_0_a3_5; + wire plm_fsm_ri_counter3_un1_reg_tx_count_0_a2_0_a3_4; + wire plm_fsm_ri_counter3_un1_reg_rx_count_0_a2_5; + wire plm_fsm_ri_counter3_un1_reg_rx_count_0_a2_4; + wire plm_fsm_ri_counter3_N_61230_i_2015; + wire plm_fsm_ri_counter3_N_61100_i_2016; + wire plm_fsm_ri_counter3_N_61141_i; + wire plm_fsm_ri_counter3_reg_expired_5; + wire plm_fsm_ri_counter3_reg_oneshot_2017; + wire plm_fsm_ri_counter3_N_61140_i; + wire plm_fsm_ri_counter3_N_61058_i_2018; + wire plm_fsm_ri_counter3_reg_tx_expired_2019; + wire plm_fsm_ri_counter3_N_61218_i; + wire plm_fsm_ri_counter3_un1_enable_0_a2_0_a2_0_a3_0_a2_2; + wire plm_fsm_ri_counter3_N_87174_i_2020; + wire plm_fsm_ri_counter3_reg_tx_count17_0_a3_0_a2_0_a2_0_a3_0_a2; + wire plm_fsm_ri_counter3_un1_enable_1_0_a2_0_a2_0_a2_0_a3_0_a2_2021; + wire plm_fsm_hr_timer_GND_2022; + wire plm_fsm_hr_timer_N_63702; + wire plm_fsm_hr_timer_N_63703; + wire plm_fsm_hr_timer_un1_expired_2ms_1_2023; + wire plm_fsm_hr_timer_un1_expired_2ms_0_2024; + wire plm_fsm_hr_timer_N_63701; + wire plm_fsm_xl_cls_timer_GND_2025; + wire plm_fsm_xl_cls_timer_N_63690; + wire plm_fsm_xl_cls_timer_N_63689; + wire plm_fsm_xl_cls_timer_N_63688; + wire plm_fsm_xl_cla_timer_GND_2026; + wire plm_fsm_xl_cla_timer_N_63692; + wire plm_fsm_xl_cla_timer_un1_expired_2ms_0_a2_0_2027; + wire plm_fsm_xl_cla_timer_N_63694; + wire plm_fsm_xl_cla_timer_N_63693; + wire plm_fsm_xl_cla_timer_N_63691; + wire plm_fsm_xl_cla_timer_un1_reg_state_5_i_i_2028; + wire plm_fsm_xl_clw_timer_GND_2029; + wire plm_fsm_xl_clw_timer_N_63697; + wire plm_fsm_xl_clw_timer_un1_expired_2ms_0_a2_0_a3_0_2030; + wire plm_fsm_xl_clw_timer_N_63699; + wire plm_fsm_xl_clw_timer_N_63698; + wire plm_fsm_xl_clw_timer_N_63696; + wire com_cmmt_ppm_suspend_ok; + wire com_cmmt_aspm_suspend_req; + wire com_N_86529_i; + wire com_N_43005_i_i; + wire com_N_43005_i; + wire com_N_55880_i; + wire com_cmmt_tdst_rdy; + wire com_cmmt_trem_n_0_sqmuxa; + wire com_cmmt_ppm_suspend_req_n; + wire com_N_63654; + wire com_N_63653; + wire com_N_63652; + wire com_N_63651; + wire com_N_63650; + wire com_N_63659; + wire com_N_63658; + wire com_N_63657; + wire com_N_63656; + wire com_N_63655; + wire com_N_63660; + wire com_N_63644; + wire com_N_63643; + wire com_N_63642; + wire com_N_63641; + wire com_N_63640; + wire com_N_63649; + wire com_N_63648; + wire com_N_63647; + wire com_N_63646; + wire com_N_63645; + wire com_N_63630; + wire com_N_63639; + wire com_N_63638; + wire com_N_63637; + wire com_N_63636; + wire com_N_63635; + wire com_N_63661; + wire com_N_63634; + wire com_N_63633; + wire com_N_63632; + wire com_N_63631; + wire com_N_63664; + wire com_N_63663; + wire com_N_63662; + wire com_N_58286; + wire com_N_56344_i; + wire com_N_55871_i; + wire com_cmmt_stat_tlp_tx_wr_ep; + wire com_cmmt_ppm_suspend_req_n_i; + wire com_cmmt_err_tlp_p_cpl; + wire com_cmmt_err_tlp_ur; + wire com_cmmt_stat_tlp_rx_cpl_abort; + wire com_cmmt_stat_tlp_rx_cpl_ep; + wire com_cmmt_stat_tlp_rx_cpl_ur; + wire com_cmmt_stat_tlp_rx_ep; + wire com_cmmt_rpm_turn_off; + wire com_cmmt_rpm_set_slot_pwr; + wire com_cmmt_rpm_as_nak_l1; + wire com_cmmt_mem32; + wire com_cmmt_mem64; + wire com_cmmt_rio; + wire com_cmmt_rdst_rdy_n; + wire com_cmmt_rsrc_rdy; + wire com_TLP_data_reg_29_; + wire com_TLP_data_reg_30_; + wire com_TLP_data_reg_0_; + wire com_TLP_data_reg_25_; + wire com_TLP_data_reg_27_; + wire com_TLP_data_reg_50_; + wire com_TLP_data_reg_49_; + wire com_TLP_data_reg_48_; + wire com_TLP_data_reg_46_; + wire com_TLP_data_reg_44_; + wire com_TLP_data_reg_8_; + wire com_TLP_data_reg_7_; + wire com_TLP_data_reg_6_; + wire com_TLP_data_reg_5_; + wire com_TLP_data_reg_4_; + wire com_TLP_data_reg_3_; + wire com_TLP_data_reg_2_; + wire com_TLP_data_reg_1_; + wire com_TLP_data_reg_23_; + wire com_TLP_data_reg_19_; + wire com_TLP_data_reg_18_; + wire com_TLP_data_reg_17_; + wire com_TLP_data_reg_16_; + wire com_TLP_data_reg_15_; + wire com_TLP_data_reg_14_; + wire com_TLP_data_reg_11_; + wire com_TLP_data_reg_10_; + wire com_TLP_data_reg_9_; + wire com_TLP_data_reg_31_; + wire com_tlp_data_29_; + wire com_tlp_data_0_; + wire com_tlp_data_27_; + wire com_cmml_suspend_now_n_i; + wire com_lnk_tfc_sent_n; + wire com_N_63252_i; + wire com_lnk_tfc_dst_rdy_n; + wire com_un1_lnk_tfc_dst_rdy_i_0_o2_i_a2; + wire com_lnk_tdst_rdy_n; + wire com_lnk_tdst_rdy_n_i; + wire com_lnk_teof; + wire com_lnk_tsof; + wire com_lnk_teof_i; + wire com_lnk_tsof_i; + wire com_reset_i_q; + wire com_cmml_suspend_ok; + wire com_cmml_suspend_now_n; + wire com_lnk_rsrc_rdy_n; + wire com_lnk_rsrc_rdy_n_i; + wire com_lnk_rsof_n; + wire com_lnk_rsof_n_i; + wire com_lnk_rsrc_dsc_n; + wire com_rx_tlp_range_err_n; + wire com_rx_tlp_tsn_err_crc_or_ferr; + wire com_lnk_reof_n; + wire com_N_56127_i; + wire com_cmml_rpm_ra; + wire com_cmml_bad_dllp_err_n; + wire com_lnk_tretry; + wire com_reg_tx_update_ack; + wire com_replay_timer_expire_pre; + wire com_replay_timer_expire; + wire com_replay_vld; + wire com_lnk_tfc_vc_hit; + wire com_N_56233_i; + wire com_N_56202_i; + wire com_N_56034_i; + wire com_N_56034_i_i; + wire com_N_3206_i_i; + wire com_reg_tx_update_retry_int; + wire com_reg_tx_update_retry_q; + wire com_st_pm_13_; + wire com_st_pm_17_; + wire com_st_pm_27_; + wire com_llm_rx_dllp_vld; + wire com_llm_reg_rx_dllp_nak_vld; + wire com_llm_reg_rx_dllp_ack_vld; + wire com_llm_ANSeqNum_Eq_AckdSeq_5_0_a2_0_a2_0_a3_0_a2_1_0_0; + wire com_llm_link_update_fc_rcv; + wire com_llm_link_li2_rcv; + wire com_llm_link_li1_cpl_rcv; + wire com_llm_link_li1_np_rcv; + wire com_llm_link_li1_p_rcv; + wire com_llm_N_56326_i; + wire com_llm_rx_reof_n; + wire com_llm_rx_rsrc_dsc_n; + wire com_llm_rx_rsrc_rdy_n; + wire com_llm_reg_dllr_in_progress; + wire com_llm_N_62468; + wire com_llm_N_56500_i; + wire com_llm_N_63255_i; + wire com_llm_reg_rx_tlp_tsn_err_0_a2_0_a2_0_a2_0_a2; + wire com_llm_trn_lnk_up_n_i; + wire com_llm_reg_rx_tlp_tsn_dup; + wire com_llm_reg_tx_dllp_dup_vld; + wire com_llm_reg_tx_dllp_ack_vld; + wire com_llm_reg_tx_dllp_nak_vld; + wire com_llm_N_56478_i; + wire com_llm_rx_dllp_range_err_n; + wire com_llm_llm_tx_top_tx_dllp_vld_n; + wire com_llm_llm_tx_top_un1_link_status_1_i_0_0_a3; + wire com_llm_llm_tx_top_tx_dllp_accepted; + wire com_llm_llm_tx_top_tx_dllp_tx_next; + wire com_llm_llm_tx_top_tx_dllp_tx_next_pre; + wire com_llm_llm_tx_top_tx_tlp_sof_pre_n; + wire com_llm_llm_tx_top_tx_tlp_vld_l_n_i; + wire com_llm_llm_tx_top_tx_tlp_sof_n; + wire com_llm_llm_tx_top_N_59251_1; + wire com_llm_llm_tx_top_tx_tlp_eof_n; + wire com_llm_llm_tx_top_N_56164_i; + wire com_llm_llm_tx_top_N_51188_i; + wire com_llm_llm_tx_top_reg_tx_tkomp_idle; + wire com_llm_llm_tx_top_reg_tx_pp_idle; + wire com_llm_llm_tx_top_reg_tx_djefe_idle; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_bat_sof_n_2031; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_bat_eof_n_2032; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_un1_tx_pipe_full_0_a2_0_a2_0_a2_2033; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_N_57527_i_2034; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_N_57527_1; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_N_16899_i; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_N_86845_i_2035; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_holy_stashed_data_2036; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_bat_rem_2037; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_sof_n_mux_i_i_2038; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_sof_n_mux_i; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_N_85587_i_2039; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_N_30495_i; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_N_61377; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_N_61392; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_GND_2040; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_VCC_2041; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_N_55885_i; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_62_N_6; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_220_; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_61_N_6; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_219_; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_60_N_6; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_218_; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_59_N_6; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_217_; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_58_N_6; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_216_; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_57_N_6; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_235_; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_56_N_6; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_234_; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_55_N_6; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_233_; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_54_N_6; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_232_; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_53_N_6; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_231_; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_52_N_6; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_230_; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_51_N_6; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_229_; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_50_N_6; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_228_; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_49_N_6; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_227_; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_48_N_6; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_226_; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_47_N_6; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_225_; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_46_N_6; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_224_; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_45_N_6; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_223_; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_44_N_6; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_222_; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_43_N_6; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_221_; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_42_N_6; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_250_; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_41_N_6; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_249_; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_40_N_6; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_248_; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_39_N_6; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_247_; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_38_N_6; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_246_; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_37_N_6; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_245_; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_36_N_6; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_244_; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_35_N_6; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_243_; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_34_N_6; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_242_; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_33_N_6; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_241_; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_32_N_6; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_240_; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_31_N_6; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_239_; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_30_N_6; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_238_; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_29_N_6; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_237_; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_28_N_6; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_236_; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_27_N_6; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_265_; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_26_N_6; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_264_; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_25_N_6; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_263_; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_24_N_6; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_262_; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_23_N_6; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_261_; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_22_N_6; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_260_; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_21_N_6; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_259_; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_20_N_6; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_258_; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_19_N_6; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_257_; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_18_N_6; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_256_; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_17_N_6; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_255_; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_16_N_6; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_254_; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_15_N_6; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_253_; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_14_N_6; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_252_; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_13_N_6; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_251_; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_12_N_6; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_279_; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_11_N_6; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_278_; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_10_N_6; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_277_; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_9_N_6; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_276_; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_8_N_6; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_275_; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_7_N_6; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_274_; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_6_N_6; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_273_; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_272_; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_4_N_6; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_271_; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_3_N_6; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_270_; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_2_N_6; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_269_; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_1_N_6; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_268_; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_0_N_6; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_267_; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_N_6; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_266_; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_tsn_pipe_10_N_6; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_tsn_pipe_47_; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_tsn_pipe_9_N_6; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_tsn_pipe_46_; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_tsn_pipe_8_N_6; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_tsn_pipe_45_; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_tsn_pipe_7_N_6; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_tsn_pipe_44_; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_tsn_pipe_6_N_6; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_tsn_pipe_43_; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_tsn_pipe_5_N_6; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_tsn_pipe_42_; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_tsn_pipe_4_N_6; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_tsn_pipe_41_; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_tsn_pipe_3_N_6; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_tsn_pipe_40_; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_tsn_pipe_2_N_6; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_tsn_pipe_39_; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_tsn_pipe_1_N_6; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_tsn_pipe_38_; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_tsn_pipe_0_N_6; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_tsn_pipe_37_; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_tsn_pipe_N_6; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_tsn_pipe_36_; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_eof_n_pipe_N_6; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_6__2042; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_5__2043; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_4__2044; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_3__2045; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_2__2046; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_1__2047; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_0__2048; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_15__2049; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_14__2050; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_13__2051; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_12__2052; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_11__2053; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_10__2054; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_9__2055; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_8__2056; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_7__2057; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_bat_td3; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_tsn_pipe_11__2058; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_tsn_pipe_10__2059; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_tsn_pipe_9__2060; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_tsn_pipe_8__2061; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_tsn_pipe_7__2062; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_tsn_pipe_6__2063; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_tsn_pipe_5__2064; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_tsn_pipe_4__2065; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_tsn_pipe_3__2066; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_tsn_pipe_2__2067; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_tsn_pipe_1__2068; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_tsn_pipe_0__2069; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_N_25962_i; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_N_25960_i; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_N_25958_i; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_N_25956_i; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_N_25954_i; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_N_25952_i; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_N_51730_i; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_N_25950_i; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_N_25948_i; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_N_51728_i; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_N_51726_i; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_N_51724_i; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_N_25946_i; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_N_25944_i; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_N_25942_i; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_N_25940_i; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_N_25938_i; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_N_25936_i; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_N_25934_i; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_N_25932_i; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_N_25930_i; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_N_25928_i; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_N_25926_i; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_N_25924_i; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_N_86895_i_2070; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_N_86894_i_2071; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_N_86893_i_2072; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_N_86892_i_2073; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_N_86891_i_2074; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_N_86890_i_2075; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_N_86889_i_2076; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_N_86888_i_2077; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_N_86887_i_2078; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_N_86886_i_2079; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_N_86885_i_2080; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_N_86884_i_2081; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_N_86883_i_2082; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_N_86882_i_2083; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_N_86881_i_2084; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_N_86880_i_2085; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_N_86879_i_2086; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_N_86878_i_2087; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_N_86877_i_2088; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_N_86876_i_2089; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_N_86875_i_2090; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_N_86874_i_2091; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_N_86873_i_2092; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_N_86872_i_2093; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_N_86871_i_2094; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_N_86870_i_2095; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_N_86869_i_2096; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_N_86868_i_2097; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_N_86867_i_2098; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_N_86866_i_2099; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_N_86865_i_2100; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_N_86864_i_2101; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_N_86863_i_2102; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_N_86862_i_2103; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_N_86861_i_2104; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_N_86860_i_2105; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_N_86859_i_2106; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_N_86858_i_2107; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_N_86857_i_2108; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_N_86856_i_2109; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mgt_tx_crcint; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_new_c48_1_1_1_; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_bm_1__2110; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_am_1__2111; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_new_c48_1_1_6_; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_bm_6__2112; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_am_6__2113; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_new_c48_1_1_10_; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_bm_10__2114; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_am_12__2115; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_am_13__2116; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_new_c16_1_1_14_; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_new_c48_1_2_14_; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_new_c48_1_0_14_; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_bm_14__2117; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_am_14__2118; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_new_c48_1_3_15_; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_new_c48_1_1_15_; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_bm_15__2119; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_am_15__2120; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_new_c16_1_1_16_; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_new_c48_1_2_16_; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_new_c48_1_1_16_; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_bm_16__2121; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_am_16__2122; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_new_c48_1_2_17_; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_bm_17__2123; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_am_17__2124; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_new_c48_1_1_18_; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_bm_18__2125; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_am_18__2126; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_new_c48_1_1_19_; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_bm_19__2127; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_am_19__2128; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_new_c48_1_2_20_; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_bm_20__2129; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_am_20__2130; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_new_c48_1_0_21_; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_bm_21__2131; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_am_21__2132; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_new_c48_1_2_27_; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_bm_27__2133; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_am_27__2134; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_new_c48_1_2_28_; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_bm_28__2135; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_am_28__2136; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_new_c48_1_2_0_; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_bm_0__2137; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_am_0__2138; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_new_c48_1_1_2_; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_bm_2__2139; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_am_2__2140; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_new_c48_1_1_3_; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_bm_3__2141; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_new_c16_1_1_4_; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_new_c48_1_1_4_; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_bm_4__2142; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_am_4__2143; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_new_c32_d16_1_5_; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_new_c48_1_1_5_; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_bm_5__2144; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_am_5__2145; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_new_c48_1_3_7_; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_new_c48_1_1_7_; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_bm_7__2146; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_am_7__2147; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_new_c16_1_1_8_; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_am_8__2148; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_new_c48_1_0_9_; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_bm_9__2149; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_am_9__2150; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_new_c48_1_1_11_; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_bm_11__2151; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_am_11__2152; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_new_c48_1_3_22_; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_bm_22__2153; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_am_22__2154; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_new_c16_1_1_23_; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_new_c48_1_1_23_; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_bm_23__2155; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_am_23__2156; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_am_24__2157; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_new_c48_1_2_25_; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_bm_25__2158; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_new_c16_1_1_26_; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_new_c48_1_1_26_; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_bm_26__2159; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_am_26__2160; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_new_c16_1_1_29_; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_new_c48_1_2_29_; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_bm_29__2161; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_am_29__2162; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_new_c16_1_1_31_; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_new_c48_1_1_31_; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_bm_31__2163; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_am_31__2164; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_am_25__2165; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_new_c32_d16_1_25_; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_am_3__2166; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_new_c32_d16_1_3_; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_am_10__2167; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_new_c16_1_1_30_; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_26520_i_2168; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_26521_i_2169; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_26522_i_2170; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_26523_i_2171; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_26524_i_2172; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_26525_i_2173; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_26526_i_2174; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_26527_i_2175; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_26528_i_2176; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_26529_i_2177; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_26530_i_2178; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_26531_i_2179; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_26532_i_2180; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_26552_i_2181; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_26553_i_2182; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_26554_i_2183; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_26555_i_2184; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_26556_i_2185; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_26557_i_2186; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_26558_i_2187; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_26559_i_2188; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_26560_i_2189; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_26561_i_2190; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_26562_i_2191; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_26563_i_2192; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_26564_i_2193; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_26533_i_2194; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_26534_i_2195; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_26535_i_2196; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_26536_i_2197; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_26537_i_2198; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_26538_i_2199; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crcint_qq_2200; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_56044_i; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_58222; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_56429; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_58220; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_56430; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_58218; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_56431; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_58216; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_56432; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_i_0_43__2201; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_i_0_42__2202; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_i_0_41__2203; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_i_0_40__2204; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_58206; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_56433; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_58204; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_56434; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_58202; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_56435; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_58200; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_56436; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_58198; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_56437; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_58196; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_56438; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_58194; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_56439; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_58192; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_56440; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_58776; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_58778; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_58774; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_58189; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_58187; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_58185; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_58183; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_58181; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_58179; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_58177; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_58175; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_58173; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_58171; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_58169; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_58167; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_61310; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_58165; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_58164; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_i_0_15__2205; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_i_0_14__2206; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_i_0_13__2207; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_i_0_12__2208; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_i_0_11__2209; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_i_0_10__2210; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_i_0_9__2211; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_i_0_8__2212; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_i_0_7__2213; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_i_0_6__2214; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_i_0_5__2215; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_i_0_4__2216; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_i_0_3__2217; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_i_0_2__2218; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_i_0_1__2219; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_i_0_0__2220; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_55887_i; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_bm_24__2221; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_bm_1_24__2222; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_bm_8__2223; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_bm_1_8__2224; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_bm_13__2225; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_bm_1_13__2226; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_new_c48_1_2_13_; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_bm_12__2227; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_bm_1_12__2228; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_d64_c_q_31__2229; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_d64_c_q_30__2230; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_d64_c_q_29__2231; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_d64_c_q_28__2232; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_d64_c_q_27__2233; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_d64_c_q_26__2234; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_d64_c_q_25__2235; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_d64_c_q_24__2236; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_d64_c_q_23__2237; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_d64_c_q_22__2238; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_d64_c_q_21__2239; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_d64_c_q_20__2240; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_d64_c_q_19__2241; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_d64_c_q_18__2242; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_d64_c_q_17__2243; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_d64_c_q_16__2244; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_d64_c_q_15__2245; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_d64_c_q_14__2246; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_d64_c_q_13__2247; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_d64_c_q_12__2248; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_d64_c_q_11__2249; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_d64_c_q_10__2250; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_d64_c_q_9__2251; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_d64_c_q_8__2252; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_d64_c_q_7__2253; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_d64_c_q_6__2254; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_d64_c_q_4__2255; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_d64_c_q_3__2256; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_d64_c_q_1__2257; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_d64_c_q_0__2258; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_i_m3_0_63__2259; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_i_m3_0_62__2260; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_i_m3_0_61__2261; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_i_m3_0_60__2262; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_51318_i; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_51316_i; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_51314_i; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_51312_i; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_i_m3_0_55__2263; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_i_m3_0_54__2264; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_i_m3_0_53__2265; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_i_m3_0_52__2266; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_i_m3_0_51__2267; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_i_m3_0_50__2268; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_i_m3_0_49__2269; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_i_m3_0_48__2270; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_51820_i; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_51818_i; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_51816_i; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_51814_i; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_51812_i; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_51810_i; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_51808_i; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_51806_i; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_51804_i; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_51802_i; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_51800_i; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_51798_i; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_51796_i; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_51794_i; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_51792_i; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_51790_i; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_52366_i; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_52368_i; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_52364_i; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_51788_i; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_51786_i; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_51784_i; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_51782_i; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_51780_i; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_51778_i; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_51776_i; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_51774_i; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_51772_i; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_51770_i; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_51768_i; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_51766_i; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_51764_i; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_51762_i; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_51760_i; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_51758_i; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_51756_i; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_51754_i; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_51752_i; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_51750_i; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_51748_i; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_51746_i; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_51744_i; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_51742_i; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_51740_i; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_51738_i; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_51736_i; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_51734_i; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_51732_i; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_0_24__2271; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_0_20__2272; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_5_25__2273; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_3_25__2274; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_2_10__2275; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_2_2__2276; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_23__2277; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_1_6__2278; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_2_15__2279; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_2_14__2280; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_2_29__2281; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_2_30__2282; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_1_9__2283; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_0_13__2284; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_2_11__2285; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_2_26__2286; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_4_31__2287; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_1_31__2288; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_5_30__2289; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_3_29__2290; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_3_28__2291; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_4_27__2292; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_3_27__2293; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_26__2294; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_3_24__2295; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_24__2296; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_3_23__2297; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_1__2298; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_4_22__2299; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_2_22__2300; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_3_21__2301; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_4_20__2302; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_18__2303; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_2_19__2304; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_4_18__2305; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_2_18__2306; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_4_17__2307; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_2_17__2308; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_2_16__2309; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_16__2310; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_5_15__2311; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_5_14__2312; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_3_13__2313; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_13__2314; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_1_12__2315; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_17__2316; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_6_11__2317; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_4_11__2318; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_6_10__2319; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_4_9__2320; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_3_9__2321; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_3_8__2322; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_2_8__2323; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_5_7__2324; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_4_7__2325; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_20__2326; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_5_6__2327; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_4_5__2328; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_4_4__2329; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_3_4__2330; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_6_3__2331; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_1_3__2332; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_6_2__2333; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_2__2334; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_4_1__2335; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_3_1__2336; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_4_0__2337; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_3_0__2338; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_2_0__2339; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_2_27__2340; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c48_new_c48_1_1_25__2341; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c48_new_c48_1_1_29__2342; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c48_new_c48_1_1_0__2343; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c48_new_c48_1_1_30__2344; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c64_new_c64_1_0_25__2345; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c64_new_c32_d64_1_4_; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c64_new_c64_1_0_16__2346; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c64_new_c64_1_1_17__2347; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c64_new_c64_1_2_19__2348; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c64_new_c64_1_1_20__2349; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c64_new_c64_1_1_21__2350; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c64_new_c64_1_1_31__2351; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c64_new_c64_1_1_29__2352; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c64_new_c64_1_1_2__2353; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c64_new_c32_d64_1_2_; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c64_new_c64_1_1_18__2354; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c64_new_c64_1_2_0__2355; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c64_new_c64_1_2_1__2356; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c64_new_c64_1_2_3__2357; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c64_new_c64_1_2_4__2358; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c64_new_c64_1_2_5__2359; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c64_new_c64_1_1_6__2360; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c64_new_c64_1_2_7__2361; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c64_new_c32_d64_1_7_; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c64_new_c64_1_1_8__2362; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c64_new_c64_1_2_9__2363; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c64_new_c64_1_1_10__2364; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c64_new_c64_1_2_11__2365; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c64_new_c64_1_1_12__2366; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c64_new_c64_1_1_13__2367; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c64_new_c64_1_1_14__2368; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c64_new_c32_d64_1_14_; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c64_new_c32_d64_1_6_; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c64_new_c64_1_1_15__2369; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c64_new_c64_1_2_22__2370; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c64_new_c64_1_0_23__2371; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c64_new_c64_1_1_24__2372; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c64_new_c64_1_1_26__2373; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c64_new_c64_1_2_27__2374; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c64_new_c64_1_1_28__2375; + wire com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c64_new_c64_1_1_30__2376; + wire com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_fc_queue_empty_i; + wire com_llm_llm_tx_top_llmx08_tx_dllp_jefe_GND_2377; + wire com_llm_llm_tx_top_llmx08_tx_dllp_jefe_crc_an_vld_q_2378; + wire com_llm_llm_tx_top_llmx08_tx_dllp_jefe_N_60686_i_2379; + wire com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_expired_lbits_2380; + wire com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_expired_hbits_2381; + wire com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_expired_hbits12_NE_2_2382; + wire com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_expired_lbits12_NE_2_2383; + wire com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_expired_lbits12_0_2384; + wire com_llm_llm_tx_top_llmx08_tx_dllp_jefe_N_85585_i_2385; + wire com_llm_llm_tx_top_llmx08_tx_dllp_jefe_N_85585_1; + wire com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_fc_queue_empty; + wire com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_expired_lbits_1_sqmuxa_i_2386; + wire com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_expired_lbits12_NE_4_2387; + wire com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_expired_lbits12_NE_1_2388; + wire com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_expired_lbits12_NE_0_2389; + wire com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_expired_hbits_1_sqmuxa_i_2390; + wire com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_expired_hbits12_NE_3_2391; + wire com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_expired_hbits12_NE_1_2392; + wire com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_expired_hbits12_NE_0_2393; + wire com_llm_llm_tx_top_llmx08_tx_dllp_jefe_N_86007_i_2394; + wire com_llm_llm_tx_top_llmx08_tx_dllp_jefe_N_86940_i_2395; + wire com_llm_llm_tx_top_llmx08_tx_dllp_jefe_reg_tx_djefe_idle_3; + wire com_llm_llm_tx_top_llmx08_tx_dllp_jefe_N_15708_i; + wire com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_fc_valid_q_2396; + wire com_llm_llm_tx_top_llmx08_tx_dllp_jefe_an_vld_q_2397; + wire com_llm_llm_tx_top_llmx08_tx_dllp_jefe_N_58432; + wire com_llm_llm_tx_top_llmx08_tx_dllp_jefe_N_55904_i; + wire com_llm_llm_tx_top_llmx08_tx_dllp_jefe_an_next_q_5_0_a2_i_i_a2_0_a2_2398; + wire com_llm_llm_tx_top_llmx08_tx_dllp_jefe_N_56478_i_i_2399; + wire com_llm_llm_tx_top_llmx08_tx_dllp_jefe_N_15732_i; + wire com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_dllp_tx_next_9_f0_i_0_0_0_0_2400; + wire com_llm_llm_tx_top_llmx08_tx_dllp_jefe_an_next_q_2401; + wire com_llm_llm_tx_top_llmx08_tx_dllp_jefe_N_85641_i_2402; + wire com_llm_llm_tx_top_llmx08_tx_dllp_jefe_an_next_q_or_tx_fc_valid_q_7_u_0_i_i_0_2_2403; + wire com_llm_llm_tx_top_llmx08_tx_dllp_jefe_an_next_q_or_tx_fc_valid_q_7_u_0_i_i_0_o3_2404; + wire com_llm_llm_tx_top_llmx08_tx_dllp_jefe_N_61418; + wire com_llm_llm_tx_top_llmx08_tx_dllp_jefe_pm_type_d24; + wire com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_fc_dout_31_; + wire com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_fc_data_q_31__2405; + wire com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_fc_dout_30_; + wire com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_fc_data_q_30__2406; + wire com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_fc_dout_29_; + wire com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_fc_data_q_29__2407; + wire com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_fc_dout_28_; + wire com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_fc_data_q_28__2408; + wire com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_fc_dout_21_; + wire com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_fc_data_q_21__2409; + wire com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_fc_dout_20_; + wire com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_fc_data_q_20__2410; + wire com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_fc_dout_19_; + wire com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_fc_data_q_19__2411; + wire com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_fc_dout_18_; + wire com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_fc_data_q_18__2412; + wire com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_fc_dout_17_; + wire com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_fc_data_q_17__2413; + wire com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_fc_dout_16_; + wire com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_fc_data_q_16__2414; + wire com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_fc_dout_15_; + wire com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_fc_data_q_15__2415; + wire com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_fc_dout_14_; + wire com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_fc_data_q_14__2416; + wire com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_fc_dout_11_; + wire com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_fc_data_q_11__2417; + wire com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_fc_dout_10_; + wire com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_fc_data_q_10__2418; + wire com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_fc_dout_9_; + wire com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_fc_data_q_9__2419; + wire com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_fc_dout_8_; + wire com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_fc_data_q_8__2420; + wire com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_fc_dout_7_; + wire com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_fc_data_q_7__2421; + wire com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_fc_dout_6_; + wire com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_fc_data_q_6__2422; + wire com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_fc_dout_5_; + wire com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_fc_data_q_5__2423; + wire com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_fc_dout_4_; + wire com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_fc_data_q_4__2424; + wire com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_fc_dout_3_; + wire com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_fc_data_q_3__2425; + wire com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_fc_dout_2_; + wire com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_fc_data_q_2__2426; + wire com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_fc_dout_1_; + wire com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_fc_data_q_1__2427; + wire com_llm_llm_tx_top_llmx08_tx_dllp_jefe_N_15711_i; + wire com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_fc_dout_0_; + wire com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_fc_data_q_0__2428; + wire com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_dllp_pre_31_; + wire com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_dllp_pre_30_; + wire com_llm_llm_tx_top_llmx08_tx_dllp_jefe_N_87143_i_2429; + wire com_llm_llm_tx_top_llmx08_tx_dllp_jefe_N_15769_i; + wire com_llm_llm_tx_top_llmx08_tx_dllp_jefe_N_15767_i; + wire com_llm_llm_tx_top_llmx08_tx_dllp_jefe_N_15765_i; + wire com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_dllp_pre_21_; + wire com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_dllp_pre_20_; + wire com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_dllp_pre_19_; + wire com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_dllp_pre_18_; + wire com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_dllp_pre_17_; + wire com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_dllp_pre_16_; + wire com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_dllp_pre_15_; + wire com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_dllp_pre_14_; + wire com_llm_llm_tx_top_llmx08_tx_dllp_jefe_N_15763_i; + wire com_llm_llm_tx_top_llmx08_tx_dllp_jefe_N_15761_i; + wire com_llm_llm_tx_top_llmx08_tx_dllp_jefe_N_15759_i; + wire com_llm_llm_tx_top_llmx08_tx_dllp_jefe_N_15757_i; + wire com_llm_llm_tx_top_llmx08_tx_dllp_jefe_N_15755_i; + wire com_llm_llm_tx_top_llmx08_tx_dllp_jefe_N_15753_i; + wire com_llm_llm_tx_top_llmx08_tx_dllp_jefe_N_15751_i; + wire com_llm_llm_tx_top_llmx08_tx_dllp_jefe_N_15749_i; + wire com_llm_llm_tx_top_llmx08_tx_dllp_jefe_N_15747_i; + wire com_llm_llm_tx_top_llmx08_tx_dllp_jefe_N_15745_i; + wire com_llm_llm_tx_top_llmx08_tx_dllp_jefe_N_15743_i; + wire com_llm_llm_tx_top_llmx08_tx_dllp_jefe_N_15741_i; + wire com_llm_llm_tx_top_llmx08_tx_dllp_jefe_N_55923_i_i_2430; + wire com_llm_llm_tx_top_llmx08_tx_dllp_jefe_N_55923_i; + wire com_llm_llm_tx_top_llmx08_tx_dllp_jefe_N_87282_i_2431; + wire com_llm_llm_tx_top_llmx08_tx_dllp_jefe_N_56110_i_i_2432; + wire com_llm_llm_tx_top_llmx08_tx_dllp_jefe_N_56110_i; + wire com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_latency_timer17_i_o2_0_o2_0_o2_0_o2_2433; + wire com_llm_llm_tx_top_llmx08_tx_dllp_jefe_llm32_fc_fifo_GND_2434; + wire com_llm_llm_tx_top_llmx08_tx_dllp_jefe_llm32_fc_fifo_un1_data_count_3_s_1_2435; + wire com_llm_llm_tx_top_llmx08_tx_dllp_jefe_llm32_fc_fifo_un1_data_count_3_cry_0_2436; + wire com_llm_llm_tx_top_llmx08_tx_dllp_jefe_llm32_fc_fifo_un1_data_count_3_s_2_2437; + wire com_llm_llm_tx_top_llmx08_tx_dllp_jefe_llm32_fc_fifo_un1_data_count_3_cry_1_2438; + wire com_llm_llm_tx_top_llmx08_tx_dllp_jefe_llm32_fc_fifo_un1_data_count_3_s_3_2439; + wire com_llm_llm_tx_top_llmx08_tx_dllp_jefe_llm32_fc_fifo_un1_data_count_3_cry_2_2440; + wire com_llm_llm_tx_top_llmx08_tx_dllp_jefe_llm32_fc_fifo_N_87129_i_2441; + wire com_llm_llm_tx_top_llmx08_tx_dllp_jefe_llm32_fc_fifo_un1_data_count_3_axb_0_2442; + wire com_llm_llm_tx_top_llmx08_tx_dllp_jefe_llm32_fc_fifo_un1_data_count_3_axb_3_2443; + wire com_llm_llm_tx_top_llmx08_tx_dllp_jefe_llm32_fc_fifo_un1_data_count_3_axb_2_2444; + wire com_llm_llm_tx_top_llmx08_tx_dllp_jefe_llm32_fc_fifo_un1_data_count_3_axb_1_2445; + wire com_llm_llm_tx_top_llmx08_tx_dllp_jefe_llm32_fc_fifo_N_58429_2; + wire com_llm_llm_tx_top_llmx08_tx_dllp_jefe_llm32_fc_fifo_un1_rd_en_4_i; + wire com_llm_llm_tx_top_llmx08_tx_dllp_jefe_llm32_fc_fifo_un1_rd_en_4_0_0_0_0_1_2446; + wire com_llm_llm_tx_top_llmx08_tx_packet_packer_next_arb_state_0_sqmuxa; + wire com_llm_llm_tx_top_llmx08_tx_packet_packer_N_59255_1; + wire com_llm_llm_tx_top_llmx08_tx_packet_packer_N_59248; + wire com_llm_llm_tx_top_llmx08_tx_packet_packer_new_c32_1_3_0_; + wire com_llm_llm_tx_top_llmx08_tx_packet_packer_new_c32_1_2_0_; + wire com_llm_llm_tx_top_llmx08_tx_packet_packer_new_c32_1_2_15_; + wire com_llm_llm_tx_top_llmx08_tx_packet_packer_new_c32_1_1_13_; + wire com_llm_llm_tx_top_llmx08_tx_packet_packer_new_c32_1_0_12_; + wire com_llm_llm_tx_top_llmx08_tx_packet_packer_N_59258_5; + wire com_llm_llm_tx_top_llmx08_tx_packet_packer_new_c32_1_1_6_; + wire com_llm_llm_tx_top_llmx08_tx_packet_packer_new_c32_1_2_4_; + wire com_llm_llm_tx_top_llmx08_tx_packet_packer_new_c32_1_1_2_; + wire com_llm_llm_tx_top_llmx08_tx_packet_packer_new_c32_1_2_1_; + wire com_llm_llm_tx_top_llmx08_tx_packet_packer_new_c32_14_; + wire com_llm_llm_tx_top_llmx08_tx_packet_packer_new_c32_11_; + wire com_llm_llm_tx_top_llmx08_tx_packet_packer_new_c32_1_0_10_; + wire com_llm_llm_tx_top_llmx08_tx_packet_packer_new_c32_1_2_8_; + wire com_llm_llm_tx_top_llmx08_tx_packet_packer_new_c32_1_2_5_; + wire com_llm_llm_tx_top_llmx08_tx_packet_packer_new_c32_1_3_3_; + wire com_llm_llm_tx_top_llmx08_tx_packet_packer_N_56522_i_2447; + wire com_llm_llm_tx_top_llmx08_tx_packet_packer_N_86829_i_2448; + wire com_llm_llm_tx_top_llmx08_tx_packet_packer_trans_non_aligned_2449; + wire com_llm_llm_tx_top_llmx08_tx_packet_packer_N_51682_i; + wire com_llm_llm_tx_top_llmx08_tx_packet_packer_N_51680_i; + wire com_llm_llm_tx_top_llmx08_tx_packet_packer_N_51678_i; + wire com_llm_llm_tx_top_llmx08_tx_packet_packer_N_51676_i; + wire com_llm_llm_tx_top_llmx08_tx_packet_packer_N_51674_i; + wire com_llm_llm_tx_top_llmx08_tx_packet_packer_N_51672_i; + wire com_llm_llm_tx_top_llmx08_tx_packet_packer_N_51670_i; + wire com_llm_llm_tx_top_llmx08_tx_packet_packer_N_51668_i; + wire com_llm_llm_tx_top_llmx08_tx_packet_packer_N_86910_i_2450; + wire com_llm_llm_tx_top_llmx08_tx_packet_packer_N_86939_i_2451; + wire com_llm_llm_tx_top_llmx08_tx_packet_packer_N_86911_i_2452; + wire com_llm_llm_tx_top_llmx08_tx_packet_packer_N_86912_i_2453; + wire com_llm_llm_tx_top_llmx08_tx_packet_packer_N_86913_i_2454; + wire com_llm_llm_tx_top_llmx08_tx_packet_packer_N_86914_i_2455; + wire com_llm_llm_tx_top_llmx08_tx_packet_packer_N_86915_i_2456; + wire com_llm_llm_tx_top_llmx08_tx_packet_packer_N_86916_i_2457; + wire com_llm_llm_tx_top_llmx08_tx_packet_packer_N_51193_i; + wire com_llm_llm_tx_top_llmx08_tx_packet_packer_N_51195_i; + wire com_llm_llm_tx_top_llmx08_tx_packet_packer_N_51291_i; + wire com_llm_llm_tx_top_llmx08_tx_packet_packer_N_51289_i; + wire com_llm_llm_tx_top_llmx08_tx_packet_packer_N_51287_i; + wire com_llm_llm_tx_top_llmx08_tx_packet_packer_N_51285_i; + wire com_llm_llm_tx_top_llmx08_tx_packet_packer_N_51283_i; + wire com_llm_llm_tx_top_llmx08_tx_packet_packer_N_51281_i; + wire com_llm_llm_tx_top_llmx08_tx_packet_packer_N_51279_i; + wire com_llm_llm_tx_top_llmx08_tx_packet_packer_N_51277_i; + wire com_llm_llm_tx_top_llmx08_tx_packet_packer_N_85739_i_2458; + wire com_llm_llm_tx_top_llmx08_tx_packet_packer_N_85738_i_2459; + wire com_llm_llm_tx_top_llmx08_tx_packet_packer_N_85737_i_2460; + wire com_llm_llm_tx_top_llmx08_tx_packet_packer_N_85736_i_2461; + wire com_llm_llm_tx_top_llmx08_tx_packet_packer_N_85735_i_2462; + wire com_llm_llm_tx_top_llmx08_tx_packet_packer_N_85734_i_2463; + wire com_llm_llm_tx_top_llmx08_tx_packet_packer_N_85698_i_2464; + wire com_llm_llm_tx_top_llmx08_tx_packet_packer_N_85733_i_2465; + wire com_llm_llm_tx_top_llmx08_tx_packet_packer_N_85732_i_2466; + wire com_llm_llm_tx_top_llmx08_tx_packet_packer_N_85731_i_2467; + wire com_llm_llm_tx_top_llmx08_tx_packet_packer_N_85730_i_2468; + wire com_llm_llm_tx_top_llmx08_tx_packet_packer_N_85729_i_2469; + wire com_llm_llm_tx_top_llmx08_tx_packet_packer_N_85728_i_2470; + wire com_llm_llm_tx_top_llmx08_tx_packet_packer_N_85727_i_2471; + wire com_llm_llm_tx_top_llmx08_tx_packet_packer_N_85726_i_2472; + wire com_llm_llm_tx_top_llmx08_tx_packet_packer_N_85725_i_2473; + wire com_llm_llm_tx_top_llmx08_tx_packet_packer_N_85699_i_2474; + wire com_llm_llm_tx_top_llmx08_tx_packet_packer_N_85700_i_2475; + wire com_llm_llm_tx_top_llmx08_tx_packet_packer_N_85724_i_2476; + wire com_llm_llm_tx_top_llmx08_tx_packet_packer_N_85723_i_2477; + wire com_llm_llm_tx_top_llmx08_tx_packet_packer_N_85722_i_2478; + wire com_llm_llm_tx_top_llmx08_tx_packet_packer_N_85721_i_2479; + wire com_llm_llm_tx_top_llmx08_tx_packet_packer_N_85720_i_2480; + wire com_llm_llm_tx_top_llmx08_tx_packet_packer_N_85719_i_2481; + wire com_llm_llm_tx_top_llmx08_tx_packet_packer_N_85718_i_2482; + wire com_llm_llm_tx_top_llmx08_tx_packet_packer_N_57425; + wire com_llm_llm_tx_top_llmx08_tx_packet_packer_N_85717_i_2483; + wire com_llm_llm_tx_top_llmx08_tx_packet_packer_N_57423; + wire com_llm_llm_tx_top_llmx08_tx_packet_packer_N_85716_i_2484; + wire com_llm_llm_tx_top_llmx08_tx_packet_packer_N_57421; + wire com_llm_llm_tx_top_llmx08_tx_packet_packer_N_85715_i_2485; + wire com_llm_llm_tx_top_llmx08_tx_packet_packer_N_57419; + wire com_llm_llm_tx_top_llmx08_tx_packet_packer_N_85714_i_2486; + wire com_llm_llm_tx_top_llmx08_tx_packet_packer_N_57417; + wire com_llm_llm_tx_top_llmx08_tx_packet_packer_N_85713_i_2487; + wire com_llm_llm_tx_top_llmx08_tx_packet_packer_N_57415; + wire com_llm_llm_tx_top_llmx08_tx_packet_packer_N_85712_i_2488; + wire com_llm_llm_tx_top_llmx08_tx_packet_packer_N_57413; + wire com_llm_llm_tx_top_llmx08_tx_packet_packer_N_85711_i_2489; + wire com_llm_llm_tx_top_llmx08_tx_packet_packer_N_61349; + wire com_llm_llm_tx_top_llmx08_tx_packet_packer_N_61327; + wire com_llm_llm_tx_top_llmx08_tx_packet_packer_N_57410; + wire com_llm_llm_tx_top_llmx08_tx_packet_packer_N_51243_i; + wire com_llm_llm_tx_top_llmx08_tx_packet_packer_N_63518; + wire com_llm_llm_tx_top_llmx08_tx_packet_packer_N_56441; + wire com_llm_llm_tx_top_llmx08_tx_packet_packer_N_51241_i; + wire com_llm_llm_tx_top_llmx08_tx_packet_packer_N_63517; + wire com_llm_llm_tx_top_llmx08_tx_packet_packer_N_56442; + wire com_llm_llm_tx_top_llmx08_tx_packet_packer_N_51239_i; + wire com_llm_llm_tx_top_llmx08_tx_packet_packer_N_63516; + wire com_llm_llm_tx_top_llmx08_tx_packet_packer_N_56443; + wire com_llm_llm_tx_top_llmx08_tx_packet_packer_N_51237_i; + wire com_llm_llm_tx_top_llmx08_tx_packet_packer_N_63515; + wire com_llm_llm_tx_top_llmx08_tx_packet_packer_N_56444; + wire com_llm_llm_tx_top_llmx08_tx_packet_packer_N_51235_i; + wire com_llm_llm_tx_top_llmx08_tx_packet_packer_N_63514; + wire com_llm_llm_tx_top_llmx08_tx_packet_packer_N_56445; + wire com_llm_llm_tx_top_llmx08_tx_packet_packer_N_51233_i; + wire com_llm_llm_tx_top_llmx08_tx_packet_packer_N_63513; + wire com_llm_llm_tx_top_llmx08_tx_packet_packer_N_56446; + wire com_llm_llm_tx_top_llmx08_tx_packet_packer_N_51231_i; + wire com_llm_llm_tx_top_llmx08_tx_packet_packer_N_63512; + wire com_llm_llm_tx_top_llmx08_tx_packet_packer_N_56447; + wire com_llm_llm_tx_top_llmx08_tx_packet_packer_N_51229_i; + wire com_llm_llm_tx_top_llmx08_tx_packet_packer_N_63511; + wire com_llm_llm_tx_top_llmx08_tx_packet_packer_N_56448; + wire com_llm_llm_tx_top_llmx08_tx_packet_packer_N_51227_i; + wire com_llm_llm_tx_top_llmx08_tx_packet_packer_N_63510; + wire com_llm_llm_tx_top_llmx08_tx_packet_packer_N_56449; + wire com_llm_llm_tx_top_llmx08_tx_packet_packer_N_51225_i; + wire com_llm_llm_tx_top_llmx08_tx_packet_packer_N_63509; + wire com_llm_llm_tx_top_llmx08_tx_packet_packer_N_56450; + wire com_llm_llm_tx_top_llmx08_tx_packet_packer_N_51223_i; + wire com_llm_llm_tx_top_llmx08_tx_packet_packer_N_63508; + wire com_llm_llm_tx_top_llmx08_tx_packet_packer_N_56451; + wire com_llm_llm_tx_top_llmx08_tx_packet_packer_N_51221_i; + wire com_llm_llm_tx_top_llmx08_tx_packet_packer_N_63507; + wire com_llm_llm_tx_top_llmx08_tx_packet_packer_N_56452; + wire com_llm_llm_tx_top_llmx08_tx_packet_packer_N_51219_i; + wire com_llm_llm_tx_top_llmx08_tx_packet_packer_N_63506; + wire com_llm_llm_tx_top_llmx08_tx_packet_packer_N_56453; + wire com_llm_llm_tx_top_llmx08_tx_packet_packer_N_51217_i; + wire com_llm_llm_tx_top_llmx08_tx_packet_packer_N_63505; + wire com_llm_llm_tx_top_llmx08_tx_packet_packer_N_56454; + wire com_llm_llm_tx_top_llmx08_tx_packet_packer_N_51215_i; + wire com_llm_llm_tx_top_llmx08_tx_packet_packer_N_63504; + wire com_llm_llm_tx_top_llmx08_tx_packet_packer_N_56455; + wire com_llm_llm_tx_top_llmx08_tx_packet_packer_N_51213_i; + wire com_llm_llm_tx_top_llmx08_tx_packet_packer_N_56456; + wire com_llm_llm_tx_top_llmx08_tx_packet_packer_N_51211_i; + wire com_llm_llm_tx_top_llmx08_tx_packet_packer_N_57409; + wire com_llm_llm_tx_top_llmx08_tx_packet_packer_N_56457; + wire com_llm_llm_tx_top_llmx08_tx_packet_packer_N_51209_i; + wire com_llm_llm_tx_top_llmx08_tx_packet_packer_N_57407; + wire com_llm_llm_tx_top_llmx08_tx_packet_packer_N_56458; + wire com_llm_llm_tx_top_llmx08_tx_packet_packer_N_51207_i; + wire com_llm_llm_tx_top_llmx08_tx_packet_packer_N_57404; + wire com_llm_llm_tx_top_llmx08_tx_packet_packer_N_51205_i; + wire com_llm_llm_tx_top_llmx08_tx_packet_packer_N_61304; + wire com_llm_llm_tx_top_llmx08_tx_packet_packer_N_57402; + wire com_llm_llm_tx_top_llmx08_tx_packet_packer_N_51203_i; + wire com_llm_llm_tx_top_llmx08_tx_packet_packer_N_57401; + wire com_llm_llm_tx_top_llmx08_tx_packet_packer_N_56461; + wire com_llm_llm_tx_top_llmx08_tx_packet_packer_N_51201_i; + wire com_llm_llm_tx_top_llmx08_tx_packet_packer_N_57399; + wire com_llm_llm_tx_top_llmx08_tx_packet_packer_N_56462; + wire com_llm_llm_tx_top_llmx08_tx_packet_packer_N_51199_i; + wire com_llm_llm_tx_top_llmx08_tx_packet_packer_N_57397; + wire com_llm_llm_tx_top_llmx08_tx_packet_packer_N_56463; + wire com_llm_llm_tx_top_llmx08_tx_packet_packer_N_51197_i; + wire com_llm_llm_tx_top_llmx08_tx_packet_packer_aligned_2490; + wire com_llm_llm_tx_top_llmx08_tx_packet_packer_N_57395; + wire com_llm_llm_tx_top_llmx08_tx_packet_packer_N_56464; + wire com_llm_llm_tx_top_llmx08_tx_packet_packer_N_56006_i; + wire com_llm_llm_tx_top_llmx08_tx_packet_packer_N_33959_i; + wire com_llm_llm_tx_top_llmx08_tx_packet_packer_next_arb_state_i_i_0_2_39368_2491; + wire com_llm_llm_tx_top_llmx08_tx_packet_packer_next_arb_state_i_i_0_2_39366_2492; + wire com_llm_llm_tx_top_llmx08_tx_packet_packer_N_33961_i; + wire com_llm_llm_tx_top_llmx08_tx_packet_packer_N_59258_4; + wire com_llm_llm_tx_top_llmx08_tx_packet_packer_N_59249; + wire com_llm_llm_tx_top_llmx08_tx_packet_packer_N_85695_i_2493; + wire com_llm_llm_tx_top_llmx08_tx_packet_packer_N_59252; + wire com_llm_llm_tx_top_llmx08_tx_packet_packer_N_56163_i; + wire com_llm_llm_tx_top_llmx08_tx_packet_packer_new_c32_1_0_7_; + wire com_llm_llm_tx_top_llmx08_tx_packet_packer_N_63503; + wire com_llm_llm_tx_top_llmx08_tx_packet_packer_N_56059_i; + wire com_llm_llm_tx_top_llmx08_tx_packet_packer_tx_idle_next_2494; + wire com_llm_llm_tx_top_llmx08_tx_packet_packer_N_59258_1; + wire com_llm_llm_tx_top_llmx08_tx_packet_packer_N_56940_i; + wire com_llm_llm_tx_top_llmx08_tx_packet_packer_llm_rx_crc16_d32_new_c32_1_0_9__2495; + wire com_llm_llm_tx_top_llmx08_tx_packet_packer_llm_rx_crc16_d32_new_c32_1_1_8__2496; + wire com_llm_llm_tx_top_llmx08_tx_packet_packer_llm_rx_crc16_d32_new_c32_1_1_4__2497; + wire com_llm_llm_tx_top_llmx08_tx_packet_packer_llm_rx_crc16_d32_new_c32_1_1_9__2498; + wire com_llm_llm_tx_top_llmx08_tx_packet_packer_llm_rx_crc16_d32_new_c32_1_0_11__2499; + wire com_llm_llm_tx_top_llmx08_tx_packet_packer_llm_rx_crc16_d32_new_c32_1_0_5__2500; + wire com_llm_llm_tx_top_llmx08_tx_packet_packer_llm_rx_crc16_d32_new_c32_1_0_3__2501; + wire com_llm_llm_rx_top_rx_tlp_ferr_n; + wire com_llm_llm_rx_top_rx_tlp_crc_err_n; + wire com_llm_llm_rx_top_rx_sof_n; + wire com_llm_llm_rx_top_rx_dllp_d_4_i_m2_i_m3_0_18_; + wire com_llm_llm_rx_top_rx_dllp_d_4_i_m2_i_m3_0_19_; + wire com_llm_llm_rx_top_rx_dllp_d_4_i_m2_i_m3_0_20_; + wire com_llm_llm_rx_top_rx_dllp_d_4_i_m2_i_m3_0_21_; + wire com_llm_llm_rx_top_rx_dllp_d_4_i_m2_i_m3_0_16_; + wire com_llm_llm_rx_top_rx_dllp_d_4_i_m3_0_14_; + wire com_llm_llm_rx_top_rx_dllp_d_4_i_m3_0_15_; + wire com_llm_llm_rx_top_rx_dllp_d_4_i_m3_0_17_; + wire com_llm_llm_rx_top_rx_tlp_eof_n; + wire com_llm_llm_rx_top_rx_tlp_eof_n_i; + wire com_llm_llm_rx_top_rx_tlp_sof_n; + wire com_llm_llm_rx_top_rx_tlp_sof_n_i; + wire com_llm_llm_rx_top_rx_tlp_vld_l_n; + wire com_llm_llm_rx_top_rx_dllp_sof_n; + wire com_llm_llm_rx_top_rx_tlp_vld_h_n; + wire com_llm_llm_rx_top_rx_dllp_vld_h_n; + wire com_llm_llm_rx_top_rx_dllp_eof_n; + wire com_llm_llm_rx_top_rx_tlp_nullified; + wire com_llm_llm_rx_top_rx_tferr_n_i; + wire com_llm_llm_rx_top_rx_dllp_sof_n_i; + wire com_llm_llm_rx_top_rx_data_60_; + wire com_llm_llm_rx_top_rx_data_55_; + wire com_llm_llm_rx_top_rx_data_54_; + wire com_llm_llm_rx_top_rx_data_53_; + wire com_llm_llm_rx_top_rx_data_52_; + wire com_llm_llm_rx_top_rx_data_51_; + wire com_llm_llm_rx_top_rx_data_50_; + wire com_llm_llm_rx_top_rx_data_49_; + wire com_llm_llm_rx_top_rx_data_48_; + wire com_llm_llm_rx_top_rx_data_47_; + wire com_llm_llm_rx_top_rx_data_46_; + wire com_llm_llm_rx_top_rx_data_45_; + wire com_llm_llm_rx_top_rx_data_44_; + wire com_llm_llm_rx_top_rx_data_43_; + wire com_llm_llm_rx_top_rx_data_42_; + wire com_llm_llm_rx_top_rx_data_41_; + wire com_llm_llm_rx_top_rx_data_40_; + wire com_llm_llm_rx_top_rx_data_39_; + wire com_llm_llm_rx_top_rx_data_38_; + wire com_llm_llm_rx_top_rx_data_37_; + wire com_llm_llm_rx_top_rx_data_36_; + wire com_llm_llm_rx_top_rx_data_35_; + wire com_llm_llm_rx_top_rx_data_33_; + wire com_llm_llm_rx_top_rx_data_32_; + wire com_llm_llm_rx_top_rx_data_31_; + wire com_llm_llm_rx_top_rx_data_30_; + wire com_llm_llm_rx_top_rx_data_29_; + wire com_llm_llm_rx_top_rx_data_28_; + wire com_llm_llm_rx_top_rx_data_27_; + wire com_llm_llm_rx_top_rx_data_26_; + wire com_llm_llm_rx_top_rx_data_25_; + wire com_llm_llm_rx_top_rx_data_24_; + wire com_llm_llm_rx_top_rx_data_23_; + wire com_llm_llm_rx_top_rx_data_22_; + wire com_llm_llm_rx_top_rx_data_21_; + wire com_llm_llm_rx_top_rx_data_20_; + wire com_llm_llm_rx_top_rx_data_19_; + wire com_llm_llm_rx_top_rx_data_18_; + wire com_llm_llm_rx_top_rx_data_17_; + wire com_llm_llm_rx_top_rx_data_16_; + wire com_llm_llm_rx_top_rx_data_15_; + wire com_llm_llm_rx_top_rx_data_14_; + wire com_llm_llm_rx_top_rx_data_13_; + wire com_llm_llm_rx_top_rx_data_12_; + wire com_llm_llm_rx_top_rx_data_11_; + wire com_llm_llm_rx_top_rx_data_10_; + wire com_llm_llm_rx_top_rx_data_9_; + wire com_llm_llm_rx_top_rx_data_8_; + wire com_llm_llm_rx_top_rx_data_7_; + wire com_llm_llm_rx_top_rx_data_6_; + wire com_llm_llm_rx_top_rx_data_5_; + wire com_llm_llm_rx_top_rx_data_4_; + wire com_llm_llm_rx_top_rx_data_3_; + wire com_llm_llm_rx_top_rx_data_2_; + wire com_llm_llm_rx_top_rx_data_1_; + wire com_llm_llm_rx_top_rx_data_0_; + wire com_llm_llm_rx_top_llm_rx_demux_un5_idle_a_n_0_2502; + wire com_llm_llm_rx_top_llm_rx_demux_un10_idle_a_n_0_2503; + wire com_llm_llm_rx_top_llm_rx_demux_un4_idle_on_low_n_0_2504; + wire com_llm_llm_rx_top_llm_rx_demux_N_15981_i; + wire com_llm_llm_rx_top_llm_rx_demux_un4_idle_on_high_n_1_2505; + wire com_llm_llm_rx_top_llm_rx_demux_un10_idle_a_n_3_2506; + wire com_llm_llm_rx_top_llm_rx_demux_un5_idle_a_n_3_2507; + wire com_llm_llm_rx_top_llm_rx_demux_un4_idle_on_low_n_3_2508; + wire com_llm_llm_rx_top_llm_rx_demux_un4_idle_on_high_n_4_2509; + wire com_llm_llm_rx_top_llm_rx_demux_un10_idle_a_n_2510; + wire com_llm_llm_rx_top_llm_rx_demux_un4_idle_on_low_n_2511; + wire com_llm_llm_rx_top_llm_rx_demux_un5_idle_a_n_2512; + wire com_llm_llm_rx_top_llm_rx_demux_dllp_vld_h_n_q_11_iv_i_a2_0_1_2_2513; + wire com_llm_llm_rx_top_llm_rx_demux_tlp_ferr_h_n_q_9_0_39369_2514; + wire com_llm_llm_rx_top_llm_rx_demux_tlp_ferr_n_qq_8_u_i_1_2515; + wire com_llm_llm_rx_top_llm_rx_demux_N_15983_i; + wire com_llm_llm_rx_top_llm_rx_demux_N_15985_i; + wire com_llm_llm_rx_top_llm_rx_demux_dllp_vld_h_n_q_11_iv_i_a2_0; + wire com_llm_llm_rx_top_llm_rx_demux_N_16012_3; + wire com_llm_llm_rx_top_llm_rx_demux_N_16012_1; + wire com_llm_llm_rx_top_llm_rx_demux_N_15978_i; + wire com_llm_llm_rx_top_llm_rx_demux_tlp_ferr_n_q_9_u_i_39421_2516; + wire com_llm_llm_rx_top_llm_rx_demux_N_15979_i; + wire com_llm_llm_rx_top_llm_rx_demux_tlp_ip_flag_5_iv_i_a2_2517; + wire com_llm_llm_rx_top_llm_rx_demux_phy_frame_l_t_2518; + wire com_llm_llm_rx_top_llm_rx_demux_un1_long_dllp_u_q14_2_i_1_2519; + wire com_llm_llm_rx_top_llm_rx_demux_phy_frame_l_q_2520; + wire com_llm_llm_rx_top_llm_rx_demux_phy_frame_h_q_2521; + wire com_llm_llm_rx_top_llm_rx_demux_phy_rbad_frm_q_2522; + wire com_llm_llm_rx_top_llm_rx_demux_N_15935_i; + wire com_llm_llm_rx_top_llm_rx_demux_dllp_eof_n_q13_i_2523; + wire com_llm_llm_rx_top_llm_rx_demux_dllp_eof_n_q_2524; + wire com_llm_llm_rx_top_llm_rx_demux_tlp_align_q_2525; + wire com_llm_llm_rx_top_llm_rx_demux_N_86947_i_2526; + wire com_llm_llm_rx_top_llm_rx_demux_dllp_sof_n_q26_m_0; + wire com_llm_llm_rx_top_llm_rx_demux_dllp_a_2527; + wire com_llm_llm_rx_top_llm_rx_demux_N_16009_i_2528; + wire com_llm_llm_rx_top_llm_rx_demux_tlp_sof_n_q_2529; + wire com_llm_llm_rx_top_llm_rx_demux_N_86946_i_2530; + wire com_llm_llm_rx_top_llm_rx_demux_dllp_sof_n_q_0_sqmuxa; + wire com_llm_llm_rx_top_llm_rx_demux_dllp_u_2531; + wire com_llm_llm_rx_top_llm_rx_demux_tlp_unalign_q13_i_a2_2532; + wire com_llm_llm_rx_top_llm_rx_demux_tlp_unalign_q_2533; + wire com_llm_llm_rx_top_llm_rx_demux_N_15949_i; + wire com_llm_llm_rx_top_llm_rx_demux_dllp_sof_n_q_2534; + wire com_llm_llm_rx_top_llm_rx_demux_N_15941_i; + wire com_llm_llm_rx_top_llm_rx_demux_N_10984_i; + wire com_llm_llm_rx_top_llm_rx_demux_tlp_ferr_h_n_q_2535; + wire com_llm_llm_rx_top_llm_rx_demux_tlp_sof_n_q_and_tlp_ip_flag_6; + wire com_llm_llm_rx_top_llm_rx_demux_N_85692_i_2536; + wire com_llm_llm_rx_top_llm_rx_demux_rx_tferr_n; + wire com_llm_llm_rx_top_llm_rx_demux_N_85691_i_2537; + wire com_llm_llm_rx_top_llm_rx_demux_N_85673_i_2538; + wire com_llm_llm_rx_top_llm_rx_demux_N_86948_i_2539; + wire com_llm_llm_rx_top_llm_rx_demux_N_15953_i; + wire com_llm_llm_rx_top_llm_rx_demux_dllp_vld_h_n_q_2540; + wire com_llm_llm_rx_top_llm_rx_demux_N_85694_i_2541; + wire com_llm_llm_rx_top_llm_rx_demux_tlp_ferr_n_q_2542; + wire com_llm_llm_rx_top_llm_rx_demux_N_15996_i_2543; + wire com_llm_llm_rx_top_llm_rx_demux_long_dllp_u_q13; + wire com_llm_llm_rx_top_llm_rx_demux_long_dllp_u_q_2544; + wire com_llm_llm_rx_top_llm_rx_demux_N_15967_i; + wire com_llm_llm_rx_top_llm_rx_demux_tlp_vld_h_n_q_2545; + wire com_llm_llm_rx_top_llm_rx_demux_N_86944_i_2546; + wire com_llm_llm_rx_top_llm_rx_demux_tlp_ip_flag_2547; + wire com_llm_llm_rx_top_llm_rx_demux_N_16008_i_2548; + wire com_llm_llm_rx_top_llm_rx_demux_N_10987_i; + wire com_llm_llm_rx_top_llm_rx_demux_tlp_vld_l_n_q_2549; + wire com_llm_llm_rx_top_llm_rx_demux_N_15977_i_i_2550; + wire com_llm_llm_rx_top_llm_rx_demux_N_15977_i; + wire com_llm_llm_rx_top_llm_rx_demux_tlp_align_q13; + wire com_llm_llm_rx_top_llm_rx_demux_N_15980_i; + wire com_llm_llm_rx_top_llm_rx_demux_phy_frame_h_t_2551; + wire com_llm_llm_rx_top_llm_rx_demux_N_85313_i_2552; + wire com_llm_llm_rx_top_llm_rx_demux_tlp_sof_n_q_and_tlp_ip_flag_2553; + wire com_llm_llm_rx_top_llm_rx_demux_tlp_eof_n_q_2554; + wire com_llm_llm_rx_top_llm_rx_demux_N_85313_i_1_2555; + wire com_llm_llm_rx_top_llm_rx_demux_N_16020_1; + wire com_llm_llm_rx_top_llm_rx_dllp_crc_RX_DLLP_LOW_M1_2_cry_0_2556; + wire com_llm_llm_rx_top_llm_rx_dllp_crc_RX_DLLP_LOW_M1_2_cry_1_2557; + wire com_llm_llm_rx_top_llm_rx_dllp_crc_RX_DLLP_LOW_M1_2_cry_2_2558; + wire com_llm_llm_rx_top_llm_rx_dllp_crc_RX_DLLP_LOW_M1_2_cry_3_2559; + wire com_llm_llm_rx_top_llm_rx_dllp_crc_RX_DLLP_LOW_M1_2_cry_4_2560; + wire com_llm_llm_rx_top_llm_rx_dllp_crc_RX_DLLP_LOW_M1_2_cry_5_2561; + wire com_llm_llm_rx_top_llm_rx_dllp_crc_RX_DLLP_LOW_M1_2_cry_6_2562; + wire com_llm_llm_rx_top_llm_rx_dllp_crc_RX_DLLP_LOW_M1_2_cry_7_2563; + wire com_llm_llm_rx_top_llm_rx_dllp_crc_RX_DLLP_LOW_M1_2_cry_8_2564; + wire com_llm_llm_rx_top_llm_rx_dllp_crc_VCC_2565; + wire com_llm_llm_rx_top_llm_rx_dllp_crc_RX_DLLP_LOW_M1_2_cry_9_2566; + wire com_llm_llm_rx_top_llm_rx_dllp_crc_RX_DLLP_LOW_M1_2_cry_10_2567; + wire com_llm_llm_rx_top_llm_rx_dllp_crc_crc16_ok; + wire com_llm_llm_rx_top_llm_rx_dllp_crc_GND_2568; + wire com_llm_llm_rx_top_llm_rx_dllp_crc_fr_straddle_q_2569; + wire com_llm_llm_rx_top_llm_rx_dllp_crc_reg_dllp_qq_2570; + wire com_llm_llm_rx_top_llm_rx_dllp_crc_str_dllp; + wire com_llm_llm_rx_top_llm_rx_dllp_crc_str_dllp_q_2571; + wire com_llm_llm_rx_top_llm_rx_dllp_crc_reg_dllp; + wire com_llm_llm_rx_top_llm_rx_dllp_crc_reg_dllp_q_2572; + wire com_llm_llm_rx_top_llm_rx_dllp_crc_N_27234_i_2573; + wire com_llm_llm_rx_top_llm_rx_dllp_crc_RX_DLLP_VLD_5; + wire com_llm_llm_rx_top_llm_rx_dllp_crc_rx_dllp_d_4_i_m3_0_0__2574; + wire com_llm_llm_rx_top_llm_rx_dllp_crc_rx_dllp_d_4_i_m3_0_11__2575; + wire com_llm_llm_rx_top_llm_rx_dllp_crc_rx_dllp_d_4_i_m3_0_10__2576; + wire com_llm_llm_rx_top_llm_rx_dllp_crc_rx_dllp_d_4_i_m3_0_9__2577; + wire com_llm_llm_rx_top_llm_rx_dllp_crc_rx_dllp_d_4_i_m3_0_8__2578; + wire com_llm_llm_rx_top_llm_rx_dllp_crc_rx_dllp_d_4_i_m2_i_m3_0_7__2579; + wire com_llm_llm_rx_top_llm_rx_dllp_crc_rx_dllp_d_4_i_m3_0_6__2580; + wire com_llm_llm_rx_top_llm_rx_dllp_crc_rx_dllp_d_4_i_m3_0_5__2581; + wire com_llm_llm_rx_top_llm_rx_dllp_crc_rx_dllp_d_4_i_m3_0_4__2582; + wire com_llm_llm_rx_top_llm_rx_dllp_crc_rx_dllp_d_4_i_m3_0_3__2583; + wire com_llm_llm_rx_top_llm_rx_dllp_crc_rx_dllp_d_4_i_m3_0_2__2584; + wire com_llm_llm_rx_top_llm_rx_dllp_crc_rx_dllp_d_4_i_m3_0_1__2585; + wire com_llm_llm_rx_top_llm_rx_dllp_crc_rx_dllp_d_4_i_m3_0_31__2586; + wire com_llm_llm_rx_top_llm_rx_dllp_crc_rx_dllp_d_4_i_m2_i_m3_0_30__2587; + wire com_llm_llm_rx_top_llm_rx_dllp_crc_rx_dllp_d_4_i_m2_i_m3_0_29__2588; + wire com_llm_llm_rx_top_llm_rx_dllp_crc_rx_dllp_d_4_i_m2_i_m3_0_28__2589; + wire com_llm_llm_rx_top_llm_rx_dllp_crc_rx_dllp_d_4_i_m3_0_27__2590; + wire com_llm_llm_rx_top_llm_rx_dllp_crc_rx_dllp_d_4_i_m3_0_26__2591; + wire com_llm_llm_rx_top_llm_rx_dllp_crc_rx_dllp_d_4_i_m3_0_25__2592; + wire com_llm_llm_rx_top_llm_rx_dllp_crc_rx_dllp_d_4_i_m3_0_24__2593; + wire com_llm_llm_rx_top_llm_rx_dllp_crc_rx_dllp_d_6__2594; + wire com_llm_llm_rx_top_llm_rx_dllp_crc_rx_dllp_d_5__2595; + wire com_llm_llm_rx_top_llm_rx_dllp_crc_rx_dllp_d_4__2596; + wire com_llm_llm_rx_top_llm_rx_dllp_crc_rx_dllp_d_3__2597; + wire com_llm_llm_rx_top_llm_rx_dllp_crc_rx_dllp_d_2__2598; + wire com_llm_llm_rx_top_llm_rx_dllp_crc_rx_dllp_d_1__2599; + wire com_llm_llm_rx_top_llm_rx_dllp_crc_rx_dllp_d_25__2600; + wire com_llm_llm_rx_top_llm_rx_dllp_crc_rx_dllp_d_24__2601; + wire com_llm_llm_rx_top_llm_rx_dllp_crc_rx_dllp_d_11__2602; + wire com_llm_llm_rx_top_llm_rx_dllp_crc_rx_dllp_d_10__2603; + wire com_llm_llm_rx_top_llm_rx_dllp_crc_rx_dllp_d_9__2604; + wire com_llm_llm_rx_top_llm_rx_dllp_crc_rx_dllp_d_8__2605; + wire com_llm_llm_rx_top_llm_rx_dllp_crc_rx_dllp_d_7__2606; + wire com_llm_llm_rx_top_llm_rx_dllp_crc_new_c32_nst_i_8_; + wire com_llm_llm_rx_top_llm_rx_dllp_crc_new_c32_1_i_0_7_; + wire com_llm_llm_rx_top_llm_rx_dllp_crc_new_c32_nst_i_6_; + wire com_llm_llm_rx_top_llm_rx_dllp_crc_new_c32_1_i_0_5_; + wire com_llm_llm_rx_top_llm_rx_dllp_crc_new_c32_1_i_0_4_; + wire com_llm_llm_rx_top_llm_rx_dllp_crc_new_c32_1_i_0_3_; + wire com_llm_llm_rx_top_llm_rx_dllp_crc_new_c32_nst_i_2_; + wire com_llm_llm_rx_top_llm_rx_dllp_crc_new_c32_nst_i_1_; + wire com_llm_llm_rx_top_llm_rx_dllp_crc_new_c32_1_i_0_0_; + wire com_llm_llm_rx_top_llm_rx_dllp_crc_rx_dllp_d_31__2607; + wire com_llm_llm_rx_top_llm_rx_dllp_crc_rx_dllp_d_30__2608; + wire com_llm_llm_rx_top_llm_rx_dllp_crc_rx_dllp_d_29__2609; + wire com_llm_llm_rx_top_llm_rx_dllp_crc_rx_dllp_d_28__2610; + wire com_llm_llm_rx_top_llm_rx_dllp_crc_rx_dllp_d_27__2611; + wire com_llm_llm_rx_top_llm_rx_dllp_crc_rx_dllp_d_26__2612; + wire com_llm_llm_rx_top_llm_rx_dllp_crc_new_c32_1_i_7_; + wire com_llm_llm_rx_top_llm_rx_dllp_crc_new_c32_st_i_6_; + wire com_llm_llm_rx_top_llm_rx_dllp_crc_new_c32_1_i_5_; + wire com_llm_llm_rx_top_llm_rx_dllp_crc_new_c32_1_i_4_; + wire com_llm_llm_rx_top_llm_rx_dllp_crc_new_c32_1_i_3_; + wire com_llm_llm_rx_top_llm_rx_dllp_crc_new_c32_st_i_2_; + wire com_llm_llm_rx_top_llm_rx_dllp_crc_new_c32_st_i_1_; + wire com_llm_llm_rx_top_llm_rx_dllp_crc_new_c32_1_i_0_; + wire com_llm_llm_rx_top_llm_rx_dllp_crc_new_c32_nst_i_15_; + wire com_llm_llm_rx_top_llm_rx_dllp_crc_new_c32_nst_i_14_; + wire com_llm_llm_rx_top_llm_rx_dllp_crc_new_c32_1_i_0_13_; + wire com_llm_llm_rx_top_llm_rx_dllp_crc_new_c32_1_i_0_12_; + wire com_llm_llm_rx_top_llm_rx_dllp_crc_new_c32_nst_i_11_; + wire com_llm_llm_rx_top_llm_rx_dllp_crc_new_c32_nst_i_10_; + wire com_llm_llm_rx_top_llm_rx_dllp_crc_new_c32_1_i_0_9_; + wire com_llm_llm_rx_top_llm_rx_dllp_crc_new_c32_st_i_15_; + wire com_llm_llm_rx_top_llm_rx_dllp_crc_new_c32_st_i_14_; + wire com_llm_llm_rx_top_llm_rx_dllp_crc_new_c32_1_i_13_; + wire com_llm_llm_rx_top_llm_rx_dllp_crc_new_c32_1_i_12_; + wire com_llm_llm_rx_top_llm_rx_dllp_crc_new_c32_st_i_11_; + wire com_llm_llm_rx_top_llm_rx_dllp_crc_new_c32_st_i_10_; + wire com_llm_llm_rx_top_llm_rx_dllp_crc_new_c32_1_i_9_; + wire com_llm_llm_rx_top_llm_rx_dllp_crc_new_c32_st_i_8_; + wire com_llm_llm_rx_top_llm_rx_dllp_crc_N_87608_i_2613; + wire com_llm_llm_rx_top_llm_rx_dllp_crc_fr_straddle_2614; + wire com_llm_llm_rx_top_llm_rx_dllp_crc_N_27; + wire com_llm_llm_rx_top_llm_rx_dllp_crc_N_3; + wire com_llm_llm_rx_top_llm_rx_dllp_crc_N_11; + wire com_llm_llm_rx_top_llm_rx_dllp_crc_N_19; + wire com_llm_llm_rx_top_llm_rx_dllp_crc_N_35; + wire com_llm_llm_rx_top_llm_rx_dllp_crc_N_43; + wire com_llm_llm_rx_top_llm_rx_dllp_crc_N_51; + wire com_llm_llm_rx_top_llm_rx_dllp_crc_N_59; + wire com_llm_llm_rx_top_llm_rx_dllp_crc_llm_rx_crc16_d32_st_new_c32_1_1_7__2615; + wire com_llm_llm_rx_top_llm_rx_dllp_crc_llm_rx_crc16_d32_st_new_c32_1_1_5__2616; + wire com_llm_llm_rx_top_llm_rx_dllp_crc_llm_rx_crc16_d32_st_new_c32_1_2_4__2617; + wire com_llm_llm_rx_top_llm_rx_dllp_crc_llm_rx_crc16_d32_st_new_c32_1_1_3__2618; + wire com_llm_llm_rx_top_llm_rx_dllp_crc_llm_rx_crc16_d32_st_new_c32_1_2_2__2619; + wire com_llm_llm_rx_top_llm_rx_dllp_crc_llm_rx_crc16_d32_st_new_c32_1_1_1__2620; + wire com_llm_llm_rx_top_llm_rx_dllp_crc_llm_rx_crc16_d32_st_new_c32_1_1_0_; + wire com_llm_llm_rx_top_llm_rx_dllp_crc_llm_rx_crc16_d32_st_new_c32_1_2_15__2621; + wire com_llm_llm_rx_top_llm_rx_dllp_crc_llm_rx_crc16_d32_st_new_c32_1_1_13__2622; + wire com_llm_llm_rx_top_llm_rx_dllp_crc_llm_rx_crc16_d32_st_new_c32_1_1_11__2623; + wire com_llm_llm_rx_top_llm_rx_dllp_crc_llm_rx_crc16_d32_st_new_c32_1_1_10__2624; + wire com_llm_llm_rx_top_llm_rx_dllp_crc_llm_rx_crc16_d32_st_new_c32_1_1_9__2625; + wire com_llm_llm_rx_top_llm_rx_dllp_crc_llm_rx_crc16_d32_st_new_c32_1_2_8__2626; + wire com_llm_llm_rx_top_llm_rx_dllp_crc_llm_rx_crc16_d32_nst_new_c32_1_1_8__2627; + wire com_llm_llm_rx_top_llm_rx_dllp_crc_llm_rx_crc16_d32_nst_new_c32_1_0_7__2628; + wire com_llm_llm_rx_top_llm_rx_dllp_crc_llm_rx_crc16_d32_nst_new_c32_1_1_5__2629; + wire com_llm_llm_rx_top_llm_rx_dllp_crc_llm_rx_crc16_d32_nst_new_c32_1_2_4__2630; + wire com_llm_llm_rx_top_llm_rx_dllp_crc_llm_rx_crc16_d32_nst_new_c32_1_1_3__2631; + wire com_llm_llm_rx_top_llm_rx_dllp_crc_llm_rx_crc16_d32_nst_new_c32_1_0_2__2632; + wire com_llm_llm_rx_top_llm_rx_dllp_crc_llm_rx_crc16_d32_nst_new_c32_1_1_1__2633; + wire com_llm_llm_rx_top_llm_rx_dllp_crc_llm_rx_crc16_d32_nst_new_c32_1_1_0_; + wire com_llm_llm_rx_top_llm_rx_dllp_crc_llm_rx_crc16_d32_nst_new_c32_1_2_15__2634; + wire com_llm_llm_rx_top_llm_rx_dllp_crc_llm_rx_crc16_d32_nst_new_c32_1_1_13__2635; + wire com_llm_llm_rx_top_llm_rx_dllp_crc_llm_rx_crc16_d32_nst_new_c32_1_0_12__2636; + wire com_llm_llm_rx_top_llm_rx_dllp_crc_llm_rx_crc16_d32_nst_new_c32_1_1_11__2637; + wire com_llm_llm_rx_top_llm_rx_dllp_crc_llm_rx_crc16_d32_nst_new_c32_1_2_10__2638; + wire com_llm_llm_rx_top_llm_rx_dllp_crc_llm_rx_crc16_d32_nst_new_c32_1_1_9__2639; + wire com_llm_llm_rx_top_llm_rx_dllp_decode_cmml_rpm_ra_3_0_a2_0_a2_0_a3_0_a2_1; + wire com_llm_llm_rx_top_llm_rx_dllp_decode_link_li1_cpl_rcv_3_1_0; + wire com_llm_llm_rx_top_llm_rx_dllp_decode_N_56536; + wire com_llm_llm_rx_top_llm_rx_dllp_decode_N_56229_i; + wire com_llm_llm_rx_top_llm_rx_dllp_decode_N_16043_i; + wire com_llm_llm_rx_top_llm_rx_dllp_decode_cmml_rpm_ra_3; + wire com_llm_llm_rx_top_llm_rx_dllp_decode_N_16048_i; + wire com_llm_llm_rx_top_llm_rx_dllp_decode_link_li1_cpl_rcv_3; + wire com_llm_llm_rx_top_llm_rx_dllp_decode_link_li1_np_rcv_3; + wire com_llm_llm_rx_top_llm_rx_dllp_decode_link_li1_p_rcv_3; + wire com_llm_llm_rx_top_llm_rx_dllp_decode_N_85888_i_2640; + wire com_llm_llm_rx_top_llm_rx_dllp_decode_lnk_rfc_header_6_N_6; + wire com_llm_llm_rx_top_llm_rx_dllp_decode_lnk_rfc_header_5_N_6; + wire com_llm_llm_rx_top_llm_rx_dllp_decode_lnk_rfc_header_4_N_6; + wire com_llm_llm_rx_top_llm_rx_dllp_decode_lnk_rfc_header_3_N_6; + wire com_llm_llm_rx_top_llm_rx_dllp_decode_lnk_rfc_header_2_N_6; + wire com_llm_llm_rx_top_llm_rx_dllp_decode_lnk_rfc_header_1_N_6; + wire com_llm_llm_rx_top_llm_rx_dllp_decode_lnk_rfc_header_0_N_6; + wire com_llm_llm_rx_top_llm_rx_dllp_decode_GND_2641; + wire com_llm_llm_rx_top_llm_rx_dllp_decode_VCC_2642; + wire com_llm_llm_rx_top_llm_rx_dllp_decode_lnk_rfc_header_N_6; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_un6_crc32_res_ok_0_2643; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_un6_crc32_res_ok_1_2644; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_un6_crc32_res_ok_2_2645; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_un6_crc32_res_ok_3_2646; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_un6_crc32_res_ok_4_2647; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_un6_crc32_res_ok_5_2648; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_un6_crc32_res_ok_6_2649; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_VCC_2650; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_un3_crc32_res_ok_0_2651; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_un3_crc32_res_ok_1_2652; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_un3_crc32_res_ok_2_2653; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_un3_crc32_res_ok_3_2654; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_un3_crc32_res_ok_4_2655; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_un3_crc32_res_ok_5_2656; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_un3_crc32_res_ok_6_2657; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_un6_crc32_res_ok_7_2658; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_un3_crc32_res_ok_7_2659; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_RX_TLP_CRC_ERR_N_6_i_0_m2_0_1_2660; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_N_31569_i; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_N_31572_i; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_un1_RX_RSRC_DSC_N17_0_0_0_2661; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_N_31560_i; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_N_31558_i; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_rx_tlp_eof_nq6_0_0_o2_2662; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_RX_TLP_CRC_ERR_N_6_i_0_o3_0_2663; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_I_28; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_I_28_0; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_GND_2664; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_rx_tlp_nullified_q_i_2665; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rsrc_dsc_nd_2666; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_rx_tlp_nullified_q_2667; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_rx_tlp_vld_l_nq_2668; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_rx_tlp_vld_h_nq_2669; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_start_high_latch_qq_2670; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_aligned_aligned_3; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_aligned_aligned_2671; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_frame_error_latch_q_2672; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_N_16213_i; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_tlp_64; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_tlp_64_q_2673; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_unaligned_aligned_3; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_unaligned_aligned_2674; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_aligned_unaligned_3; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_aligned_unaligned_2675; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_N_87780_i_2676; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_rx_reof_nd_2677; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_RX_REOF_N_5; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_dw_3; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_dw_3q_2678; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_N_85331_i_2679; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_1__2680; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_18__2681; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_17__2682; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_16__2683; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_15__2684; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_11__2685; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_10__2686; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_9__2687; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_8__2688; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_7__2689; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_5__2690; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_4__2691; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_33__2692; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_31__2693; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_30__2694; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_29__2695; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_28__2696; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_27__2697; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_26__2698; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_25__2699; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_24__2700; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_23__2701; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_22__2702; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_20__2703; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_19__2704; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_48__2705; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_47__2706; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_43__2707; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_42__2708; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_41__2709; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_40__2710; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_39__2711; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_37__2712; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_36__2713; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_rx_data_q_7__2714; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_63__2715; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_rx_data_q_6__2716; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_62__2717; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_rx_data_q_5__2718; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_61__2719; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_rx_data_q_4__2720; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_60__2721; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_rx_data_q_3__2722; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_59__2723; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_58__2724; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_rx_data_q_1__2725; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_57__2726; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_rx_data_q_0__2727; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_56__2728; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_55__2729; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_54__2730; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_53__2731; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_52__2732; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_51__2733; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_50__2734; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_49__2735; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d64_10__2736; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d64_3__2737; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d64_2__2738; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d64_1__2739; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_tlp_nullified_latch_2740; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_frame_error_latch_2741; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_start_high_latch_3; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_end_low_latch_2742; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_N_59482_i_2743; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rsof_nd_2744; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_N_31582_i_0; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_tlp_in_progress_2745; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_N_87782_i_2746; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_rx_tlp_sof_nqq_2747; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_N_87781_i_2748; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_rx_tlp_eof_nq_2749; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_rx_tlp_sof_nq_i_2750; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_rx_tlp_sof_nq_2751; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_end_low_latch_3; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_N_85330_i_2752; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_N_85330_i_1_2753; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_RX_TLP_CRC_ERR_N_6_i_0_o3_2754; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_RX_TLP_CRC_ERR_N_6_i_0_m2_0_2755; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_un1_RX_RSRC_DSC_N17_0_0_m2_0_2756; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_N_99_0; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_N_99; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_N_103; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_N_102; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_un3_crc32_res_ok_7_and; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_un3_crc32_res_ok_6_and; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_un3_crc32_res_ok_5_and; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_un3_crc32_res_ok_4_and; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_un3_crc32_res_ok_3_and; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_un3_crc32_res_ok_2_and; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_un3_crc32_res_ok_1_and; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_un3_crc32_res_ok_0_and; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_un6_crc32_res_ok_7_and; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_un6_crc32_res_ok_6_and; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_un6_crc32_res_ok_5_and; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_un6_crc32_res_ok_4_and; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_un6_crc32_res_ok_3_and; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_un6_crc32_res_ok_2_and; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_un3_crc32_res_ok_5_and_1_0; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_un6_crc32_res_ok_1_and; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_un6_crc32_res_ok_1_and_1; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_un6_crc32_res_ok_0_and; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_N_3_0; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_N_11_0; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_N_19_0; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_N_27_0; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_N_35_0; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_N_43_0; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_N_51_0; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_N_59_0; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_N_67_0; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_N_75_0; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_N_83_0; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_N_91_0; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_N_107_0; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_N_115_0; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_N_123_0; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_N_3; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_N_7; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_N_6; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_N_11; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_N_15; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_N_14; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_N_19; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_N_23; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_N_22; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_N_27; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_N_31; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_N_30; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_N_35; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_N_39; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_N_38; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_N_43; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_N_47; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_N_46; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_N_51; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_N_55; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_N_54; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_N_59; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_N_63; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_N_62; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_N_67; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_N_71; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_N_70; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_N_75; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_N_79; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_N_78; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_N_83; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_N_87; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_N_86; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_N_91; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_N_95; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_N_94; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_N_107; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_N_111; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_N_110; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_N_115; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_N_119; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_N_118; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_N_123; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_N_127; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_N_126; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d16_new_c16_1_0_9__2757; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d16_new_c16_1_1_4__2758; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d16_new_c16_1_1_3__2759; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d16_new_c16_1_0_26__2760; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d16_new_c16_1_19__2761; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d16_new_c16_1_0_17__2762; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d16_new_c16_1_1_16__2763; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d16_new_c16_1_20__2764; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d16_new_c16_1_17__2765; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d16_new_c16_1_18__2766; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d16_new_c16_1_11__2767; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_1_17__2768; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_1_0_6__2769; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_1_0_7__2770; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_3_17__2771; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_2_24__2772; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_1_5__2773; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_1_9__2774; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_0_8__2775; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_2_2__2776; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_0_30__2777; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_2_0__2778; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_23_39373_2779; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_4_29__2780; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_2_29__2781; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_0_13__2782; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_4_24__2783; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_6_1__2784; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_5__2785; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_7__2786; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_3_28__2787; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_2_28__2788; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_1_4__2789; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_0_4__2790; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_1_14__2791; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_6_9__2792; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_1_7__2793; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_1_16__2794; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_14__2795; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_5_14__2796; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_2_14__2797; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_4_13__2798; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_3_13__2799; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_5_12__2800; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_2_12__2801; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_5_11__2802; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_4_11__2803; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_3_11__2804; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_11_39376_2805; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_3_10__2806; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_2_10__2807; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_8__2808; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_7_8__2809; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_4_8__2810; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_6_7__2811; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_4_7__2812; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_3_7__2813; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_7_5__2814; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_6_5__2815; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_5_5__2816; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_4_4__2817; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_5_3__2818; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_4_3__2819; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_3_3__2820; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_2_2_; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_2__2821; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_4_2__2822; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_3_2__2823; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_1__2824; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_3_1__2825; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_2_1_; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_4_0__2826; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_3_0__2827; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_7_29__2828; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_6_29__2829; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_6_28__2830; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_4_27__2831; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_2_27__2832; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_3_26__2833; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_2_26__2834; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_6_25__2835; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_5_25__2836; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_2_25__2837; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_1_25__2838; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_6_24__2839; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_5_24__2840; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_10__2841; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_4_23__2842; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_3_23__2843; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_6_22__2844; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_5_22__2845; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_4_22__2846; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_3_22__2847; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_12__2848; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_5_21__2849; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_2_21__2850; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_6_17__2851; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_2_17__2852; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_5_16__2853; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_4_16__2854; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_3_15__2855; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_2_15__2856; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_2_31__2857; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_2_14_; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_26__2858; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_4_30__2859; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_3_30__2860; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_1_19__2861; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_7_27__2862; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_20__2863; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_18__2864; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_3_18__2865; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_1_18__2866; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_1_0_19__2867; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_4_20__2868; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_1_0_20__2869; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_6__2870; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_1_6__2871; + wire com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_1_0_9__2872; + wire com_llm_llm_rx_top_llm_rx_tlp_sm_VCC_2873; + wire com_llm_llm_rx_top_llm_rx_tlp_sm_tlp_diff_tsn_cry_0_2874; + wire com_llm_llm_rx_top_llm_rx_tlp_sm_tlp_diff_tsn_cry_1_2875; + wire com_llm_llm_rx_top_llm_rx_tlp_sm_tlp_diff_tsn_cry_2_2876; + wire com_llm_llm_rx_top_llm_rx_tlp_sm_tlp_diff_tsn_cry_3_2877; + wire com_llm_llm_rx_top_llm_rx_tlp_sm_tlp_diff_tsn_cry_4_2878; + wire com_llm_llm_rx_top_llm_rx_tlp_sm_tlp_diff_tsn_cry_5_2879; + wire com_llm_llm_rx_top_llm_rx_tlp_sm_tlp_diff_tsn_cry_6_2880; + wire com_llm_llm_rx_top_llm_rx_tlp_sm_tlp_diff_tsn_cry_7_2881; + wire com_llm_llm_rx_top_llm_rx_tlp_sm_tlp_diff_tsn_cry_8_2882; + wire com_llm_llm_rx_top_llm_rx_tlp_sm_tlp_diff_tsn_cry_9_2883; + wire com_llm_llm_rx_top_llm_rx_tlp_sm_tlp_diff_tsn_cry_10_2884; + wire com_llm_llm_rx_top_llm_rx_tlp_sm_tlp_diff_tsn_axb_11_2885; + wire com_llm_llm_rx_top_llm_rx_tlp_sm_N_59418; + wire com_llm_llm_rx_top_llm_rx_tlp_sm_N_56982; + wire com_llm_llm_rx_top_llm_rx_tlp_sm_N_58447; + wire com_llm_llm_rx_top_llm_rx_tlp_sm_tsn_eq; + wire com_llm_llm_rx_top_llm_rx_tlp_sm_GND_2886; + wire com_llm_llm_rx_top_llm_rx_tlp_sm_reg_rx_tlp_tsn_err_lrx_3; + wire com_llm_llm_rx_top_llm_rx_tlp_sm_reg_rx_tlp_tsn_err_lrx_2887; + wire com_llm_llm_rx_top_llm_rx_tlp_sm_link_up_2888; + wire com_llm_llm_rx_top_llm_rx_tlp_sm_lnk_reof_n22_i_2889; + wire com_llm_llm_rx_top_llm_rx_tlp_sm_N_39351_i; + wire com_llm_llm_rx_top_llm_rx_tlp_sm_N_16443_i; + wire com_llm_llm_rx_top_llm_rx_tlp_sm_reg_rx_tlp_tsn_err_lrfc_2890; + wire com_llm_llm_rx_top_llm_rx_tlp_sm_N_59478_i_2891; + wire com_llm_llm_rx_top_llm_rx_tlp_sm_N_85556_i_2892; + wire com_llm_llm_rx_top_llm_rx_tlp_sm_reg_rx_tlp_tsn_dup_3; + wire com_llm_llm_rx_top_llm_rx_tlp_sm_tlp_ip_q18_i_2893; + wire com_llm_llm_rx_top_llm_rx_tlp_sm_reg_rx_tlp_tsn_err_t_2894; + wire com_llm_llm_rx_top_llm_rx_tlp_sm_N_85525_i_2895; + wire com_llm_llm_rx_top_llm_rx_tlp_sm_N_85557_i_2896; + wire com_llm_llm_rx_top_llm_rx_tlp_sm_tlp_range_error17; + wire com_llm_llm_rx_top_llm_rx_tlp_sm_tlp_range_error_2897; + wire com_llm_llm_rx_top_llm_rx_tlp_sm_N_85574_i_2898; + wire com_llm_llm_rx_top_llm_rx_tlp_sm_tlp_ip_q18; + wire com_llm_llm_rx_top_llm_rx_tlp_sm_tlp_ip_q_2899; + wire com_llm_llm_rx_top_llm_rx_tlp_sm_N_27; + wire com_llm_llm_rx_top_llm_rx_tlp_sm_tlp_diff_tsn_axb_10_2900; + wire com_llm_llm_rx_top_llm_rx_tlp_sm_tlp_diff_tsn_axb_9_2901; + wire com_llm_llm_rx_top_llm_rx_tlp_sm_tlp_diff_tsn_axb_8_2902; + wire com_llm_llm_rx_top_llm_rx_tlp_sm_tlp_diff_tsn_axb_7_2903; + wire com_llm_llm_rx_top_llm_rx_tlp_sm_tlp_diff_tsn_axb_6_2904; + wire com_llm_llm_rx_top_llm_rx_tlp_sm_tlp_diff_tsn_axb_5_2905; + wire com_llm_llm_rx_top_llm_rx_tlp_sm_tlp_diff_tsn_axb_4_2906; + wire com_llm_llm_rx_top_llm_rx_tlp_sm_tlp_diff_tsn_axb_3_2907; + wire com_llm_llm_rx_top_llm_rx_tlp_sm_tlp_diff_tsn_axb_2_2908; + wire com_llm_llm_rx_top_llm_rx_tlp_sm_tlp_diff_tsn_axb_1_2909; + wire com_llm_llm_rx_top_llm_rx_tlp_sm_tlp_diff_tsn_axb_0_2910; + wire com_llm_llm_rx_top_llm_rx_tlp_sm_N_3; + wire com_llm_llm_rx_top_llm_rx_tlp_sm_N_11; + wire com_llm_llm_rx_top_llm_rx_tlp_sm_N_19; + wire com_llm_llm_rx_top_llm_rx_tlp_sm_N_35; + wire com_llm_llm_rx_top_llm_rx_tlp_sm_N_43; + wire com_llm_llm_common_N_56202_i_i; + wire com_llm_llm_common_val_3_7_; + wire com_llm_llm_common_val_2_6_; + wire com_llm_llm_common_val_3_5_; + wire com_llm_llm_common_val_3_4_; + wire com_llm_llm_common_val_3_3_; + wire com_llm_llm_common_val_2_2_; + wire com_llm_llm_common_val_2_1_; + wire com_llm_llm_common_val_3_0_; + wire com_llm_llm_common_replay_table_N_86017_i_2911; + wire com_llm_llm_common_replay_table_lat_o_1c_i; + wire com_llm_llm_common_replay_table_N_86015_i_2912; + wire com_llm_llm_common_replay_table_N_56486_i_0_i_2913; + wire com_llm_llm_common_ack_synch_table_lat_o_1c_i; + wire com_llm_llm_common_ack_synch_table_lat_o_1c_0_i; + wire com_llm_llm_common_ack_synch_table_N_56484_i_0_i_2914; + wire com_llm_llm_common_llm_link_sm_llm_link_main_sm_link_fcp_rcvq; + wire com_llm_llm_common_llm_link_sm_llm_link_main_sm_link_fcnp_rcvq; + wire com_llm_llm_common_llm_link_sm_llm_link_main_sm_link_fccpl_rcvq; + wire com_llm_llm_common_llm_link_sm_llm_link_main_sm_N_60893; + wire com_llm_llm_common_llm_link_sm_llm_link_main_sm_N_56977_i; + wire com_llm_llm_common_llm_link_sm_llm_link_main_sm_N_58438; + wire com_llm_llm_common_llm_link_sm_llm_link_main_sm_N_56934_i; + wire com_llm_llm_common_llm_link_sm_llm_link_main_sm_N_87093_i_2915; + wire com_llm_llm_common_llm_link_sm_llm_link_main_sm_N_46610_i; + wire com_llm_llm_common_llm_link_sm_llm_link_main_sm_N_46513_i; + wire com_llm_llm_common_llm_link_sm_llm_link_main_sm_N_51954_i; + wire com_llm_llm_common_llm_link_sm_llm_link_main_sm_N_16055_i; + wire com_llm_llm_common_llm_link_sm_llm_link_main_sm_sticky0_q5_i_2916; + wire com_llm_llm_common_llm_link_sm_llm_link_main_sm_sticky0_qc_2917; + wire com_llm_llm_common_llm_link_sm_llm_link_main_sm_sticky1_q5_i_2918; + wire com_llm_llm_common_llm_link_sm_llm_link_main_sm_sticky1_qc_2919; + wire com_llm_llm_common_llm_link_sm_llm_link_main_sm_sticky2_q5_i_2920; + wire com_llm_llm_common_llm_link_sm_llm_link_main_sm_sticky2_qc_2921; + wire com_llm_llm_common_llm_common_reg_replay_timeout_flag; + wire com_llm_llm_common_llm_common_reg_ack_pending; + wire com_llm_llm_common_llm_common_reg_nak_pending; + wire com_llm_llm_common_llm_common_reg_N_58792; + wire com_llm_llm_common_llm_common_reg_nak_pending_8_2; + wire com_llm_llm_common_llm_common_reg_un3_ttrans_st_hiwater_cry_0_2922; + wire com_llm_llm_common_llm_common_reg_un3_ttrans_st_hiwater_cry_1_2923; + wire com_llm_llm_common_llm_common_reg_un3_ttrans_st_hiwater_cry_2_2924; + wire com_llm_llm_common_llm_common_reg_un3_ttrans_st_hiwater_cry_3_2925; + wire com_llm_llm_common_llm_common_reg_un3_ttrans_st_hiwater_cry_4_2926; + wire com_llm_llm_common_llm_common_reg_un3_ttrans_st_hiwater_cry_5_2927; + wire com_llm_llm_common_llm_common_reg_un3_ttrans_st_hiwater_cry_6_2928; + wire com_llm_llm_common_llm_common_reg_un3_ttrans_st_hiwater_cry_7_2929; + wire com_llm_llm_common_llm_common_reg_un3_ttrans_st_hiwater_cry_8_2930; + wire com_llm_llm_common_llm_common_reg_un3_ttrans_st_hiwater_cry_9_2931; + wire com_llm_llm_common_llm_common_reg_un3_ttrans_st_hiwater_cry_10_2932; + wire com_llm_llm_common_llm_common_reg_VCC_2933; + wire com_llm_llm_common_llm_common_reg_un3_tmp_result_cry_0_2934; + wire com_llm_llm_common_llm_common_reg_un3_tmp_result_cry_1_2935; + wire com_llm_llm_common_llm_common_reg_un3_tmp_result_cry_2_2936; + wire com_llm_llm_common_llm_common_reg_un3_tmp_result_cry_3_2937; + wire com_llm_llm_common_llm_common_reg_un3_tmp_result_cry_4_2938; + wire com_llm_llm_common_llm_common_reg_un3_tmp_result_cry_5_2939; + wire com_llm_llm_common_llm_common_reg_un3_tmp_result_cry_6_2940; + wire com_llm_llm_common_llm_common_reg_un3_tmp_result_cry_7_2941; + wire com_llm_llm_common_llm_common_reg_un3_tmp_result_cry_8_2942; + wire com_llm_llm_common_llm_common_reg_un3_tmp_result_cry_9_2943; + wire com_llm_llm_common_llm_common_reg_un3_tmp_result_cry_10_2944; + wire com_llm_llm_common_llm_common_reg_reg_tx_next_tsn_4_cry_0_2945; + wire com_llm_llm_common_llm_common_reg_reg_tx_next_tsn_4_cry_1_2946; + wire com_llm_llm_common_llm_common_reg_reg_tx_next_tsn_4_cry_2_2947; + wire com_llm_llm_common_llm_common_reg_reg_tx_next_tsn_4_cry_3_2948; + wire com_llm_llm_common_llm_common_reg_reg_tx_next_tsn_4_cry_4_2949; + wire com_llm_llm_common_llm_common_reg_reg_tx_next_tsn_4_cry_5_2950; + wire com_llm_llm_common_llm_common_reg_reg_tx_next_tsn_4_cry_6_2951; + wire com_llm_llm_common_llm_common_reg_reg_tx_next_tsn_4_cry_7_2952; + wire com_llm_llm_common_llm_common_reg_reg_tx_next_tsn_4_cry_8_2953; + wire com_llm_llm_common_llm_common_reg_reg_tx_next_tsn_4_cry_9_2954; + wire com_llm_llm_common_llm_common_reg_reg_tx_next_tsn_4_cry_10_2955; + wire com_llm_llm_common_llm_common_reg_lnk_sys_reset_n_0_a2_0_a2_0_a2_0_a2_2956; + wire com_llm_llm_common_llm_common_reg_N_22173_i; + wire com_llm_llm_common_llm_common_reg_N_58798_1; + wire com_llm_llm_common_llm_common_reg_N_22175_i; + wire com_llm_llm_common_llm_common_reg_un3_ttrans_st_hiwater_axb_11_2957; + wire com_llm_llm_common_llm_common_reg_un3_tmp_result_axb_11_2958; + wire com_llm_llm_common_llm_common_reg_N_56212_i; + wire com_llm_llm_common_llm_common_reg_reg_tx_next_tsn_4_axb_11_2959; + wire com_llm_llm_common_llm_common_reg_reg_tx_next_tsn_4_axb_10_2960; + wire com_llm_llm_common_llm_common_reg_reg_tx_next_tsn_4_axb_9_2961; + wire com_llm_llm_common_llm_common_reg_reg_tx_next_tsn_4_axb_8_2962; + wire com_llm_llm_common_llm_common_reg_reg_tx_next_tsn_4_axb_7_2963; + wire com_llm_llm_common_llm_common_reg_reg_tx_next_tsn_4_axb_6_2964; + wire com_llm_llm_common_llm_common_reg_reg_tx_next_tsn_4_axb_5_2965; + wire com_llm_llm_common_llm_common_reg_reg_tx_next_tsn_4_axb_4_2966; + wire com_llm_llm_common_llm_common_reg_reg_tx_next_tsn_4_axb_3_2967; + wire com_llm_llm_common_llm_common_reg_reg_tx_next_tsn_4_axb_2_2968; + wire com_llm_llm_common_llm_common_reg_reg_tx_next_tsn_4_axb_1_2969; + wire com_llm_llm_common_llm_common_reg_N_60731_i_2970; + wire com_llm_llm_common_llm_common_reg_N_60732_i_2971; + wire com_llm_llm_common_llm_common_reg_N_60733_i_2972; + wire com_llm_llm_common_llm_common_reg_N_60734_i_2973; + wire com_llm_llm_common_llm_common_reg_N_60735_i_2974; + wire com_llm_llm_common_llm_common_reg_N_60736_i_2975; + wire com_llm_llm_common_llm_common_reg_N_60737_i_2976; + wire com_llm_llm_common_llm_common_reg_N_60738_i_2977; + wire com_llm_llm_common_llm_common_reg_N_60739_i_2978; + wire com_llm_llm_common_llm_common_reg_N_60740_i_2979; + wire com_llm_llm_common_llm_common_reg_N_60741_i_2980; + wire com_llm_llm_common_llm_common_reg_N_60742_i_2981; + wire com_llm_llm_common_llm_common_reg_N_58446_2; + wire com_llm_llm_common_llm_common_reg_N_62715_1_i; + wire com_llm_llm_common_llm_common_reg_N_58796; + wire com_llm_llm_common_llm_common_reg_ANSeqNum_Eq_AckdSeq_wire; + wire com_llm_llm_common_llm_common_reg_GND_2982; + wire com_llm_llm_common_llm_common_reg_reg_tx_update_clr_q_2983; + wire com_llm_llm_common_llm_common_reg_reg_rx_dllp_nak_vld_q_2984; + wire com_llm_llm_common_llm_common_reg_reg_rx_dllp_ack_vld_q_2985; + wire com_llm_llm_common_llm_common_reg_NxtTxTSN_ANSeqNum_wire_2986; + wire com_llm_llm_common_llm_common_reg_ANSeqNum_AckdSeq_wire_2987; + wire com_llm_llm_common_llm_common_reg_ANSeqNum_Eq_AckdSeq_5; + wire com_llm_llm_common_llm_common_reg_ANSeqNum_Eq_AckdSeq_2988; + wire com_llm_llm_common_llm_common_reg_next_eq_mark_q_3; + wire com_llm_llm_common_llm_common_reg_next_eq_mark_q_2989; + wire com_llm_llm_common_llm_common_reg_curr_eq_mark_q_3; + wire com_llm_llm_common_llm_common_reg_curr_eq_mark_q_2990; + wire com_llm_llm_common_llm_common_reg_rx_tsn_eq_sent_tsn_3; + wire com_llm_llm_common_llm_common_reg_rx_tsn_eq_sent_tsn_2991; + wire com_llm_llm_common_llm_common_reg_un3_ttrans_st_hiwater_s_11_2992; + wire com_llm_llm_common_llm_common_reg_un3_tmp_result_s_11_2993; + wire com_llm_llm_common_llm_common_reg_N_85483_i_2994; + wire com_llm_llm_common_llm_common_reg_N_87517_i_2995; + wire com_llm_llm_common_llm_common_reg_N_87591_i_2996; + wire com_llm_llm_common_llm_common_reg_reg_dllr_in_progress17; + wire com_llm_llm_common_llm_common_reg_N_60707_i_2997; + wire com_llm_llm_common_llm_common_reg_N_60708_i_2998; + wire com_llm_llm_common_llm_common_reg_N_60709_i_2999; + wire com_llm_llm_common_llm_common_reg_N_60710_i_3000; + wire com_llm_llm_common_llm_common_reg_N_60711_i_3001; + wire com_llm_llm_common_llm_common_reg_N_60712_i_3002; + wire com_llm_llm_common_llm_common_reg_N_60713_i_3003; + wire com_llm_llm_common_llm_common_reg_N_60714_i_3004; + wire com_llm_llm_common_llm_common_reg_N_60715_i_3005; + wire com_llm_llm_common_llm_common_reg_N_60716_i_3006; + wire com_llm_llm_common_llm_common_reg_N_60717_i_3007; + wire com_llm_llm_common_llm_common_reg_N_87516_i; + wire com_llm_llm_common_llm_common_reg_N_60718_i_3008; + wire com_llm_llm_common_llm_common_reg_reg_tx_dllp_ack_vld18; + wire com_llm_llm_common_llm_common_reg_N_58434_i_3009; + wire com_llm_llm_common_llm_common_reg_N_15705_i; + wire com_llm_llm_common_llm_common_reg_N_85479_i_3010; + wire com_llm_llm_common_llm_common_reg_replay_ip21; + wire com_llm_llm_common_llm_common_reg_replay_ip_3011; + wire com_llm_llm_common_llm_common_reg_N_60719_i_3012; + wire com_llm_llm_common_llm_common_reg_N_60720_i_3013; + wire com_llm_llm_common_llm_common_reg_N_60721_i_3014; + wire com_llm_llm_common_llm_common_reg_N_60722_i_3015; + wire com_llm_llm_common_llm_common_reg_N_60723_i_3016; + wire com_llm_llm_common_llm_common_reg_N_60724_i_3017; + wire com_llm_llm_common_llm_common_reg_N_60725_i_3018; + wire com_llm_llm_common_llm_common_reg_N_60726_i_3019; + wire com_llm_llm_common_llm_common_reg_N_60727_i_3020; + wire com_llm_llm_common_llm_common_reg_N_60728_i_3021; + wire com_llm_llm_common_llm_common_reg_N_60729_i_3022; + wire com_llm_llm_common_llm_common_reg_N_87603_i_3023; + wire com_llm_llm_common_llm_common_reg_N_60730_i_3024; + wire com_llm_llm_common_llm_common_reg_N_60743_i_3025; + wire com_llm_llm_common_llm_common_reg_N_60744_i_3026; + wire com_llm_llm_common_llm_common_reg_N_60745_i_3027; + wire com_llm_llm_common_llm_common_reg_N_60746_i_3028; + wire com_llm_llm_common_llm_common_reg_N_60747_i_3029; + wire com_llm_llm_common_llm_common_reg_N_60748_i_3030; + wire com_llm_llm_common_llm_common_reg_N_60749_i_3031; + wire com_llm_llm_common_llm_common_reg_N_60750_i_3032; + wire com_llm_llm_common_llm_common_reg_N_60751_i_3033; + wire com_llm_llm_common_llm_common_reg_N_60752_i_3034; + wire com_llm_llm_common_llm_common_reg_N_60753_i_3035; + wire com_llm_llm_common_llm_common_reg_N_87604_i_3036; + wire com_llm_llm_common_llm_common_reg_N_60754_i_3037; + wire com_llm_llm_common_llm_common_reg_N_62715_i_i_3038; + wire com_llm_llm_common_llm_common_reg_N_62715_i; + wire com_llm_llm_common_llm_common_reg_N_27_2; + wire com_llm_llm_common_llm_common_reg_N_27_1; + wire com_llm_llm_common_llm_common_reg_N_27_0; + wire com_llm_llm_common_llm_common_reg_N_27; + wire com_llm_llm_common_llm_common_reg_reg_tx_next_tsn_4_axb_0_3039; + wire com_llm_llm_common_llm_common_reg_un3_tmp_result_axb_10_3040; + wire com_llm_llm_common_llm_common_reg_un3_tmp_result_axb_9_3041; + wire com_llm_llm_common_llm_common_reg_un3_tmp_result_axb_8_3042; + wire com_llm_llm_common_llm_common_reg_un3_tmp_result_axb_7_3043; + wire com_llm_llm_common_llm_common_reg_un3_tmp_result_axb_6_3044; + wire com_llm_llm_common_llm_common_reg_un3_tmp_result_axb_5_3045; + wire com_llm_llm_common_llm_common_reg_un3_tmp_result_axb_4_3046; + wire com_llm_llm_common_llm_common_reg_un3_tmp_result_axb_3_3047; + wire com_llm_llm_common_llm_common_reg_un3_tmp_result_axb_2_3048; + wire com_llm_llm_common_llm_common_reg_un3_tmp_result_axb_1_3049; + wire com_llm_llm_common_llm_common_reg_un3_tmp_result_axb_0_3050; + wire com_llm_llm_common_llm_common_reg_un3_ttrans_st_hiwater_axb_10_3051; + wire com_llm_llm_common_llm_common_reg_un3_ttrans_st_hiwater_axb_9_3052; + wire com_llm_llm_common_llm_common_reg_un3_ttrans_st_hiwater_axb_8_3053; + wire com_llm_llm_common_llm_common_reg_un3_ttrans_st_hiwater_axb_7_3054; + wire com_llm_llm_common_llm_common_reg_un3_ttrans_st_hiwater_axb_6_3055; + wire com_llm_llm_common_llm_common_reg_un3_ttrans_st_hiwater_axb_5_3056; + wire com_llm_llm_common_llm_common_reg_un3_ttrans_st_hiwater_axb_4_3057; + wire com_llm_llm_common_llm_common_reg_un3_ttrans_st_hiwater_axb_3_3058; + wire com_llm_llm_common_llm_common_reg_un3_ttrans_st_hiwater_axb_2_3059; + wire com_llm_llm_common_llm_common_reg_un3_ttrans_st_hiwater_axb_1_3060; + wire com_llm_llm_common_llm_common_reg_un3_ttrans_st_hiwater_axb_0_3061; + wire com_llm_llm_common_llm_common_reg_N_3_2; + wire com_llm_llm_common_llm_common_reg_N_11_2; + wire com_llm_llm_common_llm_common_reg_N_19_2; + wire com_llm_llm_common_llm_common_reg_N_35_2; + wire com_llm_llm_common_llm_common_reg_N_43_2; + wire com_llm_llm_common_llm_common_reg_N_3_1; + wire com_llm_llm_common_llm_common_reg_N_11_1; + wire com_llm_llm_common_llm_common_reg_N_19_1; + wire com_llm_llm_common_llm_common_reg_N_35_1; + wire com_llm_llm_common_llm_common_reg_N_43_1; + wire com_llm_llm_common_llm_common_reg_N_3_0; + wire com_llm_llm_common_llm_common_reg_N_11_0; + wire com_llm_llm_common_llm_common_reg_N_19_0; + wire com_llm_llm_common_llm_common_reg_N_35_0; + wire com_llm_llm_common_llm_common_reg_N_43_0; + wire com_llm_llm_common_llm_common_reg_N_3; + wire com_llm_llm_common_llm_common_reg_N_11; + wire com_llm_llm_common_llm_common_reg_N_19; + wire com_llm_llm_common_llm_common_reg_N_35; + wire com_llm_llm_common_llm_common_reg_N_43; + wire com_llm_llm_common_llm_common_reg_compare_1_VCC_3062; + wire com_llm_llm_common_llm_common_reg_compare_1_result_cry_0_3063; + wire com_llm_llm_common_llm_common_reg_compare_1_result_cry_1_3064; + wire com_llm_llm_common_llm_common_reg_compare_1_result_cry_2_3065; + wire com_llm_llm_common_llm_common_reg_compare_1_result_cry_3_3066; + wire com_llm_llm_common_llm_common_reg_compare_1_result_cry_4_3067; + wire com_llm_llm_common_llm_common_reg_compare_1_result_cry_5_3068; + wire com_llm_llm_common_llm_common_reg_compare_1_result_cry_6_3069; + wire com_llm_llm_common_llm_common_reg_compare_1_result_cry_7_3070; + wire com_llm_llm_common_llm_common_reg_compare_1_result_cry_8_3071; + wire com_llm_llm_common_llm_common_reg_compare_1_result_cry_9_3072; + wire com_llm_llm_common_llm_common_reg_compare_1_result_cry_10_3073; + wire com_llm_llm_common_llm_common_reg_compare_1_result_axb_11_3074; + wire com_llm_llm_common_llm_common_reg_compare_1_result_axb_10_3075; + wire com_llm_llm_common_llm_common_reg_compare_1_result_axb_9_3076; + wire com_llm_llm_common_llm_common_reg_compare_1_result_axb_8_3077; + wire com_llm_llm_common_llm_common_reg_compare_1_result_axb_7_3078; + wire com_llm_llm_common_llm_common_reg_compare_1_result_axb_6_3079; + wire com_llm_llm_common_llm_common_reg_compare_1_result_axb_5_3080; + wire com_llm_llm_common_llm_common_reg_compare_1_result_axb_4_3081; + wire com_llm_llm_common_llm_common_reg_compare_1_result_axb_3_3082; + wire com_llm_llm_common_llm_common_reg_compare_1_result_axb_2_3083; + wire com_llm_llm_common_llm_common_reg_compare_1_result_axb_1_3084; + wire com_llm_llm_common_llm_common_reg_compare_1_result_axb_0_3085; + wire com_llm_llm_common_llm_common_reg_compare_2_VCC_3086; + wire com_llm_llm_common_llm_common_reg_compare_2_result_cry_0_3087; + wire com_llm_llm_common_llm_common_reg_compare_2_result_cry_1_3088; + wire com_llm_llm_common_llm_common_reg_compare_2_result_cry_2_3089; + wire com_llm_llm_common_llm_common_reg_compare_2_result_cry_3_3090; + wire com_llm_llm_common_llm_common_reg_compare_2_result_cry_4_3091; + wire com_llm_llm_common_llm_common_reg_compare_2_result_cry_5_3092; + wire com_llm_llm_common_llm_common_reg_compare_2_result_cry_6_3093; + wire com_llm_llm_common_llm_common_reg_compare_2_result_cry_7_3094; + wire com_llm_llm_common_llm_common_reg_compare_2_result_cry_8_3095; + wire com_llm_llm_common_llm_common_reg_compare_2_result_cry_9_3096; + wire com_llm_llm_common_llm_common_reg_compare_2_result_cry_10_3097; + wire com_llm_llm_common_llm_common_reg_compare_2_result_axb_11_3098; + wire com_llm_llm_common_llm_common_reg_compare_2_result_axb_10_3099; + wire com_llm_llm_common_llm_common_reg_compare_2_result_axb_9_3100; + wire com_llm_llm_common_llm_common_reg_compare_2_result_axb_8_3101; + wire com_llm_llm_common_llm_common_reg_compare_2_result_axb_7_3102; + wire com_llm_llm_common_llm_common_reg_compare_2_result_axb_6_3103; + wire com_llm_llm_common_llm_common_reg_compare_2_result_axb_5_3104; + wire com_llm_llm_common_llm_common_reg_compare_2_result_axb_4_3105; + wire com_llm_llm_common_llm_common_reg_compare_2_result_axb_3_3106; + wire com_llm_llm_common_llm_common_reg_compare_2_result_axb_2_3107; + wire com_llm_llm_common_llm_common_reg_compare_2_result_axb_1_3108; + wire com_llm_llm_common_llm_common_reg_compare_2_result_axb_0_3109; + wire com_llm_llm_common_llm_common_reg_llm_ack_nak_buf_nak_pending_8_4; + wire com_llm_llm_common_llm_common_reg_llm_ack_nak_buf_N_85480_i_1_3110; + wire com_llm_llm_common_llm_common_reg_llm_ack_nak_buf_N_85484_i_3111; + wire com_llm_llm_common_llm_common_reg_llm_ack_nak_buf_nak_pending_8; + wire com_llm_llm_common_llm_common_reg_llm_ack_nak_buf_N_85480_i_3112; + wire com_llm_llm_common_llm_common_reg_llm_ack_nak_buf_N_9920_i; + wire com_llm_llm_common_llm_common_reg_llm_ack_nak_buf_ack_pending_7_iv_0_0_0_1_3113; + wire com_llm_llm_common_llm_common_reg_llm_ack_nak_fsm_N_22182_i; + wire com_llm_llm_common_llm_common_reg_llm_ack_nak_fsm_N_87593_i; + wire com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_VCC_3114; + wire com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_set_3115; + wire com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_N_10950_i_3116; + wire com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_clear_3117; + wire com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_num21; + wire com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_N_9376_1; + wire com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_un1_replay_num_c1; + wire com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_un1_replay_num21_1_i_3118; + wire com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_N_22392_i; + wire com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_set_3; + wire com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_N_85482_i_3119; + wire com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_expire_pre_4; + wire com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_I_19; + wire com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_GND_3120; + wire com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_reg_rx_dllp_nak_vld_qq_3121; + wire com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_NxtTxTSN_ANSeqNum_q_3122; + wire com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_ANSeqNum_Eq_AckdSeq_q_3123; + wire com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_ANSeqNum_AckdSeq_q_3124; + wire com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_expire_pre_5; + wire com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_reg_same_last_ackd_tsn_3; + wire com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_reg_same_last_ackd_tsn_3125; + wire com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_expire_5; + wire com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_vld_q_3126; + wire com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_N_60706_i_3127; + wire com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_N_22385_i; + wire com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_N_22383_i; + wire com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_N_60695_i_3128; + wire com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_N_60696_i_3129; + wire com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_N_60697_i_3130; + wire com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_N_60698_i_3131; + wire com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_N_60699_i_3132; + wire com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_N_60700_i_3133; + wire com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_N_60701_i_3134; + wire com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_N_60702_i_3135; + wire com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_N_60703_i_3136; + wire com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_N_60704_i_3137; + wire com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_N_60705_i_3138; + wire com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_N_85487_i_3139; + wire com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timeout_flag17; + wire com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_N_87599_i_3140; + wire com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_waiting_3141; + wire com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_N_27_0; + wire com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_N_7_i; + wire com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_N_27; + wire com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_N_3_0; + wire com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_N_11_0; + wire com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_N_19_0; + wire com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_N_35_0; + wire com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_N_43_0; + wire com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_N_9; + wire com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_N_17; + wire com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_N_25; + wire com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_N_33; + wire com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_N_41; + wire com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_N_49; + wire com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_N_57; + wire com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_N_3; + wire com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_N_11; + wire com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_N_19; + wire com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_N_35; + wire com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_N_43; + wire com_llm_llm_common_llm_common_reg_llm_next_rcv_tsn_GND_3142; + wire com_tlm_aspm_ok; + wire com_tlm_u_tlm_tx_pkt_incoming; + wire com_tlm_u_tlm_tx_cfg_accepted; + wire com_tlm_u_tlm_tx_suspend_credit_rdy; + wire com_tlm_u_tlm_tx_fc_update_vld; + wire com_tlm_u_tlm_tx_fc_init_vld; + wire com_tlm_u_tlm_tx_un1_frees_pending; + wire com_tlm_u_tlm_tx_am_retry_dst_rdy; + wire com_tlm_u_tlm_tx_am_retry_src_rdy; + wire com_tlm_u_tlm_tx_N_55899_i; + wire com_tlm_u_tlm_tx_am_retry_lock; + wire com_tlm_u_tlm_tx_ack_pending; + wire com_tlm_u_tlm_tx_vc0_cfg; + wire com_tlm_u_tlm_tx_vc0_errfwd; + wire com_tlm_u_tlm_tx_vc0_sof; + wire com_tlm_u_tlm_tx_vc0_rem; + wire com_tlm_u_tlm_tx_vc0_retry; + wire com_tlm_u_tlm_tx_vc0_eof; + wire com_tlm_u_tlm_tx_vc0_src_rdy; + wire com_tlm_u_tlm_tx_vc0_retry_i; + wire com_tlm_u_tlm_tx_ds_buf_src_rdy; + wire com_tlm_u_tlm_tx_cfg_sent; + wire com_tlm_u_tlm_tx_data_src_cfg_sent_d_3143; + wire com_tlm_u_tlm_tx_data_src_GND_3144; + wire com_tlm_u_tlm_tx_data_src_N_59170_i_3145; + wire com_tlm_u_tlm_tx_data_src_lnk_tsrc_rdy; + wire com_tlm_u_tlm_tx_data_src_lnk_teof_o_5; + wire com_tlm_u_tlm_tx_data_src_lnk_tretry_o_5; + wire com_tlm_u_tlm_tx_data_src_lnk_tsof_o_5; + wire com_tlm_u_tlm_tx_data_src_N_59176_i_3146; + wire com_tlm_u_tlm_tx_data_src_N_30212_i; + wire com_tlm_u_tlm_tx_data_src_N_59169_i_3147; + wire com_tlm_u_tlm_tx_data_src_buf_src_rdy_o_3; + wire com_tlm_u_tlm_tx_data_src_cfg_sent_d_3; + wire com_tlm_u_tlm_tx_data_src_N_57190_i; + wire com_tlm_u_tlm_tx_data_src_un5_lnk_tsrc_rdy_o_0_a2_0_a3_0_a3_3148; + wire com_tlm_u_tlm_tx_ack_mgr_un1_oldest_tsn_1_cry_0_3149; + wire com_tlm_u_tlm_tx_ack_mgr_un1_oldest_tsn_1_cry_1_3150; + wire com_tlm_u_tlm_tx_ack_mgr_un1_oldest_tsn_1_cry_2_3151; + wire com_tlm_u_tlm_tx_ack_mgr_un1_oldest_tsn_1_cry_3_3152; + wire com_tlm_u_tlm_tx_ack_mgr_un1_oldest_tsn_1_cry_4_3153; + wire com_tlm_u_tlm_tx_ack_mgr_un1_oldest_tsn_1_cry_5_3154; + wire com_tlm_u_tlm_tx_ack_mgr_un1_oldest_tsn_1_cry_6_3155; + wire com_tlm_u_tlm_tx_ack_mgr_un1_oldest_tsn_1_cry_7_3156; + wire com_tlm_u_tlm_tx_ack_mgr_un1_oldest_tsn_1_cry_8_3157; + wire com_tlm_u_tlm_tx_ack_mgr_un1_oldest_tsn_1_cry_9_3158; + wire com_tlm_u_tlm_tx_ack_mgr_un1_oldest_tsn_1_cry_10_3159; + wire com_tlm_u_tlm_tx_ack_mgr_VCC_3160; + wire com_tlm_u_tlm_tx_ack_mgr_un4_retry_tsn_o_s_1_3161; + wire com_tlm_u_tlm_tx_ack_mgr_un4_retry_tsn_o_cry_0_3162; + wire com_tlm_u_tlm_tx_ack_mgr_un4_retry_tsn_o_s_2_3163; + wire com_tlm_u_tlm_tx_ack_mgr_un4_retry_tsn_o_cry_1_3164; + wire com_tlm_u_tlm_tx_ack_mgr_un4_retry_tsn_o_s_3_3165; + wire com_tlm_u_tlm_tx_ack_mgr_un4_retry_tsn_o_cry_2_3166; + wire com_tlm_u_tlm_tx_ack_mgr_un4_retry_tsn_o_s_4_3167; + wire com_tlm_u_tlm_tx_ack_mgr_un4_retry_tsn_o_cry_3_3168; + wire com_tlm_u_tlm_tx_ack_mgr_un4_retry_tsn_o_s_5_3169; + wire com_tlm_u_tlm_tx_ack_mgr_un4_retry_tsn_o_cry_4_3170; + wire com_tlm_u_tlm_tx_ack_mgr_un4_retry_tsn_o_s_6_3171; + wire com_tlm_u_tlm_tx_ack_mgr_un4_retry_tsn_o_cry_5_3172; + wire com_tlm_u_tlm_tx_ack_mgr_un4_retry_tsn_o_s_7_3173; + wire com_tlm_u_tlm_tx_ack_mgr_un4_retry_tsn_o_cry_6_3174; + wire com_tlm_u_tlm_tx_ack_mgr_un4_retry_tsn_o_s_8_3175; + wire com_tlm_u_tlm_tx_ack_mgr_un4_retry_tsn_o_cry_7_3176; + wire com_tlm_u_tlm_tx_ack_mgr_un4_retry_tsn_o_s_9_3177; + wire com_tlm_u_tlm_tx_ack_mgr_un4_retry_tsn_o_cry_8_3178; + wire com_tlm_u_tlm_tx_ack_mgr_un4_retry_tsn_o_s_10_3179; + wire com_tlm_u_tlm_tx_ack_mgr_un4_retry_tsn_o_cry_9_3180; + wire com_tlm_u_tlm_tx_ack_mgr_un4_retry_tsn_o_s_11_3181; + wire com_tlm_u_tlm_tx_ack_mgr_un4_retry_tsn_o_cry_10_3182; + wire com_tlm_u_tlm_tx_ack_mgr_un1_lnk_rupdate_ack_i_0_a2_0_a2_3183; + wire com_tlm_u_tlm_tx_ack_mgr_mgr_state_12__3184; + wire com_tlm_u_tlm_tx_ack_mgr_mgr_state_0__3185; + wire com_tlm_u_tlm_tx_ack_mgr_N_87231_i_3186; + wire com_tlm_u_tlm_tx_ack_mgr_mgr_state_7__3187; + wire com_tlm_u_tlm_tx_ack_mgr_N_87602_i_3188; + wire com_tlm_u_tlm_tx_ack_mgr_N_56106_i; + wire com_tlm_u_tlm_tx_ack_mgr_N_55979_i; + wire com_tlm_u_tlm_tx_ack_mgr_N_56325_i; + wire com_tlm_u_tlm_tx_ack_mgr_N_87236_i_3189; + wire com_tlm_u_tlm_tx_ack_mgr_N_51909_i; + wire com_tlm_u_tlm_tx_ack_mgr_N_58283; + wire com_tlm_u_tlm_tx_ack_mgr_mgr_state_9__3190; + wire com_tlm_u_tlm_tx_ack_mgr_retry_src_rdy_o_3_i_0_3191; + wire com_tlm_u_tlm_tx_ack_mgr_mgr_statec_i; + wire com_tlm_u_tlm_tx_ack_mgr_N_56502_i; + wire com_tlm_u_tlm_tx_ack_mgr_mgr_statec_0_i; + wire com_tlm_u_tlm_tx_ack_mgr_mgr_state_11__3192; + wire com_tlm_u_tlm_tx_ack_mgr_mgr_statec_2_i; + wire com_tlm_u_tlm_tx_ack_mgr_mgr_state_4__3193; + wire com_tlm_u_tlm_tx_ack_mgr_N_56351_i; + wire com_tlm_u_tlm_tx_ack_mgr_N_55921_i; + wire com_tlm_u_tlm_tx_ack_mgr_mgr_statec_3_i; + wire com_tlm_u_tlm_tx_ack_mgr_N_56066_i; + wire com_tlm_u_tlm_tx_ack_mgr_mgr_statec_4_i; + wire com_tlm_u_tlm_tx_ack_mgr_mgr_statec_5_i; + wire com_tlm_u_tlm_tx_ack_mgr_mgr_state_10__3194; + wire com_tlm_u_tlm_tx_ack_mgr_N_57355; + wire com_tlm_u_tlm_tx_ack_mgr_mgr_statec_6_i; + wire com_tlm_u_tlm_tx_ack_mgr_N_57048_i; + wire com_tlm_u_tlm_tx_ack_mgr_N_56143_i; + wire com_tlm_u_tlm_tx_ack_mgr_N_86010_i_3195; + wire com_tlm_u_tlm_tx_ack_mgr_N_58380_1; + wire com_tlm_u_tlm_tx_ack_mgr_N_58250; + wire com_tlm_u_tlm_tx_ack_mgr_un1_oldest_tsn_1_axb_11_3196; + wire com_tlm_u_tlm_tx_ack_mgr_un1_oldest_tsn_1_axb_10_3197; + wire com_tlm_u_tlm_tx_ack_mgr_un1_oldest_tsn_1_axb_9_3198; + wire com_tlm_u_tlm_tx_ack_mgr_un1_oldest_tsn_1_axb_8_3199; + wire com_tlm_u_tlm_tx_ack_mgr_un1_oldest_tsn_1_axb_7_3200; + wire com_tlm_u_tlm_tx_ack_mgr_un1_oldest_tsn_1_axb_6_3201; + wire com_tlm_u_tlm_tx_ack_mgr_un1_oldest_tsn_1_axb_5_3202; + wire com_tlm_u_tlm_tx_ack_mgr_un1_oldest_tsn_1_axb_4_3203; + wire com_tlm_u_tlm_tx_ack_mgr_un1_oldest_tsn_1_axb_3_3204; + wire com_tlm_u_tlm_tx_ack_mgr_un1_oldest_tsn_1_axb_2_3205; + wire com_tlm_u_tlm_tx_ack_mgr_un1_oldest_tsn_1_axb_1_3206; + wire com_tlm_u_tlm_tx_ack_mgr_un1_oldest_tsn_1_axb_0_3207; + wire com_tlm_u_tlm_tx_ack_mgr_N_55893_i; + wire com_tlm_u_tlm_tx_ack_mgr_N_56235_i; + wire com_tlm_u_tlm_tx_ack_mgr_N_60497_i_3208; + wire com_tlm_u_tlm_tx_ack_mgr_fifo_vld; + wire com_tlm_u_tlm_tx_ack_mgr_fifo_nxt_vld; + wire com_tlm_u_tlm_tx_ack_mgr_nak_in_retry19; + wire com_tlm_u_tlm_tx_ack_mgr_N_56340_i; + wire com_tlm_u_tlm_tx_ack_mgr_un4_retry_tsn_o_axb_11_3209; + wire com_tlm_u_tlm_tx_ack_mgr_un4_retry_tsn_o_axb_10_3210; + wire com_tlm_u_tlm_tx_ack_mgr_un4_retry_tsn_o_axb_9_3211; + wire com_tlm_u_tlm_tx_ack_mgr_un4_retry_tsn_o_axb_8_3212; + wire com_tlm_u_tlm_tx_ack_mgr_un4_retry_tsn_o_axb_7_3213; + wire com_tlm_u_tlm_tx_ack_mgr_un4_retry_tsn_o_axb_6_3214; + wire com_tlm_u_tlm_tx_ack_mgr_un4_retry_tsn_o_axb_5_3215; + wire com_tlm_u_tlm_tx_ack_mgr_un4_retry_tsn_o_axb_4_3216; + wire com_tlm_u_tlm_tx_ack_mgr_un4_retry_tsn_o_axb_3_3217; + wire com_tlm_u_tlm_tx_ack_mgr_un4_retry_tsn_o_axb_2_3218; + wire com_tlm_u_tlm_tx_ack_mgr_un4_retry_tsn_o_axb_1_3219; + wire com_tlm_u_tlm_tx_ack_mgr_N_56649_i_3220; + wire com_tlm_u_tlm_tx_ack_mgr_N_85579_i_3221; + wire com_tlm_u_tlm_tx_ack_mgr_retry_src_rdy_o_3_i_1_3222; + wire com_tlm_u_tlm_tx_ack_mgr_N_58367_1; + wire com_tlm_u_tlm_tx_ack_mgr_N_87598_i_3223; + wire com_tlm_u_tlm_tx_ack_mgr_nak_in_retry_3224; + wire com_tlm_u_tlm_tx_ack_mgr_N_55889_i; + wire com_tlm_u_tlm_tx_ack_mgr_N_10925_i_i; + wire com_tlm_u_tlm_tx_ack_mgr_N_58366_1; + wire com_tlm_u_tlm_tx_ack_mgr_nak_req_3225; + wire com_tlm_u_tlm_tx_ack_mgr_mgr_state_2__3226; + wire com_tlm_u_tlm_tx_ack_mgr_N_10925_i_i_i_3227; + wire com_tlm_u_tlm_tx_ack_mgr_un1_skips_pending; + wire com_tlm_u_tlm_tx_ack_mgr_GND_3228; + wire com_tlm_u_tlm_tx_ack_mgr_un1_oldest_tsn_1_s_11_3229; + wire com_tlm_u_tlm_tx_ack_mgr_un1_oldest_tsn_1_s_10_3230; + wire com_tlm_u_tlm_tx_ack_mgr_un1_oldest_tsn_1_s_9_3231; + wire com_tlm_u_tlm_tx_ack_mgr_un1_oldest_tsn_1_s_8_3232; + wire com_tlm_u_tlm_tx_ack_mgr_un1_oldest_tsn_1_s_7_3233; + wire com_tlm_u_tlm_tx_ack_mgr_un1_oldest_tsn_1_s_6_3234; + wire com_tlm_u_tlm_tx_ack_mgr_un1_oldest_tsn_1_s_5_3235; + wire com_tlm_u_tlm_tx_ack_mgr_un1_oldest_tsn_1_s_4_3236; + wire com_tlm_u_tlm_tx_ack_mgr_un1_oldest_tsn_1_s_3_3237; + wire com_tlm_u_tlm_tx_ack_mgr_un1_oldest_tsn_1_s_2_3238; + wire com_tlm_u_tlm_tx_ack_mgr_un1_oldest_tsn_1_s_1_3239; + wire com_tlm_u_tlm_tx_ack_mgr_un1_oldest_tsn_1_s_0_3240; + wire com_tlm_u_tlm_tx_ack_mgr_N_85576_i_3241; + wire com_tlm_u_tlm_tx_ack_mgr_mgr_state_8__3242; + wire com_tlm_u_tlm_tx_ack_mgr_N_27_0; + wire com_tlm_u_tlm_tx_ack_mgr_N_27; + wire com_tlm_u_tlm_tx_ack_mgr_un4_retry_tsn_o_axb_0_3243; + wire com_tlm_u_tlm_tx_ack_mgr_jump_retry_tsn_3244; + wire com_tlm_u_tlm_tx_ack_mgr_N_3_0; + wire com_tlm_u_tlm_tx_ack_mgr_N_11_0; + wire com_tlm_u_tlm_tx_ack_mgr_N_19_0; + wire com_tlm_u_tlm_tx_ack_mgr_N_35_0; + wire com_tlm_u_tlm_tx_ack_mgr_N_43_0; + wire com_tlm_u_tlm_tx_ack_mgr_N_3; + wire com_tlm_u_tlm_tx_ack_mgr_N_11; + wire com_tlm_u_tlm_tx_ack_mgr_N_19; + wire com_tlm_u_tlm_tx_ack_mgr_N_35; + wire com_tlm_u_tlm_tx_ack_mgr_N_43; + wire com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_GND_3245; + wire com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_un1_raddr_lo_1_cry_0_3246; + wire com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_un1_raddr_lo_1_cry_1_3247; + wire com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_un1_raddr_lo_1_cry_2_3248; + wire com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_ct_o35_0_a2_0; + wire com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_un1_bkp_raddr_lo_i_0_0__3249; + wire com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_un1_bkp_raddr_lo_i_0_3__3250; + wire com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_un1_bkp_raddr_lo_1_p4_3251; + wire com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_N_57365_1; + wire com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_un1_raddr_lo_1_axb_3_3252; + wire com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_N_57368; + wire com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_N_85539_i_3253; + wire com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_un1_bkp_i_1_i_0_a2_2_3254; + wire com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_ct_o35_0; + wire com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_un1_bkp_raddr_lo_1_c1; + wire com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_N_51172_i; + wire com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_vld_o_5_i_m2_i_m3_0_3255; + wire com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_bkp_vld_3256; + wire com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_nxt_vld_o_8_iv_i_m3_0_3257; + wire com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_bkp_nxt_vld_3258; + wire com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_N_51186_i; + wire com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_un1_bkp_raddr_lo_1_axbxc3_3259; + wire com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_N_51184_i; + wire com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_un1_bkp_raddr_lo_1_axbxc2_3260; + wire com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_N_51182_i; + wire com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_N_51180_i; + wire com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_un1_raddr_lo_1_s_3_3261; + wire com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_un1_raddr_lo_1_s_2_3262; + wire com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_un1_raddr_lo_1_s_1_3263; + wire com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_un1_raddr_lo_1_axb_0_3264; + wire com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_N_57359; + wire com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_N_57362; + wire com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_un1_bkp_raddr_lo_1_axbxc1_3265; + wire com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_N_51168_i; + wire com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_N_51170_i; + wire com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_N_87126_i; + wire com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_N_55936_i_i_3266; + wire com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_N_55936_i; + wire com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_un1_raddr_lo_1_axb_2_3267; + wire com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_un1_raddr_lo_1_axb_1_3268; + wire com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_un1_bkp_i_i_0_0_o2; + wire com_tlm_u_tlm_tx_vc0_released_buf; + wire com_tlm_u_tlm_tx_vc0_frame_vld; + wire com_tlm_u_tlm_tx_vc0_no_payload; + wire com_tlm_u_tlm_tx_vc0_trn_sof; + wire com_tlm_u_tlm_tx_vc0_trn_vld; + wire com_tlm_u_tlm_tx_vc0_trn_rem_i; + wire com_tlm_u_tlm_tx_vc0_trn_cfg; + wire com_tlm_u_tlm_tx_vc0_trn_eof; + wire com_tlm_u_tlm_tx_vc0_N_56167_i; + wire com_tlm_u_tlm_tx_vc0_in_frame; + wire com_tlm_u_tlm_tx_vc0_trn_errfwd; + wire com_tlm_u_tlm_tx_vc0_N_55858_i; + wire com_tlm_u_tlm_tx_vc0_N_55914_i; + wire com_tlm_u_tlm_tx_vc0_N_55980_i; + wire com_tlm_u_tlm_tx_vc0_start_retry; + wire com_tlm_u_tlm_tx_vc0_start_src_rdy; + wire com_tlm_u_tlm_tx_vc0_buf_pool_N_10911_i; + wire com_tlm_u_tlm_tx_vc0_buf_pool_N_56200_i_i; + wire com_tlm_u_tlm_tx_vc0_buf_pool_rdata_q_all_138__3269; + wire com_tlm_u_tlm_tx_vc0_buf_pool_rdata_q_all_66__3270; + wire com_tlm_u_tlm_tx_vc0_buf_pool_errfwd_wen_3271; + wire com_tlm_u_tlm_tx_vc0_buf_pool_VCC_3272; + wire com_tlm_u_tlm_tx_vc0_buf_pool_waddr_l_1_cry_0_3273; + wire com_tlm_u_tlm_tx_vc0_buf_pool_waddr_l_1_cry_1_3274; + wire com_tlm_u_tlm_tx_vc0_buf_pool_waddr_l_1_cry_2_3275; + wire com_tlm_u_tlm_tx_vc0_buf_pool_waddr_l_1_cry_3_3276; + wire com_tlm_u_tlm_tx_vc0_buf_pool_waddr_l_1_cry_4_3277; + wire com_tlm_u_tlm_tx_vc0_buf_pool_waddr_l_1_cry_5_3278; + wire com_tlm_u_tlm_tx_vc0_buf_pool_GND_3279; + wire com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all_139_; + wire com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all_67_; + wire com_tlm_u_tlm_tx_vc0_buf_pool_start_xfer_q_3280; + wire com_tlm_u_tlm_tx_vc0_buf_pool_rdata_sof_d_hold_3281; + wire com_tlm_u_tlm_tx_vc0_buf_pool_N_27043_i; + wire com_tlm_u_tlm_tx_vc0_buf_pool_N_27039_i; + wire com_tlm_u_tlm_tx_vc0_buf_pool_N_27037_i; + wire com_tlm_u_tlm_tx_vc0_buf_pool_N_55992_i; + wire com_tlm_u_tlm_tx_vc0_buf_pool_N_55935_i; + wire com_tlm_u_tlm_tx_vc0_buf_pool_wdata_vld_any_3282; + wire com_tlm_u_tlm_tx_vc0_buf_pool_N_20353_i; + wire com_tlm_u_tlm_tx_vc0_buf_pool_in_frame17_i_i_a2_0_a2_3283; + wire com_tlm_u_tlm_tx_vc0_buf_pool_waddr_l_1_axb_6_3284; + wire com_tlm_u_tlm_tx_vc0_buf_pool_waddr_l_1_axb_5_3285; + wire com_tlm_u_tlm_tx_vc0_buf_pool_waddr_l_1_axb_4_3286; + wire com_tlm_u_tlm_tx_vc0_buf_pool_waddr_l_1_axb_3_3287; + wire com_tlm_u_tlm_tx_vc0_buf_pool_waddr_l_1_axb_2_3288; + wire com_tlm_u_tlm_tx_vc0_buf_pool_waddr_l_1_axb_1_3289; + wire com_tlm_u_tlm_tx_vc0_buf_pool_rdata_q_all_5_68_; + wire com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all_68_; + wire com_tlm_u_tlm_tx_vc0_buf_pool_rdata_q_all_5_66_; + wire com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all_66_; + wire com_tlm_u_tlm_tx_vc0_buf_pool_rdata_q_all_5_65_; + wire com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all_65_; + wire com_tlm_u_tlm_tx_vc0_buf_pool_rdata_q_all_5_64_; + wire com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all_64_; + wire com_tlm_u_tlm_tx_vc0_buf_pool_rdata_q_all_18_140_; + wire com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all_140_; + wire com_tlm_u_tlm_tx_vc0_buf_pool_rdata_q_all_18_138_; + wire com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all_138_; + wire com_tlm_u_tlm_tx_vc0_buf_pool_rdata_q_all_18_137_; + wire com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all_137_; + wire com_tlm_u_tlm_tx_vc0_buf_pool_rdata_q_all_18_136_; + wire com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all_136_; + wire com_tlm_u_tlm_tx_vc0_buf_pool_N_59099_i_3290; + wire com_tlm_u_tlm_tx_vc0_buf_pool_rdata_q_all_137__3291; + wire com_tlm_u_tlm_tx_vc0_buf_pool_rdata_q_all_65__3292; + wire com_tlm_u_tlm_tx_vc0_buf_pool_rdata_q_all_136__3293; + wire com_tlm_u_tlm_tx_vc0_buf_pool_rdata_q_all_64__3294; + wire com_tlm_u_tlm_tx_vc0_buf_pool_N_27045_i; + wire com_tlm_u_tlm_tx_vc0_buf_pool_N_27041_i; + wire com_tlm_u_tlm_tx_vc0_buf_pool_rdata_q_all_140__3295; + wire com_tlm_u_tlm_tx_vc0_buf_pool_rdata_q_all_68__3296; + wire com_tlm_u_tlm_tx_vc0_buf_pool_N_87188_i_3297; + wire com_tlm_u_tlm_tx_vc0_buf_pool_N_62985_i_3298; + wire com_tlm_u_tlm_tx_vc0_buf_pool_rdata_q_all_139__3299; + wire com_tlm_u_tlm_tx_vc0_buf_pool_rdata_q_all_67__3300; + wire com_tlm_u_tlm_tx_vc0_buf_pool_N_85563_i; + wire com_tlm_u_tlm_tx_vc0_buf_pool_N_85563_i_1; + wire com_tlm_u_tlm_tx_vc0_buf_pool_rdata_sof_d_0_a2_0_a2_3301; + wire com_tlm_u_tlm_tx_vc0_buf_pool_rvld_q_any_3302; + wire com_tlm_u_tlm_tx_vc0_buf_pool_rvld_any_3303; + wire com_tlm_u_tlm_tx_vc0_buf_pool_errfwd; + wire com_tlm_u_tlm_tx_vc0_buf_pool_N_10835_i; + wire com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all_63_; + wire com_tlm_u_tlm_tx_vc0_buf_pool_rdata_q_all_63_; + wire com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all_62_; + wire com_tlm_u_tlm_tx_vc0_buf_pool_rdata_q_all_62_; + wire com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all_61_; + wire com_tlm_u_tlm_tx_vc0_buf_pool_rdata_q_all_61_; + wire com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all_60_; + wire com_tlm_u_tlm_tx_vc0_buf_pool_rdata_q_all_60_; + wire com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all_59_; + wire com_tlm_u_tlm_tx_vc0_buf_pool_rdata_q_all_59_; + wire com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all_58_; + wire com_tlm_u_tlm_tx_vc0_buf_pool_rdata_q_all_58_; + wire com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all_57_; + wire com_tlm_u_tlm_tx_vc0_buf_pool_rdata_q_all_57_; + wire com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all_56_; + wire com_tlm_u_tlm_tx_vc0_buf_pool_rdata_q_all_56_; + wire com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all_55_; + wire com_tlm_u_tlm_tx_vc0_buf_pool_rdata_q_all_55_; + wire com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all_54_; + wire com_tlm_u_tlm_tx_vc0_buf_pool_rdata_q_all_54_; + wire com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all_53_; + wire com_tlm_u_tlm_tx_vc0_buf_pool_rdata_q_all_53_; + wire com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all_52_; + wire com_tlm_u_tlm_tx_vc0_buf_pool_rdata_q_all_52_; + wire com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all_51_; + wire com_tlm_u_tlm_tx_vc0_buf_pool_rdata_q_all_51_; + wire com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all_50_; + wire com_tlm_u_tlm_tx_vc0_buf_pool_rdata_q_all_50_; + wire com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all_49_; + wire com_tlm_u_tlm_tx_vc0_buf_pool_rdata_q_all_49_; + wire com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all_48_; + wire com_tlm_u_tlm_tx_vc0_buf_pool_rdata_q_all_48_; + wire com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all_47_; + wire com_tlm_u_tlm_tx_vc0_buf_pool_rdata_q_all_47_; + wire com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all_46_; + wire com_tlm_u_tlm_tx_vc0_buf_pool_rdata_q_all_46_; + wire com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all_45_; + wire com_tlm_u_tlm_tx_vc0_buf_pool_rdata_q_all_45_; + wire com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all_44_; + wire com_tlm_u_tlm_tx_vc0_buf_pool_rdata_q_all_44_; + wire com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all_43_; + wire com_tlm_u_tlm_tx_vc0_buf_pool_rdata_q_all_43_; + wire com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all_42_; + wire com_tlm_u_tlm_tx_vc0_buf_pool_rdata_q_all_42_; + wire com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all_41_; + wire com_tlm_u_tlm_tx_vc0_buf_pool_rdata_q_all_41_; + wire com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all_40_; + wire com_tlm_u_tlm_tx_vc0_buf_pool_rdata_q_all_40_; + wire com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all_39_; + wire com_tlm_u_tlm_tx_vc0_buf_pool_rdata_q_all_39_; + wire com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all_38_; + wire com_tlm_u_tlm_tx_vc0_buf_pool_rdata_q_all_38_; + wire com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all_37_; + wire com_tlm_u_tlm_tx_vc0_buf_pool_rdata_q_all_37_; + wire com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all_36_; + wire com_tlm_u_tlm_tx_vc0_buf_pool_rdata_q_all_36_; + wire com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all_35_; + wire com_tlm_u_tlm_tx_vc0_buf_pool_rdata_q_all_35_; + wire com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all_34_; + wire com_tlm_u_tlm_tx_vc0_buf_pool_rdata_q_all_34_; + wire com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all_33_; + wire com_tlm_u_tlm_tx_vc0_buf_pool_rdata_q_all_33_; + wire com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all_32_; + wire com_tlm_u_tlm_tx_vc0_buf_pool_rdata_q_all_32_; + wire com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all_31_; + wire com_tlm_u_tlm_tx_vc0_buf_pool_rdata_q_all_31_; + wire com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all_30_; + wire com_tlm_u_tlm_tx_vc0_buf_pool_rdata_q_all_30_; + wire com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all_29_; + wire com_tlm_u_tlm_tx_vc0_buf_pool_rdata_q_all_29_; + wire com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all_28_; + wire com_tlm_u_tlm_tx_vc0_buf_pool_rdata_q_all_28_; + wire com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all_27_; + wire com_tlm_u_tlm_tx_vc0_buf_pool_rdata_q_all_27_; + wire com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all_26_; + wire com_tlm_u_tlm_tx_vc0_buf_pool_rdata_q_all_26_; + wire com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all_25_; + wire com_tlm_u_tlm_tx_vc0_buf_pool_rdata_q_all_25_; + wire com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all_24_; + wire com_tlm_u_tlm_tx_vc0_buf_pool_rdata_q_all_24_; + wire com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all_23_; + wire com_tlm_u_tlm_tx_vc0_buf_pool_rdata_q_all_23_; + wire com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all_22_; + wire com_tlm_u_tlm_tx_vc0_buf_pool_rdata_q_all_22_; + wire com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all_21_; + wire com_tlm_u_tlm_tx_vc0_buf_pool_rdata_q_all_21_; + wire com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all_20_; + wire com_tlm_u_tlm_tx_vc0_buf_pool_rdata_q_all_20_; + wire com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all_19_; + wire com_tlm_u_tlm_tx_vc0_buf_pool_rdata_q_all_19_; + wire com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all_18_; + wire com_tlm_u_tlm_tx_vc0_buf_pool_rdata_q_all_18_; + wire com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all_17_; + wire com_tlm_u_tlm_tx_vc0_buf_pool_rdata_q_all_17_; + wire com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all_16_; + wire com_tlm_u_tlm_tx_vc0_buf_pool_rdata_q_all_16_; + wire com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all_15_; + wire com_tlm_u_tlm_tx_vc0_buf_pool_rdata_q_all_15_; + wire com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all_14_; + wire com_tlm_u_tlm_tx_vc0_buf_pool_rdata_q_all_14_; + wire com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all_13_; + wire com_tlm_u_tlm_tx_vc0_buf_pool_rdata_q_all_13_; + wire com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all_12_; + wire com_tlm_u_tlm_tx_vc0_buf_pool_rdata_q_all_12_; + wire com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all_11_; + wire com_tlm_u_tlm_tx_vc0_buf_pool_rdata_q_all_11_; + wire com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all_10_; + wire com_tlm_u_tlm_tx_vc0_buf_pool_rdata_q_all_10_; + wire com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all_9_; + wire com_tlm_u_tlm_tx_vc0_buf_pool_rdata_q_all_9_; + wire com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all_8_; + wire com_tlm_u_tlm_tx_vc0_buf_pool_rdata_q_all_8_; + wire com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all_7_; + wire com_tlm_u_tlm_tx_vc0_buf_pool_rdata_q_all_7_; + wire com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all_6_; + wire com_tlm_u_tlm_tx_vc0_buf_pool_rdata_q_all_6_; + wire com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all_5_; + wire com_tlm_u_tlm_tx_vc0_buf_pool_rdata_q_all_5_; + wire com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all_4_; + wire com_tlm_u_tlm_tx_vc0_buf_pool_rdata_q_all_4_; + wire com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all_3_; + wire com_tlm_u_tlm_tx_vc0_buf_pool_rdata_q_all_3_; + wire com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all_2_; + wire com_tlm_u_tlm_tx_vc0_buf_pool_rdata_q_all_2_; + wire com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all_1_; + wire com_tlm_u_tlm_tx_vc0_buf_pool_rdata_q_all_1_; + wire com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all_0_; + wire com_tlm_u_tlm_tx_vc0_buf_pool_rdata_q_all_0_; + wire com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all_135_; + wire com_tlm_u_tlm_tx_vc0_buf_pool_rdata_q_all_135_; + wire com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all_134_; + wire com_tlm_u_tlm_tx_vc0_buf_pool_rdata_q_all_134_; + wire com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all_133_; + wire com_tlm_u_tlm_tx_vc0_buf_pool_rdata_q_all_133_; + wire com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all_132_; + wire com_tlm_u_tlm_tx_vc0_buf_pool_rdata_q_all_132_; + wire com_tlm_u_tlm_tx_vc0_buf_pool_N_86909_i_1_3304; + wire com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all_131_; + wire com_tlm_u_tlm_tx_vc0_buf_pool_rdata_q_all_131_; + wire com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all_130_; + wire com_tlm_u_tlm_tx_vc0_buf_pool_rdata_q_all_130_; + wire com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all_129_; + wire com_tlm_u_tlm_tx_vc0_buf_pool_rdata_q_all_129_; + wire com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all_128_; + wire com_tlm_u_tlm_tx_vc0_buf_pool_rdata_q_all_128_; + wire com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all_127_; + wire com_tlm_u_tlm_tx_vc0_buf_pool_rdata_q_all_127_; + wire com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all_126_; + wire com_tlm_u_tlm_tx_vc0_buf_pool_rdata_q_all_126_; + wire com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all_125_; + wire com_tlm_u_tlm_tx_vc0_buf_pool_rdata_q_all_125_; + wire com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all_124_; + wire com_tlm_u_tlm_tx_vc0_buf_pool_rdata_q_all_124_; + wire com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all_123_; + wire com_tlm_u_tlm_tx_vc0_buf_pool_rdata_q_all_123_; + wire com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all_122_; + wire com_tlm_u_tlm_tx_vc0_buf_pool_rdata_q_all_122_; + wire com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all_121_; + wire com_tlm_u_tlm_tx_vc0_buf_pool_rdata_q_all_121_; + wire com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all_120_; + wire com_tlm_u_tlm_tx_vc0_buf_pool_rdata_q_all_120_; + wire com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all_119_; + wire com_tlm_u_tlm_tx_vc0_buf_pool_rdata_q_all_119_; + wire com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all_118_; + wire com_tlm_u_tlm_tx_vc0_buf_pool_rdata_q_all_118_; + wire com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all_117_; + wire com_tlm_u_tlm_tx_vc0_buf_pool_rdata_q_all_117_; + wire com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all_116_; + wire com_tlm_u_tlm_tx_vc0_buf_pool_rdata_q_all_116_; + wire com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all_115_; + wire com_tlm_u_tlm_tx_vc0_buf_pool_rdata_q_all_115_; + wire com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all_114_; + wire com_tlm_u_tlm_tx_vc0_buf_pool_rdata_q_all_114_; + wire com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all_113_; + wire com_tlm_u_tlm_tx_vc0_buf_pool_rdata_q_all_113_; + wire com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all_112_; + wire com_tlm_u_tlm_tx_vc0_buf_pool_rdata_q_all_112_; + wire com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all_111_; + wire com_tlm_u_tlm_tx_vc0_buf_pool_rdata_q_all_111_; + wire com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all_110_; + wire com_tlm_u_tlm_tx_vc0_buf_pool_rdata_q_all_110_; + wire com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all_109_; + wire com_tlm_u_tlm_tx_vc0_buf_pool_rdata_q_all_109_; + wire com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all_108_; + wire com_tlm_u_tlm_tx_vc0_buf_pool_rdata_q_all_108_; + wire com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all_107_; + wire com_tlm_u_tlm_tx_vc0_buf_pool_rdata_q_all_107_; + wire com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all_106_; + wire com_tlm_u_tlm_tx_vc0_buf_pool_rdata_q_all_106_; + wire com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all_105_; + wire com_tlm_u_tlm_tx_vc0_buf_pool_rdata_q_all_105_; + wire com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all_104_; + wire com_tlm_u_tlm_tx_vc0_buf_pool_rdata_q_all_104_; + wire com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all_103_; + wire com_tlm_u_tlm_tx_vc0_buf_pool_rdata_q_all_103_; + wire com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all_102_; + wire com_tlm_u_tlm_tx_vc0_buf_pool_rdata_q_all_102_; + wire com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all_101_; + wire com_tlm_u_tlm_tx_vc0_buf_pool_rdata_q_all_101_; + wire com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all_100_; + wire com_tlm_u_tlm_tx_vc0_buf_pool_rdata_q_all_100_; + wire com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all_99_; + wire com_tlm_u_tlm_tx_vc0_buf_pool_rdata_q_all_99_; + wire com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all_98_; + wire com_tlm_u_tlm_tx_vc0_buf_pool_rdata_q_all_98_; + wire com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all_97_; + wire com_tlm_u_tlm_tx_vc0_buf_pool_rdata_q_all_97_; + wire com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all_96_; + wire com_tlm_u_tlm_tx_vc0_buf_pool_rdata_q_all_96_; + wire com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all_95_; + wire com_tlm_u_tlm_tx_vc0_buf_pool_rdata_q_all_95_; + wire com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all_94_; + wire com_tlm_u_tlm_tx_vc0_buf_pool_rdata_q_all_94_; + wire com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all_93_; + wire com_tlm_u_tlm_tx_vc0_buf_pool_rdata_q_all_93_; + wire com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all_92_; + wire com_tlm_u_tlm_tx_vc0_buf_pool_rdata_q_all_92_; + wire com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all_91_; + wire com_tlm_u_tlm_tx_vc0_buf_pool_rdata_q_all_91_; + wire com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all_90_; + wire com_tlm_u_tlm_tx_vc0_buf_pool_rdata_q_all_90_; + wire com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all_89_; + wire com_tlm_u_tlm_tx_vc0_buf_pool_rdata_q_all_89_; + wire com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all_88_; + wire com_tlm_u_tlm_tx_vc0_buf_pool_rdata_q_all_88_; + wire com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all_87_; + wire com_tlm_u_tlm_tx_vc0_buf_pool_rdata_q_all_87_; + wire com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all_86_; + wire com_tlm_u_tlm_tx_vc0_buf_pool_rdata_q_all_86_; + wire com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all_85_; + wire com_tlm_u_tlm_tx_vc0_buf_pool_rdata_q_all_85_; + wire com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all_84_; + wire com_tlm_u_tlm_tx_vc0_buf_pool_rdata_q_all_84_; + wire com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all_83_; + wire com_tlm_u_tlm_tx_vc0_buf_pool_rdata_q_all_83_; + wire com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all_82_; + wire com_tlm_u_tlm_tx_vc0_buf_pool_rdata_q_all_82_; + wire com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all_81_; + wire com_tlm_u_tlm_tx_vc0_buf_pool_rdata_q_all_81_; + wire com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all_80_; + wire com_tlm_u_tlm_tx_vc0_buf_pool_rdata_q_all_80_; + wire com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all_79_; + wire com_tlm_u_tlm_tx_vc0_buf_pool_rdata_q_all_79_; + wire com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all_78_; + wire com_tlm_u_tlm_tx_vc0_buf_pool_rdata_q_all_78_; + wire com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all_77_; + wire com_tlm_u_tlm_tx_vc0_buf_pool_rdata_q_all_77_; + wire com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all_76_; + wire com_tlm_u_tlm_tx_vc0_buf_pool_rdata_q_all_76_; + wire com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all_75_; + wire com_tlm_u_tlm_tx_vc0_buf_pool_rdata_q_all_75_; + wire com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all_74_; + wire com_tlm_u_tlm_tx_vc0_buf_pool_rdata_q_all_74_; + wire com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all_73_; + wire com_tlm_u_tlm_tx_vc0_buf_pool_rdata_q_all_73_; + wire com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all_72_; + wire com_tlm_u_tlm_tx_vc0_buf_pool_rdata_q_all_72_; + wire com_tlm_u_tlm_tx_vc0_buf_pool_N_86909_i_3305; + wire com_tlm_u_tlm_tx_vc0_buf_pool_rdata_errfwd_3306; + wire com_tlm_u_tlm_tx_vc0_buf_pool_N_59264_i_3307; + wire com_tlm_u_tlm_tx_vc0_buf_pool_rdata_q_errfwd_3308; + wire com_tlm_u_tlm_tx_vc0_buf_pool_wdata_66__3309; + wire com_tlm_u_tlm_tx_vc0_buf_pool_wdata_65__3310; + wire com_tlm_u_tlm_tx_vc0_buf_pool_wdata_64__3311; + wire com_tlm_u_tlm_tx_vc0_buf_pool_wdata_63__3312; + wire com_tlm_u_tlm_tx_vc0_buf_pool_wdata_62__3313; + wire com_tlm_u_tlm_tx_vc0_buf_pool_wdata_61__3314; + wire com_tlm_u_tlm_tx_vc0_buf_pool_wdata_60__3315; + wire com_tlm_u_tlm_tx_vc0_buf_pool_wdata_59__3316; + wire com_tlm_u_tlm_tx_vc0_buf_pool_wdata_58__3317; + wire com_tlm_u_tlm_tx_vc0_buf_pool_wdata_57__3318; + wire com_tlm_u_tlm_tx_vc0_buf_pool_wdata_56__3319; + wire com_tlm_u_tlm_tx_vc0_buf_pool_wdata_55__3320; + wire com_tlm_u_tlm_tx_vc0_buf_pool_wdata_54__3321; + wire com_tlm_u_tlm_tx_vc0_buf_pool_wdata_53__3322; + wire com_tlm_u_tlm_tx_vc0_buf_pool_wdata_52__3323; + wire com_tlm_u_tlm_tx_vc0_buf_pool_wdata_51__3324; + wire com_tlm_u_tlm_tx_vc0_buf_pool_wdata_50__3325; + wire com_tlm_u_tlm_tx_vc0_buf_pool_wdata_49__3326; + wire com_tlm_u_tlm_tx_vc0_buf_pool_wdata_48__3327; + wire com_tlm_u_tlm_tx_vc0_buf_pool_wdata_47__3328; + wire com_tlm_u_tlm_tx_vc0_buf_pool_wdata_46__3329; + wire com_tlm_u_tlm_tx_vc0_buf_pool_wdata_45__3330; + wire com_tlm_u_tlm_tx_vc0_buf_pool_wdata_44__3331; + wire com_tlm_u_tlm_tx_vc0_buf_pool_wdata_43__3332; + wire com_tlm_u_tlm_tx_vc0_buf_pool_wdata_42__3333; + wire com_tlm_u_tlm_tx_vc0_buf_pool_wdata_41__3334; + wire com_tlm_u_tlm_tx_vc0_buf_pool_wdata_40__3335; + wire com_tlm_u_tlm_tx_vc0_buf_pool_wdata_39__3336; + wire com_tlm_u_tlm_tx_vc0_buf_pool_wdata_38__3337; + wire com_tlm_u_tlm_tx_vc0_buf_pool_wdata_37__3338; + wire com_tlm_u_tlm_tx_vc0_buf_pool_wdata_36__3339; + wire com_tlm_u_tlm_tx_vc0_buf_pool_wdata_35__3340; + wire com_tlm_u_tlm_tx_vc0_buf_pool_wdata_34__3341; + wire com_tlm_u_tlm_tx_vc0_buf_pool_wdata_33__3342; + wire com_tlm_u_tlm_tx_vc0_buf_pool_wdata_32__3343; + wire com_tlm_u_tlm_tx_vc0_buf_pool_wdata_31__3344; + wire com_tlm_u_tlm_tx_vc0_buf_pool_wdata_30__3345; + wire com_tlm_u_tlm_tx_vc0_buf_pool_wdata_29__3346; + wire com_tlm_u_tlm_tx_vc0_buf_pool_wdata_28__3347; + wire com_tlm_u_tlm_tx_vc0_buf_pool_wdata_27__3348; + wire com_tlm_u_tlm_tx_vc0_buf_pool_wdata_26__3349; + wire com_tlm_u_tlm_tx_vc0_buf_pool_wdata_25__3350; + wire com_tlm_u_tlm_tx_vc0_buf_pool_wdata_24__3351; + wire com_tlm_u_tlm_tx_vc0_buf_pool_wdata_23__3352; + wire com_tlm_u_tlm_tx_vc0_buf_pool_wdata_22__3353; + wire com_tlm_u_tlm_tx_vc0_buf_pool_wdata_21__3354; + wire com_tlm_u_tlm_tx_vc0_buf_pool_wdata_20__3355; + wire com_tlm_u_tlm_tx_vc0_buf_pool_wdata_19__3356; + wire com_tlm_u_tlm_tx_vc0_buf_pool_wdata_18__3357; + wire com_tlm_u_tlm_tx_vc0_buf_pool_wdata_17__3358; + wire com_tlm_u_tlm_tx_vc0_buf_pool_wdata_16__3359; + wire com_tlm_u_tlm_tx_vc0_buf_pool_wdata_15__3360; + wire com_tlm_u_tlm_tx_vc0_buf_pool_wdata_14__3361; + wire com_tlm_u_tlm_tx_vc0_buf_pool_wdata_13__3362; + wire com_tlm_u_tlm_tx_vc0_buf_pool_wdata_12__3363; + wire com_tlm_u_tlm_tx_vc0_buf_pool_wdata_11__3364; + wire com_tlm_u_tlm_tx_vc0_buf_pool_wdata_10__3365; + wire com_tlm_u_tlm_tx_vc0_buf_pool_wdata_9__3366; + wire com_tlm_u_tlm_tx_vc0_buf_pool_wdata_8__3367; + wire com_tlm_u_tlm_tx_vc0_buf_pool_wdata_7__3368; + wire com_tlm_u_tlm_tx_vc0_buf_pool_wdata_6__3369; + wire com_tlm_u_tlm_tx_vc0_buf_pool_wdata_5__3370; + wire com_tlm_u_tlm_tx_vc0_buf_pool_wdata_4__3371; + wire com_tlm_u_tlm_tx_vc0_buf_pool_wdata_3__3372; + wire com_tlm_u_tlm_tx_vc0_buf_pool_wdata_2__3373; + wire com_tlm_u_tlm_tx_vc0_buf_pool_wdata_1__3374; + wire com_tlm_u_tlm_tx_vc0_buf_pool_wdata_0__3375; + wire com_tlm_u_tlm_tx_vc0_buf_pool_N_59233_i; + wire com_tlm_u_tlm_tx_vc0_buf_pool_wdata_68_; + wire com_tlm_u_tlm_tx_vc0_buf_pool_N_59265_i_3376; + wire com_tlm_u_tlm_tx_vc0_buf_pool_N_59266_i_3377; + wire com_tlm_u_tlm_tx_vc0_buf_pool_N_59267_i_3378; + wire com_tlm_u_tlm_tx_vc0_buf_pool_N_59268_i_3379; + wire com_tlm_u_tlm_tx_vc0_buf_pool_N_59269_i_3380; + wire com_tlm_u_tlm_tx_vc0_buf_pool_N_59270_i_3381; + wire com_tlm_u_tlm_tx_vc0_buf_pool_N_59271_i_3382; + wire com_tlm_u_tlm_tx_vc0_buf_pool_N_59272_i_3383; + wire com_tlm_u_tlm_tx_vc0_buf_pool_N_59273_i_3384; + wire com_tlm_u_tlm_tx_vc0_buf_pool_N_59274_i_3385; + wire com_tlm_u_tlm_tx_vc0_buf_pool_N_59275_i_3386; + wire com_tlm_u_tlm_tx_vc0_buf_pool_N_59276_i_3387; + wire com_tlm_u_tlm_tx_vc0_buf_pool_N_59277_i_3388; + wire com_tlm_u_tlm_tx_vc0_buf_pool_N_59278_i_3389; + wire com_tlm_u_tlm_tx_vc0_buf_pool_N_59279_i_3390; + wire com_tlm_u_tlm_tx_vc0_buf_pool_N_59280_i_3391; + wire com_tlm_u_tlm_tx_vc0_buf_pool_N_59281_i_3392; + wire com_tlm_u_tlm_tx_vc0_buf_pool_N_59282_i_3393; + wire com_tlm_u_tlm_tx_vc0_buf_pool_N_59283_i_3394; + wire com_tlm_u_tlm_tx_vc0_buf_pool_N_59284_i_3395; + wire com_tlm_u_tlm_tx_vc0_buf_pool_N_59285_i_3396; + wire com_tlm_u_tlm_tx_vc0_buf_pool_N_59286_i_3397; + wire com_tlm_u_tlm_tx_vc0_buf_pool_N_59287_i_3398; + wire com_tlm_u_tlm_tx_vc0_buf_pool_N_59288_i_3399; + wire com_tlm_u_tlm_tx_vc0_buf_pool_N_59289_i_3400; + wire com_tlm_u_tlm_tx_vc0_buf_pool_N_59290_i_3401; + wire com_tlm_u_tlm_tx_vc0_buf_pool_N_59291_i_3402; + wire com_tlm_u_tlm_tx_vc0_buf_pool_N_59292_i_3403; + wire com_tlm_u_tlm_tx_vc0_buf_pool_N_59293_i_3404; + wire com_tlm_u_tlm_tx_vc0_buf_pool_N_59294_i_3405; + wire com_tlm_u_tlm_tx_vc0_buf_pool_N_59295_i_3406; + wire com_tlm_u_tlm_tx_vc0_buf_pool_N_59296_i_3407; + wire com_tlm_u_tlm_tx_vc0_buf_pool_N_59297_i_3408; + wire com_tlm_u_tlm_tx_vc0_buf_pool_N_59298_i_3409; + wire com_tlm_u_tlm_tx_vc0_buf_pool_N_59299_i_3410; + wire com_tlm_u_tlm_tx_vc0_buf_pool_N_59300_i_3411; + wire com_tlm_u_tlm_tx_vc0_buf_pool_N_59301_i_3412; + wire com_tlm_u_tlm_tx_vc0_buf_pool_N_59302_i_3413; + wire com_tlm_u_tlm_tx_vc0_buf_pool_N_59303_i_3414; + wire com_tlm_u_tlm_tx_vc0_buf_pool_N_59304_i_3415; + wire com_tlm_u_tlm_tx_vc0_buf_pool_N_59305_i_3416; + wire com_tlm_u_tlm_tx_vc0_buf_pool_N_59306_i_3417; + wire com_tlm_u_tlm_tx_vc0_buf_pool_N_59307_i_3418; + wire com_tlm_u_tlm_tx_vc0_buf_pool_N_59308_i_3419; + wire com_tlm_u_tlm_tx_vc0_buf_pool_N_59309_i_3420; + wire com_tlm_u_tlm_tx_vc0_buf_pool_N_59310_i_3421; + wire com_tlm_u_tlm_tx_vc0_buf_pool_N_59311_i_3422; + wire com_tlm_u_tlm_tx_vc0_buf_pool_N_59312_i_3423; + wire com_tlm_u_tlm_tx_vc0_buf_pool_N_59313_i_3424; + wire com_tlm_u_tlm_tx_vc0_buf_pool_N_59314_i_3425; + wire com_tlm_u_tlm_tx_vc0_buf_pool_N_59315_i_3426; + wire com_tlm_u_tlm_tx_vc0_buf_pool_N_59316_i_3427; + wire com_tlm_u_tlm_tx_vc0_buf_pool_N_59317_i_3428; + wire com_tlm_u_tlm_tx_vc0_buf_pool_N_59318_i_3429; + wire com_tlm_u_tlm_tx_vc0_buf_pool_N_59319_i_3430; + wire com_tlm_u_tlm_tx_vc0_buf_pool_N_59320_i_3431; + wire com_tlm_u_tlm_tx_vc0_buf_pool_N_59321_i_3432; + wire com_tlm_u_tlm_tx_vc0_buf_pool_N_59322_i_3433; + wire com_tlm_u_tlm_tx_vc0_buf_pool_N_59323_i_3434; + wire com_tlm_u_tlm_tx_vc0_buf_pool_N_59324_i_3435; + wire com_tlm_u_tlm_tx_vc0_buf_pool_N_59325_i_3436; + wire com_tlm_u_tlm_tx_vc0_buf_pool_N_59326_i_3437; + wire com_tlm_u_tlm_tx_vc0_buf_pool_N_59327_i_3438; + wire com_tlm_u_tlm_tx_vc0_buf_pool_N_59182_i_3439; + wire com_tlm_u_tlm_tx_vc0_buf_pool_N_86423_i_3440; + wire com_tlm_u_tlm_tx_vc0_buf_pool_wdata_errfwd_3441; + wire com_tlm_u_tlm_tx_vc0_buf_pool_N_56080_i; + wire com_tlm_u_tlm_tx_vc0_buf_pool_en_ram_i_i; + wire com_tlm_u_tlm_tx_vc0_buf_pool_N_55898_i_i_3442; + wire com_tlm_u_tlm_tx_vc0_buf_pool_N_55898_i; + wire com_tlm_u_tlm_tx_vc0_buf_pool_waddr_l_1_axb_0_3443; + wire com_tlm_u_tlm_tx_vc0_buf_pool_srl_retry_retry_fifo_GND_3444; + wire com_tlm_u_tlm_tx_vc0_buf_pool_srl_retry_retry_fifo_un1_raddr_lo_1_s_1_0; + wire com_tlm_u_tlm_tx_vc0_buf_pool_srl_retry_retry_fifo_un1_raddr_lo_1_cry_0_3445; + wire com_tlm_u_tlm_tx_vc0_buf_pool_srl_retry_retry_fifo_un1_raddr_lo_1_s_2_0; + wire com_tlm_u_tlm_tx_vc0_buf_pool_srl_retry_retry_fifo_un1_raddr_lo_1_cry_1_3446; + wire com_tlm_u_tlm_tx_vc0_buf_pool_srl_retry_retry_fifo_un1_raddr_lo_1_s_3_0; + wire com_tlm_u_tlm_tx_vc0_buf_pool_srl_retry_retry_fifo_un1_raddr_lo_1_cry_2_3447; + wire com_tlm_u_tlm_tx_vc0_buf_pool_srl_retry_retry_fifo_un1_nxt_vld_o_en_1_i_0_0_0_a2_0_1_1_3448; + wire com_tlm_u_tlm_tx_vc0_buf_pool_srl_retry_retry_fifo_un1_retry_fifo_1; + wire com_tlm_u_tlm_tx_vc0_buf_pool_srl_retry_retry_fifo_raddr_en_0_0_a2_1_i_0_3449; + wire com_tlm_u_tlm_tx_vc0_buf_pool_srl_retry_retry_fifo_N_85559_i_3450; + wire com_tlm_u_tlm_tx_vc0_buf_pool_srl_retry_retry_fifo_N_58747_1; + wire com_tlm_u_tlm_tx_vc0_buf_pool_srl_retry_retry_fifo_raddr_en_0_0_i_o3_0; + wire com_tlm_u_tlm_tx_vc0_buf_pool_srl_retry_retry_fifo_N_61280_1; + wire com_tlm_u_tlm_tx_vc0_buf_pool_srl_retry_retry_fifo_raddr_en_0_0_i_a2_0_1_3451; + wire com_tlm_u_tlm_tx_vc0_buf_pool_srl_retry_retry_fifo_raddr_en_0_0_i_0_3452; + wire com_tlm_u_tlm_tx_vc0_buf_pool_srl_retry_retry_fifo_un1_raddr_lo_1_axb_0_3453; + wire com_tlm_u_tlm_tx_vc0_buf_pool_srl_retry_retry_fifo_raddr_en_0_0_i_a2_1_0_3454; + wire com_tlm_u_tlm_tx_vc0_buf_pool_srl_retry_retry_fifo_raddr_en_0_0_i_1_3455; + wire com_tlm_u_tlm_tx_vc0_buf_pool_srl_retry_retry_fifo_raddr_en_0_0_i_o3_3456; + wire com_tlm_u_tlm_tx_vc0_buf_pool_srl_retry_retry_fifo_N_53087_i; + wire com_tlm_u_tlm_tx_vc0_buf_pool_srl_retry_retry_fifo_N_56203_i; + wire com_tlm_u_tlm_tx_vc0_buf_pool_srl_retry_retry_fifo_un1_raddr_lo_1_axb_3_3457; + wire com_tlm_u_tlm_tx_vc0_buf_pool_srl_retry_retry_fifo_un1_raddr_lo_1_axb_2_3458; + wire com_tlm_u_tlm_tx_vc0_buf_pool_srl_retry_retry_fifo_un1_raddr_lo_1_axb_1_3459; + wire com_tlm_u_tlm_tx_vc0_buf_pool_srl_retry_retry_fifo_N_53076_i; + wire com_tlm_u_tlm_tx_vc0_buf_pool_bram_0__size4_bram_array_VCC_3460; + wire com_tlm_u_tlm_tx_vc0_buf_pool_bram_0__size4_bram_array_GND_3461; + wire com_tlm_u_tlm_tx_vc0_buf_pool_bram_1__size4_bram_array_VCC_3462; + wire com_tlm_u_tlm_tx_vc0_buf_pool_bram_1__size4_bram_array_GND_3463; + wire com_tlm_u_tlm_tx_vc0_trn_un1_trn_tbuf_av_o_1_cry_1_0_3464; + wire com_tlm_u_tlm_tx_vc0_trn_un1_trn_tbuf_av_o_1_s_1_3465; + wire com_tlm_u_tlm_tx_vc0_trn_un1_trn_tbuf_av_o_1_cry_0_3466; + wire com_tlm_u_tlm_tx_vc0_trn_un1_trn_tbuf_av_o_1_cry_2_0_3467; + wire com_tlm_u_tlm_tx_vc0_trn_un1_trn_tbuf_av_o_1_s_2_3468; + wire com_tlm_u_tlm_tx_vc0_trn_un1_trn_tbuf_av_o_1_cry_1_3469; + wire com_tlm_u_tlm_tx_vc0_trn_un1_trn_tbuf_av_o_1_cry_3_0_3470; + wire com_tlm_u_tlm_tx_vc0_trn_un1_trn_tbuf_av_o_1_s_3_3471; + wire com_tlm_u_tlm_tx_vc0_trn_un1_trn_tbuf_av_o_1_cry_2_3472; + wire com_tlm_u_tlm_tx_vc0_trn_un1_trn_tbuf_av_o_1_s_4_3473; + wire com_tlm_u_tlm_tx_vc0_trn_un1_trn_tbuf_av_o_1_cry_3_3474; + wire com_tlm_u_tlm_tx_vc0_trn_un1_usr_vld_0_a2_0_a2_0_a2_3475; + wire com_tlm_u_tlm_tx_vc0_trn_load_counter_q_3476; + wire com_tlm_u_tlm_tx_vc0_trn_usr_sof_3477; + wire com_tlm_u_tlm_tx_vc0_trn_dsc_in_q_3478; + wire com_tlm_u_tlm_tx_vc0_trn_buf_av_zero_3479; + wire com_tlm_u_tlm_tx_vc0_trn_buffer_rdy_3480; + wire com_tlm_u_tlm_tx_vc0_trn_N_56477_i; + wire com_tlm_u_tlm_tx_vc0_trn_N_60417; + wire com_tlm_u_tlm_tx_vc0_trn_N_86735_i_3481; + wire com_tlm_u_tlm_tx_vc0_trn_usr_dsc_3482; + wire com_tlm_u_tlm_tx_vc0_trn_N_56472_i; + wire com_tlm_u_tlm_tx_vc0_trn_N_85889_i_3483; + wire com_tlm_u_tlm_tx_vc0_trn_N_16669_i; + wire com_tlm_u_tlm_tx_vc0_trn_un1_trn_tbuf_av_o_1_axb_0_3484; + wire com_tlm_u_tlm_tx_vc0_trn_N_42906_i; + wire com_tlm_u_tlm_tx_vc0_trn_usr_calc_eof_0_sqmuxa_i_0_7_3485; + wire com_tlm_u_tlm_tx_vc0_trn_usr_calc_eof_0_sqmuxa_i_0_5_3486; + wire com_tlm_u_tlm_tx_vc0_trn_usr_calc_eof_0_sqmuxa_i_0_0_3487; + wire com_tlm_u_tlm_tx_vc0_trn_N_56231_i; + wire com_tlm_u_tlm_tx_vc0_trn_N_56107_i; + wire com_tlm_u_tlm_tx_vc0_trn_N_86362_i_3488; + wire com_tlm_u_tlm_tx_vc0_trn_usr_calc_eof_3489; + wire com_tlm_u_tlm_tx_vc0_trn_N_56947_i; + wire com_tlm_u_tlm_tx_vc0_trn_N_61337; + wire com_tlm_u_tlm_tx_vc0_trn_d_o_4_i_0_0_62__3490; + wire com_tlm_u_tlm_tx_vc0_trn_d_o_4_i_0_0_61__3491; + wire com_tlm_u_tlm_tx_vc0_trn_d_o_4_i_0_0_59__3492; + wire com_tlm_u_tlm_tx_vc0_trn_d_o_4_i_0_0_57__3493; + wire com_tlm_u_tlm_tx_vc0_trn_trn_rem; + wire com_tlm_u_tlm_tx_vc0_trn_N_56499_i_i_3494; + wire com_tlm_u_tlm_tx_vc0_trn_N_60513_i_3495; + wire com_tlm_u_tlm_tx_vc0_trn_usr_eof_filt; + wire com_tlm_u_tlm_tx_vc0_trn_usr_eof_3496; + wire com_tlm_u_tlm_tx_vc0_trn_N_60512_i_3497; + wire com_tlm_u_tlm_tx_vc0_trn_un13_pkt_incoming_o_i_3498; + wire com_tlm_u_tlm_tx_vc0_trn_N_16671_i; + wire com_tlm_u_tlm_tx_vc0_trn_N_86698_i_3499; + wire com_tlm_u_tlm_tx_vc0_trn_usr_frame_in17; + wire com_tlm_u_tlm_tx_vc0_trn_N_56499_i; + wire com_tlm_u_tlm_tx_vc0_trn_N_16676_i; + wire com_tlm_u_tlm_tx_vc0_trn_eof_o_5_i_0_0_0_3500; + wire com_tlm_u_tlm_tx_vc0_trn_N_16678_i; + wire com_tlm_u_tlm_tx_vc0_trn_usr_errfwd_3501; + wire com_tlm_u_tlm_tx_vc0_trn_N_86736_i_3502; + wire com_tlm_u_tlm_tx_vc0_trn_usr_vld_3503; + wire com_tlm_u_tlm_tx_vc0_trn_usr_sof_filt; + wire com_tlm_u_tlm_tx_vc0_trn_usr_frame_3504; + wire com_tlm_u_tlm_tx_vc0_trn_N_86547_i_3505; + wire com_tlm_u_tlm_tx_vc0_trn_N_61322; + wire com_tlm_u_tlm_tx_vc0_trn_N_42903_i; + wire com_tlm_u_tlm_tx_vc0_trn_N_86737_i_3506; + wire com_tlm_u_tlm_tx_vc0_trn_cfg_frame_in_3507; + wire com_tlm_u_tlm_tx_vc0_trn_N_57342; + wire com_tlm_u_tlm_tx_vc0_trn_N_86293_i_3508; + wire com_tlm_u_tlm_tx_vc0_trn_usr_frame_in_3509; + wire com_tlm_u_tlm_tx_vc0_trn_trn_tdst_rdy_o_3_0_0_0_0_a2_0_0; + wire com_tlm_u_tlm_tx_vc0_trn_N_57343; + wire com_tlm_u_tlm_tx_vc0_trn_N_56234_i; + wire com_tlm_u_tlm_tx_vc0_trn_N_42911_i; + wire com_tlm_u_tlm_tx_vc0_trn_cfg_o_2; + wire com_tlm_u_tlm_tx_vc0_trn_buffer_rdy_3_i_0_0_3510; + wire com_tlm_u_tlm_tx_vc0_trn_buf_av_one_3511; + wire com_tlm_u_tlm_tx_vc0_trn_un1_trn_tbuf_av_o_1_axb_4_3512; + wire com_tlm_u_tlm_tx_vc0_trn_un1_trn_tbuf_av_o_1_axb_3_3513; + wire com_tlm_u_tlm_tx_vc0_trn_un1_trn_tbuf_av_o_1_axb_2_3514; + wire com_tlm_u_tlm_tx_vc0_trn_un1_trn_tbuf_av_o_1_axb_1_3515; + wire com_tlm_u_tlm_tx_vc0_trn_N_44071_i; + wire com_tlm_u_tlm_tx_vc0_trn_un1_pkts_in_trn_1_axbxc1_3516; + wire com_tlm_u_tlm_tx_vc0_trn_usr_start; + wire com_tlm_u_tlm_tx_vc0_trn_un1_pkts_in_trn_1_ac0_0_3517; + wire com_tlm_u_tlm_tx_vc0_trn_pkts_in_trn_1_sqmuxa_5917_i_0_0_3518; + wire com_tlm_u_tlm_tx_vc0_trn_un1_pkts_in_trn_1_axb0_3519; + wire com_tlm_u_tlm_tx_vc0_trn_pkts_in_trn28_i_0_39418_3520; + wire com_tlm_u_tlm_tx_vc0_trn_rem_o_5_0_0_0_o3_1_3521; + wire com_tlm_u_tlm_tx_vc0_trn_un1_usr_abort_8_0_0_a2_0_0_3522; + wire com_tlm_u_tlm_tx_vc0_trn_N_58356_1_0; + wire com_tlm_u_tlm_tx_vc0_trn_N_85887_i_3523; + wire com_tlm_u_tlm_tx_vc0_trn_N_85887_i_1_3524; + wire com_tlm_u_tlm_tx_vc0_trn_N_58355; + wire com_tlm_u_tlm_tx_vc0_trn_released_buf_x_3525; + wire com_tlm_u_tlm_tx_vc0_trn_start_frame_q_3526; + wire com_tlm_u_tlm_tx_vc0_trn_usr_eof_filt_q_4_; + wire com_tlm_u_tlm_tx_vc0_trn_usr_no_eof_err14; + wire com_tlm_u_tlm_tx_vc0_trn_N_42816_i; + wire com_tlm_u_tlm_tx_vc0_trn_N_42814_i; + wire com_tlm_u_tlm_tx_vc0_trn_N_42812_i; + wire com_tlm_u_tlm_tx_vc0_trn_N_42810_i; + wire com_tlm_u_tlm_tx_vc0_trn_N_42808_i; + wire com_tlm_u_tlm_tx_vc0_trn_N_42806_i; + wire com_tlm_u_tlm_tx_vc0_trn_N_42804_i; + wire com_tlm_u_tlm_tx_vc0_trn_N_42802_i; + wire com_tlm_u_tlm_tx_vc0_trn_N_42800_i; + wire com_tlm_u_tlm_tx_vc0_trn_N_42798_i; + wire com_tlm_u_tlm_tx_vc0_trn_N_42796_i; + wire com_tlm_u_tlm_tx_vc0_trn_N_42841_i; + wire com_tlm_u_tlm_tx_vc0_trn_N_42839_i; + wire com_tlm_u_tlm_tx_vc0_trn_N_42837_i; + wire com_tlm_u_tlm_tx_vc0_trn_N_42835_i; + wire com_tlm_u_tlm_tx_vc0_trn_N_42833_i; + wire com_tlm_u_tlm_tx_vc0_trn_N_42831_i; + wire com_tlm_u_tlm_tx_vc0_trn_N_42829_i; + wire com_tlm_u_tlm_tx_vc0_trn_N_86273_i_3527; + wire com_tlm_u_tlm_tx_vc0_trn_N_86272_i_3528; + wire com_tlm_u_tlm_tx_vc0_trn_N_86271_i_3529; + wire com_tlm_u_tlm_tx_vc0_trn_N_42824_i; + wire com_tlm_u_tlm_tx_vc0_trn_N_86270_i_3530; + wire com_tlm_u_tlm_tx_vc0_trn_N_42821_i; + wire com_tlm_u_tlm_tx_vc0_trn_N_86269_i_3531; + wire com_tlm_u_tlm_tx_vc0_trn_N_42818_i; + wire com_tlm_u_tlm_tx_vc0_trn_N_86281_i_3532; + wire com_tlm_u_tlm_tx_vc0_trn_N_86280_i_3533; + wire com_tlm_u_tlm_tx_vc0_trn_N_86279_i_3534; + wire com_tlm_u_tlm_tx_vc0_trn_N_86278_i_3535; + wire com_tlm_u_tlm_tx_vc0_trn_N_86277_i_3536; + wire com_tlm_u_tlm_tx_vc0_trn_N_86276_i_3537; + wire com_tlm_u_tlm_tx_vc0_trn_N_86275_i_3538; + wire com_tlm_u_tlm_tx_vc0_trn_N_86274_i_3539; + wire com_tlm_u_tlm_tx_vc0_trn_N_85835_i_3540; + wire com_tlm_u_tlm_tx_vc0_trn_N_42853_i; + wire com_tlm_u_tlm_tx_vc0_trn_N_42851_i; + wire com_tlm_u_tlm_tx_vc0_trn_N_42849_i; + wire com_tlm_u_tlm_tx_vc0_trn_N_42847_i; + wire com_tlm_u_tlm_tx_vc0_trn_N_42845_i; + wire com_tlm_u_tlm_tx_vc0_trn_N_42843_i; + wire com_tlm_u_tlm_tx_vc0_trn_N_86291_i_3541; + wire com_tlm_u_tlm_tx_vc0_trn_N_42882_i; + wire com_tlm_u_tlm_tx_vc0_trn_N_42880_i; + wire com_tlm_u_tlm_tx_vc0_trn_N_42878_i; + wire com_tlm_u_tlm_tx_vc0_trn_N_86290_i_3542; + wire com_tlm_u_tlm_tx_vc0_trn_N_86289_i_3543; + wire com_tlm_u_tlm_tx_vc0_trn_N_86288_i_3544; + wire com_tlm_u_tlm_tx_vc0_trn_N_86287_i_3545; + wire com_tlm_u_tlm_tx_vc0_trn_N_86286_i_3546; + wire com_tlm_u_tlm_tx_vc0_trn_N_86285_i_3547; + wire com_tlm_u_tlm_tx_vc0_trn_N_42870_i; + wire com_tlm_u_tlm_tx_vc0_trn_N_42868_i; + wire com_tlm_u_tlm_tx_vc0_trn_N_86284_i_3548; + wire com_tlm_u_tlm_tx_vc0_trn_N_86283_i_3549; + wire com_tlm_u_tlm_tx_vc0_trn_N_86282_i_3550; + wire com_tlm_u_tlm_tx_vc0_trn_N_86292_i_3551; + wire com_tlm_u_tlm_tx_vc0_trn_N_42897_i; + wire com_tlm_u_tlm_tx_vc0_trn_N_42895_i; + wire com_tlm_u_tlm_tx_vc0_trn_N_42893_i; + wire com_tlm_u_tlm_tx_vc0_trn_N_42891_i; + wire com_tlm_u_tlm_tx_vc0_trn_N_42889_i; + wire com_tlm_u_tlm_tx_vc0_trn_N_42887_i; + wire com_tlm_u_tlm_tx_vc0_trn_N_42885_i; + wire com_tlm_u_tlm_tx_vc0_trn_load_value10; + wire com_tlm_u_tlm_tx_vc0_trn_N_55997_i; + wire com_tlm_u_tlm_tx_vc0_trn_load_value10_i; + wire com_tlm_u_tlm_tx_vc0_trn_usr_abort_i_3552; + wire com_tlm_u_tlm_tx_vc0_trn_usr_abort_3553; + wire com_tlm_u_tlm_tx_vc0_trn_trn_tdst_dsc; + wire com_tlm_u_tlm_tx_vc0_trn_trn_tdst_rdy; + wire com_tlm_u_tlm_tx_vc0_trn_usr_eof_filt_q_1__3554; + wire com_tlm_u_tlm_tx_vc0_trn_GND_3555; + wire com_tlm_u_tlm_tx_vc0_trn_usr_eof_filt_q_N_6; + wire com_tlm_u_tlm_tx_vc0_trn_un1_trn_tbuf_av_o_1_cry_0_ma_3556; + wire com_tlm_u_tlm_tx_vc0_trn_VCC_3557; + wire com_tlm_u_tlm_tx_vc0_trn_load_value_6__3558; + wire com_tlm_u_tlm_tx_vc0_trn_load_value_0__3559; + wire com_tlm_u_tlm_tx_vc0_trn_load_counter_3560; + wire com_tlm_u_tlm_tx_vc0_trn_N_85836_i_3561; + wire com_tlm_u_tlm_tx_vc0_trn_usr_rem_3562; + wire com_tlm_u_tlm_tx_vc0_trn_N_85836_i_1_3563; + wire com_tlm_u_tlm_tx_vc0_trn_vld_o_5_i_0_a2_3564; + wire com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_un1_usr_d_i_3_cry_0_3565; + wire com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_un1_usr_d_i_3_cry_1_3566; + wire com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_un1_usr_d_i_3_cry_2_3567; + wire com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_GND_3568; + wire com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_un1_usr_d_i_3_cry_3_3569; + wire com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_un1_usr_d_i_3_cry_4_3570; + wire com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_un1_usr_d_i_3_axb_5_3571; + wire com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_usr_credits14_i_3572; + wire com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_usr_cat19_0_0_1_3573; + wire com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_N_86734_i_3574; + wire com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_N_86733_i_3575; + wire com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_frame_vld_o_1c_i; + wire com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_usr_dsc_q_3576; + wire com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_frame_vld_o14_0_i_0_o3_0_1_3577; + wire com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_un1_usr_d_i_3_s_5_3578; + wire com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_un1_usr_d_i_3_s_4_3579; + wire com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_un1_usr_d_i_3_s_3_3580; + wire com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_un1_usr_d_i_3_s_2_3581; + wire com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_un1_usr_d_i_3_s_1_3582; + wire com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_un1_usr_d_i_3_s_0_3583; + wire com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_N_56181_i_3584; + wire com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_usr_cat19_0_0_3_3585; + wire com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_cfg_credits_3586; + wire com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_usr_no_payload_3587; + wire com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_cfg_no_payload_3588; + wire com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_N_86700_i_3589; + wire com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_sof_q_3590; + wire com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_no_payload_o_2_i_m2_i_m3_i_m3_0_3591; + wire com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_N_10827_i; + wire com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_un1_usr_d_i_3_axb_4_3592; + wire com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_un1_usr_d_i_3_axb_3_3593; + wire com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_un1_usr_d_i_3_axb_2_3594; + wire com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_un1_usr_d_i_3_axb_1_3595; + wire com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_un1_usr_d_i_3_axb_0_3596; + wire com_tlm_u_tlm_tx_vc0_token_fifo_VCC_3597; + wire com_tlm_u_tlm_tx_vc0_token_fifo_tokens_loaded_0_sqmuxa; + wire com_tlm_u_tlm_tx_vc0_token_fifo_tokens_loaded_0_sqmuxa_0_a2_3_a2_1_3598; + wire com_tlm_u_tlm_tx_vc0_token_fifo_N_52001_i; + wire com_tlm_u_tlm_tx_vc0_token_fifo_un1_token_index_axbxc3_3599; + wire com_tlm_u_tlm_tx_vc0_token_fifo_un1_token_index_p4_3600; + wire com_tlm_u_tlm_tx_vc0_token_fifo_un1_token_index_axbxc2_3601; + wire com_tlm_u_tlm_tx_vc0_token_fifo_un1_token_index_axbxc1_3602; + wire com_tlm_u_tlm_tx_vc0_token_fifo_un1_token_index_axbxc0_3603; + wire com_tlm_u_tlm_tx_vc0_token_fifo_tokens_loaded_3604; + wire com_tlm_u_tlm_tx_vc0_token_fifo_t_fifo_GND_3605; + wire com_tlm_u_tlm_tx_vc0_token_fifo_t_fifo_un1_raddr_lo_1_s_1_1; + wire com_tlm_u_tlm_tx_vc0_token_fifo_t_fifo_un1_raddr_lo_1_cry_0_3606; + wire com_tlm_u_tlm_tx_vc0_token_fifo_t_fifo_un1_raddr_lo_1_s_2_1; + wire com_tlm_u_tlm_tx_vc0_token_fifo_t_fifo_un1_raddr_lo_1_cry_1_3607; + wire com_tlm_u_tlm_tx_vc0_token_fifo_t_fifo_un1_raddr_lo_1_s_3_1; + wire com_tlm_u_tlm_tx_vc0_token_fifo_t_fifo_un1_raddr_lo_1_cry_2_3608; + wire com_tlm_u_tlm_tx_vc0_token_fifo_t_fifo_N_86417_i_3609; + wire com_tlm_u_tlm_tx_vc0_token_fifo_t_fifo_un1_bkp_i_1_i_0_0_0_a2_2_3610; + wire com_tlm_u_tlm_tx_vc0_token_fifo_t_fifo_un1_raddr_lo_1_axb_0_3611; + wire com_tlm_u_tlm_tx_vc0_token_fifo_t_fifo_un1_raddr_lo_1_axb_3_3612; + wire com_tlm_u_tlm_tx_vc0_token_fifo_t_fifo_un1_raddr_lo_1_axb_2_3613; + wire com_tlm_u_tlm_tx_vc0_token_fifo_t_fifo_un1_raddr_lo_1_axb_1_3614; + wire com_tlm_u_tlm_tx_vc0_token_fifo_t_fifo_nxt_vld_o_3615; + wire com_tlm_u_tlm_tx_vc0_token_fifo_t_fifo_N_56062_i; + wire com_tlm_u_tlm_tx_vc0_token_fifo_t_fifo_vld_o_3616; + wire com_tlm_u_tlm_tx_vc0_token_fifo_t_fifo_N_56062_i_i_3617; + wire com_tlm_u_tlm_tx_vc0_frm_seq_oq_ren_3618; + wire com_tlm_u_tlm_tx_vc0_frm_seq_consumed_nph_3619; + wire com_tlm_u_tlm_tx_vc0_frm_seq_consumed_ph_3620; + wire com_tlm_u_tlm_tx_vc0_frm_seq_consumed_cplh_3621; + wire com_tlm_u_tlm_tx_vc0_frm_seq_GND_3622; + wire com_tlm_u_tlm_tx_vc0_frm_seq_un4_npd_diff_cry_0_3623; + wire com_tlm_u_tlm_tx_vc0_frm_seq_un4_npd_diff_cry_1_3624; + wire com_tlm_u_tlm_tx_vc0_frm_seq_un4_npd_diff_cry_2_3625; + wire com_tlm_u_tlm_tx_vc0_frm_seq_un4_npd_diff_cry_3_3626; + wire com_tlm_u_tlm_tx_vc0_frm_seq_un4_npd_diff_cry_4_3627; + wire com_tlm_u_tlm_tx_vc0_frm_seq_un4_npd_diff_cry_5_3628; + wire com_tlm_u_tlm_tx_vc0_frm_seq_un4_npd_diff_cry_6_3629; + wire com_tlm_u_tlm_tx_vc0_frm_seq_un4_npd_diff_cry_7_3630; + wire com_tlm_u_tlm_tx_vc0_frm_seq_un4_npd_diff_cry_8_3631; + wire com_tlm_u_tlm_tx_vc0_frm_seq_un4_npd_diff_cry_9_3632; + wire com_tlm_u_tlm_tx_vc0_frm_seq_un4_npd_diff_s_11_3633; + wire com_tlm_u_tlm_tx_vc0_frm_seq_un4_npd_diff_cry_10_3634; + wire com_tlm_u_tlm_tx_vc0_frm_seq_un4_cpld_diff_cry_0_3635; + wire com_tlm_u_tlm_tx_vc0_frm_seq_un4_cpld_diff_cry_1_3636; + wire com_tlm_u_tlm_tx_vc0_frm_seq_un4_cpld_diff_cry_2_3637; + wire com_tlm_u_tlm_tx_vc0_frm_seq_un4_cpld_diff_cry_3_3638; + wire com_tlm_u_tlm_tx_vc0_frm_seq_un4_cpld_diff_cry_4_3639; + wire com_tlm_u_tlm_tx_vc0_frm_seq_un4_cpld_diff_cry_5_3640; + wire com_tlm_u_tlm_tx_vc0_frm_seq_un4_cpld_diff_cry_6_3641; + wire com_tlm_u_tlm_tx_vc0_frm_seq_un4_cpld_diff_cry_7_3642; + wire com_tlm_u_tlm_tx_vc0_frm_seq_un4_cpld_diff_cry_8_3643; + wire com_tlm_u_tlm_tx_vc0_frm_seq_un4_cpld_diff_cry_9_3644; + wire com_tlm_u_tlm_tx_vc0_frm_seq_un4_cpld_diff_s_11_3645; + wire com_tlm_u_tlm_tx_vc0_frm_seq_un4_cpld_diff_cry_10_3646; + wire com_tlm_u_tlm_tx_vc0_frm_seq_un4_bnpd_diff_cry_0_3647; + wire com_tlm_u_tlm_tx_vc0_frm_seq_un4_bnpd_diff_cry_1_3648; + wire com_tlm_u_tlm_tx_vc0_frm_seq_un4_bnpd_diff_cry_2_3649; + wire com_tlm_u_tlm_tx_vc0_frm_seq_un4_bnpd_diff_cry_3_3650; + wire com_tlm_u_tlm_tx_vc0_frm_seq_un4_bnpd_diff_cry_4_3651; + wire com_tlm_u_tlm_tx_vc0_frm_seq_un4_bnpd_diff_cry_5_3652; + wire com_tlm_u_tlm_tx_vc0_frm_seq_un4_bnpd_diff_cry_6_3653; + wire com_tlm_u_tlm_tx_vc0_frm_seq_un4_bnpd_diff_cry_7_3654; + wire com_tlm_u_tlm_tx_vc0_frm_seq_un4_bnpd_diff_cry_8_3655; + wire com_tlm_u_tlm_tx_vc0_frm_seq_un4_bnpd_diff_cry_9_3656; + wire com_tlm_u_tlm_tx_vc0_frm_seq_un4_bnpd_diff_s_11_3657; + wire com_tlm_u_tlm_tx_vc0_frm_seq_un4_bnpd_diff_cry_10_3658; + wire com_tlm_u_tlm_tx_vc0_frm_seq_un4_pd_diff_cry_0_3659; + wire com_tlm_u_tlm_tx_vc0_frm_seq_un4_pd_diff_cry_1_3660; + wire com_tlm_u_tlm_tx_vc0_frm_seq_un4_pd_diff_cry_2_3661; + wire com_tlm_u_tlm_tx_vc0_frm_seq_un4_pd_diff_cry_3_3662; + wire com_tlm_u_tlm_tx_vc0_frm_seq_un4_pd_diff_cry_4_3663; + wire com_tlm_u_tlm_tx_vc0_frm_seq_un4_pd_diff_cry_5_3664; + wire com_tlm_u_tlm_tx_vc0_frm_seq_un4_pd_diff_cry_6_3665; + wire com_tlm_u_tlm_tx_vc0_frm_seq_un4_pd_diff_cry_7_3666; + wire com_tlm_u_tlm_tx_vc0_frm_seq_un4_pd_diff_cry_8_3667; + wire com_tlm_u_tlm_tx_vc0_frm_seq_un4_pd_diff_cry_9_3668; + wire com_tlm_u_tlm_tx_vc0_frm_seq_VCC_3669; + wire com_tlm_u_tlm_tx_vc0_frm_seq_un4_pd_diff_s_11_3670; + wire com_tlm_u_tlm_tx_vc0_frm_seq_un4_pd_diff_cry_10_3671; + wire com_tlm_u_tlm_tx_vc0_frm_seq_cplh_av; + wire com_tlm_u_tlm_tx_vc0_frm_seq_bq_holdoff13; + wire com_tlm_u_tlm_tx_vc0_frm_seq_header_vld_bq_3672; + wire com_tlm_u_tlm_tx_vc0_frm_seq_bq_no_payload_qq_3673; + wire com_tlm_u_tlm_tx_vc0_frm_seq_bq_holdoff_3674; + wire com_tlm_u_tlm_tx_vc0_frm_seq_bq_ren_3675; + wire com_tlm_u_tlm_tx_vc0_frm_seq_N_62984_i; + wire com_tlm_u_tlm_tx_vc0_frm_seq_bq_wen_3676; + wire com_tlm_u_tlm_tx_vc0_frm_seq_N_62975; + wire com_tlm_u_tlm_tx_vc0_frm_seq_ph_av; + wire com_tlm_u_tlm_tx_vc0_frm_seq_oq_no_payload_qq_3677; + wire com_tlm_u_tlm_tx_vc0_frm_seq_header_vld_oq_3678; + wire com_tlm_u_tlm_tx_vc0_frm_seq_N_62976; + wire com_tlm_u_tlm_tx_vc0_frm_seq_N_61285; + wire com_tlm_u_tlm_tx_vc0_frm_seq_bq_renc_i; + wire com_tlm_u_tlm_tx_vc0_frm_seq_last_buf_num_match_3; + wire com_tlm_u_tlm_tx_vc0_frm_seq_last_buf_num_match_3_NE_0_3679; + wire com_tlm_u_tlm_tx_vc0_frm_seq_last_buf_num_match_3_0_3680; + wire com_tlm_u_tlm_tx_vc0_frm_seq_header_vld_bq_3; + wire com_tlm_u_tlm_tx_vc0_frm_seq_nph_av; + wire com_tlm_u_tlm_tx_vc0_frm_seq_bq_vld; + wire com_tlm_u_tlm_tx_vc0_frm_seq_av_valid; + wire com_tlm_u_tlm_tx_vc0_frm_seq_nonposted_vld_oq_3; + wire com_tlm_u_tlm_tx_vc0_frm_seq_un4_cpld_diff_s_11_sf_3681; + wire com_tlm_u_tlm_tx_vc0_frm_seq_cpld_av_11_; + wire com_tlm_u_tlm_tx_vc0_frm_seq_un4_npd_diff_s_11_sf_3682; + wire com_tlm_u_tlm_tx_vc0_frm_seq_un4_pd_diff_s_11_sf_3683; + wire com_tlm_u_tlm_tx_vc0_frm_seq_pd_av_11_; + wire com_tlm_u_tlm_tx_vc0_frm_seq_un4_bnpd_diff_s_11_sf_3684; + wire com_tlm_u_tlm_tx_vc0_frm_seq_N_16926_i; + wire com_tlm_u_tlm_tx_vc0_frm_seq_header_vld_oq_7_u_i_0_0_0_39305_3685; + wire com_tlm_u_tlm_tx_vc0_frm_seq_N_58463; + wire com_tlm_u_tlm_tx_vc0_frm_seq_N_58460; + wire com_tlm_u_tlm_tx_vc0_frm_seq_N_16926_i_1; + wire com_tlm_u_tlm_tx_vc0_frm_seq_N_85820_i_3686; + wire com_tlm_u_tlm_tx_vc0_frm_seq_nxt_seq_state_0_sqmuxa_1; + wire com_tlm_u_tlm_tx_vc0_frm_seq_nxt_seq_state_0_sqmuxa_2; + wire com_tlm_u_tlm_tx_vc0_frm_seq_sq_vld; + wire com_tlm_u_tlm_tx_vc0_frm_seq_N_20410_i; + wire com_tlm_u_tlm_tx_vc0_frm_seq_N_58771; + wire com_tlm_u_tlm_tx_vc0_frm_seq_N_20410_i_1; + wire com_tlm_u_tlm_tx_vc0_frm_seq_N_16888_i; + wire com_tlm_u_tlm_tx_vc0_frm_seq_N_16890_i; + wire com_tlm_u_tlm_tx_vc0_frm_seq_consumed_cplh_10_i_0_0_1_1; + wire com_tlm_u_tlm_tx_vc0_frm_seq_N_85898_i_3687; + wire com_tlm_u_tlm_tx_vc0_frm_seq_N_58768; + wire com_tlm_u_tlm_tx_vc0_frm_seq_N_58767_1; + wire com_tlm_u_tlm_tx_vc0_frm_seq_N_58766; + wire com_tlm_u_tlm_tx_vc0_frm_seq_N_86359_i_3688; + wire com_tlm_u_tlm_tx_vc0_frm_seq_sq_nxt_vld; + wire com_tlm_u_tlm_tx_vc0_frm_seq_N_52360_i; + wire com_tlm_u_tlm_tx_vc0_frm_seq_last_buf_num_match_3689; + wire com_tlm_u_tlm_tx_vc0_frm_seq_N_16924_i; + wire com_tlm_u_tlm_tx_vc0_frm_seq_bq_wen_14_u_i_0_0_0; + wire com_tlm_u_tlm_tx_vc0_frm_seq_N_56190_i; + wire com_tlm_u_tlm_tx_vc0_frm_seq_N_9929_i; + wire com_tlm_u_tlm_tx_vc0_frm_seq_bq_rdy_3690; + wire com_tlm_u_tlm_tx_vc0_frm_seq_N_57072_i; + wire com_tlm_u_tlm_tx_vc0_frm_seq_N_9928_i; + wire com_tlm_u_tlm_tx_vc0_frm_seq_nonposted_vld_oq_3691; + wire com_tlm_u_tlm_tx_vc0_frm_seq_N_63484; + wire com_tlm_u_tlm_tx_vc0_frm_seq_N_57053; + wire com_tlm_u_tlm_tx_vc0_frm_seq_N_56218_i; + wire com_tlm_u_tlm_tx_vc0_frm_seq_N_56491_i_i_3692; + wire com_tlm_u_tlm_tx_vc0_frm_seq_nxt_queue_state_1_sqmuxa_1; + wire com_tlm_u_tlm_tx_vc0_frm_seq_sq_wen_3693; + wire com_tlm_u_tlm_tx_vc0_frm_seq_un4_pd_diff_axb_5_3694; + wire com_tlm_u_tlm_tx_vc0_frm_seq_pd_av_5_; + wire com_tlm_u_tlm_tx_vc0_frm_seq_un4_pd_diff_axb_4_3695; + wire com_tlm_u_tlm_tx_vc0_frm_seq_pd_av_4_; + wire com_tlm_u_tlm_tx_vc0_frm_seq_un4_pd_diff_axb_3_3696; + wire com_tlm_u_tlm_tx_vc0_frm_seq_pd_av_3_; + wire com_tlm_u_tlm_tx_vc0_frm_seq_un4_pd_diff_axb_2_3697; + wire com_tlm_u_tlm_tx_vc0_frm_seq_pd_av_2_; + wire com_tlm_u_tlm_tx_vc0_frm_seq_un4_pd_diff_axb_1_3698; + wire com_tlm_u_tlm_tx_vc0_frm_seq_pd_av_1_; + wire com_tlm_u_tlm_tx_vc0_frm_seq_un4_pd_diff_axb_0_3699; + wire com_tlm_u_tlm_tx_vc0_frm_seq_pd_av_0_; + wire com_tlm_u_tlm_tx_vc0_frm_seq_un4_bnpd_diff_cry_10_sf_3700; + wire com_tlm_u_tlm_tx_vc0_frm_seq_un4_bnpd_diff_cry_9_sf_3701; + wire com_tlm_u_tlm_tx_vc0_frm_seq_un4_bnpd_diff_cry_8_sf_3702; + wire com_tlm_u_tlm_tx_vc0_frm_seq_un4_bnpd_diff_cry_7_sf_3703; + wire com_tlm_u_tlm_tx_vc0_frm_seq_un4_bnpd_diff_cry_6_sf_3704; + wire com_tlm_u_tlm_tx_vc0_frm_seq_un4_bnpd_diff_axb_5_3705; + wire com_tlm_u_tlm_tx_vc0_frm_seq_un4_bnpd_diff_axb_4_3706; + wire com_tlm_u_tlm_tx_vc0_frm_seq_un4_bnpd_diff_axb_3_3707; + wire com_tlm_u_tlm_tx_vc0_frm_seq_un4_bnpd_diff_axb_2_3708; + wire com_tlm_u_tlm_tx_vc0_frm_seq_un4_bnpd_diff_axb_1_3709; + wire com_tlm_u_tlm_tx_vc0_frm_seq_un4_bnpd_diff_axb_0_3710; + wire com_tlm_u_tlm_tx_vc0_frm_seq_un4_cpld_diff_axb_5_3711; + wire com_tlm_u_tlm_tx_vc0_frm_seq_cpld_av_5_; + wire com_tlm_u_tlm_tx_vc0_frm_seq_un4_cpld_diff_axb_4_3712; + wire com_tlm_u_tlm_tx_vc0_frm_seq_cpld_av_4_; + wire com_tlm_u_tlm_tx_vc0_frm_seq_un4_cpld_diff_axb_3_3713; + wire com_tlm_u_tlm_tx_vc0_frm_seq_cpld_av_3_; + wire com_tlm_u_tlm_tx_vc0_frm_seq_un4_cpld_diff_axb_2_3714; + wire com_tlm_u_tlm_tx_vc0_frm_seq_cpld_av_2_; + wire com_tlm_u_tlm_tx_vc0_frm_seq_un4_cpld_diff_axb_1_3715; + wire com_tlm_u_tlm_tx_vc0_frm_seq_cpld_av_1_; + wire com_tlm_u_tlm_tx_vc0_frm_seq_un4_cpld_diff_axb_0_3716; + wire com_tlm_u_tlm_tx_vc0_frm_seq_cpld_av_0_; + wire com_tlm_u_tlm_tx_vc0_frm_seq_un4_npd_diff_axb_5_3717; + wire com_tlm_u_tlm_tx_vc0_frm_seq_un4_npd_diff_axb_4_3718; + wire com_tlm_u_tlm_tx_vc0_frm_seq_un4_npd_diff_axb_3_3719; + wire com_tlm_u_tlm_tx_vc0_frm_seq_un4_npd_diff_axb_2_3720; + wire com_tlm_u_tlm_tx_vc0_frm_seq_un4_npd_diff_axb_1_3721; + wire com_tlm_u_tlm_tx_vc0_frm_seq_un4_npd_diff_axb_0_3722; + wire com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_GND_3723; + wire com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_un1_raddr_lo_1_s_1_2; + wire com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_un1_raddr_lo_1_cry_0_3724; + wire com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_un1_raddr_lo_1_s_2_2; + wire com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_un1_raddr_lo_1_cry_1_3725; + wire com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_un1_raddr_lo_1_s_3_2; + wire com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_un1_raddr_lo_1_cry_2_3726; + wire com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_oq_vld; + wire com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_un1_raddr_lo_1_axb_0_3727; + wire com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_N_86416_i_3728; + wire com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_un1_bkp_i_1_i_0_0_0_a2_0_2_3729; + wire com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_srl_wen; + wire com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_N_59232_i_3730; + wire com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_un1_raddr_lo_1_axb_3_3731; + wire com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_un1_raddr_lo_1_axb_2_3732; + wire com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_un1_raddr_lo_1_axb_1_3733; + wire com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_nxt_vld_o_1; + wire com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_N_62984_i_i_3734; + wire com_tlm_u_tlm_tx_vc0_frm_seq_bq_fifo_GND_3735; + wire com_tlm_u_tlm_tx_vc0_frm_seq_bq_fifo_un1_raddr_lo_1_s_1_3; + wire com_tlm_u_tlm_tx_vc0_frm_seq_bq_fifo_un1_raddr_lo_1_cry_0_3736; + wire com_tlm_u_tlm_tx_vc0_frm_seq_bq_fifo_un1_raddr_lo_1_s_2_3; + wire com_tlm_u_tlm_tx_vc0_frm_seq_bq_fifo_un1_raddr_lo_1_cry_1_3737; + wire com_tlm_u_tlm_tx_vc0_frm_seq_bq_fifo_un1_raddr_lo_1_s_3_3; + wire com_tlm_u_tlm_tx_vc0_frm_seq_bq_fifo_un1_raddr_lo_1_cry_2_3738; + wire com_tlm_u_tlm_tx_vc0_frm_seq_bq_fifo_N_86367_i_3739; + wire com_tlm_u_tlm_tx_vc0_frm_seq_bq_fifo_un1_bkp_i_1_i_0_0_0_0_a2_2_3740; + wire com_tlm_u_tlm_tx_vc0_frm_seq_bq_fifo_un1_raddr_lo_1_axb_0_3741; + wire com_tlm_u_tlm_tx_vc0_frm_seq_bq_fifo_un1_raddr_lo_1_axb_3_3742; + wire com_tlm_u_tlm_tx_vc0_frm_seq_bq_fifo_un1_raddr_lo_1_axb_2_3743; + wire com_tlm_u_tlm_tx_vc0_frm_seq_bq_fifo_un1_raddr_lo_1_axb_1_3744; + wire com_tlm_u_tlm_tx_vc0_frm_seq_bq_fifo_nxt_vld_o_0; + wire com_tlm_u_tlm_tx_vc0_frm_seq_bq_fifo_N_56063_i; + wire com_tlm_u_tlm_tx_vc0_frm_seq_bq_fifo_N_56063_i_i_3745; + wire com_tlm_u_tlm_tx_vc0_frm_seq_sq_fifo_GND_3746; + wire com_tlm_u_tlm_tx_vc0_frm_seq_sq_fifo_un1_raddr_lo_1_s_1_4; + wire com_tlm_u_tlm_tx_vc0_frm_seq_sq_fifo_un1_raddr_lo_1_cry_0_3747; + wire com_tlm_u_tlm_tx_vc0_frm_seq_sq_fifo_un1_raddr_lo_1_s_2_4; + wire com_tlm_u_tlm_tx_vc0_frm_seq_sq_fifo_un1_raddr_lo_1_cry_1_3748; + wire com_tlm_u_tlm_tx_vc0_frm_seq_sq_fifo_un1_raddr_lo_1_s_3_4; + wire com_tlm_u_tlm_tx_vc0_frm_seq_sq_fifo_un1_raddr_lo_1_cry_2_3749; + wire com_tlm_u_tlm_tx_vc0_frm_seq_sq_fifo_N_56520_i_i; + wire com_tlm_u_tlm_tx_vc0_frm_seq_sq_fifo_un1_raddr_lo_1_axb_0_3750; + wire com_tlm_u_tlm_tx_vc0_frm_seq_sq_fifo_N_87187_i_3751; + wire com_tlm_u_tlm_tx_vc0_frm_seq_sq_fifo_un1_bkp_i_1_i_0_0_0_0_a2_0_2_3752; + wire com_tlm_u_tlm_tx_vc0_frm_seq_sq_fifo_srl_wen; + wire com_tlm_u_tlm_tx_vc0_frm_seq_sq_fifo_N_59263_i_3753; + wire com_tlm_u_tlm_tx_vc0_frm_seq_sq_fifo_un1_ct_o_axbxc2_3754; + wire com_tlm_u_tlm_tx_vc0_frm_seq_sq_fifo_un1_ct_o_p4_3755; + wire com_tlm_u_tlm_tx_vc0_frm_seq_sq_fifo_un1_ct_o_axbxc1_3756; + wire com_tlm_u_tlm_tx_vc0_frm_seq_sq_fifo_un1_ct_o_axb0_3757; + wire com_tlm_u_tlm_tx_vc0_frm_seq_sq_fifo_N_56519_i; + wire com_tlm_u_tlm_tx_vc0_frm_seq_sq_fifo_un1_raddr_lo_1_axb_3_3758; + wire com_tlm_u_tlm_tx_vc0_frm_seq_sq_fifo_un1_raddr_lo_1_axb_2_3759; + wire com_tlm_u_tlm_tx_vc0_frm_seq_sq_fifo_un1_raddr_lo_1_axb_1_3760; + wire com_tlm_u_tlm_tx_vc0_frm_seq_sq_fifo_N_56061_i_i_3761; + wire com_tlm_u_tlm_tx_vc0_frm_seq_sq_fifo_N_56061_i; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un7_credits_ok_cry_0_3762; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un7_credits_ok_cry_1_3763; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un7_credits_ok_cry_2_3764; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un7_credits_ok_cry_3_3765; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un7_credits_ok_cry_4_3766; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un7_credits_ok_cry_5_3767; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un7_credits_ok_cry_6_3768; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un7_credits_ok_cry_7_3769; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un7_credits_ok_cry_8_3770; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un7_credits_ok_cry_9_3771; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un7_credits_ok_cry_10_3772; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_fc_diff_header_cry_0_3773; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_fc_diff_header_cry_1_3774; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_fc_diff_header_cry_2_3775; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_fc_diff_header_cry_3_3776; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_fc_diff_header_cry_4_3777; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_fc_diff_header_cry_5_3778; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_fc_diff_header_cry_6_3779; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_PD_1_cry_0_0_3780; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_PD_1_cry_1_0_3781; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_PD_1_s_1_3782; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_PD_1_cry_0_3783; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_PD_1_cry_2_0_3784; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_PD_1_s_2_3785; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_PD_1_cry_1_3786; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_PD_1_cry_3_0_3787; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_PD_1_s_3_3788; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_PD_1_cry_2_3789; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_PD_1_cry_4_0_3790; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_PD_1_s_4_3791; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_PD_1_cry_3_3792; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_PD_1_cry_5_0_3793; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_PD_1_s_5_3794; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_PD_1_cry_4_3795; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_PD_1_s_6_3796; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_PD_1_cry_5_3797; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_PD_1_s_7_3798; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_PD_1_cry_6_3799; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_PD_1_s_8_3800; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_PD_1_cry_7_3801; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_PD_1_s_9_3802; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_PD_1_cry_8_3803; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_PD_1_s_10_3804; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_PD_1_cry_9_3805; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_PD_1_s_11_3806; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_PD_1_cry_10_3807; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_NPD_1_cry_0_0_3808; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_NPD_1_cry_1_0_3809; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_NPD_1_s_1_3810; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_NPD_1_cry_0_3811; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_NPD_1_cry_2_0_3812; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_NPD_1_s_2_3813; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_NPD_1_cry_1_3814; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_NPD_1_cry_3_0_3815; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_NPD_1_s_3_3816; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_NPD_1_cry_2_3817; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_NPD_1_cry_4_0_3818; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_NPD_1_s_4_3819; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_NPD_1_cry_3_3820; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_NPD_1_cry_5_0_3821; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_NPD_1_s_5_3822; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_NPD_1_cry_4_3823; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_NPD_1_s_6_3824; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_NPD_1_cry_5_3825; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_NPD_1_s_7_3826; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_NPD_1_cry_6_3827; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_NPD_1_s_8_3828; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_NPD_1_cry_7_3829; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_NPD_1_s_9_3830; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_NPD_1_cry_8_3831; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_NPD_1_s_10_3832; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_NPD_1_cry_9_3833; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_NPD_1_s_11_3834; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_NPD_1_cry_10_3835; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_CPLD_1_cry_0_0_3836; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_CPLD_1_cry_1_0_3837; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_CPLD_1_s_1_3838; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_CPLD_1_cry_0_3839; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_CPLD_1_cry_2_0_3840; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_CPLD_1_s_2_3841; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_CPLD_1_cry_1_3842; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_CPLD_1_cry_3_0_3843; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_CPLD_1_s_3_3844; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_CPLD_1_cry_2_3845; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_CPLD_1_cry_4_0_3846; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_CPLD_1_s_4_3847; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_CPLD_1_cry_3_3848; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_CPLD_1_cry_5_0_3849; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_CPLD_1_s_5_3850; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_CPLD_1_cry_4_3851; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_CPLD_1_s_6_3852; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_CPLD_1_cry_5_3853; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_CPLD_1_s_7_3854; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_CPLD_1_cry_6_3855; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_CPLD_1_s_8_3856; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_CPLD_1_cry_7_3857; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_CPLD_1_s_9_3858; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_CPLD_1_cry_8_3859; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_CPLD_1_s_10_3860; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_CPLD_1_cry_9_3861; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_CPLD_1_s_11_3862; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_CPLD_1_cry_10_3863; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_VCC_3864; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_fc_diff_data_cry_0_3865; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_fc_diff_data_cry_1_3866; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_fc_diff_data_cry_2_3867; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_fc_diff_data_cry_3_3868; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_fc_diff_data_cry_4_3869; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_fc_diff_data_cry_5_3870; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_fc_diff_data_cry_6_3871; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_fc_diff_data_cry_7_3872; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_fc_diff_data_cry_8_3873; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_fc_diff_data_cry_9_3874; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_fc_diff_data_cry_10_3875; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_GND_3876; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_cpld_av_o_6_cry_0_0_3877; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_cpld_av_o_6_cry_1_0_3878; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_cpld_av_o_6_cry_0_3879; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_cpld_av_o_6_cry_2_0_3880; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_cpld_av_o_6_cry_1_3881; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_cpld_av_o_6_cry_3_0_3882; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_cpld_av_o_6_cry_2_3883; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_cpld_av_o_6_cry_4_0_3884; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_cpld_av_o_6_cry_3_3885; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_cpld_av_o_6_cry_5_0_3886; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_cpld_av_o_6_cry_4_3887; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_cpld_av_o_6_cry_6_0_3888; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_cpld_av_o_6_cry_5_3889; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_cpld_av_o_6_cry_7_0_3890; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_cpld_av_o_6_cry_6_3891; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_cpld_av_o_6_cry_8_0_3892; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_cpld_av_o_6_cry_7_3893; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_cpld_av_o_6_cry_9_0_3894; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_cpld_av_o_6_cry_8_3895; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_cpld_av_o_6_cry_10_0_3896; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_cpld_av_o_6_cry_9_3897; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_cpld_av_o_6_cry_10_3898; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_npd_av_o_6_cry_0_0_3899; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_npd_av_o_6_cry_1_0_3900; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_npd_av_o_6_cry_0_3901; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_npd_av_o_6_cry_2_0_3902; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_npd_av_o_6_cry_1_3903; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_npd_av_o_6_cry_3_0_3904; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_npd_av_o_6_cry_2_3905; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_npd_av_o_6_cry_4_0_3906; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_npd_av_o_6_cry_3_3907; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_npd_av_o_6_cry_5_0_3908; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_npd_av_o_6_cry_4_3909; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_npd_av_o_6_cry_6_0_3910; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_npd_av_o_6_cry_5_3911; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_npd_av_o_6_cry_7_0_3912; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_npd_av_o_6_cry_6_3913; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_npd_av_o_6_cry_8_0_3914; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_npd_av_o_6_cry_7_3915; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_npd_av_o_6_cry_9_0_3916; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_npd_av_o_6_cry_8_3917; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_npd_av_o_6_cry_10_0_3918; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_npd_av_o_6_cry_9_3919; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_npd_av_o_6_cry_10_3920; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_pd_av_o_6_cry_0_0_3921; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_pd_av_o_6_cry_1_0_3922; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_pd_av_o_6_cry_0_3923; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_pd_av_o_6_cry_2_0_3924; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_pd_av_o_6_cry_1_3925; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_pd_av_o_6_cry_3_0_3926; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_pd_av_o_6_cry_2_3927; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_pd_av_o_6_cry_4_0_3928; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_pd_av_o_6_cry_3_3929; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_pd_av_o_6_cry_5_0_3930; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_pd_av_o_6_cry_4_3931; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_pd_av_o_6_cry_6_0_3932; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_pd_av_o_6_cry_5_3933; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_pd_av_o_6_cry_7_0_3934; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_pd_av_o_6_cry_6_3935; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_pd_av_o_6_cry_8_0_3936; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_pd_av_o_6_cry_7_3937; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_pd_av_o_6_cry_9_0_3938; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_pd_av_o_6_cry_8_3939; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_pd_av_o_6_cry_10_0_3940; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_pd_av_o_6_cry_9_3941; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_pd_av_o_6_cry_10_3942; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_PD_1_axb_0_3943; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_NPD_1_axb_0_3944; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_CPLD_1_axb_0_3945; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_init_cplc_3946; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_init_npc_3947; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_init_pc_3948; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_init_vld_q_3949; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_infinite_PH_3950; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_infinite_NPH_3951; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_new_limit_data_ok; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_ph_av_o_6_3_3952; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_nph_av_o_6_3_3953; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_infinite_CPLH_3_3954; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_N_87844_i_3955; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_update_p_3956; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_init_p_3957; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_N_87845_i_3958; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_update_np_3959; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_init_np_3960; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_N_87846_i_3961; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_update_cpl_3962; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_init_cpl_3963; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_N_70880_i_3964; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_infinite_header_q_2_0_a2_4_3965; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_infinite_header_q_2_0_a2_0_3966; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_infinite_data_q_2_0_a2_8_3967; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_infinite_data_q_2_0_a2_7_3968; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_infinite_data_q_2_0_a2_6_3969; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_fc_diff_data_axb_11_3970; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_fc_diff_header_axb_7_3971; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_infinite_CPLH_3972; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_infinite_header_q_5_0_0_3973; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_infinite_data_q_5_0_0_3974; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_N_16839_i_3975; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_suspend_rdy_o_3_3976; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_update_cpl_3; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_update_np_3; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_update_p_3; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_update_vld_q_3977; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_av_valid_o_4; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_q_3978; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_err_fc_o13; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_update_vld_qq_3979; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_init_vld_qq_3980; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_new_limit_header_ok_3_0_a2_3981; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_N_9377_i_3982; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_infinite_CPLH_4_3983; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_infinite_CPLH_2_3984; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_infinite_CPLH_1_3985; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_infinite_CPLH_0_3986; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_N_9379_i_3987; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_nph_av_o_6_4_3988; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_nph_av_o_6_2_3989; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_nph_av_o_6_1_3990; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_nph_av_o_6_0_3991; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_N_9378_i_3992; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_ph_av_o_6_4_3993; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_ph_av_o_6_2_3994; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_ph_av_o_6_1_3995; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_ph_av_o_6_0_3996; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_N_32455_i; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_N_32453_i; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_N_32451_i; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_N_32449_i; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_N_32447_i; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_N_32445_i; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_N_32443_i; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_N_32441_i; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_N_32439_i; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_N_32437_i; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_N_32435_i; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_N_32433_i; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_N_61373; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_N_85833_i_3997; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_av_hdr_cred_7_iv_i_0_0_0_3998; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un8_suspend_cat_axbxc1_3999; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un7_credits_ok_cry_11_4000; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_av_hdr_cred_4001; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_CPLD_1_axb_11_4002; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_CPLD_1_axb_10_4003; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_CPLD_1_axb_9_4004; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_CPLD_1_axb_8_4005; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_CPLD_1_axb_7_4006; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_CPLD_1_axb_6_4007; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_CPLD_1_axb_5_4008; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_CPLD_1_axb_4_4009; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_CPLD_1_axb_3_4010; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_CPLD_1_axb_2_4011; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_CPLD_1_axb_1_4012; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_NPD_1_axb_11_4013; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_NPD_1_axb_10_4014; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_NPD_1_axb_9_4015; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_NPD_1_axb_8_4016; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_NPD_1_axb_7_4017; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_NPD_1_axb_6_4018; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_NPD_1_axb_5_4019; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_NPD_1_axb_4_4020; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_NPD_1_axb_3_4021; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_NPD_1_axb_2_4022; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_NPD_1_axb_1_4023; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_PD_1_axb_11_4024; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_PD_1_axb_10_4025; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_PD_1_axb_9_4026; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_PD_1_axb_8_4027; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_PD_1_axb_7_4028; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_PD_1_axb_6_4029; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_PD_1_axb_5_4030; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_PD_1_axb_4_4031; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_PD_1_axb_3_4032; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_PD_1_axb_2_4033; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_PD_1_axb_1_4034; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_cpld_av_o_6_axb_10_4035; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_cpld_av_o_6_axb_9_4036; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_cpld_av_o_6_axb_8_4037; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_cpld_av_o_6_axb_7_4038; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_cpld_av_o_6_axb_6_4039; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_cpld_av_o_6_axb_5_4040; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_cpld_av_o_6_axb_4_4041; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_cpld_av_o_6_axb_3_4042; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_cpld_av_o_6_axb_2_4043; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_cpld_av_o_6_axb_1_4044; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_cpld_av_o_6_axb_0_4045; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_npd_av_o_6_axb_10_4046; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_npd_av_o_6_axb_9_4047; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_npd_av_o_6_axb_8_4048; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_npd_av_o_6_axb_7_4049; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_npd_av_o_6_axb_6_4050; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_npd_av_o_6_axb_5_4051; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_npd_av_o_6_axb_4_4052; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_npd_av_o_6_axb_3_4053; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_npd_av_o_6_axb_2_4054; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_npd_av_o_6_axb_1_4055; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_npd_av_o_6_axb_0_4056; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_pd_av_o_6_axb_10_4057; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_pd_av_o_6_axb_9_4058; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_pd_av_o_6_axb_8_4059; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_pd_av_o_6_axb_7_4060; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_pd_av_o_6_axb_6_4061; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_pd_av_o_6_axb_5_4062; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_pd_av_o_6_axb_4_4063; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_pd_av_o_6_axb_3_4064; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_pd_av_o_6_axb_2_4065; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_pd_av_o_6_axb_1_4066; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_pd_av_o_6_axb_0_4067; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_N_32423_i; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_infinite_header_qq_4068; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_infinite_data_qq_4069; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_infinite_header_q_2; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_infinite_header_q_4070; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_infinite_data_q_2; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_infinite_data_q_4071; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_infinite_header_qq_4072; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_infinite_data_qq_4073; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_infinite_header_q_5; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_infinite_header_q_4074; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_infinite_data_q_5; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_infinite_data_q_4075; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_infinite_CPLD_i_4076; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_infinite_NPD_i_4077; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_infinite_PD_i_4078; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_cpld_av_o_6_axb_11_4079; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_infinite_CPLD_4080; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_npd_av_o_6_axb_11_4081; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_infinite_NPD_4082; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_pd_av_o_6_axb_11_4083; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_infinite_PD_4084; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_fc_diff_data_axb_10_4085; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_fc_diff_data_axb_9_4086; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_fc_diff_data_axb_8_4087; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_fc_diff_data_axb_7_4088; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_fc_diff_data_axb_6_4089; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_fc_diff_data_axb_5_4090; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_fc_diff_data_axb_4_4091; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_fc_diff_data_axb_3_4092; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_fc_diff_data_axb_2_4093; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_fc_diff_data_axb_1_4094; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_fc_diff_data_axb_0_4095; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_fc_diff_header_axb_6_4096; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_fc_diff_header_axb_5_4097; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_fc_diff_header_axb_4_4098; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_fc_diff_header_axb_3_4099; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_fc_diff_header_axb_2_4100; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_fc_diff_header_axb_1_4101; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_fc_diff_header_axb_0_4102; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_av_data_cred_i_11__4103; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_av_data_cred_i_10__4104; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_av_data_cred_i_9__4105; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_av_data_cred_i_8__4106; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_av_data_cred_i_7__4107; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_av_data_cred_i_6__4108; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un7_credits_ok_axb_5_i_4109; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un7_credits_ok_axb_4_i_4110; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un7_credits_ok_axb_3_i_4111; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_av_data_cred_i_2__4112; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_av_data_cred_i_1__4113; + wire com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un7_credits_ok_axb_0_i_4114; + wire com_tlm_u_tlm_tx_pm_ctrl_GND_4115; + wire com_tlm_u_tlm_tx_pm_ctrl_un1_cfg_ct_s_1_4116; + wire com_tlm_u_tlm_tx_pm_ctrl_un1_cfg_ct_cry_0_4117; + wire com_tlm_u_tlm_tx_pm_ctrl_un1_cfg_ct_s_2_4118; + wire com_tlm_u_tlm_tx_pm_ctrl_un1_cfg_ct_cry_1_4119; + wire com_tlm_u_tlm_tx_pm_ctrl_un1_cfg_ct_s_3_4120; + wire com_tlm_u_tlm_tx_pm_ctrl_un1_cfg_ct_cry_2_4121; + wire com_tlm_u_tlm_tx_pm_ctrl_un1_cfg_ct_s_4_4122; + wire com_tlm_u_tlm_tx_pm_ctrl_un1_cfg_ct_cry_3_4123; + wire com_tlm_u_tlm_tx_pm_ctrl_un1_cfg_ct_axb_0_4124; + wire com_tlm_u_tlm_tx_pm_ctrl_ppm_suspend_ok_o_3; + wire com_tlm_u_tlm_tx_pm_ctrl_cfg_pending_4125; + wire com_tlm_u_tlm_tx_pm_ctrl_N_58770; + wire com_tlm_u_tlm_tx_pm_ctrl_N_21863_i_4126; + wire com_tlm_u_tlm_tx_pm_ctrl_un1_cfg_ct_axb_4_4127; + wire com_tlm_u_tlm_tx_pm_ctrl_un1_cfg_ct_axb_3_4128; + wire com_tlm_u_tlm_tx_pm_ctrl_un1_cfg_ct_axb_2_4129; + wire com_tlm_u_tlm_tx_pm_ctrl_cfg_ct23; + wire com_tlm_u_tlm_tx_pm_ctrl_un1_cfg_ct_axb_1_4130; + wire com_tlm_u_tlm_rx_ds_cpl; + wire com_tlm_u_tlm_rx_ds_rem; + wire com_tlm_u_tlm_rx_ds_eof_i; + wire com_tlm_u_tlm_rx_ds_src_rdy; + wire com_tlm_u_tlm_rx_ds_eof; + wire com_tlm_u_tlm_rx_ds_dsc; + wire com_tlm_u_tlm_rx_wen_aux_oq_3; + wire com_tlm_u_tlm_rx_ds_bar_src_rdy; + wire com_tlm_u_tlm_rx_ds_np; + wire com_tlm_u_tlm_rx_ds_sof; + wire com_tlm_u_tlm_rx_ds_cfg; + wire com_tlm_u_tlm_rx_fc_use_cpl; + wire com_tlm_u_tlm_rx_fc_sched_np; + wire com_tlm_u_tlm_rx_fc_req_np_dst_rdy; + wire com_tlm_u_tlm_rx_fc_send_state_0_sqmuxa_0; + wire com_tlm_u_tlm_rx_fc_use_np; + wire com_tlm_u_tlm_rx_fc_sched_p; + wire com_tlm_u_tlm_rx_fc_req_p_dst_rdy; + wire com_tlm_u_tlm_rx_fc_send_state_0_sqmuxa; + wire com_tlm_u_tlm_rx_fc_use_p; + wire com_tlm_u_tlm_rx_fc_unuse; + wire com_tlm_u_tlm_rx_aspm_ok_i; + wire com_tlm_u_tlm_rx_vc0_N_55978_i; + wire com_tlm_u_tlm_rx_vc0_cmmt_reof; + wire com_tlm_u_tlm_rx_vc0_N_55948_i; + wire com_tlm_u_tlm_rx_vc0_un1_trn_active_word_0_a2_i_o2_0; + wire com_tlm_u_tlm_rx_vc0_trn_reof; + wire com_tlm_u_tlm_rx_vc0_cmmt_rsof; + wire com_tlm_u_tlm_rx_vc0_N_56232_i; + wire com_tlm_u_tlm_rx_vc0_N_60499; + wire com_tlm_u_tlm_rx_vc0_trn_rsof; + wire com_tlm_u_tlm_rx_vc0_trn_rrem; + wire com_tlm_u_tlm_rx_vc0_trn_rsrc_rdy; + wire com_tlm_u_tlm_rx_vc0_fc_free_eof; + wire com_tlm_u_tlm_rx_vc0_fifo_cpl; + wire com_tlm_u_tlm_rx_vc0_fifo_np; + wire com_tlm_u_tlm_rx_vc0_fc_free_cpl; + wire com_tlm_u_tlm_rx_vc0_fc_free_np; + wire com_tlm_u_tlm_rx_vc0_fc_free_p; + wire com_tlm_u_tlm_rx_vc0_fc_free_1header; + wire com_tlm_u_tlm_rx_vc0_fc_free_1data; + wire com_tlm_u_tlm_rx_vc0_rd_mon_GND_4131; + wire com_tlm_u_tlm_rx_vc0_rd_mon_unaligned_header_q_4132; + wire com_tlm_u_tlm_rx_vc0_rd_mon_N_86433_i_4133; + wire com_tlm_u_tlm_rx_vc0_rd_mon_N_86550_i_4134; + wire com_tlm_u_tlm_rx_vc0_rd_mon_N_61417; + wire com_tlm_u_tlm_rx_vc0_rd_mon_N_58443; + wire com_tlm_u_tlm_rx_vc0_rd_mon_N_58442; + wire com_tlm_u_tlm_rx_vc0_rd_mon_N_60499_i_4135; + wire com_tlm_u_tlm_rx_vc0_rd_mon_N_60501_3; + wire com_tlm_u_tlm_rx_vc0_rd_mon_fc_free_p_o_3_4136; + wire com_tlm_u_tlm_rx_vc0_rd_mon_np_q_4137; + wire com_tlm_u_tlm_rx_vc0_rd_mon_cpl_q_4138; + wire com_tlm_u_tlm_rx_vc0_rd_mon_N_56476_i_0_i_4139; + wire com_tlm_u_tlm_rx_vc0_rd_mon_N_56116_i; + wire com_tlm_u_tlm_rx_vc0_rd_mon_N_86549_i_4140; + wire com_tlm_u_tlm_rx_vc0_rd_mon_N_16449_i; + wire com_tlm_u_tlm_rx_vc0_rd_mon_N_58444_1; + wire com_tlm_u_tlm_rx_vc0_rd_mon_N_86706_i_4141; + wire com_tlm_u_tlm_rx_vc0_rd_mon_fc_free_1data_d_4142; + wire com_tlm_u_tlm_rx_vc0_rd_mon_N_86267_i_4143; + wire com_tlm_u_tlm_rx_vc0_rd_mon_in_header_4144; + wire com_tlm_u_tlm_rx_vc0_rd_mon_N_86267_i_1_4145; + wire com_tlm_u_tlm_rx_vc0_fifo_rem_oqr; + wire com_tlm_u_tlm_rx_vc0_fifo_GND_4146; + wire com_tlm_u_tlm_rx_vc0_fifo_wen_aux_oq_4147; + wire com_tlm_u_tlm_rx_vc0_fifo_data_bqr_64_; + wire com_tlm_u_tlm_rx_vc0_fifo_sof_hold; + wire com_tlm_u_tlm_rx_vc0_fifo_aux_vld_q; + wire com_tlm_u_tlm_rx_vc0_fifo_aux_vld; + wire com_tlm_u_tlm_rx_vc0_fifo_ep_oqr; + wire com_tlm_u_tlm_rx_vc0_fifo_data_bqr_46_; + wire com_tlm_u_tlm_rx_vc0_fifo_N_10672_i_4148; + wire com_tlm_u_tlm_rx_vc0_fifo_cfg_nxt_rdy; + wire com_tlm_u_tlm_rx_vc0_fifo_adv_pkt_bq_0_4149; + wire com_tlm_u_tlm_rx_vc0_fifo_N_58449; + wire com_tlm_u_tlm_rx_vc0_fifo_data_bqr_65_; + wire com_tlm_u_tlm_rx_vc0_fifo_ren_oq_i_a3_0_4150; + wire com_tlm_u_tlm_rx_vc0_fifo_N_44135_i; + wire com_tlm_u_tlm_rx_vc0_fifo_adv_pkt_in_i_0_4151; + wire com_tlm_u_tlm_rx_vc0_fifo_N_44893; + wire com_tlm_u_tlm_rx_vc0_fifo_N_44892; + wire com_tlm_u_tlm_rx_vc0_fifo_select_bq_0_sqmuxa_4152; + wire com_tlm_u_tlm_rx_vc0_fifo_reset_i_q_i_4153; + wire com_tlm_u_tlm_rx_vc0_fifo_data_bqr_67_; + wire com_tlm_u_tlm_rx_vc0_fifo_N_86093_i_4154; + wire com_tlm_u_tlm_rx_vc0_fifo_eof_oqr; + wire com_tlm_u_tlm_rx_vc0_fifo_N_10669_i_4155; + wire com_tlm_u_tlm_rx_vc0_fifo_un6_usr_sof_d_1; + wire com_tlm_u_tlm_rx_vc0_fifo_un4_usr_sof_d_1; + wire com_tlm_u_tlm_rx_vc0_fifo_N_44262; + wire com_tlm_u_tlm_rx_vc0_fifo_N_44261; + wire com_tlm_u_tlm_rx_vc0_fifo_N_44260; + wire com_tlm_u_tlm_rx_vc0_fifo_N_44259; + wire com_tlm_u_tlm_rx_vc0_fifo_N_44258; + wire com_tlm_u_tlm_rx_vc0_fifo_N_44257; + wire com_tlm_u_tlm_rx_vc0_fifo_N_44256; + wire com_tlm_u_tlm_rx_vc0_fifo_usr_src_rdy_d_3_4156; + wire com_tlm_u_tlm_rx_vc0_fifo_select_usr_4157; + wire com_tlm_u_tlm_rx_vc0_fifo_cfg_src_rdy_d_3_4158; + wire com_tlm_u_tlm_rx_vc0_fifo_select_cfg_4159; + wire com_tlm_u_tlm_rx_vc0_fifo_N_44082_i; + wire com_tlm_u_tlm_rx_vc0_fifo_data_oqr_63_; + wire com_tlm_u_tlm_rx_vc0_fifo_data_bqr_63_; + wire com_tlm_u_tlm_rx_vc0_fifo_data_oqr_62_; + wire com_tlm_u_tlm_rx_vc0_fifo_data_bqr_62_; + wire com_tlm_u_tlm_rx_vc0_fifo_data_oqr_61_; + wire com_tlm_u_tlm_rx_vc0_fifo_data_bqr_61_; + wire com_tlm_u_tlm_rx_vc0_fifo_data_oqr_60_; + wire com_tlm_u_tlm_rx_vc0_fifo_data_bqr_60_; + wire com_tlm_u_tlm_rx_vc0_fifo_data_oqr_59_; + wire com_tlm_u_tlm_rx_vc0_fifo_data_bqr_59_; + wire com_tlm_u_tlm_rx_vc0_fifo_data_oqr_58_; + wire com_tlm_u_tlm_rx_vc0_fifo_data_bqr_58_; + wire com_tlm_u_tlm_rx_vc0_fifo_data_oqr_57_; + wire com_tlm_u_tlm_rx_vc0_fifo_data_bqr_57_; + wire com_tlm_u_tlm_rx_vc0_fifo_data_oqr_56_; + wire com_tlm_u_tlm_rx_vc0_fifo_data_bqr_56_; + wire com_tlm_u_tlm_rx_vc0_fifo_data_oqr_55_; + wire com_tlm_u_tlm_rx_vc0_fifo_data_bqr_55_; + wire com_tlm_u_tlm_rx_vc0_fifo_data_oqr_54_; + wire com_tlm_u_tlm_rx_vc0_fifo_data_bqr_54_; + wire com_tlm_u_tlm_rx_vc0_fifo_data_oqr_53_; + wire com_tlm_u_tlm_rx_vc0_fifo_data_bqr_53_; + wire com_tlm_u_tlm_rx_vc0_fifo_data_oqr_52_; + wire com_tlm_u_tlm_rx_vc0_fifo_data_bqr_52_; + wire com_tlm_u_tlm_rx_vc0_fifo_data_oqr_51_; + wire com_tlm_u_tlm_rx_vc0_fifo_data_bqr_51_; + wire com_tlm_u_tlm_rx_vc0_fifo_data_oqr_50_; + wire com_tlm_u_tlm_rx_vc0_fifo_data_bqr_50_; + wire com_tlm_u_tlm_rx_vc0_fifo_data_oqr_49_; + wire com_tlm_u_tlm_rx_vc0_fifo_data_bqr_49_; + wire com_tlm_u_tlm_rx_vc0_fifo_data_oqr_48_; + wire com_tlm_u_tlm_rx_vc0_fifo_data_bqr_48_; + wire com_tlm_u_tlm_rx_vc0_fifo_data_oqr_47_; + wire com_tlm_u_tlm_rx_vc0_fifo_data_bqr_47_; + wire com_tlm_u_tlm_rx_vc0_fifo_data_oqr_45_; + wire com_tlm_u_tlm_rx_vc0_fifo_data_bqr_45_; + wire com_tlm_u_tlm_rx_vc0_fifo_data_oqr_44_; + wire com_tlm_u_tlm_rx_vc0_fifo_data_bqr_44_; + wire com_tlm_u_tlm_rx_vc0_fifo_data_oqr_43_; + wire com_tlm_u_tlm_rx_vc0_fifo_data_bqr_43_; + wire com_tlm_u_tlm_rx_vc0_fifo_data_oqr_42_; + wire com_tlm_u_tlm_rx_vc0_fifo_data_bqr_42_; + wire com_tlm_u_tlm_rx_vc0_fifo_data_oqr_41_; + wire com_tlm_u_tlm_rx_vc0_fifo_data_bqr_41_; + wire com_tlm_u_tlm_rx_vc0_fifo_data_oqr_40_; + wire com_tlm_u_tlm_rx_vc0_fifo_data_bqr_40_; + wire com_tlm_u_tlm_rx_vc0_fifo_data_oqr_39_; + wire com_tlm_u_tlm_rx_vc0_fifo_data_bqr_39_; + wire com_tlm_u_tlm_rx_vc0_fifo_data_oqr_38_; + wire com_tlm_u_tlm_rx_vc0_fifo_data_bqr_38_; + wire com_tlm_u_tlm_rx_vc0_fifo_data_oqr_37_; + wire com_tlm_u_tlm_rx_vc0_fifo_data_bqr_37_; + wire com_tlm_u_tlm_rx_vc0_fifo_data_oqr_36_; + wire com_tlm_u_tlm_rx_vc0_fifo_data_bqr_36_; + wire com_tlm_u_tlm_rx_vc0_fifo_data_oqr_35_; + wire com_tlm_u_tlm_rx_vc0_fifo_data_bqr_35_; + wire com_tlm_u_tlm_rx_vc0_fifo_data_oqr_34_; + wire com_tlm_u_tlm_rx_vc0_fifo_data_bqr_34_; + wire com_tlm_u_tlm_rx_vc0_fifo_data_oqr_33_; + wire com_tlm_u_tlm_rx_vc0_fifo_data_bqr_33_; + wire com_tlm_u_tlm_rx_vc0_fifo_data_oqr_32_; + wire com_tlm_u_tlm_rx_vc0_fifo_data_bqr_32_; + wire com_tlm_u_tlm_rx_vc0_fifo_data_oqr_31_; + wire com_tlm_u_tlm_rx_vc0_fifo_data_bqr_31_; + wire com_tlm_u_tlm_rx_vc0_fifo_data_oqr_30_; + wire com_tlm_u_tlm_rx_vc0_fifo_data_bqr_30_; + wire com_tlm_u_tlm_rx_vc0_fifo_data_oqr_29_; + wire com_tlm_u_tlm_rx_vc0_fifo_data_bqr_29_; + wire com_tlm_u_tlm_rx_vc0_fifo_data_oqr_28_; + wire com_tlm_u_tlm_rx_vc0_fifo_data_bqr_28_; + wire com_tlm_u_tlm_rx_vc0_fifo_data_oqr_27_; + wire com_tlm_u_tlm_rx_vc0_fifo_data_bqr_27_; + wire com_tlm_u_tlm_rx_vc0_fifo_data_oqr_26_; + wire com_tlm_u_tlm_rx_vc0_fifo_data_bqr_26_; + wire com_tlm_u_tlm_rx_vc0_fifo_data_oqr_25_; + wire com_tlm_u_tlm_rx_vc0_fifo_data_bqr_25_; + wire com_tlm_u_tlm_rx_vc0_fifo_data_oqr_24_; + wire com_tlm_u_tlm_rx_vc0_fifo_data_bqr_24_; + wire com_tlm_u_tlm_rx_vc0_fifo_data_oqr_23_; + wire com_tlm_u_tlm_rx_vc0_fifo_data_bqr_23_; + wire com_tlm_u_tlm_rx_vc0_fifo_data_oqr_22_; + wire com_tlm_u_tlm_rx_vc0_fifo_data_bqr_22_; + wire com_tlm_u_tlm_rx_vc0_fifo_data_oqr_21_; + wire com_tlm_u_tlm_rx_vc0_fifo_data_bqr_21_; + wire com_tlm_u_tlm_rx_vc0_fifo_data_oqr_20_; + wire com_tlm_u_tlm_rx_vc0_fifo_data_bqr_20_; + wire com_tlm_u_tlm_rx_vc0_fifo_data_oqr_19_; + wire com_tlm_u_tlm_rx_vc0_fifo_data_bqr_19_; + wire com_tlm_u_tlm_rx_vc0_fifo_data_oqr_18_; + wire com_tlm_u_tlm_rx_vc0_fifo_data_bqr_18_; + wire com_tlm_u_tlm_rx_vc0_fifo_data_oqr_17_; + wire com_tlm_u_tlm_rx_vc0_fifo_data_bqr_17_; + wire com_tlm_u_tlm_rx_vc0_fifo_data_oqr_16_; + wire com_tlm_u_tlm_rx_vc0_fifo_data_bqr_16_; + wire com_tlm_u_tlm_rx_vc0_fifo_data_oqr_15_; + wire com_tlm_u_tlm_rx_vc0_fifo_data_bqr_15_; + wire com_tlm_u_tlm_rx_vc0_fifo_data_oqr_14_; + wire com_tlm_u_tlm_rx_vc0_fifo_data_bqr_14_; + wire com_tlm_u_tlm_rx_vc0_fifo_data_oqr_13_; + wire com_tlm_u_tlm_rx_vc0_fifo_data_bqr_13_; + wire com_tlm_u_tlm_rx_vc0_fifo_data_oqr_12_; + wire com_tlm_u_tlm_rx_vc0_fifo_data_bqr_12_; + wire com_tlm_u_tlm_rx_vc0_fifo_data_oqr_11_; + wire com_tlm_u_tlm_rx_vc0_fifo_data_bqr_11_; + wire com_tlm_u_tlm_rx_vc0_fifo_data_oqr_10_; + wire com_tlm_u_tlm_rx_vc0_fifo_data_bqr_10_; + wire com_tlm_u_tlm_rx_vc0_fifo_data_oqr_9_; + wire com_tlm_u_tlm_rx_vc0_fifo_data_bqr_9_; + wire com_tlm_u_tlm_rx_vc0_fifo_data_oqr_8_; + wire com_tlm_u_tlm_rx_vc0_fifo_data_bqr_8_; + wire com_tlm_u_tlm_rx_vc0_fifo_data_oqr_7_; + wire com_tlm_u_tlm_rx_vc0_fifo_data_bqr_7_; + wire com_tlm_u_tlm_rx_vc0_fifo_data_oqr_6_; + wire com_tlm_u_tlm_rx_vc0_fifo_data_bqr_6_; + wire com_tlm_u_tlm_rx_vc0_fifo_data_oqr_5_; + wire com_tlm_u_tlm_rx_vc0_fifo_data_bqr_5_; + wire com_tlm_u_tlm_rx_vc0_fifo_data_oqr_4_; + wire com_tlm_u_tlm_rx_vc0_fifo_data_bqr_4_; + wire com_tlm_u_tlm_rx_vc0_fifo_data_oqr_3_; + wire com_tlm_u_tlm_rx_vc0_fifo_data_bqr_3_; + wire com_tlm_u_tlm_rx_vc0_fifo_data_oqr_2_; + wire com_tlm_u_tlm_rx_vc0_fifo_data_bqr_2_; + wire com_tlm_u_tlm_rx_vc0_fifo_data_oqr_1_; + wire com_tlm_u_tlm_rx_vc0_fifo_data_bqr_1_; + wire com_tlm_u_tlm_rx_vc0_fifo_select_oq_4160; + wire com_tlm_u_tlm_rx_vc0_fifo_select_bq_4161; + wire com_tlm_u_tlm_rx_vc0_fifo_data_oqr_0_; + wire com_tlm_u_tlm_rx_vc0_fifo_data_bqr_0_; + wire com_tlm_u_tlm_rx_vc0_fifo_select_oq2bq_d_5_4162; + wire com_tlm_u_tlm_rx_vc0_fifo_select_oq2bq_d_4163; + wire com_tlm_u_tlm_rx_vc0_fifo_select_bq17_4164; + wire com_tlm_u_tlm_rx_vc0_fifo_select_cfg_7; + wire com_tlm_u_tlm_rx_vc0_fifo_select_usr_7; + wire com_tlm_u_tlm_rx_vc0_fifo_cfg_oqr; + wire com_tlm_u_tlm_rx_vc0_fifo_adv_pkt_bq_4165; + wire com_tlm_u_tlm_rx_vc0_fifo_N_44111; + wire com_tlm_u_tlm_rx_vc0_fifo_nxt_vld_bqr; + wire com_tlm_u_tlm_rx_vc0_fifo_np_oqr; + wire com_tlm_u_tlm_rx_vc0_fifo_data_vld_bqr; + wire com_tlm_u_tlm_rx_vc0_fifo_aux_vld_oqr; + wire com_tlm_u_tlm_rx_vc0_fifo_un1_adv_pkt_oq_4166; + wire com_tlm_u_tlm_rx_vc0_fifo_un4_adv_pkt_oq; + wire com_tlm_u_tlm_rx_vc0_fifo_un1_adv_pkt_oq_1_0_4167; + wire com_tlm_u_tlm_rx_vc0_fifo_select_oq2bq_5; + wire com_tlm_u_tlm_rx_vc0_fifo_select_oq2bq_1_4168; + wire com_tlm_u_tlm_rx_vc0_fifo_N_44215_i; + wire com_tlm_u_tlm_rx_vc0_fifo_data_vld_oqr; + wire com_tlm_u_tlm_rx_vc0_fifo_select_oq2bq_4169; + wire com_tlm_u_tlm_rx_vc0_fifo_N_10673_i; + wire com_tlm_u_tlm_rx_vc0_fifo_N_10460_i; + wire com_tlm_u_tlm_rx_vc0_fifo_N_10461_i; + wire com_tlm_u_tlm_rx_vc0_fifo_N_10462_i; + wire com_tlm_u_tlm_rx_vc0_fifo_N_10463_i; + wire com_tlm_u_tlm_rx_vc0_fifo_N_10464_i; + wire com_tlm_u_tlm_rx_vc0_fifo_N_10465_i; + wire com_tlm_u_tlm_rx_vc0_fifo_N_10466_i; + wire com_tlm_u_tlm_rx_vc0_fifo_un8_cpl_d_0_a2_4170; + wire com_tlm_u_tlm_rx_vc0_fifo_N_86703_i_4171; + wire com_tlm_u_tlm_rx_vc0_fifo_N_44896_i_4172; + wire com_tlm_u_tlm_rx_vc0_fifo_N_44815_i_4173; + wire com_tlm_u_tlm_rx_vc0_fifo_N_44816_i_4174; + wire com_tlm_u_tlm_rx_vc0_fifo_N_44817_i_4175; + wire com_tlm_u_tlm_rx_vc0_fifo_N_44818_i_4176; + wire com_tlm_u_tlm_rx_vc0_fifo_N_44819_i_4177; + wire com_tlm_u_tlm_rx_vc0_fifo_N_44820_i_4178; + wire com_tlm_u_tlm_rx_vc0_fifo_N_44821_i_4179; + wire com_tlm_u_tlm_rx_vc0_fifo_N_44822_i_4180; + wire com_tlm_u_tlm_rx_vc0_fifo_N_44823_i_4181; + wire com_tlm_u_tlm_rx_vc0_fifo_N_44824_i_4182; + wire com_tlm_u_tlm_rx_vc0_fifo_N_44825_i_4183; + wire com_tlm_u_tlm_rx_vc0_fifo_N_44826_i_4184; + wire com_tlm_u_tlm_rx_vc0_fifo_N_44827_i_4185; + wire com_tlm_u_tlm_rx_vc0_fifo_N_44828_i_4186; + wire com_tlm_u_tlm_rx_vc0_fifo_N_44829_i_4187; + wire com_tlm_u_tlm_rx_vc0_fifo_N_44830_i_4188; + wire com_tlm_u_tlm_rx_vc0_fifo_N_44901_i_4189; + wire com_tlm_u_tlm_rx_vc0_fifo_N_44895_i_4190; + wire com_tlm_u_tlm_rx_vc0_fifo_N_44831_i_4191; + wire com_tlm_u_tlm_rx_vc0_fifo_N_44832_i_4192; + wire com_tlm_u_tlm_rx_vc0_fifo_N_44833_i_4193; + wire com_tlm_u_tlm_rx_vc0_fifo_N_44834_i_4194; + wire com_tlm_u_tlm_rx_vc0_fifo_N_44835_i_4195; + wire com_tlm_u_tlm_rx_vc0_fifo_N_44836_i_4196; + wire com_tlm_u_tlm_rx_vc0_fifo_N_44837_i_4197; + wire com_tlm_u_tlm_rx_vc0_fifo_N_44838_i_4198; + wire com_tlm_u_tlm_rx_vc0_fifo_N_44839_i_4199; + wire com_tlm_u_tlm_rx_vc0_fifo_N_44840_i_4200; + wire com_tlm_u_tlm_rx_vc0_fifo_N_44841_i_4201; + wire com_tlm_u_tlm_rx_vc0_fifo_N_44842_i_4202; + wire com_tlm_u_tlm_rx_vc0_fifo_N_44843_i_4203; + wire com_tlm_u_tlm_rx_vc0_fifo_N_44844_i_4204; + wire com_tlm_u_tlm_rx_vc0_fifo_N_44845_i_4205; + wire com_tlm_u_tlm_rx_vc0_fifo_N_44846_i_4206; + wire com_tlm_u_tlm_rx_vc0_fifo_N_44847_i_4207; + wire com_tlm_u_tlm_rx_vc0_fifo_N_44848_i_4208; + wire com_tlm_u_tlm_rx_vc0_fifo_N_44849_i_4209; + wire com_tlm_u_tlm_rx_vc0_fifo_N_44850_i_4210; + wire com_tlm_u_tlm_rx_vc0_fifo_N_44851_i_4211; + wire com_tlm_u_tlm_rx_vc0_fifo_N_44852_i_4212; + wire com_tlm_u_tlm_rx_vc0_fifo_N_44853_i_4213; + wire com_tlm_u_tlm_rx_vc0_fifo_N_44854_i_4214; + wire com_tlm_u_tlm_rx_vc0_fifo_N_44855_i_4215; + wire com_tlm_u_tlm_rx_vc0_fifo_N_44856_i_4216; + wire com_tlm_u_tlm_rx_vc0_fifo_N_44857_i_4217; + wire com_tlm_u_tlm_rx_vc0_fifo_N_44858_i_4218; + wire com_tlm_u_tlm_rx_vc0_fifo_N_44859_i_4219; + wire com_tlm_u_tlm_rx_vc0_fifo_N_44860_i_4220; + wire com_tlm_u_tlm_rx_vc0_fifo_N_44861_i_4221; + wire com_tlm_u_tlm_rx_vc0_fifo_N_44862_i_4222; + wire com_tlm_u_tlm_rx_vc0_fifo_N_44863_i_4223; + wire com_tlm_u_tlm_rx_vc0_fifo_N_44864_i_4224; + wire com_tlm_u_tlm_rx_vc0_fifo_N_44865_i_4225; + wire com_tlm_u_tlm_rx_vc0_fifo_N_44866_i_4226; + wire com_tlm_u_tlm_rx_vc0_fifo_N_44867_i_4227; + wire com_tlm_u_tlm_rx_vc0_fifo_N_44868_i_4228; + wire com_tlm_u_tlm_rx_vc0_fifo_N_44869_i_4229; + wire com_tlm_u_tlm_rx_vc0_fifo_N_44870_i_4230; + wire com_tlm_u_tlm_rx_vc0_fifo_N_44871_i_4231; + wire com_tlm_u_tlm_rx_vc0_fifo_N_44872_i_4232; + wire com_tlm_u_tlm_rx_vc0_fifo_N_44873_i_4233; + wire com_tlm_u_tlm_rx_vc0_fifo_N_44874_i_4234; + wire com_tlm_u_tlm_rx_vc0_fifo_N_44875_i_4235; + wire com_tlm_u_tlm_rx_vc0_fifo_N_44876_i_4236; + wire com_tlm_u_tlm_rx_vc0_fifo_trn_rerrfwd; + wire com_tlm_u_tlm_rx_vc0_fifo_trn_rsrc_dsc; + wire com_tlm_u_tlm_rx_vc0_fifo_un1_select_oq2bq_d_1_i_4237; + wire com_tlm_u_tlm_rx_vc0_fifo_un1_select_oq2bq_d_1_4238; + wire com_tlm_u_tlm_rx_vc0_fifo_N_10675_i_i_i_4239; + wire com_tlm_u_tlm_rx_vc0_fifo_N_10675_i_i; + wire com_tlm_u_tlm_rx_vc0_fifo_N_85839_i_4240; + wire com_tlm_u_tlm_rx_vc0_fifo_adv_pkt_in_i_4241; + wire com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_waddr_p1_1_s_0_4242; + wire com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_waddr_p1_1_s_1_4243; + wire com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_waddr_p1_1_cry_0_4244; + wire com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_waddr_p1_1_s_2_4245; + wire com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_waddr_p1_1_cry_1_4246; + wire com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_waddr_p1_1_s_3_4247; + wire com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_waddr_p1_1_cry_2_4248; + wire com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_waddr_p1_1_s_4_4249; + wire com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_waddr_p1_1_cry_3_4250; + wire com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_waddr_p1_1_s_5_4251; + wire com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_waddr_p1_1_cry_4_4252; + wire com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_waddr_p1_1_s_6_4253; + wire com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_waddr_p1_1_cry_5_4254; + wire com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_waddr_p1_1_s_7_4255; + wire com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_waddr_p1_1_cry_6_4256; + wire com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_waddr_p1_1_s_8_4257; + wire com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_waddr_p1_1_cry_7_4258; + wire com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_waddr_p1_1_s_9_4259; + wire com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_waddr_p1_1_cry_8_4260; + wire com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un3_pkt_ct_s_1_4261; + wire com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un3_pkt_ct_cry_0_4262; + wire com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un3_pkt_ct_s_2_4263; + wire com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un3_pkt_ct_cry_1_4264; + wire com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un3_pkt_ct_s_3_4265; + wire com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un3_pkt_ct_cry_2_4266; + wire com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un3_pkt_ct_s_4_4267; + wire com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un3_pkt_ct_cry_3_4268; + wire com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un3_pkt_ct_s_5_4269; + wire com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un3_pkt_ct_cry_4_4270; + wire com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un3_pkt_ct_s_6_4271; + wire com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un3_pkt_ct_cry_5_4272; + wire com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un3_pkt_ct_m1_s_1_4273; + wire com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un3_pkt_ct_m1_cry_0_4274; + wire com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un3_pkt_ct_m1_s_2_4275; + wire com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un3_pkt_ct_m1_cry_1_4276; + wire com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un3_pkt_ct_m1_s_3_4277; + wire com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un3_pkt_ct_m1_cry_2_4278; + wire com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un3_pkt_ct_m1_s_4_4279; + wire com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un3_pkt_ct_m1_cry_3_4280; + wire com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un3_pkt_ct_m1_s_5_4281; + wire com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un3_pkt_ct_m1_cry_4_4282; + wire com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un3_pkt_ct_m1_s_6_4283; + wire com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un3_pkt_ct_m1_cry_5_4284; + wire com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_vld_ct_1_s_1_4285; + wire com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_vld_ct_1_cry_0_4286; + wire com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_vld_ct_1_s_2_4287; + wire com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_vld_ct_1_cry_1_4288; + wire com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_vld_ct_1_s_3_4289; + wire com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_vld_ct_1_cry_2_4290; + wire com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_vld_ct_1_s_4_4291; + wire com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_vld_ct_1_cry_3_4292; + wire com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_vld_ct_1_s_5_4293; + wire com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_vld_ct_1_cry_4_4294; + wire com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_vld_ct_1_s_6_4295; + wire com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_vld_ct_1_cry_5_4296; + wire com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_vld_ct_1_cry_7_0_4297; + wire com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_vld_ct_1_s_7_4298; + wire com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_vld_ct_1_cry_6_4299; + wire com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_vld_ct_1_cry_8_0_4300; + wire com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_vld_ct_1_s_8_4301; + wire com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_vld_ct_1_cry_7_4302; + wire com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_vld_ct_1_s_9_4303; + wire com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_vld_ct_1_cry_8_4304; + wire com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_GND_4305; + wire com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_N_16460_i; + wire com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_lockout_4306; + wire com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_all_full_4307; + wire com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_wen_i_4; + wire com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_wen_i_2; + wire com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_waddr_p1_3; + wire com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_wen_i_1; + wire com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_vld_ct_eq_1_5_4308; + wire com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_frm_vld; + wire com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_nxt_vld_4309; + wire com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_overflow_4310; + wire com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_N_43142_i_i_4311; + wire com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_vld_ct_eq_1_4312; + wire com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_vld_ct_eq_1_7_4313; + wire com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_vld_ct_eq_1_6_4314; + wire com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_vld_ct_1_axb_0_4315; + wire com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_N_10350_i_4316; + wire com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_N_10763_i; + wire com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_wen_i_7; + wire com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_wen_i_6; + wire com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_wen_i_5; + wire com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_N_10763_1; + wire com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un3_pkt_ct_axb_6_4317; + wire com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un3_pkt_ct_axb_5_4318; + wire com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un3_pkt_ct_axb_4_4319; + wire com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un3_pkt_ct_axb_3_4320; + wire com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un3_pkt_ct_axb_2_4321; + wire com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un3_pkt_ct_axb_1_4322; + wire com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un3_pkt_ct_m1_axb_6_4323; + wire com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un3_pkt_ct_m1_axb_5_4324; + wire com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un3_pkt_ct_m1_axb_4_4325; + wire com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un3_pkt_ct_m1_axb_3_4326; + wire com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un3_pkt_ct_m1_axb_2_4327; + wire com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un3_pkt_ct_m1_axb_1_4328; + wire com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_vld_ct_1_axb_8_4329; + wire com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_vld_ct_1_axb_7_4330; + wire com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_vld_ct_1_axb_6_4331; + wire com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_vld_ct_1_axb_5_4332; + wire com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_vld_ct_1_axb_4_4333; + wire com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_vld_ct_1_axb_3_4334; + wire com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_vld_ct_1_axb_2_4335; + wire com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_vld_ct_1_axb_1_4336; + wire com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_waddr_p1_1_axb_9_4337; + wire com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_waddr_p1_1_axb_8_4338; + wire com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_waddr_p1_1_axb_7_4339; + wire com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_waddr_p1_1_axb_6_4340; + wire com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_waddr_p1_1_axb_5_4341; + wire com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_waddr_p1_1_axb_4_4342; + wire com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_waddr_p1_1_axb_3_4343; + wire com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_waddr_p1_1_axb_2_4344; + wire com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_waddr_p1_1_axb_1_4345; + wire com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_waddr_p1_1_axb_0_4346; + wire com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr16_4347; + wire com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_N_10762_i_4348; + wire com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_overflow_1_i; + wire com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_push; + wire com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_vld_ct25_i; + wire com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_vld_ct_1_cry_6_ma_4349; + wire com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_VCC_4350; + wire com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_vld_ct_1_axb_9_4351; + wire com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_vld_ct25; + wire com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_pop_4352; + wire com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un3_pkt_ct_m1_axb_0_4353; + wire com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un3_pkt_ct_axb_0_4354; + wire com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_queue_ram_VCC_4355; + wire com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_queue_ram_GND_4356; + wire com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_queue_ram_N_58351_i_4357; + wire com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_un1_bkp_i_1_i_4358; + wire com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_un1_bkp_i_3_i_4359; + wire com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_un13_nxt_vld_o_en_2_4360; + wire com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_overwrap_2_4361; + wire com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_N_10761_i; + wire com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_N_10749; + wire com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_N_10750; + wire com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_N_10751; + wire com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_N_10752; + wire com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_N_10753; + wire com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_N_10754; + wire com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_N_10755; + wire com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_N_10756; + wire com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_nxt_vld_o_2; + wire com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_N_10757; + wire com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_hi_eq_1_m_i_4362; + wire com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_srl_wen_4363; + wire com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_N_10759_1; + wire com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_un1_raddr_lo_1_axbxc3_4364; + wire com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_un1_raddr_lo_1_p4_0_4365; + wire com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_un1_raddr_lo_1_axbxc2_4366; + wire com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_un1_raddr_lo_1_p4_4367; + wire com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_un1_raddr_lo_1_axbxc1_4368; + wire com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_un1_raddr_lo_1_axb0_4369; + wire com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_en_4370; + wire com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_N_43140_i_i_4371; + wire com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_N_43140_i; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_sof_hold_3; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_ren_4372; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_in_86_; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_in_89_; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_in_81_; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_in_82_; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_in_83_; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_in_92_; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_in_85_; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_in_129_; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_in_88_; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_in_90_; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_in_91_; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_in_133_; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_in_93_; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_in_94_; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_in_135_; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_in_95_; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_in_96_; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_in_97_; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_in_98_; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_in_139_; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_in_99_; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_in_100_; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_in_101_; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_in_102_; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_in_103_; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_in_72_; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_in_104_; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_in_113_; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_in_73_; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_in_105_; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_in_114_; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_in_74_; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_in_106_; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_in_115_; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_in_75_; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_in_107_; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_in_76_; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_in_108_; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_in_109_; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_in_118_; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_in_78_; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_in_117_; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_in_77_; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_in_79_; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_in_111_; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_in_84_; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_in_116_; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_in_112_; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_in_121_; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_in_87_; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_in_122_; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_in_136_; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_in_123_; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_in_137_; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_in_124_; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_in_120_; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_in_80_; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_in_125_; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_in_130_; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_in_126_; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_in_132_; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_in_131_; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_in_127_; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_in_110_; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_in_119_; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_in_128_; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_in_134_; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_GND_4373; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_un1_raddr_lo_1_cry_0_4374; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_un1_raddr_lo_1_cry_1_4375; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_un1_raddr_lo_1_cry_2_4376; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_64_; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_65_; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_67_; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_overwrap_0_4377; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_un15_nxt_vld_o_en_2_4378; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_un1_bkp_i_1_i_4379; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_un1_bkp_i_3_i_4380; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_un15_nxt_vld_o_en_4381; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_overwrap_3_4382; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_135_; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_63_; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_134_; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_62_; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_133_; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_61_; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_132_; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_60_; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_131_; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_59_; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_130_; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_58_; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_129_; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_57_; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_128_; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_56_; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_127_; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_55_; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_126_; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_54_; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_125_; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_53_; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_124_; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_52_; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_123_; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_51_; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_122_; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_50_; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_121_; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_49_; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_120_; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_48_; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_119_; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_47_; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_118_; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_46_; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_117_; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_45_; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_116_; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_44_; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_115_; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_43_; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_114_; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_42_; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_113_; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_41_; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_112_; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_40_; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_111_; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_39_; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_110_; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_38_; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_109_; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_37_; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_108_; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_36_; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_107_; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_35_; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_106_; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_34_; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_105_; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_33_; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_104_; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_32_; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_103_; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_31_; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_102_; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_30_; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_101_; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_29_; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_100_; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_28_; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_99_; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_27_; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_98_; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_26_; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_97_; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_25_; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_96_; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_24_; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_95_; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_23_; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_94_; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_22_; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_93_; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_21_; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_92_; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_20_; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_91_; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_19_; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_90_; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_18_; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_89_; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_17_; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_88_; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_16_; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_87_; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_15_; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_86_; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_14_; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_85_; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_13_; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_84_; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_12_; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_83_; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_11_; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_82_; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_10_; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_81_; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_9_; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_80_; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_8_; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_79_; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_7_; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_78_; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_6_; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_77_; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_5_; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_76_; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_4_; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_75_; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_3_; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_74_; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_2_; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_73_; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_1_; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_72_; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_0_; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_hi_eq_1_m_i_4383; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_d_o_d_m_67__4384; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_139_; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_d_o_d_m_65__4385; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_137_; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_d_o_d_m_64__4386; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_136_; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_un1_raddr_lo_1_axb_3_4387; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_un1_raddr_lo_1_axb_2_4388; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_un1_raddr_lo_1_axb_1_4389; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_d_o_0_sqmuxa_4390; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_un1_raddr_lo_1_axb_0_4391; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_un1_raddr_lo_1_s_2_5; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_un1_raddr_lo_1_s_1_5; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_un1_raddr_lo_1_s_3_5; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_10683_i_4392; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_10684_i_4393; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_10685_i_4394; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_10686_i_4395; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_10687_i_4396; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_10688_i_4397; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_10689_i_4398; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_10690_i_4399; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_10691_i_4400; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_10692_i_4401; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_10693_i_4402; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_10694_i_4403; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_10695_i_4404; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_10696_i_4405; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_10697_i_4406; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_10698_i_4407; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_10699_i_4408; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_10700_i_4409; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_10701_i_4410; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_10702_i_4411; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_10703_i_4412; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_10704_i_4413; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_10705_i_4414; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_10706_i_4415; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_10707_i_4416; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_10708_i_4417; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_10709_i_4418; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_10710_i_4419; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_10711_i_4420; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_10712_i_4421; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_10713_i_4422; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_10714_i_4423; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_10715_i_4424; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_10716_i_4425; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_10717_i_4426; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_10718_i_4427; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_10719_i_4428; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_10720_i_4429; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_10721_i_4430; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_10722_i_4431; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_10723_i_4432; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_10724_i_4433; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_10725_i_4434; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_10726_i_4435; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_10727_i_4436; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_10728_i_4437; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_10729_i_4438; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_10730_i_4439; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_10731_i_4440; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_10732_i_4441; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_10733_i_4442; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_10734_i_4443; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_10735_i_4444; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_10736_i_4445; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_10737_i_4446; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_10738_i_4447; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_10739_i_4448; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_10740_i_4449; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_10741_i_4450; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_10742_i_4451; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_10743_i_4452; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_10744_i_4453; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_10745_i_4454; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_86095_i_4455; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_10746_i_4456; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_queue_aux_queue_GND_4457; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_queue_aux_queue_un1_raddr_lo_1_s_1_6; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_queue_aux_queue_un1_raddr_lo_1_cry_0_4458; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_queue_aux_queue_un1_raddr_lo_1_s_2_6; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_queue_aux_queue_un1_raddr_lo_1_cry_1_4459; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_queue_aux_queue_un1_raddr_lo_1_s_3_6; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_queue_aux_queue_un1_raddr_lo_1_cry_2_4460; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_queue_aux_queue_un1_aux_queue; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_queue_aux_queue_N_44080_i_i_4461; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_queue_aux_queue_N_86084_i_4462; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_queue_aux_queue_un1_bkp_i_1_i_0_a2_2_4463; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_queue_aux_queue_un1_raddr_lo_1_axb_0_4464; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_queue_aux_queue_un1_raddr_lo_1_axb_3_4465; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_queue_aux_queue_un1_raddr_lo_1_axb_2_4466; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_queue_aux_queue_un1_raddr_lo_1_axb_1_4467; + wire com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_queue_aux_queue_N_44106_i; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_fc_gnt_3; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_GND_4468; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_un7_lat_prescale_c3_4469; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_N_19688_i_4470; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_err_overflow_o_3_0_a2_3_4471; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_N_60552_i_4472; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_N_56162_i; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_lat_prescale_term_4473; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_lat_prescale_4_i_m3_i_m3_0_3__4474; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_N_46166_i; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_lat_prescale_4_i_m3_i_m3_0_1__4475; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_un1_lat_timer_i; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_freeze_timer_4476; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_free_q_4477; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_free_h_4478; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_h_o_cry_0_4479; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_h_o_cry_1_4480; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_h_o_cry_2_4481; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_h_o_cry_3_4482; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_h_o_cry_4_4483; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_h_o_cry_5_4484; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_h_o_cry_6_4485; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_d_o_cry_0_0_4486; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_free_d_4487; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_d_o_cry_1_0_4488; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_d_o_cry_0_4489; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_d_o_cry_2_0_4490; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_d_o_cry_1_4491; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_d_o_cry_3_0_4492; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_d_o_cry_2_4493; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_d_o_cry_4_0_4494; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_d_o_cry_3_4495; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_d_o_cry_5_0_4496; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_d_o_cry_4_4497; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_d_o_cry_5_4498; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_d_o_cry_6_4499; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_d_o_cry_7_4500; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_d_o_cry_8_4501; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_d_o_cry_9_4502; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_d_o_cry_10_4503; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_d_av_o_s_1_4504; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_d_av_o_cry_0_4505; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_d_av_o_s_2_4506; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_d_av_o_cry_1_4507; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_d_av_o_s_3_4508; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_d_av_o_cry_2_4509; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_d_av_o_s_4_4510; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_d_av_o_cry_3_4511; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_d_av_o_s_5_4512; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_d_av_o_cry_4_4513; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_d_av_o_s_6_4514; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_d_av_o_cry_5_4515; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_d_av_o_s_7_4516; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_d_av_o_cry_6_4517; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_d_av_o_s_8_4518; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_d_av_o_cry_7_4519; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_d_av_o_s_9_4520; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_d_av_o_cry_8_4521; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_d_av_o_s_10_4522; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_d_av_o_cry_9_4523; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_d_av_o_s_11_4524; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_d_av_o_cry_10_4525; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un1_fc_d_con_1_cry_0_0_4526; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un1_fc_d_con_1_cry_1_0_4527; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un1_fc_d_con_1_s_1_4528; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un1_fc_d_con_1_cry_0_4529; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un1_fc_d_con_1_cry_2_0_4530; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un1_fc_d_con_1_s_2_4531; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un1_fc_d_con_1_cry_1_4532; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un1_fc_d_con_1_cry_3_0_4533; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un1_fc_d_con_1_s_3_4534; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un1_fc_d_con_1_cry_2_4535; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un1_fc_d_con_1_cry_4_0_4536; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un1_fc_d_con_1_s_4_4537; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un1_fc_d_con_1_cry_3_4538; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un1_fc_d_con_1_cry_5_0_4539; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un1_fc_d_con_1_s_5_4540; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un1_fc_d_con_1_cry_4_4541; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un1_fc_d_con_1_s_6_4542; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un1_fc_d_con_1_cry_5_4543; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un1_fc_d_con_1_s_7_4544; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un1_fc_d_con_1_cry_6_4545; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un1_fc_d_con_1_s_8_4546; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un1_fc_d_con_1_cry_7_4547; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un1_fc_d_con_1_s_9_4548; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un1_fc_d_con_1_cry_8_4549; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un1_fc_d_con_1_s_10_4550; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un1_fc_d_con_1_cry_9_4551; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un1_fc_d_con_1_s_11_4552; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un1_fc_d_con_1_cry_10_4553; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_h_av_o_s_1_4554; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_h_av_o_cry_0_4555; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_h_av_o_s_2_4556; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_h_av_o_cry_1_4557; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_h_av_o_s_3_4558; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_h_av_o_cry_2_4559; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_h_av_o_s_4_4560; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_h_av_o_cry_3_4561; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_h_av_o_s_5_4562; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_h_av_o_cry_4_4563; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_h_av_o_s_6_4564; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_h_av_o_cry_5_4565; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_h_av_o_s_7_4566; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_h_av_o_cry_6_4567; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_h_advert_1_cry_0_4568; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_h_advert_1_cry_1_4569; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_h_advert_1_cry_2_4570; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_h_advert_1_cry_3_4571; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_h_advert_1_cry_4_4572; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_h_advert_1_cry_5_4573; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_h_advert_1_cry_6_4574; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_VCC_4575; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_d_advert_1_cry_0_4576; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_d_advert_1_cry_1_4577; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_d_advert_1_cry_2_4578; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_d_advert_1_cry_3_4579; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_d_advert_1_cry_4_4580; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_d_advert_1_cry_5_4581; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_d_advert_1_cry_6_4582; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_d_advert_1_cry_7_4583; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_d_advert_1_cry_8_4584; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_d_advert_1_cry_9_4585; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_d_advert_1_cry_10_4586; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_GND_4587; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_free_hold13; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un1_fc_d_con_1_axb_0_4588; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_free_q2_4589; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_free_hold_4590; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_gnt; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_d_advert_1_axb_11_4591; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_h_advert_1_axb_7_4592; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_free_d_3; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_free_h_3; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_free_q_3; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_h_o_axb_7_4593; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_h_o_axb_6_4594; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_h_o_axb_5_4595; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_h_o_axb_4_4596; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_h_o_axb_3_4597; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_h_o_axb_2_4598; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_h_o_axb_1_4599; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_h_o_axb_0_4600; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_d_av_o_axb_11_4601; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_d_av_o_axb_10_4602; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_d_av_o_axb_9_4603; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_d_av_o_axb_8_4604; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_d_av_o_axb_7_4605; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_d_av_o_axb_6_4606; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_d_av_o_axb_5_4607; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_d_av_o_axb_4_4608; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_d_av_o_axb_3_4609; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_d_av_o_axb_2_4610; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_d_av_o_axb_1_4611; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_d_av_o_axb_0_i_4612; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_d_av_o_axb_0_4613; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_h_av_o_axb_7_4614; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_h_av_o_axb_6_4615; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_h_av_o_axb_5_4616; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_h_av_o_axb_4_4617; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_h_av_o_axb_3_4618; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_h_av_o_axb_2_4619; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_h_av_o_axb_1_4620; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_h_av_o_axb_0_i_4621; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_h_av_o_axb_0_4622; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_d_o_axb_11_4623; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_d_o_axb_10_4624; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_d_o_axb_9_4625; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_d_o_axb_8_4626; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_d_o_axb_7_4627; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_d_o_axb_6_4628; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_d_o_axb_5_4629; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_d_o_axb_4_4630; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_d_o_axb_3_4631; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_d_o_axb_2_4632; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_d_o_axb_1_4633; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_d_o_axb_0_4634; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_N_56076_i; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un1_fc_d_con_1_axb_11_4635; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un1_fc_d_con_1_axb_10_4636; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un1_fc_d_con_1_axb_9_4637; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un1_fc_d_con_1_axb_8_4638; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un1_fc_d_con_1_axb_7_4639; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un1_fc_d_con_1_axb_6_4640; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un1_fc_d_con_1_axb_5_4641; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un1_fc_d_con_1_axb_4_4642; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un1_fc_d_con_1_axb_3_4643; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un1_fc_d_con_1_axb_2_4644; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un1_fc_d_con_1_axb_1_4645; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_N_87149_i_4646; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_N_87150_i_4647; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_req_p_src_rdy; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_N_87151_i_4648; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_send_state_2__4649; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_send_state_0__4650; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_N_57046_i; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_d_advert_1_axb_10_4651; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_d_advert_1_axb_9_4652; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_d_advert_1_axb_8_4653; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_d_advert_1_axb_7_4654; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_d_advert_1_axb_6_4655; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_d_advert_1_axb_5_4656; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_d_advert_1_axb_4_4657; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_d_advert_1_axb_3_4658; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_d_advert_1_axb_2_4659; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_d_advert_1_axb_1_4660; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_d_advert_1_axb_0_4661; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_h_advert_1_axb_6_4662; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_h_advert_1_axb_5_4663; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_h_advert_1_axb_4_4664; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_h_advert_1_axb_3_4665; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_h_advert_1_axb_2_4666; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_h_advert_1_axb_1_4667; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_h_advert_1_axb_0_4668; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_free_q_4669; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_free_h_4670; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_h_o_cry_0_4671; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_h_o_cry_1_4672; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_h_o_cry_2_4673; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_h_o_cry_3_4674; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_h_o_cry_4_4675; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_h_o_cry_5_4676; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_h_o_cry_6_4677; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_d_o_cry_0_0_4678; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_free_d_4679; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_d_o_cry_1_0_4680; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_d_o_cry_0_4681; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_d_o_cry_2_0_4682; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_d_o_cry_1_4683; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_d_o_cry_3_0_4684; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_d_o_cry_2_4685; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_d_o_cry_4_0_4686; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_d_o_cry_3_4687; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_d_o_cry_5_0_4688; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_d_o_cry_4_4689; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_d_o_cry_5_4690; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_d_o_cry_6_4691; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_d_o_cry_7_4692; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_d_o_cry_8_4693; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_d_o_cry_9_4694; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_d_o_cry_10_4695; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un36_fc_d_av_o_s_1_4696; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un36_fc_d_av_o_cry_0_4697; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un36_fc_d_av_o_s_2_4698; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un36_fc_d_av_o_cry_1_4699; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un36_fc_d_av_o_s_3_4700; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un36_fc_d_av_o_cry_2_4701; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un36_fc_d_av_o_s_4_4702; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un36_fc_d_av_o_cry_3_4703; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un36_fc_d_av_o_s_5_4704; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un36_fc_d_av_o_cry_4_4705; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un36_fc_d_av_o_s_6_4706; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un36_fc_d_av_o_cry_5_4707; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un36_fc_d_av_o_s_7_4708; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un36_fc_d_av_o_cry_6_4709; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un36_fc_d_av_o_s_8_4710; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un36_fc_d_av_o_cry_7_4711; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un36_fc_d_av_o_s_9_4712; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un36_fc_d_av_o_cry_8_4713; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un36_fc_d_av_o_s_10_4714; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un36_fc_d_av_o_cry_9_4715; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un36_fc_d_av_o_s_11_4716; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un36_fc_d_av_o_cry_10_4717; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un1_fc_d_con_1_cry_0_0_4718; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un1_fc_d_con_1_cry_1_0_4719; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un1_fc_d_con_1_s_1_0; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un1_fc_d_con_1_cry_0_4720; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un1_fc_d_con_1_cry_2_0_4721; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un1_fc_d_con_1_s_2_0; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un1_fc_d_con_1_cry_1_4722; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un1_fc_d_con_1_cry_3_0_4723; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un1_fc_d_con_1_s_3_0; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un1_fc_d_con_1_cry_2_4724; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un1_fc_d_con_1_cry_4_0_4725; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un1_fc_d_con_1_s_4_0; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un1_fc_d_con_1_cry_3_4726; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un1_fc_d_con_1_cry_5_0_4727; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un1_fc_d_con_1_s_5_0; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un1_fc_d_con_1_cry_4_4728; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un1_fc_d_con_1_s_6_0; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un1_fc_d_con_1_cry_5_4729; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un1_fc_d_con_1_s_7_0; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un1_fc_d_con_1_cry_6_4730; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un1_fc_d_con_1_s_8_0; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un1_fc_d_con_1_cry_7_4731; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un1_fc_d_con_1_s_9_0; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un1_fc_d_con_1_cry_8_4732; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un1_fc_d_con_1_s_10_0; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un1_fc_d_con_1_cry_9_4733; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un1_fc_d_con_1_s_11_0; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un1_fc_d_con_1_cry_10_4734; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un35_fc_h_av_o_s_1_4735; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un35_fc_h_av_o_cry_0_4736; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un35_fc_h_av_o_s_2_4737; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un35_fc_h_av_o_cry_1_4738; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un35_fc_h_av_o_s_3_4739; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un35_fc_h_av_o_cry_2_4740; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un35_fc_h_av_o_s_4_4741; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un35_fc_h_av_o_cry_3_4742; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un35_fc_h_av_o_s_5_4743; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un35_fc_h_av_o_cry_4_4744; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un35_fc_h_av_o_s_6_4745; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un35_fc_h_av_o_cry_5_4746; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un35_fc_h_av_o_s_7_4747; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un35_fc_h_av_o_cry_6_4748; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un5_fc_h_advert_cry_0_4749; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un5_fc_h_advert_cry_1_4750; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un5_fc_h_advert_cry_2_4751; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un5_fc_h_advert_cry_3_4752; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un5_fc_h_advert_cry_4_4753; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un5_fc_h_advert_cry_5_4754; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un5_fc_h_advert_cry_6_4755; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_VCC_4756; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un5_fc_d_advert_cry_0_4757; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un5_fc_d_advert_cry_1_4758; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un5_fc_d_advert_cry_2_4759; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un5_fc_d_advert_cry_3_4760; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un5_fc_d_advert_cry_4_4761; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un5_fc_d_advert_cry_5_4762; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un5_fc_d_advert_cry_6_4763; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un5_fc_d_advert_cry_7_4764; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un5_fc_d_advert_cry_8_4765; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un5_fc_d_advert_cry_9_4766; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un5_fc_d_advert_cry_10_4767; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_GND_4768; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_free_hold34; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un1_fc_d_con_1_axb_0_4769; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_free_q2_4770; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_free_hold_4771; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_gnt; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un5_fc_d_advert_axb_11_4772; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un5_fc_h_advert_axb_7_4773; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_free_d_8; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_free_h_8; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_free_q_8; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_h_o_axb_7_4774; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_h_o_axb_6_4775; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_h_o_axb_5_4776; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_h_o_axb_4_4777; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_h_o_axb_3_4778; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_h_o_axb_2_4779; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_h_o_axb_1_4780; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_h_o_axb_0_4781; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un36_fc_d_av_o_axb_11_4782; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un36_fc_d_av_o_axb_10_4783; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un36_fc_d_av_o_axb_9_4784; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un36_fc_d_av_o_axb_8_4785; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un36_fc_d_av_o_axb_7_4786; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un36_fc_d_av_o_axb_6_4787; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un36_fc_d_av_o_axb_5_4788; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un36_fc_d_av_o_axb_4_4789; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un36_fc_d_av_o_axb_3_4790; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un36_fc_d_av_o_axb_2_4791; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un36_fc_d_av_o_axb_1_4792; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un36_fc_d_av_o_axb_0_i_4793; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un36_fc_d_av_o_axb_0_4794; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un35_fc_h_av_o_axb_7_4795; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un35_fc_h_av_o_axb_6_4796; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un35_fc_h_av_o_axb_5_4797; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un35_fc_h_av_o_axb_4_4798; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un35_fc_h_av_o_axb_3_4799; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un35_fc_h_av_o_axb_2_4800; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un35_fc_h_av_o_axb_1_4801; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un35_fc_h_av_o_axb_0_i_4802; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un35_fc_h_av_o_axb_0_4803; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_d_o_axb_11_4804; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_d_o_axb_10_4805; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_d_o_axb_9_4806; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_d_o_axb_8_4807; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_d_o_axb_7_4808; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_d_o_axb_6_4809; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_d_o_axb_5_4810; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_d_o_axb_4_4811; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_d_o_axb_3_4812; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_d_o_axb_2_4813; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_d_o_axb_1_4814; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_d_o_axb_0_4815; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_N_56077_i; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un1_fc_d_con_1_axb_11_4816; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un1_fc_d_con_1_axb_10_4817; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un1_fc_d_con_1_axb_9_4818; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un1_fc_d_con_1_axb_8_4819; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un1_fc_d_con_1_axb_7_4820; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un1_fc_d_con_1_axb_6_4821; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un1_fc_d_con_1_axb_5_4822; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un1_fc_d_con_1_axb_4_4823; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un1_fc_d_con_1_axb_3_4824; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un1_fc_d_con_1_axb_2_4825; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un1_fc_d_con_1_axb_1_4826; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_N_87152_i_4827; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_N_87153_i_4828; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_req_np_src_rdy; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_N_87154_i_4829; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_send_state_2__4830; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_send_state_0__4831; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_N_57045_i; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un5_fc_d_advert_s_11_4832; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un5_fc_h_advert_s_7_4833; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un5_fc_d_advert_axb_10_4834; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un5_fc_d_advert_axb_9_4835; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un5_fc_d_advert_axb_8_4836; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un5_fc_d_advert_axb_7_4837; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un5_fc_d_advert_axb_6_4838; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un5_fc_d_advert_axb_5_4839; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un5_fc_d_advert_axb_4_4840; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un5_fc_d_advert_axb_3_4841; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un5_fc_d_advert_axb_2_4842; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un5_fc_d_advert_axb_1_4843; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un5_fc_d_advert_axb_0_4844; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un5_fc_h_advert_axb_6_4845; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un5_fc_h_advert_axb_5_4846; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un5_fc_h_advert_axb_4_4847; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un5_fc_h_advert_axb_3_4848; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un5_fc_h_advert_axb_2_4849; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un5_fc_h_advert_axb_1_4850; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un5_fc_h_advert_axb_0_4851; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_h_o_2_cry_0_4852; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_h_o_2_cry_1_4853; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_h_o_2_cry_2_4854; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_h_o_2_cry_3_4855; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_h_o_2_cry_4_4856; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_h_o_2_cry_5_4857; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_h_o_2_cry_6_4858; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_2_cry_1_0_4859; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_2_cry_0_4860; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_2_cry_2_0_4861; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_2_cry_1_4862; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_2_cry_3_0_4863; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_2_cry_2_4864; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_2_cry_3_4865; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_2_cry_5_0_4866; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_2_cry_4_4867; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_2_cry_5_4868; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_2_cry_6_4869; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_2_cry_7_4870; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_2_cry_8_4871; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_2_cry_9_4872; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_2_cry_10_4873; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_d_con_2_cry_0_0_4874; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_d_con_2_cry_1_0_4875; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_d_con_2_s_1_4876; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_d_con_2_cry_0_4877; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_d_con_2_cry_2_0_4878; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_d_con_2_s_2_4879; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_d_con_2_cry_1_4880; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_d_con_2_cry_3_0_4881; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_d_con_2_s_3_4882; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_d_con_2_cry_2_4883; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_d_con_2_cry_4_0_4884; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_d_con_2_s_4_4885; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_d_con_2_cry_3_4886; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_d_con_2_cry_5_0_4887; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_d_con_2_s_5_4888; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_d_con_2_cry_4_4889; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_d_con_2_s_6_4890; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_d_con_2_cry_5_4891; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_d_con_2_s_7_4892; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_d_con_2_cry_6_4893; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_d_con_2_s_8_4894; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_d_con_2_cry_7_4895; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_d_con_2_s_9_4896; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_d_con_2_cry_8_4897; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_d_con_2_s_10_4898; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_d_con_2_cry_9_4899; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_d_con_2_s_11_4900; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_d_con_2_cry_10_4901; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_h_o_1_cry_1_0_4902; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_h_o_1_cry_0_4903; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_h_o_1_cry_1_4904; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_h_o_1_cry_3_0_4905; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_h_o_1_cry_2_4906; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_h_o_1_cry_4_0_4907; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_h_o_1_cry_3_4908; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_h_o_1_cry_4_4909; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_h_o_1_cry_6_0_4910; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_h_o_1_cry_5_4911; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_h_o_1_cry_6_4912; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_1_cry_1_0_4913; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_1_cry_0_4914; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_1_cry_2_0_4915; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_1_cry_1_4916; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_1_cry_3_0_4917; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_1_cry_2_4918; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_1_cry_3_4919; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_1_cry_5_0_4920; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_1_cry_4_4921; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_1_cry_6_0_4922; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_1_cry_5_4923; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_1_cry_6_4924; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_1_cry_8_0_4925; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_1_cry_7_4926; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_1_cry_9_0_4927; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_1_cry_8_4928; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_1_cry_10_0_4929; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_1_cry_9_4930; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_1_cry_10_4931; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_GND_4932; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_free_h_4933; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_free_d_4934; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_d_con_2_axb_0_4935; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_1_axb_9_4936; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_1_axb_8_4937; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_1_axb_7_4938; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_1_axb_6_4939; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_1_axb_5_4940; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_1_axb_4_4941; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_1_axb_3_4942; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_1_axb_2_4943; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_1_axb_1_4944; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_1_axb_0_4945; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_h_o_2_axb_4_4946; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_h_o_2_axb_3_4947; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_h_o_2_axb_2_4948; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_h_o_2_axb_1_4949; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_h_o_2_axb_0_4950; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_h_o_1_axb_7_4951; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_h_o_1_axb_6_4952; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_h_o_1_axb_5_4953; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_h_o_1_axb_4_4954; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_h_o_1_axb_3_4955; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_h_o_1_axb_2_4956; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_h_o_1_axb_1_4957; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_h_o_1_axb_0_4958; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_1_axb_11_4959; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_1_axb_10_4960; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_2_axb_11_4961; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_2_axb_10_4962; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_2_axb_9_4963; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_2_axb_8_4964; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_2_axb_7_4965; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_2_axb_6_4966; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_2_axb_5_4967; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_2_axb_4_4968; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_2_axb_3_4969; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_2_axb_2_4970; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_2_axb_1_4971; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_2_axb_0_4972; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_N_61398; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_h_o_2_axb_7_4973; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_h_o_2_axb_6_4974; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_h_o_2_axb_5_4975; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_free_d_13; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_free_h_13; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_d_con_2_axb_11_4976; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_d_con_2_axb_10_4977; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_d_con_2_axb_9_4978; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_d_con_2_axb_8_4979; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_d_con_2_axb_7_4980; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_d_con_2_axb_6_4981; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_d_con_2_axb_5_4982; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_d_con_2_axb_4_4983; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_d_con_2_axb_3_4984; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_d_con_2_axb_2_4985; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_d_con_2_axb_1_4986; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_N_60525_1; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_1_s_9_4987; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_1_s_8_4988; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_1_s_7_4989; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_1_s_6_4990; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_1_s_5_4991; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_1_s_4_4992; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_1_s_3_4993; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_1_s_2_4994; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_1_s_1_4995; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_1_s_0_4996; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_h_o_2_s_4_4997; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_h_o_2_s_3_4998; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_h_o_2_s_2_4999; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_h_o_2_s_1_5000; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_h_o_2_s_0_5001; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_h_o_1_s_7_5002; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_h_o_1_s_6_5003; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_h_o_1_s_5_5004; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_h_o_1_s_4_5005; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_h_o_1_s_3_5006; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_h_o_1_s_2_5007; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_h_o_1_s_1_5008; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_h_o_1_s_0_5009; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_1_s_11_5010; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_1_s_10_5011; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_2_s_11_5012; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_2_s_10_5013; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_2_s_9_5014; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_2_s_8_5015; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_2_s_7_5016; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_2_s_6_5017; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_2_s_5_5018; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_2_s_4_5019; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_2_s_3_5020; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_2_s_2_5021; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_2_s_1_5022; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_2_s_0_5023; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_h_o_2_s_7_5024; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_h_o_2_s_6_5025; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_h_o_2_s_5_5026; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_h_con_i_1__5027; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_h_con_i_3__5028; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_h_con_i_4__5029; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_h_con_i_6__5030; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_d_con_i_1__5031; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_d_con_i_2__5032; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_d_con_i_3__5033; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_d_con_i_5__5034; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_d_con_i_6__5035; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_d_con_i_8__5036; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_d_con_i_9__5037; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_d_con_i_10__5038; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_1_cry_0_ma_5039; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_1_cry_4_ma_5040; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_1_cry_7_ma_5041; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_N_10126_i_5042; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_h_o_1_cry_0_ma_5043; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_h_o_i_m3_i_m4_i_m3_i_m3_0_0__5044; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_h_o_1_cry_2_ma_5045; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_h_o_i_m3_i_m4_i_m3_i_m3_0_2__5046; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_h_o_1_cry_5_ma_5047; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_N_10115_i_5048; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_2_cry_0_ma_5049; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_i_m3_i_m4_i_m3_i_m3_0_0__5050; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_2_cry_4_ma_5051; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_VCC_5052; + wire com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_i_m3_i_m4_i_m3_i_m3_0_4__5053; + wire com_tlm_u_tlm_rx_data_snk_latch_1st_dword_q3_5054; + wire com_tlm_u_tlm_rx_data_snk_pwr_mgmt_mode_on_5055; + wire com_tlm_u_tlm_rx_data_snk_un4_cur_byte_ct_cry_0_5056; + wire com_tlm_u_tlm_rx_data_snk_un4_cur_byte_ct_cry_1_5057; + wire com_tlm_u_tlm_rx_data_snk_un4_cur_byte_ct_cry_2_5058; + wire com_tlm_u_tlm_rx_data_snk_un4_cur_byte_ct_cry_3_5059; + wire com_tlm_u_tlm_rx_data_snk_un4_cur_byte_ct_cry_4_5060; + wire com_tlm_u_tlm_rx_data_snk_un4_cur_byte_ct_cry_5_5061; + wire com_tlm_u_tlm_rx_data_snk_un4_cur_byte_ct_cry_6_5062; + wire com_tlm_u_tlm_rx_data_snk_un4_cur_byte_ct_cry_7_5063; + wire com_tlm_u_tlm_rx_data_snk_un4_cur_byte_ct_cry_8_5064; + wire com_tlm_u_tlm_rx_data_snk_un4_cur_byte_ct_cry_9_5065; + wire com_tlm_u_tlm_rx_data_snk_un4_cur_byte_ct_cry_10_5066; + wire com_tlm_u_tlm_rx_data_snk_latch_1st_dword_q1_5067; + wire com_tlm_u_tlm_rx_data_snk_un4_cur_byte_ct_s_11_sf_5068; + wire com_tlm_u_tlm_rx_data_snk_N_16531_i_5069; + wire com_tlm_u_tlm_rx_data_snk_N_56488_i; + wire com_tlm_u_tlm_rx_data_snk_N_56132_i; + wire com_tlm_u_tlm_rx_data_snk_un1_eof_q_2_1_5070; + wire com_tlm_u_tlm_rx_data_snk_tlp_uc; + wire com_tlm_u_tlm_rx_data_snk_cur_pm_msg_detect; + wire com_tlm_u_tlm_rx_data_snk_cur_hp_msg_detect; + wire com_tlm_u_tlm_rx_data_snk_N_56246_i; + wire com_tlm_u_tlm_rx_data_snk_N_56003_i; + wire com_tlm_u_tlm_rx_data_snk_src_rdy_o_8; + wire com_tlm_u_tlm_rx_data_snk_src_rdy_o_8_u_0_bm_5071; + wire com_tlm_u_tlm_rx_data_snk_src_rdy_o_8_u_0_am_5072; + wire com_tlm_u_tlm_rx_data_snk_cur_drop_5073; + wire com_tlm_u_tlm_rx_data_snk_dsc_o_5; + wire com_tlm_u_tlm_rx_data_snk_dsc_o_5_0_am_5074; + wire com_tlm_u_tlm_rx_data_snk_un4_cur_byte_ct_s_1_5075; + wire com_tlm_u_tlm_rx_data_snk_N_17463_i; + wire com_tlm_u_tlm_rx_data_snk_N_17291_i; + wire com_tlm_u_tlm_rx_data_snk_N_17289_i; + wire com_tlm_u_tlm_rx_data_snk_un4_cur_byte_ct_s_11_5076; + wire com_tlm_u_tlm_rx_data_snk_un4_cur_byte_ct_s_10_5077; + wire com_tlm_u_tlm_rx_data_snk_un4_cur_byte_ct_s_9_5078; + wire com_tlm_u_tlm_rx_data_snk_un4_cur_byte_ct_s_8_5079; + wire com_tlm_u_tlm_rx_data_snk_un4_cur_byte_ct_s_7_5080; + wire com_tlm_u_tlm_rx_data_snk_un4_cur_byte_ct_s_6_5081; + wire com_tlm_u_tlm_rx_data_snk_un4_cur_byte_ct_s_5_5082; + wire com_tlm_u_tlm_rx_data_snk_un4_cur_byte_ct_s_4_5083; + wire com_tlm_u_tlm_rx_data_snk_un4_cur_byte_ct_s_3_5084; + wire com_tlm_u_tlm_rx_data_snk_un4_cur_byte_ct_s_2_5085; + wire com_tlm_u_tlm_rx_data_snk_N_61370_1; + wire com_tlm_u_tlm_rx_data_snk_ds_np_i_5086; + wire com_tlm_u_tlm_rx_data_snk_packet_ip_5087; + wire com_tlm_u_tlm_rx_data_snk_cur_fulltype_oh_1_; + wire com_tlm_u_tlm_rx_data_snk_cur_cpl_ep_6; + wire com_tlm_u_tlm_rx_data_snk_N_56509_i; + wire com_tlm_u_tlm_rx_data_snk_err_tlp_malformed_o_3_5088; + wire com_tlm_u_tlm_rx_data_snk_N_16424_i; + wire com_tlm_u_tlm_rx_data_snk_N_16426_i; + wire com_tlm_u_tlm_rx_data_snk_N_58441; + wire com_tlm_u_tlm_rx_data_snk_eof_o_5; + wire com_tlm_u_tlm_rx_data_snk_rem_o_5; + wire com_tlm_u_tlm_rx_data_snk_remove_lastword_5089; + wire com_tlm_u_tlm_rx_data_snk_cur_cpl_abort_6; + wire com_tlm_u_tlm_rx_data_snk_cur_cpl_ur_6; + wire com_tlm_u_tlm_rx_data_snk_remove_lastword_6; + wire com_tlm_u_tlm_rx_data_snk_cur_length1_2_0_a2_0_a2_0_a2_0_a2_5_5090; + wire com_tlm_u_tlm_rx_data_snk_cur_length1_2_0_a2_0_a2_0_a2_0_a2_4_5091; + wire com_tlm_u_tlm_rx_data_snk_err_tlp_ur_o_3_5092; + wire com_tlm_u_tlm_rx_data_snk_tlp_ur; + wire com_tlm_u_tlm_rx_data_snk_malformed; + wire com_tlm_u_tlm_rx_data_snk_N_86752_i_5093; + wire com_tlm_u_tlm_rx_data_snk_N_87127_i_5094; + wire com_tlm_u_tlm_rx_data_snk_fc_use_cpl_o_5_5095; + wire com_tlm_u_tlm_rx_data_snk_fc_use_np_o_5_5096; + wire com_tlm_u_tlm_rx_data_snk_fc_use_p_o_5_5097; + wire com_tlm_u_tlm_rx_data_snk_N_56498_i; + wire com_tlm_u_tlm_rx_data_snk_fc_unuse_o_5_5098; + wire com_tlm_u_tlm_rx_data_snk_N_56507_i; + wire com_tlm_u_tlm_rx_data_snk_N_56236_i; + wire com_tlm_u_tlm_rx_data_snk_cur_fulltype_oh40_1; + wire com_tlm_u_tlm_rx_data_snk_stat_tlp_cpl_abort_o_5_5099; + wire com_tlm_u_tlm_rx_data_snk_cur_cpl_abort_5100; + wire com_tlm_u_tlm_rx_data_snk_stat_tlp_cpl_ep_o_5_5101; + wire com_tlm_u_tlm_rx_data_snk_cur_cpl_ep_5102; + wire com_tlm_u_tlm_rx_data_snk_stat_tlp_cpl_ur_o_5_5103; + wire com_tlm_u_tlm_rx_data_snk_cur_cpl_ur_5104; + wire com_tlm_u_tlm_rx_data_snk_stat_tlp_ep_o_5_5105; + wire com_tlm_u_tlm_rx_data_snk_N_59435_1; + wire com_tlm_u_tlm_rx_data_snk_N_56191_i; + wire com_tlm_u_tlm_rx_data_snk_dsc_o_5_0_bm_5106; + wire com_tlm_u_tlm_rx_data_snk_eof_nd_q_4_; + wire com_tlm_u_tlm_rx_data_snk_cur_byte_ct_6_1_; + wire com_tlm_u_tlm_rx_data_snk_cur_byte_ct_6_0_; + wire com_tlm_u_tlm_rx_data_snk_cur_bytes_missing_1_axb0_5107; + wire com_tlm_u_tlm_rx_data_snk_cur_byte_ct_6_11_; + wire com_tlm_u_tlm_rx_data_snk_cur_byte_ct_6_10_; + wire com_tlm_u_tlm_rx_data_snk_cur_byte_ct_6_9_; + wire com_tlm_u_tlm_rx_data_snk_cur_byte_ct_6_8_; + wire com_tlm_u_tlm_rx_data_snk_cur_byte_ct_6_7_; + wire com_tlm_u_tlm_rx_data_snk_cur_byte_ct_6_6_; + wire com_tlm_u_tlm_rx_data_snk_cur_byte_ct_6_5_; + wire com_tlm_u_tlm_rx_data_snk_cur_byte_ct_6_4_; + wire com_tlm_u_tlm_rx_data_snk_cur_byte_ct_6_3_; + wire com_tlm_u_tlm_rx_data_snk_N_59469_i_5108; + wire com_tlm_u_tlm_rx_data_snk_sof_q_5__5109; + wire com_tlm_u_tlm_rx_data_snk_rem_q_4_; + wire com_tlm_u_tlm_rx_data_snk_rem_q_5__5110; + wire com_tlm_u_tlm_rx_data_snk_eof_q_5__5111; + wire com_tlm_u_tlm_rx_data_snk_eof_q_1__5112; + wire com_tlm_u_tlm_rx_data_snk_eof_q_2__5113; + wire com_tlm_u_tlm_rx_data_snk_dsc_q_4_; + wire com_tlm_u_tlm_rx_data_snk_dsc_q_5__5114; + wire com_tlm_u_tlm_rx_data_snk_src_rdy_q_4_; + wire com_tlm_u_tlm_rx_data_snk_src_rdy_q_5__5115; + wire com_tlm_u_tlm_rx_data_snk_sof_q_4_; + wire com_tlm_u_tlm_rx_data_snk_cur_ep_q_5116; + wire com_tlm_u_tlm_rx_data_snk_cur_td_q_5117; + wire com_tlm_u_tlm_rx_data_snk_cur_ep_5118; + wire com_tlm_u_tlm_rx_data_snk_cur_td_5119; + wire com_tlm_u_tlm_rx_data_snk_cur_rem_0_sqmuxa; + wire com_tlm_u_tlm_rx_data_snk_cur_rem_5120; + wire com_tlm_u_tlm_rx_data_snk_latch_1st_dword_q2; + wire com_tlm_u_tlm_rx_data_snk_cur_np_2; + wire com_tlm_u_tlm_rx_data_snk_cur_tc0_2; + wire com_tlm_u_tlm_rx_data_snk_cur_tc0_5121; + wire com_tlm_u_tlm_rx_data_snk_cur_data_credits_vld; + wire com_tlm_u_tlm_rx_data_snk_eof_q_3__5122; + wire com_tlm_u_tlm_rx_data_snk_cur_cfg; + wire com_tlm_u_tlm_rx_data_snk_cur_cpl_5123; + wire com_tlm_u_tlm_rx_data_snk_latch_1st_dword_q4_5124; + wire com_tlm_u_tlm_rx_data_snk_cur_np_5125; + wire com_tlm_u_tlm_rx_data_snk_cur_length1_2; + wire com_tlm_u_tlm_rx_data_snk_cur_length1_5126; + wire com_tlm_u_tlm_rx_data_snk_N_10630_i; + wire com_tlm_u_tlm_rx_data_snk_cur_fulltype_64_5127; + wire com_tlm_u_tlm_rx_data_snk_cur_fulltype_mem12_i_i; + wire com_tlm_u_tlm_rx_data_snk_cur_fulltype_mem_5128; + wire com_tlm_u_tlm_rx_data_snk_N_25253_i; + wire com_tlm_u_tlm_rx_data_snk_N_25251_i; + wire com_tlm_u_tlm_rx_data_snk_N_25249_i; + wire com_tlm_u_tlm_rx_data_snk_N_25247_i; + wire com_tlm_u_tlm_rx_data_snk_latch_3rd_dword_q1; + wire com_tlm_u_tlm_rx_data_snk_N_25245_i; + wire com_tlm_u_tlm_rx_data_snk_N_10626_i; + wire com_tlm_u_tlm_rx_data_snk_cur_fulltype_oh_7__5129; + wire com_tlm_u_tlm_rx_data_snk_cur_fulltype_oh35_i_a2_0_a2_0_a2_5130; + wire com_tlm_u_tlm_rx_data_snk_cur_fulltype_oh_5__5131; + wire com_tlm_u_tlm_rx_data_snk_cur_fulltype_oh37; + wire com_tlm_u_tlm_rx_data_snk_cur_fulltype_oh_3__5132; + wire com_tlm_u_tlm_rx_data_snk_latch_2nd_dword; + wire com_tlm_u_tlm_rx_data_snk_cur_fulltype_oh40; + wire com_tlm_u_tlm_rx_data_snk_cur_fulltype_oh_0__5133; + wire com_tlm_u_tlm_rx_data_snk_d_o_62_N_6; + wire com_tlm_u_tlm_rx_data_snk_d_o_61_N_6; + wire com_tlm_u_tlm_rx_data_snk_d_o_60_N_6; + wire com_tlm_u_tlm_rx_data_snk_d_o_59_N_6; + wire com_tlm_u_tlm_rx_data_snk_d_o_58_N_6; + wire com_tlm_u_tlm_rx_data_snk_d_o_57_N_6; + wire com_tlm_u_tlm_rx_data_snk_d_o_56_N_6; + wire com_tlm_u_tlm_rx_data_snk_d_o_55_N_6; + wire com_tlm_u_tlm_rx_data_snk_d_o_54_N_6; + wire com_tlm_u_tlm_rx_data_snk_d_o_53_N_6; + wire com_tlm_u_tlm_rx_data_snk_d_o_52_N_6; + wire com_tlm_u_tlm_rx_data_snk_d_o_51_N_6; + wire com_tlm_u_tlm_rx_data_snk_d_o_50_N_6; + wire com_tlm_u_tlm_rx_data_snk_d_o_49_N_6; + wire com_tlm_u_tlm_rx_data_snk_d_o_48_N_6; + wire com_tlm_u_tlm_rx_data_snk_d_o_47_N_6; + wire com_tlm_u_tlm_rx_data_snk_d_o_46_N_6; + wire com_tlm_u_tlm_rx_data_snk_d_o_45_N_6; + wire com_tlm_u_tlm_rx_data_snk_d_o_44_N_6; + wire com_tlm_u_tlm_rx_data_snk_d_o_43_N_6; + wire com_tlm_u_tlm_rx_data_snk_d_o_42_N_6; + wire com_tlm_u_tlm_rx_data_snk_d_o_41_N_6; + wire com_tlm_u_tlm_rx_data_snk_d_o_40_N_6; + wire com_tlm_u_tlm_rx_data_snk_d_o_39_N_6; + wire com_tlm_u_tlm_rx_data_snk_d_o_38_N_6; + wire com_tlm_u_tlm_rx_data_snk_d_o_37_N_6; + wire com_tlm_u_tlm_rx_data_snk_d_o_36_N_6; + wire com_tlm_u_tlm_rx_data_snk_d_o_35_N_6; + wire com_tlm_u_tlm_rx_data_snk_d_o_34_N_6; + wire com_tlm_u_tlm_rx_data_snk_d_o_33_N_6; + wire com_tlm_u_tlm_rx_data_snk_d_o_32_N_6; + wire com_tlm_u_tlm_rx_data_snk_d_o_31_N_6; + wire com_tlm_u_tlm_rx_data_snk_d_o_30_N_6; + wire com_tlm_u_tlm_rx_data_snk_d_o_29_N_6; + wire com_tlm_u_tlm_rx_data_snk_d_o_28_N_6; + wire com_tlm_u_tlm_rx_data_snk_d_o_27_N_6; + wire com_tlm_u_tlm_rx_data_snk_d_o_26_N_6; + wire com_tlm_u_tlm_rx_data_snk_d_o_25_N_6; + wire com_tlm_u_tlm_rx_data_snk_d_o_24_N_6; + wire com_tlm_u_tlm_rx_data_snk_d_o_23_N_6; + wire com_tlm_u_tlm_rx_data_snk_d_o_22_N_6; + wire com_tlm_u_tlm_rx_data_snk_d_o_21_N_6; + wire com_tlm_u_tlm_rx_data_snk_d_o_20_N_6; + wire com_tlm_u_tlm_rx_data_snk_N_17287_i; + wire com_tlm_u_tlm_rx_data_snk_d_o_19_N_6; + wire com_tlm_u_tlm_rx_data_snk_d_o_18_N_6; + wire com_tlm_u_tlm_rx_data_snk_d_o_17_N_6; + wire com_tlm_u_tlm_rx_data_snk_d_o_16_N_6; + wire com_tlm_u_tlm_rx_data_snk_d_o_15_N_6; + wire com_tlm_u_tlm_rx_data_snk_d_o_14_N_6; + wire com_tlm_u_tlm_rx_data_snk_d_o_13_N_6; + wire com_tlm_u_tlm_rx_data_snk_d_o_12_N_6; + wire com_tlm_u_tlm_rx_data_snk_d_o_11_N_6; + wire com_tlm_u_tlm_rx_data_snk_d_o_10_N_6; + wire com_tlm_u_tlm_rx_data_snk_eof_nd_q_1__5134; + wire com_tlm_u_tlm_rx_data_snk_eof_nd_q_N_6; + wire com_tlm_u_tlm_rx_data_snk_d_o_9_N_6; + wire com_tlm_u_tlm_rx_data_snk_d_o_8_N_6; + wire com_tlm_u_tlm_rx_data_snk_d_o_7_N_6; + wire com_tlm_u_tlm_rx_data_snk_d_o_6_N_6; + wire com_tlm_u_tlm_rx_data_snk_d_o_5_N_6; + wire com_tlm_u_tlm_rx_data_snk_d_o_4_N_6; + wire com_tlm_u_tlm_rx_data_snk_d_o_3_N_6; + wire com_tlm_u_tlm_rx_data_snk_d_o_2_N_6; + wire com_tlm_u_tlm_rx_data_snk_d_o_1_N_6; + wire com_tlm_u_tlm_rx_data_snk_d_o_0_N_6; + wire com_tlm_u_tlm_rx_data_snk_d_o_N_6; + wire com_tlm_u_tlm_rx_data_snk_sof_q_1__5135; + wire com_tlm_u_tlm_rx_data_snk_sof_q_N_6; + wire com_tlm_u_tlm_rx_data_snk_rem_q_1__5136; + wire com_tlm_u_tlm_rx_data_snk_rem_q_N_6; + wire com_tlm_u_tlm_rx_data_snk_dsc_q_1__5137; + wire com_tlm_u_tlm_rx_data_snk_dsc_q_N_6; + wire com_tlm_u_tlm_rx_data_snk_src_rdy_q_1__5138; + wire com_tlm_u_tlm_rx_data_snk_GND_5139; + wire com_tlm_u_tlm_rx_data_snk_VCC_5140; + wire com_tlm_u_tlm_rx_data_snk_src_rdy_q_N_6; + wire com_tlm_u_tlm_rx_data_snk_next_cur_drop_5141; + wire com_tlm_u_tlm_rx_data_snk_eof_o_3; + wire com_tlm_u_tlm_rx_data_snk_N_10631; + wire com_tlm_u_tlm_rx_data_snk_un4_cur_byte_ct_s_10_sf_5142; + wire com_tlm_u_tlm_rx_data_snk_un4_cur_byte_ct_s_9_sf_5143; + wire com_tlm_u_tlm_rx_data_snk_un4_cur_byte_ct_s_8_sf_5144; + wire com_tlm_u_tlm_rx_data_snk_un4_cur_byte_ct_s_7_sf_5145; + wire com_tlm_u_tlm_rx_data_snk_un4_cur_byte_ct_s_6_sf_5146; + wire com_tlm_u_tlm_rx_data_snk_un4_cur_byte_ct_s_5_sf_5147; + wire com_tlm_u_tlm_rx_data_snk_un4_cur_byte_ct_s_4_sf_5148; + wire com_tlm_u_tlm_rx_data_snk_un4_cur_byte_ct_s_3_sf_5149; + wire com_tlm_u_tlm_rx_data_snk_un4_cur_byte_ct_axb_2_5150; + wire com_tlm_u_tlm_rx_data_snk_un4_cur_byte_ct_axb_1_5151; + wire com_tlm_u_tlm_rx_data_snk_un4_cur_byte_ct_cry_0_sf_5152; + wire com_tlm_u_tlm_rx_data_snk_malformed_checks_sof_q3_5153; + wire com_tlm_u_tlm_rx_data_snk_malformed_checks_ur_pwr_mgmt_5154; + wire com_tlm_u_tlm_rx_data_snk_malformed_checks_uc_pwr_mgmt_5155; + wire com_tlm_u_tlm_rx_data_snk_malformed_checks_un6_malformed_maxsize_cry_0_5156; + wire com_tlm_u_tlm_rx_data_snk_malformed_checks_un6_malformed_maxsize_cry_1_5157; + wire com_tlm_u_tlm_rx_data_snk_malformed_checks_un6_malformed_maxsize_cry_2_5158; + wire com_tlm_u_tlm_rx_data_snk_malformed_checks_un6_malformed_maxsize_cry_3_5159; + wire com_tlm_u_tlm_rx_data_snk_malformed_checks_un6_malformed_maxsize_cry_4_5160; + wire com_tlm_u_tlm_rx_data_snk_malformed_checks_un6_malformed_maxsize_cry_5_5161; + wire com_tlm_u_tlm_rx_data_snk_malformed_checks_un6_malformed_maxsize_cry_6_5162; + wire com_tlm_u_tlm_rx_data_snk_malformed_checks_un6_malformed_maxsize_cry_7_5163; + wire com_tlm_u_tlm_rx_data_snk_malformed_checks_un6_malformed_maxsize_cry_8_5164; + wire com_tlm_u_tlm_rx_data_snk_malformed_checks_un1_data_credits_o_cry_0_5165; + wire com_tlm_u_tlm_rx_data_snk_malformed_checks_un1_data_credits_o_cry_1_5166; + wire com_tlm_u_tlm_rx_data_snk_malformed_checks_un1_data_credits_o_cry_2_5167; + wire com_tlm_u_tlm_rx_data_snk_malformed_checks_un1_data_credits_o_cry_3_5168; + wire com_tlm_u_tlm_rx_data_snk_malformed_checks_un1_data_credits_o_cry_4_5169; + wire com_tlm_u_tlm_rx_data_snk_malformed_checks_GND_5170; + wire com_tlm_u_tlm_rx_data_snk_malformed_checks_un4_word_ct_s_1_5171; + wire com_tlm_u_tlm_rx_data_snk_malformed_checks_un4_word_ct_cry_0_5172; + wire com_tlm_u_tlm_rx_data_snk_malformed_checks_un4_word_ct_s_2_5173; + wire com_tlm_u_tlm_rx_data_snk_malformed_checks_un4_word_ct_cry_1_5174; + wire com_tlm_u_tlm_rx_data_snk_malformed_checks_un4_word_ct_s_3_5175; + wire com_tlm_u_tlm_rx_data_snk_malformed_checks_un4_word_ct_cry_2_5176; + wire com_tlm_u_tlm_rx_data_snk_malformed_checks_un4_word_ct_s_4_5177; + wire com_tlm_u_tlm_rx_data_snk_malformed_checks_un4_word_ct_cry_3_5178; + wire com_tlm_u_tlm_rx_data_snk_malformed_checks_VCC_5179; + wire com_tlm_u_tlm_rx_data_snk_malformed_checks_un4_word_ct_s_5_5180; + wire com_tlm_u_tlm_rx_data_snk_malformed_checks_un4_word_ct_cry_4_5181; + wire com_tlm_u_tlm_rx_data_snk_malformed_checks_un4_word_ct_s_6_5182; + wire com_tlm_u_tlm_rx_data_snk_malformed_checks_un4_word_ct_cry_5_5183; + wire com_tlm_u_tlm_rx_data_snk_malformed_checks_eof_q2_5184; + wire com_tlm_u_tlm_rx_data_snk_malformed_checks_tlp_uc_o_0_sqmuxa; + wire com_tlm_u_tlm_rx_data_snk_malformed_checks_uc_format_5185; + wire com_tlm_u_tlm_rx_data_snk_malformed_checks_tlp_ur_o_0_sqmuxa; + wire com_tlm_u_tlm_rx_data_snk_malformed_checks_ur_format_5186; + wire com_tlm_u_tlm_rx_data_snk_malformed_checks_un1_data_credits_o_axb_5_5187; + wire com_tlm_u_tlm_rx_data_snk_malformed_checks_N_59470_i_5188; + wire com_tlm_u_tlm_rx_data_snk_malformed_checks_type_1dw_5189; + wire com_tlm_u_tlm_rx_data_snk_malformed_checks_malformed_message_5190; + wire com_tlm_u_tlm_rx_data_snk_malformed_checks_length_1dw_5191; + wire com_tlm_u_tlm_rx_data_snk_malformed_checks_N_56133_i; + wire com_tlm_u_tlm_rx_data_snk_malformed_checks_malformed_over_3_i_0_0_o3_4_5192; + wire com_tlm_u_tlm_rx_data_snk_malformed_checks_cfg0_ip_0_sqmuxa; + wire com_tlm_u_tlm_rx_data_snk_malformed_checks_N_56362_i_0; + wire com_tlm_u_tlm_rx_data_snk_malformed_checks_N_56185; + wire com_tlm_u_tlm_rx_data_snk_malformed_checks_cfg1_ip_0_sqmuxa; + wire com_tlm_u_tlm_rx_data_snk_malformed_checks_cfg1_ip_0_sqmuxa_1_0; + wire com_tlm_u_tlm_rx_data_snk_malformed_checks_malformed_maxsize_3_0_0_0_0_a2_0_1_5_5193; + wire com_tlm_u_tlm_rx_data_snk_malformed_checks_malformed_maxsize_3_0_0_0_0_a2_0_1_4_5194; + wire com_tlm_u_tlm_rx_data_snk_malformed_checks_N_13912_i; + wire com_tlm_u_tlm_rx_data_snk_malformed_checks_type_1dw_0_sqmuxa_i_0_0_0_1_5195; + wire com_tlm_u_tlm_rx_data_snk_malformed_checks_N_58513; + wire com_tlm_u_tlm_rx_data_snk_malformed_checks_malformed_fulltype16_0_0_0_0_39380_5196; + wire com_tlm_u_tlm_rx_data_snk_malformed_checks_delay_ctc_i; + wire com_tlm_u_tlm_rx_data_snk_malformed_checks_un1_data_credits_o_s_1_5197; + wire com_tlm_u_tlm_rx_data_snk_malformed_checks_un1_data_credits_o_s_0_5198; + wire com_tlm_u_tlm_rx_data_snk_malformed_checks_un1_data_credits_o_s_5_5199; + wire com_tlm_u_tlm_rx_data_snk_malformed_checks_un1_data_credits_o_s_4_5200; + wire com_tlm_u_tlm_rx_data_snk_malformed_checks_un1_data_credits_o_s_3_5201; + wire com_tlm_u_tlm_rx_data_snk_malformed_checks_un1_data_credits_o_s_2_5202; + wire com_tlm_u_tlm_rx_data_snk_malformed_checks_N_62722_i_5203; + wire com_tlm_u_tlm_rx_data_snk_malformed_checks_malformed_len_5204; + wire com_tlm_u_tlm_rx_data_snk_malformed_checks_malformed_fmt_5205; + wire com_tlm_u_tlm_rx_data_snk_malformed_checks_N_59447_i_5206; + wire com_tlm_u_tlm_rx_data_snk_malformed_checks_malformed_rem_5207; + wire com_tlm_u_tlm_rx_data_snk_malformed_checks_malformed_min_5208; + wire com_tlm_u_tlm_rx_data_snk_malformed_checks_malformed_eof_5209; + wire com_tlm_u_tlm_rx_data_snk_malformed_checks_N_56353_i; + wire com_tlm_u_tlm_rx_data_snk_malformed_checks_is_usr_leg_ap_3; + wire com_tlm_u_tlm_rx_data_snk_malformed_checks_is_usr_leg_ap_3_0_a2_0_a2_0_a2_0_a2_1; + wire com_tlm_u_tlm_rx_data_snk_malformed_checks_N_59001; + wire com_tlm_u_tlm_rx_data_snk_malformed_checks_length_1dw_3; + wire com_tlm_u_tlm_rx_data_snk_malformed_checks_N_62723_i_5210; + wire com_tlm_u_tlm_rx_data_snk_malformed_checks_is_usr_leg_ap_5211; + wire com_tlm_u_tlm_rx_data_snk_malformed_checks_is_usr_ext_ap_5212; + wire com_tlm_u_tlm_rx_data_snk_malformed_checks_cfg1_ip_5213; + wire com_tlm_u_tlm_rx_data_snk_malformed_checks_cfg0_ip_5214; + wire com_tlm_u_tlm_rx_data_snk_malformed_checks_N_85660_i_5215; + wire com_tlm_u_tlm_rx_data_snk_malformed_checks_malformed_tc_5216; + wire com_tlm_u_tlm_rx_data_snk_malformed_checks_malformed_maxsize_5217; + wire com_tlm_u_tlm_rx_data_snk_malformed_checks_malformed_fulltype_5218; + wire com_tlm_u_tlm_rx_data_snk_malformed_checks_malformed_fmt_3_i_0_0_2_5219; + wire com_tlm_u_tlm_rx_data_snk_malformed_checks_uc_pwr_mgmt_7; + wire com_tlm_u_tlm_rx_data_snk_malformed_checks_uc_pwr_mgmt_7_1; + wire com_tlm_u_tlm_rx_data_snk_malformed_checks_malformed_rem_3_5220; + wire com_tlm_u_tlm_rx_data_snk_malformed_checks_N_56346_i; + wire com_tlm_u_tlm_rx_data_snk_malformed_checks_N_53153_i; + wire com_tlm_u_tlm_rx_data_snk_malformed_checks_fulltype_tc012_i_0_0_0_5221; + wire com_tlm_u_tlm_rx_data_snk_malformed_checks_msgcode_hotplug12_0_0_0_0_5222; + wire com_tlm_u_tlm_rx_data_snk_malformed_checks_N_56244_i; + wire com_tlm_u_tlm_rx_data_snk_malformed_checks_N_85578_i_5223; + wire com_tlm_u_tlm_rx_data_snk_malformed_checks_malformed_fulltype16_0_0_0_0_1_5224; + wire com_tlm_u_tlm_rx_data_snk_malformed_checks_N_58350; + wire com_tlm_u_tlm_rx_data_snk_malformed_checks_N_56501_i; + wire com_tlm_u_tlm_rx_data_snk_malformed_checks_msgcode_dmatch_4_0_x3_0_x3_0_o3_0; + wire com_tlm_u_tlm_rx_data_snk_malformed_checks_msgcode_sigdef16_0_0_0_39393_5225; + wire com_tlm_u_tlm_rx_data_snk_malformed_checks_N_58343; + wire com_tlm_u_tlm_rx_data_snk_malformed_checks_N_58342; + wire com_tlm_u_tlm_rx_data_snk_malformed_checks_N_13914_i; + wire com_tlm_u_tlm_rx_data_snk_malformed_checks_ur_pwr_mgmt_7_i_0_0_0_1_5226; + wire com_tlm_u_tlm_rx_data_snk_malformed_checks_N_28370_i; + wire com_tlm_u_tlm_rx_data_snk_malformed_checks_malformed_over_5227; + wire com_tlm_u_tlm_rx_data_snk_malformed_checks_N_87098_i_5228; + wire com_tlm_u_tlm_rx_data_snk_malformed_checks_un6_malformed_maxsize_cry_9_5229; + wire com_tlm_u_tlm_rx_data_snk_malformed_checks_N_57276_1; + wire com_tlm_u_tlm_rx_data_snk_malformed_checks_N_10359_i_i; + wire com_tlm_u_tlm_rx_data_snk_malformed_checks_N_10359_i_0_0_0_0_39304_5230; + wire com_tlm_u_tlm_rx_data_snk_malformed_checks_N_10637_i_1; + wire com_tlm_u_tlm_rx_data_snk_malformed_checks_malformed_eof_3_i_0_0_a2_0_4_5231; + wire com_tlm_u_tlm_rx_data_snk_malformed_checks_fulltype_in_5__5232; + wire com_tlm_u_tlm_rx_data_snk_malformed_checks_fulltype_in_0__5233; + wire com_tlm_u_tlm_rx_data_snk_malformed_checks_N_56050_i; + wire com_tlm_u_tlm_rx_data_snk_malformed_checks_msgcode_vendef12; + wire com_tlm_u_tlm_rx_data_snk_malformed_checks_N_87170_i_5234; + wire com_tlm_u_tlm_rx_data_snk_malformed_checks_routing_vendef_5235; + wire com_tlm_u_tlm_rx_data_snk_malformed_checks_N_85558_i_5236; + wire com_tlm_u_tlm_rx_data_snk_malformed_checks_fulltype_tc0_5237; + wire com_tlm_u_tlm_rx_data_snk_malformed_checks_N_10641_i; + wire com_tlm_u_tlm_rx_data_snk_malformed_checks_msgcode_hotplug_5238; + wire com_tlm_u_tlm_rx_data_snk_malformed_checks_N_57044_i_0; + wire com_tlm_u_tlm_rx_data_snk_malformed_checks_msgcode_dmatch_5239; + wire com_tlm_u_tlm_rx_data_snk_malformed_checks_N_10638_i; + wire com_tlm_u_tlm_rx_data_snk_malformed_checks_msgcode_sigdef_5240; + wire com_tlm_u_tlm_rx_data_snk_malformed_checks_msgcode_routing18_i_i; + wire com_tlm_u_tlm_rx_data_snk_malformed_checks_N_10637_i; + wire com_tlm_u_tlm_rx_data_snk_malformed_checks_delay_ct_i_5241; + wire com_tlm_u_tlm_rx_data_snk_malformed_checks_N_25301_i; + wire com_tlm_u_tlm_rx_data_snk_malformed_checks_N_85575_i_5242; + wire com_tlm_u_tlm_rx_data_snk_malformed_checks_msgcode_vendef_5243; + wire com_tlm_u_tlm_rx_data_snk_malformed_checks_malformed_message_6_0_0_0_0_1_5244; + wire com_tlm_u_tlm_rx_data_snk_malformed_checks_N_85575_i_1_5245; + wire com_tlm_u_tlm_rx_data_snk_malformed_checks_N_57271; + wire com_tlm_u_tlm_rx_data_snk_malformed_checks_N_28368_i; + wire com_tlm_u_tlm_rx_data_snk_malformed_checks_malformed_eof_3_i_0_0_1_5246; + wire com_tlm_u_tlm_rx_data_snk_malformed_checks_delay_ct_5247; + wire com_tlm_u_tlm_rx_data_snk_malformed_checks_N_57047_i; + wire com_tlm_u_tlm_rx_data_snk_malformed_checks_un1_data_credits_o_axb_4_5248; + wire com_tlm_u_tlm_rx_data_snk_malformed_checks_un1_data_credits_o_axb_3_5249; + wire com_tlm_u_tlm_rx_data_snk_malformed_checks_un1_data_credits_o_axb_2_5250; + wire com_tlm_u_tlm_rx_data_snk_malformed_checks_un1_data_credits_o_axb_1_5251; + wire com_tlm_u_tlm_rx_data_snk_malformed_checks_un1_data_credits_o_axb_0_5252; + wire com_tlm_u_tlm_rx_data_snk_malformed_checks_un6_malformed_maxsize_axb_7_i_5253; + wire com_tlm_u_tlm_rx_data_snk_malformed_checks_un6_malformed_maxsize_axb_6_i_5254; + wire com_tlm_u_tlm_rx_data_snk_malformed_checks_un6_malformed_maxsize_axb_5_i_5255; + wire com_tlm_u_tlm_rx_data_snk_pwr_mgmt_cur_pm_turn_off_6_0_a2_0_a2_0_a2_1_0_0_5256; + wire com_tlm_u_tlm_rx_data_snk_pwr_mgmt_N_10635_i_5257; + wire com_tlm_u_tlm_rx_data_snk_pwr_mgmt_pm_as_nak_l1_o_5_5258; + wire com_tlm_u_tlm_rx_data_snk_pwr_mgmt_cur_pm_as_nak_l1_5259; + wire com_tlm_u_tlm_rx_data_snk_pwr_mgmt_pm_set_slot_pwr_o_5_5260; + wire com_tlm_u_tlm_rx_data_snk_pwr_mgmt_cur_pm_set_slot_pwr_5261; + wire com_tlm_u_tlm_rx_data_snk_pwr_mgmt_pm_turn_off_o_5_5262; + wire com_tlm_u_tlm_rx_data_snk_pwr_mgmt_cur_pm_turn_off_5263; + wire com_tlm_u_tlm_rx_data_snk_pwr_mgmt_act_pwr_mgmt_q1c_5264; + wire com_tlm_u_tlm_rx_data_snk_pwr_mgmt_cur_pm_as_nak_l1_6; + wire com_tlm_u_tlm_rx_data_snk_pwr_mgmt_cur_pm_set_slot_pwr_6; + wire com_tlm_u_tlm_rx_data_snk_pwr_mgmt_cur_pm_set_slot_pwr_6_1; + wire com_tlm_u_tlm_rx_data_snk_pwr_mgmt_cur_pm_turn_off_6; + wire com_tlm_u_tlm_rx_data_snk_pwr_mgmt_cur_pm_turn_off_6_1_0; + wire com_tlm_u_tlm_rx_data_snk_pwr_mgmt_cur_pm_turn_off_6_0_a2_0_a2_0_a2_1_5265; + wire com_tlm_u_tlm_rx_data_snk_pwr_mgmt_un1_act_pwr_mgmt_i_1_i_5266; + wire com_tlm_u_tlm_rx_data_snk_pwr_mgmt_act_pwr_mgmt_q1_5267; + wire com_tlm_u_tlm_rx_data_snk_bar_hit_check_rio_o_5; + wire com_tlm_u_tlm_rx_data_snk_bar_hit_check_rmem64_o_5; + wire com_tlm_u_tlm_rx_data_snk_bar_hit_check_rmem32_o_5; + wire com_tlm_u_tlm_rx_data_snk_bar_hit_N_87156_i_5268; + wire com_tlm_u_tlm_rx_data_snk_bar_hit_N_87157_i_5269; + wire com_tlm_u_tlm_rx_data_snk_bar_hit_N_87158_i_5270; + wire com_tlm_u_tlm_rx_data_snk_bar_hit_N_87172_i_5271; + wire com_tlm_u_tlm_rx_data_snk_bar_hit_N_87173_i_5272; + wire com_tlm_u_tlm_rx_data_snk_bar_hit_N_87159_i_5273; + wire com_tlm_u_tlm_rx_data_snk_bar_hit_N_87160_i_5274; + wire com_tlm_u_tlm_rx_data_snk_bar_hit_N_87161_i_5275; + wire com_tlm_u_tlm_rx_data_snk_bar_hit_N_87162_i_5276; + wire com_tlm_u_tlm_rx_data_snk_bar_hit_N_87163_i_5277; + wire com_tlm_u_tlm_rx_data_snk_bar_hit_N_87164_i_5278; + wire com_tlm_u_tlm_rx_data_snk_bar_hit_N_87165_i_5279; + wire com_tlm_u_tlm_rx_data_snk_bar_hit_N_87166_i_5280; + wire com_tlm_u_tlm_rx_data_snk_bar_hit_N_87167_i_5281; + wire com_tlm_u_tlm_rx_data_snk_bar_hit_N_87168_i_5282; + wire com_tlm_u_tlm_rx_data_snk_bar_hit_N_87169_i_5283; + wire com_tlm_u_tlm_rx_fc_src_GND_5284; + wire com_tlm_u_tlm_rx_fc_src_lnk_tfc_src_rdy; + wire com_tlm_u_tlm_rx_fc_src_init_pending_5285; + wire com_tlm_u_tlm_rx_fc_src_N_87522_i_5286; + wire com_tlm_u_tlm_rx_fc_src_N_87525_i_5287; + wire com_tlm_u_tlm_rx_fc_src_N_87232_i_5288; + wire com_tlm_u_tlm_rx_fc_src_N_85516_i_5289; + wire com_tlm_u_tlm_rx_fc_src_N_58440; + wire com_tlm_u_tlm_rx_fc_src_initFC_stc_i; + wire com_tlm_u_tlm_rx_fc_src_initFC_stc_0_i; + wire com_tlm_u_tlm_rx_fc_src_N_56332_i; + wire com_tlm_u_tlm_rx_fc_src_fc_sched_np_o_5; + wire com_tlm_u_tlm_rx_fc_src_np_pending_5290; + wire com_tlm_u_tlm_rx_fc_src_fc_sched_p_o_5; + wire com_tlm_u_tlm_rx_fc_src_p_pending_5291; + wire com_tlm_u_tlm_rx_fc_src_N_43438_i; + wire com_tlm_u_tlm_rx_fc_src_N_43440_i; + wire com_tlm_u_tlm_rx_fc_src_np_pending_6; + wire com_tlm_u_tlm_rx_fc_src_lnk_tfc_data_o_0_sqmuxa; + wire com_tlm_u_tlm_rx_fc_src_p_vld_5292; + wire com_tlm_u_tlm_rx_fc_src_N_16034_i; + wire com_tlm_u_tlm_rx_fc_src_init2_seq_det_5293; + wire com_tlm_u_tlm_rx_fc_src_lnk_tfc_data_o_11_3_a2_i_0_0_11_39416_5294; + wire com_tlm_u_tlm_rx_fc_src_N_59146; + wire com_tlm_u_tlm_rx_fc_src_lnk_tfc_data_o_11_3_a2_i_0_0_10_39403_5295; + wire com_tlm_u_tlm_rx_fc_src_N_59143; + wire com_tlm_u_tlm_rx_fc_src_lnk_tfc_data_o_11_i_0_0_0_9_39398_5296; + wire com_tlm_u_tlm_rx_fc_src_N_58761; + wire com_tlm_u_tlm_rx_fc_src_lnk_tfc_data_o_11_i_0_0_0_8_39399_5297; + wire com_tlm_u_tlm_rx_fc_src_N_58758; + wire com_tlm_u_tlm_rx_fc_src_lnk_tfc_data_o_11_i_0_0_0_7_39400_5298; + wire com_tlm_u_tlm_rx_fc_src_N_58755; + wire com_tlm_u_tlm_rx_fc_src_lnk_tfc_data_o_11_i_0_0_0_6_39401_5299; + wire com_tlm_u_tlm_rx_fc_src_N_58752; + wire com_tlm_u_tlm_rx_fc_src_lnk_tfc_data_o_11_i_0_0_0_5_39402_5300; + wire com_tlm_u_tlm_rx_fc_src_N_58749; + wire com_tlm_u_tlm_rx_fc_src_lnk_tfc_data_o_11_3_a2_i_0_0_4_39404_5301; + wire com_tlm_u_tlm_rx_fc_src_N_59140; + wire com_tlm_u_tlm_rx_fc_src_lnk_tfc_data_o_11_3_a2_i_0_0_3_39405_5302; + wire com_tlm_u_tlm_rx_fc_src_N_59137; + wire com_tlm_u_tlm_rx_fc_src_lnk_tfc_data_o_11_3_a2_i_0_0_2_39406_5303; + wire com_tlm_u_tlm_rx_fc_src_N_59134; + wire com_tlm_u_tlm_rx_fc_src_lnk_tfc_data_o_11_3_a2_i_0_0_1_39407_5304; + wire com_tlm_u_tlm_rx_fc_src_N_59131; + wire com_tlm_u_tlm_rx_fc_src_lnk_tfc_data_o_11_3_a2_i_0_0_0_39408_5305; + wire com_tlm_u_tlm_rx_fc_src_N_59128; + wire com_tlm_u_tlm_rx_fc_src_lnk_tfc_header_o_11_i_0_0_0_7_39397_5306; + wire com_tlm_u_tlm_rx_fc_src_N_58764; + wire com_tlm_u_tlm_rx_fc_src_lnk_tfc_header_o_11_3_a2_i_0_0_6_39409_5307; + wire com_tlm_u_tlm_rx_fc_src_N_59167; + wire com_tlm_u_tlm_rx_fc_src_lnk_tfc_header_o_11_3_a2_i_0_0_5_39410_5308; + wire com_tlm_u_tlm_rx_fc_src_N_59164; + wire com_tlm_u_tlm_rx_fc_src_lnk_tfc_header_o_11_3_a2_i_0_0_4_39411_5309; + wire com_tlm_u_tlm_rx_fc_src_N_59161; + wire com_tlm_u_tlm_rx_fc_src_lnk_tfc_header_o_11_3_a2_i_0_0_3_39412_5310; + wire com_tlm_u_tlm_rx_fc_src_N_59158; + wire com_tlm_u_tlm_rx_fc_src_lnk_tfc_header_o_11_3_a2_i_0_0_2_39413_5311; + wire com_tlm_u_tlm_rx_fc_src_N_59155; + wire com_tlm_u_tlm_rx_fc_src_lnk_tfc_header_o_11_3_a2_i_0_0_1_39414_5312; + wire com_tlm_u_tlm_rx_fc_src_N_59152; + wire com_tlm_u_tlm_rx_fc_src_lnk_tfc_header_o_11_3_a2_i_0_0_0_39415_5313; + wire com_tlm_u_tlm_rx_fc_src_N_59149; + wire com_tlm_u_tlm_rx_fc_src_N_55891_i; + wire com_tlm_u_tlm_rx_fc_src_N_21949_i; + wire com_tlm_u_tlm_rx_fc_src_np_vld_5314; + wire com_tlm_u_tlm_rx_fc_src_N_56329_i; + wire com_tlm_u_tlm_rx_fc_src_N_56217_i; + wire com_tlm_u_tlm_rx_fc_src_N_30262_i; + wire com_tlm_u_tlm_rx_fc_src_N_30260_i; + wire com_tlm_u_tlm_rx_fc_src_N_20375_i; + wire com_tlm_u_tlm_rx_fc_src_N_20373_i; + wire com_tlm_u_tlm_rx_fc_src_N_20371_i; + wire com_tlm_u_tlm_rx_fc_src_N_20369_i; + wire com_tlm_u_tlm_rx_fc_src_N_20367_i; + wire com_tlm_u_tlm_rx_fc_src_N_30258_i; + wire com_tlm_u_tlm_rx_fc_src_N_30256_i; + wire com_tlm_u_tlm_rx_fc_src_N_30254_i; + wire com_tlm_u_tlm_rx_fc_src_N_30252_i; + wire com_tlm_u_tlm_rx_fc_src_N_30250_i; + wire com_tlm_u_tlm_rx_fc_src_N_20386_i; + wire com_tlm_u_tlm_rx_fc_src_N_30276_i; + wire com_tlm_u_tlm_rx_fc_src_N_30274_i; + wire com_tlm_u_tlm_rx_fc_src_N_30272_i; + wire com_tlm_u_tlm_rx_fc_src_N_30270_i; + wire com_tlm_u_tlm_rx_fc_src_N_30268_i; + wire com_tlm_u_tlm_rx_fc_src_N_30266_i; + wire com_tlm_u_tlm_rx_fc_src_N_30264_i; + wire com_tlm_u_tlm_rx_fc_src_un1_initFC_st_2_0_a2_0_a2_0_a2_5315; + wire com_tlm_u_tlm_rx_fc_src_N_55975_i_i_5316; + wire com_tlm_u_tlm_rx_fc_src_N_58788_i_5317; + wire com_tlm_u_tlm_rx_fc_src_N_87527_i_5318; + wire com_cmm_gnt_arbiter; + wire com_cmm_cmm_arb_pend_req_n; + wire com_cmm_gnt_pm; + wire com_cmm_N_56064_i; + wire com_cmm_N_60852_i; + wire com_cmm_gnt_errman; + wire com_cmm_N_56318_i; + wire com_cmm_detectedfatal; + wire com_cmm_detectednonfatal; + wire com_cmm_unsupportedreq; + wire com_cmm_detectedparityerror; + wire com_cmm_masterdataparityerror; + wire com_cmm_receivedmasterabort; + wire com_cmm_receivedtargetabort; + wire com_cmm_pme_sent; + wire com_cmm_signaledsystemerror; + wire com_cmm_signaledtargetabort; + wire com_cmm_detectedcorrectable; + wire com_cmm_N_56058_i; + wire com_cmm_N_56057_i; + wire com_cmm_N_56056_i; + wire com_cmm_xrom_reg_11_; + wire com_cmm_xrom_reg_29_; + wire com_cmm_xrom_reg_15_; + wire com_cmm_xrom_reg_17_; + wire com_cmm_xrom_reg_21_; + wire com_cmm_xrom_reg_27_; + wire com_cmm_xrom_reg_23_; + wire com_cmm_xrom_reg_25_; + wire com_cmm_xrom_reg_13_; + wire com_cmm_xrom_reg_19_; + wire com_cmm_xrom_reg_31_; + wire com_cmm_xrom_reg_0_; + wire com_cmm_xrom_reg_12_; + wire com_cmm_xrom_reg_30_; + wire com_cmm_xrom_reg_16_; + wire com_cmm_xrom_reg_18_; + wire com_cmm_xrom_reg_22_; + wire com_cmm_xrom_reg_28_; + wire com_cmm_xrom_reg_24_; + wire com_cmm_xrom_reg_26_; + wire com_cmm_xrom_reg_14_; + wire com_cmm_xrom_reg_20_; + wire com_cmm_bar0_reg_4_; + wire com_cmm_bar0_reg_22_; + wire com_cmm_bar0_reg_10_; + wire com_cmm_bar0_reg_12_; + wire com_cmm_bar0_reg_24_; + wire com_cmm_bar0_reg_14_; + wire com_cmm_bar0_reg_18_; + wire com_cmm_bar0_reg_20_; + wire com_cmm_bar0_reg_16_; + wire com_cmm_bar0_reg_6_; + wire com_cmm_bar0_reg_26_; + wire com_cmm_bar0_reg_28_; + wire com_cmm_bar0_reg_8_; + wire com_cmm_bar0_reg_30_; + wire com_cmm_bar0_reg_0_; + wire com_cmm_bar0_reg_1_; + wire com_cmm_bar0_reg_2_; + wire com_cmm_bar0_reg_5_; + wire com_cmm_bar0_reg_31_; + wire com_cmm_bar0_reg_23_; + wire com_cmm_bar0_reg_11_; + wire com_cmm_bar0_reg_13_; + wire com_cmm_bar0_reg_25_; + wire com_cmm_bar0_reg_15_; + wire com_cmm_bar0_reg_19_; + wire com_cmm_bar0_reg_21_; + wire com_cmm_bar0_reg_17_; + wire com_cmm_bar0_reg_7_; + wire com_cmm_bar0_reg_27_; + wire com_cmm_bar0_reg_29_; + wire com_cmm_bar0_reg_9_; + wire com_cmm_N_33410_i_0; + wire com_cmm_N_33408_i_0; + wire com_cmm_tlm2cfg_wrdata_16_; + wire com_cmm_tlm2cfg_wrdata_4_; + wire com_cmm_tlm2cfg_wrdata_3_; + wire com_cmm_tlm2cfg_wrdata_2_; + wire com_cmm_tlm2cfg_wrdata_7_; + wire com_cmm_tlm2cfg_wrdata_6_; + wire com_cmm_tlm2cfg_wrdata_5_; + wire com_cmm_gnt_pkt_tx; + wire com_cmm_req_pkt_tx; + wire com_cmm_tlp_data_64_; + wire com_cmm_tlp_data_65_; + wire com_cmm_tlp_data_66_; + wire com_cmm_tlp_data_67_; + wire com_cmm_tlp_data_68_; + wire com_cmm_tlp_data_69_; + wire com_cmm_tlp_data_70_; + wire com_cmm_tlp_data_71_; + wire com_cmm_tlp_data_72_; + wire com_cmm_tlp_data_73_; + wire com_cmm_tlp_data_74_; + wire com_cmm_tlp_data_75_; + wire com_cmm_tlp_data_76_; + wire com_cmm_tlp_data_77_; + wire com_cmm_tlp_data_78_; + wire com_cmm_tlp_data_79_; + wire com_cmm_tlp_data_80_; + wire com_cmm_tlp_data_81_; + wire com_cmm_tlp_data_82_; + wire com_cmm_tlp_data_83_; + wire com_cmm_tlp_data_84_; + wire com_cmm_tlp_data_85_; + wire com_cmm_tlp_data_86_; + wire com_cmm_tlp_data_87_; + wire com_cmm_tlp_data_88_; + wire com_cmm_tlp_data_89_; + wire com_cmm_tlp_data_90_; + wire com_cmm_tlp_data_91_; + wire com_cmm_tlp_data_92_; + wire com_cmm_tlp_data_93_; + wire com_cmm_tlp_data_94_; + wire com_cmm_tlp_data_95_; + wire com_cmm_tlp_data_96_; + wire com_cmm_tlp_data_97_; + wire com_cmm_tlp_data_98_; + wire com_cmm_tlp_data_99_; + wire com_cmm_tlp_data_100_; + wire com_cmm_tlp_data_101_; + wire com_cmm_tlp_data_102_; + wire com_cmm_tlp_data_103_; + wire com_cmm_tlp_data_104_; + wire com_cmm_tlp_data_105_; + wire com_cmm_tlp_data_106_; + wire com_cmm_tlp_data_107_; + wire com_cmm_tlp_data_108_; + wire com_cmm_tlp_data_109_; + wire com_cmm_tlp_data_110_; + wire com_cmm_tlp_data_111_; + wire com_cmm_tlp_data_112_; + wire com_cmm_tlp_data_113_; + wire com_cmm_tlp_data_114_; + wire com_cmm_tlp_data_115_; + wire com_cmm_tlp_data_116_; + wire com_cmm_tlp_data_117_; + wire com_cmm_tlp_data_118_; + wire com_cmm_tlp_data_119_; + wire com_cmm_tlp_data_120_; + wire com_cmm_tlp_data_121_; + wire com_cmm_tlp_data_122_; + wire com_cmm_tlp_data_123_; + wire com_cmm_tlp_data_124_; + wire com_cmm_tlp_data_125_; + wire com_cmm_tlp_data_126_; + wire com_cmm_tlp_data_127_; + wire com_cmm_tlp_data_28_; + wire com_cmm_tlp_data_26_; + wire com_cmm_tlp_data_24_; + wire com_cmm_tlp_data_22_; + wire com_cmm_tlp_data_32_; + wire com_cmm_tlp_data_37_; + wire com_cmm_tlp_data_36_; + wire com_cmm_tlp_data_35_; + wire com_cmm_tlp_data_34_; + wire com_cmm_tlp_data_33_; + wire com_cmm_tlp_data_42_; + wire com_cmm_tlp_data_41_; + wire com_cmm_tlp_data_40_; + wire com_cmm_tlp_data_39_; + wire com_cmm_tlp_data_38_; + wire com_cmm_tlp_data_52_; + wire com_cmm_tlp_data_51_; + wire com_cmm_tlp_data_47_; + wire com_cmm_tlp_data_45_; + wire com_cmm_tlp_data_43_; + wire com_cmm_tlp_data_57_; + wire com_cmm_tlp_data_56_; + wire com_cmm_tlp_data_55_; + wire com_cmm_tlp_data_54_; + wire com_cmm_tlp_data_53_; + wire com_cmm_tlp_data_62_; + wire com_cmm_tlp_data_61_; + wire com_cmm_tlp_data_60_; + wire com_cmm_tlp_data_59_; + wire com_cmm_tlp_data_58_; + wire com_cmm_tlp_data_21_; + wire com_cmm_tlp_data_20_; + wire com_cmm_tlp_data_13_; + wire com_cmm_tlp_data_12_; + wire com_cmm_tlp_data_63_; + wire com_cmm_req_valid; + wire com_cmm_req_cfgctrl; + wire com_cmm_gnt_cfgctrl; + wire com_cmm_cfg_rd; + wire com_cmm_cfg_wr; + wire com_cmm_N_56090_i; + wire com_cmm_posnd_wr_pack; + wire com_cmm_N_55868_i; + wire com_cmm_type1_type0_bar; + wire com_cmm_bdf_err_rd_pack; + wire com_cmm_gnt_intr; + wire com_cmm_VCC_5319; + wire com_cmm_GND_5320; + wire com_cmm_req_intr; + wire com_cmm_signaledint; + wire com_cmm_rst_i_5321; + wire com_cmm_cfg_intr_rdy; + wire com_cmm_u_cmm_intr_un5_msi_64_0_5322; + wire com_cmm_u_cmm_intr_un5_msi_64_1_5323; + wire com_cmm_u_cmm_intr_un5_msi_64_2_5324; + wire com_cmm_u_cmm_intr_un5_msi_64_3_5325; + wire com_cmm_u_cmm_intr_un5_msi_64_4_5326; + wire com_cmm_u_cmm_intr_un5_msi_64_5_5327; + wire com_cmm_u_cmm_intr_un5_msi_64_6_5328; + wire com_cmm_u_cmm_intr_N_124_1; + wire com_cmm_u_cmm_intr_N_114_i; + wire com_cmm_u_cmm_intr_un5_msi_64_7_5329; + wire com_cmm_u_cmm_intr_N_239_i_5330; + wire com_cmm_u_cmm_intr_N_238_i_5331; + wire com_cmm_u_cmm_intr_N_237_i_5332; + wire com_cmm_u_cmm_intr_N_240_i_5333; + wire com_cmm_u_cmm_intr_intr_req_5334; + wire com_cmm_u_cmm_intr_intr_req_q_5335; + wire com_cmm_u_cmm_intr_un5_msi_64_7_and_5336; + wire com_cmm_u_cmm_intr_un5_msi_64_6_and_5337; + wire com_cmm_u_cmm_intr_un5_msi_64_5_and_5338; + wire com_cmm_u_cmm_intr_un5_msi_64_4_and_5339; + wire com_cmm_u_cmm_intr_un5_msi_64_3_and_5340; + wire com_cmm_u_cmm_intr_un5_msi_64_2_and_5341; + wire com_cmm_u_cmm_intr_un5_msi_64_1_and_5342; + wire com_cmm_u_cmm_intr_un5_msi_64_0_and_5343; + wire com_cmm_u_cmm_intr_GND_5344; + wire com_cmm_u_cmm_intr_VCC_5345; + wire com_cmm_u_rx_pkt_proc_idle_enable; + wire com_cmm_u_rx_pkt_proc_N_19513_i; + wire com_cmm_u_rx_pkt_proc_bdf_err_rd_pack_3_i_0_o3_0_0_5346; + wire com_cmm_u_rx_pkt_proc_un1_dw1_enable_2_0_a2_0_a2_0_a2_5347; + wire com_cmm_u_rx_pkt_proc_bdf_err_rd_pack_3_i_0_2_5348; + wire com_cmm_u_rx_pkt_proc_bdf_err_rd_pack_3_i_o4_5349; + wire com_cmm_u_rx_pkt_proc_ecrc_5350; + wire com_cmm_u_rx_pkt_proc_cfg_rd_3; + wire com_cmm_u_rx_pkt_proc_type1_type0_bar_3; + wire com_cmm_u_rx_pkt_proc_N_60331_5; + wire com_cmm_u_rx_pkt_proc_N_58687; + wire com_cmm_u_rx_pkt_proc_N_85914_i_5351; + wire com_cmm_u_rx_pkt_proc_posnd_wr_pack_6_0_i_i_0_5352; + wire com_cmm_u_rx_pkt_proc_cfg_wr_3; + wire com_cmm_u_rx_pkt_proc_N_85975_i_5353; + wire com_cmm_u_rx_pkt_proc_bdf_err_rd_pack_3_i_0_3_5354; + wire com_cmm_u_rx_pkt_proc_N_59558; + wire com_cmm_u_rx_pkt_proc_N_56198_i; + wire com_cmm_u_rx_pkt_proc_N_58688; + wire com_cmm_u_rx_pkt_proc_N_85817_i_5355; + wire com_cmm_u_rx_pkt_proc_next_state_0_sqmuxa_3; + wire com_cmm_u_rx_pkt_proc_N_43405_i; + wire com_cmm_u_rx_pkt_proc_dw1_enable; + wire com_cmm_u_rx_pkt_proc_N_19515_i; + wire com_cmm_u_rx_pkt_proc_N_86814_i_5356; + wire com_cmm_u_tx_pkt_proc_TLP_data_reg_63__5357; + wire com_cmm_u_tx_pkt_proc_TLP_data_reg_12__5358; + wire com_cmm_u_tx_pkt_proc_TLP_data_reg_13__5359; + wire com_cmm_u_tx_pkt_proc_TLP_data_reg_20__5360; + wire com_cmm_u_tx_pkt_proc_TLP_data_reg_21__5361; + wire com_cmm_u_tx_pkt_proc_TLP_data_reg_58__5362; + wire com_cmm_u_tx_pkt_proc_TLP_data_reg_59__5363; + wire com_cmm_u_tx_pkt_proc_TLP_data_reg_60__5364; + wire com_cmm_u_tx_pkt_proc_TLP_data_reg_61__5365; + wire com_cmm_u_tx_pkt_proc_TLP_data_reg_62__5366; + wire com_cmm_u_tx_pkt_proc_TLP_data_reg_53__5367; + wire com_cmm_u_tx_pkt_proc_TLP_data_reg_54__5368; + wire com_cmm_u_tx_pkt_proc_TLP_data_reg_55__5369; + wire com_cmm_u_tx_pkt_proc_TLP_data_reg_56__5370; + wire com_cmm_u_tx_pkt_proc_TLP_data_reg_57__5371; + wire com_cmm_u_tx_pkt_proc_TLP_data_reg_43__5372; + wire com_cmm_u_tx_pkt_proc_TLP_data_reg_45__5373; + wire com_cmm_u_tx_pkt_proc_TLP_data_reg_47__5374; + wire com_cmm_u_tx_pkt_proc_TLP_data_reg_51__5375; + wire com_cmm_u_tx_pkt_proc_TLP_data_reg_52__5376; + wire com_cmm_u_tx_pkt_proc_TLP_data_reg_38__5377; + wire com_cmm_u_tx_pkt_proc_TLP_data_reg_39__5378; + wire com_cmm_u_tx_pkt_proc_TLP_data_reg_40__5379; + wire com_cmm_u_tx_pkt_proc_TLP_data_reg_41__5380; + wire com_cmm_u_tx_pkt_proc_TLP_data_reg_42__5381; + wire com_cmm_u_tx_pkt_proc_TLP_data_reg_33__5382; + wire com_cmm_u_tx_pkt_proc_TLP_data_reg_34__5383; + wire com_cmm_u_tx_pkt_proc_TLP_data_reg_35__5384; + wire com_cmm_u_tx_pkt_proc_TLP_data_reg_36__5385; + wire com_cmm_u_tx_pkt_proc_TLP_data_reg_37__5386; + wire com_cmm_u_tx_pkt_proc_TLP_data_reg_32__5387; + wire com_cmm_u_tx_pkt_proc_TLP_data_reg_22__5388; + wire com_cmm_u_tx_pkt_proc_TLP_data_reg_24__5389; + wire com_cmm_u_tx_pkt_proc_TLP_data_reg_26__5390; + wire com_cmm_u_tx_pkt_proc_TLP_data_reg_28__5391; + wire com_cmm_u_tx_pkt_proc_N_60502_i_5392; + wire com_cmm_u_tx_pkt_proc_N_60436; + wire com_cmm_u_tx_pkt_proc_TLP_data_reg_10_63_; + wire com_cmm_u_tx_pkt_proc_TLP_data_reg_10_62_; + wire com_cmm_u_tx_pkt_proc_TLP_data_reg_10_61_; + wire com_cmm_u_tx_pkt_proc_TLP_data_reg_10_60_; + wire com_cmm_u_tx_pkt_proc_TLP_data_reg_10_59_; + wire com_cmm_u_tx_pkt_proc_TLP_data_reg_10_58_; + wire com_cmm_u_tx_pkt_proc_TLP_data_reg_10_57_; + wire com_cmm_u_tx_pkt_proc_TLP_data_reg_10_56_; + wire com_cmm_u_tx_pkt_proc_TLP_data_reg_10_55_; + wire com_cmm_u_tx_pkt_proc_TLP_data_reg_10_54_; + wire com_cmm_u_tx_pkt_proc_TLP_data_reg_10_53_; + wire com_cmm_u_tx_pkt_proc_TLP_data_reg_10_52_; + wire com_cmm_u_tx_pkt_proc_TLP_data_reg_10_51_; + wire com_cmm_u_tx_pkt_proc_TLP_data_reg_10_50_; + wire com_cmm_u_tx_pkt_proc_TLP_data_reg_10_49_; + wire com_cmm_u_tx_pkt_proc_TLP_data_reg_10_48_; + wire com_cmm_u_tx_pkt_proc_TLP_data_reg_10_47_; + wire com_cmm_u_tx_pkt_proc_TLP_data_reg_10_46_; + wire com_cmm_u_tx_pkt_proc_TLP_data_reg_10_45_; + wire com_cmm_u_tx_pkt_proc_TLP_data_reg_10_44_; + wire com_cmm_u_tx_pkt_proc_TLP_data_reg_10_43_; + wire com_cmm_u_tx_pkt_proc_TLP_data_reg_10_42_; + wire com_cmm_u_tx_pkt_proc_TLP_data_reg_10_41_; + wire com_cmm_u_tx_pkt_proc_TLP_data_reg_10_40_; + wire com_cmm_u_tx_pkt_proc_TLP_data_reg_10_39_; + wire com_cmm_u_tx_pkt_proc_TLP_data_reg_10_38_; + wire com_cmm_u_tx_pkt_proc_TLP_data_reg_10_37_; + wire com_cmm_u_tx_pkt_proc_TLP_data_reg_10_36_; + wire com_cmm_u_tx_pkt_proc_TLP_data_reg_10_35_; + wire com_cmm_u_tx_pkt_proc_TLP_data_reg_10_34_; + wire com_cmm_u_tx_pkt_proc_TLP_data_reg_10_33_; + wire com_cmm_u_tx_pkt_proc_TLP_data_reg_10_32_; + wire com_cmm_u_tx_pkt_proc_N_43037_i; + wire com_cmm_u_tx_pkt_proc_N_43035_i; + wire com_cmm_u_tx_pkt_proc_N_43033_i; + wire com_cmm_u_tx_pkt_proc_N_43031_i; + wire com_cmm_u_tx_pkt_proc_N_43029_i; + wire com_cmm_u_tx_pkt_proc_N_43027_i; + wire com_cmm_u_tx_pkt_proc_N_43025_i; + wire com_cmm_u_tx_pkt_proc_N_43023_i; + wire com_cmm_u_tx_pkt_proc_N_43021_i; + wire com_cmm_u_tx_pkt_proc_N_43019_i; + wire com_cmm_u_tx_pkt_proc_N_43017_i; + wire com_cmm_u_tx_pkt_proc_N_43015_i; + wire com_cmm_u_tx_pkt_proc_N_43013_i; + wire com_cmm_u_tx_pkt_proc_N_43011_i; + wire com_cmm_u_tx_pkt_proc_N_43009_i; + wire com_cmm_u_tx_pkt_proc_N_43007_i; + wire com_cmm_u_tx_pkt_proc_N_55927_i; + wire com_cmm_u_tx_pkt_proc_TLP_data_reg_10_15_; + wire com_cmm_u_tx_pkt_proc_TLP_data_reg_10_14_; + wire com_cmm_u_tx_pkt_proc_TLP_data_reg_10_13_; + wire com_cmm_u_tx_pkt_proc_TLP_data_reg_10_12_; + wire com_cmm_u_tx_pkt_proc_TLP_data_reg_10_11_; + wire com_cmm_u_tx_pkt_proc_TLP_data_reg_10_10_; + wire com_cmm_u_tx_pkt_proc_TLP_data_reg_10_9_; + wire com_cmm_u_tx_pkt_proc_TLP_data_reg_10_8_; + wire com_cmm_u_tx_pkt_proc_TLP_data_reg_10_7_; + wire com_cmm_u_tx_pkt_proc_TLP_data_reg_10_6_; + wire com_cmm_u_tx_pkt_proc_TLP_data_reg_10_5_; + wire com_cmm_u_tx_pkt_proc_TLP_data_reg_10_4_; + wire com_cmm_u_tx_pkt_proc_TLP_data_reg_10_3_; + wire com_cmm_u_tx_pkt_proc_TLP_data_reg_10_2_; + wire com_cmm_u_tx_pkt_proc_TLP_data_reg_10_1_; + wire com_cmm_u_tx_pkt_proc_TLP_data_reg_10_0_; + wire com_cmm_u_tx_pkt_proc_N_86366_i_5393; + wire com_cmm_u_tx_pkt_proc_N_85919_i_5394; + wire com_cmm_u_tx_pkt_proc_N_9934_i; + wire com_cmm_u_tx_pkt_proc_N_42769_i; + wire com_cmm_u_cfg_ctrl_N_58693; + wire com_cmm_u_cfg_ctrl_N_58695; + wire com_cmm_u_cfg_ctrl_N_85814_i_5395; + wire com_cmm_u_cfg_ctrl_N_86813_i_5396; + wire com_cmm_u_cfg_ctrl_N_86780_i_5397; + wire com_cmm_u_cfg_ctrl_next_state_0_sqmuxa_i_i_5398; + wire com_cmm_u_cfg_ctrl_next_state_0_sqmuxa_i; + wire com_cmm_u_cmm_decoder_un11_bar34_64_hit_low_0_5399; + wire com_cmm_u_cmm_decoder_un11_bar34_64_hit_low_1_5400; + wire com_cmm_u_cmm_decoder_un11_bar34_64_hit_low_2_5401; + wire com_cmm_u_cmm_decoder_un11_bar34_64_hit_low_3_5402; + wire com_cmm_u_cmm_decoder_un11_bar34_64_hit_low_4_5403; + wire com_cmm_u_cmm_decoder_un11_bar34_64_hit_low_5_5404; + wire com_cmm_u_cmm_decoder_un11_bar34_64_hit_low_6_5405; + wire com_cmm_u_cmm_decoder_un11_bar5_32_hit_nc_0_5406; + wire com_cmm_u_cmm_decoder_un11_bar5_32_hit_nc_1_5407; + wire com_cmm_u_cmm_decoder_un11_bar5_32_hit_nc_2_5408; + wire com_cmm_u_cmm_decoder_un11_bar5_32_hit_nc_3_5409; + wire com_cmm_u_cmm_decoder_un11_bar5_32_hit_nc_4_5410; + wire com_cmm_u_cmm_decoder_un11_bar5_32_hit_nc_5_5411; + wire com_cmm_u_cmm_decoder_un11_bar5_32_hit_nc_6_5412; + wire com_cmm_u_cmm_decoder_un11_bar4_32_hit_nc_0_5413; + wire com_cmm_u_cmm_decoder_un11_bar4_32_hit_nc_1_5414; + wire com_cmm_u_cmm_decoder_un11_bar4_32_hit_nc_2_5415; + wire com_cmm_u_cmm_decoder_un11_bar4_32_hit_nc_3_5416; + wire com_cmm_u_cmm_decoder_un11_bar4_32_hit_nc_4_5417; + wire com_cmm_u_cmm_decoder_un11_bar4_32_hit_nc_5_5418; + wire com_cmm_u_cmm_decoder_un11_bar4_32_hit_nc_6_5419; + wire com_cmm_u_cmm_decoder_un11_bar4_32_hit_nc_7_5420; + wire com_cmm_u_cmm_decoder_un11_bar3_32_hit_nc_0_5421; + wire com_cmm_u_cmm_decoder_un11_bar3_32_hit_nc_1_5422; + wire com_cmm_u_cmm_decoder_un11_bar3_32_hit_nc_2_5423; + wire com_cmm_u_cmm_decoder_un11_bar3_32_hit_nc_3_5424; + wire com_cmm_u_cmm_decoder_un11_bar3_32_hit_nc_4_5425; + wire com_cmm_u_cmm_decoder_un11_bar3_32_hit_nc_5_5426; + wire com_cmm_u_cmm_decoder_un11_bar3_32_hit_nc_6_5427; + wire com_cmm_u_cmm_decoder_un11_bar2_32_hit_nc_0_5428; + wire com_cmm_u_cmm_decoder_un11_bar2_32_hit_nc_1_5429; + wire com_cmm_u_cmm_decoder_un11_bar2_32_hit_nc_2_5430; + wire com_cmm_u_cmm_decoder_un11_bar2_32_hit_nc_3_5431; + wire com_cmm_u_cmm_decoder_un11_bar2_32_hit_nc_4_5432; + wire com_cmm_u_cmm_decoder_un11_bar2_32_hit_nc_5_5433; + wire com_cmm_u_cmm_decoder_un11_bar2_32_hit_nc_6_5434; + wire com_cmm_u_cmm_decoder_un11_bar1_32_hit_nc_0_5435; + wire com_cmm_u_cmm_decoder_un11_bar1_32_hit_nc_1_5436; + wire com_cmm_u_cmm_decoder_un11_bar1_32_hit_nc_2_5437; + wire com_cmm_u_cmm_decoder_un11_bar1_32_hit_nc_3_5438; + wire com_cmm_u_cmm_decoder_un11_bar1_32_hit_nc_4_5439; + wire com_cmm_u_cmm_decoder_un11_bar1_32_hit_nc_5_5440; + wire com_cmm_u_cmm_decoder_un11_bar1_32_hit_nc_6_5441; + wire com_cmm_u_cmm_decoder_un18_bar4_32_hit_nc_0_5442; + wire com_cmm_u_cmm_decoder_un18_bar4_32_hit_nc_1_5443; + wire com_cmm_u_cmm_decoder_un18_bar4_32_hit_nc_2_5444; + wire com_cmm_u_cmm_decoder_un18_bar4_32_hit_nc_3_5445; + wire com_cmm_u_cmm_decoder_un18_bar4_32_hit_nc_4_5446; + wire com_cmm_u_cmm_decoder_un18_bar4_32_hit_nc_5_5447; + wire com_cmm_u_cmm_decoder_un18_bar4_32_hit_nc_6_5448; + wire com_cmm_u_cmm_decoder_un18_bar3_32_hit_nc_0_5449; + wire com_cmm_u_cmm_decoder_un18_bar3_32_hit_nc_1_5450; + wire com_cmm_u_cmm_decoder_un18_bar3_32_hit_nc_2_5451; + wire com_cmm_u_cmm_decoder_un18_bar3_32_hit_nc_3_5452; + wire com_cmm_u_cmm_decoder_un18_bar3_32_hit_nc_4_5453; + wire com_cmm_u_cmm_decoder_un18_bar3_32_hit_nc_5_5454; + wire com_cmm_u_cmm_decoder_un18_bar3_32_hit_nc_6_5455; + wire com_cmm_u_cmm_decoder_un18_bar2_32_hit_nc_0_5456; + wire com_cmm_u_cmm_decoder_un18_bar2_32_hit_nc_1_5457; + wire com_cmm_u_cmm_decoder_un18_bar2_32_hit_nc_2_5458; + wire com_cmm_u_cmm_decoder_un18_bar2_32_hit_nc_3_5459; + wire com_cmm_u_cmm_decoder_un18_bar2_32_hit_nc_4_5460; + wire com_cmm_u_cmm_decoder_un18_bar2_32_hit_nc_5_5461; + wire com_cmm_u_cmm_decoder_un18_bar2_32_hit_nc_6_5462; + wire com_cmm_u_cmm_decoder_un18_bar1_32_hit_nc_0_5463; + wire com_cmm_u_cmm_decoder_un18_bar1_32_hit_nc_1_5464; + wire com_cmm_u_cmm_decoder_un18_bar1_32_hit_nc_2_5465; + wire com_cmm_u_cmm_decoder_un18_bar1_32_hit_nc_3_5466; + wire com_cmm_u_cmm_decoder_un18_bar1_32_hit_nc_4_5467; + wire com_cmm_u_cmm_decoder_un18_bar1_32_hit_nc_5_5468; + wire com_cmm_u_cmm_decoder_un18_bar1_32_hit_nc_6_5469; + wire com_cmm_u_cmm_decoder_un18_bar0_32_hit_nc_0_5470; + wire com_cmm_u_cmm_decoder_un18_bar0_32_hit_nc_1_5471; + wire com_cmm_u_cmm_decoder_un18_bar0_32_hit_nc_2_5472; + wire com_cmm_u_cmm_decoder_un18_bar0_32_hit_nc_3_5473; + wire com_cmm_u_cmm_decoder_un18_bar0_32_hit_nc_4_5474; + wire com_cmm_u_cmm_decoder_un18_bar0_32_hit_nc_5_5475; + wire com_cmm_u_cmm_decoder_un18_bar0_32_hit_nc_6_5476; + wire com_cmm_u_cmm_decoder_un11_bar0_32_hit_nc_0_5477; + wire com_cmm_u_cmm_decoder_un11_bar0_32_hit_nc_1_5478; + wire com_cmm_u_cmm_decoder_un11_bar0_32_hit_nc_2_5479; + wire com_cmm_u_cmm_decoder_un11_bar0_32_hit_nc_3_5480; + wire com_cmm_u_cmm_decoder_un11_bar0_32_hit_nc_4_5481; + wire com_cmm_u_cmm_decoder_un11_bar0_32_hit_nc_5_5482; + wire com_cmm_u_cmm_decoder_un11_bar0_32_hit_nc_6_5483; + wire com_cmm_u_cmm_decoder_VCC_5484; + wire com_cmm_u_cmm_decoder_un7_bar6_32_hit_nc_0_5485; + wire com_cmm_u_cmm_decoder_un7_bar6_32_hit_nc_1_5486; + wire com_cmm_u_cmm_decoder_un7_bar6_32_hit_nc_2_5487; + wire com_cmm_u_cmm_decoder_un7_bar6_32_hit_nc_3_5488; + wire com_cmm_u_cmm_decoder_un7_bar6_32_hit_nc_4_5489; + wire com_cmm_u_cmm_decoder_un7_bar6_32_hit_nc_5_5490; + wire com_cmm_u_cmm_decoder_N_54_9; + wire com_cmm_u_cmm_decoder_N_38_9; + wire com_cmm_u_cmm_decoder_N_6_9; + wire com_cmm_u_cmm_decoder_N_14_10; + wire com_cmm_u_cmm_decoder_N_22_9; + wire com_cmm_u_cmm_decoder_N_30_9; + wire com_cmm_u_cmm_decoder_N_46_9; + wire com_cmm_u_cmm_decoder_N_62_9; + wire com_cmm_u_cmm_decoder_N_70_9; + wire com_cmm_u_cmm_decoder_N_78_8; + wire com_cmm_u_cmm_decoder_N_86_8; + wire com_cmm_u_cmm_decoder_N_94_9; + wire com_cmm_u_cmm_decoder_N_102_14; + wire com_cmm_u_cmm_decoder_N_107_13; + wire com_cmm_u_cmm_decoder_N_110_7; + wire com_cmm_u_cmm_decoder_bar4_32_hit_nc_3_i_0_0_0_0_5491; + wire com_cmm_u_cmm_decoder_bar5_32_hit_nc_3_i_0_0_0_o3_0_5492; + wire com_cmm_u_cmm_decoder_N_56989; + wire com_cmm_u_cmm_decoder_un7_bar6_32_hit_nc_6_5493; + wire com_cmm_u_cmm_decoder_N_56035_i; + wire com_cmm_u_cmm_decoder_N_56986; + wire com_cmm_u_cmm_decoder_N_56113_i; + wire com_cmm_u_cmm_decoder_un18_bar2_32_hit_nc_7_5494; + wire com_cmm_u_cmm_decoder_bar2_32_hit_nc_3_i_0_0_0_1_5495; + wire com_cmm_u_cmm_decoder_N_58557; + wire com_cmm_u_cmm_decoder_un18_bar1_32_hit_nc_7_5496; + wire com_cmm_u_cmm_decoder_bar1_32_hit_nc_3_i_0_0_0_1_5497; + wire com_cmm_u_cmm_decoder_un11_bar5_32_hit_nc_7_5498; + wire com_cmm_u_cmm_decoder_un11_bar34_64_hit_low_7_5499; + wire com_cmm_u_cmm_decoder_un11_bar3_32_hit_nc_7_5500; + wire com_cmm_u_cmm_decoder_un11_bar2_32_hit_nc_7_5501; + wire com_cmm_u_cmm_decoder_un11_bar1_32_hit_nc_7_5502; + wire com_cmm_u_cmm_decoder_bar45_64_hit_low_3_0_a2_0_a2_0_a2_0_a2_0; + wire com_cmm_u_cmm_decoder_un18_bar0_32_hit_nc_7_5503; + wire com_cmm_u_cmm_decoder_un11_bar0_32_hit_nc_7_5504; + wire com_cmm_u_cmm_decoder_bar0_32_hit_nc_3_i_0_0_0_0_5505; + wire com_cmm_u_cmm_decoder_un18_bar4_32_hit_nc_7_5506; + wire com_cmm_u_cmm_decoder_un11_bar4_32_hit_nc_8_5507; + wire com_cmm_u_cmm_decoder_bar4_32_hit_nc_3_i_0_0_0_1_5508; + wire com_cmm_u_cmm_decoder_N_58543; + wire com_cmm_u_cmm_decoder_un18_bar3_32_hit_nc_7_5509; + wire com_cmm_u_cmm_decoder_bar3_32_hit_nc_3_i_0_0_0_2_5510; + wire com_cmm_u_cmm_decoder_bar2_32_hit_nc_3_i_0_0_0_0_5511; + wire com_cmm_u_cmm_decoder_N_58555; + wire com_cmm_u_cmm_decoder_bar1_32_hit_nc_3_i_0_0_0_0_5512; + wire com_cmm_u_cmm_decoder_N_58582; + wire com_cmm_u_cmm_decoder_I_10; + wire com_cmm_u_cmm_decoder_I_10_0; + wire com_cmm_u_cmm_decoder_I_10_1; + wire com_cmm_u_cmm_decoder_I_10_2; + wire com_cmm_u_cmm_decoder_I_10_3; + wire com_cmm_u_cmm_decoder_I_28_5; + wire com_cmm_u_cmm_decoder_I_28_4; + wire com_cmm_u_cmm_decoder_I_28_3; + wire com_cmm_u_cmm_decoder_I_28_2; + wire com_cmm_u_cmm_decoder_I_28_1; + wire com_cmm_u_cmm_decoder_GND_5513; + wire com_cmm_u_cmm_decoder_bar6_eq_raddr_3; + wire com_cmm_u_cmm_decoder_bar6_eq_raddr_5514; + wire com_cmm_u_cmm_decoder_bar5_eq_raddr_3; + wire com_cmm_u_cmm_decoder_bar5_eq_raddr_5515; + wire com_cmm_u_cmm_decoder_bar4_eq_raddr_3; + wire com_cmm_u_cmm_decoder_bar4_eq_raddr_5516; + wire com_cmm_u_cmm_decoder_bar3_eq_raddr_3; + wire com_cmm_u_cmm_decoder_bar3_eq_raddr_5517; + wire com_cmm_u_cmm_decoder_bar2_eq_raddr_3; + wire com_cmm_u_cmm_decoder_bar2_eq_raddr_5518; + wire com_cmm_u_cmm_decoder_bar1_eq_raddr_3; + wire com_cmm_u_cmm_decoder_bar1_eq_raddr_5519; + wire com_cmm_u_cmm_decoder_bar0_eq_raddr_3; + wire com_cmm_u_cmm_decoder_bar0_eq_raddr_5520; + wire com_cmm_u_cmm_decoder_bar45_64_hit_high_3; + wire com_cmm_u_cmm_decoder_bar45_64_hit_high_5521; + wire com_cmm_u_cmm_decoder_bar34_64_hit_high_3; + wire com_cmm_u_cmm_decoder_bar34_64_hit_high_5522; + wire com_cmm_u_cmm_decoder_bar23_64_hit_high_3; + wire com_cmm_u_cmm_decoder_bar23_64_hit_high_5523; + wire com_cmm_u_cmm_decoder_bar12_64_hit_high_3; + wire com_cmm_u_cmm_decoder_bar12_64_hit_high_5524; + wire com_cmm_u_cmm_decoder_bar01_64_hit_high_3; + wire com_cmm_u_cmm_decoder_bar01_64_hit_high_5525; + wire com_cmm_u_cmm_decoder_bar6_32_hit_nc_3; + wire com_cmm_u_cmm_decoder_bar6_32_hit_nc_5526; + wire com_cmm_u_cmm_decoder_N_17867_i; + wire com_cmm_u_cmm_decoder_bar5_32_hit_nc_5527; + wire com_cmm_u_cmm_decoder_N_18225_i; + wire com_cmm_u_cmm_decoder_bar2_32_hit_nc_5528; + wire com_cmm_u_cmm_decoder_N_18403_i; + wire com_cmm_u_cmm_decoder_bar1_32_hit_nc_5529; + wire com_cmm_u_cmm_decoder_bar45_64_hit_low_3; + wire com_cmm_u_cmm_decoder_bar45_64_hit_low_5530; + wire com_cmm_u_cmm_decoder_bar34_64_hit_low_3; + wire com_cmm_u_cmm_decoder_bar34_64_hit_low_5531; + wire com_cmm_u_cmm_decoder_bar23_64_hit_low_3; + wire com_cmm_u_cmm_decoder_bar23_64_hit_low_5532; + wire com_cmm_u_cmm_decoder_bar12_64_hit_low_3; + wire com_cmm_u_cmm_decoder_bar12_64_hit_low_5533; + wire com_cmm_u_cmm_decoder_bar01_64_hit_low_3; + wire com_cmm_u_cmm_decoder_bar01_64_hit_low_5534; + wire com_cmm_u_cmm_decoder_N_18400_i; + wire com_cmm_u_cmm_decoder_bar0_32_hit_nc_5535; + wire com_cmm_u_cmm_decoder_N_18054_i; + wire com_cmm_u_cmm_decoder_bar4_32_hit_nc_5536; + wire com_cmm_u_cmm_decoder_N_18227_i; + wire com_cmm_u_cmm_decoder_bar3_32_hit_nc_5537; + wire com_cmm_u_cmm_decoder_bar6_32_hit_5538; + wire com_cmm_u_cmm_decoder_N_18563_i_5539; + wire com_cmm_u_cmm_decoder_N_18564_i_5540; + wire com_cmm_u_cmm_decoder_N_18565_i_5541; + wire com_cmm_u_cmm_decoder_N_18566_i_5542; + wire com_cmm_u_cmm_decoder_N_18567_i_5543; + wire com_cmm_u_cmm_decoder_N_18568_i_5544; + wire com_cmm_u_cmm_decoder_N_99_14; + wire com_cmm_u_cmm_decoder_N_102_13; + wire com_cmm_u_cmm_decoder_N_99_13; + wire com_cmm_u_cmm_decoder_N_102_12; + wire com_cmm_u_cmm_decoder_N_99_12; + wire com_cmm_u_cmm_decoder_N_102_11; + wire com_cmm_u_cmm_decoder_N_99_11; + wire com_cmm_u_cmm_decoder_N_102_10; + wire com_cmm_u_cmm_decoder_N_99_10; + wire com_cmm_u_cmm_decoder_N_102_9; + wire com_cmm_u_cmm_decoder_I_10_sf; + wire com_cmm_u_cmm_decoder_N_99_9; + wire com_cmm_u_cmm_decoder_N_7_i; + wire com_cmm_u_cmm_decoder_N_99_8; + wire com_cmm_u_cmm_decoder_N_102_8; + wire com_cmm_u_cmm_decoder_N_99_7; + wire com_cmm_u_cmm_decoder_N_102_7; + wire com_cmm_u_cmm_decoder_N_99_6; + wire com_cmm_u_cmm_decoder_N_102_6; + wire com_cmm_u_cmm_decoder_N_99_5; + wire com_cmm_u_cmm_decoder_N_102_5; + wire com_cmm_u_cmm_decoder_N_99_4; + wire com_cmm_u_cmm_decoder_N_102_4; + wire com_cmm_u_cmm_decoder_N_99_3; + wire com_cmm_u_cmm_decoder_N_102_3; + wire com_cmm_u_cmm_decoder_N_99_2; + wire com_cmm_u_cmm_decoder_N_99_1; + wire com_cmm_u_cmm_decoder_N_99_0; + wire com_cmm_u_cmm_decoder_N_99; + wire com_cmm_u_cmm_decoder_un7_bar6_32_hit_nc_5_and; + wire com_cmm_u_cmm_decoder_un7_bar6_32_hit_nc_4_and; + wire com_cmm_u_cmm_decoder_un7_bar6_32_hit_nc_3_and; + wire com_cmm_u_cmm_decoder_un7_bar6_32_hit_nc_2_and; + wire com_cmm_u_cmm_decoder_un7_bar6_32_hit_nc_1_and; + wire com_cmm_u_cmm_decoder_un7_bar6_32_hit_nc_0_and_5545; + wire com_cmm_u_cmm_decoder_un11_bar0_32_hit_nc_7_and; + wire com_cmm_u_cmm_decoder_un11_bar0_32_hit_nc_6_and; + wire com_cmm_u_cmm_decoder_un11_bar0_32_hit_nc_5_and; + wire com_cmm_u_cmm_decoder_un11_bar0_32_hit_nc_4_and; + wire com_cmm_u_cmm_decoder_un11_bar0_32_hit_nc_3_and; + wire com_cmm_u_cmm_decoder_un11_bar0_32_hit_nc_2_and; + wire com_cmm_u_cmm_decoder_un11_bar0_32_hit_nc_1_and; + wire com_cmm_u_cmm_decoder_un11_bar0_32_hit_nc_0_and; + wire com_cmm_u_cmm_decoder_un18_bar0_32_hit_nc_7_and; + wire com_cmm_u_cmm_decoder_un18_bar0_32_hit_nc_6_and; + wire com_cmm_u_cmm_decoder_un18_bar0_32_hit_nc_5_and; + wire com_cmm_u_cmm_decoder_un18_bar0_32_hit_nc_4_and; + wire com_cmm_u_cmm_decoder_un18_bar0_32_hit_nc_3_and; + wire com_cmm_u_cmm_decoder_un18_bar0_32_hit_nc_2_and; + wire com_cmm_u_cmm_decoder_un18_bar0_32_hit_nc_1_and; + wire com_cmm_u_cmm_decoder_un18_bar0_32_hit_nc_0_and; + wire com_cmm_u_cmm_decoder_un18_bar0_32_hit_nc_0_and_1; + wire com_cmm_u_cmm_decoder_un18_bar1_32_hit_nc_7_and; + wire com_cmm_u_cmm_decoder_un18_bar1_32_hit_nc_6_and; + wire com_cmm_u_cmm_decoder_un18_bar1_32_hit_nc_5_and; + wire com_cmm_u_cmm_decoder_un18_bar1_32_hit_nc_4_and; + wire com_cmm_u_cmm_decoder_un18_bar1_32_hit_nc_3_and; + wire com_cmm_u_cmm_decoder_un18_bar1_32_hit_nc_2_and; + wire com_cmm_u_cmm_decoder_un18_bar1_32_hit_nc_1_and; + wire com_cmm_u_cmm_decoder_un18_bar1_32_hit_nc_0_and; + wire com_cmm_u_cmm_decoder_un18_bar1_32_hit_nc_0_and_1; + wire com_cmm_u_cmm_decoder_un18_bar2_32_hit_nc_7_and; + wire com_cmm_u_cmm_decoder_un18_bar2_32_hit_nc_6_and; + wire com_cmm_u_cmm_decoder_un18_bar2_32_hit_nc_5_and; + wire com_cmm_u_cmm_decoder_un18_bar2_32_hit_nc_4_and; + wire com_cmm_u_cmm_decoder_un18_bar2_32_hit_nc_3_and; + wire com_cmm_u_cmm_decoder_un18_bar2_32_hit_nc_2_and; + wire com_cmm_u_cmm_decoder_un18_bar2_32_hit_nc_1_and; + wire com_cmm_u_cmm_decoder_un18_bar2_32_hit_nc_0_and; + wire com_cmm_u_cmm_decoder_bar34_64_hit_high_3_1; + wire com_cmm_u_cmm_decoder_un18_bar3_32_hit_nc_7_and; + wire com_cmm_u_cmm_decoder_un18_bar3_32_hit_nc_6_and; + wire com_cmm_u_cmm_decoder_un18_bar3_32_hit_nc_5_and; + wire com_cmm_u_cmm_decoder_un18_bar3_32_hit_nc_4_and; + wire com_cmm_u_cmm_decoder_un18_bar3_32_hit_nc_3_and; + wire com_cmm_u_cmm_decoder_un18_bar3_32_hit_nc_2_and; + wire com_cmm_u_cmm_decoder_un18_bar3_32_hit_nc_1_and; + wire com_cmm_u_cmm_decoder_un18_bar3_32_hit_nc_0_and; + wire com_cmm_u_cmm_decoder_un18_bar3_32_hit_nc_0_and_1; + wire com_cmm_u_cmm_decoder_un18_bar4_32_hit_nc_7_and; + wire com_cmm_u_cmm_decoder_un18_bar4_32_hit_nc_6_and; + wire com_cmm_u_cmm_decoder_un18_bar4_32_hit_nc_5_and; + wire com_cmm_u_cmm_decoder_un18_bar4_32_hit_nc_4_and; + wire com_cmm_u_cmm_decoder_un18_bar4_32_hit_nc_3_and; + wire com_cmm_u_cmm_decoder_un18_bar4_32_hit_nc_2_and; + wire com_cmm_u_cmm_decoder_un18_bar4_32_hit_nc_1_and; + wire com_cmm_u_cmm_decoder_un18_bar4_32_hit_nc_0_and; + wire com_cmm_u_cmm_decoder_un11_bar1_32_hit_nc_7_and; + wire com_cmm_u_cmm_decoder_un11_bar1_32_hit_nc_6_and; + wire com_cmm_u_cmm_decoder_un11_bar1_32_hit_nc_5_and; + wire com_cmm_u_cmm_decoder_un11_bar1_32_hit_nc_4_and; + wire com_cmm_u_cmm_decoder_un11_bar1_32_hit_nc_3_and; + wire com_cmm_u_cmm_decoder_un11_bar1_32_hit_nc_2_and; + wire com_cmm_u_cmm_decoder_un11_bar1_32_hit_nc_1_and; + wire com_cmm_u_cmm_decoder_un11_bar1_32_hit_nc_0_and; + wire com_cmm_u_cmm_decoder_un11_bar2_32_hit_nc_7_and; + wire com_cmm_u_cmm_decoder_un11_bar2_32_hit_nc_6_and; + wire com_cmm_u_cmm_decoder_un11_bar2_32_hit_nc_5_and; + wire com_cmm_u_cmm_decoder_un11_bar2_32_hit_nc_4_and; + wire com_cmm_u_cmm_decoder_un11_bar2_32_hit_nc_3_and; + wire com_cmm_u_cmm_decoder_un11_bar2_32_hit_nc_2_and; + wire com_cmm_u_cmm_decoder_un11_bar2_32_hit_nc_1_and; + wire com_cmm_u_cmm_decoder_un11_bar2_32_hit_nc_0_and; + wire com_cmm_u_cmm_decoder_un11_bar3_32_hit_nc_7_and; + wire com_cmm_u_cmm_decoder_un11_bar3_32_hit_nc_6_and; + wire com_cmm_u_cmm_decoder_un11_bar3_32_hit_nc_5_and; + wire com_cmm_u_cmm_decoder_un11_bar3_32_hit_nc_4_and; + wire com_cmm_u_cmm_decoder_un11_bar3_32_hit_nc_3_and; + wire com_cmm_u_cmm_decoder_un11_bar3_32_hit_nc_2_and; + wire com_cmm_u_cmm_decoder_un11_bar3_32_hit_nc_1_and; + wire com_cmm_u_cmm_decoder_un11_bar3_32_hit_nc_0_and; + wire com_cmm_u_cmm_decoder_un11_bar4_32_hit_nc_7_sf_5546; + wire com_cmm_u_cmm_decoder_un11_bar4_32_hit_nc_7_and; + wire com_cmm_u_cmm_decoder_un11_bar4_32_hit_nc_6_sf_5547; + wire com_cmm_u_cmm_decoder_un11_bar4_32_hit_nc_6_and; + wire com_cmm_u_cmm_decoder_un11_bar4_32_hit_nc_5_sf_5548; + wire com_cmm_u_cmm_decoder_un11_bar4_32_hit_nc_5_and; + wire com_cmm_u_cmm_decoder_un11_bar4_32_hit_nc_4_sf_5549; + wire com_cmm_u_cmm_decoder_un11_bar4_32_hit_nc_4_and; + wire com_cmm_u_cmm_decoder_un11_bar4_32_hit_nc_3_sf_5550; + wire com_cmm_u_cmm_decoder_un11_bar4_32_hit_nc_3_and; + wire com_cmm_u_cmm_decoder_un11_bar4_32_hit_nc_2_sf_5551; + wire com_cmm_u_cmm_decoder_un11_bar4_32_hit_nc_2_and; + wire com_cmm_u_cmm_decoder_un11_bar4_32_hit_nc_1_sf_5552; + wire com_cmm_u_cmm_decoder_un11_bar4_32_hit_nc_1_and; + wire com_cmm_u_cmm_decoder_un11_bar4_32_hit_nc_0_sf_5553; + wire com_cmm_u_cmm_decoder_un11_bar5_32_hit_nc_7_and; + wire com_cmm_u_cmm_decoder_un11_bar5_32_hit_nc_6_and; + wire com_cmm_u_cmm_decoder_un11_bar5_32_hit_nc_5_and; + wire com_cmm_u_cmm_decoder_un11_bar5_32_hit_nc_4_and; + wire com_cmm_u_cmm_decoder_un11_bar5_32_hit_nc_3_and; + wire com_cmm_u_cmm_decoder_un11_bar5_32_hit_nc_2_and; + wire com_cmm_u_cmm_decoder_un11_bar5_32_hit_nc_1_and; + wire com_cmm_u_cmm_decoder_un11_bar5_32_hit_nc_0_and; + wire com_cmm_u_cmm_decoder_un11_bar4_32_hit_nc_0_and; + wire com_cmm_u_cmm_decoder_N_3_13; + wire com_cmm_u_cmm_decoder_N_11_14; + wire com_cmm_u_cmm_decoder_N_19_13; + wire com_cmm_u_cmm_decoder_N_27_13; + wire com_cmm_u_cmm_decoder_N_35_13; + wire com_cmm_u_cmm_decoder_N_43_13; + wire com_cmm_u_cmm_decoder_N_51_13; + wire com_cmm_u_cmm_decoder_N_59_13; + wire com_cmm_u_cmm_decoder_N_67_13; + wire com_cmm_u_cmm_decoder_N_75_13; + wire com_cmm_u_cmm_decoder_N_83_13; + wire com_cmm_u_cmm_decoder_N_91_13; + wire com_cmm_u_cmm_decoder_N_107_12; + wire com_cmm_u_cmm_decoder_N_3_12; + wire com_cmm_u_cmm_decoder_N_11_13; + wire com_cmm_u_cmm_decoder_N_19_12; + wire com_cmm_u_cmm_decoder_N_27_12; + wire com_cmm_u_cmm_decoder_N_35_12; + wire com_cmm_u_cmm_decoder_N_43_12; + wire com_cmm_u_cmm_decoder_N_51_12; + wire com_cmm_u_cmm_decoder_N_59_12; + wire com_cmm_u_cmm_decoder_N_67_12; + wire com_cmm_u_cmm_decoder_N_75_12; + wire com_cmm_u_cmm_decoder_N_83_12; + wire com_cmm_u_cmm_decoder_N_91_12; + wire com_cmm_u_cmm_decoder_N_107_11; + wire com_cmm_u_cmm_decoder_N_3_11; + wire com_cmm_u_cmm_decoder_N_11_12; + wire com_cmm_u_cmm_decoder_N_19_11; + wire com_cmm_u_cmm_decoder_N_27_11; + wire com_cmm_u_cmm_decoder_N_35_11; + wire com_cmm_u_cmm_decoder_N_43_11; + wire com_cmm_u_cmm_decoder_N_51_11; + wire com_cmm_u_cmm_decoder_N_59_11; + wire com_cmm_u_cmm_decoder_N_67_11; + wire com_cmm_u_cmm_decoder_N_75_11; + wire com_cmm_u_cmm_decoder_N_83_11; + wire com_cmm_u_cmm_decoder_N_91_11; + wire com_cmm_u_cmm_decoder_N_107_10; + wire com_cmm_u_cmm_decoder_N_3_10; + wire com_cmm_u_cmm_decoder_N_11_11; + wire com_cmm_u_cmm_decoder_N_19_10; + wire com_cmm_u_cmm_decoder_N_27_10; + wire com_cmm_u_cmm_decoder_N_35_10; + wire com_cmm_u_cmm_decoder_N_43_10; + wire com_cmm_u_cmm_decoder_N_51_10; + wire com_cmm_u_cmm_decoder_N_59_10; + wire com_cmm_u_cmm_decoder_N_67_10; + wire com_cmm_u_cmm_decoder_N_75_10; + wire com_cmm_u_cmm_decoder_N_83_10; + wire com_cmm_u_cmm_decoder_N_91_10; + wire com_cmm_u_cmm_decoder_N_107_9; + wire com_cmm_u_cmm_decoder_N_3_9; + wire com_cmm_u_cmm_decoder_N_6_8; + wire com_cmm_u_cmm_decoder_N_11_10; + wire com_cmm_u_cmm_decoder_N_14_9; + wire com_cmm_u_cmm_decoder_N_19_9; + wire com_cmm_u_cmm_decoder_N_22_8; + wire com_cmm_u_cmm_decoder_N_27_9; + wire com_cmm_u_cmm_decoder_N_30_8; + wire com_cmm_u_cmm_decoder_N_35_9; + wire com_cmm_u_cmm_decoder_N_38_8; + wire com_cmm_u_cmm_decoder_N_43_9; + wire com_cmm_u_cmm_decoder_N_46_8; + wire com_cmm_u_cmm_decoder_N_51_9; + wire com_cmm_u_cmm_decoder_N_54_8; + wire com_cmm_u_cmm_decoder_N_59_9; + wire com_cmm_u_cmm_decoder_N_62_8; + wire com_cmm_u_cmm_decoder_N_67_9; + wire com_cmm_u_cmm_decoder_N_70_8; + wire com_cmm_u_cmm_decoder_N_75_9; + wire com_cmm_u_cmm_decoder_N_78_7; + wire com_cmm_u_cmm_decoder_N_83_9; + wire com_cmm_u_cmm_decoder_N_86_7; + wire com_cmm_u_cmm_decoder_N_91_9; + wire com_cmm_u_cmm_decoder_N_94_8; + wire com_cmm_u_cmm_decoder_N_107_8; + wire com_cmm_u_cmm_decoder_N_110_6; + wire com_cmm_u_cmm_decoder_N_3_8; + wire com_cmm_u_cmm_decoder_N_6_7; + wire com_cmm_u_cmm_decoder_N_11_9; + wire com_cmm_u_cmm_decoder_N_14_8; + wire com_cmm_u_cmm_decoder_N_19_8; + wire com_cmm_u_cmm_decoder_N_22_7; + wire com_cmm_u_cmm_decoder_N_27_8; + wire com_cmm_u_cmm_decoder_N_30_7; + wire com_cmm_u_cmm_decoder_N_35_8; + wire com_cmm_u_cmm_decoder_N_38_7; + wire com_cmm_u_cmm_decoder_N_43_8; + wire com_cmm_u_cmm_decoder_N_46_7; + wire com_cmm_u_cmm_decoder_N_51_8; + wire com_cmm_u_cmm_decoder_N_54_7; + wire com_cmm_u_cmm_decoder_N_59_8; + wire com_cmm_u_cmm_decoder_N_62_7; + wire com_cmm_u_cmm_decoder_N_67_8; + wire com_cmm_u_cmm_decoder_N_70_7; + wire com_cmm_u_cmm_decoder_N_75_8; + wire com_cmm_u_cmm_decoder_N_78_6; + wire com_cmm_u_cmm_decoder_N_83_8; + wire com_cmm_u_cmm_decoder_N_86_6; + wire com_cmm_u_cmm_decoder_N_91_8; + wire com_cmm_u_cmm_decoder_N_94_7; + wire com_cmm_u_cmm_decoder_N_107_7; + wire com_cmm_u_cmm_decoder_N_110_5; + wire com_cmm_u_cmm_decoder_N_3_7; + wire com_cmm_u_cmm_decoder_N_6_6; + wire com_cmm_u_cmm_decoder_N_11_8; + wire com_cmm_u_cmm_decoder_N_14_7; + wire com_cmm_u_cmm_decoder_N_19_7; + wire com_cmm_u_cmm_decoder_N_22_6; + wire com_cmm_u_cmm_decoder_N_27_7; + wire com_cmm_u_cmm_decoder_N_30_6; + wire com_cmm_u_cmm_decoder_N_35_7; + wire com_cmm_u_cmm_decoder_N_38_6; + wire com_cmm_u_cmm_decoder_N_43_7; + wire com_cmm_u_cmm_decoder_N_46_6; + wire com_cmm_u_cmm_decoder_N_51_7; + wire com_cmm_u_cmm_decoder_N_54_6; + wire com_cmm_u_cmm_decoder_N_59_7; + wire com_cmm_u_cmm_decoder_N_62_6; + wire com_cmm_u_cmm_decoder_N_67_7; + wire com_cmm_u_cmm_decoder_N_70_6; + wire com_cmm_u_cmm_decoder_N_75_7; + wire com_cmm_u_cmm_decoder_N_78_5; + wire com_cmm_u_cmm_decoder_N_83_7; + wire com_cmm_u_cmm_decoder_N_86_5; + wire com_cmm_u_cmm_decoder_N_91_7; + wire com_cmm_u_cmm_decoder_N_94_6; + wire com_cmm_u_cmm_decoder_N_107_6; + wire com_cmm_u_cmm_decoder_N_110_4; + wire com_cmm_u_cmm_decoder_N_3_6; + wire com_cmm_u_cmm_decoder_N_6_5; + wire com_cmm_u_cmm_decoder_N_11_7; + wire com_cmm_u_cmm_decoder_N_14_6; + wire com_cmm_u_cmm_decoder_N_19_6; + wire com_cmm_u_cmm_decoder_N_22_5; + wire com_cmm_u_cmm_decoder_N_27_6; + wire com_cmm_u_cmm_decoder_N_30_5; + wire com_cmm_u_cmm_decoder_N_35_6; + wire com_cmm_u_cmm_decoder_N_38_5; + wire com_cmm_u_cmm_decoder_N_43_6; + wire com_cmm_u_cmm_decoder_N_46_5; + wire com_cmm_u_cmm_decoder_N_51_6; + wire com_cmm_u_cmm_decoder_N_54_5; + wire com_cmm_u_cmm_decoder_N_59_6; + wire com_cmm_u_cmm_decoder_N_62_5; + wire com_cmm_u_cmm_decoder_N_67_6; + wire com_cmm_u_cmm_decoder_N_70_5; + wire com_cmm_u_cmm_decoder_N_75_6; + wire com_cmm_u_cmm_decoder_N_78_4; + wire com_cmm_u_cmm_decoder_N_83_6; + wire com_cmm_u_cmm_decoder_N_86_4; + wire com_cmm_u_cmm_decoder_N_91_6; + wire com_cmm_u_cmm_decoder_N_94_5; + wire com_cmm_u_cmm_decoder_N_107_5; + wire com_cmm_u_cmm_decoder_N_110_3; + wire com_cmm_u_cmm_decoder_N_3_5; + wire com_cmm_u_cmm_decoder_N_6_4; + wire com_cmm_u_cmm_decoder_N_11_6; + wire com_cmm_u_cmm_decoder_N_14_5; + wire com_cmm_u_cmm_decoder_N_19_5; + wire com_cmm_u_cmm_decoder_N_22_4; + wire com_cmm_u_cmm_decoder_N_27_5; + wire com_cmm_u_cmm_decoder_N_30_4; + wire com_cmm_u_cmm_decoder_N_35_5; + wire com_cmm_u_cmm_decoder_N_38_4; + wire com_cmm_u_cmm_decoder_N_43_5; + wire com_cmm_u_cmm_decoder_N_46_4; + wire com_cmm_u_cmm_decoder_N_51_5; + wire com_cmm_u_cmm_decoder_N_54_4; + wire com_cmm_u_cmm_decoder_N_59_5; + wire com_cmm_u_cmm_decoder_N_62_4; + wire com_cmm_u_cmm_decoder_N_67_5; + wire com_cmm_u_cmm_decoder_N_70_4; + wire com_cmm_u_cmm_decoder_N_75_5; + wire com_cmm_u_cmm_decoder_N_78_3; + wire com_cmm_u_cmm_decoder_N_83_5; + wire com_cmm_u_cmm_decoder_N_86_3; + wire com_cmm_u_cmm_decoder_N_91_5; + wire com_cmm_u_cmm_decoder_N_94_4; + wire com_cmm_u_cmm_decoder_N_107_4; + wire com_cmm_u_cmm_decoder_N_110_2; + wire com_cmm_u_cmm_decoder_N_3_4; + wire com_cmm_u_cmm_decoder_N_6_3; + wire com_cmm_u_cmm_decoder_N_11_5; + wire com_cmm_u_cmm_decoder_N_14_4; + wire com_cmm_u_cmm_decoder_N_19_4; + wire com_cmm_u_cmm_decoder_N_22_3; + wire com_cmm_u_cmm_decoder_N_27_4; + wire com_cmm_u_cmm_decoder_N_30_3; + wire com_cmm_u_cmm_decoder_N_35_4; + wire com_cmm_u_cmm_decoder_N_38_3; + wire com_cmm_u_cmm_decoder_N_43_4; + wire com_cmm_u_cmm_decoder_N_46_3; + wire com_cmm_u_cmm_decoder_N_51_4; + wire com_cmm_u_cmm_decoder_N_54_3; + wire com_cmm_u_cmm_decoder_N_59_4; + wire com_cmm_u_cmm_decoder_N_62_3; + wire com_cmm_u_cmm_decoder_N_67_4; + wire com_cmm_u_cmm_decoder_N_70_3; + wire com_cmm_u_cmm_decoder_N_75_4; + wire com_cmm_u_cmm_decoder_N_78_2; + wire com_cmm_u_cmm_decoder_N_83_4; + wire com_cmm_u_cmm_decoder_N_86_2; + wire com_cmm_u_cmm_decoder_N_91_4; + wire com_cmm_u_cmm_decoder_N_94_3; + wire com_cmm_u_cmm_decoder_N_107_3; + wire com_cmm_u_cmm_decoder_N_110_1; + wire com_cmm_u_cmm_decoder_N_9; + wire com_cmm_u_cmm_decoder_N_12; + wire com_cmm_u_cmm_decoder_N_17; + wire com_cmm_u_cmm_decoder_N_20; + wire com_cmm_u_cmm_decoder_N_25; + wire com_cmm_u_cmm_decoder_N_28; + wire com_cmm_u_cmm_decoder_N_33; + wire com_cmm_u_cmm_decoder_N_36; + wire com_cmm_u_cmm_decoder_N_41; + wire com_cmm_u_cmm_decoder_N_44; + wire com_cmm_u_cmm_decoder_N_49; + wire com_cmm_u_cmm_decoder_N_52; + wire com_cmm_u_cmm_decoder_N_57; + wire com_cmm_u_cmm_decoder_N_60; + wire com_cmm_u_cmm_decoder_N_65; + wire com_cmm_u_cmm_decoder_N_68; + wire com_cmm_u_cmm_decoder_N_73; + wire com_cmm_u_cmm_decoder_N_76; + wire com_cmm_u_cmm_decoder_N_81; + wire com_cmm_u_cmm_decoder_N_84; + wire com_cmm_u_cmm_decoder_I_118_sf; + wire com_cmm_u_cmm_decoder_N_3_3; + wire com_cmm_u_cmm_decoder_I_109_sf; + wire com_cmm_u_cmm_decoder_N_11_4; + wire com_cmm_u_cmm_decoder_I_100_sf; + wire com_cmm_u_cmm_decoder_N_19_3; + wire com_cmm_u_cmm_decoder_I_91_sf; + wire com_cmm_u_cmm_decoder_N_27_3; + wire com_cmm_u_cmm_decoder_I_82_sf; + wire com_cmm_u_cmm_decoder_N_35_3; + wire com_cmm_u_cmm_decoder_I_73_sf; + wire com_cmm_u_cmm_decoder_N_43_3; + wire com_cmm_u_cmm_decoder_I_64_sf; + wire com_cmm_u_cmm_decoder_N_51_3; + wire com_cmm_u_cmm_decoder_I_55_sf; + wire com_cmm_u_cmm_decoder_N_59_3; + wire com_cmm_u_cmm_decoder_I_46_sf; + wire com_cmm_u_cmm_decoder_N_67_3; + wire com_cmm_u_cmm_decoder_I_37_sf; + wire com_cmm_u_cmm_decoder_N_75_3; + wire com_cmm_u_cmm_decoder_I_28_sf; + wire com_cmm_u_cmm_decoder_N_83_3; + wire com_cmm_u_cmm_decoder_I_19_sf; + wire com_cmm_u_cmm_decoder_N_91_3; + wire com_cmm_u_cmm_decoder_N_3_2; + wire com_cmm_u_cmm_decoder_N_86_1; + wire com_cmm_u_cmm_decoder_N_11_3; + wire com_cmm_u_cmm_decoder_N_102_2; + wire com_cmm_u_cmm_decoder_N_19_2; + wire com_cmm_u_cmm_decoder_N_14_3; + wire com_cmm_u_cmm_decoder_N_27_2; + wire com_cmm_u_cmm_decoder_N_6_2; + wire com_cmm_u_cmm_decoder_N_35_2; + wire com_cmm_u_cmm_decoder_N_54_2; + wire com_cmm_u_cmm_decoder_N_43_2; + wire com_cmm_u_cmm_decoder_N_94_2; + wire com_cmm_u_cmm_decoder_N_51_2; + wire com_cmm_u_cmm_decoder_N_46_2; + wire com_cmm_u_cmm_decoder_N_59_2; + wire com_cmm_u_cmm_decoder_N_38_2; + wire com_cmm_u_cmm_decoder_N_67_2; + wire com_cmm_u_cmm_decoder_N_22_2; + wire com_cmm_u_cmm_decoder_N_75_2; + wire com_cmm_u_cmm_decoder_N_62_2; + wire com_cmm_u_cmm_decoder_N_39_2; + wire com_cmm_u_cmm_decoder_N_83_2; + wire com_cmm_u_cmm_decoder_N_78_1; + wire com_cmm_u_cmm_decoder_N_63_2; + wire com_cmm_u_cmm_decoder_N_91_2; + wire com_cmm_u_cmm_decoder_N_70_2; + wire com_cmm_u_cmm_decoder_N_23_2; + wire com_cmm_u_cmm_decoder_N_107_2; + wire com_cmm_u_cmm_decoder_N_30_2; + wire com_cmm_u_cmm_decoder_N_7_2; + wire com_cmm_u_cmm_decoder_N_115_2; + wire com_cmm_u_cmm_decoder_N_110_0; + wire com_cmm_u_cmm_decoder_N_123_2; + wire com_cmm_u_cmm_decoder_N_111_2; + wire com_cmm_u_cmm_decoder_N_3_1; + wire com_cmm_u_cmm_decoder_N_86_0; + wire com_cmm_u_cmm_decoder_N_11_2; + wire com_cmm_u_cmm_decoder_N_102_1; + wire com_cmm_u_cmm_decoder_N_19_1; + wire com_cmm_u_cmm_decoder_N_14_2; + wire com_cmm_u_cmm_decoder_N_27_1; + wire com_cmm_u_cmm_decoder_N_6_1; + wire com_cmm_u_cmm_decoder_N_35_1; + wire com_cmm_u_cmm_decoder_N_54_1; + wire com_cmm_u_cmm_decoder_N_47_1; + wire com_cmm_u_cmm_decoder_N_43_1; + wire com_cmm_u_cmm_decoder_N_94_1; + wire com_cmm_u_cmm_decoder_N_51_1; + wire com_cmm_u_cmm_decoder_N_46_1; + wire com_cmm_u_cmm_decoder_N_59_1; + wire com_cmm_u_cmm_decoder_N_38_1; + wire com_cmm_u_cmm_decoder_N_67_1; + wire com_cmm_u_cmm_decoder_N_22_1; + wire com_cmm_u_cmm_decoder_N_15_1; + wire com_cmm_u_cmm_decoder_N_75_1; + wire com_cmm_u_cmm_decoder_N_62_1; + wire com_cmm_u_cmm_decoder_N_39_1; + wire com_cmm_u_cmm_decoder_N_83_1; + wire com_cmm_u_cmm_decoder_N_78_0; + wire com_cmm_u_cmm_decoder_N_63_1; + wire com_cmm_u_cmm_decoder_N_91_1; + wire com_cmm_u_cmm_decoder_N_70_1; + wire com_cmm_u_cmm_decoder_N_23_1; + wire com_cmm_u_cmm_decoder_N_107_1; + wire com_cmm_u_cmm_decoder_N_30_1; + wire com_cmm_u_cmm_decoder_N_7_1; + wire com_cmm_u_cmm_decoder_N_115_1; + wire com_cmm_u_cmm_decoder_N_31_1; + wire com_cmm_u_cmm_decoder_N_123_1; + wire com_cmm_u_cmm_decoder_N_111_1; + wire com_cmm_u_cmm_decoder_N_3_0; + wire com_cmm_u_cmm_decoder_N_86; + wire com_cmm_u_cmm_decoder_N_11_1; + wire com_cmm_u_cmm_decoder_N_102_0; + wire com_cmm_u_cmm_decoder_N_19_0; + wire com_cmm_u_cmm_decoder_N_14_1; + wire com_cmm_u_cmm_decoder_N_27_0; + wire com_cmm_u_cmm_decoder_N_6_0; + wire com_cmm_u_cmm_decoder_N_35_0; + wire com_cmm_u_cmm_decoder_N_54_0; + wire com_cmm_u_cmm_decoder_N_47_0; + wire com_cmm_u_cmm_decoder_N_43_0; + wire com_cmm_u_cmm_decoder_N_94_0; + wire com_cmm_u_cmm_decoder_N_51_0; + wire com_cmm_u_cmm_decoder_N_46_0; + wire com_cmm_u_cmm_decoder_N_59_0; + wire com_cmm_u_cmm_decoder_N_38_0; + wire com_cmm_u_cmm_decoder_N_67_0; + wire com_cmm_u_cmm_decoder_N_22_0; + wire com_cmm_u_cmm_decoder_N_15_0; + wire com_cmm_u_cmm_decoder_N_75_0; + wire com_cmm_u_cmm_decoder_N_62_0; + wire com_cmm_u_cmm_decoder_N_39_0; + wire com_cmm_u_cmm_decoder_N_83_0; + wire com_cmm_u_cmm_decoder_N_78; + wire com_cmm_u_cmm_decoder_N_63_0; + wire com_cmm_u_cmm_decoder_N_91_0; + wire com_cmm_u_cmm_decoder_N_70_0; + wire com_cmm_u_cmm_decoder_N_23_0; + wire com_cmm_u_cmm_decoder_N_107_0; + wire com_cmm_u_cmm_decoder_N_30_0; + wire com_cmm_u_cmm_decoder_N_7_0; + wire com_cmm_u_cmm_decoder_N_115_0; + wire com_cmm_u_cmm_decoder_N_31_0; + wire com_cmm_u_cmm_decoder_N_123_0; + wire com_cmm_u_cmm_decoder_N_111_0; + wire com_cmm_u_cmm_decoder_N_3; + wire com_cmm_u_cmm_decoder_N_79; + wire com_cmm_u_cmm_decoder_N_11_0; + wire com_cmm_u_cmm_decoder_N_102; + wire com_cmm_u_cmm_decoder_N_19; + wire com_cmm_u_cmm_decoder_N_14_0; + wire com_cmm_u_cmm_decoder_N_27; + wire com_cmm_u_cmm_decoder_N_87; + wire com_cmm_u_cmm_decoder_N_6; + wire com_cmm_u_cmm_decoder_N_35; + wire com_cmm_u_cmm_decoder_N_54; + wire com_cmm_u_cmm_decoder_N_47; + wire com_cmm_u_cmm_decoder_N_43; + wire com_cmm_u_cmm_decoder_N_94; + wire com_cmm_u_cmm_decoder_N_51; + wire com_cmm_u_cmm_decoder_N_46; + wire com_cmm_u_cmm_decoder_N_59; + wire com_cmm_u_cmm_decoder_N_38; + wire com_cmm_u_cmm_decoder_N_67; + wire com_cmm_u_cmm_decoder_N_22; + wire com_cmm_u_cmm_decoder_N_15; + wire com_cmm_u_cmm_decoder_N_75; + wire com_cmm_u_cmm_decoder_N_62; + wire com_cmm_u_cmm_decoder_N_39; + wire com_cmm_u_cmm_decoder_N_83; + wire com_cmm_u_cmm_decoder_N_63; + wire com_cmm_u_cmm_decoder_N_91; + wire com_cmm_u_cmm_decoder_N_70; + wire com_cmm_u_cmm_decoder_N_23; + wire com_cmm_u_cmm_decoder_N_107; + wire com_cmm_u_cmm_decoder_N_30; + wire com_cmm_u_cmm_decoder_N_7; + wire com_cmm_u_cmm_decoder_N_115; + wire com_cmm_u_cmm_decoder_N_110; + wire com_cmm_u_cmm_decoder_N_31; + wire com_cmm_u_cmm_decoder_N_123; + wire com_cmm_u_cmm_decoder_N_111; + wire com_cmm_u_cmm_decoder_N_11; + wire com_cmm_u_cmm_decoder_N_14; + wire com_cmm_u_cmm_cfgspace_N_10576_i_5554; + wire com_cmm_u_cmm_cfgspace_sel_encodex_en_5555; + wire com_cmm_u_cmm_cfgspace_N_18687_i; + wire com_cmm_u_cmm_cfgspace_low_addr_01_3_0_bm_0__5556; + wire com_cmm_u_cmm_cfgspace_low_addr_01_3_0_am_0__5557; + wire com_cmm_u_cmm_cfgspace_low_addr_01_3_0_bm_10__5558; + wire com_cmm_u_cmm_cfgspace_low_addr_01_3_0_am_10__5559; + wire com_cmm_u_cmm_cfgspace_N_3858; + wire com_cmm_u_cmm_cfgspace_N_3868; + wire com_cmm_u_cmm_cfgspace_low_addr_02_3_0_bm_16__5560; + wire com_cmm_u_cmm_cfgspace_low_addr_02_3_0_am_16__5561; + wire com_cmm_u_cmm_cfgspace_N_4720; + wire com_cmm_u_cmm_cfgspace_N_4722; + wire com_cmm_u_cmm_cfgspace_N_59532_1; + wire com_cmm_u_cmm_cfgspace_low_addr_02_3_0_bm_11__5562; + wire com_cmm_u_cmm_cfgspace_low_addr_02_3_0_am_11__5563; + wire com_cmm_u_cmm_cfgspace_low_addr_02_3_0_bm_12__5564; + wire com_cmm_u_cmm_cfgspace_low_addr_02_3_0_am_12__5565; + wire com_cmm_u_cmm_cfgspace_low_addr_02_3_0_bm_14__5566; + wire com_cmm_u_cmm_cfgspace_low_addr_02_3_0_am_14__5567; + wire com_cmm_u_cmm_cfgspace_N_55964_i; + wire com_cmm_u_cmm_cfgspace_N_61391; + wire com_cmm_u_cmm_cfgspace_low_addr_01_7_0_bm_20__5568; + wire com_cmm_u_cmm_cfgspace_low_addr_01_7_0_am_20__5569; + wire com_cmm_u_cmm_cfgspace_low_addr_01_7_0_bm_21__5570; + wire com_cmm_u_cmm_cfgspace_low_addr_01_7_0_am_21__5571; + wire com_cmm_u_cmm_cfgspace_low_addr_01_7_0_bm_22__5572; + wire com_cmm_u_cmm_cfgspace_low_addr_01_7_0_am_22__5573; + wire com_cmm_u_cmm_cfgspace_low_addr_01_7_0_bm_23__5574; + wire com_cmm_u_cmm_cfgspace_low_addr_01_7_0_am_23__5575; + wire com_cmm_u_cmm_cfgspace_low_addr_01_7_0_bm_18__5576; + wire com_cmm_u_cmm_cfgspace_low_addr_01_7_0_am_18__5577; + wire com_cmm_u_cmm_cfgspace_low_addr_01_7_0_bm_17__5578; + wire com_cmm_u_cmm_cfgspace_low_addr_01_7_0_am_17__5579; + wire com_cmm_u_cmm_cfgspace_low_addr_01_7_0_bm_16__5580; + wire com_cmm_u_cmm_cfgspace_low_addr_01_7_0_am_16__5581; + wire com_cmm_u_cmm_cfgspace_sel_1x_3_0_0_0_0_o3_2; + wire com_cmm_u_cmm_cfgspace_low_addr_00_i_0_1_39297_5582; + wire com_cmm_u_cmm_cfgspace_low_addr_00_0_0_0_0_14__5583; + wire com_cmm_u_cmm_cfgspace_N_61347; + wire com_cmm_u_cmm_cfgspace_N_61316; + wire com_cmm_u_cmm_cfgspace_N_59578_1; + wire com_cmm_u_cmm_cfgspace_N_61355; + wire com_cmm_u_cmm_cfgspace_N_3731; + wire com_cmm_u_cmm_cfgspace_N_3859; + wire com_cmm_u_cmm_cfgspace_low_addr_01_7_0_bm_1__5584; + wire com_cmm_u_cmm_cfgspace_low_addr_01_7_0_am_1__5585; + wire com_cmm_u_cmm_cfgspace_N_3860; + wire com_cmm_u_cmm_cfgspace_low_addr_01_7_0_bm_2__5586; + wire com_cmm_u_cmm_cfgspace_low_addr_01_7_0_am_2__5587; + wire com_cmm_u_cmm_cfgspace_N_3861; + wire com_cmm_u_cmm_cfgspace_low_addr_01_7_0_bm_3__5588; + wire com_cmm_u_cmm_cfgspace_N_3862; + wire com_cmm_u_cmm_cfgspace_low_addr_01_7_0_bm_4__5589; + wire com_cmm_u_cmm_cfgspace_low_addr_01_7_0_am_4__5590; + wire com_cmm_u_cmm_cfgspace_N_3863; + wire com_cmm_u_cmm_cfgspace_low_addr_01_7_0_bm_5__5591; + wire com_cmm_u_cmm_cfgspace_low_addr_01_7_0_am_5__5592; + wire com_cmm_u_cmm_cfgspace_N_3865; + wire com_cmm_u_cmm_cfgspace_low_addr_01_7_0_bm_7__5593; + wire com_cmm_u_cmm_cfgspace_low_addr_01_7_0_am_7__5594; + wire com_cmm_u_cmm_cfgspace_N_3738; + wire com_cmm_u_cmm_cfgspace_N_3866; + wire com_cmm_u_cmm_cfgspace_low_addr_01_7_0_bm_8__5595; + wire com_cmm_u_cmm_cfgspace_low_addr_01_7_0_am_8__5596; + wire com_cmm_u_cmm_cfgspace_N_3867; + wire com_cmm_u_cmm_cfgspace_low_addr_01_7_0_bm_9__5597; + wire com_cmm_u_cmm_cfgspace_low_addr_01_7_0_am_9__5598; + wire com_cmm_u_cmm_cfgspace_N_3773; + wire com_cmm_u_cmm_cfgspace_N_3869; + wire com_cmm_u_cmm_cfgspace_low_addr_01_7_0_bm_11__5599; + wire com_cmm_u_cmm_cfgspace_low_addr_01_7_0_am_11__5600; + wire com_cmm_u_cmm_cfgspace_N_3775; + wire com_cmm_u_cmm_cfgspace_N_3871; + wire com_cmm_u_cmm_cfgspace_low_addr_01_7_0_bm_13__5601; + wire com_cmm_u_cmm_cfgspace_low_addr_01_7_0_am_13__5602; + wire com_cmm_u_cmm_cfgspace_N_3777; + wire com_cmm_u_cmm_cfgspace_N_3873; + wire com_cmm_u_cmm_cfgspace_low_addr_01_7_0_bm_15__5603; + wire com_cmm_u_cmm_cfgspace_low_addr_01_7_0_am_15__5604; + wire com_cmm_u_cmm_cfgspace_N_3749; + wire com_cmm_u_cmm_cfgspace_low_addr_01_7_0_bm_19__5605; + wire com_cmm_u_cmm_cfgspace_low_addr_01_7_0_am_19__5606; + wire com_cmm_u_cmm_cfgspace_N_4050; + wire com_cmm_u_cmm_cfgspace_N_4051; + wire com_cmm_u_cmm_cfgspace_N_3956; + wire com_cmm_u_cmm_cfgspace_N_4052; + wire com_cmm_u_cmm_cfgspace_N_3957; + wire com_cmm_u_cmm_cfgspace_N_4053; + wire com_cmm_u_cmm_cfgspace_N_3958; + wire com_cmm_u_cmm_cfgspace_N_4054; + wire com_cmm_u_cmm_cfgspace_N_3959; + wire com_cmm_u_cmm_cfgspace_N_4055; + wire com_cmm_u_cmm_cfgspace_N_3960; + wire com_cmm_u_cmm_cfgspace_N_4056; + wire com_cmm_u_cmm_cfgspace_N_3961; + wire com_cmm_u_cmm_cfgspace_N_4057; + wire com_cmm_u_cmm_cfgspace_N_4578; + wire com_cmm_u_cmm_cfgspace_N_4706; + wire com_cmm_u_cmm_cfgspace_low_addr_02_7_0_bm_0__5607; + wire com_cmm_u_cmm_cfgspace_low_addr_02_7_0_am_0__5608; + wire com_cmm_u_cmm_cfgspace_N_4579; + wire com_cmm_u_cmm_cfgspace_N_4707; + wire com_cmm_u_cmm_cfgspace_low_addr_02_7_0_bm_1__5609; + wire com_cmm_u_cmm_cfgspace_low_addr_02_7_0_am_1__5610; + wire com_cmm_u_cmm_cfgspace_N_4708; + wire com_cmm_u_cmm_cfgspace_low_addr_02_7_0_bm_2__5611; + wire com_cmm_u_cmm_cfgspace_low_addr_02_7_0_am_2__5612; + wire com_cmm_u_cmm_cfgspace_N_4581; + wire com_cmm_u_cmm_cfgspace_N_4709; + wire com_cmm_u_cmm_cfgspace_low_addr_02_7_0_bm_3__5613; + wire com_cmm_u_cmm_cfgspace_low_addr_02_7_0_am_3__5614; + wire com_cmm_u_cmm_cfgspace_N_4710; + wire com_cmm_u_cmm_cfgspace_low_addr_02_7_0_bm_4__5615; + wire com_cmm_u_cmm_cfgspace_low_addr_02_7_0_am_4__5616; + wire com_cmm_u_cmm_cfgspace_N_4711; + wire com_cmm_u_cmm_cfgspace_low_addr_02_7_0_bm_5__5617; + wire com_cmm_u_cmm_cfgspace_low_addr_02_7_0_am_5__5618; + wire com_cmm_u_cmm_cfgspace_N_4723; + wire com_cmm_u_cmm_cfgspace_low_addr_02_7_0_bm_17__5619; + wire com_cmm_u_cmm_cfgspace_low_addr_02_7_0_am_17__5620; + wire com_cmm_u_cmm_cfgspace_N_4724; + wire com_cmm_u_cmm_cfgspace_low_addr_02_7_0_bm_18__5621; + wire com_cmm_u_cmm_cfgspace_low_addr_02_7_0_am_18__5622; + wire com_cmm_u_cmm_cfgspace_N_4725; + wire com_cmm_u_cmm_cfgspace_low_addr_02_7_0_bm_19__5623; + wire com_cmm_u_cmm_cfgspace_low_addr_02_7_0_am_19__5624; + wire com_cmm_u_cmm_cfgspace_N_4598; + wire com_cmm_u_cmm_cfgspace_N_4726; + wire com_cmm_u_cmm_cfgspace_low_addr_02_7_0_bm_20__5625; + wire com_cmm_u_cmm_cfgspace_low_addr_02_7_0_am_20__5626; + wire com_cmm_u_cmm_cfgspace_N_4727; + wire com_cmm_u_cmm_cfgspace_low_addr_02_7_0_bm_21__5627; + wire com_cmm_u_cmm_cfgspace_low_addr_02_7_0_am_21__5628; + wire com_cmm_u_cmm_cfgspace_N_4600; + wire com_cmm_u_cmm_cfgspace_N_4728; + wire com_cmm_u_cmm_cfgspace_low_addr_02_7_0_bm_22__5629; + wire com_cmm_u_cmm_cfgspace_low_addr_02_7_0_am_22__5630; + wire com_cmm_u_cmm_cfgspace_N_4729; + wire com_cmm_u_cmm_cfgspace_low_addr_02_7_0_bm_23__5631; + wire com_cmm_u_cmm_cfgspace_low_addr_02_7_0_am_23__5632; + wire com_cmm_u_cmm_cfgspace_N_4730; + wire com_cmm_u_cmm_cfgspace_low_addr_02_7_0_bm_24__5633; + wire com_cmm_u_cmm_cfgspace_low_addr_02_7_0_am_24__5634; + wire com_cmm_u_cmm_cfgspace_N_4731; + wire com_cmm_u_cmm_cfgspace_low_addr_02_7_0_bm_25__5635; + wire com_cmm_u_cmm_cfgspace_low_addr_02_7_0_am_25__5636; + wire com_cmm_u_cmm_cfgspace_N_4732; + wire com_cmm_u_cmm_cfgspace_low_addr_02_7_0_bm_26__5637; + wire com_cmm_u_cmm_cfgspace_low_addr_02_7_0_am_26__5638; + wire com_cmm_u_cmm_cfgspace_N_4733; + wire com_cmm_u_cmm_cfgspace_low_addr_02_7_0_bm_27__5639; + wire com_cmm_u_cmm_cfgspace_low_addr_02_7_0_am_27__5640; + wire com_cmm_u_cmm_cfgspace_N_4606; + wire com_cmm_u_cmm_cfgspace_N_4734; + wire com_cmm_u_cmm_cfgspace_low_addr_02_7_0_bm_28__5641; + wire com_cmm_u_cmm_cfgspace_low_addr_02_7_0_am_28__5642; + wire com_cmm_u_cmm_cfgspace_N_4735; + wire com_cmm_u_cmm_cfgspace_low_addr_02_7_0_bm_29__5643; + wire com_cmm_u_cmm_cfgspace_low_addr_02_7_0_am_29__5644; + wire com_cmm_u_cmm_cfgspace_N_4736; + wire com_cmm_u_cmm_cfgspace_low_addr_02_7_0_bm_30__5645; + wire com_cmm_u_cmm_cfgspace_low_addr_02_7_0_am_30__5646; + wire com_cmm_u_cmm_cfgspace_N_4737; + wire com_cmm_u_cmm_cfgspace_low_addr_02_7_0_bm_31__5647; + wire com_cmm_u_cmm_cfgspace_low_addr_02_7_0_am_31__5648; + wire com_cmm_u_cmm_cfgspace_N_63556; + wire com_cmm_u_cmm_cfgspace_N_63586; + wire com_cmm_u_cmm_cfgspace_N_63559; + wire com_cmm_u_cmm_cfgspace_N_63589; + wire com_cmm_u_cmm_cfgspace_N_63560; + wire com_cmm_u_cmm_cfgspace_N_63590; + wire com_cmm_u_cmm_cfgspace_N_63561; + wire com_cmm_u_cmm_cfgspace_N_63591; + wire com_cmm_u_cmm_cfgspace_N_63562; + wire com_cmm_u_cmm_cfgspace_N_63592; + wire com_cmm_u_cmm_cfgspace_N_63563; + wire com_cmm_u_cmm_cfgspace_N_63593; + wire com_cmm_u_cmm_cfgspace_N_4585; + wire com_cmm_u_cmm_cfgspace_N_4713; + wire com_cmm_u_cmm_cfgspace_low_addr_02_7_0_bm_7__5649; + wire com_cmm_u_cmm_cfgspace_low_addr_02_7_0_am_7__5650; + wire com_cmm_u_cmm_cfgspace_N_4584; + wire com_cmm_u_cmm_cfgspace_N_4712; + wire com_cmm_u_cmm_cfgspace_low_addr_02_7_0_bm_6__5651; + wire com_cmm_u_cmm_cfgspace_low_addr_02_7_0_am_6__5652; + wire com_cmm_u_cmm_cfgspace_N_3776; + wire com_cmm_u_cmm_cfgspace_N_3872; + wire com_cmm_u_cmm_cfgspace_low_addr_01_7_0_bm_14__5653; + wire com_cmm_u_cmm_cfgspace_low_addr_01_7_0_am_14__5654; + wire com_cmm_u_cmm_cfgspace_N_3774; + wire com_cmm_u_cmm_cfgspace_N_3870; + wire com_cmm_u_cmm_cfgspace_low_addr_01_7_0_bm_12__5655; + wire com_cmm_u_cmm_cfgspace_low_addr_01_7_0_am_12__5656; + wire com_cmm_u_cmm_cfgspace_N_3736; + wire com_cmm_u_cmm_cfgspace_N_3864; + wire com_cmm_u_cmm_cfgspace_low_addr_01_7_0_bm_6__5657; + wire com_cmm_u_cmm_cfgspace_low_addr_01_7_0_am_6__5658; + wire com_cmm_u_cmm_cfgspace_N_4586; + wire com_cmm_u_cmm_cfgspace_low_addr_02_7_0_bm_8__5659; + wire com_cmm_u_cmm_cfgspace_low_addr_02_7_0_am_8__5660; + wire com_cmm_u_cmm_cfgspace_N_4587; + wire com_cmm_u_cmm_cfgspace_low_addr_02_7_0_bm_9__5661; + wire com_cmm_u_cmm_cfgspace_low_addr_02_7_0_am_9__5662; + wire com_cmm_u_cmm_cfgspace_N_4588; + wire com_cmm_u_cmm_cfgspace_low_addr_02_7_0_bm_10__5663; + wire com_cmm_u_cmm_cfgspace_low_addr_02_7_0_am_10__5664; + wire com_cmm_u_cmm_cfgspace_N_4591; + wire com_cmm_u_cmm_cfgspace_low_addr_02_7_0_bm_13__5665; + wire com_cmm_u_cmm_cfgspace_low_addr_02_7_0_am_13__5666; + wire com_cmm_u_cmm_cfgspace_N_59052_1; + wire com_cmm_u_cmm_cfgspace_N_4593; + wire com_cmm_u_cmm_cfgspace_N_4721; + wire com_cmm_u_cmm_cfgspace_low_addr_02_7_0_bm_15__5667; + wire com_cmm_u_cmm_cfgspace_low_addr_02_7_0_am_15__5668; + wire com_cmm_u_cmm_cfgspace_low_addr_00_i_0_15_39327_5669; + wire com_cmm_u_cmm_cfgspace_N_59358; + wire com_cmm_u_cmm_cfgspace_N_63588; + wire com_cmm_u_cmm_cfgspace_N_63558; + wire com_cmm_u_cmm_cfgspace_N_63587; + wire com_cmm_u_cmm_cfgspace_N_63557; + wire com_cmm_u_cmm_cfgspace_N_61379; + wire com_cmm_u_cmm_cfgspace_N_57261_1; + wire com_cmm_u_cmm_cfgspace_low_addr_00_i_0_0_0_31_39352_5670; + wire com_cmm_u_cmm_cfgspace_low_addr_00_i_0_0_0_31_39351_5671; + wire com_cmm_u_cmm_cfgspace_low_addr_00_i_0_0_0_28_39357_5672; + wire com_cmm_u_cmm_cfgspace_low_addr_00_i_0_0_0_28_39356_5673; + wire com_cmm_u_cmm_cfgspace_low_addr_00_i_0_0_0_27_39362_5674; + wire com_cmm_u_cmm_cfgspace_low_addr_00_i_0_0_0_27_39361_5675; + wire com_cmm_u_cmm_cfgspace_N_61290_2; + wire com_cmm_u_cmm_cfgspace_N_63596; + wire com_cmm_u_cmm_cfgspace_N_3754; + wire com_cmm_u_cmm_cfgspace_low_addr_01_7_0_bm_24__5676; + wire com_cmm_u_cmm_cfgspace_low_addr_01_7_0_am_24__5677; + wire com_cmm_u_cmm_cfgspace_N_59875; + wire com_cmm_u_cmm_cfgspace_low_addr_01_7_0_bm_25__5678; + wire com_cmm_u_cmm_cfgspace_low_addr_01_7_0_am_25__5679; + wire com_cmm_u_cmm_cfgspace_N_59876; + wire com_cmm_u_cmm_cfgspace_low_addr_01_7_0_bm_26__5680; + wire com_cmm_u_cmm_cfgspace_low_addr_01_7_0_am_26__5681; + wire com_cmm_u_cmm_cfgspace_N_63599; + wire com_cmm_u_cmm_cfgspace_N_3757; + wire com_cmm_u_cmm_cfgspace_low_addr_01_7_0_bm_27__5682; + wire com_cmm_u_cmm_cfgspace_low_addr_01_7_0_am_27__5683; + wire com_cmm_u_cmm_cfgspace_N_63600; + wire com_cmm_u_cmm_cfgspace_N_3758; + wire com_cmm_u_cmm_cfgspace_low_addr_01_7_0_bm_28__5684; + wire com_cmm_u_cmm_cfgspace_low_addr_01_7_0_am_28__5685; + wire com_cmm_u_cmm_cfgspace_N_63601; + wire com_cmm_u_cmm_cfgspace_N_3759; + wire com_cmm_u_cmm_cfgspace_low_addr_01_7_0_bm_29__5686; + wire com_cmm_u_cmm_cfgspace_low_addr_01_7_0_am_29__5687; + wire com_cmm_u_cmm_cfgspace_N_63602; + wire com_cmm_u_cmm_cfgspace_N_3760; + wire com_cmm_u_cmm_cfgspace_low_addr_01_7_0_bm_30__5688; + wire com_cmm_u_cmm_cfgspace_low_addr_01_7_0_am_30__5689; + wire com_cmm_u_cmm_cfgspace_N_63603; + wire com_cmm_u_cmm_cfgspace_N_61397; + wire com_cmm_u_cmm_cfgspace_N_3761; + wire com_cmm_u_cmm_cfgspace_low_addr_01_7_0_bm_31__5690; + wire com_cmm_u_cmm_cfgspace_low_addr_01_7_0_am_31__5691; + wire com_cmm_u_cmm_cfgspace_N_61371; + wire com_cmm_u_cmm_cfgspace_N_57265; + wire com_cmm_u_cmm_cfgspace_N_57264_2; + wire com_cmm_u_cmm_cfgspace_N_57263; + wire com_cmm_u_cmm_cfgspace_N_57261; + wire com_cmm_u_cmm_cfgspace_N_57260_2; + wire com_cmm_u_cmm_cfgspace_N_57259; + wire com_cmm_u_cmm_cfgspace_N_58589_2; + wire com_cmm_u_cmm_cfgspace_N_57266_1; + wire com_cmm_u_cmm_cfgspace_N_57257; + wire com_cmm_u_cmm_cfgspace_sel_0x_3_0_0_0_0_0; + wire com_cmm_u_cmm_cfgspace_N_61378; + wire com_cmm_u_cmm_cfgspace_N_57266; + wire com_cmm_u_cmm_cfgspace_N_56350_i; + wire com_cmm_u_cmm_cfgspace_sel_x4_3_i_0_0_o3; + wire com_cmm_u_cmm_cfgspace_sel_x0_3_i_0_0_o3; + wire com_cmm_u_cmm_cfgspace_N_59237_1; + wire com_cmm_u_cmm_cfgspace_N_55900; + wire com_cmm_u_cmm_cfgspace_N_63569; + wire com_cmm_u_cmm_cfgspace_N_63539; + wire com_cmm_u_cmm_cfgspace_N_63568; + wire com_cmm_u_cmm_cfgspace_N_63538; + wire com_cmm_u_cmm_cfgspace_N_58586_1; + wire com_cmm_u_cmm_cfgspace_N_58304_1; + wire com_cmm_u_cmm_cfgspace_N_58308_1; + wire com_cmm_u_cmm_cfgspace_N_56069_i; + wire com_cmm_u_cmm_cfgspace_N_56067_i; + wire com_cmm_u_cmm_cfgspace_N_57085; + wire com_cmm_u_cmm_cfgspace_N_55990_i; + wire com_cmm_u_cmm_cfgspace_N_86826_i_5692; + wire com_cmm_u_cmm_cfgspace_N_86827_i_5693; + wire com_cmm_u_cmm_cfgspace_N_55962_i; + wire com_cmm_u_cmm_cfgspace_N_55961_i; + wire com_cmm_u_cmm_cfgspace_N_56033_i; + wire com_cmm_u_cmm_cfgspace_N_25331_i; + wire com_cmm_u_cmm_cfgspace_low_addr_00_i_0_0_0_31_39355_5694; + wire com_cmm_u_cmm_cfgspace_N_59010; + wire com_cmm_u_cmm_cfgspace_N_85969_i_5695; + wire com_cmm_u_cmm_cfgspace_N_25327_i; + wire com_cmm_u_cmm_cfgspace_low_addr_00_i_0_0_0_28_39360_5696; + wire com_cmm_u_cmm_cfgspace_N_59004; + wire com_cmm_u_cmm_cfgspace_N_19325_i; + wire com_cmm_u_cmm_cfgspace_low_addr_00_i_0_0_0_27_39365_5697; + wire com_cmm_u_cmm_cfgspace_N_61336; + wire com_cmm_u_cmm_cfgspace_N_58666; + wire com_cmm_u_cmm_cfgspace_N_85939_i_5698; + wire com_cmm_u_cmm_cfgspace_low_addr_00_0_0_1_21__5699; + wire com_cmm_u_cmm_cfgspace_low_addr_00_0_0_0_21__5700; + wire com_cmm_u_cmm_cfgspace_N_58005; + wire com_cmm_u_cmm_cfgspace_N_85978_i_5701; + wire com_cmm_u_cmm_cfgspace_N_59581; + wire com_cmm_u_cmm_cfgspace_N_85977_i_5702; + wire com_cmm_u_cmm_cfgspace_N_59574; + wire com_cmm_u_cmm_cfgspace_N_85976_i_5703; + wire com_cmm_u_cmm_cfgspace_N_59567; + wire com_cmm_u_cmm_cfgspace_N_17891_i; + wire com_cmm_u_cmm_cfgspace_low_addr_00_i_0_0_0_2_16__5704; + wire com_cmm_u_cmm_cfgspace_low_addr_00_i_0_0_0_1_16__5705; + wire com_cmm_u_cmm_cfgspace_N_58548; + wire com_cmm_u_cmm_cfgspace_N_58545; + wire com_cmm_u_cmm_cfgspace_N_40020_i; + wire com_cmm_u_cmm_cfgspace_low_addr_00_i_0_15_39329_5706; + wire com_cmm_u_cmm_cfgspace_low_addr_00_i_0_15_39328_5707; + wire com_cmm_u_cmm_cfgspace_N_85938_i_5708; + wire com_cmm_u_cmm_cfgspace_low_addr_00_0_0_0_1_14__5709; + wire com_cmm_u_cmm_cfgspace_N_85937_i_5710; + wire com_cmm_u_cmm_cfgspace_low_addr_00_0_0_0_1_13__5711; + wire com_cmm_u_cmm_cfgspace_low_addr_00_0_0_0_0_13__5712; + wire com_cmm_u_cmm_cfgspace_N_85936_i_5713; + wire com_cmm_u_cmm_cfgspace_N_85935_i_5714; + wire com_cmm_u_cmm_cfgspace_N_85934_i_5715; + wire com_cmm_u_cmm_cfgspace_low_addr_00_0_0_0_1_10__5716; + wire com_cmm_u_cmm_cfgspace_low_addr_00_0_0_0_0_10__5717; + wire com_cmm_u_cmm_cfgspace_N_85933_i_5718; + wire com_cmm_u_cmm_cfgspace_low_addr_00_0_0_0_1_9__5719; + wire com_cmm_u_cmm_cfgspace_low_addr_00_0_0_0_0_9__5720; + wire com_cmm_u_cmm_cfgspace_N_85932_i_5721; + wire com_cmm_u_cmm_cfgspace_low_addr_00_0_0_1_8__5722; + wire com_cmm_u_cmm_cfgspace_low_addr_00_0_0_0_8__5723; + wire com_cmm_u_cmm_cfgspace_N_85931_i_5724; + wire com_cmm_u_cmm_cfgspace_low_addr_00_0_0_1_7__5725; + wire com_cmm_u_cmm_cfgspace_low_addr_00_0_0_0_7__5726; + wire com_cmm_u_cmm_cfgspace_N_85930_i_5727; + wire com_cmm_u_cmm_cfgspace_low_addr_00_0_0_1_6__5728; + wire com_cmm_u_cmm_cfgspace_low_addr_00_0_0_0_6__5729; + wire com_cmm_u_cmm_cfgspace_N_85929_i_5730; + wire com_cmm_u_cmm_cfgspace_low_addr_00_0_0_1_5__5731; + wire com_cmm_u_cmm_cfgspace_low_addr_00_0_0_0_5__5732; + wire com_cmm_u_cmm_cfgspace_N_85928_i_5733; + wire com_cmm_u_cmm_cfgspace_low_addr_00_0_0_0_1_4__5734; + wire com_cmm_u_cmm_cfgspace_low_addr_00_0_0_0_0_4__5735; + wire com_cmm_u_cmm_cfgspace_N_85927_i_5736; + wire com_cmm_u_cmm_cfgspace_low_addr_00_0_0_1_3__5737; + wire com_cmm_u_cmm_cfgspace_low_addr_00_0_0_0_3__5738; + wire com_cmm_u_cmm_cfgspace_N_85926_i_5739; + wire com_cmm_u_cmm_cfgspace_low_addr_00_0_0_0_1_2__5740; + wire com_cmm_u_cmm_cfgspace_low_addr_00_0_0_0_0_2__5741; + wire com_cmm_u_cmm_cfgspace_N_40005_i; + wire com_cmm_u_cmm_cfgspace_low_addr_00_i_0_1_39299_5742; + wire com_cmm_u_cmm_cfgspace_low_addr_00_i_0_1_39298_5743; + wire com_cmm_u_cmm_cfgspace_N_59538_1; + wire com_cmm_u_cmm_cfgspace_N_25682_i; + wire com_cmm_u_cmm_cfgspace_low_addr_00_i_0_0_0_2_0__5744; + wire com_cmm_u_cmm_cfgspace_low_addr_00_i_0_0_0_1_0__5745; + wire com_cmm_u_cmm_cfgspace_N_4754; + wire com_cmm_u_cmm_cfgspace_N_4658; + wire com_cmm_u_cmm_cfgspace_N_4752; + wire com_cmm_u_cmm_cfgspace_N_4656; + wire com_cmm_u_cmm_cfgspace_N_4750; + wire com_cmm_u_cmm_cfgspace_N_4654; + wire com_cmm_u_cmm_cfgspace_N_4749; + wire com_cmm_u_cmm_cfgspace_N_4653; + wire com_cmm_u_cmm_cfgspace_N_85958_i_5746; + wire com_cmm_u_cmm_cfgspace_sel_encodex_en_3_i_0_0_0_0_5747; + wire com_cmm_u_cmm_cfgspace_N_58591; + wire com_cmm_u_cmm_cfgspace_N_58589; + wire com_cmm_u_cmm_cfgspace_N_58588; + wire com_cmm_u_cmm_cfgspace_N_3900; + wire com_cmm_u_cmm_cfgspace_N_3804; + wire com_cmm_u_cmm_cfgspace_N_3890; + wire com_cmm_u_cmm_cfgspace_N_3794; + wire com_cmm_u_cmm_cfgspace_low_addr_00_i_0_20_39323_5748; + wire com_cmm_u_cmm_cfgspace_low_addr_00_i_0_22_39318_5749; + wire com_cmm_u_cmm_cfgspace_low_addr_00_i_0_0_23_39342_5750; + wire com_cmm_u_cmm_cfgspace_low_addr_00_i_0_24_39313_5751; + wire com_cmm_u_cmm_cfgspace_low_addr_00_i_0_0_25_39337_5752; + wire com_cmm_u_cmm_cfgspace_low_addr_00_i_0_0_26_39332_5753; + wire com_cmm_u_cmm_cfgspace_low_addr_00_i_0_0_30_39347_5754; + wire com_cmm_u_cmm_cfgspace_N_61340; + wire com_cmm_u_cmm_cfgspace_N_58663; + wire com_cmm_u_cmm_cfgspace_N_86243_i_5755; + wire com_cmm_u_cmm_cfgspace_N_86824_i_5756; + wire com_cmm_u_cmm_cfgspace_N_86244_i_5757; + wire com_cmm_u_cmm_cfgspace_N_86825_i_5758; + wire com_cmm_u_cmm_cfgspace_sel_encodex_en_3_i_0_0_0_o3_0_5759; + wire com_cmm_u_cmm_cfgspace_N_61356; + wire com_cmm_u_cmm_cfgspace_N_61360; + wire com_cmm_u_cmm_cfgspace_N_61350; + wire com_cmm_u_cmm_cfgspace_N_61290_1; + wire com_cmm_u_cmm_cfgspace_N_58591_1; + wire com_cmm_u_cmm_cfgspace_N_57206; + wire com_cmm_u_cmm_cfgspace_N_55879_i; + wire com_cmm_u_cmm_cfgspace_N_55870_i; + wire com_cmm_u_cmm_cfgspace_N_55912_i; + wire com_cmm_u_cmm_cfgspace_N_57892_1; + wire com_cmm_u_cmm_cfgspace_N_56070_i; + wire com_cmm_u_cmm_cfgspace_N_57880_1; + wire com_cmm_u_cmm_cfgspace_N_55892_i; + wire com_cmm_u_cmm_cfgspace_N_56071_i; + wire com_cmm_u_cmm_cfgspace_N_57916_1; + wire com_cmm_u_cmm_cfgspace_N_55910_i; + wire com_cmm_u_cmm_cfgspace_N_56068_i; + wire com_cmm_u_cmm_cfgspace_set_detectedcorrectable_5760; + wire com_cmm_u_cmm_cfgspace_set_signaledtargetabort_5761; + wire com_cmm_u_cmm_cfgspace_set_signaledsystemerror_5762; + wire com_cmm_u_cmm_cfgspace_set_signaledpme_5763; + wire com_cmm_u_cmm_cfgspace_set_receivedtargetabort_5764; + wire com_cmm_u_cmm_cfgspace_set_receivedmasterabort_5765; + wire com_cmm_u_cmm_cfgspace_set_masterdataparityerror_5766; + wire com_cmm_u_cmm_cfgspace_set_detectedparityerror_5767; + wire com_cmm_u_cmm_cfgspace_set_unsupportedreq_5768; + wire com_cmm_u_cmm_cfgspace_set_detectednonfatal_5769; + wire com_cmm_u_cmm_cfgspace_set_detectedfatal_5770; + wire com_cmm_u_cmm_cfgspace_N_86820_i; + wire com_cmm_u_cmm_cfgspace_sel_5x_5771; + wire com_cmm_u_cmm_cfgspace_N_86821_i; + wire com_cmm_u_cmm_cfgspace_sel_4x_5772; + wire com_cmm_u_cmm_cfgspace_N_86822_i; + wire com_cmm_u_cmm_cfgspace_sel_3x_5773; + wire com_cmm_u_cmm_cfgspace_N_86266_i; + wire com_cmm_u_cmm_cfgspace_sel_2x_5774; + wire com_cmm_u_cmm_cfgspace_N_86823_i; + wire com_cmm_u_cmm_cfgspace_sel_1x_5775; + wire com_cmm_u_cmm_cfgspace_N_85811_i; + wire com_cmm_u_cmm_cfgspace_sel_0x_5776; + wire com_cmm_u_cmm_cfgspace_N_86819_i; + wire com_cmm_u_cmm_cfgspace_sel_6x_5777; + wire com_cmm_u_cmm_cfgspace_N_33690_i; + wire com_cmm_u_cmm_cfgspace_sel_xa_5778; + wire com_cmm_u_cmm_cfgspace_N_33688_i; + wire com_cmm_u_cmm_cfgspace_sel_x9_5779; + wire com_cmm_u_cmm_cfgspace_N_33686_i; + wire com_cmm_u_cmm_cfgspace_sel_x8_5780; + wire com_cmm_u_cmm_cfgspace_N_33684_i; + wire com_cmm_u_cmm_cfgspace_sel_x7_5781; + wire com_cmm_u_cmm_cfgspace_N_33682_i; + wire com_cmm_u_cmm_cfgspace_sel_x6_5782; + wire com_cmm_u_cmm_cfgspace_N_33680_i; + wire com_cmm_u_cmm_cfgspace_sel_x5_5783; + wire com_cmm_u_cmm_cfgspace_N_33678_i; + wire com_cmm_u_cmm_cfgspace_sel_x4_5784; + wire com_cmm_u_cmm_cfgspace_N_33676_i; + wire com_cmm_u_cmm_cfgspace_sel_x3_5785; + wire com_cmm_u_cmm_cfgspace_N_33674_i; + wire com_cmm_u_cmm_cfgspace_sel_x2_5786; + wire com_cmm_u_cmm_cfgspace_N_33672_i; + wire com_cmm_u_cmm_cfgspace_sel_x1_5787; + wire com_cmm_u_cmm_cfgspace_N_33670_i; + wire com_cmm_u_cmm_cfgspace_sel_x0_5788; + wire com_cmm_u_cmm_cfgspace_N_33700_i; + wire com_cmm_u_cmm_cfgspace_sel_xf_5789; + wire com_cmm_u_cmm_cfgspace_N_33698_i; + wire com_cmm_u_cmm_cfgspace_sel_xe_5790; + wire com_cmm_u_cmm_cfgspace_N_33696_i; + wire com_cmm_u_cmm_cfgspace_sel_xd_5791; + wire com_cmm_u_cmm_cfgspace_N_33694_i; + wire com_cmm_u_cmm_cfgspace_sel_xc_5792; + wire com_cmm_u_cmm_cfgspace_N_33692_i; + wire com_cmm_u_cmm_cfgspace_sel_xb_5793; + wire com_cmm_u_cmm_cfgspace_N_17863_i; + wire com_cmm_u_cmm_cfgspace_N_17861_i; + wire com_cmm_u_cmm_cfgspace_N_9940_i; + wire com_cmm_u_cmm_cfgspace_N_9939_i; + wire com_cmm_u_cmm_cfgspace_N_9938_i; + wire com_cmm_u_cmm_cfgspace_N_9937_i; + wire com_cmm_u_cmm_cfgspace_N_9951_i; + wire com_cmm_u_cmm_cfgspace_set_signaledint_5794; + wire com_cmm_u_cmm_cfgspace_N_9950_i; + wire com_cmm_u_cmm_cfgspace_N_35656_i; + wire com_cmm_u_cmm_cfgspace_N_39977_i; + wire com_cmm_u_cmm_cfgspace_N_39975_i; + wire com_cmm_u_cmm_cfgspace_N_35654_i; + wire com_cmm_u_cmm_cfgspace_N_85866_i; + wire com_cmm_u_cmm_cfgspace_N_85865_i; + wire com_cmm_u_cmm_cfgspace_state_5__5795; + wire com_cmm_u_cmm_cfgspace_N_33655_i; + wire com_cmm_u_cmm_cfgspace_state_4__5796; + wire com_cmm_u_cmm_cfgspace_state_2__5797; + wire com_cmm_u_cmm_cfgspace_N_18655_i; + wire com_cmm_u_cmm_cfgspace_state_1__5798; + wire com_cmm_u_cmm_cfgspace_N_85892_i_5799; + wire com_cmm_u_cmm_cfgspace_state_0__5800; + wire com_cmm_u_cmm_cfgspace_set_transaction_pending_5801; + wire com_cmm_u_cmm_cfgspace_N_9949_i; + wire com_cmm_u_cmm_cfgspace_N_9948_i; + wire com_cmm_u_cmm_cfgspace_N_9947_i; + wire com_cmm_u_cmm_cfgspace_N_9946_i; + wire com_cmm_u_cmm_cfgspace_N_9941_i; + wire com_cmm_u_cmm_cfgspace_bar1_reg45; + wire com_cmm_u_cmm_cfgspace_N_55972_i; + wire com_cmm_u_cmm_cfgspace_N_85868_i; + wire com_cmm_u_cmm_cfgspace_N_85867_i; + wire com_cmm_u_cmm_cfgspace_bar1_reg70; + wire com_cmm_u_cmm_cfgspace_bar1_reg58; + wire com_cmm_u_cmm_cfgspace_N_55973_i; + wire com_cmm_u_cmm_cfgspace_N_85872_i; + wire com_cmm_u_cmm_cfgspace_N_85871_i; + wire com_cmm_u_cmm_cfgspace_N_85870_i; + wire com_cmm_u_cmm_cfgspace_N_85869_i; + wire com_cmm_u_cmm_cfgspace_bar2_reg58; + wire com_cmm_u_cmm_cfgspace_bar2_reg45; + wire com_cmm_u_cmm_cfgspace_N_55974_i; + wire com_cmm_u_cmm_cfgspace_N_85876_i; + wire com_cmm_u_cmm_cfgspace_N_85875_i; + wire com_cmm_u_cmm_cfgspace_N_85874_i; + wire com_cmm_u_cmm_cfgspace_N_85873_i; + wire com_cmm_u_cmm_cfgspace_bar2_reg70; + wire com_cmm_u_cmm_cfgspace_bar3_reg58; + wire com_cmm_u_cmm_cfgspace_bar3_reg45; + wire com_cmm_u_cmm_cfgspace_N_55970_i; + wire com_cmm_u_cmm_cfgspace_N_85880_i; + wire com_cmm_u_cmm_cfgspace_N_85879_i; + wire com_cmm_u_cmm_cfgspace_N_85878_i; + wire com_cmm_u_cmm_cfgspace_N_85877_i; + wire com_cmm_u_cmm_cfgspace_bar3_reg70; + wire com_cmm_u_cmm_cfgspace_bar4_reg58; + wire com_cmm_u_cmm_cfgspace_bar4_reg45; + wire com_cmm_u_cmm_cfgspace_N_55971_i; + wire com_cmm_u_cmm_cfgspace_N_85884_i; + wire com_cmm_u_cmm_cfgspace_N_85883_i; + wire com_cmm_u_cmm_cfgspace_N_85882_i; + wire com_cmm_u_cmm_cfgspace_N_85881_i; + wire com_cmm_u_cmm_cfgspace_bar4_reg70; + wire com_cmm_u_cmm_cfgspace_bar5_reg58; + wire com_cmm_u_cmm_cfgspace_bar5_reg45; + wire com_cmm_u_cmm_cfgspace_N_40410_i; + wire com_cmm_u_cmm_cfgspace_N_40408_i; + wire com_cmm_u_cmm_cfgspace_N_86401_i_5802; + wire com_cmm_u_cmm_cfgspace_N_40001_i; + wire com_cmm_u_cmm_cfgspace_N_17888_i; + wire com_cmm_u_cmm_cfgspace_N_17886_i; + wire com_cmm_u_cmm_cfgspace_N_17884_i; + wire com_cmm_u_cmm_cfgspace_bar5_reg70; + wire com_cmm_u_cmm_cfgspace_N_35664_i; + wire com_cmm_u_cmm_cfgspace_N_86412_i_5803; + wire com_cmm_u_cmm_cfgspace_N_35662_i; + wire com_cmm_u_cmm_cfgspace_N_86410_i_5804; + wire com_cmm_u_cmm_cfgspace_x_dcmd_1_sqmuxa_1; + wire com_cmm_u_cmm_cfgspace_N_35660_i; + wire com_cmm_u_cmm_cfgspace_N_40003_i; + wire com_cmm_u_cmm_cfgspace_N_40412_i; + wire com_cmm_u_cmm_cfgspace_bar0_reg31; + wire com_cmm_u_cmm_cfgspace_bar0_reg18; + wire com_cmm_u_cmm_cfgspace_bar0_reg56; + wire com_cmm_u_cmm_cfgspace_bar0_reg44; + wire com_cmm_u_cmm_cfgspace_msi_laddr28; + wire com_cmm_u_cmm_cfgspace_msi_laddr16; + wire com_cmm_u_cmm_cfgspace_msi_laddr51; + wire com_cmm_u_cmm_cfgspace_msi_laddr40; + wire com_cmm_u_cmm_cfgspace_msi_haddr23; + wire com_cmm_u_cmm_cfgspace_msi_haddr12; + wire com_cmm_u_cmm_cfgspace_msi_haddr46; + wire com_cmm_u_cmm_cfgspace_msi_haddr35; + wire com_cmm_u_cmm_cfgspace_msi_data22; + wire com_cmm_u_cmm_cfgspace_msi_data12; + wire com_cmm_u_cmm_cfgspace_command93; + wire com_cmm_u_cmm_cfgspace_command67; + wire com_cmm_u_cmm_cfgspace_x_lcmd22; + wire com_cmm_u_cmm_cfgspace_VCC_5805; + wire com_cmm_u_cmm_cfgspace_set_negotiatedwidth_2__5806; + wire com_cmm_u_cmm_cfgspace_set_negotiatedwidth_0__5807; + wire com_cmm_u_cmm_cfgspace_cache_line8; + wire com_cmm_u_cmm_cfgspace_int_line8; + wire com_cmm_u_cmm_cfgspace_msi_control27; + wire com_cmm_u_cmm_cfgspace_xrom_reg_0_sqmuxa; + wire com_cmm_u_cmm_cfgspace_N_86265_i; + wire com_cmm_u_cmm_cfgspace_N_86264_i; + wire com_cmm_u_cmm_cfgspace_N_86263_i; + wire com_cmm_u_cmm_cfgspace_N_86262_i; + wire com_cmm_u_cmm_cfgspace_N_86261_i; + wire com_cmm_u_cmm_cfgspace_N_86260_i; + wire com_cmm_u_cmm_cfgspace_N_86259_i; + wire com_cmm_u_cmm_cfgspace_N_86258_i; + wire com_cmm_u_cmm_cfgspace_N_86257_i; + wire com_cmm_u_cmm_cfgspace_N_86256_i; + wire com_cmm_u_cmm_cfgspace_N_86255_i; + wire com_cmm_u_cmm_cfgspace_N_86254_i; + wire com_cmm_u_cmm_cfgspace_N_86253_i; + wire com_cmm_u_cmm_cfgspace_N_86252_i; + wire com_cmm_u_cmm_cfgspace_N_86251_i; + wire com_cmm_u_cmm_cfgspace_N_86250_i; + wire com_cmm_u_cmm_cfgspace_N_86249_i; + wire com_cmm_u_cmm_cfgspace_N_86248_i; + wire com_cmm_u_cmm_cfgspace_N_86247_i; + wire com_cmm_u_cmm_cfgspace_N_86246_i; + wire com_cmm_u_cmm_cfgspace_N_86245_i; + wire com_cmm_u_cmm_cfgspace_cfg2ulm_valid; + wire com_cmm_u_cmm_cfgspace_N_33956_i; + wire com_cmm_u_cmm_cfgspace_low_addr_00_i_0_0_1_30__5808; + wire com_cmm_u_cmm_cfgspace_low_addr_00_i_0_0_30_39348_5809; + wire com_cmm_u_cmm_cfgspace_N_35672_i; + wire com_cmm_u_cmm_cfgspace_low_addr_00_i_0_0_1_26__5810; + wire com_cmm_u_cmm_cfgspace_low_addr_00_i_0_0_26_39333_5811; + wire com_cmm_u_cmm_cfgspace_N_35670_i; + wire com_cmm_u_cmm_cfgspace_low_addr_00_i_0_0_1_25__5812; + wire com_cmm_u_cmm_cfgspace_low_addr_00_i_0_0_25_39338_5813; + wire com_cmm_u_cmm_cfgspace_N_40027_i; + wire com_cmm_u_cmm_cfgspace_low_addr_00_i_0_1_24__5814; + wire com_cmm_u_cmm_cfgspace_low_addr_00_i_0_24_39314_5815; + wire com_cmm_u_cmm_cfgspace_N_35668_i; + wire com_cmm_u_cmm_cfgspace_low_addr_00_i_0_0_1_23__5816; + wire com_cmm_u_cmm_cfgspace_low_addr_00_i_0_0_23_39343_5817; + wire com_cmm_u_cmm_cfgspace_N_40025_i; + wire com_cmm_u_cmm_cfgspace_low_addr_00_i_0_1_22__5818; + wire com_cmm_u_cmm_cfgspace_low_addr_00_i_0_22_39319_5819; + wire com_cmm_u_cmm_cfgspace_N_40022_i; + wire com_cmm_u_cmm_cfgspace_low_addr_00_i_0_1_20__5820; + wire com_cmm_u_cmm_cfgspace_low_addr_00_i_0_20_39324_5821; + wire com_cmm_u_cmm_cfgspace_N_61330; + wire com_cmm_u_cmm_errman_cplu_add_sub_b; + wire com_cmm_u_cmm_errman_cplt_add_sub_b; + wire com_cmm_u_cmm_errman_ftl_add_sub_b; + wire com_cmm_u_cmm_errman_nfl_add_sub_b; + wire com_cmm_u_cmm_errman_cor_add_sub_b; + wire com_cmm_u_cmm_errman_to_incr_0ro; + wire com_cmm_u_cmm_errman_reg_decr_nfl; + wire com_cmm_u_cmm_errman_reg_decr_cor; + wire com_cmm_u_cmm_errman_to_incr_2ro; + wire com_cmm_u_cmm_errman_to_incr_1ro; + wire com_cmm_u_cmm_errman_nfl_num_c1_5822; + wire com_cmm_u_cmm_errman_un1_reg_uflow_3_1; + wire com_cmm_u_cmm_errman_send_ftl_3_0_a2_5823; + wire com_cmm_u_cmm_errman_un1_reg_uflow_3_0; + wire com_cmm_u_cmm_errman_un1_reg_uflow_3; + wire com_cmm_u_cmm_errman_send_cor_3_0_a2_5824; + wire com_cmm_u_cmm_errman_reg_detectednonfatal_3_i_0_1_5825; + wire com_cmm_u_cmm_errman_reg_detectedcorrectable_3_i_0_0_0_3_5826; + wire com_cmm_u_cmm_errman_reg_detectedcorrectable_3_i_0_0_0_a2_0_5827; + wire com_cmm_u_cmm_errman_N_56208_i; + wire com_cmm_u_cmm_errman_N_56322_i; + wire com_cmm_u_cmm_errman_N_58733; + wire com_cmm_u_cmm_errman_N_58731; + wire com_cmm_u_cmm_errman_N_56493_i; + wire com_cmm_u_cmm_errman_N_58735_1; + wire com_cmm_u_cmm_errman_N_56317_i; + wire com_cmm_u_cmm_errman_N_55917_i; + wire com_cmm_u_cmm_errman_N_62516; + wire com_cmm_u_cmm_errman_N_58392_i_5828; + wire com_cmm_u_cmm_errman_reg_detectedcorrectable_3_i_0_0_0_a2_5829; + wire com_cmm_u_cmm_errman_replay_vld_i_5830; + wire com_cmm_u_cmm_errman_N_19038_i; + wire com_cmm_u_cmm_errman_N_86726_i_5831; + wire com_cmm_u_cmm_errman_N_58592; + wire com_cmm_u_cmm_errman_N_86392_i_5832; + wire com_cmm_u_cmm_errman_N_86391_i_5833; + wire com_cmm_u_cmm_errman_request_data31; + wire com_cmm_u_cmm_errman_request_data30; + wire com_cmm_u_cmm_errman_cs_is_ftl_5834; + wire com_cmm_u_cmm_errman_request_data28; + wire com_cmm_u_cmm_errman_cs_is_cplu_5835; + wire com_cmm_u_cmm_errman_N_20280_i_0; + wire com_cmm_u_cmm_errman_cs_is_cplt_5836; + wire com_cmm_u_cmm_errman_request_data32; + wire com_cmm_u_cmm_errman_cs_is_cor_5837; + wire com_cmm_u_cmm_errman_cfg_is_np_and_cpl_abort; + wire com_cmm_u_cmm_errman_N_86725_i_5838; + wire com_cmm_u_cmm_errman_reg_masterdataparityerror_3_5839; + wire com_cmm_u_cmm_errman_un1_reg_uflow_3_i_1_5840; + wire com_cmm_u_cmm_errman_send_nfl_5841; + wire com_cmm_u_cmm_errman_N_62936_i_5842; + wire com_cmm_u_cmm_errman_send_ftl_5843; + wire com_cmm_u_cmm_errman_un1_reg_uflow_3_i_0_5844; + wire com_cmm_u_cmm_errman_send_cplu_5845; + wire com_cmm_u_cmm_errman_un1_reg_uflow_3_i_5846; + wire com_cmm_u_cmm_errman_send_cplt_5847; + wire com_cmm_u_cmm_errman_N_62928_i_5848; + wire com_cmm_u_cmm_errman_send_cor_5849; + wire com_cmm_u_cmm_errman_N_74_2_i; + wire com_cmm_u_cmm_errman_N_85959_i_5850; + wire com_cmm_u_cmm_errman_N_85494_i_5851; + wire com_cmm_u_cmm_errman_N_59526; + wire com_cmm_u_cmm_errman_reg_incr_cplu_5852; + wire com_cmm_u_cmm_errman_N_86299_i_5853; + wire com_cmm_u_cmm_errman_N_86298_i_5854; + wire com_cmm_u_cmm_errman_N_86297_i_5855; + wire com_cmm_u_cmm_errman_N_86314_i_5856; + wire com_cmm_u_cmm_errman_N_86313_i_5857; + wire com_cmm_u_cmm_errman_N_86312_i_5858; + wire com_cmm_u_cmm_errman_N_86311_i_5859; + wire com_cmm_u_cmm_errman_N_86310_i_5860; + wire com_cmm_u_cmm_errman_N_86309_i_5861; + wire com_cmm_u_cmm_errman_N_86308_i_5862; + wire com_cmm_u_cmm_errman_N_86307_i_5863; + wire com_cmm_u_cmm_errman_N_86306_i_5864; + wire com_cmm_u_cmm_errman_N_86305_i_5865; + wire com_cmm_u_cmm_errman_N_86304_i_5866; + wire com_cmm_u_cmm_errman_N_86303_i_5867; + wire com_cmm_u_cmm_errman_N_86302_i_5868; + wire com_cmm_u_cmm_errman_N_86301_i_5869; + wire com_cmm_u_cmm_errman_N_86300_i_5870; + wire com_cmm_u_cmm_errman_N_86329_i_5871; + wire com_cmm_u_cmm_errman_N_86328_i_5872; + wire com_cmm_u_cmm_errman_N_86327_i_5873; + wire com_cmm_u_cmm_errman_N_86326_i_5874; + wire com_cmm_u_cmm_errman_N_86325_i_5875; + wire com_cmm_u_cmm_errman_N_86324_i_5876; + wire com_cmm_u_cmm_errman_N_86323_i_5877; + wire com_cmm_u_cmm_errman_N_86322_i_5878; + wire com_cmm_u_cmm_errman_N_86321_i_5879; + wire com_cmm_u_cmm_errman_N_86320_i_5880; + wire com_cmm_u_cmm_errman_N_86319_i_5881; + wire com_cmm_u_cmm_errman_N_86318_i_5882; + wire com_cmm_u_cmm_errman_N_86317_i_5883; + wire com_cmm_u_cmm_errman_N_86316_i_5884; + wire com_cmm_u_cmm_errman_N_86315_i_5885; + wire com_cmm_u_cmm_errman_N_86344_i_5886; + wire com_cmm_u_cmm_errman_N_86343_i_5887; + wire com_cmm_u_cmm_errman_N_86342_i_5888; + wire com_cmm_u_cmm_errman_N_86341_i_5889; + wire com_cmm_u_cmm_errman_N_86340_i_5890; + wire com_cmm_u_cmm_errman_N_86339_i_5891; + wire com_cmm_u_cmm_errman_N_86338_i_5892; + wire com_cmm_u_cmm_errman_N_86337_i_5893; + wire com_cmm_u_cmm_errman_N_86336_i_5894; + wire com_cmm_u_cmm_errman_N_86335_i_5895; + wire com_cmm_u_cmm_errman_N_86334_i_5896; + wire com_cmm_u_cmm_errman_N_86333_i_5897; + wire com_cmm_u_cmm_errman_N_86332_i_5898; + wire com_cmm_u_cmm_errman_N_86331_i_5899; + wire com_cmm_u_cmm_errman_N_86330_i_5900; + wire com_cmm_u_cmm_errman_N_39843_i; + wire com_cmm_u_cmm_errman_N_39841_i; + wire com_cmm_u_cmm_errman_un1_cs_fsm_1_0_a2_0_a2_5901; + wire com_cmm_u_cmm_errman_N_85896_i_5902; + wire com_cmm_u_cmm_errman_N_85897_i_5903; + wire com_cmm_u_cmm_errman_N_85997_i_5904; + wire com_cmm_u_cmm_errman_N_86360_i_5905; + wire com_cmm_u_cmm_errman_N_86399_i_5906; + wire com_cmm_u_cmm_errman_N_86398_i_5907; + wire com_cmm_u_cmm_errman_N_86346_i_5908; + wire com_cmm_u_cmm_errman_N_86345_i_5909; + wire com_cmm_u_cmm_errman_N_39873_i; + wire com_cmm_u_cmm_errman_N_39871_i; + wire com_cmm_u_cmm_errman_N_39869_i; + wire com_cmm_u_cmm_errman_N_39867_i; + wire com_cmm_u_cmm_errman_N_39865_i; + wire com_cmm_u_cmm_errman_N_39863_i; + wire com_cmm_u_cmm_errman_N_39861_i; + wire com_cmm_u_cmm_errman_N_39859_i; + wire com_cmm_u_cmm_errman_N_39857_i; + wire com_cmm_u_cmm_errman_N_39855_i; + wire com_cmm_u_cmm_errman_N_39853_i; + wire com_cmm_u_cmm_errman_N_39851_i; + wire com_cmm_u_cmm_errman_N_39849_i; + wire com_cmm_u_cmm_errman_N_39847_i; + wire com_cmm_u_cmm_errman_N_39845_i; + wire com_cmm_u_cmm_errman_N_39903_i; + wire com_cmm_u_cmm_errman_N_39901_i; + wire com_cmm_u_cmm_errman_N_39899_i; + wire com_cmm_u_cmm_errman_N_39897_i; + wire com_cmm_u_cmm_errman_N_39895_i; + wire com_cmm_u_cmm_errman_N_39893_i; + wire com_cmm_u_cmm_errman_N_39891_i; + wire com_cmm_u_cmm_errman_N_39889_i; + wire com_cmm_u_cmm_errman_N_39887_i; + wire com_cmm_u_cmm_errman_N_39885_i; + wire com_cmm_u_cmm_errman_N_39883_i; + wire com_cmm_u_cmm_errman_N_39881_i; + wire com_cmm_u_cmm_errman_N_39879_i; + wire com_cmm_u_cmm_errman_N_39877_i; + wire com_cmm_u_cmm_errman_N_39875_i; + wire com_cmm_u_cmm_errman_N_39933_i; + wire com_cmm_u_cmm_errman_N_39931_i; + wire com_cmm_u_cmm_errman_N_39929_i; + wire com_cmm_u_cmm_errman_N_39927_i; + wire com_cmm_u_cmm_errman_N_39925_i; + wire com_cmm_u_cmm_errman_N_39923_i; + wire com_cmm_u_cmm_errman_N_39921_i; + wire com_cmm_u_cmm_errman_N_39919_i; + wire com_cmm_u_cmm_errman_N_39917_i; + wire com_cmm_u_cmm_errman_N_39915_i; + wire com_cmm_u_cmm_errman_N_39913_i; + wire com_cmm_u_cmm_errman_N_39911_i; + wire com_cmm_u_cmm_errman_N_39909_i; + wire com_cmm_u_cmm_errman_N_39907_i; + wire com_cmm_u_cmm_errman_N_39905_i; + wire com_cmm_u_cmm_errman_reg_cfg_wr_hdr20; + wire com_cmm_u_cmm_errman_cfg_is_np_and_ur; + wire com_cmm_u_cmm_errman_N_39935_i; + wire com_cmm_u_cmm_errman_N_55916_i; + wire com_cmm_u_cmm_errman_N_39937_i; + wire com_cmm_u_cmm_errman_reg_signaledsystemerror_9_i_0_1_5910; + wire com_cmm_u_cmm_errman_cs_is_nfl_5911; + wire com_cmm_u_cmm_errman_wtd_cor_N_57200_i_5912; + wire com_cmm_u_cmm_errman_wtd_cor_N_56483_i_0; + wire com_cmm_u_cmm_errman_wtd_cor_un4_reg_inc_dec_b_0_o3_0_2_5913; + wire com_cmm_u_cmm_errman_cor_cntr_un14_reg_cnt_cry_0_5914; + wire com_cmm_u_cmm_errman_cor_cntr_un14_reg_cnt_cry_1_5915; + wire com_cmm_u_cmm_errman_cor_cntr_GND_5916; + wire com_cmm_u_cmm_errman_cor_cntr_un14_reg_cnt_cry_2_5917; + wire com_cmm_u_cmm_errman_cor_cntr_un25_reg_cnt_cry_0_5918; + wire com_cmm_u_cmm_errman_cor_cntr_un25_reg_cnt_cry_1_5919; + wire com_cmm_u_cmm_errman_cor_cntr_VCC_5920; + wire com_cmm_u_cmm_errman_cor_cntr_un25_reg_cnt_cry_2_5921; + wire com_cmm_u_cmm_errman_cor_cntr_N_24801_i; + wire com_cmm_u_cmm_errman_cor_cntr_un14_reg_cnt_cry_3_5922; + wire com_cmm_u_cmm_errman_cor_cntr_reg_uflow_3_i_a2_0_5923; + wire com_cmm_u_cmm_errman_cor_cntr_un14_reg_cnt_s_3_5924; + wire com_cmm_u_cmm_errman_cor_cntr_un25_reg_cnt_s_3_5925; + wire com_cmm_u_cmm_errman_cor_cntr_un14_reg_cnt_s_2_5926; + wire com_cmm_u_cmm_errman_cor_cntr_un25_reg_cnt_s_2_5927; + wire com_cmm_u_cmm_errman_cor_cntr_un14_reg_cnt_s_1_5928; + wire com_cmm_u_cmm_errman_cor_cntr_un25_reg_cnt_s_1_5929; + wire com_cmm_u_cmm_errman_cor_cntr_un25_reg_cnt_axb_0_5930; + wire com_cmm_u_cmm_errman_cor_cntr_un14_reg_cnt_axb_0_5931; + wire com_cmm_u_cmm_errman_cor_cntr_reg_extra_6; + wire com_cmm_u_cmm_errman_cor_cntr_reg_extra_5932; + wire com_cmm_u_cmm_errman_cor_cntr_N_18826_i; + wire com_cmm_u_cmm_errman_cor_cntr_reg_inc_dec_b_5933; + wire com_cmm_u_cmm_errman_cor_cntr_N_24811_i; + wire com_cmm_u_cmm_errman_cor_cntr_N_24809_i; + wire com_cmm_u_cmm_errman_cor_cntr_N_24815_i; + wire com_cmm_u_cmm_errman_cor_cntr_N_24813_i; + wire com_cmm_u_cmm_errman_cor_cntr_un25_reg_cnt_s_4_5934; + wire com_cmm_u_cmm_errman_cor_cntr_un25_reg_cnt_cry_3_5935; + wire com_cmm_u_cmm_errman_cor_cntr_un25_reg_cnt_axb_3_i_i_5936; + wire com_cmm_u_cmm_errman_cor_cntr_un25_reg_cnt_axb_2_5937; + wire com_cmm_u_cmm_errman_cor_cntr_un25_reg_cnt_axb_1_5938; + wire com_cmm_u_cmm_errman_cor_cntr_un14_reg_cnt_axb_3_5939; + wire com_cmm_u_cmm_errman_cor_cntr_reg_uflow_5940; + wire com_cmm_u_cmm_errman_cor_cntr_oflow; + wire com_cmm_u_cmm_errman_cor_cntr_un14_reg_cnt_axb_2_5941; + wire com_cmm_u_cmm_errman_cor_cntr_N_24805_i; + wire com_cmm_u_cmm_errman_cor_cntr_un14_reg_cnt_axb_1_5942; + wire com_cmm_u_cmm_errman_cor_cntr_N_24803_i; + wire com_cmm_u_cmm_errman_wtd_nfl_un4_reg_inc_dec_b_i_5943; + wire com_cmm_u_cmm_errman_wtd_nfl_N_56487_i_0; + wire com_cmm_u_cmm_errman_wtd_nfl_N_56481_i; + wire com_cmm_u_cmm_errman_nfl_cntr_un14_reg_cnt_cry_0_5944; + wire com_cmm_u_cmm_errman_nfl_cntr_un14_reg_cnt_cry_1_5945; + wire com_cmm_u_cmm_errman_nfl_cntr_GND_5946; + wire com_cmm_u_cmm_errman_nfl_cntr_un14_reg_cnt_cry_2_5947; + wire com_cmm_u_cmm_errman_nfl_cntr_un25_reg_cnt_cry_0_5948; + wire com_cmm_u_cmm_errman_nfl_cntr_un25_reg_cnt_cry_1_5949; + wire com_cmm_u_cmm_errman_nfl_cntr_VCC_5950; + wire com_cmm_u_cmm_errman_nfl_cntr_un25_reg_cnt_cry_2_5951; + wire com_cmm_u_cmm_errman_nfl_cntr_reg_uflow_3_i_a2_0_5952; + wire com_cmm_u_cmm_errman_nfl_cntr_un25_reg_cnt_axb_0_5953; + wire com_cmm_u_cmm_errman_nfl_cntr_reg_extra_6_0_u_i_m2_0_1; + wire com_cmm_u_cmm_errman_nfl_cntr_reg_extra_5954; + wire com_cmm_u_cmm_errman_nfl_cntr_N_18916_i; + wire com_cmm_u_cmm_errman_nfl_cntr_reg_uflow_5955; + wire com_cmm_u_cmm_errman_nfl_cntr_reg_inc_dec_b_5956; + wire com_cmm_u_cmm_errman_nfl_cntr_N_26170_i; + wire com_cmm_u_cmm_errman_nfl_cntr_un25_reg_cnt_cry_3_5957; + wire com_cmm_u_cmm_errman_nfl_cntr_un25_reg_cnt_axb_3_i_i_5958; + wire com_cmm_u_cmm_errman_nfl_cntr_un25_reg_cnt_axb_2_5959; + wire com_cmm_u_cmm_errman_nfl_cntr_un25_reg_cnt_axb_1_5960; + wire com_cmm_u_cmm_errman_nfl_cntr_un14_reg_cnt_axb_3_5961; + wire com_cmm_u_cmm_errman_nfl_cntr_un25_reg_cnt_axb_3_i; + wire com_cmm_u_cmm_errman_nfl_cntr_un14_reg_cnt_axb_2_5962; + wire com_cmm_u_cmm_errman_nfl_cntr_N_26174_i; + wire com_cmm_u_cmm_errman_nfl_cntr_un14_reg_cnt_axb_1_5963; + wire com_cmm_u_cmm_errman_nfl_cntr_N_26172_i; + wire com_cmm_u_cmm_errman_wtd_ftl_N_57663_i_5964; + wire com_cmm_u_cmm_errman_ftl_cntr_un14_reg_cnt_cry_0_5965; + wire com_cmm_u_cmm_errman_ftl_cntr_un14_reg_cnt_cry_1_5966; + wire com_cmm_u_cmm_errman_ftl_cntr_GND_5967; + wire com_cmm_u_cmm_errman_ftl_cntr_un14_reg_cnt_cry_2_5968; + wire com_cmm_u_cmm_errman_ftl_cntr_un25_reg_cnt_cry_0_5969; + wire com_cmm_u_cmm_errman_ftl_cntr_un25_reg_cnt_cry_1_5970; + wire com_cmm_u_cmm_errman_ftl_cntr_VCC_5971; + wire com_cmm_u_cmm_errman_ftl_cntr_un25_reg_cnt_cry_2_5972; + wire com_cmm_u_cmm_errman_ftl_cntr_un14_reg_cnt_cry_3_5973; + wire com_cmm_u_cmm_errman_ftl_cntr_reg_uflow_3_i_a2_0_5974; + wire com_cmm_u_cmm_errman_ftl_cntr_un14_reg_cnt_s_1_0; + wire com_cmm_u_cmm_errman_ftl_cntr_un25_reg_cnt_s_1_0; + wire com_cmm_u_cmm_errman_ftl_cntr_un14_reg_cnt_axb_0_5975; + wire com_cmm_u_cmm_errman_ftl_cntr_un14_reg_cnt_s_3_0; + wire com_cmm_u_cmm_errman_ftl_cntr_un25_reg_cnt_s_3_0; + wire com_cmm_u_cmm_errman_ftl_cntr_un14_reg_cnt_s_2_0; + wire com_cmm_u_cmm_errman_ftl_cntr_un25_reg_cnt_s_2_0; + wire com_cmm_u_cmm_errman_ftl_cntr_N_58544; + wire com_cmm_u_cmm_errman_ftl_cntr_un25_reg_cnt_axb_0_5976; + wire com_cmm_u_cmm_errman_ftl_cntr_N_17829_i; + wire com_cmm_u_cmm_errman_ftl_cntr_N_17881_i; + wire com_cmm_u_cmm_errman_ftl_cntr_reg_extra_5977; + wire com_cmm_u_cmm_errman_ftl_cntr_N_18871_i; + wire com_cmm_u_cmm_errman_ftl_cntr_reg_inc_dec_b_5978; + wire com_cmm_u_cmm_errman_ftl_cntr_N_17875_i; + wire com_cmm_u_cmm_errman_ftl_cntr_N_17873_i; + wire com_cmm_u_cmm_errman_ftl_cntr_N_17843_i; + wire com_cmm_u_cmm_errman_ftl_cntr_N_17841_i; + wire com_cmm_u_cmm_errman_ftl_cntr_N_17839_i; + wire com_cmm_u_cmm_errman_ftl_cntr_N_17837_i; + wire com_cmm_u_cmm_errman_ftl_cntr_N_17879_i; + wire com_cmm_u_cmm_errman_ftl_cntr_N_17877_i; + wire com_cmm_u_cmm_errman_ftl_cntr_un25_reg_cnt_s_4_0; + wire com_cmm_u_cmm_errman_ftl_cntr_un25_reg_cnt_cry_3_5979; + wire com_cmm_u_cmm_errman_ftl_cntr_un25_reg_cnt_axb_3_i_i_5980; + wire com_cmm_u_cmm_errman_ftl_cntr_un25_reg_cnt_axb_2_5981; + wire com_cmm_u_cmm_errman_ftl_cntr_un25_reg_cnt_axb_1_5982; + wire com_cmm_u_cmm_errman_ftl_cntr_un14_reg_cnt_axb_3_5983; + wire com_cmm_u_cmm_errman_ftl_cntr_reg_uflow_5984; + wire com_cmm_u_cmm_errman_ftl_cntr_oflow; + wire com_cmm_u_cmm_errman_ftl_cntr_un14_reg_cnt_axb_2_5985; + wire com_cmm_u_cmm_errman_ftl_cntr_N_17833_i; + wire com_cmm_u_cmm_errman_ftl_cntr_un14_reg_cnt_axb_1_5986; + wire com_cmm_u_cmm_errman_ftl_cntr_N_17831_i; + wire com_cmm_u_cmm_errman_wtd_cplt_N_58593_i_5987; + wire com_cmm_u_cmm_errman_wtd_cplt_N_56474_i_0; + wire com_cmm_u_cmm_errman_cplt_cntr_un25_reg_cnt_c1_5988; + wire com_cmm_u_cmm_errman_cplt_cntr_un25_reg_cnt_p4_5989; + wire com_cmm_u_cmm_errman_cplt_cntr_un14_reg_cnt_p4_5990; + wire com_cmm_u_cmm_errman_cplt_cntr_reg_extra_6_0_u_i_m2_0_5991; + wire com_cmm_u_cmm_errman_cplt_cntr_reg_extra_5992; + wire com_cmm_u_cmm_errman_cplt_cntr_reg_uflow_3; + wire com_cmm_u_cmm_errman_cplt_cntr_reg_uflow_5993; + wire com_cmm_u_cmm_errman_cplt_cntr_reg_inc_dec_b_5994; + wire com_cmm_u_cmm_errman_cplt_cntr_un25_reg_cnt_axb3_i; + wire com_cmm_u_cmm_errman_cplt_cntr_un25_reg_cnt_axb2_i; + wire com_cmm_u_cmm_errman_cplt_cntr_un25_reg_cnt_axb1_i; + wire com_cmm_u_cmm_errman_cplt_cntr_N_26185_i; + wire com_cmm_u_cmm_errman_wtd_cplu_N_86724_i_5995; + wire com_cmm_u_cmm_errman_wtd_cplu_N_39979_i; + wire com_cmm_u_cmm_errman_cplu_cntr_un25_reg_cnt_c1_0; + wire com_cmm_u_cmm_errman_cplu_cntr_un25_reg_cnt_p4_5996; + wire com_cmm_u_cmm_errman_cplu_cntr_un14_reg_cnt_p4_5997; + wire com_cmm_u_cmm_errman_cplu_cntr_reg_inc_dec_b_5998; + wire com_cmm_u_cmm_errman_cplu_cntr_reg_extra_6_0_u_i_m2_0_0; + wire com_cmm_u_cmm_errman_cplu_cntr_reg_extra_5999; + wire com_cmm_u_cmm_errman_cplu_cntr_reg_uflow_3; + wire com_cmm_u_cmm_errman_cplu_cntr_reg_uflow_6000; + wire com_cmm_u_cmm_errman_cplu_cntr_un25_reg_cnt_axb3_i; + wire com_cmm_u_cmm_errman_cplu_cntr_un25_reg_cnt_axb2_i; + wire com_cmm_u_cmm_errman_cplu_cntr_un25_reg_cnt_axb1_i; + wire com_cmm_u_cmm_errman_cplu_cntr_N_26200_i; + wire com_cmm_u_cmm_errman_cmt_hdr_buf_VCC_6001; + wire com_cmm_u_cmm_errman_cmt_hdr_buf_GND_6002; + wire com_cmm_u_cmm_errman_cfg_hdr_buf_GND_6003; + wire com_cmm_u_cmm_pm_GND_6004; + wire com_cmm_u_cmm_pm_N_58678_2; + wire com_cmm_u_cmm_pm_N_58678_1; + wire com_cmm_u_cmm_pm_un1_cmmt_ppm_suspend_req_n_comb_0_sqmuxa_i_0_0_0_39392_6005; + wire com_cmm_u_cmm_pm_N_58674; + wire com_cmm_u_cmm_pm_N_60460_1; + wire com_cmm_u_cmm_pm_N_58659_1_0; + wire com_cmm_u_cmm_pm_N_56319_i; + wire com_cmm_u_cmm_pm_un1_cmml_suspend_now_n21_i_0_0_0_a2_0_6006; + wire com_cmm_u_cmm_pm_N_58675; + wire com_cmm_u_cmm_pm_N_56002_i; + wire com_cmm_u_cmm_pm_pme_sent13; + wire com_cmm_u_cmm_pm_N_85828_i_6007; + wire com_cmm_u_cmm_pm_st_pm_0__6008; + wire com_cmm_u_cmm_pm_N_86397_i_6009; + wire com_cmm_u_cmm_pm_st_pm_18__6010; + wire com_cmm_u_cmm_pm_N_86427_i_6011; + wire com_cmm_u_cmm_pm_N_86691_i_6012; + wire com_cmm_u_cmm_pm_st_pm_16__6013; + wire com_cmm_u_cmm_pm_N_58679; + wire com_cmm_u_cmm_pm_st_pm_14__6014; + wire com_cmm_u_cmm_pm_N_58657; + wire com_cmm_u_cmm_pm_N_10381_i; + wire com_cmm_u_cmm_pm_st_pm_10__6015; + wire com_cmm_u_cmm_pm_N_58659; + wire com_cmm_u_cmm_pm_st_pm_8__6016; + wire com_cmm_u_cmm_pm_N_86396_i_6017; + wire com_cmm_u_cmm_pm_st_pm_6__6018; + wire com_cmm_u_cmm_pm_N_86426_i_6019; + wire com_cmm_u_cmm_pm_st_pm_28__6020; + wire com_cmm_u_cmm_pm_N_86395_i_6021; + wire com_cmm_u_cmm_pm_N_86393_i_6022; + wire com_cmm_u_cmm_pm_N_86394_i_6023; + wire com_cmm_u_cmm_pm_st_pm_25__6024; + wire com_cmm_u_cmm_pm_st_pm_next_3_sqmuxa_i_i_a2_0_a2_0_a2_0_a2_6025; + wire com_cmm_u_cmm_pm_st_pm_24__6026; + wire com_cmm_u_cmm_pm_st_pm_23__6027; + wire com_cmm_u_cmm_pm_N_86715_i_6028; + wire com_cmm_u_cmm_pm_N_59582; + wire com_cmm_u_cmm_pm_st_pm_21__6029; + wire com_cmm_u_cmm_pm_N_58708; + wire com_cmm_u_cmm_pm_VCC_6030; + wire com_cmm_u_cmm_pm_st_pm_19__6031; + wire com_cmm_u_cmm_pm_N_85829_i_6032; + wire com_cmm_u_cmm_pm_N_56201_i; + wire com_cmm_u_cmm_pm_N_85895_i_6033; + wire com_cmm_u_cmm_pm_N_58673_i_6034; + wire com_cmm_u_cmm_pm_st_pm_30__6035; + wire com_cmm_u_cmm_pm_N_85830_i_6036; + wire com_cmm_u_cmm_pm_N_85830_i_1_6037; + wire com_cmm_u_cmm_pm_un1_cmml_suspend_now_n21_i_0_0_0_o3_6038; + wire com_cmm_u_cmm_pm_inactivity_timer24; + wire com_cmm_u_cmm_arbiter_N_56091_i; + wire com_cmm_u_cmm_arbiter_N_60462_1; + wire com_cmm_u_cmm_arbiter_N_44141_i; + wire com_cmm_u_cmm_arbiter_ns_fsm_0_0_0_2_39423_6039; + wire com_cmm_u_cmm_arbiter_N_60432; + wire com_cmm_u_cmm_arbiter_N_60435; + wire com_cmm_u_cmm_arbiter_N_58326; + wire com_cmm_u_cmm_arbiter_N_60463; + wire com_cmm_u_cmm_arbiter_N_60462; + wire com_cmm_u_cmm_arbiter_ns_fsm_0_i_0_0_39306_6040; + wire com_cmm_u_cmm_arbiter_N_60441; + wire com_cmm_u_cmm_arbiter_N_60439; + wire com_cmm_u_cmm_arbiter_N_43125_i; + wire com_cmm_u_cmm_arbiter_N_42758_i; + wire com_cmm_u_cmm_arbiter_N_56357_i; + wire com_cmm_u_cmm_arbiter_N_42991_i; + wire com_cmm_u_cmm_arbiter_req_arbiter_6_i_0_2_39310_6041; + wire com_cmm_u_cmm_arbiter_N_42989_i; + wire com_cmm_u_cmm_arbiter_req_arbiter_6_i_0_1_39419_6042; + wire com_cmm_u_cmm_arbiter_N_60429; + wire com_cmm_u_cmm_arbiter_N_42987_i; + wire com_cmm_u_cmm_arbiter_N_60428; + wire com_cmm_u_cmm_arbiter_N_56482_i; + wire com_cmm_u_cmm_arbiter_N_56158_i; + wire com_cmm_u_cmm_arbiter_N_85985_i_6043; + wire com_cmm_u_cmm_arbiter_N_85985_i_1_6044; + wire com_cmm_u_cmm_arbiter_N_56341_i; + wire com_cmm_u_cmm_arbiter_N_56179_i; + wire com_cmm_u_cmm_arbiter_ns_fsm_0_sqmuxa_4; + wire com_cmm_u_cmm_arbiter_ns_fsm_0_sqmuxa_2; + wire com_cmm_u_cmm_arbiter_ns_fsm_0_sqmuxa; + wire com_cmm_u_cmm_arbiter_N_43044_i; + wire com_cmm_u_cmm_arbiter_N_10094_i; + wire com_cmm_u_cmm_arbiter_N_85986_i_6045; + wire com_cmm_u_cmm_arbiter_N_85984_i_6046; + wire com_cmm_u_cmm_dataproducer_N_10527_i; + wire com_cmm_u_cmm_dataproducer_m5_i_0_0_a3_0_2; + wire com_cmm_u_cmm_dataproducer_N_57698; + wire com_cmm_u_cmm_dataproducer_N_57680; + wire com_cmm_u_cmm_dataproducer_N_57737; + wire com_cmm_u_cmm_dataproducer_N_57710; + wire com_cmm_u_cmm_dataproducer_N_57707; + wire com_cmm_u_cmm_dataproducer_N_57683; + wire com_cmm_u_cmm_dataproducer_N_57692; + wire com_cmm_u_cmm_dataproducer_N_57719; + wire com_cmm_u_cmm_dataproducer_N_57701; + wire com_cmm_u_cmm_dataproducer_N_57677; + wire com_cmm_u_cmm_dataproducer_N_57674; + wire com_cmm_u_cmm_dataproducer_N_57689; + wire com_cmm_u_cmm_dataproducer_N_57728; + wire com_cmm_u_cmm_dataproducer_N_57704; + wire com_cmm_u_cmm_dataproducer_N_57740; + wire com_cmm_u_cmm_dataproducer_N_57722; + wire com_cmm_u_cmm_dataproducer_N_57686; + wire com_cmm_u_cmm_dataproducer_N_57725; + wire com_cmm_u_cmm_dataproducer_N_57734; + wire com_cmm_u_cmm_dataproducer_N_57695; + wire com_cmm_u_cmm_dataproducer_N_57716; + wire com_cmm_u_cmm_dataproducer_N_57731; + wire com_cmm_u_cmm_dataproducer_N_57713; + wire com_cmm_u_cmm_dataproducer_N_57743; + wire com_cmm_u_cmm_dataproducer_N_57748_1; + wire com_cmm_u_cmm_dataproducer_N_58650; + wire com_cmm_u_cmm_dataproducer_N_58648; + wire com_cmm_u_cmm_dataproducer_N_58647; + wire com_cmm_u_cmm_dataproducer_N_58534; + wire com_cmm_u_cmm_dataproducer_N_61317; + wire com_cmm_u_cmm_dataproducer_N_17569_i; + wire com_cmm_u_cmm_dataproducer_N_58531; + wire com_cmm_u_cmm_dataproducer_N_56514_i; + wire com_cmm_u_cmm_dataproducer_N_17567_i; + wire com_cmm_u_cmm_dataproducer_N_17565_i; + wire com_cmm_u_cmm_dataproducer_N_17563_i; + wire com_cmm_u_cmm_dataproducer_N_17557_i; + wire com_cmm_u_cmm_dataproducer_N_17573_i; + wire com_cmm_u_cmm_dataproducer_N_58533; + wire com_cmm_u_cmm_dataproducer_N_58535; + wire com_cmm_u_cmm_dataproducer_nxt_req_gnt_state38; + wire com_cmm_u_cmm_dataproducer_byte_06_21_7_; + wire com_cmm_u_cmm_dataproducer_N_52293_i; + wire com_cmm_u_cmm_dataproducer_N_58643_i_6047; + wire com_cmm_u_cmm_dataproducer_un1_byte_1062_1_i_i_i_a3_6048; + wire com_cmm_u_cmm_dataproducer_N_86296_i_6049; + wire com_cmm_u_cmm_dataproducer_N_86295_i_6050; + wire com_cmm_u_cmm_dataproducer_N_85894_i_6051; + wire com_cmm_u_cmm_dataproducer_N_86372_i_6052; + wire com_cmm_u_cmm_dataproducer_N_85819_i_6053; + wire com_cmm_u_cmm_dataproducer_N_85893_i_6054; + wire com_cmm_u_cmm_dataproducer_N_85891_i_6055; + wire com_cmm_u_cmm_dataproducer_N_86779_i_6056; + wire com_cmm_u_cmm_dataproducer_N_85852_i_6057; + wire com_cmm_u_cmm_dataproducer_N_85851_i_6058; + wire com_cmm_u_cmm_dataproducer_N_85850_i_6059; + wire com_cmm_u_cmm_dataproducer_N_85849_i_6060; + wire com_cmm_u_cmm_dataproducer_N_85848_i_6061; + wire com_cmm_u_cmm_dataproducer_N_85847_i_6062; + wire com_cmm_u_cmm_dataproducer_N_85846_i_6063; + wire com_cmm_u_cmm_dataproducer_N_85845_i_6064; + wire com_cmm_u_cmm_dataproducer_N_85844_i_6065; + wire com_cmm_u_cmm_dataproducer_N_85843_i_6066; + wire com_cmm_u_cmm_dataproducer_N_85842_i_6067; + wire com_cmm_u_cmm_dataproducer_N_85841_i_6068; + wire com_cmm_u_cmm_dataproducer_N_85864_i_6069; + wire com_cmm_u_cmm_dataproducer_N_85863_i_6070; + wire com_cmm_u_cmm_dataproducer_N_85862_i_6071; + wire com_cmm_u_cmm_dataproducer_N_85861_i_6072; + wire com_cmm_u_cmm_dataproducer_N_85860_i_6073; + wire com_cmm_u_cmm_dataproducer_N_85859_i_6074; + wire com_cmm_u_cmm_dataproducer_N_85858_i_6075; + wire com_cmm_u_cmm_dataproducer_N_85857_i_6076; + wire com_cmm_u_cmm_dataproducer_N_85856_i_6077; + wire com_cmm_u_cmm_dataproducer_N_85855_i_6078; + wire com_cmm_u_cmm_dataproducer_N_85854_i_6079; + wire com_cmm_u_cmm_dataproducer_N_85853_i_6080; + wire com_cmm_u_cmm_dataproducer_N_86765_i; + wire com_cmm_u_cmm_dataproducer_N_19187_i; + wire com_cmm_u_cmm_dataproducer_N_19185_i; + wire com_cmm_u_cmm_dataproducer_N_19183_i; + wire com_cmm_u_cmm_dataproducer_N_19181_i; + wire com_cmm_u_cmm_dataproducer_N_19179_i; + wire com_cmm_u_cmm_dataproducer_N_19177_i; + wire com_cmm_u_cmm_dataproducer_N_19175_i; + wire com_cmm_u_cmm_dataproducer_N_19173_i; + wire com_cmm_u_cmm_dataproducer_N_19171_i; + wire com_cmm_u_cmm_dataproducer_N_19169_i; + wire com_cmm_u_cmm_dataproducer_N_19167_i; + wire com_cmm_u_cmm_dataproducer_N_19165_i; + wire com_cmm_u_cmm_dataproducer_N_17522_i; + wire com_cmm_u_cmm_dataproducer_N_17520_i; + wire com_cmm_u_cmm_dataproducer_N_17518_i; + wire com_cmm_u_cmm_dataproducer_byte_06_21_3_; + wire com_cmm_u_cmm_dataproducer_byte_06_21_2_; + wire com_cmm_u_cmm_dataproducer_byte_06_21_1_; + wire com_cmm_u_cmm_dataproducer_byte_06_21_0_; + wire com_cmm_u_cmm_dataproducer_N_19189_i; + wire com_cmm_u_cmm_dataproducer_N_85818_i_6081; + wire com_cmm_u_cmm_dataproducer_N_85818_i_1_6082; + wire com_cmm_u_cmm_dataproducer_N_61357; + wire com_cmm_u_cmm_dataproducer_N_61299; + wire NLW_plm_v4f_mgt_dcm_CLK90_UNCONNECTED; + wire NLW_plm_v4f_mgt_dcm_CLK2X_UNCONNECTED; + wire NLW_plm_v4f_mgt_dcm_DO_15__UNCONNECTED; + wire NLW_plm_v4f_mgt_dcm_DO_14__UNCONNECTED; + wire NLW_plm_v4f_mgt_dcm_DO_13__UNCONNECTED; + wire NLW_plm_v4f_mgt_dcm_DO_12__UNCONNECTED; + wire NLW_plm_v4f_mgt_dcm_DO_11__UNCONNECTED; + wire NLW_plm_v4f_mgt_dcm_DO_10__UNCONNECTED; + wire NLW_plm_v4f_mgt_dcm_DO_9__UNCONNECTED; + wire NLW_plm_v4f_mgt_dcm_DO_8__UNCONNECTED; + wire NLW_plm_v4f_mgt_dcm_DO_7__UNCONNECTED; + wire NLW_plm_v4f_mgt_dcm_DO_6__UNCONNECTED; + wire NLW_plm_v4f_mgt_dcm_DO_5__UNCONNECTED; + wire NLW_plm_v4f_mgt_dcm_DO_4__UNCONNECTED; + wire NLW_plm_v4f_mgt_dcm_DO_3__UNCONNECTED; + wire NLW_plm_v4f_mgt_dcm_DO_2__UNCONNECTED; + wire NLW_plm_v4f_mgt_dcm_DO_1__UNCONNECTED; + wire NLW_plm_v4f_mgt_dcm_DO_0__UNCONNECTED; + wire NLW_plm_v4f_mgt_dcm_PSDONE_UNCONNECTED; + wire NLW_plm_v4f_mgt_dcm_CLKFX180_UNCONNECTED; + wire NLW_plm_v4f_mgt_dcm_CLK180_UNCONNECTED; + wire NLW_plm_v4f_mgt_dcm_CLK2X180_UNCONNECTED; + wire NLW_plm_v4f_mgt_dcm_CLK270_UNCONNECTED; + wire NLW_plm_v4f_mgt_dcm_DRDY_UNCONNECTED; + wire NLW_plm_v4f_mgt_reg_tee0_dlyline_I_2_Q15_UNCONNECTED; + wire NLW_plm_v4f_mgt_reg_tee0_dlyline_I_1_Q_UNCONNECTED; + wire NLW_plm_v4f_mgt_reg_tee1_dlyline_I_2_Q15_UNCONNECTED; + wire NLW_plm_v4f_mgt_reg_tee1_dlyline_I_1_Q_UNCONNECTED; + wire NLW_plm_v4f_mgt_reg_tee2_dlyline_I_2_Q15_UNCONNECTED; + wire NLW_plm_v4f_mgt_reg_tee2_dlyline_I_1_Q_UNCONNECTED; + wire NLW_plm_v4f_mgt_reg_tee3_dlyline_I_2_Q15_UNCONNECTED; + wire NLW_plm_v4f_mgt_reg_tee3_dlyline_I_1_Q_UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST_RXBUFERR_UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST_RXSTATUS_4__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST_RXSTATUS_3__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST_RXSTATUS_2__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST_RXSTATUS_1__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST_RXSTATUS_0__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST_RXNOTINTABLE_7__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST_RXNOTINTABLE_6__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST_RXNOTINTABLE_5__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST_RXNOTINTABLE_4__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST_RXCRCOUT_31__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST_RXCRCOUT_30__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST_RXCRCOUT_29__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST_RXCRCOUT_28__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST_RXCRCOUT_27__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST_RXCRCOUT_26__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST_RXCRCOUT_25__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST_RXCRCOUT_24__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST_RXCRCOUT_23__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST_RXCRCOUT_22__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST_RXCRCOUT_21__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST_RXCRCOUT_20__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST_RXCRCOUT_19__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST_RXCRCOUT_18__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST_RXCRCOUT_17__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST_RXCRCOUT_16__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST_RXCRCOUT_15__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST_RXCRCOUT_14__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST_RXCRCOUT_13__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST_RXCRCOUT_12__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST_RXCRCOUT_11__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST_RXCRCOUT_10__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST_RXCRCOUT_9__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST_RXCRCOUT_8__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST_RXCRCOUT_7__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST_RXCRCOUT_6__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST_RXCRCOUT_5__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST_RXCRCOUT_4__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST_RXCRCOUT_3__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST_RXCRCOUT_2__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST_RXCRCOUT_1__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST_RXCRCOUT_0__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST_TXBUFERR_UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST_RXREALIGN_UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST_TXCRCOUT_31__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST_TXCRCOUT_30__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST_TXCRCOUT_29__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST_TXCRCOUT_28__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST_TXCRCOUT_27__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST_TXCRCOUT_26__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST_TXCRCOUT_25__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST_TXCRCOUT_24__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST_TXCRCOUT_23__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST_TXCRCOUT_22__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST_TXCRCOUT_21__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST_TXCRCOUT_20__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST_TXCRCOUT_19__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST_TXCRCOUT_18__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST_TXCRCOUT_17__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST_TXCRCOUT_16__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST_TXCRCOUT_15__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST_TXCRCOUT_14__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST_TXCRCOUT_13__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST_TXCRCOUT_12__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST_TXCRCOUT_11__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST_TXCRCOUT_10__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST_TXCRCOUT_9__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST_TXCRCOUT_8__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST_TXCRCOUT_7__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST_TXCRCOUT_6__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST_TXCRCOUT_5__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST_TXCRCOUT_4__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST_TXCRCOUT_3__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST_TXCRCOUT_2__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST_TXCRCOUT_1__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST_TXCRCOUT_0__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST_RXCYCLELIMIT_UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST_TXCYCLELIMIT_UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST_TXCALFAIL_UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST_RXPCSHCLKOUT_UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST_TXPCSHCLKOUT_UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST_RXDATA_63__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST_RXDATA_62__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST_RXDATA_61__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST_RXDATA_60__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST_RXDATA_59__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST_RXDATA_58__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST_RXDATA_57__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST_RXDATA_56__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST_RXDATA_55__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST_RXDATA_54__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST_RXDATA_53__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST_RXDATA_52__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST_RXDATA_51__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST_RXDATA_50__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST_RXDATA_49__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST_RXDATA_48__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST_RXDATA_47__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST_RXDATA_46__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST_RXDATA_45__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST_RXDATA_44__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST_RXDATA_43__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST_RXDATA_42__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST_RXDATA_41__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST_RXDATA_40__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST_RXDATA_39__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST_RXDATA_38__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST_RXDATA_37__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST_RXDATA_36__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST_RXDATA_35__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST_RXDATA_34__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST_RXDATA_33__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST_RXDATA_32__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST_TXRUNDISP_7__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST_TXRUNDISP_6__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST_TXRUNDISP_5__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST_TXRUNDISP_4__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST_TXRUNDISP_3__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST_TXRUNDISP_2__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST_TXRUNDISP_1__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST_TXRUNDISP_0__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST_RXCALFAIL_UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST_RXLOSSOFSYNC_1__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST_RXLOSSOFSYNC_0__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST_RXRUNDISP_7__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST_RXRUNDISP_6__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST_RXRUNDISP_5__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST_RXRUNDISP_4__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST_RXMCLK_UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST_RXCOMMADET_UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST_TXOUTCLK1_UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST_TXOUTCLK2_UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST_RXRECCLK1_UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST_RXRECCLK2_UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST_RXCHARISK_7__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST_RXCHARISK_6__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST_RXCHARISK_5__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST_RXCHARISK_4__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST_RXDISPERR_7__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST_RXDISPERR_6__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST_RXDISPERR_5__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST_RXDISPERR_4__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST_RXCHARISCOMMA_7__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST_RXCHARISCOMMA_6__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST_RXCHARISCOMMA_5__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST_RXCHARISCOMMA_4__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST_RXCHARISCOMMA_3__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST_RXCHARISCOMMA_2__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST_RXCHARISCOMMA_1__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST_RXCHARISCOMMA_0__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST_TXKERR_7__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST_TXKERR_6__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST_TXKERR_5__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST_TXKERR_4__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST_TXKERR_3__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST_TXKERR_2__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST_TXKERR_1__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST_TXKERR_0__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST2_RXBUFERR_UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST2_RXSTATUS_4__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST2_RXSTATUS_3__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST2_RXSTATUS_2__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST2_RXSTATUS_1__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST2_RXSTATUS_0__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST2_RXNOTINTABLE_7__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST2_RXNOTINTABLE_6__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST2_RXNOTINTABLE_5__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST2_RXNOTINTABLE_4__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST2_RXCRCOUT_31__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST2_RXCRCOUT_30__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST2_RXCRCOUT_29__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST2_RXCRCOUT_28__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST2_RXCRCOUT_27__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST2_RXCRCOUT_26__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST2_RXCRCOUT_25__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST2_RXCRCOUT_24__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST2_RXCRCOUT_23__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST2_RXCRCOUT_22__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST2_RXCRCOUT_21__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST2_RXCRCOUT_20__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST2_RXCRCOUT_19__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST2_RXCRCOUT_18__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST2_RXCRCOUT_17__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST2_RXCRCOUT_16__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST2_RXCRCOUT_15__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST2_RXCRCOUT_14__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST2_RXCRCOUT_13__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST2_RXCRCOUT_12__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST2_RXCRCOUT_11__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST2_RXCRCOUT_10__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST2_RXCRCOUT_9__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST2_RXCRCOUT_8__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST2_RXCRCOUT_7__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST2_RXCRCOUT_6__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST2_RXCRCOUT_5__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST2_RXCRCOUT_4__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST2_RXCRCOUT_3__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST2_RXCRCOUT_2__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST2_RXCRCOUT_1__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST2_RXCRCOUT_0__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST2_TXBUFERR_UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST2_RXREALIGN_UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST2_TXCRCOUT_31__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST2_TXCRCOUT_30__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST2_TXCRCOUT_29__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST2_TXCRCOUT_28__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST2_TXCRCOUT_27__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST2_TXCRCOUT_26__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST2_TXCRCOUT_25__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST2_TXCRCOUT_24__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST2_TXCRCOUT_23__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST2_TXCRCOUT_22__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST2_TXCRCOUT_21__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST2_TXCRCOUT_20__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST2_TXCRCOUT_19__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST2_TXCRCOUT_18__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST2_TXCRCOUT_17__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST2_TXCRCOUT_16__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST2_TXCRCOUT_15__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST2_TXCRCOUT_14__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST2_TXCRCOUT_13__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST2_TXCRCOUT_12__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST2_TXCRCOUT_11__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST2_TXCRCOUT_10__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST2_TXCRCOUT_9__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST2_TXCRCOUT_8__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST2_TXCRCOUT_7__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST2_TXCRCOUT_6__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST2_TXCRCOUT_5__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST2_TXCRCOUT_4__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST2_TXCRCOUT_3__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST2_TXCRCOUT_2__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST2_TXCRCOUT_1__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST2_TXCRCOUT_0__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST2_RXCYCLELIMIT_UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST2_TXCYCLELIMIT_UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST2_TXCALFAIL_UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST2_RXPCSHCLKOUT_UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST2_TXPCSHCLKOUT_UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST2_RXDATA_63__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST2_RXDATA_62__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST2_RXDATA_61__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST2_RXDATA_60__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST2_RXDATA_59__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST2_RXDATA_58__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST2_RXDATA_57__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST2_RXDATA_56__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST2_RXDATA_55__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST2_RXDATA_54__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST2_RXDATA_53__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST2_RXDATA_52__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST2_RXDATA_51__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST2_RXDATA_50__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST2_RXDATA_49__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST2_RXDATA_48__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST2_RXDATA_47__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST2_RXDATA_46__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST2_RXDATA_45__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST2_RXDATA_44__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST2_RXDATA_43__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST2_RXDATA_42__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST2_RXDATA_41__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST2_RXDATA_40__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST2_RXDATA_39__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST2_RXDATA_38__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST2_RXDATA_37__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST2_RXDATA_36__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST2_RXDATA_35__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST2_RXDATA_34__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST2_RXDATA_33__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST2_RXDATA_32__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST2_TXRUNDISP_7__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST2_TXRUNDISP_6__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST2_TXRUNDISP_5__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST2_TXRUNDISP_4__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST2_TXRUNDISP_3__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST2_TXRUNDISP_2__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST2_TXRUNDISP_1__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST2_TXRUNDISP_0__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST2_RXCALFAIL_UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST2_RXLOSSOFSYNC_1__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST2_RXLOSSOFSYNC_0__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST2_RXRUNDISP_7__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST2_RXRUNDISP_6__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST2_RXRUNDISP_5__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST2_RXRUNDISP_4__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST2_RXMCLK_UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST2_CHBONDO_4__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST2_CHBONDO_3__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST2_CHBONDO_2__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST2_CHBONDO_1__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST2_CHBONDO_0__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST2_RXCOMMADET_UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST2_TXOUTCLK1_UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST2_TXOUTCLK2_UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST2_RXRECCLK1_UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST2_RXRECCLK2_UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST2_RXCHARISK_7__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST2_RXCHARISK_6__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST2_RXCHARISK_5__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST2_RXCHARISK_4__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST2_RXDISPERR_7__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST2_RXDISPERR_6__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST2_RXDISPERR_5__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST2_RXDISPERR_4__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST2_RXCHARISCOMMA_7__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST2_RXCHARISCOMMA_6__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST2_RXCHARISCOMMA_5__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST2_RXCHARISCOMMA_4__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST2_RXCHARISCOMMA_3__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST2_RXCHARISCOMMA_2__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST2_RXCHARISCOMMA_1__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST2_RXCHARISCOMMA_0__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST2_TXKERR_7__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST2_TXKERR_6__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST2_TXKERR_5__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST2_TXKERR_4__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST2_TXKERR_3__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST2_TXKERR_2__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST2_TXKERR_1__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST2_TXKERR_0__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST3_RXBUFERR_UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST3_RXSTATUS_4__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST3_RXSTATUS_3__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST3_RXSTATUS_2__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST3_RXSTATUS_1__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST3_RXSTATUS_0__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST3_RXNOTINTABLE_7__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST3_RXNOTINTABLE_6__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST3_RXNOTINTABLE_5__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST3_RXNOTINTABLE_4__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST3_RXCRCOUT_31__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST3_RXCRCOUT_30__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST3_RXCRCOUT_29__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST3_RXCRCOUT_28__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST3_RXCRCOUT_27__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST3_RXCRCOUT_26__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST3_RXCRCOUT_25__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST3_RXCRCOUT_24__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST3_RXCRCOUT_23__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST3_RXCRCOUT_22__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST3_RXCRCOUT_21__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST3_RXCRCOUT_20__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST3_RXCRCOUT_19__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST3_RXCRCOUT_18__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST3_RXCRCOUT_17__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST3_RXCRCOUT_16__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST3_RXCRCOUT_15__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST3_RXCRCOUT_14__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST3_RXCRCOUT_13__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST3_RXCRCOUT_12__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST3_RXCRCOUT_11__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST3_RXCRCOUT_10__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST3_RXCRCOUT_9__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST3_RXCRCOUT_8__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST3_RXCRCOUT_7__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST3_RXCRCOUT_6__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST3_RXCRCOUT_5__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST3_RXCRCOUT_4__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST3_RXCRCOUT_3__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST3_RXCRCOUT_2__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST3_RXCRCOUT_1__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST3_RXCRCOUT_0__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST3_TXBUFERR_UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST3_RXREALIGN_UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST3_TXCRCOUT_31__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST3_TXCRCOUT_30__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST3_TXCRCOUT_29__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST3_TXCRCOUT_28__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST3_TXCRCOUT_27__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST3_TXCRCOUT_26__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST3_TXCRCOUT_25__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST3_TXCRCOUT_24__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST3_TXCRCOUT_23__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST3_TXCRCOUT_22__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST3_TXCRCOUT_21__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST3_TXCRCOUT_20__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST3_TXCRCOUT_19__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST3_TXCRCOUT_18__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST3_TXCRCOUT_17__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST3_TXCRCOUT_16__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST3_TXCRCOUT_15__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST3_TXCRCOUT_14__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST3_TXCRCOUT_13__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST3_TXCRCOUT_12__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST3_TXCRCOUT_11__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST3_TXCRCOUT_10__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST3_TXCRCOUT_9__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST3_TXCRCOUT_8__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST3_TXCRCOUT_7__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST3_TXCRCOUT_6__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST3_TXCRCOUT_5__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST3_TXCRCOUT_4__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST3_TXCRCOUT_3__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST3_TXCRCOUT_2__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST3_TXCRCOUT_1__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST3_TXCRCOUT_0__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST3_RXCYCLELIMIT_UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST3_TXCYCLELIMIT_UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST3_TXCALFAIL_UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST3_RXPCSHCLKOUT_UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST3_TXPCSHCLKOUT_UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST3_RXDATA_63__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST3_RXDATA_62__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST3_RXDATA_61__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST3_RXDATA_60__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST3_RXDATA_59__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST3_RXDATA_58__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST3_RXDATA_57__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST3_RXDATA_56__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST3_RXDATA_55__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST3_RXDATA_54__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST3_RXDATA_53__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST3_RXDATA_52__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST3_RXDATA_51__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST3_RXDATA_50__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST3_RXDATA_49__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST3_RXDATA_48__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST3_RXDATA_47__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST3_RXDATA_46__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST3_RXDATA_45__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST3_RXDATA_44__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST3_RXDATA_43__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST3_RXDATA_42__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST3_RXDATA_41__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST3_RXDATA_40__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST3_RXDATA_39__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST3_RXDATA_38__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST3_RXDATA_37__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST3_RXDATA_36__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST3_RXDATA_35__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST3_RXDATA_34__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST3_RXDATA_33__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST3_RXDATA_32__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST3_TXRUNDISP_7__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST3_TXRUNDISP_6__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST3_TXRUNDISP_5__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST3_TXRUNDISP_4__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST3_TXRUNDISP_3__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST3_TXRUNDISP_2__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST3_TXRUNDISP_1__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST3_TXRUNDISP_0__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST3_RXCALFAIL_UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST3_RXLOSSOFSYNC_1__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST3_RXLOSSOFSYNC_0__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST3_RXRUNDISP_7__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST3_RXRUNDISP_6__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST3_RXRUNDISP_5__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST3_RXRUNDISP_4__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST3_RXMCLK_UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST3_CHBONDO_4__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST3_CHBONDO_3__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST3_CHBONDO_2__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST3_CHBONDO_1__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST3_CHBONDO_0__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST3_RXCOMMADET_UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST3_TXOUTCLK1_UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST3_TXOUTCLK2_UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST3_RXRECCLK1_UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST3_RXRECCLK2_UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST3_RXCHARISK_7__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST3_RXCHARISK_6__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST3_RXCHARISK_5__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST3_RXCHARISK_4__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST3_RXDISPERR_7__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST3_RXDISPERR_6__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST3_RXDISPERR_5__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST3_RXDISPERR_4__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST3_RXCHARISCOMMA_7__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST3_RXCHARISCOMMA_6__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST3_RXCHARISCOMMA_5__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST3_RXCHARISCOMMA_4__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST3_RXCHARISCOMMA_3__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST3_RXCHARISCOMMA_2__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST3_RXCHARISCOMMA_1__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST3_RXCHARISCOMMA_0__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST3_TXKERR_7__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST3_TXKERR_6__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST3_TXKERR_5__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST3_TXKERR_4__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST3_TXKERR_3__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST3_TXKERR_2__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST3_TXKERR_1__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST3_TXKERR_0__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST4_RXBUFERR_UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST4_RXSTATUS_4__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST4_RXSTATUS_3__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST4_RXSTATUS_2__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST4_RXSTATUS_1__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST4_RXSTATUS_0__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST4_RXNOTINTABLE_7__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST4_RXNOTINTABLE_6__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST4_RXNOTINTABLE_5__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST4_RXNOTINTABLE_4__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST4_RXCRCOUT_31__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST4_RXCRCOUT_30__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST4_RXCRCOUT_29__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST4_RXCRCOUT_28__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST4_RXCRCOUT_27__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST4_RXCRCOUT_26__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST4_RXCRCOUT_25__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST4_RXCRCOUT_24__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST4_RXCRCOUT_23__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST4_RXCRCOUT_22__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST4_RXCRCOUT_21__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST4_RXCRCOUT_20__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST4_RXCRCOUT_19__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST4_RXCRCOUT_18__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST4_RXCRCOUT_17__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST4_RXCRCOUT_16__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST4_RXCRCOUT_15__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST4_RXCRCOUT_14__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST4_RXCRCOUT_13__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST4_RXCRCOUT_12__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST4_RXCRCOUT_11__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST4_RXCRCOUT_10__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST4_RXCRCOUT_9__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST4_RXCRCOUT_8__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST4_RXCRCOUT_7__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST4_RXCRCOUT_6__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST4_RXCRCOUT_5__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST4_RXCRCOUT_4__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST4_RXCRCOUT_3__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST4_RXCRCOUT_2__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST4_RXCRCOUT_1__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST4_RXCRCOUT_0__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST4_TXBUFERR_UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST4_RXREALIGN_UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST4_TXCRCOUT_31__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST4_TXCRCOUT_30__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST4_TXCRCOUT_29__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST4_TXCRCOUT_28__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST4_TXCRCOUT_27__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST4_TXCRCOUT_26__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST4_TXCRCOUT_25__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST4_TXCRCOUT_24__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST4_TXCRCOUT_23__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST4_TXCRCOUT_22__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST4_TXCRCOUT_21__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST4_TXCRCOUT_20__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST4_TXCRCOUT_19__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST4_TXCRCOUT_18__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST4_TXCRCOUT_17__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST4_TXCRCOUT_16__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST4_TXCRCOUT_15__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST4_TXCRCOUT_14__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST4_TXCRCOUT_13__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST4_TXCRCOUT_12__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST4_TXCRCOUT_11__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST4_TXCRCOUT_10__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST4_TXCRCOUT_9__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST4_TXCRCOUT_8__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST4_TXCRCOUT_7__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST4_TXCRCOUT_6__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST4_TXCRCOUT_5__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST4_TXCRCOUT_4__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST4_TXCRCOUT_3__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST4_TXCRCOUT_2__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST4_TXCRCOUT_1__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST4_TXCRCOUT_0__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST4_RXCYCLELIMIT_UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST4_TXCYCLELIMIT_UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST4_TXCALFAIL_UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST4_RXPCSHCLKOUT_UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST4_TXPCSHCLKOUT_UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST4_RXDATA_63__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST4_RXDATA_62__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST4_RXDATA_61__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST4_RXDATA_60__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST4_RXDATA_59__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST4_RXDATA_58__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST4_RXDATA_57__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST4_RXDATA_56__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST4_RXDATA_55__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST4_RXDATA_54__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST4_RXDATA_53__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST4_RXDATA_52__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST4_RXDATA_51__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST4_RXDATA_50__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST4_RXDATA_49__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST4_RXDATA_48__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST4_RXDATA_47__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST4_RXDATA_46__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST4_RXDATA_45__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST4_RXDATA_44__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST4_RXDATA_43__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST4_RXDATA_42__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST4_RXDATA_41__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST4_RXDATA_40__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST4_RXDATA_39__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST4_RXDATA_38__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST4_RXDATA_37__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST4_RXDATA_36__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST4_RXDATA_35__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST4_RXDATA_34__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST4_RXDATA_33__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST4_RXDATA_32__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST4_TXRUNDISP_7__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST4_TXRUNDISP_6__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST4_TXRUNDISP_5__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST4_TXRUNDISP_4__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST4_TXRUNDISP_3__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST4_TXRUNDISP_2__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST4_TXRUNDISP_1__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST4_TXRUNDISP_0__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST4_RXCALFAIL_UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST4_RXLOSSOFSYNC_1__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST4_RXLOSSOFSYNC_0__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST4_RXRUNDISP_7__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST4_RXRUNDISP_6__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST4_RXRUNDISP_5__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST4_RXRUNDISP_4__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST4_RXMCLK_UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST4_CHBONDO_4__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST4_CHBONDO_3__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST4_CHBONDO_2__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST4_CHBONDO_1__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST4_CHBONDO_0__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST4_RXCOMMADET_UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST4_TXOUTCLK1_UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST4_TXOUTCLK2_UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST4_RXRECCLK1_UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST4_RXRECCLK2_UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST4_RXCHARISK_7__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST4_RXCHARISK_6__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST4_RXCHARISK_5__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST4_RXCHARISK_4__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST4_RXDISPERR_7__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST4_RXDISPERR_6__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST4_RXDISPERR_5__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST4_RXDISPERR_4__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST4_RXCHARISCOMMA_7__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST4_RXCHARISCOMMA_6__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST4_RXCHARISCOMMA_5__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST4_RXCHARISCOMMA_4__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST4_RXCHARISCOMMA_3__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST4_RXCHARISCOMMA_2__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST4_RXCHARISCOMMA_1__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST4_RXCHARISCOMMA_0__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST4_TXKERR_7__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST4_TXKERR_6__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST4_TXKERR_5__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST4_TXKERR_4__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST4_TXKERR_3__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST4_TXKERR_2__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST4_TXKERR_1__UNCONNECTED; + wire NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST4_TXKERR_0__UNCONNECTED; + wire NLW_plm_dfm_deframe1_dwbuf_L0S0_SPO_UNCONNECTED; + wire NLW_plm_dfm_deframe1_dwbuf_L0S1_SPO_UNCONNECTED; + wire NLW_plm_dfm_deframe1_dwbuf_L0B0_SPO_UNCONNECTED; + wire NLW_plm_dfm_deframe1_dwbuf_L0B1_SPO_UNCONNECTED; + wire NLW_plm_dfm_deframe1_dwbuf_L0B2_SPO_UNCONNECTED; + wire NLW_plm_dfm_deframe1_dwbuf_L0B3_SPO_UNCONNECTED; + wire NLW_plm_dfm_deframe1_dwbuf_L0B4_SPO_UNCONNECTED; + wire NLW_plm_dfm_deframe1_dwbuf_L0B5_SPO_UNCONNECTED; + wire NLW_plm_dfm_deframe1_dwbuf_L0B6_SPO_UNCONNECTED; + wire NLW_plm_dfm_deframe1_dwbuf_L0B7_SPO_UNCONNECTED; + wire NLW_plm_dfm_deframe1_dwbuf_L1B0_SPO_UNCONNECTED; + wire NLW_plm_dfm_deframe1_dwbuf_L1B1_SPO_UNCONNECTED; + wire NLW_plm_dfm_deframe1_dwbuf_L1B2_SPO_UNCONNECTED; + wire NLW_plm_dfm_deframe1_dwbuf_L1B3_SPO_UNCONNECTED; + wire NLW_plm_dfm_deframe1_dwbuf_L1B4_SPO_UNCONNECTED; + wire NLW_plm_dfm_deframe1_dwbuf_L1B5_SPO_UNCONNECTED; + wire NLW_plm_dfm_deframe1_dwbuf_L1B6_SPO_UNCONNECTED; + wire NLW_plm_dfm_deframe1_dwbuf_L1B7_SPO_UNCONNECTED; + wire NLW_plm_dfm_deframe1_dwbuf_L2B0_SPO_UNCONNECTED; + wire NLW_plm_dfm_deframe1_dwbuf_L2B1_SPO_UNCONNECTED; + wire NLW_plm_dfm_deframe1_dwbuf_L2B2_SPO_UNCONNECTED; + wire NLW_plm_dfm_deframe1_dwbuf_L2B3_SPO_UNCONNECTED; + wire NLW_plm_dfm_deframe1_dwbuf_L2B4_SPO_UNCONNECTED; + wire NLW_plm_dfm_deframe1_dwbuf_L2B5_SPO_UNCONNECTED; + wire NLW_plm_dfm_deframe1_dwbuf_L2B6_SPO_UNCONNECTED; + wire NLW_plm_dfm_deframe1_dwbuf_L2B7_SPO_UNCONNECTED; + wire NLW_plm_dfm_deframe1_dwbuf_L3B0_SPO_UNCONNECTED; + wire NLW_plm_dfm_deframe1_dwbuf_L3B1_SPO_UNCONNECTED; + wire NLW_plm_dfm_deframe1_dwbuf_L3B2_SPO_UNCONNECTED; + wire NLW_plm_dfm_deframe1_dwbuf_L3B3_SPO_UNCONNECTED; + wire NLW_plm_dfm_deframe1_dwbuf_L3B4_SPO_UNCONNECTED; + wire NLW_plm_dfm_deframe1_dwbuf_L3B5_SPO_UNCONNECTED; + wire NLW_plm_dfm_deframe1_dwbuf_L3B6_SPO_UNCONNECTED; + wire NLW_plm_dfm_deframe1_dwbuf_L3B7_SPO_UNCONNECTED; + wire NLW_plm_dfm_deframe1_dwbuf_L3S0_SPO_UNCONNECTED; + wire NLW_plm_dfm_deframe1_dwbuf_L3S1_SPO_UNCONNECTED; + wire NLW_com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_srlrow_0__srlcol_0__srlinst_Q15_UNCONNECTED; + wire NLW_com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_srlrow_0__srlcol_3__srlinst_Q15_UNCONNECTED; + wire NLW_com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_srlrow_0__srlcol_2__srlinst_Q15_UNCONNECTED; + wire NLW_com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_srlrow_0__srlcol_1__srlinst_Q15_UNCONNECTED; + wire NLW_com_tlm_u_tlm_tx_vc0_buf_pool_errfwd_0_I_1_SPO_UNCONNECTED; + wire NLW_com_tlm_u_tlm_tx_vc0_buf_pool_srl_retry_retry_fifo_srlrow_0__srlcol_0__srlinst_Q15_UNCONNECTED; + wire NLW_com_tlm_u_tlm_tx_vc0_buf_pool_srl_retry_retry_fifo_srlrow_0__srlcol_9__srlinst_Q15_UNCONNECTED; + wire NLW_com_tlm_u_tlm_tx_vc0_buf_pool_srl_retry_retry_fifo_srlrow_0__srlcol_5__srlinst_Q15_UNCONNECTED; + wire NLW_com_tlm_u_tlm_tx_vc0_buf_pool_srl_retry_retry_fifo_srlrow_0__srlcol_1__srlinst_Q15_UNCONNECTED; + wire NLW_com_tlm_u_tlm_tx_vc0_buf_pool_srl_retry_retry_fifo_srlrow_0__srlcol_10__srlinst_Q15_UNCONNECTED; + wire NLW_com_tlm_u_tlm_tx_vc0_buf_pool_srl_retry_retry_fifo_srlrow_0__srlcol_6__srlinst_Q15_UNCONNECTED; + wire NLW_com_tlm_u_tlm_tx_vc0_buf_pool_srl_retry_retry_fifo_srlrow_0__srlcol_2__srlinst_Q15_UNCONNECTED; + wire NLW_com_tlm_u_tlm_tx_vc0_buf_pool_srl_retry_retry_fifo_srlrow_0__srlcol_11__srlinst_Q15_UNCONNECTED; + wire NLW_com_tlm_u_tlm_tx_vc0_buf_pool_srl_retry_retry_fifo_srlrow_0__srlcol_7__srlinst_Q15_UNCONNECTED; + wire NLW_com_tlm_u_tlm_tx_vc0_buf_pool_srl_retry_retry_fifo_srlrow_0__srlcol_3__srlinst_Q15_UNCONNECTED; + wire NLW_com_tlm_u_tlm_tx_vc0_buf_pool_srl_retry_retry_fifo_srlrow_0__srlcol_12__srlinst_Q15_UNCONNECTED; + wire NLW_com_tlm_u_tlm_tx_vc0_buf_pool_srl_retry_retry_fifo_srlrow_0__srlcol_8__srlinst_Q15_UNCONNECTED; + wire NLW_com_tlm_u_tlm_tx_vc0_buf_pool_srl_retry_retry_fifo_srlrow_0__srlcol_4__srlinst_Q15_UNCONNECTED; + wire NLW_com_tlm_u_tlm_tx_vc0_buf_pool_bram_0__size4_bram_array_ram_row_0__block_ram_0__ram1024x18_bram_DOPA_1__UNCONNECTED; + wire NLW_com_tlm_u_tlm_tx_vc0_buf_pool_bram_0__size4_bram_array_ram_row_0__block_ram_0__ram1024x18_bram_DOPA_0__UNCONNECTED; + wire NLW_com_tlm_u_tlm_tx_vc0_buf_pool_bram_0__size4_bram_array_ram_row_0__block_ram_0__ram1024x18_bram_DOA_15__UNCONNECTED; + wire NLW_com_tlm_u_tlm_tx_vc0_buf_pool_bram_0__size4_bram_array_ram_row_0__block_ram_0__ram1024x18_bram_DOA_14__UNCONNECTED; + wire NLW_com_tlm_u_tlm_tx_vc0_buf_pool_bram_0__size4_bram_array_ram_row_0__block_ram_0__ram1024x18_bram_DOA_13__UNCONNECTED; + wire NLW_com_tlm_u_tlm_tx_vc0_buf_pool_bram_0__size4_bram_array_ram_row_0__block_ram_0__ram1024x18_bram_DOA_12__UNCONNECTED; + wire NLW_com_tlm_u_tlm_tx_vc0_buf_pool_bram_0__size4_bram_array_ram_row_0__block_ram_0__ram1024x18_bram_DOA_11__UNCONNECTED; + wire NLW_com_tlm_u_tlm_tx_vc0_buf_pool_bram_0__size4_bram_array_ram_row_0__block_ram_0__ram1024x18_bram_DOA_10__UNCONNECTED; + wire NLW_com_tlm_u_tlm_tx_vc0_buf_pool_bram_0__size4_bram_array_ram_row_0__block_ram_0__ram1024x18_bram_DOA_9__UNCONNECTED; + wire NLW_com_tlm_u_tlm_tx_vc0_buf_pool_bram_0__size4_bram_array_ram_row_0__block_ram_0__ram1024x18_bram_DOA_8__UNCONNECTED; + wire NLW_com_tlm_u_tlm_tx_vc0_buf_pool_bram_0__size4_bram_array_ram_row_0__block_ram_0__ram1024x18_bram_DOA_7__UNCONNECTED; + wire NLW_com_tlm_u_tlm_tx_vc0_buf_pool_bram_0__size4_bram_array_ram_row_0__block_ram_0__ram1024x18_bram_DOA_6__UNCONNECTED; + wire NLW_com_tlm_u_tlm_tx_vc0_buf_pool_bram_0__size4_bram_array_ram_row_0__block_ram_0__ram1024x18_bram_DOA_5__UNCONNECTED; + wire NLW_com_tlm_u_tlm_tx_vc0_buf_pool_bram_0__size4_bram_array_ram_row_0__block_ram_0__ram1024x18_bram_DOA_4__UNCONNECTED; + wire NLW_com_tlm_u_tlm_tx_vc0_buf_pool_bram_0__size4_bram_array_ram_row_0__block_ram_0__ram1024x18_bram_DOA_3__UNCONNECTED; + wire NLW_com_tlm_u_tlm_tx_vc0_buf_pool_bram_0__size4_bram_array_ram_row_0__block_ram_0__ram1024x18_bram_DOA_2__UNCONNECTED; + wire NLW_com_tlm_u_tlm_tx_vc0_buf_pool_bram_0__size4_bram_array_ram_row_0__block_ram_0__ram1024x18_bram_DOA_1__UNCONNECTED; + wire NLW_com_tlm_u_tlm_tx_vc0_buf_pool_bram_0__size4_bram_array_ram_row_0__block_ram_0__ram1024x18_bram_DOA_0__UNCONNECTED; + wire NLW_com_tlm_u_tlm_tx_vc0_buf_pool_bram_0__size4_bram_array_ram_row_0__block_ram_1__ram1024x18_bram_DOPA_1__UNCONNECTED; + wire NLW_com_tlm_u_tlm_tx_vc0_buf_pool_bram_0__size4_bram_array_ram_row_0__block_ram_1__ram1024x18_bram_DOPA_0__UNCONNECTED; + wire NLW_com_tlm_u_tlm_tx_vc0_buf_pool_bram_0__size4_bram_array_ram_row_0__block_ram_1__ram1024x18_bram_DOA_15__UNCONNECTED; + wire NLW_com_tlm_u_tlm_tx_vc0_buf_pool_bram_0__size4_bram_array_ram_row_0__block_ram_1__ram1024x18_bram_DOA_14__UNCONNECTED; + wire NLW_com_tlm_u_tlm_tx_vc0_buf_pool_bram_0__size4_bram_array_ram_row_0__block_ram_1__ram1024x18_bram_DOA_13__UNCONNECTED; + wire NLW_com_tlm_u_tlm_tx_vc0_buf_pool_bram_0__size4_bram_array_ram_row_0__block_ram_1__ram1024x18_bram_DOA_12__UNCONNECTED; + wire NLW_com_tlm_u_tlm_tx_vc0_buf_pool_bram_0__size4_bram_array_ram_row_0__block_ram_1__ram1024x18_bram_DOA_11__UNCONNECTED; + wire NLW_com_tlm_u_tlm_tx_vc0_buf_pool_bram_0__size4_bram_array_ram_row_0__block_ram_1__ram1024x18_bram_DOA_10__UNCONNECTED; + wire NLW_com_tlm_u_tlm_tx_vc0_buf_pool_bram_0__size4_bram_array_ram_row_0__block_ram_1__ram1024x18_bram_DOA_9__UNCONNECTED; + wire NLW_com_tlm_u_tlm_tx_vc0_buf_pool_bram_0__size4_bram_array_ram_row_0__block_ram_1__ram1024x18_bram_DOA_8__UNCONNECTED; + wire NLW_com_tlm_u_tlm_tx_vc0_buf_pool_bram_0__size4_bram_array_ram_row_0__block_ram_1__ram1024x18_bram_DOA_7__UNCONNECTED; + wire NLW_com_tlm_u_tlm_tx_vc0_buf_pool_bram_0__size4_bram_array_ram_row_0__block_ram_1__ram1024x18_bram_DOA_6__UNCONNECTED; + wire NLW_com_tlm_u_tlm_tx_vc0_buf_pool_bram_0__size4_bram_array_ram_row_0__block_ram_1__ram1024x18_bram_DOA_5__UNCONNECTED; + wire NLW_com_tlm_u_tlm_tx_vc0_buf_pool_bram_0__size4_bram_array_ram_row_0__block_ram_1__ram1024x18_bram_DOA_4__UNCONNECTED; + wire NLW_com_tlm_u_tlm_tx_vc0_buf_pool_bram_0__size4_bram_array_ram_row_0__block_ram_1__ram1024x18_bram_DOA_3__UNCONNECTED; + wire NLW_com_tlm_u_tlm_tx_vc0_buf_pool_bram_0__size4_bram_array_ram_row_0__block_ram_1__ram1024x18_bram_DOA_2__UNCONNECTED; + wire NLW_com_tlm_u_tlm_tx_vc0_buf_pool_bram_0__size4_bram_array_ram_row_0__block_ram_1__ram1024x18_bram_DOA_1__UNCONNECTED; + wire NLW_com_tlm_u_tlm_tx_vc0_buf_pool_bram_0__size4_bram_array_ram_row_0__block_ram_1__ram1024x18_bram_DOA_0__UNCONNECTED; + wire NLW_com_tlm_u_tlm_tx_vc0_buf_pool_bram_0__size4_bram_array_ram_row_0__block_ram_2__ram1024x18_bram_DOPA_1__UNCONNECTED; + wire NLW_com_tlm_u_tlm_tx_vc0_buf_pool_bram_0__size4_bram_array_ram_row_0__block_ram_2__ram1024x18_bram_DOPA_0__UNCONNECTED; + wire NLW_com_tlm_u_tlm_tx_vc0_buf_pool_bram_0__size4_bram_array_ram_row_0__block_ram_2__ram1024x18_bram_DOA_15__UNCONNECTED; + wire NLW_com_tlm_u_tlm_tx_vc0_buf_pool_bram_0__size4_bram_array_ram_row_0__block_ram_2__ram1024x18_bram_DOA_14__UNCONNECTED; + wire NLW_com_tlm_u_tlm_tx_vc0_buf_pool_bram_0__size4_bram_array_ram_row_0__block_ram_2__ram1024x18_bram_DOA_13__UNCONNECTED; + wire NLW_com_tlm_u_tlm_tx_vc0_buf_pool_bram_0__size4_bram_array_ram_row_0__block_ram_2__ram1024x18_bram_DOA_12__UNCONNECTED; + wire NLW_com_tlm_u_tlm_tx_vc0_buf_pool_bram_0__size4_bram_array_ram_row_0__block_ram_2__ram1024x18_bram_DOA_11__UNCONNECTED; + wire NLW_com_tlm_u_tlm_tx_vc0_buf_pool_bram_0__size4_bram_array_ram_row_0__block_ram_2__ram1024x18_bram_DOA_10__UNCONNECTED; + wire NLW_com_tlm_u_tlm_tx_vc0_buf_pool_bram_0__size4_bram_array_ram_row_0__block_ram_2__ram1024x18_bram_DOA_9__UNCONNECTED; + wire NLW_com_tlm_u_tlm_tx_vc0_buf_pool_bram_0__size4_bram_array_ram_row_0__block_ram_2__ram1024x18_bram_DOA_8__UNCONNECTED; + wire NLW_com_tlm_u_tlm_tx_vc0_buf_pool_bram_0__size4_bram_array_ram_row_0__block_ram_2__ram1024x18_bram_DOA_7__UNCONNECTED; + wire NLW_com_tlm_u_tlm_tx_vc0_buf_pool_bram_0__size4_bram_array_ram_row_0__block_ram_2__ram1024x18_bram_DOA_6__UNCONNECTED; + wire NLW_com_tlm_u_tlm_tx_vc0_buf_pool_bram_0__size4_bram_array_ram_row_0__block_ram_2__ram1024x18_bram_DOA_5__UNCONNECTED; + wire NLW_com_tlm_u_tlm_tx_vc0_buf_pool_bram_0__size4_bram_array_ram_row_0__block_ram_2__ram1024x18_bram_DOA_4__UNCONNECTED; + wire NLW_com_tlm_u_tlm_tx_vc0_buf_pool_bram_0__size4_bram_array_ram_row_0__block_ram_2__ram1024x18_bram_DOA_3__UNCONNECTED; + wire NLW_com_tlm_u_tlm_tx_vc0_buf_pool_bram_0__size4_bram_array_ram_row_0__block_ram_2__ram1024x18_bram_DOA_2__UNCONNECTED; + wire NLW_com_tlm_u_tlm_tx_vc0_buf_pool_bram_0__size4_bram_array_ram_row_0__block_ram_2__ram1024x18_bram_DOA_1__UNCONNECTED; + wire NLW_com_tlm_u_tlm_tx_vc0_buf_pool_bram_0__size4_bram_array_ram_row_0__block_ram_2__ram1024x18_bram_DOA_0__UNCONNECTED; + wire NLW_com_tlm_u_tlm_tx_vc0_buf_pool_bram_0__size4_bram_array_ram_row_0__block_ram_3__ram1024x18_bram_DOPA_1__UNCONNECTED; + wire NLW_com_tlm_u_tlm_tx_vc0_buf_pool_bram_0__size4_bram_array_ram_row_0__block_ram_3__ram1024x18_bram_DOPA_0__UNCONNECTED; + wire NLW_com_tlm_u_tlm_tx_vc0_buf_pool_bram_0__size4_bram_array_ram_row_0__block_ram_3__ram1024x18_bram_DOPB_1__UNCONNECTED; + wire NLW_com_tlm_u_tlm_tx_vc0_buf_pool_bram_0__size4_bram_array_ram_row_0__block_ram_3__ram1024x18_bram_DOPB_0__UNCONNECTED; + wire NLW_com_tlm_u_tlm_tx_vc0_buf_pool_bram_0__size4_bram_array_ram_row_0__block_ram_3__ram1024x18_bram_DOA_15__UNCONNECTED; + wire NLW_com_tlm_u_tlm_tx_vc0_buf_pool_bram_0__size4_bram_array_ram_row_0__block_ram_3__ram1024x18_bram_DOA_14__UNCONNECTED; + wire NLW_com_tlm_u_tlm_tx_vc0_buf_pool_bram_0__size4_bram_array_ram_row_0__block_ram_3__ram1024x18_bram_DOA_13__UNCONNECTED; + wire NLW_com_tlm_u_tlm_tx_vc0_buf_pool_bram_0__size4_bram_array_ram_row_0__block_ram_3__ram1024x18_bram_DOA_12__UNCONNECTED; + wire NLW_com_tlm_u_tlm_tx_vc0_buf_pool_bram_0__size4_bram_array_ram_row_0__block_ram_3__ram1024x18_bram_DOA_11__UNCONNECTED; + wire NLW_com_tlm_u_tlm_tx_vc0_buf_pool_bram_0__size4_bram_array_ram_row_0__block_ram_3__ram1024x18_bram_DOA_10__UNCONNECTED; + wire NLW_com_tlm_u_tlm_tx_vc0_buf_pool_bram_0__size4_bram_array_ram_row_0__block_ram_3__ram1024x18_bram_DOA_9__UNCONNECTED; + wire NLW_com_tlm_u_tlm_tx_vc0_buf_pool_bram_0__size4_bram_array_ram_row_0__block_ram_3__ram1024x18_bram_DOA_8__UNCONNECTED; + wire NLW_com_tlm_u_tlm_tx_vc0_buf_pool_bram_0__size4_bram_array_ram_row_0__block_ram_3__ram1024x18_bram_DOA_7__UNCONNECTED; + wire NLW_com_tlm_u_tlm_tx_vc0_buf_pool_bram_0__size4_bram_array_ram_row_0__block_ram_3__ram1024x18_bram_DOA_6__UNCONNECTED; + wire NLW_com_tlm_u_tlm_tx_vc0_buf_pool_bram_0__size4_bram_array_ram_row_0__block_ram_3__ram1024x18_bram_DOA_5__UNCONNECTED; + wire NLW_com_tlm_u_tlm_tx_vc0_buf_pool_bram_0__size4_bram_array_ram_row_0__block_ram_3__ram1024x18_bram_DOA_4__UNCONNECTED; + wire NLW_com_tlm_u_tlm_tx_vc0_buf_pool_bram_0__size4_bram_array_ram_row_0__block_ram_3__ram1024x18_bram_DOA_3__UNCONNECTED; + wire NLW_com_tlm_u_tlm_tx_vc0_buf_pool_bram_0__size4_bram_array_ram_row_0__block_ram_3__ram1024x18_bram_DOA_2__UNCONNECTED; + wire NLW_com_tlm_u_tlm_tx_vc0_buf_pool_bram_0__size4_bram_array_ram_row_0__block_ram_3__ram1024x18_bram_DOA_1__UNCONNECTED; + wire NLW_com_tlm_u_tlm_tx_vc0_buf_pool_bram_0__size4_bram_array_ram_row_0__block_ram_3__ram1024x18_bram_DOA_0__UNCONNECTED; + wire NLW_com_tlm_u_tlm_tx_vc0_buf_pool_bram_0__size4_bram_array_ram_row_0__block_ram_3__ram1024x18_bram_DOB_15__UNCONNECTED; + wire NLW_com_tlm_u_tlm_tx_vc0_buf_pool_bram_1__size4_bram_array_ram_row_0__block_ram_0__ram1024x18_bram_DOPA_1__UNCONNECTED; + wire NLW_com_tlm_u_tlm_tx_vc0_buf_pool_bram_1__size4_bram_array_ram_row_0__block_ram_0__ram1024x18_bram_DOPA_0__UNCONNECTED; + wire NLW_com_tlm_u_tlm_tx_vc0_buf_pool_bram_1__size4_bram_array_ram_row_0__block_ram_0__ram1024x18_bram_DOA_15__UNCONNECTED; + wire NLW_com_tlm_u_tlm_tx_vc0_buf_pool_bram_1__size4_bram_array_ram_row_0__block_ram_0__ram1024x18_bram_DOA_14__UNCONNECTED; + wire NLW_com_tlm_u_tlm_tx_vc0_buf_pool_bram_1__size4_bram_array_ram_row_0__block_ram_0__ram1024x18_bram_DOA_13__UNCONNECTED; + wire NLW_com_tlm_u_tlm_tx_vc0_buf_pool_bram_1__size4_bram_array_ram_row_0__block_ram_0__ram1024x18_bram_DOA_12__UNCONNECTED; + wire NLW_com_tlm_u_tlm_tx_vc0_buf_pool_bram_1__size4_bram_array_ram_row_0__block_ram_0__ram1024x18_bram_DOA_11__UNCONNECTED; + wire NLW_com_tlm_u_tlm_tx_vc0_buf_pool_bram_1__size4_bram_array_ram_row_0__block_ram_0__ram1024x18_bram_DOA_10__UNCONNECTED; + wire NLW_com_tlm_u_tlm_tx_vc0_buf_pool_bram_1__size4_bram_array_ram_row_0__block_ram_0__ram1024x18_bram_DOA_9__UNCONNECTED; + wire NLW_com_tlm_u_tlm_tx_vc0_buf_pool_bram_1__size4_bram_array_ram_row_0__block_ram_0__ram1024x18_bram_DOA_8__UNCONNECTED; + wire NLW_com_tlm_u_tlm_tx_vc0_buf_pool_bram_1__size4_bram_array_ram_row_0__block_ram_0__ram1024x18_bram_DOA_7__UNCONNECTED; + wire NLW_com_tlm_u_tlm_tx_vc0_buf_pool_bram_1__size4_bram_array_ram_row_0__block_ram_0__ram1024x18_bram_DOA_6__UNCONNECTED; + wire NLW_com_tlm_u_tlm_tx_vc0_buf_pool_bram_1__size4_bram_array_ram_row_0__block_ram_0__ram1024x18_bram_DOA_5__UNCONNECTED; + wire NLW_com_tlm_u_tlm_tx_vc0_buf_pool_bram_1__size4_bram_array_ram_row_0__block_ram_0__ram1024x18_bram_DOA_4__UNCONNECTED; + wire NLW_com_tlm_u_tlm_tx_vc0_buf_pool_bram_1__size4_bram_array_ram_row_0__block_ram_0__ram1024x18_bram_DOA_3__UNCONNECTED; + wire NLW_com_tlm_u_tlm_tx_vc0_buf_pool_bram_1__size4_bram_array_ram_row_0__block_ram_0__ram1024x18_bram_DOA_2__UNCONNECTED; + wire NLW_com_tlm_u_tlm_tx_vc0_buf_pool_bram_1__size4_bram_array_ram_row_0__block_ram_0__ram1024x18_bram_DOA_1__UNCONNECTED; + wire NLW_com_tlm_u_tlm_tx_vc0_buf_pool_bram_1__size4_bram_array_ram_row_0__block_ram_0__ram1024x18_bram_DOA_0__UNCONNECTED; + wire NLW_com_tlm_u_tlm_tx_vc0_buf_pool_bram_1__size4_bram_array_ram_row_0__block_ram_1__ram1024x18_bram_DOPA_1__UNCONNECTED; + wire NLW_com_tlm_u_tlm_tx_vc0_buf_pool_bram_1__size4_bram_array_ram_row_0__block_ram_1__ram1024x18_bram_DOPA_0__UNCONNECTED; + wire NLW_com_tlm_u_tlm_tx_vc0_buf_pool_bram_1__size4_bram_array_ram_row_0__block_ram_1__ram1024x18_bram_DOA_15__UNCONNECTED; + wire NLW_com_tlm_u_tlm_tx_vc0_buf_pool_bram_1__size4_bram_array_ram_row_0__block_ram_1__ram1024x18_bram_DOA_14__UNCONNECTED; + wire NLW_com_tlm_u_tlm_tx_vc0_buf_pool_bram_1__size4_bram_array_ram_row_0__block_ram_1__ram1024x18_bram_DOA_13__UNCONNECTED; + wire NLW_com_tlm_u_tlm_tx_vc0_buf_pool_bram_1__size4_bram_array_ram_row_0__block_ram_1__ram1024x18_bram_DOA_12__UNCONNECTED; + wire NLW_com_tlm_u_tlm_tx_vc0_buf_pool_bram_1__size4_bram_array_ram_row_0__block_ram_1__ram1024x18_bram_DOA_11__UNCONNECTED; + wire NLW_com_tlm_u_tlm_tx_vc0_buf_pool_bram_1__size4_bram_array_ram_row_0__block_ram_1__ram1024x18_bram_DOA_10__UNCONNECTED; + wire NLW_com_tlm_u_tlm_tx_vc0_buf_pool_bram_1__size4_bram_array_ram_row_0__block_ram_1__ram1024x18_bram_DOA_9__UNCONNECTED; + wire NLW_com_tlm_u_tlm_tx_vc0_buf_pool_bram_1__size4_bram_array_ram_row_0__block_ram_1__ram1024x18_bram_DOA_8__UNCONNECTED; + wire NLW_com_tlm_u_tlm_tx_vc0_buf_pool_bram_1__size4_bram_array_ram_row_0__block_ram_1__ram1024x18_bram_DOA_7__UNCONNECTED; + wire NLW_com_tlm_u_tlm_tx_vc0_buf_pool_bram_1__size4_bram_array_ram_row_0__block_ram_1__ram1024x18_bram_DOA_6__UNCONNECTED; + wire NLW_com_tlm_u_tlm_tx_vc0_buf_pool_bram_1__size4_bram_array_ram_row_0__block_ram_1__ram1024x18_bram_DOA_5__UNCONNECTED; + wire NLW_com_tlm_u_tlm_tx_vc0_buf_pool_bram_1__size4_bram_array_ram_row_0__block_ram_1__ram1024x18_bram_DOA_4__UNCONNECTED; + wire NLW_com_tlm_u_tlm_tx_vc0_buf_pool_bram_1__size4_bram_array_ram_row_0__block_ram_1__ram1024x18_bram_DOA_3__UNCONNECTED; + wire NLW_com_tlm_u_tlm_tx_vc0_buf_pool_bram_1__size4_bram_array_ram_row_0__block_ram_1__ram1024x18_bram_DOA_2__UNCONNECTED; + wire NLW_com_tlm_u_tlm_tx_vc0_buf_pool_bram_1__size4_bram_array_ram_row_0__block_ram_1__ram1024x18_bram_DOA_1__UNCONNECTED; + wire NLW_com_tlm_u_tlm_tx_vc0_buf_pool_bram_1__size4_bram_array_ram_row_0__block_ram_1__ram1024x18_bram_DOA_0__UNCONNECTED; + wire NLW_com_tlm_u_tlm_tx_vc0_buf_pool_bram_1__size4_bram_array_ram_row_0__block_ram_2__ram1024x18_bram_DOPA_1__UNCONNECTED; + wire NLW_com_tlm_u_tlm_tx_vc0_buf_pool_bram_1__size4_bram_array_ram_row_0__block_ram_2__ram1024x18_bram_DOPA_0__UNCONNECTED; + wire NLW_com_tlm_u_tlm_tx_vc0_buf_pool_bram_1__size4_bram_array_ram_row_0__block_ram_2__ram1024x18_bram_DOA_15__UNCONNECTED; + wire NLW_com_tlm_u_tlm_tx_vc0_buf_pool_bram_1__size4_bram_array_ram_row_0__block_ram_2__ram1024x18_bram_DOA_14__UNCONNECTED; + wire NLW_com_tlm_u_tlm_tx_vc0_buf_pool_bram_1__size4_bram_array_ram_row_0__block_ram_2__ram1024x18_bram_DOA_13__UNCONNECTED; + wire NLW_com_tlm_u_tlm_tx_vc0_buf_pool_bram_1__size4_bram_array_ram_row_0__block_ram_2__ram1024x18_bram_DOA_12__UNCONNECTED; + wire NLW_com_tlm_u_tlm_tx_vc0_buf_pool_bram_1__size4_bram_array_ram_row_0__block_ram_2__ram1024x18_bram_DOA_11__UNCONNECTED; + wire NLW_com_tlm_u_tlm_tx_vc0_buf_pool_bram_1__size4_bram_array_ram_row_0__block_ram_2__ram1024x18_bram_DOA_10__UNCONNECTED; + wire NLW_com_tlm_u_tlm_tx_vc0_buf_pool_bram_1__size4_bram_array_ram_row_0__block_ram_2__ram1024x18_bram_DOA_9__UNCONNECTED; + wire NLW_com_tlm_u_tlm_tx_vc0_buf_pool_bram_1__size4_bram_array_ram_row_0__block_ram_2__ram1024x18_bram_DOA_8__UNCONNECTED; + wire NLW_com_tlm_u_tlm_tx_vc0_buf_pool_bram_1__size4_bram_array_ram_row_0__block_ram_2__ram1024x18_bram_DOA_7__UNCONNECTED; + wire NLW_com_tlm_u_tlm_tx_vc0_buf_pool_bram_1__size4_bram_array_ram_row_0__block_ram_2__ram1024x18_bram_DOA_6__UNCONNECTED; + wire NLW_com_tlm_u_tlm_tx_vc0_buf_pool_bram_1__size4_bram_array_ram_row_0__block_ram_2__ram1024x18_bram_DOA_5__UNCONNECTED; + wire NLW_com_tlm_u_tlm_tx_vc0_buf_pool_bram_1__size4_bram_array_ram_row_0__block_ram_2__ram1024x18_bram_DOA_4__UNCONNECTED; + wire NLW_com_tlm_u_tlm_tx_vc0_buf_pool_bram_1__size4_bram_array_ram_row_0__block_ram_2__ram1024x18_bram_DOA_3__UNCONNECTED; + wire NLW_com_tlm_u_tlm_tx_vc0_buf_pool_bram_1__size4_bram_array_ram_row_0__block_ram_2__ram1024x18_bram_DOA_2__UNCONNECTED; + wire NLW_com_tlm_u_tlm_tx_vc0_buf_pool_bram_1__size4_bram_array_ram_row_0__block_ram_2__ram1024x18_bram_DOA_1__UNCONNECTED; + wire NLW_com_tlm_u_tlm_tx_vc0_buf_pool_bram_1__size4_bram_array_ram_row_0__block_ram_2__ram1024x18_bram_DOA_0__UNCONNECTED; + wire NLW_com_tlm_u_tlm_tx_vc0_buf_pool_bram_1__size4_bram_array_ram_row_0__block_ram_3__ram1024x18_bram_DOPA_1__UNCONNECTED; + wire NLW_com_tlm_u_tlm_tx_vc0_buf_pool_bram_1__size4_bram_array_ram_row_0__block_ram_3__ram1024x18_bram_DOPA_0__UNCONNECTED; + wire NLW_com_tlm_u_tlm_tx_vc0_buf_pool_bram_1__size4_bram_array_ram_row_0__block_ram_3__ram1024x18_bram_DOPB_1__UNCONNECTED; + wire NLW_com_tlm_u_tlm_tx_vc0_buf_pool_bram_1__size4_bram_array_ram_row_0__block_ram_3__ram1024x18_bram_DOPB_0__UNCONNECTED; + wire NLW_com_tlm_u_tlm_tx_vc0_buf_pool_bram_1__size4_bram_array_ram_row_0__block_ram_3__ram1024x18_bram_DOA_15__UNCONNECTED; + wire NLW_com_tlm_u_tlm_tx_vc0_buf_pool_bram_1__size4_bram_array_ram_row_0__block_ram_3__ram1024x18_bram_DOA_14__UNCONNECTED; + wire NLW_com_tlm_u_tlm_tx_vc0_buf_pool_bram_1__size4_bram_array_ram_row_0__block_ram_3__ram1024x18_bram_DOA_13__UNCONNECTED; + wire NLW_com_tlm_u_tlm_tx_vc0_buf_pool_bram_1__size4_bram_array_ram_row_0__block_ram_3__ram1024x18_bram_DOA_12__UNCONNECTED; + wire NLW_com_tlm_u_tlm_tx_vc0_buf_pool_bram_1__size4_bram_array_ram_row_0__block_ram_3__ram1024x18_bram_DOA_11__UNCONNECTED; + wire NLW_com_tlm_u_tlm_tx_vc0_buf_pool_bram_1__size4_bram_array_ram_row_0__block_ram_3__ram1024x18_bram_DOA_10__UNCONNECTED; + wire NLW_com_tlm_u_tlm_tx_vc0_buf_pool_bram_1__size4_bram_array_ram_row_0__block_ram_3__ram1024x18_bram_DOA_9__UNCONNECTED; + wire NLW_com_tlm_u_tlm_tx_vc0_buf_pool_bram_1__size4_bram_array_ram_row_0__block_ram_3__ram1024x18_bram_DOA_8__UNCONNECTED; + wire NLW_com_tlm_u_tlm_tx_vc0_buf_pool_bram_1__size4_bram_array_ram_row_0__block_ram_3__ram1024x18_bram_DOA_7__UNCONNECTED; + wire NLW_com_tlm_u_tlm_tx_vc0_buf_pool_bram_1__size4_bram_array_ram_row_0__block_ram_3__ram1024x18_bram_DOA_6__UNCONNECTED; + wire NLW_com_tlm_u_tlm_tx_vc0_buf_pool_bram_1__size4_bram_array_ram_row_0__block_ram_3__ram1024x18_bram_DOA_5__UNCONNECTED; + wire NLW_com_tlm_u_tlm_tx_vc0_buf_pool_bram_1__size4_bram_array_ram_row_0__block_ram_3__ram1024x18_bram_DOA_4__UNCONNECTED; + wire NLW_com_tlm_u_tlm_tx_vc0_buf_pool_bram_1__size4_bram_array_ram_row_0__block_ram_3__ram1024x18_bram_DOA_3__UNCONNECTED; + wire NLW_com_tlm_u_tlm_tx_vc0_buf_pool_bram_1__size4_bram_array_ram_row_0__block_ram_3__ram1024x18_bram_DOA_2__UNCONNECTED; + wire NLW_com_tlm_u_tlm_tx_vc0_buf_pool_bram_1__size4_bram_array_ram_row_0__block_ram_3__ram1024x18_bram_DOA_1__UNCONNECTED; + wire NLW_com_tlm_u_tlm_tx_vc0_buf_pool_bram_1__size4_bram_array_ram_row_0__block_ram_3__ram1024x18_bram_DOA_0__UNCONNECTED; + wire NLW_com_tlm_u_tlm_tx_vc0_buf_pool_bram_1__size4_bram_array_ram_row_0__block_ram_3__ram1024x18_bram_DOB_15__UNCONNECTED; + wire NLW_com_tlm_u_tlm_tx_vc0_token_fifo_t_fifo_srlrow_0__srlcol_0__srlinst_Q15_UNCONNECTED; + wire NLW_com_tlm_u_tlm_tx_vc0_token_fifo_t_fifo_srlrow_0__srlcol_3__srlinst_Q15_UNCONNECTED; + wire NLW_com_tlm_u_tlm_tx_vc0_token_fifo_t_fifo_srlrow_0__srlcol_2__srlinst_Q15_UNCONNECTED; + wire NLW_com_tlm_u_tlm_tx_vc0_token_fifo_t_fifo_srlrow_0__srlcol_1__srlinst_Q15_UNCONNECTED; + wire NLW_com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_srlrow_0__srlcol_0__srlinst_Q15_UNCONNECTED; + wire NLW_com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_srlrow_0__srlcol_9__srlinst_Q15_UNCONNECTED; + wire NLW_com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_srlrow_0__srlcol_5__srlinst_Q15_UNCONNECTED; + wire NLW_com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_srlrow_0__srlcol_1__srlinst_Q15_UNCONNECTED; + wire NLW_com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_srlrow_0__srlcol_10__srlinst_Q15_UNCONNECTED; + wire NLW_com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_srlrow_0__srlcol_6__srlinst_Q15_UNCONNECTED; + wire NLW_com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_srlrow_0__srlcol_2__srlinst_Q15_UNCONNECTED; + wire NLW_com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_srlrow_0__srlcol_11__srlinst_Q15_UNCONNECTED; + wire NLW_com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_srlrow_0__srlcol_7__srlinst_Q15_UNCONNECTED; + wire NLW_com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_srlrow_0__srlcol_3__srlinst_Q15_UNCONNECTED; + wire NLW_com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_srlrow_0__srlcol_12__srlinst_Q15_UNCONNECTED; + wire NLW_com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_srlrow_0__srlcol_8__srlinst_Q15_UNCONNECTED; + wire NLW_com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_srlrow_0__srlcol_4__srlinst_Q15_UNCONNECTED; + wire NLW_com_tlm_u_tlm_tx_vc0_frm_seq_bq_fifo_srlrow_0__srlcol_0__srlinst_Q15_UNCONNECTED; + wire NLW_com_tlm_u_tlm_tx_vc0_frm_seq_bq_fifo_srlrow_0__srlcol_5__srlinst_Q15_UNCONNECTED; + wire NLW_com_tlm_u_tlm_tx_vc0_frm_seq_bq_fifo_srlrow_0__srlcol_9__srlinst_Q15_UNCONNECTED; + wire NLW_com_tlm_u_tlm_tx_vc0_frm_seq_bq_fifo_srlrow_0__srlcol_10__srlinst_Q15_UNCONNECTED; + wire NLW_com_tlm_u_tlm_tx_vc0_frm_seq_bq_fifo_srlrow_0__srlcol_6__srlinst_Q15_UNCONNECTED; + wire NLW_com_tlm_u_tlm_tx_vc0_frm_seq_bq_fifo_srlrow_0__srlcol_7__srlinst_Q15_UNCONNECTED; + wire NLW_com_tlm_u_tlm_tx_vc0_frm_seq_bq_fifo_srlrow_0__srlcol_4__srlinst_Q15_UNCONNECTED; + wire NLW_com_tlm_u_tlm_tx_vc0_frm_seq_bq_fifo_srlrow_0__srlcol_3__srlinst_Q15_UNCONNECTED; + wire NLW_com_tlm_u_tlm_tx_vc0_frm_seq_bq_fifo_srlrow_0__srlcol_8__srlinst_Q15_UNCONNECTED; + wire NLW_com_tlm_u_tlm_tx_vc0_frm_seq_bq_fifo_srlrow_0__srlcol_1__srlinst_Q15_UNCONNECTED; + wire NLW_com_tlm_u_tlm_tx_vc0_frm_seq_bq_fifo_srlrow_0__srlcol_2__srlinst_Q15_UNCONNECTED; + wire NLW_com_tlm_u_tlm_tx_vc0_frm_seq_sq_fifo_srlrow_0__srlcol_0__srlinst_Q15_UNCONNECTED; + wire NLW_com_tlm_u_tlm_tx_vc0_frm_seq_sq_fifo_srlrow_0__srlcol_3__srlinst_Q15_UNCONNECTED; + wire NLW_com_tlm_u_tlm_tx_vc0_frm_seq_sq_fifo_srlrow_0__srlcol_2__srlinst_Q15_UNCONNECTED; + wire NLW_com_tlm_u_tlm_tx_vc0_frm_seq_sq_fifo_srlrow_0__srlcol_1__srlinst_Q15_UNCONNECTED; + wire NLW_com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_queue_ram_ram_row_0__block_ram_0__ram1024x18_bram_DOPA_1__UNCONNECTED; + wire NLW_com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_queue_ram_ram_row_0__block_ram_0__ram1024x18_bram_DOPA_0__UNCONNECTED; + wire NLW_com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_queue_ram_ram_row_0__block_ram_0__ram1024x18_bram_DOA_15__UNCONNECTED; + wire NLW_com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_queue_ram_ram_row_0__block_ram_0__ram1024x18_bram_DOA_14__UNCONNECTED; + wire NLW_com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_queue_ram_ram_row_0__block_ram_0__ram1024x18_bram_DOA_13__UNCONNECTED; + wire NLW_com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_queue_ram_ram_row_0__block_ram_0__ram1024x18_bram_DOA_12__UNCONNECTED; + wire NLW_com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_queue_ram_ram_row_0__block_ram_0__ram1024x18_bram_DOA_11__UNCONNECTED; + wire NLW_com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_queue_ram_ram_row_0__block_ram_0__ram1024x18_bram_DOA_10__UNCONNECTED; + wire NLW_com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_queue_ram_ram_row_0__block_ram_0__ram1024x18_bram_DOA_9__UNCONNECTED; + wire NLW_com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_queue_ram_ram_row_0__block_ram_0__ram1024x18_bram_DOA_8__UNCONNECTED; + wire NLW_com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_queue_ram_ram_row_0__block_ram_0__ram1024x18_bram_DOA_7__UNCONNECTED; + wire NLW_com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_queue_ram_ram_row_0__block_ram_0__ram1024x18_bram_DOA_6__UNCONNECTED; + wire NLW_com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_queue_ram_ram_row_0__block_ram_0__ram1024x18_bram_DOA_5__UNCONNECTED; + wire NLW_com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_queue_ram_ram_row_0__block_ram_0__ram1024x18_bram_DOA_4__UNCONNECTED; + wire NLW_com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_queue_ram_ram_row_0__block_ram_0__ram1024x18_bram_DOA_3__UNCONNECTED; + wire NLW_com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_queue_ram_ram_row_0__block_ram_0__ram1024x18_bram_DOA_2__UNCONNECTED; + wire NLW_com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_queue_ram_ram_row_0__block_ram_0__ram1024x18_bram_DOA_1__UNCONNECTED; + wire NLW_com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_queue_ram_ram_row_0__block_ram_0__ram1024x18_bram_DOA_0__UNCONNECTED; + wire NLW_com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_queue_ram_ram_row_0__block_ram_1__ram1024x18_bram_DOPA_1__UNCONNECTED; + wire NLW_com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_queue_ram_ram_row_0__block_ram_1__ram1024x18_bram_DOPA_0__UNCONNECTED; + wire NLW_com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_queue_ram_ram_row_0__block_ram_1__ram1024x18_bram_DOA_15__UNCONNECTED; + wire NLW_com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_queue_ram_ram_row_0__block_ram_1__ram1024x18_bram_DOA_14__UNCONNECTED; + wire NLW_com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_queue_ram_ram_row_0__block_ram_1__ram1024x18_bram_DOA_13__UNCONNECTED; + wire NLW_com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_queue_ram_ram_row_0__block_ram_1__ram1024x18_bram_DOA_12__UNCONNECTED; + wire NLW_com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_queue_ram_ram_row_0__block_ram_1__ram1024x18_bram_DOA_11__UNCONNECTED; + wire NLW_com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_queue_ram_ram_row_0__block_ram_1__ram1024x18_bram_DOA_10__UNCONNECTED; + wire NLW_com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_queue_ram_ram_row_0__block_ram_1__ram1024x18_bram_DOA_9__UNCONNECTED; + wire NLW_com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_queue_ram_ram_row_0__block_ram_1__ram1024x18_bram_DOA_8__UNCONNECTED; + wire NLW_com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_queue_ram_ram_row_0__block_ram_1__ram1024x18_bram_DOA_7__UNCONNECTED; + wire NLW_com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_queue_ram_ram_row_0__block_ram_1__ram1024x18_bram_DOA_6__UNCONNECTED; + wire NLW_com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_queue_ram_ram_row_0__block_ram_1__ram1024x18_bram_DOA_5__UNCONNECTED; + wire NLW_com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_queue_ram_ram_row_0__block_ram_1__ram1024x18_bram_DOA_4__UNCONNECTED; + wire NLW_com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_queue_ram_ram_row_0__block_ram_1__ram1024x18_bram_DOA_3__UNCONNECTED; + wire NLW_com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_queue_ram_ram_row_0__block_ram_1__ram1024x18_bram_DOA_2__UNCONNECTED; + wire NLW_com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_queue_ram_ram_row_0__block_ram_1__ram1024x18_bram_DOA_1__UNCONNECTED; + wire NLW_com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_queue_ram_ram_row_0__block_ram_1__ram1024x18_bram_DOA_0__UNCONNECTED; + wire NLW_com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_queue_ram_ram_row_0__block_ram_2__ram1024x18_bram_DOPA_1__UNCONNECTED; + wire NLW_com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_queue_ram_ram_row_0__block_ram_2__ram1024x18_bram_DOPA_0__UNCONNECTED; + wire NLW_com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_queue_ram_ram_row_0__block_ram_2__ram1024x18_bram_DOA_15__UNCONNECTED; + wire NLW_com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_queue_ram_ram_row_0__block_ram_2__ram1024x18_bram_DOA_14__UNCONNECTED; + wire NLW_com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_queue_ram_ram_row_0__block_ram_2__ram1024x18_bram_DOA_13__UNCONNECTED; + wire NLW_com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_queue_ram_ram_row_0__block_ram_2__ram1024x18_bram_DOA_12__UNCONNECTED; + wire NLW_com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_queue_ram_ram_row_0__block_ram_2__ram1024x18_bram_DOA_11__UNCONNECTED; + wire NLW_com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_queue_ram_ram_row_0__block_ram_2__ram1024x18_bram_DOA_10__UNCONNECTED; + wire NLW_com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_queue_ram_ram_row_0__block_ram_2__ram1024x18_bram_DOA_9__UNCONNECTED; + wire NLW_com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_queue_ram_ram_row_0__block_ram_2__ram1024x18_bram_DOA_8__UNCONNECTED; + wire NLW_com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_queue_ram_ram_row_0__block_ram_2__ram1024x18_bram_DOA_7__UNCONNECTED; + wire NLW_com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_queue_ram_ram_row_0__block_ram_2__ram1024x18_bram_DOA_6__UNCONNECTED; + wire NLW_com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_queue_ram_ram_row_0__block_ram_2__ram1024x18_bram_DOA_5__UNCONNECTED; + wire NLW_com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_queue_ram_ram_row_0__block_ram_2__ram1024x18_bram_DOA_4__UNCONNECTED; + wire NLW_com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_queue_ram_ram_row_0__block_ram_2__ram1024x18_bram_DOA_3__UNCONNECTED; + wire NLW_com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_queue_ram_ram_row_0__block_ram_2__ram1024x18_bram_DOA_2__UNCONNECTED; + wire NLW_com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_queue_ram_ram_row_0__block_ram_2__ram1024x18_bram_DOA_1__UNCONNECTED; + wire NLW_com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_queue_ram_ram_row_0__block_ram_2__ram1024x18_bram_DOA_0__UNCONNECTED; + wire NLW_com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_queue_ram_ram_row_0__block_ram_3__ram1024x18_bram_DOPA_1__UNCONNECTED; + wire NLW_com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_queue_ram_ram_row_0__block_ram_3__ram1024x18_bram_DOPA_0__UNCONNECTED; + wire NLW_com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_queue_ram_ram_row_0__block_ram_3__ram1024x18_bram_DOPB_1__UNCONNECTED; + wire NLW_com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_queue_ram_ram_row_0__block_ram_3__ram1024x18_bram_DOPB_0__UNCONNECTED; + wire NLW_com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_queue_ram_ram_row_0__block_ram_3__ram1024x18_bram_DOA_15__UNCONNECTED; + wire NLW_com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_queue_ram_ram_row_0__block_ram_3__ram1024x18_bram_DOA_14__UNCONNECTED; + wire NLW_com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_queue_ram_ram_row_0__block_ram_3__ram1024x18_bram_DOA_13__UNCONNECTED; + wire NLW_com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_queue_ram_ram_row_0__block_ram_3__ram1024x18_bram_DOA_12__UNCONNECTED; + wire NLW_com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_queue_ram_ram_row_0__block_ram_3__ram1024x18_bram_DOA_11__UNCONNECTED; + wire NLW_com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_queue_ram_ram_row_0__block_ram_3__ram1024x18_bram_DOA_10__UNCONNECTED; + wire NLW_com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_queue_ram_ram_row_0__block_ram_3__ram1024x18_bram_DOA_9__UNCONNECTED; + wire NLW_com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_queue_ram_ram_row_0__block_ram_3__ram1024x18_bram_DOA_8__UNCONNECTED; + wire NLW_com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_queue_ram_ram_row_0__block_ram_3__ram1024x18_bram_DOA_7__UNCONNECTED; + wire NLW_com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_queue_ram_ram_row_0__block_ram_3__ram1024x18_bram_DOA_6__UNCONNECTED; + wire NLW_com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_queue_ram_ram_row_0__block_ram_3__ram1024x18_bram_DOA_5__UNCONNECTED; + wire NLW_com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_queue_ram_ram_row_0__block_ram_3__ram1024x18_bram_DOA_4__UNCONNECTED; + wire NLW_com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_queue_ram_ram_row_0__block_ram_3__ram1024x18_bram_DOA_3__UNCONNECTED; + wire NLW_com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_queue_ram_ram_row_0__block_ram_3__ram1024x18_bram_DOA_2__UNCONNECTED; + wire NLW_com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_queue_ram_ram_row_0__block_ram_3__ram1024x18_bram_DOA_1__UNCONNECTED; + wire NLW_com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_queue_ram_ram_row_0__block_ram_3__ram1024x18_bram_DOA_0__UNCONNECTED; + wire NLW_com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_queue_ram_ram_row_0__block_ram_3__ram1024x18_bram_DOB_15__UNCONNECTED; + wire NLW_com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_queue_ram_ram_row_0__block_ram_3__ram1024x18_bram_DOB_14__UNCONNECTED; + wire NLW_com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_srlrow_4__srlcol_8__srlinst_Q15_UNCONNECTED; + wire NLW_com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_srlrow_4__srlcol_5__srlinst_Q15_UNCONNECTED; + wire NLW_com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_srlrow_4__srlcol_6__srlinst_Q15_UNCONNECTED; + wire NLW_com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_srlrow_4__srlcol_7__srlinst_Q15_UNCONNECTED; + wire NLW_com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_srlrow_4__srlcol_4__srlinst_Q15_UNCONNECTED; + wire NLW_com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_srlrow_4__srlcol_0__srlinst_Q15_UNCONNECTED; + wire NLW_com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_srlrow_4__srlcol_1__srlinst_Q15_UNCONNECTED; + wire NLW_com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_srlrow_4__srlcol_3__srlinst_Q15_UNCONNECTED; + wire NLW_com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_srlrow_4__srlcol_2__srlinst_Q15_UNCONNECTED; + wire NLW_com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_srlrow_1__srlcol_9__srlinst_Q15_UNCONNECTED; + wire NLW_com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_srlrow_1__srlcol_10__srlinst_Q15_UNCONNECTED; + wire NLW_com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_srlrow_1__srlcol_11__srlinst_Q15_UNCONNECTED; + wire NLW_com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_srlrow_1__srlcol_30__srlinst_Q15_UNCONNECTED; + wire NLW_com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_srlrow_1__srlcol_13__srlinst_Q15_UNCONNECTED; + wire NLW_com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_srlrow_1__srlcol_14__srlinst_Q15_UNCONNECTED; + wire NLW_com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_srlrow_1__srlcol_16__srlinst_Q15_UNCONNECTED; + wire NLW_com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_srlrow_1__srlcol_17__srlinst_Q15_UNCONNECTED; + wire NLW_com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_srlrow_1__srlcol_18__srlinst_Q15_UNCONNECTED; + wire NLW_com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_srlrow_1__srlcol_19__srlinst_Q15_UNCONNECTED; + wire NLW_com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_srlrow_1__srlcol_20__srlinst_Q15_UNCONNECTED; + wire NLW_com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_srlrow_1__srlcol_22__srlinst_Q15_UNCONNECTED; + wire NLW_com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_srlrow_1__srlcol_61__srlinst_Q15_UNCONNECTED; + wire NLW_com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_srlrow_1__srlcol_57__srlinst_Q15_UNCONNECTED; + wire NLW_com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_srlrow_1__srlcol_23__srlinst_Q15_UNCONNECTED; + wire NLW_com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_srlrow_1__srlcol_24__srlinst_Q15_UNCONNECTED; + wire NLW_com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_srlrow_1__srlcol_25__srlinst_Q15_UNCONNECTED; + wire NLW_com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_srlrow_1__srlcol_26__srlinst_Q15_UNCONNECTED; + wire NLW_com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_srlrow_1__srlcol_27__srlinst_Q15_UNCONNECTED; + wire NLW_com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_srlrow_1__srlcol_28__srlinst_Q15_UNCONNECTED; + wire NLW_com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_srlrow_1__srlcol_67__srlinst_Q15_UNCONNECTED; + wire NLW_com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_srlrow_1__srlcol_63__srlinst_Q15_UNCONNECTED; + wire NLW_com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_srlrow_1__srlcol_29__srlinst_Q15_UNCONNECTED; + wire NLW_com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_srlrow_1__srlcol_21__srlinst_Q15_UNCONNECTED; + wire NLW_com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_srlrow_1__srlcol_31__srlinst_Q15_UNCONNECTED; + wire NLW_com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_srlrow_1__srlcol_32__srlinst_Q15_UNCONNECTED; + wire NLW_com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_srlrow_1__srlcol_33__srlinst_Q15_UNCONNECTED; + wire NLW_com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_srlrow_1__srlcol_34__srlinst_Q15_UNCONNECTED; + wire NLW_com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_srlrow_1__srlcol_35__srlinst_Q15_UNCONNECTED; + wire NLW_com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_srlrow_1__srlcol_36__srlinst_Q15_UNCONNECTED; + wire NLW_com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_srlrow_1__srlcol_37__srlinst_Q15_UNCONNECTED; + wire NLW_com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_srlrow_1__srlcol_38__srlinst_Q15_UNCONNECTED; + wire NLW_com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_srlrow_1__srlcol_39__srlinst_Q15_UNCONNECTED; + wire NLW_com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_srlrow_1__srlcol_40__srlinst_Q15_UNCONNECTED; + wire NLW_com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_srlrow_1__srlcol_0__srlinst_Q15_UNCONNECTED; + wire NLW_com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_srlrow_1__srlcol_41__srlinst_Q15_UNCONNECTED; + wire NLW_com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_srlrow_1__srlcol_1__srlinst_Q15_UNCONNECTED; + wire NLW_com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_srlrow_1__srlcol_42__srlinst_Q15_UNCONNECTED; + wire NLW_com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_srlrow_1__srlcol_2__srlinst_Q15_UNCONNECTED; + wire NLW_com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_srlrow_1__srlcol_43__srlinst_Q15_UNCONNECTED; + wire NLW_com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_srlrow_1__srlcol_3__srlinst_Q15_UNCONNECTED; + wire NLW_com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_srlrow_1__srlcol_44__srlinst_Q15_UNCONNECTED; + wire NLW_com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_srlrow_1__srlcol_4__srlinst_Q15_UNCONNECTED; + wire NLW_com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_srlrow_1__srlcol_45__srlinst_Q15_UNCONNECTED; + wire NLW_com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_srlrow_1__srlcol_5__srlinst_Q15_UNCONNECTED; + wire NLW_com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_srlrow_1__srlcol_46__srlinst_Q15_UNCONNECTED; + wire NLW_com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_srlrow_1__srlcol_6__srlinst_Q15_UNCONNECTED; + wire NLW_com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_srlrow_1__srlcol_7__srlinst_Q15_UNCONNECTED; + wire NLW_com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_srlrow_1__srlcol_12__srlinst_Q15_UNCONNECTED; + wire NLW_com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_srlrow_1__srlcol_49__srlinst_Q15_UNCONNECTED; + wire NLW_com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_srlrow_1__srlcol_15__srlinst_Q15_UNCONNECTED; + wire NLW_com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_srlrow_1__srlcol_50__srlinst_Q15_UNCONNECTED; + wire NLW_com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_srlrow_1__srlcol_64__srlinst_Q15_UNCONNECTED; + wire NLW_com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_srlrow_1__srlcol_51__srlinst_Q15_UNCONNECTED; + wire NLW_com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_srlrow_1__srlcol_65__srlinst_Q15_UNCONNECTED; + wire NLW_com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_srlrow_1__srlcol_52__srlinst_Q15_UNCONNECTED; + wire NLW_com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_srlrow_1__srlcol_48__srlinst_Q15_UNCONNECTED; + wire NLW_com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_srlrow_1__srlcol_8__srlinst_Q15_UNCONNECTED; + wire NLW_com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_srlrow_1__srlcol_53__srlinst_Q15_UNCONNECTED; + wire NLW_com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_srlrow_1__srlcol_58__srlinst_Q15_UNCONNECTED; + wire NLW_com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_srlrow_1__srlcol_54__srlinst_Q15_UNCONNECTED; + wire NLW_com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_srlrow_1__srlcol_60__srlinst_Q15_UNCONNECTED; + wire NLW_com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_srlrow_1__srlcol_59__srlinst_Q15_UNCONNECTED; + wire NLW_com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_srlrow_1__srlcol_55__srlinst_Q15_UNCONNECTED; + wire NLW_com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_srlrow_1__srlcol_47__srlinst_Q15_UNCONNECTED; + wire NLW_com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_srlrow_1__srlcol_56__srlinst_Q15_UNCONNECTED; + wire NLW_com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_srlrow_1__srlcol_62__srlinst_Q15_UNCONNECTED; + wire NLW_com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_queue_aux_queue_srlrow_0__srlcol_0__srlinst_Q15_UNCONNECTED; + wire NLW_com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_queue_aux_queue_srlrow_0__srlcol_3__srlinst_Q15_UNCONNECTED; + wire NLW_com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_queue_aux_queue_srlrow_0__srlcol_2__srlinst_Q15_UNCONNECTED; + wire NLW_com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_queue_aux_queue_srlrow_0__srlcol_1__srlinst_Q15_UNCONNECTED; + wire NLW_com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_queue_aux_queue_srlrow_0__srlcol_4__srlinst_Q15_UNCONNECTED; + wire NLW_com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_queue_aux_queue_srlrow_0__srlcol_7__srlinst_Q15_UNCONNECTED; + wire NLW_com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_queue_aux_queue_srlrow_0__srlcol_6__srlinst_Q15_UNCONNECTED; + wire NLW_com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_queue_aux_queue_srlrow_0__srlcol_5__srlinst_Q15_UNCONNECTED; + wire NLW_com_cmm_u_cmm_errman_cmt_hdr_buf_lutram_data_I_1_SPO_UNCONNECTED; + wire NLW_com_cmm_u_cmm_errman_cmt_hdr_buf_lutram_data_I_2_SPO_UNCONNECTED; + wire NLW_com_cmm_u_cmm_errman_cmt_hdr_buf_lutram_data_I_3_SPO_UNCONNECTED; + wire NLW_com_cmm_u_cmm_errman_cmt_hdr_buf_lutram_data_I_4_SPO_UNCONNECTED; + wire NLW_com_cmm_u_cmm_errman_cmt_hdr_buf_lutram_data_I_5_SPO_UNCONNECTED; + wire NLW_com_cmm_u_cmm_errman_cmt_hdr_buf_lutram_data_I_6_SPO_UNCONNECTED; + wire NLW_com_cmm_u_cmm_errman_cmt_hdr_buf_lutram_data_I_7_SPO_UNCONNECTED; + wire NLW_com_cmm_u_cmm_errman_cmt_hdr_buf_lutram_data_I_8_SPO_UNCONNECTED; + wire NLW_com_cmm_u_cmm_errman_cmt_hdr_buf_lutram_data_I_9_SPO_UNCONNECTED; + wire NLW_com_cmm_u_cmm_errman_cmt_hdr_buf_lutram_data_I_10_SPO_UNCONNECTED; + wire NLW_com_cmm_u_cmm_errman_cmt_hdr_buf_lutram_data_I_11_SPO_UNCONNECTED; + wire NLW_com_cmm_u_cmm_errman_cmt_hdr_buf_lutram_data_I_12_SPO_UNCONNECTED; + wire NLW_com_cmm_u_cmm_errman_cmt_hdr_buf_lutram_data_I_13_SPO_UNCONNECTED; + wire NLW_com_cmm_u_cmm_errman_cmt_hdr_buf_lutram_data_I_14_SPO_UNCONNECTED; + wire NLW_com_cmm_u_cmm_errman_cmt_hdr_buf_lutram_data_I_15_SPO_UNCONNECTED; + wire NLW_com_cmm_u_cmm_errman_cmt_hdr_buf_lutram_data_I_16_SPO_UNCONNECTED; + wire NLW_com_cmm_u_cmm_errman_cmt_hdr_buf_lutram_data_I_17_SPO_UNCONNECTED; + wire NLW_com_cmm_u_cmm_errman_cmt_hdr_buf_lutram_data_I_18_SPO_UNCONNECTED; + wire NLW_com_cmm_u_cmm_errman_cmt_hdr_buf_lutram_data_I_19_SPO_UNCONNECTED; + wire NLW_com_cmm_u_cmm_errman_cmt_hdr_buf_lutram_data_I_20_SPO_UNCONNECTED; + wire NLW_com_cmm_u_cmm_errman_cmt_hdr_buf_lutram_data_I_21_SPO_UNCONNECTED; + wire NLW_com_cmm_u_cmm_errman_cmt_hdr_buf_lutram_data_I_22_SPO_UNCONNECTED; + wire NLW_com_cmm_u_cmm_errman_cmt_hdr_buf_lutram_data_I_23_SPO_UNCONNECTED; + wire NLW_com_cmm_u_cmm_errman_cmt_hdr_buf_lutram_data_I_24_SPO_UNCONNECTED; + wire NLW_com_cmm_u_cmm_errman_cmt_hdr_buf_lutram_data_I_25_SPO_UNCONNECTED; + wire NLW_com_cmm_u_cmm_errman_cmt_hdr_buf_lutram_data_I_26_SPO_UNCONNECTED; + wire NLW_com_cmm_u_cmm_errman_cmt_hdr_buf_lutram_data_I_27_SPO_UNCONNECTED; + wire NLW_com_cmm_u_cmm_errman_cmt_hdr_buf_lutram_data_I_28_SPO_UNCONNECTED; + wire NLW_com_cmm_u_cmm_errman_cmt_hdr_buf_lutram_data_I_29_SPO_UNCONNECTED; + wire NLW_com_cmm_u_cmm_errman_cmt_hdr_buf_lutram_data_I_30_SPO_UNCONNECTED; + wire NLW_com_cmm_u_cmm_errman_cmt_hdr_buf_lutram_data_I_31_SPO_UNCONNECTED; + wire NLW_com_cmm_u_cmm_errman_cmt_hdr_buf_lutram_data_I_32_SPO_UNCONNECTED; + wire NLW_com_cmm_u_cmm_errman_cmt_hdr_buf_lutram_data_I_33_SPO_UNCONNECTED; + wire NLW_com_cmm_u_cmm_errman_cmt_hdr_buf_lutram_data_I_34_SPO_UNCONNECTED; + wire NLW_com_cmm_u_cmm_errman_cmt_hdr_buf_lutram_data_I_35_SPO_UNCONNECTED; + wire NLW_com_cmm_u_cmm_errman_cmt_hdr_buf_lutram_data_I_36_SPO_UNCONNECTED; + wire NLW_com_cmm_u_cmm_errman_cmt_hdr_buf_lutram_data_I_37_SPO_UNCONNECTED; + wire NLW_com_cmm_u_cmm_errman_cmt_hdr_buf_lutram_data_I_38_SPO_UNCONNECTED; + wire NLW_com_cmm_u_cmm_errman_cmt_hdr_buf_lutram_data_I_39_SPO_UNCONNECTED; + wire NLW_com_cmm_u_cmm_errman_cmt_hdr_buf_lutram_data_I_40_SPO_UNCONNECTED; + wire NLW_com_cmm_u_cmm_errman_cmt_hdr_buf_lutram_data_I_41_SPO_UNCONNECTED; + wire NLW_com_cmm_u_cmm_errman_cmt_hdr_buf_lutram_data_I_42_SPO_UNCONNECTED; + wire NLW_com_cmm_u_cmm_errman_cmt_hdr_buf_lutram_data_I_43_SPO_UNCONNECTED; + wire NLW_com_cmm_u_cmm_errman_cmt_hdr_buf_lutram_data_I_44_SPO_UNCONNECTED; + wire NLW_com_cmm_u_cmm_errman_cmt_hdr_buf_lutram_data_I_45_SPO_UNCONNECTED; + wire NLW_com_cmm_u_cmm_errman_cmt_hdr_buf_lutram_data_I_46_SPO_UNCONNECTED; + wire NLW_com_cmm_u_cmm_errman_cmt_hdr_buf_lutram_data_I_47_SPO_UNCONNECTED; + wire NLW_com_cmm_u_cmm_errman_cmt_hdr_buf_lutram_data_I_48_SPO_UNCONNECTED; + wire NLW_com_cmm_u_cmm_errman_cmt_hdr_buf_lutram_data_I_49_SPO_UNCONNECTED; + wire NLW_com_cmm_u_cmm_errman_cmt_hdr_buf_lutram_data_I_50_SPO_UNCONNECTED; + wire NLW_com_cmm_u_cmm_errman_cfg_hdr_buf_lutram_data_I_1_SPO_UNCONNECTED; + wire NLW_com_cmm_u_cmm_errman_cfg_hdr_buf_lutram_data_I_2_SPO_UNCONNECTED; + wire NLW_com_cmm_u_cmm_errman_cfg_hdr_buf_lutram_data_I_3_SPO_UNCONNECTED; + wire NLW_com_cmm_u_cmm_errman_cfg_hdr_buf_lutram_data_I_4_SPO_UNCONNECTED; + wire NLW_com_cmm_u_cmm_errman_cfg_hdr_buf_lutram_data_I_5_SPO_UNCONNECTED; + wire NLW_com_cmm_u_cmm_errman_cfg_hdr_buf_lutram_data_I_6_SPO_UNCONNECTED; + wire NLW_com_cmm_u_cmm_errman_cfg_hdr_buf_lutram_data_I_7_SPO_UNCONNECTED; + wire NLW_com_cmm_u_cmm_errman_cfg_hdr_buf_lutram_data_I_8_SPO_UNCONNECTED; + wire NLW_com_cmm_u_cmm_errman_cfg_hdr_buf_lutram_data_I_9_SPO_UNCONNECTED; + wire NLW_com_cmm_u_cmm_errman_cfg_hdr_buf_lutram_data_I_10_SPO_UNCONNECTED; + wire NLW_com_cmm_u_cmm_errman_cfg_hdr_buf_lutram_data_I_11_SPO_UNCONNECTED; + wire NLW_com_cmm_u_cmm_errman_cfg_hdr_buf_lutram_data_I_12_SPO_UNCONNECTED; + wire NLW_com_cmm_u_cmm_errman_cfg_hdr_buf_lutram_data_I_13_SPO_UNCONNECTED; + wire NLW_com_cmm_u_cmm_errman_cfg_hdr_buf_lutram_data_I_14_SPO_UNCONNECTED; + wire NLW_com_cmm_u_cmm_errman_cfg_hdr_buf_lutram_data_I_15_SPO_UNCONNECTED; + wire NLW_com_cmm_u_cmm_errman_cfg_hdr_buf_lutram_data_I_16_SPO_UNCONNECTED; + wire NLW_com_cmm_u_cmm_errman_cfg_hdr_buf_lutram_data_I_17_SPO_UNCONNECTED; + wire NLW_com_cmm_u_cmm_errman_cfg_hdr_buf_lutram_data_I_18_SPO_UNCONNECTED; + wire NLW_com_cmm_u_cmm_errman_cfg_hdr_buf_lutram_data_I_19_SPO_UNCONNECTED; + wire NLW_com_cmm_u_cmm_errman_cfg_hdr_buf_lutram_data_I_20_SPO_UNCONNECTED; + wire NLW_com_cmm_u_cmm_errman_cfg_hdr_buf_lutram_data_I_21_SPO_UNCONNECTED; + wire NLW_com_cmm_u_cmm_errman_cfg_hdr_buf_lutram_data_I_22_SPO_UNCONNECTED; + wire NLW_com_cmm_u_cmm_errman_cfg_hdr_buf_lutram_data_I_23_SPO_UNCONNECTED; + wire NLW_com_cmm_u_cmm_errman_cfg_hdr_buf_lutram_data_I_24_SPO_UNCONNECTED; + wire NLW_com_cmm_u_cmm_errman_cfg_hdr_buf_lutram_data_I_25_SPO_UNCONNECTED; + wire NLW_com_cmm_u_cmm_errman_cfg_hdr_buf_lutram_data_I_26_SPO_UNCONNECTED; + wire NLW_com_cmm_u_cmm_errman_cfg_hdr_buf_lutram_data_I_27_SPO_UNCONNECTED; + wire NLW_com_cmm_u_cmm_errman_cfg_hdr_buf_lutram_data_I_28_SPO_UNCONNECTED; + wire NLW_com_cmm_u_cmm_errman_cfg_hdr_buf_lutram_data_I_29_SPO_UNCONNECTED; + wire NLW_com_cmm_u_cmm_errman_cfg_hdr_buf_lutram_data_I_30_SPO_UNCONNECTED; + wire NLW_com_cmm_u_cmm_errman_cfg_hdr_buf_lutram_data_I_31_SPO_UNCONNECTED; + wire NLW_com_cmm_u_cmm_errman_cfg_hdr_buf_lutram_data_I_32_SPO_UNCONNECTED; + wire NLW_com_cmm_u_cmm_errman_cfg_hdr_buf_lutram_data_I_33_SPO_UNCONNECTED; + wire NLW_com_cmm_u_cmm_errman_cfg_hdr_buf_lutram_data_I_34_SPO_UNCONNECTED; + wire NLW_com_cmm_u_cmm_errman_cfg_hdr_buf_lutram_data_I_35_SPO_UNCONNECTED; + wire NLW_com_cmm_u_cmm_errman_cfg_hdr_buf_lutram_data_I_36_SPO_UNCONNECTED; + wire NLW_com_cmm_u_cmm_errman_cfg_hdr_buf_lutram_data_I_37_SPO_UNCONNECTED; + wire NLW_com_cmm_u_cmm_errman_cfg_hdr_buf_lutram_data_I_38_SPO_UNCONNECTED; + wire NLW_com_cmm_u_cmm_errman_cfg_hdr_buf_lutram_data_I_39_SPO_UNCONNECTED; + wire NLW_com_cmm_u_cmm_errman_cfg_hdr_buf_lutram_data_I_40_SPO_UNCONNECTED; + wire NLW_com_cmm_u_cmm_errman_cfg_hdr_buf_lutram_data_I_41_SPO_UNCONNECTED; + wire NLW_com_cmm_u_cmm_errman_cfg_hdr_buf_lutram_data_I_42_SPO_UNCONNECTED; + wire NLW_com_cmm_u_cmm_errman_cfg_hdr_buf_lutram_data_I_43_SPO_UNCONNECTED; + wire NLW_com_cmm_u_cmm_errman_cfg_hdr_buf_lutram_data_I_44_SPO_UNCONNECTED; + wire NLW_com_cmm_u_cmm_errman_cfg_hdr_buf_lutram_data_I_45_SPO_UNCONNECTED; + wire NLW_com_cmm_u_cmm_errman_cfg_hdr_buf_lutram_data_I_46_SPO_UNCONNECTED; + wire NLW_com_cmm_u_cmm_errman_cfg_hdr_buf_lutram_data_I_47_SPO_UNCONNECTED; + wire NLW_com_cmm_u_cmm_errman_cfg_hdr_buf_lutram_data_I_48_SPO_UNCONNECTED; + wire NLW_com_cmm_u_cmm_errman_cfg_hdr_buf_lutram_data_I_49_SPO_UNCONNECTED; + wire NLW_com_cmm_u_cmm_errman_cfg_hdr_buf_lutram_data_I_50_SPO_UNCONNECTED; + wire [3 : 0] pci_exp_txp_6083; + wire [3 : 0] pci_exp_txn_6084; + wire [3 : 0] pci_exp_rxp_6085; + wire [3 : 0] pci_exp_rxn_6086; + wire [63 : 0] trn_td_6087; + wire [7 : 0] trn_trem_n_6088; + wire [4 : 0] NlwRenamedSig_OI_trn_tbuf_av; + wire [63 : 0] NlwRenamedSig_OI_trn_rd; + wire [3 : 3] NlwRenamedSignal_trn_rrem_n; + wire [15 : 15] NlwRenamedSignal_cfg_lcommand; + wire [6 : 0] trn_rbar_hit_n_6089; + wire [7 : 0] trn_rfc_nph_av_6090; + wire [11 : 0] trn_rfc_npd_av_6091; + wire [7 : 0] trn_rfc_ph_av_6092; + wire [11 : 0] trn_rfc_pd_av_6093; + wire [6 : 0] trn_rfc_cplh_av_6094; + wire [7 : 7] NlwRenamedSig_OI_trn_rfc_cplh_av; + wire [10 : 0] trn_rfc_cpld_av_6095; + wire [11 : 11] NlwRenamedSig_OI_trn_rfc_cpld_av; + wire [31 : 0] cfg_do_6096; + wire [31 : 0] cfg_di_6097; + wire [3 : 0] cfg_byte_en_n_6098; + wire [9 : 0] cfg_dwaddr_6099; + wire [47 : 0] cfg_err_tlp_cpl_header_6100; + wire [1 : 0] cfg_pcie_link_state_n_6101; + wire [7 : 0] NlwRenamedSig_OI_cfg_bus_number; + wire [4 : 0] NlwRenamedSig_OI_cfg_device_number; + wire [14 : 0] NlwRenamedSig_OI_cfg_dcommand; + wire [1023 : 0] cfg_cfg_6102; + wire [0 : 0] plm_sym_reg_count; + wire [0 : 0] com_llm_llm_rx_top_llm_rx_dllp_crc_rx_dllp_d; + wire [0 : 0] cmmp_negotiated_width_1; + wire [0 : 0] cmmp_negotiated_width_0; + wire [63 : 0] data_in_q; + wire [0 : 0] com_llm_llm_tx_top_llmx08_tx_tlp_komp_rem_pipe_DOUT; + wire [3 : 3] com_llm_llm_tx_top_llmx08_tx_tlp_komp_rem_pipe; + wire [0 : 0] com_llm_llm_tx_top_llmx08_tx_tlp_komp_eof_n_pipe_DOUT; + wire [4 : 4] com_llm_llm_tx_top_llmx08_tx_tlp_komp_eof_n_pipe; + wire [31 : 0] com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crc32_d64_feedback; + wire [0 : 0] plm_tsi0_reg_dec7_0_DOUT; + wire [0 : 0] plm_tsi0_reg_dec7_DOUT; + wire [0 : 0] plm_tsi0_reg_dec5_DOUT; + wire [12 : 12] plm_tsi0_reg_dec5; + wire [0 : 0] plm_tsi1_reg_dec6_DOUT; + wire [5 : 5] plm_tsi1_reg_dec6; + wire [0 : 0] plm_tsi1_reg_dec1_2_DOUT; + wire [4 : 1] plm_tsi1_reg_dec1; + wire [0 : 0] plm_tsi1_reg_dec1_1_DOUT; + wire [0 : 0] plm_tsi1_reg_dec1_0_DOUT; + wire [0 : 0] plm_tsi1_reg_dec1_DOUT; + wire [0 : 0] plm_tsi1_reg_dec8_DOUT; + wire [0 : 0] plm_tsi1_reg_dec7_0_DOUT; + wire [0 : 0] plm_tsi1_reg_dec7_DOUT; + wire [0 : 0] plm_tsi1_reg_dec5_DOUT; + wire [12 : 12] plm_tsi1_reg_dec5; + wire [0 : 0] plm_tsi0_reg_dec6_DOUT; + wire [5 : 5] plm_tsi0_reg_dec6; + wire [0 : 0] plm_tsi0_reg_dec1_2_DOUT; + wire [4 : 1] plm_tsi0_reg_dec1; + wire [0 : 0] plm_tsi0_reg_dec1_1_DOUT; + wire [0 : 0] plm_tsi0_reg_dec1_0_DOUT; + wire [0 : 0] plm_tsi0_reg_dec1_DOUT; + wire [0 : 0] plm_tsi0_reg_dec8_DOUT; + wire [0 : 0] plm_tsi3_reg_dec1_0_DOUT; + wire [4 : 1] plm_tsi3_reg_dec1; + wire [0 : 0] plm_tsi3_reg_dec1_DOUT; + wire [0 : 0] plm_tsi3_reg_dec8_DOUT; + wire [0 : 0] plm_tsi3_reg_dec7_0_DOUT; + wire [0 : 0] plm_tsi3_reg_dec5_DOUT; + wire [12 : 12] plm_tsi3_reg_dec5; + wire [0 : 0] plm_tsi3_reg_dec7_DOUT; + wire [0 : 0] plm_tsi2_reg_dec6_DOUT; + wire [5 : 5] plm_tsi2_reg_dec6; + wire [0 : 0] plm_tsi2_reg_dec1_2_DOUT; + wire [4 : 1] plm_tsi2_reg_dec1; + wire [0 : 0] plm_tsi2_reg_dec1_1_DOUT; + wire [0 : 0] plm_tsi2_reg_dec1_0_DOUT; + wire [0 : 0] plm_tsi2_reg_dec1_DOUT; + wire [0 : 0] plm_tsi2_reg_dec8_DOUT; + wire [0 : 0] plm_tsi2_reg_dec7_0_DOUT; + wire [0 : 0] plm_tsi2_reg_dec7_DOUT; + wire [0 : 0] plm_tsi2_reg_dec5_DOUT; + wire [12 : 12] plm_tsi2_reg_dec5; + wire [0 : 0] plm_tsi0_reg_dec8_0_DOUT; + wire [0 : 0] plm_tsi1_reg_dec8_0_DOUT; + wire [0 : 0] plm_tsi2_reg_dec8_0_DOUT; + wire [0 : 0] plm_tsi3_reg_dec8_0_DOUT; + wire [0 : 0] plm_tsi3_reg_dec6_DOUT; + wire [5 : 5] plm_tsi3_reg_dec6; + wire [0 : 0] plm_tsi3_reg_dec1_2_DOUT; + wire [0 : 0] plm_tsi3_reg_dec1_1_DOUT; + wire [7 : 0] com_lnk_rd; + wire [1 : 0] plm_dfm_deframe1_dword_sdpstp; + wire [5 : 4] plm_dfm_deframe1_qwfsm_nxt_state; + wire [1 : 1] reg_by1_preh_sdpstp_6_iv_i_0_a4; + wire [4 : 0] plm_sym_sym_gen_next_addr; + wire [17 : 17] plm_sym_sym_gen_reg_rom_out_27; + wire [4 : 4] plm_fsm_rl_counter3_loadable_tx_counter_reg_tx_count_6; + wire [3 : 0] com_cmm_u_cmm_dataproducer_req_gnt_code; + wire [11 : 11] com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d16_new_c16_1_1_1; + wire [31 : 0] com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q; + wire [2 : 2] com_llm_llm_rx_top_llm_rx_tlp_crc_rx_data_q; + wire [7 : 0] plm_rx1_lane_num; + wire [7 : 0] plm_rx2_lane_num; + wire [7 : 0] plm_rx3_lane_num; + wire [1 : 0] plm_dfm_deframe1_dword_edbedg; + wire [2 : 2] com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_num; + wire [0 : 0] com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_num_2_q; + wire [63 : 0] phy_td; + wire [63 : 0] phy_rd; + wire [0 : 0] cmmp_negotiated_width; + wire [3 : 0] plm_reg_outstanding_ccs; + wire [1 : 0] plm_frm1_is_k; + wire [1 : 0] plm_frm3_is_k; + wire [1 : 0] plm_frm0_is_k; + wire [15 : 0] plm_frm3_char; + wire [15 : 0] plm_frm2_char; + wire [15 : 0] plm_frm1_char; + wire [15 : 0] plm_frm0_char; + wire [0 : 0] plm_link_ctrl; + wire [7 : 0] plm_tx1_link_num; + wire [2 : 0] plm_send_command; + wire [1 : 1] plm_sent_status; + wire [7 : 0] plm_rx3_link_num; + wire [7 : 0] plm_rx2_link_num; + wire [7 : 0] plm_rx1_link_num; + wire [7 : 0] plm_rx0_link_num; + wire [7 : 0] plm_rx0_lane_num; + wire [15 : 0] plm_tx3_raw_char; + wire [1 : 0] plm_tx3_raw_char_is_k; + wire [1 : 0] plm_tx3_raw_char_pass; + wire [15 : 0] plm_tx2_raw_char; + wire [15 : 0] plm_tx1_raw_char; + wire [1 : 0] plm_reg_kkk; + wire [1 : 0] plm_reg_raw_char_is_k; + wire [1 : 0] plm_tx1_raw_char_is_k; + wire [1 : 0] plm_reg_dis_6103; + wire [1 : 0] plm_reg_raw_char_pass; + wire [15 : 0] plm_tx0_raw_char; + wire [1 : 0] plm_tx0_raw_char_is_k; + wire [1 : 0] plm_tx0_raw_char_pass; + wire [15 : 0] plm_rx3_raw_dat; + wire [1 : 1] plm_rx3_des_t1n; + wire [1 : 1] plm_rx3_des_t1p; + wire [1 : 0] plm_rx3_des_sym; + wire [1 : 0] plm_rx3_des_edb; + wire [1 : 0] plm_rx3_des_edg; + wire [1 : 1] plm_rx3_des_t2n; + wire [1 : 1] plm_rx3_des_t2p; + wire [1 : 0] plm_reg_com_1; + wire [15 : 0] plm_rx3_des_dat; + wire [1 : 0] plm_rx3_des_bad; + wire [0 : 0] plm_reg_t1n_4_2; + wire [1 : 1] plm_reg_pad_3_1; + wire [0 : 0] plm_reg_t1p_4_2; + wire [0 : 0] plm_reg_t2n_4_2; + wire [0 : 0] plm_reg_t2p_4_2; + wire [0 : 0] plm_reg_pad_4_1; + wire [15 : 0] plm_rx2_raw_dat; + wire [1 : 1] plm_rx2_des_t2n; + wire [1 : 1] plm_rx2_des_t2p; + wire [1 : 0] plm_reg_com_0; + wire [1 : 0] plm_rx2_des_sym; + wire [15 : 0] plm_rx2_des_dat; + wire [1 : 0] plm_rx2_des_bad; + wire [1 : 1] plm_rx2_des_t1n; + wire [1 : 1] plm_rx2_des_t1p; + wire [0 : 0] plm_reg_t1n_4_1; + wire [0 : 0] plm_reg_t1p_4_1; + wire [0 : 0] plm_reg_pad_4_0; + wire [1 : 1] plm_reg_pad_3_0; + wire [0 : 0] plm_reg_t2n_4_1; + wire [0 : 0] plm_reg_t2p_4_1; + wire [15 : 0] plm_rx1_raw_dat; + wire [1 : 0] plm_rx1_des_sym; + wire [1 : 1] plm_rx1_des_t1n; + wire [1 : 1] plm_rx1_des_t1p; + wire [1 : 1] plm_rx1_des_t2n; + wire [1 : 1] plm_rx1_des_t2p; + wire [1 : 0] plm_reg_com; + wire [15 : 0] plm_rx1_des_dat; + wire [1 : 0] plm_rx1_des_bad; + wire [0 : 0] plm_reg_t1n_4_0; + wire [0 : 0] plm_reg_t1p_4_0; + wire [0 : 0] plm_reg_t2p_4_0; + wire [0 : 0] plm_reg_pad_4; + wire [1 : 1] plm_reg_pad_3; + wire [0 : 0] plm_reg_t2n_4_0; + wire [15 : 0] plm_rx0_raw_dat; + wire [1 : 0] plm_rx0_des_sym; + wire [1 : 0] plm_rx0_des_com; + wire [1 : 0] plm_rx0_des_edb; + wire [1 : 1] plm_rx0_des_t1n; + wire [1 : 1] plm_rx0_des_t1p; + wire [1 : 1] plm_rx0_des_t2n; + wire [1 : 1] plm_rx0_des_t2p; + wire [15 : 0] plm_rx0_des_dat; + wire [1 : 0] plm_rx0_des_bad; + wire [1 : 0] plm_rx0_des_idl; + wire [1 : 0] plm_rx0_des_pad; + wire [1 : 0] plm_rx0_des_sdp; + wire [1 : 0] plm_rx0_des_skp; + wire [1 : 0] plm_rx0_des_stp; + wire [1 : 0] plm_rx0_des_edg; + wire [1 : 0] plm_rx0_des_fts; + wire [0 : 0] plm_reg_t2p_4; + wire [0 : 0] plm_reg_t1n_4; + wire [0 : 0] plm_reg_t1p_4; + wire [0 : 0] plm_reg_t2n_4; + wire [15 : 0] plm_tx3_data; + wire [1 : 0] plm_tx3_char_is_k; + wire [15 : 0] plm_rx3_data; + wire [1 : 0] plm_rx3_not_in_table; + wire [1 : 0] plm_rx3_char_is_k; + wire [15 : 0] plm_tx2_data; + wire [15 : 0] plm_rx2_data; + wire [1 : 0] plm_rx2_not_in_table; + wire [1 : 0] plm_rx2_char_is_k; + wire [15 : 0] plm_tx1_data; + wire [1 : 0] plm_tx2_char_is_k; + wire [15 : 0] plm_rx1_data; + wire [1 : 0] plm_rx1_not_in_table; + wire [1 : 0] plm_rx1_char_is_k; + wire [15 : 0] plm_tx0_data; + wire [1 : 0] plm_tx0_char_is_k; + wire [15 : 0] plm_rx0_data; + wire [1 : 0] plm_rx0_not_in_table; + wire [1 : 0] plm_rx0_char_is_k; + wire [1 : 1] plm_v4f_mgt_for_v1_4_cal_inst3_reset_r; + wire [0 : 0] plm_v4f_mgt_for_v1_4_cal_inst0_reset_r; + wire [15 : 0] plm_v4f_mgt_gt3_di; + wire [5 : 1] plm_v4f_mgt_gt3_daddr; + wire [15 : 0] plm_v4f_mgt_gt3_do; + wire [1 : 1] plm_v4f_mgt_loopback3; + wire [15 : 0] plm_v4f_mgt_gt2_di; + wire [5 : 1] plm_v4f_mgt_gt2_daddr; + wire [15 : 0] plm_v4f_mgt_gt2_do; + wire [15 : 0] plm_v4f_mgt_gt1_di; + wire [5 : 1] plm_v4f_mgt_gt1_daddr; + wire [15 : 0] plm_v4f_mgt_gt1_do; + wire [15 : 0] plm_v4f_mgt_gt0_di; + wire [5 : 1] plm_v4f_mgt_gt0_daddr; + wire [15 : 0] plm_v4f_mgt_gt0_do; + wire [13 : 1] plm_v4f_mgt_reg_rst_cnt_cry; + wire [3 : 0] plm_v4f_mgt_wrx0_char_is_k; + wire [3 : 0] plm_v4f_mgt_wrx1_char_is_k; + wire [3 : 0] plm_v4f_mgt_wrx2_char_is_k; + wire [3 : 0] plm_v4f_mgt_wrx3_char_is_k; + wire [3 : 0] plm_v4f_mgt_wrx0_disp_err; + wire [3 : 0] plm_v4f_mgt_wrx1_disp_err; + wire [3 : 0] plm_v4f_mgt_wrx2_disp_err; + wire [3 : 0] plm_v4f_mgt_wrx3_disp_err; + wire [3 : 0] plm_v4f_mgt_wrx0_run_disp; + wire [3 : 0] plm_v4f_mgt_wrx1_run_disp; + wire [3 : 0] plm_v4f_mgt_wrx2_run_disp; + wire [3 : 0] plm_v4f_mgt_wrx3_run_disp; + wire [31 : 0] plm_v4f_mgt_wrx0_data; + wire [31 : 0] plm_v4f_mgt_wrx1_data; + wire [31 : 0] plm_v4f_mgt_wrx2_data; + wire [31 : 0] plm_v4f_mgt_wrx3_data; + wire [5 : 5] plm_v4f_mgt_rx3_rxstatus; + wire [5 : 5] plm_v4f_mgt_rx2_rxstatus; + wire [5 : 5] plm_v4f_mgt_rx1_rxstatus; + wire [5 : 5] plm_v4f_mgt_rx0_rxstatus; + wire [3 : 0] plm_v4f_mgt_wrx3_ntable; + wire [3 : 0] plm_v4f_mgt_wrx2_ntable; + wire [3 : 0] plm_v4f_mgt_wrx1_ntable; + wire [3 : 0] plm_v4f_mgt_wrx0_ntable; + wire [0 : 0] plm_v4f_mgt_un1_reg_plm_rst_n_2_0_0_o4; + wire [0 : 0] plm_v4f_mgt_un1_reg_plm_rst_n_2_0_0_a2_2_1; + wire [0 : 0] plm_v4f_mgt_un1_reg_plm_rst_n_2_0_0_0; + wire [0 : 0] plm_v4f_mgt_un1_reg_plm_rst_n_2_0_0_a2; + wire [1 : 1] plm_v4f_mgt_reg_bond_state_8_0_a3; + wire [0 : 0] plm_v4f_mgt_reg_bond_state_8_i_m3; + wire [23 : 23] plm_v4f_mgt_reg_tee3_dlyline; + wire [23 : 23] plm_v4f_mgt_reg_tee2_dlyline; + wire [23 : 23] plm_v4f_mgt_reg_tee1_dlyline; + wire [23 : 23] plm_v4f_mgt_reg_tee0_dlyline; + wire [0 : 0] plm_v4f_mgt_reg_tee0_dlyline_DOUT; + wire [0 : 0] plm_v4f_mgt_reg_tee1_dlyline_DOUT; + wire [0 : 0] plm_v4f_mgt_reg_tee2_dlyline_DOUT; + wire [0 : 0] plm_v4f_mgt_reg_tee3_dlyline_DOUT; + wire [0 : 0] plm_v4f_mgt_reg_phase3_0_DOUT; + wire [14 : 0] plm_v4f_mgt_reg_rst_cnt_s; + wire [3 : 0] plm_v4f_mgt_reg_pma_cnt; + wire [0 : 0] plm_v4f_mgt_reg_pma_cnt_i; + wire [3 : 0] plm_v4f_mgt_reg_dcm_cnt; + wire [0 : 0] plm_v4f_mgt_reg_dcm_cnt_i; + wire [1 : 0] plm_v4f_mgt_bondage_reg_bond_state_9; + wire [0 : 0] plm_v4f_mgt_reg_bond_state; + wire [15 : 0] plm_v4f_mgt_dtx0_data; + wire [1 : 0] plm_v4f_mgt_dtx1_char_disp_val; + wire [1 : 0] plm_v4f_mgt_dtx1_char_disp_mode; + wire [15 : 0] plm_v4f_mgt_dtx1_data; + wire [1 : 0] plm_v4f_mgt_dtx1_char_is_k; + wire [15 : 0] plm_v4f_mgt_dtx2_data; + wire [1 : 0] plm_v4f_mgt_dtx2_char_is_k; + wire [1 : 0] plm_v4f_mgt_dtx2_char_disp_val; + wire [1 : 0] plm_v4f_mgt_dtx2_char_disp_mode; + wire [1 : 0] plm_v4f_mgt_dtx3_char_disp_val; + wire [1 : 0] plm_v4f_mgt_dtx3_char_disp_mode; + wire [15 : 0] plm_v4f_mgt_dtx3_data; + wire [1 : 0] plm_v4f_mgt_dtx3_char_is_k; + wire [1 : 0] plm_v4f_mgt_dtx0_char_is_k; + wire [1 : 0] plm_v4f_mgt_dtx0_char_disp_val; + wire [1 : 0] plm_v4f_mgt_dtx0_char_disp_mode; + wire [0 : 0] plm_v4f_mgt_un1_reg_plm_rst_n_2_i_i; + wire [0 : 0] plm_v4f_mgt_un1_reg_plm_rst_n_2_i; + wire [0 : 0] plm_v4f_mgt_reg_tee0_dlyline_tmp_array_1; + wire [0 : 0] plm_v4f_mgt_reg_tee1_dlyline_tmp_array_1; + wire [0 : 0] plm_v4f_mgt_reg_tee2_dlyline_tmp_array_1; + wire [0 : 0] plm_v4f_mgt_reg_tee3_dlyline_tmp_d_array_1; + wire [0 : 0] plm_v4f_mgt_reg_tee3_dlyline_tmp_array_1; + wire [0 : 0] plm_v4f_mgt_reg_phase3_0_tmp_d_array_0; + wire [14 : 0] plm_v4f_mgt_reg_rst_cnt; + wire [14 : 0] plm_v4f_mgt_reg_rst_cnt_qxu; + wire [3 : 3] plm_v4f_mgt_lstate_support; + wire [1 : 0] plm_v4f_mgt_rx3_disp_err; + wire [1 : 0] plm_v4f_mgt_rx3_run_disp; + wire [1 : 0] plm_v4f_mgt_rx2_disp_err; + wire [1 : 0] plm_v4f_mgt_rx2_run_disp; + wire [1 : 0] plm_v4f_mgt_rx1_disp_err; + wire [1 : 0] plm_v4f_mgt_rx1_run_disp; + wire [1 : 0] plm_v4f_mgt_rx0_disp_err; + wire [1 : 0] plm_v4f_mgt_rx0_run_disp; + wire [15 : 0] plm_v4f_mgt_gt11_by4_COMBUSOUT; + wire [15 : 0] plm_v4f_mgt_gt11_by4_COMBUSOUT_BLK2; + wire [15 : 0] plm_v4f_mgt_gt11_by4_COMBUSOUT_BLK3; + wire [4 : 0] plm_v4f_mgt_gt11_by4_CHBONDO_2; + wire [15 : 0] plm_v4f_mgt_gt11_by4_COMBUSOUT_BLK4; + wire [2 : 1] plm_v4f_mgt_for_v1_4_cal_inst0_cb_state; + wire [1 : 1] plm_v4f_mgt_for_v1_4_cal_inst0_sd_wr_wreg_9_i_i_0_m2; + wire [7 : 7] plm_v4f_mgt_for_v1_4_cal_inst0_sd_next_state_0_i_a2_0_a2_0_a2; + wire [15 : 0] plm_v4f_mgt_for_v1_4_cal_inst0_sd_wr_wreg; + wire [1 : 1] plm_v4f_mgt_for_v1_4_cal_inst0_GT_DADDR_5_i_i_a2_0_a2; + wire [2 : 2] plm_v4f_mgt_for_v1_4_cal_inst0_cb_state_i; + wire [2 : 1] plm_v4f_mgt_for_v1_4_cal_inst1_cb_state; + wire [1 : 1] plm_v4f_mgt_for_v1_4_cal_inst1_sd_wr_wreg_9_i_i_m2; + wire [12 : 12] plm_v4f_mgt_for_v1_4_cal_inst1_sd_wr_wreg_9_0_0_a2_0; + wire [13 : 0] plm_v4f_mgt_for_v1_4_cal_inst1_sd_state; + wire [15 : 0] plm_v4f_mgt_for_v1_4_cal_inst1_sd_wr_wreg; + wire [1 : 1] plm_v4f_mgt_for_v1_4_cal_inst1_GT_DADDR_5_i_i_a2_0_a2_0; + wire [2 : 2] plm_v4f_mgt_for_v1_4_cal_inst1_cb_state_i; + wire [2 : 1] plm_v4f_mgt_for_v1_4_cal_inst2_cb_state; + wire [1 : 1] plm_v4f_mgt_for_v1_4_cal_inst2_sd_wr_wreg_9_i_i_m2_0; + wire [12 : 12] plm_v4f_mgt_for_v1_4_cal_inst2_sd_wr_wreg_9_0_0_a2_0; + wire [13 : 0] plm_v4f_mgt_for_v1_4_cal_inst2_sd_state; + wire [15 : 0] plm_v4f_mgt_for_v1_4_cal_inst2_sd_wr_wreg; + wire [1 : 1] plm_v4f_mgt_for_v1_4_cal_inst2_GT_DADDR_5_i_i_a2_0_a2_1; + wire [2 : 2] plm_v4f_mgt_for_v1_4_cal_inst2_cb_state_i; + wire [2 : 1] plm_v4f_mgt_for_v1_4_cal_inst3_cb_state; + wire [1 : 1] plm_v4f_mgt_for_v1_4_cal_inst3_sd_wr_wreg_9_i_i_m2_1; + wire [12 : 12] plm_v4f_mgt_for_v1_4_cal_inst3_sd_wr_wreg_9_0_0_a2_0; + wire [13 : 0] plm_v4f_mgt_for_v1_4_cal_inst3_sd_state; + wire [15 : 0] plm_v4f_mgt_for_v1_4_cal_inst3_sd_wr_wreg; + wire [1 : 1] plm_v4f_mgt_for_v1_4_cal_inst3_GT_DADDR_5_i_i_a2_0_a2_2; + wire [2 : 2] plm_v4f_mgt_for_v1_4_cal_inst3_cb_state_i; + wire [0 : 0] plm_des0_reg_bad_4_i_a7_2_0; + wire [1 : 1] plm_des0_reg_bad_3_i_a7_2_0; + wire [7 : 0] plm_des0_reg_rx_des_dat_14_0_bm_2; + wire [7 : 0] plm_des0_reg_rx_des_dat_14_0_am_2; + wire [0 : 0] plm_des0_reg_bad_4_i_1; + wire [1 : 1] plm_des0_reg_bad_3_i_1; + wire [1 : 1] plm_des0_reg_bad_3_i_2; + wire [0 : 0] plm_des0_reg_bad_4_i_2; + wire [1 : 1] plm_des0_reg_skp_3_0_a7_1_0; + wire [0 : 0] plm_des0_reg_skp_4_0_a7_1_0; + wire [0 : 0] plm_des0_reg_stp_4_0_a7_1_0_0; + wire [1 : 1] plm_des0_reg_edg_3_0_a7_1_0_0; + wire [0 : 0] plm_des0_reg_edg_4_0_a7_1_0_0; + wire [1 : 1] plm_des0_reg_idl_3_2; + wire [0 : 0] plm_des0_reg_idl_4_2; + wire [0 : 0] plm_des0_reg_idl_4_1; + wire [1 : 1] plm_des0_reg_stp_3_0_a7_1_0_0; + wire [1 : 1] plm_des0_reg_idl_3_1; + wire [0 : 0] plm_des0_reg_t1p_4_0_a7_2_0; + wire [0 : 0] plm_des0_reg_t1n_4_1; + wire [1 : 1] plm_des0_reg_t2p_3_1_0; + wire [1 : 1] plm_des0_reg_t1n_3_0_a7_2_0; + wire [0 : 0] plm_des0_reg_t1p_4_1; + wire [0 : 0] plm_des0_reg_t1n_4_0_a7_2_0; + wire [1 : 1] plm_des0_reg_t2n_3_0_a7_1_0_0; + wire [1 : 1] plm_des0_reg_t1n_3_1; + wire [3 : 3] plm_des0_reg_lfsr_one_12_iv_i_0_0_a2; + wire [15 : 1] plm_des0_one_adv2; + wire [12 : 12] plm_des0_reg_lfsr_two_12_0_iv_0_0_0_o2; + wire [9 : 9] plm_des0_reg_lfsr_two_12_iv_0_0_0_o4; + wire [9 : 9] plm_des0_reg_lfsr_two_12_iv_0_0_0_a4_1_0; + wire [7 : 0] plm_des0_reg_rx_des_dat_14; + wire [1 : 0] plm_des0_reg_bad; + wire [0 : 0] plm_des0_reg_stp_4; + wire [1 : 0] plm_des0_reg_stp; + wire [1 : 1] plm_des0_reg_skp_3; + wire [1 : 0] plm_des0_reg_skp; + wire [0 : 0] plm_des0_reg_skp_4; + wire [1 : 1] plm_des0_reg_sdp_3; + wire [1 : 0] plm_des0_reg_sdp; + wire [0 : 0] plm_des0_reg_sdp_4; + wire [1 : 1] plm_des0_reg_pad_3; + wire [1 : 0] plm_des0_reg_pad; + wire [0 : 0] plm_des0_reg_pad_4; + wire [1 : 1] plm_des0_reg_idl_3; + wire [1 : 0] plm_des0_reg_idl; + wire [0 : 0] plm_des0_reg_idl_4; + wire [1 : 1] plm_des0_reg_fts_3; + wire [1 : 0] plm_des0_reg_fts; + wire [0 : 0] plm_des0_reg_fts_4; + wire [1 : 1] plm_des0_reg_edg_3; + wire [1 : 0] plm_des0_reg_edg; + wire [0 : 0] plm_des0_reg_edg_4; + wire [1 : 1] plm_des0_reg_edb_3; + wire [0 : 0] plm_des0_reg_edb_4; + wire [1 : 1] plm_des0_reg_com_3; + wire [0 : 0] plm_des0_reg_com_4; + wire [1 : 0] plm_des0_reg_edb; + wire [1 : 0] plm_des0_reg_com; + wire [1 : 1] plm_des0_reg_stp_3; + wire [1 : 1] plm_des0_reg_t1p_3; + wire [1 : 1] plm_des0_reg_t1p; + wire [1 : 1] plm_des0_reg_t1n_3; + wire [1 : 1] plm_des0_reg_t1n; + wire [1 : 1] plm_des0_reg_sym_3; + wire [1 : 0] plm_des0_reg_sym; + wire [0 : 0] plm_des0_reg_sym_4; + wire [1 : 1] plm_des0_reg_t2p_3; + wire [1 : 1] plm_des0_reg_t2p; + wire [1 : 1] plm_des0_reg_t2n_3; + wire [1 : 1] plm_des0_reg_t2n; + wire [1 : 0] plm_des0_reg_nitbl; + wire [15 : 0] plm_des0_reg_data; + wire [15 : 0] plm_des0_reg_dat; + wire [1 : 0] plm_des0_reg_spesh; + wire [1 : 0] plm_des0_reg_kkk; + wire [0 : 0] plm_des1_reg_bad_4_i_a7_2_0; + wire [1 : 1] plm_des1_reg_bad_3_i_a7_2_0; + wire [4 : 4] plm_des1_two_adv2_0; + wire [7 : 0] plm_des1_reg_rx_des_dat_14_0_bm_1; + wire [7 : 0] plm_des1_reg_rx_des_dat_14_0_am_1; + wire [0 : 0] plm_des1_reg_bad_4_i_1; + wire [1 : 1] plm_des1_reg_bad_3_i_1; + wire [1 : 1] plm_des1_reg_bad_3_i_2; + wire [0 : 0] plm_des1_reg_bad_4_i_2; + wire [0 : 0] plm_des1_reg_skp_4_0_a7_1; + wire [1 : 1] plm_des1_reg_pad_3_0_a7_0; + wire [0 : 0] plm_des1_reg_pad_4_0_a7_0; + wire [1 : 1] plm_des1_reg_pad_3_5; + wire [0 : 0] plm_des1_reg_skp_4_3; + wire [0 : 0] plm_des1_reg_pad_4_5; + wire [1 : 1] plm_des1_reg_t2n_3_0_a7_0_2; + wire [1 : 1] plm_des1_reg_t1p_3_1; + wire [0 : 0] plm_des1_reg_t2n_4_0_a7_0_2; + wire [0 : 0] plm_des1_reg_t1p_4_1; + wire [1 : 1] plm_des1_reg_t2n_3_3; + wire [1 : 1] plm_des1_reg_t1n_3_1; + wire [0 : 0] plm_des1_reg_t2n_4_3; + wire [0 : 0] plm_des1_reg_t1n_4_1; + wire [1 : 1] plm_des1_reg_skp_3_3; + wire [1 : 1] plm_des1_reg_skp_3_0_a7_1; + wire [15 : 1] plm_des1_one_adv2; + wire [3 : 3] plm_des1_reg_lfsr_one_12_iv_i_0_0_a2_0; + wire [15 : 15] plm_des1_reg_lfsr_two_12_iv_i_0_0_a2; + wire [12 : 12] plm_des1_reg_lfsr_two_12_0_iv_0_0_o2; + wire [9 : 9] plm_des1_reg_lfsr_two_12_iv_0_0_0_o4_0; + wire [9 : 9] plm_des1_reg_lfsr_two_12_iv_0_0_0_a4_1; + wire [7 : 0] plm_des1_reg_rx_des_dat_14; + wire [1 : 1] plm_des1_reg_t2n_3; + wire [1 : 0] plm_des1_reg_bad; + wire [0 : 0] plm_des1_reg_skp_4; + wire [1 : 0] plm_des1_reg_skp; + wire [1 : 1] plm_des1_reg_com_3; + wire [0 : 0] plm_des1_reg_com_4; + wire [1 : 1] plm_des1_reg_t2n; + wire [1 : 1] plm_des1_reg_t2p_3; + wire [1 : 1] plm_des1_reg_t2p; + wire [1 : 1] plm_des1_reg_t1p_3; + wire [1 : 1] plm_des1_reg_t1p; + wire [1 : 1] plm_des1_reg_t1n_3; + wire [1 : 1] plm_des1_reg_t1n; + wire [1 : 1] plm_des1_reg_skp_3; + wire [1 : 0] plm_des1_reg_nitbl; + wire [1 : 1] plm_des1_reg_sym_3; + wire [1 : 0] plm_des1_reg_sym; + wire [0 : 0] plm_des1_reg_sym_4; + wire [15 : 0] plm_des1_reg_data; + wire [15 : 0] plm_des1_reg_dat; + wire [1 : 0] plm_des1_reg_spesh; + wire [1 : 0] plm_des1_reg_kkk; + wire [1 : 1] plm_des2_reg_bad_3_i_a7_2_0; + wire [0 : 0] plm_des2_reg_bad_4_i_a7_2_0; + wire [4 : 4] plm_des2_two_adv2_0; + wire [7 : 0] plm_des2_reg_rx_des_dat_14_0_bm_0; + wire [7 : 0] plm_des2_reg_rx_des_dat_14_0_am_0; + wire [1 : 1] plm_des2_reg_bad_3_i_1; + wire [0 : 0] plm_des2_reg_bad_4_i_1; + wire [1 : 1] plm_des2_reg_bad_3_i_2; + wire [0 : 0] plm_des2_reg_bad_4_i_2; + wire [1 : 1] plm_des2_reg_skp_3_0_a7_1; + wire [0 : 0] plm_des2_reg_skp_4_0_a7_1; + wire [1 : 1] plm_des2_reg_pad_3_0_a7_0; + wire [0 : 0] plm_des2_reg_pad_4_0_a7_0; + wire [1 : 1] plm_des2_reg_skp_3_3; + wire [1 : 1] plm_des2_reg_pad_3_5; + wire [0 : 0] plm_des2_reg_skp_4_3; + wire [0 : 0] plm_des2_reg_pad_4_5; + wire [1 : 1] plm_des2_reg_t2n_3_0_a7_0_2; + wire [1 : 1] plm_des2_reg_t1p_3_1; + wire [0 : 0] plm_des2_reg_t2n_4_0_a7_0_2; + wire [0 : 0] plm_des2_reg_t1p_4_1; + wire [1 : 1] plm_des2_reg_t2n_3_3; + wire [1 : 1] plm_des2_reg_t1n_3_1; + wire [0 : 0] plm_des2_reg_t2n_4_3; + wire [0 : 0] plm_des2_reg_t1n_4_1; + wire [15 : 1] plm_des2_one_adv2; + wire [3 : 3] plm_des2_reg_lfsr_one_12_iv_i_0_a2; + wire [15 : 15] plm_des2_reg_lfsr_two_12_iv_i_0_a2; + wire [12 : 12] plm_des2_reg_lfsr_two_12_0_iv_0_o2; + wire [3 : 3] plm_des2_reg_lfsr_two_12_iv_0_0_a2_0; + wire [9 : 9] plm_des2_reg_lfsr_two_12_iv_0_0_o4; + wire [9 : 9] plm_des2_reg_lfsr_two_12_iv_0_0_a4_1; + wire [7 : 0] plm_des2_reg_rx_des_dat_14; + wire [1 : 1] plm_des2_reg_t2p_3; + wire [1 : 1] plm_des2_reg_t2n_3; + wire [1 : 0] plm_des2_reg_bad; + wire [1 : 1] plm_des2_reg_skp_3; + wire [1 : 0] plm_des2_reg_skp; + wire [0 : 0] plm_des2_reg_skp_4; + wire [1 : 1] plm_des2_reg_com_3; + wire [0 : 0] plm_des2_reg_com_4; + wire [1 : 1] plm_des2_reg_t2p; + wire [1 : 1] plm_des2_reg_t2n; + wire [1 : 1] plm_des2_reg_t1p_3; + wire [1 : 1] plm_des2_reg_t1p; + wire [1 : 1] plm_des2_reg_t1n_3; + wire [1 : 1] plm_des2_reg_t1n; + wire [1 : 0] plm_des2_reg_nitbl; + wire [1 : 1] plm_des2_reg_sym_3; + wire [1 : 0] plm_des2_reg_sym; + wire [0 : 0] plm_des2_reg_sym_4; + wire [15 : 0] plm_des2_reg_data; + wire [15 : 0] plm_des2_reg_dat; + wire [1 : 0] plm_des2_reg_spesh; + wire [1 : 0] plm_des2_reg_kkk; + wire [0 : 0] plm_des3_reg_bad_4_i_a7_2_0; + wire [1 : 1] plm_des3_reg_bad_3_i_a7_2_0; + wire [4 : 4] plm_des3_two_adv2_0; + wire [7 : 0] plm_des3_reg_rx_des_dat_14_0_bm; + wire [7 : 0] plm_des3_reg_rx_des_dat_14_0_am; + wire [0 : 0] plm_des3_reg_bad_4_i_1; + wire [1 : 1] plm_des3_reg_bad_3_i_1; + wire [1 : 1] plm_des3_reg_bad_3_i_2; + wire [0 : 0] plm_des3_reg_bad_4_i_2; + wire [0 : 0] plm_des3_reg_pad_4_0_a7_0; + wire [1 : 1] plm_des3_reg_edg_3_0_a7_1_0_0; + wire [0 : 0] plm_des3_reg_edg_4_0_a7_1_0_0; + wire [0 : 0] plm_des3_reg_pad_4_5; + wire [0 : 0] plm_des3_reg_t2p_4_0_a7_0; + wire [1 : 1] plm_des3_reg_t2n_3_0_a7_0; + wire [1 : 1] plm_des3_reg_t1p_3_2; + wire [1 : 1] plm_des3_reg_t1p_3_0_a7_0; + wire [0 : 0] plm_des3_reg_t2p_4_2; + wire [0 : 0] plm_des3_reg_t2n_4_2_0; + wire [1 : 1] plm_des3_reg_skp_3_3; + wire [1 : 1] plm_des3_reg_skp_3_1_0; + wire [1 : 1] plm_des3_reg_skp_3_1; + wire [0 : 0] plm_des3_reg_skp_4_3; + wire [0 : 0] plm_des3_reg_skp_4_1; + wire [0 : 0] plm_des3_reg_pad_4_5_1; + wire [1 : 1] plm_des3_reg_pad_3_5; + wire [1 : 1] plm_des3_reg_pad_3_0_a7_0; + wire [0 : 0] plm_des3_reg_t2n_4_1_0; + wire [0 : 0] plm_des3_reg_t1n_4_0_a7_0; + wire [1 : 1] plm_des3_reg_t1n_3_2; + wire [1 : 1] plm_des3_reg_t1n_3_1; + wire [15 : 1] plm_des3_one_adv2; + wire [3 : 3] plm_des3_reg_lfsr_one_12_iv_i_0_a2_0; + wire [15 : 15] plm_des3_reg_lfsr_two_12_iv_i_0_a2_0; + wire [14 : 14] plm_des3_reg_lfsr_two_12_iv_i_0_0; + wire [12 : 12] plm_des3_reg_lfsr_two_12_0_iv_0_o2_0; + wire [3 : 3] plm_des3_reg_lfsr_two_12_iv_0_0_0_a2; + wire [9 : 9] plm_des3_reg_lfsr_two_12_iv_0_0_o4_0; + wire [9 : 9] plm_des3_reg_lfsr_two_12_iv_0_0_a4_1_0; + wire [7 : 0] plm_des3_reg_rx_des_dat_14; + wire [1 : 0] plm_des3_reg_bad; + wire [1 : 1] plm_des3_reg_edg_3; + wire [0 : 0] plm_des3_reg_edg_4; + wire [1 : 1] plm_des3_reg_edb_3; + wire [0 : 0] plm_des3_reg_edb_4; + wire [1 : 1] plm_des3_reg_com_3; + wire [0 : 0] plm_des3_reg_com_4; + wire [1 : 1] plm_des3_reg_t2p_3; + wire [1 : 1] plm_des3_reg_t2p; + wire [1 : 1] plm_des3_reg_t2n_3; + wire [1 : 1] plm_des3_reg_t2n; + wire [1 : 1] plm_des3_reg_t1p_3; + wire [1 : 0] plm_des3_reg_edg; + wire [1 : 0] plm_des3_reg_edb; + wire [1 : 1] plm_des3_reg_skp_3; + wire [1 : 0] plm_des3_reg_skp; + wire [0 : 0] plm_des3_reg_skp_4; + wire [1 : 1] plm_des3_reg_t1p; + wire [1 : 1] plm_des3_reg_t1n_3; + wire [1 : 1] plm_des3_reg_t1n; + wire [1 : 0] plm_des3_reg_nitbl; + wire [1 : 1] plm_des3_reg_sym_3; + wire [1 : 0] plm_des3_reg_sym; + wire [0 : 0] plm_des3_reg_sym_4; + wire [15 : 0] plm_des3_reg_data; + wire [15 : 0] plm_des3_reg_dat; + wire [1 : 0] plm_des3_reg_spesh; + wire [1 : 0] plm_des3_reg_kkk; + wire [1 : 1] plm_scr0_reg_com_3_0_a2_1_4; + wire [0 : 0] plm_scr0_reg_skp_4_0_a2_1_4; + wire [15 : 0] plm_scr0_one_adv2; + wire [6 : 1] plm_scr0_reg_tx_data_12_2_bm_1; + wire [6 : 1] plm_scr0_reg_tx_data_12_2_am_1; + wire [0 : 0] plm_scr0_reg_skp_4_1; + wire [1 : 1] plm_scr0_reg_com_3_1; + wire [4 : 4] plm_scr0_one_adv2_i_m; + wire [15 : 15] plm_scr0_reg_lfsr_two_12_iv_i_a2; + wire [8 : 8] plm_scr0_reg_lfsr_two_12_iv_0_a2; + wire [15 : 15] plm_scr0_reg_lfsr_two_12_iv_i_o4_1; + wire [0 : 0] plm_scr0_reg_skp_4; + wire [1 : 0] plm_scr0_reg_skp; + wire [1 : 1] plm_scr0_reg_com_3; + wire [1 : 0] plm_scr0_reg_com; + wire [0 : 0] plm_scr0_reg_com_4; + wire [1 : 0] plm_scr0_reg_dis; + wire [15 : 8] plm_scr0_reg_tx_data_6; + wire [7 : 0] plm_scr0_reg_tx_data_12; + wire [1 : 1] plm_scr0_reg_skp_3; + wire [15 : 0] plm_scr0_reg_dat; + wire [1 : 0] plm_scr0_reg_kkk; + wire [1 : 0] plm_scr0_reg_raw_char_is_k; + wire [15 : 0] plm_scr0_reg_raw_char; + wire [1 : 0] plm_scr0_reg_raw_char_pass; + wire [4 : 4] plm_scr0_reg_lfsr_one_12; + wire [0 : 0] plm_scr1_reg_com_4_0_a2_1_4; + wire [1 : 1] plm_scr1_reg_com_3_0_a2_1_4; + wire [15 : 0] plm_scr1_one_adv2; + wire [6 : 1] plm_scr1_reg_tx_data_12_2_bm_0; + wire [6 : 1] plm_scr1_reg_tx_data_12_2_am_0; + wire [1 : 1] plm_scr1_reg_com_3_1; + wire [0 : 0] plm_scr1_reg_com_4_1; + wire [5 : 5] plm_scr1_reg_lfsr_two_m; + wire [8 : 8] plm_scr1_one_adv2_m_0; + wire [7 : 0] plm_scr1_reg_tx_data_12; + wire [1 : 1] plm_scr1_reg_skp_3; + wire [1 : 0] plm_scr1_reg_skp; + wire [0 : 0] plm_scr1_reg_skp_4; + wire [1 : 1] plm_scr1_reg_com_3; + wire [1 : 0] plm_scr1_reg_com; + wire [0 : 0] plm_scr1_reg_com_4; + wire [15 : 0] plm_scr1_reg_raw_char; + wire [15 : 0] plm_scr1_reg_dat; + wire [0 : 0] plm_scr2_reg_com_4_0_a2_1_4; + wire [1 : 1] plm_scr2_reg_skp_3_0_a2_1_4; + wire [6 : 1] plm_scr2_reg_tx_data_12_2_m2_0_bm; + wire [6 : 1] plm_scr2_reg_tx_data_12_2_m2_0_am; + wire [4 : 4] plm_scr2_two_adv2_0; + wire [6 : 1] plm_scr2_reg_tx_data_12_2_m2_0; + wire [1 : 1] plm_scr2_reg_skp_3_1; + wire [0 : 0] plm_scr2_reg_com_4_1; + wire [15 : 15] plm_scr2_reg_lfsr_two_12_iv_i_a2_0; + wire [14 : 14] plm_scr2_reg_lfsr_two_12_iv_i_0; + wire [8 : 8] plm_scr2_reg_lfsr_two_12_iv_0_a2_0; + wire [5 : 5] plm_scr2_reg_lfsr_two_12_iv_0_a2; + wire [15 : 15] plm_scr2_reg_lfsr_two_12_iv_i_o4_0; + wire [1 : 1] plm_scr2_reg_skp_3; + wire [1 : 0] plm_scr2_reg_skp; + wire [0 : 0] plm_scr2_reg_skp_4; + wire [1 : 1] plm_scr2_reg_com_3; + wire [1 : 0] plm_scr2_reg_com; + wire [0 : 0] plm_scr2_reg_com_4; + wire [15 : 15] plm_scr2_reg_tx_data_6; + wire [15 : 0] plm_scr2_reg_raw_char; + wire [15 : 0] plm_scr2_reg_dat; + wire [0 : 0] plm_scr2_reg_lfsr_one_12; + wire [10 : 5] plm_scr2_reg_lfsr_two; + wire [7 : 7] plm_scr3_two_adv2_1_0; + wire [1 : 1] plm_scr3_reg_com_3_0_a2_1_4; + wire [0 : 0] plm_scr3_reg_com_4_0_a2_1_4; + wire [9 : 9] plm_scr3_two_adv2_0; + wire [7 : 0] plm_scr3_reg_tx_data_12_2_bm; + wire [7 : 0] plm_scr3_reg_tx_data_12_2_am; + wire [0 : 0] plm_scr3_reg_com_4_1; + wire [1 : 1] plm_scr3_reg_com_3_1; + wire [15 : 0] plm_scr3_one_adv2; + wire [10 : 8] plm_scr3_reg_lfsr_one_12_iv_i_a2_0_1; + wire [6 : 6] plm_scr3_reg_lfsr_one_12_iv_i_a2; + wire [4 : 4] plm_scr3_one_adv2_i_m; + wire [15 : 15] plm_scr3_reg_lfsr_two_12_iv_i_a2_1; + wire [14 : 14] plm_scr3_reg_lfsr_two_12_iv_i_a2_0_0; + wire [15 : 15] plm_scr3_reg_lfsr_two_12_iv_i_o4; + wire [7 : 0] plm_scr3_reg_tx_data_12; + wire [15 : 8] plm_scr3_reg_tx_data_6; + wire [0 : 0] plm_scr3_reg_skp_4; + wire [1 : 0] plm_scr3_reg_skp; + wire [1 : 1] plm_scr3_reg_com_3; + wire [1 : 0] plm_scr3_reg_com; + wire [0 : 0] plm_scr3_reg_com_4; + wire [1 : 0] plm_scr3_reg_dis; + wire [1 : 1] plm_scr3_reg_skp_3; + wire [15 : 0] plm_scr3_reg_raw_char; + wire [15 : 0] plm_scr3_reg_dat; + wire [1 : 0] plm_scr3_reg_raw_char_is_k; + wire [1 : 0] plm_scr3_reg_kkk; + wire [4 : 4] plm_scr3_reg_lfsr_one_12; + wire [6 : 6] plm_tsi0_reg_dec9; + wire [3 : 0] plm_tsi0_reg_ts2_timer; + wire [3 : 0] plm_tsi0_reg_ts1_timer; + wire [15 : 0] plm_tsi0_reg_dly8; + wire [11 : 8] plm_tsi0_reg_dec1_6104; + wire [7 : 0] plm_tsi0_reg_dly9; + wire [15 : 0] plm_tsi0_do; + wire [15 : 0] plm_tsi0_reg_dly7; + wire [12 : 12] plm_tsi0_reg_dec6_6105; + wire [7 : 0] plm_tsi0_reg_lane_num_3; + wire [7 : 0] plm_tsi0_reg_link_num_3; + wire [0 : 0] plm_tsi0_reg_dec6_tmp_d_array_0; + wire [0 : 0] plm_tsi0_reg_dec8_tmp_d_array_0; + wire [0 : 0] plm_tsi0_reg_dec7_tmp_d_array_0; + wire [0 : 0] plm_tsi0_reg_dec5_tmp_d_array_0; + wire [3 : 0] plm_tsi0_reg_ts2_timer_5; + wire [3 : 0] plm_tsi0_reg_ts1_timer_5; + wire [6 : 6] plm_tsi1_reg_dec9; + wire [3 : 0] plm_tsi1_reg_ts2_timer; + wire [3 : 0] plm_tsi1_reg_ts1_timer; + wire [11 : 8] plm_tsi1_reg_dec1_6106; + wire [15 : 0] plm_tsi1_reg_dly8; + wire [7 : 0] plm_tsi1_reg_dly9; + wire [15 : 0] plm_tsi1_do; + wire [15 : 0] plm_tsi1_reg_dly7; + wire [12 : 12] plm_tsi1_reg_dec6_6107; + wire [7 : 0] plm_tsi1_reg_lane_num_3; + wire [7 : 0] plm_tsi1_reg_link_num_3; + wire [0 : 0] plm_tsi1_reg_dec7_tmp_d_array_0; + wire [3 : 0] plm_tsi1_reg_ts2_timer_5; + wire [3 : 0] plm_tsi1_reg_ts1_timer_5; + wire [6 : 6] plm_tsi2_reg_dec9; + wire [3 : 0] plm_tsi2_reg_ts1_timer; + wire [3 : 0] plm_tsi2_reg_ts2_timer; + wire [15 : 0] plm_tsi2_reg_dly8; + wire [11 : 8] plm_tsi2_reg_dec1_6108; + wire [7 : 0] plm_tsi2_reg_dly9; + wire [12 : 12] plm_tsi2_reg_dec6_6109; + wire [15 : 0] plm_tsi2_do; + wire [15 : 0] plm_tsi2_reg_dly7; + wire [7 : 0] plm_tsi2_reg_lane_num_3; + wire [7 : 0] plm_tsi2_reg_link_num_3; + wire [3 : 0] plm_tsi2_reg_ts1_timer_5; + wire [3 : 0] plm_tsi2_reg_ts2_timer_5; + wire [6 : 6] plm_tsi3_reg_dec9; + wire [3 : 0] plm_tsi3_reg_ts1_timer; + wire [3 : 0] plm_tsi3_reg_ts2_timer; + wire [15 : 0] plm_tsi3_reg_dly8; + wire [11 : 8] plm_tsi3_reg_dec1_6110; + wire [7 : 0] plm_tsi3_reg_dly9; + wire [12 : 12] plm_tsi3_reg_dec6_6111; + wire [15 : 0] plm_tsi3_do; + wire [15 : 0] plm_tsi3_reg_dly7; + wire [7 : 0] plm_tsi3_reg_lane_num_3; + wire [7 : 0] plm_tsi3_reg_link_num_3; + wire [3 : 0] plm_tsi3_reg_ts1_timer_5; + wire [3 : 0] plm_tsi3_reg_ts2_timer_5; + wire [1 : 0] plm_dfm_by4_prel_sdpstp; + wire [1 : 0] plm_dfm_by1_prel_sdpstp; + wire [1 : 0] plm_dfm_by4_preh_sdpstp; + wire [1 : 0] plm_dfm_by1_preh_sdpstp; + wire [1 : 0] plm_dfm_by4_prel_edbedg; + wire [1 : 0] plm_dfm_by1_prel_edbedg; + wire [1 : 0] plm_dfm_by4_preh_edbedg; + wire [1 : 0] plm_dfm_by1_preh_edbedg; + wire [31 : 0] plm_dfm_by4_preh_out; + wire [31 : 0] plm_dfm_by1_preh_out; + wire [31 : 0] plm_dfm_by4_prel_out; + wire [31 : 0] plm_dfm_by1_prel_out; + wire [1 : 1] plm_dfm_prel_sdpstp; + wire [0 : 0] plm_dfm_prel_sdpstp_i_m3_0; + wire [31 : 0] plm_dfm_preh_out_i_m3_0; + wire [27 : 27] plm_dfm_prel_out_i_m2_0; + wire [26 : 21] plm_dfm_prel_out; + wire [1 : 0] plm_dfm_preh_sdpstp_i_m3_0; + wire [31 : 0] plm_dfm_deframe1_dword_out; + wire [2 : 2] plm_dfm_deframe1_reg_push_0_i_0; + wire [1 : 0] plm_dfm_deframe1_reg_fsm_substate; + wire [1 : 0] plm_dfm_deframe1_reg_fsm_last_substate; + wire [1 : 0] plm_dfm_deframe1_reg_any_bad_6_0_a2_0_a2_0_a3_0_a2_3; + wire [1 : 0] plm_dfm_deframe1_reg_any_bad; + wire [1 : 0] plm_dfm_deframe1_reg_any_sta; + wire [1 : 0] plm_dfm_deframe1_reg_any_end; + wire [1 : 0] plm_dfm_deframe1_reg_stp_5; + wire [15 : 0] plm_dfm_deframe1_reg_dat_6; + wire [1 : 0] plm_dfm_deframe1_reg_delay_sdp; + wire [1 : 0] plm_dfm_deframe1_reg_delay_edg; + wire [1 : 0] plm_dfm_deframe1_reg_delay_edb; + wire [1 : 0] plm_dfm_deframe1_reg_sdp_5; + wire [1 : 0] plm_dfm_deframe1_reg_sdp; + wire [1 : 0] plm_dfm_deframe1_reg_edg_5; + wire [1 : 0] plm_dfm_deframe1_reg_edg; + wire [1 : 0] plm_dfm_deframe1_reg_edb_5; + wire [1 : 0] plm_dfm_deframe1_reg_edb; + wire [1 : 0] plm_dfm_deframe1_reg_any_sym; + wire [15 : 0] plm_dfm_deframe1_reg_dat; + wire [15 : 0] plm_dfm_deframe1_reg_delay_dat; + wire [1 : 0] plm_dfm_deframe1_reg_stp; + wire [1 : 0] plm_dfm_deframe1_reg_delay_stp; + wire [0 : 0] plm_dfm_deframe1_dwfsm_ns_fsm_substate_i_i_0_1; + wire [1 : 1] plm_dfm_deframe1_dwfsm_ns_fsm_substate_i_i_0_a2; + wire [1 : 0] plm_dfm_deframe1_dwbuf_wd_s0_i_m4_0; + wire [7 : 0] plm_dfm_deframe1_dwbuf_wd_l3_i_m4_0; + wire [7 : 0] plm_dfm_deframe1_dwbuf_wd_l2_i_m4_0; + wire [7 : 0] plm_dfm_deframe1_dwbuf_wd_l1_i_m4_0; + wire [7 : 0] plm_dfm_deframe1_dwbuf_wd_l0_i_m4_0; + wire [3 : 0] plm_dfm_deframe1_dwbuf_reg_wp1_4; + wire [3 : 0] plm_dfm_deframe1_dwbuf_reg_wp1; + wire [3 : 0] plm_dfm_deframe1_dwbuf_reg_wp0_4; + wire [3 : 0] plm_dfm_deframe1_dwbuf_reg_wp0; + wire [3 : 0] plm_dfm_deframe1_dwbuf_reg_rp_4; + wire [3 : 0] plm_dfm_deframe1_dwbuf_reg_rp; + wire [1 : 0] plm_dfm_deframe1_dwbuf_dpo_edbedg; + wire [3 : 0] plm_dfm_deframe1_dwbuf_reg_cnt; + wire [3 : 0] plm_dfm_deframe1_dwbuf_reg_wp3_4; + wire [3 : 0] plm_dfm_deframe1_dwbuf_reg_wp3; + wire [3 : 0] plm_dfm_deframe1_dwbuf_reg_wp2_4; + wire [3 : 0] plm_dfm_deframe1_dwbuf_reg_wp2; + wire [31 : 0] plm_dfm_deframe1_dwbuf_dpo_out; + wire [1 : 0] plm_dfm_deframe1_dwbuf_dpo_sdpstp; + wire [1 : 0] plm_dfm_deframe1_qwfsm_nxt_state_i_i_0_o4; + wire [5 : 2] plm_dfm_deframe1_qwfsm_reg_state; + wire [1 : 0] plm_dfm_deframe4_dh_cmd; + wire [7 : 0] plm_dfm_deframe4_dh_dat_m; + wire [31 : 0] plm_dfm_deframe4_reg_h_dword_8; + wire [31 : 0] plm_dfm_deframe4_dh_dat; + wire [31 : 0] plm_dfm_deframe4_reg_l_dword_8; + wire [1 : 0] plm_dfm_deframe4_dh_edbedg; + wire [1 : 0] plm_dfm_deframe4_lo_edbedg; + wire [0 : 0] plm_dfm_deframe4_ho_sdpstp; + wire [1 : 0] plm_dfm_deframe4_reg_df_sdpstp; + wire [1 : 0] plm_dfm_deframe4_dl_edbedg; + wire [1 : 0] plm_dfm_deframe4_reg_df_edbedg; + wire [1 : 0] plm_dfm_deframe4_dl_cmd; + wire [0 : 0] plm_dfm_deframe4_reg_df_cmd; + wire [0 : 0] plm_dfm_deframe4_lo_sdpstp; + wire [1 : 0] plm_dfm_deframe4_reg_l_sdpstp_5; + wire [1 : 0] plm_dfm_deframe4_dl_sdpstp; + wire [1 : 0] plm_dfm_deframe4_reg_h_sdpstp_5; + wire [1 : 0] plm_dfm_deframe4_dh_sdpstp; + wire [31 : 0] plm_dfm_deframe4_dl_dat; + wire [31 : 0] plm_dfm_deframe4_reg_df_dat; + wire [1 : 0] plm_dfm_deframe4_ho_edbedg; + wire [7 : 0] plm_dfm_deframe4_frm4hi_half_o_dat_iv_0; + wire [1 : 0] plm_dfm_deframe4_frm4hi_half_o_edbedg_0_1; + wire [0 : 0] plm_dfm_deframe4_frm4lo_half_o_edbedg_1_bm; + wire [0 : 0] plm_dfm_deframe4_frm4lo_half_o_edbedg_1_am; + wire [0 : 0] plm_dfm_deframe4_frm4lo_half_reg_o_edbedg_cnst; + wire [1 : 1] plm_dfm_deframe4_frm4lo_half_o_edbedg_1_1; + wire [1 : 0] plm_dfm_deframe4_frm4lo_half_do_cmd_m0; + wire [31 : 24] plm_dfm_deframe4_frm4lo_half_o_dat_iv_0; + wire [1 : 0] plm_sym_sym_pass; + wire [1 : 0] plm_sym_sym_is_k; + wire [3 : 3] plm_sym_reg_tx1_raw_char_8_i_0_0_0_o3; + wire [4 : 4] plm_sym_reg_tx1_raw_char_8_2_0_bm; + wire [4 : 4] plm_sym_reg_tx1_raw_char_8_2_0_am; + wire [2 : 1] plm_sym_reg_sym_gen_sel; + wire [0 : 0] plm_sym_reg_sym_gen_sel_15; + wire [0 : 0] plm_sym_reg_tx1_raw_char_8_i_0_0_0_o2_0; + wire [0 : 0] plm_sym_un1_reg_tx0_raw_char_pass_f1_0; + wire [4 : 4] plm_sym_sent_status; + wire [0 : 0] plm_sym_reg_tx1_raw_char_8_i_0_0_0_o2; + wire [11 : 11] plm_sym_reg_tx3_raw_char_8_i_i_0_i_1; + wire [2 : 0] plm_sym_sym_bypass; + wire [0 : 0] plm_sym_reg_tx0_raw_char_is_k_8_0_a2_i_0_0_0; + wire [0 : 0] plm_sym_reg_tx1_raw_char_is_k_8_0_a2_i_0_0_1; + wire [11 : 1] plm_sym_reg_count_6112; + wire [2 : 2] plm_sym_sym_gen_next_addr_cnst; + wire [25 : 25] plm_sym_sym_gen_reg_rom_out_27_0_0; + wire [5 : 0] plm_sym_sym_gen_reg_rom_out; + wire [27 : 27] plm_sym_sym_gen_reg_rom_out_27_0_a3; + wire [1 : 0] plm_frm_reg_wd_sel; + wire [1 : 1] plm_frm_reg_frm0_is_k_3_0_0; + wire [1 : 1] plm_frm_reg_frm0_char_3_i_m3_0_0; + wire [2 : 2] plm_frm_reg_frm0_char_3_0_m3_0_0; + wire [1 : 0] plm_frm_reg_state; + wire [2 : 2] plm_frm_reg_frm0_char_3_0_m3_0_3; + wire [2 : 2] plm_frm_reg_frm0_char_3_0_m3_0_2; + wire [1 : 1] plm_frm_reg_frm0_char_3_i_m3_0_3; + wire [1 : 1] plm_frm_reg_frm0_char_3_i_m3_0_2; + wire [1 : 1] plm_frm_reg_frm0_is_k_3_0_2; + wire [0 : 0] plm_frm_un7_by4_frm1_char_i_o2; + wire [0 : 0] plm_frm_reg_frm0_is_k_3_i_m3_i_0; + wire [13 : 13] plm_frm_reg_frm0_char_3_0_1; + wire [15 : 15] plm_frm_reg_frm0_char_3_i_m3_0_1; + wire [63 : 0] plm_frm_reg_d0_td; + wire [63 : 0] plm_frm_reg_d1_td; + wire [63 : 0] plm_frm_reg_d2_td; + wire [1 : 1] plm_frm_reg_d2_td_24_0_iv_i_a2; + wire [1 : 0] plm_frm_frame1_reg_wd_sel_5; + wire [10 : 10] plm_fsm_reg_tx_count_6_0; + wire [10 : 10] plm_fsm_reg_state_141_0_0_1_iv_i_0_0_a3_1; + wire [0 : 0] plm_fsm_reg_state_141_0_0_1_iv_2; + wire [3 : 3] plm_fsm_reg_state_141_0_0_2_iv_0; + wire [24 : 24] plm_fsm_reg_state_141_0_0_1_iv_i_0_i_i_2_0; + wire [7 : 7] plm_fsm_reg_state_141_0_0_1_iv_i_0_i_a3_i_o3; + wire [0 : 0] plm_fsm_reg_state_141_0_0_1_iv_10; + wire [0 : 0] plm_fsm_reg_state_141_0_0_1_iv_11; + wire [0 : 0] plm_fsm_reg_state_141_0_0_1_iv_12; + wire [0 : 0] plm_fsm_reg_state_141_0_0_1_iv_6; + wire [0 : 0] plm_fsm_reg_state_141_0_0_1_iv_5; + wire [0 : 0] plm_fsm_reg_state_141_0_0_1_iv_4; + wire [0 : 0] plm_fsm_reg_state_141_0_0_1_iv_13; + wire [3 : 3] plm_fsm_reg_state_141_0_0_2_iv_1; + wire [0 : 0] plm_fsm_reg_state_141_0_0_1_iv_15; + wire [0 : 0] plm_fsm_reg_state_141_0_0_1_iv_14; + wire [12 : 12] plm_fsm_reg_state_141_0_0_1_iv_i_0; + wire [10 : 10] plm_fsm_reg_state_141_0_0_1_iv_i_0_0_a3_3; + wire [10 : 10] plm_fsm_reg_state_141_0_0_1_iv_i_0_0_a3_0_1; + wire [0 : 0] plm_fsm_reg_send_command_28_1; + wire [10 : 10] plm_fsm_reg_state_141_0_0_1_iv_i_0_0_0; + wire [10 : 10] plm_fsm_reg_state_141_0_0_1_iv_i_0_0_0_1; + wire [8 : 0] plm_fsm_reg_rx0_old; + wire [8 : 0] plm_fsm_reg_rx1_old; + wire [8 : 0] plm_fsm_reg_rx2_old; + wire [8 : 0] plm_fsm_reg_rx3_old; + wire [8 : 0] plm_fsm_reg_xl_rx0_old; + wire [8 : 0] plm_fsm_reg_xl_rx1_old; + wire [8 : 0] plm_fsm_reg_xl_rx2_old; + wire [8 : 0] plm_fsm_reg_xl_rx3_old; + wire [7 : 0] plm_fsm_reg_tx_link_num_14; + wire [23 : 23] plm_fsm_reg_state_141_0_0_1_iv_0_o2_0; + wire [23 : 23] plm_fsm_reg_state_141_0_0_1_iv_0_1; + wire [21 : 0] plm_fsm_dq_timer_reg_count_cry; + wire [22 : 0] plm_fsm_dq_timer_reg_count_s; + wire [22 : 0] plm_fsm_dq_timer_reg_count_qxu; + wire [22 : 0] plm_fsm_dq_timer_reg_count; + wire [21 : 0] plm_fsm_pa_timer_reg_count_cry; + wire [22 : 0] plm_fsm_pa_timer_reg_count_s; + wire [22 : 0] plm_fsm_pa_timer_reg_count_qxu; + wire [22 : 0] plm_fsm_pa_timer_reg_count; + wire [6 : 0] plm_fsm_pa_counter0_reg_rx_count_cry; + wire [10 : 0] plm_fsm_pa_counter0_reg_tx_count_cry; + wire [11 : 0] plm_fsm_pa_counter0_reg_tx_count_s; + wire [7 : 0] plm_fsm_pa_counter0_reg_rx_count_s; + wire [7 : 0] plm_fsm_pa_counter0_reg_rx_count_qxu; + wire [7 : 0] plm_fsm_pa_counter0_reg_rx_count; + wire [11 : 0] plm_fsm_pa_counter0_reg_tx_count_qxu; + wire [11 : 0] plm_fsm_pa_counter0_reg_tx_count; + wire [6 : 0] plm_fsm_pa_counter1_reg_rx_count_cry; + wire [10 : 0] plm_fsm_pa_counter1_reg_tx_count_cry; + wire [11 : 0] plm_fsm_pa_counter1_reg_tx_count_s; + wire [7 : 0] plm_fsm_pa_counter1_reg_rx_count_s; + wire [7 : 0] plm_fsm_pa_counter1_reg_rx_count_qxu; + wire [7 : 0] plm_fsm_pa_counter1_reg_rx_count; + wire [11 : 0] plm_fsm_pa_counter1_reg_tx_count_qxu; + wire [11 : 0] plm_fsm_pa_counter1_reg_tx_count; + wire [6 : 0] plm_fsm_pa_counter2_reg_rx_count_cry; + wire [10 : 0] plm_fsm_pa_counter2_reg_tx_count_cry; + wire [11 : 0] plm_fsm_pa_counter2_reg_tx_count_s; + wire [7 : 0] plm_fsm_pa_counter2_reg_rx_count_s; + wire [7 : 0] plm_fsm_pa_counter2_reg_rx_count_qxu; + wire [7 : 0] plm_fsm_pa_counter2_reg_rx_count; + wire [11 : 0] plm_fsm_pa_counter2_reg_tx_count_qxu; + wire [11 : 0] plm_fsm_pa_counter2_reg_tx_count; + wire [6 : 0] plm_fsm_pa_counter3_reg_rx_count_cry; + wire [10 : 0] plm_fsm_pa_counter3_reg_tx_count_cry; + wire [11 : 0] plm_fsm_pa_counter3_reg_tx_count_s; + wire [7 : 0] plm_fsm_pa_counter3_reg_rx_count_s; + wire [7 : 0] plm_fsm_pa_counter3_reg_rx_count_qxu; + wire [7 : 0] plm_fsm_pa_counter3_reg_rx_count; + wire [11 : 0] plm_fsm_pa_counter3_reg_tx_count_qxu; + wire [11 : 0] plm_fsm_pa_counter3_reg_tx_count; + wire [21 : 0] plm_fsm_pc_timer_reg_count_cry; + wire [22 : 0] plm_fsm_pc_timer_reg_count_s; + wire [22 : 0] plm_fsm_pc_timer_reg_count_qxu; + wire [22 : 0] plm_fsm_pc_timer_reg_count; + wire [6 : 0] plm_fsm_pc_counter0_reg_rx_count_cry; + wire [6 : 0] plm_fsm_pc_counter0_reg_tx_count_cry; + wire [7 : 0] plm_fsm_pc_counter0_reg_tx_count_s; + wire [7 : 0] plm_fsm_pc_counter0_reg_rx_count_s; + wire [7 : 0] plm_fsm_pc_counter0_reg_rx_count_qxu; + wire [7 : 0] plm_fsm_pc_counter0_reg_rx_count; + wire [7 : 0] plm_fsm_pc_counter0_reg_tx_count_qxu; + wire [7 : 0] plm_fsm_pc_counter0_reg_tx_count; + wire [6 : 0] plm_fsm_pc_counter1_reg_rx_count_cry; + wire [6 : 0] plm_fsm_pc_counter1_reg_tx_count_cry; + wire [7 : 0] plm_fsm_pc_counter1_reg_tx_count_s; + wire [7 : 0] plm_fsm_pc_counter1_reg_rx_count_s; + wire [7 : 0] plm_fsm_pc_counter1_reg_rx_count_qxu; + wire [7 : 0] plm_fsm_pc_counter1_reg_rx_count; + wire [7 : 0] plm_fsm_pc_counter1_reg_tx_count_qxu; + wire [7 : 0] plm_fsm_pc_counter1_reg_tx_count; + wire [6 : 0] plm_fsm_pc_counter2_reg_rx_count_cry; + wire [6 : 0] plm_fsm_pc_counter2_reg_tx_count_cry; + wire [7 : 0] plm_fsm_pc_counter2_reg_tx_count_s; + wire [7 : 0] plm_fsm_pc_counter2_reg_rx_count_s; + wire [7 : 0] plm_fsm_pc_counter2_reg_rx_count_qxu; + wire [7 : 0] plm_fsm_pc_counter2_reg_rx_count; + wire [7 : 0] plm_fsm_pc_counter2_reg_tx_count_qxu; + wire [7 : 0] plm_fsm_pc_counter2_reg_tx_count; + wire [6 : 0] plm_fsm_pc_counter3_reg_rx_count_cry; + wire [6 : 0] plm_fsm_pc_counter3_reg_tx_count_cry; + wire [7 : 0] plm_fsm_pc_counter3_reg_tx_count_s; + wire [7 : 0] plm_fsm_pc_counter3_reg_rx_count_s; + wire [7 : 0] plm_fsm_pc_counter3_reg_rx_count_qxu; + wire [7 : 0] plm_fsm_pc_counter3_reg_rx_count; + wire [7 : 0] plm_fsm_pc_counter3_reg_tx_count_qxu; + wire [7 : 0] plm_fsm_pc_counter3_reg_tx_count; + wire [21 : 0] plm_fsm_cls_timer_reg_count_cry; + wire [22 : 0] plm_fsm_cls_timer_reg_count_s; + wire [22 : 0] plm_fsm_cls_timer_reg_count_qxu; + wire [22 : 0] plm_fsm_cls_timer_reg_count; + wire [21 : 0] plm_fsm_cla_timer_reg_count_cry; + wire [22 : 0] plm_fsm_cla_timer_reg_count_s; + wire [22 : 0] plm_fsm_cla_timer_reg_count_qxu; + wire [22 : 0] plm_fsm_cla_timer_reg_count; + wire [21 : 0] plm_fsm_clw_timer_reg_count_cry; + wire [22 : 0] plm_fsm_clw_timer_reg_count_s; + wire [22 : 0] plm_fsm_clw_timer_reg_count_qxu; + wire [22 : 0] plm_fsm_clw_timer_reg_count; + wire [21 : 0] plm_fsm_cc_timer_reg_count_cry; + wire [22 : 0] plm_fsm_cc_timer_reg_count_s; + wire [22 : 0] plm_fsm_cc_timer_reg_count_qxu; + wire [22 : 0] plm_fsm_cc_timer_reg_count; + wire [6 : 0] plm_fsm_cc_counter0_reg_rx_count_cry; + wire [6 : 0] plm_fsm_cc_counter0_reg_tx_count_cry; + wire [7 : 0] plm_fsm_cc_counter0_reg_tx_count_s; + wire [7 : 0] plm_fsm_cc_counter0_reg_rx_count_s; + wire [7 : 0] plm_fsm_cc_counter0_reg_rx_count_qxu; + wire [7 : 0] plm_fsm_cc_counter0_reg_rx_count; + wire [7 : 0] plm_fsm_cc_counter0_reg_tx_count_qxu; + wire [7 : 0] plm_fsm_cc_counter0_reg_tx_count; + wire [6 : 0] plm_fsm_cc_counter1_reg_rx_count_cry; + wire [6 : 0] plm_fsm_cc_counter1_reg_tx_count_cry; + wire [7 : 0] plm_fsm_cc_counter1_reg_tx_count_s; + wire [7 : 0] plm_fsm_cc_counter1_reg_rx_count_s; + wire [7 : 0] plm_fsm_cc_counter1_reg_rx_count_qxu; + wire [7 : 0] plm_fsm_cc_counter1_reg_rx_count; + wire [7 : 0] plm_fsm_cc_counter1_reg_tx_count_qxu; + wire [7 : 0] plm_fsm_cc_counter1_reg_tx_count; + wire [6 : 0] plm_fsm_cc_counter2_reg_rx_count_cry; + wire [6 : 0] plm_fsm_cc_counter2_reg_tx_count_cry; + wire [7 : 0] plm_fsm_cc_counter2_reg_tx_count_s; + wire [7 : 0] plm_fsm_cc_counter2_reg_rx_count_s; + wire [7 : 0] plm_fsm_cc_counter2_reg_rx_count_qxu; + wire [7 : 0] plm_fsm_cc_counter2_reg_rx_count; + wire [7 : 0] plm_fsm_cc_counter2_reg_tx_count_qxu; + wire [7 : 0] plm_fsm_cc_counter2_reg_tx_count; + wire [6 : 0] plm_fsm_cc_counter3_reg_rx_count_cry; + wire [6 : 0] plm_fsm_cc_counter3_reg_tx_count_cry; + wire [7 : 0] plm_fsm_cc_counter3_reg_tx_count_s; + wire [7 : 0] plm_fsm_cc_counter3_reg_rx_count_s; + wire [7 : 0] plm_fsm_cc_counter3_reg_rx_count_qxu; + wire [7 : 0] plm_fsm_cc_counter3_reg_rx_count; + wire [7 : 0] plm_fsm_cc_counter3_reg_tx_count_qxu; + wire [7 : 0] plm_fsm_cc_counter3_reg_tx_count; + wire [21 : 0] plm_fsm_ci_timer_reg_count_cry; + wire [22 : 0] plm_fsm_ci_timer_reg_count_s; + wire [22 : 0] plm_fsm_ci_timer_reg_count_qxu; + wire [22 : 0] plm_fsm_ci_timer_reg_count; + wire [6 : 0] plm_fsm_ci_counter0_reg_rx_count_cry; + wire [6 : 0] plm_fsm_ci_counter0_reg_tx_count_cry; + wire [7 : 0] plm_fsm_ci_counter0_reg_tx_count_s; + wire [7 : 0] plm_fsm_ci_counter0_reg_rx_count_s; + wire [7 : 0] plm_fsm_ci_counter0_reg_rx_count_qxu; + wire [7 : 0] plm_fsm_ci_counter0_reg_rx_count; + wire [7 : 0] plm_fsm_ci_counter0_reg_tx_count_qxu; + wire [7 : 0] plm_fsm_ci_counter0_reg_tx_count; + wire [6 : 0] plm_fsm_ci_counter1_reg_rx_count_cry; + wire [6 : 0] plm_fsm_ci_counter1_reg_tx_count_cry; + wire [7 : 0] plm_fsm_ci_counter1_reg_tx_count_s; + wire [7 : 0] plm_fsm_ci_counter1_reg_rx_count_s; + wire [7 : 0] plm_fsm_ci_counter1_reg_rx_count_qxu; + wire [7 : 0] plm_fsm_ci_counter1_reg_rx_count; + wire [7 : 0] plm_fsm_ci_counter1_reg_tx_count_qxu; + wire [7 : 0] plm_fsm_ci_counter1_reg_tx_count; + wire [6 : 0] plm_fsm_ci_counter2_reg_rx_count_cry; + wire [6 : 0] plm_fsm_ci_counter2_reg_tx_count_cry; + wire [7 : 0] plm_fsm_ci_counter2_reg_tx_count_s; + wire [7 : 0] plm_fsm_ci_counter2_reg_rx_count_s; + wire [7 : 0] plm_fsm_ci_counter2_reg_rx_count_qxu; + wire [7 : 0] plm_fsm_ci_counter2_reg_rx_count; + wire [7 : 0] plm_fsm_ci_counter2_reg_tx_count_qxu; + wire [7 : 0] plm_fsm_ci_counter2_reg_tx_count; + wire [6 : 0] plm_fsm_ci_counter3_reg_rx_count_cry; + wire [6 : 0] plm_fsm_ci_counter3_reg_tx_count_cry; + wire [7 : 0] plm_fsm_ci_counter3_reg_tx_count_s; + wire [7 : 0] plm_fsm_ci_counter3_reg_rx_count_s; + wire [7 : 0] plm_fsm_ci_counter3_reg_rx_count_qxu; + wire [7 : 0] plm_fsm_ci_counter3_reg_rx_count; + wire [7 : 0] plm_fsm_ci_counter3_reg_tx_count_qxu; + wire [7 : 0] plm_fsm_ci_counter3_reg_tx_count; + wire [21 : 0] plm_fsm_rl_timer_reg_count_cry; + wire [22 : 0] plm_fsm_rl_timer_reg_count_s; + wire [22 : 0] plm_fsm_rl_timer_reg_count_qxu; + wire [22 : 0] plm_fsm_rl_timer_reg_count; + wire [6 : 0] plm_fsm_rl_counterx_reg_rx_count_cry; + wire [10 : 0] plm_fsm_rl_counterx_reg_tx_count_cry; + wire [11 : 0] plm_fsm_rl_counterx_reg_tx_count_s; + wire [7 : 0] plm_fsm_rl_counterx_reg_rx_count_s; + wire [7 : 0] plm_fsm_rl_counterx_reg_rx_count_qxu; + wire [7 : 0] plm_fsm_rl_counterx_reg_rx_count; + wire [11 : 0] plm_fsm_rl_counterx_reg_tx_count_qxu; + wire [11 : 0] plm_fsm_rl_counterx_reg_tx_count; + wire [6 : 0] plm_fsm_rl_counter0_reg_rx_count_cry; + wire [7 : 0] plm_fsm_rl_counter0_reg_rx_count_s; + wire [7 : 0] plm_fsm_rl_counter0_reg_rx_count_qxu; + wire [7 : 0] plm_fsm_rl_counter0_reg_rx_count; + wire [6 : 0] plm_fsm_rl_counter1_reg_rx_count_cry; + wire [7 : 0] plm_fsm_rl_counter1_reg_rx_count_s; + wire [7 : 0] plm_fsm_rl_counter1_reg_rx_count_qxu; + wire [7 : 0] plm_fsm_rl_counter1_reg_rx_count; + wire [6 : 0] plm_fsm_rl_counter2_reg_rx_count_cry; + wire [7 : 0] plm_fsm_rl_counter2_reg_rx_count_s; + wire [7 : 0] plm_fsm_rl_counter2_reg_rx_count_qxu; + wire [7 : 0] plm_fsm_rl_counter2_reg_rx_count; + wire [6 : 0] plm_fsm_rl_counter3_reg_rx_count_cry; + wire [7 : 0] plm_fsm_rl_counter3_reg_rx_count_s; + wire [7 : 0] plm_fsm_rl_counter3_reg_rx_count_qxu; + wire [7 : 0] plm_fsm_rl_counter3_reg_rx_count; + wire [21 : 0] plm_fsm_rc_timer_reg_count_cry; + wire [22 : 0] plm_fsm_rc_timer_reg_count_s; + wire [22 : 0] plm_fsm_rc_timer_reg_count_qxu; + wire [22 : 0] plm_fsm_rc_timer_reg_count; + wire [6 : 0] plm_fsm_rc_counter_ts1_0_reg_rx_count_cry; + wire [6 : 0] plm_fsm_rc_counter_ts1_0_reg_tx_count_cry; + wire [7 : 0] plm_fsm_rc_counter_ts1_0_reg_tx_count_s; + wire [7 : 0] plm_fsm_rc_counter_ts1_0_reg_rx_count_s; + wire [7 : 0] plm_fsm_rc_counter_ts1_0_reg_rx_count_qxu; + wire [7 : 0] plm_fsm_rc_counter_ts1_0_reg_rx_count; + wire [7 : 0] plm_fsm_rc_counter_ts1_0_reg_tx_count_qxu; + wire [7 : 0] plm_fsm_rc_counter_ts1_0_reg_tx_count; + wire [6 : 0] plm_fsm_rc_counter_ts1_1_reg_rx_count_cry; + wire [6 : 0] plm_fsm_rc_counter_ts1_1_reg_tx_count_cry; + wire [7 : 0] plm_fsm_rc_counter_ts1_1_reg_tx_count_s; + wire [7 : 0] plm_fsm_rc_counter_ts1_1_reg_rx_count_s; + wire [7 : 0] plm_fsm_rc_counter_ts1_1_reg_rx_count_qxu; + wire [7 : 0] plm_fsm_rc_counter_ts1_1_reg_rx_count; + wire [7 : 0] plm_fsm_rc_counter_ts1_1_reg_tx_count_qxu; + wire [7 : 0] plm_fsm_rc_counter_ts1_1_reg_tx_count; + wire [6 : 0] plm_fsm_rc_counter_ts1_2_reg_rx_count_cry; + wire [6 : 0] plm_fsm_rc_counter_ts1_2_reg_tx_count_cry; + wire [7 : 0] plm_fsm_rc_counter_ts1_2_reg_tx_count_s; + wire [7 : 0] plm_fsm_rc_counter_ts1_2_reg_rx_count_s; + wire [7 : 0] plm_fsm_rc_counter_ts1_2_reg_rx_count_qxu; + wire [7 : 0] plm_fsm_rc_counter_ts1_2_reg_rx_count; + wire [7 : 0] plm_fsm_rc_counter_ts1_2_reg_tx_count_qxu; + wire [7 : 0] plm_fsm_rc_counter_ts1_2_reg_tx_count; + wire [6 : 0] plm_fsm_rc_counter_ts1_3_reg_rx_count_cry; + wire [6 : 0] plm_fsm_rc_counter_ts1_3_reg_tx_count_cry; + wire [7 : 0] plm_fsm_rc_counter_ts1_3_reg_tx_count_s; + wire [7 : 0] plm_fsm_rc_counter_ts1_3_reg_rx_count_s; + wire [7 : 0] plm_fsm_rc_counter_ts1_3_reg_rx_count_qxu; + wire [7 : 0] plm_fsm_rc_counter_ts1_3_reg_rx_count; + wire [7 : 0] plm_fsm_rc_counter_ts1_3_reg_tx_count_qxu; + wire [7 : 0] plm_fsm_rc_counter_ts1_3_reg_tx_count; + wire [6 : 0] plm_fsm_rc_counter_ts2_0_reg_rx_count_cry; + wire [6 : 0] plm_fsm_rc_counter_ts2_0_reg_tx_count_cry; + wire [7 : 0] plm_fsm_rc_counter_ts2_0_reg_tx_count_s; + wire [7 : 0] plm_fsm_rc_counter_ts2_0_reg_rx_count_s; + wire [7 : 0] plm_fsm_rc_counter_ts2_0_reg_rx_count_qxu; + wire [7 : 0] plm_fsm_rc_counter_ts2_0_reg_rx_count; + wire [7 : 0] plm_fsm_rc_counter_ts2_0_reg_tx_count_qxu; + wire [7 : 0] plm_fsm_rc_counter_ts2_0_reg_tx_count; + wire [6 : 0] plm_fsm_rc_counter_ts2_1_reg_rx_count_cry; + wire [6 : 0] plm_fsm_rc_counter_ts2_1_reg_tx_count_cry; + wire [7 : 0] plm_fsm_rc_counter_ts2_1_reg_tx_count_s; + wire [7 : 0] plm_fsm_rc_counter_ts2_1_reg_rx_count_s; + wire [7 : 0] plm_fsm_rc_counter_ts2_1_reg_rx_count_qxu; + wire [7 : 0] plm_fsm_rc_counter_ts2_1_reg_rx_count; + wire [7 : 0] plm_fsm_rc_counter_ts2_1_reg_tx_count_qxu; + wire [7 : 0] plm_fsm_rc_counter_ts2_1_reg_tx_count; + wire [6 : 0] plm_fsm_rc_counter_ts2_2_reg_rx_count_cry; + wire [6 : 0] plm_fsm_rc_counter_ts2_2_reg_tx_count_cry; + wire [7 : 0] plm_fsm_rc_counter_ts2_2_reg_tx_count_s; + wire [7 : 0] plm_fsm_rc_counter_ts2_2_reg_rx_count_s; + wire [7 : 0] plm_fsm_rc_counter_ts2_2_reg_rx_count_qxu; + wire [7 : 0] plm_fsm_rc_counter_ts2_2_reg_rx_count; + wire [7 : 0] plm_fsm_rc_counter_ts2_2_reg_tx_count_qxu; + wire [7 : 0] plm_fsm_rc_counter_ts2_2_reg_tx_count; + wire [6 : 0] plm_fsm_rc_counter_ts2_3_reg_rx_count_cry; + wire [6 : 0] plm_fsm_rc_counter_ts2_3_reg_tx_count_cry; + wire [7 : 0] plm_fsm_rc_counter_ts2_3_reg_tx_count_s; + wire [7 : 0] plm_fsm_rc_counter_ts2_3_reg_rx_count_s; + wire [7 : 0] plm_fsm_rc_counter_ts2_3_reg_rx_count_qxu; + wire [7 : 0] plm_fsm_rc_counter_ts2_3_reg_rx_count; + wire [7 : 0] plm_fsm_rc_counter_ts2_3_reg_tx_count_qxu; + wire [7 : 0] plm_fsm_rc_counter_ts2_3_reg_tx_count; + wire [21 : 0] plm_fsm_ri_timer_reg_count_cry; + wire [22 : 0] plm_fsm_ri_timer_reg_count_s; + wire [22 : 0] plm_fsm_ri_timer_reg_count_qxu; + wire [22 : 0] plm_fsm_ri_timer_reg_count; + wire [6 : 0] plm_fsm_ri_counter0_reg_rx_count_cry; + wire [6 : 0] plm_fsm_ri_counter0_reg_tx_count_cry; + wire [7 : 0] plm_fsm_ri_counter0_reg_tx_count_s; + wire [7 : 0] plm_fsm_ri_counter0_reg_rx_count_s; + wire [7 : 0] plm_fsm_ri_counter0_reg_rx_count_qxu; + wire [7 : 0] plm_fsm_ri_counter0_reg_rx_count; + wire [7 : 0] plm_fsm_ri_counter0_reg_tx_count_qxu; + wire [7 : 0] plm_fsm_ri_counter0_reg_tx_count; + wire [6 : 0] plm_fsm_ri_counter1_reg_rx_count_cry; + wire [6 : 0] plm_fsm_ri_counter1_reg_tx_count_cry; + wire [7 : 0] plm_fsm_ri_counter1_reg_tx_count_s; + wire [7 : 0] plm_fsm_ri_counter1_reg_rx_count_s; + wire [7 : 0] plm_fsm_ri_counter1_reg_rx_count_qxu; + wire [7 : 0] plm_fsm_ri_counter1_reg_rx_count; + wire [7 : 0] plm_fsm_ri_counter1_reg_tx_count_qxu; + wire [7 : 0] plm_fsm_ri_counter1_reg_tx_count; + wire [6 : 0] plm_fsm_ri_counter2_reg_rx_count_cry; + wire [6 : 0] plm_fsm_ri_counter2_reg_tx_count_cry; + wire [7 : 0] plm_fsm_ri_counter2_reg_tx_count_s; + wire [7 : 0] plm_fsm_ri_counter2_reg_rx_count_s; + wire [7 : 0] plm_fsm_ri_counter2_reg_rx_count_qxu; + wire [7 : 0] plm_fsm_ri_counter2_reg_rx_count; + wire [7 : 0] plm_fsm_ri_counter2_reg_tx_count_qxu; + wire [7 : 0] plm_fsm_ri_counter2_reg_tx_count; + wire [6 : 0] plm_fsm_ri_counter3_reg_rx_count_cry; + wire [6 : 0] plm_fsm_ri_counter3_reg_tx_count_cry; + wire [7 : 0] plm_fsm_ri_counter3_reg_tx_count_s; + wire [7 : 0] plm_fsm_ri_counter3_reg_rx_count_s; + wire [7 : 0] plm_fsm_ri_counter3_reg_rx_count_qxu; + wire [7 : 0] plm_fsm_ri_counter3_reg_rx_count; + wire [7 : 0] plm_fsm_ri_counter3_reg_tx_count_qxu; + wire [7 : 0] plm_fsm_ri_counter3_reg_tx_count; + wire [21 : 0] plm_fsm_hr_timer_reg_count_cry; + wire [22 : 0] plm_fsm_hr_timer_reg_count_s; + wire [22 : 0] plm_fsm_hr_timer_reg_count_qxu; + wire [22 : 0] plm_fsm_hr_timer_reg_count; + wire [21 : 0] plm_fsm_xl_cls_timer_reg_count_cry; + wire [22 : 0] plm_fsm_xl_cls_timer_reg_count_s; + wire [22 : 0] plm_fsm_xl_cls_timer_reg_count_qxu; + wire [22 : 0] plm_fsm_xl_cls_timer_reg_count; + wire [21 : 0] plm_fsm_xl_cla_timer_reg_count_cry; + wire [22 : 0] plm_fsm_xl_cla_timer_reg_count_s; + wire [22 : 0] plm_fsm_xl_cla_timer_reg_count_qxu; + wire [22 : 0] plm_fsm_xl_cla_timer_reg_count; + wire [21 : 0] plm_fsm_xl_clw_timer_reg_count_cry; + wire [22 : 0] plm_fsm_xl_clw_timer_reg_count_s; + wire [22 : 0] plm_fsm_xl_clw_timer_reg_count_qxu; + wire [22 : 0] plm_fsm_xl_clw_timer_reg_count; + wire [2 : 0] com_state; + wire [47 : 0] com_cmmt_err_tlp_hdr; + wire [6 : 0] com_cmmt_rbar_hit; + wire [9 : 0] com_cmmt_rpm_set_slot_pwr_data; + wire [63 : 4] com_cmmt_raddr; + wire [17 : 17] com_st_pm_i; + wire [2 : 2] com_pm_type_q_4_i_0_0_0_a2; + wire [11 : 0] com_lnk_tfc_data; + wire [3 : 0] com_lnk_tfc_type; + wire [7 : 0] com_lnk_tfc_header; + wire [11 : 0] com_lnk_ttrans_seq; + wire [63 : 0] com_lnk_td; + wire [4 : 1] com_link_status; + wire [0 : 0] com_lnk_trem; + wire [63 : 8] com_lnk_rd_6113; + wire [0 : 0] com_lnk_rrem; + wire [11 : 0] com_lnk_rfc_data; + wire [2 : 0] com_lnk_rfc_type; + wire [0 : 0] com_lnk_rfc_vc_n; + wire [7 : 0] com_lnk_rfc_header; + wire [11 : 0] com_lnk_tupdate_seq; + wire [0 : 0] com_lnk_ttrans_seq_i; + wire [11 : 1] com_llm_reg_rx_dllp_tsn_m1; + wire [11 : 0] com_llm_reg_rx_dllp_tsn; + wire [31 : 29] com_llm_rx_dllp; + wire [0 : 0] com_llm_link_vc_rcv; + wire [11 : 0] com_llm_reg_next_rcv_tsn; + wire [0 : 0] com_llm_link_status; + wire [14 : 0] com_llm_reg_ack_to_val; + wire [11 : 0] com_llm_reg_tx_dllp_tsn; + wire [63 : 0] com_llm_llm_tx_top_tx_tlp_td; + wire [4 : 4] com_llm_llm_tx_top_rem_pipe; + wire [2 : 2] com_llm_llm_tx_top_arb_state; + wire [1 : 0] com_llm_llm_tx_top_llmx08_tx_tlp_komp_eof_n_pipe_6114; + wire [2 : 0] com_llm_llm_tx_top_llmx08_tx_tlp_komp_sof_n_pipe; + wire [51 : 40] com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_d_i_0_0; + wire [31 : 0] com_llm_llm_tx_top_llmx08_tx_tlp_komp_sw_early_crc; + wire [0 : 0] com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_d_2_o3; + wire [0 : 0] com_llm_llm_tx_top_llmx08_tx_tlp_komp_rem_pipe_6115; + wire [52 : 52] com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_d_i_o3; + wire [0 : 0] com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_5_tmp_d_array_0; + wire [0 : 0] com_llm_llm_tx_top_llmx08_tx_tlp_komp_rem_pipe_tmp_d_array_0; + wire [63 : 8] com_llm_llm_tx_top_llmx08_tx_tlp_komp_td_mux_i_m3_i_m3_0; + wire [7 : 0] com_llm_llm_tx_top_llmx08_tx_tlp_komp_td_mux_i_m3_i_m3_i_m3_0; + wire [31 : 0] com_llm_llm_tx_top_llmx08_tx_tlp_komp_d32_sw; + wire [47 : 32] com_llm_llm_tx_top_llmx08_tx_tlp_komp_d64_sw; + wire [15 : 0] com_llm_llm_tx_top_llmx08_tx_tlp_komp_d16_sw; + wire [63 : 0] com_llm_llm_tx_top_llmx08_tx_tlp_komp_bat_td; + wire [23 : 0] com_llm_llm_tx_top_llmx08_tx_tlp_komp_sw_early_crc_i; + wire [23 : 0] com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_crc; + wire [2 : 2] com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crcdatawidth_q; + wire [31 : 0] com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4; + wire [13 : 13] com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_new_c16_1_0; + wire [24 : 24] com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_new_c16_1_2; + wire [30 : 30] com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_new_c32_d48; + wire [2 : 2] com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crcdatawidth_qq; + wire [31 : 0] com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_new_c32_d64; + wire [23 : 23] com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_new_c32_d48_1; + wire [31 : 0] com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_d64_c; + wire [26 : 25] com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_7; + wire [30 : 30] com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c48_new_c48_1_0; + wire [22 : 22] com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c64_new_c64_1_4; + wire [25 : 25] com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c64_new_c64_1_3; + wire [14 : 0] com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_latency_timer_s; + wire [13 : 0] com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_latency_timer_cry; + wire [2 : 0] com_llm_llm_tx_top_llmx08_tx_dllp_jefe_pm_type_q; + wire [14 : 0] com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_latency_timer_qxu; + wire [14 : 0] com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_latency_timer; + wire [0 : 0] com_llm_llm_tx_top_llmx08_tx_dllp_jefe_llm32_fc_fifo_un1_wr_en_7_0_0_0_0_0; + wire [3 : 0] com_llm_llm_tx_top_llmx08_tx_dllp_jefe_llm32_fc_fifo_data_count; + wire [31 : 0] com_llm_llm_tx_top_llmx08_tx_packet_packer_prev_td; + wire [0 : 0] com_llm_llm_tx_top_llmx08_tx_packet_packer_next_arb_state_0_i_0_0_a2_0_0; + wire [9 : 9] com_llm_llm_tx_top_llmx08_tx_packet_packer_new_c32_1_i; + wire [2 : 2] com_llm_llm_tx_top_llmx08_tx_packet_packer_arb_state_i; + wire [23 : 8] com_llm_llm_tx_top_llmx08_tx_packet_packer_current_td; + wire [63 : 56] com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_i_0; + wire [55 : 32] com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_0_0; + wire [0 : 0] com_llm_llm_tx_top_llmx08_tx_packet_packer_next_arb_state_0_i_0_0_2; + wire [0 : 0] com_llm_llm_tx_top_llmx08_tx_packet_packer_next_arb_state_0_i_0_0_0; + wire [8 : 8] com_llm_llm_tx_top_llmx08_tx_packet_packer_current_td_0_i_m3_0_1; + wire [1 : 1] com_llm_llm_tx_top_llmx08_tx_packet_packer_next_arb_state_i_i_0_2; + wire [1 : 1] com_llm_llm_tx_top_llmx08_tx_packet_packer_next_arb_state_i_i_0_2_1; + wire [11 : 0] com_llm_llm_rx_top_rx_tlp_tsn; + wire [63 : 0] com_llm_llm_rx_top_rx_rd; + wire [2 : 2] com_llm_llm_rx_top_rx_rrem; + wire [28 : 24] com_llm_llm_rx_top_rx_dllp; + wire [63 : 0] com_llm_llm_rx_top_llm_rx_demux_phy_rd_q_0_; + wire [6 : 0] com_llm_llm_rx_top_llm_rx_dllp_crc_data_tmp; + wire [11 : 1] com_llm_llm_rx_top_llm_rx_dllp_crc_rx_dllp_d_i; + wire [11 : 1] com_llm_llm_rx_top_llm_rx_dllp_crc_RX_DLLP_LOW_M1_2; + wire [15 : 0] com_llm_llm_rx_top_llm_rx_dllp_crc_crc16_d32_nst; + wire [15 : 0] com_llm_llm_rx_top_llm_rx_dllp_crc_crc16_d32_st; + wire [28 : 28] com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q; + wire [15 : 0] com_llm_llm_rx_top_llm_rx_dllp_crc_crc16_ori_4_i_m3_0; + wire [15 : 0] com_llm_llm_rx_top_llm_rx_dllp_crc_crc16_ori; + wire [15 : 0] com_llm_llm_rx_top_llm_rx_dllp_crc_un1_crc16_ok_0; + wire [3 : 3] com_llm_llm_rx_top_llm_rx_dllp_crc_llm_rx_crc16_d32_st_new_c32_1_1_2; + wire [4 : 3] com_llm_llm_rx_top_llm_rx_dllp_crc_llm_rx_crc16_d32_st_new_c32_1_i_1; + wire [12 : 12] com_llm_llm_rx_top_llm_rx_dllp_crc_llm_rx_crc16_d32_st_new_c32_1_0; + wire [3 : 3] com_llm_llm_rx_top_llm_rx_dllp_crc_llm_rx_crc16_d32_nst_new_c32_1_1_2; + wire [4 : 3] com_llm_llm_rx_top_llm_rx_dllp_crc_llm_rx_crc16_d32_nst_new_c32_1_i_1; + wire [14 : 0] com_llm_llm_rx_top_llm_rx_tlp_crc_data_tmp_0; + wire [14 : 0] com_llm_llm_rx_top_llm_rx_tlp_crc_data_tmp; + wire [5 : 5] com_llm_llm_rx_top_llm_rx_tlp_crc_c64_0_a2_0_a2; + wire [63 : 0] com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m3_0; + wire [63 : 32] com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sh; + wire [63 : 0] com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl; + wire [11 : 0] com_llm_llm_rx_top_llm_rx_tlp_crc_rx_tlp_tsn_d; + wire [31 : 0] com_llm_llm_rx_top_llm_rx_tlp_crc_new_c64; + wire [31 : 0] com_llm_llm_rx_top_llm_rx_tlp_crc_new_c16; + wire [31 : 0] com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d16; + wire [11 : 6] com_llm_llm_rx_top_llm_rx_tlp_crc_rx_tlp_tsn_dd_5_i_m3_i_m3_0; + wire [11 : 0] com_llm_llm_rx_top_llm_rx_tlp_crc_rx_tlp_tsn_dd; + wire [5 : 0] com_llm_llm_rx_top_llm_rx_tlp_crc_rx_tlp_tsn_dd_5_i_m3_0; + wire [31 : 31] com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d16_new_c16_1_2; + wire [2 : 2] com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_3_1; + wire [2 : 2] com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_3; + wire [10 : 10] com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_1_2; + wire [1 : 1] com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_8; + wire [27 : 27] com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_7_1; + wire [6 : 6] com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_1_1; + wire [9 : 9] com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_10; + wire [4 : 0] com_llm_llm_rx_top_llm_rx_tlp_sm_data_tmp; + wire [11 : 11] com_llm_llm_rx_top_llm_rx_tlp_sm_tlp_diff_tsn; + wire [0 : 0] com_llm_llm_common_link_status_i; + wire [0 : 0] com_llm_llm_common_lat_d_i_i_m3_i_m4_i_m3_0; + wire [7 : 0] com_llm_llm_common_val_1; + wire [14 : 0] com_llm_llm_common_reg_replay_to_val_3; + wire [14 : 0] com_llm_llm_common_reg_replay_to_val; + wire [14 : 7] com_llm_llm_common_reg_ack_to_val_3; + wire [6 : 0] com_llm_llm_common_reg_ack_to_val_3_0_0; + wire [2 : 2] com_llm_llm_common_llm_link_sm_llm_link_main_sm_ns_link_i_0_0_0_i_1; + wire [4 : 0] com_llm_llm_common_llm_common_reg_data_tmp_2; + wire [4 : 0] com_llm_llm_common_llm_common_reg_data_tmp_1; + wire [4 : 0] com_llm_llm_common_llm_common_reg_data_tmp_0; + wire [4 : 0] com_llm_llm_common_llm_common_reg_data_tmp; + wire [11 : 11] com_llm_llm_common_llm_common_reg_result_i_0; + wire [11 : 11] com_llm_llm_common_llm_common_reg_result_i; + wire [11 : 11] com_llm_llm_common_llm_common_reg_ttrans_st_hiwater; + wire [11 : 11] com_llm_llm_common_llm_common_reg_tmp_result; + wire [11 : 0] com_llm_llm_common_llm_common_reg_reg_rx_dllp_tsn_q; + wire [11 : 1] com_llm_llm_common_llm_common_reg_reg_tx_next_tsn_4; + wire [11 : 0] com_llm_llm_common_llm_common_reg_reg_tx_next_tsn; + wire [11 : 0] com_llm_llm_common_llm_common_reg_reg_tx_curr_tsn; + wire [11 : 0] com_llm_llm_common_llm_common_reg_hi_water_mark; + wire [11 : 11] com_llm_llm_common_llm_common_reg_compare_1_result; + wire [11 : 11] com_llm_llm_common_llm_common_reg_compare_2_result; + wire [1 : 1] com_llm_llm_common_llm_common_reg_llm_ack_nak_buf_acknak_state_q_5; + wire [1 : 1] com_llm_llm_common_llm_common_reg_llm_ack_nak_buf_acknak_state_q; + wire [1 : 1] com_llm_llm_common_llm_common_reg_llm_ack_nak_fsm_cs_acknakfsm_5_1; + wire [0 : 0] com_llm_llm_common_llm_common_reg_llm_ack_nak_fsm_cs_acknakfsm_5_i_0_0_1; + wire [1 : 1] com_llm_llm_common_llm_common_reg_llm_ack_nak_fsm_cs_acknakfsm_5; + wire [0 : 0] com_llm_llm_common_llm_common_reg_llm_ack_nak_fsm_acknak_state; + wire [4 : 0] com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_data_tmp_1; + wire [4 : 0] com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_data_tmp_0; + wire [6 : 0] com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_data_tmp; + wire [14 : 0] com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_s; + wire [13 : 1] com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_cry; + wire [1 : 0] com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_num_6116; + wire [0 : 0] com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_num_7_iv_0_m2_0; + wire [14 : 0] com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer; + wire [14 : 0] com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_qxu; + wire [14 : 0] com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_q; + wire [11 : 0] com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_reg_tx_ackd_tsn_q; + wire [10 : 0] com_llm_llm_common_llm_common_reg_llm_next_rcv_tsn_out_cry; + wire [11 : 0] com_llm_llm_common_llm_common_reg_llm_next_rcv_tsn_out_s; + wire [11 : 0] com_llm_llm_common_llm_common_reg_llm_next_rcv_tsn_out_qxu; + wire [0 : 0] com_tlm_u_tlm_tx_queue_state; + wire [11 : 0] com_tlm_u_tlm_tx_am_retry_tsn; + wire [3 : 0] com_tlm_u_tlm_tx_freed_buf; + wire [63 : 0] com_tlm_u_tlm_tx_vc0_d; + wire [3 : 0] com_tlm_u_tlm_tx_ds_buf_num; + wire [3 : 0] com_tlm_u_tlm_tx_vc0_buf_num; + wire [11 : 0] com_tlm_u_tlm_tx_vc0_retry_tsn; + wire [11 : 0] com_tlm_u_tlm_tx_data_src_tsn_cnt_s; + wire [10 : 0] com_tlm_u_tlm_tx_data_src_tsn_cnt_cry; + wire [11 : 0] com_tlm_u_tlm_tx_data_src_lnk_ttrans_seq_o_4_i_m2_i_m3_i_m3_0; + wire [11 : 0] com_tlm_u_tlm_tx_data_src_tsn_cnt_qxu; + wire [11 : 0] com_tlm_u_tlm_tx_data_src_tsn_cnt; + wire [4 : 0] com_tlm_u_tlm_tx_ack_mgr_data_tmp_0; + wire [4 : 0] com_tlm_u_tlm_tx_ack_mgr_data_tmp; + wire [11 : 0] com_tlm_u_tlm_tx_ack_mgr_newest_freed_tsn_s; + wire [10 : 1] com_tlm_u_tlm_tx_ack_mgr_newest_freed_tsn_cry; + wire [8 : 8] com_tlm_u_tlm_tx_ack_mgr_mgr_state_4_0_0; + wire [11 : 0] com_tlm_u_tlm_tx_ack_mgr_lnk_rupdate_seq_q; + wire [11 : 0] com_tlm_u_tlm_tx_ack_mgr_newest_freed_tsn_qxu; + wire [11 : 0] com_tlm_u_tlm_tx_ack_mgr_newest_freed_tsn; + wire [11 : 0] com_tlm_u_tlm_tx_ack_mgr_latest_ack_tsn; + wire [11 : 0] com_tlm_u_tlm_tx_ack_mgr_fifo_tsn; + wire [3 : 0] com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_shift_tap; + wire [3 : 0] com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_bkp_data; + wire [3 : 0] com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_raddr_lo; + wire [3 : 0] com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_raddr_lo_5_i_m2_i_m3_0; + wire [3 : 0] com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_bkp_raddr_lo; + wire [3 : 0] com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_d_o_4_i_m2_i_m3_0; + wire [1 : 0] com_tlm_u_tlm_tx_vc0_cat; + wire [5 : 0] com_tlm_u_tlm_tx_vc0_credits; + wire [63 : 0] com_tlm_u_tlm_tx_vc0_trn_d; + wire [3 : 0] com_tlm_u_tlm_tx_vc0_tkn_buf_num; + wire [3 : 0] com_tlm_u_tlm_tx_vc0_start_buf_num; + wire [11 : 0] com_tlm_u_tlm_tx_vc0_start_retry_tsn; + wire [6 : 0] com_tlm_u_tlm_tx_vc0_buf_pool_raddr_l_s; + wire [5 : 1] com_tlm_u_tlm_tx_vc0_buf_pool_raddr_l_cry; + wire [1 : 0] com_tlm_u_tlm_tx_vc0_buf_pool_wdata_vld; + wire [1 : 0] com_tlm_u_tlm_tx_vc0_buf_pool_rvld; + wire [68 : 68] com_tlm_u_tlm_tx_vc0_buf_pool_rdata_q_i_0_i_a2; + wire [0 : 0] com_tlm_u_tlm_tx_vc0_buf_pool_rvld_3; + wire [1 : 1] com_tlm_u_tlm_tx_vc0_buf_pool_rvld_10; + wire [1 : 0] com_tlm_u_tlm_tx_vc0_buf_pool_rvld_q; + wire [3 : 0] com_tlm_u_tlm_tx_vc0_buf_pool_raddr_h_0_0; + wire [6 : 0] com_tlm_u_tlm_tx_vc0_buf_pool_waddr_l_1; + wire [6 : 0] com_tlm_u_tlm_tx_vc0_buf_pool_waddr_l; + wire [3 : 0] com_tlm_u_tlm_tx_vc0_buf_pool_waddr_h; + wire [3 : 0] com_tlm_u_tlm_tx_vc0_buf_pool_raddr_h; + wire [3 : 0] com_tlm_u_tlm_tx_vc0_buf_pool_raddr_h_q; + wire [6 : 0] com_tlm_u_tlm_tx_vc0_buf_pool_raddr_l; + wire [6 : 0] com_tlm_u_tlm_tx_vc0_buf_pool_raddr_l_qxu; + wire [3 : 0] com_tlm_u_tlm_tx_vc0_buf_pool_srl_retry_retry_fifo_raddr_lo; + wire [12 : 0] com_tlm_u_tlm_tx_vc0_buf_pool_srl_retry_retry_fifo_shift_tap; + wire [6 : 0] com_tlm_u_tlm_tx_vc0_trn_len_counter_s; + wire [5 : 0] com_tlm_u_tlm_tx_vc0_trn_len_counter_cry; + wire [32 : 32] com_tlm_u_tlm_tx_vc0_trn_d_o_4_i_i_0; + wire [62 : 62] com_tlm_u_tlm_tx_vc0_trn_usr_d_i; + wire [1 : 0] com_tlm_u_tlm_tx_vc0_trn_pkts_in_trn; + wire [0 : 0] com_tlm_u_tlm_tx_vc0_trn_un1_buf_av_one_1_i_0_a2; + wire [63 : 0] com_tlm_u_tlm_tx_vc0_trn_usr_d; + wire [6 : 0] com_tlm_u_tlm_tx_vc0_trn_len_counter_qxu; + wire [6 : 0] com_tlm_u_tlm_tx_vc0_trn_len_counter; + wire [0 : 0] com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_usr_cat20_0_a2_0_a2_1; + wire [5 : 0] com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_usr_credits_6; + wire [5 : 0] com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_usr_credits; + wire [1 : 0] com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_cat_o_2; + wire [1 : 1] com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_cfg_cat; + wire [5 : 1] com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_credits_o_2; + wire [0 : 0] com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_credits_o_2_i_m2_i_m3_i_m3_0; + wire [0 : 0] com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_usr_cat20; + wire [1 : 0] com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_usr_cat; + wire [3 : 0] com_tlm_u_tlm_tx_vc0_token_fifo_fifo_d; + wire [3 : 3] com_tlm_u_tlm_tx_vc0_token_fifo_fifo_d_6_i_o2_i_m3_0; + wire [2 : 0] com_tlm_u_tlm_tx_vc0_token_fifo_fifo_d_6_i_m2_i_m3_0; + wire [3 : 0] com_tlm_u_tlm_tx_vc0_token_fifo_token_index; + wire [3 : 0] com_tlm_u_tlm_tx_vc0_token_fifo_t_fifo_raddr_lo; + wire [3 : 0] com_tlm_u_tlm_tx_vc0_token_fifo_t_fifo_shift_tap; + wire [10 : 0] com_tlm_u_tlm_tx_vc0_frm_seq_bq_q; + wire [10 : 0] com_tlm_u_tlm_tx_vc0_frm_seq_bq_d; + wire [10 : 6] com_tlm_u_tlm_tx_vc0_frm_seq_npd_av_i; + wire [10 : 6] com_tlm_u_tlm_tx_vc0_frm_seq_cpld_av_i; + wire [10 : 6] com_tlm_u_tlm_tx_vc0_frm_seq_pd_av_i; + wire [3 : 0] com_tlm_u_tlm_tx_vc0_frm_seq_last_buf_num; + wire [11 : 11] com_tlm_u_tlm_tx_vc0_frm_seq_pd_diff; + wire [1 : 0] com_tlm_u_tlm_tx_vc0_frm_seq_oq_cat_qq; + wire [11 : 11] com_tlm_u_tlm_tx_vc0_frm_seq_npd_diff; + wire [11 : 11] com_tlm_u_tlm_tx_vc0_frm_seq_bnpd_diff; + wire [2 : 0] com_tlm_u_tlm_tx_vc0_frm_seq_sq_cnt; + wire [11 : 11] com_tlm_u_tlm_tx_vc0_frm_seq_cpld_diff; + wire [3 : 0] com_tlm_u_tlm_tx_vc0_frm_seq_sq_q; + wire [11 : 0] com_tlm_u_tlm_tx_vc0_frm_seq_npd_av; + wire [1 : 0] com_tlm_u_tlm_tx_vc0_frm_seq_seq_state; + wire [3 : 1] com_tlm_u_tlm_tx_vc0_frm_seq_queue_state; + wire [12 : 11] com_tlm_u_tlm_tx_vc0_frm_seq_oq_q; + wire [5 : 0] com_tlm_u_tlm_tx_vc0_frm_seq_consumed_credits_4_i_m3_i_m3_i_m3_i_m3_0; + wire [5 : 0] com_tlm_u_tlm_tx_vc0_frm_seq_consumed_credits; + wire [3 : 0] com_tlm_u_tlm_tx_vc0_frm_seq_sq_d_4_i_m3_i_m3_i_m3_i_m3_0; + wire [3 : 0] com_tlm_u_tlm_tx_vc0_frm_seq_sq_d; + wire [3 : 0] com_tlm_u_tlm_tx_vc0_frm_seq_start_buf_o_2_i_m2_i_m3_i_m3_0; + wire [3 : 0] com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_raddr_lo; + wire [12 : 0] com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_shift_tap; + wire [12 : 0] com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_d_o_36_0_i_m2_i_m3_i_m3_0; + wire [3 : 0] com_tlm_u_tlm_tx_vc0_frm_seq_bq_fifo_raddr_lo; + wire [10 : 0] com_tlm_u_tlm_tx_vc0_frm_seq_bq_fifo_shift_tap; + wire [3 : 0] com_tlm_u_tlm_tx_vc0_frm_seq_sq_fifo_raddr_lo; + wire [3 : 0] com_tlm_u_tlm_tx_vc0_frm_seq_sq_fifo_shift_tap; + wire [1 : 1] com_tlm_u_tlm_tx_vc0_frm_seq_sq_fifo_un1_ct_o217_0_a2_0_a2_0_a2_0_a2; + wire [3 : 0] com_tlm_u_tlm_tx_vc0_frm_seq_sq_fifo_d_o_46_0_i_m2_i_m3_i_m3_i_m3_0; + wire [7 : 0] com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_PH_s; + wire [6 : 1] com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_PH_cry; + wire [7 : 0] com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_NPH_s; + wire [6 : 1] com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_NPH_cry; + wire [7 : 0] com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_CPLH_s; + wire [6 : 1] com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_CPLH_cry; + wire [11 : 0] com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_cpld_av_o_6; + wire [11 : 0] com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_npd_av_o_6; + wire [11 : 0] com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_pd_av_o_6; + wire [7 : 0] com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_limit_PH; + wire [7 : 0] com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_limit_NPH; + wire [11 : 0] com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_prev_limit_data_q_5_0_0; + wire [7 : 0] com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_limit_CPLH; + wire [7 : 0] com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_prev_limit_header_q_5_0_0; + wire [2 : 0] com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_credits_ok; + wire [11 : 0] com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_av_data_cred_7_i_0_0; + wire [0 : 0] com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_credits_ok_3; + wire [11 : 0] com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_limit_CPLD; + wire [11 : 0] com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_limit_NPD; + wire [11 : 0] com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_limit_PD; + wire [4 : 3] com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_min_data_cred_7; + wire [1 : 0] com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_suspend_cat; + wire [11 : 11] com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_fc_diff_data; + wire [11 : 11] com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_fc_diff_data_q; + wire [7 : 7] com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_fc_diff_header; + wire [7 : 7] com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_fc_diff_header_q; + wire [11 : 0] com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_prev_limit_data_q_5; + wire [7 : 0] com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_prev_limit_header_q_5; + wire [11 : 0] com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_prev_limit_data_q; + wire [1 : 0] com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_cat_q; + wire [7 : 0] com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_prev_limit_header_q; + wire [11 : 0] com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_data_qq; + wire [7 : 0] com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_header_q; + wire [7 : 0] com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_header_qq; + wire [11 : 0] com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_data_q; + wire [10 : 0] com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_CPLD_i; + wire [11 : 0] com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_CPLD; + wire [10 : 0] com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_NPD_i; + wire [11 : 0] com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_NPD; + wire [10 : 0] com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_PD_i; + wire [11 : 0] com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_PD; + wire [7 : 0] com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_PH; + wire [7 : 0] com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_NPH; + wire [7 : 0] com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_CPLH; + wire [7 : 0] com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_CPLH_qxu; + wire [7 : 0] com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_NPH_qxu; + wire [7 : 0] com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_PH_qxu; + wire [10 : 6] com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_pd_av; + wire [10 : 6] com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_cpld_av; + wire [11 : 0] com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_av_data_cred; + wire [5 : 3] com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_min_data_cred; + wire [4 : 0] com_tlm_u_tlm_tx_pm_ctrl_cfg_ct; + wire [63 : 0] com_tlm_u_tlm_rx_ds_d; + wire [6 : 0] com_tlm_u_tlm_rx_ds_bar; + wire [11 : 0] com_tlm_u_tlm_rx_fc_req_npd; + wire [7 : 0] com_tlm_u_tlm_rx_fc_req_nph; + wire [5 : 0] com_tlm_u_tlm_rx_fc_use_data; + wire [11 : 0] com_tlm_u_tlm_rx_fc_req_pd; + wire [7 : 0] com_tlm_u_tlm_rx_fc_req_ph; + wire [0 : 0] com_tlm_u_tlm_rx_vc0_rd_mon_word_ct_8_iv_i_0_0_1; + wire [0 : 0] com_tlm_u_tlm_rx_vc0_rd_mon_word_ct; + wire [6 : 0] com_tlm_u_tlm_rx_vc0_fifo_aux_q; + wire [6 : 0] com_tlm_u_tlm_rx_vc0_fifo_aux; + wire [67 : 64] com_tlm_u_tlm_rx_vc0_fifo_ram_dout; + wire [6 : 0] com_tlm_u_tlm_rx_vc0_fifo_aux_oqr; + wire [0 : 0] com_tlm_u_tlm_rx_vc0_fifo_un1_data_oqr; + wire [8 : 0] com_tlm_u_tlm_rx_vc0_fifo_aux_in; + wire [8 : 0] com_tlm_u_tlm_rx_vc0_fifo_aux_i_d; + wire [6 : 0] com_tlm_u_tlm_rx_vc0_fifo_trn_rbar_hit; + wire [9 : 0] com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_raddr_s; + wire [8 : 1] com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_raddr_cry; + wire [9 : 0] com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr_s; + wire [8 : 0] com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr_cry; + wire [9 : 0] com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_vld_ct; + wire [6 : 0] com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un10_vld_ct; + wire [9 : 0] com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr_qxu; + wire [9 : 0] com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr; + wire [6 : 0] com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_pkt_ct; + wire [6 : 0] com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_pkt_ct_m1; + wire [0 : 0] com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un8_pkt_ct_m1_i; + wire [9 : 0] com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr_p1; + wire [9 : 0] com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr_bkp; + wire [9 : 0] com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_raddr; + wire [9 : 0] com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_raddr_qxu; + wire [0 : 0] com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un8_pkt_ct; + wire [44 : 9] com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_shift_in; + wire [44 : 0] com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_shift_tap; + wire [8 : 0] com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_d_o_d_1; + wire [8 : 0] com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_d_o_d_0; + wire [8 : 0] com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_d_o_56; + wire [4 : 0] com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_hi_62; + wire [4 : 0] com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_hi; + wire [3 : 0] com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_lo; + wire [1 : 1] com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_un1_raddr_en_1; + wire [7 : 7] com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux; + wire [7 : 7] com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_q; + wire [3 : 0] com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo; + wire [0 : 0] com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_un615_d_o_d; + wire [0 : 0] com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_un599_d_o_d; + wire [0 : 0] com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_un591_d_o_d; + wire [1 : 0] com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_hi_71; + wire [1 : 0] com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_hi; + wire [3 : 0] com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1; + wire [3 : 0] com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_queue_aux_queue_raddr_lo; + wire [7 : 0] com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_queue_aux_queue_shift_tap_m; + wire [7 : 0] com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_queue_aux_queue_shift_tap; + wire [9 : 0] com_tlm_u_tlm_rx_vc0_flow_ctrl_lat_timer_s; + wire [8 : 0] com_tlm_u_tlm_rx_vc0_flow_ctrl_lat_timer_cry; + wire [7 : 7] com_tlm_u_tlm_rx_vc0_flow_ctrl_fc_h_advert_0; + wire [11 : 11] com_tlm_u_tlm_rx_vc0_flow_ctrl_fc_d_advert_0; + wire [7 : 7] com_tlm_u_tlm_rx_vc0_flow_ctrl_fc_h_advert; + wire [11 : 11] com_tlm_u_tlm_rx_vc0_flow_ctrl_fc_d_advert; + wire [9 : 0] com_tlm_u_tlm_rx_vc0_flow_ctrl_lat_timer_qxu; + wire [9 : 0] com_tlm_u_tlm_rx_vc0_flow_ctrl_lat_timer; + wire [3 : 0] com_tlm_u_tlm_rx_vc0_flow_ctrl_lat_prescale; + wire [0 : 0] com_tlm_u_tlm_rx_vc0_flow_ctrl_lat_prescale_i; + wire [7 : 0] com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_h_o_0; + wire [11 : 0] com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_d_o_0; + wire [7 : 0] com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_h_con_s; + wire [6 : 1] com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_h_con_cry; + wire [11 : 0] com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_d_alo; + wire [7 : 0] com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_h_alo; + wire [11 : 0] com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_d_con; + wire [11 : 11] com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_d_advert_1; + wire [7 : 7] com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_h_advert_1; + wire [7 : 0] com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_h_con_qxu; + wire [7 : 0] com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_h_con; + wire [7 : 0] com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_h_o_0; + wire [11 : 0] com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_d_o_0; + wire [7 : 0] com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_h_con_s; + wire [6 : 1] com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_h_con_cry; + wire [11 : 0] com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_d_alo; + wire [7 : 0] com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_h_alo; + wire [11 : 0] com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_d_con; + wire [7 : 0] com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_h_con_qxu; + wire [7 : 0] com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_h_con; + wire [7 : 0] com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_h_con_s; + wire [6 : 1] com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_h_con_cry; + wire [0 : 0] com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_free_h; + wire [0 : 0] com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_free_d; + wire [11 : 0] com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_d_con; + wire [5 : 5] com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_h_o; + wire [7 : 0] com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_req_h_o; + wire [11 : 0] com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_req_d_o; + wire [7 : 0] com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_h_con; + wire [7 : 0] com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_h_con_qxu; + wire [6 : 6] com_tlm_u_tlm_rx_data_snk_cur_fulltype; + wire [2 : 0] com_tlm_u_tlm_rx_data_snk_cur_byte_ct_1dw; + wire [1 : 1] com_tlm_u_tlm_rx_data_snk_sof_q_3; + wire [1 : 1] com_tlm_u_tlm_rx_data_snk_dsc_q_3; + wire [1 : 1] com_tlm_u_tlm_rx_data_snk_eof_nd_q_3; + wire [1 : 0] com_tlm_u_tlm_rx_data_snk_cur_first_be_adj; + wire [0 : 0] com_tlm_u_tlm_rx_data_snk_first_be_missing_0_0_0; + wire [2 : 1] com_tlm_u_tlm_rx_data_snk_cur_bytes_missing_1; + wire [1 : 0] com_tlm_u_tlm_rx_data_snk_cur_attr; + wire [2 : 0] com_tlm_u_tlm_rx_data_snk_cur_tc; + wire [7 : 0] com_tlm_u_tlm_rx_data_snk_cur_tag; + wire [7 : 0] com_tlm_u_tlm_rx_data_snk_cur_msgcode; + wire [15 : 0] com_tlm_u_tlm_rx_data_snk_cur_req_id; + wire [5 : 0] com_tlm_u_tlm_rx_data_snk_cur_data_credits; + wire [11 : 0] com_tlm_u_tlm_rx_data_snk_cur_byte_ct; + wire [28 : 0] com_tlm_u_tlm_rx_data_snk_cur_cpl_header_fmt; + wire [1 : 0] com_tlm_u_tlm_rx_data_snk_cur_lower_addr_22; + wire [6 : 0] com_tlm_u_tlm_rx_data_snk_cur_lower_addr; + wire [6 : 2] com_tlm_u_tlm_rx_data_snk_lower_addr64_in_q; + wire [6 : 2] com_tlm_u_tlm_rx_data_snk_lower_addr32_in_q; + wire [7 : 5] com_tlm_u_tlm_rx_data_snk_cur_length; + wire [2 : 0] com_tlm_u_tlm_rx_data_snk_cur_bytes_missing; + wire [6 : 0] com_tlm_u_tlm_rx_data_snk_malformed_checks_word_ct_d_i; + wire [6 : 0] com_tlm_u_tlm_rx_data_snk_malformed_checks_word_ct; + wire [5 : 0] com_tlm_u_tlm_rx_data_snk_malformed_checks_un11_data_credits_o_1_a2_0_a2_0_a2_0_a2; + wire [4 : 1] com_tlm_u_tlm_rx_data_snk_malformed_checks_cur_fulltype; + wire [2 : 0] com_tlm_u_tlm_rx_data_snk_malformed_checks_msgcode_routing; + wire [7 : 5] com_tlm_u_tlm_rx_data_snk_malformed_checks_max_length; + wire [63 : 63] com_tlm_u_tlm_rx_data_snk_bar_hit_check_raddr_d_i_0_0_o3; + wire [47 : 6] com_tlm_u_tlm_rx_data_snk_bar_hit_un18_check_raddr_d_0_a2_0_a2_0_a2_0_a2; + wire [5 : 4] com_tlm_u_tlm_rx_data_snk_bar_hit_un18_check_raddr_d_0_a2_0_a2_0_a2; + wire [6 : 0] com_tlm_u_tlm_rx_fc_src_initFC_st; + wire [11 : 0] com_tlm_u_tlm_rx_fc_src_pd; + wire [7 : 0] com_tlm_u_tlm_rx_fc_src_ph; + wire [11 : 0] com_tlm_u_tlm_rx_fc_src_npd; + wire [7 : 0] com_tlm_u_tlm_rx_fc_src_nph; + wire [0 : 0] com_tlm_u_tlm_rx_fc_src_initFC_st_i; + wire [3 : 0] com_cmm_req_arbiter; + wire [26 : 26] com_cmm_st_pm; + wire [49 : 0] com_cmm_data_errmanager; + wire [2 : 0] com_cmm_req_errman; + wire [31 : 0] com_cmm_bar5_reg; + wire [31 : 0] com_cmm_bar4_reg; + wire [31 : 0] com_cmm_bar3_reg; + wire [31 : 0] com_cmm_bar2_reg; + wire [31 : 0] com_cmm_bar1_reg; + wire [1 : 0] com_cmm_pme_pmcsr; + wire [31 : 0] com_cmm_cfg_rd_data; + wire [31 : 0] com_cmm_cfg2tlm_rddata; + wire [1 : 1] com_cmm_state_0; + wire [6 : 6] com_cmm_state; + wire [15 : 0] com_cmm_msi_data; + wire [27 : 24] com_cmm_cfg_wr_data; + wire [9 : 0] com_cmm_cfg_addr; + wire [1 : 0] com_cmm_attr; + wire [3 : 0] com_cmm_cfg_be; + wire [15 : 0] com_cmm_req_id; + wire [7 : 0] com_cmm_tag; + wire [31 : 0] com_cmm_msi_haddr; + wire [31 : 2] com_cmm_msi_laddr; + wire [0 : 0] com_cmm_msi_control_1; + wire [1 : 0] com_cmm_intr_req_type; + wire [3 : 2] com_cmm_u_cmm_intr_next_state_0_i_a2_0_0; + wire [0 : 0] com_cmm_u_cmm_intr_next_state_i_m3_i_o2; + wire [0 : 0] com_cmm_u_cmm_intr_state_i; + wire [3 : 0] com_cmm_u_cmm_intr_state; + wire [0 : 0] com_cmm_u_cmm_intr_next_state_i_m3_i_m2; + wire [2 : 0] com_cmm_u_rx_pkt_proc_state; + wire [31 : 0] com_cmm_u_rx_pkt_proc_nxt_cfg_wr_data; + wire [0 : 0] com_cmm_u_tx_pkt_proc_next_state_0_i_0_a2_0_1; + wire [2 : 2] com_cmm_u_tx_pkt_proc_next_state_0_i_0_0; + wire [4 : 4] com_cmm_u_tx_pkt_proc_state; + wire [2 : 2] com_cmm_u_cfg_ctrl_next_state_0_i_0_0_o3; + wire [0 : 0] com_cmm_u_cfg_ctrl_state; + wire [12 : 0] com_cmm_u_cmm_decoder_data_tmp_14; + wire [9 : 1] com_cmm_u_cmm_decoder_data_tmp_15; + wire [14 : 0] com_cmm_u_cmm_decoder_data_tmp_3; + wire [12 : 0] com_cmm_u_cmm_decoder_data_tmp_13; + wire [14 : 0] com_cmm_u_cmm_decoder_data_tmp_2; + wire [12 : 0] com_cmm_u_cmm_decoder_data_tmp_12; + wire [14 : 0] com_cmm_u_cmm_decoder_data_tmp_1; + wire [12 : 0] com_cmm_u_cmm_decoder_data_tmp_11; + wire [14 : 0] com_cmm_u_cmm_decoder_data_tmp_0; + wire [12 : 0] com_cmm_u_cmm_decoder_data_tmp_10; + wire [14 : 0] com_cmm_u_cmm_decoder_data_tmp; + wire [12 : 0] com_cmm_u_cmm_decoder_data_tmp_9; + wire [12 : 0] com_cmm_u_cmm_decoder_data_tmp_8; + wire [12 : 0] com_cmm_u_cmm_decoder_data_tmp_7; + wire [12 : 0] com_cmm_u_cmm_decoder_data_tmp_6; + wire [12 : 0] com_cmm_u_cmm_decoder_data_tmp_5; + wire [12 : 0] com_cmm_u_cmm_decoder_data_tmp_4; + wire [4 : 4] com_cmm_u_cmm_decoder_bar_hit_7_0_a2_0; + wire [3 : 3] com_cmm_u_cmm_decoder_bar_hit_6_0_a2_0; + wire [2 : 2] com_cmm_u_cmm_decoder_bar_hit_5_0_a2_0; + wire [1 : 1] com_cmm_u_cmm_decoder_bar_hit_4_0_a2_0; + wire [31 : 0] com_cmm_u_cmm_cfgspace_low_addr_02_q; + wire [31 : 0] com_cmm_u_cmm_cfgspace_low_addr_00_q; + wire [31 : 0] com_cmm_u_cmm_cfgspace_low_addr_03_q; + wire [31 : 0] com_cmm_u_cmm_cfgspace_low_addr_01_q; + wire [31 : 0] com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_bm; + wire [31 : 0] com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_am; + wire [1 : 0] com_cmm_u_cmm_cfgspace_data_scale_5_i_m4_i_m3_0_bm; + wire [1 : 0] com_cmm_u_cmm_cfgspace_data_scale_5_i_m4_i_m3_0_am; + wire [7 : 0] com_cmm_u_cmm_cfgspace_pme_data_5_i_m4_i_m3_0_bm; + wire [7 : 0] com_cmm_u_cmm_cfgspace_pme_data_5_i_m4_i_m3_0_am; + wire [1 : 0] com_cmm_u_cmm_cfgspace_data_scale_4_i_m4_i_m4_i_m3_0_bm; + wire [1 : 0] com_cmm_u_cmm_cfgspace_data_scale_4_i_m4_i_m4_i_m3_0_am; + wire [7 : 0] com_cmm_u_cmm_cfgspace_pme_data_4_i_m4_i_m4_i_m3_0_bm; + wire [7 : 0] com_cmm_u_cmm_cfgspace_pme_data_4_i_m4_i_m4_i_m3_0_am; + wire [1 : 0] com_cmm_u_cmm_cfgspace_sel_xencode; + wire [31 : 0] com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_bm; + wire [31 : 0] com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_am; + wire [12 : 11] com_cmm_u_cmm_cfgspace_low_addr_00_0_0_0_0_0; + wire [29 : 29] com_cmm_u_cmm_cfgspace_low_addr_00_i_i_0_0_1; + wire [0 : 0] com_cmm_u_cmm_cfgspace_pme_pmcsr_21_i_0_0_0_o3; + wire [14 : 14] com_cmm_u_cmm_cfgspace_pme_pmcsr_21_1; + wire [2 : 0] com_cmm_u_cmm_cfgspace_bar1_reg_8_1_0_0_0_0; + wire [3 : 3] com_cmm_u_cmm_cfgspace_bar1_reg_8_1_0_0_0; + wire [3 : 0] com_cmm_u_cmm_cfgspace_bar2_reg_8_1_0_0_0_0; + wire [3 : 0] com_cmm_u_cmm_cfgspace_bar3_reg_8_1_0_0_0_0; + wire [3 : 0] com_cmm_u_cmm_cfgspace_bar4_reg_8_1_0_0_0_0; + wire [3 : 0] com_cmm_u_cmm_cfgspace_bar5_reg_8_1_0_0_0_0; + wire [1 : 1] com_cmm_u_cmm_cfgspace_x_dcmd_18_i_0_0_o3; + wire [31 : 0] com_cmm_u_cmm_cfgspace_decoder_read_data; + wire [29 : 29] com_cmm_u_cmm_cfgspace_low_addr_00_i_i_0_0_3; + wire [29 : 29] com_cmm_u_cmm_cfgspace_low_addr_00_i_i_0_0_0; + wire [21 : 21] com_cmm_u_cmm_cfgspace_low_addr_00_0_0_2; + wire [19 : 17] com_cmm_u_cmm_cfgspace_low_addr_00_i_i_0_2; + wire [19 : 17] com_cmm_u_cmm_cfgspace_low_addr_00_i_i_0_1; + wire [19 : 17] com_cmm_u_cmm_cfgspace_low_addr_00_i_i_0_0; + wire [14 : 13] com_cmm_u_cmm_cfgspace_low_addr_00_0_0_0_2; + wire [12 : 11] com_cmm_u_cmm_cfgspace_low_addr_00_0_0_0_0_2; + wire [12 : 11] com_cmm_u_cmm_cfgspace_low_addr_00_0_0_0_0_1; + wire [0 : 0] com_cmm_u_cmm_cfgspace_low_addr_00_i_0_0_0_0; + wire [2 : 1] com_cmm_u_cmm_cfgspace_sel_encodex_2; + wire [2 : 0] com_cmm_u_cmm_cfgspace_sel_encodex_1; + wire [2 : 0] com_cmm_u_cmm_cfgspace_sel_encodex; + wire [15 : 8] com_cmm_u_cmm_cfgspace_pme_pmcsr; + wire [14 : 13] com_cmm_u_cmm_cfgspace_pme_pmcsr_21; + wire [3 : 3] com_cmm_u_cmm_cfgspace_bar0_reg; + wire [31 : 0] com_cmm_u_cmm_cfgspace_x_dcap; + wire [0 : 0] com_cmm_u_cmm_cfgspace_x_lcap; + wire [7 : 0] com_cmm_u_cmm_cfgspace_cache_line; + wire [7 : 0] com_cmm_u_cmm_cfgspace_int_line; + wire [3 : 3] com_cmm_u_cmm_cfgspace_low_addr_01_7_0_am_0; + wire [31 : 0] com_cmm_u_cmm_cfgspace_low_addr_01; + wire [31 : 0] com_cmm_u_cmm_cfgspace_low_addr_03_q_4; + wire [31 : 0] com_cmm_u_cmm_cfgspace_low_addr_02; + wire [0 : 0] com_cmm_u_cmm_errman_cplu_num; + wire [0 : 0] com_cmm_u_cmm_errman_cplt_num; + wire [2 : 0] com_cmm_u_cmm_errman_ftl_num; + wire [2 : 0] com_cmm_u_cmm_errman_ftl_num_i; + wire [2 : 0] com_cmm_u_cmm_errman_cor_num_i; + wire [2 : 0] com_cmm_u_cmm_errman_nfl_num_i; + wire [3 : 0] com_cmm_u_cmm_errman_cnt_ftl; + wire [3 : 0] com_cmm_u_cmm_errman_cnt_cor; + wire [3 : 0] com_cmm_u_cmm_errman_cnt_nfl; + wire [3 : 0] com_cmm_u_cmm_errman_cnt_cplu; + wire [3 : 0] com_cmm_u_cmm_errman_cnt_cplt; + wire [2 : 2] com_cmm_u_cmm_errman_ns_fsm_0_i_0_a2_1_1; + wire [2 : 0] com_cmm_u_cmm_errman_cor_num_int; + wire [49 : 0] com_cmm_u_cmm_errman_cmt_rd_hdr; + wire [49 : 0] com_cmm_u_cmm_errman_cfg_rd_hdr; + wire [1 : 0] com_cmm_u_cmm_errman_ns_fsm_0_i_0_0; + wire [0 : 0] com_cmm_u_cmm_errman_ns_fsm_0_i_0_a2_1; + wire [49 : 0] com_cmm_u_cmm_errman_reg_cfg_wr_hdr; + wire [1 : 0] com_cmm_u_cmm_errman_reg_cfg_rp_4; + wire [1 : 0] com_cmm_u_cmm_errman_reg_cfg_rp; + wire [1 : 0] com_cmm_u_cmm_errman_reg_cmt_rp_4; + wire [1 : 0] com_cmm_u_cmm_errman_reg_cmt_rp; + wire [3 : 0] com_cmm_u_cmm_errman_cs_fsm; + wire [47 : 0] com_cmm_u_cmm_errman_reg_cmt_wr_hdr_5; + wire [48 : 0] com_cmm_u_cmm_errman_reg_cmt_wr_hdr; + wire [1 : 0] com_cmm_u_cmm_errman_reg_cfg_wp_4; + wire [1 : 0] com_cmm_u_cmm_errman_reg_cfg_wp; + wire [1 : 0] com_cmm_u_cmm_errman_reg_cmt_wp_4; + wire [1 : 0] com_cmm_u_cmm_errman_reg_cmt_wp; + wire [2 : 2] com_cmm_u_cmm_errman_cor_num; + wire [2 : 2] com_cmm_u_cmm_errman_nfl_num; + wire [3 : 0] com_cmm_u_cmm_errman_cor_cntr_reg_cnt_6; + wire [3 : 0] com_cmm_u_cmm_errman_cor_cntr_reg_cnt; + wire [4 : 0] com_cmm_u_cmm_errman_nfl_cntr_un14_reg_cnt; + wire [4 : 1] com_cmm_u_cmm_errman_nfl_cntr_un25_reg_cnt; + wire [3 : 0] com_cmm_u_cmm_errman_nfl_cntr_reg_cnt_6_0_i_m2_0_1; + wire [3 : 0] com_cmm_u_cmm_errman_nfl_cntr_reg_cnt; + wire [3 : 0] com_cmm_u_cmm_errman_ftl_cntr_reg_cnt; + wire [2 : 2] com_cmm_u_cmm_errman_cplt_cntr_reg_cnt_6_0_i_m2_0_bm_0; + wire [2 : 2] com_cmm_u_cmm_errman_cplt_cntr_reg_cnt_6_0_i_m2_0_am_0; + wire [4 : 4] com_cmm_u_cmm_errman_cplt_cntr_un14_reg_cnt; + wire [3 : 0] com_cmm_u_cmm_errman_cplt_cntr_reg_cnt_6_0_i_m2_0; + wire [3 : 0] com_cmm_u_cmm_errman_cplt_cntr_reg_cnt; + wire [2 : 2] com_cmm_u_cmm_errman_cplu_cntr_reg_cnt_6_0_i_m2_0_bm; + wire [2 : 2] com_cmm_u_cmm_errman_cplu_cntr_reg_cnt_6_0_i_m2_0_am; + wire [4 : 4] com_cmm_u_cmm_errman_cplu_cntr_un14_reg_cnt; + wire [3 : 0] com_cmm_u_cmm_errman_cplu_cntr_reg_cnt_6_0_i_m2_0_0; + wire [3 : 0] com_cmm_u_cmm_errman_cplu_cntr_reg_cnt; + wire [49 : 0] com_cmm_u_cmm_errman_cmt_hdr_buf_lutram_data; + wire [49 : 0] com_cmm_u_cmm_errman_cfg_hdr_buf_lutram_data; + wire [7 : 0] com_cmm_u_cmm_pm_inactivity_timer_cry; + wire [0 : 0] com_cmm_u_cmm_pm_un936_st_pm_next_m_0_a2_0_a2_0_a2_0_a2_0_a2_6; + wire [0 : 0] com_cmm_u_cmm_pm_un936_st_pm_next_m_0_a2_0_a2_0_a2_0_a2_0_a2_9; + wire [0 : 0] com_cmm_u_cmm_pm_un936_st_pm_next_m_0_a2_0_a2_0_a2_0_a2_0_a2_7; + wire [1 : 1] com_cmm_u_cmm_pm_st_pm_next_0_0_0_iv_i_i_a2_i_0_1; + wire [1 : 1] com_cmm_u_cmm_pm_st_pm_next_0_0_0_iv_i_i_a2_i_0_2; + wire [0 : 0] com_cmm_u_cmm_pm_un936_st_pm_next_m_0_a2_0_a2_0_a2_0_a2_0_a2_12; + wire [8 : 0] com_cmm_u_cmm_pm_inactivity_timer_s; + wire [0 : 0] com_cmm_u_cmm_pm_st_pm_next; + wire [0 : 0] com_cmm_u_cmm_pm_cfg_pcie_link_state; + wire [1 : 1] com_cmm_u_cmm_pm_enable_cmm_tx; + wire [8 : 0] com_cmm_u_cmm_pm_inactivity_timer_qxu; + wire [8 : 0] com_cmm_u_cmm_pm_inactivity_timer; + wire [2 : 0] com_cmm_u_cmm_arbiter_req_errman_d; + wire [3 : 3] com_cmm_u_cmm_arbiter_ns_fsm_i_i_0_o3; + wire [2 : 2] com_cmm_u_cmm_arbiter_ns_fsm_0_0_0_0; + wire [2 : 2] com_cmm_u_cmm_arbiter_ns_fsm_0_a4_0_0_a2_0_a2; + wire [3 : 0] com_cmm_u_cmm_arbiter_cs_fsm; + wire [3 : 3] com_cmm_u_cmm_dataproducer_req_gnt_code_8_i_0_0_1; + wire [31 : 2] com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_bm; + wire [31 : 2] com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_am; + wire [5 : 5] com_cmm_u_cmm_dataproducer_byte_06_21_iv_i_0_i_1; + wire [6 : 2] com_cmm_u_cmm_dataproducer_byte_11_17_m0; + wire [5 : 5] com_cmm_u_cmm_dataproducer_byte_07_27_0_1_iv_i_0_0_0; + wire [6 : 0] com_cmm_u_cmm_dataproducer_byte_09_17_1_0_0; + wire [7 : 0] com_cmm_u_cmm_dataproducer_byte_08_17_1_0_0; + wire [0 : 0] com_cmm_u_cmm_dataproducer_byte_11_17_m0_0_a2_0_a2_i_o2; + wire [7 : 0] com_cmm_u_cmm_dataproducer_byte_10_17_1_0_0; + wire [7 : 7] com_cmm_u_cmm_dataproducer_byte_09_17_0_0_0; + wire [5 : 5] com_cmm_u_cmm_dataproducer_byte_01_20_i_0_0_1_1; + wire [0 : 0] com_cmm_u_cmm_dataproducer_byte_04_17_i_0_0_a2; + wire [3 : 3] com_cmm_u_cmm_dataproducer_req_gnt_code_8_i_0_0_2; + wire [2 : 2] com_cmm_u_cmm_dataproducer_req_gnt_code_8_i_0_0_o3; + wire [1 : 0] com_cmm_u_cmm_dataproducer_req_gnt_state; + wire [0 : 0] com_cmm_u_cmm_dataproducer_pcie_link_state_d; + wire [7 : 0] com_cmm_u_cmm_dataproducer_byte_11_17; + wire [7 : 6] com_cmm_u_cmm_dataproducer_byte_07_27; + wire [4 : 4] com_cmm_u_cmm_dataproducer_byte_00_19; + wire [31 : 0] com_cmm_u_cmm_dataproducer_bytes_12_to_15_17; + assign + cfg_byte_en_n_6098[3] = cfg_byte_en_n[3], + cfg_byte_en_n_6098[2] = cfg_byte_en_n[2], + cfg_byte_en_n_6098[1] = cfg_byte_en_n[1], + cfg_byte_en_n_6098[0] = cfg_byte_en_n[0], + trn_rfc_ph_av[7] = trn_rfc_ph_av_6092[7], + trn_rfc_ph_av[6] = trn_rfc_ph_av_6092[6], + trn_rfc_ph_av[5] = trn_rfc_ph_av_6092[5], + trn_rfc_ph_av[4] = trn_rfc_ph_av_6092[4], + trn_rfc_ph_av[3] = trn_rfc_ph_av_6092[3], + trn_rfc_ph_av[2] = trn_rfc_ph_av_6092[2], + trn_rfc_ph_av[1] = trn_rfc_ph_av_6092[1], + trn_rfc_ph_av[0] = trn_rfc_ph_av_6092[0], + trn_rd[63] = NlwRenamedSig_OI_trn_rd[63], + trn_rd[62] = NlwRenamedSig_OI_trn_rd[62], + trn_rd[61] = NlwRenamedSig_OI_trn_rd[61], + trn_rd[60] = NlwRenamedSig_OI_trn_rd[60], + trn_rd[59] = NlwRenamedSig_OI_trn_rd[59], + trn_rd[58] = NlwRenamedSig_OI_trn_rd[58], + trn_rd[57] = NlwRenamedSig_OI_trn_rd[57], + trn_rd[56] = NlwRenamedSig_OI_trn_rd[56], + trn_rd[55] = NlwRenamedSig_OI_trn_rd[55], + trn_rd[54] = NlwRenamedSig_OI_trn_rd[54], + trn_rd[53] = NlwRenamedSig_OI_trn_rd[53], + trn_rd[52] = NlwRenamedSig_OI_trn_rd[52], + trn_rd[51] = NlwRenamedSig_OI_trn_rd[51], + trn_rd[50] = NlwRenamedSig_OI_trn_rd[50], + trn_rd[49] = NlwRenamedSig_OI_trn_rd[49], + trn_rd[48] = NlwRenamedSig_OI_trn_rd[48], + trn_rd[47] = NlwRenamedSig_OI_trn_rd[47], + trn_rd[46] = NlwRenamedSig_OI_trn_rd[46], + trn_rd[45] = NlwRenamedSig_OI_trn_rd[45], + trn_rd[44] = NlwRenamedSig_OI_trn_rd[44], + trn_rd[43] = NlwRenamedSig_OI_trn_rd[43], + trn_rd[42] = NlwRenamedSig_OI_trn_rd[42], + trn_rd[41] = NlwRenamedSig_OI_trn_rd[41], + trn_rd[40] = NlwRenamedSig_OI_trn_rd[40], + trn_rd[39] = NlwRenamedSig_OI_trn_rd[39], + trn_rd[38] = NlwRenamedSig_OI_trn_rd[38], + trn_rd[37] = NlwRenamedSig_OI_trn_rd[37], + trn_rd[36] = NlwRenamedSig_OI_trn_rd[36], + trn_rd[35] = NlwRenamedSig_OI_trn_rd[35], + trn_rd[34] = NlwRenamedSig_OI_trn_rd[34], + trn_rd[33] = NlwRenamedSig_OI_trn_rd[33], + trn_rd[32] = NlwRenamedSig_OI_trn_rd[32], + trn_rd[31] = NlwRenamedSig_OI_trn_rd[31], + trn_rd[30] = NlwRenamedSig_OI_trn_rd[30], + trn_rd[29] = NlwRenamedSig_OI_trn_rd[29], + trn_rd[28] = NlwRenamedSig_OI_trn_rd[28], + trn_rd[27] = NlwRenamedSig_OI_trn_rd[27], + trn_rd[26] = NlwRenamedSig_OI_trn_rd[26], + trn_rd[25] = NlwRenamedSig_OI_trn_rd[25], + trn_rd[24] = NlwRenamedSig_OI_trn_rd[24], + trn_rd[23] = NlwRenamedSig_OI_trn_rd[23], + trn_rd[22] = NlwRenamedSig_OI_trn_rd[22], + trn_rd[21] = NlwRenamedSig_OI_trn_rd[21], + trn_rd[20] = NlwRenamedSig_OI_trn_rd[20], + trn_rd[19] = NlwRenamedSig_OI_trn_rd[19], + trn_rd[18] = NlwRenamedSig_OI_trn_rd[18], + trn_rd[17] = NlwRenamedSig_OI_trn_rd[17], + trn_rd[16] = NlwRenamedSig_OI_trn_rd[16], + trn_rd[15] = NlwRenamedSig_OI_trn_rd[15], + trn_rd[14] = NlwRenamedSig_OI_trn_rd[14], + trn_rd[13] = NlwRenamedSig_OI_trn_rd[13], + trn_rd[12] = NlwRenamedSig_OI_trn_rd[12], + trn_rd[11] = NlwRenamedSig_OI_trn_rd[11], + trn_rd[10] = NlwRenamedSig_OI_trn_rd[10], + trn_rd[9] = NlwRenamedSig_OI_trn_rd[9], + trn_rd[8] = NlwRenamedSig_OI_trn_rd[8], + trn_rd[7] = NlwRenamedSig_OI_trn_rd[7], + trn_rd[6] = NlwRenamedSig_OI_trn_rd[6], + trn_rd[5] = NlwRenamedSig_OI_trn_rd[5], + trn_rd[4] = NlwRenamedSig_OI_trn_rd[4], + trn_rd[3] = NlwRenamedSig_OI_trn_rd[3], + trn_rd[2] = NlwRenamedSig_OI_trn_rd[2], + trn_rd[1] = NlwRenamedSig_OI_trn_rd[1], + trn_rd[0] = NlwRenamedSig_OI_trn_rd[0], + trn_td_6087[63] = trn_td[63], + trn_td_6087[62] = trn_td[62], + trn_td_6087[61] = trn_td[61], + trn_td_6087[60] = trn_td[60], + trn_td_6087[59] = trn_td[59], + trn_td_6087[58] = trn_td[58], + trn_td_6087[57] = trn_td[57], + trn_td_6087[56] = trn_td[56], + trn_td_6087[55] = trn_td[55], + trn_td_6087[54] = trn_td[54], + trn_td_6087[53] = trn_td[53], + trn_td_6087[52] = trn_td[52], + trn_td_6087[51] = trn_td[51], + trn_td_6087[50] = trn_td[50], + trn_td_6087[49] = trn_td[49], + trn_td_6087[48] = trn_td[48], + trn_td_6087[47] = trn_td[47], + trn_td_6087[46] = trn_td[46], + trn_td_6087[45] = trn_td[45], + trn_td_6087[44] = trn_td[44], + trn_td_6087[43] = trn_td[43], + trn_td_6087[42] = trn_td[42], + trn_td_6087[41] = trn_td[41], + trn_td_6087[40] = trn_td[40], + trn_td_6087[39] = trn_td[39], + trn_td_6087[38] = trn_td[38], + trn_td_6087[37] = trn_td[37], + trn_td_6087[36] = trn_td[36], + trn_td_6087[35] = trn_td[35], + trn_td_6087[34] = trn_td[34], + trn_td_6087[33] = trn_td[33], + trn_td_6087[32] = trn_td[32], + trn_td_6087[31] = trn_td[31], + trn_td_6087[30] = trn_td[30], + trn_td_6087[29] = trn_td[29], + trn_td_6087[28] = trn_td[28], + trn_td_6087[27] = trn_td[27], + trn_td_6087[26] = trn_td[26], + trn_td_6087[25] = trn_td[25], + trn_td_6087[24] = trn_td[24], + trn_td_6087[23] = trn_td[23], + trn_td_6087[22] = trn_td[22], + trn_td_6087[21] = trn_td[21], + trn_td_6087[20] = trn_td[20], + trn_td_6087[19] = trn_td[19], + trn_td_6087[18] = trn_td[18], + trn_td_6087[17] = trn_td[17], + trn_td_6087[16] = trn_td[16], + trn_td_6087[15] = trn_td[15], + trn_td_6087[14] = trn_td[14], + trn_td_6087[13] = trn_td[13], + trn_td_6087[12] = trn_td[12], + trn_td_6087[11] = trn_td[11], + trn_td_6087[10] = trn_td[10], + trn_td_6087[9] = trn_td[9], + trn_td_6087[8] = trn_td[8], + trn_td_6087[7] = trn_td[7], + trn_td_6087[6] = trn_td[6], + trn_td_6087[5] = trn_td[5], + trn_td_6087[4] = trn_td[4], + trn_td_6087[3] = trn_td[3], + trn_td_6087[2] = trn_td[2], + trn_td_6087[1] = trn_td[1], + trn_td_6087[0] = trn_td[0], + cfg_err_tlp_cpl_header_6100[47] = cfg_err_tlp_cpl_header[47], + cfg_err_tlp_cpl_header_6100[46] = cfg_err_tlp_cpl_header[46], + cfg_err_tlp_cpl_header_6100[45] = cfg_err_tlp_cpl_header[45], + cfg_err_tlp_cpl_header_6100[44] = cfg_err_tlp_cpl_header[44], + cfg_err_tlp_cpl_header_6100[43] = cfg_err_tlp_cpl_header[43], + cfg_err_tlp_cpl_header_6100[42] = cfg_err_tlp_cpl_header[42], + cfg_err_tlp_cpl_header_6100[41] = cfg_err_tlp_cpl_header[41], + cfg_err_tlp_cpl_header_6100[40] = cfg_err_tlp_cpl_header[40], + cfg_err_tlp_cpl_header_6100[39] = cfg_err_tlp_cpl_header[39], + cfg_err_tlp_cpl_header_6100[38] = cfg_err_tlp_cpl_header[38], + cfg_err_tlp_cpl_header_6100[37] = cfg_err_tlp_cpl_header[37], + cfg_err_tlp_cpl_header_6100[36] = cfg_err_tlp_cpl_header[36], + cfg_err_tlp_cpl_header_6100[35] = cfg_err_tlp_cpl_header[35], + cfg_err_tlp_cpl_header_6100[34] = cfg_err_tlp_cpl_header[34], + cfg_err_tlp_cpl_header_6100[33] = cfg_err_tlp_cpl_header[33], + cfg_err_tlp_cpl_header_6100[32] = cfg_err_tlp_cpl_header[32], + cfg_err_tlp_cpl_header_6100[31] = cfg_err_tlp_cpl_header[31], + cfg_err_tlp_cpl_header_6100[30] = cfg_err_tlp_cpl_header[30], + cfg_err_tlp_cpl_header_6100[29] = cfg_err_tlp_cpl_header[29], + cfg_err_tlp_cpl_header_6100[28] = cfg_err_tlp_cpl_header[28], + cfg_err_tlp_cpl_header_6100[27] = cfg_err_tlp_cpl_header[27], + cfg_err_tlp_cpl_header_6100[26] = cfg_err_tlp_cpl_header[26], + cfg_err_tlp_cpl_header_6100[25] = cfg_err_tlp_cpl_header[25], + cfg_err_tlp_cpl_header_6100[24] = cfg_err_tlp_cpl_header[24], + cfg_err_tlp_cpl_header_6100[23] = cfg_err_tlp_cpl_header[23], + cfg_err_tlp_cpl_header_6100[22] = cfg_err_tlp_cpl_header[22], + cfg_err_tlp_cpl_header_6100[21] = cfg_err_tlp_cpl_header[21], + cfg_err_tlp_cpl_header_6100[20] = cfg_err_tlp_cpl_header[20], + cfg_err_tlp_cpl_header_6100[19] = cfg_err_tlp_cpl_header[19], + cfg_err_tlp_cpl_header_6100[18] = cfg_err_tlp_cpl_header[18], + cfg_err_tlp_cpl_header_6100[17] = cfg_err_tlp_cpl_header[17], + cfg_err_tlp_cpl_header_6100[16] = cfg_err_tlp_cpl_header[16], + cfg_err_tlp_cpl_header_6100[15] = cfg_err_tlp_cpl_header[15], + cfg_err_tlp_cpl_header_6100[14] = cfg_err_tlp_cpl_header[14], + cfg_err_tlp_cpl_header_6100[13] = cfg_err_tlp_cpl_header[13], + cfg_err_tlp_cpl_header_6100[12] = cfg_err_tlp_cpl_header[12], + cfg_err_tlp_cpl_header_6100[11] = cfg_err_tlp_cpl_header[11], + cfg_err_tlp_cpl_header_6100[10] = cfg_err_tlp_cpl_header[10], + cfg_err_tlp_cpl_header_6100[9] = cfg_err_tlp_cpl_header[9], + cfg_err_tlp_cpl_header_6100[8] = cfg_err_tlp_cpl_header[8], + cfg_err_tlp_cpl_header_6100[7] = cfg_err_tlp_cpl_header[7], + cfg_err_tlp_cpl_header_6100[6] = cfg_err_tlp_cpl_header[6], + cfg_err_tlp_cpl_header_6100[5] = cfg_err_tlp_cpl_header[5], + cfg_err_tlp_cpl_header_6100[4] = cfg_err_tlp_cpl_header[4], + cfg_err_tlp_cpl_header_6100[3] = cfg_err_tlp_cpl_header[3], + cfg_err_tlp_cpl_header_6100[2] = cfg_err_tlp_cpl_header[2], + cfg_err_tlp_cpl_header_6100[1] = cfg_err_tlp_cpl_header[1], + cfg_err_tlp_cpl_header_6100[0] = cfg_err_tlp_cpl_header[0], + trn_rbar_hit_n[6] = trn_rbar_hit_n_6089[6], + trn_rbar_hit_n[5] = trn_rbar_hit_n_6089[5], + trn_rbar_hit_n[4] = trn_rbar_hit_n_6089[4], + trn_rbar_hit_n[3] = trn_rbar_hit_n_6089[3], + trn_rbar_hit_n[2] = trn_rbar_hit_n_6089[2], + trn_rbar_hit_n[1] = trn_rbar_hit_n_6089[1], + trn_rbar_hit_n[0] = trn_rbar_hit_n_6089[0], + trn_rfc_cpld_av[11] = NlwRenamedSig_OI_trn_rfc_cpld_av[11], + trn_rfc_cpld_av[10] = trn_rfc_cpld_av_6095[10], + trn_rfc_cpld_av[9] = trn_rfc_cpld_av_6095[9], + trn_rfc_cpld_av[8] = trn_rfc_cpld_av_6095[8], + trn_rfc_cpld_av[7] = trn_rfc_cpld_av_6095[7], + trn_rfc_cpld_av[6] = trn_rfc_cpld_av_6095[6], + trn_rfc_cpld_av[5] = trn_rfc_cpld_av_6095[5], + trn_rfc_cpld_av[4] = trn_rfc_cpld_av_6095[4], + trn_rfc_cpld_av[3] = trn_rfc_cpld_av_6095[3], + trn_rfc_cpld_av[2] = trn_rfc_cpld_av_6095[2], + trn_rfc_cpld_av[1] = trn_rfc_cpld_av_6095[1], + trn_rfc_cpld_av[0] = trn_rfc_cpld_av_6095[0], + cfg_lcommand[15] = NlwRenamedSignal_cfg_lcommand[15], + cfg_lcommand[14] = NlwRenamedSignal_cfg_lcommand[15], + cfg_lcommand[13] = NlwRenamedSignal_cfg_lcommand[15], + cfg_lcommand[12] = NlwRenamedSignal_cfg_lcommand[15], + cfg_lcommand[11] = NlwRenamedSignal_cfg_lcommand[15], + cfg_lcommand[10] = NlwRenamedSignal_cfg_lcommand[15], + cfg_lcommand[9] = NlwRenamedSignal_cfg_lcommand[15], + cfg_lcommand[8] = NlwRenamedSignal_cfg_lcommand[15], + cfg_lcommand[7] = NlwRenamedSig_OI_cfg_lcommand_7_, + cfg_lcommand[6] = NlwRenamedSig_OI_cfg_lcommand_6_, + cfg_lcommand[5] = NlwRenamedSignal_cfg_lcommand[15], + cfg_lcommand[4] = NlwRenamedSignal_cfg_lcommand[15], + cfg_lcommand[3] = NlwRenamedSig_OI_cfg_lcommand_3_, + cfg_lcommand[2] = NlwRenamedSignal_cfg_lcommand[15], + cfg_lcommand[1] = NlwRenamedSig_OI_cfg_lcommand_1_, + cfg_lcommand[0] = NlwRenamedSig_OI_cfg_lcommand_0_, + cfg_dstatus[15] = NlwRenamedSignal_cfg_lcommand[15], + cfg_dstatus[14] = NlwRenamedSignal_cfg_lcommand[15], + cfg_dstatus[13] = NlwRenamedSignal_cfg_lcommand[15], + cfg_dstatus[12] = NlwRenamedSignal_cfg_lcommand[15], + cfg_dstatus[11] = NlwRenamedSignal_cfg_lcommand[15], + cfg_dstatus[10] = NlwRenamedSignal_cfg_lcommand[15], + cfg_dstatus[9] = NlwRenamedSignal_cfg_lcommand[15], + cfg_dstatus[8] = NlwRenamedSignal_cfg_lcommand[15], + cfg_dstatus[7] = NlwRenamedSignal_cfg_lcommand[15], + cfg_dstatus[6] = NlwRenamedSignal_cfg_lcommand[15], + cfg_dstatus[5] = NlwRenamedSig_OI_cfg_dstatus_5_, + cfg_dstatus[4] = NlwRenamedSignal_cfg_lcommand[15], + cfg_dstatus[3] = NlwRenamedSig_OI_cfg_dstatus_3_, + cfg_dstatus[2] = NlwRenamedSig_OI_cfg_dstatus_2_, + cfg_dstatus[1] = NlwRenamedSig_OI_cfg_dstatus_1_, + cfg_dstatus[0] = NlwRenamedSig_OI_cfg_dstatus_0_, + trn_rrem_n[7] = NlwRenamedSignal_cfg_lcommand[15], + trn_rrem_n[6] = NlwRenamedSignal_cfg_lcommand[15], + trn_rrem_n[5] = NlwRenamedSignal_cfg_lcommand[15], + trn_rrem_n[4] = NlwRenamedSignal_cfg_lcommand[15], + trn_rrem_n[3] = NlwRenamedSignal_trn_rrem_n[3], + trn_rrem_n[2] = NlwRenamedSignal_trn_rrem_n[3], + trn_rrem_n[1] = NlwRenamedSignal_trn_rrem_n[3], + trn_rrem_n[0] = NlwRenamedSignal_trn_rrem_n[3], + cfg_status[15] = NlwRenamedSig_OI_cfg_status_15_, + cfg_status[14] = NlwRenamedSig_OI_cfg_status_14_, + cfg_status[13] = NlwRenamedSig_OI_cfg_status_13_, + cfg_status[12] = NlwRenamedSig_OI_cfg_status_12_, + cfg_status[11] = NlwRenamedSig_OI_cfg_status_11_, + cfg_status[10] = NlwRenamedSignal_cfg_lcommand[15], + cfg_status[9] = NlwRenamedSignal_cfg_lcommand[15], + cfg_status[8] = NlwRenamedSig_OI_cfg_status_8_, + cfg_status[7] = NlwRenamedSignal_cfg_lcommand[15], + cfg_status[6] = NlwRenamedSignal_cfg_lcommand[15], + cfg_status[5] = NlwRenamedSignal_cfg_lcommand[15], + cfg_status[4] = NlwRenamedSig_OI_cfg_status_4_, + cfg_status[3] = NlwRenamedSig_OI_cfg_status_3_, + cfg_status[2] = NlwRenamedSignal_cfg_lcommand[15], + cfg_status[1] = NlwRenamedSignal_cfg_lcommand[15], + cfg_status[0] = NlwRenamedSignal_cfg_lcommand[15], + trn_rfc_cplh_av[7] = NlwRenamedSig_OI_trn_rfc_cplh_av[7], + trn_rfc_cplh_av[6] = trn_rfc_cplh_av_6094[6], + trn_rfc_cplh_av[5] = trn_rfc_cplh_av_6094[5], + trn_rfc_cplh_av[4] = trn_rfc_cplh_av_6094[4], + trn_rfc_cplh_av[3] = trn_rfc_cplh_av_6094[3], + trn_rfc_cplh_av[2] = trn_rfc_cplh_av_6094[2], + trn_rfc_cplh_av[1] = trn_rfc_cplh_av_6094[1], + trn_rfc_cplh_av[0] = trn_rfc_cplh_av_6094[0], + cfg_command[15] = NlwRenamedSignal_cfg_lcommand[15], + cfg_command[14] = NlwRenamedSignal_cfg_lcommand[15], + cfg_command[13] = NlwRenamedSignal_cfg_lcommand[15], + cfg_command[12] = NlwRenamedSignal_cfg_lcommand[15], + cfg_command[11] = NlwRenamedSignal_cfg_lcommand[15], + cfg_command[10] = NlwRenamedSig_OI_cfg_command_10_, + cfg_command[9] = NlwRenamedSignal_cfg_lcommand[15], + cfg_command[8] = NlwRenamedSig_OI_cfg_command_8_, + cfg_command[7] = NlwRenamedSignal_cfg_lcommand[15], + cfg_command[6] = NlwRenamedSig_OI_cfg_command_6_, + cfg_command[5] = NlwRenamedSignal_cfg_lcommand[15], + cfg_command[4] = NlwRenamedSignal_cfg_lcommand[15], + cfg_command[3] = NlwRenamedSignal_cfg_lcommand[15], + cfg_command[2] = NlwRenamedSig_OI_cfg_command_2_, + cfg_command[1] = NlwRenamedSig_OI_cfg_command_1_, + cfg_command[0] = NlwRenamedSig_OI_cfg_command_0_, + pci_exp_txn[3] = pci_exp_txn_6084[3], + pci_exp_txn[2] = pci_exp_txn_6084[2], + pci_exp_txn[1] = pci_exp_txn_6084[1], + pci_exp_txn[0] = pci_exp_txn_6084[0], + pci_exp_txp[3] = pci_exp_txp_6083[3], + pci_exp_txp[2] = pci_exp_txp_6083[2], + pci_exp_txp[1] = pci_exp_txp_6083[1], + pci_exp_txp[0] = pci_exp_txp_6083[0], + trn_trem_n_6088[7] = trn_trem_n[7], + trn_trem_n_6088[6] = trn_trem_n[6], + trn_trem_n_6088[5] = trn_trem_n[5], + trn_trem_n_6088[4] = trn_trem_n[4], + trn_trem_n_6088[3] = trn_trem_n[3], + trn_trem_n_6088[2] = trn_trem_n[2], + trn_trem_n_6088[1] = trn_trem_n[1], + trn_trem_n_6088[0] = trn_trem_n[0], + cfg_cfg_6102[1023] = cfg_cfg[1023], + cfg_cfg_6102[1022] = cfg_cfg[1022], + cfg_cfg_6102[1021] = cfg_cfg[1021], + cfg_cfg_6102[1020] = cfg_cfg[1020], + cfg_cfg_6102[1019] = cfg_cfg[1019], + cfg_cfg_6102[1018] = cfg_cfg[1018], + cfg_cfg_6102[1017] = cfg_cfg[1017], + cfg_cfg_6102[1016] = cfg_cfg[1016], + cfg_cfg_6102[1015] = cfg_cfg[1015], + cfg_cfg_6102[1014] = cfg_cfg[1014], + cfg_cfg_6102[1013] = cfg_cfg[1013], + cfg_cfg_6102[1012] = cfg_cfg[1012], + cfg_cfg_6102[1011] = cfg_cfg[1011], + cfg_cfg_6102[1010] = cfg_cfg[1010], + cfg_cfg_6102[1009] = cfg_cfg[1009], + cfg_cfg_6102[1008] = cfg_cfg[1008], + cfg_cfg_6102[1007] = cfg_cfg[1007], + cfg_cfg_6102[1006] = cfg_cfg[1006], + cfg_cfg_6102[1005] = cfg_cfg[1005], + cfg_cfg_6102[1004] = cfg_cfg[1004], + cfg_cfg_6102[1003] = cfg_cfg[1003], + cfg_cfg_6102[1002] = cfg_cfg[1002], + cfg_cfg_6102[1001] = cfg_cfg[1001], + cfg_cfg_6102[1000] = cfg_cfg[1000], + cfg_cfg_6102[999] = cfg_cfg[999], + cfg_cfg_6102[998] = cfg_cfg[998], + cfg_cfg_6102[997] = cfg_cfg[997], + cfg_cfg_6102[996] = cfg_cfg[996], + cfg_cfg_6102[995] = cfg_cfg[995], + cfg_cfg_6102[994] = cfg_cfg[994], + cfg_cfg_6102[993] = cfg_cfg[993], + cfg_cfg_6102[992] = cfg_cfg[992], + cfg_cfg_6102[991] = cfg_cfg[991], + cfg_cfg_6102[990] = cfg_cfg[990], + cfg_cfg_6102[989] = cfg_cfg[989], + cfg_cfg_6102[988] = cfg_cfg[988], + cfg_cfg_6102[987] = cfg_cfg[987], + cfg_cfg_6102[986] = cfg_cfg[986], + cfg_cfg_6102[985] = cfg_cfg[985], + cfg_cfg_6102[984] = cfg_cfg[984], + cfg_cfg_6102[983] = cfg_cfg[983], + cfg_cfg_6102[982] = cfg_cfg[982], + cfg_cfg_6102[981] = cfg_cfg[981], + cfg_cfg_6102[980] = cfg_cfg[980], + cfg_cfg_6102[979] = cfg_cfg[979], + cfg_cfg_6102[978] = cfg_cfg[978], + cfg_cfg_6102[977] = cfg_cfg[977], + cfg_cfg_6102[976] = cfg_cfg[976], + cfg_cfg_6102[975] = cfg_cfg[975], + cfg_cfg_6102[974] = cfg_cfg[974], + cfg_cfg_6102[973] = cfg_cfg[973], + cfg_cfg_6102[972] = cfg_cfg[972], + cfg_cfg_6102[971] = cfg_cfg[971], + cfg_cfg_6102[970] = cfg_cfg[970], + cfg_cfg_6102[969] = cfg_cfg[969], + cfg_cfg_6102[968] = cfg_cfg[968], + cfg_cfg_6102[967] = cfg_cfg[967], + cfg_cfg_6102[966] = cfg_cfg[966], + cfg_cfg_6102[965] = cfg_cfg[965], + cfg_cfg_6102[964] = cfg_cfg[964], + cfg_cfg_6102[963] = cfg_cfg[963], + cfg_cfg_6102[962] = cfg_cfg[962], + cfg_cfg_6102[961] = cfg_cfg[961], + cfg_cfg_6102[960] = cfg_cfg[960], + cfg_cfg_6102[959] = cfg_cfg[959], + cfg_cfg_6102[958] = cfg_cfg[958], + cfg_cfg_6102[957] = cfg_cfg[957], + cfg_cfg_6102[956] = cfg_cfg[956], + cfg_cfg_6102[955] = cfg_cfg[955], + cfg_cfg_6102[954] = cfg_cfg[954], + cfg_cfg_6102[953] = cfg_cfg[953], + cfg_cfg_6102[952] = cfg_cfg[952], + cfg_cfg_6102[951] = cfg_cfg[951], + cfg_cfg_6102[950] = cfg_cfg[950], + cfg_cfg_6102[949] = cfg_cfg[949], + cfg_cfg_6102[948] = cfg_cfg[948], + cfg_cfg_6102[947] = cfg_cfg[947], + cfg_cfg_6102[946] = cfg_cfg[946], + cfg_cfg_6102[945] = cfg_cfg[945], + cfg_cfg_6102[944] = cfg_cfg[944], + cfg_cfg_6102[943] = cfg_cfg[943], + cfg_cfg_6102[942] = cfg_cfg[942], + cfg_cfg_6102[941] = cfg_cfg[941], + cfg_cfg_6102[940] = cfg_cfg[940], + cfg_cfg_6102[939] = cfg_cfg[939], + cfg_cfg_6102[938] = cfg_cfg[938], + cfg_cfg_6102[937] = cfg_cfg[937], + cfg_cfg_6102[936] = cfg_cfg[936], + cfg_cfg_6102[935] = cfg_cfg[935], + cfg_cfg_6102[934] = cfg_cfg[934], + cfg_cfg_6102[933] = cfg_cfg[933], + cfg_cfg_6102[932] = cfg_cfg[932], + cfg_cfg_6102[931] = cfg_cfg[931], + cfg_cfg_6102[930] = cfg_cfg[930], + cfg_cfg_6102[929] = cfg_cfg[929], + cfg_cfg_6102[928] = cfg_cfg[928], + cfg_cfg_6102[927] = cfg_cfg[927], + cfg_cfg_6102[926] = cfg_cfg[926], + cfg_cfg_6102[925] = cfg_cfg[925], + cfg_cfg_6102[924] = cfg_cfg[924], + cfg_cfg_6102[923] = cfg_cfg[923], + cfg_cfg_6102[922] = cfg_cfg[922], + cfg_cfg_6102[921] = cfg_cfg[921], + cfg_cfg_6102[920] = cfg_cfg[920], + cfg_cfg_6102[919] = cfg_cfg[919], + cfg_cfg_6102[918] = cfg_cfg[918], + cfg_cfg_6102[917] = cfg_cfg[917], + cfg_cfg_6102[916] = cfg_cfg[916], + cfg_cfg_6102[915] = cfg_cfg[915], + cfg_cfg_6102[914] = cfg_cfg[914], + cfg_cfg_6102[913] = cfg_cfg[913], + cfg_cfg_6102[912] = cfg_cfg[912], + cfg_cfg_6102[911] = cfg_cfg[911], + cfg_cfg_6102[910] = cfg_cfg[910], + cfg_cfg_6102[909] = cfg_cfg[909], + cfg_cfg_6102[908] = cfg_cfg[908], + cfg_cfg_6102[907] = cfg_cfg[907], + cfg_cfg_6102[906] = cfg_cfg[906], + cfg_cfg_6102[905] = cfg_cfg[905], + cfg_cfg_6102[904] = cfg_cfg[904], + cfg_cfg_6102[903] = cfg_cfg[903], + cfg_cfg_6102[902] = cfg_cfg[902], + cfg_cfg_6102[901] = cfg_cfg[901], + cfg_cfg_6102[900] = cfg_cfg[900], + cfg_cfg_6102[899] = cfg_cfg[899], + cfg_cfg_6102[898] = cfg_cfg[898], + cfg_cfg_6102[897] = cfg_cfg[897], + cfg_cfg_6102[896] = cfg_cfg[896], + cfg_cfg_6102[895] = cfg_cfg[895], + cfg_cfg_6102[894] = cfg_cfg[894], + cfg_cfg_6102[893] = cfg_cfg[893], + cfg_cfg_6102[892] = cfg_cfg[892], + cfg_cfg_6102[891] = cfg_cfg[891], + cfg_cfg_6102[890] = cfg_cfg[890], + cfg_cfg_6102[889] = cfg_cfg[889], + cfg_cfg_6102[888] = cfg_cfg[888], + cfg_cfg_6102[887] = cfg_cfg[887], + cfg_cfg_6102[886] = cfg_cfg[886], + cfg_cfg_6102[885] = cfg_cfg[885], + cfg_cfg_6102[884] = cfg_cfg[884], + cfg_cfg_6102[883] = cfg_cfg[883], + cfg_cfg_6102[882] = cfg_cfg[882], + cfg_cfg_6102[881] = cfg_cfg[881], + cfg_cfg_6102[880] = cfg_cfg[880], + cfg_cfg_6102[879] = cfg_cfg[879], + cfg_cfg_6102[878] = cfg_cfg[878], + cfg_cfg_6102[877] = cfg_cfg[877], + cfg_cfg_6102[876] = cfg_cfg[876], + cfg_cfg_6102[875] = cfg_cfg[875], + cfg_cfg_6102[874] = cfg_cfg[874], + cfg_cfg_6102[873] = cfg_cfg[873], + cfg_cfg_6102[872] = cfg_cfg[872], + cfg_cfg_6102[871] = cfg_cfg[871], + cfg_cfg_6102[870] = cfg_cfg[870], + cfg_cfg_6102[869] = cfg_cfg[869], + cfg_cfg_6102[868] = cfg_cfg[868], + cfg_cfg_6102[867] = cfg_cfg[867], + cfg_cfg_6102[866] = cfg_cfg[866], + cfg_cfg_6102[865] = cfg_cfg[865], + cfg_cfg_6102[864] = cfg_cfg[864], + cfg_cfg_6102[863] = cfg_cfg[863], + cfg_cfg_6102[862] = cfg_cfg[862], + cfg_cfg_6102[861] = cfg_cfg[861], + cfg_cfg_6102[860] = cfg_cfg[860], + cfg_cfg_6102[859] = cfg_cfg[859], + cfg_cfg_6102[858] = cfg_cfg[858], + cfg_cfg_6102[857] = cfg_cfg[857], + cfg_cfg_6102[856] = cfg_cfg[856], + cfg_cfg_6102[855] = cfg_cfg[855], + cfg_cfg_6102[854] = cfg_cfg[854], + cfg_cfg_6102[853] = cfg_cfg[853], + cfg_cfg_6102[852] = cfg_cfg[852], + cfg_cfg_6102[851] = cfg_cfg[851], + cfg_cfg_6102[850] = cfg_cfg[850], + cfg_cfg_6102[849] = cfg_cfg[849], + cfg_cfg_6102[848] = cfg_cfg[848], + cfg_cfg_6102[847] = cfg_cfg[847], + cfg_cfg_6102[846] = cfg_cfg[846], + cfg_cfg_6102[845] = cfg_cfg[845], + cfg_cfg_6102[844] = cfg_cfg[844], + cfg_cfg_6102[843] = cfg_cfg[843], + cfg_cfg_6102[842] = cfg_cfg[842], + cfg_cfg_6102[841] = cfg_cfg[841], + cfg_cfg_6102[840] = cfg_cfg[840], + cfg_cfg_6102[839] = cfg_cfg[839], + cfg_cfg_6102[838] = cfg_cfg[838], + cfg_cfg_6102[837] = cfg_cfg[837], + cfg_cfg_6102[836] = cfg_cfg[836], + cfg_cfg_6102[835] = cfg_cfg[835], + cfg_cfg_6102[834] = cfg_cfg[834], + cfg_cfg_6102[833] = cfg_cfg[833], + cfg_cfg_6102[832] = cfg_cfg[832], + cfg_cfg_6102[831] = cfg_cfg[831], + cfg_cfg_6102[830] = cfg_cfg[830], + cfg_cfg_6102[829] = cfg_cfg[829], + cfg_cfg_6102[828] = cfg_cfg[828], + cfg_cfg_6102[827] = cfg_cfg[827], + cfg_cfg_6102[826] = cfg_cfg[826], + cfg_cfg_6102[825] = cfg_cfg[825], + cfg_cfg_6102[824] = cfg_cfg[824], + cfg_cfg_6102[823] = cfg_cfg[823], + cfg_cfg_6102[822] = cfg_cfg[822], + cfg_cfg_6102[821] = cfg_cfg[821], + cfg_cfg_6102[820] = cfg_cfg[820], + cfg_cfg_6102[819] = cfg_cfg[819], + cfg_cfg_6102[818] = cfg_cfg[818], + cfg_cfg_6102[817] = cfg_cfg[817], + cfg_cfg_6102[816] = cfg_cfg[816], + cfg_cfg_6102[815] = cfg_cfg[815], + cfg_cfg_6102[814] = cfg_cfg[814], + cfg_cfg_6102[813] = cfg_cfg[813], + cfg_cfg_6102[812] = cfg_cfg[812], + cfg_cfg_6102[811] = cfg_cfg[811], + cfg_cfg_6102[810] = cfg_cfg[810], + cfg_cfg_6102[809] = cfg_cfg[809], + cfg_cfg_6102[808] = cfg_cfg[808], + cfg_cfg_6102[807] = cfg_cfg[807], + cfg_cfg_6102[806] = cfg_cfg[806], + cfg_cfg_6102[805] = cfg_cfg[805], + cfg_cfg_6102[804] = cfg_cfg[804], + cfg_cfg_6102[803] = cfg_cfg[803], + cfg_cfg_6102[802] = cfg_cfg[802], + cfg_cfg_6102[801] = cfg_cfg[801], + cfg_cfg_6102[800] = cfg_cfg[800], + cfg_cfg_6102[799] = cfg_cfg[799], + cfg_cfg_6102[798] = cfg_cfg[798], + cfg_cfg_6102[797] = cfg_cfg[797], + cfg_cfg_6102[796] = cfg_cfg[796], + cfg_cfg_6102[795] = cfg_cfg[795], + cfg_cfg_6102[794] = cfg_cfg[794], + cfg_cfg_6102[793] = cfg_cfg[793], + cfg_cfg_6102[792] = cfg_cfg[792], + cfg_cfg_6102[791] = cfg_cfg[791], + cfg_cfg_6102[790] = cfg_cfg[790], + cfg_cfg_6102[789] = cfg_cfg[789], + cfg_cfg_6102[788] = cfg_cfg[788], + cfg_cfg_6102[787] = cfg_cfg[787], + cfg_cfg_6102[786] = cfg_cfg[786], + cfg_cfg_6102[785] = cfg_cfg[785], + cfg_cfg_6102[784] = cfg_cfg[784], + cfg_cfg_6102[783] = cfg_cfg[783], + cfg_cfg_6102[782] = cfg_cfg[782], + cfg_cfg_6102[781] = cfg_cfg[781], + cfg_cfg_6102[780] = cfg_cfg[780], + cfg_cfg_6102[779] = cfg_cfg[779], + cfg_cfg_6102[778] = cfg_cfg[778], + cfg_cfg_6102[777] = cfg_cfg[777], + cfg_cfg_6102[776] = cfg_cfg[776], + cfg_cfg_6102[775] = cfg_cfg[775], + cfg_cfg_6102[774] = cfg_cfg[774], + cfg_cfg_6102[773] = cfg_cfg[773], + cfg_cfg_6102[772] = cfg_cfg[772], + cfg_cfg_6102[771] = cfg_cfg[771], + cfg_cfg_6102[770] = cfg_cfg[770], + cfg_cfg_6102[769] = cfg_cfg[769], + cfg_cfg_6102[768] = cfg_cfg[768], + cfg_cfg_6102[767] = cfg_cfg[767], + cfg_cfg_6102[766] = cfg_cfg[766], + cfg_cfg_6102[765] = cfg_cfg[765], + cfg_cfg_6102[764] = cfg_cfg[764], + cfg_cfg_6102[763] = cfg_cfg[763], + cfg_cfg_6102[762] = cfg_cfg[762], + cfg_cfg_6102[761] = cfg_cfg[761], + cfg_cfg_6102[760] = cfg_cfg[760], + cfg_cfg_6102[759] = cfg_cfg[759], + cfg_cfg_6102[758] = cfg_cfg[758], + cfg_cfg_6102[757] = cfg_cfg[757], + cfg_cfg_6102[756] = cfg_cfg[756], + cfg_cfg_6102[755] = cfg_cfg[755], + cfg_cfg_6102[754] = cfg_cfg[754], + cfg_cfg_6102[753] = cfg_cfg[753], + cfg_cfg_6102[752] = cfg_cfg[752], + cfg_cfg_6102[751] = cfg_cfg[751], + cfg_cfg_6102[750] = cfg_cfg[750], + cfg_cfg_6102[749] = cfg_cfg[749], + cfg_cfg_6102[748] = cfg_cfg[748], + cfg_cfg_6102[747] = cfg_cfg[747], + cfg_cfg_6102[746] = cfg_cfg[746], + cfg_cfg_6102[745] = cfg_cfg[745], + cfg_cfg_6102[744] = cfg_cfg[744], + cfg_cfg_6102[743] = cfg_cfg[743], + cfg_cfg_6102[742] = cfg_cfg[742], + cfg_cfg_6102[741] = cfg_cfg[741], + cfg_cfg_6102[740] = cfg_cfg[740], + cfg_cfg_6102[739] = cfg_cfg[739], + cfg_cfg_6102[738] = cfg_cfg[738], + cfg_cfg_6102[737] = cfg_cfg[737], + cfg_cfg_6102[736] = cfg_cfg[736], + cfg_cfg_6102[735] = cfg_cfg[735], + cfg_cfg_6102[734] = cfg_cfg[734], + cfg_cfg_6102[733] = cfg_cfg[733], + cfg_cfg_6102[732] = cfg_cfg[732], + cfg_cfg_6102[731] = cfg_cfg[731], + cfg_cfg_6102[730] = cfg_cfg[730], + cfg_cfg_6102[729] = cfg_cfg[729], + cfg_cfg_6102[728] = cfg_cfg[728], + cfg_cfg_6102[727] = cfg_cfg[727], + cfg_cfg_6102[726] = cfg_cfg[726], + cfg_cfg_6102[725] = cfg_cfg[725], + cfg_cfg_6102[724] = cfg_cfg[724], + cfg_cfg_6102[723] = cfg_cfg[723], + cfg_cfg_6102[722] = cfg_cfg[722], + cfg_cfg_6102[721] = cfg_cfg[721], + cfg_cfg_6102[720] = cfg_cfg[720], + cfg_cfg_6102[719] = cfg_cfg[719], + cfg_cfg_6102[718] = cfg_cfg[718], + cfg_cfg_6102[717] = cfg_cfg[717], + cfg_cfg_6102[716] = cfg_cfg[716], + cfg_cfg_6102[715] = cfg_cfg[715], + cfg_cfg_6102[714] = cfg_cfg[714], + cfg_cfg_6102[713] = cfg_cfg[713], + cfg_cfg_6102[712] = cfg_cfg[712], + cfg_cfg_6102[711] = cfg_cfg[711], + cfg_cfg_6102[710] = cfg_cfg[710], + cfg_cfg_6102[709] = cfg_cfg[709], + cfg_cfg_6102[708] = cfg_cfg[708], + cfg_cfg_6102[707] = cfg_cfg[707], + cfg_cfg_6102[706] = cfg_cfg[706], + cfg_cfg_6102[705] = cfg_cfg[705], + cfg_cfg_6102[704] = cfg_cfg[704], + cfg_cfg_6102[703] = cfg_cfg[703], + cfg_cfg_6102[702] = cfg_cfg[702], + cfg_cfg_6102[701] = cfg_cfg[701], + cfg_cfg_6102[700] = cfg_cfg[700], + cfg_cfg_6102[699] = cfg_cfg[699], + cfg_cfg_6102[698] = cfg_cfg[698], + cfg_cfg_6102[697] = cfg_cfg[697], + cfg_cfg_6102[696] = cfg_cfg[696], + cfg_cfg_6102[695] = cfg_cfg[695], + cfg_cfg_6102[694] = cfg_cfg[694], + cfg_cfg_6102[693] = cfg_cfg[693], + cfg_cfg_6102[692] = cfg_cfg[692], + cfg_cfg_6102[691] = cfg_cfg[691], + cfg_cfg_6102[690] = cfg_cfg[690], + cfg_cfg_6102[689] = cfg_cfg[689], + cfg_cfg_6102[688] = cfg_cfg[688], + cfg_cfg_6102[687] = cfg_cfg[687], + cfg_cfg_6102[686] = cfg_cfg[686], + cfg_cfg_6102[685] = cfg_cfg[685], + cfg_cfg_6102[684] = cfg_cfg[684], + cfg_cfg_6102[683] = cfg_cfg[683], + cfg_cfg_6102[682] = cfg_cfg[682], + cfg_cfg_6102[681] = cfg_cfg[681], + cfg_cfg_6102[680] = cfg_cfg[680], + cfg_cfg_6102[679] = cfg_cfg[679], + cfg_cfg_6102[678] = cfg_cfg[678], + cfg_cfg_6102[677] = cfg_cfg[677], + cfg_cfg_6102[676] = cfg_cfg[676], + cfg_cfg_6102[675] = cfg_cfg[675], + cfg_cfg_6102[674] = cfg_cfg[674], + cfg_cfg_6102[673] = cfg_cfg[673], + cfg_cfg_6102[672] = cfg_cfg[672], + cfg_cfg_6102[671] = cfg_cfg[671], + cfg_cfg_6102[670] = cfg_cfg[670], + cfg_cfg_6102[669] = cfg_cfg[669], + cfg_cfg_6102[668] = cfg_cfg[668], + cfg_cfg_6102[667] = cfg_cfg[667], + cfg_cfg_6102[666] = cfg_cfg[666], + cfg_cfg_6102[665] = cfg_cfg[665], + cfg_cfg_6102[664] = cfg_cfg[664], + cfg_cfg_6102[663] = cfg_cfg[663], + cfg_cfg_6102[662] = cfg_cfg[662], + cfg_cfg_6102[661] = cfg_cfg[661], + cfg_cfg_6102[660] = cfg_cfg[660], + cfg_cfg_6102[659] = cfg_cfg[659], + cfg_cfg_6102[658] = cfg_cfg[658], + cfg_cfg_6102[657] = cfg_cfg[657], + cfg_cfg_6102[656] = cfg_cfg[656], + cfg_cfg_6102[655] = cfg_cfg[655], + cfg_cfg_6102[654] = cfg_cfg[654], + cfg_cfg_6102[653] = cfg_cfg[653], + cfg_cfg_6102[652] = cfg_cfg[652], + cfg_cfg_6102[651] = cfg_cfg[651], + cfg_cfg_6102[650] = cfg_cfg[650], + cfg_cfg_6102[649] = cfg_cfg[649], + cfg_cfg_6102[648] = cfg_cfg[648], + cfg_cfg_6102[647] = cfg_cfg[647], + cfg_cfg_6102[646] = cfg_cfg[646], + cfg_cfg_6102[645] = cfg_cfg[645], + cfg_cfg_6102[644] = cfg_cfg[644], + cfg_cfg_6102[643] = cfg_cfg[643], + cfg_cfg_6102[642] = cfg_cfg[642], + cfg_cfg_6102[641] = cfg_cfg[641], + cfg_cfg_6102[640] = cfg_cfg[640], + cfg_cfg_6102[639] = cfg_cfg[639], + cfg_cfg_6102[638] = cfg_cfg[638], + cfg_cfg_6102[637] = cfg_cfg[637], + cfg_cfg_6102[636] = cfg_cfg[636], + cfg_cfg_6102[635] = cfg_cfg[635], + cfg_cfg_6102[634] = cfg_cfg[634], + cfg_cfg_6102[633] = cfg_cfg[633], + cfg_cfg_6102[632] = cfg_cfg[632], + cfg_cfg_6102[631] = cfg_cfg[631], + cfg_cfg_6102[630] = cfg_cfg[630], + cfg_cfg_6102[629] = cfg_cfg[629], + cfg_cfg_6102[628] = cfg_cfg[628], + cfg_cfg_6102[627] = cfg_cfg[627], + cfg_cfg_6102[626] = cfg_cfg[626], + cfg_cfg_6102[625] = cfg_cfg[625], + cfg_cfg_6102[624] = cfg_cfg[624], + cfg_cfg_6102[623] = cfg_cfg[623], + cfg_cfg_6102[622] = cfg_cfg[622], + cfg_cfg_6102[621] = cfg_cfg[621], + cfg_cfg_6102[620] = cfg_cfg[620], + cfg_cfg_6102[619] = cfg_cfg[619], + cfg_cfg_6102[618] = cfg_cfg[618], + cfg_cfg_6102[617] = cfg_cfg[617], + cfg_cfg_6102[616] = cfg_cfg[616], + cfg_cfg_6102[615] = cfg_cfg[615], + cfg_cfg_6102[614] = cfg_cfg[614], + cfg_cfg_6102[613] = cfg_cfg[613], + cfg_cfg_6102[612] = cfg_cfg[612], + cfg_cfg_6102[611] = cfg_cfg[611], + cfg_cfg_6102[610] = cfg_cfg[610], + cfg_cfg_6102[609] = cfg_cfg[609], + cfg_cfg_6102[608] = cfg_cfg[608], + cfg_cfg_6102[607] = cfg_cfg[607], + cfg_cfg_6102[606] = cfg_cfg[606], + cfg_cfg_6102[605] = cfg_cfg[605], + cfg_cfg_6102[604] = cfg_cfg[604], + cfg_cfg_6102[603] = cfg_cfg[603], + cfg_cfg_6102[602] = cfg_cfg[602], + cfg_cfg_6102[601] = cfg_cfg[601], + cfg_cfg_6102[600] = cfg_cfg[600], + cfg_cfg_6102[599] = cfg_cfg[599], + cfg_cfg_6102[598] = cfg_cfg[598], + cfg_cfg_6102[597] = cfg_cfg[597], + cfg_cfg_6102[596] = cfg_cfg[596], + cfg_cfg_6102[595] = cfg_cfg[595], + cfg_cfg_6102[594] = cfg_cfg[594], + cfg_cfg_6102[593] = cfg_cfg[593], + cfg_cfg_6102[592] = cfg_cfg[592], + cfg_cfg_6102[591] = cfg_cfg[591], + cfg_cfg_6102[590] = cfg_cfg[590], + cfg_cfg_6102[589] = cfg_cfg[589], + cfg_cfg_6102[588] = cfg_cfg[588], + cfg_cfg_6102[587] = cfg_cfg[587], + cfg_cfg_6102[586] = cfg_cfg[586], + cfg_cfg_6102[585] = cfg_cfg[585], + cfg_cfg_6102[584] = cfg_cfg[584], + cfg_cfg_6102[583] = cfg_cfg[583], + cfg_cfg_6102[582] = cfg_cfg[582], + cfg_cfg_6102[581] = cfg_cfg[581], + cfg_cfg_6102[580] = cfg_cfg[580], + cfg_cfg_6102[579] = cfg_cfg[579], + cfg_cfg_6102[578] = cfg_cfg[578], + cfg_cfg_6102[577] = cfg_cfg[577], + cfg_cfg_6102[576] = cfg_cfg[576], + cfg_cfg_6102[575] = cfg_cfg[575], + cfg_cfg_6102[574] = cfg_cfg[574], + cfg_cfg_6102[573] = cfg_cfg[573], + cfg_cfg_6102[572] = cfg_cfg[572], + cfg_cfg_6102[571] = cfg_cfg[571], + cfg_cfg_6102[570] = cfg_cfg[570], + cfg_cfg_6102[569] = cfg_cfg[569], + cfg_cfg_6102[568] = cfg_cfg[568], + cfg_cfg_6102[567] = cfg_cfg[567], + cfg_cfg_6102[566] = cfg_cfg[566], + cfg_cfg_6102[565] = cfg_cfg[565], + cfg_cfg_6102[564] = cfg_cfg[564], + cfg_cfg_6102[563] = cfg_cfg[563], + cfg_cfg_6102[562] = cfg_cfg[562], + cfg_cfg_6102[561] = cfg_cfg[561], + cfg_cfg_6102[560] = cfg_cfg[560], + cfg_cfg_6102[559] = cfg_cfg[559], + cfg_cfg_6102[558] = cfg_cfg[558], + cfg_cfg_6102[557] = cfg_cfg[557], + cfg_cfg_6102[556] = cfg_cfg[556], + cfg_cfg_6102[555] = cfg_cfg[555], + cfg_cfg_6102[554] = cfg_cfg[554], + cfg_cfg_6102[553] = cfg_cfg[553], + cfg_cfg_6102[552] = cfg_cfg[552], + cfg_cfg_6102[551] = cfg_cfg[551], + cfg_cfg_6102[550] = cfg_cfg[550], + cfg_cfg_6102[549] = cfg_cfg[549], + cfg_cfg_6102[548] = cfg_cfg[548], + cfg_cfg_6102[547] = cfg_cfg[547], + cfg_cfg_6102[546] = cfg_cfg[546], + cfg_cfg_6102[545] = cfg_cfg[545], + cfg_cfg_6102[544] = cfg_cfg[544], + cfg_cfg_6102[543] = cfg_cfg[543], + cfg_cfg_6102[542] = cfg_cfg[542], + cfg_cfg_6102[541] = cfg_cfg[541], + cfg_cfg_6102[540] = cfg_cfg[540], + cfg_cfg_6102[539] = cfg_cfg[539], + cfg_cfg_6102[538] = cfg_cfg[538], + cfg_cfg_6102[537] = cfg_cfg[537], + cfg_cfg_6102[536] = cfg_cfg[536], + cfg_cfg_6102[535] = cfg_cfg[535], + cfg_cfg_6102[534] = cfg_cfg[534], + cfg_cfg_6102[533] = cfg_cfg[533], + cfg_cfg_6102[532] = cfg_cfg[532], + cfg_cfg_6102[531] = cfg_cfg[531], + cfg_cfg_6102[530] = cfg_cfg[530], + cfg_cfg_6102[529] = cfg_cfg[529], + cfg_cfg_6102[528] = cfg_cfg[528], + cfg_cfg_6102[527] = cfg_cfg[527], + cfg_cfg_6102[526] = cfg_cfg[526], + cfg_cfg_6102[525] = cfg_cfg[525], + cfg_cfg_6102[524] = cfg_cfg[524], + cfg_cfg_6102[523] = cfg_cfg[523], + cfg_cfg_6102[522] = cfg_cfg[522], + cfg_cfg_6102[521] = cfg_cfg[521], + cfg_cfg_6102[520] = cfg_cfg[520], + cfg_cfg_6102[519] = cfg_cfg[519], + cfg_cfg_6102[518] = cfg_cfg[518], + cfg_cfg_6102[517] = cfg_cfg[517], + cfg_cfg_6102[516] = cfg_cfg[516], + cfg_cfg_6102[515] = cfg_cfg[515], + cfg_cfg_6102[514] = cfg_cfg[514], + cfg_cfg_6102[513] = cfg_cfg[513], + cfg_cfg_6102[512] = cfg_cfg[512], + cfg_cfg_6102[511] = cfg_cfg[511], + cfg_cfg_6102[510] = cfg_cfg[510], + cfg_cfg_6102[509] = cfg_cfg[509], + cfg_cfg_6102[508] = cfg_cfg[508], + cfg_cfg_6102[507] = cfg_cfg[507], + cfg_cfg_6102[506] = cfg_cfg[506], + cfg_cfg_6102[505] = cfg_cfg[505], + cfg_cfg_6102[504] = cfg_cfg[504], + cfg_cfg_6102[503] = cfg_cfg[503], + cfg_cfg_6102[502] = cfg_cfg[502], + cfg_cfg_6102[501] = cfg_cfg[501], + cfg_cfg_6102[500] = cfg_cfg[500], + cfg_cfg_6102[499] = cfg_cfg[499], + cfg_cfg_6102[498] = cfg_cfg[498], + cfg_cfg_6102[497] = cfg_cfg[497], + cfg_cfg_6102[496] = cfg_cfg[496], + cfg_cfg_6102[495] = cfg_cfg[495], + cfg_cfg_6102[494] = cfg_cfg[494], + cfg_cfg_6102[493] = cfg_cfg[493], + cfg_cfg_6102[492] = cfg_cfg[492], + cfg_cfg_6102[491] = cfg_cfg[491], + cfg_cfg_6102[490] = cfg_cfg[490], + cfg_cfg_6102[489] = cfg_cfg[489], + cfg_cfg_6102[488] = cfg_cfg[488], + cfg_cfg_6102[487] = cfg_cfg[487], + cfg_cfg_6102[486] = cfg_cfg[486], + cfg_cfg_6102[485] = cfg_cfg[485], + cfg_cfg_6102[484] = cfg_cfg[484], + cfg_cfg_6102[483] = cfg_cfg[483], + cfg_cfg_6102[482] = cfg_cfg[482], + cfg_cfg_6102[481] = cfg_cfg[481], + cfg_cfg_6102[480] = cfg_cfg[480], + cfg_cfg_6102[479] = cfg_cfg[479], + cfg_cfg_6102[478] = cfg_cfg[478], + cfg_cfg_6102[477] = cfg_cfg[477], + cfg_cfg_6102[476] = cfg_cfg[476], + cfg_cfg_6102[475] = cfg_cfg[475], + cfg_cfg_6102[474] = cfg_cfg[474], + cfg_cfg_6102[473] = cfg_cfg[473], + cfg_cfg_6102[472] = cfg_cfg[472], + cfg_cfg_6102[471] = cfg_cfg[471], + cfg_cfg_6102[470] = cfg_cfg[470], + cfg_cfg_6102[469] = cfg_cfg[469], + cfg_cfg_6102[468] = cfg_cfg[468], + cfg_cfg_6102[467] = cfg_cfg[467], + cfg_cfg_6102[466] = cfg_cfg[466], + cfg_cfg_6102[465] = cfg_cfg[465], + cfg_cfg_6102[464] = cfg_cfg[464], + cfg_cfg_6102[463] = cfg_cfg[463], + cfg_cfg_6102[462] = cfg_cfg[462], + cfg_cfg_6102[461] = cfg_cfg[461], + cfg_cfg_6102[460] = cfg_cfg[460], + cfg_cfg_6102[459] = cfg_cfg[459], + cfg_cfg_6102[458] = cfg_cfg[458], + cfg_cfg_6102[457] = cfg_cfg[457], + cfg_cfg_6102[456] = cfg_cfg[456], + cfg_cfg_6102[455] = cfg_cfg[455], + cfg_cfg_6102[454] = cfg_cfg[454], + cfg_cfg_6102[453] = cfg_cfg[453], + cfg_cfg_6102[452] = cfg_cfg[452], + cfg_cfg_6102[451] = cfg_cfg[451], + cfg_cfg_6102[450] = cfg_cfg[450], + cfg_cfg_6102[449] = cfg_cfg[449], + cfg_cfg_6102[448] = cfg_cfg[448], + cfg_cfg_6102[447] = cfg_cfg[447], + cfg_cfg_6102[446] = cfg_cfg[446], + cfg_cfg_6102[445] = cfg_cfg[445], + cfg_cfg_6102[444] = cfg_cfg[444], + cfg_cfg_6102[443] = cfg_cfg[443], + cfg_cfg_6102[442] = cfg_cfg[442], + cfg_cfg_6102[441] = cfg_cfg[441], + cfg_cfg_6102[440] = cfg_cfg[440], + cfg_cfg_6102[439] = cfg_cfg[439], + cfg_cfg_6102[438] = cfg_cfg[438], + cfg_cfg_6102[437] = cfg_cfg[437], + cfg_cfg_6102[436] = cfg_cfg[436], + cfg_cfg_6102[435] = cfg_cfg[435], + cfg_cfg_6102[434] = cfg_cfg[434], + cfg_cfg_6102[433] = cfg_cfg[433], + cfg_cfg_6102[432] = cfg_cfg[432], + cfg_cfg_6102[431] = cfg_cfg[431], + cfg_cfg_6102[430] = cfg_cfg[430], + cfg_cfg_6102[429] = cfg_cfg[429], + cfg_cfg_6102[428] = cfg_cfg[428], + cfg_cfg_6102[427] = cfg_cfg[427], + cfg_cfg_6102[426] = cfg_cfg[426], + cfg_cfg_6102[425] = cfg_cfg[425], + cfg_cfg_6102[424] = cfg_cfg[424], + cfg_cfg_6102[423] = cfg_cfg[423], + cfg_cfg_6102[422] = cfg_cfg[422], + cfg_cfg_6102[421] = cfg_cfg[421], + cfg_cfg_6102[420] = cfg_cfg[420], + cfg_cfg_6102[419] = cfg_cfg[419], + cfg_cfg_6102[418] = cfg_cfg[418], + cfg_cfg_6102[417] = cfg_cfg[417], + cfg_cfg_6102[416] = cfg_cfg[416], + cfg_cfg_6102[415] = cfg_cfg[415], + cfg_cfg_6102[414] = cfg_cfg[414], + cfg_cfg_6102[413] = cfg_cfg[413], + cfg_cfg_6102[412] = cfg_cfg[412], + cfg_cfg_6102[411] = cfg_cfg[411], + cfg_cfg_6102[410] = cfg_cfg[410], + cfg_cfg_6102[409] = cfg_cfg[409], + cfg_cfg_6102[408] = cfg_cfg[408], + cfg_cfg_6102[407] = cfg_cfg[407], + cfg_cfg_6102[406] = cfg_cfg[406], + cfg_cfg_6102[405] = cfg_cfg[405], + cfg_cfg_6102[404] = cfg_cfg[404], + cfg_cfg_6102[403] = cfg_cfg[403], + cfg_cfg_6102[402] = cfg_cfg[402], + cfg_cfg_6102[401] = cfg_cfg[401], + cfg_cfg_6102[400] = cfg_cfg[400], + cfg_cfg_6102[399] = cfg_cfg[399], + cfg_cfg_6102[398] = cfg_cfg[398], + cfg_cfg_6102[397] = cfg_cfg[397], + cfg_cfg_6102[396] = cfg_cfg[396], + cfg_cfg_6102[395] = cfg_cfg[395], + cfg_cfg_6102[394] = cfg_cfg[394], + cfg_cfg_6102[393] = cfg_cfg[393], + cfg_cfg_6102[392] = cfg_cfg[392], + cfg_cfg_6102[391] = cfg_cfg[391], + cfg_cfg_6102[390] = cfg_cfg[390], + cfg_cfg_6102[389] = cfg_cfg[389], + cfg_cfg_6102[388] = cfg_cfg[388], + cfg_cfg_6102[387] = cfg_cfg[387], + cfg_cfg_6102[386] = cfg_cfg[386], + cfg_cfg_6102[385] = cfg_cfg[385], + cfg_cfg_6102[384] = cfg_cfg[384], + cfg_cfg_6102[383] = cfg_cfg[383], + cfg_cfg_6102[382] = cfg_cfg[382], + cfg_cfg_6102[381] = cfg_cfg[381], + cfg_cfg_6102[380] = cfg_cfg[380], + cfg_cfg_6102[379] = cfg_cfg[379], + cfg_cfg_6102[378] = cfg_cfg[378], + cfg_cfg_6102[377] = cfg_cfg[377], + cfg_cfg_6102[376] = cfg_cfg[376], + cfg_cfg_6102[375] = cfg_cfg[375], + cfg_cfg_6102[374] = cfg_cfg[374], + cfg_cfg_6102[373] = cfg_cfg[373], + cfg_cfg_6102[372] = cfg_cfg[372], + cfg_cfg_6102[371] = cfg_cfg[371], + cfg_cfg_6102[370] = cfg_cfg[370], + cfg_cfg_6102[369] = cfg_cfg[369], + cfg_cfg_6102[368] = cfg_cfg[368], + cfg_cfg_6102[367] = cfg_cfg[367], + cfg_cfg_6102[366] = cfg_cfg[366], + cfg_cfg_6102[365] = cfg_cfg[365], + cfg_cfg_6102[364] = cfg_cfg[364], + cfg_cfg_6102[363] = cfg_cfg[363], + cfg_cfg_6102[362] = cfg_cfg[362], + cfg_cfg_6102[361] = cfg_cfg[361], + cfg_cfg_6102[360] = cfg_cfg[360], + cfg_cfg_6102[359] = cfg_cfg[359], + cfg_cfg_6102[358] = cfg_cfg[358], + cfg_cfg_6102[357] = cfg_cfg[357], + cfg_cfg_6102[356] = cfg_cfg[356], + cfg_cfg_6102[355] = cfg_cfg[355], + cfg_cfg_6102[354] = cfg_cfg[354], + cfg_cfg_6102[353] = cfg_cfg[353], + cfg_cfg_6102[352] = cfg_cfg[352], + cfg_cfg_6102[351] = cfg_cfg[351], + cfg_cfg_6102[350] = cfg_cfg[350], + cfg_cfg_6102[349] = cfg_cfg[349], + cfg_cfg_6102[348] = cfg_cfg[348], + cfg_cfg_6102[347] = cfg_cfg[347], + cfg_cfg_6102[346] = cfg_cfg[346], + cfg_cfg_6102[345] = cfg_cfg[345], + cfg_cfg_6102[344] = cfg_cfg[344], + cfg_cfg_6102[343] = cfg_cfg[343], + cfg_cfg_6102[342] = cfg_cfg[342], + cfg_cfg_6102[341] = cfg_cfg[341], + cfg_cfg_6102[340] = cfg_cfg[340], + cfg_cfg_6102[339] = cfg_cfg[339], + cfg_cfg_6102[338] = cfg_cfg[338], + cfg_cfg_6102[337] = cfg_cfg[337], + cfg_cfg_6102[336] = cfg_cfg[336], + cfg_cfg_6102[335] = cfg_cfg[335], + cfg_cfg_6102[334] = cfg_cfg[334], + cfg_cfg_6102[333] = cfg_cfg[333], + cfg_cfg_6102[332] = cfg_cfg[332], + cfg_cfg_6102[331] = cfg_cfg[331], + cfg_cfg_6102[330] = cfg_cfg[330], + cfg_cfg_6102[329] = cfg_cfg[329], + cfg_cfg_6102[328] = cfg_cfg[328], + cfg_cfg_6102[327] = cfg_cfg[327], + cfg_cfg_6102[326] = cfg_cfg[326], + cfg_cfg_6102[325] = cfg_cfg[325], + cfg_cfg_6102[324] = cfg_cfg[324], + cfg_cfg_6102[323] = cfg_cfg[323], + cfg_cfg_6102[322] = cfg_cfg[322], + cfg_cfg_6102[321] = cfg_cfg[321], + cfg_cfg_6102[320] = cfg_cfg[320], + cfg_cfg_6102[319] = cfg_cfg[319], + cfg_cfg_6102[318] = cfg_cfg[318], + cfg_cfg_6102[317] = cfg_cfg[317], + cfg_cfg_6102[316] = cfg_cfg[316], + cfg_cfg_6102[315] = cfg_cfg[315], + cfg_cfg_6102[314] = cfg_cfg[314], + cfg_cfg_6102[313] = cfg_cfg[313], + cfg_cfg_6102[312] = cfg_cfg[312], + cfg_cfg_6102[311] = cfg_cfg[311], + cfg_cfg_6102[310] = cfg_cfg[310], + cfg_cfg_6102[309] = cfg_cfg[309], + cfg_cfg_6102[308] = cfg_cfg[308], + cfg_cfg_6102[307] = cfg_cfg[307], + cfg_cfg_6102[306] = cfg_cfg[306], + cfg_cfg_6102[305] = cfg_cfg[305], + cfg_cfg_6102[304] = cfg_cfg[304], + cfg_cfg_6102[303] = cfg_cfg[303], + cfg_cfg_6102[302] = cfg_cfg[302], + cfg_cfg_6102[301] = cfg_cfg[301], + cfg_cfg_6102[300] = cfg_cfg[300], + cfg_cfg_6102[299] = cfg_cfg[299], + cfg_cfg_6102[298] = cfg_cfg[298], + cfg_cfg_6102[297] = cfg_cfg[297], + cfg_cfg_6102[296] = cfg_cfg[296], + cfg_cfg_6102[295] = cfg_cfg[295], + cfg_cfg_6102[294] = cfg_cfg[294], + cfg_cfg_6102[293] = cfg_cfg[293], + cfg_cfg_6102[292] = cfg_cfg[292], + cfg_cfg_6102[291] = cfg_cfg[291], + cfg_cfg_6102[290] = cfg_cfg[290], + cfg_cfg_6102[289] = cfg_cfg[289], + cfg_cfg_6102[288] = cfg_cfg[288], + cfg_cfg_6102[287] = cfg_cfg[287], + cfg_cfg_6102[286] = cfg_cfg[286], + cfg_cfg_6102[285] = cfg_cfg[285], + cfg_cfg_6102[284] = cfg_cfg[284], + cfg_cfg_6102[283] = cfg_cfg[283], + cfg_cfg_6102[282] = cfg_cfg[282], + cfg_cfg_6102[281] = cfg_cfg[281], + cfg_cfg_6102[280] = cfg_cfg[280], + cfg_cfg_6102[279] = cfg_cfg[279], + cfg_cfg_6102[278] = cfg_cfg[278], + cfg_cfg_6102[277] = cfg_cfg[277], + cfg_cfg_6102[276] = cfg_cfg[276], + cfg_cfg_6102[275] = cfg_cfg[275], + cfg_cfg_6102[274] = cfg_cfg[274], + cfg_cfg_6102[273] = cfg_cfg[273], + cfg_cfg_6102[272] = cfg_cfg[272], + cfg_cfg_6102[271] = cfg_cfg[271], + cfg_cfg_6102[270] = cfg_cfg[270], + cfg_cfg_6102[269] = cfg_cfg[269], + cfg_cfg_6102[268] = cfg_cfg[268], + cfg_cfg_6102[267] = cfg_cfg[267], + cfg_cfg_6102[266] = cfg_cfg[266], + cfg_cfg_6102[265] = cfg_cfg[265], + cfg_cfg_6102[264] = cfg_cfg[264], + cfg_cfg_6102[263] = cfg_cfg[263], + cfg_cfg_6102[262] = cfg_cfg[262], + cfg_cfg_6102[261] = cfg_cfg[261], + cfg_cfg_6102[260] = cfg_cfg[260], + cfg_cfg_6102[259] = cfg_cfg[259], + cfg_cfg_6102[258] = cfg_cfg[258], + cfg_cfg_6102[257] = cfg_cfg[257], + cfg_cfg_6102[256] = cfg_cfg[256], + cfg_cfg_6102[255] = cfg_cfg[255], + cfg_cfg_6102[254] = cfg_cfg[254], + cfg_cfg_6102[253] = cfg_cfg[253], + cfg_cfg_6102[252] = cfg_cfg[252], + cfg_cfg_6102[251] = cfg_cfg[251], + cfg_cfg_6102[250] = cfg_cfg[250], + cfg_cfg_6102[249] = cfg_cfg[249], + cfg_cfg_6102[248] = cfg_cfg[248], + cfg_cfg_6102[247] = cfg_cfg[247], + cfg_cfg_6102[246] = cfg_cfg[246], + cfg_cfg_6102[245] = cfg_cfg[245], + cfg_cfg_6102[244] = cfg_cfg[244], + cfg_cfg_6102[243] = cfg_cfg[243], + cfg_cfg_6102[242] = cfg_cfg[242], + cfg_cfg_6102[241] = cfg_cfg[241], + cfg_cfg_6102[240] = cfg_cfg[240], + cfg_cfg_6102[239] = cfg_cfg[239], + cfg_cfg_6102[238] = cfg_cfg[238], + cfg_cfg_6102[237] = cfg_cfg[237], + cfg_cfg_6102[236] = cfg_cfg[236], + cfg_cfg_6102[235] = cfg_cfg[235], + cfg_cfg_6102[234] = cfg_cfg[234], + cfg_cfg_6102[233] = cfg_cfg[233], + cfg_cfg_6102[232] = cfg_cfg[232], + cfg_cfg_6102[231] = cfg_cfg[231], + cfg_cfg_6102[230] = cfg_cfg[230], + cfg_cfg_6102[229] = cfg_cfg[229], + cfg_cfg_6102[228] = cfg_cfg[228], + cfg_cfg_6102[227] = cfg_cfg[227], + cfg_cfg_6102[226] = cfg_cfg[226], + cfg_cfg_6102[225] = cfg_cfg[225], + cfg_cfg_6102[224] = cfg_cfg[224], + cfg_cfg_6102[223] = cfg_cfg[223], + cfg_cfg_6102[222] = cfg_cfg[222], + cfg_cfg_6102[221] = cfg_cfg[221], + cfg_cfg_6102[220] = cfg_cfg[220], + cfg_cfg_6102[219] = cfg_cfg[219], + cfg_cfg_6102[218] = cfg_cfg[218], + cfg_cfg_6102[217] = cfg_cfg[217], + cfg_cfg_6102[216] = cfg_cfg[216], + cfg_cfg_6102[215] = cfg_cfg[215], + cfg_cfg_6102[214] = cfg_cfg[214], + cfg_cfg_6102[213] = cfg_cfg[213], + cfg_cfg_6102[212] = cfg_cfg[212], + cfg_cfg_6102[211] = cfg_cfg[211], + cfg_cfg_6102[210] = cfg_cfg[210], + cfg_cfg_6102[209] = cfg_cfg[209], + cfg_cfg_6102[208] = cfg_cfg[208], + cfg_cfg_6102[207] = cfg_cfg[207], + cfg_cfg_6102[206] = cfg_cfg[206], + cfg_cfg_6102[205] = cfg_cfg[205], + cfg_cfg_6102[204] = cfg_cfg[204], + cfg_cfg_6102[203] = cfg_cfg[203], + cfg_cfg_6102[202] = cfg_cfg[202], + cfg_cfg_6102[201] = cfg_cfg[201], + cfg_cfg_6102[200] = cfg_cfg[200], + cfg_cfg_6102[199] = cfg_cfg[199], + cfg_cfg_6102[198] = cfg_cfg[198], + cfg_cfg_6102[197] = cfg_cfg[197], + cfg_cfg_6102[196] = cfg_cfg[196], + cfg_cfg_6102[195] = cfg_cfg[195], + cfg_cfg_6102[194] = cfg_cfg[194], + cfg_cfg_6102[193] = cfg_cfg[193], + cfg_cfg_6102[192] = cfg_cfg[192], + cfg_cfg_6102[191] = cfg_cfg[191], + cfg_cfg_6102[190] = cfg_cfg[190], + cfg_cfg_6102[189] = cfg_cfg[189], + cfg_cfg_6102[188] = cfg_cfg[188], + cfg_cfg_6102[187] = cfg_cfg[187], + cfg_cfg_6102[186] = cfg_cfg[186], + cfg_cfg_6102[185] = cfg_cfg[185], + cfg_cfg_6102[184] = cfg_cfg[184], + cfg_cfg_6102[183] = cfg_cfg[183], + cfg_cfg_6102[182] = cfg_cfg[182], + cfg_cfg_6102[181] = cfg_cfg[181], + cfg_cfg_6102[180] = cfg_cfg[180], + cfg_cfg_6102[179] = cfg_cfg[179], + cfg_cfg_6102[178] = cfg_cfg[178], + cfg_cfg_6102[177] = cfg_cfg[177], + cfg_cfg_6102[176] = cfg_cfg[176], + cfg_cfg_6102[175] = cfg_cfg[175], + cfg_cfg_6102[174] = cfg_cfg[174], + cfg_cfg_6102[173] = cfg_cfg[173], + cfg_cfg_6102[172] = cfg_cfg[172], + cfg_cfg_6102[171] = cfg_cfg[171], + cfg_cfg_6102[170] = cfg_cfg[170], + cfg_cfg_6102[169] = cfg_cfg[169], + cfg_cfg_6102[168] = cfg_cfg[168], + cfg_cfg_6102[167] = cfg_cfg[167], + cfg_cfg_6102[166] = cfg_cfg[166], + cfg_cfg_6102[165] = cfg_cfg[165], + cfg_cfg_6102[164] = cfg_cfg[164], + cfg_cfg_6102[163] = cfg_cfg[163], + cfg_cfg_6102[162] = cfg_cfg[162], + cfg_cfg_6102[161] = cfg_cfg[161], + cfg_cfg_6102[160] = cfg_cfg[160], + cfg_cfg_6102[159] = cfg_cfg[159], + cfg_cfg_6102[158] = cfg_cfg[158], + cfg_cfg_6102[157] = cfg_cfg[157], + cfg_cfg_6102[156] = cfg_cfg[156], + cfg_cfg_6102[155] = cfg_cfg[155], + cfg_cfg_6102[154] = cfg_cfg[154], + cfg_cfg_6102[153] = cfg_cfg[153], + cfg_cfg_6102[152] = cfg_cfg[152], + cfg_cfg_6102[151] = cfg_cfg[151], + cfg_cfg_6102[150] = cfg_cfg[150], + cfg_cfg_6102[149] = cfg_cfg[149], + cfg_cfg_6102[148] = cfg_cfg[148], + cfg_cfg_6102[147] = cfg_cfg[147], + cfg_cfg_6102[146] = cfg_cfg[146], + cfg_cfg_6102[145] = cfg_cfg[145], + cfg_cfg_6102[144] = cfg_cfg[144], + cfg_cfg_6102[143] = cfg_cfg[143], + cfg_cfg_6102[142] = cfg_cfg[142], + cfg_cfg_6102[141] = cfg_cfg[141], + cfg_cfg_6102[140] = cfg_cfg[140], + cfg_cfg_6102[139] = cfg_cfg[139], + cfg_cfg_6102[138] = cfg_cfg[138], + cfg_cfg_6102[137] = cfg_cfg[137], + cfg_cfg_6102[136] = cfg_cfg[136], + cfg_cfg_6102[135] = cfg_cfg[135], + cfg_cfg_6102[134] = cfg_cfg[134], + cfg_cfg_6102[133] = cfg_cfg[133], + cfg_cfg_6102[132] = cfg_cfg[132], + cfg_cfg_6102[131] = cfg_cfg[131], + cfg_cfg_6102[130] = cfg_cfg[130], + cfg_cfg_6102[129] = cfg_cfg[129], + cfg_cfg_6102[128] = cfg_cfg[128], + cfg_cfg_6102[127] = cfg_cfg[127], + cfg_cfg_6102[126] = cfg_cfg[126], + cfg_cfg_6102[125] = cfg_cfg[125], + cfg_cfg_6102[124] = cfg_cfg[124], + cfg_cfg_6102[123] = cfg_cfg[123], + cfg_cfg_6102[122] = cfg_cfg[122], + cfg_cfg_6102[121] = cfg_cfg[121], + cfg_cfg_6102[120] = cfg_cfg[120], + cfg_cfg_6102[119] = cfg_cfg[119], + cfg_cfg_6102[118] = cfg_cfg[118], + cfg_cfg_6102[117] = cfg_cfg[117], + cfg_cfg_6102[116] = cfg_cfg[116], + cfg_cfg_6102[115] = cfg_cfg[115], + cfg_cfg_6102[114] = cfg_cfg[114], + cfg_cfg_6102[113] = cfg_cfg[113], + cfg_cfg_6102[112] = cfg_cfg[112], + cfg_cfg_6102[111] = cfg_cfg[111], + cfg_cfg_6102[110] = cfg_cfg[110], + cfg_cfg_6102[109] = cfg_cfg[109], + cfg_cfg_6102[108] = cfg_cfg[108], + cfg_cfg_6102[107] = cfg_cfg[107], + cfg_cfg_6102[106] = cfg_cfg[106], + cfg_cfg_6102[105] = cfg_cfg[105], + cfg_cfg_6102[104] = cfg_cfg[104], + cfg_cfg_6102[103] = cfg_cfg[103], + cfg_cfg_6102[102] = cfg_cfg[102], + cfg_cfg_6102[101] = cfg_cfg[101], + cfg_cfg_6102[100] = cfg_cfg[100], + cfg_cfg_6102[99] = cfg_cfg[99], + cfg_cfg_6102[98] = cfg_cfg[98], + cfg_cfg_6102[97] = cfg_cfg[97], + cfg_cfg_6102[96] = cfg_cfg[96], + cfg_cfg_6102[95] = cfg_cfg[95], + cfg_cfg_6102[94] = cfg_cfg[94], + cfg_cfg_6102[93] = cfg_cfg[93], + cfg_cfg_6102[92] = cfg_cfg[92], + cfg_cfg_6102[91] = cfg_cfg[91], + cfg_cfg_6102[90] = cfg_cfg[90], + cfg_cfg_6102[89] = cfg_cfg[89], + cfg_cfg_6102[88] = cfg_cfg[88], + cfg_cfg_6102[87] = cfg_cfg[87], + cfg_cfg_6102[86] = cfg_cfg[86], + cfg_cfg_6102[85] = cfg_cfg[85], + cfg_cfg_6102[84] = cfg_cfg[84], + cfg_cfg_6102[83] = cfg_cfg[83], + cfg_cfg_6102[82] = cfg_cfg[82], + cfg_cfg_6102[81] = cfg_cfg[81], + cfg_cfg_6102[80] = cfg_cfg[80], + cfg_cfg_6102[79] = cfg_cfg[79], + cfg_cfg_6102[78] = cfg_cfg[78], + cfg_cfg_6102[77] = cfg_cfg[77], + cfg_cfg_6102[76] = cfg_cfg[76], + cfg_cfg_6102[75] = cfg_cfg[75], + cfg_cfg_6102[74] = cfg_cfg[74], + cfg_cfg_6102[73] = cfg_cfg[73], + cfg_cfg_6102[72] = cfg_cfg[72], + cfg_cfg_6102[71] = cfg_cfg[71], + cfg_cfg_6102[70] = cfg_cfg[70], + cfg_cfg_6102[69] = cfg_cfg[69], + cfg_cfg_6102[68] = cfg_cfg[68], + cfg_cfg_6102[67] = cfg_cfg[67], + cfg_cfg_6102[66] = cfg_cfg[66], + cfg_cfg_6102[65] = cfg_cfg[65], + cfg_cfg_6102[64] = cfg_cfg[64], + cfg_cfg_6102[63] = cfg_cfg[63], + cfg_cfg_6102[62] = cfg_cfg[62], + cfg_cfg_6102[61] = cfg_cfg[61], + cfg_cfg_6102[60] = cfg_cfg[60], + cfg_cfg_6102[59] = cfg_cfg[59], + cfg_cfg_6102[58] = cfg_cfg[58], + cfg_cfg_6102[57] = cfg_cfg[57], + cfg_cfg_6102[56] = cfg_cfg[56], + cfg_cfg_6102[55] = cfg_cfg[55], + cfg_cfg_6102[54] = cfg_cfg[54], + cfg_cfg_6102[53] = cfg_cfg[53], + cfg_cfg_6102[52] = cfg_cfg[52], + cfg_cfg_6102[51] = cfg_cfg[51], + cfg_cfg_6102[50] = cfg_cfg[50], + cfg_cfg_6102[49] = cfg_cfg[49], + cfg_cfg_6102[48] = cfg_cfg[48], + cfg_cfg_6102[47] = cfg_cfg[47], + cfg_cfg_6102[46] = cfg_cfg[46], + cfg_cfg_6102[45] = cfg_cfg[45], + cfg_cfg_6102[44] = cfg_cfg[44], + cfg_cfg_6102[43] = cfg_cfg[43], + cfg_cfg_6102[42] = cfg_cfg[42], + cfg_cfg_6102[41] = cfg_cfg[41], + cfg_cfg_6102[40] = cfg_cfg[40], + cfg_cfg_6102[39] = cfg_cfg[39], + cfg_cfg_6102[38] = cfg_cfg[38], + cfg_cfg_6102[37] = cfg_cfg[37], + cfg_cfg_6102[36] = cfg_cfg[36], + cfg_cfg_6102[35] = cfg_cfg[35], + cfg_cfg_6102[34] = cfg_cfg[34], + cfg_cfg_6102[33] = cfg_cfg[33], + cfg_cfg_6102[32] = cfg_cfg[32], + cfg_cfg_6102[31] = cfg_cfg[31], + cfg_cfg_6102[30] = cfg_cfg[30], + cfg_cfg_6102[29] = cfg_cfg[29], + cfg_cfg_6102[28] = cfg_cfg[28], + cfg_cfg_6102[27] = cfg_cfg[27], + cfg_cfg_6102[26] = cfg_cfg[26], + cfg_cfg_6102[25] = cfg_cfg[25], + cfg_cfg_6102[24] = cfg_cfg[24], + cfg_cfg_6102[23] = cfg_cfg[23], + cfg_cfg_6102[22] = cfg_cfg[22], + cfg_cfg_6102[21] = cfg_cfg[21], + cfg_cfg_6102[20] = cfg_cfg[20], + cfg_cfg_6102[19] = cfg_cfg[19], + cfg_cfg_6102[18] = cfg_cfg[18], + cfg_cfg_6102[17] = cfg_cfg[17], + cfg_cfg_6102[16] = cfg_cfg[16], + cfg_cfg_6102[15] = cfg_cfg[15], + cfg_cfg_6102[14] = cfg_cfg[14], + cfg_cfg_6102[13] = cfg_cfg[13], + cfg_cfg_6102[12] = cfg_cfg[12], + cfg_cfg_6102[11] = cfg_cfg[11], + cfg_cfg_6102[10] = cfg_cfg[10], + cfg_cfg_6102[9] = cfg_cfg[9], + cfg_cfg_6102[8] = cfg_cfg[8], + cfg_cfg_6102[7] = cfg_cfg[7], + cfg_cfg_6102[6] = cfg_cfg[6], + cfg_cfg_6102[5] = cfg_cfg[5], + cfg_cfg_6102[4] = cfg_cfg[4], + cfg_cfg_6102[3] = cfg_cfg[3], + cfg_cfg_6102[2] = cfg_cfg[2], + cfg_cfg_6102[1] = cfg_cfg[1], + cfg_cfg_6102[0] = cfg_cfg[0], + cfg_di_6097[31] = cfg_di[31], + cfg_di_6097[30] = cfg_di[30], + cfg_di_6097[29] = cfg_di[29], + cfg_di_6097[28] = cfg_di[28], + cfg_di_6097[27] = cfg_di[27], + cfg_di_6097[26] = cfg_di[26], + cfg_di_6097[25] = cfg_di[25], + cfg_di_6097[24] = cfg_di[24], + cfg_di_6097[23] = cfg_di[23], + cfg_di_6097[22] = cfg_di[22], + cfg_di_6097[21] = cfg_di[21], + cfg_di_6097[20] = cfg_di[20], + cfg_di_6097[19] = cfg_di[19], + cfg_di_6097[18] = cfg_di[18], + cfg_di_6097[17] = cfg_di[17], + cfg_di_6097[16] = cfg_di[16], + cfg_di_6097[15] = cfg_di[15], + cfg_di_6097[14] = cfg_di[14], + cfg_di_6097[13] = cfg_di[13], + cfg_di_6097[12] = cfg_di[12], + cfg_di_6097[11] = cfg_di[11], + cfg_di_6097[10] = cfg_di[10], + cfg_di_6097[9] = cfg_di[9], + cfg_di_6097[8] = cfg_di[8], + cfg_di_6097[7] = cfg_di[7], + cfg_di_6097[6] = cfg_di[6], + cfg_di_6097[5] = cfg_di[5], + cfg_di_6097[4] = cfg_di[4], + cfg_di_6097[3] = cfg_di[3], + cfg_di_6097[2] = cfg_di[2], + cfg_di_6097[1] = cfg_di[1], + cfg_di_6097[0] = cfg_di[0], + cfg_do[31] = cfg_do_6096[31], + cfg_do[30] = cfg_do_6096[30], + cfg_do[29] = cfg_do_6096[29], + cfg_do[28] = cfg_do_6096[28], + cfg_do[27] = cfg_do_6096[27], + cfg_do[26] = cfg_do_6096[26], + cfg_do[25] = cfg_do_6096[25], + cfg_do[24] = cfg_do_6096[24], + cfg_do[23] = cfg_do_6096[23], + cfg_do[22] = cfg_do_6096[22], + cfg_do[21] = cfg_do_6096[21], + cfg_do[20] = cfg_do_6096[20], + cfg_do[19] = cfg_do_6096[19], + cfg_do[18] = cfg_do_6096[18], + cfg_do[17] = cfg_do_6096[17], + cfg_do[16] = cfg_do_6096[16], + cfg_do[15] = cfg_do_6096[15], + cfg_do[14] = cfg_do_6096[14], + cfg_do[13] = cfg_do_6096[13], + cfg_do[12] = cfg_do_6096[12], + cfg_do[11] = cfg_do_6096[11], + cfg_do[10] = cfg_do_6096[10], + cfg_do[9] = cfg_do_6096[9], + cfg_do[8] = cfg_do_6096[8], + cfg_do[7] = cfg_do_6096[7], + cfg_do[6] = cfg_do_6096[6], + cfg_do[5] = cfg_do_6096[5], + cfg_do[4] = cfg_do_6096[4], + cfg_do[3] = cfg_do_6096[3], + cfg_do[2] = cfg_do_6096[2], + cfg_do[1] = cfg_do_6096[1], + cfg_do[0] = cfg_do_6096[0], + trn_reset_n = NlwRenamedSig_OI_trn_reset_n, + cfg_bus_number[7] = NlwRenamedSig_OI_cfg_bus_number[7], + cfg_bus_number[6] = NlwRenamedSig_OI_cfg_bus_number[6], + cfg_bus_number[5] = NlwRenamedSig_OI_cfg_bus_number[5], + cfg_bus_number[4] = NlwRenamedSig_OI_cfg_bus_number[4], + cfg_bus_number[3] = NlwRenamedSig_OI_cfg_bus_number[3], + cfg_bus_number[2] = NlwRenamedSig_OI_cfg_bus_number[2], + cfg_bus_number[1] = NlwRenamedSig_OI_cfg_bus_number[1], + cfg_bus_number[0] = NlwRenamedSig_OI_cfg_bus_number[0], + cfg_device_number[4] = NlwRenamedSig_OI_cfg_device_number[4], + cfg_device_number[3] = NlwRenamedSig_OI_cfg_device_number[3], + cfg_device_number[2] = NlwRenamedSig_OI_cfg_device_number[2], + cfg_device_number[1] = NlwRenamedSig_OI_cfg_device_number[1], + cfg_device_number[0] = NlwRenamedSig_OI_cfg_device_number[0], + trn_clk = NlwRenamedSig_OI_trn_clk, + cfg_dwaddr_6099[9] = cfg_dwaddr[9], + cfg_dwaddr_6099[8] = cfg_dwaddr[8], + cfg_dwaddr_6099[7] = cfg_dwaddr[7], + cfg_dwaddr_6099[6] = cfg_dwaddr[6], + cfg_dwaddr_6099[5] = cfg_dwaddr[5], + cfg_dwaddr_6099[4] = cfg_dwaddr[4], + cfg_dwaddr_6099[3] = cfg_dwaddr[3], + cfg_dwaddr_6099[2] = cfg_dwaddr[2], + cfg_dwaddr_6099[1] = cfg_dwaddr[1], + cfg_dwaddr_6099[0] = cfg_dwaddr[0], + trn_lnk_up_n = NlwRenamedSig_OI_trn_lnk_up_n, + trn_rfc_npd_av[11] = trn_rfc_npd_av_6091[11], + trn_rfc_npd_av[10] = trn_rfc_npd_av_6091[10], + trn_rfc_npd_av[9] = trn_rfc_npd_av_6091[9], + trn_rfc_npd_av[8] = trn_rfc_npd_av_6091[8], + trn_rfc_npd_av[7] = trn_rfc_npd_av_6091[7], + trn_rfc_npd_av[6] = trn_rfc_npd_av_6091[6], + trn_rfc_npd_av[5] = trn_rfc_npd_av_6091[5], + trn_rfc_npd_av[4] = trn_rfc_npd_av_6091[4], + trn_rfc_npd_av[3] = trn_rfc_npd_av_6091[3], + trn_rfc_npd_av[2] = trn_rfc_npd_av_6091[2], + trn_rfc_npd_av[1] = trn_rfc_npd_av_6091[1], + trn_rfc_npd_av[0] = trn_rfc_npd_av_6091[0], + cfg_dcommand[15] = NlwRenamedSignal_cfg_lcommand[15], + cfg_dcommand[14] = NlwRenamedSig_OI_cfg_dcommand[14], + cfg_dcommand[13] = NlwRenamedSig_OI_cfg_dcommand[13], + cfg_dcommand[12] = NlwRenamedSig_OI_cfg_dcommand[12], + cfg_dcommand[11] = NlwRenamedSig_OI_cfg_dcommand[11], + cfg_dcommand[10] = NlwRenamedSig_OI_cfg_dcommand[10], + cfg_dcommand[9] = NlwRenamedSig_OI_cfg_dcommand[9], + cfg_dcommand[8] = NlwRenamedSig_OI_cfg_dcommand[8], + cfg_dcommand[7] = NlwRenamedSig_OI_cfg_dcommand[7], + cfg_dcommand[6] = NlwRenamedSig_OI_cfg_dcommand[6], + cfg_dcommand[5] = NlwRenamedSig_OI_cfg_dcommand[5], + cfg_dcommand[4] = NlwRenamedSig_OI_cfg_dcommand[4], + cfg_dcommand[3] = NlwRenamedSig_OI_cfg_dcommand[3], + cfg_dcommand[2] = NlwRenamedSig_OI_cfg_dcommand[2], + cfg_dcommand[1] = NlwRenamedSig_OI_cfg_dcommand[1], + cfg_dcommand[0] = NlwRenamedSig_OI_cfg_dcommand[0], + trn_rfc_nph_av[7] = trn_rfc_nph_av_6090[7], + trn_rfc_nph_av[6] = trn_rfc_nph_av_6090[6], + trn_rfc_nph_av[5] = trn_rfc_nph_av_6090[5], + trn_rfc_nph_av[4] = trn_rfc_nph_av_6090[4], + trn_rfc_nph_av[3] = trn_rfc_nph_av_6090[3], + trn_rfc_nph_av[2] = trn_rfc_nph_av_6090[2], + trn_rfc_nph_av[1] = trn_rfc_nph_av_6090[1], + trn_rfc_nph_av[0] = trn_rfc_nph_av_6090[0], + cfg_pcie_link_state_n[2] = NlwRenamedSig_OI_cfg_status_4_, + cfg_pcie_link_state_n[1] = cfg_pcie_link_state_n_6101[1], + cfg_pcie_link_state_n[0] = cfg_pcie_link_state_n_6101[0], + sys_clkz = sys_clk, + cfg_function_number[2] = NlwRenamedSignal_cfg_lcommand[15], + cfg_function_number[1] = NlwRenamedSignal_cfg_lcommand[15], + cfg_function_number[0] = NlwRenamedSignal_cfg_lcommand[15], + cfg_lstatus[15] = NlwRenamedSignal_cfg_lcommand[15], + cfg_lstatus[14] = NlwRenamedSignal_cfg_lcommand[15], + cfg_lstatus[13] = NlwRenamedSignal_cfg_lcommand[15], + cfg_lstatus[12] = NlwRenamedSig_OI_cfg_lstatus_12_, + cfg_lstatus[11] = NlwRenamedSignal_cfg_lcommand[15], + cfg_lstatus[10] = NlwRenamedSignal_cfg_lcommand[15], + cfg_lstatus[9] = NlwRenamedSignal_cfg_lcommand[15], + cfg_lstatus[8] = NlwRenamedSignal_cfg_lcommand[15], + cfg_lstatus[7] = NlwRenamedSignal_cfg_lcommand[15], + cfg_lstatus[6] = NlwRenamedSig_OI_cfg_lstatus_6_, + cfg_lstatus[5] = NlwRenamedSignal_cfg_lcommand[15], + cfg_lstatus[4] = NlwRenamedSig_OI_cfg_lstatus_4_, + cfg_lstatus[3] = NlwRenamedSignal_cfg_lcommand[15], + cfg_lstatus[2] = NlwRenamedSignal_cfg_lcommand[15], + cfg_lstatus[1] = NlwRenamedSignal_cfg_lcommand[15], + cfg_lstatus[0] = NlwRenamedSig_OI_cfg_lstatus_0_, + pci_exp_rxn_6086[3] = pci_exp_rxn[3], + pci_exp_rxn_6086[2] = pci_exp_rxn[2], + pci_exp_rxn_6086[1] = pci_exp_rxn[1], + pci_exp_rxn_6086[0] = pci_exp_rxn[0], + pci_exp_rxp_6085[3] = pci_exp_rxp[3], + pci_exp_rxp_6085[2] = pci_exp_rxp[2], + pci_exp_rxp_6085[1] = pci_exp_rxp[1], + pci_exp_rxp_6085[0] = pci_exp_rxp[0], + trn_rfc_pd_av[11] = trn_rfc_pd_av_6093[11], + trn_rfc_pd_av[10] = trn_rfc_pd_av_6093[10], + trn_rfc_pd_av[9] = trn_rfc_pd_av_6093[9], + trn_rfc_pd_av[8] = trn_rfc_pd_av_6093[8], + trn_rfc_pd_av[7] = trn_rfc_pd_av_6093[7], + trn_rfc_pd_av[6] = trn_rfc_pd_av_6093[6], + trn_rfc_pd_av[5] = trn_rfc_pd_av_6093[5], + trn_rfc_pd_av[4] = trn_rfc_pd_av_6093[4], + trn_rfc_pd_av[3] = trn_rfc_pd_av_6093[3], + trn_rfc_pd_av[2] = trn_rfc_pd_av_6093[2], + trn_rfc_pd_av[1] = trn_rfc_pd_av_6093[1], + trn_rfc_pd_av[0] = trn_rfc_pd_av_6093[0], + trn_tbuf_av[4] = NlwRenamedSig_OI_trn_tbuf_av[4], + trn_tbuf_av[3] = NlwRenamedSig_OI_trn_tbuf_av[3], + trn_tbuf_av[2] = NlwRenamedSig_OI_trn_tbuf_av[2], + trn_tbuf_av[1] = NlwRenamedSig_OI_trn_tbuf_av[1], + trn_tbuf_av[0] = NlwRenamedSig_OI_trn_tbuf_av[0]; + defparam N_6610_i.INIT = 4'h1; + LUT1 N_6610_i ( + .I0(com_tlm_u_tlm_rx_data_snk_cur_length_0__2), + .O(N_6610_i_3) + ); + defparam N_6611_i.INIT = 4'h1; + LUT1 N_6611_i ( + .I0(com_tlm_u_tlm_rx_data_snk_cur_length_1__4), + .O(N_6611_i_5) + ); + defparam N_6612_i.INIT = 4'h1; + LUT1 N_6612_i ( + .I0(com_tlm_u_tlm_rx_data_snk_cur_length_2__6), + .O(N_6612_i_7) + ); + defparam N_6613_i.INIT = 4'h1; + LUT1 N_6613_i ( + .I0(com_tlm_u_tlm_rx_data_snk_cur_length_3__8), + .O(N_6613_i_9) + ); + defparam N_6614_i.INIT = 4'h1; + LUT1 N_6614_i ( + .I0(com_tlm_u_tlm_rx_data_snk_cur_length_4__10), + .O(N_6614_i_11) + ); + defparam N_6618_i.INIT = 4'h1; + LUT1 N_6618_i ( + .I0(com_tlm_u_tlm_rx_data_snk_cur_length_8__12), + .O(N_6618_i_13) + ); + defparam N_6619_i.INIT = 4'h1; + LUT1 N_6619_i ( + .I0(com_tlm_u_tlm_rx_data_snk_cur_length_9__14), + .O(N_6619_i_15) + ); + defparam I_39551.INIT = 4'h1; + LUT1 I_39551 ( + .I0(cfg_cfg_6102[224]), + .O(cfg_cfg_i_224_) + ); + defparam I_39705.INIT = 4'h1; + LUT1 I_39705 ( + .I0(cfg_cfg_6102[351]), + .O(cfg_cfg_i_351_) + ); + defparam N_71018_i.INIT = 4'h1; + LUT1 N_71018_i ( + .I0(plm_sym_reg_count[0]), + .O(N_71018_i_16) + ); + defparam N_71026_i.INIT = 4'h1; + LUT1 N_71026_i ( + .I0(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_dllp_d[0]), + .O(N_71026_i_17) + ); + INV I_40035 ( + .I(plm_link_up_2), + .O(plm_link_up_0) + ); + INV I_40034 ( + .I(cmmp_negotiated_width_1[0]), + .O(cmmp_negotiated_width_0[0]) + ); + INV I_40033 ( + .I(N_29556_i_1), + .O(N_29556_i_0) + ); + INV I_40032 ( + .I(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_5), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_3) + ); + INV I_40031 ( + .I(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_4), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_2) + ); + INV I_40030 ( + .I(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_3), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_1) + ); + INV I_40029 ( + .I(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_2), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_0) + ); + INV I_40028 ( + .I(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_1), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0) + ); + INV N_14477_i_i ( + .I(N_14477_i), + .O(N_14477_i_i_18) + ); + INV N_60904_i ( + .I(I_5336_i_0_i_a3_0_a2_19), + .O(N_60904_i_20) + ); + INV N_22672_i_i ( + .I(N_22672_i), + .O(N_22672_i_i_21) + ); + INV N_22527_i_i ( + .I(N_22527_i), + .O(N_22527_i_i_22) + ); + INV N_14480_i_i ( + .I(N_14480_i), + .O(N_14480_i_i_23) + ); + INV N_28800_i_i ( + .I(N_28800_i), + .O(N_28800_i_i_24) + ); + INV N_22977_i_i ( + .I(N_22977_i), + .O(N_22977_i_i_25) + ); + INV N_15212_i_i ( + .I(N_15212_i), + .O(N_15212_i_i_26) + ); + INV N_28802_i_i ( + .I(N_28802_i), + .O(N_28802_i_i_27) + ); + INV N_22826_i ( + .I(N_22826), + .O(N_22826_i_28) + ); + INV N_15205_i_i ( + .I(N_15205_i), + .O(N_15205_i_i_29) + ); + INV N_60997_i ( + .I(I_5033_0_a2_0_a2_0_a3_0_a2_30), + .O(N_60997_i_31) + ); + INV N_60983_i ( + .I(I_5039_0_a2_0_a2_0_a3_0_a2_32), + .O(N_60983_i_33) + ); + INV N_61022_i ( + .I(I_5045_0_a2_0_a2_0_a3_0_a2_34), + .O(N_61022_i_35) + ); + INV N_60976_i ( + .I(I_5051_0_a2_0_a3_0_a2_36), + .O(N_60976_i_37) + ); + INV N_61091_i ( + .I(I_5129_0_a2_0_a2_0_a3_0_a2_38), + .O(N_61091_i_39) + ); + INV N_61134_i ( + .I(I_5135_0_a2_0_a2_0_a3_0_a2_40), + .O(N_61134_i_41) + ); + INV N_61135_i ( + .I(I_5141_0_a2_0_a2_0_a3_0_a2_42), + .O(N_61135_i_43) + ); + INV N_61136_i ( + .I(I_5147_0_a2_0_a2_0_a3_0_a2_44), + .O(N_61136_i_45) + ); + INV N_61092_i ( + .I(I_5377_0_a2_0_a2_0_a3_0_a2_46), + .O(N_61092_i_47) + ); + INV N_61137_i ( + .I(I_5383_0_a2_0_a2_0_a3_0_a2_48), + .O(N_61137_i_49) + ); + INV N_61138_i ( + .I(I_5389_0_a2_0_a2_0_a3_0_a2_50), + .O(N_61138_i_51) + ); + INV N_61139_i ( + .I(I_5395_0_a2_0_a2_0_a3_0_a2_52), + .O(N_61139_i_53) + ); + INV link_up_i ( + .I(plm_link_up), + .O(plm_link_up_i) + ); + FDC G_40016 ( + .C(mgt_clk), + .D(G_39751_55), + .Q(G_40016_54), + .CLR(plm_rst) + ); + FDC G_40019 ( + .C(mgt_clk), + .D(NlwRenamedSig_OI_cfg_status_4_), + .Q(G_40019_56), + .CLR(plm_rst) + ); + FDC G_40021 ( + .C(mgt_clk), + .D(G_39720_58), + .Q(G_40021_57), + .CLR(plm_rst) + ); + FDC G_40023 ( + .C(mgt_clk), + .D(G_39722_60), + .Q(G_40023_59), + .CLR(plm_rst) + ); + FDC G_40025 ( + .C(mgt_clk), + .D(G_39731_62), + .Q(G_40025_61), + .CLR(plm_rst) + ); + FDC G_39731 ( + .C(mgt_clk), + .D(G_40023_59), + .Q(G_39731_62), + .CLR(plm_rst) + ); + FDC G_39751 ( + .C(mgt_clk), + .D(G_40025_61), + .Q(G_39751_55), + .CLR(plm_rst) + ); + FDC G_39720 ( + .C(mgt_clk), + .D(G_40019_56), + .Q(G_39720_58), + .CLR(plm_rst) + ); + FDC G_39722 ( + .C(mgt_clk), + .D(G_40021_57), + .Q(G_39722_60), + .CLR(plm_rst) + ); + FDRE G_39710 ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_i_65), + .C(NlwRenamedSig_OI_trn_clk), + .D(G_39714_64), + .Q(G_39710_63), + .R(plm_link_up_i) + ); + FDRE G_39714 ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_i_65), + .C(NlwRenamedSig_OI_trn_clk), + .D(NlwRenamedSig_OI_cfg_status_4_), + .Q(G_39714_64), + .R(plm_link_up_i) + ); + FDRE G_39716 ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_i_65), + .C(NlwRenamedSig_OI_trn_clk), + .D(G_39710_63), + .Q(G_39716_66), + .R(plm_link_up_i) + ); + defparam N_60915_i.INIT = 8'hFB; + LUT3 N_60915_i ( + .I0(plm_fsm_rc_counter_ts2_2_reg_rx_expired_67), + .I1(N_56155_i), + .I2(N_29556_i), + .O(N_60915_i_68) + ); + defparam N_60905_i.INIT = 8'hFB; + LUT3 N_60905_i ( + .I0(plm_fsm_rc_counter_ts2_0_reg_rx_expired_69), + .I1(N_56156_i), + .I2(N_29556_i), + .O(N_60905_i_70) + ); + defparam N_15208_i_i.INIT = 8'hEF; + LUT3 N_15208_i_i ( + .I0(plm_fsm_cc_counter0_reg_rx_expired_71), + .I1(N_56513_i), + .I2(N_56156_i), + .O(N_15208_i_i_72) + ); + defparam N_28971_i_i.INIT = 8'hEF; + LUT3 N_28971_i_i ( + .I0(plm_fsm_cc_counter2_reg_rx_expired_73), + .I1(N_56513_i), + .I2(N_56155_i), + .O(N_28971_i_i_74) + ); + defparam N_15210_i_i.INIT = 8'hBF; + LUT3 N_15210_i_i ( + .I0(plm_fsm_rl_counter0_reg_rx_expired_75), + .I1(plm_fsm_reg_state_13__76), + .I2(N_59396_1), + .O(N_15210_i_i_77) + ); + defparam N_22825_i.INIT = 8'hEF; + LUT3 N_22825_i ( + .I0(plm_fsm_cc_counter3_reg_rx_expired_78), + .I1(N_56513_i), + .I2(N_22826_1_0), + .O(N_22825_i_79) + ); + defparam G_470.INIT = 8'h96; + LUT3 G_470 ( + .I0(N_12128_1), + .I1(d16_i_m3_0_6_), + .I2(G_250_80), + .O(G_470_81) + ); + defparam G_465_1.INIT = 8'h96; + LUT3 G_465_1 ( + .I0(d64_i_m3_0_25_), + .I1(N_39_1), + .I2(N_3_1), + .O(N_12123_1) + ); + defparam G_376_1.INIT = 8'h96; + LUT3 G_376_1 ( + .I0(N_24), + .I1(N_51_1), + .I2(N_10_1), + .O(N_12034_1) + ); + defparam G_403_1.INIT = 8'h69; + LUT3 G_403_1 ( + .I0(c64_0_a2_0_a2_26_), + .I1(N_11858_1), + .I2(N_11847_1), + .O(N_12061_1) + ); + defparam N_22668_i_i.INIT = 8'hBF; + LUT3 N_22668_i_i ( + .I0(plm_fsm_pa_counter3_reg_rx_expired_82), + .I1(N_59114_2), + .I2(N_22668_i_1), + .O(N_22668_i_i_83) + ); + defparam N_14474_i_i.INIT = 8'hBF; + LUT3 N_14474_i_i ( + .I0(plm_fsm_pa_counter1_reg_rx_expired_84), + .I1(N_14474_i_1), + .I2(N_14474_1_i), + .O(N_14474_i_i_85) + ); + defparam N_22524_i_i.INIT = 8'hDF; + LUT3 N_22524_i_i ( + .I0(plm_rx2_link_pad), + .I1(plm_fsm_pa_counter2_reg_rx_expired_86), + .I2(N_59117_1), + .O(N_22524_i_i_87) + ); + defparam G_426.INIT = 8'h96; + LUT3 G_426 ( + .I0(data_in_q[16]), + .I1(data_in_q[45]), + .I2(N_129), + .O(G_426_88) + ); + defparam G_443.INIT = 8'h96; + LUT3 G_443 ( + .I0(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_7_), + .I1(N_218), + .I2(N_175), + .O(G_443_89) + ); + defparam G_86.INIT = 8'h96; + LUT3 G_86 ( + .I0(d64_i_m2_i_m3_0_36_), + .I1(d64_i_m3_0_17_), + .I2(d64_i_m3_0_1_), + .O(N_90) + ); + defparam G_104.INIT = 8'h96; + LUT3 G_104 ( + .I0(d64_i_m3_0_18_), + .I1(d64_i_m3_0_4_), + .I2(d64_i_m3_0_3_), + .O(N_108) + ); + defparam G_124.INIT = 8'h96; + LUT3 G_124 ( + .I0(N_11870_1), + .I1(d64_i_m3_0_35_), + .I2(d64_i_m3_0_12_), + .O(G_124_90) + ); + defparam G_319.INIT = 8'h96; + LUT3 G_319 ( + .I0(G_386_0_91), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d64_16__92), + .I2(d16_i_m3_i_m3_0_0_), + .O(G_319_93) + ); + defparam G_302.INIT = 8'h96; + LUT3 G_302 ( + .I0(N_11961_1), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d64_19__94), + .I2(d16_i_m3_0_3_), + .O(G_302_95) + ); + defparam G_469.INIT = 8'h96; + LUT3 G_469 ( + .I0(N_12127_1), + .I1(d16_i_m3_i_m3_0_0_), + .I2(d16_i_m3_0_6_), + .O(G_469_96) + ); + defparam G_39712.INIT = 4'hB; + LUT2 G_39712 ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_rem_pipe_DOUT[0]), + .I1(G_39716_66), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_rem_pipe[3]) + ); + defparam G_39717.INIT = 4'hB; + LUT2 G_39717 ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_eof_n_pipe_DOUT[0]), + .I1(G_39716_66), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_eof_n_pipe[4]) + ); + defparam G_430.INIT = 8'h96; + LUT3 G_430 ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crc32_d64_feedback[27]), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crc32_d64_feedback[25]), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crc32_d64_feedback[6]), + .O(N_12088) + ); + defparam G_136_1.INIT = 8'h56; + LUT3 G_136_1 ( + .I0(d64_i_m3_0_37_), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_initial_64_97), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d64_5__98), + .O(N_140_1) + ); + defparam G_287.INIT = 8'h96; + LUT3 G_287 ( + .I0(data_in_q[46]), + .I1(data_in_q[53]), + .I2(data_in_q[5]), + .O(G_287_99) + ); + defparam G_417.INIT = 8'h96; + LUT3 G_417 ( + .I0(plm_scr1_reg_lfsr_one_12__100), + .I1(plm_scr1_reg_lfsr_one_11__101), + .I2(plm_scr1_reg_lfsr_one_0__102), + .O(G_417_103) + ); + defparam G_39742.INIT = 4'h8; + LUT2 G_39742 ( + .I0(plm_tsi0_reg_dec7_0_DOUT[0]), + .I1(G_40025_61), + .O(plm_tsi0_reg_dec7_6_) + ); + defparam G_39733.INIT = 4'h8; + LUT2 G_39733 ( + .I0(plm_tsi0_reg_dec7_DOUT[0]), + .I1(G_40025_61), + .O(plm_tsi0_reg_dec7_13_) + ); + defparam G_39724.INIT = 4'h8; + LUT2 G_39724 ( + .I0(plm_tsi0_reg_dec5_DOUT[0]), + .I1(G_40023_59), + .O(plm_tsi0_reg_dec5[12]) + ); + defparam G_39848.INIT = 4'h8; + LUT2 G_39848 ( + .I0(G_39731_62), + .I1(plm_tsi1_reg_dec6_DOUT[0]), + .O(plm_tsi1_reg_dec6[5]) + ); + defparam G_39840.INIT = 4'h8; + LUT2 G_39840 ( + .I0(plm_tsi1_reg_dec1_2_DOUT[0]), + .I1(G_40021_57), + .O(plm_tsi1_reg_dec1[4]) + ); + defparam G_39835.INIT = 4'h8; + LUT2 G_39835 ( + .I0(plm_tsi1_reg_dec1_1_DOUT[0]), + .I1(G_40021_57), + .O(plm_tsi1_reg_dec1[3]) + ); + defparam G_39830.INIT = 4'h8; + LUT2 G_39830 ( + .I0(plm_tsi1_reg_dec1_0_DOUT[0]), + .I1(G_40021_57), + .O(plm_tsi1_reg_dec1[2]) + ); + defparam G_39825.INIT = 4'h8; + LUT2 G_39825 ( + .I0(plm_tsi1_reg_dec1_DOUT[0]), + .I1(G_40021_57), + .O(plm_tsi1_reg_dec1[1]) + ); + defparam G_39820.INIT = 4'h8; + LUT2 G_39820 ( + .I0(plm_tsi1_reg_dec8_DOUT[0]), + .I1(G_40016_54), + .O(plm_tsi1_reg_dec8_7_) + ); + defparam G_39809.INIT = 4'h8; + LUT2 G_39809 ( + .I0(plm_tsi1_reg_dec7_0_DOUT[0]), + .I1(G_40016_54), + .O(plm_tsi1_reg_dec7_6_) + ); + defparam G_39798.INIT = 4'h8; + LUT2 G_39798 ( + .I0(plm_tsi1_reg_dec7_DOUT[0]), + .I1(G_40016_54), + .O(plm_tsi1_reg_dec7_13_) + ); + defparam G_39787.INIT = 4'h8; + LUT2 G_39787 ( + .I0(plm_tsi1_reg_dec5_DOUT[0]), + .I1(G_40023_59), + .O(plm_tsi1_reg_dec5[12]) + ); + defparam G_39780.INIT = 4'h8; + LUT2 G_39780 ( + .I0(G_39731_62), + .I1(plm_tsi0_reg_dec6_DOUT[0]), + .O(plm_tsi0_reg_dec6[5]) + ); + defparam G_39772.INIT = 4'h8; + LUT2 G_39772 ( + .I0(plm_tsi0_reg_dec1_2_DOUT[0]), + .I1(G_40021_57), + .O(plm_tsi0_reg_dec1[4]) + ); + defparam G_39767.INIT = 4'h8; + LUT2 G_39767 ( + .I0(plm_tsi0_reg_dec1_1_DOUT[0]), + .I1(G_40021_57), + .O(plm_tsi0_reg_dec1[3]) + ); + defparam G_39762.INIT = 4'h8; + LUT2 G_39762 ( + .I0(plm_tsi0_reg_dec1_0_DOUT[0]), + .I1(G_40021_57), + .O(plm_tsi0_reg_dec1[2]) + ); + defparam G_39757.INIT = 4'h8; + LUT2 G_39757 ( + .I0(plm_tsi0_reg_dec1_DOUT[0]), + .I1(G_40021_57), + .O(plm_tsi0_reg_dec1[1]) + ); + defparam G_39752.INIT = 4'h8; + LUT2 G_39752 ( + .I0(G_39751_55), + .I1(plm_tsi0_reg_dec8_DOUT[0]), + .O(plm_tsi0_reg_dec8_7_) + ); + defparam G_39966.INIT = 4'h8; + LUT2 G_39966 ( + .I0(plm_tsi3_reg_dec1_0_DOUT[0]), + .I1(G_40021_57), + .O(plm_tsi3_reg_dec1[2]) + ); + defparam G_39961.INIT = 4'h8; + LUT2 G_39961 ( + .I0(plm_tsi3_reg_dec1_DOUT[0]), + .I1(G_40021_57), + .O(plm_tsi3_reg_dec1[1]) + ); + defparam G_39956.INIT = 4'h8; + LUT2 G_39956 ( + .I0(plm_tsi3_reg_dec8_DOUT[0]), + .I1(G_40016_54), + .O(plm_tsi3_reg_dec8_7_) + ); + defparam G_39945.INIT = 4'h8; + LUT2 G_39945 ( + .I0(plm_tsi3_reg_dec7_0_DOUT[0]), + .I1(G_40016_54), + .O(plm_tsi3_reg_dec7_6_) + ); + defparam G_39934.INIT = 4'h8; + LUT2 G_39934 ( + .I0(plm_tsi3_reg_dec5_DOUT[0]), + .I1(G_40023_59), + .O(plm_tsi3_reg_dec5[12]) + ); + defparam G_39927.INIT = 4'h8; + LUT2 G_39927 ( + .I0(plm_tsi3_reg_dec7_DOUT[0]), + .I1(G_40016_54), + .O(plm_tsi3_reg_dec7_13_) + ); + defparam G_39916.INIT = 4'h8; + LUT2 G_39916 ( + .I0(G_39731_62), + .I1(plm_tsi2_reg_dec6_DOUT[0]), + .O(plm_tsi2_reg_dec6[5]) + ); + defparam G_39908.INIT = 4'h8; + LUT2 G_39908 ( + .I0(plm_tsi2_reg_dec1_2_DOUT[0]), + .I1(G_40021_57), + .O(plm_tsi2_reg_dec1[4]) + ); + defparam G_39903.INIT = 4'h8; + LUT2 G_39903 ( + .I0(plm_tsi2_reg_dec1_1_DOUT[0]), + .I1(G_40021_57), + .O(plm_tsi2_reg_dec1[3]) + ); + defparam G_39898.INIT = 4'h8; + LUT2 G_39898 ( + .I0(plm_tsi2_reg_dec1_0_DOUT[0]), + .I1(G_40021_57), + .O(plm_tsi2_reg_dec1[2]) + ); + defparam G_39893.INIT = 4'h8; + LUT2 G_39893 ( + .I0(plm_tsi2_reg_dec1_DOUT[0]), + .I1(G_40021_57), + .O(plm_tsi2_reg_dec1[1]) + ); + defparam G_39888.INIT = 4'h8; + LUT2 G_39888 ( + .I0(plm_tsi2_reg_dec8_DOUT[0]), + .I1(G_40016_54), + .O(plm_tsi2_reg_dec8_7_) + ); + defparam G_39877.INIT = 4'h8; + LUT2 G_39877 ( + .I0(plm_tsi2_reg_dec7_0_DOUT[0]), + .I1(G_40016_54), + .O(plm_tsi2_reg_dec7_6_) + ); + defparam G_39866.INIT = 4'h8; + LUT2 G_39866 ( + .I0(plm_tsi2_reg_dec7_DOUT[0]), + .I1(G_40016_54), + .O(plm_tsi2_reg_dec7_13_) + ); + defparam G_39855.INIT = 4'h8; + LUT2 G_39855 ( + .I0(plm_tsi2_reg_dec5_DOUT[0]), + .I1(G_40023_59), + .O(plm_tsi2_reg_dec5[12]) + ); + defparam G_40027.INIT = 4'h8; + LUT2 G_40027 ( + .I0(G_39751_55), + .I1(plm_tsi0_reg_dec8_0_DOUT[0]), + .O(plm_tsi0_reg_dec8_0_) + ); + defparam G_40017.INIT = 4'h8; + LUT2 G_40017 ( + .I0(G_40016_54), + .I1(plm_tsi1_reg_dec8_0_DOUT[0]), + .O(plm_tsi1_reg_dec8_0_) + ); + defparam G_40006.INIT = 4'h8; + LUT2 G_40006 ( + .I0(plm_tsi2_reg_dec8_0_DOUT[0]), + .I1(G_40016_54), + .O(plm_tsi2_reg_dec8_0_) + ); + defparam G_39995.INIT = 4'h8; + LUT2 G_39995 ( + .I0(plm_tsi3_reg_dec8_0_DOUT[0]), + .I1(G_40016_54), + .O(plm_tsi3_reg_dec8_0_) + ); + defparam G_39984.INIT = 4'h8; + LUT2 G_39984 ( + .I0(G_39731_62), + .I1(plm_tsi3_reg_dec6_DOUT[0]), + .O(plm_tsi3_reg_dec6[5]) + ); + defparam G_39976.INIT = 4'h8; + LUT2 G_39976 ( + .I0(plm_tsi3_reg_dec1_2_DOUT[0]), + .I1(G_40021_57), + .O(plm_tsi3_reg_dec1[4]) + ); + defparam G_39971.INIT = 4'h8; + LUT2 G_39971 ( + .I0(plm_tsi3_reg_dec1_1_DOUT[0]), + .I1(G_40021_57), + .O(plm_tsi3_reg_dec1[3]) + ); + defparam m25_am.INIT = 16'h4315; + LUT4 m25_am ( + .I0(com_cmm_u_cmm_errman_wtd_cor_add_input_five_n_d_104), + .I1(com_cmm_u_cmm_errman_wtd_cor_add_input_three_n_d_105), + .I2(com_cmm_u_cmm_errman_wtd_cor_add_input_two_n_d_106), + .I3(m25_am_1_107), + .O(m25_am_108) + ); + defparam m25_am_1.INIT = 16'h2442; + LUT4_L m25_am_1 ( + .I0(com_cmm_u_cmm_errman_wtd_cor_add_input_one_d_109), + .I1(com_cmm_u_cmm_errman_wtd_cor_add_input_six_n_d_110), + .I2(com_cmm_u_cmm_errman_wtd_cor_add_input_three_n_d_105), + .I3(com_cmm_u_cmm_errman_wtd_cor_add_input_two_n_d_106), + .LO(m25_am_1_107) + ); + defparam N_85925_i.INIT = 16'h57D7; + LUT4_L N_85925_i ( + .I0(m5_2_0_0_0_39292_111), + .I1(com_lnk_rd[0]), + .I2(com_lnk_rd[2]), + .I3(com_lnk_rd[3]), + .LO(N_85925_i_112) + ); + defparam N_86751_i.INIT = 16'h54E8; + LUT4_L N_86751_i ( + .I0(com_lnk_rd[0]), + .I1(com_lnk_rd[1]), + .I2(com_lnk_rd[2]), + .I3(com_lnk_rd[3]), + .LO(N_86751_i_113) + ); + defparam m16_i_0_0.INIT = 16'h1F00; + LUT4_L m16_i_0_0 ( + .I0(N_56980), + .I1(N_56983), + .I2(com_lnk_rd[4]), + .I3(m16_i_0_0_4_114), + .LO(N_17347_i) + ); + defparam I_39680.INIT = 4'h1; + LUT1_L I_39680 ( + .I0(trn_tsof_n), + .LO(trn_tsof_n_i) + ); + defparam I_39707.INIT = 4'h1; + LUT1_L I_39707 ( + .I0(trn_terrfwd_n), + .LO(trn_terrfwd_n_i) + ); + defparam m4_6_0_a2_0_a2.INIT = 16'hEB00; + LUT4_L m4_6_0_a2_0_a2 ( + .I0(plm_dfm_deframe1_dword_empty), + .I1(plm_dfm_deframe1_dword_sdpstp[0]), + .I2(plm_dfm_deframe1_dword_sdpstp[1]), + .I3(plm_dfm_deframe1_qwfsm_reg_state_1__115), + .LO(plm_dfm_deframe1_qwfsm_nxt_state[4]) + ); + defparam m5_4_0_a2_0_a2.INIT = 16'hEB00; + LUT4_L m5_4_0_a2_0_a2 ( + .I0(plm_dfm_deframe1_dword_empty), + .I1(plm_dfm_deframe1_dword_sdpstp[0]), + .I2(plm_dfm_deframe1_dword_sdpstp[1]), + .I3(plm_dfm_deframe1_qwfsm_reg_state_0__116), + .LO(plm_dfm_deframe1_qwfsm_nxt_state[5]) + ); + defparam N_87771_i.INIT = 16'hAA80; + LUT4_L N_87771_i ( + .I0(m10_3_0_0_a3_117), + .I1(reg_by1_preh_sdpstp_6_iv_i_0_a4[1]), + .I2(plm_dfm_deframe1_qwfsm_reg_state_1__115), + .I3(plm_dfm_deframe1_qwfsm_reg_state_7__118), + .LO(N_87771_i_119) + ); + defparam N_87770_i.INIT = 16'hAA80; + LUT4_L N_87770_i ( + .I0(m10_3_0_0_a3_117), + .I1(reg_by1_preh_sdpstp_6_iv_i_0_a4[1]), + .I2(plm_dfm_deframe1_qwfsm_reg_state_0__116), + .I3(plm_dfm_deframe1_qwfsm_reg_state_6__120), + .LO(N_87770_i_121) + ); + defparam N_154_i.INIT = 16'h5503; + LUT4_L N_154_i ( + .I0(N_150), + .I1(N_201_i), + .I2(plm_sym_sym_gen_next_addr[3]), + .I3(plm_sym_sym_gen_next_addr[4]), + .LO(N_154_i_122) + ); + defparam m8_0.INIT = 16'h00F4; + LUT4_L m8_0 ( + .I0(N_2766), + .I1(plm_sym_sym_gen_next_addr[1]), + .I2(plm_sym_sym_gen_next_addr[2]), + .I3(plm_sym_sym_gen_next_addr[4]), + .LO(plm_sym_sym_gen_reg_rom_out_27[17]) + ); + defparam N_16_i.INIT = 16'h5F40; + LUT4_L N_16_i ( + .I0(N_202_i), + .I1(plm_sym_sym_gen_next_addr[0]), + .I2(plm_sym_sym_gen_next_addr[1]), + .I3(plm_sym_sym_gen_next_addr[2]), + .LO(N_16_i_123) + ); + defparam loadable_tx_counter_reg_tx_count_6_0_a2_0_a2_0_a2_0_a3_0_a2_4_.INIT = 4'h2; + LUT2_L loadable_tx_counter_reg_tx_count_6_0_a2_0_a2_0_a2_0_a3_0_a2_4_ ( + .I0(cfg_cfg_6102[507]), + .I1(plm_fsm_reg_state_13__76), + .LO(plm_fsm_rl_counter3_loadable_tx_counter_reg_tx_count_6[4]) + ); + defparam I_4983_0_a2_0_a2_0_a2.INIT = 4'h8; + LUT2_L I_4983_0_a2_0_a2_0_a2 ( + .I0(cfg_cfg_6102[86]), + .I1(com_cmm_cfg_wr_data_14_), + .LO(I_4983_0_a2_0_a2_0_a2_124) + ); + defparam I_4978_0_a2_0_a2_0_a2.INIT = 4'h8; + LUT2_L I_4978_0_a2_0_a2_0_a2 ( + .I0(cfg_cfg_6102[87]), + .I1(com_cmm_cfg_wr_data_15_), + .LO(I_4978_0_a2_0_a2_0_a2_125) + ); + defparam I_4973_0_a2_0_a2_0_a2.INIT = 4'h8; + LUT2_L I_4973_0_a2_0_a2_0_a2 ( + .I0(cfg_cfg_6102[88]), + .I1(com_cmm_cfg_wr_data_0_), + .LO(I_4973_0_a2_0_a2_0_a2_126) + ); + defparam I_4968_0_a2_0_a2_0_a2.INIT = 4'h8; + LUT2_L I_4968_0_a2_0_a2_0_a2 ( + .I0(cfg_cfg_6102[89]), + .I1(com_cmm_cfg_wr_data_1_), + .LO(I_4968_0_a2_0_a2_0_a2_127) + ); + defparam I_4963_0_a2_0_a2_0_a2.INIT = 4'h8; + LUT2_L I_4963_0_a2_0_a2_0_a2 ( + .I0(cfg_cfg_6102[90]), + .I1(com_cmm_cfg_wr_data_2_), + .LO(I_4963_0_a2_0_a2_0_a2_128) + ); + defparam I_4958_0_a2_0_a2_0_a2.INIT = 4'h8; + LUT2_L I_4958_0_a2_0_a2_0_a2 ( + .I0(cfg_cfg_6102[91]), + .I1(com_cmm_cfg_wr_data_3_), + .LO(I_4958_0_a2_0_a2_0_a2_129) + ); + defparam I_4953_0_a2_0_a2_0_a2.INIT = 4'h8; + LUT2_L I_4953_0_a2_0_a2_0_a2 ( + .I0(cfg_cfg_6102[92]), + .I1(com_cmm_cfg_wr_data_4_), + .LO(I_4953_0_a2_0_a2_0_a2_130) + ); + defparam I_4948_0_a2_0_a2_0_a2.INIT = 4'h8; + LUT2_L I_4948_0_a2_0_a2_0_a2 ( + .I0(cfg_cfg_6102[93]), + .I1(com_cmm_cfg_wr_data_5_), + .LO(I_4948_0_a2_0_a2_0_a2_131) + ); + defparam I_4943_0_a2_0_a2_0_a2.INIT = 4'h8; + LUT2_L I_4943_0_a2_0_a2_0_a2 ( + .I0(cfg_cfg_6102[94]), + .I1(com_cmm_cfg_wr_data_6_), + .LO(I_4943_0_a2_0_a2_0_a2_132) + ); + defparam I_4938_0_a2_0_a2_0_a2.INIT = 4'h8; + LUT2_L I_4938_0_a2_0_a2_0_a2 ( + .I0(cfg_cfg_6102[95]), + .I1(com_cmm_cfg_wr_data_7_), + .LO(I_4938_0_a2_0_a2_0_a2_133) + ); + defparam I_4933_0_a2_0_a2_0_a2_0_a2.INIT = 4'h8; + LUT2_L I_4933_0_a2_0_a2_0_a2_0_a2 ( + .I0(cfg_cfg_6102[71]), + .I1(com_cmm_cfg_wr_data_31_), + .LO(I_4933_0_a2_0_a2_0_a2_0_a2_134) + ); + defparam I_4928_0_a2_0_a2_0_a2.INIT = 4'h8; + LUT2_L I_4928_0_a2_0_a2_0_a2 ( + .I0(cfg_cfg_6102[72]), + .I1(com_cmm_cfg_wr_data_16_), + .LO(I_4928_0_a2_0_a2_0_a2_135) + ); + defparam I_4923_0_a2_0_a2_0_a2.INIT = 4'h8; + LUT2_L I_4923_0_a2_0_a2_0_a2 ( + .I0(cfg_cfg_6102[73]), + .I1(com_cmm_cfg_wr_data_17_), + .LO(I_4923_0_a2_0_a2_0_a2_136) + ); + defparam I_4918_0_a2_0_a2_0_a2.INIT = 4'h8; + LUT2_L I_4918_0_a2_0_a2_0_a2 ( + .I0(cfg_cfg_6102[74]), + .I1(com_cmm_cfg_wr_data_18_), + .LO(I_4918_0_a2_0_a2_0_a2_137) + ); + defparam I_4913_0_a2_0_a2_0_a2.INIT = 4'h8; + LUT2_L I_4913_0_a2_0_a2_0_a2 ( + .I0(cfg_cfg_6102[75]), + .I1(com_cmm_cfg_wr_data_19_), + .LO(I_4913_0_a2_0_a2_0_a2_138) + ); + defparam I_4908_0_a2_0_a2_0_a2_0_a2.INIT = 4'h8; + LUT2_L I_4908_0_a2_0_a2_0_a2_0_a2 ( + .I0(cfg_cfg_6102[76]), + .I1(com_cmm_cfg_wr_data_20_), + .LO(I_4908_0_a2_0_a2_0_a2_0_a2_139) + ); + defparam I_4903_0_a2_0_a2_0_a2_0_a2.INIT = 4'h8; + LUT2_L I_4903_0_a2_0_a2_0_a2_0_a2 ( + .I0(cfg_cfg_6102[77]), + .I1(com_cmm_cfg_wr_data_21_), + .LO(I_4903_0_a2_0_a2_0_a2_0_a2_140) + ); + defparam I_4898_0_a2_0_a2_0_a2_0_a2.INIT = 4'h8; + LUT2_L I_4898_0_a2_0_a2_0_a2_0_a2 ( + .I0(cfg_cfg_6102[78]), + .I1(com_cmm_cfg_wr_data_22_), + .LO(I_4898_0_a2_0_a2_0_a2_0_a2_141) + ); + defparam I_4893_0_a2_0_a2_0_a2_0_a2.INIT = 4'h8; + LUT2_L I_4893_0_a2_0_a2_0_a2_0_a2 ( + .I0(cfg_cfg_6102[79]), + .I1(com_cmm_cfg_wr_data_23_), + .LO(I_4893_0_a2_0_a2_0_a2_0_a2_142) + ); + defparam I_4888_0_a2_0_a2_0_a2_0_a2.INIT = 4'h8; + LUT2_L I_4888_0_a2_0_a2_0_a2_0_a2 ( + .I0(cfg_cfg_6102[80]), + .I1(com_cmm_cfg_wr_data_8_), + .LO(I_4888_0_a2_0_a2_0_a2_0_a2_143) + ); + defparam I_4883_0_a2_0_a2_0_a2_0_a2.INIT = 4'h8; + LUT2_L I_4883_0_a2_0_a2_0_a2_0_a2 ( + .I0(cfg_cfg_6102[81]), + .I1(com_cmm_cfg_wr_data_9_), + .LO(I_4883_0_a2_0_a2_0_a2_0_a2_144) + ); + defparam I_4878_0_a2_0_a2_0_a2_0_a2.INIT = 4'h8; + LUT2_L I_4878_0_a2_0_a2_0_a2_0_a2 ( + .I0(cfg_cfg_6102[82]), + .I1(com_cmm_cfg_wr_data_10_), + .LO(I_4878_0_a2_0_a2_0_a2_0_a2_145) + ); + defparam I_4873_0_a2_0_a2_0_a2_0_a2.INIT = 4'h8; + LUT2_L I_4873_0_a2_0_a2_0_a2_0_a2 ( + .I0(cfg_cfg_6102[83]), + .I1(com_cmm_cfg_wr_data_11_), + .LO(I_4873_0_a2_0_a2_0_a2_0_a2_146) + ); + defparam I_4868_0_a2_0_a2_0_a2.INIT = 4'h8; + LUT2_L I_4868_0_a2_0_a2_0_a2 ( + .I0(cfg_cfg_6102[84]), + .I1(com_cmm_cfg_wr_data_12_), + .LO(I_4868_0_a2_0_a2_0_a2_147) + ); + defparam I_4863_0_a2_0_a2_0_a2.INIT = 4'h8; + LUT2_L I_4863_0_a2_0_a2_0_a2 ( + .I0(cfg_cfg_6102[85]), + .I1(com_cmm_cfg_wr_data_13_), + .LO(I_4863_0_a2_0_a2_0_a2_148) + ); + defparam I_4858_0_a2_0_a2_0_a2_0_a2.INIT = 4'h8; + LUT2_L I_4858_0_a2_0_a2_0_a2_0_a2 ( + .I0(cfg_cfg_6102[68]), + .I1(com_cmm_cfg_wr_data_28_), + .LO(I_4858_0_a2_0_a2_0_a2_0_a2_149) + ); + defparam I_4853_0_a2_0_a2_0_a2_0_a2.INIT = 4'h8; + LUT2_L I_4853_0_a2_0_a2_0_a2_0_a2 ( + .I0(cfg_cfg_6102[69]), + .I1(com_cmm_cfg_wr_data_29_), + .LO(I_4853_0_a2_0_a2_0_a2_0_a2_150) + ); + defparam I_4848_0_a2_0_a2_0_a2_0_a2.INIT = 4'h8; + LUT2_L I_4848_0_a2_0_a2_0_a2_0_a2 ( + .I0(cfg_cfg_6102[70]), + .I1(com_cmm_cfg_wr_data_30_), + .LO(I_4848_0_a2_0_a2_0_a2_0_a2_151) + ); + defparam I_4843_0_a2_0_a2_0_a2.INIT = 4'h8; + LUT2_L I_4843_0_a2_0_a2_0_a2 ( + .I0(cfg_cfg_6102[248]), + .I1(com_cmm_cfg_wr_data_0_), + .LO(I_4843_0_a2_0_a2_0_a2_152) + ); + defparam I_4838_0_a2_0_a2_0_a2.INIT = 4'h8; + LUT2_L I_4838_0_a2_0_a2_0_a2 ( + .I0(cfg_cfg_6102[249]), + .I1(com_cmm_cfg_wr_data_1_), + .LO(I_4838_0_a2_0_a2_0_a2_153) + ); + defparam I_4833_0_a2_0_a2_0_a2.INIT = 4'h8; + LUT2_L I_4833_0_a2_0_a2_0_a2 ( + .I0(cfg_cfg_6102[250]), + .I1(com_cmm_cfg_wr_data_2_), + .LO(I_4833_0_a2_0_a2_0_a2_154) + ); + defparam I_4828_0_a2_0_a2_0_a2.INIT = 4'h8; + LUT2_L I_4828_0_a2_0_a2_0_a2 ( + .I0(cfg_cfg_6102[251]), + .I1(com_cmm_cfg_wr_data_3_), + .LO(I_4828_0_a2_0_a2_0_a2_155) + ); + defparam I_4823_0_a2_0_a2_0_a2.INIT = 4'h8; + LUT2_L I_4823_0_a2_0_a2_0_a2 ( + .I0(cfg_cfg_6102[252]), + .I1(com_cmm_cfg_wr_data_4_), + .LO(I_4823_0_a2_0_a2_0_a2_156) + ); + defparam I_4818_0_a2_0_a2_0_a2.INIT = 4'h8; + LUT2_L I_4818_0_a2_0_a2_0_a2 ( + .I0(cfg_cfg_6102[253]), + .I1(com_cmm_cfg_wr_data_5_), + .LO(I_4818_0_a2_0_a2_0_a2_157) + ); + defparam I_4813_0_a2_0_a2_0_a2.INIT = 4'h8; + LUT2_L I_4813_0_a2_0_a2_0_a2 ( + .I0(cfg_cfg_6102[254]), + .I1(com_cmm_cfg_wr_data_6_), + .LO(I_4813_0_a2_0_a2_0_a2_158) + ); + defparam I_4808_0_a2_0_a2_0_a2.INIT = 4'h8; + LUT2_L I_4808_0_a2_0_a2_0_a2 ( + .I0(cfg_cfg_6102[255]), + .I1(com_cmm_cfg_wr_data_7_), + .LO(I_4808_0_a2_0_a2_0_a2_159) + ); + defparam I_4803_0_a2_0_a2_0_a2.INIT = 4'h8; + LUT2_L I_4803_0_a2_0_a2_0_a2 ( + .I0(cfg_cfg_6102[233]), + .I1(com_cmm_cfg_wr_data_17_), + .LO(I_4803_0_a2_0_a2_0_a2_160) + ); + defparam I_4798_0_a2_0_a2_0_a2.INIT = 4'h8; + LUT2_L I_4798_0_a2_0_a2_0_a2 ( + .I0(cfg_cfg_6102[234]), + .I1(com_cmm_cfg_wr_data_18_), + .LO(I_4798_0_a2_0_a2_0_a2_161) + ); + defparam I_4793_0_a2_0_a2_0_a2.INIT = 4'h8; + LUT2_L I_4793_0_a2_0_a2_0_a2 ( + .I0(cfg_cfg_6102[235]), + .I1(com_cmm_cfg_wr_data_19_), + .LO(I_4793_0_a2_0_a2_0_a2_162) + ); + defparam I_4788_0_a2_0_a2_0_a2_0_a2.INIT = 4'h8; + LUT2_L I_4788_0_a2_0_a2_0_a2_0_a2 ( + .I0(cfg_cfg_6102[236]), + .I1(com_cmm_cfg_wr_data_20_), + .LO(I_4788_0_a2_0_a2_0_a2_0_a2_163) + ); + defparam I_4783_0_a2_0_a2_0_a2_0_a2.INIT = 4'h8; + LUT2_L I_4783_0_a2_0_a2_0_a2_0_a2 ( + .I0(cfg_cfg_6102[237]), + .I1(com_cmm_cfg_wr_data_21_), + .LO(I_4783_0_a2_0_a2_0_a2_0_a2_164) + ); + defparam I_4778_0_a2_0_a2_0_a2_0_a2.INIT = 4'h8; + LUT2_L I_4778_0_a2_0_a2_0_a2_0_a2 ( + .I0(cfg_cfg_6102[238]), + .I1(com_cmm_cfg_wr_data_22_), + .LO(I_4778_0_a2_0_a2_0_a2_0_a2_165) + ); + defparam I_4773_0_a2_0_a2_0_a2_0_a2.INIT = 4'h8; + LUT2_L I_4773_0_a2_0_a2_0_a2_0_a2 ( + .I0(cfg_cfg_6102[239]), + .I1(com_cmm_cfg_wr_data_23_), + .LO(I_4773_0_a2_0_a2_0_a2_0_a2_166) + ); + defparam I_4768_0_a2_0_a2_0_a2_0_a2.INIT = 4'h8; + LUT2_L I_4768_0_a2_0_a2_0_a2_0_a2 ( + .I0(cfg_cfg_6102[240]), + .I1(com_cmm_cfg_wr_data_8_), + .LO(I_4768_0_a2_0_a2_0_a2_0_a2_167) + ); + defparam I_4763_0_a2_0_a2_0_a2_0_a2.INIT = 4'h8; + LUT2_L I_4763_0_a2_0_a2_0_a2_0_a2 ( + .I0(cfg_cfg_6102[241]), + .I1(com_cmm_cfg_wr_data_9_), + .LO(I_4763_0_a2_0_a2_0_a2_0_a2_168) + ); + defparam I_4758_0_a2_0_a2_0_a2_0_a2.INIT = 4'h8; + LUT2_L I_4758_0_a2_0_a2_0_a2_0_a2 ( + .I0(cfg_cfg_6102[242]), + .I1(com_cmm_cfg_wr_data_10_), + .LO(I_4758_0_a2_0_a2_0_a2_0_a2_169) + ); + defparam I_4753_0_a2_0_a2_0_a2_0_a2.INIT = 4'h8; + LUT2_L I_4753_0_a2_0_a2_0_a2_0_a2 ( + .I0(cfg_cfg_6102[243]), + .I1(com_cmm_cfg_wr_data_11_), + .LO(I_4753_0_a2_0_a2_0_a2_0_a2_170) + ); + defparam I_4748_0_a2_0_a2_0_a2.INIT = 4'h8; + LUT2_L I_4748_0_a2_0_a2_0_a2 ( + .I0(cfg_cfg_6102[244]), + .I1(com_cmm_cfg_wr_data_12_), + .LO(I_4748_0_a2_0_a2_0_a2_171) + ); + defparam I_4743_0_a2_0_a2_0_a2.INIT = 4'h8; + LUT2_L I_4743_0_a2_0_a2_0_a2 ( + .I0(cfg_cfg_6102[245]), + .I1(com_cmm_cfg_wr_data_13_), + .LO(I_4743_0_a2_0_a2_0_a2_172) + ); + defparam I_4738_0_a2_0_a2_0_a2.INIT = 4'h8; + LUT2_L I_4738_0_a2_0_a2_0_a2 ( + .I0(cfg_cfg_6102[246]), + .I1(com_cmm_cfg_wr_data_14_), + .LO(I_4738_0_a2_0_a2_0_a2_173) + ); + defparam I_4733_0_a2_0_a2_0_a2.INIT = 4'h8; + LUT2_L I_4733_0_a2_0_a2_0_a2 ( + .I0(cfg_cfg_6102[247]), + .I1(com_cmm_cfg_wr_data_15_), + .LO(I_4733_0_a2_0_a2_0_a2_174) + ); + defparam I_4728_0_a2_0_a2_0_a2.INIT = 4'h8; + LUT2_L I_4728_0_a2_0_a2_0_a2 ( + .I0(cfg_cfg_6102[218]), + .I1(com_cmm_cfg_wr_data_2_), + .LO(I_4728_0_a2_0_a2_0_a2_175) + ); + defparam I_4723_0_a2_0_a2_0_a2.INIT = 4'h8; + LUT2_L I_4723_0_a2_0_a2_0_a2 ( + .I0(cfg_cfg_6102[219]), + .I1(com_cmm_cfg_wr_data_3_), + .LO(I_4723_0_a2_0_a2_0_a2_176) + ); + defparam I_4718_0_a2_0_a2_0_a2.INIT = 4'h8; + LUT2_L I_4718_0_a2_0_a2_0_a2 ( + .I0(cfg_cfg_6102[220]), + .I1(com_cmm_cfg_wr_data_4_), + .LO(I_4718_0_a2_0_a2_0_a2_177) + ); + defparam I_4713_0_a2_0_a2_0_a2.INIT = 4'h8; + LUT2_L I_4713_0_a2_0_a2_0_a2 ( + .I0(cfg_cfg_6102[221]), + .I1(com_cmm_cfg_wr_data_5_), + .LO(I_4713_0_a2_0_a2_0_a2_178) + ); + defparam I_4708_0_a2_0_a2_0_a2.INIT = 4'h8; + LUT2_L I_4708_0_a2_0_a2_0_a2 ( + .I0(cfg_cfg_6102[222]), + .I1(com_cmm_cfg_wr_data_6_), + .LO(I_4708_0_a2_0_a2_0_a2_179) + ); + defparam I_4703_0_a2_0_a2_0_a2.INIT = 4'h8; + LUT2_L I_4703_0_a2_0_a2_0_a2 ( + .I0(cfg_cfg_6102[223]), + .I1(com_cmm_cfg_wr_data_7_), + .LO(I_4703_0_a2_0_a2_0_a2_180) + ); + defparam I_4698_0_a2_0_a2_0_a2_0_a2.INIT = 4'h8; + LUT2_L I_4698_0_a2_0_a2_0_a2_0_a2 ( + .I0(cfg_cfg_6102[228]), + .I1(com_cmm_cfg_wr_data_28_), + .LO(I_4698_0_a2_0_a2_0_a2_0_a2_181) + ); + defparam I_4693_0_a2_0_a2_0_a2_0_a2.INIT = 4'h8; + LUT2_L I_4693_0_a2_0_a2_0_a2_0_a2 ( + .I0(cfg_cfg_6102[229]), + .I1(com_cmm_cfg_wr_data_29_), + .LO(I_4693_0_a2_0_a2_0_a2_0_a2_182) + ); + defparam I_4688_0_a2_0_a2_0_a2_0_a2.INIT = 4'h8; + LUT2_L I_4688_0_a2_0_a2_0_a2_0_a2 ( + .I0(cfg_cfg_6102[230]), + .I1(com_cmm_cfg_wr_data_30_), + .LO(I_4688_0_a2_0_a2_0_a2_0_a2_183) + ); + defparam I_4683_0_a2_0_a2_0_a2_0_a2.INIT = 4'h8; + LUT2_L I_4683_0_a2_0_a2_0_a2_0_a2 ( + .I0(cfg_cfg_6102[231]), + .I1(com_cmm_cfg_wr_data_31_), + .LO(I_4683_0_a2_0_a2_0_a2_0_a2_184) + ); + defparam I_4678_0_a2_0_a2_0_a2_0_a2.INIT = 4'h8; + LUT2_L I_4678_0_a2_0_a2_0_a2_0_a2 ( + .I0(cfg_cfg_6102[232]), + .I1(com_cmm_cfg_wr_data_16_), + .LO(I_4678_0_a2_0_a2_0_a2_0_a2_185) + ); + defparam I_4673_0_a2_0_a2_0_a2.INIT = 4'h8; + LUT2_L I_4673_0_a2_0_a2_0_a2 ( + .I0(cfg_cfg_6102[203]), + .I1(com_cmm_cfg_wr_data_19_), + .LO(I_4673_0_a2_0_a2_0_a2_186) + ); + defparam I_4668_0_a2_0_a2_0_a2_0_a2.INIT = 4'h8; + LUT2_L I_4668_0_a2_0_a2_0_a2_0_a2 ( + .I0(cfg_cfg_6102[204]), + .I1(com_cmm_cfg_wr_data_20_), + .LO(I_4668_0_a2_0_a2_0_a2_0_a2_187) + ); + defparam I_4663_0_a2_0_a2_0_a2_0_a2.INIT = 4'h8; + LUT2_L I_4663_0_a2_0_a2_0_a2_0_a2 ( + .I0(cfg_cfg_6102[205]), + .I1(com_cmm_cfg_wr_data_21_), + .LO(I_4663_0_a2_0_a2_0_a2_0_a2_188) + ); + defparam I_4658_0_a2_0_a2_0_a2_0_a2.INIT = 4'h8; + LUT2_L I_4658_0_a2_0_a2_0_a2_0_a2 ( + .I0(cfg_cfg_6102[206]), + .I1(com_cmm_cfg_wr_data_22_), + .LO(I_4658_0_a2_0_a2_0_a2_0_a2_189) + ); + defparam I_4653_0_a2_0_a2_0_a2_0_a2.INIT = 4'h8; + LUT2_L I_4653_0_a2_0_a2_0_a2_0_a2 ( + .I0(cfg_cfg_6102[207]), + .I1(com_cmm_cfg_wr_data_23_), + .LO(I_4653_0_a2_0_a2_0_a2_0_a2_190) + ); + defparam I_4648_0_a2_0_a2_0_a2_0_a2.INIT = 4'h8; + LUT2_L I_4648_0_a2_0_a2_0_a2_0_a2 ( + .I0(cfg_cfg_6102[208]), + .I1(com_cmm_cfg_wr_data_8_), + .LO(I_4648_0_a2_0_a2_0_a2_0_a2_191) + ); + defparam I_4643_0_a2_0_a2_0_a2_0_a2.INIT = 4'h8; + LUT2_L I_4643_0_a2_0_a2_0_a2_0_a2 ( + .I0(cfg_cfg_6102[209]), + .I1(com_cmm_cfg_wr_data_9_), + .LO(I_4643_0_a2_0_a2_0_a2_0_a2_192) + ); + defparam I_4638_0_a2_0_a2_0_a2_0_a2.INIT = 4'h8; + LUT2_L I_4638_0_a2_0_a2_0_a2_0_a2 ( + .I0(cfg_cfg_6102[210]), + .I1(com_cmm_cfg_wr_data_10_), + .LO(I_4638_0_a2_0_a2_0_a2_0_a2_193) + ); + defparam I_4633_0_a2_0_a2_0_a2_0_a2.INIT = 4'h8; + LUT2_L I_4633_0_a2_0_a2_0_a2_0_a2 ( + .I0(cfg_cfg_6102[211]), + .I1(com_cmm_cfg_wr_data_11_), + .LO(I_4633_0_a2_0_a2_0_a2_0_a2_194) + ); + defparam I_4628_0_a2_0_a2_0_a2.INIT = 4'h8; + LUT2_L I_4628_0_a2_0_a2_0_a2 ( + .I0(cfg_cfg_6102[212]), + .I1(com_cmm_cfg_wr_data_12_), + .LO(I_4628_0_a2_0_a2_0_a2_195) + ); + defparam I_4623_0_a2_0_a2_0_a2.INIT = 4'h8; + LUT2_L I_4623_0_a2_0_a2_0_a2 ( + .I0(cfg_cfg_6102[213]), + .I1(com_cmm_cfg_wr_data_13_), + .LO(I_4623_0_a2_0_a2_0_a2_196) + ); + defparam I_4618_0_a2_0_a2_0_a2.INIT = 4'h8; + LUT2_L I_4618_0_a2_0_a2_0_a2 ( + .I0(cfg_cfg_6102[214]), + .I1(com_cmm_cfg_wr_data_14_), + .LO(I_4618_0_a2_0_a2_0_a2_197) + ); + defparam I_4613_0_a2_0_a2_0_a2.INIT = 4'h8; + LUT2_L I_4613_0_a2_0_a2_0_a2 ( + .I0(cfg_cfg_6102[215]), + .I1(com_cmm_cfg_wr_data_15_), + .LO(I_4613_0_a2_0_a2_0_a2_198) + ); + defparam I_4608_0_a2_0_a2_0_a2.INIT = 4'h8; + LUT2_L I_4608_0_a2_0_a2_0_a2 ( + .I0(cfg_cfg_6102[216]), + .I1(com_cmm_cfg_wr_data_0_), + .LO(I_4608_0_a2_0_a2_0_a2_199) + ); + defparam I_4603_0_a2_0_a2_0_a2.INIT = 4'h8; + LUT2_L I_4603_0_a2_0_a2_0_a2 ( + .I0(cfg_cfg_6102[217]), + .I1(com_cmm_cfg_wr_data_1_), + .LO(I_4603_0_a2_0_a2_0_a2_200) + ); + defparam I_4598_0_a2_0_a2_0_a2.INIT = 4'h8; + LUT2_L I_4598_0_a2_0_a2_0_a2 ( + .I0(cfg_cfg_6102[188]), + .I1(com_cmm_cfg_wr_data_4_), + .LO(I_4598_0_a2_0_a2_0_a2_201) + ); + defparam I_4593_0_a2_0_a2_0_a2.INIT = 4'h8; + LUT2_L I_4593_0_a2_0_a2_0_a2 ( + .I0(cfg_cfg_6102[189]), + .I1(com_cmm_cfg_wr_data_5_), + .LO(I_4593_0_a2_0_a2_0_a2_202) + ); + defparam I_4588_0_a2_0_a2_0_a2.INIT = 4'h8; + LUT2_L I_4588_0_a2_0_a2_0_a2 ( + .I0(cfg_cfg_6102[190]), + .I1(com_cmm_cfg_wr_data_6_), + .LO(I_4588_0_a2_0_a2_0_a2_203) + ); + defparam I_4583_0_a2_0_a2_0_a2.INIT = 4'h8; + LUT2_L I_4583_0_a2_0_a2_0_a2 ( + .I0(cfg_cfg_6102[191]), + .I1(com_cmm_cfg_wr_data_7_), + .LO(I_4583_0_a2_0_a2_0_a2_204) + ); + defparam I_4578_0_a2_0_a2_0_a2_0_a2.INIT = 4'h8; + LUT2_L I_4578_0_a2_0_a2_0_a2_0_a2 ( + .I0(cfg_cfg_6102[196]), + .I1(com_cmm_cfg_wr_data_28_), + .LO(I_4578_0_a2_0_a2_0_a2_0_a2_205) + ); + defparam I_4573_0_a2_0_a2_0_a2_0_a2.INIT = 4'h8; + LUT2_L I_4573_0_a2_0_a2_0_a2_0_a2 ( + .I0(cfg_cfg_6102[197]), + .I1(com_cmm_cfg_wr_data_29_), + .LO(I_4573_0_a2_0_a2_0_a2_0_a2_206) + ); + defparam I_4568_0_a2_0_a2_0_a2_0_a2.INIT = 4'h8; + LUT2_L I_4568_0_a2_0_a2_0_a2_0_a2 ( + .I0(cfg_cfg_6102[198]), + .I1(com_cmm_cfg_wr_data_30_), + .LO(I_4568_0_a2_0_a2_0_a2_0_a2_207) + ); + defparam I_4563_0_a2_0_a2_0_a2_0_a2.INIT = 4'h8; + LUT2_L I_4563_0_a2_0_a2_0_a2_0_a2 ( + .I0(cfg_cfg_6102[199]), + .I1(com_cmm_cfg_wr_data_31_), + .LO(I_4563_0_a2_0_a2_0_a2_0_a2_208) + ); + defparam I_4558_0_a2_0_a2_0_a2.INIT = 4'h8; + LUT2_L I_4558_0_a2_0_a2_0_a2 ( + .I0(cfg_cfg_6102[200]), + .I1(com_cmm_cfg_wr_data_16_), + .LO(I_4558_0_a2_0_a2_0_a2_209) + ); + defparam I_4553_0_a2_0_a2_0_a2.INIT = 4'h8; + LUT2_L I_4553_0_a2_0_a2_0_a2 ( + .I0(cfg_cfg_6102[201]), + .I1(com_cmm_cfg_wr_data_17_), + .LO(I_4553_0_a2_0_a2_0_a2_210) + ); + defparam I_4548_0_a2_0_a2_0_a2.INIT = 4'h8; + LUT2_L I_4548_0_a2_0_a2_0_a2 ( + .I0(cfg_cfg_6102[202]), + .I1(com_cmm_cfg_wr_data_18_), + .LO(I_4548_0_a2_0_a2_0_a2_211) + ); + defparam I_4543_0_a2_0_a2_0_a2_0_a2.INIT = 4'h8; + LUT2_L I_4543_0_a2_0_a2_0_a2_0_a2 ( + .I0(cfg_cfg_6102[173]), + .I1(com_cmm_cfg_wr_data_21_), + .LO(I_4543_0_a2_0_a2_0_a2_0_a2_212) + ); + defparam I_4538_0_a2_0_a2_0_a2_0_a2.INIT = 4'h8; + LUT2_L I_4538_0_a2_0_a2_0_a2_0_a2 ( + .I0(cfg_cfg_6102[174]), + .I1(com_cmm_cfg_wr_data_22_), + .LO(I_4538_0_a2_0_a2_0_a2_0_a2_213) + ); + defparam I_4533_0_a2_0_a2_0_a2_0_a2.INIT = 4'h8; + LUT2_L I_4533_0_a2_0_a2_0_a2_0_a2 ( + .I0(cfg_cfg_6102[175]), + .I1(com_cmm_cfg_wr_data_23_), + .LO(I_4533_0_a2_0_a2_0_a2_0_a2_214) + ); + defparam I_4528_0_a2_0_a2_0_a2_0_a2.INIT = 4'h8; + LUT2_L I_4528_0_a2_0_a2_0_a2_0_a2 ( + .I0(cfg_cfg_6102[176]), + .I1(com_cmm_cfg_wr_data_8_), + .LO(I_4528_0_a2_0_a2_0_a2_0_a2_215) + ); + defparam I_4523_0_a2_0_a2_0_a2_0_a2.INIT = 4'h8; + LUT2_L I_4523_0_a2_0_a2_0_a2_0_a2 ( + .I0(cfg_cfg_6102[177]), + .I1(com_cmm_cfg_wr_data_9_), + .LO(I_4523_0_a2_0_a2_0_a2_0_a2_216) + ); + defparam I_4518_0_a2_0_a2_0_a2_0_a2.INIT = 4'h8; + LUT2_L I_4518_0_a2_0_a2_0_a2_0_a2 ( + .I0(cfg_cfg_6102[178]), + .I1(com_cmm_cfg_wr_data_10_), + .LO(I_4518_0_a2_0_a2_0_a2_0_a2_217) + ); + defparam I_4513_0_a2_0_a2_0_a2_0_a2.INIT = 4'h8; + LUT2_L I_4513_0_a2_0_a2_0_a2_0_a2 ( + .I0(cfg_cfg_6102[179]), + .I1(com_cmm_cfg_wr_data_11_), + .LO(I_4513_0_a2_0_a2_0_a2_0_a2_218) + ); + defparam I_4508_0_a2_0_a2_0_a2.INIT = 4'h8; + LUT2_L I_4508_0_a2_0_a2_0_a2 ( + .I0(cfg_cfg_6102[180]), + .I1(com_cmm_cfg_wr_data_12_), + .LO(I_4508_0_a2_0_a2_0_a2_219) + ); + defparam I_4503_0_a2_0_a2_0_a2.INIT = 4'h8; + LUT2_L I_4503_0_a2_0_a2_0_a2 ( + .I0(cfg_cfg_6102[181]), + .I1(com_cmm_cfg_wr_data_13_), + .LO(I_4503_0_a2_0_a2_0_a2_220) + ); + defparam I_4498_0_a2_0_a2_0_a2.INIT = 4'h8; + LUT2_L I_4498_0_a2_0_a2_0_a2 ( + .I0(cfg_cfg_6102[182]), + .I1(com_cmm_cfg_wr_data_14_), + .LO(I_4498_0_a2_0_a2_0_a2_221) + ); + defparam I_4493_0_a2_0_a2_0_a2.INIT = 4'h8; + LUT2_L I_4493_0_a2_0_a2_0_a2 ( + .I0(cfg_cfg_6102[183]), + .I1(com_cmm_cfg_wr_data_15_), + .LO(I_4493_0_a2_0_a2_0_a2_222) + ); + defparam I_4488_0_a2_0_a2_0_a2.INIT = 4'h8; + LUT2_L I_4488_0_a2_0_a2_0_a2 ( + .I0(cfg_cfg_6102[184]), + .I1(com_cmm_cfg_wr_data_0_), + .LO(I_4488_0_a2_0_a2_0_a2_223) + ); + defparam I_4483_0_a2_0_a2_0_a2.INIT = 4'h8; + LUT2_L I_4483_0_a2_0_a2_0_a2 ( + .I0(cfg_cfg_6102[185]), + .I1(com_cmm_cfg_wr_data_1_), + .LO(I_4483_0_a2_0_a2_0_a2_224) + ); + defparam I_4478_0_a2_0_a2_0_a2.INIT = 4'h8; + LUT2_L I_4478_0_a2_0_a2_0_a2 ( + .I0(cfg_cfg_6102[186]), + .I1(com_cmm_cfg_wr_data_2_), + .LO(I_4478_0_a2_0_a2_0_a2_225) + ); + defparam I_4473_0_a2_0_a2_0_a2.INIT = 4'h8; + LUT2_L I_4473_0_a2_0_a2_0_a2 ( + .I0(cfg_cfg_6102[187]), + .I1(com_cmm_cfg_wr_data_3_), + .LO(I_4473_0_a2_0_a2_0_a2_226) + ); + defparam I_4468_0_a2_0_a2_0_a2.INIT = 4'h8; + LUT2_L I_4468_0_a2_0_a2_0_a2 ( + .I0(cfg_cfg_6102[158]), + .I1(com_cmm_cfg_wr_data_6_), + .LO(I_4468_0_a2_0_a2_0_a2_227) + ); + defparam I_4463_0_a2_0_a2_0_a2.INIT = 4'h8; + LUT2_L I_4463_0_a2_0_a2_0_a2 ( + .I0(cfg_cfg_6102[159]), + .I1(com_cmm_cfg_wr_data_7_), + .LO(I_4463_0_a2_0_a2_0_a2_228) + ); + defparam I_4458_0_a2_0_a2_0_a2_0_a2.INIT = 4'h8; + LUT2_L I_4458_0_a2_0_a2_0_a2_0_a2 ( + .I0(cfg_cfg_6102[164]), + .I1(com_cmm_cfg_wr_data_28_), + .LO(I_4458_0_a2_0_a2_0_a2_0_a2_229) + ); + defparam I_4453_0_a2_0_a2_0_a2_0_a2.INIT = 4'h8; + LUT2_L I_4453_0_a2_0_a2_0_a2_0_a2 ( + .I0(cfg_cfg_6102[165]), + .I1(com_cmm_cfg_wr_data_29_), + .LO(I_4453_0_a2_0_a2_0_a2_0_a2_230) + ); + defparam I_4448_0_a2_0_a2_0_a2_0_a2.INIT = 4'h8; + LUT2_L I_4448_0_a2_0_a2_0_a2_0_a2 ( + .I0(cfg_cfg_6102[166]), + .I1(com_cmm_cfg_wr_data_30_), + .LO(I_4448_0_a2_0_a2_0_a2_0_a2_231) + ); + defparam I_4443_0_a2_0_a2_0_a2_0_a2.INIT = 4'h8; + LUT2_L I_4443_0_a2_0_a2_0_a2_0_a2 ( + .I0(cfg_cfg_6102[167]), + .I1(com_cmm_cfg_wr_data_31_), + .LO(I_4443_0_a2_0_a2_0_a2_0_a2_232) + ); + defparam I_4438_0_a2_0_a2_0_a2.INIT = 4'h8; + LUT2_L I_4438_0_a2_0_a2_0_a2 ( + .I0(cfg_cfg_6102[168]), + .I1(com_cmm_cfg_wr_data_16_), + .LO(I_4438_0_a2_0_a2_0_a2_233) + ); + defparam I_4433_0_a2_0_a2_0_a2.INIT = 4'h8; + LUT2_L I_4433_0_a2_0_a2_0_a2 ( + .I0(cfg_cfg_6102[169]), + .I1(com_cmm_cfg_wr_data_17_), + .LO(I_4433_0_a2_0_a2_0_a2_234) + ); + defparam I_4428_0_a2_0_a2_0_a2.INIT = 4'h8; + LUT2_L I_4428_0_a2_0_a2_0_a2 ( + .I0(cfg_cfg_6102[170]), + .I1(com_cmm_cfg_wr_data_18_), + .LO(I_4428_0_a2_0_a2_0_a2_235) + ); + defparam I_4423_0_a2_0_a2_0_a2.INIT = 4'h8; + LUT2_L I_4423_0_a2_0_a2_0_a2 ( + .I0(cfg_cfg_6102[171]), + .I1(com_cmm_cfg_wr_data_19_), + .LO(I_4423_0_a2_0_a2_0_a2_236) + ); + defparam I_4418_0_a2_0_a2_0_a2_0_a2.INIT = 4'h8; + LUT2_L I_4418_0_a2_0_a2_0_a2_0_a2 ( + .I0(cfg_cfg_6102[172]), + .I1(com_cmm_cfg_wr_data_20_), + .LO(I_4418_0_a2_0_a2_0_a2_0_a2_237) + ); + defparam I_4413_0_a2_0_a2_0_a2_0_a2.INIT = 4'h8; + LUT2_L I_4413_0_a2_0_a2_0_a2_0_a2 ( + .I0(cfg_cfg_6102[143]), + .I1(com_cmm_cfg_wr_data_23_), + .LO(I_4413_0_a2_0_a2_0_a2_0_a2_238) + ); + defparam I_4408_0_a2_0_a2_0_a2_0_a2.INIT = 4'h8; + LUT2_L I_4408_0_a2_0_a2_0_a2_0_a2 ( + .I0(cfg_cfg_6102[144]), + .I1(com_cmm_cfg_wr_data_8_), + .LO(I_4408_0_a2_0_a2_0_a2_0_a2_239) + ); + defparam I_4403_0_a2_0_a2_0_a2_0_a2.INIT = 4'h8; + LUT2_L I_4403_0_a2_0_a2_0_a2_0_a2 ( + .I0(cfg_cfg_6102[145]), + .I1(com_cmm_cfg_wr_data_9_), + .LO(I_4403_0_a2_0_a2_0_a2_0_a2_240) + ); + defparam I_4398_0_a2_0_a2_0_a2_0_a2.INIT = 4'h8; + LUT2_L I_4398_0_a2_0_a2_0_a2_0_a2 ( + .I0(cfg_cfg_6102[146]), + .I1(com_cmm_cfg_wr_data_10_), + .LO(I_4398_0_a2_0_a2_0_a2_0_a2_241) + ); + defparam I_4393_0_a2_0_a2_0_a2_0_a2.INIT = 4'h8; + LUT2_L I_4393_0_a2_0_a2_0_a2_0_a2 ( + .I0(cfg_cfg_6102[147]), + .I1(com_cmm_cfg_wr_data_11_), + .LO(I_4393_0_a2_0_a2_0_a2_0_a2_242) + ); + defparam I_4388_0_a2_0_a2_0_a2.INIT = 4'h8; + LUT2_L I_4388_0_a2_0_a2_0_a2 ( + .I0(cfg_cfg_6102[148]), + .I1(com_cmm_cfg_wr_data_12_), + .LO(I_4388_0_a2_0_a2_0_a2_243) + ); + defparam I_4383_0_a2_0_a2_0_a2.INIT = 4'h8; + LUT2_L I_4383_0_a2_0_a2_0_a2 ( + .I0(cfg_cfg_6102[149]), + .I1(com_cmm_cfg_wr_data_13_), + .LO(I_4383_0_a2_0_a2_0_a2_244) + ); + defparam I_4378_0_a2_0_a2_0_a2.INIT = 4'h8; + LUT2_L I_4378_0_a2_0_a2_0_a2 ( + .I0(cfg_cfg_6102[150]), + .I1(com_cmm_cfg_wr_data_14_), + .LO(I_4378_0_a2_0_a2_0_a2_245) + ); + defparam I_4373_0_a2_0_a2_0_a2.INIT = 4'h8; + LUT2_L I_4373_0_a2_0_a2_0_a2 ( + .I0(cfg_cfg_6102[151]), + .I1(com_cmm_cfg_wr_data_15_), + .LO(I_4373_0_a2_0_a2_0_a2_246) + ); + defparam I_4368_0_a2_0_a2_0_a2.INIT = 4'h8; + LUT2_L I_4368_0_a2_0_a2_0_a2 ( + .I0(cfg_cfg_6102[152]), + .I1(com_cmm_cfg_wr_data_0_), + .LO(I_4368_0_a2_0_a2_0_a2_247) + ); + defparam I_4363_0_a2_0_a2_0_a2.INIT = 4'h8; + LUT2_L I_4363_0_a2_0_a2_0_a2 ( + .I0(cfg_cfg_6102[153]), + .I1(com_cmm_cfg_wr_data_1_), + .LO(I_4363_0_a2_0_a2_0_a2_248) + ); + defparam I_4358_0_a2_0_a2_0_a2.INIT = 4'h8; + LUT2_L I_4358_0_a2_0_a2_0_a2 ( + .I0(cfg_cfg_6102[154]), + .I1(com_cmm_cfg_wr_data_2_), + .LO(I_4358_0_a2_0_a2_0_a2_249) + ); + defparam I_4353_0_a2_0_a2_0_a2.INIT = 4'h8; + LUT2_L I_4353_0_a2_0_a2_0_a2 ( + .I0(cfg_cfg_6102[155]), + .I1(com_cmm_cfg_wr_data_3_), + .LO(I_4353_0_a2_0_a2_0_a2_250) + ); + defparam I_4348_0_a2_0_a2_0_a2.INIT = 4'h8; + LUT2_L I_4348_0_a2_0_a2_0_a2 ( + .I0(cfg_cfg_6102[156]), + .I1(com_cmm_cfg_wr_data_4_), + .LO(I_4348_0_a2_0_a2_0_a2_251) + ); + defparam I_4343_0_a2_0_a2_0_a2.INIT = 4'h8; + LUT2_L I_4343_0_a2_0_a2_0_a2 ( + .I0(cfg_cfg_6102[157]), + .I1(com_cmm_cfg_wr_data_5_), + .LO(I_4343_0_a2_0_a2_0_a2_252) + ); + defparam I_4338_0_a2_0_a2_0_a2_0_a2.INIT = 4'h8; + LUT2_L I_4338_0_a2_0_a2_0_a2_0_a2 ( + .I0(cfg_cfg_6102[132]), + .I1(com_cmm_cfg_wr_data_28_), + .LO(I_4338_0_a2_0_a2_0_a2_0_a2_253) + ); + defparam I_4333_0_a2_0_a2_0_a2_0_a2.INIT = 4'h8; + LUT2_L I_4333_0_a2_0_a2_0_a2_0_a2 ( + .I0(cfg_cfg_6102[133]), + .I1(com_cmm_cfg_wr_data_29_), + .LO(I_4333_0_a2_0_a2_0_a2_0_a2_254) + ); + defparam I_4328_0_a2_0_a2_0_a2_0_a2.INIT = 4'h8; + LUT2_L I_4328_0_a2_0_a2_0_a2_0_a2 ( + .I0(cfg_cfg_6102[134]), + .I1(com_cmm_cfg_wr_data_30_), + .LO(I_4328_0_a2_0_a2_0_a2_0_a2_255) + ); + defparam I_4323_0_a2_0_a2_0_a2_0_a2.INIT = 4'h8; + LUT2_L I_4323_0_a2_0_a2_0_a2_0_a2 ( + .I0(cfg_cfg_6102[135]), + .I1(com_cmm_cfg_wr_data_31_), + .LO(I_4323_0_a2_0_a2_0_a2_0_a2_256) + ); + defparam I_4318_0_a2_0_a2_0_a2.INIT = 4'h8; + LUT2_L I_4318_0_a2_0_a2_0_a2 ( + .I0(cfg_cfg_6102[136]), + .I1(com_cmm_cfg_wr_data_16_), + .LO(I_4318_0_a2_0_a2_0_a2_257) + ); + defparam I_4313_0_a2_0_a2_0_a2.INIT = 4'h8; + LUT2_L I_4313_0_a2_0_a2_0_a2 ( + .I0(cfg_cfg_6102[137]), + .I1(com_cmm_cfg_wr_data_17_), + .LO(I_4313_0_a2_0_a2_0_a2_258) + ); + defparam I_4308_0_a2_0_a2_0_a2.INIT = 4'h8; + LUT2_L I_4308_0_a2_0_a2_0_a2 ( + .I0(cfg_cfg_6102[138]), + .I1(com_cmm_cfg_wr_data_18_), + .LO(I_4308_0_a2_0_a2_0_a2_259) + ); + defparam I_4303_0_a2_0_a2_0_a2.INIT = 4'h8; + LUT2_L I_4303_0_a2_0_a2_0_a2 ( + .I0(cfg_cfg_6102[139]), + .I1(com_cmm_cfg_wr_data_19_), + .LO(I_4303_0_a2_0_a2_0_a2_260) + ); + defparam I_4298_0_a2_0_a2_0_a2_0_a2.INIT = 4'h8; + LUT2_L I_4298_0_a2_0_a2_0_a2_0_a2 ( + .I0(cfg_cfg_6102[140]), + .I1(com_cmm_cfg_wr_data_20_), + .LO(I_4298_0_a2_0_a2_0_a2_0_a2_261) + ); + defparam I_4293_0_a2_0_a2_0_a2_0_a2.INIT = 4'h8; + LUT2_L I_4293_0_a2_0_a2_0_a2_0_a2 ( + .I0(cfg_cfg_6102[141]), + .I1(com_cmm_cfg_wr_data_21_), + .LO(I_4293_0_a2_0_a2_0_a2_0_a2_262) + ); + defparam I_4288_0_a2_0_a2_0_a2_0_a2.INIT = 4'h8; + LUT2_L I_4288_0_a2_0_a2_0_a2_0_a2 ( + .I0(cfg_cfg_6102[142]), + .I1(com_cmm_cfg_wr_data_22_), + .LO(I_4288_0_a2_0_a2_0_a2_0_a2_263) + ); + defparam I_4283_0_a2_0_a2_0_a2_0_a2.INIT = 4'h8; + LUT2_L I_4283_0_a2_0_a2_0_a2_0_a2 ( + .I0(cfg_cfg_6102[113]), + .I1(com_cmm_cfg_wr_data_9_), + .LO(I_4283_0_a2_0_a2_0_a2_0_a2_264) + ); + defparam I_4278_0_a2_0_a2_0_a2_0_a2.INIT = 4'h8; + LUT2_L I_4278_0_a2_0_a2_0_a2_0_a2 ( + .I0(cfg_cfg_6102[114]), + .I1(com_cmm_cfg_wr_data_10_), + .LO(I_4278_0_a2_0_a2_0_a2_0_a2_265) + ); + defparam I_4273_0_a2_0_a2_0_a2_0_a2.INIT = 4'h8; + LUT2_L I_4273_0_a2_0_a2_0_a2_0_a2 ( + .I0(cfg_cfg_6102[115]), + .I1(com_cmm_cfg_wr_data_11_), + .LO(I_4273_0_a2_0_a2_0_a2_0_a2_266) + ); + defparam I_4268_0_a2_0_a2_0_a2.INIT = 4'h8; + LUT2_L I_4268_0_a2_0_a2_0_a2 ( + .I0(cfg_cfg_6102[116]), + .I1(com_cmm_cfg_wr_data_12_), + .LO(I_4268_0_a2_0_a2_0_a2_267) + ); + defparam I_4263_0_a2_0_a2_0_a2.INIT = 4'h8; + LUT2_L I_4263_0_a2_0_a2_0_a2 ( + .I0(cfg_cfg_6102[117]), + .I1(com_cmm_cfg_wr_data_13_), + .LO(I_4263_0_a2_0_a2_0_a2_268) + ); + defparam I_4258_0_a2_0_a2_0_a2.INIT = 4'h8; + LUT2_L I_4258_0_a2_0_a2_0_a2 ( + .I0(cfg_cfg_6102[118]), + .I1(com_cmm_cfg_wr_data_14_), + .LO(I_4258_0_a2_0_a2_0_a2_269) + ); + defparam I_4253_0_a2_0_a2_0_a2.INIT = 4'h8; + LUT2_L I_4253_0_a2_0_a2_0_a2 ( + .I0(cfg_cfg_6102[119]), + .I1(com_cmm_cfg_wr_data_15_), + .LO(I_4253_0_a2_0_a2_0_a2_270) + ); + defparam I_4248_0_a2_0_a2_0_a2.INIT = 4'h8; + LUT2_L I_4248_0_a2_0_a2_0_a2 ( + .I0(cfg_cfg_6102[120]), + .I1(com_cmm_cfg_wr_data_0_), + .LO(I_4248_0_a2_0_a2_0_a2_271) + ); + defparam I_4243_0_a2_0_a2_0_a2.INIT = 4'h8; + LUT2_L I_4243_0_a2_0_a2_0_a2 ( + .I0(cfg_cfg_6102[121]), + .I1(com_cmm_cfg_wr_data_1_), + .LO(I_4243_0_a2_0_a2_0_a2_272) + ); + defparam I_4238_0_a2_0_a2_0_a2.INIT = 4'h8; + LUT2_L I_4238_0_a2_0_a2_0_a2 ( + .I0(cfg_cfg_6102[122]), + .I1(com_cmm_cfg_wr_data_2_), + .LO(I_4238_0_a2_0_a2_0_a2_273) + ); + defparam I_4233_0_a2_0_a2_0_a2.INIT = 4'h8; + LUT2_L I_4233_0_a2_0_a2_0_a2 ( + .I0(cfg_cfg_6102[123]), + .I1(com_cmm_cfg_wr_data_3_), + .LO(I_4233_0_a2_0_a2_0_a2_274) + ); + defparam I_4228_0_a2_0_a2_0_a2.INIT = 4'h8; + LUT2_L I_4228_0_a2_0_a2_0_a2 ( + .I0(cfg_cfg_6102[124]), + .I1(com_cmm_cfg_wr_data_4_), + .LO(I_4228_0_a2_0_a2_0_a2_275) + ); + defparam I_4223_0_a2_0_a2_0_a2.INIT = 4'h8; + LUT2_L I_4223_0_a2_0_a2_0_a2 ( + .I0(cfg_cfg_6102[125]), + .I1(com_cmm_cfg_wr_data_5_), + .LO(I_4223_0_a2_0_a2_0_a2_276) + ); + defparam I_4218_0_a2_0_a2_0_a2.INIT = 4'h8; + LUT2_L I_4218_0_a2_0_a2_0_a2 ( + .I0(cfg_cfg_6102[126]), + .I1(com_cmm_cfg_wr_data_6_), + .LO(I_4218_0_a2_0_a2_0_a2_277) + ); + defparam I_4213_0_a2_0_a2_0_a2.INIT = 4'h8; + LUT2_L I_4213_0_a2_0_a2_0_a2 ( + .I0(cfg_cfg_6102[127]), + .I1(com_cmm_cfg_wr_data_7_), + .LO(I_4213_0_a2_0_a2_0_a2_278) + ); + defparam I_4208_0_a2_0_a2_0_a2_0_a2.INIT = 4'h8; + LUT2_L I_4208_0_a2_0_a2_0_a2_0_a2 ( + .I0(cfg_cfg_6102[100]), + .I1(com_cmm_cfg_wr_data_28_), + .LO(I_4208_0_a2_0_a2_0_a2_0_a2_279) + ); + defparam I_4203_0_a2_0_a2_0_a2_0_a2.INIT = 4'h8; + LUT2_L I_4203_0_a2_0_a2_0_a2_0_a2 ( + .I0(cfg_cfg_6102[101]), + .I1(com_cmm_cfg_wr_data_29_), + .LO(I_4203_0_a2_0_a2_0_a2_0_a2_280) + ); + defparam I_4198_0_a2_0_a2_0_a2_0_a2.INIT = 4'h8; + LUT2_L I_4198_0_a2_0_a2_0_a2_0_a2 ( + .I0(cfg_cfg_6102[102]), + .I1(com_cmm_cfg_wr_data_30_), + .LO(I_4198_0_a2_0_a2_0_a2_0_a2_281) + ); + defparam I_4193_0_a2_0_a2_0_a2_0_a2.INIT = 4'h8; + LUT2_L I_4193_0_a2_0_a2_0_a2_0_a2 ( + .I0(cfg_cfg_6102[103]), + .I1(com_cmm_cfg_wr_data_31_), + .LO(I_4193_0_a2_0_a2_0_a2_0_a2_282) + ); + defparam I_4188_0_a2_0_a2_0_a2.INIT = 4'h8; + LUT2_L I_4188_0_a2_0_a2_0_a2 ( + .I0(cfg_cfg_6102[104]), + .I1(com_cmm_cfg_wr_data_16_), + .LO(I_4188_0_a2_0_a2_0_a2_283) + ); + defparam I_4183_0_a2_0_a2_0_a2.INIT = 4'h8; + LUT2_L I_4183_0_a2_0_a2_0_a2 ( + .I0(cfg_cfg_6102[105]), + .I1(com_cmm_cfg_wr_data_17_), + .LO(I_4183_0_a2_0_a2_0_a2_284) + ); + defparam I_4178_0_a2_0_a2_0_a2.INIT = 4'h8; + LUT2_L I_4178_0_a2_0_a2_0_a2 ( + .I0(cfg_cfg_6102[106]), + .I1(com_cmm_cfg_wr_data_18_), + .LO(I_4178_0_a2_0_a2_0_a2_285) + ); + defparam I_4173_0_a2_0_a2_0_a2.INIT = 4'h8; + LUT2_L I_4173_0_a2_0_a2_0_a2 ( + .I0(cfg_cfg_6102[107]), + .I1(com_cmm_cfg_wr_data_19_), + .LO(I_4173_0_a2_0_a2_0_a2_286) + ); + defparam I_4168_0_a2_0_a2_0_a2_0_a2.INIT = 4'h8; + LUT2_L I_4168_0_a2_0_a2_0_a2_0_a2 ( + .I0(cfg_cfg_6102[108]), + .I1(com_cmm_cfg_wr_data_20_), + .LO(I_4168_0_a2_0_a2_0_a2_0_a2_287) + ); + defparam I_4163_0_a2_0_a2_0_a2_0_a2.INIT = 4'h8; + LUT2_L I_4163_0_a2_0_a2_0_a2_0_a2 ( + .I0(cfg_cfg_6102[109]), + .I1(com_cmm_cfg_wr_data_21_), + .LO(I_4163_0_a2_0_a2_0_a2_0_a2_288) + ); + defparam I_4158_0_a2_0_a2_0_a2_0_a2.INIT = 4'h8; + LUT2_L I_4158_0_a2_0_a2_0_a2_0_a2 ( + .I0(cfg_cfg_6102[110]), + .I1(com_cmm_cfg_wr_data_22_), + .LO(I_4158_0_a2_0_a2_0_a2_0_a2_289) + ); + defparam I_4153_0_a2_0_a2_0_a2_0_a2.INIT = 4'h8; + LUT2_L I_4153_0_a2_0_a2_0_a2_0_a2 ( + .I0(cfg_cfg_6102[111]), + .I1(com_cmm_cfg_wr_data_23_), + .LO(I_4153_0_a2_0_a2_0_a2_0_a2_290) + ); + defparam I_4148_0_a2_0_a2_0_a2_0_a2.INIT = 4'h8; + LUT2_L I_4148_0_a2_0_a2_0_a2_0_a2 ( + .I0(cfg_cfg_6102[112]), + .I1(com_cmm_cfg_wr_data_8_), + .LO(I_4148_0_a2_0_a2_0_a2_0_a2_291) + ); + defparam m4.INIT = 16'h9669; + LUT4_L m4 ( + .I0(N_56022_i), + .I1(com_tlm_cmmt_err_rbuf_overflow), + .I2(com_tlm_cmmt_err_tlp_malformed), + .I3(m4_1_292), + .LO(N_5_i) + ); + defparam m12_0.INIT = 4'h4; + LUT2_L m12_0 ( + .I0(N_57661), + .I1(m12_0_39395_293), + .LO(N_13_i) + ); + defparam m14_0_a2.INIT = 8'h40; + LUT3_L m14_0_a2 ( + .I0(N_56022_i), + .I1(N_56469_i), + .I2(com_tlm_cmmt_err_tlp_malformed), + .LO(com_cmm_u_cmm_errman_wtd_ftl_to_incrdf2) + ); + defparam N_86294_i.INIT = 16'hBAAA; + LUT4_L N_86294_i ( + .I0(m4_3_0_0_0_0_a2_0_294), + .I1(com_cmm_u_cmm_dataproducer_req_gnt_code[1]), + .I2(com_cmm_u_cmm_dataproducer_req_gnt_code[2]), + .I3(com_cmm_u_cmm_dataproducer_req_gnt_code[3]), + .LO(N_86294_i_295) + ); + defparam I_39706.INIT = 4'h1; + LUT1_L I_39706 ( + .I0(cfg_trn_pending_n), + .LO(cfg_trn_pending_n_i) + ); + defparam N_6_i.INIT = 16'h9E69; + LUT4_L N_6_i ( + .I0(com_cmm_u_cmm_errman_wtd_nfl_add_input_five_n_d_296), + .I1(com_cmm_u_cmm_errman_wtd_nfl_add_input_four_n_d_297), + .I2(com_cmm_u_cmm_errman_wtd_nfl_add_input_one_d_298), + .I3(com_cmm_u_cmm_errman_wtd_nfl_add_input_two_n_d_299), + .LO(N_6_i_300) + ); + defparam m9.INIT = 16'h71E7; + LUT4_L m9 ( + .I0(com_cmm_u_cmm_errman_wtd_nfl_add_input_five_n_d_296), + .I1(com_cmm_u_cmm_errman_wtd_nfl_add_input_four_n_d_297), + .I2(com_cmm_u_cmm_errman_wtd_nfl_add_input_one_d_298), + .I3(com_cmm_u_cmm_errman_wtd_nfl_add_input_two_n_d_299), + .LO(com_cmm_u_cmm_errman_wtd_nfl_to_incr_0df1) + ); + defparam m11.INIT = 16'h0010; + LUT4_L m11 ( + .I0(com_cmm_u_cmm_errman_wtd_nfl_add_input_five_n_d_296), + .I1(com_cmm_u_cmm_errman_wtd_nfl_add_input_four_n_d_297), + .I2(com_cmm_u_cmm_errman_wtd_nfl_add_input_one_d_298), + .I3(com_cmm_u_cmm_errman_wtd_nfl_add_input_two_n_d_299), + .LO(com_cmm_u_cmm_errman_wtd_nfl_to_incr_0df2) + ); + defparam N_78313_i.INIT = 16'h353C; + LUT4_L N_78313_i ( + .I0(m7_0_301), + .I1(m3_0_302), + .I2(m24_303), + .I3(com_cmm_u_cmm_errman_wtd_cor_add_input_five_n_d_104), + .LO(N_78313_i_304) + ); + defparam m17.INIT = 16'h21ED; + LUT4_L m17 ( + .I0(m13_0_305), + .I1(m24_303), + .I2(com_cmm_u_cmm_errman_wtd_cor_add_input_five_n_d_104), + .I3(m17_1_306), + .LO(com_cmm_u_cmm_errman_wtd_cor_to_incr_0df1) + ); + defparam G_17.INIT = 8'h96; + LUT3 G_17 ( + .I0(N_19_1), + .I1(d64_i_m3_0_6_), + .I2(d64_i_m3_0_47_), + .O(N_19) + ); + defparam m2_0_0.INIT = 8'h07; + LUT3 m2_0_0 ( + .I0(plm_sym_sym_gen_next_addr[0]), + .I1(plm_sym_sym_gen_next_addr[1]), + .I2(plm_sym_sym_gen_next_addr[2]), + .O(N_150) + ); + defparam G_2711.INIT = 4'h4; + LUT2 G_2711 ( + .I0(plm_sym_sym_gen_next_addr[0]), + .I1(plm_sym_sym_gen_next_addr[3]), + .O(N_2766) + ); + defparam I_5354_0_a2_i_i_a3_0_a2.INIT = 8'h04; + LUT3 I_5354_0_a2_i_i_a3_0_a2 ( + .I0(N_29556_i), + .I1(N_56155_i), + .I2(plm_fsm_rc_counter_ts2_2_reg_rx_expired_67), + .O(I_5354_0_a2_i_i_a3_0_a2_307) + ); + defparam I_5318_i_0_i_a3_0_a2.INIT = 8'h04; + LUT3 I_5318_i_0_i_a3_0_a2 ( + .I0(N_29556_i), + .I1(N_56156_i), + .I2(plm_fsm_rc_counter_ts2_0_reg_rx_expired_69), + .O(I_5318_i_0_i_a3_0_a2_308) + ); + defparam I_5336_i_0_i_a3_0_a2.INIT = 16'h0400; + LUT4 I_5336_i_0_i_a3_0_a2 ( + .I0(N_29556_i), + .I1(N_56029_i), + .I2(plm_fsm_rc_counter_ts2_1_reg_rx_expired_309), + .I3(plm_rx1_ts2_c), + .O(I_5336_i_0_i_a3_0_a2_19) + ); + defparam I_5070_i_0_0_0.INIT = 8'h02; + LUT3 I_5070_i_0_0_0 ( + .I0(N_56156_i), + .I1(N_56513_i), + .I2(plm_fsm_cc_counter0_reg_rx_expired_71), + .O(N_15208_i) + ); + defparam I_5088_i_0_0_0.INIT = 16'h0200; + LUT4 I_5088_i_0_0_0 ( + .I0(N_56029_i), + .I1(N_56513_i), + .I2(plm_fsm_cc_counter1_reg_rx_expired_310), + .I3(plm_rx1_ts2_c), + .O(N_14477_i) + ); + defparam I_5106_0_a2_i_0_0.INIT = 8'h02; + LUT3 I_5106_0_a2_i_0_0 ( + .I0(N_56155_i), + .I1(N_56513_i), + .I2(plm_fsm_cc_counter2_reg_rx_expired_73), + .O(N_28971_i) + ); + defparam I_5166_i_0_0_0.INIT = 8'h08; + LUT3 I_5166_i_0_0_0 ( + .I0(N_59396_1), + .I1(plm_fsm_reg_state_13__76), + .I2(plm_fsm_rl_counter0_reg_rx_expired_75), + .O(N_15210_i) + ); + MUXF5 m25 ( + .I0(m25_am_108), + .I1(m25_bm_311), + .O(com_cmm_u_cmm_errman_wtd_cor_to_incr_0df2), + .S(m24_303) + ); + defparam m25_bm.INIT = 16'h022B; + LUT4 m25_bm ( + .I0(com_cmm_u_cmm_errman_wtd_cor_add_input_one_d_109), + .I1(com_cmm_u_cmm_errman_wtd_cor_add_input_six_n_d_110), + .I2(com_cmm_u_cmm_errman_wtd_cor_add_input_three_n_d_105), + .I3(com_cmm_u_cmm_errman_wtd_cor_add_input_two_n_d_106), + .O(m25_bm_311) + ); + defparam m17_1.INIT = 16'h422B; + LUT4 m17_1 ( + .I0(com_cmm_u_cmm_errman_wtd_cor_add_input_one_d_109), + .I1(com_cmm_u_cmm_errman_wtd_cor_add_input_six_n_d_110), + .I2(com_cmm_u_cmm_errman_wtd_cor_add_input_three_n_d_105), + .I3(com_cmm_u_cmm_errman_wtd_cor_add_input_two_n_d_106), + .O(m17_1_306) + ); + defparam I_5123_0_a2.INIT = 8'h02; + LUT3 I_5123_0_a2 ( + .I0(N_22826_1_0), + .I1(N_56513_i), + .I2(plm_fsm_cc_counter3_reg_rx_expired_78), + .O(N_22825) + ); + defparam I_5219_i_0_0_0.INIT = 16'h0020; + LUT4 I_5219_i_0_0_0 ( + .I0(N_56043_i), + .I1(N_56124_i), + .I2(plm_fsm_reg_state_13__76), + .I3(plm_fsm_rl_counter3_reg_rx_expired_312), + .O(N_22672_i) + ); + defparam I_5202_i_0_0_0.INIT = 16'h0020; + LUT4 I_5202_i_0_0_0 ( + .I0(N_56030_i), + .I1(N_56125_i), + .I2(plm_fsm_reg_state_13__76), + .I3(plm_fsm_rl_counter2_reg_rx_expired_313), + .O(N_22527_i) + ); + defparam I_5184_i_0_0_0.INIT = 16'h0020; + LUT4 I_5184_i_0_0_0 ( + .I0(N_56029_i), + .I1(N_56126_i), + .I2(plm_fsm_reg_state_13__76), + .I3(plm_fsm_rl_counter1_reg_rx_expired_314), + .O(N_14480_i) + ); + defparam I_5280_i_0_0_0.INIT = 16'h0100; + LUT4 I_5280_i_0_0_0 ( + .I0(N_29556_i), + .I1(N_56030_i), + .I2(plm_fsm_rc_counter_ts1_2_reg_rx_expired_315), + .I3(plm_rx2_ts1_c), + .O(N_15212_i) + ); + defparam I_5260_i_0_0_0.INIT = 16'h0100; + LUT4 I_5260_i_0_0_0 ( + .I0(N_29556_i), + .I1(N_56029_i), + .I2(plm_fsm_rc_counter_ts1_1_reg_rx_expired_316), + .I3(plm_rx1_ts1_c), + .O(N_22977_i) + ); + defparam I_5299_i_0_0.INIT = 16'h0100; + LUT4 I_5299_i_0_0 ( + .I0(N_29556_i), + .I1(N_56043_i), + .I2(plm_fsm_rc_counter_ts1_3_reg_rx_expired_317), + .I3(plm_rx3_ts1_c), + .O(N_28802_i) + ); + defparam I_5240_i_0_0.INIT = 16'h0100; + LUT4 I_5240_i_0_0 ( + .I0(N_29556_i), + .I1(N_56052_i), + .I2(plm_fsm_rc_counter_ts1_0_reg_rx_expired_318), + .I3(plm_rx0_ts1_c), + .O(N_28800_i) + ); + defparam I_5371_0_a2.INIT = 8'h02; + LUT3 I_5371_0_a2 ( + .I0(N_22826_1_0), + .I1(N_29556_i), + .I2(plm_fsm_rc_counter_ts2_3_reg_rx_expired_319), + .O(N_22826) + ); + defparam I_5106_0_a2_i_0_0_o2.INIT = 4'h8; + LUT2 I_5106_0_a2_i_0_0_o2 ( + .I0(N_56030_i), + .I1(plm_rx2_ts2_c), + .O(N_56155_i) + ); + defparam I_5070_i_0_0_0_o2.INIT = 4'h8; + LUT2 I_5070_i_0_0_0_o2 ( + .I0(N_56052_i), + .I1(plm_rx0_ts2_c), + .O(N_56156_i) + ); + defparam m12_0_39395.INIT = 16'h1B0D; + LUT4_L m12_0_39395 ( + .I0(N_56022_i), + .I1(N_56469_i), + .I2(m12_0_o3_0_320), + .I3(com_tlm_cmmt_err_tlp_malformed), + .LO(m12_0_39395_293) + ); + defparam G_372.INIT = 8'h96; + LUT3 G_372 ( + .I0(G_372_1_321), + .I1(N_14), + .I2(N_11847_1), + .O(G_372_322) + ); + defparam G_473.INIT = 8'h96; + LUT3 G_473 ( + .I0(N_64), + .I1(G_7_323), + .I2(d64_i_m3_0_21_), + .O(G_473_324) + ); + defparam G_479.INIT = 16'h6996; + LUT4 G_479 ( + .I0(G_374_0_325), + .I1(N_3), + .I2(N_33), + .I3(G_4_326), + .O(G_479_327) + ); + defparam G_403.INIT = 16'h6996; + LUT4 G_403 ( + .I0(N_39_1), + .I1(N_41), + .I2(N_160_1), + .I3(N_12061_1), + .O(G_403_328) + ); + defparam G_413.INIT = 8'h96; + LUT3 G_413 ( + .I0(N_12), + .I1(N_14), + .I2(N_12071_1), + .O(G_413_329) + ); + defparam G_370.INIT = 16'h6996; + LUT4 G_370 ( + .I0(G_460_1_1_330), + .I1(N_64), + .I2(N_11843_1), + .I3(d64_i_m2_i_m3_0_59_), + .O(G_370_331) + ); + defparam G_485.INIT = 16'h6996; + LUT4 G_485 ( + .I0(N_141_1), + .I1(G_2_332), + .I2(G_4_326), + .I3(d64_i_m3_0_7_), + .O(G_485_333) + ); + defparam G_386.INIT = 16'h6996; + LUT4 G_386 ( + .I0(G_386_0_91), + .I1(N_11978_1), + .I2(N_12047_1), + .I3(d16_i_m3_0_2_), + .O(G_386_334) + ); + defparam G_373.INIT = 16'h6996; + LUT4 G_373 ( + .I0(N_36), + .I1(G_24_335), + .I2(d64_i_m3_0_6_), + .I3(d64_i_m2_i_m3_0_59_), + .O(G_373_336) + ); + defparam G_393.INIT = 16'h9669; + LUT4 G_393 ( + .I0(N_24), + .I1(G_9_337), + .I2(G_14_338), + .I3(c64_0_a2_0_a2_1_), + .O(G_393_339) + ); + defparam G_499.INIT = 16'h6996; + LUT4 G_499 ( + .I0(N_58_1), + .I1(G_3_340), + .I2(N_12175_1), + .I3(d64_i_m3_i_m3_0_60_), + .O(G_499_341) + ); + defparam G_371.INIT = 8'h96; + LUT3 G_371 ( + .I0(G_14_338), + .I1(N_12029_1), + .I2(d64_i_m2_i_m3_0_59_), + .O(G_371_342) + ); + defparam G_378.INIT = 16'h9669; + LUT4 G_378 ( + .I0(N_32), + .I1(G_4_326), + .I2(d64_i_m3_i_m3_0_60_), + .I3(c64_0_a2_0_a2_26_), + .O(G_378_343) + ); + defparam G_404.INIT = 8'h69; + LUT3 G_404 ( + .I0(N_30), + .I1(N_32), + .I2(c64_0_a2_0_a2_26_), + .O(G_404_344) + ); + defparam G_460.INIT = 16'h6996; + LUT4 G_460 ( + .I0(G_460_1_1_330), + .I1(N_91_1), + .I2(N_11843_1), + .I3(N_11848_1), + .O(G_460_345) + ); + defparam G_465.INIT = 4'h6; + LUT2 G_465 ( + .I0(G_5_346), + .I1(N_12123_1), + .O(G_465_347) + ); + defparam m16_i_0_0_4.INIT = 16'h1F00; + LUT4_L m16_i_0_0_4 ( + .I0(N_56103_i), + .I1(N_57268), + .I2(com_lnk_rd[6]), + .I3(m16_i_0_0_2_348), + .LO(m16_i_0_0_4_114) + ); + defparam I_5371_0_a2_1.INIT = 16'h8000; + LUT4 I_5371_0_a2_1 ( + .I0(N_9901), + .I1(N_47431_i), + .I2(N_56042_i_1), + .I3(plm_rx3_ts2_c), + .O(N_22826_1_0) + ); + defparam I_5184_i_0_0_0_o2.INIT = 8'h80; + LUT3 I_5184_i_0_0_0_o2 ( + .I0(I_5184_i_0_0_0_o2_4_349), + .I1(I_5184_i_0_0_0_o2_5_350), + .I2(N_9903), + .O(N_56029_i) + ); + defparam G_2710_0_a2_0_a2_0_a2_0_a2.INIT = 4'h2; + LUT2 G_2710_0_a2_0_a2_0_a2_0_a2 ( + .I0(N_56053_i), + .I1(com_cmm_rst_351), + .O(G_2710_0_a2_0_a2_0_a2_0_a2_352) + ); + defparam I_5166_i_0_0_0_o2.INIT = 4'h8; + LUT2 I_5166_i_0_0_0_o2 ( + .I0(N_9900), + .I1(N_55989_i), + .O(N_56052_i) + ); + defparam I_5219_i_0_0_0_o2.INIT = 8'h80; + LUT3 I_5219_i_0_0_0_o2 ( + .I0(N_9901), + .I1(N_47431_i), + .I2(N_56042_i_1), + .O(N_56043_i) + ); + defparam I_5202_i_0_0_0_o2.INIT = 8'h80; + LUT3 I_5202_i_0_0_0_o2 ( + .I0(I_5202_i_0_0_0_o3_4_353), + .I1(I_5202_i_0_0_0_o3_5_354), + .I2(N_9902), + .O(N_56030_i) + ); + defparam G_459.INIT = 16'h6669; + LUT4 G_459 ( + .I0(N_19), + .I1(c64_0_a2_0_a2_2_), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d64_15__355), + .I3(com_llm_llm_rx_top_llm_rx_tlp_crc_initial_64_97), + .O(G_459_356) + ); + defparam G_380.INIT = 8'h96; + LUT3 G_380 ( + .I0(G_9_337), + .I1(d64_i_m3_0_20_), + .I2(d64_i_m3_i_m3_0_60_), + .O(G_380_357) + ); + defparam G_387.INIT = 8'h96; + LUT3 G_387 ( + .I0(G_298_358), + .I1(N_12045_1), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d64_30__359), + .O(G_387_360) + ); + defparam G_388.INIT = 8'h96; + LUT3 G_388 ( + .I0(G_297_361), + .I1(N_12129_1), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d64_30__359), + .O(G_388_362) + ); + defparam G_487.INIT = 16'h9996; + LUT4 G_487 ( + .I0(G_368_363), + .I1(d64_i_m3_0_15_), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d64_4__364), + .I3(com_llm_llm_rx_top_llm_rx_tlp_crc_initial_64_97), + .O(G_487_365) + ); + defparam G_486.INIT = 16'h9996; + LUT4 G_486 ( + .I0(G_486_2_366), + .I1(d64_i_m2_i_m3_0_36_), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d64_4__364), + .I3(com_llm_llm_rx_top_llm_rx_tlp_crc_initial_64_97), + .O(G_486_367) + ); + defparam G_469_1.INIT = 16'h6996; + LUT4 G_469_1 ( + .I0(G_249_368), + .I1(N_11969_1), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d64_16__92), + .I3(com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d64_29__369), + .O(N_12127_1) + ); + defparam G_401.INIT = 16'h6996; + LUT4 G_401 ( + .I0(G_401_0_370), + .I1(N_12048_1), + .I2(d16_i_m3_0_3_), + .I3(d16_i_m3_i_m3_0_15_), + .O(G_401_371) + ); + defparam G_371_1.INIT = 16'h9669; + LUT4 G_371_1 ( + .I0(N_112_1), + .I1(G_9_337), + .I2(d64_i_m3_0_20_), + .I3(c64_0_a2_0_a2_17_), + .O(N_12029_1) + ); + defparam G_389.INIT = 4'h6; + LUT2 G_389 ( + .I0(N_12047_1), + .I1(d16_i_m3_0_2_), + .O(G_389_372) + ); + defparam G_470_2.INIT = 4'h6; + LUT2 G_470_2 ( + .I0(G_250_80), + .I1(d16_i_m3_0_6_), + .O(N_12128_2) + ); + defparam G_491.INIT = 4'h6; + LUT2 G_491 ( + .I0(G_9_337), + .I1(N_12149_1), + .O(G_491_373) + ); + defparam G_516_i_x4_0_x4.INIT = 8'h69; + LUT3 G_516_i_x4_0_x4 ( + .I0(N_11977_2), + .I1(N_12048_1), + .I2(N_12105_1), + .O(N_31590_i_0) + ); + defparam G_449_0_x4.INIT = 4'h6; + LUT2 G_449_0_x4 ( + .I0(N_3), + .I1(d64_i_m3_0_21_), + .O(N_31587_i_0) + ); + defparam G_484.INIT = 8'h96; + LUT3 G_484 ( + .I0(G_249_368), + .I1(N_12128_1), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d64_29__369), + .O(G_484_374) + ); + defparam m16_i_0_0_2.INIT = 16'h3600; + LUT4_L m16_i_0_0_2 ( + .I0(com_lnk_rd[4]), + .I1(com_lnk_rd[5]), + .I2(com_lnk_rd[6]), + .I3(m16_i_0_0_1_375), + .LO(m16_i_0_0_2_348) + ); + defparam G_522.INIT = 8'h96; + LUT3 G_522 ( + .I0(N_114), + .I1(N_130), + .I2(data_in_q[52]), + .O(G_522_376) + ); + defparam G_392.INIT = 8'h96; + LUT3 G_392 ( + .I0(N_133), + .I1(G_127_377), + .I2(data_in_q[14]), + .O(G_392_378) + ); + defparam G_397.INIT = 16'h6996; + LUT4 G_397 ( + .I0(G_127_377), + .I1(G_149_379), + .I2(data_in_q[11]), + .I3(data_in_q[23]), + .O(G_397_380) + ); + defparam G_425.INIT = 8'h96; + LUT3 G_425 ( + .I0(N_136), + .I1(G_112_381), + .I2(N_12083_1), + .O(G_425_382) + ); + defparam G_453.INIT = 8'h96; + LUT3 G_453 ( + .I0(G_453_2_383), + .I1(N_118), + .I2(G_111_384), + .O(G_453_385) + ); + defparam G_452.INIT = 8'h96; + LUT3 G_452 ( + .I0(G_452_2_386), + .I1(N_180), + .I2(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_29_), + .O(G_452_387) + ); + defparam G_450.INIT = 8'h96; + LUT3 G_450 ( + .I0(G_450_2_388), + .I1(N_176), + .I2(com_llm_llm_rx_top_rx_data_61_), + .O(G_450_389) + ); + defparam G_432.INIT = 16'h6996; + LUT4 G_432 ( + .I0(N_232), + .I1(N_11897), + .I2(com_llm_llm_tx_top_tx_dllp_td_27_), + .I3(com_llm_llm_tx_top_tx_dllp_td_28_), + .O(N_12090) + ); + defparam G_451.INIT = 16'h6996; + LUT4 G_451 ( + .I0(N_12109_1), + .I1(com_llm_llm_tx_top_tx_dllp_td_25_), + .I2(com_llm_llm_tx_top_tx_dllp_td_26_), + .I3(com_llm_llm_tx_top_tx_dllp_td_40_), + .O(N_12109) + ); + defparam m13_0.INIT = 16'h2BBD; + LUT4 m13_0 ( + .I0(com_cmm_u_cmm_errman_wtd_cor_add_input_one_d_109), + .I1(com_cmm_u_cmm_errman_wtd_cor_add_input_six_n_d_110), + .I2(com_cmm_u_cmm_errman_wtd_cor_add_input_three_n_d_105), + .I3(com_cmm_u_cmm_errman_wtd_cor_add_input_two_n_d_106), + .O(m13_0_305) + ); + defparam m7_0.INIT = 16'h2996; + LUT4 m7_0 ( + .I0(com_cmm_u_cmm_errman_wtd_cor_add_input_one_d_109), + .I1(com_cmm_u_cmm_errman_wtd_cor_add_input_six_n_d_110), + .I2(com_cmm_u_cmm_errman_wtd_cor_add_input_three_n_d_105), + .I3(com_cmm_u_cmm_errman_wtd_cor_add_input_two_n_d_106), + .O(m7_0_301) + ); + defparam G_462.INIT = 8'h96; + LUT3 G_462 ( + .I0(G_462_1_1), + .I1(N_220), + .I2(com_llm_llm_tx_top_tx_dllp_td_25_), + .O(N_12120) + ); + defparam G_424.INIT = 16'h6996; + LUT4 G_424 ( + .I0(N_177), + .I1(N_220), + .I2(N_11897), + .I3(com_llm_llm_tx_top_tx_dllp_td_38_), + .O(N_12082) + ); + defparam G_442.INIT = 8'h96; + LUT3 G_442 ( + .I0(N_179), + .I1(N_219), + .I2(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_39_), + .O(G_442_390) + ); + defparam G_372_1.INIT = 16'h6996; + LUT4 G_372_1 ( + .I0(d64_i_m3_0_15_), + .I1(d64_i_m3_0_33_), + .I2(d64_i_m2_i_m3_0_27_), + .I3(d64_i_m2_i_m3_0_59_), + .O(G_372_1_321) + ); + defparam G_374_0.INIT = 8'h69; + LUT3 G_374_0 ( + .I0(d64_i_m3_0_52_), + .I1(d64_i_m3_i_m3_0_60_), + .I2(c64_0_a2_0_a2_26_), + .O(G_374_0_325) + ); + defparam G_486_2.INIT = 16'h9996; + LUT4_L G_486_2 ( + .I0(G_486_1_391), + .I1(d64_i_m3_0_47_), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d64_15__355), + .I3(com_llm_llm_rx_top_llm_rx_tlp_crc_initial_64_97), + .LO(G_486_2_366) + ); + defparam G_460_1_1.INIT = 16'h9996; + LUT4 G_460_1_1 ( + .I0(d64_i_m3_0_12_), + .I1(d64_i_m3_0_0_), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d64_15__355), + .I3(com_llm_llm_rx_top_llm_rx_tlp_crc_initial_64_97), + .O(G_460_1_1_330) + ); + defparam G_429.INIT = 16'h9996; + LUT4 G_429 ( + .I0(d64_i_m3_0_23_), + .I1(d64_i_m2_i_m3_0_26_), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d64_16__92), + .I3(com_llm_llm_rx_top_llm_rx_tlp_crc_initial_64_97), + .O(G_429_392) + ); + defparam G_368.INIT = 8'h96; + LUT3 G_368 ( + .I0(N_12175_1), + .I1(d64_i_m3_i_m3_0_60_), + .I2(d64_i_m2_i_m3_0_59_), + .O(G_368_363) + ); + defparam G_297.INIT = 8'h96; + LUT3 G_297 ( + .I0(N_11961_1), + .I1(d16_i_m3_0_8_), + .I2(d16_i_m3_i_m3_0_14_), + .O(G_297_361) + ); + defparam G_298.INIT = 8'h96; + LUT3 G_298 ( + .I0(N_11969_1), + .I1(d16_i_m3_i_m3_0_14_), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d64_16__92), + .O(G_298_358) + ); + defparam G_249.INIT = 8'h96; + LUT3 G_249 ( + .I0(N_11972_1), + .I1(d16_i_m3_i_m3_0_13_), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d64_22__393), + .O(G_249_368) + ); + defparam G_250.INIT = 16'h6996; + LUT4 G_250 ( + .I0(d16_i_m3_0_2_), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d64_18__394), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d64_22__393), + .I3(com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d64_24__395), + .O(G_250_80) + ); + defparam G_251.INIT = 8'h96; + LUT3 G_251 ( + .I0(G_386_0_91), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d64_16__92), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d64_22__393), + .O(G_251_396) + ); + defparam G_156.INIT = 8'h69; + LUT3 G_156 ( + .I0(N_11870_1), + .I1(d64_i_m3_0_13_), + .I2(c64_0_a2_0_a2_10_), + .O(G_156_397) + ); + defparam G_121.INIT = 8'h96; + LUT3 G_121 ( + .I0(N_160_1), + .I1(d64_i_m3_0_11_), + .I2(d64_i_m3_0_14_), + .O(G_121_398) + ); + defparam G_138.INIT = 8'h96; + LUT3 G_138 ( + .I0(d64_i_m3_0_7_), + .I1(d64_i_m3_0_16_), + .I2(d64_i_m3_0_35_), + .O(N_142) + ); + defparam G_70.INIT = 8'h69; + LUT3 G_70 ( + .I0(N_140_1), + .I1(d64_i_m3_i_m3_0_49_), + .I2(c64_0_a2_0_a2_2_), + .O(G_70_399) + ); + defparam G_71.INIT = 8'h96; + LUT3 G_71 ( + .I0(N_75_1), + .I1(d64_i_m3_0_19_), + .I2(d64_i_m3_i_m3_0_49_), + .O(N_75) + ); + defparam G_73.INIT = 16'h9669; + LUT4 G_73 ( + .I0(d64_i_m3_0_0_), + .I1(d64_i_m3_0_13_), + .I2(d64_i_m3_0_34_), + .I3(c64_0_a2_0_a2_17_), + .O(N_77) + ); + defparam G_74.INIT = 8'h69; + LUT3 G_74 ( + .I0(d64_i_m3_0_21_), + .I1(d64_i_m3_0_15_), + .I2(c64_0_a2_0_a2_17_), + .O(N_78) + ); + defparam G_75.INIT = 8'h96; + LUT3 G_75 ( + .I0(N_11858_1), + .I1(d64_i_m3_0_8_), + .I2(d64_i_m3_i_m3_0_30_), + .O(N_79) + ); + defparam G_85.INIT = 8'h69; + LUT3 G_85 ( + .I0(N_90_1), + .I1(d64_i_m3_0_15_), + .I2(c64_0_a2_0_a2_10_), + .O(N_89) + ); + defparam G_88.INIT = 8'h96; + LUT3 G_88 ( + .I0(N_92_1), + .I1(d64_i_m3_0_0_), + .I2(d64_i_m3_0_19_), + .O(N_92) + ); + defparam G_103.INIT = 8'h96; + LUT3 G_103 ( + .I0(N_107_1), + .I1(d64_i_m3_0_18_), + .I2(d64_i_m3_0_20_), + .O(N_107) + ); + defparam G_108.INIT = 8'h96; + LUT3 G_108 ( + .I0(N_112_1), + .I1(d64_i_m3_0_37_), + .I2(d64_i_m3_i_m3_0_30_), + .O(N_112) + ); + defparam G_28.INIT = 8'h96; + LUT3 G_28 ( + .I0(N_12149_1), + .I1(d64_i_m3_0_29_), + .I2(d64_i_m3_0_58_), + .O(N_32) + ); + defparam G_29.INIT = 8'h96; + LUT3 G_29 ( + .I0(N_51_1), + .I1(d64_i_m3_0_3_), + .I2(d64_i_m3_0_58_), + .O(N_33) + ); + defparam G_33.INIT = 8'h96; + LUT3 G_33 ( + .I0(N_39_1), + .I1(d64_i_m3_0_5_), + .I2(d64_i_m3_0_24_), + .O(N_37) + ); + defparam G_36.INIT = 8'h69; + LUT3 G_36 ( + .I0(G_36_0_400), + .I1(d64_i_m3_0_35_), + .I2(c64_0_a2_0_a2_3_), + .O(N_40) + ); + defparam G_38.INIT = 8'h69; + LUT3 G_38 ( + .I0(N_42_1), + .I1(d64_i_m3_0_29_), + .I2(c64_0_a2_0_a2_17_), + .O(N_42) + ); + defparam G_47.INIT = 8'h96; + LUT3 G_47 ( + .I0(N_51_1), + .I1(d64_i_m3_0_21_), + .I2(d64_i_m3_0_4_), + .O(N_51) + ); + defparam G_49.INIT = 16'h9669; + LUT4 G_49 ( + .I0(d64_i_m3_0_22_), + .I1(d64_i_m3_0_23_), + .I2(d64_i_m3_0_28_), + .I3(c64_0_a2_0_a2_10_), + .O(N_53) + ); + defparam G_51.INIT = 8'h96; + LUT3 G_51 ( + .I0(N_92_1), + .I1(d64_i_m3_0_8_), + .I2(d64_i_m3_0_28_), + .O(N_55) + ); + defparam G_53.INIT = 16'h9669; + LUT4 G_53 ( + .I0(d64_i_m3_0_16_), + .I1(d64_i_m3_0_34_), + .I2(d64_i_m3_0_55_), + .I3(c64_0_a2_0_a2_2_), + .O(N_57) + ); + defparam G_54.INIT = 16'h9996; + LUT4 G_54 ( + .I0(N_58_1), + .I1(d64_i_m3_0_55_), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d64_16__92), + .I3(com_llm_llm_rx_top_llm_rx_tlp_crc_initial_64_97), + .O(N_58) + ); + defparam G_56.INIT = 8'h69; + LUT3 G_56 ( + .I0(N_12033_1), + .I1(d64_i_m3_0_8_), + .I2(c64_0_a2_0_a2_3_), + .O(N_60) + ); + defparam G_57.INIT = 8'h96; + LUT3 G_57 ( + .I0(N_12071_1), + .I1(d64_i_m3_0_21_), + .I2(d64_i_m3_0_5_), + .O(N_61) + ); + defparam G_58.INIT = 16'h9669; + LUT4 G_58 ( + .I0(d64_i_m3_0_5_), + .I1(d64_i_m3_0_13_), + .I2(d64_i_m3_0_18_), + .I3(c64_0_a2_0_a2_17_), + .O(N_62) + ); + defparam G_5.INIT = 16'hAA96; + LUT4 G_5 ( + .I0(N_11843_1), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d64_15__355), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d64_28__401), + .I3(com_llm_llm_rx_top_llm_rx_tlp_crc_initial_64_97), + .O(G_5_346) + ); + defparam G_9.INIT = 8'h69; + LUT3 G_9 ( + .I0(N_35_1), + .I1(d64_i_m3_i_m3_0_49_), + .I2(c64_0_a2_0_a2_27_), + .O(G_9_337) + ); + defparam G_12.INIT = 8'h69; + LUT3 G_12 ( + .I0(N_107_1), + .I1(d64_i_m3_0_3_), + .I2(c64_0_a2_0_a2_1_), + .O(N_14) + ); + defparam G_13.INIT = 8'h69; + LUT3 G_13 ( + .I0(N_91_1), + .I1(d64_i_m3_0_23_), + .I2(c64_0_a2_0_a2_1_), + .O(N_15) + ); + defparam G_20.INIT = 8'h96; + LUT3 G_20 ( + .I0(N_35_1), + .I1(d64_i_m3_0_9_), + .I2(d64_i_m3_i_m3_0_31_), + .O(N_23) + ); + defparam G_26.INIT = 8'h69; + LUT3 G_26 ( + .I0(N_11848_1), + .I1(d64_i_m3_0_55_), + .I2(c64_0_a2_0_a2_23_), + .O(N_30) + ); + defparam G_4.INIT = 16'h6669; + LUT4 G_4 ( + .I0(N_11847_1), + .I1(c64_0_a2_0_a2_23_), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d64_28__401), + .I3(com_llm_llm_rx_top_llm_rx_tlp_crc_initial_64_97), + .O(G_4_326) + ); + defparam G_32.INIT = 8'h96; + LUT3 G_32 ( + .I0(N_87_1), + .I1(d64_i_m3_0_7_), + .I2(d64_i_m3_0_24_), + .O(N_36) + ); + defparam G_19.INIT = 8'h96; + LUT3 G_19 ( + .I0(N_58_1), + .I1(d64_i_m3_0_19_), + .I2(d64_i_m3_i_m3_0_31_), + .O(N_22) + ); + defparam G_48.INIT = 8'h96; + LUT3 G_48 ( + .I0(N_12116_1), + .I1(d64_i_m3_i_m3_0_48_), + .I2(d64_i_m2_i_m3_0_27_), + .O(N_52) + ); + defparam G_60.INIT = 8'h96; + LUT3 G_60 ( + .I0(N_11870_1), + .I1(d64_i_m3_0_2_), + .I2(d64_i_m3_i_m3_0_30_), + .O(N_64) + ); + defparam G_6.INIT = 16'h9996; + LUT4 G_6 ( + .I0(N_140_1), + .I1(d64_i_m3_0_10_), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d64_28__401), + .I3(com_llm_llm_rx_top_llm_rx_tlp_crc_initial_64_97), + .O(G_6_402) + ); + defparam G_55.INIT = 8'h96; + LUT3 G_55 ( + .I0(N_12033_1), + .I1(d64_i_m3_0_2_), + .I2(d64_i_m3_0_18_), + .O(N_59) + ); + defparam G_3.INIT = 16'h9996; + LUT4 G_3 ( + .I0(N_11845_1), + .I1(d64_i_m2_i_m3_0_36_), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d64_20__403), + .I3(com_llm_llm_rx_top_llm_rx_tlp_crc_initial_64_97), + .O(G_3_340) + ); + defparam G_2.INIT = 16'h9996; + LUT4 G_2 ( + .I0(N_10_1), + .I1(d64_i_m3_0_8_), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d64_20__403), + .I3(com_llm_llm_rx_top_llm_rx_tlp_crc_initial_64_97), + .O(G_2_332) + ); + defparam G_122.INIT = 8'h96; + LUT3 G_122 ( + .I0(N_12116_1), + .I1(d64_i_m3_0_11_), + .I2(d64_i_m3_0_23_), + .O(G_122_404) + ); + defparam G_61.INIT = 16'h9996; + LUT4 G_61 ( + .I0(N_65_1), + .I1(d64_i_m3_0_16_), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d64_7__405), + .I3(com_llm_llm_rx_top_llm_rx_tlp_crc_initial_64_97), + .O(N_65) + ); + defparam G_389_1.INIT = 16'h6996; + LUT4 G_389_1 ( + .I0(N_11961_1), + .I1(d16_i_m3_i_m3_0_14_), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d64_18__394), + .I3(com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d64_30__359), + .O(N_12047_1) + ); + defparam G_145.INIT = 16'h6996; + LUT4 G_145 ( + .I0(d64_i_m3_0_4_), + .I1(d64_i_m3_0_20_), + .I2(d64_i_m3_0_25_), + .I3(d64_i_m2_i_m3_0_26_), + .O(G_145_406) + ); + defparam G_11.INIT = 8'h96; + LUT3 G_11 ( + .I0(G_11_1_407), + .I1(c64_0_a2_0_a2_27_), + .I2(c64_0_a2_0_a2_1_), + .O(G_11_408) + ); + defparam G_10.INIT = 16'h6996; + LUT4 G_10 ( + .I0(d64_i_m3_0_14_), + .I1(d64_i_m3_0_58_), + .I2(c64_0_a2_0_a2_27_), + .I3(c64_0_a2_0_a2_26_), + .O(N_12) + ); + defparam G_62.INIT = 16'h6996; + LUT4 G_62 ( + .I0(d64_i_m3_0_7_), + .I1(d64_i_m3_0_2_), + .I2(d64_i_m3_0_14_), + .I3(d64_i_m3_0_19_), + .O(N_66) + ); + defparam G_83.INIT = 4'h6; + LUT2 G_83 ( + .I0(N_87_1), + .I1(N_11870_1), + .O(N_87) + ); + defparam G_21.INIT = 8'h96; + LUT3 G_21 ( + .I0(N_87_1), + .I1(d64_i_m3_0_9_), + .I2(d64_i_m2_i_m3_0_27_), + .O(N_24) + ); + defparam G_1.INIT = 4'h6; + LUT2 G_1 ( + .I0(N_3_1), + .I1(N_39_1), + .O(N_3) + ); + defparam G_7.INIT = 4'h6; + LUT2 G_7 ( + .I0(N_10_1), + .I1(N_51_1), + .O(G_7_323) + ); + defparam G_14.INIT = 4'h6; + LUT2 G_14 ( + .I0(N_11842_1), + .I1(N_11848_1), + .O(G_14_338) + ); + defparam G_15.INIT = 8'h69; + LUT3 G_15 ( + .I0(N_11842_1), + .I1(d64_i_m3_0_22_), + .I2(c64_0_a2_0_a2_10_), + .O(G_15_409) + ); + defparam G_24.INIT = 4'h6; + LUT2 G_24 ( + .I0(N_11847_1), + .I1(N_11858_1), + .O(G_24_335) + ); + defparam G_37.INIT = 8'h96; + LUT3 G_37 ( + .I0(N_92_1), + .I1(d64_i_m3_0_25_), + .I2(d64_i_m3_0_29_), + .O(N_41) + ); + defparam G_46.INIT = 4'h6; + LUT2 G_46 ( + .I0(N_51_1), + .I1(N_12071_1), + .O(N_50) + ); + defparam G_59.INIT = 8'h96; + LUT3 G_59 ( + .I0(N_87_1), + .I1(d64_i_m3_0_1_), + .I2(d64_i_m3_0_5_), + .O(N_63) + ); + defparam G_87.INIT = 16'h9996; + LUT4 G_87 ( + .I0(N_91_1), + .I1(d64_i_m2_i_m3_0_36_), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d64_4__364), + .I3(com_llm_llm_rx_top_llm_rx_tlp_crc_initial_64_97), + .O(N_91) + ); + defparam G_299.INIT = 8'h96; + LUT3 G_299 ( + .I0(N_12128_1), + .I1(d16_i_m3_0_2_), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d64_18__394), + .O(G_299_410) + ); + defparam G_301.INIT = 8'h96; + LUT3 G_301 ( + .I0(d16_i_m3_0_2_), + .I1(d16_i_m3_0_8_), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d64_24__395), + .O(G_301_411) + ); + defparam G_303.INIT = 4'h6; + LUT2 G_303 ( + .I0(N_11961_1), + .I1(N_12048_1), + .O(G_303_412) + ); + defparam G_305.INIT = 4'h6; + LUT2 G_305 ( + .I0(N_11963_1), + .I1(N_11969_1), + .O(G_305_413) + ); + defparam G_308.INIT = 8'h96; + LUT3 G_308 ( + .I0(N_12129_1), + .I1(d16_i_m3_0_8_), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d64_24__395), + .O(G_308_414) + ); + defparam G_313.INIT = 4'h6; + LUT2 G_313 ( + .I0(N_11972_1), + .I1(N_12129_1), + .O(G_313_415) + ); + defparam G_314.INIT = 4'h6; + LUT2 G_314 ( + .I0(G_386_0_91), + .I1(N_11972_1), + .O(G_314_416) + ); + defparam G_375.INIT = 8'h96; + LUT3 G_375 ( + .I0(N_12033_1), + .I1(d64_i_m3_0_52_), + .I2(d64_i_m3_i_m3_0_60_), + .O(G_375_417) + ); + defparam G_390.INIT = 4'h6; + LUT2 G_390 ( + .I0(N_12048_1), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d64_30__359), + .O(G_390_418) + ); + defparam G_447.INIT = 4'h6; + LUT2 G_447 ( + .I0(N_12105_1), + .I1(d16_i_m3_i_m3_0_0_), + .O(com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d16_new_c16_1_1_1[11]) + ); + defparam G_471.INIT = 4'h6; + LUT2 G_471 ( + .I0(N_12129_1), + .I1(d16_i_m3_0_6_), + .O(G_471_419) + ); + defparam m16_i_0_0_1.INIT = 16'h0037; + LUT4_L m16_i_0_0_1 ( + .I0(com_lnk_rd[2]), + .I1(com_lnk_rd[3]), + .I2(com_lnk_rd[5]), + .I3(com_lnk_rd[7]), + .LO(m16_i_0_0_1_375) + ); + defparam m5_2_0_0_0_39292.INIT = 8'hBC; + LUT3_L m5_2_0_0_0_39292 ( + .I0(com_lnk_rd[0]), + .I1(com_lnk_rd[1]), + .I2(com_lnk_rd[3]), + .LO(m5_2_0_0_0_39292_111) + ); + defparam G_513.INIT = 8'h96; + LUT3 G_513 ( + .I0(N_197), + .I1(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_30_), + .I2(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_35_), + .O(G_513_420) + ); + defparam G_407.INIT = 8'h96; + LUT3 G_407 ( + .I0(N_114), + .I1(data_in_q[19]), + .I2(data_in_q[20]), + .O(G_407_421) + ); + defparam G_427.INIT = 8'h96; + LUT3 G_427 ( + .I0(N_130), + .I1(data_in_q[19]), + .I2(data_in_q[49]), + .O(G_427_422) + ); + defparam G_510.INIT = 8'h96; + LUT3 G_510 ( + .I0(N_198), + .I1(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_3_), + .I2(com_llm_llm_rx_top_rx_data_62_), + .O(G_510_423) + ); + defparam I_5027_i_0_0_0.INIT = 8'h08; + LUT3 I_5027_i_0_0_0 ( + .I0(N_22668_i_1), + .I1(N_59114_2), + .I2(plm_fsm_pa_counter3_reg_rx_expired_82), + .O(N_22668_i) + ); + defparam I_5005_i_0_0_0.INIT = 8'h08; + LUT3 I_5005_i_0_0_0 ( + .I0(N_14474_1_i), + .I1(N_14474_i_1), + .I2(plm_fsm_pa_counter1_reg_rx_expired_84), + .O(N_14474_i) + ); + defparam I_4994_i_0_0_0.INIT = 16'h0400; + LUT4 I_4994_i_0_0_0 ( + .I0(N_56123_i), + .I1(N_56496_i), + .I2(plm_fsm_pa_counter0_reg_rx_expired_424), + .I3(plm_fsm_reg_state_1__425), + .O(N_15205_i) + ); + defparam I_5016_i_0_0_0.INIT = 8'h20; + LUT3 I_5016_i_0_0_0 ( + .I0(N_59117_1), + .I1(plm_fsm_pa_counter2_reg_rx_expired_86), + .I2(plm_rx2_link_pad), + .O(N_22524_i) + ); + defparam G_512.INIT = 8'h96; + LUT3 G_512 ( + .I0(N_196), + .I1(com_llm_llm_tx_top_tx_dllp_td_30_), + .I2(com_llm_llm_tx_top_tx_dllp_td_35_), + .O(N_12170) + ); + defparam G_523.INIT = 16'h6996; + LUT4 G_523 ( + .I0(N_184), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crc32_d64_feedback[8]), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crc32_d64_feedback[29]), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crc32_d64_feedback[31]), + .O(N_12181) + ); + defparam G_418.INIT = 8'h96; + LUT3 G_418 ( + .I0(N_67), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[2]), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[3]), + .O(N_12076) + ); + defparam m12_0_o3_0.INIT = 8'h2B; + LUT3 m12_0_o3_0 ( + .I0(com_cmml_protocol_err_n), + .I1(com_tlm_cmmt_err_flow_control), + .I2(com_tlm_cmmt_err_rbuf_overflow), + .O(m12_0_o3_0_320) + ); + defparam m4_3_0_0_0_0_a2_0.INIT = 16'h2000; + LUT4 m4_3_0_0_0_0_a2_0 ( + .I0(N_58537), + .I1(com_cmm_pme_ack_bar), + .I2(com_cmm_u_cmm_dataproducer_req_gnt_code[0]), + .I3(com_cmm_u_cmm_dataproducer_req_gnt_code[1]), + .O(m4_3_0_0_0_0_a2_0_294) + ); + defparam G_349.INIT = 4'h6; + LUT2 G_349 ( + .I0(N_12007_1_0), + .I1(plm_scr2_reg_lfsr_two_15__426), + .O(G_349_427) + ); + defparam G_514.INIT = 16'h6996; + LUT4 G_514 ( + .I0(N_129), + .I1(N_11867_1), + .I2(data_in_q[36]), + .I3(data_in_q[52]), + .O(G_514_428) + ); + defparam G_457.INIT = 16'h6996; + LUT4 G_457 ( + .I0(G_457_1_429), + .I1(N_199_1), + .I2(data_in_q[4]), + .I3(data_in_q[22]), + .O(G_457_430) + ); + defparam G_440.INIT = 16'h6996; + LUT4 G_440 ( + .I0(G_202_431), + .I1(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_36_), + .I2(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_49_), + .I3(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_50_), + .O(G_440_432) + ); + defparam G_439.INIT = 16'h6996; + LUT4 G_439 ( + .I0(G_203_433), + .I1(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_4_), + .I2(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_17_), + .I3(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_18_), + .O(G_439_434) + ); + defparam G_524.INIT = 16'h6996; + LUT4 G_524 ( + .I0(N_204), + .I1(N_217_1), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crc32_d64_feedback[3]), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crc32_d64_feedback[10]), + .O(N_12182) + ); + defparam m3_0.INIT = 16'h9669; + LUT4 m3_0 ( + .I0(com_cmm_u_cmm_errman_wtd_cor_add_input_one_d_109), + .I1(com_cmm_u_cmm_errman_wtd_cor_add_input_six_n_d_110), + .I2(com_cmm_u_cmm_errman_wtd_cor_add_input_three_n_d_105), + .I3(com_cmm_u_cmm_errman_wtd_cor_add_input_two_n_d_106), + .O(m3_0_302) + ); + defparam G_445.INIT = 4'h6; + LUT2 G_445 ( + .I0(N_215), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crc32_d64_feedback[10]), + .O(N_12103) + ); + defparam G_463.INIT = 4'h6; + LUT2 G_463 ( + .I0(N_67), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[12]), + .O(N_12121) + ); + defparam G_466.INIT = 4'h6; + LUT2 G_466 ( + .I0(N_181), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crc32_d64_feedback[7]), + .O(N_12124) + ); + defparam G_507.INIT = 4'h6; + LUT2 G_507 ( + .I0(N_177), + .I1(com_llm_llm_tx_top_tx_dllp_td_24_), + .O(N_12165) + ); + defparam G_451_1.INIT = 16'h6996; + LUT4 G_451_1 ( + .I0(com_llm_llm_tx_top_tx_dllp_td_29_), + .I1(com_llm_llm_tx_top_tx_dllp_td_34_), + .I2(com_llm_llm_tx_top_tx_dllp_td_52_), + .I3(com_llm_llm_tx_top_tx_dllp_td_55_), + .O(N_12109_1) + ); + defparam G_399_0_x4.INIT = 4'h6; + LUT2 G_399_0_x4 ( + .I0(G_237_435), + .I1(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_55_), + .O(N_31577_i_0) + ); + defparam G_396_1.INIT = 4'h6; + LUT2 G_396_1 ( + .I0(N_117), + .I1(data_in_q[15]), + .O(N_12054_1) + ); + defparam G_426_1.INIT = 4'h6; + LUT2 G_426_1 ( + .I0(N_129), + .I1(data_in_q[45]), + .O(N_12084_1) + ); + defparam G_443_1.INIT = 4'h6; + LUT2 G_443_1 ( + .I0(N_175), + .I1(N_218), + .O(N_12101_1) + ); + defparam G_454.INIT = 8'h96; + LUT3 G_454 ( + .I0(N_118), + .I1(data_in_q[7]), + .I2(data_in_q[10]), + .O(G_454_436) + ); + defparam G_461.INIT = 8'h96; + LUT3 G_461 ( + .I0(G_165_437), + .I1(data_in_q[0]), + .I2(data_in_q[12]), + .O(G_461_438) + ); + defparam G_400_0_x4.INIT = 4'h6; + LUT2 G_400_0_x4 ( + .I0(G_241_439), + .I1(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_23_), + .O(N_31578_i_0) + ); + defparam G_468.INIT = 4'h6; + LUT2 G_468 ( + .I0(N_117), + .I1(G_150_440), + .O(G_468_441) + ); + defparam G_467.INIT = 4'h6; + LUT2 G_467 ( + .I0(N_132), + .I1(N_189), + .O(G_467_442) + ); + defparam G_394.INIT = 4'h6; + LUT2 G_394 ( + .I0(N_146), + .I1(data_in_q[38]), + .O(G_394_443) + ); + defparam G_391_0.INIT = 4'h6; + LUT2 G_391_0 ( + .I0(d64_i_m3_0_17_), + .I1(d64_i_m3_0_22_), + .O(G_391_0_444) + ); + defparam G_486_1.INIT = 4'h6; + LUT2_L G_486_1 ( + .I0(d64_i_m3_0_1_), + .I1(d64_i_m3_0_14_), + .LO(G_486_1_391) + ); + defparam G_36_0.INIT = 4'h6; + LUT2_L G_36_0 ( + .I0(d64_i_m3_0_29_), + .I1(d64_i_m2_i_m3_0_26_), + .LO(G_36_0_400) + ); + defparam G_50_0.INIT = 4'h6; + LUT2 G_50_0 ( + .I0(d64_i_m3_0_10_), + .I1(d64_i_m3_0_28_), + .O(G_50_0_445) + ); + defparam G_84_0.INIT = 4'h6; + LUT2 G_84_0 ( + .I0(d64_i_m3_0_1_), + .I1(d64_i_m3_0_42_), + .O(G_84_0_446) + ); + defparam G_11_1.INIT = 4'h6; + LUT2_L G_11_1 ( + .I0(d64_i_m3_0_11_), + .I1(d64_i_m3_0_33_), + .LO(G_11_1_407) + ); + defparam G_499_0.INIT = 8'h56; + LUT3 G_499_0 ( + .I0(d64_i_m3_0_39_), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d64_7__405), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_initial_64_97), + .O(N_58_1) + ); + defparam G_386_0.INIT = 16'h5A66; + LUT4 G_386_0 ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d64_26__447), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_13__448), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_45__449), + .I3(com_llm_llm_rx_top_llm_rx_tlp_crc_start_high_latch_q_450), + .O(G_386_0_91) + ); + defparam G_409_0_m3_0.INIT = 16'hC355; + LUT4 G_409_0_m3_0 ( + .I0(N_31580_i), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_data_q[2]), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_21__451), + .I3(com_llm_llm_rx_top_llm_rx_tlp_crc_start_high_latch_452), + .O(G_409_0_m3_0_453) + ); + defparam m16_i_0_0_m3_0.INIT = 16'hFCAA; + LUT4 m16_i_0_0_m3_0 ( + .I0(N_56031_i), + .I1(com_lnk_rd[2]), + .I2(com_lnk_rd[3]), + .I3(com_lnk_rd[6]), + .O(N_56980) + ); + defparam m16_i_0_0_m3_0_0.INIT = 8'h6E; + LUT3 m16_i_0_0_m3_0_0 ( + .I0(com_lnk_rd[0]), + .I1(com_lnk_rd[1]), + .I2(com_lnk_rd[3]), + .O(N_56983) + ); + defparam G_47_1.INIT = 8'h56; + LUT3 G_47_1 ( + .I0(N_31638), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d64_19__94), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_initial_64_97), + .O(N_51_1) + ); + defparam G_8_1.INIT = 8'h56; + LUT3 G_8_1 ( + .I0(N_31643), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d64_24__395), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_initial_64_97), + .O(N_10_1) + ); + defparam G_303_1.INIT = 16'h5A66; + LUT4 G_303_1 ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d64_23__454), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_0__455), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_32__456), + .I3(com_llm_llm_rx_top_llm_rx_tlp_crc_start_high_latch_q_450), + .O(N_11961_1) + ); + defparam G_103_1.INIT = 8'h56; + LUT3 G_103_1 ( + .I0(N_31629), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d64_8__457), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_initial_64_97), + .O(N_107_1) + ); + defparam G_22_1.INIT = 8'h56; + LUT3 G_22_1 ( + .I0(d64_i_m3_0_9_), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d64_4__364), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_initial_64_97), + .O(N_11845_1) + ); + defparam G_1_1.INIT = 8'h56; + LUT3 G_1_1 ( + .I0(d64_i_m3_i_m3_0_31_), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d64_20__403), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_initial_64_97), + .O(N_3_1) + ); + defparam G_413_1.INIT = 8'h56; + LUT3 G_413_1 ( + .I0(N_31794), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d64_0__458), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_initial_64_97), + .O(N_12071_1) + ); + defparam G_83_1.INIT = 8'h56; + LUT3 G_83_1 ( + .I0(N_31640), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d64_21__459), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_initial_64_97), + .O(N_87_1) + ); + defparam G_480_0_x4_0_x4.INIT = 16'h5A66; + LUT4 G_480_0_x4_0_x4 ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d64_27__460), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_12__461), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_44__462), + .I3(com_llm_llm_rx_top_llm_rx_tlp_crc_start_high_latch_q_450), + .O(N_12048_1) + ); + defparam G_61_1.INIT = 4'h6; + LUT2 G_61_1 ( + .I0(d64_i_m3_0_0_), + .I1(d64_i_m3_0_2_), + .O(N_65_1) + ); + defparam G_156_1.INIT = 8'h56; + LUT3 G_156_1 ( + .I0(N_31762), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d64_31__463), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_initial_64_97), + .O(N_11870_1) + ); + defparam G_15_1.INIT = 8'h56; + LUT3 G_15_1 ( + .I0(d64_i_m3_i_m3_0_62_), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d64_30__359), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_initial_64_97), + .O(N_11842_1) + ); + defparam G_16_1.INIT = 4'h6; + LUT2 G_16_1 ( + .I0(d64_i_m3_0_24_), + .I1(d64_i_m3_0_47_), + .O(N_11843_1) + ); + defparam G_17_1.INIT = 4'h6; + LUT2 G_17_1 ( + .I0(d64_i_m3_0_42_), + .I1(d64_i_m3_0_55_), + .O(N_19_1) + ); + defparam G_25_1.INIT = 8'h56; + LUT3 G_25_1 ( + .I0(d64_i_m3_0_50_), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d64_18__394), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_initial_64_97), + .O(N_11847_1) + ); + defparam G_27_1.INIT = 8'h56; + LUT3 G_27_1 ( + .I0(d64_i_m3_0_44_), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d64_12__464), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_initial_64_97), + .O(N_11848_1) + ); + defparam G_31_1.INIT = 8'h56; + LUT3 G_31_1 ( + .I0(d64_i_m3_0_54_), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d64_22__393), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_initial_64_97), + .O(N_35_1) + ); + defparam G_35_1.INIT = 8'h56; + LUT3 G_35_1 ( + .I0(d64_i_m3_0_57_), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d64_25__465), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_initial_64_97), + .O(N_39_1) + ); + defparam G_38_1.INIT = 4'h6; + LUT2 G_38_1 ( + .I0(d64_i_m3_0_5_), + .I1(d64_i_m3_0_28_), + .O(N_42_1) + ); + defparam G_71_1.INIT = 4'h9; + LUT2 G_71_1 ( + .I0(d64_i_m3_0_11_), + .I1(c64_0_a2_0_a2_17_), + .O(N_75_1) + ); + defparam G_86_1.INIT = 4'h6; + LUT2 G_86_1 ( + .I0(d64_i_m3_0_1_), + .I1(d64_i_m3_0_17_), + .O(N_90_1) + ); + defparam G_87_1.INIT = 8'h56; + LUT3 G_87_1 ( + .I0(d64_i_m3_i_m3_0_48_), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d64_16__92), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_initial_64_97), + .O(N_91_1) + ); + defparam G_88_1.INIT = 8'h56; + LUT3 G_88_1 ( + .I0(d64_i_m3_0_41_), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d64_9__466), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_initial_64_97), + .O(N_92_1) + ); + defparam G_108_1.INIT = 4'h6; + LUT2 G_108_1 ( + .I0(d64_i_m3_0_6_), + .I1(d64_i_m2_i_m3_0_26_), + .O(N_112_1) + ); + defparam G_109_1.INIT = 4'h6; + LUT2 G_109_1 ( + .I0(d64_i_m3_0_3_), + .I1(d64_i_m3_0_4_), + .O(N_113_1) + ); + defparam G_120_1.INIT = 8'h56; + LUT3 G_120_1 ( + .I0(d64_i_m3_0_46_), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d64_14__467), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_initial_64_97), + .O(N_11858_1) + ); + defparam G_124_1.INIT = 4'h6; + LUT2 G_124_1 ( + .I0(d64_i_m3_0_12_), + .I1(d64_i_m3_0_35_), + .O(N_11862_1) + ); + defparam G_137_1.INIT = 4'h6; + LUT2 G_137_1 ( + .I0(d64_i_m3_0_20_), + .I1(d64_i_m3_i_m3_0_30_), + .O(N_141_1) + ); + defparam G_155_1.INIT = 8'h56; + LUT3 G_155_1 ( + .I0(d64_i_m3_0_45_), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d64_13__468), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_initial_64_97), + .O(N_160_1) + ); + defparam G_305_1.INIT = 4'h6; + LUT2 G_305_1 ( + .I0(d16_i_m3_i_m3_0_13_), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d64_29__369), + .O(N_11963_1) + ); + defparam G_311_1.INIT = 16'h5A66; + LUT4 G_311_1 ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d64_25__465), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_14__469), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_46__470), + .I3(com_llm_llm_rx_top_llm_rx_tlp_crc_start_high_latch_q_450), + .O(N_11969_1) + ); + defparam G_314_1.INIT = 16'h5A66; + LUT4 G_314_1 ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d64_17__471), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_6__472), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_38__473), + .I3(com_llm_llm_rx_top_llm_rx_tlp_crc_start_high_latch_q_450), + .O(N_11972_1) + ); + defparam G_319_2.INIT = 4'h6; + LUT2 G_319_2 ( + .I0(d16_i_m3_i_m3_0_0_), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d64_16__92), + .O(N_11977_2) + ); + defparam G_320_1.INIT = 4'h6; + LUT2 G_320_1 ( + .I0(d16_i_m3_i_m3_0_15_), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d64_31__463), + .O(N_11978_1) + ); + defparam G_375_1.INIT = 8'h56; + LUT3 G_375_1 ( + .I0(d64_i_m3_0_38_), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d64_6__474), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_initial_64_97), + .O(N_12033_1) + ); + defparam G_387_1.INIT = 4'h6; + LUT2 G_387_1 ( + .I0(d16_i_m3_0_3_), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d64_19__94), + .O(N_12045_1) + ); + defparam G_458_1.INIT = 8'h56; + LUT3 G_458_1 ( + .I0(d64_i_m3_0_43_), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d64_11__475), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_initial_64_97), + .O(N_12116_1) + ); + defparam G_469_2.INIT = 4'h6; + LUT2 G_469_2 ( + .I0(d16_i_m3_0_6_), + .I1(d16_i_m3_i_m3_0_0_), + .O(N_12127_2) + ); + defparam G_470_1.INIT = 16'h5A66; + LUT4 G_470_1 ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d64_21__459), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_2__476), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_34__477), + .I3(com_llm_llm_rx_top_llm_rx_tlp_crc_start_high_latch_q_450), + .O(N_12128_1) + ); + defparam G_471_1.INIT = 16'h5A66; + LUT4 G_471_1 ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d64_20__403), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_3__478), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_35__479), + .I3(com_llm_llm_rx_top_llm_rx_tlp_crc_start_high_latch_q_450), + .O(N_12129_1) + ); + defparam G_491_1.INIT = 8'h56; + LUT3 G_491_1 ( + .I0(d64_i_m3_i_m3_0_61_), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d64_29__369), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_initial_64_97), + .O(N_12149_1) + ); + defparam G_517_1.INIT = 4'h6; + LUT2 G_517_1 ( + .I0(d64_i_m3_0_33_), + .I1(d64_i_m3_0_52_), + .O(N_12175_1) + ); + defparam I_5184_i_0_0_0_o2_5.INIT = 16'h0001; + LUT4 I_5184_i_0_0_0_o2_5 ( + .I0(plm_rx1_lane_num[1]), + .I1(plm_rx1_lane_num[2]), + .I2(plm_rx1_lane_num[3]), + .I3(plm_rx1_lane_num[7]), + .O(I_5184_i_0_0_0_o2_5_350) + ); + defparam I_5184_i_0_0_0_o2_4.INIT = 16'h0002; + LUT4 I_5184_i_0_0_0_o2_4 ( + .I0(plm_rx1_lane_num[0]), + .I1(plm_rx1_lane_num[4]), + .I2(plm_rx1_lane_num[5]), + .I3(plm_rx1_lane_num[6]), + .O(I_5184_i_0_0_0_o2_4_349) + ); + defparam G_450_2.INIT = 16'h6996; + LUT4 G_450_2 ( + .I0(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_8_), + .I1(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_15_), + .I2(com_llm_llm_rx_top_rx_data_57_), + .I3(com_llm_llm_rx_top_rx_data_58_), + .O(G_450_2_388) + ); + defparam G_452_2.INIT = 16'h6996; + LUT4 G_452_2 ( + .I0(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_25_), + .I1(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_26_), + .I2(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_40_), + .I3(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_47_), + .O(G_452_2_386) + ); + defparam G_453_2.INIT = 16'h6996; + LUT4 G_453_2 ( + .I0(data_in_q[6]), + .I1(data_in_q[46]), + .I2(data_in_q[54]), + .I3(data_in_q[59]), + .O(G_453_2_383) + ); + defparam I_5202_i_0_0_0_o3_5.INIT = 16'h0002; + LUT4 I_5202_i_0_0_0_o3_5 ( + .I0(plm_rx2_lane_num[1]), + .I1(plm_rx2_lane_num[4]), + .I2(plm_rx2_lane_num[5]), + .I3(plm_rx2_lane_num[7]), + .O(I_5202_i_0_0_0_o3_5_354) + ); + defparam I_5202_i_0_0_0_o3_4.INIT = 16'h0001; + LUT4 I_5202_i_0_0_0_o3_4 ( + .I0(plm_rx2_lane_num[0]), + .I1(plm_rx2_lane_num[2]), + .I2(plm_rx2_lane_num[3]), + .I3(plm_rx2_lane_num[6]), + .O(I_5202_i_0_0_0_o3_4_353) + ); + defparam m12_0_a2_0.INIT = 8'h02; + LUT3 m12_0_a2_0 ( + .I0(com_cmml_protocol_err_n), + .I1(com_tlm_cmmt_err_flow_control), + .I2(com_tlm_cmmt_err_rbuf_overflow), + .O(N_57661) + ); + defparam G_482.INIT = 8'h96; + LUT3 G_482 ( + .I0(data_in_q[12]), + .I1(data_in_q[25]), + .I2(data_in_q[30]), + .O(G_482_480) + ); + defparam G_475.INIT = 8'h96; + LUT3 G_475 ( + .I0(data_in_q[10]), + .I1(data_in_q[32]), + .I2(data_in_q[43]), + .O(G_475_481) + ); + defparam G_349_1_0.INIT = 8'h96; + LUT3 G_349_1_0 ( + .I0(plm_scr2_reg_lfsr_two_0__482), + .I1(plm_scr2_reg_lfsr_two_11__483), + .I2(plm_scr2_reg_lfsr_two_13__484), + .O(N_12007_1_0) + ); + defparam G_351.INIT = 16'h6996; + LUT4 G_351 ( + .I0(plm_des2_reg_lfsr_two_0__485), + .I1(plm_des2_reg_lfsr_two_11__486), + .I2(plm_des2_reg_lfsr_two_13__487), + .I3(plm_des2_reg_lfsr_two_15__488), + .O(G_351_489) + ); + defparam G_353.INIT = 16'h6996; + LUT4 G_353 ( + .I0(plm_scr0_reg_lfsr_two_0__490), + .I1(plm_scr0_reg_lfsr_two_11__491), + .I2(plm_scr0_reg_lfsr_two_13__492), + .I3(plm_scr0_reg_lfsr_two_15__493), + .O(G_353_494) + ); + defparam G_329.INIT = 8'h96; + LUT3 G_329 ( + .I0(N_12074_1), + .I1(plm_scr3_reg_lfsr_one_1__495), + .I2(plm_scr3_reg_lfsr_one_15__496), + .O(G_329_497) + ); + defparam G_330.INIT = 8'h96; + LUT3 G_330 ( + .I0(plm_scr3_reg_lfsr_one_3__498), + .I1(plm_scr3_reg_lfsr_one_13__499), + .I2(plm_scr3_reg_lfsr_one_15__496), + .O(G_330_500) + ); + defparam G_331.INIT = 8'h96; + LUT3 G_331 ( + .I0(N_12078_1), + .I1(plm_des1_reg_lfsr_one_1__501), + .I2(plm_des1_reg_lfsr_one_15__502), + .O(G_331_503) + ); + defparam G_332.INIT = 8'h96; + LUT3 G_332 ( + .I0(plm_des1_reg_lfsr_one_3__504), + .I1(plm_des1_reg_lfsr_one_13__505), + .I2(plm_des1_reg_lfsr_one_15__502), + .O(G_332_506) + ); + defparam G_333.INIT = 8'h96; + LUT3 G_333 ( + .I0(N_12075_1), + .I1(plm_scr1_reg_lfsr_one_1__507), + .I2(plm_scr1_reg_lfsr_one_15__508), + .O(G_333_509) + ); + defparam G_334.INIT = 8'h96; + LUT3 G_334 ( + .I0(plm_scr1_reg_lfsr_one_3__510), + .I1(plm_scr1_reg_lfsr_one_13__511), + .I2(plm_scr1_reg_lfsr_one_15__508), + .O(G_334_512) + ); + defparam G_335.INIT = 8'h96; + LUT3 G_335 ( + .I0(N_12072_1), + .I1(plm_des3_reg_lfsr_one_1__513), + .I2(plm_des3_reg_lfsr_one_15__514), + .O(G_335_515) + ); + defparam G_336.INIT = 8'h96; + LUT3 G_336 ( + .I0(plm_des3_reg_lfsr_one_3__516), + .I1(plm_des3_reg_lfsr_one_13__517), + .I2(plm_des3_reg_lfsr_one_15__514), + .O(G_336_518) + ); + defparam G_337.INIT = 8'h96; + LUT3 G_337 ( + .I0(N_12079_1), + .I1(plm_des2_reg_lfsr_one_1__519), + .I2(plm_des2_reg_lfsr_one_15__520), + .O(G_337_521) + ); + defparam G_338.INIT = 8'h96; + LUT3 G_338 ( + .I0(plm_des2_reg_lfsr_one_3__522), + .I1(plm_des2_reg_lfsr_one_13__523), + .I2(plm_des2_reg_lfsr_one_15__520), + .O(G_338_524) + ); + defparam G_339.INIT = 16'h6996; + LUT4 G_339 ( + .I0(plm_des3_reg_lfsr_two_0__525), + .I1(plm_des3_reg_lfsr_two_11__526), + .I2(plm_des3_reg_lfsr_two_13__527), + .I3(plm_des3_reg_lfsr_two_15__528), + .O(G_339_529) + ); + defparam G_341.INIT = 16'h6996; + LUT4 G_341 ( + .I0(plm_des0_reg_lfsr_two_0__530), + .I1(plm_des0_reg_lfsr_two_11__531), + .I2(plm_des0_reg_lfsr_two_13__532), + .I3(plm_des0_reg_lfsr_two_15__533), + .O(G_341_534) + ); + defparam G_343.INIT = 8'h96; + LUT3 G_343 ( + .I0(N_12001_1), + .I1(plm_scr1_reg_lfsr_two_13__535), + .I2(plm_scr1_reg_lfsr_two_15__536), + .O(G_343_537) + ); + defparam G_345.INIT = 16'h6996; + LUT4 G_345 ( + .I0(plm_scr3_reg_lfsr_two_0__538), + .I1(plm_scr3_reg_lfsr_two_11__539), + .I2(plm_scr3_reg_lfsr_two_13__540), + .I3(plm_scr3_reg_lfsr_two_15__541), + .O(G_345_542) + ); + defparam G_347.INIT = 16'h6996; + LUT4 G_347 ( + .I0(plm_des1_reg_lfsr_two_0__543), + .I1(plm_des1_reg_lfsr_two_11__544), + .I2(plm_des1_reg_lfsr_two_13__545), + .I3(plm_des1_reg_lfsr_two_15__546), + .O(G_347_547) + ); + defparam G_279.INIT = 16'h6996; + LUT4 G_279 ( + .I0(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_1_), + .I1(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_9_), + .I2(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_16_), + .I3(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_17_), + .O(G_279_548) + ); + defparam G_280.INIT = 16'h6996; + LUT4 G_280 ( + .I0(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_33_), + .I1(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_41_), + .I2(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_48_), + .I3(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_49_), + .O(G_280_549) + ); + defparam G_285.INIT = 8'h96; + LUT3 G_285 ( + .I0(data_in_q[24]), + .I1(data_in_q[48]), + .I2(data_in_q[49]), + .O(G_285_550) + ); + defparam G_286.INIT = 8'h96; + LUT3 G_286 ( + .I0(data_in_q[5]), + .I1(data_in_q[32]), + .I2(data_in_q[35]), + .O(G_286_551) + ); + defparam G_288.INIT = 16'h6996; + LUT4 G_288 ( + .I0(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_25_), + .I1(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_33_), + .I2(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_35_), + .I3(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_50_), + .O(G_288_552) + ); + defparam G_290.INIT = 16'h6996; + LUT4 G_290 ( + .I0(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_1_), + .I1(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_3_), + .I2(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_18_), + .I3(com_llm_llm_rx_top_rx_data_57_), + .O(G_290_553) + ); + defparam G_295.INIT = 8'h96; + LUT3 G_295 ( + .I0(data_in_q[15]), + .I1(data_in_q[37]), + .I2(data_in_q[46]), + .O(G_295_554) + ); + defparam G_323.INIT = 8'h96; + LUT3 G_323 ( + .I0(N_12081_1), + .I1(plm_scr2_reg_lfsr_one_1__555), + .I2(plm_scr2_reg_lfsr_one_15__556), + .O(G_323_557) + ); + defparam G_324.INIT = 8'h96; + LUT3 G_324 ( + .I0(plm_scr2_reg_lfsr_one_3__558), + .I1(plm_scr2_reg_lfsr_one_13__559), + .I2(plm_scr2_reg_lfsr_one_15__556), + .O(G_324_560) + ); + defparam G_325.INIT = 16'h6996; + LUT4 G_325 ( + .I0(plm_des0_reg_lfsr_one_0__561), + .I1(plm_des0_reg_lfsr_one_1__562), + .I2(plm_des0_reg_lfsr_one_11__563), + .I3(plm_des0_reg_lfsr_one_15__564), + .O(G_325_565) + ); + defparam G_326.INIT = 8'h96; + LUT3 G_326 ( + .I0(plm_des0_reg_lfsr_one_3__566), + .I1(plm_des0_reg_lfsr_one_13__567), + .I2(plm_des0_reg_lfsr_one_15__564), + .O(G_326_568) + ); + defparam G_327.INIT = 8'h96; + LUT3 G_327 ( + .I0(N_12080_1), + .I1(plm_scr0_reg_lfsr_one_1__569), + .I2(plm_scr0_reg_lfsr_one_15__570), + .O(G_327_571) + ); + defparam G_328.INIT = 8'h96; + LUT3 G_328 ( + .I0(plm_scr0_reg_lfsr_one_3__572), + .I1(plm_scr0_reg_lfsr_one_13__573), + .I2(plm_scr0_reg_lfsr_one_15__570), + .O(G_328_574) + ); + defparam G_236.INIT = 8'h96; + LUT3 G_236 ( + .I0(N_11894_1), + .I1(data_in_q[22]), + .I2(data_in_q[49]), + .O(G_236_575) + ); + defparam G_237.INIT = 16'h6996; + LUT4 G_237 ( + .I0(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_24_), + .I1(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_34_), + .I2(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_36_), + .I3(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_40_), + .O(G_237_435) + ); + defparam G_241.INIT = 8'h96; + LUT3 G_241 ( + .I0(N_11899_1), + .I1(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_2_), + .I2(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_8_), + .O(G_241_439) + ); + defparam G_255.INIT = 16'h6996; + LUT4 G_255 ( + .I0(data_in_q[0]), + .I1(data_in_q[4]), + .I2(data_in_q[12]), + .I3(data_in_q[41]), + .O(G_255_576) + ); + defparam G_256.INIT = 16'h6996; + LUT4 G_256 ( + .I0(data_in_q[14]), + .I1(data_in_q[38]), + .I2(data_in_q[41]), + .I3(data_in_q[45]), + .O(G_256_577) + ); + defparam G_259.INIT = 16'h6996; + LUT4 G_259 ( + .I0(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_26_), + .I1(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_33_), + .I2(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_38_), + .I3(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_53_), + .O(G_259_578) + ); + defparam G_260.INIT = 16'h6996; + LUT4 G_260 ( + .I0(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_1_), + .I1(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_6_), + .I2(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_21_), + .I3(com_llm_llm_rx_top_rx_data_58_), + .O(G_260_579) + ); + defparam G_274.INIT = 8'h96; + LUT3 G_274 ( + .I0(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_30_), + .I1(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_32_), + .I2(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_48_), + .O(G_274_580) + ); + defparam G_202.INIT = 16'h6996; + LUT4 G_202 ( + .I0(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_42_), + .I1(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_44_), + .I2(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_45_), + .I3(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_53_), + .O(G_202_431) + ); + defparam G_203.INIT = 16'h6996; + LUT4 G_203 ( + .I0(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_10_), + .I1(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_12_), + .I2(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_13_), + .I3(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_21_), + .O(G_203_433) + ); + defparam G_204.INIT = 8'h96; + LUT3 G_204 ( + .I0(N_11881_1), + .I1(data_in_q[27]), + .I2(data_in_q[39]), + .O(G_204_581) + ); + defparam G_205.INIT = 16'h6996; + LUT4 G_205 ( + .I0(data_in_q[9]), + .I1(data_in_q[25]), + .I2(data_in_q[36]), + .I3(data_in_q[48]), + .O(G_205_582) + ); + defparam G_206.INIT = 8'h96; + LUT3 G_206 ( + .I0(N_212_1), + .I1(data_in_q[9]), + .I2(data_in_q[53]), + .O(N_212) + ); + defparam G_207.INIT = 8'h96; + LUT3 G_207 ( + .I0(data_in_q[1]), + .I1(data_in_q[9]), + .I2(data_in_q[17]), + .O(G_207_583) + ); + defparam G_224.INIT = 16'h6996; + LUT4 G_224 ( + .I0(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_6_), + .I1(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_14_), + .I2(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_18_), + .I3(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_22_), + .O(N_230) + ); + defparam G_225.INIT = 16'h6996; + LUT4 G_225 ( + .I0(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_1_), + .I1(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_3_), + .I2(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_7_), + .I3(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_22_), + .O(N_231) + ); + defparam G_227.INIT = 16'h6996; + LUT4 G_227 ( + .I0(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_33_), + .I1(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_35_), + .I2(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_39_), + .I3(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_54_), + .O(G_227_584) + ); + defparam G_228.INIT = 8'h96; + LUT3 G_228 ( + .I0(N_11888_1), + .I1(data_in_q[5]), + .I2(data_in_q[47]), + .O(G_228_585) + ); + defparam G_233.INIT = 8'h96; + LUT3 G_233 ( + .I0(N_11891_1), + .I1(data_in_q[27]), + .I2(data_in_q[40]), + .O(G_233_586) + ); + defparam G_168.INIT = 8'h96; + LUT3 G_168 ( + .I0(N_202_1), + .I1(data_in_q[2]), + .I2(data_in_q[43]), + .O(N_173) + ); + defparam G_169.INIT = 8'h96; + LUT3 G_169 ( + .I0(N_174_1), + .I1(data_in_q[40]), + .I2(data_in_q[63]), + .O(N_174) + ); + defparam G_185.INIT = 16'h6996; + LUT4 G_185 ( + .I0(data_in_q[7]), + .I1(data_in_q[10]), + .I2(data_in_q[19]), + .I3(data_in_q[31]), + .O(N_190) + ); + defparam G_195.INIT = 8'h96; + LUT3 G_195 ( + .I0(N_11945_1), + .I1(data_in_q[9]), + .I2(data_in_q[29]), + .O(N_200) + ); + defparam G_196.INIT = 8'h96; + LUT3 G_196 ( + .I0(N_202_1), + .I1(data_in_q[1]), + .I2(data_in_q[42]), + .O(N_202) + ); + defparam G_149.INIT = 8'h96; + LUT3 G_149 ( + .I0(N_11867_1), + .I1(data_in_q[24]), + .I2(data_in_q[39]), + .O(G_149_379) + ); + defparam G_150.INIT = 16'h6996; + LUT4 G_150 ( + .I0(data_in_q[6]), + .I1(data_in_q[13]), + .I2(data_in_q[57]), + .I3(data_in_q[58]), + .O(G_150_440) + ); + defparam G_151.INIT = 16'h6996; + LUT4 G_151 ( + .I0(data_in_q[6]), + .I1(data_in_q[28]), + .I2(data_in_q[53]), + .I3(data_in_q[58]), + .O(G_151_587) + ); + defparam G_157.INIT = 16'h6996; + LUT4 G_157 ( + .I0(data_in_q[10]), + .I1(data_in_q[22]), + .I2(data_in_q[42]), + .I3(data_in_q[62]), + .O(N_162) + ); + defparam G_158.INIT = 8'h96; + LUT3 G_158 ( + .I0(N_212_1), + .I1(data_in_q[43]), + .I2(data_in_q[62]), + .O(N_163) + ); + defparam G_159.INIT = 8'h96; + LUT3 G_159 ( + .I0(N_11871_1), + .I1(data_in_q[29]), + .I2(data_in_q[62]), + .O(G_159_588) + ); + defparam G_160.INIT = 8'h96; + LUT3 G_160 ( + .I0(N_165_1), + .I1(data_in_q[3]), + .I2(data_in_q[8]), + .O(N_165) + ); + defparam G_161.INIT = 8'h96; + LUT3 G_161 ( + .I0(N_11872_1), + .I1(data_in_q[0]), + .I2(data_in_q[39]), + .O(G_161_589) + ); + defparam G_165.INIT = 8'h96; + LUT3 G_165 ( + .I0(N_11876_1), + .I1(data_in_q[19]), + .I2(data_in_q[57]), + .O(G_165_437) + ); + defparam G_166.INIT = 16'h6996; + LUT4 G_166 ( + .I0(data_in_q[1]), + .I1(data_in_q[43]), + .I2(data_in_q[54]), + .I3(data_in_q[57]), + .O(G_166_590) + ); + defparam G_127.INIT = 16'h6996; + LUT4 G_127 ( + .I0(data_in_q[1]), + .I1(data_in_q[32]), + .I2(data_in_q[43]), + .I3(data_in_q[55]), + .O(G_127_377) + ); + defparam G_129.INIT = 16'h6996; + LUT4 G_129 ( + .I0(data_in_q[16]), + .I1(data_in_q[18]), + .I2(data_in_q[48]), + .I3(data_in_q[60]), + .O(N_133) + ); + defparam G_131.INIT = 16'h6996; + LUT4 G_131 ( + .I0(data_in_q[2]), + .I1(data_in_q[18]), + .I2(data_in_q[52]), + .I3(data_in_q[60]), + .O(N_135) + ); + defparam G_132.INIT = 16'h6996; + LUT4 G_132 ( + .I0(data_in_q[7]), + .I1(data_in_q[51]), + .I2(data_in_q[52]), + .I3(data_in_q[53]), + .O(N_136) + ); + defparam G_142.INIT = 16'h6996; + LUT4 G_142 ( + .I0(data_in_q[4]), + .I1(data_in_q[12]), + .I2(data_in_q[33]), + .I3(data_in_q[51]), + .O(N_146) + ); + defparam G_144.INIT = 16'h6996; + LUT4 G_144 ( + .I0(data_in_q[7]), + .I1(data_in_q[8]), + .I2(data_in_q[40]), + .I3(data_in_q[51]), + .O(N_148) + ); + defparam G_114.INIT = 16'h6996; + LUT4 G_114 ( + .I0(data_in_q[21]), + .I1(data_in_q[50]), + .I2(data_in_q[61]), + .I3(data_in_q[63]), + .O(N_118) + ); + defparam G_245.INIT = 8'h96; + LUT3 G_245 ( + .I0(N_11903_1), + .I1(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_47_), + .I2(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_55_), + .O(G_245_591) + ); + defparam G_222.INIT = 16'h6996; + LUT4 G_222 ( + .I0(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_38_), + .I1(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_46_), + .I2(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_50_), + .I3(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_54_), + .O(G_222_592) + ); + defparam G_317.INIT = 8'h96; + LUT3 G_317 ( + .I0(N_11975_1), + .I1(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_7_), + .I2(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_17_), + .O(G_317_593) + ); + defparam G_273.INIT = 8'h96; + LUT3 G_273 ( + .I0(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_0_), + .I1(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_16_), + .I2(com_llm_llm_rx_top_rx_data_62_), + .O(G_273_594) + ); + defparam G_316.INIT = 8'h96; + LUT3 G_316 ( + .I0(N_31583_i_0), + .I1(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_39_), + .I2(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_49_), + .O(G_316_595) + ); + defparam G_264.INIT = 8'h96; + LUT3 G_264 ( + .I0(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_9_), + .I1(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_21_), + .I2(com_llm_llm_rx_top_rx_data_59_), + .O(G_264_596) + ); + defparam G_262.INIT = 8'h96; + LUT3 G_262 ( + .I0(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_27_), + .I1(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_41_), + .I2(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_53_), + .O(G_262_597) + ); + defparam I_5219_i_0_0_0_o3_1.INIT = 16'h0008; + LUT4 I_5219_i_0_0_0_o3_1 ( + .I0(plm_rx3_lane_num[0]), + .I1(plm_rx3_lane_num[1]), + .I2(plm_rx3_lane_num[2]), + .I3(plm_rx3_lane_num[7]), + .O(N_56042_i_1) + ); + defparam I_5045_0_a2_0_a2_0_a3_0_a2.INIT = 8'h40; + LUT3 I_5045_0_a2_0_a2_0_a3_0_a2 ( + .I0(plm_fsm_pc_counter2_reg_rx_expired_598), + .I1(plm_fsm_reg_state_2__599), + .I2(plm_rx2_ts2_c), + .O(I_5045_0_a2_0_a2_0_a3_0_a2_34) + ); + defparam I_5033_0_a2_0_a2_0_a3_0_a2.INIT = 8'h40; + LUT3 I_5033_0_a2_0_a2_0_a3_0_a2 ( + .I0(plm_fsm_pc_counter0_reg_rx_expired_600), + .I1(plm_fsm_reg_state_2__599), + .I2(plm_rx0_ts2_c), + .O(I_5033_0_a2_0_a2_0_a3_0_a2_30) + ); + defparam I_5039_0_a2_0_a2_0_a3_0_a2.INIT = 8'h40; + LUT3 I_5039_0_a2_0_a2_0_a3_0_a2 ( + .I0(plm_fsm_pc_counter1_reg_rx_expired_601), + .I1(plm_fsm_reg_state_2__599), + .I2(plm_rx1_ts2_c), + .O(I_5039_0_a2_0_a2_0_a3_0_a2_32) + ); + defparam I_5051_0_a2_0_a3_0_a2.INIT = 8'h40; + LUT3 I_5051_0_a2_0_a3_0_a2 ( + .I0(plm_fsm_pc_counter3_reg_rx_expired_602), + .I1(plm_fsm_reg_state_2__599), + .I2(plm_rx3_ts2_c), + .O(I_5051_0_a2_0_a3_0_a2_36) + ); + defparam I_5395_0_a2_0_a2_0_a3_0_a2.INIT = 8'h20; + LUT3 I_5395_0_a2_0_a2_0_a3_0_a2 ( + .I0(plm_fsm_reg_state_16__603), + .I1(plm_fsm_ri_counter3_reg_rx_expired_604), + .I2(plm_rx3_idl_c), + .O(I_5395_0_a2_0_a2_0_a3_0_a2_52) + ); + defparam I_5389_0_a2_0_a2_0_a3_0_a2.INIT = 8'h20; + LUT3 I_5389_0_a2_0_a2_0_a3_0_a2 ( + .I0(plm_fsm_reg_state_16__603), + .I1(plm_fsm_ri_counter2_reg_rx_expired_605), + .I2(plm_rx2_idl_c), + .O(I_5389_0_a2_0_a2_0_a3_0_a2_50) + ); + defparam I_5383_0_a2_0_a2_0_a3_0_a2.INIT = 8'h20; + LUT3 I_5383_0_a2_0_a2_0_a3_0_a2 ( + .I0(plm_fsm_reg_state_16__603), + .I1(plm_fsm_ri_counter1_reg_rx_expired_606), + .I2(plm_rx1_idl_c), + .O(I_5383_0_a2_0_a2_0_a3_0_a2_48) + ); + defparam I_5147_0_a2_0_a2_0_a3_0_a2.INIT = 8'h40; + LUT3 I_5147_0_a2_0_a2_0_a3_0_a2 ( + .I0(plm_fsm_ci_counter3_reg_rx_expired_607), + .I1(plm_fsm_reg_state_11__608), + .I2(plm_rx3_idl_c), + .O(I_5147_0_a2_0_a2_0_a3_0_a2_44) + ); + defparam I_5141_0_a2_0_a2_0_a3_0_a2.INIT = 8'h40; + LUT3 I_5141_0_a2_0_a2_0_a3_0_a2 ( + .I0(plm_fsm_ci_counter2_reg_rx_expired_609), + .I1(plm_fsm_reg_state_11__608), + .I2(plm_rx2_idl_c), + .O(I_5141_0_a2_0_a2_0_a3_0_a2_42) + ); + defparam I_5135_0_a2_0_a2_0_a3_0_a2.INIT = 8'h40; + LUT3 I_5135_0_a2_0_a2_0_a3_0_a2 ( + .I0(plm_fsm_ci_counter1_reg_rx_expired_610), + .I1(plm_fsm_reg_state_11__608), + .I2(plm_rx1_idl_c), + .O(I_5135_0_a2_0_a2_0_a3_0_a2_40) + ); + defparam I_5377_0_a2_0_a2_0_a3_0_a2.INIT = 8'h20; + LUT3 I_5377_0_a2_0_a2_0_a3_0_a2 ( + .I0(plm_fsm_reg_state_16__603), + .I1(plm_fsm_ri_counter0_reg_rx_expired_611), + .I2(plm_rx0_idl_c), + .O(I_5377_0_a2_0_a2_0_a3_0_a2_46) + ); + defparam I_5129_0_a2_0_a2_0_a3_0_a2.INIT = 8'h40; + LUT3 I_5129_0_a2_0_a2_0_a3_0_a2 ( + .I0(plm_fsm_ci_counter0_reg_rx_expired_612), + .I1(plm_fsm_reg_state_11__608), + .I2(plm_rx0_idl_c), + .O(I_5129_0_a2_0_a2_0_a3_0_a2_38) + ); + defparam I_5371_0_a2_1_0_a2_0_o3.INIT = 16'h0001; + LUT4 I_5371_0_a2_1_0_a2_0_o3 ( + .I0(plm_rx3_lane_num[3]), + .I1(plm_rx3_lane_num[4]), + .I2(plm_rx3_lane_num[5]), + .I3(plm_rx3_lane_num[6]), + .O(N_47431_i) + ); + defparam G_258.INIT = 8'h96; + LUT3 G_258 ( + .I0(N_11916_1), + .I1(com_llm_llm_tx_top_tx_dllp_td_33_), + .I2(com_llm_llm_tx_top_tx_dllp_td_38_), + .O(N_11916) + ); + defparam G_248.INIT = 8'h96; + LUT3 G_248 ( + .I0(com_llm_llm_tx_top_tx_dllp_td_32_), + .I1(com_llm_llm_tx_top_tx_dllp_td_41_), + .I2(com_llm_llm_tx_top_tx_dllp_td_55_), + .O(N_11906) + ); + defparam G_239.INIT = 8'h96; + LUT3 G_239 ( + .I0(com_llm_llm_tx_top_tx_dllp_td_24_), + .I1(com_llm_llm_tx_top_tx_dllp_td_34_), + .I2(com_llm_llm_tx_top_tx_dllp_td_40_), + .O(N_11897) + ); + defparam G_226.INIT = 16'h6996; + LUT4 G_226 ( + .I0(com_llm_llm_tx_top_tx_dllp_td_33_), + .I1(com_llm_llm_tx_top_tx_dllp_td_35_), + .I2(com_llm_llm_tx_top_tx_dllp_td_39_), + .I3(com_llm_llm_tx_top_tx_dllp_td_54_), + .O(N_232) + ); + defparam G_214.INIT = 8'h96; + LUT3 G_214 ( + .I0(com_llm_llm_tx_top_tx_dllp_td_32_), + .I1(com_llm_llm_tx_top_tx_dllp_td_43_), + .I2(com_llm_llm_tx_top_tx_dllp_td_45_), + .O(N_220) + ); + defparam G_191.INIT = 8'h96; + LUT3 G_191 ( + .I0(com_llm_llm_tx_top_tx_dllp_td_40_), + .I1(com_llm_llm_tx_top_tx_dllp_td_43_), + .I2(com_llm_llm_tx_top_tx_dllp_td_48_), + .O(N_196) + ); + defparam G_172.INIT = 8'h96; + LUT3 G_172 ( + .I0(com_llm_llm_tx_top_tx_dllp_td_44_), + .I1(com_llm_llm_tx_top_tx_dllp_td_52_), + .I2(com_llm_llm_tx_top_tx_dllp_td_54_), + .O(N_177) + ); + defparam G_278.INIT = 8'h96; + LUT3 G_278 ( + .I0(N_11936_1), + .I1(com_llm_llm_tx_top_tx_dllp_td_33_), + .I2(com_llm_llm_tx_top_tx_dllp_td_49_), + .O(N_11936) + ); + defparam G_275.INIT = 8'h96; + LUT3 G_275 ( + .I0(com_llm_llm_tx_top_tx_dllp_td_30_), + .I1(com_llm_llm_tx_top_tx_dllp_td_32_), + .I2(com_llm_llm_tx_top_tx_dllp_td_48_), + .O(N_11933) + ); + defparam G_67.INIT = 16'h6996; + LUT4 G_67 ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[18]), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[21]), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[30]), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[31]), + .O(N_71) + ); + defparam G_66.INIT = 16'h6996; + LUT4 G_66 ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[3]), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[10]), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[13]), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[31]), + .O(N_70) + ); + defparam G_65.INIT = 16'h6996; + LUT4 G_65 ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[6]), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[9]), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[22]), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[31]), + .O(N_69) + ); + defparam G_63.INIT = 16'h6996; + LUT4 G_63 ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[9]), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[15]), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[28]), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[31]), + .O(N_67) + ); + defparam G_45.INIT = 8'h96; + LUT3 G_45 ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[23]), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[26]), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[30]), + .O(N_49) + ); + defparam G_44.INIT = 16'h6996; + LUT4 G_44 ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[4]), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[8]), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[10]), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[23]), + .O(N_48) + ); + defparam G_43.INIT = 16'h6996; + LUT4 G_43 ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[0]), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[10]), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[20]), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[23]), + .O(N_47) + ); + defparam G_41.INIT = 16'h6996; + LUT4 G_41 ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[17]), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[22]), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[23]), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[29]), + .O(N_45) + ); + defparam G_40.INIT = 16'h6996; + LUT4 G_40 ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[19]), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[23]), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[24]), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[31]), + .O(N_44) + ); + defparam G_135.INIT = 16'h6996; + LUT4 G_135 ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[6]), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[14]), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[28]), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[30]), + .O(N_11864) + ); + defparam G_115.INIT = 16'h6996; + LUT4 G_115 ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[6]), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[13]), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[18]), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[26]), + .O(N_119) + ); + defparam G_99.INIT = 16'h6996; + LUT4 G_99 ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[7]), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[16]), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[26]), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[27]), + .O(N_103) + ); + defparam G_94.INIT = 16'h6996; + LUT4 G_94 ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[8]), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[10]), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[11]), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[24]), + .O(N_98) + ); + defparam G_93.INIT = 16'h6996; + LUT4 G_93 ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[4]), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[13]), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[24]), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[25]), + .O(N_97) + ); + defparam G_92.INIT = 8'h96; + LUT3 G_92 ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[16]), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[22]), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[26]), + .O(N_96) + ); + defparam G_90.INIT = 16'h6996; + LUT4 G_90 ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[6]), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[7]), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[12]), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[22]), + .O(N_94) + ); + defparam G_81.INIT = 16'h6996; + LUT4 G_81 ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[17]), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[20]), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[21]), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[27]), + .O(N_85) + ); + defparam G_79.INIT = 16'h6996; + LUT4 G_79 ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[0]), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[8]), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[11]), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[17]), + .O(N_83) + ); + defparam G_77.INIT = 8'h96; + LUT3 G_77 ( + .I0(N_81_1), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[17]), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[26]), + .O(N_81) + ); + defparam G_68.INIT = 8'h96; + LUT3 G_68 ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[2]), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[26]), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[31]), + .O(N_72) + ); + defparam G_215.INIT = 8'h96; + LUT3 G_215 ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crc32_d64_feedback[2]), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crc32_d64_feedback[18]), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crc32_d64_feedback[21]), + .O(N_221) + ); + defparam G_210.INIT = 8'h96; + LUT3 G_210 ( + .I0(N_11934_1), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crc32_d64_feedback[23]), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crc32_d64_feedback[29]), + .O(N_11885) + ); + defparam G_209.INIT = 8'h96; + LUT3 G_209 ( + .I0(N_217_1), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crc32_d64_feedback[16]), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crc32_d64_feedback[28]), + .O(N_215) + ); + defparam G_208.INIT = 8'h96; + LUT3 G_208 ( + .I0(N_11884_1), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crc32_d64_feedback[20]), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crc32_d64_feedback[27]), + .O(N_11884) + ); + defparam G_199.INIT = 8'h96; + LUT3 G_199 ( + .I0(N_11877_1), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crc32_d64_feedback[13]), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crc32_d64_feedback[20]), + .O(N_11877) + ); + defparam G_198.INIT = 8'h96; + LUT3 G_198 ( + .I0(N_11877_1), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crc32_d64_feedback[4]), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crc32_d64_feedback[7]), + .O(N_204) + ); + defparam G_182.INIT = 16'h6996; + LUT4 G_182 ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crc32_d64_feedback[19]), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crc32_d64_feedback[21]), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crc32_d64_feedback[24]), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crc32_d64_feedback[31]), + .O(N_187) + ); + defparam G_181.INIT = 8'h96; + LUT3 G_181 ( + .I0(N_186_1), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crc32_d64_feedback[9]), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crc32_d64_feedback[23]), + .O(N_186) + ); + defparam G_180.INIT = 16'h6996; + LUT4 G_180 ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crc32_d64_feedback[3]), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crc32_d64_feedback[19]), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crc32_d64_feedback[20]), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crc32_d64_feedback[21]), + .O(N_185) + ); + defparam G_179.INIT = 8'h96; + LUT3 G_179 ( + .I0(N_186_1), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crc32_d64_feedback[11]), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crc32_d64_feedback[25]), + .O(N_184) + ); + defparam G_178.INIT = 16'h6996; + LUT4 G_178 ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crc32_d64_feedback[8]), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crc32_d64_feedback[17]), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crc32_d64_feedback[24]), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crc32_d64_feedback[29]), + .O(N_183) + ); + defparam G_177.INIT = 16'h6996; + LUT4 G_177 ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crc32_d64_feedback[15]), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crc32_d64_feedback[17]), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crc32_d64_feedback[18]), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crc32_d64_feedback[27]), + .O(N_182) + ); + defparam G_162.INIT = 8'h96; + LUT3 G_162 ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[5]), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[14]), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[27]), + .O(N_167) + ); + defparam G_428.INIT = 8'h96; + LUT3 G_428 ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crc32_d64_feedback[0]), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crc32_d64_feedback[11]), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crc32_d64_feedback[13]), + .O(N_12086) + ); + defparam G_312.INIT = 8'h96; + LUT3 G_312 ( + .I0(N_11970_1), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crc32_d64_feedback[5]), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crc32_d64_feedback[15]), + .O(N_11970) + ); + defparam G_283.INIT = 8'h96; + LUT3 G_283 ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crc32_d64_feedback[1]), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crc32_d64_feedback[9]), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crc32_d64_feedback[14]), + .O(N_11941) + ); + defparam G_276.INIT = 8'h96; + LUT3 G_276 ( + .I0(N_11934_1), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crc32_d64_feedback[21]), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crc32_d64_feedback[22]), + .O(N_11934) + ); + defparam G_270.INIT = 8'h96; + LUT3 G_270 ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crc32_d64_feedback[5]), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crc32_d64_feedback[28]), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crc32_d64_feedback[31]), + .O(N_11928) + ); + defparam G_267.INIT = 8'h96; + LUT3 G_267 ( + .I0(N_11927_1), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crc32_d64_feedback[12]), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crc32_d64_feedback[26]), + .O(N_11925) + ); + defparam G_266.INIT = 8'h96; + LUT3 G_266 ( + .I0(N_11924_1), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crc32_d64_feedback[28]), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crc32_d64_feedback[30]), + .O(N_11924) + ); + defparam G_265.INIT = 16'h6996; + LUT4 G_265 ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crc32_d64_feedback[1]), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crc32_d64_feedback[5]), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crc32_d64_feedback[26]), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crc32_d64_feedback[30]), + .O(N_11923) + ); + defparam G_261.INIT = 8'h96; + LUT3 G_261 ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crc32_d64_feedback[6]), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crc32_d64_feedback[8]), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crc32_d64_feedback[22]), + .O(N_11919) + ); + defparam G_216.INIT = 8'h96; + LUT3 G_216 ( + .I0(N_11924_1), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crc32_d64_feedback[9]), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crc32_d64_feedback[29]), + .O(N_222) + ); + defparam G_253.INIT = 16'h6996; + LUT4 G_253 ( + .I0(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_35_), + .I1(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_42_), + .I2(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_50_), + .I3(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_53_), + .O(G_253_613) + ); + defparam G_252.INIT = 16'h6996; + LUT4 G_252 ( + .I0(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_3_), + .I1(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_10_), + .I2(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_18_), + .I3(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_21_), + .O(G_252_614) + ); + defparam G_234.INIT = 16'h6996; + LUT4 G_234 ( + .I0(data_in_q[32]), + .I1(data_in_q[37]), + .I2(data_in_q[40]), + .I3(data_in_q[45]), + .O(G_234_615) + ); + defparam G_213.INIT = 16'h6996; + LUT4 G_213 ( + .I0(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_32_), + .I1(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_43_), + .I2(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_45_), + .I3(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_46_), + .O(N_219) + ); + defparam G_212.INIT = 16'h6996; + LUT4 G_212 ( + .I0(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_0_), + .I1(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_11_), + .I2(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_13_), + .I3(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_14_), + .O(N_218) + ); + defparam G_193.INIT = 16'h6996; + LUT4 G_193 ( + .I0(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_8_), + .I1(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_11_), + .I2(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_16_), + .I3(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_19_), + .O(N_198) + ); + defparam G_192.INIT = 16'h6996; + LUT4 G_192 ( + .I0(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_40_), + .I1(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_43_), + .I2(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_48_), + .I3(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_51_), + .O(N_197) + ); + defparam G_189.INIT = 16'h6996; + LUT4 G_189 ( + .I0(data_in_q[7]), + .I1(data_in_q[27]), + .I2(data_in_q[44]), + .I3(data_in_q[63]), + .O(N_194) + ); + defparam G_188.INIT = 16'h6996; + LUT4 G_188 ( + .I0(data_in_q[5]), + .I1(data_in_q[7]), + .I2(data_in_q[21]), + .I3(data_in_q[45]), + .O(N_193) + ); + defparam G_186.INIT = 16'h6996; + LUT4 G_186 ( + .I0(data_in_q[16]), + .I1(data_in_q[35]), + .I2(data_in_q[38]), + .I3(data_in_q[59]), + .O(N_191) + ); + defparam G_184.INIT = 16'h6996; + LUT4 G_184 ( + .I0(data_in_q[8]), + .I1(data_in_q[11]), + .I2(data_in_q[31]), + .I3(data_in_q[46]), + .O(N_189) + ); + defparam G_175.INIT = 16'h6996; + LUT4 G_175 ( + .I0(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_34_), + .I1(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_37_), + .I2(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_52_), + .I3(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_55_), + .O(N_180) + ); + defparam G_174.INIT = 16'h6996; + LUT4 G_174 ( + .I0(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_44_), + .I1(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_51_), + .I2(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_52_), + .I3(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_54_), + .O(N_179) + ); + defparam G_171.INIT = 16'h6996; + LUT4 G_171 ( + .I0(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_2_), + .I1(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_5_), + .I2(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_20_), + .I3(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_23_), + .O(N_176) + ); + defparam G_170.INIT = 16'h6996; + LUT4 G_170 ( + .I0(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_12_), + .I1(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_19_), + .I2(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_20_), + .I3(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_22_), + .O(N_175) + ); + defparam G_167.INIT = 16'h6996; + LUT4 G_167 ( + .I0(data_in_q[2]), + .I1(data_in_q[14]), + .I2(data_in_q[32]), + .I3(data_in_q[39]), + .O(N_172) + ); + defparam G_164.INIT = 16'h6996; + LUT4 G_164 ( + .I0(data_in_q[30]), + .I1(data_in_q[44]), + .I2(data_in_q[57]), + .I3(data_in_q[59]), + .O(G_164_616) + ); + defparam G_154.INIT = 16'h6996; + LUT4 G_154 ( + .I0(data_in_q[27]), + .I1(data_in_q[28]), + .I2(data_in_q[30]), + .I3(data_in_q[35]), + .O(N_159) + ); + defparam G_153.INIT = 16'h6996; + LUT4 G_153 ( + .I0(data_in_q[28]), + .I1(data_in_q[40]), + .I2(data_in_q[41]), + .I3(data_in_q[44]), + .O(N_157) + ); + defparam G_143.INIT = 16'h6996; + LUT4 G_143 ( + .I0(data_in_q[13]), + .I1(data_in_q[24]), + .I2(data_in_q[37]), + .I3(data_in_q[51]), + .O(N_147) + ); + defparam G_133.INIT = 16'h6996; + LUT4 G_133 ( + .I0(data_in_q[18]), + .I1(data_in_q[31]), + .I2(data_in_q[49]), + .I3(data_in_q[52]), + .O(N_137) + ); + defparam G_130.INIT = 16'h6996; + LUT4 G_130 ( + .I0(data_in_q[29]), + .I1(data_in_q[32]), + .I2(data_in_q[54]), + .I3(data_in_q[60]), + .O(N_134) + ); + defparam G_128.INIT = 16'h6996; + LUT4 G_128 ( + .I0(data_in_q[23]), + .I1(data_in_q[28]), + .I2(data_in_q[52]), + .I3(data_in_q[60]), + .O(N_132) + ); + defparam G_126.INIT = 16'h6996; + LUT4 G_126 ( + .I0(data_in_q[4]), + .I1(data_in_q[20]), + .I2(data_in_q[54]), + .I3(data_in_q[55]), + .O(N_130) + ); + defparam G_125.INIT = 16'h6996; + LUT4 G_125 ( + .I0(data_in_q[9]), + .I1(data_in_q[26]), + .I2(data_in_q[31]), + .I3(data_in_q[55]), + .O(N_129) + ); + defparam G_113.INIT = 16'h6996; + LUT4 G_113 ( + .I0(data_in_q[3]), + .I1(data_in_q[25]), + .I2(data_in_q[47]), + .I3(data_in_q[50]), + .O(N_117) + ); + defparam G_112.INIT = 16'h6996; + LUT4 G_112 ( + .I0(data_in_q[14]), + .I1(data_in_q[56]), + .I2(data_in_q[58]), + .I3(data_in_q[59]), + .O(G_112_381) + ); + defparam G_111.INIT = 16'h6996; + LUT4 G_111 ( + .I0(data_in_q[2]), + .I1(data_in_q[51]), + .I2(data_in_q[56]), + .I3(data_in_q[57]), + .O(G_111_384) + ); + defparam G_110.INIT = 16'h6996; + LUT4 G_110 ( + .I0(data_in_q[50]), + .I1(data_in_q[56]), + .I2(data_in_q[60]), + .I3(data_in_q[62]), + .O(N_114) + ); + defparam G_201.INIT = 16'h6996; + LUT4 G_201 ( + .I0(com_llm_llm_tx_top_tx_dllp_td_42_), + .I1(com_llm_llm_tx_top_tx_dllp_td_44_), + .I2(com_llm_llm_tx_top_tx_dllp_td_45_), + .I3(com_llm_llm_tx_top_tx_dllp_td_53_), + .O(N_11878) + ); + defparam G_78.INIT = 16'h6996; + LUT4 G_78 ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[7]), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[13]), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[17]), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[27]), + .O(N_82) + ); + defparam G_95.INIT = 16'h6996; + LUT4 G_95 ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[3]), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[9]), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[11]), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[24]), + .O(N_99) + ); + defparam G_106.INIT = 16'h6996; + LUT4 G_106 ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[7]), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[11]), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[20]), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[29]), + .O(N_11850) + ); + defparam G_183.INIT = 16'h6996; + LUT4 G_183 ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crc32_d64_feedback[12]), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crc32_d64_feedback[16]), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crc32_d64_feedback[19]), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crc32_d64_feedback[25]), + .O(N_188) + ); + defparam G_200.INIT = 16'h6996; + LUT4 G_200 ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crc32_d64_feedback[16]), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crc32_d64_feedback[24]), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crc32_d64_feedback[26]), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crc32_d64_feedback[27]), + .O(N_206) + ); + defparam G_217.INIT = 16'h6996; + LUT4 G_217 ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crc32_d64_feedback[10]), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crc32_d64_feedback[14]), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crc32_d64_feedback[29]), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crc32_d64_feedback[31]), + .O(N_223) + ); + defparam G_268.INIT = 16'h6996; + LUT4 G_268 ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crc32_d64_feedback[6]), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crc32_d64_feedback[12]), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crc32_d64_feedback[14]), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crc32_d64_feedback[28]), + .O(N_11926) + ); + defparam G_385.INIT = 16'h6996; + LUT4 G_385 ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[2]), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[8]), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[19]), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[25]), + .O(N_12043) + ); + defparam G_289.INIT = 8'h96; + LUT3 G_289 ( + .I0(com_llm_llm_tx_top_tx_dllp_td_25_), + .I1(com_llm_llm_tx_top_tx_dllp_td_33_), + .I2(com_llm_llm_tx_top_tx_dllp_td_35_), + .O(N_11947) + ); + defparam G_89.INIT = 16'h6996; + LUT4 G_89 ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[15]), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[21]), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[22]), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[28]), + .O(N_93) + ); + defparam G_91.INIT = 8'h96; + LUT3 G_91 ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[18]), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[21]), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[22]), + .O(N_95) + ); + defparam m12_0_o3.INIT = 8'h40; + LUT3 m12_0_o3 ( + .I0(com_cmml_protocol_err_n), + .I1(com_tlm_cmmt_err_flow_control), + .I2(com_tlm_cmmt_err_rbuf_overflow), + .O(N_56469_i) + ); + defparam G_498.INIT = 8'h96; + LUT3 G_498 ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crc32_d64_feedback[2]), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crc32_d64_feedback[3]), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crc32_d64_feedback[6]), + .O(N_12156) + ); + defparam G_515.INIT = 8'h96; + LUT3 G_515 ( + .I0(N_102), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[18]), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[30]), + .O(N_12173) + ); + defparam G_291.INIT = 8'h96; + LUT3 G_291 ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crc32_d64_feedback[5]), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crc32_d64_feedback[7]), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crc32_d64_feedback[26]), + .O(N_11949) + ); + defparam G_282.INIT = 8'h96; + LUT3 G_282 ( + .I0(N_11940_1), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crc32_d64_feedback[11]), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crc32_d64_feedback[15]), + .O(N_11940) + ); + defparam G_281.INIT = 4'h6; + LUT2 G_281 ( + .I0(N_11939_1), + .I1(N_11940_1), + .O(N_11939) + ); + defparam G_269.INIT = 8'h96; + LUT3 G_269 ( + .I0(N_11927_1), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crc32_d64_feedback[12]), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crc32_d64_feedback[22]), + .O(N_11927) + ); + defparam G_176.INIT = 16'h6996; + LUT4 G_176 ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crc32_d64_feedback[12]), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crc32_d64_feedback[17]), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crc32_d64_feedback[22]), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crc32_d64_feedback[27]), + .O(N_181) + ); + defparam G_148.INIT = 8'h96; + LUT3 G_148 ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[1]), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[21]), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[30]), + .O(N_152) + ); + defparam G_147.INIT = 16'h6996; + LUT4 G_147 ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[8]), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[11]), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[14]), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[30]), + .O(N_151) + ); + defparam G_139.INIT = 8'h96; + LUT3 G_139 ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[5]), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[25]), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[29]), + .O(N_143) + ); + defparam G_107.INIT = 8'h96; + LUT3 G_107 ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[20]), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[21]), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[28]), + .O(N_11851) + ); + defparam G_105.INIT = 16'h6996; + LUT4 G_105 ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[0]), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[1]), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[4]), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[20]), + .O(N_109) + ); + defparam G_100.INIT = 16'h6996; + LUT4 G_100 ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[16]), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[25]), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[27]), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[28]), + .O(N_104) + ); + defparam G_96.INIT = 8'h96; + LUT3 G_96 ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[20]), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[24]), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[28]), + .O(N_100) + ); + defparam G_82.INIT = 8'h96; + LUT3 G_82 ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[17]), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[25]), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[30]), + .O(N_86) + ); + defparam G_80.INIT = 16'h6996; + LUT4 G_80 ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[5]), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[12]), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[17]), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[25]), + .O(N_84) + ); + defparam G_76.INIT = 8'h96; + LUT3 G_76 ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[17]), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[25]), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[29]), + .O(N_80) + ); + defparam G_69.INIT = 8'h96; + LUT3 G_69 ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[24]), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[27]), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[31]), + .O(N_73) + ); + defparam G_64.INIT = 16'h6996; + LUT4 G_64 ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[16]), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[20]), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[28]), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[31]), + .O(N_68) + ); + defparam G_42.INIT = 16'h6996; + LUT4 G_42 ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[5]), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[8]), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[12]), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[23]), + .O(N_46) + ); + defparam G_39.INIT = 16'h6996; + LUT4 G_39 ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[18]), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[22]), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[23]), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[30]), + .O(N_43) + ); + defparam G_315.INIT = 8'h96; + LUT3 G_315 ( + .I0(N_11973_1), + .I1(com_llm_llm_tx_top_tx_dllp_td_39_), + .I2(com_llm_llm_tx_top_tx_dllp_td_49_), + .O(N_11973) + ); + defparam I_5005_i_0_0_0_1.INIT = 4'h4; + LUT2 I_5005_i_0_0_0_1 ( + .I0(N_56126_i), + .I1(plm_fsm_reg_state_1__425), + .O(N_14474_1_i) + ); + defparam G_231.INIT = 8'h96; + LUT3 G_231 ( + .I0(N_237_1), + .I1(data_in_q[17]), + .I2(data_in_q[36]), + .O(N_237) + ); + defparam G_235.INIT = 8'h96; + LUT3 G_235 ( + .I0(N_11894_1), + .I1(data_in_q[38]), + .I2(data_in_q[45]), + .O(G_235_617) + ); + defparam G_271.INIT = 8'h96; + LUT3 G_271 ( + .I0(N_11929_2), + .I1(data_in_q[22]), + .I2(data_in_q[42]), + .O(G_271_618) + ); + defparam G_398.INIT = 8'h96; + LUT3 G_398 ( + .I0(data_in_q[11]), + .I1(data_in_q[23]), + .I2(data_in_q[61]), + .O(G_398_619) + ); + defparam G_414.INIT = 4'h6; + LUT2 G_414 ( + .I0(N_12072_1), + .I1(plm_des3_reg_lfsr_one_12__620), + .O(G_414_621) + ); + defparam G_415.INIT = 8'h96; + LUT3 G_415 ( + .I0(plm_des0_reg_lfsr_one_0__561), + .I1(plm_des0_reg_lfsr_one_11__563), + .I2(plm_des0_reg_lfsr_one_12__622), + .O(G_415_623) + ); + defparam G_420.INIT = 4'h6; + LUT2 G_420 ( + .I0(N_12078_1), + .I1(plm_des1_reg_lfsr_one_12__624), + .O(G_420_625) + ); + defparam G_526_i_x4_0_x4.INIT = 8'h69; + LUT3 G_526_i_x4_0_x4 ( + .I0(plm_des3_reg_lfsr_two_3__626), + .I1(plm_des3_reg_lfsr_two_12__627), + .I2(plm_des3_reg_lfsr_two_14__628), + .O(N_49072_i_0) + ); + defparam G_401_0.INIT = 4'h6; + LUT2 G_401_0 ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d64_19__94), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d64_31__463), + .O(G_401_0_370) + ); + defparam m4_1.INIT = 4'h6; + LUT2 m4_1 ( + .I0(com_cmml_protocol_err_n), + .I1(com_tlm_cmmt_err_flow_control), + .O(m4_1_292) + ); + defparam G_457_1.INIT = 4'h6; + LUT2 G_457_1 ( + .I0(data_in_q[29]), + .I1(data_in_q[46]), + .O(G_457_1_429) + ); + defparam I_5005_i_0_0_0_1_0.INIT = 4'h8; + LUT2 I_5005_i_0_0_0_1_0 ( + .I0(plm_rx1_lane_pad), + .I1(plm_rx1_link_pad), + .O(N_14474_i_1) + ); + defparam I_5027_i_0_0_0_1.INIT = 4'h8; + LUT2 I_5027_i_0_0_0_1 ( + .I0(plm_rx3_lane_pad), + .I1(plm_rx3_link_pad), + .O(N_22668_i_1) + ); + defparam m24.INIT = 4'h6; + LUT2 m24 ( + .I0(com_cmm_u_cmm_errman_wtd_cor_add_input_five_n_d_104), + .I1(com_cmm_u_cmm_errman_wtd_cor_add_input_four_n_d_629), + .O(m24_303) + ); + defparam m10.INIT = 4'h4; + LUT2 m10 ( + .I0(com_cmm_u_cmm_errman_wtd_cor_add_input_one_d_109), + .I1(com_cmm_u_cmm_errman_wtd_cor_add_input_two_n_d_106), + .O(m10_630) + ); + defparam G_98.INIT = 4'h6; + LUT2 G_98 ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[16]), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[21]), + .O(N_102) + ); + defparam G_101.INIT = 4'h6; + LUT2 G_101 ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[16]), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_d64_c_q_2__631), + .O(N_105) + ); + defparam G_117.INIT = 4'h6; + LUT2 G_117 ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[18]), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[27]), + .O(N_11855) + ); + defparam G_304.INIT = 4'h6; + LUT2 G_304 ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[1]), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[2]), + .O(N_11962) + ); + defparam G_382.INIT = 4'h6; + LUT2 G_382 ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[19]), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[22]), + .O(N_12040) + ); + defparam G_383.INIT = 4'h6; + LUT2 G_383 ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[19]), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[29]), + .O(N_12041) + ); + defparam G_384.INIT = 4'h6; + LUT2 G_384 ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[15]), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[19]), + .O(N_12042) + ); + defparam G_406.INIT = 4'h6; + LUT2 G_406 ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crc32_d64_feedback[4]), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crc32_d64_feedback[23]), + .O(N_12064) + ); + defparam G_437.INIT = 4'h6; + LUT2 G_437 ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[12]), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[28]), + .O(N_12095) + ); + defparam G_441.INIT = 4'h6; + LUT2 G_441 ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[26]), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_d64_c_q_5__632), + .O(N_12099) + ); + defparam G_446.INIT = 4'h6; + LUT2 G_446 ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crc32_d64_feedback[2]), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crc32_d64_feedback[10]), + .O(N_12104) + ); + defparam G_509.INIT = 4'h6; + LUT2 G_509 ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[2]), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[4]), + .O(N_12167) + ); + defparam G_511.INIT = 4'h6; + LUT2 G_511 ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crc32_d64_feedback[2]), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crc32_d64_feedback[7]), + .O(N_12169) + ); + defparam G_489_1.INIT = 4'h6; + LUT2 G_489_1 ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crc32_d64_feedback[14]), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crc32_d64_feedback[22]), + .O(N_12147_1) + ); + defparam G_430_1.INIT = 4'h6; + LUT2 G_430_1 ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crc32_d64_feedback[6]), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crc32_d64_feedback[25]), + .O(N_12088_1) + ); + defparam G_312_1.INIT = 4'h6; + LUT2 G_312_1 ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crc32_d64_feedback[0]), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crc32_d64_feedback[3]), + .O(N_11970_1) + ); + defparam G_282_1.INIT = 4'h6; + LUT2 G_282_1 ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crc32_d64_feedback[1]), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crc32_d64_feedback[4]), + .O(N_11940_1) + ); + defparam G_281_1.INIT = 4'h6; + LUT2 G_281_1 ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crc32_d64_feedback[16]), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crc32_d64_feedback[20]), + .O(N_11939_1) + ); + defparam G_276_1.INIT = 4'h6; + LUT2 G_276_1 ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crc32_d64_feedback[0]), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crc32_d64_feedback[26]), + .O(N_11934_1) + ); + defparam G_269_1.INIT = 4'h6; + LUT2 G_269_1 ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crc32_d64_feedback[13]), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crc32_d64_feedback[15]), + .O(N_11927_1) + ); + defparam G_266_1.INIT = 4'h6; + LUT2 G_266_1 ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crc32_d64_feedback[20]), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crc32_d64_feedback[25]), + .O(N_11924_1) + ); + defparam G_211_1.INIT = 4'h6; + LUT2 G_211_1 ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crc32_d64_feedback[23]), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crc32_d64_feedback[30]), + .O(N_217_1) + ); + defparam G_208_1.INIT = 4'h6; + LUT2 G_208_1 ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crc32_d64_feedback[1]), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crc32_d64_feedback[8]), + .O(N_11884_1) + ); + defparam G_199_1.INIT = 4'h6; + LUT2 G_199_1 ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crc32_d64_feedback[24]), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crc32_d64_feedback[28]), + .O(N_11877_1) + ); + defparam G_181_1.INIT = 4'h6; + LUT2 G_181_1 ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crc32_d64_feedback[18]), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crc32_d64_feedback[19]), + .O(N_186_1) + ); + defparam G_77_1.INIT = 4'h6; + LUT2 G_77_1 ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[16]), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[24]), + .O(N_81_1) + ); + defparam G_278_1.INIT = 4'h6; + LUT2 G_278_1 ( + .I0(com_llm_llm_tx_top_tx_dllp_td_41_), + .I1(com_llm_llm_tx_top_tx_dllp_td_48_), + .O(N_11936_1) + ); + defparam G_258_1.INIT = 4'h6; + LUT2 G_258_1 ( + .I0(com_llm_llm_tx_top_tx_dllp_td_26_), + .I1(com_llm_llm_tx_top_tx_dllp_td_53_), + .O(N_11916_1) + ); + defparam G_315_1.INIT = 4'h6; + LUT2 G_315_1 ( + .I0(com_llm_llm_tx_top_tx_dllp_td_27_), + .I1(com_llm_llm_tx_top_tx_dllp_td_31_), + .O(N_11973_1) + ); + defparam I_4994_i_0_0_0_o3.INIT = 4'h1; + LUT2 I_4994_i_0_0_0_o3 ( + .I0(plm_rx0_ts1_c), + .I1(plm_rx0_ts2_c), + .O(N_56123_i) + ); + defparam I_4994_i_0_0_0_o2.INIT = 4'h8; + LUT2 I_4994_i_0_0_0_o2 ( + .I0(plm_rx0_lane_pad), + .I1(plm_rx0_link_pad), + .O(N_56496_i) + ); + defparam I_5005_i_0_0_0_o3.INIT = 4'h1; + LUT2 I_5005_i_0_0_0_o3 ( + .I0(plm_rx1_ts1_c), + .I1(plm_rx1_ts2_c), + .O(N_56126_i) + ); + defparam G_497_0_x4_0_x4.INIT = 4'h6; + LUT2 G_497_0_x4_0_x4 ( + .I0(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_27_), + .I1(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_31_), + .O(N_31583_i_0) + ); + defparam G_317_1.INIT = 4'h6; + LUT2 G_317_1 ( + .I0(com_llm_llm_rx_top_rx_data_59_), + .I1(com_llm_llm_rx_top_rx_data_63_), + .O(N_11975_1) + ); + defparam G_246_1.INIT = 4'h6; + LUT2 G_246_1 ( + .I0(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_41_), + .I1(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_47_), + .O(N_11904_1) + ); + defparam G_245_1.INIT = 4'h6; + LUT2 G_245_1 ( + .I0(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_37_), + .I1(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_42_), + .O(N_11903_1) + ); + defparam G_149_1.INIT = 4'h6; + LUT2 G_149_1 ( + .I0(data_in_q[29]), + .I1(data_in_q[58]), + .O(N_11867_1) + ); + defparam G_159_1.INIT = 4'h6; + LUT2 G_159_1 ( + .I0(data_in_q[21]), + .I1(data_in_q[22]), + .O(N_11871_1) + ); + defparam G_160_1.INIT = 4'h6; + LUT2 G_160_1 ( + .I0(data_in_q[15]), + .I1(data_in_q[33]), + .O(N_165_1) + ); + defparam G_161_1.INIT = 4'h6; + LUT2 G_161_1 ( + .I0(data_in_q[3]), + .I1(data_in_q[59]), + .O(N_11872_1) + ); + defparam G_169_1.INIT = 4'h6; + LUT2 G_169_1 ( + .I0(data_in_q[2]), + .I1(data_in_q[19]), + .O(N_174_1) + ); + defparam G_194_1.INIT = 4'h6; + LUT2 G_194_1 ( + .I0(data_in_q[8]), + .I1(data_in_q[26]), + .O(N_199_1) + ); + defparam G_196_1.INIT = 4'h6; + LUT2 G_196_1 ( + .I0(data_in_q[6]), + .I1(data_in_q[29]), + .O(N_202_1) + ); + defparam G_197_1.INIT = 4'h6; + LUT2 G_197_1 ( + .I0(data_in_q[44]), + .I1(data_in_q[47]), + .O(N_11876_1) + ); + defparam G_204_1.INIT = 4'h6; + LUT2 G_204_1 ( + .I0(data_in_q[36]), + .I1(data_in_q[54]), + .O(N_11881_1) + ); + defparam G_206_1.INIT = 4'h6; + LUT2 G_206_1 ( + .I0(data_in_q[24]), + .I1(data_in_q[27]), + .O(N_212_1) + ); + defparam G_228_1.INIT = 4'h6; + LUT2 G_228_1 ( + .I0(data_in_q[1]), + .I1(data_in_q[30]), + .O(N_11888_1) + ); + defparam G_231_1.INIT = 4'h6; + LUT2 G_231_1 ( + .I0(data_in_q[0]), + .I1(data_in_q[24]), + .O(N_237_1) + ); + defparam G_233_1.INIT = 4'h6; + LUT2 G_233_1 ( + .I0(data_in_q[26]), + .I1(data_in_q[61]), + .O(N_11891_1) + ); + defparam G_236_1.INIT = 4'h6; + LUT2 G_236_1 ( + .I0(data_in_q[20]), + .I1(data_in_q[33]), + .O(N_11894_1) + ); + defparam G_241_1.INIT = 4'h6; + LUT2 G_241_1 ( + .I0(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_4_), + .I1(com_llm_llm_rx_top_rx_data_56_), + .O(N_11899_1) + ); + defparam G_243_1.INIT = 4'h6; + LUT2 G_243_1 ( + .I0(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_5_), + .I1(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_10_), + .O(N_11901_1) + ); + defparam G_244_1.INIT = 4'h6; + LUT2 G_244_1 ( + .I0(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_9_), + .I1(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_15_), + .O(N_11902_1) + ); + defparam G_271_2.INIT = 4'h6; + LUT2 G_271_2 ( + .I0(data_in_q[0]), + .I1(data_in_q[34]), + .O(N_11929_2) + ); + defparam G_287_1.INIT = 4'h6; + LUT2_L G_287_1 ( + .I0(data_in_q[5]), + .I1(data_in_q[53]), + .LO(N_11945_1) + ); + defparam G_343_1.INIT = 4'h6; + LUT2 G_343_1 ( + .I0(plm_scr1_reg_lfsr_two_0__633), + .I1(plm_scr1_reg_lfsr_two_11__634), + .O(N_12001_1) + ); + defparam G_414_1.INIT = 4'h6; + LUT2 G_414_1 ( + .I0(plm_des3_reg_lfsr_one_0__635), + .I1(plm_des3_reg_lfsr_one_11__636), + .O(N_12072_1) + ); + defparam G_416_1.INIT = 4'h6; + LUT2 G_416_1 ( + .I0(plm_scr3_reg_lfsr_one_0__637), + .I1(plm_scr3_reg_lfsr_one_11__638), + .O(N_12074_1) + ); + defparam G_417_1.INIT = 4'h6; + LUT2_L G_417_1 ( + .I0(plm_scr1_reg_lfsr_one_0__102), + .I1(plm_scr1_reg_lfsr_one_11__101), + .LO(N_12075_1) + ); + defparam G_420_1.INIT = 4'h6; + LUT2 G_420_1 ( + .I0(plm_des1_reg_lfsr_one_0__639), + .I1(plm_des1_reg_lfsr_one_11__640), + .O(N_12078_1) + ); + defparam G_421_1.INIT = 4'h6; + LUT2 G_421_1 ( + .I0(plm_des2_reg_lfsr_one_0__641), + .I1(plm_des2_reg_lfsr_one_11__642), + .O(N_12079_1) + ); + defparam G_422_1.INIT = 4'h6; + LUT2 G_422_1 ( + .I0(plm_scr0_reg_lfsr_one_0__643), + .I1(plm_scr0_reg_lfsr_one_11__644), + .O(N_12080_1) + ); + defparam G_423_1.INIT = 4'h6; + LUT2 G_423_1 ( + .I0(plm_scr2_reg_lfsr_one_0__645), + .I1(plm_scr2_reg_lfsr_one_11__646), + .O(N_12081_1) + ); + defparam G_425_1.INIT = 4'h6; + LUT2 G_425_1 ( + .I0(data_in_q[48]), + .I1(data_in_q[63]), + .O(N_12083_1) + ); + defparam G_435_0_x4_0_x2_0_x4.INIT = 4'h6; + LUT2 G_435_0_x4_0_x2_0_x4 ( + .I0(plm_des0_reg_lfsr_two_1__647), + .I1(plm_des0_reg_lfsr_two_2__648), + .O(N_49163_i_0) + ); + defparam G_501_0_x4_0_x2_0_x4.INIT = 4'h6; + LUT2 G_501_0_x4_0_x2_0_x4 ( + .I0(plm_des0_reg_lfsr_two_11__531), + .I1(plm_des0_reg_lfsr_two_14__649), + .O(N_49162_i_0) + ); + defparam G_358_0_x4_0_x2_0_x4.INIT = 4'h6; + LUT2 G_358_0_x4_0_x2_0_x4 ( + .I0(plm_des0_reg_lfsr_one_3__566), + .I1(plm_des0_reg_lfsr_one_14__650), + .O(N_49160_i_0) + ); + defparam G_342_0_x4_0_x2_0_x4.INIT = 4'h6; + LUT2 G_342_0_x4_0_x2_0_x4 ( + .I0(plm_des0_reg_lfsr_two_4__651), + .I1(plm_des0_reg_lfsr_two_15__533), + .O(N_49159_i_0) + ); + defparam G_503_0_x4_0_x2_0_x4.INIT = 4'h6; + LUT2 G_503_0_x4_0_x2_0_x4 ( + .I0(plm_des1_reg_lfsr_two_11__544), + .I1(plm_des1_reg_lfsr_two_14__652), + .O(N_49152_i_0) + ); + defparam G_356_0_x4_0_x2_0_x4.INIT = 4'h6; + LUT2 G_356_0_x4_0_x2_0_x4 ( + .I0(plm_des1_reg_lfsr_one_3__504), + .I1(plm_des1_reg_lfsr_one_14__653), + .O(N_49150_i_0) + ); + defparam G_348_0_x4_0_x2_0_x4.INIT = 4'h6; + LUT2 G_348_0_x4_0_x2_0_x4 ( + .I0(plm_des1_reg_lfsr_two_4__654), + .I1(plm_des1_reg_lfsr_two_15__546), + .O(N_49149_i_0) + ); + defparam G_502_0_x4_0_x2_0_x4.INIT = 4'h6; + LUT2 G_502_0_x4_0_x2_0_x4 ( + .I0(plm_des2_reg_lfsr_two_11__486), + .I1(plm_des2_reg_lfsr_two_14__655), + .O(N_49141_i_0) + ); + defparam G_361_0_x4_0_x2_0_x4.INIT = 4'h6; + LUT2 G_361_0_x4_0_x2_0_x4 ( + .I0(plm_des2_reg_lfsr_one_3__522), + .I1(plm_des2_reg_lfsr_one_14__656), + .O(N_49139_i_0) + ); + defparam G_362_0_x4_0_x2_0_x4.INIT = 4'h6; + LUT2 G_362_0_x4_0_x2_0_x4 ( + .I0(plm_des3_reg_lfsr_one_3__516), + .I1(plm_des3_reg_lfsr_one_14__657), + .O(N_49118_i_0) + ); + defparam G_481_0_x2_0_x4.INIT = 4'h6; + LUT2 G_481_0_x2_0_x4 ( + .I0(plm_des1_reg_lfsr_two_1__658), + .I1(plm_des1_reg_lfsr_two_2__659), + .O(N_49108_i_0) + ); + defparam G_340_0_x2_0_x4.INIT = 4'h6; + LUT2 G_340_0_x2_0_x4 ( + .I0(plm_des3_reg_lfsr_two_4__660), + .I1(plm_des3_reg_lfsr_two_15__528), + .O(N_49107_i_0) + ); + defparam G_520_0_x4_0_x4.INIT = 4'h6; + LUT2 G_520_0_x4_0_x4 ( + .I0(plm_des3_reg_lfsr_two_11__526), + .I1(plm_des3_reg_lfsr_two_14__628), + .O(N_49085_i_0) + ); + defparam G_525_0_x4.INIT = 4'h6; + LUT2 G_525_0_x4 ( + .I0(plm_des3_reg_lfsr_two_2__661), + .I1(plm_des3_reg_lfsr_two_13__527), + .O(N_49083_i_0) + ); + defparam G_494_0_x4.INIT = 4'h6; + LUT2 G_494_0_x4 ( + .I0(plm_des2_reg_lfsr_two_1__662), + .I1(plm_des2_reg_lfsr_two_2__663), + .O(N_49082_i_0) + ); + defparam G_352_0_x4.INIT = 4'h6; + LUT2 G_352_0_x4 ( + .I0(plm_des2_reg_lfsr_two_4__664), + .I1(plm_des2_reg_lfsr_two_15__488), + .O(N_49081_i_0) + ); + defparam m10_3_0_0_a3.INIT = 4'h1; + LUT2 m10_3_0_0_a3 ( + .I0(plm_dfm_deframe1_dword_edbedg[0]), + .I1(plm_dfm_deframe1_dword_edbedg[1]), + .O(m10_3_0_0_a3_117) + ); + defparam G_409_0_x4_0.INIT = 4'h6; + LUT2_L G_409_0_x4_0 ( + .I0(com_llm_llm_rx_top_rx_data_34_), + .I1(com_llm_llm_rx_top_rx_data_61_), + .LO(N_31580_i) + ); + defparam G_492_0_x4.INIT = 4'h6; + LUT2 G_492_0_x4 ( + .I0(plm_scr0_reg_lfsr_two_1__665), + .I1(plm_scr0_reg_lfsr_two_2__666), + .O(N_21118_i_0) + ); + defparam G_505_0_x4.INIT = 4'h6; + LUT2 G_505_0_x4 ( + .I0(plm_scr2_reg_lfsr_two_11__483), + .I1(plm_scr2_reg_lfsr_two_14__667), + .O(N_20991_i_0) + ); + defparam G_496_0_x4.INIT = 4'h6; + LUT2 G_496_0_x4 ( + .I0(plm_scr2_reg_lfsr_two_1__668), + .I1(plm_scr2_reg_lfsr_two_12__669), + .O(N_20990_i_0) + ); + defparam G_365_0_x4.INIT = 4'h6; + LUT2 G_365_0_x4 ( + .I0(plm_scr2_reg_lfsr_two_3__670), + .I1(plm_scr2_reg_lfsr_two_14__667), + .O(N_20989_i_0) + ); + defparam G_350_0_x4.INIT = 4'h6; + LUT2 G_350_0_x4 ( + .I0(plm_scr2_reg_lfsr_two_4__671), + .I1(plm_scr2_reg_lfsr_two_15__426), + .O(N_20988_i_0) + ); + defparam G_474_0_x4.INIT = 4'h6; + LUT2 G_474_0_x4 ( + .I0(plm_scr3_reg_lfsr_two_1__672), + .I1(plm_scr3_reg_lfsr_two_2__673), + .O(N_20852_i_0) + ); + defparam G_519_0_x2.INIT = 4'h6; + LUT2 G_519_0_x2 ( + .I0(plm_scr2_reg_lfsr_two_2__674), + .I1(plm_scr2_reg_lfsr_two_13__484), + .O(N_13591_i_0) + ); + defparam G_360_0_x4.INIT = 4'h6; + LUT2 G_360_0_x4 ( + .I0(plm_scr2_reg_lfsr_one_3__558), + .I1(plm_scr2_reg_lfsr_one_14__675), + .O(N_13489_i_0) + ); + defparam G_500.INIT = 4'h6; + LUT2 G_500 ( + .I0(plm_scr1_reg_lfsr_two_11__634), + .I1(plm_scr1_reg_lfsr_two_14__676), + .O(G_500_677) + ); + defparam G_477.INIT = 4'h6; + LUT2 G_477 ( + .I0(data_in_q[25]), + .I1(data_in_q[49]), + .O(G_477_678) + ); + defparam G_436.INIT = 4'h6; + LUT2 G_436 ( + .I0(plm_scr1_reg_lfsr_two_1__679), + .I1(plm_scr1_reg_lfsr_two_2__680), + .O(G_436_681) + ); + defparam G_410.INIT = 4'h6; + LUT2 G_410 ( + .I0(plm_scr0_reg_lfsr_two_3__682), + .I1(plm_scr0_reg_lfsr_two_14__683), + .O(G_410_684) + ); + defparam G_395.INIT = 4'h6; + LUT2 G_395 ( + .I0(data_in_q[25]), + .I1(data_in_q[38]), + .O(G_395_685) + ); + defparam G_366.INIT = 4'h6; + LUT2 G_366 ( + .I0(plm_scr1_reg_lfsr_two_3__686), + .I1(plm_scr1_reg_lfsr_two_14__676), + .O(G_366_687) + ); + defparam G_359.INIT = 4'h6; + LUT2 G_359 ( + .I0(plm_scr0_reg_lfsr_one_3__572), + .I1(plm_scr0_reg_lfsr_one_14__688), + .O(G_359_689) + ); + defparam G_357.INIT = 4'h6; + LUT2 G_357 ( + .I0(plm_scr1_reg_lfsr_one_3__510), + .I1(plm_scr1_reg_lfsr_one_14__690), + .O(G_357_691) + ); + defparam G_355.INIT = 4'h6; + LUT2 G_355 ( + .I0(plm_scr3_reg_lfsr_one_3__498), + .I1(plm_scr3_reg_lfsr_one_14__692), + .O(G_355_693) + ); + defparam G_354.INIT = 4'h6; + LUT2 G_354 ( + .I0(plm_scr0_reg_lfsr_two_4__694), + .I1(plm_scr0_reg_lfsr_two_15__493), + .O(G_354_695) + ); + defparam G_344.INIT = 4'h6; + LUT2 G_344 ( + .I0(plm_scr1_reg_lfsr_two_4__696), + .I1(plm_scr1_reg_lfsr_two_15__536), + .O(G_344_697) + ); + defparam G_294.INIT = 4'h6; + LUT2 G_294 ( + .I0(data_in_q[17]), + .I1(data_in_q[30]), + .O(G_294_698) + ); + defparam G_293.INIT = 4'h6; + LUT2 G_293 ( + .I0(data_in_q[17]), + .I1(data_in_q[35]), + .O(G_293_699) + ); + defparam G_272.INIT = 4'h6; + LUT2 G_272 ( + .I0(data_in_q[13]), + .I1(data_in_q[42]), + .O(G_272_700) + ); + FDR regcom_cmm_u_cmm_errman_wtd_nfl_reg_cor_num_0_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(NlwRenamedSig_OI_cfg_status_4_), + .Q(com_cmm_u_cmm_pm_dev_power_state_eq_d0), + .R(com_cmm_rst_351) + ); + GND GND_0 ( + .G(NlwRenamedSignal_cfg_lcommand[15]) + ); + VCC VCC_1 ( + .P(NlwRenamedSig_OI_cfg_status_4_) + ); + VCC plm_VCC ( + .P(plm_VCC_701) + ); + GND plm_GND ( + .G(plm_GND_702) + ); + defparam plm_un2_tstall_n_0_a2_0.INIT = 4'h1; + LUT2_L plm_un2_tstall_n_0_a2_0 ( + .I0(plm_reg_raw_tstall_d2_706), + .I1(plm_reg_raw_tstall_d3_705), + .LO(plm_un2_tstall_n_0_a2_0_704) + ); + defparam plm_N_61233_i.INIT = 4'hE; + LUT2_L plm_N_61233_i ( + .I0(cfg_cfg_6102[510]), + .I1(plm_noscramble), + .LO(plm_N_61233_i_703) + ); + defparam plm_N_62716_i.INIT = 4'hE; + LUT2_L plm_N_62716_i ( + .I0(plm_phy_rbad_dfrm_h), + .I1(plm_phy_rbad_dfrm_l), + .LO(N_62716_i) + ); + defparam plm_un3_tstall_n_0_m3_0.INIT = 16'h1311; + LUT4_L plm_un3_tstall_n_0_m3_0 ( + .I0(cmmp_negotiated_width_1[0]), + .I1(plm_raw_tstall), + .I2(plm_reg_raw_tstall_d1_707), + .I3(plm_un2_tstall_n_0_a2_0_704), + .LO(plm_un3_tstall_n_0_m3_0_708) + ); + FDC plm_reg_raw_tstall_d3 ( + .C(mgt_clk), + .D(plm_reg_raw_tstall_d2_706), + .Q(plm_reg_raw_tstall_d3_705), + .CLR(plm_rst) + ); + FDC plm_reg_raw_tstall_d2 ( + .C(mgt_clk), + .D(plm_reg_raw_tstall_d1_707), + .Q(plm_reg_raw_tstall_d2_706), + .CLR(plm_rst) + ); + FDC plm_reg_raw_tstall_d1 ( + .C(mgt_clk), + .D(plm_raw_tstall), + .Q(plm_reg_raw_tstall_d1_707), + .CLR(plm_rst) + ); + FDPE plm_reg_phy_tstall_n ( + .PRE(plm_rst), + .CE(plm_phy_cke_3_709), + .C(mgt_clk), + .D(plm_un3_tstall_n_0_m3_0_708), + .Q(plm_phy_tstall_n) + ); + INV plm_phy_tstall_n_i ( + .I(plm_phy_tstall_n), + .O(phy_tstall_n_i) + ); + INV plm_trn_reset_n_i ( + .I(NlwRenamedSig_OI_trn_reset_n), + .O(trn_reset_n_i) + ); + BUF plm_phy_cke_0 ( + .I(plm_phy_cke), + .O(plm_phy_cke_0_712) + ); + BUF plm_phy_cke_1 ( + .I(plm_phy_cke), + .O(plm_phy_cke_1_711) + ); + BUF plm_phy_cke_2 ( + .I(plm_phy_cke), + .O(plm_phy_cke_2_710) + ); + BUF plm_phy_cke_3 ( + .I(plm_phy_cke), + .O(plm_phy_cke_3_709) + ); + VCC plm_v4f_mgt_VCC ( + .P(plm_v4f_mgt_pipe_phystatus) + ); + GND plm_v4f_mgt_GND ( + .G(plm_v4f_mgt_lstate_support[3]) + ); + BUFG plm_v4f_mgt_special_bufg ( + .I(sys_clkz), + .O(plm_v4f_mgt_special_clk) + ); + defparam plm_v4f_mgt_dcm.CLKFX_DIVIDE = 4; + defparam plm_v4f_mgt_dcm.CLKFX_MULTIPLY = 2; + defparam plm_v4f_mgt_dcm.CLKIN_DIVIDE_BY_2 = "TRUE"; + defparam plm_v4f_mgt_dcm.CLKIN_PERIOD = 4.0; + defparam plm_v4f_mgt_dcm.DCM_AUTOCALIBRATION = "FALSE"; + defparam plm_v4f_mgt_dcm.CLKDV_DIVIDE = 4.0; + DCM_ADV plm_v4f_mgt_dcm ( + .CLK90(NLW_plm_v4f_mgt_dcm_CLK90_UNCONNECTED), + .CLKFX(plm_v4f_mgt_dcm_clkf), + .CLKIN(sys_clkz), + .LOCKED(plm_v4f_mgt_dcm_lock), + .CLK2X(NLW_plm_v4f_mgt_dcm_CLK2X_UNCONNECTED), + .DWE(plm_v4f_mgt_lstate_support[3]), + .PSCLK(plm_v4f_mgt_lstate_support[3]), + .DCLK(plm_v4f_mgt_lstate_support[3]), + .PSDONE(NLW_plm_v4f_mgt_dcm_PSDONE_UNCONNECTED), + .PSINCDEC(plm_v4f_mgt_lstate_support[3]), + .PSEN(plm_v4f_mgt_lstate_support[3]), + .CLK0(plm_v4f_mgt_dcm_clk0), + .CLKFX180(NLW_plm_v4f_mgt_dcm_CLKFX180_UNCONNECTED), + .DEN(plm_v4f_mgt_lstate_support[3]), + .CLK180(NLW_plm_v4f_mgt_dcm_CLK180_UNCONNECTED), + .CLK2X180(NLW_plm_v4f_mgt_dcm_CLK2X180_UNCONNECTED), + .RST(plm_v4f_mgt_reg_dcm_766), + .CLK270(NLW_plm_v4f_mgt_dcm_CLK270_UNCONNECTED), + .CLKFB(mgt_clk), + .DRDY(NLW_plm_v4f_mgt_dcm_DRDY_UNCONNECTED), + .CLKDV(plm_v4f_mgt_dcm_clkd), + .DADDR({plm_v4f_mgt_lstate_support[3], plm_v4f_mgt_lstate_support[3], plm_v4f_mgt_lstate_support[3], plm_v4f_mgt_lstate_support[3], +plm_v4f_mgt_lstate_support[3], plm_v4f_mgt_lstate_support[3], plm_v4f_mgt_lstate_support[3]}), + .DI({plm_v4f_mgt_lstate_support[3], plm_v4f_mgt_lstate_support[3], plm_v4f_mgt_lstate_support[3], plm_v4f_mgt_lstate_support[3], +plm_v4f_mgt_lstate_support[3], plm_v4f_mgt_lstate_support[3], plm_v4f_mgt_lstate_support[3], plm_v4f_mgt_lstate_support[3], +plm_v4f_mgt_lstate_support[3], plm_v4f_mgt_lstate_support[3], plm_v4f_mgt_lstate_support[3], plm_v4f_mgt_lstate_support[3], +plm_v4f_mgt_lstate_support[3], plm_v4f_mgt_lstate_support[3], plm_v4f_mgt_lstate_support[3], plm_v4f_mgt_lstate_support[3]}), + .DO({NLW_plm_v4f_mgt_dcm_DO_15__UNCONNECTED, NLW_plm_v4f_mgt_dcm_DO_14__UNCONNECTED, NLW_plm_v4f_mgt_dcm_DO_13__UNCONNECTED, +NLW_plm_v4f_mgt_dcm_DO_12__UNCONNECTED, NLW_plm_v4f_mgt_dcm_DO_11__UNCONNECTED, NLW_plm_v4f_mgt_dcm_DO_10__UNCONNECTED, +NLW_plm_v4f_mgt_dcm_DO_9__UNCONNECTED, NLW_plm_v4f_mgt_dcm_DO_8__UNCONNECTED, NLW_plm_v4f_mgt_dcm_DO_7__UNCONNECTED, +NLW_plm_v4f_mgt_dcm_DO_6__UNCONNECTED, NLW_plm_v4f_mgt_dcm_DO_5__UNCONNECTED, NLW_plm_v4f_mgt_dcm_DO_4__UNCONNECTED, +NLW_plm_v4f_mgt_dcm_DO_3__UNCONNECTED, NLW_plm_v4f_mgt_dcm_DO_2__UNCONNECTED, NLW_plm_v4f_mgt_dcm_DO_1__UNCONNECTED, +NLW_plm_v4f_mgt_dcm_DO_0__UNCONNECTED}) + ); + BUFGMUX_VIRTEX4 plm_v4f_mgt_phy_bufg ( + .I0(plm_v4f_mgt_dcm_clkd), + .I1(plm_v4f_mgt_dcm_clk0), + .O(NlwRenamedSig_OI_trn_clk), + .S(cmmp_negotiated_width_0[0]) + ); + BUFG plm_v4f_mgt_mgt_bufg ( + .I(plm_v4f_mgt_dcm_clk0), + .O(mgt_clk) + ); + BUFG plm_v4f_mgt_mgtdiv2_bufg ( + .I(plm_v4f_mgt_dcm_clkf), + .O(plm_v4f_mgt_mgtdiv2_clk) + ); + BUFG plm_v4f_mgt_cal_bufg ( + .I(plm_v4f_mgt_dcm_clkd), + .O(plm_v4f_mgt_cal_clk) + ); + FD plm_v4f_mgt_SYNC0A ( + .C(mgt_clk), + .D(plm_v4f_mgt_rx0_sigdet_n_async), + .Q(plm_v4f_mgt_rx0_sigdet_n_temp) + ); + FD plm_v4f_mgt_SYNC0B ( + .C(mgt_clk), + .D(plm_v4f_mgt_rx0_sigdet_n_temp), + .Q(plm_v4f_mgt_rx0_enter_elecidle) + ); + FD plm_v4f_mgt_SYNC1A ( + .C(mgt_clk), + .D(plm_v4f_mgt_rx1_sigdet_n_async), + .Q(plm_v4f_mgt_rx1_sigdet_n_temp) + ); + FD plm_v4f_mgt_SYNC1B ( + .C(mgt_clk), + .D(plm_v4f_mgt_rx1_sigdet_n_temp), + .Q(plm_v4f_mgt_rx1_enter_elecidle) + ); + FD plm_v4f_mgt_SYNC2A ( + .C(mgt_clk), + .D(plm_v4f_mgt_rx2_sigdet_n_async), + .Q(plm_v4f_mgt_rx2_sigdet_n_temp) + ); + FD plm_v4f_mgt_SYNC2B ( + .C(mgt_clk), + .D(plm_v4f_mgt_rx2_sigdet_n_temp), + .Q(plm_v4f_mgt_rx2_enter_elecidle) + ); + FD plm_v4f_mgt_SYNC3A ( + .C(mgt_clk), + .D(plm_v4f_mgt_rx3_sigdet_n_async), + .Q(plm_v4f_mgt_rx3_sigdet_n_temp) + ); + FD plm_v4f_mgt_SYNC3B ( + .C(mgt_clk), + .D(plm_v4f_mgt_rx3_sigdet_n_temp), + .Q(plm_v4f_mgt_rx3_enter_elecidle) + ); + MUXCY_L plm_v4f_mgt_reg_rst_cnt_cry_1_ ( + .CI(plm_v4f_mgt_reg_rst_cnt[0]), + .DI(plm_v4f_mgt_lstate_support[3]), + .LO(plm_v4f_mgt_reg_rst_cnt_cry[1]), + .S(plm_v4f_mgt_reg_rst_cnt_qxu[1]) + ); + XORCY plm_v4f_mgt_reg_rst_cnt_s_1_ ( + .CI(plm_v4f_mgt_reg_rst_cnt[0]), + .LI(plm_v4f_mgt_reg_rst_cnt_qxu[1]), + .O(plm_v4f_mgt_reg_rst_cnt_s[1]) + ); + MUXCY_L plm_v4f_mgt_reg_rst_cnt_cry_2_ ( + .CI(plm_v4f_mgt_reg_rst_cnt_cry[1]), + .DI(plm_v4f_mgt_lstate_support[3]), + .LO(plm_v4f_mgt_reg_rst_cnt_cry[2]), + .S(plm_v4f_mgt_reg_rst_cnt_qxu[2]) + ); + XORCY plm_v4f_mgt_reg_rst_cnt_s_2_ ( + .CI(plm_v4f_mgt_reg_rst_cnt_cry[1]), + .LI(plm_v4f_mgt_reg_rst_cnt_qxu[2]), + .O(plm_v4f_mgt_reg_rst_cnt_s[2]) + ); + MUXCY_L plm_v4f_mgt_reg_rst_cnt_cry_3_ ( + .CI(plm_v4f_mgt_reg_rst_cnt_cry[2]), + .DI(plm_v4f_mgt_lstate_support[3]), + .LO(plm_v4f_mgt_reg_rst_cnt_cry[3]), + .S(plm_v4f_mgt_reg_rst_cnt_qxu[3]) + ); + XORCY plm_v4f_mgt_reg_rst_cnt_s_3_ ( + .CI(plm_v4f_mgt_reg_rst_cnt_cry[2]), + .LI(plm_v4f_mgt_reg_rst_cnt_qxu[3]), + .O(plm_v4f_mgt_reg_rst_cnt_s[3]) + ); + MUXCY_L plm_v4f_mgt_reg_rst_cnt_cry_4_ ( + .CI(plm_v4f_mgt_reg_rst_cnt_cry[3]), + .DI(plm_v4f_mgt_lstate_support[3]), + .LO(plm_v4f_mgt_reg_rst_cnt_cry[4]), + .S(plm_v4f_mgt_reg_rst_cnt_qxu[4]) + ); + XORCY plm_v4f_mgt_reg_rst_cnt_s_4_ ( + .CI(plm_v4f_mgt_reg_rst_cnt_cry[3]), + .LI(plm_v4f_mgt_reg_rst_cnt_qxu[4]), + .O(plm_v4f_mgt_reg_rst_cnt_s[4]) + ); + MUXCY_L plm_v4f_mgt_reg_rst_cnt_cry_5_ ( + .CI(plm_v4f_mgt_reg_rst_cnt_cry[4]), + .DI(plm_v4f_mgt_lstate_support[3]), + .LO(plm_v4f_mgt_reg_rst_cnt_cry[5]), + .S(plm_v4f_mgt_reg_rst_cnt_qxu[5]) + ); + XORCY plm_v4f_mgt_reg_rst_cnt_s_5_ ( + .CI(plm_v4f_mgt_reg_rst_cnt_cry[4]), + .LI(plm_v4f_mgt_reg_rst_cnt_qxu[5]), + .O(plm_v4f_mgt_reg_rst_cnt_s[5]) + ); + MUXCY_L plm_v4f_mgt_reg_rst_cnt_cry_6_ ( + .CI(plm_v4f_mgt_reg_rst_cnt_cry[5]), + .DI(plm_v4f_mgt_lstate_support[3]), + .LO(plm_v4f_mgt_reg_rst_cnt_cry[6]), + .S(plm_v4f_mgt_reg_rst_cnt_qxu[6]) + ); + XORCY plm_v4f_mgt_reg_rst_cnt_s_6_ ( + .CI(plm_v4f_mgt_reg_rst_cnt_cry[5]), + .LI(plm_v4f_mgt_reg_rst_cnt_qxu[6]), + .O(plm_v4f_mgt_reg_rst_cnt_s[6]) + ); + MUXCY_L plm_v4f_mgt_reg_rst_cnt_cry_7_ ( + .CI(plm_v4f_mgt_reg_rst_cnt_cry[6]), + .DI(plm_v4f_mgt_lstate_support[3]), + .LO(plm_v4f_mgt_reg_rst_cnt_cry[7]), + .S(plm_v4f_mgt_reg_rst_cnt_qxu[7]) + ); + XORCY plm_v4f_mgt_reg_rst_cnt_s_7_ ( + .CI(plm_v4f_mgt_reg_rst_cnt_cry[6]), + .LI(plm_v4f_mgt_reg_rst_cnt_qxu[7]), + .O(plm_v4f_mgt_reg_rst_cnt_s[7]) + ); + MUXCY_L plm_v4f_mgt_reg_rst_cnt_cry_8_ ( + .CI(plm_v4f_mgt_reg_rst_cnt_cry[7]), + .DI(plm_v4f_mgt_lstate_support[3]), + .LO(plm_v4f_mgt_reg_rst_cnt_cry[8]), + .S(plm_v4f_mgt_reg_rst_cnt_qxu[8]) + ); + XORCY plm_v4f_mgt_reg_rst_cnt_s_8_ ( + .CI(plm_v4f_mgt_reg_rst_cnt_cry[7]), + .LI(plm_v4f_mgt_reg_rst_cnt_qxu[8]), + .O(plm_v4f_mgt_reg_rst_cnt_s[8]) + ); + MUXCY_L plm_v4f_mgt_reg_rst_cnt_cry_9_ ( + .CI(plm_v4f_mgt_reg_rst_cnt_cry[8]), + .DI(plm_v4f_mgt_lstate_support[3]), + .LO(plm_v4f_mgt_reg_rst_cnt_cry[9]), + .S(plm_v4f_mgt_reg_rst_cnt_qxu[9]) + ); + XORCY plm_v4f_mgt_reg_rst_cnt_s_9_ ( + .CI(plm_v4f_mgt_reg_rst_cnt_cry[8]), + .LI(plm_v4f_mgt_reg_rst_cnt_qxu[9]), + .O(plm_v4f_mgt_reg_rst_cnt_s[9]) + ); + MUXCY_L plm_v4f_mgt_reg_rst_cnt_cry_10_ ( + .CI(plm_v4f_mgt_reg_rst_cnt_cry[9]), + .DI(plm_v4f_mgt_lstate_support[3]), + .LO(plm_v4f_mgt_reg_rst_cnt_cry[10]), + .S(plm_v4f_mgt_reg_rst_cnt_qxu[10]) + ); + XORCY plm_v4f_mgt_reg_rst_cnt_s_10_ ( + .CI(plm_v4f_mgt_reg_rst_cnt_cry[9]), + .LI(plm_v4f_mgt_reg_rst_cnt_qxu[10]), + .O(plm_v4f_mgt_reg_rst_cnt_s[10]) + ); + MUXCY_L plm_v4f_mgt_reg_rst_cnt_cry_11_ ( + .CI(plm_v4f_mgt_reg_rst_cnt_cry[10]), + .DI(plm_v4f_mgt_lstate_support[3]), + .LO(plm_v4f_mgt_reg_rst_cnt_cry[11]), + .S(plm_v4f_mgt_reg_rst_cnt_qxu[11]) + ); + XORCY plm_v4f_mgt_reg_rst_cnt_s_11_ ( + .CI(plm_v4f_mgt_reg_rst_cnt_cry[10]), + .LI(plm_v4f_mgt_reg_rst_cnt_qxu[11]), + .O(plm_v4f_mgt_reg_rst_cnt_s[11]) + ); + MUXCY_L plm_v4f_mgt_reg_rst_cnt_cry_12_ ( + .CI(plm_v4f_mgt_reg_rst_cnt_cry[11]), + .DI(plm_v4f_mgt_lstate_support[3]), + .LO(plm_v4f_mgt_reg_rst_cnt_cry[12]), + .S(plm_v4f_mgt_reg_rst_cnt_qxu[12]) + ); + XORCY plm_v4f_mgt_reg_rst_cnt_s_12_ ( + .CI(plm_v4f_mgt_reg_rst_cnt_cry[11]), + .LI(plm_v4f_mgt_reg_rst_cnt_qxu[12]), + .O(plm_v4f_mgt_reg_rst_cnt_s[12]) + ); + MUXCY_L plm_v4f_mgt_reg_rst_cnt_cry_13_ ( + .CI(plm_v4f_mgt_reg_rst_cnt_cry[12]), + .DI(plm_v4f_mgt_lstate_support[3]), + .LO(plm_v4f_mgt_reg_rst_cnt_cry[13]), + .S(plm_v4f_mgt_reg_rst_cnt_qxu[13]) + ); + XORCY plm_v4f_mgt_reg_rst_cnt_s_13_ ( + .CI(plm_v4f_mgt_reg_rst_cnt_cry[12]), + .LI(plm_v4f_mgt_reg_rst_cnt_qxu[13]), + .O(plm_v4f_mgt_reg_rst_cnt_s[13]) + ); + XORCY plm_v4f_mgt_reg_rst_cnt_s_14_ ( + .CI(plm_v4f_mgt_reg_rst_cnt_cry[13]), + .LI(plm_v4f_mgt_reg_rst_cnt_qxu[14]), + .O(plm_v4f_mgt_reg_rst_cnt_s[14]) + ); + defparam plm_v4f_mgt_reset_delay_reg_tx_pcs_init_3_1_0_a2.INIT = 4'h1; + LUT2 plm_v4f_mgt_reset_delay_reg_tx_pcs_init_3_1_0_a2 ( + .I0(plm_v4f_mgt_reg_rst_cnt[11]), + .I1(plm_v4f_mgt_reg_rst_cnt[12]), + .O(plm_v4f_mgt_reset_delay_reg_tx_pcs_init_3_1) + ); + defparam plm_v4f_mgt_un1_reg_plm_rst_n_2_0_0_o4_0_.INIT = 4'h8; + LUT2 plm_v4f_mgt_un1_reg_plm_rst_n_2_0_0_o4_0_ ( + .I0(plm_v4f_mgt_reg_rst_cnt[13]), + .I1(plm_v4f_mgt_reg_rst_cnt[14]), + .O(plm_v4f_mgt_un1_reg_plm_rst_n_2_0_0_o4[0]) + ); + defparam plm_v4f_mgt_un1_reg_plm_rst_n_2_0_0_o4_0_0_.INIT = 4'h8; + LUT2 plm_v4f_mgt_un1_reg_plm_rst_n_2_0_0_o4_0_0_ ( + .I0(plm_v4f_mgt_reg_rst_cnt[3]), + .I1(plm_v4f_mgt_reg_rst_cnt[4]), + .O(plm_v4f_mgt_N_871_i) + ); + defparam plm_v4f_mgt_reset_delay_reg_tx_sync_5_i_0_o4_0.INIT = 4'h4; + LUT2 plm_v4f_mgt_reset_delay_reg_tx_sync_5_i_0_o4_0 ( + .I0(plm_v4f_mgt_reg_rst_cnt[1]), + .I1(plm_v4f_mgt_reg_rst_cnt[2]), + .O(plm_v4f_mgt_reg_tx_sync_5_i_0_o4_0) + ); + defparam plm_v4f_mgt_sys_init_n_0_a2_0.INIT = 4'h8; + LUT2 plm_v4f_mgt_sys_init_n_0_a2_0 ( + .I0(plm_v4f_mgt_pma_txlock0), + .I1(plm_v4f_mgt_pma_txlock1), + .O(plm_v4f_mgt_sys_init_n_0_a2_0_716) + ); + defparam plm_v4f_mgt_un3_rx0_char_is_k.INIT = 8'hE4; + LUT3 plm_v4f_mgt_un3_rx0_char_is_k ( + .I0(plm_v4f_mgt_reg_mgtdiv2_cke_phase1_749), + .I1(plm_v4f_mgt_wrx0_char_is_k[1]), + .I2(plm_v4f_mgt_wrx0_char_is_k[3]), + .O(plm_rx0_char_is_k[0]) + ); + defparam plm_v4f_mgt_un10_rx0_char_is_k.INIT = 8'hE4; + LUT3 plm_v4f_mgt_un10_rx0_char_is_k ( + .I0(plm_v4f_mgt_reg_mgtdiv2_cke_phase1_749), + .I1(plm_v4f_mgt_wrx0_char_is_k[0]), + .I2(plm_v4f_mgt_wrx0_char_is_k[2]), + .O(plm_rx0_char_is_k[1]) + ); + defparam plm_v4f_mgt_un3_rx1_char_is_k.INIT = 8'hE4; + LUT3 plm_v4f_mgt_un3_rx1_char_is_k ( + .I0(plm_v4f_mgt_reg_mgtdiv2_cke_phase1_749), + .I1(plm_v4f_mgt_wrx1_char_is_k[1]), + .I2(plm_v4f_mgt_wrx1_char_is_k[3]), + .O(plm_rx1_char_is_k[0]) + ); + defparam plm_v4f_mgt_un10_rx1_char_is_k.INIT = 8'hE4; + LUT3 plm_v4f_mgt_un10_rx1_char_is_k ( + .I0(plm_v4f_mgt_reg_mgtdiv2_cke_phase1_749), + .I1(plm_v4f_mgt_wrx1_char_is_k[0]), + .I2(plm_v4f_mgt_wrx1_char_is_k[2]), + .O(plm_rx1_char_is_k[1]) + ); + defparam plm_v4f_mgt_un3_rx2_char_is_k.INIT = 8'hE4; + LUT3 plm_v4f_mgt_un3_rx2_char_is_k ( + .I0(plm_v4f_mgt_reg_mgtdiv2_cke_phase1_749), + .I1(plm_v4f_mgt_wrx2_char_is_k[1]), + .I2(plm_v4f_mgt_wrx2_char_is_k[3]), + .O(plm_rx2_char_is_k[0]) + ); + defparam plm_v4f_mgt_un10_rx2_char_is_k.INIT = 8'hE4; + LUT3 plm_v4f_mgt_un10_rx2_char_is_k ( + .I0(plm_v4f_mgt_reg_mgtdiv2_cke_phase1_749), + .I1(plm_v4f_mgt_wrx2_char_is_k[0]), + .I2(plm_v4f_mgt_wrx2_char_is_k[2]), + .O(plm_rx2_char_is_k[1]) + ); + defparam plm_v4f_mgt_un3_rx3_char_is_k.INIT = 8'hE4; + LUT3 plm_v4f_mgt_un3_rx3_char_is_k ( + .I0(plm_v4f_mgt_reg_mgtdiv2_cke_phase1_749), + .I1(plm_v4f_mgt_wrx3_char_is_k[1]), + .I2(plm_v4f_mgt_wrx3_char_is_k[3]), + .O(plm_rx3_char_is_k[0]) + ); + defparam plm_v4f_mgt_un10_rx3_char_is_k.INIT = 8'hE4; + LUT3 plm_v4f_mgt_un10_rx3_char_is_k ( + .I0(plm_v4f_mgt_reg_mgtdiv2_cke_phase1_749), + .I1(plm_v4f_mgt_wrx3_char_is_k[0]), + .I2(plm_v4f_mgt_wrx3_char_is_k[2]), + .O(plm_rx3_char_is_k[1]) + ); + defparam plm_v4f_mgt_un3_rx0_disp_err.INIT = 8'hE4; + LUT3 plm_v4f_mgt_un3_rx0_disp_err ( + .I0(plm_v4f_mgt_reg_mgtdiv2_cke_phase1_749), + .I1(plm_v4f_mgt_wrx0_disp_err[1]), + .I2(plm_v4f_mgt_wrx0_disp_err[3]), + .O(plm_v4f_mgt_rx0_disp_err[0]) + ); + defparam plm_v4f_mgt_un10_rx0_disp_err.INIT = 8'hE4; + LUT3 plm_v4f_mgt_un10_rx0_disp_err ( + .I0(plm_v4f_mgt_reg_mgtdiv2_cke_phase1_749), + .I1(plm_v4f_mgt_wrx0_disp_err[0]), + .I2(plm_v4f_mgt_wrx0_disp_err[2]), + .O(plm_v4f_mgt_rx0_disp_err[1]) + ); + defparam plm_v4f_mgt_un3_rx1_disp_err.INIT = 8'hE4; + LUT3 plm_v4f_mgt_un3_rx1_disp_err ( + .I0(plm_v4f_mgt_reg_mgtdiv2_cke_phase1_749), + .I1(plm_v4f_mgt_wrx1_disp_err[1]), + .I2(plm_v4f_mgt_wrx1_disp_err[3]), + .O(plm_v4f_mgt_rx1_disp_err[0]) + ); + defparam plm_v4f_mgt_un10_rx1_disp_err.INIT = 8'hE4; + LUT3 plm_v4f_mgt_un10_rx1_disp_err ( + .I0(plm_v4f_mgt_reg_mgtdiv2_cke_phase1_749), + .I1(plm_v4f_mgt_wrx1_disp_err[0]), + .I2(plm_v4f_mgt_wrx1_disp_err[2]), + .O(plm_v4f_mgt_rx1_disp_err[1]) + ); + defparam plm_v4f_mgt_un3_rx2_disp_err.INIT = 8'hE4; + LUT3 plm_v4f_mgt_un3_rx2_disp_err ( + .I0(plm_v4f_mgt_reg_mgtdiv2_cke_phase1_749), + .I1(plm_v4f_mgt_wrx2_disp_err[1]), + .I2(plm_v4f_mgt_wrx2_disp_err[3]), + .O(plm_v4f_mgt_rx2_disp_err[0]) + ); + defparam plm_v4f_mgt_un10_rx2_disp_err.INIT = 8'hE4; + LUT3 plm_v4f_mgt_un10_rx2_disp_err ( + .I0(plm_v4f_mgt_reg_mgtdiv2_cke_phase1_749), + .I1(plm_v4f_mgt_wrx2_disp_err[0]), + .I2(plm_v4f_mgt_wrx2_disp_err[2]), + .O(plm_v4f_mgt_rx2_disp_err[1]) + ); + defparam plm_v4f_mgt_un3_rx3_disp_err.INIT = 8'hE4; + LUT3 plm_v4f_mgt_un3_rx3_disp_err ( + .I0(plm_v4f_mgt_reg_mgtdiv2_cke_phase1_749), + .I1(plm_v4f_mgt_wrx3_disp_err[1]), + .I2(plm_v4f_mgt_wrx3_disp_err[3]), + .O(plm_v4f_mgt_rx3_disp_err[0]) + ); + defparam plm_v4f_mgt_un10_rx3_disp_err.INIT = 8'hE4; + LUT3 plm_v4f_mgt_un10_rx3_disp_err ( + .I0(plm_v4f_mgt_reg_mgtdiv2_cke_phase1_749), + .I1(plm_v4f_mgt_wrx3_disp_err[0]), + .I2(plm_v4f_mgt_wrx3_disp_err[2]), + .O(plm_v4f_mgt_rx3_disp_err[1]) + ); + defparam plm_v4f_mgt_un3_rx0_run_disp.INIT = 8'hE4; + LUT3 plm_v4f_mgt_un3_rx0_run_disp ( + .I0(plm_v4f_mgt_reg_mgtdiv2_cke_phase1_749), + .I1(plm_v4f_mgt_wrx0_run_disp[1]), + .I2(plm_v4f_mgt_wrx0_run_disp[3]), + .O(plm_v4f_mgt_rx0_run_disp[0]) + ); + defparam plm_v4f_mgt_un10_rx0_run_disp.INIT = 8'hE4; + LUT3 plm_v4f_mgt_un10_rx0_run_disp ( + .I0(plm_v4f_mgt_reg_mgtdiv2_cke_phase1_749), + .I1(plm_v4f_mgt_wrx0_run_disp[0]), + .I2(plm_v4f_mgt_wrx0_run_disp[2]), + .O(plm_v4f_mgt_rx0_run_disp[1]) + ); + defparam plm_v4f_mgt_un3_rx1_run_disp.INIT = 8'hE4; + LUT3 plm_v4f_mgt_un3_rx1_run_disp ( + .I0(plm_v4f_mgt_reg_mgtdiv2_cke_phase1_749), + .I1(plm_v4f_mgt_wrx1_run_disp[1]), + .I2(plm_v4f_mgt_wrx1_run_disp[3]), + .O(plm_v4f_mgt_rx1_run_disp[0]) + ); + defparam plm_v4f_mgt_un10_rx1_run_disp.INIT = 8'hE4; + LUT3 plm_v4f_mgt_un10_rx1_run_disp ( + .I0(plm_v4f_mgt_reg_mgtdiv2_cke_phase1_749), + .I1(plm_v4f_mgt_wrx1_run_disp[0]), + .I2(plm_v4f_mgt_wrx1_run_disp[2]), + .O(plm_v4f_mgt_rx1_run_disp[1]) + ); + defparam plm_v4f_mgt_un3_rx2_run_disp.INIT = 8'hE4; + LUT3 plm_v4f_mgt_un3_rx2_run_disp ( + .I0(plm_v4f_mgt_reg_mgtdiv2_cke_phase1_749), + .I1(plm_v4f_mgt_wrx2_run_disp[1]), + .I2(plm_v4f_mgt_wrx2_run_disp[3]), + .O(plm_v4f_mgt_rx2_run_disp[0]) + ); + defparam plm_v4f_mgt_un10_rx2_run_disp.INIT = 8'hE4; + LUT3 plm_v4f_mgt_un10_rx2_run_disp ( + .I0(plm_v4f_mgt_reg_mgtdiv2_cke_phase1_749), + .I1(plm_v4f_mgt_wrx2_run_disp[0]), + .I2(plm_v4f_mgt_wrx2_run_disp[2]), + .O(plm_v4f_mgt_rx2_run_disp[1]) + ); + defparam plm_v4f_mgt_un3_rx3_run_disp.INIT = 8'hE4; + LUT3 plm_v4f_mgt_un3_rx3_run_disp ( + .I0(plm_v4f_mgt_reg_mgtdiv2_cke_phase1_749), + .I1(plm_v4f_mgt_wrx3_run_disp[1]), + .I2(plm_v4f_mgt_wrx3_run_disp[3]), + .O(plm_v4f_mgt_rx3_run_disp[0]) + ); + defparam plm_v4f_mgt_un10_rx3_run_disp.INIT = 8'hE4; + LUT3 plm_v4f_mgt_un10_rx3_run_disp ( + .I0(plm_v4f_mgt_reg_mgtdiv2_cke_phase1_749), + .I1(plm_v4f_mgt_wrx3_run_disp[0]), + .I2(plm_v4f_mgt_wrx3_run_disp[2]), + .O(plm_v4f_mgt_rx3_run_disp[1]) + ); + defparam plm_v4f_mgt_un3_rx0_data_0_.INIT = 8'hE4; + LUT3 plm_v4f_mgt_un3_rx0_data_0_ ( + .I0(plm_v4f_mgt_reg_mgtdiv2_cke_phase1_749), + .I1(plm_v4f_mgt_wrx0_data[8]), + .I2(plm_v4f_mgt_wrx0_data[24]), + .O(plm_rx0_data[0]) + ); + defparam plm_v4f_mgt_un3_rx0_data_1_.INIT = 8'hE4; + LUT3 plm_v4f_mgt_un3_rx0_data_1_ ( + .I0(plm_v4f_mgt_reg_mgtdiv2_cke_phase1_749), + .I1(plm_v4f_mgt_wrx0_data[9]), + .I2(plm_v4f_mgt_wrx0_data[25]), + .O(plm_rx0_data[1]) + ); + defparam plm_v4f_mgt_un3_rx0_data_2_.INIT = 8'hE4; + LUT3 plm_v4f_mgt_un3_rx0_data_2_ ( + .I0(plm_v4f_mgt_reg_mgtdiv2_cke_phase1_749), + .I1(plm_v4f_mgt_wrx0_data[10]), + .I2(plm_v4f_mgt_wrx0_data[26]), + .O(plm_rx0_data[2]) + ); + defparam plm_v4f_mgt_un3_rx0_data_3_.INIT = 8'hE4; + LUT3 plm_v4f_mgt_un3_rx0_data_3_ ( + .I0(plm_v4f_mgt_reg_mgtdiv2_cke_phase1_749), + .I1(plm_v4f_mgt_wrx0_data[11]), + .I2(plm_v4f_mgt_wrx0_data[27]), + .O(plm_rx0_data[3]) + ); + defparam plm_v4f_mgt_un3_rx0_data_4_.INIT = 8'hE4; + LUT3 plm_v4f_mgt_un3_rx0_data_4_ ( + .I0(plm_v4f_mgt_reg_mgtdiv2_cke_phase1_749), + .I1(plm_v4f_mgt_wrx0_data[12]), + .I2(plm_v4f_mgt_wrx0_data[28]), + .O(plm_rx0_data[4]) + ); + defparam plm_v4f_mgt_un3_rx0_data_5_.INIT = 8'hE4; + LUT3 plm_v4f_mgt_un3_rx0_data_5_ ( + .I0(plm_v4f_mgt_reg_mgtdiv2_cke_phase1_749), + .I1(plm_v4f_mgt_wrx0_data[13]), + .I2(plm_v4f_mgt_wrx0_data[29]), + .O(plm_rx0_data[5]) + ); + defparam plm_v4f_mgt_un3_rx0_data_6_.INIT = 8'hE4; + LUT3 plm_v4f_mgt_un3_rx0_data_6_ ( + .I0(plm_v4f_mgt_reg_mgtdiv2_cke_phase1_749), + .I1(plm_v4f_mgt_wrx0_data[14]), + .I2(plm_v4f_mgt_wrx0_data[30]), + .O(plm_rx0_data[6]) + ); + defparam plm_v4f_mgt_un3_rx0_data_7_.INIT = 8'hE4; + LUT3 plm_v4f_mgt_un3_rx0_data_7_ ( + .I0(plm_v4f_mgt_reg_mgtdiv2_cke_phase1_749), + .I1(plm_v4f_mgt_wrx0_data[15]), + .I2(plm_v4f_mgt_wrx0_data[31]), + .O(plm_rx0_data[7]) + ); + defparam plm_v4f_mgt_un10_rx0_data_0_.INIT = 8'hE4; + LUT3 plm_v4f_mgt_un10_rx0_data_0_ ( + .I0(plm_v4f_mgt_reg_mgtdiv2_cke_phase1_749), + .I1(plm_v4f_mgt_wrx0_data[0]), + .I2(plm_v4f_mgt_wrx0_data[16]), + .O(plm_rx0_data[8]) + ); + defparam plm_v4f_mgt_un10_rx0_data_1_.INIT = 8'hE4; + LUT3 plm_v4f_mgt_un10_rx0_data_1_ ( + .I0(plm_v4f_mgt_reg_mgtdiv2_cke_phase1_749), + .I1(plm_v4f_mgt_wrx0_data[1]), + .I2(plm_v4f_mgt_wrx0_data[17]), + .O(plm_rx0_data[9]) + ); + defparam plm_v4f_mgt_un10_rx0_data_2_.INIT = 8'hE4; + LUT3 plm_v4f_mgt_un10_rx0_data_2_ ( + .I0(plm_v4f_mgt_reg_mgtdiv2_cke_phase1_749), + .I1(plm_v4f_mgt_wrx0_data[2]), + .I2(plm_v4f_mgt_wrx0_data[18]), + .O(plm_rx0_data[10]) + ); + defparam plm_v4f_mgt_un10_rx0_data_3_.INIT = 8'hE4; + LUT3 plm_v4f_mgt_un10_rx0_data_3_ ( + .I0(plm_v4f_mgt_reg_mgtdiv2_cke_phase1_749), + .I1(plm_v4f_mgt_wrx0_data[3]), + .I2(plm_v4f_mgt_wrx0_data[19]), + .O(plm_rx0_data[11]) + ); + defparam plm_v4f_mgt_un10_rx0_data_4_.INIT = 8'hE4; + LUT3 plm_v4f_mgt_un10_rx0_data_4_ ( + .I0(plm_v4f_mgt_reg_mgtdiv2_cke_phase1_749), + .I1(plm_v4f_mgt_wrx0_data[4]), + .I2(plm_v4f_mgt_wrx0_data[20]), + .O(plm_rx0_data[12]) + ); + defparam plm_v4f_mgt_un10_rx0_data_5_.INIT = 8'hE4; + LUT3 plm_v4f_mgt_un10_rx0_data_5_ ( + .I0(plm_v4f_mgt_reg_mgtdiv2_cke_phase1_749), + .I1(plm_v4f_mgt_wrx0_data[5]), + .I2(plm_v4f_mgt_wrx0_data[21]), + .O(plm_rx0_data[13]) + ); + defparam plm_v4f_mgt_un10_rx0_data_6_.INIT = 8'hE4; + LUT3 plm_v4f_mgt_un10_rx0_data_6_ ( + .I0(plm_v4f_mgt_reg_mgtdiv2_cke_phase1_749), + .I1(plm_v4f_mgt_wrx0_data[6]), + .I2(plm_v4f_mgt_wrx0_data[22]), + .O(plm_rx0_data[14]) + ); + defparam plm_v4f_mgt_un10_rx0_data_7_.INIT = 8'hE4; + LUT3 plm_v4f_mgt_un10_rx0_data_7_ ( + .I0(plm_v4f_mgt_reg_mgtdiv2_cke_phase1_749), + .I1(plm_v4f_mgt_wrx0_data[7]), + .I2(plm_v4f_mgt_wrx0_data[23]), + .O(plm_rx0_data[15]) + ); + defparam plm_v4f_mgt_un3_rx1_data_0_.INIT = 8'hE4; + LUT3 plm_v4f_mgt_un3_rx1_data_0_ ( + .I0(plm_v4f_mgt_reg_mgtdiv2_cke_phase1_749), + .I1(plm_v4f_mgt_wrx1_data[8]), + .I2(plm_v4f_mgt_wrx1_data[24]), + .O(plm_rx1_data[0]) + ); + defparam plm_v4f_mgt_un3_rx1_data_1_.INIT = 8'hE4; + LUT3 plm_v4f_mgt_un3_rx1_data_1_ ( + .I0(plm_v4f_mgt_reg_mgtdiv2_cke_phase1_749), + .I1(plm_v4f_mgt_wrx1_data[9]), + .I2(plm_v4f_mgt_wrx1_data[25]), + .O(plm_rx1_data[1]) + ); + defparam plm_v4f_mgt_un3_rx1_data_2_.INIT = 8'hE4; + LUT3 plm_v4f_mgt_un3_rx1_data_2_ ( + .I0(plm_v4f_mgt_reg_mgtdiv2_cke_phase1_749), + .I1(plm_v4f_mgt_wrx1_data[10]), + .I2(plm_v4f_mgt_wrx1_data[26]), + .O(plm_rx1_data[2]) + ); + defparam plm_v4f_mgt_un3_rx1_data_3_.INIT = 8'hE4; + LUT3 plm_v4f_mgt_un3_rx1_data_3_ ( + .I0(plm_v4f_mgt_reg_mgtdiv2_cke_phase1_749), + .I1(plm_v4f_mgt_wrx1_data[11]), + .I2(plm_v4f_mgt_wrx1_data[27]), + .O(plm_rx1_data[3]) + ); + defparam plm_v4f_mgt_un3_rx1_data_4_.INIT = 8'hE4; + LUT3 plm_v4f_mgt_un3_rx1_data_4_ ( + .I0(plm_v4f_mgt_reg_mgtdiv2_cke_phase1_749), + .I1(plm_v4f_mgt_wrx1_data[12]), + .I2(plm_v4f_mgt_wrx1_data[28]), + .O(plm_rx1_data[4]) + ); + defparam plm_v4f_mgt_un3_rx1_data_5_.INIT = 8'hE4; + LUT3 plm_v4f_mgt_un3_rx1_data_5_ ( + .I0(plm_v4f_mgt_reg_mgtdiv2_cke_phase1_749), + .I1(plm_v4f_mgt_wrx1_data[13]), + .I2(plm_v4f_mgt_wrx1_data[29]), + .O(plm_rx1_data[5]) + ); + defparam plm_v4f_mgt_un3_rx1_data_6_.INIT = 8'hE4; + LUT3 plm_v4f_mgt_un3_rx1_data_6_ ( + .I0(plm_v4f_mgt_reg_mgtdiv2_cke_phase1_749), + .I1(plm_v4f_mgt_wrx1_data[14]), + .I2(plm_v4f_mgt_wrx1_data[30]), + .O(plm_rx1_data[6]) + ); + defparam plm_v4f_mgt_un3_rx1_data_7_.INIT = 8'hE4; + LUT3 plm_v4f_mgt_un3_rx1_data_7_ ( + .I0(plm_v4f_mgt_reg_mgtdiv2_cke_phase1_749), + .I1(plm_v4f_mgt_wrx1_data[15]), + .I2(plm_v4f_mgt_wrx1_data[31]), + .O(plm_rx1_data[7]) + ); + defparam plm_v4f_mgt_un10_rx1_data_0_.INIT = 8'hE4; + LUT3 plm_v4f_mgt_un10_rx1_data_0_ ( + .I0(plm_v4f_mgt_reg_mgtdiv2_cke_phase1_749), + .I1(plm_v4f_mgt_wrx1_data[0]), + .I2(plm_v4f_mgt_wrx1_data[16]), + .O(plm_rx1_data[8]) + ); + defparam plm_v4f_mgt_un10_rx1_data_1_.INIT = 8'hE4; + LUT3 plm_v4f_mgt_un10_rx1_data_1_ ( + .I0(plm_v4f_mgt_reg_mgtdiv2_cke_phase1_749), + .I1(plm_v4f_mgt_wrx1_data[1]), + .I2(plm_v4f_mgt_wrx1_data[17]), + .O(plm_rx1_data[9]) + ); + defparam plm_v4f_mgt_un10_rx1_data_2_.INIT = 8'hE4; + LUT3 plm_v4f_mgt_un10_rx1_data_2_ ( + .I0(plm_v4f_mgt_reg_mgtdiv2_cke_phase1_749), + .I1(plm_v4f_mgt_wrx1_data[2]), + .I2(plm_v4f_mgt_wrx1_data[18]), + .O(plm_rx1_data[10]) + ); + defparam plm_v4f_mgt_un10_rx1_data_3_.INIT = 8'hE4; + LUT3 plm_v4f_mgt_un10_rx1_data_3_ ( + .I0(plm_v4f_mgt_reg_mgtdiv2_cke_phase1_749), + .I1(plm_v4f_mgt_wrx1_data[3]), + .I2(plm_v4f_mgt_wrx1_data[19]), + .O(plm_rx1_data[11]) + ); + defparam plm_v4f_mgt_un10_rx1_data_4_.INIT = 8'hE4; + LUT3 plm_v4f_mgt_un10_rx1_data_4_ ( + .I0(plm_v4f_mgt_reg_mgtdiv2_cke_phase1_749), + .I1(plm_v4f_mgt_wrx1_data[4]), + .I2(plm_v4f_mgt_wrx1_data[20]), + .O(plm_rx1_data[12]) + ); + defparam plm_v4f_mgt_un10_rx1_data_5_.INIT = 8'hE4; + LUT3 plm_v4f_mgt_un10_rx1_data_5_ ( + .I0(plm_v4f_mgt_reg_mgtdiv2_cke_phase1_749), + .I1(plm_v4f_mgt_wrx1_data[5]), + .I2(plm_v4f_mgt_wrx1_data[21]), + .O(plm_rx1_data[13]) + ); + defparam plm_v4f_mgt_un10_rx1_data_6_.INIT = 8'hE4; + LUT3 plm_v4f_mgt_un10_rx1_data_6_ ( + .I0(plm_v4f_mgt_reg_mgtdiv2_cke_phase1_749), + .I1(plm_v4f_mgt_wrx1_data[6]), + .I2(plm_v4f_mgt_wrx1_data[22]), + .O(plm_rx1_data[14]) + ); + defparam plm_v4f_mgt_un10_rx1_data_7_.INIT = 8'hE4; + LUT3 plm_v4f_mgt_un10_rx1_data_7_ ( + .I0(plm_v4f_mgt_reg_mgtdiv2_cke_phase1_749), + .I1(plm_v4f_mgt_wrx1_data[7]), + .I2(plm_v4f_mgt_wrx1_data[23]), + .O(plm_rx1_data[15]) + ); + defparam plm_v4f_mgt_un3_rx2_data_0_.INIT = 8'hE4; + LUT3 plm_v4f_mgt_un3_rx2_data_0_ ( + .I0(plm_v4f_mgt_reg_mgtdiv2_cke_phase1_749), + .I1(plm_v4f_mgt_wrx2_data[8]), + .I2(plm_v4f_mgt_wrx2_data[24]), + .O(plm_rx2_data[0]) + ); + defparam plm_v4f_mgt_un3_rx2_data_1_.INIT = 8'hE4; + LUT3 plm_v4f_mgt_un3_rx2_data_1_ ( + .I0(plm_v4f_mgt_reg_mgtdiv2_cke_phase1_749), + .I1(plm_v4f_mgt_wrx2_data[9]), + .I2(plm_v4f_mgt_wrx2_data[25]), + .O(plm_rx2_data[1]) + ); + defparam plm_v4f_mgt_un3_rx2_data_2_.INIT = 8'hE4; + LUT3 plm_v4f_mgt_un3_rx2_data_2_ ( + .I0(plm_v4f_mgt_reg_mgtdiv2_cke_phase1_749), + .I1(plm_v4f_mgt_wrx2_data[10]), + .I2(plm_v4f_mgt_wrx2_data[26]), + .O(plm_rx2_data[2]) + ); + defparam plm_v4f_mgt_un3_rx2_data_3_.INIT = 8'hE4; + LUT3 plm_v4f_mgt_un3_rx2_data_3_ ( + .I0(plm_v4f_mgt_reg_mgtdiv2_cke_phase1_749), + .I1(plm_v4f_mgt_wrx2_data[11]), + .I2(plm_v4f_mgt_wrx2_data[27]), + .O(plm_rx2_data[3]) + ); + defparam plm_v4f_mgt_un3_rx2_data_4_.INIT = 8'hE4; + LUT3 plm_v4f_mgt_un3_rx2_data_4_ ( + .I0(plm_v4f_mgt_reg_mgtdiv2_cke_phase1_749), + .I1(plm_v4f_mgt_wrx2_data[12]), + .I2(plm_v4f_mgt_wrx2_data[28]), + .O(plm_rx2_data[4]) + ); + defparam plm_v4f_mgt_un3_rx2_data_5_.INIT = 8'hE4; + LUT3 plm_v4f_mgt_un3_rx2_data_5_ ( + .I0(plm_v4f_mgt_reg_mgtdiv2_cke_phase1_749), + .I1(plm_v4f_mgt_wrx2_data[13]), + .I2(plm_v4f_mgt_wrx2_data[29]), + .O(plm_rx2_data[5]) + ); + defparam plm_v4f_mgt_un3_rx2_data_6_.INIT = 8'hE4; + LUT3 plm_v4f_mgt_un3_rx2_data_6_ ( + .I0(plm_v4f_mgt_reg_mgtdiv2_cke_phase1_749), + .I1(plm_v4f_mgt_wrx2_data[14]), + .I2(plm_v4f_mgt_wrx2_data[30]), + .O(plm_rx2_data[6]) + ); + defparam plm_v4f_mgt_un3_rx2_data_7_.INIT = 8'hE4; + LUT3 plm_v4f_mgt_un3_rx2_data_7_ ( + .I0(plm_v4f_mgt_reg_mgtdiv2_cke_phase1_749), + .I1(plm_v4f_mgt_wrx2_data[15]), + .I2(plm_v4f_mgt_wrx2_data[31]), + .O(plm_rx2_data[7]) + ); + defparam plm_v4f_mgt_un10_rx2_data_0_.INIT = 8'hE4; + LUT3 plm_v4f_mgt_un10_rx2_data_0_ ( + .I0(plm_v4f_mgt_reg_mgtdiv2_cke_phase1_749), + .I1(plm_v4f_mgt_wrx2_data[0]), + .I2(plm_v4f_mgt_wrx2_data[16]), + .O(plm_rx2_data[8]) + ); + defparam plm_v4f_mgt_un10_rx2_data_1_.INIT = 8'hE4; + LUT3 plm_v4f_mgt_un10_rx2_data_1_ ( + .I0(plm_v4f_mgt_reg_mgtdiv2_cke_phase1_749), + .I1(plm_v4f_mgt_wrx2_data[1]), + .I2(plm_v4f_mgt_wrx2_data[17]), + .O(plm_rx2_data[9]) + ); + defparam plm_v4f_mgt_un10_rx2_data_2_.INIT = 8'hE4; + LUT3 plm_v4f_mgt_un10_rx2_data_2_ ( + .I0(plm_v4f_mgt_reg_mgtdiv2_cke_phase1_749), + .I1(plm_v4f_mgt_wrx2_data[2]), + .I2(plm_v4f_mgt_wrx2_data[18]), + .O(plm_rx2_data[10]) + ); + defparam plm_v4f_mgt_un10_rx2_data_3_.INIT = 8'hE4; + LUT3 plm_v4f_mgt_un10_rx2_data_3_ ( + .I0(plm_v4f_mgt_reg_mgtdiv2_cke_phase1_749), + .I1(plm_v4f_mgt_wrx2_data[3]), + .I2(plm_v4f_mgt_wrx2_data[19]), + .O(plm_rx2_data[11]) + ); + defparam plm_v4f_mgt_un10_rx2_data_4_.INIT = 8'hE4; + LUT3 plm_v4f_mgt_un10_rx2_data_4_ ( + .I0(plm_v4f_mgt_reg_mgtdiv2_cke_phase1_749), + .I1(plm_v4f_mgt_wrx2_data[4]), + .I2(plm_v4f_mgt_wrx2_data[20]), + .O(plm_rx2_data[12]) + ); + defparam plm_v4f_mgt_un10_rx2_data_5_.INIT = 8'hE4; + LUT3 plm_v4f_mgt_un10_rx2_data_5_ ( + .I0(plm_v4f_mgt_reg_mgtdiv2_cke_phase1_749), + .I1(plm_v4f_mgt_wrx2_data[5]), + .I2(plm_v4f_mgt_wrx2_data[21]), + .O(plm_rx2_data[13]) + ); + defparam plm_v4f_mgt_un10_rx2_data_6_.INIT = 8'hE4; + LUT3 plm_v4f_mgt_un10_rx2_data_6_ ( + .I0(plm_v4f_mgt_reg_mgtdiv2_cke_phase1_749), + .I1(plm_v4f_mgt_wrx2_data[6]), + .I2(plm_v4f_mgt_wrx2_data[22]), + .O(plm_rx2_data[14]) + ); + defparam plm_v4f_mgt_un10_rx2_data_7_.INIT = 8'hE4; + LUT3 plm_v4f_mgt_un10_rx2_data_7_ ( + .I0(plm_v4f_mgt_reg_mgtdiv2_cke_phase1_749), + .I1(plm_v4f_mgt_wrx2_data[7]), + .I2(plm_v4f_mgt_wrx2_data[23]), + .O(plm_rx2_data[15]) + ); + defparam plm_v4f_mgt_un3_rx3_data_0_.INIT = 8'hE4; + LUT3 plm_v4f_mgt_un3_rx3_data_0_ ( + .I0(plm_v4f_mgt_reg_mgtdiv2_cke_phase1_749), + .I1(plm_v4f_mgt_wrx3_data[8]), + .I2(plm_v4f_mgt_wrx3_data[24]), + .O(plm_rx3_data[0]) + ); + defparam plm_v4f_mgt_un3_rx3_data_1_.INIT = 8'hE4; + LUT3 plm_v4f_mgt_un3_rx3_data_1_ ( + .I0(plm_v4f_mgt_reg_mgtdiv2_cke_phase1_749), + .I1(plm_v4f_mgt_wrx3_data[9]), + .I2(plm_v4f_mgt_wrx3_data[25]), + .O(plm_rx3_data[1]) + ); + defparam plm_v4f_mgt_un3_rx3_data_2_.INIT = 8'hE4; + LUT3 plm_v4f_mgt_un3_rx3_data_2_ ( + .I0(plm_v4f_mgt_reg_mgtdiv2_cke_phase1_749), + .I1(plm_v4f_mgt_wrx3_data[10]), + .I2(plm_v4f_mgt_wrx3_data[26]), + .O(plm_rx3_data[2]) + ); + defparam plm_v4f_mgt_un3_rx3_data_3_.INIT = 8'hE4; + LUT3 plm_v4f_mgt_un3_rx3_data_3_ ( + .I0(plm_v4f_mgt_reg_mgtdiv2_cke_phase1_749), + .I1(plm_v4f_mgt_wrx3_data[11]), + .I2(plm_v4f_mgt_wrx3_data[27]), + .O(plm_rx3_data[3]) + ); + defparam plm_v4f_mgt_un3_rx3_data_4_.INIT = 8'hE4; + LUT3 plm_v4f_mgt_un3_rx3_data_4_ ( + .I0(plm_v4f_mgt_reg_mgtdiv2_cke_phase1_749), + .I1(plm_v4f_mgt_wrx3_data[12]), + .I2(plm_v4f_mgt_wrx3_data[28]), + .O(plm_rx3_data[4]) + ); + defparam plm_v4f_mgt_un3_rx3_data_5_.INIT = 8'hE4; + LUT3 plm_v4f_mgt_un3_rx3_data_5_ ( + .I0(plm_v4f_mgt_reg_mgtdiv2_cke_phase1_749), + .I1(plm_v4f_mgt_wrx3_data[13]), + .I2(plm_v4f_mgt_wrx3_data[29]), + .O(plm_rx3_data[5]) + ); + defparam plm_v4f_mgt_un3_rx3_data_6_.INIT = 8'hE4; + LUT3 plm_v4f_mgt_un3_rx3_data_6_ ( + .I0(plm_v4f_mgt_reg_mgtdiv2_cke_phase1_749), + .I1(plm_v4f_mgt_wrx3_data[14]), + .I2(plm_v4f_mgt_wrx3_data[30]), + .O(plm_rx3_data[6]) + ); + defparam plm_v4f_mgt_un3_rx3_data_7_.INIT = 8'hE4; + LUT3 plm_v4f_mgt_un3_rx3_data_7_ ( + .I0(plm_v4f_mgt_reg_mgtdiv2_cke_phase1_749), + .I1(plm_v4f_mgt_wrx3_data[15]), + .I2(plm_v4f_mgt_wrx3_data[31]), + .O(plm_rx3_data[7]) + ); + defparam plm_v4f_mgt_un10_rx3_data_0_.INIT = 8'hE4; + LUT3 plm_v4f_mgt_un10_rx3_data_0_ ( + .I0(plm_v4f_mgt_reg_mgtdiv2_cke_phase1_749), + .I1(plm_v4f_mgt_wrx3_data[0]), + .I2(plm_v4f_mgt_wrx3_data[16]), + .O(plm_rx3_data[8]) + ); + defparam plm_v4f_mgt_un10_rx3_data_1_.INIT = 8'hE4; + LUT3 plm_v4f_mgt_un10_rx3_data_1_ ( + .I0(plm_v4f_mgt_reg_mgtdiv2_cke_phase1_749), + .I1(plm_v4f_mgt_wrx3_data[1]), + .I2(plm_v4f_mgt_wrx3_data[17]), + .O(plm_rx3_data[9]) + ); + defparam plm_v4f_mgt_un10_rx3_data_2_.INIT = 8'hE4; + LUT3 plm_v4f_mgt_un10_rx3_data_2_ ( + .I0(plm_v4f_mgt_reg_mgtdiv2_cke_phase1_749), + .I1(plm_v4f_mgt_wrx3_data[2]), + .I2(plm_v4f_mgt_wrx3_data[18]), + .O(plm_rx3_data[10]) + ); + defparam plm_v4f_mgt_un10_rx3_data_3_.INIT = 8'hE4; + LUT3 plm_v4f_mgt_un10_rx3_data_3_ ( + .I0(plm_v4f_mgt_reg_mgtdiv2_cke_phase1_749), + .I1(plm_v4f_mgt_wrx3_data[3]), + .I2(plm_v4f_mgt_wrx3_data[19]), + .O(plm_rx3_data[11]) + ); + defparam plm_v4f_mgt_un10_rx3_data_4_.INIT = 8'hE4; + LUT3 plm_v4f_mgt_un10_rx3_data_4_ ( + .I0(plm_v4f_mgt_reg_mgtdiv2_cke_phase1_749), + .I1(plm_v4f_mgt_wrx3_data[4]), + .I2(plm_v4f_mgt_wrx3_data[20]), + .O(plm_rx3_data[12]) + ); + defparam plm_v4f_mgt_un10_rx3_data_5_.INIT = 8'hE4; + LUT3 plm_v4f_mgt_un10_rx3_data_5_ ( + .I0(plm_v4f_mgt_reg_mgtdiv2_cke_phase1_749), + .I1(plm_v4f_mgt_wrx3_data[5]), + .I2(plm_v4f_mgt_wrx3_data[21]), + .O(plm_rx3_data[13]) + ); + defparam plm_v4f_mgt_un10_rx3_data_6_.INIT = 8'hE4; + LUT3 plm_v4f_mgt_un10_rx3_data_6_ ( + .I0(plm_v4f_mgt_reg_mgtdiv2_cke_phase1_749), + .I1(plm_v4f_mgt_wrx3_data[6]), + .I2(plm_v4f_mgt_wrx3_data[22]), + .O(plm_rx3_data[14]) + ); + defparam plm_v4f_mgt_un10_rx3_data_7_.INIT = 8'hE4; + LUT3 plm_v4f_mgt_un10_rx3_data_7_ ( + .I0(plm_v4f_mgt_reg_mgtdiv2_cke_phase1_749), + .I1(plm_v4f_mgt_wrx3_data[7]), + .I2(plm_v4f_mgt_wrx3_data[23]), + .O(plm_rx3_data[15]) + ); + defparam plm_v4f_mgt_for_v1_4_N_438_i.INIT = 4'hD; + LUT2 plm_v4f_mgt_for_v1_4_N_438_i ( + .I0(plm_v4f_mgt_dcm_lock), + .I1(cfg_cfg_6102[511]), + .O(plm_v4f_mgt_N_438_i) + ); + defparam plm_v4f_mgt_reset_delay_reg_tx_sync_5_i_0_o2.INIT = 4'h4; + LUT2 plm_v4f_mgt_reset_delay_reg_tx_sync_5_i_0_o2 ( + .I0(plm_v4f_mgt_reg_rst_cnt[10]), + .I1(plm_v4f_mgt_reset_delay_reg_tx_pcs_init_3_1), + .O(plm_v4f_mgt_N_866_i) + ); + defparam plm_v4f_mgt_reset_delay_reg_tx_pcs_init_5_i_o2_0_a3_0_0.INIT = 8'h80; + LUT3 plm_v4f_mgt_reset_delay_reg_tx_pcs_init_5_i_o2_0_a3_0_0 ( + .I0(plm_v4f_mgt_reg_rst_cnt[0]), + .I1(plm_v4f_mgt_reg_rst_cnt[1]), + .I2(plm_v4f_mgt_reg_rst_cnt[2]), + .O(plm_v4f_mgt_reset_delay_reg_tx_sync_5_i_0_a2_1_0) + ); + defparam plm_v4f_mgt_dcm_delay_reg_dcm9.INIT = 16'h8000; + LUT4 plm_v4f_mgt_dcm_delay_reg_dcm9 ( + .I0(plm_v4f_mgt_reg_dcm_cnt[0]), + .I1(plm_v4f_mgt_reg_dcm_cnt[1]), + .I2(plm_v4f_mgt_reg_dcm_cnt[2]), + .I3(plm_v4f_mgt_reg_dcm_cnt[3]), + .O(plm_v4f_mgt_dcm_delay_reg_dcm9_765) + ); + defparam plm_v4f_mgt_pma_delay_reg_pma9.INIT = 16'h8000; + LUT4 plm_v4f_mgt_pma_delay_reg_pma9 ( + .I0(plm_v4f_mgt_reg_pma_cnt[0]), + .I1(plm_v4f_mgt_reg_pma_cnt[1]), + .I2(plm_v4f_mgt_reg_pma_cnt[2]), + .I3(plm_v4f_mgt_reg_pma_cnt[3]), + .O(plm_v4f_mgt_pma_delay_reg_pma9_767) + ); + defparam plm_v4f_mgt_bond_success.INIT = 16'h8000; + LUT4 plm_v4f_mgt_bond_success ( + .I0(plm_v4f_mgt_rx0_rxstatus[5]), + .I1(plm_v4f_mgt_rx1_rxstatus[5]), + .I2(plm_v4f_mgt_rx2_rxstatus[5]), + .I3(plm_v4f_mgt_rx3_rxstatus[5]), + .O(plm_v4f_mgt_bond_success_713) + ); + defparam plm_v4f_mgt_un1_reg_plm_rst_n_2_0_0_o3_0_.INIT = 16'h0001; + LUT4 plm_v4f_mgt_un1_reg_plm_rst_n_2_0_0_o3_0_ ( + .I0(plm_v4f_mgt_reg_rst_cnt[5]), + .I1(plm_v4f_mgt_reg_rst_cnt[6]), + .I2(plm_v4f_mgt_reg_rst_cnt[7]), + .I3(plm_v4f_mgt_reg_rst_cnt[8]), + .O(plm_v4f_mgt_N_860_i) + ); + defparam plm_v4f_mgt_bondage_reg_bond_state_8_0_a3_1_.INIT = 4'h8; + LUT2_L plm_v4f_mgt_bondage_reg_bond_state_8_0_a3_1_ ( + .I0(plm_v4f_mgt_bond_success_713), + .I1(plm_v4f_mgt_reg_bond_state[0]), + .LO(plm_v4f_mgt_reg_bond_state_8_0_a3[1]) + ); + defparam plm_v4f_mgt_reset_delay_reg_tx_sync_5_i_0_a2_1_1.INIT = 16'h8000; + LUT4 plm_v4f_mgt_reset_delay_reg_tx_sync_5_i_0_a2_1_1 ( + .I0(plm_v4f_mgt_N_871_i), + .I1(plm_v4f_mgt_reg_rst_cnt[5]), + .I2(plm_v4f_mgt_reg_rst_cnt[6]), + .I3(plm_v4f_mgt_reg_rst_cnt[7]), + .O(plm_v4f_mgt_N_882_1) + ); + defparam plm_v4f_mgt_reset_delay_reg_tx_sync_5_i_0_o4.INIT = 8'h02; + LUT3 plm_v4f_mgt_reset_delay_reg_tx_sync_5_i_0_o4 ( + .I0(plm_v4f_mgt_N_860_i), + .I1(plm_v4f_mgt_reg_rst_cnt[13]), + .I2(plm_v4f_mgt_reg_rst_cnt[14]), + .O(plm_v4f_mgt_N_863_i) + ); + defparam plm_v4f_mgt_un1_reg_plm_rst_n_2_0_0_a2_2_1_0_.INIT = 16'h0010; + LUT4 plm_v4f_mgt_un1_reg_plm_rst_n_2_0_0_a2_2_1_0_ ( + .I0(plm_v4f_mgt_reg_rst_cnt[4]), + .I1(plm_v4f_mgt_reg_rst_cnt[9]), + .I2(plm_v4f_mgt_reset_delay_reg_tx_pcs_init_3_1), + .I3(cfg_cfg_6102[507]), + .O(plm_v4f_mgt_un1_reg_plm_rst_n_2_0_0_a2_2_1[0]) + ); + defparam plm_v4f_mgt_reset_delay_reg_tx_sync_5_i_0_0.INIT = 16'h22F0; + LUT4_L plm_v4f_mgt_reset_delay_reg_tx_sync_5_i_0_0 ( + .I0(plm_v4f_mgt_reg_tx_sync_5_i_0_o4_0), + .I1(plm_v4f_mgt_reg_rst_cnt[4]), + .I2(plm_v4f_mgt_reg_rst_cnt[8]), + .I3(cfg_cfg_6102[507]), + .LO(plm_v4f_mgt_reset_delay_reg_tx_sync_5_i_0_0_714) + ); + defparam plm_v4f_mgt_reset_delay_reg_tx_pcs_init_5_i_o2_0_o2_0.INIT = 16'hA022; + LUT4_L plm_v4f_mgt_reset_delay_reg_tx_pcs_init_5_i_o2_0_o2_0 ( + .I0(plm_v4f_mgt_N_866_i), + .I1(plm_v4f_mgt_reg_rst_cnt[4]), + .I2(plm_v4f_mgt_reg_rst_cnt[8]), + .I3(plm_v4f_mgt_reg_rst_cnt[9]), + .LO(plm_v4f_mgt_reset_delay_reg_tx_pcs_init_5_i_o2_0_o2_0_715) + ); + defparam plm_v4f_mgt_bondage_reg_bond_state_8_i_m3_0_.INIT = 8'hC5; + LUT3_L plm_v4f_mgt_bondage_reg_bond_state_8_i_m3_0_ ( + .I0(plm_N_11062_i), + .I1(plm_v4f_mgt_bond_success_713), + .I2(plm_v4f_mgt_reg_bond_state[0]), + .LO(plm_v4f_mgt_reg_bond_state_8_i_m3[0]) + ); + defparam plm_v4f_mgt_N_891_i.INIT = 16'hFD75; + LUT4 plm_v4f_mgt_N_891_i ( + .I0(plm_v4f_mgt_pma_rxlock3), + .I1(plm_v4f_mgt_reg_mgtdiv2_cke_phase1_749), + .I2(plm_v4f_mgt_wrx3_ntable[1]), + .I3(plm_v4f_mgt_wrx3_ntable[3]), + .O(plm_rx3_not_in_table[0]) + ); + defparam plm_v4f_mgt_N_890_i.INIT = 16'hFD75; + LUT4 plm_v4f_mgt_N_890_i ( + .I0(plm_v4f_mgt_pma_rxlock3), + .I1(plm_v4f_mgt_reg_mgtdiv2_cke_phase1_749), + .I2(plm_v4f_mgt_wrx3_ntable[0]), + .I3(plm_v4f_mgt_wrx3_ntable[2]), + .O(plm_rx3_not_in_table[1]) + ); + defparam plm_v4f_mgt_N_893_i.INIT = 16'hFD75; + LUT4 plm_v4f_mgt_N_893_i ( + .I0(plm_v4f_mgt_pma_rxlock2), + .I1(plm_v4f_mgt_reg_mgtdiv2_cke_phase1_749), + .I2(plm_v4f_mgt_wrx2_ntable[1]), + .I3(plm_v4f_mgt_wrx2_ntable[3]), + .O(plm_rx2_not_in_table[0]) + ); + defparam plm_v4f_mgt_N_892_i.INIT = 16'hFD75; + LUT4 plm_v4f_mgt_N_892_i ( + .I0(plm_v4f_mgt_pma_rxlock2), + .I1(plm_v4f_mgt_reg_mgtdiv2_cke_phase1_749), + .I2(plm_v4f_mgt_wrx2_ntable[0]), + .I3(plm_v4f_mgt_wrx2_ntable[2]), + .O(plm_rx2_not_in_table[1]) + ); + defparam plm_v4f_mgt_N_887_i.INIT = 16'hFD75; + LUT4 plm_v4f_mgt_N_887_i ( + .I0(plm_v4f_mgt_pma_rxlock1), + .I1(plm_v4f_mgt_reg_mgtdiv2_cke_phase1_749), + .I2(plm_v4f_mgt_wrx1_ntable[1]), + .I3(plm_v4f_mgt_wrx1_ntable[3]), + .O(plm_rx1_not_in_table[0]) + ); + defparam plm_v4f_mgt_N_894_i.INIT = 16'hFD75; + LUT4 plm_v4f_mgt_N_894_i ( + .I0(plm_v4f_mgt_pma_rxlock1), + .I1(plm_v4f_mgt_reg_mgtdiv2_cke_phase1_749), + .I2(plm_v4f_mgt_wrx1_ntable[0]), + .I3(plm_v4f_mgt_wrx1_ntable[2]), + .O(plm_rx1_not_in_table[1]) + ); + defparam plm_v4f_mgt_N_889_i.INIT = 16'hFD75; + LUT4 plm_v4f_mgt_N_889_i ( + .I0(plm_v4f_mgt_pma_rxlock0), + .I1(plm_v4f_mgt_reg_mgtdiv2_cke_phase1_749), + .I2(plm_v4f_mgt_wrx0_ntable[1]), + .I3(plm_v4f_mgt_wrx0_ntable[3]), + .O(plm_rx0_not_in_table[0]) + ); + defparam plm_v4f_mgt_N_888_i.INIT = 16'hFD75; + LUT4 plm_v4f_mgt_N_888_i ( + .I0(plm_v4f_mgt_pma_rxlock0), + .I1(plm_v4f_mgt_reg_mgtdiv2_cke_phase1_749), + .I2(plm_v4f_mgt_wrx0_ntable[0]), + .I3(plm_v4f_mgt_wrx0_ntable[2]), + .O(plm_rx0_not_in_table[1]) + ); + defparam plm_v4f_mgt_reset_delay_reg_tx_sync_5_i_0_1.INIT = 16'h30A0; + LUT4 plm_v4f_mgt_reset_delay_reg_tx_sync_5_i_0_1 ( + .I0(plm_v4f_mgt_un1_reg_plm_rst_n_2_0_0_o4[0]), + .I1(plm_v4f_mgt_reg_rst_cnt[3]), + .I2(plm_v4f_mgt_reset_delay_reg_tx_sync_5_i_0_0_714), + .I3(cfg_cfg_6102[507]), + .O(plm_v4f_mgt_reset_delay_reg_tx_sync_5_i_0_1_720) + ); + defparam plm_v4f_mgt_un1_reg_plm_rst_n_2_0_0_0_0_.INIT = 8'hF4; + LUT3 plm_v4f_mgt_un1_reg_plm_rst_n_2_0_0_0_0_ ( + .I0(plm_v4f_mgt_N_866_i), + .I1(plm_v4f_mgt_un1_reg_plm_rst_n_2_0_0_o4[0]), + .I2(cfg_cfg_6102[507]), + .O(plm_v4f_mgt_un1_reg_plm_rst_n_2_0_0_0[0]) + ); + defparam plm_v4f_mgt_reset_delay_reg_tx_pcs_init_5_i_o2_0_o2_1.INIT = 16'hAC00; + LUT4_L plm_v4f_mgt_reset_delay_reg_tx_pcs_init_5_i_o2_0_o2_1 ( + .I0(plm_v4f_mgt_un1_reg_plm_rst_n_2_0_0_o4[0]), + .I1(plm_v4f_mgt_reg_rst_cnt[3]), + .I2(plm_v4f_mgt_reg_rst_cnt[9]), + .I3(plm_v4f_mgt_reset_delay_reg_tx_pcs_init_5_i_o2_0_o2_0_715), + .LO(plm_v4f_mgt_reset_delay_reg_tx_pcs_init_5_i_o2_0_o2_1_717) + ); + defparam plm_v4f_mgt_sys_init_n_i.INIT = 16'h7FFF; + LUT4 plm_v4f_mgt_sys_init_n_i ( + .I0(plm_v4f_mgt_dcm_lock), + .I1(plm_v4f_mgt_pma_txlock2), + .I2(plm_v4f_mgt_pma_txlock3), + .I3(plm_v4f_mgt_sys_init_n_0_a2_0_716), + .O(plm_v4f_mgt_sys_init_n_i_757) + ); + defparam plm_v4f_mgt_un1_reg_plm_rst_n_2_0_0_a2_0_.INIT = 16'h0008; + LUT4_L plm_v4f_mgt_un1_reg_plm_rst_n_2_0_0_a2_0_ ( + .I0(plm_v4f_mgt_N_863_i), + .I1(plm_v4f_mgt_N_866_i), + .I2(plm_v4f_mgt_N_871_i), + .I3(plm_v4f_mgt_reg_rst_cnt[9]), + .LO(plm_v4f_mgt_un1_reg_plm_rst_n_2_0_0_a2[0]) + ); + defparam plm_v4f_mgt_reset_delay_reg_tx_sync_5_i_0_3.INIT = 16'h2A3F; + LUT4_L plm_v4f_mgt_reset_delay_reg_tx_sync_5_i_0_3 ( + .I0(plm_v4f_mgt_N_863_i), + .I1(plm_v4f_mgt_N_882_1), + .I2(plm_v4f_mgt_reset_delay_reg_tx_sync_5_i_0_a2_1_0), + .I3(cfg_cfg_6102[507]), + .LO(plm_v4f_mgt_reset_delay_reg_tx_sync_5_i_0_3_719) + ); + defparam plm_v4f_mgt_un1_reg_plm_rst_n_2_0_0_0_.INIT = 16'h1030; + LUT4 plm_v4f_mgt_un1_reg_plm_rst_n_2_0_0_0_ ( + .I0(plm_v4f_mgt_N_860_i), + .I1(plm_v4f_mgt_un1_reg_plm_rst_n_2_0_0_a2[0]), + .I2(plm_v4f_mgt_un1_reg_plm_rst_n_2_0_0_0[0]), + .I3(plm_v4f_mgt_un1_reg_plm_rst_n_2_0_0_a2_2_1[0]), + .O(plm_v4f_mgt_un1_reg_plm_rst_n_2_i[0]) + ); + defparam plm_v4f_mgt_reset_delay_reg_tx_pcs_init_5_i_o2_0_o2_2.INIT = 16'h40F0; + LUT4_L plm_v4f_mgt_reset_delay_reg_tx_pcs_init_5_i_o2_0_o2_2 ( + .I0(plm_v4f_mgt_N_882_1), + .I1(plm_v4f_mgt_reg_rst_cnt[9]), + .I2(plm_v4f_mgt_reset_delay_reg_tx_pcs_init_5_i_o2_0_o2_1_717), + .I3(plm_v4f_mgt_reset_delay_reg_tx_sync_5_i_0_a2_1_0), + .LO(plm_v4f_mgt_reset_delay_reg_tx_pcs_init_5_i_o2_0_o2_2_718) + ); + defparam plm_v4f_mgt_reset_delay_reg_tx_pcs_init_5_i_o2_0_o2.INIT = 16'h20C0; + LUT4 plm_v4f_mgt_reset_delay_reg_tx_pcs_init_5_i_o2_0_o2 ( + .I0(plm_v4f_mgt_N_863_i), + .I1(plm_v4f_mgt_reg_rst_cnt[9]), + .I2(plm_v4f_mgt_reset_delay_reg_tx_pcs_init_5_i_o2_0_o2_2_718), + .I3(cfg_cfg_6102[507]), + .O(plm_v4f_mgt_N_870_i) + ); + defparam plm_v4f_mgt_reg_phy_clk_toggle_i.INIT = 4'h1; + LUT1_L plm_v4f_mgt_reg_phy_clk_toggle_i ( + .I0(plm_v4f_mgt_reg_phy_clk_toggle_745), + .LO(plm_v4f_mgt_reg_phy_clk_toggle_i_744) + ); + defparam plm_v4f_mgt_delta_detect_mgtdiv2_cke_reg_mgtdiv2_cke_phase1_3.INIT = 4'h6; + LUT2_L plm_v4f_mgt_delta_detect_mgtdiv2_cke_reg_mgtdiv2_cke_phase1_3 ( + .I0(plm_v4f_mgt_reg_mgtdiv2_clk_sample_747), + .I1(plm_v4f_mgt_reg_mgtdiv2_clk_toggle_751), + .LO(plm_v4f_mgt_delta_detect_mgtdiv2_cke_reg_mgtdiv2_cke_phase1_3_748) + ); + defparam plm_v4f_mgt_reg_mgtdiv2_clk_toggle_i.INIT = 4'h1; + LUT1_L plm_v4f_mgt_reg_mgtdiv2_clk_toggle_i ( + .I0(plm_v4f_mgt_reg_mgtdiv2_clk_toggle_751), + .LO(plm_v4f_mgt_reg_mgtdiv2_clk_toggle_i_750) + ); + defparam plm_v4f_mgt_reset_delay_N_886_i.INIT = 4'hB; + LUT2_L plm_v4f_mgt_reset_delay_N_886_i ( + .I0(plm_v4f_mgt_N_870_i), + .I1(plm_v4f_mgt_pma_rxlock3), + .LO(plm_v4f_mgt_N_886_i) + ); + defparam plm_v4f_mgt_reset_delay_N_885_i.INIT = 4'hB; + LUT2_L plm_v4f_mgt_reset_delay_N_885_i ( + .I0(plm_v4f_mgt_N_870_i), + .I1(plm_v4f_mgt_pma_rxlock2), + .LO(plm_v4f_mgt_N_885_i) + ); + defparam plm_v4f_mgt_reset_delay_N_884_i.INIT = 4'hB; + LUT2_L plm_v4f_mgt_reset_delay_N_884_i ( + .I0(plm_v4f_mgt_N_870_i), + .I1(plm_v4f_mgt_pma_rxlock1), + .LO(plm_v4f_mgt_N_884_i) + ); + defparam plm_v4f_mgt_reset_delay_N_883_i.INIT = 4'hB; + LUT2_L plm_v4f_mgt_reset_delay_N_883_i ( + .I0(plm_v4f_mgt_N_870_i), + .I1(plm_v4f_mgt_pma_rxlock0), + .LO(plm_v4f_mgt_N_883_i) + ); + defparam plm_v4f_mgt_reset_delay_reg_tx_sync_5_i_0.INIT = 16'h2000; + LUT4_L plm_v4f_mgt_reset_delay_reg_tx_sync_5_i_0 ( + .I0(plm_v4f_mgt_N_866_i), + .I1(plm_v4f_mgt_reg_rst_cnt[9]), + .I2(plm_v4f_mgt_reset_delay_reg_tx_sync_5_i_0_1_720), + .I3(plm_v4f_mgt_reset_delay_reg_tx_sync_5_i_0_3_719), + .LO(plm_v4f_mgt_N_444_i) + ); + defparam plm_v4f_mgt_un3_reg_pma_cnt_axbxc2.INIT = 8'h78; + LUT3_L plm_v4f_mgt_un3_reg_pma_cnt_axbxc2 ( + .I0(plm_v4f_mgt_reg_pma_cnt[0]), + .I1(plm_v4f_mgt_reg_pma_cnt[1]), + .I2(plm_v4f_mgt_reg_pma_cnt[2]), + .LO(plm_v4f_mgt_un3_reg_pma_cnt_axbxc2_759) + ); + defparam plm_v4f_mgt_un3_reg_pma_cnt_axbxc1.INIT = 4'h6; + LUT2_L plm_v4f_mgt_un3_reg_pma_cnt_axbxc1 ( + .I0(plm_v4f_mgt_reg_pma_cnt[0]), + .I1(plm_v4f_mgt_reg_pma_cnt[1]), + .LO(plm_v4f_mgt_un3_reg_pma_cnt_axbxc1_760) + ); + defparam plm_v4f_mgt_reg_pma_cnt_i_0_.INIT = 4'h1; + LUT1_L plm_v4f_mgt_reg_pma_cnt_i_0_ ( + .I0(plm_v4f_mgt_reg_pma_cnt[0]), + .LO(plm_v4f_mgt_reg_pma_cnt_i[0]) + ); + defparam plm_v4f_mgt_un3_reg_dcm_cnt_axbxc3.INIT = 16'h7F80; + LUT4_L plm_v4f_mgt_un3_reg_dcm_cnt_axbxc3 ( + .I0(plm_v4f_mgt_reg_dcm_cnt[0]), + .I1(plm_v4f_mgt_reg_dcm_cnt[1]), + .I2(plm_v4f_mgt_reg_dcm_cnt[2]), + .I3(plm_v4f_mgt_reg_dcm_cnt[3]), + .LO(plm_v4f_mgt_un3_reg_dcm_cnt_axbxc3_761) + ); + defparam plm_v4f_mgt_un3_reg_dcm_cnt_axbxc2.INIT = 8'h78; + LUT3_L plm_v4f_mgt_un3_reg_dcm_cnt_axbxc2 ( + .I0(plm_v4f_mgt_reg_dcm_cnt[0]), + .I1(plm_v4f_mgt_reg_dcm_cnt[1]), + .I2(plm_v4f_mgt_reg_dcm_cnt[2]), + .LO(plm_v4f_mgt_un3_reg_dcm_cnt_axbxc2_762) + ); + defparam plm_v4f_mgt_un3_reg_dcm_cnt_axbxc1.INIT = 4'h6; + LUT2_L plm_v4f_mgt_un3_reg_dcm_cnt_axbxc1 ( + .I0(plm_v4f_mgt_reg_dcm_cnt[0]), + .I1(plm_v4f_mgt_reg_dcm_cnt[1]), + .LO(plm_v4f_mgt_un3_reg_dcm_cnt_axbxc1_763) + ); + defparam plm_v4f_mgt_reg_dcm_cnt_i_0_.INIT = 4'h1; + LUT1_L plm_v4f_mgt_reg_dcm_cnt_i_0_ ( + .I0(plm_v4f_mgt_reg_dcm_cnt[0]), + .LO(plm_v4f_mgt_reg_dcm_cnt_i[0]) + ); + defparam plm_v4f_mgt_bondage_reg_bond_state_9_1_.INIT = 16'h00EA; + LUT4_L plm_v4f_mgt_bondage_reg_bond_state_9_1_ ( + .I0(plm_v4f_mgt_reg_bond_state_8_0_a3[1]), + .I1(plm_N_11062_i), + .I2(plm_chb_done), + .I3(plm_rx_clear_cs), + .LO(plm_v4f_mgt_bondage_reg_bond_state_9[1]) + ); + defparam plm_v4f_mgt_bondage_reg_bond_state_9_0_.INIT = 8'h01; + LUT3_L plm_v4f_mgt_bondage_reg_bond_state_9_0_ ( + .I0(plm_v4f_mgt_reg_bond_state_8_i_m3[0]), + .I1(plm_chb_done), + .I2(plm_rx_clear_cs), + .LO(plm_v4f_mgt_bondage_reg_bond_state_9[0]) + ); + defparam plm_v4f_mgt_un3_reg_pma_cnt_axbxc3.INIT = 16'h7F80; + LUT4_L plm_v4f_mgt_un3_reg_pma_cnt_axbxc3 ( + .I0(plm_v4f_mgt_reg_pma_cnt[0]), + .I1(plm_v4f_mgt_reg_pma_cnt[1]), + .I2(plm_v4f_mgt_reg_pma_cnt[2]), + .I3(plm_v4f_mgt_reg_pma_cnt[3]), + .LO(plm_v4f_mgt_un3_reg_pma_cnt_axbxc3_764) + ); + defparam plm_v4f_mgt_delta_detect_reg_phase1_3.INIT = 4'h6; + LUT2_L plm_v4f_mgt_delta_detect_reg_phase1_3 ( + .I0(plm_v4f_mgt_reg_mgt_clk_sample_746), + .I1(plm_v4f_mgt_reg_phy_clk_toggle_745), + .LO(plm_v4f_mgt_delta_detect_reg_phase1_3_771) + ); + defparam plm_v4f_mgt_G_837.INIT = 4'h8; + LUT2 plm_v4f_mgt_G_837 ( + .I0(plm_v4f_mgt_reg_phase3_0_DOUT[0]), + .I1(plm_v4f_mgt_G_919_742), + .O(plm_phy_cke) + ); + defparam plm_v4f_mgt_G_863.INIT = 4'hE; + LUT2 plm_v4f_mgt_G_863 ( + .I0(plm_v4f_mgt_N_2600_i), + .I1(plm_v4f_mgt_reg_tee3_dlyline_DOUT[0]), + .O(plm_v4f_mgt_reg_tee3_dlyline[23]) + ); + defparam plm_v4f_mgt_G_889.INIT = 4'hE; + LUT2 plm_v4f_mgt_G_889 ( + .I0(plm_v4f_mgt_N_2600_i), + .I1(plm_v4f_mgt_reg_tee2_dlyline_DOUT[0]), + .O(plm_v4f_mgt_reg_tee2_dlyline[23]) + ); + defparam plm_v4f_mgt_G_915.INIT = 4'hE; + LUT2 plm_v4f_mgt_G_915 ( + .I0(plm_v4f_mgt_N_2600_i), + .I1(plm_v4f_mgt_reg_tee1_dlyline_DOUT[0]), + .O(plm_v4f_mgt_reg_tee1_dlyline[23]) + ); + defparam plm_v4f_mgt_G_941.INIT = 4'hE; + LUT2 plm_v4f_mgt_G_941 ( + .I0(plm_v4f_mgt_N_2600_i), + .I1(plm_v4f_mgt_reg_tee0_dlyline_DOUT[0]), + .O(plm_v4f_mgt_reg_tee0_dlyline[23]) + ); + FDC plm_v4f_mgt_G_848 ( + .C(mgt_clk), + .D(plm_v4f_mgt_G_925_736), + .Q(plm_v4f_mgt_G_848_733), + .CLR(plm_rst) + ); + FDC plm_v4f_mgt_G_846 ( + .C(mgt_clk), + .D(plm_v4f_mgt_G_923_738), + .Q(plm_v4f_mgt_G_846_735), + .CLR(plm_rst) + ); + FDC plm_v4f_mgt_G_844 ( + .C(mgt_clk), + .D(plm_v4f_mgt_G_921_740), + .Q(plm_v4f_mgt_G_844_737), + .CLR(plm_rst) + ); + FDC plm_v4f_mgt_G_842 ( + .C(mgt_clk), + .D(plm_v4f_mgt_G_919_742), + .Q(plm_v4f_mgt_G_842_739), + .CLR(plm_rst) + ); + FDC plm_v4f_mgt_G_835 ( + .C(mgt_clk), + .D(plm_v4f_mgt_G_917_743), + .Q(plm_v4f_mgt_G_835_741), + .CLR(plm_rst) + ); + FDC plm_v4f_mgt_G_862 ( + .C(mgt_clk), + .D(plm_v4f_mgt_G_939_722), + .Q(plm_v4f_mgt_G_862_770), + .CLR(plm_rst) + ); + FDC plm_v4f_mgt_G_860 ( + .C(mgt_clk), + .D(plm_v4f_mgt_G_937_724), + .Q(plm_v4f_mgt_G_860_721), + .CLR(plm_rst) + ); + FDC plm_v4f_mgt_G_858 ( + .C(mgt_clk), + .D(plm_v4f_mgt_G_935_726), + .Q(plm_v4f_mgt_G_858_723), + .CLR(plm_rst) + ); + FDC plm_v4f_mgt_G_856 ( + .C(mgt_clk), + .D(plm_v4f_mgt_G_933_728), + .Q(plm_v4f_mgt_G_856_725), + .CLR(plm_rst) + ); + FDC plm_v4f_mgt_G_854 ( + .C(mgt_clk), + .D(plm_v4f_mgt_G_931_730), + .Q(plm_v4f_mgt_G_854_727), + .CLR(plm_rst) + ); + FDC plm_v4f_mgt_G_852 ( + .C(mgt_clk), + .D(plm_v4f_mgt_G_929_732), + .Q(plm_v4f_mgt_G_852_729), + .CLR(plm_rst) + ); + FDC plm_v4f_mgt_G_850 ( + .C(mgt_clk), + .D(plm_v4f_mgt_G_927_734), + .Q(plm_v4f_mgt_G_850_731), + .CLR(plm_rst) + ); + FDC plm_v4f_mgt_G_939 ( + .C(mgt_clk), + .D(plm_v4f_mgt_G_860_721), + .Q(plm_v4f_mgt_G_939_722), + .CLR(plm_rst) + ); + FDC plm_v4f_mgt_G_937 ( + .C(mgt_clk), + .D(plm_v4f_mgt_G_858_723), + .Q(plm_v4f_mgt_G_937_724), + .CLR(plm_rst) + ); + FDC plm_v4f_mgt_G_935 ( + .C(mgt_clk), + .D(plm_v4f_mgt_G_856_725), + .Q(plm_v4f_mgt_G_935_726), + .CLR(plm_rst) + ); + FDC plm_v4f_mgt_G_933 ( + .C(mgt_clk), + .D(plm_v4f_mgt_G_854_727), + .Q(plm_v4f_mgt_G_933_728), + .CLR(plm_rst) + ); + FDC plm_v4f_mgt_G_931 ( + .C(mgt_clk), + .D(plm_v4f_mgt_G_852_729), + .Q(plm_v4f_mgt_G_931_730), + .CLR(plm_rst) + ); + FDC plm_v4f_mgt_G_929 ( + .C(mgt_clk), + .D(plm_v4f_mgt_G_850_731), + .Q(plm_v4f_mgt_G_929_732), + .CLR(plm_rst) + ); + FDC plm_v4f_mgt_G_927 ( + .C(mgt_clk), + .D(plm_v4f_mgt_G_848_733), + .Q(plm_v4f_mgt_G_927_734), + .CLR(plm_rst) + ); + FDC plm_v4f_mgt_G_925 ( + .C(mgt_clk), + .D(plm_v4f_mgt_G_846_735), + .Q(plm_v4f_mgt_G_925_736), + .CLR(plm_rst) + ); + FDC plm_v4f_mgt_G_923 ( + .C(mgt_clk), + .D(plm_v4f_mgt_G_844_737), + .Q(plm_v4f_mgt_G_923_738), + .CLR(plm_rst) + ); + FDC plm_v4f_mgt_G_921 ( + .C(mgt_clk), + .D(plm_v4f_mgt_G_842_739), + .Q(plm_v4f_mgt_G_921_740), + .CLR(plm_rst) + ); + FDC plm_v4f_mgt_G_919 ( + .C(mgt_clk), + .D(plm_v4f_mgt_G_835_741), + .Q(plm_v4f_mgt_G_919_742), + .CLR(plm_rst) + ); + FDC plm_v4f_mgt_G_917 ( + .C(mgt_clk), + .D(plm_v4f_mgt_pipe_phystatus), + .Q(plm_v4f_mgt_G_917_743), + .CLR(plm_rst) + ); + FD plm_v4f_mgt_reg_tee0_dlyline_DOUT_0_ ( + .C(mgt_clk), + .D(plm_v4f_mgt_reg_tee0_dlyline_N_7), + .Q(plm_v4f_mgt_reg_tee0_dlyline_DOUT[0]) + ); + FD plm_v4f_mgt_reg_tee1_dlyline_DOUT_0_ ( + .C(mgt_clk), + .D(plm_v4f_mgt_reg_tee1_dlyline_N_7), + .Q(plm_v4f_mgt_reg_tee1_dlyline_DOUT[0]) + ); + FD plm_v4f_mgt_reg_tee2_dlyline_DOUT_0_ ( + .C(mgt_clk), + .D(plm_v4f_mgt_reg_tee2_dlyline_N_7), + .Q(plm_v4f_mgt_reg_tee2_dlyline_DOUT[0]) + ); + FD plm_v4f_mgt_reg_tee3_dlyline_DOUT_0_ ( + .C(mgt_clk), + .D(plm_v4f_mgt_reg_tee3_dlyline_tmp_d_array_1[0]), + .Q(plm_v4f_mgt_reg_tee3_dlyline_DOUT[0]) + ); + FD plm_v4f_mgt_reg_phase3_0_DOUT_0_ ( + .C(mgt_clk), + .D(plm_v4f_mgt_reg_phase3_0_tmp_d_array_0[0]), + .Q(plm_v4f_mgt_reg_phase3_0_DOUT[0]) + ); + FDCE plm_v4f_mgt_reg_rst_cnt_14_ ( + .CE(plm_v4f_mgt_un1_reg_plm_rst_n_2_i_i[0]), + .C(mgt_clk), + .D(plm_v4f_mgt_reg_rst_cnt_s[14]), + .Q(plm_v4f_mgt_reg_rst_cnt[14]), + .CLR(plm_v4f_mgt_sys_init_n_i_757) + ); + FDCE plm_v4f_mgt_reg_rst_cnt_13_ ( + .CE(plm_v4f_mgt_un1_reg_plm_rst_n_2_i_i[0]), + .C(mgt_clk), + .D(plm_v4f_mgt_reg_rst_cnt_s[13]), + .Q(plm_v4f_mgt_reg_rst_cnt[13]), + .CLR(plm_v4f_mgt_sys_init_n_i_757) + ); + FDCE plm_v4f_mgt_reg_rst_cnt_12_ ( + .CE(plm_v4f_mgt_un1_reg_plm_rst_n_2_i_i[0]), + .C(mgt_clk), + .D(plm_v4f_mgt_reg_rst_cnt_s[12]), + .Q(plm_v4f_mgt_reg_rst_cnt[12]), + .CLR(plm_v4f_mgt_sys_init_n_i_757) + ); + FDCE plm_v4f_mgt_reg_rst_cnt_11_ ( + .CE(plm_v4f_mgt_un1_reg_plm_rst_n_2_i_i[0]), + .C(mgt_clk), + .D(plm_v4f_mgt_reg_rst_cnt_s[11]), + .Q(plm_v4f_mgt_reg_rst_cnt[11]), + .CLR(plm_v4f_mgt_sys_init_n_i_757) + ); + FDCE plm_v4f_mgt_reg_rst_cnt_10_ ( + .CE(plm_v4f_mgt_un1_reg_plm_rst_n_2_i_i[0]), + .C(mgt_clk), + .D(plm_v4f_mgt_reg_rst_cnt_s[10]), + .Q(plm_v4f_mgt_reg_rst_cnt[10]), + .CLR(plm_v4f_mgt_sys_init_n_i_757) + ); + FDCE plm_v4f_mgt_reg_rst_cnt_9_ ( + .CE(plm_v4f_mgt_un1_reg_plm_rst_n_2_i_i[0]), + .C(mgt_clk), + .D(plm_v4f_mgt_reg_rst_cnt_s[9]), + .Q(plm_v4f_mgt_reg_rst_cnt[9]), + .CLR(plm_v4f_mgt_sys_init_n_i_757) + ); + FDCE plm_v4f_mgt_reg_rst_cnt_8_ ( + .CE(plm_v4f_mgt_un1_reg_plm_rst_n_2_i_i[0]), + .C(mgt_clk), + .D(plm_v4f_mgt_reg_rst_cnt_s[8]), + .Q(plm_v4f_mgt_reg_rst_cnt[8]), + .CLR(plm_v4f_mgt_sys_init_n_i_757) + ); + FDCE plm_v4f_mgt_reg_rst_cnt_7_ ( + .CE(plm_v4f_mgt_un1_reg_plm_rst_n_2_i_i[0]), + .C(mgt_clk), + .D(plm_v4f_mgt_reg_rst_cnt_s[7]), + .Q(plm_v4f_mgt_reg_rst_cnt[7]), + .CLR(plm_v4f_mgt_sys_init_n_i_757) + ); + FDCE plm_v4f_mgt_reg_rst_cnt_6_ ( + .CE(plm_v4f_mgt_un1_reg_plm_rst_n_2_i_i[0]), + .C(mgt_clk), + .D(plm_v4f_mgt_reg_rst_cnt_s[6]), + .Q(plm_v4f_mgt_reg_rst_cnt[6]), + .CLR(plm_v4f_mgt_sys_init_n_i_757) + ); + FDCE plm_v4f_mgt_reg_rst_cnt_5_ ( + .CE(plm_v4f_mgt_un1_reg_plm_rst_n_2_i_i[0]), + .C(mgt_clk), + .D(plm_v4f_mgt_reg_rst_cnt_s[5]), + .Q(plm_v4f_mgt_reg_rst_cnt[5]), + .CLR(plm_v4f_mgt_sys_init_n_i_757) + ); + FDCE plm_v4f_mgt_reg_rst_cnt_4_ ( + .CE(plm_v4f_mgt_un1_reg_plm_rst_n_2_i_i[0]), + .C(mgt_clk), + .D(plm_v4f_mgt_reg_rst_cnt_s[4]), + .Q(plm_v4f_mgt_reg_rst_cnt[4]), + .CLR(plm_v4f_mgt_sys_init_n_i_757) + ); + FDCE plm_v4f_mgt_reg_rst_cnt_3_ ( + .CE(plm_v4f_mgt_un1_reg_plm_rst_n_2_i_i[0]), + .C(mgt_clk), + .D(plm_v4f_mgt_reg_rst_cnt_s[3]), + .Q(plm_v4f_mgt_reg_rst_cnt[3]), + .CLR(plm_v4f_mgt_sys_init_n_i_757) + ); + FDCE plm_v4f_mgt_reg_rst_cnt_2_ ( + .CE(plm_v4f_mgt_un1_reg_plm_rst_n_2_i_i[0]), + .C(mgt_clk), + .D(plm_v4f_mgt_reg_rst_cnt_s[2]), + .Q(plm_v4f_mgt_reg_rst_cnt[2]), + .CLR(plm_v4f_mgt_sys_init_n_i_757) + ); + FDCE plm_v4f_mgt_reg_rst_cnt_1_ ( + .CE(plm_v4f_mgt_un1_reg_plm_rst_n_2_i_i[0]), + .C(mgt_clk), + .D(plm_v4f_mgt_reg_rst_cnt_s[1]), + .Q(plm_v4f_mgt_reg_rst_cnt[1]), + .CLR(plm_v4f_mgt_sys_init_n_i_757) + ); + FDCE plm_v4f_mgt_reg_rst_cnt_0_ ( + .CE(plm_v4f_mgt_un1_reg_plm_rst_n_2_i_i[0]), + .C(mgt_clk), + .D(plm_v4f_mgt_reg_rst_cnt_s[0]), + .Q(plm_v4f_mgt_reg_rst_cnt[0]), + .CLR(plm_v4f_mgt_sys_init_n_i_757) + ); + FDC plm_v4f_mgt_reg_phy_clk_toggle ( + .C(NlwRenamedSig_OI_trn_clk), + .D(plm_v4f_mgt_reg_phy_clk_toggle_i_744), + .Q(plm_v4f_mgt_reg_phy_clk_toggle_745), + .CLR(plm_rst) + ); + FDC plm_v4f_mgt_reg_mgt_clk_sample ( + .C(mgt_clk), + .D(plm_v4f_mgt_reg_phy_clk_toggle_745), + .Q(plm_v4f_mgt_reg_mgt_clk_sample_746), + .CLR(plm_rst) + ); + FDC plm_v4f_mgt_reg_mgtdiv2_clk_sample ( + .C(mgt_clk), + .D(plm_v4f_mgt_reg_mgtdiv2_clk_toggle_751), + .Q(plm_v4f_mgt_reg_mgtdiv2_clk_sample_747), + .CLR(plm_v4f_mgt_sys_init_n_i_757) + ); + FDC plm_v4f_mgt_reg_mgtdiv2_cke_phase1 ( + .C(mgt_clk), + .D(plm_v4f_mgt_delta_detect_mgtdiv2_cke_reg_mgtdiv2_cke_phase1_3_748), + .Q(plm_v4f_mgt_reg_mgtdiv2_cke_phase1_749), + .CLR(plm_v4f_mgt_sys_init_n_i_757) + ); + FDC plm_v4f_mgt_reg_mgtdiv2_clk_toggle ( + .C(plm_v4f_mgt_mgtdiv2_clk), + .D(plm_v4f_mgt_reg_mgtdiv2_clk_toggle_i_750), + .Q(plm_v4f_mgt_reg_mgtdiv2_clk_toggle_751), + .CLR(plm_v4f_mgt_sys_init_n_i_757) + ); + FDC plm_v4f_mgt_reg_plm_rst_n ( + .C(mgt_clk), + .D(plm_v4f_mgt_un1_reg_plm_rst_n_2_i[0]), + .Q(NlwRenamedSig_OI_trn_reset_n), + .CLR(plm_v4f_mgt_sys_init_n_i_757) + ); + FDP plm_v4f_mgt_reg_plm_rst ( + .PRE(plm_v4f_mgt_sys_init_n_i_757), + .C(mgt_clk), + .D(plm_v4f_mgt_un1_reg_plm_rst_n_2_i_i[0]), + .Q(plm_rst) + ); + FDC plm_v4f_mgt_reg_rx3_pcs_init ( + .C(mgt_clk), + .D(plm_v4f_mgt_N_886_i), + .Q(plm_v4f_mgt_reg_rx3_pcs_init_752), + .CLR(plm_v4f_mgt_sys_init_n_i_757) + ); + FDC plm_v4f_mgt_reg_rx2_pcs_init ( + .C(mgt_clk), + .D(plm_v4f_mgt_N_885_i), + .Q(plm_v4f_mgt_reg_rx2_pcs_init_753), + .CLR(plm_v4f_mgt_sys_init_n_i_757) + ); + FDC plm_v4f_mgt_reg_rx1_pcs_init ( + .C(mgt_clk), + .D(plm_v4f_mgt_N_884_i), + .Q(plm_v4f_mgt_reg_rx1_pcs_init_754), + .CLR(plm_v4f_mgt_sys_init_n_i_757) + ); + FDC plm_v4f_mgt_reg_rx0_pcs_init ( + .C(mgt_clk), + .D(plm_v4f_mgt_N_883_i), + .Q(plm_v4f_mgt_reg_rx0_pcs_init_755), + .CLR(plm_v4f_mgt_sys_init_n_i_757) + ); + FDC plm_v4f_mgt_reg_tx_sync ( + .C(mgt_clk), + .D(plm_v4f_mgt_N_444_i), + .Q(plm_v4f_mgt_reg_tx_sync_756), + .CLR(plm_v4f_mgt_sys_init_n_i_757) + ); + FDC plm_v4f_mgt_reg_tx_pcs_init ( + .C(mgt_clk), + .D(plm_v4f_mgt_N_870_i), + .Q(plm_v4f_mgt_reg_tx_pcs_init_758), + .CLR(plm_v4f_mgt_sys_init_n_i_757) + ); + FDC plm_v4f_mgt_reg_pma_cnt_2_ ( + .C(plm_v4f_mgt_special_clk), + .D(plm_v4f_mgt_un3_reg_pma_cnt_axbxc2_759), + .Q(plm_v4f_mgt_reg_pma_cnt[2]), + .CLR(plm_v4f_mgt_dcm_lock_i_769) + ); + FDC plm_v4f_mgt_reg_pma_cnt_1_ ( + .C(plm_v4f_mgt_special_clk), + .D(plm_v4f_mgt_un3_reg_pma_cnt_axbxc1_760), + .Q(plm_v4f_mgt_reg_pma_cnt[1]), + .CLR(plm_v4f_mgt_dcm_lock_i_769) + ); + FDC plm_v4f_mgt_reg_pma_cnt_0_ ( + .C(plm_v4f_mgt_special_clk), + .D(plm_v4f_mgt_reg_pma_cnt_i[0]), + .Q(plm_v4f_mgt_reg_pma_cnt[0]), + .CLR(plm_v4f_mgt_dcm_lock_i_769) + ); + FDC plm_v4f_mgt_reg_dcm_cnt_3_ ( + .C(plm_v4f_mgt_special_clk), + .D(plm_v4f_mgt_un3_reg_dcm_cnt_axbxc3_761), + .Q(plm_v4f_mgt_reg_dcm_cnt[3]), + .CLR(plm_v4f_mgt_sys_rst_n_i) + ); + FDC plm_v4f_mgt_reg_dcm_cnt_2_ ( + .C(plm_v4f_mgt_special_clk), + .D(plm_v4f_mgt_un3_reg_dcm_cnt_axbxc2_762), + .Q(plm_v4f_mgt_reg_dcm_cnt[2]), + .CLR(plm_v4f_mgt_sys_rst_n_i) + ); + FDC plm_v4f_mgt_reg_dcm_cnt_1_ ( + .C(plm_v4f_mgt_special_clk), + .D(plm_v4f_mgt_un3_reg_dcm_cnt_axbxc1_763), + .Q(plm_v4f_mgt_reg_dcm_cnt[1]), + .CLR(plm_v4f_mgt_sys_rst_n_i) + ); + FDC plm_v4f_mgt_reg_dcm_cnt_0_ ( + .C(plm_v4f_mgt_special_clk), + .D(plm_v4f_mgt_reg_dcm_cnt_i[0]), + .Q(plm_v4f_mgt_reg_dcm_cnt[0]), + .CLR(plm_v4f_mgt_sys_rst_n_i) + ); + FDC plm_v4f_mgt_reg_bond_state_1_ ( + .C(mgt_clk), + .D(plm_v4f_mgt_bondage_reg_bond_state_9[1]), + .Q(plm_chb_done), + .CLR(plm_rst) + ); + FDC plm_v4f_mgt_reg_bond_state_0_ ( + .C(mgt_clk), + .D(plm_v4f_mgt_bondage_reg_bond_state_9[0]), + .Q(plm_v4f_mgt_reg_bond_state[0]), + .CLR(plm_rst) + ); + FDC plm_v4f_mgt_reg_pma_cnt_3_ ( + .C(plm_v4f_mgt_special_clk), + .D(plm_v4f_mgt_un3_reg_pma_cnt_axbxc3_764), + .Q(plm_v4f_mgt_reg_pma_cnt[3]), + .CLR(plm_v4f_mgt_dcm_lock_i_769) + ); + FD plm_v4f_mgt_dtx0_data_3_ ( + .C(mgt_clk), + .D(plm_tx0_data[3]), + .Q(plm_v4f_mgt_dtx0_data[3]) + ); + FD plm_v4f_mgt_dtx0_data_2_ ( + .C(mgt_clk), + .D(plm_tx0_data[2]), + .Q(plm_v4f_mgt_dtx0_data[2]) + ); + FD plm_v4f_mgt_dtx0_data_1_ ( + .C(mgt_clk), + .D(plm_tx0_data[1]), + .Q(plm_v4f_mgt_dtx0_data[1]) + ); + FD plm_v4f_mgt_dtx0_data_0_ ( + .C(mgt_clk), + .D(plm_tx0_data[0]), + .Q(plm_v4f_mgt_dtx0_data[0]) + ); + FD plm_v4f_mgt_dtx1_char_disp_val_0_ ( + .C(mgt_clk), + .D(plm_GND_702), + .Q(plm_v4f_mgt_dtx1_char_disp_val[0]) + ); + FD plm_v4f_mgt_dtx1_char_disp_mode_1_ ( + .C(mgt_clk), + .D(plm_GND_702), + .Q(plm_v4f_mgt_dtx1_char_disp_mode[1]) + ); + FD plm_v4f_mgt_dtx1_char_disp_mode_0_ ( + .C(mgt_clk), + .D(plm_GND_702), + .Q(plm_v4f_mgt_dtx1_char_disp_mode[0]) + ); + FD plm_v4f_mgt_dtx0_data_15_ ( + .C(mgt_clk), + .D(plm_tx0_data[15]), + .Q(plm_v4f_mgt_dtx0_data[15]) + ); + FD plm_v4f_mgt_dtx0_data_14_ ( + .C(mgt_clk), + .D(plm_tx0_data[14]), + .Q(plm_v4f_mgt_dtx0_data[14]) + ); + FD plm_v4f_mgt_dtx0_data_13_ ( + .C(mgt_clk), + .D(plm_tx0_data[13]), + .Q(plm_v4f_mgt_dtx0_data[13]) + ); + FD plm_v4f_mgt_dtx0_data_12_ ( + .C(mgt_clk), + .D(plm_tx0_data[12]), + .Q(plm_v4f_mgt_dtx0_data[12]) + ); + FD plm_v4f_mgt_dtx0_data_11_ ( + .C(mgt_clk), + .D(plm_tx0_data[11]), + .Q(plm_v4f_mgt_dtx0_data[11]) + ); + FD plm_v4f_mgt_dtx0_data_10_ ( + .C(mgt_clk), + .D(plm_tx0_data[10]), + .Q(plm_v4f_mgt_dtx0_data[10]) + ); + FD plm_v4f_mgt_dtx0_data_9_ ( + .C(mgt_clk), + .D(plm_tx0_data[9]), + .Q(plm_v4f_mgt_dtx0_data[9]) + ); + FD plm_v4f_mgt_dtx0_data_8_ ( + .C(mgt_clk), + .D(plm_tx0_data[8]), + .Q(plm_v4f_mgt_dtx0_data[8]) + ); + FD plm_v4f_mgt_dtx0_data_7_ ( + .C(mgt_clk), + .D(plm_tx0_data[7]), + .Q(plm_v4f_mgt_dtx0_data[7]) + ); + FD plm_v4f_mgt_dtx0_data_6_ ( + .C(mgt_clk), + .D(plm_tx0_data[6]), + .Q(plm_v4f_mgt_dtx0_data[6]) + ); + FD plm_v4f_mgt_dtx0_data_5_ ( + .C(mgt_clk), + .D(plm_tx0_data[5]), + .Q(plm_v4f_mgt_dtx0_data[5]) + ); + FD plm_v4f_mgt_dtx0_data_4_ ( + .C(mgt_clk), + .D(plm_tx0_data[4]), + .Q(plm_v4f_mgt_dtx0_data[4]) + ); + FD plm_v4f_mgt_dtx1_data_11_ ( + .C(mgt_clk), + .D(plm_tx1_data[11]), + .Q(plm_v4f_mgt_dtx1_data[11]) + ); + FD plm_v4f_mgt_dtx1_data_10_ ( + .C(mgt_clk), + .D(plm_tx1_data[10]), + .Q(plm_v4f_mgt_dtx1_data[10]) + ); + FD plm_v4f_mgt_dtx1_data_9_ ( + .C(mgt_clk), + .D(plm_tx1_data[9]), + .Q(plm_v4f_mgt_dtx1_data[9]) + ); + FD plm_v4f_mgt_dtx1_data_8_ ( + .C(mgt_clk), + .D(plm_tx1_data[8]), + .Q(plm_v4f_mgt_dtx1_data[8]) + ); + FD plm_v4f_mgt_dtx1_data_7_ ( + .C(mgt_clk), + .D(plm_tx1_data[7]), + .Q(plm_v4f_mgt_dtx1_data[7]) + ); + FD plm_v4f_mgt_dtx1_data_6_ ( + .C(mgt_clk), + .D(plm_tx1_data[6]), + .Q(plm_v4f_mgt_dtx1_data[6]) + ); + FD plm_v4f_mgt_dtx1_data_5_ ( + .C(mgt_clk), + .D(plm_tx1_data[5]), + .Q(plm_v4f_mgt_dtx1_data[5]) + ); + FD plm_v4f_mgt_dtx1_data_4_ ( + .C(mgt_clk), + .D(plm_tx1_data[4]), + .Q(plm_v4f_mgt_dtx1_data[4]) + ); + FD plm_v4f_mgt_dtx1_data_3_ ( + .C(mgt_clk), + .D(plm_tx1_data[3]), + .Q(plm_v4f_mgt_dtx1_data[3]) + ); + FD plm_v4f_mgt_dtx1_data_2_ ( + .C(mgt_clk), + .D(plm_tx1_data[2]), + .Q(plm_v4f_mgt_dtx1_data[2]) + ); + FD plm_v4f_mgt_dtx1_data_1_ ( + .C(mgt_clk), + .D(plm_tx1_data[1]), + .Q(plm_v4f_mgt_dtx1_data[1]) + ); + FD plm_v4f_mgt_dtx1_data_0_ ( + .C(mgt_clk), + .D(plm_tx1_data[0]), + .Q(plm_v4f_mgt_dtx1_data[0]) + ); + FD plm_v4f_mgt_dtx1_char_is_k_1_ ( + .C(mgt_clk), + .D(plm_tx2_char_is_k[1]), + .Q(plm_v4f_mgt_dtx1_char_is_k[1]) + ); + FD plm_v4f_mgt_dtx1_char_is_k_0_ ( + .C(mgt_clk), + .D(plm_tx2_char_is_k[0]), + .Q(plm_v4f_mgt_dtx1_char_is_k[0]) + ); + FD plm_v4f_mgt_dtx1_char_disp_val_1_ ( + .C(mgt_clk), + .D(plm_GND_702), + .Q(plm_v4f_mgt_dtx1_char_disp_val[1]) + ); + FD plm_v4f_mgt_dtx2_data_4_ ( + .C(mgt_clk), + .D(plm_tx2_data[4]), + .Q(plm_v4f_mgt_dtx2_data[4]) + ); + FD plm_v4f_mgt_dtx2_data_3_ ( + .C(mgt_clk), + .D(plm_tx2_data[3]), + .Q(plm_v4f_mgt_dtx2_data[3]) + ); + FD plm_v4f_mgt_dtx2_data_2_ ( + .C(mgt_clk), + .D(plm_tx2_data[2]), + .Q(plm_v4f_mgt_dtx2_data[2]) + ); + FD plm_v4f_mgt_dtx2_data_1_ ( + .C(mgt_clk), + .D(plm_tx2_data[1]), + .Q(plm_v4f_mgt_dtx2_data[1]) + ); + FD plm_v4f_mgt_dtx2_data_0_ ( + .C(mgt_clk), + .D(plm_tx2_data[0]), + .Q(plm_v4f_mgt_dtx2_data[0]) + ); + FD plm_v4f_mgt_dtx2_char_is_k_1_ ( + .C(mgt_clk), + .D(plm_tx2_char_is_k[1]), + .Q(plm_v4f_mgt_dtx2_char_is_k[1]) + ); + FD plm_v4f_mgt_dtx2_char_is_k_0_ ( + .C(mgt_clk), + .D(plm_tx2_char_is_k[0]), + .Q(plm_v4f_mgt_dtx2_char_is_k[0]) + ); + FD plm_v4f_mgt_dtx2_char_disp_val_1_ ( + .C(mgt_clk), + .D(plm_GND_702), + .Q(plm_v4f_mgt_dtx2_char_disp_val[1]) + ); + FD plm_v4f_mgt_dtx2_char_disp_val_0_ ( + .C(mgt_clk), + .D(plm_GND_702), + .Q(plm_v4f_mgt_dtx2_char_disp_val[0]) + ); + FD plm_v4f_mgt_dtx2_char_disp_mode_1_ ( + .C(mgt_clk), + .D(plm_GND_702), + .Q(plm_v4f_mgt_dtx2_char_disp_mode[1]) + ); + FD plm_v4f_mgt_dtx2_char_disp_mode_0_ ( + .C(mgt_clk), + .D(plm_GND_702), + .Q(plm_v4f_mgt_dtx2_char_disp_mode[0]) + ); + FD plm_v4f_mgt_dtx1_data_15_ ( + .C(mgt_clk), + .D(plm_tx1_data[15]), + .Q(plm_v4f_mgt_dtx1_data[15]) + ); + FD plm_v4f_mgt_dtx1_data_14_ ( + .C(mgt_clk), + .D(plm_tx1_data[14]), + .Q(plm_v4f_mgt_dtx1_data[14]) + ); + FD plm_v4f_mgt_dtx1_data_13_ ( + .C(mgt_clk), + .D(plm_tx1_data[13]), + .Q(plm_v4f_mgt_dtx1_data[13]) + ); + FD plm_v4f_mgt_dtx1_data_12_ ( + .C(mgt_clk), + .D(plm_tx1_data[12]), + .Q(plm_v4f_mgt_dtx1_data[12]) + ); + FD plm_v4f_mgt_dtx3_char_disp_val_1_ ( + .C(mgt_clk), + .D(plm_GND_702), + .Q(plm_v4f_mgt_dtx3_char_disp_val[1]) + ); + FD plm_v4f_mgt_dtx3_char_disp_val_0_ ( + .C(mgt_clk), + .D(plm_GND_702), + .Q(plm_v4f_mgt_dtx3_char_disp_val[0]) + ); + FD plm_v4f_mgt_dtx3_char_disp_mode_1_ ( + .C(mgt_clk), + .D(plm_GND_702), + .Q(plm_v4f_mgt_dtx3_char_disp_mode[1]) + ); + FD plm_v4f_mgt_dtx3_char_disp_mode_0_ ( + .C(mgt_clk), + .D(plm_GND_702), + .Q(plm_v4f_mgt_dtx3_char_disp_mode[0]) + ); + FD plm_v4f_mgt_dtx2_data_15_ ( + .C(mgt_clk), + .D(plm_tx2_data[15]), + .Q(plm_v4f_mgt_dtx2_data[15]) + ); + FD plm_v4f_mgt_dtx2_data_14_ ( + .C(mgt_clk), + .D(plm_tx2_data[14]), + .Q(plm_v4f_mgt_dtx2_data[14]) + ); + FD plm_v4f_mgt_dtx2_data_13_ ( + .C(mgt_clk), + .D(plm_tx2_data[13]), + .Q(plm_v4f_mgt_dtx2_data[13]) + ); + FD plm_v4f_mgt_dtx2_data_12_ ( + .C(mgt_clk), + .D(plm_tx2_data[12]), + .Q(plm_v4f_mgt_dtx2_data[12]) + ); + FD plm_v4f_mgt_dtx2_data_11_ ( + .C(mgt_clk), + .D(plm_tx2_data[11]), + .Q(plm_v4f_mgt_dtx2_data[11]) + ); + FD plm_v4f_mgt_dtx2_data_10_ ( + .C(mgt_clk), + .D(plm_tx2_data[10]), + .Q(plm_v4f_mgt_dtx2_data[10]) + ); + FD plm_v4f_mgt_dtx2_data_9_ ( + .C(mgt_clk), + .D(plm_tx2_data[9]), + .Q(plm_v4f_mgt_dtx2_data[9]) + ); + FD plm_v4f_mgt_dtx2_data_8_ ( + .C(mgt_clk), + .D(plm_tx2_data[8]), + .Q(plm_v4f_mgt_dtx2_data[8]) + ); + FD plm_v4f_mgt_dtx2_data_7_ ( + .C(mgt_clk), + .D(plm_tx2_data[7]), + .Q(plm_v4f_mgt_dtx2_data[7]) + ); + FD plm_v4f_mgt_dtx2_data_6_ ( + .C(mgt_clk), + .D(plm_tx2_data[6]), + .Q(plm_v4f_mgt_dtx2_data[6]) + ); + FD plm_v4f_mgt_dtx2_data_5_ ( + .C(mgt_clk), + .D(plm_tx2_data[5]), + .Q(plm_v4f_mgt_dtx2_data[5]) + ); + FD plm_v4f_mgt_dtx3_data_12_ ( + .C(mgt_clk), + .D(plm_tx3_data[12]), + .Q(plm_v4f_mgt_dtx3_data[12]) + ); + FD plm_v4f_mgt_dtx3_data_11_ ( + .C(mgt_clk), + .D(plm_tx3_data[11]), + .Q(plm_v4f_mgt_dtx3_data[11]) + ); + FD plm_v4f_mgt_dtx3_data_10_ ( + .C(mgt_clk), + .D(plm_tx3_data[10]), + .Q(plm_v4f_mgt_dtx3_data[10]) + ); + FD plm_v4f_mgt_dtx3_data_9_ ( + .C(mgt_clk), + .D(plm_tx3_data[9]), + .Q(plm_v4f_mgt_dtx3_data[9]) + ); + FD plm_v4f_mgt_dtx3_data_8_ ( + .C(mgt_clk), + .D(plm_tx3_data[8]), + .Q(plm_v4f_mgt_dtx3_data[8]) + ); + FD plm_v4f_mgt_dtx3_data_7_ ( + .C(mgt_clk), + .D(plm_tx3_data[7]), + .Q(plm_v4f_mgt_dtx3_data[7]) + ); + FD plm_v4f_mgt_dtx3_data_6_ ( + .C(mgt_clk), + .D(plm_tx3_data[6]), + .Q(plm_v4f_mgt_dtx3_data[6]) + ); + FD plm_v4f_mgt_dtx3_data_5_ ( + .C(mgt_clk), + .D(plm_tx3_data[5]), + .Q(plm_v4f_mgt_dtx3_data[5]) + ); + FD plm_v4f_mgt_dtx3_data_4_ ( + .C(mgt_clk), + .D(plm_tx3_data[4]), + .Q(plm_v4f_mgt_dtx3_data[4]) + ); + FD plm_v4f_mgt_dtx3_data_3_ ( + .C(mgt_clk), + .D(plm_tx3_data[3]), + .Q(plm_v4f_mgt_dtx3_data[3]) + ); + FD plm_v4f_mgt_dtx3_data_2_ ( + .C(mgt_clk), + .D(plm_tx3_data[2]), + .Q(plm_v4f_mgt_dtx3_data[2]) + ); + FD plm_v4f_mgt_dtx3_data_1_ ( + .C(mgt_clk), + .D(plm_tx3_data[1]), + .Q(plm_v4f_mgt_dtx3_data[1]) + ); + FD plm_v4f_mgt_dtx3_data_0_ ( + .C(mgt_clk), + .D(plm_tx3_data[0]), + .Q(plm_v4f_mgt_dtx3_data[0]) + ); + FD plm_v4f_mgt_dtx3_char_is_k_1_ ( + .C(mgt_clk), + .D(plm_tx3_char_is_k[1]), + .Q(plm_v4f_mgt_dtx3_char_is_k[1]) + ); + FD plm_v4f_mgt_dtx3_char_is_k_0_ ( + .C(mgt_clk), + .D(plm_tx3_char_is_k[0]), + .Q(plm_v4f_mgt_dtx3_char_is_k[0]) + ); + FD plm_v4f_mgt_dtx0_char_is_k_1_ ( + .C(mgt_clk), + .D(plm_tx0_char_is_k[1]), + .Q(plm_v4f_mgt_dtx0_char_is_k[1]) + ); + FD plm_v4f_mgt_dtx0_char_is_k_0_ ( + .C(mgt_clk), + .D(plm_tx0_char_is_k[0]), + .Q(plm_v4f_mgt_dtx0_char_is_k[0]) + ); + FD plm_v4f_mgt_dtx0_char_disp_val_1_ ( + .C(mgt_clk), + .D(plm_GND_702), + .Q(plm_v4f_mgt_dtx0_char_disp_val[1]) + ); + FD plm_v4f_mgt_dtx0_char_disp_val_0_ ( + .C(mgt_clk), + .D(plm_GND_702), + .Q(plm_v4f_mgt_dtx0_char_disp_val[0]) + ); + FD plm_v4f_mgt_dtx0_char_disp_mode_1_ ( + .C(mgt_clk), + .D(plm_GND_702), + .Q(plm_v4f_mgt_dtx0_char_disp_mode[1]) + ); + FD plm_v4f_mgt_dtx0_char_disp_mode_0_ ( + .C(mgt_clk), + .D(plm_GND_702), + .Q(plm_v4f_mgt_dtx0_char_disp_mode[0]) + ); + FD plm_v4f_mgt_dtx3_data_15_ ( + .C(mgt_clk), + .D(plm_tx3_data[15]), + .Q(plm_v4f_mgt_dtx3_data[15]) + ); + FD plm_v4f_mgt_dtx3_data_14_ ( + .C(mgt_clk), + .D(plm_tx3_data[14]), + .Q(plm_v4f_mgt_dtx3_data[14]) + ); + FD plm_v4f_mgt_dtx3_data_13_ ( + .C(mgt_clk), + .D(plm_tx3_data[13]), + .Q(plm_v4f_mgt_dtx3_data[13]) + ); + FDPE plm_v4f_mgt_reg_dcm ( + .PRE(plm_v4f_mgt_sys_rst_n_i), + .CE(plm_v4f_mgt_dcm_delay_reg_dcm9_765), + .C(plm_v4f_mgt_special_clk), + .D(plm_v4f_mgt_lstate_support[3]), + .Q(plm_v4f_mgt_reg_dcm_766) + ); + FDPE plm_v4f_mgt_reg_pma ( + .PRE(plm_v4f_mgt_dcm_lock_i_769), + .CE(plm_v4f_mgt_pma_delay_reg_pma9_767), + .C(plm_v4f_mgt_special_clk), + .D(plm_v4f_mgt_lstate_support[3]), + .Q(plm_v4f_mgt_reg_pma_768) + ); + INV plm_v4f_mgt_I_831 ( + .I(sys_reset_n), + .O(plm_v4f_mgt_sys_rst_n_i) + ); + INV plm_v4f_mgt_dcm_lock_i ( + .I(plm_v4f_mgt_dcm_lock), + .O(plm_v4f_mgt_dcm_lock_i_769) + ); + INV plm_v4f_mgt_I_828 ( + .I(cmmp_negotiated_width_0[0]), + .O(plm_v4f_mgt_clk_sel_by_4_i) + ); + INV plm_v4f_mgt_un1_reg_plm_rst_n_2_i_i_0_ ( + .I(plm_v4f_mgt_un1_reg_plm_rst_n_2_i[0]), + .O(plm_v4f_mgt_un1_reg_plm_rst_n_2_i_i[0]) + ); + INV plm_v4f_mgt_N_2681_i ( + .I(plm_v4f_mgt_G_862_770), + .O(plm_v4f_mgt_N_2600_i) + ); + SRLC16 plm_v4f_mgt_reg_tee0_dlyline_I_2 ( + .D(plm_v4f_mgt_reg_tee0_dlyline_tmp_array_1[0]), + .Q(plm_v4f_mgt_reg_tee0_dlyline_N_7), + .CLK(mgt_clk), + .Q15(NLW_plm_v4f_mgt_reg_tee0_dlyline_I_2_Q15_UNCONNECTED), + .A0(plm_v4f_mgt_lstate_support[3]), + .A1(plm_v4f_mgt_pipe_phystatus), + .A2(plm_v4f_mgt_pipe_phystatus), + .A3(plm_v4f_mgt_lstate_support[3]) + ); + SRLC16 plm_v4f_mgt_reg_tee0_dlyline_I_1 ( + .D(plm_tx1_txinhibit), + .Q(NLW_plm_v4f_mgt_reg_tee0_dlyline_I_1_Q_UNCONNECTED), + .CLK(mgt_clk), + .Q15(plm_v4f_mgt_reg_tee0_dlyline_tmp_array_1[0]), + .A0(plm_v4f_mgt_pipe_phystatus), + .A1(plm_v4f_mgt_pipe_phystatus), + .A2(plm_v4f_mgt_pipe_phystatus), + .A3(plm_v4f_mgt_pipe_phystatus) + ); + SRLC16 plm_v4f_mgt_reg_tee1_dlyline_I_2 ( + .D(plm_v4f_mgt_reg_tee1_dlyline_tmp_array_1[0]), + .Q(plm_v4f_mgt_reg_tee1_dlyline_N_7), + .CLK(mgt_clk), + .Q15(NLW_plm_v4f_mgt_reg_tee1_dlyline_I_2_Q15_UNCONNECTED), + .A0(plm_v4f_mgt_lstate_support[3]), + .A1(plm_v4f_mgt_pipe_phystatus), + .A2(plm_v4f_mgt_pipe_phystatus), + .A3(plm_v4f_mgt_lstate_support[3]) + ); + SRLC16 plm_v4f_mgt_reg_tee1_dlyline_I_1 ( + .D(plm_tx1_txinhibit), + .Q(NLW_plm_v4f_mgt_reg_tee1_dlyline_I_1_Q_UNCONNECTED), + .CLK(mgt_clk), + .Q15(plm_v4f_mgt_reg_tee1_dlyline_tmp_array_1[0]), + .A0(plm_v4f_mgt_pipe_phystatus), + .A1(plm_v4f_mgt_pipe_phystatus), + .A2(plm_v4f_mgt_pipe_phystatus), + .A3(plm_v4f_mgt_pipe_phystatus) + ); + SRLC16 plm_v4f_mgt_reg_tee2_dlyline_I_2 ( + .D(plm_v4f_mgt_reg_tee2_dlyline_tmp_array_1[0]), + .Q(plm_v4f_mgt_reg_tee2_dlyline_N_7), + .CLK(mgt_clk), + .Q15(NLW_plm_v4f_mgt_reg_tee2_dlyline_I_2_Q15_UNCONNECTED), + .A0(plm_v4f_mgt_lstate_support[3]), + .A1(plm_v4f_mgt_pipe_phystatus), + .A2(plm_v4f_mgt_pipe_phystatus), + .A3(plm_v4f_mgt_lstate_support[3]) + ); + SRLC16 plm_v4f_mgt_reg_tee2_dlyline_I_1 ( + .D(plm_tx1_txinhibit), + .Q(NLW_plm_v4f_mgt_reg_tee2_dlyline_I_1_Q_UNCONNECTED), + .CLK(mgt_clk), + .Q15(plm_v4f_mgt_reg_tee2_dlyline_tmp_array_1[0]), + .A0(plm_v4f_mgt_pipe_phystatus), + .A1(plm_v4f_mgt_pipe_phystatus), + .A2(plm_v4f_mgt_pipe_phystatus), + .A3(plm_v4f_mgt_pipe_phystatus) + ); + SRLC16 plm_v4f_mgt_reg_tee3_dlyline_I_2 ( + .D(plm_v4f_mgt_reg_tee3_dlyline_tmp_array_1[0]), + .Q(plm_v4f_mgt_reg_tee3_dlyline_tmp_d_array_1[0]), + .CLK(mgt_clk), + .Q15(NLW_plm_v4f_mgt_reg_tee3_dlyline_I_2_Q15_UNCONNECTED), + .A0(plm_v4f_mgt_lstate_support[3]), + .A1(plm_v4f_mgt_pipe_phystatus), + .A2(plm_v4f_mgt_pipe_phystatus), + .A3(plm_v4f_mgt_lstate_support[3]) + ); + SRLC16 plm_v4f_mgt_reg_tee3_dlyline_I_1 ( + .D(plm_tx1_txinhibit), + .Q(NLW_plm_v4f_mgt_reg_tee3_dlyline_I_1_Q_UNCONNECTED), + .CLK(mgt_clk), + .Q15(plm_v4f_mgt_reg_tee3_dlyline_tmp_array_1[0]), + .A0(plm_v4f_mgt_pipe_phystatus), + .A1(plm_v4f_mgt_pipe_phystatus), + .A2(plm_v4f_mgt_pipe_phystatus), + .A3(plm_v4f_mgt_pipe_phystatus) + ); + SRL16 plm_v4f_mgt_reg_phase3_0_I_1 ( + .D(plm_v4f_mgt_delta_detect_reg_phase1_3_771), + .Q(plm_v4f_mgt_reg_phase3_0_tmp_d_array_0[0]), + .CLK(mgt_clk), + .A0(plm_v4f_mgt_pipe_phystatus), + .A1(plm_v4f_mgt_lstate_support[3]), + .A2(plm_v4f_mgt_lstate_support[3]), + .A3(plm_v4f_mgt_lstate_support[3]) + ); + defparam plm_v4f_mgt_reg_rst_cnt_qxu_0_0_.INIT = 4'h2; + LUT1_L plm_v4f_mgt_reg_rst_cnt_qxu_0_0_ ( + .I0(plm_v4f_mgt_reg_rst_cnt[0]), + .LO(plm_v4f_mgt_reg_rst_cnt_qxu[0]) + ); + defparam plm_v4f_mgt_reg_rst_cnt_s_0_.INIT = 4'h1; + LUT1_L plm_v4f_mgt_reg_rst_cnt_s_0_ ( + .I0(plm_v4f_mgt_reg_rst_cnt_qxu[0]), + .LO(plm_v4f_mgt_reg_rst_cnt_s[0]) + ); + defparam plm_v4f_mgt_reg_rst_cnt_qxu_0_1_.INIT = 4'h2; + LUT1_L plm_v4f_mgt_reg_rst_cnt_qxu_0_1_ ( + .I0(plm_v4f_mgt_reg_rst_cnt[1]), + .LO(plm_v4f_mgt_reg_rst_cnt_qxu[1]) + ); + defparam plm_v4f_mgt_reg_rst_cnt_qxu_0_2_.INIT = 4'h2; + LUT1_L plm_v4f_mgt_reg_rst_cnt_qxu_0_2_ ( + .I0(plm_v4f_mgt_reg_rst_cnt[2]), + .LO(plm_v4f_mgt_reg_rst_cnt_qxu[2]) + ); + defparam plm_v4f_mgt_reg_rst_cnt_qxu_0_3_.INIT = 4'h2; + LUT1_L plm_v4f_mgt_reg_rst_cnt_qxu_0_3_ ( + .I0(plm_v4f_mgt_reg_rst_cnt[3]), + .LO(plm_v4f_mgt_reg_rst_cnt_qxu[3]) + ); + defparam plm_v4f_mgt_reg_rst_cnt_qxu_0_4_.INIT = 4'h2; + LUT1_L plm_v4f_mgt_reg_rst_cnt_qxu_0_4_ ( + .I0(plm_v4f_mgt_reg_rst_cnt[4]), + .LO(plm_v4f_mgt_reg_rst_cnt_qxu[4]) + ); + defparam plm_v4f_mgt_reg_rst_cnt_qxu_0_5_.INIT = 4'h2; + LUT1_L plm_v4f_mgt_reg_rst_cnt_qxu_0_5_ ( + .I0(plm_v4f_mgt_reg_rst_cnt[5]), + .LO(plm_v4f_mgt_reg_rst_cnt_qxu[5]) + ); + defparam plm_v4f_mgt_reg_rst_cnt_qxu_0_6_.INIT = 4'h2; + LUT1_L plm_v4f_mgt_reg_rst_cnt_qxu_0_6_ ( + .I0(plm_v4f_mgt_reg_rst_cnt[6]), + .LO(plm_v4f_mgt_reg_rst_cnt_qxu[6]) + ); + defparam plm_v4f_mgt_reg_rst_cnt_qxu_0_7_.INIT = 4'h2; + LUT1_L plm_v4f_mgt_reg_rst_cnt_qxu_0_7_ ( + .I0(plm_v4f_mgt_reg_rst_cnt[7]), + .LO(plm_v4f_mgt_reg_rst_cnt_qxu[7]) + ); + defparam plm_v4f_mgt_reg_rst_cnt_qxu_0_8_.INIT = 4'h2; + LUT1_L plm_v4f_mgt_reg_rst_cnt_qxu_0_8_ ( + .I0(plm_v4f_mgt_reg_rst_cnt[8]), + .LO(plm_v4f_mgt_reg_rst_cnt_qxu[8]) + ); + defparam plm_v4f_mgt_reg_rst_cnt_qxu_0_9_.INIT = 4'h2; + LUT1_L plm_v4f_mgt_reg_rst_cnt_qxu_0_9_ ( + .I0(plm_v4f_mgt_reg_rst_cnt[9]), + .LO(plm_v4f_mgt_reg_rst_cnt_qxu[9]) + ); + defparam plm_v4f_mgt_reg_rst_cnt_qxu_0_10_.INIT = 4'h2; + LUT1_L plm_v4f_mgt_reg_rst_cnt_qxu_0_10_ ( + .I0(plm_v4f_mgt_reg_rst_cnt[10]), + .LO(plm_v4f_mgt_reg_rst_cnt_qxu[10]) + ); + defparam plm_v4f_mgt_reg_rst_cnt_qxu_0_11_.INIT = 4'h2; + LUT1_L plm_v4f_mgt_reg_rst_cnt_qxu_0_11_ ( + .I0(plm_v4f_mgt_reg_rst_cnt[11]), + .LO(plm_v4f_mgt_reg_rst_cnt_qxu[11]) + ); + defparam plm_v4f_mgt_reg_rst_cnt_qxu_0_12_.INIT = 4'h2; + LUT1_L plm_v4f_mgt_reg_rst_cnt_qxu_0_12_ ( + .I0(plm_v4f_mgt_reg_rst_cnt[12]), + .LO(plm_v4f_mgt_reg_rst_cnt_qxu[12]) + ); + defparam plm_v4f_mgt_reg_rst_cnt_qxu_0_13_.INIT = 4'h2; + LUT1_L plm_v4f_mgt_reg_rst_cnt_qxu_0_13_ ( + .I0(plm_v4f_mgt_reg_rst_cnt[13]), + .LO(plm_v4f_mgt_reg_rst_cnt_qxu[13]) + ); + defparam plm_v4f_mgt_reg_rst_cnt_qxu_0_14_.INIT = 4'h2; + LUT1_L plm_v4f_mgt_reg_rst_cnt_qxu_0_14_ ( + .I0(plm_v4f_mgt_reg_rst_cnt[14]), + .LO(plm_v4f_mgt_reg_rst_cnt_qxu[14]) + ); + VCC plm_v4f_mgt_gt11_by4_VCC ( + .P(plm_v4f_mgt_gt11_by4_VCC_773) + ); + GND plm_v4f_mgt_gt11_by4_GND ( + .G(plm_v4f_mgt_gt11_by4_GND_772) + ); + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST.MCOMMA_32B_VALUE = 32'h00000283; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST.PCOMMA_32B_VALUE = 32'h0000017C; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST.RXCTRL1 = 12'h200; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST.RXCPSEL = "FALSE"; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST.RXDIGRX = "FALSE"; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST.RXLOOPFILT = 4'b1111; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST.RXPLLNDIVSEL = 20; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST.RXOUTDIV2SEL = 4; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST.TXPD = "FALSE"; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST.TXDAT_TAP_DAC = 5'b01010; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST.TXPOST_TAP_DAC = 5'b00000; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST.TXPOST_TAP_PD = "FALSE"; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST.TXDAT_PRDRV_DAC = 3'b111; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST.TXPOST_PRDRV_DAC = 3'b111; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST.TXSLEWRATE = "TRUE"; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST.TXASYNCDIVIDE = 2'b11; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST.TXTERMTRIM = 4'b1100; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST.TXAREFBIASSEL = "TRUE"; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST.TXHIGHSIGNALEN = "TRUE"; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST.TXCLKMODE = 4'b0000; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST.TXPRE_TAP_DAC = 5'b00000; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST.TXPRE_TAP_PD = "TRUE"; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST.TXPRE_PRDRV_DAC = 3'b111; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST.TXCTRL1 = 12'h200; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST.TXCPSEL = "FALSE"; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST.TXLOOPFILT = 4'b0101; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST.TXPLLNDIVSEL = 20; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST.TXOUTDIV2SEL = 4; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST.RXEQ = 64'h4000000000000000; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST.RXPD = "FALSE"; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST.RXDIGRESET = "FALSE"; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST.RXLKADJ = 5'b00000; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST.RXDCCOUPLE = "FALSE"; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST.RXCDRLOS = 6'b001100; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST.RXAFEEQ = 9'b000000111; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST.RXRCPADJ = 3'b010; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST.RXLB = "FALSE"; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST.RXCLKMODE = 6'b000001; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST.RXASYNCDIVIDE = 2'b11; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST.PMA_BIT_SLIP = "FALSE"; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST.PMACOREPWRENABLE = "TRUE"; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST.PMACLKENABLE = "TRUE"; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST.TXPHASESEL = "FALSE"; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST.BANDGAPSEL = "FALSE"; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST.TXABPMACLKSEL = "REFCLK1"; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST.RXPMACLKSEL = "REFCLK1"; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST.RXRECCLK1_USE_SYNC = "FALSE"; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST.TXOUTCLK1_USE_SYNC = "FALSE"; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST.TXCLK0_FORCE_PMACLK = "TRUE"; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST.RXCLK0_FORCE_PMACLK = "TRUE"; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST.TX_CLOCK_DIVIDER = 2'b11; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST.RX_CLOCK_DIVIDER = 2'b11; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST.TXCRCENABLE = "TRUE"; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST.TXCRCINITVAL = 32'hFFFFFFFF; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST.TXCRCSAMECLOCK = "TRUE"; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST.TXCRCINVERTGEN = "FALSE"; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST.TXCRCCLOCKDOUBLE = "FALSE"; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST.RXCRCINITVAL = 32'hFFFFFFFF; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST.RXCRCENABLE = "TRUE"; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST.RXCRCSAMECLOCK = "TRUE"; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST.RXCRCINVERTGEN = "FALSE"; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST.RXCRCCLOCKDOUBLE = "FALSE"; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST.VCODAC_INIT = 10'b0000000000; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST.SLOWDOWN_CAL = 2'b00; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST.LOOPCAL_WAIT = 2'b00; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST.FDET_HYS_CAL = 3'b010; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST.FDET_LCK_CAL = 3'b101; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST.FDET_HYS_SEL = 3'b001; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST.FDET_LCK_SEL = 3'b111; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST.VCO_CTRL_ENABLE = "TRUE"; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST.CYCLE_LIMIT_SEL = 2'b00; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST.RXVCODAC_INIT = 10'b0000000000; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST.RXSLOWDOWN_CAL = 2'b00; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST.RXLOOPCAL_WAIT = 2'b00; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST.RXFDET_HYS_CAL = 3'b010; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST.RXFDET_LCK_CAL = 3'b101; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST.RXFDET_HYS_SEL = 3'b001; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST.RXFDET_LCK_SEL = 3'b100; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST.RXVCO_CTRL_ENABLE = "TRUE"; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST.RXCYCLE_LIMIT_SEL = 2'b00; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST.RXFDCAL_CLOCK_DIVIDE = "NONE"; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST.TXFDCAL_CLOCK_DIVIDE = "NONE"; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST.BIASRESSEL = "FALSE"; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST.RXPDDTST = "TRUE"; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST.RXCMADJ = 2'b01; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST.RXBY_32 = "FALSE"; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST.REPEATER = "FALSE"; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST.ENABLE_DCDR = "FALSE"; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST.SAMPLE_8X = "FALSE"; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST.DCDR_FILTER = 3'b010; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST.RXUSRDIVISOR = 1; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST.COMMA_10B_MASK = 12'h3FF; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST.PCOMMA_DETECT = "TRUE"; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST.MCOMMA_DETECT = "TRUE"; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST.DEC_VALID_COMMA_ONLY = "TRUE"; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST.DEC_PCOMMA_DETECT = "TRUE"; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST.DEC_MCOMMA_DETECT = "TRUE"; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST.ALIGN_COMMA_WORD = 1; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST.CLK_COR_8B10B_DE = "TRUE"; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST.CLK_CORRECT_USE = "TRUE"; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST.CLK_COR_SEQ_LEN = 4; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST.CLK_COR_SEQ_DROP = "FALSE"; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST.CLK_COR_SEQ_2_USE = "FALSE"; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST.CLK_COR_MAX_LAT = 44; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST.CLK_COR_SEQ_2_MASK = 4'b1110; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST.CLK_COR_SEQ_2_4 = 11'b00000000000; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST.CLK_COR_SEQ_2_3 = 11'b00000000000; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST.CLK_COR_SEQ_2_2 = 11'b00000000000; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST.CLK_COR_SEQ_2_1 = 11'b00000000000; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST.RXDATA_SEL = 2'b00; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST.TXDATA_SEL = 2'b00; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST.CLK_COR_MIN_LAT = 36; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST.PCS_BIT_SLIP = "FALSE"; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST.DIGRX_FWDCLK = 2'b00; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST.DIGRX_SYNC_MODE = "FALSE"; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST.CLK_COR_SEQ_1_MASK = 4'b0000; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST.CLK_COR_SEQ_1_4 = 11'b00100011100; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST.CLK_COR_SEQ_1_3 = 11'b00100011100; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST.CLK_COR_SEQ_1_2 = 11'b00100011100; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST.CLK_COR_SEQ_1_1 = 11'b00110111100; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST.CCCB_ARBITRATOR_DISABLE = "FALSE"; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST.OPPOSITE_SELECT = "FALSE"; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST.POWER_ENABLE = "TRUE"; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST.CHAN_BOND_SEQ_2_MASK = 4'b0000; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST.CHAN_BOND_SEQ_2_4 = 11'b00000000000; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST.CHAN_BOND_SEQ_2_3 = 11'b00000000000; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST.CHAN_BOND_SEQ_2_2 = 11'b00000000000; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST.CHAN_BOND_SEQ_2_1 = 11'b00000000000; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST.TX_BUFFER_USE = "TRUE"; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST.RX_BUFFER_USE = "TRUE"; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST.CHAN_BOND_SEQ_LEN = 4; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST.CHAN_BOND_SEQ_2_USE = "FALSE"; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST.CHAN_BOND_ONE_SHOT = "FALSE"; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST.CHAN_BOND_MODE = "MASTER"; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST.CHAN_BOND_LIMIT = 6; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST.CHAN_BOND_SEQ_1_MASK = 4'b0000; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST.CHAN_BOND_SEQ_1_4 = 11'b00110111100; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST.CHAN_BOND_SEQ_1_3 = 11'b00001000101; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST.CHAN_BOND_SEQ_1_2 = 11'b00001000101; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST.CHAN_BOND_SEQ_1_1 = 11'b00001000101; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST.GT11_MODE = "A"; + GT11 plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST ( + .RXCRCPD(plm_v4f_mgt_gt11_by4_VCC_773), + .RXBUFERR(NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST_RXBUFERR_UNCONNECTED), + .TXSYNC(plm_v4f_mgt_reg_tx_sync_756), + .POWERDOWN(plm_v4f_mgt_gt11_by4_GND_772), + .TXUSRCLK2(plm_v4f_mgt_mgtdiv2_clk), + .ENPCOMMAALIGN(plm_v4f_mgt_gt11_by4_VCC_773), + .RXPOLARITY(plm_rx0_polarity), + .ENMCOMMAALIGN(plm_v4f_mgt_gt11_by4_VCC_773), + .TXBUFERR(NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST_TXBUFERR_UNCONNECTED), + .TXCRCPD(plm_v4f_mgt_gt11_by4_VCC_773), + .RXSIGDET(plm_v4f_mgt_rx0_sigdet_n_async), + .TXCLKSTABLE(plm_v4f_mgt_gt11_by4_VCC_773), + .RXUSRCLK2(plm_v4f_mgt_mgtdiv2_clk), + .TXPOLARITY(plm_v4f_mgt_gt11_by4_GND_772), + .DWE(plm_v4f_mgt_gt0_dwe), + .RXREALIGN(NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST_RXREALIGN_UNCONNECTED), + .TXGEARBOX64B66BUSE(plm_v4f_mgt_gt11_by4_GND_772), + .RXCYCLELIMIT(NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST_RXCYCLELIMIT_UNCONNECTED), + .RXRESET(plm_v4f_mgt_reg_rx0_pcs_init_755), + .TXCYCLELIMIT(NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST_TXCYCLELIMIT_UNCONNECTED), + .TXCALFAIL(NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST_TXCALFAIL_UNCONNECTED), + .RXUSRCLK(plm_v4f_mgt_mgtdiv2_clk), + .RXDEC64B66BUSE(plm_v4f_mgt_gt11_by4_GND_772), + .RXPCSHCLKOUT(NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST_RXPCSHCLKOUT_UNCONNECTED), + .TXPCSHCLKOUT(NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST_TXPCSHCLKOUT_UNCONNECTED), + .RXCOMMADETUSE(plm_v4f_mgt_gt11_by4_VCC_773), + .DCLK(plm_v4f_mgt_cal_clk), + .TXCRCINIT(plm_v4f_mgt_gt11_by4_GND_772), + .TXUSRCLK(plm_v4f_mgt_mgtdiv2_clk), + .RXCALFAIL(NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST_RXCALFAIL_UNCONNECTED), + .RXPMARESET(plm_v4f_mgt_reg_pma_768), + .RX1N(pci_exp_rxn_6086[0]), + .RX1P(pci_exp_rxp_6085[0]), + .TXRESET(plm_v4f_mgt_reg_tx_pcs_init_758), + .RXSLIDE(plm_v4f_mgt_gt11_by4_GND_772), + .TXPMARESET(plm_v4f_mgt_reg_pma_768), + .TXCRCINTCLK(plm_v4f_mgt_gt11_by4_GND_772), + .RXCRCINIT(plm_v4f_mgt_gt11_by4_GND_772), + .RXDEC8B10BUSE(plm_v4f_mgt_gt11_by4_VCC_773), + .RXCLKSTABLE(plm_v4f_mgt_gt11_by4_VCC_773), + .RXLOCK(plm_v4f_mgt_pma_rxlock0), + .TXCRCDATAVALID(plm_v4f_mgt_gt11_by4_GND_772), + .GREFCLK(plm_v4f_mgt_mgtdiv2_clk), + .ENCHANSYNC(plm_v4f_mgt_gt11_by4_VCC_773), + .DEN(plm_v4f_mgt_gt0_den), + .RXMCLK(NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST_RXMCLK_UNCONNECTED), + .RXCOMMADET(NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST_RXCOMMADET_UNCONNECTED), + .TXOUTCLK1(NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST_TXOUTCLK1_UNCONNECTED), + .TXOUTCLK2(NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST_TXOUTCLK2_UNCONNECTED), + .RXCRCRESET(plm_v4f_mgt_gt11_by4_VCC_773), + .RXCRCCLK(plm_v4f_mgt_gt11_by4_GND_772), + .TXENC64B66BUSE(plm_v4f_mgt_gt11_by4_GND_772), + .TXINHIBIT(plm_v4f_mgt_gt11_by4_GND_772), + .RXRECCLK1(NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST_RXRECCLK1_UNCONNECTED), + .RXRECCLK2(NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST_RXRECCLK2_UNCONNECTED), + .TXLOCK(plm_v4f_mgt_pma_txlock0), + .TXCRCRESET(plm_v4f_mgt_gt11_by4_VCC_773), + .RXDESCRAM64B66BUSE(plm_v4f_mgt_gt11_by4_GND_772), + .RXBLOCKSYNC64B66BUSE(plm_v4f_mgt_gt11_by4_GND_772), + .RXIGNOREBTF(plm_v4f_mgt_gt11_by4_GND_772), + .TXCRCCLK(plm_v4f_mgt_gt11_by4_GND_772), + .RXCRCDATAVALID(plm_v4f_mgt_gt11_by4_GND_772), + .TXSCRAM64B66BUSE(plm_v4f_mgt_gt11_by4_GND_772), + .RXCRCINTCLK(plm_v4f_mgt_gt11_by4_GND_772), + .RXSYNC(plm_v4f_mgt_gt11_by4_GND_772), + .DRDY(plm_v4f_mgt_gt0_drdy), + .TXENC8B10BUSE(plm_v4f_mgt_gt11_by4_VCC_773), + .REFCLK1(sys_clkz), + .TXENOOB(plm_v4f_mgt_reg_tee0_dlyline[23]), + .REFCLK2(plm_v4f_mgt_gt11_by4_GND_772), + .TX1N(pci_exp_txn_6084[0]), + .TX1P(pci_exp_txp_6083[0]), + .RXSTATUS({plm_v4f_mgt_rx0_rxstatus[5], NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST_RXSTATUS_4__UNCONNECTED, +NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST_RXSTATUS_3__UNCONNECTED, NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST_RXSTATUS_2__UNCONNECTED, +NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST_RXSTATUS_1__UNCONNECTED, NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST_RXSTATUS_0__UNCONNECTED}), + .RXNOTINTABLE({NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST_RXNOTINTABLE_7__UNCONNECTED, +NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST_RXNOTINTABLE_6__UNCONNECTED, NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST_RXNOTINTABLE_5__UNCONNECTED, +NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST_RXNOTINTABLE_4__UNCONNECTED, plm_v4f_mgt_wrx0_ntable[3], plm_v4f_mgt_wrx0_ntable[2], +plm_v4f_mgt_wrx0_ntable[1], plm_v4f_mgt_wrx0_ntable[0]}), + .DADDR({plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_VCC_773, plm_v4f_mgt_gt0_daddr[5], plm_v4f_mgt_gt0_daddr[4], plm_v4f_mgt_gt0_daddr[3], +plm_v4f_mgt_gt0_daddr[2], plm_v4f_mgt_gt0_daddr[1], plm_v4f_mgt_gt0_daddr[4]}), + .TXDATAWIDTH({plm_v4f_mgt_gt11_by4_VCC_773, plm_v4f_mgt_gt11_by4_GND_772}), + .RXCRCOUT({NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST_RXCRCOUT_31__UNCONNECTED, +NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST_RXCRCOUT_30__UNCONNECTED, NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST_RXCRCOUT_29__UNCONNECTED, +NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST_RXCRCOUT_28__UNCONNECTED, NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST_RXCRCOUT_27__UNCONNECTED, +NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST_RXCRCOUT_26__UNCONNECTED, NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST_RXCRCOUT_25__UNCONNECTED, +NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST_RXCRCOUT_24__UNCONNECTED, NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST_RXCRCOUT_23__UNCONNECTED, +NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST_RXCRCOUT_22__UNCONNECTED, NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST_RXCRCOUT_21__UNCONNECTED, +NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST_RXCRCOUT_20__UNCONNECTED, NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST_RXCRCOUT_19__UNCONNECTED, +NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST_RXCRCOUT_18__UNCONNECTED, NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST_RXCRCOUT_17__UNCONNECTED, +NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST_RXCRCOUT_16__UNCONNECTED, NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST_RXCRCOUT_15__UNCONNECTED, +NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST_RXCRCOUT_14__UNCONNECTED, NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST_RXCRCOUT_13__UNCONNECTED, +NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST_RXCRCOUT_12__UNCONNECTED, NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST_RXCRCOUT_11__UNCONNECTED, +NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST_RXCRCOUT_10__UNCONNECTED, NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST_RXCRCOUT_9__UNCONNECTED, +NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST_RXCRCOUT_8__UNCONNECTED, NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST_RXCRCOUT_7__UNCONNECTED, +NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST_RXCRCOUT_6__UNCONNECTED, NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST_RXCRCOUT_5__UNCONNECTED, +NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST_RXCRCOUT_4__UNCONNECTED, NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST_RXCRCOUT_3__UNCONNECTED, +NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST_RXCRCOUT_2__UNCONNECTED, NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST_RXCRCOUT_1__UNCONNECTED, +NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST_RXCRCOUT_0__UNCONNECTED}), + .TXINTDATAWIDTH({plm_v4f_mgt_gt11_by4_VCC_773, plm_v4f_mgt_gt11_by4_VCC_773}), + .DI({plm_v4f_mgt_gt0_do[15], plm_v4f_mgt_gt0_do[14], plm_v4f_mgt_gt0_do[13], plm_v4f_mgt_gt0_do[12], plm_v4f_mgt_gt0_do[11], +plm_v4f_mgt_gt0_do[10], plm_v4f_mgt_gt0_do[9], plm_v4f_mgt_gt0_do[8], plm_v4f_mgt_gt0_do[7], plm_v4f_mgt_gt0_do[6], plm_v4f_mgt_gt0_do[5], +plm_v4f_mgt_gt0_do[4], plm_v4f_mgt_gt0_do[3], plm_v4f_mgt_gt0_do[2], plm_v4f_mgt_gt0_do[1], plm_v4f_mgt_gt0_do[0]}), + .DO({plm_v4f_mgt_gt0_di[15], plm_v4f_mgt_gt0_di[14], plm_v4f_mgt_gt0_di[13], plm_v4f_mgt_gt0_di[12], plm_v4f_mgt_gt0_di[11], +plm_v4f_mgt_gt0_di[10], plm_v4f_mgt_gt0_di[9], plm_v4f_mgt_gt0_di[8], plm_v4f_mgt_gt0_di[7], plm_v4f_mgt_gt0_di[6], plm_v4f_mgt_gt0_di[5], +plm_v4f_mgt_gt0_di[4], plm_v4f_mgt_gt0_di[3], plm_v4f_mgt_gt0_di[2], plm_v4f_mgt_gt0_di[1], plm_v4f_mgt_gt0_di[0]}), + .TXCRCOUT({NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST_TXCRCOUT_31__UNCONNECTED, +NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST_TXCRCOUT_30__UNCONNECTED, NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST_TXCRCOUT_29__UNCONNECTED, +NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST_TXCRCOUT_28__UNCONNECTED, NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST_TXCRCOUT_27__UNCONNECTED, +NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST_TXCRCOUT_26__UNCONNECTED, NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST_TXCRCOUT_25__UNCONNECTED, +NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST_TXCRCOUT_24__UNCONNECTED, NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST_TXCRCOUT_23__UNCONNECTED, +NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST_TXCRCOUT_22__UNCONNECTED, NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST_TXCRCOUT_21__UNCONNECTED, +NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST_TXCRCOUT_20__UNCONNECTED, NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST_TXCRCOUT_19__UNCONNECTED, +NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST_TXCRCOUT_18__UNCONNECTED, NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST_TXCRCOUT_17__UNCONNECTED, +NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST_TXCRCOUT_16__UNCONNECTED, NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST_TXCRCOUT_15__UNCONNECTED, +NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST_TXCRCOUT_14__UNCONNECTED, NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST_TXCRCOUT_13__UNCONNECTED, +NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST_TXCRCOUT_12__UNCONNECTED, NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST_TXCRCOUT_11__UNCONNECTED, +NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST_TXCRCOUT_10__UNCONNECTED, NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST_TXCRCOUT_9__UNCONNECTED, +NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST_TXCRCOUT_8__UNCONNECTED, NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST_TXCRCOUT_7__UNCONNECTED, +NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST_TXCRCOUT_6__UNCONNECTED, NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST_TXCRCOUT_5__UNCONNECTED, +NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST_TXCRCOUT_4__UNCONNECTED, NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST_TXCRCOUT_3__UNCONNECTED, +NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST_TXCRCOUT_2__UNCONNECTED, NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST_TXCRCOUT_1__UNCONNECTED, +NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST_TXCRCOUT_0__UNCONNECTED}), + .COMBUSIN({plm_v4f_mgt_gt11_by4_COMBUSOUT_BLK2[15], plm_v4f_mgt_gt11_by4_COMBUSOUT_BLK2[14], plm_v4f_mgt_gt11_by4_COMBUSOUT_BLK2[13], +plm_v4f_mgt_gt11_by4_COMBUSOUT_BLK2[12], plm_v4f_mgt_gt11_by4_COMBUSOUT_BLK2[11], plm_v4f_mgt_gt11_by4_COMBUSOUT_BLK2[10], +plm_v4f_mgt_gt11_by4_COMBUSOUT_BLK2[9], plm_v4f_mgt_gt11_by4_COMBUSOUT_BLK2[8], plm_v4f_mgt_gt11_by4_COMBUSOUT_BLK2[7], +plm_v4f_mgt_gt11_by4_COMBUSOUT_BLK2[6], plm_v4f_mgt_gt11_by4_COMBUSOUT_BLK2[5], plm_v4f_mgt_gt11_by4_COMBUSOUT_BLK2[4], +plm_v4f_mgt_gt11_by4_COMBUSOUT_BLK2[3], plm_v4f_mgt_gt11_by4_COMBUSOUT_BLK2[2], plm_v4f_mgt_gt11_by4_COMBUSOUT_BLK2[1], +plm_v4f_mgt_gt11_by4_COMBUSOUT_BLK2[0]}), + .COMBUSOUT({plm_v4f_mgt_gt11_by4_COMBUSOUT[15], plm_v4f_mgt_gt11_by4_COMBUSOUT[14], plm_v4f_mgt_gt11_by4_COMBUSOUT[13], +plm_v4f_mgt_gt11_by4_COMBUSOUT[12], plm_v4f_mgt_gt11_by4_COMBUSOUT[11], plm_v4f_mgt_gt11_by4_COMBUSOUT[10], plm_v4f_mgt_gt11_by4_COMBUSOUT[9], +plm_v4f_mgt_gt11_by4_COMBUSOUT[8], plm_v4f_mgt_gt11_by4_COMBUSOUT[7], plm_v4f_mgt_gt11_by4_COMBUSOUT[6], plm_v4f_mgt_gt11_by4_COMBUSOUT[5], +plm_v4f_mgt_gt11_by4_COMBUSOUT[4], plm_v4f_mgt_gt11_by4_COMBUSOUT[3], plm_v4f_mgt_gt11_by4_COMBUSOUT[2], plm_v4f_mgt_gt11_by4_COMBUSOUT[1], +plm_v4f_mgt_gt11_by4_COMBUSOUT[0]}), + .RXDATA({NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST_RXDATA_63__UNCONNECTED, NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST_RXDATA_62__UNCONNECTED, +NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST_RXDATA_61__UNCONNECTED, NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST_RXDATA_60__UNCONNECTED, +NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST_RXDATA_59__UNCONNECTED, NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST_RXDATA_58__UNCONNECTED, +NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST_RXDATA_57__UNCONNECTED, NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST_RXDATA_56__UNCONNECTED, +NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST_RXDATA_55__UNCONNECTED, NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST_RXDATA_54__UNCONNECTED, +NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST_RXDATA_53__UNCONNECTED, NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST_RXDATA_52__UNCONNECTED, +NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST_RXDATA_51__UNCONNECTED, NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST_RXDATA_50__UNCONNECTED, +NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST_RXDATA_49__UNCONNECTED, NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST_RXDATA_48__UNCONNECTED, +NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST_RXDATA_47__UNCONNECTED, NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST_RXDATA_46__UNCONNECTED, +NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST_RXDATA_45__UNCONNECTED, NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST_RXDATA_44__UNCONNECTED, +NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST_RXDATA_43__UNCONNECTED, NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST_RXDATA_42__UNCONNECTED, +NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST_RXDATA_41__UNCONNECTED, NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST_RXDATA_40__UNCONNECTED, +NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST_RXDATA_39__UNCONNECTED, NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST_RXDATA_38__UNCONNECTED, +NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST_RXDATA_37__UNCONNECTED, NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST_RXDATA_36__UNCONNECTED, +NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST_RXDATA_35__UNCONNECTED, NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST_RXDATA_34__UNCONNECTED, +NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST_RXDATA_33__UNCONNECTED, NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST_RXDATA_32__UNCONNECTED, +plm_v4f_mgt_wrx0_data[31], plm_v4f_mgt_wrx0_data[30], plm_v4f_mgt_wrx0_data[29], plm_v4f_mgt_wrx0_data[28], plm_v4f_mgt_wrx0_data[27], +plm_v4f_mgt_wrx0_data[26], plm_v4f_mgt_wrx0_data[25], plm_v4f_mgt_wrx0_data[24], plm_v4f_mgt_wrx0_data[23], plm_v4f_mgt_wrx0_data[22], +plm_v4f_mgt_wrx0_data[21], plm_v4f_mgt_wrx0_data[20], plm_v4f_mgt_wrx0_data[19], plm_v4f_mgt_wrx0_data[18], plm_v4f_mgt_wrx0_data[17], +plm_v4f_mgt_wrx0_data[16], plm_v4f_mgt_wrx0_data[15], plm_v4f_mgt_wrx0_data[14], plm_v4f_mgt_wrx0_data[13], plm_v4f_mgt_wrx0_data[12], +plm_v4f_mgt_wrx0_data[11], plm_v4f_mgt_wrx0_data[10], plm_v4f_mgt_wrx0_data[9], plm_v4f_mgt_wrx0_data[8], plm_v4f_mgt_wrx0_data[7], +plm_v4f_mgt_wrx0_data[6], plm_v4f_mgt_wrx0_data[5], plm_v4f_mgt_wrx0_data[4], plm_v4f_mgt_wrx0_data[3], plm_v4f_mgt_wrx0_data[2], +plm_v4f_mgt_wrx0_data[1], plm_v4f_mgt_wrx0_data[0]}), + .TXRUNDISP({NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST_TXRUNDISP_7__UNCONNECTED, +NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST_TXRUNDISP_6__UNCONNECTED, NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST_TXRUNDISP_5__UNCONNECTED, +NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST_TXRUNDISP_4__UNCONNECTED, NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST_TXRUNDISP_3__UNCONNECTED, +NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST_TXRUNDISP_2__UNCONNECTED, NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST_TXRUNDISP_1__UNCONNECTED, +NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST_TXRUNDISP_0__UNCONNECTED}), + .RXINTDATAWIDTH({plm_v4f_mgt_gt11_by4_VCC_773, plm_v4f_mgt_gt11_by4_VCC_773}), + .RXDATAWIDTH({plm_v4f_mgt_gt11_by4_VCC_773, plm_v4f_mgt_gt11_by4_GND_772}), + .RXLOSSOFSYNC({NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST_RXLOSSOFSYNC_1__UNCONNECTED, +NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST_RXLOSSOFSYNC_0__UNCONNECTED}), + .RXRUNDISP({NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST_RXRUNDISP_7__UNCONNECTED, +NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST_RXRUNDISP_6__UNCONNECTED, NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST_RXRUNDISP_5__UNCONNECTED, +NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST_RXRUNDISP_4__UNCONNECTED, plm_v4f_mgt_wrx0_run_disp[3], plm_v4f_mgt_wrx0_run_disp[2], +plm_v4f_mgt_wrx0_run_disp[1], plm_v4f_mgt_wrx0_run_disp[0]}), + .TXDATA({plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, +plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, +plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, +plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, +plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, +plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, +plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, plm_tx0_data[7], plm_tx0_data[6], plm_tx0_data[5], +plm_tx0_data[4], plm_tx0_data[3], plm_tx0_data[2], plm_tx0_data[1], plm_tx0_data[0], plm_tx0_data[15], plm_tx0_data[14], plm_tx0_data[13], +plm_tx0_data[12], plm_tx0_data[11], plm_tx0_data[10], plm_tx0_data[9], plm_tx0_data[8], plm_v4f_mgt_dtx0_data[7], plm_v4f_mgt_dtx0_data[6], +plm_v4f_mgt_dtx0_data[5], plm_v4f_mgt_dtx0_data[4], plm_v4f_mgt_dtx0_data[3], plm_v4f_mgt_dtx0_data[2], plm_v4f_mgt_dtx0_data[1], +plm_v4f_mgt_dtx0_data[0], plm_v4f_mgt_dtx0_data[15], plm_v4f_mgt_dtx0_data[14], plm_v4f_mgt_dtx0_data[13], plm_v4f_mgt_dtx0_data[12], +plm_v4f_mgt_dtx0_data[11], plm_v4f_mgt_dtx0_data[10], plm_v4f_mgt_dtx0_data[9], plm_v4f_mgt_dtx0_data[8]}), + .TXCHARDISPVAL({plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, +plm_GND_702, plm_GND_702, plm_v4f_mgt_dtx0_char_disp_val[0], plm_v4f_mgt_dtx0_char_disp_val[1]}), + .LOOPBACK({plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772}), + .CHBONDI({plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, +plm_v4f_mgt_gt11_by4_GND_772}), + .TXCRCDATAWIDTH({plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772}), + .CHBONDO({plm_v4f_mgt_gt11_by4_CHBONDO_2[4], plm_v4f_mgt_gt11_by4_CHBONDO_2[3], plm_v4f_mgt_gt11_by4_CHBONDO_2[2], +plm_v4f_mgt_gt11_by4_CHBONDO_2[1], plm_v4f_mgt_gt11_by4_CHBONDO_2[0]}), + .TXCHARISK({plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, +plm_tx0_char_is_k[0], plm_tx0_char_is_k[1], plm_v4f_mgt_dtx0_char_is_k[0], plm_v4f_mgt_dtx0_char_is_k[1]}), + .TXBYPASS8B10B({plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, +plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772}), + .RXCRCIN({plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, +plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, +plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, +plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, +plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, +plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, +plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, +plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, +plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, +plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, +plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, +plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, +plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772}) +, + .RXCHARISK({NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST_RXCHARISK_7__UNCONNECTED, +NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST_RXCHARISK_6__UNCONNECTED, NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST_RXCHARISK_5__UNCONNECTED, +NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST_RXCHARISK_4__UNCONNECTED, plm_v4f_mgt_wrx0_char_is_k[3], plm_v4f_mgt_wrx0_char_is_k[2], +plm_v4f_mgt_wrx0_char_is_k[1], plm_v4f_mgt_wrx0_char_is_k[0]}), + .TXCHARDISPMODE({plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, +plm_GND_702, plm_GND_702, plm_v4f_mgt_dtx0_char_disp_mode[0], plm_v4f_mgt_dtx0_char_disp_mode[1]}), + .RXCRCDATAWIDTH({plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772}), + .RXDISPERR({NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST_RXDISPERR_7__UNCONNECTED, +NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST_RXDISPERR_6__UNCONNECTED, NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST_RXDISPERR_5__UNCONNECTED, +NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST_RXDISPERR_4__UNCONNECTED, plm_v4f_mgt_wrx0_disp_err[3], plm_v4f_mgt_wrx0_disp_err[2], +plm_v4f_mgt_wrx0_disp_err[1], plm_v4f_mgt_wrx0_disp_err[0]}), + .RXCHARISCOMMA({NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST_RXCHARISCOMMA_7__UNCONNECTED, +NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST_RXCHARISCOMMA_6__UNCONNECTED, NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST_RXCHARISCOMMA_5__UNCONNECTED, +NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST_RXCHARISCOMMA_4__UNCONNECTED, NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST_RXCHARISCOMMA_3__UNCONNECTED, +NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST_RXCHARISCOMMA_2__UNCONNECTED, NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST_RXCHARISCOMMA_1__UNCONNECTED, +NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST_RXCHARISCOMMA_0__UNCONNECTED}), + .TXCRCIN({plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, +plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, +plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, +plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, +plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, +plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, +plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, +plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, +plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, +plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, +plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, +plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, +plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772}) +, + .TXKERR({NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST_TXKERR_7__UNCONNECTED, NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST_TXKERR_6__UNCONNECTED, +NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST_TXKERR_5__UNCONNECTED, NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST_TXKERR_4__UNCONNECTED, +NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST_TXKERR_3__UNCONNECTED, NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST_TXKERR_2__UNCONNECTED, +NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST_TXKERR_1__UNCONNECTED, NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST_TXKERR_0__UNCONNECTED}) + ); + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST2.MCOMMA_32B_VALUE = 32'h00000283; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST2.PCOMMA_32B_VALUE = 32'h0000017C; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST2.RXCTRL1 = 12'h200; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST2.RXCPSEL = "FALSE"; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST2.RXDIGRX = "FALSE"; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST2.RXLOOPFILT = 4'b1111; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST2.RXPLLNDIVSEL = 20; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST2.RXOUTDIV2SEL = 4; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST2.TXPD = "FALSE"; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST2.TXDAT_TAP_DAC = 5'b01010; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST2.TXPOST_TAP_DAC = 5'b00000; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST2.TXPOST_TAP_PD = "FALSE"; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST2.TXDAT_PRDRV_DAC = 3'b111; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST2.TXPOST_PRDRV_DAC = 3'b111; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST2.TXSLEWRATE = "TRUE"; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST2.TXASYNCDIVIDE = 2'b11; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST2.TXTERMTRIM = 4'b1100; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST2.TXAREFBIASSEL = "TRUE"; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST2.TXHIGHSIGNALEN = "TRUE"; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST2.TXCLKMODE = 4'b0000; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST2.TXPRE_TAP_DAC = 5'b00000; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST2.TXPRE_TAP_PD = "TRUE"; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST2.TXPRE_PRDRV_DAC = 3'b111; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST2.TXCTRL1 = 12'h200; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST2.TXCPSEL = "FALSE"; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST2.TXLOOPFILT = 4'b0101; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST2.TXPLLNDIVSEL = 20; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST2.TXOUTDIV2SEL = 4; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST2.RXEQ = 64'h4000000000000000; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST2.RXPD = "FALSE"; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST2.RXDIGRESET = "FALSE"; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST2.RXLKADJ = 5'b00000; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST2.RXDCCOUPLE = "FALSE"; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST2.RXCDRLOS = 6'b001100; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST2.RXAFEEQ = 9'b000000111; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST2.RXRCPADJ = 3'b010; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST2.RXLB = "FALSE"; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST2.RXCLKMODE = 6'b000001; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST2.RXASYNCDIVIDE = 2'b11; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST2.PMA_BIT_SLIP = "FALSE"; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST2.PMACOREPWRENABLE = "TRUE"; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST2.PMACLKENABLE = "TRUE"; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST2.TXPHASESEL = "FALSE"; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST2.BANDGAPSEL = "FALSE"; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST2.TXABPMACLKSEL = "REFCLK1"; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST2.RXPMACLKSEL = "REFCLK1"; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST2.RXRECCLK1_USE_SYNC = "FALSE"; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST2.TXOUTCLK1_USE_SYNC = "FALSE"; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST2.TXCLK0_FORCE_PMACLK = "TRUE"; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST2.RXCLK0_FORCE_PMACLK = "TRUE"; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST2.TX_CLOCK_DIVIDER = 2'b11; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST2.RX_CLOCK_DIVIDER = 2'b11; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST2.TXCRCENABLE = "TRUE"; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST2.TXCRCINITVAL = 32'hFFFFFFFF; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST2.TXCRCSAMECLOCK = "TRUE"; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST2.TXCRCINVERTGEN = "FALSE"; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST2.TXCRCCLOCKDOUBLE = "FALSE"; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST2.RXCRCINITVAL = 32'hFFFFFFFF; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST2.RXCRCENABLE = "TRUE"; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST2.RXCRCSAMECLOCK = "TRUE"; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST2.RXCRCINVERTGEN = "FALSE"; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST2.RXCRCCLOCKDOUBLE = "FALSE"; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST2.VCODAC_INIT = 10'b0000000000; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST2.SLOWDOWN_CAL = 2'b00; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST2.LOOPCAL_WAIT = 2'b00; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST2.FDET_HYS_CAL = 3'b010; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST2.FDET_LCK_CAL = 3'b101; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST2.FDET_HYS_SEL = 3'b001; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST2.FDET_LCK_SEL = 3'b111; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST2.VCO_CTRL_ENABLE = "TRUE"; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST2.CYCLE_LIMIT_SEL = 2'b00; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST2.RXVCODAC_INIT = 10'b0000000000; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST2.RXSLOWDOWN_CAL = 2'b00; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST2.RXLOOPCAL_WAIT = 2'b00; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST2.RXFDET_HYS_CAL = 3'b010; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST2.RXFDET_LCK_CAL = 3'b101; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST2.RXFDET_HYS_SEL = 3'b001; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST2.RXFDET_LCK_SEL = 3'b100; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST2.RXVCO_CTRL_ENABLE = "TRUE"; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST2.RXCYCLE_LIMIT_SEL = 2'b00; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST2.RXFDCAL_CLOCK_DIVIDE = "NONE"; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST2.TXFDCAL_CLOCK_DIVIDE = "NONE"; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST2.BIASRESSEL = "FALSE"; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST2.RXPDDTST = "TRUE"; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST2.RXCMADJ = 2'b01; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST2.RXBY_32 = "FALSE"; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST2.REPEATER = "FALSE"; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST2.ENABLE_DCDR = "FALSE"; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST2.SAMPLE_8X = "FALSE"; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST2.DCDR_FILTER = 3'b010; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST2.RXUSRDIVISOR = 1; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST2.COMMA_10B_MASK = 12'h3FF; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST2.PCOMMA_DETECT = "TRUE"; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST2.MCOMMA_DETECT = "TRUE"; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST2.DEC_VALID_COMMA_ONLY = "TRUE"; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST2.DEC_PCOMMA_DETECT = "TRUE"; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST2.DEC_MCOMMA_DETECT = "TRUE"; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST2.ALIGN_COMMA_WORD = 1; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST2.CLK_COR_8B10B_DE = "TRUE"; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST2.CLK_CORRECT_USE = "TRUE"; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST2.CLK_COR_SEQ_LEN = 4; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST2.CLK_COR_SEQ_DROP = "FALSE"; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST2.CLK_COR_SEQ_2_USE = "FALSE"; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST2.CLK_COR_MAX_LAT = 44; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST2.CLK_COR_SEQ_2_MASK = 4'b1110; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST2.CLK_COR_SEQ_2_4 = 11'b00000000000; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST2.CLK_COR_SEQ_2_3 = 11'b00000000000; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST2.CLK_COR_SEQ_2_2 = 11'b00000000000; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST2.CLK_COR_SEQ_2_1 = 11'b00000000000; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST2.RXDATA_SEL = 2'b00; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST2.TXDATA_SEL = 2'b00; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST2.CLK_COR_MIN_LAT = 36; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST2.PCS_BIT_SLIP = "FALSE"; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST2.DIGRX_FWDCLK = 2'b00; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST2.DIGRX_SYNC_MODE = "FALSE"; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST2.CLK_COR_SEQ_1_MASK = 4'b0000; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST2.CLK_COR_SEQ_1_4 = 11'b00100011100; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST2.CLK_COR_SEQ_1_3 = 11'b00100011100; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST2.CLK_COR_SEQ_1_2 = 11'b00100011100; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST2.CLK_COR_SEQ_1_1 = 11'b00110111100; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST2.CCCB_ARBITRATOR_DISABLE = "FALSE"; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST2.OPPOSITE_SELECT = "FALSE"; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST2.POWER_ENABLE = "TRUE"; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST2.CHAN_BOND_SEQ_2_MASK = 4'b0000; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST2.CHAN_BOND_SEQ_2_4 = 11'b00000000000; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST2.CHAN_BOND_SEQ_2_3 = 11'b00000000000; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST2.CHAN_BOND_SEQ_2_2 = 11'b00000000000; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST2.CHAN_BOND_SEQ_2_1 = 11'b00000000000; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST2.TX_BUFFER_USE = "TRUE"; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST2.RX_BUFFER_USE = "TRUE"; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST2.CHAN_BOND_SEQ_LEN = 4; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST2.CHAN_BOND_SEQ_2_USE = "FALSE"; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST2.CHAN_BOND_ONE_SHOT = "FALSE"; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST2.CHAN_BOND_MODE = "SLAVE_1_HOP"; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST2.CHAN_BOND_LIMIT = 6; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST2.CHAN_BOND_SEQ_1_MASK = 4'b0000; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST2.CHAN_BOND_SEQ_1_4 = 11'b00110111100; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST2.CHAN_BOND_SEQ_1_3 = 11'b00001000101; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST2.CHAN_BOND_SEQ_1_2 = 11'b00001000101; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST2.CHAN_BOND_SEQ_1_1 = 11'b00001000101; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST2.GT11_MODE = "B"; + GT11 plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST2 ( + .RXCRCPD(plm_v4f_mgt_gt11_by4_VCC_773), + .RXBUFERR(NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST2_RXBUFERR_UNCONNECTED), + .TXSYNC(plm_v4f_mgt_reg_tx_sync_756), + .POWERDOWN(plm_v4f_mgt_gt11_by4_GND_772), + .TXUSRCLK2(plm_v4f_mgt_mgtdiv2_clk), + .ENPCOMMAALIGN(plm_v4f_mgt_gt11_by4_VCC_773), + .RXPOLARITY(plm_rx1_polarity), + .ENMCOMMAALIGN(plm_v4f_mgt_gt11_by4_VCC_773), + .TXBUFERR(NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST2_TXBUFERR_UNCONNECTED), + .TXCRCPD(plm_v4f_mgt_gt11_by4_VCC_773), + .RXSIGDET(plm_v4f_mgt_rx1_sigdet_n_async), + .TXCLKSTABLE(plm_v4f_mgt_gt11_by4_VCC_773), + .RXUSRCLK2(plm_v4f_mgt_mgtdiv2_clk), + .TXPOLARITY(plm_v4f_mgt_gt11_by4_GND_772), + .DWE(plm_v4f_mgt_gt1_dwe), + .RXREALIGN(NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST2_RXREALIGN_UNCONNECTED), + .TXGEARBOX64B66BUSE(plm_v4f_mgt_gt11_by4_GND_772), + .RXCYCLELIMIT(NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST2_RXCYCLELIMIT_UNCONNECTED), + .RXRESET(plm_v4f_mgt_reg_rx1_pcs_init_754), + .TXCYCLELIMIT(NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST2_TXCYCLELIMIT_UNCONNECTED), + .TXCALFAIL(NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST2_TXCALFAIL_UNCONNECTED), + .RXUSRCLK(plm_v4f_mgt_mgtdiv2_clk), + .RXDEC64B66BUSE(plm_v4f_mgt_gt11_by4_GND_772), + .RXPCSHCLKOUT(NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST2_RXPCSHCLKOUT_UNCONNECTED), + .TXPCSHCLKOUT(NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST2_TXPCSHCLKOUT_UNCONNECTED), + .RXCOMMADETUSE(plm_v4f_mgt_gt11_by4_VCC_773), + .DCLK(plm_v4f_mgt_cal_clk), + .TXCRCINIT(plm_v4f_mgt_gt11_by4_GND_772), + .TXUSRCLK(plm_v4f_mgt_mgtdiv2_clk), + .RXCALFAIL(NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST2_RXCALFAIL_UNCONNECTED), + .RXPMARESET(plm_v4f_mgt_reg_pma_768), + .RX1N(pci_exp_rxn_6086[1]), + .RX1P(pci_exp_rxp_6085[1]), + .TXRESET(plm_v4f_mgt_reg_tx_pcs_init_758), + .RXSLIDE(plm_v4f_mgt_gt11_by4_GND_772), + .TXPMARESET(plm_v4f_mgt_reg_pma_768), + .TXCRCINTCLK(plm_v4f_mgt_gt11_by4_GND_772), + .RXCRCINIT(plm_v4f_mgt_gt11_by4_GND_772), + .RXDEC8B10BUSE(plm_v4f_mgt_gt11_by4_VCC_773), + .RXCLKSTABLE(plm_v4f_mgt_gt11_by4_VCC_773), + .RXLOCK(plm_v4f_mgt_pma_rxlock1), + .TXCRCDATAVALID(plm_v4f_mgt_gt11_by4_GND_772), + .GREFCLK(plm_v4f_mgt_mgtdiv2_clk), + .ENCHANSYNC(plm_v4f_mgt_gt11_by4_VCC_773), + .DEN(plm_v4f_mgt_gt1_den), + .RXMCLK(NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST2_RXMCLK_UNCONNECTED), + .RXCOMMADET(NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST2_RXCOMMADET_UNCONNECTED), + .TXOUTCLK1(NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST2_TXOUTCLK1_UNCONNECTED), + .TXOUTCLK2(NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST2_TXOUTCLK2_UNCONNECTED), + .RXCRCRESET(plm_v4f_mgt_gt11_by4_VCC_773), + .RXCRCCLK(plm_v4f_mgt_gt11_by4_GND_772), + .TXENC64B66BUSE(plm_v4f_mgt_gt11_by4_GND_772), + .TXINHIBIT(plm_v4f_mgt_gt11_by4_GND_772), + .RXRECCLK1(NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST2_RXRECCLK1_UNCONNECTED), + .RXRECCLK2(NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST2_RXRECCLK2_UNCONNECTED), + .TXLOCK(plm_v4f_mgt_pma_txlock1), + .TXCRCRESET(plm_v4f_mgt_gt11_by4_VCC_773), + .RXDESCRAM64B66BUSE(plm_v4f_mgt_gt11_by4_GND_772), + .RXBLOCKSYNC64B66BUSE(plm_v4f_mgt_gt11_by4_GND_772), + .RXIGNOREBTF(plm_v4f_mgt_gt11_by4_GND_772), + .TXCRCCLK(plm_v4f_mgt_gt11_by4_GND_772), + .RXCRCDATAVALID(plm_v4f_mgt_gt11_by4_GND_772), + .TXSCRAM64B66BUSE(plm_v4f_mgt_gt11_by4_GND_772), + .RXCRCINTCLK(plm_v4f_mgt_gt11_by4_GND_772), + .RXSYNC(plm_v4f_mgt_gt11_by4_GND_772), + .DRDY(plm_v4f_mgt_gt1_drdy), + .TXENC8B10BUSE(plm_v4f_mgt_gt11_by4_VCC_773), + .REFCLK1(sys_clkz), + .TXENOOB(plm_v4f_mgt_reg_tee1_dlyline[23]), + .REFCLK2(plm_v4f_mgt_gt11_by4_GND_772), + .TX1N(pci_exp_txn_6084[1]), + .TX1P(pci_exp_txp_6083[1]), + .RXSTATUS({plm_v4f_mgt_rx1_rxstatus[5], NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST2_RXSTATUS_4__UNCONNECTED, +NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST2_RXSTATUS_3__UNCONNECTED, NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST2_RXSTATUS_2__UNCONNECTED, +NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST2_RXSTATUS_1__UNCONNECTED, NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST2_RXSTATUS_0__UNCONNECTED}), + .RXNOTINTABLE({NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST2_RXNOTINTABLE_7__UNCONNECTED, +NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST2_RXNOTINTABLE_6__UNCONNECTED, NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST2_RXNOTINTABLE_5__UNCONNECTED, +NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST2_RXNOTINTABLE_4__UNCONNECTED, plm_v4f_mgt_wrx1_ntable[3], plm_v4f_mgt_wrx1_ntable[2], +plm_v4f_mgt_wrx1_ntable[1], plm_v4f_mgt_wrx1_ntable[0]}), + .DADDR({plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_VCC_773, plm_v4f_mgt_gt1_daddr[5], plm_v4f_mgt_gt1_daddr[4], plm_v4f_mgt_gt1_daddr[3], +plm_v4f_mgt_gt1_daddr[2], plm_v4f_mgt_gt1_daddr[1], plm_v4f_mgt_gt1_daddr[4]}), + .TXDATAWIDTH({plm_v4f_mgt_gt11_by4_VCC_773, plm_v4f_mgt_gt11_by4_GND_772}), + .RXCRCOUT({NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST2_RXCRCOUT_31__UNCONNECTED, +NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST2_RXCRCOUT_30__UNCONNECTED, NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST2_RXCRCOUT_29__UNCONNECTED, +NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST2_RXCRCOUT_28__UNCONNECTED, NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST2_RXCRCOUT_27__UNCONNECTED, +NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST2_RXCRCOUT_26__UNCONNECTED, NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST2_RXCRCOUT_25__UNCONNECTED, +NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST2_RXCRCOUT_24__UNCONNECTED, NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST2_RXCRCOUT_23__UNCONNECTED, +NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST2_RXCRCOUT_22__UNCONNECTED, NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST2_RXCRCOUT_21__UNCONNECTED, +NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST2_RXCRCOUT_20__UNCONNECTED, NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST2_RXCRCOUT_19__UNCONNECTED, +NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST2_RXCRCOUT_18__UNCONNECTED, NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST2_RXCRCOUT_17__UNCONNECTED, +NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST2_RXCRCOUT_16__UNCONNECTED, NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST2_RXCRCOUT_15__UNCONNECTED, +NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST2_RXCRCOUT_14__UNCONNECTED, NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST2_RXCRCOUT_13__UNCONNECTED, +NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST2_RXCRCOUT_12__UNCONNECTED, NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST2_RXCRCOUT_11__UNCONNECTED, +NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST2_RXCRCOUT_10__UNCONNECTED, NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST2_RXCRCOUT_9__UNCONNECTED, +NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST2_RXCRCOUT_8__UNCONNECTED, NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST2_RXCRCOUT_7__UNCONNECTED, +NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST2_RXCRCOUT_6__UNCONNECTED, NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST2_RXCRCOUT_5__UNCONNECTED, +NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST2_RXCRCOUT_4__UNCONNECTED, NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST2_RXCRCOUT_3__UNCONNECTED, +NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST2_RXCRCOUT_2__UNCONNECTED, NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST2_RXCRCOUT_1__UNCONNECTED, +NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST2_RXCRCOUT_0__UNCONNECTED}), + .TXINTDATAWIDTH({plm_v4f_mgt_gt11_by4_VCC_773, plm_v4f_mgt_gt11_by4_VCC_773}), + .DI({plm_v4f_mgt_gt1_do[15], plm_v4f_mgt_gt1_do[14], plm_v4f_mgt_gt1_do[13], plm_v4f_mgt_gt1_do[12], plm_v4f_mgt_gt1_do[11], +plm_v4f_mgt_gt1_do[10], plm_v4f_mgt_gt1_do[9], plm_v4f_mgt_gt1_do[8], plm_v4f_mgt_gt1_do[7], plm_v4f_mgt_gt1_do[6], plm_v4f_mgt_gt1_do[5], +plm_v4f_mgt_gt1_do[4], plm_v4f_mgt_gt1_do[3], plm_v4f_mgt_gt1_do[2], plm_v4f_mgt_gt1_do[1], plm_v4f_mgt_gt1_do[0]}), + .DO({plm_v4f_mgt_gt1_di[15], plm_v4f_mgt_gt1_di[14], plm_v4f_mgt_gt1_di[13], plm_v4f_mgt_gt1_di[12], plm_v4f_mgt_gt1_di[11], +plm_v4f_mgt_gt1_di[10], plm_v4f_mgt_gt1_di[9], plm_v4f_mgt_gt1_di[8], plm_v4f_mgt_gt1_di[7], plm_v4f_mgt_gt1_di[6], plm_v4f_mgt_gt1_di[5], +plm_v4f_mgt_gt1_di[4], plm_v4f_mgt_gt1_di[3], plm_v4f_mgt_gt1_di[2], plm_v4f_mgt_gt1_di[1], plm_v4f_mgt_gt1_di[0]}), + .TXCRCOUT({NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST2_TXCRCOUT_31__UNCONNECTED, +NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST2_TXCRCOUT_30__UNCONNECTED, NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST2_TXCRCOUT_29__UNCONNECTED, +NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST2_TXCRCOUT_28__UNCONNECTED, NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST2_TXCRCOUT_27__UNCONNECTED, +NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST2_TXCRCOUT_26__UNCONNECTED, NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST2_TXCRCOUT_25__UNCONNECTED, +NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST2_TXCRCOUT_24__UNCONNECTED, NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST2_TXCRCOUT_23__UNCONNECTED, +NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST2_TXCRCOUT_22__UNCONNECTED, NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST2_TXCRCOUT_21__UNCONNECTED, +NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST2_TXCRCOUT_20__UNCONNECTED, NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST2_TXCRCOUT_19__UNCONNECTED, +NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST2_TXCRCOUT_18__UNCONNECTED, NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST2_TXCRCOUT_17__UNCONNECTED, +NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST2_TXCRCOUT_16__UNCONNECTED, NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST2_TXCRCOUT_15__UNCONNECTED, +NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST2_TXCRCOUT_14__UNCONNECTED, NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST2_TXCRCOUT_13__UNCONNECTED, +NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST2_TXCRCOUT_12__UNCONNECTED, NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST2_TXCRCOUT_11__UNCONNECTED, +NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST2_TXCRCOUT_10__UNCONNECTED, NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST2_TXCRCOUT_9__UNCONNECTED, +NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST2_TXCRCOUT_8__UNCONNECTED, NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST2_TXCRCOUT_7__UNCONNECTED, +NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST2_TXCRCOUT_6__UNCONNECTED, NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST2_TXCRCOUT_5__UNCONNECTED, +NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST2_TXCRCOUT_4__UNCONNECTED, NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST2_TXCRCOUT_3__UNCONNECTED, +NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST2_TXCRCOUT_2__UNCONNECTED, NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST2_TXCRCOUT_1__UNCONNECTED, +NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST2_TXCRCOUT_0__UNCONNECTED}), + .COMBUSIN({plm_v4f_mgt_gt11_by4_COMBUSOUT[15], plm_v4f_mgt_gt11_by4_COMBUSOUT[14], plm_v4f_mgt_gt11_by4_COMBUSOUT[13], +plm_v4f_mgt_gt11_by4_COMBUSOUT[12], plm_v4f_mgt_gt11_by4_COMBUSOUT[11], plm_v4f_mgt_gt11_by4_COMBUSOUT[10], plm_v4f_mgt_gt11_by4_COMBUSOUT[9], +plm_v4f_mgt_gt11_by4_COMBUSOUT[8], plm_v4f_mgt_gt11_by4_COMBUSOUT[7], plm_v4f_mgt_gt11_by4_COMBUSOUT[6], plm_v4f_mgt_gt11_by4_COMBUSOUT[5], +plm_v4f_mgt_gt11_by4_COMBUSOUT[4], plm_v4f_mgt_gt11_by4_COMBUSOUT[3], plm_v4f_mgt_gt11_by4_COMBUSOUT[2], plm_v4f_mgt_gt11_by4_COMBUSOUT[1], +plm_v4f_mgt_gt11_by4_COMBUSOUT[0]}), + .COMBUSOUT({plm_v4f_mgt_gt11_by4_COMBUSOUT_BLK2[15], plm_v4f_mgt_gt11_by4_COMBUSOUT_BLK2[14], plm_v4f_mgt_gt11_by4_COMBUSOUT_BLK2[13], +plm_v4f_mgt_gt11_by4_COMBUSOUT_BLK2[12], plm_v4f_mgt_gt11_by4_COMBUSOUT_BLK2[11], plm_v4f_mgt_gt11_by4_COMBUSOUT_BLK2[10], +plm_v4f_mgt_gt11_by4_COMBUSOUT_BLK2[9], plm_v4f_mgt_gt11_by4_COMBUSOUT_BLK2[8], plm_v4f_mgt_gt11_by4_COMBUSOUT_BLK2[7], +plm_v4f_mgt_gt11_by4_COMBUSOUT_BLK2[6], plm_v4f_mgt_gt11_by4_COMBUSOUT_BLK2[5], plm_v4f_mgt_gt11_by4_COMBUSOUT_BLK2[4], +plm_v4f_mgt_gt11_by4_COMBUSOUT_BLK2[3], plm_v4f_mgt_gt11_by4_COMBUSOUT_BLK2[2], plm_v4f_mgt_gt11_by4_COMBUSOUT_BLK2[1], +plm_v4f_mgt_gt11_by4_COMBUSOUT_BLK2[0]}), + .RXDATA({NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST2_RXDATA_63__UNCONNECTED, NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST2_RXDATA_62__UNCONNECTED +, NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST2_RXDATA_61__UNCONNECTED, NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST2_RXDATA_60__UNCONNECTED, +NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST2_RXDATA_59__UNCONNECTED, NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST2_RXDATA_58__UNCONNECTED, +NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST2_RXDATA_57__UNCONNECTED, NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST2_RXDATA_56__UNCONNECTED, +NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST2_RXDATA_55__UNCONNECTED, NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST2_RXDATA_54__UNCONNECTED, +NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST2_RXDATA_53__UNCONNECTED, NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST2_RXDATA_52__UNCONNECTED, +NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST2_RXDATA_51__UNCONNECTED, NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST2_RXDATA_50__UNCONNECTED, +NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST2_RXDATA_49__UNCONNECTED, NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST2_RXDATA_48__UNCONNECTED, +NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST2_RXDATA_47__UNCONNECTED, NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST2_RXDATA_46__UNCONNECTED, +NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST2_RXDATA_45__UNCONNECTED, NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST2_RXDATA_44__UNCONNECTED, +NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST2_RXDATA_43__UNCONNECTED, NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST2_RXDATA_42__UNCONNECTED, +NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST2_RXDATA_41__UNCONNECTED, NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST2_RXDATA_40__UNCONNECTED, +NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST2_RXDATA_39__UNCONNECTED, NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST2_RXDATA_38__UNCONNECTED, +NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST2_RXDATA_37__UNCONNECTED, NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST2_RXDATA_36__UNCONNECTED, +NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST2_RXDATA_35__UNCONNECTED, NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST2_RXDATA_34__UNCONNECTED, +NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST2_RXDATA_33__UNCONNECTED, NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST2_RXDATA_32__UNCONNECTED, +plm_v4f_mgt_wrx1_data[31], plm_v4f_mgt_wrx1_data[30], plm_v4f_mgt_wrx1_data[29], plm_v4f_mgt_wrx1_data[28], plm_v4f_mgt_wrx1_data[27], +plm_v4f_mgt_wrx1_data[26], plm_v4f_mgt_wrx1_data[25], plm_v4f_mgt_wrx1_data[24], plm_v4f_mgt_wrx1_data[23], plm_v4f_mgt_wrx1_data[22], +plm_v4f_mgt_wrx1_data[21], plm_v4f_mgt_wrx1_data[20], plm_v4f_mgt_wrx1_data[19], plm_v4f_mgt_wrx1_data[18], plm_v4f_mgt_wrx1_data[17], +plm_v4f_mgt_wrx1_data[16], plm_v4f_mgt_wrx1_data[15], plm_v4f_mgt_wrx1_data[14], plm_v4f_mgt_wrx1_data[13], plm_v4f_mgt_wrx1_data[12], +plm_v4f_mgt_wrx1_data[11], plm_v4f_mgt_wrx1_data[10], plm_v4f_mgt_wrx1_data[9], plm_v4f_mgt_wrx1_data[8], plm_v4f_mgt_wrx1_data[7], +plm_v4f_mgt_wrx1_data[6], plm_v4f_mgt_wrx1_data[5], plm_v4f_mgt_wrx1_data[4], plm_v4f_mgt_wrx1_data[3], plm_v4f_mgt_wrx1_data[2], +plm_v4f_mgt_wrx1_data[1], plm_v4f_mgt_wrx1_data[0]}), + .TXRUNDISP({NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST2_TXRUNDISP_7__UNCONNECTED, +NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST2_TXRUNDISP_6__UNCONNECTED, NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST2_TXRUNDISP_5__UNCONNECTED, +NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST2_TXRUNDISP_4__UNCONNECTED, NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST2_TXRUNDISP_3__UNCONNECTED, +NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST2_TXRUNDISP_2__UNCONNECTED, NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST2_TXRUNDISP_1__UNCONNECTED, +NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST2_TXRUNDISP_0__UNCONNECTED}), + .RXINTDATAWIDTH({plm_v4f_mgt_gt11_by4_VCC_773, plm_v4f_mgt_gt11_by4_VCC_773}), + .RXDATAWIDTH({plm_v4f_mgt_gt11_by4_VCC_773, plm_v4f_mgt_gt11_by4_GND_772}), + .RXLOSSOFSYNC({NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST2_RXLOSSOFSYNC_1__UNCONNECTED, +NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST2_RXLOSSOFSYNC_0__UNCONNECTED}), + .RXRUNDISP({NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST2_RXRUNDISP_7__UNCONNECTED, +NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST2_RXRUNDISP_6__UNCONNECTED, NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST2_RXRUNDISP_5__UNCONNECTED, +NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST2_RXRUNDISP_4__UNCONNECTED, plm_v4f_mgt_wrx1_run_disp[3], plm_v4f_mgt_wrx1_run_disp[2], +plm_v4f_mgt_wrx1_run_disp[1], plm_v4f_mgt_wrx1_run_disp[0]}), + .TXDATA({plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, +plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, +plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, +plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, +plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, +plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, +plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, plm_tx1_data[7], plm_tx1_data[6], plm_tx1_data[5], +plm_tx1_data[4], plm_tx1_data[3], plm_tx1_data[2], plm_tx1_data[1], plm_tx1_data[0], plm_tx1_data[15], plm_tx1_data[14], plm_tx1_data[13], +plm_tx1_data[12], plm_tx1_data[11], plm_tx1_data[10], plm_tx1_data[9], plm_tx1_data[8], plm_v4f_mgt_dtx1_data[7], plm_v4f_mgt_dtx1_data[6], +plm_v4f_mgt_dtx1_data[5], plm_v4f_mgt_dtx1_data[4], plm_v4f_mgt_dtx1_data[3], plm_v4f_mgt_dtx1_data[2], plm_v4f_mgt_dtx1_data[1], +plm_v4f_mgt_dtx1_data[0], plm_v4f_mgt_dtx1_data[15], plm_v4f_mgt_dtx1_data[14], plm_v4f_mgt_dtx1_data[13], plm_v4f_mgt_dtx1_data[12], +plm_v4f_mgt_dtx1_data[11], plm_v4f_mgt_dtx1_data[10], plm_v4f_mgt_dtx1_data[9], plm_v4f_mgt_dtx1_data[8]}), + .TXCHARDISPVAL({plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, +plm_GND_702, plm_GND_702, plm_v4f_mgt_dtx1_char_disp_val[0], plm_v4f_mgt_dtx1_char_disp_val[1]}), + .LOOPBACK({plm_v4f_mgt_loopback3[1], plm_v4f_mgt_loopback3[1]}), + .CHBONDI({plm_v4f_mgt_gt11_by4_CHBONDO_2[4], plm_v4f_mgt_gt11_by4_CHBONDO_2[3], plm_v4f_mgt_gt11_by4_CHBONDO_2[2], +plm_v4f_mgt_gt11_by4_CHBONDO_2[1], plm_v4f_mgt_gt11_by4_CHBONDO_2[0]}), + .TXCRCDATAWIDTH({plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772}), + .CHBONDO({NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST2_CHBONDO_4__UNCONNECTED, NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST2_CHBONDO_3__UNCONNECTED +, NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST2_CHBONDO_2__UNCONNECTED, NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST2_CHBONDO_1__UNCONNECTED, +NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST2_CHBONDO_0__UNCONNECTED}), + .TXCHARISK({plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, +plm_tx2_char_is_k[0], plm_tx2_char_is_k[1], plm_v4f_mgt_dtx1_char_is_k[0], plm_v4f_mgt_dtx1_char_is_k[1]}), + .TXBYPASS8B10B({plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, +plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772}), + .RXCRCIN({plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, +plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, +plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, +plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, +plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, +plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, +plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, +plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, +plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, +plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, +plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, +plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, +plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772}) +, + .RXCHARISK({NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST2_RXCHARISK_7__UNCONNECTED, +NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST2_RXCHARISK_6__UNCONNECTED, NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST2_RXCHARISK_5__UNCONNECTED, +NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST2_RXCHARISK_4__UNCONNECTED, plm_v4f_mgt_wrx1_char_is_k[3], plm_v4f_mgt_wrx1_char_is_k[2], +plm_v4f_mgt_wrx1_char_is_k[1], plm_v4f_mgt_wrx1_char_is_k[0]}), + .TXCHARDISPMODE({plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, +plm_GND_702, plm_GND_702, plm_v4f_mgt_dtx1_char_disp_mode[0], plm_v4f_mgt_dtx1_char_disp_mode[1]}), + .RXCRCDATAWIDTH({plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772}), + .RXDISPERR({NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST2_RXDISPERR_7__UNCONNECTED, +NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST2_RXDISPERR_6__UNCONNECTED, NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST2_RXDISPERR_5__UNCONNECTED, +NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST2_RXDISPERR_4__UNCONNECTED, plm_v4f_mgt_wrx1_disp_err[3], plm_v4f_mgt_wrx1_disp_err[2], +plm_v4f_mgt_wrx1_disp_err[1], plm_v4f_mgt_wrx1_disp_err[0]}), + .RXCHARISCOMMA({NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST2_RXCHARISCOMMA_7__UNCONNECTED, +NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST2_RXCHARISCOMMA_6__UNCONNECTED, NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST2_RXCHARISCOMMA_5__UNCONNECTED, +NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST2_RXCHARISCOMMA_4__UNCONNECTED, NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST2_RXCHARISCOMMA_3__UNCONNECTED, +NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST2_RXCHARISCOMMA_2__UNCONNECTED, NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST2_RXCHARISCOMMA_1__UNCONNECTED, +NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST2_RXCHARISCOMMA_0__UNCONNECTED}), + .TXCRCIN({plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, +plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, +plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, +plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, +plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, +plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, +plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, +plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, +plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, +plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, +plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, +plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, +plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772}) +, + .TXKERR({NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST2_TXKERR_7__UNCONNECTED, NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST2_TXKERR_6__UNCONNECTED, +NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST2_TXKERR_5__UNCONNECTED, NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST2_TXKERR_4__UNCONNECTED, +NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST2_TXKERR_3__UNCONNECTED, NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST2_TXKERR_2__UNCONNECTED, +NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST2_TXKERR_1__UNCONNECTED, NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST2_TXKERR_0__UNCONNECTED}) + ); + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST3.MCOMMA_32B_VALUE = 32'h00000283; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST3.PCOMMA_32B_VALUE = 32'h0000017C; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST3.RXCTRL1 = 12'h200; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST3.RXCPSEL = "FALSE"; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST3.RXDIGRX = "FALSE"; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST3.RXLOOPFILT = 4'b1111; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST3.RXPLLNDIVSEL = 20; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST3.RXOUTDIV2SEL = 4; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST3.TXPD = "FALSE"; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST3.TXDAT_TAP_DAC = 5'b01010; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST3.TXPOST_TAP_DAC = 5'b00000; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST3.TXPOST_TAP_PD = "FALSE"; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST3.TXDAT_PRDRV_DAC = 3'b111; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST3.TXPOST_PRDRV_DAC = 3'b111; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST3.TXSLEWRATE = "TRUE"; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST3.TXASYNCDIVIDE = 2'b11; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST3.TXTERMTRIM = 4'b1100; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST3.TXAREFBIASSEL = "TRUE"; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST3.TXHIGHSIGNALEN = "TRUE"; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST3.TXCLKMODE = 4'b0000; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST3.TXPRE_TAP_DAC = 5'b00000; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST3.TXPRE_TAP_PD = "TRUE"; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST3.TXPRE_PRDRV_DAC = 3'b111; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST3.TXCTRL1 = 12'h200; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST3.TXCPSEL = "FALSE"; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST3.TXLOOPFILT = 4'b0101; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST3.TXPLLNDIVSEL = 20; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST3.TXOUTDIV2SEL = 4; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST3.RXEQ = 64'h4000000000000000; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST3.RXPD = "FALSE"; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST3.RXDIGRESET = "FALSE"; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST3.RXLKADJ = 5'b00000; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST3.RXDCCOUPLE = "FALSE"; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST3.RXCDRLOS = 6'b001100; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST3.RXAFEEQ = 9'b000000111; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST3.RXRCPADJ = 3'b010; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST3.RXLB = "FALSE"; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST3.RXCLKMODE = 6'b000001; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST3.RXASYNCDIVIDE = 2'b11; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST3.PMA_BIT_SLIP = "FALSE"; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST3.PMACOREPWRENABLE = "TRUE"; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST3.PMACLKENABLE = "TRUE"; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST3.TXPHASESEL = "FALSE"; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST3.BANDGAPSEL = "FALSE"; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST3.TXABPMACLKSEL = "REFCLK1"; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST3.RXPMACLKSEL = "REFCLK1"; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST3.RXRECCLK1_USE_SYNC = "FALSE"; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST3.TXOUTCLK1_USE_SYNC = "FALSE"; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST3.TXCLK0_FORCE_PMACLK = "TRUE"; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST3.RXCLK0_FORCE_PMACLK = "TRUE"; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST3.TX_CLOCK_DIVIDER = 2'b11; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST3.RX_CLOCK_DIVIDER = 2'b11; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST3.TXCRCENABLE = "TRUE"; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST3.TXCRCINITVAL = 32'hFFFFFFFF; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST3.TXCRCSAMECLOCK = "TRUE"; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST3.TXCRCINVERTGEN = "FALSE"; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST3.TXCRCCLOCKDOUBLE = "FALSE"; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST3.RXCRCINITVAL = 32'hFFFFFFFF; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST3.RXCRCENABLE = "TRUE"; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST3.RXCRCSAMECLOCK = "TRUE"; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST3.RXCRCINVERTGEN = "FALSE"; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST3.RXCRCCLOCKDOUBLE = "FALSE"; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST3.VCODAC_INIT = 10'b0000000000; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST3.SLOWDOWN_CAL = 2'b00; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST3.LOOPCAL_WAIT = 2'b00; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST3.FDET_HYS_CAL = 3'b010; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST3.FDET_LCK_CAL = 3'b101; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST3.FDET_HYS_SEL = 3'b001; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST3.FDET_LCK_SEL = 3'b111; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST3.VCO_CTRL_ENABLE = "TRUE"; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST3.CYCLE_LIMIT_SEL = 2'b00; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST3.RXVCODAC_INIT = 10'b0000000000; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST3.RXSLOWDOWN_CAL = 2'b00; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST3.RXLOOPCAL_WAIT = 2'b00; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST3.RXFDET_HYS_CAL = 3'b010; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST3.RXFDET_LCK_CAL = 3'b101; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST3.RXFDET_HYS_SEL = 3'b001; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST3.RXFDET_LCK_SEL = 3'b100; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST3.RXVCO_CTRL_ENABLE = "TRUE"; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST3.RXCYCLE_LIMIT_SEL = 2'b00; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST3.RXFDCAL_CLOCK_DIVIDE = "NONE"; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST3.TXFDCAL_CLOCK_DIVIDE = "NONE"; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST3.BIASRESSEL = "FALSE"; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST3.RXPDDTST = "TRUE"; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST3.RXCMADJ = 2'b01; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST3.RXBY_32 = "FALSE"; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST3.REPEATER = "FALSE"; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST3.ENABLE_DCDR = "FALSE"; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST3.SAMPLE_8X = "FALSE"; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST3.DCDR_FILTER = 3'b010; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST3.RXUSRDIVISOR = 1; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST3.COMMA_10B_MASK = 12'h3FF; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST3.PCOMMA_DETECT = "TRUE"; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST3.MCOMMA_DETECT = "TRUE"; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST3.DEC_VALID_COMMA_ONLY = "TRUE"; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST3.DEC_PCOMMA_DETECT = "TRUE"; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST3.DEC_MCOMMA_DETECT = "TRUE"; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST3.ALIGN_COMMA_WORD = 1; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST3.CLK_COR_8B10B_DE = "TRUE"; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST3.CLK_CORRECT_USE = "TRUE"; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST3.CLK_COR_SEQ_LEN = 4; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST3.CLK_COR_SEQ_DROP = "FALSE"; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST3.CLK_COR_SEQ_2_USE = "FALSE"; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST3.CLK_COR_MAX_LAT = 44; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST3.CLK_COR_SEQ_2_MASK = 4'b1110; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST3.CLK_COR_SEQ_2_4 = 11'b00000000000; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST3.CLK_COR_SEQ_2_3 = 11'b00000000000; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST3.CLK_COR_SEQ_2_2 = 11'b00000000000; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST3.CLK_COR_SEQ_2_1 = 11'b00000000000; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST3.RXDATA_SEL = 2'b00; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST3.TXDATA_SEL = 2'b00; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST3.CLK_COR_MIN_LAT = 36; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST3.PCS_BIT_SLIP = "FALSE"; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST3.DIGRX_FWDCLK = 2'b00; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST3.DIGRX_SYNC_MODE = "FALSE"; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST3.CLK_COR_SEQ_1_MASK = 4'b0000; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST3.CLK_COR_SEQ_1_4 = 11'b00100011100; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST3.CLK_COR_SEQ_1_3 = 11'b00100011100; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST3.CLK_COR_SEQ_1_2 = 11'b00100011100; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST3.CLK_COR_SEQ_1_1 = 11'b00110111100; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST3.CCCB_ARBITRATOR_DISABLE = "FALSE"; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST3.OPPOSITE_SELECT = "FALSE"; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST3.POWER_ENABLE = "TRUE"; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST3.CHAN_BOND_SEQ_2_MASK = 4'b0000; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST3.CHAN_BOND_SEQ_2_4 = 11'b00000000000; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST3.CHAN_BOND_SEQ_2_3 = 11'b00000000000; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST3.CHAN_BOND_SEQ_2_2 = 11'b00000000000; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST3.CHAN_BOND_SEQ_2_1 = 11'b00000000000; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST3.TX_BUFFER_USE = "TRUE"; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST3.RX_BUFFER_USE = "TRUE"; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST3.CHAN_BOND_SEQ_LEN = 4; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST3.CHAN_BOND_SEQ_2_USE = "FALSE"; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST3.CHAN_BOND_ONE_SHOT = "FALSE"; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST3.CHAN_BOND_MODE = "SLAVE_1_HOP"; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST3.CHAN_BOND_LIMIT = 6; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST3.CHAN_BOND_SEQ_1_MASK = 4'b0000; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST3.CHAN_BOND_SEQ_1_4 = 11'b00110111100; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST3.CHAN_BOND_SEQ_1_3 = 11'b00001000101; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST3.CHAN_BOND_SEQ_1_2 = 11'b00001000101; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST3.CHAN_BOND_SEQ_1_1 = 11'b00001000101; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST3.GT11_MODE = "A"; + GT11 plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST3 ( + .RXCRCPD(plm_v4f_mgt_gt11_by4_VCC_773), + .RXBUFERR(NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST3_RXBUFERR_UNCONNECTED), + .TXSYNC(plm_v4f_mgt_reg_tx_sync_756), + .POWERDOWN(plm_v4f_mgt_gt11_by4_GND_772), + .TXUSRCLK2(plm_v4f_mgt_mgtdiv2_clk), + .ENPCOMMAALIGN(plm_v4f_mgt_gt11_by4_VCC_773), + .RXPOLARITY(plm_rx2_polarity), + .ENMCOMMAALIGN(plm_v4f_mgt_gt11_by4_VCC_773), + .TXBUFERR(NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST3_TXBUFERR_UNCONNECTED), + .TXCRCPD(plm_v4f_mgt_gt11_by4_VCC_773), + .RXSIGDET(plm_v4f_mgt_rx2_sigdet_n_async), + .TXCLKSTABLE(plm_v4f_mgt_gt11_by4_VCC_773), + .RXUSRCLK2(plm_v4f_mgt_mgtdiv2_clk), + .TXPOLARITY(plm_v4f_mgt_gt11_by4_GND_772), + .DWE(plm_v4f_mgt_gt2_dwe), + .RXREALIGN(NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST3_RXREALIGN_UNCONNECTED), + .TXGEARBOX64B66BUSE(plm_v4f_mgt_gt11_by4_GND_772), + .RXCYCLELIMIT(NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST3_RXCYCLELIMIT_UNCONNECTED), + .RXRESET(plm_v4f_mgt_reg_rx2_pcs_init_753), + .TXCYCLELIMIT(NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST3_TXCYCLELIMIT_UNCONNECTED), + .TXCALFAIL(NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST3_TXCALFAIL_UNCONNECTED), + .RXUSRCLK(plm_v4f_mgt_mgtdiv2_clk), + .RXDEC64B66BUSE(plm_v4f_mgt_gt11_by4_GND_772), + .RXPCSHCLKOUT(NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST3_RXPCSHCLKOUT_UNCONNECTED), + .TXPCSHCLKOUT(NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST3_TXPCSHCLKOUT_UNCONNECTED), + .RXCOMMADETUSE(plm_v4f_mgt_gt11_by4_VCC_773), + .DCLK(plm_v4f_mgt_cal_clk), + .TXCRCINIT(plm_v4f_mgt_gt11_by4_GND_772), + .TXUSRCLK(plm_v4f_mgt_mgtdiv2_clk), + .RXCALFAIL(NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST3_RXCALFAIL_UNCONNECTED), + .RXPMARESET(plm_v4f_mgt_reg_pma_768), + .RX1N(pci_exp_rxn_6086[2]), + .RX1P(pci_exp_rxp_6085[2]), + .TXRESET(plm_v4f_mgt_reg_tx_pcs_init_758), + .RXSLIDE(plm_v4f_mgt_gt11_by4_GND_772), + .TXPMARESET(plm_v4f_mgt_reg_pma_768), + .TXCRCINTCLK(plm_v4f_mgt_gt11_by4_GND_772), + .RXCRCINIT(plm_v4f_mgt_gt11_by4_GND_772), + .RXDEC8B10BUSE(plm_v4f_mgt_gt11_by4_VCC_773), + .RXCLKSTABLE(plm_v4f_mgt_gt11_by4_VCC_773), + .RXLOCK(plm_v4f_mgt_pma_rxlock2), + .TXCRCDATAVALID(plm_v4f_mgt_gt11_by4_GND_772), + .GREFCLK(plm_v4f_mgt_mgtdiv2_clk), + .ENCHANSYNC(plm_v4f_mgt_gt11_by4_VCC_773), + .DEN(plm_v4f_mgt_gt2_den), + .RXMCLK(NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST3_RXMCLK_UNCONNECTED), + .RXCOMMADET(NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST3_RXCOMMADET_UNCONNECTED), + .TXOUTCLK1(NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST3_TXOUTCLK1_UNCONNECTED), + .TXOUTCLK2(NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST3_TXOUTCLK2_UNCONNECTED), + .RXCRCRESET(plm_v4f_mgt_gt11_by4_VCC_773), + .RXCRCCLK(plm_v4f_mgt_gt11_by4_GND_772), + .TXENC64B66BUSE(plm_v4f_mgt_gt11_by4_GND_772), + .TXINHIBIT(plm_v4f_mgt_gt11_by4_GND_772), + .RXRECCLK1(NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST3_RXRECCLK1_UNCONNECTED), + .RXRECCLK2(NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST3_RXRECCLK2_UNCONNECTED), + .TXLOCK(plm_v4f_mgt_pma_txlock2), + .TXCRCRESET(plm_v4f_mgt_gt11_by4_VCC_773), + .RXDESCRAM64B66BUSE(plm_v4f_mgt_gt11_by4_GND_772), + .RXBLOCKSYNC64B66BUSE(plm_v4f_mgt_gt11_by4_GND_772), + .RXIGNOREBTF(plm_v4f_mgt_gt11_by4_GND_772), + .TXCRCCLK(plm_v4f_mgt_gt11_by4_GND_772), + .RXCRCDATAVALID(plm_v4f_mgt_gt11_by4_GND_772), + .TXSCRAM64B66BUSE(plm_v4f_mgt_gt11_by4_GND_772), + .RXCRCINTCLK(plm_v4f_mgt_gt11_by4_GND_772), + .RXSYNC(plm_v4f_mgt_gt11_by4_GND_772), + .DRDY(plm_v4f_mgt_gt2_drdy), + .TXENC8B10BUSE(plm_v4f_mgt_gt11_by4_VCC_773), + .REFCLK1(sys_clkz), + .TXENOOB(plm_v4f_mgt_reg_tee2_dlyline[23]), + .REFCLK2(plm_v4f_mgt_gt11_by4_GND_772), + .TX1N(pci_exp_txn_6084[2]), + .TX1P(pci_exp_txp_6083[2]), + .RXSTATUS({plm_v4f_mgt_rx2_rxstatus[5], NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST3_RXSTATUS_4__UNCONNECTED, +NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST3_RXSTATUS_3__UNCONNECTED, NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST3_RXSTATUS_2__UNCONNECTED, +NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST3_RXSTATUS_1__UNCONNECTED, NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST3_RXSTATUS_0__UNCONNECTED}), + .RXNOTINTABLE({NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST3_RXNOTINTABLE_7__UNCONNECTED, +NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST3_RXNOTINTABLE_6__UNCONNECTED, NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST3_RXNOTINTABLE_5__UNCONNECTED, +NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST3_RXNOTINTABLE_4__UNCONNECTED, plm_v4f_mgt_wrx2_ntable[3], plm_v4f_mgt_wrx2_ntable[2], +plm_v4f_mgt_wrx2_ntable[1], plm_v4f_mgt_wrx2_ntable[0]}), + .DADDR({plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_VCC_773, plm_v4f_mgt_gt2_daddr[5], plm_v4f_mgt_gt2_daddr[4], plm_v4f_mgt_gt2_daddr[3], +plm_v4f_mgt_gt2_daddr[2], plm_v4f_mgt_gt2_daddr[1], plm_v4f_mgt_gt2_daddr[4]}), + .TXDATAWIDTH({plm_v4f_mgt_gt11_by4_VCC_773, plm_v4f_mgt_gt11_by4_GND_772}), + .RXCRCOUT({NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST3_RXCRCOUT_31__UNCONNECTED, +NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST3_RXCRCOUT_30__UNCONNECTED, NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST3_RXCRCOUT_29__UNCONNECTED, +NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST3_RXCRCOUT_28__UNCONNECTED, NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST3_RXCRCOUT_27__UNCONNECTED, +NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST3_RXCRCOUT_26__UNCONNECTED, NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST3_RXCRCOUT_25__UNCONNECTED, +NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST3_RXCRCOUT_24__UNCONNECTED, NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST3_RXCRCOUT_23__UNCONNECTED, +NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST3_RXCRCOUT_22__UNCONNECTED, NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST3_RXCRCOUT_21__UNCONNECTED, +NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST3_RXCRCOUT_20__UNCONNECTED, NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST3_RXCRCOUT_19__UNCONNECTED, +NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST3_RXCRCOUT_18__UNCONNECTED, NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST3_RXCRCOUT_17__UNCONNECTED, +NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST3_RXCRCOUT_16__UNCONNECTED, NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST3_RXCRCOUT_15__UNCONNECTED, +NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST3_RXCRCOUT_14__UNCONNECTED, NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST3_RXCRCOUT_13__UNCONNECTED, +NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST3_RXCRCOUT_12__UNCONNECTED, NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST3_RXCRCOUT_11__UNCONNECTED, +NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST3_RXCRCOUT_10__UNCONNECTED, NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST3_RXCRCOUT_9__UNCONNECTED, +NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST3_RXCRCOUT_8__UNCONNECTED, NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST3_RXCRCOUT_7__UNCONNECTED, +NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST3_RXCRCOUT_6__UNCONNECTED, NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST3_RXCRCOUT_5__UNCONNECTED, +NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST3_RXCRCOUT_4__UNCONNECTED, NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST3_RXCRCOUT_3__UNCONNECTED, +NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST3_RXCRCOUT_2__UNCONNECTED, NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST3_RXCRCOUT_1__UNCONNECTED, +NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST3_RXCRCOUT_0__UNCONNECTED}), + .TXINTDATAWIDTH({plm_v4f_mgt_gt11_by4_VCC_773, plm_v4f_mgt_gt11_by4_VCC_773}), + .DI({plm_v4f_mgt_gt2_do[15], plm_v4f_mgt_gt2_do[14], plm_v4f_mgt_gt2_do[13], plm_v4f_mgt_gt2_do[12], plm_v4f_mgt_gt2_do[11], +plm_v4f_mgt_gt2_do[10], plm_v4f_mgt_gt2_do[9], plm_v4f_mgt_gt2_do[8], plm_v4f_mgt_gt2_do[7], plm_v4f_mgt_gt2_do[6], plm_v4f_mgt_gt2_do[5], +plm_v4f_mgt_gt2_do[4], plm_v4f_mgt_gt2_do[3], plm_v4f_mgt_gt2_do[2], plm_v4f_mgt_gt2_do[1], plm_v4f_mgt_gt2_do[0]}), + .DO({plm_v4f_mgt_gt2_di[15], plm_v4f_mgt_gt2_di[14], plm_v4f_mgt_gt2_di[13], plm_v4f_mgt_gt2_di[12], plm_v4f_mgt_gt2_di[11], +plm_v4f_mgt_gt2_di[10], plm_v4f_mgt_gt2_di[9], plm_v4f_mgt_gt2_di[8], plm_v4f_mgt_gt2_di[7], plm_v4f_mgt_gt2_di[6], plm_v4f_mgt_gt2_di[5], +plm_v4f_mgt_gt2_di[4], plm_v4f_mgt_gt2_di[3], plm_v4f_mgt_gt2_di[2], plm_v4f_mgt_gt2_di[1], plm_v4f_mgt_gt2_di[0]}), + .TXCRCOUT({NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST3_TXCRCOUT_31__UNCONNECTED, +NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST3_TXCRCOUT_30__UNCONNECTED, NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST3_TXCRCOUT_29__UNCONNECTED, +NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST3_TXCRCOUT_28__UNCONNECTED, NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST3_TXCRCOUT_27__UNCONNECTED, +NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST3_TXCRCOUT_26__UNCONNECTED, NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST3_TXCRCOUT_25__UNCONNECTED, +NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST3_TXCRCOUT_24__UNCONNECTED, NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST3_TXCRCOUT_23__UNCONNECTED, +NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST3_TXCRCOUT_22__UNCONNECTED, NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST3_TXCRCOUT_21__UNCONNECTED, +NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST3_TXCRCOUT_20__UNCONNECTED, NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST3_TXCRCOUT_19__UNCONNECTED, +NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST3_TXCRCOUT_18__UNCONNECTED, NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST3_TXCRCOUT_17__UNCONNECTED, +NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST3_TXCRCOUT_16__UNCONNECTED, NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST3_TXCRCOUT_15__UNCONNECTED, +NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST3_TXCRCOUT_14__UNCONNECTED, NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST3_TXCRCOUT_13__UNCONNECTED, +NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST3_TXCRCOUT_12__UNCONNECTED, NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST3_TXCRCOUT_11__UNCONNECTED, +NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST3_TXCRCOUT_10__UNCONNECTED, NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST3_TXCRCOUT_9__UNCONNECTED, +NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST3_TXCRCOUT_8__UNCONNECTED, NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST3_TXCRCOUT_7__UNCONNECTED, +NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST3_TXCRCOUT_6__UNCONNECTED, NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST3_TXCRCOUT_5__UNCONNECTED, +NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST3_TXCRCOUT_4__UNCONNECTED, NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST3_TXCRCOUT_3__UNCONNECTED, +NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST3_TXCRCOUT_2__UNCONNECTED, NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST3_TXCRCOUT_1__UNCONNECTED, +NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST3_TXCRCOUT_0__UNCONNECTED}), + .COMBUSIN({plm_v4f_mgt_gt11_by4_COMBUSOUT_BLK4[15], plm_v4f_mgt_gt11_by4_COMBUSOUT_BLK4[14], plm_v4f_mgt_gt11_by4_COMBUSOUT_BLK4[13], +plm_v4f_mgt_gt11_by4_COMBUSOUT_BLK4[12], plm_v4f_mgt_gt11_by4_COMBUSOUT_BLK4[11], plm_v4f_mgt_gt11_by4_COMBUSOUT_BLK4[10], +plm_v4f_mgt_gt11_by4_COMBUSOUT_BLK4[9], plm_v4f_mgt_gt11_by4_COMBUSOUT_BLK4[8], plm_v4f_mgt_gt11_by4_COMBUSOUT_BLK4[7], +plm_v4f_mgt_gt11_by4_COMBUSOUT_BLK4[6], plm_v4f_mgt_gt11_by4_COMBUSOUT_BLK4[5], plm_v4f_mgt_gt11_by4_COMBUSOUT_BLK4[4], +plm_v4f_mgt_gt11_by4_COMBUSOUT_BLK4[3], plm_v4f_mgt_gt11_by4_COMBUSOUT_BLK4[2], plm_v4f_mgt_gt11_by4_COMBUSOUT_BLK4[1], +plm_v4f_mgt_gt11_by4_COMBUSOUT_BLK4[0]}), + .COMBUSOUT({plm_v4f_mgt_gt11_by4_COMBUSOUT_BLK3[15], plm_v4f_mgt_gt11_by4_COMBUSOUT_BLK3[14], plm_v4f_mgt_gt11_by4_COMBUSOUT_BLK3[13], +plm_v4f_mgt_gt11_by4_COMBUSOUT_BLK3[12], plm_v4f_mgt_gt11_by4_COMBUSOUT_BLK3[11], plm_v4f_mgt_gt11_by4_COMBUSOUT_BLK3[10], +plm_v4f_mgt_gt11_by4_COMBUSOUT_BLK3[9], plm_v4f_mgt_gt11_by4_COMBUSOUT_BLK3[8], plm_v4f_mgt_gt11_by4_COMBUSOUT_BLK3[7], +plm_v4f_mgt_gt11_by4_COMBUSOUT_BLK3[6], plm_v4f_mgt_gt11_by4_COMBUSOUT_BLK3[5], plm_v4f_mgt_gt11_by4_COMBUSOUT_BLK3[4], +plm_v4f_mgt_gt11_by4_COMBUSOUT_BLK3[3], plm_v4f_mgt_gt11_by4_COMBUSOUT_BLK3[2], plm_v4f_mgt_gt11_by4_COMBUSOUT_BLK3[1], +plm_v4f_mgt_gt11_by4_COMBUSOUT_BLK3[0]}), + .RXDATA({NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST3_RXDATA_63__UNCONNECTED, NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST3_RXDATA_62__UNCONNECTED +, NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST3_RXDATA_61__UNCONNECTED, NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST3_RXDATA_60__UNCONNECTED, +NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST3_RXDATA_59__UNCONNECTED, NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST3_RXDATA_58__UNCONNECTED, +NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST3_RXDATA_57__UNCONNECTED, NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST3_RXDATA_56__UNCONNECTED, +NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST3_RXDATA_55__UNCONNECTED, NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST3_RXDATA_54__UNCONNECTED, +NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST3_RXDATA_53__UNCONNECTED, NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST3_RXDATA_52__UNCONNECTED, +NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST3_RXDATA_51__UNCONNECTED, NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST3_RXDATA_50__UNCONNECTED, +NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST3_RXDATA_49__UNCONNECTED, NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST3_RXDATA_48__UNCONNECTED, +NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST3_RXDATA_47__UNCONNECTED, NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST3_RXDATA_46__UNCONNECTED, +NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST3_RXDATA_45__UNCONNECTED, NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST3_RXDATA_44__UNCONNECTED, +NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST3_RXDATA_43__UNCONNECTED, NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST3_RXDATA_42__UNCONNECTED, +NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST3_RXDATA_41__UNCONNECTED, NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST3_RXDATA_40__UNCONNECTED, +NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST3_RXDATA_39__UNCONNECTED, NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST3_RXDATA_38__UNCONNECTED, +NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST3_RXDATA_37__UNCONNECTED, NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST3_RXDATA_36__UNCONNECTED, +NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST3_RXDATA_35__UNCONNECTED, NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST3_RXDATA_34__UNCONNECTED, +NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST3_RXDATA_33__UNCONNECTED, NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST3_RXDATA_32__UNCONNECTED, +plm_v4f_mgt_wrx2_data[31], plm_v4f_mgt_wrx2_data[30], plm_v4f_mgt_wrx2_data[29], plm_v4f_mgt_wrx2_data[28], plm_v4f_mgt_wrx2_data[27], +plm_v4f_mgt_wrx2_data[26], plm_v4f_mgt_wrx2_data[25], plm_v4f_mgt_wrx2_data[24], plm_v4f_mgt_wrx2_data[23], plm_v4f_mgt_wrx2_data[22], +plm_v4f_mgt_wrx2_data[21], plm_v4f_mgt_wrx2_data[20], plm_v4f_mgt_wrx2_data[19], plm_v4f_mgt_wrx2_data[18], plm_v4f_mgt_wrx2_data[17], +plm_v4f_mgt_wrx2_data[16], plm_v4f_mgt_wrx2_data[15], plm_v4f_mgt_wrx2_data[14], plm_v4f_mgt_wrx2_data[13], plm_v4f_mgt_wrx2_data[12], +plm_v4f_mgt_wrx2_data[11], plm_v4f_mgt_wrx2_data[10], plm_v4f_mgt_wrx2_data[9], plm_v4f_mgt_wrx2_data[8], plm_v4f_mgt_wrx2_data[7], +plm_v4f_mgt_wrx2_data[6], plm_v4f_mgt_wrx2_data[5], plm_v4f_mgt_wrx2_data[4], plm_v4f_mgt_wrx2_data[3], plm_v4f_mgt_wrx2_data[2], +plm_v4f_mgt_wrx2_data[1], plm_v4f_mgt_wrx2_data[0]}), + .TXRUNDISP({NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST3_TXRUNDISP_7__UNCONNECTED, +NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST3_TXRUNDISP_6__UNCONNECTED, NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST3_TXRUNDISP_5__UNCONNECTED, +NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST3_TXRUNDISP_4__UNCONNECTED, NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST3_TXRUNDISP_3__UNCONNECTED, +NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST3_TXRUNDISP_2__UNCONNECTED, NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST3_TXRUNDISP_1__UNCONNECTED, +NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST3_TXRUNDISP_0__UNCONNECTED}), + .RXINTDATAWIDTH({plm_v4f_mgt_gt11_by4_VCC_773, plm_v4f_mgt_gt11_by4_VCC_773}), + .RXDATAWIDTH({plm_v4f_mgt_gt11_by4_VCC_773, plm_v4f_mgt_gt11_by4_GND_772}), + .RXLOSSOFSYNC({NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST3_RXLOSSOFSYNC_1__UNCONNECTED, +NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST3_RXLOSSOFSYNC_0__UNCONNECTED}), + .RXRUNDISP({NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST3_RXRUNDISP_7__UNCONNECTED, +NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST3_RXRUNDISP_6__UNCONNECTED, NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST3_RXRUNDISP_5__UNCONNECTED, +NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST3_RXRUNDISP_4__UNCONNECTED, plm_v4f_mgt_wrx2_run_disp[3], plm_v4f_mgt_wrx2_run_disp[2], +plm_v4f_mgt_wrx2_run_disp[1], plm_v4f_mgt_wrx2_run_disp[0]}), + .TXDATA({plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, +plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, +plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, +plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, +plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, +plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, +plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, plm_tx2_data[7], plm_tx2_data[6], plm_tx2_data[5], +plm_tx2_data[4], plm_tx2_data[3], plm_tx2_data[2], plm_tx2_data[1], plm_tx2_data[0], plm_tx2_data[15], plm_tx2_data[14], plm_tx2_data[13], +plm_tx2_data[12], plm_tx2_data[11], plm_tx2_data[10], plm_tx2_data[9], plm_tx2_data[8], plm_v4f_mgt_dtx2_data[7], plm_v4f_mgt_dtx2_data[6], +plm_v4f_mgt_dtx2_data[5], plm_v4f_mgt_dtx2_data[4], plm_v4f_mgt_dtx2_data[3], plm_v4f_mgt_dtx2_data[2], plm_v4f_mgt_dtx2_data[1], +plm_v4f_mgt_dtx2_data[0], plm_v4f_mgt_dtx2_data[15], plm_v4f_mgt_dtx2_data[14], plm_v4f_mgt_dtx2_data[13], plm_v4f_mgt_dtx2_data[12], +plm_v4f_mgt_dtx2_data[11], plm_v4f_mgt_dtx2_data[10], plm_v4f_mgt_dtx2_data[9], plm_v4f_mgt_dtx2_data[8]}), + .TXCHARDISPVAL({plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, +plm_GND_702, plm_GND_702, plm_v4f_mgt_dtx2_char_disp_val[0], plm_v4f_mgt_dtx2_char_disp_val[1]}), + .LOOPBACK({plm_v4f_mgt_loopback3[1], plm_v4f_mgt_loopback3[1]}), + .CHBONDI({plm_v4f_mgt_gt11_by4_CHBONDO_2[4], plm_v4f_mgt_gt11_by4_CHBONDO_2[3], plm_v4f_mgt_gt11_by4_CHBONDO_2[2], +plm_v4f_mgt_gt11_by4_CHBONDO_2[1], plm_v4f_mgt_gt11_by4_CHBONDO_2[0]}), + .TXCRCDATAWIDTH({plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772}), + .CHBONDO({NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST3_CHBONDO_4__UNCONNECTED, NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST3_CHBONDO_3__UNCONNECTED +, NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST3_CHBONDO_2__UNCONNECTED, NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST3_CHBONDO_1__UNCONNECTED, +NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST3_CHBONDO_0__UNCONNECTED}), + .TXCHARISK({plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, +plm_tx2_char_is_k[0], plm_tx2_char_is_k[1], plm_v4f_mgt_dtx2_char_is_k[0], plm_v4f_mgt_dtx2_char_is_k[1]}), + .TXBYPASS8B10B({plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, +plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772}), + .RXCRCIN({plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, +plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, +plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, +plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, +plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, +plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, +plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, +plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, +plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, +plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, +plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, +plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, +plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772}) +, + .RXCHARISK({NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST3_RXCHARISK_7__UNCONNECTED, +NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST3_RXCHARISK_6__UNCONNECTED, NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST3_RXCHARISK_5__UNCONNECTED, +NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST3_RXCHARISK_4__UNCONNECTED, plm_v4f_mgt_wrx2_char_is_k[3], plm_v4f_mgt_wrx2_char_is_k[2], +plm_v4f_mgt_wrx2_char_is_k[1], plm_v4f_mgt_wrx2_char_is_k[0]}), + .TXCHARDISPMODE({plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, +plm_GND_702, plm_GND_702, plm_v4f_mgt_dtx2_char_disp_mode[0], plm_v4f_mgt_dtx2_char_disp_mode[1]}), + .RXCRCDATAWIDTH({plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772}), + .RXDISPERR({NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST3_RXDISPERR_7__UNCONNECTED, +NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST3_RXDISPERR_6__UNCONNECTED, NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST3_RXDISPERR_5__UNCONNECTED, +NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST3_RXDISPERR_4__UNCONNECTED, plm_v4f_mgt_wrx2_disp_err[3], plm_v4f_mgt_wrx2_disp_err[2], +plm_v4f_mgt_wrx2_disp_err[1], plm_v4f_mgt_wrx2_disp_err[0]}), + .RXCHARISCOMMA({NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST3_RXCHARISCOMMA_7__UNCONNECTED, +NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST3_RXCHARISCOMMA_6__UNCONNECTED, NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST3_RXCHARISCOMMA_5__UNCONNECTED, +NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST3_RXCHARISCOMMA_4__UNCONNECTED, NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST3_RXCHARISCOMMA_3__UNCONNECTED, +NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST3_RXCHARISCOMMA_2__UNCONNECTED, NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST3_RXCHARISCOMMA_1__UNCONNECTED, +NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST3_RXCHARISCOMMA_0__UNCONNECTED}), + .TXCRCIN({plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, +plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, +plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, +plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, +plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, +plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, +plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, +plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, +plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, +plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, +plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, +plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, +plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772}) +, + .TXKERR({NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST3_TXKERR_7__UNCONNECTED, NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST3_TXKERR_6__UNCONNECTED, +NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST3_TXKERR_5__UNCONNECTED, NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST3_TXKERR_4__UNCONNECTED, +NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST3_TXKERR_3__UNCONNECTED, NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST3_TXKERR_2__UNCONNECTED, +NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST3_TXKERR_1__UNCONNECTED, NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST3_TXKERR_0__UNCONNECTED}) + ); + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST4.MCOMMA_32B_VALUE = 32'h00000283; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST4.PCOMMA_32B_VALUE = 32'h0000017C; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST4.RXCTRL1 = 12'h200; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST4.RXCPSEL = "FALSE"; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST4.RXDIGRX = "FALSE"; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST4.RXLOOPFILT = 4'b1111; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST4.RXPLLNDIVSEL = 20; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST4.RXOUTDIV2SEL = 4; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST4.TXPD = "FALSE"; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST4.TXDAT_TAP_DAC = 5'b01010; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST4.TXPOST_TAP_DAC = 5'b00000; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST4.TXPOST_TAP_PD = "FALSE"; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST4.TXDAT_PRDRV_DAC = 3'b111; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST4.TXPOST_PRDRV_DAC = 3'b111; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST4.TXSLEWRATE = "TRUE"; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST4.TXASYNCDIVIDE = 2'b11; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST4.TXTERMTRIM = 4'b1100; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST4.TXAREFBIASSEL = "TRUE"; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST4.TXHIGHSIGNALEN = "TRUE"; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST4.TXCLKMODE = 4'b0000; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST4.TXPRE_TAP_DAC = 5'b00000; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST4.TXPRE_TAP_PD = "TRUE"; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST4.TXPRE_PRDRV_DAC = 3'b111; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST4.TXCTRL1 = 12'h200; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST4.TXCPSEL = "FALSE"; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST4.TXLOOPFILT = 4'b0101; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST4.TXPLLNDIVSEL = 20; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST4.TXOUTDIV2SEL = 4; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST4.RXEQ = 64'h4000000000000000; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST4.RXPD = "FALSE"; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST4.RXDIGRESET = "FALSE"; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST4.RXLKADJ = 5'b00000; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST4.RXDCCOUPLE = "FALSE"; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST4.RXCDRLOS = 6'b001100; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST4.RXAFEEQ = 9'b000000111; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST4.RXRCPADJ = 3'b010; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST4.RXLB = "FALSE"; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST4.RXCLKMODE = 6'b000001; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST4.RXASYNCDIVIDE = 2'b11; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST4.PMA_BIT_SLIP = "FALSE"; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST4.PMACOREPWRENABLE = "TRUE"; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST4.PMACLKENABLE = "TRUE"; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST4.TXPHASESEL = "FALSE"; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST4.BANDGAPSEL = "FALSE"; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST4.TXABPMACLKSEL = "REFCLK1"; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST4.RXPMACLKSEL = "REFCLK1"; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST4.RXRECCLK1_USE_SYNC = "FALSE"; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST4.TXOUTCLK1_USE_SYNC = "FALSE"; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST4.TXCLK0_FORCE_PMACLK = "TRUE"; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST4.RXCLK0_FORCE_PMACLK = "TRUE"; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST4.TX_CLOCK_DIVIDER = 2'b11; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST4.RX_CLOCK_DIVIDER = 2'b11; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST4.TXCRCENABLE = "TRUE"; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST4.TXCRCINITVAL = 32'hFFFFFFFF; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST4.TXCRCSAMECLOCK = "TRUE"; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST4.TXCRCINVERTGEN = "FALSE"; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST4.TXCRCCLOCKDOUBLE = "FALSE"; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST4.RXCRCINITVAL = 32'hFFFFFFFF; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST4.RXCRCENABLE = "TRUE"; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST4.RXCRCSAMECLOCK = "TRUE"; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST4.RXCRCINVERTGEN = "FALSE"; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST4.RXCRCCLOCKDOUBLE = "FALSE"; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST4.VCODAC_INIT = 10'b0000000000; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST4.SLOWDOWN_CAL = 2'b00; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST4.LOOPCAL_WAIT = 2'b00; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST4.FDET_HYS_CAL = 3'b010; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST4.FDET_LCK_CAL = 3'b101; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST4.FDET_HYS_SEL = 3'b001; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST4.FDET_LCK_SEL = 3'b111; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST4.VCO_CTRL_ENABLE = "TRUE"; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST4.CYCLE_LIMIT_SEL = 2'b00; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST4.RXVCODAC_INIT = 10'b0000000000; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST4.RXSLOWDOWN_CAL = 2'b00; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST4.RXLOOPCAL_WAIT = 2'b00; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST4.RXFDET_HYS_CAL = 3'b010; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST4.RXFDET_LCK_CAL = 3'b101; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST4.RXFDET_HYS_SEL = 3'b001; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST4.RXFDET_LCK_SEL = 3'b100; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST4.RXVCO_CTRL_ENABLE = "TRUE"; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST4.RXCYCLE_LIMIT_SEL = 2'b00; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST4.RXFDCAL_CLOCK_DIVIDE = "NONE"; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST4.TXFDCAL_CLOCK_DIVIDE = "NONE"; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST4.BIASRESSEL = "FALSE"; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST4.RXPDDTST = "TRUE"; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST4.RXCMADJ = 2'b01; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST4.RXBY_32 = "FALSE"; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST4.REPEATER = "FALSE"; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST4.ENABLE_DCDR = "FALSE"; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST4.SAMPLE_8X = "FALSE"; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST4.DCDR_FILTER = 3'b010; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST4.RXUSRDIVISOR = 1; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST4.COMMA_10B_MASK = 12'h3FF; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST4.PCOMMA_DETECT = "TRUE"; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST4.MCOMMA_DETECT = "TRUE"; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST4.DEC_VALID_COMMA_ONLY = "TRUE"; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST4.DEC_PCOMMA_DETECT = "TRUE"; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST4.DEC_MCOMMA_DETECT = "TRUE"; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST4.ALIGN_COMMA_WORD = 1; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST4.CLK_COR_8B10B_DE = "TRUE"; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST4.CLK_CORRECT_USE = "TRUE"; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST4.CLK_COR_SEQ_LEN = 4; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST4.CLK_COR_SEQ_DROP = "FALSE"; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST4.CLK_COR_SEQ_2_USE = "FALSE"; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST4.CLK_COR_MAX_LAT = 44; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST4.CLK_COR_SEQ_2_MASK = 4'b1110; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST4.CLK_COR_SEQ_2_4 = 11'b00000000000; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST4.CLK_COR_SEQ_2_3 = 11'b00000000000; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST4.CLK_COR_SEQ_2_2 = 11'b00000000000; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST4.CLK_COR_SEQ_2_1 = 11'b00000000000; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST4.RXDATA_SEL = 2'b00; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST4.TXDATA_SEL = 2'b00; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST4.CLK_COR_MIN_LAT = 36; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST4.PCS_BIT_SLIP = "FALSE"; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST4.DIGRX_FWDCLK = 2'b00; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST4.DIGRX_SYNC_MODE = "FALSE"; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST4.CLK_COR_SEQ_1_MASK = 4'b0000; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST4.CLK_COR_SEQ_1_4 = 11'b00100011100; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST4.CLK_COR_SEQ_1_3 = 11'b00100011100; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST4.CLK_COR_SEQ_1_2 = 11'b00100011100; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST4.CLK_COR_SEQ_1_1 = 11'b00110111100; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST4.CCCB_ARBITRATOR_DISABLE = "FALSE"; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST4.OPPOSITE_SELECT = "FALSE"; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST4.POWER_ENABLE = "TRUE"; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST4.CHAN_BOND_SEQ_2_MASK = 4'b0000; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST4.CHAN_BOND_SEQ_2_4 = 11'b00000000000; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST4.CHAN_BOND_SEQ_2_3 = 11'b00000000000; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST4.CHAN_BOND_SEQ_2_2 = 11'b00000000000; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST4.CHAN_BOND_SEQ_2_1 = 11'b00000000000; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST4.TX_BUFFER_USE = "TRUE"; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST4.RX_BUFFER_USE = "TRUE"; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST4.CHAN_BOND_SEQ_LEN = 4; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST4.CHAN_BOND_SEQ_2_USE = "FALSE"; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST4.CHAN_BOND_ONE_SHOT = "FALSE"; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST4.CHAN_BOND_MODE = "SLAVE_1_HOP"; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST4.CHAN_BOND_LIMIT = 6; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST4.CHAN_BOND_SEQ_1_MASK = 4'b0000; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST4.CHAN_BOND_SEQ_1_4 = 11'b00110111100; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST4.CHAN_BOND_SEQ_1_3 = 11'b00001000101; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST4.CHAN_BOND_SEQ_1_2 = 11'b00001000101; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST4.CHAN_BOND_SEQ_1_1 = 11'b00001000101; + defparam plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST4.GT11_MODE = "B"; + GT11 plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST4 ( + .RXCRCPD(plm_v4f_mgt_gt11_by4_VCC_773), + .RXBUFERR(NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST4_RXBUFERR_UNCONNECTED), + .TXSYNC(plm_v4f_mgt_reg_tx_sync_756), + .POWERDOWN(plm_v4f_mgt_gt11_by4_GND_772), + .TXUSRCLK2(plm_v4f_mgt_mgtdiv2_clk), + .ENPCOMMAALIGN(plm_v4f_mgt_gt11_by4_VCC_773), + .RXPOLARITY(plm_rx3_polarity), + .ENMCOMMAALIGN(plm_v4f_mgt_gt11_by4_VCC_773), + .TXBUFERR(NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST4_TXBUFERR_UNCONNECTED), + .TXCRCPD(plm_v4f_mgt_gt11_by4_VCC_773), + .RXSIGDET(plm_v4f_mgt_rx3_sigdet_n_async), + .TXCLKSTABLE(plm_v4f_mgt_gt11_by4_VCC_773), + .RXUSRCLK2(plm_v4f_mgt_mgtdiv2_clk), + .TXPOLARITY(plm_v4f_mgt_gt11_by4_GND_772), + .DWE(plm_v4f_mgt_gt3_dwe), + .RXREALIGN(NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST4_RXREALIGN_UNCONNECTED), + .TXGEARBOX64B66BUSE(plm_v4f_mgt_gt11_by4_GND_772), + .RXCYCLELIMIT(NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST4_RXCYCLELIMIT_UNCONNECTED), + .RXRESET(plm_v4f_mgt_reg_rx3_pcs_init_752), + .TXCYCLELIMIT(NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST4_TXCYCLELIMIT_UNCONNECTED), + .TXCALFAIL(NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST4_TXCALFAIL_UNCONNECTED), + .RXUSRCLK(plm_v4f_mgt_mgtdiv2_clk), + .RXDEC64B66BUSE(plm_v4f_mgt_gt11_by4_GND_772), + .RXPCSHCLKOUT(NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST4_RXPCSHCLKOUT_UNCONNECTED), + .TXPCSHCLKOUT(NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST4_TXPCSHCLKOUT_UNCONNECTED), + .RXCOMMADETUSE(plm_v4f_mgt_gt11_by4_VCC_773), + .DCLK(plm_v4f_mgt_cal_clk), + .TXCRCINIT(plm_v4f_mgt_gt11_by4_GND_772), + .TXUSRCLK(plm_v4f_mgt_mgtdiv2_clk), + .RXCALFAIL(NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST4_RXCALFAIL_UNCONNECTED), + .RXPMARESET(plm_v4f_mgt_reg_pma_768), + .RX1N(pci_exp_rxn_6086[3]), + .RX1P(pci_exp_rxp_6085[3]), + .TXRESET(plm_v4f_mgt_reg_tx_pcs_init_758), + .RXSLIDE(plm_v4f_mgt_gt11_by4_GND_772), + .TXPMARESET(plm_v4f_mgt_reg_pma_768), + .TXCRCINTCLK(plm_v4f_mgt_gt11_by4_GND_772), + .RXCRCINIT(plm_v4f_mgt_gt11_by4_GND_772), + .RXDEC8B10BUSE(plm_v4f_mgt_gt11_by4_VCC_773), + .RXCLKSTABLE(plm_v4f_mgt_gt11_by4_VCC_773), + .RXLOCK(plm_v4f_mgt_pma_rxlock3), + .TXCRCDATAVALID(plm_v4f_mgt_gt11_by4_GND_772), + .GREFCLK(plm_v4f_mgt_mgtdiv2_clk), + .ENCHANSYNC(plm_v4f_mgt_gt11_by4_VCC_773), + .DEN(plm_v4f_mgt_gt3_den), + .RXMCLK(NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST4_RXMCLK_UNCONNECTED), + .RXCOMMADET(NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST4_RXCOMMADET_UNCONNECTED), + .TXOUTCLK1(NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST4_TXOUTCLK1_UNCONNECTED), + .TXOUTCLK2(NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST4_TXOUTCLK2_UNCONNECTED), + .RXCRCRESET(plm_v4f_mgt_gt11_by4_VCC_773), + .RXCRCCLK(plm_v4f_mgt_gt11_by4_GND_772), + .TXENC64B66BUSE(plm_v4f_mgt_gt11_by4_GND_772), + .TXINHIBIT(plm_v4f_mgt_gt11_by4_GND_772), + .RXRECCLK1(NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST4_RXRECCLK1_UNCONNECTED), + .RXRECCLK2(NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST4_RXRECCLK2_UNCONNECTED), + .TXLOCK(plm_v4f_mgt_pma_txlock3), + .TXCRCRESET(plm_v4f_mgt_gt11_by4_VCC_773), + .RXDESCRAM64B66BUSE(plm_v4f_mgt_gt11_by4_GND_772), + .RXBLOCKSYNC64B66BUSE(plm_v4f_mgt_gt11_by4_GND_772), + .RXIGNOREBTF(plm_v4f_mgt_gt11_by4_GND_772), + .TXCRCCLK(plm_v4f_mgt_gt11_by4_GND_772), + .RXCRCDATAVALID(plm_v4f_mgt_gt11_by4_GND_772), + .TXSCRAM64B66BUSE(plm_v4f_mgt_gt11_by4_GND_772), + .RXCRCINTCLK(plm_v4f_mgt_gt11_by4_GND_772), + .RXSYNC(plm_v4f_mgt_gt11_by4_GND_772), + .DRDY(plm_v4f_mgt_gt3_drdy), + .TXENC8B10BUSE(plm_v4f_mgt_gt11_by4_VCC_773), + .REFCLK1(sys_clkz), + .TXENOOB(plm_v4f_mgt_reg_tee3_dlyline[23]), + .REFCLK2(plm_v4f_mgt_gt11_by4_GND_772), + .TX1N(pci_exp_txn_6084[3]), + .TX1P(pci_exp_txp_6083[3]), + .RXSTATUS({plm_v4f_mgt_rx3_rxstatus[5], NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST4_RXSTATUS_4__UNCONNECTED, +NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST4_RXSTATUS_3__UNCONNECTED, NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST4_RXSTATUS_2__UNCONNECTED, +NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST4_RXSTATUS_1__UNCONNECTED, NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST4_RXSTATUS_0__UNCONNECTED}), + .RXNOTINTABLE({NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST4_RXNOTINTABLE_7__UNCONNECTED, +NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST4_RXNOTINTABLE_6__UNCONNECTED, NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST4_RXNOTINTABLE_5__UNCONNECTED, +NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST4_RXNOTINTABLE_4__UNCONNECTED, plm_v4f_mgt_wrx3_ntable[3], plm_v4f_mgt_wrx3_ntable[2], +plm_v4f_mgt_wrx3_ntable[1], plm_v4f_mgt_wrx3_ntable[0]}), + .DADDR({plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_VCC_773, plm_v4f_mgt_gt3_daddr[5], plm_v4f_mgt_gt3_daddr[4], plm_v4f_mgt_gt3_daddr[3], +plm_v4f_mgt_gt3_daddr[2], plm_v4f_mgt_gt3_daddr[1], plm_v4f_mgt_gt3_daddr[4]}), + .TXDATAWIDTH({plm_v4f_mgt_gt11_by4_VCC_773, plm_v4f_mgt_gt11_by4_GND_772}), + .RXCRCOUT({NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST4_RXCRCOUT_31__UNCONNECTED, +NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST4_RXCRCOUT_30__UNCONNECTED, NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST4_RXCRCOUT_29__UNCONNECTED, +NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST4_RXCRCOUT_28__UNCONNECTED, NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST4_RXCRCOUT_27__UNCONNECTED, +NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST4_RXCRCOUT_26__UNCONNECTED, NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST4_RXCRCOUT_25__UNCONNECTED, +NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST4_RXCRCOUT_24__UNCONNECTED, NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST4_RXCRCOUT_23__UNCONNECTED, +NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST4_RXCRCOUT_22__UNCONNECTED, NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST4_RXCRCOUT_21__UNCONNECTED, +NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST4_RXCRCOUT_20__UNCONNECTED, NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST4_RXCRCOUT_19__UNCONNECTED, +NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST4_RXCRCOUT_18__UNCONNECTED, NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST4_RXCRCOUT_17__UNCONNECTED, +NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST4_RXCRCOUT_16__UNCONNECTED, NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST4_RXCRCOUT_15__UNCONNECTED, +NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST4_RXCRCOUT_14__UNCONNECTED, NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST4_RXCRCOUT_13__UNCONNECTED, +NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST4_RXCRCOUT_12__UNCONNECTED, NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST4_RXCRCOUT_11__UNCONNECTED, +NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST4_RXCRCOUT_10__UNCONNECTED, NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST4_RXCRCOUT_9__UNCONNECTED, +NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST4_RXCRCOUT_8__UNCONNECTED, NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST4_RXCRCOUT_7__UNCONNECTED, +NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST4_RXCRCOUT_6__UNCONNECTED, NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST4_RXCRCOUT_5__UNCONNECTED, +NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST4_RXCRCOUT_4__UNCONNECTED, NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST4_RXCRCOUT_3__UNCONNECTED, +NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST4_RXCRCOUT_2__UNCONNECTED, NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST4_RXCRCOUT_1__UNCONNECTED, +NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST4_RXCRCOUT_0__UNCONNECTED}), + .TXINTDATAWIDTH({plm_v4f_mgt_gt11_by4_VCC_773, plm_v4f_mgt_gt11_by4_VCC_773}), + .DI({plm_v4f_mgt_gt3_do[15], plm_v4f_mgt_gt3_do[14], plm_v4f_mgt_gt3_do[13], plm_v4f_mgt_gt3_do[12], plm_v4f_mgt_gt3_do[11], +plm_v4f_mgt_gt3_do[10], plm_v4f_mgt_gt3_do[9], plm_v4f_mgt_gt3_do[8], plm_v4f_mgt_gt3_do[7], plm_v4f_mgt_gt3_do[6], plm_v4f_mgt_gt3_do[5], +plm_v4f_mgt_gt3_do[4], plm_v4f_mgt_gt3_do[3], plm_v4f_mgt_gt3_do[2], plm_v4f_mgt_gt3_do[1], plm_v4f_mgt_gt3_do[0]}), + .DO({plm_v4f_mgt_gt3_di[15], plm_v4f_mgt_gt3_di[14], plm_v4f_mgt_gt3_di[13], plm_v4f_mgt_gt3_di[12], plm_v4f_mgt_gt3_di[11], +plm_v4f_mgt_gt3_di[10], plm_v4f_mgt_gt3_di[9], plm_v4f_mgt_gt3_di[8], plm_v4f_mgt_gt3_di[7], plm_v4f_mgt_gt3_di[6], plm_v4f_mgt_gt3_di[5], +plm_v4f_mgt_gt3_di[4], plm_v4f_mgt_gt3_di[3], plm_v4f_mgt_gt3_di[2], plm_v4f_mgt_gt3_di[1], plm_v4f_mgt_gt3_di[0]}), + .TXCRCOUT({NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST4_TXCRCOUT_31__UNCONNECTED, +NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST4_TXCRCOUT_30__UNCONNECTED, NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST4_TXCRCOUT_29__UNCONNECTED, +NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST4_TXCRCOUT_28__UNCONNECTED, NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST4_TXCRCOUT_27__UNCONNECTED, +NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST4_TXCRCOUT_26__UNCONNECTED, NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST4_TXCRCOUT_25__UNCONNECTED, +NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST4_TXCRCOUT_24__UNCONNECTED, NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST4_TXCRCOUT_23__UNCONNECTED, +NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST4_TXCRCOUT_22__UNCONNECTED, NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST4_TXCRCOUT_21__UNCONNECTED, +NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST4_TXCRCOUT_20__UNCONNECTED, NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST4_TXCRCOUT_19__UNCONNECTED, +NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST4_TXCRCOUT_18__UNCONNECTED, NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST4_TXCRCOUT_17__UNCONNECTED, +NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST4_TXCRCOUT_16__UNCONNECTED, NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST4_TXCRCOUT_15__UNCONNECTED, +NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST4_TXCRCOUT_14__UNCONNECTED, NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST4_TXCRCOUT_13__UNCONNECTED, +NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST4_TXCRCOUT_12__UNCONNECTED, NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST4_TXCRCOUT_11__UNCONNECTED, +NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST4_TXCRCOUT_10__UNCONNECTED, NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST4_TXCRCOUT_9__UNCONNECTED, +NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST4_TXCRCOUT_8__UNCONNECTED, NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST4_TXCRCOUT_7__UNCONNECTED, +NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST4_TXCRCOUT_6__UNCONNECTED, NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST4_TXCRCOUT_5__UNCONNECTED, +NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST4_TXCRCOUT_4__UNCONNECTED, NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST4_TXCRCOUT_3__UNCONNECTED, +NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST4_TXCRCOUT_2__UNCONNECTED, NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST4_TXCRCOUT_1__UNCONNECTED, +NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST4_TXCRCOUT_0__UNCONNECTED}), + .COMBUSIN({plm_v4f_mgt_gt11_by4_COMBUSOUT_BLK3[15], plm_v4f_mgt_gt11_by4_COMBUSOUT_BLK3[14], plm_v4f_mgt_gt11_by4_COMBUSOUT_BLK3[13], +plm_v4f_mgt_gt11_by4_COMBUSOUT_BLK3[12], plm_v4f_mgt_gt11_by4_COMBUSOUT_BLK3[11], plm_v4f_mgt_gt11_by4_COMBUSOUT_BLK3[10], +plm_v4f_mgt_gt11_by4_COMBUSOUT_BLK3[9], plm_v4f_mgt_gt11_by4_COMBUSOUT_BLK3[8], plm_v4f_mgt_gt11_by4_COMBUSOUT_BLK3[7], +plm_v4f_mgt_gt11_by4_COMBUSOUT_BLK3[6], plm_v4f_mgt_gt11_by4_COMBUSOUT_BLK3[5], plm_v4f_mgt_gt11_by4_COMBUSOUT_BLK3[4], +plm_v4f_mgt_gt11_by4_COMBUSOUT_BLK3[3], plm_v4f_mgt_gt11_by4_COMBUSOUT_BLK3[2], plm_v4f_mgt_gt11_by4_COMBUSOUT_BLK3[1], +plm_v4f_mgt_gt11_by4_COMBUSOUT_BLK3[0]}), + .COMBUSOUT({plm_v4f_mgt_gt11_by4_COMBUSOUT_BLK4[15], plm_v4f_mgt_gt11_by4_COMBUSOUT_BLK4[14], plm_v4f_mgt_gt11_by4_COMBUSOUT_BLK4[13], +plm_v4f_mgt_gt11_by4_COMBUSOUT_BLK4[12], plm_v4f_mgt_gt11_by4_COMBUSOUT_BLK4[11], plm_v4f_mgt_gt11_by4_COMBUSOUT_BLK4[10], +plm_v4f_mgt_gt11_by4_COMBUSOUT_BLK4[9], plm_v4f_mgt_gt11_by4_COMBUSOUT_BLK4[8], plm_v4f_mgt_gt11_by4_COMBUSOUT_BLK4[7], +plm_v4f_mgt_gt11_by4_COMBUSOUT_BLK4[6], plm_v4f_mgt_gt11_by4_COMBUSOUT_BLK4[5], plm_v4f_mgt_gt11_by4_COMBUSOUT_BLK4[4], +plm_v4f_mgt_gt11_by4_COMBUSOUT_BLK4[3], plm_v4f_mgt_gt11_by4_COMBUSOUT_BLK4[2], plm_v4f_mgt_gt11_by4_COMBUSOUT_BLK4[1], +plm_v4f_mgt_gt11_by4_COMBUSOUT_BLK4[0]}), + .RXDATA({NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST4_RXDATA_63__UNCONNECTED, NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST4_RXDATA_62__UNCONNECTED +, NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST4_RXDATA_61__UNCONNECTED, NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST4_RXDATA_60__UNCONNECTED, +NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST4_RXDATA_59__UNCONNECTED, NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST4_RXDATA_58__UNCONNECTED, +NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST4_RXDATA_57__UNCONNECTED, NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST4_RXDATA_56__UNCONNECTED, +NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST4_RXDATA_55__UNCONNECTED, NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST4_RXDATA_54__UNCONNECTED, +NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST4_RXDATA_53__UNCONNECTED, NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST4_RXDATA_52__UNCONNECTED, +NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST4_RXDATA_51__UNCONNECTED, NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST4_RXDATA_50__UNCONNECTED, +NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST4_RXDATA_49__UNCONNECTED, NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST4_RXDATA_48__UNCONNECTED, +NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST4_RXDATA_47__UNCONNECTED, NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST4_RXDATA_46__UNCONNECTED, +NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST4_RXDATA_45__UNCONNECTED, NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST4_RXDATA_44__UNCONNECTED, +NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST4_RXDATA_43__UNCONNECTED, NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST4_RXDATA_42__UNCONNECTED, +NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST4_RXDATA_41__UNCONNECTED, NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST4_RXDATA_40__UNCONNECTED, +NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST4_RXDATA_39__UNCONNECTED, NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST4_RXDATA_38__UNCONNECTED, +NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST4_RXDATA_37__UNCONNECTED, NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST4_RXDATA_36__UNCONNECTED, +NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST4_RXDATA_35__UNCONNECTED, NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST4_RXDATA_34__UNCONNECTED, +NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST4_RXDATA_33__UNCONNECTED, NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST4_RXDATA_32__UNCONNECTED, +plm_v4f_mgt_wrx3_data[31], plm_v4f_mgt_wrx3_data[30], plm_v4f_mgt_wrx3_data[29], plm_v4f_mgt_wrx3_data[28], plm_v4f_mgt_wrx3_data[27], +plm_v4f_mgt_wrx3_data[26], plm_v4f_mgt_wrx3_data[25], plm_v4f_mgt_wrx3_data[24], plm_v4f_mgt_wrx3_data[23], plm_v4f_mgt_wrx3_data[22], +plm_v4f_mgt_wrx3_data[21], plm_v4f_mgt_wrx3_data[20], plm_v4f_mgt_wrx3_data[19], plm_v4f_mgt_wrx3_data[18], plm_v4f_mgt_wrx3_data[17], +plm_v4f_mgt_wrx3_data[16], plm_v4f_mgt_wrx3_data[15], plm_v4f_mgt_wrx3_data[14], plm_v4f_mgt_wrx3_data[13], plm_v4f_mgt_wrx3_data[12], +plm_v4f_mgt_wrx3_data[11], plm_v4f_mgt_wrx3_data[10], plm_v4f_mgt_wrx3_data[9], plm_v4f_mgt_wrx3_data[8], plm_v4f_mgt_wrx3_data[7], +plm_v4f_mgt_wrx3_data[6], plm_v4f_mgt_wrx3_data[5], plm_v4f_mgt_wrx3_data[4], plm_v4f_mgt_wrx3_data[3], plm_v4f_mgt_wrx3_data[2], +plm_v4f_mgt_wrx3_data[1], plm_v4f_mgt_wrx3_data[0]}), + .TXRUNDISP({NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST4_TXRUNDISP_7__UNCONNECTED, +NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST4_TXRUNDISP_6__UNCONNECTED, NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST4_TXRUNDISP_5__UNCONNECTED, +NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST4_TXRUNDISP_4__UNCONNECTED, NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST4_TXRUNDISP_3__UNCONNECTED, +NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST4_TXRUNDISP_2__UNCONNECTED, NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST4_TXRUNDISP_1__UNCONNECTED, +NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST4_TXRUNDISP_0__UNCONNECTED}), + .RXINTDATAWIDTH({plm_v4f_mgt_gt11_by4_VCC_773, plm_v4f_mgt_gt11_by4_VCC_773}), + .RXDATAWIDTH({plm_v4f_mgt_gt11_by4_VCC_773, plm_v4f_mgt_gt11_by4_GND_772}), + .RXLOSSOFSYNC({NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST4_RXLOSSOFSYNC_1__UNCONNECTED, +NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST4_RXLOSSOFSYNC_0__UNCONNECTED}), + .RXRUNDISP({NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST4_RXRUNDISP_7__UNCONNECTED, +NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST4_RXRUNDISP_6__UNCONNECTED, NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST4_RXRUNDISP_5__UNCONNECTED, +NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST4_RXRUNDISP_4__UNCONNECTED, plm_v4f_mgt_wrx3_run_disp[3], plm_v4f_mgt_wrx3_run_disp[2], +plm_v4f_mgt_wrx3_run_disp[1], plm_v4f_mgt_wrx3_run_disp[0]}), + .TXDATA({plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, +plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, +plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, +plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, +plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, +plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, +plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, plm_tx3_data[7], plm_tx3_data[6], plm_tx3_data[5], +plm_tx3_data[4], plm_tx3_data[3], plm_tx3_data[2], plm_tx3_data[1], plm_tx3_data[0], plm_tx3_data[15], plm_tx3_data[14], plm_tx3_data[13], +plm_tx3_data[12], plm_tx3_data[11], plm_tx3_data[10], plm_tx3_data[9], plm_tx3_data[8], plm_v4f_mgt_dtx3_data[7], plm_v4f_mgt_dtx3_data[6], +plm_v4f_mgt_dtx3_data[5], plm_v4f_mgt_dtx3_data[4], plm_v4f_mgt_dtx3_data[3], plm_v4f_mgt_dtx3_data[2], plm_v4f_mgt_dtx3_data[1], +plm_v4f_mgt_dtx3_data[0], plm_v4f_mgt_dtx3_data[15], plm_v4f_mgt_dtx3_data[14], plm_v4f_mgt_dtx3_data[13], plm_v4f_mgt_dtx3_data[12], +plm_v4f_mgt_dtx3_data[11], plm_v4f_mgt_dtx3_data[10], plm_v4f_mgt_dtx3_data[9], plm_v4f_mgt_dtx3_data[8]}), + .TXCHARDISPVAL({plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, +plm_GND_702, plm_GND_702, plm_v4f_mgt_dtx3_char_disp_val[0], plm_v4f_mgt_dtx3_char_disp_val[1]}), + .LOOPBACK({plm_v4f_mgt_loopback3[1], plm_v4f_mgt_loopback3[1]}), + .CHBONDI({plm_v4f_mgt_gt11_by4_CHBONDO_2[4], plm_v4f_mgt_gt11_by4_CHBONDO_2[3], plm_v4f_mgt_gt11_by4_CHBONDO_2[2], +plm_v4f_mgt_gt11_by4_CHBONDO_2[1], plm_v4f_mgt_gt11_by4_CHBONDO_2[0]}), + .TXCRCDATAWIDTH({plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772}), + .CHBONDO({NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST4_CHBONDO_4__UNCONNECTED, NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST4_CHBONDO_3__UNCONNECTED +, NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST4_CHBONDO_2__UNCONNECTED, NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST4_CHBONDO_1__UNCONNECTED, +NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST4_CHBONDO_0__UNCONNECTED}), + .TXCHARISK({plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, +plm_tx3_char_is_k[0], plm_tx3_char_is_k[1], plm_v4f_mgt_dtx3_char_is_k[0], plm_v4f_mgt_dtx3_char_is_k[1]}), + .TXBYPASS8B10B({plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, +plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772}), + .RXCRCIN({plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, +plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, +plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, +plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, +plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, +plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, +plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, +plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, +plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, +plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, +plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, +plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, +plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772}) +, + .RXCHARISK({NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST4_RXCHARISK_7__UNCONNECTED, +NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST4_RXCHARISK_6__UNCONNECTED, NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST4_RXCHARISK_5__UNCONNECTED, +NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST4_RXCHARISK_4__UNCONNECTED, plm_v4f_mgt_wrx3_char_is_k[3], plm_v4f_mgt_wrx3_char_is_k[2], +plm_v4f_mgt_wrx3_char_is_k[1], plm_v4f_mgt_wrx3_char_is_k[0]}), + .TXCHARDISPMODE({plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, +plm_GND_702, plm_GND_702, plm_v4f_mgt_dtx3_char_disp_mode[0], plm_v4f_mgt_dtx3_char_disp_mode[1]}), + .RXCRCDATAWIDTH({plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772}), + .RXDISPERR({NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST4_RXDISPERR_7__UNCONNECTED, +NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST4_RXDISPERR_6__UNCONNECTED, NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST4_RXDISPERR_5__UNCONNECTED, +NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST4_RXDISPERR_4__UNCONNECTED, plm_v4f_mgt_wrx3_disp_err[3], plm_v4f_mgt_wrx3_disp_err[2], +plm_v4f_mgt_wrx3_disp_err[1], plm_v4f_mgt_wrx3_disp_err[0]}), + .RXCHARISCOMMA({NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST4_RXCHARISCOMMA_7__UNCONNECTED, +NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST4_RXCHARISCOMMA_6__UNCONNECTED, NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST4_RXCHARISCOMMA_5__UNCONNECTED, +NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST4_RXCHARISCOMMA_4__UNCONNECTED, NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST4_RXCHARISCOMMA_3__UNCONNECTED, +NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST4_RXCHARISCOMMA_2__UNCONNECTED, NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST4_RXCHARISCOMMA_1__UNCONNECTED, +NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST4_RXCHARISCOMMA_0__UNCONNECTED}), + .TXCRCIN({plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, +plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, +plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, +plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, +plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, +plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, +plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, +plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, +plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, +plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, +plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, +plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, +plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772, plm_v4f_mgt_gt11_by4_GND_772}) +, + .TXKERR({NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST4_TXKERR_7__UNCONNECTED, NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST4_TXKERR_6__UNCONNECTED, +NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST4_TXKERR_5__UNCONNECTED, NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST4_TXKERR_4__UNCONNECTED, +NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST4_TXKERR_3__UNCONNECTED, NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST4_TXKERR_2__UNCONNECTED, +NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST4_TXKERR_1__UNCONNECTED, NLW_plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST4_TXKERR_0__UNCONNECTED}) + ); + VCC plm_v4f_mgt_for_v1_4_cal_inst0_VCC ( + .P(plm_v4f_mgt_for_v1_4_cal_inst0_VCC_812) + ); + GND plm_v4f_mgt_for_v1_4_cal_inst0_GND ( + .G(plm_v4f_mgt_for_v1_4_cal_inst0_GND_808) + ); + FDS plm_v4f_mgt_for_v1_4_cal_inst0_drp_state_0_ ( + .C(plm_v4f_mgt_cal_clk), + .D(plm_v4f_mgt_for_v1_4_cal_inst0_N_2439_i_802), + .Q(plm_v4f_mgt_for_v1_4_cal_inst0_drp_state_0__804), + .S(plm_v4f_mgt_for_v1_4_cal_inst0_reset_r[0]) + ); + FDR plm_v4f_mgt_for_v1_4_cal_inst0_drp_state_1_ ( + .C(plm_v4f_mgt_cal_clk), + .D(plm_v4f_mgt_for_v1_4_cal_inst0_N_1013_i), + .Q(plm_v4f_mgt_for_v1_4_cal_inst0_drp_state_1__799), + .R(plm_v4f_mgt_for_v1_4_cal_inst0_reset_r[0]) + ); + FDR plm_v4f_mgt_for_v1_4_cal_inst0_drp_state_2_ ( + .C(plm_v4f_mgt_cal_clk), + .D(plm_v4f_mgt_for_v1_4_cal_inst0_drp_next_state_0_sqmuxa_1), + .Q(plm_v4f_mgt_gt0_dwe), + .R(plm_v4f_mgt_for_v1_4_cal_inst0_reset_r[0]) + ); + FDR plm_v4f_mgt_for_v1_4_cal_inst0_drp_state_3_ ( + .C(plm_v4f_mgt_cal_clk), + .D(plm_v4f_mgt_for_v1_4_cal_inst0_N_2393_i_797), + .Q(plm_v4f_mgt_for_v1_4_cal_inst0_drp_state_3__798), + .R(plm_v4f_mgt_for_v1_4_cal_inst0_reset_r[0]) + ); + FDR plm_v4f_mgt_for_v1_4_cal_inst0_drp_state_4_ ( + .C(plm_v4f_mgt_cal_clk), + .D(plm_v4f_mgt_for_v1_4_cal_inst0_drp_next_state_0_sqmuxa), + .Q(plm_v4f_mgt_for_v1_4_cal_inst0_drp_state_4__803), + .R(plm_v4f_mgt_for_v1_4_cal_inst0_reset_r[0]) + ); + FDR plm_v4f_mgt_for_v1_4_cal_inst0_sd_state_3_ ( + .C(plm_v4f_mgt_cal_clk), + .D(plm_v4f_mgt_for_v1_4_cal_inst0_N_1689_i), + .Q(plm_v4f_mgt_for_v1_4_cal_inst0_sd_state_3__795), + .R(plm_v4f_mgt_for_v1_4_cal_inst0_reset_r[0]) + ); + FDR plm_v4f_mgt_for_v1_4_cal_inst0_sd_state_5_ ( + .C(plm_v4f_mgt_cal_clk), + .D(plm_v4f_mgt_for_v1_4_cal_inst0_sd_next_state_0_sqmuxa_1), + .Q(plm_v4f_mgt_for_v1_4_cal_inst0_sd_state_5__793), + .R(plm_v4f_mgt_for_v1_4_cal_inst0_reset_r[0]) + ); + FDR plm_v4f_mgt_for_v1_4_cal_inst0_sd_state_6_ ( + .C(plm_v4f_mgt_cal_clk), + .D(plm_v4f_mgt_for_v1_4_cal_inst0_N_1688_i_791), + .Q(plm_v4f_mgt_for_v1_4_cal_inst0_sd_state_6__792), + .R(plm_v4f_mgt_for_v1_4_cal_inst0_reset_r[0]) + ); + FDR plm_v4f_mgt_for_v1_4_cal_inst0_sd_state_7_ ( + .C(plm_v4f_mgt_cal_clk), + .D(plm_v4f_mgt_for_v1_4_cal_inst0_sd_next_state_0_i_a2_0_a2_0_a2[7]), + .Q(plm_v4f_mgt_for_v1_4_cal_inst0_sd_state_7__790), + .R(plm_v4f_mgt_for_v1_4_cal_inst0_reset_r[0]) + ); + FDR plm_v4f_mgt_for_v1_4_cal_inst0_sd_state_8_ ( + .C(plm_v4f_mgt_cal_clk), + .D(plm_v4f_mgt_for_v1_4_cal_inst0_N_2449_i_788), + .Q(plm_v4f_mgt_for_v1_4_cal_inst0_sd_state_8__789), + .R(plm_v4f_mgt_for_v1_4_cal_inst0_reset_r[0]) + ); + FDR plm_v4f_mgt_for_v1_4_cal_inst0_sd_state_9_ ( + .C(plm_v4f_mgt_cal_clk), + .D(plm_v4f_mgt_for_v1_4_cal_inst0_sd_next_state_0_sqmuxa_2), + .Q(plm_v4f_mgt_for_v1_4_cal_inst0_sd_state_9__787), + .R(plm_v4f_mgt_for_v1_4_cal_inst0_reset_r[0]) + ); + FDR plm_v4f_mgt_for_v1_4_cal_inst0_sd_state_10_ ( + .C(plm_v4f_mgt_cal_clk), + .D(plm_v4f_mgt_for_v1_4_cal_inst0_N_1686_i_785), + .Q(plm_v4f_mgt_for_v1_4_cal_inst0_sd_state_10__786), + .R(plm_v4f_mgt_for_v1_4_cal_inst0_reset_r[0]) + ); + FDR plm_v4f_mgt_for_v1_4_cal_inst0_sd_state_12_ ( + .C(plm_v4f_mgt_cal_clk), + .D(plm_v4f_mgt_for_v1_4_cal_inst0_sd_next_state_0_sqmuxa_3), + .Q(plm_v4f_mgt_for_v1_4_cal_inst0_sd_state_12__783), + .R(plm_v4f_mgt_for_v1_4_cal_inst0_reset_r[0]) + ); + FDR plm_v4f_mgt_for_v1_4_cal_inst0_sd_state_13_ ( + .C(plm_v4f_mgt_cal_clk), + .D(plm_v4f_mgt_for_v1_4_cal_inst0_N_2448_i_781), + .Q(plm_v4f_mgt_for_v1_4_cal_inst0_sd_state_13__782), + .R(plm_v4f_mgt_for_v1_4_cal_inst0_reset_r[0]) + ); + FDR plm_v4f_mgt_for_v1_4_cal_inst0_GT_DEN ( + .C(plm_v4f_mgt_cal_clk), + .D(plm_v4f_mgt_for_v1_4_cal_inst0_N_1015_i), + .Q(plm_v4f_mgt_gt0_den), + .R(plm_v4f_mgt_for_v1_4_cal_inst0_reset_r[0]) + ); + FDR plm_v4f_mgt_for_v1_4_cal_inst0_sd_write ( + .C(plm_v4f_mgt_cal_clk), + .D(plm_v4f_mgt_for_v1_4_cal_inst0_N_1827_i_780), + .Q(plm_v4f_mgt_for_v1_4_cal_inst0_sd_write_800), + .R(plm_v4f_mgt_for_v1_4_cal_inst0_N_1829_i_774) + ); + FDR plm_v4f_mgt_for_v1_4_cal_inst0_sd_read ( + .C(plm_v4f_mgt_cal_clk), + .D(plm_v4f_mgt_for_v1_4_cal_inst0_N_1828_i_779), + .Q(plm_v4f_mgt_for_v1_4_cal_inst0_sd_read_801), + .R(plm_v4f_mgt_for_v1_4_cal_inst0_N_1829_i_774) + ); + FDR plm_v4f_mgt_for_v1_4_cal_inst0_sd_req ( + .C(plm_v4f_mgt_cal_clk), + .D(plm_v4f_mgt_for_v1_4_cal_inst0_N_1816_i_778), + .Q(plm_v4f_mgt_for_v1_4_cal_inst0_sd_req_776), + .R(plm_v4f_mgt_for_v1_4_cal_inst0_N_1829_i_774) + ); + FDRE plm_v4f_mgt_for_v1_4_cal_inst0_sd_state_11_ ( + .CE(plm_v4f_mgt_for_v1_4_cal_inst0_sd_drp_done_796), + .C(plm_v4f_mgt_cal_clk), + .D(plm_v4f_mgt_for_v1_4_cal_inst0_sd_state_10__786), + .Q(plm_v4f_mgt_for_v1_4_cal_inst0_sd_state_11__784), + .R(plm_v4f_mgt_for_v1_4_cal_inst0_reset_r[0]) + ); + FDRE plm_v4f_mgt_for_v1_4_cal_inst0_sd_state_4_ ( + .CE(plm_v4f_mgt_for_v1_4_cal_inst0_sd_drp_done_796), + .C(plm_v4f_mgt_cal_clk), + .D(plm_v4f_mgt_for_v1_4_cal_inst0_sd_state_3__795), + .Q(plm_v4f_mgt_for_v1_4_cal_inst0_sd_state_4__794), + .R(plm_v4f_mgt_for_v1_4_cal_inst0_reset_r[0]) + ); + FDSE plm_v4f_mgt_for_v1_4_cal_inst0_sd_state_0_ ( + .CE(plm_v4f_mgt_for_v1_4_cal_inst0_sd_state_13__782), + .C(plm_v4f_mgt_cal_clk), + .D(plm_v4f_mgt_for_v1_4_cal_inst0_sd_drp_done_796), + .Q(plm_v4f_mgt_for_v1_4_cal_inst0_sd_state_0__775), + .S(plm_v4f_mgt_for_v1_4_cal_inst0_reset_r[0]) + ); + FDR plm_v4f_mgt_for_v1_4_cal_inst0_cb_state_2_ ( + .C(plm_v4f_mgt_cal_clk), + .D(plm_v4f_mgt_for_v1_4_cal_inst0_cb_statec_i_i_777), + .Q(plm_v4f_mgt_for_v1_4_cal_inst0_cb_state[2]), + .R(plm_v4f_mgt_for_v1_4_cal_inst0_reset_r[0]) + ); + FDR plm_v4f_mgt_for_v1_4_cal_inst0_cb_state_1_ ( + .C(plm_v4f_mgt_cal_clk), + .D(plm_v4f_mgt_for_v1_4_cal_inst0_cb_statec_i), + .Q(plm_v4f_mgt_for_v1_4_cal_inst0_cb_state[1]), + .R(plm_v4f_mgt_for_v1_4_cal_inst0_reset_r[0]) + ); + FDR plm_v4f_mgt_for_v1_4_cal_inst0_sd_drp_done ( + .C(plm_v4f_mgt_cal_clk), + .D(plm_v4f_mgt_gt0_drdy), + .Q(plm_v4f_mgt_for_v1_4_cal_inst0_sd_drp_done_796), + .R(plm_v4f_mgt_for_v1_4_cal_inst0_cb_state_i[2]) + ); + defparam plm_v4f_mgt_for_v1_4_cal_inst0_sd_req_3_0_a2_0_a2.INIT = 4'h1; + LUT2 plm_v4f_mgt_for_v1_4_cal_inst0_sd_req_3_0_a2_0_a2 ( + .I0(plm_v4f_mgt_for_v1_4_cal_inst0_sd_read_801), + .I1(plm_v4f_mgt_for_v1_4_cal_inst0_sd_write_800), + .O(plm_v4f_mgt_for_v1_4_cal_inst0_sd_req_3_0_a2_0_a2_805) + ); + defparam plm_v4f_mgt_for_v1_4_cal_inst0_sd_write_3_0_a2_0_a2_0_o3.INIT = 4'h1; + LUT2 plm_v4f_mgt_for_v1_4_cal_inst0_sd_write_3_0_a2_0_a2_0_o3 ( + .I0(plm_v4f_mgt_for_v1_4_cal_inst0_sd_state_6__792), + .I1(plm_v4f_mgt_for_v1_4_cal_inst0_sd_state_10__786), + .O(plm_v4f_mgt_for_v1_4_cal_inst0_N_1661_i) + ); + defparam plm_v4f_mgt_for_v1_4_cal_inst0_N_1829_i.INIT = 4'hE; + LUT2 plm_v4f_mgt_for_v1_4_cal_inst0_N_1829_i ( + .I0(plm_v4f_mgt_for_v1_4_cal_inst0_sd_drp_done_796), + .I1(plm_v4f_mgt_for_v1_4_cal_inst0_sd_state_0__775), + .O(plm_v4f_mgt_for_v1_4_cal_inst0_N_1829_i_774) + ); + defparam plm_v4f_mgt_for_v1_4_cal_inst0_cb_state_4_i_a2_2_.INIT = 16'h51F3; + LUT4 plm_v4f_mgt_for_v1_4_cal_inst0_cb_state_4_i_a2_2_ ( + .I0(plm_v4f_mgt_for_v1_4_cal_inst0_cb_state[1]), + .I1(plm_v4f_mgt_for_v1_4_cal_inst0_cb_state[2]), + .I2(plm_v4f_mgt_for_v1_4_cal_inst0_gt_drdy_r_806), + .I3(plm_v4f_mgt_for_v1_4_cal_inst0_sd_req_776), + .O(plm_v4f_mgt_for_v1_4_cal_inst0_cb_statec_i) + ); + defparam plm_v4f_mgt_for_v1_4_cal_inst0_sd_wr_wreg_9_0_0_0_o2_12_.INIT = 8'h80; + LUT3 plm_v4f_mgt_for_v1_4_cal_inst0_sd_wr_wreg_9_0_0_0_o2_12_ ( + .I0(plm_v4f_mgt_for_v1_4_cal_inst0_cb_state[2]), + .I1(plm_v4f_mgt_for_v1_4_cal_inst0_sd_read_801), + .I2(plm_v4f_mgt_gt0_drdy), + .O(plm_v4f_mgt_for_v1_4_cal_inst0_N_1642_i) + ); + defparam plm_v4f_mgt_for_v1_4_cal_inst0_GT_DADDR_5_i_0_0_o2_2_.INIT = 8'h02; + LUT3 plm_v4f_mgt_for_v1_4_cal_inst0_GT_DADDR_5_i_0_0_o2_2_ ( + .I0(plm_v4f_mgt_for_v1_4_cal_inst0_N_1661_i), + .I1(plm_v4f_mgt_for_v1_4_cal_inst0_sd_state_4__794), + .I2(plm_v4f_mgt_for_v1_4_cal_inst0_sd_state_8__789), + .O(plm_v4f_mgt_for_v1_4_cal_inst0_N_1662_i) + ); + defparam plm_v4f_mgt_for_v1_4_cal_inst0_sd_wr_wreg_9_i_i_0_m2_1_.INIT = 8'h1B; + LUT3_L plm_v4f_mgt_for_v1_4_cal_inst0_sd_wr_wreg_9_i_i_0_m2_1_ ( + .I0(plm_v4f_mgt_for_v1_4_cal_inst0_N_1642_i), + .I1(plm_v4f_mgt_for_v1_4_cal_inst0_sd_state_5__793), + .I2(plm_v4f_mgt_gt0_di[1]), + .LO(plm_v4f_mgt_for_v1_4_cal_inst0_sd_wr_wreg_9_i_i_0_m2[1]) + ); + defparam plm_v4f_mgt_for_v1_4_cal_inst0_cb_statec_i_i.INIT = 4'h1; + LUT1_L plm_v4f_mgt_for_v1_4_cal_inst0_cb_statec_i_i ( + .I0(plm_v4f_mgt_for_v1_4_cal_inst0_cb_statec_i), + .LO(plm_v4f_mgt_for_v1_4_cal_inst0_cb_statec_i_i_777) + ); + defparam plm_v4f_mgt_for_v1_4_cal_inst0_N_2438_i.INIT = 16'h3733; + LUT4_L plm_v4f_mgt_for_v1_4_cal_inst0_N_2438_i ( + .I0(plm_v4f_mgt_for_v1_4_cal_inst0_N_1642_i), + .I1(plm_v4f_mgt_for_v1_4_cal_inst0_sd_wr_wreg_9_i_i_0_m2[1]), + .I2(plm_v4f_mgt_for_v1_4_cal_inst0_sd_state_9__787), + .I3(plm_v4f_mgt_for_v1_4_cal_inst0_sd_wr_wreg[1]), + .LO(plm_v4f_mgt_for_v1_4_cal_inst0_N_2438_i_807) + ); + defparam plm_v4f_mgt_for_v1_4_cal_inst0_N_2450_i.INIT = 16'hBA10; + LUT4_L plm_v4f_mgt_for_v1_4_cal_inst0_N_2450_i ( + .I0(plm_v4f_mgt_for_v1_4_cal_inst0_N_1642_i), + .I1(plm_v4f_mgt_for_v1_4_cal_inst0_sd_state_12__783), + .I2(plm_v4f_mgt_for_v1_4_cal_inst0_sd_wr_wreg[12]), + .I3(plm_v4f_mgt_gt0_di[12]), + .LO(plm_v4f_mgt_for_v1_4_cal_inst0_N_2450_i_809) + ); + defparam plm_v4f_mgt_for_v1_4_cal_inst0_gt_do_r_4_i_m2_0_a2_0_a2_15_.INIT = 4'h8; + LUT2_L plm_v4f_mgt_for_v1_4_cal_inst0_gt_do_r_4_i_m2_0_a2_0_a2_15_ ( + .I0(plm_v4f_mgt_for_v1_4_cal_inst0_cb_state[2]), + .I1(plm_v4f_mgt_for_v1_4_cal_inst0_sd_wr_wreg[15]), + .LO(plm_v4f_mgt_for_v1_4_cal_inst0_gt_do_r_4_i_m2_0_a2_0_a2_2_15_) + ); + defparam plm_v4f_mgt_for_v1_4_cal_inst0_gt_do_r_4_i_m2_0_a2_0_a2_14_.INIT = 4'h8; + LUT2_L plm_v4f_mgt_for_v1_4_cal_inst0_gt_do_r_4_i_m2_0_a2_0_a2_14_ ( + .I0(plm_v4f_mgt_for_v1_4_cal_inst0_cb_state[2]), + .I1(plm_v4f_mgt_for_v1_4_cal_inst0_sd_wr_wreg[14]), + .LO(plm_v4f_mgt_for_v1_4_cal_inst0_gt_do_r_4_i_m2_0_a2_0_a2_2_14_) + ); + defparam plm_v4f_mgt_for_v1_4_cal_inst0_gt_do_r_4_i_m2_0_a2_0_a2_13_.INIT = 4'h8; + LUT2_L plm_v4f_mgt_for_v1_4_cal_inst0_gt_do_r_4_i_m2_0_a2_0_a2_13_ ( + .I0(plm_v4f_mgt_for_v1_4_cal_inst0_cb_state[2]), + .I1(plm_v4f_mgt_for_v1_4_cal_inst0_sd_wr_wreg[13]), + .LO(plm_v4f_mgt_for_v1_4_cal_inst0_gt_do_r_4_i_m2_0_a2_0_a2_2_13_) + ); + defparam plm_v4f_mgt_for_v1_4_cal_inst0_gt_do_r_4_i_m2_0_a2_0_a2_12_.INIT = 4'h8; + LUT2_L plm_v4f_mgt_for_v1_4_cal_inst0_gt_do_r_4_i_m2_0_a2_0_a2_12_ ( + .I0(plm_v4f_mgt_for_v1_4_cal_inst0_cb_state[2]), + .I1(plm_v4f_mgt_for_v1_4_cal_inst0_sd_wr_wreg[12]), + .LO(plm_v4f_mgt_for_v1_4_cal_inst0_gt_do_r_4_i_m2_0_a2_0_a2_12__810) + ); + defparam plm_v4f_mgt_for_v1_4_cal_inst0_gt_do_r_4_i_m2_0_a2_0_a2_11_.INIT = 4'h8; + LUT2_L plm_v4f_mgt_for_v1_4_cal_inst0_gt_do_r_4_i_m2_0_a2_0_a2_11_ ( + .I0(plm_v4f_mgt_for_v1_4_cal_inst0_cb_state[2]), + .I1(plm_v4f_mgt_for_v1_4_cal_inst0_sd_wr_wreg[11]), + .LO(plm_v4f_mgt_for_v1_4_cal_inst0_gt_do_r_4_i_m2_0_a2_0_a2_2_11_) + ); + defparam plm_v4f_mgt_for_v1_4_cal_inst0_gt_do_r_4_i_m2_0_a2_0_a2_10_.INIT = 4'h8; + LUT2_L plm_v4f_mgt_for_v1_4_cal_inst0_gt_do_r_4_i_m2_0_a2_0_a2_10_ ( + .I0(plm_v4f_mgt_for_v1_4_cal_inst0_cb_state[2]), + .I1(plm_v4f_mgt_for_v1_4_cal_inst0_sd_wr_wreg[10]), + .LO(plm_v4f_mgt_for_v1_4_cal_inst0_gt_do_r_4_i_m2_0_a2_0_a2_2_10_) + ); + defparam plm_v4f_mgt_for_v1_4_cal_inst0_gt_do_r_4_i_m2_0_a2_0_a2_9_.INIT = 4'h8; + LUT2_L plm_v4f_mgt_for_v1_4_cal_inst0_gt_do_r_4_i_m2_0_a2_0_a2_9_ ( + .I0(plm_v4f_mgt_for_v1_4_cal_inst0_cb_state[2]), + .I1(plm_v4f_mgt_for_v1_4_cal_inst0_sd_wr_wreg[9]), + .LO(plm_v4f_mgt_for_v1_4_cal_inst0_gt_do_r_4_i_m2_0_a2_0_a2_2_9_) + ); + defparam plm_v4f_mgt_for_v1_4_cal_inst0_gt_do_r_4_i_m2_0_a2_0_a2_8_.INIT = 4'h8; + LUT2_L plm_v4f_mgt_for_v1_4_cal_inst0_gt_do_r_4_i_m2_0_a2_0_a2_8_ ( + .I0(plm_v4f_mgt_for_v1_4_cal_inst0_cb_state[2]), + .I1(plm_v4f_mgt_for_v1_4_cal_inst0_sd_wr_wreg[8]), + .LO(plm_v4f_mgt_for_v1_4_cal_inst0_gt_do_r_4_i_m2_0_a2_0_a2_2_8_) + ); + defparam plm_v4f_mgt_for_v1_4_cal_inst0_gt_do_r_4_i_m2_0_a2_0_a2_7_.INIT = 4'h8; + LUT2_L plm_v4f_mgt_for_v1_4_cal_inst0_gt_do_r_4_i_m2_0_a2_0_a2_7_ ( + .I0(plm_v4f_mgt_for_v1_4_cal_inst0_cb_state[2]), + .I1(plm_v4f_mgt_for_v1_4_cal_inst0_sd_wr_wreg[7]), + .LO(plm_v4f_mgt_for_v1_4_cal_inst0_gt_do_r_4_i_m2_0_a2_0_a2_2_7_) + ); + defparam plm_v4f_mgt_for_v1_4_cal_inst0_gt_do_r_4_i_m2_0_a2_0_a2_6_.INIT = 4'h8; + LUT2_L plm_v4f_mgt_for_v1_4_cal_inst0_gt_do_r_4_i_m2_0_a2_0_a2_6_ ( + .I0(plm_v4f_mgt_for_v1_4_cal_inst0_cb_state[2]), + .I1(plm_v4f_mgt_for_v1_4_cal_inst0_sd_wr_wreg[6]), + .LO(plm_v4f_mgt_for_v1_4_cal_inst0_gt_do_r_4_i_m2_0_a2_0_a2_2_6_) + ); + defparam plm_v4f_mgt_for_v1_4_cal_inst0_gt_do_r_4_i_m2_0_a2_0_a2_5_.INIT = 4'h8; + LUT2_L plm_v4f_mgt_for_v1_4_cal_inst0_gt_do_r_4_i_m2_0_a2_0_a2_5_ ( + .I0(plm_v4f_mgt_for_v1_4_cal_inst0_cb_state[2]), + .I1(plm_v4f_mgt_for_v1_4_cal_inst0_sd_wr_wreg[5]), + .LO(plm_v4f_mgt_for_v1_4_cal_inst0_gt_do_r_4_i_m2_0_a2_0_a2_2_5_) + ); + defparam plm_v4f_mgt_for_v1_4_cal_inst0_gt_do_r_4_i_m2_0_a2_0_a2_4_.INIT = 4'h8; + LUT2_L plm_v4f_mgt_for_v1_4_cal_inst0_gt_do_r_4_i_m2_0_a2_0_a2_4_ ( + .I0(plm_v4f_mgt_for_v1_4_cal_inst0_cb_state[2]), + .I1(plm_v4f_mgt_for_v1_4_cal_inst0_sd_wr_wreg[4]), + .LO(plm_v4f_mgt_for_v1_4_cal_inst0_gt_do_r_4_i_m2_0_a2_0_a2_2_4_) + ); + defparam plm_v4f_mgt_for_v1_4_cal_inst0_gt_do_r_4_i_m2_0_a2_0_a2_3_.INIT = 4'h8; + LUT2_L plm_v4f_mgt_for_v1_4_cal_inst0_gt_do_r_4_i_m2_0_a2_0_a2_3_ ( + .I0(plm_v4f_mgt_for_v1_4_cal_inst0_cb_state[2]), + .I1(plm_v4f_mgt_for_v1_4_cal_inst0_sd_wr_wreg[3]), + .LO(plm_v4f_mgt_for_v1_4_cal_inst0_gt_do_r_4_i_m2_0_a2_0_a2_2_3_) + ); + defparam plm_v4f_mgt_for_v1_4_cal_inst0_gt_do_r_4_i_m2_0_a2_0_a2_2_.INIT = 4'h8; + LUT2_L plm_v4f_mgt_for_v1_4_cal_inst0_gt_do_r_4_i_m2_0_a2_0_a2_2_ ( + .I0(plm_v4f_mgt_for_v1_4_cal_inst0_cb_state[2]), + .I1(plm_v4f_mgt_for_v1_4_cal_inst0_sd_wr_wreg[2]), + .LO(plm_v4f_mgt_for_v1_4_cal_inst0_gt_do_r_4_i_m2_0_a2_0_a2_2_2_) + ); + defparam plm_v4f_mgt_for_v1_4_cal_inst0_gt_do_r_4_i_m2_0_a2_0_a2_1_.INIT = 4'h8; + LUT2_L plm_v4f_mgt_for_v1_4_cal_inst0_gt_do_r_4_i_m2_0_a2_0_a2_1_ ( + .I0(plm_v4f_mgt_for_v1_4_cal_inst0_cb_state[2]), + .I1(plm_v4f_mgt_for_v1_4_cal_inst0_sd_wr_wreg[1]), + .LO(plm_v4f_mgt_for_v1_4_cal_inst0_gt_do_r_4_i_m2_0_a2_0_a2_1__811) + ); + defparam plm_v4f_mgt_for_v1_4_cal_inst0_gt_do_r_4_i_m2_0_a2_0_a2_0_.INIT = 4'h8; + LUT2_L plm_v4f_mgt_for_v1_4_cal_inst0_gt_do_r_4_i_m2_0_a2_0_a2_0_ ( + .I0(plm_v4f_mgt_for_v1_4_cal_inst0_cb_state[2]), + .I1(plm_v4f_mgt_for_v1_4_cal_inst0_sd_wr_wreg[0]), + .LO(plm_v4f_mgt_for_v1_4_cal_inst0_gt_do_r_4_i_m2_0_a2_0_a2_2_0_) + ); + defparam plm_v4f_mgt_for_v1_4_cal_inst0_N_1816_i.INIT = 4'h1; + LUT1_L plm_v4f_mgt_for_v1_4_cal_inst0_N_1816_i ( + .I0(plm_v4f_mgt_for_v1_4_cal_inst0_sd_req_3_0_a2_0_a2_805), + .LO(plm_v4f_mgt_for_v1_4_cal_inst0_N_1816_i_778) + ); + defparam plm_v4f_mgt_for_v1_4_cal_inst0_N_1828_i.INIT = 8'hFE; + LUT3_L plm_v4f_mgt_for_v1_4_cal_inst0_N_1828_i ( + .I0(plm_v4f_mgt_for_v1_4_cal_inst0_sd_state_4__794), + .I1(plm_v4f_mgt_for_v1_4_cal_inst0_sd_state_8__789), + .I2(plm_v4f_mgt_for_v1_4_cal_inst0_sd_state_11__784), + .LO(plm_v4f_mgt_for_v1_4_cal_inst0_N_1828_i_779) + ); + defparam plm_v4f_mgt_for_v1_4_cal_inst0_N_1827_i.INIT = 8'hFD; + LUT3_L plm_v4f_mgt_for_v1_4_cal_inst0_N_1827_i ( + .I0(plm_v4f_mgt_for_v1_4_cal_inst0_N_1661_i), + .I1(plm_v4f_mgt_for_v1_4_cal_inst0_sd_state_3__795), + .I2(plm_v4f_mgt_for_v1_4_cal_inst0_sd_state_13__782), + .LO(plm_v4f_mgt_for_v1_4_cal_inst0_N_1827_i_780) + ); + defparam plm_v4f_mgt_for_v1_4_cal_inst0_GT_DEN_3_i_0.INIT = 8'h40; + LUT3_L plm_v4f_mgt_for_v1_4_cal_inst0_GT_DEN_3_i_0 ( + .I0(plm_v4f_mgt_for_v1_4_cal_inst0_sd_req_3_0_a2_0_a2_805), + .I1(plm_v4f_mgt_for_v1_4_cal_inst0_cb_state[2]), + .I2(plm_v4f_mgt_for_v1_4_cal_inst0_drp_state_0__804), + .LO(plm_v4f_mgt_for_v1_4_cal_inst0_N_1015_i) + ); + defparam plm_v4f_mgt_for_v1_4_cal_inst0_GT_DADDR_5_i_0_0_5_.INIT = 4'h1; + LUT2_L plm_v4f_mgt_for_v1_4_cal_inst0_GT_DADDR_5_i_0_0_5_ ( + .I0(plm_v4f_mgt_for_v1_4_cal_inst0_N_1662_i), + .I1(cfg_cfg_6102[509]), + .LO(plm_v4f_mgt_for_v1_4_cal_inst0_N_260_i) + ); + defparam plm_v4f_mgt_for_v1_4_cal_inst0_N_1788_i.INIT = 4'hB; + LUT2_L plm_v4f_mgt_for_v1_4_cal_inst0_N_1788_i ( + .I0(plm_v4f_mgt_for_v1_4_cal_inst0_N_1662_i), + .I1(cfg_cfg_6102[509]), + .LO(plm_v4f_mgt_for_v1_4_cal_inst0_N_1788_i_813) + ); + defparam plm_v4f_mgt_for_v1_4_cal_inst0_GT_DADDR_5_i_i_a2_0_a2_1_.INIT = 4'h8; + LUT2_L plm_v4f_mgt_for_v1_4_cal_inst0_GT_DADDR_5_i_i_a2_0_a2_1_ ( + .I0(plm_v4f_mgt_for_v1_4_cal_inst0_N_1662_i), + .I1(cfg_cfg_6102[509]), + .LO(plm_v4f_mgt_for_v1_4_cal_inst0_GT_DADDR_5_i_i_a2_0_a2[1]) + ); + defparam plm_v4f_mgt_for_v1_4_cal_inst0_N_1662_i_i.INIT = 4'h1; + LUT1_L plm_v4f_mgt_for_v1_4_cal_inst0_N_1662_i_i ( + .I0(plm_v4f_mgt_for_v1_4_cal_inst0_N_1662_i), + .LO(plm_v4f_mgt_for_v1_4_cal_inst0_N_1662_i_i_814) + ); + defparam plm_v4f_mgt_for_v1_4_cal_inst0_N_2448_i.INIT = 8'hDC; + LUT3_L plm_v4f_mgt_for_v1_4_cal_inst0_N_2448_i ( + .I0(plm_v4f_mgt_for_v1_4_cal_inst0_sd_drp_done_796), + .I1(plm_v4f_mgt_for_v1_4_cal_inst0_sd_state_12__783), + .I2(plm_v4f_mgt_for_v1_4_cal_inst0_sd_state_13__782), + .LO(plm_v4f_mgt_for_v1_4_cal_inst0_N_2448_i_781) + ); + defparam plm_v4f_mgt_for_v1_4_cal_inst0_sd_next_state_0_sqmuxa_3_0_a2_0_a2_0_a2.INIT = 4'h8; + LUT2_L plm_v4f_mgt_for_v1_4_cal_inst0_sd_next_state_0_sqmuxa_3_0_a2_0_a2_0_a2 ( + .I0(plm_v4f_mgt_for_v1_4_cal_inst0_sd_drp_done_796), + .I1(plm_v4f_mgt_for_v1_4_cal_inst0_sd_state_11__784), + .LO(plm_v4f_mgt_for_v1_4_cal_inst0_sd_next_state_0_sqmuxa_3) + ); + defparam plm_v4f_mgt_for_v1_4_cal_inst0_N_1686_i.INIT = 8'h5C; + LUT3_L plm_v4f_mgt_for_v1_4_cal_inst0_N_1686_i ( + .I0(plm_v4f_mgt_for_v1_4_cal_inst0_sd_drp_done_796), + .I1(plm_v4f_mgt_for_v1_4_cal_inst0_sd_state_9__787), + .I2(plm_v4f_mgt_for_v1_4_cal_inst0_sd_state_10__786), + .LO(plm_v4f_mgt_for_v1_4_cal_inst0_N_1686_i_785) + ); + defparam plm_v4f_mgt_for_v1_4_cal_inst0_sd_next_state_0_sqmuxa_2_0_a2_0_a2_0_a2.INIT = 4'h8; + LUT2_L plm_v4f_mgt_for_v1_4_cal_inst0_sd_next_state_0_sqmuxa_2_0_a2_0_a2_0_a2 ( + .I0(plm_v4f_mgt_for_v1_4_cal_inst0_sd_drp_done_796), + .I1(plm_v4f_mgt_for_v1_4_cal_inst0_sd_state_8__789), + .LO(plm_v4f_mgt_for_v1_4_cal_inst0_sd_next_state_0_sqmuxa_2) + ); + defparam plm_v4f_mgt_for_v1_4_cal_inst0_N_2449_i.INIT = 8'hDC; + LUT3_L plm_v4f_mgt_for_v1_4_cal_inst0_N_2449_i ( + .I0(plm_v4f_mgt_for_v1_4_cal_inst0_sd_drp_done_796), + .I1(plm_v4f_mgt_for_v1_4_cal_inst0_sd_state_7__790), + .I2(plm_v4f_mgt_for_v1_4_cal_inst0_sd_state_8__789), + .LO(plm_v4f_mgt_for_v1_4_cal_inst0_N_2449_i_788) + ); + defparam plm_v4f_mgt_for_v1_4_cal_inst0_sd_next_state_0_i_a2_0_a2_0_a2_7_.INIT = 4'h8; + LUT2_L plm_v4f_mgt_for_v1_4_cal_inst0_sd_next_state_0_i_a2_0_a2_0_a2_7_ ( + .I0(plm_v4f_mgt_for_v1_4_cal_inst0_sd_drp_done_796), + .I1(plm_v4f_mgt_for_v1_4_cal_inst0_sd_state_6__792), + .LO(plm_v4f_mgt_for_v1_4_cal_inst0_sd_next_state_0_i_a2_0_a2_0_a2[7]) + ); + defparam plm_v4f_mgt_for_v1_4_cal_inst0_N_1688_i.INIT = 8'h5C; + LUT3_L plm_v4f_mgt_for_v1_4_cal_inst0_N_1688_i ( + .I0(plm_v4f_mgt_for_v1_4_cal_inst0_sd_drp_done_796), + .I1(plm_v4f_mgt_for_v1_4_cal_inst0_sd_state_5__793), + .I2(plm_v4f_mgt_for_v1_4_cal_inst0_sd_state_6__792), + .LO(plm_v4f_mgt_for_v1_4_cal_inst0_N_1688_i_791) + ); + defparam plm_v4f_mgt_for_v1_4_cal_inst0_sd_next_state_0_sqmuxa_1_0_a2_0_a2_0_a2.INIT = 4'h8; + LUT2_L plm_v4f_mgt_for_v1_4_cal_inst0_sd_next_state_0_sqmuxa_1_0_a2_0_a2_0_a2 ( + .I0(plm_v4f_mgt_for_v1_4_cal_inst0_sd_drp_done_796), + .I1(plm_v4f_mgt_for_v1_4_cal_inst0_sd_state_4__794), + .LO(plm_v4f_mgt_for_v1_4_cal_inst0_sd_next_state_0_sqmuxa_1) + ); + defparam plm_v4f_mgt_for_v1_4_cal_inst0_sd_next_state_0_m4_i_m2_i_m2_i_m2_3_.INIT = 4'h4; + LUT2_L plm_v4f_mgt_for_v1_4_cal_inst0_sd_next_state_0_m4_i_m2_i_m2_i_m2_3_ ( + .I0(plm_v4f_mgt_for_v1_4_cal_inst0_sd_drp_done_796), + .I1(plm_v4f_mgt_for_v1_4_cal_inst0_sd_state_3__795), + .LO(plm_v4f_mgt_for_v1_4_cal_inst0_N_1689_i) + ); + defparam plm_v4f_mgt_for_v1_4_cal_inst0_drp_next_state_0_sqmuxa_0_a2.INIT = 4'h8; + LUT2_L plm_v4f_mgt_for_v1_4_cal_inst0_drp_next_state_0_sqmuxa_0_a2 ( + .I0(plm_v4f_mgt_for_v1_4_cal_inst0_drp_state_3__798), + .I1(plm_v4f_mgt_for_v1_4_cal_inst0_gt_drdy_r_806), + .LO(plm_v4f_mgt_for_v1_4_cal_inst0_drp_next_state_0_sqmuxa) + ); + defparam plm_v4f_mgt_for_v1_4_cal_inst0_N_2393_i.INIT = 16'hFFAE; + LUT4_L plm_v4f_mgt_for_v1_4_cal_inst0_N_2393_i ( + .I0(plm_v4f_mgt_for_v1_4_cal_inst0_drp_state_1__799), + .I1(plm_v4f_mgt_for_v1_4_cal_inst0_drp_state_3__798), + .I2(plm_v4f_mgt_for_v1_4_cal_inst0_gt_drdy_r_806), + .I3(plm_v4f_mgt_gt0_dwe), + .LO(plm_v4f_mgt_for_v1_4_cal_inst0_N_2393_i_797) + ); + defparam plm_v4f_mgt_for_v1_4_cal_inst0_drp_next_state_0_sqmuxa_1_0_a2_0_a2.INIT = 8'h80; + LUT3_L plm_v4f_mgt_for_v1_4_cal_inst0_drp_next_state_0_sqmuxa_1_0_a2_0_a2 ( + .I0(plm_v4f_mgt_for_v1_4_cal_inst0_cb_state[2]), + .I1(plm_v4f_mgt_for_v1_4_cal_inst0_drp_state_0__804), + .I2(plm_v4f_mgt_for_v1_4_cal_inst0_sd_write_800), + .LO(plm_v4f_mgt_for_v1_4_cal_inst0_drp_next_state_0_sqmuxa_1) + ); + defparam plm_v4f_mgt_for_v1_4_cal_inst0_drp_next_state_1_sqmuxa_1_i_0.INIT = 8'h80; + LUT3_L plm_v4f_mgt_for_v1_4_cal_inst0_drp_next_state_1_sqmuxa_1_i_0 ( + .I0(plm_v4f_mgt_for_v1_4_cal_inst0_cb_state[2]), + .I1(plm_v4f_mgt_for_v1_4_cal_inst0_drp_state_0__804), + .I2(plm_v4f_mgt_for_v1_4_cal_inst0_sd_read_801), + .LO(plm_v4f_mgt_for_v1_4_cal_inst0_N_1013_i) + ); + defparam plm_v4f_mgt_for_v1_4_cal_inst0_N_2439_i.INIT = 16'hFFB0; + LUT4_L plm_v4f_mgt_for_v1_4_cal_inst0_N_2439_i ( + .I0(plm_v4f_mgt_for_v1_4_cal_inst0_sd_req_3_0_a2_0_a2_805), + .I1(plm_v4f_mgt_for_v1_4_cal_inst0_cb_state[2]), + .I2(plm_v4f_mgt_for_v1_4_cal_inst0_drp_state_0__804), + .I3(plm_v4f_mgt_for_v1_4_cal_inst0_drp_state_4__803), + .LO(plm_v4f_mgt_for_v1_4_cal_inst0_N_2439_i_802) + ); + FD plm_v4f_mgt_for_v1_4_cal_inst0_gt_drdy_r ( + .C(plm_v4f_mgt_cal_clk), + .D(plm_v4f_mgt_gt0_drdy), + .Q(plm_v4f_mgt_for_v1_4_cal_inst0_gt_drdy_r_806) + ); + FDE plm_v4f_mgt_for_v1_4_cal_inst0_sd_wr_wreg_9_ ( + .CE(plm_v4f_mgt_for_v1_4_cal_inst0_N_1642_i), + .C(plm_v4f_mgt_cal_clk), + .D(plm_v4f_mgt_gt0_di[9]), + .Q(plm_v4f_mgt_for_v1_4_cal_inst0_sd_wr_wreg[9]) + ); + FDE plm_v4f_mgt_for_v1_4_cal_inst0_sd_wr_wreg_8_ ( + .CE(plm_v4f_mgt_for_v1_4_cal_inst0_N_1642_i), + .C(plm_v4f_mgt_cal_clk), + .D(plm_v4f_mgt_gt0_di[8]), + .Q(plm_v4f_mgt_for_v1_4_cal_inst0_sd_wr_wreg[8]) + ); + FDE plm_v4f_mgt_for_v1_4_cal_inst0_sd_wr_wreg_7_ ( + .CE(plm_v4f_mgt_for_v1_4_cal_inst0_N_1642_i), + .C(plm_v4f_mgt_cal_clk), + .D(plm_v4f_mgt_gt0_di[7]), + .Q(plm_v4f_mgt_for_v1_4_cal_inst0_sd_wr_wreg[7]) + ); + FDE plm_v4f_mgt_for_v1_4_cal_inst0_sd_wr_wreg_6_ ( + .CE(plm_v4f_mgt_for_v1_4_cal_inst0_N_1642_i), + .C(plm_v4f_mgt_cal_clk), + .D(plm_v4f_mgt_gt0_di[6]), + .Q(plm_v4f_mgt_for_v1_4_cal_inst0_sd_wr_wreg[6]) + ); + FDE plm_v4f_mgt_for_v1_4_cal_inst0_sd_wr_wreg_5_ ( + .CE(plm_v4f_mgt_for_v1_4_cal_inst0_N_1642_i), + .C(plm_v4f_mgt_cal_clk), + .D(plm_v4f_mgt_gt0_di[5]), + .Q(plm_v4f_mgt_for_v1_4_cal_inst0_sd_wr_wreg[5]) + ); + FDE plm_v4f_mgt_for_v1_4_cal_inst0_sd_wr_wreg_4_ ( + .CE(plm_v4f_mgt_for_v1_4_cal_inst0_N_1642_i), + .C(plm_v4f_mgt_cal_clk), + .D(plm_v4f_mgt_gt0_di[4]), + .Q(plm_v4f_mgt_for_v1_4_cal_inst0_sd_wr_wreg[4]) + ); + FDE plm_v4f_mgt_for_v1_4_cal_inst0_sd_wr_wreg_3_ ( + .CE(plm_v4f_mgt_for_v1_4_cal_inst0_N_1642_i), + .C(plm_v4f_mgt_cal_clk), + .D(plm_v4f_mgt_gt0_di[3]), + .Q(plm_v4f_mgt_for_v1_4_cal_inst0_sd_wr_wreg[3]) + ); + FDE plm_v4f_mgt_for_v1_4_cal_inst0_sd_wr_wreg_2_ ( + .CE(plm_v4f_mgt_for_v1_4_cal_inst0_N_1642_i), + .C(plm_v4f_mgt_cal_clk), + .D(plm_v4f_mgt_gt0_di[2]), + .Q(plm_v4f_mgt_for_v1_4_cal_inst0_sd_wr_wreg[2]) + ); + FD plm_v4f_mgt_for_v1_4_cal_inst0_sd_wr_wreg_1_ ( + .C(plm_v4f_mgt_cal_clk), + .D(plm_v4f_mgt_for_v1_4_cal_inst0_N_2438_i_807), + .Q(plm_v4f_mgt_for_v1_4_cal_inst0_sd_wr_wreg[1]) + ); + FDE plm_v4f_mgt_for_v1_4_cal_inst0_sd_wr_wreg_0_ ( + .CE(plm_v4f_mgt_for_v1_4_cal_inst0_N_1642_i), + .C(plm_v4f_mgt_cal_clk), + .D(plm_v4f_mgt_gt0_di[0]), + .Q(plm_v4f_mgt_for_v1_4_cal_inst0_sd_wr_wreg[0]) + ); + FDP plm_v4f_mgt_for_v1_4_cal_inst0_reset_r_1_ ( + .PRE(plm_v4f_mgt_N_438_i), + .C(plm_v4f_mgt_cal_clk), + .D(plm_v4f_mgt_for_v1_4_cal_inst0_GND_808), + .Q(plm_v4f_mgt_for_v1_4_cal_inst3_reset_r[1]) + ); + FDE plm_v4f_mgt_for_v1_4_cal_inst0_sd_wr_wreg_15_ ( + .CE(plm_v4f_mgt_for_v1_4_cal_inst0_N_1642_i), + .C(plm_v4f_mgt_cal_clk), + .D(plm_v4f_mgt_gt0_di[15]), + .Q(plm_v4f_mgt_for_v1_4_cal_inst0_sd_wr_wreg[15]) + ); + FDE plm_v4f_mgt_for_v1_4_cal_inst0_sd_wr_wreg_14_ ( + .CE(plm_v4f_mgt_for_v1_4_cal_inst0_N_1642_i), + .C(plm_v4f_mgt_cal_clk), + .D(plm_v4f_mgt_gt0_di[14]), + .Q(plm_v4f_mgt_for_v1_4_cal_inst0_sd_wr_wreg[14]) + ); + FDE plm_v4f_mgt_for_v1_4_cal_inst0_sd_wr_wreg_13_ ( + .CE(plm_v4f_mgt_for_v1_4_cal_inst0_N_1642_i), + .C(plm_v4f_mgt_cal_clk), + .D(plm_v4f_mgt_gt0_di[13]), + .Q(plm_v4f_mgt_for_v1_4_cal_inst0_sd_wr_wreg[13]) + ); + FD plm_v4f_mgt_for_v1_4_cal_inst0_sd_wr_wreg_12_ ( + .C(plm_v4f_mgt_cal_clk), + .D(plm_v4f_mgt_for_v1_4_cal_inst0_N_2450_i_809), + .Q(plm_v4f_mgt_for_v1_4_cal_inst0_sd_wr_wreg[12]) + ); + FDE plm_v4f_mgt_for_v1_4_cal_inst0_sd_wr_wreg_11_ ( + .CE(plm_v4f_mgt_for_v1_4_cal_inst0_N_1642_i), + .C(plm_v4f_mgt_cal_clk), + .D(plm_v4f_mgt_gt0_di[11]), + .Q(plm_v4f_mgt_for_v1_4_cal_inst0_sd_wr_wreg[11]) + ); + FDE plm_v4f_mgt_for_v1_4_cal_inst0_sd_wr_wreg_10_ ( + .CE(plm_v4f_mgt_for_v1_4_cal_inst0_N_1642_i), + .C(plm_v4f_mgt_cal_clk), + .D(plm_v4f_mgt_gt0_di[10]), + .Q(plm_v4f_mgt_for_v1_4_cal_inst0_sd_wr_wreg[10]) + ); + FDE plm_v4f_mgt_for_v1_4_cal_inst0_gt_do_r_15_ ( + .CE(plm_v4f_mgt_for_v1_4_cal_inst0_cb_state[2]), + .C(plm_v4f_mgt_cal_clk), + .D(plm_v4f_mgt_for_v1_4_cal_inst0_gt_do_r_4_i_m2_0_a2_0_a2_2_15_), + .Q(plm_v4f_mgt_gt0_do[15]) + ); + FDE plm_v4f_mgt_for_v1_4_cal_inst0_gt_do_r_14_ ( + .CE(plm_v4f_mgt_for_v1_4_cal_inst0_cb_state[2]), + .C(plm_v4f_mgt_cal_clk), + .D(plm_v4f_mgt_for_v1_4_cal_inst0_gt_do_r_4_i_m2_0_a2_0_a2_2_14_), + .Q(plm_v4f_mgt_gt0_do[14]) + ); + FDE plm_v4f_mgt_for_v1_4_cal_inst0_gt_do_r_13_ ( + .CE(plm_v4f_mgt_for_v1_4_cal_inst0_cb_state[2]), + .C(plm_v4f_mgt_cal_clk), + .D(plm_v4f_mgt_for_v1_4_cal_inst0_gt_do_r_4_i_m2_0_a2_0_a2_2_13_), + .Q(plm_v4f_mgt_gt0_do[13]) + ); + FDE plm_v4f_mgt_for_v1_4_cal_inst0_gt_do_r_12_ ( + .CE(plm_v4f_mgt_for_v1_4_cal_inst0_cb_state[2]), + .C(plm_v4f_mgt_cal_clk), + .D(plm_v4f_mgt_for_v1_4_cal_inst0_gt_do_r_4_i_m2_0_a2_0_a2_12__810), + .Q(plm_v4f_mgt_gt0_do[12]) + ); + FDE plm_v4f_mgt_for_v1_4_cal_inst0_gt_do_r_11_ ( + .CE(plm_v4f_mgt_for_v1_4_cal_inst0_cb_state[2]), + .C(plm_v4f_mgt_cal_clk), + .D(plm_v4f_mgt_for_v1_4_cal_inst0_gt_do_r_4_i_m2_0_a2_0_a2_2_11_), + .Q(plm_v4f_mgt_gt0_do[11]) + ); + FDE plm_v4f_mgt_for_v1_4_cal_inst0_gt_do_r_10_ ( + .CE(plm_v4f_mgt_for_v1_4_cal_inst0_cb_state[2]), + .C(plm_v4f_mgt_cal_clk), + .D(plm_v4f_mgt_for_v1_4_cal_inst0_gt_do_r_4_i_m2_0_a2_0_a2_2_10_), + .Q(plm_v4f_mgt_gt0_do[10]) + ); + FDE plm_v4f_mgt_for_v1_4_cal_inst0_gt_do_r_9_ ( + .CE(plm_v4f_mgt_for_v1_4_cal_inst0_cb_state[2]), + .C(plm_v4f_mgt_cal_clk), + .D(plm_v4f_mgt_for_v1_4_cal_inst0_gt_do_r_4_i_m2_0_a2_0_a2_2_9_), + .Q(plm_v4f_mgt_gt0_do[9]) + ); + FDE plm_v4f_mgt_for_v1_4_cal_inst0_gt_do_r_8_ ( + .CE(plm_v4f_mgt_for_v1_4_cal_inst0_cb_state[2]), + .C(plm_v4f_mgt_cal_clk), + .D(plm_v4f_mgt_for_v1_4_cal_inst0_gt_do_r_4_i_m2_0_a2_0_a2_2_8_), + .Q(plm_v4f_mgt_gt0_do[8]) + ); + FDE plm_v4f_mgt_for_v1_4_cal_inst0_gt_do_r_7_ ( + .CE(plm_v4f_mgt_for_v1_4_cal_inst0_cb_state[2]), + .C(plm_v4f_mgt_cal_clk), + .D(plm_v4f_mgt_for_v1_4_cal_inst0_gt_do_r_4_i_m2_0_a2_0_a2_2_7_), + .Q(plm_v4f_mgt_gt0_do[7]) + ); + FDE plm_v4f_mgt_for_v1_4_cal_inst0_gt_do_r_6_ ( + .CE(plm_v4f_mgt_for_v1_4_cal_inst0_cb_state[2]), + .C(plm_v4f_mgt_cal_clk), + .D(plm_v4f_mgt_for_v1_4_cal_inst0_gt_do_r_4_i_m2_0_a2_0_a2_2_6_), + .Q(plm_v4f_mgt_gt0_do[6]) + ); + FDE plm_v4f_mgt_for_v1_4_cal_inst0_gt_do_r_5_ ( + .CE(plm_v4f_mgt_for_v1_4_cal_inst0_cb_state[2]), + .C(plm_v4f_mgt_cal_clk), + .D(plm_v4f_mgt_for_v1_4_cal_inst0_gt_do_r_4_i_m2_0_a2_0_a2_2_5_), + .Q(plm_v4f_mgt_gt0_do[5]) + ); + FDE plm_v4f_mgt_for_v1_4_cal_inst0_gt_do_r_4_ ( + .CE(plm_v4f_mgt_for_v1_4_cal_inst0_cb_state[2]), + .C(plm_v4f_mgt_cal_clk), + .D(plm_v4f_mgt_for_v1_4_cal_inst0_gt_do_r_4_i_m2_0_a2_0_a2_2_4_), + .Q(plm_v4f_mgt_gt0_do[4]) + ); + FDE plm_v4f_mgt_for_v1_4_cal_inst0_gt_do_r_3_ ( + .CE(plm_v4f_mgt_for_v1_4_cal_inst0_cb_state[2]), + .C(plm_v4f_mgt_cal_clk), + .D(plm_v4f_mgt_for_v1_4_cal_inst0_gt_do_r_4_i_m2_0_a2_0_a2_2_3_), + .Q(plm_v4f_mgt_gt0_do[3]) + ); + FDE plm_v4f_mgt_for_v1_4_cal_inst0_gt_do_r_2_ ( + .CE(plm_v4f_mgt_for_v1_4_cal_inst0_cb_state[2]), + .C(plm_v4f_mgt_cal_clk), + .D(plm_v4f_mgt_for_v1_4_cal_inst0_gt_do_r_4_i_m2_0_a2_0_a2_2_2_), + .Q(plm_v4f_mgt_gt0_do[2]) + ); + FDE plm_v4f_mgt_for_v1_4_cal_inst0_gt_do_r_1_ ( + .CE(plm_v4f_mgt_for_v1_4_cal_inst0_cb_state[2]), + .C(plm_v4f_mgt_cal_clk), + .D(plm_v4f_mgt_for_v1_4_cal_inst0_gt_do_r_4_i_m2_0_a2_0_a2_1__811), + .Q(plm_v4f_mgt_gt0_do[1]) + ); + FDE plm_v4f_mgt_for_v1_4_cal_inst0_gt_do_r_0_ ( + .CE(plm_v4f_mgt_for_v1_4_cal_inst0_cb_state[2]), + .C(plm_v4f_mgt_cal_clk), + .D(plm_v4f_mgt_for_v1_4_cal_inst0_gt_do_r_4_i_m2_0_a2_0_a2_2_0_), + .Q(plm_v4f_mgt_gt0_do[0]) + ); + FDE plm_v4f_mgt_for_v1_4_cal_inst0_GT_DADDR_1_5_ ( + .CE(plm_v4f_mgt_for_v1_4_cal_inst0_cb_state[2]), + .C(plm_v4f_mgt_cal_clk), + .D(plm_v4f_mgt_for_v1_4_cal_inst0_N_260_i), + .Q(plm_v4f_mgt_gt0_daddr[5]) + ); + FDE plm_v4f_mgt_for_v1_4_cal_inst0_GT_DADDR_1_3_ ( + .CE(plm_v4f_mgt_for_v1_4_cal_inst0_cb_state[2]), + .C(plm_v4f_mgt_cal_clk), + .D(plm_v4f_mgt_for_v1_4_cal_inst0_VCC_812), + .Q(plm_v4f_mgt_gt0_daddr[3]) + ); + FDE plm_v4f_mgt_for_v1_4_cal_inst0_GT_DADDR_1_2_ ( + .CE(plm_v4f_mgt_for_v1_4_cal_inst0_cb_state[2]), + .C(plm_v4f_mgt_cal_clk), + .D(plm_v4f_mgt_for_v1_4_cal_inst0_N_1788_i_813), + .Q(plm_v4f_mgt_gt0_daddr[2]) + ); + FDE plm_v4f_mgt_for_v1_4_cal_inst0_GT_DADDR_1_1_ ( + .CE(plm_v4f_mgt_for_v1_4_cal_inst0_cb_state[2]), + .C(plm_v4f_mgt_cal_clk), + .D(plm_v4f_mgt_for_v1_4_cal_inst0_GT_DADDR_5_i_i_a2_0_a2[1]), + .Q(plm_v4f_mgt_gt0_daddr[1]) + ); + FDE plm_v4f_mgt_for_v1_4_cal_inst0_GT_DADDR_1_0_ ( + .CE(plm_v4f_mgt_for_v1_4_cal_inst0_cb_state[2]), + .C(plm_v4f_mgt_cal_clk), + .D(plm_v4f_mgt_for_v1_4_cal_inst0_N_1662_i_i_814), + .Q(plm_v4f_mgt_gt0_daddr[4]) + ); + INV plm_v4f_mgt_for_v1_4_cal_inst0_cb_state_i_2_ ( + .I(plm_v4f_mgt_for_v1_4_cal_inst0_cb_state[2]), + .O(plm_v4f_mgt_for_v1_4_cal_inst0_cb_state_i[2]) + ); + VCC plm_v4f_mgt_for_v1_4_cal_inst1_VCC ( + .P(plm_v4f_mgt_for_v1_4_cal_inst1_VCC_842) + ); + GND plm_v4f_mgt_for_v1_4_cal_inst1_GND ( + .G(plm_v4f_mgt_for_v1_4_cal_inst1_GND_815) + ); + FDS plm_v4f_mgt_for_v1_4_cal_inst1_drp_state_0_ ( + .C(plm_v4f_mgt_cal_clk), + .D(plm_v4f_mgt_for_v1_4_cal_inst1_N_2442_i_836), + .Q(plm_v4f_mgt_for_v1_4_cal_inst1_drp_state_0__838), + .S(plm_v4f_mgt_for_v1_4_cal_inst0_reset_r[0]) + ); + FDR plm_v4f_mgt_for_v1_4_cal_inst1_drp_state_1_ ( + .C(plm_v4f_mgt_cal_clk), + .D(plm_v4f_mgt_for_v1_4_cal_inst1_N_995_i), + .Q(plm_v4f_mgt_for_v1_4_cal_inst1_drp_state_1__833), + .R(plm_v4f_mgt_for_v1_4_cal_inst0_reset_r[0]) + ); + FDR plm_v4f_mgt_for_v1_4_cal_inst1_drp_state_2_ ( + .C(plm_v4f_mgt_cal_clk), + .D(plm_v4f_mgt_for_v1_4_cal_inst1_drp_next_state_0_sqmuxa_1), + .Q(plm_v4f_mgt_gt1_dwe), + .R(plm_v4f_mgt_for_v1_4_cal_inst0_reset_r[0]) + ); + FDR plm_v4f_mgt_for_v1_4_cal_inst1_drp_state_3_ ( + .C(plm_v4f_mgt_cal_clk), + .D(plm_v4f_mgt_for_v1_4_cal_inst1_N_2394_i_831), + .Q(plm_v4f_mgt_for_v1_4_cal_inst1_drp_state_3__832), + .R(plm_v4f_mgt_for_v1_4_cal_inst0_reset_r[0]) + ); + FDR plm_v4f_mgt_for_v1_4_cal_inst1_drp_state_4_ ( + .C(plm_v4f_mgt_cal_clk), + .D(plm_v4f_mgt_for_v1_4_cal_inst1_drp_next_state_0_sqmuxa), + .Q(plm_v4f_mgt_for_v1_4_cal_inst1_drp_state_4__837), + .R(plm_v4f_mgt_for_v1_4_cal_inst0_reset_r[0]) + ); + FDS plm_v4f_mgt_for_v1_4_cal_inst1_sd_state_0_ ( + .C(plm_v4f_mgt_cal_clk), + .D(plm_v4f_mgt_for_v1_4_cal_inst1_N_2454_i_829), + .Q(plm_v4f_mgt_for_v1_4_cal_inst1_sd_state[0]), + .S(plm_v4f_mgt_for_v1_4_cal_inst0_reset_r[0]) + ); + FDR plm_v4f_mgt_for_v1_4_cal_inst1_sd_state_1_ ( + .C(plm_v4f_mgt_cal_clk), + .D(plm_v4f_mgt_for_v1_4_cal_inst1_N_2456_i_828), + .Q(plm_v4f_mgt_for_v1_4_cal_inst1_sd_state[1]), + .R(plm_v4f_mgt_for_v1_4_cal_inst0_reset_r[0]) + ); + FDR plm_v4f_mgt_for_v1_4_cal_inst1_sd_state_2_ ( + .C(plm_v4f_mgt_cal_clk), + .D(plm_v4f_mgt_for_v1_4_cal_inst1_sd_next_state_0_sqmuxa), + .Q(plm_v4f_mgt_for_v1_4_cal_inst1_sd_state[2]), + .R(plm_v4f_mgt_for_v1_4_cal_inst0_reset_r[0]) + ); + FDR plm_v4f_mgt_for_v1_4_cal_inst1_sd_state_3_ ( + .C(plm_v4f_mgt_cal_clk), + .D(plm_v4f_mgt_for_v1_4_cal_inst1_N_1683_i_827), + .Q(plm_v4f_mgt_for_v1_4_cal_inst1_sd_state[3]), + .R(plm_v4f_mgt_for_v1_4_cal_inst0_reset_r[0]) + ); + FDR plm_v4f_mgt_for_v1_4_cal_inst1_sd_state_5_ ( + .C(plm_v4f_mgt_cal_clk), + .D(plm_v4f_mgt_for_v1_4_cal_inst1_sd_next_state_0_sqmuxa_1), + .Q(plm_v4f_mgt_for_v1_4_cal_inst1_sd_state[5]), + .R(plm_v4f_mgt_for_v1_4_cal_inst0_reset_r[0]) + ); + FDR plm_v4f_mgt_for_v1_4_cal_inst1_sd_state_6_ ( + .C(plm_v4f_mgt_cal_clk), + .D(plm_v4f_mgt_for_v1_4_cal_inst1_N_1682_i_826), + .Q(plm_v4f_mgt_for_v1_4_cal_inst1_sd_state[6]), + .R(plm_v4f_mgt_for_v1_4_cal_inst0_reset_r[0]) + ); + FDR plm_v4f_mgt_for_v1_4_cal_inst1_sd_state_7_ ( + .C(plm_v4f_mgt_cal_clk), + .D(plm_v4f_mgt_for_v1_4_cal_inst1_N_2452_i_825), + .Q(plm_v4f_mgt_for_v1_4_cal_inst1_sd_state[7]), + .R(plm_v4f_mgt_for_v1_4_cal_inst0_reset_r[0]) + ); + FDR plm_v4f_mgt_for_v1_4_cal_inst1_sd_state_8_ ( + .C(plm_v4f_mgt_cal_clk), + .D(plm_v4f_mgt_for_v1_4_cal_inst1_N_2453_i_824), + .Q(plm_v4f_mgt_for_v1_4_cal_inst1_sd_state[8]), + .R(plm_v4f_mgt_for_v1_4_cal_inst0_reset_r[0]) + ); + FDR plm_v4f_mgt_for_v1_4_cal_inst1_sd_state_9_ ( + .C(plm_v4f_mgt_cal_clk), + .D(plm_v4f_mgt_for_v1_4_cal_inst1_sd_next_state_0_sqmuxa_2), + .Q(plm_v4f_mgt_for_v1_4_cal_inst1_sd_state[9]), + .R(plm_v4f_mgt_for_v1_4_cal_inst0_reset_r[0]) + ); + FDR plm_v4f_mgt_for_v1_4_cal_inst1_sd_state_10_ ( + .C(plm_v4f_mgt_cal_clk), + .D(plm_v4f_mgt_for_v1_4_cal_inst1_N_1680_i_823), + .Q(plm_v4f_mgt_for_v1_4_cal_inst1_sd_state[10]), + .R(plm_v4f_mgt_for_v1_4_cal_inst0_reset_r[0]) + ); + FDR plm_v4f_mgt_for_v1_4_cal_inst1_sd_state_12_ ( + .C(plm_v4f_mgt_cal_clk), + .D(plm_v4f_mgt_for_v1_4_cal_inst1_sd_next_state_0_sqmuxa_3), + .Q(plm_v4f_mgt_for_v1_4_cal_inst1_sd_state[12]), + .R(plm_v4f_mgt_for_v1_4_cal_inst0_reset_r[0]) + ); + FDR plm_v4f_mgt_for_v1_4_cal_inst1_sd_state_13_ ( + .C(plm_v4f_mgt_cal_clk), + .D(plm_v4f_mgt_for_v1_4_cal_inst1_N_2451_i_822), + .Q(plm_v4f_mgt_for_v1_4_cal_inst1_sd_state[13]), + .R(plm_v4f_mgt_for_v1_4_cal_inst0_reset_r[0]) + ); + FDR plm_v4f_mgt_for_v1_4_cal_inst1_GT_DEN ( + .C(plm_v4f_mgt_cal_clk), + .D(plm_v4f_mgt_for_v1_4_cal_inst1_N_997_i), + .Q(plm_v4f_mgt_gt1_den), + .R(plm_v4f_mgt_for_v1_4_cal_inst0_reset_r[0]) + ); + FDR plm_v4f_mgt_for_v1_4_cal_inst1_sd_write ( + .C(plm_v4f_mgt_cal_clk), + .D(plm_v4f_mgt_for_v1_4_cal_inst1_N_1778_i_821), + .Q(plm_v4f_mgt_for_v1_4_cal_inst1_sd_write_834), + .R(plm_v4f_mgt_for_v1_4_cal_inst1_N_1780_i_816) + ); + FDR plm_v4f_mgt_for_v1_4_cal_inst1_sd_read ( + .C(plm_v4f_mgt_cal_clk), + .D(plm_v4f_mgt_for_v1_4_cal_inst1_N_1779_i_820), + .Q(plm_v4f_mgt_for_v1_4_cal_inst1_sd_read_835), + .R(plm_v4f_mgt_for_v1_4_cal_inst1_N_1780_i_816) + ); + FDR plm_v4f_mgt_for_v1_4_cal_inst1_sd_req ( + .C(plm_v4f_mgt_cal_clk), + .D(plm_v4f_mgt_for_v1_4_cal_inst1_N_1810_i_819), + .Q(plm_v4f_mgt_for_v1_4_cal_inst1_sd_req_817), + .R(plm_v4f_mgt_for_v1_4_cal_inst1_N_1780_i_816) + ); + FDRS plm_v4f_mgt_for_v1_4_cal_inst1_GT_LOOPBACK_1_ ( + .C(plm_v4f_mgt_cal_clk), + .D(plm_v4f_mgt_for_v1_4_cal_inst1_GND_815), + .Q(plm_v4f_mgt_loopback3[1]), + .R(plm_v4f_mgt_for_v1_4_cal_inst0_reset_r[0]), + .S(plm_v4f_mgt_clk_sel_by_4_i) + ); + FDRE plm_v4f_mgt_for_v1_4_cal_inst1_sd_state_11_ ( + .CE(plm_v4f_mgt_for_v1_4_cal_inst1_sd_drp_done_830), + .C(plm_v4f_mgt_cal_clk), + .D(plm_v4f_mgt_for_v1_4_cal_inst1_sd_state[10]), + .Q(plm_v4f_mgt_for_v1_4_cal_inst1_sd_state[11]), + .R(plm_v4f_mgt_for_v1_4_cal_inst0_reset_r[0]) + ); + FDRE plm_v4f_mgt_for_v1_4_cal_inst1_sd_state_4_ ( + .CE(plm_v4f_mgt_for_v1_4_cal_inst1_sd_drp_done_830), + .C(plm_v4f_mgt_cal_clk), + .D(plm_v4f_mgt_for_v1_4_cal_inst1_sd_state[3]), + .Q(plm_v4f_mgt_for_v1_4_cal_inst1_sd_state[4]), + .R(plm_v4f_mgt_for_v1_4_cal_inst0_reset_r[0]) + ); + FDR plm_v4f_mgt_for_v1_4_cal_inst1_cb_state_2_ ( + .C(plm_v4f_mgt_cal_clk), + .D(plm_v4f_mgt_for_v1_4_cal_inst1_cb_statec_i_i_818), + .Q(plm_v4f_mgt_for_v1_4_cal_inst1_cb_state[2]), + .R(plm_v4f_mgt_for_v1_4_cal_inst0_reset_r[0]) + ); + FDR plm_v4f_mgt_for_v1_4_cal_inst1_cb_state_1_ ( + .C(plm_v4f_mgt_cal_clk), + .D(plm_v4f_mgt_for_v1_4_cal_inst1_cb_statec_i), + .Q(plm_v4f_mgt_for_v1_4_cal_inst1_cb_state[1]), + .R(plm_v4f_mgt_for_v1_4_cal_inst0_reset_r[0]) + ); + FDR plm_v4f_mgt_for_v1_4_cal_inst1_sd_drp_done ( + .C(plm_v4f_mgt_cal_clk), + .D(plm_v4f_mgt_gt1_drdy), + .Q(plm_v4f_mgt_for_v1_4_cal_inst1_sd_drp_done_830), + .R(plm_v4f_mgt_for_v1_4_cal_inst1_cb_state_i[2]) + ); + defparam plm_v4f_mgt_for_v1_4_cal_inst1_sd_req_3_0_a2_0_a2.INIT = 4'h1; + LUT2 plm_v4f_mgt_for_v1_4_cal_inst1_sd_req_3_0_a2_0_a2 ( + .I0(plm_v4f_mgt_for_v1_4_cal_inst1_sd_read_835), + .I1(plm_v4f_mgt_for_v1_4_cal_inst1_sd_write_834), + .O(plm_v4f_mgt_for_v1_4_cal_inst1_sd_req_3_0_a2_0_a2_0) + ); + defparam plm_v4f_mgt_for_v1_4_cal_inst1_sd_wr_wreg_9_0_0_a2_0_0_12_.INIT = 4'h4; + LUT2 plm_v4f_mgt_for_v1_4_cal_inst1_sd_wr_wreg_9_0_0_a2_0_0_12_ ( + .I0(plm_v4f_mgt_for_v1_4_cal_inst1_sd_state[12]), + .I1(plm_v4f_mgt_for_v1_4_cal_inst1_sd_wr_wreg[12]), + .O(plm_v4f_mgt_for_v1_4_cal_inst1_sd_wr_wreg_9_0_0_a2_0[12]) + ); + defparam plm_v4f_mgt_for_v1_4_cal_inst1_N_1780_i.INIT = 4'hE; + LUT2 plm_v4f_mgt_for_v1_4_cal_inst1_N_1780_i ( + .I0(plm_v4f_mgt_for_v1_4_cal_inst1_sd_drp_done_830), + .I1(plm_v4f_mgt_for_v1_4_cal_inst1_sd_state[0]), + .O(plm_v4f_mgt_for_v1_4_cal_inst1_N_1780_i_816) + ); + defparam plm_v4f_mgt_for_v1_4_cal_inst1_cb_state_4_i_a2_2_.INIT = 16'h51F3; + LUT4 plm_v4f_mgt_for_v1_4_cal_inst1_cb_state_4_i_a2_2_ ( + .I0(plm_v4f_mgt_for_v1_4_cal_inst1_cb_state[1]), + .I1(plm_v4f_mgt_for_v1_4_cal_inst1_cb_state[2]), + .I2(plm_v4f_mgt_for_v1_4_cal_inst1_gt_drdy_r_839), + .I3(plm_v4f_mgt_for_v1_4_cal_inst1_sd_req_817), + .O(plm_v4f_mgt_for_v1_4_cal_inst1_cb_statec_i) + ); + defparam plm_v4f_mgt_for_v1_4_cal_inst1_sd_wr_wreg_9_0_0_o2_12_.INIT = 8'h80; + LUT3 plm_v4f_mgt_for_v1_4_cal_inst1_sd_wr_wreg_9_0_0_o2_12_ ( + .I0(plm_v4f_mgt_for_v1_4_cal_inst1_cb_state[2]), + .I1(plm_v4f_mgt_for_v1_4_cal_inst1_sd_read_835), + .I2(plm_v4f_mgt_gt1_drdy), + .O(plm_v4f_mgt_for_v1_4_cal_inst1_N_1643_i) + ); + defparam plm_v4f_mgt_for_v1_4_cal_inst1_GT_DADDR_5_i_0_0_o2_2_.INIT = 16'h0001; + LUT4 plm_v4f_mgt_for_v1_4_cal_inst1_GT_DADDR_5_i_0_0_o2_2_ ( + .I0(plm_v4f_mgt_for_v1_4_cal_inst1_sd_state[4]), + .I1(plm_v4f_mgt_for_v1_4_cal_inst1_sd_state[6]), + .I2(plm_v4f_mgt_for_v1_4_cal_inst1_sd_state[8]), + .I3(plm_v4f_mgt_for_v1_4_cal_inst1_sd_state[10]), + .O(plm_v4f_mgt_for_v1_4_cal_inst1_N_1663_i) + ); + defparam plm_v4f_mgt_for_v1_4_cal_inst1_sd_wr_wreg_9_i_i_m2_1_.INIT = 8'h1B; + LUT3_L plm_v4f_mgt_for_v1_4_cal_inst1_sd_wr_wreg_9_i_i_m2_1_ ( + .I0(plm_v4f_mgt_for_v1_4_cal_inst1_N_1643_i), + .I1(plm_v4f_mgt_for_v1_4_cal_inst1_sd_state[5]), + .I2(plm_v4f_mgt_gt1_di[1]), + .LO(plm_v4f_mgt_for_v1_4_cal_inst1_sd_wr_wreg_9_i_i_m2[1]) + ); + defparam plm_v4f_mgt_for_v1_4_cal_inst1_cb_statec_i_i.INIT = 4'h1; + LUT1_L plm_v4f_mgt_for_v1_4_cal_inst1_cb_statec_i_i ( + .I0(plm_v4f_mgt_for_v1_4_cal_inst1_cb_statec_i), + .LO(plm_v4f_mgt_for_v1_4_cal_inst1_cb_statec_i_i_818) + ); + defparam plm_v4f_mgt_for_v1_4_cal_inst1_N_2455_i.INIT = 16'h3733; + LUT4_L plm_v4f_mgt_for_v1_4_cal_inst1_N_2455_i ( + .I0(plm_v4f_mgt_for_v1_4_cal_inst1_N_1643_i), + .I1(plm_v4f_mgt_for_v1_4_cal_inst1_sd_wr_wreg_9_i_i_m2[1]), + .I2(plm_v4f_mgt_for_v1_4_cal_inst1_sd_state[9]), + .I3(plm_v4f_mgt_for_v1_4_cal_inst1_sd_wr_wreg[1]), + .LO(plm_v4f_mgt_for_v1_4_cal_inst1_N_2455_i_840) + ); + defparam plm_v4f_mgt_for_v1_4_cal_inst1_N_2457_i.INIT = 16'hBA10; + LUT4_L plm_v4f_mgt_for_v1_4_cal_inst1_N_2457_i ( + .I0(plm_v4f_mgt_for_v1_4_cal_inst1_N_1643_i), + .I1(plm_v4f_mgt_for_v1_4_cal_inst1_sd_state[2]), + .I2(plm_v4f_mgt_for_v1_4_cal_inst1_sd_wr_wreg_9_0_0_a2_0[12]), + .I3(plm_v4f_mgt_gt1_di[12]), + .LO(plm_v4f_mgt_for_v1_4_cal_inst1_N_2457_i_841) + ); + defparam plm_v4f_mgt_for_v1_4_cal_inst1_gt_do_r_4_i_m2_0_a2_0_a2_15_.INIT = 4'h8; + LUT2_L plm_v4f_mgt_for_v1_4_cal_inst1_gt_do_r_4_i_m2_0_a2_0_a2_15_ ( + .I0(plm_v4f_mgt_for_v1_4_cal_inst1_cb_state[2]), + .I1(plm_v4f_mgt_for_v1_4_cal_inst1_sd_wr_wreg[15]), + .LO(plm_v4f_mgt_for_v1_4_cal_inst1_gt_do_r_4_i_m2_0_a2_0_a2_1_15_) + ); + defparam plm_v4f_mgt_for_v1_4_cal_inst1_gt_do_r_4_i_m2_0_a2_0_a2_14_.INIT = 4'h8; + LUT2_L plm_v4f_mgt_for_v1_4_cal_inst1_gt_do_r_4_i_m2_0_a2_0_a2_14_ ( + .I0(plm_v4f_mgt_for_v1_4_cal_inst1_cb_state[2]), + .I1(plm_v4f_mgt_for_v1_4_cal_inst1_sd_wr_wreg[14]), + .LO(plm_v4f_mgt_for_v1_4_cal_inst1_gt_do_r_4_i_m2_0_a2_0_a2_1_14_) + ); + defparam plm_v4f_mgt_for_v1_4_cal_inst1_gt_do_r_4_i_m2_0_a2_0_a2_13_.INIT = 4'h8; + LUT2_L plm_v4f_mgt_for_v1_4_cal_inst1_gt_do_r_4_i_m2_0_a2_0_a2_13_ ( + .I0(plm_v4f_mgt_for_v1_4_cal_inst1_cb_state[2]), + .I1(plm_v4f_mgt_for_v1_4_cal_inst1_sd_wr_wreg[13]), + .LO(plm_v4f_mgt_for_v1_4_cal_inst1_gt_do_r_4_i_m2_0_a2_0_a2_1_13_) + ); + defparam plm_v4f_mgt_for_v1_4_cal_inst1_gt_do_r_4_i_m2_0_a2_0_a2_12_.INIT = 4'h8; + LUT2_L plm_v4f_mgt_for_v1_4_cal_inst1_gt_do_r_4_i_m2_0_a2_0_a2_12_ ( + .I0(plm_v4f_mgt_for_v1_4_cal_inst1_cb_state[2]), + .I1(plm_v4f_mgt_for_v1_4_cal_inst1_sd_wr_wreg[12]), + .LO(plm_v4f_mgt_for_v1_4_cal_inst1_gt_do_r_4_i_m2_0_a2_0_a2_0_12_) + ); + defparam plm_v4f_mgt_for_v1_4_cal_inst1_gt_do_r_4_i_m2_0_a2_0_a2_11_.INIT = 4'h8; + LUT2_L plm_v4f_mgt_for_v1_4_cal_inst1_gt_do_r_4_i_m2_0_a2_0_a2_11_ ( + .I0(plm_v4f_mgt_for_v1_4_cal_inst1_cb_state[2]), + .I1(plm_v4f_mgt_for_v1_4_cal_inst1_sd_wr_wreg[11]), + .LO(plm_v4f_mgt_for_v1_4_cal_inst1_gt_do_r_4_i_m2_0_a2_0_a2_1_11_) + ); + defparam plm_v4f_mgt_for_v1_4_cal_inst1_gt_do_r_4_i_m2_0_a2_0_a2_10_.INIT = 4'h8; + LUT2_L plm_v4f_mgt_for_v1_4_cal_inst1_gt_do_r_4_i_m2_0_a2_0_a2_10_ ( + .I0(plm_v4f_mgt_for_v1_4_cal_inst1_cb_state[2]), + .I1(plm_v4f_mgt_for_v1_4_cal_inst1_sd_wr_wreg[10]), + .LO(plm_v4f_mgt_for_v1_4_cal_inst1_gt_do_r_4_i_m2_0_a2_0_a2_1_10_) + ); + defparam plm_v4f_mgt_for_v1_4_cal_inst1_gt_do_r_4_i_m2_0_a2_0_a2_9_.INIT = 4'h8; + LUT2_L plm_v4f_mgt_for_v1_4_cal_inst1_gt_do_r_4_i_m2_0_a2_0_a2_9_ ( + .I0(plm_v4f_mgt_for_v1_4_cal_inst1_cb_state[2]), + .I1(plm_v4f_mgt_for_v1_4_cal_inst1_sd_wr_wreg[9]), + .LO(plm_v4f_mgt_for_v1_4_cal_inst1_gt_do_r_4_i_m2_0_a2_0_a2_1_9_) + ); + defparam plm_v4f_mgt_for_v1_4_cal_inst1_gt_do_r_4_i_m2_0_a2_0_a2_8_.INIT = 4'h8; + LUT2_L plm_v4f_mgt_for_v1_4_cal_inst1_gt_do_r_4_i_m2_0_a2_0_a2_8_ ( + .I0(plm_v4f_mgt_for_v1_4_cal_inst1_cb_state[2]), + .I1(plm_v4f_mgt_for_v1_4_cal_inst1_sd_wr_wreg[8]), + .LO(plm_v4f_mgt_for_v1_4_cal_inst1_gt_do_r_4_i_m2_0_a2_0_a2_1_8_) + ); + defparam plm_v4f_mgt_for_v1_4_cal_inst1_gt_do_r_4_i_m2_0_a2_0_a2_7_.INIT = 4'h8; + LUT2_L plm_v4f_mgt_for_v1_4_cal_inst1_gt_do_r_4_i_m2_0_a2_0_a2_7_ ( + .I0(plm_v4f_mgt_for_v1_4_cal_inst1_cb_state[2]), + .I1(plm_v4f_mgt_for_v1_4_cal_inst1_sd_wr_wreg[7]), + .LO(plm_v4f_mgt_for_v1_4_cal_inst1_gt_do_r_4_i_m2_0_a2_0_a2_1_7_) + ); + defparam plm_v4f_mgt_for_v1_4_cal_inst1_gt_do_r_4_i_m2_0_a2_0_a2_6_.INIT = 4'h8; + LUT2_L plm_v4f_mgt_for_v1_4_cal_inst1_gt_do_r_4_i_m2_0_a2_0_a2_6_ ( + .I0(plm_v4f_mgt_for_v1_4_cal_inst1_cb_state[2]), + .I1(plm_v4f_mgt_for_v1_4_cal_inst1_sd_wr_wreg[6]), + .LO(plm_v4f_mgt_for_v1_4_cal_inst1_gt_do_r_4_i_m2_0_a2_0_a2_1_6_) + ); + defparam plm_v4f_mgt_for_v1_4_cal_inst1_gt_do_r_4_i_m2_0_a2_0_a2_5_.INIT = 4'h8; + LUT2_L plm_v4f_mgt_for_v1_4_cal_inst1_gt_do_r_4_i_m2_0_a2_0_a2_5_ ( + .I0(plm_v4f_mgt_for_v1_4_cal_inst1_cb_state[2]), + .I1(plm_v4f_mgt_for_v1_4_cal_inst1_sd_wr_wreg[5]), + .LO(plm_v4f_mgt_for_v1_4_cal_inst1_gt_do_r_4_i_m2_0_a2_0_a2_1_5_) + ); + defparam plm_v4f_mgt_for_v1_4_cal_inst1_gt_do_r_4_i_m2_0_a2_0_a2_4_.INIT = 4'h8; + LUT2_L plm_v4f_mgt_for_v1_4_cal_inst1_gt_do_r_4_i_m2_0_a2_0_a2_4_ ( + .I0(plm_v4f_mgt_for_v1_4_cal_inst1_cb_state[2]), + .I1(plm_v4f_mgt_for_v1_4_cal_inst1_sd_wr_wreg[4]), + .LO(plm_v4f_mgt_for_v1_4_cal_inst1_gt_do_r_4_i_m2_0_a2_0_a2_1_4_) + ); + defparam plm_v4f_mgt_for_v1_4_cal_inst1_gt_do_r_4_i_m2_0_a2_0_a2_3_.INIT = 4'h8; + LUT2_L plm_v4f_mgt_for_v1_4_cal_inst1_gt_do_r_4_i_m2_0_a2_0_a2_3_ ( + .I0(plm_v4f_mgt_for_v1_4_cal_inst1_cb_state[2]), + .I1(plm_v4f_mgt_for_v1_4_cal_inst1_sd_wr_wreg[3]), + .LO(plm_v4f_mgt_for_v1_4_cal_inst1_gt_do_r_4_i_m2_0_a2_0_a2_1_3_) + ); + defparam plm_v4f_mgt_for_v1_4_cal_inst1_gt_do_r_4_i_m2_0_a2_0_a2_2_.INIT = 4'h8; + LUT2_L plm_v4f_mgt_for_v1_4_cal_inst1_gt_do_r_4_i_m2_0_a2_0_a2_2_ ( + .I0(plm_v4f_mgt_for_v1_4_cal_inst1_cb_state[2]), + .I1(plm_v4f_mgt_for_v1_4_cal_inst1_sd_wr_wreg[2]), + .LO(plm_v4f_mgt_for_v1_4_cal_inst1_gt_do_r_4_i_m2_0_a2_0_a2_1_2_) + ); + defparam plm_v4f_mgt_for_v1_4_cal_inst1_gt_do_r_4_i_m2_0_a2_0_a2_1_.INIT = 4'h8; + LUT2_L plm_v4f_mgt_for_v1_4_cal_inst1_gt_do_r_4_i_m2_0_a2_0_a2_1_ ( + .I0(plm_v4f_mgt_for_v1_4_cal_inst1_cb_state[2]), + .I1(plm_v4f_mgt_for_v1_4_cal_inst1_sd_wr_wreg[1]), + .LO(plm_v4f_mgt_for_v1_4_cal_inst1_gt_do_r_4_i_m2_0_a2_0_a2_0_1_) + ); + defparam plm_v4f_mgt_for_v1_4_cal_inst1_gt_do_r_4_i_m2_0_a2_0_a2_0_.INIT = 4'h8; + LUT2_L plm_v4f_mgt_for_v1_4_cal_inst1_gt_do_r_4_i_m2_0_a2_0_a2_0_ ( + .I0(plm_v4f_mgt_for_v1_4_cal_inst1_cb_state[2]), + .I1(plm_v4f_mgt_for_v1_4_cal_inst1_sd_wr_wreg[0]), + .LO(plm_v4f_mgt_for_v1_4_cal_inst1_gt_do_r_4_i_m2_0_a2_0_a2_1_0_) + ); + defparam plm_v4f_mgt_for_v1_4_cal_inst1_N_1810_i.INIT = 4'h1; + LUT1_L plm_v4f_mgt_for_v1_4_cal_inst1_N_1810_i ( + .I0(plm_v4f_mgt_for_v1_4_cal_inst1_sd_req_3_0_a2_0_a2_0), + .LO(plm_v4f_mgt_for_v1_4_cal_inst1_N_1810_i_819) + ); + defparam plm_v4f_mgt_for_v1_4_cal_inst1_N_1779_i.INIT = 16'hFFFE; + LUT4_L plm_v4f_mgt_for_v1_4_cal_inst1_N_1779_i ( + .I0(plm_v4f_mgt_for_v1_4_cal_inst1_sd_state[1]), + .I1(plm_v4f_mgt_for_v1_4_cal_inst1_sd_state[4]), + .I2(plm_v4f_mgt_for_v1_4_cal_inst1_sd_state[8]), + .I3(plm_v4f_mgt_for_v1_4_cal_inst1_sd_state[11]), + .LO(plm_v4f_mgt_for_v1_4_cal_inst1_N_1779_i_820) + ); + defparam plm_v4f_mgt_for_v1_4_cal_inst1_N_1778_i.INIT = 16'hFFFE; + LUT4_L plm_v4f_mgt_for_v1_4_cal_inst1_N_1778_i ( + .I0(plm_v4f_mgt_for_v1_4_cal_inst1_sd_state[3]), + .I1(plm_v4f_mgt_for_v1_4_cal_inst1_sd_state[6]), + .I2(plm_v4f_mgt_for_v1_4_cal_inst1_sd_state[10]), + .I3(plm_v4f_mgt_for_v1_4_cal_inst1_sd_state[13]), + .LO(plm_v4f_mgt_for_v1_4_cal_inst1_N_1778_i_821) + ); + defparam plm_v4f_mgt_for_v1_4_cal_inst1_GT_DEN_3_i_0.INIT = 8'h40; + LUT3_L plm_v4f_mgt_for_v1_4_cal_inst1_GT_DEN_3_i_0 ( + .I0(plm_v4f_mgt_for_v1_4_cal_inst1_sd_req_3_0_a2_0_a2_0), + .I1(plm_v4f_mgt_for_v1_4_cal_inst1_cb_state[2]), + .I2(plm_v4f_mgt_for_v1_4_cal_inst1_drp_state_0__838), + .LO(plm_v4f_mgt_for_v1_4_cal_inst1_N_997_i) + ); + defparam plm_v4f_mgt_for_v1_4_cal_inst1_GT_DADDR_5_i_i_a2_i_5_.INIT = 4'h4; + LUT2_L plm_v4f_mgt_for_v1_4_cal_inst1_GT_DADDR_5_i_i_a2_i_5_ ( + .I0(plm_v4f_mgt_for_v1_4_cal_inst1_N_1663_i), + .I1(cfg_cfg_6102[509]), + .LO(plm_v4f_mgt_for_v1_4_cal_inst1_N_1540_i) + ); + defparam plm_v4f_mgt_for_v1_4_cal_inst1_N_1768_i.INIT = 4'hE; + LUT2_L plm_v4f_mgt_for_v1_4_cal_inst1_N_1768_i ( + .I0(plm_v4f_mgt_for_v1_4_cal_inst1_N_1663_i), + .I1(cfg_cfg_6102[509]), + .LO(plm_v4f_mgt_for_v1_4_cal_inst1_N_1768_i_843) + ); + defparam plm_v4f_mgt_for_v1_4_cal_inst1_GT_DADDR_5_i_i_a2_0_a2_1_.INIT = 4'h2; + LUT2_L plm_v4f_mgt_for_v1_4_cal_inst1_GT_DADDR_5_i_i_a2_0_a2_1_ ( + .I0(plm_v4f_mgt_for_v1_4_cal_inst1_N_1663_i), + .I1(cfg_cfg_6102[509]), + .LO(plm_v4f_mgt_for_v1_4_cal_inst1_GT_DADDR_5_i_i_a2_0_a2_0[1]) + ); + defparam plm_v4f_mgt_for_v1_4_cal_inst1_N_1663_i_i.INIT = 4'h1; + LUT1_L plm_v4f_mgt_for_v1_4_cal_inst1_N_1663_i_i ( + .I0(plm_v4f_mgt_for_v1_4_cal_inst1_N_1663_i), + .LO(plm_v4f_mgt_for_v1_4_cal_inst1_N_1663_i_i_844) + ); + defparam plm_v4f_mgt_for_v1_4_cal_inst1_N_2451_i.INIT = 8'hDC; + LUT3_L plm_v4f_mgt_for_v1_4_cal_inst1_N_2451_i ( + .I0(plm_v4f_mgt_for_v1_4_cal_inst1_sd_drp_done_830), + .I1(plm_v4f_mgt_for_v1_4_cal_inst1_sd_state[12]), + .I2(plm_v4f_mgt_for_v1_4_cal_inst1_sd_state[13]), + .LO(plm_v4f_mgt_for_v1_4_cal_inst1_N_2451_i_822) + ); + defparam plm_v4f_mgt_for_v1_4_cal_inst1_sd_next_state_0_sqmuxa_3_0_a2_0_a2.INIT = 4'h8; + LUT2_L plm_v4f_mgt_for_v1_4_cal_inst1_sd_next_state_0_sqmuxa_3_0_a2_0_a2 ( + .I0(plm_v4f_mgt_for_v1_4_cal_inst1_sd_drp_done_830), + .I1(plm_v4f_mgt_for_v1_4_cal_inst1_sd_state[11]), + .LO(plm_v4f_mgt_for_v1_4_cal_inst1_sd_next_state_0_sqmuxa_3) + ); + defparam plm_v4f_mgt_for_v1_4_cal_inst1_N_1680_i.INIT = 8'h5C; + LUT3_L plm_v4f_mgt_for_v1_4_cal_inst1_N_1680_i ( + .I0(plm_v4f_mgt_for_v1_4_cal_inst1_sd_drp_done_830), + .I1(plm_v4f_mgt_for_v1_4_cal_inst1_sd_state[9]), + .I2(plm_v4f_mgt_for_v1_4_cal_inst1_sd_state[10]), + .LO(plm_v4f_mgt_for_v1_4_cal_inst1_N_1680_i_823) + ); + defparam plm_v4f_mgt_for_v1_4_cal_inst1_sd_next_state_0_sqmuxa_2_0_a2_0_a2.INIT = 4'h8; + LUT2_L plm_v4f_mgt_for_v1_4_cal_inst1_sd_next_state_0_sqmuxa_2_0_a2_0_a2 ( + .I0(plm_v4f_mgt_for_v1_4_cal_inst1_sd_drp_done_830), + .I1(plm_v4f_mgt_for_v1_4_cal_inst1_sd_state[8]), + .LO(plm_v4f_mgt_for_v1_4_cal_inst1_sd_next_state_0_sqmuxa_2) + ); + defparam plm_v4f_mgt_for_v1_4_cal_inst1_N_2453_i.INIT = 16'hB3A0; + LUT4_L plm_v4f_mgt_for_v1_4_cal_inst1_N_2453_i ( + .I0(cmmp_negotiated_width_0[0]), + .I1(plm_v4f_mgt_for_v1_4_cal_inst1_sd_drp_done_830), + .I2(plm_v4f_mgt_for_v1_4_cal_inst1_sd_state[7]), + .I3(plm_v4f_mgt_for_v1_4_cal_inst1_sd_state[8]), + .LO(plm_v4f_mgt_for_v1_4_cal_inst1_N_2453_i_824) + ); + defparam plm_v4f_mgt_for_v1_4_cal_inst1_N_2452_i.INIT = 16'hD5C0; + LUT4_L plm_v4f_mgt_for_v1_4_cal_inst1_N_2452_i ( + .I0(cmmp_negotiated_width_0[0]), + .I1(plm_v4f_mgt_for_v1_4_cal_inst1_sd_drp_done_830), + .I2(plm_v4f_mgt_for_v1_4_cal_inst1_sd_state[6]), + .I3(plm_v4f_mgt_for_v1_4_cal_inst1_sd_state[7]), + .LO(plm_v4f_mgt_for_v1_4_cal_inst1_N_2452_i_825) + ); + defparam plm_v4f_mgt_for_v1_4_cal_inst1_N_1682_i.INIT = 8'h5C; + LUT3_L plm_v4f_mgt_for_v1_4_cal_inst1_N_1682_i ( + .I0(plm_v4f_mgt_for_v1_4_cal_inst1_sd_drp_done_830), + .I1(plm_v4f_mgt_for_v1_4_cal_inst1_sd_state[5]), + .I2(plm_v4f_mgt_for_v1_4_cal_inst1_sd_state[6]), + .LO(plm_v4f_mgt_for_v1_4_cal_inst1_N_1682_i_826) + ); + defparam plm_v4f_mgt_for_v1_4_cal_inst1_sd_next_state_0_sqmuxa_1_0_a2_0_a2.INIT = 4'h8; + LUT2_L plm_v4f_mgt_for_v1_4_cal_inst1_sd_next_state_0_sqmuxa_1_0_a2_0_a2 ( + .I0(plm_v4f_mgt_for_v1_4_cal_inst1_sd_drp_done_830), + .I1(plm_v4f_mgt_for_v1_4_cal_inst1_sd_state[4]), + .LO(plm_v4f_mgt_for_v1_4_cal_inst1_sd_next_state_0_sqmuxa_1) + ); + defparam plm_v4f_mgt_for_v1_4_cal_inst1_N_1683_i.INIT = 8'h5C; + LUT3_L plm_v4f_mgt_for_v1_4_cal_inst1_N_1683_i ( + .I0(plm_v4f_mgt_for_v1_4_cal_inst1_sd_drp_done_830), + .I1(plm_v4f_mgt_for_v1_4_cal_inst1_sd_state[2]), + .I2(plm_v4f_mgt_for_v1_4_cal_inst1_sd_state[3]), + .LO(plm_v4f_mgt_for_v1_4_cal_inst1_N_1683_i_827) + ); + defparam plm_v4f_mgt_for_v1_4_cal_inst1_sd_next_state_0_sqmuxa_0_a2_0_a2.INIT = 4'h8; + LUT2_L plm_v4f_mgt_for_v1_4_cal_inst1_sd_next_state_0_sqmuxa_0_a2_0_a2 ( + .I0(plm_v4f_mgt_for_v1_4_cal_inst1_sd_drp_done_830), + .I1(plm_v4f_mgt_for_v1_4_cal_inst1_sd_state[1]), + .LO(plm_v4f_mgt_for_v1_4_cal_inst1_sd_next_state_0_sqmuxa) + ); + defparam plm_v4f_mgt_for_v1_4_cal_inst1_N_2456_i.INIT = 16'h3350; + LUT4_L plm_v4f_mgt_for_v1_4_cal_inst1_N_2456_i ( + .I0(cmmp_negotiated_width_0[0]), + .I1(plm_v4f_mgt_for_v1_4_cal_inst1_sd_drp_done_830), + .I2(plm_v4f_mgt_for_v1_4_cal_inst1_sd_state[0]), + .I3(plm_v4f_mgt_for_v1_4_cal_inst1_sd_state[1]), + .LO(plm_v4f_mgt_for_v1_4_cal_inst1_N_2456_i_828) + ); + defparam plm_v4f_mgt_for_v1_4_cal_inst1_N_2454_i.INIT = 16'hCCA0; + LUT4_L plm_v4f_mgt_for_v1_4_cal_inst1_N_2454_i ( + .I0(cmmp_negotiated_width_0[0]), + .I1(plm_v4f_mgt_for_v1_4_cal_inst1_sd_drp_done_830), + .I2(plm_v4f_mgt_for_v1_4_cal_inst1_sd_state[0]), + .I3(plm_v4f_mgt_for_v1_4_cal_inst1_sd_state[13]), + .LO(plm_v4f_mgt_for_v1_4_cal_inst1_N_2454_i_829) + ); + defparam plm_v4f_mgt_for_v1_4_cal_inst1_drp_next_state_0_sqmuxa_0_a2.INIT = 4'h8; + LUT2_L plm_v4f_mgt_for_v1_4_cal_inst1_drp_next_state_0_sqmuxa_0_a2 ( + .I0(plm_v4f_mgt_for_v1_4_cal_inst1_drp_state_3__832), + .I1(plm_v4f_mgt_for_v1_4_cal_inst1_gt_drdy_r_839), + .LO(plm_v4f_mgt_for_v1_4_cal_inst1_drp_next_state_0_sqmuxa) + ); + defparam plm_v4f_mgt_for_v1_4_cal_inst1_N_2394_i.INIT = 16'hFFAE; + LUT4_L plm_v4f_mgt_for_v1_4_cal_inst1_N_2394_i ( + .I0(plm_v4f_mgt_for_v1_4_cal_inst1_drp_state_1__833), + .I1(plm_v4f_mgt_for_v1_4_cal_inst1_drp_state_3__832), + .I2(plm_v4f_mgt_for_v1_4_cal_inst1_gt_drdy_r_839), + .I3(plm_v4f_mgt_gt1_dwe), + .LO(plm_v4f_mgt_for_v1_4_cal_inst1_N_2394_i_831) + ); + defparam plm_v4f_mgt_for_v1_4_cal_inst1_drp_next_state_0_sqmuxa_1_0_a2_0_a2.INIT = 8'h80; + LUT3_L plm_v4f_mgt_for_v1_4_cal_inst1_drp_next_state_0_sqmuxa_1_0_a2_0_a2 ( + .I0(plm_v4f_mgt_for_v1_4_cal_inst1_cb_state[2]), + .I1(plm_v4f_mgt_for_v1_4_cal_inst1_drp_state_0__838), + .I2(plm_v4f_mgt_for_v1_4_cal_inst1_sd_write_834), + .LO(plm_v4f_mgt_for_v1_4_cal_inst1_drp_next_state_0_sqmuxa_1) + ); + defparam plm_v4f_mgt_for_v1_4_cal_inst1_drp_next_state_1_sqmuxa_1_i_0.INIT = 8'h80; + LUT3_L plm_v4f_mgt_for_v1_4_cal_inst1_drp_next_state_1_sqmuxa_1_i_0 ( + .I0(plm_v4f_mgt_for_v1_4_cal_inst1_cb_state[2]), + .I1(plm_v4f_mgt_for_v1_4_cal_inst1_drp_state_0__838), + .I2(plm_v4f_mgt_for_v1_4_cal_inst1_sd_read_835), + .LO(plm_v4f_mgt_for_v1_4_cal_inst1_N_995_i) + ); + defparam plm_v4f_mgt_for_v1_4_cal_inst1_N_2442_i.INIT = 16'hFFB0; + LUT4_L plm_v4f_mgt_for_v1_4_cal_inst1_N_2442_i ( + .I0(plm_v4f_mgt_for_v1_4_cal_inst1_sd_req_3_0_a2_0_a2_0), + .I1(plm_v4f_mgt_for_v1_4_cal_inst1_cb_state[2]), + .I2(plm_v4f_mgt_for_v1_4_cal_inst1_drp_state_0__838), + .I3(plm_v4f_mgt_for_v1_4_cal_inst1_drp_state_4__837), + .LO(plm_v4f_mgt_for_v1_4_cal_inst1_N_2442_i_836) + ); + FD plm_v4f_mgt_for_v1_4_cal_inst1_gt_drdy_r ( + .C(plm_v4f_mgt_cal_clk), + .D(plm_v4f_mgt_gt1_drdy), + .Q(plm_v4f_mgt_for_v1_4_cal_inst1_gt_drdy_r_839) + ); + FDE plm_v4f_mgt_for_v1_4_cal_inst1_sd_wr_wreg_9_ ( + .CE(plm_v4f_mgt_for_v1_4_cal_inst1_N_1643_i), + .C(plm_v4f_mgt_cal_clk), + .D(plm_v4f_mgt_gt1_di[9]), + .Q(plm_v4f_mgt_for_v1_4_cal_inst1_sd_wr_wreg[9]) + ); + FDE plm_v4f_mgt_for_v1_4_cal_inst1_sd_wr_wreg_8_ ( + .CE(plm_v4f_mgt_for_v1_4_cal_inst1_N_1643_i), + .C(plm_v4f_mgt_cal_clk), + .D(plm_v4f_mgt_gt1_di[8]), + .Q(plm_v4f_mgt_for_v1_4_cal_inst1_sd_wr_wreg[8]) + ); + FDE plm_v4f_mgt_for_v1_4_cal_inst1_sd_wr_wreg_7_ ( + .CE(plm_v4f_mgt_for_v1_4_cal_inst1_N_1643_i), + .C(plm_v4f_mgt_cal_clk), + .D(plm_v4f_mgt_gt1_di[7]), + .Q(plm_v4f_mgt_for_v1_4_cal_inst1_sd_wr_wreg[7]) + ); + FDE plm_v4f_mgt_for_v1_4_cal_inst1_sd_wr_wreg_6_ ( + .CE(plm_v4f_mgt_for_v1_4_cal_inst1_N_1643_i), + .C(plm_v4f_mgt_cal_clk), + .D(plm_v4f_mgt_gt1_di[6]), + .Q(plm_v4f_mgt_for_v1_4_cal_inst1_sd_wr_wreg[6]) + ); + FDE plm_v4f_mgt_for_v1_4_cal_inst1_sd_wr_wreg_5_ ( + .CE(plm_v4f_mgt_for_v1_4_cal_inst1_N_1643_i), + .C(plm_v4f_mgt_cal_clk), + .D(plm_v4f_mgt_gt1_di[5]), + .Q(plm_v4f_mgt_for_v1_4_cal_inst1_sd_wr_wreg[5]) + ); + FDE plm_v4f_mgt_for_v1_4_cal_inst1_sd_wr_wreg_4_ ( + .CE(plm_v4f_mgt_for_v1_4_cal_inst1_N_1643_i), + .C(plm_v4f_mgt_cal_clk), + .D(plm_v4f_mgt_gt1_di[4]), + .Q(plm_v4f_mgt_for_v1_4_cal_inst1_sd_wr_wreg[4]) + ); + FDE plm_v4f_mgt_for_v1_4_cal_inst1_sd_wr_wreg_3_ ( + .CE(plm_v4f_mgt_for_v1_4_cal_inst1_N_1643_i), + .C(plm_v4f_mgt_cal_clk), + .D(plm_v4f_mgt_gt1_di[3]), + .Q(plm_v4f_mgt_for_v1_4_cal_inst1_sd_wr_wreg[3]) + ); + FDE plm_v4f_mgt_for_v1_4_cal_inst1_sd_wr_wreg_2_ ( + .CE(plm_v4f_mgt_for_v1_4_cal_inst1_N_1643_i), + .C(plm_v4f_mgt_cal_clk), + .D(plm_v4f_mgt_gt1_di[2]), + .Q(plm_v4f_mgt_for_v1_4_cal_inst1_sd_wr_wreg[2]) + ); + FD plm_v4f_mgt_for_v1_4_cal_inst1_sd_wr_wreg_1_ ( + .C(plm_v4f_mgt_cal_clk), + .D(plm_v4f_mgt_for_v1_4_cal_inst1_N_2455_i_840), + .Q(plm_v4f_mgt_for_v1_4_cal_inst1_sd_wr_wreg[1]) + ); + FDE plm_v4f_mgt_for_v1_4_cal_inst1_sd_wr_wreg_0_ ( + .CE(plm_v4f_mgt_for_v1_4_cal_inst1_N_1643_i), + .C(plm_v4f_mgt_cal_clk), + .D(plm_v4f_mgt_gt1_di[0]), + .Q(plm_v4f_mgt_for_v1_4_cal_inst1_sd_wr_wreg[0]) + ); + FDE plm_v4f_mgt_for_v1_4_cal_inst1_sd_wr_wreg_15_ ( + .CE(plm_v4f_mgt_for_v1_4_cal_inst1_N_1643_i), + .C(plm_v4f_mgt_cal_clk), + .D(plm_v4f_mgt_gt1_di[15]), + .Q(plm_v4f_mgt_for_v1_4_cal_inst1_sd_wr_wreg[15]) + ); + FDE plm_v4f_mgt_for_v1_4_cal_inst1_sd_wr_wreg_14_ ( + .CE(plm_v4f_mgt_for_v1_4_cal_inst1_N_1643_i), + .C(plm_v4f_mgt_cal_clk), + .D(plm_v4f_mgt_gt1_di[14]), + .Q(plm_v4f_mgt_for_v1_4_cal_inst1_sd_wr_wreg[14]) + ); + FDE plm_v4f_mgt_for_v1_4_cal_inst1_sd_wr_wreg_13_ ( + .CE(plm_v4f_mgt_for_v1_4_cal_inst1_N_1643_i), + .C(plm_v4f_mgt_cal_clk), + .D(plm_v4f_mgt_gt1_di[13]), + .Q(plm_v4f_mgt_for_v1_4_cal_inst1_sd_wr_wreg[13]) + ); + FD plm_v4f_mgt_for_v1_4_cal_inst1_sd_wr_wreg_12_ ( + .C(plm_v4f_mgt_cal_clk), + .D(plm_v4f_mgt_for_v1_4_cal_inst1_N_2457_i_841), + .Q(plm_v4f_mgt_for_v1_4_cal_inst1_sd_wr_wreg[12]) + ); + FDE plm_v4f_mgt_for_v1_4_cal_inst1_sd_wr_wreg_11_ ( + .CE(plm_v4f_mgt_for_v1_4_cal_inst1_N_1643_i), + .C(plm_v4f_mgt_cal_clk), + .D(plm_v4f_mgt_gt1_di[11]), + .Q(plm_v4f_mgt_for_v1_4_cal_inst1_sd_wr_wreg[11]) + ); + FDE plm_v4f_mgt_for_v1_4_cal_inst1_sd_wr_wreg_10_ ( + .CE(plm_v4f_mgt_for_v1_4_cal_inst1_N_1643_i), + .C(plm_v4f_mgt_cal_clk), + .D(plm_v4f_mgt_gt1_di[10]), + .Q(plm_v4f_mgt_for_v1_4_cal_inst1_sd_wr_wreg[10]) + ); + FDE plm_v4f_mgt_for_v1_4_cal_inst1_gt_do_r_15_ ( + .CE(plm_v4f_mgt_for_v1_4_cal_inst1_cb_state[2]), + .C(plm_v4f_mgt_cal_clk), + .D(plm_v4f_mgt_for_v1_4_cal_inst1_gt_do_r_4_i_m2_0_a2_0_a2_1_15_), + .Q(plm_v4f_mgt_gt1_do[15]) + ); + FDE plm_v4f_mgt_for_v1_4_cal_inst1_gt_do_r_14_ ( + .CE(plm_v4f_mgt_for_v1_4_cal_inst1_cb_state[2]), + .C(plm_v4f_mgt_cal_clk), + .D(plm_v4f_mgt_for_v1_4_cal_inst1_gt_do_r_4_i_m2_0_a2_0_a2_1_14_), + .Q(plm_v4f_mgt_gt1_do[14]) + ); + FDE plm_v4f_mgt_for_v1_4_cal_inst1_gt_do_r_13_ ( + .CE(plm_v4f_mgt_for_v1_4_cal_inst1_cb_state[2]), + .C(plm_v4f_mgt_cal_clk), + .D(plm_v4f_mgt_for_v1_4_cal_inst1_gt_do_r_4_i_m2_0_a2_0_a2_1_13_), + .Q(plm_v4f_mgt_gt1_do[13]) + ); + FDE plm_v4f_mgt_for_v1_4_cal_inst1_gt_do_r_12_ ( + .CE(plm_v4f_mgt_for_v1_4_cal_inst1_cb_state[2]), + .C(plm_v4f_mgt_cal_clk), + .D(plm_v4f_mgt_for_v1_4_cal_inst1_gt_do_r_4_i_m2_0_a2_0_a2_0_12_), + .Q(plm_v4f_mgt_gt1_do[12]) + ); + FDE plm_v4f_mgt_for_v1_4_cal_inst1_gt_do_r_11_ ( + .CE(plm_v4f_mgt_for_v1_4_cal_inst1_cb_state[2]), + .C(plm_v4f_mgt_cal_clk), + .D(plm_v4f_mgt_for_v1_4_cal_inst1_gt_do_r_4_i_m2_0_a2_0_a2_1_11_), + .Q(plm_v4f_mgt_gt1_do[11]) + ); + FDE plm_v4f_mgt_for_v1_4_cal_inst1_gt_do_r_10_ ( + .CE(plm_v4f_mgt_for_v1_4_cal_inst1_cb_state[2]), + .C(plm_v4f_mgt_cal_clk), + .D(plm_v4f_mgt_for_v1_4_cal_inst1_gt_do_r_4_i_m2_0_a2_0_a2_1_10_), + .Q(plm_v4f_mgt_gt1_do[10]) + ); + FDE plm_v4f_mgt_for_v1_4_cal_inst1_gt_do_r_9_ ( + .CE(plm_v4f_mgt_for_v1_4_cal_inst1_cb_state[2]), + .C(plm_v4f_mgt_cal_clk), + .D(plm_v4f_mgt_for_v1_4_cal_inst1_gt_do_r_4_i_m2_0_a2_0_a2_1_9_), + .Q(plm_v4f_mgt_gt1_do[9]) + ); + FDE plm_v4f_mgt_for_v1_4_cal_inst1_gt_do_r_8_ ( + .CE(plm_v4f_mgt_for_v1_4_cal_inst1_cb_state[2]), + .C(plm_v4f_mgt_cal_clk), + .D(plm_v4f_mgt_for_v1_4_cal_inst1_gt_do_r_4_i_m2_0_a2_0_a2_1_8_), + .Q(plm_v4f_mgt_gt1_do[8]) + ); + FDE plm_v4f_mgt_for_v1_4_cal_inst1_gt_do_r_7_ ( + .CE(plm_v4f_mgt_for_v1_4_cal_inst1_cb_state[2]), + .C(plm_v4f_mgt_cal_clk), + .D(plm_v4f_mgt_for_v1_4_cal_inst1_gt_do_r_4_i_m2_0_a2_0_a2_1_7_), + .Q(plm_v4f_mgt_gt1_do[7]) + ); + FDE plm_v4f_mgt_for_v1_4_cal_inst1_gt_do_r_6_ ( + .CE(plm_v4f_mgt_for_v1_4_cal_inst1_cb_state[2]), + .C(plm_v4f_mgt_cal_clk), + .D(plm_v4f_mgt_for_v1_4_cal_inst1_gt_do_r_4_i_m2_0_a2_0_a2_1_6_), + .Q(plm_v4f_mgt_gt1_do[6]) + ); + FDE plm_v4f_mgt_for_v1_4_cal_inst1_gt_do_r_5_ ( + .CE(plm_v4f_mgt_for_v1_4_cal_inst1_cb_state[2]), + .C(plm_v4f_mgt_cal_clk), + .D(plm_v4f_mgt_for_v1_4_cal_inst1_gt_do_r_4_i_m2_0_a2_0_a2_1_5_), + .Q(plm_v4f_mgt_gt1_do[5]) + ); + FDE plm_v4f_mgt_for_v1_4_cal_inst1_gt_do_r_4_ ( + .CE(plm_v4f_mgt_for_v1_4_cal_inst1_cb_state[2]), + .C(plm_v4f_mgt_cal_clk), + .D(plm_v4f_mgt_for_v1_4_cal_inst1_gt_do_r_4_i_m2_0_a2_0_a2_1_4_), + .Q(plm_v4f_mgt_gt1_do[4]) + ); + FDE plm_v4f_mgt_for_v1_4_cal_inst1_gt_do_r_3_ ( + .CE(plm_v4f_mgt_for_v1_4_cal_inst1_cb_state[2]), + .C(plm_v4f_mgt_cal_clk), + .D(plm_v4f_mgt_for_v1_4_cal_inst1_gt_do_r_4_i_m2_0_a2_0_a2_1_3_), + .Q(plm_v4f_mgt_gt1_do[3]) + ); + FDE plm_v4f_mgt_for_v1_4_cal_inst1_gt_do_r_2_ ( + .CE(plm_v4f_mgt_for_v1_4_cal_inst1_cb_state[2]), + .C(plm_v4f_mgt_cal_clk), + .D(plm_v4f_mgt_for_v1_4_cal_inst1_gt_do_r_4_i_m2_0_a2_0_a2_1_2_), + .Q(plm_v4f_mgt_gt1_do[2]) + ); + FDE plm_v4f_mgt_for_v1_4_cal_inst1_gt_do_r_1_ ( + .CE(plm_v4f_mgt_for_v1_4_cal_inst1_cb_state[2]), + .C(plm_v4f_mgt_cal_clk), + .D(plm_v4f_mgt_for_v1_4_cal_inst1_gt_do_r_4_i_m2_0_a2_0_a2_0_1_), + .Q(plm_v4f_mgt_gt1_do[1]) + ); + FDE plm_v4f_mgt_for_v1_4_cal_inst1_gt_do_r_0_ ( + .CE(plm_v4f_mgt_for_v1_4_cal_inst1_cb_state[2]), + .C(plm_v4f_mgt_cal_clk), + .D(plm_v4f_mgt_for_v1_4_cal_inst1_gt_do_r_4_i_m2_0_a2_0_a2_1_0_), + .Q(plm_v4f_mgt_gt1_do[0]) + ); + FDE plm_v4f_mgt_for_v1_4_cal_inst1_GT_DADDR_1_5_ ( + .CE(plm_v4f_mgt_for_v1_4_cal_inst1_cb_state[2]), + .C(plm_v4f_mgt_cal_clk), + .D(plm_v4f_mgt_for_v1_4_cal_inst1_N_1540_i), + .Q(plm_v4f_mgt_gt1_daddr[5]) + ); + FDE plm_v4f_mgt_for_v1_4_cal_inst1_GT_DADDR_1_3_ ( + .CE(plm_v4f_mgt_for_v1_4_cal_inst1_cb_state[2]), + .C(plm_v4f_mgt_cal_clk), + .D(plm_v4f_mgt_for_v1_4_cal_inst1_VCC_842), + .Q(plm_v4f_mgt_gt1_daddr[3]) + ); + FDE plm_v4f_mgt_for_v1_4_cal_inst1_GT_DADDR_1_2_ ( + .CE(plm_v4f_mgt_for_v1_4_cal_inst1_cb_state[2]), + .C(plm_v4f_mgt_cal_clk), + .D(plm_v4f_mgt_for_v1_4_cal_inst1_N_1768_i_843), + .Q(plm_v4f_mgt_gt1_daddr[2]) + ); + FDE plm_v4f_mgt_for_v1_4_cal_inst1_GT_DADDR_1_1_ ( + .CE(plm_v4f_mgt_for_v1_4_cal_inst1_cb_state[2]), + .C(plm_v4f_mgt_cal_clk), + .D(plm_v4f_mgt_for_v1_4_cal_inst1_GT_DADDR_5_i_i_a2_0_a2_0[1]), + .Q(plm_v4f_mgt_gt1_daddr[1]) + ); + FDE plm_v4f_mgt_for_v1_4_cal_inst1_GT_DADDR_1_0_ ( + .CE(plm_v4f_mgt_for_v1_4_cal_inst1_cb_state[2]), + .C(plm_v4f_mgt_cal_clk), + .D(plm_v4f_mgt_for_v1_4_cal_inst1_N_1663_i_i_844), + .Q(plm_v4f_mgt_gt1_daddr[4]) + ); + INV plm_v4f_mgt_for_v1_4_cal_inst1_cb_state_i_2_ ( + .I(plm_v4f_mgt_for_v1_4_cal_inst1_cb_state[2]), + .O(plm_v4f_mgt_for_v1_4_cal_inst1_cb_state_i[2]) + ); + VCC plm_v4f_mgt_for_v1_4_cal_inst2_VCC ( + .P(plm_v4f_mgt_for_v1_4_cal_inst2_VCC_871) + ); + FDS plm_v4f_mgt_for_v1_4_cal_inst2_drp_state_0_ ( + .C(plm_v4f_mgt_cal_clk), + .D(plm_v4f_mgt_for_v1_4_cal_inst2_N_2445_i_865), + .Q(plm_v4f_mgt_for_v1_4_cal_inst2_drp_state_0__867), + .S(plm_v4f_mgt_for_v1_4_cal_inst0_reset_r[0]) + ); + FDR plm_v4f_mgt_for_v1_4_cal_inst2_drp_state_1_ ( + .C(plm_v4f_mgt_cal_clk), + .D(plm_v4f_mgt_for_v1_4_cal_inst2_N_977_i), + .Q(plm_v4f_mgt_for_v1_4_cal_inst2_drp_state_1__862), + .R(plm_v4f_mgt_for_v1_4_cal_inst0_reset_r[0]) + ); + FDR plm_v4f_mgt_for_v1_4_cal_inst2_drp_state_2_ ( + .C(plm_v4f_mgt_cal_clk), + .D(plm_v4f_mgt_for_v1_4_cal_inst2_drp_next_state_0_sqmuxa_1), + .Q(plm_v4f_mgt_gt2_dwe), + .R(plm_v4f_mgt_for_v1_4_cal_inst0_reset_r[0]) + ); + FDR plm_v4f_mgt_for_v1_4_cal_inst2_drp_state_3_ ( + .C(plm_v4f_mgt_cal_clk), + .D(plm_v4f_mgt_for_v1_4_cal_inst2_N_2395_i_860), + .Q(plm_v4f_mgt_for_v1_4_cal_inst2_drp_state_3__861), + .R(plm_v4f_mgt_for_v1_4_cal_inst0_reset_r[0]) + ); + FDR plm_v4f_mgt_for_v1_4_cal_inst2_drp_state_4_ ( + .C(plm_v4f_mgt_cal_clk), + .D(plm_v4f_mgt_for_v1_4_cal_inst2_drp_next_state_0_sqmuxa), + .Q(plm_v4f_mgt_for_v1_4_cal_inst2_drp_state_4__866), + .R(plm_v4f_mgt_for_v1_4_cal_inst0_reset_r[0]) + ); + FDS plm_v4f_mgt_for_v1_4_cal_inst2_sd_state_0_ ( + .C(plm_v4f_mgt_cal_clk), + .D(plm_v4f_mgt_for_v1_4_cal_inst2_N_2461_i_858), + .Q(plm_v4f_mgt_for_v1_4_cal_inst2_sd_state[0]), + .S(plm_v4f_mgt_for_v1_4_cal_inst0_reset_r[0]) + ); + FDR plm_v4f_mgt_for_v1_4_cal_inst2_sd_state_1_ ( + .C(plm_v4f_mgt_cal_clk), + .D(plm_v4f_mgt_for_v1_4_cal_inst2_N_2463_i_857), + .Q(plm_v4f_mgt_for_v1_4_cal_inst2_sd_state[1]), + .R(plm_v4f_mgt_for_v1_4_cal_inst0_reset_r[0]) + ); + FDR plm_v4f_mgt_for_v1_4_cal_inst2_sd_state_2_ ( + .C(plm_v4f_mgt_cal_clk), + .D(plm_v4f_mgt_for_v1_4_cal_inst2_sd_next_state_0_sqmuxa), + .Q(plm_v4f_mgt_for_v1_4_cal_inst2_sd_state[2]), + .R(plm_v4f_mgt_for_v1_4_cal_inst0_reset_r[0]) + ); + FDR plm_v4f_mgt_for_v1_4_cal_inst2_sd_state_3_ ( + .C(plm_v4f_mgt_cal_clk), + .D(plm_v4f_mgt_for_v1_4_cal_inst2_N_1678_i_856), + .Q(plm_v4f_mgt_for_v1_4_cal_inst2_sd_state[3]), + .R(plm_v4f_mgt_for_v1_4_cal_inst0_reset_r[0]) + ); + FDR plm_v4f_mgt_for_v1_4_cal_inst2_sd_state_5_ ( + .C(plm_v4f_mgt_cal_clk), + .D(plm_v4f_mgt_for_v1_4_cal_inst2_sd_next_state_0_sqmuxa_1), + .Q(plm_v4f_mgt_for_v1_4_cal_inst2_sd_state[5]), + .R(plm_v4f_mgt_for_v1_4_cal_inst0_reset_r[0]) + ); + FDR plm_v4f_mgt_for_v1_4_cal_inst2_sd_state_6_ ( + .C(plm_v4f_mgt_cal_clk), + .D(plm_v4f_mgt_for_v1_4_cal_inst2_N_1677_i_855), + .Q(plm_v4f_mgt_for_v1_4_cal_inst2_sd_state[6]), + .R(plm_v4f_mgt_for_v1_4_cal_inst0_reset_r[0]) + ); + FDR plm_v4f_mgt_for_v1_4_cal_inst2_sd_state_7_ ( + .C(plm_v4f_mgt_cal_clk), + .D(plm_v4f_mgt_for_v1_4_cal_inst2_N_2459_i_854), + .Q(plm_v4f_mgt_for_v1_4_cal_inst2_sd_state[7]), + .R(plm_v4f_mgt_for_v1_4_cal_inst0_reset_r[0]) + ); + FDR plm_v4f_mgt_for_v1_4_cal_inst2_sd_state_8_ ( + .C(plm_v4f_mgt_cal_clk), + .D(plm_v4f_mgt_for_v1_4_cal_inst2_N_2460_i_853), + .Q(plm_v4f_mgt_for_v1_4_cal_inst2_sd_state[8]), + .R(plm_v4f_mgt_for_v1_4_cal_inst0_reset_r[0]) + ); + FDR plm_v4f_mgt_for_v1_4_cal_inst2_sd_state_9_ ( + .C(plm_v4f_mgt_cal_clk), + .D(plm_v4f_mgt_for_v1_4_cal_inst2_sd_next_state_0_sqmuxa_2), + .Q(plm_v4f_mgt_for_v1_4_cal_inst2_sd_state[9]), + .R(plm_v4f_mgt_for_v1_4_cal_inst0_reset_r[0]) + ); + FDR plm_v4f_mgt_for_v1_4_cal_inst2_sd_state_10_ ( + .C(plm_v4f_mgt_cal_clk), + .D(plm_v4f_mgt_for_v1_4_cal_inst2_N_1675_i_852), + .Q(plm_v4f_mgt_for_v1_4_cal_inst2_sd_state[10]), + .R(plm_v4f_mgt_for_v1_4_cal_inst0_reset_r[0]) + ); + FDR plm_v4f_mgt_for_v1_4_cal_inst2_sd_state_12_ ( + .C(plm_v4f_mgt_cal_clk), + .D(plm_v4f_mgt_for_v1_4_cal_inst2_sd_next_state_0_sqmuxa_3), + .Q(plm_v4f_mgt_for_v1_4_cal_inst2_sd_state[12]), + .R(plm_v4f_mgt_for_v1_4_cal_inst0_reset_r[0]) + ); + FDR plm_v4f_mgt_for_v1_4_cal_inst2_sd_state_13_ ( + .C(plm_v4f_mgt_cal_clk), + .D(plm_v4f_mgt_for_v1_4_cal_inst2_N_2458_i_851), + .Q(plm_v4f_mgt_for_v1_4_cal_inst2_sd_state[13]), + .R(plm_v4f_mgt_for_v1_4_cal_inst0_reset_r[0]) + ); + FDR plm_v4f_mgt_for_v1_4_cal_inst2_GT_DEN ( + .C(plm_v4f_mgt_cal_clk), + .D(plm_v4f_mgt_for_v1_4_cal_inst2_N_979_i), + .Q(plm_v4f_mgt_gt2_den), + .R(plm_v4f_mgt_for_v1_4_cal_inst0_reset_r[0]) + ); + FDR plm_v4f_mgt_for_v1_4_cal_inst2_sd_write ( + .C(plm_v4f_mgt_cal_clk), + .D(plm_v4f_mgt_for_v1_4_cal_inst2_N_1753_i_850), + .Q(plm_v4f_mgt_for_v1_4_cal_inst2_sd_write_863), + .R(plm_v4f_mgt_for_v1_4_cal_inst2_N_1755_i_845) + ); + FDR plm_v4f_mgt_for_v1_4_cal_inst2_sd_read ( + .C(plm_v4f_mgt_cal_clk), + .D(plm_v4f_mgt_for_v1_4_cal_inst2_N_1754_i_849), + .Q(plm_v4f_mgt_for_v1_4_cal_inst2_sd_read_864), + .R(plm_v4f_mgt_for_v1_4_cal_inst2_N_1755_i_845) + ); + FDR plm_v4f_mgt_for_v1_4_cal_inst2_sd_req ( + .C(plm_v4f_mgt_cal_clk), + .D(plm_v4f_mgt_for_v1_4_cal_inst2_N_1804_i_848), + .Q(plm_v4f_mgt_for_v1_4_cal_inst2_sd_req_846), + .R(plm_v4f_mgt_for_v1_4_cal_inst2_N_1755_i_845) + ); + FDRE plm_v4f_mgt_for_v1_4_cal_inst2_sd_state_11_ ( + .CE(plm_v4f_mgt_for_v1_4_cal_inst2_sd_drp_done_859), + .C(plm_v4f_mgt_cal_clk), + .D(plm_v4f_mgt_for_v1_4_cal_inst2_sd_state[10]), + .Q(plm_v4f_mgt_for_v1_4_cal_inst2_sd_state[11]), + .R(plm_v4f_mgt_for_v1_4_cal_inst0_reset_r[0]) + ); + FDRE plm_v4f_mgt_for_v1_4_cal_inst2_sd_state_4_ ( + .CE(plm_v4f_mgt_for_v1_4_cal_inst2_sd_drp_done_859), + .C(plm_v4f_mgt_cal_clk), + .D(plm_v4f_mgt_for_v1_4_cal_inst2_sd_state[3]), + .Q(plm_v4f_mgt_for_v1_4_cal_inst2_sd_state[4]), + .R(plm_v4f_mgt_for_v1_4_cal_inst0_reset_r[0]) + ); + FDR plm_v4f_mgt_for_v1_4_cal_inst2_cb_state_2_ ( + .C(plm_v4f_mgt_cal_clk), + .D(plm_v4f_mgt_for_v1_4_cal_inst2_cb_statec_i_i_847), + .Q(plm_v4f_mgt_for_v1_4_cal_inst2_cb_state[2]), + .R(plm_v4f_mgt_for_v1_4_cal_inst0_reset_r[0]) + ); + FDR plm_v4f_mgt_for_v1_4_cal_inst2_cb_state_1_ ( + .C(plm_v4f_mgt_cal_clk), + .D(plm_v4f_mgt_for_v1_4_cal_inst2_cb_statec_i), + .Q(plm_v4f_mgt_for_v1_4_cal_inst2_cb_state[1]), + .R(plm_v4f_mgt_for_v1_4_cal_inst0_reset_r[0]) + ); + FDR plm_v4f_mgt_for_v1_4_cal_inst2_sd_drp_done ( + .C(plm_v4f_mgt_cal_clk), + .D(plm_v4f_mgt_gt2_drdy), + .Q(plm_v4f_mgt_for_v1_4_cal_inst2_sd_drp_done_859), + .R(plm_v4f_mgt_for_v1_4_cal_inst2_cb_state_i[2]) + ); + defparam plm_v4f_mgt_for_v1_4_cal_inst2_sd_req_3_0_a2_0_a2.INIT = 4'h1; + LUT2 plm_v4f_mgt_for_v1_4_cal_inst2_sd_req_3_0_a2_0_a2 ( + .I0(plm_v4f_mgt_for_v1_4_cal_inst2_sd_read_864), + .I1(plm_v4f_mgt_for_v1_4_cal_inst2_sd_write_863), + .O(plm_v4f_mgt_for_v1_4_cal_inst2_sd_req_3_0_a2_0_a2_1) + ); + defparam plm_v4f_mgt_for_v1_4_cal_inst2_sd_write_3_0_a2_0_o3.INIT = 4'h1; + LUT2 plm_v4f_mgt_for_v1_4_cal_inst2_sd_write_3_0_a2_0_o3 ( + .I0(plm_v4f_mgt_for_v1_4_cal_inst2_sd_state[6]), + .I1(plm_v4f_mgt_for_v1_4_cal_inst2_sd_state[10]), + .O(plm_v4f_mgt_for_v1_4_cal_inst2_N_1657_i) + ); + defparam plm_v4f_mgt_for_v1_4_cal_inst2_sd_wr_wreg_9_0_0_a2_0_0_12_.INIT = 4'h4; + LUT2 plm_v4f_mgt_for_v1_4_cal_inst2_sd_wr_wreg_9_0_0_a2_0_0_12_ ( + .I0(plm_v4f_mgt_for_v1_4_cal_inst2_sd_state[12]), + .I1(plm_v4f_mgt_for_v1_4_cal_inst2_sd_wr_wreg[12]), + .O(plm_v4f_mgt_for_v1_4_cal_inst2_sd_wr_wreg_9_0_0_a2_0[12]) + ); + defparam plm_v4f_mgt_for_v1_4_cal_inst2_N_1755_i.INIT = 4'hE; + LUT2 plm_v4f_mgt_for_v1_4_cal_inst2_N_1755_i ( + .I0(plm_v4f_mgt_for_v1_4_cal_inst2_sd_drp_done_859), + .I1(plm_v4f_mgt_for_v1_4_cal_inst2_sd_state[0]), + .O(plm_v4f_mgt_for_v1_4_cal_inst2_N_1755_i_845) + ); + defparam plm_v4f_mgt_for_v1_4_cal_inst2_cb_state_4_i_a2_2_.INIT = 16'h51F3; + LUT4 plm_v4f_mgt_for_v1_4_cal_inst2_cb_state_4_i_a2_2_ ( + .I0(plm_v4f_mgt_for_v1_4_cal_inst2_cb_state[1]), + .I1(plm_v4f_mgt_for_v1_4_cal_inst2_cb_state[2]), + .I2(plm_v4f_mgt_for_v1_4_cal_inst2_gt_drdy_r_868), + .I3(plm_v4f_mgt_for_v1_4_cal_inst2_sd_req_846), + .O(plm_v4f_mgt_for_v1_4_cal_inst2_cb_statec_i) + ); + defparam plm_v4f_mgt_for_v1_4_cal_inst2_sd_wr_wreg_9_0_0_o2_12_.INIT = 8'h80; + LUT3 plm_v4f_mgt_for_v1_4_cal_inst2_sd_wr_wreg_9_0_0_o2_12_ ( + .I0(plm_v4f_mgt_for_v1_4_cal_inst2_cb_state[2]), + .I1(plm_v4f_mgt_for_v1_4_cal_inst2_sd_read_864), + .I2(plm_v4f_mgt_gt2_drdy), + .O(plm_v4f_mgt_for_v1_4_cal_inst2_N_1644_i) + ); + defparam plm_v4f_mgt_for_v1_4_cal_inst2_sd_wr_wreg_9_i_i_m2_1_.INIT = 8'h1B; + LUT3_L plm_v4f_mgt_for_v1_4_cal_inst2_sd_wr_wreg_9_i_i_m2_1_ ( + .I0(plm_v4f_mgt_for_v1_4_cal_inst2_N_1644_i), + .I1(plm_v4f_mgt_for_v1_4_cal_inst2_sd_state[5]), + .I2(plm_v4f_mgt_gt2_di[1]), + .LO(plm_v4f_mgt_for_v1_4_cal_inst2_sd_wr_wreg_9_i_i_m2_0[1]) + ); + defparam plm_v4f_mgt_for_v1_4_cal_inst2_cb_statec_i_i.INIT = 4'h1; + LUT1_L plm_v4f_mgt_for_v1_4_cal_inst2_cb_statec_i_i ( + .I0(plm_v4f_mgt_for_v1_4_cal_inst2_cb_statec_i), + .LO(plm_v4f_mgt_for_v1_4_cal_inst2_cb_statec_i_i_847) + ); + defparam plm_v4f_mgt_for_v1_4_cal_inst2_N_2462_i.INIT = 16'h3733; + LUT4_L plm_v4f_mgt_for_v1_4_cal_inst2_N_2462_i ( + .I0(plm_v4f_mgt_for_v1_4_cal_inst2_N_1644_i), + .I1(plm_v4f_mgt_for_v1_4_cal_inst2_sd_wr_wreg_9_i_i_m2_0[1]), + .I2(plm_v4f_mgt_for_v1_4_cal_inst2_sd_state[9]), + .I3(plm_v4f_mgt_for_v1_4_cal_inst2_sd_wr_wreg[1]), + .LO(plm_v4f_mgt_for_v1_4_cal_inst2_N_2462_i_869) + ); + defparam plm_v4f_mgt_for_v1_4_cal_inst2_N_2464_i.INIT = 16'hBA10; + LUT4_L plm_v4f_mgt_for_v1_4_cal_inst2_N_2464_i ( + .I0(plm_v4f_mgt_for_v1_4_cal_inst2_N_1644_i), + .I1(plm_v4f_mgt_for_v1_4_cal_inst2_sd_state[2]), + .I2(plm_v4f_mgt_for_v1_4_cal_inst2_sd_wr_wreg_9_0_0_a2_0[12]), + .I3(plm_v4f_mgt_gt2_di[12]), + .LO(plm_v4f_mgt_for_v1_4_cal_inst2_N_2464_i_870) + ); + defparam plm_v4f_mgt_for_v1_4_cal_inst2_gt_do_r_4_i_m2_0_a2_0_a2_15_.INIT = 4'h8; + LUT2_L plm_v4f_mgt_for_v1_4_cal_inst2_gt_do_r_4_i_m2_0_a2_0_a2_15_ ( + .I0(plm_v4f_mgt_for_v1_4_cal_inst2_cb_state[2]), + .I1(plm_v4f_mgt_for_v1_4_cal_inst2_sd_wr_wreg[15]), + .LO(plm_v4f_mgt_for_v1_4_cal_inst2_gt_do_r_4_i_m2_0_a2_0_a2_0_15_) + ); + defparam plm_v4f_mgt_for_v1_4_cal_inst2_gt_do_r_4_i_m2_0_a2_0_a2_14_.INIT = 4'h8; + LUT2_L plm_v4f_mgt_for_v1_4_cal_inst2_gt_do_r_4_i_m2_0_a2_0_a2_14_ ( + .I0(plm_v4f_mgt_for_v1_4_cal_inst2_cb_state[2]), + .I1(plm_v4f_mgt_for_v1_4_cal_inst2_sd_wr_wreg[14]), + .LO(plm_v4f_mgt_for_v1_4_cal_inst2_gt_do_r_4_i_m2_0_a2_0_a2_0_14_) + ); + defparam plm_v4f_mgt_for_v1_4_cal_inst2_gt_do_r_4_i_m2_0_a2_0_a2_13_.INIT = 4'h8; + LUT2_L plm_v4f_mgt_for_v1_4_cal_inst2_gt_do_r_4_i_m2_0_a2_0_a2_13_ ( + .I0(plm_v4f_mgt_for_v1_4_cal_inst2_cb_state[2]), + .I1(plm_v4f_mgt_for_v1_4_cal_inst2_sd_wr_wreg[13]), + .LO(plm_v4f_mgt_for_v1_4_cal_inst2_gt_do_r_4_i_m2_0_a2_0_a2_0_13_) + ); + defparam plm_v4f_mgt_for_v1_4_cal_inst2_gt_do_r_4_i_m2_0_a2_0_a2_12_.INIT = 4'h8; + LUT2_L plm_v4f_mgt_for_v1_4_cal_inst2_gt_do_r_4_i_m2_0_a2_0_a2_12_ ( + .I0(plm_v4f_mgt_for_v1_4_cal_inst2_cb_state[2]), + .I1(plm_v4f_mgt_for_v1_4_cal_inst2_sd_wr_wreg[12]), + .LO(plm_v4f_mgt_for_v1_4_cal_inst2_gt_do_r_4_i_m2_0_a2_0_a2_1_12_) + ); + defparam plm_v4f_mgt_for_v1_4_cal_inst2_gt_do_r_4_i_m2_0_a2_0_a2_11_.INIT = 4'h8; + LUT2_L plm_v4f_mgt_for_v1_4_cal_inst2_gt_do_r_4_i_m2_0_a2_0_a2_11_ ( + .I0(plm_v4f_mgt_for_v1_4_cal_inst2_cb_state[2]), + .I1(plm_v4f_mgt_for_v1_4_cal_inst2_sd_wr_wreg[11]), + .LO(plm_v4f_mgt_for_v1_4_cal_inst2_gt_do_r_4_i_m2_0_a2_0_a2_0_11_) + ); + defparam plm_v4f_mgt_for_v1_4_cal_inst2_gt_do_r_4_i_m2_0_a2_0_a2_10_.INIT = 4'h8; + LUT2_L plm_v4f_mgt_for_v1_4_cal_inst2_gt_do_r_4_i_m2_0_a2_0_a2_10_ ( + .I0(plm_v4f_mgt_for_v1_4_cal_inst2_cb_state[2]), + .I1(plm_v4f_mgt_for_v1_4_cal_inst2_sd_wr_wreg[10]), + .LO(plm_v4f_mgt_for_v1_4_cal_inst2_gt_do_r_4_i_m2_0_a2_0_a2_0_10_) + ); + defparam plm_v4f_mgt_for_v1_4_cal_inst2_gt_do_r_4_i_m2_0_a2_0_a2_9_.INIT = 4'h8; + LUT2_L plm_v4f_mgt_for_v1_4_cal_inst2_gt_do_r_4_i_m2_0_a2_0_a2_9_ ( + .I0(plm_v4f_mgt_for_v1_4_cal_inst2_cb_state[2]), + .I1(plm_v4f_mgt_for_v1_4_cal_inst2_sd_wr_wreg[9]), + .LO(plm_v4f_mgt_for_v1_4_cal_inst2_gt_do_r_4_i_m2_0_a2_0_a2_0_9_) + ); + defparam plm_v4f_mgt_for_v1_4_cal_inst2_gt_do_r_4_i_m2_0_a2_0_a2_8_.INIT = 4'h8; + LUT2_L plm_v4f_mgt_for_v1_4_cal_inst2_gt_do_r_4_i_m2_0_a2_0_a2_8_ ( + .I0(plm_v4f_mgt_for_v1_4_cal_inst2_cb_state[2]), + .I1(plm_v4f_mgt_for_v1_4_cal_inst2_sd_wr_wreg[8]), + .LO(plm_v4f_mgt_for_v1_4_cal_inst2_gt_do_r_4_i_m2_0_a2_0_a2_0_8_) + ); + defparam plm_v4f_mgt_for_v1_4_cal_inst2_gt_do_r_4_i_m2_0_a2_0_a2_7_.INIT = 4'h8; + LUT2_L plm_v4f_mgt_for_v1_4_cal_inst2_gt_do_r_4_i_m2_0_a2_0_a2_7_ ( + .I0(plm_v4f_mgt_for_v1_4_cal_inst2_cb_state[2]), + .I1(plm_v4f_mgt_for_v1_4_cal_inst2_sd_wr_wreg[7]), + .LO(plm_v4f_mgt_for_v1_4_cal_inst2_gt_do_r_4_i_m2_0_a2_0_a2_0_7_) + ); + defparam plm_v4f_mgt_for_v1_4_cal_inst2_gt_do_r_4_i_m2_0_a2_0_a2_6_.INIT = 4'h8; + LUT2_L plm_v4f_mgt_for_v1_4_cal_inst2_gt_do_r_4_i_m2_0_a2_0_a2_6_ ( + .I0(plm_v4f_mgt_for_v1_4_cal_inst2_cb_state[2]), + .I1(plm_v4f_mgt_for_v1_4_cal_inst2_sd_wr_wreg[6]), + .LO(plm_v4f_mgt_for_v1_4_cal_inst2_gt_do_r_4_i_m2_0_a2_0_a2_0_6_) + ); + defparam plm_v4f_mgt_for_v1_4_cal_inst2_gt_do_r_4_i_m2_0_a2_0_a2_5_.INIT = 4'h8; + LUT2_L plm_v4f_mgt_for_v1_4_cal_inst2_gt_do_r_4_i_m2_0_a2_0_a2_5_ ( + .I0(plm_v4f_mgt_for_v1_4_cal_inst2_cb_state[2]), + .I1(plm_v4f_mgt_for_v1_4_cal_inst2_sd_wr_wreg[5]), + .LO(plm_v4f_mgt_for_v1_4_cal_inst2_gt_do_r_4_i_m2_0_a2_0_a2_0_5_) + ); + defparam plm_v4f_mgt_for_v1_4_cal_inst2_gt_do_r_4_i_m2_0_a2_0_a2_4_.INIT = 4'h8; + LUT2_L plm_v4f_mgt_for_v1_4_cal_inst2_gt_do_r_4_i_m2_0_a2_0_a2_4_ ( + .I0(plm_v4f_mgt_for_v1_4_cal_inst2_cb_state[2]), + .I1(plm_v4f_mgt_for_v1_4_cal_inst2_sd_wr_wreg[4]), + .LO(plm_v4f_mgt_for_v1_4_cal_inst2_gt_do_r_4_i_m2_0_a2_0_a2_0_4_) + ); + defparam plm_v4f_mgt_for_v1_4_cal_inst2_gt_do_r_4_i_m2_0_a2_0_a2_3_.INIT = 4'h8; + LUT2_L plm_v4f_mgt_for_v1_4_cal_inst2_gt_do_r_4_i_m2_0_a2_0_a2_3_ ( + .I0(plm_v4f_mgt_for_v1_4_cal_inst2_cb_state[2]), + .I1(plm_v4f_mgt_for_v1_4_cal_inst2_sd_wr_wreg[3]), + .LO(plm_v4f_mgt_for_v1_4_cal_inst2_gt_do_r_4_i_m2_0_a2_0_a2_0_3_) + ); + defparam plm_v4f_mgt_for_v1_4_cal_inst2_gt_do_r_4_i_m2_0_a2_0_a2_2_.INIT = 4'h8; + LUT2_L plm_v4f_mgt_for_v1_4_cal_inst2_gt_do_r_4_i_m2_0_a2_0_a2_2_ ( + .I0(plm_v4f_mgt_for_v1_4_cal_inst2_cb_state[2]), + .I1(plm_v4f_mgt_for_v1_4_cal_inst2_sd_wr_wreg[2]), + .LO(plm_v4f_mgt_for_v1_4_cal_inst2_gt_do_r_4_i_m2_0_a2_0_a2_0_2_) + ); + defparam plm_v4f_mgt_for_v1_4_cal_inst2_gt_do_r_4_i_m2_0_a2_0_a2_1_.INIT = 4'h8; + LUT2_L plm_v4f_mgt_for_v1_4_cal_inst2_gt_do_r_4_i_m2_0_a2_0_a2_1_ ( + .I0(plm_v4f_mgt_for_v1_4_cal_inst2_cb_state[2]), + .I1(plm_v4f_mgt_for_v1_4_cal_inst2_sd_wr_wreg[1]), + .LO(plm_v4f_mgt_for_v1_4_cal_inst2_gt_do_r_4_i_m2_0_a2_0_a2_1_1_) + ); + defparam plm_v4f_mgt_for_v1_4_cal_inst2_gt_do_r_4_i_m2_0_a2_0_a2_0_.INIT = 4'h8; + LUT2_L plm_v4f_mgt_for_v1_4_cal_inst2_gt_do_r_4_i_m2_0_a2_0_a2_0_ ( + .I0(plm_v4f_mgt_for_v1_4_cal_inst2_cb_state[2]), + .I1(plm_v4f_mgt_for_v1_4_cal_inst2_sd_wr_wreg[0]), + .LO(plm_v4f_mgt_for_v1_4_cal_inst2_gt_do_r_4_i_m2_0_a2_0_a2_0_0_) + ); + defparam plm_v4f_mgt_for_v1_4_cal_inst2_N_1804_i.INIT = 4'h1; + LUT1_L plm_v4f_mgt_for_v1_4_cal_inst2_N_1804_i ( + .I0(plm_v4f_mgt_for_v1_4_cal_inst2_sd_req_3_0_a2_0_a2_1), + .LO(plm_v4f_mgt_for_v1_4_cal_inst2_N_1804_i_848) + ); + defparam plm_v4f_mgt_for_v1_4_cal_inst2_N_1754_i.INIT = 16'hFFFE; + LUT4_L plm_v4f_mgt_for_v1_4_cal_inst2_N_1754_i ( + .I0(plm_v4f_mgt_for_v1_4_cal_inst2_sd_state[1]), + .I1(plm_v4f_mgt_for_v1_4_cal_inst2_sd_state[4]), + .I2(plm_v4f_mgt_for_v1_4_cal_inst2_sd_state[8]), + .I3(plm_v4f_mgt_for_v1_4_cal_inst2_sd_state[11]), + .LO(plm_v4f_mgt_for_v1_4_cal_inst2_N_1754_i_849) + ); + defparam plm_v4f_mgt_for_v1_4_cal_inst2_N_1753_i.INIT = 8'hFD; + LUT3_L plm_v4f_mgt_for_v1_4_cal_inst2_N_1753_i ( + .I0(plm_v4f_mgt_for_v1_4_cal_inst2_N_1657_i), + .I1(plm_v4f_mgt_for_v1_4_cal_inst2_sd_state[3]), + .I2(plm_v4f_mgt_for_v1_4_cal_inst2_sd_state[13]), + .LO(plm_v4f_mgt_for_v1_4_cal_inst2_N_1753_i_850) + ); + defparam plm_v4f_mgt_for_v1_4_cal_inst2_GT_DEN_3_i_0.INIT = 8'h40; + LUT3_L plm_v4f_mgt_for_v1_4_cal_inst2_GT_DEN_3_i_0 ( + .I0(plm_v4f_mgt_for_v1_4_cal_inst2_sd_req_3_0_a2_0_a2_1), + .I1(plm_v4f_mgt_for_v1_4_cal_inst2_cb_state[2]), + .I2(plm_v4f_mgt_for_v1_4_cal_inst2_drp_state_0__867), + .LO(plm_v4f_mgt_for_v1_4_cal_inst2_N_979_i) + ); + defparam plm_v4f_mgt_for_v1_4_cal_inst2_GT_DADDR_5_i_i_a2_i_5_.INIT = 16'h00FD; + LUT4_L plm_v4f_mgt_for_v1_4_cal_inst2_GT_DADDR_5_i_i_a2_i_5_ ( + .I0(plm_v4f_mgt_for_v1_4_cal_inst2_N_1657_i), + .I1(plm_v4f_mgt_for_v1_4_cal_inst2_sd_state[4]), + .I2(plm_v4f_mgt_for_v1_4_cal_inst2_sd_state[8]), + .I3(cfg_cfg_6102[509]), + .LO(plm_v4f_mgt_for_v1_4_cal_inst2_N_1532_i) + ); + defparam plm_v4f_mgt_for_v1_4_cal_inst2_N_1743_i.INIT = 16'h02FF; + LUT4_L plm_v4f_mgt_for_v1_4_cal_inst2_N_1743_i ( + .I0(plm_v4f_mgt_for_v1_4_cal_inst2_N_1657_i), + .I1(plm_v4f_mgt_for_v1_4_cal_inst2_sd_state[4]), + .I2(plm_v4f_mgt_for_v1_4_cal_inst2_sd_state[8]), + .I3(cfg_cfg_6102[509]), + .LO(plm_v4f_mgt_for_v1_4_cal_inst2_N_1743_i_872) + ); + defparam plm_v4f_mgt_for_v1_4_cal_inst2_GT_DADDR_5_i_i_a2_0_a2_1_.INIT = 16'h0200; + LUT4_L plm_v4f_mgt_for_v1_4_cal_inst2_GT_DADDR_5_i_i_a2_0_a2_1_ ( + .I0(plm_v4f_mgt_for_v1_4_cal_inst2_N_1657_i), + .I1(plm_v4f_mgt_for_v1_4_cal_inst2_sd_state[4]), + .I2(plm_v4f_mgt_for_v1_4_cal_inst2_sd_state[8]), + .I3(cfg_cfg_6102[509]), + .LO(plm_v4f_mgt_for_v1_4_cal_inst2_GT_DADDR_5_i_i_a2_0_a2_1[1]) + ); + defparam plm_v4f_mgt_for_v1_4_cal_inst2_N_1664_i_i.INIT = 8'hFD; + LUT3_L plm_v4f_mgt_for_v1_4_cal_inst2_N_1664_i_i ( + .I0(plm_v4f_mgt_for_v1_4_cal_inst2_N_1657_i), + .I1(plm_v4f_mgt_for_v1_4_cal_inst2_sd_state[4]), + .I2(plm_v4f_mgt_for_v1_4_cal_inst2_sd_state[8]), + .LO(plm_v4f_mgt_for_v1_4_cal_inst2_N_1664_i_i_873) + ); + defparam plm_v4f_mgt_for_v1_4_cal_inst2_N_2458_i.INIT = 8'hDC; + LUT3_L plm_v4f_mgt_for_v1_4_cal_inst2_N_2458_i ( + .I0(plm_v4f_mgt_for_v1_4_cal_inst2_sd_drp_done_859), + .I1(plm_v4f_mgt_for_v1_4_cal_inst2_sd_state[12]), + .I2(plm_v4f_mgt_for_v1_4_cal_inst2_sd_state[13]), + .LO(plm_v4f_mgt_for_v1_4_cal_inst2_N_2458_i_851) + ); + defparam plm_v4f_mgt_for_v1_4_cal_inst2_sd_next_state_0_sqmuxa_3_0_a2_0_a2.INIT = 4'h8; + LUT2_L plm_v4f_mgt_for_v1_4_cal_inst2_sd_next_state_0_sqmuxa_3_0_a2_0_a2 ( + .I0(plm_v4f_mgt_for_v1_4_cal_inst2_sd_drp_done_859), + .I1(plm_v4f_mgt_for_v1_4_cal_inst2_sd_state[11]), + .LO(plm_v4f_mgt_for_v1_4_cal_inst2_sd_next_state_0_sqmuxa_3) + ); + defparam plm_v4f_mgt_for_v1_4_cal_inst2_N_1675_i.INIT = 8'h5C; + LUT3_L plm_v4f_mgt_for_v1_4_cal_inst2_N_1675_i ( + .I0(plm_v4f_mgt_for_v1_4_cal_inst2_sd_drp_done_859), + .I1(plm_v4f_mgt_for_v1_4_cal_inst2_sd_state[9]), + .I2(plm_v4f_mgt_for_v1_4_cal_inst2_sd_state[10]), + .LO(plm_v4f_mgt_for_v1_4_cal_inst2_N_1675_i_852) + ); + defparam plm_v4f_mgt_for_v1_4_cal_inst2_sd_next_state_0_sqmuxa_2_0_a2_0_a2.INIT = 4'h8; + LUT2_L plm_v4f_mgt_for_v1_4_cal_inst2_sd_next_state_0_sqmuxa_2_0_a2_0_a2 ( + .I0(plm_v4f_mgt_for_v1_4_cal_inst2_sd_drp_done_859), + .I1(plm_v4f_mgt_for_v1_4_cal_inst2_sd_state[8]), + .LO(plm_v4f_mgt_for_v1_4_cal_inst2_sd_next_state_0_sqmuxa_2) + ); + defparam plm_v4f_mgt_for_v1_4_cal_inst2_N_2460_i.INIT = 16'hB3A0; + LUT4_L plm_v4f_mgt_for_v1_4_cal_inst2_N_2460_i ( + .I0(cmmp_negotiated_width_0[0]), + .I1(plm_v4f_mgt_for_v1_4_cal_inst2_sd_drp_done_859), + .I2(plm_v4f_mgt_for_v1_4_cal_inst2_sd_state[7]), + .I3(plm_v4f_mgt_for_v1_4_cal_inst2_sd_state[8]), + .LO(plm_v4f_mgt_for_v1_4_cal_inst2_N_2460_i_853) + ); + defparam plm_v4f_mgt_for_v1_4_cal_inst2_N_2459_i.INIT = 16'hD5C0; + LUT4_L plm_v4f_mgt_for_v1_4_cal_inst2_N_2459_i ( + .I0(cmmp_negotiated_width_0[0]), + .I1(plm_v4f_mgt_for_v1_4_cal_inst2_sd_drp_done_859), + .I2(plm_v4f_mgt_for_v1_4_cal_inst2_sd_state[6]), + .I3(plm_v4f_mgt_for_v1_4_cal_inst2_sd_state[7]), + .LO(plm_v4f_mgt_for_v1_4_cal_inst2_N_2459_i_854) + ); + defparam plm_v4f_mgt_for_v1_4_cal_inst2_N_1677_i.INIT = 8'h5C; + LUT3_L plm_v4f_mgt_for_v1_4_cal_inst2_N_1677_i ( + .I0(plm_v4f_mgt_for_v1_4_cal_inst2_sd_drp_done_859), + .I1(plm_v4f_mgt_for_v1_4_cal_inst2_sd_state[5]), + .I2(plm_v4f_mgt_for_v1_4_cal_inst2_sd_state[6]), + .LO(plm_v4f_mgt_for_v1_4_cal_inst2_N_1677_i_855) + ); + defparam plm_v4f_mgt_for_v1_4_cal_inst2_sd_next_state_0_sqmuxa_1_0_a2_0_a2.INIT = 4'h8; + LUT2_L plm_v4f_mgt_for_v1_4_cal_inst2_sd_next_state_0_sqmuxa_1_0_a2_0_a2 ( + .I0(plm_v4f_mgt_for_v1_4_cal_inst2_sd_drp_done_859), + .I1(plm_v4f_mgt_for_v1_4_cal_inst2_sd_state[4]), + .LO(plm_v4f_mgt_for_v1_4_cal_inst2_sd_next_state_0_sqmuxa_1) + ); + defparam plm_v4f_mgt_for_v1_4_cal_inst2_N_1678_i.INIT = 8'h5C; + LUT3_L plm_v4f_mgt_for_v1_4_cal_inst2_N_1678_i ( + .I0(plm_v4f_mgt_for_v1_4_cal_inst2_sd_drp_done_859), + .I1(plm_v4f_mgt_for_v1_4_cal_inst2_sd_state[2]), + .I2(plm_v4f_mgt_for_v1_4_cal_inst2_sd_state[3]), + .LO(plm_v4f_mgt_for_v1_4_cal_inst2_N_1678_i_856) + ); + defparam plm_v4f_mgt_for_v1_4_cal_inst2_sd_next_state_0_sqmuxa_0_a2_0_a2.INIT = 4'h8; + LUT2_L plm_v4f_mgt_for_v1_4_cal_inst2_sd_next_state_0_sqmuxa_0_a2_0_a2 ( + .I0(plm_v4f_mgt_for_v1_4_cal_inst2_sd_drp_done_859), + .I1(plm_v4f_mgt_for_v1_4_cal_inst2_sd_state[1]), + .LO(plm_v4f_mgt_for_v1_4_cal_inst2_sd_next_state_0_sqmuxa) + ); + defparam plm_v4f_mgt_for_v1_4_cal_inst2_N_2463_i.INIT = 16'h3350; + LUT4_L plm_v4f_mgt_for_v1_4_cal_inst2_N_2463_i ( + .I0(cmmp_negotiated_width_0[0]), + .I1(plm_v4f_mgt_for_v1_4_cal_inst2_sd_drp_done_859), + .I2(plm_v4f_mgt_for_v1_4_cal_inst2_sd_state[0]), + .I3(plm_v4f_mgt_for_v1_4_cal_inst2_sd_state[1]), + .LO(plm_v4f_mgt_for_v1_4_cal_inst2_N_2463_i_857) + ); + defparam plm_v4f_mgt_for_v1_4_cal_inst2_N_2461_i.INIT = 16'hCCA0; + LUT4_L plm_v4f_mgt_for_v1_4_cal_inst2_N_2461_i ( + .I0(cmmp_negotiated_width_0[0]), + .I1(plm_v4f_mgt_for_v1_4_cal_inst2_sd_drp_done_859), + .I2(plm_v4f_mgt_for_v1_4_cal_inst2_sd_state[0]), + .I3(plm_v4f_mgt_for_v1_4_cal_inst2_sd_state[13]), + .LO(plm_v4f_mgt_for_v1_4_cal_inst2_N_2461_i_858) + ); + defparam plm_v4f_mgt_for_v1_4_cal_inst2_drp_next_state_0_sqmuxa_0_a2.INIT = 4'h8; + LUT2_L plm_v4f_mgt_for_v1_4_cal_inst2_drp_next_state_0_sqmuxa_0_a2 ( + .I0(plm_v4f_mgt_for_v1_4_cal_inst2_drp_state_3__861), + .I1(plm_v4f_mgt_for_v1_4_cal_inst2_gt_drdy_r_868), + .LO(plm_v4f_mgt_for_v1_4_cal_inst2_drp_next_state_0_sqmuxa) + ); + defparam plm_v4f_mgt_for_v1_4_cal_inst2_N_2395_i.INIT = 16'hFFAE; + LUT4_L plm_v4f_mgt_for_v1_4_cal_inst2_N_2395_i ( + .I0(plm_v4f_mgt_for_v1_4_cal_inst2_drp_state_1__862), + .I1(plm_v4f_mgt_for_v1_4_cal_inst2_drp_state_3__861), + .I2(plm_v4f_mgt_for_v1_4_cal_inst2_gt_drdy_r_868), + .I3(plm_v4f_mgt_gt2_dwe), + .LO(plm_v4f_mgt_for_v1_4_cal_inst2_N_2395_i_860) + ); + defparam plm_v4f_mgt_for_v1_4_cal_inst2_drp_next_state_0_sqmuxa_1_0_a2_0_a2.INIT = 8'h80; + LUT3_L plm_v4f_mgt_for_v1_4_cal_inst2_drp_next_state_0_sqmuxa_1_0_a2_0_a2 ( + .I0(plm_v4f_mgt_for_v1_4_cal_inst2_cb_state[2]), + .I1(plm_v4f_mgt_for_v1_4_cal_inst2_drp_state_0__867), + .I2(plm_v4f_mgt_for_v1_4_cal_inst2_sd_write_863), + .LO(plm_v4f_mgt_for_v1_4_cal_inst2_drp_next_state_0_sqmuxa_1) + ); + defparam plm_v4f_mgt_for_v1_4_cal_inst2_drp_next_state_1_sqmuxa_1_i_0.INIT = 8'h80; + LUT3_L plm_v4f_mgt_for_v1_4_cal_inst2_drp_next_state_1_sqmuxa_1_i_0 ( + .I0(plm_v4f_mgt_for_v1_4_cal_inst2_cb_state[2]), + .I1(plm_v4f_mgt_for_v1_4_cal_inst2_drp_state_0__867), + .I2(plm_v4f_mgt_for_v1_4_cal_inst2_sd_read_864), + .LO(plm_v4f_mgt_for_v1_4_cal_inst2_N_977_i) + ); + defparam plm_v4f_mgt_for_v1_4_cal_inst2_N_2445_i.INIT = 16'hFFB0; + LUT4_L plm_v4f_mgt_for_v1_4_cal_inst2_N_2445_i ( + .I0(plm_v4f_mgt_for_v1_4_cal_inst2_sd_req_3_0_a2_0_a2_1), + .I1(plm_v4f_mgt_for_v1_4_cal_inst2_cb_state[2]), + .I2(plm_v4f_mgt_for_v1_4_cal_inst2_drp_state_0__867), + .I3(plm_v4f_mgt_for_v1_4_cal_inst2_drp_state_4__866), + .LO(plm_v4f_mgt_for_v1_4_cal_inst2_N_2445_i_865) + ); + FD plm_v4f_mgt_for_v1_4_cal_inst2_gt_drdy_r ( + .C(plm_v4f_mgt_cal_clk), + .D(plm_v4f_mgt_gt2_drdy), + .Q(plm_v4f_mgt_for_v1_4_cal_inst2_gt_drdy_r_868) + ); + FDE plm_v4f_mgt_for_v1_4_cal_inst2_sd_wr_wreg_9_ ( + .CE(plm_v4f_mgt_for_v1_4_cal_inst2_N_1644_i), + .C(plm_v4f_mgt_cal_clk), + .D(plm_v4f_mgt_gt2_di[9]), + .Q(plm_v4f_mgt_for_v1_4_cal_inst2_sd_wr_wreg[9]) + ); + FDE plm_v4f_mgt_for_v1_4_cal_inst2_sd_wr_wreg_8_ ( + .CE(plm_v4f_mgt_for_v1_4_cal_inst2_N_1644_i), + .C(plm_v4f_mgt_cal_clk), + .D(plm_v4f_mgt_gt2_di[8]), + .Q(plm_v4f_mgt_for_v1_4_cal_inst2_sd_wr_wreg[8]) + ); + FDE plm_v4f_mgt_for_v1_4_cal_inst2_sd_wr_wreg_7_ ( + .CE(plm_v4f_mgt_for_v1_4_cal_inst2_N_1644_i), + .C(plm_v4f_mgt_cal_clk), + .D(plm_v4f_mgt_gt2_di[7]), + .Q(plm_v4f_mgt_for_v1_4_cal_inst2_sd_wr_wreg[7]) + ); + FDE plm_v4f_mgt_for_v1_4_cal_inst2_sd_wr_wreg_6_ ( + .CE(plm_v4f_mgt_for_v1_4_cal_inst2_N_1644_i), + .C(plm_v4f_mgt_cal_clk), + .D(plm_v4f_mgt_gt2_di[6]), + .Q(plm_v4f_mgt_for_v1_4_cal_inst2_sd_wr_wreg[6]) + ); + FDE plm_v4f_mgt_for_v1_4_cal_inst2_sd_wr_wreg_5_ ( + .CE(plm_v4f_mgt_for_v1_4_cal_inst2_N_1644_i), + .C(plm_v4f_mgt_cal_clk), + .D(plm_v4f_mgt_gt2_di[5]), + .Q(plm_v4f_mgt_for_v1_4_cal_inst2_sd_wr_wreg[5]) + ); + FDE plm_v4f_mgt_for_v1_4_cal_inst2_sd_wr_wreg_4_ ( + .CE(plm_v4f_mgt_for_v1_4_cal_inst2_N_1644_i), + .C(plm_v4f_mgt_cal_clk), + .D(plm_v4f_mgt_gt2_di[4]), + .Q(plm_v4f_mgt_for_v1_4_cal_inst2_sd_wr_wreg[4]) + ); + FDE plm_v4f_mgt_for_v1_4_cal_inst2_sd_wr_wreg_3_ ( + .CE(plm_v4f_mgt_for_v1_4_cal_inst2_N_1644_i), + .C(plm_v4f_mgt_cal_clk), + .D(plm_v4f_mgt_gt2_di[3]), + .Q(plm_v4f_mgt_for_v1_4_cal_inst2_sd_wr_wreg[3]) + ); + FDE plm_v4f_mgt_for_v1_4_cal_inst2_sd_wr_wreg_2_ ( + .CE(plm_v4f_mgt_for_v1_4_cal_inst2_N_1644_i), + .C(plm_v4f_mgt_cal_clk), + .D(plm_v4f_mgt_gt2_di[2]), + .Q(plm_v4f_mgt_for_v1_4_cal_inst2_sd_wr_wreg[2]) + ); + FD plm_v4f_mgt_for_v1_4_cal_inst2_sd_wr_wreg_1_ ( + .C(plm_v4f_mgt_cal_clk), + .D(plm_v4f_mgt_for_v1_4_cal_inst2_N_2462_i_869), + .Q(plm_v4f_mgt_for_v1_4_cal_inst2_sd_wr_wreg[1]) + ); + FDE plm_v4f_mgt_for_v1_4_cal_inst2_sd_wr_wreg_0_ ( + .CE(plm_v4f_mgt_for_v1_4_cal_inst2_N_1644_i), + .C(plm_v4f_mgt_cal_clk), + .D(plm_v4f_mgt_gt2_di[0]), + .Q(plm_v4f_mgt_for_v1_4_cal_inst2_sd_wr_wreg[0]) + ); + FDE plm_v4f_mgt_for_v1_4_cal_inst2_sd_wr_wreg_15_ ( + .CE(plm_v4f_mgt_for_v1_4_cal_inst2_N_1644_i), + .C(plm_v4f_mgt_cal_clk), + .D(plm_v4f_mgt_gt2_di[15]), + .Q(plm_v4f_mgt_for_v1_4_cal_inst2_sd_wr_wreg[15]) + ); + FDE plm_v4f_mgt_for_v1_4_cal_inst2_sd_wr_wreg_14_ ( + .CE(plm_v4f_mgt_for_v1_4_cal_inst2_N_1644_i), + .C(plm_v4f_mgt_cal_clk), + .D(plm_v4f_mgt_gt2_di[14]), + .Q(plm_v4f_mgt_for_v1_4_cal_inst2_sd_wr_wreg[14]) + ); + FDE plm_v4f_mgt_for_v1_4_cal_inst2_sd_wr_wreg_13_ ( + .CE(plm_v4f_mgt_for_v1_4_cal_inst2_N_1644_i), + .C(plm_v4f_mgt_cal_clk), + .D(plm_v4f_mgt_gt2_di[13]), + .Q(plm_v4f_mgt_for_v1_4_cal_inst2_sd_wr_wreg[13]) + ); + FD plm_v4f_mgt_for_v1_4_cal_inst2_sd_wr_wreg_12_ ( + .C(plm_v4f_mgt_cal_clk), + .D(plm_v4f_mgt_for_v1_4_cal_inst2_N_2464_i_870), + .Q(plm_v4f_mgt_for_v1_4_cal_inst2_sd_wr_wreg[12]) + ); + FDE plm_v4f_mgt_for_v1_4_cal_inst2_sd_wr_wreg_11_ ( + .CE(plm_v4f_mgt_for_v1_4_cal_inst2_N_1644_i), + .C(plm_v4f_mgt_cal_clk), + .D(plm_v4f_mgt_gt2_di[11]), + .Q(plm_v4f_mgt_for_v1_4_cal_inst2_sd_wr_wreg[11]) + ); + FDE plm_v4f_mgt_for_v1_4_cal_inst2_sd_wr_wreg_10_ ( + .CE(plm_v4f_mgt_for_v1_4_cal_inst2_N_1644_i), + .C(plm_v4f_mgt_cal_clk), + .D(plm_v4f_mgt_gt2_di[10]), + .Q(plm_v4f_mgt_for_v1_4_cal_inst2_sd_wr_wreg[10]) + ); + FDE plm_v4f_mgt_for_v1_4_cal_inst2_gt_do_r_15_ ( + .CE(plm_v4f_mgt_for_v1_4_cal_inst2_cb_state[2]), + .C(plm_v4f_mgt_cal_clk), + .D(plm_v4f_mgt_for_v1_4_cal_inst2_gt_do_r_4_i_m2_0_a2_0_a2_0_15_), + .Q(plm_v4f_mgt_gt2_do[15]) + ); + FDE plm_v4f_mgt_for_v1_4_cal_inst2_gt_do_r_14_ ( + .CE(plm_v4f_mgt_for_v1_4_cal_inst2_cb_state[2]), + .C(plm_v4f_mgt_cal_clk), + .D(plm_v4f_mgt_for_v1_4_cal_inst2_gt_do_r_4_i_m2_0_a2_0_a2_0_14_), + .Q(plm_v4f_mgt_gt2_do[14]) + ); + FDE plm_v4f_mgt_for_v1_4_cal_inst2_gt_do_r_13_ ( + .CE(plm_v4f_mgt_for_v1_4_cal_inst2_cb_state[2]), + .C(plm_v4f_mgt_cal_clk), + .D(plm_v4f_mgt_for_v1_4_cal_inst2_gt_do_r_4_i_m2_0_a2_0_a2_0_13_), + .Q(plm_v4f_mgt_gt2_do[13]) + ); + FDE plm_v4f_mgt_for_v1_4_cal_inst2_gt_do_r_12_ ( + .CE(plm_v4f_mgt_for_v1_4_cal_inst2_cb_state[2]), + .C(plm_v4f_mgt_cal_clk), + .D(plm_v4f_mgt_for_v1_4_cal_inst2_gt_do_r_4_i_m2_0_a2_0_a2_1_12_), + .Q(plm_v4f_mgt_gt2_do[12]) + ); + FDE plm_v4f_mgt_for_v1_4_cal_inst2_gt_do_r_11_ ( + .CE(plm_v4f_mgt_for_v1_4_cal_inst2_cb_state[2]), + .C(plm_v4f_mgt_cal_clk), + .D(plm_v4f_mgt_for_v1_4_cal_inst2_gt_do_r_4_i_m2_0_a2_0_a2_0_11_), + .Q(plm_v4f_mgt_gt2_do[11]) + ); + FDE plm_v4f_mgt_for_v1_4_cal_inst2_gt_do_r_10_ ( + .CE(plm_v4f_mgt_for_v1_4_cal_inst2_cb_state[2]), + .C(plm_v4f_mgt_cal_clk), + .D(plm_v4f_mgt_for_v1_4_cal_inst2_gt_do_r_4_i_m2_0_a2_0_a2_0_10_), + .Q(plm_v4f_mgt_gt2_do[10]) + ); + FDE plm_v4f_mgt_for_v1_4_cal_inst2_gt_do_r_9_ ( + .CE(plm_v4f_mgt_for_v1_4_cal_inst2_cb_state[2]), + .C(plm_v4f_mgt_cal_clk), + .D(plm_v4f_mgt_for_v1_4_cal_inst2_gt_do_r_4_i_m2_0_a2_0_a2_0_9_), + .Q(plm_v4f_mgt_gt2_do[9]) + ); + FDE plm_v4f_mgt_for_v1_4_cal_inst2_gt_do_r_8_ ( + .CE(plm_v4f_mgt_for_v1_4_cal_inst2_cb_state[2]), + .C(plm_v4f_mgt_cal_clk), + .D(plm_v4f_mgt_for_v1_4_cal_inst2_gt_do_r_4_i_m2_0_a2_0_a2_0_8_), + .Q(plm_v4f_mgt_gt2_do[8]) + ); + FDE plm_v4f_mgt_for_v1_4_cal_inst2_gt_do_r_7_ ( + .CE(plm_v4f_mgt_for_v1_4_cal_inst2_cb_state[2]), + .C(plm_v4f_mgt_cal_clk), + .D(plm_v4f_mgt_for_v1_4_cal_inst2_gt_do_r_4_i_m2_0_a2_0_a2_0_7_), + .Q(plm_v4f_mgt_gt2_do[7]) + ); + FDE plm_v4f_mgt_for_v1_4_cal_inst2_gt_do_r_6_ ( + .CE(plm_v4f_mgt_for_v1_4_cal_inst2_cb_state[2]), + .C(plm_v4f_mgt_cal_clk), + .D(plm_v4f_mgt_for_v1_4_cal_inst2_gt_do_r_4_i_m2_0_a2_0_a2_0_6_), + .Q(plm_v4f_mgt_gt2_do[6]) + ); + FDE plm_v4f_mgt_for_v1_4_cal_inst2_gt_do_r_5_ ( + .CE(plm_v4f_mgt_for_v1_4_cal_inst2_cb_state[2]), + .C(plm_v4f_mgt_cal_clk), + .D(plm_v4f_mgt_for_v1_4_cal_inst2_gt_do_r_4_i_m2_0_a2_0_a2_0_5_), + .Q(plm_v4f_mgt_gt2_do[5]) + ); + FDE plm_v4f_mgt_for_v1_4_cal_inst2_gt_do_r_4_ ( + .CE(plm_v4f_mgt_for_v1_4_cal_inst2_cb_state[2]), + .C(plm_v4f_mgt_cal_clk), + .D(plm_v4f_mgt_for_v1_4_cal_inst2_gt_do_r_4_i_m2_0_a2_0_a2_0_4_), + .Q(plm_v4f_mgt_gt2_do[4]) + ); + FDE plm_v4f_mgt_for_v1_4_cal_inst2_gt_do_r_3_ ( + .CE(plm_v4f_mgt_for_v1_4_cal_inst2_cb_state[2]), + .C(plm_v4f_mgt_cal_clk), + .D(plm_v4f_mgt_for_v1_4_cal_inst2_gt_do_r_4_i_m2_0_a2_0_a2_0_3_), + .Q(plm_v4f_mgt_gt2_do[3]) + ); + FDE plm_v4f_mgt_for_v1_4_cal_inst2_gt_do_r_2_ ( + .CE(plm_v4f_mgt_for_v1_4_cal_inst2_cb_state[2]), + .C(plm_v4f_mgt_cal_clk), + .D(plm_v4f_mgt_for_v1_4_cal_inst2_gt_do_r_4_i_m2_0_a2_0_a2_0_2_), + .Q(plm_v4f_mgt_gt2_do[2]) + ); + FDE plm_v4f_mgt_for_v1_4_cal_inst2_gt_do_r_1_ ( + .CE(plm_v4f_mgt_for_v1_4_cal_inst2_cb_state[2]), + .C(plm_v4f_mgt_cal_clk), + .D(plm_v4f_mgt_for_v1_4_cal_inst2_gt_do_r_4_i_m2_0_a2_0_a2_1_1_), + .Q(plm_v4f_mgt_gt2_do[1]) + ); + FDE plm_v4f_mgt_for_v1_4_cal_inst2_gt_do_r_0_ ( + .CE(plm_v4f_mgt_for_v1_4_cal_inst2_cb_state[2]), + .C(plm_v4f_mgt_cal_clk), + .D(plm_v4f_mgt_for_v1_4_cal_inst2_gt_do_r_4_i_m2_0_a2_0_a2_0_0_), + .Q(plm_v4f_mgt_gt2_do[0]) + ); + FDE plm_v4f_mgt_for_v1_4_cal_inst2_GT_DADDR_1_5_ ( + .CE(plm_v4f_mgt_for_v1_4_cal_inst2_cb_state[2]), + .C(plm_v4f_mgt_cal_clk), + .D(plm_v4f_mgt_for_v1_4_cal_inst2_N_1532_i), + .Q(plm_v4f_mgt_gt2_daddr[5]) + ); + FDE plm_v4f_mgt_for_v1_4_cal_inst2_GT_DADDR_1_3_ ( + .CE(plm_v4f_mgt_for_v1_4_cal_inst2_cb_state[2]), + .C(plm_v4f_mgt_cal_clk), + .D(plm_v4f_mgt_for_v1_4_cal_inst2_VCC_871), + .Q(plm_v4f_mgt_gt2_daddr[3]) + ); + FDE plm_v4f_mgt_for_v1_4_cal_inst2_GT_DADDR_1_2_ ( + .CE(plm_v4f_mgt_for_v1_4_cal_inst2_cb_state[2]), + .C(plm_v4f_mgt_cal_clk), + .D(plm_v4f_mgt_for_v1_4_cal_inst2_N_1743_i_872), + .Q(plm_v4f_mgt_gt2_daddr[2]) + ); + FDE plm_v4f_mgt_for_v1_4_cal_inst2_GT_DADDR_1_1_ ( + .CE(plm_v4f_mgt_for_v1_4_cal_inst2_cb_state[2]), + .C(plm_v4f_mgt_cal_clk), + .D(plm_v4f_mgt_for_v1_4_cal_inst2_GT_DADDR_5_i_i_a2_0_a2_1[1]), + .Q(plm_v4f_mgt_gt2_daddr[1]) + ); + FDE plm_v4f_mgt_for_v1_4_cal_inst2_GT_DADDR_1_0_ ( + .CE(plm_v4f_mgt_for_v1_4_cal_inst2_cb_state[2]), + .C(plm_v4f_mgt_cal_clk), + .D(plm_v4f_mgt_for_v1_4_cal_inst2_N_1664_i_i_873), + .Q(plm_v4f_mgt_gt2_daddr[4]) + ); + INV plm_v4f_mgt_for_v1_4_cal_inst2_cb_state_i_2_ ( + .I(plm_v4f_mgt_for_v1_4_cal_inst2_cb_state[2]), + .O(plm_v4f_mgt_for_v1_4_cal_inst2_cb_state_i[2]) + ); + VCC plm_v4f_mgt_for_v1_4_cal_inst3_VCC ( + .P(plm_v4f_mgt_for_v1_4_cal_inst3_VCC_914) + ); + FDS plm_v4f_mgt_for_v1_4_cal_inst3_drp_state_0_ ( + .C(plm_v4f_mgt_cal_clk), + .D(plm_v4f_mgt_for_v1_4_cal_inst3_N_2470_i_894), + .Q(plm_v4f_mgt_for_v1_4_cal_inst3_drp_state_0__896), + .S(plm_v4f_mgt_for_v1_4_cal_inst0_reset_r[0]) + ); + FDR plm_v4f_mgt_for_v1_4_cal_inst3_drp_state_1_ ( + .C(plm_v4f_mgt_cal_clk), + .D(plm_v4f_mgt_for_v1_4_cal_inst3_N_1379_i), + .Q(plm_v4f_mgt_for_v1_4_cal_inst3_drp_state_1__891), + .R(plm_v4f_mgt_for_v1_4_cal_inst0_reset_r[0]) + ); + FDR plm_v4f_mgt_for_v1_4_cal_inst3_drp_state_2_ ( + .C(plm_v4f_mgt_cal_clk), + .D(plm_v4f_mgt_for_v1_4_cal_inst3_drp_next_state_0_sqmuxa_1), + .Q(plm_v4f_mgt_gt3_dwe), + .R(plm_v4f_mgt_for_v1_4_cal_inst0_reset_r[0]) + ); + FDR plm_v4f_mgt_for_v1_4_cal_inst3_drp_state_3_ ( + .C(plm_v4f_mgt_cal_clk), + .D(plm_v4f_mgt_for_v1_4_cal_inst3_N_2396_i_889), + .Q(plm_v4f_mgt_for_v1_4_cal_inst3_drp_state_3__890), + .R(plm_v4f_mgt_for_v1_4_cal_inst0_reset_r[0]) + ); + FDR plm_v4f_mgt_for_v1_4_cal_inst3_drp_state_4_ ( + .C(plm_v4f_mgt_cal_clk), + .D(plm_v4f_mgt_for_v1_4_cal_inst3_drp_next_state_0_sqmuxa), + .Q(plm_v4f_mgt_for_v1_4_cal_inst3_drp_state_4__895), + .R(plm_v4f_mgt_for_v1_4_cal_inst0_reset_r[0]) + ); + FDS plm_v4f_mgt_for_v1_4_cal_inst3_sd_state_0_ ( + .C(plm_v4f_mgt_cal_clk), + .D(plm_v4f_mgt_for_v1_4_cal_inst3_N_2468_i_887), + .Q(plm_v4f_mgt_for_v1_4_cal_inst3_sd_state[0]), + .S(plm_v4f_mgt_for_v1_4_cal_inst0_reset_r[0]) + ); + FDR plm_v4f_mgt_for_v1_4_cal_inst3_sd_state_1_ ( + .C(plm_v4f_mgt_cal_clk), + .D(plm_v4f_mgt_for_v1_4_cal_inst3_N_2471_i_886), + .Q(plm_v4f_mgt_for_v1_4_cal_inst3_sd_state[1]), + .R(plm_v4f_mgt_for_v1_4_cal_inst0_reset_r[0]) + ); + FDR plm_v4f_mgt_for_v1_4_cal_inst3_sd_state_2_ ( + .C(plm_v4f_mgt_cal_clk), + .D(plm_v4f_mgt_for_v1_4_cal_inst3_sd_next_state_0_sqmuxa), + .Q(plm_v4f_mgt_for_v1_4_cal_inst3_sd_state[2]), + .R(plm_v4f_mgt_for_v1_4_cal_inst0_reset_r[0]) + ); + FDR plm_v4f_mgt_for_v1_4_cal_inst3_sd_state_3_ ( + .C(plm_v4f_mgt_cal_clk), + .D(plm_v4f_mgt_for_v1_4_cal_inst3_N_1673_i_885), + .Q(plm_v4f_mgt_for_v1_4_cal_inst3_sd_state[3]), + .R(plm_v4f_mgt_for_v1_4_cal_inst0_reset_r[0]) + ); + FDR plm_v4f_mgt_for_v1_4_cal_inst3_sd_state_5_ ( + .C(plm_v4f_mgt_cal_clk), + .D(plm_v4f_mgt_for_v1_4_cal_inst3_sd_next_state_0_sqmuxa_1), + .Q(plm_v4f_mgt_for_v1_4_cal_inst3_sd_state[5]), + .R(plm_v4f_mgt_for_v1_4_cal_inst0_reset_r[0]) + ); + FDR plm_v4f_mgt_for_v1_4_cal_inst3_sd_state_6_ ( + .C(plm_v4f_mgt_cal_clk), + .D(plm_v4f_mgt_for_v1_4_cal_inst3_N_1672_i_884), + .Q(plm_v4f_mgt_for_v1_4_cal_inst3_sd_state[6]), + .R(plm_v4f_mgt_for_v1_4_cal_inst0_reset_r[0]) + ); + FDR plm_v4f_mgt_for_v1_4_cal_inst3_sd_state_7_ ( + .C(plm_v4f_mgt_cal_clk), + .D(plm_v4f_mgt_for_v1_4_cal_inst3_N_2466_i_883), + .Q(plm_v4f_mgt_for_v1_4_cal_inst3_sd_state[7]), + .R(plm_v4f_mgt_for_v1_4_cal_inst0_reset_r[0]) + ); + FDR plm_v4f_mgt_for_v1_4_cal_inst3_sd_state_8_ ( + .C(plm_v4f_mgt_cal_clk), + .D(plm_v4f_mgt_for_v1_4_cal_inst3_N_2467_i_882), + .Q(plm_v4f_mgt_for_v1_4_cal_inst3_sd_state[8]), + .R(plm_v4f_mgt_for_v1_4_cal_inst0_reset_r[0]) + ); + FDR plm_v4f_mgt_for_v1_4_cal_inst3_sd_state_9_ ( + .C(plm_v4f_mgt_cal_clk), + .D(plm_v4f_mgt_for_v1_4_cal_inst3_sd_next_state_0_sqmuxa_2), + .Q(plm_v4f_mgt_for_v1_4_cal_inst3_sd_state[9]), + .R(plm_v4f_mgt_for_v1_4_cal_inst0_reset_r[0]) + ); + FDR plm_v4f_mgt_for_v1_4_cal_inst3_sd_state_10_ ( + .C(plm_v4f_mgt_cal_clk), + .D(plm_v4f_mgt_for_v1_4_cal_inst3_N_1670_i_881), + .Q(plm_v4f_mgt_for_v1_4_cal_inst3_sd_state[10]), + .R(plm_v4f_mgt_for_v1_4_cal_inst0_reset_r[0]) + ); + FDR plm_v4f_mgt_for_v1_4_cal_inst3_sd_state_12_ ( + .C(plm_v4f_mgt_cal_clk), + .D(plm_v4f_mgt_for_v1_4_cal_inst3_sd_next_state_0_sqmuxa_3), + .Q(plm_v4f_mgt_for_v1_4_cal_inst3_sd_state[12]), + .R(plm_v4f_mgt_for_v1_4_cal_inst0_reset_r[0]) + ); + FDR plm_v4f_mgt_for_v1_4_cal_inst3_sd_state_13_ ( + .C(plm_v4f_mgt_cal_clk), + .D(plm_v4f_mgt_for_v1_4_cal_inst3_N_2465_i_880), + .Q(plm_v4f_mgt_for_v1_4_cal_inst3_sd_state[13]), + .R(plm_v4f_mgt_for_v1_4_cal_inst0_reset_r[0]) + ); + FDR plm_v4f_mgt_for_v1_4_cal_inst3_GT_DEN ( + .C(plm_v4f_mgt_cal_clk), + .D(plm_v4f_mgt_for_v1_4_cal_inst3_N_1381_i), + .Q(plm_v4f_mgt_gt3_den), + .R(plm_v4f_mgt_for_v1_4_cal_inst0_reset_r[0]) + ); + FDR plm_v4f_mgt_for_v1_4_cal_inst3_sd_write ( + .C(plm_v4f_mgt_cal_clk), + .D(plm_v4f_mgt_for_v1_4_cal_inst3_N_1728_i_879), + .Q(plm_v4f_mgt_for_v1_4_cal_inst3_sd_write_892), + .R(plm_v4f_mgt_for_v1_4_cal_inst3_N_1730_i_874) + ); + FDR plm_v4f_mgt_for_v1_4_cal_inst3_sd_read ( + .C(plm_v4f_mgt_cal_clk), + .D(plm_v4f_mgt_for_v1_4_cal_inst3_N_1729_i_878), + .Q(plm_v4f_mgt_for_v1_4_cal_inst3_sd_read_893), + .R(plm_v4f_mgt_for_v1_4_cal_inst3_N_1730_i_874) + ); + FDR plm_v4f_mgt_for_v1_4_cal_inst3_sd_req ( + .C(plm_v4f_mgt_cal_clk), + .D(plm_v4f_mgt_for_v1_4_cal_inst3_N_1798_i_877), + .Q(plm_v4f_mgt_for_v1_4_cal_inst3_sd_req_875), + .R(plm_v4f_mgt_for_v1_4_cal_inst3_N_1730_i_874) + ); + FDRE plm_v4f_mgt_for_v1_4_cal_inst3_sd_state_11_ ( + .CE(plm_v4f_mgt_for_v1_4_cal_inst3_sd_drp_done_888), + .C(plm_v4f_mgt_cal_clk), + .D(plm_v4f_mgt_for_v1_4_cal_inst3_sd_state[10]), + .Q(plm_v4f_mgt_for_v1_4_cal_inst3_sd_state[11]), + .R(plm_v4f_mgt_for_v1_4_cal_inst0_reset_r[0]) + ); + FDRE plm_v4f_mgt_for_v1_4_cal_inst3_sd_state_4_ ( + .CE(plm_v4f_mgt_for_v1_4_cal_inst3_sd_drp_done_888), + .C(plm_v4f_mgt_cal_clk), + .D(plm_v4f_mgt_for_v1_4_cal_inst3_sd_state[3]), + .Q(plm_v4f_mgt_for_v1_4_cal_inst3_sd_state[4]), + .R(plm_v4f_mgt_for_v1_4_cal_inst0_reset_r[0]) + ); + FDR plm_v4f_mgt_for_v1_4_cal_inst3_cb_state_2_ ( + .C(plm_v4f_mgt_cal_clk), + .D(plm_v4f_mgt_for_v1_4_cal_inst3_cb_statec_i_i_876), + .Q(plm_v4f_mgt_for_v1_4_cal_inst3_cb_state[2]), + .R(plm_v4f_mgt_for_v1_4_cal_inst0_reset_r[0]) + ); + FDR plm_v4f_mgt_for_v1_4_cal_inst3_cb_state_1_ ( + .C(plm_v4f_mgt_cal_clk), + .D(plm_v4f_mgt_for_v1_4_cal_inst3_cb_statec_i), + .Q(plm_v4f_mgt_for_v1_4_cal_inst3_cb_state[1]), + .R(plm_v4f_mgt_for_v1_4_cal_inst0_reset_r[0]) + ); + FDR plm_v4f_mgt_for_v1_4_cal_inst3_sd_drp_done ( + .C(plm_v4f_mgt_cal_clk), + .D(plm_v4f_mgt_gt3_drdy), + .Q(plm_v4f_mgt_for_v1_4_cal_inst3_sd_drp_done_888), + .R(plm_v4f_mgt_for_v1_4_cal_inst3_cb_state_i[2]) + ); + defparam plm_v4f_mgt_for_v1_4_cal_inst3_sd_req_3_0_a2_0_a2.INIT = 4'h1; + LUT2 plm_v4f_mgt_for_v1_4_cal_inst3_sd_req_3_0_a2_0_a2 ( + .I0(plm_v4f_mgt_for_v1_4_cal_inst3_sd_read_893), + .I1(plm_v4f_mgt_for_v1_4_cal_inst3_sd_write_892), + .O(plm_v4f_mgt_for_v1_4_cal_inst3_sd_req_3_0_a2_0_a2_2) + ); + defparam plm_v4f_mgt_for_v1_4_cal_inst3_sd_wr_wreg_9_0_0_a2_0_0_12_.INIT = 4'h4; + LUT2 plm_v4f_mgt_for_v1_4_cal_inst3_sd_wr_wreg_9_0_0_a2_0_0_12_ ( + .I0(plm_v4f_mgt_for_v1_4_cal_inst3_sd_state[12]), + .I1(plm_v4f_mgt_for_v1_4_cal_inst3_sd_wr_wreg[12]), + .O(plm_v4f_mgt_for_v1_4_cal_inst3_sd_wr_wreg_9_0_0_a2_0[12]) + ); + defparam plm_v4f_mgt_for_v1_4_cal_inst3_N_1730_i.INIT = 4'hE; + LUT2 plm_v4f_mgt_for_v1_4_cal_inst3_N_1730_i ( + .I0(plm_v4f_mgt_for_v1_4_cal_inst3_sd_drp_done_888), + .I1(plm_v4f_mgt_for_v1_4_cal_inst3_sd_state[0]), + .O(plm_v4f_mgt_for_v1_4_cal_inst3_N_1730_i_874) + ); + defparam plm_v4f_mgt_for_v1_4_cal_inst3_cb_state_4_i_a2_2_.INIT = 16'h51F3; + LUT4 plm_v4f_mgt_for_v1_4_cal_inst3_cb_state_4_i_a2_2_ ( + .I0(plm_v4f_mgt_for_v1_4_cal_inst3_cb_state[1]), + .I1(plm_v4f_mgt_for_v1_4_cal_inst3_cb_state[2]), + .I2(plm_v4f_mgt_for_v1_4_cal_inst3_gt_drdy_r_897), + .I3(plm_v4f_mgt_for_v1_4_cal_inst3_sd_req_875), + .O(plm_v4f_mgt_for_v1_4_cal_inst3_cb_statec_i) + ); + defparam plm_v4f_mgt_for_v1_4_cal_inst3_sd_wr_wreg_9_0_0_o2_12_.INIT = 8'h80; + LUT3 plm_v4f_mgt_for_v1_4_cal_inst3_sd_wr_wreg_9_0_0_o2_12_ ( + .I0(plm_v4f_mgt_for_v1_4_cal_inst3_cb_state[2]), + .I1(plm_v4f_mgt_for_v1_4_cal_inst3_sd_read_893), + .I2(plm_v4f_mgt_gt3_drdy), + .O(plm_v4f_mgt_for_v1_4_cal_inst3_N_1645_i) + ); + defparam plm_v4f_mgt_for_v1_4_cal_inst3_GT_DADDR_5_i_0_0_o2_2_.INIT = 16'h0001; + LUT4 plm_v4f_mgt_for_v1_4_cal_inst3_GT_DADDR_5_i_0_0_o2_2_ ( + .I0(plm_v4f_mgt_for_v1_4_cal_inst3_sd_state[4]), + .I1(plm_v4f_mgt_for_v1_4_cal_inst3_sd_state[6]), + .I2(plm_v4f_mgt_for_v1_4_cal_inst3_sd_state[8]), + .I3(plm_v4f_mgt_for_v1_4_cal_inst3_sd_state[10]), + .O(plm_v4f_mgt_for_v1_4_cal_inst3_N_1665_i) + ); + defparam plm_v4f_mgt_for_v1_4_cal_inst3_sd_wr_wreg_9_i_i_m2_1_.INIT = 8'h1B; + LUT3_L plm_v4f_mgt_for_v1_4_cal_inst3_sd_wr_wreg_9_i_i_m2_1_ ( + .I0(plm_v4f_mgt_for_v1_4_cal_inst3_N_1645_i), + .I1(plm_v4f_mgt_for_v1_4_cal_inst3_sd_state[5]), + .I2(plm_v4f_mgt_gt3_di[1]), + .LO(plm_v4f_mgt_for_v1_4_cal_inst3_sd_wr_wreg_9_i_i_m2_1[1]) + ); + defparam plm_v4f_mgt_for_v1_4_cal_inst3_cb_statec_i_i.INIT = 4'h1; + LUT1_L plm_v4f_mgt_for_v1_4_cal_inst3_cb_statec_i_i ( + .I0(plm_v4f_mgt_for_v1_4_cal_inst3_cb_statec_i), + .LO(plm_v4f_mgt_for_v1_4_cal_inst3_cb_statec_i_i_876) + ); + defparam plm_v4f_mgt_for_v1_4_cal_inst3_N_2469_i.INIT = 16'h3733; + LUT4_L plm_v4f_mgt_for_v1_4_cal_inst3_N_2469_i ( + .I0(plm_v4f_mgt_for_v1_4_cal_inst3_N_1645_i), + .I1(plm_v4f_mgt_for_v1_4_cal_inst3_sd_wr_wreg_9_i_i_m2_1[1]), + .I2(plm_v4f_mgt_for_v1_4_cal_inst3_sd_state[9]), + .I3(plm_v4f_mgt_for_v1_4_cal_inst3_sd_wr_wreg[1]), + .LO(plm_v4f_mgt_for_v1_4_cal_inst3_N_2469_i_898) + ); + defparam plm_v4f_mgt_for_v1_4_cal_inst3_N_2472_i.INIT = 16'hBA10; + LUT4_L plm_v4f_mgt_for_v1_4_cal_inst3_N_2472_i ( + .I0(plm_v4f_mgt_for_v1_4_cal_inst3_N_1645_i), + .I1(plm_v4f_mgt_for_v1_4_cal_inst3_sd_state[2]), + .I2(plm_v4f_mgt_for_v1_4_cal_inst3_sd_wr_wreg_9_0_0_a2_0[12]), + .I3(plm_v4f_mgt_gt3_di[12]), + .LO(plm_v4f_mgt_for_v1_4_cal_inst3_N_2472_i_899) + ); + defparam plm_v4f_mgt_for_v1_4_cal_inst3_gt_do_r_4_i_m2_0_a2_0_a2_15_.INIT = 4'h8; + LUT2_L plm_v4f_mgt_for_v1_4_cal_inst3_gt_do_r_4_i_m2_0_a2_0_a2_15_ ( + .I0(plm_v4f_mgt_for_v1_4_cal_inst3_cb_state[2]), + .I1(plm_v4f_mgt_for_v1_4_cal_inst3_sd_wr_wreg[15]), + .LO(plm_v4f_mgt_for_v1_4_cal_inst3_gt_do_r_4_i_m2_0_a2_0_a2_15__900) + ); + defparam plm_v4f_mgt_for_v1_4_cal_inst3_gt_do_r_4_i_m2_0_a2_0_a2_14_.INIT = 4'h8; + LUT2_L plm_v4f_mgt_for_v1_4_cal_inst3_gt_do_r_4_i_m2_0_a2_0_a2_14_ ( + .I0(plm_v4f_mgt_for_v1_4_cal_inst3_cb_state[2]), + .I1(plm_v4f_mgt_for_v1_4_cal_inst3_sd_wr_wreg[14]), + .LO(plm_v4f_mgt_for_v1_4_cal_inst3_gt_do_r_4_i_m2_0_a2_0_a2_14__901) + ); + defparam plm_v4f_mgt_for_v1_4_cal_inst3_gt_do_r_4_i_m2_0_a2_0_a2_13_.INIT = 4'h8; + LUT2_L plm_v4f_mgt_for_v1_4_cal_inst3_gt_do_r_4_i_m2_0_a2_0_a2_13_ ( + .I0(plm_v4f_mgt_for_v1_4_cal_inst3_cb_state[2]), + .I1(plm_v4f_mgt_for_v1_4_cal_inst3_sd_wr_wreg[13]), + .LO(plm_v4f_mgt_for_v1_4_cal_inst3_gt_do_r_4_i_m2_0_a2_0_a2_13__902) + ); + defparam plm_v4f_mgt_for_v1_4_cal_inst3_gt_do_r_4_i_m2_0_a2_0_a2_12_.INIT = 4'h8; + LUT2_L plm_v4f_mgt_for_v1_4_cal_inst3_gt_do_r_4_i_m2_0_a2_0_a2_12_ ( + .I0(plm_v4f_mgt_for_v1_4_cal_inst3_cb_state[2]), + .I1(plm_v4f_mgt_for_v1_4_cal_inst3_sd_wr_wreg[12]), + .LO(plm_v4f_mgt_for_v1_4_cal_inst3_gt_do_r_4_i_m2_0_a2_0_a2_2_12_) + ); + defparam plm_v4f_mgt_for_v1_4_cal_inst3_gt_do_r_4_i_m2_0_a2_0_a2_11_.INIT = 4'h8; + LUT2_L plm_v4f_mgt_for_v1_4_cal_inst3_gt_do_r_4_i_m2_0_a2_0_a2_11_ ( + .I0(plm_v4f_mgt_for_v1_4_cal_inst3_cb_state[2]), + .I1(plm_v4f_mgt_for_v1_4_cal_inst3_sd_wr_wreg[11]), + .LO(plm_v4f_mgt_for_v1_4_cal_inst3_gt_do_r_4_i_m2_0_a2_0_a2_11__903) + ); + defparam plm_v4f_mgt_for_v1_4_cal_inst3_gt_do_r_4_i_m2_0_a2_0_a2_10_.INIT = 4'h8; + LUT2_L plm_v4f_mgt_for_v1_4_cal_inst3_gt_do_r_4_i_m2_0_a2_0_a2_10_ ( + .I0(plm_v4f_mgt_for_v1_4_cal_inst3_cb_state[2]), + .I1(plm_v4f_mgt_for_v1_4_cal_inst3_sd_wr_wreg[10]), + .LO(plm_v4f_mgt_for_v1_4_cal_inst3_gt_do_r_4_i_m2_0_a2_0_a2_10__904) + ); + defparam plm_v4f_mgt_for_v1_4_cal_inst3_gt_do_r_4_i_m2_0_a2_0_a2_9_.INIT = 4'h8; + LUT2_L plm_v4f_mgt_for_v1_4_cal_inst3_gt_do_r_4_i_m2_0_a2_0_a2_9_ ( + .I0(plm_v4f_mgt_for_v1_4_cal_inst3_cb_state[2]), + .I1(plm_v4f_mgt_for_v1_4_cal_inst3_sd_wr_wreg[9]), + .LO(plm_v4f_mgt_for_v1_4_cal_inst3_gt_do_r_4_i_m2_0_a2_0_a2_9__905) + ); + defparam plm_v4f_mgt_for_v1_4_cal_inst3_gt_do_r_4_i_m2_0_a2_0_a2_8_.INIT = 4'h8; + LUT2_L plm_v4f_mgt_for_v1_4_cal_inst3_gt_do_r_4_i_m2_0_a2_0_a2_8_ ( + .I0(plm_v4f_mgt_for_v1_4_cal_inst3_cb_state[2]), + .I1(plm_v4f_mgt_for_v1_4_cal_inst3_sd_wr_wreg[8]), + .LO(plm_v4f_mgt_for_v1_4_cal_inst3_gt_do_r_4_i_m2_0_a2_0_a2_8__906) + ); + defparam plm_v4f_mgt_for_v1_4_cal_inst3_gt_do_r_4_i_m2_0_a2_0_a2_7_.INIT = 4'h8; + LUT2_L plm_v4f_mgt_for_v1_4_cal_inst3_gt_do_r_4_i_m2_0_a2_0_a2_7_ ( + .I0(plm_v4f_mgt_for_v1_4_cal_inst3_cb_state[2]), + .I1(plm_v4f_mgt_for_v1_4_cal_inst3_sd_wr_wreg[7]), + .LO(plm_v4f_mgt_for_v1_4_cal_inst3_gt_do_r_4_i_m2_0_a2_0_a2_7__907) + ); + defparam plm_v4f_mgt_for_v1_4_cal_inst3_gt_do_r_4_i_m2_0_a2_0_a2_6_.INIT = 4'h8; + LUT2_L plm_v4f_mgt_for_v1_4_cal_inst3_gt_do_r_4_i_m2_0_a2_0_a2_6_ ( + .I0(plm_v4f_mgt_for_v1_4_cal_inst3_cb_state[2]), + .I1(plm_v4f_mgt_for_v1_4_cal_inst3_sd_wr_wreg[6]), + .LO(plm_v4f_mgt_for_v1_4_cal_inst3_gt_do_r_4_i_m2_0_a2_0_a2_6__908) + ); + defparam plm_v4f_mgt_for_v1_4_cal_inst3_gt_do_r_4_i_m2_0_a2_0_a2_5_.INIT = 4'h8; + LUT2_L plm_v4f_mgt_for_v1_4_cal_inst3_gt_do_r_4_i_m2_0_a2_0_a2_5_ ( + .I0(plm_v4f_mgt_for_v1_4_cal_inst3_cb_state[2]), + .I1(plm_v4f_mgt_for_v1_4_cal_inst3_sd_wr_wreg[5]), + .LO(plm_v4f_mgt_for_v1_4_cal_inst3_gt_do_r_4_i_m2_0_a2_0_a2_5__909) + ); + defparam plm_v4f_mgt_for_v1_4_cal_inst3_gt_do_r_4_i_m2_0_a2_0_a2_4_.INIT = 4'h8; + LUT2_L plm_v4f_mgt_for_v1_4_cal_inst3_gt_do_r_4_i_m2_0_a2_0_a2_4_ ( + .I0(plm_v4f_mgt_for_v1_4_cal_inst3_cb_state[2]), + .I1(plm_v4f_mgt_for_v1_4_cal_inst3_sd_wr_wreg[4]), + .LO(plm_v4f_mgt_for_v1_4_cal_inst3_gt_do_r_4_i_m2_0_a2_0_a2_4__910) + ); + defparam plm_v4f_mgt_for_v1_4_cal_inst3_gt_do_r_4_i_m2_0_a2_0_a2_3_.INIT = 4'h8; + LUT2_L plm_v4f_mgt_for_v1_4_cal_inst3_gt_do_r_4_i_m2_0_a2_0_a2_3_ ( + .I0(plm_v4f_mgt_for_v1_4_cal_inst3_cb_state[2]), + .I1(plm_v4f_mgt_for_v1_4_cal_inst3_sd_wr_wreg[3]), + .LO(plm_v4f_mgt_for_v1_4_cal_inst3_gt_do_r_4_i_m2_0_a2_0_a2_3__911) + ); + defparam plm_v4f_mgt_for_v1_4_cal_inst3_gt_do_r_4_i_m2_0_a2_0_a2_2_.INIT = 4'h8; + LUT2_L plm_v4f_mgt_for_v1_4_cal_inst3_gt_do_r_4_i_m2_0_a2_0_a2_2_ ( + .I0(plm_v4f_mgt_for_v1_4_cal_inst3_cb_state[2]), + .I1(plm_v4f_mgt_for_v1_4_cal_inst3_sd_wr_wreg[2]), + .LO(plm_v4f_mgt_for_v1_4_cal_inst3_gt_do_r_4_i_m2_0_a2_0_a2_2__912) + ); + defparam plm_v4f_mgt_for_v1_4_cal_inst3_gt_do_r_4_i_m2_0_a2_0_a2_1_.INIT = 4'h8; + LUT2_L plm_v4f_mgt_for_v1_4_cal_inst3_gt_do_r_4_i_m2_0_a2_0_a2_1_ ( + .I0(plm_v4f_mgt_for_v1_4_cal_inst3_cb_state[2]), + .I1(plm_v4f_mgt_for_v1_4_cal_inst3_sd_wr_wreg[1]), + .LO(plm_v4f_mgt_for_v1_4_cal_inst3_gt_do_r_4_i_m2_0_a2_0_a2_2_1_) + ); + defparam plm_v4f_mgt_for_v1_4_cal_inst3_gt_do_r_4_i_m2_0_a2_0_a2_0_.INIT = 4'h8; + LUT2_L plm_v4f_mgt_for_v1_4_cal_inst3_gt_do_r_4_i_m2_0_a2_0_a2_0_ ( + .I0(plm_v4f_mgt_for_v1_4_cal_inst3_cb_state[2]), + .I1(plm_v4f_mgt_for_v1_4_cal_inst3_sd_wr_wreg[0]), + .LO(plm_v4f_mgt_for_v1_4_cal_inst3_gt_do_r_4_i_m2_0_a2_0_a2_0__913) + ); + defparam plm_v4f_mgt_for_v1_4_cal_inst3_N_1798_i.INIT = 4'h1; + LUT1_L plm_v4f_mgt_for_v1_4_cal_inst3_N_1798_i ( + .I0(plm_v4f_mgt_for_v1_4_cal_inst3_sd_req_3_0_a2_0_a2_2), + .LO(plm_v4f_mgt_for_v1_4_cal_inst3_N_1798_i_877) + ); + defparam plm_v4f_mgt_for_v1_4_cal_inst3_N_1729_i.INIT = 16'hFFFE; + LUT4_L plm_v4f_mgt_for_v1_4_cal_inst3_N_1729_i ( + .I0(plm_v4f_mgt_for_v1_4_cal_inst3_sd_state[1]), + .I1(plm_v4f_mgt_for_v1_4_cal_inst3_sd_state[4]), + .I2(plm_v4f_mgt_for_v1_4_cal_inst3_sd_state[8]), + .I3(plm_v4f_mgt_for_v1_4_cal_inst3_sd_state[11]), + .LO(plm_v4f_mgt_for_v1_4_cal_inst3_N_1729_i_878) + ); + defparam plm_v4f_mgt_for_v1_4_cal_inst3_N_1728_i.INIT = 16'hFFFE; + LUT4_L plm_v4f_mgt_for_v1_4_cal_inst3_N_1728_i ( + .I0(plm_v4f_mgt_for_v1_4_cal_inst3_sd_state[3]), + .I1(plm_v4f_mgt_for_v1_4_cal_inst3_sd_state[6]), + .I2(plm_v4f_mgt_for_v1_4_cal_inst3_sd_state[10]), + .I3(plm_v4f_mgt_for_v1_4_cal_inst3_sd_state[13]), + .LO(plm_v4f_mgt_for_v1_4_cal_inst3_N_1728_i_879) + ); + defparam plm_v4f_mgt_for_v1_4_cal_inst3_GT_DEN_3_i.INIT = 8'h40; + LUT3_L plm_v4f_mgt_for_v1_4_cal_inst3_GT_DEN_3_i ( + .I0(plm_v4f_mgt_for_v1_4_cal_inst3_sd_req_3_0_a2_0_a2_2), + .I1(plm_v4f_mgt_for_v1_4_cal_inst3_cb_state[2]), + .I2(plm_v4f_mgt_for_v1_4_cal_inst3_drp_state_0__896), + .LO(plm_v4f_mgt_for_v1_4_cal_inst3_N_1381_i) + ); + defparam plm_v4f_mgt_for_v1_4_cal_inst3_GT_DADDR_5_i_i_a2_i_5_.INIT = 4'h4; + LUT2_L plm_v4f_mgt_for_v1_4_cal_inst3_GT_DADDR_5_i_i_a2_i_5_ ( + .I0(plm_v4f_mgt_for_v1_4_cal_inst3_N_1665_i), + .I1(cfg_cfg_6102[509]), + .LO(plm_v4f_mgt_for_v1_4_cal_inst3_N_1524_i) + ); + defparam plm_v4f_mgt_for_v1_4_cal_inst3_N_1718_i.INIT = 4'hE; + LUT2_L plm_v4f_mgt_for_v1_4_cal_inst3_N_1718_i ( + .I0(plm_v4f_mgt_for_v1_4_cal_inst3_N_1665_i), + .I1(cfg_cfg_6102[509]), + .LO(plm_v4f_mgt_for_v1_4_cal_inst3_N_1718_i_915) + ); + defparam plm_v4f_mgt_for_v1_4_cal_inst3_GT_DADDR_5_i_i_a2_0_a2_1_.INIT = 4'h2; + LUT2_L plm_v4f_mgt_for_v1_4_cal_inst3_GT_DADDR_5_i_i_a2_0_a2_1_ ( + .I0(plm_v4f_mgt_for_v1_4_cal_inst3_N_1665_i), + .I1(cfg_cfg_6102[509]), + .LO(plm_v4f_mgt_for_v1_4_cal_inst3_GT_DADDR_5_i_i_a2_0_a2_2[1]) + ); + defparam plm_v4f_mgt_for_v1_4_cal_inst3_N_1665_i_i.INIT = 4'h1; + LUT1_L plm_v4f_mgt_for_v1_4_cal_inst3_N_1665_i_i ( + .I0(plm_v4f_mgt_for_v1_4_cal_inst3_N_1665_i), + .LO(plm_v4f_mgt_for_v1_4_cal_inst3_N_1665_i_i_916) + ); + defparam plm_v4f_mgt_for_v1_4_cal_inst3_N_2465_i.INIT = 8'hDC; + LUT3_L plm_v4f_mgt_for_v1_4_cal_inst3_N_2465_i ( + .I0(plm_v4f_mgt_for_v1_4_cal_inst3_sd_drp_done_888), + .I1(plm_v4f_mgt_for_v1_4_cal_inst3_sd_state[12]), + .I2(plm_v4f_mgt_for_v1_4_cal_inst3_sd_state[13]), + .LO(plm_v4f_mgt_for_v1_4_cal_inst3_N_2465_i_880) + ); + defparam plm_v4f_mgt_for_v1_4_cal_inst3_sd_next_state_0_sqmuxa_3_0_a2_0_a2.INIT = 4'h8; + LUT2_L plm_v4f_mgt_for_v1_4_cal_inst3_sd_next_state_0_sqmuxa_3_0_a2_0_a2 ( + .I0(plm_v4f_mgt_for_v1_4_cal_inst3_sd_drp_done_888), + .I1(plm_v4f_mgt_for_v1_4_cal_inst3_sd_state[11]), + .LO(plm_v4f_mgt_for_v1_4_cal_inst3_sd_next_state_0_sqmuxa_3) + ); + defparam plm_v4f_mgt_for_v1_4_cal_inst3_N_1670_i.INIT = 8'h5C; + LUT3_L plm_v4f_mgt_for_v1_4_cal_inst3_N_1670_i ( + .I0(plm_v4f_mgt_for_v1_4_cal_inst3_sd_drp_done_888), + .I1(plm_v4f_mgt_for_v1_4_cal_inst3_sd_state[9]), + .I2(plm_v4f_mgt_for_v1_4_cal_inst3_sd_state[10]), + .LO(plm_v4f_mgt_for_v1_4_cal_inst3_N_1670_i_881) + ); + defparam plm_v4f_mgt_for_v1_4_cal_inst3_sd_next_state_0_sqmuxa_2_0_a2_0_a2.INIT = 4'h8; + LUT2_L plm_v4f_mgt_for_v1_4_cal_inst3_sd_next_state_0_sqmuxa_2_0_a2_0_a2 ( + .I0(plm_v4f_mgt_for_v1_4_cal_inst3_sd_drp_done_888), + .I1(plm_v4f_mgt_for_v1_4_cal_inst3_sd_state[8]), + .LO(plm_v4f_mgt_for_v1_4_cal_inst3_sd_next_state_0_sqmuxa_2) + ); + defparam plm_v4f_mgt_for_v1_4_cal_inst3_N_2467_i.INIT = 16'hB3A0; + LUT4_L plm_v4f_mgt_for_v1_4_cal_inst3_N_2467_i ( + .I0(cmmp_negotiated_width_0[0]), + .I1(plm_v4f_mgt_for_v1_4_cal_inst3_sd_drp_done_888), + .I2(plm_v4f_mgt_for_v1_4_cal_inst3_sd_state[7]), + .I3(plm_v4f_mgt_for_v1_4_cal_inst3_sd_state[8]), + .LO(plm_v4f_mgt_for_v1_4_cal_inst3_N_2467_i_882) + ); + defparam plm_v4f_mgt_for_v1_4_cal_inst3_N_2466_i.INIT = 16'hD5C0; + LUT4_L plm_v4f_mgt_for_v1_4_cal_inst3_N_2466_i ( + .I0(cmmp_negotiated_width_0[0]), + .I1(plm_v4f_mgt_for_v1_4_cal_inst3_sd_drp_done_888), + .I2(plm_v4f_mgt_for_v1_4_cal_inst3_sd_state[6]), + .I3(plm_v4f_mgt_for_v1_4_cal_inst3_sd_state[7]), + .LO(plm_v4f_mgt_for_v1_4_cal_inst3_N_2466_i_883) + ); + defparam plm_v4f_mgt_for_v1_4_cal_inst3_N_1672_i.INIT = 8'h5C; + LUT3_L plm_v4f_mgt_for_v1_4_cal_inst3_N_1672_i ( + .I0(plm_v4f_mgt_for_v1_4_cal_inst3_sd_drp_done_888), + .I1(plm_v4f_mgt_for_v1_4_cal_inst3_sd_state[5]), + .I2(plm_v4f_mgt_for_v1_4_cal_inst3_sd_state[6]), + .LO(plm_v4f_mgt_for_v1_4_cal_inst3_N_1672_i_884) + ); + defparam plm_v4f_mgt_for_v1_4_cal_inst3_sd_next_state_0_sqmuxa_1_0_a2_0_a2.INIT = 4'h8; + LUT2_L plm_v4f_mgt_for_v1_4_cal_inst3_sd_next_state_0_sqmuxa_1_0_a2_0_a2 ( + .I0(plm_v4f_mgt_for_v1_4_cal_inst3_sd_drp_done_888), + .I1(plm_v4f_mgt_for_v1_4_cal_inst3_sd_state[4]), + .LO(plm_v4f_mgt_for_v1_4_cal_inst3_sd_next_state_0_sqmuxa_1) + ); + defparam plm_v4f_mgt_for_v1_4_cal_inst3_N_1673_i.INIT = 8'h5C; + LUT3_L plm_v4f_mgt_for_v1_4_cal_inst3_N_1673_i ( + .I0(plm_v4f_mgt_for_v1_4_cal_inst3_sd_drp_done_888), + .I1(plm_v4f_mgt_for_v1_4_cal_inst3_sd_state[2]), + .I2(plm_v4f_mgt_for_v1_4_cal_inst3_sd_state[3]), + .LO(plm_v4f_mgt_for_v1_4_cal_inst3_N_1673_i_885) + ); + defparam plm_v4f_mgt_for_v1_4_cal_inst3_sd_next_state_0_sqmuxa_0_a2_0_a2.INIT = 4'h8; + LUT2_L plm_v4f_mgt_for_v1_4_cal_inst3_sd_next_state_0_sqmuxa_0_a2_0_a2 ( + .I0(plm_v4f_mgt_for_v1_4_cal_inst3_sd_drp_done_888), + .I1(plm_v4f_mgt_for_v1_4_cal_inst3_sd_state[1]), + .LO(plm_v4f_mgt_for_v1_4_cal_inst3_sd_next_state_0_sqmuxa) + ); + defparam plm_v4f_mgt_for_v1_4_cal_inst3_N_2471_i.INIT = 16'h3350; + LUT4_L plm_v4f_mgt_for_v1_4_cal_inst3_N_2471_i ( + .I0(cmmp_negotiated_width_0[0]), + .I1(plm_v4f_mgt_for_v1_4_cal_inst3_sd_drp_done_888), + .I2(plm_v4f_mgt_for_v1_4_cal_inst3_sd_state[0]), + .I3(plm_v4f_mgt_for_v1_4_cal_inst3_sd_state[1]), + .LO(plm_v4f_mgt_for_v1_4_cal_inst3_N_2471_i_886) + ); + defparam plm_v4f_mgt_for_v1_4_cal_inst3_N_2468_i.INIT = 16'hCCA0; + LUT4_L plm_v4f_mgt_for_v1_4_cal_inst3_N_2468_i ( + .I0(cmmp_negotiated_width_0[0]), + .I1(plm_v4f_mgt_for_v1_4_cal_inst3_sd_drp_done_888), + .I2(plm_v4f_mgt_for_v1_4_cal_inst3_sd_state[0]), + .I3(plm_v4f_mgt_for_v1_4_cal_inst3_sd_state[13]), + .LO(plm_v4f_mgt_for_v1_4_cal_inst3_N_2468_i_887) + ); + defparam plm_v4f_mgt_for_v1_4_cal_inst3_drp_next_state_0_sqmuxa_0_a2.INIT = 4'h8; + LUT2_L plm_v4f_mgt_for_v1_4_cal_inst3_drp_next_state_0_sqmuxa_0_a2 ( + .I0(plm_v4f_mgt_for_v1_4_cal_inst3_drp_state_3__890), + .I1(plm_v4f_mgt_for_v1_4_cal_inst3_gt_drdy_r_897), + .LO(plm_v4f_mgt_for_v1_4_cal_inst3_drp_next_state_0_sqmuxa) + ); + defparam plm_v4f_mgt_for_v1_4_cal_inst3_N_2396_i.INIT = 16'hFFAE; + LUT4_L plm_v4f_mgt_for_v1_4_cal_inst3_N_2396_i ( + .I0(plm_v4f_mgt_for_v1_4_cal_inst3_drp_state_1__891), + .I1(plm_v4f_mgt_for_v1_4_cal_inst3_drp_state_3__890), + .I2(plm_v4f_mgt_for_v1_4_cal_inst3_gt_drdy_r_897), + .I3(plm_v4f_mgt_gt3_dwe), + .LO(plm_v4f_mgt_for_v1_4_cal_inst3_N_2396_i_889) + ); + defparam plm_v4f_mgt_for_v1_4_cal_inst3_drp_next_state_0_sqmuxa_1_0_a2.INIT = 8'h80; + LUT3_L plm_v4f_mgt_for_v1_4_cal_inst3_drp_next_state_0_sqmuxa_1_0_a2 ( + .I0(plm_v4f_mgt_for_v1_4_cal_inst3_cb_state[2]), + .I1(plm_v4f_mgt_for_v1_4_cal_inst3_drp_state_0__896), + .I2(plm_v4f_mgt_for_v1_4_cal_inst3_sd_write_892), + .LO(plm_v4f_mgt_for_v1_4_cal_inst3_drp_next_state_0_sqmuxa_1) + ); + defparam plm_v4f_mgt_for_v1_4_cal_inst3_drp_next_state_1_sqmuxa_1_i.INIT = 8'h80; + LUT3_L plm_v4f_mgt_for_v1_4_cal_inst3_drp_next_state_1_sqmuxa_1_i ( + .I0(plm_v4f_mgt_for_v1_4_cal_inst3_cb_state[2]), + .I1(plm_v4f_mgt_for_v1_4_cal_inst3_drp_state_0__896), + .I2(plm_v4f_mgt_for_v1_4_cal_inst3_sd_read_893), + .LO(plm_v4f_mgt_for_v1_4_cal_inst3_N_1379_i) + ); + defparam plm_v4f_mgt_for_v1_4_cal_inst3_N_2470_i.INIT = 16'hFFB0; + LUT4_L plm_v4f_mgt_for_v1_4_cal_inst3_N_2470_i ( + .I0(plm_v4f_mgt_for_v1_4_cal_inst3_sd_req_3_0_a2_0_a2_2), + .I1(plm_v4f_mgt_for_v1_4_cal_inst3_cb_state[2]), + .I2(plm_v4f_mgt_for_v1_4_cal_inst3_drp_state_0__896), + .I3(plm_v4f_mgt_for_v1_4_cal_inst3_drp_state_4__895), + .LO(plm_v4f_mgt_for_v1_4_cal_inst3_N_2470_i_894) + ); + FD plm_v4f_mgt_for_v1_4_cal_inst3_gt_drdy_r ( + .C(plm_v4f_mgt_cal_clk), + .D(plm_v4f_mgt_gt3_drdy), + .Q(plm_v4f_mgt_for_v1_4_cal_inst3_gt_drdy_r_897) + ); + FDE plm_v4f_mgt_for_v1_4_cal_inst3_sd_wr_wreg_9_ ( + .CE(plm_v4f_mgt_for_v1_4_cal_inst3_N_1645_i), + .C(plm_v4f_mgt_cal_clk), + .D(plm_v4f_mgt_gt3_di[9]), + .Q(plm_v4f_mgt_for_v1_4_cal_inst3_sd_wr_wreg[9]) + ); + FDE plm_v4f_mgt_for_v1_4_cal_inst3_sd_wr_wreg_8_ ( + .CE(plm_v4f_mgt_for_v1_4_cal_inst3_N_1645_i), + .C(plm_v4f_mgt_cal_clk), + .D(plm_v4f_mgt_gt3_di[8]), + .Q(plm_v4f_mgt_for_v1_4_cal_inst3_sd_wr_wreg[8]) + ); + FDE plm_v4f_mgt_for_v1_4_cal_inst3_sd_wr_wreg_7_ ( + .CE(plm_v4f_mgt_for_v1_4_cal_inst3_N_1645_i), + .C(plm_v4f_mgt_cal_clk), + .D(plm_v4f_mgt_gt3_di[7]), + .Q(plm_v4f_mgt_for_v1_4_cal_inst3_sd_wr_wreg[7]) + ); + FDE plm_v4f_mgt_for_v1_4_cal_inst3_sd_wr_wreg_6_ ( + .CE(plm_v4f_mgt_for_v1_4_cal_inst3_N_1645_i), + .C(plm_v4f_mgt_cal_clk), + .D(plm_v4f_mgt_gt3_di[6]), + .Q(plm_v4f_mgt_for_v1_4_cal_inst3_sd_wr_wreg[6]) + ); + FDE plm_v4f_mgt_for_v1_4_cal_inst3_sd_wr_wreg_5_ ( + .CE(plm_v4f_mgt_for_v1_4_cal_inst3_N_1645_i), + .C(plm_v4f_mgt_cal_clk), + .D(plm_v4f_mgt_gt3_di[5]), + .Q(plm_v4f_mgt_for_v1_4_cal_inst3_sd_wr_wreg[5]) + ); + FDE plm_v4f_mgt_for_v1_4_cal_inst3_sd_wr_wreg_4_ ( + .CE(plm_v4f_mgt_for_v1_4_cal_inst3_N_1645_i), + .C(plm_v4f_mgt_cal_clk), + .D(plm_v4f_mgt_gt3_di[4]), + .Q(plm_v4f_mgt_for_v1_4_cal_inst3_sd_wr_wreg[4]) + ); + FDE plm_v4f_mgt_for_v1_4_cal_inst3_sd_wr_wreg_3_ ( + .CE(plm_v4f_mgt_for_v1_4_cal_inst3_N_1645_i), + .C(plm_v4f_mgt_cal_clk), + .D(plm_v4f_mgt_gt3_di[3]), + .Q(plm_v4f_mgt_for_v1_4_cal_inst3_sd_wr_wreg[3]) + ); + FDE plm_v4f_mgt_for_v1_4_cal_inst3_sd_wr_wreg_2_ ( + .CE(plm_v4f_mgt_for_v1_4_cal_inst3_N_1645_i), + .C(plm_v4f_mgt_cal_clk), + .D(plm_v4f_mgt_gt3_di[2]), + .Q(plm_v4f_mgt_for_v1_4_cal_inst3_sd_wr_wreg[2]) + ); + FD plm_v4f_mgt_for_v1_4_cal_inst3_sd_wr_wreg_1_ ( + .C(plm_v4f_mgt_cal_clk), + .D(plm_v4f_mgt_for_v1_4_cal_inst3_N_2469_i_898), + .Q(plm_v4f_mgt_for_v1_4_cal_inst3_sd_wr_wreg[1]) + ); + FDE plm_v4f_mgt_for_v1_4_cal_inst3_sd_wr_wreg_0_ ( + .CE(plm_v4f_mgt_for_v1_4_cal_inst3_N_1645_i), + .C(plm_v4f_mgt_cal_clk), + .D(plm_v4f_mgt_gt3_di[0]), + .Q(plm_v4f_mgt_for_v1_4_cal_inst3_sd_wr_wreg[0]) + ); + FDP plm_v4f_mgt_for_v1_4_cal_inst3_reset_r_0_ ( + .PRE(plm_v4f_mgt_N_438_i), + .C(plm_v4f_mgt_cal_clk), + .D(plm_v4f_mgt_for_v1_4_cal_inst3_reset_r[1]), + .Q(plm_v4f_mgt_for_v1_4_cal_inst0_reset_r[0]) + ); + FDE plm_v4f_mgt_for_v1_4_cal_inst3_sd_wr_wreg_15_ ( + .CE(plm_v4f_mgt_for_v1_4_cal_inst3_N_1645_i), + .C(plm_v4f_mgt_cal_clk), + .D(plm_v4f_mgt_gt3_di[15]), + .Q(plm_v4f_mgt_for_v1_4_cal_inst3_sd_wr_wreg[15]) + ); + FDE plm_v4f_mgt_for_v1_4_cal_inst3_sd_wr_wreg_14_ ( + .CE(plm_v4f_mgt_for_v1_4_cal_inst3_N_1645_i), + .C(plm_v4f_mgt_cal_clk), + .D(plm_v4f_mgt_gt3_di[14]), + .Q(plm_v4f_mgt_for_v1_4_cal_inst3_sd_wr_wreg[14]) + ); + FDE plm_v4f_mgt_for_v1_4_cal_inst3_sd_wr_wreg_13_ ( + .CE(plm_v4f_mgt_for_v1_4_cal_inst3_N_1645_i), + .C(plm_v4f_mgt_cal_clk), + .D(plm_v4f_mgt_gt3_di[13]), + .Q(plm_v4f_mgt_for_v1_4_cal_inst3_sd_wr_wreg[13]) + ); + FD plm_v4f_mgt_for_v1_4_cal_inst3_sd_wr_wreg_12_ ( + .C(plm_v4f_mgt_cal_clk), + .D(plm_v4f_mgt_for_v1_4_cal_inst3_N_2472_i_899), + .Q(plm_v4f_mgt_for_v1_4_cal_inst3_sd_wr_wreg[12]) + ); + FDE plm_v4f_mgt_for_v1_4_cal_inst3_sd_wr_wreg_11_ ( + .CE(plm_v4f_mgt_for_v1_4_cal_inst3_N_1645_i), + .C(plm_v4f_mgt_cal_clk), + .D(plm_v4f_mgt_gt3_di[11]), + .Q(plm_v4f_mgt_for_v1_4_cal_inst3_sd_wr_wreg[11]) + ); + FDE plm_v4f_mgt_for_v1_4_cal_inst3_sd_wr_wreg_10_ ( + .CE(plm_v4f_mgt_for_v1_4_cal_inst3_N_1645_i), + .C(plm_v4f_mgt_cal_clk), + .D(plm_v4f_mgt_gt3_di[10]), + .Q(plm_v4f_mgt_for_v1_4_cal_inst3_sd_wr_wreg[10]) + ); + FDE plm_v4f_mgt_for_v1_4_cal_inst3_gt_do_r_15_ ( + .CE(plm_v4f_mgt_for_v1_4_cal_inst3_cb_state[2]), + .C(plm_v4f_mgt_cal_clk), + .D(plm_v4f_mgt_for_v1_4_cal_inst3_gt_do_r_4_i_m2_0_a2_0_a2_15__900), + .Q(plm_v4f_mgt_gt3_do[15]) + ); + FDE plm_v4f_mgt_for_v1_4_cal_inst3_gt_do_r_14_ ( + .CE(plm_v4f_mgt_for_v1_4_cal_inst3_cb_state[2]), + .C(plm_v4f_mgt_cal_clk), + .D(plm_v4f_mgt_for_v1_4_cal_inst3_gt_do_r_4_i_m2_0_a2_0_a2_14__901), + .Q(plm_v4f_mgt_gt3_do[14]) + ); + FDE plm_v4f_mgt_for_v1_4_cal_inst3_gt_do_r_13_ ( + .CE(plm_v4f_mgt_for_v1_4_cal_inst3_cb_state[2]), + .C(plm_v4f_mgt_cal_clk), + .D(plm_v4f_mgt_for_v1_4_cal_inst3_gt_do_r_4_i_m2_0_a2_0_a2_13__902), + .Q(plm_v4f_mgt_gt3_do[13]) + ); + FDE plm_v4f_mgt_for_v1_4_cal_inst3_gt_do_r_12_ ( + .CE(plm_v4f_mgt_for_v1_4_cal_inst3_cb_state[2]), + .C(plm_v4f_mgt_cal_clk), + .D(plm_v4f_mgt_for_v1_4_cal_inst3_gt_do_r_4_i_m2_0_a2_0_a2_2_12_), + .Q(plm_v4f_mgt_gt3_do[12]) + ); + FDE plm_v4f_mgt_for_v1_4_cal_inst3_gt_do_r_11_ ( + .CE(plm_v4f_mgt_for_v1_4_cal_inst3_cb_state[2]), + .C(plm_v4f_mgt_cal_clk), + .D(plm_v4f_mgt_for_v1_4_cal_inst3_gt_do_r_4_i_m2_0_a2_0_a2_11__903), + .Q(plm_v4f_mgt_gt3_do[11]) + ); + FDE plm_v4f_mgt_for_v1_4_cal_inst3_gt_do_r_10_ ( + .CE(plm_v4f_mgt_for_v1_4_cal_inst3_cb_state[2]), + .C(plm_v4f_mgt_cal_clk), + .D(plm_v4f_mgt_for_v1_4_cal_inst3_gt_do_r_4_i_m2_0_a2_0_a2_10__904), + .Q(plm_v4f_mgt_gt3_do[10]) + ); + FDE plm_v4f_mgt_for_v1_4_cal_inst3_gt_do_r_9_ ( + .CE(plm_v4f_mgt_for_v1_4_cal_inst3_cb_state[2]), + .C(plm_v4f_mgt_cal_clk), + .D(plm_v4f_mgt_for_v1_4_cal_inst3_gt_do_r_4_i_m2_0_a2_0_a2_9__905), + .Q(plm_v4f_mgt_gt3_do[9]) + ); + FDE plm_v4f_mgt_for_v1_4_cal_inst3_gt_do_r_8_ ( + .CE(plm_v4f_mgt_for_v1_4_cal_inst3_cb_state[2]), + .C(plm_v4f_mgt_cal_clk), + .D(plm_v4f_mgt_for_v1_4_cal_inst3_gt_do_r_4_i_m2_0_a2_0_a2_8__906), + .Q(plm_v4f_mgt_gt3_do[8]) + ); + FDE plm_v4f_mgt_for_v1_4_cal_inst3_gt_do_r_7_ ( + .CE(plm_v4f_mgt_for_v1_4_cal_inst3_cb_state[2]), + .C(plm_v4f_mgt_cal_clk), + .D(plm_v4f_mgt_for_v1_4_cal_inst3_gt_do_r_4_i_m2_0_a2_0_a2_7__907), + .Q(plm_v4f_mgt_gt3_do[7]) + ); + FDE plm_v4f_mgt_for_v1_4_cal_inst3_gt_do_r_6_ ( + .CE(plm_v4f_mgt_for_v1_4_cal_inst3_cb_state[2]), + .C(plm_v4f_mgt_cal_clk), + .D(plm_v4f_mgt_for_v1_4_cal_inst3_gt_do_r_4_i_m2_0_a2_0_a2_6__908), + .Q(plm_v4f_mgt_gt3_do[6]) + ); + FDE plm_v4f_mgt_for_v1_4_cal_inst3_gt_do_r_5_ ( + .CE(plm_v4f_mgt_for_v1_4_cal_inst3_cb_state[2]), + .C(plm_v4f_mgt_cal_clk), + .D(plm_v4f_mgt_for_v1_4_cal_inst3_gt_do_r_4_i_m2_0_a2_0_a2_5__909), + .Q(plm_v4f_mgt_gt3_do[5]) + ); + FDE plm_v4f_mgt_for_v1_4_cal_inst3_gt_do_r_4_ ( + .CE(plm_v4f_mgt_for_v1_4_cal_inst3_cb_state[2]), + .C(plm_v4f_mgt_cal_clk), + .D(plm_v4f_mgt_for_v1_4_cal_inst3_gt_do_r_4_i_m2_0_a2_0_a2_4__910), + .Q(plm_v4f_mgt_gt3_do[4]) + ); + FDE plm_v4f_mgt_for_v1_4_cal_inst3_gt_do_r_3_ ( + .CE(plm_v4f_mgt_for_v1_4_cal_inst3_cb_state[2]), + .C(plm_v4f_mgt_cal_clk), + .D(plm_v4f_mgt_for_v1_4_cal_inst3_gt_do_r_4_i_m2_0_a2_0_a2_3__911), + .Q(plm_v4f_mgt_gt3_do[3]) + ); + FDE plm_v4f_mgt_for_v1_4_cal_inst3_gt_do_r_2_ ( + .CE(plm_v4f_mgt_for_v1_4_cal_inst3_cb_state[2]), + .C(plm_v4f_mgt_cal_clk), + .D(plm_v4f_mgt_for_v1_4_cal_inst3_gt_do_r_4_i_m2_0_a2_0_a2_2__912), + .Q(plm_v4f_mgt_gt3_do[2]) + ); + FDE plm_v4f_mgt_for_v1_4_cal_inst3_gt_do_r_1_ ( + .CE(plm_v4f_mgt_for_v1_4_cal_inst3_cb_state[2]), + .C(plm_v4f_mgt_cal_clk), + .D(plm_v4f_mgt_for_v1_4_cal_inst3_gt_do_r_4_i_m2_0_a2_0_a2_2_1_), + .Q(plm_v4f_mgt_gt3_do[1]) + ); + FDE plm_v4f_mgt_for_v1_4_cal_inst3_gt_do_r_0_ ( + .CE(plm_v4f_mgt_for_v1_4_cal_inst3_cb_state[2]), + .C(plm_v4f_mgt_cal_clk), + .D(plm_v4f_mgt_for_v1_4_cal_inst3_gt_do_r_4_i_m2_0_a2_0_a2_0__913), + .Q(plm_v4f_mgt_gt3_do[0]) + ); + FDE plm_v4f_mgt_for_v1_4_cal_inst3_GT_DADDR_1_5_ ( + .CE(plm_v4f_mgt_for_v1_4_cal_inst3_cb_state[2]), + .C(plm_v4f_mgt_cal_clk), + .D(plm_v4f_mgt_for_v1_4_cal_inst3_N_1524_i), + .Q(plm_v4f_mgt_gt3_daddr[5]) + ); + FDE plm_v4f_mgt_for_v1_4_cal_inst3_GT_DADDR_1_3_ ( + .CE(plm_v4f_mgt_for_v1_4_cal_inst3_cb_state[2]), + .C(plm_v4f_mgt_cal_clk), + .D(plm_v4f_mgt_for_v1_4_cal_inst3_VCC_914), + .Q(plm_v4f_mgt_gt3_daddr[3]) + ); + FDE plm_v4f_mgt_for_v1_4_cal_inst3_GT_DADDR_1_2_ ( + .CE(plm_v4f_mgt_for_v1_4_cal_inst3_cb_state[2]), + .C(plm_v4f_mgt_cal_clk), + .D(plm_v4f_mgt_for_v1_4_cal_inst3_N_1718_i_915), + .Q(plm_v4f_mgt_gt3_daddr[2]) + ); + FDE plm_v4f_mgt_for_v1_4_cal_inst3_GT_DADDR_1_1_ ( + .CE(plm_v4f_mgt_for_v1_4_cal_inst3_cb_state[2]), + .C(plm_v4f_mgt_cal_clk), + .D(plm_v4f_mgt_for_v1_4_cal_inst3_GT_DADDR_5_i_i_a2_0_a2_2[1]), + .Q(plm_v4f_mgt_gt3_daddr[1]) + ); + FDE plm_v4f_mgt_for_v1_4_cal_inst3_GT_DADDR_1_0_ ( + .CE(plm_v4f_mgt_for_v1_4_cal_inst3_cb_state[2]), + .C(plm_v4f_mgt_cal_clk), + .D(plm_v4f_mgt_for_v1_4_cal_inst3_N_1665_i_i_916), + .Q(plm_v4f_mgt_gt3_daddr[4]) + ); + INV plm_v4f_mgt_for_v1_4_cal_inst3_cb_state_i_2_ ( + .I(plm_v4f_mgt_for_v1_4_cal_inst3_cb_state[2]), + .O(plm_v4f_mgt_for_v1_4_cal_inst3_cb_state_i[2]) + ); + defparam plm_des0_input_decoder_reg_sym_4_0_a7_0_.INIT = 4'h1; + LUT2 plm_des0_input_decoder_reg_sym_4_0_a7_0_ ( + .I0(plm_des0_reg_nitbl[0]), + .I1(plm_des0_reg_spesh[0]), + .O(plm_des0_reg_sym_4[0]) + ); + defparam plm_des0_input_decoder_reg_sym_3_0_a7_1_.INIT = 4'h1; + LUT2 plm_des0_input_decoder_reg_sym_3_0_a7_1_ ( + .I0(plm_des0_reg_nitbl[1]), + .I1(plm_des0_reg_spesh[1]), + .O(plm_des0_reg_sym_3[1]) + ); + defparam plm_des0_descram_reg_rx_des_dat_14_sn_m1_0_a2_0_a3_0_a2_0_a2.INIT = 4'h1; + LUT2 plm_des0_descram_reg_rx_des_dat_14_sn_m1_0_a2_0_a3_0_a2_0_a2 ( + .I0(plm_des0_reg_kkk[0]), + .I1(plm_reg_dis), + .O(plm_des0_m1_0_a2_0_a3_0_a2_0_a2) + ); + defparam plm_des0_lfsrs_reg_lfsr_one_12_0_iv_i_i_0_o4_0_.INIT = 4'h1; + LUT2 plm_des0_lfsrs_reg_lfsr_one_12_0_iv_i_i_0_o4_0_ ( + .I0(plm_des0_reg_skp[0]), + .I1(plm_des0_reg_skp[1]), + .O(plm_des0_N_49056_i) + ); + defparam plm_des0_descram_reg_rx_des_dat_7_0_x2_0_x2_0_o4_0_8_.INIT = 4'h1; + LUT2 plm_des0_descram_reg_rx_des_dat_7_0_x2_0_x2_0_o4_0_8_ ( + .I0(plm_des0_reg_kkk[1]), + .I1(plm_reg_dis), + .O(plm_des0_N_49067_i) + ); + defparam plm_des0_lfsrs_reg_lfsr_two_12_0_iv_0_0_0_o2_12_.INIT = 4'h1; + LUT2 plm_des0_lfsrs_reg_lfsr_two_12_0_iv_0_0_0_o2_12_ ( + .I0(plm_des0_reg_com[0]), + .I1(plm_des0_reg_com[1]), + .O(plm_des0_reg_lfsr_two_12_0_iv_0_0_0_o2[12]) + ); + defparam plm_des0_one_adv2_1_15_.INIT = 4'h6; + LUT2 plm_des0_one_adv2_1_15_ ( + .I0(plm_des0_reg_lfsr_one_10__935), + .I1(plm_des0_reg_lfsr_one_11__563), + .O(plm_des0_one_adv2_1_15__917) + ); + defparam plm_des0_one_adv2_1_13_.INIT = 4'h6; + LUT2 plm_des0_one_adv2_1_13_ ( + .I0(plm_des0_reg_lfsr_one_8__937), + .I1(plm_des0_reg_lfsr_one_9__936), + .O(plm_des0_one_adv2_1_13__918) + ); + defparam plm_des0_one_adv2_1_9_.INIT = 4'h6; + LUT2 plm_des0_one_adv2_1_9_ ( + .I0(plm_des0_reg_lfsr_one_4__941), + .I1(plm_des0_reg_lfsr_one_5__940), + .O(plm_des0_one_adv2_1_9__925) + ); + defparam plm_des0_one_adv2_1_6_.INIT = 4'h6; + LUT2 plm_des0_one_adv2_1_6_ ( + .I0(plm_des0_reg_lfsr_one_1__562), + .I1(plm_des0_reg_lfsr_one_12__622), + .O(plm_des0_one_adv2_1_6__924) + ); + defparam plm_des0_one_adv2_1_5_.INIT = 4'h6; + LUT2 plm_des0_one_adv2_1_5_ ( + .I0(plm_des0_reg_lfsr_one_2__942), + .I1(plm_des0_reg_lfsr_one_13__567), + .O(plm_des0_one_adv2_1_5__926) + ); + defparam plm_des0_two_adv2_1_14_.INIT = 4'h6; + LUT2 plm_des0_two_adv2_1_14_ ( + .I0(plm_des0_reg_lfsr_two_9__945), + .I1(plm_des0_reg_lfsr_two_10__944), + .O(plm_des0_two_adv2_1_14__920) + ); + defparam plm_des0_two_adv2_1_12_.INIT = 4'h6; + LUT2 plm_des0_two_adv2_1_12_ ( + .I0(plm_des0_reg_lfsr_two_7__947), + .I1(plm_des0_reg_lfsr_two_8__946), + .O(plm_des0_two_adv2_1_12__921) + ); + defparam plm_des0_two_adv2_1_10_.INIT = 4'h6; + LUT2 plm_des0_two_adv2_1_10_ ( + .I0(plm_des0_reg_lfsr_two_5__949), + .I1(plm_des0_reg_lfsr_two_6__948), + .O(plm_des0_two_adv2_1_10__927) + ); + defparam plm_des0_two_adv2_1_7_.INIT = 4'h6; + LUT2 plm_des0_two_adv2_1_7_ ( + .I0(plm_des0_reg_lfsr_two_2__648), + .I1(plm_des0_reg_lfsr_two_13__532), + .O(plm_des0_two_adv2_1_7__923) + ); + defparam plm_des0_two_adv2_1_1_.INIT = 4'h6; + LUT2 plm_des0_two_adv2_1_1_ ( + .I0(plm_des0_reg_lfsr_two_12__943), + .I1(plm_des0_reg_lfsr_two_13__532), + .O(plm_des0_two_adv2_1_1__922) + ); + defparam plm_des0_input_decoder_reg_bad_4_i_a7_2_0_0_.INIT = 4'h4; + LUT2_L plm_des0_input_decoder_reg_bad_4_i_a7_2_0_0_ ( + .I0(plm_des0_reg_data[5]), + .I1(plm_des0_reg_data[7]), + .LO(plm_des0_reg_bad_4_i_a7_2_0[0]) + ); + defparam plm_des0_input_decoder_reg_bad_3_i_a7_2_0_1_.INIT = 4'h4; + LUT2_L plm_des0_input_decoder_reg_bad_3_i_a7_2_0_1_ ( + .I0(plm_des0_reg_data[13]), + .I1(plm_des0_reg_data[15]), + .LO(plm_des0_reg_bad_3_i_a7_2_0[1]) + ); + defparam plm_des0_two_adv2_0_15_.INIT = 4'h6; + LUT2 plm_des0_two_adv2_0_15_ ( + .I0(plm_des0_reg_lfsr_two_10__944), + .I1(plm_des0_reg_lfsr_two_15__533), + .O(plm_des0_two_adv2_0_15__919) + ); + defparam plm_des0_two_adv2_0_4_.INIT = 4'h6; + LUT2 plm_des0_two_adv2_0_4_ ( + .I0(plm_des0_reg_lfsr_two_0__530), + .I1(plm_des0_reg_lfsr_two_1__647), + .O(plm_des0_two_adv2_0_4__930) + ); + defparam plm_des0_lfsrs_reg_lfsr_one32_i.INIT = 4'h7; + LUT2 plm_des0_lfsrs_reg_lfsr_one32_i ( + .I0(plm_des0_reg_skp[0]), + .I1(plm_des0_reg_skp[1]), + .O(plm_des0_reg_lfsr_one32_i) + ); + defparam plm_des0_input_decoder_reg_bad_4_i_x2_0_.INIT = 16'h7888; + LUT4 plm_des0_input_decoder_reg_bad_4_i_x2_0_ ( + .I0(plm_des0_reg_data[0]), + .I1(plm_des0_reg_data[1]), + .I2(plm_des0_reg_data[2]), + .I3(plm_des0_reg_data[3]), + .O(plm_des0_N_14272_i) + ); + defparam plm_des0_input_decoder_reg_bad_4_i_x2_0_0_.INIT = 16'hE111; + LUT4 plm_des0_input_decoder_reg_bad_4_i_x2_0_0_ ( + .I0(plm_des0_reg_data[0]), + .I1(plm_des0_reg_data[1]), + .I2(plm_des0_reg_data[6]), + .I3(plm_des0_reg_data[7]), + .O(plm_des0_N_14273_i) + ); + defparam plm_des0_input_decoder_reg_bad_3_i_x2_1_.INIT = 16'h7888; + LUT4 plm_des0_input_decoder_reg_bad_3_i_x2_1_ ( + .I0(plm_des0_reg_data[8]), + .I1(plm_des0_reg_data[9]), + .I2(plm_des0_reg_data[10]), + .I3(plm_des0_reg_data[11]), + .O(plm_des0_N_14319_i) + ); + defparam plm_des0_input_decoder_reg_bad_3_i_x2_0_1_.INIT = 16'hE111; + LUT4 plm_des0_input_decoder_reg_bad_3_i_x2_0_1_ ( + .I0(plm_des0_reg_data[8]), + .I1(plm_des0_reg_data[9]), + .I2(plm_des0_reg_data[14]), + .I3(plm_des0_reg_data[15]), + .O(plm_des0_N_14320_i) + ); + defparam plm_des0_input_decoder_reg_idl_3_0_a7_2_1_.INIT = 16'h1000; + LUT4 plm_des0_input_decoder_reg_idl_3_0_a7_2_1_ ( + .I0(plm_des0_reg_data[8]), + .I1(plm_des0_reg_data[9]), + .I2(plm_des0_reg_data[10]), + .I3(plm_des0_reg_data[11]), + .O(plm_des0_reg_idl_3_2[1]) + ); + defparam plm_des0_input_decoder_reg_idl_4_0_a7_2_0_.INIT = 16'h1000; + LUT4 plm_des0_input_decoder_reg_idl_4_0_a7_2_0_ ( + .I0(plm_des0_reg_data[0]), + .I1(plm_des0_reg_data[1]), + .I2(plm_des0_reg_data[2]), + .I3(plm_des0_reg_data[3]), + .O(plm_des0_reg_idl_4_2[0]) + ); + defparam plm_des0_lfsrs_reg_lfsr_two_12_iv_0_0_0_o4_9_.INIT = 8'h23; + LUT3 plm_des0_lfsrs_reg_lfsr_two_12_iv_0_0_0_o4_9_ ( + .I0(plm_des0_reg_com[1]), + .I1(plm_des0_reg_skp[0]), + .I2(plm_des0_reg_skp[1]), + .O(plm_des0_reg_lfsr_two_12_iv_0_0_0_o4[9]) + ); + defparam plm_des0_lfsrs_reg_lfsr_two_12_iv_0_0_0_o2_9_.INIT = 8'h15; + LUT3 plm_des0_lfsrs_reg_lfsr_two_12_iv_0_0_0_o2_9_ ( + .I0(plm_des0_reg_com[0]), + .I1(plm_des0_reg_com[1]), + .I2(plm_des0_reg_skp[0]), + .O(plm_des0_N_49059_i) + ); + defparam plm_des0_two_adv2_1_6_.INIT = 8'h96; + LUT3 plm_des0_two_adv2_1_6_ ( + .I0(plm_des0_reg_lfsr_two_3__950), + .I1(plm_des0_reg_lfsr_two_12__943), + .I2(plm_des0_reg_lfsr_two_14__649), + .O(plm_des0_two_adv2_1_6__929) + ); + defparam plm_des0_one_adv2_2_.INIT = 8'h96; + LUT3 plm_des0_one_adv2_2_ ( + .I0(plm_des0_one_adv2_1_5__926), + .I1(plm_des0_reg_lfsr_one_14__650), + .I2(plm_des0_reg_lfsr_one_15__564), + .O(plm_des0_one_adv2[2]) + ); + defparam plm_des0_one_adv2_1_.INIT = 8'h96; + LUT3 plm_des0_one_adv2_1_ ( + .I0(plm_des0_one_adv2_1_6__924), + .I1(plm_des0_reg_lfsr_one_13__567), + .I2(plm_des0_reg_lfsr_one_14__650), + .O(plm_des0_one_adv2[1]) + ); + defparam plm_des0_two_adv2_12_.INIT = 8'h96; + LUT3 plm_des0_two_adv2_12_ ( + .I0(plm_des0_reg_lfsr_two_9__945), + .I1(plm_des0_reg_lfsr_two_12__943), + .I2(plm_des0_two_adv2_1_12__921), + .O(plm_des0_two_adv2_12__931) + ); + defparam plm_des0_two_adv2_10_.INIT = 8'h96; + LUT3 plm_des0_two_adv2_10_ ( + .I0(plm_des0_reg_lfsr_two_7__947), + .I1(plm_des0_reg_lfsr_two_10__944), + .I2(plm_des0_two_adv2_1_10__927), + .O(plm_des0_two_adv2_10__932) + ); + defparam plm_des0_one_adv2_15_.INIT = 8'h96; + LUT3 plm_des0_one_adv2_15_ ( + .I0(plm_des0_one_adv2_1_15__917), + .I1(plm_des0_reg_lfsr_one_12__622), + .I2(plm_des0_reg_lfsr_one_15__564), + .O(plm_des0_one_adv2[15]) + ); + defparam plm_des0_one_adv2_14_.INIT = 8'h96; + LUT3 plm_des0_one_adv2_14_ ( + .I0(plm_des0_one_adv2_1_15__917), + .I1(plm_des0_reg_lfsr_one_9__936), + .I2(plm_des0_reg_lfsr_one_14__650), + .O(plm_des0_one_adv2[14]) + ); + defparam plm_des0_one_adv2_13_.INIT = 8'h96; + LUT3 plm_des0_one_adv2_13_ ( + .I0(plm_des0_one_adv2_1_13__918), + .I1(plm_des0_reg_lfsr_one_10__935), + .I2(plm_des0_reg_lfsr_one_13__567), + .O(plm_des0_one_adv2[13]) + ); + defparam plm_des0_one_adv2_12_.INIT = 8'h96; + LUT3 plm_des0_one_adv2_12_ ( + .I0(plm_des0_one_adv2_1_13__918), + .I1(plm_des0_reg_lfsr_one_7__938), + .I2(plm_des0_reg_lfsr_one_12__622), + .O(plm_des0_one_adv2[12]) + ); + defparam plm_des0_one_adv2_11_.INIT = 16'h6996; + LUT4 plm_des0_one_adv2_11_ ( + .I0(plm_des0_reg_lfsr_one_6__939), + .I1(plm_des0_reg_lfsr_one_7__938), + .I2(plm_des0_reg_lfsr_one_8__937), + .I3(plm_des0_reg_lfsr_one_11__563), + .O(plm_des0_one_adv2[11]) + ); + defparam plm_des0_one_adv2_10_.INIT = 16'h6996; + LUT4 plm_des0_one_adv2_10_ ( + .I0(plm_des0_reg_lfsr_one_5__940), + .I1(plm_des0_reg_lfsr_one_6__939), + .I2(plm_des0_reg_lfsr_one_7__938), + .I3(plm_des0_reg_lfsr_one_10__935), + .O(plm_des0_one_adv2[10]) + ); + defparam plm_des0_input_decoder_reg_t1n_4_0_a7_1_0_0_.INIT = 16'h0800; + LUT4 plm_des0_input_decoder_reg_t1n_4_0_a7_1_0_0_ ( + .I0(plm_des0_reg_data[4]), + .I1(plm_des0_reg_data[5]), + .I2(plm_des0_reg_data[6]), + .I3(plm_des0_reg_data[7]), + .O(plm_des0_reg_t1n_4_1[0]) + ); + defparam plm_des0_input_decoder_reg_t1p_4_0_a7_1_0_0_.INIT = 16'h0010; + LUT4 plm_des0_input_decoder_reg_t1p_4_0_a7_1_0_0_ ( + .I0(plm_des0_reg_data[4]), + .I1(plm_des0_reg_data[5]), + .I2(plm_des0_reg_data[6]), + .I3(plm_des0_reg_data[7]), + .O(plm_des0_reg_t1p_4_1[0]) + ); + defparam plm_des0_input_decoder_reg_t2p_3_0_a7_1_0_1_.INIT = 16'h0010; + LUT4 plm_des0_input_decoder_reg_t2p_3_0_a7_1_0_1_ ( + .I0(plm_des0_reg_data[12]), + .I1(plm_des0_reg_data[13]), + .I2(plm_des0_reg_data[14]), + .I3(plm_des0_reg_data[15]), + .O(plm_des0_reg_t2p_3_1_0[1]) + ); + defparam plm_des0_input_decoder_reg_t1n_3_0_a7_1_0_1_.INIT = 16'h0800; + LUT4 plm_des0_input_decoder_reg_t1n_3_0_a7_1_0_1_ ( + .I0(plm_des0_reg_data[12]), + .I1(plm_des0_reg_data[13]), + .I2(plm_des0_reg_data[14]), + .I3(plm_des0_reg_data[15]), + .O(plm_des0_reg_t1n_3_1[1]) + ); + defparam plm_des0_two_adv2_1_8_.INIT = 8'h96; + LUT3 plm_des0_two_adv2_1_8_ ( + .I0(plm_des0_reg_lfsr_two_4__651), + .I1(plm_des0_reg_lfsr_two_5__949), + .I2(plm_des0_reg_lfsr_two_8__946), + .O(plm_des0_two_adv2_1_8__928) + ); + defparam plm_des0_input_decoder_reg_t1n_3_0_a7_2_0_1_.INIT = 16'h0020; + LUT4 plm_des0_input_decoder_reg_t1n_3_0_a7_2_0_1_ ( + .I0(plm_des0_reg_data[8]), + .I1(plm_des0_reg_data[9]), + .I2(plm_des0_reg_data[10]), + .I3(plm_des0_reg_data[11]), + .O(plm_des0_reg_t1n_3_0_a7_2_0[1]) + ); + defparam plm_des0_input_decoder_reg_t1p_4_0_a7_2_0_0_.INIT = 16'h0400; + LUT4 plm_des0_input_decoder_reg_t1p_4_0_a7_2_0_0_ ( + .I0(plm_des0_reg_data[0]), + .I1(plm_des0_reg_data[1]), + .I2(plm_des0_reg_data[2]), + .I3(plm_des0_reg_data[3]), + .O(plm_des0_reg_t1p_4_0_a7_2_0[0]) + ); + defparam plm_des0_input_decoder_reg_t1n_4_0_a7_2_0_0_.INIT = 16'h0020; + LUT4 plm_des0_input_decoder_reg_t1n_4_0_a7_2_0_0_ ( + .I0(plm_des0_reg_data[0]), + .I1(plm_des0_reg_data[1]), + .I2(plm_des0_reg_data[2]), + .I3(plm_des0_reg_data[3]), + .O(plm_des0_reg_t1n_4_0_a7_2_0[0]) + ); + defparam plm_des0_input_decoder_reg_t2n_3_0_a7_1_0_0_1_.INIT = 16'h0400; + LUT4 plm_des0_input_decoder_reg_t2n_3_0_a7_1_0_0_1_ ( + .I0(plm_des0_reg_data[8]), + .I1(plm_des0_reg_data[9]), + .I2(plm_des0_reg_data[10]), + .I3(plm_des0_reg_data[11]), + .O(plm_des0_reg_t2n_3_0_a7_1_0_0[1]) + ); + defparam plm_des0_input_decoder_reg_edg_4_0_a7_1_0_0_0_.INIT = 16'h8000; + LUT4 plm_des0_input_decoder_reg_edg_4_0_a7_1_0_0_0_ ( + .I0(plm_des0_reg_data[2]), + .I1(plm_des0_reg_data[3]), + .I2(plm_des0_reg_data[6]), + .I3(plm_des0_reg_data[7]), + .O(plm_des0_reg_edg_4_0_a7_1_0_0[0]) + ); + defparam plm_des0_input_decoder_reg_edg_3_0_a7_1_0_0_1_.INIT = 16'h8000; + LUT4 plm_des0_input_decoder_reg_edg_3_0_a7_1_0_0_1_ ( + .I0(plm_des0_reg_data[10]), + .I1(plm_des0_reg_data[11]), + .I2(plm_des0_reg_data[14]), + .I3(plm_des0_reg_data[15]), + .O(plm_des0_reg_edg_3_0_a7_1_0_0[1]) + ); + defparam plm_des0_input_decoder_reg_stp_3_0_a7_1_0_0_1_.INIT = 16'h8000; + LUT4 plm_des0_input_decoder_reg_stp_3_0_a7_1_0_0_1_ ( + .I0(plm_des0_reg_data[8]), + .I1(plm_des0_reg_data[9]), + .I2(plm_des0_reg_data[14]), + .I3(plm_des0_reg_data[15]), + .O(plm_des0_reg_stp_3_0_a7_1_0_0[1]) + ); + defparam plm_des0_input_decoder_reg_stp_4_0_a7_1_0_0_0_.INIT = 16'h8000; + LUT4 plm_des0_input_decoder_reg_stp_4_0_a7_1_0_0_0_ ( + .I0(plm_des0_reg_data[0]), + .I1(plm_des0_reg_data[1]), + .I2(plm_des0_reg_data[6]), + .I3(plm_des0_reg_data[7]), + .O(plm_des0_reg_stp_4_0_a7_1_0_0[0]) + ); + defparam plm_des0_input_decoder_reg_idl_3_0_a7_1_1_.INIT = 16'h0800; + LUT4 plm_des0_input_decoder_reg_idl_3_0_a7_1_1_ ( + .I0(plm_des0_reg_data[12]), + .I1(plm_des0_reg_data[13]), + .I2(plm_des0_reg_nitbl[1]), + .I3(plm_des0_reg_spesh[1]), + .O(plm_des0_reg_idl_3_1[1]) + ); + defparam plm_des0_input_decoder_reg_idl_4_0_a7_1_0_.INIT = 16'h0800; + LUT4 plm_des0_input_decoder_reg_idl_4_0_a7_1_0_ ( + .I0(plm_des0_reg_data[4]), + .I1(plm_des0_reg_data[5]), + .I2(plm_des0_reg_nitbl[0]), + .I3(plm_des0_reg_spesh[0]), + .O(plm_des0_reg_idl_4_1[0]) + ); + defparam plm_des0_lfsrs_reg_lfsr_two_12_iv_i_0_0_a2_0_15_.INIT = 16'h8228; + LUT4 plm_des0_lfsrs_reg_lfsr_two_12_iv_i_0_0_a2_0_15_ ( + .I0(plm_des0_reg_lfsr_two_12_iv_0_0_0_a4_1_0[9]), + .I1(plm_des0_reg_lfsr_two_11__531), + .I2(plm_des0_reg_lfsr_two_12__943), + .I3(plm_des0_two_adv2_0_15__919), + .O(plm_des0_reg_lfsr_two_12_iv_i_0_0_a2_0_15_) + ); + defparam plm_des0_lfsrs_reg_lfsr_two_12_iv_i_0_0_a2_0_14_.INIT = 8'h48; + LUT3 plm_des0_lfsrs_reg_lfsr_two_12_iv_i_0_0_a2_0_14_ ( + .I0(N_49162_i_0), + .I1(plm_des0_reg_lfsr_two_12_iv_0_0_0_a4_1_0[9]), + .I2(plm_des0_two_adv2_1_14__920), + .O(plm_des0_reg_lfsr_two_12_iv_i_0_0_a2_0_14_) + ); + defparam plm_des0_lfsrs_reg_lfsr_two_12_iv_i_0_0_a2_0_13_.INIT = 16'h8228; + LUT4 plm_des0_lfsrs_reg_lfsr_two_12_iv_i_0_0_a2_0_13_ ( + .I0(plm_des0_reg_lfsr_two_12_iv_0_0_0_a4_1_0[9]), + .I1(plm_des0_reg_lfsr_two_8__946), + .I2(plm_des0_reg_lfsr_two_13__532), + .I3(plm_des0_two_adv2_1_14__920), + .O(plm_des0_reg_lfsr_two_12_iv_i_0_0_a2_0_13_) + ); + defparam plm_des0_lfsrs_reg_lfsr_two_12_iv_i_0_0_a2_0_11_.INIT = 16'h8228; + LUT4_L plm_des0_lfsrs_reg_lfsr_two_12_iv_i_0_0_a2_0_11_ ( + .I0(plm_des0_reg_lfsr_two_12_iv_0_0_0_a4_1_0[9]), + .I1(plm_des0_reg_lfsr_two_6__948), + .I2(plm_des0_reg_lfsr_two_11__531), + .I3(plm_des0_two_adv2_1_12__921), + .LO(plm_des0_reg_lfsr_two_12_iv_i_0_0_a2_0_11_) + ); + defparam plm_des0_lfsrs_reg_lfsr_two_12_iv_i_0_0_a2_0_2_.INIT = 16'h8228; + LUT4 plm_des0_lfsrs_reg_lfsr_two_12_iv_i_0_0_a2_0_2_ ( + .I0(plm_des0_reg_lfsr_two_12_iv_0_0_0_a4_1_0[9]), + .I1(plm_des0_reg_lfsr_two_14__649), + .I2(plm_des0_reg_lfsr_two_15__533), + .I3(plm_des0_two_adv2_1_7__923), + .O(plm_des0_reg_lfsr_two_12_iv_i_0_0_a2_0_2_) + ); + defparam plm_des0_lfsrs_reg_lfsr_two_12_iv_i_0_0_a2_0_1_.INIT = 16'h8228; + LUT4 plm_des0_lfsrs_reg_lfsr_two_12_iv_i_0_0_a2_0_1_ ( + .I0(plm_des0_reg_lfsr_two_12_iv_0_0_0_a4_1_0[9]), + .I1(plm_des0_reg_lfsr_two_1__647), + .I2(plm_des0_reg_lfsr_two_14__649), + .I3(plm_des0_two_adv2_1_1__922), + .O(plm_des0_reg_lfsr_two_12_iv_i_0_0_a2_0_1_) + ); + defparam plm_des0_lfsrs_reg_lfsr_two_12_iv_i_0_0_a2_0_0_.INIT = 16'h8228; + LUT4 plm_des0_lfsrs_reg_lfsr_two_12_iv_i_0_0_a2_0_0_ ( + .I0(plm_des0_reg_lfsr_two_12_iv_0_0_0_a4_1_0[9]), + .I1(plm_des0_reg_lfsr_two_0__530), + .I2(plm_des0_reg_lfsr_two_11__531), + .I3(plm_des0_two_adv2_1_1__922), + .O(plm_des0_reg_lfsr_two_12_iv_i_0_0_a2_0_0_) + ); + defparam plm_des0_lfsrs_reg_lfsr_one_12_iv_i_0_0_a2_0_12_.INIT = 4'h8; + LUT2_L plm_des0_lfsrs_reg_lfsr_one_12_iv_i_0_0_a2_0_12_ ( + .I0(plm_des0_reg_lfsr_two_12_iv_0_0_0_a4_1_0[9]), + .I1(plm_des0_one_adv2[12]), + .LO(plm_des0_reg_lfsr_one_12_iv_i_0_0_a2_0_12_) + ); + defparam plm_des0_lfsrs_reg_lfsr_one_12_iv_i_0_0_a2_0_10_.INIT = 4'h8; + LUT2_L plm_des0_lfsrs_reg_lfsr_one_12_iv_i_0_0_a2_0_10_ ( + .I0(plm_des0_reg_lfsr_two_12_iv_0_0_0_a4_1_0[9]), + .I1(plm_des0_one_adv2[10]), + .LO(plm_des0_reg_lfsr_one_12_iv_i_0_0_a2_0_10_) + ); + defparam plm_des0_lfsrs_reg_lfsr_one_12_iv_i_0_0_a2_3_.INIT = 4'h4; + LUT2 plm_des0_lfsrs_reg_lfsr_one_12_iv_i_0_0_a2_3_ ( + .I0(plm_des0_reg_lfsr_two_12_iv_0_0_0_o4[9]), + .I1(plm_des0_reg_lfsr_two_3__950), + .O(plm_des0_reg_lfsr_one_12_iv_i_0_0_a2[3]) + ); + defparam plm_des0_lfsrs_reg_lfsr_one_12_0_iv_i_i_0_x4_0_.INIT = 4'h6; + LUT2 plm_des0_lfsrs_reg_lfsr_one_12_0_iv_i_i_0_x4_0_ ( + .I0(G_415_623), + .I1(plm_des0_reg_lfsr_one_13__567), + .O(plm_des0_N_49079_i_0) + ); + defparam plm_des0_descram_N_86080_i.INIT = 8'h57; + LUT3 plm_des0_descram_N_86080_i ( + .I0(plm_des0_m1_0_a2_0_a3_0_a2_0_a2), + .I1(plm_des0_reg_com[1]), + .I2(plm_des0_reg_skp[1]), + .O(plm_des0_N_86080_i) + ); + defparam plm_des0_two_adv2_7_.INIT = 16'h6996; + LUT4 plm_des0_two_adv2_7_ ( + .I0(N_49159_i_0), + .I1(plm_des0_reg_lfsr_two_3__950), + .I2(plm_des0_reg_lfsr_two_7__947), + .I3(plm_des0_two_adv2_1_7__923), + .O(plm_des0_two_adv2_7__933) + ); + defparam plm_des0_one_adv2_6_.INIT = 16'h6996; + LUT4 plm_des0_one_adv2_6_ ( + .I0(N_49160_i_0), + .I1(plm_des0_one_adv2_1_6__924), + .I2(plm_des0_reg_lfsr_one_2__942), + .I3(plm_des0_reg_lfsr_one_6__939), + .O(plm_des0_one_adv2[6]) + ); + defparam plm_des0_one_adv2_7_.INIT = 16'h6996; + LUT4 plm_des0_one_adv2_7_ ( + .I0(G_326_568), + .I1(plm_des0_reg_lfsr_one_2__942), + .I2(plm_des0_reg_lfsr_one_4__941), + .I3(plm_des0_reg_lfsr_one_7__938), + .O(plm_des0_one_adv2[7]) + ); + defparam plm_des0_one_adv2_9_.INIT = 16'h6996; + LUT4 plm_des0_one_adv2_9_ ( + .I0(plm_des0_one_adv2_1_9__925), + .I1(plm_des0_reg_lfsr_one_6__939), + .I2(plm_des0_reg_lfsr_one_9__936), + .I3(plm_des0_reg_lfsr_one_15__564), + .O(plm_des0_one_adv2[9]) + ); + defparam plm_des0_two_adv2_6_.INIT = 8'h96; + LUT3 plm_des0_two_adv2_6_ ( + .I0(N_49163_i_0), + .I1(plm_des0_reg_lfsr_two_6__948), + .I2(plm_des0_two_adv2_1_6__929), + .O(plm_des0_two_adv2_6__934) + ); + defparam plm_des0_one_adv2_8_.INIT = 8'h96; + LUT3 plm_des0_one_adv2_8_ ( + .I0(N_49160_i_0), + .I1(plm_des0_one_adv2_1_9__925), + .I2(plm_des0_reg_lfsr_one_8__937), + .O(plm_des0_one_adv2[8]) + ); + defparam plm_des0_one_adv2_5_.INIT = 8'h96; + LUT3 plm_des0_one_adv2_5_ ( + .I0(G_325_565), + .I1(plm_des0_one_adv2_1_5__926), + .I2(plm_des0_reg_lfsr_one_5__940), + .O(plm_des0_one_adv2[5]) + ); + defparam plm_des0_one_adv2_4_.INIT = 8'h96; + LUT3 plm_des0_one_adv2_4_ ( + .I0(G_325_565), + .I1(plm_des0_reg_lfsr_one_4__941), + .I2(plm_des0_reg_lfsr_one_14__650), + .O(plm_des0_one_adv2[4]) + ); + defparam plm_des0_input_decoder_reg_skp_3_0_a7_1_0_1_.INIT = 16'h0200; + LUT4 plm_des0_input_decoder_reg_skp_3_0_a7_1_0_1_ ( + .I0(plm_des0_reg_data[12]), + .I1(plm_des0_reg_data[13]), + .I2(plm_des0_reg_nitbl[1]), + .I3(plm_des0_reg_spesh[1]), + .O(plm_des0_reg_skp_3_0_a7_1_0[1]) + ); + defparam plm_des0_input_decoder_reg_skp_4_0_a7_1_0_0_.INIT = 16'h0200; + LUT4 plm_des0_input_decoder_reg_skp_4_0_a7_1_0_0_ ( + .I0(plm_des0_reg_data[4]), + .I1(plm_des0_reg_data[5]), + .I2(plm_des0_reg_nitbl[0]), + .I3(plm_des0_reg_spesh[0]), + .O(plm_des0_reg_skp_4_0_a7_1_0[0]) + ); + defparam plm_des0_input_decoder_reg_bad_4_i_1_0_.INIT = 16'h54FF; + LUT4_L plm_des0_input_decoder_reg_bad_4_i_1_0_ ( + .I0(plm_des0_reg_bad_4_i_a7_2_0[0]), + .I1(plm_des0_reg_data[2]), + .I2(plm_des0_reg_data[3]), + .I3(plm_des0_reg_spesh[0]), + .LO(plm_des0_reg_bad_4_i_1[0]) + ); + defparam plm_des0_input_decoder_reg_bad_3_i_1_1_.INIT = 16'h54FF; + LUT4_L plm_des0_input_decoder_reg_bad_3_i_1_1_ ( + .I0(plm_des0_reg_bad_3_i_a7_2_0[1]), + .I1(plm_des0_reg_data[10]), + .I2(plm_des0_reg_data[11]), + .I3(plm_des0_reg_spesh[1]), + .LO(plm_des0_reg_bad_3_i_1[1]) + ); + defparam plm_des0_lfsrs_reg_lfsr_two_12_iv_0_0_0_a2_0_9_.INIT = 16'h4884; + LUT4 plm_des0_lfsrs_reg_lfsr_two_12_iv_0_0_0_a2_0_9_ ( + .I0(N_49159_i_0), + .I1(plm_des0_reg_lfsr_two_12_iv_0_0_0_a4_1_0[9]), + .I2(plm_des0_reg_lfsr_two_9__945), + .I3(plm_des0_two_adv2_1_10__927), + .O(plm_des0_reg_lfsr_two_12_iv_0_0_0_a2_0_0_9_) + ); + defparam plm_des0_lfsrs_reg_lfsr_two_12_iv_0_0_0_a2_0_8_.INIT = 16'h2882; + LUT4 plm_des0_lfsrs_reg_lfsr_two_12_iv_0_0_0_a2_0_8_ ( + .I0(plm_des0_reg_lfsr_two_12_iv_0_0_0_a4_1_0[9]), + .I1(plm_des0_reg_lfsr_two_3__950), + .I2(plm_des0_reg_lfsr_two_14__649), + .I3(plm_des0_two_adv2_1_8__928), + .O(plm_des0_reg_lfsr_two_12_iv_0_0_0_a2_0_0_8_) + ); + defparam plm_des0_lfsrs_reg_lfsr_two_12_iv_0_0_0_a2_0_5_.INIT = 16'h6090; + LUT4 plm_des0_lfsrs_reg_lfsr_two_12_iv_0_0_0_a2_0_5_ ( + .I0(G_341_534), + .I1(N_49163_i_0), + .I2(plm_des0_reg_lfsr_two_12_iv_0_0_0_a4_1_0[9]), + .I3(plm_des0_reg_lfsr_two_5__949), + .O(plm_des0_reg_lfsr_two_12_iv_0_0_0_a2_0_0_5_) + ); + defparam plm_des0_lfsrs_reg_lfsr_two_12_iv_0_0_0_a2_0_3_.INIT = 8'h84; + LUT3 plm_des0_lfsrs_reg_lfsr_two_12_iv_0_0_0_a2_0_3_ ( + .I0(G_341_534), + .I1(plm_des0_reg_lfsr_two_12_iv_0_0_0_a4_1_0[9]), + .I2(plm_des0_two_adv2_1_6__929), + .O(plm_des0_reg_lfsr_two_12_iv_0_0_0_a2_0_0_3_) + ); + defparam plm_des0_lfsrs_reg_lfsr_two_12_iv_i_0_0_a2_0_4_.INIT = 16'h9060; + LUT4 plm_des0_lfsrs_reg_lfsr_two_12_iv_i_0_0_a2_0_4_ ( + .I0(N_49159_i_0), + .I1(N_49162_i_0), + .I2(plm_des0_reg_lfsr_two_12_iv_0_0_0_a4_1_0[9]), + .I3(plm_des0_two_adv2_0_4__930), + .O(plm_des0_reg_lfsr_two_12_iv_i_0_0_a2_0_4_) + ); + defparam plm_des0_lfsrs_reg_lfsr_one_12_iv_i_0_0_a2_0_9_.INIT = 4'h8; + LUT2_L plm_des0_lfsrs_reg_lfsr_one_12_iv_i_0_0_a2_0_9_ ( + .I0(plm_des0_reg_lfsr_two_12_iv_0_0_0_a4_1_0[9]), + .I1(plm_des0_one_adv2[9]), + .LO(plm_des0_reg_lfsr_one_12_iv_i_0_0_a2_0_9_) + ); + defparam plm_des0_lfsrs_reg_lfsr_one_12_iv_i_0_0_a2_0_8_.INIT = 4'h8; + LUT2_L plm_des0_lfsrs_reg_lfsr_one_12_iv_i_0_0_a2_0_8_ ( + .I0(plm_des0_reg_lfsr_two_12_iv_0_0_0_a4_1_0[9]), + .I1(plm_des0_one_adv2[8]), + .LO(plm_des0_reg_lfsr_one_12_iv_i_0_0_a2_0_8_) + ); + defparam plm_des0_lfsrs_reg_lfsr_one_12_iv_i_0_0_a2_0_7_.INIT = 4'h8; + LUT2_L plm_des0_lfsrs_reg_lfsr_one_12_iv_i_0_0_a2_0_7_ ( + .I0(plm_des0_reg_lfsr_two_12_iv_0_0_0_a4_1_0[9]), + .I1(plm_des0_one_adv2[7]), + .LO(plm_des0_reg_lfsr_one_12_iv_i_0_0_a2_0_7_) + ); + defparam plm_des0_lfsrs_reg_lfsr_one_12_iv_i_0_0_a2_0_6_.INIT = 4'h8; + LUT2_L plm_des0_lfsrs_reg_lfsr_one_12_iv_i_0_0_a2_0_6_ ( + .I0(plm_des0_reg_lfsr_two_12_iv_0_0_0_a4_1_0[9]), + .I1(plm_des0_one_adv2[6]), + .LO(plm_des0_reg_lfsr_one_12_iv_i_0_0_a2_0_6_) + ); + defparam plm_des0_lfsrs_reg_lfsr_one_12_iv_i_0_0_a2_0_5_.INIT = 4'h8; + LUT2_L plm_des0_lfsrs_reg_lfsr_one_12_iv_i_0_0_a2_0_5_ ( + .I0(plm_des0_reg_lfsr_two_12_iv_0_0_0_a4_1_0[9]), + .I1(plm_des0_one_adv2[5]), + .LO(plm_des0_reg_lfsr_one_12_iv_i_0_0_a2_0_5_) + ); + defparam plm_des0_descram_reg_rx_des_dat_14_0_am_7_.INIT = 8'h65; + LUT3 plm_des0_descram_reg_rx_des_dat_14_0_am_7_ ( + .I0(plm_des0_reg_dat[7]), + .I1(plm_des0_reg_lfsr_one_8__937), + .I2(plm_des0_reg_skp[1]), + .O(plm_des0_reg_rx_des_dat_14_0_am_2[7]) + ); + defparam plm_des0_descram_reg_rx_des_dat_14_0_bm_7_.INIT = 8'h6C; + LUT3 plm_des0_descram_reg_rx_des_dat_14_0_bm_7_ ( + .I0(plm_des0_m1_0_a2_0_a3_0_a2_0_a2), + .I1(plm_des0_reg_dat[7]), + .I2(plm_des0_reg_lfsr_two_8__946), + .O(plm_des0_reg_rx_des_dat_14_0_bm_2[7]) + ); + MUXF5 plm_des0_descram_reg_rx_des_dat_14_0_7_ ( + .I0(plm_des0_reg_rx_des_dat_14_0_am_2[7]), + .I1(plm_des0_reg_rx_des_dat_14_0_bm_2[7]), + .O(plm_des0_reg_rx_des_dat_14[7]), + .S(plm_des0_N_86080_i) + ); + defparam plm_des0_descram_reg_rx_des_dat_14_0_am_6_.INIT = 8'h65; + LUT3 plm_des0_descram_reg_rx_des_dat_14_0_am_6_ ( + .I0(plm_des0_reg_dat[6]), + .I1(plm_des0_reg_lfsr_one_9__936), + .I2(plm_des0_reg_skp[1]), + .O(plm_des0_reg_rx_des_dat_14_0_am_2[6]) + ); + defparam plm_des0_descram_reg_rx_des_dat_14_0_bm_6_.INIT = 8'h6C; + LUT3 plm_des0_descram_reg_rx_des_dat_14_0_bm_6_ ( + .I0(plm_des0_m1_0_a2_0_a3_0_a2_0_a2), + .I1(plm_des0_reg_dat[6]), + .I2(plm_des0_reg_lfsr_two_9__945), + .O(plm_des0_reg_rx_des_dat_14_0_bm_2[6]) + ); + MUXF5 plm_des0_descram_reg_rx_des_dat_14_0_6_ ( + .I0(plm_des0_reg_rx_des_dat_14_0_am_2[6]), + .I1(plm_des0_reg_rx_des_dat_14_0_bm_2[6]), + .O(plm_des0_reg_rx_des_dat_14[6]), + .S(plm_des0_N_86080_i) + ); + defparam plm_des0_descram_reg_rx_des_dat_14_0_am_5_.INIT = 8'h65; + LUT3 plm_des0_descram_reg_rx_des_dat_14_0_am_5_ ( + .I0(plm_des0_reg_dat[5]), + .I1(plm_des0_reg_lfsr_one_10__935), + .I2(plm_des0_reg_skp[1]), + .O(plm_des0_reg_rx_des_dat_14_0_am_2[5]) + ); + defparam plm_des0_descram_reg_rx_des_dat_14_0_bm_5_.INIT = 8'h6C; + LUT3 plm_des0_descram_reg_rx_des_dat_14_0_bm_5_ ( + .I0(plm_des0_m1_0_a2_0_a3_0_a2_0_a2), + .I1(plm_des0_reg_dat[5]), + .I2(plm_des0_reg_lfsr_two_10__944), + .O(plm_des0_reg_rx_des_dat_14_0_bm_2[5]) + ); + MUXF5 plm_des0_descram_reg_rx_des_dat_14_0_5_ ( + .I0(plm_des0_reg_rx_des_dat_14_0_am_2[5]), + .I1(plm_des0_reg_rx_des_dat_14_0_bm_2[5]), + .O(plm_des0_reg_rx_des_dat_14[5]), + .S(plm_des0_N_86080_i) + ); + defparam plm_des0_descram_reg_rx_des_dat_14_0_am_4_.INIT = 8'h65; + LUT3 plm_des0_descram_reg_rx_des_dat_14_0_am_4_ ( + .I0(plm_des0_reg_dat[4]), + .I1(plm_des0_reg_lfsr_one_11__563), + .I2(plm_des0_reg_skp[1]), + .O(plm_des0_reg_rx_des_dat_14_0_am_2[4]) + ); + defparam plm_des0_descram_reg_rx_des_dat_14_0_bm_4_.INIT = 8'h6C; + LUT3 plm_des0_descram_reg_rx_des_dat_14_0_bm_4_ ( + .I0(plm_des0_m1_0_a2_0_a3_0_a2_0_a2), + .I1(plm_des0_reg_dat[4]), + .I2(plm_des0_reg_lfsr_two_11__531), + .O(plm_des0_reg_rx_des_dat_14_0_bm_2[4]) + ); + MUXF5 plm_des0_descram_reg_rx_des_dat_14_0_4_ ( + .I0(plm_des0_reg_rx_des_dat_14_0_am_2[4]), + .I1(plm_des0_reg_rx_des_dat_14_0_bm_2[4]), + .O(plm_des0_reg_rx_des_dat_14[4]), + .S(plm_des0_N_86080_i) + ); + defparam plm_des0_descram_reg_rx_des_dat_14_0_am_3_.INIT = 8'h65; + LUT3 plm_des0_descram_reg_rx_des_dat_14_0_am_3_ ( + .I0(plm_des0_reg_dat[3]), + .I1(plm_des0_reg_lfsr_one_12__622), + .I2(plm_des0_reg_skp[1]), + .O(plm_des0_reg_rx_des_dat_14_0_am_2[3]) + ); + defparam plm_des0_descram_reg_rx_des_dat_14_0_bm_3_.INIT = 8'h6C; + LUT3 plm_des0_descram_reg_rx_des_dat_14_0_bm_3_ ( + .I0(plm_des0_m1_0_a2_0_a3_0_a2_0_a2), + .I1(plm_des0_reg_dat[3]), + .I2(plm_des0_reg_lfsr_two_12__943), + .O(plm_des0_reg_rx_des_dat_14_0_bm_2[3]) + ); + MUXF5 plm_des0_descram_reg_rx_des_dat_14_0_3_ ( + .I0(plm_des0_reg_rx_des_dat_14_0_am_2[3]), + .I1(plm_des0_reg_rx_des_dat_14_0_bm_2[3]), + .O(plm_des0_reg_rx_des_dat_14[3]), + .S(plm_des0_N_86080_i) + ); + defparam plm_des0_descram_reg_rx_des_dat_14_0_am_2_.INIT = 8'h65; + LUT3 plm_des0_descram_reg_rx_des_dat_14_0_am_2_ ( + .I0(plm_des0_reg_dat[2]), + .I1(plm_des0_reg_lfsr_one_13__567), + .I2(plm_des0_reg_skp[1]), + .O(plm_des0_reg_rx_des_dat_14_0_am_2[2]) + ); + defparam plm_des0_descram_reg_rx_des_dat_14_0_bm_2_.INIT = 8'h6C; + LUT3 plm_des0_descram_reg_rx_des_dat_14_0_bm_2_ ( + .I0(plm_des0_m1_0_a2_0_a3_0_a2_0_a2), + .I1(plm_des0_reg_dat[2]), + .I2(plm_des0_reg_lfsr_two_13__532), + .O(plm_des0_reg_rx_des_dat_14_0_bm_2[2]) + ); + MUXF5 plm_des0_descram_reg_rx_des_dat_14_0_2_ ( + .I0(plm_des0_reg_rx_des_dat_14_0_am_2[2]), + .I1(plm_des0_reg_rx_des_dat_14_0_bm_2[2]), + .O(plm_des0_reg_rx_des_dat_14[2]), + .S(plm_des0_N_86080_i) + ); + defparam plm_des0_descram_reg_rx_des_dat_14_0_am_1_.INIT = 8'h65; + LUT3 plm_des0_descram_reg_rx_des_dat_14_0_am_1_ ( + .I0(plm_des0_reg_dat[1]), + .I1(plm_des0_reg_lfsr_one_14__650), + .I2(plm_des0_reg_skp[1]), + .O(plm_des0_reg_rx_des_dat_14_0_am_2[1]) + ); + defparam plm_des0_descram_reg_rx_des_dat_14_0_bm_1_.INIT = 8'h6C; + LUT3 plm_des0_descram_reg_rx_des_dat_14_0_bm_1_ ( + .I0(plm_des0_m1_0_a2_0_a3_0_a2_0_a2), + .I1(plm_des0_reg_dat[1]), + .I2(plm_des0_reg_lfsr_two_14__649), + .O(plm_des0_reg_rx_des_dat_14_0_bm_2[1]) + ); + MUXF5 plm_des0_descram_reg_rx_des_dat_14_0_1_ ( + .I0(plm_des0_reg_rx_des_dat_14_0_am_2[1]), + .I1(plm_des0_reg_rx_des_dat_14_0_bm_2[1]), + .O(plm_des0_reg_rx_des_dat_14[1]), + .S(plm_des0_N_86080_i) + ); + defparam plm_des0_descram_reg_rx_des_dat_14_0_am_0_.INIT = 8'h65; + LUT3 plm_des0_descram_reg_rx_des_dat_14_0_am_0_ ( + .I0(plm_des0_reg_dat[0]), + .I1(plm_des0_reg_lfsr_one_15__564), + .I2(plm_des0_reg_skp[1]), + .O(plm_des0_reg_rx_des_dat_14_0_am_2[0]) + ); + defparam plm_des0_descram_reg_rx_des_dat_14_0_bm_0_.INIT = 8'h6C; + LUT3 plm_des0_descram_reg_rx_des_dat_14_0_bm_0_ ( + .I0(plm_des0_m1_0_a2_0_a3_0_a2_0_a2), + .I1(plm_des0_reg_dat[0]), + .I2(plm_des0_reg_lfsr_two_15__533), + .O(plm_des0_reg_rx_des_dat_14_0_bm_2[0]) + ); + MUXF5 plm_des0_descram_reg_rx_des_dat_14_0_0_ ( + .I0(plm_des0_reg_rx_des_dat_14_0_am_2[0]), + .I1(plm_des0_reg_rx_des_dat_14_0_bm_2[0]), + .O(plm_des0_reg_rx_des_dat_14[0]), + .S(plm_des0_N_86080_i) + ); + defparam plm_des0_one_adv2_3_.INIT = 8'h96; + LUT3 plm_des0_one_adv2_3_ ( + .I0(G_326_568), + .I1(G_415_623), + .I2(plm_des0_reg_lfsr_one_14__650), + .O(plm_des0_one_adv2[3]) + ); + defparam plm_des0_input_decoder_reg_bad_4_i_2_0_.INIT = 16'h080A; + LUT4_L plm_des0_input_decoder_reg_bad_4_i_2_0_ ( + .I0(plm_des0_reg_bad_4_i_1[0]), + .I1(plm_des0_reg_data[4]), + .I2(plm_des0_reg_nitbl[0]), + .I3(plm_des0_reg_spesh[0]), + .LO(plm_des0_reg_bad_4_i_2[0]) + ); + defparam plm_des0_input_decoder_reg_bad_3_i_2_1_.INIT = 16'h080A; + LUT4_L plm_des0_input_decoder_reg_bad_3_i_2_1_ ( + .I0(plm_des0_reg_bad_3_i_1[1]), + .I1(plm_des0_reg_data[12]), + .I2(plm_des0_reg_nitbl[1]), + .I3(plm_des0_reg_spesh[1]), + .LO(plm_des0_reg_bad_3_i_2[1]) + ); + defparam plm_des0_input_decoder_N_85316_i.INIT = 16'h7F0F; + LUT4_L plm_des0_input_decoder_N_85316_i ( + .I0(plm_des0_N_14319_i), + .I1(plm_des0_N_14320_i), + .I2(plm_des0_reg_bad_3_i_2[1]), + .I3(plm_des0_reg_spesh[1]), + .LO(plm_des0_N_85316_i) + ); + defparam plm_des0_input_decoder_N_85317_i.INIT = 16'h7F0F; + LUT4_L plm_des0_input_decoder_N_85317_i ( + .I0(plm_des0_N_14272_i), + .I1(plm_des0_N_14273_i), + .I2(plm_des0_reg_bad_4_i_2[0]), + .I3(plm_des0_reg_spesh[0]), + .LO(plm_des0_N_85317_i) + ); + defparam plm_des0_descram_N_49180_i_0_i.INIT = 8'h6C; + LUT3_L plm_des0_descram_N_49180_i_0_i ( + .I0(plm_des0_N_49067_i), + .I1(plm_des0_reg_dat[15]), + .I2(plm_des0_reg_lfsr_one_8__937), + .LO(plm_des0_N_49180_i_0_i) + ); + defparam plm_des0_descram_N_49178_i_0_i.INIT = 8'h6C; + LUT3_L plm_des0_descram_N_49178_i_0_i ( + .I0(plm_des0_N_49067_i), + .I1(plm_des0_reg_dat[14]), + .I2(plm_des0_reg_lfsr_one_9__936), + .LO(plm_des0_N_49178_i_0_i) + ); + defparam plm_des0_descram_N_49176_i_0_i.INIT = 8'h6C; + LUT3_L plm_des0_descram_N_49176_i_0_i ( + .I0(plm_des0_N_49067_i), + .I1(plm_des0_reg_dat[13]), + .I2(plm_des0_reg_lfsr_one_10__935), + .LO(plm_des0_N_49176_i_0_i) + ); + defparam plm_des0_descram_N_49174_i_0_i.INIT = 8'h6C; + LUT3_L plm_des0_descram_N_49174_i_0_i ( + .I0(plm_des0_N_49067_i), + .I1(plm_des0_reg_dat[12]), + .I2(plm_des0_reg_lfsr_one_11__563), + .LO(plm_des0_N_49174_i_0_i) + ); + defparam plm_des0_descram_N_49172_i_0_i.INIT = 8'h6C; + LUT3_L plm_des0_descram_N_49172_i_0_i ( + .I0(plm_des0_N_49067_i), + .I1(plm_des0_reg_dat[11]), + .I2(plm_des0_reg_lfsr_one_12__622), + .LO(plm_des0_N_49172_i_0_i) + ); + defparam plm_des0_descram_N_49170_i_0_i.INIT = 8'h6C; + LUT3_L plm_des0_descram_N_49170_i_0_i ( + .I0(plm_des0_N_49067_i), + .I1(plm_des0_reg_dat[10]), + .I2(plm_des0_reg_lfsr_one_13__567), + .LO(plm_des0_N_49170_i_0_i) + ); + defparam plm_des0_descram_N_49168_i_0_i.INIT = 8'h6C; + LUT3_L plm_des0_descram_N_49168_i_0_i ( + .I0(plm_des0_N_49067_i), + .I1(plm_des0_reg_dat[9]), + .I2(plm_des0_reg_lfsr_one_14__650), + .LO(plm_des0_N_49168_i_0_i) + ); + defparam plm_des0_descram_N_49166_i_0_i.INIT = 8'h6C; + LUT3_L plm_des0_descram_N_49166_i_0_i ( + .I0(plm_des0_N_49067_i), + .I1(plm_des0_reg_dat[8]), + .I2(plm_des0_reg_lfsr_one_15__564), + .LO(plm_des0_N_49166_i_0_i) + ); + defparam plm_des0_input_decoder_reg_stp_4_0_a7_0_.INIT = 16'h0800; + LUT4_L plm_des0_input_decoder_reg_stp_4_0_a7_0_ ( + .I0(plm_des0_reg_idl_4_1[0]), + .I1(plm_des0_reg_stp_4_0_a7_1_0_0[0]), + .I2(plm_des0_reg_data[2]), + .I3(plm_des0_reg_data[3]), + .LO(plm_des0_reg_stp_4[0]) + ); + defparam plm_des0_input_decoder_reg_skp_3_0_a7_1_.INIT = 16'h0008; + LUT4_L plm_des0_input_decoder_reg_skp_3_0_a7_1_ ( + .I0(plm_des0_reg_idl_3_2[1]), + .I1(plm_des0_reg_skp_3_0_a7_1_0[1]), + .I2(plm_des0_reg_data[14]), + .I3(plm_des0_reg_data[15]), + .LO(plm_des0_reg_skp_3[1]) + ); + defparam plm_des0_input_decoder_reg_skp_4_0_a7_0_.INIT = 16'h0008; + LUT4_L plm_des0_input_decoder_reg_skp_4_0_a7_0_ ( + .I0(plm_des0_reg_idl_4_2[0]), + .I1(plm_des0_reg_skp_4_0_a7_1_0[0]), + .I2(plm_des0_reg_data[6]), + .I3(plm_des0_reg_data[7]), + .LO(plm_des0_reg_skp_4[0]) + ); + defparam plm_des0_input_decoder_reg_sdp_3_0_a7_1_.INIT = 16'h0080; + LUT4_L plm_des0_input_decoder_reg_sdp_3_0_a7_1_ ( + .I0(plm_des0_reg_idl_3_2[1]), + .I1(plm_des0_reg_skp_3_0_a7_1_0[1]), + .I2(plm_des0_reg_data[14]), + .I3(plm_des0_reg_data[15]), + .LO(plm_des0_reg_sdp_3[1]) + ); + defparam plm_des0_input_decoder_reg_sdp_4_0_a7_0_.INIT = 16'h0080; + LUT4_L plm_des0_input_decoder_reg_sdp_4_0_a7_0_ ( + .I0(plm_des0_reg_idl_4_2[0]), + .I1(plm_des0_reg_skp_4_0_a7_1_0[0]), + .I2(plm_des0_reg_data[6]), + .I3(plm_des0_reg_data[7]), + .LO(plm_des0_reg_sdp_4[0]) + ); + defparam plm_des0_input_decoder_reg_pad_3_0_a7_1_.INIT = 16'h0080; + LUT4_L plm_des0_input_decoder_reg_pad_3_0_a7_1_ ( + .I0(plm_des0_reg_idl_3_1[1]), + .I1(plm_des0_reg_stp_3_0_a7_1_0_0[1]), + .I2(plm_des0_reg_data[10]), + .I3(plm_des0_reg_data[11]), + .LO(plm_des0_reg_pad_3[1]) + ); + defparam plm_des0_input_decoder_reg_pad_4_0_a7_0_.INIT = 16'h0080; + LUT4_L plm_des0_input_decoder_reg_pad_4_0_a7_0_ ( + .I0(plm_des0_reg_idl_4_1[0]), + .I1(plm_des0_reg_stp_4_0_a7_1_0_0[0]), + .I2(plm_des0_reg_data[2]), + .I3(plm_des0_reg_data[3]), + .LO(plm_des0_reg_pad_4[0]) + ); + defparam plm_des0_input_decoder_reg_idl_3_0_a7_1_.INIT = 16'h0080; + LUT4_L plm_des0_input_decoder_reg_idl_3_0_a7_1_ ( + .I0(plm_des0_reg_idl_3_1[1]), + .I1(plm_des0_reg_idl_3_2[1]), + .I2(plm_des0_reg_data[14]), + .I3(plm_des0_reg_data[15]), + .LO(plm_des0_reg_idl_3[1]) + ); + defparam plm_des0_input_decoder_reg_idl_4_0_a7_0_.INIT = 16'h0080; + LUT4_L plm_des0_input_decoder_reg_idl_4_0_a7_0_ ( + .I0(plm_des0_reg_idl_4_1[0]), + .I1(plm_des0_reg_idl_4_2[0]), + .I2(plm_des0_reg_data[6]), + .I3(plm_des0_reg_data[7]), + .LO(plm_des0_reg_idl_4[0]) + ); + defparam plm_des0_input_decoder_reg_fts_3_0_a7_1_.INIT = 16'h0008; + LUT4_L plm_des0_input_decoder_reg_fts_3_0_a7_1_ ( + .I0(plm_des0_reg_idl_3_1[1]), + .I1(plm_des0_reg_idl_3_2[1]), + .I2(plm_des0_reg_data[14]), + .I3(plm_des0_reg_data[15]), + .LO(plm_des0_reg_fts_3[1]) + ); + defparam plm_des0_input_decoder_reg_fts_4_0_a7_0_.INIT = 16'h0008; + LUT4_L plm_des0_input_decoder_reg_fts_4_0_a7_0_ ( + .I0(plm_des0_reg_idl_4_1[0]), + .I1(plm_des0_reg_idl_4_2[0]), + .I2(plm_des0_reg_data[6]), + .I3(plm_des0_reg_data[7]), + .LO(plm_des0_reg_fts_4[0]) + ); + defparam plm_des0_input_decoder_reg_edg_3_0_a7_1_.INIT = 16'h0080; + LUT4_L plm_des0_input_decoder_reg_edg_3_0_a7_1_ ( + .I0(plm_des0_reg_edg_3_0_a7_1_0_0[1]), + .I1(plm_des0_reg_idl_3_1[1]), + .I2(plm_des0_reg_data[8]), + .I3(plm_des0_reg_data[9]), + .LO(plm_des0_reg_edg_3[1]) + ); + defparam plm_des0_input_decoder_reg_edg_4_0_a7_0_.INIT = 16'h0080; + LUT4_L plm_des0_input_decoder_reg_edg_4_0_a7_0_ ( + .I0(plm_des0_reg_edg_4_0_a7_1_0_0[0]), + .I1(plm_des0_reg_idl_4_1[0]), + .I2(plm_des0_reg_data[0]), + .I3(plm_des0_reg_data[1]), + .LO(plm_des0_reg_edg_4[0]) + ); + defparam plm_des0_input_decoder_reg_edb_3_0_a7_1_.INIT = 16'h0800; + LUT4_L plm_des0_input_decoder_reg_edb_3_0_a7_1_ ( + .I0(plm_des0_reg_edg_3_0_a7_1_0_0[1]), + .I1(plm_des0_reg_idl_3_1[1]), + .I2(plm_des0_reg_data[8]), + .I3(plm_des0_reg_data[9]), + .LO(plm_des0_reg_edb_3[1]) + ); + defparam plm_des0_input_decoder_reg_edb_4_0_a7_0_.INIT = 16'h0800; + LUT4_L plm_des0_input_decoder_reg_edb_4_0_a7_0_ ( + .I0(plm_des0_reg_edg_4_0_a7_1_0_0[0]), + .I1(plm_des0_reg_idl_4_1[0]), + .I2(plm_des0_reg_data[0]), + .I3(plm_des0_reg_data[1]), + .LO(plm_des0_reg_edb_4[0]) + ); + defparam plm_des0_input_decoder_reg_com_3_0_a7_1_.INIT = 16'h0800; + LUT4_L plm_des0_input_decoder_reg_com_3_0_a7_1_ ( + .I0(plm_des0_reg_idl_3_1[1]), + .I1(plm_des0_reg_idl_3_2[1]), + .I2(plm_des0_reg_data[14]), + .I3(plm_des0_reg_data[15]), + .LO(plm_des0_reg_com_3[1]) + ); + defparam plm_des0_input_decoder_reg_com_4_0_a7_0_.INIT = 16'h0800; + LUT4_L plm_des0_input_decoder_reg_com_4_0_a7_0_ ( + .I0(plm_des0_reg_idl_4_1[0]), + .I1(plm_des0_reg_idl_4_2[0]), + .I2(plm_des0_reg_data[6]), + .I3(plm_des0_reg_data[7]), + .LO(plm_des0_reg_com_4[0]) + ); + defparam plm_des0_input_decoder_reg_stp_3_0_a7_1_.INIT = 16'h0800; + LUT4_L plm_des0_input_decoder_reg_stp_3_0_a7_1_ ( + .I0(plm_des0_reg_idl_3_1[1]), + .I1(plm_des0_reg_stp_3_0_a7_1_0_0[1]), + .I2(plm_des0_reg_data[10]), + .I3(plm_des0_reg_data[11]), + .LO(plm_des0_reg_stp_3[1]) + ); + defparam plm_des0_input_decoder_reg_t2n_4_0_a7_0_.INIT = 8'h80; + LUT3_L plm_des0_input_decoder_reg_t2n_4_0_a7_0_ ( + .I0(plm_des0_reg_sym_4[0]), + .I1(plm_des0_reg_t1n_4_1[0]), + .I2(plm_des0_reg_t1p_4_0_a7_2_0[0]), + .LO(plm_reg_t2n_4[0]) + ); + defparam plm_des0_input_decoder_reg_t1p_3_0_a7_1_.INIT = 8'h80; + LUT3_L plm_des0_input_decoder_reg_t1p_3_0_a7_1_ ( + .I0(plm_des0_reg_sym_3[1]), + .I1(plm_des0_reg_t2n_3_0_a7_1_0_0[1]), + .I2(plm_des0_reg_t2p_3_1_0[1]), + .LO(plm_des0_reg_t1p_3[1]) + ); + defparam plm_des0_input_decoder_reg_t1p_4_0_a7_0_.INIT = 8'h80; + LUT3_L plm_des0_input_decoder_reg_t1p_4_0_a7_0_ ( + .I0(plm_des0_reg_sym_4[0]), + .I1(plm_des0_reg_t1p_4_0_a7_2_0[0]), + .I2(plm_des0_reg_t1p_4_1[0]), + .LO(plm_reg_t1p_4[0]) + ); + defparam plm_des0_input_decoder_reg_t1n_3_0_a7_1_.INIT = 8'h80; + LUT3_L plm_des0_input_decoder_reg_t1n_3_0_a7_1_ ( + .I0(plm_des0_reg_sym_3[1]), + .I1(plm_des0_reg_t1n_3_0_a7_2_0[1]), + .I2(plm_des0_reg_t1n_3_1[1]), + .LO(plm_des0_reg_t1n_3[1]) + ); + defparam plm_des0_input_decoder_reg_t1n_4_0_a7_0_.INIT = 8'h80; + LUT3_L plm_des0_input_decoder_reg_t1n_4_0_a7_0_ ( + .I0(plm_des0_reg_sym_4[0]), + .I1(plm_des0_reg_t1n_4_0_a7_2_0[0]), + .I2(plm_des0_reg_t1n_4_1[0]), + .LO(plm_reg_t1n_4[0]) + ); + defparam plm_des0_input_decoder_reg_t2p_3_0_a7_1_.INIT = 8'h80; + LUT3_L plm_des0_input_decoder_reg_t2p_3_0_a7_1_ ( + .I0(plm_des0_reg_sym_3[1]), + .I1(plm_des0_reg_t1n_3_0_a7_2_0[1]), + .I2(plm_des0_reg_t2p_3_1_0[1]), + .LO(plm_des0_reg_t2p_3[1]) + ); + defparam plm_des0_input_decoder_reg_t2p_4_0_a7_0_.INIT = 8'h80; + LUT3_L plm_des0_input_decoder_reg_t2p_4_0_a7_0_ ( + .I0(plm_des0_reg_sym_4[0]), + .I1(plm_des0_reg_t1n_4_0_a7_2_0[0]), + .I2(plm_des0_reg_t1p_4_1[0]), + .LO(plm_reg_t2p_4[0]) + ); + defparam plm_des0_input_decoder_reg_t2n_3_0_a7_1_.INIT = 8'h80; + LUT3_L plm_des0_input_decoder_reg_t2n_3_0_a7_1_ ( + .I0(plm_des0_reg_sym_3[1]), + .I1(plm_des0_reg_t1n_3_1[1]), + .I2(plm_des0_reg_t2n_3_0_a7_1_0_0[1]), + .LO(plm_des0_reg_t2n_3[1]) + ); + defparam plm_des0_lfsrs_N_87707_i.INIT = 16'hF7B3; + LUT4_L plm_des0_lfsrs_N_87707_i ( + .I0(plm_des0_N_49056_i), + .I1(plm_des0_reg_lfsr_two_12_0_iv_0_0_0_o2[12]), + .I2(plm_des0_one_adv2[15]), + .I3(plm_des0_reg_lfsr_two_15__533), + .LO(plm_des0_N_87707_i) + ); + defparam plm_des0_lfsrs_N_87706_i.INIT = 16'hF7B3; + LUT4_L plm_des0_lfsrs_N_87706_i ( + .I0(plm_des0_N_49056_i), + .I1(plm_des0_reg_lfsr_two_12_0_iv_0_0_0_o2[12]), + .I2(plm_des0_one_adv2[14]), + .I3(plm_des0_reg_lfsr_two_14__649), + .LO(plm_des0_N_87706_i) + ); + defparam plm_des0_lfsrs_N_87705_i.INIT = 16'hF7B3; + LUT4_L plm_des0_lfsrs_N_87705_i ( + .I0(plm_des0_N_49056_i), + .I1(plm_des0_reg_lfsr_two_12_0_iv_0_0_0_o2[12]), + .I2(plm_des0_one_adv2[13]), + .I3(plm_des0_reg_lfsr_two_13__532), + .LO(plm_des0_N_87705_i) + ); + defparam plm_des0_lfsrs_N_85339_i.INIT = 16'hDFDD; + LUT4_L plm_des0_lfsrs_N_85339_i ( + .I0(plm_des0_N_49059_i), + .I1(plm_des0_reg_lfsr_one_12_iv_i_0_0_a2_0_12_), + .I2(plm_des0_reg_lfsr_two_12_iv_0_0_0_o4[9]), + .I3(plm_des0_reg_lfsr_two_12__943), + .LO(plm_des0_N_85339_i) + ); + defparam plm_des0_lfsrs_N_87704_i.INIT = 16'hF7B3; + LUT4_L plm_des0_lfsrs_N_87704_i ( + .I0(plm_des0_N_49056_i), + .I1(plm_des0_reg_lfsr_two_12_0_iv_0_0_0_o2[12]), + .I2(plm_des0_one_adv2[11]), + .I3(plm_des0_reg_lfsr_two_11__531), + .LO(plm_des0_N_87704_i) + ); + defparam plm_des0_lfsrs_N_85338_i.INIT = 16'hDFDD; + LUT4_L plm_des0_lfsrs_N_85338_i ( + .I0(plm_des0_N_49059_i), + .I1(plm_des0_reg_lfsr_one_12_iv_i_0_0_a2_0_10_), + .I2(plm_des0_reg_lfsr_two_12_iv_0_0_0_o4[9]), + .I3(plm_des0_reg_lfsr_two_10__944), + .LO(plm_des0_N_85338_i) + ); + defparam plm_des0_lfsrs_N_85337_i.INIT = 16'hDFDD; + LUT4_L plm_des0_lfsrs_N_85337_i ( + .I0(plm_des0_N_49059_i), + .I1(plm_des0_reg_lfsr_one_12_iv_i_0_0_a2_0_9_), + .I2(plm_des0_reg_lfsr_two_12_iv_0_0_0_o4[9]), + .I3(plm_des0_reg_lfsr_two_9__945), + .LO(plm_des0_N_85337_i) + ); + defparam plm_des0_lfsrs_N_85336_i.INIT = 16'hDFDD; + LUT4_L plm_des0_lfsrs_N_85336_i ( + .I0(plm_des0_N_49059_i), + .I1(plm_des0_reg_lfsr_one_12_iv_i_0_0_a2_0_8_), + .I2(plm_des0_reg_lfsr_two_12_iv_0_0_0_o4[9]), + .I3(plm_des0_reg_lfsr_two_8__946), + .LO(plm_des0_N_85336_i) + ); + defparam plm_des0_lfsrs_N_85335_i.INIT = 16'hDFDD; + LUT4_L plm_des0_lfsrs_N_85335_i ( + .I0(plm_des0_N_49059_i), + .I1(plm_des0_reg_lfsr_one_12_iv_i_0_0_a2_0_7_), + .I2(plm_des0_reg_lfsr_two_12_iv_0_0_0_o4[9]), + .I3(plm_des0_reg_lfsr_two_7__947), + .LO(plm_des0_N_85335_i) + ); + defparam plm_des0_lfsrs_N_85334_i.INIT = 16'hDFDD; + LUT4_L plm_des0_lfsrs_N_85334_i ( + .I0(plm_des0_N_49059_i), + .I1(plm_des0_reg_lfsr_one_12_iv_i_0_0_a2_0_6_), + .I2(plm_des0_reg_lfsr_two_12_iv_0_0_0_o4[9]), + .I3(plm_des0_reg_lfsr_two_6__948), + .LO(plm_des0_N_85334_i) + ); + defparam plm_des0_lfsrs_N_85333_i.INIT = 16'hDFDD; + LUT4_L plm_des0_lfsrs_N_85333_i ( + .I0(plm_des0_N_49059_i), + .I1(plm_des0_reg_lfsr_one_12_iv_i_0_0_a2_0_5_), + .I2(plm_des0_reg_lfsr_two_12_iv_0_0_0_o4[9]), + .I3(plm_des0_reg_lfsr_two_5__949), + .LO(plm_des0_N_85333_i) + ); + defparam plm_des0_lfsrs_N_87703_i.INIT = 16'hF7B3; + LUT4_L plm_des0_lfsrs_N_87703_i ( + .I0(plm_des0_N_49056_i), + .I1(plm_des0_reg_lfsr_two_12_0_iv_0_0_0_o2[12]), + .I2(plm_des0_one_adv2[4]), + .I3(plm_des0_reg_lfsr_two_4__651), + .LO(plm_des0_N_87703_i) + ); + defparam plm_des0_lfsrs_N_85332_i.INIT = 16'hFDDD; + LUT4_L plm_des0_lfsrs_N_85332_i ( + .I0(plm_des0_N_49059_i), + .I1(plm_des0_reg_lfsr_one_12_iv_i_0_0_a2[3]), + .I2(plm_des0_reg_lfsr_two_12_iv_0_0_0_a4_1_0[9]), + .I3(plm_des0_one_adv2[3]), + .LO(plm_des0_N_85332_i) + ); + defparam plm_des0_lfsrs_N_87702_i.INIT = 16'hF7B3; + LUT4_L plm_des0_lfsrs_N_87702_i ( + .I0(plm_des0_N_49056_i), + .I1(plm_des0_reg_lfsr_two_12_0_iv_0_0_0_o2[12]), + .I2(plm_des0_one_adv2[2]), + .I3(plm_des0_reg_lfsr_two_2__648), + .LO(plm_des0_N_87702_i) + ); + defparam plm_des0_lfsrs_N_87701_i.INIT = 16'hF7B3; + LUT4_L plm_des0_lfsrs_N_87701_i ( + .I0(plm_des0_N_49056_i), + .I1(plm_des0_reg_lfsr_two_12_0_iv_0_0_0_o2[12]), + .I2(plm_des0_one_adv2[1]), + .I3(plm_des0_reg_lfsr_two_1__647), + .LO(plm_des0_N_87701_i) + ); + defparam plm_des0_lfsrs_N_87664_i.INIT = 16'hDF8F; + LUT4_L plm_des0_lfsrs_N_87664_i ( + .I0(plm_des0_N_49056_i), + .I1(plm_des0_N_49079_i_0), + .I2(plm_des0_reg_lfsr_two_12_0_iv_0_0_0_o2[12]), + .I3(plm_des0_reg_lfsr_two_0__530), + .LO(plm_des0_N_87664_i) + ); + defparam plm_des0_lfsrs_N_85347_i.INIT = 16'hDFDD; + LUT4_L plm_des0_lfsrs_N_85347_i ( + .I0(plm_des0_N_49059_i), + .I1(plm_des0_reg_lfsr_two_12_iv_i_0_0_a2_0_15_), + .I2(plm_des0_reg_lfsr_two_12_iv_0_0_0_o4[9]), + .I3(plm_des0_one_adv2[15]), + .LO(plm_des0_N_85347_i) + ); + defparam plm_des0_lfsrs_N_85346_i.INIT = 16'hDFDD; + LUT4_L plm_des0_lfsrs_N_85346_i ( + .I0(plm_des0_N_49059_i), + .I1(plm_des0_reg_lfsr_two_12_iv_i_0_0_a2_0_14_), + .I2(plm_des0_reg_lfsr_two_12_iv_0_0_0_o4[9]), + .I3(plm_des0_one_adv2[14]), + .LO(plm_des0_N_85346_i) + ); + defparam plm_des0_lfsrs_N_85345_i.INIT = 16'hDFDD; + LUT4_L plm_des0_lfsrs_N_85345_i ( + .I0(plm_des0_N_49059_i), + .I1(plm_des0_reg_lfsr_two_12_iv_i_0_0_a2_0_13_), + .I2(plm_des0_reg_lfsr_two_12_iv_0_0_0_o4[9]), + .I3(plm_des0_one_adv2[13]), + .LO(plm_des0_N_85345_i) + ); + defparam plm_des0_lfsrs_reg_lfsr_two_12_0_iv_0_0_0_12_.INIT = 16'hC840; + LUT4_L plm_des0_lfsrs_reg_lfsr_two_12_0_iv_0_0_0_12_ ( + .I0(plm_des0_N_49056_i), + .I1(plm_des0_reg_lfsr_two_12_0_iv_0_0_0_o2[12]), + .I2(plm_des0_one_adv2[12]), + .I3(plm_des0_two_adv2_12__931), + .LO(plm_des0_N_9511_i) + ); + defparam plm_des0_lfsrs_N_85344_i.INIT = 16'hDFDD; + LUT4_L plm_des0_lfsrs_N_85344_i ( + .I0(plm_des0_N_49059_i), + .I1(plm_des0_reg_lfsr_two_12_iv_i_0_0_a2_0_11_), + .I2(plm_des0_reg_lfsr_two_12_iv_0_0_0_o4[9]), + .I3(plm_des0_one_adv2[11]), + .LO(plm_des0_N_85344_i) + ); + defparam plm_des0_lfsrs_reg_lfsr_two_12_0_iv_0_0_0_10_.INIT = 16'hC840; + LUT4_L plm_des0_lfsrs_reg_lfsr_two_12_0_iv_0_0_0_10_ ( + .I0(plm_des0_N_49056_i), + .I1(plm_des0_reg_lfsr_two_12_0_iv_0_0_0_o2[12]), + .I2(plm_des0_one_adv2[10]), + .I3(plm_des0_two_adv2_10__932), + .LO(plm_des0_N_9513_i) + ); + defparam plm_des0_lfsrs_reg_lfsr_two_12_iv_0_0_0_9_.INIT = 16'h2220; + LUT4_L plm_des0_lfsrs_reg_lfsr_two_12_iv_0_0_0_9_ ( + .I0(plm_des0_N_49059_i), + .I1(plm_des0_reg_lfsr_two_12_iv_0_0_0_a2_0_0_9_), + .I2(plm_des0_reg_lfsr_two_12_iv_0_0_0_o4[9]), + .I3(plm_des0_one_adv2[9]), + .LO(plm_des0_N_9514_i) + ); + defparam plm_des0_lfsrs_reg_lfsr_two_12_iv_0_0_0_8_.INIT = 16'h2220; + LUT4_L plm_des0_lfsrs_reg_lfsr_two_12_iv_0_0_0_8_ ( + .I0(plm_des0_N_49059_i), + .I1(plm_des0_reg_lfsr_two_12_iv_0_0_0_a2_0_0_8_), + .I2(plm_des0_reg_lfsr_two_12_iv_0_0_0_o4[9]), + .I3(plm_des0_one_adv2[8]), + .LO(plm_des0_N_9515_i) + ); + defparam plm_des0_lfsrs_reg_lfsr_two_12_0_iv_0_0_0_7_.INIT = 16'hC840; + LUT4_L plm_des0_lfsrs_reg_lfsr_two_12_0_iv_0_0_0_7_ ( + .I0(plm_des0_N_49056_i), + .I1(plm_des0_reg_lfsr_two_12_0_iv_0_0_0_o2[12]), + .I2(plm_des0_one_adv2[7]), + .I3(plm_des0_two_adv2_7__933), + .LO(plm_des0_N_9516_i) + ); + defparam plm_des0_lfsrs_reg_lfsr_two_12_0_iv_0_0_0_6_.INIT = 16'hC840; + LUT4_L plm_des0_lfsrs_reg_lfsr_two_12_0_iv_0_0_0_6_ ( + .I0(plm_des0_N_49056_i), + .I1(plm_des0_reg_lfsr_two_12_0_iv_0_0_0_o2[12]), + .I2(plm_des0_one_adv2[6]), + .I3(plm_des0_two_adv2_6__934), + .LO(plm_des0_N_9517_i) + ); + defparam plm_des0_lfsrs_reg_lfsr_two_12_iv_0_0_0_5_.INIT = 16'h2220; + LUT4_L plm_des0_lfsrs_reg_lfsr_two_12_iv_0_0_0_5_ ( + .I0(plm_des0_N_49059_i), + .I1(plm_des0_reg_lfsr_two_12_iv_0_0_0_a2_0_0_5_), + .I2(plm_des0_reg_lfsr_two_12_iv_0_0_0_o4[9]), + .I3(plm_des0_one_adv2[5]), + .LO(plm_des0_N_9518_i) + ); + defparam plm_des0_lfsrs_N_85343_i.INIT = 16'hDFDD; + LUT4_L plm_des0_lfsrs_N_85343_i ( + .I0(plm_des0_N_49059_i), + .I1(plm_des0_reg_lfsr_two_12_iv_i_0_0_a2_0_4_), + .I2(plm_des0_reg_lfsr_two_12_iv_0_0_0_o4[9]), + .I3(plm_des0_one_adv2[4]), + .LO(plm_des0_N_85343_i) + ); + defparam plm_des0_lfsrs_reg_lfsr_two_12_iv_0_0_0_3_.INIT = 16'h2220; + LUT4_L plm_des0_lfsrs_reg_lfsr_two_12_iv_0_0_0_3_ ( + .I0(plm_des0_N_49059_i), + .I1(plm_des0_reg_lfsr_two_12_iv_0_0_0_a2_0_0_3_), + .I2(plm_des0_reg_lfsr_two_12_iv_0_0_0_o4[9]), + .I3(plm_des0_one_adv2[3]), + .LO(plm_des0_N_9520_i) + ); + defparam plm_des0_lfsrs_N_85342_i.INIT = 16'hDFDD; + LUT4_L plm_des0_lfsrs_N_85342_i ( + .I0(plm_des0_N_49059_i), + .I1(plm_des0_reg_lfsr_two_12_iv_i_0_0_a2_0_2_), + .I2(plm_des0_reg_lfsr_two_12_iv_0_0_0_o4[9]), + .I3(plm_des0_one_adv2[2]), + .LO(plm_des0_N_85342_i) + ); + defparam plm_des0_lfsrs_N_85341_i.INIT = 16'hDFDD; + LUT4_L plm_des0_lfsrs_N_85341_i ( + .I0(plm_des0_N_49059_i), + .I1(plm_des0_reg_lfsr_two_12_iv_i_0_0_a2_0_1_), + .I2(plm_des0_reg_lfsr_two_12_iv_0_0_0_o4[9]), + .I3(plm_des0_one_adv2[1]), + .LO(plm_des0_N_85341_i) + ); + defparam plm_des0_lfsrs_N_85340_i.INIT = 16'hF5FD; + LUT4_L plm_des0_lfsrs_N_85340_i ( + .I0(plm_des0_N_49059_i), + .I1(plm_des0_N_49079_i_0), + .I2(plm_des0_reg_lfsr_two_12_iv_i_0_0_a2_0_0_), + .I3(plm_des0_reg_lfsr_two_12_iv_0_0_0_o4[9]), + .LO(plm_des0_N_85340_i) + ); + defparam plm_des0_lfsrs_reg_lfsr_two_12_iv_0_0_0_a4_1_9_.INIT = 8'h01; + LUT3 plm_des0_lfsrs_reg_lfsr_two_12_iv_0_0_0_a4_1_9_ ( + .I0(plm_des0_reg_com[1]), + .I1(plm_des0_reg_skp[1]), + .I2(plm_des0_reg_skp[0]), + .O(plm_des0_reg_lfsr_two_12_iv_0_0_0_a4_1_0[9]) + ); + FDC plm_des0_reg_dis ( + .C(mgt_clk), + .D(plm_reg_disdes), + .Q(plm_reg_dis), + .CLR(plm_rst) + ); + FDC plm_des0_reg_rx_des_fts_1_ ( + .C(mgt_clk), + .D(plm_des0_reg_fts[1]), + .Q(plm_rx0_des_fts[1]), + .CLR(plm_rst) + ); + FDC plm_des0_reg_rx_des_fts_0_ ( + .C(mgt_clk), + .D(plm_des0_reg_fts[0]), + .Q(plm_rx0_des_fts[0]), + .CLR(plm_rst) + ); + FDC plm_des0_reg_rx_des_edg_1_ ( + .C(mgt_clk), + .D(plm_des0_reg_edg[1]), + .Q(plm_rx0_des_edg[1]), + .CLR(plm_rst) + ); + FDC plm_des0_reg_rx_des_edg_0_ ( + .C(mgt_clk), + .D(plm_des0_reg_edg[0]), + .Q(plm_rx0_des_edg[0]), + .CLR(plm_rst) + ); + FDC plm_des0_reg_rx_des_dat_4_ ( + .C(mgt_clk), + .D(plm_des0_reg_rx_des_dat_14[4]), + .Q(plm_rx0_des_dat[4]), + .CLR(plm_rst) + ); + FDC plm_des0_reg_rx_des_dat_3_ ( + .C(mgt_clk), + .D(plm_des0_reg_rx_des_dat_14[3]), + .Q(plm_rx0_des_dat[3]), + .CLR(plm_rst) + ); + FDC plm_des0_reg_rx_des_dat_2_ ( + .C(mgt_clk), + .D(plm_des0_reg_rx_des_dat_14[2]), + .Q(plm_rx0_des_dat[2]), + .CLR(plm_rst) + ); + FDC plm_des0_reg_rx_des_dat_1_ ( + .C(mgt_clk), + .D(plm_des0_reg_rx_des_dat_14[1]), + .Q(plm_rx0_des_dat[1]), + .CLR(plm_rst) + ); + FDC plm_des0_reg_rx_des_dat_0_ ( + .C(mgt_clk), + .D(plm_des0_reg_rx_des_dat_14[0]), + .Q(plm_rx0_des_dat[0]), + .CLR(plm_rst) + ); + FDC plm_des0_reg_rx_des_stp_1_ ( + .C(mgt_clk), + .D(plm_des0_reg_stp[1]), + .Q(plm_rx0_des_stp[1]), + .CLR(plm_rst) + ); + FDC plm_des0_reg_rx_des_stp_0_ ( + .C(mgt_clk), + .D(plm_des0_reg_stp[0]), + .Q(plm_rx0_des_stp[0]), + .CLR(plm_rst) + ); + FDC plm_des0_reg_rx_des_skp_1_ ( + .C(mgt_clk), + .D(plm_des0_reg_skp[1]), + .Q(plm_rx0_des_skp[1]), + .CLR(plm_rst) + ); + FDC plm_des0_reg_rx_des_skp_0_ ( + .C(mgt_clk), + .D(plm_des0_reg_skp[0]), + .Q(plm_rx0_des_skp[0]), + .CLR(plm_rst) + ); + FDC plm_des0_reg_rx_des_sdp_1_ ( + .C(mgt_clk), + .D(plm_des0_reg_sdp[1]), + .Q(plm_rx0_des_sdp[1]), + .CLR(plm_rst) + ); + FDC plm_des0_reg_rx_des_sdp_0_ ( + .C(mgt_clk), + .D(plm_des0_reg_sdp[0]), + .Q(plm_rx0_des_sdp[0]), + .CLR(plm_rst) + ); + FDC plm_des0_reg_rx_des_pad_1_ ( + .C(mgt_clk), + .D(plm_des0_reg_pad[1]), + .Q(plm_rx0_des_pad[1]), + .CLR(plm_rst) + ); + FDC plm_des0_reg_rx_des_pad_0_ ( + .C(mgt_clk), + .D(plm_des0_reg_pad[0]), + .Q(plm_rx0_des_pad[0]), + .CLR(plm_rst) + ); + FDC plm_des0_reg_rx_des_idl_1_ ( + .C(mgt_clk), + .D(plm_des0_reg_idl[1]), + .Q(plm_rx0_des_idl[1]), + .CLR(plm_rst) + ); + FDC plm_des0_reg_rx_des_idl_0_ ( + .C(mgt_clk), + .D(plm_des0_reg_idl[0]), + .Q(plm_rx0_des_idl[0]), + .CLR(plm_rst) + ); + FDC plm_des0_reg_rx_des_bad_1_ ( + .C(mgt_clk), + .D(plm_des0_reg_bad[1]), + .Q(plm_rx0_des_bad[1]), + .CLR(plm_rst) + ); + FDC plm_des0_reg_rx_des_bad_0_ ( + .C(mgt_clk), + .D(plm_des0_reg_bad[0]), + .Q(plm_rx0_des_bad[0]), + .CLR(plm_rst) + ); + FDC plm_des0_reg_bad_1_ ( + .C(mgt_clk), + .D(plm_des0_N_85316_i), + .Q(plm_des0_reg_bad[1]), + .CLR(plm_rst) + ); + FDC plm_des0_reg_bad_0_ ( + .C(mgt_clk), + .D(plm_des0_N_85317_i), + .Q(plm_des0_reg_bad[0]), + .CLR(plm_rst) + ); + FDC plm_des0_reg_rx_des_dat_15_ ( + .C(mgt_clk), + .D(plm_des0_N_49180_i_0_i), + .Q(plm_rx0_des_dat[15]), + .CLR(plm_rst) + ); + FDC plm_des0_reg_rx_des_dat_14_ ( + .C(mgt_clk), + .D(plm_des0_N_49178_i_0_i), + .Q(plm_rx0_des_dat[14]), + .CLR(plm_rst) + ); + FDC plm_des0_reg_rx_des_dat_13_ ( + .C(mgt_clk), + .D(plm_des0_N_49176_i_0_i), + .Q(plm_rx0_des_dat[13]), + .CLR(plm_rst) + ); + FDC plm_des0_reg_rx_des_dat_12_ ( + .C(mgt_clk), + .D(plm_des0_N_49174_i_0_i), + .Q(plm_rx0_des_dat[12]), + .CLR(plm_rst) + ); + FDC plm_des0_reg_rx_des_dat_11_ ( + .C(mgt_clk), + .D(plm_des0_N_49172_i_0_i), + .Q(plm_rx0_des_dat[11]), + .CLR(plm_rst) + ); + FDC plm_des0_reg_rx_des_dat_10_ ( + .C(mgt_clk), + .D(plm_des0_N_49170_i_0_i), + .Q(plm_rx0_des_dat[10]), + .CLR(plm_rst) + ); + FDC plm_des0_reg_rx_des_dat_9_ ( + .C(mgt_clk), + .D(plm_des0_N_49168_i_0_i), + .Q(plm_rx0_des_dat[9]), + .CLR(plm_rst) + ); + FDC plm_des0_reg_rx_des_dat_8_ ( + .C(mgt_clk), + .D(plm_des0_N_49166_i_0_i), + .Q(plm_rx0_des_dat[8]), + .CLR(plm_rst) + ); + FDC plm_des0_reg_rx_des_dat_7_ ( + .C(mgt_clk), + .D(plm_des0_reg_rx_des_dat_14[7]), + .Q(plm_rx0_des_dat[7]), + .CLR(plm_rst) + ); + FDC plm_des0_reg_rx_des_dat_6_ ( + .C(mgt_clk), + .D(plm_des0_reg_rx_des_dat_14[6]), + .Q(plm_rx0_des_dat[6]), + .CLR(plm_rst) + ); + FDC plm_des0_reg_rx_des_dat_5_ ( + .C(mgt_clk), + .D(plm_des0_reg_rx_des_dat_14[5]), + .Q(plm_rx0_des_dat[5]), + .CLR(plm_rst) + ); + FDC plm_des0_reg_stp_0_ ( + .C(mgt_clk), + .D(plm_des0_reg_stp_4[0]), + .Q(plm_des0_reg_stp[0]), + .CLR(plm_rst) + ); + FDC plm_des0_reg_skp_1_ ( + .C(mgt_clk), + .D(plm_des0_reg_skp_3[1]), + .Q(plm_des0_reg_skp[1]), + .CLR(plm_rst) + ); + FDC plm_des0_reg_skp_0_ ( + .C(mgt_clk), + .D(plm_des0_reg_skp_4[0]), + .Q(plm_des0_reg_skp[0]), + .CLR(plm_rst) + ); + FDC plm_des0_reg_sdp_1_ ( + .C(mgt_clk), + .D(plm_des0_reg_sdp_3[1]), + .Q(plm_des0_reg_sdp[1]), + .CLR(plm_rst) + ); + FDC plm_des0_reg_sdp_0_ ( + .C(mgt_clk), + .D(plm_des0_reg_sdp_4[0]), + .Q(plm_des0_reg_sdp[0]), + .CLR(plm_rst) + ); + FDC plm_des0_reg_pad_1_ ( + .C(mgt_clk), + .D(plm_des0_reg_pad_3[1]), + .Q(plm_des0_reg_pad[1]), + .CLR(plm_rst) + ); + FDC plm_des0_reg_pad_0_ ( + .C(mgt_clk), + .D(plm_des0_reg_pad_4[0]), + .Q(plm_des0_reg_pad[0]), + .CLR(plm_rst) + ); + FDC plm_des0_reg_idl_1_ ( + .C(mgt_clk), + .D(plm_des0_reg_idl_3[1]), + .Q(plm_des0_reg_idl[1]), + .CLR(plm_rst) + ); + FDC plm_des0_reg_idl_0_ ( + .C(mgt_clk), + .D(plm_des0_reg_idl_4[0]), + .Q(plm_des0_reg_idl[0]), + .CLR(plm_rst) + ); + FDC plm_des0_reg_fts_1_ ( + .C(mgt_clk), + .D(plm_des0_reg_fts_3[1]), + .Q(plm_des0_reg_fts[1]), + .CLR(plm_rst) + ); + FDC plm_des0_reg_fts_0_ ( + .C(mgt_clk), + .D(plm_des0_reg_fts_4[0]), + .Q(plm_des0_reg_fts[0]), + .CLR(plm_rst) + ); + FDC plm_des0_reg_edg_1_ ( + .C(mgt_clk), + .D(plm_des0_reg_edg_3[1]), + .Q(plm_des0_reg_edg[1]), + .CLR(plm_rst) + ); + FDC plm_des0_reg_edg_0_ ( + .C(mgt_clk), + .D(plm_des0_reg_edg_4[0]), + .Q(plm_des0_reg_edg[0]), + .CLR(plm_rst) + ); + FDC plm_des0_reg_edb_1_ ( + .C(mgt_clk), + .D(plm_des0_reg_edb_3[1]), + .Q(plm_des0_reg_edb[1]), + .CLR(plm_rst) + ); + FDC plm_des0_reg_edb_0_ ( + .C(mgt_clk), + .D(plm_des0_reg_edb_4[0]), + .Q(plm_des0_reg_edb[0]), + .CLR(plm_rst) + ); + FDC plm_des0_reg_com_1_ ( + .C(mgt_clk), + .D(plm_des0_reg_com_3[1]), + .Q(plm_des0_reg_com[1]), + .CLR(plm_rst) + ); + FDC plm_des0_reg_com_0_ ( + .C(mgt_clk), + .D(plm_des0_reg_com_4[0]), + .Q(plm_des0_reg_com[0]), + .CLR(plm_rst) + ); + FDC plm_des0_reg_rx_des_t2p_1_ ( + .C(mgt_clk), + .D(plm_des0_reg_t2p[1]), + .Q(plm_rx0_des_t2p[1]), + .CLR(plm_rst) + ); + FDC plm_des0_reg_rx_des_t2n_1_ ( + .C(mgt_clk), + .D(plm_des0_reg_t2n[1]), + .Q(plm_rx0_des_t2n[1]), + .CLR(plm_rst) + ); + FDC plm_des0_reg_rx_des_t1p_1_ ( + .C(mgt_clk), + .D(plm_des0_reg_t1p[1]), + .Q(plm_rx0_des_t1p[1]), + .CLR(plm_rst) + ); + FDC plm_des0_reg_rx_des_t1n_1_ ( + .C(mgt_clk), + .D(plm_des0_reg_t1n[1]), + .Q(plm_rx0_des_t1n[1]), + .CLR(plm_rst) + ); + FDC plm_des0_reg_rx_des_edb_1_ ( + .C(mgt_clk), + .D(plm_des0_reg_edb[1]), + .Q(plm_rx0_des_edb[1]), + .CLR(plm_rst) + ); + FDC plm_des0_reg_rx_des_edb_0_ ( + .C(mgt_clk), + .D(plm_des0_reg_edb[0]), + .Q(plm_rx0_des_edb[0]), + .CLR(plm_rst) + ); + FDC plm_des0_reg_rx_des_com_1_ ( + .C(mgt_clk), + .D(plm_des0_reg_com[1]), + .Q(plm_rx0_des_com[1]), + .CLR(plm_rst) + ); + FDC plm_des0_reg_rx_des_com_0_ ( + .C(mgt_clk), + .D(plm_des0_reg_com[0]), + .Q(plm_rx0_des_com[0]), + .CLR(plm_rst) + ); + FDC plm_des0_reg_stp_1_ ( + .C(mgt_clk), + .D(plm_des0_reg_stp_3[1]), + .Q(plm_des0_reg_stp[1]), + .CLR(plm_rst) + ); + FDC plm_des0_reg_t1p_1_ ( + .C(mgt_clk), + .D(plm_des0_reg_t1p_3[1]), + .Q(plm_des0_reg_t1p[1]), + .CLR(plm_rst) + ); + FDC plm_des0_reg_t1n_1_ ( + .C(mgt_clk), + .D(plm_des0_reg_t1n_3[1]), + .Q(plm_des0_reg_t1n[1]), + .CLR(plm_rst) + ); + FDC plm_des0_reg_rx_des_sym_1_ ( + .C(mgt_clk), + .D(plm_des0_reg_sym[1]), + .Q(plm_rx0_des_sym[1]), + .CLR(plm_rst) + ); + FDC plm_des0_reg_rx_des_sym_0_ ( + .C(mgt_clk), + .D(plm_des0_reg_sym[0]), + .Q(plm_rx0_des_sym[0]), + .CLR(plm_rst) + ); + FDC plm_des0_reg_rx_raw_dat_9_ ( + .C(mgt_clk), + .D(plm_des0_reg_dat[9]), + .Q(plm_rx0_raw_dat[9]), + .CLR(plm_rst) + ); + FDC plm_des0_reg_rx_raw_dat_8_ ( + .C(mgt_clk), + .D(plm_des0_reg_dat[8]), + .Q(plm_rx0_raw_dat[8]), + .CLR(plm_rst) + ); + FDC plm_des0_reg_rx_raw_dat_7_ ( + .C(mgt_clk), + .D(plm_des0_reg_dat[7]), + .Q(plm_rx0_raw_dat[7]), + .CLR(plm_rst) + ); + FDC plm_des0_reg_rx_raw_dat_6_ ( + .C(mgt_clk), + .D(plm_des0_reg_dat[6]), + .Q(plm_rx0_raw_dat[6]), + .CLR(plm_rst) + ); + FDC plm_des0_reg_rx_raw_dat_5_ ( + .C(mgt_clk), + .D(plm_des0_reg_dat[5]), + .Q(plm_rx0_raw_dat[5]), + .CLR(plm_rst) + ); + FDC plm_des0_reg_rx_raw_dat_4_ ( + .C(mgt_clk), + .D(plm_des0_reg_dat[4]), + .Q(plm_rx0_raw_dat[4]), + .CLR(plm_rst) + ); + FDC plm_des0_reg_rx_raw_dat_3_ ( + .C(mgt_clk), + .D(plm_des0_reg_dat[3]), + .Q(plm_rx0_raw_dat[3]), + .CLR(plm_rst) + ); + FDC plm_des0_reg_rx_raw_dat_2_ ( + .C(mgt_clk), + .D(plm_des0_reg_dat[2]), + .Q(plm_rx0_raw_dat[2]), + .CLR(plm_rst) + ); + FDC plm_des0_reg_rx_raw_dat_1_ ( + .C(mgt_clk), + .D(plm_des0_reg_dat[1]), + .Q(plm_rx0_raw_dat[1]), + .CLR(plm_rst) + ); + FDC plm_des0_reg_rx_raw_dat_0_ ( + .C(mgt_clk), + .D(plm_des0_reg_dat[0]), + .Q(plm_rx0_raw_dat[0]), + .CLR(plm_rst) + ); + FDC plm_des0_reg_sym_1_ ( + .C(mgt_clk), + .D(plm_des0_reg_sym_3[1]), + .Q(plm_des0_reg_sym[1]), + .CLR(plm_rst) + ); + FDC plm_des0_reg_sym_0_ ( + .C(mgt_clk), + .D(plm_des0_reg_sym_4[0]), + .Q(plm_des0_reg_sym[0]), + .CLR(plm_rst) + ); + FDC plm_des0_reg_t2p_1_ ( + .C(mgt_clk), + .D(plm_des0_reg_t2p_3[1]), + .Q(plm_des0_reg_t2p[1]), + .CLR(plm_rst) + ); + FDC plm_des0_reg_t2n_1_ ( + .C(mgt_clk), + .D(plm_des0_reg_t2n_3[1]), + .Q(plm_des0_reg_t2n[1]), + .CLR(plm_rst) + ); + FDC plm_des0_reg_data_4_ ( + .C(mgt_clk), + .D(plm_rx0_data[4]), + .Q(plm_des0_reg_data[4]), + .CLR(plm_rst) + ); + FDC plm_des0_reg_data_3_ ( + .C(mgt_clk), + .D(plm_rx0_data[3]), + .Q(plm_des0_reg_data[3]), + .CLR(plm_rst) + ); + FDC plm_des0_reg_data_2_ ( + .C(mgt_clk), + .D(plm_rx0_data[2]), + .Q(plm_des0_reg_data[2]), + .CLR(plm_rst) + ); + FDC plm_des0_reg_data_1_ ( + .C(mgt_clk), + .D(plm_rx0_data[1]), + .Q(plm_des0_reg_data[1]), + .CLR(plm_rst) + ); + FDC plm_des0_reg_data_0_ ( + .C(mgt_clk), + .D(plm_rx0_data[0]), + .Q(plm_des0_reg_data[0]), + .CLR(plm_rst) + ); + FDC plm_des0_reg_spesh_1_ ( + .C(mgt_clk), + .D(plm_rx0_char_is_k[1]), + .Q(plm_des0_reg_spesh[1]), + .CLR(plm_rst) + ); + FDC plm_des0_reg_spesh_0_ ( + .C(mgt_clk), + .D(plm_rx0_char_is_k[0]), + .Q(plm_des0_reg_spesh[0]), + .CLR(plm_rst) + ); + FDC plm_des0_reg_nitbl_1_ ( + .C(mgt_clk), + .D(plm_rx0_not_in_table[1]), + .Q(plm_des0_reg_nitbl[1]), + .CLR(plm_rst) + ); + FDC plm_des0_reg_nitbl_0_ ( + .C(mgt_clk), + .D(plm_rx0_not_in_table[0]), + .Q(plm_des0_reg_nitbl[0]), + .CLR(plm_rst) + ); + FDC plm_des0_reg_rx_raw_dat_15_ ( + .C(mgt_clk), + .D(plm_des0_reg_dat[15]), + .Q(plm_rx0_raw_dat[15]), + .CLR(plm_rst) + ); + FDC plm_des0_reg_rx_raw_dat_14_ ( + .C(mgt_clk), + .D(plm_des0_reg_dat[14]), + .Q(plm_rx0_raw_dat[14]), + .CLR(plm_rst) + ); + FDC plm_des0_reg_rx_raw_dat_13_ ( + .C(mgt_clk), + .D(plm_des0_reg_dat[13]), + .Q(plm_rx0_raw_dat[13]), + .CLR(plm_rst) + ); + FDC plm_des0_reg_rx_raw_dat_12_ ( + .C(mgt_clk), + .D(plm_des0_reg_dat[12]), + .Q(plm_rx0_raw_dat[12]), + .CLR(plm_rst) + ); + FDC plm_des0_reg_rx_raw_dat_11_ ( + .C(mgt_clk), + .D(plm_des0_reg_dat[11]), + .Q(plm_rx0_raw_dat[11]), + .CLR(plm_rst) + ); + FDC plm_des0_reg_rx_raw_dat_10_ ( + .C(mgt_clk), + .D(plm_des0_reg_dat[10]), + .Q(plm_rx0_raw_dat[10]), + .CLR(plm_rst) + ); + FDC plm_des0_reg_dat_1_ ( + .C(mgt_clk), + .D(plm_des0_reg_data[1]), + .Q(plm_des0_reg_dat[1]), + .CLR(plm_rst) + ); + FDC plm_des0_reg_dat_0_ ( + .C(mgt_clk), + .D(plm_des0_reg_data[0]), + .Q(plm_des0_reg_dat[0]), + .CLR(plm_rst) + ); + FDC plm_des0_reg_kkk_1_ ( + .C(mgt_clk), + .D(plm_des0_reg_spesh[1]), + .Q(plm_des0_reg_kkk[1]), + .CLR(plm_rst) + ); + FDC plm_des0_reg_kkk_0_ ( + .C(mgt_clk), + .D(plm_des0_reg_spesh[0]), + .Q(plm_des0_reg_kkk[0]), + .CLR(plm_rst) + ); + FDC plm_des0_reg_data_15_ ( + .C(mgt_clk), + .D(plm_rx0_data[15]), + .Q(plm_des0_reg_data[15]), + .CLR(plm_rst) + ); + FDC plm_des0_reg_data_14_ ( + .C(mgt_clk), + .D(plm_rx0_data[14]), + .Q(plm_des0_reg_data[14]), + .CLR(plm_rst) + ); + FDC plm_des0_reg_data_13_ ( + .C(mgt_clk), + .D(plm_rx0_data[13]), + .Q(plm_des0_reg_data[13]), + .CLR(plm_rst) + ); + FDC plm_des0_reg_data_12_ ( + .C(mgt_clk), + .D(plm_rx0_data[12]), + .Q(plm_des0_reg_data[12]), + .CLR(plm_rst) + ); + FDC plm_des0_reg_data_11_ ( + .C(mgt_clk), + .D(plm_rx0_data[11]), + .Q(plm_des0_reg_data[11]), + .CLR(plm_rst) + ); + FDC plm_des0_reg_data_10_ ( + .C(mgt_clk), + .D(plm_rx0_data[10]), + .Q(plm_des0_reg_data[10]), + .CLR(plm_rst) + ); + FDC plm_des0_reg_data_9_ ( + .C(mgt_clk), + .D(plm_rx0_data[9]), + .Q(plm_des0_reg_data[9]), + .CLR(plm_rst) + ); + FDC plm_des0_reg_data_8_ ( + .C(mgt_clk), + .D(plm_rx0_data[8]), + .Q(plm_des0_reg_data[8]), + .CLR(plm_rst) + ); + FDC plm_des0_reg_data_7_ ( + .C(mgt_clk), + .D(plm_rx0_data[7]), + .Q(plm_des0_reg_data[7]), + .CLR(plm_rst) + ); + FDC plm_des0_reg_data_6_ ( + .C(mgt_clk), + .D(plm_rx0_data[6]), + .Q(plm_des0_reg_data[6]), + .CLR(plm_rst) + ); + FDC plm_des0_reg_data_5_ ( + .C(mgt_clk), + .D(plm_rx0_data[5]), + .Q(plm_des0_reg_data[5]), + .CLR(plm_rst) + ); + FDC plm_des0_reg_dat_15_ ( + .C(mgt_clk), + .D(plm_des0_reg_data[15]), + .Q(plm_des0_reg_dat[15]), + .CLR(plm_rst) + ); + FDC plm_des0_reg_dat_14_ ( + .C(mgt_clk), + .D(plm_des0_reg_data[14]), + .Q(plm_des0_reg_dat[14]), + .CLR(plm_rst) + ); + FDC plm_des0_reg_dat_13_ ( + .C(mgt_clk), + .D(plm_des0_reg_data[13]), + .Q(plm_des0_reg_dat[13]), + .CLR(plm_rst) + ); + FDC plm_des0_reg_dat_12_ ( + .C(mgt_clk), + .D(plm_des0_reg_data[12]), + .Q(plm_des0_reg_dat[12]), + .CLR(plm_rst) + ); + FDC plm_des0_reg_dat_11_ ( + .C(mgt_clk), + .D(plm_des0_reg_data[11]), + .Q(plm_des0_reg_dat[11]), + .CLR(plm_rst) + ); + FDC plm_des0_reg_dat_10_ ( + .C(mgt_clk), + .D(plm_des0_reg_data[10]), + .Q(plm_des0_reg_dat[10]), + .CLR(plm_rst) + ); + FDC plm_des0_reg_dat_9_ ( + .C(mgt_clk), + .D(plm_des0_reg_data[9]), + .Q(plm_des0_reg_dat[9]), + .CLR(plm_rst) + ); + FDC plm_des0_reg_dat_8_ ( + .C(mgt_clk), + .D(plm_des0_reg_data[8]), + .Q(plm_des0_reg_dat[8]), + .CLR(plm_rst) + ); + FDC plm_des0_reg_dat_7_ ( + .C(mgt_clk), + .D(plm_des0_reg_data[7]), + .Q(plm_des0_reg_dat[7]), + .CLR(plm_rst) + ); + FDC plm_des0_reg_dat_6_ ( + .C(mgt_clk), + .D(plm_des0_reg_data[6]), + .Q(plm_des0_reg_dat[6]), + .CLR(plm_rst) + ); + FDC plm_des0_reg_dat_5_ ( + .C(mgt_clk), + .D(plm_des0_reg_data[5]), + .Q(plm_des0_reg_dat[5]), + .CLR(plm_rst) + ); + FDC plm_des0_reg_dat_4_ ( + .C(mgt_clk), + .D(plm_des0_reg_data[4]), + .Q(plm_des0_reg_dat[4]), + .CLR(plm_rst) + ); + FDC plm_des0_reg_dat_3_ ( + .C(mgt_clk), + .D(plm_des0_reg_data[3]), + .Q(plm_des0_reg_dat[3]), + .CLR(plm_rst) + ); + FDC plm_des0_reg_dat_2_ ( + .C(mgt_clk), + .D(plm_des0_reg_data[2]), + .Q(plm_des0_reg_dat[2]), + .CLR(plm_rst) + ); + FDPE plm_des0_reg_lfsr_one_15_ ( + .PRE(plm_rst), + .CE(plm_des0_reg_lfsr_one32_i), + .C(mgt_clk), + .D(plm_des0_N_87707_i), + .Q(plm_des0_reg_lfsr_one_15__564) + ); + FDPE plm_des0_reg_lfsr_one_14_ ( + .PRE(plm_rst), + .CE(plm_des0_reg_lfsr_one32_i), + .C(mgt_clk), + .D(plm_des0_N_87706_i), + .Q(plm_des0_reg_lfsr_one_14__650) + ); + FDPE plm_des0_reg_lfsr_one_13_ ( + .PRE(plm_rst), + .CE(plm_des0_reg_lfsr_one32_i), + .C(mgt_clk), + .D(plm_des0_N_87705_i), + .Q(plm_des0_reg_lfsr_one_13__567) + ); + FDPE plm_des0_reg_lfsr_one_12_ ( + .PRE(plm_rst), + .CE(plm_des0_reg_lfsr_one32_i), + .C(mgt_clk), + .D(plm_des0_N_85339_i), + .Q(plm_des0_reg_lfsr_one_12__622) + ); + FDPE plm_des0_reg_lfsr_one_11_ ( + .PRE(plm_rst), + .CE(plm_des0_reg_lfsr_one32_i), + .C(mgt_clk), + .D(plm_des0_N_87704_i), + .Q(plm_des0_reg_lfsr_one_11__563) + ); + FDPE plm_des0_reg_lfsr_one_10_ ( + .PRE(plm_rst), + .CE(plm_des0_reg_lfsr_one32_i), + .C(mgt_clk), + .D(plm_des0_N_85338_i), + .Q(plm_des0_reg_lfsr_one_10__935) + ); + FDPE plm_des0_reg_lfsr_one_9_ ( + .PRE(plm_rst), + .CE(plm_des0_reg_lfsr_one32_i), + .C(mgt_clk), + .D(plm_des0_N_85337_i), + .Q(plm_des0_reg_lfsr_one_9__936) + ); + FDPE plm_des0_reg_lfsr_one_8_ ( + .PRE(plm_rst), + .CE(plm_des0_reg_lfsr_one32_i), + .C(mgt_clk), + .D(plm_des0_N_85336_i), + .Q(plm_des0_reg_lfsr_one_8__937) + ); + FDPE plm_des0_reg_lfsr_one_7_ ( + .PRE(plm_rst), + .CE(plm_des0_reg_lfsr_one32_i), + .C(mgt_clk), + .D(plm_des0_N_85335_i), + .Q(plm_des0_reg_lfsr_one_7__938) + ); + FDPE plm_des0_reg_lfsr_one_6_ ( + .PRE(plm_rst), + .CE(plm_des0_reg_lfsr_one32_i), + .C(mgt_clk), + .D(plm_des0_N_85334_i), + .Q(plm_des0_reg_lfsr_one_6__939) + ); + FDPE plm_des0_reg_lfsr_one_5_ ( + .PRE(plm_rst), + .CE(plm_des0_reg_lfsr_one32_i), + .C(mgt_clk), + .D(plm_des0_N_85333_i), + .Q(plm_des0_reg_lfsr_one_5__940) + ); + FDPE plm_des0_reg_lfsr_one_4_ ( + .PRE(plm_rst), + .CE(plm_des0_reg_lfsr_one32_i), + .C(mgt_clk), + .D(plm_des0_N_87703_i), + .Q(plm_des0_reg_lfsr_one_4__941) + ); + FDPE plm_des0_reg_lfsr_one_3_ ( + .PRE(plm_rst), + .CE(plm_des0_reg_lfsr_one32_i), + .C(mgt_clk), + .D(plm_des0_N_85332_i), + .Q(plm_des0_reg_lfsr_one_3__566) + ); + FDPE plm_des0_reg_lfsr_one_2_ ( + .PRE(plm_rst), + .CE(plm_des0_reg_lfsr_one32_i), + .C(mgt_clk), + .D(plm_des0_N_87702_i), + .Q(plm_des0_reg_lfsr_one_2__942) + ); + FDPE plm_des0_reg_lfsr_one_1_ ( + .PRE(plm_rst), + .CE(plm_des0_reg_lfsr_one32_i), + .C(mgt_clk), + .D(plm_des0_N_87701_i), + .Q(plm_des0_reg_lfsr_one_1__562) + ); + FDPE plm_des0_reg_lfsr_one_0_ ( + .PRE(plm_rst), + .CE(plm_des0_reg_lfsr_one32_i), + .C(mgt_clk), + .D(plm_des0_N_87664_i), + .Q(plm_des0_reg_lfsr_one_0__561) + ); + FDPE plm_des0_reg_lfsr_two_15_ ( + .PRE(plm_rst), + .CE(plm_des0_reg_lfsr_one32_i), + .C(mgt_clk), + .D(plm_des0_N_85347_i), + .Q(plm_des0_reg_lfsr_two_15__533) + ); + FDPE plm_des0_reg_lfsr_two_14_ ( + .PRE(plm_rst), + .CE(plm_des0_reg_lfsr_one32_i), + .C(mgt_clk), + .D(plm_des0_N_85346_i), + .Q(plm_des0_reg_lfsr_two_14__649) + ); + FDPE plm_des0_reg_lfsr_two_13_ ( + .PRE(plm_rst), + .CE(plm_des0_reg_lfsr_one32_i), + .C(mgt_clk), + .D(plm_des0_N_85345_i), + .Q(plm_des0_reg_lfsr_two_13__532) + ); + FDCE plm_des0_reg_lfsr_two_12_ ( + .CE(plm_des0_reg_lfsr_one32_i), + .C(mgt_clk), + .D(plm_des0_N_9511_i), + .Q(plm_des0_reg_lfsr_two_12__943), + .CLR(plm_rst) + ); + FDPE plm_des0_reg_lfsr_two_11_ ( + .PRE(plm_rst), + .CE(plm_des0_reg_lfsr_one32_i), + .C(mgt_clk), + .D(plm_des0_N_85344_i), + .Q(plm_des0_reg_lfsr_two_11__531) + ); + FDCE plm_des0_reg_lfsr_two_10_ ( + .CE(plm_des0_reg_lfsr_one32_i), + .C(mgt_clk), + .D(plm_des0_N_9513_i), + .Q(plm_des0_reg_lfsr_two_10__944), + .CLR(plm_rst) + ); + FDCE plm_des0_reg_lfsr_two_9_ ( + .CE(plm_des0_reg_lfsr_one32_i), + .C(mgt_clk), + .D(plm_des0_N_9514_i), + .Q(plm_des0_reg_lfsr_two_9__945), + .CLR(plm_rst) + ); + FDCE plm_des0_reg_lfsr_two_8_ ( + .CE(plm_des0_reg_lfsr_one32_i), + .C(mgt_clk), + .D(plm_des0_N_9515_i), + .Q(plm_des0_reg_lfsr_two_8__946), + .CLR(plm_rst) + ); + FDCE plm_des0_reg_lfsr_two_7_ ( + .CE(plm_des0_reg_lfsr_one32_i), + .C(mgt_clk), + .D(plm_des0_N_9516_i), + .Q(plm_des0_reg_lfsr_two_7__947), + .CLR(plm_rst) + ); + FDCE plm_des0_reg_lfsr_two_6_ ( + .CE(plm_des0_reg_lfsr_one32_i), + .C(mgt_clk), + .D(plm_des0_N_9517_i), + .Q(plm_des0_reg_lfsr_two_6__948), + .CLR(plm_rst) + ); + FDCE plm_des0_reg_lfsr_two_5_ ( + .CE(plm_des0_reg_lfsr_one32_i), + .C(mgt_clk), + .D(plm_des0_N_9518_i), + .Q(plm_des0_reg_lfsr_two_5__949), + .CLR(plm_rst) + ); + FDPE plm_des0_reg_lfsr_two_4_ ( + .PRE(plm_rst), + .CE(plm_des0_reg_lfsr_one32_i), + .C(mgt_clk), + .D(plm_des0_N_85343_i), + .Q(plm_des0_reg_lfsr_two_4__651) + ); + FDCE plm_des0_reg_lfsr_two_3_ ( + .CE(plm_des0_reg_lfsr_one32_i), + .C(mgt_clk), + .D(plm_des0_N_9520_i), + .Q(plm_des0_reg_lfsr_two_3__950), + .CLR(plm_rst) + ); + FDPE plm_des0_reg_lfsr_two_2_ ( + .PRE(plm_rst), + .CE(plm_des0_reg_lfsr_one32_i), + .C(mgt_clk), + .D(plm_des0_N_85342_i), + .Q(plm_des0_reg_lfsr_two_2__648) + ); + FDPE plm_des0_reg_lfsr_two_1_ ( + .PRE(plm_rst), + .CE(plm_des0_reg_lfsr_one32_i), + .C(mgt_clk), + .D(plm_des0_N_85341_i), + .Q(plm_des0_reg_lfsr_two_1__647) + ); + FDPE plm_des0_reg_lfsr_two_0_ ( + .PRE(plm_rst), + .CE(plm_des0_reg_lfsr_one32_i), + .C(mgt_clk), + .D(plm_des0_N_85340_i), + .Q(plm_des0_reg_lfsr_two_0__530) + ); + defparam plm_des1_input_decoder_reg_sym_4_0_a2_0_.INIT = 4'h1; + LUT2 plm_des1_input_decoder_reg_sym_4_0_a2_0_ ( + .I0(plm_des1_reg_nitbl[0]), + .I1(plm_des1_reg_spesh[0]), + .O(plm_des1_reg_sym_4[0]) + ); + defparam plm_des1_input_decoder_reg_sym_3_0_a2_1_.INIT = 4'h1; + LUT2 plm_des1_input_decoder_reg_sym_3_0_a2_1_ ( + .I0(plm_des1_reg_nitbl[1]), + .I1(plm_des1_reg_spesh[1]), + .O(plm_des1_reg_sym_3[1]) + ); + defparam plm_des1_descram_reg_rx_des_dat_14_sn_m1_0_a2_0_a3_0_a2_0_a2.INIT = 4'h1; + LUT2 plm_des1_descram_reg_rx_des_dat_14_sn_m1_0_a2_0_a3_0_a2_0_a2 ( + .I0(plm_des1_reg_kkk[0]), + .I1(plm_reg_dis), + .O(plm_des1_m1_0_a2_0_a3_0_a2_0_a2_0) + ); + defparam plm_des1_lfsrs_reg_lfsr_one_12_0_iv_0_0_o4_0_.INIT = 4'h1; + LUT2 plm_des1_lfsrs_reg_lfsr_one_12_0_iv_0_0_o4_0_ ( + .I0(plm_des1_reg_skp[0]), + .I1(plm_des1_reg_skp[1]), + .O(plm_des1_N_49057_i) + ); + defparam plm_des1_descram_reg_rx_des_dat_7_i_x2_0_x2_0_o4_0_8_.INIT = 4'h1; + LUT2 plm_des1_descram_reg_rx_des_dat_7_i_x2_0_x2_0_o4_0_8_ ( + .I0(plm_des1_reg_kkk[1]), + .I1(plm_reg_dis), + .O(plm_des1_N_49066_i) + ); + defparam plm_des1_lfsrs_reg_lfsr_two_12_0_iv_0_0_o2_12_.INIT = 4'h1; + LUT2 plm_des1_lfsrs_reg_lfsr_two_12_0_iv_0_0_o2_12_ ( + .I0(plm_reg_com[0]), + .I1(plm_reg_com[1]), + .O(plm_des1_reg_lfsr_two_12_0_iv_0_0_o2[12]) + ); + defparam plm_des1_one_adv2_1_15_.INIT = 4'h6; + LUT2 plm_des1_one_adv2_1_15_ ( + .I0(plm_des1_reg_lfsr_one_10__968), + .I1(plm_des1_reg_lfsr_one_11__640), + .O(plm_des1_one_adv2_1_15__951) + ); + defparam plm_des1_one_adv2_1_13_.INIT = 4'h6; + LUT2 plm_des1_one_adv2_1_13_ ( + .I0(plm_des1_reg_lfsr_one_8__970), + .I1(plm_des1_reg_lfsr_one_9__969), + .O(plm_des1_one_adv2_1_13__952) + ); + defparam plm_des1_one_adv2_1_9_.INIT = 4'h6; + LUT2 plm_des1_one_adv2_1_9_ ( + .I0(plm_des1_reg_lfsr_one_4__974), + .I1(plm_des1_reg_lfsr_one_5__973), + .O(plm_des1_one_adv2_1_9__959) + ); + defparam plm_des1_one_adv2_1_6_.INIT = 4'h6; + LUT2 plm_des1_one_adv2_1_6_ ( + .I0(plm_des1_reg_lfsr_one_1__501), + .I1(plm_des1_reg_lfsr_one_12__624), + .O(plm_des1_one_adv2_1_6__957) + ); + defparam plm_des1_one_adv2_1_5_.INIT = 4'h6; + LUT2 plm_des1_one_adv2_1_5_ ( + .I0(plm_des1_reg_lfsr_one_2__975), + .I1(plm_des1_reg_lfsr_one_13__505), + .O(plm_des1_one_adv2_1_5__958) + ); + defparam plm_des1_two_adv2_1_14_.INIT = 4'h6; + LUT2 plm_des1_two_adv2_1_14_ ( + .I0(plm_des1_reg_lfsr_two_9__978), + .I1(plm_des1_reg_lfsr_two_10__977), + .O(plm_des1_two_adv2_1_14__953) + ); + defparam plm_des1_two_adv2_1_12_.INIT = 4'h6; + LUT2 plm_des1_two_adv2_1_12_ ( + .I0(plm_des1_reg_lfsr_two_7__980), + .I1(plm_des1_reg_lfsr_two_8__979), + .O(plm_des1_two_adv2_1_12__954) + ); + defparam plm_des1_two_adv2_1_10_.INIT = 4'h6; + LUT2 plm_des1_two_adv2_1_10_ ( + .I0(plm_des1_reg_lfsr_two_5__982), + .I1(plm_des1_reg_lfsr_two_6__981), + .O(plm_des1_two_adv2_1_10__960) + ); + defparam plm_des1_two_adv2_1_7_.INIT = 4'h6; + LUT2 plm_des1_two_adv2_1_7_ ( + .I0(plm_des1_reg_lfsr_two_2__659), + .I1(plm_des1_reg_lfsr_two_13__545), + .O(plm_des1_two_adv2_1_7__956) + ); + defparam plm_des1_two_adv2_1_1_.INIT = 4'h6; + LUT2 plm_des1_two_adv2_1_1_ ( + .I0(plm_des1_reg_lfsr_two_12__976), + .I1(plm_des1_reg_lfsr_two_13__545), + .O(plm_des1_two_adv2_1_1__955) + ); + defparam plm_des1_input_decoder_reg_bad_3_i_a7_2_0_1_.INIT = 4'h4; + LUT2_L plm_des1_input_decoder_reg_bad_3_i_a7_2_0_1_ ( + .I0(plm_des1_reg_data[13]), + .I1(plm_des1_reg_data[15]), + .LO(plm_des1_reg_bad_3_i_a7_2_0[1]) + ); + defparam plm_des1_input_decoder_reg_bad_4_i_a7_2_0_0_.INIT = 4'h4; + LUT2_L plm_des1_input_decoder_reg_bad_4_i_a7_2_0_0_ ( + .I0(plm_des1_reg_data[5]), + .I1(plm_des1_reg_data[7]), + .LO(plm_des1_reg_bad_4_i_a7_2_0[0]) + ); + defparam plm_des1_two_adv2_0_4_.INIT = 4'h6; + LUT2 plm_des1_two_adv2_0_4_ ( + .I0(plm_des1_reg_lfsr_two_0__543), + .I1(plm_des1_reg_lfsr_two_1__658), + .O(plm_des1_two_adv2_0[4]) + ); + defparam plm_des1_lfsrs_reg_lfsr_one32_i.INIT = 4'h7; + LUT2 plm_des1_lfsrs_reg_lfsr_one32_i ( + .I0(plm_des1_reg_skp[0]), + .I1(plm_des1_reg_skp[1]), + .O(plm_des1_reg_lfsr_one32_i) + ); + defparam plm_des1_input_decoder_reg_bad_4_i_x2_0_.INIT = 16'hE111; + LUT4 plm_des1_input_decoder_reg_bad_4_i_x2_0_ ( + .I0(plm_des1_reg_data[0]), + .I1(plm_des1_reg_data[1]), + .I2(plm_des1_reg_data[6]), + .I3(plm_des1_reg_data[7]), + .O(plm_des1_N_14198_i) + ); + defparam plm_des1_input_decoder_reg_bad_4_i_x2_0_0_.INIT = 16'h7888; + LUT4 plm_des1_input_decoder_reg_bad_4_i_x2_0_0_ ( + .I0(plm_des1_reg_data[0]), + .I1(plm_des1_reg_data[1]), + .I2(plm_des1_reg_data[2]), + .I3(plm_des1_reg_data[3]), + .O(plm_des1_N_14199_i) + ); + defparam plm_des1_input_decoder_reg_bad_3_i_x2_1_.INIT = 16'hE111; + LUT4 plm_des1_input_decoder_reg_bad_3_i_x2_1_ ( + .I0(plm_des1_reg_data[8]), + .I1(plm_des1_reg_data[9]), + .I2(plm_des1_reg_data[14]), + .I3(plm_des1_reg_data[15]), + .O(plm_des1_N_14232_i) + ); + defparam plm_des1_input_decoder_reg_bad_3_i_x2_0_1_.INIT = 16'h7888; + LUT4 plm_des1_input_decoder_reg_bad_3_i_x2_0_1_ ( + .I0(plm_des1_reg_data[8]), + .I1(plm_des1_reg_data[9]), + .I2(plm_des1_reg_data[10]), + .I3(plm_des1_reg_data[11]), + .O(plm_des1_N_14233_i) + ); + defparam plm_des1_input_decoder_reg_skp_3_0_a7_3_1_.INIT = 16'h1000; + LUT4 plm_des1_input_decoder_reg_skp_3_0_a7_3_1_ ( + .I0(plm_des1_reg_data[8]), + .I1(plm_des1_reg_data[9]), + .I2(plm_des1_reg_data[10]), + .I3(plm_des1_reg_data[11]), + .O(plm_des1_reg_skp_3_3[1]) + ); + defparam plm_des1_input_decoder_reg_com_3_0_a7_2_1_.INIT = 16'h0800; + LUT4 plm_des1_input_decoder_reg_com_3_0_a7_2_1_ ( + .I0(plm_des1_reg_data[12]), + .I1(plm_des1_reg_data[13]), + .I2(plm_des1_reg_nitbl[1]), + .I3(plm_des1_reg_spesh[1]), + .O(plm_des1_reg_pad_3_5[1]) + ); + defparam plm_des1_input_decoder_reg_t1n_3_0_a7_1_1_.INIT = 16'h0800; + LUT4 plm_des1_input_decoder_reg_t1n_3_0_a7_1_1_ ( + .I0(plm_des1_reg_data[12]), + .I1(plm_des1_reg_data[13]), + .I2(plm_des1_reg_data[14]), + .I3(plm_des1_reg_data[15]), + .O(plm_des1_reg_t2n_3_3[1]) + ); + defparam plm_des1_input_decoder_reg_skp_4_0_a7_3_0_.INIT = 16'h1000; + LUT4 plm_des1_input_decoder_reg_skp_4_0_a7_3_0_ ( + .I0(plm_des1_reg_data[0]), + .I1(plm_des1_reg_data[1]), + .I2(plm_des1_reg_data[2]), + .I3(plm_des1_reg_data[3]), + .O(plm_des1_reg_skp_4_3[0]) + ); + defparam plm_des1_input_decoder_reg_com_4_0_a7_2_0_.INIT = 16'h0800; + LUT4 plm_des1_input_decoder_reg_com_4_0_a7_2_0_ ( + .I0(plm_des1_reg_data[4]), + .I1(plm_des1_reg_data[5]), + .I2(plm_des1_reg_nitbl[0]), + .I3(plm_des1_reg_spesh[0]), + .O(plm_des1_reg_pad_4_5[0]) + ); + defparam plm_des1_input_decoder_reg_t1n_4_0_a7_1_0_.INIT = 16'h0800; + LUT4 plm_des1_input_decoder_reg_t1n_4_0_a7_1_0_ ( + .I0(plm_des1_reg_data[4]), + .I1(plm_des1_reg_data[5]), + .I2(plm_des1_reg_data[6]), + .I3(plm_des1_reg_data[7]), + .O(plm_des1_reg_t2n_4_3[0]) + ); + defparam plm_des1_lfsrs_reg_lfsr_two_12_iv_0_0_0_o4_9_.INIT = 8'h23; + LUT3 plm_des1_lfsrs_reg_lfsr_two_12_iv_0_0_0_o4_9_ ( + .I0(plm_reg_com[1]), + .I1(plm_des1_reg_skp[0]), + .I2(plm_des1_reg_skp[1]), + .O(plm_des1_reg_lfsr_two_12_iv_0_0_0_o4_0[9]) + ); + defparam plm_des1_lfsrs_reg_lfsr_two_12_iv_0_0_0_o2_9_.INIT = 8'h15; + LUT3 plm_des1_lfsrs_reg_lfsr_two_12_iv_0_0_0_o2_9_ ( + .I0(plm_reg_com[0]), + .I1(plm_reg_com[1]), + .I2(plm_des1_reg_skp[0]), + .O(plm_des1_N_49060_i) + ); + defparam plm_des1_two_adv2_1_6_.INIT = 8'h96; + LUT3 plm_des1_two_adv2_1_6_ ( + .I0(plm_des1_reg_lfsr_two_3__983), + .I1(plm_des1_reg_lfsr_two_12__976), + .I2(plm_des1_reg_lfsr_two_14__652), + .O(plm_des1_two_adv2_1_6__962) + ); + defparam plm_des1_two_adv2_15_.INIT = 16'h6996; + LUT4 plm_des1_two_adv2_15_ ( + .I0(plm_des1_reg_lfsr_two_10__977), + .I1(plm_des1_reg_lfsr_two_11__544), + .I2(plm_des1_reg_lfsr_two_12__976), + .I3(plm_des1_reg_lfsr_two_15__546), + .O(plm_des1_two_adv2_15__963) + ); + defparam plm_des1_input_decoder_reg_t1n_4_0_a7_1_0_0_.INIT = 8'h08; + LUT3 plm_des1_input_decoder_reg_t1n_4_0_a7_1_0_0_ ( + .I0(plm_des1_reg_sym_4[0]), + .I1(plm_des1_reg_data[2]), + .I2(plm_des1_reg_data[3]), + .O(plm_des1_reg_t1n_4_1[0]) + ); + defparam plm_des1_input_decoder_reg_t1n_3_0_a7_1_0_1_.INIT = 8'h08; + LUT3 plm_des1_input_decoder_reg_t1n_3_0_a7_1_0_1_ ( + .I0(plm_des1_reg_sym_3[1]), + .I1(plm_des1_reg_data[10]), + .I2(plm_des1_reg_data[11]), + .O(plm_des1_reg_t1n_3_1[1]) + ); + defparam plm_des1_one_adv2_2_.INIT = 8'h96; + LUT3 plm_des1_one_adv2_2_ ( + .I0(plm_des1_one_adv2_1_5__958), + .I1(plm_des1_reg_lfsr_one_14__653), + .I2(plm_des1_reg_lfsr_one_15__502), + .O(plm_des1_one_adv2[2]) + ); + defparam plm_des1_one_adv2_1_.INIT = 8'h96; + LUT3 plm_des1_one_adv2_1_ ( + .I0(plm_des1_one_adv2_1_6__957), + .I1(plm_des1_reg_lfsr_one_13__505), + .I2(plm_des1_reg_lfsr_one_14__653), + .O(plm_des1_one_adv2[1]) + ); + defparam plm_des1_two_adv2_12_.INIT = 8'h96; + LUT3 plm_des1_two_adv2_12_ ( + .I0(plm_des1_reg_lfsr_two_9__978), + .I1(plm_des1_reg_lfsr_two_12__976), + .I2(plm_des1_two_adv2_1_12__954), + .O(plm_des1_two_adv2_12__964) + ); + defparam plm_des1_two_adv2_10_.INIT = 8'h96; + LUT3 plm_des1_two_adv2_10_ ( + .I0(plm_des1_reg_lfsr_two_7__980), + .I1(plm_des1_reg_lfsr_two_10__977), + .I2(plm_des1_two_adv2_1_10__960), + .O(plm_des1_two_adv2_10__965) + ); + defparam plm_des1_one_adv2_15_.INIT = 8'h96; + LUT3 plm_des1_one_adv2_15_ ( + .I0(plm_des1_one_adv2_1_15__951), + .I1(plm_des1_reg_lfsr_one_12__624), + .I2(plm_des1_reg_lfsr_one_15__502), + .O(plm_des1_one_adv2[15]) + ); + defparam plm_des1_one_adv2_14_.INIT = 8'h96; + LUT3 plm_des1_one_adv2_14_ ( + .I0(plm_des1_one_adv2_1_15__951), + .I1(plm_des1_reg_lfsr_one_9__969), + .I2(plm_des1_reg_lfsr_one_14__653), + .O(plm_des1_one_adv2[14]) + ); + defparam plm_des1_one_adv2_13_.INIT = 8'h96; + LUT3 plm_des1_one_adv2_13_ ( + .I0(plm_des1_one_adv2_1_13__952), + .I1(plm_des1_reg_lfsr_one_10__968), + .I2(plm_des1_reg_lfsr_one_13__505), + .O(plm_des1_one_adv2[13]) + ); + defparam plm_des1_one_adv2_12_.INIT = 8'h96; + LUT3 plm_des1_one_adv2_12_ ( + .I0(plm_des1_one_adv2_1_13__952), + .I1(plm_des1_reg_lfsr_one_7__971), + .I2(plm_des1_reg_lfsr_one_12__624), + .O(plm_des1_one_adv2[12]) + ); + defparam plm_des1_one_adv2_11_.INIT = 16'h6996; + LUT4 plm_des1_one_adv2_11_ ( + .I0(plm_des1_reg_lfsr_one_6__972), + .I1(plm_des1_reg_lfsr_one_7__971), + .I2(plm_des1_reg_lfsr_one_8__970), + .I3(plm_des1_reg_lfsr_one_11__640), + .O(plm_des1_one_adv2[11]) + ); + defparam plm_des1_one_adv2_10_.INIT = 16'h6996; + LUT4 plm_des1_one_adv2_10_ ( + .I0(plm_des1_reg_lfsr_one_5__973), + .I1(plm_des1_reg_lfsr_one_6__972), + .I2(plm_des1_reg_lfsr_one_7__971), + .I3(plm_des1_reg_lfsr_one_10__968), + .O(plm_des1_one_adv2[10]) + ); + defparam plm_des1_input_decoder_reg_t1p_3_0_a7_1_1_.INIT = 16'h0010; + LUT4 plm_des1_input_decoder_reg_t1p_3_0_a7_1_1_ ( + .I0(plm_des1_reg_data[12]), + .I1(plm_des1_reg_data[13]), + .I2(plm_des1_reg_data[14]), + .I3(plm_des1_reg_data[15]), + .O(plm_des1_reg_t1p_3_1[1]) + ); + defparam plm_des1_input_decoder_reg_t1p_4_0_a7_1_0_.INIT = 16'h0010; + LUT4 plm_des1_input_decoder_reg_t1p_4_0_a7_1_0_ ( + .I0(plm_des1_reg_data[4]), + .I1(plm_des1_reg_data[5]), + .I2(plm_des1_reg_data[6]), + .I3(plm_des1_reg_data[7]), + .O(plm_des1_reg_t1p_4_1[0]) + ); + defparam plm_des1_two_adv2_1_8_.INIT = 8'h96; + LUT3 plm_des1_two_adv2_1_8_ ( + .I0(plm_des1_reg_lfsr_two_4__654), + .I1(plm_des1_reg_lfsr_two_5__982), + .I2(plm_des1_reg_lfsr_two_8__979), + .O(plm_des1_two_adv2_1_8__961) + ); + defparam plm_des1_input_decoder_reg_t2n_4_0_a7_0_2_0_.INIT = 16'h0400; + LUT4 plm_des1_input_decoder_reg_t2n_4_0_a7_0_2_0_ ( + .I0(plm_des1_reg_data[0]), + .I1(plm_des1_reg_data[1]), + .I2(plm_des1_reg_data[2]), + .I3(plm_des1_reg_data[3]), + .O(plm_des1_reg_t2n_4_0_a7_0_2[0]) + ); + defparam plm_des1_input_decoder_reg_t2n_3_0_a7_0_2_1_.INIT = 16'h0400; + LUT4 plm_des1_input_decoder_reg_t2n_3_0_a7_0_2_1_ ( + .I0(plm_des1_reg_data[8]), + .I1(plm_des1_reg_data[9]), + .I2(plm_des1_reg_data[10]), + .I3(plm_des1_reg_data[11]), + .O(plm_des1_reg_t2n_3_0_a7_0_2[1]) + ); + defparam plm_des1_input_decoder_reg_pad_3_0_a7_0_1_.INIT = 16'h2000; + LUT4 plm_des1_input_decoder_reg_pad_3_0_a7_0_1_ ( + .I0(plm_des1_reg_data[10]), + .I1(plm_des1_reg_data[11]), + .I2(plm_des1_reg_data[14]), + .I3(plm_des1_reg_data[15]), + .O(plm_des1_reg_pad_3_0_a7_0[1]) + ); + defparam plm_des1_input_decoder_reg_pad_4_0_a7_0_0_.INIT = 16'h2000; + LUT4 plm_des1_input_decoder_reg_pad_4_0_a7_0_0_ ( + .I0(plm_des1_reg_data[2]), + .I1(plm_des1_reg_data[3]), + .I2(plm_des1_reg_data[6]), + .I3(plm_des1_reg_data[7]), + .O(plm_des1_reg_pad_4_0_a7_0[0]) + ); + defparam plm_des1_input_decoder_reg_skp_4_0_a7_1_0_.INIT = 16'h0002; + LUT4 plm_des1_input_decoder_reg_skp_4_0_a7_1_0_ ( + .I0(plm_des1_reg_data[4]), + .I1(plm_des1_reg_data[5]), + .I2(plm_des1_reg_data[6]), + .I3(plm_des1_reg_data[7]), + .O(plm_des1_reg_skp_4_0_a7_1[0]) + ); + defparam plm_des1_input_decoder_reg_skp_3_0_a7_1_1_.INIT = 16'h0002; + LUT4 plm_des1_input_decoder_reg_skp_3_0_a7_1_1_ ( + .I0(plm_des1_reg_data[12]), + .I1(plm_des1_reg_data[13]), + .I2(plm_des1_reg_data[14]), + .I3(plm_des1_reg_data[15]), + .O(plm_des1_reg_skp_3_0_a7_1[1]) + ); + defparam plm_des1_lfsrs_reg_lfsr_two_12_iv_i_0_0_a2_15_.INIT = 4'h4; + LUT2_L plm_des1_lfsrs_reg_lfsr_two_12_iv_i_0_0_a2_15_ ( + .I0(plm_des1_reg_lfsr_two_12_iv_0_0_0_o4_0[9]), + .I1(plm_des1_one_adv2[15]), + .LO(plm_des1_reg_lfsr_two_12_iv_i_0_0_a2[15]) + ); + defparam plm_des1_lfsrs_reg_lfsr_two_12_iv_i_0_0_a2_0_14_.INIT = 8'h48; + LUT3 plm_des1_lfsrs_reg_lfsr_two_12_iv_i_0_0_a2_0_14_ ( + .I0(N_49152_i_0), + .I1(plm_des1_reg_lfsr_two_12_iv_0_0_0_a4_1[9]), + .I2(plm_des1_two_adv2_1_14__953), + .O(plm_des1_reg_lfsr_two_12_iv_i_0_0_a2_0_0_14_) + ); + defparam plm_des1_lfsrs_reg_lfsr_two_12_iv_i_0_0_a2_0_13_.INIT = 16'h8228; + LUT4 plm_des1_lfsrs_reg_lfsr_two_12_iv_i_0_0_a2_0_13_ ( + .I0(plm_des1_reg_lfsr_two_12_iv_0_0_0_a4_1[9]), + .I1(plm_des1_reg_lfsr_two_8__979), + .I2(plm_des1_reg_lfsr_two_13__545), + .I3(plm_des1_two_adv2_1_14__953), + .O(plm_des1_reg_lfsr_two_12_iv_i_0_0_a2_0_0_13_) + ); + defparam plm_des1_lfsrs_reg_lfsr_two_12_iv_i_0_0_a2_0_11_.INIT = 16'h8228; + LUT4_L plm_des1_lfsrs_reg_lfsr_two_12_iv_i_0_0_a2_0_11_ ( + .I0(plm_des1_reg_lfsr_two_12_iv_0_0_0_a4_1[9]), + .I1(plm_des1_reg_lfsr_two_6__981), + .I2(plm_des1_reg_lfsr_two_11__544), + .I3(plm_des1_two_adv2_1_12__954), + .LO(plm_des1_reg_lfsr_two_12_iv_i_0_0_a2_0_0_11_) + ); + defparam plm_des1_lfsrs_reg_lfsr_two_12_iv_i_0_0_a2_0_2_.INIT = 16'h8228; + LUT4 plm_des1_lfsrs_reg_lfsr_two_12_iv_i_0_0_a2_0_2_ ( + .I0(plm_des1_reg_lfsr_two_12_iv_0_0_0_a4_1[9]), + .I1(plm_des1_reg_lfsr_two_14__652), + .I2(plm_des1_reg_lfsr_two_15__546), + .I3(plm_des1_two_adv2_1_7__956), + .O(plm_des1_reg_lfsr_two_12_iv_i_0_0_a2_0_0_2_) + ); + defparam plm_des1_lfsrs_reg_lfsr_two_12_iv_i_0_0_a2_0_1_.INIT = 16'h8228; + LUT4 plm_des1_lfsrs_reg_lfsr_two_12_iv_i_0_0_a2_0_1_ ( + .I0(plm_des1_reg_lfsr_two_12_iv_0_0_0_a4_1[9]), + .I1(plm_des1_reg_lfsr_two_1__658), + .I2(plm_des1_reg_lfsr_two_14__652), + .I3(plm_des1_two_adv2_1_1__955), + .O(plm_des1_reg_lfsr_two_12_iv_i_0_0_a2_0_0_1_) + ); + defparam plm_des1_lfsrs_reg_lfsr_two_12_iv_i_0_0_a2_0_0_.INIT = 16'h8228; + LUT4 plm_des1_lfsrs_reg_lfsr_two_12_iv_i_0_0_a2_0_0_ ( + .I0(plm_des1_reg_lfsr_two_12_iv_0_0_0_a4_1[9]), + .I1(plm_des1_reg_lfsr_two_0__543), + .I2(plm_des1_reg_lfsr_two_11__544), + .I3(plm_des1_two_adv2_1_1__955), + .O(plm_des1_reg_lfsr_two_12_iv_i_0_0_a2_0_0_0_) + ); + defparam plm_des1_lfsrs_reg_lfsr_one_12_iv_i_0_0_a2_0_12_.INIT = 4'h8; + LUT2_L plm_des1_lfsrs_reg_lfsr_one_12_iv_i_0_0_a2_0_12_ ( + .I0(plm_des1_reg_lfsr_two_12_iv_0_0_0_a4_1[9]), + .I1(plm_des1_one_adv2[12]), + .LO(plm_des1_reg_lfsr_one_12_iv_i_0_0_a2_0_0_12_) + ); + defparam plm_des1_lfsrs_reg_lfsr_one_12_iv_i_0_0_a2_0_10_.INIT = 4'h8; + LUT2_L plm_des1_lfsrs_reg_lfsr_one_12_iv_i_0_0_a2_0_10_ ( + .I0(plm_des1_reg_lfsr_two_12_iv_0_0_0_a4_1[9]), + .I1(plm_des1_one_adv2[10]), + .LO(plm_des1_reg_lfsr_one_12_iv_i_0_0_a2_0_0_10_) + ); + defparam plm_des1_lfsrs_reg_lfsr_one_12_iv_i_0_0_a2_3_.INIT = 4'h4; + LUT2 plm_des1_lfsrs_reg_lfsr_one_12_iv_i_0_0_a2_3_ ( + .I0(plm_des1_reg_lfsr_two_12_iv_0_0_0_o4_0[9]), + .I1(plm_des1_reg_lfsr_two_3__983), + .O(plm_des1_reg_lfsr_one_12_iv_i_0_0_a2_0[3]) + ); + defparam plm_des1_lfsrs_reg_lfsr_one_12_0_iv_0_0_x4_0_.INIT = 4'h6; + LUT2 plm_des1_lfsrs_reg_lfsr_one_12_0_iv_0_0_x4_0_ ( + .I0(G_420_625), + .I1(plm_des1_reg_lfsr_one_13__505), + .O(plm_des1_N_49078_i_0) + ); + defparam plm_des1_descram_N_86081_i.INIT = 8'h57; + LUT3 plm_des1_descram_N_86081_i ( + .I0(plm_des1_m1_0_a2_0_a3_0_a2_0_a2_0), + .I1(plm_reg_com[1]), + .I2(plm_des1_reg_skp[1]), + .O(plm_des1_N_86081_i) + ); + defparam plm_des1_two_adv2_7_.INIT = 16'h6996; + LUT4 plm_des1_two_adv2_7_ ( + .I0(N_49149_i_0), + .I1(plm_des1_reg_lfsr_two_3__983), + .I2(plm_des1_reg_lfsr_two_7__980), + .I3(plm_des1_two_adv2_1_7__956), + .O(plm_des1_two_adv2_7__966) + ); + defparam plm_des1_one_adv2_6_.INIT = 16'h6996; + LUT4 plm_des1_one_adv2_6_ ( + .I0(N_49150_i_0), + .I1(plm_des1_one_adv2_1_6__957), + .I2(plm_des1_reg_lfsr_one_2__975), + .I3(plm_des1_reg_lfsr_one_6__972), + .O(plm_des1_one_adv2[6]) + ); + defparam plm_des1_one_adv2_7_.INIT = 16'h6996; + LUT4 plm_des1_one_adv2_7_ ( + .I0(G_332_506), + .I1(plm_des1_reg_lfsr_one_2__975), + .I2(plm_des1_reg_lfsr_one_4__974), + .I3(plm_des1_reg_lfsr_one_7__971), + .O(plm_des1_one_adv2[7]) + ); + defparam plm_des1_one_adv2_9_.INIT = 16'h6996; + LUT4 plm_des1_one_adv2_9_ ( + .I0(plm_des1_one_adv2_1_9__959), + .I1(plm_des1_reg_lfsr_one_6__972), + .I2(plm_des1_reg_lfsr_one_9__969), + .I3(plm_des1_reg_lfsr_one_15__502), + .O(plm_des1_one_adv2[9]) + ); + defparam plm_des1_two_adv2_6_.INIT = 8'h96; + LUT3 plm_des1_two_adv2_6_ ( + .I0(N_49108_i_0), + .I1(plm_des1_reg_lfsr_two_6__981), + .I2(plm_des1_two_adv2_1_6__962), + .O(plm_des1_two_adv2_6__967) + ); + defparam plm_des1_one_adv2_5_.INIT = 8'h96; + LUT3 plm_des1_one_adv2_5_ ( + .I0(G_331_503), + .I1(plm_des1_one_adv2_1_5__958), + .I2(plm_des1_reg_lfsr_one_5__973), + .O(plm_des1_one_adv2[5]) + ); + defparam plm_des1_one_adv2_4_.INIT = 8'h96; + LUT3 plm_des1_one_adv2_4_ ( + .I0(G_331_503), + .I1(plm_des1_reg_lfsr_one_4__974), + .I2(plm_des1_reg_lfsr_one_14__653), + .O(plm_des1_one_adv2[4]) + ); + defparam plm_des1_one_adv2_8_.INIT = 8'h96; + LUT3 plm_des1_one_adv2_8_ ( + .I0(N_49150_i_0), + .I1(plm_des1_one_adv2_1_9__959), + .I2(plm_des1_reg_lfsr_one_8__970), + .O(plm_des1_one_adv2[8]) + ); + defparam plm_des1_input_decoder_reg_bad_4_i_1_0_.INIT = 16'h54FF; + LUT4_L plm_des1_input_decoder_reg_bad_4_i_1_0_ ( + .I0(plm_des1_reg_bad_4_i_a7_2_0[0]), + .I1(plm_des1_reg_data[2]), + .I2(plm_des1_reg_data[3]), + .I3(plm_des1_reg_spesh[0]), + .LO(plm_des1_reg_bad_4_i_1[0]) + ); + defparam plm_des1_input_decoder_reg_bad_3_i_1_1_.INIT = 16'h54FF; + LUT4_L plm_des1_input_decoder_reg_bad_3_i_1_1_ ( + .I0(plm_des1_reg_bad_3_i_a7_2_0[1]), + .I1(plm_des1_reg_data[10]), + .I2(plm_des1_reg_data[11]), + .I3(plm_des1_reg_spesh[1]), + .LO(plm_des1_reg_bad_3_i_1[1]) + ); + defparam plm_des1_lfsrs_reg_lfsr_two_12_iv_0_0_0_a2_0_9_.INIT = 16'h4884; + LUT4 plm_des1_lfsrs_reg_lfsr_two_12_iv_0_0_0_a2_0_9_ ( + .I0(N_49149_i_0), + .I1(plm_des1_reg_lfsr_two_12_iv_0_0_0_a4_1[9]), + .I2(plm_des1_reg_lfsr_two_9__978), + .I3(plm_des1_two_adv2_1_10__960), + .O(plm_des1_reg_lfsr_two_12_iv_0_0_0_a2_0_9_) + ); + defparam plm_des1_lfsrs_reg_lfsr_two_12_iv_0_0_0_a2_0_8_.INIT = 16'h2882; + LUT4 plm_des1_lfsrs_reg_lfsr_two_12_iv_0_0_0_a2_0_8_ ( + .I0(plm_des1_reg_lfsr_two_12_iv_0_0_0_a4_1[9]), + .I1(plm_des1_reg_lfsr_two_3__983), + .I2(plm_des1_reg_lfsr_two_14__652), + .I3(plm_des1_two_adv2_1_8__961), + .O(plm_des1_reg_lfsr_two_12_iv_0_0_0_a2_0_8_) + ); + defparam plm_des1_lfsrs_reg_lfsr_two_12_iv_0_0_0_a2_0_5_.INIT = 16'h6090; + LUT4 plm_des1_lfsrs_reg_lfsr_two_12_iv_0_0_0_a2_0_5_ ( + .I0(G_347_547), + .I1(N_49108_i_0), + .I2(plm_des1_reg_lfsr_two_12_iv_0_0_0_a4_1[9]), + .I3(plm_des1_reg_lfsr_two_5__982), + .O(plm_des1_reg_lfsr_two_12_iv_0_0_0_a2_0_5_) + ); + defparam plm_des1_lfsrs_reg_lfsr_two_12_iv_0_0_0_a2_0_3_.INIT = 8'h84; + LUT3 plm_des1_lfsrs_reg_lfsr_two_12_iv_0_0_0_a2_0_3_ ( + .I0(G_347_547), + .I1(plm_des1_reg_lfsr_two_12_iv_0_0_0_a4_1[9]), + .I2(plm_des1_two_adv2_1_6__962), + .O(plm_des1_reg_lfsr_two_12_iv_0_0_0_a2_0_3_) + ); + defparam plm_des1_lfsrs_reg_lfsr_two_12_iv_i_0_0_a2_0_4_.INIT = 16'h9060; + LUT4 plm_des1_lfsrs_reg_lfsr_two_12_iv_i_0_0_a2_0_4_ ( + .I0(N_49149_i_0), + .I1(N_49152_i_0), + .I2(plm_des1_reg_lfsr_two_12_iv_0_0_0_a4_1[9]), + .I3(plm_des1_two_adv2_0[4]), + .O(plm_des1_reg_lfsr_two_12_iv_i_0_0_a2_0_0_4_) + ); + defparam plm_des1_lfsrs_reg_lfsr_one_12_iv_i_0_0_a2_0_9_.INIT = 4'h8; + LUT2_L plm_des1_lfsrs_reg_lfsr_one_12_iv_i_0_0_a2_0_9_ ( + .I0(plm_des1_reg_lfsr_two_12_iv_0_0_0_a4_1[9]), + .I1(plm_des1_one_adv2[9]), + .LO(plm_des1_reg_lfsr_one_12_iv_i_0_0_a2_0_0_9_) + ); + defparam plm_des1_lfsrs_reg_lfsr_one_12_iv_i_0_0_a2_0_8_.INIT = 4'h8; + LUT2_L plm_des1_lfsrs_reg_lfsr_one_12_iv_i_0_0_a2_0_8_ ( + .I0(plm_des1_reg_lfsr_two_12_iv_0_0_0_a4_1[9]), + .I1(plm_des1_one_adv2[8]), + .LO(plm_des1_reg_lfsr_one_12_iv_i_0_0_a2_0_0_8_) + ); + defparam plm_des1_lfsrs_reg_lfsr_one_12_iv_i_0_0_a2_0_7_.INIT = 4'h8; + LUT2_L plm_des1_lfsrs_reg_lfsr_one_12_iv_i_0_0_a2_0_7_ ( + .I0(plm_des1_reg_lfsr_two_12_iv_0_0_0_a4_1[9]), + .I1(plm_des1_one_adv2[7]), + .LO(plm_des1_reg_lfsr_one_12_iv_i_0_0_a2_0_0_7_) + ); + defparam plm_des1_lfsrs_reg_lfsr_one_12_iv_i_0_0_a2_0_6_.INIT = 4'h8; + LUT2_L plm_des1_lfsrs_reg_lfsr_one_12_iv_i_0_0_a2_0_6_ ( + .I0(plm_des1_reg_lfsr_two_12_iv_0_0_0_a4_1[9]), + .I1(plm_des1_one_adv2[6]), + .LO(plm_des1_reg_lfsr_one_12_iv_i_0_0_a2_0_0_6_) + ); + defparam plm_des1_lfsrs_reg_lfsr_one_12_iv_i_0_0_a2_0_5_.INIT = 4'h8; + LUT2_L plm_des1_lfsrs_reg_lfsr_one_12_iv_i_0_0_a2_0_5_ ( + .I0(plm_des1_reg_lfsr_two_12_iv_0_0_0_a4_1[9]), + .I1(plm_des1_one_adv2[5]), + .LO(plm_des1_reg_lfsr_one_12_iv_i_0_0_a2_0_0_5_) + ); + defparam plm_des1_descram_reg_rx_des_dat_14_0_am_7_.INIT = 8'h65; + LUT3 plm_des1_descram_reg_rx_des_dat_14_0_am_7_ ( + .I0(plm_des1_reg_dat[7]), + .I1(plm_des1_reg_lfsr_one_8__970), + .I2(plm_des1_reg_skp[1]), + .O(plm_des1_reg_rx_des_dat_14_0_am_1[7]) + ); + defparam plm_des1_descram_reg_rx_des_dat_14_0_bm_7_.INIT = 8'h6C; + LUT3 plm_des1_descram_reg_rx_des_dat_14_0_bm_7_ ( + .I0(plm_des1_m1_0_a2_0_a3_0_a2_0_a2_0), + .I1(plm_des1_reg_dat[7]), + .I2(plm_des1_reg_lfsr_two_8__979), + .O(plm_des1_reg_rx_des_dat_14_0_bm_1[7]) + ); + MUXF5 plm_des1_descram_reg_rx_des_dat_14_0_7_ ( + .I0(plm_des1_reg_rx_des_dat_14_0_am_1[7]), + .I1(plm_des1_reg_rx_des_dat_14_0_bm_1[7]), + .O(plm_des1_reg_rx_des_dat_14[7]), + .S(plm_des1_N_86081_i) + ); + defparam plm_des1_descram_reg_rx_des_dat_14_0_am_6_.INIT = 8'h65; + LUT3 plm_des1_descram_reg_rx_des_dat_14_0_am_6_ ( + .I0(plm_des1_reg_dat[6]), + .I1(plm_des1_reg_lfsr_one_9__969), + .I2(plm_des1_reg_skp[1]), + .O(plm_des1_reg_rx_des_dat_14_0_am_1[6]) + ); + defparam plm_des1_descram_reg_rx_des_dat_14_0_bm_6_.INIT = 8'h6C; + LUT3 plm_des1_descram_reg_rx_des_dat_14_0_bm_6_ ( + .I0(plm_des1_m1_0_a2_0_a3_0_a2_0_a2_0), + .I1(plm_des1_reg_dat[6]), + .I2(plm_des1_reg_lfsr_two_9__978), + .O(plm_des1_reg_rx_des_dat_14_0_bm_1[6]) + ); + MUXF5 plm_des1_descram_reg_rx_des_dat_14_0_6_ ( + .I0(plm_des1_reg_rx_des_dat_14_0_am_1[6]), + .I1(plm_des1_reg_rx_des_dat_14_0_bm_1[6]), + .O(plm_des1_reg_rx_des_dat_14[6]), + .S(plm_des1_N_86081_i) + ); + defparam plm_des1_descram_reg_rx_des_dat_14_0_am_5_.INIT = 8'h65; + LUT3 plm_des1_descram_reg_rx_des_dat_14_0_am_5_ ( + .I0(plm_des1_reg_dat[5]), + .I1(plm_des1_reg_lfsr_one_10__968), + .I2(plm_des1_reg_skp[1]), + .O(plm_des1_reg_rx_des_dat_14_0_am_1[5]) + ); + defparam plm_des1_descram_reg_rx_des_dat_14_0_bm_5_.INIT = 8'h6C; + LUT3 plm_des1_descram_reg_rx_des_dat_14_0_bm_5_ ( + .I0(plm_des1_m1_0_a2_0_a3_0_a2_0_a2_0), + .I1(plm_des1_reg_dat[5]), + .I2(plm_des1_reg_lfsr_two_10__977), + .O(plm_des1_reg_rx_des_dat_14_0_bm_1[5]) + ); + MUXF5 plm_des1_descram_reg_rx_des_dat_14_0_5_ ( + .I0(plm_des1_reg_rx_des_dat_14_0_am_1[5]), + .I1(plm_des1_reg_rx_des_dat_14_0_bm_1[5]), + .O(plm_des1_reg_rx_des_dat_14[5]), + .S(plm_des1_N_86081_i) + ); + defparam plm_des1_descram_reg_rx_des_dat_14_0_am_4_.INIT = 8'h65; + LUT3 plm_des1_descram_reg_rx_des_dat_14_0_am_4_ ( + .I0(plm_des1_reg_dat[4]), + .I1(plm_des1_reg_lfsr_one_11__640), + .I2(plm_des1_reg_skp[1]), + .O(plm_des1_reg_rx_des_dat_14_0_am_1[4]) + ); + defparam plm_des1_descram_reg_rx_des_dat_14_0_bm_4_.INIT = 8'h6C; + LUT3 plm_des1_descram_reg_rx_des_dat_14_0_bm_4_ ( + .I0(plm_des1_m1_0_a2_0_a3_0_a2_0_a2_0), + .I1(plm_des1_reg_dat[4]), + .I2(plm_des1_reg_lfsr_two_11__544), + .O(plm_des1_reg_rx_des_dat_14_0_bm_1[4]) + ); + MUXF5 plm_des1_descram_reg_rx_des_dat_14_0_4_ ( + .I0(plm_des1_reg_rx_des_dat_14_0_am_1[4]), + .I1(plm_des1_reg_rx_des_dat_14_0_bm_1[4]), + .O(plm_des1_reg_rx_des_dat_14[4]), + .S(plm_des1_N_86081_i) + ); + defparam plm_des1_descram_reg_rx_des_dat_14_0_am_3_.INIT = 8'h65; + LUT3 plm_des1_descram_reg_rx_des_dat_14_0_am_3_ ( + .I0(plm_des1_reg_dat[3]), + .I1(plm_des1_reg_lfsr_one_12__624), + .I2(plm_des1_reg_skp[1]), + .O(plm_des1_reg_rx_des_dat_14_0_am_1[3]) + ); + defparam plm_des1_descram_reg_rx_des_dat_14_0_bm_3_.INIT = 8'h6C; + LUT3 plm_des1_descram_reg_rx_des_dat_14_0_bm_3_ ( + .I0(plm_des1_m1_0_a2_0_a3_0_a2_0_a2_0), + .I1(plm_des1_reg_dat[3]), + .I2(plm_des1_reg_lfsr_two_12__976), + .O(plm_des1_reg_rx_des_dat_14_0_bm_1[3]) + ); + MUXF5 plm_des1_descram_reg_rx_des_dat_14_0_3_ ( + .I0(plm_des1_reg_rx_des_dat_14_0_am_1[3]), + .I1(plm_des1_reg_rx_des_dat_14_0_bm_1[3]), + .O(plm_des1_reg_rx_des_dat_14[3]), + .S(plm_des1_N_86081_i) + ); + defparam plm_des1_descram_reg_rx_des_dat_14_0_am_2_.INIT = 8'h65; + LUT3 plm_des1_descram_reg_rx_des_dat_14_0_am_2_ ( + .I0(plm_des1_reg_dat[2]), + .I1(plm_des1_reg_lfsr_one_13__505), + .I2(plm_des1_reg_skp[1]), + .O(plm_des1_reg_rx_des_dat_14_0_am_1[2]) + ); + defparam plm_des1_descram_reg_rx_des_dat_14_0_bm_2_.INIT = 8'h6C; + LUT3 plm_des1_descram_reg_rx_des_dat_14_0_bm_2_ ( + .I0(plm_des1_m1_0_a2_0_a3_0_a2_0_a2_0), + .I1(plm_des1_reg_dat[2]), + .I2(plm_des1_reg_lfsr_two_13__545), + .O(plm_des1_reg_rx_des_dat_14_0_bm_1[2]) + ); + MUXF5 plm_des1_descram_reg_rx_des_dat_14_0_2_ ( + .I0(plm_des1_reg_rx_des_dat_14_0_am_1[2]), + .I1(plm_des1_reg_rx_des_dat_14_0_bm_1[2]), + .O(plm_des1_reg_rx_des_dat_14[2]), + .S(plm_des1_N_86081_i) + ); + defparam plm_des1_descram_reg_rx_des_dat_14_0_am_1_.INIT = 8'h65; + LUT3 plm_des1_descram_reg_rx_des_dat_14_0_am_1_ ( + .I0(plm_des1_reg_dat[1]), + .I1(plm_des1_reg_lfsr_one_14__653), + .I2(plm_des1_reg_skp[1]), + .O(plm_des1_reg_rx_des_dat_14_0_am_1[1]) + ); + defparam plm_des1_descram_reg_rx_des_dat_14_0_bm_1_.INIT = 8'h6C; + LUT3 plm_des1_descram_reg_rx_des_dat_14_0_bm_1_ ( + .I0(plm_des1_m1_0_a2_0_a3_0_a2_0_a2_0), + .I1(plm_des1_reg_dat[1]), + .I2(plm_des1_reg_lfsr_two_14__652), + .O(plm_des1_reg_rx_des_dat_14_0_bm_1[1]) + ); + MUXF5 plm_des1_descram_reg_rx_des_dat_14_0_1_ ( + .I0(plm_des1_reg_rx_des_dat_14_0_am_1[1]), + .I1(plm_des1_reg_rx_des_dat_14_0_bm_1[1]), + .O(plm_des1_reg_rx_des_dat_14[1]), + .S(plm_des1_N_86081_i) + ); + defparam plm_des1_descram_reg_rx_des_dat_14_0_am_0_.INIT = 8'h65; + LUT3 plm_des1_descram_reg_rx_des_dat_14_0_am_0_ ( + .I0(plm_des1_reg_dat[0]), + .I1(plm_des1_reg_lfsr_one_15__502), + .I2(plm_des1_reg_skp[1]), + .O(plm_des1_reg_rx_des_dat_14_0_am_1[0]) + ); + defparam plm_des1_descram_reg_rx_des_dat_14_0_bm_0_.INIT = 8'h6C; + LUT3 plm_des1_descram_reg_rx_des_dat_14_0_bm_0_ ( + .I0(plm_des1_m1_0_a2_0_a3_0_a2_0_a2_0), + .I1(plm_des1_reg_dat[0]), + .I2(plm_des1_reg_lfsr_two_15__546), + .O(plm_des1_reg_rx_des_dat_14_0_bm_1[0]) + ); + MUXF5 plm_des1_descram_reg_rx_des_dat_14_0_0_ ( + .I0(plm_des1_reg_rx_des_dat_14_0_am_1[0]), + .I1(plm_des1_reg_rx_des_dat_14_0_bm_1[0]), + .O(plm_des1_reg_rx_des_dat_14[0]), + .S(plm_des1_N_86081_i) + ); + defparam plm_des1_one_adv2_3_.INIT = 8'h96; + LUT3 plm_des1_one_adv2_3_ ( + .I0(G_332_506), + .I1(G_420_625), + .I2(plm_des1_reg_lfsr_one_14__653), + .O(plm_des1_one_adv2[3]) + ); + defparam plm_des1_input_decoder_reg_bad_4_i_2_0_.INIT = 16'h080A; + LUT4_L plm_des1_input_decoder_reg_bad_4_i_2_0_ ( + .I0(plm_des1_reg_bad_4_i_1[0]), + .I1(plm_des1_reg_data[4]), + .I2(plm_des1_reg_nitbl[0]), + .I3(plm_des1_reg_spesh[0]), + .LO(plm_des1_reg_bad_4_i_2[0]) + ); + defparam plm_des1_input_decoder_reg_bad_3_i_2_1_.INIT = 16'h080A; + LUT4_L plm_des1_input_decoder_reg_bad_3_i_2_1_ ( + .I0(plm_des1_reg_bad_3_i_1[1]), + .I1(plm_des1_reg_data[12]), + .I2(plm_des1_reg_nitbl[1]), + .I3(plm_des1_reg_spesh[1]), + .LO(plm_des1_reg_bad_3_i_2[1]) + ); + defparam plm_des1_input_decoder_reg_t2n_3_0_a7_1_.INIT = 8'h80; + LUT3_L plm_des1_input_decoder_reg_t2n_3_0_a7_1_ ( + .I0(plm_des1_reg_sym_3[1]), + .I1(plm_des1_reg_t2n_3_0_a7_0_2[1]), + .I2(plm_des1_reg_t2n_3_3[1]), + .LO(plm_des1_reg_t2n_3[1]) + ); + defparam plm_des1_input_decoder_reg_t2n_4_0_a7_0_.INIT = 8'h80; + LUT3_L plm_des1_input_decoder_reg_t2n_4_0_a7_0_ ( + .I0(plm_des1_reg_sym_4[0]), + .I1(plm_des1_reg_t2n_4_0_a7_0_2[0]), + .I2(plm_des1_reg_t2n_4_3[0]), + .LO(plm_reg_t2n_4_0[0]) + ); + defparam plm_des1_input_decoder_N_85318_i.INIT = 16'h7F0F; + LUT4_L plm_des1_input_decoder_N_85318_i ( + .I0(plm_des1_N_14232_i), + .I1(plm_des1_N_14233_i), + .I2(plm_des1_reg_bad_3_i_2[1]), + .I3(plm_des1_reg_spesh[1]), + .LO(plm_des1_N_85318_i) + ); + defparam plm_des1_input_decoder_N_85319_i.INIT = 16'h7F0F; + LUT4_L plm_des1_input_decoder_N_85319_i ( + .I0(plm_des1_N_14198_i), + .I1(plm_des1_N_14199_i), + .I2(plm_des1_reg_bad_4_i_2[0]), + .I3(plm_des1_reg_spesh[0]), + .LO(plm_des1_N_85319_i) + ); + defparam plm_des1_descram_N_49196_i_0_i.INIT = 8'h6C; + LUT3_L plm_des1_descram_N_49196_i_0_i ( + .I0(plm_des1_N_49066_i), + .I1(plm_des1_reg_dat[15]), + .I2(plm_des1_reg_lfsr_one_8__970), + .LO(plm_des1_N_49196_i_0_i) + ); + defparam plm_des1_descram_N_49194_i_0_i.INIT = 8'h6C; + LUT3_L plm_des1_descram_N_49194_i_0_i ( + .I0(plm_des1_N_49066_i), + .I1(plm_des1_reg_dat[14]), + .I2(plm_des1_reg_lfsr_one_9__969), + .LO(plm_des1_N_49194_i_0_i) + ); + defparam plm_des1_descram_N_49192_i_0_i.INIT = 8'h6C; + LUT3_L plm_des1_descram_N_49192_i_0_i ( + .I0(plm_des1_N_49066_i), + .I1(plm_des1_reg_dat[13]), + .I2(plm_des1_reg_lfsr_one_10__968), + .LO(plm_des1_N_49192_i_0_i) + ); + defparam plm_des1_descram_N_49190_i_0_i.INIT = 8'h6C; + LUT3_L plm_des1_descram_N_49190_i_0_i ( + .I0(plm_des1_N_49066_i), + .I1(plm_des1_reg_dat[12]), + .I2(plm_des1_reg_lfsr_one_11__640), + .LO(plm_des1_N_49190_i_0_i) + ); + defparam plm_des1_descram_N_49188_i_0_i.INIT = 8'h6C; + LUT3_L plm_des1_descram_N_49188_i_0_i ( + .I0(plm_des1_N_49066_i), + .I1(plm_des1_reg_dat[11]), + .I2(plm_des1_reg_lfsr_one_12__624), + .LO(plm_des1_N_49188_i_0_i) + ); + defparam plm_des1_descram_N_49186_i_0_i.INIT = 8'h6C; + LUT3_L plm_des1_descram_N_49186_i_0_i ( + .I0(plm_des1_N_49066_i), + .I1(plm_des1_reg_dat[10]), + .I2(plm_des1_reg_lfsr_one_13__505), + .LO(plm_des1_N_49186_i_0_i) + ); + defparam plm_des1_descram_N_49184_i_0_i.INIT = 8'h6C; + LUT3_L plm_des1_descram_N_49184_i_0_i ( + .I0(plm_des1_N_49066_i), + .I1(plm_des1_reg_dat[9]), + .I2(plm_des1_reg_lfsr_one_14__653), + .LO(plm_des1_N_49184_i_0_i) + ); + defparam plm_des1_descram_N_49182_i_0_i.INIT = 8'h6C; + LUT3_L plm_des1_descram_N_49182_i_0_i ( + .I0(plm_des1_N_49066_i), + .I1(plm_des1_reg_dat[8]), + .I2(plm_des1_reg_lfsr_one_15__502), + .LO(plm_des1_N_49182_i_0_i) + ); + defparam plm_des1_input_decoder_reg_skp_4_0_a7_0_.INIT = 16'h0800; + LUT4_L plm_des1_input_decoder_reg_skp_4_0_a7_0_ ( + .I0(plm_des1_reg_skp_4_0_a7_1[0]), + .I1(plm_des1_reg_skp_4_3[0]), + .I2(plm_des1_reg_nitbl[0]), + .I3(plm_des1_reg_spesh[0]), + .LO(plm_des1_reg_skp_4[0]) + ); + defparam plm_des1_input_decoder_reg_pad_3_0_a7_1_.INIT = 16'h8000; + LUT4_L plm_des1_input_decoder_reg_pad_3_0_a7_1_ ( + .I0(plm_des1_reg_pad_3_0_a7_0[1]), + .I1(plm_des1_reg_pad_3_5[1]), + .I2(plm_des1_reg_data[8]), + .I3(plm_des1_reg_data[9]), + .LO(plm_reg_pad_3[1]) + ); + defparam plm_des1_input_decoder_reg_pad_4_0_a7_0_.INIT = 16'h8000; + LUT4_L plm_des1_input_decoder_reg_pad_4_0_a7_0_ ( + .I0(plm_des1_reg_pad_4_0_a7_0[0]), + .I1(plm_des1_reg_pad_4_5[0]), + .I2(plm_des1_reg_data[0]), + .I3(plm_des1_reg_data[1]), + .LO(plm_reg_pad_4[0]) + ); + defparam plm_des1_input_decoder_reg_com_3_0_a7_1_.INIT = 16'h0800; + LUT4_L plm_des1_input_decoder_reg_com_3_0_a7_1_ ( + .I0(plm_des1_reg_pad_3_5[1]), + .I1(plm_des1_reg_skp_3_3[1]), + .I2(plm_des1_reg_data[14]), + .I3(plm_des1_reg_data[15]), + .LO(plm_des1_reg_com_3[1]) + ); + defparam plm_des1_input_decoder_reg_com_4_0_a7_0_.INIT = 16'h0800; + LUT4_L plm_des1_input_decoder_reg_com_4_0_a7_0_ ( + .I0(plm_des1_reg_pad_4_5[0]), + .I1(plm_des1_reg_skp_4_3[0]), + .I2(plm_des1_reg_data[6]), + .I3(plm_des1_reg_data[7]), + .LO(plm_des1_reg_com_4[0]) + ); + defparam plm_des1_input_decoder_reg_t2p_3_0_a7_1_.INIT = 16'h0080; + LUT4_L plm_des1_input_decoder_reg_t2p_3_0_a7_1_ ( + .I0(plm_des1_reg_t1n_3_1[1]), + .I1(plm_des1_reg_t1p_3_1[1]), + .I2(plm_des1_reg_data[8]), + .I3(plm_des1_reg_data[9]), + .LO(plm_des1_reg_t2p_3[1]) + ); + defparam plm_des1_input_decoder_reg_t2p_4_0_a7_0_.INIT = 16'h0080; + LUT4_L plm_des1_input_decoder_reg_t2p_4_0_a7_0_ ( + .I0(plm_des1_reg_t1n_4_1[0]), + .I1(plm_des1_reg_t1p_4_1[0]), + .I2(plm_des1_reg_data[0]), + .I3(plm_des1_reg_data[1]), + .LO(plm_reg_t2p_4_0[0]) + ); + defparam plm_des1_input_decoder_reg_t1p_3_0_a7_1_.INIT = 8'h80; + LUT3_L plm_des1_input_decoder_reg_t1p_3_0_a7_1_ ( + .I0(plm_des1_reg_sym_3[1]), + .I1(plm_des1_reg_t1p_3_1[1]), + .I2(plm_des1_reg_t2n_3_0_a7_0_2[1]), + .LO(plm_des1_reg_t1p_3[1]) + ); + defparam plm_des1_input_decoder_reg_t1p_4_0_a7_0_.INIT = 8'h80; + LUT3_L plm_des1_input_decoder_reg_t1p_4_0_a7_0_ ( + .I0(plm_des1_reg_sym_4[0]), + .I1(plm_des1_reg_t1p_4_1[0]), + .I2(plm_des1_reg_t2n_4_0_a7_0_2[0]), + .LO(plm_reg_t1p_4_0[0]) + ); + defparam plm_des1_input_decoder_reg_t1n_3_0_a7_1_.INIT = 16'h0080; + LUT4_L plm_des1_input_decoder_reg_t1n_3_0_a7_1_ ( + .I0(plm_des1_reg_t1n_3_1[1]), + .I1(plm_des1_reg_t2n_3_3[1]), + .I2(plm_des1_reg_data[8]), + .I3(plm_des1_reg_data[9]), + .LO(plm_des1_reg_t1n_3[1]) + ); + defparam plm_des1_input_decoder_reg_t1n_4_0_a7_0_.INIT = 16'h0080; + LUT4_L plm_des1_input_decoder_reg_t1n_4_0_a7_0_ ( + .I0(plm_des1_reg_t1n_4_1[0]), + .I1(plm_des1_reg_t2n_4_3[0]), + .I2(plm_des1_reg_data[0]), + .I3(plm_des1_reg_data[1]), + .LO(plm_reg_t1n_4_0[0]) + ); + defparam plm_des1_input_decoder_reg_skp_3_0_a7_1_.INIT = 16'h0800; + LUT4_L plm_des1_input_decoder_reg_skp_3_0_a7_1_ ( + .I0(plm_des1_reg_skp_3_0_a7_1[1]), + .I1(plm_des1_reg_skp_3_3[1]), + .I2(plm_des1_reg_nitbl[1]), + .I3(plm_des1_reg_spesh[1]), + .LO(plm_des1_reg_skp_3[1]) + ); + defparam plm_des1_lfsrs_N_87696_i.INIT = 16'hF7B3; + LUT4_L plm_des1_lfsrs_N_87696_i ( + .I0(plm_des1_N_49057_i), + .I1(plm_des1_reg_lfsr_two_12_0_iv_0_0_o2[12]), + .I2(plm_des1_one_adv2[15]), + .I3(plm_des1_reg_lfsr_two_15__546), + .LO(plm_des1_N_87696_i) + ); + defparam plm_des1_lfsrs_N_87695_i.INIT = 16'hF7B3; + LUT4_L plm_des1_lfsrs_N_87695_i ( + .I0(plm_des1_N_49057_i), + .I1(plm_des1_reg_lfsr_two_12_0_iv_0_0_o2[12]), + .I2(plm_des1_one_adv2[14]), + .I3(plm_des1_reg_lfsr_two_14__652), + .LO(plm_des1_N_87695_i) + ); + defparam plm_des1_lfsrs_N_87694_i.INIT = 16'hF7B3; + LUT4_L plm_des1_lfsrs_N_87694_i ( + .I0(plm_des1_N_49057_i), + .I1(plm_des1_reg_lfsr_two_12_0_iv_0_0_o2[12]), + .I2(plm_des1_one_adv2[13]), + .I3(plm_des1_reg_lfsr_two_13__545), + .LO(plm_des1_N_87694_i) + ); + defparam plm_des1_lfsrs_N_85355_i.INIT = 16'hDFDD; + LUT4_L plm_des1_lfsrs_N_85355_i ( + .I0(plm_des1_N_49060_i), + .I1(plm_des1_reg_lfsr_one_12_iv_i_0_0_a2_0_0_12_), + .I2(plm_des1_reg_lfsr_two_12_iv_0_0_0_o4_0[9]), + .I3(plm_des1_reg_lfsr_two_12__976), + .LO(plm_des1_N_85355_i) + ); + defparam plm_des1_lfsrs_N_87693_i.INIT = 16'hF7B3; + LUT4_L plm_des1_lfsrs_N_87693_i ( + .I0(plm_des1_N_49057_i), + .I1(plm_des1_reg_lfsr_two_12_0_iv_0_0_o2[12]), + .I2(plm_des1_one_adv2[11]), + .I3(plm_des1_reg_lfsr_two_11__544), + .LO(plm_des1_N_87693_i) + ); + defparam plm_des1_lfsrs_N_85354_i.INIT = 16'hDFDD; + LUT4_L plm_des1_lfsrs_N_85354_i ( + .I0(plm_des1_N_49060_i), + .I1(plm_des1_reg_lfsr_one_12_iv_i_0_0_a2_0_0_10_), + .I2(plm_des1_reg_lfsr_two_12_iv_0_0_0_o4_0[9]), + .I3(plm_des1_reg_lfsr_two_10__977), + .LO(plm_des1_N_85354_i) + ); + defparam plm_des1_lfsrs_N_85353_i.INIT = 16'hDFDD; + LUT4_L plm_des1_lfsrs_N_85353_i ( + .I0(plm_des1_N_49060_i), + .I1(plm_des1_reg_lfsr_one_12_iv_i_0_0_a2_0_0_9_), + .I2(plm_des1_reg_lfsr_two_12_iv_0_0_0_o4_0[9]), + .I3(plm_des1_reg_lfsr_two_9__978), + .LO(plm_des1_N_85353_i) + ); + defparam plm_des1_lfsrs_N_85352_i.INIT = 16'hDFDD; + LUT4_L plm_des1_lfsrs_N_85352_i ( + .I0(plm_des1_N_49060_i), + .I1(plm_des1_reg_lfsr_one_12_iv_i_0_0_a2_0_0_8_), + .I2(plm_des1_reg_lfsr_two_12_iv_0_0_0_o4_0[9]), + .I3(plm_des1_reg_lfsr_two_8__979), + .LO(plm_des1_N_85352_i) + ); + defparam plm_des1_lfsrs_N_85351_i.INIT = 16'hDFDD; + LUT4_L plm_des1_lfsrs_N_85351_i ( + .I0(plm_des1_N_49060_i), + .I1(plm_des1_reg_lfsr_one_12_iv_i_0_0_a2_0_0_7_), + .I2(plm_des1_reg_lfsr_two_12_iv_0_0_0_o4_0[9]), + .I3(plm_des1_reg_lfsr_two_7__980), + .LO(plm_des1_N_85351_i) + ); + defparam plm_des1_lfsrs_N_85350_i.INIT = 16'hDFDD; + LUT4_L plm_des1_lfsrs_N_85350_i ( + .I0(plm_des1_N_49060_i), + .I1(plm_des1_reg_lfsr_one_12_iv_i_0_0_a2_0_0_6_), + .I2(plm_des1_reg_lfsr_two_12_iv_0_0_0_o4_0[9]), + .I3(plm_des1_reg_lfsr_two_6__981), + .LO(plm_des1_N_85350_i) + ); + defparam plm_des1_lfsrs_N_85349_i.INIT = 16'hDFDD; + LUT4_L plm_des1_lfsrs_N_85349_i ( + .I0(plm_des1_N_49060_i), + .I1(plm_des1_reg_lfsr_one_12_iv_i_0_0_a2_0_0_5_), + .I2(plm_des1_reg_lfsr_two_12_iv_0_0_0_o4_0[9]), + .I3(plm_des1_reg_lfsr_two_5__982), + .LO(plm_des1_N_85349_i) + ); + defparam plm_des1_lfsrs_N_87692_i.INIT = 16'hF7B3; + LUT4_L plm_des1_lfsrs_N_87692_i ( + .I0(plm_des1_N_49057_i), + .I1(plm_des1_reg_lfsr_two_12_0_iv_0_0_o2[12]), + .I2(plm_des1_one_adv2[4]), + .I3(plm_des1_reg_lfsr_two_4__654), + .LO(plm_des1_N_87692_i) + ); + defparam plm_des1_lfsrs_N_85348_i.INIT = 16'hFDDD; + LUT4_L plm_des1_lfsrs_N_85348_i ( + .I0(plm_des1_N_49060_i), + .I1(plm_des1_reg_lfsr_one_12_iv_i_0_0_a2_0[3]), + .I2(plm_des1_reg_lfsr_two_12_iv_0_0_0_a4_1[9]), + .I3(plm_des1_one_adv2[3]), + .LO(plm_des1_N_85348_i) + ); + defparam plm_des1_lfsrs_N_87691_i.INIT = 16'hF7B3; + LUT4_L plm_des1_lfsrs_N_87691_i ( + .I0(plm_des1_N_49057_i), + .I1(plm_des1_reg_lfsr_two_12_0_iv_0_0_o2[12]), + .I2(plm_des1_one_adv2[2]), + .I3(plm_des1_reg_lfsr_two_2__659), + .LO(plm_des1_N_87691_i) + ); + defparam plm_des1_lfsrs_N_87690_i.INIT = 16'hF7B3; + LUT4_L plm_des1_lfsrs_N_87690_i ( + .I0(plm_des1_N_49057_i), + .I1(plm_des1_reg_lfsr_two_12_0_iv_0_0_o2[12]), + .I2(plm_des1_one_adv2[1]), + .I3(plm_des1_reg_lfsr_two_1__658), + .LO(plm_des1_N_87690_i) + ); + defparam plm_des1_lfsrs_N_87689_i.INIT = 16'hDF8F; + LUT4_L plm_des1_lfsrs_N_87689_i ( + .I0(plm_des1_N_49057_i), + .I1(plm_des1_N_49078_i_0), + .I2(plm_des1_reg_lfsr_two_12_0_iv_0_0_o2[12]), + .I3(plm_des1_reg_lfsr_two_0__543), + .LO(plm_des1_N_87689_i) + ); + defparam plm_des1_lfsrs_N_85363_i.INIT = 16'hFDDD; + LUT4_L plm_des1_lfsrs_N_85363_i ( + .I0(plm_des1_N_49060_i), + .I1(plm_des1_reg_lfsr_two_12_iv_i_0_0_a2[15]), + .I2(plm_des1_reg_lfsr_two_12_iv_0_0_0_a4_1[9]), + .I3(plm_des1_two_adv2_15__963), + .LO(plm_des1_N_85363_i) + ); + defparam plm_des1_lfsrs_N_85362_i.INIT = 16'hDFDD; + LUT4_L plm_des1_lfsrs_N_85362_i ( + .I0(plm_des1_N_49060_i), + .I1(plm_des1_reg_lfsr_two_12_iv_i_0_0_a2_0_0_14_), + .I2(plm_des1_reg_lfsr_two_12_iv_0_0_0_o4_0[9]), + .I3(plm_des1_one_adv2[14]), + .LO(plm_des1_N_85362_i) + ); + defparam plm_des1_lfsrs_N_85361_i.INIT = 16'hDFDD; + LUT4_L plm_des1_lfsrs_N_85361_i ( + .I0(plm_des1_N_49060_i), + .I1(plm_des1_reg_lfsr_two_12_iv_i_0_0_a2_0_0_13_), + .I2(plm_des1_reg_lfsr_two_12_iv_0_0_0_o4_0[9]), + .I3(plm_des1_one_adv2[13]), + .LO(plm_des1_N_85361_i) + ); + defparam plm_des1_lfsrs_reg_lfsr_two_12_0_iv_0_0_12_.INIT = 16'hC840; + LUT4_L plm_des1_lfsrs_reg_lfsr_two_12_0_iv_0_0_12_ ( + .I0(plm_des1_N_49057_i), + .I1(plm_des1_reg_lfsr_two_12_0_iv_0_0_o2[12]), + .I2(plm_des1_one_adv2[12]), + .I3(plm_des1_two_adv2_12__964), + .LO(plm_des1_N_9543_i) + ); + defparam plm_des1_lfsrs_N_85360_i.INIT = 16'hDFDD; + LUT4_L plm_des1_lfsrs_N_85360_i ( + .I0(plm_des1_N_49060_i), + .I1(plm_des1_reg_lfsr_two_12_iv_i_0_0_a2_0_0_11_), + .I2(plm_des1_reg_lfsr_two_12_iv_0_0_0_o4_0[9]), + .I3(plm_des1_one_adv2[11]), + .LO(plm_des1_N_85360_i) + ); + defparam plm_des1_lfsrs_reg_lfsr_two_12_0_iv_0_0_10_.INIT = 16'hC840; + LUT4_L plm_des1_lfsrs_reg_lfsr_two_12_0_iv_0_0_10_ ( + .I0(plm_des1_N_49057_i), + .I1(plm_des1_reg_lfsr_two_12_0_iv_0_0_o2[12]), + .I2(plm_des1_one_adv2[10]), + .I3(plm_des1_two_adv2_10__965), + .LO(plm_des1_N_9545_i) + ); + defparam plm_des1_lfsrs_reg_lfsr_two_12_iv_0_0_0_9_.INIT = 16'h2220; + LUT4_L plm_des1_lfsrs_reg_lfsr_two_12_iv_0_0_0_9_ ( + .I0(plm_des1_N_49060_i), + .I1(plm_des1_reg_lfsr_two_12_iv_0_0_0_a2_0_9_), + .I2(plm_des1_reg_lfsr_two_12_iv_0_0_0_o4_0[9]), + .I3(plm_des1_one_adv2[9]), + .LO(plm_des1_N_9546_i) + ); + defparam plm_des1_lfsrs_reg_lfsr_two_12_iv_0_0_0_8_.INIT = 16'h2220; + LUT4_L plm_des1_lfsrs_reg_lfsr_two_12_iv_0_0_0_8_ ( + .I0(plm_des1_N_49060_i), + .I1(plm_des1_reg_lfsr_two_12_iv_0_0_0_a2_0_8_), + .I2(plm_des1_reg_lfsr_two_12_iv_0_0_0_o4_0[9]), + .I3(plm_des1_one_adv2[8]), + .LO(plm_des1_N_9547_i) + ); + defparam plm_des1_lfsrs_reg_lfsr_two_12_0_iv_0_0_7_.INIT = 16'hC840; + LUT4_L plm_des1_lfsrs_reg_lfsr_two_12_0_iv_0_0_7_ ( + .I0(plm_des1_N_49057_i), + .I1(plm_des1_reg_lfsr_two_12_0_iv_0_0_o2[12]), + .I2(plm_des1_one_adv2[7]), + .I3(plm_des1_two_adv2_7__966), + .LO(plm_des1_N_9548_i) + ); + defparam plm_des1_lfsrs_reg_lfsr_two_12_0_iv_0_0_6_.INIT = 16'hC840; + LUT4_L plm_des1_lfsrs_reg_lfsr_two_12_0_iv_0_0_6_ ( + .I0(plm_des1_N_49057_i), + .I1(plm_des1_reg_lfsr_two_12_0_iv_0_0_o2[12]), + .I2(plm_des1_one_adv2[6]), + .I3(plm_des1_two_adv2_6__967), + .LO(plm_des1_N_9549_i) + ); + defparam plm_des1_lfsrs_reg_lfsr_two_12_iv_0_0_0_5_.INIT = 16'h2220; + LUT4_L plm_des1_lfsrs_reg_lfsr_two_12_iv_0_0_0_5_ ( + .I0(plm_des1_N_49060_i), + .I1(plm_des1_reg_lfsr_two_12_iv_0_0_0_a2_0_5_), + .I2(plm_des1_reg_lfsr_two_12_iv_0_0_0_o4_0[9]), + .I3(plm_des1_one_adv2[5]), + .LO(plm_des1_N_9550_i) + ); + defparam plm_des1_lfsrs_N_85359_i.INIT = 16'hDFDD; + LUT4_L plm_des1_lfsrs_N_85359_i ( + .I0(plm_des1_N_49060_i), + .I1(plm_des1_reg_lfsr_two_12_iv_i_0_0_a2_0_0_4_), + .I2(plm_des1_reg_lfsr_two_12_iv_0_0_0_o4_0[9]), + .I3(plm_des1_one_adv2[4]), + .LO(plm_des1_N_85359_i) + ); + defparam plm_des1_lfsrs_reg_lfsr_two_12_iv_0_0_0_3_.INIT = 16'h2220; + LUT4_L plm_des1_lfsrs_reg_lfsr_two_12_iv_0_0_0_3_ ( + .I0(plm_des1_N_49060_i), + .I1(plm_des1_reg_lfsr_two_12_iv_0_0_0_a2_0_3_), + .I2(plm_des1_reg_lfsr_two_12_iv_0_0_0_o4_0[9]), + .I3(plm_des1_one_adv2[3]), + .LO(plm_des1_N_9552_i) + ); + defparam plm_des1_lfsrs_N_85358_i.INIT = 16'hDFDD; + LUT4_L plm_des1_lfsrs_N_85358_i ( + .I0(plm_des1_N_49060_i), + .I1(plm_des1_reg_lfsr_two_12_iv_i_0_0_a2_0_0_2_), + .I2(plm_des1_reg_lfsr_two_12_iv_0_0_0_o4_0[9]), + .I3(plm_des1_one_adv2[2]), + .LO(plm_des1_N_85358_i) + ); + defparam plm_des1_lfsrs_N_85357_i.INIT = 16'hDFDD; + LUT4_L plm_des1_lfsrs_N_85357_i ( + .I0(plm_des1_N_49060_i), + .I1(plm_des1_reg_lfsr_two_12_iv_i_0_0_a2_0_0_1_), + .I2(plm_des1_reg_lfsr_two_12_iv_0_0_0_o4_0[9]), + .I3(plm_des1_one_adv2[1]), + .LO(plm_des1_N_85357_i) + ); + defparam plm_des1_lfsrs_N_85356_i.INIT = 16'hF5FD; + LUT4_L plm_des1_lfsrs_N_85356_i ( + .I0(plm_des1_N_49060_i), + .I1(plm_des1_N_49078_i_0), + .I2(plm_des1_reg_lfsr_two_12_iv_i_0_0_a2_0_0_0_), + .I3(plm_des1_reg_lfsr_two_12_iv_0_0_0_o4_0[9]), + .LO(plm_des1_N_85356_i) + ); + defparam plm_des1_lfsrs_reg_lfsr_two_12_iv_0_0_0_a4_1_9_.INIT = 8'h01; + LUT3 plm_des1_lfsrs_reg_lfsr_two_12_iv_0_0_0_a4_1_9_ ( + .I0(plm_reg_com[1]), + .I1(plm_des1_reg_skp[1]), + .I2(plm_des1_reg_skp[0]), + .O(plm_des1_reg_lfsr_two_12_iv_0_0_0_a4_1[9]) + ); + FDC plm_des1_reg_rx_des_dat_6_ ( + .C(mgt_clk), + .D(plm_des1_reg_rx_des_dat_14[6]), + .Q(plm_rx1_des_dat[6]), + .CLR(plm_rst) + ); + FDC plm_des1_reg_rx_des_dat_5_ ( + .C(mgt_clk), + .D(plm_des1_reg_rx_des_dat_14[5]), + .Q(plm_rx1_des_dat[5]), + .CLR(plm_rst) + ); + FDC plm_des1_reg_rx_des_dat_4_ ( + .C(mgt_clk), + .D(plm_des1_reg_rx_des_dat_14[4]), + .Q(plm_rx1_des_dat[4]), + .CLR(plm_rst) + ); + FDC plm_des1_reg_rx_des_dat_3_ ( + .C(mgt_clk), + .D(plm_des1_reg_rx_des_dat_14[3]), + .Q(plm_rx1_des_dat[3]), + .CLR(plm_rst) + ); + FDC plm_des1_reg_rx_des_dat_2_ ( + .C(mgt_clk), + .D(plm_des1_reg_rx_des_dat_14[2]), + .Q(plm_rx1_des_dat[2]), + .CLR(plm_rst) + ); + FDC plm_des1_reg_rx_des_dat_1_ ( + .C(mgt_clk), + .D(plm_des1_reg_rx_des_dat_14[1]), + .Q(plm_rx1_des_dat[1]), + .CLR(plm_rst) + ); + FDC plm_des1_reg_rx_des_dat_0_ ( + .C(mgt_clk), + .D(plm_des1_reg_rx_des_dat_14[0]), + .Q(plm_rx1_des_dat[0]), + .CLR(plm_rst) + ); + FDC plm_des1_reg_t2n_1_ ( + .C(mgt_clk), + .D(plm_des1_reg_t2n_3[1]), + .Q(plm_des1_reg_t2n[1]), + .CLR(plm_rst) + ); + FDC plm_des1_reg_rx_des_bad_1_ ( + .C(mgt_clk), + .D(plm_des1_reg_bad[1]), + .Q(plm_rx1_des_bad[1]), + .CLR(plm_rst) + ); + FDC plm_des1_reg_rx_des_bad_0_ ( + .C(mgt_clk), + .D(plm_des1_reg_bad[0]), + .Q(plm_rx1_des_bad[0]), + .CLR(plm_rst) + ); + FDC plm_des1_reg_bad_1_ ( + .C(mgt_clk), + .D(plm_des1_N_85318_i), + .Q(plm_des1_reg_bad[1]), + .CLR(plm_rst) + ); + FDC plm_des1_reg_bad_0_ ( + .C(mgt_clk), + .D(plm_des1_N_85319_i), + .Q(plm_des1_reg_bad[0]), + .CLR(plm_rst) + ); + FDC plm_des1_reg_rx_des_dat_15_ ( + .C(mgt_clk), + .D(plm_des1_N_49196_i_0_i), + .Q(plm_rx1_des_dat[15]), + .CLR(plm_rst) + ); + FDC plm_des1_reg_rx_des_dat_14_ ( + .C(mgt_clk), + .D(plm_des1_N_49194_i_0_i), + .Q(plm_rx1_des_dat[14]), + .CLR(plm_rst) + ); + FDC plm_des1_reg_rx_des_dat_13_ ( + .C(mgt_clk), + .D(plm_des1_N_49192_i_0_i), + .Q(plm_rx1_des_dat[13]), + .CLR(plm_rst) + ); + FDC plm_des1_reg_rx_des_dat_12_ ( + .C(mgt_clk), + .D(plm_des1_N_49190_i_0_i), + .Q(plm_rx1_des_dat[12]), + .CLR(plm_rst) + ); + FDC plm_des1_reg_rx_des_dat_11_ ( + .C(mgt_clk), + .D(plm_des1_N_49188_i_0_i), + .Q(plm_rx1_des_dat[11]), + .CLR(plm_rst) + ); + FDC plm_des1_reg_rx_des_dat_10_ ( + .C(mgt_clk), + .D(plm_des1_N_49186_i_0_i), + .Q(plm_rx1_des_dat[10]), + .CLR(plm_rst) + ); + FDC plm_des1_reg_rx_des_dat_9_ ( + .C(mgt_clk), + .D(plm_des1_N_49184_i_0_i), + .Q(plm_rx1_des_dat[9]), + .CLR(plm_rst) + ); + FDC plm_des1_reg_rx_des_dat_8_ ( + .C(mgt_clk), + .D(plm_des1_N_49182_i_0_i), + .Q(plm_rx1_des_dat[8]), + .CLR(plm_rst) + ); + FDC plm_des1_reg_rx_des_dat_7_ ( + .C(mgt_clk), + .D(plm_des1_reg_rx_des_dat_14[7]), + .Q(plm_rx1_des_dat[7]), + .CLR(plm_rst) + ); + FDC plm_des1_reg_skp_0_ ( + .C(mgt_clk), + .D(plm_des1_reg_skp_4[0]), + .Q(plm_des1_reg_skp[0]), + .CLR(plm_rst) + ); + FDC plm_des1_reg_com_1_ ( + .C(mgt_clk), + .D(plm_des1_reg_com_3[1]), + .Q(plm_reg_com[1]), + .CLR(plm_rst) + ); + FDC plm_des1_reg_com_0_ ( + .C(mgt_clk), + .D(plm_des1_reg_com_4[0]), + .Q(plm_reg_com[0]), + .CLR(plm_rst) + ); + FDC plm_des1_reg_rx_des_t2p_1_ ( + .C(mgt_clk), + .D(plm_des1_reg_t2p[1]), + .Q(plm_rx1_des_t2p[1]), + .CLR(plm_rst) + ); + FDC plm_des1_reg_rx_des_t2n_1_ ( + .C(mgt_clk), + .D(plm_des1_reg_t2n[1]), + .Q(plm_rx1_des_t2n[1]), + .CLR(plm_rst) + ); + FDC plm_des1_reg_rx_des_t1p_1_ ( + .C(mgt_clk), + .D(plm_des1_reg_t1p[1]), + .Q(plm_rx1_des_t1p[1]), + .CLR(plm_rst) + ); + FDC plm_des1_reg_rx_des_t1n_1_ ( + .C(mgt_clk), + .D(plm_des1_reg_t1n[1]), + .Q(plm_rx1_des_t1n[1]), + .CLR(plm_rst) + ); + FDC plm_des1_reg_t2p_1_ ( + .C(mgt_clk), + .D(plm_des1_reg_t2p_3[1]), + .Q(plm_des1_reg_t2p[1]), + .CLR(plm_rst) + ); + FDC plm_des1_reg_t1p_1_ ( + .C(mgt_clk), + .D(plm_des1_reg_t1p_3[1]), + .Q(plm_des1_reg_t1p[1]), + .CLR(plm_rst) + ); + FDC plm_des1_reg_t1n_1_ ( + .C(mgt_clk), + .D(plm_des1_reg_t1n_3[1]), + .Q(plm_des1_reg_t1n[1]), + .CLR(plm_rst) + ); + FDC plm_des1_reg_rx_des_sym_1_ ( + .C(mgt_clk), + .D(plm_des1_reg_sym[1]), + .Q(plm_rx1_des_sym[1]), + .CLR(plm_rst) + ); + FDC plm_des1_reg_rx_des_sym_0_ ( + .C(mgt_clk), + .D(plm_des1_reg_sym[0]), + .Q(plm_rx1_des_sym[0]), + .CLR(plm_rst) + ); + FDC plm_des1_reg_skp_1_ ( + .C(mgt_clk), + .D(plm_des1_reg_skp_3[1]), + .Q(plm_des1_reg_skp[1]), + .CLR(plm_rst) + ); + FDC plm_des1_reg_rx_raw_dat_14_ ( + .C(mgt_clk), + .D(plm_des1_reg_dat[14]), + .Q(plm_rx1_raw_dat[14]), + .CLR(plm_rst) + ); + FDC plm_des1_reg_rx_raw_dat_13_ ( + .C(mgt_clk), + .D(plm_des1_reg_dat[13]), + .Q(plm_rx1_raw_dat[13]), + .CLR(plm_rst) + ); + FDC plm_des1_reg_rx_raw_dat_12_ ( + .C(mgt_clk), + .D(plm_des1_reg_dat[12]), + .Q(plm_rx1_raw_dat[12]), + .CLR(plm_rst) + ); + FDC plm_des1_reg_rx_raw_dat_11_ ( + .C(mgt_clk), + .D(plm_des1_reg_dat[11]), + .Q(plm_rx1_raw_dat[11]), + .CLR(plm_rst) + ); + FDC plm_des1_reg_rx_raw_dat_10_ ( + .C(mgt_clk), + .D(plm_des1_reg_dat[10]), + .Q(plm_rx1_raw_dat[10]), + .CLR(plm_rst) + ); + FDC plm_des1_reg_rx_raw_dat_9_ ( + .C(mgt_clk), + .D(plm_des1_reg_dat[9]), + .Q(plm_rx1_raw_dat[9]), + .CLR(plm_rst) + ); + FDC plm_des1_reg_rx_raw_dat_8_ ( + .C(mgt_clk), + .D(plm_des1_reg_dat[8]), + .Q(plm_rx1_raw_dat[8]), + .CLR(plm_rst) + ); + FDC plm_des1_reg_rx_raw_dat_7_ ( + .C(mgt_clk), + .D(plm_des1_reg_dat[7]), + .Q(plm_rx1_raw_dat[7]), + .CLR(plm_rst) + ); + FDC plm_des1_reg_rx_raw_dat_6_ ( + .C(mgt_clk), + .D(plm_des1_reg_dat[6]), + .Q(plm_rx1_raw_dat[6]), + .CLR(plm_rst) + ); + FDC plm_des1_reg_rx_raw_dat_5_ ( + .C(mgt_clk), + .D(plm_des1_reg_dat[5]), + .Q(plm_rx1_raw_dat[5]), + .CLR(plm_rst) + ); + FDC plm_des1_reg_rx_raw_dat_4_ ( + .C(mgt_clk), + .D(plm_des1_reg_dat[4]), + .Q(plm_rx1_raw_dat[4]), + .CLR(plm_rst) + ); + FDC plm_des1_reg_rx_raw_dat_3_ ( + .C(mgt_clk), + .D(plm_des1_reg_dat[3]), + .Q(plm_rx1_raw_dat[3]), + .CLR(plm_rst) + ); + FDC plm_des1_reg_rx_raw_dat_2_ ( + .C(mgt_clk), + .D(plm_des1_reg_dat[2]), + .Q(plm_rx1_raw_dat[2]), + .CLR(plm_rst) + ); + FDC plm_des1_reg_rx_raw_dat_1_ ( + .C(mgt_clk), + .D(plm_des1_reg_dat[1]), + .Q(plm_rx1_raw_dat[1]), + .CLR(plm_rst) + ); + FDC plm_des1_reg_rx_raw_dat_0_ ( + .C(mgt_clk), + .D(plm_des1_reg_dat[0]), + .Q(plm_rx1_raw_dat[0]), + .CLR(plm_rst) + ); + FDC plm_des1_reg_data_7_ ( + .C(mgt_clk), + .D(plm_rx1_data[7]), + .Q(plm_des1_reg_data[7]), + .CLR(plm_rst) + ); + FDC plm_des1_reg_data_6_ ( + .C(mgt_clk), + .D(plm_rx1_data[6]), + .Q(plm_des1_reg_data[6]), + .CLR(plm_rst) + ); + FDC plm_des1_reg_data_5_ ( + .C(mgt_clk), + .D(plm_rx1_data[5]), + .Q(plm_des1_reg_data[5]), + .CLR(plm_rst) + ); + FDC plm_des1_reg_data_4_ ( + .C(mgt_clk), + .D(plm_rx1_data[4]), + .Q(plm_des1_reg_data[4]), + .CLR(plm_rst) + ); + FDC plm_des1_reg_data_3_ ( + .C(mgt_clk), + .D(plm_rx1_data[3]), + .Q(plm_des1_reg_data[3]), + .CLR(plm_rst) + ); + FDC plm_des1_reg_data_2_ ( + .C(mgt_clk), + .D(plm_rx1_data[2]), + .Q(plm_des1_reg_data[2]), + .CLR(plm_rst) + ); + FDC plm_des1_reg_data_1_ ( + .C(mgt_clk), + .D(plm_rx1_data[1]), + .Q(plm_des1_reg_data[1]), + .CLR(plm_rst) + ); + FDC plm_des1_reg_data_0_ ( + .C(mgt_clk), + .D(plm_rx1_data[0]), + .Q(plm_des1_reg_data[0]), + .CLR(plm_rst) + ); + FDC plm_des1_reg_spesh_1_ ( + .C(mgt_clk), + .D(plm_rx1_char_is_k[1]), + .Q(plm_des1_reg_spesh[1]), + .CLR(plm_rst) + ); + FDC plm_des1_reg_spesh_0_ ( + .C(mgt_clk), + .D(plm_rx1_char_is_k[0]), + .Q(plm_des1_reg_spesh[0]), + .CLR(plm_rst) + ); + FDC plm_des1_reg_nitbl_1_ ( + .C(mgt_clk), + .D(plm_rx1_not_in_table[1]), + .Q(plm_des1_reg_nitbl[1]), + .CLR(plm_rst) + ); + FDC plm_des1_reg_nitbl_0_ ( + .C(mgt_clk), + .D(plm_rx1_not_in_table[0]), + .Q(plm_des1_reg_nitbl[0]), + .CLR(plm_rst) + ); + FDC plm_des1_reg_sym_1_ ( + .C(mgt_clk), + .D(plm_des1_reg_sym_3[1]), + .Q(plm_des1_reg_sym[1]), + .CLR(plm_rst) + ); + FDC plm_des1_reg_sym_0_ ( + .C(mgt_clk), + .D(plm_des1_reg_sym_4[0]), + .Q(plm_des1_reg_sym[0]), + .CLR(plm_rst) + ); + FDC plm_des1_reg_rx_raw_dat_15_ ( + .C(mgt_clk), + .D(plm_des1_reg_dat[15]), + .Q(plm_rx1_raw_dat[15]), + .CLR(plm_rst) + ); + FDC plm_des1_reg_dat_4_ ( + .C(mgt_clk), + .D(plm_des1_reg_data[4]), + .Q(plm_des1_reg_dat[4]), + .CLR(plm_rst) + ); + FDC plm_des1_reg_dat_3_ ( + .C(mgt_clk), + .D(plm_des1_reg_data[3]), + .Q(plm_des1_reg_dat[3]), + .CLR(plm_rst) + ); + FDC plm_des1_reg_dat_2_ ( + .C(mgt_clk), + .D(plm_des1_reg_data[2]), + .Q(plm_des1_reg_dat[2]), + .CLR(plm_rst) + ); + FDC plm_des1_reg_dat_1_ ( + .C(mgt_clk), + .D(plm_des1_reg_data[1]), + .Q(plm_des1_reg_dat[1]), + .CLR(plm_rst) + ); + FDC plm_des1_reg_dat_0_ ( + .C(mgt_clk), + .D(plm_des1_reg_data[0]), + .Q(plm_des1_reg_dat[0]), + .CLR(plm_rst) + ); + FDC plm_des1_reg_kkk_1_ ( + .C(mgt_clk), + .D(plm_des1_reg_spesh[1]), + .Q(plm_des1_reg_kkk[1]), + .CLR(plm_rst) + ); + FDC plm_des1_reg_kkk_0_ ( + .C(mgt_clk), + .D(plm_des1_reg_spesh[0]), + .Q(plm_des1_reg_kkk[0]), + .CLR(plm_rst) + ); + FDC plm_des1_reg_data_15_ ( + .C(mgt_clk), + .D(plm_rx1_data[15]), + .Q(plm_des1_reg_data[15]), + .CLR(plm_rst) + ); + FDC plm_des1_reg_data_14_ ( + .C(mgt_clk), + .D(plm_rx1_data[14]), + .Q(plm_des1_reg_data[14]), + .CLR(plm_rst) + ); + FDC plm_des1_reg_data_13_ ( + .C(mgt_clk), + .D(plm_rx1_data[13]), + .Q(plm_des1_reg_data[13]), + .CLR(plm_rst) + ); + FDC plm_des1_reg_data_12_ ( + .C(mgt_clk), + .D(plm_rx1_data[12]), + .Q(plm_des1_reg_data[12]), + .CLR(plm_rst) + ); + FDC plm_des1_reg_data_11_ ( + .C(mgt_clk), + .D(plm_rx1_data[11]), + .Q(plm_des1_reg_data[11]), + .CLR(plm_rst) + ); + FDC plm_des1_reg_data_10_ ( + .C(mgt_clk), + .D(plm_rx1_data[10]), + .Q(plm_des1_reg_data[10]), + .CLR(plm_rst) + ); + FDC plm_des1_reg_data_9_ ( + .C(mgt_clk), + .D(plm_rx1_data[9]), + .Q(plm_des1_reg_data[9]), + .CLR(plm_rst) + ); + FDC plm_des1_reg_data_8_ ( + .C(mgt_clk), + .D(plm_rx1_data[8]), + .Q(plm_des1_reg_data[8]), + .CLR(plm_rst) + ); + FDC plm_des1_reg_dat_15_ ( + .C(mgt_clk), + .D(plm_des1_reg_data[15]), + .Q(plm_des1_reg_dat[15]), + .CLR(plm_rst) + ); + FDC plm_des1_reg_dat_14_ ( + .C(mgt_clk), + .D(plm_des1_reg_data[14]), + .Q(plm_des1_reg_dat[14]), + .CLR(plm_rst) + ); + FDC plm_des1_reg_dat_13_ ( + .C(mgt_clk), + .D(plm_des1_reg_data[13]), + .Q(plm_des1_reg_dat[13]), + .CLR(plm_rst) + ); + FDC plm_des1_reg_dat_12_ ( + .C(mgt_clk), + .D(plm_des1_reg_data[12]), + .Q(plm_des1_reg_dat[12]), + .CLR(plm_rst) + ); + FDC plm_des1_reg_dat_11_ ( + .C(mgt_clk), + .D(plm_des1_reg_data[11]), + .Q(plm_des1_reg_dat[11]), + .CLR(plm_rst) + ); + FDC plm_des1_reg_dat_10_ ( + .C(mgt_clk), + .D(plm_des1_reg_data[10]), + .Q(plm_des1_reg_dat[10]), + .CLR(plm_rst) + ); + FDC plm_des1_reg_dat_9_ ( + .C(mgt_clk), + .D(plm_des1_reg_data[9]), + .Q(plm_des1_reg_dat[9]), + .CLR(plm_rst) + ); + FDC plm_des1_reg_dat_8_ ( + .C(mgt_clk), + .D(plm_des1_reg_data[8]), + .Q(plm_des1_reg_dat[8]), + .CLR(plm_rst) + ); + FDC plm_des1_reg_dat_7_ ( + .C(mgt_clk), + .D(plm_des1_reg_data[7]), + .Q(plm_des1_reg_dat[7]), + .CLR(plm_rst) + ); + FDC plm_des1_reg_dat_6_ ( + .C(mgt_clk), + .D(plm_des1_reg_data[6]), + .Q(plm_des1_reg_dat[6]), + .CLR(plm_rst) + ); + FDC plm_des1_reg_dat_5_ ( + .C(mgt_clk), + .D(plm_des1_reg_data[5]), + .Q(plm_des1_reg_dat[5]), + .CLR(plm_rst) + ); + FDPE plm_des1_reg_lfsr_one_15_ ( + .PRE(plm_rst), + .CE(plm_des1_reg_lfsr_one32_i), + .C(mgt_clk), + .D(plm_des1_N_87696_i), + .Q(plm_des1_reg_lfsr_one_15__502) + ); + FDPE plm_des1_reg_lfsr_one_14_ ( + .PRE(plm_rst), + .CE(plm_des1_reg_lfsr_one32_i), + .C(mgt_clk), + .D(plm_des1_N_87695_i), + .Q(plm_des1_reg_lfsr_one_14__653) + ); + FDPE plm_des1_reg_lfsr_one_13_ ( + .PRE(plm_rst), + .CE(plm_des1_reg_lfsr_one32_i), + .C(mgt_clk), + .D(plm_des1_N_87694_i), + .Q(plm_des1_reg_lfsr_one_13__505) + ); + FDPE plm_des1_reg_lfsr_one_12_ ( + .PRE(plm_rst), + .CE(plm_des1_reg_lfsr_one32_i), + .C(mgt_clk), + .D(plm_des1_N_85355_i), + .Q(plm_des1_reg_lfsr_one_12__624) + ); + FDPE plm_des1_reg_lfsr_one_11_ ( + .PRE(plm_rst), + .CE(plm_des1_reg_lfsr_one32_i), + .C(mgt_clk), + .D(plm_des1_N_87693_i), + .Q(plm_des1_reg_lfsr_one_11__640) + ); + FDPE plm_des1_reg_lfsr_one_10_ ( + .PRE(plm_rst), + .CE(plm_des1_reg_lfsr_one32_i), + .C(mgt_clk), + .D(plm_des1_N_85354_i), + .Q(plm_des1_reg_lfsr_one_10__968) + ); + FDPE plm_des1_reg_lfsr_one_9_ ( + .PRE(plm_rst), + .CE(plm_des1_reg_lfsr_one32_i), + .C(mgt_clk), + .D(plm_des1_N_85353_i), + .Q(plm_des1_reg_lfsr_one_9__969) + ); + FDPE plm_des1_reg_lfsr_one_8_ ( + .PRE(plm_rst), + .CE(plm_des1_reg_lfsr_one32_i), + .C(mgt_clk), + .D(plm_des1_N_85352_i), + .Q(plm_des1_reg_lfsr_one_8__970) + ); + FDPE plm_des1_reg_lfsr_one_7_ ( + .PRE(plm_rst), + .CE(plm_des1_reg_lfsr_one32_i), + .C(mgt_clk), + .D(plm_des1_N_85351_i), + .Q(plm_des1_reg_lfsr_one_7__971) + ); + FDPE plm_des1_reg_lfsr_one_6_ ( + .PRE(plm_rst), + .CE(plm_des1_reg_lfsr_one32_i), + .C(mgt_clk), + .D(plm_des1_N_85350_i), + .Q(plm_des1_reg_lfsr_one_6__972) + ); + FDPE plm_des1_reg_lfsr_one_5_ ( + .PRE(plm_rst), + .CE(plm_des1_reg_lfsr_one32_i), + .C(mgt_clk), + .D(plm_des1_N_85349_i), + .Q(plm_des1_reg_lfsr_one_5__973) + ); + FDPE plm_des1_reg_lfsr_one_4_ ( + .PRE(plm_rst), + .CE(plm_des1_reg_lfsr_one32_i), + .C(mgt_clk), + .D(plm_des1_N_87692_i), + .Q(plm_des1_reg_lfsr_one_4__974) + ); + FDPE plm_des1_reg_lfsr_one_3_ ( + .PRE(plm_rst), + .CE(plm_des1_reg_lfsr_one32_i), + .C(mgt_clk), + .D(plm_des1_N_85348_i), + .Q(plm_des1_reg_lfsr_one_3__504) + ); + FDPE plm_des1_reg_lfsr_one_2_ ( + .PRE(plm_rst), + .CE(plm_des1_reg_lfsr_one32_i), + .C(mgt_clk), + .D(plm_des1_N_87691_i), + .Q(plm_des1_reg_lfsr_one_2__975) + ); + FDPE plm_des1_reg_lfsr_one_1_ ( + .PRE(plm_rst), + .CE(plm_des1_reg_lfsr_one32_i), + .C(mgt_clk), + .D(plm_des1_N_87690_i), + .Q(plm_des1_reg_lfsr_one_1__501) + ); + FDPE plm_des1_reg_lfsr_one_0_ ( + .PRE(plm_rst), + .CE(plm_des1_reg_lfsr_one32_i), + .C(mgt_clk), + .D(plm_des1_N_87689_i), + .Q(plm_des1_reg_lfsr_one_0__639) + ); + FDPE plm_des1_reg_lfsr_two_15_ ( + .PRE(plm_rst), + .CE(plm_des1_reg_lfsr_one32_i), + .C(mgt_clk), + .D(plm_des1_N_85363_i), + .Q(plm_des1_reg_lfsr_two_15__546) + ); + FDPE plm_des1_reg_lfsr_two_14_ ( + .PRE(plm_rst), + .CE(plm_des1_reg_lfsr_one32_i), + .C(mgt_clk), + .D(plm_des1_N_85362_i), + .Q(plm_des1_reg_lfsr_two_14__652) + ); + FDPE plm_des1_reg_lfsr_two_13_ ( + .PRE(plm_rst), + .CE(plm_des1_reg_lfsr_one32_i), + .C(mgt_clk), + .D(plm_des1_N_85361_i), + .Q(plm_des1_reg_lfsr_two_13__545) + ); + FDCE plm_des1_reg_lfsr_two_12_ ( + .CE(plm_des1_reg_lfsr_one32_i), + .C(mgt_clk), + .D(plm_des1_N_9543_i), + .Q(plm_des1_reg_lfsr_two_12__976), + .CLR(plm_rst) + ); + FDPE plm_des1_reg_lfsr_two_11_ ( + .PRE(plm_rst), + .CE(plm_des1_reg_lfsr_one32_i), + .C(mgt_clk), + .D(plm_des1_N_85360_i), + .Q(plm_des1_reg_lfsr_two_11__544) + ); + FDCE plm_des1_reg_lfsr_two_10_ ( + .CE(plm_des1_reg_lfsr_one32_i), + .C(mgt_clk), + .D(plm_des1_N_9545_i), + .Q(plm_des1_reg_lfsr_two_10__977), + .CLR(plm_rst) + ); + FDCE plm_des1_reg_lfsr_two_9_ ( + .CE(plm_des1_reg_lfsr_one32_i), + .C(mgt_clk), + .D(plm_des1_N_9546_i), + .Q(plm_des1_reg_lfsr_two_9__978), + .CLR(plm_rst) + ); + FDCE plm_des1_reg_lfsr_two_8_ ( + .CE(plm_des1_reg_lfsr_one32_i), + .C(mgt_clk), + .D(plm_des1_N_9547_i), + .Q(plm_des1_reg_lfsr_two_8__979), + .CLR(plm_rst) + ); + FDCE plm_des1_reg_lfsr_two_7_ ( + .CE(plm_des1_reg_lfsr_one32_i), + .C(mgt_clk), + .D(plm_des1_N_9548_i), + .Q(plm_des1_reg_lfsr_two_7__980), + .CLR(plm_rst) + ); + FDCE plm_des1_reg_lfsr_two_6_ ( + .CE(plm_des1_reg_lfsr_one32_i), + .C(mgt_clk), + .D(plm_des1_N_9549_i), + .Q(plm_des1_reg_lfsr_two_6__981), + .CLR(plm_rst) + ); + FDCE plm_des1_reg_lfsr_two_5_ ( + .CE(plm_des1_reg_lfsr_one32_i), + .C(mgt_clk), + .D(plm_des1_N_9550_i), + .Q(plm_des1_reg_lfsr_two_5__982), + .CLR(plm_rst) + ); + FDPE plm_des1_reg_lfsr_two_4_ ( + .PRE(plm_rst), + .CE(plm_des1_reg_lfsr_one32_i), + .C(mgt_clk), + .D(plm_des1_N_85359_i), + .Q(plm_des1_reg_lfsr_two_4__654) + ); + FDCE plm_des1_reg_lfsr_two_3_ ( + .CE(plm_des1_reg_lfsr_one32_i), + .C(mgt_clk), + .D(plm_des1_N_9552_i), + .Q(plm_des1_reg_lfsr_two_3__983), + .CLR(plm_rst) + ); + FDPE plm_des1_reg_lfsr_two_2_ ( + .PRE(plm_rst), + .CE(plm_des1_reg_lfsr_one32_i), + .C(mgt_clk), + .D(plm_des1_N_85358_i), + .Q(plm_des1_reg_lfsr_two_2__659) + ); + FDPE plm_des1_reg_lfsr_two_1_ ( + .PRE(plm_rst), + .CE(plm_des1_reg_lfsr_one32_i), + .C(mgt_clk), + .D(plm_des1_N_85357_i), + .Q(plm_des1_reg_lfsr_two_1__658) + ); + FDPE plm_des1_reg_lfsr_two_0_ ( + .PRE(plm_rst), + .CE(plm_des1_reg_lfsr_one32_i), + .C(mgt_clk), + .D(plm_des1_N_85356_i), + .Q(plm_des1_reg_lfsr_two_0__543) + ); + defparam plm_des2_input_decoder_reg_sym_4_0_a2_0_.INIT = 4'h1; + LUT2 plm_des2_input_decoder_reg_sym_4_0_a2_0_ ( + .I0(plm_des2_reg_nitbl[0]), + .I1(plm_des2_reg_spesh[0]), + .O(plm_des2_reg_sym_4[0]) + ); + defparam plm_des2_input_decoder_reg_sym_3_0_a2_1_.INIT = 4'h1; + LUT2 plm_des2_input_decoder_reg_sym_3_0_a2_1_ ( + .I0(plm_des2_reg_nitbl[1]), + .I1(plm_des2_reg_spesh[1]), + .O(plm_des2_reg_sym_3[1]) + ); + defparam plm_des2_descram_reg_rx_des_dat_14_sn_m1_0_a2_0_a3_0_a2_0_a2.INIT = 4'h1; + LUT2 plm_des2_descram_reg_rx_des_dat_14_sn_m1_0_a2_0_a3_0_a2_0_a2 ( + .I0(plm_des2_reg_kkk[0]), + .I1(plm_reg_dis), + .O(plm_des2_m1_0_a2_0_a3_0_a2_0_a2_1) + ); + defparam plm_des2_lfsrs_reg_lfsr_one_12_0_iv_i_i_o4_0_.INIT = 4'h1; + LUT2 plm_des2_lfsrs_reg_lfsr_one_12_0_iv_i_i_o4_0_ ( + .I0(plm_des2_reg_skp[0]), + .I1(plm_des2_reg_skp[1]), + .O(plm_des2_N_49058_i) + ); + defparam plm_des2_descram_reg_rx_des_dat_7_i_x2_0_x2_0_o4_0_8_.INIT = 4'h1; + LUT2 plm_des2_descram_reg_rx_des_dat_7_i_x2_0_x2_0_o4_0_8_ ( + .I0(plm_des2_reg_kkk[1]), + .I1(plm_reg_dis), + .O(plm_des2_N_49065_i) + ); + defparam plm_des2_lfsrs_reg_lfsr_two_12_0_iv_0_o2_12_.INIT = 4'h1; + LUT2 plm_des2_lfsrs_reg_lfsr_two_12_0_iv_0_o2_12_ ( + .I0(plm_reg_com_0[0]), + .I1(plm_reg_com_0[1]), + .O(plm_des2_reg_lfsr_two_12_0_iv_0_o2[12]) + ); + defparam plm_des2_one_adv2_1_15_.INIT = 4'h6; + LUT2 plm_des2_one_adv2_1_15_ ( + .I0(plm_des2_reg_lfsr_one_10__1002), + .I1(plm_des2_reg_lfsr_one_11__642), + .O(plm_des2_one_adv2_1_15__984) + ); + defparam plm_des2_one_adv2_1_13_.INIT = 4'h6; + LUT2 plm_des2_one_adv2_1_13_ ( + .I0(plm_des2_reg_lfsr_one_8__1004), + .I1(plm_des2_reg_lfsr_one_9__1003), + .O(plm_des2_one_adv2_1_13__985) + ); + defparam plm_des2_one_adv2_1_9_.INIT = 4'h6; + LUT2 plm_des2_one_adv2_1_9_ ( + .I0(plm_des2_reg_lfsr_one_4__1008), + .I1(plm_des2_reg_lfsr_one_5__1007), + .O(plm_des2_one_adv2_1_9__992) + ); + defparam plm_des2_one_adv2_1_6_.INIT = 4'h6; + LUT2 plm_des2_one_adv2_1_6_ ( + .I0(plm_des2_reg_lfsr_one_1__519), + .I1(plm_des2_reg_lfsr_one_12__1001), + .O(plm_des2_one_adv2_1_6__990) + ); + defparam plm_des2_one_adv2_1_5_.INIT = 4'h6; + LUT2 plm_des2_one_adv2_1_5_ ( + .I0(plm_des2_reg_lfsr_one_2__1009), + .I1(plm_des2_reg_lfsr_one_13__523), + .O(plm_des2_one_adv2_1_5__991) + ); + defparam plm_des2_two_adv2_1_14_.INIT = 4'h6; + LUT2 plm_des2_two_adv2_1_14_ ( + .I0(plm_des2_reg_lfsr_two_9__1012), + .I1(plm_des2_reg_lfsr_two_10__1011), + .O(plm_des2_two_adv2_1_14__986) + ); + defparam plm_des2_two_adv2_1_12_.INIT = 4'h6; + LUT2 plm_des2_two_adv2_1_12_ ( + .I0(plm_des2_reg_lfsr_two_7__1014), + .I1(plm_des2_reg_lfsr_two_8__1013), + .O(plm_des2_two_adv2_1_12__987) + ); + defparam plm_des2_two_adv2_1_10_.INIT = 4'h6; + LUT2 plm_des2_two_adv2_1_10_ ( + .I0(plm_des2_reg_lfsr_two_5__1016), + .I1(plm_des2_reg_lfsr_two_6__1015), + .O(plm_des2_two_adv2_1_10__993) + ); + defparam plm_des2_two_adv2_1_7_.INIT = 4'h6; + LUT2 plm_des2_two_adv2_1_7_ ( + .I0(plm_des2_reg_lfsr_two_2__663), + .I1(plm_des2_reg_lfsr_two_13__487), + .O(plm_des2_two_adv2_1_7__989) + ); + defparam plm_des2_two_adv2_1_1_.INIT = 4'h6; + LUT2 plm_des2_two_adv2_1_1_ ( + .I0(plm_des2_reg_lfsr_two_12__1010), + .I1(plm_des2_reg_lfsr_two_13__487), + .O(plm_des2_two_adv2_1_1__988) + ); + defparam plm_des2_input_decoder_reg_bad_3_i_a7_2_0_1_.INIT = 4'h4; + LUT2_L plm_des2_input_decoder_reg_bad_3_i_a7_2_0_1_ ( + .I0(plm_des2_reg_data[13]), + .I1(plm_des2_reg_data[15]), + .LO(plm_des2_reg_bad_3_i_a7_2_0[1]) + ); + defparam plm_des2_input_decoder_reg_bad_4_i_a7_2_0_0_.INIT = 4'h4; + LUT2_L plm_des2_input_decoder_reg_bad_4_i_a7_2_0_0_ ( + .I0(plm_des2_reg_data[5]), + .I1(plm_des2_reg_data[7]), + .LO(plm_des2_reg_bad_4_i_a7_2_0[0]) + ); + defparam plm_des2_two_adv2_0_4_.INIT = 4'h6; + LUT2 plm_des2_two_adv2_0_4_ ( + .I0(plm_des2_reg_lfsr_two_0__485), + .I1(plm_des2_reg_lfsr_two_1__662), + .O(plm_des2_two_adv2_0[4]) + ); + defparam plm_des2_lfsrs_reg_lfsr_one32_i.INIT = 4'h7; + LUT2 plm_des2_lfsrs_reg_lfsr_one32_i ( + .I0(plm_des2_reg_skp[0]), + .I1(plm_des2_reg_skp[1]), + .O(plm_des2_reg_lfsr_one32_i) + ); + defparam plm_des2_input_decoder_reg_bad_4_i_x2_0_.INIT = 16'hE111; + LUT4 plm_des2_input_decoder_reg_bad_4_i_x2_0_ ( + .I0(plm_des2_reg_data[0]), + .I1(plm_des2_reg_data[1]), + .I2(plm_des2_reg_data[6]), + .I3(plm_des2_reg_data[7]), + .O(plm_des2_N_14130_i) + ); + defparam plm_des2_input_decoder_reg_bad_4_i_x2_0_0_.INIT = 16'h7888; + LUT4 plm_des2_input_decoder_reg_bad_4_i_x2_0_0_ ( + .I0(plm_des2_reg_data[0]), + .I1(plm_des2_reg_data[1]), + .I2(plm_des2_reg_data[2]), + .I3(plm_des2_reg_data[3]), + .O(plm_des2_N_14131_i) + ); + defparam plm_des2_input_decoder_reg_bad_3_i_x2_1_.INIT = 16'hE111; + LUT4 plm_des2_input_decoder_reg_bad_3_i_x2_1_ ( + .I0(plm_des2_reg_data[8]), + .I1(plm_des2_reg_data[9]), + .I2(plm_des2_reg_data[14]), + .I3(plm_des2_reg_data[15]), + .O(plm_des2_N_14164_i) + ); + defparam plm_des2_input_decoder_reg_bad_3_i_x2_0_1_.INIT = 16'h7888; + LUT4 plm_des2_input_decoder_reg_bad_3_i_x2_0_1_ ( + .I0(plm_des2_reg_data[8]), + .I1(plm_des2_reg_data[9]), + .I2(plm_des2_reg_data[10]), + .I3(plm_des2_reg_data[11]), + .O(plm_des2_N_14165_i) + ); + defparam plm_des2_input_decoder_reg_skp_3_0_a7_3_1_.INIT = 16'h1000; + LUT4 plm_des2_input_decoder_reg_skp_3_0_a7_3_1_ ( + .I0(plm_des2_reg_data[8]), + .I1(plm_des2_reg_data[9]), + .I2(plm_des2_reg_data[10]), + .I3(plm_des2_reg_data[11]), + .O(plm_des2_reg_skp_3_3[1]) + ); + defparam plm_des2_input_decoder_reg_com_3_0_a7_2_1_.INIT = 16'h0800; + LUT4 plm_des2_input_decoder_reg_com_3_0_a7_2_1_ ( + .I0(plm_des2_reg_data[12]), + .I1(plm_des2_reg_data[13]), + .I2(plm_des2_reg_nitbl[1]), + .I3(plm_des2_reg_spesh[1]), + .O(plm_des2_reg_pad_3_5[1]) + ); + defparam plm_des2_input_decoder_reg_t1n_3_0_a7_1_1_.INIT = 16'h0800; + LUT4 plm_des2_input_decoder_reg_t1n_3_0_a7_1_1_ ( + .I0(plm_des2_reg_data[12]), + .I1(plm_des2_reg_data[13]), + .I2(plm_des2_reg_data[14]), + .I3(plm_des2_reg_data[15]), + .O(plm_des2_reg_t2n_3_3[1]) + ); + defparam plm_des2_input_decoder_reg_skp_4_0_a7_3_0_.INIT = 16'h1000; + LUT4 plm_des2_input_decoder_reg_skp_4_0_a7_3_0_ ( + .I0(plm_des2_reg_data[0]), + .I1(plm_des2_reg_data[1]), + .I2(plm_des2_reg_data[2]), + .I3(plm_des2_reg_data[3]), + .O(plm_des2_reg_skp_4_3[0]) + ); + defparam plm_des2_input_decoder_reg_com_4_0_a7_2_0_.INIT = 16'h0800; + LUT4 plm_des2_input_decoder_reg_com_4_0_a7_2_0_ ( + .I0(plm_des2_reg_data[4]), + .I1(plm_des2_reg_data[5]), + .I2(plm_des2_reg_nitbl[0]), + .I3(plm_des2_reg_spesh[0]), + .O(plm_des2_reg_pad_4_5[0]) + ); + defparam plm_des2_input_decoder_reg_t1n_4_0_a7_1_0_.INIT = 16'h0800; + LUT4 plm_des2_input_decoder_reg_t1n_4_0_a7_1_0_ ( + .I0(plm_des2_reg_data[4]), + .I1(plm_des2_reg_data[5]), + .I2(plm_des2_reg_data[6]), + .I3(plm_des2_reg_data[7]), + .O(plm_des2_reg_t2n_4_3[0]) + ); + defparam plm_des2_lfsrs_reg_lfsr_two_12_iv_0_0_o4_9_.INIT = 8'h23; + LUT3 plm_des2_lfsrs_reg_lfsr_two_12_iv_0_0_o4_9_ ( + .I0(plm_reg_com_0[1]), + .I1(plm_des2_reg_skp[0]), + .I2(plm_des2_reg_skp[1]), + .O(plm_des2_reg_lfsr_two_12_iv_0_0_o4[9]) + ); + defparam plm_des2_lfsrs_reg_lfsr_two_12_iv_0_0_o2_9_.INIT = 8'h15; + LUT3 plm_des2_lfsrs_reg_lfsr_two_12_iv_0_0_o2_9_ ( + .I0(plm_reg_com_0[0]), + .I1(plm_reg_com_0[1]), + .I2(plm_des2_reg_skp[0]), + .O(plm_des2_N_49061_i) + ); + defparam plm_des2_two_adv2_1_6_.INIT = 8'h96; + LUT3 plm_des2_two_adv2_1_6_ ( + .I0(plm_des2_reg_lfsr_two_3__1017), + .I1(plm_des2_reg_lfsr_two_12__1010), + .I2(plm_des2_reg_lfsr_two_14__655), + .O(plm_des2_two_adv2_1_6__995) + ); + defparam plm_des2_two_adv2_15_.INIT = 16'h6996; + LUT4 plm_des2_two_adv2_15_ ( + .I0(plm_des2_reg_lfsr_two_10__1011), + .I1(plm_des2_reg_lfsr_two_11__486), + .I2(plm_des2_reg_lfsr_two_12__1010), + .I3(plm_des2_reg_lfsr_two_15__488), + .O(plm_des2_two_adv2_15__996) + ); + defparam plm_des2_input_decoder_reg_t1n_4_0_a7_1_0_0_.INIT = 8'h08; + LUT3 plm_des2_input_decoder_reg_t1n_4_0_a7_1_0_0_ ( + .I0(plm_des2_reg_sym_4[0]), + .I1(plm_des2_reg_data[2]), + .I2(plm_des2_reg_data[3]), + .O(plm_des2_reg_t1n_4_1[0]) + ); + defparam plm_des2_input_decoder_reg_t1n_3_0_a7_1_0_1_.INIT = 8'h08; + LUT3 plm_des2_input_decoder_reg_t1n_3_0_a7_1_0_1_ ( + .I0(plm_des2_reg_sym_3[1]), + .I1(plm_des2_reg_data[10]), + .I2(plm_des2_reg_data[11]), + .O(plm_des2_reg_t1n_3_1[1]) + ); + defparam plm_des2_one_adv2_2_.INIT = 8'h96; + LUT3 plm_des2_one_adv2_2_ ( + .I0(plm_des2_one_adv2_1_5__991), + .I1(plm_des2_reg_lfsr_one_14__656), + .I2(plm_des2_reg_lfsr_one_15__520), + .O(plm_des2_one_adv2[2]) + ); + defparam plm_des2_one_adv2_1_.INIT = 8'h96; + LUT3 plm_des2_one_adv2_1_ ( + .I0(plm_des2_one_adv2_1_6__990), + .I1(plm_des2_reg_lfsr_one_13__523), + .I2(plm_des2_reg_lfsr_one_14__656), + .O(plm_des2_one_adv2[1]) + ); + defparam plm_des2_two_adv2_12_.INIT = 8'h96; + LUT3 plm_des2_two_adv2_12_ ( + .I0(plm_des2_reg_lfsr_two_9__1012), + .I1(plm_des2_reg_lfsr_two_12__1010), + .I2(plm_des2_two_adv2_1_12__987), + .O(plm_des2_two_adv2_12__997) + ); + defparam plm_des2_two_adv2_10_.INIT = 8'h96; + LUT3 plm_des2_two_adv2_10_ ( + .I0(plm_des2_reg_lfsr_two_7__1014), + .I1(plm_des2_reg_lfsr_two_10__1011), + .I2(plm_des2_two_adv2_1_10__993), + .O(plm_des2_two_adv2_10__998) + ); + defparam plm_des2_one_adv2_15_.INIT = 8'h96; + LUT3 plm_des2_one_adv2_15_ ( + .I0(plm_des2_one_adv2_1_15__984), + .I1(plm_des2_reg_lfsr_one_12__1001), + .I2(plm_des2_reg_lfsr_one_15__520), + .O(plm_des2_one_adv2[15]) + ); + defparam plm_des2_one_adv2_14_.INIT = 8'h96; + LUT3 plm_des2_one_adv2_14_ ( + .I0(plm_des2_one_adv2_1_15__984), + .I1(plm_des2_reg_lfsr_one_9__1003), + .I2(plm_des2_reg_lfsr_one_14__656), + .O(plm_des2_one_adv2[14]) + ); + defparam plm_des2_one_adv2_13_.INIT = 8'h96; + LUT3 plm_des2_one_adv2_13_ ( + .I0(plm_des2_one_adv2_1_13__985), + .I1(plm_des2_reg_lfsr_one_10__1002), + .I2(plm_des2_reg_lfsr_one_13__523), + .O(plm_des2_one_adv2[13]) + ); + defparam plm_des2_one_adv2_12_.INIT = 8'h96; + LUT3 plm_des2_one_adv2_12_ ( + .I0(plm_des2_one_adv2_1_13__985), + .I1(plm_des2_reg_lfsr_one_7__1005), + .I2(plm_des2_reg_lfsr_one_12__1001), + .O(plm_des2_one_adv2[12]) + ); + defparam plm_des2_one_adv2_11_.INIT = 16'h6996; + LUT4 plm_des2_one_adv2_11_ ( + .I0(plm_des2_reg_lfsr_one_6__1006), + .I1(plm_des2_reg_lfsr_one_7__1005), + .I2(plm_des2_reg_lfsr_one_8__1004), + .I3(plm_des2_reg_lfsr_one_11__642), + .O(plm_des2_one_adv2[11]) + ); + defparam plm_des2_one_adv2_10_.INIT = 16'h6996; + LUT4 plm_des2_one_adv2_10_ ( + .I0(plm_des2_reg_lfsr_one_5__1007), + .I1(plm_des2_reg_lfsr_one_6__1006), + .I2(plm_des2_reg_lfsr_one_7__1005), + .I3(plm_des2_reg_lfsr_one_10__1002), + .O(plm_des2_one_adv2[10]) + ); + defparam plm_des2_input_decoder_reg_t1p_3_0_a7_1_1_.INIT = 16'h0010; + LUT4 plm_des2_input_decoder_reg_t1p_3_0_a7_1_1_ ( + .I0(plm_des2_reg_data[12]), + .I1(plm_des2_reg_data[13]), + .I2(plm_des2_reg_data[14]), + .I3(plm_des2_reg_data[15]), + .O(plm_des2_reg_t1p_3_1[1]) + ); + defparam plm_des2_input_decoder_reg_t1p_4_0_a7_1_0_.INIT = 16'h0010; + LUT4 plm_des2_input_decoder_reg_t1p_4_0_a7_1_0_ ( + .I0(plm_des2_reg_data[4]), + .I1(plm_des2_reg_data[5]), + .I2(plm_des2_reg_data[6]), + .I3(plm_des2_reg_data[7]), + .O(plm_des2_reg_t1p_4_1[0]) + ); + defparam plm_des2_two_adv2_1_8_.INIT = 8'h96; + LUT3 plm_des2_two_adv2_1_8_ ( + .I0(plm_des2_reg_lfsr_two_4__664), + .I1(plm_des2_reg_lfsr_two_5__1016), + .I2(plm_des2_reg_lfsr_two_8__1013), + .O(plm_des2_two_adv2_1_8__994) + ); + defparam plm_des2_input_decoder_reg_t2n_4_0_a7_0_2_0_.INIT = 16'h0400; + LUT4 plm_des2_input_decoder_reg_t2n_4_0_a7_0_2_0_ ( + .I0(plm_des2_reg_data[0]), + .I1(plm_des2_reg_data[1]), + .I2(plm_des2_reg_data[2]), + .I3(plm_des2_reg_data[3]), + .O(plm_des2_reg_t2n_4_0_a7_0_2[0]) + ); + defparam plm_des2_input_decoder_reg_t2n_3_0_a7_0_2_1_.INIT = 16'h0400; + LUT4 plm_des2_input_decoder_reg_t2n_3_0_a7_0_2_1_ ( + .I0(plm_des2_reg_data[8]), + .I1(plm_des2_reg_data[9]), + .I2(plm_des2_reg_data[10]), + .I3(plm_des2_reg_data[11]), + .O(plm_des2_reg_t2n_3_0_a7_0_2[1]) + ); + defparam plm_des2_input_decoder_reg_pad_4_0_a7_0_0_.INIT = 16'h2000; + LUT4 plm_des2_input_decoder_reg_pad_4_0_a7_0_0_ ( + .I0(plm_des2_reg_data[2]), + .I1(plm_des2_reg_data[3]), + .I2(plm_des2_reg_data[6]), + .I3(plm_des2_reg_data[7]), + .O(plm_des2_reg_pad_4_0_a7_0[0]) + ); + defparam plm_des2_input_decoder_reg_pad_3_0_a7_0_1_.INIT = 16'h2000; + LUT4 plm_des2_input_decoder_reg_pad_3_0_a7_0_1_ ( + .I0(plm_des2_reg_data[10]), + .I1(plm_des2_reg_data[11]), + .I2(plm_des2_reg_data[14]), + .I3(plm_des2_reg_data[15]), + .O(plm_des2_reg_pad_3_0_a7_0[1]) + ); + defparam plm_des2_input_decoder_reg_skp_4_0_a7_1_0_.INIT = 16'h0002; + LUT4 plm_des2_input_decoder_reg_skp_4_0_a7_1_0_ ( + .I0(plm_des2_reg_data[4]), + .I1(plm_des2_reg_data[5]), + .I2(plm_des2_reg_data[6]), + .I3(plm_des2_reg_data[7]), + .O(plm_des2_reg_skp_4_0_a7_1[0]) + ); + defparam plm_des2_input_decoder_reg_skp_3_0_a7_1_1_.INIT = 16'h0002; + LUT4 plm_des2_input_decoder_reg_skp_3_0_a7_1_1_ ( + .I0(plm_des2_reg_data[12]), + .I1(plm_des2_reg_data[13]), + .I2(plm_des2_reg_data[14]), + .I3(plm_des2_reg_data[15]), + .O(plm_des2_reg_skp_3_0_a7_1[1]) + ); + defparam plm_des2_lfsrs_reg_lfsr_two_12_iv_i_0_a2_15_.INIT = 4'h4; + LUT2_L plm_des2_lfsrs_reg_lfsr_two_12_iv_i_0_a2_15_ ( + .I0(plm_des2_reg_lfsr_two_12_iv_0_0_o4[9]), + .I1(plm_des2_one_adv2[15]), + .LO(plm_des2_reg_lfsr_two_12_iv_i_0_a2[15]) + ); + defparam plm_des2_lfsrs_reg_lfsr_two_12_iv_i_0_a2_0_14_.INIT = 8'h48; + LUT3 plm_des2_lfsrs_reg_lfsr_two_12_iv_i_0_a2_0_14_ ( + .I0(N_49141_i_0), + .I1(plm_des2_reg_lfsr_two_12_iv_0_0_a4_1[9]), + .I2(plm_des2_two_adv2_1_14__986), + .O(plm_des2_reg_lfsr_two_12_iv_i_0_a2_0_14_) + ); + defparam plm_des2_lfsrs_reg_lfsr_two_12_iv_i_0_a2_0_13_.INIT = 16'h8228; + LUT4 plm_des2_lfsrs_reg_lfsr_two_12_iv_i_0_a2_0_13_ ( + .I0(plm_des2_reg_lfsr_two_12_iv_0_0_a4_1[9]), + .I1(plm_des2_reg_lfsr_two_8__1013), + .I2(plm_des2_reg_lfsr_two_13__487), + .I3(plm_des2_two_adv2_1_14__986), + .O(plm_des2_reg_lfsr_two_12_iv_i_0_a2_0_13_) + ); + defparam plm_des2_lfsrs_reg_lfsr_two_12_iv_i_0_a2_0_11_.INIT = 16'h8228; + LUT4_L plm_des2_lfsrs_reg_lfsr_two_12_iv_i_0_a2_0_11_ ( + .I0(plm_des2_reg_lfsr_two_12_iv_0_0_a4_1[9]), + .I1(plm_des2_reg_lfsr_two_6__1015), + .I2(plm_des2_reg_lfsr_two_11__486), + .I3(plm_des2_two_adv2_1_12__987), + .LO(plm_des2_reg_lfsr_two_12_iv_i_0_a2_0_11_) + ); + defparam plm_des2_lfsrs_reg_lfsr_two_12_iv_i_0_a2_0_2_.INIT = 16'h8228; + LUT4 plm_des2_lfsrs_reg_lfsr_two_12_iv_i_0_a2_0_2_ ( + .I0(plm_des2_reg_lfsr_two_12_iv_0_0_a4_1[9]), + .I1(plm_des2_reg_lfsr_two_14__655), + .I2(plm_des2_reg_lfsr_two_15__488), + .I3(plm_des2_two_adv2_1_7__989), + .O(plm_des2_reg_lfsr_two_12_iv_i_0_a2_0_2_) + ); + defparam plm_des2_lfsrs_reg_lfsr_two_12_iv_i_0_a2_0_1_.INIT = 16'h8228; + LUT4 plm_des2_lfsrs_reg_lfsr_two_12_iv_i_0_a2_0_1_ ( + .I0(plm_des2_reg_lfsr_two_12_iv_0_0_a4_1[9]), + .I1(plm_des2_reg_lfsr_two_1__662), + .I2(plm_des2_reg_lfsr_two_14__655), + .I3(plm_des2_two_adv2_1_1__988), + .O(plm_des2_reg_lfsr_two_12_iv_i_0_a2_0_1_) + ); + defparam plm_des2_lfsrs_reg_lfsr_two_12_iv_i_0_a2_0_0_.INIT = 16'h8228; + LUT4 plm_des2_lfsrs_reg_lfsr_two_12_iv_i_0_a2_0_0_ ( + .I0(plm_des2_reg_lfsr_two_12_iv_0_0_a4_1[9]), + .I1(plm_des2_reg_lfsr_two_0__485), + .I2(plm_des2_reg_lfsr_two_11__486), + .I3(plm_des2_two_adv2_1_1__988), + .O(plm_des2_reg_lfsr_two_12_iv_i_0_a2_0_0_) + ); + defparam plm_des2_lfsrs_reg_lfsr_one_12_iv_i_0_a2_0_12_.INIT = 4'h8; + LUT2_L plm_des2_lfsrs_reg_lfsr_one_12_iv_i_0_a2_0_12_ ( + .I0(plm_des2_reg_lfsr_two_12_iv_0_0_a4_1[9]), + .I1(plm_des2_one_adv2[12]), + .LO(plm_des2_reg_lfsr_one_12_iv_i_0_a2_0_12_) + ); + defparam plm_des2_lfsrs_reg_lfsr_one_12_iv_i_0_a2_0_10_.INIT = 4'h8; + LUT2_L plm_des2_lfsrs_reg_lfsr_one_12_iv_i_0_a2_0_10_ ( + .I0(plm_des2_reg_lfsr_two_12_iv_0_0_a4_1[9]), + .I1(plm_des2_one_adv2[10]), + .LO(plm_des2_reg_lfsr_one_12_iv_i_0_a2_0_10_) + ); + defparam plm_des2_lfsrs_reg_lfsr_one_12_iv_i_0_a2_3_.INIT = 4'h4; + LUT2 plm_des2_lfsrs_reg_lfsr_one_12_iv_i_0_a2_3_ ( + .I0(plm_des2_reg_lfsr_two_12_iv_0_0_o4[9]), + .I1(plm_des2_reg_lfsr_two_3__1017), + .O(plm_des2_reg_lfsr_one_12_iv_i_0_a2[3]) + ); + defparam plm_des2_lfsrs_reg_lfsr_one_12_0_iv_i_i_x4_0_.INIT = 8'h96; + LUT3 plm_des2_lfsrs_reg_lfsr_one_12_0_iv_i_i_x4_0_ ( + .I0(N_12079_1), + .I1(plm_des2_reg_lfsr_one_12__1001), + .I2(plm_des2_reg_lfsr_one_13__523), + .O(plm_des2_N_49077_i_0) + ); + defparam plm_des2_descram_N_86082_i.INIT = 8'h57; + LUT3 plm_des2_descram_N_86082_i ( + .I0(plm_des2_m1_0_a2_0_a3_0_a2_0_a2_1), + .I1(plm_reg_com_0[1]), + .I2(plm_des2_reg_skp[1]), + .O(plm_des2_N_86082_i) + ); + defparam plm_des2_two_adv2_7_.INIT = 16'h6996; + LUT4 plm_des2_two_adv2_7_ ( + .I0(N_49081_i_0), + .I1(plm_des2_reg_lfsr_two_3__1017), + .I2(plm_des2_reg_lfsr_two_7__1014), + .I3(plm_des2_two_adv2_1_7__989), + .O(plm_des2_two_adv2_7__999) + ); + defparam plm_des2_one_adv2_6_.INIT = 16'h6996; + LUT4 plm_des2_one_adv2_6_ ( + .I0(N_49139_i_0), + .I1(plm_des2_one_adv2_1_6__990), + .I2(plm_des2_reg_lfsr_one_2__1009), + .I3(plm_des2_reg_lfsr_one_6__1006), + .O(plm_des2_one_adv2[6]) + ); + defparam plm_des2_one_adv2_7_.INIT = 16'h6996; + LUT4 plm_des2_one_adv2_7_ ( + .I0(G_338_524), + .I1(plm_des2_reg_lfsr_one_2__1009), + .I2(plm_des2_reg_lfsr_one_4__1008), + .I3(plm_des2_reg_lfsr_one_7__1005), + .O(plm_des2_one_adv2[7]) + ); + defparam plm_des2_one_adv2_9_.INIT = 16'h6996; + LUT4 plm_des2_one_adv2_9_ ( + .I0(plm_des2_one_adv2_1_9__992), + .I1(plm_des2_reg_lfsr_one_6__1006), + .I2(plm_des2_reg_lfsr_one_9__1003), + .I3(plm_des2_reg_lfsr_one_15__520), + .O(plm_des2_one_adv2[9]) + ); + defparam plm_des2_one_adv2_5_.INIT = 8'h96; + LUT3 plm_des2_one_adv2_5_ ( + .I0(G_337_521), + .I1(plm_des2_one_adv2_1_5__991), + .I2(plm_des2_reg_lfsr_one_5__1007), + .O(plm_des2_one_adv2[5]) + ); + defparam plm_des2_one_adv2_4_.INIT = 8'h96; + LUT3 plm_des2_one_adv2_4_ ( + .I0(G_337_521), + .I1(plm_des2_reg_lfsr_one_4__1008), + .I2(plm_des2_reg_lfsr_one_14__656), + .O(plm_des2_one_adv2[4]) + ); + defparam plm_des2_two_adv2_6_.INIT = 8'h96; + LUT3 plm_des2_two_adv2_6_ ( + .I0(N_49082_i_0), + .I1(plm_des2_reg_lfsr_two_6__1015), + .I2(plm_des2_two_adv2_1_6__995), + .O(plm_des2_two_adv2_6__1000) + ); + defparam plm_des2_one_adv2_8_.INIT = 8'h96; + LUT3 plm_des2_one_adv2_8_ ( + .I0(N_49139_i_0), + .I1(plm_des2_one_adv2_1_9__992), + .I2(plm_des2_reg_lfsr_one_8__1004), + .O(plm_des2_one_adv2[8]) + ); + defparam plm_des2_input_decoder_reg_bad_3_i_1_1_.INIT = 16'h54FF; + LUT4_L plm_des2_input_decoder_reg_bad_3_i_1_1_ ( + .I0(plm_des2_reg_bad_3_i_a7_2_0[1]), + .I1(plm_des2_reg_data[10]), + .I2(plm_des2_reg_data[11]), + .I3(plm_des2_reg_spesh[1]), + .LO(plm_des2_reg_bad_3_i_1[1]) + ); + defparam plm_des2_input_decoder_reg_bad_4_i_1_0_.INIT = 16'h54FF; + LUT4_L plm_des2_input_decoder_reg_bad_4_i_1_0_ ( + .I0(plm_des2_reg_bad_4_i_a7_2_0[0]), + .I1(plm_des2_reg_data[2]), + .I2(plm_des2_reg_data[3]), + .I3(plm_des2_reg_spesh[0]), + .LO(plm_des2_reg_bad_4_i_1[0]) + ); + defparam plm_des2_lfsrs_reg_lfsr_two_12_iv_0_0_a2_0_9_.INIT = 16'h4884; + LUT4 plm_des2_lfsrs_reg_lfsr_two_12_iv_0_0_a2_0_9_ ( + .I0(N_49081_i_0), + .I1(plm_des2_reg_lfsr_two_12_iv_0_0_a4_1[9]), + .I2(plm_des2_reg_lfsr_two_9__1012), + .I3(plm_des2_two_adv2_1_10__993), + .O(plm_des2_reg_lfsr_two_12_iv_0_0_a2_0_0_9_) + ); + defparam plm_des2_lfsrs_reg_lfsr_two_12_iv_0_0_a2_0_8_.INIT = 16'h2882; + LUT4 plm_des2_lfsrs_reg_lfsr_two_12_iv_0_0_a2_0_8_ ( + .I0(plm_des2_reg_lfsr_two_12_iv_0_0_a4_1[9]), + .I1(plm_des2_reg_lfsr_two_3__1017), + .I2(plm_des2_reg_lfsr_two_14__655), + .I3(plm_des2_two_adv2_1_8__994), + .O(plm_des2_reg_lfsr_two_12_iv_0_0_a2_0_0_8_) + ); + defparam plm_des2_lfsrs_reg_lfsr_two_12_iv_0_0_a2_0_5_.INIT = 16'h6090; + LUT4 plm_des2_lfsrs_reg_lfsr_two_12_iv_0_0_a2_0_5_ ( + .I0(G_351_489), + .I1(N_49082_i_0), + .I2(plm_des2_reg_lfsr_two_12_iv_0_0_a4_1[9]), + .I3(plm_des2_reg_lfsr_two_5__1016), + .O(plm_des2_reg_lfsr_two_12_iv_0_0_a2_0_0_5_) + ); + defparam plm_des2_lfsrs_reg_lfsr_two_12_iv_0_0_a2_0_3_.INIT = 8'h84; + LUT3 plm_des2_lfsrs_reg_lfsr_two_12_iv_0_0_a2_0_3_ ( + .I0(G_351_489), + .I1(plm_des2_reg_lfsr_two_12_iv_0_0_a4_1[9]), + .I2(plm_des2_two_adv2_1_6__995), + .O(plm_des2_reg_lfsr_two_12_iv_0_0_a2_0[3]) + ); + defparam plm_des2_lfsrs_reg_lfsr_two_12_iv_i_0_a2_0_4_.INIT = 16'h9060; + LUT4 plm_des2_lfsrs_reg_lfsr_two_12_iv_i_0_a2_0_4_ ( + .I0(N_49081_i_0), + .I1(N_49141_i_0), + .I2(plm_des2_reg_lfsr_two_12_iv_0_0_a4_1[9]), + .I3(plm_des2_two_adv2_0[4]), + .O(plm_des2_reg_lfsr_two_12_iv_i_0_a2_0_4_) + ); + defparam plm_des2_lfsrs_reg_lfsr_one_12_iv_i_0_a2_0_9_.INIT = 4'h8; + LUT2_L plm_des2_lfsrs_reg_lfsr_one_12_iv_i_0_a2_0_9_ ( + .I0(plm_des2_reg_lfsr_two_12_iv_0_0_a4_1[9]), + .I1(plm_des2_one_adv2[9]), + .LO(plm_des2_reg_lfsr_one_12_iv_i_0_a2_0_9_) + ); + defparam plm_des2_lfsrs_reg_lfsr_one_12_iv_i_0_a2_0_8_.INIT = 4'h8; + LUT2_L plm_des2_lfsrs_reg_lfsr_one_12_iv_i_0_a2_0_8_ ( + .I0(plm_des2_reg_lfsr_two_12_iv_0_0_a4_1[9]), + .I1(plm_des2_one_adv2[8]), + .LO(plm_des2_reg_lfsr_one_12_iv_i_0_a2_0_8_) + ); + defparam plm_des2_lfsrs_reg_lfsr_one_12_iv_i_0_a2_0_7_.INIT = 4'h8; + LUT2_L plm_des2_lfsrs_reg_lfsr_one_12_iv_i_0_a2_0_7_ ( + .I0(plm_des2_reg_lfsr_two_12_iv_0_0_a4_1[9]), + .I1(plm_des2_one_adv2[7]), + .LO(plm_des2_reg_lfsr_one_12_iv_i_0_a2_0_7_) + ); + defparam plm_des2_lfsrs_reg_lfsr_one_12_iv_i_0_a2_0_6_.INIT = 4'h8; + LUT2_L plm_des2_lfsrs_reg_lfsr_one_12_iv_i_0_a2_0_6_ ( + .I0(plm_des2_reg_lfsr_two_12_iv_0_0_a4_1[9]), + .I1(plm_des2_one_adv2[6]), + .LO(plm_des2_reg_lfsr_one_12_iv_i_0_a2_0_6_) + ); + defparam plm_des2_lfsrs_reg_lfsr_one_12_iv_i_0_a2_0_5_.INIT = 4'h8; + LUT2_L plm_des2_lfsrs_reg_lfsr_one_12_iv_i_0_a2_0_5_ ( + .I0(plm_des2_reg_lfsr_two_12_iv_0_0_a4_1[9]), + .I1(plm_des2_one_adv2[5]), + .LO(plm_des2_reg_lfsr_one_12_iv_i_0_a2_0_5_) + ); + defparam plm_des2_descram_reg_rx_des_dat_14_0_am_7_.INIT = 8'h65; + LUT3 plm_des2_descram_reg_rx_des_dat_14_0_am_7_ ( + .I0(plm_des2_reg_dat[7]), + .I1(plm_des2_reg_lfsr_one_8__1004), + .I2(plm_des2_reg_skp[1]), + .O(plm_des2_reg_rx_des_dat_14_0_am_0[7]) + ); + defparam plm_des2_descram_reg_rx_des_dat_14_0_bm_7_.INIT = 8'h6C; + LUT3 plm_des2_descram_reg_rx_des_dat_14_0_bm_7_ ( + .I0(plm_des2_m1_0_a2_0_a3_0_a2_0_a2_1), + .I1(plm_des2_reg_dat[7]), + .I2(plm_des2_reg_lfsr_two_8__1013), + .O(plm_des2_reg_rx_des_dat_14_0_bm_0[7]) + ); + MUXF5 plm_des2_descram_reg_rx_des_dat_14_0_7_ ( + .I0(plm_des2_reg_rx_des_dat_14_0_am_0[7]), + .I1(plm_des2_reg_rx_des_dat_14_0_bm_0[7]), + .O(plm_des2_reg_rx_des_dat_14[7]), + .S(plm_des2_N_86082_i) + ); + defparam plm_des2_descram_reg_rx_des_dat_14_0_am_6_.INIT = 8'h65; + LUT3 plm_des2_descram_reg_rx_des_dat_14_0_am_6_ ( + .I0(plm_des2_reg_dat[6]), + .I1(plm_des2_reg_lfsr_one_9__1003), + .I2(plm_des2_reg_skp[1]), + .O(plm_des2_reg_rx_des_dat_14_0_am_0[6]) + ); + defparam plm_des2_descram_reg_rx_des_dat_14_0_bm_6_.INIT = 8'h6C; + LUT3 plm_des2_descram_reg_rx_des_dat_14_0_bm_6_ ( + .I0(plm_des2_m1_0_a2_0_a3_0_a2_0_a2_1), + .I1(plm_des2_reg_dat[6]), + .I2(plm_des2_reg_lfsr_two_9__1012), + .O(plm_des2_reg_rx_des_dat_14_0_bm_0[6]) + ); + MUXF5 plm_des2_descram_reg_rx_des_dat_14_0_6_ ( + .I0(plm_des2_reg_rx_des_dat_14_0_am_0[6]), + .I1(plm_des2_reg_rx_des_dat_14_0_bm_0[6]), + .O(plm_des2_reg_rx_des_dat_14[6]), + .S(plm_des2_N_86082_i) + ); + defparam plm_des2_descram_reg_rx_des_dat_14_0_am_5_.INIT = 8'h65; + LUT3 plm_des2_descram_reg_rx_des_dat_14_0_am_5_ ( + .I0(plm_des2_reg_dat[5]), + .I1(plm_des2_reg_lfsr_one_10__1002), + .I2(plm_des2_reg_skp[1]), + .O(plm_des2_reg_rx_des_dat_14_0_am_0[5]) + ); + defparam plm_des2_descram_reg_rx_des_dat_14_0_bm_5_.INIT = 8'h6C; + LUT3 plm_des2_descram_reg_rx_des_dat_14_0_bm_5_ ( + .I0(plm_des2_m1_0_a2_0_a3_0_a2_0_a2_1), + .I1(plm_des2_reg_dat[5]), + .I2(plm_des2_reg_lfsr_two_10__1011), + .O(plm_des2_reg_rx_des_dat_14_0_bm_0[5]) + ); + MUXF5 plm_des2_descram_reg_rx_des_dat_14_0_5_ ( + .I0(plm_des2_reg_rx_des_dat_14_0_am_0[5]), + .I1(plm_des2_reg_rx_des_dat_14_0_bm_0[5]), + .O(plm_des2_reg_rx_des_dat_14[5]), + .S(plm_des2_N_86082_i) + ); + defparam plm_des2_descram_reg_rx_des_dat_14_0_am_4_.INIT = 8'h65; + LUT3 plm_des2_descram_reg_rx_des_dat_14_0_am_4_ ( + .I0(plm_des2_reg_dat[4]), + .I1(plm_des2_reg_lfsr_one_11__642), + .I2(plm_des2_reg_skp[1]), + .O(plm_des2_reg_rx_des_dat_14_0_am_0[4]) + ); + defparam plm_des2_descram_reg_rx_des_dat_14_0_bm_4_.INIT = 8'h6C; + LUT3 plm_des2_descram_reg_rx_des_dat_14_0_bm_4_ ( + .I0(plm_des2_m1_0_a2_0_a3_0_a2_0_a2_1), + .I1(plm_des2_reg_dat[4]), + .I2(plm_des2_reg_lfsr_two_11__486), + .O(plm_des2_reg_rx_des_dat_14_0_bm_0[4]) + ); + MUXF5 plm_des2_descram_reg_rx_des_dat_14_0_4_ ( + .I0(plm_des2_reg_rx_des_dat_14_0_am_0[4]), + .I1(plm_des2_reg_rx_des_dat_14_0_bm_0[4]), + .O(plm_des2_reg_rx_des_dat_14[4]), + .S(plm_des2_N_86082_i) + ); + defparam plm_des2_descram_reg_rx_des_dat_14_0_am_3_.INIT = 8'h65; + LUT3 plm_des2_descram_reg_rx_des_dat_14_0_am_3_ ( + .I0(plm_des2_reg_dat[3]), + .I1(plm_des2_reg_lfsr_one_12__1001), + .I2(plm_des2_reg_skp[1]), + .O(plm_des2_reg_rx_des_dat_14_0_am_0[3]) + ); + defparam plm_des2_descram_reg_rx_des_dat_14_0_bm_3_.INIT = 8'h6C; + LUT3 plm_des2_descram_reg_rx_des_dat_14_0_bm_3_ ( + .I0(plm_des2_m1_0_a2_0_a3_0_a2_0_a2_1), + .I1(plm_des2_reg_dat[3]), + .I2(plm_des2_reg_lfsr_two_12__1010), + .O(plm_des2_reg_rx_des_dat_14_0_bm_0[3]) + ); + MUXF5 plm_des2_descram_reg_rx_des_dat_14_0_3_ ( + .I0(plm_des2_reg_rx_des_dat_14_0_am_0[3]), + .I1(plm_des2_reg_rx_des_dat_14_0_bm_0[3]), + .O(plm_des2_reg_rx_des_dat_14[3]), + .S(plm_des2_N_86082_i) + ); + defparam plm_des2_descram_reg_rx_des_dat_14_0_am_2_.INIT = 8'h65; + LUT3 plm_des2_descram_reg_rx_des_dat_14_0_am_2_ ( + .I0(plm_des2_reg_dat[2]), + .I1(plm_des2_reg_lfsr_one_13__523), + .I2(plm_des2_reg_skp[1]), + .O(plm_des2_reg_rx_des_dat_14_0_am_0[2]) + ); + defparam plm_des2_descram_reg_rx_des_dat_14_0_bm_2_.INIT = 8'h6C; + LUT3 plm_des2_descram_reg_rx_des_dat_14_0_bm_2_ ( + .I0(plm_des2_m1_0_a2_0_a3_0_a2_0_a2_1), + .I1(plm_des2_reg_dat[2]), + .I2(plm_des2_reg_lfsr_two_13__487), + .O(plm_des2_reg_rx_des_dat_14_0_bm_0[2]) + ); + MUXF5 plm_des2_descram_reg_rx_des_dat_14_0_2_ ( + .I0(plm_des2_reg_rx_des_dat_14_0_am_0[2]), + .I1(plm_des2_reg_rx_des_dat_14_0_bm_0[2]), + .O(plm_des2_reg_rx_des_dat_14[2]), + .S(plm_des2_N_86082_i) + ); + defparam plm_des2_descram_reg_rx_des_dat_14_0_am_1_.INIT = 8'h65; + LUT3 plm_des2_descram_reg_rx_des_dat_14_0_am_1_ ( + .I0(plm_des2_reg_dat[1]), + .I1(plm_des2_reg_lfsr_one_14__656), + .I2(plm_des2_reg_skp[1]), + .O(plm_des2_reg_rx_des_dat_14_0_am_0[1]) + ); + defparam plm_des2_descram_reg_rx_des_dat_14_0_bm_1_.INIT = 8'h6C; + LUT3 plm_des2_descram_reg_rx_des_dat_14_0_bm_1_ ( + .I0(plm_des2_m1_0_a2_0_a3_0_a2_0_a2_1), + .I1(plm_des2_reg_dat[1]), + .I2(plm_des2_reg_lfsr_two_14__655), + .O(plm_des2_reg_rx_des_dat_14_0_bm_0[1]) + ); + MUXF5 plm_des2_descram_reg_rx_des_dat_14_0_1_ ( + .I0(plm_des2_reg_rx_des_dat_14_0_am_0[1]), + .I1(plm_des2_reg_rx_des_dat_14_0_bm_0[1]), + .O(plm_des2_reg_rx_des_dat_14[1]), + .S(plm_des2_N_86082_i) + ); + defparam plm_des2_descram_reg_rx_des_dat_14_0_am_0_.INIT = 8'h65; + LUT3 plm_des2_descram_reg_rx_des_dat_14_0_am_0_ ( + .I0(plm_des2_reg_dat[0]), + .I1(plm_des2_reg_lfsr_one_15__520), + .I2(plm_des2_reg_skp[1]), + .O(plm_des2_reg_rx_des_dat_14_0_am_0[0]) + ); + defparam plm_des2_descram_reg_rx_des_dat_14_0_bm_0_.INIT = 8'h6C; + LUT3 plm_des2_descram_reg_rx_des_dat_14_0_bm_0_ ( + .I0(plm_des2_m1_0_a2_0_a3_0_a2_0_a2_1), + .I1(plm_des2_reg_dat[0]), + .I2(plm_des2_reg_lfsr_two_15__488), + .O(plm_des2_reg_rx_des_dat_14_0_bm_0[0]) + ); + MUXF5 plm_des2_descram_reg_rx_des_dat_14_0_0_ ( + .I0(plm_des2_reg_rx_des_dat_14_0_am_0[0]), + .I1(plm_des2_reg_rx_des_dat_14_0_bm_0[0]), + .O(plm_des2_reg_rx_des_dat_14[0]), + .S(plm_des2_N_86082_i) + ); + defparam plm_des2_one_adv2_3_.INIT = 16'h6996; + LUT4 plm_des2_one_adv2_3_ ( + .I0(G_338_524), + .I1(N_12079_1), + .I2(plm_des2_reg_lfsr_one_12__1001), + .I3(plm_des2_reg_lfsr_one_14__656), + .O(plm_des2_one_adv2[3]) + ); + defparam plm_des2_input_decoder_reg_bad_3_i_2_1_.INIT = 16'h080A; + LUT4_L plm_des2_input_decoder_reg_bad_3_i_2_1_ ( + .I0(plm_des2_reg_bad_3_i_1[1]), + .I1(plm_des2_reg_data[12]), + .I2(plm_des2_reg_nitbl[1]), + .I3(plm_des2_reg_spesh[1]), + .LO(plm_des2_reg_bad_3_i_2[1]) + ); + defparam plm_des2_input_decoder_reg_bad_4_i_2_0_.INIT = 16'h080A; + LUT4_L plm_des2_input_decoder_reg_bad_4_i_2_0_ ( + .I0(plm_des2_reg_bad_4_i_1[0]), + .I1(plm_des2_reg_data[4]), + .I2(plm_des2_reg_nitbl[0]), + .I3(plm_des2_reg_spesh[0]), + .LO(plm_des2_reg_bad_4_i_2[0]) + ); + defparam plm_des2_descram_N_49208_i_0_i.INIT = 8'h6C; + LUT3_L plm_des2_descram_N_49208_i_0_i ( + .I0(plm_des2_N_49065_i), + .I1(plm_des2_reg_dat[13]), + .I2(plm_des2_reg_lfsr_one_10__1002), + .LO(plm_des2_N_49208_i_0_i) + ); + defparam plm_des2_descram_N_49206_i_0_i.INIT = 8'h6C; + LUT3_L plm_des2_descram_N_49206_i_0_i ( + .I0(plm_des2_N_49065_i), + .I1(plm_des2_reg_dat[12]), + .I2(plm_des2_reg_lfsr_one_11__642), + .LO(plm_des2_N_49206_i_0_i) + ); + defparam plm_des2_descram_N_49204_i_0_i.INIT = 8'h6C; + LUT3_L plm_des2_descram_N_49204_i_0_i ( + .I0(plm_des2_N_49065_i), + .I1(plm_des2_reg_dat[11]), + .I2(plm_des2_reg_lfsr_one_12__1001), + .LO(plm_des2_N_49204_i_0_i) + ); + defparam plm_des2_descram_N_49202_i_0_i.INIT = 8'h6C; + LUT3_L plm_des2_descram_N_49202_i_0_i ( + .I0(plm_des2_N_49065_i), + .I1(plm_des2_reg_dat[10]), + .I2(plm_des2_reg_lfsr_one_13__523), + .LO(plm_des2_N_49202_i_0_i) + ); + defparam plm_des2_descram_N_49200_i_0_i.INIT = 8'h6C; + LUT3_L plm_des2_descram_N_49200_i_0_i ( + .I0(plm_des2_N_49065_i), + .I1(plm_des2_reg_dat[9]), + .I2(plm_des2_reg_lfsr_one_14__656), + .LO(plm_des2_N_49200_i_0_i) + ); + defparam plm_des2_descram_N_49198_i_0_i.INIT = 8'h6C; + LUT3_L plm_des2_descram_N_49198_i_0_i ( + .I0(plm_des2_N_49065_i), + .I1(plm_des2_reg_dat[8]), + .I2(plm_des2_reg_lfsr_one_15__520), + .LO(plm_des2_N_49198_i_0_i) + ); + defparam plm_des2_input_decoder_reg_t2p_3_0_a7_1_.INIT = 16'h0080; + LUT4_L plm_des2_input_decoder_reg_t2p_3_0_a7_1_ ( + .I0(plm_des2_reg_t1n_3_1[1]), + .I1(plm_des2_reg_t1p_3_1[1]), + .I2(plm_des2_reg_data[8]), + .I3(plm_des2_reg_data[9]), + .LO(plm_des2_reg_t2p_3[1]) + ); + defparam plm_des2_input_decoder_reg_t2p_4_0_a7_0_.INIT = 16'h0080; + LUT4_L plm_des2_input_decoder_reg_t2p_4_0_a7_0_ ( + .I0(plm_des2_reg_t1n_4_1[0]), + .I1(plm_des2_reg_t1p_4_1[0]), + .I2(plm_des2_reg_data[0]), + .I3(plm_des2_reg_data[1]), + .LO(plm_reg_t2p_4_1[0]) + ); + defparam plm_des2_input_decoder_reg_t2n_3_0_a7_1_.INIT = 8'h80; + LUT3_L plm_des2_input_decoder_reg_t2n_3_0_a7_1_ ( + .I0(plm_des2_reg_sym_3[1]), + .I1(plm_des2_reg_t2n_3_0_a7_0_2[1]), + .I2(plm_des2_reg_t2n_3_3[1]), + .LO(plm_des2_reg_t2n_3[1]) + ); + defparam plm_des2_input_decoder_reg_t2n_4_0_a7_0_.INIT = 8'h80; + LUT3_L plm_des2_input_decoder_reg_t2n_4_0_a7_0_ ( + .I0(plm_des2_reg_sym_4[0]), + .I1(plm_des2_reg_t2n_4_0_a7_0_2[0]), + .I2(plm_des2_reg_t2n_4_3[0]), + .LO(plm_reg_t2n_4_1[0]) + ); + defparam plm_des2_input_decoder_N_85320_i.INIT = 16'h7F0F; + LUT4_L plm_des2_input_decoder_N_85320_i ( + .I0(plm_des2_N_14164_i), + .I1(plm_des2_N_14165_i), + .I2(plm_des2_reg_bad_3_i_2[1]), + .I3(plm_des2_reg_spesh[1]), + .LO(plm_des2_N_85320_i) + ); + defparam plm_des2_input_decoder_N_85321_i.INIT = 16'h7F0F; + LUT4_L plm_des2_input_decoder_N_85321_i ( + .I0(plm_des2_N_14130_i), + .I1(plm_des2_N_14131_i), + .I2(plm_des2_reg_bad_4_i_2[0]), + .I3(plm_des2_reg_spesh[0]), + .LO(plm_des2_N_85321_i) + ); + defparam plm_des2_descram_N_49212_i_0_i.INIT = 8'h6C; + LUT3_L plm_des2_descram_N_49212_i_0_i ( + .I0(plm_des2_N_49065_i), + .I1(plm_des2_reg_dat[15]), + .I2(plm_des2_reg_lfsr_one_8__1004), + .LO(plm_des2_N_49212_i_0_i) + ); + defparam plm_des2_descram_N_49210_i_0_i.INIT = 8'h6C; + LUT3_L plm_des2_descram_N_49210_i_0_i ( + .I0(plm_des2_N_49065_i), + .I1(plm_des2_reg_dat[14]), + .I2(plm_des2_reg_lfsr_one_9__1003), + .LO(plm_des2_N_49210_i_0_i) + ); + defparam plm_des2_input_decoder_reg_skp_3_0_a7_1_.INIT = 16'h0800; + LUT4_L plm_des2_input_decoder_reg_skp_3_0_a7_1_ ( + .I0(plm_des2_reg_skp_3_0_a7_1[1]), + .I1(plm_des2_reg_skp_3_3[1]), + .I2(plm_des2_reg_nitbl[1]), + .I3(plm_des2_reg_spesh[1]), + .LO(plm_des2_reg_skp_3[1]) + ); + defparam plm_des2_input_decoder_reg_skp_4_0_a7_0_.INIT = 16'h0800; + LUT4_L plm_des2_input_decoder_reg_skp_4_0_a7_0_ ( + .I0(plm_des2_reg_skp_4_0_a7_1[0]), + .I1(plm_des2_reg_skp_4_3[0]), + .I2(plm_des2_reg_nitbl[0]), + .I3(plm_des2_reg_spesh[0]), + .LO(plm_des2_reg_skp_4[0]) + ); + defparam plm_des2_input_decoder_reg_pad_3_0_a7_1_.INIT = 16'h8000; + LUT4_L plm_des2_input_decoder_reg_pad_3_0_a7_1_ ( + .I0(plm_des2_reg_pad_3_0_a7_0[1]), + .I1(plm_des2_reg_pad_3_5[1]), + .I2(plm_des2_reg_data[8]), + .I3(plm_des2_reg_data[9]), + .LO(plm_reg_pad_3_0[1]) + ); + defparam plm_des2_input_decoder_reg_pad_4_0_a7_0_.INIT = 16'h8000; + LUT4_L plm_des2_input_decoder_reg_pad_4_0_a7_0_ ( + .I0(plm_des2_reg_pad_4_0_a7_0[0]), + .I1(plm_des2_reg_pad_4_5[0]), + .I2(plm_des2_reg_data[0]), + .I3(plm_des2_reg_data[1]), + .LO(plm_reg_pad_4_0[0]) + ); + defparam plm_des2_input_decoder_reg_com_3_0_a7_1_.INIT = 16'h0800; + LUT4_L plm_des2_input_decoder_reg_com_3_0_a7_1_ ( + .I0(plm_des2_reg_pad_3_5[1]), + .I1(plm_des2_reg_skp_3_3[1]), + .I2(plm_des2_reg_data[14]), + .I3(plm_des2_reg_data[15]), + .LO(plm_des2_reg_com_3[1]) + ); + defparam plm_des2_input_decoder_reg_com_4_0_a7_0_.INIT = 16'h0800; + LUT4_L plm_des2_input_decoder_reg_com_4_0_a7_0_ ( + .I0(plm_des2_reg_pad_4_5[0]), + .I1(plm_des2_reg_skp_4_3[0]), + .I2(plm_des2_reg_data[6]), + .I3(plm_des2_reg_data[7]), + .LO(plm_des2_reg_com_4[0]) + ); + defparam plm_des2_input_decoder_reg_t1p_3_0_a7_1_.INIT = 8'h80; + LUT3_L plm_des2_input_decoder_reg_t1p_3_0_a7_1_ ( + .I0(plm_des2_reg_sym_3[1]), + .I1(plm_des2_reg_t1p_3_1[1]), + .I2(plm_des2_reg_t2n_3_0_a7_0_2[1]), + .LO(plm_des2_reg_t1p_3[1]) + ); + defparam plm_des2_input_decoder_reg_t1p_4_0_a7_0_.INIT = 8'h80; + LUT3_L plm_des2_input_decoder_reg_t1p_4_0_a7_0_ ( + .I0(plm_des2_reg_sym_4[0]), + .I1(plm_des2_reg_t1p_4_1[0]), + .I2(plm_des2_reg_t2n_4_0_a7_0_2[0]), + .LO(plm_reg_t1p_4_1[0]) + ); + defparam plm_des2_input_decoder_reg_t1n_3_0_a7_1_.INIT = 16'h0080; + LUT4_L plm_des2_input_decoder_reg_t1n_3_0_a7_1_ ( + .I0(plm_des2_reg_t1n_3_1[1]), + .I1(plm_des2_reg_t2n_3_3[1]), + .I2(plm_des2_reg_data[8]), + .I3(plm_des2_reg_data[9]), + .LO(plm_des2_reg_t1n_3[1]) + ); + defparam plm_des2_input_decoder_reg_t1n_4_0_a7_0_.INIT = 16'h0080; + LUT4_L plm_des2_input_decoder_reg_t1n_4_0_a7_0_ ( + .I0(plm_des2_reg_t1n_4_1[0]), + .I1(plm_des2_reg_t2n_4_3[0]), + .I2(plm_des2_reg_data[0]), + .I3(plm_des2_reg_data[1]), + .LO(plm_reg_t1n_4_1[0]) + ); + defparam plm_des2_lfsrs_N_87684_i.INIT = 16'hF7B3; + LUT4_L plm_des2_lfsrs_N_87684_i ( + .I0(plm_des2_N_49058_i), + .I1(plm_des2_reg_lfsr_two_12_0_iv_0_o2[12]), + .I2(plm_des2_one_adv2[15]), + .I3(plm_des2_reg_lfsr_two_15__488), + .LO(plm_des2_N_87684_i) + ); + defparam plm_des2_lfsrs_N_87683_i.INIT = 16'hF7B3; + LUT4_L plm_des2_lfsrs_N_87683_i ( + .I0(plm_des2_N_49058_i), + .I1(plm_des2_reg_lfsr_two_12_0_iv_0_o2[12]), + .I2(plm_des2_one_adv2[14]), + .I3(plm_des2_reg_lfsr_two_14__655), + .LO(plm_des2_N_87683_i) + ); + defparam plm_des2_lfsrs_N_87682_i.INIT = 16'hF7B3; + LUT4_L plm_des2_lfsrs_N_87682_i ( + .I0(plm_des2_N_49058_i), + .I1(plm_des2_reg_lfsr_two_12_0_iv_0_o2[12]), + .I2(plm_des2_one_adv2[13]), + .I3(plm_des2_reg_lfsr_two_13__487), + .LO(plm_des2_N_87682_i) + ); + defparam plm_des2_lfsrs_N_85371_i.INIT = 16'hDFDD; + LUT4_L plm_des2_lfsrs_N_85371_i ( + .I0(plm_des2_N_49061_i), + .I1(plm_des2_reg_lfsr_one_12_iv_i_0_a2_0_12_), + .I2(plm_des2_reg_lfsr_two_12_iv_0_0_o4[9]), + .I3(plm_des2_reg_lfsr_two_12__1010), + .LO(plm_des2_N_85371_i) + ); + defparam plm_des2_lfsrs_N_87681_i.INIT = 16'hF7B3; + LUT4_L plm_des2_lfsrs_N_87681_i ( + .I0(plm_des2_N_49058_i), + .I1(plm_des2_reg_lfsr_two_12_0_iv_0_o2[12]), + .I2(plm_des2_one_adv2[11]), + .I3(plm_des2_reg_lfsr_two_11__486), + .LO(plm_des2_N_87681_i) + ); + defparam plm_des2_lfsrs_N_85370_i.INIT = 16'hDFDD; + LUT4_L plm_des2_lfsrs_N_85370_i ( + .I0(plm_des2_N_49061_i), + .I1(plm_des2_reg_lfsr_one_12_iv_i_0_a2_0_10_), + .I2(plm_des2_reg_lfsr_two_12_iv_0_0_o4[9]), + .I3(plm_des2_reg_lfsr_two_10__1011), + .LO(plm_des2_N_85370_i) + ); + defparam plm_des2_lfsrs_N_85369_i.INIT = 16'hDFDD; + LUT4_L plm_des2_lfsrs_N_85369_i ( + .I0(plm_des2_N_49061_i), + .I1(plm_des2_reg_lfsr_one_12_iv_i_0_a2_0_9_), + .I2(plm_des2_reg_lfsr_two_12_iv_0_0_o4[9]), + .I3(plm_des2_reg_lfsr_two_9__1012), + .LO(plm_des2_N_85369_i) + ); + defparam plm_des2_lfsrs_N_85368_i.INIT = 16'hDFDD; + LUT4_L plm_des2_lfsrs_N_85368_i ( + .I0(plm_des2_N_49061_i), + .I1(plm_des2_reg_lfsr_one_12_iv_i_0_a2_0_8_), + .I2(plm_des2_reg_lfsr_two_12_iv_0_0_o4[9]), + .I3(plm_des2_reg_lfsr_two_8__1013), + .LO(plm_des2_N_85368_i) + ); + defparam plm_des2_lfsrs_N_85367_i.INIT = 16'hDFDD; + LUT4_L plm_des2_lfsrs_N_85367_i ( + .I0(plm_des2_N_49061_i), + .I1(plm_des2_reg_lfsr_one_12_iv_i_0_a2_0_7_), + .I2(plm_des2_reg_lfsr_two_12_iv_0_0_o4[9]), + .I3(plm_des2_reg_lfsr_two_7__1014), + .LO(plm_des2_N_85367_i) + ); + defparam plm_des2_lfsrs_N_85366_i.INIT = 16'hDFDD; + LUT4_L plm_des2_lfsrs_N_85366_i ( + .I0(plm_des2_N_49061_i), + .I1(plm_des2_reg_lfsr_one_12_iv_i_0_a2_0_6_), + .I2(plm_des2_reg_lfsr_two_12_iv_0_0_o4[9]), + .I3(plm_des2_reg_lfsr_two_6__1015), + .LO(plm_des2_N_85366_i) + ); + defparam plm_des2_lfsrs_N_85365_i.INIT = 16'hDFDD; + LUT4_L plm_des2_lfsrs_N_85365_i ( + .I0(plm_des2_N_49061_i), + .I1(plm_des2_reg_lfsr_one_12_iv_i_0_a2_0_5_), + .I2(plm_des2_reg_lfsr_two_12_iv_0_0_o4[9]), + .I3(plm_des2_reg_lfsr_two_5__1016), + .LO(plm_des2_N_85365_i) + ); + defparam plm_des2_lfsrs_N_87680_i.INIT = 16'hF7B3; + LUT4_L plm_des2_lfsrs_N_87680_i ( + .I0(plm_des2_N_49058_i), + .I1(plm_des2_reg_lfsr_two_12_0_iv_0_o2[12]), + .I2(plm_des2_one_adv2[4]), + .I3(plm_des2_reg_lfsr_two_4__664), + .LO(plm_des2_N_87680_i) + ); + defparam plm_des2_lfsrs_N_85364_i.INIT = 16'hFDDD; + LUT4_L plm_des2_lfsrs_N_85364_i ( + .I0(plm_des2_N_49061_i), + .I1(plm_des2_reg_lfsr_one_12_iv_i_0_a2[3]), + .I2(plm_des2_reg_lfsr_two_12_iv_0_0_a4_1[9]), + .I3(plm_des2_one_adv2[3]), + .LO(plm_des2_N_85364_i) + ); + defparam plm_des2_lfsrs_N_87679_i.INIT = 16'hF7B3; + LUT4_L plm_des2_lfsrs_N_87679_i ( + .I0(plm_des2_N_49058_i), + .I1(plm_des2_reg_lfsr_two_12_0_iv_0_o2[12]), + .I2(plm_des2_one_adv2[2]), + .I3(plm_des2_reg_lfsr_two_2__663), + .LO(plm_des2_N_87679_i) + ); + defparam plm_des2_lfsrs_N_87678_i.INIT = 16'hF7B3; + LUT4_L plm_des2_lfsrs_N_87678_i ( + .I0(plm_des2_N_49058_i), + .I1(plm_des2_reg_lfsr_two_12_0_iv_0_o2[12]), + .I2(plm_des2_one_adv2[1]), + .I3(plm_des2_reg_lfsr_two_1__662), + .LO(plm_des2_N_87678_i) + ); + defparam plm_des2_lfsrs_N_87665_i.INIT = 16'hDF8F; + LUT4_L plm_des2_lfsrs_N_87665_i ( + .I0(plm_des2_N_49058_i), + .I1(plm_des2_N_49077_i_0), + .I2(plm_des2_reg_lfsr_two_12_0_iv_0_o2[12]), + .I3(plm_des2_reg_lfsr_two_0__485), + .LO(plm_des2_N_87665_i) + ); + defparam plm_des2_lfsrs_N_85379_i.INIT = 16'hFDDD; + LUT4_L plm_des2_lfsrs_N_85379_i ( + .I0(plm_des2_N_49061_i), + .I1(plm_des2_reg_lfsr_two_12_iv_i_0_a2[15]), + .I2(plm_des2_reg_lfsr_two_12_iv_0_0_a4_1[9]), + .I3(plm_des2_two_adv2_15__996), + .LO(plm_des2_N_85379_i) + ); + defparam plm_des2_lfsrs_N_85378_i.INIT = 16'hDFDD; + LUT4_L plm_des2_lfsrs_N_85378_i ( + .I0(plm_des2_N_49061_i), + .I1(plm_des2_reg_lfsr_two_12_iv_i_0_a2_0_14_), + .I2(plm_des2_reg_lfsr_two_12_iv_0_0_o4[9]), + .I3(plm_des2_one_adv2[14]), + .LO(plm_des2_N_85378_i) + ); + defparam plm_des2_lfsrs_N_85377_i.INIT = 16'hDFDD; + LUT4_L plm_des2_lfsrs_N_85377_i ( + .I0(plm_des2_N_49061_i), + .I1(plm_des2_reg_lfsr_two_12_iv_i_0_a2_0_13_), + .I2(plm_des2_reg_lfsr_two_12_iv_0_0_o4[9]), + .I3(plm_des2_one_adv2[13]), + .LO(plm_des2_N_85377_i) + ); + defparam plm_des2_lfsrs_reg_lfsr_two_12_0_iv_0_12_.INIT = 16'hC840; + LUT4_L plm_des2_lfsrs_reg_lfsr_two_12_0_iv_0_12_ ( + .I0(plm_des2_N_49058_i), + .I1(plm_des2_reg_lfsr_two_12_0_iv_0_o2[12]), + .I2(plm_des2_one_adv2[12]), + .I3(plm_des2_two_adv2_12__997), + .LO(plm_des2_N_9575_i) + ); + defparam plm_des2_lfsrs_N_85376_i.INIT = 16'hDFDD; + LUT4_L plm_des2_lfsrs_N_85376_i ( + .I0(plm_des2_N_49061_i), + .I1(plm_des2_reg_lfsr_two_12_iv_i_0_a2_0_11_), + .I2(plm_des2_reg_lfsr_two_12_iv_0_0_o4[9]), + .I3(plm_des2_one_adv2[11]), + .LO(plm_des2_N_85376_i) + ); + defparam plm_des2_lfsrs_reg_lfsr_two_12_0_iv_0_10_.INIT = 16'hC840; + LUT4_L plm_des2_lfsrs_reg_lfsr_two_12_0_iv_0_10_ ( + .I0(plm_des2_N_49058_i), + .I1(plm_des2_reg_lfsr_two_12_0_iv_0_o2[12]), + .I2(plm_des2_one_adv2[10]), + .I3(plm_des2_two_adv2_10__998), + .LO(plm_des2_N_9577_i) + ); + defparam plm_des2_lfsrs_reg_lfsr_two_12_iv_0_0_9_.INIT = 16'h2220; + LUT4_L plm_des2_lfsrs_reg_lfsr_two_12_iv_0_0_9_ ( + .I0(plm_des2_N_49061_i), + .I1(plm_des2_reg_lfsr_two_12_iv_0_0_a2_0_0_9_), + .I2(plm_des2_reg_lfsr_two_12_iv_0_0_o4[9]), + .I3(plm_des2_one_adv2[9]), + .LO(plm_des2_N_9578_i) + ); + defparam plm_des2_lfsrs_reg_lfsr_two_12_iv_0_0_8_.INIT = 16'h2220; + LUT4_L plm_des2_lfsrs_reg_lfsr_two_12_iv_0_0_8_ ( + .I0(plm_des2_N_49061_i), + .I1(plm_des2_reg_lfsr_two_12_iv_0_0_a2_0_0_8_), + .I2(plm_des2_reg_lfsr_two_12_iv_0_0_o4[9]), + .I3(plm_des2_one_adv2[8]), + .LO(plm_des2_N_9579_i) + ); + defparam plm_des2_lfsrs_reg_lfsr_two_12_0_iv_0_7_.INIT = 16'hC840; + LUT4_L plm_des2_lfsrs_reg_lfsr_two_12_0_iv_0_7_ ( + .I0(plm_des2_N_49058_i), + .I1(plm_des2_reg_lfsr_two_12_0_iv_0_o2[12]), + .I2(plm_des2_one_adv2[7]), + .I3(plm_des2_two_adv2_7__999), + .LO(plm_des2_N_9580_i) + ); + defparam plm_des2_lfsrs_reg_lfsr_two_12_0_iv_0_0_0_6_.INIT = 16'hC840; + LUT4_L plm_des2_lfsrs_reg_lfsr_two_12_0_iv_0_0_0_6_ ( + .I0(plm_des2_N_49058_i), + .I1(plm_des2_reg_lfsr_two_12_0_iv_0_o2[12]), + .I2(plm_des2_one_adv2[6]), + .I3(plm_des2_two_adv2_6__1000), + .LO(plm_des2_N_9581_i) + ); + defparam plm_des2_lfsrs_reg_lfsr_two_12_iv_0_0_5_.INIT = 16'h2220; + LUT4_L plm_des2_lfsrs_reg_lfsr_two_12_iv_0_0_5_ ( + .I0(plm_des2_N_49061_i), + .I1(plm_des2_reg_lfsr_two_12_iv_0_0_a2_0_0_5_), + .I2(plm_des2_reg_lfsr_two_12_iv_0_0_o4[9]), + .I3(plm_des2_one_adv2[5]), + .LO(plm_des2_N_9582_i) + ); + defparam plm_des2_lfsrs_N_85375_i.INIT = 16'hDFDD; + LUT4_L plm_des2_lfsrs_N_85375_i ( + .I0(plm_des2_N_49061_i), + .I1(plm_des2_reg_lfsr_two_12_iv_i_0_a2_0_4_), + .I2(plm_des2_reg_lfsr_two_12_iv_0_0_o4[9]), + .I3(plm_des2_one_adv2[4]), + .LO(plm_des2_N_85375_i) + ); + defparam plm_des2_lfsrs_reg_lfsr_two_12_iv_0_0_3_.INIT = 16'h2220; + LUT4_L plm_des2_lfsrs_reg_lfsr_two_12_iv_0_0_3_ ( + .I0(plm_des2_N_49061_i), + .I1(plm_des2_reg_lfsr_two_12_iv_0_0_a2_0[3]), + .I2(plm_des2_reg_lfsr_two_12_iv_0_0_o4[9]), + .I3(plm_des2_one_adv2[3]), + .LO(plm_des2_N_9584_i) + ); + defparam plm_des2_lfsrs_N_85374_i.INIT = 16'hDFDD; + LUT4_L plm_des2_lfsrs_N_85374_i ( + .I0(plm_des2_N_49061_i), + .I1(plm_des2_reg_lfsr_two_12_iv_i_0_a2_0_2_), + .I2(plm_des2_reg_lfsr_two_12_iv_0_0_o4[9]), + .I3(plm_des2_one_adv2[2]), + .LO(plm_des2_N_85374_i) + ); + defparam plm_des2_lfsrs_N_85373_i.INIT = 16'hDFDD; + LUT4_L plm_des2_lfsrs_N_85373_i ( + .I0(plm_des2_N_49061_i), + .I1(plm_des2_reg_lfsr_two_12_iv_i_0_a2_0_1_), + .I2(plm_des2_reg_lfsr_two_12_iv_0_0_o4[9]), + .I3(plm_des2_one_adv2[1]), + .LO(plm_des2_N_85373_i) + ); + defparam plm_des2_lfsrs_N_85372_i.INIT = 16'hF5FD; + LUT4_L plm_des2_lfsrs_N_85372_i ( + .I0(plm_des2_N_49061_i), + .I1(plm_des2_N_49077_i_0), + .I2(plm_des2_reg_lfsr_two_12_iv_i_0_a2_0_0_), + .I3(plm_des2_reg_lfsr_two_12_iv_0_0_o4[9]), + .LO(plm_des2_N_85372_i) + ); + defparam plm_des2_lfsrs_reg_lfsr_two_12_iv_0_0_a4_1_9_.INIT = 8'h01; + LUT3 plm_des2_lfsrs_reg_lfsr_two_12_iv_0_0_a4_1_9_ ( + .I0(plm_reg_com_0[1]), + .I1(plm_des2_reg_skp[1]), + .I2(plm_des2_reg_skp[0]), + .O(plm_des2_reg_lfsr_two_12_iv_0_0_a4_1[9]) + ); + FDC plm_des2_reg_rx_des_dat_13_ ( + .C(mgt_clk), + .D(plm_des2_N_49208_i_0_i), + .Q(plm_rx2_des_dat[13]), + .CLR(plm_rst) + ); + FDC plm_des2_reg_rx_des_dat_12_ ( + .C(mgt_clk), + .D(plm_des2_N_49206_i_0_i), + .Q(plm_rx2_des_dat[12]), + .CLR(plm_rst) + ); + FDC plm_des2_reg_rx_des_dat_11_ ( + .C(mgt_clk), + .D(plm_des2_N_49204_i_0_i), + .Q(plm_rx2_des_dat[11]), + .CLR(plm_rst) + ); + FDC plm_des2_reg_rx_des_dat_10_ ( + .C(mgt_clk), + .D(plm_des2_N_49202_i_0_i), + .Q(plm_rx2_des_dat[10]), + .CLR(plm_rst) + ); + FDC plm_des2_reg_rx_des_dat_9_ ( + .C(mgt_clk), + .D(plm_des2_N_49200_i_0_i), + .Q(plm_rx2_des_dat[9]), + .CLR(plm_rst) + ); + FDC plm_des2_reg_rx_des_dat_8_ ( + .C(mgt_clk), + .D(plm_des2_N_49198_i_0_i), + .Q(plm_rx2_des_dat[8]), + .CLR(plm_rst) + ); + FDC plm_des2_reg_rx_des_dat_7_ ( + .C(mgt_clk), + .D(plm_des2_reg_rx_des_dat_14[7]), + .Q(plm_rx2_des_dat[7]), + .CLR(plm_rst) + ); + FDC plm_des2_reg_rx_des_dat_6_ ( + .C(mgt_clk), + .D(plm_des2_reg_rx_des_dat_14[6]), + .Q(plm_rx2_des_dat[6]), + .CLR(plm_rst) + ); + FDC plm_des2_reg_rx_des_dat_5_ ( + .C(mgt_clk), + .D(plm_des2_reg_rx_des_dat_14[5]), + .Q(plm_rx2_des_dat[5]), + .CLR(plm_rst) + ); + FDC plm_des2_reg_rx_des_dat_4_ ( + .C(mgt_clk), + .D(plm_des2_reg_rx_des_dat_14[4]), + .Q(plm_rx2_des_dat[4]), + .CLR(plm_rst) + ); + FDC plm_des2_reg_rx_des_dat_3_ ( + .C(mgt_clk), + .D(plm_des2_reg_rx_des_dat_14[3]), + .Q(plm_rx2_des_dat[3]), + .CLR(plm_rst) + ); + FDC plm_des2_reg_rx_des_dat_2_ ( + .C(mgt_clk), + .D(plm_des2_reg_rx_des_dat_14[2]), + .Q(plm_rx2_des_dat[2]), + .CLR(plm_rst) + ); + FDC plm_des2_reg_rx_des_dat_1_ ( + .C(mgt_clk), + .D(plm_des2_reg_rx_des_dat_14[1]), + .Q(plm_rx2_des_dat[1]), + .CLR(plm_rst) + ); + FDC plm_des2_reg_rx_des_dat_0_ ( + .C(mgt_clk), + .D(plm_des2_reg_rx_des_dat_14[0]), + .Q(plm_rx2_des_dat[0]), + .CLR(plm_rst) + ); + FDC plm_des2_reg_rx_des_t1p_1_ ( + .C(mgt_clk), + .D(plm_des2_reg_t1p[1]), + .Q(plm_rx2_des_t1p[1]), + .CLR(plm_rst) + ); + FDC plm_des2_reg_rx_des_t1n_1_ ( + .C(mgt_clk), + .D(plm_des2_reg_t1n[1]), + .Q(plm_rx2_des_t1n[1]), + .CLR(plm_rst) + ); + FDC plm_des2_reg_t2p_1_ ( + .C(mgt_clk), + .D(plm_des2_reg_t2p_3[1]), + .Q(plm_des2_reg_t2p[1]), + .CLR(plm_rst) + ); + FDC plm_des2_reg_t2n_1_ ( + .C(mgt_clk), + .D(plm_des2_reg_t2n_3[1]), + .Q(plm_des2_reg_t2n[1]), + .CLR(plm_rst) + ); + FDC plm_des2_reg_rx_des_bad_1_ ( + .C(mgt_clk), + .D(plm_des2_reg_bad[1]), + .Q(plm_rx2_des_bad[1]), + .CLR(plm_rst) + ); + FDC plm_des2_reg_rx_des_bad_0_ ( + .C(mgt_clk), + .D(plm_des2_reg_bad[0]), + .Q(plm_rx2_des_bad[0]), + .CLR(plm_rst) + ); + FDC plm_des2_reg_bad_1_ ( + .C(mgt_clk), + .D(plm_des2_N_85320_i), + .Q(plm_des2_reg_bad[1]), + .CLR(plm_rst) + ); + FDC plm_des2_reg_bad_0_ ( + .C(mgt_clk), + .D(plm_des2_N_85321_i), + .Q(plm_des2_reg_bad[0]), + .CLR(plm_rst) + ); + FDC plm_des2_reg_rx_des_dat_15_ ( + .C(mgt_clk), + .D(plm_des2_N_49212_i_0_i), + .Q(plm_rx2_des_dat[15]), + .CLR(plm_rst) + ); + FDC plm_des2_reg_rx_des_dat_14_ ( + .C(mgt_clk), + .D(plm_des2_N_49210_i_0_i), + .Q(plm_rx2_des_dat[14]), + .CLR(plm_rst) + ); + FDC plm_des2_reg_rx_des_sym_1_ ( + .C(mgt_clk), + .D(plm_des2_reg_sym[1]), + .Q(plm_rx2_des_sym[1]), + .CLR(plm_rst) + ); + FDC plm_des2_reg_rx_des_sym_0_ ( + .C(mgt_clk), + .D(plm_des2_reg_sym[0]), + .Q(plm_rx2_des_sym[0]), + .CLR(plm_rst) + ); + FDC plm_des2_reg_skp_1_ ( + .C(mgt_clk), + .D(plm_des2_reg_skp_3[1]), + .Q(plm_des2_reg_skp[1]), + .CLR(plm_rst) + ); + FDC plm_des2_reg_skp_0_ ( + .C(mgt_clk), + .D(plm_des2_reg_skp_4[0]), + .Q(plm_des2_reg_skp[0]), + .CLR(plm_rst) + ); + FDC plm_des2_reg_com_1_ ( + .C(mgt_clk), + .D(plm_des2_reg_com_3[1]), + .Q(plm_reg_com_0[1]), + .CLR(plm_rst) + ); + FDC plm_des2_reg_com_0_ ( + .C(mgt_clk), + .D(plm_des2_reg_com_4[0]), + .Q(plm_reg_com_0[0]), + .CLR(plm_rst) + ); + FDC plm_des2_reg_rx_des_t2p_1_ ( + .C(mgt_clk), + .D(plm_des2_reg_t2p[1]), + .Q(plm_rx2_des_t2p[1]), + .CLR(plm_rst) + ); + FDC plm_des2_reg_rx_des_t2n_1_ ( + .C(mgt_clk), + .D(plm_des2_reg_t2n[1]), + .Q(plm_rx2_des_t2n[1]), + .CLR(plm_rst) + ); + FDC plm_des2_reg_rx_raw_dat_6_ ( + .C(mgt_clk), + .D(plm_des2_reg_dat[6]), + .Q(plm_rx2_raw_dat[6]), + .CLR(plm_rst) + ); + FDC plm_des2_reg_rx_raw_dat_5_ ( + .C(mgt_clk), + .D(plm_des2_reg_dat[5]), + .Q(plm_rx2_raw_dat[5]), + .CLR(plm_rst) + ); + FDC plm_des2_reg_rx_raw_dat_4_ ( + .C(mgt_clk), + .D(plm_des2_reg_dat[4]), + .Q(plm_rx2_raw_dat[4]), + .CLR(plm_rst) + ); + FDC plm_des2_reg_rx_raw_dat_3_ ( + .C(mgt_clk), + .D(plm_des2_reg_dat[3]), + .Q(plm_rx2_raw_dat[3]), + .CLR(plm_rst) + ); + FDC plm_des2_reg_rx_raw_dat_2_ ( + .C(mgt_clk), + .D(plm_des2_reg_dat[2]), + .Q(plm_rx2_raw_dat[2]), + .CLR(plm_rst) + ); + FDC plm_des2_reg_rx_raw_dat_1_ ( + .C(mgt_clk), + .D(plm_des2_reg_dat[1]), + .Q(plm_rx2_raw_dat[1]), + .CLR(plm_rst) + ); + FDC plm_des2_reg_rx_raw_dat_0_ ( + .C(mgt_clk), + .D(plm_des2_reg_dat[0]), + .Q(plm_rx2_raw_dat[0]), + .CLR(plm_rst) + ); + FDC plm_des2_reg_t1p_1_ ( + .C(mgt_clk), + .D(plm_des2_reg_t1p_3[1]), + .Q(plm_des2_reg_t1p[1]), + .CLR(plm_rst) + ); + FDC plm_des2_reg_t1n_1_ ( + .C(mgt_clk), + .D(plm_des2_reg_t1n_3[1]), + .Q(plm_des2_reg_t1n[1]), + .CLR(plm_rst) + ); + FDC plm_des2_reg_spesh_1_ ( + .C(mgt_clk), + .D(plm_rx2_char_is_k[1]), + .Q(plm_des2_reg_spesh[1]), + .CLR(plm_rst) + ); + FDC plm_des2_reg_spesh_0_ ( + .C(mgt_clk), + .D(plm_rx2_char_is_k[0]), + .Q(plm_des2_reg_spesh[0]), + .CLR(plm_rst) + ); + FDC plm_des2_reg_nitbl_1_ ( + .C(mgt_clk), + .D(plm_rx2_not_in_table[1]), + .Q(plm_des2_reg_nitbl[1]), + .CLR(plm_rst) + ); + FDC plm_des2_reg_nitbl_0_ ( + .C(mgt_clk), + .D(plm_rx2_not_in_table[0]), + .Q(plm_des2_reg_nitbl[0]), + .CLR(plm_rst) + ); + FDC plm_des2_reg_sym_1_ ( + .C(mgt_clk), + .D(plm_des2_reg_sym_3[1]), + .Q(plm_des2_reg_sym[1]), + .CLR(plm_rst) + ); + FDC plm_des2_reg_sym_0_ ( + .C(mgt_clk), + .D(plm_des2_reg_sym_4[0]), + .Q(plm_des2_reg_sym[0]), + .CLR(plm_rst) + ); + FDC plm_des2_reg_rx_raw_dat_15_ ( + .C(mgt_clk), + .D(plm_des2_reg_dat[15]), + .Q(plm_rx2_raw_dat[15]), + .CLR(plm_rst) + ); + FDC plm_des2_reg_rx_raw_dat_14_ ( + .C(mgt_clk), + .D(plm_des2_reg_dat[14]), + .Q(plm_rx2_raw_dat[14]), + .CLR(plm_rst) + ); + FDC plm_des2_reg_rx_raw_dat_13_ ( + .C(mgt_clk), + .D(plm_des2_reg_dat[13]), + .Q(plm_rx2_raw_dat[13]), + .CLR(plm_rst) + ); + FDC plm_des2_reg_rx_raw_dat_12_ ( + .C(mgt_clk), + .D(plm_des2_reg_dat[12]), + .Q(plm_rx2_raw_dat[12]), + .CLR(plm_rst) + ); + FDC plm_des2_reg_rx_raw_dat_11_ ( + .C(mgt_clk), + .D(plm_des2_reg_dat[11]), + .Q(plm_rx2_raw_dat[11]), + .CLR(plm_rst) + ); + FDC plm_des2_reg_rx_raw_dat_10_ ( + .C(mgt_clk), + .D(plm_des2_reg_dat[10]), + .Q(plm_rx2_raw_dat[10]), + .CLR(plm_rst) + ); + FDC plm_des2_reg_rx_raw_dat_9_ ( + .C(mgt_clk), + .D(plm_des2_reg_dat[9]), + .Q(plm_rx2_raw_dat[9]), + .CLR(plm_rst) + ); + FDC plm_des2_reg_rx_raw_dat_8_ ( + .C(mgt_clk), + .D(plm_des2_reg_dat[8]), + .Q(plm_rx2_raw_dat[8]), + .CLR(plm_rst) + ); + FDC plm_des2_reg_rx_raw_dat_7_ ( + .C(mgt_clk), + .D(plm_des2_reg_dat[7]), + .Q(plm_rx2_raw_dat[7]), + .CLR(plm_rst) + ); + FDC plm_des2_reg_data_14_ ( + .C(mgt_clk), + .D(plm_rx2_data[14]), + .Q(plm_des2_reg_data[14]), + .CLR(plm_rst) + ); + FDC plm_des2_reg_data_13_ ( + .C(mgt_clk), + .D(plm_rx2_data[13]), + .Q(plm_des2_reg_data[13]), + .CLR(plm_rst) + ); + FDC plm_des2_reg_data_12_ ( + .C(mgt_clk), + .D(plm_rx2_data[12]), + .Q(plm_des2_reg_data[12]), + .CLR(plm_rst) + ); + FDC plm_des2_reg_data_11_ ( + .C(mgt_clk), + .D(plm_rx2_data[11]), + .Q(plm_des2_reg_data[11]), + .CLR(plm_rst) + ); + FDC plm_des2_reg_data_10_ ( + .C(mgt_clk), + .D(plm_rx2_data[10]), + .Q(plm_des2_reg_data[10]), + .CLR(plm_rst) + ); + FDC plm_des2_reg_data_9_ ( + .C(mgt_clk), + .D(plm_rx2_data[9]), + .Q(plm_des2_reg_data[9]), + .CLR(plm_rst) + ); + FDC plm_des2_reg_data_8_ ( + .C(mgt_clk), + .D(plm_rx2_data[8]), + .Q(plm_des2_reg_data[8]), + .CLR(plm_rst) + ); + FDC plm_des2_reg_data_7_ ( + .C(mgt_clk), + .D(plm_rx2_data[7]), + .Q(plm_des2_reg_data[7]), + .CLR(plm_rst) + ); + FDC plm_des2_reg_data_6_ ( + .C(mgt_clk), + .D(plm_rx2_data[6]), + .Q(plm_des2_reg_data[6]), + .CLR(plm_rst) + ); + FDC plm_des2_reg_data_5_ ( + .C(mgt_clk), + .D(plm_rx2_data[5]), + .Q(plm_des2_reg_data[5]), + .CLR(plm_rst) + ); + FDC plm_des2_reg_data_4_ ( + .C(mgt_clk), + .D(plm_rx2_data[4]), + .Q(plm_des2_reg_data[4]), + .CLR(plm_rst) + ); + FDC plm_des2_reg_data_3_ ( + .C(mgt_clk), + .D(plm_rx2_data[3]), + .Q(plm_des2_reg_data[3]), + .CLR(plm_rst) + ); + FDC plm_des2_reg_data_2_ ( + .C(mgt_clk), + .D(plm_rx2_data[2]), + .Q(plm_des2_reg_data[2]), + .CLR(plm_rst) + ); + FDC plm_des2_reg_data_1_ ( + .C(mgt_clk), + .D(plm_rx2_data[1]), + .Q(plm_des2_reg_data[1]), + .CLR(plm_rst) + ); + FDC plm_des2_reg_data_0_ ( + .C(mgt_clk), + .D(plm_rx2_data[0]), + .Q(plm_des2_reg_data[0]), + .CLR(plm_rst) + ); + FDC plm_des2_reg_dat_11_ ( + .C(mgt_clk), + .D(plm_des2_reg_data[11]), + .Q(plm_des2_reg_dat[11]), + .CLR(plm_rst) + ); + FDC plm_des2_reg_dat_10_ ( + .C(mgt_clk), + .D(plm_des2_reg_data[10]), + .Q(plm_des2_reg_dat[10]), + .CLR(plm_rst) + ); + FDC plm_des2_reg_dat_9_ ( + .C(mgt_clk), + .D(plm_des2_reg_data[9]), + .Q(plm_des2_reg_dat[9]), + .CLR(plm_rst) + ); + FDC plm_des2_reg_dat_8_ ( + .C(mgt_clk), + .D(plm_des2_reg_data[8]), + .Q(plm_des2_reg_dat[8]), + .CLR(plm_rst) + ); + FDC plm_des2_reg_dat_7_ ( + .C(mgt_clk), + .D(plm_des2_reg_data[7]), + .Q(plm_des2_reg_dat[7]), + .CLR(plm_rst) + ); + FDC plm_des2_reg_dat_6_ ( + .C(mgt_clk), + .D(plm_des2_reg_data[6]), + .Q(plm_des2_reg_dat[6]), + .CLR(plm_rst) + ); + FDC plm_des2_reg_dat_5_ ( + .C(mgt_clk), + .D(plm_des2_reg_data[5]), + .Q(plm_des2_reg_dat[5]), + .CLR(plm_rst) + ); + FDC plm_des2_reg_dat_4_ ( + .C(mgt_clk), + .D(plm_des2_reg_data[4]), + .Q(plm_des2_reg_dat[4]), + .CLR(plm_rst) + ); + FDC plm_des2_reg_dat_3_ ( + .C(mgt_clk), + .D(plm_des2_reg_data[3]), + .Q(plm_des2_reg_dat[3]), + .CLR(plm_rst) + ); + FDC plm_des2_reg_dat_2_ ( + .C(mgt_clk), + .D(plm_des2_reg_data[2]), + .Q(plm_des2_reg_dat[2]), + .CLR(plm_rst) + ); + FDC plm_des2_reg_dat_1_ ( + .C(mgt_clk), + .D(plm_des2_reg_data[1]), + .Q(plm_des2_reg_dat[1]), + .CLR(plm_rst) + ); + FDC plm_des2_reg_dat_0_ ( + .C(mgt_clk), + .D(plm_des2_reg_data[0]), + .Q(plm_des2_reg_dat[0]), + .CLR(plm_rst) + ); + FDC plm_des2_reg_kkk_1_ ( + .C(mgt_clk), + .D(plm_des2_reg_spesh[1]), + .Q(plm_des2_reg_kkk[1]), + .CLR(plm_rst) + ); + FDC plm_des2_reg_kkk_0_ ( + .C(mgt_clk), + .D(plm_des2_reg_spesh[0]), + .Q(plm_des2_reg_kkk[0]), + .CLR(plm_rst) + ); + FDC plm_des2_reg_data_15_ ( + .C(mgt_clk), + .D(plm_rx2_data[15]), + .Q(plm_des2_reg_data[15]), + .CLR(plm_rst) + ); + FDC plm_des2_reg_dat_15_ ( + .C(mgt_clk), + .D(plm_des2_reg_data[15]), + .Q(plm_des2_reg_dat[15]), + .CLR(plm_rst) + ); + FDC plm_des2_reg_dat_14_ ( + .C(mgt_clk), + .D(plm_des2_reg_data[14]), + .Q(plm_des2_reg_dat[14]), + .CLR(plm_rst) + ); + FDC plm_des2_reg_dat_13_ ( + .C(mgt_clk), + .D(plm_des2_reg_data[13]), + .Q(plm_des2_reg_dat[13]), + .CLR(plm_rst) + ); + FDC plm_des2_reg_dat_12_ ( + .C(mgt_clk), + .D(plm_des2_reg_data[12]), + .Q(plm_des2_reg_dat[12]), + .CLR(plm_rst) + ); + FDPE plm_des2_reg_lfsr_one_15_ ( + .PRE(plm_rst), + .CE(plm_des2_reg_lfsr_one32_i), + .C(mgt_clk), + .D(plm_des2_N_87684_i), + .Q(plm_des2_reg_lfsr_one_15__520) + ); + FDPE plm_des2_reg_lfsr_one_14_ ( + .PRE(plm_rst), + .CE(plm_des2_reg_lfsr_one32_i), + .C(mgt_clk), + .D(plm_des2_N_87683_i), + .Q(plm_des2_reg_lfsr_one_14__656) + ); + FDPE plm_des2_reg_lfsr_one_13_ ( + .PRE(plm_rst), + .CE(plm_des2_reg_lfsr_one32_i), + .C(mgt_clk), + .D(plm_des2_N_87682_i), + .Q(plm_des2_reg_lfsr_one_13__523) + ); + FDPE plm_des2_reg_lfsr_one_12_ ( + .PRE(plm_rst), + .CE(plm_des2_reg_lfsr_one32_i), + .C(mgt_clk), + .D(plm_des2_N_85371_i), + .Q(plm_des2_reg_lfsr_one_12__1001) + ); + FDPE plm_des2_reg_lfsr_one_11_ ( + .PRE(plm_rst), + .CE(plm_des2_reg_lfsr_one32_i), + .C(mgt_clk), + .D(plm_des2_N_87681_i), + .Q(plm_des2_reg_lfsr_one_11__642) + ); + FDPE plm_des2_reg_lfsr_one_10_ ( + .PRE(plm_rst), + .CE(plm_des2_reg_lfsr_one32_i), + .C(mgt_clk), + .D(plm_des2_N_85370_i), + .Q(plm_des2_reg_lfsr_one_10__1002) + ); + FDPE plm_des2_reg_lfsr_one_9_ ( + .PRE(plm_rst), + .CE(plm_des2_reg_lfsr_one32_i), + .C(mgt_clk), + .D(plm_des2_N_85369_i), + .Q(plm_des2_reg_lfsr_one_9__1003) + ); + FDPE plm_des2_reg_lfsr_one_8_ ( + .PRE(plm_rst), + .CE(plm_des2_reg_lfsr_one32_i), + .C(mgt_clk), + .D(plm_des2_N_85368_i), + .Q(plm_des2_reg_lfsr_one_8__1004) + ); + FDPE plm_des2_reg_lfsr_one_7_ ( + .PRE(plm_rst), + .CE(plm_des2_reg_lfsr_one32_i), + .C(mgt_clk), + .D(plm_des2_N_85367_i), + .Q(plm_des2_reg_lfsr_one_7__1005) + ); + FDPE plm_des2_reg_lfsr_one_6_ ( + .PRE(plm_rst), + .CE(plm_des2_reg_lfsr_one32_i), + .C(mgt_clk), + .D(plm_des2_N_85366_i), + .Q(plm_des2_reg_lfsr_one_6__1006) + ); + FDPE plm_des2_reg_lfsr_one_5_ ( + .PRE(plm_rst), + .CE(plm_des2_reg_lfsr_one32_i), + .C(mgt_clk), + .D(plm_des2_N_85365_i), + .Q(plm_des2_reg_lfsr_one_5__1007) + ); + FDPE plm_des2_reg_lfsr_one_4_ ( + .PRE(plm_rst), + .CE(plm_des2_reg_lfsr_one32_i), + .C(mgt_clk), + .D(plm_des2_N_87680_i), + .Q(plm_des2_reg_lfsr_one_4__1008) + ); + FDPE plm_des2_reg_lfsr_one_3_ ( + .PRE(plm_rst), + .CE(plm_des2_reg_lfsr_one32_i), + .C(mgt_clk), + .D(plm_des2_N_85364_i), + .Q(plm_des2_reg_lfsr_one_3__522) + ); + FDPE plm_des2_reg_lfsr_one_2_ ( + .PRE(plm_rst), + .CE(plm_des2_reg_lfsr_one32_i), + .C(mgt_clk), + .D(plm_des2_N_87679_i), + .Q(plm_des2_reg_lfsr_one_2__1009) + ); + FDPE plm_des2_reg_lfsr_one_1_ ( + .PRE(plm_rst), + .CE(plm_des2_reg_lfsr_one32_i), + .C(mgt_clk), + .D(plm_des2_N_87678_i), + .Q(plm_des2_reg_lfsr_one_1__519) + ); + FDPE plm_des2_reg_lfsr_one_0_ ( + .PRE(plm_rst), + .CE(plm_des2_reg_lfsr_one32_i), + .C(mgt_clk), + .D(plm_des2_N_87665_i), + .Q(plm_des2_reg_lfsr_one_0__641) + ); + FDPE plm_des2_reg_lfsr_two_15_ ( + .PRE(plm_rst), + .CE(plm_des2_reg_lfsr_one32_i), + .C(mgt_clk), + .D(plm_des2_N_85379_i), + .Q(plm_des2_reg_lfsr_two_15__488) + ); + FDPE plm_des2_reg_lfsr_two_14_ ( + .PRE(plm_rst), + .CE(plm_des2_reg_lfsr_one32_i), + .C(mgt_clk), + .D(plm_des2_N_85378_i), + .Q(plm_des2_reg_lfsr_two_14__655) + ); + FDPE plm_des2_reg_lfsr_two_13_ ( + .PRE(plm_rst), + .CE(plm_des2_reg_lfsr_one32_i), + .C(mgt_clk), + .D(plm_des2_N_85377_i), + .Q(plm_des2_reg_lfsr_two_13__487) + ); + FDCE plm_des2_reg_lfsr_two_12_ ( + .CE(plm_des2_reg_lfsr_one32_i), + .C(mgt_clk), + .D(plm_des2_N_9575_i), + .Q(plm_des2_reg_lfsr_two_12__1010), + .CLR(plm_rst) + ); + FDPE plm_des2_reg_lfsr_two_11_ ( + .PRE(plm_rst), + .CE(plm_des2_reg_lfsr_one32_i), + .C(mgt_clk), + .D(plm_des2_N_85376_i), + .Q(plm_des2_reg_lfsr_two_11__486) + ); + FDCE plm_des2_reg_lfsr_two_10_ ( + .CE(plm_des2_reg_lfsr_one32_i), + .C(mgt_clk), + .D(plm_des2_N_9577_i), + .Q(plm_des2_reg_lfsr_two_10__1011), + .CLR(plm_rst) + ); + FDCE plm_des2_reg_lfsr_two_9_ ( + .CE(plm_des2_reg_lfsr_one32_i), + .C(mgt_clk), + .D(plm_des2_N_9578_i), + .Q(plm_des2_reg_lfsr_two_9__1012), + .CLR(plm_rst) + ); + FDCE plm_des2_reg_lfsr_two_8_ ( + .CE(plm_des2_reg_lfsr_one32_i), + .C(mgt_clk), + .D(plm_des2_N_9579_i), + .Q(plm_des2_reg_lfsr_two_8__1013), + .CLR(plm_rst) + ); + FDCE plm_des2_reg_lfsr_two_7_ ( + .CE(plm_des2_reg_lfsr_one32_i), + .C(mgt_clk), + .D(plm_des2_N_9580_i), + .Q(plm_des2_reg_lfsr_two_7__1014), + .CLR(plm_rst) + ); + FDCE plm_des2_reg_lfsr_two_6_ ( + .CE(plm_des2_reg_lfsr_one32_i), + .C(mgt_clk), + .D(plm_des2_N_9581_i), + .Q(plm_des2_reg_lfsr_two_6__1015), + .CLR(plm_rst) + ); + FDCE plm_des2_reg_lfsr_two_5_ ( + .CE(plm_des2_reg_lfsr_one32_i), + .C(mgt_clk), + .D(plm_des2_N_9582_i), + .Q(plm_des2_reg_lfsr_two_5__1016), + .CLR(plm_rst) + ); + FDPE plm_des2_reg_lfsr_two_4_ ( + .PRE(plm_rst), + .CE(plm_des2_reg_lfsr_one32_i), + .C(mgt_clk), + .D(plm_des2_N_85375_i), + .Q(plm_des2_reg_lfsr_two_4__664) + ); + FDCE plm_des2_reg_lfsr_two_3_ ( + .CE(plm_des2_reg_lfsr_one32_i), + .C(mgt_clk), + .D(plm_des2_N_9584_i), + .Q(plm_des2_reg_lfsr_two_3__1017), + .CLR(plm_rst) + ); + FDPE plm_des2_reg_lfsr_two_2_ ( + .PRE(plm_rst), + .CE(plm_des2_reg_lfsr_one32_i), + .C(mgt_clk), + .D(plm_des2_N_85374_i), + .Q(plm_des2_reg_lfsr_two_2__663) + ); + FDPE plm_des2_reg_lfsr_two_1_ ( + .PRE(plm_rst), + .CE(plm_des2_reg_lfsr_one32_i), + .C(mgt_clk), + .D(plm_des2_N_85373_i), + .Q(plm_des2_reg_lfsr_two_1__662) + ); + FDPE plm_des2_reg_lfsr_two_0_ ( + .PRE(plm_rst), + .CE(plm_des2_reg_lfsr_one32_i), + .C(mgt_clk), + .D(plm_des2_N_85372_i), + .Q(plm_des2_reg_lfsr_two_0__485) + ); + defparam plm_des3_input_decoder_reg_sym_4_0_a7_0_.INIT = 4'h1; + LUT2 plm_des3_input_decoder_reg_sym_4_0_a7_0_ ( + .I0(plm_des3_reg_nitbl[0]), + .I1(plm_des3_reg_spesh[0]), + .O(plm_des3_reg_sym_4[0]) + ); + defparam plm_des3_input_decoder_reg_sym_3_0_a7_1_.INIT = 4'h1; + LUT2 plm_des3_input_decoder_reg_sym_3_0_a7_1_ ( + .I0(plm_des3_reg_nitbl[1]), + .I1(plm_des3_reg_spesh[1]), + .O(plm_des3_reg_sym_3[1]) + ); + defparam plm_des3_input_decoder_reg_skp_3_0_a7_1_1_.INIT = 4'h1; + LUT2 plm_des3_input_decoder_reg_skp_3_0_a7_1_1_ ( + .I0(plm_des3_reg_data[13]), + .I1(plm_des3_reg_data[15]), + .O(plm_des3_reg_skp_3_1[1]) + ); + defparam plm_des3_input_decoder_reg_skp_4_0_a7_1_0_.INIT = 4'h1; + LUT2 plm_des3_input_decoder_reg_skp_4_0_a7_1_0_ ( + .I0(plm_des3_reg_data[5]), + .I1(plm_des3_reg_data[7]), + .O(plm_des3_reg_skp_4_1[0]) + ); + defparam plm_des3_descram_reg_rx_des_dat_14_sn_m1_0_a2_0_a3_0_a2_0_a2.INIT = 4'h1; + LUT2 plm_des3_descram_reg_rx_des_dat_14_sn_m1_0_a2_0_a3_0_a2_0_a2 ( + .I0(plm_reg_dis), + .I1(plm_des3_reg_kkk[0]), + .O(plm_des3_m1_0_a2_0_a3_0_a2_0_a2_2) + ); + defparam plm_des3_lfsrs_reg_lfsr_one_12_0_iv_i_i_o4_0_.INIT = 4'h1; + LUT2 plm_des3_lfsrs_reg_lfsr_one_12_0_iv_i_i_o4_0_ ( + .I0(plm_des3_reg_skp[0]), + .I1(plm_des3_reg_skp[1]), + .O(plm_des3_N_49055_i) + ); + defparam plm_des3_descram_reg_rx_des_dat_7_i_x2_0_x2_0_o4_0_8_.INIT = 4'h1; + LUT2 plm_des3_descram_reg_rx_des_dat_7_i_x2_0_x2_0_o4_0_8_ ( + .I0(plm_reg_dis), + .I1(plm_des3_reg_kkk[1]), + .O(plm_des3_N_49064_i) + ); + defparam plm_des3_lfsrs_reg_lfsr_two_12_0_iv_0_o2_12_.INIT = 4'h1; + LUT2 plm_des3_lfsrs_reg_lfsr_two_12_0_iv_0_o2_12_ ( + .I0(plm_reg_com_1[0]), + .I1(plm_reg_com_1[1]), + .O(plm_des3_reg_lfsr_two_12_0_iv_0_o2_0[12]) + ); + defparam plm_des3_one_adv2_1_15_.INIT = 4'h6; + LUT2 plm_des3_one_adv2_1_15_ ( + .I0(plm_des3_reg_lfsr_one_10__1034), + .I1(plm_des3_reg_lfsr_one_11__636), + .O(plm_des3_one_adv2_1_15__1018) + ); + defparam plm_des3_one_adv2_1_13_.INIT = 4'h6; + LUT2 plm_des3_one_adv2_1_13_ ( + .I0(plm_des3_reg_lfsr_one_8__1036), + .I1(plm_des3_reg_lfsr_one_9__1035), + .O(plm_des3_one_adv2_1_13__1019) + ); + defparam plm_des3_one_adv2_1_9_.INIT = 4'h6; + LUT2 plm_des3_one_adv2_1_9_ ( + .I0(plm_des3_reg_lfsr_one_4__1040), + .I1(plm_des3_reg_lfsr_one_5__1039), + .O(plm_des3_one_adv2_1_9__1023) + ); + defparam plm_des3_one_adv2_1_6_.INIT = 4'h6; + LUT2 plm_des3_one_adv2_1_6_ ( + .I0(plm_des3_reg_lfsr_one_1__513), + .I1(plm_des3_reg_lfsr_one_12__620), + .O(plm_des3_one_adv2_1_6__1022) + ); + defparam plm_des3_one_adv2_1_5_.INIT = 4'h6; + LUT2 plm_des3_one_adv2_1_5_ ( + .I0(plm_des3_reg_lfsr_one_2__1041), + .I1(plm_des3_reg_lfsr_one_13__517), + .O(plm_des3_one_adv2_1_5__1024) + ); + defparam plm_des3_two_adv2_1_14_.INIT = 4'h6; + LUT2 plm_des3_two_adv2_1_14_ ( + .I0(plm_des3_reg_lfsr_two_9__1043), + .I1(plm_des3_reg_lfsr_two_10__1042), + .O(plm_des3_two_adv2_1_14__1029) + ); + defparam plm_des3_two_adv2_1_12_.INIT = 4'h6; + LUT2 plm_des3_two_adv2_1_12_ ( + .I0(plm_des3_reg_lfsr_two_7__1045), + .I1(plm_des3_reg_lfsr_two_8__1044), + .O(plm_des3_two_adv2_1_12__1020) + ); + defparam plm_des3_two_adv2_1_10_.INIT = 4'h6; + LUT2 plm_des3_two_adv2_1_10_ ( + .I0(plm_des3_reg_lfsr_two_5__1047), + .I1(plm_des3_reg_lfsr_two_6__1046), + .O(plm_des3_two_adv2_1_10__1025) + ); + defparam plm_des3_two_adv2_1_6_.INIT = 4'h6; + LUT2 plm_des3_two_adv2_1_6_ ( + .I0(plm_des3_reg_lfsr_two_1__1048), + .I1(plm_des3_reg_lfsr_two_2__661), + .O(plm_des3_two_adv2_1_6__1027) + ); + defparam plm_des3_two_adv2_1_1_.INIT = 4'h6; + LUT2 plm_des3_two_adv2_1_1_ ( + .I0(plm_des3_reg_lfsr_two_12__627), + .I1(plm_des3_reg_lfsr_two_13__527), + .O(plm_des3_two_adv2_1_1__1021) + ); + defparam plm_des3_input_decoder_reg_bad_4_i_a7_2_0_0_.INIT = 4'h4; + LUT2_L plm_des3_input_decoder_reg_bad_4_i_a7_2_0_0_ ( + .I0(plm_des3_reg_data[5]), + .I1(plm_des3_reg_data[7]), + .LO(plm_des3_reg_bad_4_i_a7_2_0[0]) + ); + defparam plm_des3_input_decoder_reg_bad_3_i_a7_2_0_1_.INIT = 4'h4; + LUT2_L plm_des3_input_decoder_reg_bad_3_i_a7_2_0_1_ ( + .I0(plm_des3_reg_data[13]), + .I1(plm_des3_reg_data[15]), + .LO(plm_des3_reg_bad_3_i_a7_2_0[1]) + ); + defparam plm_des3_two_adv2_0_4_.INIT = 4'h6; + LUT2 plm_des3_two_adv2_0_4_ ( + .I0(plm_des3_reg_lfsr_two_0__525), + .I1(plm_des3_reg_lfsr_two_1__1048), + .O(plm_des3_two_adv2_0[4]) + ); + defparam plm_des3_lfsrs_reg_lfsr_one32_i.INIT = 4'h7; + LUT2 plm_des3_lfsrs_reg_lfsr_one32_i ( + .I0(plm_des3_reg_skp[0]), + .I1(plm_des3_reg_skp[1]), + .O(plm_des3_reg_lfsr_one32_i) + ); + defparam plm_des3_input_decoder_reg_bad_4_i_x2_0_.INIT = 16'h7888; + LUT4 plm_des3_input_decoder_reg_bad_4_i_x2_0_ ( + .I0(plm_des3_reg_data[0]), + .I1(plm_des3_reg_data[1]), + .I2(plm_des3_reg_data[2]), + .I3(plm_des3_reg_data[3]), + .O(plm_des3_N_14057_i) + ); + defparam plm_des3_input_decoder_reg_bad_4_i_x2_0_0_.INIT = 16'hE111; + LUT4 plm_des3_input_decoder_reg_bad_4_i_x2_0_0_ ( + .I0(plm_des3_reg_data[0]), + .I1(plm_des3_reg_data[1]), + .I2(plm_des3_reg_data[6]), + .I3(plm_des3_reg_data[7]), + .O(plm_des3_N_14058_i) + ); + defparam plm_des3_input_decoder_reg_bad_3_i_x2_1_.INIT = 16'h7888; + LUT4 plm_des3_input_decoder_reg_bad_3_i_x2_1_ ( + .I0(plm_des3_reg_data[8]), + .I1(plm_des3_reg_data[9]), + .I2(plm_des3_reg_data[10]), + .I3(plm_des3_reg_data[11]), + .O(plm_des3_N_14094_i) + ); + defparam plm_des3_input_decoder_reg_bad_3_i_x2_0_1_.INIT = 16'hE111; + LUT4 plm_des3_input_decoder_reg_bad_3_i_x2_0_1_ ( + .I0(plm_des3_reg_data[8]), + .I1(plm_des3_reg_data[9]), + .I2(plm_des3_reg_data[14]), + .I3(plm_des3_reg_data[15]), + .O(plm_des3_N_14095_i) + ); + defparam plm_des3_input_decoder_reg_skp_3_0_a7_3_1_.INIT = 16'h1000; + LUT4 plm_des3_input_decoder_reg_skp_3_0_a7_3_1_ ( + .I0(plm_des3_reg_data[8]), + .I1(plm_des3_reg_data[9]), + .I2(plm_des3_reg_data[10]), + .I3(plm_des3_reg_data[11]), + .O(plm_des3_reg_skp_3_3[1]) + ); + defparam plm_des3_input_decoder_reg_skp_4_0_a7_3_0_.INIT = 16'h1000; + LUT4 plm_des3_input_decoder_reg_skp_4_0_a7_3_0_ ( + .I0(plm_des3_reg_data[0]), + .I1(plm_des3_reg_data[1]), + .I2(plm_des3_reg_data[2]), + .I3(plm_des3_reg_data[3]), + .O(plm_des3_reg_skp_4_3[0]) + ); + defparam plm_des3_lfsrs_reg_lfsr_two_12_iv_0_0_o4_9_.INIT = 8'h23; + LUT3 plm_des3_lfsrs_reg_lfsr_two_12_iv_0_0_o4_9_ ( + .I0(plm_reg_com_1[1]), + .I1(plm_des3_reg_skp[0]), + .I2(plm_des3_reg_skp[1]), + .O(plm_des3_reg_lfsr_two_12_iv_0_0_o4_0[9]) + ); + defparam plm_des3_lfsrs_reg_lfsr_two_12_iv_0_0_o2_9_.INIT = 8'h15; + LUT3 plm_des3_lfsrs_reg_lfsr_two_12_iv_0_0_o2_9_ ( + .I0(plm_reg_com_1[0]), + .I1(plm_reg_com_1[1]), + .I2(plm_des3_reg_skp[0]), + .O(plm_des3_N_49062_i) + ); + defparam plm_des3_two_adv2_15_.INIT = 16'h6996; + LUT4 plm_des3_two_adv2_15_ ( + .I0(plm_des3_reg_lfsr_two_10__1042), + .I1(plm_des3_reg_lfsr_two_11__526), + .I2(plm_des3_reg_lfsr_two_12__627), + .I3(plm_des3_reg_lfsr_two_15__528), + .O(plm_des3_two_adv2_15__1028) + ); + defparam plm_des3_input_decoder_reg_t2n_4_0_a7_1_0_0_.INIT = 8'h20; + LUT3 plm_des3_input_decoder_reg_t2n_4_0_a7_1_0_0_ ( + .I0(plm_des3_reg_sym_4[0]), + .I1(plm_des3_reg_data[6]), + .I2(plm_des3_reg_data[7]), + .O(plm_des3_reg_t2n_4_1_0[0]) + ); + defparam plm_des3_input_decoder_reg_t1n_3_0_a7_1_1_.INIT = 8'h20; + LUT3 plm_des3_input_decoder_reg_t1n_3_0_a7_1_1_ ( + .I0(plm_des3_reg_sym_3[1]), + .I1(plm_des3_reg_data[14]), + .I2(plm_des3_reg_data[15]), + .O(plm_des3_reg_t1n_3_1[1]) + ); + defparam plm_des3_input_decoder_reg_t1n_3_0_a7_2_1_.INIT = 16'h0020; + LUT4 plm_des3_input_decoder_reg_t1n_3_0_a7_2_1_ ( + .I0(plm_des3_reg_data[8]), + .I1(plm_des3_reg_data[9]), + .I2(plm_des3_reg_data[10]), + .I3(plm_des3_reg_data[11]), + .O(plm_des3_reg_t1n_3_2[1]) + ); + defparam plm_des3_one_adv2_2_.INIT = 8'h96; + LUT3 plm_des3_one_adv2_2_ ( + .I0(plm_des3_one_adv2_1_5__1024), + .I1(plm_des3_reg_lfsr_one_14__657), + .I2(plm_des3_reg_lfsr_one_15__514), + .O(plm_des3_one_adv2[2]) + ); + defparam plm_des3_one_adv2_1_.INIT = 8'h96; + LUT3 plm_des3_one_adv2_1_ ( + .I0(plm_des3_one_adv2_1_6__1022), + .I1(plm_des3_reg_lfsr_one_13__517), + .I2(plm_des3_reg_lfsr_one_14__657), + .O(plm_des3_one_adv2[1]) + ); + defparam plm_des3_two_adv2_12_.INIT = 8'h96; + LUT3 plm_des3_two_adv2_12_ ( + .I0(plm_des3_reg_lfsr_two_9__1043), + .I1(plm_des3_reg_lfsr_two_12__627), + .I2(plm_des3_two_adv2_1_12__1020), + .O(plm_des3_two_adv2_12__1030) + ); + defparam plm_des3_two_adv2_10_.INIT = 8'h96; + LUT3 plm_des3_two_adv2_10_ ( + .I0(plm_des3_reg_lfsr_two_7__1045), + .I1(plm_des3_reg_lfsr_two_10__1042), + .I2(plm_des3_two_adv2_1_10__1025), + .O(plm_des3_two_adv2_10__1031) + ); + defparam plm_des3_one_adv2_15_.INIT = 8'h96; + LUT3 plm_des3_one_adv2_15_ ( + .I0(plm_des3_one_adv2_1_15__1018), + .I1(plm_des3_reg_lfsr_one_12__620), + .I2(plm_des3_reg_lfsr_one_15__514), + .O(plm_des3_one_adv2[15]) + ); + defparam plm_des3_one_adv2_14_.INIT = 8'h96; + LUT3 plm_des3_one_adv2_14_ ( + .I0(plm_des3_one_adv2_1_15__1018), + .I1(plm_des3_reg_lfsr_one_9__1035), + .I2(plm_des3_reg_lfsr_one_14__657), + .O(plm_des3_one_adv2[14]) + ); + defparam plm_des3_one_adv2_13_.INIT = 8'h96; + LUT3 plm_des3_one_adv2_13_ ( + .I0(plm_des3_one_adv2_1_13__1019), + .I1(plm_des3_reg_lfsr_one_10__1034), + .I2(plm_des3_reg_lfsr_one_13__517), + .O(plm_des3_one_adv2[13]) + ); + defparam plm_des3_one_adv2_12_.INIT = 8'h96; + LUT3 plm_des3_one_adv2_12_ ( + .I0(plm_des3_one_adv2_1_13__1019), + .I1(plm_des3_reg_lfsr_one_7__1037), + .I2(plm_des3_reg_lfsr_one_12__620), + .O(plm_des3_one_adv2[12]) + ); + defparam plm_des3_one_adv2_11_.INIT = 16'h6996; + LUT4 plm_des3_one_adv2_11_ ( + .I0(plm_des3_reg_lfsr_one_6__1038), + .I1(plm_des3_reg_lfsr_one_7__1037), + .I2(plm_des3_reg_lfsr_one_8__1036), + .I3(plm_des3_reg_lfsr_one_11__636), + .O(plm_des3_one_adv2[11]) + ); + defparam plm_des3_one_adv2_10_.INIT = 16'h6996; + LUT4 plm_des3_one_adv2_10_ ( + .I0(plm_des3_reg_lfsr_one_5__1039), + .I1(plm_des3_reg_lfsr_one_6__1038), + .I2(plm_des3_reg_lfsr_one_7__1037), + .I3(plm_des3_reg_lfsr_one_10__1034), + .O(plm_des3_one_adv2[10]) + ); + defparam plm_des3_input_decoder_reg_t1p_3_0_a7_2_1_.INIT = 8'h20; + LUT3 plm_des3_input_decoder_reg_t1p_3_0_a7_2_1_ ( + .I0(plm_des3_reg_skp_3_1[1]), + .I1(plm_des3_reg_data[12]), + .I2(plm_des3_reg_data[14]), + .O(plm_des3_reg_t1p_3_2[1]) + ); + defparam plm_des3_input_decoder_reg_com_4_0_a7_2_1_0_.INIT = 8'h20; + LUT3 plm_des3_input_decoder_reg_com_4_0_a7_2_1_0_ ( + .I0(plm_des3_reg_data[4]), + .I1(plm_des3_reg_nitbl[0]), + .I2(plm_des3_reg_spesh[0]), + .O(plm_des3_reg_pad_4_5_1[0]) + ); + defparam plm_des3_input_decoder_reg_t2n_4_0_a7_2_0_0_.INIT = 16'h0400; + LUT4 plm_des3_input_decoder_reg_t2n_4_0_a7_2_0_0_ ( + .I0(plm_des3_reg_data[0]), + .I1(plm_des3_reg_data[1]), + .I2(plm_des3_reg_data[2]), + .I3(plm_des3_reg_data[3]), + .O(plm_des3_reg_t2n_4_2_0[0]) + ); + defparam plm_des3_input_decoder_reg_t2p_4_0_a7_2_0_.INIT = 8'h20; + LUT3 plm_des3_input_decoder_reg_t2p_4_0_a7_2_0_ ( + .I0(plm_des3_reg_skp_4_1[0]), + .I1(plm_des3_reg_data[4]), + .I2(plm_des3_reg_data[6]), + .O(plm_des3_reg_t2p_4_2[0]) + ); + defparam plm_des3_input_decoder_reg_skp_3_0_a7_1_0_1_.INIT = 8'h20; + LUT3 plm_des3_input_decoder_reg_skp_3_0_a7_1_0_1_ ( + .I0(plm_des3_reg_data[12]), + .I1(plm_des3_reg_nitbl[1]), + .I2(plm_des3_reg_spesh[1]), + .O(plm_des3_reg_skp_3_1_0[1]) + ); + defparam plm_des3_two_adv2_1_8_.INIT = 8'h96; + LUT3 plm_des3_two_adv2_1_8_ ( + .I0(plm_des3_reg_lfsr_two_4__660), + .I1(plm_des3_reg_lfsr_two_5__1047), + .I2(plm_des3_reg_lfsr_two_8__1044), + .O(plm_des3_two_adv2_1_8__1026) + ); + defparam plm_des3_input_decoder_reg_t1p_3_0_a7_0_1_.INIT = 16'h0400; + LUT4 plm_des3_input_decoder_reg_t1p_3_0_a7_0_1_ ( + .I0(plm_des3_reg_data[8]), + .I1(plm_des3_reg_data[9]), + .I2(plm_des3_reg_data[10]), + .I3(plm_des3_reg_data[11]), + .O(plm_des3_reg_t1p_3_0_a7_0[1]) + ); + defparam plm_des3_input_decoder_reg_t2p_4_0_a7_0_0_.INIT = 16'h0020; + LUT4 plm_des3_input_decoder_reg_t2p_4_0_a7_0_0_ ( + .I0(plm_des3_reg_data[0]), + .I1(plm_des3_reg_data[1]), + .I2(plm_des3_reg_data[2]), + .I3(plm_des3_reg_data[3]), + .O(plm_des3_reg_t2p_4_0_a7_0[0]) + ); + defparam plm_des3_input_decoder_reg_t1n_4_0_a7_0_0_.INIT = 16'h2000; + LUT4 plm_des3_input_decoder_reg_t1n_4_0_a7_0_0_ ( + .I0(plm_des3_reg_data[0]), + .I1(plm_des3_reg_data[1]), + .I2(plm_des3_reg_data[4]), + .I3(plm_des3_reg_data[5]), + .O(plm_des3_reg_t1n_4_0_a7_0[0]) + ); + defparam plm_des3_input_decoder_reg_t2n_3_0_a7_0_1_.INIT = 16'h4000; + LUT4 plm_des3_input_decoder_reg_t2n_3_0_a7_0_1_ ( + .I0(plm_des3_reg_data[10]), + .I1(plm_des3_reg_data[11]), + .I2(plm_des3_reg_data[12]), + .I3(plm_des3_reg_data[13]), + .O(plm_des3_reg_t2n_3_0_a7_0[1]) + ); + defparam plm_des3_input_decoder_reg_pad_3_0_a7_0_1_.INIT = 16'h0080; + LUT4 plm_des3_input_decoder_reg_pad_3_0_a7_0_1_ ( + .I0(plm_des3_reg_data[8]), + .I1(plm_des3_reg_data[9]), + .I2(plm_des3_reg_data[10]), + .I3(plm_des3_reg_data[11]), + .O(plm_des3_reg_pad_3_0_a7_0[1]) + ); + defparam plm_des3_input_decoder_reg_pad_4_0_a7_0_0_.INIT = 16'h0080; + LUT4 plm_des3_input_decoder_reg_pad_4_0_a7_0_0_ ( + .I0(plm_des3_reg_data[0]), + .I1(plm_des3_reg_data[1]), + .I2(plm_des3_reg_data[2]), + .I3(plm_des3_reg_data[3]), + .O(plm_des3_reg_pad_4_0_a7_0[0]) + ); + defparam plm_des3_input_decoder_reg_edg_3_0_a7_1_0_0_1_.INIT = 16'h8000; + LUT4 plm_des3_input_decoder_reg_edg_3_0_a7_1_0_0_1_ ( + .I0(plm_des3_reg_data[10]), + .I1(plm_des3_reg_data[11]), + .I2(plm_des3_reg_data[14]), + .I3(plm_des3_reg_data[15]), + .O(plm_des3_reg_edg_3_0_a7_1_0_0[1]) + ); + defparam plm_des3_input_decoder_reg_edg_4_0_a7_1_0_0_0_.INIT = 16'h8000; + LUT4 plm_des3_input_decoder_reg_edg_4_0_a7_1_0_0_0_ ( + .I0(plm_des3_reg_data[2]), + .I1(plm_des3_reg_data[3]), + .I2(plm_des3_reg_data[6]), + .I3(plm_des3_reg_data[7]), + .O(plm_des3_reg_edg_4_0_a7_1_0_0[0]) + ); + defparam plm_des3_lfsrs_reg_lfsr_two_12_iv_i_0_a2_15_.INIT = 4'h4; + LUT2_L plm_des3_lfsrs_reg_lfsr_two_12_iv_i_0_a2_15_ ( + .I0(plm_des3_reg_lfsr_two_12_iv_0_0_o4_0[9]), + .I1(plm_des3_one_adv2[15]), + .LO(plm_des3_reg_lfsr_two_12_iv_i_0_a2_0[15]) + ); + defparam plm_des3_lfsrs_reg_lfsr_two_12_iv_i_0_a2_0_13_.INIT = 16'h8228; + LUT4 plm_des3_lfsrs_reg_lfsr_two_12_iv_i_0_a2_0_13_ ( + .I0(plm_des3_reg_lfsr_two_12_iv_0_0_a4_1_0[9]), + .I1(plm_des3_reg_lfsr_two_8__1044), + .I2(plm_des3_reg_lfsr_two_13__527), + .I3(plm_des3_two_adv2_1_14__1029), + .O(plm_des3_reg_lfsr_two_12_iv_i_0_a2_0_0_13_) + ); + defparam plm_des3_lfsrs_reg_lfsr_two_12_iv_i_0_a2_0_11_.INIT = 16'h8228; + LUT4_L plm_des3_lfsrs_reg_lfsr_two_12_iv_i_0_a2_0_11_ ( + .I0(plm_des3_reg_lfsr_two_12_iv_0_0_a4_1_0[9]), + .I1(plm_des3_reg_lfsr_two_6__1046), + .I2(plm_des3_reg_lfsr_two_11__526), + .I3(plm_des3_two_adv2_1_12__1020), + .LO(plm_des3_reg_lfsr_two_12_iv_i_0_a2_0_0_11_) + ); + defparam plm_des3_lfsrs_reg_lfsr_two_12_iv_i_0_a2_0_2_.INIT = 16'h8448; + LUT4 plm_des3_lfsrs_reg_lfsr_two_12_iv_i_0_a2_0_2_ ( + .I0(N_49083_i_0), + .I1(plm_des3_reg_lfsr_two_12_iv_0_0_a4_1_0[9]), + .I2(plm_des3_reg_lfsr_two_14__628), + .I3(plm_des3_reg_lfsr_two_15__528), + .O(plm_des3_reg_lfsr_two_12_iv_i_0_a2_0_0_2_) + ); + defparam plm_des3_lfsrs_reg_lfsr_two_12_iv_i_0_a2_0_1_.INIT = 16'h8228; + LUT4 plm_des3_lfsrs_reg_lfsr_two_12_iv_i_0_a2_0_1_ ( + .I0(plm_des3_reg_lfsr_two_12_iv_0_0_a4_1_0[9]), + .I1(plm_des3_reg_lfsr_two_1__1048), + .I2(plm_des3_reg_lfsr_two_14__628), + .I3(plm_des3_two_adv2_1_1__1021), + .O(plm_des3_reg_lfsr_two_12_iv_i_0_a2_0_0_1_) + ); + defparam plm_des3_lfsrs_reg_lfsr_two_12_iv_i_0_a2_0_0_.INIT = 16'h8228; + LUT4 plm_des3_lfsrs_reg_lfsr_two_12_iv_i_0_a2_0_0_ ( + .I0(plm_des3_reg_lfsr_two_12_iv_0_0_a4_1_0[9]), + .I1(plm_des3_reg_lfsr_two_0__525), + .I2(plm_des3_reg_lfsr_two_11__526), + .I3(plm_des3_two_adv2_1_1__1021), + .O(plm_des3_reg_lfsr_two_12_iv_i_0_a2_0_0_0_) + ); + defparam plm_des3_lfsrs_reg_lfsr_one_12_iv_i_0_a2_0_12_.INIT = 4'h8; + LUT2_L plm_des3_lfsrs_reg_lfsr_one_12_iv_i_0_a2_0_12_ ( + .I0(plm_des3_reg_lfsr_two_12_iv_0_0_a4_1_0[9]), + .I1(plm_des3_one_adv2[12]), + .LO(plm_des3_reg_lfsr_one_12_iv_i_0_a2_0_0_12_) + ); + defparam plm_des3_lfsrs_reg_lfsr_one_12_iv_i_0_0_a2_0_10_.INIT = 4'h8; + LUT2_L plm_des3_lfsrs_reg_lfsr_one_12_iv_i_0_0_a2_0_10_ ( + .I0(plm_des3_reg_lfsr_two_12_iv_0_0_a4_1_0[9]), + .I1(plm_des3_one_adv2[10]), + .LO(plm_des3_reg_lfsr_one_12_iv_i_0_0_a2_0_1_10_) + ); + defparam plm_des3_lfsrs_reg_lfsr_one_12_iv_i_0_a2_3_.INIT = 4'h4; + LUT2 plm_des3_lfsrs_reg_lfsr_one_12_iv_i_0_a2_3_ ( + .I0(plm_des3_reg_lfsr_two_12_iv_0_0_o4_0[9]), + .I1(plm_des3_reg_lfsr_two_3__626), + .O(plm_des3_reg_lfsr_one_12_iv_i_0_a2_0[3]) + ); + defparam plm_des3_lfsrs_reg_lfsr_one_12_0_iv_i_i_x4_0_.INIT = 4'h6; + LUT2 plm_des3_lfsrs_reg_lfsr_one_12_0_iv_i_i_x4_0_ ( + .I0(G_414_621), + .I1(plm_des3_reg_lfsr_one_13__517), + .O(plm_des3_N_49080_i_0) + ); + defparam plm_des3_descram_N_86083_i.INIT = 8'h57; + LUT3 plm_des3_descram_N_86083_i ( + .I0(plm_des3_m1_0_a2_0_a3_0_a2_0_a2_2), + .I1(plm_reg_com_1[1]), + .I2(plm_des3_reg_skp[1]), + .O(plm_des3_N_86083_i) + ); + defparam plm_des3_two_adv2_7_.INIT = 16'h6996; + LUT4 plm_des3_two_adv2_7_ ( + .I0(N_49083_i_0), + .I1(N_49107_i_0), + .I2(plm_des3_reg_lfsr_two_3__626), + .I3(plm_des3_reg_lfsr_two_7__1045), + .O(plm_des3_two_adv2_7__1032) + ); + defparam plm_des3_one_adv2_6_.INIT = 16'h6996; + LUT4 plm_des3_one_adv2_6_ ( + .I0(N_49118_i_0), + .I1(plm_des3_one_adv2_1_6__1022), + .I2(plm_des3_reg_lfsr_one_2__1041), + .I3(plm_des3_reg_lfsr_one_6__1038), + .O(plm_des3_one_adv2[6]) + ); + defparam plm_des3_one_adv2_7_.INIT = 16'h6996; + LUT4 plm_des3_one_adv2_7_ ( + .I0(G_336_518), + .I1(plm_des3_reg_lfsr_one_2__1041), + .I2(plm_des3_reg_lfsr_one_4__1040), + .I3(plm_des3_reg_lfsr_one_7__1037), + .O(plm_des3_one_adv2[7]) + ); + defparam plm_des3_one_adv2_9_.INIT = 16'h6996; + LUT4 plm_des3_one_adv2_9_ ( + .I0(plm_des3_one_adv2_1_9__1023), + .I1(plm_des3_reg_lfsr_one_6__1038), + .I2(plm_des3_reg_lfsr_one_9__1035), + .I3(plm_des3_reg_lfsr_one_15__514), + .O(plm_des3_one_adv2[9]) + ); + defparam plm_des3_input_decoder_reg_com_4_0_a7_2_0_.INIT = 4'h8; + LUT2 plm_des3_input_decoder_reg_com_4_0_a7_2_0_ ( + .I0(plm_des3_reg_pad_4_5_1[0]), + .I1(plm_des3_reg_data[5]), + .O(plm_des3_reg_pad_4_5[0]) + ); + defparam plm_des3_input_decoder_reg_com_3_0_a7_2_1_.INIT = 4'h8; + LUT2 plm_des3_input_decoder_reg_com_3_0_a7_2_1_ ( + .I0(plm_des3_reg_skp_3_1_0[1]), + .I1(plm_des3_reg_data[13]), + .O(plm_des3_reg_pad_3_5[1]) + ); + defparam plm_des3_two_adv2_6_.INIT = 8'h69; + LUT3 plm_des3_two_adv2_6_ ( + .I0(N_49072_i_0), + .I1(plm_des3_reg_lfsr_two_6__1046), + .I2(plm_des3_two_adv2_1_6__1027), + .O(plm_des3_two_adv2_6__1033) + ); + defparam plm_des3_one_adv2_8_.INIT = 8'h96; + LUT3 plm_des3_one_adv2_8_ ( + .I0(N_49118_i_0), + .I1(plm_des3_one_adv2_1_9__1023), + .I2(plm_des3_reg_lfsr_one_8__1036), + .O(plm_des3_one_adv2[8]) + ); + defparam plm_des3_one_adv2_5_.INIT = 8'h96; + LUT3 plm_des3_one_adv2_5_ ( + .I0(G_335_515), + .I1(plm_des3_one_adv2_1_5__1024), + .I2(plm_des3_reg_lfsr_one_5__1039), + .O(plm_des3_one_adv2[5]) + ); + defparam plm_des3_one_adv2_4_.INIT = 8'h96; + LUT3 plm_des3_one_adv2_4_ ( + .I0(G_335_515), + .I1(plm_des3_reg_lfsr_one_4__1040), + .I2(plm_des3_reg_lfsr_one_14__657), + .O(plm_des3_one_adv2[4]) + ); + defparam plm_des3_input_decoder_reg_bad_4_i_1_0_.INIT = 16'h54FF; + LUT4_L plm_des3_input_decoder_reg_bad_4_i_1_0_ ( + .I0(plm_des3_reg_bad_4_i_a7_2_0[0]), + .I1(plm_des3_reg_data[2]), + .I2(plm_des3_reg_data[3]), + .I3(plm_des3_reg_spesh[0]), + .LO(plm_des3_reg_bad_4_i_1[0]) + ); + defparam plm_des3_input_decoder_reg_bad_3_i_1_1_.INIT = 16'h54FF; + LUT4_L plm_des3_input_decoder_reg_bad_3_i_1_1_ ( + .I0(plm_des3_reg_bad_3_i_a7_2_0[1]), + .I1(plm_des3_reg_data[10]), + .I2(plm_des3_reg_data[11]), + .I3(plm_des3_reg_spesh[1]), + .LO(plm_des3_reg_bad_3_i_1[1]) + ); + defparam plm_des3_lfsrs_reg_lfsr_two_12_iv_0_0_a2_0_9_.INIT = 16'h4884; + LUT4 plm_des3_lfsrs_reg_lfsr_two_12_iv_0_0_a2_0_9_ ( + .I0(N_49107_i_0), + .I1(plm_des3_reg_lfsr_two_12_iv_0_0_a4_1_0[9]), + .I2(plm_des3_reg_lfsr_two_9__1043), + .I3(plm_des3_two_adv2_1_10__1025), + .O(plm_des3_reg_lfsr_two_12_iv_0_0_a2_0_9_) + ); + defparam plm_des3_lfsrs_reg_lfsr_two_12_iv_0_0_a2_0_8_.INIT = 16'h2882; + LUT4 plm_des3_lfsrs_reg_lfsr_two_12_iv_0_0_a2_0_8_ ( + .I0(plm_des3_reg_lfsr_two_12_iv_0_0_a4_1_0[9]), + .I1(plm_des3_reg_lfsr_two_3__626), + .I2(plm_des3_reg_lfsr_two_14__628), + .I3(plm_des3_two_adv2_1_8__1026), + .O(plm_des3_reg_lfsr_two_12_iv_0_0_a2_0_8_) + ); + defparam plm_des3_lfsrs_reg_lfsr_two_12_iv_0_0_a2_0_5_.INIT = 16'h4884; + LUT4 plm_des3_lfsrs_reg_lfsr_two_12_iv_0_0_a2_0_5_ ( + .I0(G_339_529), + .I1(plm_des3_reg_lfsr_two_12_iv_0_0_a4_1_0[9]), + .I2(plm_des3_reg_lfsr_two_5__1047), + .I3(plm_des3_two_adv2_1_6__1027), + .O(plm_des3_reg_lfsr_two_12_iv_0_0_a2_0_5_) + ); + defparam plm_des3_lfsrs_reg_lfsr_two_12_iv_0_0_0_a2_3_.INIT = 8'h60; + LUT3 plm_des3_lfsrs_reg_lfsr_two_12_iv_0_0_0_a2_3_ ( + .I0(G_339_529), + .I1(N_49072_i_0), + .I2(plm_des3_reg_lfsr_two_12_iv_0_0_a4_1_0[9]), + .O(plm_des3_reg_lfsr_two_12_iv_0_0_0_a2[3]) + ); + defparam plm_des3_lfsrs_reg_lfsr_two_12_iv_i_0_a2_0_4_.INIT = 16'h9060; + LUT4 plm_des3_lfsrs_reg_lfsr_two_12_iv_i_0_a2_0_4_ ( + .I0(N_49085_i_0), + .I1(N_49107_i_0), + .I2(plm_des3_reg_lfsr_two_12_iv_0_0_a4_1_0[9]), + .I3(plm_des3_two_adv2_0[4]), + .O(plm_des3_reg_lfsr_two_12_iv_i_0_a2_0_0_4_) + ); + defparam plm_des3_lfsrs_reg_lfsr_one_12_iv_i_0_0_a2_0_9_.INIT = 4'h8; + LUT2_L plm_des3_lfsrs_reg_lfsr_one_12_iv_i_0_0_a2_0_9_ ( + .I0(plm_des3_reg_lfsr_two_12_iv_0_0_a4_1_0[9]), + .I1(plm_des3_one_adv2[9]), + .LO(plm_des3_reg_lfsr_one_12_iv_i_0_0_a2_0_1_9_) + ); + defparam plm_des3_lfsrs_reg_lfsr_one_12_iv_i_0_0_a2_0_8_.INIT = 4'h8; + LUT2_L plm_des3_lfsrs_reg_lfsr_one_12_iv_i_0_0_a2_0_8_ ( + .I0(plm_des3_reg_lfsr_two_12_iv_0_0_a4_1_0[9]), + .I1(plm_des3_one_adv2[8]), + .LO(plm_des3_reg_lfsr_one_12_iv_i_0_0_a2_0_1_8_) + ); + defparam plm_des3_lfsrs_reg_lfsr_one_12_iv_i_0_a2_0_7_.INIT = 4'h8; + LUT2_L plm_des3_lfsrs_reg_lfsr_one_12_iv_i_0_a2_0_7_ ( + .I0(plm_des3_reg_lfsr_two_12_iv_0_0_a4_1_0[9]), + .I1(plm_des3_one_adv2[7]), + .LO(plm_des3_reg_lfsr_one_12_iv_i_0_a2_0_0_7_) + ); + defparam plm_des3_lfsrs_reg_lfsr_one_12_iv_i_0_0_a2_0_6_.INIT = 4'h8; + LUT2_L plm_des3_lfsrs_reg_lfsr_one_12_iv_i_0_0_a2_0_6_ ( + .I0(plm_des3_reg_lfsr_two_12_iv_0_0_a4_1_0[9]), + .I1(plm_des3_one_adv2[6]), + .LO(plm_des3_reg_lfsr_one_12_iv_i_0_0_a2_0_1_6_) + ); + defparam plm_des3_lfsrs_reg_lfsr_one_12_iv_i_0_0_a2_0_5_.INIT = 4'h8; + LUT2_L plm_des3_lfsrs_reg_lfsr_one_12_iv_i_0_0_a2_0_5_ ( + .I0(plm_des3_reg_lfsr_two_12_iv_0_0_a4_1_0[9]), + .I1(plm_des3_one_adv2[5]), + .LO(plm_des3_reg_lfsr_one_12_iv_i_0_0_a2_0_1_5_) + ); + defparam plm_des3_descram_reg_rx_des_dat_14_0_am_7_.INIT = 8'h65; + LUT3 plm_des3_descram_reg_rx_des_dat_14_0_am_7_ ( + .I0(plm_des3_reg_dat[7]), + .I1(plm_des3_reg_lfsr_one_8__1036), + .I2(plm_des3_reg_skp[1]), + .O(plm_des3_reg_rx_des_dat_14_0_am[7]) + ); + defparam plm_des3_descram_reg_rx_des_dat_14_0_bm_7_.INIT = 8'h6C; + LUT3 plm_des3_descram_reg_rx_des_dat_14_0_bm_7_ ( + .I0(plm_des3_m1_0_a2_0_a3_0_a2_0_a2_2), + .I1(plm_des3_reg_dat[7]), + .I2(plm_des3_reg_lfsr_two_8__1044), + .O(plm_des3_reg_rx_des_dat_14_0_bm[7]) + ); + MUXF5 plm_des3_descram_reg_rx_des_dat_14_0_7_ ( + .I0(plm_des3_reg_rx_des_dat_14_0_am[7]), + .I1(plm_des3_reg_rx_des_dat_14_0_bm[7]), + .O(plm_des3_reg_rx_des_dat_14[7]), + .S(plm_des3_N_86083_i) + ); + defparam plm_des3_descram_reg_rx_des_dat_14_0_am_6_.INIT = 8'h65; + LUT3 plm_des3_descram_reg_rx_des_dat_14_0_am_6_ ( + .I0(plm_des3_reg_dat[6]), + .I1(plm_des3_reg_lfsr_one_9__1035), + .I2(plm_des3_reg_skp[1]), + .O(plm_des3_reg_rx_des_dat_14_0_am[6]) + ); + defparam plm_des3_descram_reg_rx_des_dat_14_0_bm_6_.INIT = 8'h6C; + LUT3 plm_des3_descram_reg_rx_des_dat_14_0_bm_6_ ( + .I0(plm_des3_m1_0_a2_0_a3_0_a2_0_a2_2), + .I1(plm_des3_reg_dat[6]), + .I2(plm_des3_reg_lfsr_two_9__1043), + .O(plm_des3_reg_rx_des_dat_14_0_bm[6]) + ); + MUXF5 plm_des3_descram_reg_rx_des_dat_14_0_6_ ( + .I0(plm_des3_reg_rx_des_dat_14_0_am[6]), + .I1(plm_des3_reg_rx_des_dat_14_0_bm[6]), + .O(plm_des3_reg_rx_des_dat_14[6]), + .S(plm_des3_N_86083_i) + ); + defparam plm_des3_descram_reg_rx_des_dat_14_0_am_5_.INIT = 8'h65; + LUT3 plm_des3_descram_reg_rx_des_dat_14_0_am_5_ ( + .I0(plm_des3_reg_dat[5]), + .I1(plm_des3_reg_lfsr_one_10__1034), + .I2(plm_des3_reg_skp[1]), + .O(plm_des3_reg_rx_des_dat_14_0_am[5]) + ); + defparam plm_des3_descram_reg_rx_des_dat_14_0_bm_5_.INIT = 8'h6C; + LUT3 plm_des3_descram_reg_rx_des_dat_14_0_bm_5_ ( + .I0(plm_des3_m1_0_a2_0_a3_0_a2_0_a2_2), + .I1(plm_des3_reg_dat[5]), + .I2(plm_des3_reg_lfsr_two_10__1042), + .O(plm_des3_reg_rx_des_dat_14_0_bm[5]) + ); + MUXF5 plm_des3_descram_reg_rx_des_dat_14_0_5_ ( + .I0(plm_des3_reg_rx_des_dat_14_0_am[5]), + .I1(plm_des3_reg_rx_des_dat_14_0_bm[5]), + .O(plm_des3_reg_rx_des_dat_14[5]), + .S(plm_des3_N_86083_i) + ); + defparam plm_des3_descram_reg_rx_des_dat_14_0_am_4_.INIT = 8'h65; + LUT3 plm_des3_descram_reg_rx_des_dat_14_0_am_4_ ( + .I0(plm_des3_reg_dat[4]), + .I1(plm_des3_reg_lfsr_one_11__636), + .I2(plm_des3_reg_skp[1]), + .O(plm_des3_reg_rx_des_dat_14_0_am[4]) + ); + defparam plm_des3_descram_reg_rx_des_dat_14_0_bm_4_.INIT = 8'h6C; + LUT3 plm_des3_descram_reg_rx_des_dat_14_0_bm_4_ ( + .I0(plm_des3_m1_0_a2_0_a3_0_a2_0_a2_2), + .I1(plm_des3_reg_dat[4]), + .I2(plm_des3_reg_lfsr_two_11__526), + .O(plm_des3_reg_rx_des_dat_14_0_bm[4]) + ); + MUXF5 plm_des3_descram_reg_rx_des_dat_14_0_4_ ( + .I0(plm_des3_reg_rx_des_dat_14_0_am[4]), + .I1(plm_des3_reg_rx_des_dat_14_0_bm[4]), + .O(plm_des3_reg_rx_des_dat_14[4]), + .S(plm_des3_N_86083_i) + ); + defparam plm_des3_descram_reg_rx_des_dat_14_0_am_3_.INIT = 8'h65; + LUT3 plm_des3_descram_reg_rx_des_dat_14_0_am_3_ ( + .I0(plm_des3_reg_dat[3]), + .I1(plm_des3_reg_lfsr_one_12__620), + .I2(plm_des3_reg_skp[1]), + .O(plm_des3_reg_rx_des_dat_14_0_am[3]) + ); + defparam plm_des3_descram_reg_rx_des_dat_14_0_bm_3_.INIT = 8'h6C; + LUT3 plm_des3_descram_reg_rx_des_dat_14_0_bm_3_ ( + .I0(plm_des3_m1_0_a2_0_a3_0_a2_0_a2_2), + .I1(plm_des3_reg_dat[3]), + .I2(plm_des3_reg_lfsr_two_12__627), + .O(plm_des3_reg_rx_des_dat_14_0_bm[3]) + ); + MUXF5 plm_des3_descram_reg_rx_des_dat_14_0_3_ ( + .I0(plm_des3_reg_rx_des_dat_14_0_am[3]), + .I1(plm_des3_reg_rx_des_dat_14_0_bm[3]), + .O(plm_des3_reg_rx_des_dat_14[3]), + .S(plm_des3_N_86083_i) + ); + defparam plm_des3_descram_reg_rx_des_dat_14_0_am_2_.INIT = 8'h65; + LUT3 plm_des3_descram_reg_rx_des_dat_14_0_am_2_ ( + .I0(plm_des3_reg_dat[2]), + .I1(plm_des3_reg_lfsr_one_13__517), + .I2(plm_des3_reg_skp[1]), + .O(plm_des3_reg_rx_des_dat_14_0_am[2]) + ); + defparam plm_des3_descram_reg_rx_des_dat_14_0_bm_2_.INIT = 8'h6C; + LUT3 plm_des3_descram_reg_rx_des_dat_14_0_bm_2_ ( + .I0(plm_des3_m1_0_a2_0_a3_0_a2_0_a2_2), + .I1(plm_des3_reg_dat[2]), + .I2(plm_des3_reg_lfsr_two_13__527), + .O(plm_des3_reg_rx_des_dat_14_0_bm[2]) + ); + MUXF5 plm_des3_descram_reg_rx_des_dat_14_0_2_ ( + .I0(plm_des3_reg_rx_des_dat_14_0_am[2]), + .I1(plm_des3_reg_rx_des_dat_14_0_bm[2]), + .O(plm_des3_reg_rx_des_dat_14[2]), + .S(plm_des3_N_86083_i) + ); + defparam plm_des3_descram_reg_rx_des_dat_14_0_am_1_.INIT = 8'h65; + LUT3 plm_des3_descram_reg_rx_des_dat_14_0_am_1_ ( + .I0(plm_des3_reg_dat[1]), + .I1(plm_des3_reg_lfsr_one_14__657), + .I2(plm_des3_reg_skp[1]), + .O(plm_des3_reg_rx_des_dat_14_0_am[1]) + ); + defparam plm_des3_descram_reg_rx_des_dat_14_0_bm_1_.INIT = 8'h6C; + LUT3 plm_des3_descram_reg_rx_des_dat_14_0_bm_1_ ( + .I0(plm_des3_m1_0_a2_0_a3_0_a2_0_a2_2), + .I1(plm_des3_reg_dat[1]), + .I2(plm_des3_reg_lfsr_two_14__628), + .O(plm_des3_reg_rx_des_dat_14_0_bm[1]) + ); + MUXF5 plm_des3_descram_reg_rx_des_dat_14_0_1_ ( + .I0(plm_des3_reg_rx_des_dat_14_0_am[1]), + .I1(plm_des3_reg_rx_des_dat_14_0_bm[1]), + .O(plm_des3_reg_rx_des_dat_14[1]), + .S(plm_des3_N_86083_i) + ); + defparam plm_des3_descram_reg_rx_des_dat_14_0_am_0_.INIT = 8'h65; + LUT3 plm_des3_descram_reg_rx_des_dat_14_0_am_0_ ( + .I0(plm_des3_reg_dat[0]), + .I1(plm_des3_reg_lfsr_one_15__514), + .I2(plm_des3_reg_skp[1]), + .O(plm_des3_reg_rx_des_dat_14_0_am[0]) + ); + defparam plm_des3_descram_reg_rx_des_dat_14_0_bm_0_.INIT = 8'h6C; + LUT3 plm_des3_descram_reg_rx_des_dat_14_0_bm_0_ ( + .I0(plm_des3_m1_0_a2_0_a3_0_a2_0_a2_2), + .I1(plm_des3_reg_dat[0]), + .I2(plm_des3_reg_lfsr_two_15__528), + .O(plm_des3_reg_rx_des_dat_14_0_bm[0]) + ); + MUXF5 plm_des3_descram_reg_rx_des_dat_14_0_0_ ( + .I0(plm_des3_reg_rx_des_dat_14_0_am[0]), + .I1(plm_des3_reg_rx_des_dat_14_0_bm[0]), + .O(plm_des3_reg_rx_des_dat_14[0]), + .S(plm_des3_N_86083_i) + ); + defparam plm_des3_one_adv2_3_.INIT = 8'h96; + LUT3 plm_des3_one_adv2_3_ ( + .I0(G_336_518), + .I1(G_414_621), + .I2(plm_des3_reg_lfsr_one_14__657), + .O(plm_des3_one_adv2[3]) + ); + defparam plm_des3_lfsrs_reg_lfsr_two_12_iv_i_0_0_14_.INIT = 8'h8A; + LUT3_L plm_des3_lfsrs_reg_lfsr_two_12_iv_i_0_0_14_ ( + .I0(plm_des3_N_49062_i), + .I1(plm_des3_reg_lfsr_two_12_iv_0_0_o4_0[9]), + .I2(plm_des3_one_adv2[14]), + .LO(plm_des3_reg_lfsr_two_12_iv_i_0_0[14]) + ); + defparam plm_des3_input_decoder_reg_bad_4_i_2_0_.INIT = 16'h080A; + LUT4_L plm_des3_input_decoder_reg_bad_4_i_2_0_ ( + .I0(plm_des3_reg_bad_4_i_1[0]), + .I1(plm_des3_reg_data[4]), + .I2(plm_des3_reg_nitbl[0]), + .I3(plm_des3_reg_spesh[0]), + .LO(plm_des3_reg_bad_4_i_2[0]) + ); + defparam plm_des3_input_decoder_reg_bad_3_i_2_1_.INIT = 16'h080A; + LUT4_L plm_des3_input_decoder_reg_bad_3_i_2_1_ ( + .I0(plm_des3_reg_bad_3_i_1[1]), + .I1(plm_des3_reg_data[12]), + .I2(plm_des3_reg_nitbl[1]), + .I3(plm_des3_reg_spesh[1]), + .LO(plm_des3_reg_bad_3_i_2[1]) + ); + defparam plm_des3_input_decoder_N_85322_i.INIT = 16'h7F0F; + LUT4_L plm_des3_input_decoder_N_85322_i ( + .I0(plm_des3_N_14094_i), + .I1(plm_des3_N_14095_i), + .I2(plm_des3_reg_bad_3_i_2[1]), + .I3(plm_des3_reg_spesh[1]), + .LO(plm_des3_N_85322_i) + ); + defparam plm_des3_input_decoder_N_85323_i.INIT = 16'h7F0F; + LUT4_L plm_des3_input_decoder_N_85323_i ( + .I0(plm_des3_N_14057_i), + .I1(plm_des3_N_14058_i), + .I2(plm_des3_reg_bad_4_i_2[0]), + .I3(plm_des3_reg_spesh[0]), + .LO(plm_des3_N_85323_i) + ); + defparam plm_des3_descram_N_49228_i_0_i.INIT = 8'h6C; + LUT3_L plm_des3_descram_N_49228_i_0_i ( + .I0(plm_des3_N_49064_i), + .I1(plm_des3_reg_dat[15]), + .I2(plm_des3_reg_lfsr_one_8__1036), + .LO(plm_des3_N_49228_i_0_i) + ); + defparam plm_des3_descram_N_49226_i_0_i.INIT = 8'h6C; + LUT3_L plm_des3_descram_N_49226_i_0_i ( + .I0(plm_des3_N_49064_i), + .I1(plm_des3_reg_dat[14]), + .I2(plm_des3_reg_lfsr_one_9__1035), + .LO(plm_des3_N_49226_i_0_i) + ); + defparam plm_des3_descram_N_49224_i_0_i.INIT = 8'h6C; + LUT3_L plm_des3_descram_N_49224_i_0_i ( + .I0(plm_des3_N_49064_i), + .I1(plm_des3_reg_dat[13]), + .I2(plm_des3_reg_lfsr_one_10__1034), + .LO(plm_des3_N_49224_i_0_i) + ); + defparam plm_des3_descram_N_49222_i_0_i.INIT = 8'h6C; + LUT3_L plm_des3_descram_N_49222_i_0_i ( + .I0(plm_des3_N_49064_i), + .I1(plm_des3_reg_dat[12]), + .I2(plm_des3_reg_lfsr_one_11__636), + .LO(plm_des3_N_49222_i_0_i) + ); + defparam plm_des3_descram_N_49220_i_0_i.INIT = 8'h6C; + LUT3_L plm_des3_descram_N_49220_i_0_i ( + .I0(plm_des3_N_49064_i), + .I1(plm_des3_reg_dat[11]), + .I2(plm_des3_reg_lfsr_one_12__620), + .LO(plm_des3_N_49220_i_0_i) + ); + defparam plm_des3_descram_N_49218_i_0_i.INIT = 8'h6C; + LUT3_L plm_des3_descram_N_49218_i_0_i ( + .I0(plm_des3_N_49064_i), + .I1(plm_des3_reg_dat[10]), + .I2(plm_des3_reg_lfsr_one_13__517), + .LO(plm_des3_N_49218_i_0_i) + ); + defparam plm_des3_descram_N_49216_i_0_i.INIT = 8'h6C; + LUT3_L plm_des3_descram_N_49216_i_0_i ( + .I0(plm_des3_N_49064_i), + .I1(plm_des3_reg_dat[9]), + .I2(plm_des3_reg_lfsr_one_14__657), + .LO(plm_des3_N_49216_i_0_i) + ); + defparam plm_des3_descram_N_49214_i_0_i.INIT = 8'h6C; + LUT3_L plm_des3_descram_N_49214_i_0_i ( + .I0(plm_des3_N_49064_i), + .I1(plm_des3_reg_dat[8]), + .I2(plm_des3_reg_lfsr_one_15__514), + .LO(plm_des3_N_49214_i_0_i) + ); + defparam plm_des3_input_decoder_reg_pad_4_0_a7_0_.INIT = 16'h8000; + LUT4_L plm_des3_input_decoder_reg_pad_4_0_a7_0_ ( + .I0(plm_des3_reg_pad_4_0_a7_0[0]), + .I1(plm_des3_reg_pad_4_5[0]), + .I2(plm_des3_reg_data[6]), + .I3(plm_des3_reg_data[7]), + .LO(plm_reg_pad_4_1[0]) + ); + defparam plm_des3_input_decoder_reg_edg_3_0_a7_1_.INIT = 16'h0080; + LUT4_L plm_des3_input_decoder_reg_edg_3_0_a7_1_ ( + .I0(plm_des3_reg_edg_3_0_a7_1_0_0[1]), + .I1(plm_des3_reg_pad_3_5[1]), + .I2(plm_des3_reg_data[8]), + .I3(plm_des3_reg_data[9]), + .LO(plm_des3_reg_edg_3[1]) + ); + defparam plm_des3_input_decoder_reg_edg_4_0_a7_0_.INIT = 16'h0080; + LUT4_L plm_des3_input_decoder_reg_edg_4_0_a7_0_ ( + .I0(plm_des3_reg_edg_4_0_a7_1_0_0[0]), + .I1(plm_des3_reg_pad_4_5[0]), + .I2(plm_des3_reg_data[0]), + .I3(plm_des3_reg_data[1]), + .LO(plm_des3_reg_edg_4[0]) + ); + defparam plm_des3_input_decoder_reg_edb_3_0_a7_1_.INIT = 16'h0800; + LUT4_L plm_des3_input_decoder_reg_edb_3_0_a7_1_ ( + .I0(plm_des3_reg_edg_3_0_a7_1_0_0[1]), + .I1(plm_des3_reg_pad_3_5[1]), + .I2(plm_des3_reg_data[8]), + .I3(plm_des3_reg_data[9]), + .LO(plm_des3_reg_edb_3[1]) + ); + defparam plm_des3_input_decoder_reg_edb_4_0_a7_0_.INIT = 16'h0800; + LUT4_L plm_des3_input_decoder_reg_edb_4_0_a7_0_ ( + .I0(plm_des3_reg_edg_4_0_a7_1_0_0[0]), + .I1(plm_des3_reg_pad_4_5[0]), + .I2(plm_des3_reg_data[0]), + .I3(plm_des3_reg_data[1]), + .LO(plm_des3_reg_edb_4[0]) + ); + defparam plm_des3_input_decoder_reg_com_3_0_a7_1_.INIT = 16'h0800; + LUT4_L plm_des3_input_decoder_reg_com_3_0_a7_1_ ( + .I0(plm_des3_reg_pad_3_5[1]), + .I1(plm_des3_reg_skp_3_3[1]), + .I2(plm_des3_reg_data[14]), + .I3(plm_des3_reg_data[15]), + .LO(plm_des3_reg_com_3[1]) + ); + defparam plm_des3_input_decoder_reg_com_4_0_a7_0_.INIT = 16'h0800; + LUT4_L plm_des3_input_decoder_reg_com_4_0_a7_0_ ( + .I0(plm_des3_reg_pad_4_5[0]), + .I1(plm_des3_reg_skp_4_3[0]), + .I2(plm_des3_reg_data[6]), + .I3(plm_des3_reg_data[7]), + .LO(plm_des3_reg_com_4[0]) + ); + defparam plm_des3_input_decoder_reg_t2p_3_0_a7_1_.INIT = 8'h80; + LUT3_L plm_des3_input_decoder_reg_t2p_3_0_a7_1_ ( + .I0(plm_des3_reg_sym_3[1]), + .I1(plm_des3_reg_t1n_3_2[1]), + .I2(plm_des3_reg_t1p_3_2[1]), + .LO(plm_des3_reg_t2p_3[1]) + ); + defparam plm_des3_input_decoder_reg_t2p_4_0_a7_0_.INIT = 8'h80; + LUT3_L plm_des3_input_decoder_reg_t2p_4_0_a7_0_ ( + .I0(plm_des3_reg_sym_4[0]), + .I1(plm_des3_reg_t2p_4_0_a7_0[0]), + .I2(plm_des3_reg_t2p_4_2[0]), + .LO(plm_reg_t2p_4_2[0]) + ); + defparam plm_des3_input_decoder_reg_t2n_3_0_a7_1_.INIT = 16'h0800; + LUT4_L plm_des3_input_decoder_reg_t2n_3_0_a7_1_ ( + .I0(plm_des3_reg_t1n_3_1[1]), + .I1(plm_des3_reg_t2n_3_0_a7_0[1]), + .I2(plm_des3_reg_data[8]), + .I3(plm_des3_reg_data[9]), + .LO(plm_des3_reg_t2n_3[1]) + ); + defparam plm_des3_input_decoder_reg_t2n_4_0_a7_0_.INIT = 16'h8000; + LUT4_L plm_des3_input_decoder_reg_t2n_4_0_a7_0_ ( + .I0(plm_des3_reg_t2n_4_1_0[0]), + .I1(plm_des3_reg_t2n_4_2_0[0]), + .I2(plm_des3_reg_data[4]), + .I3(plm_des3_reg_data[5]), + .LO(plm_reg_t2n_4_2[0]) + ); + defparam plm_des3_input_decoder_reg_t1p_3_0_a7_1_.INIT = 8'h80; + LUT3_L plm_des3_input_decoder_reg_t1p_3_0_a7_1_ ( + .I0(plm_des3_reg_sym_3[1]), + .I1(plm_des3_reg_t1p_3_0_a7_0[1]), + .I2(plm_des3_reg_t1p_3_2[1]), + .LO(plm_des3_reg_t1p_3[1]) + ); + defparam plm_des3_input_decoder_reg_t1p_4_0_a7_0_.INIT = 8'h80; + LUT3_L plm_des3_input_decoder_reg_t1p_4_0_a7_0_ ( + .I0(plm_des3_reg_sym_4[0]), + .I1(plm_des3_reg_t2n_4_2_0[0]), + .I2(plm_des3_reg_t2p_4_2[0]), + .LO(plm_reg_t1p_4_2[0]) + ); + defparam plm_des3_input_decoder_reg_skp_3_0_a7_1_.INIT = 16'h0080; + LUT4_L plm_des3_input_decoder_reg_skp_3_0_a7_1_ ( + .I0(plm_des3_reg_skp_3_1[1]), + .I1(plm_des3_reg_skp_3_1_0[1]), + .I2(plm_des3_reg_skp_3_3[1]), + .I3(plm_des3_reg_data[14]), + .LO(plm_des3_reg_skp_3[1]) + ); + defparam plm_des3_input_decoder_reg_skp_4_0_a7_0_.INIT = 16'h0080; + LUT4_L plm_des3_input_decoder_reg_skp_4_0_a7_0_ ( + .I0(plm_des3_reg_pad_4_5_1[0]), + .I1(plm_des3_reg_skp_4_1[0]), + .I2(plm_des3_reg_skp_4_3[0]), + .I3(plm_des3_reg_data[6]), + .LO(plm_des3_reg_skp_4[0]) + ); + defparam plm_des3_input_decoder_reg_pad_3_0_a7_1_.INIT = 16'h8000; + LUT4_L plm_des3_input_decoder_reg_pad_3_0_a7_1_ ( + .I0(plm_des3_reg_pad_3_0_a7_0[1]), + .I1(plm_des3_reg_pad_3_5[1]), + .I2(plm_des3_reg_data[14]), + .I3(plm_des3_reg_data[15]), + .LO(plm_reg_pad_3_1[1]) + ); + defparam plm_des3_input_decoder_reg_t1n_4_0_a7_0_.INIT = 16'h0080; + LUT4_L plm_des3_input_decoder_reg_t1n_4_0_a7_0_ ( + .I0(plm_des3_reg_t1n_4_0_a7_0[0]), + .I1(plm_des3_reg_t2n_4_1_0[0]), + .I2(plm_des3_reg_data[2]), + .I3(plm_des3_reg_data[3]), + .LO(plm_reg_t1n_4_2[0]) + ); + defparam plm_des3_input_decoder_reg_t1n_3_0_a7_1_.INIT = 16'h8000; + LUT4_L plm_des3_input_decoder_reg_t1n_3_0_a7_1_ ( + .I0(plm_des3_reg_t1n_3_1[1]), + .I1(plm_des3_reg_t1n_3_2[1]), + .I2(plm_des3_reg_data[12]), + .I3(plm_des3_reg_data[13]), + .LO(plm_des3_reg_t1n_3[1]) + ); + defparam plm_des3_lfsrs_N_87674_i.INIT = 16'hF7B3; + LUT4_L plm_des3_lfsrs_N_87674_i ( + .I0(plm_des3_N_49055_i), + .I1(plm_des3_reg_lfsr_two_12_0_iv_0_o2_0[12]), + .I2(plm_des3_one_adv2[15]), + .I3(plm_des3_reg_lfsr_two_15__528), + .LO(plm_des3_N_87674_i) + ); + defparam plm_des3_lfsrs_N_87673_i.INIT = 16'hF7B3; + LUT4_L plm_des3_lfsrs_N_87673_i ( + .I0(plm_des3_N_49055_i), + .I1(plm_des3_reg_lfsr_two_12_0_iv_0_o2_0[12]), + .I2(plm_des3_one_adv2[14]), + .I3(plm_des3_reg_lfsr_two_14__628), + .LO(plm_des3_N_87673_i) + ); + defparam plm_des3_lfsrs_N_87672_i.INIT = 16'hF7B3; + LUT4_L plm_des3_lfsrs_N_87672_i ( + .I0(plm_des3_N_49055_i), + .I1(plm_des3_reg_lfsr_two_12_0_iv_0_o2_0[12]), + .I2(plm_des3_one_adv2[13]), + .I3(plm_des3_reg_lfsr_two_13__527), + .LO(plm_des3_N_87672_i) + ); + defparam plm_des3_lfsrs_N_85387_i.INIT = 16'hDFDD; + LUT4_L plm_des3_lfsrs_N_85387_i ( + .I0(plm_des3_N_49062_i), + .I1(plm_des3_reg_lfsr_one_12_iv_i_0_a2_0_0_12_), + .I2(plm_des3_reg_lfsr_two_12_iv_0_0_o4_0[9]), + .I3(plm_des3_reg_lfsr_two_12__627), + .LO(plm_des3_N_85387_i) + ); + defparam plm_des3_lfsrs_N_87671_i.INIT = 16'hF7B3; + LUT4_L plm_des3_lfsrs_N_87671_i ( + .I0(plm_des3_N_49055_i), + .I1(plm_des3_reg_lfsr_two_12_0_iv_0_o2_0[12]), + .I2(plm_des3_one_adv2[11]), + .I3(plm_des3_reg_lfsr_two_11__526), + .LO(plm_des3_N_87671_i) + ); + defparam plm_des3_lfsrs_N_85386_i.INIT = 16'hDFDD; + LUT4_L plm_des3_lfsrs_N_85386_i ( + .I0(plm_des3_N_49062_i), + .I1(plm_des3_reg_lfsr_one_12_iv_i_0_0_a2_0_1_10_), + .I2(plm_des3_reg_lfsr_two_12_iv_0_0_o4_0[9]), + .I3(plm_des3_reg_lfsr_two_10__1042), + .LO(plm_des3_N_85386_i) + ); + defparam plm_des3_lfsrs_N_85385_i.INIT = 16'hDFDD; + LUT4_L plm_des3_lfsrs_N_85385_i ( + .I0(plm_des3_N_49062_i), + .I1(plm_des3_reg_lfsr_one_12_iv_i_0_0_a2_0_1_9_), + .I2(plm_des3_reg_lfsr_two_12_iv_0_0_o4_0[9]), + .I3(plm_des3_reg_lfsr_two_9__1043), + .LO(plm_des3_N_85385_i) + ); + defparam plm_des3_lfsrs_N_85384_i.INIT = 16'hDFDD; + LUT4_L plm_des3_lfsrs_N_85384_i ( + .I0(plm_des3_N_49062_i), + .I1(plm_des3_reg_lfsr_one_12_iv_i_0_0_a2_0_1_8_), + .I2(plm_des3_reg_lfsr_two_12_iv_0_0_o4_0[9]), + .I3(plm_des3_reg_lfsr_two_8__1044), + .LO(plm_des3_N_85384_i) + ); + defparam plm_des3_lfsrs_N_85383_i.INIT = 16'hDFDD; + LUT4_L plm_des3_lfsrs_N_85383_i ( + .I0(plm_des3_N_49062_i), + .I1(plm_des3_reg_lfsr_one_12_iv_i_0_a2_0_0_7_), + .I2(plm_des3_reg_lfsr_two_12_iv_0_0_o4_0[9]), + .I3(plm_des3_reg_lfsr_two_7__1045), + .LO(plm_des3_N_85383_i) + ); + defparam plm_des3_lfsrs_N_85382_i.INIT = 16'hDFDD; + LUT4_L plm_des3_lfsrs_N_85382_i ( + .I0(plm_des3_N_49062_i), + .I1(plm_des3_reg_lfsr_one_12_iv_i_0_0_a2_0_1_6_), + .I2(plm_des3_reg_lfsr_two_12_iv_0_0_o4_0[9]), + .I3(plm_des3_reg_lfsr_two_6__1046), + .LO(plm_des3_N_85382_i) + ); + defparam plm_des3_lfsrs_N_85381_i.INIT = 16'hDFDD; + LUT4_L plm_des3_lfsrs_N_85381_i ( + .I0(plm_des3_N_49062_i), + .I1(plm_des3_reg_lfsr_one_12_iv_i_0_0_a2_0_1_5_), + .I2(plm_des3_reg_lfsr_two_12_iv_0_0_o4_0[9]), + .I3(plm_des3_reg_lfsr_two_5__1047), + .LO(plm_des3_N_85381_i) + ); + defparam plm_des3_lfsrs_N_87670_i.INIT = 16'hF7B3; + LUT4_L plm_des3_lfsrs_N_87670_i ( + .I0(plm_des3_N_49055_i), + .I1(plm_des3_reg_lfsr_two_12_0_iv_0_o2_0[12]), + .I2(plm_des3_one_adv2[4]), + .I3(plm_des3_reg_lfsr_two_4__660), + .LO(plm_des3_N_87670_i) + ); + defparam plm_des3_lfsrs_N_85380_i.INIT = 16'hFDDD; + LUT4_L plm_des3_lfsrs_N_85380_i ( + .I0(plm_des3_N_49062_i), + .I1(plm_des3_reg_lfsr_one_12_iv_i_0_a2_0[3]), + .I2(plm_des3_reg_lfsr_two_12_iv_0_0_a4_1_0[9]), + .I3(plm_des3_one_adv2[3]), + .LO(plm_des3_N_85380_i) + ); + defparam plm_des3_lfsrs_N_87669_i.INIT = 16'hF7B3; + LUT4_L plm_des3_lfsrs_N_87669_i ( + .I0(plm_des3_N_49055_i), + .I1(plm_des3_reg_lfsr_two_12_0_iv_0_o2_0[12]), + .I2(plm_des3_one_adv2[2]), + .I3(plm_des3_reg_lfsr_two_2__661), + .LO(plm_des3_N_87669_i) + ); + defparam plm_des3_lfsrs_N_87667_i.INIT = 16'hF7B3; + LUT4_L plm_des3_lfsrs_N_87667_i ( + .I0(plm_des3_N_49055_i), + .I1(plm_des3_reg_lfsr_two_12_0_iv_0_o2_0[12]), + .I2(plm_des3_one_adv2[1]), + .I3(plm_des3_reg_lfsr_two_1__1048), + .LO(plm_des3_N_87667_i) + ); + defparam plm_des3_lfsrs_N_87666_i.INIT = 16'hDF8F; + LUT4_L plm_des3_lfsrs_N_87666_i ( + .I0(plm_des3_N_49055_i), + .I1(plm_des3_N_49080_i_0), + .I2(plm_des3_reg_lfsr_two_12_0_iv_0_o2_0[12]), + .I3(plm_des3_reg_lfsr_two_0__525), + .LO(plm_des3_N_87666_i) + ); + defparam plm_des3_lfsrs_N_85395_i.INIT = 16'hFDDD; + LUT4_L plm_des3_lfsrs_N_85395_i ( + .I0(plm_des3_N_49062_i), + .I1(plm_des3_reg_lfsr_two_12_iv_i_0_a2_0[15]), + .I2(plm_des3_reg_lfsr_two_12_iv_0_0_a4_1_0[9]), + .I3(plm_des3_two_adv2_15__1028), + .LO(plm_des3_N_85395_i) + ); + defparam plm_des3_lfsrs_N_85394_i.INIT = 16'h4F8F; + LUT4_L plm_des3_lfsrs_N_85394_i ( + .I0(N_49085_i_0), + .I1(plm_des3_reg_lfsr_two_12_iv_0_0_a4_1_0[9]), + .I2(plm_des3_reg_lfsr_two_12_iv_i_0_0[14]), + .I3(plm_des3_two_adv2_1_14__1029), + .LO(plm_des3_N_85394_i) + ); + defparam plm_des3_lfsrs_N_85393_i.INIT = 16'hDFDD; + LUT4_L plm_des3_lfsrs_N_85393_i ( + .I0(plm_des3_N_49062_i), + .I1(plm_des3_reg_lfsr_two_12_iv_i_0_a2_0_0_13_), + .I2(plm_des3_reg_lfsr_two_12_iv_0_0_o4_0[9]), + .I3(plm_des3_one_adv2[13]), + .LO(plm_des3_N_85393_i) + ); + defparam plm_des3_lfsrs_reg_lfsr_two_12_0_iv_0_12_.INIT = 16'hC840; + LUT4_L plm_des3_lfsrs_reg_lfsr_two_12_0_iv_0_12_ ( + .I0(plm_des3_N_49055_i), + .I1(plm_des3_reg_lfsr_two_12_0_iv_0_o2_0[12]), + .I2(plm_des3_one_adv2[12]), + .I3(plm_des3_two_adv2_12__1030), + .LO(plm_des3_N_9607_i) + ); + defparam plm_des3_lfsrs_N_85392_i.INIT = 16'hDFDD; + LUT4_L plm_des3_lfsrs_N_85392_i ( + .I0(plm_des3_N_49062_i), + .I1(plm_des3_reg_lfsr_two_12_iv_i_0_a2_0_0_11_), + .I2(plm_des3_reg_lfsr_two_12_iv_0_0_o4_0[9]), + .I3(plm_des3_one_adv2[11]), + .LO(plm_des3_N_85392_i) + ); + defparam plm_des3_lfsrs_reg_lfsr_two_12_0_iv_i_i_10_.INIT = 16'hC840; + LUT4_L plm_des3_lfsrs_reg_lfsr_two_12_0_iv_i_i_10_ ( + .I0(plm_des3_N_49055_i), + .I1(plm_des3_reg_lfsr_two_12_0_iv_0_o2_0[12]), + .I2(plm_des3_one_adv2[10]), + .I3(plm_des3_two_adv2_10__1031), + .LO(plm_des3_N_48875_i) + ); + defparam plm_des3_lfsrs_reg_lfsr_two_12_iv_0_0_9_.INIT = 16'h2220; + LUT4_L plm_des3_lfsrs_reg_lfsr_two_12_iv_0_0_9_ ( + .I0(plm_des3_N_49062_i), + .I1(plm_des3_reg_lfsr_two_12_iv_0_0_a2_0_9_), + .I2(plm_des3_reg_lfsr_two_12_iv_0_0_o4_0[9]), + .I3(plm_des3_one_adv2[9]), + .LO(plm_des3_N_9610_i) + ); + defparam plm_des3_lfsrs_reg_lfsr_two_12_iv_0_0_8_.INIT = 16'h2220; + LUT4_L plm_des3_lfsrs_reg_lfsr_two_12_iv_0_0_8_ ( + .I0(plm_des3_N_49062_i), + .I1(plm_des3_reg_lfsr_two_12_iv_0_0_a2_0_8_), + .I2(plm_des3_reg_lfsr_two_12_iv_0_0_o4_0[9]), + .I3(plm_des3_one_adv2[8]), + .LO(plm_des3_N_9611_i) + ); + defparam plm_des3_lfsrs_reg_lfsr_two_12_0_iv_0_7_.INIT = 16'hC840; + LUT4_L plm_des3_lfsrs_reg_lfsr_two_12_0_iv_0_7_ ( + .I0(plm_des3_N_49055_i), + .I1(plm_des3_reg_lfsr_two_12_0_iv_0_o2_0[12]), + .I2(plm_des3_one_adv2[7]), + .I3(plm_des3_two_adv2_7__1032), + .LO(plm_des3_N_9612_i) + ); + defparam plm_des3_lfsrs_reg_lfsr_two_12_0_iv_0_6_.INIT = 16'hC840; + LUT4_L plm_des3_lfsrs_reg_lfsr_two_12_0_iv_0_6_ ( + .I0(plm_des3_N_49055_i), + .I1(plm_des3_reg_lfsr_two_12_0_iv_0_o2_0[12]), + .I2(plm_des3_one_adv2[6]), + .I3(plm_des3_two_adv2_6__1033), + .LO(plm_des3_N_9613_i) + ); + defparam plm_des3_lfsrs_reg_lfsr_two_12_iv_0_0_5_.INIT = 16'h2220; + LUT4_L plm_des3_lfsrs_reg_lfsr_two_12_iv_0_0_5_ ( + .I0(plm_des3_N_49062_i), + .I1(plm_des3_reg_lfsr_two_12_iv_0_0_a2_0_5_), + .I2(plm_des3_reg_lfsr_two_12_iv_0_0_o4_0[9]), + .I3(plm_des3_one_adv2[5]), + .LO(plm_des3_N_9614_i) + ); + defparam plm_des3_lfsrs_N_85391_i.INIT = 16'hDFDD; + LUT4_L plm_des3_lfsrs_N_85391_i ( + .I0(plm_des3_N_49062_i), + .I1(plm_des3_reg_lfsr_two_12_iv_i_0_a2_0_0_4_), + .I2(plm_des3_reg_lfsr_two_12_iv_0_0_o4_0[9]), + .I3(plm_des3_one_adv2[4]), + .LO(plm_des3_N_85391_i) + ); + defparam plm_des3_lfsrs_reg_lfsr_two_12_iv_0_0_0_3_.INIT = 16'h2220; + LUT4_L plm_des3_lfsrs_reg_lfsr_two_12_iv_0_0_0_3_ ( + .I0(plm_des3_N_49062_i), + .I1(plm_des3_reg_lfsr_two_12_iv_0_0_0_a2[3]), + .I2(plm_des3_reg_lfsr_two_12_iv_0_0_o4_0[9]), + .I3(plm_des3_one_adv2[3]), + .LO(plm_des3_N_9616_i) + ); + defparam plm_des3_lfsrs_N_85390_i.INIT = 16'hDFDD; + LUT4_L plm_des3_lfsrs_N_85390_i ( + .I0(plm_des3_N_49062_i), + .I1(plm_des3_reg_lfsr_two_12_iv_i_0_a2_0_0_2_), + .I2(plm_des3_reg_lfsr_two_12_iv_0_0_o4_0[9]), + .I3(plm_des3_one_adv2[2]), + .LO(plm_des3_N_85390_i) + ); + defparam plm_des3_lfsrs_N_85389_i.INIT = 16'hDFDD; + LUT4_L plm_des3_lfsrs_N_85389_i ( + .I0(plm_des3_N_49062_i), + .I1(plm_des3_reg_lfsr_two_12_iv_i_0_a2_0_0_1_), + .I2(plm_des3_reg_lfsr_two_12_iv_0_0_o4_0[9]), + .I3(plm_des3_one_adv2[1]), + .LO(plm_des3_N_85389_i) + ); + defparam plm_des3_lfsrs_N_85388_i.INIT = 16'hF5FD; + LUT4_L plm_des3_lfsrs_N_85388_i ( + .I0(plm_des3_N_49062_i), + .I1(plm_des3_N_49080_i_0), + .I2(plm_des3_reg_lfsr_two_12_iv_i_0_a2_0_0_0_), + .I3(plm_des3_reg_lfsr_two_12_iv_0_0_o4_0[9]), + .LO(plm_des3_N_85388_i) + ); + defparam plm_des3_lfsrs_reg_lfsr_two_12_iv_0_0_a4_1_9_.INIT = 8'h01; + LUT3 plm_des3_lfsrs_reg_lfsr_two_12_iv_0_0_a4_1_9_ ( + .I0(plm_reg_com_1[1]), + .I1(plm_des3_reg_skp[1]), + .I2(plm_des3_reg_skp[0]), + .O(plm_des3_reg_lfsr_two_12_iv_0_0_a4_1_0[9]) + ); + FDC plm_des3_reg_rx_des_dat_5_ ( + .C(mgt_clk), + .D(plm_des3_reg_rx_des_dat_14[5]), + .Q(plm_rx3_des_dat[5]), + .CLR(plm_rst) + ); + FDC plm_des3_reg_rx_des_dat_4_ ( + .C(mgt_clk), + .D(plm_des3_reg_rx_des_dat_14[4]), + .Q(plm_rx3_des_dat[4]), + .CLR(plm_rst) + ); + FDC plm_des3_reg_rx_des_dat_3_ ( + .C(mgt_clk), + .D(plm_des3_reg_rx_des_dat_14[3]), + .Q(plm_rx3_des_dat[3]), + .CLR(plm_rst) + ); + FDC plm_des3_reg_rx_des_dat_2_ ( + .C(mgt_clk), + .D(plm_des3_reg_rx_des_dat_14[2]), + .Q(plm_rx3_des_dat[2]), + .CLR(plm_rst) + ); + FDC plm_des3_reg_rx_des_dat_1_ ( + .C(mgt_clk), + .D(plm_des3_reg_rx_des_dat_14[1]), + .Q(plm_rx3_des_dat[1]), + .CLR(plm_rst) + ); + FDC plm_des3_reg_rx_des_dat_0_ ( + .C(mgt_clk), + .D(plm_des3_reg_rx_des_dat_14[0]), + .Q(plm_rx3_des_dat[0]), + .CLR(plm_rst) + ); + FDC plm_des3_reg_rx_des_bad_1_ ( + .C(mgt_clk), + .D(plm_des3_reg_bad[1]), + .Q(plm_rx3_des_bad[1]), + .CLR(plm_rst) + ); + FDC plm_des3_reg_rx_des_bad_0_ ( + .C(mgt_clk), + .D(plm_des3_reg_bad[0]), + .Q(plm_rx3_des_bad[0]), + .CLR(plm_rst) + ); + FDC plm_des3_reg_bad_1_ ( + .C(mgt_clk), + .D(plm_des3_N_85322_i), + .Q(plm_des3_reg_bad[1]), + .CLR(plm_rst) + ); + FDC plm_des3_reg_bad_0_ ( + .C(mgt_clk), + .D(plm_des3_N_85323_i), + .Q(plm_des3_reg_bad[0]), + .CLR(plm_rst) + ); + FDC plm_des3_reg_rx_des_dat_15_ ( + .C(mgt_clk), + .D(plm_des3_N_49228_i_0_i), + .Q(plm_rx3_des_dat[15]), + .CLR(plm_rst) + ); + FDC plm_des3_reg_rx_des_dat_14_ ( + .C(mgt_clk), + .D(plm_des3_N_49226_i_0_i), + .Q(plm_rx3_des_dat[14]), + .CLR(plm_rst) + ); + FDC plm_des3_reg_rx_des_dat_13_ ( + .C(mgt_clk), + .D(plm_des3_N_49224_i_0_i), + .Q(plm_rx3_des_dat[13]), + .CLR(plm_rst) + ); + FDC plm_des3_reg_rx_des_dat_12_ ( + .C(mgt_clk), + .D(plm_des3_N_49222_i_0_i), + .Q(plm_rx3_des_dat[12]), + .CLR(plm_rst) + ); + FDC plm_des3_reg_rx_des_dat_11_ ( + .C(mgt_clk), + .D(plm_des3_N_49220_i_0_i), + .Q(plm_rx3_des_dat[11]), + .CLR(plm_rst) + ); + FDC plm_des3_reg_rx_des_dat_10_ ( + .C(mgt_clk), + .D(plm_des3_N_49218_i_0_i), + .Q(plm_rx3_des_dat[10]), + .CLR(plm_rst) + ); + FDC plm_des3_reg_rx_des_dat_9_ ( + .C(mgt_clk), + .D(plm_des3_N_49216_i_0_i), + .Q(plm_rx3_des_dat[9]), + .CLR(plm_rst) + ); + FDC plm_des3_reg_rx_des_dat_8_ ( + .C(mgt_clk), + .D(plm_des3_N_49214_i_0_i), + .Q(plm_rx3_des_dat[8]), + .CLR(plm_rst) + ); + FDC plm_des3_reg_rx_des_dat_7_ ( + .C(mgt_clk), + .D(plm_des3_reg_rx_des_dat_14[7]), + .Q(plm_rx3_des_dat[7]), + .CLR(plm_rst) + ); + FDC plm_des3_reg_rx_des_dat_6_ ( + .C(mgt_clk), + .D(plm_des3_reg_rx_des_dat_14[6]), + .Q(plm_rx3_des_dat[6]), + .CLR(plm_rst) + ); + FDC plm_des3_reg_edg_1_ ( + .C(mgt_clk), + .D(plm_des3_reg_edg_3[1]), + .Q(plm_des3_reg_edg[1]), + .CLR(plm_rst) + ); + FDC plm_des3_reg_edg_0_ ( + .C(mgt_clk), + .D(plm_des3_reg_edg_4[0]), + .Q(plm_des3_reg_edg[0]), + .CLR(plm_rst) + ); + FDC plm_des3_reg_edb_1_ ( + .C(mgt_clk), + .D(plm_des3_reg_edb_3[1]), + .Q(plm_des3_reg_edb[1]), + .CLR(plm_rst) + ); + FDC plm_des3_reg_edb_0_ ( + .C(mgt_clk), + .D(plm_des3_reg_edb_4[0]), + .Q(plm_des3_reg_edb[0]), + .CLR(plm_rst) + ); + FDC plm_des3_reg_com_1_ ( + .C(mgt_clk), + .D(plm_des3_reg_com_3[1]), + .Q(plm_reg_com_1[1]), + .CLR(plm_rst) + ); + FDC plm_des3_reg_com_0_ ( + .C(mgt_clk), + .D(plm_des3_reg_com_4[0]), + .Q(plm_reg_com_1[0]), + .CLR(plm_rst) + ); + FDC plm_des3_reg_rx_des_t2p_1_ ( + .C(mgt_clk), + .D(plm_des3_reg_t2p[1]), + .Q(plm_rx3_des_t2p[1]), + .CLR(plm_rst) + ); + FDC plm_des3_reg_rx_des_t2n_1_ ( + .C(mgt_clk), + .D(plm_des3_reg_t2n[1]), + .Q(plm_rx3_des_t2n[1]), + .CLR(plm_rst) + ); + FDC plm_des3_reg_t2p_1_ ( + .C(mgt_clk), + .D(plm_des3_reg_t2p_3[1]), + .Q(plm_des3_reg_t2p[1]), + .CLR(plm_rst) + ); + FDC plm_des3_reg_t2n_1_ ( + .C(mgt_clk), + .D(plm_des3_reg_t2n_3[1]), + .Q(plm_des3_reg_t2n[1]), + .CLR(plm_rst) + ); + FDC plm_des3_reg_t1p_1_ ( + .C(mgt_clk), + .D(plm_des3_reg_t1p_3[1]), + .Q(plm_des3_reg_t1p[1]), + .CLR(plm_rst) + ); + FDC plm_des3_reg_rx_des_edg_1_ ( + .C(mgt_clk), + .D(plm_des3_reg_edg[1]), + .Q(plm_rx3_des_edg[1]), + .CLR(plm_rst) + ); + FDC plm_des3_reg_rx_des_edg_0_ ( + .C(mgt_clk), + .D(plm_des3_reg_edg[0]), + .Q(plm_rx3_des_edg[0]), + .CLR(plm_rst) + ); + FDC plm_des3_reg_rx_des_edb_1_ ( + .C(mgt_clk), + .D(plm_des3_reg_edb[1]), + .Q(plm_rx3_des_edb[1]), + .CLR(plm_rst) + ); + FDC plm_des3_reg_rx_des_edb_0_ ( + .C(mgt_clk), + .D(plm_des3_reg_edb[0]), + .Q(plm_rx3_des_edb[0]), + .CLR(plm_rst) + ); + FDC plm_des3_reg_skp_1_ ( + .C(mgt_clk), + .D(plm_des3_reg_skp_3[1]), + .Q(plm_des3_reg_skp[1]), + .CLR(plm_rst) + ); + FDC plm_des3_reg_skp_0_ ( + .C(mgt_clk), + .D(plm_des3_reg_skp_4[0]), + .Q(plm_des3_reg_skp[0]), + .CLR(plm_rst) + ); + FDC plm_des3_reg_rx_des_sym_1_ ( + .C(mgt_clk), + .D(plm_des3_reg_sym[1]), + .Q(plm_rx3_des_sym[1]), + .CLR(plm_rst) + ); + FDC plm_des3_reg_rx_des_sym_0_ ( + .C(mgt_clk), + .D(plm_des3_reg_sym[0]), + .Q(plm_rx3_des_sym[0]), + .CLR(plm_rst) + ); + FDC plm_des3_reg_rx_des_t1p_1_ ( + .C(mgt_clk), + .D(plm_des3_reg_t1p[1]), + .Q(plm_rx3_des_t1p[1]), + .CLR(plm_rst) + ); + FDC plm_des3_reg_rx_des_t1n_1_ ( + .C(mgt_clk), + .D(plm_des3_reg_t1n[1]), + .Q(plm_rx3_des_t1n[1]), + .CLR(plm_rst) + ); + FDC plm_des3_reg_rx_raw_dat_13_ ( + .C(mgt_clk), + .D(plm_des3_reg_dat[13]), + .Q(plm_rx3_raw_dat[13]), + .CLR(plm_rst) + ); + FDC plm_des3_reg_rx_raw_dat_12_ ( + .C(mgt_clk), + .D(plm_des3_reg_dat[12]), + .Q(plm_rx3_raw_dat[12]), + .CLR(plm_rst) + ); + FDC plm_des3_reg_rx_raw_dat_11_ ( + .C(mgt_clk), + .D(plm_des3_reg_dat[11]), + .Q(plm_rx3_raw_dat[11]), + .CLR(plm_rst) + ); + FDC plm_des3_reg_rx_raw_dat_10_ ( + .C(mgt_clk), + .D(plm_des3_reg_dat[10]), + .Q(plm_rx3_raw_dat[10]), + .CLR(plm_rst) + ); + FDC plm_des3_reg_rx_raw_dat_9_ ( + .C(mgt_clk), + .D(plm_des3_reg_dat[9]), + .Q(plm_rx3_raw_dat[9]), + .CLR(plm_rst) + ); + FDC plm_des3_reg_rx_raw_dat_8_ ( + .C(mgt_clk), + .D(plm_des3_reg_dat[8]), + .Q(plm_rx3_raw_dat[8]), + .CLR(plm_rst) + ); + FDC plm_des3_reg_rx_raw_dat_7_ ( + .C(mgt_clk), + .D(plm_des3_reg_dat[7]), + .Q(plm_rx3_raw_dat[7]), + .CLR(plm_rst) + ); + FDC plm_des3_reg_rx_raw_dat_6_ ( + .C(mgt_clk), + .D(plm_des3_reg_dat[6]), + .Q(plm_rx3_raw_dat[6]), + .CLR(plm_rst) + ); + FDC plm_des3_reg_rx_raw_dat_5_ ( + .C(mgt_clk), + .D(plm_des3_reg_dat[5]), + .Q(plm_rx3_raw_dat[5]), + .CLR(plm_rst) + ); + FDC plm_des3_reg_rx_raw_dat_4_ ( + .C(mgt_clk), + .D(plm_des3_reg_dat[4]), + .Q(plm_rx3_raw_dat[4]), + .CLR(plm_rst) + ); + FDC plm_des3_reg_rx_raw_dat_3_ ( + .C(mgt_clk), + .D(plm_des3_reg_dat[3]), + .Q(plm_rx3_raw_dat[3]), + .CLR(plm_rst) + ); + FDC plm_des3_reg_rx_raw_dat_2_ ( + .C(mgt_clk), + .D(plm_des3_reg_dat[2]), + .Q(plm_rx3_raw_dat[2]), + .CLR(plm_rst) + ); + FDC plm_des3_reg_rx_raw_dat_1_ ( + .C(mgt_clk), + .D(plm_des3_reg_dat[1]), + .Q(plm_rx3_raw_dat[1]), + .CLR(plm_rst) + ); + FDC plm_des3_reg_rx_raw_dat_0_ ( + .C(mgt_clk), + .D(plm_des3_reg_dat[0]), + .Q(plm_rx3_raw_dat[0]), + .CLR(plm_rst) + ); + FDC plm_des3_reg_t1n_1_ ( + .C(mgt_clk), + .D(plm_des3_reg_t1n_3[1]), + .Q(plm_des3_reg_t1n[1]), + .CLR(plm_rst) + ); + FDC plm_des3_reg_data_6_ ( + .C(mgt_clk), + .D(plm_rx3_data[6]), + .Q(plm_des3_reg_data[6]), + .CLR(plm_rst) + ); + FDC plm_des3_reg_data_5_ ( + .C(mgt_clk), + .D(plm_rx3_data[5]), + .Q(plm_des3_reg_data[5]), + .CLR(plm_rst) + ); + FDC plm_des3_reg_data_4_ ( + .C(mgt_clk), + .D(plm_rx3_data[4]), + .Q(plm_des3_reg_data[4]), + .CLR(plm_rst) + ); + FDC plm_des3_reg_data_3_ ( + .C(mgt_clk), + .D(plm_rx3_data[3]), + .Q(plm_des3_reg_data[3]), + .CLR(plm_rst) + ); + FDC plm_des3_reg_data_2_ ( + .C(mgt_clk), + .D(plm_rx3_data[2]), + .Q(plm_des3_reg_data[2]), + .CLR(plm_rst) + ); + FDC plm_des3_reg_data_1_ ( + .C(mgt_clk), + .D(plm_rx3_data[1]), + .Q(plm_des3_reg_data[1]), + .CLR(plm_rst) + ); + FDC plm_des3_reg_data_0_ ( + .C(mgt_clk), + .D(plm_rx3_data[0]), + .Q(plm_des3_reg_data[0]), + .CLR(plm_rst) + ); + FDC plm_des3_reg_spesh_1_ ( + .C(mgt_clk), + .D(plm_rx3_char_is_k[1]), + .Q(plm_des3_reg_spesh[1]), + .CLR(plm_rst) + ); + FDC plm_des3_reg_spesh_0_ ( + .C(mgt_clk), + .D(plm_rx3_char_is_k[0]), + .Q(plm_des3_reg_spesh[0]), + .CLR(plm_rst) + ); + FDC plm_des3_reg_nitbl_1_ ( + .C(mgt_clk), + .D(plm_rx3_not_in_table[1]), + .Q(plm_des3_reg_nitbl[1]), + .CLR(plm_rst) + ); + FDC plm_des3_reg_nitbl_0_ ( + .C(mgt_clk), + .D(plm_rx3_not_in_table[0]), + .Q(plm_des3_reg_nitbl[0]), + .CLR(plm_rst) + ); + FDC plm_des3_reg_sym_1_ ( + .C(mgt_clk), + .D(plm_des3_reg_sym_3[1]), + .Q(plm_des3_reg_sym[1]), + .CLR(plm_rst) + ); + FDC plm_des3_reg_sym_0_ ( + .C(mgt_clk), + .D(plm_des3_reg_sym_4[0]), + .Q(plm_des3_reg_sym[0]), + .CLR(plm_rst) + ); + FDC plm_des3_reg_rx_raw_dat_15_ ( + .C(mgt_clk), + .D(plm_des3_reg_dat[15]), + .Q(plm_rx3_raw_dat[15]), + .CLR(plm_rst) + ); + FDC plm_des3_reg_rx_raw_dat_14_ ( + .C(mgt_clk), + .D(plm_des3_reg_dat[14]), + .Q(plm_rx3_raw_dat[14]), + .CLR(plm_rst) + ); + FDC plm_des3_reg_dat_3_ ( + .C(mgt_clk), + .D(plm_des3_reg_data[3]), + .Q(plm_des3_reg_dat[3]), + .CLR(plm_rst) + ); + FDC plm_des3_reg_dat_2_ ( + .C(mgt_clk), + .D(plm_des3_reg_data[2]), + .Q(plm_des3_reg_dat[2]), + .CLR(plm_rst) + ); + FDC plm_des3_reg_dat_1_ ( + .C(mgt_clk), + .D(plm_des3_reg_data[1]), + .Q(plm_des3_reg_dat[1]), + .CLR(plm_rst) + ); + FDC plm_des3_reg_dat_0_ ( + .C(mgt_clk), + .D(plm_des3_reg_data[0]), + .Q(plm_des3_reg_dat[0]), + .CLR(plm_rst) + ); + FDC plm_des3_reg_kkk_1_ ( + .C(mgt_clk), + .D(plm_des3_reg_spesh[1]), + .Q(plm_des3_reg_kkk[1]), + .CLR(plm_rst) + ); + FDC plm_des3_reg_kkk_0_ ( + .C(mgt_clk), + .D(plm_des3_reg_spesh[0]), + .Q(plm_des3_reg_kkk[0]), + .CLR(plm_rst) + ); + FDC plm_des3_reg_data_15_ ( + .C(mgt_clk), + .D(plm_rx3_data[15]), + .Q(plm_des3_reg_data[15]), + .CLR(plm_rst) + ); + FDC plm_des3_reg_data_14_ ( + .C(mgt_clk), + .D(plm_rx3_data[14]), + .Q(plm_des3_reg_data[14]), + .CLR(plm_rst) + ); + FDC plm_des3_reg_data_13_ ( + .C(mgt_clk), + .D(plm_rx3_data[13]), + .Q(plm_des3_reg_data[13]), + .CLR(plm_rst) + ); + FDC plm_des3_reg_data_12_ ( + .C(mgt_clk), + .D(plm_rx3_data[12]), + .Q(plm_des3_reg_data[12]), + .CLR(plm_rst) + ); + FDC plm_des3_reg_data_11_ ( + .C(mgt_clk), + .D(plm_rx3_data[11]), + .Q(plm_des3_reg_data[11]), + .CLR(plm_rst) + ); + FDC plm_des3_reg_data_10_ ( + .C(mgt_clk), + .D(plm_rx3_data[10]), + .Q(plm_des3_reg_data[10]), + .CLR(plm_rst) + ); + FDC plm_des3_reg_data_9_ ( + .C(mgt_clk), + .D(plm_rx3_data[9]), + .Q(plm_des3_reg_data[9]), + .CLR(plm_rst) + ); + FDC plm_des3_reg_data_8_ ( + .C(mgt_clk), + .D(plm_rx3_data[8]), + .Q(plm_des3_reg_data[8]), + .CLR(plm_rst) + ); + FDC plm_des3_reg_data_7_ ( + .C(mgt_clk), + .D(plm_rx3_data[7]), + .Q(plm_des3_reg_data[7]), + .CLR(plm_rst) + ); + FDC plm_des3_reg_dat_15_ ( + .C(mgt_clk), + .D(plm_des3_reg_data[15]), + .Q(plm_des3_reg_dat[15]), + .CLR(plm_rst) + ); + FDC plm_des3_reg_dat_14_ ( + .C(mgt_clk), + .D(plm_des3_reg_data[14]), + .Q(plm_des3_reg_dat[14]), + .CLR(plm_rst) + ); + FDC plm_des3_reg_dat_13_ ( + .C(mgt_clk), + .D(plm_des3_reg_data[13]), + .Q(plm_des3_reg_dat[13]), + .CLR(plm_rst) + ); + FDC plm_des3_reg_dat_12_ ( + .C(mgt_clk), + .D(plm_des3_reg_data[12]), + .Q(plm_des3_reg_dat[12]), + .CLR(plm_rst) + ); + FDC plm_des3_reg_dat_11_ ( + .C(mgt_clk), + .D(plm_des3_reg_data[11]), + .Q(plm_des3_reg_dat[11]), + .CLR(plm_rst) + ); + FDC plm_des3_reg_dat_10_ ( + .C(mgt_clk), + .D(plm_des3_reg_data[10]), + .Q(plm_des3_reg_dat[10]), + .CLR(plm_rst) + ); + FDC plm_des3_reg_dat_9_ ( + .C(mgt_clk), + .D(plm_des3_reg_data[9]), + .Q(plm_des3_reg_dat[9]), + .CLR(plm_rst) + ); + FDC plm_des3_reg_dat_8_ ( + .C(mgt_clk), + .D(plm_des3_reg_data[8]), + .Q(plm_des3_reg_dat[8]), + .CLR(plm_rst) + ); + FDC plm_des3_reg_dat_7_ ( + .C(mgt_clk), + .D(plm_des3_reg_data[7]), + .Q(plm_des3_reg_dat[7]), + .CLR(plm_rst) + ); + FDC plm_des3_reg_dat_6_ ( + .C(mgt_clk), + .D(plm_des3_reg_data[6]), + .Q(plm_des3_reg_dat[6]), + .CLR(plm_rst) + ); + FDC plm_des3_reg_dat_5_ ( + .C(mgt_clk), + .D(plm_des3_reg_data[5]), + .Q(plm_des3_reg_dat[5]), + .CLR(plm_rst) + ); + FDC plm_des3_reg_dat_4_ ( + .C(mgt_clk), + .D(plm_des3_reg_data[4]), + .Q(plm_des3_reg_dat[4]), + .CLR(plm_rst) + ); + FDPE plm_des3_reg_lfsr_one_15_ ( + .PRE(plm_rst), + .CE(plm_des3_reg_lfsr_one32_i), + .C(mgt_clk), + .D(plm_des3_N_87674_i), + .Q(plm_des3_reg_lfsr_one_15__514) + ); + FDPE plm_des3_reg_lfsr_one_14_ ( + .PRE(plm_rst), + .CE(plm_des3_reg_lfsr_one32_i), + .C(mgt_clk), + .D(plm_des3_N_87673_i), + .Q(plm_des3_reg_lfsr_one_14__657) + ); + FDPE plm_des3_reg_lfsr_one_13_ ( + .PRE(plm_rst), + .CE(plm_des3_reg_lfsr_one32_i), + .C(mgt_clk), + .D(plm_des3_N_87672_i), + .Q(plm_des3_reg_lfsr_one_13__517) + ); + FDPE plm_des3_reg_lfsr_one_12_ ( + .PRE(plm_rst), + .CE(plm_des3_reg_lfsr_one32_i), + .C(mgt_clk), + .D(plm_des3_N_85387_i), + .Q(plm_des3_reg_lfsr_one_12__620) + ); + FDPE plm_des3_reg_lfsr_one_11_ ( + .PRE(plm_rst), + .CE(plm_des3_reg_lfsr_one32_i), + .C(mgt_clk), + .D(plm_des3_N_87671_i), + .Q(plm_des3_reg_lfsr_one_11__636) + ); + FDPE plm_des3_reg_lfsr_one_10_ ( + .PRE(plm_rst), + .CE(plm_des3_reg_lfsr_one32_i), + .C(mgt_clk), + .D(plm_des3_N_85386_i), + .Q(plm_des3_reg_lfsr_one_10__1034) + ); + FDPE plm_des3_reg_lfsr_one_9_ ( + .PRE(plm_rst), + .CE(plm_des3_reg_lfsr_one32_i), + .C(mgt_clk), + .D(plm_des3_N_85385_i), + .Q(plm_des3_reg_lfsr_one_9__1035) + ); + FDPE plm_des3_reg_lfsr_one_8_ ( + .PRE(plm_rst), + .CE(plm_des3_reg_lfsr_one32_i), + .C(mgt_clk), + .D(plm_des3_N_85384_i), + .Q(plm_des3_reg_lfsr_one_8__1036) + ); + FDPE plm_des3_reg_lfsr_one_7_ ( + .PRE(plm_rst), + .CE(plm_des3_reg_lfsr_one32_i), + .C(mgt_clk), + .D(plm_des3_N_85383_i), + .Q(plm_des3_reg_lfsr_one_7__1037) + ); + FDPE plm_des3_reg_lfsr_one_6_ ( + .PRE(plm_rst), + .CE(plm_des3_reg_lfsr_one32_i), + .C(mgt_clk), + .D(plm_des3_N_85382_i), + .Q(plm_des3_reg_lfsr_one_6__1038) + ); + FDPE plm_des3_reg_lfsr_one_5_ ( + .PRE(plm_rst), + .CE(plm_des3_reg_lfsr_one32_i), + .C(mgt_clk), + .D(plm_des3_N_85381_i), + .Q(plm_des3_reg_lfsr_one_5__1039) + ); + FDPE plm_des3_reg_lfsr_one_4_ ( + .PRE(plm_rst), + .CE(plm_des3_reg_lfsr_one32_i), + .C(mgt_clk), + .D(plm_des3_N_87670_i), + .Q(plm_des3_reg_lfsr_one_4__1040) + ); + FDPE plm_des3_reg_lfsr_one_3_ ( + .PRE(plm_rst), + .CE(plm_des3_reg_lfsr_one32_i), + .C(mgt_clk), + .D(plm_des3_N_85380_i), + .Q(plm_des3_reg_lfsr_one_3__516) + ); + FDPE plm_des3_reg_lfsr_one_2_ ( + .PRE(plm_rst), + .CE(plm_des3_reg_lfsr_one32_i), + .C(mgt_clk), + .D(plm_des3_N_87669_i), + .Q(plm_des3_reg_lfsr_one_2__1041) + ); + FDPE plm_des3_reg_lfsr_one_1_ ( + .PRE(plm_rst), + .CE(plm_des3_reg_lfsr_one32_i), + .C(mgt_clk), + .D(plm_des3_N_87667_i), + .Q(plm_des3_reg_lfsr_one_1__513) + ); + FDPE plm_des3_reg_lfsr_one_0_ ( + .PRE(plm_rst), + .CE(plm_des3_reg_lfsr_one32_i), + .C(mgt_clk), + .D(plm_des3_N_87666_i), + .Q(plm_des3_reg_lfsr_one_0__635) + ); + FDPE plm_des3_reg_lfsr_two_15_ ( + .PRE(plm_rst), + .CE(plm_des3_reg_lfsr_one32_i), + .C(mgt_clk), + .D(plm_des3_N_85395_i), + .Q(plm_des3_reg_lfsr_two_15__528) + ); + FDPE plm_des3_reg_lfsr_two_14_ ( + .PRE(plm_rst), + .CE(plm_des3_reg_lfsr_one32_i), + .C(mgt_clk), + .D(plm_des3_N_85394_i), + .Q(plm_des3_reg_lfsr_two_14__628) + ); + FDPE plm_des3_reg_lfsr_two_13_ ( + .PRE(plm_rst), + .CE(plm_des3_reg_lfsr_one32_i), + .C(mgt_clk), + .D(plm_des3_N_85393_i), + .Q(plm_des3_reg_lfsr_two_13__527) + ); + FDCE plm_des3_reg_lfsr_two_12_ ( + .CE(plm_des3_reg_lfsr_one32_i), + .C(mgt_clk), + .D(plm_des3_N_9607_i), + .Q(plm_des3_reg_lfsr_two_12__627), + .CLR(plm_rst) + ); + FDPE plm_des3_reg_lfsr_two_11_ ( + .PRE(plm_rst), + .CE(plm_des3_reg_lfsr_one32_i), + .C(mgt_clk), + .D(plm_des3_N_85392_i), + .Q(plm_des3_reg_lfsr_two_11__526) + ); + FDCE plm_des3_reg_lfsr_two_10_ ( + .CE(plm_des3_reg_lfsr_one32_i), + .C(mgt_clk), + .D(plm_des3_N_48875_i), + .Q(plm_des3_reg_lfsr_two_10__1042), + .CLR(plm_rst) + ); + FDCE plm_des3_reg_lfsr_two_9_ ( + .CE(plm_des3_reg_lfsr_one32_i), + .C(mgt_clk), + .D(plm_des3_N_9610_i), + .Q(plm_des3_reg_lfsr_two_9__1043), + .CLR(plm_rst) + ); + FDCE plm_des3_reg_lfsr_two_8_ ( + .CE(plm_des3_reg_lfsr_one32_i), + .C(mgt_clk), + .D(plm_des3_N_9611_i), + .Q(plm_des3_reg_lfsr_two_8__1044), + .CLR(plm_rst) + ); + FDCE plm_des3_reg_lfsr_two_7_ ( + .CE(plm_des3_reg_lfsr_one32_i), + .C(mgt_clk), + .D(plm_des3_N_9612_i), + .Q(plm_des3_reg_lfsr_two_7__1045), + .CLR(plm_rst) + ); + FDCE plm_des3_reg_lfsr_two_6_ ( + .CE(plm_des3_reg_lfsr_one32_i), + .C(mgt_clk), + .D(plm_des3_N_9613_i), + .Q(plm_des3_reg_lfsr_two_6__1046), + .CLR(plm_rst) + ); + FDCE plm_des3_reg_lfsr_two_5_ ( + .CE(plm_des3_reg_lfsr_one32_i), + .C(mgt_clk), + .D(plm_des3_N_9614_i), + .Q(plm_des3_reg_lfsr_two_5__1047), + .CLR(plm_rst) + ); + FDPE plm_des3_reg_lfsr_two_4_ ( + .PRE(plm_rst), + .CE(plm_des3_reg_lfsr_one32_i), + .C(mgt_clk), + .D(plm_des3_N_85391_i), + .Q(plm_des3_reg_lfsr_two_4__660) + ); + FDCE plm_des3_reg_lfsr_two_3_ ( + .CE(plm_des3_reg_lfsr_one32_i), + .C(mgt_clk), + .D(plm_des3_N_9616_i), + .Q(plm_des3_reg_lfsr_two_3__626), + .CLR(plm_rst) + ); + FDPE plm_des3_reg_lfsr_two_2_ ( + .PRE(plm_rst), + .CE(plm_des3_reg_lfsr_one32_i), + .C(mgt_clk), + .D(plm_des3_N_85390_i), + .Q(plm_des3_reg_lfsr_two_2__661) + ); + FDPE plm_des3_reg_lfsr_two_1_ ( + .PRE(plm_rst), + .CE(plm_des3_reg_lfsr_one32_i), + .C(mgt_clk), + .D(plm_des3_N_85389_i), + .Q(plm_des3_reg_lfsr_two_1__1048) + ); + FDPE plm_des3_reg_lfsr_two_0_ ( + .PRE(plm_rst), + .CE(plm_des3_reg_lfsr_one32_i), + .C(mgt_clk), + .D(plm_des3_N_85388_i), + .Q(plm_des3_reg_lfsr_two_0__525) + ); + defparam plm_scr0_scram_reg_tx_data_12_sn_m2.INIT = 4'h1; + LUT2 plm_scr0_scram_reg_tx_data_12_sn_m2 ( + .I0(plm_scr0_reg_dis[0]), + .I1(plm_scr0_reg_skp[1]), + .O(plm_scr0_reg_tx_data_12_sn_m2) + ); + defparam plm_scr0_un1_reg_com_1_i_o4.INIT = 4'h1; + LUT2 plm_scr0_un1_reg_com_1_i_o4 ( + .I0(plm_scr0_reg_skp[0]), + .I1(plm_scr0_reg_skp[1]), + .O(plm_scr0_N_21114_i) + ); + defparam plm_scr0_un1_reg_com_1_i_o2.INIT = 4'h1; + LUT2 plm_scr0_un1_reg_com_1_i_o2 ( + .I0(plm_scr0_reg_com[0]), + .I1(plm_scr0_reg_com[1]), + .O(plm_scr0_N_21117_i) + ); + defparam plm_scr0_one_adv2_1_15_.INIT = 4'h6; + LUT2 plm_scr0_one_adv2_1_15_ ( + .I0(plm_scr0_reg_lfsr_one_10__1067), + .I1(plm_scr0_reg_lfsr_one_11__644), + .O(plm_scr0_one_adv2_1_15__1049) + ); + defparam plm_scr0_one_adv2_1_13_.INIT = 4'h6; + LUT2 plm_scr0_one_adv2_1_13_ ( + .I0(plm_scr0_reg_lfsr_one_8__1069), + .I1(plm_scr0_reg_lfsr_one_9__1068), + .O(plm_scr0_one_adv2_1_13__1050) + ); + defparam plm_scr0_one_adv2_1_11_.INIT = 4'h6; + LUT2 plm_scr0_one_adv2_1_11_ ( + .I0(plm_scr0_reg_lfsr_one_6__1071), + .I1(plm_scr0_reg_lfsr_one_7__1070), + .O(plm_scr0_one_adv2_1_11__1051) + ); + defparam plm_scr0_one_adv2_1_9_.INIT = 4'h6; + LUT2 plm_scr0_one_adv2_1_9_ ( + .I0(plm_scr0_reg_lfsr_one_4__1073), + .I1(plm_scr0_reg_lfsr_one_5__1072), + .O(plm_scr0_one_adv2_1_9__1057) + ); + defparam plm_scr0_one_adv2_1_6_.INIT = 4'h6; + LUT2 plm_scr0_one_adv2_1_6_ ( + .I0(plm_scr0_reg_lfsr_one_1__569), + .I1(plm_scr0_reg_lfsr_one_12__1066), + .O(plm_scr0_one_adv2_1_6__1056) + ); + defparam plm_scr0_two_adv2_1_14_.INIT = 4'h6; + LUT2 plm_scr0_two_adv2_1_14_ ( + .I0(plm_scr0_reg_lfsr_two_9__1077), + .I1(plm_scr0_reg_lfsr_two_10__1076), + .O(plm_scr0_two_adv2_1_14__1052) + ); + defparam plm_scr0_two_adv2_1_12_.INIT = 4'h6; + LUT2 plm_scr0_two_adv2_1_12_ ( + .I0(plm_scr0_reg_lfsr_two_7__1079), + .I1(plm_scr0_reg_lfsr_two_8__1078), + .O(plm_scr0_two_adv2_1_12__1053) + ); + defparam plm_scr0_two_adv2_1_10_.INIT = 4'h6; + LUT2 plm_scr0_two_adv2_1_10_ ( + .I0(plm_scr0_reg_lfsr_two_5__1081), + .I1(plm_scr0_reg_lfsr_two_6__1080), + .O(plm_scr0_two_adv2_1_10__1058) + ); + defparam plm_scr0_two_adv2_1_7_.INIT = 4'h6; + LUT2 plm_scr0_two_adv2_1_7_ ( + .I0(plm_scr0_reg_lfsr_two_2__666), + .I1(plm_scr0_reg_lfsr_two_13__492), + .O(plm_scr0_two_adv2_1_7__1055) + ); + defparam plm_scr0_two_adv2_1_1_.INIT = 4'h6; + LUT2 plm_scr0_two_adv2_1_1_ ( + .I0(plm_scr0_reg_lfsr_two_12__1075), + .I1(plm_scr0_reg_lfsr_two_13__492), + .O(plm_scr0_two_adv2_1_1__1054) + ); + defparam plm_scr0_lfsrs_reg_lfsr_one32_i.INIT = 4'h7; + LUT2 plm_scr0_lfsrs_reg_lfsr_one32_i ( + .I0(plm_scr0_reg_skp[0]), + .I1(plm_scr0_reg_skp[1]), + .O(plm_scr0_reg_lfsr_one32_i) + ); + defparam plm_scr0_lfsrs_reg_lfsr_two_12_iv_i_o4_15_.INIT = 8'h23; + LUT3 plm_scr0_lfsrs_reg_lfsr_two_12_iv_i_o4_15_ ( + .I0(plm_scr0_reg_com[1]), + .I1(plm_scr0_reg_skp[0]), + .I2(plm_scr0_reg_skp[1]), + .O(plm_scr0_reg_lfsr_two_12_iv_i_o4_1[15]) + ); + defparam plm_scr0_lfsrs_reg_lfsr_two_12_iv_i_o2_15_.INIT = 8'h15; + LUT3 plm_scr0_lfsrs_reg_lfsr_two_12_iv_i_o2_15_ ( + .I0(plm_scr0_reg_com[0]), + .I1(plm_scr0_reg_com[1]), + .I2(plm_scr0_reg_skp[0]), + .O(plm_scr0_N_21115_i) + ); + defparam plm_scr0_two_adv2_15_.INIT = 16'h6996; + LUT4 plm_scr0_two_adv2_15_ ( + .I0(plm_scr0_reg_lfsr_two_10__1076), + .I1(plm_scr0_reg_lfsr_two_11__491), + .I2(plm_scr0_reg_lfsr_two_12__1075), + .I3(plm_scr0_reg_lfsr_two_15__493), + .O(plm_scr0_two_adv2_15__1060) + ); + defparam plm_scr0_one_adv2_1_.INIT = 8'h96; + LUT3 plm_scr0_one_adv2_1_ ( + .I0(plm_scr0_one_adv2_1_6__1056), + .I1(plm_scr0_reg_lfsr_one_13__573), + .I2(plm_scr0_reg_lfsr_one_14__688), + .O(plm_scr0_one_adv2[1]) + ); + defparam plm_scr0_two_adv2_12_.INIT = 8'h96; + LUT3 plm_scr0_two_adv2_12_ ( + .I0(plm_scr0_reg_lfsr_two_9__1077), + .I1(plm_scr0_reg_lfsr_two_12__1075), + .I2(plm_scr0_two_adv2_1_12__1053), + .O(plm_scr0_two_adv2_12__1061) + ); + defparam plm_scr0_two_adv2_10_.INIT = 8'h96; + LUT3 plm_scr0_two_adv2_10_ ( + .I0(plm_scr0_reg_lfsr_two_7__1079), + .I1(plm_scr0_reg_lfsr_two_10__1076), + .I2(plm_scr0_two_adv2_1_10__1058), + .O(plm_scr0_two_adv2_10__1062) + ); + defparam plm_scr0_one_adv2_15_.INIT = 8'h96; + LUT3 plm_scr0_one_adv2_15_ ( + .I0(plm_scr0_one_adv2_1_15__1049), + .I1(plm_scr0_reg_lfsr_one_12__1066), + .I2(plm_scr0_reg_lfsr_one_15__570), + .O(plm_scr0_one_adv2[15]) + ); + defparam plm_scr0_one_adv2_14_.INIT = 8'h96; + LUT3 plm_scr0_one_adv2_14_ ( + .I0(plm_scr0_one_adv2_1_15__1049), + .I1(plm_scr0_reg_lfsr_one_9__1068), + .I2(plm_scr0_reg_lfsr_one_14__688), + .O(plm_scr0_one_adv2[14]) + ); + defparam plm_scr0_one_adv2_13_.INIT = 8'h96; + LUT3 plm_scr0_one_adv2_13_ ( + .I0(plm_scr0_one_adv2_1_13__1050), + .I1(plm_scr0_reg_lfsr_one_10__1067), + .I2(plm_scr0_reg_lfsr_one_13__573), + .O(plm_scr0_one_adv2[13]) + ); + defparam plm_scr0_one_adv2_12_.INIT = 8'h96; + LUT3 plm_scr0_one_adv2_12_ ( + .I0(plm_scr0_one_adv2_1_13__1050), + .I1(plm_scr0_reg_lfsr_one_7__1070), + .I2(plm_scr0_reg_lfsr_one_12__1066), + .O(plm_scr0_one_adv2[12]) + ); + defparam plm_scr0_one_adv2_11_.INIT = 8'h96; + LUT3 plm_scr0_one_adv2_11_ ( + .I0(plm_scr0_one_adv2_1_11__1051), + .I1(plm_scr0_reg_lfsr_one_8__1069), + .I2(plm_scr0_reg_lfsr_one_11__644), + .O(plm_scr0_one_adv2[11]) + ); + defparam plm_scr0_one_adv2_10_.INIT = 8'h96; + LUT3 plm_scr0_one_adv2_10_ ( + .I0(plm_scr0_one_adv2_1_11__1051), + .I1(plm_scr0_reg_lfsr_one_5__1072), + .I2(plm_scr0_reg_lfsr_one_10__1067), + .O(plm_scr0_one_adv2[10]) + ); + defparam plm_scr0_one_adv2_2_.INIT = 16'h6996; + LUT4 plm_scr0_one_adv2_2_ ( + .I0(plm_scr0_reg_lfsr_one_2__1074), + .I1(plm_scr0_reg_lfsr_one_13__573), + .I2(plm_scr0_reg_lfsr_one_14__688), + .I3(plm_scr0_reg_lfsr_one_15__570), + .O(plm_scr0_one_adv2[2]) + ); + defparam plm_scr0_input_decoder_reg_skp_4_0_a2_1_4_0_.INIT = 16'h0080; + LUT4_L plm_scr0_input_decoder_reg_skp_4_0_a2_1_4_0_ ( + .I0(plm_scr0_reg_raw_char[2]), + .I1(plm_scr0_reg_raw_char[3]), + .I2(plm_scr0_reg_raw_char[4]), + .I3(plm_scr0_reg_raw_char[6]), + .LO(plm_scr0_reg_skp_4_0_a2_1_4[0]) + ); + defparam plm_scr0_input_decoder_reg_com_3_0_a2_1_4_1_.INIT = 16'h0080; + LUT4_L plm_scr0_input_decoder_reg_com_3_0_a2_1_4_1_ ( + .I0(plm_scr0_reg_raw_char[10]), + .I1(plm_scr0_reg_raw_char[11]), + .I2(plm_scr0_reg_raw_char[12]), + .I3(plm_scr0_reg_raw_char[14]), + .LO(plm_scr0_reg_com_3_0_a2_1_4[1]) + ); + defparam plm_scr0_two_adv2_1_4_.INIT = 16'h6996; + LUT4 plm_scr0_two_adv2_1_4_ ( + .I0(plm_scr0_reg_lfsr_two_0__490), + .I1(plm_scr0_reg_lfsr_two_1__665), + .I2(plm_scr0_reg_lfsr_two_11__491), + .I3(plm_scr0_reg_lfsr_two_14__683), + .O(plm_scr0_two_adv2_1_4__1059) + ); + defparam plm_scr0_one_adv2_0_.INIT = 8'h96; + LUT3 plm_scr0_one_adv2_0_ ( + .I0(N_12080_1), + .I1(plm_scr0_reg_lfsr_one_12__1066), + .I2(plm_scr0_reg_lfsr_one_13__573), + .O(plm_scr0_one_adv2[0]) + ); + defparam plm_scr0_lfsrs_reg_lfsr_two_12_iv_i_a2_15_.INIT = 4'h4; + LUT2_L plm_scr0_lfsrs_reg_lfsr_two_12_iv_i_a2_15_ ( + .I0(plm_scr0_reg_lfsr_two_12_iv_i_o4_1[15]), + .I1(plm_scr0_one_adv2[15]), + .LO(plm_scr0_reg_lfsr_two_12_iv_i_a2[15]) + ); + defparam plm_scr0_lfsrs_reg_lfsr_two_12_iv_i_a2_0_14_.INIT = 16'h8228; + LUT4 plm_scr0_lfsrs_reg_lfsr_two_12_iv_i_a2_0_14_ ( + .I0(plm_scr0_reg_lfsr_one29_0_a4), + .I1(plm_scr0_reg_lfsr_two_11__491), + .I2(plm_scr0_reg_lfsr_two_14__683), + .I3(plm_scr0_two_adv2_1_14__1052), + .O(plm_scr0_reg_lfsr_two_12_iv_i_a2_0_14_) + ); + defparam plm_scr0_lfsrs_reg_lfsr_two_12_iv_i_a2_0_13_.INIT = 16'h8228; + LUT4 plm_scr0_lfsrs_reg_lfsr_two_12_iv_i_a2_0_13_ ( + .I0(plm_scr0_reg_lfsr_one29_0_a4), + .I1(plm_scr0_reg_lfsr_two_8__1078), + .I2(plm_scr0_reg_lfsr_two_13__492), + .I3(plm_scr0_two_adv2_1_14__1052), + .O(plm_scr0_reg_lfsr_two_12_iv_i_a2_0_13_) + ); + defparam plm_scr0_lfsrs_reg_lfsr_two_12_iv_i_a2_0_11_.INIT = 16'h8228; + LUT4 plm_scr0_lfsrs_reg_lfsr_two_12_iv_i_a2_0_11_ ( + .I0(plm_scr0_reg_lfsr_one29_0_a4), + .I1(plm_scr0_reg_lfsr_two_6__1080), + .I2(plm_scr0_reg_lfsr_two_11__491), + .I3(plm_scr0_two_adv2_1_12__1053), + .O(plm_scr0_reg_lfsr_two_12_iv_i_a2_0_11_) + ); + defparam plm_scr0_lfsrs_reg_lfsr_two_12_iv_i_a2_0_2_.INIT = 16'h8228; + LUT4_L plm_scr0_lfsrs_reg_lfsr_two_12_iv_i_a2_0_2_ ( + .I0(plm_scr0_reg_lfsr_one29_0_a4), + .I1(plm_scr0_reg_lfsr_two_14__683), + .I2(plm_scr0_reg_lfsr_two_15__493), + .I3(plm_scr0_two_adv2_1_7__1055), + .LO(plm_scr0_reg_lfsr_two_12_iv_i_a2_0_2_) + ); + defparam plm_scr0_lfsrs_reg_lfsr_two_12_iv_i_a2_0_1_.INIT = 16'h8228; + LUT4 plm_scr0_lfsrs_reg_lfsr_two_12_iv_i_a2_0_1_ ( + .I0(plm_scr0_reg_lfsr_one29_0_a4), + .I1(plm_scr0_reg_lfsr_two_1__665), + .I2(plm_scr0_reg_lfsr_two_14__683), + .I3(plm_scr0_two_adv2_1_1__1054), + .O(plm_scr0_reg_lfsr_two_12_iv_i_a2_0_1_) + ); + defparam plm_scr0_lfsrs_reg_lfsr_two_12_iv_i_a2_0_0_.INIT = 16'h8228; + LUT4 plm_scr0_lfsrs_reg_lfsr_two_12_iv_i_a2_0_0_ ( + .I0(plm_scr0_reg_lfsr_one29_0_a4), + .I1(plm_scr0_reg_lfsr_two_0__490), + .I2(plm_scr0_reg_lfsr_two_11__491), + .I3(plm_scr0_two_adv2_1_1__1054), + .O(plm_scr0_reg_lfsr_two_12_iv_i_a2_0_0_) + ); + defparam plm_scr0_lfsrs_reg_lfsr_one_12_iv_i_a2_12_.INIT = 4'h4; + LUT2 plm_scr0_lfsrs_reg_lfsr_one_12_iv_i_a2_12_ ( + .I0(plm_scr0_reg_lfsr_two_12_iv_i_o4_1[15]), + .I1(plm_scr0_reg_lfsr_two_12__1075), + .O(plm_scr0_reg_lfsr_one_12_iv_i_a2_12_) + ); + defparam plm_scr0_lfsrs_reg_lfsr_one_12_iv_i_a2_0_10_.INIT = 4'h8; + LUT2_L plm_scr0_lfsrs_reg_lfsr_one_12_iv_i_a2_0_10_ ( + .I0(plm_scr0_reg_lfsr_one29_0_a4), + .I1(plm_scr0_one_adv2[10]), + .LO(plm_scr0_reg_lfsr_one_12_iv_i_a2_0_10_) + ); + defparam plm_scr0_lfsrs_reg_lfsr_one_12_iv_i_a2_7_.INIT = 4'h4; + LUT2 plm_scr0_lfsrs_reg_lfsr_one_12_iv_i_a2_7_ ( + .I0(plm_scr0_reg_lfsr_two_12_iv_i_o4_1[15]), + .I1(plm_scr0_reg_lfsr_two_7__1079), + .O(plm_scr0_reg_lfsr_one_12_iv_i_a2_7_) + ); + defparam plm_scr0_lfsrs_reg_lfsr_one_12_iv_i_a2_5_.INIT = 4'h4; + LUT2 plm_scr0_lfsrs_reg_lfsr_one_12_iv_i_a2_5_ ( + .I0(plm_scr0_reg_lfsr_two_12_iv_i_o4_1[15]), + .I1(plm_scr0_reg_lfsr_two_5__1081), + .O(plm_scr0_reg_lfsr_one_12_iv_i_a2_5_) + ); + defparam plm_scr0_lfsrs_reg_lfsr_one_12_iv_i_a2_3_.INIT = 4'h4; + LUT2 plm_scr0_lfsrs_reg_lfsr_one_12_iv_i_a2_3_ ( + .I0(plm_scr0_reg_lfsr_two_12_iv_i_o4_1[15]), + .I1(plm_scr0_reg_lfsr_two_3__682), + .O(plm_scr0_reg_lfsr_one_12_iv_i_a2_3_) + ); + defparam plm_scr0_two_adv2_7_.INIT = 16'h6996; + LUT4 plm_scr0_two_adv2_7_ ( + .I0(G_354_695), + .I1(plm_scr0_reg_lfsr_two_3__682), + .I2(plm_scr0_reg_lfsr_two_7__1079), + .I3(plm_scr0_two_adv2_1_7__1055), + .O(plm_scr0_two_adv2_7__1064) + ); + defparam plm_scr0_two_adv2_8_.INIT = 16'h6996; + LUT4 plm_scr0_two_adv2_8_ ( + .I0(G_410_684), + .I1(plm_scr0_reg_lfsr_two_4__694), + .I2(plm_scr0_reg_lfsr_two_5__1081), + .I3(plm_scr0_reg_lfsr_two_8__1078), + .O(plm_scr0_two_adv2_8__1063) + ); + defparam plm_scr0_one_adv2_6_.INIT = 16'h6996; + LUT4 plm_scr0_one_adv2_6_ ( + .I0(G_359_689), + .I1(plm_scr0_one_adv2_1_6__1056), + .I2(plm_scr0_reg_lfsr_one_2__1074), + .I3(plm_scr0_reg_lfsr_one_6__1071), + .O(plm_scr0_one_adv2[6]) + ); + defparam plm_scr0_one_adv2_7_.INIT = 16'h6996; + LUT4 plm_scr0_one_adv2_7_ ( + .I0(G_328_574), + .I1(plm_scr0_reg_lfsr_one_2__1074), + .I2(plm_scr0_reg_lfsr_one_4__1073), + .I3(plm_scr0_reg_lfsr_one_7__1070), + .O(plm_scr0_one_adv2[7]) + ); + defparam plm_scr0_one_adv2_9_.INIT = 16'h6996; + LUT4 plm_scr0_one_adv2_9_ ( + .I0(plm_scr0_one_adv2_1_9__1057), + .I1(plm_scr0_reg_lfsr_one_6__1071), + .I2(plm_scr0_reg_lfsr_one_9__1068), + .I3(plm_scr0_reg_lfsr_one_15__570), + .O(plm_scr0_one_adv2[9]) + ); + defparam plm_scr0_two_adv2_6_.INIT = 16'h6996; + LUT4 plm_scr0_two_adv2_6_ ( + .I0(G_410_684), + .I1(N_21118_i_0), + .I2(plm_scr0_reg_lfsr_two_6__1080), + .I3(plm_scr0_reg_lfsr_two_12__1075), + .O(plm_scr0_two_adv2_6__1065) + ); + defparam plm_scr0_one_adv2_8_.INIT = 8'h96; + LUT3 plm_scr0_one_adv2_8_ ( + .I0(G_359_689), + .I1(plm_scr0_one_adv2_1_9__1057), + .I2(plm_scr0_reg_lfsr_one_8__1069), + .O(plm_scr0_one_adv2[8]) + ); + defparam plm_scr0_one_adv2_5_.INIT = 16'h6996; + LUT4 plm_scr0_one_adv2_5_ ( + .I0(G_327_571), + .I1(plm_scr0_reg_lfsr_one_2__1074), + .I2(plm_scr0_reg_lfsr_one_5__1072), + .I3(plm_scr0_reg_lfsr_one_13__573), + .O(plm_scr0_one_adv2[5]) + ); + defparam plm_scr0_one_adv2_4_.INIT = 8'h96; + LUT3 plm_scr0_one_adv2_4_ ( + .I0(G_327_571), + .I1(plm_scr0_reg_lfsr_one_4__1073), + .I2(plm_scr0_reg_lfsr_one_14__688), + .O(plm_scr0_one_adv2[4]) + ); + defparam plm_scr0_input_decoder_reg_com_3_0_a2_1_1_.INIT = 16'h0200; + LUT4 plm_scr0_input_decoder_reg_com_3_0_a2_1_1_ ( + .I0(plm_scr0_reg_com_3_0_a2_1_4[1]), + .I1(plm_scr0_reg_raw_char[8]), + .I2(plm_scr0_reg_raw_char[9]), + .I3(plm_scr0_reg_raw_char_is_k[1]), + .O(plm_scr0_reg_com_3_1[1]) + ); + defparam plm_scr0_input_decoder_reg_skp_4_0_a2_1_0_.INIT = 16'h0200; + LUT4 plm_scr0_input_decoder_reg_skp_4_0_a2_1_0_ ( + .I0(plm_scr0_reg_skp_4_0_a2_1_4[0]), + .I1(plm_scr0_reg_raw_char[0]), + .I2(plm_scr0_reg_raw_char[1]), + .I3(plm_scr0_reg_raw_char_is_k[0]), + .O(plm_scr0_reg_skp_4_1[0]) + ); + defparam plm_scr0_lfsrs_reg_lfsr_two_12_iv_0_a2_0_9_.INIT = 16'h4884; + LUT4 plm_scr0_lfsrs_reg_lfsr_two_12_iv_0_a2_0_9_ ( + .I0(G_354_695), + .I1(plm_scr0_reg_lfsr_one29_0_a4), + .I2(plm_scr0_reg_lfsr_two_9__1077), + .I3(plm_scr0_two_adv2_1_10__1058), + .O(plm_scr0_reg_lfsr_two_12_iv_0_a2_0_9_) + ); + defparam plm_scr0_lfsrs_reg_lfsr_two_12_iv_0_a2_8_.INIT = 4'h1; + LUT2_L plm_scr0_lfsrs_reg_lfsr_two_12_iv_0_a2_8_ ( + .I0(plm_scr0_reg_lfsr_two_12_iv_i_o4_1[15]), + .I1(plm_scr0_one_adv2[8]), + .LO(plm_scr0_reg_lfsr_two_12_iv_0_a2[8]) + ); + defparam plm_scr0_lfsrs_reg_lfsr_two_12_iv_0_a2_0_5_.INIT = 16'h6090; + LUT4 plm_scr0_lfsrs_reg_lfsr_two_12_iv_0_a2_0_5_ ( + .I0(G_353_494), + .I1(N_21118_i_0), + .I2(plm_scr0_reg_lfsr_one29_0_a4), + .I3(plm_scr0_reg_lfsr_two_5__1081), + .O(plm_scr0_reg_lfsr_two_12_iv_0_a2_0_5_) + ); + defparam plm_scr0_lfsrs_reg_lfsr_two_12_iv_i_a2_0_4_.INIT = 8'h48; + LUT3 plm_scr0_lfsrs_reg_lfsr_two_12_iv_i_a2_0_4_ ( + .I0(G_354_695), + .I1(plm_scr0_reg_lfsr_one29_0_a4), + .I2(plm_scr0_two_adv2_1_4__1059), + .O(plm_scr0_reg_lfsr_two_12_iv_i_a2_0_4_) + ); + defparam plm_scr0_lfsrs_reg_lfsr_two_12_iv_0_a2_0_3_.INIT = 16'h6090; + LUT4 plm_scr0_lfsrs_reg_lfsr_two_12_iv_0_a2_0_3_ ( + .I0(G_353_494), + .I1(G_410_684), + .I2(plm_scr0_reg_lfsr_one29_0_a4), + .I3(plm_scr0_reg_lfsr_two_12__1075), + .O(plm_scr0_reg_lfsr_two_12_iv_0_a2_0_3_) + ); + defparam plm_scr0_lfsrs_reg_lfsr_one_12_iv_i_a2_0_9_.INIT = 4'h8; + LUT2_L plm_scr0_lfsrs_reg_lfsr_one_12_iv_i_a2_0_9_ ( + .I0(plm_scr0_reg_lfsr_one29_0_a4), + .I1(plm_scr0_one_adv2[9]), + .LO(plm_scr0_reg_lfsr_one_12_iv_i_a2_0_9_) + ); + defparam plm_scr0_lfsrs_reg_lfsr_one_12_iv_i_a2_0_8_.INIT = 4'h8; + LUT2_L plm_scr0_lfsrs_reg_lfsr_one_12_iv_i_a2_0_8_ ( + .I0(plm_scr0_reg_lfsr_one29_0_a4), + .I1(plm_scr0_one_adv2[8]), + .LO(plm_scr0_reg_lfsr_one_12_iv_i_a2_0_8_) + ); + defparam plm_scr0_lfsrs_reg_lfsr_one_12_iv_i_a2_0_6_.INIT = 4'h8; + LUT2_L plm_scr0_lfsrs_reg_lfsr_one_12_iv_i_a2_0_6_ ( + .I0(plm_scr0_reg_lfsr_one29_0_a4), + .I1(plm_scr0_one_adv2[6]), + .LO(plm_scr0_reg_lfsr_one_12_iv_i_a2_0_6_) + ); + defparam plm_scr0_scram_reg_tx_data_12_2_am_7_.INIT = 8'h9A; + LUT3 plm_scr0_scram_reg_tx_data_12_2_am_7_ ( + .I0(plm_scr0_reg_dat[7]), + .I1(plm_scr0_reg_dis[0]), + .I2(plm_scr0_reg_lfsr_one_8__1069), + .O(plm_scr0_reg_tx_data_12_2_am_2_7_) + ); + defparam plm_scr0_scram_reg_tx_data_12_2_bm_7_.INIT = 8'h36; + LUT3 plm_scr0_scram_reg_tx_data_12_2_bm_7_ ( + .I0(plm_scr0_reg_com[1]), + .I1(plm_scr0_reg_dat[7]), + .I2(plm_scr0_reg_lfsr_two_8__1078), + .O(plm_scr0_reg_tx_data_12_2_bm_2_7_) + ); + MUXF5 plm_scr0_scram_reg_tx_data_12_2_7_ ( + .I0(plm_scr0_reg_tx_data_12_2_am_2_7_), + .I1(plm_scr0_reg_tx_data_12_2_bm_2_7_), + .O(plm_scr0_reg_tx_data_12[7]), + .S(plm_scr0_reg_tx_data_12_sn_m2) + ); + defparam plm_scr0_scram_reg_tx_data_12_2_am_6_.INIT = 8'h9A; + LUT3 plm_scr0_scram_reg_tx_data_12_2_am_6_ ( + .I0(plm_scr0_reg_dat[6]), + .I1(plm_scr0_reg_dis[0]), + .I2(plm_scr0_reg_lfsr_one_9__1068), + .O(plm_scr0_reg_tx_data_12_2_am_1[6]) + ); + defparam plm_scr0_scram_reg_tx_data_12_2_bm_6_.INIT = 8'h36; + LUT3 plm_scr0_scram_reg_tx_data_12_2_bm_6_ ( + .I0(plm_scr0_reg_com[1]), + .I1(plm_scr0_reg_dat[6]), + .I2(plm_scr0_reg_lfsr_two_9__1077), + .O(plm_scr0_reg_tx_data_12_2_bm_1[6]) + ); + MUXF5 plm_scr0_scram_reg_tx_data_12_2_6_ ( + .I0(plm_scr0_reg_tx_data_12_2_am_1[6]), + .I1(plm_scr0_reg_tx_data_12_2_bm_1[6]), + .O(plm_scr0_reg_tx_data_12[6]), + .S(plm_scr0_reg_tx_data_12_sn_m2) + ); + defparam plm_scr0_scram_reg_tx_data_12_2_am_5_.INIT = 8'h9A; + LUT3 plm_scr0_scram_reg_tx_data_12_2_am_5_ ( + .I0(plm_scr0_reg_dat[5]), + .I1(plm_scr0_reg_dis[0]), + .I2(plm_scr0_reg_lfsr_one_10__1067), + .O(plm_scr0_reg_tx_data_12_2_am_1[5]) + ); + defparam plm_scr0_scram_reg_tx_data_12_2_bm_5_.INIT = 8'h36; + LUT3 plm_scr0_scram_reg_tx_data_12_2_bm_5_ ( + .I0(plm_scr0_reg_com[1]), + .I1(plm_scr0_reg_dat[5]), + .I2(plm_scr0_reg_lfsr_two_10__1076), + .O(plm_scr0_reg_tx_data_12_2_bm_1[5]) + ); + MUXF5 plm_scr0_scram_reg_tx_data_12_2_5_ ( + .I0(plm_scr0_reg_tx_data_12_2_am_1[5]), + .I1(plm_scr0_reg_tx_data_12_2_bm_1[5]), + .O(plm_scr0_reg_tx_data_12[5]), + .S(plm_scr0_reg_tx_data_12_sn_m2) + ); + defparam plm_scr0_scram_reg_tx_data_12_2_am_4_.INIT = 8'h9A; + LUT3 plm_scr0_scram_reg_tx_data_12_2_am_4_ ( + .I0(plm_scr0_reg_dat[4]), + .I1(plm_scr0_reg_dis[0]), + .I2(plm_scr0_reg_lfsr_one_11__644), + .O(plm_scr0_reg_tx_data_12_2_am_1[4]) + ); + defparam plm_scr0_scram_reg_tx_data_12_2_bm_4_.INIT = 8'h36; + LUT3 plm_scr0_scram_reg_tx_data_12_2_bm_4_ ( + .I0(plm_scr0_reg_com[1]), + .I1(plm_scr0_reg_dat[4]), + .I2(plm_scr0_reg_lfsr_two_11__491), + .O(plm_scr0_reg_tx_data_12_2_bm_1[4]) + ); + MUXF5 plm_scr0_scram_reg_tx_data_12_2_4_ ( + .I0(plm_scr0_reg_tx_data_12_2_am_1[4]), + .I1(plm_scr0_reg_tx_data_12_2_bm_1[4]), + .O(plm_scr0_reg_tx_data_12[4]), + .S(plm_scr0_reg_tx_data_12_sn_m2) + ); + defparam plm_scr0_scram_reg_tx_data_12_2_am_3_.INIT = 8'h9A; + LUT3 plm_scr0_scram_reg_tx_data_12_2_am_3_ ( + .I0(plm_scr0_reg_dat[3]), + .I1(plm_scr0_reg_dis[0]), + .I2(plm_scr0_reg_lfsr_one_12__1066), + .O(plm_scr0_reg_tx_data_12_2_am_1[3]) + ); + defparam plm_scr0_scram_reg_tx_data_12_2_bm_3_.INIT = 8'h36; + LUT3 plm_scr0_scram_reg_tx_data_12_2_bm_3_ ( + .I0(plm_scr0_reg_com[1]), + .I1(plm_scr0_reg_dat[3]), + .I2(plm_scr0_reg_lfsr_two_12__1075), + .O(plm_scr0_reg_tx_data_12_2_bm_1[3]) + ); + MUXF5 plm_scr0_scram_reg_tx_data_12_2_3_ ( + .I0(plm_scr0_reg_tx_data_12_2_am_1[3]), + .I1(plm_scr0_reg_tx_data_12_2_bm_1[3]), + .O(plm_scr0_reg_tx_data_12[3]), + .S(plm_scr0_reg_tx_data_12_sn_m2) + ); + defparam plm_scr0_scram_reg_tx_data_12_2_am_2_.INIT = 8'h9A; + LUT3 plm_scr0_scram_reg_tx_data_12_2_am_2_ ( + .I0(plm_scr0_reg_dat[2]), + .I1(plm_scr0_reg_dis[0]), + .I2(plm_scr0_reg_lfsr_one_13__573), + .O(plm_scr0_reg_tx_data_12_2_am_1[2]) + ); + defparam plm_scr0_scram_reg_tx_data_12_2_bm_2_.INIT = 8'h36; + LUT3 plm_scr0_scram_reg_tx_data_12_2_bm_2_ ( + .I0(plm_scr0_reg_com[1]), + .I1(plm_scr0_reg_dat[2]), + .I2(plm_scr0_reg_lfsr_two_13__492), + .O(plm_scr0_reg_tx_data_12_2_bm_1[2]) + ); + MUXF5 plm_scr0_scram_reg_tx_data_12_2_2_ ( + .I0(plm_scr0_reg_tx_data_12_2_am_1[2]), + .I1(plm_scr0_reg_tx_data_12_2_bm_1[2]), + .O(plm_scr0_reg_tx_data_12[2]), + .S(plm_scr0_reg_tx_data_12_sn_m2) + ); + defparam plm_scr0_scram_reg_tx_data_12_2_am_1_.INIT = 8'h9A; + LUT3 plm_scr0_scram_reg_tx_data_12_2_am_1_ ( + .I0(plm_scr0_reg_dat[1]), + .I1(plm_scr0_reg_dis[0]), + .I2(plm_scr0_reg_lfsr_one_14__688), + .O(plm_scr0_reg_tx_data_12_2_am_1[1]) + ); + defparam plm_scr0_scram_reg_tx_data_12_2_bm_1_.INIT = 8'h36; + LUT3 plm_scr0_scram_reg_tx_data_12_2_bm_1_ ( + .I0(plm_scr0_reg_com[1]), + .I1(plm_scr0_reg_dat[1]), + .I2(plm_scr0_reg_lfsr_two_14__683), + .O(plm_scr0_reg_tx_data_12_2_bm_1[1]) + ); + MUXF5 plm_scr0_scram_reg_tx_data_12_2_1_ ( + .I0(plm_scr0_reg_tx_data_12_2_am_1[1]), + .I1(plm_scr0_reg_tx_data_12_2_bm_1[1]), + .O(plm_scr0_reg_tx_data_12[1]), + .S(plm_scr0_reg_tx_data_12_sn_m2) + ); + defparam plm_scr0_scram_reg_tx_data_12_2_am_0_.INIT = 8'h9A; + LUT3 plm_scr0_scram_reg_tx_data_12_2_am_0_ ( + .I0(plm_scr0_reg_dat[0]), + .I1(plm_scr0_reg_dis[0]), + .I2(plm_scr0_reg_lfsr_one_15__570), + .O(plm_scr0_reg_tx_data_12_2_am_2_0_) + ); + defparam plm_scr0_scram_reg_tx_data_12_2_bm_0_.INIT = 8'h36; + LUT3 plm_scr0_scram_reg_tx_data_12_2_bm_0_ ( + .I0(plm_scr0_reg_com[1]), + .I1(plm_scr0_reg_dat[0]), + .I2(plm_scr0_reg_lfsr_two_15__493), + .O(plm_scr0_reg_tx_data_12_2_bm_2_0_) + ); + MUXF5 plm_scr0_scram_reg_tx_data_12_2_0_ ( + .I0(plm_scr0_reg_tx_data_12_2_am_2_0_), + .I1(plm_scr0_reg_tx_data_12_2_bm_2_0_), + .O(plm_scr0_reg_tx_data_12[0]), + .S(plm_scr0_reg_tx_data_12_sn_m2) + ); + defparam plm_scr0_one_adv2_3_.INIT = 16'h6996; + LUT4 plm_scr0_one_adv2_3_ ( + .I0(G_328_574), + .I1(N_12080_1), + .I2(plm_scr0_reg_lfsr_one_12__1066), + .I3(plm_scr0_reg_lfsr_one_14__688), + .O(plm_scr0_one_adv2[3]) + ); + defparam plm_scr0_one_adv2_i_m_4_.INIT = 8'h02; + LUT3 plm_scr0_one_adv2_i_m_4_ ( + .I0(plm_scr0_reg_lfsr_one29_0_a4), + .I1(plm_scr0_one_adv2[4]), + .I2(plm_scr0_reg_com[0]), + .O(plm_scr0_one_adv2_i_m[4]) + ); + defparam plm_scr0_input_decoder_reg_skp_4_0_a2_0_.INIT = 8'h02; + LUT3_L plm_scr0_input_decoder_reg_skp_4_0_a2_0_ ( + .I0(plm_scr0_reg_skp_4_1[0]), + .I1(plm_scr0_reg_raw_char[5]), + .I2(plm_scr0_reg_raw_char[7]), + .LO(plm_scr0_reg_skp_4[0]) + ); + defparam plm_scr0_input_decoder_reg_com_3_0_a2_1_.INIT = 8'h80; + LUT3_L plm_scr0_input_decoder_reg_com_3_0_a2_1_ ( + .I0(plm_scr0_reg_com_3_1[1]), + .I1(plm_scr0_reg_raw_char[13]), + .I2(plm_scr0_reg_raw_char[15]), + .LO(plm_scr0_reg_com_3[1]) + ); + defparam plm_scr0_input_decoder_reg_com_4_0_a2_0_.INIT = 8'h80; + LUT3_L plm_scr0_input_decoder_reg_com_4_0_a2_0_ ( + .I0(plm_scr0_reg_skp_4_1[0]), + .I1(plm_scr0_reg_raw_char[5]), + .I2(plm_scr0_reg_raw_char[7]), + .LO(plm_scr0_reg_com_4[0]) + ); + defparam plm_scr0_input_decoder_N_14358_i.INIT = 8'hFE; + LUT3_L plm_scr0_input_decoder_N_14358_i ( + .I0(plm_reg_disdes), + .I1(plm_scr0_reg_raw_char_is_k[1]), + .I2(plm_scr0_reg_raw_char_pass[1]), + .LO(plm_scr0_N_14358_i) + ); + defparam plm_scr0_input_decoder_N_14357_i.INIT = 8'hFE; + LUT3_L plm_scr0_input_decoder_N_14357_i ( + .I0(plm_reg_disdes), + .I1(plm_scr0_reg_raw_char_is_k[0]), + .I2(plm_scr0_reg_raw_char_pass[0]), + .LO(plm_scr0_N_14357_i) + ); + defparam plm_scr0_scram_reg_tx_data_6_0_13_.INIT = 8'h9A; + LUT3_L plm_scr0_scram_reg_tx_data_6_0_13_ ( + .I0(plm_scr0_reg_dat[13]), + .I1(plm_scr0_reg_dis[1]), + .I2(plm_scr0_reg_lfsr_one_10__1067), + .LO(plm_scr0_reg_tx_data_6[13]) + ); + defparam plm_scr0_scram_reg_tx_data_6_0_12_.INIT = 8'h9A; + LUT3_L plm_scr0_scram_reg_tx_data_6_0_12_ ( + .I0(plm_scr0_reg_dat[12]), + .I1(plm_scr0_reg_dis[1]), + .I2(plm_scr0_reg_lfsr_one_11__644), + .LO(plm_scr0_reg_tx_data_6[12]) + ); + defparam plm_scr0_scram_reg_tx_data_6_0_11_.INIT = 8'h9A; + LUT3_L plm_scr0_scram_reg_tx_data_6_0_11_ ( + .I0(plm_scr0_reg_dat[11]), + .I1(plm_scr0_reg_dis[1]), + .I2(plm_scr0_reg_lfsr_one_12__1066), + .LO(plm_scr0_reg_tx_data_6[11]) + ); + defparam plm_scr0_scram_reg_tx_data_6_0_10_.INIT = 8'h9A; + LUT3_L plm_scr0_scram_reg_tx_data_6_0_10_ ( + .I0(plm_scr0_reg_dat[10]), + .I1(plm_scr0_reg_dis[1]), + .I2(plm_scr0_reg_lfsr_one_13__573), + .LO(plm_scr0_reg_tx_data_6[10]) + ); + defparam plm_scr0_scram_reg_tx_data_6_0_9_.INIT = 8'h9A; + LUT3_L plm_scr0_scram_reg_tx_data_6_0_9_ ( + .I0(plm_scr0_reg_dat[9]), + .I1(plm_scr0_reg_dis[1]), + .I2(plm_scr0_reg_lfsr_one_14__688), + .LO(plm_scr0_reg_tx_data_6[9]) + ); + defparam plm_scr0_scram_reg_tx_data_6_0_8_.INIT = 8'h9A; + LUT3_L plm_scr0_scram_reg_tx_data_6_0_8_ ( + .I0(plm_scr0_reg_dat[8]), + .I1(plm_scr0_reg_dis[1]), + .I2(plm_scr0_reg_lfsr_one_15__570), + .LO(plm_scr0_reg_tx_data_6[8]) + ); + defparam plm_scr0_input_decoder_reg_skp_3_0_a2_1_.INIT = 8'h02; + LUT3_L plm_scr0_input_decoder_reg_skp_3_0_a2_1_ ( + .I0(plm_scr0_reg_com_3_1[1]), + .I1(plm_scr0_reg_raw_char[13]), + .I2(plm_scr0_reg_raw_char[15]), + .LO(plm_scr0_reg_skp_3[1]) + ); + defparam plm_scr0_scram_reg_tx_data_6_0_15_.INIT = 8'h9A; + LUT3_L plm_scr0_scram_reg_tx_data_6_0_15_ ( + .I0(plm_scr0_reg_dat[15]), + .I1(plm_scr0_reg_dis[1]), + .I2(plm_scr0_reg_lfsr_one_8__1069), + .LO(plm_scr0_reg_tx_data_6[15]) + ); + defparam plm_scr0_scram_reg_tx_data_6_0_14_.INIT = 8'h9A; + LUT3_L plm_scr0_scram_reg_tx_data_6_0_14_ ( + .I0(plm_scr0_reg_dat[14]), + .I1(plm_scr0_reg_dis[1]), + .I2(plm_scr0_reg_lfsr_one_9__1068), + .LO(plm_scr0_reg_tx_data_6[14]) + ); + defparam plm_scr0_lfsrs_N_87816_i.INIT = 16'hF7B3; + LUT4_L plm_scr0_lfsrs_N_87816_i ( + .I0(plm_scr0_N_21114_i), + .I1(plm_scr0_N_21117_i), + .I2(plm_scr0_one_adv2[15]), + .I3(plm_scr0_reg_lfsr_two_15__493), + .LO(plm_scr0_N_87816_i) + ); + defparam plm_scr0_lfsrs_N_87815_i.INIT = 16'hF7B3; + LUT4_L plm_scr0_lfsrs_N_87815_i ( + .I0(plm_scr0_N_21114_i), + .I1(plm_scr0_N_21117_i), + .I2(plm_scr0_one_adv2[14]), + .I3(plm_scr0_reg_lfsr_two_14__683), + .LO(plm_scr0_N_87815_i) + ); + defparam plm_scr0_lfsrs_N_87814_i.INIT = 16'hF7B3; + LUT4_L plm_scr0_lfsrs_N_87814_i ( + .I0(plm_scr0_N_21114_i), + .I1(plm_scr0_N_21117_i), + .I2(plm_scr0_one_adv2[13]), + .I3(plm_scr0_reg_lfsr_two_13__492), + .LO(plm_scr0_N_87814_i) + ); + defparam plm_scr0_lfsrs_N_85423_i.INIT = 16'hFDDD; + LUT4_L plm_scr0_lfsrs_N_85423_i ( + .I0(plm_scr0_N_21115_i), + .I1(plm_scr0_reg_lfsr_one_12_iv_i_a2_12_), + .I2(plm_scr0_reg_lfsr_one29_0_a4), + .I3(plm_scr0_one_adv2[12]), + .LO(plm_scr0_N_85423_i) + ); + defparam plm_scr0_lfsrs_N_87813_i.INIT = 16'hF7B3; + LUT4_L plm_scr0_lfsrs_N_87813_i ( + .I0(plm_scr0_N_21114_i), + .I1(plm_scr0_N_21117_i), + .I2(plm_scr0_one_adv2[11]), + .I3(plm_scr0_reg_lfsr_two_11__491), + .LO(plm_scr0_N_87813_i) + ); + defparam plm_scr0_lfsrs_N_85422_i.INIT = 16'hDFDD; + LUT4_L plm_scr0_lfsrs_N_85422_i ( + .I0(plm_scr0_N_21115_i), + .I1(plm_scr0_reg_lfsr_one_12_iv_i_a2_0_10_), + .I2(plm_scr0_reg_lfsr_two_12_iv_i_o4_1[15]), + .I3(plm_scr0_reg_lfsr_two_10__1076), + .LO(plm_scr0_N_85422_i) + ); + defparam plm_scr0_lfsrs_N_85421_i.INIT = 16'hDFDD; + LUT4_L plm_scr0_lfsrs_N_85421_i ( + .I0(plm_scr0_N_21115_i), + .I1(plm_scr0_reg_lfsr_one_12_iv_i_a2_0_9_), + .I2(plm_scr0_reg_lfsr_two_12_iv_i_o4_1[15]), + .I3(plm_scr0_reg_lfsr_two_9__1077), + .LO(plm_scr0_N_85421_i) + ); + defparam plm_scr0_lfsrs_N_85420_i.INIT = 16'hDFDD; + LUT4_L plm_scr0_lfsrs_N_85420_i ( + .I0(plm_scr0_N_21115_i), + .I1(plm_scr0_reg_lfsr_one_12_iv_i_a2_0_8_), + .I2(plm_scr0_reg_lfsr_two_12_iv_i_o4_1[15]), + .I3(plm_scr0_reg_lfsr_two_8__1078), + .LO(plm_scr0_N_85420_i) + ); + defparam plm_scr0_lfsrs_N_85419_i.INIT = 16'hFDDD; + LUT4_L plm_scr0_lfsrs_N_85419_i ( + .I0(plm_scr0_N_21115_i), + .I1(plm_scr0_reg_lfsr_one_12_iv_i_a2_7_), + .I2(plm_scr0_reg_lfsr_one29_0_a4), + .I3(plm_scr0_one_adv2[7]), + .LO(plm_scr0_N_85419_i) + ); + defparam plm_scr0_lfsrs_N_85418_i.INIT = 16'hDFDD; + LUT4_L plm_scr0_lfsrs_N_85418_i ( + .I0(plm_scr0_N_21115_i), + .I1(plm_scr0_reg_lfsr_one_12_iv_i_a2_0_6_), + .I2(plm_scr0_reg_lfsr_two_12_iv_i_o4_1[15]), + .I3(plm_scr0_reg_lfsr_two_6__1080), + .LO(plm_scr0_N_85418_i) + ); + defparam plm_scr0_lfsrs_N_85417_i.INIT = 16'hFDDD; + LUT4_L plm_scr0_lfsrs_N_85417_i ( + .I0(plm_scr0_N_21115_i), + .I1(plm_scr0_reg_lfsr_one_12_iv_i_a2_5_), + .I2(plm_scr0_reg_lfsr_one29_0_a4), + .I3(plm_scr0_one_adv2[5]), + .LO(plm_scr0_N_85417_i) + ); + defparam plm_scr0_lfsrs_reg_lfsr_one_12_0_iv_4_.INIT = 16'h0F0B; + LUT4_L plm_scr0_lfsrs_reg_lfsr_one_12_0_iv_4_ ( + .I0(plm_scr0_N_21114_i), + .I1(plm_scr0_N_21117_i), + .I2(plm_scr0_one_adv2_i_m[4]), + .I3(plm_scr0_reg_lfsr_two_4__694), + .LO(plm_scr0_reg_lfsr_one_12[4]) + ); + defparam plm_scr0_lfsrs_N_85416_i.INIT = 16'hFDDD; + LUT4_L plm_scr0_lfsrs_N_85416_i ( + .I0(plm_scr0_N_21115_i), + .I1(plm_scr0_reg_lfsr_one_12_iv_i_a2_3_), + .I2(plm_scr0_reg_lfsr_one29_0_a4), + .I3(plm_scr0_one_adv2[3]), + .LO(plm_scr0_N_85416_i) + ); + defparam plm_scr0_lfsrs_N_87812_i.INIT = 16'hF7B3; + LUT4_L plm_scr0_lfsrs_N_87812_i ( + .I0(plm_scr0_N_21114_i), + .I1(plm_scr0_N_21117_i), + .I2(plm_scr0_one_adv2[2]), + .I3(plm_scr0_reg_lfsr_two_2__666), + .LO(plm_scr0_N_87812_i) + ); + defparam plm_scr0_lfsrs_N_87811_i.INIT = 16'hF7B3; + LUT4_L plm_scr0_lfsrs_N_87811_i ( + .I0(plm_scr0_N_21114_i), + .I1(plm_scr0_N_21117_i), + .I2(plm_scr0_one_adv2[1]), + .I3(plm_scr0_reg_lfsr_two_1__665), + .LO(plm_scr0_N_87811_i) + ); + defparam plm_scr0_lfsrs_N_87810_i.INIT = 16'hF7B3; + LUT4_L plm_scr0_lfsrs_N_87810_i ( + .I0(plm_scr0_N_21114_i), + .I1(plm_scr0_N_21117_i), + .I2(plm_scr0_one_adv2[0]), + .I3(plm_scr0_reg_lfsr_two_0__490), + .LO(plm_scr0_N_87810_i) + ); + defparam plm_scr0_lfsrs_N_85435_i.INIT = 16'hFDDD; + LUT4_L plm_scr0_lfsrs_N_85435_i ( + .I0(plm_scr0_N_21115_i), + .I1(plm_scr0_reg_lfsr_two_12_iv_i_a2[15]), + .I2(plm_scr0_reg_lfsr_one29_0_a4), + .I3(plm_scr0_two_adv2_15__1060), + .LO(plm_scr0_N_85435_i) + ); + defparam plm_scr0_lfsrs_N_85434_i.INIT = 16'hDFDD; + LUT4_L plm_scr0_lfsrs_N_85434_i ( + .I0(plm_scr0_N_21115_i), + .I1(plm_scr0_reg_lfsr_two_12_iv_i_a2_0_14_), + .I2(plm_scr0_reg_lfsr_two_12_iv_i_o4_1[15]), + .I3(plm_scr0_one_adv2[14]), + .LO(plm_scr0_N_85434_i) + ); + defparam plm_scr0_lfsrs_N_85433_i.INIT = 16'hDFDD; + LUT4_L plm_scr0_lfsrs_N_85433_i ( + .I0(plm_scr0_N_21115_i), + .I1(plm_scr0_reg_lfsr_two_12_iv_i_a2_0_13_), + .I2(plm_scr0_reg_lfsr_two_12_iv_i_o4_1[15]), + .I3(plm_scr0_one_adv2[13]), + .LO(plm_scr0_N_85433_i) + ); + defparam plm_scr0_lfsrs_reg_lfsr_two_12_0_iv_0_12_.INIT = 16'hC840; + LUT4_L plm_scr0_lfsrs_reg_lfsr_two_12_0_iv_0_12_ ( + .I0(plm_scr0_N_21114_i), + .I1(plm_scr0_N_21117_i), + .I2(plm_scr0_one_adv2[12]), + .I3(plm_scr0_two_adv2_12__1061), + .LO(plm_scr0_N_9639_i) + ); + defparam plm_scr0_lfsrs_N_85432_i.INIT = 16'hDFDD; + LUT4_L plm_scr0_lfsrs_N_85432_i ( + .I0(plm_scr0_N_21115_i), + .I1(plm_scr0_reg_lfsr_two_12_iv_i_a2_0_11_), + .I2(plm_scr0_reg_lfsr_two_12_iv_i_o4_1[15]), + .I3(plm_scr0_one_adv2[11]), + .LO(plm_scr0_N_85432_i) + ); + defparam plm_scr0_lfsrs_reg_lfsr_two_12_0_iv_0_10_.INIT = 16'hC840; + LUT4_L plm_scr0_lfsrs_reg_lfsr_two_12_0_iv_0_10_ ( + .I0(plm_scr0_N_21114_i), + .I1(plm_scr0_N_21117_i), + .I2(plm_scr0_one_adv2[10]), + .I3(plm_scr0_two_adv2_10__1062), + .LO(plm_scr0_N_9641_i) + ); + defparam plm_scr0_lfsrs_reg_lfsr_two_12_iv_0_9_.INIT = 16'h2220; + LUT4_L plm_scr0_lfsrs_reg_lfsr_two_12_iv_0_9_ ( + .I0(plm_scr0_N_21115_i), + .I1(plm_scr0_reg_lfsr_two_12_iv_0_a2_0_9_), + .I2(plm_scr0_reg_lfsr_two_12_iv_i_o4_1[15]), + .I3(plm_scr0_one_adv2[9]), + .LO(plm_scr0_N_9642_i) + ); + defparam plm_scr0_lfsrs_reg_lfsr_two_12_iv_0_8_.INIT = 16'h2202; + LUT4_L plm_scr0_lfsrs_reg_lfsr_two_12_iv_0_8_ ( + .I0(plm_scr0_N_21115_i), + .I1(plm_scr0_reg_lfsr_two_12_iv_0_a2[8]), + .I2(plm_scr0_reg_lfsr_one29_0_a4), + .I3(plm_scr0_two_adv2_8__1063), + .LO(plm_scr0_N_9643_i) + ); + defparam plm_scr0_lfsrs_reg_lfsr_two_12_0_iv_0_7_.INIT = 16'hC840; + LUT4_L plm_scr0_lfsrs_reg_lfsr_two_12_0_iv_0_7_ ( + .I0(plm_scr0_N_21114_i), + .I1(plm_scr0_N_21117_i), + .I2(plm_scr0_one_adv2[7]), + .I3(plm_scr0_two_adv2_7__1064), + .LO(plm_scr0_N_9644_i) + ); + defparam plm_scr0_lfsrs_reg_lfsr_two_12_0_iv_0_6_.INIT = 16'hC840; + LUT4_L plm_scr0_lfsrs_reg_lfsr_two_12_0_iv_0_6_ ( + .I0(plm_scr0_N_21114_i), + .I1(plm_scr0_N_21117_i), + .I2(plm_scr0_one_adv2[6]), + .I3(plm_scr0_two_adv2_6__1065), + .LO(plm_scr0_N_9645_i) + ); + defparam plm_scr0_lfsrs_reg_lfsr_two_12_iv_0_5_.INIT = 16'h2220; + LUT4_L plm_scr0_lfsrs_reg_lfsr_two_12_iv_0_5_ ( + .I0(plm_scr0_N_21115_i), + .I1(plm_scr0_reg_lfsr_two_12_iv_0_a2_0_5_), + .I2(plm_scr0_reg_lfsr_two_12_iv_i_o4_1[15]), + .I3(plm_scr0_one_adv2[5]), + .LO(plm_scr0_N_9646_i) + ); + defparam plm_scr0_lfsrs_N_85428_i.INIT = 16'hDFDD; + LUT4_L plm_scr0_lfsrs_N_85428_i ( + .I0(plm_scr0_N_21115_i), + .I1(plm_scr0_reg_lfsr_two_12_iv_i_a2_0_4_), + .I2(plm_scr0_reg_lfsr_two_12_iv_i_o4_1[15]), + .I3(plm_scr0_one_adv2[4]), + .LO(plm_scr0_N_85428_i) + ); + defparam plm_scr0_lfsrs_reg_lfsr_two_12_iv_0_3_.INIT = 16'h2220; + LUT4_L plm_scr0_lfsrs_reg_lfsr_two_12_iv_0_3_ ( + .I0(plm_scr0_N_21115_i), + .I1(plm_scr0_reg_lfsr_two_12_iv_0_a2_0_3_), + .I2(plm_scr0_reg_lfsr_two_12_iv_i_o4_1[15]), + .I3(plm_scr0_one_adv2[3]), + .LO(plm_scr0_N_9648_i) + ); + defparam plm_scr0_lfsrs_N_85426_i.INIT = 16'hDFDD; + LUT4_L plm_scr0_lfsrs_N_85426_i ( + .I0(plm_scr0_N_21115_i), + .I1(plm_scr0_reg_lfsr_two_12_iv_i_a2_0_2_), + .I2(plm_scr0_reg_lfsr_two_12_iv_i_o4_1[15]), + .I3(plm_scr0_one_adv2[2]), + .LO(plm_scr0_N_85426_i) + ); + defparam plm_scr0_lfsrs_N_85425_i.INIT = 16'hDFDD; + LUT4_L plm_scr0_lfsrs_N_85425_i ( + .I0(plm_scr0_N_21115_i), + .I1(plm_scr0_reg_lfsr_two_12_iv_i_a2_0_1_), + .I2(plm_scr0_reg_lfsr_two_12_iv_i_o4_1[15]), + .I3(plm_scr0_one_adv2[1]), + .LO(plm_scr0_N_85425_i) + ); + defparam plm_scr0_lfsrs_N_85424_i.INIT = 16'hDFDD; + LUT4_L plm_scr0_lfsrs_N_85424_i ( + .I0(plm_scr0_N_21115_i), + .I1(plm_scr0_reg_lfsr_two_12_iv_i_a2_0_0_), + .I2(plm_scr0_reg_lfsr_two_12_iv_i_o4_1[15]), + .I3(plm_scr0_one_adv2[0]), + .LO(plm_scr0_N_85424_i) + ); + defparam plm_scr0_lfsrs_reg_lfsr_one29_0_a4.INIT = 8'h01; + LUT3 plm_scr0_lfsrs_reg_lfsr_one29_0_a4 ( + .I0(plm_scr0_reg_com[1]), + .I1(plm_scr0_reg_skp[1]), + .I2(plm_scr0_reg_skp[0]), + .O(plm_scr0_reg_lfsr_one29_0_a4) + ); + FDC plm_scr0_reg_skp_0_ ( + .C(mgt_clk), + .D(plm_scr0_reg_skp_4[0]), + .Q(plm_scr0_reg_skp[0]), + .CLR(plm_rst) + ); + FDC plm_scr0_reg_com_1_ ( + .C(mgt_clk), + .D(plm_scr0_reg_com_3[1]), + .Q(plm_scr0_reg_com[1]), + .CLR(plm_rst) + ); + FDC plm_scr0_reg_com_0_ ( + .C(mgt_clk), + .D(plm_scr0_reg_com_4[0]), + .Q(plm_scr0_reg_com[0]), + .CLR(plm_rst) + ); + FDC plm_scr0_reg_dis_1_ ( + .C(mgt_clk), + .D(plm_scr0_N_14358_i), + .Q(plm_scr0_reg_dis[1]), + .CLR(plm_rst) + ); + FDC plm_scr0_reg_dis_0_ ( + .C(mgt_clk), + .D(plm_scr0_N_14357_i), + .Q(plm_scr0_reg_dis[0]), + .CLR(plm_rst) + ); + FDC plm_scr0_reg_tx_data_13_ ( + .C(mgt_clk), + .D(plm_scr0_reg_tx_data_6[13]), + .Q(plm_tx0_data[13]), + .CLR(plm_rst) + ); + FDC plm_scr0_reg_tx_data_12_ ( + .C(mgt_clk), + .D(plm_scr0_reg_tx_data_6[12]), + .Q(plm_tx0_data[12]), + .CLR(plm_rst) + ); + FDC plm_scr0_reg_tx_data_11_ ( + .C(mgt_clk), + .D(plm_scr0_reg_tx_data_6[11]), + .Q(plm_tx0_data[11]), + .CLR(plm_rst) + ); + FDC plm_scr0_reg_tx_data_10_ ( + .C(mgt_clk), + .D(plm_scr0_reg_tx_data_6[10]), + .Q(plm_tx0_data[10]), + .CLR(plm_rst) + ); + FDC plm_scr0_reg_tx_data_9_ ( + .C(mgt_clk), + .D(plm_scr0_reg_tx_data_6[9]), + .Q(plm_tx0_data[9]), + .CLR(plm_rst) + ); + FDC plm_scr0_reg_tx_data_8_ ( + .C(mgt_clk), + .D(plm_scr0_reg_tx_data_6[8]), + .Q(plm_tx0_data[8]), + .CLR(plm_rst) + ); + FDC plm_scr0_reg_tx_data_7_ ( + .C(mgt_clk), + .D(plm_scr0_reg_tx_data_12[7]), + .Q(plm_tx0_data[7]), + .CLR(plm_rst) + ); + FDC plm_scr0_reg_tx_data_6_ ( + .C(mgt_clk), + .D(plm_scr0_reg_tx_data_12[6]), + .Q(plm_tx0_data[6]), + .CLR(plm_rst) + ); + FDC plm_scr0_reg_tx_data_5_ ( + .C(mgt_clk), + .D(plm_scr0_reg_tx_data_12[5]), + .Q(plm_tx0_data[5]), + .CLR(plm_rst) + ); + FDC plm_scr0_reg_tx_data_4_ ( + .C(mgt_clk), + .D(plm_scr0_reg_tx_data_12[4]), + .Q(plm_tx0_data[4]), + .CLR(plm_rst) + ); + FDC plm_scr0_reg_tx_data_3_ ( + .C(mgt_clk), + .D(plm_scr0_reg_tx_data_12[3]), + .Q(plm_tx0_data[3]), + .CLR(plm_rst) + ); + FDC plm_scr0_reg_tx_data_2_ ( + .C(mgt_clk), + .D(plm_scr0_reg_tx_data_12[2]), + .Q(plm_tx0_data[2]), + .CLR(plm_rst) + ); + FDC plm_scr0_reg_tx_data_1_ ( + .C(mgt_clk), + .D(plm_scr0_reg_tx_data_12[1]), + .Q(plm_tx0_data[1]), + .CLR(plm_rst) + ); + FDC plm_scr0_reg_tx_data_0_ ( + .C(mgt_clk), + .D(plm_scr0_reg_tx_data_12[0]), + .Q(plm_tx0_data[0]), + .CLR(plm_rst) + ); + FDC plm_scr0_reg_skp_1_ ( + .C(mgt_clk), + .D(plm_scr0_reg_skp_3[1]), + .Q(plm_scr0_reg_skp[1]), + .CLR(plm_rst) + ); + FDC plm_scr0_reg_dat_8_ ( + .C(mgt_clk), + .D(plm_scr0_reg_raw_char[8]), + .Q(plm_scr0_reg_dat[8]), + .CLR(plm_rst) + ); + FDC plm_scr0_reg_dat_7_ ( + .C(mgt_clk), + .D(plm_scr0_reg_raw_char[7]), + .Q(plm_scr0_reg_dat[7]), + .CLR(plm_rst) + ); + FDC plm_scr0_reg_dat_6_ ( + .C(mgt_clk), + .D(plm_scr0_reg_raw_char[6]), + .Q(plm_scr0_reg_dat[6]), + .CLR(plm_rst) + ); + FDC plm_scr0_reg_dat_5_ ( + .C(mgt_clk), + .D(plm_scr0_reg_raw_char[5]), + .Q(plm_scr0_reg_dat[5]), + .CLR(plm_rst) + ); + FDC plm_scr0_reg_dat_4_ ( + .C(mgt_clk), + .D(plm_scr0_reg_raw_char[4]), + .Q(plm_scr0_reg_dat[4]), + .CLR(plm_rst) + ); + FDC plm_scr0_reg_dat_3_ ( + .C(mgt_clk), + .D(plm_scr0_reg_raw_char[3]), + .Q(plm_scr0_reg_dat[3]), + .CLR(plm_rst) + ); + FDC plm_scr0_reg_dat_2_ ( + .C(mgt_clk), + .D(plm_scr0_reg_raw_char[2]), + .Q(plm_scr0_reg_dat[2]), + .CLR(plm_rst) + ); + FDC plm_scr0_reg_dat_1_ ( + .C(mgt_clk), + .D(plm_scr0_reg_raw_char[1]), + .Q(plm_scr0_reg_dat[1]), + .CLR(plm_rst) + ); + FDC plm_scr0_reg_dat_0_ ( + .C(mgt_clk), + .D(plm_scr0_reg_raw_char[0]), + .Q(plm_scr0_reg_dat[0]), + .CLR(plm_rst) + ); + FDC plm_scr0_reg_kkk_1_ ( + .C(mgt_clk), + .D(plm_scr0_reg_raw_char_is_k[1]), + .Q(plm_scr0_reg_kkk[1]), + .CLR(plm_rst) + ); + FDC plm_scr0_reg_kkk_0_ ( + .C(mgt_clk), + .D(plm_scr0_reg_raw_char_is_k[0]), + .Q(plm_scr0_reg_kkk[0]), + .CLR(plm_rst) + ); + FDC plm_scr0_reg_tx_char_is_k_1_ ( + .C(mgt_clk), + .D(plm_scr0_reg_kkk[1]), + .Q(plm_tx0_char_is_k[1]), + .CLR(plm_rst) + ); + FDC plm_scr0_reg_tx_char_is_k_0_ ( + .C(mgt_clk), + .D(plm_scr0_reg_kkk[0]), + .Q(plm_tx0_char_is_k[0]), + .CLR(plm_rst) + ); + FDC plm_scr0_reg_tx_data_15_ ( + .C(mgt_clk), + .D(plm_scr0_reg_tx_data_6[15]), + .Q(plm_tx0_data[15]), + .CLR(plm_rst) + ); + FDC plm_scr0_reg_tx_data_14_ ( + .C(mgt_clk), + .D(plm_scr0_reg_tx_data_6[14]), + .Q(plm_tx0_data[14]), + .CLR(plm_rst) + ); + FDC plm_scr0_reg_dat_15_ ( + .C(mgt_clk), + .D(plm_scr0_reg_raw_char[15]), + .Q(plm_scr0_reg_dat[15]), + .CLR(plm_rst) + ); + FDC plm_scr0_reg_dat_14_ ( + .C(mgt_clk), + .D(plm_scr0_reg_raw_char[14]), + .Q(plm_scr0_reg_dat[14]), + .CLR(plm_rst) + ); + FDC plm_scr0_reg_dat_13_ ( + .C(mgt_clk), + .D(plm_scr0_reg_raw_char[13]), + .Q(plm_scr0_reg_dat[13]), + .CLR(plm_rst) + ); + FDC plm_scr0_reg_dat_12_ ( + .C(mgt_clk), + .D(plm_scr0_reg_raw_char[12]), + .Q(plm_scr0_reg_dat[12]), + .CLR(plm_rst) + ); + FDC plm_scr0_reg_dat_11_ ( + .C(mgt_clk), + .D(plm_scr0_reg_raw_char[11]), + .Q(plm_scr0_reg_dat[11]), + .CLR(plm_rst) + ); + FDC plm_scr0_reg_dat_10_ ( + .C(mgt_clk), + .D(plm_scr0_reg_raw_char[10]), + .Q(plm_scr0_reg_dat[10]), + .CLR(plm_rst) + ); + FDC plm_scr0_reg_dat_9_ ( + .C(mgt_clk), + .D(plm_scr0_reg_raw_char[9]), + .Q(plm_scr0_reg_dat[9]), + .CLR(plm_rst) + ); + FDC plm_scr0_reg_raw_char_is_k_0_ ( + .C(mgt_clk), + .D(plm_tx0_raw_char_is_k[0]), + .Q(plm_scr0_reg_raw_char_is_k[0]), + .CLR(plm_rst) + ); + FDC plm_scr0_reg_raw_char_11_ ( + .C(mgt_clk), + .D(plm_tx0_raw_char[11]), + .Q(plm_scr0_reg_raw_char[11]), + .CLR(plm_rst) + ); + FDC plm_scr0_reg_raw_char_10_ ( + .C(mgt_clk), + .D(plm_tx0_raw_char[10]), + .Q(plm_scr0_reg_raw_char[10]), + .CLR(plm_rst) + ); + FDC plm_scr0_reg_raw_char_9_ ( + .C(mgt_clk), + .D(plm_tx0_raw_char[9]), + .Q(plm_scr0_reg_raw_char[9]), + .CLR(plm_rst) + ); + FDC plm_scr0_reg_raw_char_8_ ( + .C(mgt_clk), + .D(plm_tx0_raw_char[8]), + .Q(plm_scr0_reg_raw_char[8]), + .CLR(plm_rst) + ); + FDC plm_scr0_reg_raw_char_7_ ( + .C(mgt_clk), + .D(plm_tx0_raw_char[7]), + .Q(plm_scr0_reg_raw_char[7]), + .CLR(plm_rst) + ); + FDC plm_scr0_reg_raw_char_6_ ( + .C(mgt_clk), + .D(plm_tx0_raw_char[6]), + .Q(plm_scr0_reg_raw_char[6]), + .CLR(plm_rst) + ); + FDC plm_scr0_reg_raw_char_5_ ( + .C(mgt_clk), + .D(plm_tx0_raw_char[5]), + .Q(plm_scr0_reg_raw_char[5]), + .CLR(plm_rst) + ); + FDC plm_scr0_reg_raw_char_4_ ( + .C(mgt_clk), + .D(plm_tx0_raw_char[4]), + .Q(plm_scr0_reg_raw_char[4]), + .CLR(plm_rst) + ); + FDC plm_scr0_reg_raw_char_3_ ( + .C(mgt_clk), + .D(plm_tx0_raw_char[3]), + .Q(plm_scr0_reg_raw_char[3]), + .CLR(plm_rst) + ); + FDC plm_scr0_reg_raw_char_2_ ( + .C(mgt_clk), + .D(plm_tx0_raw_char[2]), + .Q(plm_scr0_reg_raw_char[2]), + .CLR(plm_rst) + ); + FDC plm_scr0_reg_raw_char_1_ ( + .C(mgt_clk), + .D(plm_tx0_raw_char[1]), + .Q(plm_scr0_reg_raw_char[1]), + .CLR(plm_rst) + ); + FDC plm_scr0_reg_raw_char_0_ ( + .C(mgt_clk), + .D(plm_tx0_raw_char[0]), + .Q(plm_scr0_reg_raw_char[0]), + .CLR(plm_rst) + ); + FDC plm_scr0_reg_raw_char_pass_1_ ( + .C(mgt_clk), + .D(plm_tx0_raw_char_pass[1]), + .Q(plm_scr0_reg_raw_char_pass[1]), + .CLR(plm_rst) + ); + FDC plm_scr0_reg_raw_char_pass_0_ ( + .C(mgt_clk), + .D(plm_tx0_raw_char_pass[0]), + .Q(plm_scr0_reg_raw_char_pass[0]), + .CLR(plm_rst) + ); + FDC plm_scr0_reg_raw_char_is_k_1_ ( + .C(mgt_clk), + .D(plm_tx0_raw_char_is_k[1]), + .Q(plm_scr0_reg_raw_char_is_k[1]), + .CLR(plm_rst) + ); + FDC plm_scr0_reg_raw_char_15_ ( + .C(mgt_clk), + .D(plm_tx0_raw_char[15]), + .Q(plm_scr0_reg_raw_char[15]), + .CLR(plm_rst) + ); + FDC plm_scr0_reg_raw_char_14_ ( + .C(mgt_clk), + .D(plm_tx0_raw_char[14]), + .Q(plm_scr0_reg_raw_char[14]), + .CLR(plm_rst) + ); + FDC plm_scr0_reg_raw_char_13_ ( + .C(mgt_clk), + .D(plm_tx0_raw_char[13]), + .Q(plm_scr0_reg_raw_char[13]), + .CLR(plm_rst) + ); + FDC plm_scr0_reg_raw_char_12_ ( + .C(mgt_clk), + .D(plm_tx0_raw_char[12]), + .Q(plm_scr0_reg_raw_char[12]), + .CLR(plm_rst) + ); + FDPE plm_scr0_reg_lfsr_one_15_ ( + .PRE(plm_rst), + .CE(plm_scr0_reg_lfsr_one32_i), + .C(mgt_clk), + .D(plm_scr0_N_87816_i), + .Q(plm_scr0_reg_lfsr_one_15__570) + ); + FDPE plm_scr0_reg_lfsr_one_14_ ( + .PRE(plm_rst), + .CE(plm_scr0_reg_lfsr_one32_i), + .C(mgt_clk), + .D(plm_scr0_N_87815_i), + .Q(plm_scr0_reg_lfsr_one_14__688) + ); + FDPE plm_scr0_reg_lfsr_one_13_ ( + .PRE(plm_rst), + .CE(plm_scr0_reg_lfsr_one32_i), + .C(mgt_clk), + .D(plm_scr0_N_87814_i), + .Q(plm_scr0_reg_lfsr_one_13__573) + ); + FDPE plm_scr0_reg_lfsr_one_12_ ( + .PRE(plm_rst), + .CE(plm_scr0_reg_lfsr_one32_i), + .C(mgt_clk), + .D(plm_scr0_N_85423_i), + .Q(plm_scr0_reg_lfsr_one_12__1066) + ); + FDPE plm_scr0_reg_lfsr_one_11_ ( + .PRE(plm_rst), + .CE(plm_scr0_reg_lfsr_one32_i), + .C(mgt_clk), + .D(plm_scr0_N_87813_i), + .Q(plm_scr0_reg_lfsr_one_11__644) + ); + FDPE plm_scr0_reg_lfsr_one_10_ ( + .PRE(plm_rst), + .CE(plm_scr0_reg_lfsr_one32_i), + .C(mgt_clk), + .D(plm_scr0_N_85422_i), + .Q(plm_scr0_reg_lfsr_one_10__1067) + ); + FDPE plm_scr0_reg_lfsr_one_9_ ( + .PRE(plm_rst), + .CE(plm_scr0_reg_lfsr_one32_i), + .C(mgt_clk), + .D(plm_scr0_N_85421_i), + .Q(plm_scr0_reg_lfsr_one_9__1068) + ); + FDPE plm_scr0_reg_lfsr_one_8_ ( + .PRE(plm_rst), + .CE(plm_scr0_reg_lfsr_one32_i), + .C(mgt_clk), + .D(plm_scr0_N_85420_i), + .Q(plm_scr0_reg_lfsr_one_8__1069) + ); + FDPE plm_scr0_reg_lfsr_one_7_ ( + .PRE(plm_rst), + .CE(plm_scr0_reg_lfsr_one32_i), + .C(mgt_clk), + .D(plm_scr0_N_85419_i), + .Q(plm_scr0_reg_lfsr_one_7__1070) + ); + FDPE plm_scr0_reg_lfsr_one_6_ ( + .PRE(plm_rst), + .CE(plm_scr0_reg_lfsr_one32_i), + .C(mgt_clk), + .D(plm_scr0_N_85418_i), + .Q(plm_scr0_reg_lfsr_one_6__1071) + ); + FDPE plm_scr0_reg_lfsr_one_5_ ( + .PRE(plm_rst), + .CE(plm_scr0_reg_lfsr_one32_i), + .C(mgt_clk), + .D(plm_scr0_N_85417_i), + .Q(plm_scr0_reg_lfsr_one_5__1072) + ); + FDPE plm_scr0_reg_lfsr_one_4_ ( + .PRE(plm_rst), + .CE(plm_scr0_reg_lfsr_one32_i), + .C(mgt_clk), + .D(plm_scr0_reg_lfsr_one_12[4]), + .Q(plm_scr0_reg_lfsr_one_4__1073) + ); + FDPE plm_scr0_reg_lfsr_one_3_ ( + .PRE(plm_rst), + .CE(plm_scr0_reg_lfsr_one32_i), + .C(mgt_clk), + .D(plm_scr0_N_85416_i), + .Q(plm_scr0_reg_lfsr_one_3__572) + ); + FDPE plm_scr0_reg_lfsr_one_2_ ( + .PRE(plm_rst), + .CE(plm_scr0_reg_lfsr_one32_i), + .C(mgt_clk), + .D(plm_scr0_N_87812_i), + .Q(plm_scr0_reg_lfsr_one_2__1074) + ); + FDPE plm_scr0_reg_lfsr_one_1_ ( + .PRE(plm_rst), + .CE(plm_scr0_reg_lfsr_one32_i), + .C(mgt_clk), + .D(plm_scr0_N_87811_i), + .Q(plm_scr0_reg_lfsr_one_1__569) + ); + FDPE plm_scr0_reg_lfsr_one_0_ ( + .PRE(plm_rst), + .CE(plm_scr0_reg_lfsr_one32_i), + .C(mgt_clk), + .D(plm_scr0_N_87810_i), + .Q(plm_scr0_reg_lfsr_one_0__643) + ); + FDPE plm_scr0_reg_lfsr_two_15_ ( + .PRE(plm_rst), + .CE(plm_scr0_reg_lfsr_one32_i), + .C(mgt_clk), + .D(plm_scr0_N_85435_i), + .Q(plm_scr0_reg_lfsr_two_15__493) + ); + FDPE plm_scr0_reg_lfsr_two_14_ ( + .PRE(plm_rst), + .CE(plm_scr0_reg_lfsr_one32_i), + .C(mgt_clk), + .D(plm_scr0_N_85434_i), + .Q(plm_scr0_reg_lfsr_two_14__683) + ); + FDPE plm_scr0_reg_lfsr_two_13_ ( + .PRE(plm_rst), + .CE(plm_scr0_reg_lfsr_one32_i), + .C(mgt_clk), + .D(plm_scr0_N_85433_i), + .Q(plm_scr0_reg_lfsr_two_13__492) + ); + FDCE plm_scr0_reg_lfsr_two_12_ ( + .CE(plm_scr0_reg_lfsr_one32_i), + .C(mgt_clk), + .D(plm_scr0_N_9639_i), + .Q(plm_scr0_reg_lfsr_two_12__1075), + .CLR(plm_rst) + ); + FDPE plm_scr0_reg_lfsr_two_11_ ( + .PRE(plm_rst), + .CE(plm_scr0_reg_lfsr_one32_i), + .C(mgt_clk), + .D(plm_scr0_N_85432_i), + .Q(plm_scr0_reg_lfsr_two_11__491) + ); + FDCE plm_scr0_reg_lfsr_two_10_ ( + .CE(plm_scr0_reg_lfsr_one32_i), + .C(mgt_clk), + .D(plm_scr0_N_9641_i), + .Q(plm_scr0_reg_lfsr_two_10__1076), + .CLR(plm_rst) + ); + FDCE plm_scr0_reg_lfsr_two_9_ ( + .CE(plm_scr0_reg_lfsr_one32_i), + .C(mgt_clk), + .D(plm_scr0_N_9642_i), + .Q(plm_scr0_reg_lfsr_two_9__1077), + .CLR(plm_rst) + ); + FDCE plm_scr0_reg_lfsr_two_8_ ( + .CE(plm_scr0_reg_lfsr_one32_i), + .C(mgt_clk), + .D(plm_scr0_N_9643_i), + .Q(plm_scr0_reg_lfsr_two_8__1078), + .CLR(plm_rst) + ); + FDCE plm_scr0_reg_lfsr_two_7_ ( + .CE(plm_scr0_reg_lfsr_one32_i), + .C(mgt_clk), + .D(plm_scr0_N_9644_i), + .Q(plm_scr0_reg_lfsr_two_7__1079), + .CLR(plm_rst) + ); + FDCE plm_scr0_reg_lfsr_two_6_ ( + .CE(plm_scr0_reg_lfsr_one32_i), + .C(mgt_clk), + .D(plm_scr0_N_9645_i), + .Q(plm_scr0_reg_lfsr_two_6__1080), + .CLR(plm_rst) + ); + FDCE plm_scr0_reg_lfsr_two_5_ ( + .CE(plm_scr0_reg_lfsr_one32_i), + .C(mgt_clk), + .D(plm_scr0_N_9646_i), + .Q(plm_scr0_reg_lfsr_two_5__1081), + .CLR(plm_rst) + ); + FDPE plm_scr0_reg_lfsr_two_4_ ( + .PRE(plm_rst), + .CE(plm_scr0_reg_lfsr_one32_i), + .C(mgt_clk), + .D(plm_scr0_N_85428_i), + .Q(plm_scr0_reg_lfsr_two_4__694) + ); + FDCE plm_scr0_reg_lfsr_two_3_ ( + .CE(plm_scr0_reg_lfsr_one32_i), + .C(mgt_clk), + .D(plm_scr0_N_9648_i), + .Q(plm_scr0_reg_lfsr_two_3__682), + .CLR(plm_rst) + ); + FDPE plm_scr0_reg_lfsr_two_2_ ( + .PRE(plm_rst), + .CE(plm_scr0_reg_lfsr_one32_i), + .C(mgt_clk), + .D(plm_scr0_N_85426_i), + .Q(plm_scr0_reg_lfsr_two_2__666) + ); + FDPE plm_scr0_reg_lfsr_two_1_ ( + .PRE(plm_rst), + .CE(plm_scr0_reg_lfsr_one32_i), + .C(mgt_clk), + .D(plm_scr0_N_85425_i), + .Q(plm_scr0_reg_lfsr_two_1__665) + ); + FDPE plm_scr0_reg_lfsr_two_0_ ( + .PRE(plm_rst), + .CE(plm_scr0_reg_lfsr_one32_i), + .C(mgt_clk), + .D(plm_scr0_N_85424_i), + .Q(plm_scr0_reg_lfsr_two_0__490) + ); + defparam plm_scr1_scram_reg_tx_data_12_sn_m2.INIT = 4'h1; + LUT2 plm_scr1_scram_reg_tx_data_12_sn_m2 ( + .I0(plm_reg_dis_6103[0]), + .I1(plm_scr1_reg_skp[1]), + .O(plm_scr1_reg_tx_data_12_sn_m2_0) + ); + defparam plm_scr1_one_adv2_1_15_.INIT = 4'h6; + LUT2 plm_scr1_one_adv2_1_15_ ( + .I0(plm_scr1_reg_lfsr_one_10__1120), + .I1(plm_scr1_reg_lfsr_one_11__101), + .O(plm_scr1_one_adv2_1_15__1084) + ); + defparam plm_scr1_one_adv2_1_13_.INIT = 4'h6; + LUT2 plm_scr1_one_adv2_1_13_ ( + .I0(plm_scr1_reg_lfsr_one_8__1122), + .I1(plm_scr1_reg_lfsr_one_9__1121), + .O(plm_scr1_one_adv2_1_13__1082) + ); + defparam plm_scr1_one_adv2_1_11_.INIT = 4'h6; + LUT2 plm_scr1_one_adv2_1_11_ ( + .I0(plm_scr1_reg_lfsr_one_6__1124), + .I1(plm_scr1_reg_lfsr_one_7__1123), + .O(plm_scr1_one_adv2_1_11__1083) + ); + defparam plm_scr1_one_adv2_1_9_.INIT = 4'h6; + LUT2 plm_scr1_one_adv2_1_9_ ( + .I0(plm_scr1_reg_lfsr_one_4__1126), + .I1(plm_scr1_reg_lfsr_one_5__1125), + .O(plm_scr1_one_adv2_1_9__1091) + ); + defparam plm_scr1_one_adv2_1_6_.INIT = 4'h6; + LUT2 plm_scr1_one_adv2_1_6_ ( + .I0(plm_scr1_reg_lfsr_one_1__507), + .I1(plm_scr1_reg_lfsr_one_12__100), + .O(plm_scr1_one_adv2_1_6__1090) + ); + defparam plm_scr1_one_adv2_1_5_.INIT = 4'h6; + LUT2 plm_scr1_one_adv2_1_5_ ( + .I0(plm_scr1_reg_lfsr_one_2__1127), + .I1(plm_scr1_reg_lfsr_one_13__511), + .O(plm_scr1_one_adv2_1_5__1092) + ); + defparam plm_scr1_two_adv2_1_14_.INIT = 4'h6; + LUT2 plm_scr1_two_adv2_1_14_ ( + .I0(plm_scr1_reg_lfsr_two_9__1130), + .I1(plm_scr1_reg_lfsr_two_10__1129), + .O(plm_scr1_two_adv2_1_14__1087) + ); + defparam plm_scr1_two_adv2_1_12_.INIT = 4'h6; + LUT2 plm_scr1_two_adv2_1_12_ ( + .I0(plm_scr1_reg_lfsr_two_7__1132), + .I1(plm_scr1_reg_lfsr_two_8__1131), + .O(plm_scr1_two_adv2_1_12__1086) + ); + defparam plm_scr1_two_adv2_1_10_.INIT = 4'h6; + LUT2 plm_scr1_two_adv2_1_10_ ( + .I0(plm_scr1_reg_lfsr_two_5__1134), + .I1(plm_scr1_reg_lfsr_two_6__1133), + .O(plm_scr1_two_adv2_1_10__1094) + ); + defparam plm_scr1_two_adv2_1_7_.INIT = 4'h6; + LUT2 plm_scr1_two_adv2_1_7_ ( + .I0(plm_scr1_reg_lfsr_two_2__680), + .I1(plm_scr1_reg_lfsr_two_13__535), + .O(plm_scr1_two_adv2_1_7__1089) + ); + defparam plm_scr1_two_adv2_1_1_.INIT = 4'h6; + LUT2 plm_scr1_two_adv2_1_1_ ( + .I0(plm_scr1_reg_lfsr_two_12__1128), + .I1(plm_scr1_reg_lfsr_two_13__535), + .O(plm_scr1_two_adv2_1_1__1085) + ); + defparam plm_scr1_two_adv2_0_15_.INIT = 4'h6; + LUT2 plm_scr1_two_adv2_0_15_ ( + .I0(plm_scr1_reg_lfsr_two_10__1129), + .I1(plm_scr1_reg_lfsr_two_15__536), + .O(plm_scr1_two_adv2_0_15__1088) + ); + defparam plm_scr1_two_adv2_0_4_.INIT = 4'h6; + LUT2 plm_scr1_two_adv2_0_4_ ( + .I0(plm_scr1_reg_lfsr_two_0__633), + .I1(plm_scr1_reg_lfsr_two_1__679), + .O(plm_scr1_two_adv2_0_4__1093) + ); + defparam plm_scr1_un1_reg_lfsr_one37.INIT = 8'h15; + LUT3 plm_scr1_un1_reg_lfsr_one37 ( + .I0(plm_scr1_reg_com[0]), + .I1(plm_scr1_reg_com[1]), + .I2(plm_scr1_reg_skp[0]), + .O(plm_scr1_un1_reg_lfsr_one37_i) + ); + defparam plm_scr1_lfsrs_reg_lfsr_one32_i.INIT = 4'h7; + LUT2 plm_scr1_lfsrs_reg_lfsr_one32_i ( + .I0(plm_scr1_reg_skp[0]), + .I1(plm_scr1_reg_skp[1]), + .O(plm_scr1_reg_lfsr_one32_i) + ); + defparam plm_scr1_lfsrs_reg_lfsr_one29.INIT = 16'h0001; + LUT4 plm_scr1_lfsrs_reg_lfsr_one29 ( + .I0(plm_scr1_reg_com[0]), + .I1(plm_scr1_reg_com[1]), + .I2(plm_scr1_reg_skp[0]), + .I3(plm_scr1_reg_skp[1]), + .O(plm_scr1_reg_lfsr_one29) + ); + defparam plm_scr1_un1_reg_com_1.INIT = 16'h1110; + LUT4 plm_scr1_un1_reg_com_1 ( + .I0(plm_scr1_reg_com[0]), + .I1(plm_scr1_reg_com[1]), + .I2(plm_scr1_reg_skp[0]), + .I3(plm_scr1_reg_skp[1]), + .O(plm_scr1_un1_reg_com_1_1118) + ); + defparam plm_scr1_two_adv2_12_.INIT = 8'h96; + LUT3 plm_scr1_two_adv2_12_ ( + .I0(plm_scr1_reg_lfsr_two_9__1130), + .I1(plm_scr1_reg_lfsr_two_12__1128), + .I2(plm_scr1_two_adv2_1_12__1086), + .O(plm_scr1_two_adv2_12__1105) + ); + defparam plm_scr1_two_adv2_10_.INIT = 8'h96; + LUT3 plm_scr1_two_adv2_10_ ( + .I0(plm_scr1_reg_lfsr_two_7__1132), + .I1(plm_scr1_reg_lfsr_two_10__1129), + .I2(plm_scr1_two_adv2_1_10__1094), + .O(plm_scr1_two_adv2_10__1107) + ); + defparam plm_scr1_one_adv2_14_.INIT = 8'h96; + LUT3 plm_scr1_one_adv2_14_ ( + .I0(plm_scr1_one_adv2_1_15__1084), + .I1(plm_scr1_reg_lfsr_one_9__1121), + .I2(plm_scr1_reg_lfsr_one_14__690), + .O(plm_scr1_one_adv2[14]) + ); + defparam plm_scr1_one_adv2_13_.INIT = 8'h96; + LUT3 plm_scr1_one_adv2_13_ ( + .I0(plm_scr1_one_adv2_1_13__1082), + .I1(plm_scr1_reg_lfsr_one_10__1120), + .I2(plm_scr1_reg_lfsr_one_13__511), + .O(plm_scr1_one_adv2[13]) + ); + defparam plm_scr1_one_adv2_12_.INIT = 8'h96; + LUT3 plm_scr1_one_adv2_12_ ( + .I0(plm_scr1_one_adv2_1_13__1082), + .I1(plm_scr1_reg_lfsr_one_7__1123), + .I2(plm_scr1_reg_lfsr_one_12__100), + .O(plm_scr1_one_adv2[12]) + ); + defparam plm_scr1_one_adv2_11_.INIT = 8'h96; + LUT3 plm_scr1_one_adv2_11_ ( + .I0(plm_scr1_one_adv2_1_11__1083), + .I1(plm_scr1_reg_lfsr_one_8__1122), + .I2(plm_scr1_reg_lfsr_one_11__101), + .O(plm_scr1_one_adv2[11]) + ); + defparam plm_scr1_one_adv2_10_.INIT = 8'h96; + LUT3 plm_scr1_one_adv2_10_ ( + .I0(plm_scr1_one_adv2_1_11__1083), + .I1(plm_scr1_reg_lfsr_one_5__1125), + .I2(plm_scr1_reg_lfsr_one_10__1120), + .O(plm_scr1_one_adv2[10]) + ); + defparam plm_scr1_one_adv2_2_.INIT = 8'h96; + LUT3 plm_scr1_one_adv2_2_ ( + .I0(plm_scr1_one_adv2_1_5__1092), + .I1(plm_scr1_reg_lfsr_one_14__690), + .I2(plm_scr1_reg_lfsr_one_15__508), + .O(plm_scr1_one_adv2[2]) + ); + defparam plm_scr1_one_adv2_1_.INIT = 8'h96; + LUT3 plm_scr1_one_adv2_1_ ( + .I0(plm_scr1_one_adv2_1_6__1090), + .I1(plm_scr1_reg_lfsr_one_13__511), + .I2(plm_scr1_reg_lfsr_one_14__690), + .O(plm_scr1_one_adv2[1]) + ); + defparam plm_scr1_one_adv2_15_.INIT = 8'h96; + LUT3 plm_scr1_one_adv2_15_ ( + .I0(plm_scr1_one_adv2_1_15__1084), + .I1(plm_scr1_reg_lfsr_one_12__100), + .I2(plm_scr1_reg_lfsr_one_15__508), + .O(plm_scr1_one_adv2[15]) + ); + defparam plm_scr1_un1_reg_skp_2.INIT = 8'h04; + LUT3 plm_scr1_un1_reg_skp_2 ( + .I0(plm_scr1_reg_com[0]), + .I1(plm_scr1_reg_com[1]), + .I2(plm_scr1_reg_skp[0]), + .O(plm_scr1_un1_reg_skp_2_1114) + ); + defparam plm_scr1_input_decoder_reg_com_4_0_a2_1_4_0_.INIT = 16'h0080; + LUT4_L plm_scr1_input_decoder_reg_com_4_0_a2_1_4_0_ ( + .I0(plm_scr1_reg_raw_char[2]), + .I1(plm_scr1_reg_raw_char[3]), + .I2(plm_scr1_reg_raw_char[4]), + .I3(plm_scr1_reg_raw_char[6]), + .LO(plm_scr1_reg_com_4_0_a2_1_4[0]) + ); + defparam plm_scr1_input_decoder_reg_com_3_0_a2_1_4_1_.INIT = 16'h0080; + LUT4_L plm_scr1_input_decoder_reg_com_3_0_a2_1_4_1_ ( + .I0(plm_scr1_reg_raw_char[10]), + .I1(plm_scr1_reg_raw_char[11]), + .I2(plm_scr1_reg_raw_char[12]), + .I3(plm_scr1_reg_raw_char[14]), + .LO(plm_scr1_reg_com_3_0_a2_1_4[1]) + ); + defparam plm_scr1_reg_lfsr_two_m_5_.INIT = 4'h8; + LUT2 plm_scr1_reg_lfsr_two_m_5_ ( + .I0(plm_scr1_reg_lfsr_two_5__1134), + .I1(plm_scr1_un1_reg_com_1_1118), + .O(plm_scr1_reg_lfsr_two_m[5]) + ); + defparam plm_scr1_one_adv2_m_10_.INIT = 4'h8; + LUT2 plm_scr1_one_adv2_m_10_ ( + .I0(plm_scr1_reg_lfsr_one29), + .I1(plm_scr1_one_adv2[10]), + .O(plm_scr1_one_adv2_m_10__1096) + ); + defparam plm_scr1_one_adv2_m_12_.INIT = 4'h8; + LUT2 plm_scr1_one_adv2_m_12_ ( + .I0(plm_scr1_reg_lfsr_one29), + .I1(plm_scr1_one_adv2[12]), + .O(plm_scr1_one_adv2_m_12__1095) + ); + defparam plm_scr1_two_adv2_m_0_.INIT = 8'h48; + LUT3 plm_scr1_two_adv2_m_0_ ( + .I0(N_12001_1), + .I1(plm_scr1_reg_lfsr_one29), + .I2(plm_scr1_two_adv2_1_1__1085), + .O(plm_scr1_two_adv2_m_0__1119) + ); + defparam plm_scr1_two_adv2_m_1_.INIT = 16'h8228; + LUT4 plm_scr1_two_adv2_m_1_ ( + .I0(plm_scr1_reg_lfsr_one29), + .I1(plm_scr1_reg_lfsr_two_1__679), + .I2(plm_scr1_reg_lfsr_two_14__676), + .I3(plm_scr1_two_adv2_1_1__1085), + .O(plm_scr1_two_adv2_m_1__1117) + ); + defparam plm_scr1_two_adv2_m_2_.INIT = 16'h8228; + LUT4 plm_scr1_two_adv2_m_2_ ( + .I0(plm_scr1_reg_lfsr_one29), + .I1(plm_scr1_reg_lfsr_two_14__676), + .I2(plm_scr1_reg_lfsr_two_15__536), + .I3(plm_scr1_two_adv2_1_7__1089), + .O(plm_scr1_two_adv2_m_2__1116) + ); + defparam plm_scr1_two_adv2_m_11_.INIT = 16'h8228; + LUT4 plm_scr1_two_adv2_m_11_ ( + .I0(plm_scr1_reg_lfsr_one29), + .I1(plm_scr1_reg_lfsr_two_6__1133), + .I2(plm_scr1_reg_lfsr_two_11__634), + .I3(plm_scr1_two_adv2_1_12__1086), + .O(plm_scr1_two_adv2_m_11__1106) + ); + defparam plm_scr1_two_adv2_m_13_.INIT = 16'h8228; + LUT4 plm_scr1_two_adv2_m_13_ ( + .I0(plm_scr1_reg_lfsr_one29), + .I1(plm_scr1_reg_lfsr_two_8__1131), + .I2(plm_scr1_reg_lfsr_two_13__535), + .I3(plm_scr1_two_adv2_1_14__1087), + .O(plm_scr1_two_adv2_m_13__1104) + ); + defparam plm_scr1_two_adv2_m_14_.INIT = 8'h48; + LUT3 plm_scr1_two_adv2_m_14_ ( + .I0(G_500_677), + .I1(plm_scr1_reg_lfsr_one29), + .I2(plm_scr1_two_adv2_1_14__1087), + .O(plm_scr1_two_adv2_m_14__1103) + ); + defparam plm_scr1_two_adv2_m_15_.INIT = 16'h8228; + LUT4 plm_scr1_two_adv2_m_15_ ( + .I0(plm_scr1_reg_lfsr_one29), + .I1(plm_scr1_reg_lfsr_two_11__634), + .I2(plm_scr1_reg_lfsr_two_12__1128), + .I3(plm_scr1_two_adv2_0_15__1088), + .O(plm_scr1_two_adv2_m_15__1102) + ); + defparam plm_scr1_one_adv2_0_.INIT = 4'h6; + LUT2 plm_scr1_one_adv2_0_ ( + .I0(G_417_103), + .I1(plm_scr1_reg_lfsr_one_13__511), + .O(plm_scr1_one_adv2[0]) + ); + defparam plm_scr1_two_adv2_7_.INIT = 16'h6996; + LUT4 plm_scr1_two_adv2_7_ ( + .I0(G_344_697), + .I1(plm_scr1_reg_lfsr_two_3__686), + .I2(plm_scr1_reg_lfsr_two_7__1132), + .I3(plm_scr1_two_adv2_1_7__1089), + .O(plm_scr1_two_adv2_7__1110) + ); + defparam plm_scr1_two_adv2_8_.INIT = 16'h6996; + LUT4 plm_scr1_two_adv2_8_ ( + .I0(G_366_687), + .I1(plm_scr1_reg_lfsr_two_4__696), + .I2(plm_scr1_reg_lfsr_two_5__1134), + .I3(plm_scr1_reg_lfsr_two_8__1131), + .O(plm_scr1_two_adv2_8__1109) + ); + defparam plm_scr1_one_adv2_6_.INIT = 16'h6996; + LUT4 plm_scr1_one_adv2_6_ ( + .I0(G_357_691), + .I1(plm_scr1_one_adv2_1_6__1090), + .I2(plm_scr1_reg_lfsr_one_2__1127), + .I3(plm_scr1_reg_lfsr_one_6__1124), + .O(plm_scr1_one_adv2[6]) + ); + defparam plm_scr1_one_adv2_7_.INIT = 16'h6996; + LUT4 plm_scr1_one_adv2_7_ ( + .I0(G_334_512), + .I1(plm_scr1_reg_lfsr_one_2__1127), + .I2(plm_scr1_reg_lfsr_one_4__1126), + .I3(plm_scr1_reg_lfsr_one_7__1123), + .O(plm_scr1_one_adv2[7]) + ); + defparam plm_scr1_one_adv2_9_.INIT = 16'h6996; + LUT4 plm_scr1_one_adv2_9_ ( + .I0(plm_scr1_one_adv2_1_9__1091), + .I1(plm_scr1_reg_lfsr_one_6__1124), + .I2(plm_scr1_reg_lfsr_one_9__1121), + .I3(plm_scr1_reg_lfsr_one_15__508), + .O(plm_scr1_one_adv2[9]) + ); + defparam plm_scr1_two_adv2_6_.INIT = 16'h6996; + LUT4 plm_scr1_two_adv2_6_ ( + .I0(G_366_687), + .I1(G_436_681), + .I2(plm_scr1_reg_lfsr_two_6__1133), + .I3(plm_scr1_reg_lfsr_two_12__1128), + .O(plm_scr1_two_adv2_6__1111) + ); + defparam plm_scr1_one_adv2_8_.INIT = 8'h96; + LUT3 plm_scr1_one_adv2_8_ ( + .I0(G_357_691), + .I1(plm_scr1_one_adv2_1_9__1091), + .I2(plm_scr1_reg_lfsr_one_8__1122), + .O(plm_scr1_one_adv2[8]) + ); + defparam plm_scr1_one_adv2_5_.INIT = 8'h96; + LUT3 plm_scr1_one_adv2_5_ ( + .I0(G_333_509), + .I1(plm_scr1_one_adv2_1_5__1092), + .I2(plm_scr1_reg_lfsr_one_5__1125), + .O(plm_scr1_one_adv2[5]) + ); + defparam plm_scr1_one_adv2_4_.INIT = 8'h96; + LUT3 plm_scr1_one_adv2_4_ ( + .I0(G_333_509), + .I1(plm_scr1_reg_lfsr_one_4__1126), + .I2(plm_scr1_reg_lfsr_one_14__690), + .O(plm_scr1_one_adv2[4]) + ); + defparam plm_scr1_input_decoder_reg_com_4_0_a2_1_0_.INIT = 16'h0200; + LUT4 plm_scr1_input_decoder_reg_com_4_0_a2_1_0_ ( + .I0(plm_scr1_reg_com_4_0_a2_1_4[0]), + .I1(plm_scr1_reg_raw_char[0]), + .I2(plm_scr1_reg_raw_char[1]), + .I3(plm_reg_raw_char_is_k[0]), + .O(plm_scr1_reg_com_4_1[0]) + ); + defparam plm_scr1_input_decoder_reg_com_3_0_a2_1_1_.INIT = 16'h0200; + LUT4 plm_scr1_input_decoder_reg_com_3_0_a2_1_1_ ( + .I0(plm_scr1_reg_com_3_0_a2_1_4[1]), + .I1(plm_scr1_reg_raw_char[8]), + .I2(plm_scr1_reg_raw_char[9]), + .I3(plm_reg_raw_char_is_k[1]), + .O(plm_scr1_reg_com_3_1[1]) + ); + defparam plm_scr1_one_adv2_m_6_.INIT = 4'h8; + LUT2 plm_scr1_one_adv2_m_6_ ( + .I0(plm_scr1_reg_lfsr_one29), + .I1(plm_scr1_one_adv2[6]), + .O(plm_scr1_one_adv2_m_6__1100) + ); + defparam plm_scr1_one_adv2_m_7_.INIT = 4'h8; + LUT2 plm_scr1_one_adv2_m_7_ ( + .I0(plm_scr1_reg_lfsr_one29), + .I1(plm_scr1_one_adv2[7]), + .O(plm_scr1_one_adv2_m_7__1099) + ); + defparam plm_scr1_one_adv2_m_8_.INIT = 4'h8; + LUT2 plm_scr1_one_adv2_m_8_ ( + .I0(plm_scr1_reg_lfsr_one29), + .I1(plm_scr1_one_adv2[8]), + .O(plm_scr1_one_adv2_m_8__1098) + ); + defparam plm_scr1_one_adv2_m_9_.INIT = 4'h8; + LUT2 plm_scr1_one_adv2_m_9_ ( + .I0(plm_scr1_reg_lfsr_one29), + .I1(plm_scr1_one_adv2[9]), + .O(plm_scr1_one_adv2_m_9__1097) + ); + defparam plm_scr1_two_adv2_m_3_.INIT = 16'h9060; + LUT4 plm_scr1_two_adv2_m_3_ ( + .I0(G_343_537), + .I1(G_366_687), + .I2(plm_scr1_reg_lfsr_one29), + .I3(plm_scr1_reg_lfsr_two_12__1128), + .O(plm_scr1_two_adv2_m_3__1115) + ); + defparam plm_scr1_two_adv2_m_4_.INIT = 16'h9060; + LUT4 plm_scr1_two_adv2_m_4_ ( + .I0(G_344_697), + .I1(G_500_677), + .I2(plm_scr1_reg_lfsr_one29), + .I3(plm_scr1_two_adv2_0_4__1093), + .O(plm_scr1_two_adv2_m_4__1113) + ); + defparam plm_scr1_two_adv2_m_5_.INIT = 16'h9060; + LUT4 plm_scr1_two_adv2_m_5_ ( + .I0(G_343_537), + .I1(G_436_681), + .I2(plm_scr1_reg_lfsr_one29), + .I3(plm_scr1_reg_lfsr_two_5__1134), + .O(plm_scr1_two_adv2_m_5__1112) + ); + defparam plm_scr1_one_adv2_m_0_8_.INIT = 4'h8; + LUT2 plm_scr1_one_adv2_m_0_8_ ( + .I0(plm_scr1_one_adv2[8]), + .I1(plm_scr1_un1_reg_com_1_1118), + .O(plm_scr1_one_adv2_m_0[8]) + ); + defparam plm_scr1_two_adv2_m_9_.INIT = 16'h8448; + LUT4 plm_scr1_two_adv2_m_9_ ( + .I0(G_344_697), + .I1(plm_scr1_reg_lfsr_one29), + .I2(plm_scr1_reg_lfsr_two_9__1130), + .I3(plm_scr1_two_adv2_1_10__1094), + .O(plm_scr1_two_adv2_m_9__1108) + ); + defparam plm_scr1_scram_reg_tx_data_12_2_am_7_.INIT = 8'h9A; + LUT3 plm_scr1_scram_reg_tx_data_12_2_am_7_ ( + .I0(plm_scr1_reg_dat[7]), + .I1(plm_reg_dis_6103[0]), + .I2(plm_scr1_reg_lfsr_one_8__1122), + .O(plm_scr1_reg_tx_data_12_2_am_1_7_) + ); + defparam plm_scr1_scram_reg_tx_data_12_2_bm_7_.INIT = 8'h36; + LUT3 plm_scr1_scram_reg_tx_data_12_2_bm_7_ ( + .I0(plm_scr1_reg_com[1]), + .I1(plm_scr1_reg_dat[7]), + .I2(plm_scr1_reg_lfsr_two_8__1131), + .O(plm_scr1_reg_tx_data_12_2_bm_1_7_) + ); + MUXF5 plm_scr1_scram_reg_tx_data_12_2_7_ ( + .I0(plm_scr1_reg_tx_data_12_2_am_1_7_), + .I1(plm_scr1_reg_tx_data_12_2_bm_1_7_), + .O(plm_scr1_reg_tx_data_12[7]), + .S(plm_scr1_reg_tx_data_12_sn_m2_0) + ); + defparam plm_scr1_scram_reg_tx_data_12_2_am_6_.INIT = 8'h9A; + LUT3 plm_scr1_scram_reg_tx_data_12_2_am_6_ ( + .I0(plm_scr1_reg_dat[6]), + .I1(plm_reg_dis_6103[0]), + .I2(plm_scr1_reg_lfsr_one_9__1121), + .O(plm_scr1_reg_tx_data_12_2_am_0[6]) + ); + defparam plm_scr1_scram_reg_tx_data_12_2_bm_6_.INIT = 8'h36; + LUT3 plm_scr1_scram_reg_tx_data_12_2_bm_6_ ( + .I0(plm_scr1_reg_com[1]), + .I1(plm_scr1_reg_dat[6]), + .I2(plm_scr1_reg_lfsr_two_9__1130), + .O(plm_scr1_reg_tx_data_12_2_bm_0[6]) + ); + MUXF5 plm_scr1_scram_reg_tx_data_12_2_6_ ( + .I0(plm_scr1_reg_tx_data_12_2_am_0[6]), + .I1(plm_scr1_reg_tx_data_12_2_bm_0[6]), + .O(plm_scr1_reg_tx_data_12[6]), + .S(plm_scr1_reg_tx_data_12_sn_m2_0) + ); + defparam plm_scr1_scram_reg_tx_data_12_2_am_5_.INIT = 8'h9A; + LUT3 plm_scr1_scram_reg_tx_data_12_2_am_5_ ( + .I0(plm_scr1_reg_dat[5]), + .I1(plm_reg_dis_6103[0]), + .I2(plm_scr1_reg_lfsr_one_10__1120), + .O(plm_scr1_reg_tx_data_12_2_am_0[5]) + ); + defparam plm_scr1_scram_reg_tx_data_12_2_bm_5_.INIT = 8'h36; + LUT3 plm_scr1_scram_reg_tx_data_12_2_bm_5_ ( + .I0(plm_scr1_reg_com[1]), + .I1(plm_scr1_reg_dat[5]), + .I2(plm_scr1_reg_lfsr_two_10__1129), + .O(plm_scr1_reg_tx_data_12_2_bm_0[5]) + ); + MUXF5 plm_scr1_scram_reg_tx_data_12_2_5_ ( + .I0(plm_scr1_reg_tx_data_12_2_am_0[5]), + .I1(plm_scr1_reg_tx_data_12_2_bm_0[5]), + .O(plm_scr1_reg_tx_data_12[5]), + .S(plm_scr1_reg_tx_data_12_sn_m2_0) + ); + defparam plm_scr1_scram_reg_tx_data_12_2_am_4_.INIT = 8'h9A; + LUT3 plm_scr1_scram_reg_tx_data_12_2_am_4_ ( + .I0(plm_scr1_reg_dat[4]), + .I1(plm_reg_dis_6103[0]), + .I2(plm_scr1_reg_lfsr_one_11__101), + .O(plm_scr1_reg_tx_data_12_2_am_0[4]) + ); + defparam plm_scr1_scram_reg_tx_data_12_2_bm_4_.INIT = 8'h36; + LUT3 plm_scr1_scram_reg_tx_data_12_2_bm_4_ ( + .I0(plm_scr1_reg_com[1]), + .I1(plm_scr1_reg_dat[4]), + .I2(plm_scr1_reg_lfsr_two_11__634), + .O(plm_scr1_reg_tx_data_12_2_bm_0[4]) + ); + MUXF5 plm_scr1_scram_reg_tx_data_12_2_4_ ( + .I0(plm_scr1_reg_tx_data_12_2_am_0[4]), + .I1(plm_scr1_reg_tx_data_12_2_bm_0[4]), + .O(plm_scr1_reg_tx_data_12[4]), + .S(plm_scr1_reg_tx_data_12_sn_m2_0) + ); + defparam plm_scr1_scram_reg_tx_data_12_2_am_3_.INIT = 8'h9A; + LUT3 plm_scr1_scram_reg_tx_data_12_2_am_3_ ( + .I0(plm_scr1_reg_dat[3]), + .I1(plm_reg_dis_6103[0]), + .I2(plm_scr1_reg_lfsr_one_12__100), + .O(plm_scr1_reg_tx_data_12_2_am_0[3]) + ); + defparam plm_scr1_scram_reg_tx_data_12_2_bm_3_.INIT = 8'h36; + LUT3 plm_scr1_scram_reg_tx_data_12_2_bm_3_ ( + .I0(plm_scr1_reg_com[1]), + .I1(plm_scr1_reg_dat[3]), + .I2(plm_scr1_reg_lfsr_two_12__1128), + .O(plm_scr1_reg_tx_data_12_2_bm_0[3]) + ); + MUXF5 plm_scr1_scram_reg_tx_data_12_2_3_ ( + .I0(plm_scr1_reg_tx_data_12_2_am_0[3]), + .I1(plm_scr1_reg_tx_data_12_2_bm_0[3]), + .O(plm_scr1_reg_tx_data_12[3]), + .S(plm_scr1_reg_tx_data_12_sn_m2_0) + ); + defparam plm_scr1_scram_reg_tx_data_12_2_am_2_.INIT = 8'h9A; + LUT3 plm_scr1_scram_reg_tx_data_12_2_am_2_ ( + .I0(plm_scr1_reg_dat[2]), + .I1(plm_reg_dis_6103[0]), + .I2(plm_scr1_reg_lfsr_one_13__511), + .O(plm_scr1_reg_tx_data_12_2_am_0[2]) + ); + defparam plm_scr1_scram_reg_tx_data_12_2_bm_2_.INIT = 8'h36; + LUT3 plm_scr1_scram_reg_tx_data_12_2_bm_2_ ( + .I0(plm_scr1_reg_com[1]), + .I1(plm_scr1_reg_dat[2]), + .I2(plm_scr1_reg_lfsr_two_13__535), + .O(plm_scr1_reg_tx_data_12_2_bm_0[2]) + ); + MUXF5 plm_scr1_scram_reg_tx_data_12_2_2_ ( + .I0(plm_scr1_reg_tx_data_12_2_am_0[2]), + .I1(plm_scr1_reg_tx_data_12_2_bm_0[2]), + .O(plm_scr1_reg_tx_data_12[2]), + .S(plm_scr1_reg_tx_data_12_sn_m2_0) + ); + defparam plm_scr1_scram_reg_tx_data_12_2_am_1_.INIT = 8'h9A; + LUT3 plm_scr1_scram_reg_tx_data_12_2_am_1_ ( + .I0(plm_scr1_reg_dat[1]), + .I1(plm_reg_dis_6103[0]), + .I2(plm_scr1_reg_lfsr_one_14__690), + .O(plm_scr1_reg_tx_data_12_2_am_0[1]) + ); + defparam plm_scr1_scram_reg_tx_data_12_2_bm_1_.INIT = 8'h36; + LUT3 plm_scr1_scram_reg_tx_data_12_2_bm_1_ ( + .I0(plm_scr1_reg_com[1]), + .I1(plm_scr1_reg_dat[1]), + .I2(plm_scr1_reg_lfsr_two_14__676), + .O(plm_scr1_reg_tx_data_12_2_bm_0[1]) + ); + MUXF5 plm_scr1_scram_reg_tx_data_12_2_1_ ( + .I0(plm_scr1_reg_tx_data_12_2_am_0[1]), + .I1(plm_scr1_reg_tx_data_12_2_bm_0[1]), + .O(plm_scr1_reg_tx_data_12[1]), + .S(plm_scr1_reg_tx_data_12_sn_m2_0) + ); + defparam plm_scr1_scram_reg_tx_data_12_2_am_0_.INIT = 8'h9A; + LUT3 plm_scr1_scram_reg_tx_data_12_2_am_0_ ( + .I0(plm_scr1_reg_dat[0]), + .I1(plm_reg_dis_6103[0]), + .I2(plm_scr1_reg_lfsr_one_15__508), + .O(plm_scr1_reg_tx_data_12_2_am_1_0_) + ); + defparam plm_scr1_scram_reg_tx_data_12_2_bm_0_.INIT = 8'h36; + LUT3 plm_scr1_scram_reg_tx_data_12_2_bm_0_ ( + .I0(plm_scr1_reg_com[1]), + .I1(plm_scr1_reg_dat[0]), + .I2(plm_scr1_reg_lfsr_two_15__536), + .O(plm_scr1_reg_tx_data_12_2_bm_1_0_) + ); + MUXF5 plm_scr1_scram_reg_tx_data_12_2_0_ ( + .I0(plm_scr1_reg_tx_data_12_2_am_1_0_), + .I1(plm_scr1_reg_tx_data_12_2_bm_1_0_), + .O(plm_scr1_reg_tx_data_12[0]), + .S(plm_scr1_reg_tx_data_12_sn_m2_0) + ); + defparam plm_scr1_one_adv2_3_.INIT = 8'h96; + LUT3 plm_scr1_one_adv2_3_ ( + .I0(G_334_512), + .I1(G_417_103), + .I2(plm_scr1_reg_lfsr_one_14__690), + .O(plm_scr1_one_adv2[3]) + ); + defparam plm_scr1_one_adv2_m_3_.INIT = 4'h8; + LUT2 plm_scr1_one_adv2_m_3_ ( + .I0(plm_scr1_reg_lfsr_one29), + .I1(plm_scr1_one_adv2[3]), + .O(plm_scr1_one_adv2_m_3__1101) + ); + defparam plm_scr1_input_decoder_reg_skp_3_0_a2_1_.INIT = 8'h02; + LUT3_L plm_scr1_input_decoder_reg_skp_3_0_a2_1_ ( + .I0(plm_scr1_reg_com_3_1[1]), + .I1(plm_scr1_reg_raw_char[13]), + .I2(plm_scr1_reg_raw_char[15]), + .LO(plm_scr1_reg_skp_3[1]) + ); + defparam plm_scr1_input_decoder_reg_skp_4_0_a2_0_.INIT = 8'h02; + LUT3_L plm_scr1_input_decoder_reg_skp_4_0_a2_0_ ( + .I0(plm_scr1_reg_com_4_1[0]), + .I1(plm_scr1_reg_raw_char[5]), + .I2(plm_scr1_reg_raw_char[7]), + .LO(plm_scr1_reg_skp_4[0]) + ); + defparam plm_scr1_input_decoder_reg_com_3_0_a2_1_.INIT = 8'h80; + LUT3_L plm_scr1_input_decoder_reg_com_3_0_a2_1_ ( + .I0(plm_scr1_reg_com_3_1[1]), + .I1(plm_scr1_reg_raw_char[13]), + .I2(plm_scr1_reg_raw_char[15]), + .LO(plm_scr1_reg_com_3[1]) + ); + defparam plm_scr1_input_decoder_reg_com_4_0_a2_0_.INIT = 8'h80; + LUT3_L plm_scr1_input_decoder_reg_com_4_0_a2_0_ ( + .I0(plm_scr1_reg_com_4_1[0]), + .I1(plm_scr1_reg_raw_char[5]), + .I2(plm_scr1_reg_raw_char[7]), + .LO(plm_scr1_reg_com_4[0]) + ); + defparam plm_scr1_input_decoder_N_14392_i.INIT = 8'hFE; + LUT3_L plm_scr1_input_decoder_N_14392_i ( + .I0(plm_reg_disdes), + .I1(plm_reg_raw_char_pass[1]), + .I2(plm_reg_raw_char_is_k[1]), + .LO(plm_N_14392_i) + ); + defparam plm_scr1_input_decoder_N_14376_i.INIT = 8'hFE; + LUT3_L plm_scr1_input_decoder_N_14376_i ( + .I0(plm_reg_disdes), + .I1(plm_reg_raw_char_pass[0]), + .I2(plm_reg_raw_char_is_k[0]), + .LO(plm_N_14376_i) + ); + defparam plm_scr1_scram_reg_tx_data_6_0_15_.INIT = 8'h9A; + LUT3_L plm_scr1_scram_reg_tx_data_6_0_15_ ( + .I0(plm_scr1_reg_dat[15]), + .I1(plm_reg_dis_6103[1]), + .I2(plm_scr1_reg_lfsr_one_8__1122), + .LO(plm_scr1_reg_tx_data_6_15_) + ); + defparam plm_scr1_scram_N_13597_i_0_i.INIT = 8'h9A; + LUT3_L plm_scr1_scram_N_13597_i_0_i ( + .I0(plm_scr1_reg_dat[14]), + .I1(plm_reg_dis_6103[1]), + .I2(plm_scr1_reg_lfsr_one_9__1121), + .LO(plm_scr1_N_13597_i_0_i) + ); + defparam plm_scr1_scram_N_13595_i_0_i.INIT = 8'h9A; + LUT3_L plm_scr1_scram_N_13595_i_0_i ( + .I0(plm_scr1_reg_dat[13]), + .I1(plm_reg_dis_6103[1]), + .I2(plm_scr1_reg_lfsr_one_10__1120), + .LO(plm_scr1_N_13595_i_0_i) + ); + defparam plm_scr1_scram_N_13593_i_0_i.INIT = 8'h9A; + LUT3_L plm_scr1_scram_N_13593_i_0_i ( + .I0(plm_scr1_reg_dat[12]), + .I1(plm_reg_dis_6103[1]), + .I2(plm_scr1_reg_lfsr_one_11__101), + .LO(plm_scr1_N_13593_i_0_i) + ); + defparam plm_scr1_scram_N_13519_i_0_i.INIT = 8'h9A; + LUT3_L plm_scr1_scram_N_13519_i_0_i ( + .I0(plm_scr1_reg_dat[11]), + .I1(plm_reg_dis_6103[1]), + .I2(plm_scr1_reg_lfsr_one_12__100), + .LO(plm_scr1_N_13519_i_0_i) + ); + defparam plm_scr1_scram_reg_tx_data_6_0_10_.INIT = 8'h9A; + LUT3_L plm_scr1_scram_reg_tx_data_6_0_10_ ( + .I0(plm_scr1_reg_dat[10]), + .I1(plm_reg_dis_6103[1]), + .I2(plm_scr1_reg_lfsr_one_13__511), + .LO(plm_scr1_reg_tx_data_6_10_) + ); + defparam plm_scr1_scram_reg_tx_data_6_0_9_.INIT = 8'h9A; + LUT3_L plm_scr1_scram_reg_tx_data_6_0_9_ ( + .I0(plm_scr1_reg_dat[9]), + .I1(plm_reg_dis_6103[1]), + .I2(plm_scr1_reg_lfsr_one_14__690), + .LO(plm_scr1_reg_tx_data_6_9_) + ); + defparam plm_scr1_scram_N_13517_i_0_i.INIT = 8'h9A; + LUT3_L plm_scr1_scram_N_13517_i_0_i ( + .I0(plm_scr1_reg_dat[8]), + .I1(plm_reg_dis_6103[1]), + .I2(plm_scr1_reg_lfsr_one_15__508), + .LO(plm_scr1_N_13517_i_0_i) + ); + defparam plm_scr1_lfsrs_reg_lfsr_one_12_0_iv_15_.INIT = 16'hD0DD; + LUT4_L plm_scr1_lfsrs_reg_lfsr_one_12_0_iv_15_ ( + .I0(plm_scr1_reg_lfsr_one29), + .I1(plm_scr1_one_adv2[15]), + .I2(plm_scr1_reg_lfsr_two_15__536), + .I3(plm_scr1_un1_reg_com_1_1118), + .LO(plm_scr1_reg_lfsr_one_12_15_) + ); + defparam plm_scr1_lfsrs_reg_lfsr_one_12_0_iv_14_.INIT = 16'hD0DD; + LUT4_L plm_scr1_lfsrs_reg_lfsr_one_12_0_iv_14_ ( + .I0(plm_scr1_reg_lfsr_one29), + .I1(plm_scr1_one_adv2[14]), + .I2(plm_scr1_reg_lfsr_two_14__676), + .I3(plm_scr1_un1_reg_com_1_1118), + .LO(plm_scr1_reg_lfsr_one_12_14_) + ); + defparam plm_scr1_lfsrs_reg_lfsr_one_12_0_iv_13_.INIT = 16'hD0DD; + LUT4_L plm_scr1_lfsrs_reg_lfsr_one_12_0_iv_13_ ( + .I0(plm_scr1_reg_lfsr_one29), + .I1(plm_scr1_one_adv2[13]), + .I2(plm_scr1_reg_lfsr_two_13__535), + .I3(plm_scr1_un1_reg_com_1_1118), + .LO(plm_scr1_reg_lfsr_one_12_13_) + ); + defparam plm_scr1_lfsrs_N_9687_i.INIT = 16'hEAFF; + LUT4_L plm_scr1_lfsrs_N_9687_i ( + .I0(plm_scr1_one_adv2_m_12__1095), + .I1(plm_scr1_reg_lfsr_two_12__1128), + .I2(plm_scr1_un1_reg_com_1_1118), + .I3(plm_scr1_un1_reg_lfsr_one37_i), + .LO(plm_scr1_N_9687_i) + ); + defparam plm_scr1_lfsrs_reg_lfsr_one_12_0_iv_11_.INIT = 16'hD0DD; + LUT4_L plm_scr1_lfsrs_reg_lfsr_one_12_0_iv_11_ ( + .I0(plm_scr1_reg_lfsr_one29), + .I1(plm_scr1_one_adv2[11]), + .I2(plm_scr1_reg_lfsr_two_11__634), + .I3(plm_scr1_un1_reg_com_1_1118), + .LO(plm_scr1_reg_lfsr_one_12_11_) + ); + defparam plm_scr1_lfsrs_N_9689_i.INIT = 16'hEAFF; + LUT4_L plm_scr1_lfsrs_N_9689_i ( + .I0(plm_scr1_one_adv2_m_10__1096), + .I1(plm_scr1_reg_lfsr_two_10__1129), + .I2(plm_scr1_un1_reg_com_1_1118), + .I3(plm_scr1_un1_reg_lfsr_one37_i), + .LO(plm_scr1_N_9689_i) + ); + defparam plm_scr1_lfsrs_N_9690_i.INIT = 16'hEAFF; + LUT4_L plm_scr1_lfsrs_N_9690_i ( + .I0(plm_scr1_one_adv2_m_9__1097), + .I1(plm_scr1_reg_lfsr_two_9__1130), + .I2(plm_scr1_un1_reg_com_1_1118), + .I3(plm_scr1_un1_reg_lfsr_one37_i), + .LO(plm_scr1_N_9690_i) + ); + defparam plm_scr1_lfsrs_N_9691_i.INIT = 16'hEAFF; + LUT4_L plm_scr1_lfsrs_N_9691_i ( + .I0(plm_scr1_one_adv2_m_8__1098), + .I1(plm_scr1_reg_lfsr_two_8__1131), + .I2(plm_scr1_un1_reg_com_1_1118), + .I3(plm_scr1_un1_reg_lfsr_one37_i), + .LO(plm_scr1_N_9691_i) + ); + defparam plm_scr1_lfsrs_N_9692_i.INIT = 16'hEAFF; + LUT4_L plm_scr1_lfsrs_N_9692_i ( + .I0(plm_scr1_one_adv2_m_7__1099), + .I1(plm_scr1_reg_lfsr_two_7__1132), + .I2(plm_scr1_un1_reg_com_1_1118), + .I3(plm_scr1_un1_reg_lfsr_one37_i), + .LO(plm_scr1_N_9692_i) + ); + defparam plm_scr1_lfsrs_N_9693_i.INIT = 16'hEAFF; + LUT4_L plm_scr1_lfsrs_N_9693_i ( + .I0(plm_scr1_one_adv2_m_6__1100), + .I1(plm_scr1_reg_lfsr_two_6__1133), + .I2(plm_scr1_un1_reg_com_1_1118), + .I3(plm_scr1_un1_reg_lfsr_one37_i), + .LO(plm_scr1_N_9693_i) + ); + defparam plm_scr1_lfsrs_N_9694_i.INIT = 16'hF8FF; + LUT4_L plm_scr1_lfsrs_N_9694_i ( + .I0(plm_scr1_reg_lfsr_one29), + .I1(plm_scr1_one_adv2[5]), + .I2(plm_scr1_reg_lfsr_two_m[5]), + .I3(plm_scr1_un1_reg_lfsr_one37_i), + .LO(plm_scr1_N_9694_i) + ); + defparam plm_scr1_lfsrs_reg_lfsr_one_12_0_iv_4_.INIT = 16'hD0DD; + LUT4_L plm_scr1_lfsrs_reg_lfsr_one_12_0_iv_4_ ( + .I0(plm_scr1_reg_lfsr_one29), + .I1(plm_scr1_one_adv2[4]), + .I2(plm_scr1_reg_lfsr_two_4__696), + .I3(plm_scr1_un1_reg_com_1_1118), + .LO(plm_scr1_reg_lfsr_one_12_4_) + ); + defparam plm_scr1_lfsrs_N_9696_i.INIT = 16'hEAFF; + LUT4_L plm_scr1_lfsrs_N_9696_i ( + .I0(plm_scr1_one_adv2_m_3__1101), + .I1(plm_scr1_reg_lfsr_two_3__686), + .I2(plm_scr1_un1_reg_com_1_1118), + .I3(plm_scr1_un1_reg_lfsr_one37_i), + .LO(plm_scr1_N_9696_i) + ); + defparam plm_scr1_lfsrs_reg_lfsr_one_12_0_iv_2_.INIT = 16'hD0DD; + LUT4_L plm_scr1_lfsrs_reg_lfsr_one_12_0_iv_2_ ( + .I0(plm_scr1_reg_lfsr_one29), + .I1(plm_scr1_one_adv2[2]), + .I2(plm_scr1_reg_lfsr_two_2__680), + .I3(plm_scr1_un1_reg_com_1_1118), + .LO(plm_scr1_reg_lfsr_one_12_2_) + ); + defparam plm_scr1_lfsrs_reg_lfsr_one_12_0_iv_1_.INIT = 16'hD0DD; + LUT4_L plm_scr1_lfsrs_reg_lfsr_one_12_0_iv_1_ ( + .I0(plm_scr1_reg_lfsr_one29), + .I1(plm_scr1_one_adv2[1]), + .I2(plm_scr1_reg_lfsr_two_1__679), + .I3(plm_scr1_un1_reg_com_1_1118), + .LO(plm_scr1_reg_lfsr_one_12_1_) + ); + defparam plm_scr1_lfsrs_reg_lfsr_one_12_0_iv_0_.INIT = 16'hD0DD; + LUT4_L plm_scr1_lfsrs_reg_lfsr_one_12_0_iv_0_ ( + .I0(plm_scr1_reg_lfsr_one29), + .I1(plm_scr1_one_adv2[0]), + .I2(plm_scr1_reg_lfsr_two_0__633), + .I3(plm_scr1_un1_reg_com_1_1118), + .LO(plm_scr1_reg_lfsr_one_12_0_) + ); + defparam plm_scr1_lfsrs_N_9668_i.INIT = 16'hECFF; + LUT4_L plm_scr1_lfsrs_N_9668_i ( + .I0(plm_scr1_one_adv2[15]), + .I1(plm_scr1_two_adv2_m_15__1102), + .I2(plm_scr1_un1_reg_com_1_1118), + .I3(plm_scr1_un1_reg_lfsr_one37_i), + .LO(plm_scr1_N_9668_i) + ); + defparam plm_scr1_lfsrs_N_9669_i.INIT = 16'hECFF; + LUT4_L plm_scr1_lfsrs_N_9669_i ( + .I0(plm_scr1_one_adv2[14]), + .I1(plm_scr1_two_adv2_m_14__1103), + .I2(plm_scr1_un1_reg_com_1_1118), + .I3(plm_scr1_un1_reg_lfsr_one37_i), + .LO(plm_scr1_N_9669_i) + ); + defparam plm_scr1_lfsrs_N_9670_i.INIT = 16'hECFF; + LUT4_L plm_scr1_lfsrs_N_9670_i ( + .I0(plm_scr1_one_adv2[13]), + .I1(plm_scr1_two_adv2_m_13__1104), + .I2(plm_scr1_un1_reg_com_1_1118), + .I3(plm_scr1_un1_reg_lfsr_one37_i), + .LO(plm_scr1_N_9670_i) + ); + defparam plm_scr1_lfsrs_N_9671_i.INIT = 16'hECA0; + LUT4_L plm_scr1_lfsrs_N_9671_i ( + .I0(plm_scr1_reg_lfsr_one29), + .I1(plm_scr1_one_adv2[12]), + .I2(plm_scr1_two_adv2_12__1105), + .I3(plm_scr1_un1_reg_com_1_1118), + .LO(plm_scr1_N_9671_i) + ); + defparam plm_scr1_lfsrs_N_9672_i.INIT = 16'hECFF; + LUT4_L plm_scr1_lfsrs_N_9672_i ( + .I0(plm_scr1_one_adv2[11]), + .I1(plm_scr1_two_adv2_m_11__1106), + .I2(plm_scr1_un1_reg_com_1_1118), + .I3(plm_scr1_un1_reg_lfsr_one37_i), + .LO(plm_scr1_N_9672_i) + ); + defparam plm_scr1_lfsrs_N_9673_i.INIT = 16'hECA0; + LUT4_L plm_scr1_lfsrs_N_9673_i ( + .I0(plm_scr1_reg_lfsr_one29), + .I1(plm_scr1_one_adv2[10]), + .I2(plm_scr1_two_adv2_10__1107), + .I3(plm_scr1_un1_reg_com_1_1118), + .LO(plm_scr1_N_9673_i) + ); + defparam plm_scr1_lfsrs_N_9674_i.INIT = 16'hFFEC; + LUT4_L plm_scr1_lfsrs_N_9674_i ( + .I0(plm_scr1_one_adv2[9]), + .I1(plm_scr1_two_adv2_m_9__1108), + .I2(plm_scr1_un1_reg_com_1_1118), + .I3(plm_scr1_un1_reg_skp_2_1114), + .LO(plm_scr1_N_9674_i) + ); + defparam plm_scr1_lfsrs_N_9675_i.INIT = 16'hFFEC; + LUT4_L plm_scr1_lfsrs_N_9675_i ( + .I0(plm_scr1_reg_lfsr_one29), + .I1(plm_scr1_one_adv2_m_0[8]), + .I2(plm_scr1_two_adv2_8__1109), + .I3(plm_scr1_un1_reg_skp_2_1114), + .LO(plm_scr1_N_9675_i) + ); + defparam plm_scr1_lfsrs_N_9676_i.INIT = 16'hECA0; + LUT4_L plm_scr1_lfsrs_N_9676_i ( + .I0(plm_scr1_reg_lfsr_one29), + .I1(plm_scr1_one_adv2[7]), + .I2(plm_scr1_two_adv2_7__1110), + .I3(plm_scr1_un1_reg_com_1_1118), + .LO(plm_scr1_N_9676_i) + ); + defparam plm_scr1_lfsrs_N_9677_i.INIT = 16'hECA0; + LUT4_L plm_scr1_lfsrs_N_9677_i ( + .I0(plm_scr1_reg_lfsr_one29), + .I1(plm_scr1_one_adv2[6]), + .I2(plm_scr1_two_adv2_6__1111), + .I3(plm_scr1_un1_reg_com_1_1118), + .LO(plm_scr1_N_9677_i) + ); + defparam plm_scr1_lfsrs_N_9678_i.INIT = 16'hFFEC; + LUT4_L plm_scr1_lfsrs_N_9678_i ( + .I0(plm_scr1_one_adv2[5]), + .I1(plm_scr1_two_adv2_m_5__1112), + .I2(plm_scr1_un1_reg_com_1_1118), + .I3(plm_scr1_un1_reg_skp_2_1114), + .LO(plm_scr1_N_9678_i) + ); + defparam plm_scr1_lfsrs_N_9679_i.INIT = 16'hECFF; + LUT4_L plm_scr1_lfsrs_N_9679_i ( + .I0(plm_scr1_one_adv2[4]), + .I1(plm_scr1_two_adv2_m_4__1113), + .I2(plm_scr1_un1_reg_com_1_1118), + .I3(plm_scr1_un1_reg_lfsr_one37_i), + .LO(plm_scr1_N_9679_i) + ); + defparam plm_scr1_lfsrs_N_9680_i.INIT = 16'hFFEC; + LUT4_L plm_scr1_lfsrs_N_9680_i ( + .I0(plm_scr1_one_adv2[3]), + .I1(plm_scr1_two_adv2_m_3__1115), + .I2(plm_scr1_un1_reg_com_1_1118), + .I3(plm_scr1_un1_reg_skp_2_1114), + .LO(plm_scr1_N_9680_i) + ); + defparam plm_scr1_lfsrs_N_9681_i.INIT = 16'hECFF; + LUT4_L plm_scr1_lfsrs_N_9681_i ( + .I0(plm_scr1_one_adv2[2]), + .I1(plm_scr1_two_adv2_m_2__1116), + .I2(plm_scr1_un1_reg_com_1_1118), + .I3(plm_scr1_un1_reg_lfsr_one37_i), + .LO(plm_scr1_N_9681_i) + ); + defparam plm_scr1_lfsrs_N_9682_i.INIT = 16'hECFF; + LUT4_L plm_scr1_lfsrs_N_9682_i ( + .I0(plm_scr1_one_adv2[1]), + .I1(plm_scr1_two_adv2_m_1__1117), + .I2(plm_scr1_un1_reg_com_1_1118), + .I3(plm_scr1_un1_reg_lfsr_one37_i), + .LO(plm_scr1_N_9682_i) + ); + defparam plm_scr1_lfsrs_N_9683_i.INIT = 16'hECFF; + LUT4_L plm_scr1_lfsrs_N_9683_i ( + .I0(plm_scr1_one_adv2[0]), + .I1(plm_scr1_two_adv2_m_0__1119), + .I2(plm_scr1_un1_reg_com_1_1118), + .I3(plm_scr1_un1_reg_lfsr_one37_i), + .LO(plm_scr1_N_9683_i) + ); + FDC plm_scr1_reg_tx_data_1_ ( + .C(mgt_clk), + .D(plm_scr1_reg_tx_data_12[1]), + .Q(plm_tx1_data[1]), + .CLR(plm_rst) + ); + FDC plm_scr1_reg_tx_data_0_ ( + .C(mgt_clk), + .D(plm_scr1_reg_tx_data_12[0]), + .Q(plm_tx1_data[0]), + .CLR(plm_rst) + ); + FDC plm_scr1_reg_skp_1_ ( + .C(mgt_clk), + .D(plm_scr1_reg_skp_3[1]), + .Q(plm_scr1_reg_skp[1]), + .CLR(plm_rst) + ); + FDC plm_scr1_reg_skp_0_ ( + .C(mgt_clk), + .D(plm_scr1_reg_skp_4[0]), + .Q(plm_scr1_reg_skp[0]), + .CLR(plm_rst) + ); + FDC plm_scr1_reg_com_1_ ( + .C(mgt_clk), + .D(plm_scr1_reg_com_3[1]), + .Q(plm_scr1_reg_com[1]), + .CLR(plm_rst) + ); + FDC plm_scr1_reg_com_0_ ( + .C(mgt_clk), + .D(plm_scr1_reg_com_4[0]), + .Q(plm_scr1_reg_com[0]), + .CLR(plm_rst) + ); + FDC plm_scr1_reg_tx_data_15_ ( + .C(mgt_clk), + .D(plm_scr1_reg_tx_data_6_15_), + .Q(plm_tx1_data[15]), + .CLR(plm_rst) + ); + FDC plm_scr1_reg_tx_data_14_ ( + .C(mgt_clk), + .D(plm_scr1_N_13597_i_0_i), + .Q(plm_tx1_data[14]), + .CLR(plm_rst) + ); + FDC plm_scr1_reg_tx_data_13_ ( + .C(mgt_clk), + .D(plm_scr1_N_13595_i_0_i), + .Q(plm_tx1_data[13]), + .CLR(plm_rst) + ); + FDC plm_scr1_reg_tx_data_12_ ( + .C(mgt_clk), + .D(plm_scr1_N_13593_i_0_i), + .Q(plm_tx1_data[12]), + .CLR(plm_rst) + ); + FDC plm_scr1_reg_tx_data_11_ ( + .C(mgt_clk), + .D(plm_scr1_N_13519_i_0_i), + .Q(plm_tx1_data[11]), + .CLR(plm_rst) + ); + FDC plm_scr1_reg_tx_data_10_ ( + .C(mgt_clk), + .D(plm_scr1_reg_tx_data_6_10_), + .Q(plm_tx1_data[10]), + .CLR(plm_rst) + ); + FDC plm_scr1_reg_tx_data_9_ ( + .C(mgt_clk), + .D(plm_scr1_reg_tx_data_6_9_), + .Q(plm_tx1_data[9]), + .CLR(plm_rst) + ); + FDC plm_scr1_reg_tx_data_8_ ( + .C(mgt_clk), + .D(plm_scr1_N_13517_i_0_i), + .Q(plm_tx1_data[8]), + .CLR(plm_rst) + ); + FDC plm_scr1_reg_tx_data_7_ ( + .C(mgt_clk), + .D(plm_scr1_reg_tx_data_12[7]), + .Q(plm_tx1_data[7]), + .CLR(plm_rst) + ); + FDC plm_scr1_reg_tx_data_6_ ( + .C(mgt_clk), + .D(plm_scr1_reg_tx_data_12[6]), + .Q(plm_tx1_data[6]), + .CLR(plm_rst) + ); + FDC plm_scr1_reg_tx_data_5_ ( + .C(mgt_clk), + .D(plm_scr1_reg_tx_data_12[5]), + .Q(plm_tx1_data[5]), + .CLR(plm_rst) + ); + FDC plm_scr1_reg_tx_data_4_ ( + .C(mgt_clk), + .D(plm_scr1_reg_tx_data_12[4]), + .Q(plm_tx1_data[4]), + .CLR(plm_rst) + ); + FDC plm_scr1_reg_tx_data_3_ ( + .C(mgt_clk), + .D(plm_scr1_reg_tx_data_12[3]), + .Q(plm_tx1_data[3]), + .CLR(plm_rst) + ); + FDC plm_scr1_reg_tx_data_2_ ( + .C(mgt_clk), + .D(plm_scr1_reg_tx_data_12[2]), + .Q(plm_tx1_data[2]), + .CLR(plm_rst) + ); + FDC plm_scr1_reg_raw_char_is_k_1_ ( + .C(mgt_clk), + .D(plm_tx1_raw_char_is_k[1]), + .Q(plm_reg_raw_char_is_k[1]), + .CLR(plm_rst) + ); + FDC plm_scr1_reg_raw_char_is_k_0_ ( + .C(mgt_clk), + .D(plm_tx1_raw_char_is_k[0]), + .Q(plm_reg_raw_char_is_k[0]), + .CLR(plm_rst) + ); + FDC plm_scr1_reg_tx_char_is_k_1_ ( + .C(mgt_clk), + .D(plm_reg_kkk[1]), + .Q(plm_tx2_char_is_k[1]), + .CLR(plm_rst) + ); + FDC plm_scr1_reg_tx_char_is_k_0_ ( + .C(mgt_clk), + .D(plm_reg_kkk[0]), + .Q(plm_tx2_char_is_k[0]), + .CLR(plm_rst) + ); + FDC plm_scr1_reg_raw_char_14_ ( + .C(mgt_clk), + .D(plm_tx1_raw_char[14]), + .Q(plm_scr1_reg_raw_char[14]), + .CLR(plm_rst) + ); + FDC plm_scr1_reg_raw_char_13_ ( + .C(mgt_clk), + .D(plm_tx1_raw_char[13]), + .Q(plm_scr1_reg_raw_char[13]), + .CLR(plm_rst) + ); + FDC plm_scr1_reg_raw_char_12_ ( + .C(mgt_clk), + .D(plm_tx1_raw_char[12]), + .Q(plm_scr1_reg_raw_char[12]), + .CLR(plm_rst) + ); + FDC plm_scr1_reg_raw_char_11_ ( + .C(mgt_clk), + .D(plm_tx1_raw_char[11]), + .Q(plm_scr1_reg_raw_char[11]), + .CLR(plm_rst) + ); + FDC plm_scr1_reg_raw_char_10_ ( + .C(mgt_clk), + .D(plm_tx1_raw_char[10]), + .Q(plm_scr1_reg_raw_char[10]), + .CLR(plm_rst) + ); + FDC plm_scr1_reg_raw_char_9_ ( + .C(mgt_clk), + .D(plm_tx1_raw_char[9]), + .Q(plm_scr1_reg_raw_char[9]), + .CLR(plm_rst) + ); + FDC plm_scr1_reg_raw_char_8_ ( + .C(mgt_clk), + .D(plm_tx1_raw_char[8]), + .Q(plm_scr1_reg_raw_char[8]), + .CLR(plm_rst) + ); + FDC plm_scr1_reg_raw_char_7_ ( + .C(mgt_clk), + .D(plm_tx1_raw_char[7]), + .Q(plm_scr1_reg_raw_char[7]), + .CLR(plm_rst) + ); + FDC plm_scr1_reg_raw_char_6_ ( + .C(mgt_clk), + .D(plm_tx1_raw_char[6]), + .Q(plm_scr1_reg_raw_char[6]), + .CLR(plm_rst) + ); + FDC plm_scr1_reg_raw_char_5_ ( + .C(mgt_clk), + .D(plm_tx1_raw_char[5]), + .Q(plm_scr1_reg_raw_char[5]), + .CLR(plm_rst) + ); + FDC plm_scr1_reg_raw_char_4_ ( + .C(mgt_clk), + .D(plm_tx1_raw_char[4]), + .Q(plm_scr1_reg_raw_char[4]), + .CLR(plm_rst) + ); + FDC plm_scr1_reg_raw_char_3_ ( + .C(mgt_clk), + .D(plm_tx1_raw_char[3]), + .Q(plm_scr1_reg_raw_char[3]), + .CLR(plm_rst) + ); + FDC plm_scr1_reg_raw_char_2_ ( + .C(mgt_clk), + .D(plm_tx1_raw_char[2]), + .Q(plm_scr1_reg_raw_char[2]), + .CLR(plm_rst) + ); + FDC plm_scr1_reg_raw_char_1_ ( + .C(mgt_clk), + .D(plm_tx1_raw_char[1]), + .Q(plm_scr1_reg_raw_char[1]), + .CLR(plm_rst) + ); + FDC plm_scr1_reg_raw_char_0_ ( + .C(mgt_clk), + .D(plm_tx1_raw_char[0]), + .Q(plm_scr1_reg_raw_char[0]), + .CLR(plm_rst) + ); + FDC plm_scr1_reg_dat_13_ ( + .C(mgt_clk), + .D(plm_scr1_reg_raw_char[13]), + .Q(plm_scr1_reg_dat[13]), + .CLR(plm_rst) + ); + FDC plm_scr1_reg_dat_12_ ( + .C(mgt_clk), + .D(plm_scr1_reg_raw_char[12]), + .Q(plm_scr1_reg_dat[12]), + .CLR(plm_rst) + ); + FDC plm_scr1_reg_dat_11_ ( + .C(mgt_clk), + .D(plm_scr1_reg_raw_char[11]), + .Q(plm_scr1_reg_dat[11]), + .CLR(plm_rst) + ); + FDC plm_scr1_reg_dat_10_ ( + .C(mgt_clk), + .D(plm_scr1_reg_raw_char[10]), + .Q(plm_scr1_reg_dat[10]), + .CLR(plm_rst) + ); + FDC plm_scr1_reg_dat_9_ ( + .C(mgt_clk), + .D(plm_scr1_reg_raw_char[9]), + .Q(plm_scr1_reg_dat[9]), + .CLR(plm_rst) + ); + FDC plm_scr1_reg_dat_8_ ( + .C(mgt_clk), + .D(plm_scr1_reg_raw_char[8]), + .Q(plm_scr1_reg_dat[8]), + .CLR(plm_rst) + ); + FDC plm_scr1_reg_dat_7_ ( + .C(mgt_clk), + .D(plm_scr1_reg_raw_char[7]), + .Q(plm_scr1_reg_dat[7]), + .CLR(plm_rst) + ); + FDC plm_scr1_reg_dat_6_ ( + .C(mgt_clk), + .D(plm_scr1_reg_raw_char[6]), + .Q(plm_scr1_reg_dat[6]), + .CLR(plm_rst) + ); + FDC plm_scr1_reg_dat_5_ ( + .C(mgt_clk), + .D(plm_scr1_reg_raw_char[5]), + .Q(plm_scr1_reg_dat[5]), + .CLR(plm_rst) + ); + FDC plm_scr1_reg_dat_4_ ( + .C(mgt_clk), + .D(plm_scr1_reg_raw_char[4]), + .Q(plm_scr1_reg_dat[4]), + .CLR(plm_rst) + ); + FDC plm_scr1_reg_dat_3_ ( + .C(mgt_clk), + .D(plm_scr1_reg_raw_char[3]), + .Q(plm_scr1_reg_dat[3]), + .CLR(plm_rst) + ); + FDC plm_scr1_reg_dat_2_ ( + .C(mgt_clk), + .D(plm_scr1_reg_raw_char[2]), + .Q(plm_scr1_reg_dat[2]), + .CLR(plm_rst) + ); + FDC plm_scr1_reg_dat_1_ ( + .C(mgt_clk), + .D(plm_scr1_reg_raw_char[1]), + .Q(plm_scr1_reg_dat[1]), + .CLR(plm_rst) + ); + FDC plm_scr1_reg_dat_0_ ( + .C(mgt_clk), + .D(plm_scr1_reg_raw_char[0]), + .Q(plm_scr1_reg_dat[0]), + .CLR(plm_rst) + ); + FDC plm_scr1_reg_raw_char_15_ ( + .C(mgt_clk), + .D(plm_tx1_raw_char[15]), + .Q(plm_scr1_reg_raw_char[15]), + .CLR(plm_rst) + ); + FDC plm_scr1_reg_dat_15_ ( + .C(mgt_clk), + .D(plm_scr1_reg_raw_char[15]), + .Q(plm_scr1_reg_dat[15]), + .CLR(plm_rst) + ); + FDC plm_scr1_reg_dat_14_ ( + .C(mgt_clk), + .D(plm_scr1_reg_raw_char[14]), + .Q(plm_scr1_reg_dat[14]), + .CLR(plm_rst) + ); + FDPE plm_scr1_reg_lfsr_one_15_ ( + .PRE(plm_rst), + .CE(plm_scr1_reg_lfsr_one32_i), + .C(mgt_clk), + .D(plm_scr1_reg_lfsr_one_12_15_), + .Q(plm_scr1_reg_lfsr_one_15__508) + ); + FDPE plm_scr1_reg_lfsr_one_14_ ( + .PRE(plm_rst), + .CE(plm_scr1_reg_lfsr_one32_i), + .C(mgt_clk), + .D(plm_scr1_reg_lfsr_one_12_14_), + .Q(plm_scr1_reg_lfsr_one_14__690) + ); + FDPE plm_scr1_reg_lfsr_one_13_ ( + .PRE(plm_rst), + .CE(plm_scr1_reg_lfsr_one32_i), + .C(mgt_clk), + .D(plm_scr1_reg_lfsr_one_12_13_), + .Q(plm_scr1_reg_lfsr_one_13__511) + ); + FDPE plm_scr1_reg_lfsr_one_12_ ( + .PRE(plm_rst), + .CE(plm_scr1_reg_lfsr_one32_i), + .C(mgt_clk), + .D(plm_scr1_N_9687_i), + .Q(plm_scr1_reg_lfsr_one_12__100) + ); + FDPE plm_scr1_reg_lfsr_one_11_ ( + .PRE(plm_rst), + .CE(plm_scr1_reg_lfsr_one32_i), + .C(mgt_clk), + .D(plm_scr1_reg_lfsr_one_12_11_), + .Q(plm_scr1_reg_lfsr_one_11__101) + ); + FDPE plm_scr1_reg_lfsr_one_10_ ( + .PRE(plm_rst), + .CE(plm_scr1_reg_lfsr_one32_i), + .C(mgt_clk), + .D(plm_scr1_N_9689_i), + .Q(plm_scr1_reg_lfsr_one_10__1120) + ); + FDPE plm_scr1_reg_lfsr_one_9_ ( + .PRE(plm_rst), + .CE(plm_scr1_reg_lfsr_one32_i), + .C(mgt_clk), + .D(plm_scr1_N_9690_i), + .Q(plm_scr1_reg_lfsr_one_9__1121) + ); + FDPE plm_scr1_reg_lfsr_one_8_ ( + .PRE(plm_rst), + .CE(plm_scr1_reg_lfsr_one32_i), + .C(mgt_clk), + .D(plm_scr1_N_9691_i), + .Q(plm_scr1_reg_lfsr_one_8__1122) + ); + FDPE plm_scr1_reg_lfsr_one_7_ ( + .PRE(plm_rst), + .CE(plm_scr1_reg_lfsr_one32_i), + .C(mgt_clk), + .D(plm_scr1_N_9692_i), + .Q(plm_scr1_reg_lfsr_one_7__1123) + ); + FDPE plm_scr1_reg_lfsr_one_6_ ( + .PRE(plm_rst), + .CE(plm_scr1_reg_lfsr_one32_i), + .C(mgt_clk), + .D(plm_scr1_N_9693_i), + .Q(plm_scr1_reg_lfsr_one_6__1124) + ); + FDPE plm_scr1_reg_lfsr_one_5_ ( + .PRE(plm_rst), + .CE(plm_scr1_reg_lfsr_one32_i), + .C(mgt_clk), + .D(plm_scr1_N_9694_i), + .Q(plm_scr1_reg_lfsr_one_5__1125) + ); + FDPE plm_scr1_reg_lfsr_one_4_ ( + .PRE(plm_rst), + .CE(plm_scr1_reg_lfsr_one32_i), + .C(mgt_clk), + .D(plm_scr1_reg_lfsr_one_12_4_), + .Q(plm_scr1_reg_lfsr_one_4__1126) + ); + FDPE plm_scr1_reg_lfsr_one_3_ ( + .PRE(plm_rst), + .CE(plm_scr1_reg_lfsr_one32_i), + .C(mgt_clk), + .D(plm_scr1_N_9696_i), + .Q(plm_scr1_reg_lfsr_one_3__510) + ); + FDPE plm_scr1_reg_lfsr_one_2_ ( + .PRE(plm_rst), + .CE(plm_scr1_reg_lfsr_one32_i), + .C(mgt_clk), + .D(plm_scr1_reg_lfsr_one_12_2_), + .Q(plm_scr1_reg_lfsr_one_2__1127) + ); + FDPE plm_scr1_reg_lfsr_one_1_ ( + .PRE(plm_rst), + .CE(plm_scr1_reg_lfsr_one32_i), + .C(mgt_clk), + .D(plm_scr1_reg_lfsr_one_12_1_), + .Q(plm_scr1_reg_lfsr_one_1__507) + ); + FDPE plm_scr1_reg_lfsr_one_0_ ( + .PRE(plm_rst), + .CE(plm_scr1_reg_lfsr_one32_i), + .C(mgt_clk), + .D(plm_scr1_reg_lfsr_one_12_0_), + .Q(plm_scr1_reg_lfsr_one_0__102) + ); + FDPE plm_scr1_reg_lfsr_two_15_ ( + .PRE(plm_rst), + .CE(plm_scr1_reg_lfsr_one32_i), + .C(mgt_clk), + .D(plm_scr1_N_9668_i), + .Q(plm_scr1_reg_lfsr_two_15__536) + ); + FDPE plm_scr1_reg_lfsr_two_14_ ( + .PRE(plm_rst), + .CE(plm_scr1_reg_lfsr_one32_i), + .C(mgt_clk), + .D(plm_scr1_N_9669_i), + .Q(plm_scr1_reg_lfsr_two_14__676) + ); + FDPE plm_scr1_reg_lfsr_two_13_ ( + .PRE(plm_rst), + .CE(plm_scr1_reg_lfsr_one32_i), + .C(mgt_clk), + .D(plm_scr1_N_9670_i), + .Q(plm_scr1_reg_lfsr_two_13__535) + ); + FDCE plm_scr1_reg_lfsr_two_12_ ( + .CE(plm_scr1_reg_lfsr_one32_i), + .C(mgt_clk), + .D(plm_scr1_N_9671_i), + .Q(plm_scr1_reg_lfsr_two_12__1128), + .CLR(plm_rst) + ); + FDPE plm_scr1_reg_lfsr_two_11_ ( + .PRE(plm_rst), + .CE(plm_scr1_reg_lfsr_one32_i), + .C(mgt_clk), + .D(plm_scr1_N_9672_i), + .Q(plm_scr1_reg_lfsr_two_11__634) + ); + FDCE plm_scr1_reg_lfsr_two_10_ ( + .CE(plm_scr1_reg_lfsr_one32_i), + .C(mgt_clk), + .D(plm_scr1_N_9673_i), + .Q(plm_scr1_reg_lfsr_two_10__1129), + .CLR(plm_rst) + ); + FDCE plm_scr1_reg_lfsr_two_9_ ( + .CE(plm_scr1_reg_lfsr_one32_i), + .C(mgt_clk), + .D(plm_scr1_N_9674_i), + .Q(plm_scr1_reg_lfsr_two_9__1130), + .CLR(plm_rst) + ); + FDCE plm_scr1_reg_lfsr_two_8_ ( + .CE(plm_scr1_reg_lfsr_one32_i), + .C(mgt_clk), + .D(plm_scr1_N_9675_i), + .Q(plm_scr1_reg_lfsr_two_8__1131), + .CLR(plm_rst) + ); + FDCE plm_scr1_reg_lfsr_two_7_ ( + .CE(plm_scr1_reg_lfsr_one32_i), + .C(mgt_clk), + .D(plm_scr1_N_9676_i), + .Q(plm_scr1_reg_lfsr_two_7__1132), + .CLR(plm_rst) + ); + FDCE plm_scr1_reg_lfsr_two_6_ ( + .CE(plm_scr1_reg_lfsr_one32_i), + .C(mgt_clk), + .D(plm_scr1_N_9677_i), + .Q(plm_scr1_reg_lfsr_two_6__1133), + .CLR(plm_rst) + ); + FDCE plm_scr1_reg_lfsr_two_5_ ( + .CE(plm_scr1_reg_lfsr_one32_i), + .C(mgt_clk), + .D(plm_scr1_N_9678_i), + .Q(plm_scr1_reg_lfsr_two_5__1134), + .CLR(plm_rst) + ); + FDPE plm_scr1_reg_lfsr_two_4_ ( + .PRE(plm_rst), + .CE(plm_scr1_reg_lfsr_one32_i), + .C(mgt_clk), + .D(plm_scr1_N_9679_i), + .Q(plm_scr1_reg_lfsr_two_4__696) + ); + FDCE plm_scr1_reg_lfsr_two_3_ ( + .CE(plm_scr1_reg_lfsr_one32_i), + .C(mgt_clk), + .D(plm_scr1_N_9680_i), + .Q(plm_scr1_reg_lfsr_two_3__686), + .CLR(plm_rst) + ); + FDPE plm_scr1_reg_lfsr_two_2_ ( + .PRE(plm_rst), + .CE(plm_scr1_reg_lfsr_one32_i), + .C(mgt_clk), + .D(plm_scr1_N_9681_i), + .Q(plm_scr1_reg_lfsr_two_2__680) + ); + FDPE plm_scr1_reg_lfsr_two_1_ ( + .PRE(plm_rst), + .CE(plm_scr1_reg_lfsr_one32_i), + .C(mgt_clk), + .D(plm_scr1_N_9682_i), + .Q(plm_scr1_reg_lfsr_two_1__679) + ); + FDPE plm_scr1_reg_lfsr_two_0_ ( + .PRE(plm_rst), + .CE(plm_scr1_reg_lfsr_one32_i), + .C(mgt_clk), + .D(plm_scr1_N_9683_i), + .Q(plm_scr1_reg_lfsr_two_0__633) + ); + defparam plm_scr2_scram_reg_tx_data_12_sn_m2.INIT = 4'h1; + LUT2 plm_scr2_scram_reg_tx_data_12_sn_m2 ( + .I0(plm_reg_dis_6103[0]), + .I1(plm_scr2_reg_skp[1]), + .O(plm_scr2_reg_tx_data_12_sn_m2_1) + ); + defparam plm_scr2_un1_reg_com_1_i_o4.INIT = 4'h1; + LUT2 plm_scr2_un1_reg_com_1_i_o4 ( + .I0(plm_scr2_reg_skp[0]), + .I1(plm_scr2_reg_skp[1]), + .O(plm_scr2_N_20985_i) + ); + defparam plm_scr2_lfsrs_reg_lfsr_two_12_0_iv_0_o2_12_.INIT = 4'h1; + LUT2 plm_scr2_lfsrs_reg_lfsr_two_12_0_iv_0_o2_12_ ( + .I0(plm_scr2_reg_com[0]), + .I1(plm_scr2_reg_com[1]), + .O(plm_scr2_N_25901_i) + ); + defparam plm_scr2_one_adv2_1_13_.INIT = 4'h6; + LUT2 plm_scr2_one_adv2_1_13_ ( + .I0(plm_scr2_reg_lfsr_one_8__1168), + .I1(plm_scr2_reg_lfsr_one_9__1167), + .O(plm_scr2_one_adv2_1_13__1136) + ); + defparam plm_scr2_one_adv2_1_11_.INIT = 4'h6; + LUT2 plm_scr2_one_adv2_1_11_ ( + .I0(plm_scr2_reg_lfsr_one_6__1170), + .I1(plm_scr2_reg_lfsr_one_7__1169), + .O(plm_scr2_one_adv2_1_11__1135) + ); + defparam plm_scr2_one_adv2_1_9_.INIT = 4'h6; + LUT2 plm_scr2_one_adv2_1_9_ ( + .I0(plm_scr2_reg_lfsr_one_4__1172), + .I1(plm_scr2_reg_lfsr_one_5__1171), + .O(plm_scr2_one_adv2_1_9__1139) + ); + defparam plm_scr2_one_adv2_1_6_.INIT = 4'h6; + LUT2 plm_scr2_one_adv2_1_6_ ( + .I0(plm_scr2_reg_lfsr_one_1__555), + .I1(plm_scr2_reg_lfsr_one_12__1165), + .O(plm_scr2_one_adv2_1_6__1138) + ); + defparam plm_scr2_one_adv2_1_5_.INIT = 4'h6; + LUT2 plm_scr2_one_adv2_1_5_ ( + .I0(plm_scr2_reg_lfsr_one_2__1173), + .I1(plm_scr2_reg_lfsr_one_13__559), + .O(plm_scr2_one_adv2_1_5__1142) + ); + defparam plm_scr2_two_adv2_1_14_.INIT = 4'h6; + LUT2 plm_scr2_two_adv2_1_14_ ( + .I0(plm_scr2_reg_lfsr_two[9]), + .I1(plm_scr2_reg_lfsr_two[10]), + .O(plm_scr2_two_adv2_1_14__1146) + ); + defparam plm_scr2_two_adv2_1_12_.INIT = 4'h6; + LUT2 plm_scr2_two_adv2_1_12_ ( + .I0(plm_scr2_reg_lfsr_two[7]), + .I1(plm_scr2_reg_lfsr_two[8]), + .O(plm_scr2_two_adv2_1_12__1137) + ); + defparam plm_scr2_two_adv2_1_10_.INIT = 4'h6; + LUT2 plm_scr2_two_adv2_1_10_ ( + .I0(plm_scr2_reg_lfsr_two[5]), + .I1(plm_scr2_reg_lfsr_two[6]), + .O(plm_scr2_two_adv2_1_10__1140) + ); + defparam plm_scr2_two_adv2_0_4_.INIT = 4'h6; + LUT2 plm_scr2_two_adv2_0_4_ ( + .I0(plm_scr2_reg_lfsr_two_0__482), + .I1(plm_scr2_reg_lfsr_two_1__668), + .O(plm_scr2_two_adv2_0[4]) + ); + defparam plm_scr2_lfsrs_reg_lfsr_one32_i.INIT = 4'h7; + LUT2 plm_scr2_lfsrs_reg_lfsr_one32_i ( + .I0(plm_scr2_reg_skp[0]), + .I1(plm_scr2_reg_skp[1]), + .O(plm_scr2_reg_lfsr_one32_i) + ); + defparam plm_scr2_lfsrs_reg_lfsr_two_12_iv_i_o4_15_.INIT = 8'h23; + LUT3 plm_scr2_lfsrs_reg_lfsr_two_12_iv_i_o4_15_ ( + .I0(plm_scr2_reg_com[1]), + .I1(plm_scr2_reg_skp[0]), + .I2(plm_scr2_reg_skp[1]), + .O(plm_scr2_reg_lfsr_two_12_iv_i_o4_0[15]) + ); + defparam plm_scr2_lfsrs_reg_lfsr_two_12_iv_i_o2_15_.INIT = 8'h15; + LUT3 plm_scr2_lfsrs_reg_lfsr_two_12_iv_i_o2_15_ ( + .I0(plm_scr2_reg_com[0]), + .I1(plm_scr2_reg_com[1]), + .I2(plm_scr2_reg_skp[0]), + .O(plm_scr2_N_20984_i) + ); + defparam plm_scr2_two_adv2_15_.INIT = 16'h6996; + LUT4 plm_scr2_two_adv2_15_ ( + .I0(plm_scr2_reg_lfsr_two[10]), + .I1(plm_scr2_reg_lfsr_two_11__483), + .I2(plm_scr2_reg_lfsr_two_12__669), + .I3(plm_scr2_reg_lfsr_two_15__426), + .O(plm_scr2_two_adv2_15__1145) + ); + defparam plm_scr2_two_adv2_10_.INIT = 8'h96; + LUT3 plm_scr2_two_adv2_10_ ( + .I0(plm_scr2_reg_lfsr_two[7]), + .I1(plm_scr2_reg_lfsr_two[10]), + .I2(plm_scr2_two_adv2_1_10__1140), + .O(plm_scr2_two_adv2_10__1151) + ); + defparam plm_scr2_one_adv2_12_.INIT = 8'h96; + LUT3 plm_scr2_one_adv2_12_ ( + .I0(plm_scr2_one_adv2_1_13__1136), + .I1(plm_scr2_reg_lfsr_one_7__1169), + .I2(plm_scr2_reg_lfsr_one_12__1165), + .O(plm_scr2_one_adv2_12__1149) + ); + defparam plm_scr2_one_adv2_11_.INIT = 8'h96; + LUT3 plm_scr2_one_adv2_11_ ( + .I0(plm_scr2_one_adv2_1_11__1135), + .I1(plm_scr2_reg_lfsr_one_8__1168), + .I2(plm_scr2_reg_lfsr_one_11__646), + .O(plm_scr2_one_adv2_11__1150) + ); + defparam plm_scr2_one_adv2_10_.INIT = 8'h96; + LUT3 plm_scr2_one_adv2_10_ ( + .I0(plm_scr2_one_adv2_1_11__1135), + .I1(plm_scr2_reg_lfsr_one_5__1171), + .I2(plm_scr2_reg_lfsr_one_10__1166), + .O(plm_scr2_one_adv2_10__1152) + ); + defparam plm_scr2_one_adv2_2_.INIT = 8'h96; + LUT3 plm_scr2_one_adv2_2_ ( + .I0(plm_scr2_one_adv2_1_5__1142), + .I1(plm_scr2_reg_lfsr_one_14__675), + .I2(plm_scr2_reg_lfsr_one_15__556), + .O(plm_scr2_one_adv2_2__1162) + ); + defparam plm_scr2_one_adv2_1_.INIT = 8'h96; + LUT3 plm_scr2_one_adv2_1_ ( + .I0(plm_scr2_one_adv2_1_6__1138), + .I1(plm_scr2_reg_lfsr_one_13__559), + .I2(plm_scr2_reg_lfsr_one_14__675), + .O(plm_scr2_one_adv2_1__1163) + ); + defparam plm_scr2_two_adv2_12_.INIT = 8'h96; + LUT3 plm_scr2_two_adv2_12_ ( + .I0(plm_scr2_reg_lfsr_two[9]), + .I1(plm_scr2_reg_lfsr_two_12__669), + .I2(plm_scr2_two_adv2_1_12__1137), + .O(plm_scr2_two_adv2_12__1148) + ); + defparam plm_scr2_one_adv2_15_.INIT = 16'h6996; + LUT4 plm_scr2_one_adv2_15_ ( + .I0(plm_scr2_reg_lfsr_one_10__1166), + .I1(plm_scr2_reg_lfsr_one_11__646), + .I2(plm_scr2_reg_lfsr_one_12__1165), + .I3(plm_scr2_reg_lfsr_one_15__556), + .O(plm_scr2_one_adv2_15__1143) + ); + defparam plm_scr2_one_adv2_14_.INIT = 16'h6996; + LUT4 plm_scr2_one_adv2_14_ ( + .I0(plm_scr2_reg_lfsr_one_9__1167), + .I1(plm_scr2_reg_lfsr_one_10__1166), + .I2(plm_scr2_reg_lfsr_one_11__646), + .I3(plm_scr2_reg_lfsr_one_14__675), + .O(plm_scr2_one_adv2_14__1144) + ); + defparam plm_scr2_one_adv2_13_.INIT = 8'h96; + LUT3 plm_scr2_one_adv2_13_ ( + .I0(plm_scr2_one_adv2_1_13__1136), + .I1(plm_scr2_reg_lfsr_one_10__1166), + .I2(plm_scr2_reg_lfsr_one_13__559), + .O(plm_scr2_one_adv2_13__1147) + ); + defparam plm_scr2_input_decoder_reg_skp_3_0_a2_1_4_1_.INIT = 16'h0080; + LUT4_L plm_scr2_input_decoder_reg_skp_3_0_a2_1_4_1_ ( + .I0(plm_scr2_reg_raw_char[10]), + .I1(plm_scr2_reg_raw_char[11]), + .I2(plm_scr2_reg_raw_char[12]), + .I3(plm_scr2_reg_raw_char[14]), + .LO(plm_scr2_reg_skp_3_0_a2_1_4[1]) + ); + defparam plm_scr2_input_decoder_reg_com_4_0_a2_1_4_0_.INIT = 16'h0080; + LUT4_L plm_scr2_input_decoder_reg_com_4_0_a2_1_4_0_ ( + .I0(plm_scr2_reg_raw_char[2]), + .I1(plm_scr2_reg_raw_char[3]), + .I2(plm_scr2_reg_raw_char[4]), + .I3(plm_scr2_reg_raw_char[6]), + .LO(plm_scr2_reg_com_4_0_a2_1_4[0]) + ); + defparam plm_scr2_one_adv2_0_.INIT = 8'h96; + LUT3 plm_scr2_one_adv2_0_ ( + .I0(N_12081_1), + .I1(plm_scr2_reg_lfsr_one_12__1165), + .I2(plm_scr2_reg_lfsr_one_13__559), + .O(plm_scr2_one_adv2_0__1164) + ); + defparam plm_scr2_lfsrs_reg_lfsr_two_12_iv_i_a2_15_.INIT = 4'h4; + LUT2_L plm_scr2_lfsrs_reg_lfsr_two_12_iv_i_a2_15_ ( + .I0(plm_scr2_reg_lfsr_two_12_iv_i_o4_0[15]), + .I1(plm_scr2_one_adv2_15__1143), + .LO(plm_scr2_reg_lfsr_two_12_iv_i_a2_0[15]) + ); + defparam plm_scr2_lfsrs_reg_lfsr_two_12_iv_i_a2_0_13_.INIT = 16'h8228; + LUT4 plm_scr2_lfsrs_reg_lfsr_two_12_iv_i_a2_0_13_ ( + .I0(plm_scr2_reg_lfsr_one29_0_a4_0_a2), + .I1(plm_scr2_reg_lfsr_two[8]), + .I2(plm_scr2_reg_lfsr_two_13__484), + .I3(plm_scr2_two_adv2_1_14__1146), + .O(plm_scr2_reg_lfsr_two_12_iv_i_a2_0_0_13_) + ); + defparam plm_scr2_lfsrs_reg_lfsr_two_12_iv_i_a2_0_11_.INIT = 16'h8228; + LUT4 plm_scr2_lfsrs_reg_lfsr_two_12_iv_i_a2_0_11_ ( + .I0(plm_scr2_reg_lfsr_one29_0_a4_0_a2), + .I1(plm_scr2_reg_lfsr_two[6]), + .I2(plm_scr2_reg_lfsr_two_11__483), + .I3(plm_scr2_two_adv2_1_12__1137), + .O(plm_scr2_reg_lfsr_two_12_iv_i_a2_0_0_11_) + ); + defparam plm_scr2_lfsrs_reg_lfsr_two_12_iv_i_a2_0_2_.INIT = 16'h8448; + LUT4 plm_scr2_lfsrs_reg_lfsr_two_12_iv_i_a2_0_2_ ( + .I0(N_13591_i_0), + .I1(plm_scr2_reg_lfsr_one29_0_a4_0_a2), + .I2(plm_scr2_reg_lfsr_two_14__667), + .I3(plm_scr2_reg_lfsr_two_15__426), + .O(plm_scr2_reg_lfsr_two_12_iv_i_a2_0_0_2_) + ); + defparam plm_scr2_lfsrs_reg_lfsr_two_12_iv_i_a2_0_1_.INIT = 16'h8448; + LUT4 plm_scr2_lfsrs_reg_lfsr_two_12_iv_i_a2_0_1_ ( + .I0(N_20990_i_0), + .I1(plm_scr2_reg_lfsr_one29_0_a4_0_a2), + .I2(plm_scr2_reg_lfsr_two_13__484), + .I3(plm_scr2_reg_lfsr_two_14__667), + .O(plm_scr2_reg_lfsr_two_12_iv_i_a2_0_0_1_) + ); + defparam plm_scr2_lfsrs_reg_lfsr_one_12_iv_i_a2_12_.INIT = 4'h4; + LUT2 plm_scr2_lfsrs_reg_lfsr_one_12_iv_i_a2_12_ ( + .I0(plm_scr2_reg_lfsr_two_12_iv_i_o4_0[15]), + .I1(plm_scr2_reg_lfsr_two_12__669), + .O(plm_scr2_reg_lfsr_one_12_iv_i_a2_0_12_) + ); + defparam plm_scr2_lfsrs_reg_lfsr_one_12_iv_i_a2_0_10_.INIT = 4'h8; + LUT2_L plm_scr2_lfsrs_reg_lfsr_one_12_iv_i_a2_0_10_ ( + .I0(plm_scr2_reg_lfsr_one29_0_a4_0_a2), + .I1(plm_scr2_one_adv2_10__1152), + .LO(plm_scr2_reg_lfsr_one_12_iv_i_a2_0_0_10_) + ); + defparam plm_scr2_lfsrs_reg_lfsr_one_12_iv_i_a2_7_.INIT = 4'h4; + LUT2 plm_scr2_lfsrs_reg_lfsr_one_12_iv_i_a2_7_ ( + .I0(plm_scr2_reg_lfsr_two_12_iv_i_o4_0[15]), + .I1(plm_scr2_reg_lfsr_two[7]), + .O(plm_scr2_reg_lfsr_one_12_iv_i_a2_0_7_) + ); + defparam plm_scr2_lfsrs_reg_lfsr_one_12_iv_i_a2_3_.INIT = 4'h4; + LUT2 plm_scr2_lfsrs_reg_lfsr_one_12_iv_i_a2_3_ ( + .I0(plm_scr2_reg_lfsr_two_12_iv_i_o4_0[15]), + .I1(plm_scr2_reg_lfsr_two_3__670), + .O(plm_scr2_reg_lfsr_one_12_iv_i_a2_0_3_) + ); + defparam plm_scr2_two_adv2_6_.INIT = 16'h6996; + LUT4 plm_scr2_two_adv2_6_ ( + .I0(N_20989_i_0), + .I1(N_20990_i_0), + .I2(plm_scr2_reg_lfsr_two_2__674), + .I3(plm_scr2_reg_lfsr_two[6]), + .O(plm_scr2_two_adv2_6__1157) + ); + defparam plm_scr2_two_adv2_7_.INIT = 16'h6996; + LUT4 plm_scr2_two_adv2_7_ ( + .I0(N_13591_i_0), + .I1(N_20988_i_0), + .I2(plm_scr2_reg_lfsr_two_3__670), + .I3(plm_scr2_reg_lfsr_two[7]), + .O(plm_scr2_two_adv2_7__1155) + ); + defparam plm_scr2_two_adv2_8_.INIT = 16'h6996; + LUT4 plm_scr2_two_adv2_8_ ( + .I0(N_20989_i_0), + .I1(plm_scr2_reg_lfsr_two_4__671), + .I2(plm_scr2_reg_lfsr_two[5]), + .I3(plm_scr2_reg_lfsr_two[8]), + .O(plm_scr2_two_adv2_8__1154) + ); + defparam plm_scr2_one_adv2_6_.INIT = 16'h6996; + LUT4 plm_scr2_one_adv2_6_ ( + .I0(N_13489_i_0), + .I1(plm_scr2_one_adv2_1_6__1138), + .I2(plm_scr2_reg_lfsr_one_2__1173), + .I3(plm_scr2_reg_lfsr_one_6__1170), + .O(plm_scr2_one_adv2_6__1158) + ); + defparam plm_scr2_one_adv2_7_.INIT = 16'h6996; + LUT4 plm_scr2_one_adv2_7_ ( + .I0(G_324_560), + .I1(plm_scr2_reg_lfsr_one_2__1173), + .I2(plm_scr2_reg_lfsr_one_4__1172), + .I3(plm_scr2_reg_lfsr_one_7__1169), + .O(plm_scr2_one_adv2_7__1156) + ); + defparam plm_scr2_one_adv2_9_.INIT = 16'h6996; + LUT4 plm_scr2_one_adv2_9_ ( + .I0(plm_scr2_one_adv2_1_9__1139), + .I1(plm_scr2_reg_lfsr_one_6__1170), + .I2(plm_scr2_reg_lfsr_one_9__1167), + .I3(plm_scr2_reg_lfsr_one_15__556), + .O(plm_scr2_one_adv2_9__1153) + ); + defparam plm_scr2_one_adv2_8_.INIT = 8'h96; + LUT3 plm_scr2_one_adv2_8_ ( + .I0(N_13489_i_0), + .I1(plm_scr2_one_adv2_1_9__1139), + .I2(plm_scr2_reg_lfsr_one_8__1168), + .O(plm_scr2_one_adv2_8__1141) + ); + defparam plm_scr2_one_adv2_4_.INIT = 8'h96; + LUT3 plm_scr2_one_adv2_4_ ( + .I0(G_323_557), + .I1(plm_scr2_reg_lfsr_one_4__1172), + .I2(plm_scr2_reg_lfsr_one_14__675), + .O(plm_scr2_one_adv2_4__1160) + ); + defparam plm_scr2_input_decoder_reg_com_4_0_a2_1_0_.INIT = 16'h0200; + LUT4 plm_scr2_input_decoder_reg_com_4_0_a2_1_0_ ( + .I0(plm_scr2_reg_com_4_0_a2_1_4[0]), + .I1(plm_scr2_reg_raw_char[0]), + .I2(plm_scr2_reg_raw_char[1]), + .I3(plm_reg_raw_char_is_k[0]), + .O(plm_scr2_reg_com_4_1[0]) + ); + defparam plm_scr2_input_decoder_reg_skp_3_0_a2_1_1_.INIT = 16'h0200; + LUT4 plm_scr2_input_decoder_reg_skp_3_0_a2_1_1_ ( + .I0(plm_scr2_reg_skp_3_0_a2_1_4[1]), + .I1(plm_scr2_reg_raw_char[8]), + .I2(plm_scr2_reg_raw_char[9]), + .I3(plm_reg_raw_char_is_k[1]), + .O(plm_scr2_reg_skp_3_1[1]) + ); + defparam plm_scr2_scram_reg_tx_data_12_2_m2_0_am_6_.INIT = 8'h63; + LUT3 plm_scr2_scram_reg_tx_data_12_2_m2_0_am_6_ ( + .I0(plm_reg_dis_6103[0]), + .I1(plm_scr2_reg_dat[6]), + .I2(plm_scr2_reg_lfsr_one_9__1167), + .O(plm_scr2_reg_tx_data_12_2_m2_0_am[6]) + ); + defparam plm_scr2_scram_reg_tx_data_12_2_m2_0_bm_6_.INIT = 8'hC9; + LUT3 plm_scr2_scram_reg_tx_data_12_2_m2_0_bm_6_ ( + .I0(plm_scr2_reg_com[1]), + .I1(plm_scr2_reg_dat[6]), + .I2(plm_scr2_reg_lfsr_two[9]), + .O(plm_scr2_reg_tx_data_12_2_m2_0_bm[6]) + ); + MUXF5 plm_scr2_scram_reg_tx_data_12_2_m2_0_6_ ( + .I0(plm_scr2_reg_tx_data_12_2_m2_0_am[6]), + .I1(plm_scr2_reg_tx_data_12_2_m2_0_bm[6]), + .O(plm_scr2_reg_tx_data_12_2_m2_0[6]), + .S(plm_scr2_reg_tx_data_12_sn_m2_1) + ); + defparam plm_scr2_scram_reg_tx_data_12_2_m2_0_am_5_.INIT = 8'h63; + LUT3 plm_scr2_scram_reg_tx_data_12_2_m2_0_am_5_ ( + .I0(plm_reg_dis_6103[0]), + .I1(plm_scr2_reg_dat[5]), + .I2(plm_scr2_reg_lfsr_one_10__1166), + .O(plm_scr2_reg_tx_data_12_2_m2_0_am[5]) + ); + defparam plm_scr2_scram_reg_tx_data_12_2_m2_0_bm_5_.INIT = 8'hC9; + LUT3 plm_scr2_scram_reg_tx_data_12_2_m2_0_bm_5_ ( + .I0(plm_scr2_reg_com[1]), + .I1(plm_scr2_reg_dat[5]), + .I2(plm_scr2_reg_lfsr_two[10]), + .O(plm_scr2_reg_tx_data_12_2_m2_0_bm[5]) + ); + MUXF5 plm_scr2_scram_reg_tx_data_12_2_m2_0_5_ ( + .I0(plm_scr2_reg_tx_data_12_2_m2_0_am[5]), + .I1(plm_scr2_reg_tx_data_12_2_m2_0_bm[5]), + .O(plm_scr2_reg_tx_data_12_2_m2_0[5]), + .S(plm_scr2_reg_tx_data_12_sn_m2_1) + ); + defparam plm_scr2_scram_reg_tx_data_12_2_m2_0_am_4_.INIT = 8'h63; + LUT3 plm_scr2_scram_reg_tx_data_12_2_m2_0_am_4_ ( + .I0(plm_reg_dis_6103[0]), + .I1(plm_scr2_reg_dat[4]), + .I2(plm_scr2_reg_lfsr_one_11__646), + .O(plm_scr2_reg_tx_data_12_2_m2_0_am[4]) + ); + defparam plm_scr2_scram_reg_tx_data_12_2_m2_0_bm_4_.INIT = 8'hC9; + LUT3 plm_scr2_scram_reg_tx_data_12_2_m2_0_bm_4_ ( + .I0(plm_scr2_reg_com[1]), + .I1(plm_scr2_reg_dat[4]), + .I2(plm_scr2_reg_lfsr_two_11__483), + .O(plm_scr2_reg_tx_data_12_2_m2_0_bm[4]) + ); + MUXF5 plm_scr2_scram_reg_tx_data_12_2_m2_0_4_ ( + .I0(plm_scr2_reg_tx_data_12_2_m2_0_am[4]), + .I1(plm_scr2_reg_tx_data_12_2_m2_0_bm[4]), + .O(plm_scr2_reg_tx_data_12_2_m2_0[4]), + .S(plm_scr2_reg_tx_data_12_sn_m2_1) + ); + defparam plm_scr2_scram_reg_tx_data_12_2_m2_0_am_3_.INIT = 8'h63; + LUT3 plm_scr2_scram_reg_tx_data_12_2_m2_0_am_3_ ( + .I0(plm_reg_dis_6103[0]), + .I1(plm_scr2_reg_dat[3]), + .I2(plm_scr2_reg_lfsr_one_12__1165), + .O(plm_scr2_reg_tx_data_12_2_m2_0_am[3]) + ); + defparam plm_scr2_scram_reg_tx_data_12_2_m2_0_bm_3_.INIT = 8'hC9; + LUT3 plm_scr2_scram_reg_tx_data_12_2_m2_0_bm_3_ ( + .I0(plm_scr2_reg_com[1]), + .I1(plm_scr2_reg_dat[3]), + .I2(plm_scr2_reg_lfsr_two_12__669), + .O(plm_scr2_reg_tx_data_12_2_m2_0_bm[3]) + ); + MUXF5 plm_scr2_scram_reg_tx_data_12_2_m2_0_3_ ( + .I0(plm_scr2_reg_tx_data_12_2_m2_0_am[3]), + .I1(plm_scr2_reg_tx_data_12_2_m2_0_bm[3]), + .O(plm_scr2_reg_tx_data_12_2_m2_0[3]), + .S(plm_scr2_reg_tx_data_12_sn_m2_1) + ); + defparam plm_scr2_scram_reg_tx_data_12_2_m2_0_am_2_.INIT = 8'h63; + LUT3 plm_scr2_scram_reg_tx_data_12_2_m2_0_am_2_ ( + .I0(plm_reg_dis_6103[0]), + .I1(plm_scr2_reg_dat[2]), + .I2(plm_scr2_reg_lfsr_one_13__559), + .O(plm_scr2_reg_tx_data_12_2_m2_0_am[2]) + ); + defparam plm_scr2_scram_reg_tx_data_12_2_m2_0_bm_2_.INIT = 8'hC9; + LUT3 plm_scr2_scram_reg_tx_data_12_2_m2_0_bm_2_ ( + .I0(plm_scr2_reg_com[1]), + .I1(plm_scr2_reg_dat[2]), + .I2(plm_scr2_reg_lfsr_two_13__484), + .O(plm_scr2_reg_tx_data_12_2_m2_0_bm[2]) + ); + MUXF5 plm_scr2_scram_reg_tx_data_12_2_m2_0_2_ ( + .I0(plm_scr2_reg_tx_data_12_2_m2_0_am[2]), + .I1(plm_scr2_reg_tx_data_12_2_m2_0_bm[2]), + .O(plm_scr2_reg_tx_data_12_2_m2_0[2]), + .S(plm_scr2_reg_tx_data_12_sn_m2_1) + ); + defparam plm_scr2_scram_reg_tx_data_12_2_m2_0_am_1_.INIT = 8'h63; + LUT3 plm_scr2_scram_reg_tx_data_12_2_m2_0_am_1_ ( + .I0(plm_reg_dis_6103[0]), + .I1(plm_scr2_reg_dat[1]), + .I2(plm_scr2_reg_lfsr_one_14__675), + .O(plm_scr2_reg_tx_data_12_2_m2_0_am[1]) + ); + defparam plm_scr2_scram_reg_tx_data_12_2_m2_0_bm_1_.INIT = 8'hC9; + LUT3 plm_scr2_scram_reg_tx_data_12_2_m2_0_bm_1_ ( + .I0(plm_scr2_reg_com[1]), + .I1(plm_scr2_reg_dat[1]), + .I2(plm_scr2_reg_lfsr_two_14__667), + .O(plm_scr2_reg_tx_data_12_2_m2_0_bm[1]) + ); + MUXF5 plm_scr2_scram_reg_tx_data_12_2_m2_0_1_ ( + .I0(plm_scr2_reg_tx_data_12_2_m2_0_am[1]), + .I1(plm_scr2_reg_tx_data_12_2_m2_0_bm[1]), + .O(plm_scr2_reg_tx_data_12_2_m2_0[1]), + .S(plm_scr2_reg_tx_data_12_sn_m2_1) + ); + defparam plm_scr2_lfsrs_reg_lfsr_two_12_iv_0_a2_0_9_.INIT = 16'h4884; + LUT4 plm_scr2_lfsrs_reg_lfsr_two_12_iv_0_a2_0_9_ ( + .I0(N_20988_i_0), + .I1(plm_scr2_reg_lfsr_one29_0_a4_0_a2), + .I2(plm_scr2_reg_lfsr_two[9]), + .I3(plm_scr2_two_adv2_1_10__1140), + .O(plm_scr2_reg_lfsr_two_12_iv_0_a2_0_0_9_) + ); + defparam plm_scr2_lfsrs_reg_lfsr_two_12_iv_0_a2_8_.INIT = 4'h1; + LUT2_L plm_scr2_lfsrs_reg_lfsr_two_12_iv_0_a2_8_ ( + .I0(plm_scr2_reg_lfsr_two_12_iv_i_o4_0[15]), + .I1(plm_scr2_one_adv2_8__1141), + .LO(plm_scr2_reg_lfsr_two_12_iv_0_a2_0[8]) + ); + defparam plm_scr2_lfsrs_reg_lfsr_two_12_iv_0_a2_5_.INIT = 16'h1221; + LUT4 plm_scr2_lfsrs_reg_lfsr_two_12_iv_0_a2_5_ ( + .I0(G_323_557), + .I1(plm_scr2_reg_lfsr_two_12_iv_i_o4_0[15]), + .I2(plm_scr2_one_adv2_1_5__1142), + .I3(plm_scr2_reg_lfsr_one_5__1171), + .O(plm_scr2_reg_lfsr_two_12_iv_0_a2[5]) + ); + defparam plm_scr2_lfsrs_reg_lfsr_two_12_iv_i_a2_0_4_.INIT = 16'h9060; + LUT4 plm_scr2_lfsrs_reg_lfsr_two_12_iv_i_a2_0_4_ ( + .I0(N_20988_i_0), + .I1(N_20991_i_0), + .I2(plm_scr2_reg_lfsr_one29_0_a4_0_a2), + .I3(plm_scr2_two_adv2_0[4]), + .O(plm_scr2_reg_lfsr_two_12_iv_i_a2_0_0_4_) + ); + defparam plm_scr2_lfsrs_reg_lfsr_two_12_iv_i_a2_0_0_.INIT = 8'h48; + LUT3 plm_scr2_lfsrs_reg_lfsr_two_12_iv_i_a2_0_0_ ( + .I0(N_12007_1_0), + .I1(plm_scr2_reg_lfsr_one29_0_a4_0_a2), + .I2(plm_scr2_reg_lfsr_two_12__669), + .O(plm_scr2_reg_lfsr_two_12_iv_i_a2_0_0_0_) + ); + defparam plm_scr2_lfsrs_reg_lfsr_one_12_iv_i_a2_0_9_.INIT = 4'h8; + LUT2_L plm_scr2_lfsrs_reg_lfsr_one_12_iv_i_a2_0_9_ ( + .I0(plm_scr2_reg_lfsr_one29_0_a4_0_a2), + .I1(plm_scr2_one_adv2_9__1153), + .LO(plm_scr2_reg_lfsr_one_12_iv_i_a2_0_0_9_) + ); + defparam plm_scr2_lfsrs_reg_lfsr_one_12_iv_i_a2_0_8_.INIT = 4'h8; + LUT2_L plm_scr2_lfsrs_reg_lfsr_one_12_iv_i_a2_0_8_ ( + .I0(plm_scr2_reg_lfsr_one29_0_a4_0_a2), + .I1(plm_scr2_one_adv2_8__1141), + .LO(plm_scr2_reg_lfsr_one_12_iv_i_a2_0_0_8_) + ); + defparam plm_scr2_lfsrs_reg_lfsr_one_12_iv_i_a2_0_6_.INIT = 4'h8; + LUT2_L plm_scr2_lfsrs_reg_lfsr_one_12_iv_i_a2_0_6_ ( + .I0(plm_scr2_reg_lfsr_one29_0_a4_0_a2), + .I1(plm_scr2_one_adv2_6__1158), + .LO(plm_scr2_reg_lfsr_one_12_iv_i_a2_0_0_6_) + ); + defparam plm_scr2_lfsrs_reg_lfsr_one_12_iv_i_a2_0_5_.INIT = 16'h8448; + LUT4_L plm_scr2_lfsrs_reg_lfsr_one_12_iv_i_a2_0_5_ ( + .I0(G_323_557), + .I1(plm_scr2_reg_lfsr_one29_0_a4_0_a2), + .I2(plm_scr2_one_adv2_1_5__1142), + .I3(plm_scr2_reg_lfsr_one_5__1171), + .LO(plm_scr2_reg_lfsr_one_12_iv_i_a2_0_5_) + ); + defparam plm_scr2_scram_reg_tx_data_12_2_am_7_.INIT = 8'h9C; + LUT3 plm_scr2_scram_reg_tx_data_12_2_am_7_ ( + .I0(plm_reg_dis_6103[0]), + .I1(plm_scr2_reg_dat[7]), + .I2(plm_scr2_reg_lfsr_one_8__1168), + .O(plm_scr2_reg_tx_data_12_2_am_0_7_) + ); + defparam plm_scr2_scram_reg_tx_data_12_2_bm_7_.INIT = 8'h36; + LUT3 plm_scr2_scram_reg_tx_data_12_2_bm_7_ ( + .I0(plm_scr2_reg_com[1]), + .I1(plm_scr2_reg_dat[7]), + .I2(plm_scr2_reg_lfsr_two[8]), + .O(plm_scr2_reg_tx_data_12_2_bm_0_7_) + ); + MUXF5 plm_scr2_scram_reg_tx_data_12_2_7_ ( + .I0(plm_scr2_reg_tx_data_12_2_am_0_7_), + .I1(plm_scr2_reg_tx_data_12_2_bm_0_7_), + .O(plm_scr2_reg_tx_data_12_7_), + .S(plm_scr2_reg_tx_data_12_sn_m2_1) + ); + defparam plm_scr2_scram_reg_tx_data_12_2_am_0_.INIT = 8'h9C; + LUT3 plm_scr2_scram_reg_tx_data_12_2_am_0_ ( + .I0(plm_reg_dis_6103[0]), + .I1(plm_scr2_reg_dat[0]), + .I2(plm_scr2_reg_lfsr_one_15__556), + .O(plm_scr2_reg_tx_data_12_2_am_0_0_) + ); + defparam plm_scr2_scram_reg_tx_data_12_2_bm_0_.INIT = 8'h36; + LUT3 plm_scr2_scram_reg_tx_data_12_2_bm_0_ ( + .I0(plm_scr2_reg_com[1]), + .I1(plm_scr2_reg_dat[0]), + .I2(plm_scr2_reg_lfsr_two_15__426), + .O(plm_scr2_reg_tx_data_12_2_bm_0_0_) + ); + MUXF5 plm_scr2_scram_reg_tx_data_12_2_0_ ( + .I0(plm_scr2_reg_tx_data_12_2_am_0_0_), + .I1(plm_scr2_reg_tx_data_12_2_bm_0_0_), + .O(plm_scr2_reg_tx_data_12_0_), + .S(plm_scr2_reg_tx_data_12_sn_m2_1) + ); + defparam plm_scr2_two_adv2_5_.INIT = 16'h6996; + LUT4 plm_scr2_two_adv2_5_ ( + .I0(G_349_427), + .I1(plm_scr2_reg_lfsr_two_1__668), + .I2(plm_scr2_reg_lfsr_two_2__674), + .I3(plm_scr2_reg_lfsr_two[5]), + .O(plm_scr2_two_adv2_5__1159) + ); + defparam plm_scr2_one_adv2_3_.INIT = 16'h6996; + LUT4 plm_scr2_one_adv2_3_ ( + .I0(G_324_560), + .I1(N_12081_1), + .I2(plm_scr2_reg_lfsr_one_12__1165), + .I3(plm_scr2_reg_lfsr_one_14__675), + .O(plm_scr2_one_adv2_3__1161) + ); + defparam plm_scr2_lfsrs_reg_lfsr_two_12_iv_i_0_14_.INIT = 8'h8A; + LUT3_L plm_scr2_lfsrs_reg_lfsr_two_12_iv_i_0_14_ ( + .I0(plm_scr2_N_20984_i), + .I1(plm_scr2_reg_lfsr_two_12_iv_i_o4_0[15]), + .I2(plm_scr2_one_adv2_14__1144), + .LO(plm_scr2_reg_lfsr_two_12_iv_i_0[14]) + ); + defparam plm_scr2_lfsrs_reg_lfsr_two_12_iv_0_a2_0_3_.INIT = 16'h6090; + LUT4_L plm_scr2_lfsrs_reg_lfsr_two_12_iv_0_a2_0_3_ ( + .I0(G_349_427), + .I1(N_20989_i_0), + .I2(plm_scr2_reg_lfsr_one29_0_a4_0_a2), + .I3(plm_scr2_reg_lfsr_two_12__669), + .LO(plm_scr2_reg_lfsr_two_12_iv_0_a2_0_0_3_) + ); + defparam plm_scr2_scram_N_13503_i_0_i.INIT = 8'h9C; + LUT3_L plm_scr2_scram_N_13503_i_0_i ( + .I0(plm_reg_dis_6103[1]), + .I1(plm_scr2_reg_dat[8]), + .I2(plm_scr2_reg_lfsr_one_15__556), + .LO(plm_scr2_N_13503_i_0_i) + ); + defparam plm_scr2_scram_N_13525_i.INIT = 4'h1; + LUT1_L plm_scr2_scram_N_13525_i ( + .I0(plm_scr2_reg_tx_data_12_2_m2_0[6]), + .LO(plm_scr2_N_13525_i) + ); + defparam plm_scr2_scram_N_13524_i.INIT = 4'h1; + LUT1_L plm_scr2_scram_N_13524_i ( + .I0(plm_scr2_reg_tx_data_12_2_m2_0[5]), + .LO(plm_scr2_N_13524_i) + ); + defparam plm_scr2_scram_N_13523_i.INIT = 4'h1; + LUT1_L plm_scr2_scram_N_13523_i ( + .I0(plm_scr2_reg_tx_data_12_2_m2_0[4]), + .LO(plm_scr2_N_13523_i) + ); + defparam plm_scr2_scram_N_13522_i.INIT = 4'h1; + LUT1_L plm_scr2_scram_N_13522_i ( + .I0(plm_scr2_reg_tx_data_12_2_m2_0[3]), + .LO(plm_scr2_N_13522_i) + ); + defparam plm_scr2_scram_N_13521_i.INIT = 4'h1; + LUT1_L plm_scr2_scram_N_13521_i ( + .I0(plm_scr2_reg_tx_data_12_2_m2_0[2]), + .LO(plm_scr2_N_13521_i) + ); + defparam plm_scr2_scram_N_13520_i.INIT = 4'h1; + LUT1_L plm_scr2_scram_N_13520_i ( + .I0(plm_scr2_reg_tx_data_12_2_m2_0[1]), + .LO(plm_scr2_N_13520_i) + ); + defparam plm_scr2_input_decoder_reg_skp_3_0_a2_1_.INIT = 8'h02; + LUT3_L plm_scr2_input_decoder_reg_skp_3_0_a2_1_ ( + .I0(plm_scr2_reg_skp_3_1[1]), + .I1(plm_scr2_reg_raw_char[13]), + .I2(plm_scr2_reg_raw_char[15]), + .LO(plm_scr2_reg_skp_3[1]) + ); + defparam plm_scr2_input_decoder_reg_skp_4_0_a2_0_.INIT = 8'h02; + LUT3_L plm_scr2_input_decoder_reg_skp_4_0_a2_0_ ( + .I0(plm_scr2_reg_com_4_1[0]), + .I1(plm_scr2_reg_raw_char[5]), + .I2(plm_scr2_reg_raw_char[7]), + .LO(plm_scr2_reg_skp_4[0]) + ); + defparam plm_scr2_input_decoder_reg_com_3_0_a2_1_.INIT = 8'h80; + LUT3_L plm_scr2_input_decoder_reg_com_3_0_a2_1_ ( + .I0(plm_scr2_reg_skp_3_1[1]), + .I1(plm_scr2_reg_raw_char[13]), + .I2(plm_scr2_reg_raw_char[15]), + .LO(plm_scr2_reg_com_3[1]) + ); + defparam plm_scr2_input_decoder_reg_com_4_0_a2_0_.INIT = 8'h80; + LUT3_L plm_scr2_input_decoder_reg_com_4_0_a2_0_ ( + .I0(plm_scr2_reg_com_4_1[0]), + .I1(plm_scr2_reg_raw_char[5]), + .I2(plm_scr2_reg_raw_char[7]), + .LO(plm_scr2_reg_com_4[0]) + ); + defparam plm_scr2_scram_reg_tx_data_6_0_15_.INIT = 8'h9C; + LUT3_L plm_scr2_scram_reg_tx_data_6_0_15_ ( + .I0(plm_reg_dis_6103[1]), + .I1(plm_scr2_reg_dat[15]), + .I2(plm_scr2_reg_lfsr_one_8__1168), + .LO(plm_scr2_reg_tx_data_6[15]) + ); + defparam plm_scr2_scram_N_13515_i_0_i.INIT = 8'h9C; + LUT3_L plm_scr2_scram_N_13515_i_0_i ( + .I0(plm_reg_dis_6103[1]), + .I1(plm_scr2_reg_dat[14]), + .I2(plm_scr2_reg_lfsr_one_9__1167), + .LO(plm_scr2_N_13515_i_0_i) + ); + defparam plm_scr2_scram_N_13513_i_0_i.INIT = 8'h9C; + LUT3_L plm_scr2_scram_N_13513_i_0_i ( + .I0(plm_reg_dis_6103[1]), + .I1(plm_scr2_reg_dat[13]), + .I2(plm_scr2_reg_lfsr_one_10__1166), + .LO(plm_scr2_N_13513_i_0_i) + ); + defparam plm_scr2_scram_N_13511_i_0_i.INIT = 8'h9C; + LUT3_L plm_scr2_scram_N_13511_i_0_i ( + .I0(plm_reg_dis_6103[1]), + .I1(plm_scr2_reg_dat[12]), + .I2(plm_scr2_reg_lfsr_one_11__646), + .LO(plm_scr2_N_13511_i_0_i) + ); + defparam plm_scr2_scram_N_13509_i_0_i.INIT = 8'h9C; + LUT3_L plm_scr2_scram_N_13509_i_0_i ( + .I0(plm_reg_dis_6103[1]), + .I1(plm_scr2_reg_dat[11]), + .I2(plm_scr2_reg_lfsr_one_12__1165), + .LO(plm_scr2_N_13509_i_0_i) + ); + defparam plm_scr2_scram_N_13507_i_0_i.INIT = 8'h9C; + LUT3_L plm_scr2_scram_N_13507_i_0_i ( + .I0(plm_reg_dis_6103[1]), + .I1(plm_scr2_reg_dat[10]), + .I2(plm_scr2_reg_lfsr_one_13__559), + .LO(plm_scr2_N_13507_i_0_i) + ); + defparam plm_scr2_scram_N_13505_i_0_i.INIT = 8'h9C; + LUT3_L plm_scr2_scram_N_13505_i_0_i ( + .I0(plm_reg_dis_6103[1]), + .I1(plm_scr2_reg_dat[9]), + .I2(plm_scr2_reg_lfsr_one_14__675), + .LO(plm_scr2_N_13505_i_0_i) + ); + defparam plm_scr2_lfsrs_N_87798_i.INIT = 16'hF7B3; + LUT4_L plm_scr2_lfsrs_N_87798_i ( + .I0(plm_scr2_N_20985_i), + .I1(plm_scr2_N_25901_i), + .I2(plm_scr2_one_adv2_15__1143), + .I3(plm_scr2_reg_lfsr_two_15__426), + .LO(plm_scr2_N_87798_i) + ); + defparam plm_scr2_lfsrs_N_87828_i.INIT = 16'hF7B3; + LUT4_L plm_scr2_lfsrs_N_87828_i ( + .I0(plm_scr2_N_20985_i), + .I1(plm_scr2_N_25901_i), + .I2(plm_scr2_one_adv2_14__1144), + .I3(plm_scr2_reg_lfsr_two_14__667), + .LO(plm_scr2_N_87828_i) + ); + defparam plm_scr2_lfsrs_reg_lfsr_one_12_0_iv_i_13_.INIT = 16'hF7B3; + LUT4_L plm_scr2_lfsrs_reg_lfsr_one_12_0_iv_i_13_ ( + .I0(plm_scr2_N_20985_i), + .I1(plm_scr2_N_25901_i), + .I2(plm_scr2_one_adv2_13__1147), + .I3(plm_scr2_reg_lfsr_two_13__484), + .LO(plm_scr2_N_13589_i) + ); + defparam plm_scr2_lfsrs_N_85443_i.INIT = 16'hFDDD; + LUT4_L plm_scr2_lfsrs_N_85443_i ( + .I0(plm_scr2_N_20984_i), + .I1(plm_scr2_reg_lfsr_one_12_iv_i_a2_0_12_), + .I2(plm_scr2_reg_lfsr_one29_0_a4_0_a2), + .I3(plm_scr2_one_adv2_12__1149), + .LO(plm_scr2_N_85443_i) + ); + defparam plm_scr2_lfsrs_N_87827_i.INIT = 16'hF7B3; + LUT4_L plm_scr2_lfsrs_N_87827_i ( + .I0(plm_scr2_N_20985_i), + .I1(plm_scr2_N_25901_i), + .I2(plm_scr2_one_adv2_11__1150), + .I3(plm_scr2_reg_lfsr_two_11__483), + .LO(plm_scr2_N_87827_i) + ); + defparam plm_scr2_lfsrs_N_85442_i.INIT = 16'hDFDD; + LUT4_L plm_scr2_lfsrs_N_85442_i ( + .I0(plm_scr2_N_20984_i), + .I1(plm_scr2_reg_lfsr_one_12_iv_i_a2_0_0_10_), + .I2(plm_scr2_reg_lfsr_two_12_iv_i_o4_0[15]), + .I3(plm_scr2_reg_lfsr_two[10]), + .LO(plm_scr2_N_85442_i) + ); + defparam plm_scr2_lfsrs_N_85441_i.INIT = 16'hDFDD; + LUT4_L plm_scr2_lfsrs_N_85441_i ( + .I0(plm_scr2_N_20984_i), + .I1(plm_scr2_reg_lfsr_one_12_iv_i_a2_0_0_9_), + .I2(plm_scr2_reg_lfsr_two_12_iv_i_o4_0[15]), + .I3(plm_scr2_reg_lfsr_two[9]), + .LO(plm_scr2_N_85441_i) + ); + defparam plm_scr2_lfsrs_N_85440_i.INIT = 16'hDFDD; + LUT4_L plm_scr2_lfsrs_N_85440_i ( + .I0(plm_scr2_N_20984_i), + .I1(plm_scr2_reg_lfsr_one_12_iv_i_a2_0_0_8_), + .I2(plm_scr2_reg_lfsr_two_12_iv_i_o4_0[15]), + .I3(plm_scr2_reg_lfsr_two[8]), + .LO(plm_scr2_N_85440_i) + ); + defparam plm_scr2_lfsrs_N_85439_i.INIT = 16'hFDDD; + LUT4_L plm_scr2_lfsrs_N_85439_i ( + .I0(plm_scr2_N_20984_i), + .I1(plm_scr2_reg_lfsr_one_12_iv_i_a2_0_7_), + .I2(plm_scr2_reg_lfsr_one29_0_a4_0_a2), + .I3(plm_scr2_one_adv2_7__1156), + .LO(plm_scr2_N_85439_i) + ); + defparam plm_scr2_lfsrs_N_85438_i.INIT = 16'hDFDD; + LUT4_L plm_scr2_lfsrs_N_85438_i ( + .I0(plm_scr2_N_20984_i), + .I1(plm_scr2_reg_lfsr_one_12_iv_i_a2_0_0_6_), + .I2(plm_scr2_reg_lfsr_two_12_iv_i_o4_0[15]), + .I3(plm_scr2_reg_lfsr_two[6]), + .LO(plm_scr2_N_85438_i) + ); + defparam plm_scr2_lfsrs_N_85437_i.INIT = 16'hDFDD; + LUT4_L plm_scr2_lfsrs_N_85437_i ( + .I0(plm_scr2_N_20984_i), + .I1(plm_scr2_reg_lfsr_one_12_iv_i_a2_0_5_), + .I2(plm_scr2_reg_lfsr_two_12_iv_i_o4_0[15]), + .I3(plm_scr2_reg_lfsr_two[5]), + .LO(plm_scr2_N_85437_i) + ); + defparam plm_scr2_lfsrs_N_87826_i.INIT = 16'hF7B3; + LUT4_L plm_scr2_lfsrs_N_87826_i ( + .I0(plm_scr2_N_20985_i), + .I1(plm_scr2_N_25901_i), + .I2(plm_scr2_one_adv2_4__1160), + .I3(plm_scr2_reg_lfsr_two_4__671), + .LO(plm_scr2_N_87826_i) + ); + defparam plm_scr2_lfsrs_N_85436_i.INIT = 16'hFDDD; + LUT4_L plm_scr2_lfsrs_N_85436_i ( + .I0(plm_scr2_N_20984_i), + .I1(plm_scr2_reg_lfsr_one_12_iv_i_a2_0_3_), + .I2(plm_scr2_reg_lfsr_one29_0_a4_0_a2), + .I3(plm_scr2_one_adv2_3__1161), + .LO(plm_scr2_N_85436_i) + ); + defparam plm_scr2_lfsrs_N_87825_i.INIT = 16'hF7B3; + LUT4_L plm_scr2_lfsrs_N_87825_i ( + .I0(plm_scr2_N_20985_i), + .I1(plm_scr2_N_25901_i), + .I2(plm_scr2_one_adv2_2__1162), + .I3(plm_scr2_reg_lfsr_two_2__674), + .LO(plm_scr2_N_87825_i) + ); + defparam plm_scr2_lfsrs_N_87824_i.INIT = 16'hF7B3; + LUT4_L plm_scr2_lfsrs_N_87824_i ( + .I0(plm_scr2_N_20985_i), + .I1(plm_scr2_N_25901_i), + .I2(plm_scr2_one_adv2_1__1163), + .I3(plm_scr2_reg_lfsr_two_1__668), + .LO(plm_scr2_N_87824_i) + ); + defparam plm_scr2_lfsrs_reg_lfsr_one_12_0_iv_0_.INIT = 16'hF7B3; + LUT4_L plm_scr2_lfsrs_reg_lfsr_one_12_0_iv_0_ ( + .I0(plm_scr2_N_20985_i), + .I1(plm_scr2_N_25901_i), + .I2(plm_scr2_one_adv2_0__1164), + .I3(plm_scr2_reg_lfsr_two_0__482), + .LO(plm_scr2_reg_lfsr_one_12[0]) + ); + defparam plm_scr2_lfsrs_N_85455_i.INIT = 16'hFDDD; + LUT4_L plm_scr2_lfsrs_N_85455_i ( + .I0(plm_scr2_N_20984_i), + .I1(plm_scr2_reg_lfsr_two_12_iv_i_a2_0[15]), + .I2(plm_scr2_reg_lfsr_one29_0_a4_0_a2), + .I3(plm_scr2_two_adv2_15__1145), + .LO(plm_scr2_N_85455_i) + ); + defparam plm_scr2_lfsrs_N_85454_i.INIT = 16'h4F8F; + LUT4_L plm_scr2_lfsrs_N_85454_i ( + .I0(N_20991_i_0), + .I1(plm_scr2_reg_lfsr_one29_0_a4_0_a2), + .I2(plm_scr2_reg_lfsr_two_12_iv_i_0[14]), + .I3(plm_scr2_two_adv2_1_14__1146), + .LO(plm_scr2_N_85454_i) + ); + defparam plm_scr2_lfsrs_N_85453_i.INIT = 16'hDFDD; + LUT4_L plm_scr2_lfsrs_N_85453_i ( + .I0(plm_scr2_N_20984_i), + .I1(plm_scr2_reg_lfsr_two_12_iv_i_a2_0_0_13_), + .I2(plm_scr2_reg_lfsr_two_12_iv_i_o4_0[15]), + .I3(plm_scr2_one_adv2_13__1147), + .LO(plm_scr2_N_85453_i) + ); + defparam plm_scr2_lfsrs_reg_lfsr_two_12_0_iv_0_12_.INIT = 16'hC840; + LUT4_L plm_scr2_lfsrs_reg_lfsr_two_12_0_iv_0_12_ ( + .I0(plm_scr2_N_20985_i), + .I1(plm_scr2_N_25901_i), + .I2(plm_scr2_one_adv2_12__1149), + .I3(plm_scr2_two_adv2_12__1148), + .LO(plm_scr2_N_9703_i) + ); + defparam plm_scr2_lfsrs_N_85452_i.INIT = 16'hDFDD; + LUT4_L plm_scr2_lfsrs_N_85452_i ( + .I0(plm_scr2_N_20984_i), + .I1(plm_scr2_reg_lfsr_two_12_iv_i_a2_0_0_11_), + .I2(plm_scr2_reg_lfsr_two_12_iv_i_o4_0[15]), + .I3(plm_scr2_one_adv2_11__1150), + .LO(plm_scr2_N_85452_i) + ); + defparam plm_scr2_lfsrs_reg_lfsr_two_12_0_iv_0_10_.INIT = 16'hC840; + LUT4_L plm_scr2_lfsrs_reg_lfsr_two_12_0_iv_0_10_ ( + .I0(plm_scr2_N_20985_i), + .I1(plm_scr2_N_25901_i), + .I2(plm_scr2_one_adv2_10__1152), + .I3(plm_scr2_two_adv2_10__1151), + .LO(plm_scr2_N_9705_i) + ); + defparam plm_scr2_lfsrs_reg_lfsr_two_12_iv_0_9_.INIT = 16'h2220; + LUT4_L plm_scr2_lfsrs_reg_lfsr_two_12_iv_0_9_ ( + .I0(plm_scr2_N_20984_i), + .I1(plm_scr2_reg_lfsr_two_12_iv_0_a2_0_0_9_), + .I2(plm_scr2_reg_lfsr_two_12_iv_i_o4_0[15]), + .I3(plm_scr2_one_adv2_9__1153), + .LO(plm_scr2_N_9706_i) + ); + defparam plm_scr2_lfsrs_reg_lfsr_two_12_iv_0_8_.INIT = 16'h2202; + LUT4_L plm_scr2_lfsrs_reg_lfsr_two_12_iv_0_8_ ( + .I0(plm_scr2_N_20984_i), + .I1(plm_scr2_reg_lfsr_two_12_iv_0_a2_0[8]), + .I2(plm_scr2_reg_lfsr_one29_0_a4_0_a2), + .I3(plm_scr2_two_adv2_8__1154), + .LO(plm_scr2_N_9707_i) + ); + defparam plm_scr2_lfsrs_reg_lfsr_two_12_0_iv_0_7_.INIT = 16'hC840; + LUT4_L plm_scr2_lfsrs_reg_lfsr_two_12_0_iv_0_7_ ( + .I0(plm_scr2_N_20985_i), + .I1(plm_scr2_N_25901_i), + .I2(plm_scr2_one_adv2_7__1156), + .I3(plm_scr2_two_adv2_7__1155), + .LO(plm_scr2_N_9708_i) + ); + defparam plm_scr2_lfsrs_reg_lfsr_two_12_0_iv_0_6_.INIT = 16'hC840; + LUT4_L plm_scr2_lfsrs_reg_lfsr_two_12_0_iv_0_6_ ( + .I0(plm_scr2_N_20985_i), + .I1(plm_scr2_N_25901_i), + .I2(plm_scr2_one_adv2_6__1158), + .I3(plm_scr2_two_adv2_6__1157), + .LO(plm_scr2_N_9709_i) + ); + defparam plm_scr2_lfsrs_reg_lfsr_two_12_iv_0_5_.INIT = 16'h2202; + LUT4_L plm_scr2_lfsrs_reg_lfsr_two_12_iv_0_5_ ( + .I0(plm_scr2_N_20984_i), + .I1(plm_scr2_reg_lfsr_two_12_iv_0_a2[5]), + .I2(plm_scr2_reg_lfsr_one29_0_a4_0_a2), + .I3(plm_scr2_two_adv2_5__1159), + .LO(plm_scr2_N_9710_i) + ); + defparam plm_scr2_lfsrs_N_85448_i.INIT = 16'hDFDD; + LUT4_L plm_scr2_lfsrs_N_85448_i ( + .I0(plm_scr2_N_20984_i), + .I1(plm_scr2_reg_lfsr_two_12_iv_i_a2_0_0_4_), + .I2(plm_scr2_reg_lfsr_two_12_iv_i_o4_0[15]), + .I3(plm_scr2_one_adv2_4__1160), + .LO(plm_scr2_N_85448_i) + ); + defparam plm_scr2_lfsrs_reg_lfsr_two_12_iv_0_3_.INIT = 16'h2220; + LUT4_L plm_scr2_lfsrs_reg_lfsr_two_12_iv_0_3_ ( + .I0(plm_scr2_N_20984_i), + .I1(plm_scr2_reg_lfsr_two_12_iv_0_a2_0_0_3_), + .I2(plm_scr2_reg_lfsr_two_12_iv_i_o4_0[15]), + .I3(plm_scr2_one_adv2_3__1161), + .LO(plm_scr2_N_9712_i) + ); + defparam plm_scr2_lfsrs_N_85446_i.INIT = 16'hDFDD; + LUT4_L plm_scr2_lfsrs_N_85446_i ( + .I0(plm_scr2_N_20984_i), + .I1(plm_scr2_reg_lfsr_two_12_iv_i_a2_0_0_2_), + .I2(plm_scr2_reg_lfsr_two_12_iv_i_o4_0[15]), + .I3(plm_scr2_one_adv2_2__1162), + .LO(plm_scr2_N_85446_i) + ); + defparam plm_scr2_lfsrs_N_85445_i.INIT = 16'hDFDD; + LUT4_L plm_scr2_lfsrs_N_85445_i ( + .I0(plm_scr2_N_20984_i), + .I1(plm_scr2_reg_lfsr_two_12_iv_i_a2_0_0_1_), + .I2(plm_scr2_reg_lfsr_two_12_iv_i_o4_0[15]), + .I3(plm_scr2_one_adv2_1__1163), + .LO(plm_scr2_N_85445_i) + ); + defparam plm_scr2_lfsrs_N_85444_i.INIT = 16'hDFDD; + LUT4_L plm_scr2_lfsrs_N_85444_i ( + .I0(plm_scr2_N_20984_i), + .I1(plm_scr2_reg_lfsr_two_12_iv_i_a2_0_0_0_), + .I2(plm_scr2_reg_lfsr_two_12_iv_i_o4_0[15]), + .I3(plm_scr2_one_adv2_0__1164), + .LO(plm_scr2_N_85444_i) + ); + defparam plm_scr2_lfsrs_reg_lfsr_one29_0_a4_0_a2.INIT = 8'h01; + LUT3 plm_scr2_lfsrs_reg_lfsr_one29_0_a4_0_a2 ( + .I0(plm_scr2_reg_com[1]), + .I1(plm_scr2_reg_skp[1]), + .I2(plm_scr2_reg_skp[0]), + .O(plm_scr2_reg_lfsr_one29_0_a4_0_a2) + ); + FDC plm_scr2_reg_tx_data_8_ ( + .C(mgt_clk), + .D(plm_scr2_N_13503_i_0_i), + .Q(plm_tx2_data[8]), + .CLR(plm_rst) + ); + FDC plm_scr2_reg_tx_data_7_ ( + .C(mgt_clk), + .D(plm_scr2_reg_tx_data_12_7_), + .Q(plm_tx2_data[7]), + .CLR(plm_rst) + ); + FDC plm_scr2_reg_tx_data_6_ ( + .C(mgt_clk), + .D(plm_scr2_N_13525_i), + .Q(plm_tx2_data[6]), + .CLR(plm_rst) + ); + FDC plm_scr2_reg_tx_data_5_ ( + .C(mgt_clk), + .D(plm_scr2_N_13524_i), + .Q(plm_tx2_data[5]), + .CLR(plm_rst) + ); + FDC plm_scr2_reg_tx_data_4_ ( + .C(mgt_clk), + .D(plm_scr2_N_13523_i), + .Q(plm_tx2_data[4]), + .CLR(plm_rst) + ); + FDC plm_scr2_reg_tx_data_3_ ( + .C(mgt_clk), + .D(plm_scr2_N_13522_i), + .Q(plm_tx2_data[3]), + .CLR(plm_rst) + ); + FDC plm_scr2_reg_tx_data_2_ ( + .C(mgt_clk), + .D(plm_scr2_N_13521_i), + .Q(plm_tx2_data[2]), + .CLR(plm_rst) + ); + FDC plm_scr2_reg_tx_data_1_ ( + .C(mgt_clk), + .D(plm_scr2_N_13520_i), + .Q(plm_tx2_data[1]), + .CLR(plm_rst) + ); + FDC plm_scr2_reg_tx_data_0_ ( + .C(mgt_clk), + .D(plm_scr2_reg_tx_data_12_0_), + .Q(plm_tx2_data[0]), + .CLR(plm_rst) + ); + FDC plm_scr2_reg_skp_1_ ( + .C(mgt_clk), + .D(plm_scr2_reg_skp_3[1]), + .Q(plm_scr2_reg_skp[1]), + .CLR(plm_rst) + ); + FDC plm_scr2_reg_skp_0_ ( + .C(mgt_clk), + .D(plm_scr2_reg_skp_4[0]), + .Q(plm_scr2_reg_skp[0]), + .CLR(plm_rst) + ); + FDC plm_scr2_reg_com_1_ ( + .C(mgt_clk), + .D(plm_scr2_reg_com_3[1]), + .Q(plm_scr2_reg_com[1]), + .CLR(plm_rst) + ); + FDC plm_scr2_reg_com_0_ ( + .C(mgt_clk), + .D(plm_scr2_reg_com_4[0]), + .Q(plm_scr2_reg_com[0]), + .CLR(plm_rst) + ); + FDC plm_scr2_reg_dis_1_ ( + .C(mgt_clk), + .D(plm_N_14392_i), + .Q(plm_reg_dis_6103[1]), + .CLR(plm_rst) + ); + FDC plm_scr2_reg_dis_0_ ( + .C(mgt_clk), + .D(plm_N_14376_i), + .Q(plm_reg_dis_6103[0]), + .CLR(plm_rst) + ); + FDC plm_scr2_reg_tx_data_15_ ( + .C(mgt_clk), + .D(plm_scr2_reg_tx_data_6[15]), + .Q(plm_tx2_data[15]), + .CLR(plm_rst) + ); + FDC plm_scr2_reg_tx_data_14_ ( + .C(mgt_clk), + .D(plm_scr2_N_13515_i_0_i), + .Q(plm_tx2_data[14]), + .CLR(plm_rst) + ); + FDC plm_scr2_reg_tx_data_13_ ( + .C(mgt_clk), + .D(plm_scr2_N_13513_i_0_i), + .Q(plm_tx2_data[13]), + .CLR(plm_rst) + ); + FDC plm_scr2_reg_tx_data_12_ ( + .C(mgt_clk), + .D(plm_scr2_N_13511_i_0_i), + .Q(plm_tx2_data[12]), + .CLR(plm_rst) + ); + FDC plm_scr2_reg_tx_data_11_ ( + .C(mgt_clk), + .D(plm_scr2_N_13509_i_0_i), + .Q(plm_tx2_data[11]), + .CLR(plm_rst) + ); + FDC plm_scr2_reg_tx_data_10_ ( + .C(mgt_clk), + .D(plm_scr2_N_13507_i_0_i), + .Q(plm_tx2_data[10]), + .CLR(plm_rst) + ); + FDC plm_scr2_reg_tx_data_9_ ( + .C(mgt_clk), + .D(plm_scr2_N_13505_i_0_i), + .Q(plm_tx2_data[9]), + .CLR(plm_rst) + ); + FDC plm_scr2_reg_raw_char_0_ ( + .C(mgt_clk), + .D(plm_tx2_raw_char[0]), + .Q(plm_scr2_reg_raw_char[0]), + .CLR(plm_rst) + ); + FDC plm_scr2_reg_raw_char_15_ ( + .C(mgt_clk), + .D(plm_tx2_raw_char[15]), + .Q(plm_scr2_reg_raw_char[15]), + .CLR(plm_rst) + ); + FDC plm_scr2_reg_raw_char_14_ ( + .C(mgt_clk), + .D(plm_tx2_raw_char[14]), + .Q(plm_scr2_reg_raw_char[14]), + .CLR(plm_rst) + ); + FDC plm_scr2_reg_raw_char_13_ ( + .C(mgt_clk), + .D(plm_tx2_raw_char[13]), + .Q(plm_scr2_reg_raw_char[13]), + .CLR(plm_rst) + ); + FDC plm_scr2_reg_raw_char_12_ ( + .C(mgt_clk), + .D(plm_tx2_raw_char[12]), + .Q(plm_scr2_reg_raw_char[12]), + .CLR(plm_rst) + ); + FDC plm_scr2_reg_raw_char_11_ ( + .C(mgt_clk), + .D(plm_tx2_raw_char[11]), + .Q(plm_scr2_reg_raw_char[11]), + .CLR(plm_rst) + ); + FDC plm_scr2_reg_raw_char_10_ ( + .C(mgt_clk), + .D(plm_tx2_raw_char[10]), + .Q(plm_scr2_reg_raw_char[10]), + .CLR(plm_rst) + ); + FDC plm_scr2_reg_raw_char_9_ ( + .C(mgt_clk), + .D(plm_tx2_raw_char[9]), + .Q(plm_scr2_reg_raw_char[9]), + .CLR(plm_rst) + ); + FDC plm_scr2_reg_raw_char_8_ ( + .C(mgt_clk), + .D(plm_tx2_raw_char[8]), + .Q(plm_scr2_reg_raw_char[8]), + .CLR(plm_rst) + ); + FDC plm_scr2_reg_raw_char_7_ ( + .C(mgt_clk), + .D(plm_tx2_raw_char[7]), + .Q(plm_scr2_reg_raw_char[7]), + .CLR(plm_rst) + ); + FDC plm_scr2_reg_raw_char_6_ ( + .C(mgt_clk), + .D(plm_tx2_raw_char[6]), + .Q(plm_scr2_reg_raw_char[6]), + .CLR(plm_rst) + ); + FDC plm_scr2_reg_raw_char_5_ ( + .C(mgt_clk), + .D(plm_tx2_raw_char[5]), + .Q(plm_scr2_reg_raw_char[5]), + .CLR(plm_rst) + ); + FDC plm_scr2_reg_raw_char_4_ ( + .C(mgt_clk), + .D(plm_tx2_raw_char[4]), + .Q(plm_scr2_reg_raw_char[4]), + .CLR(plm_rst) + ); + FDC plm_scr2_reg_raw_char_3_ ( + .C(mgt_clk), + .D(plm_tx2_raw_char[3]), + .Q(plm_scr2_reg_raw_char[3]), + .CLR(plm_rst) + ); + FDC plm_scr2_reg_raw_char_2_ ( + .C(mgt_clk), + .D(plm_tx2_raw_char[2]), + .Q(plm_scr2_reg_raw_char[2]), + .CLR(plm_rst) + ); + FDC plm_scr2_reg_raw_char_1_ ( + .C(mgt_clk), + .D(plm_tx2_raw_char[1]), + .Q(plm_scr2_reg_raw_char[1]), + .CLR(plm_rst) + ); + FDC plm_scr2_reg_dat_12_ ( + .C(mgt_clk), + .D(plm_scr2_reg_raw_char[12]), + .Q(plm_scr2_reg_dat[12]), + .CLR(plm_rst) + ); + FDC plm_scr2_reg_dat_11_ ( + .C(mgt_clk), + .D(plm_scr2_reg_raw_char[11]), + .Q(plm_scr2_reg_dat[11]), + .CLR(plm_rst) + ); + FDC plm_scr2_reg_dat_10_ ( + .C(mgt_clk), + .D(plm_scr2_reg_raw_char[10]), + .Q(plm_scr2_reg_dat[10]), + .CLR(plm_rst) + ); + FDC plm_scr2_reg_dat_9_ ( + .C(mgt_clk), + .D(plm_scr2_reg_raw_char[9]), + .Q(plm_scr2_reg_dat[9]), + .CLR(plm_rst) + ); + FDC plm_scr2_reg_dat_8_ ( + .C(mgt_clk), + .D(plm_scr2_reg_raw_char[8]), + .Q(plm_scr2_reg_dat[8]), + .CLR(plm_rst) + ); + FDC plm_scr2_reg_dat_7_ ( + .C(mgt_clk), + .D(plm_scr2_reg_raw_char[7]), + .Q(plm_scr2_reg_dat[7]), + .CLR(plm_rst) + ); + FDC plm_scr2_reg_dat_6_ ( + .C(mgt_clk), + .D(plm_scr2_reg_raw_char[6]), + .Q(plm_scr2_reg_dat[6]), + .CLR(plm_rst) + ); + FDC plm_scr2_reg_dat_5_ ( + .C(mgt_clk), + .D(plm_scr2_reg_raw_char[5]), + .Q(plm_scr2_reg_dat[5]), + .CLR(plm_rst) + ); + FDC plm_scr2_reg_dat_4_ ( + .C(mgt_clk), + .D(plm_scr2_reg_raw_char[4]), + .Q(plm_scr2_reg_dat[4]), + .CLR(plm_rst) + ); + FDC plm_scr2_reg_dat_3_ ( + .C(mgt_clk), + .D(plm_scr2_reg_raw_char[3]), + .Q(plm_scr2_reg_dat[3]), + .CLR(plm_rst) + ); + FDC plm_scr2_reg_dat_2_ ( + .C(mgt_clk), + .D(plm_scr2_reg_raw_char[2]), + .Q(plm_scr2_reg_dat[2]), + .CLR(plm_rst) + ); + FDC plm_scr2_reg_dat_1_ ( + .C(mgt_clk), + .D(plm_scr2_reg_raw_char[1]), + .Q(plm_scr2_reg_dat[1]), + .CLR(plm_rst) + ); + FDC plm_scr2_reg_dat_0_ ( + .C(mgt_clk), + .D(plm_scr2_reg_raw_char[0]), + .Q(plm_scr2_reg_dat[0]), + .CLR(plm_rst) + ); + FDC plm_scr2_reg_kkk_1_ ( + .C(mgt_clk), + .D(plm_reg_raw_char_is_k[1]), + .Q(plm_reg_kkk[1]), + .CLR(plm_rst) + ); + FDC plm_scr2_reg_kkk_0_ ( + .C(mgt_clk), + .D(plm_reg_raw_char_is_k[0]), + .Q(plm_reg_kkk[0]), + .CLR(plm_rst) + ); + FDC plm_scr2_reg_dat_15_ ( + .C(mgt_clk), + .D(plm_scr2_reg_raw_char[15]), + .Q(plm_scr2_reg_dat[15]), + .CLR(plm_rst) + ); + FDC plm_scr2_reg_dat_14_ ( + .C(mgt_clk), + .D(plm_scr2_reg_raw_char[14]), + .Q(plm_scr2_reg_dat[14]), + .CLR(plm_rst) + ); + FDC plm_scr2_reg_dat_13_ ( + .C(mgt_clk), + .D(plm_scr2_reg_raw_char[13]), + .Q(plm_scr2_reg_dat[13]), + .CLR(plm_rst) + ); + FDPE plm_scr2_reg_lfsr_one_15_ ( + .PRE(plm_rst), + .CE(plm_scr2_reg_lfsr_one32_i), + .C(mgt_clk), + .D(plm_scr2_N_87798_i), + .Q(plm_scr2_reg_lfsr_one_15__556) + ); + FDPE plm_scr2_reg_lfsr_one_14_ ( + .PRE(plm_rst), + .CE(plm_scr2_reg_lfsr_one32_i), + .C(mgt_clk), + .D(plm_scr2_N_87828_i), + .Q(plm_scr2_reg_lfsr_one_14__675) + ); + FDPE plm_scr2_reg_lfsr_one_13_ ( + .PRE(plm_rst), + .CE(plm_scr2_reg_lfsr_one32_i), + .C(mgt_clk), + .D(plm_scr2_N_13589_i), + .Q(plm_scr2_reg_lfsr_one_13__559) + ); + FDPE plm_scr2_reg_lfsr_one_12_ ( + .PRE(plm_rst), + .CE(plm_scr2_reg_lfsr_one32_i), + .C(mgt_clk), + .D(plm_scr2_N_85443_i), + .Q(plm_scr2_reg_lfsr_one_12__1165) + ); + FDPE plm_scr2_reg_lfsr_one_11_ ( + .PRE(plm_rst), + .CE(plm_scr2_reg_lfsr_one32_i), + .C(mgt_clk), + .D(plm_scr2_N_87827_i), + .Q(plm_scr2_reg_lfsr_one_11__646) + ); + FDPE plm_scr2_reg_lfsr_one_10_ ( + .PRE(plm_rst), + .CE(plm_scr2_reg_lfsr_one32_i), + .C(mgt_clk), + .D(plm_scr2_N_85442_i), + .Q(plm_scr2_reg_lfsr_one_10__1166) + ); + FDPE plm_scr2_reg_lfsr_one_9_ ( + .PRE(plm_rst), + .CE(plm_scr2_reg_lfsr_one32_i), + .C(mgt_clk), + .D(plm_scr2_N_85441_i), + .Q(plm_scr2_reg_lfsr_one_9__1167) + ); + FDPE plm_scr2_reg_lfsr_one_8_ ( + .PRE(plm_rst), + .CE(plm_scr2_reg_lfsr_one32_i), + .C(mgt_clk), + .D(plm_scr2_N_85440_i), + .Q(plm_scr2_reg_lfsr_one_8__1168) + ); + FDPE plm_scr2_reg_lfsr_one_7_ ( + .PRE(plm_rst), + .CE(plm_scr2_reg_lfsr_one32_i), + .C(mgt_clk), + .D(plm_scr2_N_85439_i), + .Q(plm_scr2_reg_lfsr_one_7__1169) + ); + FDPE plm_scr2_reg_lfsr_one_6_ ( + .PRE(plm_rst), + .CE(plm_scr2_reg_lfsr_one32_i), + .C(mgt_clk), + .D(plm_scr2_N_85438_i), + .Q(plm_scr2_reg_lfsr_one_6__1170) + ); + FDPE plm_scr2_reg_lfsr_one_5_ ( + .PRE(plm_rst), + .CE(plm_scr2_reg_lfsr_one32_i), + .C(mgt_clk), + .D(plm_scr2_N_85437_i), + .Q(plm_scr2_reg_lfsr_one_5__1171) + ); + FDPE plm_scr2_reg_lfsr_one_4_ ( + .PRE(plm_rst), + .CE(plm_scr2_reg_lfsr_one32_i), + .C(mgt_clk), + .D(plm_scr2_N_87826_i), + .Q(plm_scr2_reg_lfsr_one_4__1172) + ); + FDPE plm_scr2_reg_lfsr_one_3_ ( + .PRE(plm_rst), + .CE(plm_scr2_reg_lfsr_one32_i), + .C(mgt_clk), + .D(plm_scr2_N_85436_i), + .Q(plm_scr2_reg_lfsr_one_3__558) + ); + FDPE plm_scr2_reg_lfsr_one_2_ ( + .PRE(plm_rst), + .CE(plm_scr2_reg_lfsr_one32_i), + .C(mgt_clk), + .D(plm_scr2_N_87825_i), + .Q(plm_scr2_reg_lfsr_one_2__1173) + ); + FDPE plm_scr2_reg_lfsr_one_1_ ( + .PRE(plm_rst), + .CE(plm_scr2_reg_lfsr_one32_i), + .C(mgt_clk), + .D(plm_scr2_N_87824_i), + .Q(plm_scr2_reg_lfsr_one_1__555) + ); + FDPE plm_scr2_reg_lfsr_one_0_ ( + .PRE(plm_rst), + .CE(plm_scr2_reg_lfsr_one32_i), + .C(mgt_clk), + .D(plm_scr2_reg_lfsr_one_12[0]), + .Q(plm_scr2_reg_lfsr_one_0__645) + ); + FDPE plm_scr2_reg_lfsr_two_15_ ( + .PRE(plm_rst), + .CE(plm_scr2_reg_lfsr_one32_i), + .C(mgt_clk), + .D(plm_scr2_N_85455_i), + .Q(plm_scr2_reg_lfsr_two_15__426) + ); + FDPE plm_scr2_reg_lfsr_two_14_ ( + .PRE(plm_rst), + .CE(plm_scr2_reg_lfsr_one32_i), + .C(mgt_clk), + .D(plm_scr2_N_85454_i), + .Q(plm_scr2_reg_lfsr_two_14__667) + ); + FDPE plm_scr2_reg_lfsr_two_13_ ( + .PRE(plm_rst), + .CE(plm_scr2_reg_lfsr_one32_i), + .C(mgt_clk), + .D(plm_scr2_N_85453_i), + .Q(plm_scr2_reg_lfsr_two_13__484) + ); + FDCE plm_scr2_reg_lfsr_two_12_ ( + .CE(plm_scr2_reg_lfsr_one32_i), + .C(mgt_clk), + .D(plm_scr2_N_9703_i), + .Q(plm_scr2_reg_lfsr_two_12__669), + .CLR(plm_rst) + ); + FDPE plm_scr2_reg_lfsr_two_11_ ( + .PRE(plm_rst), + .CE(plm_scr2_reg_lfsr_one32_i), + .C(mgt_clk), + .D(plm_scr2_N_85452_i), + .Q(plm_scr2_reg_lfsr_two_11__483) + ); + FDCE plm_scr2_reg_lfsr_two_10_ ( + .CE(plm_scr2_reg_lfsr_one32_i), + .C(mgt_clk), + .D(plm_scr2_N_9705_i), + .Q(plm_scr2_reg_lfsr_two[10]), + .CLR(plm_rst) + ); + FDCE plm_scr2_reg_lfsr_two_9_ ( + .CE(plm_scr2_reg_lfsr_one32_i), + .C(mgt_clk), + .D(plm_scr2_N_9706_i), + .Q(plm_scr2_reg_lfsr_two[9]), + .CLR(plm_rst) + ); + FDCE plm_scr2_reg_lfsr_two_8_ ( + .CE(plm_scr2_reg_lfsr_one32_i), + .C(mgt_clk), + .D(plm_scr2_N_9707_i), + .Q(plm_scr2_reg_lfsr_two[8]), + .CLR(plm_rst) + ); + FDCE plm_scr2_reg_lfsr_two_7_ ( + .CE(plm_scr2_reg_lfsr_one32_i), + .C(mgt_clk), + .D(plm_scr2_N_9708_i), + .Q(plm_scr2_reg_lfsr_two[7]), + .CLR(plm_rst) + ); + FDCE plm_scr2_reg_lfsr_two_6_ ( + .CE(plm_scr2_reg_lfsr_one32_i), + .C(mgt_clk), + .D(plm_scr2_N_9709_i), + .Q(plm_scr2_reg_lfsr_two[6]), + .CLR(plm_rst) + ); + FDCE plm_scr2_reg_lfsr_two_5_ ( + .CE(plm_scr2_reg_lfsr_one32_i), + .C(mgt_clk), + .D(plm_scr2_N_9710_i), + .Q(plm_scr2_reg_lfsr_two[5]), + .CLR(plm_rst) + ); + FDPE plm_scr2_reg_lfsr_two_4_ ( + .PRE(plm_rst), + .CE(plm_scr2_reg_lfsr_one32_i), + .C(mgt_clk), + .D(plm_scr2_N_85448_i), + .Q(plm_scr2_reg_lfsr_two_4__671) + ); + FDCE plm_scr2_reg_lfsr_two_3_ ( + .CE(plm_scr2_reg_lfsr_one32_i), + .C(mgt_clk), + .D(plm_scr2_N_9712_i), + .Q(plm_scr2_reg_lfsr_two_3__670), + .CLR(plm_rst) + ); + FDPE plm_scr2_reg_lfsr_two_2_ ( + .PRE(plm_rst), + .CE(plm_scr2_reg_lfsr_one32_i), + .C(mgt_clk), + .D(plm_scr2_N_85446_i), + .Q(plm_scr2_reg_lfsr_two_2__674) + ); + FDPE plm_scr2_reg_lfsr_two_1_ ( + .PRE(plm_rst), + .CE(plm_scr2_reg_lfsr_one32_i), + .C(mgt_clk), + .D(plm_scr2_N_85445_i), + .Q(plm_scr2_reg_lfsr_two_1__668) + ); + FDPE plm_scr2_reg_lfsr_two_0_ ( + .PRE(plm_rst), + .CE(plm_scr2_reg_lfsr_one32_i), + .C(mgt_clk), + .D(plm_scr2_N_85444_i), + .Q(plm_scr2_reg_lfsr_two_0__482) + ); + defparam plm_scr3_scram_reg_tx_data_12_sn_m2.INIT = 4'h1; + LUT2 plm_scr3_scram_reg_tx_data_12_sn_m2 ( + .I0(plm_scr3_reg_dis[0]), + .I1(plm_scr3_reg_skp[1]), + .O(plm_scr3_reg_tx_data_12_sn_m2_2) + ); + defparam plm_scr3_un1_reg_com_1_i_o4.INIT = 4'h1; + LUT2 plm_scr3_un1_reg_com_1_i_o4 ( + .I0(plm_scr3_reg_skp[0]), + .I1(plm_scr3_reg_skp[1]), + .O(plm_scr3_N_20848_i) + ); + defparam plm_scr3_un1_reg_com_1_i_o2.INIT = 4'h1; + LUT2 plm_scr3_un1_reg_com_1_i_o2 ( + .I0(plm_scr3_reg_com[0]), + .I1(plm_scr3_reg_com[1]), + .O(plm_scr3_N_20851_i) + ); + defparam plm_scr3_one_adv2_1_15_.INIT = 4'h6; + LUT2 plm_scr3_one_adv2_1_15_ ( + .I0(plm_scr3_reg_lfsr_one_10__1192), + .I1(plm_scr3_reg_lfsr_one_11__638), + .O(plm_scr3_one_adv2_1_15__1175) + ); + defparam plm_scr3_one_adv2_1_13_.INIT = 4'h6; + LUT2 plm_scr3_one_adv2_1_13_ ( + .I0(plm_scr3_reg_lfsr_one_8__1194), + .I1(plm_scr3_reg_lfsr_one_9__1193), + .O(plm_scr3_one_adv2_1_13__1176) + ); + defparam plm_scr3_one_adv2_1_11_.INIT = 4'h6; + LUT2 plm_scr3_one_adv2_1_11_ ( + .I0(plm_scr3_reg_lfsr_one_6__1196), + .I1(plm_scr3_reg_lfsr_one_7__1195), + .O(plm_scr3_one_adv2_1_11__1174) + ); + defparam plm_scr3_one_adv2_1_9_.INIT = 4'h6; + LUT2 plm_scr3_one_adv2_1_9_ ( + .I0(plm_scr3_reg_lfsr_one_4__1198), + .I1(plm_scr3_reg_lfsr_one_5__1197), + .O(plm_scr3_one_adv2_1_9__1182) + ); + defparam plm_scr3_one_adv2_1_6_.INIT = 4'h6; + LUT2 plm_scr3_one_adv2_1_6_ ( + .I0(plm_scr3_reg_lfsr_one_1__495), + .I1(plm_scr3_reg_lfsr_one_12__1191), + .O(plm_scr3_one_adv2_1_6__1181) + ); + defparam plm_scr3_two_adv2_1_14_.INIT = 4'h6; + LUT2 plm_scr3_two_adv2_1_14_ ( + .I0(plm_scr3_reg_lfsr_two_9__1203), + .I1(plm_scr3_reg_lfsr_two_10__1202), + .O(plm_scr3_two_adv2_1_14__1177) + ); + defparam plm_scr3_two_adv2_1_12_.INIT = 4'h6; + LUT2 plm_scr3_two_adv2_1_12_ ( + .I0(plm_scr3_reg_lfsr_two_7__1205), + .I1(plm_scr3_reg_lfsr_two_8__1204), + .O(plm_scr3_two_adv2_1_12__1178) + ); + defparam plm_scr3_two_adv2_1_7_.INIT = 4'h6; + LUT2 plm_scr3_two_adv2_1_7_ ( + .I0(plm_scr3_reg_lfsr_two_2__673), + .I1(plm_scr3_reg_lfsr_two_13__540), + .O(plm_scr3_two_adv2_1_7__1179) + ); + defparam plm_scr3_two_adv2_1_1_.INIT = 4'h6; + LUT2 plm_scr3_two_adv2_1_1_ ( + .I0(plm_scr3_reg_lfsr_two_12__1201), + .I1(plm_scr3_reg_lfsr_two_13__540), + .O(plm_scr3_two_adv2_1_1__1180) + ); + defparam plm_scr3_lfsrs_reg_lfsr_one32_i.INIT = 4'h7; + LUT2 plm_scr3_lfsrs_reg_lfsr_one32_i ( + .I0(plm_scr3_reg_skp[0]), + .I1(plm_scr3_reg_skp[1]), + .O(plm_scr3_reg_lfsr_one32_i) + ); + defparam plm_scr3_lfsrs_reg_lfsr_two_12_iv_i_o4_15_.INIT = 8'h23; + LUT3 plm_scr3_lfsrs_reg_lfsr_two_12_iv_i_o4_15_ ( + .I0(plm_scr3_reg_com[1]), + .I1(plm_scr3_reg_skp[0]), + .I2(plm_scr3_reg_skp[1]), + .O(plm_scr3_reg_lfsr_two_12_iv_i_o4[15]) + ); + defparam plm_scr3_lfsrs_reg_lfsr_two_12_iv_i_o2_15_.INIT = 8'h15; + LUT3 plm_scr3_lfsrs_reg_lfsr_two_12_iv_i_o2_15_ ( + .I0(plm_scr3_reg_com[0]), + .I1(plm_scr3_reg_com[1]), + .I2(plm_scr3_reg_skp[0]), + .O(plm_scr3_N_20849_i) + ); + defparam plm_scr3_two_adv2_1_6_.INIT = 8'h96; + LUT3 plm_scr3_two_adv2_1_6_ ( + .I0(plm_scr3_reg_lfsr_two_3__1209), + .I1(plm_scr3_reg_lfsr_two_12__1201), + .I2(plm_scr3_reg_lfsr_two_14__1200), + .O(plm_scr3_two_adv2_1_6__1185) + ); + defparam plm_scr3_two_adv2_15_.INIT = 16'h6996; + LUT4 plm_scr3_two_adv2_15_ ( + .I0(plm_scr3_reg_lfsr_two_10__1202), + .I1(plm_scr3_reg_lfsr_two_11__539), + .I2(plm_scr3_reg_lfsr_two_12__1201), + .I3(plm_scr3_reg_lfsr_two_15__541), + .O(plm_scr3_two_adv2_15__1186) + ); + defparam plm_scr3_two_adv2_10_.INIT = 16'h6996; + LUT4 plm_scr3_two_adv2_10_ ( + .I0(plm_scr3_reg_lfsr_two_5__1207), + .I1(plm_scr3_reg_lfsr_two_6__1206), + .I2(plm_scr3_reg_lfsr_two_7__1205), + .I3(plm_scr3_reg_lfsr_two_10__1202), + .O(plm_scr3_two_adv2_10__1188) + ); + defparam plm_scr3_one_adv2_12_.INIT = 8'h96; + LUT3 plm_scr3_one_adv2_12_ ( + .I0(plm_scr3_one_adv2_1_13__1176), + .I1(plm_scr3_reg_lfsr_one_7__1195), + .I2(plm_scr3_reg_lfsr_one_12__1191), + .O(plm_scr3_one_adv2[12]) + ); + defparam plm_scr3_one_adv2_11_.INIT = 8'h96; + LUT3 plm_scr3_one_adv2_11_ ( + .I0(plm_scr3_one_adv2_1_11__1174), + .I1(plm_scr3_reg_lfsr_one_8__1194), + .I2(plm_scr3_reg_lfsr_one_11__638), + .O(plm_scr3_one_adv2[11]) + ); + defparam plm_scr3_one_adv2_10_.INIT = 8'h96; + LUT3 plm_scr3_one_adv2_10_ ( + .I0(plm_scr3_one_adv2_1_11__1174), + .I1(plm_scr3_reg_lfsr_one_5__1197), + .I2(plm_scr3_reg_lfsr_one_10__1192), + .O(plm_scr3_one_adv2[10]) + ); + defparam plm_scr3_one_adv2_2_.INIT = 16'h6996; + LUT4 plm_scr3_one_adv2_2_ ( + .I0(plm_scr3_reg_lfsr_one_2__1199), + .I1(plm_scr3_reg_lfsr_one_13__499), + .I2(plm_scr3_reg_lfsr_one_14__692), + .I3(plm_scr3_reg_lfsr_one_15__496), + .O(plm_scr3_one_adv2[2]) + ); + defparam plm_scr3_one_adv2_1_.INIT = 8'h96; + LUT3 plm_scr3_one_adv2_1_ ( + .I0(plm_scr3_one_adv2_1_6__1181), + .I1(plm_scr3_reg_lfsr_one_13__499), + .I2(plm_scr3_reg_lfsr_one_14__692), + .O(plm_scr3_one_adv2[1]) + ); + defparam plm_scr3_two_adv2_12_.INIT = 8'h96; + LUT3 plm_scr3_two_adv2_12_ ( + .I0(plm_scr3_reg_lfsr_two_9__1203), + .I1(plm_scr3_reg_lfsr_two_12__1201), + .I2(plm_scr3_two_adv2_1_12__1178), + .O(plm_scr3_two_adv2_12__1187) + ); + defparam plm_scr3_one_adv2_15_.INIT = 8'h96; + LUT3 plm_scr3_one_adv2_15_ ( + .I0(plm_scr3_one_adv2_1_15__1175), + .I1(plm_scr3_reg_lfsr_one_12__1191), + .I2(plm_scr3_reg_lfsr_one_15__496), + .O(plm_scr3_one_adv2[15]) + ); + defparam plm_scr3_one_adv2_14_.INIT = 8'h96; + LUT3 plm_scr3_one_adv2_14_ ( + .I0(plm_scr3_one_adv2_1_15__1175), + .I1(plm_scr3_reg_lfsr_one_9__1193), + .I2(plm_scr3_reg_lfsr_one_14__692), + .O(plm_scr3_one_adv2[14]) + ); + defparam plm_scr3_one_adv2_13_.INIT = 8'h96; + LUT3 plm_scr3_one_adv2_13_ ( + .I0(plm_scr3_one_adv2_1_13__1176), + .I1(plm_scr3_reg_lfsr_one_10__1192), + .I2(plm_scr3_reg_lfsr_one_13__499), + .O(plm_scr3_one_adv2[13]) + ); + defparam plm_scr3_input_decoder_reg_com_4_0_a2_1_4_0_.INIT = 16'h0080; + LUT4_L plm_scr3_input_decoder_reg_com_4_0_a2_1_4_0_ ( + .I0(plm_scr3_reg_raw_char[2]), + .I1(plm_scr3_reg_raw_char[3]), + .I2(plm_scr3_reg_raw_char[4]), + .I3(plm_scr3_reg_raw_char[6]), + .LO(plm_scr3_reg_com_4_0_a2_1_4[0]) + ); + defparam plm_scr3_input_decoder_reg_com_3_0_a2_1_4_1_.INIT = 16'h0080; + LUT4_L plm_scr3_input_decoder_reg_com_3_0_a2_1_4_1_ ( + .I0(plm_scr3_reg_raw_char[10]), + .I1(plm_scr3_reg_raw_char[11]), + .I2(plm_scr3_reg_raw_char[12]), + .I3(plm_scr3_reg_raw_char[14]), + .LO(plm_scr3_reg_com_3_0_a2_1_4[1]) + ); + defparam plm_scr3_two_adv2_1_8_.INIT = 8'h96; + LUT3 plm_scr3_two_adv2_1_8_ ( + .I0(plm_scr3_reg_lfsr_two_4__1208), + .I1(plm_scr3_reg_lfsr_two_5__1207), + .I2(plm_scr3_reg_lfsr_two_8__1204), + .O(plm_scr3_two_adv2_1_8__1183) + ); + defparam plm_scr3_two_adv2_0_9_.INIT = 8'h96; + LUT3 plm_scr3_two_adv2_0_9_ ( + .I0(plm_scr3_reg_lfsr_two_5__1207), + .I1(plm_scr3_reg_lfsr_two_6__1206), + .I2(plm_scr3_reg_lfsr_two_9__1203), + .O(plm_scr3_two_adv2_0[9]) + ); + defparam plm_scr3_two_adv2_1_4_.INIT = 16'h6996; + LUT4 plm_scr3_two_adv2_1_4_ ( + .I0(plm_scr3_reg_lfsr_two_0__538), + .I1(plm_scr3_reg_lfsr_two_1__672), + .I2(plm_scr3_reg_lfsr_two_11__539), + .I3(plm_scr3_reg_lfsr_two_14__1200), + .O(plm_scr3_two_adv2_1_4__1184) + ); + defparam plm_scr3_two_adv2_1_0_7_.INIT = 8'h96; + LUT3_L plm_scr3_two_adv2_1_0_7_ ( + .I0(plm_scr3_reg_lfsr_two_3__1209), + .I1(plm_scr3_reg_lfsr_two_7__1205), + .I2(plm_scr3_two_adv2_1_7__1179), + .LO(plm_scr3_two_adv2_1_0[7]) + ); + defparam plm_scr3_one_adv2_0_.INIT = 8'h96; + LUT3 plm_scr3_one_adv2_0_ ( + .I0(N_12074_1), + .I1(plm_scr3_reg_lfsr_one_12__1191), + .I2(plm_scr3_reg_lfsr_one_13__499), + .O(plm_scr3_one_adv2[0]) + ); + defparam plm_scr3_lfsrs_reg_lfsr_two_12_iv_i_a2_15_.INIT = 4'h4; + LUT2_L plm_scr3_lfsrs_reg_lfsr_two_12_iv_i_a2_15_ ( + .I0(plm_scr3_reg_lfsr_two_12_iv_i_o4[15]), + .I1(plm_scr3_one_adv2[15]), + .LO(plm_scr3_reg_lfsr_two_12_iv_i_a2_1[15]) + ); + defparam plm_scr3_lfsrs_reg_lfsr_two_12_iv_i_a2_0_14_.INIT = 16'h8228; + LUT4 plm_scr3_lfsrs_reg_lfsr_two_12_iv_i_a2_0_14_ ( + .I0(plm_scr3_reg_lfsr_one29_0_a4_0), + .I1(plm_scr3_reg_lfsr_two_11__539), + .I2(plm_scr3_reg_lfsr_two_14__1200), + .I3(plm_scr3_two_adv2_1_14__1177), + .O(plm_scr3_reg_lfsr_two_12_iv_i_a2_0_0[14]) + ); + defparam plm_scr3_lfsrs_reg_lfsr_two_12_iv_i_a2_0_13_.INIT = 16'h8228; + LUT4 plm_scr3_lfsrs_reg_lfsr_two_12_iv_i_a2_0_13_ ( + .I0(plm_scr3_reg_lfsr_one29_0_a4_0), + .I1(plm_scr3_reg_lfsr_two_8__1204), + .I2(plm_scr3_reg_lfsr_two_13__540), + .I3(plm_scr3_two_adv2_1_14__1177), + .O(plm_scr3_reg_lfsr_two_12_iv_i_a2_0_1_13_) + ); + defparam plm_scr3_lfsrs_reg_lfsr_two_12_iv_i_a2_0_11_.INIT = 16'h8228; + LUT4 plm_scr3_lfsrs_reg_lfsr_two_12_iv_i_a2_0_11_ ( + .I0(plm_scr3_reg_lfsr_one29_0_a4_0), + .I1(plm_scr3_reg_lfsr_two_6__1206), + .I2(plm_scr3_reg_lfsr_two_11__539), + .I3(plm_scr3_two_adv2_1_12__1178), + .O(plm_scr3_reg_lfsr_two_12_iv_i_a2_0_1_11_) + ); + defparam plm_scr3_lfsrs_reg_lfsr_two_12_iv_i_a2_0_2_.INIT = 16'h8228; + LUT4_L plm_scr3_lfsrs_reg_lfsr_two_12_iv_i_a2_0_2_ ( + .I0(plm_scr3_reg_lfsr_one29_0_a4_0), + .I1(plm_scr3_reg_lfsr_two_14__1200), + .I2(plm_scr3_reg_lfsr_two_15__541), + .I3(plm_scr3_two_adv2_1_7__1179), + .LO(plm_scr3_reg_lfsr_two_12_iv_i_a2_0_1_2_) + ); + defparam plm_scr3_lfsrs_reg_lfsr_two_12_iv_i_a2_0_1_.INIT = 16'h8228; + LUT4 plm_scr3_lfsrs_reg_lfsr_two_12_iv_i_a2_0_1_ ( + .I0(plm_scr3_reg_lfsr_one29_0_a4_0), + .I1(plm_scr3_reg_lfsr_two_1__672), + .I2(plm_scr3_reg_lfsr_two_14__1200), + .I3(plm_scr3_two_adv2_1_1__1180), + .O(plm_scr3_reg_lfsr_two_12_iv_i_a2_0_1_1_) + ); + defparam plm_scr3_lfsrs_reg_lfsr_two_12_iv_i_a2_0_0_.INIT = 16'h8228; + LUT4 plm_scr3_lfsrs_reg_lfsr_two_12_iv_i_a2_0_0_ ( + .I0(plm_scr3_reg_lfsr_one29_0_a4_0), + .I1(plm_scr3_reg_lfsr_two_0__538), + .I2(plm_scr3_reg_lfsr_two_11__539), + .I3(plm_scr3_two_adv2_1_1__1180), + .O(plm_scr3_reg_lfsr_two_12_iv_i_a2_0_1_0_) + ); + defparam plm_scr3_lfsrs_reg_lfsr_one_12_iv_i_a2_12_.INIT = 4'h4; + LUT2 plm_scr3_lfsrs_reg_lfsr_one_12_iv_i_a2_12_ ( + .I0(plm_scr3_reg_lfsr_two_12_iv_i_o4[15]), + .I1(plm_scr3_reg_lfsr_two_12__1201), + .O(plm_scr3_reg_lfsr_one_12_iv_i_a2_1_12_) + ); + defparam plm_scr3_lfsrs_reg_lfsr_one_12_iv_i_a2_0_10_.INIT = 4'h8; + LUT2_L plm_scr3_lfsrs_reg_lfsr_one_12_iv_i_a2_0_10_ ( + .I0(plm_scr3_reg_lfsr_one29_0_a4_0), + .I1(plm_scr3_one_adv2[10]), + .LO(plm_scr3_reg_lfsr_one_12_iv_i_a2_0_1[10]) + ); + defparam plm_scr3_lfsrs_reg_lfsr_one_12_iv_i_a2_7_.INIT = 4'h4; + LUT2 plm_scr3_lfsrs_reg_lfsr_one_12_iv_i_a2_7_ ( + .I0(plm_scr3_reg_lfsr_two_12_iv_i_o4[15]), + .I1(plm_scr3_reg_lfsr_two_7__1205), + .O(plm_scr3_reg_lfsr_one_12_iv_i_a2_1_7_) + ); + defparam plm_scr3_lfsrs_reg_lfsr_one_12_iv_i_a2_6_.INIT = 4'h4; + LUT2 plm_scr3_lfsrs_reg_lfsr_one_12_iv_i_a2_6_ ( + .I0(plm_scr3_reg_lfsr_two_12_iv_i_o4[15]), + .I1(plm_scr3_reg_lfsr_two_6__1206), + .O(plm_scr3_reg_lfsr_one_12_iv_i_a2[6]) + ); + defparam plm_scr3_lfsrs_reg_lfsr_one_12_iv_i_a2_5_.INIT = 4'h4; + LUT2 plm_scr3_lfsrs_reg_lfsr_one_12_iv_i_a2_5_ ( + .I0(plm_scr3_reg_lfsr_two_12_iv_i_o4[15]), + .I1(plm_scr3_reg_lfsr_two_5__1207), + .O(plm_scr3_reg_lfsr_one_12_iv_i_a2_1_5_) + ); + defparam plm_scr3_lfsrs_reg_lfsr_one_12_iv_i_a2_3_.INIT = 4'h4; + LUT2 plm_scr3_lfsrs_reg_lfsr_one_12_iv_i_a2_3_ ( + .I0(plm_scr3_reg_lfsr_two_12_iv_i_o4[15]), + .I1(plm_scr3_reg_lfsr_two_3__1209), + .O(plm_scr3_reg_lfsr_one_12_iv_i_a2_1_3_) + ); + defparam plm_scr3_two_adv2_7_.INIT = 8'h96; + LUT3 plm_scr3_two_adv2_7_ ( + .I0(plm_scr3_reg_lfsr_two_4__1208), + .I1(plm_scr3_reg_lfsr_two_15__541), + .I2(plm_scr3_two_adv2_1_0[7]), + .O(plm_scr3_two_adv2_7__1189) + ); + defparam plm_scr3_one_adv2_6_.INIT = 16'h6996; + LUT4 plm_scr3_one_adv2_6_ ( + .I0(G_355_693), + .I1(plm_scr3_one_adv2_1_6__1181), + .I2(plm_scr3_reg_lfsr_one_2__1199), + .I3(plm_scr3_reg_lfsr_one_6__1196), + .O(plm_scr3_one_adv2[6]) + ); + defparam plm_scr3_one_adv2_7_.INIT = 16'h6996; + LUT4 plm_scr3_one_adv2_7_ ( + .I0(G_330_500), + .I1(plm_scr3_reg_lfsr_one_2__1199), + .I2(plm_scr3_reg_lfsr_one_4__1198), + .I3(plm_scr3_reg_lfsr_one_7__1195), + .O(plm_scr3_one_adv2[7]) + ); + defparam plm_scr3_one_adv2_9_.INIT = 16'h6996; + LUT4 plm_scr3_one_adv2_9_ ( + .I0(plm_scr3_one_adv2_1_9__1182), + .I1(plm_scr3_reg_lfsr_one_6__1196), + .I2(plm_scr3_reg_lfsr_one_9__1193), + .I3(plm_scr3_reg_lfsr_one_15__496), + .O(plm_scr3_one_adv2[9]) + ); + defparam plm_scr3_two_adv2_6_.INIT = 8'h96; + LUT3 plm_scr3_two_adv2_6_ ( + .I0(N_20852_i_0), + .I1(plm_scr3_reg_lfsr_two_6__1206), + .I2(plm_scr3_two_adv2_1_6__1185), + .O(plm_scr3_two_adv2_6__1190) + ); + defparam plm_scr3_one_adv2_8_.INIT = 8'h96; + LUT3 plm_scr3_one_adv2_8_ ( + .I0(G_355_693), + .I1(plm_scr3_one_adv2_1_9__1182), + .I2(plm_scr3_reg_lfsr_one_8__1194), + .O(plm_scr3_one_adv2[8]) + ); + defparam plm_scr3_one_adv2_5_.INIT = 16'h6996; + LUT4 plm_scr3_one_adv2_5_ ( + .I0(G_329_497), + .I1(plm_scr3_reg_lfsr_one_2__1199), + .I2(plm_scr3_reg_lfsr_one_5__1197), + .I3(plm_scr3_reg_lfsr_one_13__499), + .O(plm_scr3_one_adv2[5]) + ); + defparam plm_scr3_one_adv2_4_.INIT = 8'h96; + LUT3 plm_scr3_one_adv2_4_ ( + .I0(G_329_497), + .I1(plm_scr3_reg_lfsr_one_4__1198), + .I2(plm_scr3_reg_lfsr_one_14__692), + .O(plm_scr3_one_adv2[4]) + ); + defparam plm_scr3_input_decoder_reg_com_3_0_a2_1_1_.INIT = 16'h0200; + LUT4 plm_scr3_input_decoder_reg_com_3_0_a2_1_1_ ( + .I0(plm_scr3_reg_com_3_0_a2_1_4[1]), + .I1(plm_scr3_reg_raw_char[8]), + .I2(plm_scr3_reg_raw_char[9]), + .I3(plm_scr3_reg_raw_char_is_k[1]), + .O(plm_scr3_reg_com_3_1[1]) + ); + defparam plm_scr3_input_decoder_reg_com_4_0_a2_1_0_.INIT = 16'h0200; + LUT4 plm_scr3_input_decoder_reg_com_4_0_a2_1_0_ ( + .I0(plm_scr3_reg_com_4_0_a2_1_4[0]), + .I1(plm_scr3_reg_raw_char[0]), + .I2(plm_scr3_reg_raw_char[1]), + .I3(plm_scr3_reg_raw_char_is_k[0]), + .O(plm_scr3_reg_com_4_1[0]) + ); + defparam plm_scr3_lfsrs_reg_lfsr_two_12_iv_0_a2_0_9_.INIT = 16'h2882; + LUT4 plm_scr3_lfsrs_reg_lfsr_two_12_iv_0_a2_0_9_ ( + .I0(plm_scr3_reg_lfsr_one29_0_a4_0), + .I1(plm_scr3_reg_lfsr_two_4__1208), + .I2(plm_scr3_reg_lfsr_two_15__541), + .I3(plm_scr3_two_adv2_0[9]), + .O(plm_scr3_reg_lfsr_two_12_iv_0_a2_0_1_9_) + ); + defparam plm_scr3_lfsrs_reg_lfsr_two_12_iv_0_a2_0_8_.INIT = 16'h2882; + LUT4 plm_scr3_lfsrs_reg_lfsr_two_12_iv_0_a2_0_8_ ( + .I0(plm_scr3_reg_lfsr_one29_0_a4_0), + .I1(plm_scr3_reg_lfsr_two_3__1209), + .I2(plm_scr3_reg_lfsr_two_14__1200), + .I3(plm_scr3_two_adv2_1_8__1183), + .O(plm_scr3_reg_lfsr_two_12_iv_0_a2_0_0_8_) + ); + defparam plm_scr3_lfsrs_reg_lfsr_two_12_iv_0_a2_0_5_.INIT = 16'h6090; + LUT4 plm_scr3_lfsrs_reg_lfsr_two_12_iv_0_a2_0_5_ ( + .I0(G_345_542), + .I1(N_20852_i_0), + .I2(plm_scr3_reg_lfsr_one29_0_a4_0), + .I3(plm_scr3_reg_lfsr_two_5__1207), + .O(plm_scr3_reg_lfsr_two_12_iv_0_a2_0_0_5_) + ); + defparam plm_scr3_lfsrs_reg_lfsr_two_12_iv_i_a2_0_4_.INIT = 16'h8228; + LUT4 plm_scr3_lfsrs_reg_lfsr_two_12_iv_i_a2_0_4_ ( + .I0(plm_scr3_reg_lfsr_one29_0_a4_0), + .I1(plm_scr3_reg_lfsr_two_4__1208), + .I2(plm_scr3_reg_lfsr_two_15__541), + .I3(plm_scr3_two_adv2_1_4__1184), + .O(plm_scr3_reg_lfsr_two_12_iv_i_a2_0_1_4_) + ); + defparam plm_scr3_lfsrs_reg_lfsr_two_12_iv_0_a2_0_3_.INIT = 8'h84; + LUT3 plm_scr3_lfsrs_reg_lfsr_two_12_iv_0_a2_0_3_ ( + .I0(G_345_542), + .I1(plm_scr3_reg_lfsr_one29_0_a4_0), + .I2(plm_scr3_two_adv2_1_6__1185), + .O(plm_scr3_reg_lfsr_two_12_iv_0_a2_0_1_3_) + ); + defparam plm_scr3_lfsrs_reg_lfsr_one_12_iv_i_a2_0_9_.INIT = 4'h8; + LUT2_L plm_scr3_lfsrs_reg_lfsr_one_12_iv_i_a2_0_9_ ( + .I0(plm_scr3_reg_lfsr_one29_0_a4_0), + .I1(plm_scr3_one_adv2[9]), + .LO(plm_scr3_reg_lfsr_one_12_iv_i_a2_0_1[9]) + ); + defparam plm_scr3_lfsrs_reg_lfsr_one_12_iv_i_a2_0_8_.INIT = 4'h8; + LUT2_L plm_scr3_lfsrs_reg_lfsr_one_12_iv_i_a2_0_8_ ( + .I0(plm_scr3_reg_lfsr_one29_0_a4_0), + .I1(plm_scr3_one_adv2[8]), + .LO(plm_scr3_reg_lfsr_one_12_iv_i_a2_0_1[8]) + ); + defparam plm_scr3_scram_reg_tx_data_12_2_am_7_.INIT = 8'h9A; + LUT3 plm_scr3_scram_reg_tx_data_12_2_am_7_ ( + .I0(plm_scr3_reg_dat[7]), + .I1(plm_scr3_reg_dis[0]), + .I2(plm_scr3_reg_lfsr_one_8__1194), + .O(plm_scr3_reg_tx_data_12_2_am[7]) + ); + defparam plm_scr3_scram_reg_tx_data_12_2_bm_7_.INIT = 8'h36; + LUT3 plm_scr3_scram_reg_tx_data_12_2_bm_7_ ( + .I0(plm_scr3_reg_com[1]), + .I1(plm_scr3_reg_dat[7]), + .I2(plm_scr3_reg_lfsr_two_8__1204), + .O(plm_scr3_reg_tx_data_12_2_bm[7]) + ); + MUXF5 plm_scr3_scram_reg_tx_data_12_2_7_ ( + .I0(plm_scr3_reg_tx_data_12_2_am[7]), + .I1(plm_scr3_reg_tx_data_12_2_bm[7]), + .O(plm_scr3_reg_tx_data_12[7]), + .S(plm_scr3_reg_tx_data_12_sn_m2_2) + ); + defparam plm_scr3_scram_reg_tx_data_12_2_am_6_.INIT = 8'h9A; + LUT3 plm_scr3_scram_reg_tx_data_12_2_am_6_ ( + .I0(plm_scr3_reg_dat[6]), + .I1(plm_scr3_reg_dis[0]), + .I2(plm_scr3_reg_lfsr_one_9__1193), + .O(plm_scr3_reg_tx_data_12_2_am[6]) + ); + defparam plm_scr3_scram_reg_tx_data_12_2_bm_6_.INIT = 8'h36; + LUT3 plm_scr3_scram_reg_tx_data_12_2_bm_6_ ( + .I0(plm_scr3_reg_com[1]), + .I1(plm_scr3_reg_dat[6]), + .I2(plm_scr3_reg_lfsr_two_9__1203), + .O(plm_scr3_reg_tx_data_12_2_bm[6]) + ); + MUXF5 plm_scr3_scram_reg_tx_data_12_2_6_ ( + .I0(plm_scr3_reg_tx_data_12_2_am[6]), + .I1(plm_scr3_reg_tx_data_12_2_bm[6]), + .O(plm_scr3_reg_tx_data_12[6]), + .S(plm_scr3_reg_tx_data_12_sn_m2_2) + ); + defparam plm_scr3_scram_reg_tx_data_12_2_am_5_.INIT = 8'h9A; + LUT3 plm_scr3_scram_reg_tx_data_12_2_am_5_ ( + .I0(plm_scr3_reg_dat[5]), + .I1(plm_scr3_reg_dis[0]), + .I2(plm_scr3_reg_lfsr_one_10__1192), + .O(plm_scr3_reg_tx_data_12_2_am[5]) + ); + defparam plm_scr3_scram_reg_tx_data_12_2_bm_5_.INIT = 8'h36; + LUT3 plm_scr3_scram_reg_tx_data_12_2_bm_5_ ( + .I0(plm_scr3_reg_com[1]), + .I1(plm_scr3_reg_dat[5]), + .I2(plm_scr3_reg_lfsr_two_10__1202), + .O(plm_scr3_reg_tx_data_12_2_bm[5]) + ); + MUXF5 plm_scr3_scram_reg_tx_data_12_2_5_ ( + .I0(plm_scr3_reg_tx_data_12_2_am[5]), + .I1(plm_scr3_reg_tx_data_12_2_bm[5]), + .O(plm_scr3_reg_tx_data_12[5]), + .S(plm_scr3_reg_tx_data_12_sn_m2_2) + ); + defparam plm_scr3_scram_reg_tx_data_12_2_am_4_.INIT = 8'h9A; + LUT3 plm_scr3_scram_reg_tx_data_12_2_am_4_ ( + .I0(plm_scr3_reg_dat[4]), + .I1(plm_scr3_reg_dis[0]), + .I2(plm_scr3_reg_lfsr_one_11__638), + .O(plm_scr3_reg_tx_data_12_2_am[4]) + ); + defparam plm_scr3_scram_reg_tx_data_12_2_bm_4_.INIT = 8'h36; + LUT3 plm_scr3_scram_reg_tx_data_12_2_bm_4_ ( + .I0(plm_scr3_reg_com[1]), + .I1(plm_scr3_reg_dat[4]), + .I2(plm_scr3_reg_lfsr_two_11__539), + .O(plm_scr3_reg_tx_data_12_2_bm[4]) + ); + MUXF5 plm_scr3_scram_reg_tx_data_12_2_4_ ( + .I0(plm_scr3_reg_tx_data_12_2_am[4]), + .I1(plm_scr3_reg_tx_data_12_2_bm[4]), + .O(plm_scr3_reg_tx_data_12[4]), + .S(plm_scr3_reg_tx_data_12_sn_m2_2) + ); + defparam plm_scr3_scram_reg_tx_data_12_2_am_3_.INIT = 8'h9A; + LUT3 plm_scr3_scram_reg_tx_data_12_2_am_3_ ( + .I0(plm_scr3_reg_dat[3]), + .I1(plm_scr3_reg_dis[0]), + .I2(plm_scr3_reg_lfsr_one_12__1191), + .O(plm_scr3_reg_tx_data_12_2_am[3]) + ); + defparam plm_scr3_scram_reg_tx_data_12_2_bm_3_.INIT = 8'h36; + LUT3 plm_scr3_scram_reg_tx_data_12_2_bm_3_ ( + .I0(plm_scr3_reg_com[1]), + .I1(plm_scr3_reg_dat[3]), + .I2(plm_scr3_reg_lfsr_two_12__1201), + .O(plm_scr3_reg_tx_data_12_2_bm[3]) + ); + MUXF5 plm_scr3_scram_reg_tx_data_12_2_3_ ( + .I0(plm_scr3_reg_tx_data_12_2_am[3]), + .I1(plm_scr3_reg_tx_data_12_2_bm[3]), + .O(plm_scr3_reg_tx_data_12[3]), + .S(plm_scr3_reg_tx_data_12_sn_m2_2) + ); + defparam plm_scr3_scram_reg_tx_data_12_2_am_2_.INIT = 8'h9A; + LUT3 plm_scr3_scram_reg_tx_data_12_2_am_2_ ( + .I0(plm_scr3_reg_dat[2]), + .I1(plm_scr3_reg_dis[0]), + .I2(plm_scr3_reg_lfsr_one_13__499), + .O(plm_scr3_reg_tx_data_12_2_am[2]) + ); + defparam plm_scr3_scram_reg_tx_data_12_2_bm_2_.INIT = 8'h36; + LUT3 plm_scr3_scram_reg_tx_data_12_2_bm_2_ ( + .I0(plm_scr3_reg_com[1]), + .I1(plm_scr3_reg_dat[2]), + .I2(plm_scr3_reg_lfsr_two_13__540), + .O(plm_scr3_reg_tx_data_12_2_bm[2]) + ); + MUXF5 plm_scr3_scram_reg_tx_data_12_2_2_ ( + .I0(plm_scr3_reg_tx_data_12_2_am[2]), + .I1(plm_scr3_reg_tx_data_12_2_bm[2]), + .O(plm_scr3_reg_tx_data_12[2]), + .S(plm_scr3_reg_tx_data_12_sn_m2_2) + ); + defparam plm_scr3_scram_reg_tx_data_12_2_am_1_.INIT = 8'h9A; + LUT3 plm_scr3_scram_reg_tx_data_12_2_am_1_ ( + .I0(plm_scr3_reg_dat[1]), + .I1(plm_scr3_reg_dis[0]), + .I2(plm_scr3_reg_lfsr_one_14__692), + .O(plm_scr3_reg_tx_data_12_2_am[1]) + ); + defparam plm_scr3_scram_reg_tx_data_12_2_bm_1_.INIT = 8'h36; + LUT3 plm_scr3_scram_reg_tx_data_12_2_bm_1_ ( + .I0(plm_scr3_reg_com[1]), + .I1(plm_scr3_reg_dat[1]), + .I2(plm_scr3_reg_lfsr_two_14__1200), + .O(plm_scr3_reg_tx_data_12_2_bm[1]) + ); + MUXF5 plm_scr3_scram_reg_tx_data_12_2_1_ ( + .I0(plm_scr3_reg_tx_data_12_2_am[1]), + .I1(plm_scr3_reg_tx_data_12_2_bm[1]), + .O(plm_scr3_reg_tx_data_12[1]), + .S(plm_scr3_reg_tx_data_12_sn_m2_2) + ); + defparam plm_scr3_scram_reg_tx_data_12_2_am_0_.INIT = 8'h9A; + LUT3 plm_scr3_scram_reg_tx_data_12_2_am_0_ ( + .I0(plm_scr3_reg_dat[0]), + .I1(plm_scr3_reg_dis[0]), + .I2(plm_scr3_reg_lfsr_one_15__496), + .O(plm_scr3_reg_tx_data_12_2_am[0]) + ); + defparam plm_scr3_scram_reg_tx_data_12_2_bm_0_.INIT = 8'h36; + LUT3 plm_scr3_scram_reg_tx_data_12_2_bm_0_ ( + .I0(plm_scr3_reg_com[1]), + .I1(plm_scr3_reg_dat[0]), + .I2(plm_scr3_reg_lfsr_two_15__541), + .O(plm_scr3_reg_tx_data_12_2_bm[0]) + ); + MUXF5 plm_scr3_scram_reg_tx_data_12_2_0_ ( + .I0(plm_scr3_reg_tx_data_12_2_am[0]), + .I1(plm_scr3_reg_tx_data_12_2_bm[0]), + .O(plm_scr3_reg_tx_data_12[0]), + .S(plm_scr3_reg_tx_data_12_sn_m2_2) + ); + defparam plm_scr3_one_adv2_3_.INIT = 16'h6996; + LUT4 plm_scr3_one_adv2_3_ ( + .I0(G_330_500), + .I1(N_12074_1), + .I2(plm_scr3_reg_lfsr_one_12__1191), + .I3(plm_scr3_reg_lfsr_one_14__692), + .O(plm_scr3_one_adv2[3]) + ); + defparam plm_scr3_one_adv2_i_m_4_.INIT = 8'h02; + LUT3 plm_scr3_one_adv2_i_m_4_ ( + .I0(plm_scr3_reg_lfsr_one29_0_a4_0), + .I1(plm_scr3_one_adv2[4]), + .I2(plm_scr3_reg_com[0]), + .O(plm_scr3_one_adv2_i_m[4]) + ); + defparam plm_scr3_scram_reg_tx_data_6_0_15_.INIT = 8'h9A; + LUT3_L plm_scr3_scram_reg_tx_data_6_0_15_ ( + .I0(plm_scr3_reg_dat[15]), + .I1(plm_scr3_reg_dis[1]), + .I2(plm_scr3_reg_lfsr_one_8__1194), + .LO(plm_scr3_reg_tx_data_6[15]) + ); + defparam plm_scr3_scram_reg_tx_data_6_0_14_.INIT = 8'h9A; + LUT3_L plm_scr3_scram_reg_tx_data_6_0_14_ ( + .I0(plm_scr3_reg_dat[14]), + .I1(plm_scr3_reg_dis[1]), + .I2(plm_scr3_reg_lfsr_one_9__1193), + .LO(plm_scr3_reg_tx_data_6[14]) + ); + defparam plm_scr3_scram_reg_tx_data_6_0_13_.INIT = 8'h9A; + LUT3_L plm_scr3_scram_reg_tx_data_6_0_13_ ( + .I0(plm_scr3_reg_dat[13]), + .I1(plm_scr3_reg_dis[1]), + .I2(plm_scr3_reg_lfsr_one_10__1192), + .LO(plm_scr3_reg_tx_data_6[13]) + ); + defparam plm_scr3_scram_reg_tx_data_6_0_12_.INIT = 8'h9A; + LUT3_L plm_scr3_scram_reg_tx_data_6_0_12_ ( + .I0(plm_scr3_reg_dat[12]), + .I1(plm_scr3_reg_dis[1]), + .I2(plm_scr3_reg_lfsr_one_11__638), + .LO(plm_scr3_reg_tx_data_6[12]) + ); + defparam plm_scr3_scram_reg_tx_data_6_0_11_.INIT = 8'h9A; + LUT3_L plm_scr3_scram_reg_tx_data_6_0_11_ ( + .I0(plm_scr3_reg_dat[11]), + .I1(plm_scr3_reg_dis[1]), + .I2(plm_scr3_reg_lfsr_one_12__1191), + .LO(plm_scr3_reg_tx_data_6[11]) + ); + defparam plm_scr3_scram_reg_tx_data_6_0_10_.INIT = 8'h9A; + LUT3_L plm_scr3_scram_reg_tx_data_6_0_10_ ( + .I0(plm_scr3_reg_dat[10]), + .I1(plm_scr3_reg_dis[1]), + .I2(plm_scr3_reg_lfsr_one_13__499), + .LO(plm_scr3_reg_tx_data_6[10]) + ); + defparam plm_scr3_scram_reg_tx_data_6_0_9_.INIT = 8'h9A; + LUT3_L plm_scr3_scram_reg_tx_data_6_0_9_ ( + .I0(plm_scr3_reg_dat[9]), + .I1(plm_scr3_reg_dis[1]), + .I2(plm_scr3_reg_lfsr_one_14__692), + .LO(plm_scr3_reg_tx_data_6[9]) + ); + defparam plm_scr3_scram_reg_tx_data_6_0_8_.INIT = 8'h9A; + LUT3_L plm_scr3_scram_reg_tx_data_6_0_8_ ( + .I0(plm_scr3_reg_dat[8]), + .I1(plm_scr3_reg_dis[1]), + .I2(plm_scr3_reg_lfsr_one_15__496), + .LO(plm_scr3_reg_tx_data_6[8]) + ); + defparam plm_scr3_input_decoder_reg_skp_4_0_a2_0_.INIT = 8'h02; + LUT3_L plm_scr3_input_decoder_reg_skp_4_0_a2_0_ ( + .I0(plm_scr3_reg_com_4_1[0]), + .I1(plm_scr3_reg_raw_char[5]), + .I2(plm_scr3_reg_raw_char[7]), + .LO(plm_scr3_reg_skp_4[0]) + ); + defparam plm_scr3_input_decoder_reg_com_3_0_a2_1_.INIT = 8'h80; + LUT3_L plm_scr3_input_decoder_reg_com_3_0_a2_1_ ( + .I0(plm_scr3_reg_com_3_1[1]), + .I1(plm_scr3_reg_raw_char[13]), + .I2(plm_scr3_reg_raw_char[15]), + .LO(plm_scr3_reg_com_3[1]) + ); + defparam plm_scr3_input_decoder_reg_com_4_0_a2_0_.INIT = 8'h80; + LUT3_L plm_scr3_input_decoder_reg_com_4_0_a2_0_ ( + .I0(plm_scr3_reg_com_4_1[0]), + .I1(plm_scr3_reg_raw_char[5]), + .I2(plm_scr3_reg_raw_char[7]), + .LO(plm_scr3_reg_com_4[0]) + ); + defparam plm_scr3_input_decoder_N_14391_i.INIT = 8'hFE; + LUT3_L plm_scr3_input_decoder_N_14391_i ( + .I0(plm_reg_disdes), + .I1(plm_reg_raw_char_pass[1]), + .I2(plm_scr3_reg_raw_char_is_k[1]), + .LO(plm_scr3_N_14391_i) + ); + defparam plm_scr3_input_decoder_N_14375_i.INIT = 8'hFE; + LUT3_L plm_scr3_input_decoder_N_14375_i ( + .I0(plm_reg_disdes), + .I1(plm_reg_raw_char_pass[0]), + .I2(plm_scr3_reg_raw_char_is_k[0]), + .LO(plm_scr3_N_14375_i) + ); + defparam plm_scr3_input_decoder_reg_skp_3_0_a2_1_.INIT = 8'h02; + LUT3_L plm_scr3_input_decoder_reg_skp_3_0_a2_1_ ( + .I0(plm_scr3_reg_com_3_1[1]), + .I1(plm_scr3_reg_raw_char[13]), + .I2(plm_scr3_reg_raw_char[15]), + .LO(plm_scr3_reg_skp_3[1]) + ); + defparam plm_scr3_lfsrs_N_87839_i.INIT = 16'hF7B3; + LUT4_L plm_scr3_lfsrs_N_87839_i ( + .I0(plm_scr3_N_20848_i), + .I1(plm_scr3_N_20851_i), + .I2(plm_scr3_one_adv2[15]), + .I3(plm_scr3_reg_lfsr_two_15__541), + .LO(plm_scr3_N_87839_i) + ); + defparam plm_scr3_lfsrs_N_87838_i.INIT = 16'hF7B3; + LUT4_L plm_scr3_lfsrs_N_87838_i ( + .I0(plm_scr3_N_20848_i), + .I1(plm_scr3_N_20851_i), + .I2(plm_scr3_one_adv2[14]), + .I3(plm_scr3_reg_lfsr_two_14__1200), + .LO(plm_scr3_N_87838_i) + ); + defparam plm_scr3_lfsrs_N_87837_i.INIT = 16'hF7B3; + LUT4_L plm_scr3_lfsrs_N_87837_i ( + .I0(plm_scr3_N_20848_i), + .I1(plm_scr3_N_20851_i), + .I2(plm_scr3_one_adv2[13]), + .I3(plm_scr3_reg_lfsr_two_13__540), + .LO(plm_scr3_N_87837_i) + ); + defparam plm_scr3_lfsrs_N_85463_i.INIT = 16'hFDDD; + LUT4_L plm_scr3_lfsrs_N_85463_i ( + .I0(plm_scr3_N_20849_i), + .I1(plm_scr3_reg_lfsr_one_12_iv_i_a2_1_12_), + .I2(plm_scr3_reg_lfsr_one29_0_a4_0), + .I3(plm_scr3_one_adv2[12]), + .LO(plm_scr3_N_85463_i) + ); + defparam plm_scr3_lfsrs_N_87836_i.INIT = 16'hF7B3; + LUT4_L plm_scr3_lfsrs_N_87836_i ( + .I0(plm_scr3_N_20848_i), + .I1(plm_scr3_N_20851_i), + .I2(plm_scr3_one_adv2[11]), + .I3(plm_scr3_reg_lfsr_two_11__539), + .LO(plm_scr3_N_87836_i) + ); + defparam plm_scr3_lfsrs_N_85462_i.INIT = 16'hDFDD; + LUT4_L plm_scr3_lfsrs_N_85462_i ( + .I0(plm_scr3_N_20849_i), + .I1(plm_scr3_reg_lfsr_one_12_iv_i_a2_0_1[10]), + .I2(plm_scr3_reg_lfsr_two_12_iv_i_o4[15]), + .I3(plm_scr3_reg_lfsr_two_10__1202), + .LO(plm_scr3_N_85462_i) + ); + defparam plm_scr3_lfsrs_N_85461_i.INIT = 16'hDFDD; + LUT4_L plm_scr3_lfsrs_N_85461_i ( + .I0(plm_scr3_N_20849_i), + .I1(plm_scr3_reg_lfsr_one_12_iv_i_a2_0_1[9]), + .I2(plm_scr3_reg_lfsr_two_12_iv_i_o4[15]), + .I3(plm_scr3_reg_lfsr_two_9__1203), + .LO(plm_scr3_N_85461_i) + ); + defparam plm_scr3_lfsrs_N_85460_i.INIT = 16'hDFDD; + LUT4_L plm_scr3_lfsrs_N_85460_i ( + .I0(plm_scr3_N_20849_i), + .I1(plm_scr3_reg_lfsr_one_12_iv_i_a2_0_1[8]), + .I2(plm_scr3_reg_lfsr_two_12_iv_i_o4[15]), + .I3(plm_scr3_reg_lfsr_two_8__1204), + .LO(plm_scr3_N_85460_i) + ); + defparam plm_scr3_lfsrs_N_85459_i.INIT = 16'hFDDD; + LUT4_L plm_scr3_lfsrs_N_85459_i ( + .I0(plm_scr3_N_20849_i), + .I1(plm_scr3_reg_lfsr_one_12_iv_i_a2_1_7_), + .I2(plm_scr3_reg_lfsr_one29_0_a4_0), + .I3(plm_scr3_one_adv2[7]), + .LO(plm_scr3_N_85459_i) + ); + defparam plm_scr3_lfsrs_N_85458_i.INIT = 16'hFDDD; + LUT4_L plm_scr3_lfsrs_N_85458_i ( + .I0(plm_scr3_N_20849_i), + .I1(plm_scr3_reg_lfsr_one_12_iv_i_a2[6]), + .I2(plm_scr3_reg_lfsr_one29_0_a4_0), + .I3(plm_scr3_one_adv2[6]), + .LO(plm_scr3_N_85458_i) + ); + defparam plm_scr3_lfsrs_N_85457_i.INIT = 16'hFDDD; + LUT4_L plm_scr3_lfsrs_N_85457_i ( + .I0(plm_scr3_N_20849_i), + .I1(plm_scr3_reg_lfsr_one_12_iv_i_a2_1_5_), + .I2(plm_scr3_reg_lfsr_one29_0_a4_0), + .I3(plm_scr3_one_adv2[5]), + .LO(plm_scr3_N_85457_i) + ); + defparam plm_scr3_lfsrs_reg_lfsr_one_12_0_iv_4_.INIT = 16'h0F0B; + LUT4_L plm_scr3_lfsrs_reg_lfsr_one_12_0_iv_4_ ( + .I0(plm_scr3_N_20848_i), + .I1(plm_scr3_N_20851_i), + .I2(plm_scr3_one_adv2_i_m[4]), + .I3(plm_scr3_reg_lfsr_two_4__1208), + .LO(plm_scr3_reg_lfsr_one_12[4]) + ); + defparam plm_scr3_lfsrs_N_85456_i.INIT = 16'hFDDD; + LUT4_L plm_scr3_lfsrs_N_85456_i ( + .I0(plm_scr3_N_20849_i), + .I1(plm_scr3_reg_lfsr_one_12_iv_i_a2_1_3_), + .I2(plm_scr3_reg_lfsr_one29_0_a4_0), + .I3(plm_scr3_one_adv2[3]), + .LO(plm_scr3_N_85456_i) + ); + defparam plm_scr3_lfsrs_N_87835_i.INIT = 16'hF7B3; + LUT4_L plm_scr3_lfsrs_N_87835_i ( + .I0(plm_scr3_N_20848_i), + .I1(plm_scr3_N_20851_i), + .I2(plm_scr3_one_adv2[2]), + .I3(plm_scr3_reg_lfsr_two_2__673), + .LO(plm_scr3_N_87835_i) + ); + defparam plm_scr3_lfsrs_N_87834_i.INIT = 16'hF7B3; + LUT4_L plm_scr3_lfsrs_N_87834_i ( + .I0(plm_scr3_N_20848_i), + .I1(plm_scr3_N_20851_i), + .I2(plm_scr3_one_adv2[1]), + .I3(plm_scr3_reg_lfsr_two_1__672), + .LO(plm_scr3_N_87834_i) + ); + defparam plm_scr3_lfsrs_N_87833_i.INIT = 16'hF7B3; + LUT4_L plm_scr3_lfsrs_N_87833_i ( + .I0(plm_scr3_N_20848_i), + .I1(plm_scr3_N_20851_i), + .I2(plm_scr3_one_adv2[0]), + .I3(plm_scr3_reg_lfsr_two_0__538), + .LO(plm_scr3_N_87833_i) + ); + defparam plm_scr3_lfsrs_N_85475_i.INIT = 16'hFDDD; + LUT4_L plm_scr3_lfsrs_N_85475_i ( + .I0(plm_scr3_N_20849_i), + .I1(plm_scr3_reg_lfsr_two_12_iv_i_a2_1[15]), + .I2(plm_scr3_reg_lfsr_one29_0_a4_0), + .I3(plm_scr3_two_adv2_15__1186), + .LO(plm_scr3_N_85475_i) + ); + defparam plm_scr3_lfsrs_N_85474_i.INIT = 16'hDFDD; + LUT4_L plm_scr3_lfsrs_N_85474_i ( + .I0(plm_scr3_N_20849_i), + .I1(plm_scr3_reg_lfsr_two_12_iv_i_a2_0_0[14]), + .I2(plm_scr3_reg_lfsr_two_12_iv_i_o4[15]), + .I3(plm_scr3_one_adv2[14]), + .LO(plm_scr3_N_85474_i) + ); + defparam plm_scr3_lfsrs_N_85473_i.INIT = 16'hDFDD; + LUT4_L plm_scr3_lfsrs_N_85473_i ( + .I0(plm_scr3_N_20849_i), + .I1(plm_scr3_reg_lfsr_two_12_iv_i_a2_0_1_13_), + .I2(plm_scr3_reg_lfsr_two_12_iv_i_o4[15]), + .I3(plm_scr3_one_adv2[13]), + .LO(plm_scr3_N_85473_i) + ); + defparam plm_scr3_lfsrs_reg_lfsr_two_12_0_iv_0_12_.INIT = 16'hC840; + LUT4_L plm_scr3_lfsrs_reg_lfsr_two_12_0_iv_0_12_ ( + .I0(plm_scr3_N_20848_i), + .I1(plm_scr3_N_20851_i), + .I2(plm_scr3_one_adv2[12]), + .I3(plm_scr3_two_adv2_12__1187), + .LO(plm_scr3_N_9735_i) + ); + defparam plm_scr3_lfsrs_N_85472_i.INIT = 16'hDFDD; + LUT4_L plm_scr3_lfsrs_N_85472_i ( + .I0(plm_scr3_N_20849_i), + .I1(plm_scr3_reg_lfsr_two_12_iv_i_a2_0_1_11_), + .I2(plm_scr3_reg_lfsr_two_12_iv_i_o4[15]), + .I3(plm_scr3_one_adv2[11]), + .LO(plm_scr3_N_85472_i) + ); + defparam plm_scr3_lfsrs_reg_lfsr_two_12_0_iv_0_10_.INIT = 16'hC840; + LUT4_L plm_scr3_lfsrs_reg_lfsr_two_12_0_iv_0_10_ ( + .I0(plm_scr3_N_20848_i), + .I1(plm_scr3_N_20851_i), + .I2(plm_scr3_one_adv2[10]), + .I3(plm_scr3_two_adv2_10__1188), + .LO(plm_scr3_N_9737_i) + ); + defparam plm_scr3_lfsrs_reg_lfsr_two_12_iv_0_9_.INIT = 16'h2220; + LUT4_L plm_scr3_lfsrs_reg_lfsr_two_12_iv_0_9_ ( + .I0(plm_scr3_N_20849_i), + .I1(plm_scr3_reg_lfsr_two_12_iv_0_a2_0_1_9_), + .I2(plm_scr3_reg_lfsr_two_12_iv_i_o4[15]), + .I3(plm_scr3_one_adv2[9]), + .LO(plm_scr3_N_9738_i) + ); + defparam plm_scr3_lfsrs_reg_lfsr_two_12_iv_0_8_.INIT = 16'h2220; + LUT4_L plm_scr3_lfsrs_reg_lfsr_two_12_iv_0_8_ ( + .I0(plm_scr3_N_20849_i), + .I1(plm_scr3_reg_lfsr_two_12_iv_0_a2_0_0_8_), + .I2(plm_scr3_reg_lfsr_two_12_iv_i_o4[15]), + .I3(plm_scr3_one_adv2[8]), + .LO(plm_scr3_N_9739_i) + ); + defparam plm_scr3_lfsrs_reg_lfsr_two_12_0_iv_0_7_.INIT = 16'hC840; + LUT4_L plm_scr3_lfsrs_reg_lfsr_two_12_0_iv_0_7_ ( + .I0(plm_scr3_N_20848_i), + .I1(plm_scr3_N_20851_i), + .I2(plm_scr3_one_adv2[7]), + .I3(plm_scr3_two_adv2_7__1189), + .LO(plm_scr3_N_9740_i) + ); + defparam plm_scr3_lfsrs_reg_lfsr_two_12_0_iv_0_6_.INIT = 16'hC840; + LUT4_L plm_scr3_lfsrs_reg_lfsr_two_12_0_iv_0_6_ ( + .I0(plm_scr3_N_20848_i), + .I1(plm_scr3_N_20851_i), + .I2(plm_scr3_one_adv2[6]), + .I3(plm_scr3_two_adv2_6__1190), + .LO(plm_scr3_N_9741_i) + ); + defparam plm_scr3_lfsrs_reg_lfsr_two_12_iv_0_5_.INIT = 16'h2220; + LUT4_L plm_scr3_lfsrs_reg_lfsr_two_12_iv_0_5_ ( + .I0(plm_scr3_N_20849_i), + .I1(plm_scr3_reg_lfsr_two_12_iv_0_a2_0_0_5_), + .I2(plm_scr3_reg_lfsr_two_12_iv_i_o4[15]), + .I3(plm_scr3_one_adv2[5]), + .LO(plm_scr3_N_9742_i) + ); + defparam plm_scr3_lfsrs_N_85468_i.INIT = 16'hDFDD; + LUT4_L plm_scr3_lfsrs_N_85468_i ( + .I0(plm_scr3_N_20849_i), + .I1(plm_scr3_reg_lfsr_two_12_iv_i_a2_0_1_4_), + .I2(plm_scr3_reg_lfsr_two_12_iv_i_o4[15]), + .I3(plm_scr3_one_adv2[4]), + .LO(plm_scr3_N_85468_i) + ); + defparam plm_scr3_lfsrs_reg_lfsr_two_12_iv_0_3_.INIT = 16'h2220; + LUT4_L plm_scr3_lfsrs_reg_lfsr_two_12_iv_0_3_ ( + .I0(plm_scr3_N_20849_i), + .I1(plm_scr3_reg_lfsr_two_12_iv_0_a2_0_1_3_), + .I2(plm_scr3_reg_lfsr_two_12_iv_i_o4[15]), + .I3(plm_scr3_one_adv2[3]), + .LO(plm_scr3_N_9744_i) + ); + defparam plm_scr3_lfsrs_N_85466_i.INIT = 16'hDFDD; + LUT4_L plm_scr3_lfsrs_N_85466_i ( + .I0(plm_scr3_N_20849_i), + .I1(plm_scr3_reg_lfsr_two_12_iv_i_a2_0_1_2_), + .I2(plm_scr3_reg_lfsr_two_12_iv_i_o4[15]), + .I3(plm_scr3_one_adv2[2]), + .LO(plm_scr3_N_85466_i) + ); + defparam plm_scr3_lfsrs_N_85465_i.INIT = 16'hDFDD; + LUT4_L plm_scr3_lfsrs_N_85465_i ( + .I0(plm_scr3_N_20849_i), + .I1(plm_scr3_reg_lfsr_two_12_iv_i_a2_0_1_1_), + .I2(plm_scr3_reg_lfsr_two_12_iv_i_o4[15]), + .I3(plm_scr3_one_adv2[1]), + .LO(plm_scr3_N_85465_i) + ); + defparam plm_scr3_lfsrs_N_85464_i.INIT = 16'hDFDD; + LUT4_L plm_scr3_lfsrs_N_85464_i ( + .I0(plm_scr3_N_20849_i), + .I1(plm_scr3_reg_lfsr_two_12_iv_i_a2_0_1_0_), + .I2(plm_scr3_reg_lfsr_two_12_iv_i_o4[15]), + .I3(plm_scr3_one_adv2[0]), + .LO(plm_scr3_N_85464_i) + ); + defparam plm_scr3_lfsrs_reg_lfsr_one29_0_a4.INIT = 8'h01; + LUT3 plm_scr3_lfsrs_reg_lfsr_one29_0_a4 ( + .I0(plm_scr3_reg_com[1]), + .I1(plm_scr3_reg_skp[1]), + .I2(plm_scr3_reg_skp[0]), + .O(plm_scr3_reg_lfsr_one29_0_a4_0) + ); + FDC plm_scr3_reg_disable_scr ( + .C(mgt_clk), + .D(plm_N_61233_i_703), + .Q(plm_reg_disdes), + .CLR(plm_rst) + ); + FDC plm_scr3_reg_tx_data_0_ ( + .C(mgt_clk), + .D(plm_scr3_reg_tx_data_12[0]), + .Q(plm_tx3_data[0]), + .CLR(plm_rst) + ); + FDC plm_scr3_reg_tx_data_15_ ( + .C(mgt_clk), + .D(plm_scr3_reg_tx_data_6[15]), + .Q(plm_tx3_data[15]), + .CLR(plm_rst) + ); + FDC plm_scr3_reg_tx_data_14_ ( + .C(mgt_clk), + .D(plm_scr3_reg_tx_data_6[14]), + .Q(plm_tx3_data[14]), + .CLR(plm_rst) + ); + FDC plm_scr3_reg_tx_data_13_ ( + .C(mgt_clk), + .D(plm_scr3_reg_tx_data_6[13]), + .Q(plm_tx3_data[13]), + .CLR(plm_rst) + ); + FDC plm_scr3_reg_tx_data_12_ ( + .C(mgt_clk), + .D(plm_scr3_reg_tx_data_6[12]), + .Q(plm_tx3_data[12]), + .CLR(plm_rst) + ); + FDC plm_scr3_reg_tx_data_11_ ( + .C(mgt_clk), + .D(plm_scr3_reg_tx_data_6[11]), + .Q(plm_tx3_data[11]), + .CLR(plm_rst) + ); + FDC plm_scr3_reg_tx_data_10_ ( + .C(mgt_clk), + .D(plm_scr3_reg_tx_data_6[10]), + .Q(plm_tx3_data[10]), + .CLR(plm_rst) + ); + FDC plm_scr3_reg_tx_data_9_ ( + .C(mgt_clk), + .D(plm_scr3_reg_tx_data_6[9]), + .Q(plm_tx3_data[9]), + .CLR(plm_rst) + ); + FDC plm_scr3_reg_tx_data_8_ ( + .C(mgt_clk), + .D(plm_scr3_reg_tx_data_6[8]), + .Q(plm_tx3_data[8]), + .CLR(plm_rst) + ); + FDC plm_scr3_reg_tx_data_7_ ( + .C(mgt_clk), + .D(plm_scr3_reg_tx_data_12[7]), + .Q(plm_tx3_data[7]), + .CLR(plm_rst) + ); + FDC plm_scr3_reg_tx_data_6_ ( + .C(mgt_clk), + .D(plm_scr3_reg_tx_data_12[6]), + .Q(plm_tx3_data[6]), + .CLR(plm_rst) + ); + FDC plm_scr3_reg_tx_data_5_ ( + .C(mgt_clk), + .D(plm_scr3_reg_tx_data_12[5]), + .Q(plm_tx3_data[5]), + .CLR(plm_rst) + ); + FDC plm_scr3_reg_tx_data_4_ ( + .C(mgt_clk), + .D(plm_scr3_reg_tx_data_12[4]), + .Q(plm_tx3_data[4]), + .CLR(plm_rst) + ); + FDC plm_scr3_reg_tx_data_3_ ( + .C(mgt_clk), + .D(plm_scr3_reg_tx_data_12[3]), + .Q(plm_tx3_data[3]), + .CLR(plm_rst) + ); + FDC plm_scr3_reg_tx_data_2_ ( + .C(mgt_clk), + .D(plm_scr3_reg_tx_data_12[2]), + .Q(plm_tx3_data[2]), + .CLR(plm_rst) + ); + FDC plm_scr3_reg_tx_data_1_ ( + .C(mgt_clk), + .D(plm_scr3_reg_tx_data_12[1]), + .Q(plm_tx3_data[1]), + .CLR(plm_rst) + ); + FDC plm_scr3_reg_skp_0_ ( + .C(mgt_clk), + .D(plm_scr3_reg_skp_4[0]), + .Q(plm_scr3_reg_skp[0]), + .CLR(plm_rst) + ); + FDC plm_scr3_reg_com_1_ ( + .C(mgt_clk), + .D(plm_scr3_reg_com_3[1]), + .Q(plm_scr3_reg_com[1]), + .CLR(plm_rst) + ); + FDC plm_scr3_reg_com_0_ ( + .C(mgt_clk), + .D(plm_scr3_reg_com_4[0]), + .Q(plm_scr3_reg_com[0]), + .CLR(plm_rst) + ); + FDC plm_scr3_reg_dis_1_ ( + .C(mgt_clk), + .D(plm_scr3_N_14391_i), + .Q(plm_scr3_reg_dis[1]), + .CLR(plm_rst) + ); + FDC plm_scr3_reg_dis_0_ ( + .C(mgt_clk), + .D(plm_scr3_N_14375_i), + .Q(plm_scr3_reg_dis[0]), + .CLR(plm_rst) + ); + FDC plm_scr3_reg_tx_char_is_k_1_ ( + .C(mgt_clk), + .D(plm_scr3_reg_kkk[1]), + .Q(plm_tx3_char_is_k[1]), + .CLR(plm_rst) + ); + FDC plm_scr3_reg_tx_char_is_k_0_ ( + .C(mgt_clk), + .D(plm_scr3_reg_kkk[0]), + .Q(plm_tx3_char_is_k[0]), + .CLR(plm_rst) + ); + FDC plm_scr3_reg_raw_char_9_ ( + .C(mgt_clk), + .D(plm_tx3_raw_char[9]), + .Q(plm_scr3_reg_raw_char[9]), + .CLR(plm_rst) + ); + FDC plm_scr3_reg_raw_char_8_ ( + .C(mgt_clk), + .D(plm_tx3_raw_char[8]), + .Q(plm_scr3_reg_raw_char[8]), + .CLR(plm_rst) + ); + FDC plm_scr3_reg_raw_char_7_ ( + .C(mgt_clk), + .D(plm_tx3_raw_char[7]), + .Q(plm_scr3_reg_raw_char[7]), + .CLR(plm_rst) + ); + FDC plm_scr3_reg_raw_char_6_ ( + .C(mgt_clk), + .D(plm_tx3_raw_char[6]), + .Q(plm_scr3_reg_raw_char[6]), + .CLR(plm_rst) + ); + FDC plm_scr3_reg_raw_char_5_ ( + .C(mgt_clk), + .D(plm_tx3_raw_char[5]), + .Q(plm_scr3_reg_raw_char[5]), + .CLR(plm_rst) + ); + FDC plm_scr3_reg_raw_char_4_ ( + .C(mgt_clk), + .D(plm_tx3_raw_char[4]), + .Q(plm_scr3_reg_raw_char[4]), + .CLR(plm_rst) + ); + FDC plm_scr3_reg_raw_char_3_ ( + .C(mgt_clk), + .D(plm_tx3_raw_char[3]), + .Q(plm_scr3_reg_raw_char[3]), + .CLR(plm_rst) + ); + FDC plm_scr3_reg_raw_char_2_ ( + .C(mgt_clk), + .D(plm_tx3_raw_char[2]), + .Q(plm_scr3_reg_raw_char[2]), + .CLR(plm_rst) + ); + FDC plm_scr3_reg_raw_char_1_ ( + .C(mgt_clk), + .D(plm_tx3_raw_char[1]), + .Q(plm_scr3_reg_raw_char[1]), + .CLR(plm_rst) + ); + FDC plm_scr3_reg_raw_char_0_ ( + .C(mgt_clk), + .D(plm_tx3_raw_char[0]), + .Q(plm_scr3_reg_raw_char[0]), + .CLR(plm_rst) + ); + FDC plm_scr3_reg_raw_char_pass_1_ ( + .C(mgt_clk), + .D(plm_tx3_raw_char_pass[1]), + .Q(plm_reg_raw_char_pass[1]), + .CLR(plm_rst) + ); + FDC plm_scr3_reg_raw_char_pass_0_ ( + .C(mgt_clk), + .D(plm_tx3_raw_char_pass[0]), + .Q(plm_reg_raw_char_pass[0]), + .CLR(plm_rst) + ); + FDC plm_scr3_reg_raw_char_is_k_1_ ( + .C(mgt_clk), + .D(plm_tx3_raw_char_is_k[1]), + .Q(plm_scr3_reg_raw_char_is_k[1]), + .CLR(plm_rst) + ); + FDC plm_scr3_reg_raw_char_is_k_0_ ( + .C(mgt_clk), + .D(plm_tx3_raw_char_is_k[0]), + .Q(plm_scr3_reg_raw_char_is_k[0]), + .CLR(plm_rst) + ); + FDC plm_scr3_reg_skp_1_ ( + .C(mgt_clk), + .D(plm_scr3_reg_skp_3[1]), + .Q(plm_scr3_reg_skp[1]), + .CLR(plm_rst) + ); + FDC plm_scr3_reg_dat_6_ ( + .C(mgt_clk), + .D(plm_scr3_reg_raw_char[6]), + .Q(plm_scr3_reg_dat[6]), + .CLR(plm_rst) + ); + FDC plm_scr3_reg_dat_5_ ( + .C(mgt_clk), + .D(plm_scr3_reg_raw_char[5]), + .Q(plm_scr3_reg_dat[5]), + .CLR(plm_rst) + ); + FDC plm_scr3_reg_dat_4_ ( + .C(mgt_clk), + .D(plm_scr3_reg_raw_char[4]), + .Q(plm_scr3_reg_dat[4]), + .CLR(plm_rst) + ); + FDC plm_scr3_reg_dat_3_ ( + .C(mgt_clk), + .D(plm_scr3_reg_raw_char[3]), + .Q(plm_scr3_reg_dat[3]), + .CLR(plm_rst) + ); + FDC plm_scr3_reg_dat_2_ ( + .C(mgt_clk), + .D(plm_scr3_reg_raw_char[2]), + .Q(plm_scr3_reg_dat[2]), + .CLR(plm_rst) + ); + FDC plm_scr3_reg_dat_1_ ( + .C(mgt_clk), + .D(plm_scr3_reg_raw_char[1]), + .Q(plm_scr3_reg_dat[1]), + .CLR(plm_rst) + ); + FDC plm_scr3_reg_dat_0_ ( + .C(mgt_clk), + .D(plm_scr3_reg_raw_char[0]), + .Q(plm_scr3_reg_dat[0]), + .CLR(plm_rst) + ); + FDC plm_scr3_reg_kkk_1_ ( + .C(mgt_clk), + .D(plm_scr3_reg_raw_char_is_k[1]), + .Q(plm_scr3_reg_kkk[1]), + .CLR(plm_rst) + ); + FDC plm_scr3_reg_kkk_0_ ( + .C(mgt_clk), + .D(plm_scr3_reg_raw_char_is_k[0]), + .Q(plm_scr3_reg_kkk[0]), + .CLR(plm_rst) + ); + FDC plm_scr3_reg_raw_char_15_ ( + .C(mgt_clk), + .D(plm_tx3_raw_char[15]), + .Q(plm_scr3_reg_raw_char[15]), + .CLR(plm_rst) + ); + FDC plm_scr3_reg_raw_char_14_ ( + .C(mgt_clk), + .D(plm_tx3_raw_char[14]), + .Q(plm_scr3_reg_raw_char[14]), + .CLR(plm_rst) + ); + FDC plm_scr3_reg_raw_char_13_ ( + .C(mgt_clk), + .D(plm_tx3_raw_char[13]), + .Q(plm_scr3_reg_raw_char[13]), + .CLR(plm_rst) + ); + FDC plm_scr3_reg_raw_char_12_ ( + .C(mgt_clk), + .D(plm_tx3_raw_char[12]), + .Q(plm_scr3_reg_raw_char[12]), + .CLR(plm_rst) + ); + FDC plm_scr3_reg_raw_char_11_ ( + .C(mgt_clk), + .D(plm_tx3_raw_char[11]), + .Q(plm_scr3_reg_raw_char[11]), + .CLR(plm_rst) + ); + FDC plm_scr3_reg_raw_char_10_ ( + .C(mgt_clk), + .D(plm_tx3_raw_char[10]), + .Q(plm_scr3_reg_raw_char[10]), + .CLR(plm_rst) + ); + FDC plm_scr3_reg_dat_15_ ( + .C(mgt_clk), + .D(plm_scr3_reg_raw_char[15]), + .Q(plm_scr3_reg_dat[15]), + .CLR(plm_rst) + ); + FDC plm_scr3_reg_dat_14_ ( + .C(mgt_clk), + .D(plm_scr3_reg_raw_char[14]), + .Q(plm_scr3_reg_dat[14]), + .CLR(plm_rst) + ); + FDC plm_scr3_reg_dat_13_ ( + .C(mgt_clk), + .D(plm_scr3_reg_raw_char[13]), + .Q(plm_scr3_reg_dat[13]), + .CLR(plm_rst) + ); + FDC plm_scr3_reg_dat_12_ ( + .C(mgt_clk), + .D(plm_scr3_reg_raw_char[12]), + .Q(plm_scr3_reg_dat[12]), + .CLR(plm_rst) + ); + FDC plm_scr3_reg_dat_11_ ( + .C(mgt_clk), + .D(plm_scr3_reg_raw_char[11]), + .Q(plm_scr3_reg_dat[11]), + .CLR(plm_rst) + ); + FDC plm_scr3_reg_dat_10_ ( + .C(mgt_clk), + .D(plm_scr3_reg_raw_char[10]), + .Q(plm_scr3_reg_dat[10]), + .CLR(plm_rst) + ); + FDC plm_scr3_reg_dat_9_ ( + .C(mgt_clk), + .D(plm_scr3_reg_raw_char[9]), + .Q(plm_scr3_reg_dat[9]), + .CLR(plm_rst) + ); + FDC plm_scr3_reg_dat_8_ ( + .C(mgt_clk), + .D(plm_scr3_reg_raw_char[8]), + .Q(plm_scr3_reg_dat[8]), + .CLR(plm_rst) + ); + FDC plm_scr3_reg_dat_7_ ( + .C(mgt_clk), + .D(plm_scr3_reg_raw_char[7]), + .Q(plm_scr3_reg_dat[7]), + .CLR(plm_rst) + ); + FDPE plm_scr3_reg_lfsr_one_15_ ( + .PRE(plm_rst), + .CE(plm_scr3_reg_lfsr_one32_i), + .C(mgt_clk), + .D(plm_scr3_N_87839_i), + .Q(plm_scr3_reg_lfsr_one_15__496) + ); + FDPE plm_scr3_reg_lfsr_one_14_ ( + .PRE(plm_rst), + .CE(plm_scr3_reg_lfsr_one32_i), + .C(mgt_clk), + .D(plm_scr3_N_87838_i), + .Q(plm_scr3_reg_lfsr_one_14__692) + ); + FDPE plm_scr3_reg_lfsr_one_13_ ( + .PRE(plm_rst), + .CE(plm_scr3_reg_lfsr_one32_i), + .C(mgt_clk), + .D(plm_scr3_N_87837_i), + .Q(plm_scr3_reg_lfsr_one_13__499) + ); + FDPE plm_scr3_reg_lfsr_one_12_ ( + .PRE(plm_rst), + .CE(plm_scr3_reg_lfsr_one32_i), + .C(mgt_clk), + .D(plm_scr3_N_85463_i), + .Q(plm_scr3_reg_lfsr_one_12__1191) + ); + FDPE plm_scr3_reg_lfsr_one_11_ ( + .PRE(plm_rst), + .CE(plm_scr3_reg_lfsr_one32_i), + .C(mgt_clk), + .D(plm_scr3_N_87836_i), + .Q(plm_scr3_reg_lfsr_one_11__638) + ); + FDPE plm_scr3_reg_lfsr_one_10_ ( + .PRE(plm_rst), + .CE(plm_scr3_reg_lfsr_one32_i), + .C(mgt_clk), + .D(plm_scr3_N_85462_i), + .Q(plm_scr3_reg_lfsr_one_10__1192) + ); + FDPE plm_scr3_reg_lfsr_one_9_ ( + .PRE(plm_rst), + .CE(plm_scr3_reg_lfsr_one32_i), + .C(mgt_clk), + .D(plm_scr3_N_85461_i), + .Q(plm_scr3_reg_lfsr_one_9__1193) + ); + FDPE plm_scr3_reg_lfsr_one_8_ ( + .PRE(plm_rst), + .CE(plm_scr3_reg_lfsr_one32_i), + .C(mgt_clk), + .D(plm_scr3_N_85460_i), + .Q(plm_scr3_reg_lfsr_one_8__1194) + ); + FDPE plm_scr3_reg_lfsr_one_7_ ( + .PRE(plm_rst), + .CE(plm_scr3_reg_lfsr_one32_i), + .C(mgt_clk), + .D(plm_scr3_N_85459_i), + .Q(plm_scr3_reg_lfsr_one_7__1195) + ); + FDPE plm_scr3_reg_lfsr_one_6_ ( + .PRE(plm_rst), + .CE(plm_scr3_reg_lfsr_one32_i), + .C(mgt_clk), + .D(plm_scr3_N_85458_i), + .Q(plm_scr3_reg_lfsr_one_6__1196) + ); + FDPE plm_scr3_reg_lfsr_one_5_ ( + .PRE(plm_rst), + .CE(plm_scr3_reg_lfsr_one32_i), + .C(mgt_clk), + .D(plm_scr3_N_85457_i), + .Q(plm_scr3_reg_lfsr_one_5__1197) + ); + FDPE plm_scr3_reg_lfsr_one_4_ ( + .PRE(plm_rst), + .CE(plm_scr3_reg_lfsr_one32_i), + .C(mgt_clk), + .D(plm_scr3_reg_lfsr_one_12[4]), + .Q(plm_scr3_reg_lfsr_one_4__1198) + ); + FDPE plm_scr3_reg_lfsr_one_3_ ( + .PRE(plm_rst), + .CE(plm_scr3_reg_lfsr_one32_i), + .C(mgt_clk), + .D(plm_scr3_N_85456_i), + .Q(plm_scr3_reg_lfsr_one_3__498) + ); + FDPE plm_scr3_reg_lfsr_one_2_ ( + .PRE(plm_rst), + .CE(plm_scr3_reg_lfsr_one32_i), + .C(mgt_clk), + .D(plm_scr3_N_87835_i), + .Q(plm_scr3_reg_lfsr_one_2__1199) + ); + FDPE plm_scr3_reg_lfsr_one_1_ ( + .PRE(plm_rst), + .CE(plm_scr3_reg_lfsr_one32_i), + .C(mgt_clk), + .D(plm_scr3_N_87834_i), + .Q(plm_scr3_reg_lfsr_one_1__495) + ); + FDPE plm_scr3_reg_lfsr_one_0_ ( + .PRE(plm_rst), + .CE(plm_scr3_reg_lfsr_one32_i), + .C(mgt_clk), + .D(plm_scr3_N_87833_i), + .Q(plm_scr3_reg_lfsr_one_0__637) + ); + FDPE plm_scr3_reg_lfsr_two_15_ ( + .PRE(plm_rst), + .CE(plm_scr3_reg_lfsr_one32_i), + .C(mgt_clk), + .D(plm_scr3_N_85475_i), + .Q(plm_scr3_reg_lfsr_two_15__541) + ); + FDPE plm_scr3_reg_lfsr_two_14_ ( + .PRE(plm_rst), + .CE(plm_scr3_reg_lfsr_one32_i), + .C(mgt_clk), + .D(plm_scr3_N_85474_i), + .Q(plm_scr3_reg_lfsr_two_14__1200) + ); + FDPE plm_scr3_reg_lfsr_two_13_ ( + .PRE(plm_rst), + .CE(plm_scr3_reg_lfsr_one32_i), + .C(mgt_clk), + .D(plm_scr3_N_85473_i), + .Q(plm_scr3_reg_lfsr_two_13__540) + ); + FDCE plm_scr3_reg_lfsr_two_12_ ( + .CE(plm_scr3_reg_lfsr_one32_i), + .C(mgt_clk), + .D(plm_scr3_N_9735_i), + .Q(plm_scr3_reg_lfsr_two_12__1201), + .CLR(plm_rst) + ); + FDPE plm_scr3_reg_lfsr_two_11_ ( + .PRE(plm_rst), + .CE(plm_scr3_reg_lfsr_one32_i), + .C(mgt_clk), + .D(plm_scr3_N_85472_i), + .Q(plm_scr3_reg_lfsr_two_11__539) + ); + FDCE plm_scr3_reg_lfsr_two_10_ ( + .CE(plm_scr3_reg_lfsr_one32_i), + .C(mgt_clk), + .D(plm_scr3_N_9737_i), + .Q(plm_scr3_reg_lfsr_two_10__1202), + .CLR(plm_rst) + ); + FDCE plm_scr3_reg_lfsr_two_9_ ( + .CE(plm_scr3_reg_lfsr_one32_i), + .C(mgt_clk), + .D(plm_scr3_N_9738_i), + .Q(plm_scr3_reg_lfsr_two_9__1203), + .CLR(plm_rst) + ); + FDCE plm_scr3_reg_lfsr_two_8_ ( + .CE(plm_scr3_reg_lfsr_one32_i), + .C(mgt_clk), + .D(plm_scr3_N_9739_i), + .Q(plm_scr3_reg_lfsr_two_8__1204), + .CLR(plm_rst) + ); + FDCE plm_scr3_reg_lfsr_two_7_ ( + .CE(plm_scr3_reg_lfsr_one32_i), + .C(mgt_clk), + .D(plm_scr3_N_9740_i), + .Q(plm_scr3_reg_lfsr_two_7__1205), + .CLR(plm_rst) + ); + FDCE plm_scr3_reg_lfsr_two_6_ ( + .CE(plm_scr3_reg_lfsr_one32_i), + .C(mgt_clk), + .D(plm_scr3_N_9741_i), + .Q(plm_scr3_reg_lfsr_two_6__1206), + .CLR(plm_rst) + ); + FDCE plm_scr3_reg_lfsr_two_5_ ( + .CE(plm_scr3_reg_lfsr_one32_i), + .C(mgt_clk), + .D(plm_scr3_N_9742_i), + .Q(plm_scr3_reg_lfsr_two_5__1207), + .CLR(plm_rst) + ); + FDPE plm_scr3_reg_lfsr_two_4_ ( + .PRE(plm_rst), + .CE(plm_scr3_reg_lfsr_one32_i), + .C(mgt_clk), + .D(plm_scr3_N_85468_i), + .Q(plm_scr3_reg_lfsr_two_4__1208) + ); + FDCE plm_scr3_reg_lfsr_two_3_ ( + .CE(plm_scr3_reg_lfsr_one32_i), + .C(mgt_clk), + .D(plm_scr3_N_9744_i), + .Q(plm_scr3_reg_lfsr_two_3__1209), + .CLR(plm_rst) + ); + FDPE plm_scr3_reg_lfsr_two_2_ ( + .PRE(plm_rst), + .CE(plm_scr3_reg_lfsr_one32_i), + .C(mgt_clk), + .D(plm_scr3_N_85466_i), + .Q(plm_scr3_reg_lfsr_two_2__673) + ); + FDPE plm_scr3_reg_lfsr_two_1_ ( + .PRE(plm_rst), + .CE(plm_scr3_reg_lfsr_one32_i), + .C(mgt_clk), + .D(plm_scr3_N_85465_i), + .Q(plm_scr3_reg_lfsr_two_1__672) + ); + FDPE plm_scr3_reg_lfsr_two_0_ ( + .PRE(plm_rst), + .CE(plm_scr3_reg_lfsr_one32_i), + .C(mgt_clk), + .D(plm_scr3_N_85464_i), + .Q(plm_scr3_reg_lfsr_two_0__538) + ); + VCC plm_tsi0_VCC ( + .P(plm_tsi0_VCC_1283) + ); + GND plm_tsi0_GND ( + .G(plm_tsi0_GND_1282) + ); + SRL16 plm_tsi0_D00 ( + .D(plm_rx0_raw_dat[0]), + .Q(plm_tsi0_do[0]), + .CLK(mgt_clk), + .A0(plm_tsi0_VCC_1283), + .A1(plm_tsi0_GND_1282), + .A2(plm_tsi0_VCC_1283), + .A3(plm_tsi0_GND_1282) + ); + SRL16 plm_tsi0_D01 ( + .D(plm_rx0_raw_dat[1]), + .Q(plm_tsi0_do[1]), + .CLK(mgt_clk), + .A0(plm_tsi0_VCC_1283), + .A1(plm_tsi0_GND_1282), + .A2(plm_tsi0_VCC_1283), + .A3(plm_tsi0_GND_1282) + ); + SRL16 plm_tsi0_D02 ( + .D(plm_rx0_raw_dat[2]), + .Q(plm_tsi0_do[2]), + .CLK(mgt_clk), + .A0(plm_tsi0_VCC_1283), + .A1(plm_tsi0_GND_1282), + .A2(plm_tsi0_VCC_1283), + .A3(plm_tsi0_GND_1282) + ); + SRL16 plm_tsi0_D03 ( + .D(plm_rx0_raw_dat[3]), + .Q(plm_tsi0_do[3]), + .CLK(mgt_clk), + .A0(plm_tsi0_VCC_1283), + .A1(plm_tsi0_GND_1282), + .A2(plm_tsi0_VCC_1283), + .A3(plm_tsi0_GND_1282) + ); + SRL16 plm_tsi0_D04 ( + .D(plm_rx0_raw_dat[4]), + .Q(plm_tsi0_do[4]), + .CLK(mgt_clk), + .A0(plm_tsi0_VCC_1283), + .A1(plm_tsi0_GND_1282), + .A2(plm_tsi0_VCC_1283), + .A3(plm_tsi0_GND_1282) + ); + SRL16 plm_tsi0_D05 ( + .D(plm_rx0_raw_dat[5]), + .Q(plm_tsi0_do[5]), + .CLK(mgt_clk), + .A0(plm_tsi0_VCC_1283), + .A1(plm_tsi0_GND_1282), + .A2(plm_tsi0_VCC_1283), + .A3(plm_tsi0_GND_1282) + ); + SRL16 plm_tsi0_D06 ( + .D(plm_rx0_raw_dat[6]), + .Q(plm_tsi0_do[6]), + .CLK(mgt_clk), + .A0(plm_tsi0_VCC_1283), + .A1(plm_tsi0_GND_1282), + .A2(plm_tsi0_VCC_1283), + .A3(plm_tsi0_GND_1282) + ); + SRL16 plm_tsi0_D07 ( + .D(plm_rx0_raw_dat[7]), + .Q(plm_tsi0_do[7]), + .CLK(mgt_clk), + .A0(plm_tsi0_VCC_1283), + .A1(plm_tsi0_GND_1282), + .A2(plm_tsi0_VCC_1283), + .A3(plm_tsi0_GND_1282) + ); + SRL16 plm_tsi0_D08 ( + .D(plm_rx0_raw_dat[8]), + .Q(plm_tsi0_do[8]), + .CLK(mgt_clk), + .A0(plm_tsi0_VCC_1283), + .A1(plm_tsi0_GND_1282), + .A2(plm_tsi0_VCC_1283), + .A3(plm_tsi0_GND_1282) + ); + SRL16 plm_tsi0_D09 ( + .D(plm_rx0_raw_dat[9]), + .Q(plm_tsi0_do[9]), + .CLK(mgt_clk), + .A0(plm_tsi0_VCC_1283), + .A1(plm_tsi0_GND_1282), + .A2(plm_tsi0_VCC_1283), + .A3(plm_tsi0_GND_1282) + ); + SRL16 plm_tsi0_D10 ( + .D(plm_rx0_raw_dat[10]), + .Q(plm_tsi0_do[10]), + .CLK(mgt_clk), + .A0(plm_tsi0_VCC_1283), + .A1(plm_tsi0_GND_1282), + .A2(plm_tsi0_VCC_1283), + .A3(plm_tsi0_GND_1282) + ); + SRL16 plm_tsi0_D11 ( + .D(plm_rx0_raw_dat[11]), + .Q(plm_tsi0_do[11]), + .CLK(mgt_clk), + .A0(plm_tsi0_VCC_1283), + .A1(plm_tsi0_GND_1282), + .A2(plm_tsi0_VCC_1283), + .A3(plm_tsi0_GND_1282) + ); + SRL16 plm_tsi0_D12 ( + .D(plm_rx0_raw_dat[12]), + .Q(plm_tsi0_do[12]), + .CLK(mgt_clk), + .A0(plm_tsi0_VCC_1283), + .A1(plm_tsi0_GND_1282), + .A2(plm_tsi0_VCC_1283), + .A3(plm_tsi0_GND_1282) + ); + SRL16 plm_tsi0_D13 ( + .D(plm_rx0_raw_dat[13]), + .Q(plm_tsi0_do[13]), + .CLK(mgt_clk), + .A0(plm_tsi0_VCC_1283), + .A1(plm_tsi0_GND_1282), + .A2(plm_tsi0_VCC_1283), + .A3(plm_tsi0_GND_1282) + ); + SRL16 plm_tsi0_D14 ( + .D(plm_rx0_raw_dat[14]), + .Q(plm_tsi0_do[14]), + .CLK(mgt_clk), + .A0(plm_tsi0_VCC_1283), + .A1(plm_tsi0_GND_1282), + .A2(plm_tsi0_VCC_1283), + .A3(plm_tsi0_GND_1282) + ); + SRL16 plm_tsi0_D15 ( + .D(plm_rx0_raw_dat[15]), + .Q(plm_tsi0_do[15]), + .CLK(mgt_clk), + .A0(plm_tsi0_VCC_1283), + .A1(plm_tsi0_GND_1282), + .A2(plm_tsi0_VCC_1283), + .A3(plm_tsi0_GND_1282) + ); + defparam plm_tsi0_un2_com_data_jog0.INIT = 4'h1; + LUT2 plm_tsi0_un2_com_data_jog0 ( + .I0(plm_tsi0_reg_dec8_5__1245), + .I1(plm_tsi0_reg_dec8_6__1244), + .O(plm_tsi0_un2_com_data_jog0_1210) + ); + defparam plm_tsi0_un2_recent_ts1.INIT = 16'h0001; + LUT4 plm_tsi0_un2_recent_ts1 ( + .I0(plm_tsi0_reg_ts1_timer[0]), + .I1(plm_tsi0_reg_ts1_timer[1]), + .I2(plm_tsi0_reg_ts1_timer[2]), + .I3(plm_tsi0_reg_ts1_timer[3]), + .O(plm_tsi0_un2_recent_ts1_1238) + ); + defparam plm_tsi0_un2_recent_ts2.INIT = 16'h0001; + LUT4 plm_tsi0_un2_recent_ts2 ( + .I0(plm_tsi0_reg_ts2_timer[0]), + .I1(plm_tsi0_reg_ts2_timer[1]), + .I2(plm_tsi0_reg_ts2_timer[2]), + .I3(plm_tsi0_reg_ts2_timer[3]), + .O(plm_tsi0_un2_recent_ts2_1235) + ); + defparam plm_tsi0_com_data_jog0_2.INIT = 16'h8880; + LUT4 plm_tsi0_com_data_jog0_2 ( + .I0(plm_tsi0_reg_dec6[5]), + .I1(plm_tsi0_reg_dec6_6105[12]), + .I2(plm_tsi0_reg_dec7_12__1267), + .I3(plm_tsi0_reg_dec7_13_), + .O(plm_tsi0_com_data_jog1_2) + ); + defparam plm_tsi0_ts2_inv1_jog1_1_4.INIT = 8'h80; + LUT3_L plm_tsi0_ts2_inv1_jog1_1_4 ( + .I0(plm_tsi0_reg_dec1[4]), + .I1(plm_tsi0_reg_dec1_6104[11]), + .I2(plm_tsi0_reg_dec2_4__1261), + .LO(plm_tsi0_ts2_inv1_jog1_1_4_1217) + ); + defparam plm_tsi0_ts2_inv1_jog1_1_5.INIT = 16'h8000; + LUT4 plm_tsi0_ts2_inv1_jog1_1_5 ( + .I0(plm_tsi0_reg_dec2_11__1253), + .I1(plm_tsi0_reg_dec3_4__1262), + .I2(plm_tsi0_reg_dec3_11__1254), + .I3(plm_tsi0_reg_dec4_4__1276), + .O(plm_tsi0_ts2_inv1_jog1_1_5_1216) + ); + defparam plm_tsi0_ts1_inv1_jog1_1_4.INIT = 8'h80; + LUT3_L plm_tsi0_ts1_inv1_jog1_1_4 ( + .I0(plm_tsi0_reg_dec1[2]), + .I1(plm_tsi0_reg_dec1_6104[9]), + .I2(plm_tsi0_reg_dec2_2__1265), + .LO(plm_tsi0_ts1_inv1_jog1_1_4_1213) + ); + defparam plm_tsi0_ts1_inv1_jog1_1_5.INIT = 16'h8000; + LUT4 plm_tsi0_ts1_inv1_jog1_1_5 ( + .I0(plm_tsi0_reg_dec2_9__1257), + .I1(plm_tsi0_reg_dec3_2__1266), + .I2(plm_tsi0_reg_dec3_9__1258), + .I3(plm_tsi0_reg_dec4_2__1249), + .O(plm_tsi0_ts1_inv1_jog1_1_5_1212) + ); + defparam plm_tsi0_ts2_inv0_jog1_1_4.INIT = 8'h80; + LUT3_L plm_tsi0_ts2_inv0_jog1_1_4 ( + .I0(plm_tsi0_reg_dec1[3]), + .I1(plm_tsi0_reg_dec1_6104[10]), + .I2(plm_tsi0_reg_dec2_3__1263), + .LO(plm_tsi0_ts2_inv0_jog1_1_4_1215) + ); + defparam plm_tsi0_ts2_inv0_jog1_1_5.INIT = 16'h8000; + LUT4 plm_tsi0_ts2_inv0_jog1_1_5 ( + .I0(plm_tsi0_reg_dec2_10__1255), + .I1(plm_tsi0_reg_dec3_3__1264), + .I2(plm_tsi0_reg_dec3_10__1256), + .I3(plm_tsi0_reg_dec4_3__1278), + .O(plm_tsi0_ts2_inv0_jog1_1_5_1214) + ); + defparam plm_tsi0_ts1_inv0_jog0_1_4.INIT = 8'h80; + LUT3_L plm_tsi0_ts1_inv0_jog0_1_4 ( + .I0(plm_tsi0_reg_dec1[1]), + .I1(plm_tsi0_reg_dec1_6104[8]), + .I2(plm_tsi0_reg_dec2_1__1246), + .LO(plm_tsi0_ts1_inv0_jog0_1_4_1219) + ); + defparam plm_tsi0_ts1_inv0_jog0_1_5.INIT = 16'h8000; + LUT4 plm_tsi0_ts1_inv0_jog0_1_5 ( + .I0(plm_tsi0_reg_dec2_8__1259), + .I1(plm_tsi0_reg_dec3_1__1247), + .I2(plm_tsi0_reg_dec3_8__1260), + .I3(plm_tsi0_reg_dec4_1__1251), + .O(plm_tsi0_ts1_inv0_jog0_1_5_1218) + ); + defparam plm_tsi0_idle_pair_0_a2_0_a2_0_a3_0_a2_9.INIT = 16'h0001; + LUT4 plm_tsi0_idle_pair_0_a2_0_a2_0_a3_0_a2_9 ( + .I0(plm_rx0_des_dat[0]), + .I1(plm_rx0_des_dat[1]), + .I2(plm_rx0_des_dat[2]), + .I3(plm_rx0_des_dat[4]), + .O(plm_tsi0_idle_pair_0_a2_0_a2_0_a3_0_a2_9_1224) + ); + defparam plm_tsi0_idle_pair_0_a2_0_a2_0_a3_0_a2_10.INIT = 16'h0001; + LUT4 plm_tsi0_idle_pair_0_a2_0_a2_0_a3_0_a2_10 ( + .I0(plm_rx0_des_dat[8]), + .I1(plm_rx0_des_dat[9]), + .I2(plm_rx0_des_dat[14]), + .I3(plm_rx0_des_dat[15]), + .O(plm_tsi0_idle_pair_0_a2_0_a2_0_a3_0_a2_10_1223) + ); + defparam plm_tsi0_idle_pair_0_a2_0_a2_0_a3_0_a2_11.INIT = 16'h0001; + LUT4 plm_tsi0_idle_pair_0_a2_0_a2_0_a3_0_a2_11 ( + .I0(plm_rx0_des_dat[6]), + .I1(plm_rx0_des_dat[7]), + .I2(plm_rx0_des_dat[12]), + .I3(plm_rx0_des_dat[13]), + .O(plm_tsi0_idle_pair_0_a2_0_a2_0_a3_0_a2_11_1222) + ); + defparam plm_tsi0_idle_pair_0_a2_0_a2_0_a3_0_a2_12.INIT = 16'h0001; + LUT4_L plm_tsi0_idle_pair_0_a2_0_a2_0_a3_0_a2_12 ( + .I0(plm_rx0_des_dat[3]), + .I1(plm_rx0_des_dat[5]), + .I2(plm_rx0_des_dat[10]), + .I3(plm_rx0_des_dat[11]), + .LO(plm_tsi0_idle_pair_0_a2_0_a2_0_a3_0_a2_12_1211) + ); + defparam plm_tsi0_com_data_jog1_1.INIT = 16'hA800; + LUT4 plm_tsi0_com_data_jog1_1 ( + .I0(plm_tsi0_reg_dec5[12]), + .I1(plm_tsi0_reg_dec7_5__1248), + .I2(plm_tsi0_reg_dec7_6_), + .I3(plm_tsi0_reg_dec8_0_), + .O(plm_tsi0_com_data_jog1_1_1220) + ); + defparam plm_tsi0_com_data_jog0.INIT = 16'h4000; + LUT4 plm_tsi0_com_data_jog0 ( + .I0(plm_tsi0_un2_com_data_jog0_1210), + .I1(plm_tsi0_com_data_jog1_2), + .I2(plm_tsi0_reg_dec7_5__1248), + .I3(plm_tsi0_reg_dec8_7_), + .O(plm_tsi0_com_data_jog0_1229) + ); + defparam plm_tsi0_idle_pair_0_a2_0_a2_0_a3_0_a2_13.INIT = 8'h80; + LUT3_L plm_tsi0_idle_pair_0_a2_0_a2_0_a3_0_a2_13 ( + .I0(plm_rx0_des_sym[0]), + .I1(plm_rx0_des_sym[1]), + .I2(plm_tsi0_idle_pair_0_a2_0_a2_0_a3_0_a2_12_1211), + .LO(plm_tsi0_idle_pair_0_a2_0_a2_0_a3_0_a2_13_1221) + ); + defparam plm_tsi0_reg_ts1_timer_0_sqmuxa.INIT = 8'h01; + LUT3 plm_tsi0_reg_ts1_timer_0_sqmuxa ( + .I0(plm_tsi0_un2_recent_ts1_1238), + .I1(plm_rx_clear_cs), + .I2(plm_tsi0_reg_capture_ts1_1242), + .O(plm_tsi0_reg_ts1_timer_0_sqmuxa_1239) + ); + defparam plm_tsi0_reg_ts2_timer_0_sqmuxa.INIT = 8'h01; + LUT3 plm_tsi0_reg_ts2_timer_0_sqmuxa ( + .I0(plm_tsi0_un2_recent_ts2_1235), + .I1(plm_rx_clear_cs), + .I2(plm_tsi0_reg_capture_ts2_1241), + .O(plm_tsi0_reg_ts2_timer_0_sqmuxa_1236) + ); + defparam plm_tsi0_ts1_inv1_jog1_1.INIT = 16'h8000; + LUT4 plm_tsi0_ts1_inv1_jog1_1 ( + .I0(plm_tsi0_reg_dec4_9__1272), + .I1(plm_tsi0_reg_dec5_2__1250), + .I2(plm_tsi0_ts1_inv1_jog1_1_4_1213), + .I3(plm_tsi0_ts1_inv1_jog1_1_5_1212), + .O(plm_tsi0_ts1_inv1_jog1_1_1225) + ); + defparam plm_tsi0_ts2_inv0_jog1_1.INIT = 16'h8000; + LUT4 plm_tsi0_ts2_inv0_jog1_1 ( + .I0(plm_tsi0_reg_dec4_10__1270), + .I1(plm_tsi0_reg_dec5_3__1279), + .I2(plm_tsi0_ts2_inv0_jog1_1_4_1215), + .I3(plm_tsi0_ts2_inv0_jog1_1_5_1214), + .O(plm_tsi0_ts2_inv0_jog1_1_1228) + ); + defparam plm_tsi0_ts2_inv1_jog1_1.INIT = 16'h8000; + LUT4 plm_tsi0_ts2_inv1_jog1_1 ( + .I0(plm_tsi0_reg_dec4_11__1268), + .I1(plm_tsi0_reg_dec5_4__1277), + .I2(plm_tsi0_ts2_inv1_jog1_1_4_1217), + .I3(plm_tsi0_ts2_inv1_jog1_1_5_1216), + .O(plm_tsi0_ts2_inv1_jog1_1_1226) + ); + defparam plm_tsi0_ts1_inv0_jog0_1.INIT = 16'h8000; + LUT4 plm_tsi0_ts1_inv0_jog0_1 ( + .I0(plm_tsi0_reg_dec4_8__1274), + .I1(plm_tsi0_reg_dec5_1__1252), + .I2(plm_tsi0_ts1_inv0_jog0_1_4_1219), + .I3(plm_tsi0_ts1_inv0_jog0_1_5_1218), + .O(plm_tsi0_ts1_inv0_jog0_1_1227) + ); + defparam plm_tsi0_un7_reg_ts1_timer_axbxc3.INIT = 16'hFE01; + LUT4 plm_tsi0_un7_reg_ts1_timer_axbxc3 ( + .I0(plm_tsi0_reg_ts1_timer[0]), + .I1(plm_tsi0_reg_ts1_timer[1]), + .I2(plm_tsi0_reg_ts1_timer[2]), + .I3(plm_tsi0_reg_ts1_timer[3]), + .O(plm_tsi0_un7_reg_ts1_timer_axbxc3_1237) + ); + defparam plm_tsi0_un7_reg_ts2_timer_axbxc3.INIT = 16'hFE01; + LUT4 plm_tsi0_un7_reg_ts2_timer_axbxc3 ( + .I0(plm_tsi0_reg_ts2_timer[0]), + .I1(plm_tsi0_reg_ts2_timer[1]), + .I2(plm_tsi0_reg_ts2_timer[2]), + .I3(plm_tsi0_reg_ts2_timer[3]), + .O(plm_tsi0_un7_reg_ts2_timer_axbxc3_1234) + ); + defparam plm_tsi0_ts1_inv0_jog1.INIT = 16'h8000; + LUT4 plm_tsi0_ts1_inv0_jog1 ( + .I0(plm_rx0_des_t1p[1]), + .I1(plm_tsi0_com_data_jog1_1_1220), + .I2(plm_tsi0_com_data_jog1_2), + .I3(plm_tsi0_ts1_inv0_jog0_1_1227), + .O(plm_tsi0_ts1_inv0_jog1_1233) + ); + defparam plm_tsi0_ts1_inv1_jog1.INIT = 16'h8000; + LUT4 plm_tsi0_ts1_inv1_jog1 ( + .I0(plm_rx0_des_t1n[1]), + .I1(plm_tsi0_com_data_jog1_1_1220), + .I2(plm_tsi0_com_data_jog1_2), + .I3(plm_tsi0_ts1_inv1_jog1_1_1225), + .O(plm_tsi0_ts1_inv1_jog1_1232) + ); + defparam plm_tsi0_ts2_inv0_jog1.INIT = 16'h8000; + LUT4 plm_tsi0_ts2_inv0_jog1 ( + .I0(plm_rx0_des_t2p[1]), + .I1(plm_tsi0_com_data_jog1_1_1220), + .I2(plm_tsi0_com_data_jog1_2), + .I3(plm_tsi0_ts2_inv0_jog1_1_1228), + .O(plm_tsi0_ts2_inv0_jog1_1231) + ); + defparam plm_tsi0_ts2_inv1_jog1.INIT = 16'h8000; + LUT4 plm_tsi0_ts2_inv1_jog1 ( + .I0(plm_rx0_des_t2n[1]), + .I1(plm_tsi0_com_data_jog1_1_1220), + .I2(plm_tsi0_com_data_jog1_2), + .I3(plm_tsi0_ts2_inv1_jog1_1_1226), + .O(plm_tsi0_ts2_inv1_jog1_1230) + ); + defparam plm_tsi0_idle_pair_0_a2_0_a2_0_a3_0_a2.INIT = 16'h8000; + LUT4 plm_tsi0_idle_pair_0_a2_0_a2_0_a3_0_a2 ( + .I0(plm_tsi0_idle_pair_0_a2_0_a2_0_a3_0_a2_9_1224), + .I1(plm_tsi0_idle_pair_0_a2_0_a2_0_a3_0_a2_10_1223), + .I2(plm_tsi0_idle_pair_0_a2_0_a2_0_a3_0_a2_11_1222), + .I3(plm_tsi0_idle_pair_0_a2_0_a2_0_a3_0_a2_13_1221), + .O(plm_tsi0_idle_pair) + ); + defparam plm_tsi0_what_it_is_reg_capture_inv_3_5906.INIT = 16'h070F; + LUT4 plm_tsi0_what_it_is_reg_capture_inv_3_5906 ( + .I0(plm_tsi0_com_data_jog0_1229), + .I1(plm_tsi0_reg_dec5_9__1273), + .I2(plm_tsi0_ts1_inv1_jog1_1232), + .I3(plm_tsi0_ts1_inv1_jog1_1_1225), + .O(plm_tsi0_reg_capture_inv_3_5906) + ); + defparam plm_tsi0_what_it_is_reg_capture_inv_3_5907.INIT = 16'h070F; + LUT4 plm_tsi0_what_it_is_reg_capture_inv_3_5907 ( + .I0(plm_tsi0_com_data_jog0_1229), + .I1(plm_tsi0_reg_dec5_11__1269), + .I2(plm_tsi0_ts2_inv1_jog1_1230), + .I3(plm_tsi0_ts2_inv1_jog1_1_1226), + .O(plm_tsi0_reg_capture_inv_3_5907) + ); + defparam plm_tsi0_what_it_is_reg_capture_ts1_3_0.INIT = 16'h007F; + LUT4 plm_tsi0_what_it_is_reg_capture_ts1_3_0 ( + .I0(plm_tsi0_com_data_jog0_1229), + .I1(plm_tsi0_reg_dec5_8__1275), + .I2(plm_tsi0_ts1_inv0_jog0_1_1227), + .I3(plm_tsi0_ts1_inv0_jog1_1233), + .O(plm_tsi0_reg_capture_ts1_3_0) + ); + defparam plm_tsi0_what_it_is_reg_capture_ts2_3_0.INIT = 16'h070F; + LUT4 plm_tsi0_what_it_is_reg_capture_ts2_3_0 ( + .I0(plm_tsi0_com_data_jog0_1229), + .I1(plm_tsi0_reg_dec5_10__1271), + .I2(plm_tsi0_ts2_inv0_jog1_1231), + .I3(plm_tsi0_ts2_inv0_jog1_1_1228), + .O(plm_tsi0_reg_capture_ts2_3_0) + ); + defparam plm_tsi0_idle_hands_reg_rx_idl_c_3_0_a2_0_a2_0_a3_0_a2.INIT = 4'h8; + LUT2_L plm_tsi0_idle_hands_reg_rx_idl_c_3_0_a2_0_a2_0_a3_0_a2 ( + .I0(plm_reg_rx_idl_1), + .I1(plm_tsi0_idle_pair), + .LO(plm_tsi0_reg_rx_idl_c_3) + ); + defparam plm_tsi0_event_regs_reg_ts2_c_3.INIT = 8'h10; + LUT3_L plm_tsi0_event_regs_reg_ts2_c_3 ( + .I0(plm_tsi0_un2_recent_ts2_1235), + .I1(plm_rx_clear_cs), + .I2(plm_tsi0_reg_capture_ts2_1241), + .LO(plm_tsi0_reg_ts2_c_3) + ); + defparam plm_tsi0_event_regs_reg_ts1_c_3.INIT = 8'h10; + LUT3_L plm_tsi0_event_regs_reg_ts1_c_3 ( + .I0(plm_tsi0_un2_recent_ts1_1238), + .I1(plm_rx_clear_cs), + .I2(plm_tsi0_reg_capture_ts1_1242), + .LO(plm_tsi0_reg_ts1_c_3) + ); + defparam plm_tsi0_what_it_is_N_11393_i.INIT = 16'h7FFF; + LUT4_L plm_tsi0_what_it_is_N_11393_i ( + .I0(plm_tsi0_reg_capture_inv_3_5906), + .I1(plm_tsi0_reg_capture_inv_3_5907), + .I2(plm_tsi0_reg_capture_ts1_3_0), + .I3(plm_tsi0_reg_capture_ts2_3_0), + .LO(plm_tsi0_N_11393_i) + ); + defparam plm_tsi0_what_it_is_N_11394_i.INIT = 4'h7; + LUT2_L plm_tsi0_what_it_is_N_11394_i ( + .I0(plm_tsi0_reg_capture_inv_3_5907), + .I1(plm_tsi0_reg_capture_ts2_3_0), + .LO(plm_tsi0_N_11394_i) + ); + defparam plm_tsi0_what_it_is_N_11395_i.INIT = 4'h7; + LUT2_L plm_tsi0_what_it_is_N_11395_i ( + .I0(plm_tsi0_reg_capture_inv_3_5906), + .I1(plm_tsi0_reg_capture_ts1_3_0), + .LO(plm_tsi0_N_11395_i) + ); + defparam plm_tsi0_what_it_is_N_11397_i.INIT = 16'hFFFE; + LUT4_L plm_tsi0_what_it_is_N_11397_i ( + .I0(plm_tsi0_ts1_inv0_jog1_1233), + .I1(plm_tsi0_ts1_inv1_jog1_1232), + .I2(plm_tsi0_ts2_inv0_jog1_1231), + .I3(plm_tsi0_ts2_inv1_jog1_1230), + .LO(plm_tsi0_N_11397_i) + ); + defparam plm_tsi0_what_it_is_N_11396_i.INIT = 4'h7; + LUT2_L plm_tsi0_what_it_is_N_11396_i ( + .I0(plm_tsi0_reg_capture_inv_3_5906), + .I1(plm_tsi0_reg_capture_inv_3_5907), + .LO(plm_tsi0_N_11396_i) + ); + defparam plm_tsi0_event_regs_reg_ts2_timer_5_f0_3_.INIT = 16'hF1F0; + LUT4_L plm_tsi0_event_regs_reg_ts2_timer_5_f0_3_ ( + .I0(plm_tsi0_un2_recent_ts2_1235), + .I1(plm_rx_clear_cs), + .I2(plm_tsi0_reg_capture_ts2_1241), + .I3(plm_tsi0_un7_reg_ts2_timer_axbxc3_1234), + .LO(plm_tsi0_reg_ts2_timer_5[3]) + ); + defparam plm_tsi0_event_regs_reg_ts2_timer_5_2_.INIT = 16'hE100; + LUT4_L plm_tsi0_event_regs_reg_ts2_timer_5_2_ ( + .I0(plm_tsi0_reg_ts2_timer[0]), + .I1(plm_tsi0_reg_ts2_timer[1]), + .I2(plm_tsi0_reg_ts2_timer[2]), + .I3(plm_tsi0_reg_ts2_timer_0_sqmuxa_1236), + .LO(plm_tsi0_reg_ts2_timer_5[2]) + ); + defparam plm_tsi0_event_regs_reg_ts2_timer_5_1_.INIT = 8'h90; + LUT3_L plm_tsi0_event_regs_reg_ts2_timer_5_1_ ( + .I0(plm_tsi0_reg_ts2_timer[0]), + .I1(plm_tsi0_reg_ts2_timer[1]), + .I2(plm_tsi0_reg_ts2_timer_0_sqmuxa_1236), + .LO(plm_tsi0_reg_ts2_timer_5[1]) + ); + defparam plm_tsi0_event_regs_reg_ts2_timer_5_0_.INIT = 4'h4; + LUT2_L plm_tsi0_event_regs_reg_ts2_timer_5_0_ ( + .I0(plm_tsi0_reg_ts2_timer[0]), + .I1(plm_tsi0_reg_ts2_timer_0_sqmuxa_1236), + .LO(plm_tsi0_reg_ts2_timer_5[0]) + ); + defparam plm_tsi0_event_regs_reg_ts1_timer_5_f0_3_.INIT = 16'hF1F0; + LUT4_L plm_tsi0_event_regs_reg_ts1_timer_5_f0_3_ ( + .I0(plm_tsi0_un2_recent_ts1_1238), + .I1(plm_rx_clear_cs), + .I2(plm_tsi0_reg_capture_ts1_1242), + .I3(plm_tsi0_un7_reg_ts1_timer_axbxc3_1237), + .LO(plm_tsi0_reg_ts1_timer_5[3]) + ); + defparam plm_tsi0_event_regs_reg_ts1_timer_5_2_.INIT = 16'hE100; + LUT4_L plm_tsi0_event_regs_reg_ts1_timer_5_2_ ( + .I0(plm_tsi0_reg_ts1_timer[0]), + .I1(plm_tsi0_reg_ts1_timer[1]), + .I2(plm_tsi0_reg_ts1_timer[2]), + .I3(plm_tsi0_reg_ts1_timer_0_sqmuxa_1239), + .LO(plm_tsi0_reg_ts1_timer_5[2]) + ); + defparam plm_tsi0_event_regs_reg_ts1_timer_5_1_.INIT = 8'h90; + LUT3_L plm_tsi0_event_regs_reg_ts1_timer_5_1_ ( + .I0(plm_tsi0_reg_ts1_timer[0]), + .I1(plm_tsi0_reg_ts1_timer[1]), + .I2(plm_tsi0_reg_ts1_timer_0_sqmuxa_1239), + .LO(plm_tsi0_reg_ts1_timer_5[1]) + ); + defparam plm_tsi0_event_regs_reg_ts1_timer_5_0_.INIT = 4'h4; + LUT2_L plm_tsi0_event_regs_reg_ts1_timer_5_0_ ( + .I0(plm_tsi0_reg_ts1_timer[0]), + .I1(plm_tsi0_reg_ts1_timer_0_sqmuxa_1239), + .LO(plm_tsi0_reg_ts1_timer_5[0]) + ); + defparam plm_tsi0_holding_regs_reg_lane_pad_3_0.INIT = 8'hD8; + LUT3_L plm_tsi0_holding_regs_reg_lane_pad_3_0 ( + .I0(plm_tsi0_reg_capture_jog_1243), + .I1(plm_tsi0_reg_dec8_6__1244), + .I2(plm_tsi0_reg_dec8_13__1240), + .LO(plm_tsi0_reg_lane_pad_3) + ); + defparam plm_tsi0_holding_regs_reg_link_pad_3_0.INIT = 8'hD8; + LUT3_L plm_tsi0_holding_regs_reg_link_pad_3_0 ( + .I0(plm_tsi0_reg_capture_jog_1243), + .I1(plm_tsi0_reg_dec8_13__1240), + .I2(plm_tsi0_reg_dec9[6]), + .LO(plm_tsi0_reg_link_pad_3) + ); + defparam plm_tsi0_holding_regs_reg_lane_num_3_7_.INIT = 16'h596A; + LUT4_L plm_tsi0_holding_regs_reg_lane_num_3_7_ ( + .I0(plm_tsi0_reg_capture_inv_1280), + .I1(plm_tsi0_reg_capture_jog_1243), + .I2(plm_tsi0_reg_dly8[7]), + .I3(plm_tsi0_reg_dly8[15]), + .LO(plm_tsi0_reg_lane_num_3[7]) + ); + defparam plm_tsi0_holding_regs_reg_lane_num_3_6_.INIT = 16'h596A; + LUT4_L plm_tsi0_holding_regs_reg_lane_num_3_6_ ( + .I0(plm_tsi0_reg_capture_inv_1280), + .I1(plm_tsi0_reg_capture_jog_1243), + .I2(plm_tsi0_reg_dly8[6]), + .I3(plm_tsi0_reg_dly8[14]), + .LO(plm_tsi0_reg_lane_num_3[6]) + ); + defparam plm_tsi0_holding_regs_reg_lane_num_3_5_.INIT = 16'h596A; + LUT4_L plm_tsi0_holding_regs_reg_lane_num_3_5_ ( + .I0(plm_tsi0_reg_capture_inv_1280), + .I1(plm_tsi0_reg_capture_jog_1243), + .I2(plm_tsi0_reg_dly8[5]), + .I3(plm_tsi0_reg_dly8[13]), + .LO(plm_tsi0_reg_lane_num_3[5]) + ); + defparam plm_tsi0_holding_regs_reg_lane_num_3_4_.INIT = 16'h596A; + LUT4_L plm_tsi0_holding_regs_reg_lane_num_3_4_ ( + .I0(plm_tsi0_reg_capture_inv_1280), + .I1(plm_tsi0_reg_capture_jog_1243), + .I2(plm_tsi0_reg_dly8[4]), + .I3(plm_tsi0_reg_dly8[12]), + .LO(plm_tsi0_reg_lane_num_3[4]) + ); + defparam plm_tsi0_holding_regs_reg_lane_num_3_3_.INIT = 16'h596A; + LUT4_L plm_tsi0_holding_regs_reg_lane_num_3_3_ ( + .I0(plm_tsi0_reg_capture_inv_1280), + .I1(plm_tsi0_reg_capture_jog_1243), + .I2(plm_tsi0_reg_dly8[3]), + .I3(plm_tsi0_reg_dly8[11]), + .LO(plm_tsi0_reg_lane_num_3[3]) + ); + defparam plm_tsi0_holding_regs_reg_lane_num_3_2_.INIT = 16'h596A; + LUT4_L plm_tsi0_holding_regs_reg_lane_num_3_2_ ( + .I0(plm_tsi0_reg_capture_inv_1280), + .I1(plm_tsi0_reg_capture_jog_1243), + .I2(plm_tsi0_reg_dly8[2]), + .I3(plm_tsi0_reg_dly8[10]), + .LO(plm_tsi0_reg_lane_num_3[2]) + ); + defparam plm_tsi0_holding_regs_reg_lane_num_3_1_.INIT = 16'h596A; + LUT4_L plm_tsi0_holding_regs_reg_lane_num_3_1_ ( + .I0(plm_tsi0_reg_capture_inv_1280), + .I1(plm_tsi0_reg_capture_jog_1243), + .I2(plm_tsi0_reg_dly8[1]), + .I3(plm_tsi0_reg_dly8[9]), + .LO(plm_tsi0_reg_lane_num_3[1]) + ); + defparam plm_tsi0_holding_regs_reg_lane_num_3_0_.INIT = 16'h596A; + LUT4_L plm_tsi0_holding_regs_reg_lane_num_3_0_ ( + .I0(plm_tsi0_reg_capture_inv_1280), + .I1(plm_tsi0_reg_capture_jog_1243), + .I2(plm_tsi0_reg_dly8[0]), + .I3(plm_tsi0_reg_dly8[8]), + .LO(plm_tsi0_reg_lane_num_3[0]) + ); + defparam plm_tsi0_holding_regs_reg_link_num_3_7_.INIT = 16'h596A; + LUT4_L plm_tsi0_holding_regs_reg_link_num_3_7_ ( + .I0(plm_tsi0_reg_capture_inv_1280), + .I1(plm_tsi0_reg_capture_jog_1243), + .I2(plm_tsi0_reg_dly8[15]), + .I3(plm_tsi0_reg_dly9[7]), + .LO(plm_tsi0_reg_link_num_3[7]) + ); + defparam plm_tsi0_holding_regs_reg_link_num_3_6_.INIT = 16'h596A; + LUT4_L plm_tsi0_holding_regs_reg_link_num_3_6_ ( + .I0(plm_tsi0_reg_capture_inv_1280), + .I1(plm_tsi0_reg_capture_jog_1243), + .I2(plm_tsi0_reg_dly8[14]), + .I3(plm_tsi0_reg_dly9[6]), + .LO(plm_tsi0_reg_link_num_3[6]) + ); + defparam plm_tsi0_holding_regs_reg_link_num_3_5_.INIT = 16'h596A; + LUT4_L plm_tsi0_holding_regs_reg_link_num_3_5_ ( + .I0(plm_tsi0_reg_capture_inv_1280), + .I1(plm_tsi0_reg_capture_jog_1243), + .I2(plm_tsi0_reg_dly8[13]), + .I3(plm_tsi0_reg_dly9[5]), + .LO(plm_tsi0_reg_link_num_3[5]) + ); + defparam plm_tsi0_holding_regs_reg_link_num_3_4_.INIT = 16'h596A; + LUT4_L plm_tsi0_holding_regs_reg_link_num_3_4_ ( + .I0(plm_tsi0_reg_capture_inv_1280), + .I1(plm_tsi0_reg_capture_jog_1243), + .I2(plm_tsi0_reg_dly8[12]), + .I3(plm_tsi0_reg_dly9[4]), + .LO(plm_tsi0_reg_link_num_3[4]) + ); + defparam plm_tsi0_holding_regs_reg_link_num_3_3_.INIT = 16'h596A; + LUT4_L plm_tsi0_holding_regs_reg_link_num_3_3_ ( + .I0(plm_tsi0_reg_capture_inv_1280), + .I1(plm_tsi0_reg_capture_jog_1243), + .I2(plm_tsi0_reg_dly8[11]), + .I3(plm_tsi0_reg_dly9[3]), + .LO(plm_tsi0_reg_link_num_3[3]) + ); + defparam plm_tsi0_holding_regs_reg_link_num_3_2_.INIT = 16'h596A; + LUT4_L plm_tsi0_holding_regs_reg_link_num_3_2_ ( + .I0(plm_tsi0_reg_capture_inv_1280), + .I1(plm_tsi0_reg_capture_jog_1243), + .I2(plm_tsi0_reg_dly8[10]), + .I3(plm_tsi0_reg_dly9[2]), + .LO(plm_tsi0_reg_link_num_3[2]) + ); + defparam plm_tsi0_holding_regs_reg_link_num_3_1_.INIT = 16'h596A; + LUT4_L plm_tsi0_holding_regs_reg_link_num_3_1_ ( + .I0(plm_tsi0_reg_capture_inv_1280), + .I1(plm_tsi0_reg_capture_jog_1243), + .I2(plm_tsi0_reg_dly8[9]), + .I3(plm_tsi0_reg_dly9[1]), + .LO(plm_tsi0_reg_link_num_3[1]) + ); + defparam plm_tsi0_holding_regs_reg_link_num_3_0_.INIT = 16'h596A; + LUT4_L plm_tsi0_holding_regs_reg_link_num_3_0_ ( + .I0(plm_tsi0_reg_capture_inv_1280), + .I1(plm_tsi0_reg_capture_jog_1243), + .I2(plm_tsi0_reg_dly8[8]), + .I3(plm_tsi0_reg_dly9[0]), + .LO(plm_tsi0_reg_link_num_3[0]) + ); + defparam plm_tsi0_holding_regs_reg_linkctrl_3_3_.INIT = 16'h636C; + LUT4_L plm_tsi0_holding_regs_reg_linkctrl_3_3_ ( + .I0(plm_tsi0_do[11]), + .I1(plm_tsi0_reg_capture_inv_1280), + .I2(plm_tsi0_reg_capture_jog_1243), + .I3(plm_tsi0_reg_dly7[3]), + .LO(plm_tsi0_reg_linkctrl_3_3_) + ); + defparam plm_tsi0_holding_regs_reg_linkctrl_3_0_.INIT = 16'h636C; + LUT4_L plm_tsi0_holding_regs_reg_linkctrl_3_0_ ( + .I0(plm_tsi0_do[8]), + .I1(plm_tsi0_reg_capture_inv_1280), + .I2(plm_tsi0_reg_capture_jog_1243), + .I3(plm_tsi0_reg_dly7[0]), + .LO(plm_tsi0_reg_linkctrl_3_0_) + ); + FD plm_tsi0_reg_dec8_0_DOUT_0_ ( + .C(mgt_clk), + .D(plm_tsi0_reg_dec8_0_N_6), + .Q(plm_tsi0_reg_dec8_0_DOUT[0]) + ); + FD plm_tsi0_reg_dec6_DOUT_0_ ( + .C(mgt_clk), + .D(plm_tsi0_reg_dec6_tmp_d_array_0[0]), + .Q(plm_tsi0_reg_dec6_DOUT[0]) + ); + FD plm_tsi0_reg_dec1_2_DOUT_0_ ( + .C(mgt_clk), + .D(plm_tsi0_reg_dec1_2_N_6), + .Q(plm_tsi0_reg_dec1_2_DOUT[0]) + ); + FD plm_tsi0_reg_dec1_1_DOUT_0_ ( + .C(mgt_clk), + .D(plm_tsi0_reg_dec1_1_N_6), + .Q(plm_tsi0_reg_dec1_1_DOUT[0]) + ); + FD plm_tsi0_reg_dec1_0_DOUT_0_ ( + .C(mgt_clk), + .D(plm_tsi0_reg_dec1_0_N_6), + .Q(plm_tsi0_reg_dec1_0_DOUT[0]) + ); + FD plm_tsi0_reg_dec1_DOUT_0_ ( + .C(mgt_clk), + .D(plm_tsi0_reg_dec1_N_6), + .Q(plm_tsi0_reg_dec1_DOUT[0]) + ); + FD plm_tsi0_reg_dec8_DOUT_0_ ( + .C(mgt_clk), + .D(plm_tsi0_reg_dec8_tmp_d_array_0[0]), + .Q(plm_tsi0_reg_dec8_DOUT[0]) + ); + FD plm_tsi0_reg_dec7_0_DOUT_0_ ( + .C(mgt_clk), + .D(plm_tsi0_reg_dec7_0_N_6), + .Q(plm_tsi0_reg_dec7_0_DOUT[0]) + ); + FD plm_tsi0_reg_dec7_DOUT_0_ ( + .C(mgt_clk), + .D(plm_tsi0_reg_dec7_tmp_d_array_0[0]), + .Q(plm_tsi0_reg_dec7_DOUT[0]) + ); + FD plm_tsi0_reg_dec5_DOUT_0_ ( + .C(mgt_clk), + .D(plm_tsi0_reg_dec5_tmp_d_array_0[0]), + .Q(plm_tsi0_reg_dec5_DOUT[0]) + ); + FDC plm_tsi0_reg_dec8_13_ ( + .C(mgt_clk), + .D(plm_tsi0_reg_dec7_13_), + .Q(plm_tsi0_reg_dec8_13__1240), + .CLR(plm_rst) + ); + FDC plm_tsi0_reg_dec9_6_ ( + .C(mgt_clk), + .D(plm_tsi0_reg_dec8_6__1244), + .Q(plm_tsi0_reg_dec9[6]), + .CLR(plm_rst) + ); + FDC plm_tsi0_reg_rx_idl_c ( + .C(mgt_clk), + .D(plm_tsi0_reg_rx_idl_c_3), + .Q(plm_rx0_idl_c), + .CLR(plm_rst) + ); + FDC plm_tsi0_reg_rx_idl_1 ( + .C(mgt_clk), + .D(plm_tsi0_idle_pair), + .Q(plm_reg_rx_idl_1), + .CLR(plm_rst) + ); + FDC plm_tsi0_reg_ts2_c ( + .C(mgt_clk), + .D(plm_tsi0_reg_ts2_c_3), + .Q(plm_rx0_ts2_c), + .CLR(plm_rst) + ); + FDC plm_tsi0_reg_ts1_c ( + .C(mgt_clk), + .D(plm_tsi0_reg_ts1_c_3), + .Q(plm_rx0_ts1_c), + .CLR(plm_rst) + ); + FDC plm_tsi0_reg_ts2_1 ( + .C(mgt_clk), + .D(plm_tsi0_reg_capture_ts2_1241), + .Q(plm_reg_ts2_1), + .CLR(plm_rst) + ); + FDC plm_tsi0_reg_ts1_1 ( + .C(mgt_clk), + .D(plm_tsi0_reg_capture_ts1_1242), + .Q(plm_reg_ts1_1), + .CLR(plm_rst) + ); + FDC plm_tsi0_reg_capture_now ( + .C(mgt_clk), + .D(plm_tsi0_N_11393_i), + .Q(plm_tsi0_reg_capture_now_1281), + .CLR(plm_rst) + ); + FDC plm_tsi0_reg_capture_ts2 ( + .C(mgt_clk), + .D(plm_tsi0_N_11394_i), + .Q(plm_tsi0_reg_capture_ts2_1241), + .CLR(plm_rst) + ); + FDC plm_tsi0_reg_capture_ts1 ( + .C(mgt_clk), + .D(plm_tsi0_N_11395_i), + .Q(plm_tsi0_reg_capture_ts1_1242), + .CLR(plm_rst) + ); + FDC plm_tsi0_reg_capture_jog ( + .C(mgt_clk), + .D(plm_tsi0_N_11397_i), + .Q(plm_tsi0_reg_capture_jog_1243), + .CLR(plm_rst) + ); + FDC plm_tsi0_reg_capture_inv ( + .C(mgt_clk), + .D(plm_tsi0_N_11396_i), + .Q(plm_tsi0_reg_capture_inv_1280), + .CLR(plm_rst) + ); + FDC plm_tsi0_reg_dly8_6_ ( + .C(mgt_clk), + .D(plm_tsi0_reg_dly7[6]), + .Q(plm_tsi0_reg_dly8[6]), + .CLR(plm_rst) + ); + FDC plm_tsi0_reg_dly8_5_ ( + .C(mgt_clk), + .D(plm_tsi0_reg_dly7[5]), + .Q(plm_tsi0_reg_dly8[5]), + .CLR(plm_rst) + ); + FDC plm_tsi0_reg_dly8_4_ ( + .C(mgt_clk), + .D(plm_tsi0_reg_dly7[4]), + .Q(plm_tsi0_reg_dly8[4]), + .CLR(plm_rst) + ); + FDC plm_tsi0_reg_dly8_3_ ( + .C(mgt_clk), + .D(plm_tsi0_reg_dly7[3]), + .Q(plm_tsi0_reg_dly8[3]), + .CLR(plm_rst) + ); + FDC plm_tsi0_reg_dly8_2_ ( + .C(mgt_clk), + .D(plm_tsi0_reg_dly7[2]), + .Q(plm_tsi0_reg_dly8[2]), + .CLR(plm_rst) + ); + FDC plm_tsi0_reg_dly8_1_ ( + .C(mgt_clk), + .D(plm_tsi0_reg_dly7[1]), + .Q(plm_tsi0_reg_dly8[1]), + .CLR(plm_rst) + ); + FDC plm_tsi0_reg_dly8_0_ ( + .C(mgt_clk), + .D(plm_tsi0_reg_dly7[0]), + .Q(plm_tsi0_reg_dly8[0]), + .CLR(plm_rst) + ); + FDC plm_tsi0_reg_ts2_timer_3_ ( + .C(mgt_clk), + .D(plm_tsi0_reg_ts2_timer_5[3]), + .Q(plm_tsi0_reg_ts2_timer[3]), + .CLR(plm_rst) + ); + FDC plm_tsi0_reg_ts2_timer_2_ ( + .C(mgt_clk), + .D(plm_tsi0_reg_ts2_timer_5[2]), + .Q(plm_tsi0_reg_ts2_timer[2]), + .CLR(plm_rst) + ); + FDC plm_tsi0_reg_ts2_timer_1_ ( + .C(mgt_clk), + .D(plm_tsi0_reg_ts2_timer_5[1]), + .Q(plm_tsi0_reg_ts2_timer[1]), + .CLR(plm_rst) + ); + FDC plm_tsi0_reg_ts2_timer_0_ ( + .C(mgt_clk), + .D(plm_tsi0_reg_ts2_timer_5[0]), + .Q(plm_tsi0_reg_ts2_timer[0]), + .CLR(plm_rst) + ); + FDC plm_tsi0_reg_ts1_timer_3_ ( + .C(mgt_clk), + .D(plm_tsi0_reg_ts1_timer_5[3]), + .Q(plm_tsi0_reg_ts1_timer[3]), + .CLR(plm_rst) + ); + FDC plm_tsi0_reg_ts1_timer_2_ ( + .C(mgt_clk), + .D(plm_tsi0_reg_ts1_timer_5[2]), + .Q(plm_tsi0_reg_ts1_timer[2]), + .CLR(plm_rst) + ); + FDC plm_tsi0_reg_ts1_timer_1_ ( + .C(mgt_clk), + .D(plm_tsi0_reg_ts1_timer_5[1]), + .Q(plm_tsi0_reg_ts1_timer[1]), + .CLR(plm_rst) + ); + FDC plm_tsi0_reg_ts1_timer_0_ ( + .C(mgt_clk), + .D(plm_tsi0_reg_ts1_timer_5[0]), + .Q(plm_tsi0_reg_ts1_timer[0]), + .CLR(plm_rst) + ); + FDC plm_tsi0_reg_dec2_4_ ( + .C(mgt_clk), + .D(plm_tsi0_reg_dec1[4]), + .Q(plm_tsi0_reg_dec2_4__1261), + .CLR(plm_rst) + ); + FDC plm_tsi0_reg_dec2_3_ ( + .C(mgt_clk), + .D(plm_tsi0_reg_dec1[3]), + .Q(plm_tsi0_reg_dec2_3__1263), + .CLR(plm_rst) + ); + FDC plm_tsi0_reg_dec2_2_ ( + .C(mgt_clk), + .D(plm_tsi0_reg_dec1[2]), + .Q(plm_tsi0_reg_dec2_2__1265), + .CLR(plm_rst) + ); + FDC plm_tsi0_reg_dec2_1_ ( + .C(mgt_clk), + .D(plm_tsi0_reg_dec1[1]), + .Q(plm_tsi0_reg_dec2_1__1246), + .CLR(plm_rst) + ); + FDC plm_tsi0_reg_dly8_15_ ( + .C(mgt_clk), + .D(plm_tsi0_reg_dly7[15]), + .Q(plm_tsi0_reg_dly8[15]), + .CLR(plm_rst) + ); + FDC plm_tsi0_reg_dly8_14_ ( + .C(mgt_clk), + .D(plm_tsi0_reg_dly7[14]), + .Q(plm_tsi0_reg_dly8[14]), + .CLR(plm_rst) + ); + FDC plm_tsi0_reg_dly8_13_ ( + .C(mgt_clk), + .D(plm_tsi0_reg_dly7[13]), + .Q(plm_tsi0_reg_dly8[13]), + .CLR(plm_rst) + ); + FDC plm_tsi0_reg_dly8_12_ ( + .C(mgt_clk), + .D(plm_tsi0_reg_dly7[12]), + .Q(plm_tsi0_reg_dly8[12]), + .CLR(plm_rst) + ); + FDC plm_tsi0_reg_dly8_11_ ( + .C(mgt_clk), + .D(plm_tsi0_reg_dly7[11]), + .Q(plm_tsi0_reg_dly8[11]), + .CLR(plm_rst) + ); + FDC plm_tsi0_reg_dly8_10_ ( + .C(mgt_clk), + .D(plm_tsi0_reg_dly7[10]), + .Q(plm_tsi0_reg_dly8[10]), + .CLR(plm_rst) + ); + FDC plm_tsi0_reg_dly8_9_ ( + .C(mgt_clk), + .D(plm_tsi0_reg_dly7[9]), + .Q(plm_tsi0_reg_dly8[9]), + .CLR(plm_rst) + ); + FDC plm_tsi0_reg_dly8_8_ ( + .C(mgt_clk), + .D(plm_tsi0_reg_dly7[8]), + .Q(plm_tsi0_reg_dly8[8]), + .CLR(plm_rst) + ); + FDC plm_tsi0_reg_dly8_7_ ( + .C(mgt_clk), + .D(plm_tsi0_reg_dly7[7]), + .Q(plm_tsi0_reg_dly8[7]), + .CLR(plm_rst) + ); + FDC plm_tsi0_reg_dec8_6_ ( + .C(mgt_clk), + .D(plm_tsi0_reg_dec7_6_), + .Q(plm_tsi0_reg_dec8_6__1244), + .CLR(plm_rst) + ); + FDC plm_tsi0_reg_dec8_5_ ( + .C(mgt_clk), + .D(plm_tsi0_reg_dec7_5__1248), + .Q(plm_tsi0_reg_dec8_5__1245), + .CLR(plm_rst) + ); + FDC plm_tsi0_reg_dec2_11_ ( + .C(mgt_clk), + .D(plm_tsi0_reg_dec1_6104[11]), + .Q(plm_tsi0_reg_dec2_11__1253), + .CLR(plm_rst) + ); + FDC plm_tsi0_reg_dec2_10_ ( + .C(mgt_clk), + .D(plm_tsi0_reg_dec1_6104[10]), + .Q(plm_tsi0_reg_dec2_10__1255), + .CLR(plm_rst) + ); + FDC plm_tsi0_reg_dec2_9_ ( + .C(mgt_clk), + .D(plm_tsi0_reg_dec1_6104[9]), + .Q(plm_tsi0_reg_dec2_9__1257), + .CLR(plm_rst) + ); + FDC plm_tsi0_reg_dec2_8_ ( + .C(mgt_clk), + .D(plm_tsi0_reg_dec1_6104[8]), + .Q(plm_tsi0_reg_dec2_8__1259), + .CLR(plm_rst) + ); + FDC plm_tsi0_reg_dec1_11_ ( + .C(mgt_clk), + .D(plm_rx0_des_t2n[1]), + .Q(plm_tsi0_reg_dec1_6104[11]), + .CLR(plm_rst) + ); + FDC plm_tsi0_reg_dec1_10_ ( + .C(mgt_clk), + .D(plm_rx0_des_t2p[1]), + .Q(plm_tsi0_reg_dec1_6104[10]), + .CLR(plm_rst) + ); + FDC plm_tsi0_reg_dec1_9_ ( + .C(mgt_clk), + .D(plm_rx0_des_t1n[1]), + .Q(plm_tsi0_reg_dec1_6104[9]), + .CLR(plm_rst) + ); + FDC plm_tsi0_reg_dec1_8_ ( + .C(mgt_clk), + .D(plm_rx0_des_t1p[1]), + .Q(plm_tsi0_reg_dec1_6104[8]), + .CLR(plm_rst) + ); + FDC plm_tsi0_reg_dec6_12_ ( + .C(mgt_clk), + .D(plm_tsi0_reg_dec5[12]), + .Q(plm_tsi0_reg_dec6_6105[12]), + .CLR(plm_rst) + ); + FDC plm_tsi0_reg_dec4_11_ ( + .C(mgt_clk), + .D(plm_tsi0_reg_dec3_11__1254), + .Q(plm_tsi0_reg_dec4_11__1268), + .CLR(plm_rst) + ); + FDC plm_tsi0_reg_dec4_10_ ( + .C(mgt_clk), + .D(plm_tsi0_reg_dec3_10__1256), + .Q(plm_tsi0_reg_dec4_10__1270), + .CLR(plm_rst) + ); + FDC plm_tsi0_reg_dec4_9_ ( + .C(mgt_clk), + .D(plm_tsi0_reg_dec3_9__1258), + .Q(plm_tsi0_reg_dec4_9__1272), + .CLR(plm_rst) + ); + FDC plm_tsi0_reg_dec4_8_ ( + .C(mgt_clk), + .D(plm_tsi0_reg_dec3_8__1260), + .Q(plm_tsi0_reg_dec4_8__1274), + .CLR(plm_rst) + ); + FDC plm_tsi0_reg_dec4_4_ ( + .C(mgt_clk), + .D(plm_tsi0_reg_dec3_4__1262), + .Q(plm_tsi0_reg_dec4_4__1276), + .CLR(plm_rst) + ); + FDC plm_tsi0_reg_dec4_3_ ( + .C(mgt_clk), + .D(plm_tsi0_reg_dec3_3__1264), + .Q(plm_tsi0_reg_dec4_3__1278), + .CLR(plm_rst) + ); + FDC plm_tsi0_reg_dec4_2_ ( + .C(mgt_clk), + .D(plm_tsi0_reg_dec3_2__1266), + .Q(plm_tsi0_reg_dec4_2__1249), + .CLR(plm_rst) + ); + FDC plm_tsi0_reg_dec4_1_ ( + .C(mgt_clk), + .D(plm_tsi0_reg_dec3_1__1247), + .Q(plm_tsi0_reg_dec4_1__1251), + .CLR(plm_rst) + ); + FDC plm_tsi0_reg_dec3_1_ ( + .C(mgt_clk), + .D(plm_tsi0_reg_dec2_1__1246), + .Q(plm_tsi0_reg_dec3_1__1247), + .CLR(plm_rst) + ); + FDC plm_tsi0_reg_dec7_5_ ( + .C(mgt_clk), + .D(plm_tsi0_reg_dec6[5]), + .Q(plm_tsi0_reg_dec7_5__1248), + .CLR(plm_rst) + ); + FDC plm_tsi0_reg_dly9_7_ ( + .C(mgt_clk), + .D(plm_tsi0_reg_dly8[7]), + .Q(plm_tsi0_reg_dly9[7]), + .CLR(plm_rst) + ); + FDC plm_tsi0_reg_dly9_6_ ( + .C(mgt_clk), + .D(plm_tsi0_reg_dly8[6]), + .Q(plm_tsi0_reg_dly9[6]), + .CLR(plm_rst) + ); + FDC plm_tsi0_reg_dly9_5_ ( + .C(mgt_clk), + .D(plm_tsi0_reg_dly8[5]), + .Q(plm_tsi0_reg_dly9[5]), + .CLR(plm_rst) + ); + FDC plm_tsi0_reg_dly9_4_ ( + .C(mgt_clk), + .D(plm_tsi0_reg_dly8[4]), + .Q(plm_tsi0_reg_dly9[4]), + .CLR(plm_rst) + ); + FDC plm_tsi0_reg_dly9_3_ ( + .C(mgt_clk), + .D(plm_tsi0_reg_dly8[3]), + .Q(plm_tsi0_reg_dly9[3]), + .CLR(plm_rst) + ); + FDC plm_tsi0_reg_dly9_2_ ( + .C(mgt_clk), + .D(plm_tsi0_reg_dly8[2]), + .Q(plm_tsi0_reg_dly9[2]), + .CLR(plm_rst) + ); + FDC plm_tsi0_reg_dly9_1_ ( + .C(mgt_clk), + .D(plm_tsi0_reg_dly8[1]), + .Q(plm_tsi0_reg_dly9[1]), + .CLR(plm_rst) + ); + FDC plm_tsi0_reg_dly9_0_ ( + .C(mgt_clk), + .D(plm_tsi0_reg_dly8[0]), + .Q(plm_tsi0_reg_dly9[0]), + .CLR(plm_rst) + ); + FDC plm_tsi0_reg_dec5_2_ ( + .C(mgt_clk), + .D(plm_tsi0_reg_dec4_2__1249), + .Q(plm_tsi0_reg_dec5_2__1250), + .CLR(plm_rst) + ); + FDC plm_tsi0_reg_dec5_1_ ( + .C(mgt_clk), + .D(plm_tsi0_reg_dec4_1__1251), + .Q(plm_tsi0_reg_dec5_1__1252), + .CLR(plm_rst) + ); + FDC plm_tsi0_reg_dec3_11_ ( + .C(mgt_clk), + .D(plm_tsi0_reg_dec2_11__1253), + .Q(plm_tsi0_reg_dec3_11__1254), + .CLR(plm_rst) + ); + FDC plm_tsi0_reg_dec3_10_ ( + .C(mgt_clk), + .D(plm_tsi0_reg_dec2_10__1255), + .Q(plm_tsi0_reg_dec3_10__1256), + .CLR(plm_rst) + ); + FDC plm_tsi0_reg_dec3_9_ ( + .C(mgt_clk), + .D(plm_tsi0_reg_dec2_9__1257), + .Q(plm_tsi0_reg_dec3_9__1258), + .CLR(plm_rst) + ); + FDC plm_tsi0_reg_dec3_8_ ( + .C(mgt_clk), + .D(plm_tsi0_reg_dec2_8__1259), + .Q(plm_tsi0_reg_dec3_8__1260), + .CLR(plm_rst) + ); + FDC plm_tsi0_reg_dec3_4_ ( + .C(mgt_clk), + .D(plm_tsi0_reg_dec2_4__1261), + .Q(plm_tsi0_reg_dec3_4__1262), + .CLR(plm_rst) + ); + FDC plm_tsi0_reg_dec3_3_ ( + .C(mgt_clk), + .D(plm_tsi0_reg_dec2_3__1263), + .Q(plm_tsi0_reg_dec3_3__1264), + .CLR(plm_rst) + ); + FDC plm_tsi0_reg_dec3_2_ ( + .C(mgt_clk), + .D(plm_tsi0_reg_dec2_2__1265), + .Q(plm_tsi0_reg_dec3_2__1266), + .CLR(plm_rst) + ); + FDC plm_tsi0_reg_dly7_1_ ( + .C(mgt_clk), + .D(plm_tsi0_do[1]), + .Q(plm_tsi0_reg_dly7[1]), + .CLR(plm_rst) + ); + FDC plm_tsi0_reg_dly7_0_ ( + .C(mgt_clk), + .D(plm_tsi0_do[0]), + .Q(plm_tsi0_reg_dly7[0]), + .CLR(plm_rst) + ); + FDC plm_tsi0_reg_dec7_12_ ( + .C(mgt_clk), + .D(plm_tsi0_reg_dec6_6105[12]), + .Q(plm_tsi0_reg_dec7_12__1267), + .CLR(plm_rst) + ); + FDC plm_tsi0_reg_dec5_11_ ( + .C(mgt_clk), + .D(plm_tsi0_reg_dec4_11__1268), + .Q(plm_tsi0_reg_dec5_11__1269), + .CLR(plm_rst) + ); + FDC plm_tsi0_reg_dec5_10_ ( + .C(mgt_clk), + .D(plm_tsi0_reg_dec4_10__1270), + .Q(plm_tsi0_reg_dec5_10__1271), + .CLR(plm_rst) + ); + FDC plm_tsi0_reg_dec5_9_ ( + .C(mgt_clk), + .D(plm_tsi0_reg_dec4_9__1272), + .Q(plm_tsi0_reg_dec5_9__1273), + .CLR(plm_rst) + ); + FDC plm_tsi0_reg_dec5_8_ ( + .C(mgt_clk), + .D(plm_tsi0_reg_dec4_8__1274), + .Q(plm_tsi0_reg_dec5_8__1275), + .CLR(plm_rst) + ); + FDC plm_tsi0_reg_dec5_4_ ( + .C(mgt_clk), + .D(plm_tsi0_reg_dec4_4__1276), + .Q(plm_tsi0_reg_dec5_4__1277), + .CLR(plm_rst) + ); + FDC plm_tsi0_reg_dec5_3_ ( + .C(mgt_clk), + .D(plm_tsi0_reg_dec4_3__1278), + .Q(plm_tsi0_reg_dec5_3__1279), + .CLR(plm_rst) + ); + FDC plm_tsi0_reg_dly7_15_ ( + .C(mgt_clk), + .D(plm_tsi0_do[15]), + .Q(plm_tsi0_reg_dly7[15]), + .CLR(plm_rst) + ); + FDC plm_tsi0_reg_dly7_14_ ( + .C(mgt_clk), + .D(plm_tsi0_do[14]), + .Q(plm_tsi0_reg_dly7[14]), + .CLR(plm_rst) + ); + FDC plm_tsi0_reg_dly7_13_ ( + .C(mgt_clk), + .D(plm_tsi0_do[13]), + .Q(plm_tsi0_reg_dly7[13]), + .CLR(plm_rst) + ); + FDC plm_tsi0_reg_dly7_12_ ( + .C(mgt_clk), + .D(plm_tsi0_do[12]), + .Q(plm_tsi0_reg_dly7[12]), + .CLR(plm_rst) + ); + FDC plm_tsi0_reg_dly7_11_ ( + .C(mgt_clk), + .D(plm_tsi0_do[11]), + .Q(plm_tsi0_reg_dly7[11]), + .CLR(plm_rst) + ); + FDC plm_tsi0_reg_dly7_10_ ( + .C(mgt_clk), + .D(plm_tsi0_do[10]), + .Q(plm_tsi0_reg_dly7[10]), + .CLR(plm_rst) + ); + FDC plm_tsi0_reg_dly7_9_ ( + .C(mgt_clk), + .D(plm_tsi0_do[9]), + .Q(plm_tsi0_reg_dly7[9]), + .CLR(plm_rst) + ); + FDC plm_tsi0_reg_dly7_8_ ( + .C(mgt_clk), + .D(plm_tsi0_do[8]), + .Q(plm_tsi0_reg_dly7[8]), + .CLR(plm_rst) + ); + FDC plm_tsi0_reg_dly7_7_ ( + .C(mgt_clk), + .D(plm_tsi0_do[7]), + .Q(plm_tsi0_reg_dly7[7]), + .CLR(plm_rst) + ); + FDC plm_tsi0_reg_dly7_6_ ( + .C(mgt_clk), + .D(plm_tsi0_do[6]), + .Q(plm_tsi0_reg_dly7[6]), + .CLR(plm_rst) + ); + FDC plm_tsi0_reg_dly7_5_ ( + .C(mgt_clk), + .D(plm_tsi0_do[5]), + .Q(plm_tsi0_reg_dly7[5]), + .CLR(plm_rst) + ); + FDC plm_tsi0_reg_dly7_4_ ( + .C(mgt_clk), + .D(plm_tsi0_do[4]), + .Q(plm_tsi0_reg_dly7[4]), + .CLR(plm_rst) + ); + FDC plm_tsi0_reg_dly7_3_ ( + .C(mgt_clk), + .D(plm_tsi0_do[3]), + .Q(plm_tsi0_reg_dly7[3]), + .CLR(plm_rst) + ); + FDC plm_tsi0_reg_dly7_2_ ( + .C(mgt_clk), + .D(plm_tsi0_do[2]), + .Q(plm_tsi0_reg_dly7[2]), + .CLR(plm_rst) + ); + FDCE plm_tsi0_reg_inverted ( + .CE(plm_tsi0_reg_capture_now_1281), + .C(mgt_clk), + .D(plm_tsi0_reg_capture_inv_1280), + .Q(plm_rx0_inverted), + .CLR(plm_rst) + ); + FDCE plm_tsi0_reg_lane_pad ( + .CE(plm_tsi0_reg_capture_now_1281), + .C(mgt_clk), + .D(plm_tsi0_reg_lane_pad_3), + .Q(plm_rx0_lane_pad), + .CLR(plm_rst) + ); + FDCE plm_tsi0_reg_link_pad ( + .CE(plm_tsi0_reg_capture_now_1281), + .C(mgt_clk), + .D(plm_tsi0_reg_link_pad_3), + .Q(plm_rx0_link_pad), + .CLR(plm_rst) + ); + FDCE plm_tsi0_reg_lane_num_7_ ( + .CE(plm_tsi0_reg_capture_now_1281), + .C(mgt_clk), + .D(plm_tsi0_reg_lane_num_3[7]), + .Q(plm_rx0_lane_num[7]), + .CLR(plm_rst) + ); + FDCE plm_tsi0_reg_lane_num_6_ ( + .CE(plm_tsi0_reg_capture_now_1281), + .C(mgt_clk), + .D(plm_tsi0_reg_lane_num_3[6]), + .Q(plm_rx0_lane_num[6]), + .CLR(plm_rst) + ); + FDCE plm_tsi0_reg_lane_num_5_ ( + .CE(plm_tsi0_reg_capture_now_1281), + .C(mgt_clk), + .D(plm_tsi0_reg_lane_num_3[5]), + .Q(plm_rx0_lane_num[5]), + .CLR(plm_rst) + ); + FDCE plm_tsi0_reg_lane_num_4_ ( + .CE(plm_tsi0_reg_capture_now_1281), + .C(mgt_clk), + .D(plm_tsi0_reg_lane_num_3[4]), + .Q(plm_rx0_lane_num[4]), + .CLR(plm_rst) + ); + FDCE plm_tsi0_reg_lane_num_3_ ( + .CE(plm_tsi0_reg_capture_now_1281), + .C(mgt_clk), + .D(plm_tsi0_reg_lane_num_3[3]), + .Q(plm_rx0_lane_num[3]), + .CLR(plm_rst) + ); + FDCE plm_tsi0_reg_lane_num_2_ ( + .CE(plm_tsi0_reg_capture_now_1281), + .C(mgt_clk), + .D(plm_tsi0_reg_lane_num_3[2]), + .Q(plm_rx0_lane_num[2]), + .CLR(plm_rst) + ); + FDCE plm_tsi0_reg_lane_num_1_ ( + .CE(plm_tsi0_reg_capture_now_1281), + .C(mgt_clk), + .D(plm_tsi0_reg_lane_num_3[1]), + .Q(plm_rx0_lane_num[1]), + .CLR(plm_rst) + ); + FDCE plm_tsi0_reg_lane_num_0_ ( + .CE(plm_tsi0_reg_capture_now_1281), + .C(mgt_clk), + .D(plm_tsi0_reg_lane_num_3[0]), + .Q(plm_rx0_lane_num[0]), + .CLR(plm_rst) + ); + FDCE plm_tsi0_reg_link_num_7_ ( + .CE(plm_tsi0_reg_capture_now_1281), + .C(mgt_clk), + .D(plm_tsi0_reg_link_num_3[7]), + .Q(plm_rx0_link_num[7]), + .CLR(plm_rst) + ); + FDCE plm_tsi0_reg_link_num_6_ ( + .CE(plm_tsi0_reg_capture_now_1281), + .C(mgt_clk), + .D(plm_tsi0_reg_link_num_3[6]), + .Q(plm_rx0_link_num[6]), + .CLR(plm_rst) + ); + FDCE plm_tsi0_reg_link_num_5_ ( + .CE(plm_tsi0_reg_capture_now_1281), + .C(mgt_clk), + .D(plm_tsi0_reg_link_num_3[5]), + .Q(plm_rx0_link_num[5]), + .CLR(plm_rst) + ); + FDCE plm_tsi0_reg_link_num_4_ ( + .CE(plm_tsi0_reg_capture_now_1281), + .C(mgt_clk), + .D(plm_tsi0_reg_link_num_3[4]), + .Q(plm_rx0_link_num[4]), + .CLR(plm_rst) + ); + FDCE plm_tsi0_reg_link_num_3_ ( + .CE(plm_tsi0_reg_capture_now_1281), + .C(mgt_clk), + .D(plm_tsi0_reg_link_num_3[3]), + .Q(plm_rx0_link_num[3]), + .CLR(plm_rst) + ); + FDCE plm_tsi0_reg_link_num_2_ ( + .CE(plm_tsi0_reg_capture_now_1281), + .C(mgt_clk), + .D(plm_tsi0_reg_link_num_3[2]), + .Q(plm_rx0_link_num[2]), + .CLR(plm_rst) + ); + FDCE plm_tsi0_reg_link_num_1_ ( + .CE(plm_tsi0_reg_capture_now_1281), + .C(mgt_clk), + .D(plm_tsi0_reg_link_num_3[1]), + .Q(plm_rx0_link_num[1]), + .CLR(plm_rst) + ); + FDCE plm_tsi0_reg_link_num_0_ ( + .CE(plm_tsi0_reg_capture_now_1281), + .C(mgt_clk), + .D(plm_tsi0_reg_link_num_3[0]), + .Q(plm_rx0_link_num[0]), + .CLR(plm_rst) + ); + FDCE plm_tsi0_reg_linkctrl_3_ ( + .CE(plm_tsi0_reg_capture_now_1281), + .C(mgt_clk), + .D(plm_tsi0_reg_linkctrl_3_3_), + .Q(plm_rx0_linkctrl_3_), + .CLR(plm_rst) + ); + FDCE plm_tsi0_reg_linkctrl_0_ ( + .CE(plm_tsi0_reg_capture_now_1281), + .C(mgt_clk), + .D(plm_tsi0_reg_linkctrl_3_0_), + .Q(plm_rx0_linkctrl_0_), + .CLR(plm_rst) + ); + SRL16 plm_tsi0_reg_dec8_0_I_1 ( + .D(plm_rx0_des_com[0]), + .Q(plm_tsi0_reg_dec8_0_N_6), + .CLK(mgt_clk), + .A0(plm_tsi0_GND_1282), + .A1(plm_tsi0_VCC_1283), + .A2(plm_tsi0_VCC_1283), + .A3(plm_tsi0_GND_1282) + ); + SRL16 plm_tsi0_reg_dec6_I_1 ( + .D(plm_rx0_des_sym[0]), + .Q(plm_tsi0_reg_dec6_tmp_d_array_0[0]), + .CLK(mgt_clk), + .A0(plm_tsi0_GND_1282), + .A1(plm_tsi0_GND_1282), + .A2(plm_tsi0_VCC_1283), + .A3(plm_tsi0_GND_1282) + ); + SRL16 plm_tsi0_reg_dec1_2_I_1 ( + .D(plm_reg_t2n_4[0]), + .Q(plm_tsi0_reg_dec1_2_N_6), + .CLK(mgt_clk), + .A0(plm_tsi0_VCC_1283), + .A1(plm_tsi0_GND_1282), + .A2(plm_tsi0_GND_1282), + .A3(plm_tsi0_GND_1282) + ); + SRL16 plm_tsi0_reg_dec1_1_I_1 ( + .D(plm_reg_t2p_4[0]), + .Q(plm_tsi0_reg_dec1_1_N_6), + .CLK(mgt_clk), + .A0(plm_tsi0_VCC_1283), + .A1(plm_tsi0_GND_1282), + .A2(plm_tsi0_GND_1282), + .A3(plm_tsi0_GND_1282) + ); + SRL16 plm_tsi0_reg_dec1_0_I_1 ( + .D(plm_reg_t1n_4[0]), + .Q(plm_tsi0_reg_dec1_0_N_6), + .CLK(mgt_clk), + .A0(plm_tsi0_VCC_1283), + .A1(plm_tsi0_GND_1282), + .A2(plm_tsi0_GND_1282), + .A3(plm_tsi0_GND_1282) + ); + SRL16 plm_tsi0_reg_dec1_I_1 ( + .D(plm_reg_t1p_4[0]), + .Q(plm_tsi0_reg_dec1_N_6), + .CLK(mgt_clk), + .A0(plm_tsi0_VCC_1283), + .A1(plm_tsi0_GND_1282), + .A2(plm_tsi0_GND_1282), + .A3(plm_tsi0_GND_1282) + ); + SRL16 plm_tsi0_reg_dec8_I_1 ( + .D(plm_rx0_des_com[1]), + .Q(plm_tsi0_reg_dec8_tmp_d_array_0[0]), + .CLK(mgt_clk), + .A0(plm_tsi0_GND_1282), + .A1(plm_tsi0_VCC_1283), + .A2(plm_tsi0_VCC_1283), + .A3(plm_tsi0_GND_1282) + ); + SRL16 plm_tsi0_reg_dec7_0_I_1 ( + .D(plm_rx0_des_pad[0]), + .Q(plm_tsi0_reg_dec7_0_N_6), + .CLK(mgt_clk), + .A0(plm_tsi0_VCC_1283), + .A1(plm_tsi0_GND_1282), + .A2(plm_tsi0_VCC_1283), + .A3(plm_tsi0_GND_1282) + ); + SRL16 plm_tsi0_reg_dec7_I_1 ( + .D(plm_rx0_des_pad[1]), + .Q(plm_tsi0_reg_dec7_tmp_d_array_0[0]), + .CLK(mgt_clk), + .A0(plm_tsi0_VCC_1283), + .A1(plm_tsi0_GND_1282), + .A2(plm_tsi0_VCC_1283), + .A3(plm_tsi0_GND_1282) + ); + SRL16 plm_tsi0_reg_dec5_I_1 ( + .D(plm_rx0_des_sym[1]), + .Q(plm_tsi0_reg_dec5_tmp_d_array_0[0]), + .CLK(mgt_clk), + .A0(plm_tsi0_VCC_1283), + .A1(plm_tsi0_VCC_1283), + .A2(plm_tsi0_GND_1282), + .A3(plm_tsi0_GND_1282) + ); + VCC plm_tsi1_VCC ( + .P(plm_tsi1_VCC_1354) + ); + GND plm_tsi1_GND ( + .G(plm_tsi1_GND_1353) + ); + SRL16 plm_tsi1_D00 ( + .D(plm_rx1_raw_dat[0]), + .Q(plm_tsi1_do[0]), + .CLK(mgt_clk), + .A0(plm_tsi1_VCC_1354), + .A1(plm_tsi1_GND_1353), + .A2(plm_tsi1_VCC_1354), + .A3(plm_tsi1_GND_1353) + ); + SRL16 plm_tsi1_D01 ( + .D(plm_rx1_raw_dat[1]), + .Q(plm_tsi1_do[1]), + .CLK(mgt_clk), + .A0(plm_tsi1_VCC_1354), + .A1(plm_tsi1_GND_1353), + .A2(plm_tsi1_VCC_1354), + .A3(plm_tsi1_GND_1353) + ); + SRL16 plm_tsi1_D02 ( + .D(plm_rx1_raw_dat[2]), + .Q(plm_tsi1_do[2]), + .CLK(mgt_clk), + .A0(plm_tsi1_VCC_1354), + .A1(plm_tsi1_GND_1353), + .A2(plm_tsi1_VCC_1354), + .A3(plm_tsi1_GND_1353) + ); + SRL16 plm_tsi1_D03 ( + .D(plm_rx1_raw_dat[3]), + .Q(plm_tsi1_do[3]), + .CLK(mgt_clk), + .A0(plm_tsi1_VCC_1354), + .A1(plm_tsi1_GND_1353), + .A2(plm_tsi1_VCC_1354), + .A3(plm_tsi1_GND_1353) + ); + SRL16 plm_tsi1_D04 ( + .D(plm_rx1_raw_dat[4]), + .Q(plm_tsi1_do[4]), + .CLK(mgt_clk), + .A0(plm_tsi1_VCC_1354), + .A1(plm_tsi1_GND_1353), + .A2(plm_tsi1_VCC_1354), + .A3(plm_tsi1_GND_1353) + ); + SRL16 plm_tsi1_D05 ( + .D(plm_rx1_raw_dat[5]), + .Q(plm_tsi1_do[5]), + .CLK(mgt_clk), + .A0(plm_tsi1_VCC_1354), + .A1(plm_tsi1_GND_1353), + .A2(plm_tsi1_VCC_1354), + .A3(plm_tsi1_GND_1353) + ); + SRL16 plm_tsi1_D06 ( + .D(plm_rx1_raw_dat[6]), + .Q(plm_tsi1_do[6]), + .CLK(mgt_clk), + .A0(plm_tsi1_VCC_1354), + .A1(plm_tsi1_GND_1353), + .A2(plm_tsi1_VCC_1354), + .A3(plm_tsi1_GND_1353) + ); + SRL16 plm_tsi1_D07 ( + .D(plm_rx1_raw_dat[7]), + .Q(plm_tsi1_do[7]), + .CLK(mgt_clk), + .A0(plm_tsi1_VCC_1354), + .A1(plm_tsi1_GND_1353), + .A2(plm_tsi1_VCC_1354), + .A3(plm_tsi1_GND_1353) + ); + SRL16 plm_tsi1_D08 ( + .D(plm_rx1_raw_dat[8]), + .Q(plm_tsi1_do[8]), + .CLK(mgt_clk), + .A0(plm_tsi1_VCC_1354), + .A1(plm_tsi1_GND_1353), + .A2(plm_tsi1_VCC_1354), + .A3(plm_tsi1_GND_1353) + ); + SRL16 plm_tsi1_D09 ( + .D(plm_rx1_raw_dat[9]), + .Q(plm_tsi1_do[9]), + .CLK(mgt_clk), + .A0(plm_tsi1_VCC_1354), + .A1(plm_tsi1_GND_1353), + .A2(plm_tsi1_VCC_1354), + .A3(plm_tsi1_GND_1353) + ); + SRL16 plm_tsi1_D10 ( + .D(plm_rx1_raw_dat[10]), + .Q(plm_tsi1_do[10]), + .CLK(mgt_clk), + .A0(plm_tsi1_VCC_1354), + .A1(plm_tsi1_GND_1353), + .A2(plm_tsi1_VCC_1354), + .A3(plm_tsi1_GND_1353) + ); + SRL16 plm_tsi1_D11 ( + .D(plm_rx1_raw_dat[11]), + .Q(plm_tsi1_do[11]), + .CLK(mgt_clk), + .A0(plm_tsi1_VCC_1354), + .A1(plm_tsi1_GND_1353), + .A2(plm_tsi1_VCC_1354), + .A3(plm_tsi1_GND_1353) + ); + SRL16 plm_tsi1_D12 ( + .D(plm_rx1_raw_dat[12]), + .Q(plm_tsi1_do[12]), + .CLK(mgt_clk), + .A0(plm_tsi1_VCC_1354), + .A1(plm_tsi1_GND_1353), + .A2(plm_tsi1_VCC_1354), + .A3(plm_tsi1_GND_1353) + ); + SRL16 plm_tsi1_D13 ( + .D(plm_rx1_raw_dat[13]), + .Q(plm_tsi1_do[13]), + .CLK(mgt_clk), + .A0(plm_tsi1_VCC_1354), + .A1(plm_tsi1_GND_1353), + .A2(plm_tsi1_VCC_1354), + .A3(plm_tsi1_GND_1353) + ); + SRL16 plm_tsi1_D14 ( + .D(plm_rx1_raw_dat[14]), + .Q(plm_tsi1_do[14]), + .CLK(mgt_clk), + .A0(plm_tsi1_VCC_1354), + .A1(plm_tsi1_GND_1353), + .A2(plm_tsi1_VCC_1354), + .A3(plm_tsi1_GND_1353) + ); + SRL16 plm_tsi1_D15 ( + .D(plm_rx1_raw_dat[15]), + .Q(plm_tsi1_do[15]), + .CLK(mgt_clk), + .A0(plm_tsi1_VCC_1354), + .A1(plm_tsi1_GND_1353), + .A2(plm_tsi1_VCC_1354), + .A3(plm_tsi1_GND_1353) + ); + defparam plm_tsi1_un2_com_data_jog0.INIT = 4'h1; + LUT2 plm_tsi1_un2_com_data_jog0 ( + .I0(plm_tsi1_reg_dec8_5__1316), + .I1(plm_tsi1_reg_dec8_6__1315), + .O(plm_tsi1_un2_com_data_jog0_0) + ); + defparam plm_tsi1_un2_recent_ts1.INIT = 16'h0001; + LUT4 plm_tsi1_un2_recent_ts1 ( + .I0(plm_tsi1_reg_ts1_timer[0]), + .I1(plm_tsi1_reg_ts1_timer[1]), + .I2(plm_tsi1_reg_ts1_timer[2]), + .I3(plm_tsi1_reg_ts1_timer[3]), + .O(plm_tsi1_un2_recent_ts1_0) + ); + defparam plm_tsi1_un2_recent_ts2.INIT = 16'h0001; + LUT4 plm_tsi1_un2_recent_ts2 ( + .I0(plm_tsi1_reg_ts2_timer[0]), + .I1(plm_tsi1_reg_ts2_timer[1]), + .I2(plm_tsi1_reg_ts2_timer[2]), + .I3(plm_tsi1_reg_ts2_timer[3]), + .O(plm_tsi1_un2_recent_ts2_0) + ); + defparam plm_tsi1_com_data_jog1_2.INIT = 16'h8880; + LUT4 plm_tsi1_com_data_jog1_2 ( + .I0(plm_tsi1_reg_dec6[5]), + .I1(plm_tsi1_reg_dec6_6107[12]), + .I2(plm_tsi1_reg_dec7_12__1336), + .I3(plm_tsi1_reg_dec7_13_), + .O(plm_tsi1_com_data_jog0_2) + ); + defparam plm_tsi1_ts1_inv0_jog1_1_4.INIT = 8'h80; + LUT3_L plm_tsi1_ts1_inv0_jog1_1_4 ( + .I0(plm_tsi1_reg_dec1[1]), + .I1(plm_tsi1_reg_dec1_6106[8]), + .I2(plm_tsi1_reg_dec2_1__1334), + .LO(plm_tsi1_ts1_inv0_jog1_1_4_1290) + ); + defparam plm_tsi1_ts1_inv0_jog1_1_5.INIT = 16'h8000; + LUT4 plm_tsi1_ts1_inv0_jog1_1_5 ( + .I0(plm_tsi1_reg_dec2_8__1326), + .I1(plm_tsi1_reg_dec3_1__1335), + .I2(plm_tsi1_reg_dec3_8__1327), + .I3(plm_tsi1_reg_dec4_1__1318), + .O(plm_tsi1_ts1_inv0_jog1_1_5_1289) + ); + defparam plm_tsi1_ts1_inv1_jog1_1_4.INIT = 8'h80; + LUT3_L plm_tsi1_ts1_inv1_jog1_1_4 ( + .I0(plm_tsi1_reg_dec1[2]), + .I1(plm_tsi1_reg_dec1_6106[9]), + .I2(plm_tsi1_reg_dec2_2__1332), + .LO(plm_tsi1_ts1_inv1_jog1_1_4_1292) + ); + defparam plm_tsi1_ts1_inv1_jog1_1_5.INIT = 16'h8000; + LUT4 plm_tsi1_ts1_inv1_jog1_1_5 ( + .I0(plm_tsi1_reg_dec2_9__1324), + .I1(plm_tsi1_reg_dec3_2__1333), + .I2(plm_tsi1_reg_dec3_9__1325), + .I3(plm_tsi1_reg_dec4_2__1349), + .O(plm_tsi1_ts1_inv1_jog1_1_5_1291) + ); + defparam plm_tsi1_ts2_inv1_jog0_1_4.INIT = 8'h80; + LUT3_L plm_tsi1_ts2_inv1_jog0_1_4 ( + .I0(plm_tsi1_reg_dec1[4]), + .I1(plm_tsi1_reg_dec1_6106[11]), + .I2(plm_tsi1_reg_dec2_4__1328), + .LO(plm_tsi1_ts2_inv1_jog0_1_4_1288) + ); + defparam plm_tsi1_ts2_inv1_jog0_1_5.INIT = 16'h8000; + LUT4 plm_tsi1_ts2_inv1_jog0_1_5 ( + .I0(plm_tsi1_reg_dec2_11__1320), + .I1(plm_tsi1_reg_dec3_4__1329), + .I2(plm_tsi1_reg_dec3_11__1321), + .I3(plm_tsi1_reg_dec4_4__1345), + .O(plm_tsi1_ts2_inv1_jog0_1_5_1287) + ); + defparam plm_tsi1_ts2_inv0_jog0_1_4.INIT = 8'h80; + LUT3_L plm_tsi1_ts2_inv0_jog0_1_4 ( + .I0(plm_tsi1_reg_dec1[3]), + .I1(plm_tsi1_reg_dec1_6106[10]), + .I2(plm_tsi1_reg_dec2_3__1330), + .LO(plm_tsi1_ts2_inv0_jog0_1_4_1286) + ); + defparam plm_tsi1_ts2_inv0_jog0_1_5.INIT = 16'h8000; + LUT4 plm_tsi1_ts2_inv0_jog0_1_5 ( + .I0(plm_tsi1_reg_dec2_10__1322), + .I1(plm_tsi1_reg_dec3_3__1331), + .I2(plm_tsi1_reg_dec3_10__1323), + .I3(plm_tsi1_reg_dec4_3__1347), + .O(plm_tsi1_ts2_inv0_jog0_1_5_1285) + ); + defparam plm_tsi1_idle_pair_0_a2_0_a2_0_a3_0_a2_9.INIT = 16'h0001; + LUT4 plm_tsi1_idle_pair_0_a2_0_a2_0_a3_0_a2_9 ( + .I0(plm_rx1_des_dat[6]), + .I1(plm_rx1_des_dat[7]), + .I2(plm_rx1_des_dat[13]), + .I3(plm_rx1_des_dat[14]), + .O(plm_tsi1_idle_pair_0_a2_0_a2_0_a3_0_a2_9_1298) + ); + defparam plm_tsi1_idle_pair_0_a2_0_a2_0_a3_0_a2_10.INIT = 16'h0001; + LUT4 plm_tsi1_idle_pair_0_a2_0_a2_0_a3_0_a2_10 ( + .I0(plm_rx1_des_dat[2]), + .I1(plm_rx1_des_dat[4]), + .I2(plm_rx1_des_dat[5]), + .I3(plm_rx1_des_dat[12]), + .O(plm_tsi1_idle_pair_0_a2_0_a2_0_a3_0_a2_10_1297) + ); + defparam plm_tsi1_idle_pair_0_a2_0_a2_0_a3_0_a2_11.INIT = 16'h0001; + LUT4 plm_tsi1_idle_pair_0_a2_0_a2_0_a3_0_a2_11 ( + .I0(plm_rx1_des_dat[0]), + .I1(plm_rx1_des_dat[10]), + .I2(plm_rx1_des_dat[11]), + .I3(plm_rx1_des_dat[15]), + .O(plm_tsi1_idle_pair_0_a2_0_a2_0_a3_0_a2_11_1296) + ); + defparam plm_tsi1_idle_pair_0_a2_0_a2_0_a3_0_a2_12.INIT = 16'h0001; + LUT4_L plm_tsi1_idle_pair_0_a2_0_a2_0_a3_0_a2_12 ( + .I0(plm_rx1_des_dat[1]), + .I1(plm_rx1_des_dat[3]), + .I2(plm_rx1_des_dat[8]), + .I3(plm_rx1_des_dat[9]), + .LO(plm_tsi1_idle_pair_0_a2_0_a2_0_a3_0_a2_12_1284) + ); + defparam plm_tsi1_com_data_jog1_1.INIT = 16'hA800; + LUT4 plm_tsi1_com_data_jog1_1 ( + .I0(plm_tsi1_reg_dec5[12]), + .I1(plm_tsi1_reg_dec7_5__1317), + .I2(plm_tsi1_reg_dec7_6_), + .I3(plm_tsi1_reg_dec8_0_), + .O(plm_tsi1_com_data_jog1_1_1294) + ); + defparam plm_tsi1_com_data_jog0.INIT = 16'h4000; + LUT4 plm_tsi1_com_data_jog0 ( + .I0(plm_tsi1_un2_com_data_jog0_0), + .I1(plm_tsi1_com_data_jog0_2), + .I2(plm_tsi1_reg_dec7_5__1317), + .I3(plm_tsi1_reg_dec8_7_), + .O(plm_tsi1_com_data_jog0_1301) + ); + defparam plm_tsi1_idle_pair_0_a2_0_a2_0_a3_0_a2_13.INIT = 8'h80; + LUT3_L plm_tsi1_idle_pair_0_a2_0_a2_0_a3_0_a2_13 ( + .I0(plm_rx1_des_sym[0]), + .I1(plm_rx1_des_sym[1]), + .I2(plm_tsi1_idle_pair_0_a2_0_a2_0_a3_0_a2_12_1284), + .LO(plm_tsi1_idle_pair_0_a2_0_a2_0_a3_0_a2_13_1295) + ); + defparam plm_tsi1_reg_ts1_timer_0_sqmuxa.INIT = 8'h01; + LUT3 plm_tsi1_reg_ts1_timer_0_sqmuxa ( + .I0(plm_tsi1_un2_recent_ts1_0), + .I1(plm_rx_clear_cs), + .I2(plm_tsi1_reg_capture_ts1_1314), + .O(plm_tsi1_reg_ts1_timer_0_sqmuxa_1310) + ); + defparam plm_tsi1_reg_ts2_timer_0_sqmuxa.INIT = 8'h01; + LUT3 plm_tsi1_reg_ts2_timer_0_sqmuxa ( + .I0(plm_tsi1_un2_recent_ts2_0), + .I1(plm_rx_clear_cs), + .I2(plm_tsi1_reg_capture_ts2_1313), + .O(plm_tsi1_reg_ts2_timer_0_sqmuxa_1309) + ); + defparam plm_tsi1_ts2_inv0_jog0_1.INIT = 16'h8000; + LUT4 plm_tsi1_ts2_inv0_jog0_1 ( + .I0(plm_tsi1_reg_dec4_10__1339), + .I1(plm_tsi1_reg_dec5_3__1348), + .I2(plm_tsi1_ts2_inv0_jog0_1_4_1286), + .I3(plm_tsi1_ts2_inv0_jog0_1_5_1285), + .O(plm_tsi1_ts2_inv0_jog0_1_1302) + ); + defparam plm_tsi1_ts2_inv1_jog0_1.INIT = 16'h8000; + LUT4 plm_tsi1_ts2_inv1_jog0_1 ( + .I0(plm_tsi1_reg_dec4_11__1337), + .I1(plm_tsi1_reg_dec5_4__1346), + .I2(plm_tsi1_ts2_inv1_jog0_1_4_1288), + .I3(plm_tsi1_ts2_inv1_jog0_1_5_1287), + .O(plm_tsi1_ts2_inv1_jog0_1_1300) + ); + defparam plm_tsi1_ts1_inv0_jog1_1.INIT = 16'h8000; + LUT4 plm_tsi1_ts1_inv0_jog1_1 ( + .I0(plm_tsi1_reg_dec4_8__1343), + .I1(plm_tsi1_reg_dec5_1__1319), + .I2(plm_tsi1_ts1_inv0_jog1_1_4_1290), + .I3(plm_tsi1_ts1_inv0_jog1_1_5_1289), + .O(plm_tsi1_ts1_inv0_jog1_1_1293) + ); + defparam plm_tsi1_ts1_inv1_jog1_1.INIT = 16'h8000; + LUT4 plm_tsi1_ts1_inv1_jog1_1 ( + .I0(plm_tsi1_reg_dec4_9__1341), + .I1(plm_tsi1_reg_dec5_2__1350), + .I2(plm_tsi1_ts1_inv1_jog1_1_4_1292), + .I3(plm_tsi1_ts1_inv1_jog1_1_5_1291), + .O(plm_tsi1_ts1_inv1_jog1_1_1299) + ); + defparam plm_tsi1_ts2_inv0_jog0_0.INIT = 4'h8; + LUT2 plm_tsi1_ts2_inv0_jog0_0 ( + .I0(plm_tsi1_com_data_jog0_1301), + .I1(plm_tsi1_reg_dec5_10__1340), + .O(plm_tsi1_ts2_inv0_jog0_0_1303) + ); + defparam plm_tsi1_un7_reg_ts1_timer_axbxc3.INIT = 16'hFE01; + LUT4 plm_tsi1_un7_reg_ts1_timer_axbxc3 ( + .I0(plm_tsi1_reg_ts1_timer[0]), + .I1(plm_tsi1_reg_ts1_timer[1]), + .I2(plm_tsi1_reg_ts1_timer[2]), + .I3(plm_tsi1_reg_ts1_timer[3]), + .O(plm_tsi1_un7_reg_ts1_timer_axbxc3_0) + ); + defparam plm_tsi1_un7_reg_ts2_timer_axbxc3.INIT = 16'hFE01; + LUT4 plm_tsi1_un7_reg_ts2_timer_axbxc3 ( + .I0(plm_tsi1_reg_ts2_timer[0]), + .I1(plm_tsi1_reg_ts2_timer[1]), + .I2(plm_tsi1_reg_ts2_timer[2]), + .I3(plm_tsi1_reg_ts2_timer[3]), + .O(plm_tsi1_un7_reg_ts2_timer_axbxc3_0) + ); + defparam plm_tsi1_ts2_inv0_jog1.INIT = 16'h8000; + LUT4 plm_tsi1_ts2_inv0_jog1 ( + .I0(plm_rx1_des_t2p[1]), + .I1(plm_tsi1_com_data_jog0_2), + .I2(plm_tsi1_com_data_jog1_1_1294), + .I3(plm_tsi1_ts2_inv0_jog0_1_1302), + .O(plm_tsi1_ts2_inv0_jog1_1305) + ); + defparam plm_tsi1_ts2_inv1_jog1.INIT = 16'h8000; + LUT4 plm_tsi1_ts2_inv1_jog1 ( + .I0(plm_rx1_des_t2n[1]), + .I1(plm_tsi1_com_data_jog0_2), + .I2(plm_tsi1_com_data_jog1_1_1294), + .I3(plm_tsi1_ts2_inv1_jog0_1_1300), + .O(plm_tsi1_ts2_inv1_jog1_1304) + ); + defparam plm_tsi1_ts1_inv0_jog0.INIT = 8'h80; + LUT3 plm_tsi1_ts1_inv0_jog0 ( + .I0(plm_tsi1_com_data_jog0_1301), + .I1(plm_tsi1_reg_dec5_8__1344), + .I2(plm_tsi1_ts1_inv0_jog1_1_1293), + .O(plm_tsi1_ts1_inv0_jog0_1308) + ); + defparam plm_tsi1_ts1_inv0_jog1.INIT = 16'h8000; + LUT4 plm_tsi1_ts1_inv0_jog1 ( + .I0(plm_rx1_des_t1p[1]), + .I1(plm_tsi1_com_data_jog0_2), + .I2(plm_tsi1_com_data_jog1_1_1294), + .I3(plm_tsi1_ts1_inv0_jog1_1_1293), + .O(plm_tsi1_ts1_inv0_jog1_1307) + ); + defparam plm_tsi1_ts1_inv1_jog1.INIT = 16'h8000; + LUT4 plm_tsi1_ts1_inv1_jog1 ( + .I0(plm_rx1_des_t1n[1]), + .I1(plm_tsi1_com_data_jog0_2), + .I2(plm_tsi1_com_data_jog1_1_1294), + .I3(plm_tsi1_ts1_inv1_jog1_1_1299), + .O(plm_tsi1_ts1_inv1_jog1_1306) + ); + defparam plm_tsi1_idle_pair_0_a2_0_a2_0_a3_0_a2.INIT = 16'h8000; + LUT4 plm_tsi1_idle_pair_0_a2_0_a2_0_a3_0_a2 ( + .I0(plm_tsi1_idle_pair_0_a2_0_a2_0_a3_0_a2_9_1298), + .I1(plm_tsi1_idle_pair_0_a2_0_a2_0_a3_0_a2_10_1297), + .I2(plm_tsi1_idle_pair_0_a2_0_a2_0_a3_0_a2_11_1296), + .I3(plm_tsi1_idle_pair_0_a2_0_a2_0_a3_0_a2_13_1295), + .O(plm_tsi1_idle_pair) + ); + defparam plm_tsi1_what_it_is_reg_capture_inv_3_5893.INIT = 16'h070F; + LUT4 plm_tsi1_what_it_is_reg_capture_inv_3_5893 ( + .I0(plm_tsi1_com_data_jog0_1301), + .I1(plm_tsi1_reg_dec5_9__1342), + .I2(plm_tsi1_ts1_inv1_jog1_1306), + .I3(plm_tsi1_ts1_inv1_jog1_1_1299), + .O(plm_tsi1_reg_capture_inv_3_5893) + ); + defparam plm_tsi1_what_it_is_reg_capture_inv_3_5894.INIT = 16'h007F; + LUT4 plm_tsi1_what_it_is_reg_capture_inv_3_5894 ( + .I0(plm_tsi1_com_data_jog0_1301), + .I1(plm_tsi1_reg_dec5_11__1338), + .I2(plm_tsi1_ts2_inv1_jog0_1_1300), + .I3(plm_tsi1_ts2_inv1_jog1_1304), + .O(plm_tsi1_reg_capture_inv_3_5894) + ); + defparam plm_tsi1_what_it_is_reg_capture_ts2_3.INIT = 16'h002A; + LUT4 plm_tsi1_what_it_is_reg_capture_ts2_3 ( + .I0(plm_tsi1_reg_capture_inv_3_5894), + .I1(plm_tsi1_ts2_inv0_jog0_0_1303), + .I2(plm_tsi1_ts2_inv0_jog0_1_1302), + .I3(plm_tsi1_ts2_inv0_jog1_1305), + .O(plm_tsi1_reg_capture_ts2_3) + ); + defparam plm_tsi1_event_regs_reg_ts2_c_3.INIT = 8'h10; + LUT3_L plm_tsi1_event_regs_reg_ts2_c_3 ( + .I0(plm_tsi1_un2_recent_ts2_0), + .I1(plm_rx_clear_cs), + .I2(plm_tsi1_reg_capture_ts2_1313), + .LO(plm_tsi1_reg_ts2_c_3) + ); + defparam plm_tsi1_event_regs_reg_ts1_c_3.INIT = 8'h10; + LUT3_L plm_tsi1_event_regs_reg_ts1_c_3 ( + .I0(plm_tsi1_un2_recent_ts1_0), + .I1(plm_rx_clear_cs), + .I2(plm_tsi1_reg_capture_ts1_1314), + .LO(plm_tsi1_reg_ts1_c_3) + ); + defparam plm_tsi1_what_it_is_N_11384_i.INIT = 4'h1; + LUT1_L plm_tsi1_what_it_is_N_11384_i ( + .I0(plm_tsi1_reg_capture_ts2_3), + .LO(plm_tsi1_N_11384_i) + ); + defparam plm_tsi1_what_it_is_N_11385_i.INIT = 8'hFD; + LUT3_L plm_tsi1_what_it_is_N_11385_i ( + .I0(plm_tsi1_reg_capture_inv_3_5893), + .I1(plm_tsi1_ts1_inv0_jog0_1308), + .I2(plm_tsi1_ts1_inv0_jog1_1307), + .LO(plm_tsi1_N_11385_i) + ); + defparam plm_tsi1_what_it_is_N_11387_i.INIT = 16'hFFFE; + LUT4_L plm_tsi1_what_it_is_N_11387_i ( + .I0(plm_tsi1_ts1_inv0_jog1_1307), + .I1(plm_tsi1_ts1_inv1_jog1_1306), + .I2(plm_tsi1_ts2_inv0_jog1_1305), + .I3(plm_tsi1_ts2_inv1_jog1_1304), + .LO(plm_tsi1_N_11387_i) + ); + defparam plm_tsi1_what_it_is_N_11386_i.INIT = 4'h7; + LUT2_L plm_tsi1_what_it_is_N_11386_i ( + .I0(plm_tsi1_reg_capture_inv_3_5893), + .I1(plm_tsi1_reg_capture_inv_3_5894), + .LO(plm_tsi1_N_11386_i) + ); + defparam plm_tsi1_idle_hands_reg_rx_idl_c_3_0_a2_0_a2_0_a3_0_a2.INIT = 4'h8; + LUT2_L plm_tsi1_idle_hands_reg_rx_idl_c_3_0_a2_0_a2_0_a3_0_a2 ( + .I0(plm_reg_rx_idl_1_0), + .I1(plm_tsi1_idle_pair), + .LO(plm_tsi1_reg_rx_idl_c_3) + ); + defparam plm_tsi1_what_it_is_N_11383_i.INIT = 16'hFFF7; + LUT4_L plm_tsi1_what_it_is_N_11383_i ( + .I0(plm_tsi1_reg_capture_ts2_3), + .I1(plm_tsi1_reg_capture_inv_3_5893), + .I2(plm_tsi1_ts1_inv0_jog0_1308), + .I3(plm_tsi1_ts1_inv0_jog1_1307), + .LO(plm_tsi1_N_11383_i) + ); + defparam plm_tsi1_event_regs_reg_ts2_timer_5_f0_3_.INIT = 16'hF1F0; + LUT4_L plm_tsi1_event_regs_reg_ts2_timer_5_f0_3_ ( + .I0(plm_tsi1_un2_recent_ts2_0), + .I1(plm_rx_clear_cs), + .I2(plm_tsi1_reg_capture_ts2_1313), + .I3(plm_tsi1_un7_reg_ts2_timer_axbxc3_0), + .LO(plm_tsi1_reg_ts2_timer_5[3]) + ); + defparam plm_tsi1_event_regs_reg_ts2_timer_5_2_.INIT = 16'hE100; + LUT4_L plm_tsi1_event_regs_reg_ts2_timer_5_2_ ( + .I0(plm_tsi1_reg_ts2_timer[0]), + .I1(plm_tsi1_reg_ts2_timer[1]), + .I2(plm_tsi1_reg_ts2_timer[2]), + .I3(plm_tsi1_reg_ts2_timer_0_sqmuxa_1309), + .LO(plm_tsi1_reg_ts2_timer_5[2]) + ); + defparam plm_tsi1_event_regs_reg_ts2_timer_5_1_.INIT = 8'h90; + LUT3_L plm_tsi1_event_regs_reg_ts2_timer_5_1_ ( + .I0(plm_tsi1_reg_ts2_timer[0]), + .I1(plm_tsi1_reg_ts2_timer[1]), + .I2(plm_tsi1_reg_ts2_timer_0_sqmuxa_1309), + .LO(plm_tsi1_reg_ts2_timer_5[1]) + ); + defparam plm_tsi1_event_regs_reg_ts2_timer_5_0_.INIT = 4'h4; + LUT2_L plm_tsi1_event_regs_reg_ts2_timer_5_0_ ( + .I0(plm_tsi1_reg_ts2_timer[0]), + .I1(plm_tsi1_reg_ts2_timer_0_sqmuxa_1309), + .LO(plm_tsi1_reg_ts2_timer_5[0]) + ); + defparam plm_tsi1_event_regs_reg_ts1_timer_5_f0_3_.INIT = 16'hF1F0; + LUT4_L plm_tsi1_event_regs_reg_ts1_timer_5_f0_3_ ( + .I0(plm_tsi1_un2_recent_ts1_0), + .I1(plm_rx_clear_cs), + .I2(plm_tsi1_reg_capture_ts1_1314), + .I3(plm_tsi1_un7_reg_ts1_timer_axbxc3_0), + .LO(plm_tsi1_reg_ts1_timer_5[3]) + ); + defparam plm_tsi1_event_regs_reg_ts1_timer_5_2_.INIT = 16'hE100; + LUT4_L plm_tsi1_event_regs_reg_ts1_timer_5_2_ ( + .I0(plm_tsi1_reg_ts1_timer[0]), + .I1(plm_tsi1_reg_ts1_timer[1]), + .I2(plm_tsi1_reg_ts1_timer[2]), + .I3(plm_tsi1_reg_ts1_timer_0_sqmuxa_1310), + .LO(plm_tsi1_reg_ts1_timer_5[2]) + ); + defparam plm_tsi1_event_regs_reg_ts1_timer_5_1_.INIT = 8'h90; + LUT3_L plm_tsi1_event_regs_reg_ts1_timer_5_1_ ( + .I0(plm_tsi1_reg_ts1_timer[0]), + .I1(plm_tsi1_reg_ts1_timer[1]), + .I2(plm_tsi1_reg_ts1_timer_0_sqmuxa_1310), + .LO(plm_tsi1_reg_ts1_timer_5[1]) + ); + defparam plm_tsi1_event_regs_reg_ts1_timer_5_0_.INIT = 4'h4; + LUT2_L plm_tsi1_event_regs_reg_ts1_timer_5_0_ ( + .I0(plm_tsi1_reg_ts1_timer[0]), + .I1(plm_tsi1_reg_ts1_timer_0_sqmuxa_1310), + .LO(plm_tsi1_reg_ts1_timer_5[0]) + ); + defparam plm_tsi1_holding_regs_reg_lane_pad_3_0.INIT = 8'hD8; + LUT3_L plm_tsi1_holding_regs_reg_lane_pad_3_0 ( + .I0(plm_tsi1_reg_capture_jog_1312), + .I1(plm_tsi1_reg_dec8_6__1315), + .I2(plm_tsi1_reg_dec8_13__1311), + .LO(plm_tsi1_reg_lane_pad_3) + ); + defparam plm_tsi1_holding_regs_reg_link_pad_3_0.INIT = 8'hD8; + LUT3_L plm_tsi1_holding_regs_reg_link_pad_3_0 ( + .I0(plm_tsi1_reg_capture_jog_1312), + .I1(plm_tsi1_reg_dec8_13__1311), + .I2(plm_tsi1_reg_dec9[6]), + .LO(plm_tsi1_reg_link_pad_3) + ); + defparam plm_tsi1_holding_regs_reg_lane_num_3_7_.INIT = 16'h596A; + LUT4_L plm_tsi1_holding_regs_reg_lane_num_3_7_ ( + .I0(plm_tsi1_reg_capture_inv_1351), + .I1(plm_tsi1_reg_capture_jog_1312), + .I2(plm_tsi1_reg_dly8[7]), + .I3(plm_tsi1_reg_dly8[15]), + .LO(plm_tsi1_reg_lane_num_3[7]) + ); + defparam plm_tsi1_holding_regs_reg_lane_num_3_6_.INIT = 16'h596A; + LUT4_L plm_tsi1_holding_regs_reg_lane_num_3_6_ ( + .I0(plm_tsi1_reg_capture_inv_1351), + .I1(plm_tsi1_reg_capture_jog_1312), + .I2(plm_tsi1_reg_dly8[6]), + .I3(plm_tsi1_reg_dly8[14]), + .LO(plm_tsi1_reg_lane_num_3[6]) + ); + defparam plm_tsi1_holding_regs_reg_lane_num_3_5_.INIT = 16'h596A; + LUT4_L plm_tsi1_holding_regs_reg_lane_num_3_5_ ( + .I0(plm_tsi1_reg_capture_inv_1351), + .I1(plm_tsi1_reg_capture_jog_1312), + .I2(plm_tsi1_reg_dly8[5]), + .I3(plm_tsi1_reg_dly8[13]), + .LO(plm_tsi1_reg_lane_num_3[5]) + ); + defparam plm_tsi1_holding_regs_reg_lane_num_3_4_.INIT = 16'h596A; + LUT4_L plm_tsi1_holding_regs_reg_lane_num_3_4_ ( + .I0(plm_tsi1_reg_capture_inv_1351), + .I1(plm_tsi1_reg_capture_jog_1312), + .I2(plm_tsi1_reg_dly8[4]), + .I3(plm_tsi1_reg_dly8[12]), + .LO(plm_tsi1_reg_lane_num_3[4]) + ); + defparam plm_tsi1_holding_regs_reg_lane_num_3_3_.INIT = 16'h596A; + LUT4_L plm_tsi1_holding_regs_reg_lane_num_3_3_ ( + .I0(plm_tsi1_reg_capture_inv_1351), + .I1(plm_tsi1_reg_capture_jog_1312), + .I2(plm_tsi1_reg_dly8[3]), + .I3(plm_tsi1_reg_dly8[11]), + .LO(plm_tsi1_reg_lane_num_3[3]) + ); + defparam plm_tsi1_holding_regs_reg_lane_num_3_2_.INIT = 16'h596A; + LUT4_L plm_tsi1_holding_regs_reg_lane_num_3_2_ ( + .I0(plm_tsi1_reg_capture_inv_1351), + .I1(plm_tsi1_reg_capture_jog_1312), + .I2(plm_tsi1_reg_dly8[2]), + .I3(plm_tsi1_reg_dly8[10]), + .LO(plm_tsi1_reg_lane_num_3[2]) + ); + defparam plm_tsi1_holding_regs_reg_lane_num_3_1_.INIT = 16'h596A; + LUT4_L plm_tsi1_holding_regs_reg_lane_num_3_1_ ( + .I0(plm_tsi1_reg_capture_inv_1351), + .I1(plm_tsi1_reg_capture_jog_1312), + .I2(plm_tsi1_reg_dly8[1]), + .I3(plm_tsi1_reg_dly8[9]), + .LO(plm_tsi1_reg_lane_num_3[1]) + ); + defparam plm_tsi1_holding_regs_reg_lane_num_3_0_.INIT = 16'h596A; + LUT4_L plm_tsi1_holding_regs_reg_lane_num_3_0_ ( + .I0(plm_tsi1_reg_capture_inv_1351), + .I1(plm_tsi1_reg_capture_jog_1312), + .I2(plm_tsi1_reg_dly8[0]), + .I3(plm_tsi1_reg_dly8[8]), + .LO(plm_tsi1_reg_lane_num_3[0]) + ); + defparam plm_tsi1_holding_regs_reg_link_num_3_7_.INIT = 16'h596A; + LUT4_L plm_tsi1_holding_regs_reg_link_num_3_7_ ( + .I0(plm_tsi1_reg_capture_inv_1351), + .I1(plm_tsi1_reg_capture_jog_1312), + .I2(plm_tsi1_reg_dly8[15]), + .I3(plm_tsi1_reg_dly9[7]), + .LO(plm_tsi1_reg_link_num_3[7]) + ); + defparam plm_tsi1_holding_regs_reg_link_num_3_6_.INIT = 16'h596A; + LUT4_L plm_tsi1_holding_regs_reg_link_num_3_6_ ( + .I0(plm_tsi1_reg_capture_inv_1351), + .I1(plm_tsi1_reg_capture_jog_1312), + .I2(plm_tsi1_reg_dly8[14]), + .I3(plm_tsi1_reg_dly9[6]), + .LO(plm_tsi1_reg_link_num_3[6]) + ); + defparam plm_tsi1_holding_regs_reg_link_num_3_5_.INIT = 16'h596A; + LUT4_L plm_tsi1_holding_regs_reg_link_num_3_5_ ( + .I0(plm_tsi1_reg_capture_inv_1351), + .I1(plm_tsi1_reg_capture_jog_1312), + .I2(plm_tsi1_reg_dly8[13]), + .I3(plm_tsi1_reg_dly9[5]), + .LO(plm_tsi1_reg_link_num_3[5]) + ); + defparam plm_tsi1_holding_regs_reg_link_num_3_4_.INIT = 16'h596A; + LUT4_L plm_tsi1_holding_regs_reg_link_num_3_4_ ( + .I0(plm_tsi1_reg_capture_inv_1351), + .I1(plm_tsi1_reg_capture_jog_1312), + .I2(plm_tsi1_reg_dly8[12]), + .I3(plm_tsi1_reg_dly9[4]), + .LO(plm_tsi1_reg_link_num_3[4]) + ); + defparam plm_tsi1_holding_regs_reg_link_num_3_3_.INIT = 16'h596A; + LUT4_L plm_tsi1_holding_regs_reg_link_num_3_3_ ( + .I0(plm_tsi1_reg_capture_inv_1351), + .I1(plm_tsi1_reg_capture_jog_1312), + .I2(plm_tsi1_reg_dly8[11]), + .I3(plm_tsi1_reg_dly9[3]), + .LO(plm_tsi1_reg_link_num_3[3]) + ); + defparam plm_tsi1_holding_regs_reg_link_num_3_2_.INIT = 16'h596A; + LUT4_L plm_tsi1_holding_regs_reg_link_num_3_2_ ( + .I0(plm_tsi1_reg_capture_inv_1351), + .I1(plm_tsi1_reg_capture_jog_1312), + .I2(plm_tsi1_reg_dly8[10]), + .I3(plm_tsi1_reg_dly9[2]), + .LO(plm_tsi1_reg_link_num_3[2]) + ); + defparam plm_tsi1_holding_regs_reg_link_num_3_1_.INIT = 16'h596A; + LUT4_L plm_tsi1_holding_regs_reg_link_num_3_1_ ( + .I0(plm_tsi1_reg_capture_inv_1351), + .I1(plm_tsi1_reg_capture_jog_1312), + .I2(plm_tsi1_reg_dly8[9]), + .I3(plm_tsi1_reg_dly9[1]), + .LO(plm_tsi1_reg_link_num_3[1]) + ); + defparam plm_tsi1_holding_regs_reg_link_num_3_0_.INIT = 16'h596A; + LUT4_L plm_tsi1_holding_regs_reg_link_num_3_0_ ( + .I0(plm_tsi1_reg_capture_inv_1351), + .I1(plm_tsi1_reg_capture_jog_1312), + .I2(plm_tsi1_reg_dly8[8]), + .I3(plm_tsi1_reg_dly9[0]), + .LO(plm_tsi1_reg_link_num_3[0]) + ); + defparam plm_tsi1_holding_regs_reg_linkctrl_3_3_.INIT = 16'h636C; + LUT4_L plm_tsi1_holding_regs_reg_linkctrl_3_3_ ( + .I0(plm_tsi1_do[11]), + .I1(plm_tsi1_reg_capture_inv_1351), + .I2(plm_tsi1_reg_capture_jog_1312), + .I3(plm_tsi1_reg_dly7[3]), + .LO(plm_tsi1_reg_linkctrl_3_3_) + ); + defparam plm_tsi1_holding_regs_reg_linkctrl_3_0_.INIT = 16'h636C; + LUT4_L plm_tsi1_holding_regs_reg_linkctrl_3_0_ ( + .I0(plm_tsi1_do[8]), + .I1(plm_tsi1_reg_capture_inv_1351), + .I2(plm_tsi1_reg_capture_jog_1312), + .I3(plm_tsi1_reg_dly7[0]), + .LO(plm_tsi1_reg_linkctrl_3_0_) + ); + FD plm_tsi1_reg_dec8_0_DOUT_0_ ( + .C(mgt_clk), + .D(plm_tsi1_reg_dec8_0_N_6), + .Q(plm_tsi1_reg_dec8_0_DOUT[0]) + ); + FD plm_tsi1_reg_dec6_DOUT_0_ ( + .C(mgt_clk), + .D(plm_tsi1_reg_dec6_N_6), + .Q(plm_tsi1_reg_dec6_DOUT[0]) + ); + FD plm_tsi1_reg_dec1_2_DOUT_0_ ( + .C(mgt_clk), + .D(plm_tsi1_reg_dec1_2_N_6), + .Q(plm_tsi1_reg_dec1_2_DOUT[0]) + ); + FD plm_tsi1_reg_dec1_1_DOUT_0_ ( + .C(mgt_clk), + .D(plm_tsi1_reg_dec1_1_N_6), + .Q(plm_tsi1_reg_dec1_1_DOUT[0]) + ); + FD plm_tsi1_reg_dec1_0_DOUT_0_ ( + .C(mgt_clk), + .D(plm_tsi1_reg_dec1_0_N_6), + .Q(plm_tsi1_reg_dec1_0_DOUT[0]) + ); + FD plm_tsi1_reg_dec1_DOUT_0_ ( + .C(mgt_clk), + .D(plm_tsi1_reg_dec1_N_6), + .Q(plm_tsi1_reg_dec1_DOUT[0]) + ); + FD plm_tsi1_reg_dec8_DOUT_0_ ( + .C(mgt_clk), + .D(plm_tsi1_reg_dec8_N_6), + .Q(plm_tsi1_reg_dec8_DOUT[0]) + ); + FD plm_tsi1_reg_dec7_0_DOUT_0_ ( + .C(mgt_clk), + .D(plm_tsi1_reg_dec7_0_N_6), + .Q(plm_tsi1_reg_dec7_0_DOUT[0]) + ); + FD plm_tsi1_reg_dec7_DOUT_0_ ( + .C(mgt_clk), + .D(plm_tsi1_reg_dec7_tmp_d_array_0[0]), + .Q(plm_tsi1_reg_dec7_DOUT[0]) + ); + FD plm_tsi1_reg_dec5_DOUT_0_ ( + .C(mgt_clk), + .D(plm_tsi1_reg_dec5_N_6), + .Q(plm_tsi1_reg_dec5_DOUT[0]) + ); + FDC plm_tsi1_reg_dec9_6_ ( + .C(mgt_clk), + .D(plm_tsi1_reg_dec8_6__1315), + .Q(plm_tsi1_reg_dec9[6]), + .CLR(plm_rst) + ); + FDC plm_tsi1_reg_dec8_13_ ( + .C(mgt_clk), + .D(plm_tsi1_reg_dec7_13_), + .Q(plm_tsi1_reg_dec8_13__1311), + .CLR(plm_rst) + ); + FDC plm_tsi1_reg_rx_idl_1 ( + .C(mgt_clk), + .D(plm_tsi1_idle_pair), + .Q(plm_reg_rx_idl_1_0), + .CLR(plm_rst) + ); + FDC plm_tsi1_reg_ts2_c ( + .C(mgt_clk), + .D(plm_tsi1_reg_ts2_c_3), + .Q(plm_rx1_ts2_c), + .CLR(plm_rst) + ); + FDC plm_tsi1_reg_ts1_c ( + .C(mgt_clk), + .D(plm_tsi1_reg_ts1_c_3), + .Q(plm_rx1_ts1_c), + .CLR(plm_rst) + ); + FDC plm_tsi1_reg_capture_ts2 ( + .C(mgt_clk), + .D(plm_tsi1_N_11384_i), + .Q(plm_tsi1_reg_capture_ts2_1313), + .CLR(plm_rst) + ); + FDC plm_tsi1_reg_capture_ts1 ( + .C(mgt_clk), + .D(plm_tsi1_N_11385_i), + .Q(plm_tsi1_reg_capture_ts1_1314), + .CLR(plm_rst) + ); + FDC plm_tsi1_reg_capture_jog ( + .C(mgt_clk), + .D(plm_tsi1_N_11387_i), + .Q(plm_tsi1_reg_capture_jog_1312), + .CLR(plm_rst) + ); + FDC plm_tsi1_reg_capture_inv ( + .C(mgt_clk), + .D(plm_tsi1_N_11386_i), + .Q(plm_tsi1_reg_capture_inv_1351), + .CLR(plm_rst) + ); + FDC plm_tsi1_reg_rx_idl_c ( + .C(mgt_clk), + .D(plm_tsi1_reg_rx_idl_c_3), + .Q(plm_rx1_idl_c), + .CLR(plm_rst) + ); + FDC plm_tsi1_reg_ts2_1 ( + .C(mgt_clk), + .D(plm_tsi1_reg_capture_ts2_1313), + .Q(plm_reg_ts2_1_0), + .CLR(plm_rst) + ); + FDC plm_tsi1_reg_ts1_1 ( + .C(mgt_clk), + .D(plm_tsi1_reg_capture_ts1_1314), + .Q(plm_reg_ts1_1_0), + .CLR(plm_rst) + ); + FDC plm_tsi1_reg_capture_now ( + .C(mgt_clk), + .D(plm_tsi1_N_11383_i), + .Q(plm_tsi1_reg_capture_now_1352), + .CLR(plm_rst) + ); + FDC plm_tsi1_reg_dec2_4_ ( + .C(mgt_clk), + .D(plm_tsi1_reg_dec1[4]), + .Q(plm_tsi1_reg_dec2_4__1328), + .CLR(plm_rst) + ); + FDC plm_tsi1_reg_dec2_3_ ( + .C(mgt_clk), + .D(plm_tsi1_reg_dec1[3]), + .Q(plm_tsi1_reg_dec2_3__1330), + .CLR(plm_rst) + ); + FDC plm_tsi1_reg_dec2_2_ ( + .C(mgt_clk), + .D(plm_tsi1_reg_dec1[2]), + .Q(plm_tsi1_reg_dec2_2__1332), + .CLR(plm_rst) + ); + FDC plm_tsi1_reg_dec2_1_ ( + .C(mgt_clk), + .D(plm_tsi1_reg_dec1[1]), + .Q(plm_tsi1_reg_dec2_1__1334), + .CLR(plm_rst) + ); + FDC plm_tsi1_reg_ts2_timer_3_ ( + .C(mgt_clk), + .D(plm_tsi1_reg_ts2_timer_5[3]), + .Q(plm_tsi1_reg_ts2_timer[3]), + .CLR(plm_rst) + ); + FDC plm_tsi1_reg_ts2_timer_2_ ( + .C(mgt_clk), + .D(plm_tsi1_reg_ts2_timer_5[2]), + .Q(plm_tsi1_reg_ts2_timer[2]), + .CLR(plm_rst) + ); + FDC plm_tsi1_reg_ts2_timer_1_ ( + .C(mgt_clk), + .D(plm_tsi1_reg_ts2_timer_5[1]), + .Q(plm_tsi1_reg_ts2_timer[1]), + .CLR(plm_rst) + ); + FDC plm_tsi1_reg_ts2_timer_0_ ( + .C(mgt_clk), + .D(plm_tsi1_reg_ts2_timer_5[0]), + .Q(plm_tsi1_reg_ts2_timer[0]), + .CLR(plm_rst) + ); + FDC plm_tsi1_reg_ts1_timer_3_ ( + .C(mgt_clk), + .D(plm_tsi1_reg_ts1_timer_5[3]), + .Q(plm_tsi1_reg_ts1_timer[3]), + .CLR(plm_rst) + ); + FDC plm_tsi1_reg_ts1_timer_2_ ( + .C(mgt_clk), + .D(plm_tsi1_reg_ts1_timer_5[2]), + .Q(plm_tsi1_reg_ts1_timer[2]), + .CLR(plm_rst) + ); + FDC plm_tsi1_reg_ts1_timer_1_ ( + .C(mgt_clk), + .D(plm_tsi1_reg_ts1_timer_5[1]), + .Q(plm_tsi1_reg_ts1_timer[1]), + .CLR(plm_rst) + ); + FDC plm_tsi1_reg_ts1_timer_0_ ( + .C(mgt_clk), + .D(plm_tsi1_reg_ts1_timer_5[0]), + .Q(plm_tsi1_reg_ts1_timer[0]), + .CLR(plm_rst) + ); + FDC plm_tsi1_reg_dec8_6_ ( + .C(mgt_clk), + .D(plm_tsi1_reg_dec7_6_), + .Q(plm_tsi1_reg_dec8_6__1315), + .CLR(plm_rst) + ); + FDC plm_tsi1_reg_dec8_5_ ( + .C(mgt_clk), + .D(plm_tsi1_reg_dec7_5__1317), + .Q(plm_tsi1_reg_dec8_5__1316), + .CLR(plm_rst) + ); + FDC plm_tsi1_reg_dec2_11_ ( + .C(mgt_clk), + .D(plm_tsi1_reg_dec1_6106[11]), + .Q(plm_tsi1_reg_dec2_11__1320), + .CLR(plm_rst) + ); + FDC plm_tsi1_reg_dec2_10_ ( + .C(mgt_clk), + .D(plm_tsi1_reg_dec1_6106[10]), + .Q(plm_tsi1_reg_dec2_10__1322), + .CLR(plm_rst) + ); + FDC plm_tsi1_reg_dec2_9_ ( + .C(mgt_clk), + .D(plm_tsi1_reg_dec1_6106[9]), + .Q(plm_tsi1_reg_dec2_9__1324), + .CLR(plm_rst) + ); + FDC plm_tsi1_reg_dec2_8_ ( + .C(mgt_clk), + .D(plm_tsi1_reg_dec1_6106[8]), + .Q(plm_tsi1_reg_dec2_8__1326), + .CLR(plm_rst) + ); + FDC plm_tsi1_reg_dec1_11_ ( + .C(mgt_clk), + .D(plm_rx1_des_t2n[1]), + .Q(plm_tsi1_reg_dec1_6106[11]), + .CLR(plm_rst) + ); + FDC plm_tsi1_reg_dec1_10_ ( + .C(mgt_clk), + .D(plm_rx1_des_t2p[1]), + .Q(plm_tsi1_reg_dec1_6106[10]), + .CLR(plm_rst) + ); + FDC plm_tsi1_reg_dec1_9_ ( + .C(mgt_clk), + .D(plm_rx1_des_t1n[1]), + .Q(plm_tsi1_reg_dec1_6106[9]), + .CLR(plm_rst) + ); + FDC plm_tsi1_reg_dec1_8_ ( + .C(mgt_clk), + .D(plm_rx1_des_t1p[1]), + .Q(plm_tsi1_reg_dec1_6106[8]), + .CLR(plm_rst) + ); + FDC plm_tsi1_reg_dec6_12_ ( + .C(mgt_clk), + .D(plm_tsi1_reg_dec5[12]), + .Q(plm_tsi1_reg_dec6_6107[12]), + .CLR(plm_rst) + ); + FDC plm_tsi1_reg_dec4_11_ ( + .C(mgt_clk), + .D(plm_tsi1_reg_dec3_11__1321), + .Q(plm_tsi1_reg_dec4_11__1337), + .CLR(plm_rst) + ); + FDC plm_tsi1_reg_dec4_10_ ( + .C(mgt_clk), + .D(plm_tsi1_reg_dec3_10__1323), + .Q(plm_tsi1_reg_dec4_10__1339), + .CLR(plm_rst) + ); + FDC plm_tsi1_reg_dec4_9_ ( + .C(mgt_clk), + .D(plm_tsi1_reg_dec3_9__1325), + .Q(plm_tsi1_reg_dec4_9__1341), + .CLR(plm_rst) + ); + FDC plm_tsi1_reg_dec4_8_ ( + .C(mgt_clk), + .D(plm_tsi1_reg_dec3_8__1327), + .Q(plm_tsi1_reg_dec4_8__1343), + .CLR(plm_rst) + ); + FDC plm_tsi1_reg_dec4_4_ ( + .C(mgt_clk), + .D(plm_tsi1_reg_dec3_4__1329), + .Q(plm_tsi1_reg_dec4_4__1345), + .CLR(plm_rst) + ); + FDC plm_tsi1_reg_dec4_3_ ( + .C(mgt_clk), + .D(plm_tsi1_reg_dec3_3__1331), + .Q(plm_tsi1_reg_dec4_3__1347), + .CLR(plm_rst) + ); + FDC plm_tsi1_reg_dec4_2_ ( + .C(mgt_clk), + .D(plm_tsi1_reg_dec3_2__1333), + .Q(plm_tsi1_reg_dec4_2__1349), + .CLR(plm_rst) + ); + FDC plm_tsi1_reg_dec4_1_ ( + .C(mgt_clk), + .D(plm_tsi1_reg_dec3_1__1335), + .Q(plm_tsi1_reg_dec4_1__1318), + .CLR(plm_rst) + ); + FDC plm_tsi1_reg_dly8_12_ ( + .C(mgt_clk), + .D(plm_tsi1_reg_dly7[12]), + .Q(plm_tsi1_reg_dly8[12]), + .CLR(plm_rst) + ); + FDC plm_tsi1_reg_dly8_11_ ( + .C(mgt_clk), + .D(plm_tsi1_reg_dly7[11]), + .Q(plm_tsi1_reg_dly8[11]), + .CLR(plm_rst) + ); + FDC plm_tsi1_reg_dly8_10_ ( + .C(mgt_clk), + .D(plm_tsi1_reg_dly7[10]), + .Q(plm_tsi1_reg_dly8[10]), + .CLR(plm_rst) + ); + FDC plm_tsi1_reg_dly8_9_ ( + .C(mgt_clk), + .D(plm_tsi1_reg_dly7[9]), + .Q(plm_tsi1_reg_dly8[9]), + .CLR(plm_rst) + ); + FDC plm_tsi1_reg_dly8_8_ ( + .C(mgt_clk), + .D(plm_tsi1_reg_dly7[8]), + .Q(plm_tsi1_reg_dly8[8]), + .CLR(plm_rst) + ); + FDC plm_tsi1_reg_dly8_7_ ( + .C(mgt_clk), + .D(plm_tsi1_reg_dly7[7]), + .Q(plm_tsi1_reg_dly8[7]), + .CLR(plm_rst) + ); + FDC plm_tsi1_reg_dly8_6_ ( + .C(mgt_clk), + .D(plm_tsi1_reg_dly7[6]), + .Q(plm_tsi1_reg_dly8[6]), + .CLR(plm_rst) + ); + FDC plm_tsi1_reg_dly8_5_ ( + .C(mgt_clk), + .D(plm_tsi1_reg_dly7[5]), + .Q(plm_tsi1_reg_dly8[5]), + .CLR(plm_rst) + ); + FDC plm_tsi1_reg_dly8_4_ ( + .C(mgt_clk), + .D(plm_tsi1_reg_dly7[4]), + .Q(plm_tsi1_reg_dly8[4]), + .CLR(plm_rst) + ); + FDC plm_tsi1_reg_dly8_3_ ( + .C(mgt_clk), + .D(plm_tsi1_reg_dly7[3]), + .Q(plm_tsi1_reg_dly8[3]), + .CLR(plm_rst) + ); + FDC plm_tsi1_reg_dly8_2_ ( + .C(mgt_clk), + .D(plm_tsi1_reg_dly7[2]), + .Q(plm_tsi1_reg_dly8[2]), + .CLR(plm_rst) + ); + FDC plm_tsi1_reg_dly8_1_ ( + .C(mgt_clk), + .D(plm_tsi1_reg_dly7[1]), + .Q(plm_tsi1_reg_dly8[1]), + .CLR(plm_rst) + ); + FDC plm_tsi1_reg_dly8_0_ ( + .C(mgt_clk), + .D(plm_tsi1_reg_dly7[0]), + .Q(plm_tsi1_reg_dly8[0]), + .CLR(plm_rst) + ); + FDC plm_tsi1_reg_dec7_5_ ( + .C(mgt_clk), + .D(plm_tsi1_reg_dec6[5]), + .Q(plm_tsi1_reg_dec7_5__1317), + .CLR(plm_rst) + ); + FDC plm_tsi1_reg_dly9_7_ ( + .C(mgt_clk), + .D(plm_tsi1_reg_dly8[7]), + .Q(plm_tsi1_reg_dly9[7]), + .CLR(plm_rst) + ); + FDC plm_tsi1_reg_dly9_6_ ( + .C(mgt_clk), + .D(plm_tsi1_reg_dly8[6]), + .Q(plm_tsi1_reg_dly9[6]), + .CLR(plm_rst) + ); + FDC plm_tsi1_reg_dly9_5_ ( + .C(mgt_clk), + .D(plm_tsi1_reg_dly8[5]), + .Q(plm_tsi1_reg_dly9[5]), + .CLR(plm_rst) + ); + FDC plm_tsi1_reg_dly9_4_ ( + .C(mgt_clk), + .D(plm_tsi1_reg_dly8[4]), + .Q(plm_tsi1_reg_dly9[4]), + .CLR(plm_rst) + ); + FDC plm_tsi1_reg_dly9_3_ ( + .C(mgt_clk), + .D(plm_tsi1_reg_dly8[3]), + .Q(plm_tsi1_reg_dly9[3]), + .CLR(plm_rst) + ); + FDC plm_tsi1_reg_dly9_2_ ( + .C(mgt_clk), + .D(plm_tsi1_reg_dly8[2]), + .Q(plm_tsi1_reg_dly9[2]), + .CLR(plm_rst) + ); + FDC plm_tsi1_reg_dly9_1_ ( + .C(mgt_clk), + .D(plm_tsi1_reg_dly8[1]), + .Q(plm_tsi1_reg_dly9[1]), + .CLR(plm_rst) + ); + FDC plm_tsi1_reg_dly9_0_ ( + .C(mgt_clk), + .D(plm_tsi1_reg_dly8[0]), + .Q(plm_tsi1_reg_dly9[0]), + .CLR(plm_rst) + ); + FDC plm_tsi1_reg_dly8_15_ ( + .C(mgt_clk), + .D(plm_tsi1_reg_dly7[15]), + .Q(plm_tsi1_reg_dly8[15]), + .CLR(plm_rst) + ); + FDC plm_tsi1_reg_dly8_14_ ( + .C(mgt_clk), + .D(plm_tsi1_reg_dly7[14]), + .Q(plm_tsi1_reg_dly8[14]), + .CLR(plm_rst) + ); + FDC plm_tsi1_reg_dly8_13_ ( + .C(mgt_clk), + .D(plm_tsi1_reg_dly7[13]), + .Q(plm_tsi1_reg_dly8[13]), + .CLR(plm_rst) + ); + FDC plm_tsi1_reg_dec5_1_ ( + .C(mgt_clk), + .D(plm_tsi1_reg_dec4_1__1318), + .Q(plm_tsi1_reg_dec5_1__1319), + .CLR(plm_rst) + ); + FDC plm_tsi1_reg_dec3_11_ ( + .C(mgt_clk), + .D(plm_tsi1_reg_dec2_11__1320), + .Q(plm_tsi1_reg_dec3_11__1321), + .CLR(plm_rst) + ); + FDC plm_tsi1_reg_dec3_10_ ( + .C(mgt_clk), + .D(plm_tsi1_reg_dec2_10__1322), + .Q(plm_tsi1_reg_dec3_10__1323), + .CLR(plm_rst) + ); + FDC plm_tsi1_reg_dec3_9_ ( + .C(mgt_clk), + .D(plm_tsi1_reg_dec2_9__1324), + .Q(plm_tsi1_reg_dec3_9__1325), + .CLR(plm_rst) + ); + FDC plm_tsi1_reg_dec3_8_ ( + .C(mgt_clk), + .D(plm_tsi1_reg_dec2_8__1326), + .Q(plm_tsi1_reg_dec3_8__1327), + .CLR(plm_rst) + ); + FDC plm_tsi1_reg_dec3_4_ ( + .C(mgt_clk), + .D(plm_tsi1_reg_dec2_4__1328), + .Q(plm_tsi1_reg_dec3_4__1329), + .CLR(plm_rst) + ); + FDC plm_tsi1_reg_dec3_3_ ( + .C(mgt_clk), + .D(plm_tsi1_reg_dec2_3__1330), + .Q(plm_tsi1_reg_dec3_3__1331), + .CLR(plm_rst) + ); + FDC plm_tsi1_reg_dec3_2_ ( + .C(mgt_clk), + .D(plm_tsi1_reg_dec2_2__1332), + .Q(plm_tsi1_reg_dec3_2__1333), + .CLR(plm_rst) + ); + FDC plm_tsi1_reg_dec3_1_ ( + .C(mgt_clk), + .D(plm_tsi1_reg_dec2_1__1334), + .Q(plm_tsi1_reg_dec3_1__1335), + .CLR(plm_rst) + ); + FDC plm_tsi1_reg_dly7_0_ ( + .C(mgt_clk), + .D(plm_tsi1_do[0]), + .Q(plm_tsi1_reg_dly7[0]), + .CLR(plm_rst) + ); + FDC plm_tsi1_reg_dec7_12_ ( + .C(mgt_clk), + .D(plm_tsi1_reg_dec6_6107[12]), + .Q(plm_tsi1_reg_dec7_12__1336), + .CLR(plm_rst) + ); + FDC plm_tsi1_reg_dec5_11_ ( + .C(mgt_clk), + .D(plm_tsi1_reg_dec4_11__1337), + .Q(plm_tsi1_reg_dec5_11__1338), + .CLR(plm_rst) + ); + FDC plm_tsi1_reg_dec5_10_ ( + .C(mgt_clk), + .D(plm_tsi1_reg_dec4_10__1339), + .Q(plm_tsi1_reg_dec5_10__1340), + .CLR(plm_rst) + ); + FDC plm_tsi1_reg_dec5_9_ ( + .C(mgt_clk), + .D(plm_tsi1_reg_dec4_9__1341), + .Q(plm_tsi1_reg_dec5_9__1342), + .CLR(plm_rst) + ); + FDC plm_tsi1_reg_dec5_8_ ( + .C(mgt_clk), + .D(plm_tsi1_reg_dec4_8__1343), + .Q(plm_tsi1_reg_dec5_8__1344), + .CLR(plm_rst) + ); + FDC plm_tsi1_reg_dec5_4_ ( + .C(mgt_clk), + .D(plm_tsi1_reg_dec4_4__1345), + .Q(plm_tsi1_reg_dec5_4__1346), + .CLR(plm_rst) + ); + FDC plm_tsi1_reg_dec5_3_ ( + .C(mgt_clk), + .D(plm_tsi1_reg_dec4_3__1347), + .Q(plm_tsi1_reg_dec5_3__1348), + .CLR(plm_rst) + ); + FDC plm_tsi1_reg_dec5_2_ ( + .C(mgt_clk), + .D(plm_tsi1_reg_dec4_2__1349), + .Q(plm_tsi1_reg_dec5_2__1350), + .CLR(plm_rst) + ); + FDC plm_tsi1_reg_dly7_15_ ( + .C(mgt_clk), + .D(plm_tsi1_do[15]), + .Q(plm_tsi1_reg_dly7[15]), + .CLR(plm_rst) + ); + FDC plm_tsi1_reg_dly7_14_ ( + .C(mgt_clk), + .D(plm_tsi1_do[14]), + .Q(plm_tsi1_reg_dly7[14]), + .CLR(plm_rst) + ); + FDC plm_tsi1_reg_dly7_13_ ( + .C(mgt_clk), + .D(plm_tsi1_do[13]), + .Q(plm_tsi1_reg_dly7[13]), + .CLR(plm_rst) + ); + FDC plm_tsi1_reg_dly7_12_ ( + .C(mgt_clk), + .D(plm_tsi1_do[12]), + .Q(plm_tsi1_reg_dly7[12]), + .CLR(plm_rst) + ); + FDC plm_tsi1_reg_dly7_11_ ( + .C(mgt_clk), + .D(plm_tsi1_do[11]), + .Q(plm_tsi1_reg_dly7[11]), + .CLR(plm_rst) + ); + FDC plm_tsi1_reg_dly7_10_ ( + .C(mgt_clk), + .D(plm_tsi1_do[10]), + .Q(plm_tsi1_reg_dly7[10]), + .CLR(plm_rst) + ); + FDC plm_tsi1_reg_dly7_9_ ( + .C(mgt_clk), + .D(plm_tsi1_do[9]), + .Q(plm_tsi1_reg_dly7[9]), + .CLR(plm_rst) + ); + FDC plm_tsi1_reg_dly7_8_ ( + .C(mgt_clk), + .D(plm_tsi1_do[8]), + .Q(plm_tsi1_reg_dly7[8]), + .CLR(plm_rst) + ); + FDC plm_tsi1_reg_dly7_7_ ( + .C(mgt_clk), + .D(plm_tsi1_do[7]), + .Q(plm_tsi1_reg_dly7[7]), + .CLR(plm_rst) + ); + FDC plm_tsi1_reg_dly7_6_ ( + .C(mgt_clk), + .D(plm_tsi1_do[6]), + .Q(plm_tsi1_reg_dly7[6]), + .CLR(plm_rst) + ); + FDC plm_tsi1_reg_dly7_5_ ( + .C(mgt_clk), + .D(plm_tsi1_do[5]), + .Q(plm_tsi1_reg_dly7[5]), + .CLR(plm_rst) + ); + FDC plm_tsi1_reg_dly7_4_ ( + .C(mgt_clk), + .D(plm_tsi1_do[4]), + .Q(plm_tsi1_reg_dly7[4]), + .CLR(plm_rst) + ); + FDC plm_tsi1_reg_dly7_3_ ( + .C(mgt_clk), + .D(plm_tsi1_do[3]), + .Q(plm_tsi1_reg_dly7[3]), + .CLR(plm_rst) + ); + FDC plm_tsi1_reg_dly7_2_ ( + .C(mgt_clk), + .D(plm_tsi1_do[2]), + .Q(plm_tsi1_reg_dly7[2]), + .CLR(plm_rst) + ); + FDC plm_tsi1_reg_dly7_1_ ( + .C(mgt_clk), + .D(plm_tsi1_do[1]), + .Q(plm_tsi1_reg_dly7[1]), + .CLR(plm_rst) + ); + FDCE plm_tsi1_reg_inverted ( + .CE(plm_tsi1_reg_capture_now_1352), + .C(mgt_clk), + .D(plm_tsi1_reg_capture_inv_1351), + .Q(plm_rx1_inverted), + .CLR(plm_rst) + ); + FDCE plm_tsi1_reg_lane_pad ( + .CE(plm_tsi1_reg_capture_now_1352), + .C(mgt_clk), + .D(plm_tsi1_reg_lane_pad_3), + .Q(plm_rx1_lane_pad), + .CLR(plm_rst) + ); + FDCE plm_tsi1_reg_link_pad ( + .CE(plm_tsi1_reg_capture_now_1352), + .C(mgt_clk), + .D(plm_tsi1_reg_link_pad_3), + .Q(plm_rx1_link_pad), + .CLR(plm_rst) + ); + FDCE plm_tsi1_reg_lane_num_7_ ( + .CE(plm_tsi1_reg_capture_now_1352), + .C(mgt_clk), + .D(plm_tsi1_reg_lane_num_3[7]), + .Q(plm_rx1_lane_num[7]), + .CLR(plm_rst) + ); + FDCE plm_tsi1_reg_lane_num_6_ ( + .CE(plm_tsi1_reg_capture_now_1352), + .C(mgt_clk), + .D(plm_tsi1_reg_lane_num_3[6]), + .Q(plm_rx1_lane_num[6]), + .CLR(plm_rst) + ); + FDCE plm_tsi1_reg_lane_num_5_ ( + .CE(plm_tsi1_reg_capture_now_1352), + .C(mgt_clk), + .D(plm_tsi1_reg_lane_num_3[5]), + .Q(plm_rx1_lane_num[5]), + .CLR(plm_rst) + ); + FDCE plm_tsi1_reg_lane_num_4_ ( + .CE(plm_tsi1_reg_capture_now_1352), + .C(mgt_clk), + .D(plm_tsi1_reg_lane_num_3[4]), + .Q(plm_rx1_lane_num[4]), + .CLR(plm_rst) + ); + FDCE plm_tsi1_reg_lane_num_3_ ( + .CE(plm_tsi1_reg_capture_now_1352), + .C(mgt_clk), + .D(plm_tsi1_reg_lane_num_3[3]), + .Q(plm_rx1_lane_num[3]), + .CLR(plm_rst) + ); + FDCE plm_tsi1_reg_lane_num_2_ ( + .CE(plm_tsi1_reg_capture_now_1352), + .C(mgt_clk), + .D(plm_tsi1_reg_lane_num_3[2]), + .Q(plm_rx1_lane_num[2]), + .CLR(plm_rst) + ); + FDCE plm_tsi1_reg_lane_num_1_ ( + .CE(plm_tsi1_reg_capture_now_1352), + .C(mgt_clk), + .D(plm_tsi1_reg_lane_num_3[1]), + .Q(plm_rx1_lane_num[1]), + .CLR(plm_rst) + ); + FDCE plm_tsi1_reg_lane_num_0_ ( + .CE(plm_tsi1_reg_capture_now_1352), + .C(mgt_clk), + .D(plm_tsi1_reg_lane_num_3[0]), + .Q(plm_rx1_lane_num[0]), + .CLR(plm_rst) + ); + FDCE plm_tsi1_reg_link_num_7_ ( + .CE(plm_tsi1_reg_capture_now_1352), + .C(mgt_clk), + .D(plm_tsi1_reg_link_num_3[7]), + .Q(plm_rx1_link_num[7]), + .CLR(plm_rst) + ); + FDCE plm_tsi1_reg_link_num_6_ ( + .CE(plm_tsi1_reg_capture_now_1352), + .C(mgt_clk), + .D(plm_tsi1_reg_link_num_3[6]), + .Q(plm_rx1_link_num[6]), + .CLR(plm_rst) + ); + FDCE plm_tsi1_reg_link_num_5_ ( + .CE(plm_tsi1_reg_capture_now_1352), + .C(mgt_clk), + .D(plm_tsi1_reg_link_num_3[5]), + .Q(plm_rx1_link_num[5]), + .CLR(plm_rst) + ); + FDCE plm_tsi1_reg_link_num_4_ ( + .CE(plm_tsi1_reg_capture_now_1352), + .C(mgt_clk), + .D(plm_tsi1_reg_link_num_3[4]), + .Q(plm_rx1_link_num[4]), + .CLR(plm_rst) + ); + FDCE plm_tsi1_reg_link_num_3_ ( + .CE(plm_tsi1_reg_capture_now_1352), + .C(mgt_clk), + .D(plm_tsi1_reg_link_num_3[3]), + .Q(plm_rx1_link_num[3]), + .CLR(plm_rst) + ); + FDCE plm_tsi1_reg_link_num_2_ ( + .CE(plm_tsi1_reg_capture_now_1352), + .C(mgt_clk), + .D(plm_tsi1_reg_link_num_3[2]), + .Q(plm_rx1_link_num[2]), + .CLR(plm_rst) + ); + FDCE plm_tsi1_reg_link_num_1_ ( + .CE(plm_tsi1_reg_capture_now_1352), + .C(mgt_clk), + .D(plm_tsi1_reg_link_num_3[1]), + .Q(plm_rx1_link_num[1]), + .CLR(plm_rst) + ); + FDCE plm_tsi1_reg_link_num_0_ ( + .CE(plm_tsi1_reg_capture_now_1352), + .C(mgt_clk), + .D(plm_tsi1_reg_link_num_3[0]), + .Q(plm_rx1_link_num[0]), + .CLR(plm_rst) + ); + FDCE plm_tsi1_reg_linkctrl_3_ ( + .CE(plm_tsi1_reg_capture_now_1352), + .C(mgt_clk), + .D(plm_tsi1_reg_linkctrl_3_3_), + .Q(plm_rx1_linkctrl_3_), + .CLR(plm_rst) + ); + FDCE plm_tsi1_reg_linkctrl_0_ ( + .CE(plm_tsi1_reg_capture_now_1352), + .C(mgt_clk), + .D(plm_tsi1_reg_linkctrl_3_0_), + .Q(plm_rx1_linkctrl_0_), + .CLR(plm_rst) + ); + SRL16 plm_tsi1_reg_dec8_0_I_1 ( + .D(plm_reg_com[0]), + .Q(plm_tsi1_reg_dec8_0_N_6), + .CLK(mgt_clk), + .A0(plm_tsi1_VCC_1354), + .A1(plm_tsi1_VCC_1354), + .A2(plm_tsi1_VCC_1354), + .A3(plm_tsi1_GND_1353) + ); + SRL16 plm_tsi1_reg_dec6_I_1 ( + .D(plm_rx1_des_sym[0]), + .Q(plm_tsi1_reg_dec6_N_6), + .CLK(mgt_clk), + .A0(plm_tsi1_GND_1353), + .A1(plm_tsi1_GND_1353), + .A2(plm_tsi1_VCC_1354), + .A3(plm_tsi1_GND_1353) + ); + SRL16 plm_tsi1_reg_dec1_2_I_1 ( + .D(plm_reg_t2n_4_0[0]), + .Q(plm_tsi1_reg_dec1_2_N_6), + .CLK(mgt_clk), + .A0(plm_tsi1_VCC_1354), + .A1(plm_tsi1_GND_1353), + .A2(plm_tsi1_GND_1353), + .A3(plm_tsi1_GND_1353) + ); + SRL16 plm_tsi1_reg_dec1_1_I_1 ( + .D(plm_reg_t2p_4_0[0]), + .Q(plm_tsi1_reg_dec1_1_N_6), + .CLK(mgt_clk), + .A0(plm_tsi1_VCC_1354), + .A1(plm_tsi1_GND_1353), + .A2(plm_tsi1_GND_1353), + .A3(plm_tsi1_GND_1353) + ); + SRL16 plm_tsi1_reg_dec1_0_I_1 ( + .D(plm_reg_t1n_4_0[0]), + .Q(plm_tsi1_reg_dec1_0_N_6), + .CLK(mgt_clk), + .A0(plm_tsi1_VCC_1354), + .A1(plm_tsi1_GND_1353), + .A2(plm_tsi1_GND_1353), + .A3(plm_tsi1_GND_1353) + ); + SRL16 plm_tsi1_reg_dec1_I_1 ( + .D(plm_reg_t1p_4_0[0]), + .Q(plm_tsi1_reg_dec1_N_6), + .CLK(mgt_clk), + .A0(plm_tsi1_VCC_1354), + .A1(plm_tsi1_GND_1353), + .A2(plm_tsi1_GND_1353), + .A3(plm_tsi1_GND_1353) + ); + SRL16 plm_tsi1_reg_dec8_I_1 ( + .D(plm_reg_com[1]), + .Q(plm_tsi1_reg_dec8_N_6), + .CLK(mgt_clk), + .A0(plm_tsi1_VCC_1354), + .A1(plm_tsi1_VCC_1354), + .A2(plm_tsi1_VCC_1354), + .A3(plm_tsi1_GND_1353) + ); + SRL16 plm_tsi1_reg_dec7_0_I_1 ( + .D(plm_reg_pad_4[0]), + .Q(plm_tsi1_reg_dec7_0_N_6), + .CLK(mgt_clk), + .A0(plm_tsi1_VCC_1354), + .A1(plm_tsi1_VCC_1354), + .A2(plm_tsi1_VCC_1354), + .A3(plm_tsi1_GND_1353) + ); + SRL16 plm_tsi1_reg_dec7_I_1 ( + .D(plm_reg_pad_3[1]), + .Q(plm_tsi1_reg_dec7_tmp_d_array_0[0]), + .CLK(mgt_clk), + .A0(plm_tsi1_VCC_1354), + .A1(plm_tsi1_VCC_1354), + .A2(plm_tsi1_VCC_1354), + .A3(plm_tsi1_GND_1353) + ); + SRL16 plm_tsi1_reg_dec5_I_1 ( + .D(plm_rx1_des_sym[1]), + .Q(plm_tsi1_reg_dec5_N_6), + .CLK(mgt_clk), + .A0(plm_tsi1_VCC_1354), + .A1(plm_tsi1_VCC_1354), + .A2(plm_tsi1_GND_1353), + .A3(plm_tsi1_GND_1353) + ); + VCC plm_tsi2_VCC ( + .P(plm_tsi2_VCC_1425) + ); + GND plm_tsi2_GND ( + .G(plm_tsi2_GND_1424) + ); + SRL16 plm_tsi2_D00 ( + .D(plm_rx2_raw_dat[0]), + .Q(plm_tsi2_do[0]), + .CLK(mgt_clk), + .A0(plm_tsi2_VCC_1425), + .A1(plm_tsi2_GND_1424), + .A2(plm_tsi2_VCC_1425), + .A3(plm_tsi2_GND_1424) + ); + SRL16 plm_tsi2_D01 ( + .D(plm_rx2_raw_dat[1]), + .Q(plm_tsi2_do[1]), + .CLK(mgt_clk), + .A0(plm_tsi2_VCC_1425), + .A1(plm_tsi2_GND_1424), + .A2(plm_tsi2_VCC_1425), + .A3(plm_tsi2_GND_1424) + ); + SRL16 plm_tsi2_D02 ( + .D(plm_rx2_raw_dat[2]), + .Q(plm_tsi2_do[2]), + .CLK(mgt_clk), + .A0(plm_tsi2_VCC_1425), + .A1(plm_tsi2_GND_1424), + .A2(plm_tsi2_VCC_1425), + .A3(plm_tsi2_GND_1424) + ); + SRL16 plm_tsi2_D03 ( + .D(plm_rx2_raw_dat[3]), + .Q(plm_tsi2_do[3]), + .CLK(mgt_clk), + .A0(plm_tsi2_VCC_1425), + .A1(plm_tsi2_GND_1424), + .A2(plm_tsi2_VCC_1425), + .A3(plm_tsi2_GND_1424) + ); + SRL16 plm_tsi2_D04 ( + .D(plm_rx2_raw_dat[4]), + .Q(plm_tsi2_do[4]), + .CLK(mgt_clk), + .A0(plm_tsi2_VCC_1425), + .A1(plm_tsi2_GND_1424), + .A2(plm_tsi2_VCC_1425), + .A3(plm_tsi2_GND_1424) + ); + SRL16 plm_tsi2_D05 ( + .D(plm_rx2_raw_dat[5]), + .Q(plm_tsi2_do[5]), + .CLK(mgt_clk), + .A0(plm_tsi2_VCC_1425), + .A1(plm_tsi2_GND_1424), + .A2(plm_tsi2_VCC_1425), + .A3(plm_tsi2_GND_1424) + ); + SRL16 plm_tsi2_D06 ( + .D(plm_rx2_raw_dat[6]), + .Q(plm_tsi2_do[6]), + .CLK(mgt_clk), + .A0(plm_tsi2_VCC_1425), + .A1(plm_tsi2_GND_1424), + .A2(plm_tsi2_VCC_1425), + .A3(plm_tsi2_GND_1424) + ); + SRL16 plm_tsi2_D07 ( + .D(plm_rx2_raw_dat[7]), + .Q(plm_tsi2_do[7]), + .CLK(mgt_clk), + .A0(plm_tsi2_VCC_1425), + .A1(plm_tsi2_GND_1424), + .A2(plm_tsi2_VCC_1425), + .A3(plm_tsi2_GND_1424) + ); + SRL16 plm_tsi2_D08 ( + .D(plm_rx2_raw_dat[8]), + .Q(plm_tsi2_do[8]), + .CLK(mgt_clk), + .A0(plm_tsi2_VCC_1425), + .A1(plm_tsi2_GND_1424), + .A2(plm_tsi2_VCC_1425), + .A3(plm_tsi2_GND_1424) + ); + SRL16 plm_tsi2_D09 ( + .D(plm_rx2_raw_dat[9]), + .Q(plm_tsi2_do[9]), + .CLK(mgt_clk), + .A0(plm_tsi2_VCC_1425), + .A1(plm_tsi2_GND_1424), + .A2(plm_tsi2_VCC_1425), + .A3(plm_tsi2_GND_1424) + ); + SRL16 plm_tsi2_D10 ( + .D(plm_rx2_raw_dat[10]), + .Q(plm_tsi2_do[10]), + .CLK(mgt_clk), + .A0(plm_tsi2_VCC_1425), + .A1(plm_tsi2_GND_1424), + .A2(plm_tsi2_VCC_1425), + .A3(plm_tsi2_GND_1424) + ); + SRL16 plm_tsi2_D11 ( + .D(plm_rx2_raw_dat[11]), + .Q(plm_tsi2_do[11]), + .CLK(mgt_clk), + .A0(plm_tsi2_VCC_1425), + .A1(plm_tsi2_GND_1424), + .A2(plm_tsi2_VCC_1425), + .A3(plm_tsi2_GND_1424) + ); + SRL16 plm_tsi2_D12 ( + .D(plm_rx2_raw_dat[12]), + .Q(plm_tsi2_do[12]), + .CLK(mgt_clk), + .A0(plm_tsi2_VCC_1425), + .A1(plm_tsi2_GND_1424), + .A2(plm_tsi2_VCC_1425), + .A3(plm_tsi2_GND_1424) + ); + SRL16 plm_tsi2_D13 ( + .D(plm_rx2_raw_dat[13]), + .Q(plm_tsi2_do[13]), + .CLK(mgt_clk), + .A0(plm_tsi2_VCC_1425), + .A1(plm_tsi2_GND_1424), + .A2(plm_tsi2_VCC_1425), + .A3(plm_tsi2_GND_1424) + ); + SRL16 plm_tsi2_D14 ( + .D(plm_rx2_raw_dat[14]), + .Q(plm_tsi2_do[14]), + .CLK(mgt_clk), + .A0(plm_tsi2_VCC_1425), + .A1(plm_tsi2_GND_1424), + .A2(plm_tsi2_VCC_1425), + .A3(plm_tsi2_GND_1424) + ); + SRL16 plm_tsi2_D15 ( + .D(plm_rx2_raw_dat[15]), + .Q(plm_tsi2_do[15]), + .CLK(mgt_clk), + .A0(plm_tsi2_VCC_1425), + .A1(plm_tsi2_GND_1424), + .A2(plm_tsi2_VCC_1425), + .A3(plm_tsi2_GND_1424) + ); + defparam plm_tsi2_un2_com_data_jog0.INIT = 4'h1; + LUT2 plm_tsi2_un2_com_data_jog0 ( + .I0(plm_tsi2_reg_dec8_5__1387), + .I1(plm_tsi2_reg_dec8_6__1386), + .O(plm_tsi2_un2_com_data_jog0_1) + ); + defparam plm_tsi2_un2_recent_ts1.INIT = 16'h0001; + LUT4 plm_tsi2_un2_recent_ts1 ( + .I0(plm_tsi2_reg_ts1_timer[0]), + .I1(plm_tsi2_reg_ts1_timer[1]), + .I2(plm_tsi2_reg_ts1_timer[2]), + .I3(plm_tsi2_reg_ts1_timer[3]), + .O(plm_tsi2_un2_recent_ts1_1) + ); + defparam plm_tsi2_un2_recent_ts2.INIT = 16'h0001; + LUT4 plm_tsi2_un2_recent_ts2 ( + .I0(plm_tsi2_reg_ts2_timer[0]), + .I1(plm_tsi2_reg_ts2_timer[1]), + .I2(plm_tsi2_reg_ts2_timer[2]), + .I3(plm_tsi2_reg_ts2_timer[3]), + .O(plm_tsi2_un2_recent_ts2_1) + ); + defparam plm_tsi2_com_data_jog1_2.INIT = 16'h8880; + LUT4 plm_tsi2_com_data_jog1_2 ( + .I0(plm_tsi2_reg_dec6[5]), + .I1(plm_tsi2_reg_dec6_6109[12]), + .I2(plm_tsi2_reg_dec7_12__1405), + .I3(plm_tsi2_reg_dec7_13_), + .O(plm_tsi2_com_data_jog0_2) + ); + defparam plm_tsi2_ts1_inv0_jog0_1_4.INIT = 8'h80; + LUT3_L plm_tsi2_ts1_inv0_jog0_1_4 ( + .I0(plm_tsi2_reg_dec1[1]), + .I1(plm_tsi2_reg_dec1_6108[8]), + .I2(plm_tsi2_reg_dec2_1__1403), + .LO(plm_tsi2_ts1_inv0_jog0_1_4_1359) + ); + defparam plm_tsi2_ts1_inv0_jog0_1_5.INIT = 16'h8000; + LUT4 plm_tsi2_ts1_inv0_jog0_1_5 ( + .I0(plm_tsi2_reg_dec2_8__1395), + .I1(plm_tsi2_reg_dec3_1__1404), + .I2(plm_tsi2_reg_dec3_8__1396), + .I3(plm_tsi2_reg_dec4_1__1420), + .O(plm_tsi2_ts1_inv0_jog0_1_5_1358) + ); + defparam plm_tsi2_ts2_inv0_jog0_1_4.INIT = 8'h80; + LUT3_L plm_tsi2_ts2_inv0_jog0_1_4 ( + .I0(plm_tsi2_reg_dec1[3]), + .I1(plm_tsi2_reg_dec1_6108[10]), + .I2(plm_tsi2_reg_dec2_3__1399), + .LO(plm_tsi2_ts2_inv0_jog0_1_4_1363) + ); + defparam plm_tsi2_ts2_inv0_jog0_1_5.INIT = 16'h8000; + LUT4 plm_tsi2_ts2_inv0_jog0_1_5 ( + .I0(plm_tsi2_reg_dec2_10__1391), + .I1(plm_tsi2_reg_dec3_3__1400), + .I2(plm_tsi2_reg_dec3_10__1392), + .I3(plm_tsi2_reg_dec4_3__1416), + .O(plm_tsi2_ts2_inv0_jog0_1_5_1362) + ); + defparam plm_tsi2_ts1_inv1_jog0_1_4.INIT = 8'h80; + LUT3_L plm_tsi2_ts1_inv1_jog0_1_4 ( + .I0(plm_tsi2_reg_dec1[2]), + .I1(plm_tsi2_reg_dec1_6108[9]), + .I2(plm_tsi2_reg_dec2_2__1401), + .LO(plm_tsi2_ts1_inv1_jog0_1_4_1361) + ); + defparam plm_tsi2_ts1_inv1_jog0_1_5.INIT = 16'h8000; + LUT4 plm_tsi2_ts1_inv1_jog0_1_5 ( + .I0(plm_tsi2_reg_dec2_9__1393), + .I1(plm_tsi2_reg_dec3_2__1402), + .I2(plm_tsi2_reg_dec3_9__1394), + .I3(plm_tsi2_reg_dec4_2__1418), + .O(plm_tsi2_ts1_inv1_jog0_1_5_1360) + ); + defparam plm_tsi2_ts2_inv1_jog1_1_4.INIT = 8'h80; + LUT3_L plm_tsi2_ts2_inv1_jog1_1_4 ( + .I0(plm_tsi2_reg_dec1[4]), + .I1(plm_tsi2_reg_dec1_6108[11]), + .I2(plm_tsi2_reg_dec2_4__1397), + .LO(plm_tsi2_ts2_inv1_jog1_1_4_1357) + ); + defparam plm_tsi2_ts2_inv1_jog1_1_5.INIT = 16'h8000; + LUT4 plm_tsi2_ts2_inv1_jog1_1_5 ( + .I0(plm_tsi2_reg_dec2_11__1389), + .I1(plm_tsi2_reg_dec3_4__1398), + .I2(plm_tsi2_reg_dec3_11__1390), + .I3(plm_tsi2_reg_dec4_4__1414), + .O(plm_tsi2_ts2_inv1_jog1_1_5_1356) + ); + defparam plm_tsi2_idle_pair_0_a2_0_a3_0_a2_9.INIT = 16'h0001; + LUT4 plm_tsi2_idle_pair_0_a2_0_a3_0_a2_9 ( + .I0(plm_rx2_des_dat[4]), + .I1(plm_rx2_des_dat[5]), + .I2(plm_rx2_des_dat[13]), + .I3(plm_rx2_des_dat[14]), + .O(plm_tsi2_idle_pair_0_a2_0_a3_0_a2_9_1369) + ); + defparam plm_tsi2_idle_pair_0_a2_0_a3_0_a2_10.INIT = 16'h0001; + LUT4 plm_tsi2_idle_pair_0_a2_0_a3_0_a2_10 ( + .I0(plm_rx2_des_dat[1]), + .I1(plm_rx2_des_dat[3]), + .I2(plm_rx2_des_dat[11]), + .I3(plm_rx2_des_dat[12]), + .O(plm_tsi2_idle_pair_0_a2_0_a3_0_a2_10_1368) + ); + defparam plm_tsi2_idle_pair_0_a2_0_a3_0_a2_11.INIT = 16'h0001; + LUT4 plm_tsi2_idle_pair_0_a2_0_a3_0_a2_11 ( + .I0(plm_rx2_des_dat[0]), + .I1(plm_rx2_des_dat[9]), + .I2(plm_rx2_des_dat[10]), + .I3(plm_rx2_des_dat[15]), + .O(plm_tsi2_idle_pair_0_a2_0_a3_0_a2_11_1367) + ); + defparam plm_tsi2_idle_pair_0_a2_0_a3_0_a2_12.INIT = 16'h0001; + LUT4_L plm_tsi2_idle_pair_0_a2_0_a3_0_a2_12 ( + .I0(plm_rx2_des_dat[2]), + .I1(plm_rx2_des_dat[6]), + .I2(plm_rx2_des_dat[7]), + .I3(plm_rx2_des_dat[8]), + .LO(plm_tsi2_idle_pair_0_a2_0_a3_0_a2_12_1355) + ); + defparam plm_tsi2_com_data_jog1_1.INIT = 16'hA800; + LUT4 plm_tsi2_com_data_jog1_1 ( + .I0(plm_tsi2_reg_dec5[12]), + .I1(plm_tsi2_reg_dec7_5__1388), + .I2(plm_tsi2_reg_dec7_6_), + .I3(plm_tsi2_reg_dec8_0_), + .O(plm_tsi2_com_data_jog1_1_1364) + ); + defparam plm_tsi2_com_data_jog0.INIT = 16'h4000; + LUT4 plm_tsi2_com_data_jog0 ( + .I0(plm_tsi2_un2_com_data_jog0_1), + .I1(plm_tsi2_com_data_jog0_2), + .I2(plm_tsi2_reg_dec7_5__1388), + .I3(plm_tsi2_reg_dec8_7_), + .O(plm_tsi2_com_data_jog0_1372) + ); + defparam plm_tsi2_idle_pair_0_a2_0_a3_0_a2_13.INIT = 8'h80; + LUT3_L plm_tsi2_idle_pair_0_a2_0_a3_0_a2_13 ( + .I0(plm_rx2_des_sym[0]), + .I1(plm_rx2_des_sym[1]), + .I2(plm_tsi2_idle_pair_0_a2_0_a3_0_a2_12_1355), + .LO(plm_tsi2_idle_pair_0_a2_0_a3_0_a2_13_1366) + ); + defparam plm_tsi2_reg_ts1_timer_0_sqmuxa.INIT = 8'h01; + LUT3 plm_tsi2_reg_ts1_timer_0_sqmuxa ( + .I0(plm_tsi2_un2_recent_ts1_1), + .I1(plm_rx_clear_cs), + .I2(plm_tsi2_reg_capture_ts1_1384), + .O(plm_tsi2_reg_ts1_timer_0_sqmuxa_1380) + ); + defparam plm_tsi2_reg_ts2_timer_0_sqmuxa.INIT = 8'h01; + LUT3 plm_tsi2_reg_ts2_timer_0_sqmuxa ( + .I0(plm_tsi2_un2_recent_ts2_1), + .I1(plm_rx_clear_cs), + .I2(plm_tsi2_reg_capture_ts2_1383), + .O(plm_tsi2_reg_ts2_timer_0_sqmuxa_1381) + ); + defparam plm_tsi2_ts2_inv1_jog1_1.INIT = 16'h8000; + LUT4 plm_tsi2_ts2_inv1_jog1_1 ( + .I0(plm_tsi2_reg_dec4_11__1406), + .I1(plm_tsi2_reg_dec5_4__1415), + .I2(plm_tsi2_ts2_inv1_jog1_1_4_1357), + .I3(plm_tsi2_ts2_inv1_jog1_1_5_1356), + .O(plm_tsi2_ts2_inv1_jog1_1_1371) + ); + defparam plm_tsi2_ts1_inv0_jog0_1.INIT = 16'h8000; + LUT4 plm_tsi2_ts1_inv0_jog0_1 ( + .I0(plm_tsi2_reg_dec4_8__1412), + .I1(plm_tsi2_reg_dec5_1__1421), + .I2(plm_tsi2_ts1_inv0_jog0_1_4_1359), + .I3(plm_tsi2_ts1_inv0_jog0_1_5_1358), + .O(plm_tsi2_ts1_inv0_jog0_1_1365) + ); + defparam plm_tsi2_ts1_inv1_jog0_1.INIT = 16'h8000; + LUT4 plm_tsi2_ts1_inv1_jog0_1 ( + .I0(plm_tsi2_reg_dec4_9__1410), + .I1(plm_tsi2_reg_dec5_2__1419), + .I2(plm_tsi2_ts1_inv1_jog0_1_4_1361), + .I3(plm_tsi2_ts1_inv1_jog0_1_5_1360), + .O(plm_tsi2_ts1_inv1_jog0_1_1370) + ); + defparam plm_tsi2_ts2_inv0_jog0_1.INIT = 16'h8000; + LUT4 plm_tsi2_ts2_inv0_jog0_1 ( + .I0(plm_tsi2_reg_dec4_10__1408), + .I1(plm_tsi2_reg_dec5_3__1417), + .I2(plm_tsi2_ts2_inv0_jog0_1_4_1363), + .I3(plm_tsi2_ts2_inv0_jog0_1_5_1362), + .O(plm_tsi2_ts2_inv0_jog0_1_1373) + ); + defparam plm_tsi2_ts2_inv0_jog0_0.INIT = 4'h8; + LUT2 plm_tsi2_ts2_inv0_jog0_0 ( + .I0(plm_tsi2_com_data_jog0_1372), + .I1(plm_tsi2_reg_dec5_10__1409), + .O(plm_tsi2_ts2_inv0_jog0_0_1374) + ); + defparam plm_tsi2_un7_reg_ts2_timer_axbxc3.INIT = 16'hFE01; + LUT4 plm_tsi2_un7_reg_ts2_timer_axbxc3 ( + .I0(plm_tsi2_reg_ts2_timer[0]), + .I1(plm_tsi2_reg_ts2_timer[1]), + .I2(plm_tsi2_reg_ts2_timer[2]), + .I3(plm_tsi2_reg_ts2_timer[3]), + .O(plm_tsi2_un7_reg_ts2_timer_axbxc3_1) + ); + defparam plm_tsi2_un7_reg_ts1_timer_axbxc3.INIT = 16'hFE01; + LUT4 plm_tsi2_un7_reg_ts1_timer_axbxc3 ( + .I0(plm_tsi2_reg_ts1_timer[0]), + .I1(plm_tsi2_reg_ts1_timer[1]), + .I2(plm_tsi2_reg_ts1_timer[2]), + .I3(plm_tsi2_reg_ts1_timer[3]), + .O(plm_tsi2_un7_reg_ts1_timer_axbxc3_1) + ); + defparam plm_tsi2_ts1_inv0_jog1.INIT = 16'h8000; + LUT4 plm_tsi2_ts1_inv0_jog1 ( + .I0(plm_rx2_des_t1p[1]), + .I1(plm_tsi2_com_data_jog0_2), + .I2(plm_tsi2_com_data_jog1_1_1364), + .I3(plm_tsi2_ts1_inv0_jog0_1_1365), + .O(plm_tsi2_ts1_inv0_jog1_1379) + ); + defparam plm_tsi2_ts1_inv1_jog1.INIT = 16'h8000; + LUT4 plm_tsi2_ts1_inv1_jog1 ( + .I0(plm_rx2_des_t1n[1]), + .I1(plm_tsi2_com_data_jog0_2), + .I2(plm_tsi2_com_data_jog1_1_1364), + .I3(plm_tsi2_ts1_inv1_jog0_1_1370), + .O(plm_tsi2_ts1_inv1_jog1_1378) + ); + defparam plm_tsi2_ts2_inv0_jog1.INIT = 16'h8000; + LUT4 plm_tsi2_ts2_inv0_jog1 ( + .I0(plm_rx2_des_t2p[1]), + .I1(plm_tsi2_com_data_jog0_2), + .I2(plm_tsi2_com_data_jog1_1_1364), + .I3(plm_tsi2_ts2_inv0_jog0_1_1373), + .O(plm_tsi2_ts2_inv0_jog1_1377) + ); + defparam plm_tsi2_ts2_inv1_jog1.INIT = 16'h8000; + LUT4 plm_tsi2_ts2_inv1_jog1 ( + .I0(plm_rx2_des_t2n[1]), + .I1(plm_tsi2_com_data_jog0_2), + .I2(plm_tsi2_com_data_jog1_1_1364), + .I3(plm_tsi2_ts2_inv1_jog1_1_1371), + .O(plm_tsi2_ts2_inv1_jog1_1376) + ); + defparam plm_tsi2_ts1_inv0_jog0.INIT = 8'h80; + LUT3 plm_tsi2_ts1_inv0_jog0 ( + .I0(plm_tsi2_com_data_jog0_1372), + .I1(plm_tsi2_reg_dec5_8__1413), + .I2(plm_tsi2_ts1_inv0_jog0_1_1365), + .O(plm_tsi2_ts1_inv0_jog0_1375) + ); + defparam plm_tsi2_idle_pair_0_a2_0_a3_0_a2.INIT = 16'h8000; + LUT4 plm_tsi2_idle_pair_0_a2_0_a3_0_a2 ( + .I0(plm_tsi2_idle_pair_0_a2_0_a3_0_a2_9_1369), + .I1(plm_tsi2_idle_pair_0_a2_0_a3_0_a2_10_1368), + .I2(plm_tsi2_idle_pair_0_a2_0_a3_0_a2_11_1367), + .I3(plm_tsi2_idle_pair_0_a2_0_a3_0_a2_13_1366), + .O(plm_tsi2_idle_pair) + ); + defparam plm_tsi2_what_it_is_reg_capture_inv_3_5880.INIT = 16'h007F; + LUT4 plm_tsi2_what_it_is_reg_capture_inv_3_5880 ( + .I0(plm_tsi2_com_data_jog0_1372), + .I1(plm_tsi2_reg_dec5_9__1411), + .I2(plm_tsi2_ts1_inv1_jog0_1_1370), + .I3(plm_tsi2_ts1_inv1_jog1_1378), + .O(plm_tsi2_reg_capture_inv_3_5880) + ); + defparam plm_tsi2_what_it_is_reg_capture_inv_3_5881.INIT = 16'h070F; + LUT4 plm_tsi2_what_it_is_reg_capture_inv_3_5881 ( + .I0(plm_tsi2_com_data_jog0_1372), + .I1(plm_tsi2_reg_dec5_11__1407), + .I2(plm_tsi2_ts2_inv1_jog1_1376), + .I3(plm_tsi2_ts2_inv1_jog1_1_1371), + .O(plm_tsi2_reg_capture_inv_3_5881) + ); + defparam plm_tsi2_what_it_is_reg_capture_ts2_3.INIT = 16'h002A; + LUT4 plm_tsi2_what_it_is_reg_capture_ts2_3 ( + .I0(plm_tsi2_reg_capture_inv_3_5881), + .I1(plm_tsi2_ts2_inv0_jog0_0_1374), + .I2(plm_tsi2_ts2_inv0_jog0_1_1373), + .I3(plm_tsi2_ts2_inv0_jog1_1377), + .O(plm_tsi2_reg_capture_ts2_3_0) + ); + defparam plm_tsi2_event_regs_reg_ts2_c_3.INIT = 8'h10; + LUT3_L plm_tsi2_event_regs_reg_ts2_c_3 ( + .I0(plm_tsi2_un2_recent_ts2_1), + .I1(plm_rx_clear_cs), + .I2(plm_tsi2_reg_capture_ts2_1383), + .LO(plm_tsi2_reg_ts2_c_3) + ); + defparam plm_tsi2_event_regs_reg_ts1_c_3.INIT = 8'h10; + LUT3_L plm_tsi2_event_regs_reg_ts1_c_3 ( + .I0(plm_tsi2_un2_recent_ts1_1), + .I1(plm_rx_clear_cs), + .I2(plm_tsi2_reg_capture_ts1_1384), + .LO(plm_tsi2_reg_ts1_c_3) + ); + defparam plm_tsi2_what_it_is_N_11373_i.INIT = 16'hFFF7; + LUT4_L plm_tsi2_what_it_is_N_11373_i ( + .I0(plm_tsi2_reg_capture_ts2_3_0), + .I1(plm_tsi2_reg_capture_inv_3_5880), + .I2(plm_tsi2_ts1_inv0_jog0_1375), + .I3(plm_tsi2_ts1_inv0_jog1_1379), + .LO(plm_tsi2_N_11373_i) + ); + defparam plm_tsi2_what_it_is_N_11374_i.INIT = 4'h1; + LUT1_L plm_tsi2_what_it_is_N_11374_i ( + .I0(plm_tsi2_reg_capture_ts2_3_0), + .LO(plm_tsi2_N_11374_i) + ); + defparam plm_tsi2_what_it_is_N_11375_i.INIT = 8'hFD; + LUT3_L plm_tsi2_what_it_is_N_11375_i ( + .I0(plm_tsi2_reg_capture_inv_3_5880), + .I1(plm_tsi2_ts1_inv0_jog0_1375), + .I2(plm_tsi2_ts1_inv0_jog1_1379), + .LO(plm_tsi2_N_11375_i) + ); + defparam plm_tsi2_what_it_is_N_11377_i.INIT = 16'hFFFE; + LUT4_L plm_tsi2_what_it_is_N_11377_i ( + .I0(plm_tsi2_ts1_inv0_jog1_1379), + .I1(plm_tsi2_ts1_inv1_jog1_1378), + .I2(plm_tsi2_ts2_inv0_jog1_1377), + .I3(plm_tsi2_ts2_inv1_jog1_1376), + .LO(plm_tsi2_N_11377_i) + ); + defparam plm_tsi2_what_it_is_N_11376_i.INIT = 4'h7; + LUT2_L plm_tsi2_what_it_is_N_11376_i ( + .I0(plm_tsi2_reg_capture_inv_3_5880), + .I1(plm_tsi2_reg_capture_inv_3_5881), + .LO(plm_tsi2_N_11376_i) + ); + defparam plm_tsi2_idle_hands_reg_rx_idl_c_3_0_a2_0_a2_0_a3_0_a2.INIT = 4'h8; + LUT2_L plm_tsi2_idle_hands_reg_rx_idl_c_3_0_a2_0_a2_0_a3_0_a2 ( + .I0(plm_reg_rx_idl_1_1), + .I1(plm_tsi2_idle_pair), + .LO(plm_tsi2_reg_rx_idl_c_3) + ); + defparam plm_tsi2_event_regs_reg_ts1_timer_5_f0_3_.INIT = 16'hF1F0; + LUT4_L plm_tsi2_event_regs_reg_ts1_timer_5_f0_3_ ( + .I0(plm_tsi2_un2_recent_ts1_1), + .I1(plm_rx_clear_cs), + .I2(plm_tsi2_reg_capture_ts1_1384), + .I3(plm_tsi2_un7_reg_ts1_timer_axbxc3_1), + .LO(plm_tsi2_reg_ts1_timer_5[3]) + ); + defparam plm_tsi2_event_regs_reg_ts1_timer_5_2_.INIT = 16'hE100; + LUT4_L plm_tsi2_event_regs_reg_ts1_timer_5_2_ ( + .I0(plm_tsi2_reg_ts1_timer[0]), + .I1(plm_tsi2_reg_ts1_timer[1]), + .I2(plm_tsi2_reg_ts1_timer[2]), + .I3(plm_tsi2_reg_ts1_timer_0_sqmuxa_1380), + .LO(plm_tsi2_reg_ts1_timer_5[2]) + ); + defparam plm_tsi2_event_regs_reg_ts1_timer_5_1_.INIT = 8'h90; + LUT3_L plm_tsi2_event_regs_reg_ts1_timer_5_1_ ( + .I0(plm_tsi2_reg_ts1_timer[0]), + .I1(plm_tsi2_reg_ts1_timer[1]), + .I2(plm_tsi2_reg_ts1_timer_0_sqmuxa_1380), + .LO(plm_tsi2_reg_ts1_timer_5[1]) + ); + defparam plm_tsi2_event_regs_reg_ts1_timer_5_0_.INIT = 4'h4; + LUT2_L plm_tsi2_event_regs_reg_ts1_timer_5_0_ ( + .I0(plm_tsi2_reg_ts1_timer[0]), + .I1(plm_tsi2_reg_ts1_timer_0_sqmuxa_1380), + .LO(plm_tsi2_reg_ts1_timer_5[0]) + ); + defparam plm_tsi2_event_regs_reg_ts2_timer_5_f0_3_.INIT = 16'hF1F0; + LUT4_L plm_tsi2_event_regs_reg_ts2_timer_5_f0_3_ ( + .I0(plm_tsi2_un2_recent_ts2_1), + .I1(plm_rx_clear_cs), + .I2(plm_tsi2_reg_capture_ts2_1383), + .I3(plm_tsi2_un7_reg_ts2_timer_axbxc3_1), + .LO(plm_tsi2_reg_ts2_timer_5[3]) + ); + defparam plm_tsi2_event_regs_reg_ts2_timer_5_2_.INIT = 16'hE100; + LUT4_L plm_tsi2_event_regs_reg_ts2_timer_5_2_ ( + .I0(plm_tsi2_reg_ts2_timer[0]), + .I1(plm_tsi2_reg_ts2_timer[1]), + .I2(plm_tsi2_reg_ts2_timer[2]), + .I3(plm_tsi2_reg_ts2_timer_0_sqmuxa_1381), + .LO(plm_tsi2_reg_ts2_timer_5[2]) + ); + defparam plm_tsi2_event_regs_reg_ts2_timer_5_1_.INIT = 8'h90; + LUT3_L plm_tsi2_event_regs_reg_ts2_timer_5_1_ ( + .I0(plm_tsi2_reg_ts2_timer[0]), + .I1(plm_tsi2_reg_ts2_timer[1]), + .I2(plm_tsi2_reg_ts2_timer_0_sqmuxa_1381), + .LO(plm_tsi2_reg_ts2_timer_5[1]) + ); + defparam plm_tsi2_event_regs_reg_ts2_timer_5_0_.INIT = 4'h4; + LUT2_L plm_tsi2_event_regs_reg_ts2_timer_5_0_ ( + .I0(plm_tsi2_reg_ts2_timer[0]), + .I1(plm_tsi2_reg_ts2_timer_0_sqmuxa_1381), + .LO(plm_tsi2_reg_ts2_timer_5[0]) + ); + defparam plm_tsi2_holding_regs_reg_lane_pad_3_0.INIT = 8'hD8; + LUT3_L plm_tsi2_holding_regs_reg_lane_pad_3_0 ( + .I0(plm_tsi2_reg_capture_jog_1385), + .I1(plm_tsi2_reg_dec8_6__1386), + .I2(plm_tsi2_reg_dec8_13__1382), + .LO(plm_tsi2_reg_lane_pad_3) + ); + defparam plm_tsi2_holding_regs_reg_link_pad_3_0.INIT = 8'hD8; + LUT3_L plm_tsi2_holding_regs_reg_link_pad_3_0 ( + .I0(plm_tsi2_reg_capture_jog_1385), + .I1(plm_tsi2_reg_dec8_13__1382), + .I2(plm_tsi2_reg_dec9[6]), + .LO(plm_tsi2_reg_link_pad_3) + ); + defparam plm_tsi2_holding_regs_reg_lane_num_3_7_.INIT = 16'h596A; + LUT4_L plm_tsi2_holding_regs_reg_lane_num_3_7_ ( + .I0(plm_tsi2_reg_capture_inv_1422), + .I1(plm_tsi2_reg_capture_jog_1385), + .I2(plm_tsi2_reg_dly8[7]), + .I3(plm_tsi2_reg_dly8[15]), + .LO(plm_tsi2_reg_lane_num_3[7]) + ); + defparam plm_tsi2_holding_regs_reg_lane_num_3_6_.INIT = 16'h596A; + LUT4_L plm_tsi2_holding_regs_reg_lane_num_3_6_ ( + .I0(plm_tsi2_reg_capture_inv_1422), + .I1(plm_tsi2_reg_capture_jog_1385), + .I2(plm_tsi2_reg_dly8[6]), + .I3(plm_tsi2_reg_dly8[14]), + .LO(plm_tsi2_reg_lane_num_3[6]) + ); + defparam plm_tsi2_holding_regs_reg_lane_num_3_5_.INIT = 16'h596A; + LUT4_L plm_tsi2_holding_regs_reg_lane_num_3_5_ ( + .I0(plm_tsi2_reg_capture_inv_1422), + .I1(plm_tsi2_reg_capture_jog_1385), + .I2(plm_tsi2_reg_dly8[5]), + .I3(plm_tsi2_reg_dly8[13]), + .LO(plm_tsi2_reg_lane_num_3[5]) + ); + defparam plm_tsi2_holding_regs_reg_lane_num_3_4_.INIT = 16'h596A; + LUT4_L plm_tsi2_holding_regs_reg_lane_num_3_4_ ( + .I0(plm_tsi2_reg_capture_inv_1422), + .I1(plm_tsi2_reg_capture_jog_1385), + .I2(plm_tsi2_reg_dly8[4]), + .I3(plm_tsi2_reg_dly8[12]), + .LO(plm_tsi2_reg_lane_num_3[4]) + ); + defparam plm_tsi2_holding_regs_reg_lane_num_3_3_.INIT = 16'h596A; + LUT4_L plm_tsi2_holding_regs_reg_lane_num_3_3_ ( + .I0(plm_tsi2_reg_capture_inv_1422), + .I1(plm_tsi2_reg_capture_jog_1385), + .I2(plm_tsi2_reg_dly8[3]), + .I3(plm_tsi2_reg_dly8[11]), + .LO(plm_tsi2_reg_lane_num_3[3]) + ); + defparam plm_tsi2_holding_regs_reg_lane_num_3_2_.INIT = 16'h596A; + LUT4_L plm_tsi2_holding_regs_reg_lane_num_3_2_ ( + .I0(plm_tsi2_reg_capture_inv_1422), + .I1(plm_tsi2_reg_capture_jog_1385), + .I2(plm_tsi2_reg_dly8[2]), + .I3(plm_tsi2_reg_dly8[10]), + .LO(plm_tsi2_reg_lane_num_3[2]) + ); + defparam plm_tsi2_holding_regs_reg_lane_num_3_1_.INIT = 16'h596A; + LUT4_L plm_tsi2_holding_regs_reg_lane_num_3_1_ ( + .I0(plm_tsi2_reg_capture_inv_1422), + .I1(plm_tsi2_reg_capture_jog_1385), + .I2(plm_tsi2_reg_dly8[1]), + .I3(plm_tsi2_reg_dly8[9]), + .LO(plm_tsi2_reg_lane_num_3[1]) + ); + defparam plm_tsi2_holding_regs_reg_lane_num_3_0_.INIT = 16'h596A; + LUT4_L plm_tsi2_holding_regs_reg_lane_num_3_0_ ( + .I0(plm_tsi2_reg_capture_inv_1422), + .I1(plm_tsi2_reg_capture_jog_1385), + .I2(plm_tsi2_reg_dly8[0]), + .I3(plm_tsi2_reg_dly8[8]), + .LO(plm_tsi2_reg_lane_num_3[0]) + ); + defparam plm_tsi2_holding_regs_reg_link_num_3_7_.INIT = 16'h596A; + LUT4_L plm_tsi2_holding_regs_reg_link_num_3_7_ ( + .I0(plm_tsi2_reg_capture_inv_1422), + .I1(plm_tsi2_reg_capture_jog_1385), + .I2(plm_tsi2_reg_dly8[15]), + .I3(plm_tsi2_reg_dly9[7]), + .LO(plm_tsi2_reg_link_num_3[7]) + ); + defparam plm_tsi2_holding_regs_reg_link_num_3_6_.INIT = 16'h596A; + LUT4_L plm_tsi2_holding_regs_reg_link_num_3_6_ ( + .I0(plm_tsi2_reg_capture_inv_1422), + .I1(plm_tsi2_reg_capture_jog_1385), + .I2(plm_tsi2_reg_dly8[14]), + .I3(plm_tsi2_reg_dly9[6]), + .LO(plm_tsi2_reg_link_num_3[6]) + ); + defparam plm_tsi2_holding_regs_reg_link_num_3_5_.INIT = 16'h596A; + LUT4_L plm_tsi2_holding_regs_reg_link_num_3_5_ ( + .I0(plm_tsi2_reg_capture_inv_1422), + .I1(plm_tsi2_reg_capture_jog_1385), + .I2(plm_tsi2_reg_dly8[13]), + .I3(plm_tsi2_reg_dly9[5]), + .LO(plm_tsi2_reg_link_num_3[5]) + ); + defparam plm_tsi2_holding_regs_reg_link_num_3_4_.INIT = 16'h596A; + LUT4_L plm_tsi2_holding_regs_reg_link_num_3_4_ ( + .I0(plm_tsi2_reg_capture_inv_1422), + .I1(plm_tsi2_reg_capture_jog_1385), + .I2(plm_tsi2_reg_dly8[12]), + .I3(plm_tsi2_reg_dly9[4]), + .LO(plm_tsi2_reg_link_num_3[4]) + ); + defparam plm_tsi2_holding_regs_reg_link_num_3_3_.INIT = 16'h596A; + LUT4_L plm_tsi2_holding_regs_reg_link_num_3_3_ ( + .I0(plm_tsi2_reg_capture_inv_1422), + .I1(plm_tsi2_reg_capture_jog_1385), + .I2(plm_tsi2_reg_dly8[11]), + .I3(plm_tsi2_reg_dly9[3]), + .LO(plm_tsi2_reg_link_num_3[3]) + ); + defparam plm_tsi2_holding_regs_reg_link_num_3_2_.INIT = 16'h596A; + LUT4_L plm_tsi2_holding_regs_reg_link_num_3_2_ ( + .I0(plm_tsi2_reg_capture_inv_1422), + .I1(plm_tsi2_reg_capture_jog_1385), + .I2(plm_tsi2_reg_dly8[10]), + .I3(plm_tsi2_reg_dly9[2]), + .LO(plm_tsi2_reg_link_num_3[2]) + ); + defparam plm_tsi2_holding_regs_reg_link_num_3_1_.INIT = 16'h596A; + LUT4_L plm_tsi2_holding_regs_reg_link_num_3_1_ ( + .I0(plm_tsi2_reg_capture_inv_1422), + .I1(plm_tsi2_reg_capture_jog_1385), + .I2(plm_tsi2_reg_dly8[9]), + .I3(plm_tsi2_reg_dly9[1]), + .LO(plm_tsi2_reg_link_num_3[1]) + ); + defparam plm_tsi2_holding_regs_reg_link_num_3_0_.INIT = 16'h596A; + LUT4_L plm_tsi2_holding_regs_reg_link_num_3_0_ ( + .I0(plm_tsi2_reg_capture_inv_1422), + .I1(plm_tsi2_reg_capture_jog_1385), + .I2(plm_tsi2_reg_dly8[8]), + .I3(plm_tsi2_reg_dly9[0]), + .LO(plm_tsi2_reg_link_num_3[0]) + ); + defparam plm_tsi2_holding_regs_reg_linkctrl_3_3_.INIT = 16'h636C; + LUT4_L plm_tsi2_holding_regs_reg_linkctrl_3_3_ ( + .I0(plm_tsi2_do[11]), + .I1(plm_tsi2_reg_capture_inv_1422), + .I2(plm_tsi2_reg_capture_jog_1385), + .I3(plm_tsi2_reg_dly7[3]), + .LO(plm_tsi2_reg_linkctrl_3_3_) + ); + defparam plm_tsi2_holding_regs_reg_linkctrl_3_0_.INIT = 16'h636C; + LUT4_L plm_tsi2_holding_regs_reg_linkctrl_3_0_ ( + .I0(plm_tsi2_do[8]), + .I1(plm_tsi2_reg_capture_inv_1422), + .I2(plm_tsi2_reg_capture_jog_1385), + .I3(plm_tsi2_reg_dly7[0]), + .LO(plm_tsi2_reg_linkctrl_3_0_) + ); + FD plm_tsi2_reg_dec8_0_DOUT_0_ ( + .C(mgt_clk), + .D(plm_tsi2_reg_dec8_0_N_6), + .Q(plm_tsi2_reg_dec8_0_DOUT[0]) + ); + FD plm_tsi2_reg_dec6_DOUT_0_ ( + .C(mgt_clk), + .D(plm_tsi2_reg_dec6_N_6), + .Q(plm_tsi2_reg_dec6_DOUT[0]) + ); + FD plm_tsi2_reg_dec1_2_DOUT_0_ ( + .C(mgt_clk), + .D(plm_tsi2_reg_dec1_2_N_6), + .Q(plm_tsi2_reg_dec1_2_DOUT[0]) + ); + FD plm_tsi2_reg_dec1_1_DOUT_0_ ( + .C(mgt_clk), + .D(plm_tsi2_reg_dec1_1_N_6), + .Q(plm_tsi2_reg_dec1_1_DOUT[0]) + ); + FD plm_tsi2_reg_dec1_0_DOUT_0_ ( + .C(mgt_clk), + .D(plm_tsi2_reg_dec1_0_N_6), + .Q(plm_tsi2_reg_dec1_0_DOUT[0]) + ); + FD plm_tsi2_reg_dec1_DOUT_0_ ( + .C(mgt_clk), + .D(plm_tsi2_reg_dec1_N_6), + .Q(plm_tsi2_reg_dec1_DOUT[0]) + ); + FD plm_tsi2_reg_dec8_DOUT_0_ ( + .C(mgt_clk), + .D(plm_tsi2_reg_dec8_N_6), + .Q(plm_tsi2_reg_dec8_DOUT[0]) + ); + FD plm_tsi2_reg_dec7_0_DOUT_0_ ( + .C(mgt_clk), + .D(plm_tsi2_reg_dec7_0_N_6), + .Q(plm_tsi2_reg_dec7_0_DOUT[0]) + ); + FD plm_tsi2_reg_dec7_DOUT_0_ ( + .C(mgt_clk), + .D(plm_tsi2_reg_dec7_N_6), + .Q(plm_tsi2_reg_dec7_DOUT[0]) + ); + FD plm_tsi2_reg_dec5_DOUT_0_ ( + .C(mgt_clk), + .D(plm_tsi2_reg_dec5_N_6), + .Q(plm_tsi2_reg_dec5_DOUT[0]) + ); + FDC plm_tsi2_reg_dec8_13_ ( + .C(mgt_clk), + .D(plm_tsi2_reg_dec7_13_), + .Q(plm_tsi2_reg_dec8_13__1382), + .CLR(plm_rst) + ); + FDC plm_tsi2_reg_dec9_6_ ( + .C(mgt_clk), + .D(plm_tsi2_reg_dec8_6__1386), + .Q(plm_tsi2_reg_dec9[6]), + .CLR(plm_rst) + ); + FDC plm_tsi2_reg_rx_idl_1 ( + .C(mgt_clk), + .D(plm_tsi2_idle_pair), + .Q(plm_reg_rx_idl_1_1), + .CLR(plm_rst) + ); + FDC plm_tsi2_reg_ts2_c ( + .C(mgt_clk), + .D(plm_tsi2_reg_ts2_c_3), + .Q(plm_rx2_ts2_c), + .CLR(plm_rst) + ); + FDC plm_tsi2_reg_ts1_c ( + .C(mgt_clk), + .D(plm_tsi2_reg_ts1_c_3), + .Q(plm_rx2_ts1_c), + .CLR(plm_rst) + ); + FDC plm_tsi2_reg_ts2_1 ( + .C(mgt_clk), + .D(plm_tsi2_reg_capture_ts2_1383), + .Q(plm_reg_ts2_1_1), + .CLR(plm_rst) + ); + FDC plm_tsi2_reg_ts1_1 ( + .C(mgt_clk), + .D(plm_tsi2_reg_capture_ts1_1384), + .Q(plm_reg_ts1_1_1), + .CLR(plm_rst) + ); + FDC plm_tsi2_reg_capture_now ( + .C(mgt_clk), + .D(plm_tsi2_N_11373_i), + .Q(plm_tsi2_reg_capture_now_1423), + .CLR(plm_rst) + ); + FDC plm_tsi2_reg_capture_ts2 ( + .C(mgt_clk), + .D(plm_tsi2_N_11374_i), + .Q(plm_tsi2_reg_capture_ts2_1383), + .CLR(plm_rst) + ); + FDC plm_tsi2_reg_capture_ts1 ( + .C(mgt_clk), + .D(plm_tsi2_N_11375_i), + .Q(plm_tsi2_reg_capture_ts1_1384), + .CLR(plm_rst) + ); + FDC plm_tsi2_reg_capture_jog ( + .C(mgt_clk), + .D(plm_tsi2_N_11377_i), + .Q(plm_tsi2_reg_capture_jog_1385), + .CLR(plm_rst) + ); + FDC plm_tsi2_reg_capture_inv ( + .C(mgt_clk), + .D(plm_tsi2_N_11376_i), + .Q(plm_tsi2_reg_capture_inv_1422), + .CLR(plm_rst) + ); + FDC plm_tsi2_reg_rx_idl_c ( + .C(mgt_clk), + .D(plm_tsi2_reg_rx_idl_c_3), + .Q(plm_rx2_idl_c), + .CLR(plm_rst) + ); + FDC plm_tsi2_reg_ts1_timer_3_ ( + .C(mgt_clk), + .D(plm_tsi2_reg_ts1_timer_5[3]), + .Q(plm_tsi2_reg_ts1_timer[3]), + .CLR(plm_rst) + ); + FDC plm_tsi2_reg_ts1_timer_2_ ( + .C(mgt_clk), + .D(plm_tsi2_reg_ts1_timer_5[2]), + .Q(plm_tsi2_reg_ts1_timer[2]), + .CLR(plm_rst) + ); + FDC plm_tsi2_reg_ts1_timer_1_ ( + .C(mgt_clk), + .D(plm_tsi2_reg_ts1_timer_5[1]), + .Q(plm_tsi2_reg_ts1_timer[1]), + .CLR(plm_rst) + ); + FDC plm_tsi2_reg_ts1_timer_0_ ( + .C(mgt_clk), + .D(plm_tsi2_reg_ts1_timer_5[0]), + .Q(plm_tsi2_reg_ts1_timer[0]), + .CLR(plm_rst) + ); + FDC plm_tsi2_reg_ts2_timer_3_ ( + .C(mgt_clk), + .D(plm_tsi2_reg_ts2_timer_5[3]), + .Q(plm_tsi2_reg_ts2_timer[3]), + .CLR(plm_rst) + ); + FDC plm_tsi2_reg_ts2_timer_2_ ( + .C(mgt_clk), + .D(plm_tsi2_reg_ts2_timer_5[2]), + .Q(plm_tsi2_reg_ts2_timer[2]), + .CLR(plm_rst) + ); + FDC plm_tsi2_reg_ts2_timer_1_ ( + .C(mgt_clk), + .D(plm_tsi2_reg_ts2_timer_5[1]), + .Q(plm_tsi2_reg_ts2_timer[1]), + .CLR(plm_rst) + ); + FDC plm_tsi2_reg_ts2_timer_0_ ( + .C(mgt_clk), + .D(plm_tsi2_reg_ts2_timer_5[0]), + .Q(plm_tsi2_reg_ts2_timer[0]), + .CLR(plm_rst) + ); + FDC plm_tsi2_reg_dec1_11_ ( + .C(mgt_clk), + .D(plm_rx2_des_t2n[1]), + .Q(plm_tsi2_reg_dec1_6108[11]), + .CLR(plm_rst) + ); + FDC plm_tsi2_reg_dec1_10_ ( + .C(mgt_clk), + .D(plm_rx2_des_t2p[1]), + .Q(plm_tsi2_reg_dec1_6108[10]), + .CLR(plm_rst) + ); + FDC plm_tsi2_reg_dec1_9_ ( + .C(mgt_clk), + .D(plm_rx2_des_t1n[1]), + .Q(plm_tsi2_reg_dec1_6108[9]), + .CLR(plm_rst) + ); + FDC plm_tsi2_reg_dec1_8_ ( + .C(mgt_clk), + .D(plm_rx2_des_t1p[1]), + .Q(plm_tsi2_reg_dec1_6108[8]), + .CLR(plm_rst) + ); + FDC plm_tsi2_reg_dec8_6_ ( + .C(mgt_clk), + .D(plm_tsi2_reg_dec7_6_), + .Q(plm_tsi2_reg_dec8_6__1386), + .CLR(plm_rst) + ); + FDC plm_tsi2_reg_dec8_5_ ( + .C(mgt_clk), + .D(plm_tsi2_reg_dec7_5__1388), + .Q(plm_tsi2_reg_dec8_5__1387), + .CLR(plm_rst) + ); + FDC plm_tsi2_reg_dec4_11_ ( + .C(mgt_clk), + .D(plm_tsi2_reg_dec3_11__1390), + .Q(plm_tsi2_reg_dec4_11__1406), + .CLR(plm_rst) + ); + FDC plm_tsi2_reg_dec4_10_ ( + .C(mgt_clk), + .D(plm_tsi2_reg_dec3_10__1392), + .Q(plm_tsi2_reg_dec4_10__1408), + .CLR(plm_rst) + ); + FDC plm_tsi2_reg_dec4_9_ ( + .C(mgt_clk), + .D(plm_tsi2_reg_dec3_9__1394), + .Q(plm_tsi2_reg_dec4_9__1410), + .CLR(plm_rst) + ); + FDC plm_tsi2_reg_dec4_8_ ( + .C(mgt_clk), + .D(plm_tsi2_reg_dec3_8__1396), + .Q(plm_tsi2_reg_dec4_8__1412), + .CLR(plm_rst) + ); + FDC plm_tsi2_reg_dec4_4_ ( + .C(mgt_clk), + .D(plm_tsi2_reg_dec3_4__1398), + .Q(plm_tsi2_reg_dec4_4__1414), + .CLR(plm_rst) + ); + FDC plm_tsi2_reg_dec4_3_ ( + .C(mgt_clk), + .D(plm_tsi2_reg_dec3_3__1400), + .Q(plm_tsi2_reg_dec4_3__1416), + .CLR(plm_rst) + ); + FDC plm_tsi2_reg_dec4_2_ ( + .C(mgt_clk), + .D(plm_tsi2_reg_dec3_2__1402), + .Q(plm_tsi2_reg_dec4_2__1418), + .CLR(plm_rst) + ); + FDC plm_tsi2_reg_dec4_1_ ( + .C(mgt_clk), + .D(plm_tsi2_reg_dec3_1__1404), + .Q(plm_tsi2_reg_dec4_1__1420), + .CLR(plm_rst) + ); + FDC plm_tsi2_reg_dec6_12_ ( + .C(mgt_clk), + .D(plm_tsi2_reg_dec5[12]), + .Q(plm_tsi2_reg_dec6_6109[12]), + .CLR(plm_rst) + ); + FDC plm_tsi2_reg_dly8_10_ ( + .C(mgt_clk), + .D(plm_tsi2_reg_dly7[10]), + .Q(plm_tsi2_reg_dly8[10]), + .CLR(plm_rst) + ); + FDC plm_tsi2_reg_dly8_9_ ( + .C(mgt_clk), + .D(plm_tsi2_reg_dly7[9]), + .Q(plm_tsi2_reg_dly8[9]), + .CLR(plm_rst) + ); + FDC plm_tsi2_reg_dly8_8_ ( + .C(mgt_clk), + .D(plm_tsi2_reg_dly7[8]), + .Q(plm_tsi2_reg_dly8[8]), + .CLR(plm_rst) + ); + FDC plm_tsi2_reg_dly8_7_ ( + .C(mgt_clk), + .D(plm_tsi2_reg_dly7[7]), + .Q(plm_tsi2_reg_dly8[7]), + .CLR(plm_rst) + ); + FDC plm_tsi2_reg_dly8_6_ ( + .C(mgt_clk), + .D(plm_tsi2_reg_dly7[6]), + .Q(plm_tsi2_reg_dly8[6]), + .CLR(plm_rst) + ); + FDC plm_tsi2_reg_dly8_5_ ( + .C(mgt_clk), + .D(plm_tsi2_reg_dly7[5]), + .Q(plm_tsi2_reg_dly8[5]), + .CLR(plm_rst) + ); + FDC plm_tsi2_reg_dly8_4_ ( + .C(mgt_clk), + .D(plm_tsi2_reg_dly7[4]), + .Q(plm_tsi2_reg_dly8[4]), + .CLR(plm_rst) + ); + FDC plm_tsi2_reg_dly8_3_ ( + .C(mgt_clk), + .D(plm_tsi2_reg_dly7[3]), + .Q(plm_tsi2_reg_dly8[3]), + .CLR(plm_rst) + ); + FDC plm_tsi2_reg_dly8_2_ ( + .C(mgt_clk), + .D(plm_tsi2_reg_dly7[2]), + .Q(plm_tsi2_reg_dly8[2]), + .CLR(plm_rst) + ); + FDC plm_tsi2_reg_dly8_1_ ( + .C(mgt_clk), + .D(plm_tsi2_reg_dly7[1]), + .Q(plm_tsi2_reg_dly8[1]), + .CLR(plm_rst) + ); + FDC plm_tsi2_reg_dly8_0_ ( + .C(mgt_clk), + .D(plm_tsi2_reg_dly7[0]), + .Q(plm_tsi2_reg_dly8[0]), + .CLR(plm_rst) + ); + FDC plm_tsi2_reg_dec2_9_ ( + .C(mgt_clk), + .D(plm_tsi2_reg_dec1_6108[9]), + .Q(plm_tsi2_reg_dec2_9__1393), + .CLR(plm_rst) + ); + FDC plm_tsi2_reg_dec2_8_ ( + .C(mgt_clk), + .D(plm_tsi2_reg_dec1_6108[8]), + .Q(plm_tsi2_reg_dec2_8__1395), + .CLR(plm_rst) + ); + FDC plm_tsi2_reg_dec2_4_ ( + .C(mgt_clk), + .D(plm_tsi2_reg_dec1[4]), + .Q(plm_tsi2_reg_dec2_4__1397), + .CLR(plm_rst) + ); + FDC plm_tsi2_reg_dec2_3_ ( + .C(mgt_clk), + .D(plm_tsi2_reg_dec1[3]), + .Q(plm_tsi2_reg_dec2_3__1399), + .CLR(plm_rst) + ); + FDC plm_tsi2_reg_dec2_2_ ( + .C(mgt_clk), + .D(plm_tsi2_reg_dec1[2]), + .Q(plm_tsi2_reg_dec2_2__1401), + .CLR(plm_rst) + ); + FDC plm_tsi2_reg_dec2_1_ ( + .C(mgt_clk), + .D(plm_tsi2_reg_dec1[1]), + .Q(plm_tsi2_reg_dec2_1__1403), + .CLR(plm_rst) + ); + FDC plm_tsi2_reg_dly8_15_ ( + .C(mgt_clk), + .D(plm_tsi2_reg_dly7[15]), + .Q(plm_tsi2_reg_dly8[15]), + .CLR(plm_rst) + ); + FDC plm_tsi2_reg_dly8_14_ ( + .C(mgt_clk), + .D(plm_tsi2_reg_dly7[14]), + .Q(plm_tsi2_reg_dly8[14]), + .CLR(plm_rst) + ); + FDC plm_tsi2_reg_dly8_13_ ( + .C(mgt_clk), + .D(plm_tsi2_reg_dly7[13]), + .Q(plm_tsi2_reg_dly8[13]), + .CLR(plm_rst) + ); + FDC plm_tsi2_reg_dly8_12_ ( + .C(mgt_clk), + .D(plm_tsi2_reg_dly7[12]), + .Q(plm_tsi2_reg_dly8[12]), + .CLR(plm_rst) + ); + FDC plm_tsi2_reg_dly8_11_ ( + .C(mgt_clk), + .D(plm_tsi2_reg_dly7[11]), + .Q(plm_tsi2_reg_dly8[11]), + .CLR(plm_rst) + ); + FDC plm_tsi2_reg_dec7_5_ ( + .C(mgt_clk), + .D(plm_tsi2_reg_dec6[5]), + .Q(plm_tsi2_reg_dec7_5__1388), + .CLR(plm_rst) + ); + FDC plm_tsi2_reg_dly9_7_ ( + .C(mgt_clk), + .D(plm_tsi2_reg_dly8[7]), + .Q(plm_tsi2_reg_dly9[7]), + .CLR(plm_rst) + ); + FDC plm_tsi2_reg_dly9_6_ ( + .C(mgt_clk), + .D(plm_tsi2_reg_dly8[6]), + .Q(plm_tsi2_reg_dly9[6]), + .CLR(plm_rst) + ); + FDC plm_tsi2_reg_dly9_5_ ( + .C(mgt_clk), + .D(plm_tsi2_reg_dly8[5]), + .Q(plm_tsi2_reg_dly9[5]), + .CLR(plm_rst) + ); + FDC plm_tsi2_reg_dly9_4_ ( + .C(mgt_clk), + .D(plm_tsi2_reg_dly8[4]), + .Q(plm_tsi2_reg_dly9[4]), + .CLR(plm_rst) + ); + FDC plm_tsi2_reg_dly9_3_ ( + .C(mgt_clk), + .D(plm_tsi2_reg_dly8[3]), + .Q(plm_tsi2_reg_dly9[3]), + .CLR(plm_rst) + ); + FDC plm_tsi2_reg_dly9_2_ ( + .C(mgt_clk), + .D(plm_tsi2_reg_dly8[2]), + .Q(plm_tsi2_reg_dly9[2]), + .CLR(plm_rst) + ); + FDC plm_tsi2_reg_dly9_1_ ( + .C(mgt_clk), + .D(plm_tsi2_reg_dly8[1]), + .Q(plm_tsi2_reg_dly9[1]), + .CLR(plm_rst) + ); + FDC plm_tsi2_reg_dly9_0_ ( + .C(mgt_clk), + .D(plm_tsi2_reg_dly8[0]), + .Q(plm_tsi2_reg_dly9[0]), + .CLR(plm_rst) + ); + FDC plm_tsi2_reg_dec2_11_ ( + .C(mgt_clk), + .D(plm_tsi2_reg_dec1_6108[11]), + .Q(plm_tsi2_reg_dec2_11__1389), + .CLR(plm_rst) + ); + FDC plm_tsi2_reg_dec2_10_ ( + .C(mgt_clk), + .D(plm_tsi2_reg_dec1_6108[10]), + .Q(plm_tsi2_reg_dec2_10__1391), + .CLR(plm_rst) + ); + FDC plm_tsi2_reg_dec3_11_ ( + .C(mgt_clk), + .D(plm_tsi2_reg_dec2_11__1389), + .Q(plm_tsi2_reg_dec3_11__1390), + .CLR(plm_rst) + ); + FDC plm_tsi2_reg_dec3_10_ ( + .C(mgt_clk), + .D(plm_tsi2_reg_dec2_10__1391), + .Q(plm_tsi2_reg_dec3_10__1392), + .CLR(plm_rst) + ); + FDC plm_tsi2_reg_dec3_9_ ( + .C(mgt_clk), + .D(plm_tsi2_reg_dec2_9__1393), + .Q(plm_tsi2_reg_dec3_9__1394), + .CLR(plm_rst) + ); + FDC plm_tsi2_reg_dec3_8_ ( + .C(mgt_clk), + .D(plm_tsi2_reg_dec2_8__1395), + .Q(plm_tsi2_reg_dec3_8__1396), + .CLR(plm_rst) + ); + FDC plm_tsi2_reg_dec3_4_ ( + .C(mgt_clk), + .D(plm_tsi2_reg_dec2_4__1397), + .Q(plm_tsi2_reg_dec3_4__1398), + .CLR(plm_rst) + ); + FDC plm_tsi2_reg_dec3_3_ ( + .C(mgt_clk), + .D(plm_tsi2_reg_dec2_3__1399), + .Q(plm_tsi2_reg_dec3_3__1400), + .CLR(plm_rst) + ); + FDC plm_tsi2_reg_dec3_2_ ( + .C(mgt_clk), + .D(plm_tsi2_reg_dec2_2__1401), + .Q(plm_tsi2_reg_dec3_2__1402), + .CLR(plm_rst) + ); + FDC plm_tsi2_reg_dec3_1_ ( + .C(mgt_clk), + .D(plm_tsi2_reg_dec2_1__1403), + .Q(plm_tsi2_reg_dec3_1__1404), + .CLR(plm_rst) + ); + FDC plm_tsi2_reg_dec7_12_ ( + .C(mgt_clk), + .D(plm_tsi2_reg_dec6_6109[12]), + .Q(plm_tsi2_reg_dec7_12__1405), + .CLR(plm_rst) + ); + FDC plm_tsi2_reg_dec5_11_ ( + .C(mgt_clk), + .D(plm_tsi2_reg_dec4_11__1406), + .Q(plm_tsi2_reg_dec5_11__1407), + .CLR(plm_rst) + ); + FDC plm_tsi2_reg_dec5_10_ ( + .C(mgt_clk), + .D(plm_tsi2_reg_dec4_10__1408), + .Q(plm_tsi2_reg_dec5_10__1409), + .CLR(plm_rst) + ); + FDC plm_tsi2_reg_dec5_9_ ( + .C(mgt_clk), + .D(plm_tsi2_reg_dec4_9__1410), + .Q(plm_tsi2_reg_dec5_9__1411), + .CLR(plm_rst) + ); + FDC plm_tsi2_reg_dec5_8_ ( + .C(mgt_clk), + .D(plm_tsi2_reg_dec4_8__1412), + .Q(plm_tsi2_reg_dec5_8__1413), + .CLR(plm_rst) + ); + FDC plm_tsi2_reg_dec5_4_ ( + .C(mgt_clk), + .D(plm_tsi2_reg_dec4_4__1414), + .Q(plm_tsi2_reg_dec5_4__1415), + .CLR(plm_rst) + ); + FDC plm_tsi2_reg_dec5_3_ ( + .C(mgt_clk), + .D(plm_tsi2_reg_dec4_3__1416), + .Q(plm_tsi2_reg_dec5_3__1417), + .CLR(plm_rst) + ); + FDC plm_tsi2_reg_dec5_2_ ( + .C(mgt_clk), + .D(plm_tsi2_reg_dec4_2__1418), + .Q(plm_tsi2_reg_dec5_2__1419), + .CLR(plm_rst) + ); + FDC plm_tsi2_reg_dec5_1_ ( + .C(mgt_clk), + .D(plm_tsi2_reg_dec4_1__1420), + .Q(plm_tsi2_reg_dec5_1__1421), + .CLR(plm_rst) + ); + FDC plm_tsi2_reg_dly7_14_ ( + .C(mgt_clk), + .D(plm_tsi2_do[14]), + .Q(plm_tsi2_reg_dly7[14]), + .CLR(plm_rst) + ); + FDC plm_tsi2_reg_dly7_13_ ( + .C(mgt_clk), + .D(plm_tsi2_do[13]), + .Q(plm_tsi2_reg_dly7[13]), + .CLR(plm_rst) + ); + FDC plm_tsi2_reg_dly7_12_ ( + .C(mgt_clk), + .D(plm_tsi2_do[12]), + .Q(plm_tsi2_reg_dly7[12]), + .CLR(plm_rst) + ); + FDC plm_tsi2_reg_dly7_11_ ( + .C(mgt_clk), + .D(plm_tsi2_do[11]), + .Q(plm_tsi2_reg_dly7[11]), + .CLR(plm_rst) + ); + FDC plm_tsi2_reg_dly7_10_ ( + .C(mgt_clk), + .D(plm_tsi2_do[10]), + .Q(plm_tsi2_reg_dly7[10]), + .CLR(plm_rst) + ); + FDC plm_tsi2_reg_dly7_9_ ( + .C(mgt_clk), + .D(plm_tsi2_do[9]), + .Q(plm_tsi2_reg_dly7[9]), + .CLR(plm_rst) + ); + FDC plm_tsi2_reg_dly7_8_ ( + .C(mgt_clk), + .D(plm_tsi2_do[8]), + .Q(plm_tsi2_reg_dly7[8]), + .CLR(plm_rst) + ); + FDC plm_tsi2_reg_dly7_7_ ( + .C(mgt_clk), + .D(plm_tsi2_do[7]), + .Q(plm_tsi2_reg_dly7[7]), + .CLR(plm_rst) + ); + FDC plm_tsi2_reg_dly7_6_ ( + .C(mgt_clk), + .D(plm_tsi2_do[6]), + .Q(plm_tsi2_reg_dly7[6]), + .CLR(plm_rst) + ); + FDC plm_tsi2_reg_dly7_5_ ( + .C(mgt_clk), + .D(plm_tsi2_do[5]), + .Q(plm_tsi2_reg_dly7[5]), + .CLR(plm_rst) + ); + FDC plm_tsi2_reg_dly7_4_ ( + .C(mgt_clk), + .D(plm_tsi2_do[4]), + .Q(plm_tsi2_reg_dly7[4]), + .CLR(plm_rst) + ); + FDC plm_tsi2_reg_dly7_3_ ( + .C(mgt_clk), + .D(plm_tsi2_do[3]), + .Q(plm_tsi2_reg_dly7[3]), + .CLR(plm_rst) + ); + FDC plm_tsi2_reg_dly7_2_ ( + .C(mgt_clk), + .D(plm_tsi2_do[2]), + .Q(plm_tsi2_reg_dly7[2]), + .CLR(plm_rst) + ); + FDC plm_tsi2_reg_dly7_1_ ( + .C(mgt_clk), + .D(plm_tsi2_do[1]), + .Q(plm_tsi2_reg_dly7[1]), + .CLR(plm_rst) + ); + FDC plm_tsi2_reg_dly7_0_ ( + .C(mgt_clk), + .D(plm_tsi2_do[0]), + .Q(plm_tsi2_reg_dly7[0]), + .CLR(plm_rst) + ); + FDC plm_tsi2_reg_dly7_15_ ( + .C(mgt_clk), + .D(plm_tsi2_do[15]), + .Q(plm_tsi2_reg_dly7[15]), + .CLR(plm_rst) + ); + FDCE plm_tsi2_reg_inverted ( + .CE(plm_tsi2_reg_capture_now_1423), + .C(mgt_clk), + .D(plm_tsi2_reg_capture_inv_1422), + .Q(plm_rx2_inverted), + .CLR(plm_rst) + ); + FDCE plm_tsi2_reg_lane_pad ( + .CE(plm_tsi2_reg_capture_now_1423), + .C(mgt_clk), + .D(plm_tsi2_reg_lane_pad_3), + .Q(plm_rx2_lane_pad), + .CLR(plm_rst) + ); + FDCE plm_tsi2_reg_link_pad ( + .CE(plm_tsi2_reg_capture_now_1423), + .C(mgt_clk), + .D(plm_tsi2_reg_link_pad_3), + .Q(plm_rx2_link_pad), + .CLR(plm_rst) + ); + FDCE plm_tsi2_reg_lane_num_7_ ( + .CE(plm_tsi2_reg_capture_now_1423), + .C(mgt_clk), + .D(plm_tsi2_reg_lane_num_3[7]), + .Q(plm_rx2_lane_num[7]), + .CLR(plm_rst) + ); + FDCE plm_tsi2_reg_lane_num_6_ ( + .CE(plm_tsi2_reg_capture_now_1423), + .C(mgt_clk), + .D(plm_tsi2_reg_lane_num_3[6]), + .Q(plm_rx2_lane_num[6]), + .CLR(plm_rst) + ); + FDCE plm_tsi2_reg_lane_num_5_ ( + .CE(plm_tsi2_reg_capture_now_1423), + .C(mgt_clk), + .D(plm_tsi2_reg_lane_num_3[5]), + .Q(plm_rx2_lane_num[5]), + .CLR(plm_rst) + ); + FDCE plm_tsi2_reg_lane_num_4_ ( + .CE(plm_tsi2_reg_capture_now_1423), + .C(mgt_clk), + .D(plm_tsi2_reg_lane_num_3[4]), + .Q(plm_rx2_lane_num[4]), + .CLR(plm_rst) + ); + FDCE plm_tsi2_reg_lane_num_3_ ( + .CE(plm_tsi2_reg_capture_now_1423), + .C(mgt_clk), + .D(plm_tsi2_reg_lane_num_3[3]), + .Q(plm_rx2_lane_num[3]), + .CLR(plm_rst) + ); + FDCE plm_tsi2_reg_lane_num_2_ ( + .CE(plm_tsi2_reg_capture_now_1423), + .C(mgt_clk), + .D(plm_tsi2_reg_lane_num_3[2]), + .Q(plm_rx2_lane_num[2]), + .CLR(plm_rst) + ); + FDCE plm_tsi2_reg_lane_num_1_ ( + .CE(plm_tsi2_reg_capture_now_1423), + .C(mgt_clk), + .D(plm_tsi2_reg_lane_num_3[1]), + .Q(plm_rx2_lane_num[1]), + .CLR(plm_rst) + ); + FDCE plm_tsi2_reg_lane_num_0_ ( + .CE(plm_tsi2_reg_capture_now_1423), + .C(mgt_clk), + .D(plm_tsi2_reg_lane_num_3[0]), + .Q(plm_rx2_lane_num[0]), + .CLR(plm_rst) + ); + FDCE plm_tsi2_reg_link_num_7_ ( + .CE(plm_tsi2_reg_capture_now_1423), + .C(mgt_clk), + .D(plm_tsi2_reg_link_num_3[7]), + .Q(plm_rx2_link_num[7]), + .CLR(plm_rst) + ); + FDCE plm_tsi2_reg_link_num_6_ ( + .CE(plm_tsi2_reg_capture_now_1423), + .C(mgt_clk), + .D(plm_tsi2_reg_link_num_3[6]), + .Q(plm_rx2_link_num[6]), + .CLR(plm_rst) + ); + FDCE plm_tsi2_reg_link_num_5_ ( + .CE(plm_tsi2_reg_capture_now_1423), + .C(mgt_clk), + .D(plm_tsi2_reg_link_num_3[5]), + .Q(plm_rx2_link_num[5]), + .CLR(plm_rst) + ); + FDCE plm_tsi2_reg_link_num_4_ ( + .CE(plm_tsi2_reg_capture_now_1423), + .C(mgt_clk), + .D(plm_tsi2_reg_link_num_3[4]), + .Q(plm_rx2_link_num[4]), + .CLR(plm_rst) + ); + FDCE plm_tsi2_reg_link_num_3_ ( + .CE(plm_tsi2_reg_capture_now_1423), + .C(mgt_clk), + .D(plm_tsi2_reg_link_num_3[3]), + .Q(plm_rx2_link_num[3]), + .CLR(plm_rst) + ); + FDCE plm_tsi2_reg_link_num_2_ ( + .CE(plm_tsi2_reg_capture_now_1423), + .C(mgt_clk), + .D(plm_tsi2_reg_link_num_3[2]), + .Q(plm_rx2_link_num[2]), + .CLR(plm_rst) + ); + FDCE plm_tsi2_reg_link_num_1_ ( + .CE(plm_tsi2_reg_capture_now_1423), + .C(mgt_clk), + .D(plm_tsi2_reg_link_num_3[1]), + .Q(plm_rx2_link_num[1]), + .CLR(plm_rst) + ); + FDCE plm_tsi2_reg_link_num_0_ ( + .CE(plm_tsi2_reg_capture_now_1423), + .C(mgt_clk), + .D(plm_tsi2_reg_link_num_3[0]), + .Q(plm_rx2_link_num[0]), + .CLR(plm_rst) + ); + FDCE plm_tsi2_reg_linkctrl_3_ ( + .CE(plm_tsi2_reg_capture_now_1423), + .C(mgt_clk), + .D(plm_tsi2_reg_linkctrl_3_3_), + .Q(plm_rx2_linkctrl_3_), + .CLR(plm_rst) + ); + FDCE plm_tsi2_reg_linkctrl_0_ ( + .CE(plm_tsi2_reg_capture_now_1423), + .C(mgt_clk), + .D(plm_tsi2_reg_linkctrl_3_0_), + .Q(plm_rx2_linkctrl_0_), + .CLR(plm_rst) + ); + SRL16 plm_tsi2_reg_dec8_0_I_1 ( + .D(plm_reg_com_0[0]), + .Q(plm_tsi2_reg_dec8_0_N_6), + .CLK(mgt_clk), + .A0(plm_tsi2_VCC_1425), + .A1(plm_tsi2_VCC_1425), + .A2(plm_tsi2_VCC_1425), + .A3(plm_tsi2_GND_1424) + ); + SRL16 plm_tsi2_reg_dec6_I_1 ( + .D(plm_rx2_des_sym[0]), + .Q(plm_tsi2_reg_dec6_N_6), + .CLK(mgt_clk), + .A0(plm_tsi2_GND_1424), + .A1(plm_tsi2_GND_1424), + .A2(plm_tsi2_VCC_1425), + .A3(plm_tsi2_GND_1424) + ); + SRL16 plm_tsi2_reg_dec1_2_I_1 ( + .D(plm_reg_t2n_4_1[0]), + .Q(plm_tsi2_reg_dec1_2_N_6), + .CLK(mgt_clk), + .A0(plm_tsi2_VCC_1425), + .A1(plm_tsi2_GND_1424), + .A2(plm_tsi2_GND_1424), + .A3(plm_tsi2_GND_1424) + ); + SRL16 plm_tsi2_reg_dec1_1_I_1 ( + .D(plm_reg_t2p_4_1[0]), + .Q(plm_tsi2_reg_dec1_1_N_6), + .CLK(mgt_clk), + .A0(plm_tsi2_VCC_1425), + .A1(plm_tsi2_GND_1424), + .A2(plm_tsi2_GND_1424), + .A3(plm_tsi2_GND_1424) + ); + SRL16 plm_tsi2_reg_dec1_0_I_1 ( + .D(plm_reg_t1n_4_1[0]), + .Q(plm_tsi2_reg_dec1_0_N_6), + .CLK(mgt_clk), + .A0(plm_tsi2_VCC_1425), + .A1(plm_tsi2_GND_1424), + .A2(plm_tsi2_GND_1424), + .A3(plm_tsi2_GND_1424) + ); + SRL16 plm_tsi2_reg_dec1_I_1 ( + .D(plm_reg_t1p_4_1[0]), + .Q(plm_tsi2_reg_dec1_N_6), + .CLK(mgt_clk), + .A0(plm_tsi2_VCC_1425), + .A1(plm_tsi2_GND_1424), + .A2(plm_tsi2_GND_1424), + .A3(plm_tsi2_GND_1424) + ); + SRL16 plm_tsi2_reg_dec8_I_1 ( + .D(plm_reg_com_0[1]), + .Q(plm_tsi2_reg_dec8_N_6), + .CLK(mgt_clk), + .A0(plm_tsi2_VCC_1425), + .A1(plm_tsi2_VCC_1425), + .A2(plm_tsi2_VCC_1425), + .A3(plm_tsi2_GND_1424) + ); + SRL16 plm_tsi2_reg_dec7_0_I_1 ( + .D(plm_reg_pad_4_0[0]), + .Q(plm_tsi2_reg_dec7_0_N_6), + .CLK(mgt_clk), + .A0(plm_tsi2_VCC_1425), + .A1(plm_tsi2_VCC_1425), + .A2(plm_tsi2_VCC_1425), + .A3(plm_tsi2_GND_1424) + ); + SRL16 plm_tsi2_reg_dec7_I_1 ( + .D(plm_reg_pad_3_0[1]), + .Q(plm_tsi2_reg_dec7_N_6), + .CLK(mgt_clk), + .A0(plm_tsi2_VCC_1425), + .A1(plm_tsi2_VCC_1425), + .A2(plm_tsi2_VCC_1425), + .A3(plm_tsi2_GND_1424) + ); + SRL16 plm_tsi2_reg_dec5_I_1 ( + .D(plm_rx2_des_sym[1]), + .Q(plm_tsi2_reg_dec5_N_6), + .CLK(mgt_clk), + .A0(plm_tsi2_VCC_1425), + .A1(plm_tsi2_VCC_1425), + .A2(plm_tsi2_GND_1424), + .A3(plm_tsi2_GND_1424) + ); + VCC plm_tsi3_VCC ( + .P(plm_tsi3_VCC_1494) + ); + GND plm_tsi3_GND ( + .G(plm_tsi3_GND_1493) + ); + SRL16 plm_tsi3_D00 ( + .D(plm_rx3_raw_dat[0]), + .Q(plm_tsi3_do[0]), + .CLK(mgt_clk), + .A0(plm_tsi3_VCC_1494), + .A1(plm_tsi3_GND_1493), + .A2(plm_tsi3_VCC_1494), + .A3(plm_tsi3_GND_1493) + ); + SRL16 plm_tsi3_D01 ( + .D(plm_rx3_raw_dat[1]), + .Q(plm_tsi3_do[1]), + .CLK(mgt_clk), + .A0(plm_tsi3_VCC_1494), + .A1(plm_tsi3_GND_1493), + .A2(plm_tsi3_VCC_1494), + .A3(plm_tsi3_GND_1493) + ); + SRL16 plm_tsi3_D02 ( + .D(plm_rx3_raw_dat[2]), + .Q(plm_tsi3_do[2]), + .CLK(mgt_clk), + .A0(plm_tsi3_VCC_1494), + .A1(plm_tsi3_GND_1493), + .A2(plm_tsi3_VCC_1494), + .A3(plm_tsi3_GND_1493) + ); + SRL16 plm_tsi3_D03 ( + .D(plm_rx3_raw_dat[3]), + .Q(plm_tsi3_do[3]), + .CLK(mgt_clk), + .A0(plm_tsi3_VCC_1494), + .A1(plm_tsi3_GND_1493), + .A2(plm_tsi3_VCC_1494), + .A3(plm_tsi3_GND_1493) + ); + SRL16 plm_tsi3_D04 ( + .D(plm_rx3_raw_dat[4]), + .Q(plm_tsi3_do[4]), + .CLK(mgt_clk), + .A0(plm_tsi3_VCC_1494), + .A1(plm_tsi3_GND_1493), + .A2(plm_tsi3_VCC_1494), + .A3(plm_tsi3_GND_1493) + ); + SRL16 plm_tsi3_D05 ( + .D(plm_rx3_raw_dat[5]), + .Q(plm_tsi3_do[5]), + .CLK(mgt_clk), + .A0(plm_tsi3_VCC_1494), + .A1(plm_tsi3_GND_1493), + .A2(plm_tsi3_VCC_1494), + .A3(plm_tsi3_GND_1493) + ); + SRL16 plm_tsi3_D06 ( + .D(plm_rx3_raw_dat[6]), + .Q(plm_tsi3_do[6]), + .CLK(mgt_clk), + .A0(plm_tsi3_VCC_1494), + .A1(plm_tsi3_GND_1493), + .A2(plm_tsi3_VCC_1494), + .A3(plm_tsi3_GND_1493) + ); + SRL16 plm_tsi3_D07 ( + .D(plm_rx3_raw_dat[7]), + .Q(plm_tsi3_do[7]), + .CLK(mgt_clk), + .A0(plm_tsi3_VCC_1494), + .A1(plm_tsi3_GND_1493), + .A2(plm_tsi3_VCC_1494), + .A3(plm_tsi3_GND_1493) + ); + SRL16 plm_tsi3_D08 ( + .D(plm_rx3_raw_dat[8]), + .Q(plm_tsi3_do[8]), + .CLK(mgt_clk), + .A0(plm_tsi3_VCC_1494), + .A1(plm_tsi3_GND_1493), + .A2(plm_tsi3_VCC_1494), + .A3(plm_tsi3_GND_1493) + ); + SRL16 plm_tsi3_D09 ( + .D(plm_rx3_raw_dat[9]), + .Q(plm_tsi3_do[9]), + .CLK(mgt_clk), + .A0(plm_tsi3_VCC_1494), + .A1(plm_tsi3_GND_1493), + .A2(plm_tsi3_VCC_1494), + .A3(plm_tsi3_GND_1493) + ); + SRL16 plm_tsi3_D10 ( + .D(plm_rx3_raw_dat[10]), + .Q(plm_tsi3_do[10]), + .CLK(mgt_clk), + .A0(plm_tsi3_VCC_1494), + .A1(plm_tsi3_GND_1493), + .A2(plm_tsi3_VCC_1494), + .A3(plm_tsi3_GND_1493) + ); + SRL16 plm_tsi3_D11 ( + .D(plm_rx3_raw_dat[11]), + .Q(plm_tsi3_do[11]), + .CLK(mgt_clk), + .A0(plm_tsi3_VCC_1494), + .A1(plm_tsi3_GND_1493), + .A2(plm_tsi3_VCC_1494), + .A3(plm_tsi3_GND_1493) + ); + SRL16 plm_tsi3_D12 ( + .D(plm_rx3_raw_dat[12]), + .Q(plm_tsi3_do[12]), + .CLK(mgt_clk), + .A0(plm_tsi3_VCC_1494), + .A1(plm_tsi3_GND_1493), + .A2(plm_tsi3_VCC_1494), + .A3(plm_tsi3_GND_1493) + ); + SRL16 plm_tsi3_D13 ( + .D(plm_rx3_raw_dat[13]), + .Q(plm_tsi3_do[13]), + .CLK(mgt_clk), + .A0(plm_tsi3_VCC_1494), + .A1(plm_tsi3_GND_1493), + .A2(plm_tsi3_VCC_1494), + .A3(plm_tsi3_GND_1493) + ); + SRL16 plm_tsi3_D14 ( + .D(plm_rx3_raw_dat[14]), + .Q(plm_tsi3_do[14]), + .CLK(mgt_clk), + .A0(plm_tsi3_VCC_1494), + .A1(plm_tsi3_GND_1493), + .A2(plm_tsi3_VCC_1494), + .A3(plm_tsi3_GND_1493) + ); + SRL16 plm_tsi3_D15 ( + .D(plm_rx3_raw_dat[15]), + .Q(plm_tsi3_do[15]), + .CLK(mgt_clk), + .A0(plm_tsi3_VCC_1494), + .A1(plm_tsi3_GND_1493), + .A2(plm_tsi3_VCC_1494), + .A3(plm_tsi3_GND_1493) + ); + defparam plm_tsi3_un2_com_data_jog0.INIT = 4'h1; + LUT2 plm_tsi3_un2_com_data_jog0 ( + .I0(plm_tsi3_reg_dec8_5__1456), + .I1(plm_tsi3_reg_dec8_6__1455), + .O(plm_tsi3_un2_com_data_jog0_2) + ); + defparam plm_tsi3_un2_recent_ts1.INIT = 16'h0001; + LUT4 plm_tsi3_un2_recent_ts1 ( + .I0(plm_tsi3_reg_ts1_timer[0]), + .I1(plm_tsi3_reg_ts1_timer[1]), + .I2(plm_tsi3_reg_ts1_timer[2]), + .I3(plm_tsi3_reg_ts1_timer[3]), + .O(plm_tsi3_un2_recent_ts1_2) + ); + defparam plm_tsi3_un2_recent_ts2.INIT = 16'h0001; + LUT4 plm_tsi3_un2_recent_ts2 ( + .I0(plm_tsi3_reg_ts2_timer[0]), + .I1(plm_tsi3_reg_ts2_timer[1]), + .I2(plm_tsi3_reg_ts2_timer[2]), + .I3(plm_tsi3_reg_ts2_timer[3]), + .O(plm_tsi3_un2_recent_ts2_2) + ); + defparam plm_tsi3_com_data_jog0_2.INIT = 16'h8880; + LUT4 plm_tsi3_com_data_jog0_2 ( + .I0(plm_tsi3_reg_dec6[5]), + .I1(plm_tsi3_reg_dec6_6111[12]), + .I2(plm_tsi3_reg_dec7_12__1474), + .I3(plm_tsi3_reg_dec7_13_), + .O(plm_tsi3_com_data_jog1_2) + ); + defparam plm_tsi3_ts1_inv1_jog1_1_4.INIT = 8'h80; + LUT3_L plm_tsi3_ts1_inv1_jog1_1_4 ( + .I0(plm_tsi3_reg_dec1[2]), + .I1(plm_tsi3_reg_dec1_6110[9]), + .I2(plm_tsi3_reg_dec2_2__1470), + .LO(plm_tsi3_ts1_inv1_jog1_1_4_1434) + ); + defparam plm_tsi3_ts1_inv1_jog1_1_5.INIT = 16'h8000; + LUT4 plm_tsi3_ts1_inv1_jog1_1_5 ( + .I0(plm_tsi3_reg_dec2_9__1462), + .I1(plm_tsi3_reg_dec3_2__1471), + .I2(plm_tsi3_reg_dec3_9__1463), + .I3(plm_tsi3_reg_dec4_2__1487), + .O(plm_tsi3_ts1_inv1_jog1_1_5_1433) + ); + defparam plm_tsi3_ts2_inv0_jog0_1_4.INIT = 8'h80; + LUT3_L plm_tsi3_ts2_inv0_jog0_1_4 ( + .I0(plm_tsi3_reg_dec1[3]), + .I1(plm_tsi3_reg_dec1_6110[10]), + .I2(plm_tsi3_reg_dec2_3__1468), + .LO(plm_tsi3_ts2_inv0_jog0_1_4_1428) + ); + defparam plm_tsi3_ts2_inv0_jog0_1_5.INIT = 16'h8000; + LUT4 plm_tsi3_ts2_inv0_jog0_1_5 ( + .I0(plm_tsi3_reg_dec2_10__1460), + .I1(plm_tsi3_reg_dec3_3__1469), + .I2(plm_tsi3_reg_dec3_10__1461), + .I3(plm_tsi3_reg_dec4_3__1485), + .O(plm_tsi3_ts2_inv0_jog0_1_5_1427) + ); + defparam plm_tsi3_ts1_inv0_jog1_1_4.INIT = 8'h80; + LUT3_L plm_tsi3_ts1_inv0_jog1_1_4 ( + .I0(plm_tsi3_reg_dec1[1]), + .I1(plm_tsi3_reg_dec1_6110[8]), + .I2(plm_tsi3_reg_dec2_1__1472), + .LO(plm_tsi3_ts1_inv0_jog1_1_4_1432) + ); + defparam plm_tsi3_ts1_inv0_jog1_1_5.INIT = 16'h8000; + LUT4 plm_tsi3_ts1_inv0_jog1_1_5 ( + .I0(plm_tsi3_reg_dec2_8__1464), + .I1(plm_tsi3_reg_dec3_1__1473), + .I2(plm_tsi3_reg_dec3_8__1465), + .I3(plm_tsi3_reg_dec4_1__1489), + .O(plm_tsi3_ts1_inv0_jog1_1_5_1431) + ); + defparam plm_tsi3_ts2_inv1_jog0_1_4.INIT = 8'h80; + LUT3_L plm_tsi3_ts2_inv1_jog0_1_4 ( + .I0(plm_tsi3_reg_dec1[4]), + .I1(plm_tsi3_reg_dec1_6110[11]), + .I2(plm_tsi3_reg_dec2_4__1466), + .LO(plm_tsi3_ts2_inv1_jog0_1_4_1430) + ); + defparam plm_tsi3_ts2_inv1_jog0_1_5.INIT = 16'h8000; + LUT4 plm_tsi3_ts2_inv1_jog0_1_5 ( + .I0(plm_tsi3_reg_dec2_11__1458), + .I1(plm_tsi3_reg_dec3_4__1467), + .I2(plm_tsi3_reg_dec3_11__1459), + .I3(plm_tsi3_reg_dec4_4__1483), + .O(plm_tsi3_ts2_inv1_jog0_1_5_1429) + ); + defparam plm_tsi3_idle_pair_0_a2_0_a2_0_a3_0_a2_9.INIT = 16'h0001; + LUT4 plm_tsi3_idle_pair_0_a2_0_a2_0_a3_0_a2_9 ( + .I0(plm_rx3_des_dat[3]), + .I1(plm_rx3_des_dat[4]), + .I2(plm_rx3_des_dat[12]), + .I3(plm_rx3_des_dat[14]), + .O(plm_tsi3_idle_pair_0_a2_0_a2_0_a3_0_a2_9_1439) + ); + defparam plm_tsi3_idle_pair_0_a2_0_a2_0_a3_0_a2_10.INIT = 16'h0001; + LUT4 plm_tsi3_idle_pair_0_a2_0_a2_0_a3_0_a2_10 ( + .I0(plm_rx3_des_dat[1]), + .I1(plm_rx3_des_dat[2]), + .I2(plm_rx3_des_dat[11]), + .I3(plm_rx3_des_dat[13]), + .O(plm_tsi3_idle_pair_0_a2_0_a2_0_a3_0_a2_10_1438) + ); + defparam plm_tsi3_idle_pair_0_a2_0_a2_0_a3_0_a2_11.INIT = 16'h0001; + LUT4 plm_tsi3_idle_pair_0_a2_0_a2_0_a3_0_a2_11 ( + .I0(plm_rx3_des_dat[0]), + .I1(plm_rx3_des_dat[9]), + .I2(plm_rx3_des_dat[10]), + .I3(plm_rx3_des_dat[15]), + .O(plm_tsi3_idle_pair_0_a2_0_a2_0_a3_0_a2_11_1437) + ); + defparam plm_tsi3_idle_pair_0_a2_0_a2_0_a3_0_a2_12.INIT = 16'h0001; + LUT4_L plm_tsi3_idle_pair_0_a2_0_a2_0_a3_0_a2_12 ( + .I0(plm_rx3_des_dat[5]), + .I1(plm_rx3_des_dat[6]), + .I2(plm_rx3_des_dat[7]), + .I3(plm_rx3_des_dat[8]), + .LO(plm_tsi3_idle_pair_0_a2_0_a2_0_a3_0_a2_12_1426) + ); + defparam plm_tsi3_com_data_jog1_1.INIT = 16'hA800; + LUT4 plm_tsi3_com_data_jog1_1 ( + .I0(plm_tsi3_reg_dec5[12]), + .I1(plm_tsi3_reg_dec7_5__1457), + .I2(plm_tsi3_reg_dec7_6_), + .I3(plm_tsi3_reg_dec8_0_), + .O(plm_tsi3_com_data_jog1_1_1435) + ); + defparam plm_tsi3_com_data_jog0.INIT = 16'h4000; + LUT4 plm_tsi3_com_data_jog0 ( + .I0(plm_tsi3_un2_com_data_jog0_2), + .I1(plm_tsi3_com_data_jog1_2), + .I2(plm_tsi3_reg_dec7_5__1457), + .I3(plm_tsi3_reg_dec8_7_), + .O(plm_tsi3_com_data_jog0_1444) + ); + defparam plm_tsi3_idle_pair_0_a2_0_a2_0_a3_0_a2_13.INIT = 8'h80; + LUT3_L plm_tsi3_idle_pair_0_a2_0_a2_0_a3_0_a2_13 ( + .I0(plm_rx3_des_sym[0]), + .I1(plm_rx3_des_sym[1]), + .I2(plm_tsi3_idle_pair_0_a2_0_a2_0_a3_0_a2_12_1426), + .LO(plm_tsi3_idle_pair_0_a2_0_a2_0_a3_0_a2_13_1436) + ); + defparam plm_tsi3_reg_ts1_timer_0_sqmuxa.INIT = 8'h01; + LUT3 plm_tsi3_reg_ts1_timer_0_sqmuxa ( + .I0(plm_tsi3_un2_recent_ts1_2), + .I1(plm_rx_clear_cs), + .I2(plm_tsi3_reg_capture_ts1_1453), + .O(plm_tsi3_reg_ts1_timer_0_sqmuxa_1449) + ); + defparam plm_tsi3_reg_ts2_timer_0_sqmuxa.INIT = 8'h01; + LUT3 plm_tsi3_reg_ts2_timer_0_sqmuxa ( + .I0(plm_tsi3_un2_recent_ts2_2), + .I1(plm_rx_clear_cs), + .I2(plm_tsi3_reg_capture_ts2_1452), + .O(plm_tsi3_reg_ts2_timer_0_sqmuxa_1450) + ); + defparam plm_tsi3_ts2_inv0_jog0_1.INIT = 16'h8000; + LUT4 plm_tsi3_ts2_inv0_jog0_1 ( + .I0(plm_tsi3_reg_dec4_10__1477), + .I1(plm_tsi3_reg_dec5_3__1486), + .I2(plm_tsi3_ts2_inv0_jog0_1_4_1428), + .I3(plm_tsi3_ts2_inv0_jog0_1_5_1427), + .O(plm_tsi3_ts2_inv0_jog0_1_1443) + ); + defparam plm_tsi3_ts2_inv1_jog0_1.INIT = 16'h8000; + LUT4 plm_tsi3_ts2_inv1_jog0_1 ( + .I0(plm_tsi3_reg_dec4_11__1475), + .I1(plm_tsi3_reg_dec5_4__1484), + .I2(plm_tsi3_ts2_inv1_jog0_1_4_1430), + .I3(plm_tsi3_ts2_inv1_jog0_1_5_1429), + .O(plm_tsi3_ts2_inv1_jog0_1_1441) + ); + defparam plm_tsi3_ts1_inv0_jog1_1.INIT = 16'h8000; + LUT4 plm_tsi3_ts1_inv0_jog1_1 ( + .I0(plm_tsi3_reg_dec4_8__1481), + .I1(plm_tsi3_reg_dec5_1__1490), + .I2(plm_tsi3_ts1_inv0_jog1_1_4_1432), + .I3(plm_tsi3_ts1_inv0_jog1_1_5_1431), + .O(plm_tsi3_ts1_inv0_jog1_1_1442) + ); + defparam plm_tsi3_ts1_inv1_jog1_1.INIT = 16'h8000; + LUT4 plm_tsi3_ts1_inv1_jog1_1 ( + .I0(plm_tsi3_reg_dec4_9__1479), + .I1(plm_tsi3_reg_dec5_2__1488), + .I2(plm_tsi3_ts1_inv1_jog1_1_4_1434), + .I3(plm_tsi3_ts1_inv1_jog1_1_5_1433), + .O(plm_tsi3_ts1_inv1_jog1_1_1440) + ); + defparam plm_tsi3_un7_reg_ts1_timer_axbxc3.INIT = 16'hFE01; + LUT4 plm_tsi3_un7_reg_ts1_timer_axbxc3 ( + .I0(plm_tsi3_reg_ts1_timer[0]), + .I1(plm_tsi3_reg_ts1_timer[1]), + .I2(plm_tsi3_reg_ts1_timer[2]), + .I3(plm_tsi3_reg_ts1_timer[3]), + .O(plm_tsi3_un7_reg_ts1_timer_axbxc3_2) + ); + defparam plm_tsi3_un7_reg_ts2_timer_axbxc3.INIT = 16'hFE01; + LUT4 plm_tsi3_un7_reg_ts2_timer_axbxc3 ( + .I0(plm_tsi3_reg_ts2_timer[0]), + .I1(plm_tsi3_reg_ts2_timer[1]), + .I2(plm_tsi3_reg_ts2_timer[2]), + .I3(plm_tsi3_reg_ts2_timer[3]), + .O(plm_tsi3_un7_reg_ts2_timer_axbxc3_2) + ); + defparam plm_tsi3_ts2_inv0_jog1.INIT = 16'h8000; + LUT4 plm_tsi3_ts2_inv0_jog1 ( + .I0(plm_rx3_des_t2p[1]), + .I1(plm_tsi3_com_data_jog1_1_1435), + .I2(plm_tsi3_com_data_jog1_2), + .I3(plm_tsi3_ts2_inv0_jog0_1_1443), + .O(plm_tsi3_ts2_inv0_jog1_1446) + ); + defparam plm_tsi3_ts2_inv1_jog1.INIT = 16'h8000; + LUT4 plm_tsi3_ts2_inv1_jog1 ( + .I0(plm_rx3_des_t2n[1]), + .I1(plm_tsi3_com_data_jog1_1_1435), + .I2(plm_tsi3_com_data_jog1_2), + .I3(plm_tsi3_ts2_inv1_jog0_1_1441), + .O(plm_tsi3_ts2_inv1_jog1_1445) + ); + defparam plm_tsi3_ts1_inv0_jog1.INIT = 16'h8000; + LUT4 plm_tsi3_ts1_inv0_jog1 ( + .I0(plm_rx3_des_t1p[1]), + .I1(plm_tsi3_com_data_jog1_1_1435), + .I2(plm_tsi3_com_data_jog1_2), + .I3(plm_tsi3_ts1_inv0_jog1_1_1442), + .O(plm_tsi3_ts1_inv0_jog1_1448) + ); + defparam plm_tsi3_ts1_inv1_jog1.INIT = 16'h8000; + LUT4 plm_tsi3_ts1_inv1_jog1 ( + .I0(plm_rx3_des_t1n[1]), + .I1(plm_tsi3_com_data_jog1_1_1435), + .I2(plm_tsi3_com_data_jog1_2), + .I3(plm_tsi3_ts1_inv1_jog1_1_1440), + .O(plm_tsi3_ts1_inv1_jog1_1447) + ); + defparam plm_tsi3_idle_pair_0_a2_0_a2_0_a3_0_a2.INIT = 16'h8000; + LUT4 plm_tsi3_idle_pair_0_a2_0_a2_0_a3_0_a2 ( + .I0(plm_tsi3_idle_pair_0_a2_0_a2_0_a3_0_a2_9_1439), + .I1(plm_tsi3_idle_pair_0_a2_0_a2_0_a3_0_a2_10_1438), + .I2(plm_tsi3_idle_pair_0_a2_0_a2_0_a3_0_a2_11_1437), + .I3(plm_tsi3_idle_pair_0_a2_0_a2_0_a3_0_a2_13_1436), + .O(plm_tsi3_idle_pair) + ); + defparam plm_tsi3_what_it_is_reg_capture_inv_3_5867.INIT = 16'h070F; + LUT4 plm_tsi3_what_it_is_reg_capture_inv_3_5867 ( + .I0(plm_tsi3_com_data_jog0_1444), + .I1(plm_tsi3_reg_dec5_9__1480), + .I2(plm_tsi3_ts1_inv1_jog1_1447), + .I3(plm_tsi3_ts1_inv1_jog1_1_1440), + .O(plm_tsi3_reg_capture_inv_3_5867) + ); + defparam plm_tsi3_what_it_is_reg_capture_inv_3_5868.INIT = 16'h007F; + LUT4 plm_tsi3_what_it_is_reg_capture_inv_3_5868 ( + .I0(plm_tsi3_com_data_jog0_1444), + .I1(plm_tsi3_reg_dec5_11__1476), + .I2(plm_tsi3_ts2_inv1_jog0_1_1441), + .I3(plm_tsi3_ts2_inv1_jog1_1445), + .O(plm_tsi3_reg_capture_inv_3_5868) + ); + defparam plm_tsi3_what_it_is_reg_capture_ts1_3_0.INIT = 16'h070F; + LUT4 plm_tsi3_what_it_is_reg_capture_ts1_3_0 ( + .I0(plm_tsi3_com_data_jog0_1444), + .I1(plm_tsi3_reg_dec5_8__1482), + .I2(plm_tsi3_ts1_inv0_jog1_1448), + .I3(plm_tsi3_ts1_inv0_jog1_1_1442), + .O(plm_tsi3_reg_capture_ts1_3_0) + ); + defparam plm_tsi3_what_it_is_reg_capture_ts2_3_0.INIT = 16'h007F; + LUT4 plm_tsi3_what_it_is_reg_capture_ts2_3_0 ( + .I0(plm_tsi3_com_data_jog0_1444), + .I1(plm_tsi3_reg_dec5_10__1478), + .I2(plm_tsi3_ts2_inv0_jog0_1_1443), + .I3(plm_tsi3_ts2_inv0_jog1_1446), + .O(plm_tsi3_reg_capture_ts2_3_0) + ); + defparam plm_tsi3_event_regs_reg_ts2_c_3.INIT = 8'h10; + LUT3_L plm_tsi3_event_regs_reg_ts2_c_3 ( + .I0(plm_tsi3_un2_recent_ts2_2), + .I1(plm_rx_clear_cs), + .I2(plm_tsi3_reg_capture_ts2_1452), + .LO(plm_tsi3_reg_ts2_c_3) + ); + defparam plm_tsi3_event_regs_reg_ts1_c_3.INIT = 8'h10; + LUT3_L plm_tsi3_event_regs_reg_ts1_c_3 ( + .I0(plm_tsi3_un2_recent_ts1_2), + .I1(plm_rx_clear_cs), + .I2(plm_tsi3_reg_capture_ts1_1453), + .LO(plm_tsi3_reg_ts1_c_3) + ); + defparam plm_tsi3_idle_hands_reg_rx_idl_c_3_0_a2_0_a2_0_a3_0_a2.INIT = 4'h8; + LUT2_L plm_tsi3_idle_hands_reg_rx_idl_c_3_0_a2_0_a2_0_a3_0_a2 ( + .I0(plm_reg_rx_idl_1_2), + .I1(plm_tsi3_idle_pair), + .LO(plm_tsi3_reg_rx_idl_c_3) + ); + defparam plm_tsi3_what_it_is_N_11363_i.INIT = 16'h7FFF; + LUT4_L plm_tsi3_what_it_is_N_11363_i ( + .I0(plm_tsi3_reg_capture_inv_3_5867), + .I1(plm_tsi3_reg_capture_inv_3_5868), + .I2(plm_tsi3_reg_capture_ts1_3_0), + .I3(plm_tsi3_reg_capture_ts2_3_0), + .LO(plm_tsi3_N_11363_i) + ); + defparam plm_tsi3_what_it_is_N_11364_i.INIT = 4'h7; + LUT2_L plm_tsi3_what_it_is_N_11364_i ( + .I0(plm_tsi3_reg_capture_inv_3_5868), + .I1(plm_tsi3_reg_capture_ts2_3_0), + .LO(plm_tsi3_N_11364_i) + ); + defparam plm_tsi3_what_it_is_N_11365_i.INIT = 4'h7; + LUT2_L plm_tsi3_what_it_is_N_11365_i ( + .I0(plm_tsi3_reg_capture_inv_3_5867), + .I1(plm_tsi3_reg_capture_ts1_3_0), + .LO(plm_tsi3_N_11365_i) + ); + defparam plm_tsi3_what_it_is_N_11367_i.INIT = 16'hFFFE; + LUT4_L plm_tsi3_what_it_is_N_11367_i ( + .I0(plm_tsi3_ts1_inv0_jog1_1448), + .I1(plm_tsi3_ts1_inv1_jog1_1447), + .I2(plm_tsi3_ts2_inv0_jog1_1446), + .I3(plm_tsi3_ts2_inv1_jog1_1445), + .LO(plm_tsi3_N_11367_i) + ); + defparam plm_tsi3_what_it_is_N_11366_i.INIT = 4'h7; + LUT2_L plm_tsi3_what_it_is_N_11366_i ( + .I0(plm_tsi3_reg_capture_inv_3_5867), + .I1(plm_tsi3_reg_capture_inv_3_5868), + .LO(plm_tsi3_N_11366_i) + ); + defparam plm_tsi3_event_regs_reg_ts1_timer_5_f0_3_.INIT = 16'hF1F0; + LUT4_L plm_tsi3_event_regs_reg_ts1_timer_5_f0_3_ ( + .I0(plm_tsi3_un2_recent_ts1_2), + .I1(plm_rx_clear_cs), + .I2(plm_tsi3_reg_capture_ts1_1453), + .I3(plm_tsi3_un7_reg_ts1_timer_axbxc3_2), + .LO(plm_tsi3_reg_ts1_timer_5[3]) + ); + defparam plm_tsi3_event_regs_reg_ts1_timer_5_2_.INIT = 16'hE100; + LUT4_L plm_tsi3_event_regs_reg_ts1_timer_5_2_ ( + .I0(plm_tsi3_reg_ts1_timer[0]), + .I1(plm_tsi3_reg_ts1_timer[1]), + .I2(plm_tsi3_reg_ts1_timer[2]), + .I3(plm_tsi3_reg_ts1_timer_0_sqmuxa_1449), + .LO(plm_tsi3_reg_ts1_timer_5[2]) + ); + defparam plm_tsi3_event_regs_reg_ts1_timer_5_1_.INIT = 8'h90; + LUT3_L plm_tsi3_event_regs_reg_ts1_timer_5_1_ ( + .I0(plm_tsi3_reg_ts1_timer[0]), + .I1(plm_tsi3_reg_ts1_timer[1]), + .I2(plm_tsi3_reg_ts1_timer_0_sqmuxa_1449), + .LO(plm_tsi3_reg_ts1_timer_5[1]) + ); + defparam plm_tsi3_event_regs_reg_ts1_timer_5_0_.INIT = 4'h4; + LUT2_L plm_tsi3_event_regs_reg_ts1_timer_5_0_ ( + .I0(plm_tsi3_reg_ts1_timer[0]), + .I1(plm_tsi3_reg_ts1_timer_0_sqmuxa_1449), + .LO(plm_tsi3_reg_ts1_timer_5[0]) + ); + defparam plm_tsi3_event_regs_reg_ts2_timer_5_f0_3_.INIT = 16'hF1F0; + LUT4_L plm_tsi3_event_regs_reg_ts2_timer_5_f0_3_ ( + .I0(plm_tsi3_un2_recent_ts2_2), + .I1(plm_rx_clear_cs), + .I2(plm_tsi3_reg_capture_ts2_1452), + .I3(plm_tsi3_un7_reg_ts2_timer_axbxc3_2), + .LO(plm_tsi3_reg_ts2_timer_5[3]) + ); + defparam plm_tsi3_event_regs_reg_ts2_timer_5_2_.INIT = 16'hE100; + LUT4_L plm_tsi3_event_regs_reg_ts2_timer_5_2_ ( + .I0(plm_tsi3_reg_ts2_timer[0]), + .I1(plm_tsi3_reg_ts2_timer[1]), + .I2(plm_tsi3_reg_ts2_timer[2]), + .I3(plm_tsi3_reg_ts2_timer_0_sqmuxa_1450), + .LO(plm_tsi3_reg_ts2_timer_5[2]) + ); + defparam plm_tsi3_event_regs_reg_ts2_timer_5_1_.INIT = 8'h90; + LUT3_L plm_tsi3_event_regs_reg_ts2_timer_5_1_ ( + .I0(plm_tsi3_reg_ts2_timer[0]), + .I1(plm_tsi3_reg_ts2_timer[1]), + .I2(plm_tsi3_reg_ts2_timer_0_sqmuxa_1450), + .LO(plm_tsi3_reg_ts2_timer_5[1]) + ); + defparam plm_tsi3_event_regs_reg_ts2_timer_5_0_.INIT = 4'h4; + LUT2_L plm_tsi3_event_regs_reg_ts2_timer_5_0_ ( + .I0(plm_tsi3_reg_ts2_timer[0]), + .I1(plm_tsi3_reg_ts2_timer_0_sqmuxa_1450), + .LO(plm_tsi3_reg_ts2_timer_5[0]) + ); + defparam plm_tsi3_holding_regs_reg_lane_pad_3_0.INIT = 8'hD8; + LUT3_L plm_tsi3_holding_regs_reg_lane_pad_3_0 ( + .I0(plm_tsi3_reg_capture_jog_1454), + .I1(plm_tsi3_reg_dec8_6__1455), + .I2(plm_tsi3_reg_dec8_13__1451), + .LO(plm_tsi3_reg_lane_pad_3) + ); + defparam plm_tsi3_holding_regs_reg_link_pad_3_0.INIT = 8'hD8; + LUT3_L plm_tsi3_holding_regs_reg_link_pad_3_0 ( + .I0(plm_tsi3_reg_capture_jog_1454), + .I1(plm_tsi3_reg_dec8_13__1451), + .I2(plm_tsi3_reg_dec9[6]), + .LO(plm_tsi3_reg_link_pad_3) + ); + defparam plm_tsi3_holding_regs_reg_lane_num_3_7_.INIT = 16'h596A; + LUT4_L plm_tsi3_holding_regs_reg_lane_num_3_7_ ( + .I0(plm_tsi3_reg_capture_inv_1491), + .I1(plm_tsi3_reg_capture_jog_1454), + .I2(plm_tsi3_reg_dly8[7]), + .I3(plm_tsi3_reg_dly8[15]), + .LO(plm_tsi3_reg_lane_num_3[7]) + ); + defparam plm_tsi3_holding_regs_reg_lane_num_3_6_.INIT = 16'h596A; + LUT4_L plm_tsi3_holding_regs_reg_lane_num_3_6_ ( + .I0(plm_tsi3_reg_capture_inv_1491), + .I1(plm_tsi3_reg_capture_jog_1454), + .I2(plm_tsi3_reg_dly8[6]), + .I3(plm_tsi3_reg_dly8[14]), + .LO(plm_tsi3_reg_lane_num_3[6]) + ); + defparam plm_tsi3_holding_regs_reg_lane_num_3_5_.INIT = 16'h596A; + LUT4_L plm_tsi3_holding_regs_reg_lane_num_3_5_ ( + .I0(plm_tsi3_reg_capture_inv_1491), + .I1(plm_tsi3_reg_capture_jog_1454), + .I2(plm_tsi3_reg_dly8[5]), + .I3(plm_tsi3_reg_dly8[13]), + .LO(plm_tsi3_reg_lane_num_3[5]) + ); + defparam plm_tsi3_holding_regs_reg_lane_num_3_4_.INIT = 16'h596A; + LUT4_L plm_tsi3_holding_regs_reg_lane_num_3_4_ ( + .I0(plm_tsi3_reg_capture_inv_1491), + .I1(plm_tsi3_reg_capture_jog_1454), + .I2(plm_tsi3_reg_dly8[4]), + .I3(plm_tsi3_reg_dly8[12]), + .LO(plm_tsi3_reg_lane_num_3[4]) + ); + defparam plm_tsi3_holding_regs_reg_lane_num_3_3_.INIT = 16'h596A; + LUT4_L plm_tsi3_holding_regs_reg_lane_num_3_3_ ( + .I0(plm_tsi3_reg_capture_inv_1491), + .I1(plm_tsi3_reg_capture_jog_1454), + .I2(plm_tsi3_reg_dly8[3]), + .I3(plm_tsi3_reg_dly8[11]), + .LO(plm_tsi3_reg_lane_num_3[3]) + ); + defparam plm_tsi3_holding_regs_reg_lane_num_3_2_.INIT = 16'h596A; + LUT4_L plm_tsi3_holding_regs_reg_lane_num_3_2_ ( + .I0(plm_tsi3_reg_capture_inv_1491), + .I1(plm_tsi3_reg_capture_jog_1454), + .I2(plm_tsi3_reg_dly8[2]), + .I3(plm_tsi3_reg_dly8[10]), + .LO(plm_tsi3_reg_lane_num_3[2]) + ); + defparam plm_tsi3_holding_regs_reg_lane_num_3_1_.INIT = 16'h596A; + LUT4_L plm_tsi3_holding_regs_reg_lane_num_3_1_ ( + .I0(plm_tsi3_reg_capture_inv_1491), + .I1(plm_tsi3_reg_capture_jog_1454), + .I2(plm_tsi3_reg_dly8[1]), + .I3(plm_tsi3_reg_dly8[9]), + .LO(plm_tsi3_reg_lane_num_3[1]) + ); + defparam plm_tsi3_holding_regs_reg_lane_num_3_0_.INIT = 16'h596A; + LUT4_L plm_tsi3_holding_regs_reg_lane_num_3_0_ ( + .I0(plm_tsi3_reg_capture_inv_1491), + .I1(plm_tsi3_reg_capture_jog_1454), + .I2(plm_tsi3_reg_dly8[0]), + .I3(plm_tsi3_reg_dly8[8]), + .LO(plm_tsi3_reg_lane_num_3[0]) + ); + defparam plm_tsi3_holding_regs_reg_link_num_3_7_.INIT = 16'h596A; + LUT4_L plm_tsi3_holding_regs_reg_link_num_3_7_ ( + .I0(plm_tsi3_reg_capture_inv_1491), + .I1(plm_tsi3_reg_capture_jog_1454), + .I2(plm_tsi3_reg_dly8[15]), + .I3(plm_tsi3_reg_dly9[7]), + .LO(plm_tsi3_reg_link_num_3[7]) + ); + defparam plm_tsi3_holding_regs_reg_link_num_3_6_.INIT = 16'h596A; + LUT4_L plm_tsi3_holding_regs_reg_link_num_3_6_ ( + .I0(plm_tsi3_reg_capture_inv_1491), + .I1(plm_tsi3_reg_capture_jog_1454), + .I2(plm_tsi3_reg_dly8[14]), + .I3(plm_tsi3_reg_dly9[6]), + .LO(plm_tsi3_reg_link_num_3[6]) + ); + defparam plm_tsi3_holding_regs_reg_link_num_3_5_.INIT = 16'h596A; + LUT4_L plm_tsi3_holding_regs_reg_link_num_3_5_ ( + .I0(plm_tsi3_reg_capture_inv_1491), + .I1(plm_tsi3_reg_capture_jog_1454), + .I2(plm_tsi3_reg_dly8[13]), + .I3(plm_tsi3_reg_dly9[5]), + .LO(plm_tsi3_reg_link_num_3[5]) + ); + defparam plm_tsi3_holding_regs_reg_link_num_3_4_.INIT = 16'h596A; + LUT4_L plm_tsi3_holding_regs_reg_link_num_3_4_ ( + .I0(plm_tsi3_reg_capture_inv_1491), + .I1(plm_tsi3_reg_capture_jog_1454), + .I2(plm_tsi3_reg_dly8[12]), + .I3(plm_tsi3_reg_dly9[4]), + .LO(plm_tsi3_reg_link_num_3[4]) + ); + defparam plm_tsi3_holding_regs_reg_link_num_3_3_.INIT = 16'h596A; + LUT4_L plm_tsi3_holding_regs_reg_link_num_3_3_ ( + .I0(plm_tsi3_reg_capture_inv_1491), + .I1(plm_tsi3_reg_capture_jog_1454), + .I2(plm_tsi3_reg_dly8[11]), + .I3(plm_tsi3_reg_dly9[3]), + .LO(plm_tsi3_reg_link_num_3[3]) + ); + defparam plm_tsi3_holding_regs_reg_link_num_3_2_.INIT = 16'h596A; + LUT4_L plm_tsi3_holding_regs_reg_link_num_3_2_ ( + .I0(plm_tsi3_reg_capture_inv_1491), + .I1(plm_tsi3_reg_capture_jog_1454), + .I2(plm_tsi3_reg_dly8[10]), + .I3(plm_tsi3_reg_dly9[2]), + .LO(plm_tsi3_reg_link_num_3[2]) + ); + defparam plm_tsi3_holding_regs_reg_link_num_3_1_.INIT = 16'h596A; + LUT4_L plm_tsi3_holding_regs_reg_link_num_3_1_ ( + .I0(plm_tsi3_reg_capture_inv_1491), + .I1(plm_tsi3_reg_capture_jog_1454), + .I2(plm_tsi3_reg_dly8[9]), + .I3(plm_tsi3_reg_dly9[1]), + .LO(plm_tsi3_reg_link_num_3[1]) + ); + defparam plm_tsi3_holding_regs_reg_link_num_3_0_.INIT = 16'h596A; + LUT4_L plm_tsi3_holding_regs_reg_link_num_3_0_ ( + .I0(plm_tsi3_reg_capture_inv_1491), + .I1(plm_tsi3_reg_capture_jog_1454), + .I2(plm_tsi3_reg_dly8[8]), + .I3(plm_tsi3_reg_dly9[0]), + .LO(plm_tsi3_reg_link_num_3[0]) + ); + defparam plm_tsi3_holding_regs_reg_linkctrl_3_3_.INIT = 16'h636C; + LUT4_L plm_tsi3_holding_regs_reg_linkctrl_3_3_ ( + .I0(plm_tsi3_do[11]), + .I1(plm_tsi3_reg_capture_inv_1491), + .I2(plm_tsi3_reg_capture_jog_1454), + .I3(plm_tsi3_reg_dly7[3]), + .LO(plm_tsi3_reg_linkctrl_3_3_) + ); + defparam plm_tsi3_holding_regs_reg_linkctrl_3_0_.INIT = 16'h636C; + LUT4_L plm_tsi3_holding_regs_reg_linkctrl_3_0_ ( + .I0(plm_tsi3_do[8]), + .I1(plm_tsi3_reg_capture_inv_1491), + .I2(plm_tsi3_reg_capture_jog_1454), + .I3(plm_tsi3_reg_dly7[0]), + .LO(plm_tsi3_reg_linkctrl_3_0_) + ); + FD plm_tsi3_reg_dec8_0_DOUT_0_ ( + .C(mgt_clk), + .D(plm_tsi3_reg_dec8_0_N_6), + .Q(plm_tsi3_reg_dec8_0_DOUT[0]) + ); + FD plm_tsi3_reg_dec6_DOUT_0_ ( + .C(mgt_clk), + .D(plm_tsi3_reg_dec6_N_6), + .Q(plm_tsi3_reg_dec6_DOUT[0]) + ); + FD plm_tsi3_reg_dec1_2_DOUT_0_ ( + .C(mgt_clk), + .D(plm_tsi3_reg_dec1_2_N_6), + .Q(plm_tsi3_reg_dec1_2_DOUT[0]) + ); + FD plm_tsi3_reg_dec1_1_DOUT_0_ ( + .C(mgt_clk), + .D(plm_tsi3_reg_dec1_1_N_6), + .Q(plm_tsi3_reg_dec1_1_DOUT[0]) + ); + FD plm_tsi3_reg_dec1_0_DOUT_0_ ( + .C(mgt_clk), + .D(plm_tsi3_reg_dec1_0_N_6), + .Q(plm_tsi3_reg_dec1_0_DOUT[0]) + ); + FD plm_tsi3_reg_dec1_DOUT_0_ ( + .C(mgt_clk), + .D(plm_tsi3_reg_dec1_N_6), + .Q(plm_tsi3_reg_dec1_DOUT[0]) + ); + FD plm_tsi3_reg_dec8_DOUT_0_ ( + .C(mgt_clk), + .D(plm_tsi3_reg_dec8_N_6), + .Q(plm_tsi3_reg_dec8_DOUT[0]) + ); + FD plm_tsi3_reg_dec7_0_DOUT_0_ ( + .C(mgt_clk), + .D(plm_tsi3_reg_dec7_0_N_6), + .Q(plm_tsi3_reg_dec7_0_DOUT[0]) + ); + FD plm_tsi3_reg_dec5_DOUT_0_ ( + .C(mgt_clk), + .D(plm_tsi3_reg_dec5_N_6), + .Q(plm_tsi3_reg_dec5_DOUT[0]) + ); + FD plm_tsi3_reg_dec7_DOUT_0_ ( + .C(mgt_clk), + .D(plm_tsi3_reg_dec7_N_6), + .Q(plm_tsi3_reg_dec7_DOUT[0]) + ); + FDC plm_tsi3_reg_dec8_13_ ( + .C(mgt_clk), + .D(plm_tsi3_reg_dec7_13_), + .Q(plm_tsi3_reg_dec8_13__1451), + .CLR(plm_rst) + ); + FDC plm_tsi3_reg_dec9_6_ ( + .C(mgt_clk), + .D(plm_tsi3_reg_dec8_6__1455), + .Q(plm_tsi3_reg_dec9[6]), + .CLR(plm_rst) + ); + FDC plm_tsi3_reg_ts2_c ( + .C(mgt_clk), + .D(plm_tsi3_reg_ts2_c_3), + .Q(plm_rx3_ts2_c), + .CLR(plm_rst) + ); + FDC plm_tsi3_reg_ts1_c ( + .C(mgt_clk), + .D(plm_tsi3_reg_ts1_c_3), + .Q(plm_rx3_ts1_c), + .CLR(plm_rst) + ); + FDC plm_tsi3_reg_rx_idl_c ( + .C(mgt_clk), + .D(plm_tsi3_reg_rx_idl_c_3), + .Q(plm_rx3_idl_c), + .CLR(plm_rst) + ); + FDC plm_tsi3_reg_rx_idl_1 ( + .C(mgt_clk), + .D(plm_tsi3_idle_pair), + .Q(plm_reg_rx_idl_1_2), + .CLR(plm_rst) + ); + FDC plm_tsi3_reg_ts2_1 ( + .C(mgt_clk), + .D(plm_tsi3_reg_capture_ts2_1452), + .Q(plm_reg_ts2_1_2), + .CLR(plm_rst) + ); + FDC plm_tsi3_reg_ts1_1 ( + .C(mgt_clk), + .D(plm_tsi3_reg_capture_ts1_1453), + .Q(plm_reg_ts1_1_2), + .CLR(plm_rst) + ); + FDC plm_tsi3_reg_capture_now ( + .C(mgt_clk), + .D(plm_tsi3_N_11363_i), + .Q(plm_tsi3_reg_capture_now_1492), + .CLR(plm_rst) + ); + FDC plm_tsi3_reg_capture_ts2 ( + .C(mgt_clk), + .D(plm_tsi3_N_11364_i), + .Q(plm_tsi3_reg_capture_ts2_1452), + .CLR(plm_rst) + ); + FDC plm_tsi3_reg_capture_ts1 ( + .C(mgt_clk), + .D(plm_tsi3_N_11365_i), + .Q(plm_tsi3_reg_capture_ts1_1453), + .CLR(plm_rst) + ); + FDC plm_tsi3_reg_capture_jog ( + .C(mgt_clk), + .D(plm_tsi3_N_11367_i), + .Q(plm_tsi3_reg_capture_jog_1454), + .CLR(plm_rst) + ); + FDC plm_tsi3_reg_capture_inv ( + .C(mgt_clk), + .D(plm_tsi3_N_11366_i), + .Q(plm_tsi3_reg_capture_inv_1491), + .CLR(plm_rst) + ); + FDC plm_tsi3_reg_ts1_timer_3_ ( + .C(mgt_clk), + .D(plm_tsi3_reg_ts1_timer_5[3]), + .Q(plm_tsi3_reg_ts1_timer[3]), + .CLR(plm_rst) + ); + FDC plm_tsi3_reg_ts1_timer_2_ ( + .C(mgt_clk), + .D(plm_tsi3_reg_ts1_timer_5[2]), + .Q(plm_tsi3_reg_ts1_timer[2]), + .CLR(plm_rst) + ); + FDC plm_tsi3_reg_ts1_timer_1_ ( + .C(mgt_clk), + .D(plm_tsi3_reg_ts1_timer_5[1]), + .Q(plm_tsi3_reg_ts1_timer[1]), + .CLR(plm_rst) + ); + FDC plm_tsi3_reg_ts1_timer_0_ ( + .C(mgt_clk), + .D(plm_tsi3_reg_ts1_timer_5[0]), + .Q(plm_tsi3_reg_ts1_timer[0]), + .CLR(plm_rst) + ); + FDC plm_tsi3_reg_ts2_timer_3_ ( + .C(mgt_clk), + .D(plm_tsi3_reg_ts2_timer_5[3]), + .Q(plm_tsi3_reg_ts2_timer[3]), + .CLR(plm_rst) + ); + FDC plm_tsi3_reg_ts2_timer_2_ ( + .C(mgt_clk), + .D(plm_tsi3_reg_ts2_timer_5[2]), + .Q(plm_tsi3_reg_ts2_timer[2]), + .CLR(plm_rst) + ); + FDC plm_tsi3_reg_ts2_timer_1_ ( + .C(mgt_clk), + .D(plm_tsi3_reg_ts2_timer_5[1]), + .Q(plm_tsi3_reg_ts2_timer[1]), + .CLR(plm_rst) + ); + FDC plm_tsi3_reg_ts2_timer_0_ ( + .C(mgt_clk), + .D(plm_tsi3_reg_ts2_timer_5[0]), + .Q(plm_tsi3_reg_ts2_timer[0]), + .CLR(plm_rst) + ); + FDC plm_tsi3_reg_dec1_10_ ( + .C(mgt_clk), + .D(plm_rx3_des_t2p[1]), + .Q(plm_tsi3_reg_dec1_6110[10]), + .CLR(plm_rst) + ); + FDC plm_tsi3_reg_dec1_9_ ( + .C(mgt_clk), + .D(plm_rx3_des_t1n[1]), + .Q(plm_tsi3_reg_dec1_6110[9]), + .CLR(plm_rst) + ); + FDC plm_tsi3_reg_dec1_8_ ( + .C(mgt_clk), + .D(plm_rx3_des_t1p[1]), + .Q(plm_tsi3_reg_dec1_6110[8]), + .CLR(plm_rst) + ); + FDC plm_tsi3_reg_dec8_6_ ( + .C(mgt_clk), + .D(plm_tsi3_reg_dec7_6_), + .Q(plm_tsi3_reg_dec8_6__1455), + .CLR(plm_rst) + ); + FDC plm_tsi3_reg_dec8_5_ ( + .C(mgt_clk), + .D(plm_tsi3_reg_dec7_5__1457), + .Q(plm_tsi3_reg_dec8_5__1456), + .CLR(plm_rst) + ); + FDC plm_tsi3_reg_dec4_11_ ( + .C(mgt_clk), + .D(plm_tsi3_reg_dec3_11__1459), + .Q(plm_tsi3_reg_dec4_11__1475), + .CLR(plm_rst) + ); + FDC plm_tsi3_reg_dec4_10_ ( + .C(mgt_clk), + .D(plm_tsi3_reg_dec3_10__1461), + .Q(plm_tsi3_reg_dec4_10__1477), + .CLR(plm_rst) + ); + FDC plm_tsi3_reg_dec4_9_ ( + .C(mgt_clk), + .D(plm_tsi3_reg_dec3_9__1463), + .Q(plm_tsi3_reg_dec4_9__1479), + .CLR(plm_rst) + ); + FDC plm_tsi3_reg_dec4_8_ ( + .C(mgt_clk), + .D(plm_tsi3_reg_dec3_8__1465), + .Q(plm_tsi3_reg_dec4_8__1481), + .CLR(plm_rst) + ); + FDC plm_tsi3_reg_dec4_4_ ( + .C(mgt_clk), + .D(plm_tsi3_reg_dec3_4__1467), + .Q(plm_tsi3_reg_dec4_4__1483), + .CLR(plm_rst) + ); + FDC plm_tsi3_reg_dec4_3_ ( + .C(mgt_clk), + .D(plm_tsi3_reg_dec3_3__1469), + .Q(plm_tsi3_reg_dec4_3__1485), + .CLR(plm_rst) + ); + FDC plm_tsi3_reg_dec4_2_ ( + .C(mgt_clk), + .D(plm_tsi3_reg_dec3_2__1471), + .Q(plm_tsi3_reg_dec4_2__1487), + .CLR(plm_rst) + ); + FDC plm_tsi3_reg_dec4_1_ ( + .C(mgt_clk), + .D(plm_tsi3_reg_dec3_1__1473), + .Q(plm_tsi3_reg_dec4_1__1489), + .CLR(plm_rst) + ); + FDC plm_tsi3_reg_dec1_11_ ( + .C(mgt_clk), + .D(plm_rx3_des_t2n[1]), + .Q(plm_tsi3_reg_dec1_6110[11]), + .CLR(plm_rst) + ); + FDC plm_tsi3_reg_dec6_12_ ( + .C(mgt_clk), + .D(plm_tsi3_reg_dec5[12]), + .Q(plm_tsi3_reg_dec6_6111[12]), + .CLR(plm_rst) + ); + FDC plm_tsi3_reg_dly8_9_ ( + .C(mgt_clk), + .D(plm_tsi3_reg_dly7[9]), + .Q(plm_tsi3_reg_dly8[9]), + .CLR(plm_rst) + ); + FDC plm_tsi3_reg_dly8_8_ ( + .C(mgt_clk), + .D(plm_tsi3_reg_dly7[8]), + .Q(plm_tsi3_reg_dly8[8]), + .CLR(plm_rst) + ); + FDC plm_tsi3_reg_dly8_7_ ( + .C(mgt_clk), + .D(plm_tsi3_reg_dly7[7]), + .Q(plm_tsi3_reg_dly8[7]), + .CLR(plm_rst) + ); + FDC plm_tsi3_reg_dly8_6_ ( + .C(mgt_clk), + .D(plm_tsi3_reg_dly7[6]), + .Q(plm_tsi3_reg_dly8[6]), + .CLR(plm_rst) + ); + FDC plm_tsi3_reg_dly8_5_ ( + .C(mgt_clk), + .D(plm_tsi3_reg_dly7[5]), + .Q(plm_tsi3_reg_dly8[5]), + .CLR(plm_rst) + ); + FDC plm_tsi3_reg_dly8_4_ ( + .C(mgt_clk), + .D(plm_tsi3_reg_dly7[4]), + .Q(plm_tsi3_reg_dly8[4]), + .CLR(plm_rst) + ); + FDC plm_tsi3_reg_dly8_3_ ( + .C(mgt_clk), + .D(plm_tsi3_reg_dly7[3]), + .Q(plm_tsi3_reg_dly8[3]), + .CLR(plm_rst) + ); + FDC plm_tsi3_reg_dly8_2_ ( + .C(mgt_clk), + .D(plm_tsi3_reg_dly7[2]), + .Q(plm_tsi3_reg_dly8[2]), + .CLR(plm_rst) + ); + FDC plm_tsi3_reg_dly8_1_ ( + .C(mgt_clk), + .D(plm_tsi3_reg_dly7[1]), + .Q(plm_tsi3_reg_dly8[1]), + .CLR(plm_rst) + ); + FDC plm_tsi3_reg_dly8_0_ ( + .C(mgt_clk), + .D(plm_tsi3_reg_dly7[0]), + .Q(plm_tsi3_reg_dly8[0]), + .CLR(plm_rst) + ); + FDC plm_tsi3_reg_dec2_8_ ( + .C(mgt_clk), + .D(plm_tsi3_reg_dec1_6110[8]), + .Q(plm_tsi3_reg_dec2_8__1464), + .CLR(plm_rst) + ); + FDC plm_tsi3_reg_dec2_4_ ( + .C(mgt_clk), + .D(plm_tsi3_reg_dec1[4]), + .Q(plm_tsi3_reg_dec2_4__1466), + .CLR(plm_rst) + ); + FDC plm_tsi3_reg_dec2_3_ ( + .C(mgt_clk), + .D(plm_tsi3_reg_dec1[3]), + .Q(plm_tsi3_reg_dec2_3__1468), + .CLR(plm_rst) + ); + FDC plm_tsi3_reg_dec2_2_ ( + .C(mgt_clk), + .D(plm_tsi3_reg_dec1[2]), + .Q(plm_tsi3_reg_dec2_2__1470), + .CLR(plm_rst) + ); + FDC plm_tsi3_reg_dec2_1_ ( + .C(mgt_clk), + .D(plm_tsi3_reg_dec1[1]), + .Q(plm_tsi3_reg_dec2_1__1472), + .CLR(plm_rst) + ); + FDC plm_tsi3_reg_dly8_15_ ( + .C(mgt_clk), + .D(plm_tsi3_reg_dly7[15]), + .Q(plm_tsi3_reg_dly8[15]), + .CLR(plm_rst) + ); + FDC plm_tsi3_reg_dly8_14_ ( + .C(mgt_clk), + .D(plm_tsi3_reg_dly7[14]), + .Q(plm_tsi3_reg_dly8[14]), + .CLR(plm_rst) + ); + FDC plm_tsi3_reg_dly8_13_ ( + .C(mgt_clk), + .D(plm_tsi3_reg_dly7[13]), + .Q(plm_tsi3_reg_dly8[13]), + .CLR(plm_rst) + ); + FDC plm_tsi3_reg_dly8_12_ ( + .C(mgt_clk), + .D(plm_tsi3_reg_dly7[12]), + .Q(plm_tsi3_reg_dly8[12]), + .CLR(plm_rst) + ); + FDC plm_tsi3_reg_dly8_11_ ( + .C(mgt_clk), + .D(plm_tsi3_reg_dly7[11]), + .Q(plm_tsi3_reg_dly8[11]), + .CLR(plm_rst) + ); + FDC plm_tsi3_reg_dly8_10_ ( + .C(mgt_clk), + .D(plm_tsi3_reg_dly7[10]), + .Q(plm_tsi3_reg_dly8[10]), + .CLR(plm_rst) + ); + FDC plm_tsi3_reg_dec7_5_ ( + .C(mgt_clk), + .D(plm_tsi3_reg_dec6[5]), + .Q(plm_tsi3_reg_dec7_5__1457), + .CLR(plm_rst) + ); + FDC plm_tsi3_reg_dly9_7_ ( + .C(mgt_clk), + .D(plm_tsi3_reg_dly8[7]), + .Q(plm_tsi3_reg_dly9[7]), + .CLR(plm_rst) + ); + FDC plm_tsi3_reg_dly9_6_ ( + .C(mgt_clk), + .D(plm_tsi3_reg_dly8[6]), + .Q(plm_tsi3_reg_dly9[6]), + .CLR(plm_rst) + ); + FDC plm_tsi3_reg_dly9_5_ ( + .C(mgt_clk), + .D(plm_tsi3_reg_dly8[5]), + .Q(plm_tsi3_reg_dly9[5]), + .CLR(plm_rst) + ); + FDC plm_tsi3_reg_dly9_4_ ( + .C(mgt_clk), + .D(plm_tsi3_reg_dly8[4]), + .Q(plm_tsi3_reg_dly9[4]), + .CLR(plm_rst) + ); + FDC plm_tsi3_reg_dly9_3_ ( + .C(mgt_clk), + .D(plm_tsi3_reg_dly8[3]), + .Q(plm_tsi3_reg_dly9[3]), + .CLR(plm_rst) + ); + FDC plm_tsi3_reg_dly9_2_ ( + .C(mgt_clk), + .D(plm_tsi3_reg_dly8[2]), + .Q(plm_tsi3_reg_dly9[2]), + .CLR(plm_rst) + ); + FDC plm_tsi3_reg_dly9_1_ ( + .C(mgt_clk), + .D(plm_tsi3_reg_dly8[1]), + .Q(plm_tsi3_reg_dly9[1]), + .CLR(plm_rst) + ); + FDC plm_tsi3_reg_dly9_0_ ( + .C(mgt_clk), + .D(plm_tsi3_reg_dly8[0]), + .Q(plm_tsi3_reg_dly9[0]), + .CLR(plm_rst) + ); + FDC plm_tsi3_reg_dec2_11_ ( + .C(mgt_clk), + .D(plm_tsi3_reg_dec1_6110[11]), + .Q(plm_tsi3_reg_dec2_11__1458), + .CLR(plm_rst) + ); + FDC plm_tsi3_reg_dec2_10_ ( + .C(mgt_clk), + .D(plm_tsi3_reg_dec1_6110[10]), + .Q(plm_tsi3_reg_dec2_10__1460), + .CLR(plm_rst) + ); + FDC plm_tsi3_reg_dec2_9_ ( + .C(mgt_clk), + .D(plm_tsi3_reg_dec1_6110[9]), + .Q(plm_tsi3_reg_dec2_9__1462), + .CLR(plm_rst) + ); + FDC plm_tsi3_reg_dec3_11_ ( + .C(mgt_clk), + .D(plm_tsi3_reg_dec2_11__1458), + .Q(plm_tsi3_reg_dec3_11__1459), + .CLR(plm_rst) + ); + FDC plm_tsi3_reg_dec3_10_ ( + .C(mgt_clk), + .D(plm_tsi3_reg_dec2_10__1460), + .Q(plm_tsi3_reg_dec3_10__1461), + .CLR(plm_rst) + ); + FDC plm_tsi3_reg_dec3_9_ ( + .C(mgt_clk), + .D(plm_tsi3_reg_dec2_9__1462), + .Q(plm_tsi3_reg_dec3_9__1463), + .CLR(plm_rst) + ); + FDC plm_tsi3_reg_dec3_8_ ( + .C(mgt_clk), + .D(plm_tsi3_reg_dec2_8__1464), + .Q(plm_tsi3_reg_dec3_8__1465), + .CLR(plm_rst) + ); + FDC plm_tsi3_reg_dec3_4_ ( + .C(mgt_clk), + .D(plm_tsi3_reg_dec2_4__1466), + .Q(plm_tsi3_reg_dec3_4__1467), + .CLR(plm_rst) + ); + FDC plm_tsi3_reg_dec3_3_ ( + .C(mgt_clk), + .D(plm_tsi3_reg_dec2_3__1468), + .Q(plm_tsi3_reg_dec3_3__1469), + .CLR(plm_rst) + ); + FDC plm_tsi3_reg_dec3_2_ ( + .C(mgt_clk), + .D(plm_tsi3_reg_dec2_2__1470), + .Q(plm_tsi3_reg_dec3_2__1471), + .CLR(plm_rst) + ); + FDC plm_tsi3_reg_dec3_1_ ( + .C(mgt_clk), + .D(plm_tsi3_reg_dec2_1__1472), + .Q(plm_tsi3_reg_dec3_1__1473), + .CLR(plm_rst) + ); + FDC plm_tsi3_reg_dec7_12_ ( + .C(mgt_clk), + .D(plm_tsi3_reg_dec6_6111[12]), + .Q(plm_tsi3_reg_dec7_12__1474), + .CLR(plm_rst) + ); + FDC plm_tsi3_reg_dec5_11_ ( + .C(mgt_clk), + .D(plm_tsi3_reg_dec4_11__1475), + .Q(plm_tsi3_reg_dec5_11__1476), + .CLR(plm_rst) + ); + FDC plm_tsi3_reg_dec5_10_ ( + .C(mgt_clk), + .D(plm_tsi3_reg_dec4_10__1477), + .Q(plm_tsi3_reg_dec5_10__1478), + .CLR(plm_rst) + ); + FDC plm_tsi3_reg_dec5_9_ ( + .C(mgt_clk), + .D(plm_tsi3_reg_dec4_9__1479), + .Q(plm_tsi3_reg_dec5_9__1480), + .CLR(plm_rst) + ); + FDC plm_tsi3_reg_dec5_8_ ( + .C(mgt_clk), + .D(plm_tsi3_reg_dec4_8__1481), + .Q(plm_tsi3_reg_dec5_8__1482), + .CLR(plm_rst) + ); + FDC plm_tsi3_reg_dec5_4_ ( + .C(mgt_clk), + .D(plm_tsi3_reg_dec4_4__1483), + .Q(plm_tsi3_reg_dec5_4__1484), + .CLR(plm_rst) + ); + FDC plm_tsi3_reg_dec5_3_ ( + .C(mgt_clk), + .D(plm_tsi3_reg_dec4_3__1485), + .Q(plm_tsi3_reg_dec5_3__1486), + .CLR(plm_rst) + ); + FDC plm_tsi3_reg_dec5_2_ ( + .C(mgt_clk), + .D(plm_tsi3_reg_dec4_2__1487), + .Q(plm_tsi3_reg_dec5_2__1488), + .CLR(plm_rst) + ); + FDC plm_tsi3_reg_dec5_1_ ( + .C(mgt_clk), + .D(plm_tsi3_reg_dec4_1__1489), + .Q(plm_tsi3_reg_dec5_1__1490), + .CLR(plm_rst) + ); + FDC plm_tsi3_reg_dly7_13_ ( + .C(mgt_clk), + .D(plm_tsi3_do[13]), + .Q(plm_tsi3_reg_dly7[13]), + .CLR(plm_rst) + ); + FDC plm_tsi3_reg_dly7_12_ ( + .C(mgt_clk), + .D(plm_tsi3_do[12]), + .Q(plm_tsi3_reg_dly7[12]), + .CLR(plm_rst) + ); + FDC plm_tsi3_reg_dly7_11_ ( + .C(mgt_clk), + .D(plm_tsi3_do[11]), + .Q(plm_tsi3_reg_dly7[11]), + .CLR(plm_rst) + ); + FDC plm_tsi3_reg_dly7_10_ ( + .C(mgt_clk), + .D(plm_tsi3_do[10]), + .Q(plm_tsi3_reg_dly7[10]), + .CLR(plm_rst) + ); + FDC plm_tsi3_reg_dly7_9_ ( + .C(mgt_clk), + .D(plm_tsi3_do[9]), + .Q(plm_tsi3_reg_dly7[9]), + .CLR(plm_rst) + ); + FDC plm_tsi3_reg_dly7_8_ ( + .C(mgt_clk), + .D(plm_tsi3_do[8]), + .Q(plm_tsi3_reg_dly7[8]), + .CLR(plm_rst) + ); + FDC plm_tsi3_reg_dly7_7_ ( + .C(mgt_clk), + .D(plm_tsi3_do[7]), + .Q(plm_tsi3_reg_dly7[7]), + .CLR(plm_rst) + ); + FDC plm_tsi3_reg_dly7_6_ ( + .C(mgt_clk), + .D(plm_tsi3_do[6]), + .Q(plm_tsi3_reg_dly7[6]), + .CLR(plm_rst) + ); + FDC plm_tsi3_reg_dly7_5_ ( + .C(mgt_clk), + .D(plm_tsi3_do[5]), + .Q(plm_tsi3_reg_dly7[5]), + .CLR(plm_rst) + ); + FDC plm_tsi3_reg_dly7_4_ ( + .C(mgt_clk), + .D(plm_tsi3_do[4]), + .Q(plm_tsi3_reg_dly7[4]), + .CLR(plm_rst) + ); + FDC plm_tsi3_reg_dly7_3_ ( + .C(mgt_clk), + .D(plm_tsi3_do[3]), + .Q(plm_tsi3_reg_dly7[3]), + .CLR(plm_rst) + ); + FDC plm_tsi3_reg_dly7_2_ ( + .C(mgt_clk), + .D(plm_tsi3_do[2]), + .Q(plm_tsi3_reg_dly7[2]), + .CLR(plm_rst) + ); + FDC plm_tsi3_reg_dly7_1_ ( + .C(mgt_clk), + .D(plm_tsi3_do[1]), + .Q(plm_tsi3_reg_dly7[1]), + .CLR(plm_rst) + ); + FDC plm_tsi3_reg_dly7_0_ ( + .C(mgt_clk), + .D(plm_tsi3_do[0]), + .Q(plm_tsi3_reg_dly7[0]), + .CLR(plm_rst) + ); + FDC plm_tsi3_reg_dly7_15_ ( + .C(mgt_clk), + .D(plm_tsi3_do[15]), + .Q(plm_tsi3_reg_dly7[15]), + .CLR(plm_rst) + ); + FDC plm_tsi3_reg_dly7_14_ ( + .C(mgt_clk), + .D(plm_tsi3_do[14]), + .Q(plm_tsi3_reg_dly7[14]), + .CLR(plm_rst) + ); + FDCE plm_tsi3_reg_inverted ( + .CE(plm_tsi3_reg_capture_now_1492), + .C(mgt_clk), + .D(plm_tsi3_reg_capture_inv_1491), + .Q(plm_rx3_inverted), + .CLR(plm_rst) + ); + FDCE plm_tsi3_reg_lane_pad ( + .CE(plm_tsi3_reg_capture_now_1492), + .C(mgt_clk), + .D(plm_tsi3_reg_lane_pad_3), + .Q(plm_rx3_lane_pad), + .CLR(plm_rst) + ); + FDCE plm_tsi3_reg_link_pad ( + .CE(plm_tsi3_reg_capture_now_1492), + .C(mgt_clk), + .D(plm_tsi3_reg_link_pad_3), + .Q(plm_rx3_link_pad), + .CLR(plm_rst) + ); + FDCE plm_tsi3_reg_lane_num_7_ ( + .CE(plm_tsi3_reg_capture_now_1492), + .C(mgt_clk), + .D(plm_tsi3_reg_lane_num_3[7]), + .Q(plm_rx3_lane_num[7]), + .CLR(plm_rst) + ); + FDCE plm_tsi3_reg_lane_num_6_ ( + .CE(plm_tsi3_reg_capture_now_1492), + .C(mgt_clk), + .D(plm_tsi3_reg_lane_num_3[6]), + .Q(plm_rx3_lane_num[6]), + .CLR(plm_rst) + ); + FDCE plm_tsi3_reg_lane_num_5_ ( + .CE(plm_tsi3_reg_capture_now_1492), + .C(mgt_clk), + .D(plm_tsi3_reg_lane_num_3[5]), + .Q(plm_rx3_lane_num[5]), + .CLR(plm_rst) + ); + FDCE plm_tsi3_reg_lane_num_4_ ( + .CE(plm_tsi3_reg_capture_now_1492), + .C(mgt_clk), + .D(plm_tsi3_reg_lane_num_3[4]), + .Q(plm_rx3_lane_num[4]), + .CLR(plm_rst) + ); + FDCE plm_tsi3_reg_lane_num_3_ ( + .CE(plm_tsi3_reg_capture_now_1492), + .C(mgt_clk), + .D(plm_tsi3_reg_lane_num_3[3]), + .Q(plm_rx3_lane_num[3]), + .CLR(plm_rst) + ); + FDCE plm_tsi3_reg_lane_num_2_ ( + .CE(plm_tsi3_reg_capture_now_1492), + .C(mgt_clk), + .D(plm_tsi3_reg_lane_num_3[2]), + .Q(plm_rx3_lane_num[2]), + .CLR(plm_rst) + ); + FDCE plm_tsi3_reg_lane_num_1_ ( + .CE(plm_tsi3_reg_capture_now_1492), + .C(mgt_clk), + .D(plm_tsi3_reg_lane_num_3[1]), + .Q(plm_rx3_lane_num[1]), + .CLR(plm_rst) + ); + FDCE plm_tsi3_reg_lane_num_0_ ( + .CE(plm_tsi3_reg_capture_now_1492), + .C(mgt_clk), + .D(plm_tsi3_reg_lane_num_3[0]), + .Q(plm_rx3_lane_num[0]), + .CLR(plm_rst) + ); + FDCE plm_tsi3_reg_link_num_7_ ( + .CE(plm_tsi3_reg_capture_now_1492), + .C(mgt_clk), + .D(plm_tsi3_reg_link_num_3[7]), + .Q(plm_rx3_link_num[7]), + .CLR(plm_rst) + ); + FDCE plm_tsi3_reg_link_num_6_ ( + .CE(plm_tsi3_reg_capture_now_1492), + .C(mgt_clk), + .D(plm_tsi3_reg_link_num_3[6]), + .Q(plm_rx3_link_num[6]), + .CLR(plm_rst) + ); + FDCE plm_tsi3_reg_link_num_5_ ( + .CE(plm_tsi3_reg_capture_now_1492), + .C(mgt_clk), + .D(plm_tsi3_reg_link_num_3[5]), + .Q(plm_rx3_link_num[5]), + .CLR(plm_rst) + ); + FDCE plm_tsi3_reg_link_num_4_ ( + .CE(plm_tsi3_reg_capture_now_1492), + .C(mgt_clk), + .D(plm_tsi3_reg_link_num_3[4]), + .Q(plm_rx3_link_num[4]), + .CLR(plm_rst) + ); + FDCE plm_tsi3_reg_link_num_3_ ( + .CE(plm_tsi3_reg_capture_now_1492), + .C(mgt_clk), + .D(plm_tsi3_reg_link_num_3[3]), + .Q(plm_rx3_link_num[3]), + .CLR(plm_rst) + ); + FDCE plm_tsi3_reg_link_num_2_ ( + .CE(plm_tsi3_reg_capture_now_1492), + .C(mgt_clk), + .D(plm_tsi3_reg_link_num_3[2]), + .Q(plm_rx3_link_num[2]), + .CLR(plm_rst) + ); + FDCE plm_tsi3_reg_link_num_1_ ( + .CE(plm_tsi3_reg_capture_now_1492), + .C(mgt_clk), + .D(plm_tsi3_reg_link_num_3[1]), + .Q(plm_rx3_link_num[1]), + .CLR(plm_rst) + ); + FDCE plm_tsi3_reg_link_num_0_ ( + .CE(plm_tsi3_reg_capture_now_1492), + .C(mgt_clk), + .D(plm_tsi3_reg_link_num_3[0]), + .Q(plm_rx3_link_num[0]), + .CLR(plm_rst) + ); + FDCE plm_tsi3_reg_linkctrl_3_ ( + .CE(plm_tsi3_reg_capture_now_1492), + .C(mgt_clk), + .D(plm_tsi3_reg_linkctrl_3_3_), + .Q(plm_rx3_linkctrl_3_), + .CLR(plm_rst) + ); + FDCE plm_tsi3_reg_linkctrl_0_ ( + .CE(plm_tsi3_reg_capture_now_1492), + .C(mgt_clk), + .D(plm_tsi3_reg_linkctrl_3_0_), + .Q(plm_rx3_linkctrl_0_), + .CLR(plm_rst) + ); + SRL16 plm_tsi3_reg_dec8_0_I_1 ( + .D(plm_reg_com_1[0]), + .Q(plm_tsi3_reg_dec8_0_N_6), + .CLK(mgt_clk), + .A0(plm_tsi3_VCC_1494), + .A1(plm_tsi3_VCC_1494), + .A2(plm_tsi3_VCC_1494), + .A3(plm_tsi3_GND_1493) + ); + SRL16 plm_tsi3_reg_dec6_I_1 ( + .D(plm_rx3_des_sym[0]), + .Q(plm_tsi3_reg_dec6_N_6), + .CLK(mgt_clk), + .A0(plm_tsi3_GND_1493), + .A1(plm_tsi3_GND_1493), + .A2(plm_tsi3_VCC_1494), + .A3(plm_tsi3_GND_1493) + ); + SRL16 plm_tsi3_reg_dec1_2_I_1 ( + .D(plm_reg_t2n_4_2[0]), + .Q(plm_tsi3_reg_dec1_2_N_6), + .CLK(mgt_clk), + .A0(plm_tsi3_VCC_1494), + .A1(plm_tsi3_GND_1493), + .A2(plm_tsi3_GND_1493), + .A3(plm_tsi3_GND_1493) + ); + SRL16 plm_tsi3_reg_dec1_1_I_1 ( + .D(plm_reg_t2p_4_2[0]), + .Q(plm_tsi3_reg_dec1_1_N_6), + .CLK(mgt_clk), + .A0(plm_tsi3_VCC_1494), + .A1(plm_tsi3_GND_1493), + .A2(plm_tsi3_GND_1493), + .A3(plm_tsi3_GND_1493) + ); + SRL16 plm_tsi3_reg_dec1_0_I_1 ( + .D(plm_reg_t1n_4_2[0]), + .Q(plm_tsi3_reg_dec1_0_N_6), + .CLK(mgt_clk), + .A0(plm_tsi3_VCC_1494), + .A1(plm_tsi3_GND_1493), + .A2(plm_tsi3_GND_1493), + .A3(plm_tsi3_GND_1493) + ); + SRL16 plm_tsi3_reg_dec1_I_1 ( + .D(plm_reg_t1p_4_2[0]), + .Q(plm_tsi3_reg_dec1_N_6), + .CLK(mgt_clk), + .A0(plm_tsi3_VCC_1494), + .A1(plm_tsi3_GND_1493), + .A2(plm_tsi3_GND_1493), + .A3(plm_tsi3_GND_1493) + ); + SRL16 plm_tsi3_reg_dec8_I_1 ( + .D(plm_reg_com_1[1]), + .Q(plm_tsi3_reg_dec8_N_6), + .CLK(mgt_clk), + .A0(plm_tsi3_VCC_1494), + .A1(plm_tsi3_VCC_1494), + .A2(plm_tsi3_VCC_1494), + .A3(plm_tsi3_GND_1493) + ); + SRL16 plm_tsi3_reg_dec7_0_I_1 ( + .D(plm_reg_pad_4_1[0]), + .Q(plm_tsi3_reg_dec7_0_N_6), + .CLK(mgt_clk), + .A0(plm_tsi3_VCC_1494), + .A1(plm_tsi3_VCC_1494), + .A2(plm_tsi3_VCC_1494), + .A3(plm_tsi3_GND_1493) + ); + SRL16 plm_tsi3_reg_dec5_I_1 ( + .D(plm_rx3_des_sym[1]), + .Q(plm_tsi3_reg_dec5_N_6), + .CLK(mgt_clk), + .A0(plm_tsi3_VCC_1494), + .A1(plm_tsi3_VCC_1494), + .A2(plm_tsi3_GND_1493), + .A3(plm_tsi3_GND_1493) + ); + SRL16 plm_tsi3_reg_dec7_I_1 ( + .D(plm_reg_pad_3_1[1]), + .Q(plm_tsi3_reg_dec7_N_6), + .CLK(mgt_clk), + .A0(plm_tsi3_VCC_1494), + .A1(plm_tsi3_VCC_1494), + .A2(plm_tsi3_VCC_1494), + .A3(plm_tsi3_GND_1493) + ); + defparam plm_dfm_prel_sdpstp_0_1_.INIT = 8'hD8; + LUT3 plm_dfm_prel_sdpstp_0_1_ ( + .I0(cmmp_negotiated_width[0]), + .I1(plm_dfm_by1_prel_sdpstp[1]), + .I2(plm_dfm_by4_prel_sdpstp[1]), + .O(plm_dfm_prel_sdpstp[1]) + ); + defparam plm_dfm_preh_sdpstp_i_m3_0_0_.INIT = 8'hD8; + LUT3 plm_dfm_preh_sdpstp_i_m3_0_0_ ( + .I0(cmmp_negotiated_width[0]), + .I1(plm_dfm_by1_preh_sdpstp[0]), + .I2(plm_dfm_by4_preh_sdpstp[0]), + .O(plm_dfm_preh_sdpstp_i_m3_0[0]) + ); + defparam plm_dfm_preh_sdpstp_i_m3_0_1_.INIT = 8'hD8; + LUT3 plm_dfm_preh_sdpstp_i_m3_0_1_ ( + .I0(cmmp_negotiated_width[0]), + .I1(plm_dfm_by1_preh_sdpstp[1]), + .I2(plm_dfm_by4_preh_sdpstp[1]), + .O(plm_dfm_preh_sdpstp_i_m3_0[1]) + ); + defparam plm_dfm_prel_sdpstp_i_m3_0_0_.INIT = 8'hD8; + LUT3 plm_dfm_prel_sdpstp_i_m3_0_0_ ( + .I0(cmmp_negotiated_width[0]), + .I1(plm_dfm_by1_prel_sdpstp[0]), + .I2(plm_dfm_by4_prel_sdpstp[0]), + .O(plm_dfm_prel_sdpstp_i_m3_0[0]) + ); + defparam plm_dfm_prel_edbedg_i_m3_0_0_.INIT = 8'hD8; + LUT3 plm_dfm_prel_edbedg_i_m3_0_0_ ( + .I0(cmmp_negotiated_width[0]), + .I1(plm_dfm_by1_prel_edbedg[0]), + .I2(plm_dfm_by4_prel_edbedg[0]), + .O(plm_dfm_N_38141) + ); + defparam plm_dfm_preh_edbedg_i_m3_0_0_.INIT = 8'hD8; + LUT3 plm_dfm_preh_edbedg_i_m3_0_0_ ( + .I0(cmmp_negotiated_width[0]), + .I1(plm_dfm_by1_preh_edbedg[0]), + .I2(plm_dfm_by4_preh_edbedg[0]), + .O(plm_dfm_N_38113) + ); + defparam plm_dfm_N_9858_i_0_m2_0.INIT = 8'hA3; + LUT3_L plm_dfm_N_9858_i_0_m2_0 ( + .I0(plm_dfm_preh_sdpstp_i_m3_0[0]), + .I1(plm_dfm_preh_sdpstp_i_m3_0[1]), + .I2(phy_rctrl_l), + .LO(plm_dfm_N_9858_i_0_m2_0_1495) + ); + defparam plm_dfm_prec_rcverr_i_m3_0.INIT = 8'hD8; + LUT3_L plm_dfm_prec_rcverr_i_m3_0 ( + .I0(cmmp_negotiated_width[0]), + .I1(plm_dfm_by1_prec_rcverr), + .I2(plm_dfm_by4_prec_rcverr), + .LO(plm_dfm_prec_rcverr_i_m3_0_1496) + ); + defparam plm_dfm_preh_out_i_m3_0_31_.INIT = 8'hD8; + LUT3_L plm_dfm_preh_out_i_m3_0_31_ ( + .I0(cmmp_negotiated_width[0]), + .I1(plm_dfm_by1_preh_out[31]), + .I2(plm_dfm_by4_preh_out[31]), + .LO(plm_dfm_preh_out_i_m3_0[31]) + ); + defparam plm_dfm_preh_out_i_m3_0_30_.INIT = 8'hD8; + LUT3_L plm_dfm_preh_out_i_m3_0_30_ ( + .I0(cmmp_negotiated_width[0]), + .I1(plm_dfm_by1_preh_out[30]), + .I2(plm_dfm_by4_preh_out[30]), + .LO(plm_dfm_preh_out_i_m3_0[30]) + ); + defparam plm_dfm_preh_out_i_m3_0_29_.INIT = 8'hD8; + LUT3_L plm_dfm_preh_out_i_m3_0_29_ ( + .I0(cmmp_negotiated_width[0]), + .I1(plm_dfm_by1_preh_out[29]), + .I2(plm_dfm_by4_preh_out[29]), + .LO(plm_dfm_preh_out_i_m3_0[29]) + ); + defparam plm_dfm_preh_out_i_m3_0_28_.INIT = 8'hD8; + LUT3_L plm_dfm_preh_out_i_m3_0_28_ ( + .I0(cmmp_negotiated_width[0]), + .I1(plm_dfm_by1_preh_out[28]), + .I2(plm_dfm_by4_preh_out[28]), + .LO(plm_dfm_preh_out_i_m3_0[28]) + ); + defparam plm_dfm_preh_out_i_m3_0_27_.INIT = 8'hD8; + LUT3_L plm_dfm_preh_out_i_m3_0_27_ ( + .I0(cmmp_negotiated_width[0]), + .I1(plm_dfm_by1_preh_out[27]), + .I2(plm_dfm_by4_preh_out[27]), + .LO(plm_dfm_preh_out_i_m3_0[27]) + ); + defparam plm_dfm_preh_out_i_m3_0_26_.INIT = 8'hD8; + LUT3_L plm_dfm_preh_out_i_m3_0_26_ ( + .I0(cmmp_negotiated_width[0]), + .I1(plm_dfm_by1_preh_out[26]), + .I2(plm_dfm_by4_preh_out[26]), + .LO(plm_dfm_preh_out_i_m3_0[26]) + ); + defparam plm_dfm_preh_out_i_m3_0_25_.INIT = 8'hD8; + LUT3_L plm_dfm_preh_out_i_m3_0_25_ ( + .I0(cmmp_negotiated_width[0]), + .I1(plm_dfm_by1_preh_out[25]), + .I2(plm_dfm_by4_preh_out[25]), + .LO(plm_dfm_preh_out_i_m3_0[25]) + ); + defparam plm_dfm_preh_out_i_m3_0_24_.INIT = 8'hD8; + LUT3_L plm_dfm_preh_out_i_m3_0_24_ ( + .I0(cmmp_negotiated_width[0]), + .I1(plm_dfm_by1_preh_out[24]), + .I2(plm_dfm_by4_preh_out[24]), + .LO(plm_dfm_preh_out_i_m3_0[24]) + ); + defparam plm_dfm_preh_out_i_m3_0_23_.INIT = 8'hD8; + LUT3_L plm_dfm_preh_out_i_m3_0_23_ ( + .I0(cmmp_negotiated_width[0]), + .I1(plm_dfm_by1_preh_out[23]), + .I2(plm_dfm_by4_preh_out[23]), + .LO(plm_dfm_preh_out_i_m3_0[23]) + ); + defparam plm_dfm_preh_out_i_m3_0_22_.INIT = 8'hD8; + LUT3_L plm_dfm_preh_out_i_m3_0_22_ ( + .I0(cmmp_negotiated_width[0]), + .I1(plm_dfm_by1_preh_out[22]), + .I2(plm_dfm_by4_preh_out[22]), + .LO(plm_dfm_preh_out_i_m3_0[22]) + ); + defparam plm_dfm_preh_out_i_m3_0_21_.INIT = 8'hD8; + LUT3_L plm_dfm_preh_out_i_m3_0_21_ ( + .I0(cmmp_negotiated_width[0]), + .I1(plm_dfm_by1_preh_out[21]), + .I2(plm_dfm_by4_preh_out[21]), + .LO(plm_dfm_preh_out_i_m3_0[21]) + ); + defparam plm_dfm_preh_out_i_m3_0_20_.INIT = 8'hD8; + LUT3_L plm_dfm_preh_out_i_m3_0_20_ ( + .I0(cmmp_negotiated_width[0]), + .I1(plm_dfm_by1_preh_out[20]), + .I2(plm_dfm_by4_preh_out[20]), + .LO(plm_dfm_preh_out_i_m3_0[20]) + ); + defparam plm_dfm_preh_out_i_m3_0_19_.INIT = 8'hD8; + LUT3_L plm_dfm_preh_out_i_m3_0_19_ ( + .I0(cmmp_negotiated_width[0]), + .I1(plm_dfm_by1_preh_out[19]), + .I2(plm_dfm_by4_preh_out[19]), + .LO(plm_dfm_preh_out_i_m3_0[19]) + ); + defparam plm_dfm_preh_out_i_m3_0_18_.INIT = 8'hD8; + LUT3_L plm_dfm_preh_out_i_m3_0_18_ ( + .I0(cmmp_negotiated_width[0]), + .I1(plm_dfm_by1_preh_out[18]), + .I2(plm_dfm_by4_preh_out[18]), + .LO(plm_dfm_preh_out_i_m3_0[18]) + ); + defparam plm_dfm_preh_out_i_m3_0_17_.INIT = 8'hD8; + LUT3_L plm_dfm_preh_out_i_m3_0_17_ ( + .I0(cmmp_negotiated_width[0]), + .I1(plm_dfm_by1_preh_out[17]), + .I2(plm_dfm_by4_preh_out[17]), + .LO(plm_dfm_preh_out_i_m3_0[17]) + ); + defparam plm_dfm_preh_out_i_m3_0_16_.INIT = 8'hD8; + LUT3_L plm_dfm_preh_out_i_m3_0_16_ ( + .I0(cmmp_negotiated_width[0]), + .I1(plm_dfm_by1_preh_out[16]), + .I2(plm_dfm_by4_preh_out[16]), + .LO(plm_dfm_preh_out_i_m3_0[16]) + ); + defparam plm_dfm_preh_out_i_m3_0_15_.INIT = 8'hD8; + LUT3_L plm_dfm_preh_out_i_m3_0_15_ ( + .I0(cmmp_negotiated_width[0]), + .I1(plm_dfm_by1_preh_out[15]), + .I2(plm_dfm_by4_preh_out[15]), + .LO(plm_dfm_preh_out_i_m3_0[15]) + ); + defparam plm_dfm_preh_out_i_m3_0_14_.INIT = 8'hD8; + LUT3_L plm_dfm_preh_out_i_m3_0_14_ ( + .I0(cmmp_negotiated_width[0]), + .I1(plm_dfm_by1_preh_out[14]), + .I2(plm_dfm_by4_preh_out[14]), + .LO(plm_dfm_preh_out_i_m3_0[14]) + ); + defparam plm_dfm_preh_out_i_m3_0_13_.INIT = 8'hD8; + LUT3_L plm_dfm_preh_out_i_m3_0_13_ ( + .I0(cmmp_negotiated_width[0]), + .I1(plm_dfm_by1_preh_out[13]), + .I2(plm_dfm_by4_preh_out[13]), + .LO(plm_dfm_preh_out_i_m3_0[13]) + ); + defparam plm_dfm_preh_out_i_m3_0_12_.INIT = 8'hD8; + LUT3_L plm_dfm_preh_out_i_m3_0_12_ ( + .I0(cmmp_negotiated_width_1[0]), + .I1(plm_dfm_by1_preh_out[12]), + .I2(plm_dfm_by4_preh_out[12]), + .LO(plm_dfm_preh_out_i_m3_0[12]) + ); + defparam plm_dfm_preh_out_i_m3_0_11_.INIT = 8'hD8; + LUT3_L plm_dfm_preh_out_i_m3_0_11_ ( + .I0(cmmp_negotiated_width_1[0]), + .I1(plm_dfm_by1_preh_out[11]), + .I2(plm_dfm_by4_preh_out[11]), + .LO(plm_dfm_preh_out_i_m3_0[11]) + ); + defparam plm_dfm_preh_out_i_m3_0_10_.INIT = 8'hD8; + LUT3_L plm_dfm_preh_out_i_m3_0_10_ ( + .I0(cmmp_negotiated_width_1[0]), + .I1(plm_dfm_by1_preh_out[10]), + .I2(plm_dfm_by4_preh_out[10]), + .LO(plm_dfm_preh_out_i_m3_0[10]) + ); + defparam plm_dfm_preh_out_i_m3_0_9_.INIT = 8'hD8; + LUT3_L plm_dfm_preh_out_i_m3_0_9_ ( + .I0(cmmp_negotiated_width_1[0]), + .I1(plm_dfm_by1_preh_out[9]), + .I2(plm_dfm_by4_preh_out[9]), + .LO(plm_dfm_preh_out_i_m3_0[9]) + ); + defparam plm_dfm_preh_out_i_m3_0_8_.INIT = 8'hD8; + LUT3_L plm_dfm_preh_out_i_m3_0_8_ ( + .I0(cmmp_negotiated_width_1[0]), + .I1(plm_dfm_by1_preh_out[8]), + .I2(plm_dfm_by4_preh_out[8]), + .LO(plm_dfm_preh_out_i_m3_0[8]) + ); + defparam plm_dfm_preh_out_i_m3_0_7_.INIT = 8'hD8; + LUT3_L plm_dfm_preh_out_i_m3_0_7_ ( + .I0(cmmp_negotiated_width_1[0]), + .I1(plm_dfm_by1_preh_out[7]), + .I2(plm_dfm_by4_preh_out[7]), + .LO(plm_dfm_preh_out_i_m3_0[7]) + ); + defparam plm_dfm_preh_out_i_m3_0_6_.INIT = 8'hD8; + LUT3_L plm_dfm_preh_out_i_m3_0_6_ ( + .I0(cmmp_negotiated_width_1[0]), + .I1(plm_dfm_by1_preh_out[6]), + .I2(plm_dfm_by4_preh_out[6]), + .LO(plm_dfm_preh_out_i_m3_0[6]) + ); + defparam plm_dfm_preh_out_i_m3_0_5_.INIT = 8'hD8; + LUT3_L plm_dfm_preh_out_i_m3_0_5_ ( + .I0(cmmp_negotiated_width_1[0]), + .I1(plm_dfm_by1_preh_out[5]), + .I2(plm_dfm_by4_preh_out[5]), + .LO(plm_dfm_preh_out_i_m3_0[5]) + ); + defparam plm_dfm_preh_out_i_m3_0_4_.INIT = 8'hD8; + LUT3_L plm_dfm_preh_out_i_m3_0_4_ ( + .I0(cmmp_negotiated_width_1[0]), + .I1(plm_dfm_by1_preh_out[4]), + .I2(plm_dfm_by4_preh_out[4]), + .LO(plm_dfm_preh_out_i_m3_0[4]) + ); + defparam plm_dfm_preh_out_i_m3_0_3_.INIT = 8'hD8; + LUT3_L plm_dfm_preh_out_i_m3_0_3_ ( + .I0(cmmp_negotiated_width_1[0]), + .I1(plm_dfm_by1_preh_out[3]), + .I2(plm_dfm_by4_preh_out[3]), + .LO(plm_dfm_preh_out_i_m3_0[3]) + ); + defparam plm_dfm_preh_out_i_m3_0_2_.INIT = 8'hD8; + LUT3_L plm_dfm_preh_out_i_m3_0_2_ ( + .I0(cmmp_negotiated_width_1[0]), + .I1(plm_dfm_by1_preh_out[2]), + .I2(plm_dfm_by4_preh_out[2]), + .LO(plm_dfm_preh_out_i_m3_0[2]) + ); + defparam plm_dfm_preh_out_i_m3_0_1_.INIT = 8'hD8; + LUT3_L plm_dfm_preh_out_i_m3_0_1_ ( + .I0(cmmp_negotiated_width_1[0]), + .I1(plm_dfm_by1_preh_out[1]), + .I2(plm_dfm_by4_preh_out[1]), + .LO(plm_dfm_preh_out_i_m3_0[1]) + ); + defparam plm_dfm_preh_out_i_m3_0_0_.INIT = 8'hD8; + LUT3_L plm_dfm_preh_out_i_m3_0_0_ ( + .I0(cmmp_negotiated_width_1[0]), + .I1(plm_dfm_by1_preh_out[0]), + .I2(plm_dfm_by4_preh_out[0]), + .LO(plm_dfm_preh_out_i_m3_0[0]) + ); + defparam plm_dfm_prel_out_i_m3_0_31_.INIT = 8'hD8; + LUT3_L plm_dfm_prel_out_i_m3_0_31_ ( + .I0(cmmp_negotiated_width_1[0]), + .I1(plm_dfm_by1_prel_out[31]), + .I2(plm_dfm_by4_prel_out[31]), + .LO(plm_dfm_prel_out_i_m3_0_31__1497) + ); + defparam plm_dfm_prel_out_i_m3_0_30_.INIT = 8'hD8; + LUT3_L plm_dfm_prel_out_i_m3_0_30_ ( + .I0(cmmp_negotiated_width_1[0]), + .I1(plm_dfm_by1_prel_out[30]), + .I2(plm_dfm_by4_prel_out[30]), + .LO(plm_dfm_prel_out_i_m3_0_30__1498) + ); + defparam plm_dfm_prel_out_i_m3_0_29_.INIT = 8'hD8; + LUT3_L plm_dfm_prel_out_i_m3_0_29_ ( + .I0(cmmp_negotiated_width_1[0]), + .I1(plm_dfm_by1_prel_out[29]), + .I2(plm_dfm_by4_prel_out[29]), + .LO(plm_dfm_prel_out_i_m3_0_29__1499) + ); + defparam plm_dfm_prel_out_i_m3_0_28_.INIT = 8'hD8; + LUT3_L plm_dfm_prel_out_i_m3_0_28_ ( + .I0(cmmp_negotiated_width_1[0]), + .I1(plm_dfm_by1_prel_out[28]), + .I2(plm_dfm_by4_prel_out[28]), + .LO(plm_dfm_prel_out_i_m3_0_28__1500) + ); + defparam plm_dfm_prel_out_i_m2_0_27_.INIT = 8'hD8; + LUT3_L plm_dfm_prel_out_i_m2_0_27_ ( + .I0(cmmp_negotiated_width_1[0]), + .I1(plm_dfm_by1_prel_out[27]), + .I2(plm_dfm_by4_prel_out[27]), + .LO(plm_dfm_prel_out_i_m2_0[27]) + ); + defparam plm_dfm_prel_out_0_26_.INIT = 8'hD8; + LUT3_L plm_dfm_prel_out_0_26_ ( + .I0(cmmp_negotiated_width_1[0]), + .I1(plm_dfm_by1_prel_out[26]), + .I2(plm_dfm_by4_prel_out[26]), + .LO(plm_dfm_prel_out[26]) + ); + defparam plm_dfm_prel_out_0_25_.INIT = 8'hD8; + LUT3_L plm_dfm_prel_out_0_25_ ( + .I0(cmmp_negotiated_width_1[0]), + .I1(plm_dfm_by1_prel_out[25]), + .I2(plm_dfm_by4_prel_out[25]), + .LO(plm_dfm_prel_out[25]) + ); + defparam plm_dfm_prel_out_0_24_.INIT = 8'hD8; + LUT3_L plm_dfm_prel_out_0_24_ ( + .I0(cmmp_negotiated_width_1[0]), + .I1(plm_dfm_by1_prel_out[24]), + .I2(plm_dfm_by4_prel_out[24]), + .LO(plm_dfm_prel_out[24]) + ); + defparam plm_dfm_prel_out_0_23_.INIT = 8'hD8; + LUT3_L plm_dfm_prel_out_0_23_ ( + .I0(cmmp_negotiated_width_1[0]), + .I1(plm_dfm_by1_prel_out[23]), + .I2(plm_dfm_by4_prel_out[23]), + .LO(plm_dfm_prel_out[23]) + ); + defparam plm_dfm_prel_out_0_22_.INIT = 8'hD8; + LUT3_L plm_dfm_prel_out_0_22_ ( + .I0(cmmp_negotiated_width_1[0]), + .I1(plm_dfm_by1_prel_out[22]), + .I2(plm_dfm_by4_prel_out[22]), + .LO(plm_dfm_prel_out[22]) + ); + defparam plm_dfm_prel_out_0_21_.INIT = 8'hD8; + LUT3_L plm_dfm_prel_out_0_21_ ( + .I0(cmmp_negotiated_width_1[0]), + .I1(plm_dfm_by1_prel_out[21]), + .I2(plm_dfm_by4_prel_out[21]), + .LO(plm_dfm_prel_out[21]) + ); + defparam plm_dfm_prel_out_i_m3_0_20_.INIT = 8'hD8; + LUT3_L plm_dfm_prel_out_i_m3_0_20_ ( + .I0(cmmp_negotiated_width_1[0]), + .I1(plm_dfm_by1_prel_out[20]), + .I2(plm_dfm_by4_prel_out[20]), + .LO(plm_dfm_prel_out_i_m3_0_20__1501) + ); + defparam plm_dfm_prel_out_i_m3_0_19_.INIT = 8'hD8; + LUT3_L plm_dfm_prel_out_i_m3_0_19_ ( + .I0(cmmp_negotiated_width_1[0]), + .I1(plm_dfm_by1_prel_out[19]), + .I2(plm_dfm_by4_prel_out[19]), + .LO(plm_dfm_prel_out_i_m3_0_19__1502) + ); + defparam plm_dfm_prel_out_i_m3_0_18_.INIT = 8'hD8; + LUT3_L plm_dfm_prel_out_i_m3_0_18_ ( + .I0(cmmp_negotiated_width_1[0]), + .I1(plm_dfm_by1_prel_out[18]), + .I2(plm_dfm_by4_prel_out[18]), + .LO(plm_dfm_prel_out_i_m3_0_18__1503) + ); + defparam plm_dfm_prel_out_i_m3_0_17_.INIT = 8'hD8; + LUT3_L plm_dfm_prel_out_i_m3_0_17_ ( + .I0(cmmp_negotiated_width_1[0]), + .I1(plm_dfm_by1_prel_out[17]), + .I2(plm_dfm_by4_prel_out[17]), + .LO(plm_dfm_prel_out_i_m3_0_17__1504) + ); + defparam plm_dfm_prel_out_i_m3_0_16_.INIT = 8'hD8; + LUT3_L plm_dfm_prel_out_i_m3_0_16_ ( + .I0(cmmp_negotiated_width_1[0]), + .I1(plm_dfm_by1_prel_out[16]), + .I2(plm_dfm_by4_prel_out[16]), + .LO(plm_dfm_prel_out_i_m3_0_16__1505) + ); + defparam plm_dfm_prel_out_i_m3_0_15_.INIT = 8'hD8; + LUT3_L plm_dfm_prel_out_i_m3_0_15_ ( + .I0(cmmp_negotiated_width_1[0]), + .I1(plm_dfm_by1_prel_out[15]), + .I2(plm_dfm_by4_prel_out[15]), + .LO(plm_dfm_prel_out_i_m3_0_15__1506) + ); + defparam plm_dfm_prel_out_i_m3_0_14_.INIT = 8'hD8; + LUT3_L plm_dfm_prel_out_i_m3_0_14_ ( + .I0(cmmp_negotiated_width_1[0]), + .I1(plm_dfm_by1_prel_out[14]), + .I2(plm_dfm_by4_prel_out[14]), + .LO(plm_dfm_prel_out_i_m3_0_14__1507) + ); + defparam plm_dfm_prel_out_i_m3_0_13_.INIT = 8'hD8; + LUT3_L plm_dfm_prel_out_i_m3_0_13_ ( + .I0(cmmp_negotiated_width_1[0]), + .I1(plm_dfm_by1_prel_out[13]), + .I2(plm_dfm_by4_prel_out[13]), + .LO(plm_dfm_prel_out_i_m3_0_13__1508) + ); + defparam plm_dfm_prel_out_i_m3_0_12_.INIT = 8'hD8; + LUT3_L plm_dfm_prel_out_i_m3_0_12_ ( + .I0(cmmp_negotiated_width_1[0]), + .I1(plm_dfm_by1_prel_out[12]), + .I2(plm_dfm_by4_prel_out[12]), + .LO(plm_dfm_prel_out_i_m3_0_12__1509) + ); + defparam plm_dfm_prel_out_i_m3_0_11_.INIT = 8'hD8; + LUT3_L plm_dfm_prel_out_i_m3_0_11_ ( + .I0(cmmp_negotiated_width_1[0]), + .I1(plm_dfm_by1_prel_out[11]), + .I2(plm_dfm_by4_prel_out[11]), + .LO(plm_dfm_prel_out_i_m3_0_11__1510) + ); + defparam plm_dfm_prel_out_i_m3_0_10_.INIT = 8'hD8; + LUT3_L plm_dfm_prel_out_i_m3_0_10_ ( + .I0(cmmp_negotiated_width_1[0]), + .I1(plm_dfm_by1_prel_out[10]), + .I2(plm_dfm_by4_prel_out[10]), + .LO(plm_dfm_prel_out_i_m3_0_10__1511) + ); + defparam plm_dfm_prel_out_i_m3_0_9_.INIT = 8'hD8; + LUT3_L plm_dfm_prel_out_i_m3_0_9_ ( + .I0(cmmp_negotiated_width_1[0]), + .I1(plm_dfm_by1_prel_out[9]), + .I2(plm_dfm_by4_prel_out[9]), + .LO(plm_dfm_prel_out_i_m3_0_9__1512) + ); + defparam plm_dfm_prel_out_i_m3_0_8_.INIT = 8'hD8; + LUT3_L plm_dfm_prel_out_i_m3_0_8_ ( + .I0(cmmp_negotiated_width_1[0]), + .I1(plm_dfm_by1_prel_out[8]), + .I2(plm_dfm_by4_prel_out[8]), + .LO(plm_dfm_prel_out_i_m3_0_8__1513) + ); + defparam plm_dfm_prel_out_i_m3_0_7_.INIT = 8'hD8; + LUT3_L plm_dfm_prel_out_i_m3_0_7_ ( + .I0(cmmp_negotiated_width_1[0]), + .I1(plm_dfm_by1_prel_out[7]), + .I2(plm_dfm_by4_prel_out[7]), + .LO(plm_dfm_prel_out_i_m3_0_7__1514) + ); + defparam plm_dfm_prel_out_i_m3_0_6_.INIT = 8'hD8; + LUT3_L plm_dfm_prel_out_i_m3_0_6_ ( + .I0(cmmp_negotiated_width_1[0]), + .I1(plm_dfm_by1_prel_out[6]), + .I2(plm_dfm_by4_prel_out[6]), + .LO(plm_dfm_prel_out_i_m3_0_6__1515) + ); + defparam plm_dfm_prel_out_i_m3_0_5_.INIT = 8'hD8; + LUT3_L plm_dfm_prel_out_i_m3_0_5_ ( + .I0(cmmp_negotiated_width_1[0]), + .I1(plm_dfm_by1_prel_out[5]), + .I2(plm_dfm_by4_prel_out[5]), + .LO(plm_dfm_prel_out_i_m3_0_5__1516) + ); + defparam plm_dfm_prel_out_i_m3_0_4_.INIT = 8'hD8; + LUT3_L plm_dfm_prel_out_i_m3_0_4_ ( + .I0(cmmp_negotiated_width_1[0]), + .I1(plm_dfm_by1_prel_out[4]), + .I2(plm_dfm_by4_prel_out[4]), + .LO(plm_dfm_prel_out_i_m3_0_4__1517) + ); + defparam plm_dfm_prel_out_i_m3_0_3_.INIT = 8'hD8; + LUT3_L plm_dfm_prel_out_i_m3_0_3_ ( + .I0(cmmp_negotiated_width_1[0]), + .I1(plm_dfm_by1_prel_out[3]), + .I2(plm_dfm_by4_prel_out[3]), + .LO(plm_dfm_prel_out_i_m3_0_3__1518) + ); + defparam plm_dfm_prel_out_i_m3_0_2_.INIT = 8'hD8; + LUT3_L plm_dfm_prel_out_i_m3_0_2_ ( + .I0(cmmp_negotiated_width_1[0]), + .I1(plm_dfm_by1_prel_out[2]), + .I2(plm_dfm_by4_prel_out[2]), + .LO(plm_dfm_prel_out_i_m3_0_2__1519) + ); + defparam plm_dfm_prel_out_i_m3_0_1_.INIT = 8'hD8; + LUT3_L plm_dfm_prel_out_i_m3_0_1_ ( + .I0(cmmp_negotiated_width_1[0]), + .I1(plm_dfm_by1_prel_out[1]), + .I2(plm_dfm_by4_prel_out[1]), + .LO(plm_dfm_prel_out_i_m3_0_1__1520) + ); + defparam plm_dfm_prel_out_i_m3_0_0_.INIT = 8'hD8; + LUT3_L plm_dfm_prel_out_i_m3_0_0_ ( + .I0(cmmp_negotiated_width_1[0]), + .I1(plm_dfm_by1_prel_out[0]), + .I2(plm_dfm_by4_prel_out[0]), + .LO(plm_dfm_prel_out_i_m3_0_0__1521) + ); + defparam plm_dfm_not_my_prob_after_this_reg_phy_rframe_h_3.INIT = 8'h96; + LUT3_L plm_dfm_not_my_prob_after_this_reg_phy_rframe_h_3 ( + .I0(plm_dfm_preh_sdpstp_i_m3_0[0]), + .I1(plm_dfm_preh_sdpstp_i_m3_0[1]), + .I2(phy_rframe_h), + .LO(plm_dfm_reg_phy_rframe_h_3) + ); + defparam plm_dfm_not_my_prob_after_this_reg_phy_rframe_l_3.INIT = 8'h96; + LUT3_L plm_dfm_not_my_prob_after_this_reg_phy_rframe_l_3 ( + .I0(plm_dfm_prel_sdpstp_i_m3_0[0]), + .I1(phy_rframe_l), + .I2(plm_dfm_prel_sdpstp[1]), + .LO(plm_dfm_reg_phy_rframe_l_3) + ); + defparam plm_dfm_not_my_prob_after_this_reg_phy_rbad_dfrm_h_3_0_a2.INIT = 16'h5140; + LUT4_L plm_dfm_not_my_prob_after_this_reg_phy_rbad_dfrm_h_3_0_a2 ( + .I0(plm_dfm_N_38113), + .I1(cmmp_negotiated_width_1[0]), + .I2(plm_dfm_by1_preh_edbedg[1]), + .I3(plm_dfm_by4_preh_edbedg[1]), + .LO(plm_dfm_reg_phy_rbad_dfrm_h_3) + ); + defparam plm_dfm_not_my_prob_after_this_reg_phy_rbad_dfrm_l_3_0_a2.INIT = 16'h5140; + LUT4_L plm_dfm_not_my_prob_after_this_reg_phy_rbad_dfrm_l_3_0_a2 ( + .I0(plm_dfm_N_38141), + .I1(cmmp_negotiated_width_1[0]), + .I2(plm_dfm_by1_prel_edbedg[1]), + .I3(plm_dfm_by4_prel_edbedg[1]), + .LO(plm_dfm_reg_phy_rbad_dfrm_l_3) + ); + defparam plm_dfm_not_my_prob_after_this_un4_reg_phy_ferr_h_n_i.INIT = 16'h5D7F; + LUT4_L plm_dfm_not_my_prob_after_this_un4_reg_phy_ferr_h_n_i ( + .I0(plm_dfm_N_38113), + .I1(cmmp_negotiated_width_1[0]), + .I2(plm_dfm_by1_preh_edbedg[1]), + .I3(plm_dfm_by4_preh_edbedg[1]), + .LO(plm_dfm_un4_reg_phy_ferr_h_n_i) + ); + defparam plm_dfm_not_my_prob_after_this_un4_reg_phy_ferr_l_n_i.INIT = 16'h5D7F; + LUT4_L plm_dfm_not_my_prob_after_this_un4_reg_phy_ferr_l_n_i ( + .I0(plm_dfm_N_38141), + .I1(cmmp_negotiated_width_1[0]), + .I2(plm_dfm_by1_prel_edbedg[1]), + .I3(plm_dfm_by4_prel_edbedg[1]), + .LO(plm_dfm_un4_reg_phy_ferr_l_n_i) + ); + defparam plm_dfm_ns_phy_rctrl_l_iv_0_m2_0.INIT = 8'hB1; + LUT3_L plm_dfm_ns_phy_rctrl_l_iv_0_m2_0 ( + .I0(plm_dfm_N_9858_i_0_m2_0_1495), + .I1(plm_dfm_prel_sdpstp_i_m3_0[0]), + .I2(plm_dfm_prel_sdpstp[1]), + .LO(plm_dfm_ns_phy_rctrl_l_iv_0_m2_0_1522) + ); + FDC plm_dfm_reg_phy_rerr ( + .C(mgt_clk), + .D(plm_dfm_prec_rcverr_i_m3_0_1496), + .Q(cmmp_receiver_err), + .CLR(plm_rst) + ); + FDPE plm_dfm_reg_phy_rd_63_ ( + .PRE(plm_rst), + .CE(plm_phy_cke_1_711), + .C(mgt_clk), + .D(plm_dfm_preh_out_i_m3_0[31]), + .Q(phy_rd[63]) + ); + FDPE plm_dfm_reg_phy_rd_62_ ( + .PRE(plm_rst), + .CE(plm_phy_cke_1_711), + .C(mgt_clk), + .D(plm_dfm_preh_out_i_m3_0[30]), + .Q(phy_rd[62]) + ); + FDPE plm_dfm_reg_phy_rd_61_ ( + .PRE(plm_rst), + .CE(plm_phy_cke_1_711), + .C(mgt_clk), + .D(plm_dfm_preh_out_i_m3_0[29]), + .Q(phy_rd[61]) + ); + FDPE plm_dfm_reg_phy_rd_60_ ( + .PRE(plm_rst), + .CE(plm_phy_cke_1_711), + .C(mgt_clk), + .D(plm_dfm_preh_out_i_m3_0[28]), + .Q(phy_rd[60]) + ); + FDPE plm_dfm_reg_phy_rd_59_ ( + .PRE(plm_rst), + .CE(plm_phy_cke_1_711), + .C(mgt_clk), + .D(plm_dfm_preh_out_i_m3_0[27]), + .Q(phy_rd[59]) + ); + FDPE plm_dfm_reg_phy_rd_58_ ( + .PRE(plm_rst), + .CE(plm_phy_cke_1_711), + .C(mgt_clk), + .D(plm_dfm_preh_out_i_m3_0[26]), + .Q(phy_rd[58]) + ); + FDPE plm_dfm_reg_phy_rd_57_ ( + .PRE(plm_rst), + .CE(plm_phy_cke_1_711), + .C(mgt_clk), + .D(plm_dfm_preh_out_i_m3_0[25]), + .Q(phy_rd[57]) + ); + FDPE plm_dfm_reg_phy_rd_56_ ( + .PRE(plm_rst), + .CE(plm_phy_cke_1_711), + .C(mgt_clk), + .D(plm_dfm_preh_out_i_m3_0[24]), + .Q(phy_rd[56]) + ); + FDCE plm_dfm_reg_phy_rd_55_ ( + .CE(plm_phy_cke_1_711), + .C(mgt_clk), + .D(plm_dfm_preh_out_i_m3_0[23]), + .Q(phy_rd[55]), + .CLR(plm_rst) + ); + FDCE plm_dfm_reg_phy_rd_54_ ( + .CE(plm_phy_cke_1_711), + .C(mgt_clk), + .D(plm_dfm_preh_out_i_m3_0[22]), + .Q(phy_rd[54]), + .CLR(plm_rst) + ); + FDCE plm_dfm_reg_phy_rd_53_ ( + .CE(plm_phy_cke_1_711), + .C(mgt_clk), + .D(plm_dfm_preh_out_i_m3_0[21]), + .Q(phy_rd[53]), + .CLR(plm_rst) + ); + FDCE plm_dfm_reg_phy_rd_52_ ( + .CE(plm_phy_cke_1_711), + .C(mgt_clk), + .D(plm_dfm_preh_out_i_m3_0[20]), + .Q(phy_rd[52]), + .CLR(plm_rst) + ); + FDCE plm_dfm_reg_phy_rd_51_ ( + .CE(plm_phy_cke_1_711), + .C(mgt_clk), + .D(plm_dfm_preh_out_i_m3_0[19]), + .Q(phy_rd[51]), + .CLR(plm_rst) + ); + FDCE plm_dfm_reg_phy_rd_50_ ( + .CE(plm_phy_cke_1_711), + .C(mgt_clk), + .D(plm_dfm_preh_out_i_m3_0[18]), + .Q(phy_rd[50]), + .CLR(plm_rst) + ); + FDCE plm_dfm_reg_phy_rd_49_ ( + .CE(plm_phy_cke_1_711), + .C(mgt_clk), + .D(plm_dfm_preh_out_i_m3_0[17]), + .Q(phy_rd[49]), + .CLR(plm_rst) + ); + FDCE plm_dfm_reg_phy_rd_48_ ( + .CE(plm_phy_cke_1_711), + .C(mgt_clk), + .D(plm_dfm_preh_out_i_m3_0[16]), + .Q(phy_rd[48]), + .CLR(plm_rst) + ); + FDCE plm_dfm_reg_phy_rd_47_ ( + .CE(plm_phy_cke_1_711), + .C(mgt_clk), + .D(plm_dfm_preh_out_i_m3_0[15]), + .Q(phy_rd[47]), + .CLR(plm_rst) + ); + FDCE plm_dfm_reg_phy_rd_46_ ( + .CE(plm_phy_cke_1_711), + .C(mgt_clk), + .D(plm_dfm_preh_out_i_m3_0[14]), + .Q(phy_rd[46]), + .CLR(plm_rst) + ); + FDCE plm_dfm_reg_phy_rd_45_ ( + .CE(plm_phy_cke_1_711), + .C(mgt_clk), + .D(plm_dfm_preh_out_i_m3_0[13]), + .Q(phy_rd[45]), + .CLR(plm_rst) + ); + FDCE plm_dfm_reg_phy_rd_44_ ( + .CE(plm_phy_cke_1_711), + .C(mgt_clk), + .D(plm_dfm_preh_out_i_m3_0[12]), + .Q(phy_rd[44]), + .CLR(plm_rst) + ); + FDCE plm_dfm_reg_phy_rd_43_ ( + .CE(plm_phy_cke_1_711), + .C(mgt_clk), + .D(plm_dfm_preh_out_i_m3_0[11]), + .Q(phy_rd[43]), + .CLR(plm_rst) + ); + FDCE plm_dfm_reg_phy_rd_42_ ( + .CE(plm_phy_cke_1_711), + .C(mgt_clk), + .D(plm_dfm_preh_out_i_m3_0[10]), + .Q(phy_rd[42]), + .CLR(plm_rst) + ); + FDCE plm_dfm_reg_phy_rd_41_ ( + .CE(plm_phy_cke_1_711), + .C(mgt_clk), + .D(plm_dfm_preh_out_i_m3_0[9]), + .Q(phy_rd[41]), + .CLR(plm_rst) + ); + FDCE plm_dfm_reg_phy_rd_40_ ( + .CE(plm_phy_cke_1_711), + .C(mgt_clk), + .D(plm_dfm_preh_out_i_m3_0[8]), + .Q(phy_rd[40]), + .CLR(plm_rst) + ); + FDCE plm_dfm_reg_phy_rd_39_ ( + .CE(plm_phy_cke_1_711), + .C(mgt_clk), + .D(plm_dfm_preh_out_i_m3_0[7]), + .Q(phy_rd[39]), + .CLR(plm_rst) + ); + FDCE plm_dfm_reg_phy_rd_38_ ( + .CE(plm_phy_cke_1_711), + .C(mgt_clk), + .D(plm_dfm_preh_out_i_m3_0[6]), + .Q(phy_rd[38]), + .CLR(plm_rst) + ); + FDCE plm_dfm_reg_phy_rd_37_ ( + .CE(plm_phy_cke_1_711), + .C(mgt_clk), + .D(plm_dfm_preh_out_i_m3_0[5]), + .Q(phy_rd[37]), + .CLR(plm_rst) + ); + FDCE plm_dfm_reg_phy_rd_36_ ( + .CE(plm_phy_cke_1_711), + .C(mgt_clk), + .D(plm_dfm_preh_out_i_m3_0[4]), + .Q(phy_rd[36]), + .CLR(plm_rst) + ); + FDCE plm_dfm_reg_phy_rd_35_ ( + .CE(plm_phy_cke_1_711), + .C(mgt_clk), + .D(plm_dfm_preh_out_i_m3_0[3]), + .Q(phy_rd[35]), + .CLR(plm_rst) + ); + FDCE plm_dfm_reg_phy_rd_34_ ( + .CE(plm_phy_cke_0_712), + .C(mgt_clk), + .D(plm_dfm_preh_out_i_m3_0[2]), + .Q(phy_rd[34]), + .CLR(plm_rst) + ); + FDCE plm_dfm_reg_phy_rd_33_ ( + .CE(plm_phy_cke_0_712), + .C(mgt_clk), + .D(plm_dfm_preh_out_i_m3_0[1]), + .Q(phy_rd[33]), + .CLR(plm_rst) + ); + FDCE plm_dfm_reg_phy_rd_32_ ( + .CE(plm_phy_cke_0_712), + .C(mgt_clk), + .D(plm_dfm_preh_out_i_m3_0[0]), + .Q(phy_rd[32]), + .CLR(plm_rst) + ); + FDCE plm_dfm_reg_phy_rd_31_ ( + .CE(plm_phy_cke_0_712), + .C(mgt_clk), + .D(plm_dfm_prel_out_i_m3_0_31__1497), + .Q(phy_rd[31]), + .CLR(plm_rst) + ); + FDCE plm_dfm_reg_phy_rd_30_ ( + .CE(plm_phy_cke_0_712), + .C(mgt_clk), + .D(plm_dfm_prel_out_i_m3_0_30__1498), + .Q(phy_rd[30]), + .CLR(plm_rst) + ); + FDCE plm_dfm_reg_phy_rd_29_ ( + .CE(plm_phy_cke_0_712), + .C(mgt_clk), + .D(plm_dfm_prel_out_i_m3_0_29__1499), + .Q(phy_rd[29]), + .CLR(plm_rst) + ); + FDCE plm_dfm_reg_phy_rd_28_ ( + .CE(plm_phy_cke_0_712), + .C(mgt_clk), + .D(plm_dfm_prel_out_i_m3_0_28__1500), + .Q(phy_rd[28]), + .CLR(plm_rst) + ); + FDCE plm_dfm_reg_phy_rd_27_ ( + .CE(plm_phy_cke_0_712), + .C(mgt_clk), + .D(plm_dfm_prel_out_i_m2_0[27]), + .Q(phy_rd[27]), + .CLR(plm_rst) + ); + FDCE plm_dfm_reg_phy_rd_26_ ( + .CE(plm_phy_cke_0_712), + .C(mgt_clk), + .D(plm_dfm_prel_out[26]), + .Q(phy_rd[26]), + .CLR(plm_rst) + ); + FDCE plm_dfm_reg_phy_rd_25_ ( + .CE(plm_phy_cke_0_712), + .C(mgt_clk), + .D(plm_dfm_prel_out[25]), + .Q(phy_rd[25]), + .CLR(plm_rst) + ); + FDCE plm_dfm_reg_phy_rd_24_ ( + .CE(plm_phy_cke_0_712), + .C(mgt_clk), + .D(plm_dfm_prel_out[24]), + .Q(phy_rd[24]), + .CLR(plm_rst) + ); + FDCE plm_dfm_reg_phy_rd_23_ ( + .CE(plm_phy_cke_0_712), + .C(mgt_clk), + .D(plm_dfm_prel_out[23]), + .Q(phy_rd[23]), + .CLR(plm_rst) + ); + FDCE plm_dfm_reg_phy_rd_22_ ( + .CE(plm_phy_cke_0_712), + .C(mgt_clk), + .D(plm_dfm_prel_out[22]), + .Q(phy_rd[22]), + .CLR(plm_rst) + ); + FDCE plm_dfm_reg_phy_rd_21_ ( + .CE(plm_phy_cke_0_712), + .C(mgt_clk), + .D(plm_dfm_prel_out[21]), + .Q(phy_rd[21]), + .CLR(plm_rst) + ); + FDCE plm_dfm_reg_phy_rd_20_ ( + .CE(plm_phy_cke_0_712), + .C(mgt_clk), + .D(plm_dfm_prel_out_i_m3_0_20__1501), + .Q(phy_rd[20]), + .CLR(plm_rst) + ); + FDCE plm_dfm_reg_phy_rd_19_ ( + .CE(plm_phy_cke_0_712), + .C(mgt_clk), + .D(plm_dfm_prel_out_i_m3_0_19__1502), + .Q(phy_rd[19]), + .CLR(plm_rst) + ); + FDCE plm_dfm_reg_phy_rd_18_ ( + .CE(plm_phy_cke_0_712), + .C(mgt_clk), + .D(plm_dfm_prel_out_i_m3_0_18__1503), + .Q(phy_rd[18]), + .CLR(plm_rst) + ); + FDCE plm_dfm_reg_phy_rd_17_ ( + .CE(plm_phy_cke_0_712), + .C(mgt_clk), + .D(plm_dfm_prel_out_i_m3_0_17__1504), + .Q(phy_rd[17]), + .CLR(plm_rst) + ); + FDCE plm_dfm_reg_phy_rd_16_ ( + .CE(plm_phy_cke_0_712), + .C(mgt_clk), + .D(plm_dfm_prel_out_i_m3_0_16__1505), + .Q(phy_rd[16]), + .CLR(plm_rst) + ); + FDCE plm_dfm_reg_phy_rd_15_ ( + .CE(plm_phy_cke_0_712), + .C(mgt_clk), + .D(plm_dfm_prel_out_i_m3_0_15__1506), + .Q(phy_rd[15]), + .CLR(plm_rst) + ); + FDCE plm_dfm_reg_phy_rd_14_ ( + .CE(plm_phy_cke_0_712), + .C(mgt_clk), + .D(plm_dfm_prel_out_i_m3_0_14__1507), + .Q(phy_rd[14]), + .CLR(plm_rst) + ); + FDCE plm_dfm_reg_phy_rd_13_ ( + .CE(plm_phy_cke_0_712), + .C(mgt_clk), + .D(plm_dfm_prel_out_i_m3_0_13__1508), + .Q(phy_rd[13]), + .CLR(plm_rst) + ); + FDCE plm_dfm_reg_phy_rd_12_ ( + .CE(plm_phy_cke_0_712), + .C(mgt_clk), + .D(plm_dfm_prel_out_i_m3_0_12__1509), + .Q(phy_rd[12]), + .CLR(plm_rst) + ); + FDCE plm_dfm_reg_phy_rd_11_ ( + .CE(plm_phy_cke_0_712), + .C(mgt_clk), + .D(plm_dfm_prel_out_i_m3_0_11__1510), + .Q(phy_rd[11]), + .CLR(plm_rst) + ); + FDCE plm_dfm_reg_phy_rd_10_ ( + .CE(plm_phy_cke_0_712), + .C(mgt_clk), + .D(plm_dfm_prel_out_i_m3_0_10__1511), + .Q(phy_rd[10]), + .CLR(plm_rst) + ); + FDCE plm_dfm_reg_phy_rd_9_ ( + .CE(plm_phy_cke_0_712), + .C(mgt_clk), + .D(plm_dfm_prel_out_i_m3_0_9__1512), + .Q(phy_rd[9]), + .CLR(plm_rst) + ); + FDCE plm_dfm_reg_phy_rd_8_ ( + .CE(plm_phy_cke_0_712), + .C(mgt_clk), + .D(plm_dfm_prel_out_i_m3_0_8__1513), + .Q(phy_rd[8]), + .CLR(plm_rst) + ); + FDPE plm_dfm_reg_phy_rd_7_ ( + .PRE(plm_rst), + .CE(plm_phy_cke_0_712), + .C(mgt_clk), + .D(plm_dfm_prel_out_i_m3_0_7__1514), + .Q(phy_rd[7]) + ); + FDPE plm_dfm_reg_phy_rd_6_ ( + .PRE(plm_rst), + .CE(plm_phy_cke_0_712), + .C(mgt_clk), + .D(plm_dfm_prel_out_i_m3_0_6__1515), + .Q(phy_rd[6]) + ); + FDPE plm_dfm_reg_phy_rd_5_ ( + .PRE(plm_rst), + .CE(plm_phy_cke_0_712), + .C(mgt_clk), + .D(plm_dfm_prel_out_i_m3_0_5__1516), + .Q(phy_rd[5]) + ); + FDPE plm_dfm_reg_phy_rd_4_ ( + .PRE(plm_rst), + .CE(plm_phy_cke_0_712), + .C(mgt_clk), + .D(plm_dfm_prel_out_i_m3_0_4__1517), + .Q(phy_rd[4]) + ); + FDPE plm_dfm_reg_phy_rd_3_ ( + .PRE(plm_rst), + .CE(plm_phy_cke_0_712), + .C(mgt_clk), + .D(plm_dfm_prel_out_i_m3_0_3__1518), + .Q(phy_rd[3]) + ); + FDPE plm_dfm_reg_phy_rd_2_ ( + .PRE(plm_rst), + .CE(plm_phy_cke_0_712), + .C(mgt_clk), + .D(plm_dfm_prel_out_i_m3_0_2__1519), + .Q(phy_rd[2]) + ); + FDPE plm_dfm_reg_phy_rd_1_ ( + .PRE(plm_rst), + .CE(plm_phy_cke_0_712), + .C(mgt_clk), + .D(plm_dfm_prel_out_i_m3_0_1__1520), + .Q(phy_rd[1]) + ); + FDPE plm_dfm_reg_phy_rd_0_ ( + .PRE(plm_rst), + .CE(plm_phy_cke_0_712), + .C(mgt_clk), + .D(plm_dfm_prel_out_i_m3_0_0__1521), + .Q(phy_rd[0]) + ); + FDCE plm_dfm_reg_phy_rframe_h ( + .CE(plm_phy_cke_1_711), + .C(mgt_clk), + .D(plm_dfm_reg_phy_rframe_h_3), + .Q(phy_rframe_h), + .CLR(plm_rst) + ); + FDCE plm_dfm_reg_phy_rframe_l ( + .CE(plm_phy_cke_1_711), + .C(mgt_clk), + .D(plm_dfm_reg_phy_rframe_l_3), + .Q(phy_rframe_l), + .CLR(plm_rst) + ); + FDCE plm_dfm_reg_phy_rbad_dfrm_h ( + .CE(plm_phy_cke_0_712), + .C(mgt_clk), + .D(plm_dfm_reg_phy_rbad_dfrm_h_3), + .Q(plm_phy_rbad_dfrm_h), + .CLR(plm_rst) + ); + FDCE plm_dfm_reg_phy_rbad_dfrm_l ( + .CE(plm_phy_cke_0_712), + .C(mgt_clk), + .D(plm_dfm_reg_phy_rbad_dfrm_l_3), + .Q(plm_phy_rbad_dfrm_l), + .CLR(plm_rst) + ); + FDPE plm_dfm_reg_phy_ferr_h_n ( + .PRE(plm_rst), + .CE(plm_phy_cke_0_712), + .C(mgt_clk), + .D(plm_dfm_un4_reg_phy_ferr_h_n_i), + .Q(phy_rferr_h_n) + ); + FDPE plm_dfm_reg_phy_ferr_l_n ( + .PRE(plm_rst), + .CE(plm_phy_cke_0_712), + .C(mgt_clk), + .D(plm_dfm_un4_reg_phy_ferr_l_n_i), + .Q(phy_rferr_l_n) + ); + FDPE plm_dfm_reg_phy_rctrl_h ( + .PRE(plm_rst), + .CE(plm_phy_cke_0_712), + .C(mgt_clk), + .D(plm_dfm_N_20788_i_1523), + .Q(phy_rctrl_h) + ); + FDPE plm_dfm_reg_phy_rctrl_l ( + .PRE(plm_rst), + .CE(plm_phy_cke_0_712), + .C(mgt_clk), + .D(plm_dfm_ns_phy_rctrl_l_iv_0_m2_0_1522), + .Q(phy_rctrl_l) + ); + defparam plm_dfm_N_20788_i.INIT = 8'h4E; + LUT3_L plm_dfm_N_20788_i ( + .I0(phy_rctrl_l), + .I1(plm_dfm_preh_sdpstp_i_m3_0[1]), + .I2(plm_dfm_preh_sdpstp_i_m3_0[0]), + .LO(plm_dfm_N_20788_i_1523) + ); + defparam plm_dfm_deframe1_filter_reg_any_end_6_i_0_0_0_o2_0_.INIT = 4'h8; + LUT2 plm_dfm_deframe1_filter_reg_any_end_6_i_0_0_0_o2_0_ ( + .I0(cmmp_negotiated_width[0]), + .I1(plm_link_l0), + .O(plm_dfm_deframe1_N_55957_i) + ); + defparam plm_dfm_deframe1_det_d0_0_a2_0_a2_0_a3_0_a2.INIT = 4'h1; + LUT2 plm_dfm_deframe1_det_d0_0_a2_0_a2_0_a3_0_a2 ( + .I0(plm_rx0_des_bad[0]), + .I1(plm_rx0_des_bad[1]), + .O(plm_dfm_det_d0_i) + ); + defparam plm_dfm_deframe1_filter_reg_any_sta_6_i_0_0_0_a2_1_.INIT = 4'h1; + LUT2 plm_dfm_deframe1_filter_reg_any_sta_6_i_0_0_0_a2_1_ ( + .I0(plm_rx0_des_sdp[1]), + .I1(plm_rx0_des_stp[1]), + .O(plm_dfm_N_58722) + ); + defparam plm_dfm_deframe1_filter_reg_any_sta_6_i_0_0_0_a2_0_.INIT = 4'h1; + LUT2 plm_dfm_deframe1_filter_reg_any_sta_6_i_0_0_0_a2_0_ ( + .I0(plm_rx0_des_sdp[0]), + .I1(plm_rx0_des_stp[0]), + .O(plm_dfm_N_58721) + ); + defparam plm_dfm_deframe1_filter_reg_any_sym_5_0_a2_0_a2_0_a3_0_a3_1_.INIT = 4'h8; + LUT2 plm_dfm_deframe1_filter_reg_any_sym_5_0_a2_0_a2_0_a3_0_a3_1_ ( + .I0(plm_dfm_deframe1_N_55957_i), + .I1(plm_rx0_des_sym[1]), + .O(plm_dfm_deframe1_reg_dat_1_sqmuxa) + ); + defparam plm_dfm_deframe1_filter_reg_any_sym_5_0_a2_0_a2_0_a3_0_a3_0_.INIT = 4'h8; + LUT2 plm_dfm_deframe1_filter_reg_any_sym_5_0_a2_0_a2_0_a3_0_a3_0_ ( + .I0(plm_dfm_deframe1_N_55957_i), + .I1(plm_rx0_des_sym[0]), + .O(plm_dfm_deframe1_reg_dat_1_sqmuxa_1) + ); + defparam plm_dfm_deframe1_filter_reg_any_bad_6_0_a2_0_a2_0_a3_0_a2_3_0_.INIT = 16'h0001; + LUT4 plm_dfm_deframe1_filter_reg_any_bad_6_0_a2_0_a2_0_a3_0_a2_3_0_ ( + .I0(plm_rx0_des_bad[0]), + .I1(plm_rx0_des_com[0]), + .I2(plm_rx0_des_idl[0]), + .I3(plm_rx0_des_skp[0]), + .O(plm_dfm_deframe1_reg_any_bad_6_0_a2_0_a2_0_a3_0_a2_3[0]) + ); + defparam plm_dfm_deframe1_filter_reg_any_bad_6_0_a2_0_a2_0_a3_0_a2_3_1_.INIT = 16'h0001; + LUT4 plm_dfm_deframe1_filter_reg_any_bad_6_0_a2_0_a2_0_a3_0_a2_3_1_ ( + .I0(plm_rx0_des_bad[1]), + .I1(plm_rx0_des_com[1]), + .I2(plm_rx0_des_idl[1]), + .I3(plm_rx0_des_skp[1]), + .O(plm_dfm_deframe1_reg_any_bad_6_0_a2_0_a2_0_a3_0_a2_3[1]) + ); + defparam plm_dfm_deframe1_filter_N_61202_i.INIT = 16'hFFF7; + LUT4_L plm_dfm_deframe1_filter_N_61202_i ( + .I0(plm_dfm_deframe1_N_55957_i), + .I1(plm_dfm_deframe1_reg_any_bad_6_0_a2_0_a2_0_a3_0_a2_3[0]), + .I2(plm_rx0_des_fts[0]), + .I3(plm_rx0_des_pad[0]), + .LO(plm_dfm_deframe1_N_61202_i) + ); + defparam plm_dfm_deframe1_filter_reg_any_sta_6_i_0_0_0_1_.INIT = 4'h2; + LUT2_L plm_dfm_deframe1_filter_reg_any_sta_6_i_0_0_0_1_ ( + .I0(plm_dfm_deframe1_N_55957_i), + .I1(plm_dfm_N_58722), + .LO(plm_dfm_deframe1_N_20140_i) + ); + defparam plm_dfm_deframe1_filter_reg_any_sta_6_i_0_0_0_0_.INIT = 4'h2; + LUT2_L plm_dfm_deframe1_filter_reg_any_sta_6_i_0_0_0_0_ ( + .I0(plm_dfm_deframe1_N_55957_i), + .I1(plm_dfm_N_58721), + .LO(plm_dfm_deframe1_N_20138_i) + ); + defparam plm_dfm_deframe1_filter_reg_any_end_6_i_0_0_0_1_.INIT = 8'hA8; + LUT3_L plm_dfm_deframe1_filter_reg_any_end_6_i_0_0_0_1_ ( + .I0(plm_dfm_deframe1_N_55957_i), + .I1(plm_rx0_des_edb[1]), + .I2(plm_rx0_des_edg[1]), + .LO(plm_dfm_deframe1_N_20136_i) + ); + defparam plm_dfm_deframe1_filter_reg_any_end_6_i_0_0_0_0_.INIT = 8'hA8; + LUT3_L plm_dfm_deframe1_filter_reg_any_end_6_i_0_0_0_0_ ( + .I0(plm_dfm_deframe1_N_55957_i), + .I1(plm_rx0_des_edb[0]), + .I2(plm_rx0_des_edg[0]), + .LO(plm_dfm_deframe1_N_20134_i) + ); + defparam plm_dfm_deframe1_filter_reg_stp_5_0_a2_0_a2_0_a3_0_a2_1_.INIT = 4'h8; + LUT2_L plm_dfm_deframe1_filter_reg_stp_5_0_a2_0_a2_0_a3_0_a2_1_ ( + .I0(plm_dfm_deframe1_N_55957_i), + .I1(plm_rx0_des_stp[1]), + .LO(plm_dfm_deframe1_reg_stp_5[1]) + ); + defparam plm_dfm_deframe1_filter_reg_stp_5_0_a2_0_a2_0_a3_0_a2_0_.INIT = 4'h8; + LUT2_L plm_dfm_deframe1_filter_reg_stp_5_0_a2_0_a2_0_a3_0_a2_0_ ( + .I0(plm_dfm_deframe1_N_55957_i), + .I1(plm_rx0_des_stp[0]), + .LO(plm_dfm_deframe1_reg_stp_5[0]) + ); + defparam plm_dfm_deframe1_reg_dat_6_0_a2_0_a2_0_a3_0_a2_13_.INIT = 4'h8; + LUT2_L plm_dfm_deframe1_reg_dat_6_0_a2_0_a2_0_a3_0_a2_13_ ( + .I0(plm_dfm_deframe1_reg_dat_1_sqmuxa), + .I1(plm_rx0_des_dat[13]), + .LO(plm_dfm_deframe1_reg_dat_6[13]) + ); + defparam plm_dfm_deframe1_reg_dat_6_0_a2_0_a2_0_a3_0_a2_12_.INIT = 4'h8; + LUT2_L plm_dfm_deframe1_reg_dat_6_0_a2_0_a2_0_a3_0_a2_12_ ( + .I0(plm_dfm_deframe1_reg_dat_1_sqmuxa), + .I1(plm_rx0_des_dat[12]), + .LO(plm_dfm_deframe1_reg_dat_6[12]) + ); + defparam plm_dfm_deframe1_reg_dat_6_0_a2_0_a2_0_a3_0_a2_11_.INIT = 4'h8; + LUT2_L plm_dfm_deframe1_reg_dat_6_0_a2_0_a2_0_a3_0_a2_11_ ( + .I0(plm_dfm_deframe1_reg_dat_1_sqmuxa), + .I1(plm_rx0_des_dat[11]), + .LO(plm_dfm_deframe1_reg_dat_6[11]) + ); + defparam plm_dfm_deframe1_reg_dat_6_0_a2_0_a2_0_a3_0_a2_10_.INIT = 4'h8; + LUT2_L plm_dfm_deframe1_reg_dat_6_0_a2_0_a2_0_a3_0_a2_10_ ( + .I0(plm_dfm_deframe1_reg_dat_1_sqmuxa), + .I1(plm_rx0_des_dat[10]), + .LO(plm_dfm_deframe1_reg_dat_6[10]) + ); + defparam plm_dfm_deframe1_reg_dat_6_0_a2_0_a2_0_a3_0_a2_9_.INIT = 4'h8; + LUT2_L plm_dfm_deframe1_reg_dat_6_0_a2_0_a2_0_a3_0_a2_9_ ( + .I0(plm_dfm_deframe1_reg_dat_1_sqmuxa), + .I1(plm_rx0_des_dat[9]), + .LO(plm_dfm_deframe1_reg_dat_6[9]) + ); + defparam plm_dfm_deframe1_reg_dat_6_0_a2_0_a2_0_a3_0_a2_8_.INIT = 4'h8; + LUT2_L plm_dfm_deframe1_reg_dat_6_0_a2_0_a2_0_a3_0_a2_8_ ( + .I0(plm_dfm_deframe1_reg_dat_1_sqmuxa), + .I1(plm_rx0_des_dat[8]), + .LO(plm_dfm_deframe1_reg_dat_6[8]) + ); + defparam plm_dfm_deframe1_reg_dat_6_0_a2_0_a2_0_a3_0_a2_7_.INIT = 4'h8; + LUT2_L plm_dfm_deframe1_reg_dat_6_0_a2_0_a2_0_a3_0_a2_7_ ( + .I0(plm_dfm_deframe1_reg_dat_1_sqmuxa_1), + .I1(plm_rx0_des_dat[7]), + .LO(plm_dfm_deframe1_reg_dat_6[7]) + ); + defparam plm_dfm_deframe1_reg_dat_6_0_a2_0_a2_0_a3_0_a2_6_.INIT = 4'h8; + LUT2_L plm_dfm_deframe1_reg_dat_6_0_a2_0_a2_0_a3_0_a2_6_ ( + .I0(plm_dfm_deframe1_reg_dat_1_sqmuxa_1), + .I1(plm_rx0_des_dat[6]), + .LO(plm_dfm_deframe1_reg_dat_6[6]) + ); + defparam plm_dfm_deframe1_reg_dat_6_0_a2_0_a2_0_a3_0_a2_5_.INIT = 4'h8; + LUT2_L plm_dfm_deframe1_reg_dat_6_0_a2_0_a2_0_a3_0_a2_5_ ( + .I0(plm_dfm_deframe1_reg_dat_1_sqmuxa_1), + .I1(plm_rx0_des_dat[5]), + .LO(plm_dfm_deframe1_reg_dat_6[5]) + ); + defparam plm_dfm_deframe1_reg_dat_6_0_a2_0_a2_0_a3_0_a2_4_.INIT = 4'h8; + LUT2_L plm_dfm_deframe1_reg_dat_6_0_a2_0_a2_0_a3_0_a2_4_ ( + .I0(plm_dfm_deframe1_reg_dat_1_sqmuxa_1), + .I1(plm_rx0_des_dat[4]), + .LO(plm_dfm_deframe1_reg_dat_6[4]) + ); + defparam plm_dfm_deframe1_reg_dat_6_0_a2_0_a2_0_a3_0_a2_3_.INIT = 4'h8; + LUT2_L plm_dfm_deframe1_reg_dat_6_0_a2_0_a2_0_a3_0_a2_3_ ( + .I0(plm_dfm_deframe1_reg_dat_1_sqmuxa_1), + .I1(plm_rx0_des_dat[3]), + .LO(plm_dfm_deframe1_reg_dat_6[3]) + ); + defparam plm_dfm_deframe1_reg_dat_6_0_a2_0_a2_0_a3_0_a2_2_.INIT = 4'h8; + LUT2_L plm_dfm_deframe1_reg_dat_6_0_a2_0_a2_0_a3_0_a2_2_ ( + .I0(plm_dfm_deframe1_reg_dat_1_sqmuxa_1), + .I1(plm_rx0_des_dat[2]), + .LO(plm_dfm_deframe1_reg_dat_6[2]) + ); + defparam plm_dfm_deframe1_reg_dat_6_0_a2_0_a2_0_a3_0_a2_1_.INIT = 4'h8; + LUT2_L plm_dfm_deframe1_reg_dat_6_0_a2_0_a2_0_a3_0_a2_1_ ( + .I0(plm_dfm_deframe1_reg_dat_1_sqmuxa_1), + .I1(plm_rx0_des_dat[1]), + .LO(plm_dfm_deframe1_reg_dat_6[1]) + ); + defparam plm_dfm_deframe1_reg_dat_6_0_a2_0_a2_0_a3_0_a2_0_.INIT = 4'h8; + LUT2_L plm_dfm_deframe1_reg_dat_6_0_a2_0_a2_0_a3_0_a2_0_ ( + .I0(plm_dfm_deframe1_reg_dat_1_sqmuxa_1), + .I1(plm_rx0_des_dat[0]), + .LO(plm_dfm_deframe1_reg_dat_6[0]) + ); + defparam plm_dfm_deframe1_filter_N_61203_i.INIT = 16'hFFF7; + LUT4_L plm_dfm_deframe1_filter_N_61203_i ( + .I0(plm_dfm_deframe1_N_55957_i), + .I1(plm_dfm_deframe1_reg_any_bad_6_0_a2_0_a2_0_a3_0_a2_3[1]), + .I2(plm_rx0_des_fts[1]), + .I3(plm_rx0_des_pad[1]), + .LO(plm_dfm_deframe1_N_61203_i) + ); + defparam plm_dfm_deframe1_filter_reg_sdp_5_0_a2_0_a2_0_a3_0_a2_1_.INIT = 4'h8; + LUT2_L plm_dfm_deframe1_filter_reg_sdp_5_0_a2_0_a2_0_a3_0_a2_1_ ( + .I0(plm_dfm_deframe1_N_55957_i), + .I1(plm_rx0_des_sdp[1]), + .LO(plm_dfm_deframe1_reg_sdp_5[1]) + ); + defparam plm_dfm_deframe1_filter_reg_sdp_5_0_a2_0_a2_0_a3_0_a2_0_.INIT = 4'h8; + LUT2_L plm_dfm_deframe1_filter_reg_sdp_5_0_a2_0_a2_0_a3_0_a2_0_ ( + .I0(plm_dfm_deframe1_N_55957_i), + .I1(plm_rx0_des_sdp[0]), + .LO(plm_dfm_deframe1_reg_sdp_5[0]) + ); + defparam plm_dfm_deframe1_filter_reg_edg_5_0_a2_0_a2_0_a3_0_a2_1_.INIT = 4'h8; + LUT2_L plm_dfm_deframe1_filter_reg_edg_5_0_a2_0_a2_0_a3_0_a2_1_ ( + .I0(plm_dfm_deframe1_N_55957_i), + .I1(plm_rx0_des_edg[1]), + .LO(plm_dfm_deframe1_reg_edg_5[1]) + ); + defparam plm_dfm_deframe1_filter_reg_edg_5_0_a2_0_a2_0_a3_0_a2_0_.INIT = 4'h8; + LUT2_L plm_dfm_deframe1_filter_reg_edg_5_0_a2_0_a2_0_a3_0_a2_0_ ( + .I0(plm_dfm_deframe1_N_55957_i), + .I1(plm_rx0_des_edg[0]), + .LO(plm_dfm_deframe1_reg_edg_5[0]) + ); + defparam plm_dfm_deframe1_filter_reg_edb_5_0_a2_0_a2_0_a3_0_a2_1_.INIT = 4'h8; + LUT2_L plm_dfm_deframe1_filter_reg_edb_5_0_a2_0_a2_0_a3_0_a2_1_ ( + .I0(plm_dfm_deframe1_N_55957_i), + .I1(plm_rx0_des_edb[1]), + .LO(plm_dfm_deframe1_reg_edb_5[1]) + ); + defparam plm_dfm_deframe1_filter_reg_edb_5_0_a2_0_a2_0_a3_0_a2_0_.INIT = 4'h8; + LUT2_L plm_dfm_deframe1_filter_reg_edb_5_0_a2_0_a2_0_a3_0_a2_0_ ( + .I0(plm_dfm_deframe1_N_55957_i), + .I1(plm_rx0_des_edb[0]), + .LO(plm_dfm_deframe1_reg_edb_5[0]) + ); + defparam plm_dfm_deframe1_reg_dat_6_0_a2_0_a2_0_a3_0_a2_15_.INIT = 4'h8; + LUT2_L plm_dfm_deframe1_reg_dat_6_0_a2_0_a2_0_a3_0_a2_15_ ( + .I0(plm_dfm_deframe1_reg_dat_1_sqmuxa), + .I1(plm_rx0_des_dat[15]), + .LO(plm_dfm_deframe1_reg_dat_6[15]) + ); + defparam plm_dfm_deframe1_reg_dat_6_0_a2_0_a2_0_a3_0_a2_14_.INIT = 4'h8; + LUT2_L plm_dfm_deframe1_reg_dat_6_0_a2_0_a2_0_a3_0_a2_14_ ( + .I0(plm_dfm_deframe1_reg_dat_1_sqmuxa), + .I1(plm_rx0_des_dat[14]), + .LO(plm_dfm_deframe1_reg_dat_6[14]) + ); + defparam plm_dfm_deframe1_detect_and_stretch_N_61205_i.INIT = 16'hFFFD; + LUT4_L plm_dfm_deframe1_detect_and_stretch_N_61205_i ( + .I0(plm_dfm_det_d0_i), + .I1(plm_dfm_deframe1_reg_det_d1_1525), + .I2(plm_dfm_deframe1_reg_det_d2_1526), + .I3(plm_dfm_deframe1_reg_det_d3_1524), + .LO(plm_dfm_deframe1_N_61205_i) + ); + FDC plm_dfm_deframe1_reg_det_d1 ( + .C(mgt_clk), + .D(plm_dfm_deframe1_det_d0_i_i_1527), + .Q(plm_dfm_deframe1_reg_det_d1_1525), + .CLR(plm_rst) + ); + FDC plm_dfm_deframe1_reg_det_d3 ( + .C(mgt_clk), + .D(plm_dfm_deframe1_reg_det_d2_1526), + .Q(plm_dfm_deframe1_reg_det_d3_1524), + .CLR(plm_rst) + ); + FDC plm_dfm_deframe1_reg_det_d2 ( + .C(mgt_clk), + .D(plm_dfm_deframe1_reg_det_d1_1525), + .Q(plm_dfm_deframe1_reg_det_d2_1526), + .CLR(plm_rst) + ); + FDP plm_dfm_deframe1_reg_any_bad_0_ ( + .PRE(plm_rst), + .C(mgt_clk), + .D(plm_dfm_deframe1_N_61202_i), + .Q(plm_dfm_deframe1_reg_any_bad[0]) + ); + FDC plm_dfm_deframe1_reg_any_sta_1_ ( + .C(mgt_clk), + .D(plm_dfm_deframe1_N_20140_i), + .Q(plm_dfm_deframe1_reg_any_sta[1]), + .CLR(plm_rst) + ); + FDC plm_dfm_deframe1_reg_any_sta_0_ ( + .C(mgt_clk), + .D(plm_dfm_deframe1_N_20138_i), + .Q(plm_dfm_deframe1_reg_any_sta[0]), + .CLR(plm_rst) + ); + FDC plm_dfm_deframe1_reg_any_end_1_ ( + .C(mgt_clk), + .D(plm_dfm_deframe1_N_20136_i), + .Q(plm_dfm_deframe1_reg_any_end[1]), + .CLR(plm_rst) + ); + FDC plm_dfm_deframe1_reg_any_end_0_ ( + .C(mgt_clk), + .D(plm_dfm_deframe1_N_20134_i), + .Q(plm_dfm_deframe1_reg_any_end[0]), + .CLR(plm_rst) + ); + FDC plm_dfm_deframe1_reg_stp_1_ ( + .C(mgt_clk), + .D(plm_dfm_deframe1_reg_stp_5[1]), + .Q(plm_dfm_deframe1_reg_stp[1]), + .CLR(plm_rst) + ); + FDC plm_dfm_deframe1_reg_stp_0_ ( + .C(mgt_clk), + .D(plm_dfm_deframe1_reg_stp_5[0]), + .Q(plm_dfm_deframe1_reg_stp[0]), + .CLR(plm_rst) + ); + FDC plm_dfm_deframe1_reg_dat_13_ ( + .C(mgt_clk), + .D(plm_dfm_deframe1_reg_dat_6[13]), + .Q(plm_dfm_deframe1_reg_dat[13]), + .CLR(plm_rst) + ); + FDC plm_dfm_deframe1_reg_dat_12_ ( + .C(mgt_clk), + .D(plm_dfm_deframe1_reg_dat_6[12]), + .Q(plm_dfm_deframe1_reg_dat[12]), + .CLR(plm_rst) + ); + FDC plm_dfm_deframe1_reg_dat_11_ ( + .C(mgt_clk), + .D(plm_dfm_deframe1_reg_dat_6[11]), + .Q(plm_dfm_deframe1_reg_dat[11]), + .CLR(plm_rst) + ); + FDC plm_dfm_deframe1_reg_dat_10_ ( + .C(mgt_clk), + .D(plm_dfm_deframe1_reg_dat_6[10]), + .Q(plm_dfm_deframe1_reg_dat[10]), + .CLR(plm_rst) + ); + FDC plm_dfm_deframe1_reg_dat_9_ ( + .C(mgt_clk), + .D(plm_dfm_deframe1_reg_dat_6[9]), + .Q(plm_dfm_deframe1_reg_dat[9]), + .CLR(plm_rst) + ); + FDC plm_dfm_deframe1_reg_dat_8_ ( + .C(mgt_clk), + .D(plm_dfm_deframe1_reg_dat_6[8]), + .Q(plm_dfm_deframe1_reg_dat[8]), + .CLR(plm_rst) + ); + FDC plm_dfm_deframe1_reg_dat_7_ ( + .C(mgt_clk), + .D(plm_dfm_deframe1_reg_dat_6[7]), + .Q(plm_dfm_deframe1_reg_dat[7]), + .CLR(plm_rst) + ); + FDC plm_dfm_deframe1_reg_dat_6_ ( + .C(mgt_clk), + .D(plm_dfm_deframe1_reg_dat_6[6]), + .Q(plm_dfm_deframe1_reg_dat[6]), + .CLR(plm_rst) + ); + FDC plm_dfm_deframe1_reg_dat_5_ ( + .C(mgt_clk), + .D(plm_dfm_deframe1_reg_dat_6[5]), + .Q(plm_dfm_deframe1_reg_dat[5]), + .CLR(plm_rst) + ); + FDC plm_dfm_deframe1_reg_dat_4_ ( + .C(mgt_clk), + .D(plm_dfm_deframe1_reg_dat_6[4]), + .Q(plm_dfm_deframe1_reg_dat[4]), + .CLR(plm_rst) + ); + FDC plm_dfm_deframe1_reg_dat_3_ ( + .C(mgt_clk), + .D(plm_dfm_deframe1_reg_dat_6[3]), + .Q(plm_dfm_deframe1_reg_dat[3]), + .CLR(plm_rst) + ); + FDC plm_dfm_deframe1_reg_dat_2_ ( + .C(mgt_clk), + .D(plm_dfm_deframe1_reg_dat_6[2]), + .Q(plm_dfm_deframe1_reg_dat[2]), + .CLR(plm_rst) + ); + FDC plm_dfm_deframe1_reg_dat_1_ ( + .C(mgt_clk), + .D(plm_dfm_deframe1_reg_dat_6[1]), + .Q(plm_dfm_deframe1_reg_dat[1]), + .CLR(plm_rst) + ); + FDC plm_dfm_deframe1_reg_dat_0_ ( + .C(mgt_clk), + .D(plm_dfm_deframe1_reg_dat_6[0]), + .Q(plm_dfm_deframe1_reg_dat[0]), + .CLR(plm_rst) + ); + FDP plm_dfm_deframe1_reg_any_bad_1_ ( + .PRE(plm_rst), + .C(mgt_clk), + .D(plm_dfm_deframe1_N_61203_i), + .Q(plm_dfm_deframe1_reg_any_bad[1]) + ); + FDC plm_dfm_deframe1_reg_delay_sdp_0_ ( + .C(mgt_clk), + .D(plm_dfm_deframe1_reg_sdp[0]), + .Q(plm_dfm_deframe1_reg_delay_sdp[0]), + .CLR(plm_rst) + ); + FDC plm_dfm_deframe1_reg_delay_edg_1_ ( + .C(mgt_clk), + .D(plm_dfm_deframe1_reg_edg[1]), + .Q(plm_dfm_deframe1_reg_delay_edg[1]), + .CLR(plm_rst) + ); + FDC plm_dfm_deframe1_reg_delay_edg_0_ ( + .C(mgt_clk), + .D(plm_dfm_deframe1_reg_edg[0]), + .Q(plm_dfm_deframe1_reg_delay_edg[0]), + .CLR(plm_rst) + ); + FDC plm_dfm_deframe1_reg_delay_edb_1_ ( + .C(mgt_clk), + .D(plm_dfm_deframe1_reg_edb[1]), + .Q(plm_dfm_deframe1_reg_delay_edb[1]), + .CLR(plm_rst) + ); + FDC plm_dfm_deframe1_reg_delay_edb_0_ ( + .C(mgt_clk), + .D(plm_dfm_deframe1_reg_edb[0]), + .Q(plm_dfm_deframe1_reg_delay_edb[0]), + .CLR(plm_rst) + ); + FDC plm_dfm_deframe1_reg_sdp_1_ ( + .C(mgt_clk), + .D(plm_dfm_deframe1_reg_sdp_5[1]), + .Q(plm_dfm_deframe1_reg_sdp[1]), + .CLR(plm_rst) + ); + FDC plm_dfm_deframe1_reg_sdp_0_ ( + .C(mgt_clk), + .D(plm_dfm_deframe1_reg_sdp_5[0]), + .Q(plm_dfm_deframe1_reg_sdp[0]), + .CLR(plm_rst) + ); + FDC plm_dfm_deframe1_reg_edg_1_ ( + .C(mgt_clk), + .D(plm_dfm_deframe1_reg_edg_5[1]), + .Q(plm_dfm_deframe1_reg_edg[1]), + .CLR(plm_rst) + ); + FDC plm_dfm_deframe1_reg_edg_0_ ( + .C(mgt_clk), + .D(plm_dfm_deframe1_reg_edg_5[0]), + .Q(plm_dfm_deframe1_reg_edg[0]), + .CLR(plm_rst) + ); + FDC plm_dfm_deframe1_reg_edb_1_ ( + .C(mgt_clk), + .D(plm_dfm_deframe1_reg_edb_5[1]), + .Q(plm_dfm_deframe1_reg_edb[1]), + .CLR(plm_rst) + ); + FDC plm_dfm_deframe1_reg_edb_0_ ( + .C(mgt_clk), + .D(plm_dfm_deframe1_reg_edb_5[0]), + .Q(plm_dfm_deframe1_reg_edb[0]), + .CLR(plm_rst) + ); + FDC plm_dfm_deframe1_reg_any_sym_1_ ( + .C(mgt_clk), + .D(plm_dfm_deframe1_reg_dat_1_sqmuxa), + .Q(plm_dfm_deframe1_reg_any_sym[1]), + .CLR(plm_rst) + ); + FDC plm_dfm_deframe1_reg_any_sym_0_ ( + .C(mgt_clk), + .D(plm_dfm_deframe1_reg_dat_1_sqmuxa_1), + .Q(plm_dfm_deframe1_reg_any_sym[0]), + .CLR(plm_rst) + ); + FDC plm_dfm_deframe1_reg_dat_15_ ( + .C(mgt_clk), + .D(plm_dfm_deframe1_reg_dat_6[15]), + .Q(plm_dfm_deframe1_reg_dat[15]), + .CLR(plm_rst) + ); + FDC plm_dfm_deframe1_reg_dat_14_ ( + .C(mgt_clk), + .D(plm_dfm_deframe1_reg_dat_6[14]), + .Q(plm_dfm_deframe1_reg_dat[14]), + .CLR(plm_rst) + ); + FDC plm_dfm_deframe1_reg_delay_dat_11_ ( + .C(mgt_clk), + .D(plm_dfm_deframe1_reg_dat[11]), + .Q(plm_dfm_deframe1_reg_delay_dat[11]), + .CLR(plm_rst) + ); + FDC plm_dfm_deframe1_reg_delay_dat_10_ ( + .C(mgt_clk), + .D(plm_dfm_deframe1_reg_dat[10]), + .Q(plm_dfm_deframe1_reg_delay_dat[10]), + .CLR(plm_rst) + ); + FDC plm_dfm_deframe1_reg_delay_dat_9_ ( + .C(mgt_clk), + .D(plm_dfm_deframe1_reg_dat[9]), + .Q(plm_dfm_deframe1_reg_delay_dat[9]), + .CLR(plm_rst) + ); + FDC plm_dfm_deframe1_reg_delay_dat_8_ ( + .C(mgt_clk), + .D(plm_dfm_deframe1_reg_dat[8]), + .Q(plm_dfm_deframe1_reg_delay_dat[8]), + .CLR(plm_rst) + ); + FDC plm_dfm_deframe1_reg_delay_dat_7_ ( + .C(mgt_clk), + .D(plm_dfm_deframe1_reg_dat[7]), + .Q(plm_dfm_deframe1_reg_delay_dat[7]), + .CLR(plm_rst) + ); + FDC plm_dfm_deframe1_reg_delay_dat_6_ ( + .C(mgt_clk), + .D(plm_dfm_deframe1_reg_dat[6]), + .Q(plm_dfm_deframe1_reg_delay_dat[6]), + .CLR(plm_rst) + ); + FDC plm_dfm_deframe1_reg_delay_dat_5_ ( + .C(mgt_clk), + .D(plm_dfm_deframe1_reg_dat[5]), + .Q(plm_dfm_deframe1_reg_delay_dat[5]), + .CLR(plm_rst) + ); + FDC plm_dfm_deframe1_reg_delay_dat_4_ ( + .C(mgt_clk), + .D(plm_dfm_deframe1_reg_dat[4]), + .Q(plm_dfm_deframe1_reg_delay_dat[4]), + .CLR(plm_rst) + ); + FDC plm_dfm_deframe1_reg_delay_dat_3_ ( + .C(mgt_clk), + .D(plm_dfm_deframe1_reg_dat[3]), + .Q(plm_dfm_deframe1_reg_delay_dat[3]), + .CLR(plm_rst) + ); + FDC plm_dfm_deframe1_reg_delay_dat_2_ ( + .C(mgt_clk), + .D(plm_dfm_deframe1_reg_dat[2]), + .Q(plm_dfm_deframe1_reg_delay_dat[2]), + .CLR(plm_rst) + ); + FDC plm_dfm_deframe1_reg_delay_dat_1_ ( + .C(mgt_clk), + .D(plm_dfm_deframe1_reg_dat[1]), + .Q(plm_dfm_deframe1_reg_delay_dat[1]), + .CLR(plm_rst) + ); + FDC plm_dfm_deframe1_reg_delay_dat_0_ ( + .C(mgt_clk), + .D(plm_dfm_deframe1_reg_dat[0]), + .Q(plm_dfm_deframe1_reg_delay_dat[0]), + .CLR(plm_rst) + ); + FDC plm_dfm_deframe1_reg_delay_stp_1_ ( + .C(mgt_clk), + .D(plm_dfm_deframe1_reg_stp[1]), + .Q(plm_dfm_deframe1_reg_delay_stp[1]), + .CLR(plm_rst) + ); + FDC plm_dfm_deframe1_reg_delay_stp_0_ ( + .C(mgt_clk), + .D(plm_dfm_deframe1_reg_stp[0]), + .Q(plm_dfm_deframe1_reg_delay_stp[0]), + .CLR(plm_rst) + ); + FDC plm_dfm_deframe1_reg_delay_sdp_1_ ( + .C(mgt_clk), + .D(plm_dfm_deframe1_reg_sdp[1]), + .Q(plm_dfm_deframe1_reg_delay_sdp[1]), + .CLR(plm_rst) + ); + FDC plm_dfm_deframe1_reg_delay_dat_15_ ( + .C(mgt_clk), + .D(plm_dfm_deframe1_reg_dat[15]), + .Q(plm_dfm_deframe1_reg_delay_dat[15]), + .CLR(plm_rst) + ); + FDC plm_dfm_deframe1_reg_delay_dat_14_ ( + .C(mgt_clk), + .D(plm_dfm_deframe1_reg_dat[14]), + .Q(plm_dfm_deframe1_reg_delay_dat[14]), + .CLR(plm_rst) + ); + FDC plm_dfm_deframe1_reg_delay_dat_13_ ( + .C(mgt_clk), + .D(plm_dfm_deframe1_reg_dat[13]), + .Q(plm_dfm_deframe1_reg_delay_dat[13]), + .CLR(plm_rst) + ); + FDC plm_dfm_deframe1_reg_delay_dat_12_ ( + .C(mgt_clk), + .D(plm_dfm_deframe1_reg_dat[12]), + .Q(plm_dfm_deframe1_reg_delay_dat[12]), + .CLR(plm_rst) + ); + FDCE plm_dfm_deframe1_reg_by1_prec_rcverr ( + .CE(plm_phy_cke_0_712), + .C(mgt_clk), + .D(plm_dfm_deframe1_N_61205_i), + .Q(plm_dfm_by1_prec_rcverr), + .CLR(plm_rst) + ); + defparam plm_dfm_deframe1_det_d0_i_i.INIT = 4'hE; + LUT2_L plm_dfm_deframe1_det_d0_i_i ( + .I0(plm_rx0_des_bad[1]), + .I1(plm_rx0_des_bad[0]), + .LO(plm_dfm_deframe1_det_d0_i_i_1527) + ); + defparam plm_dfm_deframe1_dwfsm_reg_push_0_a4_0_a2_0_a2_1_.INIT = 4'h4; + LUT2 plm_dfm_deframe1_dwfsm_reg_push_0_a4_0_a2_0_a2_1_ ( + .I0(plm_dfm_deframe1_reg_fsm_last_substate[1]), + .I1(plm_dfm_deframe1_reg_fsm_substate[1]), + .O(plm_dfm_deframe1_push1) + ); + defparam plm_dfm_deframe1_dwfsm_ns_fsm_substate_i_i_0_a2_1_1_.INIT = 4'h1; + LUT2 plm_dfm_deframe1_dwfsm_ns_fsm_substate_i_i_0_a2_1_1_ ( + .I0(plm_dfm_deframe1_reg_any_bad[0]), + .I1(plm_dfm_deframe1_reg_any_end[0]), + .O(plm_dfm_deframe1_dwfsm_N_35606_1) + ); + defparam plm_dfm_deframe1_dwfsm_valid_on_third_symbol_reg_ferr_40_i_i_0_a2_1_0.INIT = 4'h8; + LUT2_L plm_dfm_deframe1_dwfsm_valid_on_third_symbol_reg_ferr_40_i_i_0_a2_1_0 ( + .I0(plm_dfm_deframe1_reg_any_end[0]), + .I1(plm_dfm_deframe1_reg_any_sym[1]), + .LO(plm_dfm_deframe1_dwfsm_reg_ferr_40_i_i_0_a2_1_0) + ); + defparam plm_dfm_deframe1_dwfsm_ns_fsm_framing_iv_i_i_0_a2_1.INIT = 8'h08; + LUT3_L plm_dfm_deframe1_dwfsm_ns_fsm_framing_iv_i_i_0_a2_1 ( + .I0(plm_dfm_deframe1_dwfsm_reg_fsm_errored_1537), + .I1(plm_dfm_deframe1_dwfsm_reg_fsm_framing_1536), + .I2(plm_dfm_deframe1_reg_fsm_substate[1]), + .LO(plm_dfm_deframe1_dwfsm_ns_fsm_framing_iv_i_i_0_a2_1_1528) + ); + defparam plm_dfm_deframe1_dwfsm_ns_fsm_framing_iv_i_i_0_a2_0_1.INIT = 8'h01; + LUT3 plm_dfm_deframe1_dwfsm_ns_fsm_framing_iv_i_i_0_a2_0_1 ( + .I0(plm_dfm_deframe1_reg_any_bad[1]), + .I1(plm_dfm_deframe1_reg_any_end[1]), + .I2(plm_dfm_deframe1_reg_any_sym[1]), + .O(plm_dfm_deframe1_dwfsm_N_35599_1) + ); + defparam plm_dfm_deframe1_dwfsm_reg_push_i_i_0_0_.INIT = 16'h1190; + LUT4 plm_dfm_deframe1_dwfsm_reg_push_i_i_0_0_ ( + .I0(plm_dfm_deframe1_reg_fsm_last_substate[0]), + .I1(plm_dfm_deframe1_reg_fsm_last_substate[1]), + .I2(plm_dfm_deframe1_reg_fsm_substate[0]), + .I3(plm_dfm_deframe1_reg_fsm_substate[1]), + .O(plm_dfm_deframe1_N_22418_i) + ); + defparam plm_dfm_deframe1_dwfsm_ns_fsm_errored_iv_0_0_0.INIT = 16'h3704; + LUT4_L plm_dfm_deframe1_dwfsm_ns_fsm_errored_iv_0_0_0 ( + .I0(plm_dfm_deframe1_dwfsm_reg_fsm_errored_1537), + .I1(plm_dfm_deframe1_dwfsm_reg_fsm_framing_1536), + .I2(plm_dfm_deframe1_reg_fsm_substate[1]), + .I3(plm_dfm_deframe1_reg_any_sta[1]), + .LO(plm_dfm_deframe1_dwfsm_ns_fsm_errored_iv_0_0_0_1529) + ); + defparam plm_dfm_deframe1_dwfsm_reg_push_0_i_0_2_.INIT = 16'h0FFB; + LUT4 plm_dfm_deframe1_dwfsm_reg_push_0_i_0_2_ ( + .I0(plm_dfm_deframe1_reg_fsm_last_substate[0]), + .I1(plm_dfm_deframe1_reg_fsm_last_substate[1]), + .I2(plm_dfm_deframe1_reg_fsm_substate[0]), + .I3(plm_dfm_deframe1_reg_fsm_substate[1]), + .O(plm_dfm_deframe1_reg_push_0_i_0[2]) + ); + defparam plm_dfm_deframe1_dwfsm_ns_fsm_framing_iv_i_i_0_o4.INIT = 16'h5111; + LUT4 plm_dfm_deframe1_dwfsm_ns_fsm_framing_iv_i_i_0_o4 ( + .I0(plm_dfm_deframe1_dwfsm_reg_fsm_errored_1537), + .I1(plm_dfm_deframe1_reg_fsm_substate[1]), + .I2(plm_dfm_deframe1_reg_any_sym[0]), + .I3(plm_dfm_deframe1_reg_any_sym[1]), + .O(plm_dfm_deframe1_dwfsm_ns_fsm_framing_iv_i_i_0_o4_1535) + ); + defparam plm_dfm_deframe1_dwfsm_ns_fsm_framing_iv_i_i_0_a2_3.INIT = 16'h0002; + LUT4 plm_dfm_deframe1_dwfsm_ns_fsm_framing_iv_i_i_0_a2_3 ( + .I0(plm_dfm_deframe1_dwfsm_N_35606_1), + .I1(plm_dfm_deframe1_dwfsm_reg_fsm_framing_1536), + .I2(plm_dfm_deframe1_reg_any_sta[0]), + .I3(plm_dfm_deframe1_reg_any_sym[0]), + .O(plm_dfm_deframe1_dwfsm_ns_fsm_framing_iv_i_i_0_a2_3_1531) + ); + defparam plm_dfm_deframe1_dwfsm_ns_fsm_substate_i_i_0_a2_1_.INIT = 16'h0008; + LUT4_L plm_dfm_deframe1_dwfsm_ns_fsm_substate_i_i_0_a2_1_ ( + .I0(plm_dfm_deframe1_dwfsm_N_35606_1), + .I1(plm_dfm_deframe1_reg_fsm_substate[1]), + .I2(plm_dfm_deframe1_reg_any_sta[0]), + .I3(plm_dfm_deframe1_reg_any_sym[0]), + .LO(plm_dfm_deframe1_dwfsm_ns_fsm_substate_i_i_0_a2[1]) + ); + defparam plm_dfm_deframe1_dwfsm_ns_fsm_framing_iv_i_i_0_a2_0.INIT = 16'h00A2; + LUT4 plm_dfm_deframe1_dwfsm_ns_fsm_framing_iv_i_i_0_a2_0 ( + .I0(plm_dfm_deframe1_dwfsm_N_35599_1), + .I1(plm_dfm_deframe1_dwfsm_reg_fsm_framing_1536), + .I2(plm_dfm_deframe1_reg_fsm_substate[1]), + .I3(plm_dfm_deframe1_reg_any_sta[1]), + .O(plm_dfm_deframe1_dwfsm_ns_fsm_framing_iv_i_i_0_a2_0_1532) + ); + defparam plm_dfm_deframe1_dwfsm_valid_on_third_symbol_reg_ferr_40_i_i_0_0.INIT = 16'hABEF; + LUT4_L plm_dfm_deframe1_dwfsm_valid_on_third_symbol_reg_ferr_40_i_i_0_0 ( + .I0(plm_dfm_deframe1_dwfsm_reg_fsm_errored_1537), + .I1(plm_dfm_deframe1_reg_fsm_substate[0]), + .I2(plm_dfm_deframe1_dwfsm_reg_ferr_40_i_i_0_a2_1_0), + .I3(plm_dfm_deframe1_reg_any_end[1]), + .LO(plm_dfm_deframe1_dwfsm_reg_ferr_40_i_i_0_0) + ); + defparam plm_dfm_deframe1_dwfsm_ns_fsm_framing_iv_i_i_0_0.INIT = 16'h5554; + LUT4 plm_dfm_deframe1_dwfsm_ns_fsm_framing_iv_i_i_0_0 ( + .I0(plm_dfm_deframe1_dwfsm_ns_fsm_framing_iv_i_i_0_a2_1_1528), + .I1(plm_dfm_deframe1_dwfsm_reg_fsm_framing_1536), + .I2(plm_dfm_deframe1_reg_any_sta[0]), + .I3(plm_dfm_deframe1_reg_any_sta[1]), + .O(plm_dfm_deframe1_dwfsm_ns_fsm_framing_iv_i_i_0_0_1530) + ); + defparam plm_dfm_deframe1_dwfsm_ns_fsm_errored_iv_0_0_1.INIT = 16'h2AAA; + LUT4_L plm_dfm_deframe1_dwfsm_ns_fsm_errored_iv_0_0_1 ( + .I0(plm_dfm_deframe1_dwfsm_ns_fsm_errored_iv_0_0_0_1529), + .I1(plm_dfm_deframe1_dwfsm_reg_fsm_framing_1536), + .I2(plm_dfm_deframe1_reg_any_sym[0]), + .I3(plm_dfm_deframe1_reg_any_sym[1]), + .LO(plm_dfm_deframe1_dwfsm_ns_fsm_errored_iv_0_0_1_1534) + ); + defparam plm_dfm_deframe1_dwfsm_ns_fsm_framing_iv_i_i_0_a2.INIT = 16'h0444; + LUT4_L plm_dfm_deframe1_dwfsm_ns_fsm_framing_iv_i_i_0_a2 ( + .I0(plm_dfm_deframe1_dwfsm_ns_fsm_framing_iv_i_i_0_o4_1535), + .I1(plm_dfm_deframe1_dwfsm_reg_fsm_framing_1536), + .I2(plm_dfm_deframe1_reg_fsm_substate[0]), + .I3(plm_dfm_deframe1_reg_any_sta[0]), + .LO(plm_dfm_deframe1_dwfsm_ns_fsm_framing_iv_i_i_0_a2_1533) + ); + defparam plm_dfm_deframe1_dwfsm_ns_fsm_substate_i_i_0_1_0_.INIT = 16'hD1C0; + LUT4_L plm_dfm_deframe1_dwfsm_ns_fsm_substate_i_i_0_1_0_ ( + .I0(plm_dfm_deframe1_dwfsm_N_35599_1), + .I1(plm_dfm_deframe1_dwfsm_reg_fsm_framing_1536), + .I2(plm_dfm_deframe1_reg_fsm_substate[0]), + .I3(plm_dfm_deframe1_reg_any_sta[0]), + .LO(plm_dfm_deframe1_dwfsm_ns_fsm_substate_i_i_0_1[0]) + ); + defparam plm_dfm_deframe1_dwfsm_ns_fsm_framing_iv_i_i_0.INIT = 16'h0100; + LUT4_L plm_dfm_deframe1_dwfsm_ns_fsm_framing_iv_i_i_0 ( + .I0(plm_dfm_deframe1_dwfsm_ns_fsm_framing_iv_i_i_0_a2_1533), + .I1(plm_dfm_deframe1_dwfsm_ns_fsm_framing_iv_i_i_0_a2_0_1532), + .I2(plm_dfm_deframe1_dwfsm_ns_fsm_framing_iv_i_i_0_a2_3_1531), + .I3(plm_dfm_deframe1_dwfsm_ns_fsm_framing_iv_i_i_0_0_1530), + .LO(plm_dfm_deframe1_dwfsm_N_22408_i) + ); + defparam plm_dfm_deframe1_dwfsm_ns_fsm_errored_iv_0_0.INIT = 16'hCCC4; + LUT4_L plm_dfm_deframe1_dwfsm_ns_fsm_errored_iv_0_0 ( + .I0(plm_dfm_deframe1_dwfsm_N_35606_1), + .I1(plm_dfm_deframe1_dwfsm_ns_fsm_errored_iv_0_0_1_1534), + .I2(plm_dfm_deframe1_dwfsm_reg_fsm_framing_1536), + .I3(plm_dfm_deframe1_reg_any_sta[0]), + .LO(plm_dfm_deframe1_dwfsm_N_9422_i) + ); + defparam plm_dfm_deframe1_dwfsm_valid_on_third_symbol_reg_ferr_40_i_i_0.INIT = 16'h8CCC; + LUT4_L plm_dfm_deframe1_dwfsm_valid_on_third_symbol_reg_ferr_40_i_i_0 ( + .I0(plm_dfm_deframe1_dwfsm_reg_fsm_errored_1537), + .I1(plm_dfm_deframe1_dwfsm_reg_ferr_40_i_i_0_0), + .I2(plm_dfm_deframe1_reg_any_sym[0]), + .I3(plm_dfm_deframe1_reg_any_sym[1]), + .LO(plm_dfm_deframe1_dwfsm_N_22412_i) + ); + defparam plm_dfm_deframe1_dwfsm_ns_fsm_substate_i_i_0_0_.INIT = 8'hC8; + LUT3_L plm_dfm_deframe1_dwfsm_ns_fsm_substate_i_i_0_0_ ( + .I0(plm_dfm_deframe1_dwfsm_ns_fsm_framing_iv_i_i_0_o4_1535), + .I1(plm_dfm_deframe1_dwfsm_ns_fsm_substate_i_i_0_1[0]), + .I2(plm_dfm_deframe1_reg_any_sta[0]), + .LO(plm_dfm_deframe1_dwfsm_N_22416_i) + ); + defparam plm_dfm_deframe1_dwfsm_corkscrew_select_reg_high60_0_a2_0_a2.INIT = 8'h80; + LUT3_L plm_dfm_deframe1_dwfsm_corkscrew_select_reg_high60_0_a2_0_a2 ( + .I0(plm_dfm_deframe1_dwfsm_reg_fsm_framing_1536), + .I1(plm_dfm_deframe1_reg_fsm_substate[0]), + .I2(plm_dfm_deframe1_reg_fsm_substate[1]), + .LO(plm_dfm_deframe1_dwfsm_reg_high60) + ); + defparam plm_dfm_deframe1_dwfsm_corkscrew_select_reg_high59_0_a2_0_a2.INIT = 8'h20; + LUT3_L plm_dfm_deframe1_dwfsm_corkscrew_select_reg_high59_0_a2_0_a2 ( + .I0(plm_dfm_deframe1_dwfsm_reg_fsm_framing_1536), + .I1(plm_dfm_deframe1_reg_fsm_substate[0]), + .I2(plm_dfm_deframe1_reg_fsm_substate[1]), + .LO(plm_dfm_deframe1_dwfsm_reg_high59) + ); + defparam plm_dfm_deframe1_dwfsm_corkscrew_select_reg_high58_0_a2_0_a2.INIT = 8'h08; + LUT3_L plm_dfm_deframe1_dwfsm_corkscrew_select_reg_high58_0_a2_0_a2 ( + .I0(plm_dfm_deframe1_dwfsm_reg_fsm_framing_1536), + .I1(plm_dfm_deframe1_reg_fsm_substate[0]), + .I2(plm_dfm_deframe1_reg_fsm_substate[1]), + .LO(plm_dfm_deframe1_dwfsm_reg_high58) + ); + defparam plm_dfm_deframe1_dwfsm_reg_high_12_iv_0_0_0_.INIT = 16'h5702; + LUT4_L plm_dfm_deframe1_dwfsm_reg_high_12_iv_0_0_0_ ( + .I0(plm_dfm_deframe1_dwfsm_reg_fsm_framing_1536), + .I1(plm_dfm_deframe1_reg_fsm_substate[0]), + .I2(plm_dfm_deframe1_reg_fsm_substate[1]), + .I3(plm_dfm_deframe1_reg_any_sta[1]), + .LO(plm_dfm_deframe1_dwfsm_N_9772_i) + ); + defparam plm_dfm_deframe1_dwfsm_ns_fsm_substate_i_i_0_1_.INIT = 16'h1504; + LUT4_L plm_dfm_deframe1_dwfsm_ns_fsm_substate_i_i_0_1_ ( + .I0(plm_dfm_deframe1_dwfsm_ns_fsm_substate_i_i_0_a2[1]), + .I1(plm_dfm_deframe1_dwfsm_reg_fsm_framing_1536), + .I2(plm_dfm_deframe1_reg_fsm_substate[1]), + .I3(plm_dfm_deframe1_reg_any_sta[1]), + .LO(plm_dfm_deframe1_dwfsm_N_22414_i) + ); + FDC plm_dfm_deframe1_dwfsm_reg_fsm_framing ( + .C(mgt_clk), + .D(plm_dfm_deframe1_dwfsm_N_22408_i), + .Q(plm_dfm_deframe1_dwfsm_reg_fsm_framing_1536), + .CLR(plm_rst) + ); + FDC plm_dfm_deframe1_dwfsm_reg_fsm_errored ( + .C(mgt_clk), + .D(plm_dfm_deframe1_dwfsm_N_9422_i), + .Q(plm_dfm_deframe1_dwfsm_reg_fsm_errored_1537), + .CLR(plm_rst) + ); + FDC plm_dfm_deframe1_dwfsm_reg_ferr ( + .C(mgt_clk), + .D(plm_dfm_deframe1_dwfsm_N_22412_i), + .Q(plm_dfm_deframe1_ferr), + .CLR(plm_rst) + ); + FDC plm_dfm_deframe1_dwfsm_reg_fsm_substate_0_ ( + .C(mgt_clk), + .D(plm_dfm_deframe1_dwfsm_N_22416_i), + .Q(plm_dfm_deframe1_reg_fsm_substate[0]), + .CLR(plm_rst) + ); + FDC plm_dfm_deframe1_dwfsm_reg_high_3_ ( + .C(mgt_clk), + .D(plm_dfm_deframe1_dwfsm_reg_high60), + .Q(plm_dfm_deframe1_high3), + .CLR(plm_rst) + ); + FDC plm_dfm_deframe1_dwfsm_reg_high_2_ ( + .C(mgt_clk), + .D(plm_dfm_deframe1_dwfsm_reg_high59), + .Q(plm_dfm_deframe1_high2), + .CLR(plm_rst) + ); + FDC plm_dfm_deframe1_dwfsm_reg_high_1_ ( + .C(mgt_clk), + .D(plm_dfm_deframe1_dwfsm_reg_high58), + .Q(plm_dfm_deframe1_high1), + .CLR(plm_rst) + ); + FDC plm_dfm_deframe1_dwfsm_reg_high_0_ ( + .C(mgt_clk), + .D(plm_dfm_deframe1_dwfsm_N_9772_i), + .Q(plm_dfm_deframe1_high0), + .CLR(plm_rst) + ); + FDC plm_dfm_deframe1_dwfsm_reg_fsm_last_substate_1_ ( + .C(mgt_clk), + .D(plm_dfm_deframe1_reg_fsm_substate[1]), + .Q(plm_dfm_deframe1_reg_fsm_last_substate[1]), + .CLR(plm_rst) + ); + FDC plm_dfm_deframe1_dwfsm_reg_fsm_last_substate_0_ ( + .C(mgt_clk), + .D(plm_dfm_deframe1_reg_fsm_substate[0]), + .Q(plm_dfm_deframe1_reg_fsm_last_substate[0]), + .CLR(plm_rst) + ); + FDC plm_dfm_deframe1_dwfsm_reg_fsm_substate_1_ ( + .C(mgt_clk), + .D(plm_dfm_deframe1_dwfsm_N_22414_i), + .Q(plm_dfm_deframe1_reg_fsm_substate[1]), + .CLR(plm_rst) + ); + INV plm_dfm_deframe1_dwfsm_N_87731_i ( + .I(plm_dfm_deframe1_reg_push_0_i_0[2]), + .O(plm_dfm_deframe1_N_87731_i) + ); + GND plm_dfm_deframe1_dwbuf_GND ( + .G(plm_dfm_deframe1_dwbuf_GND_1538) + ); + RAM16X1D plm_dfm_deframe1_dwbuf_L0S0 ( + .DPO(plm_dfm_deframe1_dwbuf_dpo_sdpstp[0]), + .WCLK(mgt_clk), + .D(plm_dfm_deframe1_dwbuf_wd_s0_i_m4_0[0]), + .A0(plm_dfm_deframe1_dwbuf_reg_wp0[0]), + .A1(plm_dfm_deframe1_dwbuf_reg_wp0[1]), + .A2(plm_dfm_deframe1_dwbuf_reg_wp0[2]), + .A3(plm_dfm_deframe1_dwbuf_reg_wp0[3]), + .DPRA0(plm_dfm_deframe1_dwbuf_reg_rp[0]), + .DPRA1(plm_dfm_deframe1_dwbuf_reg_rp[1]), + .DPRA2(plm_dfm_deframe1_dwbuf_reg_rp[2]), + .DPRA3(plm_dfm_deframe1_dwbuf_reg_rp[3]), + .SPO(NLW_plm_dfm_deframe1_dwbuf_L0S0_SPO_UNCONNECTED), + .WE(plm_dfm_deframe1_N_22418_i) + ); + RAM16X1D plm_dfm_deframe1_dwbuf_L0S1 ( + .DPO(plm_dfm_deframe1_dwbuf_dpo_sdpstp[1]), + .WCLK(mgt_clk), + .D(plm_dfm_deframe1_dwbuf_wd_s0_i_m4_0[1]), + .A0(plm_dfm_deframe1_dwbuf_reg_wp0[0]), + .A1(plm_dfm_deframe1_dwbuf_reg_wp0[1]), + .A2(plm_dfm_deframe1_dwbuf_reg_wp0[2]), + .A3(plm_dfm_deframe1_dwbuf_reg_wp0[3]), + .DPRA0(plm_dfm_deframe1_dwbuf_reg_rp[0]), + .DPRA1(plm_dfm_deframe1_dwbuf_reg_rp[1]), + .DPRA2(plm_dfm_deframe1_dwbuf_reg_rp[2]), + .DPRA3(plm_dfm_deframe1_dwbuf_reg_rp[3]), + .SPO(NLW_plm_dfm_deframe1_dwbuf_L0S1_SPO_UNCONNECTED), + .WE(plm_dfm_deframe1_N_22418_i) + ); + RAM16X1D plm_dfm_deframe1_dwbuf_L0B0 ( + .DPO(plm_dfm_deframe1_dwbuf_dpo_out[24]), + .WCLK(mgt_clk), + .D(plm_dfm_deframe1_dwbuf_wd_l0_i_m4_0[0]), + .A0(plm_dfm_deframe1_dwbuf_reg_wp0[0]), + .A1(plm_dfm_deframe1_dwbuf_reg_wp0[1]), + .A2(plm_dfm_deframe1_dwbuf_reg_wp0[2]), + .A3(plm_dfm_deframe1_dwbuf_reg_wp0[3]), + .DPRA0(plm_dfm_deframe1_dwbuf_reg_rp[0]), + .DPRA1(plm_dfm_deframe1_dwbuf_reg_rp[1]), + .DPRA2(plm_dfm_deframe1_dwbuf_reg_rp[2]), + .DPRA3(plm_dfm_deframe1_dwbuf_reg_rp[3]), + .SPO(NLW_plm_dfm_deframe1_dwbuf_L0B0_SPO_UNCONNECTED), + .WE(plm_dfm_deframe1_N_22418_i) + ); + RAM16X1D plm_dfm_deframe1_dwbuf_L0B1 ( + .DPO(plm_dfm_deframe1_dwbuf_dpo_out[25]), + .WCLK(mgt_clk), + .D(plm_dfm_deframe1_dwbuf_wd_l0_i_m4_0[1]), + .A0(plm_dfm_deframe1_dwbuf_reg_wp0[0]), + .A1(plm_dfm_deframe1_dwbuf_reg_wp0[1]), + .A2(plm_dfm_deframe1_dwbuf_reg_wp0[2]), + .A3(plm_dfm_deframe1_dwbuf_reg_wp0[3]), + .DPRA0(plm_dfm_deframe1_dwbuf_reg_rp[0]), + .DPRA1(plm_dfm_deframe1_dwbuf_reg_rp[1]), + .DPRA2(plm_dfm_deframe1_dwbuf_reg_rp[2]), + .DPRA3(plm_dfm_deframe1_dwbuf_reg_rp[3]), + .SPO(NLW_plm_dfm_deframe1_dwbuf_L0B1_SPO_UNCONNECTED), + .WE(plm_dfm_deframe1_N_22418_i) + ); + RAM16X1D plm_dfm_deframe1_dwbuf_L0B2 ( + .DPO(plm_dfm_deframe1_dwbuf_dpo_out[26]), + .WCLK(mgt_clk), + .D(plm_dfm_deframe1_dwbuf_wd_l0_i_m4_0[2]), + .A0(plm_dfm_deframe1_dwbuf_reg_wp0[0]), + .A1(plm_dfm_deframe1_dwbuf_reg_wp0[1]), + .A2(plm_dfm_deframe1_dwbuf_reg_wp0[2]), + .A3(plm_dfm_deframe1_dwbuf_reg_wp0[3]), + .DPRA0(plm_dfm_deframe1_dwbuf_reg_rp[0]), + .DPRA1(plm_dfm_deframe1_dwbuf_reg_rp[1]), + .DPRA2(plm_dfm_deframe1_dwbuf_reg_rp[2]), + .DPRA3(plm_dfm_deframe1_dwbuf_reg_rp[3]), + .SPO(NLW_plm_dfm_deframe1_dwbuf_L0B2_SPO_UNCONNECTED), + .WE(plm_dfm_deframe1_N_22418_i) + ); + RAM16X1D plm_dfm_deframe1_dwbuf_L0B3 ( + .DPO(plm_dfm_deframe1_dwbuf_dpo_out[27]), + .WCLK(mgt_clk), + .D(plm_dfm_deframe1_dwbuf_wd_l0_i_m4_0[3]), + .A0(plm_dfm_deframe1_dwbuf_reg_wp0[0]), + .A1(plm_dfm_deframe1_dwbuf_reg_wp0[1]), + .A2(plm_dfm_deframe1_dwbuf_reg_wp0[2]), + .A3(plm_dfm_deframe1_dwbuf_reg_wp0[3]), + .DPRA0(plm_dfm_deframe1_dwbuf_reg_rp[0]), + .DPRA1(plm_dfm_deframe1_dwbuf_reg_rp[1]), + .DPRA2(plm_dfm_deframe1_dwbuf_reg_rp[2]), + .DPRA3(plm_dfm_deframe1_dwbuf_reg_rp[3]), + .SPO(NLW_plm_dfm_deframe1_dwbuf_L0B3_SPO_UNCONNECTED), + .WE(plm_dfm_deframe1_N_22418_i) + ); + RAM16X1D plm_dfm_deframe1_dwbuf_L0B4 ( + .DPO(plm_dfm_deframe1_dwbuf_dpo_out[28]), + .WCLK(mgt_clk), + .D(plm_dfm_deframe1_dwbuf_wd_l0_i_m4_0[4]), + .A0(plm_dfm_deframe1_dwbuf_reg_wp0[0]), + .A1(plm_dfm_deframe1_dwbuf_reg_wp0[1]), + .A2(plm_dfm_deframe1_dwbuf_reg_wp0[2]), + .A3(plm_dfm_deframe1_dwbuf_reg_wp0[3]), + .DPRA0(plm_dfm_deframe1_dwbuf_reg_rp[0]), + .DPRA1(plm_dfm_deframe1_dwbuf_reg_rp[1]), + .DPRA2(plm_dfm_deframe1_dwbuf_reg_rp[2]), + .DPRA3(plm_dfm_deframe1_dwbuf_reg_rp[3]), + .SPO(NLW_plm_dfm_deframe1_dwbuf_L0B4_SPO_UNCONNECTED), + .WE(plm_dfm_deframe1_N_22418_i) + ); + RAM16X1D plm_dfm_deframe1_dwbuf_L0B5 ( + .DPO(plm_dfm_deframe1_dwbuf_dpo_out[29]), + .WCLK(mgt_clk), + .D(plm_dfm_deframe1_dwbuf_wd_l0_i_m4_0[5]), + .A0(plm_dfm_deframe1_dwbuf_reg_wp0[0]), + .A1(plm_dfm_deframe1_dwbuf_reg_wp0[1]), + .A2(plm_dfm_deframe1_dwbuf_reg_wp0[2]), + .A3(plm_dfm_deframe1_dwbuf_reg_wp0[3]), + .DPRA0(plm_dfm_deframe1_dwbuf_reg_rp[0]), + .DPRA1(plm_dfm_deframe1_dwbuf_reg_rp[1]), + .DPRA2(plm_dfm_deframe1_dwbuf_reg_rp[2]), + .DPRA3(plm_dfm_deframe1_dwbuf_reg_rp[3]), + .SPO(NLW_plm_dfm_deframe1_dwbuf_L0B5_SPO_UNCONNECTED), + .WE(plm_dfm_deframe1_N_22418_i) + ); + RAM16X1D plm_dfm_deframe1_dwbuf_L0B6 ( + .DPO(plm_dfm_deframe1_dwbuf_dpo_out[30]), + .WCLK(mgt_clk), + .D(plm_dfm_deframe1_dwbuf_wd_l0_i_m4_0[6]), + .A0(plm_dfm_deframe1_dwbuf_reg_wp0[0]), + .A1(plm_dfm_deframe1_dwbuf_reg_wp0[1]), + .A2(plm_dfm_deframe1_dwbuf_reg_wp0[2]), + .A3(plm_dfm_deframe1_dwbuf_reg_wp0[3]), + .DPRA0(plm_dfm_deframe1_dwbuf_reg_rp[0]), + .DPRA1(plm_dfm_deframe1_dwbuf_reg_rp[1]), + .DPRA2(plm_dfm_deframe1_dwbuf_reg_rp[2]), + .DPRA3(plm_dfm_deframe1_dwbuf_reg_rp[3]), + .SPO(NLW_plm_dfm_deframe1_dwbuf_L0B6_SPO_UNCONNECTED), + .WE(plm_dfm_deframe1_N_22418_i) + ); + RAM16X1D plm_dfm_deframe1_dwbuf_L0B7 ( + .DPO(plm_dfm_deframe1_dwbuf_dpo_out[31]), + .WCLK(mgt_clk), + .D(plm_dfm_deframe1_dwbuf_wd_l0_i_m4_0[7]), + .A0(plm_dfm_deframe1_dwbuf_reg_wp0[0]), + .A1(plm_dfm_deframe1_dwbuf_reg_wp0[1]), + .A2(plm_dfm_deframe1_dwbuf_reg_wp0[2]), + .A3(plm_dfm_deframe1_dwbuf_reg_wp0[3]), + .DPRA0(plm_dfm_deframe1_dwbuf_reg_rp[0]), + .DPRA1(plm_dfm_deframe1_dwbuf_reg_rp[1]), + .DPRA2(plm_dfm_deframe1_dwbuf_reg_rp[2]), + .DPRA3(plm_dfm_deframe1_dwbuf_reg_rp[3]), + .SPO(NLW_plm_dfm_deframe1_dwbuf_L0B7_SPO_UNCONNECTED), + .WE(plm_dfm_deframe1_N_22418_i) + ); + RAM16X1D plm_dfm_deframe1_dwbuf_L1B0 ( + .DPO(plm_dfm_deframe1_dwbuf_dpo_out[16]), + .WCLK(mgt_clk), + .D(plm_dfm_deframe1_dwbuf_wd_l1_i_m4_0[0]), + .A0(plm_dfm_deframe1_dwbuf_reg_wp1[0]), + .A1(plm_dfm_deframe1_dwbuf_reg_wp1[1]), + .A2(plm_dfm_deframe1_dwbuf_reg_wp1[2]), + .A3(plm_dfm_deframe1_dwbuf_reg_wp1[3]), + .DPRA0(plm_dfm_deframe1_dwbuf_reg_rp[0]), + .DPRA1(plm_dfm_deframe1_dwbuf_reg_rp[1]), + .DPRA2(plm_dfm_deframe1_dwbuf_reg_rp[2]), + .DPRA3(plm_dfm_deframe1_dwbuf_reg_rp[3]), + .SPO(NLW_plm_dfm_deframe1_dwbuf_L1B0_SPO_UNCONNECTED), + .WE(plm_dfm_deframe1_push1) + ); + RAM16X1D plm_dfm_deframe1_dwbuf_L1B1 ( + .DPO(plm_dfm_deframe1_dwbuf_dpo_out[17]), + .WCLK(mgt_clk), + .D(plm_dfm_deframe1_dwbuf_wd_l1_i_m4_0[1]), + .A0(plm_dfm_deframe1_dwbuf_reg_wp1[0]), + .A1(plm_dfm_deframe1_dwbuf_reg_wp1[1]), + .A2(plm_dfm_deframe1_dwbuf_reg_wp1[2]), + .A3(plm_dfm_deframe1_dwbuf_reg_wp1[3]), + .DPRA0(plm_dfm_deframe1_dwbuf_reg_rp[0]), + .DPRA1(plm_dfm_deframe1_dwbuf_reg_rp[1]), + .DPRA2(plm_dfm_deframe1_dwbuf_reg_rp[2]), + .DPRA3(plm_dfm_deframe1_dwbuf_reg_rp[3]), + .SPO(NLW_plm_dfm_deframe1_dwbuf_L1B1_SPO_UNCONNECTED), + .WE(plm_dfm_deframe1_push1) + ); + RAM16X1D plm_dfm_deframe1_dwbuf_L1B2 ( + .DPO(plm_dfm_deframe1_dwbuf_dpo_out[18]), + .WCLK(mgt_clk), + .D(plm_dfm_deframe1_dwbuf_wd_l1_i_m4_0[2]), + .A0(plm_dfm_deframe1_dwbuf_reg_wp1[0]), + .A1(plm_dfm_deframe1_dwbuf_reg_wp1[1]), + .A2(plm_dfm_deframe1_dwbuf_reg_wp1[2]), + .A3(plm_dfm_deframe1_dwbuf_reg_wp1[3]), + .DPRA0(plm_dfm_deframe1_dwbuf_reg_rp[0]), + .DPRA1(plm_dfm_deframe1_dwbuf_reg_rp[1]), + .DPRA2(plm_dfm_deframe1_dwbuf_reg_rp[2]), + .DPRA3(plm_dfm_deframe1_dwbuf_reg_rp[3]), + .SPO(NLW_plm_dfm_deframe1_dwbuf_L1B2_SPO_UNCONNECTED), + .WE(plm_dfm_deframe1_push1) + ); + RAM16X1D plm_dfm_deframe1_dwbuf_L1B3 ( + .DPO(plm_dfm_deframe1_dwbuf_dpo_out[19]), + .WCLK(mgt_clk), + .D(plm_dfm_deframe1_dwbuf_wd_l1_i_m4_0[3]), + .A0(plm_dfm_deframe1_dwbuf_reg_wp1[0]), + .A1(plm_dfm_deframe1_dwbuf_reg_wp1[1]), + .A2(plm_dfm_deframe1_dwbuf_reg_wp1[2]), + .A3(plm_dfm_deframe1_dwbuf_reg_wp1[3]), + .DPRA0(plm_dfm_deframe1_dwbuf_reg_rp[0]), + .DPRA1(plm_dfm_deframe1_dwbuf_reg_rp[1]), + .DPRA2(plm_dfm_deframe1_dwbuf_reg_rp[2]), + .DPRA3(plm_dfm_deframe1_dwbuf_reg_rp[3]), + .SPO(NLW_plm_dfm_deframe1_dwbuf_L1B3_SPO_UNCONNECTED), + .WE(plm_dfm_deframe1_push1) + ); + RAM16X1D plm_dfm_deframe1_dwbuf_L1B4 ( + .DPO(plm_dfm_deframe1_dwbuf_dpo_out[20]), + .WCLK(mgt_clk), + .D(plm_dfm_deframe1_dwbuf_wd_l1_i_m4_0[4]), + .A0(plm_dfm_deframe1_dwbuf_reg_wp1[0]), + .A1(plm_dfm_deframe1_dwbuf_reg_wp1[1]), + .A2(plm_dfm_deframe1_dwbuf_reg_wp1[2]), + .A3(plm_dfm_deframe1_dwbuf_reg_wp1[3]), + .DPRA0(plm_dfm_deframe1_dwbuf_reg_rp[0]), + .DPRA1(plm_dfm_deframe1_dwbuf_reg_rp[1]), + .DPRA2(plm_dfm_deframe1_dwbuf_reg_rp[2]), + .DPRA3(plm_dfm_deframe1_dwbuf_reg_rp[3]), + .SPO(NLW_plm_dfm_deframe1_dwbuf_L1B4_SPO_UNCONNECTED), + .WE(plm_dfm_deframe1_push1) + ); + RAM16X1D plm_dfm_deframe1_dwbuf_L1B5 ( + .DPO(plm_dfm_deframe1_dwbuf_dpo_out[21]), + .WCLK(mgt_clk), + .D(plm_dfm_deframe1_dwbuf_wd_l1_i_m4_0[5]), + .A0(plm_dfm_deframe1_dwbuf_reg_wp1[0]), + .A1(plm_dfm_deframe1_dwbuf_reg_wp1[1]), + .A2(plm_dfm_deframe1_dwbuf_reg_wp1[2]), + .A3(plm_dfm_deframe1_dwbuf_reg_wp1[3]), + .DPRA0(plm_dfm_deframe1_dwbuf_reg_rp[0]), + .DPRA1(plm_dfm_deframe1_dwbuf_reg_rp[1]), + .DPRA2(plm_dfm_deframe1_dwbuf_reg_rp[2]), + .DPRA3(plm_dfm_deframe1_dwbuf_reg_rp[3]), + .SPO(NLW_plm_dfm_deframe1_dwbuf_L1B5_SPO_UNCONNECTED), + .WE(plm_dfm_deframe1_push1) + ); + RAM16X1D plm_dfm_deframe1_dwbuf_L1B6 ( + .DPO(plm_dfm_deframe1_dwbuf_dpo_out[22]), + .WCLK(mgt_clk), + .D(plm_dfm_deframe1_dwbuf_wd_l1_i_m4_0[6]), + .A0(plm_dfm_deframe1_dwbuf_reg_wp1[0]), + .A1(plm_dfm_deframe1_dwbuf_reg_wp1[1]), + .A2(plm_dfm_deframe1_dwbuf_reg_wp1[2]), + .A3(plm_dfm_deframe1_dwbuf_reg_wp1[3]), + .DPRA0(plm_dfm_deframe1_dwbuf_reg_rp[0]), + .DPRA1(plm_dfm_deframe1_dwbuf_reg_rp[1]), + .DPRA2(plm_dfm_deframe1_dwbuf_reg_rp[2]), + .DPRA3(plm_dfm_deframe1_dwbuf_reg_rp[3]), + .SPO(NLW_plm_dfm_deframe1_dwbuf_L1B6_SPO_UNCONNECTED), + .WE(plm_dfm_deframe1_push1) + ); + RAM16X1D plm_dfm_deframe1_dwbuf_L1B7 ( + .DPO(plm_dfm_deframe1_dwbuf_dpo_out[23]), + .WCLK(mgt_clk), + .D(plm_dfm_deframe1_dwbuf_wd_l1_i_m4_0[7]), + .A0(plm_dfm_deframe1_dwbuf_reg_wp1[0]), + .A1(plm_dfm_deframe1_dwbuf_reg_wp1[1]), + .A2(plm_dfm_deframe1_dwbuf_reg_wp1[2]), + .A3(plm_dfm_deframe1_dwbuf_reg_wp1[3]), + .DPRA0(plm_dfm_deframe1_dwbuf_reg_rp[0]), + .DPRA1(plm_dfm_deframe1_dwbuf_reg_rp[1]), + .DPRA2(plm_dfm_deframe1_dwbuf_reg_rp[2]), + .DPRA3(plm_dfm_deframe1_dwbuf_reg_rp[3]), + .SPO(NLW_plm_dfm_deframe1_dwbuf_L1B7_SPO_UNCONNECTED), + .WE(plm_dfm_deframe1_push1) + ); + RAM16X1D plm_dfm_deframe1_dwbuf_L2B0 ( + .DPO(plm_dfm_deframe1_dwbuf_dpo_out[8]), + .WCLK(mgt_clk), + .D(plm_dfm_deframe1_dwbuf_wd_l2_i_m4_0[0]), + .A0(plm_dfm_deframe1_dwbuf_reg_wp2[0]), + .A1(plm_dfm_deframe1_dwbuf_reg_wp2[1]), + .A2(plm_dfm_deframe1_dwbuf_reg_wp2[2]), + .A3(plm_dfm_deframe1_dwbuf_reg_wp2[3]), + .DPRA0(plm_dfm_deframe1_dwbuf_reg_rp[0]), + .DPRA1(plm_dfm_deframe1_dwbuf_reg_rp[1]), + .DPRA2(plm_dfm_deframe1_dwbuf_reg_rp[2]), + .DPRA3(plm_dfm_deframe1_dwbuf_reg_rp[3]), + .SPO(NLW_plm_dfm_deframe1_dwbuf_L2B0_SPO_UNCONNECTED), + .WE(plm_dfm_deframe1_N_87731_i) + ); + RAM16X1D plm_dfm_deframe1_dwbuf_L2B1 ( + .DPO(plm_dfm_deframe1_dwbuf_dpo_out[9]), + .WCLK(mgt_clk), + .D(plm_dfm_deframe1_dwbuf_wd_l2_i_m4_0[1]), + .A0(plm_dfm_deframe1_dwbuf_reg_wp2[0]), + .A1(plm_dfm_deframe1_dwbuf_reg_wp2[1]), + .A2(plm_dfm_deframe1_dwbuf_reg_wp2[2]), + .A3(plm_dfm_deframe1_dwbuf_reg_wp2[3]), + .DPRA0(plm_dfm_deframe1_dwbuf_reg_rp[0]), + .DPRA1(plm_dfm_deframe1_dwbuf_reg_rp[1]), + .DPRA2(plm_dfm_deframe1_dwbuf_reg_rp[2]), + .DPRA3(plm_dfm_deframe1_dwbuf_reg_rp[3]), + .SPO(NLW_plm_dfm_deframe1_dwbuf_L2B1_SPO_UNCONNECTED), + .WE(plm_dfm_deframe1_N_87731_i) + ); + RAM16X1D plm_dfm_deframe1_dwbuf_L2B2 ( + .DPO(plm_dfm_deframe1_dwbuf_dpo_out[10]), + .WCLK(mgt_clk), + .D(plm_dfm_deframe1_dwbuf_wd_l2_i_m4_0[2]), + .A0(plm_dfm_deframe1_dwbuf_reg_wp2[0]), + .A1(plm_dfm_deframe1_dwbuf_reg_wp2[1]), + .A2(plm_dfm_deframe1_dwbuf_reg_wp2[2]), + .A3(plm_dfm_deframe1_dwbuf_reg_wp2[3]), + .DPRA0(plm_dfm_deframe1_dwbuf_reg_rp[0]), + .DPRA1(plm_dfm_deframe1_dwbuf_reg_rp[1]), + .DPRA2(plm_dfm_deframe1_dwbuf_reg_rp[2]), + .DPRA3(plm_dfm_deframe1_dwbuf_reg_rp[3]), + .SPO(NLW_plm_dfm_deframe1_dwbuf_L2B2_SPO_UNCONNECTED), + .WE(plm_dfm_deframe1_N_87731_i) + ); + RAM16X1D plm_dfm_deframe1_dwbuf_L2B3 ( + .DPO(plm_dfm_deframe1_dwbuf_dpo_out[11]), + .WCLK(mgt_clk), + .D(plm_dfm_deframe1_dwbuf_wd_l2_i_m4_0[3]), + .A0(plm_dfm_deframe1_dwbuf_reg_wp2[0]), + .A1(plm_dfm_deframe1_dwbuf_reg_wp2[1]), + .A2(plm_dfm_deframe1_dwbuf_reg_wp2[2]), + .A3(plm_dfm_deframe1_dwbuf_reg_wp2[3]), + .DPRA0(plm_dfm_deframe1_dwbuf_reg_rp[0]), + .DPRA1(plm_dfm_deframe1_dwbuf_reg_rp[1]), + .DPRA2(plm_dfm_deframe1_dwbuf_reg_rp[2]), + .DPRA3(plm_dfm_deframe1_dwbuf_reg_rp[3]), + .SPO(NLW_plm_dfm_deframe1_dwbuf_L2B3_SPO_UNCONNECTED), + .WE(plm_dfm_deframe1_N_87731_i) + ); + RAM16X1D plm_dfm_deframe1_dwbuf_L2B4 ( + .DPO(plm_dfm_deframe1_dwbuf_dpo_out[12]), + .WCLK(mgt_clk), + .D(plm_dfm_deframe1_dwbuf_wd_l2_i_m4_0[4]), + .A0(plm_dfm_deframe1_dwbuf_reg_wp2[0]), + .A1(plm_dfm_deframe1_dwbuf_reg_wp2[1]), + .A2(plm_dfm_deframe1_dwbuf_reg_wp2[2]), + .A3(plm_dfm_deframe1_dwbuf_reg_wp2[3]), + .DPRA0(plm_dfm_deframe1_dwbuf_reg_rp[0]), + .DPRA1(plm_dfm_deframe1_dwbuf_reg_rp[1]), + .DPRA2(plm_dfm_deframe1_dwbuf_reg_rp[2]), + .DPRA3(plm_dfm_deframe1_dwbuf_reg_rp[3]), + .SPO(NLW_plm_dfm_deframe1_dwbuf_L2B4_SPO_UNCONNECTED), + .WE(plm_dfm_deframe1_N_87731_i) + ); + RAM16X1D plm_dfm_deframe1_dwbuf_L2B5 ( + .DPO(plm_dfm_deframe1_dwbuf_dpo_out[13]), + .WCLK(mgt_clk), + .D(plm_dfm_deframe1_dwbuf_wd_l2_i_m4_0[5]), + .A0(plm_dfm_deframe1_dwbuf_reg_wp2[0]), + .A1(plm_dfm_deframe1_dwbuf_reg_wp2[1]), + .A2(plm_dfm_deframe1_dwbuf_reg_wp2[2]), + .A3(plm_dfm_deframe1_dwbuf_reg_wp2[3]), + .DPRA0(plm_dfm_deframe1_dwbuf_reg_rp[0]), + .DPRA1(plm_dfm_deframe1_dwbuf_reg_rp[1]), + .DPRA2(plm_dfm_deframe1_dwbuf_reg_rp[2]), + .DPRA3(plm_dfm_deframe1_dwbuf_reg_rp[3]), + .SPO(NLW_plm_dfm_deframe1_dwbuf_L2B5_SPO_UNCONNECTED), + .WE(plm_dfm_deframe1_N_87731_i) + ); + RAM16X1D plm_dfm_deframe1_dwbuf_L2B6 ( + .DPO(plm_dfm_deframe1_dwbuf_dpo_out[14]), + .WCLK(mgt_clk), + .D(plm_dfm_deframe1_dwbuf_wd_l2_i_m4_0[6]), + .A0(plm_dfm_deframe1_dwbuf_reg_wp2[0]), + .A1(plm_dfm_deframe1_dwbuf_reg_wp2[1]), + .A2(plm_dfm_deframe1_dwbuf_reg_wp2[2]), + .A3(plm_dfm_deframe1_dwbuf_reg_wp2[3]), + .DPRA0(plm_dfm_deframe1_dwbuf_reg_rp[0]), + .DPRA1(plm_dfm_deframe1_dwbuf_reg_rp[1]), + .DPRA2(plm_dfm_deframe1_dwbuf_reg_rp[2]), + .DPRA3(plm_dfm_deframe1_dwbuf_reg_rp[3]), + .SPO(NLW_plm_dfm_deframe1_dwbuf_L2B6_SPO_UNCONNECTED), + .WE(plm_dfm_deframe1_N_87731_i) + ); + RAM16X1D plm_dfm_deframe1_dwbuf_L2B7 ( + .DPO(plm_dfm_deframe1_dwbuf_dpo_out[15]), + .WCLK(mgt_clk), + .D(plm_dfm_deframe1_dwbuf_wd_l2_i_m4_0[7]), + .A0(plm_dfm_deframe1_dwbuf_reg_wp2[0]), + .A1(plm_dfm_deframe1_dwbuf_reg_wp2[1]), + .A2(plm_dfm_deframe1_dwbuf_reg_wp2[2]), + .A3(plm_dfm_deframe1_dwbuf_reg_wp2[3]), + .DPRA0(plm_dfm_deframe1_dwbuf_reg_rp[0]), + .DPRA1(plm_dfm_deframe1_dwbuf_reg_rp[1]), + .DPRA2(plm_dfm_deframe1_dwbuf_reg_rp[2]), + .DPRA3(plm_dfm_deframe1_dwbuf_reg_rp[3]), + .SPO(NLW_plm_dfm_deframe1_dwbuf_L2B7_SPO_UNCONNECTED), + .WE(plm_dfm_deframe1_N_87731_i) + ); + RAM16X1D plm_dfm_deframe1_dwbuf_L3B0 ( + .DPO(plm_dfm_deframe1_dwbuf_dpo_out[0]), + .WCLK(mgt_clk), + .D(plm_dfm_deframe1_dwbuf_wd_l3_i_m4_0[0]), + .A0(plm_dfm_deframe1_dwbuf_reg_wp3[0]), + .A1(plm_dfm_deframe1_dwbuf_reg_wp3[1]), + .A2(plm_dfm_deframe1_dwbuf_reg_wp3[2]), + .A3(plm_dfm_deframe1_dwbuf_reg_wp3[3]), + .DPRA0(plm_dfm_deframe1_dwbuf_reg_rp[0]), + .DPRA1(plm_dfm_deframe1_dwbuf_reg_rp[1]), + .DPRA2(plm_dfm_deframe1_dwbuf_reg_rp[2]), + .DPRA3(plm_dfm_deframe1_dwbuf_reg_rp[3]), + .SPO(NLW_plm_dfm_deframe1_dwbuf_L3B0_SPO_UNCONNECTED), + .WE(plm_dfm_deframe1_dwbuf_N_35533_i) + ); + RAM16X1D plm_dfm_deframe1_dwbuf_L3B1 ( + .DPO(plm_dfm_deframe1_dwbuf_dpo_out[1]), + .WCLK(mgt_clk), + .D(plm_dfm_deframe1_dwbuf_wd_l3_i_m4_0[1]), + .A0(plm_dfm_deframe1_dwbuf_reg_wp3[0]), + .A1(plm_dfm_deframe1_dwbuf_reg_wp3[1]), + .A2(plm_dfm_deframe1_dwbuf_reg_wp3[2]), + .A3(plm_dfm_deframe1_dwbuf_reg_wp3[3]), + .DPRA0(plm_dfm_deframe1_dwbuf_reg_rp[0]), + .DPRA1(plm_dfm_deframe1_dwbuf_reg_rp[1]), + .DPRA2(plm_dfm_deframe1_dwbuf_reg_rp[2]), + .DPRA3(plm_dfm_deframe1_dwbuf_reg_rp[3]), + .SPO(NLW_plm_dfm_deframe1_dwbuf_L3B1_SPO_UNCONNECTED), + .WE(plm_dfm_deframe1_dwbuf_N_35533_i) + ); + RAM16X1D plm_dfm_deframe1_dwbuf_L3B2 ( + .DPO(plm_dfm_deframe1_dwbuf_dpo_out[2]), + .WCLK(mgt_clk), + .D(plm_dfm_deframe1_dwbuf_wd_l3_i_m4_0[2]), + .A0(plm_dfm_deframe1_dwbuf_reg_wp3[0]), + .A1(plm_dfm_deframe1_dwbuf_reg_wp3[1]), + .A2(plm_dfm_deframe1_dwbuf_reg_wp3[2]), + .A3(plm_dfm_deframe1_dwbuf_reg_wp3[3]), + .DPRA0(plm_dfm_deframe1_dwbuf_reg_rp[0]), + .DPRA1(plm_dfm_deframe1_dwbuf_reg_rp[1]), + .DPRA2(plm_dfm_deframe1_dwbuf_reg_rp[2]), + .DPRA3(plm_dfm_deframe1_dwbuf_reg_rp[3]), + .SPO(NLW_plm_dfm_deframe1_dwbuf_L3B2_SPO_UNCONNECTED), + .WE(plm_dfm_deframe1_dwbuf_N_35533_i) + ); + RAM16X1D plm_dfm_deframe1_dwbuf_L3B3 ( + .DPO(plm_dfm_deframe1_dwbuf_dpo_out[3]), + .WCLK(mgt_clk), + .D(plm_dfm_deframe1_dwbuf_wd_l3_i_m4_0[3]), + .A0(plm_dfm_deframe1_dwbuf_reg_wp3[0]), + .A1(plm_dfm_deframe1_dwbuf_reg_wp3[1]), + .A2(plm_dfm_deframe1_dwbuf_reg_wp3[2]), + .A3(plm_dfm_deframe1_dwbuf_reg_wp3[3]), + .DPRA0(plm_dfm_deframe1_dwbuf_reg_rp[0]), + .DPRA1(plm_dfm_deframe1_dwbuf_reg_rp[1]), + .DPRA2(plm_dfm_deframe1_dwbuf_reg_rp[2]), + .DPRA3(plm_dfm_deframe1_dwbuf_reg_rp[3]), + .SPO(NLW_plm_dfm_deframe1_dwbuf_L3B3_SPO_UNCONNECTED), + .WE(plm_dfm_deframe1_dwbuf_N_35533_i) + ); + RAM16X1D plm_dfm_deframe1_dwbuf_L3B4 ( + .DPO(plm_dfm_deframe1_dwbuf_dpo_out[4]), + .WCLK(mgt_clk), + .D(plm_dfm_deframe1_dwbuf_wd_l3_i_m4_0[4]), + .A0(plm_dfm_deframe1_dwbuf_reg_wp3[0]), + .A1(plm_dfm_deframe1_dwbuf_reg_wp3[1]), + .A2(plm_dfm_deframe1_dwbuf_reg_wp3[2]), + .A3(plm_dfm_deframe1_dwbuf_reg_wp3[3]), + .DPRA0(plm_dfm_deframe1_dwbuf_reg_rp[0]), + .DPRA1(plm_dfm_deframe1_dwbuf_reg_rp[1]), + .DPRA2(plm_dfm_deframe1_dwbuf_reg_rp[2]), + .DPRA3(plm_dfm_deframe1_dwbuf_reg_rp[3]), + .SPO(NLW_plm_dfm_deframe1_dwbuf_L3B4_SPO_UNCONNECTED), + .WE(plm_dfm_deframe1_dwbuf_N_35533_i) + ); + RAM16X1D plm_dfm_deframe1_dwbuf_L3B5 ( + .DPO(plm_dfm_deframe1_dwbuf_dpo_out[5]), + .WCLK(mgt_clk), + .D(plm_dfm_deframe1_dwbuf_wd_l3_i_m4_0[5]), + .A0(plm_dfm_deframe1_dwbuf_reg_wp3[0]), + .A1(plm_dfm_deframe1_dwbuf_reg_wp3[1]), + .A2(plm_dfm_deframe1_dwbuf_reg_wp3[2]), + .A3(plm_dfm_deframe1_dwbuf_reg_wp3[3]), + .DPRA0(plm_dfm_deframe1_dwbuf_reg_rp[0]), + .DPRA1(plm_dfm_deframe1_dwbuf_reg_rp[1]), + .DPRA2(plm_dfm_deframe1_dwbuf_reg_rp[2]), + .DPRA3(plm_dfm_deframe1_dwbuf_reg_rp[3]), + .SPO(NLW_plm_dfm_deframe1_dwbuf_L3B5_SPO_UNCONNECTED), + .WE(plm_dfm_deframe1_dwbuf_N_35533_i) + ); + RAM16X1D plm_dfm_deframe1_dwbuf_L3B6 ( + .DPO(plm_dfm_deframe1_dwbuf_dpo_out[6]), + .WCLK(mgt_clk), + .D(plm_dfm_deframe1_dwbuf_wd_l3_i_m4_0[6]), + .A0(plm_dfm_deframe1_dwbuf_reg_wp3[0]), + .A1(plm_dfm_deframe1_dwbuf_reg_wp3[1]), + .A2(plm_dfm_deframe1_dwbuf_reg_wp3[2]), + .A3(plm_dfm_deframe1_dwbuf_reg_wp3[3]), + .DPRA0(plm_dfm_deframe1_dwbuf_reg_rp[0]), + .DPRA1(plm_dfm_deframe1_dwbuf_reg_rp[1]), + .DPRA2(plm_dfm_deframe1_dwbuf_reg_rp[2]), + .DPRA3(plm_dfm_deframe1_dwbuf_reg_rp[3]), + .SPO(NLW_plm_dfm_deframe1_dwbuf_L3B6_SPO_UNCONNECTED), + .WE(plm_dfm_deframe1_dwbuf_N_35533_i) + ); + RAM16X1D plm_dfm_deframe1_dwbuf_L3B7 ( + .DPO(plm_dfm_deframe1_dwbuf_dpo_out[7]), + .WCLK(mgt_clk), + .D(plm_dfm_deframe1_dwbuf_wd_l3_i_m4_0[7]), + .A0(plm_dfm_deframe1_dwbuf_reg_wp3[0]), + .A1(plm_dfm_deframe1_dwbuf_reg_wp3[1]), + .A2(plm_dfm_deframe1_dwbuf_reg_wp3[2]), + .A3(plm_dfm_deframe1_dwbuf_reg_wp3[3]), + .DPRA0(plm_dfm_deframe1_dwbuf_reg_rp[0]), + .DPRA1(plm_dfm_deframe1_dwbuf_reg_rp[1]), + .DPRA2(plm_dfm_deframe1_dwbuf_reg_rp[2]), + .DPRA3(plm_dfm_deframe1_dwbuf_reg_rp[3]), + .SPO(NLW_plm_dfm_deframe1_dwbuf_L3B7_SPO_UNCONNECTED), + .WE(plm_dfm_deframe1_dwbuf_N_35533_i) + ); + RAM16X1D plm_dfm_deframe1_dwbuf_L3S0 ( + .DPO(plm_dfm_deframe1_dwbuf_dpo_edbedg[0]), + .WCLK(mgt_clk), + .D(plm_dfm_deframe1_dwbuf_N_87784_i_1542), + .A0(plm_dfm_deframe1_dwbuf_reg_wp3[0]), + .A1(plm_dfm_deframe1_dwbuf_reg_wp3[1]), + .A2(plm_dfm_deframe1_dwbuf_reg_wp3[2]), + .A3(plm_dfm_deframe1_dwbuf_reg_wp3[3]), + .DPRA0(plm_dfm_deframe1_dwbuf_reg_rp[0]), + .DPRA1(plm_dfm_deframe1_dwbuf_reg_rp[1]), + .DPRA2(plm_dfm_deframe1_dwbuf_reg_rp[2]), + .DPRA3(plm_dfm_deframe1_dwbuf_reg_rp[3]), + .SPO(NLW_plm_dfm_deframe1_dwbuf_L3S0_SPO_UNCONNECTED), + .WE(plm_dfm_deframe1_dwbuf_N_35533_i) + ); + RAM16X1D plm_dfm_deframe1_dwbuf_L3S1 ( + .DPO(plm_dfm_deframe1_dwbuf_dpo_edbedg[1]), + .WCLK(mgt_clk), + .D(plm_dfm_deframe1_dwbuf_N_87783_i_1543), + .A0(plm_dfm_deframe1_dwbuf_reg_wp3[0]), + .A1(plm_dfm_deframe1_dwbuf_reg_wp3[1]), + .A2(plm_dfm_deframe1_dwbuf_reg_wp3[2]), + .A3(plm_dfm_deframe1_dwbuf_reg_wp3[3]), + .DPRA0(plm_dfm_deframe1_dwbuf_reg_rp[0]), + .DPRA1(plm_dfm_deframe1_dwbuf_reg_rp[1]), + .DPRA2(plm_dfm_deframe1_dwbuf_reg_rp[2]), + .DPRA3(plm_dfm_deframe1_dwbuf_reg_rp[3]), + .SPO(NLW_plm_dfm_deframe1_dwbuf_L3S1_SPO_UNCONNECTED), + .WE(plm_dfm_deframe1_dwbuf_N_35533_i) + ); + MUXCY_L plm_dfm_deframe1_dwbuf_un1_reg_cnt_1_cry_0 ( + .CI(plm_dfm_deframe1_dwbuf_GND_1538), + .DI(plm_dfm_deframe1_dwbuf_reg_cnt[0]), + .LO(plm_dfm_deframe1_dwbuf_un1_reg_cnt_1_cry_0_1539), + .S(plm_dfm_deframe1_dwbuf_un1_reg_cnt_1_axb_0_1548) + ); + MUXCY_L plm_dfm_deframe1_dwbuf_un1_reg_cnt_1_cry_1 ( + .CI(plm_dfm_deframe1_dwbuf_un1_reg_cnt_1_cry_0_1539), + .DI(plm_dfm_deframe1_dwbuf_reg_cnt[1]), + .LO(plm_dfm_deframe1_dwbuf_un1_reg_cnt_1_cry_1_1540), + .S(plm_dfm_deframe1_dwbuf_un1_reg_cnt_1_axb_1_1550) + ); + XORCY plm_dfm_deframe1_dwbuf_un1_reg_cnt_1_s_1 ( + .CI(plm_dfm_deframe1_dwbuf_un1_reg_cnt_1_cry_0_1539), + .LI(plm_dfm_deframe1_dwbuf_un1_reg_cnt_1_axb_1_1550), + .O(plm_dfm_deframe1_dwbuf_un1_reg_cnt_1_s_1_1547) + ); + MUXCY_L plm_dfm_deframe1_dwbuf_un1_reg_cnt_1_cry_2 ( + .CI(plm_dfm_deframe1_dwbuf_un1_reg_cnt_1_cry_1_1540), + .DI(plm_dfm_deframe1_dwbuf_reg_cnt[2]), + .LO(plm_dfm_deframe1_dwbuf_un1_reg_cnt_1_cry_2_1541), + .S(plm_dfm_deframe1_dwbuf_un1_reg_cnt_1_axb_2_1551) + ); + XORCY plm_dfm_deframe1_dwbuf_un1_reg_cnt_1_s_2 ( + .CI(plm_dfm_deframe1_dwbuf_un1_reg_cnt_1_cry_1_1540), + .LI(plm_dfm_deframe1_dwbuf_un1_reg_cnt_1_axb_2_1551), + .O(plm_dfm_deframe1_dwbuf_un1_reg_cnt_1_s_2_1546) + ); + XORCY plm_dfm_deframe1_dwbuf_un1_reg_cnt_1_s_3 ( + .CI(plm_dfm_deframe1_dwbuf_un1_reg_cnt_1_cry_2_1541), + .LI(plm_dfm_deframe1_dwbuf_un1_reg_cnt_1_axb_3_1552), + .O(plm_dfm_deframe1_dwbuf_un1_reg_cnt_1_s_3_1545) + ); + defparam plm_dfm_deframe1_dwbuf_pointers_reg_wp0_4_p4.INIT = 16'h8000; + LUT4_L plm_dfm_deframe1_dwbuf_pointers_reg_wp0_4_p4 ( + .I0(plm_dfm_deframe1_N_22418_i), + .I1(plm_dfm_deframe1_dwbuf_reg_wp0[0]), + .I2(plm_dfm_deframe1_dwbuf_reg_wp0[1]), + .I3(plm_dfm_deframe1_dwbuf_reg_wp0[2]), + .LO(plm_dfm_deframe1_dwbuf_reg_wp0_4_p4) + ); + defparam plm_dfm_deframe1_dwbuf_pointers_reg_wp1_4_p4.INIT = 16'h8000; + LUT4_L plm_dfm_deframe1_dwbuf_pointers_reg_wp1_4_p4 ( + .I0(plm_dfm_deframe1_dwbuf_reg_wp1[0]), + .I1(plm_dfm_deframe1_dwbuf_reg_wp1[1]), + .I2(plm_dfm_deframe1_dwbuf_reg_wp1[2]), + .I3(plm_dfm_deframe1_push1), + .LO(plm_dfm_deframe1_dwbuf_reg_wp1_4_p4) + ); + defparam plm_dfm_deframe1_dwbuf_pointers_reg_wp2_4_p4.INIT = 16'h4000; + LUT4_L plm_dfm_deframe1_dwbuf_pointers_reg_wp2_4_p4 ( + .I0(plm_dfm_deframe1_reg_push_0_i_0[2]), + .I1(plm_dfm_deframe1_dwbuf_reg_wp2[0]), + .I2(plm_dfm_deframe1_dwbuf_reg_wp2[1]), + .I3(plm_dfm_deframe1_dwbuf_reg_wp2[2]), + .LO(plm_dfm_deframe1_dwbuf_reg_wp2_4_p4) + ); + defparam plm_dfm_deframe1_dwbuf_pointers_reg_wp3_4_p4.INIT = 16'h8000; + LUT4_L plm_dfm_deframe1_dwbuf_pointers_reg_wp3_4_p4 ( + .I0(plm_dfm_deframe1_dwbuf_N_35533_i), + .I1(plm_dfm_deframe1_dwbuf_reg_wp3[0]), + .I2(plm_dfm_deframe1_dwbuf_reg_wp3[1]), + .I3(plm_dfm_deframe1_dwbuf_reg_wp3[2]), + .LO(plm_dfm_deframe1_dwbuf_reg_wp3_4_p4) + ); + defparam plm_dfm_deframe1_dwbuf_pointers_reg_rp_4_p4.INIT = 16'h8000; + LUT4_L plm_dfm_deframe1_dwbuf_pointers_reg_rp_4_p4 ( + .I0(plm_dfm_deframe1_N_35550_i), + .I1(plm_dfm_deframe1_dwbuf_reg_rp[0]), + .I2(plm_dfm_deframe1_dwbuf_reg_rp[1]), + .I3(plm_dfm_deframe1_dwbuf_reg_rp[2]), + .LO(plm_dfm_deframe1_dwbuf_reg_rp_4_p4) + ); + defparam plm_dfm_deframe1_dwbuf_un1_reg_empty19_0_o2_i_o4_0.INIT = 4'h1; + LUT2 plm_dfm_deframe1_dwbuf_un1_reg_empty19_0_o2_i_o4_0 ( + .I0(plm_dfm_deframe1_reg_phi1), + .I1(plm_phy_cke_0_712), + .O(plm_dfm_deframe1_N_35534_i) + ); + defparam plm_dfm_deframe1_dwbuf_wd_s0_i_m4_0_1_.INIT = 8'hE4; + LUT3 plm_dfm_deframe1_dwbuf_wd_s0_i_m4_0_1_ ( + .I0(plm_dfm_deframe1_high0), + .I1(plm_dfm_deframe1_reg_delay_sdp[0]), + .I2(plm_dfm_deframe1_reg_delay_sdp[1]), + .O(plm_dfm_deframe1_dwbuf_wd_s0_i_m4_0[1]) + ); + defparam plm_dfm_deframe1_dwbuf_wd_s0_i_m4_0_0_.INIT = 8'hE4; + LUT3 plm_dfm_deframe1_dwbuf_wd_s0_i_m4_0_0_ ( + .I0(plm_dfm_deframe1_high0), + .I1(plm_dfm_deframe1_reg_delay_stp[0]), + .I2(plm_dfm_deframe1_reg_delay_stp[1]), + .O(plm_dfm_deframe1_dwbuf_wd_s0_i_m4_0[0]) + ); + defparam plm_dfm_deframe1_dwbuf_wd_l3_i_m4_0_7_.INIT = 8'hE4; + LUT3 plm_dfm_deframe1_dwbuf_wd_l3_i_m4_0_7_ ( + .I0(plm_dfm_deframe1_high3), + .I1(plm_dfm_deframe1_reg_delay_dat[7]), + .I2(plm_dfm_deframe1_reg_delay_dat[15]), + .O(plm_dfm_deframe1_dwbuf_wd_l3_i_m4_0[7]) + ); + defparam plm_dfm_deframe1_dwbuf_wd_l3_i_m4_0_6_.INIT = 8'hE4; + LUT3 plm_dfm_deframe1_dwbuf_wd_l3_i_m4_0_6_ ( + .I0(plm_dfm_deframe1_high3), + .I1(plm_dfm_deframe1_reg_delay_dat[6]), + .I2(plm_dfm_deframe1_reg_delay_dat[14]), + .O(plm_dfm_deframe1_dwbuf_wd_l3_i_m4_0[6]) + ); + defparam plm_dfm_deframe1_dwbuf_wd_l3_i_m4_0_5_.INIT = 8'hE4; + LUT3 plm_dfm_deframe1_dwbuf_wd_l3_i_m4_0_5_ ( + .I0(plm_dfm_deframe1_high3), + .I1(plm_dfm_deframe1_reg_delay_dat[5]), + .I2(plm_dfm_deframe1_reg_delay_dat[13]), + .O(plm_dfm_deframe1_dwbuf_wd_l3_i_m4_0[5]) + ); + defparam plm_dfm_deframe1_dwbuf_wd_l3_i_m4_0_4_.INIT = 8'hE4; + LUT3 plm_dfm_deframe1_dwbuf_wd_l3_i_m4_0_4_ ( + .I0(plm_dfm_deframe1_high3), + .I1(plm_dfm_deframe1_reg_delay_dat[4]), + .I2(plm_dfm_deframe1_reg_delay_dat[12]), + .O(plm_dfm_deframe1_dwbuf_wd_l3_i_m4_0[4]) + ); + defparam plm_dfm_deframe1_dwbuf_wd_l3_i_m4_0_3_.INIT = 8'hE4; + LUT3 plm_dfm_deframe1_dwbuf_wd_l3_i_m4_0_3_ ( + .I0(plm_dfm_deframe1_high3), + .I1(plm_dfm_deframe1_reg_delay_dat[3]), + .I2(plm_dfm_deframe1_reg_delay_dat[11]), + .O(plm_dfm_deframe1_dwbuf_wd_l3_i_m4_0[3]) + ); + defparam plm_dfm_deframe1_dwbuf_wd_l3_i_m4_0_2_.INIT = 8'hE4; + LUT3 plm_dfm_deframe1_dwbuf_wd_l3_i_m4_0_2_ ( + .I0(plm_dfm_deframe1_high3), + .I1(plm_dfm_deframe1_reg_delay_dat[2]), + .I2(plm_dfm_deframe1_reg_delay_dat[10]), + .O(plm_dfm_deframe1_dwbuf_wd_l3_i_m4_0[2]) + ); + defparam plm_dfm_deframe1_dwbuf_wd_l3_i_m4_0_1_.INIT = 8'hE4; + LUT3 plm_dfm_deframe1_dwbuf_wd_l3_i_m4_0_1_ ( + .I0(plm_dfm_deframe1_high3), + .I1(plm_dfm_deframe1_reg_delay_dat[1]), + .I2(plm_dfm_deframe1_reg_delay_dat[9]), + .O(plm_dfm_deframe1_dwbuf_wd_l3_i_m4_0[1]) + ); + defparam plm_dfm_deframe1_dwbuf_wd_l3_i_m4_0_0_.INIT = 8'hE4; + LUT3 plm_dfm_deframe1_dwbuf_wd_l3_i_m4_0_0_ ( + .I0(plm_dfm_deframe1_high3), + .I1(plm_dfm_deframe1_reg_delay_dat[0]), + .I2(plm_dfm_deframe1_reg_delay_dat[8]), + .O(plm_dfm_deframe1_dwbuf_wd_l3_i_m4_0[0]) + ); + defparam plm_dfm_deframe1_dwbuf_wd_l2_i_m4_0_7_.INIT = 8'hE4; + LUT3 plm_dfm_deframe1_dwbuf_wd_l2_i_m4_0_7_ ( + .I0(plm_dfm_deframe1_high2), + .I1(plm_dfm_deframe1_reg_delay_dat[7]), + .I2(plm_dfm_deframe1_reg_delay_dat[15]), + .O(plm_dfm_deframe1_dwbuf_wd_l2_i_m4_0[7]) + ); + defparam plm_dfm_deframe1_dwbuf_wd_l2_i_m4_0_6_.INIT = 8'hE4; + LUT3 plm_dfm_deframe1_dwbuf_wd_l2_i_m4_0_6_ ( + .I0(plm_dfm_deframe1_high2), + .I1(plm_dfm_deframe1_reg_delay_dat[6]), + .I2(plm_dfm_deframe1_reg_delay_dat[14]), + .O(plm_dfm_deframe1_dwbuf_wd_l2_i_m4_0[6]) + ); + defparam plm_dfm_deframe1_dwbuf_wd_l2_i_m4_0_5_.INIT = 8'hE4; + LUT3 plm_dfm_deframe1_dwbuf_wd_l2_i_m4_0_5_ ( + .I0(plm_dfm_deframe1_high2), + .I1(plm_dfm_deframe1_reg_delay_dat[5]), + .I2(plm_dfm_deframe1_reg_delay_dat[13]), + .O(plm_dfm_deframe1_dwbuf_wd_l2_i_m4_0[5]) + ); + defparam plm_dfm_deframe1_dwbuf_wd_l2_i_m4_0_4_.INIT = 8'hE4; + LUT3 plm_dfm_deframe1_dwbuf_wd_l2_i_m4_0_4_ ( + .I0(plm_dfm_deframe1_high2), + .I1(plm_dfm_deframe1_reg_delay_dat[4]), + .I2(plm_dfm_deframe1_reg_delay_dat[12]), + .O(plm_dfm_deframe1_dwbuf_wd_l2_i_m4_0[4]) + ); + defparam plm_dfm_deframe1_dwbuf_wd_l2_i_m4_0_3_.INIT = 8'hE4; + LUT3 plm_dfm_deframe1_dwbuf_wd_l2_i_m4_0_3_ ( + .I0(plm_dfm_deframe1_high2), + .I1(plm_dfm_deframe1_reg_delay_dat[3]), + .I2(plm_dfm_deframe1_reg_delay_dat[11]), + .O(plm_dfm_deframe1_dwbuf_wd_l2_i_m4_0[3]) + ); + defparam plm_dfm_deframe1_dwbuf_wd_l2_i_m4_0_2_.INIT = 8'hE4; + LUT3 plm_dfm_deframe1_dwbuf_wd_l2_i_m4_0_2_ ( + .I0(plm_dfm_deframe1_high2), + .I1(plm_dfm_deframe1_reg_delay_dat[2]), + .I2(plm_dfm_deframe1_reg_delay_dat[10]), + .O(plm_dfm_deframe1_dwbuf_wd_l2_i_m4_0[2]) + ); + defparam plm_dfm_deframe1_dwbuf_wd_l2_i_m4_0_1_.INIT = 8'hE4; + LUT3 plm_dfm_deframe1_dwbuf_wd_l2_i_m4_0_1_ ( + .I0(plm_dfm_deframe1_high2), + .I1(plm_dfm_deframe1_reg_delay_dat[1]), + .I2(plm_dfm_deframe1_reg_delay_dat[9]), + .O(plm_dfm_deframe1_dwbuf_wd_l2_i_m4_0[1]) + ); + defparam plm_dfm_deframe1_dwbuf_wd_l2_i_m4_0_0_.INIT = 8'hE4; + LUT3 plm_dfm_deframe1_dwbuf_wd_l2_i_m4_0_0_ ( + .I0(plm_dfm_deframe1_high2), + .I1(plm_dfm_deframe1_reg_delay_dat[0]), + .I2(plm_dfm_deframe1_reg_delay_dat[8]), + .O(plm_dfm_deframe1_dwbuf_wd_l2_i_m4_0[0]) + ); + defparam plm_dfm_deframe1_dwbuf_wd_l1_i_m4_0_7_.INIT = 8'hE4; + LUT3 plm_dfm_deframe1_dwbuf_wd_l1_i_m4_0_7_ ( + .I0(plm_dfm_deframe1_high1), + .I1(plm_dfm_deframe1_reg_delay_dat[7]), + .I2(plm_dfm_deframe1_reg_delay_dat[15]), + .O(plm_dfm_deframe1_dwbuf_wd_l1_i_m4_0[7]) + ); + defparam plm_dfm_deframe1_dwbuf_wd_l1_i_m4_0_6_.INIT = 8'hE4; + LUT3 plm_dfm_deframe1_dwbuf_wd_l1_i_m4_0_6_ ( + .I0(plm_dfm_deframe1_high1), + .I1(plm_dfm_deframe1_reg_delay_dat[6]), + .I2(plm_dfm_deframe1_reg_delay_dat[14]), + .O(plm_dfm_deframe1_dwbuf_wd_l1_i_m4_0[6]) + ); + defparam plm_dfm_deframe1_dwbuf_wd_l1_i_m4_0_5_.INIT = 8'hE4; + LUT3 plm_dfm_deframe1_dwbuf_wd_l1_i_m4_0_5_ ( + .I0(plm_dfm_deframe1_high1), + .I1(plm_dfm_deframe1_reg_delay_dat[5]), + .I2(plm_dfm_deframe1_reg_delay_dat[13]), + .O(plm_dfm_deframe1_dwbuf_wd_l1_i_m4_0[5]) + ); + defparam plm_dfm_deframe1_dwbuf_wd_l1_i_m4_0_4_.INIT = 8'hE4; + LUT3 plm_dfm_deframe1_dwbuf_wd_l1_i_m4_0_4_ ( + .I0(plm_dfm_deframe1_high1), + .I1(plm_dfm_deframe1_reg_delay_dat[4]), + .I2(plm_dfm_deframe1_reg_delay_dat[12]), + .O(plm_dfm_deframe1_dwbuf_wd_l1_i_m4_0[4]) + ); + defparam plm_dfm_deframe1_dwbuf_wd_l1_i_m4_0_3_.INIT = 8'hE4; + LUT3 plm_dfm_deframe1_dwbuf_wd_l1_i_m4_0_3_ ( + .I0(plm_dfm_deframe1_high1), + .I1(plm_dfm_deframe1_reg_delay_dat[3]), + .I2(plm_dfm_deframe1_reg_delay_dat[11]), + .O(plm_dfm_deframe1_dwbuf_wd_l1_i_m4_0[3]) + ); + defparam plm_dfm_deframe1_dwbuf_wd_l1_i_m4_0_2_.INIT = 8'hE4; + LUT3 plm_dfm_deframe1_dwbuf_wd_l1_i_m4_0_2_ ( + .I0(plm_dfm_deframe1_high1), + .I1(plm_dfm_deframe1_reg_delay_dat[2]), + .I2(plm_dfm_deframe1_reg_delay_dat[10]), + .O(plm_dfm_deframe1_dwbuf_wd_l1_i_m4_0[2]) + ); + defparam plm_dfm_deframe1_dwbuf_wd_l1_i_m4_0_1_.INIT = 8'hE4; + LUT3 plm_dfm_deframe1_dwbuf_wd_l1_i_m4_0_1_ ( + .I0(plm_dfm_deframe1_high1), + .I1(plm_dfm_deframe1_reg_delay_dat[1]), + .I2(plm_dfm_deframe1_reg_delay_dat[9]), + .O(plm_dfm_deframe1_dwbuf_wd_l1_i_m4_0[1]) + ); + defparam plm_dfm_deframe1_dwbuf_wd_l1_i_m4_0_0_.INIT = 8'hE4; + LUT3 plm_dfm_deframe1_dwbuf_wd_l1_i_m4_0_0_ ( + .I0(plm_dfm_deframe1_high1), + .I1(plm_dfm_deframe1_reg_delay_dat[0]), + .I2(plm_dfm_deframe1_reg_delay_dat[8]), + .O(plm_dfm_deframe1_dwbuf_wd_l1_i_m4_0[0]) + ); + defparam plm_dfm_deframe1_dwbuf_wd_l0_i_m4_0_7_.INIT = 8'hE4; + LUT3 plm_dfm_deframe1_dwbuf_wd_l0_i_m4_0_7_ ( + .I0(plm_dfm_deframe1_high0), + .I1(plm_dfm_deframe1_reg_delay_dat[7]), + .I2(plm_dfm_deframe1_reg_delay_dat[15]), + .O(plm_dfm_deframe1_dwbuf_wd_l0_i_m4_0[7]) + ); + defparam plm_dfm_deframe1_dwbuf_wd_l0_i_m4_0_6_.INIT = 8'hE4; + LUT3 plm_dfm_deframe1_dwbuf_wd_l0_i_m4_0_6_ ( + .I0(plm_dfm_deframe1_high0), + .I1(plm_dfm_deframe1_reg_delay_dat[6]), + .I2(plm_dfm_deframe1_reg_delay_dat[14]), + .O(plm_dfm_deframe1_dwbuf_wd_l0_i_m4_0[6]) + ); + defparam plm_dfm_deframe1_dwbuf_wd_l0_i_m4_0_5_.INIT = 8'hE4; + LUT3 plm_dfm_deframe1_dwbuf_wd_l0_i_m4_0_5_ ( + .I0(plm_dfm_deframe1_high0), + .I1(plm_dfm_deframe1_reg_delay_dat[5]), + .I2(plm_dfm_deframe1_reg_delay_dat[13]), + .O(plm_dfm_deframe1_dwbuf_wd_l0_i_m4_0[5]) + ); + defparam plm_dfm_deframe1_dwbuf_wd_l0_i_m4_0_4_.INIT = 8'hE4; + LUT3 plm_dfm_deframe1_dwbuf_wd_l0_i_m4_0_4_ ( + .I0(plm_dfm_deframe1_high0), + .I1(plm_dfm_deframe1_reg_delay_dat[4]), + .I2(plm_dfm_deframe1_reg_delay_dat[12]), + .O(plm_dfm_deframe1_dwbuf_wd_l0_i_m4_0[4]) + ); + defparam plm_dfm_deframe1_dwbuf_wd_l0_i_m4_0_3_.INIT = 8'hE4; + LUT3 plm_dfm_deframe1_dwbuf_wd_l0_i_m4_0_3_ ( + .I0(plm_dfm_deframe1_high0), + .I1(plm_dfm_deframe1_reg_delay_dat[3]), + .I2(plm_dfm_deframe1_reg_delay_dat[11]), + .O(plm_dfm_deframe1_dwbuf_wd_l0_i_m4_0[3]) + ); + defparam plm_dfm_deframe1_dwbuf_wd_l0_i_m4_0_2_.INIT = 8'hE4; + LUT3 plm_dfm_deframe1_dwbuf_wd_l0_i_m4_0_2_ ( + .I0(plm_dfm_deframe1_high0), + .I1(plm_dfm_deframe1_reg_delay_dat[2]), + .I2(plm_dfm_deframe1_reg_delay_dat[10]), + .O(plm_dfm_deframe1_dwbuf_wd_l0_i_m4_0[2]) + ); + defparam plm_dfm_deframe1_dwbuf_wd_l0_i_m4_0_1_.INIT = 8'hE4; + LUT3 plm_dfm_deframe1_dwbuf_wd_l0_i_m4_0_1_ ( + .I0(plm_dfm_deframe1_high0), + .I1(plm_dfm_deframe1_reg_delay_dat[1]), + .I2(plm_dfm_deframe1_reg_delay_dat[9]), + .O(plm_dfm_deframe1_dwbuf_wd_l0_i_m4_0[1]) + ); + defparam plm_dfm_deframe1_dwbuf_wd_l0_i_m4_0_0_.INIT = 8'hE4; + LUT3 plm_dfm_deframe1_dwbuf_wd_l0_i_m4_0_0_ ( + .I0(plm_dfm_deframe1_high0), + .I1(plm_dfm_deframe1_reg_delay_dat[0]), + .I2(plm_dfm_deframe1_reg_delay_dat[8]), + .O(plm_dfm_deframe1_dwbuf_wd_l0_i_m4_0[0]) + ); + defparam plm_dfm_deframe1_dwbuf_un1_reg_empty19_0_o2_i_o4.INIT = 16'h008C; + LUT4 plm_dfm_deframe1_dwbuf_un1_reg_empty19_0_o2_i_o4 ( + .I0(plm_dfm_deframe1_reg_fsm_last_substate[0]), + .I1(plm_dfm_deframe1_reg_fsm_last_substate[1]), + .I2(plm_dfm_deframe1_reg_fsm_substate[0]), + .I3(plm_dfm_deframe1_reg_fsm_substate[1]), + .O(plm_dfm_deframe1_dwbuf_N_35533_i) + ); + defparam plm_dfm_deframe1_dwbuf_un1_reg_empty19_0_o2_i_o4_1.INIT = 8'h28; + LUT3 plm_dfm_deframe1_dwbuf_un1_reg_empty19_0_o2_i_o4_1 ( + .I0(plm_dfm_deframe1_N_35527_i), + .I1(plm_dfm_deframe1_dword_sdpstp[0]), + .I2(plm_dfm_deframe1_dword_sdpstp[1]), + .O(plm_dfm_deframe1_N_35545_i) + ); + defparam plm_dfm_deframe1_dwbuf_pointers_reg_empty_8_0_i_0.INIT = 8'h82; + LUT3 plm_dfm_deframe1_dwbuf_pointers_reg_empty_8_0_i_0 ( + .I0(plm_dfm_deframe1_dwbuf_reg_cnt[0]), + .I1(plm_dfm_deframe1_dwbuf_reg_cnt[1]), + .I2(plm_dfm_deframe1_dwbuf_reg_cnt[2]), + .O(plm_dfm_deframe1_dwbuf_reg_empty_8_0_i_0) + ); + defparam plm_dfm_deframe1_dwbuf_N_87784_i.INIT = 16'hFEBA; + LUT4 plm_dfm_deframe1_dwbuf_N_87784_i ( + .I0(plm_dfm_deframe1_ferr), + .I1(plm_dfm_deframe1_high3), + .I2(plm_dfm_deframe1_reg_delay_edg[0]), + .I3(plm_dfm_deframe1_reg_delay_edg[1]), + .O(plm_dfm_deframe1_dwbuf_N_87784_i_1542) + ); + defparam plm_dfm_deframe1_dwbuf_N_87783_i.INIT = 16'hFEBA; + LUT4 plm_dfm_deframe1_dwbuf_N_87783_i ( + .I0(plm_dfm_deframe1_ferr), + .I1(plm_dfm_deframe1_high3), + .I2(plm_dfm_deframe1_reg_delay_edb[0]), + .I3(plm_dfm_deframe1_reg_delay_edb[1]), + .O(plm_dfm_deframe1_dwbuf_N_87783_i_1543) + ); + defparam plm_dfm_deframe1_dwbuf_un1_reg_cnt_1_axb_0.INIT = 4'h6; + LUT2 plm_dfm_deframe1_dwbuf_un1_reg_cnt_1_axb_0 ( + .I0(plm_dfm_deframe1_dwbuf_N_35515_i), + .I1(plm_dfm_deframe1_dwbuf_reg_cnt[0]), + .O(plm_dfm_deframe1_dwbuf_un1_reg_cnt_1_axb_0_1548) + ); + defparam plm_dfm_deframe1_dwbuf_pointers_reg_wp1_4_axbxc2.INIT = 16'h78F0; + LUT4_L plm_dfm_deframe1_dwbuf_pointers_reg_wp1_4_axbxc2 ( + .I0(plm_dfm_deframe1_dwbuf_reg_wp1[0]), + .I1(plm_dfm_deframe1_dwbuf_reg_wp1[1]), + .I2(plm_dfm_deframe1_dwbuf_reg_wp1[2]), + .I3(plm_dfm_deframe1_push1), + .LO(plm_dfm_deframe1_dwbuf_reg_wp1_4[2]) + ); + defparam plm_dfm_deframe1_dwbuf_pointers_reg_wp1_4_axbxc1.INIT = 8'h6C; + LUT3_L plm_dfm_deframe1_dwbuf_pointers_reg_wp1_4_axbxc1 ( + .I0(plm_dfm_deframe1_dwbuf_reg_wp1[0]), + .I1(plm_dfm_deframe1_dwbuf_reg_wp1[1]), + .I2(plm_dfm_deframe1_push1), + .LO(plm_dfm_deframe1_dwbuf_reg_wp1_4[1]) + ); + defparam plm_dfm_deframe1_dwbuf_pointers_reg_wp1_4_axbxc0.INIT = 4'h6; + LUT2_L plm_dfm_deframe1_dwbuf_pointers_reg_wp1_4_axbxc0 ( + .I0(plm_dfm_deframe1_dwbuf_reg_wp1[0]), + .I1(plm_dfm_deframe1_push1), + .LO(plm_dfm_deframe1_dwbuf_reg_wp1_4[0]) + ); + defparam plm_dfm_deframe1_dwbuf_pointers_reg_wp0_4_axbxc3.INIT = 4'h6; + LUT2_L plm_dfm_deframe1_dwbuf_pointers_reg_wp0_4_axbxc3 ( + .I0(plm_dfm_deframe1_dwbuf_reg_wp0_4_p4), + .I1(plm_dfm_deframe1_dwbuf_reg_wp0[3]), + .LO(plm_dfm_deframe1_dwbuf_reg_wp0_4[3]) + ); + defparam plm_dfm_deframe1_dwbuf_pointers_reg_wp0_4_axbxc2.INIT = 16'h7F80; + LUT4_L plm_dfm_deframe1_dwbuf_pointers_reg_wp0_4_axbxc2 ( + .I0(plm_dfm_deframe1_N_22418_i), + .I1(plm_dfm_deframe1_dwbuf_reg_wp0[0]), + .I2(plm_dfm_deframe1_dwbuf_reg_wp0[1]), + .I3(plm_dfm_deframe1_dwbuf_reg_wp0[2]), + .LO(plm_dfm_deframe1_dwbuf_reg_wp0_4[2]) + ); + defparam plm_dfm_deframe1_dwbuf_pointers_reg_wp0_4_axbxc1.INIT = 8'h78; + LUT3_L plm_dfm_deframe1_dwbuf_pointers_reg_wp0_4_axbxc1 ( + .I0(plm_dfm_deframe1_N_22418_i), + .I1(plm_dfm_deframe1_dwbuf_reg_wp0[0]), + .I2(plm_dfm_deframe1_dwbuf_reg_wp0[1]), + .LO(plm_dfm_deframe1_dwbuf_reg_wp0_4[1]) + ); + defparam plm_dfm_deframe1_dwbuf_pointers_reg_wp0_4_axbxc0.INIT = 4'h6; + LUT2_L plm_dfm_deframe1_dwbuf_pointers_reg_wp0_4_axbxc0 ( + .I0(plm_dfm_deframe1_N_22418_i), + .I1(plm_dfm_deframe1_dwbuf_reg_wp0[0]), + .LO(plm_dfm_deframe1_dwbuf_reg_wp0_4[0]) + ); + defparam plm_dfm_deframe1_dwbuf_pointers_reg_rp_4_axbxc3.INIT = 4'h6; + LUT2_L plm_dfm_deframe1_dwbuf_pointers_reg_rp_4_axbxc3 ( + .I0(plm_dfm_deframe1_dwbuf_reg_rp_4_p4), + .I1(plm_dfm_deframe1_dwbuf_reg_rp[3]), + .LO(plm_dfm_deframe1_dwbuf_reg_rp_4[3]) + ); + defparam plm_dfm_deframe1_dwbuf_pointers_reg_rp_4_axbxc2.INIT = 16'h7F80; + LUT4_L plm_dfm_deframe1_dwbuf_pointers_reg_rp_4_axbxc2 ( + .I0(plm_dfm_deframe1_N_35550_i), + .I1(plm_dfm_deframe1_dwbuf_reg_rp[0]), + .I2(plm_dfm_deframe1_dwbuf_reg_rp[1]), + .I3(plm_dfm_deframe1_dwbuf_reg_rp[2]), + .LO(plm_dfm_deframe1_dwbuf_reg_rp_4[2]) + ); + defparam plm_dfm_deframe1_dwbuf_pointers_reg_rp_4_axbxc1.INIT = 8'h78; + LUT3_L plm_dfm_deframe1_dwbuf_pointers_reg_rp_4_axbxc1 ( + .I0(plm_dfm_deframe1_N_35550_i), + .I1(plm_dfm_deframe1_dwbuf_reg_rp[0]), + .I2(plm_dfm_deframe1_dwbuf_reg_rp[1]), + .LO(plm_dfm_deframe1_dwbuf_reg_rp_4[1]) + ); + defparam plm_dfm_deframe1_dwbuf_pointers_reg_rp_4_axbxc0.INIT = 4'h6; + LUT2_L plm_dfm_deframe1_dwbuf_pointers_reg_rp_4_axbxc0 ( + .I0(plm_dfm_deframe1_N_35550_i), + .I1(plm_dfm_deframe1_dwbuf_reg_rp[0]), + .LO(plm_dfm_deframe1_dwbuf_reg_rp_4[0]) + ); + defparam plm_dfm_deframe1_dwbuf_pointers_reg_wp3_4_axbxc3.INIT = 4'h6; + LUT2_L plm_dfm_deframe1_dwbuf_pointers_reg_wp3_4_axbxc3 ( + .I0(plm_dfm_deframe1_dwbuf_reg_wp3_4_p4), + .I1(plm_dfm_deframe1_dwbuf_reg_wp3[3]), + .LO(plm_dfm_deframe1_dwbuf_reg_wp3_4[3]) + ); + defparam plm_dfm_deframe1_dwbuf_pointers_reg_wp3_4_axbxc2.INIT = 16'h7F80; + LUT4_L plm_dfm_deframe1_dwbuf_pointers_reg_wp3_4_axbxc2 ( + .I0(plm_dfm_deframe1_dwbuf_N_35533_i), + .I1(plm_dfm_deframe1_dwbuf_reg_wp3[0]), + .I2(plm_dfm_deframe1_dwbuf_reg_wp3[1]), + .I3(plm_dfm_deframe1_dwbuf_reg_wp3[2]), + .LO(plm_dfm_deframe1_dwbuf_reg_wp3_4[2]) + ); + defparam plm_dfm_deframe1_dwbuf_pointers_reg_wp3_4_axbxc1.INIT = 8'h78; + LUT3_L plm_dfm_deframe1_dwbuf_pointers_reg_wp3_4_axbxc1 ( + .I0(plm_dfm_deframe1_dwbuf_N_35533_i), + .I1(plm_dfm_deframe1_dwbuf_reg_wp3[0]), + .I2(plm_dfm_deframe1_dwbuf_reg_wp3[1]), + .LO(plm_dfm_deframe1_dwbuf_reg_wp3_4[1]) + ); + defparam plm_dfm_deframe1_dwbuf_pointers_reg_wp3_4_axbxc0.INIT = 4'h6; + LUT2_L plm_dfm_deframe1_dwbuf_pointers_reg_wp3_4_axbxc0 ( + .I0(plm_dfm_deframe1_dwbuf_N_35533_i), + .I1(plm_dfm_deframe1_dwbuf_reg_wp3[0]), + .LO(plm_dfm_deframe1_dwbuf_reg_wp3_4[0]) + ); + defparam plm_dfm_deframe1_dwbuf_pointers_reg_wp2_4_axbxc3.INIT = 4'h6; + LUT2_L plm_dfm_deframe1_dwbuf_pointers_reg_wp2_4_axbxc3 ( + .I0(plm_dfm_deframe1_dwbuf_reg_wp2_4_p4), + .I1(plm_dfm_deframe1_dwbuf_reg_wp2[3]), + .LO(plm_dfm_deframe1_dwbuf_reg_wp2_4[3]) + ); + defparam plm_dfm_deframe1_dwbuf_pointers_reg_wp2_4_axbxc2.INIT = 16'hBF40; + LUT4_L plm_dfm_deframe1_dwbuf_pointers_reg_wp2_4_axbxc2 ( + .I0(plm_dfm_deframe1_reg_push_0_i_0[2]), + .I1(plm_dfm_deframe1_dwbuf_reg_wp2[0]), + .I2(plm_dfm_deframe1_dwbuf_reg_wp2[1]), + .I3(plm_dfm_deframe1_dwbuf_reg_wp2[2]), + .LO(plm_dfm_deframe1_dwbuf_reg_wp2_4[2]) + ); + defparam plm_dfm_deframe1_dwbuf_pointers_reg_wp2_4_axbxc1.INIT = 8'hB4; + LUT3_L plm_dfm_deframe1_dwbuf_pointers_reg_wp2_4_axbxc1 ( + .I0(plm_dfm_deframe1_reg_push_0_i_0[2]), + .I1(plm_dfm_deframe1_dwbuf_reg_wp2[0]), + .I2(plm_dfm_deframe1_dwbuf_reg_wp2[1]), + .LO(plm_dfm_deframe1_dwbuf_reg_wp2_4[1]) + ); + defparam plm_dfm_deframe1_dwbuf_pointers_reg_wp2_4_axbxc0.INIT = 4'h9; + LUT2_L plm_dfm_deframe1_dwbuf_pointers_reg_wp2_4_axbxc0 ( + .I0(plm_dfm_deframe1_reg_push_0_i_0[2]), + .I1(plm_dfm_deframe1_dwbuf_reg_wp2[0]), + .LO(plm_dfm_deframe1_dwbuf_reg_wp2_4[0]) + ); + defparam plm_dfm_deframe1_dwbuf_pointers_reg_wp1_4_axbxc3.INIT = 4'h6; + LUT2_L plm_dfm_deframe1_dwbuf_pointers_reg_wp1_4_axbxc3 ( + .I0(plm_dfm_deframe1_dwbuf_reg_wp1_4_p4), + .I1(plm_dfm_deframe1_dwbuf_reg_wp1[3]), + .LO(plm_dfm_deframe1_dwbuf_reg_wp1_4[3]) + ); + defparam plm_dfm_deframe1_dwbuf_pointers_reg_empty_8_0_i.INIT = 16'h8004; + LUT4_L plm_dfm_deframe1_dwbuf_pointers_reg_empty_8_0_i ( + .I0(plm_dfm_deframe1_dwbuf_N_35533_i), + .I1(plm_dfm_deframe1_dwbuf_reg_empty_8_0_i_0), + .I2(plm_dfm_deframe1_dwbuf_reg_cnt[1]), + .I3(plm_dfm_deframe1_dwbuf_reg_cnt[3]), + .LO(plm_dfm_deframe1_dwbuf_N_35458_i) + ); + defparam plm_dfm_deframe1_dwbuf_un1_reg_empty19_0_o2_i_1.INIT = 16'h7770; + LUT4 plm_dfm_deframe1_dwbuf_un1_reg_empty19_0_o2_i_1 ( + .I0(plm_dfm_deframe1_N_35527_i), + .I1(plm_dfm_deframe1_N_35528_i), + .I2(plm_dfm_deframe1_N_35545_i), + .I3(plm_dfm_deframe1_dword_empty), + .O(plm_dfm_deframe1_dwbuf_un1_reg_empty19_0_o2_i_1_1544) + ); + defparam plm_dfm_deframe1_dwbuf_un1_reg_empty19_0_o2_i.INIT = 16'hFAD8; + LUT4 plm_dfm_deframe1_dwbuf_un1_reg_empty19_0_o2_i ( + .I0(plm_dfm_deframe1_dwbuf_N_35533_i), + .I1(plm_dfm_deframe1_N_35534_i), + .I2(plm_dfm_deframe1_N_35550_i), + .I3(plm_dfm_deframe1_dwbuf_un1_reg_empty19_0_o2_i_1_1544), + .O(plm_dfm_deframe1_dwbuf_N_35515_i) + ); + FDP plm_dfm_deframe1_dwbuf_reg_opt_empty ( + .PRE(plm_rst), + .C(mgt_clk), + .D(plm_dfm_deframe1_dwbuf_reg_empty_1549), + .Q(plm_dfm_deframe1_dword_empty) + ); + FDC plm_dfm_deframe1_dwbuf_reg_wp1_2_ ( + .C(mgt_clk), + .D(plm_dfm_deframe1_dwbuf_reg_wp1_4[2]), + .Q(plm_dfm_deframe1_dwbuf_reg_wp1[2]), + .CLR(plm_rst) + ); + FDC plm_dfm_deframe1_dwbuf_reg_wp1_1_ ( + .C(mgt_clk), + .D(plm_dfm_deframe1_dwbuf_reg_wp1_4[1]), + .Q(plm_dfm_deframe1_dwbuf_reg_wp1[1]), + .CLR(plm_rst) + ); + FDC plm_dfm_deframe1_dwbuf_reg_wp1_0_ ( + .C(mgt_clk), + .D(plm_dfm_deframe1_dwbuf_reg_wp1_4[0]), + .Q(plm_dfm_deframe1_dwbuf_reg_wp1[0]), + .CLR(plm_rst) + ); + FDC plm_dfm_deframe1_dwbuf_reg_wp0_3_ ( + .C(mgt_clk), + .D(plm_dfm_deframe1_dwbuf_reg_wp0_4[3]), + .Q(plm_dfm_deframe1_dwbuf_reg_wp0[3]), + .CLR(plm_rst) + ); + FDC plm_dfm_deframe1_dwbuf_reg_wp0_2_ ( + .C(mgt_clk), + .D(plm_dfm_deframe1_dwbuf_reg_wp0_4[2]), + .Q(plm_dfm_deframe1_dwbuf_reg_wp0[2]), + .CLR(plm_rst) + ); + FDC plm_dfm_deframe1_dwbuf_reg_wp0_1_ ( + .C(mgt_clk), + .D(plm_dfm_deframe1_dwbuf_reg_wp0_4[1]), + .Q(plm_dfm_deframe1_dwbuf_reg_wp0[1]), + .CLR(plm_rst) + ); + FDC plm_dfm_deframe1_dwbuf_reg_wp0_0_ ( + .C(mgt_clk), + .D(plm_dfm_deframe1_dwbuf_reg_wp0_4[0]), + .Q(plm_dfm_deframe1_dwbuf_reg_wp0[0]), + .CLR(plm_rst) + ); + FDC plm_dfm_deframe1_dwbuf_reg_rp_3_ ( + .C(mgt_clk), + .D(plm_dfm_deframe1_dwbuf_reg_rp_4[3]), + .Q(plm_dfm_deframe1_dwbuf_reg_rp[3]), + .CLR(plm_rst) + ); + FDC plm_dfm_deframe1_dwbuf_reg_rp_2_ ( + .C(mgt_clk), + .D(plm_dfm_deframe1_dwbuf_reg_rp_4[2]), + .Q(plm_dfm_deframe1_dwbuf_reg_rp[2]), + .CLR(plm_rst) + ); + FDC plm_dfm_deframe1_dwbuf_reg_rp_1_ ( + .C(mgt_clk), + .D(plm_dfm_deframe1_dwbuf_reg_rp_4[1]), + .Q(plm_dfm_deframe1_dwbuf_reg_rp[1]), + .CLR(plm_rst) + ); + FDC plm_dfm_deframe1_dwbuf_reg_rp_0_ ( + .C(mgt_clk), + .D(plm_dfm_deframe1_dwbuf_reg_rp_4[0]), + .Q(plm_dfm_deframe1_dwbuf_reg_rp[0]), + .CLR(plm_rst) + ); + FDC plm_dfm_deframe1_dwbuf_reg_opt_edbedg_1_ ( + .C(mgt_clk), + .D(plm_dfm_deframe1_dwbuf_dpo_edbedg[1]), + .Q(plm_dfm_deframe1_dword_edbedg[1]), + .CLR(plm_rst) + ); + FDC plm_dfm_deframe1_dwbuf_reg_opt_edbedg_0_ ( + .C(mgt_clk), + .D(plm_dfm_deframe1_dwbuf_dpo_edbedg[0]), + .Q(plm_dfm_deframe1_dword_edbedg[0]), + .CLR(plm_rst) + ); + FDC plm_dfm_deframe1_dwbuf_reg_cnt_3_ ( + .C(mgt_clk), + .D(plm_dfm_deframe1_dwbuf_un1_reg_cnt_1_s_3_1545), + .Q(plm_dfm_deframe1_dwbuf_reg_cnt[3]), + .CLR(plm_rst) + ); + FDC plm_dfm_deframe1_dwbuf_reg_cnt_2_ ( + .C(mgt_clk), + .D(plm_dfm_deframe1_dwbuf_un1_reg_cnt_1_s_2_1546), + .Q(plm_dfm_deframe1_dwbuf_reg_cnt[2]), + .CLR(plm_rst) + ); + FDC plm_dfm_deframe1_dwbuf_reg_cnt_1_ ( + .C(mgt_clk), + .D(plm_dfm_deframe1_dwbuf_un1_reg_cnt_1_s_1_1547), + .Q(plm_dfm_deframe1_dwbuf_reg_cnt[1]), + .CLR(plm_rst) + ); + FDC plm_dfm_deframe1_dwbuf_reg_cnt_0_ ( + .C(mgt_clk), + .D(plm_dfm_deframe1_dwbuf_un1_reg_cnt_1_axb_0_1548), + .Q(plm_dfm_deframe1_dwbuf_reg_cnt[0]), + .CLR(plm_rst) + ); + FDC plm_dfm_deframe1_dwbuf_reg_wp3_3_ ( + .C(mgt_clk), + .D(plm_dfm_deframe1_dwbuf_reg_wp3_4[3]), + .Q(plm_dfm_deframe1_dwbuf_reg_wp3[3]), + .CLR(plm_rst) + ); + FDC plm_dfm_deframe1_dwbuf_reg_wp3_2_ ( + .C(mgt_clk), + .D(plm_dfm_deframe1_dwbuf_reg_wp3_4[2]), + .Q(plm_dfm_deframe1_dwbuf_reg_wp3[2]), + .CLR(plm_rst) + ); + FDC plm_dfm_deframe1_dwbuf_reg_wp3_1_ ( + .C(mgt_clk), + .D(plm_dfm_deframe1_dwbuf_reg_wp3_4[1]), + .Q(plm_dfm_deframe1_dwbuf_reg_wp3[1]), + .CLR(plm_rst) + ); + FDC plm_dfm_deframe1_dwbuf_reg_wp3_0_ ( + .C(mgt_clk), + .D(plm_dfm_deframe1_dwbuf_reg_wp3_4[0]), + .Q(plm_dfm_deframe1_dwbuf_reg_wp3[0]), + .CLR(plm_rst) + ); + FDC plm_dfm_deframe1_dwbuf_reg_wp2_3_ ( + .C(mgt_clk), + .D(plm_dfm_deframe1_dwbuf_reg_wp2_4[3]), + .Q(plm_dfm_deframe1_dwbuf_reg_wp2[3]), + .CLR(plm_rst) + ); + FDC plm_dfm_deframe1_dwbuf_reg_wp2_2_ ( + .C(mgt_clk), + .D(plm_dfm_deframe1_dwbuf_reg_wp2_4[2]), + .Q(plm_dfm_deframe1_dwbuf_reg_wp2[2]), + .CLR(plm_rst) + ); + FDC plm_dfm_deframe1_dwbuf_reg_wp2_1_ ( + .C(mgt_clk), + .D(plm_dfm_deframe1_dwbuf_reg_wp2_4[1]), + .Q(plm_dfm_deframe1_dwbuf_reg_wp2[1]), + .CLR(plm_rst) + ); + FDC plm_dfm_deframe1_dwbuf_reg_wp2_0_ ( + .C(mgt_clk), + .D(plm_dfm_deframe1_dwbuf_reg_wp2_4[0]), + .Q(plm_dfm_deframe1_dwbuf_reg_wp2[0]), + .CLR(plm_rst) + ); + FDC plm_dfm_deframe1_dwbuf_reg_wp1_3_ ( + .C(mgt_clk), + .D(plm_dfm_deframe1_dwbuf_reg_wp1_4[3]), + .Q(plm_dfm_deframe1_dwbuf_reg_wp1[3]), + .CLR(plm_rst) + ); + FDC plm_dfm_deframe1_dwbuf_reg_opt_out_12_ ( + .C(mgt_clk), + .D(plm_dfm_deframe1_dwbuf_dpo_out[12]), + .Q(plm_dfm_deframe1_dword_out[12]), + .CLR(plm_rst) + ); + FDC plm_dfm_deframe1_dwbuf_reg_opt_out_11_ ( + .C(mgt_clk), + .D(plm_dfm_deframe1_dwbuf_dpo_out[11]), + .Q(plm_dfm_deframe1_dword_out[11]), + .CLR(plm_rst) + ); + FDC plm_dfm_deframe1_dwbuf_reg_opt_out_10_ ( + .C(mgt_clk), + .D(plm_dfm_deframe1_dwbuf_dpo_out[10]), + .Q(plm_dfm_deframe1_dword_out[10]), + .CLR(plm_rst) + ); + FDC plm_dfm_deframe1_dwbuf_reg_opt_out_9_ ( + .C(mgt_clk), + .D(plm_dfm_deframe1_dwbuf_dpo_out[9]), + .Q(plm_dfm_deframe1_dword_out[9]), + .CLR(plm_rst) + ); + FDC plm_dfm_deframe1_dwbuf_reg_opt_out_8_ ( + .C(mgt_clk), + .D(plm_dfm_deframe1_dwbuf_dpo_out[8]), + .Q(plm_dfm_deframe1_dword_out[8]), + .CLR(plm_rst) + ); + FDC plm_dfm_deframe1_dwbuf_reg_opt_out_7_ ( + .C(mgt_clk), + .D(plm_dfm_deframe1_dwbuf_dpo_out[7]), + .Q(plm_dfm_deframe1_dword_out[7]), + .CLR(plm_rst) + ); + FDC plm_dfm_deframe1_dwbuf_reg_opt_out_6_ ( + .C(mgt_clk), + .D(plm_dfm_deframe1_dwbuf_dpo_out[6]), + .Q(plm_dfm_deframe1_dword_out[6]), + .CLR(plm_rst) + ); + FDC plm_dfm_deframe1_dwbuf_reg_opt_out_5_ ( + .C(mgt_clk), + .D(plm_dfm_deframe1_dwbuf_dpo_out[5]), + .Q(plm_dfm_deframe1_dword_out[5]), + .CLR(plm_rst) + ); + FDC plm_dfm_deframe1_dwbuf_reg_opt_out_4_ ( + .C(mgt_clk), + .D(plm_dfm_deframe1_dwbuf_dpo_out[4]), + .Q(plm_dfm_deframe1_dword_out[4]), + .CLR(plm_rst) + ); + FDC plm_dfm_deframe1_dwbuf_reg_opt_out_3_ ( + .C(mgt_clk), + .D(plm_dfm_deframe1_dwbuf_dpo_out[3]), + .Q(plm_dfm_deframe1_dword_out[3]), + .CLR(plm_rst) + ); + FDC plm_dfm_deframe1_dwbuf_reg_opt_out_2_ ( + .C(mgt_clk), + .D(plm_dfm_deframe1_dwbuf_dpo_out[2]), + .Q(plm_dfm_deframe1_dword_out[2]), + .CLR(plm_rst) + ); + FDC plm_dfm_deframe1_dwbuf_reg_opt_out_1_ ( + .C(mgt_clk), + .D(plm_dfm_deframe1_dwbuf_dpo_out[1]), + .Q(plm_dfm_deframe1_dword_out[1]), + .CLR(plm_rst) + ); + FDC plm_dfm_deframe1_dwbuf_reg_opt_out_0_ ( + .C(mgt_clk), + .D(plm_dfm_deframe1_dwbuf_dpo_out[0]), + .Q(plm_dfm_deframe1_dword_out[0]), + .CLR(plm_rst) + ); + FDC plm_dfm_deframe1_dwbuf_reg_opt_sdpstp_1_ ( + .C(mgt_clk), + .D(plm_dfm_deframe1_dwbuf_dpo_sdpstp[1]), + .Q(plm_dfm_deframe1_dword_sdpstp[1]), + .CLR(plm_rst) + ); + FDC plm_dfm_deframe1_dwbuf_reg_opt_sdpstp_0_ ( + .C(mgt_clk), + .D(plm_dfm_deframe1_dwbuf_dpo_sdpstp[0]), + .Q(plm_dfm_deframe1_dword_sdpstp[0]), + .CLR(plm_rst) + ); + FDC plm_dfm_deframe1_dwbuf_reg_opt_out_27_ ( + .C(mgt_clk), + .D(plm_dfm_deframe1_dwbuf_dpo_out[27]), + .Q(plm_dfm_deframe1_dword_out[27]), + .CLR(plm_rst) + ); + FDC plm_dfm_deframe1_dwbuf_reg_opt_out_26_ ( + .C(mgt_clk), + .D(plm_dfm_deframe1_dwbuf_dpo_out[26]), + .Q(plm_dfm_deframe1_dword_out[26]), + .CLR(plm_rst) + ); + FDC plm_dfm_deframe1_dwbuf_reg_opt_out_25_ ( + .C(mgt_clk), + .D(plm_dfm_deframe1_dwbuf_dpo_out[25]), + .Q(plm_dfm_deframe1_dword_out[25]), + .CLR(plm_rst) + ); + FDC plm_dfm_deframe1_dwbuf_reg_opt_out_24_ ( + .C(mgt_clk), + .D(plm_dfm_deframe1_dwbuf_dpo_out[24]), + .Q(plm_dfm_deframe1_dword_out[24]), + .CLR(plm_rst) + ); + FDC plm_dfm_deframe1_dwbuf_reg_opt_out_23_ ( + .C(mgt_clk), + .D(plm_dfm_deframe1_dwbuf_dpo_out[23]), + .Q(plm_dfm_deframe1_dword_out[23]), + .CLR(plm_rst) + ); + FDC plm_dfm_deframe1_dwbuf_reg_opt_out_22_ ( + .C(mgt_clk), + .D(plm_dfm_deframe1_dwbuf_dpo_out[22]), + .Q(plm_dfm_deframe1_dword_out[22]), + .CLR(plm_rst) + ); + FDC plm_dfm_deframe1_dwbuf_reg_opt_out_21_ ( + .C(mgt_clk), + .D(plm_dfm_deframe1_dwbuf_dpo_out[21]), + .Q(plm_dfm_deframe1_dword_out[21]), + .CLR(plm_rst) + ); + FDC plm_dfm_deframe1_dwbuf_reg_opt_out_20_ ( + .C(mgt_clk), + .D(plm_dfm_deframe1_dwbuf_dpo_out[20]), + .Q(plm_dfm_deframe1_dword_out[20]), + .CLR(plm_rst) + ); + FDC plm_dfm_deframe1_dwbuf_reg_opt_out_19_ ( + .C(mgt_clk), + .D(plm_dfm_deframe1_dwbuf_dpo_out[19]), + .Q(plm_dfm_deframe1_dword_out[19]), + .CLR(plm_rst) + ); + FDC plm_dfm_deframe1_dwbuf_reg_opt_out_18_ ( + .C(mgt_clk), + .D(plm_dfm_deframe1_dwbuf_dpo_out[18]), + .Q(plm_dfm_deframe1_dword_out[18]), + .CLR(plm_rst) + ); + FDC plm_dfm_deframe1_dwbuf_reg_opt_out_17_ ( + .C(mgt_clk), + .D(plm_dfm_deframe1_dwbuf_dpo_out[17]), + .Q(plm_dfm_deframe1_dword_out[17]), + .CLR(plm_rst) + ); + FDC plm_dfm_deframe1_dwbuf_reg_opt_out_16_ ( + .C(mgt_clk), + .D(plm_dfm_deframe1_dwbuf_dpo_out[16]), + .Q(plm_dfm_deframe1_dword_out[16]), + .CLR(plm_rst) + ); + FDC plm_dfm_deframe1_dwbuf_reg_opt_out_15_ ( + .C(mgt_clk), + .D(plm_dfm_deframe1_dwbuf_dpo_out[15]), + .Q(plm_dfm_deframe1_dword_out[15]), + .CLR(plm_rst) + ); + FDC plm_dfm_deframe1_dwbuf_reg_opt_out_14_ ( + .C(mgt_clk), + .D(plm_dfm_deframe1_dwbuf_dpo_out[14]), + .Q(plm_dfm_deframe1_dword_out[14]), + .CLR(plm_rst) + ); + FDC plm_dfm_deframe1_dwbuf_reg_opt_out_13_ ( + .C(mgt_clk), + .D(plm_dfm_deframe1_dwbuf_dpo_out[13]), + .Q(plm_dfm_deframe1_dword_out[13]), + .CLR(plm_rst) + ); + FDC plm_dfm_deframe1_dwbuf_reg_opt_out_31_ ( + .C(mgt_clk), + .D(plm_dfm_deframe1_dwbuf_dpo_out[31]), + .Q(plm_dfm_deframe1_dword_out[31]), + .CLR(plm_rst) + ); + FDC plm_dfm_deframe1_dwbuf_reg_opt_out_30_ ( + .C(mgt_clk), + .D(plm_dfm_deframe1_dwbuf_dpo_out[30]), + .Q(plm_dfm_deframe1_dword_out[30]), + .CLR(plm_rst) + ); + FDC plm_dfm_deframe1_dwbuf_reg_opt_out_29_ ( + .C(mgt_clk), + .D(plm_dfm_deframe1_dwbuf_dpo_out[29]), + .Q(plm_dfm_deframe1_dword_out[29]), + .CLR(plm_rst) + ); + FDC plm_dfm_deframe1_dwbuf_reg_opt_out_28_ ( + .C(mgt_clk), + .D(plm_dfm_deframe1_dwbuf_dpo_out[28]), + .Q(plm_dfm_deframe1_dword_out[28]), + .CLR(plm_rst) + ); + FDPE plm_dfm_deframe1_dwbuf_reg_empty ( + .PRE(plm_rst), + .CE(plm_dfm_deframe1_dwbuf_N_35515_i), + .C(mgt_clk), + .D(plm_dfm_deframe1_dwbuf_N_35458_i), + .Q(plm_dfm_deframe1_dwbuf_reg_empty_1549) + ); + INV plm_dfm_deframe1_dwbuf_N_35534_i_i ( + .I(plm_dfm_deframe1_N_35534_i), + .O(plm_dfm_deframe1_N_35534_i_i) + ); + defparam plm_dfm_deframe1_dwbuf_un1_reg_cnt_1_axb_1.INIT = 8'hA6; + LUT3_L plm_dfm_deframe1_dwbuf_un1_reg_cnt_1_axb_1 ( + .I0(plm_dfm_deframe1_dwbuf_reg_cnt[1]), + .I1(plm_dfm_deframe1_N_35550_i), + .I2(plm_dfm_deframe1_dwbuf_N_35533_i), + .LO(plm_dfm_deframe1_dwbuf_un1_reg_cnt_1_axb_1_1550) + ); + defparam plm_dfm_deframe1_dwbuf_un1_reg_cnt_1_axb_2.INIT = 8'hA6; + LUT3_L plm_dfm_deframe1_dwbuf_un1_reg_cnt_1_axb_2 ( + .I0(plm_dfm_deframe1_dwbuf_reg_cnt[2]), + .I1(plm_dfm_deframe1_N_35550_i), + .I2(plm_dfm_deframe1_dwbuf_N_35533_i), + .LO(plm_dfm_deframe1_dwbuf_un1_reg_cnt_1_axb_2_1551) + ); + defparam plm_dfm_deframe1_dwbuf_un1_reg_cnt_1_axb_3.INIT = 8'hA6; + LUT3_L plm_dfm_deframe1_dwbuf_un1_reg_cnt_1_axb_3 ( + .I0(plm_dfm_deframe1_dwbuf_reg_cnt[3]), + .I1(plm_dfm_deframe1_N_35550_i), + .I2(plm_dfm_deframe1_dwbuf_N_35533_i), + .LO(plm_dfm_deframe1_dwbuf_un1_reg_cnt_1_axb_3_1552) + ); + defparam plm_dfm_deframe1_qwfsm_prerelease_reg_by1_preh_sdpstp_6_i_0_o4_0_.INIT = 4'h1; + LUT2 plm_dfm_deframe1_qwfsm_prerelease_reg_by1_preh_sdpstp_6_i_0_o4_0_ ( + .I0(plm_dfm_deframe1_qwfsm_reg_state_0__116), + .I1(plm_dfm_deframe1_qwfsm_reg_state_1__115), + .O(plm_dfm_deframe1_N_35527_i) + ); + defparam plm_dfm_deframe1_qwfsm_prerelease_reg_by1_preh_out_6_i_0_o2_8_.INIT = 4'h1; + LUT2 plm_dfm_deframe1_qwfsm_prerelease_reg_by1_preh_out_6_i_0_o2_8_ ( + .I0(plm_dfm_deframe1_qwfsm_reg_state[4]), + .I1(plm_dfm_deframe1_qwfsm_reg_state[5]), + .O(plm_dfm_deframe1_N_35528_i) + ); + defparam plm_dfm_deframe1_qwfsm_prerelease_reg_by1_preh_sdpstp_6_i_0_o4_0_0_.INIT = 4'h1; + LUT2 plm_dfm_deframe1_qwfsm_prerelease_reg_by1_preh_sdpstp_6_i_0_o4_0_0_ ( + .I0(plm_dfm_deframe1_dword_empty), + .I1(plm_dfm_deframe1_dword_sdpstp[1]), + .O(plm_dfm_deframe1_qwfsm_N_35544_i) + ); + defparam plm_dfm_deframe1_qwfsm_prerelease_reg_by1_preh_edbedg_8_0_0_o4_1_.INIT = 4'h1; + LUT2 plm_dfm_deframe1_qwfsm_prerelease_reg_by1_preh_edbedg_8_0_0_o4_1_ ( + .I0(plm_dfm_deframe1_qwfsm_reg_state[2]), + .I1(plm_dfm_deframe1_qwfsm_reg_state[3]), + .O(plm_dfm_deframe1_qwfsm_N_35555_i) + ); + defparam plm_dfm_deframe1_qwfsm_nxt_state_i_i_0_a2_1_0_.INIT = 4'h1; + LUT2 plm_dfm_deframe1_qwfsm_nxt_state_i_i_0_a2_1_0_ ( + .I0(plm_dfm_deframe1_qwfsm_reg_state[3]), + .I1(plm_dfm_deframe1_qwfsm_reg_state[5]), + .O(plm_dfm_deframe1_qwfsm_N_35590_1) + ); + defparam plm_dfm_deframe1_qwfsm_nxt_state_i_i_0_a2_1_1_.INIT = 4'h1; + LUT2 plm_dfm_deframe1_qwfsm_nxt_state_i_i_0_a2_1_1_ ( + .I0(plm_dfm_deframe1_qwfsm_reg_state[2]), + .I1(plm_dfm_deframe1_qwfsm_reg_state[4]), + .O(plm_dfm_deframe1_qwfsm_N_35588_1) + ); + defparam plm_dfm_deframe1_qwfsm_prerelease_reg_by1_preh_sdpstp_6_iv_i_0_a4_1_.INIT = 4'h8; + LUT2 plm_dfm_deframe1_qwfsm_prerelease_reg_by1_preh_sdpstp_6_iv_i_0_a4_1_ ( + .I0(plm_dfm_deframe1_qwfsm_N_35544_i), + .I1(plm_dfm_deframe1_dword_sdpstp[0]), + .O(reg_by1_preh_sdpstp_6_iv_i_0_a4[1]) + ); + defparam plm_dfm_deframe1_qwfsm_nxt_state_6_sqmuxa_0_a2_0_a2_0.INIT = 8'h10; + LUT3 plm_dfm_deframe1_qwfsm_nxt_state_6_sqmuxa_0_a2_0_a2_0 ( + .I0(plm_dfm_deframe1_dword_empty), + .I1(plm_dfm_deframe1_dword_sdpstp[0]), + .I2(plm_dfm_deframe1_dword_sdpstp[1]), + .O(plm_dfm_deframe1_qwfsm_nxt_state_6_sqmuxa_0_a2_0_a2_0_1554) + ); + defparam plm_dfm_deframe1_qwfsm_prerelease_reg_by1_preh_out_6_i_0_o4_8_.INIT = 16'h5445; + LUT4 plm_dfm_deframe1_qwfsm_prerelease_reg_by1_preh_out_6_i_0_o4_8_ ( + .I0(plm_dfm_deframe1_N_35527_i), + .I1(plm_dfm_deframe1_dword_empty), + .I2(plm_dfm_deframe1_dword_sdpstp[0]), + .I3(plm_dfm_deframe1_dword_sdpstp[1]), + .O(plm_dfm_deframe1_qwfsm_N_35531_i) + ); + defparam plm_dfm_deframe1_qwfsm_nxt_state_i_i_0_o4_1_.INIT = 16'h1400; + LUT4 plm_dfm_deframe1_qwfsm_nxt_state_i_i_0_o4_1_ ( + .I0(plm_dfm_deframe1_dword_empty), + .I1(plm_dfm_deframe1_dword_sdpstp[0]), + .I2(plm_dfm_deframe1_dword_sdpstp[1]), + .I3(plm_dfm_deframe1_qwfsm_reg_state_0__116), + .O(plm_dfm_deframe1_qwfsm_nxt_state_i_i_0_o4[1]) + ); + defparam plm_dfm_deframe1_qwfsm_nxt_state_i_i_0_o4_0_.INIT = 16'h1400; + LUT4 plm_dfm_deframe1_qwfsm_nxt_state_i_i_0_o4_0_ ( + .I0(plm_dfm_deframe1_dword_empty), + .I1(plm_dfm_deframe1_dword_sdpstp[0]), + .I2(plm_dfm_deframe1_dword_sdpstp[1]), + .I3(plm_dfm_deframe1_qwfsm_reg_state_1__115), + .O(plm_dfm_deframe1_qwfsm_nxt_state_i_i_0_o4[0]) + ); + defparam plm_dfm_deframe1_qwfsm_prerelease_reg_by1_preh_sdpstp_6_i_0_0_.INIT = 16'hC800; + LUT4 plm_dfm_deframe1_qwfsm_prerelease_reg_by1_preh_sdpstp_6_i_0_0_ ( + .I0(plm_dfm_deframe1_N_35527_i), + .I1(plm_dfm_deframe1_N_35528_i), + .I2(plm_dfm_deframe1_qwfsm_N_35544_i), + .I3(plm_dfm_deframe1_dword_sdpstp[0]), + .O(plm_dfm_deframe1_qwfsm_N_20680_i) + ); + defparam plm_dfm_deframe1_qwfsm_dword_pop_0_i_o2_0_o2_0.INIT = 8'h23; + LUT3_L plm_dfm_deframe1_qwfsm_dword_pop_0_i_o2_0_o2_0 ( + .I0(plm_dfm_deframe1_N_35527_i), + .I1(plm_dfm_deframe1_N_35534_i), + .I2(plm_dfm_deframe1_dword_empty), + .LO(plm_dfm_deframe1_qwfsm_dword_pop_0_i_o2_0_o2_0_1553) + ); + defparam plm_dfm_deframe1_qwfsm_prerelease_reg_by1_preh_out_6_i_0_o2_9_.INIT = 4'h2; + LUT2_L plm_dfm_deframe1_qwfsm_prerelease_reg_by1_preh_out_6_i_0_o2_9_ ( + .I0(plm_dfm_deframe1_N_35528_i), + .I1(plm_dfm_deframe1_qwfsm_N_35531_i), + .LO(plm_dfm_deframe1_qwfsm_N_35536_i) + ); + defparam plm_dfm_deframe1_qwfsm_prerelease_reg_by1_preh_sdpstp_6_iv_i_0_1_.INIT = 16'h0C04; + LUT4 plm_dfm_deframe1_qwfsm_prerelease_reg_by1_preh_sdpstp_6_iv_i_0_1_ ( + .I0(plm_dfm_deframe1_N_35527_i), + .I1(plm_dfm_deframe1_N_35528_i), + .I2(reg_by1_preh_sdpstp_6_iv_i_0_a4[1]), + .I3(plm_dfm_deframe1_dword_sdpstp[1]), + .O(plm_dfm_deframe1_qwfsm_N_20721_i) + ); + defparam plm_dfm_deframe1_qwfsm_prerelease_reg_by1_preh_edbedg_8_i_0_0_.INIT = 16'h7757; + LUT4 plm_dfm_deframe1_qwfsm_prerelease_reg_by1_preh_edbedg_8_i_0_0_ ( + .I0(plm_dfm_deframe1_N_35528_i), + .I1(plm_dfm_deframe1_qwfsm_N_35531_i), + .I2(plm_dfm_deframe1_qwfsm_N_35555_i), + .I3(plm_dfm_deframe1_dword_edbedg[0]), + .O(plm_dfm_deframe1_qwfsm_N_20686_i) + ); + defparam plm_dfm_deframe1_qwfsm_prerelease_reg_by1_preh_out_6_iv_i_0_31_.INIT = 8'hA8; + LUT3 plm_dfm_deframe1_qwfsm_prerelease_reg_by1_preh_out_6_iv_i_0_31_ ( + .I0(plm_dfm_deframe1_N_35528_i), + .I1(plm_dfm_deframe1_qwfsm_N_35531_i), + .I2(plm_dfm_deframe1_dword_out[31]), + .O(plm_dfm_deframe1_qwfsm_N_20689_i) + ); + defparam plm_dfm_deframe1_qwfsm_prerelease_reg_by1_preh_out_6_iv_i_0_30_.INIT = 8'hA8; + LUT3 plm_dfm_deframe1_qwfsm_prerelease_reg_by1_preh_out_6_iv_i_0_30_ ( + .I0(plm_dfm_deframe1_N_35528_i), + .I1(plm_dfm_deframe1_qwfsm_N_35531_i), + .I2(plm_dfm_deframe1_dword_out[30]), + .O(plm_dfm_deframe1_qwfsm_N_20691_i) + ); + defparam plm_dfm_deframe1_qwfsm_prerelease_reg_by1_preh_out_6_iv_i_0_29_.INIT = 8'hA8; + LUT3 plm_dfm_deframe1_qwfsm_prerelease_reg_by1_preh_out_6_iv_i_0_29_ ( + .I0(plm_dfm_deframe1_N_35528_i), + .I1(plm_dfm_deframe1_qwfsm_N_35531_i), + .I2(plm_dfm_deframe1_dword_out[29]), + .O(plm_dfm_deframe1_qwfsm_N_20693_i) + ); + defparam plm_dfm_deframe1_qwfsm_prerelease_reg_by1_preh_out_6_iv_i_0_28_.INIT = 8'hA8; + LUT3 plm_dfm_deframe1_qwfsm_prerelease_reg_by1_preh_out_6_iv_i_0_28_ ( + .I0(plm_dfm_deframe1_N_35528_i), + .I1(plm_dfm_deframe1_qwfsm_N_35531_i), + .I2(plm_dfm_deframe1_dword_out[28]), + .O(plm_dfm_deframe1_qwfsm_N_20695_i) + ); + defparam plm_dfm_deframe1_qwfsm_prerelease_reg_by1_preh_out_6_iv_i_0_27_.INIT = 8'hA8; + LUT3 plm_dfm_deframe1_qwfsm_prerelease_reg_by1_preh_out_6_iv_i_0_27_ ( + .I0(plm_dfm_deframe1_N_35528_i), + .I1(plm_dfm_deframe1_qwfsm_N_35531_i), + .I2(plm_dfm_deframe1_dword_out[27]), + .O(plm_dfm_deframe1_qwfsm_N_20697_i) + ); + defparam plm_dfm_deframe1_qwfsm_prerelease_reg_by1_preh_out_6_iv_i_0_26_.INIT = 8'hA8; + LUT3 plm_dfm_deframe1_qwfsm_prerelease_reg_by1_preh_out_6_iv_i_0_26_ ( + .I0(plm_dfm_deframe1_N_35528_i), + .I1(plm_dfm_deframe1_qwfsm_N_35531_i), + .I2(plm_dfm_deframe1_dword_out[26]), + .O(plm_dfm_deframe1_qwfsm_N_20699_i) + ); + defparam plm_dfm_deframe1_qwfsm_prerelease_reg_by1_preh_out_6_iv_i_0_25_.INIT = 8'hA8; + LUT3 plm_dfm_deframe1_qwfsm_prerelease_reg_by1_preh_out_6_iv_i_0_25_ ( + .I0(plm_dfm_deframe1_N_35528_i), + .I1(plm_dfm_deframe1_qwfsm_N_35531_i), + .I2(plm_dfm_deframe1_dword_out[25]), + .O(plm_dfm_deframe1_qwfsm_N_20701_i) + ); + defparam plm_dfm_deframe1_qwfsm_prerelease_reg_by1_preh_out_6_iv_i_0_24_.INIT = 8'hA8; + LUT3 plm_dfm_deframe1_qwfsm_prerelease_reg_by1_preh_out_6_iv_i_0_24_ ( + .I0(plm_dfm_deframe1_N_35528_i), + .I1(plm_dfm_deframe1_qwfsm_N_35531_i), + .I2(plm_dfm_deframe1_dword_out[24]), + .O(plm_dfm_deframe1_qwfsm_N_20703_i) + ); + defparam plm_dfm_deframe1_qwfsm_dword_pop_0_i_o2_0_o2.INIT = 16'hAB00; + LUT4 plm_dfm_deframe1_qwfsm_dword_pop_0_i_o2_0_o2 ( + .I0(plm_dfm_deframe1_N_35528_i), + .I1(plm_dfm_deframe1_N_35545_i), + .I2(plm_dfm_deframe1_dword_empty), + .I3(plm_dfm_deframe1_qwfsm_dword_pop_0_i_o2_0_o2_0_1553), + .O(plm_dfm_deframe1_N_35550_i) + ); + defparam plm_dfm_deframe1_qwfsm_prerelease_N_87736_i.INIT = 8'h75; + LUT3 plm_dfm_deframe1_qwfsm_prerelease_N_87736_i ( + .I0(plm_dfm_deframe1_N_35528_i), + .I1(plm_dfm_deframe1_qwfsm_N_35531_i), + .I2(plm_dfm_deframe1_dword_out[0]), + .O(plm_dfm_deframe1_qwfsm_N_87736_i) + ); + defparam plm_dfm_deframe1_qwfsm_prerelease_N_87737_i.INIT = 8'h75; + LUT3 plm_dfm_deframe1_qwfsm_prerelease_N_87737_i ( + .I0(plm_dfm_deframe1_N_35528_i), + .I1(plm_dfm_deframe1_qwfsm_N_35531_i), + .I2(plm_dfm_deframe1_dword_out[1]), + .O(plm_dfm_deframe1_qwfsm_N_87737_i) + ); + defparam plm_dfm_deframe1_qwfsm_prerelease_N_87738_i.INIT = 8'h75; + LUT3 plm_dfm_deframe1_qwfsm_prerelease_N_87738_i ( + .I0(plm_dfm_deframe1_N_35528_i), + .I1(plm_dfm_deframe1_qwfsm_N_35531_i), + .I2(plm_dfm_deframe1_dword_out[2]), + .O(plm_dfm_deframe1_qwfsm_N_87738_i) + ); + defparam plm_dfm_deframe1_qwfsm_prerelease_N_87739_i.INIT = 8'h75; + LUT3 plm_dfm_deframe1_qwfsm_prerelease_N_87739_i ( + .I0(plm_dfm_deframe1_N_35528_i), + .I1(plm_dfm_deframe1_qwfsm_N_35531_i), + .I2(plm_dfm_deframe1_dword_out[3]), + .O(plm_dfm_deframe1_qwfsm_N_87739_i) + ); + defparam plm_dfm_deframe1_qwfsm_prerelease_N_87740_i.INIT = 8'h75; + LUT3 plm_dfm_deframe1_qwfsm_prerelease_N_87740_i ( + .I0(plm_dfm_deframe1_N_35528_i), + .I1(plm_dfm_deframe1_qwfsm_N_35531_i), + .I2(plm_dfm_deframe1_dword_out[4]), + .O(plm_dfm_deframe1_qwfsm_N_87740_i) + ); + defparam plm_dfm_deframe1_qwfsm_prerelease_N_87741_i.INIT = 8'h75; + LUT3 plm_dfm_deframe1_qwfsm_prerelease_N_87741_i ( + .I0(plm_dfm_deframe1_N_35528_i), + .I1(plm_dfm_deframe1_qwfsm_N_35531_i), + .I2(plm_dfm_deframe1_dword_out[5]), + .O(plm_dfm_deframe1_qwfsm_N_87741_i) + ); + defparam plm_dfm_deframe1_qwfsm_prerelease_N_87742_i.INIT = 8'h75; + LUT3 plm_dfm_deframe1_qwfsm_prerelease_N_87742_i ( + .I0(plm_dfm_deframe1_N_35528_i), + .I1(plm_dfm_deframe1_qwfsm_N_35531_i), + .I2(plm_dfm_deframe1_dword_out[6]), + .O(plm_dfm_deframe1_qwfsm_N_87742_i) + ); + defparam plm_dfm_deframe1_qwfsm_prerelease_N_87743_i.INIT = 8'h75; + LUT3 plm_dfm_deframe1_qwfsm_prerelease_N_87743_i ( + .I0(plm_dfm_deframe1_N_35528_i), + .I1(plm_dfm_deframe1_qwfsm_N_35531_i), + .I2(plm_dfm_deframe1_dword_out[7]), + .O(plm_dfm_deframe1_qwfsm_N_87743_i) + ); + defparam plm_dfm_deframe1_qwfsm_prerelease_N_87769_i.INIT = 16'hAB03; + LUT4 plm_dfm_deframe1_qwfsm_prerelease_N_87769_i ( + .I0(plm_dfm_deframe1_qwfsm_N_35536_i), + .I1(plm_dfm_deframe1_qwfsm_N_35555_i), + .I2(plm_dfm_deframe1_dword_edbedg[0]), + .I3(plm_dfm_deframe1_dword_edbedg[1]), + .O(plm_dfm_deframe1_qwfsm_N_87769_i) + ); + defparam plm_dfm_deframe1_qwfsm_nxt_state_6_sqmuxa_1_0_a2_0_a2.INIT = 8'h80; + LUT3_L plm_dfm_deframe1_qwfsm_nxt_state_6_sqmuxa_1_0_a2_0_a2 ( + .I0(m10_3_0_0_a3_117), + .I1(plm_dfm_deframe1_qwfsm_nxt_state_6_sqmuxa_0_a2_0_a2_0_1554), + .I2(plm_dfm_deframe1_qwfsm_reg_state_0__116), + .LO(plm_dfm_deframe1_qwfsm_nxt_state_6_sqmuxa_1) + ); + defparam plm_dfm_deframe1_qwfsm_nxt_state_6_sqmuxa_0_a2_0_a2.INIT = 8'h80; + LUT3_L plm_dfm_deframe1_qwfsm_nxt_state_6_sqmuxa_0_a2_0_a2 ( + .I0(m10_3_0_0_a3_117), + .I1(plm_dfm_deframe1_qwfsm_nxt_state_6_sqmuxa_0_a2_0_a2_0_1554), + .I2(plm_dfm_deframe1_qwfsm_reg_state_1__115), + .LO(plm_dfm_deframe1_qwfsm_nxt_state_6_sqmuxa) + ); + defparam plm_dfm_deframe1_qwfsm_nxt_state_i_i_0_1_.INIT = 16'h7775; + LUT4_L plm_dfm_deframe1_qwfsm_nxt_state_i_i_0_1_ ( + .I0(plm_dfm_deframe1_qwfsm_N_35588_1), + .I1(m10_3_0_0_a3_117), + .I2(plm_dfm_deframe1_qwfsm_nxt_state_i_i_0_o4[1]), + .I3(plm_dfm_deframe1_qwfsm_reg_state_6__120), + .LO(plm_dfm_deframe1_qwfsm_N_20723_i) + ); + defparam plm_dfm_deframe1_qwfsm_nxt_state_i_i_0_0_.INIT = 16'h7775; + LUT4_L plm_dfm_deframe1_qwfsm_nxt_state_i_i_0_0_ ( + .I0(plm_dfm_deframe1_qwfsm_N_35590_1), + .I1(m10_3_0_0_a3_117), + .I2(plm_dfm_deframe1_qwfsm_nxt_state_i_i_0_o4[0]), + .I3(plm_dfm_deframe1_qwfsm_reg_state_7__118), + .LO(plm_dfm_deframe1_qwfsm_N_20725_i) + ); + defparam plm_dfm_deframe1_qwfsm_prerelease_reg_by1_preh_out_6_i_0_9_.INIT = 8'h20; + LUT3 plm_dfm_deframe1_qwfsm_prerelease_reg_by1_preh_out_6_i_0_9_ ( + .I0(plm_dfm_deframe1_dword_out[9]), + .I1(plm_dfm_deframe1_qwfsm_N_35531_i), + .I2(plm_dfm_deframe1_N_35528_i), + .O(plm_dfm_deframe1_qwfsm_N_20650_i) + ); + defparam plm_dfm_deframe1_qwfsm_prerelease_reg_by1_preh_out_6_i_0_10_.INIT = 8'h20; + LUT3 plm_dfm_deframe1_qwfsm_prerelease_reg_by1_preh_out_6_i_0_10_ ( + .I0(plm_dfm_deframe1_dword_out[10]), + .I1(plm_dfm_deframe1_qwfsm_N_35531_i), + .I2(plm_dfm_deframe1_N_35528_i), + .O(plm_dfm_deframe1_qwfsm_N_20652_i) + ); + defparam plm_dfm_deframe1_qwfsm_prerelease_reg_by1_preh_out_6_i_0_11_.INIT = 8'h20; + LUT3 plm_dfm_deframe1_qwfsm_prerelease_reg_by1_preh_out_6_i_0_11_ ( + .I0(plm_dfm_deframe1_dword_out[11]), + .I1(plm_dfm_deframe1_qwfsm_N_35531_i), + .I2(plm_dfm_deframe1_N_35528_i), + .O(plm_dfm_deframe1_qwfsm_N_20654_i) + ); + defparam plm_dfm_deframe1_qwfsm_prerelease_reg_by1_preh_out_6_i_0_12_.INIT = 8'h20; + LUT3 plm_dfm_deframe1_qwfsm_prerelease_reg_by1_preh_out_6_i_0_12_ ( + .I0(plm_dfm_deframe1_dword_out[12]), + .I1(plm_dfm_deframe1_qwfsm_N_35531_i), + .I2(plm_dfm_deframe1_N_35528_i), + .O(plm_dfm_deframe1_qwfsm_N_20656_i) + ); + defparam plm_dfm_deframe1_qwfsm_prerelease_reg_by1_preh_out_6_i_0_13_.INIT = 8'h20; + LUT3 plm_dfm_deframe1_qwfsm_prerelease_reg_by1_preh_out_6_i_0_13_ ( + .I0(plm_dfm_deframe1_dword_out[13]), + .I1(plm_dfm_deframe1_qwfsm_N_35531_i), + .I2(plm_dfm_deframe1_N_35528_i), + .O(plm_dfm_deframe1_qwfsm_N_20658_i) + ); + defparam plm_dfm_deframe1_qwfsm_prerelease_reg_by1_preh_out_6_i_0_14_.INIT = 8'h20; + LUT3 plm_dfm_deframe1_qwfsm_prerelease_reg_by1_preh_out_6_i_0_14_ ( + .I0(plm_dfm_deframe1_dword_out[14]), + .I1(plm_dfm_deframe1_qwfsm_N_35531_i), + .I2(plm_dfm_deframe1_N_35528_i), + .O(plm_dfm_deframe1_qwfsm_N_20660_i) + ); + defparam plm_dfm_deframe1_qwfsm_prerelease_reg_by1_preh_out_6_i_0_15_.INIT = 8'h20; + LUT3 plm_dfm_deframe1_qwfsm_prerelease_reg_by1_preh_out_6_i_0_15_ ( + .I0(plm_dfm_deframe1_dword_out[15]), + .I1(plm_dfm_deframe1_qwfsm_N_35531_i), + .I2(plm_dfm_deframe1_N_35528_i), + .O(plm_dfm_deframe1_qwfsm_N_20662_i) + ); + defparam plm_dfm_deframe1_qwfsm_prerelease_reg_by1_preh_out_6_i_0_16_.INIT = 8'h20; + LUT3 plm_dfm_deframe1_qwfsm_prerelease_reg_by1_preh_out_6_i_0_16_ ( + .I0(plm_dfm_deframe1_dword_out[16]), + .I1(plm_dfm_deframe1_qwfsm_N_35531_i), + .I2(plm_dfm_deframe1_N_35528_i), + .O(plm_dfm_deframe1_qwfsm_N_20664_i) + ); + defparam plm_dfm_deframe1_qwfsm_prerelease_reg_by1_preh_out_6_i_0_17_.INIT = 8'h20; + LUT3 plm_dfm_deframe1_qwfsm_prerelease_reg_by1_preh_out_6_i_0_17_ ( + .I0(plm_dfm_deframe1_dword_out[17]), + .I1(plm_dfm_deframe1_qwfsm_N_35531_i), + .I2(plm_dfm_deframe1_N_35528_i), + .O(plm_dfm_deframe1_qwfsm_N_20666_i) + ); + defparam plm_dfm_deframe1_qwfsm_prerelease_reg_by1_preh_out_6_i_0_18_.INIT = 8'h20; + LUT3 plm_dfm_deframe1_qwfsm_prerelease_reg_by1_preh_out_6_i_0_18_ ( + .I0(plm_dfm_deframe1_dword_out[18]), + .I1(plm_dfm_deframe1_qwfsm_N_35531_i), + .I2(plm_dfm_deframe1_N_35528_i), + .O(plm_dfm_deframe1_qwfsm_N_20668_i) + ); + defparam plm_dfm_deframe1_qwfsm_prerelease_reg_by1_preh_out_6_i_0_19_.INIT = 8'h20; + LUT3 plm_dfm_deframe1_qwfsm_prerelease_reg_by1_preh_out_6_i_0_19_ ( + .I0(plm_dfm_deframe1_dword_out[19]), + .I1(plm_dfm_deframe1_qwfsm_N_35531_i), + .I2(plm_dfm_deframe1_N_35528_i), + .O(plm_dfm_deframe1_qwfsm_N_20670_i) + ); + defparam plm_dfm_deframe1_qwfsm_prerelease_reg_by1_preh_out_6_i_0_20_.INIT = 8'h20; + LUT3 plm_dfm_deframe1_qwfsm_prerelease_reg_by1_preh_out_6_i_0_20_ ( + .I0(plm_dfm_deframe1_dword_out[20]), + .I1(plm_dfm_deframe1_qwfsm_N_35531_i), + .I2(plm_dfm_deframe1_N_35528_i), + .O(plm_dfm_deframe1_qwfsm_N_20672_i) + ); + defparam plm_dfm_deframe1_qwfsm_prerelease_reg_by1_preh_out_6_i_0_21_.INIT = 8'h20; + LUT3 plm_dfm_deframe1_qwfsm_prerelease_reg_by1_preh_out_6_i_0_21_ ( + .I0(plm_dfm_deframe1_dword_out[21]), + .I1(plm_dfm_deframe1_qwfsm_N_35531_i), + .I2(plm_dfm_deframe1_N_35528_i), + .O(plm_dfm_deframe1_qwfsm_N_20674_i) + ); + defparam plm_dfm_deframe1_qwfsm_prerelease_reg_by1_preh_out_6_i_0_22_.INIT = 8'h20; + LUT3 plm_dfm_deframe1_qwfsm_prerelease_reg_by1_preh_out_6_i_0_22_ ( + .I0(plm_dfm_deframe1_dword_out[22]), + .I1(plm_dfm_deframe1_qwfsm_N_35531_i), + .I2(plm_dfm_deframe1_N_35528_i), + .O(plm_dfm_deframe1_qwfsm_N_20676_i) + ); + defparam plm_dfm_deframe1_qwfsm_prerelease_reg_by1_preh_out_6_i_0_23_.INIT = 8'h20; + LUT3 plm_dfm_deframe1_qwfsm_prerelease_reg_by1_preh_out_6_i_0_23_ ( + .I0(plm_dfm_deframe1_dword_out[23]), + .I1(plm_dfm_deframe1_qwfsm_N_35531_i), + .I2(plm_dfm_deframe1_N_35528_i), + .O(plm_dfm_deframe1_qwfsm_N_20678_i) + ); + defparam plm_dfm_deframe1_qwfsm_prerelease_reg_by1_preh_out_6_i_0_8_.INIT = 8'h20; + LUT3 plm_dfm_deframe1_qwfsm_prerelease_reg_by1_preh_out_6_i_0_8_ ( + .I0(plm_dfm_deframe1_dword_out[8]), + .I1(plm_dfm_deframe1_qwfsm_N_35531_i), + .I2(plm_dfm_deframe1_N_35528_i), + .O(plm_dfm_deframe1_qwfsm_N_20648_i) + ); + FDC plm_dfm_deframe1_qwfsm_reg_phi1 ( + .C(mgt_clk), + .D(plm_dfm_deframe1_qwfsm_reg_phi0_1555), + .Q(plm_dfm_deframe1_reg_phi1), + .CLR(plm_rst) + ); + FDC plm_dfm_deframe1_qwfsm_reg_phi0 ( + .C(mgt_clk), + .D(plm_phy_cke_0_712), + .Q(plm_dfm_deframe1_qwfsm_reg_phi0_1555), + .CLR(plm_rst) + ); + FDCE plm_dfm_deframe1_qwfsm_reg_state_7_ ( + .CE(plm_dfm_deframe1_N_35534_i_i), + .C(mgt_clk), + .D(N_87770_i_121), + .Q(plm_dfm_deframe1_qwfsm_reg_state_7__118), + .CLR(plm_rst) + ); + FDCE plm_dfm_deframe1_qwfsm_reg_state_6_ ( + .CE(plm_dfm_deframe1_N_35534_i_i), + .C(mgt_clk), + .D(N_87771_i_119), + .Q(plm_dfm_deframe1_qwfsm_reg_state_6__120), + .CLR(plm_rst) + ); + FDCE plm_dfm_deframe1_qwfsm_reg_state_5_ ( + .CE(plm_dfm_deframe1_N_35534_i_i), + .C(mgt_clk), + .D(plm_dfm_deframe1_qwfsm_nxt_state[5]), + .Q(plm_dfm_deframe1_qwfsm_reg_state[5]), + .CLR(plm_rst) + ); + FDCE plm_dfm_deframe1_qwfsm_reg_state_4_ ( + .CE(plm_dfm_deframe1_N_35534_i_i), + .C(mgt_clk), + .D(plm_dfm_deframe1_qwfsm_nxt_state[4]), + .Q(plm_dfm_deframe1_qwfsm_reg_state[4]), + .CLR(plm_rst) + ); + FDCE plm_dfm_deframe1_qwfsm_reg_state_3_ ( + .CE(plm_dfm_deframe1_N_35534_i_i), + .C(mgt_clk), + .D(plm_dfm_deframe1_qwfsm_nxt_state_6_sqmuxa_1), + .Q(plm_dfm_deframe1_qwfsm_reg_state[3]), + .CLR(plm_rst) + ); + FDCE plm_dfm_deframe1_qwfsm_reg_state_2_ ( + .CE(plm_dfm_deframe1_N_35534_i_i), + .C(mgt_clk), + .D(plm_dfm_deframe1_qwfsm_nxt_state_6_sqmuxa), + .Q(plm_dfm_deframe1_qwfsm_reg_state[2]), + .CLR(plm_rst) + ); + FDCE plm_dfm_deframe1_qwfsm_reg_state_1_ ( + .CE(plm_dfm_deframe1_N_35534_i_i), + .C(mgt_clk), + .D(plm_dfm_deframe1_qwfsm_N_20723_i), + .Q(plm_dfm_deframe1_qwfsm_reg_state_1__115), + .CLR(plm_rst) + ); + FDPE plm_dfm_deframe1_qwfsm_reg_state_0_ ( + .PRE(plm_rst), + .CE(plm_dfm_deframe1_N_35534_i_i), + .C(mgt_clk), + .D(plm_dfm_deframe1_qwfsm_N_20725_i), + .Q(plm_dfm_deframe1_qwfsm_reg_state_0__116) + ); + FDCE plm_dfm_deframe1_qwfsm_reg_by1_prel_sdpstp_1_ ( + .CE(plm_dfm_deframe1_reg_phi1), + .C(mgt_clk), + .D(plm_dfm_deframe1_qwfsm_N_20721_i), + .Q(plm_dfm_by1_prel_sdpstp[1]), + .CLR(plm_rst) + ); + FDCE plm_dfm_deframe1_qwfsm_reg_by1_prel_sdpstp_0_ ( + .CE(plm_dfm_deframe1_reg_phi1), + .C(mgt_clk), + .D(plm_dfm_deframe1_qwfsm_N_20680_i), + .Q(plm_dfm_by1_prel_sdpstp[0]), + .CLR(plm_rst) + ); + FDPE plm_dfm_deframe1_qwfsm_reg_by1_preh_sdpstp_1_ ( + .PRE(plm_rst), + .CE(plm_phy_cke_0_712), + .C(mgt_clk), + .D(plm_dfm_deframe1_qwfsm_N_20721_i), + .Q(plm_dfm_by1_preh_sdpstp[1]) + ); + FDCE plm_dfm_deframe1_qwfsm_reg_by1_preh_sdpstp_0_ ( + .CE(plm_phy_cke_0_712), + .C(mgt_clk), + .D(plm_dfm_deframe1_qwfsm_N_20680_i), + .Q(plm_dfm_by1_preh_sdpstp[0]), + .CLR(plm_rst) + ); + FDPE plm_dfm_deframe1_qwfsm_reg_by1_preh_out_31_ ( + .PRE(plm_rst), + .CE(plm_phy_cke_0_712), + .C(mgt_clk), + .D(plm_dfm_deframe1_qwfsm_N_20689_i), + .Q(plm_dfm_by1_preh_out[31]) + ); + FDPE plm_dfm_deframe1_qwfsm_reg_by1_preh_out_30_ ( + .PRE(plm_rst), + .CE(plm_phy_cke_0_712), + .C(mgt_clk), + .D(plm_dfm_deframe1_qwfsm_N_20691_i), + .Q(plm_dfm_by1_preh_out[30]) + ); + FDPE plm_dfm_deframe1_qwfsm_reg_by1_preh_out_29_ ( + .PRE(plm_rst), + .CE(plm_phy_cke_0_712), + .C(mgt_clk), + .D(plm_dfm_deframe1_qwfsm_N_20693_i), + .Q(plm_dfm_by1_preh_out[29]) + ); + FDPE plm_dfm_deframe1_qwfsm_reg_by1_preh_out_28_ ( + .PRE(plm_rst), + .CE(plm_phy_cke_0_712), + .C(mgt_clk), + .D(plm_dfm_deframe1_qwfsm_N_20695_i), + .Q(plm_dfm_by1_preh_out[28]) + ); + FDPE plm_dfm_deframe1_qwfsm_reg_by1_preh_out_27_ ( + .PRE(plm_rst), + .CE(plm_phy_cke_0_712), + .C(mgt_clk), + .D(plm_dfm_deframe1_qwfsm_N_20697_i), + .Q(plm_dfm_by1_preh_out[27]) + ); + FDPE plm_dfm_deframe1_qwfsm_reg_by1_preh_out_26_ ( + .PRE(plm_rst), + .CE(plm_phy_cke_0_712), + .C(mgt_clk), + .D(plm_dfm_deframe1_qwfsm_N_20699_i), + .Q(plm_dfm_by1_preh_out[26]) + ); + FDPE plm_dfm_deframe1_qwfsm_reg_by1_preh_out_25_ ( + .PRE(plm_rst), + .CE(plm_phy_cke_0_712), + .C(mgt_clk), + .D(plm_dfm_deframe1_qwfsm_N_20701_i), + .Q(plm_dfm_by1_preh_out[25]) + ); + FDPE plm_dfm_deframe1_qwfsm_reg_by1_preh_out_24_ ( + .PRE(plm_rst), + .CE(plm_phy_cke_0_712), + .C(mgt_clk), + .D(plm_dfm_deframe1_qwfsm_N_20703_i), + .Q(plm_dfm_by1_preh_out[24]) + ); + FDCE plm_dfm_deframe1_qwfsm_reg_by1_preh_out_23_ ( + .CE(plm_phy_cke_0_712), + .C(mgt_clk), + .D(plm_dfm_deframe1_qwfsm_N_20678_i), + .Q(plm_dfm_by1_preh_out[23]), + .CLR(plm_rst) + ); + FDCE plm_dfm_deframe1_qwfsm_reg_by1_preh_out_22_ ( + .CE(plm_phy_cke_0_712), + .C(mgt_clk), + .D(plm_dfm_deframe1_qwfsm_N_20676_i), + .Q(plm_dfm_by1_preh_out[22]), + .CLR(plm_rst) + ); + FDCE plm_dfm_deframe1_qwfsm_reg_by1_preh_out_21_ ( + .CE(plm_phy_cke_0_712), + .C(mgt_clk), + .D(plm_dfm_deframe1_qwfsm_N_20674_i), + .Q(plm_dfm_by1_preh_out[21]), + .CLR(plm_rst) + ); + FDCE plm_dfm_deframe1_qwfsm_reg_by1_preh_out_20_ ( + .CE(plm_phy_cke_0_712), + .C(mgt_clk), + .D(plm_dfm_deframe1_qwfsm_N_20672_i), + .Q(plm_dfm_by1_preh_out[20]), + .CLR(plm_rst) + ); + FDCE plm_dfm_deframe1_qwfsm_reg_by1_preh_out_19_ ( + .CE(plm_phy_cke_0_712), + .C(mgt_clk), + .D(plm_dfm_deframe1_qwfsm_N_20670_i), + .Q(plm_dfm_by1_preh_out[19]), + .CLR(plm_rst) + ); + FDCE plm_dfm_deframe1_qwfsm_reg_by1_preh_out_18_ ( + .CE(plm_phy_cke_0_712), + .C(mgt_clk), + .D(plm_dfm_deframe1_qwfsm_N_20668_i), + .Q(plm_dfm_by1_preh_out[18]), + .CLR(plm_rst) + ); + FDCE plm_dfm_deframe1_qwfsm_reg_by1_preh_out_17_ ( + .CE(plm_phy_cke_0_712), + .C(mgt_clk), + .D(plm_dfm_deframe1_qwfsm_N_20666_i), + .Q(plm_dfm_by1_preh_out[17]), + .CLR(plm_rst) + ); + FDCE plm_dfm_deframe1_qwfsm_reg_by1_preh_out_16_ ( + .CE(plm_phy_cke_0_712), + .C(mgt_clk), + .D(plm_dfm_deframe1_qwfsm_N_20664_i), + .Q(plm_dfm_by1_preh_out[16]), + .CLR(plm_rst) + ); + FDCE plm_dfm_deframe1_qwfsm_reg_by1_preh_out_15_ ( + .CE(plm_phy_cke_0_712), + .C(mgt_clk), + .D(plm_dfm_deframe1_qwfsm_N_20662_i), + .Q(plm_dfm_by1_preh_out[15]), + .CLR(plm_rst) + ); + FDCE plm_dfm_deframe1_qwfsm_reg_by1_preh_out_14_ ( + .CE(plm_phy_cke_0_712), + .C(mgt_clk), + .D(plm_dfm_deframe1_qwfsm_N_20660_i), + .Q(plm_dfm_by1_preh_out[14]), + .CLR(plm_rst) + ); + FDCE plm_dfm_deframe1_qwfsm_reg_by1_preh_out_13_ ( + .CE(plm_phy_cke_0_712), + .C(mgt_clk), + .D(plm_dfm_deframe1_qwfsm_N_20658_i), + .Q(plm_dfm_by1_preh_out[13]), + .CLR(plm_rst) + ); + FDCE plm_dfm_deframe1_qwfsm_reg_by1_preh_out_12_ ( + .CE(plm_phy_cke_0_712), + .C(mgt_clk), + .D(plm_dfm_deframe1_qwfsm_N_20656_i), + .Q(plm_dfm_by1_preh_out[12]), + .CLR(plm_rst) + ); + FDCE plm_dfm_deframe1_qwfsm_reg_by1_preh_out_11_ ( + .CE(plm_phy_cke_0_712), + .C(mgt_clk), + .D(plm_dfm_deframe1_qwfsm_N_20654_i), + .Q(plm_dfm_by1_preh_out[11]), + .CLR(plm_rst) + ); + FDCE plm_dfm_deframe1_qwfsm_reg_by1_preh_out_10_ ( + .CE(plm_phy_cke_0_712), + .C(mgt_clk), + .D(plm_dfm_deframe1_qwfsm_N_20652_i), + .Q(plm_dfm_by1_preh_out[10]), + .CLR(plm_rst) + ); + FDCE plm_dfm_deframe1_qwfsm_reg_by1_preh_out_9_ ( + .CE(plm_phy_cke_0_712), + .C(mgt_clk), + .D(plm_dfm_deframe1_qwfsm_N_20650_i), + .Q(plm_dfm_by1_preh_out[9]), + .CLR(plm_rst) + ); + FDCE plm_dfm_deframe1_qwfsm_reg_by1_preh_out_8_ ( + .CE(plm_phy_cke_0_712), + .C(mgt_clk), + .D(plm_dfm_deframe1_qwfsm_N_20648_i), + .Q(plm_dfm_by1_preh_out[8]), + .CLR(plm_rst) + ); + FDCE plm_dfm_deframe1_qwfsm_reg_by1_preh_out_7_ ( + .CE(plm_phy_cke_0_712), + .C(mgt_clk), + .D(plm_dfm_deframe1_qwfsm_N_87743_i), + .Q(plm_dfm_by1_preh_out[7]), + .CLR(plm_rst) + ); + FDCE plm_dfm_deframe1_qwfsm_reg_by1_preh_out_6_ ( + .CE(plm_phy_cke_0_712), + .C(mgt_clk), + .D(plm_dfm_deframe1_qwfsm_N_87742_i), + .Q(plm_dfm_by1_preh_out[6]), + .CLR(plm_rst) + ); + FDCE plm_dfm_deframe1_qwfsm_reg_by1_preh_out_5_ ( + .CE(plm_phy_cke_0_712), + .C(mgt_clk), + .D(plm_dfm_deframe1_qwfsm_N_87741_i), + .Q(plm_dfm_by1_preh_out[5]), + .CLR(plm_rst) + ); + FDCE plm_dfm_deframe1_qwfsm_reg_by1_preh_out_4_ ( + .CE(plm_phy_cke_0_712), + .C(mgt_clk), + .D(plm_dfm_deframe1_qwfsm_N_87740_i), + .Q(plm_dfm_by1_preh_out[4]), + .CLR(plm_rst) + ); + FDCE plm_dfm_deframe1_qwfsm_reg_by1_preh_out_3_ ( + .CE(plm_phy_cke_0_712), + .C(mgt_clk), + .D(plm_dfm_deframe1_qwfsm_N_87739_i), + .Q(plm_dfm_by1_preh_out[3]), + .CLR(plm_rst) + ); + FDCE plm_dfm_deframe1_qwfsm_reg_by1_preh_out_2_ ( + .CE(plm_phy_cke_0_712), + .C(mgt_clk), + .D(plm_dfm_deframe1_qwfsm_N_87738_i), + .Q(plm_dfm_by1_preh_out[2]), + .CLR(plm_rst) + ); + FDCE plm_dfm_deframe1_qwfsm_reg_by1_preh_out_1_ ( + .CE(plm_phy_cke_0_712), + .C(mgt_clk), + .D(plm_dfm_deframe1_qwfsm_N_87737_i), + .Q(plm_dfm_by1_preh_out[1]), + .CLR(plm_rst) + ); + FDCE plm_dfm_deframe1_qwfsm_reg_by1_preh_out_0_ ( + .CE(plm_phy_cke_0_712), + .C(mgt_clk), + .D(plm_dfm_deframe1_qwfsm_N_87736_i), + .Q(plm_dfm_by1_preh_out[0]), + .CLR(plm_rst) + ); + FDCE plm_dfm_deframe1_qwfsm_reg_by1_prel_out_31_ ( + .CE(plm_dfm_deframe1_reg_phi1), + .C(mgt_clk), + .D(plm_dfm_deframe1_qwfsm_N_20689_i), + .Q(plm_dfm_by1_prel_out[31]), + .CLR(plm_rst) + ); + FDCE plm_dfm_deframe1_qwfsm_reg_by1_prel_out_30_ ( + .CE(plm_dfm_deframe1_reg_phi1), + .C(mgt_clk), + .D(plm_dfm_deframe1_qwfsm_N_20691_i), + .Q(plm_dfm_by1_prel_out[30]), + .CLR(plm_rst) + ); + FDCE plm_dfm_deframe1_qwfsm_reg_by1_prel_out_29_ ( + .CE(plm_dfm_deframe1_reg_phi1), + .C(mgt_clk), + .D(plm_dfm_deframe1_qwfsm_N_20693_i), + .Q(plm_dfm_by1_prel_out[29]), + .CLR(plm_rst) + ); + FDCE plm_dfm_deframe1_qwfsm_reg_by1_prel_out_28_ ( + .CE(plm_dfm_deframe1_reg_phi1), + .C(mgt_clk), + .D(plm_dfm_deframe1_qwfsm_N_20695_i), + .Q(plm_dfm_by1_prel_out[28]), + .CLR(plm_rst) + ); + FDCE plm_dfm_deframe1_qwfsm_reg_by1_prel_out_27_ ( + .CE(plm_dfm_deframe1_reg_phi1), + .C(mgt_clk), + .D(plm_dfm_deframe1_qwfsm_N_20697_i), + .Q(plm_dfm_by1_prel_out[27]), + .CLR(plm_rst) + ); + FDCE plm_dfm_deframe1_qwfsm_reg_by1_prel_out_26_ ( + .CE(plm_dfm_deframe1_reg_phi1), + .C(mgt_clk), + .D(plm_dfm_deframe1_qwfsm_N_20699_i), + .Q(plm_dfm_by1_prel_out[26]), + .CLR(plm_rst) + ); + FDCE plm_dfm_deframe1_qwfsm_reg_by1_prel_out_25_ ( + .CE(plm_dfm_deframe1_reg_phi1), + .C(mgt_clk), + .D(plm_dfm_deframe1_qwfsm_N_20701_i), + .Q(plm_dfm_by1_prel_out[25]), + .CLR(plm_rst) + ); + FDCE plm_dfm_deframe1_qwfsm_reg_by1_prel_out_24_ ( + .CE(plm_dfm_deframe1_reg_phi1), + .C(mgt_clk), + .D(plm_dfm_deframe1_qwfsm_N_20703_i), + .Q(plm_dfm_by1_prel_out[24]), + .CLR(plm_rst) + ); + FDCE plm_dfm_deframe1_qwfsm_reg_by1_prel_out_23_ ( + .CE(plm_dfm_deframe1_reg_phi1), + .C(mgt_clk), + .D(plm_dfm_deframe1_qwfsm_N_20678_i), + .Q(plm_dfm_by1_prel_out[23]), + .CLR(plm_rst) + ); + FDCE plm_dfm_deframe1_qwfsm_reg_by1_prel_out_22_ ( + .CE(plm_dfm_deframe1_reg_phi1), + .C(mgt_clk), + .D(plm_dfm_deframe1_qwfsm_N_20676_i), + .Q(plm_dfm_by1_prel_out[22]), + .CLR(plm_rst) + ); + FDCE plm_dfm_deframe1_qwfsm_reg_by1_prel_out_21_ ( + .CE(plm_dfm_deframe1_reg_phi1), + .C(mgt_clk), + .D(plm_dfm_deframe1_qwfsm_N_20674_i), + .Q(plm_dfm_by1_prel_out[21]), + .CLR(plm_rst) + ); + FDCE plm_dfm_deframe1_qwfsm_reg_by1_prel_out_20_ ( + .CE(plm_dfm_deframe1_reg_phi1), + .C(mgt_clk), + .D(plm_dfm_deframe1_qwfsm_N_20672_i), + .Q(plm_dfm_by1_prel_out[20]), + .CLR(plm_rst) + ); + FDCE plm_dfm_deframe1_qwfsm_reg_by1_prel_out_19_ ( + .CE(plm_dfm_deframe1_reg_phi1), + .C(mgt_clk), + .D(plm_dfm_deframe1_qwfsm_N_20670_i), + .Q(plm_dfm_by1_prel_out[19]), + .CLR(plm_rst) + ); + FDCE plm_dfm_deframe1_qwfsm_reg_by1_prel_out_18_ ( + .CE(plm_dfm_deframe1_reg_phi1), + .C(mgt_clk), + .D(plm_dfm_deframe1_qwfsm_N_20668_i), + .Q(plm_dfm_by1_prel_out[18]), + .CLR(plm_rst) + ); + FDCE plm_dfm_deframe1_qwfsm_reg_by1_prel_out_17_ ( + .CE(plm_dfm_deframe1_reg_phi1), + .C(mgt_clk), + .D(plm_dfm_deframe1_qwfsm_N_20666_i), + .Q(plm_dfm_by1_prel_out[17]), + .CLR(plm_rst) + ); + FDCE plm_dfm_deframe1_qwfsm_reg_by1_prel_out_16_ ( + .CE(plm_dfm_deframe1_reg_phi1), + .C(mgt_clk), + .D(plm_dfm_deframe1_qwfsm_N_20664_i), + .Q(plm_dfm_by1_prel_out[16]), + .CLR(plm_rst) + ); + FDCE plm_dfm_deframe1_qwfsm_reg_by1_prel_out_15_ ( + .CE(plm_dfm_deframe1_reg_phi1), + .C(mgt_clk), + .D(plm_dfm_deframe1_qwfsm_N_20662_i), + .Q(plm_dfm_by1_prel_out[15]), + .CLR(plm_rst) + ); + FDCE plm_dfm_deframe1_qwfsm_reg_by1_prel_out_14_ ( + .CE(plm_dfm_deframe1_reg_phi1), + .C(mgt_clk), + .D(plm_dfm_deframe1_qwfsm_N_20660_i), + .Q(plm_dfm_by1_prel_out[14]), + .CLR(plm_rst) + ); + FDCE plm_dfm_deframe1_qwfsm_reg_by1_prel_out_13_ ( + .CE(plm_dfm_deframe1_reg_phi1), + .C(mgt_clk), + .D(plm_dfm_deframe1_qwfsm_N_20658_i), + .Q(plm_dfm_by1_prel_out[13]), + .CLR(plm_rst) + ); + FDCE plm_dfm_deframe1_qwfsm_reg_by1_prel_out_12_ ( + .CE(plm_dfm_deframe1_reg_phi1), + .C(mgt_clk), + .D(plm_dfm_deframe1_qwfsm_N_20656_i), + .Q(plm_dfm_by1_prel_out[12]), + .CLR(plm_rst) + ); + FDCE plm_dfm_deframe1_qwfsm_reg_by1_prel_out_11_ ( + .CE(plm_dfm_deframe1_reg_phi1), + .C(mgt_clk), + .D(plm_dfm_deframe1_qwfsm_N_20654_i), + .Q(plm_dfm_by1_prel_out[11]), + .CLR(plm_rst) + ); + FDCE plm_dfm_deframe1_qwfsm_reg_by1_prel_out_10_ ( + .CE(plm_dfm_deframe1_reg_phi1), + .C(mgt_clk), + .D(plm_dfm_deframe1_qwfsm_N_20652_i), + .Q(plm_dfm_by1_prel_out[10]), + .CLR(plm_rst) + ); + FDCE plm_dfm_deframe1_qwfsm_reg_by1_prel_out_9_ ( + .CE(plm_dfm_deframe1_reg_phi1), + .C(mgt_clk), + .D(plm_dfm_deframe1_qwfsm_N_20650_i), + .Q(plm_dfm_by1_prel_out[9]), + .CLR(plm_rst) + ); + FDCE plm_dfm_deframe1_qwfsm_reg_by1_prel_out_8_ ( + .CE(plm_dfm_deframe1_reg_phi1), + .C(mgt_clk), + .D(plm_dfm_deframe1_qwfsm_N_20648_i), + .Q(plm_dfm_by1_prel_out[8]), + .CLR(plm_rst) + ); + FDPE plm_dfm_deframe1_qwfsm_reg_by1_prel_out_7_ ( + .PRE(plm_rst), + .CE(plm_dfm_deframe1_reg_phi1), + .C(mgt_clk), + .D(plm_dfm_deframe1_qwfsm_N_87743_i), + .Q(plm_dfm_by1_prel_out[7]) + ); + FDPE plm_dfm_deframe1_qwfsm_reg_by1_prel_out_6_ ( + .PRE(plm_rst), + .CE(plm_dfm_deframe1_reg_phi1), + .C(mgt_clk), + .D(plm_dfm_deframe1_qwfsm_N_87742_i), + .Q(plm_dfm_by1_prel_out[6]) + ); + FDPE plm_dfm_deframe1_qwfsm_reg_by1_prel_out_5_ ( + .PRE(plm_rst), + .CE(plm_dfm_deframe1_reg_phi1), + .C(mgt_clk), + .D(plm_dfm_deframe1_qwfsm_N_87741_i), + .Q(plm_dfm_by1_prel_out[5]) + ); + FDPE plm_dfm_deframe1_qwfsm_reg_by1_prel_out_4_ ( + .PRE(plm_rst), + .CE(plm_dfm_deframe1_reg_phi1), + .C(mgt_clk), + .D(plm_dfm_deframe1_qwfsm_N_87740_i), + .Q(plm_dfm_by1_prel_out[4]) + ); + FDPE plm_dfm_deframe1_qwfsm_reg_by1_prel_out_3_ ( + .PRE(plm_rst), + .CE(plm_dfm_deframe1_reg_phi1), + .C(mgt_clk), + .D(plm_dfm_deframe1_qwfsm_N_87739_i), + .Q(plm_dfm_by1_prel_out[3]) + ); + FDPE plm_dfm_deframe1_qwfsm_reg_by1_prel_out_2_ ( + .PRE(plm_rst), + .CE(plm_dfm_deframe1_reg_phi1), + .C(mgt_clk), + .D(plm_dfm_deframe1_qwfsm_N_87738_i), + .Q(plm_dfm_by1_prel_out[2]) + ); + FDPE plm_dfm_deframe1_qwfsm_reg_by1_prel_out_1_ ( + .PRE(plm_rst), + .CE(plm_dfm_deframe1_reg_phi1), + .C(mgt_clk), + .D(plm_dfm_deframe1_qwfsm_N_87737_i), + .Q(plm_dfm_by1_prel_out[1]) + ); + FDPE plm_dfm_deframe1_qwfsm_reg_by1_prel_out_0_ ( + .PRE(plm_rst), + .CE(plm_dfm_deframe1_reg_phi1), + .C(mgt_clk), + .D(plm_dfm_deframe1_qwfsm_N_87736_i), + .Q(plm_dfm_by1_prel_out[0]) + ); + FDCE plm_dfm_deframe1_qwfsm_reg_by1_preh_edbedg_1_ ( + .CE(plm_phy_cke_0_712), + .C(mgt_clk), + .D(plm_dfm_deframe1_qwfsm_N_87769_i), + .Q(plm_dfm_by1_preh_edbedg[1]), + .CLR(plm_rst) + ); + FDCE plm_dfm_deframe1_qwfsm_reg_by1_preh_edbedg_0_ ( + .CE(plm_phy_cke_0_712), + .C(mgt_clk), + .D(plm_dfm_deframe1_qwfsm_N_20686_i), + .Q(plm_dfm_by1_preh_edbedg[0]), + .CLR(plm_rst) + ); + FDCE plm_dfm_deframe1_qwfsm_reg_by1_prel_edbedg_1_ ( + .CE(plm_dfm_deframe1_reg_phi1), + .C(mgt_clk), + .D(plm_dfm_deframe1_qwfsm_N_87769_i), + .Q(plm_dfm_by1_prel_edbedg[1]), + .CLR(plm_rst) + ); + FDPE plm_dfm_deframe1_qwfsm_reg_by1_prel_edbedg_0_ ( + .PRE(plm_rst), + .CE(plm_dfm_deframe1_reg_phi1), + .C(mgt_clk), + .D(plm_dfm_deframe1_qwfsm_N_20686_i), + .Q(plm_dfm_by1_prel_edbedg[0]) + ); + defparam plm_dfm_deframe4_filter_reg_h_edbedg_5_i_0_0_0_o3_0_.INIT = 4'h4; + LUT2 plm_dfm_deframe4_filter_reg_h_edbedg_5_i_0_0_0_o3_0_ ( + .I0(cmmp_negotiated_width[0]), + .I1(plm_link_l0), + .O(plm_dfm_deframe4_N_55905_i) + ); + defparam plm_dfm_deframe4_filter_reg_l_edbedg_5_i_0_0_0_o2_0_.INIT = 4'h8; + LUT2 plm_dfm_deframe4_filter_reg_l_edbedg_5_i_0_0_0_o2_0_ ( + .I0(plm_dfm_deframe4_N_55905_i), + .I1(plm_rx2_des_sym[0]), + .O(plm_dfm_deframe4_N_56146_i) + ); + defparam plm_dfm_deframe4_filter_reg_h_edbedg_5_i_0_0_0_o2_0_.INIT = 4'h8; + LUT2 plm_dfm_deframe4_filter_reg_h_edbedg_5_i_0_0_0_o2_0_ ( + .I0(plm_dfm_deframe4_N_55905_i), + .I1(plm_rx1_des_sym[1]), + .O(plm_dfm_deframe4_N_56145_i) + ); + defparam plm_dfm_deframe4_reg_h_dword_8_0_a2_1_a2_1_a3_1_a3_0_.INIT = 4'h8; + LUT2 plm_dfm_deframe4_reg_h_dword_8_0_a2_1_a2_1_a3_1_a3_0_ ( + .I0(plm_dfm_deframe4_N_55905_i), + .I1(plm_rx3_des_sym[1]), + .O(plm_dfm_deframe4_N_61405) + ); + defparam plm_dfm_deframe4_reg_l_dword_8_0_a2_0_a2_1_a3_0_a3_20_.INIT = 4'h8; + LUT2 plm_dfm_deframe4_reg_l_dword_8_0_a2_0_a2_1_a3_0_a3_20_ ( + .I0(plm_dfm_deframe4_N_55905_i), + .I1(plm_rx1_des_sym[0]), + .O(plm_dfm_deframe4_N_61404) + ); + defparam plm_dfm_deframe4_reg_l_dword_8_0_a2_1_a2_1_a3_1_a3_0_.INIT = 4'h8; + LUT2 plm_dfm_deframe4_reg_l_dword_8_0_a2_1_a2_1_a3_1_a3_0_ ( + .I0(plm_dfm_deframe4_N_55905_i), + .I1(plm_rx3_des_sym[0]), + .O(plm_dfm_deframe4_N_61403) + ); + defparam plm_dfm_deframe4_reg_h_dword_8_0_a2_1_a2_1_a3_1_a3_8_.INIT = 4'h8; + LUT2 plm_dfm_deframe4_reg_h_dword_8_0_a2_1_a2_1_a3_1_a3_8_ ( + .I0(plm_dfm_deframe4_N_55905_i), + .I1(plm_rx2_des_sym[1]), + .O(plm_dfm_deframe4_N_61402) + ); + defparam plm_dfm_deframe4_det_d0_0_a2_0_a2_0_a3_0_a2_3.INIT = 16'h0001; + LUT4 plm_dfm_deframe4_det_d0_0_a2_0_a2_0_a3_0_a2_3 ( + .I0(plm_rx2_des_bad[0]), + .I1(plm_rx2_des_bad[1]), + .I2(plm_rx3_des_bad[0]), + .I3(plm_rx3_des_bad[1]), + .O(plm_dfm_deframe4_det_d0_0_a2_0_a2_0_a3_0_a2_3_1564) + ); + defparam plm_dfm_deframe4_filter_reg_l_edbedg_5_i_0_0_0_1_0_1_.INIT = 16'hA200; + LUT4 plm_dfm_deframe4_filter_reg_l_edbedg_5_i_0_0_0_1_0_1_ ( + .I0(plm_dfm_deframe4_N_56146_i), + .I1(plm_dfm_N_58721), + .I2(plm_rx0_des_sym[0]), + .I3(plm_rx1_des_sym[0]), + .O(plm_dfm_deframe4_N_85591_1) + ); + defparam plm_dfm_deframe4_filter_reg_h_edbedg_5_i_0_0_0_1_0_.INIT = 16'hA200; + LUT4 plm_dfm_deframe4_filter_reg_h_edbedg_5_i_0_0_0_1_0_ ( + .I0(plm_dfm_deframe4_N_56145_i), + .I1(plm_dfm_N_58722), + .I2(plm_rx0_des_sym[1]), + .I3(plm_rx2_des_sym[1]), + .O(plm_dfm_deframe4_N_85588_1) + ); + defparam plm_dfm_deframe4_reg_df_dat_m_24_.INIT = 4'h4; + LUT2 plm_dfm_deframe4_reg_df_dat_m_24_ ( + .I0(plm_dfm_deframe4_N_11342), + .I1(plm_dfm_deframe4_reg_df_dat[24]), + .O(plm_dfm_deframe4_reg_df_dat_m_24__1556) + ); + defparam plm_dfm_deframe4_reg_df_dat_m_27_.INIT = 4'h4; + LUT2 plm_dfm_deframe4_reg_df_dat_m_27_ ( + .I0(plm_dfm_deframe4_N_11342), + .I1(plm_dfm_deframe4_reg_df_dat[27]), + .O(plm_dfm_deframe4_reg_df_dat_m_27__1557) + ); + defparam plm_dfm_deframe4_reg_df_dat_m_28_.INIT = 4'h4; + LUT2 plm_dfm_deframe4_reg_df_dat_m_28_ ( + .I0(plm_dfm_deframe4_N_11342), + .I1(plm_dfm_deframe4_reg_df_dat[28]), + .O(plm_dfm_deframe4_reg_df_dat_m_28__1558) + ); + defparam plm_dfm_deframe4_reg_df_dat_m_26_.INIT = 4'h4; + LUT2 plm_dfm_deframe4_reg_df_dat_m_26_ ( + .I0(plm_dfm_deframe4_N_11342), + .I1(plm_dfm_deframe4_reg_df_dat[26]), + .O(plm_dfm_deframe4_reg_df_dat_m_26__1559) + ); + defparam plm_dfm_deframe4_dh_dat_m_0_29_.INIT = 4'h2; + LUT2 plm_dfm_deframe4_dh_dat_m_0_29_ ( + .I0(plm_dfm_deframe4_dh_dat[29]), + .I1(plm_dfm_deframe4_dh_valid), + .O(plm_dfm_deframe4_dh_dat_m_0_29__1560) + ); + defparam plm_dfm_deframe4_dh_dat_m_0_31_.INIT = 4'h2; + LUT2 plm_dfm_deframe4_dh_dat_m_0_31_ ( + .I0(plm_dfm_deframe4_dh_dat[31]), + .I1(plm_dfm_deframe4_dh_valid), + .O(plm_dfm_deframe4_dh_dat_m_0_31__1561) + ); + defparam plm_dfm_deframe4_reg_df_dat_m_30_.INIT = 4'h4; + LUT2 plm_dfm_deframe4_reg_df_dat_m_30_ ( + .I0(plm_dfm_deframe4_N_11342), + .I1(plm_dfm_deframe4_reg_df_dat[30]), + .O(plm_dfm_deframe4_reg_df_dat_m_30__1562) + ); + defparam plm_dfm_deframe4_reg_df_dat_m_25_.INIT = 4'h4; + LUT2 plm_dfm_deframe4_reg_df_dat_m_25_ ( + .I0(plm_dfm_deframe4_N_11342), + .I1(plm_dfm_deframe4_reg_df_dat[25]), + .O(plm_dfm_deframe4_reg_df_dat_m_25__1563) + ); + defparam plm_dfm_deframe4_dh_dat_m_5_.INIT = 4'h4; + LUT2 plm_dfm_deframe4_dh_dat_m_5_ ( + .I0(plm_dfm_deframe4_N_11332), + .I1(plm_dfm_deframe4_dh_dat[5]), + .O(plm_dfm_deframe4_dh_dat_m[5]) + ); + defparam plm_dfm_deframe4_dh_dat_m_2_.INIT = 4'h4; + LUT2 plm_dfm_deframe4_dh_dat_m_2_ ( + .I0(plm_dfm_deframe4_N_11332), + .I1(plm_dfm_deframe4_dh_dat[2]), + .O(plm_dfm_deframe4_dh_dat_m[2]) + ); + defparam plm_dfm_deframe4_dh_dat_m_3_.INIT = 4'h4; + LUT2 plm_dfm_deframe4_dh_dat_m_3_ ( + .I0(plm_dfm_deframe4_N_11332), + .I1(plm_dfm_deframe4_dh_dat[3]), + .O(plm_dfm_deframe4_dh_dat_m[3]) + ); + defparam plm_dfm_deframe4_dh_dat_m_4_.INIT = 4'h4; + LUT2 plm_dfm_deframe4_dh_dat_m_4_ ( + .I0(plm_dfm_deframe4_N_11332), + .I1(plm_dfm_deframe4_dh_dat[4]), + .O(plm_dfm_deframe4_dh_dat_m[4]) + ); + defparam plm_dfm_deframe4_dh_dat_m_7_.INIT = 4'h4; + LUT2 plm_dfm_deframe4_dh_dat_m_7_ ( + .I0(plm_dfm_deframe4_N_11332), + .I1(plm_dfm_deframe4_dh_dat[7]), + .O(plm_dfm_deframe4_dh_dat_m[7]) + ); + defparam plm_dfm_deframe4_dh_dat_m_6_.INIT = 4'h4; + LUT2 plm_dfm_deframe4_dh_dat_m_6_ ( + .I0(plm_dfm_deframe4_N_11332), + .I1(plm_dfm_deframe4_dh_dat[6]), + .O(plm_dfm_deframe4_dh_dat_m[6]) + ); + defparam plm_dfm_deframe4_dh_dat_m_1_.INIT = 4'h4; + LUT2 plm_dfm_deframe4_dh_dat_m_1_ ( + .I0(plm_dfm_deframe4_N_11332), + .I1(plm_dfm_deframe4_dh_dat[1]), + .O(plm_dfm_deframe4_dh_dat_m[1]) + ); + defparam plm_dfm_deframe4_dh_dat_m_0_.INIT = 4'h4; + LUT2 plm_dfm_deframe4_dh_dat_m_0_ ( + .I0(plm_dfm_deframe4_N_11332), + .I1(plm_dfm_deframe4_dh_dat[0]), + .O(plm_dfm_deframe4_dh_dat_m[0]) + ); + defparam plm_dfm_deframe4_N_61204_i.INIT = 16'hFFF7; + LUT4_L plm_dfm_deframe4_N_61204_i ( + .I0(plm_dfm_det_d0_i), + .I1(plm_dfm_deframe4_det_d0_0_a2_0_a2_0_a3_0_a2_3_1564), + .I2(plm_rx1_des_bad[0]), + .I3(plm_rx1_des_bad[1]), + .LO(plm_dfm_deframe4_N_61204_i_1566) + ); + defparam plm_dfm_deframe4_reg_h_dword_8_0_a2_0_a2_0_a3_0_a2_7_.INIT = 4'h8; + LUT2_L plm_dfm_deframe4_reg_h_dword_8_0_a2_0_a2_0_a3_0_a2_7_ ( + .I0(plm_dfm_deframe4_N_61405), + .I1(plm_rx3_des_dat[15]), + .LO(plm_dfm_deframe4_reg_h_dword_8[7]) + ); + defparam plm_dfm_deframe4_reg_h_dword_8_0_a2_0_a2_0_a3_0_a2_6_.INIT = 4'h8; + LUT2_L plm_dfm_deframe4_reg_h_dword_8_0_a2_0_a2_0_a3_0_a2_6_ ( + .I0(plm_dfm_deframe4_N_61405), + .I1(plm_rx3_des_dat[14]), + .LO(plm_dfm_deframe4_reg_h_dword_8[6]) + ); + defparam plm_dfm_deframe4_reg_h_dword_8_0_a2_0_a2_0_a3_0_a2_5_.INIT = 4'h8; + LUT2_L plm_dfm_deframe4_reg_h_dword_8_0_a2_0_a2_0_a3_0_a2_5_ ( + .I0(plm_dfm_deframe4_N_61405), + .I1(plm_rx3_des_dat[13]), + .LO(plm_dfm_deframe4_reg_h_dword_8[5]) + ); + defparam plm_dfm_deframe4_reg_h_dword_8_0_a2_0_a2_0_a3_0_a2_4_.INIT = 4'h8; + LUT2_L plm_dfm_deframe4_reg_h_dword_8_0_a2_0_a2_0_a3_0_a2_4_ ( + .I0(plm_dfm_deframe4_N_61405), + .I1(plm_rx3_des_dat[12]), + .LO(plm_dfm_deframe4_reg_h_dword_8[4]) + ); + defparam plm_dfm_deframe4_reg_h_dword_8_0_a2_0_a2_0_a3_0_a2_3_.INIT = 4'h8; + LUT2_L plm_dfm_deframe4_reg_h_dword_8_0_a2_0_a2_0_a3_0_a2_3_ ( + .I0(plm_dfm_deframe4_N_61405), + .I1(plm_rx3_des_dat[11]), + .LO(plm_dfm_deframe4_reg_h_dword_8[3]) + ); + defparam plm_dfm_deframe4_reg_h_dword_8_0_a2_0_a2_0_a3_0_a2_2_.INIT = 4'h8; + LUT2_L plm_dfm_deframe4_reg_h_dword_8_0_a2_0_a2_0_a3_0_a2_2_ ( + .I0(plm_dfm_deframe4_N_61405), + .I1(plm_rx3_des_dat[10]), + .LO(plm_dfm_deframe4_reg_h_dword_8[2]) + ); + defparam plm_dfm_deframe4_reg_h_dword_8_0_a2_0_a2_0_a3_0_a2_1_.INIT = 4'h8; + LUT2_L plm_dfm_deframe4_reg_h_dword_8_0_a2_0_a2_0_a3_0_a2_1_ ( + .I0(plm_dfm_deframe4_N_61405), + .I1(plm_rx3_des_dat[9]), + .LO(plm_dfm_deframe4_reg_h_dword_8[1]) + ); + defparam plm_dfm_deframe4_reg_h_dword_8_0_a2_1_a2_1_a3_1_a2_0_.INIT = 4'h8; + LUT2_L plm_dfm_deframe4_reg_h_dword_8_0_a2_1_a2_1_a3_1_a2_0_ ( + .I0(plm_dfm_deframe4_N_61405), + .I1(plm_rx3_des_dat[8]), + .LO(plm_dfm_deframe4_reg_h_dword_8[0]) + ); + defparam plm_dfm_deframe4_reg_h_dword_8_0_a2_0_a2_0_a3_0_a2_22_.INIT = 4'h8; + LUT2_L plm_dfm_deframe4_reg_h_dword_8_0_a2_0_a2_0_a3_0_a2_22_ ( + .I0(plm_dfm_deframe4_N_56145_i), + .I1(plm_rx1_des_dat[14]), + .LO(plm_dfm_deframe4_reg_h_dword_8[22]) + ); + defparam plm_dfm_deframe4_reg_h_dword_8_0_a2_0_a2_0_a3_0_a2_21_.INIT = 4'h8; + LUT2_L plm_dfm_deframe4_reg_h_dword_8_0_a2_0_a2_0_a3_0_a2_21_ ( + .I0(plm_dfm_deframe4_N_56145_i), + .I1(plm_rx1_des_dat[13]), + .LO(plm_dfm_deframe4_reg_h_dword_8[21]) + ); + defparam plm_dfm_deframe4_reg_h_dword_8_0_a2_0_a2_0_a3_0_a2_20_.INIT = 4'h8; + LUT2_L plm_dfm_deframe4_reg_h_dword_8_0_a2_0_a2_0_a3_0_a2_20_ ( + .I0(plm_dfm_deframe4_N_56145_i), + .I1(plm_rx1_des_dat[12]), + .LO(plm_dfm_deframe4_reg_h_dword_8[20]) + ); + defparam plm_dfm_deframe4_reg_h_dword_8_0_a2_0_a2_0_a3_0_a2_19_.INIT = 4'h8; + LUT2_L plm_dfm_deframe4_reg_h_dword_8_0_a2_0_a2_0_a3_0_a2_19_ ( + .I0(plm_dfm_deframe4_N_56145_i), + .I1(plm_rx1_des_dat[11]), + .LO(plm_dfm_deframe4_reg_h_dword_8[19]) + ); + defparam plm_dfm_deframe4_reg_h_dword_8_0_a2_0_a2_0_a3_0_a2_18_.INIT = 4'h8; + LUT2_L plm_dfm_deframe4_reg_h_dword_8_0_a2_0_a2_0_a3_0_a2_18_ ( + .I0(plm_dfm_deframe4_N_56145_i), + .I1(plm_rx1_des_dat[10]), + .LO(plm_dfm_deframe4_reg_h_dword_8[18]) + ); + defparam plm_dfm_deframe4_reg_h_dword_8_0_a2_0_a2_0_a3_0_a2_17_.INIT = 4'h8; + LUT2_L plm_dfm_deframe4_reg_h_dword_8_0_a2_0_a2_0_a3_0_a2_17_ ( + .I0(plm_dfm_deframe4_N_56145_i), + .I1(plm_rx1_des_dat[9]), + .LO(plm_dfm_deframe4_reg_h_dword_8[17]) + ); + defparam plm_dfm_deframe4_reg_h_dword_8_0_a2_1_a2_0_a3_0_a2_16_.INIT = 4'h8; + LUT2_L plm_dfm_deframe4_reg_h_dword_8_0_a2_1_a2_0_a3_0_a2_16_ ( + .I0(plm_dfm_deframe4_N_56145_i), + .I1(plm_rx1_des_dat[8]), + .LO(plm_dfm_deframe4_reg_h_dword_8[16]) + ); + defparam plm_dfm_deframe4_reg_h_dword_8_0_a2_0_a2_0_a3_0_a2_15_.INIT = 4'h8; + LUT2_L plm_dfm_deframe4_reg_h_dword_8_0_a2_0_a2_0_a3_0_a2_15_ ( + .I0(plm_dfm_deframe4_N_61402), + .I1(plm_rx2_des_dat[15]), + .LO(plm_dfm_deframe4_reg_h_dword_8[15]) + ); + defparam plm_dfm_deframe4_reg_h_dword_8_0_a2_0_a2_0_a3_0_a2_14_.INIT = 4'h8; + LUT2_L plm_dfm_deframe4_reg_h_dword_8_0_a2_0_a2_0_a3_0_a2_14_ ( + .I0(plm_dfm_deframe4_N_61402), + .I1(plm_rx2_des_dat[14]), + .LO(plm_dfm_deframe4_reg_h_dword_8[14]) + ); + defparam plm_dfm_deframe4_reg_h_dword_8_0_a2_0_a2_0_a3_0_a2_13_.INIT = 4'h8; + LUT2_L plm_dfm_deframe4_reg_h_dword_8_0_a2_0_a2_0_a3_0_a2_13_ ( + .I0(plm_dfm_deframe4_N_61402), + .I1(plm_rx2_des_dat[13]), + .LO(plm_dfm_deframe4_reg_h_dword_8[13]) + ); + defparam plm_dfm_deframe4_reg_h_dword_8_0_a2_0_a2_0_a3_0_a2_12_.INIT = 4'h8; + LUT2_L plm_dfm_deframe4_reg_h_dword_8_0_a2_0_a2_0_a3_0_a2_12_ ( + .I0(plm_dfm_deframe4_N_61402), + .I1(plm_rx2_des_dat[12]), + .LO(plm_dfm_deframe4_reg_h_dword_8[12]) + ); + defparam plm_dfm_deframe4_reg_h_dword_8_0_a2_0_a2_0_a3_0_a2_11_.INIT = 4'h8; + LUT2_L plm_dfm_deframe4_reg_h_dword_8_0_a2_0_a2_0_a3_0_a2_11_ ( + .I0(plm_dfm_deframe4_N_61402), + .I1(plm_rx2_des_dat[11]), + .LO(plm_dfm_deframe4_reg_h_dword_8[11]) + ); + defparam plm_dfm_deframe4_reg_h_dword_8_0_a2_0_a2_0_a3_0_a2_10_.INIT = 4'h8; + LUT2_L plm_dfm_deframe4_reg_h_dword_8_0_a2_0_a2_0_a3_0_a2_10_ ( + .I0(plm_dfm_deframe4_N_61402), + .I1(plm_rx2_des_dat[10]), + .LO(plm_dfm_deframe4_reg_h_dword_8[10]) + ); + defparam plm_dfm_deframe4_reg_h_dword_8_0_a2_0_a2_0_a3_0_a2_9_.INIT = 4'h8; + LUT2_L plm_dfm_deframe4_reg_h_dword_8_0_a2_0_a2_0_a3_0_a2_9_ ( + .I0(plm_dfm_deframe4_N_61402), + .I1(plm_rx2_des_dat[9]), + .LO(plm_dfm_deframe4_reg_h_dword_8[9]) + ); + defparam plm_dfm_deframe4_reg_h_dword_8_0_a2_1_a2_1_a3_1_a2_8_.INIT = 4'h8; + LUT2_L plm_dfm_deframe4_reg_h_dword_8_0_a2_1_a2_1_a3_1_a2_8_ ( + .I0(plm_dfm_deframe4_N_61402), + .I1(plm_rx2_des_dat[8]), + .LO(plm_dfm_deframe4_reg_h_dword_8[8]) + ); + defparam plm_dfm_deframe4_reg_l_dword_8_0_a2_0_a2_0_a3_0_a2_5_.INIT = 4'h8; + LUT2_L plm_dfm_deframe4_reg_l_dword_8_0_a2_0_a2_0_a3_0_a2_5_ ( + .I0(plm_dfm_deframe4_N_61403), + .I1(plm_rx3_des_dat[5]), + .LO(plm_dfm_deframe4_reg_l_dword_8[5]) + ); + defparam plm_dfm_deframe4_reg_l_dword_8_0_a2_0_a2_0_a3_0_a2_4_.INIT = 4'h8; + LUT2_L plm_dfm_deframe4_reg_l_dword_8_0_a2_0_a2_0_a3_0_a2_4_ ( + .I0(plm_dfm_deframe4_N_61403), + .I1(plm_rx3_des_dat[4]), + .LO(plm_dfm_deframe4_reg_l_dword_8[4]) + ); + defparam plm_dfm_deframe4_reg_l_dword_8_0_a2_0_a2_0_a3_0_a2_3_.INIT = 4'h8; + LUT2_L plm_dfm_deframe4_reg_l_dword_8_0_a2_0_a2_0_a3_0_a2_3_ ( + .I0(plm_dfm_deframe4_N_61403), + .I1(plm_rx3_des_dat[3]), + .LO(plm_dfm_deframe4_reg_l_dword_8[3]) + ); + defparam plm_dfm_deframe4_reg_l_dword_8_0_a2_0_a2_0_a3_0_a2_2_.INIT = 4'h8; + LUT2_L plm_dfm_deframe4_reg_l_dword_8_0_a2_0_a2_0_a3_0_a2_2_ ( + .I0(plm_dfm_deframe4_N_61403), + .I1(plm_rx3_des_dat[2]), + .LO(plm_dfm_deframe4_reg_l_dword_8[2]) + ); + defparam plm_dfm_deframe4_reg_l_dword_8_0_a2_0_a2_0_a3_0_a2_1_.INIT = 4'h8; + LUT2_L plm_dfm_deframe4_reg_l_dword_8_0_a2_0_a2_0_a3_0_a2_1_ ( + .I0(plm_dfm_deframe4_N_61403), + .I1(plm_rx3_des_dat[1]), + .LO(plm_dfm_deframe4_reg_l_dword_8[1]) + ); + defparam plm_dfm_deframe4_reg_l_dword_8_0_a2_1_a2_1_a3_1_a2_0_.INIT = 4'h8; + LUT2_L plm_dfm_deframe4_reg_l_dword_8_0_a2_1_a2_1_a3_1_a2_0_ ( + .I0(plm_dfm_deframe4_N_61403), + .I1(plm_rx3_des_dat[0]), + .LO(plm_dfm_deframe4_reg_l_dword_8[0]) + ); + defparam plm_dfm_deframe4_reg_h_dword_8_0_a2_0_a2_0_a3_0_a2_31_.INIT = 8'h80; + LUT3_L plm_dfm_deframe4_reg_h_dword_8_0_a2_0_a2_0_a3_0_a2_31_ ( + .I0(plm_dfm_deframe4_N_55905_i), + .I1(plm_rx0_des_dat[15]), + .I2(plm_rx0_des_sym[1]), + .LO(plm_dfm_deframe4_reg_h_dword_8[31]) + ); + defparam plm_dfm_deframe4_reg_h_dword_8_0_a2_0_a2_0_a3_0_a2_30_.INIT = 8'h80; + LUT3_L plm_dfm_deframe4_reg_h_dword_8_0_a2_0_a2_0_a3_0_a2_30_ ( + .I0(plm_dfm_deframe4_N_55905_i), + .I1(plm_rx0_des_dat[14]), + .I2(plm_rx0_des_sym[1]), + .LO(plm_dfm_deframe4_reg_h_dword_8[30]) + ); + defparam plm_dfm_deframe4_reg_h_dword_8_0_a2_0_a2_0_a3_0_a2_29_.INIT = 8'h80; + LUT3_L plm_dfm_deframe4_reg_h_dword_8_0_a2_0_a2_0_a3_0_a2_29_ ( + .I0(plm_dfm_deframe4_N_55905_i), + .I1(plm_rx0_des_dat[13]), + .I2(plm_rx0_des_sym[1]), + .LO(plm_dfm_deframe4_reg_h_dword_8[29]) + ); + defparam plm_dfm_deframe4_reg_h_dword_8_0_a2_0_a2_0_a3_0_a2_28_.INIT = 8'h80; + LUT3_L plm_dfm_deframe4_reg_h_dword_8_0_a2_0_a2_0_a3_0_a2_28_ ( + .I0(plm_dfm_deframe4_N_55905_i), + .I1(plm_rx0_des_dat[12]), + .I2(plm_rx0_des_sym[1]), + .LO(plm_dfm_deframe4_reg_h_dword_8[28]) + ); + defparam plm_dfm_deframe4_reg_h_dword_8_0_a2_0_a2_0_a3_0_a2_27_.INIT = 8'h80; + LUT3_L plm_dfm_deframe4_reg_h_dword_8_0_a2_0_a2_0_a3_0_a2_27_ ( + .I0(plm_dfm_deframe4_N_55905_i), + .I1(plm_rx0_des_dat[11]), + .I2(plm_rx0_des_sym[1]), + .LO(plm_dfm_deframe4_reg_h_dword_8[27]) + ); + defparam plm_dfm_deframe4_reg_h_dword_8_0_a2_0_a2_0_a3_0_a2_26_.INIT = 8'h80; + LUT3_L plm_dfm_deframe4_reg_h_dword_8_0_a2_0_a2_0_a3_0_a2_26_ ( + .I0(plm_dfm_deframe4_N_55905_i), + .I1(plm_rx0_des_dat[10]), + .I2(plm_rx0_des_sym[1]), + .LO(plm_dfm_deframe4_reg_h_dword_8[26]) + ); + defparam plm_dfm_deframe4_reg_h_dword_8_0_a2_0_a2_0_a3_0_a2_25_.INIT = 8'h80; + LUT3_L plm_dfm_deframe4_reg_h_dword_8_0_a2_0_a2_0_a3_0_a2_25_ ( + .I0(plm_dfm_deframe4_N_55905_i), + .I1(plm_rx0_des_dat[9]), + .I2(plm_rx0_des_sym[1]), + .LO(plm_dfm_deframe4_reg_h_dword_8[25]) + ); + defparam plm_dfm_deframe4_reg_h_dword_8_0_a2_0_a2_1_a3_1_a2_24_.INIT = 8'h80; + LUT3_L plm_dfm_deframe4_reg_h_dword_8_0_a2_0_a2_1_a3_1_a2_24_ ( + .I0(plm_dfm_deframe4_N_55905_i), + .I1(plm_rx0_des_dat[8]), + .I2(plm_rx0_des_sym[1]), + .LO(plm_dfm_deframe4_reg_h_dword_8[24]) + ); + defparam plm_dfm_deframe4_reg_h_dword_8_0_a2_0_a2_0_a3_0_a2_23_.INIT = 4'h8; + LUT2_L plm_dfm_deframe4_reg_h_dword_8_0_a2_0_a2_0_a3_0_a2_23_ ( + .I0(plm_dfm_deframe4_N_56145_i), + .I1(plm_rx1_des_dat[15]), + .LO(plm_dfm_deframe4_reg_h_dword_8[23]) + ); + defparam plm_dfm_deframe4_reg_l_dword_8_0_a2_0_a2_1_a3_0_a2_20_.INIT = 4'h8; + LUT2_L plm_dfm_deframe4_reg_l_dword_8_0_a2_0_a2_1_a3_0_a2_20_ ( + .I0(plm_dfm_deframe4_N_61404), + .I1(plm_rx1_des_dat[4]), + .LO(plm_dfm_deframe4_reg_l_dword_8[20]) + ); + defparam plm_dfm_deframe4_reg_l_dword_8_0_a2_0_a2_0_a3_0_a2_19_.INIT = 4'h8; + LUT2_L plm_dfm_deframe4_reg_l_dword_8_0_a2_0_a2_0_a3_0_a2_19_ ( + .I0(plm_dfm_deframe4_N_61404), + .I1(plm_rx1_des_dat[3]), + .LO(plm_dfm_deframe4_reg_l_dword_8[19]) + ); + defparam plm_dfm_deframe4_reg_l_dword_8_0_a2_0_a2_0_a3_0_a2_18_.INIT = 4'h8; + LUT2_L plm_dfm_deframe4_reg_l_dword_8_0_a2_0_a2_0_a3_0_a2_18_ ( + .I0(plm_dfm_deframe4_N_61404), + .I1(plm_rx1_des_dat[2]), + .LO(plm_dfm_deframe4_reg_l_dword_8[18]) + ); + defparam plm_dfm_deframe4_reg_l_dword_8_0_a2_0_a2_0_a3_0_a2_17_.INIT = 4'h8; + LUT2_L plm_dfm_deframe4_reg_l_dword_8_0_a2_0_a2_0_a3_0_a2_17_ ( + .I0(plm_dfm_deframe4_N_61404), + .I1(plm_rx1_des_dat[1]), + .LO(plm_dfm_deframe4_reg_l_dword_8[17]) + ); + defparam plm_dfm_deframe4_reg_l_dword_8_0_a2_0_a2_0_a3_0_a2_16_.INIT = 4'h8; + LUT2_L plm_dfm_deframe4_reg_l_dword_8_0_a2_0_a2_0_a3_0_a2_16_ ( + .I0(plm_dfm_deframe4_N_61404), + .I1(plm_rx1_des_dat[0]), + .LO(plm_dfm_deframe4_reg_l_dword_8[16]) + ); + defparam plm_dfm_deframe4_reg_l_dword_8_0_a2_0_a2_0_a3_0_a2_15_.INIT = 4'h8; + LUT2_L plm_dfm_deframe4_reg_l_dword_8_0_a2_0_a2_0_a3_0_a2_15_ ( + .I0(plm_dfm_deframe4_N_56146_i), + .I1(plm_rx2_des_dat[7]), + .LO(plm_dfm_deframe4_reg_l_dword_8[15]) + ); + defparam plm_dfm_deframe4_reg_l_dword_8_0_a2_0_a2_0_a3_0_a2_14_.INIT = 4'h8; + LUT2_L plm_dfm_deframe4_reg_l_dword_8_0_a2_0_a2_0_a3_0_a2_14_ ( + .I0(plm_dfm_deframe4_N_56146_i), + .I1(plm_rx2_des_dat[6]), + .LO(plm_dfm_deframe4_reg_l_dword_8[14]) + ); + defparam plm_dfm_deframe4_reg_l_dword_8_0_a2_0_a2_0_a3_0_a2_13_.INIT = 4'h8; + LUT2_L plm_dfm_deframe4_reg_l_dword_8_0_a2_0_a2_0_a3_0_a2_13_ ( + .I0(plm_dfm_deframe4_N_56146_i), + .I1(plm_rx2_des_dat[5]), + .LO(plm_dfm_deframe4_reg_l_dword_8[13]) + ); + defparam plm_dfm_deframe4_reg_l_dword_8_0_a2_0_a2_0_a3_0_a2_12_.INIT = 4'h8; + LUT2_L plm_dfm_deframe4_reg_l_dword_8_0_a2_0_a2_0_a3_0_a2_12_ ( + .I0(plm_dfm_deframe4_N_56146_i), + .I1(plm_rx2_des_dat[4]), + .LO(plm_dfm_deframe4_reg_l_dword_8[12]) + ); + defparam plm_dfm_deframe4_reg_l_dword_8_0_a2_0_a2_0_a3_0_a2_11_.INIT = 4'h8; + LUT2_L plm_dfm_deframe4_reg_l_dword_8_0_a2_0_a2_0_a3_0_a2_11_ ( + .I0(plm_dfm_deframe4_N_56146_i), + .I1(plm_rx2_des_dat[3]), + .LO(plm_dfm_deframe4_reg_l_dword_8[11]) + ); + defparam plm_dfm_deframe4_reg_l_dword_8_0_a2_0_a2_0_a3_0_a2_10_.INIT = 4'h8; + LUT2_L plm_dfm_deframe4_reg_l_dword_8_0_a2_0_a2_0_a3_0_a2_10_ ( + .I0(plm_dfm_deframe4_N_56146_i), + .I1(plm_rx2_des_dat[2]), + .LO(plm_dfm_deframe4_reg_l_dword_8[10]) + ); + defparam plm_dfm_deframe4_reg_l_dword_8_0_a2_0_a2_0_a3_0_a2_9_.INIT = 4'h8; + LUT2_L plm_dfm_deframe4_reg_l_dword_8_0_a2_0_a2_0_a3_0_a2_9_ ( + .I0(plm_dfm_deframe4_N_56146_i), + .I1(plm_rx2_des_dat[1]), + .LO(plm_dfm_deframe4_reg_l_dword_8[9]) + ); + defparam plm_dfm_deframe4_reg_l_dword_8_0_a2_1_a2_0_a3_1_a2_8_.INIT = 4'h8; + LUT2_L plm_dfm_deframe4_reg_l_dword_8_0_a2_1_a2_0_a3_1_a2_8_ ( + .I0(plm_dfm_deframe4_N_56146_i), + .I1(plm_rx2_des_dat[0]), + .LO(plm_dfm_deframe4_reg_l_dword_8[8]) + ); + defparam plm_dfm_deframe4_reg_l_dword_8_0_a2_0_a2_0_a3_0_a2_7_.INIT = 4'h8; + LUT2_L plm_dfm_deframe4_reg_l_dword_8_0_a2_0_a2_0_a3_0_a2_7_ ( + .I0(plm_dfm_deframe4_N_61403), + .I1(plm_rx3_des_dat[7]), + .LO(plm_dfm_deframe4_reg_l_dword_8[7]) + ); + defparam plm_dfm_deframe4_reg_l_dword_8_0_a2_0_a2_0_a3_0_a2_6_.INIT = 4'h8; + LUT2_L plm_dfm_deframe4_reg_l_dword_8_0_a2_0_a2_0_a3_0_a2_6_ ( + .I0(plm_dfm_deframe4_N_61403), + .I1(plm_rx3_des_dat[6]), + .LO(plm_dfm_deframe4_reg_l_dword_8[6]) + ); + defparam plm_dfm_deframe4_filter_N_85591_i.INIT = 16'hDDDF; + LUT4_L plm_dfm_deframe4_filter_N_85591_i ( + .I0(plm_dfm_deframe4_N_85591_1), + .I1(plm_rx3_des_edb[0]), + .I2(plm_rx3_des_edg[0]), + .I3(plm_rx3_des_sym[0]), + .LO(plm_dfm_deframe4_N_85591_i) + ); + defparam plm_dfm_deframe4_filter_N_85590_i.INIT = 16'hF5F7; + LUT4_L plm_dfm_deframe4_filter_N_85590_i ( + .I0(plm_dfm_deframe4_N_85591_1), + .I1(plm_rx3_des_edb[0]), + .I2(plm_rx3_des_edg[0]), + .I3(plm_rx3_des_sym[0]), + .LO(plm_dfm_deframe4_N_85590_i) + ); + defparam plm_dfm_deframe4_filter_N_85589_i.INIT = 16'hDDDF; + LUT4_L plm_dfm_deframe4_filter_N_85589_i ( + .I0(plm_dfm_deframe4_N_85588_1), + .I1(plm_rx3_des_edb[1]), + .I2(plm_rx3_des_edg[1]), + .I3(plm_rx3_des_sym[1]), + .LO(plm_dfm_deframe4_N_85589_i) + ); + defparam plm_dfm_deframe4_filter_N_85588_i.INIT = 16'hF5F7; + LUT4_L plm_dfm_deframe4_filter_N_85588_i ( + .I0(plm_dfm_deframe4_N_85588_1), + .I1(plm_rx3_des_edb[1]), + .I2(plm_rx3_des_edg[1]), + .I3(plm_rx3_des_sym[1]), + .LO(plm_dfm_deframe4_N_85588_i) + ); + defparam plm_dfm_deframe4_reg_l_dword_8_0_a2_0_a2_0_a3_0_a2_31_.INIT = 8'h80; + LUT3_L plm_dfm_deframe4_reg_l_dword_8_0_a2_0_a2_0_a3_0_a2_31_ ( + .I0(plm_dfm_deframe4_N_55905_i), + .I1(plm_rx0_des_dat[7]), + .I2(plm_rx0_des_sym[0]), + .LO(plm_dfm_deframe4_reg_l_dword_8[31]) + ); + defparam plm_dfm_deframe4_reg_l_dword_8_0_a2_0_a2_0_a3_0_a2_30_.INIT = 8'h80; + LUT3_L plm_dfm_deframe4_reg_l_dword_8_0_a2_0_a2_0_a3_0_a2_30_ ( + .I0(plm_dfm_deframe4_N_55905_i), + .I1(plm_rx0_des_dat[6]), + .I2(plm_rx0_des_sym[0]), + .LO(plm_dfm_deframe4_reg_l_dword_8[30]) + ); + defparam plm_dfm_deframe4_reg_l_dword_8_0_a2_0_a2_0_a3_0_a2_29_.INIT = 8'h80; + LUT3_L plm_dfm_deframe4_reg_l_dword_8_0_a2_0_a2_0_a3_0_a2_29_ ( + .I0(plm_dfm_deframe4_N_55905_i), + .I1(plm_rx0_des_dat[5]), + .I2(plm_rx0_des_sym[0]), + .LO(plm_dfm_deframe4_reg_l_dword_8[29]) + ); + defparam plm_dfm_deframe4_reg_l_dword_8_0_a2_0_a2_0_a3_0_a2_28_.INIT = 8'h80; + LUT3_L plm_dfm_deframe4_reg_l_dword_8_0_a2_0_a2_0_a3_0_a2_28_ ( + .I0(plm_dfm_deframe4_N_55905_i), + .I1(plm_rx0_des_dat[4]), + .I2(plm_rx0_des_sym[0]), + .LO(plm_dfm_deframe4_reg_l_dword_8[28]) + ); + defparam plm_dfm_deframe4_reg_l_dword_8_0_a2_0_a2_0_a3_0_a2_27_.INIT = 8'h80; + LUT3_L plm_dfm_deframe4_reg_l_dword_8_0_a2_0_a2_0_a3_0_a2_27_ ( + .I0(plm_dfm_deframe4_N_55905_i), + .I1(plm_rx0_des_dat[3]), + .I2(plm_rx0_des_sym[0]), + .LO(plm_dfm_deframe4_reg_l_dword_8[27]) + ); + defparam plm_dfm_deframe4_reg_l_dword_8_0_a2_0_a2_0_a3_0_a2_26_.INIT = 8'h80; + LUT3_L plm_dfm_deframe4_reg_l_dword_8_0_a2_0_a2_0_a3_0_a2_26_ ( + .I0(plm_dfm_deframe4_N_55905_i), + .I1(plm_rx0_des_dat[2]), + .I2(plm_rx0_des_sym[0]), + .LO(plm_dfm_deframe4_reg_l_dword_8[26]) + ); + defparam plm_dfm_deframe4_reg_l_dword_8_0_a2_0_a2_0_a3_0_a2_25_.INIT = 8'h80; + LUT3_L plm_dfm_deframe4_reg_l_dword_8_0_a2_0_a2_0_a3_0_a2_25_ ( + .I0(plm_dfm_deframe4_N_55905_i), + .I1(plm_rx0_des_dat[1]), + .I2(plm_rx0_des_sym[0]), + .LO(plm_dfm_deframe4_reg_l_dword_8[25]) + ); + defparam plm_dfm_deframe4_reg_l_dword_8_0_a2_0_a2_1_a3_1_a2_24_.INIT = 8'h80; + LUT3_L plm_dfm_deframe4_reg_l_dword_8_0_a2_0_a2_1_a3_1_a2_24_ ( + .I0(plm_dfm_deframe4_N_55905_i), + .I1(plm_rx0_des_dat[0]), + .I2(plm_rx0_des_sym[0]), + .LO(plm_dfm_deframe4_reg_l_dword_8[24]) + ); + defparam plm_dfm_deframe4_reg_l_dword_8_0_a2_0_a2_0_a3_0_a2_23_.INIT = 4'h8; + LUT2_L plm_dfm_deframe4_reg_l_dword_8_0_a2_0_a2_0_a3_0_a2_23_ ( + .I0(plm_dfm_deframe4_N_61404), + .I1(plm_rx1_des_dat[7]), + .LO(plm_dfm_deframe4_reg_l_dword_8[23]) + ); + defparam plm_dfm_deframe4_reg_l_dword_8_0_a2_0_a2_0_a3_0_a2_22_.INIT = 4'h8; + LUT2_L plm_dfm_deframe4_reg_l_dword_8_0_a2_0_a2_0_a3_0_a2_22_ ( + .I0(plm_dfm_deframe4_N_61404), + .I1(plm_rx1_des_dat[6]), + .LO(plm_dfm_deframe4_reg_l_dword_8[22]) + ); + defparam plm_dfm_deframe4_reg_l_dword_8_0_a2_0_a2_0_a3_0_a2_21_.INIT = 4'h8; + LUT2_L plm_dfm_deframe4_reg_l_dword_8_0_a2_0_a2_0_a3_0_a2_21_ ( + .I0(plm_dfm_deframe4_N_61404), + .I1(plm_rx1_des_dat[5]), + .LO(plm_dfm_deframe4_reg_l_dword_8[21]) + ); + defparam plm_dfm_deframe4_filter_reg_l_sdpstp_5_0_a2_0_a2_0_a3_0_a2_1_.INIT = 4'h8; + LUT2_L plm_dfm_deframe4_filter_reg_l_sdpstp_5_0_a2_0_a2_0_a3_0_a2_1_ ( + .I0(plm_dfm_deframe4_N_55905_i), + .I1(plm_rx0_des_sdp[0]), + .LO(plm_dfm_deframe4_reg_l_sdpstp_5[1]) + ); + defparam plm_dfm_deframe4_filter_reg_l_sdpstp_5_0_a2_0_a2_0_a3_0_a2_0_.INIT = 4'h8; + LUT2_L plm_dfm_deframe4_filter_reg_l_sdpstp_5_0_a2_0_a2_0_a3_0_a2_0_ ( + .I0(plm_dfm_deframe4_N_55905_i), + .I1(plm_rx0_des_stp[0]), + .LO(plm_dfm_deframe4_reg_l_sdpstp_5[0]) + ); + defparam plm_dfm_deframe4_filter_reg_h_sdpstp_5_0_a2_0_a2_0_a3_0_a2_1_.INIT = 4'h8; + LUT2_L plm_dfm_deframe4_filter_reg_h_sdpstp_5_0_a2_0_a2_0_a3_0_a2_1_ ( + .I0(plm_dfm_deframe4_N_55905_i), + .I1(plm_rx0_des_sdp[1]), + .LO(plm_dfm_deframe4_reg_h_sdpstp_5[1]) + ); + defparam plm_dfm_deframe4_filter_reg_h_sdpstp_5_0_a2_0_a2_0_a3_0_a2_0_.INIT = 4'h8; + LUT2_L plm_dfm_deframe4_filter_reg_h_sdpstp_5_0_a2_0_a2_0_a3_0_a2_0_ ( + .I0(plm_dfm_deframe4_N_55905_i), + .I1(plm_rx0_des_stp[1]), + .LO(plm_dfm_deframe4_reg_h_sdpstp_5[0]) + ); + FDC plm_dfm_deframe4_reg_df_valid ( + .C(mgt_clk), + .D(plm_dfm_deframe4_dl_valid), + .Q(plm_dfm_deframe4_reg_df_valid_1565), + .CLR(plm_rst) + ); + FDC plm_dfm_deframe4_reg_by4_prec_rcverr ( + .C(mgt_clk), + .D(plm_dfm_deframe4_N_61204_i_1566), + .Q(plm_dfm_by4_prec_rcverr), + .CLR(plm_rst) + ); + FDC plm_dfm_deframe4_reg_h_dword_7_ ( + .C(mgt_clk), + .D(plm_dfm_deframe4_reg_h_dword_8[7]), + .Q(plm_dfm_deframe4_dh_dat[7]), + .CLR(plm_rst) + ); + FDC plm_dfm_deframe4_reg_h_dword_6_ ( + .C(mgt_clk), + .D(plm_dfm_deframe4_reg_h_dword_8[6]), + .Q(plm_dfm_deframe4_dh_dat[6]), + .CLR(plm_rst) + ); + FDC plm_dfm_deframe4_reg_h_dword_5_ ( + .C(mgt_clk), + .D(plm_dfm_deframe4_reg_h_dword_8[5]), + .Q(plm_dfm_deframe4_dh_dat[5]), + .CLR(plm_rst) + ); + FDC plm_dfm_deframe4_reg_h_dword_4_ ( + .C(mgt_clk), + .D(plm_dfm_deframe4_reg_h_dword_8[4]), + .Q(plm_dfm_deframe4_dh_dat[4]), + .CLR(plm_rst) + ); + FDC plm_dfm_deframe4_reg_h_dword_3_ ( + .C(mgt_clk), + .D(plm_dfm_deframe4_reg_h_dword_8[3]), + .Q(plm_dfm_deframe4_dh_dat[3]), + .CLR(plm_rst) + ); + FDC plm_dfm_deframe4_reg_h_dword_2_ ( + .C(mgt_clk), + .D(plm_dfm_deframe4_reg_h_dword_8[2]), + .Q(plm_dfm_deframe4_dh_dat[2]), + .CLR(plm_rst) + ); + FDC plm_dfm_deframe4_reg_h_dword_1_ ( + .C(mgt_clk), + .D(plm_dfm_deframe4_reg_h_dword_8[1]), + .Q(plm_dfm_deframe4_dh_dat[1]), + .CLR(plm_rst) + ); + FDC plm_dfm_deframe4_reg_h_dword_0_ ( + .C(mgt_clk), + .D(plm_dfm_deframe4_reg_h_dword_8[0]), + .Q(plm_dfm_deframe4_dh_dat[0]), + .CLR(plm_rst) + ); + FDC plm_dfm_deframe4_reg_h_dword_22_ ( + .C(mgt_clk), + .D(plm_dfm_deframe4_reg_h_dword_8[22]), + .Q(plm_dfm_deframe4_dh_dat[22]), + .CLR(plm_rst) + ); + FDC plm_dfm_deframe4_reg_h_dword_21_ ( + .C(mgt_clk), + .D(plm_dfm_deframe4_reg_h_dword_8[21]), + .Q(plm_dfm_deframe4_dh_dat[21]), + .CLR(plm_rst) + ); + FDC plm_dfm_deframe4_reg_h_dword_20_ ( + .C(mgt_clk), + .D(plm_dfm_deframe4_reg_h_dword_8[20]), + .Q(plm_dfm_deframe4_dh_dat[20]), + .CLR(plm_rst) + ); + FDC plm_dfm_deframe4_reg_h_dword_19_ ( + .C(mgt_clk), + .D(plm_dfm_deframe4_reg_h_dword_8[19]), + .Q(plm_dfm_deframe4_dh_dat[19]), + .CLR(plm_rst) + ); + FDC plm_dfm_deframe4_reg_h_dword_18_ ( + .C(mgt_clk), + .D(plm_dfm_deframe4_reg_h_dword_8[18]), + .Q(plm_dfm_deframe4_dh_dat[18]), + .CLR(plm_rst) + ); + FDC plm_dfm_deframe4_reg_h_dword_17_ ( + .C(mgt_clk), + .D(plm_dfm_deframe4_reg_h_dword_8[17]), + .Q(plm_dfm_deframe4_dh_dat[17]), + .CLR(plm_rst) + ); + FDC plm_dfm_deframe4_reg_h_dword_16_ ( + .C(mgt_clk), + .D(plm_dfm_deframe4_reg_h_dword_8[16]), + .Q(plm_dfm_deframe4_dh_dat[16]), + .CLR(plm_rst) + ); + FDC plm_dfm_deframe4_reg_h_dword_15_ ( + .C(mgt_clk), + .D(plm_dfm_deframe4_reg_h_dword_8[15]), + .Q(plm_dfm_deframe4_dh_dat[15]), + .CLR(plm_rst) + ); + FDC plm_dfm_deframe4_reg_h_dword_14_ ( + .C(mgt_clk), + .D(plm_dfm_deframe4_reg_h_dword_8[14]), + .Q(plm_dfm_deframe4_dh_dat[14]), + .CLR(plm_rst) + ); + FDC plm_dfm_deframe4_reg_h_dword_13_ ( + .C(mgt_clk), + .D(plm_dfm_deframe4_reg_h_dword_8[13]), + .Q(plm_dfm_deframe4_dh_dat[13]), + .CLR(plm_rst) + ); + FDC plm_dfm_deframe4_reg_h_dword_12_ ( + .C(mgt_clk), + .D(plm_dfm_deframe4_reg_h_dword_8[12]), + .Q(plm_dfm_deframe4_dh_dat[12]), + .CLR(plm_rst) + ); + FDC plm_dfm_deframe4_reg_h_dword_11_ ( + .C(mgt_clk), + .D(plm_dfm_deframe4_reg_h_dword_8[11]), + .Q(plm_dfm_deframe4_dh_dat[11]), + .CLR(plm_rst) + ); + FDC plm_dfm_deframe4_reg_h_dword_10_ ( + .C(mgt_clk), + .D(plm_dfm_deframe4_reg_h_dword_8[10]), + .Q(plm_dfm_deframe4_dh_dat[10]), + .CLR(plm_rst) + ); + FDC plm_dfm_deframe4_reg_h_dword_9_ ( + .C(mgt_clk), + .D(plm_dfm_deframe4_reg_h_dword_8[9]), + .Q(plm_dfm_deframe4_dh_dat[9]), + .CLR(plm_rst) + ); + FDC plm_dfm_deframe4_reg_h_dword_8_ ( + .C(mgt_clk), + .D(plm_dfm_deframe4_reg_h_dword_8[8]), + .Q(plm_dfm_deframe4_dh_dat[8]), + .CLR(plm_rst) + ); + FDC plm_dfm_deframe4_reg_l_dword_5_ ( + .C(mgt_clk), + .D(plm_dfm_deframe4_reg_l_dword_8[5]), + .Q(plm_dfm_deframe4_dl_dat[5]), + .CLR(plm_rst) + ); + FDC plm_dfm_deframe4_reg_l_dword_4_ ( + .C(mgt_clk), + .D(plm_dfm_deframe4_reg_l_dword_8[4]), + .Q(plm_dfm_deframe4_dl_dat[4]), + .CLR(plm_rst) + ); + FDC plm_dfm_deframe4_reg_l_dword_3_ ( + .C(mgt_clk), + .D(plm_dfm_deframe4_reg_l_dword_8[3]), + .Q(plm_dfm_deframe4_dl_dat[3]), + .CLR(plm_rst) + ); + FDC plm_dfm_deframe4_reg_l_dword_2_ ( + .C(mgt_clk), + .D(plm_dfm_deframe4_reg_l_dword_8[2]), + .Q(plm_dfm_deframe4_dl_dat[2]), + .CLR(plm_rst) + ); + FDC plm_dfm_deframe4_reg_l_dword_1_ ( + .C(mgt_clk), + .D(plm_dfm_deframe4_reg_l_dword_8[1]), + .Q(plm_dfm_deframe4_dl_dat[1]), + .CLR(plm_rst) + ); + FDC plm_dfm_deframe4_reg_l_dword_0_ ( + .C(mgt_clk), + .D(plm_dfm_deframe4_reg_l_dword_8[0]), + .Q(plm_dfm_deframe4_dl_dat[0]), + .CLR(plm_rst) + ); + FDC plm_dfm_deframe4_reg_h_dword_31_ ( + .C(mgt_clk), + .D(plm_dfm_deframe4_reg_h_dword_8[31]), + .Q(plm_dfm_deframe4_dh_dat[31]), + .CLR(plm_rst) + ); + FDC plm_dfm_deframe4_reg_h_dword_30_ ( + .C(mgt_clk), + .D(plm_dfm_deframe4_reg_h_dword_8[30]), + .Q(plm_dfm_deframe4_dh_dat[30]), + .CLR(plm_rst) + ); + FDC plm_dfm_deframe4_reg_h_dword_29_ ( + .C(mgt_clk), + .D(plm_dfm_deframe4_reg_h_dword_8[29]), + .Q(plm_dfm_deframe4_dh_dat[29]), + .CLR(plm_rst) + ); + FDC plm_dfm_deframe4_reg_h_dword_28_ ( + .C(mgt_clk), + .D(plm_dfm_deframe4_reg_h_dword_8[28]), + .Q(plm_dfm_deframe4_dh_dat[28]), + .CLR(plm_rst) + ); + FDC plm_dfm_deframe4_reg_h_dword_27_ ( + .C(mgt_clk), + .D(plm_dfm_deframe4_reg_h_dword_8[27]), + .Q(plm_dfm_deframe4_dh_dat[27]), + .CLR(plm_rst) + ); + FDC plm_dfm_deframe4_reg_h_dword_26_ ( + .C(mgt_clk), + .D(plm_dfm_deframe4_reg_h_dword_8[26]), + .Q(plm_dfm_deframe4_dh_dat[26]), + .CLR(plm_rst) + ); + FDC plm_dfm_deframe4_reg_h_dword_25_ ( + .C(mgt_clk), + .D(plm_dfm_deframe4_reg_h_dword_8[25]), + .Q(plm_dfm_deframe4_dh_dat[25]), + .CLR(plm_rst) + ); + FDC plm_dfm_deframe4_reg_h_dword_24_ ( + .C(mgt_clk), + .D(plm_dfm_deframe4_reg_h_dword_8[24]), + .Q(plm_dfm_deframe4_dh_dat[24]), + .CLR(plm_rst) + ); + FDC plm_dfm_deframe4_reg_h_dword_23_ ( + .C(mgt_clk), + .D(plm_dfm_deframe4_reg_h_dword_8[23]), + .Q(plm_dfm_deframe4_dh_dat[23]), + .CLR(plm_rst) + ); + FDC plm_dfm_deframe4_reg_l_dword_20_ ( + .C(mgt_clk), + .D(plm_dfm_deframe4_reg_l_dword_8[20]), + .Q(plm_dfm_deframe4_dl_dat[20]), + .CLR(plm_rst) + ); + FDC plm_dfm_deframe4_reg_l_dword_19_ ( + .C(mgt_clk), + .D(plm_dfm_deframe4_reg_l_dword_8[19]), + .Q(plm_dfm_deframe4_dl_dat[19]), + .CLR(plm_rst) + ); + FDC plm_dfm_deframe4_reg_l_dword_18_ ( + .C(mgt_clk), + .D(plm_dfm_deframe4_reg_l_dword_8[18]), + .Q(plm_dfm_deframe4_dl_dat[18]), + .CLR(plm_rst) + ); + FDC plm_dfm_deframe4_reg_l_dword_17_ ( + .C(mgt_clk), + .D(plm_dfm_deframe4_reg_l_dword_8[17]), + .Q(plm_dfm_deframe4_dl_dat[17]), + .CLR(plm_rst) + ); + FDC plm_dfm_deframe4_reg_l_dword_16_ ( + .C(mgt_clk), + .D(plm_dfm_deframe4_reg_l_dword_8[16]), + .Q(plm_dfm_deframe4_dl_dat[16]), + .CLR(plm_rst) + ); + FDC plm_dfm_deframe4_reg_l_dword_15_ ( + .C(mgt_clk), + .D(plm_dfm_deframe4_reg_l_dword_8[15]), + .Q(plm_dfm_deframe4_dl_dat[15]), + .CLR(plm_rst) + ); + FDC plm_dfm_deframe4_reg_l_dword_14_ ( + .C(mgt_clk), + .D(plm_dfm_deframe4_reg_l_dword_8[14]), + .Q(plm_dfm_deframe4_dl_dat[14]), + .CLR(plm_rst) + ); + FDC plm_dfm_deframe4_reg_l_dword_13_ ( + .C(mgt_clk), + .D(plm_dfm_deframe4_reg_l_dword_8[13]), + .Q(plm_dfm_deframe4_dl_dat[13]), + .CLR(plm_rst) + ); + FDC plm_dfm_deframe4_reg_l_dword_12_ ( + .C(mgt_clk), + .D(plm_dfm_deframe4_reg_l_dword_8[12]), + .Q(plm_dfm_deframe4_dl_dat[12]), + .CLR(plm_rst) + ); + FDC plm_dfm_deframe4_reg_l_dword_11_ ( + .C(mgt_clk), + .D(plm_dfm_deframe4_reg_l_dword_8[11]), + .Q(plm_dfm_deframe4_dl_dat[11]), + .CLR(plm_rst) + ); + FDC plm_dfm_deframe4_reg_l_dword_10_ ( + .C(mgt_clk), + .D(plm_dfm_deframe4_reg_l_dword_8[10]), + .Q(plm_dfm_deframe4_dl_dat[10]), + .CLR(plm_rst) + ); + FDC plm_dfm_deframe4_reg_l_dword_9_ ( + .C(mgt_clk), + .D(plm_dfm_deframe4_reg_l_dword_8[9]), + .Q(plm_dfm_deframe4_dl_dat[9]), + .CLR(plm_rst) + ); + FDC plm_dfm_deframe4_reg_l_dword_8_ ( + .C(mgt_clk), + .D(plm_dfm_deframe4_reg_l_dword_8[8]), + .Q(plm_dfm_deframe4_dl_dat[8]), + .CLR(plm_rst) + ); + FDC plm_dfm_deframe4_reg_l_dword_7_ ( + .C(mgt_clk), + .D(plm_dfm_deframe4_reg_l_dword_8[7]), + .Q(plm_dfm_deframe4_dl_dat[7]), + .CLR(plm_rst) + ); + FDC plm_dfm_deframe4_reg_l_dword_6_ ( + .C(mgt_clk), + .D(plm_dfm_deframe4_reg_l_dword_8[6]), + .Q(plm_dfm_deframe4_dl_dat[6]), + .CLR(plm_rst) + ); + FDP plm_dfm_deframe4_reg_l_edbedg_1_ ( + .PRE(plm_rst), + .C(mgt_clk), + .D(plm_dfm_deframe4_N_85591_i), + .Q(plm_dfm_deframe4_dl_edbedg[1]) + ); + FDP plm_dfm_deframe4_reg_l_edbedg_0_ ( + .PRE(plm_rst), + .C(mgt_clk), + .D(plm_dfm_deframe4_N_85590_i), + .Q(plm_dfm_deframe4_dl_edbedg[0]) + ); + FDP plm_dfm_deframe4_reg_h_edbedg_1_ ( + .PRE(plm_rst), + .C(mgt_clk), + .D(plm_dfm_deframe4_N_85589_i), + .Q(plm_dfm_deframe4_dh_edbedg[1]) + ); + FDP plm_dfm_deframe4_reg_h_edbedg_0_ ( + .PRE(plm_rst), + .C(mgt_clk), + .D(plm_dfm_deframe4_N_85588_i), + .Q(plm_dfm_deframe4_dh_edbedg[0]) + ); + FDC plm_dfm_deframe4_reg_l_dword_31_ ( + .C(mgt_clk), + .D(plm_dfm_deframe4_reg_l_dword_8[31]), + .Q(plm_dfm_deframe4_dl_dat[31]), + .CLR(plm_rst) + ); + FDC plm_dfm_deframe4_reg_l_dword_30_ ( + .C(mgt_clk), + .D(plm_dfm_deframe4_reg_l_dword_8[30]), + .Q(plm_dfm_deframe4_dl_dat[30]), + .CLR(plm_rst) + ); + FDC plm_dfm_deframe4_reg_l_dword_29_ ( + .C(mgt_clk), + .D(plm_dfm_deframe4_reg_l_dword_8[29]), + .Q(plm_dfm_deframe4_dl_dat[29]), + .CLR(plm_rst) + ); + FDC plm_dfm_deframe4_reg_l_dword_28_ ( + .C(mgt_clk), + .D(plm_dfm_deframe4_reg_l_dword_8[28]), + .Q(plm_dfm_deframe4_dl_dat[28]), + .CLR(plm_rst) + ); + FDC plm_dfm_deframe4_reg_l_dword_27_ ( + .C(mgt_clk), + .D(plm_dfm_deframe4_reg_l_dword_8[27]), + .Q(plm_dfm_deframe4_dl_dat[27]), + .CLR(plm_rst) + ); + FDC plm_dfm_deframe4_reg_l_dword_26_ ( + .C(mgt_clk), + .D(plm_dfm_deframe4_reg_l_dword_8[26]), + .Q(plm_dfm_deframe4_dl_dat[26]), + .CLR(plm_rst) + ); + FDC plm_dfm_deframe4_reg_l_dword_25_ ( + .C(mgt_clk), + .D(plm_dfm_deframe4_reg_l_dword_8[25]), + .Q(plm_dfm_deframe4_dl_dat[25]), + .CLR(plm_rst) + ); + FDC plm_dfm_deframe4_reg_l_dword_24_ ( + .C(mgt_clk), + .D(plm_dfm_deframe4_reg_l_dword_8[24]), + .Q(plm_dfm_deframe4_dl_dat[24]), + .CLR(plm_rst) + ); + FDC plm_dfm_deframe4_reg_l_dword_23_ ( + .C(mgt_clk), + .D(plm_dfm_deframe4_reg_l_dword_8[23]), + .Q(plm_dfm_deframe4_dl_dat[23]), + .CLR(plm_rst) + ); + FDC plm_dfm_deframe4_reg_l_dword_22_ ( + .C(mgt_clk), + .D(plm_dfm_deframe4_reg_l_dword_8[22]), + .Q(plm_dfm_deframe4_dl_dat[22]), + .CLR(plm_rst) + ); + FDC plm_dfm_deframe4_reg_l_dword_21_ ( + .C(mgt_clk), + .D(plm_dfm_deframe4_reg_l_dword_8[21]), + .Q(plm_dfm_deframe4_dl_dat[21]), + .CLR(plm_rst) + ); + FDC plm_dfm_deframe4_reg_by4_prel_edbedg_1_ ( + .C(mgt_clk), + .D(plm_dfm_deframe4_lo_edbedg[1]), + .Q(plm_dfm_by4_prel_edbedg[1]), + .CLR(plm_rst) + ); + FDP plm_dfm_deframe4_reg_by4_prel_edbedg_0_ ( + .PRE(plm_rst), + .C(mgt_clk), + .D(plm_dfm_deframe4_lo_edbedg[0]), + .Q(plm_dfm_by4_prel_edbedg[0]) + ); + FDP plm_dfm_deframe4_reg_by4_preh_sdpstp_1_ ( + .PRE(plm_rst), + .C(mgt_clk), + .D(plm_dfm_deframe4_dh_cmd[1]), + .Q(plm_dfm_by4_preh_sdpstp[1]) + ); + FDC plm_dfm_deframe4_reg_by4_preh_sdpstp_0_ ( + .C(mgt_clk), + .D(plm_dfm_deframe4_ho_sdpstp[0]), + .Q(plm_dfm_by4_preh_sdpstp[0]), + .CLR(plm_rst) + ); + FDC plm_dfm_deframe4_reg_df_sdpstp_1_ ( + .C(mgt_clk), + .D(plm_dfm_deframe4_dl_sdpstp[1]), + .Q(plm_dfm_deframe4_reg_df_sdpstp[1]), + .CLR(plm_rst) + ); + FDC plm_dfm_deframe4_reg_df_sdpstp_0_ ( + .C(mgt_clk), + .D(plm_dfm_deframe4_dl_sdpstp[0]), + .Q(plm_dfm_deframe4_reg_df_sdpstp[0]), + .CLR(plm_rst) + ); + FDC plm_dfm_deframe4_reg_df_edbedg_1_ ( + .C(mgt_clk), + .D(plm_dfm_deframe4_dl_edbedg[1]), + .Q(plm_dfm_deframe4_reg_df_edbedg[1]), + .CLR(plm_rst) + ); + FDC plm_dfm_deframe4_reg_df_edbedg_0_ ( + .C(mgt_clk), + .D(plm_dfm_deframe4_dl_edbedg[0]), + .Q(plm_dfm_deframe4_reg_df_edbedg[0]), + .CLR(plm_rst) + ); + FDC plm_dfm_deframe4_reg_df_cmd_1_ ( + .C(mgt_clk), + .D(plm_dfm_deframe4_dl_cmd[1]), + .Q(plm_dfm_by4_prel_sdpstp[1]), + .CLR(plm_rst) + ); + FDC plm_dfm_deframe4_reg_df_cmd_0_ ( + .C(mgt_clk), + .D(plm_dfm_deframe4_dl_cmd[0]), + .Q(plm_dfm_deframe4_reg_df_cmd[0]), + .CLR(plm_rst) + ); + FDC plm_dfm_deframe4_reg_by4_prel_sdpstp_0_ ( + .C(mgt_clk), + .D(plm_dfm_deframe4_lo_sdpstp[0]), + .Q(plm_dfm_by4_prel_sdpstp[0]), + .CLR(plm_rst) + ); + FDC plm_dfm_deframe4_reg_l_sdpstp_1_ ( + .C(mgt_clk), + .D(plm_dfm_deframe4_reg_l_sdpstp_5[1]), + .Q(plm_dfm_deframe4_dl_sdpstp[1]), + .CLR(plm_rst) + ); + FDC plm_dfm_deframe4_reg_l_sdpstp_0_ ( + .C(mgt_clk), + .D(plm_dfm_deframe4_reg_l_sdpstp_5[0]), + .Q(plm_dfm_deframe4_dl_sdpstp[0]), + .CLR(plm_rst) + ); + FDC plm_dfm_deframe4_reg_h_sdpstp_1_ ( + .C(mgt_clk), + .D(plm_dfm_deframe4_reg_h_sdpstp_5[1]), + .Q(plm_dfm_deframe4_dh_sdpstp[1]), + .CLR(plm_rst) + ); + FDC plm_dfm_deframe4_reg_h_sdpstp_0_ ( + .C(mgt_clk), + .D(plm_dfm_deframe4_reg_h_sdpstp_5[0]), + .Q(plm_dfm_deframe4_dh_sdpstp[0]), + .CLR(plm_rst) + ); + FDC plm_dfm_deframe4_reg_df_dat_14_ ( + .C(mgt_clk), + .D(plm_dfm_deframe4_dl_dat[14]), + .Q(plm_dfm_deframe4_reg_df_dat[14]), + .CLR(plm_rst) + ); + FDC plm_dfm_deframe4_reg_df_dat_13_ ( + .C(mgt_clk), + .D(plm_dfm_deframe4_dl_dat[13]), + .Q(plm_dfm_deframe4_reg_df_dat[13]), + .CLR(plm_rst) + ); + FDC plm_dfm_deframe4_reg_df_dat_12_ ( + .C(mgt_clk), + .D(plm_dfm_deframe4_dl_dat[12]), + .Q(plm_dfm_deframe4_reg_df_dat[12]), + .CLR(plm_rst) + ); + FDC plm_dfm_deframe4_reg_df_dat_11_ ( + .C(mgt_clk), + .D(plm_dfm_deframe4_dl_dat[11]), + .Q(plm_dfm_deframe4_reg_df_dat[11]), + .CLR(plm_rst) + ); + FDC plm_dfm_deframe4_reg_df_dat_10_ ( + .C(mgt_clk), + .D(plm_dfm_deframe4_dl_dat[10]), + .Q(plm_dfm_deframe4_reg_df_dat[10]), + .CLR(plm_rst) + ); + FDC plm_dfm_deframe4_reg_df_dat_9_ ( + .C(mgt_clk), + .D(plm_dfm_deframe4_dl_dat[9]), + .Q(plm_dfm_deframe4_reg_df_dat[9]), + .CLR(plm_rst) + ); + FDC plm_dfm_deframe4_reg_df_dat_8_ ( + .C(mgt_clk), + .D(plm_dfm_deframe4_dl_dat[8]), + .Q(plm_dfm_deframe4_reg_df_dat[8]), + .CLR(plm_rst) + ); + FDC plm_dfm_deframe4_reg_df_dat_7_ ( + .C(mgt_clk), + .D(plm_dfm_deframe4_dl_dat[7]), + .Q(plm_dfm_deframe4_reg_df_dat[7]), + .CLR(plm_rst) + ); + FDC plm_dfm_deframe4_reg_df_dat_6_ ( + .C(mgt_clk), + .D(plm_dfm_deframe4_dl_dat[6]), + .Q(plm_dfm_deframe4_reg_df_dat[6]), + .CLR(plm_rst) + ); + FDC plm_dfm_deframe4_reg_df_dat_5_ ( + .C(mgt_clk), + .D(plm_dfm_deframe4_dl_dat[5]), + .Q(plm_dfm_deframe4_reg_df_dat[5]), + .CLR(plm_rst) + ); + FDC plm_dfm_deframe4_reg_df_dat_4_ ( + .C(mgt_clk), + .D(plm_dfm_deframe4_dl_dat[4]), + .Q(plm_dfm_deframe4_reg_df_dat[4]), + .CLR(plm_rst) + ); + FDC plm_dfm_deframe4_reg_df_dat_3_ ( + .C(mgt_clk), + .D(plm_dfm_deframe4_dl_dat[3]), + .Q(plm_dfm_deframe4_reg_df_dat[3]), + .CLR(plm_rst) + ); + FDC plm_dfm_deframe4_reg_df_dat_2_ ( + .C(mgt_clk), + .D(plm_dfm_deframe4_dl_dat[2]), + .Q(plm_dfm_deframe4_reg_df_dat[2]), + .CLR(plm_rst) + ); + FDC plm_dfm_deframe4_reg_df_dat_1_ ( + .C(mgt_clk), + .D(plm_dfm_deframe4_dl_dat[1]), + .Q(plm_dfm_deframe4_reg_df_dat[1]), + .CLR(plm_rst) + ); + FDC plm_dfm_deframe4_reg_df_dat_0_ ( + .C(mgt_clk), + .D(plm_dfm_deframe4_dl_dat[0]), + .Q(plm_dfm_deframe4_reg_df_dat[0]), + .CLR(plm_rst) + ); + FDC plm_dfm_deframe4_reg_df_dat_29_ ( + .C(mgt_clk), + .D(plm_dfm_deframe4_dl_dat[29]), + .Q(plm_dfm_deframe4_reg_df_dat[29]), + .CLR(plm_rst) + ); + FDC plm_dfm_deframe4_reg_df_dat_28_ ( + .C(mgt_clk), + .D(plm_dfm_deframe4_dl_dat[28]), + .Q(plm_dfm_deframe4_reg_df_dat[28]), + .CLR(plm_rst) + ); + FDC plm_dfm_deframe4_reg_df_dat_27_ ( + .C(mgt_clk), + .D(plm_dfm_deframe4_dl_dat[27]), + .Q(plm_dfm_deframe4_reg_df_dat[27]), + .CLR(plm_rst) + ); + FDC plm_dfm_deframe4_reg_df_dat_26_ ( + .C(mgt_clk), + .D(plm_dfm_deframe4_dl_dat[26]), + .Q(plm_dfm_deframe4_reg_df_dat[26]), + .CLR(plm_rst) + ); + FDC plm_dfm_deframe4_reg_df_dat_25_ ( + .C(mgt_clk), + .D(plm_dfm_deframe4_dl_dat[25]), + .Q(plm_dfm_deframe4_reg_df_dat[25]), + .CLR(plm_rst) + ); + FDC plm_dfm_deframe4_reg_df_dat_24_ ( + .C(mgt_clk), + .D(plm_dfm_deframe4_dl_dat[24]), + .Q(plm_dfm_deframe4_reg_df_dat[24]), + .CLR(plm_rst) + ); + FDC plm_dfm_deframe4_reg_df_dat_23_ ( + .C(mgt_clk), + .D(plm_dfm_deframe4_dl_dat[23]), + .Q(plm_dfm_deframe4_reg_df_dat[23]), + .CLR(plm_rst) + ); + FDC plm_dfm_deframe4_reg_df_dat_22_ ( + .C(mgt_clk), + .D(plm_dfm_deframe4_dl_dat[22]), + .Q(plm_dfm_deframe4_reg_df_dat[22]), + .CLR(plm_rst) + ); + FDC plm_dfm_deframe4_reg_df_dat_21_ ( + .C(mgt_clk), + .D(plm_dfm_deframe4_dl_dat[21]), + .Q(plm_dfm_deframe4_reg_df_dat[21]), + .CLR(plm_rst) + ); + FDC plm_dfm_deframe4_reg_df_dat_20_ ( + .C(mgt_clk), + .D(plm_dfm_deframe4_dl_dat[20]), + .Q(plm_dfm_deframe4_reg_df_dat[20]), + .CLR(plm_rst) + ); + FDC plm_dfm_deframe4_reg_df_dat_19_ ( + .C(mgt_clk), + .D(plm_dfm_deframe4_dl_dat[19]), + .Q(plm_dfm_deframe4_reg_df_dat[19]), + .CLR(plm_rst) + ); + FDC plm_dfm_deframe4_reg_df_dat_18_ ( + .C(mgt_clk), + .D(plm_dfm_deframe4_dl_dat[18]), + .Q(plm_dfm_deframe4_reg_df_dat[18]), + .CLR(plm_rst) + ); + FDC plm_dfm_deframe4_reg_df_dat_17_ ( + .C(mgt_clk), + .D(plm_dfm_deframe4_dl_dat[17]), + .Q(plm_dfm_deframe4_reg_df_dat[17]), + .CLR(plm_rst) + ); + FDC plm_dfm_deframe4_reg_df_dat_16_ ( + .C(mgt_clk), + .D(plm_dfm_deframe4_dl_dat[16]), + .Q(plm_dfm_deframe4_reg_df_dat[16]), + .CLR(plm_rst) + ); + FDC plm_dfm_deframe4_reg_df_dat_15_ ( + .C(mgt_clk), + .D(plm_dfm_deframe4_dl_dat[15]), + .Q(plm_dfm_deframe4_reg_df_dat[15]), + .CLR(plm_rst) + ); + FDC plm_dfm_deframe4_reg_by4_preh_out_12_ ( + .C(mgt_clk), + .D(plm_dfm_deframe4_N_9810_i), + .Q(plm_dfm_by4_preh_out[12]), + .CLR(plm_rst) + ); + FDC plm_dfm_deframe4_reg_by4_preh_out_11_ ( + .C(mgt_clk), + .D(plm_dfm_deframe4_N_9811_i), + .Q(plm_dfm_by4_preh_out[11]), + .CLR(plm_rst) + ); + FDC plm_dfm_deframe4_reg_by4_preh_out_10_ ( + .C(mgt_clk), + .D(plm_dfm_deframe4_N_9812_i), + .Q(plm_dfm_by4_preh_out[10]), + .CLR(plm_rst) + ); + FDC plm_dfm_deframe4_reg_by4_preh_out_9_ ( + .C(mgt_clk), + .D(plm_dfm_deframe4_N_9813_i), + .Q(plm_dfm_by4_preh_out[9]), + .CLR(plm_rst) + ); + FDC plm_dfm_deframe4_reg_by4_preh_out_8_ ( + .C(mgt_clk), + .D(plm_dfm_deframe4_N_9814_i), + .Q(plm_dfm_by4_preh_out[8]), + .CLR(plm_rst) + ); + FDC plm_dfm_deframe4_reg_by4_preh_out_7_ ( + .C(mgt_clk), + .D(plm_dfm_deframe4_N_9815_i), + .Q(plm_dfm_by4_preh_out[7]), + .CLR(plm_rst) + ); + FDC plm_dfm_deframe4_reg_by4_preh_out_6_ ( + .C(mgt_clk), + .D(plm_dfm_deframe4_N_9816_i), + .Q(plm_dfm_by4_preh_out[6]), + .CLR(plm_rst) + ); + FDC plm_dfm_deframe4_reg_by4_preh_out_5_ ( + .C(mgt_clk), + .D(plm_dfm_deframe4_N_9817_i), + .Q(plm_dfm_by4_preh_out[5]), + .CLR(plm_rst) + ); + FDC plm_dfm_deframe4_reg_by4_preh_out_4_ ( + .C(mgt_clk), + .D(plm_dfm_deframe4_N_9818_i), + .Q(plm_dfm_by4_preh_out[4]), + .CLR(plm_rst) + ); + FDC plm_dfm_deframe4_reg_by4_preh_out_3_ ( + .C(mgt_clk), + .D(plm_dfm_deframe4_N_9819_i), + .Q(plm_dfm_by4_preh_out[3]), + .CLR(plm_rst) + ); + FDC plm_dfm_deframe4_reg_by4_preh_out_2_ ( + .C(mgt_clk), + .D(plm_dfm_deframe4_N_9820_i), + .Q(plm_dfm_by4_preh_out[2]), + .CLR(plm_rst) + ); + FDC plm_dfm_deframe4_reg_by4_preh_out_1_ ( + .C(mgt_clk), + .D(plm_dfm_deframe4_N_9821_i), + .Q(plm_dfm_by4_preh_out[1]), + .CLR(plm_rst) + ); + FDC plm_dfm_deframe4_reg_by4_preh_out_0_ ( + .C(mgt_clk), + .D(plm_dfm_deframe4_N_9822_i), + .Q(plm_dfm_by4_preh_out[0]), + .CLR(plm_rst) + ); + FDC plm_dfm_deframe4_reg_df_dat_31_ ( + .C(mgt_clk), + .D(plm_dfm_deframe4_dl_dat[31]), + .Q(plm_dfm_deframe4_reg_df_dat[31]), + .CLR(plm_rst) + ); + FDC plm_dfm_deframe4_reg_df_dat_30_ ( + .C(mgt_clk), + .D(plm_dfm_deframe4_dl_dat[30]), + .Q(plm_dfm_deframe4_reg_df_dat[30]), + .CLR(plm_rst) + ); + FDP plm_dfm_deframe4_reg_by4_preh_out_27_ ( + .PRE(plm_rst), + .C(mgt_clk), + .D(plm_dfm_deframe4_N_9795_i), + .Q(plm_dfm_by4_preh_out[27]) + ); + FDP plm_dfm_deframe4_reg_by4_preh_out_26_ ( + .PRE(plm_rst), + .C(mgt_clk), + .D(plm_dfm_deframe4_N_9796_i), + .Q(plm_dfm_by4_preh_out[26]) + ); + FDP plm_dfm_deframe4_reg_by4_preh_out_25_ ( + .PRE(plm_rst), + .C(mgt_clk), + .D(plm_dfm_deframe4_N_9797_i), + .Q(plm_dfm_by4_preh_out[25]) + ); + FDP plm_dfm_deframe4_reg_by4_preh_out_24_ ( + .PRE(plm_rst), + .C(mgt_clk), + .D(plm_dfm_deframe4_N_9798_i), + .Q(plm_dfm_by4_preh_out[24]) + ); + FDC plm_dfm_deframe4_reg_by4_preh_out_23_ ( + .C(mgt_clk), + .D(plm_dfm_deframe4_N_9799_i), + .Q(plm_dfm_by4_preh_out[23]), + .CLR(plm_rst) + ); + FDC plm_dfm_deframe4_reg_by4_preh_out_22_ ( + .C(mgt_clk), + .D(plm_dfm_deframe4_N_9800_i), + .Q(plm_dfm_by4_preh_out[22]), + .CLR(plm_rst) + ); + FDC plm_dfm_deframe4_reg_by4_preh_out_21_ ( + .C(mgt_clk), + .D(plm_dfm_deframe4_N_9801_i), + .Q(plm_dfm_by4_preh_out[21]), + .CLR(plm_rst) + ); + FDC plm_dfm_deframe4_reg_by4_preh_out_20_ ( + .C(mgt_clk), + .D(plm_dfm_deframe4_N_9802_i), + .Q(plm_dfm_by4_preh_out[20]), + .CLR(plm_rst) + ); + FDC plm_dfm_deframe4_reg_by4_preh_out_19_ ( + .C(mgt_clk), + .D(plm_dfm_deframe4_N_9803_i), + .Q(plm_dfm_by4_preh_out[19]), + .CLR(plm_rst) + ); + FDC plm_dfm_deframe4_reg_by4_preh_out_18_ ( + .C(mgt_clk), + .D(plm_dfm_deframe4_N_9804_i), + .Q(plm_dfm_by4_preh_out[18]), + .CLR(plm_rst) + ); + FDC plm_dfm_deframe4_reg_by4_preh_out_17_ ( + .C(mgt_clk), + .D(plm_dfm_deframe4_N_9805_i), + .Q(plm_dfm_by4_preh_out[17]), + .CLR(plm_rst) + ); + FDC plm_dfm_deframe4_reg_by4_preh_out_16_ ( + .C(mgt_clk), + .D(plm_dfm_deframe4_N_9806_i), + .Q(plm_dfm_by4_preh_out[16]), + .CLR(plm_rst) + ); + FDC plm_dfm_deframe4_reg_by4_preh_out_15_ ( + .C(mgt_clk), + .D(plm_dfm_deframe4_N_9807_i), + .Q(plm_dfm_by4_preh_out[15]), + .CLR(plm_rst) + ); + FDC plm_dfm_deframe4_reg_by4_preh_out_14_ ( + .C(mgt_clk), + .D(plm_dfm_deframe4_N_9808_i), + .Q(plm_dfm_by4_preh_out[14]), + .CLR(plm_rst) + ); + FDC plm_dfm_deframe4_reg_by4_preh_out_13_ ( + .C(mgt_clk), + .D(plm_dfm_deframe4_N_9809_i), + .Q(plm_dfm_by4_preh_out[13]), + .CLR(plm_rst) + ); + FDC plm_dfm_deframe4_reg_by4_prel_out_10_ ( + .C(mgt_clk), + .D(plm_dfm_deframe4_N_9845_i), + .Q(plm_dfm_by4_prel_out[10]), + .CLR(plm_rst) + ); + FDC plm_dfm_deframe4_reg_by4_prel_out_9_ ( + .C(mgt_clk), + .D(plm_dfm_deframe4_N_9846_i), + .Q(plm_dfm_by4_prel_out[9]), + .CLR(plm_rst) + ); + FDC plm_dfm_deframe4_reg_by4_prel_out_8_ ( + .C(mgt_clk), + .D(plm_dfm_deframe4_N_9847_i), + .Q(plm_dfm_by4_prel_out[8]), + .CLR(plm_rst) + ); + FDP plm_dfm_deframe4_reg_by4_prel_out_7_ ( + .PRE(plm_rst), + .C(mgt_clk), + .D(plm_dfm_deframe4_N_9848_i), + .Q(plm_dfm_by4_prel_out[7]) + ); + FDP plm_dfm_deframe4_reg_by4_prel_out_6_ ( + .PRE(plm_rst), + .C(mgt_clk), + .D(plm_dfm_deframe4_N_9849_i), + .Q(plm_dfm_by4_prel_out[6]) + ); + FDP plm_dfm_deframe4_reg_by4_prel_out_5_ ( + .PRE(plm_rst), + .C(mgt_clk), + .D(plm_dfm_deframe4_N_9850_i), + .Q(plm_dfm_by4_prel_out[5]) + ); + FDP plm_dfm_deframe4_reg_by4_prel_out_4_ ( + .PRE(plm_rst), + .C(mgt_clk), + .D(plm_dfm_deframe4_N_9851_i), + .Q(plm_dfm_by4_prel_out[4]) + ); + FDP plm_dfm_deframe4_reg_by4_prel_out_3_ ( + .PRE(plm_rst), + .C(mgt_clk), + .D(plm_dfm_deframe4_N_9852_i), + .Q(plm_dfm_by4_prel_out[3]) + ); + FDP plm_dfm_deframe4_reg_by4_prel_out_2_ ( + .PRE(plm_rst), + .C(mgt_clk), + .D(plm_dfm_deframe4_N_9853_i), + .Q(plm_dfm_by4_prel_out[2]) + ); + FDP plm_dfm_deframe4_reg_by4_prel_out_1_ ( + .PRE(plm_rst), + .C(mgt_clk), + .D(plm_dfm_deframe4_N_9854_i), + .Q(plm_dfm_by4_prel_out[1]) + ); + FDP plm_dfm_deframe4_reg_by4_prel_out_0_ ( + .PRE(plm_rst), + .C(mgt_clk), + .D(plm_dfm_deframe4_N_9855_i), + .Q(plm_dfm_by4_prel_out[0]) + ); + FDP plm_dfm_deframe4_reg_by4_preh_out_31_ ( + .PRE(plm_rst), + .C(mgt_clk), + .D(plm_dfm_deframe4_N_9791_i), + .Q(plm_dfm_by4_preh_out[31]) + ); + FDP plm_dfm_deframe4_reg_by4_preh_out_30_ ( + .PRE(plm_rst), + .C(mgt_clk), + .D(plm_dfm_deframe4_N_9792_i), + .Q(plm_dfm_by4_preh_out[30]) + ); + FDP plm_dfm_deframe4_reg_by4_preh_out_29_ ( + .PRE(plm_rst), + .C(mgt_clk), + .D(plm_dfm_deframe4_N_9793_i), + .Q(plm_dfm_by4_preh_out[29]) + ); + FDP plm_dfm_deframe4_reg_by4_preh_out_28_ ( + .PRE(plm_rst), + .C(mgt_clk), + .D(plm_dfm_deframe4_N_9794_i), + .Q(plm_dfm_by4_preh_out[28]) + ); + FDC plm_dfm_deframe4_reg_by4_prel_out_25_ ( + .C(mgt_clk), + .D(plm_dfm_deframe4_N_9830_i), + .Q(plm_dfm_by4_prel_out[25]), + .CLR(plm_rst) + ); + FDC plm_dfm_deframe4_reg_by4_prel_out_24_ ( + .C(mgt_clk), + .D(plm_dfm_deframe4_N_9831_i), + .Q(plm_dfm_by4_prel_out[24]), + .CLR(plm_rst) + ); + FDC plm_dfm_deframe4_reg_by4_prel_out_23_ ( + .C(mgt_clk), + .D(plm_dfm_deframe4_N_9832_i), + .Q(plm_dfm_by4_prel_out[23]), + .CLR(plm_rst) + ); + FDC plm_dfm_deframe4_reg_by4_prel_out_22_ ( + .C(mgt_clk), + .D(plm_dfm_deframe4_N_9833_i), + .Q(plm_dfm_by4_prel_out[22]), + .CLR(plm_rst) + ); + FDC plm_dfm_deframe4_reg_by4_prel_out_21_ ( + .C(mgt_clk), + .D(plm_dfm_deframe4_N_9834_i), + .Q(plm_dfm_by4_prel_out[21]), + .CLR(plm_rst) + ); + FDC plm_dfm_deframe4_reg_by4_prel_out_20_ ( + .C(mgt_clk), + .D(plm_dfm_deframe4_N_9835_i), + .Q(plm_dfm_by4_prel_out[20]), + .CLR(plm_rst) + ); + FDC plm_dfm_deframe4_reg_by4_prel_out_19_ ( + .C(mgt_clk), + .D(plm_dfm_deframe4_N_9836_i), + .Q(plm_dfm_by4_prel_out[19]), + .CLR(plm_rst) + ); + FDC plm_dfm_deframe4_reg_by4_prel_out_18_ ( + .C(mgt_clk), + .D(plm_dfm_deframe4_N_9837_i), + .Q(plm_dfm_by4_prel_out[18]), + .CLR(plm_rst) + ); + FDC plm_dfm_deframe4_reg_by4_prel_out_17_ ( + .C(mgt_clk), + .D(plm_dfm_deframe4_N_9838_i), + .Q(plm_dfm_by4_prel_out[17]), + .CLR(plm_rst) + ); + FDC plm_dfm_deframe4_reg_by4_prel_out_16_ ( + .C(mgt_clk), + .D(plm_dfm_deframe4_N_9839_i), + .Q(plm_dfm_by4_prel_out[16]), + .CLR(plm_rst) + ); + FDC plm_dfm_deframe4_reg_by4_prel_out_15_ ( + .C(mgt_clk), + .D(plm_dfm_deframe4_N_9840_i), + .Q(plm_dfm_by4_prel_out[15]), + .CLR(plm_rst) + ); + FDC plm_dfm_deframe4_reg_by4_prel_out_14_ ( + .C(mgt_clk), + .D(plm_dfm_deframe4_N_9841_i), + .Q(plm_dfm_by4_prel_out[14]), + .CLR(plm_rst) + ); + FDC plm_dfm_deframe4_reg_by4_prel_out_13_ ( + .C(mgt_clk), + .D(plm_dfm_deframe4_N_9842_i), + .Q(plm_dfm_by4_prel_out[13]), + .CLR(plm_rst) + ); + FDC plm_dfm_deframe4_reg_by4_prel_out_12_ ( + .C(mgt_clk), + .D(plm_dfm_deframe4_N_9843_i), + .Q(plm_dfm_by4_prel_out[12]), + .CLR(plm_rst) + ); + FDC plm_dfm_deframe4_reg_by4_prel_out_11_ ( + .C(mgt_clk), + .D(plm_dfm_deframe4_N_9844_i), + .Q(plm_dfm_by4_prel_out[11]), + .CLR(plm_rst) + ); + FDC plm_dfm_deframe4_reg_by4_preh_edbedg_1_ ( + .C(mgt_clk), + .D(plm_dfm_deframe4_ho_edbedg[1]), + .Q(plm_dfm_by4_preh_edbedg[1]), + .CLR(plm_rst) + ); + FDC plm_dfm_deframe4_reg_by4_preh_edbedg_0_ ( + .C(mgt_clk), + .D(plm_dfm_deframe4_ho_edbedg[0]), + .Q(plm_dfm_by4_preh_edbedg[0]), + .CLR(plm_rst) + ); + FDC plm_dfm_deframe4_reg_by4_prel_out_31_ ( + .C(mgt_clk), + .D(plm_dfm_deframe4_N_9824_i), + .Q(plm_dfm_by4_prel_out[31]), + .CLR(plm_rst) + ); + FDC plm_dfm_deframe4_reg_by4_prel_out_30_ ( + .C(mgt_clk), + .D(plm_dfm_deframe4_N_9825_i), + .Q(plm_dfm_by4_prel_out[30]), + .CLR(plm_rst) + ); + FDC plm_dfm_deframe4_reg_by4_prel_out_29_ ( + .C(mgt_clk), + .D(plm_dfm_deframe4_N_9826_i), + .Q(plm_dfm_by4_prel_out[29]), + .CLR(plm_rst) + ); + FDC plm_dfm_deframe4_reg_by4_prel_out_28_ ( + .C(mgt_clk), + .D(plm_dfm_deframe4_N_9827_i), + .Q(plm_dfm_by4_prel_out[28]), + .CLR(plm_rst) + ); + FDC plm_dfm_deframe4_reg_by4_prel_out_27_ ( + .C(mgt_clk), + .D(plm_dfm_deframe4_N_9828_i), + .Q(plm_dfm_by4_prel_out[27]), + .CLR(plm_rst) + ); + FDC plm_dfm_deframe4_reg_by4_prel_out_26_ ( + .C(mgt_clk), + .D(plm_dfm_deframe4_N_9829_i), + .Q(plm_dfm_by4_prel_out[26]), + .CLR(plm_rst) + ); + defparam plm_dfm_deframe4_frm4hi_half_reg_o_edbedg_cnst_0_a2_0_o2_0_.INIT = 4'h1; + LUT2 plm_dfm_deframe4_frm4hi_half_reg_o_edbedg_cnst_0_a2_0_o2_0_ ( + .I0(plm_dfm_by4_prel_sdpstp[1]), + .I1(plm_dfm_deframe4_reg_df_cmd[0]), + .O(plm_dfm_deframe4_frm4hi_half_N_14418_i) + ); + defparam plm_dfm_deframe4_frm4hi_half_half_framer_un1_reg_o_edbedg16_0_o2.INIT = 4'h1; + LUT2 plm_dfm_deframe4_frm4hi_half_half_framer_un1_reg_o_edbedg16_0_o2 ( + .I0(plm_dfm_deframe4_reg_df_edbedg[0]), + .I1(plm_dfm_deframe4_reg_df_edbedg[1]), + .O(plm_dfm_deframe4_frm4hi_half_N_14411_i) + ); + defparam plm_dfm_deframe4_frm4hi_half_half_framer_reg_o_edbedg68_0_a4.INIT = 4'h4; + LUT2 plm_dfm_deframe4_frm4hi_half_half_framer_reg_o_edbedg68_0_a4 ( + .I0(plm_dfm_by4_prel_sdpstp[1]), + .I1(plm_dfm_deframe4_reg_df_cmd[0]), + .O(plm_dfm_deframe4_frm4hi_half_reg_o_edbedg68) + ); + defparam plm_dfm_deframe4_frm4hi_half_do_cmd_sn_m4_i_0_a2.INIT = 4'h8; + LUT2 plm_dfm_deframe4_frm4hi_half_do_cmd_sn_m4_i_0_a2 ( + .I0(plm_dfm_deframe4_reg_df_sdpstp[1]), + .I1(plm_dfm_deframe4_reg_df_valid_1565), + .O(plm_dfm_deframe4_frm4hi_half_N_14422) + ); + defparam plm_dfm_deframe4_frm4hi_half_half_framer_reg_o_edbedg70.INIT = 4'h2; + LUT2 plm_dfm_deframe4_frm4hi_half_half_framer_reg_o_edbedg70 ( + .I0(plm_dfm_by4_prel_sdpstp[1]), + .I1(plm_dfm_deframe4_reg_df_cmd[0]), + .O(plm_dfm_deframe4_frm4hi_half_reg_o_edbedg70) + ); + defparam plm_dfm_deframe4_frm4hi_half_half_framer_reg_o_edbedg10.INIT = 16'h0010; + LUT4 plm_dfm_deframe4_frm4hi_half_half_framer_reg_o_edbedg10 ( + .I0(plm_dfm_deframe4_dh_edbedg[0]), + .I1(plm_dfm_deframe4_dh_edbedg[1]), + .I2(plm_dfm_deframe4_dh_sdpstp[0]), + .I3(plm_dfm_deframe4_dh_sdpstp[1]), + .O(plm_dfm_deframe4_reg_o_edbedg15) + ); + defparam plm_dfm_deframe4_frm4hi_half_half_framer_reg_o_edbedg11.INIT = 16'h0100; + LUT4 plm_dfm_deframe4_frm4hi_half_half_framer_reg_o_edbedg11 ( + .I0(plm_dfm_deframe4_dh_edbedg[0]), + .I1(plm_dfm_deframe4_dh_edbedg[1]), + .I2(plm_dfm_deframe4_dh_sdpstp[0]), + .I3(plm_dfm_deframe4_dh_sdpstp[1]), + .O(plm_dfm_deframe4_reg_o_edbedg16) + ); + defparam plm_dfm_deframe4_frm4hi_half_un1_di_valid_m.INIT = 8'h06; + LUT3 plm_dfm_deframe4_frm4hi_half_un1_di_valid_m ( + .I0(plm_dfm_by4_prel_sdpstp[1]), + .I1(plm_dfm_deframe4_reg_df_cmd[0]), + .I2(plm_dfm_deframe4_reg_df_valid_1565), + .O(plm_dfm_deframe4_frm4hi_half_un1_di_valid_m_1568) + ); + defparam plm_dfm_deframe4_frm4hi_half_reg_o_edbedg_2_sqmuxa_1.INIT = 16'h0010; + LUT4_L plm_dfm_deframe4_frm4hi_half_reg_o_edbedg_2_sqmuxa_1 ( + .I0(plm_dfm_deframe4_dh_sdpstp[0]), + .I1(plm_dfm_deframe4_dh_sdpstp[1]), + .I2(plm_dfm_deframe4_frm4hi_half_reg_o_edbedg68), + .I3(plm_dfm_deframe4_reg_df_valid_1565), + .LO(plm_dfm_deframe4_frm4hi_half_reg_o_edbedg_2_sqmuxa_1_1567) + ); + defparam plm_dfm_deframe4_frm4hi_half_reg_o_edbedg_cnst_0_a2_0_a2_0_.INIT = 16'h2800; + LUT4 plm_dfm_deframe4_frm4hi_half_reg_o_edbedg_cnst_0_a2_0_a2_0_ ( + .I0(plm_dfm_deframe4_frm4hi_half_N_14411_i), + .I1(plm_dfm_deframe4_reg_df_sdpstp[0]), + .I2(plm_dfm_deframe4_reg_df_sdpstp[1]), + .I3(plm_dfm_deframe4_reg_df_valid_1565), + .O(plm_dfm_deframe4_frm4hi_half_N_14421) + ); + defparam plm_dfm_deframe4_frm4hi_half_reg_o_edbedg_1_sqmuxa_1.INIT = 16'h0200; + LUT4 plm_dfm_deframe4_frm4hi_half_reg_o_edbedg_1_sqmuxa_1 ( + .I0(plm_dfm_deframe4_frm4hi_half_reg_o_edbedg68), + .I1(plm_dfm_deframe4_reg_df_sdpstp[0]), + .I2(plm_dfm_deframe4_reg_df_sdpstp[1]), + .I3(plm_dfm_deframe4_reg_df_valid_1565), + .O(plm_dfm_deframe4_frm4hi_half_reg_o_edbedg_1_sqmuxa_1_1569) + ); + defparam plm_dfm_deframe4_frm4hi_half_do_cmd_sn_m4_i_0_1.INIT = 16'h2888; + LUT4 plm_dfm_deframe4_frm4hi_half_do_cmd_sn_m4_i_0_1 ( + .I0(plm_dfm_deframe4_frm4hi_half_m4_i_0_0), + .I1(plm_dfm_deframe4_reg_df_cmd[0]), + .I2(plm_dfm_deframe4_reg_df_sdpstp[0]), + .I3(plm_dfm_deframe4_reg_df_valid_1565), + .O(plm_dfm_deframe4_frm4hi_half_m4_i_0_1) + ); + defparam plm_dfm_deframe4_frm4hi_half_do_cmd_sn_m4_i_0_m2_0.INIT = 8'h53; + LUT3 plm_dfm_deframe4_frm4hi_half_do_cmd_sn_m4_i_0_m2_0 ( + .I0(plm_dfm_deframe4_frm4hi_half_N_14411_i), + .I1(plm_dfm_deframe4_N_14414_i), + .I2(plm_dfm_deframe4_reg_df_valid_1565), + .O(plm_dfm_deframe4_frm4hi_half_N_14419) + ); + defparam plm_dfm_deframe4_frm4hi_half_un1_reg_o_edbedg_2_sqmuxa.INIT = 16'h0F07; + LUT4 plm_dfm_deframe4_frm4hi_half_un1_reg_o_edbedg_2_sqmuxa ( + .I0(plm_dfm_deframe4_dh_edbedg[0]), + .I1(plm_dfm_deframe4_frm4hi_half_reg_o_edbedg70), + .I2(plm_dfm_deframe4_frm4hi_half_reg_o_edbedg_2_sqmuxa_1_1567), + .I3(plm_dfm_deframe4_reg_df_valid_1565), + .O(plm_dfm_deframe4_frm4hi_half_N_11343) + ); + defparam plm_dfm_deframe4_frm4hi_half_un1_reg_o_edbedg_0_sqmuxa_1.INIT = 16'hC1FD; + LUT4 plm_dfm_deframe4_frm4hi_half_un1_reg_o_edbedg_0_sqmuxa_1 ( + .I0(plm_dfm_deframe4_frm4hi_half_N_14421), + .I1(plm_dfm_by4_prel_sdpstp[1]), + .I2(plm_dfm_deframe4_reg_df_cmd[0]), + .I3(plm_dfm_deframe4_reg_df_valid_1565), + .O(plm_dfm_deframe4_N_11342) + ); + defparam plm_dfm_deframe4_frm4hi_half_reg_o_dat_1_sqmuxa_1.INIT = 8'h08; + LUT3 plm_dfm_deframe4_frm4hi_half_reg_o_dat_1_sqmuxa_1 ( + .I0(plm_dfm_deframe4_N_11335), + .I1(plm_dfm_deframe4_frm4hi_half_N_14418_i), + .I2(plm_dfm_deframe4_frm4hi_half_N_14421), + .O(plm_dfm_deframe4_reg_o_dat_1_sqmuxa_1) + ); + defparam plm_dfm_deframe4_frm4hi_half_do_valid_iv.INIT = 8'h0D; + LUT3 plm_dfm_deframe4_frm4hi_half_do_valid_iv ( + .I0(plm_dfm_deframe4_frm4hi_half_N_14418_i), + .I1(plm_dfm_deframe4_frm4hi_half_N_14421), + .I2(plm_dfm_deframe4_frm4hi_half_un1_di_valid_m_1568), + .O(plm_dfm_deframe4_dh_valid) + ); + defparam plm_dfm_deframe4_frm4hi_half_o_edbedg_sn_m1_39370.INIT = 16'h2AAA; + LUT4_L plm_dfm_deframe4_frm4hi_half_o_edbedg_sn_m1_39370 ( + .I0(plm_dfm_deframe4_frm4hi_half_N_11343), + .I1(plm_dfm_deframe4_frm4hi_half_reg_o_edbedg70), + .I2(plm_dfm_deframe4_reg_df_edbedg[0]), + .I3(plm_dfm_deframe4_reg_df_valid_1565), + .LO(plm_dfm_deframe4_frm4hi_half_o_edbedg_sn_m1_39370_1570) + ); + defparam plm_dfm_deframe4_frm4hi_half_do_cmds2.INIT = 16'h4C5F; + LUT4 plm_dfm_deframe4_frm4hi_half_do_cmds2 ( + .I0(plm_dfm_deframe4_frm4hi_half_N_14418_i), + .I1(plm_dfm_deframe4_frm4hi_half_N_14419), + .I2(plm_dfm_deframe4_frm4hi_half_N_14421), + .I3(plm_dfm_deframe4_frm4hi_half_m4_i_0_1), + .O(plm_dfm_deframe4_frm4hi_half_N_10101) + ); + defparam plm_dfm_deframe4_frm4hi_half_un1_reg_o_dat_1_sqmuxa.INIT = 16'h00FB; + LUT4 plm_dfm_deframe4_frm4hi_half_un1_reg_o_dat_1_sqmuxa ( + .I0(plm_dfm_deframe4_N_11335), + .I1(plm_dfm_deframe4_frm4hi_half_N_14418_i), + .I2(plm_dfm_deframe4_frm4hi_half_N_14421), + .I3(plm_dfm_deframe4_frm4hi_half_un1_di_valid_m_1568), + .O(plm_dfm_deframe4_frm4hi_half_N_11340) + ); + defparam plm_dfm_deframe4_frm4hi_half_do_cmd_0_0_.INIT = 16'h058D; + LUT4 plm_dfm_deframe4_frm4hi_half_do_cmd_0_0_ ( + .I0(plm_dfm_deframe4_frm4hi_half_N_10101), + .I1(plm_dfm_deframe4_frm4hi_half_N_14418_i), + .I2(plm_dfm_deframe4_frm4hi_half_N_14422), + .I3(plm_dfm_deframe4_reg_o_edbedg16), + .O(plm_dfm_deframe4_dh_cmd[0]) + ); + defparam plm_dfm_deframe4_frm4hi_half_do_cmd_0_1_.INIT = 16'h50D8; + LUT4 plm_dfm_deframe4_frm4hi_half_do_cmd_0_1_ ( + .I0(plm_dfm_deframe4_frm4hi_half_N_10101), + .I1(plm_dfm_deframe4_frm4hi_half_N_14418_i), + .I2(plm_dfm_deframe4_frm4hi_half_N_14422), + .I3(plm_dfm_deframe4_reg_o_edbedg15), + .O(plm_dfm_deframe4_dh_cmd[1]) + ); + defparam plm_dfm_deframe4_frm4hi_half_o_edbedg_sn_m1.INIT = 16'h0070; + LUT4 plm_dfm_deframe4_frm4hi_half_o_edbedg_sn_m1 ( + .I0(plm_dfm_deframe4_frm4hi_half_N_14418_i), + .I1(plm_dfm_deframe4_frm4hi_half_N_14421), + .I2(plm_dfm_deframe4_frm4hi_half_o_edbedg_sn_m1_39370_1570), + .I3(plm_dfm_deframe4_frm4hi_half_reg_o_edbedg_1_sqmuxa_1_1569), + .O(plm_dfm_deframe4_frm4hi_half_o_edbedg_sn_N_2) + ); + defparam plm_dfm_deframe4_frm4hi_half_o_dat_iv_0_1_.INIT = 16'h2A3F; + LUT4_L plm_dfm_deframe4_frm4hi_half_o_dat_iv_0_1_ ( + .I0(plm_dfm_deframe4_N_11342), + .I1(plm_dfm_by4_prel_sdpstp[1]), + .I2(plm_dfm_deframe4_reg_df_cmd[0]), + .I3(plm_dfm_deframe4_reg_df_dat[1]), + .LO(plm_dfm_deframe4_frm4hi_half_o_dat_iv_0[1]) + ); + defparam plm_dfm_deframe4_frm4hi_half_o_dat_iv_0_3_.INIT = 16'h2A3F; + LUT4_L plm_dfm_deframe4_frm4hi_half_o_dat_iv_0_3_ ( + .I0(plm_dfm_deframe4_N_11342), + .I1(plm_dfm_by4_prel_sdpstp[1]), + .I2(plm_dfm_deframe4_reg_df_cmd[0]), + .I3(plm_dfm_deframe4_reg_df_dat[3]), + .LO(plm_dfm_deframe4_frm4hi_half_o_dat_iv_0[3]) + ); + defparam plm_dfm_deframe4_frm4hi_half_o_dat_iv_0_7_.INIT = 16'h2A3F; + LUT4_L plm_dfm_deframe4_frm4hi_half_o_dat_iv_0_7_ ( + .I0(plm_dfm_deframe4_N_11342), + .I1(plm_dfm_by4_prel_sdpstp[1]), + .I2(plm_dfm_deframe4_reg_df_cmd[0]), + .I3(plm_dfm_deframe4_reg_df_dat[7]), + .LO(plm_dfm_deframe4_frm4hi_half_o_dat_iv_0[7]) + ); + defparam plm_dfm_deframe4_frm4hi_half_o_dat_iv_0_0_.INIT = 16'h2A3F; + LUT4_L plm_dfm_deframe4_frm4hi_half_o_dat_iv_0_0_ ( + .I0(plm_dfm_deframe4_N_11342), + .I1(plm_dfm_by4_prel_sdpstp[1]), + .I2(plm_dfm_deframe4_reg_df_cmd[0]), + .I3(plm_dfm_deframe4_reg_df_dat[0]), + .LO(plm_dfm_deframe4_frm4hi_half_o_dat_iv_0[0]) + ); + defparam plm_dfm_deframe4_frm4hi_half_o_dat_iv_0_2_.INIT = 16'h2A3F; + LUT4_L plm_dfm_deframe4_frm4hi_half_o_dat_iv_0_2_ ( + .I0(plm_dfm_deframe4_N_11342), + .I1(plm_dfm_by4_prel_sdpstp[1]), + .I2(plm_dfm_deframe4_reg_df_cmd[0]), + .I3(plm_dfm_deframe4_reg_df_dat[2]), + .LO(plm_dfm_deframe4_frm4hi_half_o_dat_iv_0[2]) + ); + defparam plm_dfm_deframe4_frm4hi_half_o_dat_iv_0_6_.INIT = 16'h2A3F; + LUT4_L plm_dfm_deframe4_frm4hi_half_o_dat_iv_0_6_ ( + .I0(plm_dfm_deframe4_N_11342), + .I1(plm_dfm_by4_prel_sdpstp[1]), + .I2(plm_dfm_deframe4_reg_df_cmd[0]), + .I3(plm_dfm_deframe4_reg_df_dat[6]), + .LO(plm_dfm_deframe4_frm4hi_half_o_dat_iv_0[6]) + ); + defparam plm_dfm_deframe4_frm4hi_half_o_dat_iv_0_5_.INIT = 16'h2A3F; + LUT4_L plm_dfm_deframe4_frm4hi_half_o_dat_iv_0_5_ ( + .I0(plm_dfm_deframe4_N_11342), + .I1(plm_dfm_by4_prel_sdpstp[1]), + .I2(plm_dfm_deframe4_reg_df_cmd[0]), + .I3(plm_dfm_deframe4_reg_df_dat[5]), + .LO(plm_dfm_deframe4_frm4hi_half_o_dat_iv_0[5]) + ); + defparam plm_dfm_deframe4_frm4hi_half_o_dat_iv_0_4_.INIT = 16'h2A3F; + LUT4_L plm_dfm_deframe4_frm4hi_half_o_dat_iv_0_4_ ( + .I0(plm_dfm_deframe4_N_11342), + .I1(plm_dfm_by4_prel_sdpstp[1]), + .I2(plm_dfm_deframe4_reg_df_cmd[0]), + .I3(plm_dfm_deframe4_reg_df_dat[4]), + .LO(plm_dfm_deframe4_frm4hi_half_o_dat_iv_0[4]) + ); + defparam plm_dfm_deframe4_frm4hi_half_o_edbedg_0_1_1_.INIT = 8'h1B; + LUT3 plm_dfm_deframe4_frm4hi_half_o_edbedg_0_1_1_ ( + .I0(plm_dfm_deframe4_frm4hi_half_N_11343), + .I1(plm_dfm_deframe4_dh_edbedg[1]), + .I2(plm_dfm_deframe4_reg_df_edbedg[1]), + .O(plm_dfm_deframe4_frm4hi_half_o_edbedg_0_1[1]) + ); + defparam plm_dfm_deframe4_frm4hi_half_o_edbedg_0_1_0_.INIT = 8'h1B; + LUT3 plm_dfm_deframe4_frm4hi_half_o_edbedg_0_1_0_ ( + .I0(plm_dfm_deframe4_frm4hi_half_N_11343), + .I1(plm_dfm_deframe4_dh_edbedg[0]), + .I2(plm_dfm_deframe4_reg_df_edbedg[0]), + .O(plm_dfm_deframe4_frm4hi_half_o_edbedg_0_1[0]) + ); + defparam plm_dfm_deframe4_frm4hi_half_reg_o_sdpstp_u_0_.INIT = 16'hA820; + LUT4_L plm_dfm_deframe4_frm4hi_half_reg_o_sdpstp_u_0_ ( + .I0(plm_dfm_deframe4_frm4hi_half_N_14418_i), + .I1(plm_dfm_deframe4_frm4hi_half_N_14421), + .I2(plm_dfm_deframe4_reg_o_edbedg15), + .I3(plm_dfm_deframe4_reg_df_sdpstp[0]), + .LO(plm_dfm_deframe4_ho_sdpstp[0]) + ); + defparam plm_dfm_deframe4_frm4hi_half_N_9810_i.INIT = 16'h7350; + LUT4_L plm_dfm_deframe4_frm4hi_half_N_9810_i ( + .I0(plm_dfm_deframe4_frm4hi_half_N_11340), + .I1(plm_dfm_deframe4_N_11342), + .I2(plm_dfm_deframe4_dh_dat[12]), + .I3(plm_dfm_deframe4_reg_df_dat[12]), + .LO(plm_dfm_deframe4_N_9810_i) + ); + defparam plm_dfm_deframe4_frm4hi_half_N_9811_i.INIT = 16'h7350; + LUT4_L plm_dfm_deframe4_frm4hi_half_N_9811_i ( + .I0(plm_dfm_deframe4_frm4hi_half_N_11340), + .I1(plm_dfm_deframe4_N_11342), + .I2(plm_dfm_deframe4_dh_dat[11]), + .I3(plm_dfm_deframe4_reg_df_dat[11]), + .LO(plm_dfm_deframe4_N_9811_i) + ); + defparam plm_dfm_deframe4_frm4hi_half_N_9812_i.INIT = 16'h7350; + LUT4_L plm_dfm_deframe4_frm4hi_half_N_9812_i ( + .I0(plm_dfm_deframe4_frm4hi_half_N_11340), + .I1(plm_dfm_deframe4_N_11342), + .I2(plm_dfm_deframe4_dh_dat[10]), + .I3(plm_dfm_deframe4_reg_df_dat[10]), + .LO(plm_dfm_deframe4_N_9812_i) + ); + defparam plm_dfm_deframe4_frm4hi_half_N_9813_i.INIT = 16'h7350; + LUT4_L plm_dfm_deframe4_frm4hi_half_N_9813_i ( + .I0(plm_dfm_deframe4_frm4hi_half_N_11340), + .I1(plm_dfm_deframe4_N_11342), + .I2(plm_dfm_deframe4_dh_dat[9]), + .I3(plm_dfm_deframe4_reg_df_dat[9]), + .LO(plm_dfm_deframe4_N_9813_i) + ); + defparam plm_dfm_deframe4_frm4hi_half_N_9814_i.INIT = 16'h7350; + LUT4_L plm_dfm_deframe4_frm4hi_half_N_9814_i ( + .I0(plm_dfm_deframe4_frm4hi_half_N_11340), + .I1(plm_dfm_deframe4_N_11342), + .I2(plm_dfm_deframe4_dh_dat[8]), + .I3(plm_dfm_deframe4_reg_df_dat[8]), + .LO(plm_dfm_deframe4_N_9814_i) + ); + defparam plm_dfm_deframe4_frm4hi_half_N_9815_i.INIT = 8'h4F; + LUT3_L plm_dfm_deframe4_frm4hi_half_N_9815_i ( + .I0(plm_dfm_deframe4_frm4hi_half_N_11340), + .I1(plm_dfm_deframe4_dh_dat[7]), + .I2(plm_dfm_deframe4_frm4hi_half_o_dat_iv_0[7]), + .LO(plm_dfm_deframe4_N_9815_i) + ); + defparam plm_dfm_deframe4_frm4hi_half_N_9816_i.INIT = 8'h4F; + LUT3_L plm_dfm_deframe4_frm4hi_half_N_9816_i ( + .I0(plm_dfm_deframe4_frm4hi_half_N_11340), + .I1(plm_dfm_deframe4_dh_dat[6]), + .I2(plm_dfm_deframe4_frm4hi_half_o_dat_iv_0[6]), + .LO(plm_dfm_deframe4_N_9816_i) + ); + defparam plm_dfm_deframe4_frm4hi_half_N_9817_i.INIT = 8'h4F; + LUT3_L plm_dfm_deframe4_frm4hi_half_N_9817_i ( + .I0(plm_dfm_deframe4_frm4hi_half_N_11340), + .I1(plm_dfm_deframe4_dh_dat[5]), + .I2(plm_dfm_deframe4_frm4hi_half_o_dat_iv_0[5]), + .LO(plm_dfm_deframe4_N_9817_i) + ); + defparam plm_dfm_deframe4_frm4hi_half_N_9818_i.INIT = 8'h4F; + LUT3_L plm_dfm_deframe4_frm4hi_half_N_9818_i ( + .I0(plm_dfm_deframe4_frm4hi_half_N_11340), + .I1(plm_dfm_deframe4_dh_dat[4]), + .I2(plm_dfm_deframe4_frm4hi_half_o_dat_iv_0[4]), + .LO(plm_dfm_deframe4_N_9818_i) + ); + defparam plm_dfm_deframe4_frm4hi_half_N_9819_i.INIT = 8'h4F; + LUT3_L plm_dfm_deframe4_frm4hi_half_N_9819_i ( + .I0(plm_dfm_deframe4_frm4hi_half_N_11340), + .I1(plm_dfm_deframe4_dh_dat[3]), + .I2(plm_dfm_deframe4_frm4hi_half_o_dat_iv_0[3]), + .LO(plm_dfm_deframe4_N_9819_i) + ); + defparam plm_dfm_deframe4_frm4hi_half_N_9820_i.INIT = 8'h4F; + LUT3_L plm_dfm_deframe4_frm4hi_half_N_9820_i ( + .I0(plm_dfm_deframe4_frm4hi_half_N_11340), + .I1(plm_dfm_deframe4_dh_dat[2]), + .I2(plm_dfm_deframe4_frm4hi_half_o_dat_iv_0[2]), + .LO(plm_dfm_deframe4_N_9820_i) + ); + defparam plm_dfm_deframe4_frm4hi_half_N_9821_i.INIT = 8'h4F; + LUT3_L plm_dfm_deframe4_frm4hi_half_N_9821_i ( + .I0(plm_dfm_deframe4_frm4hi_half_N_11340), + .I1(plm_dfm_deframe4_dh_dat[1]), + .I2(plm_dfm_deframe4_frm4hi_half_o_dat_iv_0[1]), + .LO(plm_dfm_deframe4_N_9821_i) + ); + defparam plm_dfm_deframe4_frm4hi_half_N_9822_i.INIT = 8'h4F; + LUT3_L plm_dfm_deframe4_frm4hi_half_N_9822_i ( + .I0(plm_dfm_deframe4_frm4hi_half_N_11340), + .I1(plm_dfm_deframe4_dh_dat[0]), + .I2(plm_dfm_deframe4_frm4hi_half_o_dat_iv_0[0]), + .LO(plm_dfm_deframe4_N_9822_i) + ); + defparam plm_dfm_deframe4_frm4hi_half_N_9795_i.INIT = 16'hFFF4; + LUT4_L plm_dfm_deframe4_frm4hi_half_N_9795_i ( + .I0(plm_dfm_deframe4_frm4hi_half_N_11340), + .I1(plm_dfm_deframe4_dh_dat[27]), + .I2(plm_dfm_deframe4_reg_o_dat_1_sqmuxa_1), + .I3(plm_dfm_deframe4_reg_df_dat_m_27__1557), + .LO(plm_dfm_deframe4_N_9795_i) + ); + defparam plm_dfm_deframe4_frm4hi_half_N_9796_i.INIT = 16'hFFF4; + LUT4_L plm_dfm_deframe4_frm4hi_half_N_9796_i ( + .I0(plm_dfm_deframe4_frm4hi_half_N_11340), + .I1(plm_dfm_deframe4_dh_dat[26]), + .I2(plm_dfm_deframe4_reg_o_dat_1_sqmuxa_1), + .I3(plm_dfm_deframe4_reg_df_dat_m_26__1559), + .LO(plm_dfm_deframe4_N_9796_i) + ); + defparam plm_dfm_deframe4_frm4hi_half_N_9797_i.INIT = 16'hFFF4; + LUT4_L plm_dfm_deframe4_frm4hi_half_N_9797_i ( + .I0(plm_dfm_deframe4_frm4hi_half_N_11340), + .I1(plm_dfm_deframe4_dh_dat[25]), + .I2(plm_dfm_deframe4_reg_o_dat_1_sqmuxa_1), + .I3(plm_dfm_deframe4_reg_df_dat_m_25__1563), + .LO(plm_dfm_deframe4_N_9797_i) + ); + defparam plm_dfm_deframe4_frm4hi_half_N_9798_i.INIT = 16'hFFF4; + LUT4_L plm_dfm_deframe4_frm4hi_half_N_9798_i ( + .I0(plm_dfm_deframe4_frm4hi_half_N_11340), + .I1(plm_dfm_deframe4_dh_dat[24]), + .I2(plm_dfm_deframe4_reg_o_dat_1_sqmuxa_1), + .I3(plm_dfm_deframe4_reg_df_dat_m_24__1556), + .LO(plm_dfm_deframe4_N_9798_i) + ); + defparam plm_dfm_deframe4_frm4hi_half_N_9799_i.INIT = 16'h7350; + LUT4_L plm_dfm_deframe4_frm4hi_half_N_9799_i ( + .I0(plm_dfm_deframe4_frm4hi_half_N_11340), + .I1(plm_dfm_deframe4_N_11342), + .I2(plm_dfm_deframe4_dh_dat[23]), + .I3(plm_dfm_deframe4_reg_df_dat[23]), + .LO(plm_dfm_deframe4_N_9799_i) + ); + defparam plm_dfm_deframe4_frm4hi_half_N_9800_i.INIT = 16'h7350; + LUT4_L plm_dfm_deframe4_frm4hi_half_N_9800_i ( + .I0(plm_dfm_deframe4_frm4hi_half_N_11340), + .I1(plm_dfm_deframe4_N_11342), + .I2(plm_dfm_deframe4_dh_dat[22]), + .I3(plm_dfm_deframe4_reg_df_dat[22]), + .LO(plm_dfm_deframe4_N_9800_i) + ); + defparam plm_dfm_deframe4_frm4hi_half_N_9801_i.INIT = 16'h7350; + LUT4_L plm_dfm_deframe4_frm4hi_half_N_9801_i ( + .I0(plm_dfm_deframe4_frm4hi_half_N_11340), + .I1(plm_dfm_deframe4_N_11342), + .I2(plm_dfm_deframe4_dh_dat[21]), + .I3(plm_dfm_deframe4_reg_df_dat[21]), + .LO(plm_dfm_deframe4_N_9801_i) + ); + defparam plm_dfm_deframe4_frm4hi_half_N_9802_i.INIT = 16'h7350; + LUT4_L plm_dfm_deframe4_frm4hi_half_N_9802_i ( + .I0(plm_dfm_deframe4_frm4hi_half_N_11340), + .I1(plm_dfm_deframe4_N_11342), + .I2(plm_dfm_deframe4_dh_dat[20]), + .I3(plm_dfm_deframe4_reg_df_dat[20]), + .LO(plm_dfm_deframe4_N_9802_i) + ); + defparam plm_dfm_deframe4_frm4hi_half_N_9803_i.INIT = 16'h7350; + LUT4_L plm_dfm_deframe4_frm4hi_half_N_9803_i ( + .I0(plm_dfm_deframe4_frm4hi_half_N_11340), + .I1(plm_dfm_deframe4_N_11342), + .I2(plm_dfm_deframe4_dh_dat[19]), + .I3(plm_dfm_deframe4_reg_df_dat[19]), + .LO(plm_dfm_deframe4_N_9803_i) + ); + defparam plm_dfm_deframe4_frm4hi_half_N_9804_i.INIT = 16'h7350; + LUT4_L plm_dfm_deframe4_frm4hi_half_N_9804_i ( + .I0(plm_dfm_deframe4_frm4hi_half_N_11340), + .I1(plm_dfm_deframe4_N_11342), + .I2(plm_dfm_deframe4_dh_dat[18]), + .I3(plm_dfm_deframe4_reg_df_dat[18]), + .LO(plm_dfm_deframe4_N_9804_i) + ); + defparam plm_dfm_deframe4_frm4hi_half_N_9805_i.INIT = 16'h7350; + LUT4_L plm_dfm_deframe4_frm4hi_half_N_9805_i ( + .I0(plm_dfm_deframe4_frm4hi_half_N_11340), + .I1(plm_dfm_deframe4_N_11342), + .I2(plm_dfm_deframe4_dh_dat[17]), + .I3(plm_dfm_deframe4_reg_df_dat[17]), + .LO(plm_dfm_deframe4_N_9805_i) + ); + defparam plm_dfm_deframe4_frm4hi_half_N_9806_i.INIT = 16'h7350; + LUT4_L plm_dfm_deframe4_frm4hi_half_N_9806_i ( + .I0(plm_dfm_deframe4_frm4hi_half_N_11340), + .I1(plm_dfm_deframe4_N_11342), + .I2(plm_dfm_deframe4_dh_dat[16]), + .I3(plm_dfm_deframe4_reg_df_dat[16]), + .LO(plm_dfm_deframe4_N_9806_i) + ); + defparam plm_dfm_deframe4_frm4hi_half_N_9807_i.INIT = 16'h7350; + LUT4_L plm_dfm_deframe4_frm4hi_half_N_9807_i ( + .I0(plm_dfm_deframe4_frm4hi_half_N_11340), + .I1(plm_dfm_deframe4_N_11342), + .I2(plm_dfm_deframe4_dh_dat[15]), + .I3(plm_dfm_deframe4_reg_df_dat[15]), + .LO(plm_dfm_deframe4_N_9807_i) + ); + defparam plm_dfm_deframe4_frm4hi_half_N_9808_i.INIT = 16'h7350; + LUT4_L plm_dfm_deframe4_frm4hi_half_N_9808_i ( + .I0(plm_dfm_deframe4_frm4hi_half_N_11340), + .I1(plm_dfm_deframe4_N_11342), + .I2(plm_dfm_deframe4_dh_dat[14]), + .I3(plm_dfm_deframe4_reg_df_dat[14]), + .LO(plm_dfm_deframe4_N_9808_i) + ); + defparam plm_dfm_deframe4_frm4hi_half_N_9809_i.INIT = 16'h7350; + LUT4_L plm_dfm_deframe4_frm4hi_half_N_9809_i ( + .I0(plm_dfm_deframe4_frm4hi_half_N_11340), + .I1(plm_dfm_deframe4_N_11342), + .I2(plm_dfm_deframe4_dh_dat[13]), + .I3(plm_dfm_deframe4_reg_df_dat[13]), + .LO(plm_dfm_deframe4_N_9809_i) + ); + defparam plm_dfm_deframe4_frm4hi_half_N_9791_i.INIT = 16'hFDFC; + LUT4_L plm_dfm_deframe4_frm4hi_half_N_9791_i ( + .I0(plm_dfm_deframe4_N_11342), + .I1(plm_dfm_deframe4_dh_dat_m_0_31__1561), + .I2(plm_dfm_deframe4_reg_o_dat_1_sqmuxa_1), + .I3(plm_dfm_deframe4_reg_df_dat[31]), + .LO(plm_dfm_deframe4_N_9791_i) + ); + defparam plm_dfm_deframe4_frm4hi_half_N_9792_i.INIT = 16'hFFF4; + LUT4_L plm_dfm_deframe4_frm4hi_half_N_9792_i ( + .I0(plm_dfm_deframe4_frm4hi_half_N_11340), + .I1(plm_dfm_deframe4_dh_dat[30]), + .I2(plm_dfm_deframe4_reg_o_dat_1_sqmuxa_1), + .I3(plm_dfm_deframe4_reg_df_dat_m_30__1562), + .LO(plm_dfm_deframe4_N_9792_i) + ); + defparam plm_dfm_deframe4_frm4hi_half_N_9793_i.INIT = 16'hFDFC; + LUT4_L plm_dfm_deframe4_frm4hi_half_N_9793_i ( + .I0(plm_dfm_deframe4_N_11342), + .I1(plm_dfm_deframe4_dh_dat_m_0_29__1560), + .I2(plm_dfm_deframe4_reg_o_dat_1_sqmuxa_1), + .I3(plm_dfm_deframe4_reg_df_dat[29]), + .LO(plm_dfm_deframe4_N_9793_i) + ); + defparam plm_dfm_deframe4_frm4hi_half_N_9794_i.INIT = 16'hFFF4; + LUT4_L plm_dfm_deframe4_frm4hi_half_N_9794_i ( + .I0(plm_dfm_deframe4_frm4hi_half_N_11340), + .I1(plm_dfm_deframe4_dh_dat[28]), + .I2(plm_dfm_deframe4_reg_o_dat_1_sqmuxa_1), + .I3(plm_dfm_deframe4_reg_df_dat_m_28__1558), + .LO(plm_dfm_deframe4_N_9794_i) + ); + defparam plm_dfm_deframe4_frm4hi_half_o_edbedg_0_1_.INIT = 16'hEE0F; + LUT4_L plm_dfm_deframe4_frm4hi_half_o_edbedg_0_1_ ( + .I0(plm_dfm_deframe4_frm4hi_half_reg_o_edbedg68), + .I1(plm_dfm_deframe4_frm4hi_half_reg_o_edbedg70), + .I2(plm_dfm_deframe4_frm4hi_half_o_edbedg_0_1[1]), + .I3(plm_dfm_deframe4_frm4hi_half_o_edbedg_sn_N_2), + .LO(plm_dfm_deframe4_ho_edbedg[1]) + ); + defparam plm_dfm_deframe4_frm4hi_half_o_edbedg_0_0_.INIT = 16'hDD0F; + LUT4_L plm_dfm_deframe4_frm4hi_half_o_edbedg_0_0_ ( + .I0(plm_dfm_deframe4_frm4hi_half_N_14418_i), + .I1(plm_dfm_deframe4_frm4hi_half_N_14421), + .I2(plm_dfm_deframe4_frm4hi_half_o_edbedg_0_1[0]), + .I3(plm_dfm_deframe4_frm4hi_half_o_edbedg_sn_N_2), + .LO(plm_dfm_deframe4_ho_edbedg[0]) + ); + defparam plm_dfm_deframe4_frm4hi_half_do_cmd_sn_m4_i_0_0.INIT = 8'h15; + LUT3_L plm_dfm_deframe4_frm4hi_half_do_cmd_sn_m4_i_0_0 ( + .I0(plm_dfm_by4_prel_sdpstp[1]), + .I1(plm_dfm_deframe4_reg_df_valid_1565), + .I2(plm_dfm_deframe4_reg_df_sdpstp[1]), + .LO(plm_dfm_deframe4_frm4hi_half_m4_i_0_0) + ); + defparam plm_dfm_deframe4_frm4lo_half_half_framer_un43_reg_do_cmd_0_o4.INIT = 16'h0001; + LUT4 plm_dfm_deframe4_frm4lo_half_half_framer_un43_reg_do_cmd_0_o4 ( + .I0(plm_dfm_deframe4_dh_edbedg[0]), + .I1(plm_dfm_deframe4_dh_edbedg[1]), + .I2(plm_dfm_deframe4_dh_sdpstp[0]), + .I3(plm_dfm_deframe4_dh_sdpstp[1]), + .O(plm_dfm_deframe4_N_14414_i) + ); + defparam plm_dfm_deframe4_frm4lo_half_half_framer_reg_o_edbedg11.INIT = 16'h0100; + LUT4 plm_dfm_deframe4_frm4lo_half_half_framer_reg_o_edbedg11 ( + .I0(plm_dfm_deframe4_dl_edbedg[0]), + .I1(plm_dfm_deframe4_dl_edbedg[1]), + .I2(plm_dfm_deframe4_dl_sdpstp[0]), + .I3(plm_dfm_deframe4_dl_sdpstp[1]), + .O(plm_dfm_deframe4_frm4lo_half_reg_o_edbedg11) + ); + defparam plm_dfm_deframe4_frm4lo_half_half_framer_reg_o_edbedg10.INIT = 16'h0010; + LUT4 plm_dfm_deframe4_frm4lo_half_half_framer_reg_o_edbedg10 ( + .I0(plm_dfm_deframe4_dl_edbedg[0]), + .I1(plm_dfm_deframe4_dl_edbedg[1]), + .I2(plm_dfm_deframe4_dl_sdpstp[0]), + .I3(plm_dfm_deframe4_dl_sdpstp[1]), + .O(plm_dfm_deframe4_frm4lo_half_reg_o_edbedg10) + ); + defparam plm_dfm_deframe4_frm4lo_half_half_framer_un1_reg_o_edbedg11.INIT = 4'h1; + LUT2 plm_dfm_deframe4_frm4lo_half_half_framer_un1_reg_o_edbedg11 ( + .I0(plm_dfm_deframe4_frm4lo_half_reg_o_edbedg10), + .I1(plm_dfm_deframe4_frm4lo_half_reg_o_edbedg11), + .O(plm_dfm_deframe4_frm4lo_half_N_11334) + ); + defparam plm_dfm_deframe4_frm4lo_half_half_framer_un1_reg_o_edbedg16.INIT = 4'h1; + LUT2 plm_dfm_deframe4_frm4lo_half_half_framer_un1_reg_o_edbedg16 ( + .I0(plm_dfm_deframe4_reg_o_edbedg15), + .I1(plm_dfm_deframe4_reg_o_edbedg16), + .O(plm_dfm_deframe4_N_11335) + ); + defparam plm_dfm_deframe4_frm4lo_half_reg_o_sdpstp_0_0_0_.INIT = 16'hEF40; + LUT4 plm_dfm_deframe4_frm4lo_half_reg_o_sdpstp_0_0_0_ ( + .I0(plm_dfm_deframe4_N_11335), + .I1(plm_dfm_deframe4_dh_sdpstp[0]), + .I2(plm_dfm_deframe4_dh_valid), + .I3(plm_dfm_deframe4_frm4lo_half_reg_o_edbedg10), + .O(plm_dfm_deframe4_frm4lo_half_N_6336) + ); + defparam plm_dfm_deframe4_frm4lo_half_half_framer_reg_o_edbedg70.INIT = 4'h4; + LUT2 plm_dfm_deframe4_frm4lo_half_half_framer_reg_o_edbedg70 ( + .I0(plm_dfm_deframe4_dh_cmd[0]), + .I1(plm_dfm_deframe4_dh_cmd[1]), + .O(plm_dfm_deframe4_frm4lo_half_reg_o_edbedg70) + ); + defparam plm_dfm_deframe4_frm4lo_half_half_framer_reg_o_edbedg68.INIT = 4'h2; + LUT2 plm_dfm_deframe4_frm4lo_half_half_framer_reg_o_edbedg68 ( + .I0(plm_dfm_deframe4_dh_cmd[0]), + .I1(plm_dfm_deframe4_dh_cmd[1]), + .O(plm_dfm_deframe4_frm4lo_half_reg_o_edbedg68) + ); + defparam plm_dfm_deframe4_frm4lo_half_do_cmd_m0_1_.INIT = 8'h01; + LUT3 plm_dfm_deframe4_frm4lo_half_do_cmd_m0_1_ ( + .I0(plm_dfm_deframe4_dh_cmd[0]), + .I1(plm_dfm_deframe4_dh_cmd[1]), + .I2(plm_dfm_deframe4_frm4lo_half_reg_o_edbedg10), + .O(plm_dfm_deframe4_frm4lo_half_do_cmd_m0[1]) + ); + defparam plm_dfm_deframe4_frm4lo_half_do_cmd_m0_0_.INIT = 8'h01; + LUT3 plm_dfm_deframe4_frm4lo_half_do_cmd_m0_0_ ( + .I0(plm_dfm_deframe4_dh_cmd[0]), + .I1(plm_dfm_deframe4_dh_cmd[1]), + .I2(plm_dfm_deframe4_frm4lo_half_reg_o_edbedg11), + .O(plm_dfm_deframe4_frm4lo_half_do_cmd_m0[0]) + ); + defparam plm_dfm_deframe4_frm4lo_half_do_cmd_sn_m4_i_a2_1.INIT = 8'h10; + LUT3 plm_dfm_deframe4_frm4lo_half_do_cmd_sn_m4_i_a2_1 ( + .I0(plm_dfm_deframe4_dh_cmd[0]), + .I1(plm_dfm_deframe4_dh_cmd[1]), + .I2(plm_dfm_deframe4_dh_valid), + .O(plm_dfm_deframe4_frm4lo_half_N_15_1) + ); + defparam plm_dfm_deframe4_frm4lo_half_reg_o_edbedg_2_sqmuxa_1.INIT = 16'h0100; + LUT4 plm_dfm_deframe4_frm4lo_half_reg_o_edbedg_2_sqmuxa_1 ( + .I0(plm_dfm_deframe4_dh_valid), + .I1(plm_dfm_deframe4_dl_sdpstp[0]), + .I2(plm_dfm_deframe4_dl_sdpstp[1]), + .I3(plm_dfm_deframe4_frm4lo_half_reg_o_edbedg68), + .O(plm_dfm_deframe4_frm4lo_half_reg_o_edbedg_2_sqmuxa_1_1571) + ); + defparam plm_dfm_deframe4_frm4lo_half_reg_o_edbedg_1_sqmuxa_1.INIT = 16'h1000; + LUT4_L plm_dfm_deframe4_frm4lo_half_reg_o_edbedg_1_sqmuxa_1 ( + .I0(plm_dfm_deframe4_dh_sdpstp[0]), + .I1(plm_dfm_deframe4_dh_sdpstp[1]), + .I2(plm_dfm_deframe4_dh_valid), + .I3(plm_dfm_deframe4_frm4lo_half_reg_o_edbedg68), + .LO(plm_dfm_deframe4_frm4lo_half_reg_o_edbedg_1_sqmuxa_1_1572) + ); + defparam plm_dfm_deframe4_frm4lo_half_un1_di_valid_m.INIT = 8'h06; + LUT3 plm_dfm_deframe4_frm4lo_half_un1_di_valid_m ( + .I0(plm_dfm_deframe4_dh_cmd[0]), + .I1(plm_dfm_deframe4_dh_cmd[1]), + .I2(plm_dfm_deframe4_dh_valid), + .O(plm_dfm_deframe4_frm4lo_half_un1_di_valid_m_1576) + ); + defparam plm_dfm_deframe4_frm4lo_half_reg_do_cmd_1_sqmuxa_1.INIT = 8'h80; + LUT3 plm_dfm_deframe4_frm4lo_half_reg_do_cmd_1_sqmuxa_1 ( + .I0(plm_dfm_deframe4_N_14414_i), + .I1(plm_dfm_deframe4_dh_valid), + .I2(plm_dfm_deframe4_frm4lo_half_reg_o_edbedg68), + .O(plm_dfm_deframe4_frm4lo_half_reg_do_cmd_1_sqmuxa_1_1574) + ); + defparam plm_dfm_deframe4_frm4lo_half_un1_reg_o_edbedg_2_sqmuxa.INIT = 16'h00BF; + LUT4 plm_dfm_deframe4_frm4lo_half_un1_reg_o_edbedg_2_sqmuxa ( + .I0(plm_dfm_deframe4_dh_valid), + .I1(plm_dfm_deframe4_dl_edbedg[0]), + .I2(plm_dfm_deframe4_frm4lo_half_reg_o_edbedg70), + .I3(plm_dfm_deframe4_frm4lo_half_reg_o_edbedg_2_sqmuxa_1_1571), + .O(plm_dfm_deframe4_frm4lo_half_N_11333) + ); + defparam plm_dfm_deframe4_frm4lo_half_reg_do_cmd_1_sqmuxa_2.INIT = 8'h10; + LUT3 plm_dfm_deframe4_frm4lo_half_reg_do_cmd_1_sqmuxa_2 ( + .I0(plm_dfm_deframe4_dl_edbedg[0]), + .I1(plm_dfm_deframe4_dl_edbedg[1]), + .I2(plm_dfm_deframe4_frm4lo_half_reg_o_edbedg_2_sqmuxa_1_1571), + .O(plm_dfm_deframe4_frm4lo_half_reg_do_cmd_1_sqmuxa_2_1573) + ); + defparam plm_dfm_deframe4_frm4lo_half_un1_reg_o_edbedg_0_sqmuxa_1.INIT = 16'hC2FF; + LUT4 plm_dfm_deframe4_frm4lo_half_un1_reg_o_edbedg_0_sqmuxa_1 ( + .I0(plm_dfm_deframe4_N_11335), + .I1(plm_dfm_deframe4_dh_cmd[0]), + .I2(plm_dfm_deframe4_dh_cmd[1]), + .I3(plm_dfm_deframe4_dh_valid), + .O(plm_dfm_deframe4_N_11332) + ); + defparam plm_dfm_deframe4_frm4lo_half_reg_o_edbedg_cnst_0_a2_0_.INIT = 16'hFDFC; + LUT4 plm_dfm_deframe4_frm4lo_half_reg_o_edbedg_cnst_0_a2_0_ ( + .I0(plm_dfm_deframe4_N_11335), + .I1(plm_dfm_deframe4_dh_cmd[0]), + .I2(plm_dfm_deframe4_dh_cmd[1]), + .I3(plm_dfm_deframe4_dh_valid), + .O(plm_dfm_deframe4_frm4lo_half_reg_o_edbedg_cnst[0]) + ); + defparam plm_dfm_deframe4_frm4lo_half_o_edbedg_sn_m1_0.INIT = 16'h007F; + LUT4 plm_dfm_deframe4_frm4lo_half_o_edbedg_sn_m1_0 ( + .I0(plm_dfm_deframe4_dh_edbedg[0]), + .I1(plm_dfm_deframe4_dh_valid), + .I2(plm_dfm_deframe4_frm4lo_half_reg_o_edbedg70), + .I3(plm_dfm_deframe4_frm4lo_half_reg_o_edbedg_1_sqmuxa_1_1572), + .O(plm_dfm_deframe4_frm4lo_half_o_edbedg_sn_m1_0_1575) + ); + defparam plm_dfm_deframe4_frm4lo_half_do_cmd_sn_m4_i.INIT = 16'h0007; + LUT4 plm_dfm_deframe4_frm4lo_half_do_cmd_sn_m4_i ( + .I0(plm_dfm_deframe4_frm4lo_half_N_15_1), + .I1(plm_dfm_deframe4_reg_o_edbedg15), + .I2(plm_dfm_deframe4_frm4lo_half_reg_do_cmd_1_sqmuxa_1_1574), + .I3(plm_dfm_deframe4_frm4lo_half_reg_do_cmd_1_sqmuxa_2_1573), + .O(plm_dfm_deframe4_frm4lo_half_un1_reg_do_cmd_0_sqmuxa_1_sn_i) + ); + defparam plm_dfm_deframe4_frm4lo_half_o_edbedg_sn_m1.INIT = 16'h8A00; + LUT4 plm_dfm_deframe4_frm4lo_half_o_edbedg_sn_m1 ( + .I0(plm_dfm_deframe4_frm4lo_half_N_11333), + .I1(plm_dfm_deframe4_N_11335), + .I2(plm_dfm_deframe4_frm4lo_half_N_15_1), + .I3(plm_dfm_deframe4_frm4lo_half_o_edbedg_sn_m1_0_1575), + .O(plm_dfm_deframe4_frm4lo_half_o_edbedg_sn_N_2) + ); + defparam plm_dfm_deframe4_frm4lo_half_un1_reg_o_dat_1_sqmuxa.INIT = 8'h0E; + LUT3 plm_dfm_deframe4_frm4lo_half_un1_reg_o_dat_1_sqmuxa ( + .I0(plm_dfm_deframe4_frm4lo_half_N_11334), + .I1(plm_dfm_deframe4_frm4lo_half_reg_o_edbedg_cnst[0]), + .I2(plm_dfm_deframe4_frm4lo_half_un1_di_valid_m_1576), + .O(plm_dfm_deframe4_frm4lo_half_N_11330) + ); + defparam plm_dfm_deframe4_frm4lo_half_o_dat_iv_0_28_.INIT = 16'hAF23; + LUT4 plm_dfm_deframe4_frm4lo_half_o_dat_iv_0_28_ ( + .I0(plm_dfm_deframe4_N_11332), + .I1(plm_dfm_deframe4_frm4lo_half_N_11334), + .I2(plm_dfm_deframe4_dh_dat[28]), + .I3(plm_dfm_deframe4_frm4lo_half_reg_o_edbedg_cnst[0]), + .O(plm_dfm_deframe4_frm4lo_half_o_dat_iv_0[28]) + ); + defparam plm_dfm_deframe4_frm4lo_half_o_dat_iv_0_30_.INIT = 16'hAF23; + LUT4 plm_dfm_deframe4_frm4lo_half_o_dat_iv_0_30_ ( + .I0(plm_dfm_deframe4_N_11332), + .I1(plm_dfm_deframe4_frm4lo_half_N_11334), + .I2(plm_dfm_deframe4_dh_dat[30]), + .I3(plm_dfm_deframe4_frm4lo_half_reg_o_edbedg_cnst[0]), + .O(plm_dfm_deframe4_frm4lo_half_o_dat_iv_0[30]) + ); + defparam plm_dfm_deframe4_frm4lo_half_o_dat_iv_0_29_.INIT = 16'hAF23; + LUT4 plm_dfm_deframe4_frm4lo_half_o_dat_iv_0_29_ ( + .I0(plm_dfm_deframe4_N_11332), + .I1(plm_dfm_deframe4_frm4lo_half_N_11334), + .I2(plm_dfm_deframe4_dh_dat[29]), + .I3(plm_dfm_deframe4_frm4lo_half_reg_o_edbedg_cnst[0]), + .O(plm_dfm_deframe4_frm4lo_half_o_dat_iv_0[29]) + ); + defparam plm_dfm_deframe4_frm4lo_half_o_dat_iv_0_26_.INIT = 16'hAF23; + LUT4 plm_dfm_deframe4_frm4lo_half_o_dat_iv_0_26_ ( + .I0(plm_dfm_deframe4_N_11332), + .I1(plm_dfm_deframe4_frm4lo_half_N_11334), + .I2(plm_dfm_deframe4_dh_dat[26]), + .I3(plm_dfm_deframe4_frm4lo_half_reg_o_edbedg_cnst[0]), + .O(plm_dfm_deframe4_frm4lo_half_o_dat_iv_0[26]) + ); + defparam plm_dfm_deframe4_frm4lo_half_o_dat_iv_0_24_.INIT = 16'hAF23; + LUT4 plm_dfm_deframe4_frm4lo_half_o_dat_iv_0_24_ ( + .I0(plm_dfm_deframe4_N_11332), + .I1(plm_dfm_deframe4_frm4lo_half_N_11334), + .I2(plm_dfm_deframe4_dh_dat[24]), + .I3(plm_dfm_deframe4_frm4lo_half_reg_o_edbedg_cnst[0]), + .O(plm_dfm_deframe4_frm4lo_half_o_dat_iv_0[24]) + ); + defparam plm_dfm_deframe4_frm4lo_half_o_dat_iv_0_31_.INIT = 16'hAF23; + LUT4 plm_dfm_deframe4_frm4lo_half_o_dat_iv_0_31_ ( + .I0(plm_dfm_deframe4_N_11332), + .I1(plm_dfm_deframe4_frm4lo_half_N_11334), + .I2(plm_dfm_deframe4_dh_dat[31]), + .I3(plm_dfm_deframe4_frm4lo_half_reg_o_edbedg_cnst[0]), + .O(plm_dfm_deframe4_frm4lo_half_o_dat_iv_0[31]) + ); + defparam plm_dfm_deframe4_frm4lo_half_o_dat_iv_0_27_.INIT = 16'hAF23; + LUT4 plm_dfm_deframe4_frm4lo_half_o_dat_iv_0_27_ ( + .I0(plm_dfm_deframe4_N_11332), + .I1(plm_dfm_deframe4_frm4lo_half_N_11334), + .I2(plm_dfm_deframe4_dh_dat[27]), + .I3(plm_dfm_deframe4_frm4lo_half_reg_o_edbedg_cnst[0]), + .O(plm_dfm_deframe4_frm4lo_half_o_dat_iv_0[27]) + ); + defparam plm_dfm_deframe4_frm4lo_half_o_dat_iv_0_25_.INIT = 16'hAF23; + LUT4 plm_dfm_deframe4_frm4lo_half_o_dat_iv_0_25_ ( + .I0(plm_dfm_deframe4_N_11332), + .I1(plm_dfm_deframe4_frm4lo_half_N_11334), + .I2(plm_dfm_deframe4_dh_dat[25]), + .I3(plm_dfm_deframe4_frm4lo_half_reg_o_edbedg_cnst[0]), + .O(plm_dfm_deframe4_frm4lo_half_o_dat_iv_0[25]) + ); + defparam plm_dfm_deframe4_frm4lo_half_o_edbedg_1_1_1_.INIT = 8'h27; + LUT3 plm_dfm_deframe4_frm4lo_half_o_edbedg_1_1_1_ ( + .I0(plm_dfm_deframe4_frm4lo_half_N_11333), + .I1(plm_dfm_deframe4_dh_edbedg[1]), + .I2(plm_dfm_deframe4_dl_edbedg[1]), + .O(plm_dfm_deframe4_frm4lo_half_o_edbedg_1_1[1]) + ); + defparam plm_dfm_deframe4_frm4lo_half_o_edbedg_1_am_0_.INIT = 8'hD8; + LUT3 plm_dfm_deframe4_frm4lo_half_o_edbedg_1_am_0_ ( + .I0(plm_dfm_deframe4_frm4lo_half_N_11333), + .I1(plm_dfm_deframe4_dh_edbedg[0]), + .I2(plm_dfm_deframe4_dl_edbedg[0]), + .O(plm_dfm_deframe4_frm4lo_half_o_edbedg_1_am[0]) + ); + defparam plm_dfm_deframe4_frm4lo_half_o_edbedg_1_bm_0_.INIT = 16'hFDFC; + LUT4 plm_dfm_deframe4_frm4lo_half_o_edbedg_1_bm_0_ ( + .I0(plm_dfm_deframe4_N_11335), + .I1(plm_dfm_deframe4_dh_cmd[0]), + .I2(plm_dfm_deframe4_dh_cmd[1]), + .I3(plm_dfm_deframe4_dh_valid), + .O(plm_dfm_deframe4_frm4lo_half_o_edbedg_1_bm[0]) + ); + MUXF5 plm_dfm_deframe4_frm4lo_half_o_edbedg_1_0_ ( + .I0(plm_dfm_deframe4_frm4lo_half_o_edbedg_1_am[0]), + .I1(plm_dfm_deframe4_frm4lo_half_o_edbedg_1_bm[0]), + .O(plm_dfm_deframe4_lo_edbedg[0]), + .S(plm_dfm_deframe4_frm4lo_half_o_edbedg_sn_N_2) + ); + defparam plm_dfm_deframe4_frm4lo_half_do_valid_iv.INIT = 4'h2; + LUT2_L plm_dfm_deframe4_frm4lo_half_do_valid_iv ( + .I0(plm_dfm_deframe4_frm4lo_half_reg_o_edbedg_cnst[0]), + .I1(plm_dfm_deframe4_frm4lo_half_un1_di_valid_m_1576), + .LO(plm_dfm_deframe4_dl_valid) + ); + defparam plm_dfm_deframe4_frm4lo_half_o_edbedg_1_1_.INIT = 16'hEE0F; + LUT4_L plm_dfm_deframe4_frm4lo_half_o_edbedg_1_1_ ( + .I0(plm_dfm_deframe4_frm4lo_half_reg_o_edbedg68), + .I1(plm_dfm_deframe4_frm4lo_half_reg_o_edbedg70), + .I2(plm_dfm_deframe4_frm4lo_half_o_edbedg_1_1[1]), + .I3(plm_dfm_deframe4_frm4lo_half_o_edbedg_sn_N_2), + .LO(plm_dfm_deframe4_lo_edbedg[1]) + ); + defparam plm_dfm_deframe4_frm4lo_half_do_cmd_0_1_.INIT = 16'hDC00; + LUT4_L plm_dfm_deframe4_frm4lo_half_do_cmd_0_1_ ( + .I0(plm_dfm_deframe4_N_11335), + .I1(plm_dfm_deframe4_frm4lo_half_do_cmd_m0[1]), + .I2(plm_dfm_deframe4_frm4lo_half_N_15_1), + .I3(plm_dfm_deframe4_frm4lo_half_un1_reg_do_cmd_0_sqmuxa_1_sn_i), + .LO(plm_dfm_deframe4_dl_cmd[1]) + ); + defparam plm_dfm_deframe4_frm4lo_half_do_cmd_0_0_.INIT = 16'h8CFF; + LUT4_L plm_dfm_deframe4_frm4lo_half_do_cmd_0_0_ ( + .I0(plm_dfm_deframe4_N_11335), + .I1(plm_dfm_deframe4_frm4lo_half_do_cmd_m0[0]), + .I2(plm_dfm_deframe4_frm4lo_half_N_15_1), + .I3(plm_dfm_deframe4_frm4lo_half_un1_reg_do_cmd_0_sqmuxa_1_sn_i), + .LO(plm_dfm_deframe4_dl_cmd[0]) + ); + defparam plm_dfm_deframe4_frm4lo_half_reg_o_sdpstp_u_0_.INIT = 8'h02; + LUT3_L plm_dfm_deframe4_frm4lo_half_reg_o_sdpstp_u_0_ ( + .I0(plm_dfm_deframe4_frm4lo_half_N_6336), + .I1(plm_dfm_deframe4_dh_cmd[0]), + .I2(plm_dfm_deframe4_dh_cmd[1]), + .LO(plm_dfm_deframe4_lo_sdpstp[0]) + ); + defparam plm_dfm_deframe4_frm4lo_half_N_9845_i.INIT = 16'h7530; + LUT4_L plm_dfm_deframe4_frm4lo_half_N_9845_i ( + .I0(plm_dfm_deframe4_frm4lo_half_N_11330), + .I1(plm_dfm_deframe4_N_11332), + .I2(plm_dfm_deframe4_dh_dat[10]), + .I3(plm_dfm_deframe4_dl_dat[10]), + .LO(plm_dfm_deframe4_N_9845_i) + ); + defparam plm_dfm_deframe4_frm4lo_half_N_9846_i.INIT = 16'h7530; + LUT4_L plm_dfm_deframe4_frm4lo_half_N_9846_i ( + .I0(plm_dfm_deframe4_frm4lo_half_N_11330), + .I1(plm_dfm_deframe4_N_11332), + .I2(plm_dfm_deframe4_dh_dat[9]), + .I3(plm_dfm_deframe4_dl_dat[9]), + .LO(plm_dfm_deframe4_N_9846_i) + ); + defparam plm_dfm_deframe4_frm4lo_half_N_9847_i.INIT = 16'h7530; + LUT4_L plm_dfm_deframe4_frm4lo_half_N_9847_i ( + .I0(plm_dfm_deframe4_frm4lo_half_N_11330), + .I1(plm_dfm_deframe4_N_11332), + .I2(plm_dfm_deframe4_dh_dat[8]), + .I3(plm_dfm_deframe4_dl_dat[8]), + .LO(plm_dfm_deframe4_N_9847_i) + ); + defparam plm_dfm_deframe4_frm4lo_half_N_9848_i.INIT = 16'hFFDC; + LUT4_L plm_dfm_deframe4_frm4lo_half_N_9848_i ( + .I0(plm_dfm_deframe4_frm4lo_half_N_11330), + .I1(plm_dfm_deframe4_dh_dat_m[7]), + .I2(plm_dfm_deframe4_dl_dat[7]), + .I3(plm_dfm_deframe4_reg_o_dat_1_sqmuxa_1), + .LO(plm_dfm_deframe4_N_9848_i) + ); + defparam plm_dfm_deframe4_frm4lo_half_N_9849_i.INIT = 16'hFFDC; + LUT4_L plm_dfm_deframe4_frm4lo_half_N_9849_i ( + .I0(plm_dfm_deframe4_frm4lo_half_N_11330), + .I1(plm_dfm_deframe4_dh_dat_m[6]), + .I2(plm_dfm_deframe4_dl_dat[6]), + .I3(plm_dfm_deframe4_reg_o_dat_1_sqmuxa_1), + .LO(plm_dfm_deframe4_N_9849_i) + ); + defparam plm_dfm_deframe4_frm4lo_half_N_9850_i.INIT = 16'hFFDC; + LUT4_L plm_dfm_deframe4_frm4lo_half_N_9850_i ( + .I0(plm_dfm_deframe4_frm4lo_half_N_11330), + .I1(plm_dfm_deframe4_dh_dat_m[5]), + .I2(plm_dfm_deframe4_dl_dat[5]), + .I3(plm_dfm_deframe4_reg_o_dat_1_sqmuxa_1), + .LO(plm_dfm_deframe4_N_9850_i) + ); + defparam plm_dfm_deframe4_frm4lo_half_N_9851_i.INIT = 16'hFFDC; + LUT4_L plm_dfm_deframe4_frm4lo_half_N_9851_i ( + .I0(plm_dfm_deframe4_frm4lo_half_N_11330), + .I1(plm_dfm_deframe4_dh_dat_m[4]), + .I2(plm_dfm_deframe4_dl_dat[4]), + .I3(plm_dfm_deframe4_reg_o_dat_1_sqmuxa_1), + .LO(plm_dfm_deframe4_N_9851_i) + ); + defparam plm_dfm_deframe4_frm4lo_half_N_9852_i.INIT = 16'hFFDC; + LUT4_L plm_dfm_deframe4_frm4lo_half_N_9852_i ( + .I0(plm_dfm_deframe4_frm4lo_half_N_11330), + .I1(plm_dfm_deframe4_dh_dat_m[3]), + .I2(plm_dfm_deframe4_dl_dat[3]), + .I3(plm_dfm_deframe4_reg_o_dat_1_sqmuxa_1), + .LO(plm_dfm_deframe4_N_9852_i) + ); + defparam plm_dfm_deframe4_frm4lo_half_N_9853_i.INIT = 16'hFFDC; + LUT4_L plm_dfm_deframe4_frm4lo_half_N_9853_i ( + .I0(plm_dfm_deframe4_frm4lo_half_N_11330), + .I1(plm_dfm_deframe4_dh_dat_m[2]), + .I2(plm_dfm_deframe4_dl_dat[2]), + .I3(plm_dfm_deframe4_reg_o_dat_1_sqmuxa_1), + .LO(plm_dfm_deframe4_N_9853_i) + ); + defparam plm_dfm_deframe4_frm4lo_half_N_9854_i.INIT = 16'hFFDC; + LUT4_L plm_dfm_deframe4_frm4lo_half_N_9854_i ( + .I0(plm_dfm_deframe4_frm4lo_half_N_11330), + .I1(plm_dfm_deframe4_dh_dat_m[1]), + .I2(plm_dfm_deframe4_dl_dat[1]), + .I3(plm_dfm_deframe4_reg_o_dat_1_sqmuxa_1), + .LO(plm_dfm_deframe4_N_9854_i) + ); + defparam plm_dfm_deframe4_frm4lo_half_N_9855_i.INIT = 16'hFFDC; + LUT4_L plm_dfm_deframe4_frm4lo_half_N_9855_i ( + .I0(plm_dfm_deframe4_frm4lo_half_N_11330), + .I1(plm_dfm_deframe4_dh_dat_m[0]), + .I2(plm_dfm_deframe4_dl_dat[0]), + .I3(plm_dfm_deframe4_reg_o_dat_1_sqmuxa_1), + .LO(plm_dfm_deframe4_N_9855_i) + ); + defparam plm_dfm_deframe4_frm4lo_half_N_9830_i.INIT = 8'h4F; + LUT3_L plm_dfm_deframe4_frm4lo_half_N_9830_i ( + .I0(plm_dfm_deframe4_frm4lo_half_N_11330), + .I1(plm_dfm_deframe4_dl_dat[25]), + .I2(plm_dfm_deframe4_frm4lo_half_o_dat_iv_0[25]), + .LO(plm_dfm_deframe4_N_9830_i) + ); + defparam plm_dfm_deframe4_frm4lo_half_N_9831_i.INIT = 8'h4F; + LUT3_L plm_dfm_deframe4_frm4lo_half_N_9831_i ( + .I0(plm_dfm_deframe4_frm4lo_half_N_11330), + .I1(plm_dfm_deframe4_dl_dat[24]), + .I2(plm_dfm_deframe4_frm4lo_half_o_dat_iv_0[24]), + .LO(plm_dfm_deframe4_N_9831_i) + ); + defparam plm_dfm_deframe4_frm4lo_half_N_9832_i.INIT = 16'h7530; + LUT4_L plm_dfm_deframe4_frm4lo_half_N_9832_i ( + .I0(plm_dfm_deframe4_frm4lo_half_N_11330), + .I1(plm_dfm_deframe4_N_11332), + .I2(plm_dfm_deframe4_dh_dat[23]), + .I3(plm_dfm_deframe4_dl_dat[23]), + .LO(plm_dfm_deframe4_N_9832_i) + ); + defparam plm_dfm_deframe4_frm4lo_half_N_9833_i.INIT = 16'h7530; + LUT4_L plm_dfm_deframe4_frm4lo_half_N_9833_i ( + .I0(plm_dfm_deframe4_frm4lo_half_N_11330), + .I1(plm_dfm_deframe4_N_11332), + .I2(plm_dfm_deframe4_dh_dat[22]), + .I3(plm_dfm_deframe4_dl_dat[22]), + .LO(plm_dfm_deframe4_N_9833_i) + ); + defparam plm_dfm_deframe4_frm4lo_half_N_9834_i.INIT = 16'h7530; + LUT4_L plm_dfm_deframe4_frm4lo_half_N_9834_i ( + .I0(plm_dfm_deframe4_frm4lo_half_N_11330), + .I1(plm_dfm_deframe4_N_11332), + .I2(plm_dfm_deframe4_dh_dat[21]), + .I3(plm_dfm_deframe4_dl_dat[21]), + .LO(plm_dfm_deframe4_N_9834_i) + ); + defparam plm_dfm_deframe4_frm4lo_half_N_9835_i.INIT = 16'h7530; + LUT4_L plm_dfm_deframe4_frm4lo_half_N_9835_i ( + .I0(plm_dfm_deframe4_frm4lo_half_N_11330), + .I1(plm_dfm_deframe4_N_11332), + .I2(plm_dfm_deframe4_dh_dat[20]), + .I3(plm_dfm_deframe4_dl_dat[20]), + .LO(plm_dfm_deframe4_N_9835_i) + ); + defparam plm_dfm_deframe4_frm4lo_half_N_9836_i.INIT = 16'h7530; + LUT4_L plm_dfm_deframe4_frm4lo_half_N_9836_i ( + .I0(plm_dfm_deframe4_frm4lo_half_N_11330), + .I1(plm_dfm_deframe4_N_11332), + .I2(plm_dfm_deframe4_dh_dat[19]), + .I3(plm_dfm_deframe4_dl_dat[19]), + .LO(plm_dfm_deframe4_N_9836_i) + ); + defparam plm_dfm_deframe4_frm4lo_half_N_9837_i.INIT = 16'h7530; + LUT4_L plm_dfm_deframe4_frm4lo_half_N_9837_i ( + .I0(plm_dfm_deframe4_frm4lo_half_N_11330), + .I1(plm_dfm_deframe4_N_11332), + .I2(plm_dfm_deframe4_dh_dat[18]), + .I3(plm_dfm_deframe4_dl_dat[18]), + .LO(plm_dfm_deframe4_N_9837_i) + ); + defparam plm_dfm_deframe4_frm4lo_half_N_9838_i.INIT = 16'h7530; + LUT4_L plm_dfm_deframe4_frm4lo_half_N_9838_i ( + .I0(plm_dfm_deframe4_frm4lo_half_N_11330), + .I1(plm_dfm_deframe4_N_11332), + .I2(plm_dfm_deframe4_dh_dat[17]), + .I3(plm_dfm_deframe4_dl_dat[17]), + .LO(plm_dfm_deframe4_N_9838_i) + ); + defparam plm_dfm_deframe4_frm4lo_half_N_9839_i.INIT = 16'h7530; + LUT4_L plm_dfm_deframe4_frm4lo_half_N_9839_i ( + .I0(plm_dfm_deframe4_frm4lo_half_N_11330), + .I1(plm_dfm_deframe4_N_11332), + .I2(plm_dfm_deframe4_dh_dat[16]), + .I3(plm_dfm_deframe4_dl_dat[16]), + .LO(plm_dfm_deframe4_N_9839_i) + ); + defparam plm_dfm_deframe4_frm4lo_half_N_9840_i.INIT = 16'h7530; + LUT4_L plm_dfm_deframe4_frm4lo_half_N_9840_i ( + .I0(plm_dfm_deframe4_frm4lo_half_N_11330), + .I1(plm_dfm_deframe4_N_11332), + .I2(plm_dfm_deframe4_dh_dat[15]), + .I3(plm_dfm_deframe4_dl_dat[15]), + .LO(plm_dfm_deframe4_N_9840_i) + ); + defparam plm_dfm_deframe4_frm4lo_half_N_9841_i.INIT = 16'h7530; + LUT4_L plm_dfm_deframe4_frm4lo_half_N_9841_i ( + .I0(plm_dfm_deframe4_frm4lo_half_N_11330), + .I1(plm_dfm_deframe4_N_11332), + .I2(plm_dfm_deframe4_dh_dat[14]), + .I3(plm_dfm_deframe4_dl_dat[14]), + .LO(plm_dfm_deframe4_N_9841_i) + ); + defparam plm_dfm_deframe4_frm4lo_half_N_9842_i.INIT = 16'h7530; + LUT4_L plm_dfm_deframe4_frm4lo_half_N_9842_i ( + .I0(plm_dfm_deframe4_frm4lo_half_N_11330), + .I1(plm_dfm_deframe4_N_11332), + .I2(plm_dfm_deframe4_dh_dat[13]), + .I3(plm_dfm_deframe4_dl_dat[13]), + .LO(plm_dfm_deframe4_N_9842_i) + ); + defparam plm_dfm_deframe4_frm4lo_half_N_9843_i.INIT = 16'h7530; + LUT4_L plm_dfm_deframe4_frm4lo_half_N_9843_i ( + .I0(plm_dfm_deframe4_frm4lo_half_N_11330), + .I1(plm_dfm_deframe4_N_11332), + .I2(plm_dfm_deframe4_dh_dat[12]), + .I3(plm_dfm_deframe4_dl_dat[12]), + .LO(plm_dfm_deframe4_N_9843_i) + ); + defparam plm_dfm_deframe4_frm4lo_half_N_9844_i.INIT = 16'h7530; + LUT4_L plm_dfm_deframe4_frm4lo_half_N_9844_i ( + .I0(plm_dfm_deframe4_frm4lo_half_N_11330), + .I1(plm_dfm_deframe4_N_11332), + .I2(plm_dfm_deframe4_dh_dat[11]), + .I3(plm_dfm_deframe4_dl_dat[11]), + .LO(plm_dfm_deframe4_N_9844_i) + ); + defparam plm_dfm_deframe4_frm4lo_half_N_9824_i.INIT = 8'h4F; + LUT3_L plm_dfm_deframe4_frm4lo_half_N_9824_i ( + .I0(plm_dfm_deframe4_frm4lo_half_N_11330), + .I1(plm_dfm_deframe4_dl_dat[31]), + .I2(plm_dfm_deframe4_frm4lo_half_o_dat_iv_0[31]), + .LO(plm_dfm_deframe4_N_9824_i) + ); + defparam plm_dfm_deframe4_frm4lo_half_N_9825_i.INIT = 8'h4F; + LUT3_L plm_dfm_deframe4_frm4lo_half_N_9825_i ( + .I0(plm_dfm_deframe4_frm4lo_half_N_11330), + .I1(plm_dfm_deframe4_dl_dat[30]), + .I2(plm_dfm_deframe4_frm4lo_half_o_dat_iv_0[30]), + .LO(plm_dfm_deframe4_N_9825_i) + ); + defparam plm_dfm_deframe4_frm4lo_half_N_9826_i.INIT = 8'h4F; + LUT3_L plm_dfm_deframe4_frm4lo_half_N_9826_i ( + .I0(plm_dfm_deframe4_frm4lo_half_N_11330), + .I1(plm_dfm_deframe4_dl_dat[29]), + .I2(plm_dfm_deframe4_frm4lo_half_o_dat_iv_0[29]), + .LO(plm_dfm_deframe4_N_9826_i) + ); + defparam plm_dfm_deframe4_frm4lo_half_N_9827_i.INIT = 8'h4F; + LUT3_L plm_dfm_deframe4_frm4lo_half_N_9827_i ( + .I0(plm_dfm_deframe4_frm4lo_half_N_11330), + .I1(plm_dfm_deframe4_dl_dat[28]), + .I2(plm_dfm_deframe4_frm4lo_half_o_dat_iv_0[28]), + .LO(plm_dfm_deframe4_N_9827_i) + ); + defparam plm_dfm_deframe4_frm4lo_half_N_9828_i.INIT = 8'h4F; + LUT3_L plm_dfm_deframe4_frm4lo_half_N_9828_i ( + .I0(plm_dfm_deframe4_frm4lo_half_N_11330), + .I1(plm_dfm_deframe4_dl_dat[27]), + .I2(plm_dfm_deframe4_frm4lo_half_o_dat_iv_0[27]), + .LO(plm_dfm_deframe4_N_9828_i) + ); + defparam plm_dfm_deframe4_frm4lo_half_N_9829_i.INIT = 8'h4F; + LUT3_L plm_dfm_deframe4_frm4lo_half_N_9829_i ( + .I0(plm_dfm_deframe4_frm4lo_half_N_11330), + .I1(plm_dfm_deframe4_dl_dat[26]), + .I2(plm_dfm_deframe4_frm4lo_half_o_dat_iv_0[26]), + .LO(plm_dfm_deframe4_N_9829_i) + ); + VCC plm_sym_VCC ( + .P(plm_sym_VCC_1586) + ); + GND plm_sym_GND ( + .G(plm_sym_GND_1589) + ); + MUXCY_L plm_sym_un6_reg_count_cry_0 ( + .CI(plm_sym_GND_1589), + .DI(plm_sym_VCC_1586), + .LO(plm_sym_un6_reg_count_cry_0_1577), + .S(N_71018_i_16) + ); + MUXCY_L plm_sym_un6_reg_count_cry_1 ( + .CI(plm_sym_un6_reg_count_cry_0_1577), + .DI(plm_sym_VCC_1586), + .LO(plm_sym_un6_reg_count_cry_1_1578), + .S(plm_sym_un6_reg_count_s_1_sf_1637) + ); + XORCY plm_sym_un6_reg_count_s_1 ( + .CI(plm_sym_un6_reg_count_cry_0_1577), + .LI(plm_sym_un6_reg_count_s_1_sf_1637), + .O(plm_sym_un6_reg_count_s_1_1611) + ); + MUXCY_L plm_sym_un6_reg_count_cry_2 ( + .CI(plm_sym_un6_reg_count_cry_1_1578), + .DI(plm_sym_VCC_1586), + .LO(plm_sym_un6_reg_count_cry_2_1579), + .S(plm_sym_un6_reg_count_s_2_sf_1636) + ); + XORCY plm_sym_un6_reg_count_s_2 ( + .CI(plm_sym_un6_reg_count_cry_1_1578), + .LI(plm_sym_un6_reg_count_s_2_sf_1636), + .O(plm_sym_un6_reg_count_s_2_1610) + ); + MUXCY_L plm_sym_un6_reg_count_cry_3 ( + .CI(plm_sym_un6_reg_count_cry_2_1579), + .DI(plm_sym_VCC_1586), + .LO(plm_sym_un6_reg_count_cry_3_1580), + .S(plm_sym_un6_reg_count_s_3_sf_1635) + ); + XORCY plm_sym_un6_reg_count_s_3 ( + .CI(plm_sym_un6_reg_count_cry_2_1579), + .LI(plm_sym_un6_reg_count_s_3_sf_1635), + .O(plm_sym_un6_reg_count_s_3_1609) + ); + MUXCY_L plm_sym_un6_reg_count_cry_4 ( + .CI(plm_sym_un6_reg_count_cry_3_1580), + .DI(plm_sym_VCC_1586), + .LO(plm_sym_un6_reg_count_cry_4_1581), + .S(plm_sym_un6_reg_count_s_4_sf_1634) + ); + XORCY plm_sym_un6_reg_count_s_4 ( + .CI(plm_sym_un6_reg_count_cry_3_1580), + .LI(plm_sym_un6_reg_count_s_4_sf_1634), + .O(plm_sym_un6_reg_count_s_4_1608) + ); + MUXCY_L plm_sym_un6_reg_count_cry_5 ( + .CI(plm_sym_un6_reg_count_cry_4_1581), + .DI(plm_sym_VCC_1586), + .LO(plm_sym_un6_reg_count_cry_5_1582), + .S(plm_sym_un6_reg_count_s_5_sf_1633) + ); + XORCY plm_sym_un6_reg_count_s_5 ( + .CI(plm_sym_un6_reg_count_cry_4_1581), + .LI(plm_sym_un6_reg_count_s_5_sf_1633), + .O(plm_sym_un6_reg_count_s_5_1607) + ); + MUXCY_L plm_sym_un6_reg_count_cry_6 ( + .CI(plm_sym_un6_reg_count_cry_5_1582), + .DI(plm_sym_VCC_1586), + .LO(plm_sym_un6_reg_count_cry_6_1583), + .S(plm_sym_un6_reg_count_s_6_sf_1632) + ); + XORCY plm_sym_un6_reg_count_s_6 ( + .CI(plm_sym_un6_reg_count_cry_5_1582), + .LI(plm_sym_un6_reg_count_s_6_sf_1632), + .O(plm_sym_un6_reg_count_s_6_1606) + ); + MUXCY_L plm_sym_un6_reg_count_cry_7 ( + .CI(plm_sym_un6_reg_count_cry_6_1583), + .DI(plm_sym_VCC_1586), + .LO(plm_sym_un6_reg_count_cry_7_1584), + .S(plm_sym_un6_reg_count_s_7_sf_1631) + ); + XORCY plm_sym_un6_reg_count_s_7 ( + .CI(plm_sym_un6_reg_count_cry_6_1583), + .LI(plm_sym_un6_reg_count_s_7_sf_1631), + .O(plm_sym_un6_reg_count_s_7_1605) + ); + MUXCY_L plm_sym_un6_reg_count_cry_8 ( + .CI(plm_sym_un6_reg_count_cry_7_1584), + .DI(plm_sym_VCC_1586), + .LO(plm_sym_un6_reg_count_cry_8_1585), + .S(plm_sym_un6_reg_count_s_8_sf_1604) + ); + XORCY plm_sym_un6_reg_count_s_8 ( + .CI(plm_sym_un6_reg_count_cry_7_1584), + .LI(plm_sym_un6_reg_count_s_8_sf_1604), + .O(plm_sym_un6_reg_count_s_8_1621) + ); + MUXCY_L plm_sym_un6_reg_count_cry_9 ( + .CI(plm_sym_un6_reg_count_cry_8_1585), + .DI(plm_sym_VCC_1586), + .LO(plm_sym_un6_reg_count_cry_9_1587), + .S(plm_sym_un6_reg_count_s_9_sf_1603) + ); + XORCY plm_sym_un6_reg_count_s_9 ( + .CI(plm_sym_un6_reg_count_cry_8_1585), + .LI(plm_sym_un6_reg_count_s_9_sf_1603), + .O(plm_sym_un6_reg_count_s_9_1620) + ); + MUXCY_L plm_sym_un6_reg_count_cry_10 ( + .CI(plm_sym_un6_reg_count_cry_9_1587), + .DI(plm_sym_VCC_1586), + .LO(plm_sym_un6_reg_count_cry_10_1588), + .S(plm_sym_un6_reg_count_s_10_sf_1630) + ); + XORCY plm_sym_un6_reg_count_s_10 ( + .CI(plm_sym_un6_reg_count_cry_9_1587), + .LI(plm_sym_un6_reg_count_s_10_sf_1630), + .O(plm_sym_un6_reg_count_s_10_1602) + ); + XORCY plm_sym_un6_reg_count_s_11 ( + .CI(plm_sym_un6_reg_count_cry_10_1588), + .LI(plm_sym_un6_reg_count_s_11_sf_1593), + .O(plm_sym_un6_reg_count_s_11_1601) + ); + MUXCY_L plm_sym_un1_reg_outstanding_ccs_1_cry_0 ( + .CI(plm_sym_GND_1589), + .DI(plm_reg_outstanding_ccs[0]), + .LO(plm_sym_un1_reg_outstanding_ccs_1_cry_0_1590), + .S(plm_sym_un1_reg_outstanding_ccs_1_axb_0_1617) + ); + MUXCY_L plm_sym_un1_reg_outstanding_ccs_1_cry_1 ( + .CI(plm_sym_un1_reg_outstanding_ccs_1_cry_0_1590), + .DI(plm_reg_outstanding_ccs[1]), + .LO(plm_sym_un1_reg_outstanding_ccs_1_cry_1_1591), + .S(plm_sym_un1_reg_outstanding_ccs_1_axb_1_1599) + ); + XORCY plm_sym_un1_reg_outstanding_ccs_1_s_1 ( + .CI(plm_sym_un1_reg_outstanding_ccs_1_cry_0_1590), + .LI(plm_sym_un1_reg_outstanding_ccs_1_axb_1_1599), + .O(plm_sym_un1_reg_outstanding_ccs_1_s_1_1616) + ); + MUXCY_L plm_sym_un1_reg_outstanding_ccs_1_cry_2 ( + .CI(plm_sym_un1_reg_outstanding_ccs_1_cry_1_1591), + .DI(plm_reg_outstanding_ccs[2]), + .LO(plm_sym_un1_reg_outstanding_ccs_1_cry_2_1592), + .S(plm_sym_un1_reg_outstanding_ccs_1_axb_2_1598) + ); + XORCY plm_sym_un1_reg_outstanding_ccs_1_s_2 ( + .CI(plm_sym_un1_reg_outstanding_ccs_1_cry_1_1591), + .LI(plm_sym_un1_reg_outstanding_ccs_1_axb_2_1598), + .O(plm_sym_un1_reg_outstanding_ccs_1_s_2_1615) + ); + XORCY plm_sym_un1_reg_outstanding_ccs_1_s_3 ( + .CI(plm_sym_un1_reg_outstanding_ccs_1_cry_2_1592), + .LI(plm_sym_un1_reg_outstanding_ccs_1_axb_3_1597), + .O(plm_sym_un1_reg_outstanding_ccs_1_s_3_1614) + ); + defparam plm_sym_lane2_bypass_reg_tx2_raw_char_8_0_0_0_i_a3_11_.INIT = 4'h4; + LUT2 plm_sym_lane2_bypass_reg_tx2_raw_char_8_0_0_0_i_a3_11_ ( + .I0(plm_sym_sym_bypass[0]), + .I1(plm_sym_sym_bypass[2]), + .O(plm_sym_N_61309) + ); + defparam plm_sym_lane0_bypass_reg_tx0_raw_char_8_0_0_0_i_a3_0_10_.INIT = 4'h1; + LUT2 plm_sym_lane0_bypass_reg_tx0_raw_char_8_0_0_0_i_a3_0_10_ ( + .I0(plm_sym_sym_bypass[0]), + .I1(plm_sym_sym_bypass[2]), + .O(plm_sym_N_61369) + ); + defparam plm_sym_lane1_bypass_reg_tx1_raw_char_8_i_0_0_0_o3_3_.INIT = 4'h4; + LUT2 plm_sym_lane1_bypass_reg_tx1_raw_char_8_i_0_0_0_o3_3_ ( + .I0(cfg_cfg_6102[510]), + .I1(plm_sym_sym_bypass[0]), + .O(plm_sym_reg_tx1_raw_char_8_i_0_0_0_o3[3]) + ); + defparam plm_sym_lane1_bypass_reg_tx1_raw_char_8_i_0_0_0_a3_0_7_.INIT = 4'h2; + LUT2 plm_sym_lane1_bypass_reg_tx1_raw_char_8_i_0_0_0_a3_0_7_ ( + .I0(plm_sym_sym_bypass[0]), + .I1(plm_sym_sym_bypass[1]), + .O(plm_sym_N_61382) + ); + defparam plm_sym_reg_sym_gen_sel_15_i_o3_1_.INIT = 4'h8; + LUT2 plm_sym_reg_sym_gen_sel_15_i_o3_1_ ( + .I0(plm_send_command[0]), + .I1(plm_send_command[2]), + .O(plm_sym_N_10027) + ); + defparam plm_sym_frm_dispatched_ccs.INIT = 4'h2; + LUT2 plm_sym_frm_dispatched_ccs ( + .I0(plm_frm_atomic), + .I1(plm_sym_reg_frm_atomic_1613), + .O(plm_sym_frm_dispatched_ccs_1600) + ); + defparam plm_sym_un6_reg_count_s_11_sf.INIT = 4'h1; + LUT1 plm_sym_un6_reg_count_s_11_sf ( + .I0(plm_sym_reg_count_6112[11]), + .O(plm_sym_un6_reg_count_s_11_sf_1593) + ); + defparam plm_sym_lane1_bypass_reg_tx1_raw_char_8_0_0_0_i_m3_0_14_.INIT = 8'hB8; + LUT3_L plm_sym_lane1_bypass_reg_tx1_raw_char_8_0_0_0_i_m3_0_14_ ( + .I0(plm_frm1_char[14]), + .I1(plm_sym_sym_bypass[2]), + .I2(plm_sym_sym_symbol_14_), + .LO(plm_sym_N_56524) + ); + defparam plm_sym_lane2_bypass_reg_tx2_raw_char_8_0_0_0_i_m3_0_14_.INIT = 8'hB8; + LUT3_L plm_sym_lane2_bypass_reg_tx2_raw_char_8_0_0_0_i_m3_0_14_ ( + .I0(plm_frm2_char[14]), + .I1(plm_sym_sym_bypass[2]), + .I2(plm_sym_sym_symbol_14_), + .LO(plm_sym_N_56525) + ); + defparam plm_sym_lane3_bypass_reg_tx3_raw_char_8_0_0_0_i_m3_0_14_.INIT = 8'hB8; + LUT3_L plm_sym_lane3_bypass_reg_tx3_raw_char_8_0_0_0_i_m3_0_14_ ( + .I0(plm_frm3_char[14]), + .I1(plm_sym_sym_bypass[2]), + .I2(plm_sym_sym_symbol_14_), + .LO(plm_sym_N_56526) + ); + defparam plm_sym_lane2_bypass_reg_tx2_raw_char_8_i_i_0_i_m3_0_8_.INIT = 8'hB8; + LUT3_L plm_sym_lane2_bypass_reg_tx2_raw_char_8_i_i_0_i_m3_0_8_ ( + .I0(plm_frm2_char[8]), + .I1(plm_sym_sym_bypass[2]), + .I2(plm_sym_sym_symbol_0_), + .LO(plm_sym_N_56625) + ); + defparam plm_sym_lane0_bypass_reg_tx0_raw_char_8_i_i_0_i_m3_0_14_.INIT = 8'hB8; + LUT3_L plm_sym_lane0_bypass_reg_tx0_raw_char_8_i_i_0_i_m3_0_14_ ( + .I0(plm_frm0_char[14]), + .I1(plm_sym_sym_bypass[2]), + .I2(plm_sym_sym_symbol_14_), + .LO(plm_sym_N_56624) + ); + defparam plm_sym_lane0_bypass_reg_tx0_raw_char_8_i_i_0_i_m3_0_8_.INIT = 8'hB8; + LUT3_L plm_sym_lane0_bypass_reg_tx0_raw_char_8_i_i_0_i_m3_0_8_ ( + .I0(plm_frm0_char[8]), + .I1(plm_sym_sym_bypass[2]), + .I2(plm_sym_sym_symbol_0_), + .LO(plm_sym_N_56623) + ); + defparam plm_sym_lane3_bypass_reg_tx3_raw_char_is_k_8_0_a2_i_0_0_o2_0_.INIT = 8'h54; + LUT3 plm_sym_lane3_bypass_reg_tx3_raw_char_is_k_8_0_a2_i_0_0_o2_0_ ( + .I0(plm_sym_sym_bypass[1]), + .I1(plm_sym_sym_bypass[2]), + .I2(plm_sym_sym_is_k[0]), + .O(plm_sym_N_56230_i) + ); + defparam plm_sym_lane3_bypass_reg_tx3_raw_char_pass_8_0_iv_i_0_0_0_o2_0_.INIT = 8'h45; + LUT3 plm_sym_lane3_bypass_reg_tx3_raw_char_pass_8_0_iv_i_0_0_0_o2_0_ ( + .I0(plm_sym_sym_bypass[1]), + .I1(plm_sym_sym_bypass[2]), + .I2(plm_sym_sym_pass[0]), + .O(plm_sym_N_56928_i) + ); + defparam plm_sym_lane0_bypass_reg_tx0_raw_char_8_0_0_0_i_a3_10_.INIT = 4'h2; + LUT2 plm_sym_lane0_bypass_reg_tx0_raw_char_8_0_0_0_i_a3_10_ ( + .I0(plm_sym_N_61309), + .I1(plm_sym_sym_bypass[1]), + .O(plm_sym_N_61348) + ); + defparam plm_sym_lane1_bypass_reg_tx1_raw_char_8_i_0_0_0_a2_7_.INIT = 4'h8; + LUT2 plm_sym_lane1_bypass_reg_tx1_raw_char_8_i_0_0_0_a2_7_ ( + .I0(plm_sym_N_61382), + .I1(plm_tx1_link_num[7]), + .O(plm_sym_N_58965) + ); + defparam plm_sym_lane1_bypass_reg_tx1_raw_char_8_i_0_0_i_a2_9_.INIT = 8'hC8; + LUT3 plm_sym_lane1_bypass_reg_tx1_raw_char_8_i_0_0_i_a2_9_ ( + .I0(plm_sym_sym_bypass[0]), + .I1(plm_sym_sym_bypass[1]), + .I2(plm_tx2_lane_pad), + .O(plm_sym_N_58963) + ); + defparam plm_sym_lane0_bypass_reg_tx0_raw_char_8_i_0_0_i_a2_9_.INIT = 8'hC8; + LUT3 plm_sym_lane0_bypass_reg_tx0_raw_char_8_i_0_0_i_a2_9_ ( + .I0(plm_sym_sym_bypass[0]), + .I1(plm_sym_sym_bypass[1]), + .I2(plm_tx0_lane_pad), + .O(plm_sym_N_58960) + ); + defparam plm_sym_lane1_bypass_reg_tx1_raw_char_8_0_0_0_i_a2_10_.INIT = 8'h8C; + LUT3 plm_sym_lane1_bypass_reg_tx1_raw_char_8_0_0_0_i_a2_10_ ( + .I0(plm_sym_sym_bypass[0]), + .I1(plm_sym_sym_bypass[1]), + .I2(plm_tx2_lane_pad), + .O(plm_sym_N_58232) + ); + defparam plm_sym_lane0_bypass_reg_tx0_raw_char_8_0_0_0_i_a2_10_.INIT = 8'h8C; + LUT3 plm_sym_lane0_bypass_reg_tx0_raw_char_8_0_0_0_i_a2_10_ ( + .I0(plm_sym_sym_bypass[0]), + .I1(plm_sym_sym_bypass[1]), + .I2(plm_tx0_lane_pad), + .O(plm_sym_N_58223) + ); + defparam plm_sym_lane0_bypass_reg_tx0_raw_char_is_k_8_i_m2_i_0_i_a2_1_.INIT = 8'h01; + LUT3 plm_sym_lane0_bypass_reg_tx0_raw_char_is_k_8_i_m2_i_0_i_a2_1_ ( + .I0(plm_sym_sym_bypass[1]), + .I1(plm_sym_sym_bypass[2]), + .I2(plm_sym_sym_is_k[1]), + .O(plm_sym_N_59407) + ); + defparam plm_sym_reg_sym_gen_sel_15_i_a3_0_2_.INIT = 8'h02; + LUT3 plm_sym_reg_sym_gen_sel_15_i_a3_0_2_ ( + .I0(plm_send_command[0]), + .I1(plm_send_command[1]), + .I2(plm_send_command[2]), + .O(plm_N_3288) + ); + defparam plm_sym_insert_ccs_6.INIT = 16'h0001; + LUT4_L plm_sym_insert_ccs_6 ( + .I0(plm_sym_reg_count[0]), + .I1(plm_sym_reg_count_6112[1]), + .I2(plm_sym_reg_count_6112[2]), + .I3(plm_sym_reg_count_6112[11]), + .LO(plm_sym_insert_ccs_6_1596) + ); + defparam plm_sym_insert_ccs_7.INIT = 16'h0001; + LUT4 plm_sym_insert_ccs_7 ( + .I0(plm_sym_reg_count_6112[3]), + .I1(plm_sym_reg_count_6112[4]), + .I2(plm_sym_reg_count_6112[5]), + .I3(plm_sym_reg_count_6112[6]), + .O(plm_sym_insert_ccs_7_1595) + ); + defparam plm_sym_insert_ccs_8.INIT = 16'h0001; + LUT4 plm_sym_insert_ccs_8 ( + .I0(plm_sym_reg_count_6112[7]), + .I1(plm_sym_reg_count_6112[8]), + .I2(plm_sym_reg_count_6112[9]), + .I3(plm_sym_reg_count_6112[10]), + .O(plm_sym_insert_ccs_8_1594) + ); + defparam plm_sym_lane3_bypass_reg_tx3_raw_char_8_0_i_0_0_a2_8_.INIT = 16'h4544; + LUT4 plm_sym_lane3_bypass_reg_tx3_raw_char_8_0_i_0_0_a2_8_ ( + .I0(plm_sym_sym_bypass[0]), + .I1(plm_sym_sym_bypass[1]), + .I2(plm_sym_sym_bypass[2]), + .I3(plm_sym_sym_symbol_0_), + .O(plm_sym_N_59366) + ); + defparam plm_sym_lane1_bypass_reg_tx1_raw_char_8_0_i_0_0_1_2_.INIT = 16'h135F; + LUT4 plm_sym_lane1_bypass_reg_tx1_raw_char_8_0_i_0_0_1_2_ ( + .I0(plm_sym_N_61369), + .I1(plm_sym_N_61382), + .I2(plm_sym_sym_symbol_2_), + .I3(plm_tx1_link_num[2]), + .O(plm_sym_N_36447_1_i) + ); + defparam plm_sym_lane0_bypass_reg_tx0_raw_char_8_0_0_0_i_a2_0_10_.INIT = 8'h02; + LUT3 plm_sym_lane0_bypass_reg_tx0_raw_char_8_0_0_0_i_a2_0_10_ ( + .I0(plm_sym_N_61369), + .I1(plm_sym_sym_bypass[1]), + .I2(plm_sym_sym_symbol_10_), + .O(plm_sym_N_58224) + ); + defparam plm_sym_lane0_bypass_reg_tx0_raw_char_8_0_0_0_i_a2_12_.INIT = 8'h02; + LUT3 plm_sym_lane0_bypass_reg_tx0_raw_char_8_0_0_0_i_a2_12_ ( + .I0(plm_sym_N_61369), + .I1(plm_sym_sym_bypass[1]), + .I2(plm_sym_sym_is_k[1]), + .O(plm_sym_N_58226) + ); + defparam plm_sym_lane0_bypass_reg_tx0_raw_char_8_0_0_0_i_a2_13_.INIT = 8'h02; + LUT3 plm_sym_lane0_bypass_reg_tx0_raw_char_8_0_0_0_i_a2_13_ ( + .I0(plm_sym_N_61369), + .I1(plm_sym_sym_bypass[1]), + .I2(plm_sym_sym_symbol_13_), + .O(plm_sym_N_58228) + ); + defparam plm_sym_lane0_bypass_reg_tx0_raw_char_8_0_0_0_i_a2_15_.INIT = 8'h02; + LUT3 plm_sym_lane0_bypass_reg_tx0_raw_char_8_0_0_0_i_a2_15_ ( + .I0(plm_sym_N_61369), + .I1(plm_sym_sym_bypass[1]), + .I2(plm_sym_sym_symbol_15_), + .O(plm_sym_N_58230) + ); + defparam plm_sym_lane0_bypass_reg_tx0_raw_char_8_i_0_0_i_a2_0_9_.INIT = 8'h20; + LUT3 plm_sym_lane0_bypass_reg_tx0_raw_char_8_i_0_0_i_a2_0_9_ ( + .I0(plm_sym_N_61369), + .I1(plm_sym_sym_bypass[1]), + .I2(plm_sym_sym_symbol_1_), + .O(plm_sym_N_58961) + ); + defparam plm_sym_lane0_bypass_reg_tx0_raw_char_8_i_0_0_0_a2_0_3_.INIT = 8'h20; + LUT3 plm_sym_lane0_bypass_reg_tx0_raw_char_8_i_0_0_0_a2_0_3_ ( + .I0(plm_sym_N_61382), + .I1(plm_tx0_link_pad), + .I2(plm_tx1_link_num[3]), + .O(plm_sym_N_58988) + ); + defparam plm_sym_lane3_bypass_reg_tx3_raw_char_8_i_i_0_i_1_11_.INIT = 8'h31; + LUT3 plm_sym_lane3_bypass_reg_tx3_raw_char_8_i_i_0_i_1_11_ ( + .I0(plm_sym_N_61369), + .I1(plm_sym_sym_bypass[1]), + .I2(plm_sym_sym_symbol_11_), + .O(plm_sym_reg_tx3_raw_char_8_i_i_0_i_1[11]) + ); + defparam plm_sym_lane1_bypass_reg_tx1_raw_char_is_k_8_0_a2_i_0_0_1_0_.INIT = 16'hAA2A; + LUT4 plm_sym_lane1_bypass_reg_tx1_raw_char_is_k_8_0_a2_i_0_0_1_0_ ( + .I0(plm_sym_N_56230_i), + .I1(plm_sym_sym_bypass[0]), + .I2(plm_sym_sym_bypass[2]), + .I3(plm_tx2_link_pad), + .O(plm_sym_reg_tx1_raw_char_is_k_8_0_a2_i_0_0_1[0]) + ); + defparam plm_sym_lane2_bypass_reg_tx2_raw_char_8_i_0_0_1_6_.INIT = 16'h135F; + LUT4 plm_sym_lane2_bypass_reg_tx2_raw_char_8_i_0_0_1_6_ ( + .I0(plm_sym_N_61369), + .I1(plm_sym_N_61382), + .I2(plm_sym_sym_symbol_6_), + .I3(plm_tx1_link_num[6]), + .O(plm_sym_N_36431_1_i) + ); + defparam plm_sym_lane2_bypass_reg_tx2_raw_char_8_i_0_0_1_5_.INIT = 16'h135F; + LUT4 plm_sym_lane2_bypass_reg_tx2_raw_char_8_i_0_0_1_5_ ( + .I0(plm_sym_N_61369), + .I1(plm_sym_N_61382), + .I2(plm_sym_sym_symbol_5_), + .I3(plm_tx1_link_num[5]), + .O(plm_sym_N_36433_1_i) + ); + defparam plm_sym_lane2_bypass_reg_tx2_raw_char_8_0_i_0_0_1_4_.INIT = 16'h135F; + LUT4 plm_sym_lane2_bypass_reg_tx2_raw_char_8_0_i_0_0_1_4_ ( + .I0(plm_sym_N_61369), + .I1(plm_sym_N_61382), + .I2(plm_sym_sym_is_k[0]), + .I3(plm_tx1_link_num[4]), + .O(plm_sym_N_36435_1_i) + ); + defparam plm_sym_lane2_bypass_reg_tx2_raw_char_8_i_0_0_1_3_.INIT = 16'h45CF; + LUT4 plm_sym_lane2_bypass_reg_tx2_raw_char_8_i_0_0_1_3_ ( + .I0(plm_sym_N_61369), + .I1(plm_sym_reg_tx1_raw_char_8_i_0_0_0_o3[3]), + .I2(plm_sym_sym_bypass[1]), + .I3(plm_sym_sym_symbol_3_), + .O(plm_sym_N_36437_1_i) + ); + defparam plm_sym_lane0_bypass_reg_tx0_raw_char_8_1_i_0_0_1_1_.INIT = 8'h15; + LUT3 plm_sym_lane0_bypass_reg_tx0_raw_char_8_1_i_0_0_1_1_ ( + .I0(plm_sym_N_58978), + .I1(plm_sym_N_61382), + .I2(plm_tx1_link_num[1]), + .O(plm_sym_N_36449_1_i) + ); + defparam plm_sym_lane0_bypass_reg_tx0_raw_char_8_i_0_0_0_o2_7_.INIT = 8'h9B; + LUT3 plm_sym_lane0_bypass_reg_tx0_raw_char_8_i_0_0_0_o2_7_ ( + .I0(plm_sym_sym_bypass[0]), + .I1(plm_sym_sym_bypass[1]), + .I2(plm_tx0_link_pad), + .O(plm_sym_N_55945_i) + ); + defparam plm_sym_lane1_bypass_reg_tx1_raw_char_8_i_0_0_0_o2_7_.INIT = 8'h9B; + LUT3 plm_sym_lane1_bypass_reg_tx1_raw_char_8_i_0_0_0_o2_7_ ( + .I0(plm_sym_sym_bypass[0]), + .I1(plm_sym_sym_bypass[1]), + .I2(plm_tx2_link_pad), + .O(plm_sym_N_55888_i) + ); + defparam plm_sym_lane0_bypass_reg_tx0_raw_char_8_i_0_0_0_0_39382.INIT = 16'hDCDF; + LUT4 plm_sym_lane0_bypass_reg_tx0_raw_char_8_i_0_0_0_0_39382 ( + .I0(plm_frm0_char[0]), + .I1(plm_sym_sym_bypass[0]), + .I2(plm_sym_sym_bypass[2]), + .I3(plm_sym_sym_symbol_0_), + .O(plm_sym_reg_tx0_raw_char_8_i_0_0_0_0_39382) + ); + defparam plm_sym_lane0_bypass_reg_tx0_raw_char_is_k_8_0_a2_i_0_0_0_0_.INIT = 16'hAA2A; + LUT4_L plm_sym_lane0_bypass_reg_tx0_raw_char_is_k_8_0_a2_i_0_0_0_0_ ( + .I0(plm_sym_N_56230_i), + .I1(plm_sym_sym_bypass[0]), + .I2(plm_sym_sym_bypass[2]), + .I3(plm_tx0_link_pad), + .LO(plm_sym_reg_tx0_raw_char_is_k_8_0_a2_i_0_0_0[0]) + ); + defparam plm_sym_lane1_bypass_reg_tx1_raw_char_8_i_0_0_0_o2_0_0_.INIT = 16'h153F; + LUT4_L plm_sym_lane1_bypass_reg_tx1_raw_char_8_i_0_0_0_o2_0_0_ ( + .I0(plm_sym_N_61369), + .I1(plm_link_ctrl[0]), + .I2(plm_sym_sym_bypass[1]), + .I3(plm_sym_sym_symbol_0_), + .LO(plm_sym_reg_tx1_raw_char_8_i_0_0_0_o2_0[0]) + ); + defparam plm_sym_lane1_bypass_reg_tx1_raw_char_8_2_0_am_4_.INIT = 8'hB8; + LUT3 plm_sym_lane1_bypass_reg_tx1_raw_char_8_2_0_am_4_ ( + .I0(plm_frm1_char[4]), + .I1(plm_sym_sym_bypass[2]), + .I2(plm_sym_sym_is_k[0]), + .O(plm_sym_reg_tx1_raw_char_8_2_0_am[4]) + ); + defparam plm_sym_lane1_bypass_reg_tx1_raw_char_8_2_0_bm_4_.INIT = 8'h54; + LUT3 plm_sym_lane1_bypass_reg_tx1_raw_char_8_2_0_bm_4_ ( + .I0(plm_sym_sym_bypass[1]), + .I1(plm_tx1_link_num[4]), + .I2(plm_tx2_link_pad), + .O(plm_sym_reg_tx1_raw_char_8_2_0_bm[4]) + ); + MUXF5 plm_sym_lane1_bypass_reg_tx1_raw_char_8_2_0_4_ ( + .I0(plm_sym_reg_tx1_raw_char_8_2_0_am[4]), + .I1(plm_sym_reg_tx1_raw_char_8_2_0_bm[4]), + .O(plm_sym_N_38074), + .S(plm_sym_sym_bypass[0]) + ); + defparam plm_sym_reg_sym_gen_sel_15_i_0_.INIT = 16'hC88C; + LUT4_L plm_sym_reg_sym_gen_sel_15_i_0_ ( + .I0(plm_N_55932_i), + .I1(plm_send_command[0]), + .I2(plm_send_command[1]), + .I3(plm_send_command[2]), + .LO(plm_sym_reg_sym_gen_sel_15[0]) + ); + defparam plm_sym_lane1_bypass_reg_tx1_raw_char_8_i_0_0_0_1_3_.INIT = 16'hAA2A; + LUT4 plm_sym_lane1_bypass_reg_tx1_raw_char_8_i_0_0_0_1_3_ ( + .I0(plm_sym_N_36437_1_i), + .I1(plm_sym_N_61382), + .I2(plm_tx1_link_num[3]), + .I3(plm_tx2_link_pad), + .O(plm_sym_N_85603_1) + ); + defparam plm_sym_reg_sym_gen_sel_2_.INIT = 16'h0501; + LUT4 plm_sym_reg_sym_gen_sel_2_ ( + .I0(plm_N_3288), + .I1(plm_N_55932_i), + .I2(plm_frm_atomic), + .I3(plm_send_command[2]), + .O(plm_sym_reg_sym_gen_sel[2]) + ); + defparam plm_sym_insert_ccs.INIT = 8'h80; + LUT3 plm_sym_insert_ccs ( + .I0(plm_sym_insert_ccs_6_1596), + .I1(plm_sym_insert_ccs_7_1595), + .I2(plm_sym_insert_ccs_8_1594), + .O(plm_sym_insert_ccs_1612) + ); + defparam plm_sym_reg_sym_gen_sel_1_.INIT = 16'h0E00; + LUT4 plm_sym_reg_sym_gen_sel_1_ ( + .I0(plm_sym_N_10027), + .I1(plm_N_55932_i), + .I2(plm_frm_atomic), + .I3(plm_send_command[1]), + .O(plm_sym_reg_sym_gen_sel[1]) + ); + defparam plm_sym_lane0_bypass_reg_tx0_raw_char_8_i_0_0_0_0_39381.INIT = 8'h2A; + LUT3_L plm_sym_lane0_bypass_reg_tx0_raw_char_8_i_0_0_0_0_39381 ( + .I0(plm_sym_N_55945_i), + .I1(plm_sym_N_61382), + .I2(plm_tx1_link_num[0]), + .LO(plm_sym_reg_tx0_raw_char_8_i_0_0_0_0_39381) + ); + defparam plm_sym_reg_sym_gen_sel_0_.INIT = 4'h1; + LUT2 plm_sym_reg_sym_gen_sel_0_ ( + .I0(plm_frm_atomic), + .I1(plm_sym_reg_sym_gen_sel_15[0]), + .O(plm_sym_N_10147) + ); + defparam plm_sym_lane1_bypass_reg_tx1_raw_char_8_i_0_0_0_o2_0_.INIT = 16'h20A0; + LUT4 plm_sym_lane1_bypass_reg_tx1_raw_char_8_i_0_0_0_o2_0_ ( + .I0(plm_sym_N_55888_i), + .I1(plm_sym_N_61382), + .I2(plm_sym_reg_tx1_raw_char_8_i_0_0_0_o2_0[0]), + .I3(plm_tx1_link_num[0]), + .O(plm_sym_reg_tx1_raw_char_8_i_0_0_0_o2[0]) + ); + defparam plm_sym_un1_reg_tx0_raw_char_pass_f1_1_0_.INIT = 8'hF9; + LUT3 plm_sym_un1_reg_tx0_raw_char_pass_f1_1_0_ ( + .I0(plm_sym_sent_status[4]), + .I1(plm_sym_frm_dispatched_ccs_1600), + .I2(plm_sym_insert_ccs_1612), + .O(plm_sym_N_9419_1) + ); + defparam plm_sym_un1_reg_tx0_raw_char_pass_f1_0_0_.INIT = 8'h6F; + LUT3 plm_sym_un1_reg_tx0_raw_char_pass_f1_0_0_ ( + .I0(plm_sym_sent_status[4]), + .I1(plm_sym_frm_dispatched_ccs_1600), + .I2(plm_sym_insert_ccs_1612), + .O(plm_sym_un1_reg_tx0_raw_char_pass_f1_0[0]) + ); + defparam plm_sym_un1_reg_outstanding_ccs_1_axb_0.INIT = 8'h93; + LUT3 plm_sym_un1_reg_outstanding_ccs_1_axb_0 ( + .I0(plm_sym_N_9419_1), + .I1(plm_reg_outstanding_ccs[0]), + .I2(plm_sym_un1_reg_tx0_raw_char_pass_f1_0[0]), + .O(plm_sym_un1_reg_outstanding_ccs_1_axb_0_1617) + ); + defparam plm_sym_lane0_bypass_N_85608_i.INIT = 16'hFDDD; + LUT4_L plm_sym_lane0_bypass_N_85608_i ( + .I0(plm_sym_N_36437_1_i), + .I1(plm_sym_N_58988), + .I2(plm_sym_N_61309), + .I3(plm_frm0_char[3]), + .LO(plm_sym_N_85608_i) + ); + defparam plm_sym_lane0_bypass_N_85609_i.INIT = 16'hF777; + LUT4_L plm_sym_lane0_bypass_N_85609_i ( + .I0(plm_sym_N_36447_1_i), + .I1(plm_sym_N_55945_i), + .I2(plm_sym_N_61309), + .I3(plm_frm0_char[2]), + .LO(plm_sym_N_85609_i) + ); + defparam plm_sym_lane0_bypass_N_85640_i.INIT = 16'hF777; + LUT4_L plm_sym_lane0_bypass_N_85640_i ( + .I0(plm_sym_N_36449_1_i), + .I1(plm_sym_N_55945_i), + .I2(plm_sym_N_61309), + .I3(plm_frm0_char[1]), + .LO(plm_sym_N_85640_i) + ); + defparam plm_sym_lane0_bypass_N_85610_i.INIT = 16'hF777; + LUT4_L plm_sym_lane0_bypass_N_85610_i ( + .I0(plm_sym_reg_tx0_raw_char_8_i_0_0_0_0_39381), + .I1(plm_sym_reg_tx0_raw_char_8_i_0_0_0_0_39382), + .I2(plm_link_ctrl[0]), + .I3(plm_sym_sym_bypass[1]), + .LO(plm_sym_N_85610_i) + ); + defparam plm_sym_un1_reg_outstanding_ccs_1_axb_3.INIT = 16'h718E; + LUT4_L plm_sym_un1_reg_outstanding_ccs_1_axb_3 ( + .I0(plm_sym_sent_status[4]), + .I1(plm_sym_frm_dispatched_ccs_1600), + .I2(plm_sym_insert_ccs_1612), + .I3(plm_reg_outstanding_ccs[3]), + .LO(plm_sym_un1_reg_outstanding_ccs_1_axb_3_1597) + ); + defparam plm_sym_un1_reg_outstanding_ccs_1_axb_2.INIT = 16'h718E; + LUT4_L plm_sym_un1_reg_outstanding_ccs_1_axb_2 ( + .I0(plm_sym_sent_status[4]), + .I1(plm_sym_frm_dispatched_ccs_1600), + .I2(plm_sym_insert_ccs_1612), + .I3(plm_reg_outstanding_ccs[2]), + .LO(plm_sym_un1_reg_outstanding_ccs_1_axb_2_1598) + ); + defparam plm_sym_un1_reg_outstanding_ccs_1_axb_1.INIT = 16'h718E; + LUT4_L plm_sym_un1_reg_outstanding_ccs_1_axb_1 ( + .I0(plm_sym_sent_status[4]), + .I1(plm_sym_frm_dispatched_ccs_1600), + .I2(plm_sym_insert_ccs_1612), + .I3(plm_reg_outstanding_ccs[1]), + .LO(plm_sym_un1_reg_outstanding_ccs_1_axb_1_1599) + ); + defparam plm_sym_lane1_bypass_N_85639_i.INIT = 16'hF777; + LUT4_L plm_sym_lane1_bypass_N_85639_i ( + .I0(plm_sym_N_36447_1_i), + .I1(plm_sym_N_55888_i), + .I2(plm_sym_N_61309), + .I3(plm_frm1_char[2]), + .LO(plm_sym_N_85639_i) + ); + defparam plm_sym_lane1_bypass_N_85604_i.INIT = 16'hF777; + LUT4_L plm_sym_lane1_bypass_N_85604_i ( + .I0(plm_sym_N_36449_1_i), + .I1(plm_sym_N_55888_i), + .I2(plm_sym_N_61309), + .I3(plm_frm1_char[1]), + .LO(plm_sym_N_85604_i) + ); + defparam plm_sym_lane1_bypass_N_87198_i.INIT = 8'hB3; + LUT3_L plm_sym_lane1_bypass_N_87198_i ( + .I0(plm_sym_N_61309), + .I1(plm_sym_reg_tx1_raw_char_8_i_0_0_0_o2[0]), + .I2(plm_frm1_char[0]), + .LO(plm_sym_N_87198_i) + ); + defparam plm_sym_lane0_bypass_reg_tx0_raw_char_8_0_0_0_i_15_.INIT = 16'h1101; + LUT4_L plm_sym_lane0_bypass_reg_tx0_raw_char_8_0_0_0_i_15_ ( + .I0(plm_sym_N_58223), + .I1(plm_sym_N_58230), + .I2(plm_sym_N_61348), + .I3(plm_frm0_char[15]), + .LO(plm_sym_N_51828_i) + ); + defparam plm_sym_lane0_bypass_reg_tx0_raw_char_8_i_i_0_i_14_.INIT = 16'h3202; + LUT4_L plm_sym_lane0_bypass_reg_tx0_raw_char_8_i_i_0_i_14_ ( + .I0(plm_sym_N_56624), + .I1(plm_sym_sym_bypass[0]), + .I2(plm_sym_sym_bypass[1]), + .I3(plm_tx0_lane_pad), + .LO(plm_sym_N_53136_i) + ); + defparam plm_sym_lane0_bypass_reg_tx0_raw_char_8_0_0_0_i_13_.INIT = 16'h1101; + LUT4_L plm_sym_lane0_bypass_reg_tx0_raw_char_8_0_0_0_i_13_ ( + .I0(plm_sym_N_58223), + .I1(plm_sym_N_58228), + .I2(plm_sym_N_61348), + .I3(plm_frm0_char[13]), + .LO(plm_sym_N_51826_i) + ); + defparam plm_sym_lane0_bypass_reg_tx0_raw_char_8_0_0_0_i_12_.INIT = 16'h1101; + LUT4_L plm_sym_lane0_bypass_reg_tx0_raw_char_8_0_0_0_i_12_ ( + .I0(plm_sym_N_58223), + .I1(plm_sym_N_58226), + .I2(plm_sym_N_61348), + .I3(plm_frm0_char[12]), + .LO(plm_sym_N_51824_i) + ); + defparam plm_sym_lane0_bypass_reg_tx0_raw_char_8_i_i_0_i_11_.INIT = 8'hC4; + LUT3_L plm_sym_lane0_bypass_reg_tx0_raw_char_8_i_i_0_i_11_ ( + .I0(plm_sym_N_61309), + .I1(plm_sym_reg_tx3_raw_char_8_i_i_0_i_1[11]), + .I2(plm_frm0_char[11]), + .LO(plm_sym_N_53134_i) + ); + defparam plm_sym_lane0_bypass_reg_tx0_raw_char_8_0_0_0_i_10_.INIT = 16'h1101; + LUT4_L plm_sym_lane0_bypass_reg_tx0_raw_char_8_0_0_0_i_10_ ( + .I0(plm_sym_N_58223), + .I1(plm_sym_N_58224), + .I2(plm_sym_N_61348), + .I3(plm_frm0_char[10]), + .LO(plm_sym_N_51822_i) + ); + defparam plm_sym_lane0_bypass_N_85560_i.INIT = 16'hFEEE; + LUT4_L plm_sym_lane0_bypass_N_85560_i ( + .I0(plm_sym_N_58960), + .I1(plm_sym_N_58961), + .I2(plm_sym_N_61348), + .I3(plm_frm0_char[9]), + .LO(plm_sym_N_85560_i) + ); + defparam plm_sym_lane0_bypass_reg_tx0_raw_char_8_i_i_0_i_8_.INIT = 16'h3202; + LUT4_L plm_sym_lane0_bypass_reg_tx0_raw_char_8_i_i_0_i_8_ ( + .I0(plm_sym_N_56623), + .I1(plm_sym_sym_bypass[0]), + .I2(plm_sym_sym_bypass[1]), + .I3(plm_tx0_lane_pad), + .LO(plm_sym_N_53132_i) + ); + defparam plm_sym_lane0_bypass_N_85562_i.INIT = 16'hFDDD; + LUT4_L plm_sym_lane0_bypass_N_85562_i ( + .I0(plm_sym_N_55945_i), + .I1(plm_sym_N_58965), + .I2(plm_sym_N_61309), + .I3(plm_frm0_char[7]), + .LO(plm_sym_N_85562_i) + ); + defparam plm_sym_lane0_bypass_N_85605_i.INIT = 16'hF777; + LUT4_L plm_sym_lane0_bypass_N_85605_i ( + .I0(plm_sym_N_36431_1_i), + .I1(plm_sym_N_55945_i), + .I2(plm_sym_N_61309), + .I3(plm_frm0_char[6]), + .LO(plm_sym_N_85605_i) + ); + defparam plm_sym_lane0_bypass_N_85606_i.INIT = 16'hF777; + LUT4_L plm_sym_lane0_bypass_N_85606_i ( + .I0(plm_sym_N_36433_1_i), + .I1(plm_sym_N_55945_i), + .I2(plm_sym_N_61309), + .I3(plm_frm0_char[5]), + .LO(plm_sym_N_85606_i) + ); + defparam plm_sym_lane0_bypass_N_85607_i.INIT = 16'hF777; + LUT4_L plm_sym_lane0_bypass_N_85607_i ( + .I0(plm_sym_N_36435_1_i), + .I1(plm_sym_N_55945_i), + .I2(plm_sym_N_61309), + .I3(plm_frm0_char[4]), + .LO(plm_sym_N_85607_i) + ); + defparam plm_sym_lane2_bypass_N_85638_i.INIT = 16'hF777; + LUT4_L plm_sym_lane2_bypass_N_85638_i ( + .I0(plm_sym_N_36449_1_i), + .I1(plm_sym_N_55888_i), + .I2(plm_sym_N_61309), + .I3(plm_frm2_char[1]), + .LO(plm_sym_N_85638_i) + ); + defparam plm_sym_lane2_bypass_N_87225_i.INIT = 8'hB3; + LUT3_L plm_sym_lane2_bypass_N_87225_i ( + .I0(plm_sym_N_61309), + .I1(plm_sym_reg_tx1_raw_char_8_i_0_0_0_o2[0]), + .I2(plm_frm2_char[0]), + .LO(plm_sym_N_87225_i) + ); + defparam plm_sym_lane1_bypass_reg_tx1_raw_char_8_0_0_0_i_15_.INIT = 16'h1101; + LUT4_L plm_sym_lane1_bypass_reg_tx1_raw_char_8_0_0_0_i_15_ ( + .I0(plm_sym_N_58230), + .I1(plm_sym_N_58232), + .I2(plm_sym_N_61348), + .I3(plm_frm1_char[15]), + .LO(plm_sym_N_51838_i) + ); + defparam plm_sym_lane1_bypass_reg_tx1_raw_char_8_0_0_0_i_14_.INIT = 16'h3202; + LUT4_L plm_sym_lane1_bypass_reg_tx1_raw_char_8_0_0_0_i_14_ ( + .I0(plm_sym_N_56524), + .I1(plm_sym_sym_bypass[0]), + .I2(plm_sym_sym_bypass[1]), + .I3(plm_tx2_lane_pad), + .LO(plm_sym_N_51836_i) + ); + defparam plm_sym_lane1_bypass_reg_tx1_raw_char_8_0_0_0_i_13_.INIT = 16'h1101; + LUT4_L plm_sym_lane1_bypass_reg_tx1_raw_char_8_0_0_0_i_13_ ( + .I0(plm_sym_N_58228), + .I1(plm_sym_N_58232), + .I2(plm_sym_N_61348), + .I3(plm_frm1_char[13]), + .LO(plm_sym_N_51834_i) + ); + defparam plm_sym_lane1_bypass_reg_tx1_raw_char_8_0_0_0_i_12_.INIT = 16'h1101; + LUT4_L plm_sym_lane1_bypass_reg_tx1_raw_char_8_0_0_0_i_12_ ( + .I0(plm_sym_N_58226), + .I1(plm_sym_N_58232), + .I2(plm_sym_N_61348), + .I3(plm_frm1_char[12]), + .LO(plm_sym_N_51832_i) + ); + defparam plm_sym_lane1_bypass_reg_tx1_raw_char_8_i_i_0_i_11_.INIT = 8'hC4; + LUT3_L plm_sym_lane1_bypass_reg_tx1_raw_char_8_i_i_0_i_11_ ( + .I0(plm_sym_N_61309), + .I1(plm_sym_reg_tx3_raw_char_8_i_i_0_i_1[11]), + .I2(plm_frm1_char[11]), + .LO(plm_sym_N_53138_i) + ); + defparam plm_sym_lane1_bypass_reg_tx1_raw_char_8_0_0_0_i_10_.INIT = 16'h1101; + LUT4_L plm_sym_lane1_bypass_reg_tx1_raw_char_8_0_0_0_i_10_ ( + .I0(plm_sym_N_58224), + .I1(plm_sym_N_58232), + .I2(plm_sym_N_61348), + .I3(plm_frm1_char[10]), + .LO(plm_sym_N_51830_i) + ); + defparam plm_sym_lane1_bypass_N_85561_i.INIT = 16'hFEEE; + LUT4_L plm_sym_lane1_bypass_N_85561_i ( + .I0(plm_sym_N_58961), + .I1(plm_sym_N_58963), + .I2(plm_sym_N_61348), + .I3(plm_frm1_char[9]), + .LO(plm_sym_N_85561_i) + ); + defparam plm_sym_lane1_bypass_N_87567_i.INIT = 8'hEA; + LUT3_L plm_sym_lane1_bypass_N_87567_i ( + .I0(plm_sym_N_59366), + .I1(plm_sym_N_61309), + .I2(plm_frm1_char[8]), + .LO(plm_sym_N_87567_i) + ); + defparam plm_sym_lane1_bypass_N_87486_i.INIT = 16'hFDDD; + LUT4_L plm_sym_lane1_bypass_N_87486_i ( + .I0(plm_sym_N_55888_i), + .I1(plm_sym_N_58965), + .I2(plm_sym_N_61309), + .I3(plm_frm1_char[7]), + .LO(plm_sym_N_87486_i) + ); + defparam plm_sym_lane1_bypass_N_85601_i.INIT = 16'hF777; + LUT4_L plm_sym_lane1_bypass_N_85601_i ( + .I0(plm_sym_N_36431_1_i), + .I1(plm_sym_N_55888_i), + .I2(plm_sym_N_61309), + .I3(plm_frm1_char[6]), + .LO(plm_sym_N_85601_i) + ); + defparam plm_sym_lane1_bypass_N_85602_i.INIT = 16'hF777; + LUT4_L plm_sym_lane1_bypass_N_85602_i ( + .I0(plm_sym_N_36433_1_i), + .I1(plm_sym_N_55888_i), + .I2(plm_sym_N_61309), + .I3(plm_frm1_char[5]), + .LO(plm_sym_N_85602_i) + ); + defparam plm_sym_lane1_bypass_N_87094_i.INIT = 8'hBA; + LUT3_L plm_sym_lane1_bypass_N_87094_i ( + .I0(plm_sym_N_38074), + .I1(plm_sym_sym_bypass[0]), + .I2(plm_sym_sym_bypass[1]), + .LO(plm_sym_N_87094_i) + ); + defparam plm_sym_lane1_bypass_N_85603_i.INIT = 8'hB3; + LUT3_L plm_sym_lane1_bypass_N_85603_i ( + .I0(plm_sym_N_61309), + .I1(plm_sym_N_85603_1), + .I2(plm_frm1_char[3]), + .LO(plm_sym_N_85603_i) + ); + defparam plm_sym_lane3_bypass_N_87224_i.INIT = 8'hB3; + LUT3_L plm_sym_lane3_bypass_N_87224_i ( + .I0(plm_sym_N_61309), + .I1(plm_sym_reg_tx1_raw_char_8_i_0_0_0_o2[0]), + .I2(plm_frm3_char[0]), + .LO(plm_sym_N_87224_i) + ); + defparam plm_sym_lane2_bypass_reg_tx2_raw_char_8_0_0_0_i_15_.INIT = 16'h1101; + LUT4_L plm_sym_lane2_bypass_reg_tx2_raw_char_8_0_0_0_i_15_ ( + .I0(plm_sym_N_58230), + .I1(plm_sym_N_58232), + .I2(plm_sym_N_61348), + .I3(plm_frm2_char[15]), + .LO(plm_sym_N_51850_i) + ); + defparam plm_sym_lane2_bypass_reg_tx2_raw_char_8_0_0_0_i_14_.INIT = 16'h3202; + LUT4_L plm_sym_lane2_bypass_reg_tx2_raw_char_8_0_0_0_i_14_ ( + .I0(plm_sym_N_56525), + .I1(plm_sym_sym_bypass[0]), + .I2(plm_sym_sym_bypass[1]), + .I3(plm_tx2_lane_pad), + .LO(plm_sym_N_51848_i) + ); + defparam plm_sym_lane2_bypass_reg_tx2_raw_char_8_0_0_0_i_13_.INIT = 16'h1101; + LUT4_L plm_sym_lane2_bypass_reg_tx2_raw_char_8_0_0_0_i_13_ ( + .I0(plm_sym_N_58228), + .I1(plm_sym_N_58232), + .I2(plm_sym_N_61348), + .I3(plm_frm2_char[13]), + .LO(plm_sym_N_51846_i) + ); + defparam plm_sym_lane2_bypass_reg_tx2_raw_char_8_0_0_0_i_12_.INIT = 16'h1101; + LUT4_L plm_sym_lane2_bypass_reg_tx2_raw_char_8_0_0_0_i_12_ ( + .I0(plm_sym_N_58226), + .I1(plm_sym_N_58232), + .I2(plm_sym_N_61348), + .I3(plm_frm2_char[12]), + .LO(plm_sym_N_51844_i) + ); + defparam plm_sym_lane2_bypass_reg_tx2_raw_char_8_0_0_0_i_11_.INIT = 8'hC4; + LUT3_L plm_sym_lane2_bypass_reg_tx2_raw_char_8_0_0_0_i_11_ ( + .I0(plm_sym_N_61309), + .I1(plm_sym_reg_tx3_raw_char_8_i_i_0_i_1[11]), + .I2(plm_frm2_char[11]), + .LO(plm_sym_N_51842_i) + ); + defparam plm_sym_lane2_bypass_reg_tx2_raw_char_8_0_0_0_i_10_.INIT = 16'h1101; + LUT4_L plm_sym_lane2_bypass_reg_tx2_raw_char_8_0_0_0_i_10_ ( + .I0(plm_sym_N_58224), + .I1(plm_sym_N_58232), + .I2(plm_sym_N_61348), + .I3(plm_frm2_char[10]), + .LO(plm_sym_N_51840_i) + ); + defparam plm_sym_lane2_bypass_N_87475_i.INIT = 16'hFFEA; + LUT4_L plm_sym_lane2_bypass_N_87475_i ( + .I0(plm_sym_N_58978), + .I1(plm_sym_N_61309), + .I2(plm_frm2_char[9]), + .I3(plm_sym_sym_bypass[1]), + .LO(plm_sym_N_87475_i) + ); + defparam plm_sym_lane2_bypass_reg_tx2_raw_char_8_i_i_0_i_8_.INIT = 16'h3202; + LUT4_L plm_sym_lane2_bypass_reg_tx2_raw_char_8_i_i_0_i_8_ ( + .I0(plm_sym_N_56625), + .I1(plm_sym_sym_bypass[0]), + .I2(plm_sym_sym_bypass[1]), + .I3(plm_tx2_lane_pad), + .LO(plm_sym_N_53140_i) + ); + defparam plm_sym_lane2_bypass_N_87478_i.INIT = 16'hFDDD; + LUT4_L plm_sym_lane2_bypass_N_87478_i ( + .I0(plm_sym_N_55888_i), + .I1(plm_sym_N_58965), + .I2(plm_sym_N_61309), + .I3(plm_frm2_char[7]), + .LO(plm_sym_N_87478_i) + ); + defparam plm_sym_lane2_bypass_N_85633_i.INIT = 16'hF777; + LUT4_L plm_sym_lane2_bypass_N_85633_i ( + .I0(plm_sym_N_36431_1_i), + .I1(plm_sym_N_55888_i), + .I2(plm_sym_N_61309), + .I3(plm_frm2_char[6]), + .LO(plm_sym_N_85633_i) + ); + defparam plm_sym_lane2_bypass_N_85634_i.INIT = 16'hF777; + LUT4_L plm_sym_lane2_bypass_N_85634_i ( + .I0(plm_sym_N_36433_1_i), + .I1(plm_sym_N_55888_i), + .I2(plm_sym_N_61309), + .I3(plm_frm2_char[5]), + .LO(plm_sym_N_85634_i) + ); + defparam plm_sym_lane2_bypass_N_85635_i.INIT = 16'hF777; + LUT4_L plm_sym_lane2_bypass_N_85635_i ( + .I0(plm_sym_N_36435_1_i), + .I1(plm_sym_N_55888_i), + .I2(plm_sym_N_61309), + .I3(plm_frm2_char[4]), + .LO(plm_sym_N_85635_i) + ); + defparam plm_sym_lane2_bypass_N_85636_i.INIT = 8'hB3; + LUT3_L plm_sym_lane2_bypass_N_85636_i ( + .I0(plm_sym_N_61309), + .I1(plm_sym_N_85603_1), + .I2(plm_frm2_char[3]), + .LO(plm_sym_N_85636_i) + ); + defparam plm_sym_lane2_bypass_N_85637_i.INIT = 16'hF777; + LUT4_L plm_sym_lane2_bypass_N_85637_i ( + .I0(plm_sym_N_36447_1_i), + .I1(plm_sym_N_55888_i), + .I2(plm_sym_N_61309), + .I3(plm_frm2_char[2]), + .LO(plm_sym_N_85637_i) + ); + defparam plm_sym_lane3_bypass_reg_tx3_raw_char_8_0_0_0_i_15_.INIT = 16'h1101; + LUT4_L plm_sym_lane3_bypass_reg_tx3_raw_char_8_0_0_0_i_15_ ( + .I0(plm_sym_N_58230), + .I1(plm_sym_N_58232), + .I2(plm_sym_N_61348), + .I3(plm_frm3_char[15]), + .LO(plm_sym_N_51860_i) + ); + defparam plm_sym_lane3_bypass_reg_tx3_raw_char_8_0_0_0_i_14_.INIT = 16'h3202; + LUT4_L plm_sym_lane3_bypass_reg_tx3_raw_char_8_0_0_0_i_14_ ( + .I0(plm_sym_N_56526), + .I1(plm_sym_sym_bypass[0]), + .I2(plm_sym_sym_bypass[1]), + .I3(plm_tx2_lane_pad), + .LO(plm_sym_N_51858_i) + ); + defparam plm_sym_lane3_bypass_reg_tx3_raw_char_8_0_0_0_i_13_.INIT = 16'h1101; + LUT4_L plm_sym_lane3_bypass_reg_tx3_raw_char_8_0_0_0_i_13_ ( + .I0(plm_sym_N_58228), + .I1(plm_sym_N_58232), + .I2(plm_sym_N_61348), + .I3(plm_frm3_char[13]), + .LO(plm_sym_N_51856_i) + ); + defparam plm_sym_lane3_bypass_reg_tx3_raw_char_8_0_0_0_i_12_.INIT = 16'h1101; + LUT4_L plm_sym_lane3_bypass_reg_tx3_raw_char_8_0_0_0_i_12_ ( + .I0(plm_sym_N_58226), + .I1(plm_sym_N_58232), + .I2(plm_sym_N_61348), + .I3(plm_frm3_char[12]), + .LO(plm_sym_N_51854_i) + ); + defparam plm_sym_lane3_bypass_reg_tx3_raw_char_8_i_i_0_i_11_.INIT = 8'hC4; + LUT3_L plm_sym_lane3_bypass_reg_tx3_raw_char_8_i_i_0_i_11_ ( + .I0(plm_sym_N_61309), + .I1(plm_sym_reg_tx3_raw_char_8_i_i_0_i_1[11]), + .I2(plm_frm3_char[11]), + .LO(plm_sym_N_53142_i) + ); + defparam plm_sym_lane3_bypass_reg_tx3_raw_char_8_0_0_0_i_10_.INIT = 16'h1101; + LUT4_L plm_sym_lane3_bypass_reg_tx3_raw_char_8_0_0_0_i_10_ ( + .I0(plm_sym_N_58224), + .I1(plm_sym_N_58232), + .I2(plm_sym_N_61348), + .I3(plm_frm3_char[10]), + .LO(plm_sym_N_51852_i) + ); + defparam plm_sym_lane3_bypass_N_87476_i.INIT = 16'hFFEA; + LUT4_L plm_sym_lane3_bypass_N_87476_i ( + .I0(plm_sym_N_58978), + .I1(plm_sym_N_61309), + .I2(plm_frm3_char[9]), + .I3(plm_sym_sym_bypass[1]), + .LO(plm_sym_N_87476_i) + ); + defparam plm_sym_lane3_bypass_N_87568_i.INIT = 8'hEA; + LUT3_L plm_sym_lane3_bypass_N_87568_i ( + .I0(plm_sym_N_59366), + .I1(plm_sym_N_61309), + .I2(plm_frm3_char[8]), + .LO(plm_sym_N_87568_i) + ); + defparam plm_sym_lane3_bypass_N_87479_i.INIT = 16'hFDDD; + LUT4_L plm_sym_lane3_bypass_N_87479_i ( + .I0(plm_sym_N_55888_i), + .I1(plm_sym_N_58965), + .I2(plm_sym_N_61309), + .I3(plm_frm3_char[7]), + .LO(plm_sym_N_87479_i) + ); + defparam plm_sym_lane3_bypass_N_85627_i.INIT = 16'hF777; + LUT4_L plm_sym_lane3_bypass_N_85627_i ( + .I0(plm_sym_N_36431_1_i), + .I1(plm_sym_N_55888_i), + .I2(plm_sym_N_61309), + .I3(plm_frm3_char[6]), + .LO(plm_sym_N_85627_i) + ); + defparam plm_sym_lane3_bypass_N_85628_i.INIT = 16'hF777; + LUT4_L plm_sym_lane3_bypass_N_85628_i ( + .I0(plm_sym_N_36433_1_i), + .I1(plm_sym_N_55888_i), + .I2(plm_sym_N_61309), + .I3(plm_frm3_char[5]), + .LO(plm_sym_N_85628_i) + ); + defparam plm_sym_lane3_bypass_N_85629_i.INIT = 16'hF777; + LUT4_L plm_sym_lane3_bypass_N_85629_i ( + .I0(plm_sym_N_36435_1_i), + .I1(plm_sym_N_55888_i), + .I2(plm_sym_N_61309), + .I3(plm_frm3_char[4]), + .LO(plm_sym_N_85629_i) + ); + defparam plm_sym_lane3_bypass_N_85630_i.INIT = 8'hB3; + LUT3_L plm_sym_lane3_bypass_N_85630_i ( + .I0(plm_sym_N_61309), + .I1(plm_sym_N_85603_1), + .I2(plm_frm3_char[3]), + .LO(plm_sym_N_85630_i) + ); + defparam plm_sym_lane3_bypass_N_85631_i.INIT = 16'hF777; + LUT4_L plm_sym_lane3_bypass_N_85631_i ( + .I0(plm_sym_N_36447_1_i), + .I1(plm_sym_N_55888_i), + .I2(plm_sym_N_61309), + .I3(plm_frm3_char[2]), + .LO(plm_sym_N_85631_i) + ); + defparam plm_sym_lane3_bypass_N_85632_i.INIT = 16'hF777; + LUT4_L plm_sym_lane3_bypass_N_85632_i ( + .I0(plm_sym_N_36449_1_i), + .I1(plm_sym_N_55888_i), + .I2(plm_sym_N_61309), + .I3(plm_frm3_char[1]), + .LO(plm_sym_N_85632_i) + ); + defparam plm_sym_lane0_bypass_N_87196_i.INIT = 8'h5D; + LUT3_L plm_sym_lane0_bypass_N_87196_i ( + .I0(plm_sym_N_56928_i), + .I1(plm_sym_sym_bypass[0]), + .I2(plm_tx0_link_pad), + .LO(plm_sym_N_87196_i) + ); + defparam plm_sym_lane0_bypass_reg_tx0_raw_char_is_k_8_i_m2_i_0_i_1_.INIT = 16'h1101; + LUT4_L plm_sym_lane0_bypass_reg_tx0_raw_char_is_k_8_i_m2_i_0_i_1_ ( + .I0(plm_sym_N_58223), + .I1(plm_sym_N_59407), + .I2(plm_sym_N_61348), + .I3(plm_frm0_is_k[1]), + .LO(plm_sym_N_53144_i) + ); + defparam plm_sym_lane0_bypass_reg_tx0_raw_char_is_k_8_0_a2_i_0_0_0_.INIT = 8'hD0; + LUT3_L plm_sym_lane0_bypass_reg_tx0_raw_char_is_k_8_0_a2_i_0_0_0_ ( + .I0(plm_sym_N_61309), + .I1(plm_frm0_is_k[0]), + .I2(plm_sym_reg_tx0_raw_char_is_k_8_0_a2_i_0_0_0[0]), + .LO(plm_sym_N_36576_i) + ); + defparam plm_sym_reg_count_5_11_.INIT = 4'h4; + LUT2_L plm_sym_reg_count_5_11_ ( + .I0(plm_sym_insert_ccs_1612), + .I1(plm_sym_un6_reg_count_s_11_1601), + .LO(plm_sym_reg_count_5_11__1618) + ); + defparam plm_sym_reg_count_5_10_.INIT = 4'h4; + LUT2_L plm_sym_reg_count_5_10_ ( + .I0(plm_sym_insert_ccs_1612), + .I1(plm_sym_un6_reg_count_s_10_1602), + .LO(plm_sym_reg_count_5_10__1619) + ); + defparam plm_sym_un6_reg_count_s_9_sf.INIT = 4'h1; + LUT1_L plm_sym_un6_reg_count_s_9_sf ( + .I0(plm_sym_reg_count_6112[9]), + .LO(plm_sym_un6_reg_count_s_9_sf_1603) + ); + defparam plm_sym_un6_reg_count_s_8_sf.INIT = 4'h1; + LUT1_L plm_sym_un6_reg_count_s_8_sf ( + .I0(plm_sym_reg_count_6112[8]), + .LO(plm_sym_un6_reg_count_s_8_sf_1604) + ); + defparam plm_sym_reg_count_5_7_.INIT = 4'h4; + LUT2_L plm_sym_reg_count_5_7_ ( + .I0(plm_sym_insert_ccs_1612), + .I1(plm_sym_un6_reg_count_s_7_1605), + .LO(plm_sym_reg_count_5_7__1622) + ); + defparam plm_sym_reg_count_5_6_.INIT = 4'h4; + LUT2_L plm_sym_reg_count_5_6_ ( + .I0(plm_sym_insert_ccs_1612), + .I1(plm_sym_un6_reg_count_s_6_1606), + .LO(plm_sym_reg_count_5_6__1623) + ); + defparam plm_sym_reg_count_5_5_.INIT = 4'h4; + LUT2_L plm_sym_reg_count_5_5_ ( + .I0(plm_sym_insert_ccs_1612), + .I1(plm_sym_un6_reg_count_s_5_1607), + .LO(plm_sym_reg_count_5_5__1624) + ); + defparam plm_sym_reg_count_5_4_.INIT = 4'h4; + LUT2_L plm_sym_reg_count_5_4_ ( + .I0(plm_sym_insert_ccs_1612), + .I1(plm_sym_un6_reg_count_s_4_1608), + .LO(plm_sym_reg_count_5_4__1625) + ); + defparam plm_sym_reg_count_5_3_.INIT = 4'h4; + LUT2_L plm_sym_reg_count_5_3_ ( + .I0(plm_sym_insert_ccs_1612), + .I1(plm_sym_un6_reg_count_s_3_1609), + .LO(plm_sym_reg_count_5_3__1626) + ); + defparam plm_sym_reg_count_5_2_.INIT = 4'h4; + LUT2_L plm_sym_reg_count_5_2_ ( + .I0(plm_sym_insert_ccs_1612), + .I1(plm_sym_un6_reg_count_s_2_1610), + .LO(plm_sym_reg_count_5_2__1627) + ); + defparam plm_sym_reg_count_5_1_.INIT = 4'h4; + LUT2_L plm_sym_reg_count_5_1_ ( + .I0(plm_sym_insert_ccs_1612), + .I1(plm_sym_un6_reg_count_s_1_1611), + .LO(plm_sym_reg_count_5_1__1628) + ); + defparam plm_sym_reg_count_5_0_.INIT = 4'h1; + LUT2_L plm_sym_reg_count_5_0_ ( + .I0(plm_sym_insert_ccs_1612), + .I1(plm_sym_reg_count[0]), + .LO(plm_sym_reg_count_5_0__1629) + ); + defparam plm_sym_lane3_bypass_reg_tx3_raw_char_is_k_8_i_i_i_1_.INIT = 16'h1101; + LUT4_L plm_sym_lane3_bypass_reg_tx3_raw_char_is_k_8_i_i_i_1_ ( + .I0(plm_sym_N_58232), + .I1(plm_sym_N_59407), + .I2(plm_sym_N_61348), + .I3(plm_frm3_is_k[1]), + .LO(plm_sym_N_54688_i) + ); + defparam plm_sym_lane3_bypass_reg_tx3_raw_char_is_k_8_0_a2_i_0_0_0_.INIT = 8'hC4; + LUT3_L plm_sym_lane3_bypass_reg_tx3_raw_char_is_k_8_0_a2_i_0_0_0_ ( + .I0(plm_sym_N_61309), + .I1(plm_sym_reg_tx1_raw_char_is_k_8_0_a2_i_0_0_1[0]), + .I2(plm_frm3_is_k[0]), + .LO(plm_sym_N_36574_i) + ); + defparam plm_sym_lane1_bypass_reg_tx1_raw_char_is_k_8_i_i_i_1_.INIT = 16'h1101; + LUT4_L plm_sym_lane1_bypass_reg_tx1_raw_char_is_k_8_i_i_i_1_ ( + .I0(plm_sym_N_58232), + .I1(plm_sym_N_59407), + .I2(plm_sym_N_61348), + .I3(plm_frm1_is_k[1]), + .LO(plm_sym_N_54690_i) + ); + defparam plm_sym_lane1_bypass_reg_tx1_raw_char_is_k_8_0_a2_i_0_0_0_.INIT = 8'hC4; + LUT3_L plm_sym_lane1_bypass_reg_tx1_raw_char_is_k_8_0_a2_i_0_0_0_ ( + .I0(plm_sym_N_61309), + .I1(plm_sym_reg_tx1_raw_char_is_k_8_0_a2_i_0_0_1[0]), + .I2(plm_frm1_is_k[0]), + .LO(plm_sym_N_36578_i) + ); + defparam plm_sym_lane3_bypass_N_87227_i.INIT = 8'hBA; + LUT3_L plm_sym_lane3_bypass_N_87227_i ( + .I0(plm_sym_N_58232), + .I1(plm_sym_sym_bypass[2]), + .I2(plm_sym_sym_pass[1]), + .LO(plm_sym_N_87227_i) + ); + defparam plm_sym_lane3_bypass_N_87195_i.INIT = 8'h5D; + LUT3_L plm_sym_lane3_bypass_N_87195_i ( + .I0(plm_sym_N_56928_i), + .I1(plm_sym_sym_bypass[0]), + .I2(plm_tx2_link_pad), + .LO(plm_sym_N_87195_i) + ); + defparam plm_sym_lane0_bypass_N_87226_i.INIT = 8'hBA; + LUT3_L plm_sym_lane0_bypass_N_87226_i ( + .I0(plm_sym_N_58223), + .I1(plm_sym_sym_bypass[2]), + .I2(plm_sym_sym_pass[1]), + .LO(plm_sym_N_87226_i) + ); + defparam plm_sym_lane1_bypass_reg_tx1_raw_char_8_i_0_0_0_a2_0_1_.INIT = 8'h02; + LUT3 plm_sym_lane1_bypass_reg_tx1_raw_char_8_i_0_0_0_a2_0_1_ ( + .I0(plm_sym_sym_symbol_1_), + .I1(plm_sym_sym_bypass[2]), + .I2(plm_sym_sym_bypass[0]), + .O(plm_sym_N_58978) + ); + FDC plm_sym_reg_raw_tstall ( + .C(mgt_clk), + .D(plm_sym_insert_ccs_1612), + .Q(plm_raw_tstall), + .CLR(plm_rst) + ); + FDC plm_sym_reg_frm_atomic ( + .C(mgt_clk), + .D(plm_frm_atomic), + .Q(plm_sym_reg_frm_atomic_1613), + .CLR(plm_rst) + ); + FDC plm_sym_reg_tx0_raw_char_3_ ( + .C(mgt_clk), + .D(plm_sym_N_85608_i), + .Q(plm_tx0_raw_char[3]), + .CLR(plm_rst) + ); + FDC plm_sym_reg_tx0_raw_char_2_ ( + .C(mgt_clk), + .D(plm_sym_N_85609_i), + .Q(plm_tx0_raw_char[2]), + .CLR(plm_rst) + ); + FDC plm_sym_reg_tx0_raw_char_1_ ( + .C(mgt_clk), + .D(plm_sym_N_85640_i), + .Q(plm_tx0_raw_char[1]), + .CLR(plm_rst) + ); + FDC plm_sym_reg_tx0_raw_char_0_ ( + .C(mgt_clk), + .D(plm_sym_N_85610_i), + .Q(plm_tx0_raw_char[0]), + .CLR(plm_rst) + ); + FDC plm_sym_reg_outstanding_ccs_3_ ( + .C(mgt_clk), + .D(plm_sym_un1_reg_outstanding_ccs_1_s_3_1614), + .Q(plm_reg_outstanding_ccs[3]), + .CLR(plm_rst) + ); + FDC plm_sym_reg_outstanding_ccs_2_ ( + .C(mgt_clk), + .D(plm_sym_un1_reg_outstanding_ccs_1_s_2_1615), + .Q(plm_reg_outstanding_ccs[2]), + .CLR(plm_rst) + ); + FDC plm_sym_reg_outstanding_ccs_1_ ( + .C(mgt_clk), + .D(plm_sym_un1_reg_outstanding_ccs_1_s_1_1616), + .Q(plm_reg_outstanding_ccs[1]), + .CLR(plm_rst) + ); + FDC plm_sym_reg_outstanding_ccs_0_ ( + .C(mgt_clk), + .D(plm_sym_un1_reg_outstanding_ccs_1_axb_0_1617), + .Q(plm_reg_outstanding_ccs[0]), + .CLR(plm_rst) + ); + FDC plm_sym_reg_tx1_raw_char_2_ ( + .C(mgt_clk), + .D(plm_sym_N_85639_i), + .Q(plm_tx1_raw_char[2]), + .CLR(plm_rst) + ); + FDC plm_sym_reg_tx1_raw_char_1_ ( + .C(mgt_clk), + .D(plm_sym_N_85604_i), + .Q(plm_tx1_raw_char[1]), + .CLR(plm_rst) + ); + FDC plm_sym_reg_tx1_raw_char_0_ ( + .C(mgt_clk), + .D(plm_sym_N_87198_i), + .Q(plm_tx1_raw_char[0]), + .CLR(plm_rst) + ); + FDC plm_sym_reg_tx0_raw_char_15_ ( + .C(mgt_clk), + .D(plm_sym_N_51828_i), + .Q(plm_tx0_raw_char[15]), + .CLR(plm_rst) + ); + FDC plm_sym_reg_tx0_raw_char_14_ ( + .C(mgt_clk), + .D(plm_sym_N_53136_i), + .Q(plm_tx0_raw_char[14]), + .CLR(plm_rst) + ); + FDC plm_sym_reg_tx0_raw_char_13_ ( + .C(mgt_clk), + .D(plm_sym_N_51826_i), + .Q(plm_tx0_raw_char[13]), + .CLR(plm_rst) + ); + FDC plm_sym_reg_tx0_raw_char_12_ ( + .C(mgt_clk), + .D(plm_sym_N_51824_i), + .Q(plm_tx0_raw_char[12]), + .CLR(plm_rst) + ); + FDC plm_sym_reg_tx0_raw_char_11_ ( + .C(mgt_clk), + .D(plm_sym_N_53134_i), + .Q(plm_tx0_raw_char[11]), + .CLR(plm_rst) + ); + FDC plm_sym_reg_tx0_raw_char_10_ ( + .C(mgt_clk), + .D(plm_sym_N_51822_i), + .Q(plm_tx0_raw_char[10]), + .CLR(plm_rst) + ); + FDC plm_sym_reg_tx0_raw_char_9_ ( + .C(mgt_clk), + .D(plm_sym_N_85560_i), + .Q(plm_tx0_raw_char[9]), + .CLR(plm_rst) + ); + FDC plm_sym_reg_tx0_raw_char_8_ ( + .C(mgt_clk), + .D(plm_sym_N_53132_i), + .Q(plm_tx0_raw_char[8]), + .CLR(plm_rst) + ); + FDC plm_sym_reg_tx0_raw_char_7_ ( + .C(mgt_clk), + .D(plm_sym_N_85562_i), + .Q(plm_tx0_raw_char[7]), + .CLR(plm_rst) + ); + FDC plm_sym_reg_tx0_raw_char_6_ ( + .C(mgt_clk), + .D(plm_sym_N_85605_i), + .Q(plm_tx0_raw_char[6]), + .CLR(plm_rst) + ); + FDC plm_sym_reg_tx0_raw_char_5_ ( + .C(mgt_clk), + .D(plm_sym_N_85606_i), + .Q(plm_tx0_raw_char[5]), + .CLR(plm_rst) + ); + FDC plm_sym_reg_tx0_raw_char_4_ ( + .C(mgt_clk), + .D(plm_sym_N_85607_i), + .Q(plm_tx0_raw_char[4]), + .CLR(plm_rst) + ); + FDC plm_sym_reg_tx2_raw_char_1_ ( + .C(mgt_clk), + .D(plm_sym_N_85638_i), + .Q(plm_tx2_raw_char[1]), + .CLR(plm_rst) + ); + FDC plm_sym_reg_tx2_raw_char_0_ ( + .C(mgt_clk), + .D(plm_sym_N_87225_i), + .Q(plm_tx2_raw_char[0]), + .CLR(plm_rst) + ); + FDC plm_sym_reg_tx1_raw_char_15_ ( + .C(mgt_clk), + .D(plm_sym_N_51838_i), + .Q(plm_tx1_raw_char[15]), + .CLR(plm_rst) + ); + FDC plm_sym_reg_tx1_raw_char_14_ ( + .C(mgt_clk), + .D(plm_sym_N_51836_i), + .Q(plm_tx1_raw_char[14]), + .CLR(plm_rst) + ); + FDC plm_sym_reg_tx1_raw_char_13_ ( + .C(mgt_clk), + .D(plm_sym_N_51834_i), + .Q(plm_tx1_raw_char[13]), + .CLR(plm_rst) + ); + FDC plm_sym_reg_tx1_raw_char_12_ ( + .C(mgt_clk), + .D(plm_sym_N_51832_i), + .Q(plm_tx1_raw_char[12]), + .CLR(plm_rst) + ); + FDC plm_sym_reg_tx1_raw_char_11_ ( + .C(mgt_clk), + .D(plm_sym_N_53138_i), + .Q(plm_tx1_raw_char[11]), + .CLR(plm_rst) + ); + FDC plm_sym_reg_tx1_raw_char_10_ ( + .C(mgt_clk), + .D(plm_sym_N_51830_i), + .Q(plm_tx1_raw_char[10]), + .CLR(plm_rst) + ); + FDC plm_sym_reg_tx1_raw_char_9_ ( + .C(mgt_clk), + .D(plm_sym_N_85561_i), + .Q(plm_tx1_raw_char[9]), + .CLR(plm_rst) + ); + FDC plm_sym_reg_tx1_raw_char_8_ ( + .C(mgt_clk), + .D(plm_sym_N_87567_i), + .Q(plm_tx1_raw_char[8]), + .CLR(plm_rst) + ); + FDC plm_sym_reg_tx1_raw_char_7_ ( + .C(mgt_clk), + .D(plm_sym_N_87486_i), + .Q(plm_tx1_raw_char[7]), + .CLR(plm_rst) + ); + FDC plm_sym_reg_tx1_raw_char_6_ ( + .C(mgt_clk), + .D(plm_sym_N_85601_i), + .Q(plm_tx1_raw_char[6]), + .CLR(plm_rst) + ); + FDC plm_sym_reg_tx1_raw_char_5_ ( + .C(mgt_clk), + .D(plm_sym_N_85602_i), + .Q(plm_tx1_raw_char[5]), + .CLR(plm_rst) + ); + FDC plm_sym_reg_tx1_raw_char_4_ ( + .C(mgt_clk), + .D(plm_sym_N_87094_i), + .Q(plm_tx1_raw_char[4]), + .CLR(plm_rst) + ); + FDC plm_sym_reg_tx1_raw_char_3_ ( + .C(mgt_clk), + .D(plm_sym_N_85603_i), + .Q(plm_tx1_raw_char[3]), + .CLR(plm_rst) + ); + FDC plm_sym_reg_tx3_raw_char_0_ ( + .C(mgt_clk), + .D(plm_sym_N_87224_i), + .Q(plm_tx3_raw_char[0]), + .CLR(plm_rst) + ); + FDC plm_sym_reg_tx2_raw_char_15_ ( + .C(mgt_clk), + .D(plm_sym_N_51850_i), + .Q(plm_tx2_raw_char[15]), + .CLR(plm_rst) + ); + FDC plm_sym_reg_tx2_raw_char_14_ ( + .C(mgt_clk), + .D(plm_sym_N_51848_i), + .Q(plm_tx2_raw_char[14]), + .CLR(plm_rst) + ); + FDC plm_sym_reg_tx2_raw_char_13_ ( + .C(mgt_clk), + .D(plm_sym_N_51846_i), + .Q(plm_tx2_raw_char[13]), + .CLR(plm_rst) + ); + FDC plm_sym_reg_tx2_raw_char_12_ ( + .C(mgt_clk), + .D(plm_sym_N_51844_i), + .Q(plm_tx2_raw_char[12]), + .CLR(plm_rst) + ); + FDC plm_sym_reg_tx2_raw_char_11_ ( + .C(mgt_clk), + .D(plm_sym_N_51842_i), + .Q(plm_tx2_raw_char[11]), + .CLR(plm_rst) + ); + FDC plm_sym_reg_tx2_raw_char_10_ ( + .C(mgt_clk), + .D(plm_sym_N_51840_i), + .Q(plm_tx2_raw_char[10]), + .CLR(plm_rst) + ); + FDC plm_sym_reg_tx2_raw_char_9_ ( + .C(mgt_clk), + .D(plm_sym_N_87475_i), + .Q(plm_tx2_raw_char[9]), + .CLR(plm_rst) + ); + FDC plm_sym_reg_tx2_raw_char_8_ ( + .C(mgt_clk), + .D(plm_sym_N_53140_i), + .Q(plm_tx2_raw_char[8]), + .CLR(plm_rst) + ); + FDC plm_sym_reg_tx2_raw_char_7_ ( + .C(mgt_clk), + .D(plm_sym_N_87478_i), + .Q(plm_tx2_raw_char[7]), + .CLR(plm_rst) + ); + FDC plm_sym_reg_tx2_raw_char_6_ ( + .C(mgt_clk), + .D(plm_sym_N_85633_i), + .Q(plm_tx2_raw_char[6]), + .CLR(plm_rst) + ); + FDC plm_sym_reg_tx2_raw_char_5_ ( + .C(mgt_clk), + .D(plm_sym_N_85634_i), + .Q(plm_tx2_raw_char[5]), + .CLR(plm_rst) + ); + FDC plm_sym_reg_tx2_raw_char_4_ ( + .C(mgt_clk), + .D(plm_sym_N_85635_i), + .Q(plm_tx2_raw_char[4]), + .CLR(plm_rst) + ); + FDC plm_sym_reg_tx2_raw_char_3_ ( + .C(mgt_clk), + .D(plm_sym_N_85636_i), + .Q(plm_tx2_raw_char[3]), + .CLR(plm_rst) + ); + FDC plm_sym_reg_tx2_raw_char_2_ ( + .C(mgt_clk), + .D(plm_sym_N_85637_i), + .Q(plm_tx2_raw_char[2]), + .CLR(plm_rst) + ); + FDC plm_sym_reg_tx3_raw_char_15_ ( + .C(mgt_clk), + .D(plm_sym_N_51860_i), + .Q(plm_tx3_raw_char[15]), + .CLR(plm_rst) + ); + FDC plm_sym_reg_tx3_raw_char_14_ ( + .C(mgt_clk), + .D(plm_sym_N_51858_i), + .Q(plm_tx3_raw_char[14]), + .CLR(plm_rst) + ); + FDC plm_sym_reg_tx3_raw_char_13_ ( + .C(mgt_clk), + .D(plm_sym_N_51856_i), + .Q(plm_tx3_raw_char[13]), + .CLR(plm_rst) + ); + FDC plm_sym_reg_tx3_raw_char_12_ ( + .C(mgt_clk), + .D(plm_sym_N_51854_i), + .Q(plm_tx3_raw_char[12]), + .CLR(plm_rst) + ); + FDC plm_sym_reg_tx3_raw_char_11_ ( + .C(mgt_clk), + .D(plm_sym_N_53142_i), + .Q(plm_tx3_raw_char[11]), + .CLR(plm_rst) + ); + FDC plm_sym_reg_tx3_raw_char_10_ ( + .C(mgt_clk), + .D(plm_sym_N_51852_i), + .Q(plm_tx3_raw_char[10]), + .CLR(plm_rst) + ); + FDC plm_sym_reg_tx3_raw_char_9_ ( + .C(mgt_clk), + .D(plm_sym_N_87476_i), + .Q(plm_tx3_raw_char[9]), + .CLR(plm_rst) + ); + FDC plm_sym_reg_tx3_raw_char_8_ ( + .C(mgt_clk), + .D(plm_sym_N_87568_i), + .Q(plm_tx3_raw_char[8]), + .CLR(plm_rst) + ); + FDC plm_sym_reg_tx3_raw_char_7_ ( + .C(mgt_clk), + .D(plm_sym_N_87479_i), + .Q(plm_tx3_raw_char[7]), + .CLR(plm_rst) + ); + FDC plm_sym_reg_tx3_raw_char_6_ ( + .C(mgt_clk), + .D(plm_sym_N_85627_i), + .Q(plm_tx3_raw_char[6]), + .CLR(plm_rst) + ); + FDC plm_sym_reg_tx3_raw_char_5_ ( + .C(mgt_clk), + .D(plm_sym_N_85628_i), + .Q(plm_tx3_raw_char[5]), + .CLR(plm_rst) + ); + FDC plm_sym_reg_tx3_raw_char_4_ ( + .C(mgt_clk), + .D(plm_sym_N_85629_i), + .Q(plm_tx3_raw_char[4]), + .CLR(plm_rst) + ); + FDC plm_sym_reg_tx3_raw_char_3_ ( + .C(mgt_clk), + .D(plm_sym_N_85630_i), + .Q(plm_tx3_raw_char[3]), + .CLR(plm_rst) + ); + FDC plm_sym_reg_tx3_raw_char_2_ ( + .C(mgt_clk), + .D(plm_sym_N_85631_i), + .Q(plm_tx3_raw_char[2]), + .CLR(plm_rst) + ); + FDC plm_sym_reg_tx3_raw_char_1_ ( + .C(mgt_clk), + .D(plm_sym_N_85632_i), + .Q(plm_tx3_raw_char[1]), + .CLR(plm_rst) + ); + FDC plm_sym_reg_tx0_raw_char_pass_0_ ( + .C(mgt_clk), + .D(plm_sym_N_87196_i), + .Q(plm_tx0_raw_char_pass[0]), + .CLR(plm_rst) + ); + FDC plm_sym_reg_tx0_raw_char_is_k_1_ ( + .C(mgt_clk), + .D(plm_sym_N_53144_i), + .Q(plm_tx0_raw_char_is_k[1]), + .CLR(plm_rst) + ); + FDC plm_sym_reg_tx0_raw_char_is_k_0_ ( + .C(mgt_clk), + .D(plm_sym_N_36576_i), + .Q(plm_tx0_raw_char_is_k[0]), + .CLR(plm_rst) + ); + FDC plm_sym_reg_count_11_ ( + .C(mgt_clk), + .D(plm_sym_reg_count_5_11__1618), + .Q(plm_sym_reg_count_6112[11]), + .CLR(plm_rst) + ); + FDC plm_sym_reg_count_10_ ( + .C(mgt_clk), + .D(plm_sym_reg_count_5_10__1619), + .Q(plm_sym_reg_count_6112[10]), + .CLR(plm_rst) + ); + FDP plm_sym_reg_count_9_ ( + .PRE(plm_rst), + .C(mgt_clk), + .D(plm_sym_un6_reg_count_s_9_1620), + .Q(plm_sym_reg_count_6112[9]) + ); + FDP plm_sym_reg_count_8_ ( + .PRE(plm_rst), + .C(mgt_clk), + .D(plm_sym_un6_reg_count_s_8_1621), + .Q(plm_sym_reg_count_6112[8]) + ); + FDC plm_sym_reg_count_7_ ( + .C(mgt_clk), + .D(plm_sym_reg_count_5_7__1622), + .Q(plm_sym_reg_count_6112[7]), + .CLR(plm_rst) + ); + FDC plm_sym_reg_count_6_ ( + .C(mgt_clk), + .D(plm_sym_reg_count_5_6__1623), + .Q(plm_sym_reg_count_6112[6]), + .CLR(plm_rst) + ); + FDC plm_sym_reg_count_5_ ( + .C(mgt_clk), + .D(plm_sym_reg_count_5_5__1624), + .Q(plm_sym_reg_count_6112[5]), + .CLR(plm_rst) + ); + FDC plm_sym_reg_count_4_ ( + .C(mgt_clk), + .D(plm_sym_reg_count_5_4__1625), + .Q(plm_sym_reg_count_6112[4]), + .CLR(plm_rst) + ); + FDC plm_sym_reg_count_3_ ( + .C(mgt_clk), + .D(plm_sym_reg_count_5_3__1626), + .Q(plm_sym_reg_count_6112[3]), + .CLR(plm_rst) + ); + FDC plm_sym_reg_count_2_ ( + .C(mgt_clk), + .D(plm_sym_reg_count_5_2__1627), + .Q(plm_sym_reg_count_6112[2]), + .CLR(plm_rst) + ); + FDC plm_sym_reg_count_1_ ( + .C(mgt_clk), + .D(plm_sym_reg_count_5_1__1628), + .Q(plm_sym_reg_count_6112[1]), + .CLR(plm_rst) + ); + FDC plm_sym_reg_count_0_ ( + .C(mgt_clk), + .D(plm_sym_reg_count_5_0__1629), + .Q(plm_sym_reg_count[0]), + .CLR(plm_rst) + ); + FDC plm_sym_reg_tx3_raw_char_is_k_1_ ( + .C(mgt_clk), + .D(plm_sym_N_54688_i), + .Q(plm_tx3_raw_char_is_k[1]), + .CLR(plm_rst) + ); + FDC plm_sym_reg_tx3_raw_char_is_k_0_ ( + .C(mgt_clk), + .D(plm_sym_N_36574_i), + .Q(plm_tx3_raw_char_is_k[0]), + .CLR(plm_rst) + ); + FDC plm_sym_reg_tx2_raw_char_is_k_1_ ( + .C(mgt_clk), + .D(plm_sym_N_54690_i), + .Q(plm_tx1_raw_char_is_k[1]), + .CLR(plm_rst) + ); + FDC plm_sym_reg_tx2_raw_char_is_k_0_ ( + .C(mgt_clk), + .D(plm_sym_N_36578_i), + .Q(plm_tx1_raw_char_is_k[0]), + .CLR(plm_rst) + ); + FDC plm_sym_reg_tx1_raw_char_pass_1_ ( + .C(mgt_clk), + .D(plm_sym_N_87227_i), + .Q(plm_tx3_raw_char_pass[1]), + .CLR(plm_rst) + ); + FDC plm_sym_reg_tx1_raw_char_pass_0_ ( + .C(mgt_clk), + .D(plm_sym_N_87195_i), + .Q(plm_tx3_raw_char_pass[0]), + .CLR(plm_rst) + ); + FDC plm_sym_reg_tx0_raw_char_pass_1_ ( + .C(mgt_clk), + .D(plm_sym_N_87226_i), + .Q(plm_tx0_raw_char_pass[1]), + .CLR(plm_rst) + ); + defparam plm_sym_un6_reg_count_s_10_sf.INIT = 4'h1; + LUT1 plm_sym_un6_reg_count_s_10_sf ( + .I0(plm_sym_reg_count_6112[10]), + .O(plm_sym_un6_reg_count_s_10_sf_1630) + ); + defparam plm_sym_un6_reg_count_s_7_sf.INIT = 4'h1; + LUT1 plm_sym_un6_reg_count_s_7_sf ( + .I0(plm_sym_reg_count_6112[7]), + .O(plm_sym_un6_reg_count_s_7_sf_1631) + ); + defparam plm_sym_un6_reg_count_s_6_sf.INIT = 4'h1; + LUT1 plm_sym_un6_reg_count_s_6_sf ( + .I0(plm_sym_reg_count_6112[6]), + .O(plm_sym_un6_reg_count_s_6_sf_1632) + ); + defparam plm_sym_un6_reg_count_s_5_sf.INIT = 4'h1; + LUT1 plm_sym_un6_reg_count_s_5_sf ( + .I0(plm_sym_reg_count_6112[5]), + .O(plm_sym_un6_reg_count_s_5_sf_1633) + ); + defparam plm_sym_un6_reg_count_s_4_sf.INIT = 4'h1; + LUT1 plm_sym_un6_reg_count_s_4_sf ( + .I0(plm_sym_reg_count_6112[4]), + .O(plm_sym_un6_reg_count_s_4_sf_1634) + ); + defparam plm_sym_un6_reg_count_s_3_sf.INIT = 4'h1; + LUT1 plm_sym_un6_reg_count_s_3_sf ( + .I0(plm_sym_reg_count_6112[3]), + .O(plm_sym_un6_reg_count_s_3_sf_1635) + ); + defparam plm_sym_un6_reg_count_s_2_sf.INIT = 4'h1; + LUT1 plm_sym_un6_reg_count_s_2_sf ( + .I0(plm_sym_reg_count_6112[2]), + .O(plm_sym_un6_reg_count_s_2_sf_1636) + ); + defparam plm_sym_un6_reg_count_s_1_sf.INIT = 4'h1; + LUT1 plm_sym_un6_reg_count_s_1_sf ( + .I0(plm_sym_reg_count_6112[1]), + .O(plm_sym_un6_reg_count_s_1_sf_1637) + ); + defparam plm_sym_sym_gen_next_addr_cnst_i_a2_2_.INIT = 4'h1; + LUT2 plm_sym_sym_gen_next_addr_cnst_i_a2_2_ ( + .I0(plm_sym_reg_sym_gen_sel[1]), + .I1(plm_sym_reg_sym_gen_sel[2]), + .O(plm_sym_sym_gen_N_3311) + ); + defparam plm_sym_sym_gen_next_addr_cnst_i_x2_1_.INIT = 4'h6; + LUT2 plm_sym_sym_gen_next_addr_cnst_i_x2_1_ ( + .I0(plm_sym_reg_sym_gen_sel[1]), + .I1(plm_sym_reg_sym_gen_sel[2]), + .O(plm_sym_sym_gen_N_3303_i) + ); + defparam plm_sym_sym_gen_next_addr_0_4_.INIT = 16'h88F0; + LUT4 plm_sym_sym_gen_next_addr_0_4_ ( + .I0(plm_sym_reg_sym_gen_sel[1]), + .I1(plm_sym_reg_sym_gen_sel[2]), + .I2(plm_sym_sym_gen_reg_rom_out[4]), + .I3(plm_sym_sym_gen_reg_rom_out[5]), + .O(plm_sym_sym_gen_next_addr[4]) + ); + defparam plm_sym_sym_gen_next_addr_cnst_i_2_.INIT = 8'h64; + LUT3_L plm_sym_sym_gen_next_addr_cnst_i_2_ ( + .I0(plm_sym_N_10147), + .I1(plm_sym_reg_sym_gen_sel[1]), + .I2(plm_sym_reg_sym_gen_sel[2]), + .LO(plm_sym_sym_gen_next_addr_cnst[2]) + ); + defparam plm_sym_sym_gen_next_addr_0_3_.INIT = 16'h44F0; + LUT4 plm_sym_sym_gen_next_addr_0_3_ ( + .I0(plm_sym_N_10147), + .I1(plm_sym_reg_sym_gen_sel[2]), + .I2(plm_sym_sym_gen_reg_rom_out[3]), + .I3(plm_sym_sym_gen_reg_rom_out[5]), + .O(plm_sym_sym_gen_next_addr[3]) + ); + defparam plm_sym_sym_gen_next_addr_0_1_.INIT = 16'h88F0; + LUT4 plm_sym_sym_gen_next_addr_0_1_ ( + .I0(plm_sym_sym_gen_N_3303_i), + .I1(plm_sym_N_10147), + .I2(plm_sym_sym_gen_reg_rom_out[1]), + .I3(plm_sym_sym_gen_reg_rom_out[5]), + .O(plm_sym_sym_gen_next_addr[1]) + ); + defparam plm_sym_sym_gen_next_addr_0_0_.INIT = 16'h22F0; + LUT4 plm_sym_sym_gen_next_addr_0_0_ ( + .I0(plm_sym_sym_gen_N_3311), + .I1(plm_sym_N_10147), + .I2(plm_sym_sym_gen_reg_rom_out[0]), + .I3(plm_sym_sym_gen_reg_rom_out[5]), + .O(plm_sym_sym_gen_next_addr[0]) + ); + defparam plm_sym_sym_gen_reg_rom_out_27_i_o2_8_.INIT = 4'h1; + LUT2 plm_sym_sym_gen_reg_rom_out_27_i_o2_8_ ( + .I0(plm_sym_sym_gen_next_addr[3]), + .I1(plm_sym_sym_gen_next_addr[4]), + .O(N_202_i) + ); + defparam plm_sym_sym_gen_next_addr_0_2_.INIT = 8'hAC; + LUT3 plm_sym_sym_gen_next_addr_0_2_ ( + .I0(plm_sym_sym_gen_next_addr_cnst[2]), + .I1(plm_sym_sym_gen_reg_rom_out[2]), + .I2(plm_sym_sym_gen_reg_rom_out[5]), + .O(plm_sym_sym_gen_next_addr[2]) + ); + defparam plm_sym_sym_gen_reg_rom_out_27_i_a2_28_.INIT = 4'h2; + LUT2 plm_sym_sym_gen_reg_rom_out_27_i_a2_28_ ( + .I0(N_202_i), + .I1(plm_sym_sym_gen_next_addr[0]), + .O(plm_sym_sym_gen_N_139) + ); + defparam plm_sym_sym_gen_reg_rom_out_27_i_o3_30_.INIT = 4'h1; + LUT2 plm_sym_sym_gen_reg_rom_out_27_i_o3_30_ ( + .I0(plm_sym_sym_gen_next_addr[0]), + .I1(plm_sym_sym_gen_next_addr[2]), + .O(plm_sym_sym_gen_N_111_i) + ); + defparam plm_sym_sym_gen_reg_rom_out_27_i_a2_2_.INIT = 4'h8; + LUT2 plm_sym_sym_gen_reg_rom_out_27_i_a2_2_ ( + .I0(plm_sym_sym_gen_next_addr[2]), + .I1(plm_sym_sym_gen_reg_rom_out[1]), + .O(plm_sym_sym_gen_N_214) + ); + defparam plm_sym_sym_gen_reg_rom_out_27_0_o2_6_.INIT = 4'h1; + LUT2 plm_sym_sym_gen_reg_rom_out_27_0_o2_6_ ( + .I0(plm_sym_sym_gen_next_addr[1]), + .I1(plm_sym_sym_gen_next_addr[2]), + .O(N_201_i) + ); + defparam plm_sym_sym_gen_reg_rom_out_27_0_a3_0_26_.INIT = 8'h02; + LUT3 plm_sym_sym_gen_reg_rom_out_27_0_a3_0_26_ ( + .I0(N_201_i), + .I1(N_202_i), + .I2(plm_sym_sym_gen_next_addr[0]), + .O(plm_sym_sym_gen_N_126) + ); + defparam plm_sym_sym_gen_reg_rom_out_27_0_a3_27_.INIT = 8'h28; + LUT3 plm_sym_sym_gen_reg_rom_out_27_0_a3_27_ ( + .I0(N_202_i), + .I1(plm_sym_sym_gen_next_addr[1]), + .I2(plm_sym_sym_gen_next_addr[2]), + .O(plm_sym_sym_gen_reg_rom_out_27_0_a3[27]) + ); + defparam plm_sym_sym_gen_reg_rom_out_27_0_0_25_.INIT = 8'h53; + LUT3 plm_sym_sym_gen_reg_rom_out_27_0_0_25_ ( + .I0(N_202_i), + .I1(N_2766), + .I2(plm_sym_sym_gen_next_addr[1]), + .O(plm_sym_sym_gen_reg_rom_out_27_0_0[25]) + ); + defparam plm_sym_sym_gen_reg_rom_out_27_i_m3_0_24_.INIT = 16'hD8DA; + LUT4_L plm_sym_sym_gen_reg_rom_out_27_i_m3_0_24_ ( + .I0(N_201_i), + .I1(plm_sym_sym_gen_next_addr[0]), + .I2(plm_sym_sym_gen_next_addr[3]), + .I3(plm_sym_sym_gen_next_addr[4]), + .LO(plm_sym_sym_gen_N_116) + ); + defparam plm_sym_sym_gen_N_10508_i.INIT = 16'hFC88; + LUT4_L plm_sym_sym_gen_N_10508_i ( + .I0(N_201_i), + .I1(N_202_i), + .I2(plm_sym_sym_gen_N_214), + .I3(plm_sym_sym_gen_next_addr[0]), + .LO(plm_sym_sym_gen_N_10508_i_1638) + ); + defparam plm_sym_sym_gen_reg_rom_out_27_i_4_.INIT = 8'h70; + LUT3_L plm_sym_sym_gen_reg_rom_out_27_i_4_ ( + .I0(plm_sym_sym_gen_N_214), + .I1(plm_sym_sym_gen_next_addr[0]), + .I2(plm_sym_sym_gen_next_addr[4]), + .LO(plm_sym_sym_gen_reg_rom_out_27_4_) + ); + defparam plm_sym_sym_gen_reg_rom_out_27_i_3_.INIT = 8'h70; + LUT3_L plm_sym_sym_gen_reg_rom_out_27_i_3_ ( + .I0(plm_sym_sym_gen_N_214), + .I1(plm_sym_sym_gen_next_addr[0]), + .I2(plm_sym_sym_gen_next_addr[3]), + .LO(plm_sym_sym_gen_reg_rom_out_27_3_) + ); + defparam plm_sym_sym_gen_reg_rom_out_27_i_2_.INIT = 16'h0155; + LUT4_L plm_sym_sym_gen_reg_rom_out_27_i_2_ ( + .I0(N_150), + .I1(N_202_i), + .I2(plm_sym_sym_gen_N_214), + .I3(plm_sym_sym_gen_next_addr[0]), + .LO(plm_sym_sym_gen_reg_rom_out_27_2_) + ); + defparam plm_sym_sym_gen_reg_rom_out_27_i_1_.INIT = 8'h34; + LUT3_L plm_sym_sym_gen_reg_rom_out_27_i_1_ ( + .I0(N_202_i), + .I1(plm_sym_sym_gen_next_addr[0]), + .I2(plm_sym_sym_gen_next_addr[1]), + .LO(plm_sym_sym_gen_reg_rom_out_27_1_) + ); + defparam plm_sym_sym_gen_reg_rom_out_27_i_0_.INIT = 8'h07; + LUT3_L plm_sym_sym_gen_reg_rom_out_27_i_0_ ( + .I0(N_201_i), + .I1(N_202_i), + .I2(plm_sym_sym_gen_next_addr[0]), + .LO(plm_sym_sym_gen_reg_rom_out_27_0_) + ); + defparam plm_sym_sym_gen_N_10520_i.INIT = 16'hFEEE; + LUT4_L plm_sym_sym_gen_N_10520_i ( + .I0(plm_sym_sym_gen_N_126), + .I1(plm_sym_sym_gen_reg_rom_out_27_0_a3[27]), + .I2(plm_sym_sym_gen_N_139), + .I3(plm_sym_sym_gen_next_addr[1]), + .LO(plm_sym_sym_gen_N_10520_i_1639) + ); + defparam plm_sym_sym_gen_N_10521_i.INIT = 4'hE; + LUT2_L plm_sym_sym_gen_N_10521_i ( + .I0(plm_sym_sym_gen_N_126), + .I1(plm_sym_sym_gen_reg_rom_out_27_6_), + .LO(plm_sym_sym_gen_N_10521_i_1640) + ); + defparam plm_sym_sym_gen_N_10522_i.INIT = 16'hA3FF; + LUT4_L plm_sym_sym_gen_N_10522_i ( + .I0(plm_sym_sym_gen_N_126), + .I1(N_150), + .I2(plm_sym_sym_gen_next_addr[4]), + .I3(plm_sym_sym_gen_reg_rom_out_27_0_0[25]), + .LO(plm_sym_sym_gen_N_10522_i_1641) + ); + defparam plm_sym_sym_gen_reg_rom_out_27_i_24_.INIT = 16'h1333; + LUT4_L plm_sym_sym_gen_reg_rom_out_27_i_24_ ( + .I0(plm_sym_sym_gen_N_111_i), + .I1(plm_sym_sym_gen_N_116), + .I2(plm_sym_sym_gen_next_addr[1]), + .I3(plm_sym_sym_gen_next_addr[4]), + .LO(plm_sym_sym_gen_reg_rom_out_27_24_) + ); + defparam plm_sym_sym_gen_reg_rom_out_27_0_a3_23_.INIT = 4'h4; + LUT2_L plm_sym_sym_gen_reg_rom_out_27_0_a3_23_ ( + .I0(N_150), + .I1(plm_sym_sym_gen_next_addr[3]), + .LO(plm_sym_sym_gen_reg_rom_out_27_23_) + ); + defparam plm_sym_sym_gen_reg_rom_out_27_i_22_.INIT = 4'h4; + LUT2_L plm_sym_sym_gen_reg_rom_out_27_i_22_ ( + .I0(N_150), + .I1(plm_sym_sym_gen_next_addr[4]), + .LO(plm_sym_sym_gen_reg_rom_out_27_22_) + ); + defparam plm_sym_sym_gen_reg_rom_out_27_i_9_.INIT = 4'h1; + LUT2_L plm_sym_sym_gen_reg_rom_out_27_i_9_ ( + .I0(plm_sym_sym_gen_N_126), + .I1(N_202_i), + .LO(plm_sym_sym_gen_reg_rom_out_27_9_) + ); + defparam plm_sym_sym_gen_N_202_i_i.INIT = 4'h1; + LUT1_L plm_sym_sym_gen_N_202_i_i ( + .I0(N_202_i), + .LO(plm_sym_sym_gen_N_202_i_i_1642) + ); + defparam plm_sym_sym_gen_address_table_next_addr45.INIT = 16'h8000; + LUT4_L plm_sym_sym_gen_address_table_next_addr45 ( + .I0(plm_sym_N_10147), + .I1(plm_sym_reg_sym_gen_sel[1]), + .I2(plm_sym_reg_sym_gen_sel[2]), + .I3(plm_sym_sym_gen_reg_rom_out[5]), + .LO(plm_sym_sym_gen_next_addr45) + ); + defparam plm_sym_sym_gen_address_table_next_addr44.INIT = 16'h1000; + LUT4_L plm_sym_sym_gen_address_table_next_addr44 ( + .I0(plm_sym_N_10147), + .I1(plm_sym_reg_sym_gen_sel[1]), + .I2(plm_sym_reg_sym_gen_sel[2]), + .I3(plm_sym_sym_gen_reg_rom_out[5]), + .LO(plm_sym_sym_gen_next_addr44) + ); + defparam plm_sym_sym_gen_address_table_next_addr43.INIT = 16'h2000; + LUT4_L plm_sym_sym_gen_address_table_next_addr43 ( + .I0(plm_sym_N_10147), + .I1(plm_sym_reg_sym_gen_sel[1]), + .I2(plm_sym_reg_sym_gen_sel[2]), + .I3(plm_sym_sym_gen_reg_rom_out[5]), + .LO(plm_sym_sym_gen_next_addr43) + ); + defparam plm_sym_sym_gen_address_table_next_addr40.INIT = 8'h20; + LUT3_L plm_sym_sym_gen_address_table_next_addr40 ( + .I0(plm_sym_sym_gen_N_3311), + .I1(plm_sym_N_10147), + .I2(plm_sym_sym_gen_reg_rom_out[5]), + .LO(plm_sym_sym_gen_next_addr40) + ); + defparam plm_sym_sym_gen_address_table_next_addr39.INIT = 8'h80; + LUT3_L plm_sym_sym_gen_address_table_next_addr39 ( + .I0(plm_sym_sym_gen_N_3311), + .I1(plm_sym_N_10147), + .I2(plm_sym_sym_gen_reg_rom_out[5]), + .LO(plm_sym_sym_gen_next_addr39) + ); + defparam plm_sym_sym_gen_reg_rom_out_27_i_32_.INIT = 4'h4; + LUT2_L plm_sym_sym_gen_reg_rom_out_27_i_32_ ( + .I0(plm_sym_sym_gen_N_139), + .I1(N_150), + .LO(plm_sym_sym_gen_reg_rom_out_27_32_) + ); + defparam plm_sym_sym_gen_reg_rom_out_27_0_a3_31_.INIT = 16'h0014; + LUT4_L plm_sym_sym_gen_reg_rom_out_27_0_a3_31_ ( + .I0(N_202_i), + .I1(plm_sym_sym_gen_next_addr[0]), + .I2(plm_sym_sym_gen_next_addr[1]), + .I3(plm_sym_sym_gen_next_addr[2]), + .LO(plm_sym_sym_gen_reg_rom_out_27_31_) + ); + defparam plm_sym_sym_gen_reg_rom_out_27_i_30_.INIT = 4'h2; + LUT2_L plm_sym_sym_gen_reg_rom_out_27_i_30_ ( + .I0(plm_sym_sym_gen_N_111_i), + .I1(N_202_i), + .LO(plm_sym_sym_gen_reg_rom_out_27_30_) + ); + defparam plm_sym_sym_gen_reg_rom_out_27_0_a3_29_.INIT = 8'h06; + LUT3_L plm_sym_sym_gen_reg_rom_out_27_0_a3_29_ ( + .I0(N_201_i), + .I1(N_202_i), + .I2(plm_sym_sym_gen_next_addr[0]), + .LO(plm_sym_sym_gen_reg_rom_out_27_29_) + ); + defparam plm_sym_sym_gen_reg_rom_out_27_i_28_.INIT = 16'h1151; + LUT4_L plm_sym_sym_gen_reg_rom_out_27_i_28_ ( + .I0(N_150), + .I1(N_202_i), + .I2(plm_sym_sym_gen_next_addr[0]), + .I3(plm_sym_sym_gen_next_addr[1]), + .LO(plm_sym_sym_gen_reg_rom_out_27_28_) + ); + defparam plm_sym_sym_gen_reg_rom_out_27_0_a3_6_.INIT = 8'h01; + LUT3 plm_sym_sym_gen_reg_rom_out_27_0_a3_6_ ( + .I0(N_201_i), + .I1(plm_sym_sym_gen_next_addr[4]), + .I2(plm_sym_sym_gen_next_addr[3]), + .O(plm_sym_sym_gen_reg_rom_out_27_6_) + ); + FDC plm_sym_sym_gen_reg_rom_out_6_ ( + .C(mgt_clk), + .D(plm_sym_sym_gen_reg_rom_out_27_6_), + .Q(plm_sym_sym_is_k[0]), + .CLR(plm_rst) + ); + FDC plm_sym_sym_gen_reg_rom_out_5_ ( + .C(mgt_clk), + .D(plm_sym_sym_gen_N_10508_i_1638), + .Q(plm_sym_sym_gen_reg_rom_out[5]), + .CLR(plm_rst) + ); + FDC plm_sym_sym_gen_reg_rom_out_4_ ( + .C(mgt_clk), + .D(plm_sym_sym_gen_reg_rom_out_27_4_), + .Q(plm_sym_sym_gen_reg_rom_out[4]), + .CLR(plm_rst) + ); + FDC plm_sym_sym_gen_reg_rom_out_3_ ( + .C(mgt_clk), + .D(plm_sym_sym_gen_reg_rom_out_27_3_), + .Q(plm_sym_sym_gen_reg_rom_out[3]), + .CLR(plm_rst) + ); + FDC plm_sym_sym_gen_reg_rom_out_2_ ( + .C(mgt_clk), + .D(plm_sym_sym_gen_reg_rom_out_27_2_), + .Q(plm_sym_sym_gen_reg_rom_out[2]), + .CLR(plm_rst) + ); + FDC plm_sym_sym_gen_reg_rom_out_1_ ( + .C(mgt_clk), + .D(plm_sym_sym_gen_reg_rom_out_27_1_), + .Q(plm_sym_sym_gen_reg_rom_out[1]), + .CLR(plm_rst) + ); + FDC plm_sym_sym_gen_reg_rom_out_0_ ( + .C(mgt_clk), + .D(plm_sym_sym_gen_reg_rom_out_27_0_), + .Q(plm_sym_sym_gen_reg_rom_out[0]), + .CLR(plm_rst) + ); + FDC plm_sym_sym_gen_reg_rom_out_27_ ( + .C(mgt_clk), + .D(plm_sym_sym_gen_N_10520_i_1639), + .Q(plm_sym_sym_symbol_13_), + .CLR(plm_rst) + ); + FDC plm_sym_sym_gen_reg_rom_out_26_ ( + .C(mgt_clk), + .D(plm_sym_sym_gen_N_10521_i_1640), + .Q(plm_sym_sym_is_k[1]), + .CLR(plm_rst) + ); + FDC plm_sym_sym_gen_reg_rom_out_25_ ( + .C(mgt_clk), + .D(plm_sym_sym_gen_N_10522_i_1641), + .Q(plm_sym_sym_symbol_11_), + .CLR(plm_rst) + ); + FDC plm_sym_sym_gen_reg_rom_out_24_ ( + .C(mgt_clk), + .D(plm_sym_sym_gen_reg_rom_out_27_24_), + .Q(plm_sym_sym_symbol_10_), + .CLR(plm_rst) + ); + FDC plm_sym_sym_gen_reg_rom_out_23_ ( + .C(mgt_clk), + .D(plm_sym_sym_gen_reg_rom_out_27_23_), + .Q(plm_sym_sym_symbol_1_), + .CLR(plm_rst) + ); + FDC plm_sym_sym_gen_reg_rom_out_22_ ( + .C(mgt_clk), + .D(plm_sym_sym_gen_reg_rom_out_27_22_), + .Q(plm_sym_sym_symbol_0_), + .CLR(plm_rst) + ); + FDC plm_sym_sym_gen_reg_rom_out_20_ ( + .C(mgt_clk), + .D(N_16_i_123), + .Q(plm_sym_sym_symbol_6_), + .CLR(plm_rst) + ); + FDC plm_sym_sym_gen_reg_rom_out_19_ ( + .C(mgt_clk), + .D(plm_sym_sym_gen_reg_rom_out_27_0_a3[27]), + .Q(plm_sym_sym_symbol_5_), + .CLR(plm_rst) + ); + FDC plm_sym_sym_gen_reg_rom_out_17_ ( + .C(mgt_clk), + .D(plm_sym_sym_gen_reg_rom_out_27[17]), + .Q(plm_sym_sym_symbol_3_), + .CLR(plm_rst) + ); + FDC plm_sym_sym_gen_reg_rom_out_16_ ( + .C(mgt_clk), + .D(N_154_i_122), + .Q(plm_sym_sym_symbol_2_), + .CLR(plm_rst) + ); + FDC plm_sym_sym_gen_reg_rom_out_9_ ( + .C(mgt_clk), + .D(plm_sym_sym_gen_reg_rom_out_27_9_), + .Q(plm_sym_sym_pass[1]), + .CLR(plm_rst) + ); + FDC plm_sym_sym_gen_reg_rom_out_8_ ( + .C(mgt_clk), + .D(plm_sym_sym_gen_N_202_i_i_1642), + .Q(plm_sym_sym_pass[0]), + .CLR(plm_rst) + ); + FDC plm_sym_sym_gen_reg_sym_sent_6_ ( + .C(mgt_clk), + .D(plm_sym_sym_gen_next_addr45), + .Q(plm_reg_sym_sent_6_), + .CLR(plm_rst) + ); + FDC plm_sym_sym_gen_reg_sym_sent_5_ ( + .C(mgt_clk), + .D(plm_sym_sym_gen_next_addr44), + .Q(plm_reg_sym_sent_5_), + .CLR(plm_rst) + ); + FDC plm_sym_sym_gen_reg_sym_sent_4_ ( + .C(mgt_clk), + .D(plm_sym_sym_gen_next_addr43), + .Q(plm_sym_sent_status[4]), + .CLR(plm_rst) + ); + FDC plm_sym_sym_gen_reg_sym_sent_1_ ( + .C(mgt_clk), + .D(plm_sym_sym_gen_next_addr40), + .Q(plm_sent_status[1]), + .CLR(plm_rst) + ); + FDC plm_sym_sym_gen_reg_sym_sent_0_ ( + .C(mgt_clk), + .D(plm_sym_sym_gen_next_addr39), + .Q(plm_reg_sym_sent_0_), + .CLR(plm_rst) + ); + FDC plm_sym_sym_gen_reg_rom_out_32_ ( + .C(mgt_clk), + .D(plm_sym_sym_gen_reg_rom_out_27_32_), + .Q(plm_sym_sym_bypass[2]), + .CLR(plm_rst) + ); + FDC plm_sym_sym_gen_reg_rom_out_31_ ( + .C(mgt_clk), + .D(plm_sym_sym_gen_reg_rom_out_27_31_), + .Q(plm_sym_sym_bypass[1]), + .CLR(plm_rst) + ); + FDC plm_sym_sym_gen_reg_rom_out_30_ ( + .C(mgt_clk), + .D(plm_sym_sym_gen_reg_rom_out_27_30_), + .Q(plm_sym_sym_bypass[0]), + .CLR(plm_rst) + ); + FDC plm_sym_sym_gen_reg_rom_out_29_ ( + .C(mgt_clk), + .D(plm_sym_sym_gen_reg_rom_out_27_29_), + .Q(plm_sym_sym_symbol_15_), + .CLR(plm_rst) + ); + FDC plm_sym_sym_gen_reg_rom_out_28_ ( + .C(mgt_clk), + .D(plm_sym_sym_gen_reg_rom_out_27_28_), + .Q(plm_sym_sym_symbol_14_), + .CLR(plm_rst) + ); + defparam plm_frm_delay_two_b_reg_d2_td_13_1_f0_i_x3_34_.INIT = 4'h6; + LUT2 plm_frm_delay_two_b_reg_d2_td_13_1_f0_i_x3_34_ ( + .I0(plm_frm_reg_d1_tframe_h_1650), + .I1(plm_frm_reg_d2_tframe_h_1651), + .O(plm_frm_N_55866_i_0) + ); + defparam plm_frm_ciao_baby_reg_frm_atomic_3_i_x3.INIT = 4'h6; + LUT2 plm_frm_ciao_baby_reg_frm_atomic_3_i_x3 ( + .I0(plm_frm_reg_d0_tframe_h_1648), + .I1(plm_frm_reg_d2_tframe_h_1651), + .O(plm_frm_N_56427_i_0) + ); + defparam plm_frm_delay_two_b_reg_d2_td_24_1_f0_i_x3_2_.INIT = 4'h6; + LUT2 plm_frm_delay_two_b_reg_d2_td_24_1_f0_i_x3_2_ ( + .I0(plm_frm_reg_d0_tframe_h_1648), + .I1(plm_frm_reg_d1_tframe_h_1650), + .O(plm_frm_N_55867_i_0) + ); + defparam plm_frm_d1_end_h.INIT = 4'h6; + LUT2 plm_frm_d1_end_h ( + .I0(plm_frm_reg_d1_tframe_l_1652), + .I1(plm_frm_reg_d2_tframe_l_1653), + .O(plm_frm_d1_end_h_1643) + ); + defparam plm_frm_ciao_baby_reg_frm_atomic_3_i_a3.INIT = 4'h8; + LUT2 plm_frm_ciao_baby_reg_frm_atomic_3_i_a3 ( + .I0(cmmp_negotiated_width[0]), + .I1(plm_frm_reg_wd_sel[0]), + .O(plm_frm_N_61321) + ); + defparam plm_frm_delay_one_reg_d1_idleflag_lh_3_0.INIT = 4'h8; + LUT2 plm_frm_delay_one_reg_d1_idleflag_lh_3_0 ( + .I0(plm_frm_reg_d0_td[30]), + .I1(plm_frm_reg_d0_td[31]), + .O(plm_frm_reg_d1_idleflag_lh_3_0) + ); + defparam plm_frm_delay_one_reg_d1_idleflag_hl_3_0.INIT = 4'h8; + LUT2 plm_frm_delay_one_reg_d1_idleflag_hl_3_0 ( + .I0(plm_frm_reg_d0_td[38]), + .I1(plm_frm_reg_d0_td[39]), + .O(plm_frm_reg_d1_idleflag_hl_3_0) + ); + defparam plm_frm_delay_one_reg_d1_idleflag_ll_3_0.INIT = 4'h8; + LUT2 plm_frm_delay_one_reg_d1_idleflag_ll_3_0 ( + .I0(plm_frm_reg_d0_td[6]), + .I1(plm_frm_reg_d0_td[7]), + .O(plm_frm_reg_d1_idleflag_ll_3_0) + ); + defparam plm_frm_delay_one_reg_d1_idleflag_hh_3_0.INIT = 4'h8; + LUT2 plm_frm_delay_one_reg_d1_idleflag_hh_3_0 ( + .I0(plm_frm_reg_d0_td[62]), + .I1(plm_frm_reg_d0_td[63]), + .O(plm_frm_reg_d1_idleflag_hh_3_0) + ); + defparam plm_frm_ciao_baby_reg_frm0_is_k_3_i_m3_i_m3_0_0_.INIT = 8'hE4; + LUT3 plm_frm_ciao_baby_reg_frm0_is_k_3_i_m3_i_m3_0_0_ ( + .I0(plm_frm_reg_wd_sel[1]), + .I1(plm_frm_reg_d2_idle_h_1658), + .I2(plm_frm_reg_d2_idle_l_1659), + .O(plm_frm_N_55890) + ); + defparam plm_frm_reg_d2_charisk_1_sqmuxa_1_i_0_o2.INIT = 4'h2; + LUT2 plm_frm_reg_d2_charisk_1_sqmuxa_1_i_0_o2 ( + .I0(plm_frm_N_55866_i_0), + .I1(plm_frm_d1_end_h_1643), + .O(plm_frm_N_56105_i) + ); + defparam plm_frm_reg_d2_charisk_1_sqmuxa_2_i_0_o2.INIT = 4'h2; + LUT2 plm_frm_reg_d2_charisk_1_sqmuxa_2_i_0_o2 ( + .I0(plm_frm_N_55867_i_0), + .I1(plm_frm_d1_end_h_1643), + .O(plm_frm_N_56005_i) + ); + defparam plm_frm_ciao_baby_reg_frm0_char_3_0_a3_5_.INIT = 8'h01; + LUT3 plm_frm_ciao_baby_reg_frm0_char_3_0_a3_5_ ( + .I0(cmmp_negotiated_width[0]), + .I1(plm_frm_reg_state[0]), + .I2(plm_frm_reg_state[1]), + .O(plm_frm_N_61385) + ); + defparam plm_frm_ciao_baby_reg_frm0_char_3_0_a3_1_13_.INIT = 8'h02; + LUT3 plm_frm_ciao_baby_reg_frm0_char_3_0_a3_1_13_ ( + .I0(cmmp_negotiated_width[0]), + .I1(plm_frm_reg_wd_sel[0]), + .I2(plm_frm_reg_wd_sel[1]), + .O(plm_frm_N_61332) + ); + defparam plm_frm_ciao_baby_reg_frm0_char_3_0_a3_0_13_.INIT = 8'h20; + LUT3 plm_frm_ciao_baby_reg_frm0_char_3_0_a3_0_13_ ( + .I0(cmmp_negotiated_width[0]), + .I1(plm_frm_reg_wd_sel[0]), + .I2(plm_frm_reg_wd_sel[1]), + .O(plm_frm_N_61329) + ); + defparam plm_frm_ciao_baby_reg_frm0_char_3_0_a3_0_.INIT = 8'h02; + LUT3 plm_frm_ciao_baby_reg_frm0_char_3_0_a3_0_ ( + .I0(plm_frm_N_61321), + .I1(plm_frm_reg_byp1), + .I2(plm_frm_reg_wd_sel[1]), + .O(plm_frm_N_61353) + ); + defparam plm_frm_ciao_baby_reg_frm0_char_3_0_a3_0_0_.INIT = 8'h20; + LUT3 plm_frm_ciao_baby_reg_frm0_char_3_0_a3_0_0_ ( + .I0(plm_frm_N_61321), + .I1(plm_frm_reg_byp3), + .I2(plm_frm_reg_wd_sel[1]), + .O(plm_frm_N_61354) + ); + defparam plm_frm_by1_opportunity_h_i_0_o3.INIT = 16'h0001; + LUT4 plm_frm_by1_opportunity_h_i_0_o3 ( + .I0(plm_reg_outstanding_ccs[0]), + .I1(plm_reg_outstanding_ccs[1]), + .I2(plm_reg_outstanding_ccs[2]), + .I3(plm_reg_outstanding_ccs[3]), + .O(plm_N_55932_i) + ); + defparam plm_frm_delay_one_reg_d1_idleflag_lh_3_4.INIT = 16'h8000; + LUT4 plm_frm_delay_one_reg_d1_idleflag_lh_3_4 ( + .I0(plm_frm_reg_d0_td[24]), + .I1(plm_frm_reg_d0_td[25]), + .I2(plm_frm_reg_d0_td[26]), + .I3(plm_frm_reg_d0_td[27]), + .O(plm_frm_reg_d1_idleflag_lh_3_4) + ); + defparam plm_frm_delay_one_reg_d1_idleflag_hl_3_4.INIT = 16'h8000; + LUT4 plm_frm_delay_one_reg_d1_idleflag_hl_3_4 ( + .I0(plm_frm_reg_d0_td[32]), + .I1(plm_frm_reg_d0_td[33]), + .I2(plm_frm_reg_d0_td[34]), + .I3(plm_frm_reg_d0_td[35]), + .O(plm_frm_reg_d1_idleflag_hl_3_4) + ); + defparam plm_frm_delay_one_reg_d1_idleflag_ll_3_4.INIT = 16'h8000; + LUT4 plm_frm_delay_one_reg_d1_idleflag_ll_3_4 ( + .I0(plm_frm_reg_d0_td[0]), + .I1(plm_frm_reg_d0_td[1]), + .I2(plm_frm_reg_d0_td[2]), + .I3(plm_frm_reg_d0_td[3]), + .O(plm_frm_reg_d1_idleflag_ll_3_4) + ); + defparam plm_frm_delay_one_reg_d1_idleflag_hh_3_4.INIT = 16'h8000; + LUT4 plm_frm_delay_one_reg_d1_idleflag_hh_3_4 ( + .I0(plm_frm_reg_d0_td[56]), + .I1(plm_frm_reg_d0_td[57]), + .I2(plm_frm_reg_d0_td[58]), + .I3(plm_frm_reg_d0_td[59]), + .O(plm_frm_reg_d1_idleflag_hh_3_4) + ); + defparam plm_frm_ciao_baby_reg_frm0_is_k_3_0_a2_1_.INIT = 16'hA088; + LUT4_L plm_frm_ciao_baby_reg_frm0_is_k_3_0_a2_1_ ( + .I0(plm_frm_N_61321), + .I1(plm_frm_reg_byp1), + .I2(plm_frm_reg_byp3), + .I3(plm_frm_reg_wd_sel[1]), + .LO(plm_frm_N_57641) + ); + defparam plm_frm_delay_two_b_reg_d2_td_13_1_f0_i_a2_0_34_.INIT = 8'h40; + LUT3 plm_frm_delay_two_b_reg_d2_td_13_1_f0_i_a2_0_34_ ( + .I0(plm_frm_N_55866_i_0), + .I1(plm_frm_d1_end_h_1643), + .I2(plm_frm_reg_d1_idleflag_hl_1655), + .O(plm_frm_N_57648) + ); + defparam plm_frm_N_11312_i_i_a2.INIT = 8'h15; + LUT3 plm_frm_N_11312_i_i_a2 ( + .I0(plm_frm_N_55866_i_0), + .I1(plm_frm_d1_end_h_1643), + .I2(plm_frm_reg_d1_idleflag_hl_1655), + .O(plm_frm_N_61261) + ); + defparam plm_frm_reg_d2_charisk_1_sqmuxa_1_i_0.INIT = 4'h2; + LUT2 plm_frm_reg_d2_charisk_1_sqmuxa_1_i_0 ( + .I0(plm_frm_N_56105_i), + .I1(plm_frm_reg_d1_idleflag_hh_1654), + .O(plm_frm_N_51384_i) + ); + defparam plm_frm_delay_two_b_reg_d2_td_24_1_f0_i_a2_2_.INIT = 4'h4; + LUT2 plm_frm_delay_two_b_reg_d2_td_24_1_f0_i_a2_2_ ( + .I0(plm_frm_N_55867_i_0), + .I1(plm_frm_N_55996_i), + .O(plm_frm_N_57655) + ); + defparam plm_frm_delay_two_b_reg_d2_td_24_0_iv_i_a2_0_0_.INIT = 4'h2; + LUT2 plm_frm_delay_two_b_reg_d2_td_24_0_iv_i_a2_0_0_ ( + .I0(plm_frm_N_56005_i), + .I1(plm_frm_reg_d1_idleflag_ll_1657), + .O(plm_frm_N_58272) + ); + defparam plm_frm_ciao_baby_reg_frm0_char_3_0_a3_2_0_.INIT = 4'h8; + LUT2 plm_frm_ciao_baby_reg_frm0_char_3_0_a3_2_0_ ( + .I0(plm_N_55932_i), + .I1(plm_frm_N_61329), + .O(plm_frm_N_61366) + ); + defparam plm_frm_ciao_baby_reg_frm0_char_3_0_a3_1_0_.INIT = 4'h8; + LUT2 plm_frm_ciao_baby_reg_frm0_char_3_0_a3_1_0_ ( + .I0(plm_N_55932_i), + .I1(plm_frm_N_61332), + .O(plm_frm_N_61365) + ); + defparam plm_frm_by1_opportunity_l_i_0_o3.INIT = 4'h8; + LUT2 plm_frm_by1_opportunity_l_i_0_o3 ( + .I0(plm_N_3288), + .I1(plm_sent_status[1]), + .O(plm_frm_N_55877_i) + ); + defparam plm_frm_ciao_baby_reg_frm_atomic_3_i_o3_0.INIT = 16'hF3A2; + LUT4 plm_frm_ciao_baby_reg_frm_atomic_3_i_o3_0 ( + .I0(plm_frm_N_55866_i_0), + .I1(plm_frm_N_56427_i_0), + .I2(plm_frm_d1_end_h_1643), + .I3(plm_frm_reg_d1_idleflag_hl_1655), + .O(plm_frm_reg_frm_atomic_3_i_o3_0) + ); + defparam plm_frm_ciao_baby_reg_frm0_is_k_3_0_0_1_.INIT = 16'hA8FF; + LUT4 plm_frm_ciao_baby_reg_frm0_is_k_3_0_0_1_ ( + .I0(cmmp_negotiated_width[0]), + .I1(plm_frm_reg_wd_sel[0]), + .I2(plm_frm_reg_wd_sel[1]), + .I3(plm_frm_reg_d2_charisk_7__1661), + .O(plm_frm_reg_frm0_is_k_3_0_0[1]) + ); + defparam plm_frm_delay_two_b_reg_d2_td_13_0_iv_0_o2_33_.INIT = 16'h1357; + LUT4 plm_frm_delay_two_b_reg_d2_td_13_0_iv_0_o2_33_ ( + .I0(plm_frm_N_55866_i_0), + .I1(plm_frm_d1_end_h_1643), + .I2(plm_frm_reg_d1_idleflag_hh_1654), + .I3(plm_frm_reg_d1_idleflag_hl_1655), + .O(plm_frm_N_57040_i) + ); + defparam plm_frm_delay_two_b_reg_d2_td_13_i_48_37194.INIT = 8'h13; + LUT3 plm_frm_delay_two_b_reg_d2_td_13_i_48_37194 ( + .I0(plm_frm_N_56105_i), + .I1(plm_frm_N_57648), + .I2(plm_frm_reg_d1_idleflag_hh_1654), + .O(plm_frm_N_63791_i) + ); + defparam plm_frm_N_11312_i_i_o2.INIT = 16'hEC00; + LUT4 plm_frm_N_11312_i_i_o2 ( + .I0(plm_frm_d1_end_h_1643), + .I1(plm_frm_reg_d1_idleflag_hh_1654), + .I2(plm_frm_reg_d1_idleflag_hl_1655), + .I3(plm_frm_reg_d1_tctrl_h_1645), + .O(plm_frm_N_57042_i) + ); + defparam plm_frm_N_11311_i_i_o2.INIT = 16'hEC00; + LUT4 plm_frm_N_11311_i_i_o2 ( + .I0(plm_frm_N_55867_i_0), + .I1(plm_frm_N_55996_i), + .I2(plm_frm_reg_d1_idleflag_ll_1657), + .I3(plm_frm_reg_d1_tctrl_l_1647), + .O(plm_frm_N_57067_i) + ); + defparam plm_frm_delay_two_b_reg_d2_td_24_0_iv_0_o2_26_.INIT = 16'h1113; + LUT4 plm_frm_delay_two_b_reg_d2_td_24_0_iv_0_o2_26_ ( + .I0(plm_frm_N_55867_i_0), + .I1(plm_frm_N_55996_i), + .I2(plm_frm_d1_end_h_1643), + .I3(plm_frm_reg_d1_idleflag_ll_1657), + .O(plm_frm_N_56109_i) + ); + defparam plm_frm_delay_two_b_reg_d2_td_24_i_14_37180.INIT = 8'h13; + LUT3 plm_frm_delay_two_b_reg_d2_td_24_i_14_37180 ( + .I0(plm_frm_N_56005_i), + .I1(plm_frm_N_57655), + .I2(plm_frm_reg_d1_idleflag_ll_1657), + .O(plm_frm_N_63777_i) + ); + defparam plm_frm_ciao_baby_reg_frm0_char_3_0_m3_0_a2_5_2_.INIT = 4'h2; + LUT2_L plm_frm_ciao_baby_reg_frm0_char_3_0_m3_0_a2_5_2_ ( + .I0(plm_frm_N_61365), + .I1(plm_frm_reg_d2_td[50]), + .LO(plm_frm_N_58409) + ); + defparam plm_frm_ciao_baby_reg_frm0_char_3_i_m3_0_a2_5_1_.INIT = 4'h8; + LUT2_L plm_frm_ciao_baby_reg_frm0_char_3_i_m3_0_a2_5_1_ ( + .I0(plm_frm_N_61365), + .I1(plm_frm_reg_d2_td[49]), + .LO(plm_frm_N_58402) + ); + defparam plm_frm_ciao_baby_reg_frm0_char_3_0_a2_5_14_.INIT = 4'h8; + LUT2_L plm_frm_ciao_baby_reg_frm0_char_3_0_a2_5_14_ ( + .I0(plm_frm_N_61365), + .I1(plm_frm_reg_d2_td[62]), + .LO(plm_frm_N_57640) + ); + defparam plm_frm_ciao_baby_reg_frm0_char_3_i_a2_5_12_.INIT = 4'h2; + LUT2_L plm_frm_ciao_baby_reg_frm0_char_3_i_a2_5_12_ ( + .I0(plm_frm_N_61365), + .I1(plm_frm_reg_d2_td[60]), + .LO(plm_frm_N_57626) + ); + defparam plm_frm_ciao_baby_reg_frm0_char_3_i_a2_5_11_.INIT = 4'h2; + LUT2_L plm_frm_ciao_baby_reg_frm0_char_3_i_a2_5_11_ ( + .I0(plm_frm_N_61365), + .I1(plm_frm_reg_d2_td[59]), + .LO(plm_frm_N_57619) + ); + defparam plm_frm_ciao_baby_reg_frm0_char_3_i_a2_5_10_.INIT = 4'h2; + LUT2_L plm_frm_ciao_baby_reg_frm0_char_3_i_a2_5_10_ ( + .I0(plm_frm_N_61365), + .I1(plm_frm_reg_d2_td[58]), + .LO(plm_frm_N_57612) + ); + defparam plm_frm_ciao_baby_reg_frm0_char_3_0_a2_5_9_.INIT = 4'h8; + LUT2_L plm_frm_ciao_baby_reg_frm0_char_3_0_a2_5_9_ ( + .I0(plm_frm_N_61365), + .I1(plm_frm_reg_d2_td[57]), + .LO(plm_frm_N_57605) + ); + defparam plm_frm_ciao_baby_reg_frm0_char_3_0_a2_5_8_.INIT = 4'h8; + LUT2_L plm_frm_ciao_baby_reg_frm0_char_3_0_a2_5_8_ ( + .I0(plm_frm_N_61365), + .I1(plm_frm_reg_d2_td[56]), + .LO(plm_frm_N_57598) + ); + defparam plm_frm_ciao_baby_reg_frm0_char_3_0_a2_5_6_.INIT = 4'h8; + LUT2_L plm_frm_ciao_baby_reg_frm0_char_3_0_a2_5_6_ ( + .I0(plm_frm_N_61365), + .I1(plm_frm_reg_d2_td[54]), + .LO(plm_frm_N_57584) + ); + defparam plm_frm_ciao_baby_reg_frm0_char_3_i_a2_5_4_.INIT = 4'h2; + LUT2_L plm_frm_ciao_baby_reg_frm0_char_3_i_a2_5_4_ ( + .I0(plm_frm_N_61365), + .I1(plm_frm_reg_d2_td[52]), + .LO(plm_frm_N_57569) + ); + defparam plm_frm_ciao_baby_reg_frm0_char_3_i_a2_5_3_.INIT = 4'h2; + LUT2_L plm_frm_ciao_baby_reg_frm0_char_3_i_a2_5_3_ ( + .I0(plm_frm_N_61365), + .I1(plm_frm_reg_d2_td[51]), + .LO(plm_frm_N_57562) + ); + defparam plm_frm_ciao_baby_reg_frm0_char_3_0_a2_5_0_.INIT = 4'h8; + LUT2_L plm_frm_ciao_baby_reg_frm0_char_3_0_a2_5_0_ ( + .I0(plm_frm_N_61365), + .I1(plm_frm_reg_d2_td[48]), + .LO(plm_frm_N_57555) + ); + defparam plm_frm_ciao_baby_reg_frm0_is_k_3_i_m3_i_o3_0_.INIT = 8'h08; + LUT3 plm_frm_ciao_baby_reg_frm0_is_k_3_i_m3_i_o3_0_ ( + .I0(plm_frm_N_55877_i), + .I1(plm_frm_N_55890), + .I2(plm_N_55932_i), + .O(plm_frm_N_56240_i) + ); + defparam plm_frm_ciao_baby_reg_frm0_char_3_i_m3_0_1_0_15_.INIT = 16'h153F; + LUT4_L plm_frm_ciao_baby_reg_frm0_char_3_i_m3_0_1_0_15_ ( + .I0(plm_frm_N_61329), + .I1(plm_frm_N_61354), + .I2(plm_frm_reg_d2_td[15]), + .I3(plm_frm_reg_d2_td[31]), + .LO(plm_frm_reg_frm0_char_3_i_m3_0_1[15]) + ); + defparam plm_frm_ciao_baby_reg_frm0_char_3_0_1_13_.INIT = 16'h153F; + LUT4_L plm_frm_ciao_baby_reg_frm0_char_3_0_1_13_ ( + .I0(plm_frm_N_61329), + .I1(plm_frm_N_61354), + .I2(plm_frm_reg_d2_td[13]), + .I3(plm_frm_reg_d2_td[29]), + .LO(plm_frm_reg_frm0_char_3_0_1[13]) + ); + defparam plm_frm_ciao_baby_reg_frm0_char_3_0_0_8_.INIT = 16'h153F; + LUT4 plm_frm_ciao_baby_reg_frm0_char_3_0_0_8_ ( + .I0(plm_frm_N_61353), + .I1(plm_frm_N_61354), + .I2(plm_frm_reg_d2_td[8]), + .I3(plm_frm_reg_d2_td[40]), + .O(plm_frm_reg_frm0_char_3_0_0_8_) + ); + defparam plm_frm_ciao_baby_reg_frm0_char_3_i_0_11_.INIT = 16'hF351; + LUT4 plm_frm_ciao_baby_reg_frm0_char_3_i_0_11_ ( + .I0(plm_frm_N_61353), + .I1(plm_frm_N_61354), + .I2(plm_frm_reg_d2_td[11]), + .I3(plm_frm_reg_d2_td[43]), + .O(plm_frm_reg_frm0_char_3_i_0_11_) + ); + defparam plm_frm_ciao_baby_reg_frm0_char_3_0_0_9_.INIT = 16'h153F; + LUT4 plm_frm_ciao_baby_reg_frm0_char_3_0_0_9_ ( + .I0(plm_frm_N_61353), + .I1(plm_frm_N_61354), + .I2(plm_frm_reg_d2_td[9]), + .I3(plm_frm_reg_d2_td[41]), + .O(plm_frm_reg_frm0_char_3_0_0_9_) + ); + defparam plm_frm_ciao_baby_reg_frm0_char_3_0_0_14_.INIT = 16'h153F; + LUT4 plm_frm_ciao_baby_reg_frm0_char_3_0_0_14_ ( + .I0(plm_frm_N_61353), + .I1(plm_frm_N_61354), + .I2(plm_frm_reg_d2_td[14]), + .I3(plm_frm_reg_d2_td[46]), + .O(plm_frm_reg_frm0_char_3_0_0_14_) + ); + defparam plm_frm_ciao_baby_reg_frm0_char_3_i_0_10_.INIT = 16'hF351; + LUT4 plm_frm_ciao_baby_reg_frm0_char_3_i_0_10_ ( + .I0(plm_frm_N_61353), + .I1(plm_frm_N_61354), + .I2(plm_frm_reg_d2_td[10]), + .I3(plm_frm_reg_d2_td[42]), + .O(plm_frm_reg_frm0_char_3_i_0_10_) + ); + defparam plm_frm_ciao_baby_reg_frm0_char_3_i_0_12_.INIT = 16'hF351; + LUT4 plm_frm_ciao_baby_reg_frm0_char_3_i_0_12_ ( + .I0(plm_frm_N_61353), + .I1(plm_frm_N_61354), + .I2(plm_frm_reg_d2_td[12]), + .I3(plm_frm_reg_d2_td[44]), + .O(plm_frm_reg_frm0_char_3_i_0_12_) + ); + defparam plm_frm_ciao_baby_reg_frm0_is_k_3_i_m3_i_0_0_.INIT = 16'hF351; + LUT4 plm_frm_ciao_baby_reg_frm0_is_k_3_i_m3_i_0_0_ ( + .I0(plm_frm_N_61353), + .I1(plm_frm_N_61354), + .I2(plm_frm_reg_d2_charisk_0__1660), + .I3(plm_frm_reg_d2_charisk_4__1662), + .O(plm_frm_reg_frm0_is_k_3_i_m3_i_0[0]) + ); + defparam plm_frm_ciao_baby_reg_frm0_char_3_0_0_7_.INIT = 16'h153F; + LUT4 plm_frm_ciao_baby_reg_frm0_char_3_0_0_7_ ( + .I0(plm_frm_N_61353), + .I1(plm_frm_N_61354), + .I2(plm_frm_reg_d2_td[7]), + .I3(plm_frm_reg_d2_td[39]), + .O(plm_frm_reg_frm0_char_3_0_0_7_) + ); + defparam plm_frm_ciao_baby_reg_frm0_char_3_0_0_6_.INIT = 16'h153F; + LUT4 plm_frm_ciao_baby_reg_frm0_char_3_0_0_6_ ( + .I0(plm_frm_N_61353), + .I1(plm_frm_N_61354), + .I2(plm_frm_reg_d2_td[6]), + .I3(plm_frm_reg_d2_td[38]), + .O(plm_frm_reg_frm0_char_3_0_0_6_) + ); + defparam plm_frm_ciao_baby_reg_frm0_char_3_0_0_5_.INIT = 16'h153F; + LUT4 plm_frm_ciao_baby_reg_frm0_char_3_0_0_5_ ( + .I0(plm_frm_N_61353), + .I1(plm_frm_N_61354), + .I2(plm_frm_reg_d2_td[5]), + .I3(plm_frm_reg_d2_td[37]), + .O(plm_frm_reg_frm0_char_3_0_0_5_) + ); + defparam plm_frm_ciao_baby_reg_frm0_char_3_i_0_4_.INIT = 16'hF351; + LUT4 plm_frm_ciao_baby_reg_frm0_char_3_i_0_4_ ( + .I0(plm_frm_N_61353), + .I1(plm_frm_N_61354), + .I2(plm_frm_reg_d2_td[4]), + .I3(plm_frm_reg_d2_td[36]), + .O(plm_frm_reg_frm0_char_3_i_0_4_) + ); + defparam plm_frm_ciao_baby_reg_frm0_char_3_i_m3_0_0_1_.INIT = 16'h153F; + LUT4 plm_frm_ciao_baby_reg_frm0_char_3_i_m3_0_0_1_ ( + .I0(plm_frm_N_61353), + .I1(plm_frm_N_61354), + .I2(plm_frm_reg_d2_td[1]), + .I3(plm_frm_reg_d2_td[33]), + .O(plm_frm_reg_frm0_char_3_i_m3_0_0[1]) + ); + defparam plm_frm_ciao_baby_reg_frm0_char_3_i_0_3_.INIT = 16'hF351; + LUT4 plm_frm_ciao_baby_reg_frm0_char_3_i_0_3_ ( + .I0(plm_frm_N_61353), + .I1(plm_frm_N_61354), + .I2(plm_frm_reg_d2_td[3]), + .I3(plm_frm_reg_d2_td[35]), + .O(plm_frm_reg_frm0_char_3_i_0_3_) + ); + defparam plm_frm_ciao_baby_reg_frm0_char_3_0_m3_0_0_2_.INIT = 16'hF351; + LUT4 plm_frm_ciao_baby_reg_frm0_char_3_0_m3_0_0_2_ ( + .I0(plm_frm_N_61353), + .I1(plm_frm_N_61354), + .I2(plm_frm_reg_d2_td[2]), + .I3(plm_frm_reg_d2_td[34]), + .O(plm_frm_reg_frm0_char_3_0_m3_0_0[2]) + ); + defparam plm_frm_ciao_baby_reg_frm0_char_3_0_0_0_.INIT = 16'h153F; + LUT4 plm_frm_ciao_baby_reg_frm0_char_3_0_0_0_ ( + .I0(plm_frm_N_61353), + .I1(plm_frm_N_61354), + .I2(plm_frm_reg_d2_td[0]), + .I3(plm_frm_reg_d2_td[32]), + .O(plm_frm_reg_frm0_char_3_0_0_0_) + ); + defparam plm_frm_ciao_baby_reg_frm0_is_k_3_i_m3_i_a2_0_.INIT = 8'h04; + LUT3 plm_frm_ciao_baby_reg_frm0_is_k_3_i_m3_i_a2_0_ ( + .I0(plm_frm_N_56240_i), + .I1(cmmp_negotiated_width[0]), + .I2(plm_frm_reg_wd_sel[0]), + .O(plm_frm_N_58415) + ); + defparam plm_frm_by1_opportunity_l_i_0.INIT = 8'h20; + LUT3 plm_frm_by1_opportunity_l_i_0 ( + .I0(plm_frm_N_55877_i), + .I1(plm_N_55932_i), + .I2(plm_frm_reg_d2_idle_l_1659), + .O(plm_frm_N_51332_i) + ); + defparam plm_frm_ciao_baby_reg_frm0_char_3_0_a3_4_0_.INIT = 8'h4C; + LUT3 plm_frm_ciao_baby_reg_frm0_char_3_0_a3_4_0_ ( + .I0(plm_frm_N_55877_i), + .I1(plm_frm_N_61332), + .I2(plm_frm_reg_d2_idle_h_1658), + .O(plm_frm_N_61368) + ); + defparam plm_frm_ciao_baby_reg_frm0_char_3_0_a3_3_0_.INIT = 8'h4C; + LUT3 plm_frm_ciao_baby_reg_frm0_char_3_0_a3_3_0_ ( + .I0(plm_frm_N_55877_i), + .I1(plm_frm_N_61329), + .I2(plm_frm_reg_d2_idle_l_1659), + .O(plm_frm_N_61367) + ); + defparam plm_frm_ciao_baby_reg_frm0_char_3_0_a2_13_.INIT = 8'h08; + LUT3 plm_frm_ciao_baby_reg_frm0_char_3_0_a2_13_ ( + .I0(plm_frm_N_56240_i), + .I1(cmmp_negotiated_width[0]), + .I2(plm_frm_reg_wd_sel[0]), + .O(plm_frm_N_57627) + ); + defparam plm_frm_ciao_baby_reg_frm0_is_k_3_0_2_1_.INIT = 16'h1050; + LUT4 plm_frm_ciao_baby_reg_frm0_is_k_3_0_2_1_ ( + .I0(plm_frm_N_57641), + .I1(plm_frm_N_61329), + .I2(plm_frm_reg_frm0_is_k_3_0_0[1]), + .I3(plm_frm_reg_d2_charisk_3__1663), + .O(plm_frm_reg_frm0_is_k_3_0_2[1]) + ); + defparam plm_frm_ciao_baby_reg_frm0_char_3_0_2_8_.INIT = 16'h1050; + LUT4 plm_frm_ciao_baby_reg_frm0_char_3_0_2_8_ ( + .I0(plm_frm_N_57598), + .I1(plm_frm_N_61366), + .I2(plm_frm_reg_frm0_char_3_0_0_8_), + .I3(plm_frm_reg_d2_td[24]), + .O(plm_frm_reg_frm0_char_3_0_2_8_) + ); + defparam plm_frm_ciao_baby_reg_frm0_char_3_i_2_11_.INIT = 16'h5010; + LUT4 plm_frm_ciao_baby_reg_frm0_char_3_i_2_11_ ( + .I0(plm_frm_N_57619), + .I1(plm_frm_N_61366), + .I2(plm_frm_reg_frm0_char_3_i_0_11_), + .I3(plm_frm_reg_d2_td[27]), + .O(plm_frm_reg_frm0_char_3_i_2_11_) + ); + defparam plm_frm_ciao_baby_reg_frm0_char_3_0_2_9_.INIT = 16'h1050; + LUT4 plm_frm_ciao_baby_reg_frm0_char_3_0_2_9_ ( + .I0(plm_frm_N_57605), + .I1(plm_frm_N_61366), + .I2(plm_frm_reg_frm0_char_3_0_0_9_), + .I3(plm_frm_reg_d2_td[25]), + .O(plm_frm_reg_frm0_char_3_0_2_9_) + ); + defparam plm_frm_ciao_baby_reg_frm0_char_3_0_2_14_.INIT = 16'h1050; + LUT4 plm_frm_ciao_baby_reg_frm0_char_3_0_2_14_ ( + .I0(plm_frm_N_57640), + .I1(plm_frm_N_61366), + .I2(plm_frm_reg_frm0_char_3_0_0_14_), + .I3(plm_frm_reg_d2_td[30]), + .O(plm_frm_reg_frm0_char_3_0_2_14_) + ); + defparam plm_frm_ciao_baby_reg_frm0_char_3_i_2_10_.INIT = 16'h5010; + LUT4 plm_frm_ciao_baby_reg_frm0_char_3_i_2_10_ ( + .I0(plm_frm_N_57612), + .I1(plm_frm_N_61366), + .I2(plm_frm_reg_frm0_char_3_i_0_10_), + .I3(plm_frm_reg_d2_td[26]), + .O(plm_frm_reg_frm0_char_3_i_2_10_) + ); + defparam plm_frm_ciao_baby_reg_frm0_char_3_i_2_12_.INIT = 16'h5010; + LUT4 plm_frm_ciao_baby_reg_frm0_char_3_i_2_12_ ( + .I0(plm_frm_N_57626), + .I1(plm_frm_N_61366), + .I2(plm_frm_reg_frm0_char_3_i_0_12_), + .I3(plm_frm_reg_d2_td[28]), + .O(plm_frm_reg_frm0_char_3_i_2_12_) + ); + defparam plm_frm_ciao_baby_reg_frm0_char_3_0_2_6_.INIT = 16'h1050; + LUT4 plm_frm_ciao_baby_reg_frm0_char_3_0_2_6_ ( + .I0(plm_frm_N_57584), + .I1(plm_frm_N_61366), + .I2(plm_frm_reg_frm0_char_3_0_0_6_), + .I3(plm_frm_reg_d2_td[22]), + .O(plm_frm_reg_frm0_char_3_0_2_6_) + ); + defparam plm_frm_ciao_baby_reg_frm0_char_3_i_2_4_.INIT = 16'h5010; + LUT4 plm_frm_ciao_baby_reg_frm0_char_3_i_2_4_ ( + .I0(plm_frm_N_57569), + .I1(plm_frm_N_61366), + .I2(plm_frm_reg_frm0_char_3_i_0_4_), + .I3(plm_frm_reg_d2_td[20]), + .O(plm_frm_reg_frm0_char_3_i_2_4_) + ); + defparam plm_frm_ciao_baby_reg_frm0_char_3_i_m3_0_2_1_.INIT = 16'h1050; + LUT4 plm_frm_ciao_baby_reg_frm0_char_3_i_m3_0_2_1_ ( + .I0(plm_frm_N_58402), + .I1(plm_frm_N_61366), + .I2(plm_frm_reg_frm0_char_3_i_m3_0_0[1]), + .I3(plm_frm_reg_d2_td[17]), + .O(plm_frm_reg_frm0_char_3_i_m3_0_2[1]) + ); + defparam plm_frm_ciao_baby_reg_frm0_char_3_i_2_3_.INIT = 16'h5010; + LUT4 plm_frm_ciao_baby_reg_frm0_char_3_i_2_3_ ( + .I0(plm_frm_N_57562), + .I1(plm_frm_N_61366), + .I2(plm_frm_reg_frm0_char_3_i_0_3_), + .I3(plm_frm_reg_d2_td[19]), + .O(plm_frm_reg_frm0_char_3_i_2_3_) + ); + defparam plm_frm_ciao_baby_reg_frm0_char_3_0_m3_0_2_2_.INIT = 16'h5010; + LUT4 plm_frm_ciao_baby_reg_frm0_char_3_0_m3_0_2_2_ ( + .I0(plm_frm_N_58409), + .I1(plm_frm_N_61366), + .I2(plm_frm_reg_frm0_char_3_0_m3_0_0[2]), + .I3(plm_frm_reg_d2_td[18]), + .O(plm_frm_reg_frm0_char_3_0_m3_0_2[2]) + ); + defparam plm_frm_ciao_baby_reg_frm0_char_3_0_2_0_.INIT = 16'h1050; + LUT4 plm_frm_ciao_baby_reg_frm0_char_3_0_2_0_ ( + .I0(plm_frm_N_57555), + .I1(plm_frm_N_61366), + .I2(plm_frm_reg_frm0_char_3_0_0_0_), + .I3(plm_frm_reg_d2_td[16]), + .O(plm_frm_reg_frm0_char_3_0_2_0_) + ); + defparam plm_frm_ciao_baby_reg_frm_atomic_3_i_0.INIT = 16'h083B; + LUT4 plm_frm_ciao_baby_reg_frm_atomic_3_i_0 ( + .I0(plm_frm_N_56240_i), + .I1(cmmp_negotiated_width[0]), + .I2(plm_frm_reg_wd_sel[0]), + .I3(plm_frm_reg_state[0]), + .O(plm_frm_reg_frm_atomic_3_i_0) + ); + defparam plm_frm_ciao_baby_reg_frm_atomic_3_i_o3.INIT = 16'h8000; + LUT4 plm_frm_ciao_baby_reg_frm_atomic_3_i_o3 ( + .I0(plm_frm_N_51332_i), + .I1(plm_frm_N_57042_i), + .I2(plm_frm_N_57067_i), + .I3(plm_frm_reg_frm_atomic_3_i_o3_0), + .O(plm_frm_reg_frm_atomic_3_i_o3) + ); + defparam plm_frm_ciao_baby_reg_frm0_char_3_0_3_8_.INIT = 16'h135F; + LUT4 plm_frm_ciao_baby_reg_frm0_char_3_0_3_8_ ( + .I0(plm_frm_N_61367), + .I1(plm_frm_N_61368), + .I2(plm_frm_reg_d2_td[24]), + .I3(plm_frm_reg_d2_td[56]), + .O(plm_frm_reg_frm0_char_3_0_3_8_) + ); + defparam plm_frm_ciao_baby_reg_frm0_char_3_i_3_11_.INIT = 16'hF531; + LUT4 plm_frm_ciao_baby_reg_frm0_char_3_i_3_11_ ( + .I0(plm_frm_N_61367), + .I1(plm_frm_N_61368), + .I2(plm_frm_reg_d2_td[27]), + .I3(plm_frm_reg_d2_td[59]), + .O(plm_frm_reg_frm0_char_3_i_3_11_) + ); + defparam plm_frm_ciao_baby_reg_frm0_char_3_0_3_9_.INIT = 16'h135F; + LUT4 plm_frm_ciao_baby_reg_frm0_char_3_0_3_9_ ( + .I0(plm_frm_N_61367), + .I1(plm_frm_N_61368), + .I2(plm_frm_reg_d2_td[25]), + .I3(plm_frm_reg_d2_td[57]), + .O(plm_frm_reg_frm0_char_3_0_3_9_) + ); + defparam plm_frm_ciao_baby_reg_frm0_char_3_0_3_14_.INIT = 16'h135F; + LUT4 plm_frm_ciao_baby_reg_frm0_char_3_0_3_14_ ( + .I0(plm_frm_N_61367), + .I1(plm_frm_N_61368), + .I2(plm_frm_reg_d2_td[30]), + .I3(plm_frm_reg_d2_td[62]), + .O(plm_frm_reg_frm0_char_3_0_3_14_) + ); + defparam plm_frm_ciao_baby_reg_frm0_char_3_i_3_10_.INIT = 16'hF531; + LUT4 plm_frm_ciao_baby_reg_frm0_char_3_i_3_10_ ( + .I0(plm_frm_N_61367), + .I1(plm_frm_N_61368), + .I2(plm_frm_reg_d2_td[26]), + .I3(plm_frm_reg_d2_td[58]), + .O(plm_frm_reg_frm0_char_3_i_3_10_) + ); + defparam plm_frm_ciao_baby_reg_frm0_char_3_i_3_12_.INIT = 16'hF531; + LUT4 plm_frm_ciao_baby_reg_frm0_char_3_i_3_12_ ( + .I0(plm_frm_N_61367), + .I1(plm_frm_N_61368), + .I2(plm_frm_reg_d2_td[28]), + .I3(plm_frm_reg_d2_td[60]), + .O(plm_frm_reg_frm0_char_3_i_3_12_) + ); + defparam plm_frm_ciao_baby_reg_frm0_char_3_0_3_6_.INIT = 16'h135F; + LUT4 plm_frm_ciao_baby_reg_frm0_char_3_0_3_6_ ( + .I0(plm_frm_N_61367), + .I1(plm_frm_N_61368), + .I2(plm_frm_reg_d2_td[22]), + .I3(plm_frm_reg_d2_td[54]), + .O(plm_frm_reg_frm0_char_3_0_3_6_) + ); + defparam plm_frm_ciao_baby_reg_frm0_char_3_i_3_4_.INIT = 16'hF531; + LUT4 plm_frm_ciao_baby_reg_frm0_char_3_i_3_4_ ( + .I0(plm_frm_N_61367), + .I1(plm_frm_N_61368), + .I2(plm_frm_reg_d2_td[20]), + .I3(plm_frm_reg_d2_td[52]), + .O(plm_frm_reg_frm0_char_3_i_3_4_) + ); + defparam plm_frm_ciao_baby_reg_frm0_char_3_i_m3_0_3_1_.INIT = 16'h135F; + LUT4 plm_frm_ciao_baby_reg_frm0_char_3_i_m3_0_3_1_ ( + .I0(plm_frm_N_61367), + .I1(plm_frm_N_61368), + .I2(plm_frm_reg_d2_td[17]), + .I3(plm_frm_reg_d2_td[49]), + .O(plm_frm_reg_frm0_char_3_i_m3_0_3[1]) + ); + defparam plm_frm_ciao_baby_reg_frm0_char_3_i_3_3_.INIT = 16'hF531; + LUT4 plm_frm_ciao_baby_reg_frm0_char_3_i_3_3_ ( + .I0(plm_frm_N_61367), + .I1(plm_frm_N_61368), + .I2(plm_frm_reg_d2_td[19]), + .I3(plm_frm_reg_d2_td[51]), + .O(plm_frm_reg_frm0_char_3_i_3_3_) + ); + defparam plm_frm_ciao_baby_reg_frm0_char_3_0_m3_0_3_2_.INIT = 16'hF531; + LUT4 plm_frm_ciao_baby_reg_frm0_char_3_0_m3_0_3_2_ ( + .I0(plm_frm_N_61367), + .I1(plm_frm_N_61368), + .I2(plm_frm_reg_d2_td[18]), + .I3(plm_frm_reg_d2_td[50]), + .O(plm_frm_reg_frm0_char_3_0_m3_0_3[2]) + ); + defparam plm_frm_ciao_baby_reg_frm0_char_3_0_3_0_.INIT = 16'h135F; + LUT4 plm_frm_ciao_baby_reg_frm0_char_3_0_3_0_ ( + .I0(plm_frm_N_61367), + .I1(plm_frm_N_61368), + .I2(plm_frm_reg_d2_td[16]), + .I3(plm_frm_reg_d2_td[48]), + .O(plm_frm_reg_frm0_char_3_0_3_0_) + ); + defparam plm_frm_ciao_baby_reg_frm0_char_3_0_o3_8_.INIT = 4'h8; + LUT2 plm_frm_ciao_baby_reg_frm0_char_3_0_o3_8_ ( + .I0(plm_frm_reg_frm_atomic_3_i_o3), + .I1(plm_frm_reg_d2_idle_h_1658), + .O(plm_frm_N_55915_i) + ); + defparam plm_frm_ciao_baby_reg_frm0_char_3_0_a2_1_0_14_.INIT = 4'h4; + LUT2 plm_frm_ciao_baby_reg_frm0_char_3_0_a2_1_0_14_ ( + .I0(plm_frm_N_55915_i), + .I1(plm_frm_N_61385), + .O(plm_frm_N_57634_1) + ); + defparam plm_frm_ciao_baby_reg_frm0_char_3_0_a2_2_5_.INIT = 8'h08; + LUT3 plm_frm_ciao_baby_reg_frm0_char_3_0_a2_2_5_ ( + .I0(plm_frm_N_61385), + .I1(plm_frm_reg_frm_atomic_3_i_o3), + .I2(plm_frm_reg_d2_idle_h_1658), + .O(plm_frm_N_57573) + ); + defparam plm_frm_ciao_baby_reg_frm0_char_3_i_m3_0_1_15_.INIT = 8'h13; + LUT3 plm_frm_ciao_baby_reg_frm0_char_3_i_m3_0_1_15_ ( + .I0(plm_frm_N_55915_i), + .I1(plm_frm_N_57627), + .I2(plm_frm_N_61385), + .O(plm_frm_N_14937_1_i) + ); + defparam plm_frm_ciao_baby_reg_frm0_char_3_0_a3_5_0_.INIT = 4'h1; + LUT2 plm_frm_ciao_baby_reg_frm0_char_3_0_a3_5_0_ ( + .I0(plm_frm_N_55875_i), + .I1(cmmp_negotiated_width[0]), + .O(plm_frm_N_61390) + ); + defparam plm_frm_by1_opportunity_h_i_0.INIT = 8'h20; + LUT3_L plm_frm_by1_opportunity_h_i_0 ( + .I0(plm_frm_N_55877_i), + .I1(plm_N_55932_i), + .I2(plm_frm_reg_d2_idle_h_1658), + .LO(plm_frm_N_51330_i) + ); + defparam plm_frm_ciao_baby_reg_frm_atomic_3_i.INIT = 16'hF0E0; + LUT4_L plm_frm_ciao_baby_reg_frm_atomic_3_i ( + .I0(plm_frm_reg_frm_atomic_3_i_o3), + .I1(cmmp_negotiated_width[0]), + .I2(plm_frm_reg_frm_atomic_3_i_0), + .I3(plm_frm_reg_state[1]), + .LO(plm_frm_N_51380_i) + ); + defparam plm_frm_ciao_baby_N_85680_i.INIT = 16'hEFAF; + LUT4_L plm_frm_ciao_baby_N_85680_i ( + .I0(plm_frm_N_57573), + .I1(plm_frm_N_61390), + .I2(plm_frm_reg_frm0_char_3_0_4_7_), + .I3(plm_frm_reg_d2_td[31]), + .LO(plm_frm_N_85680_i) + ); + defparam plm_frm_ciao_baby_N_85679_i.INIT = 16'hBF3F; + LUT4_L plm_frm_ciao_baby_N_85679_i ( + .I0(plm_frm_N_61390), + .I1(plm_frm_reg_frm0_char_3_0_2_6_), + .I2(plm_frm_reg_frm0_char_3_0_3_6_), + .I3(plm_frm_reg_d2_td[30]), + .LO(plm_frm_N_85679_i) + ); + defparam plm_frm_ciao_baby_N_85678_i.INIT = 16'hEFAF; + LUT4_L plm_frm_ciao_baby_N_85678_i ( + .I0(plm_frm_N_57573), + .I1(plm_frm_N_61390), + .I2(plm_frm_reg_frm0_char_3_0_4_5_), + .I3(plm_frm_reg_d2_td[29]), + .LO(plm_frm_N_85678_i) + ); + defparam plm_frm_ciao_baby_reg_frm0_char_3_i_4_.INIT = 16'hC040; + LUT4_L plm_frm_ciao_baby_reg_frm0_char_3_i_4_ ( + .I0(plm_frm_N_61390), + .I1(plm_frm_reg_frm0_char_3_i_2_4_), + .I2(plm_frm_reg_frm0_char_3_i_3_4_), + .I3(plm_frm_reg_d2_td[28]), + .LO(plm_frm_N_51364_i) + ); + defparam plm_frm_ciao_baby_reg_frm0_char_3_i_3_.INIT = 16'hC040; + LUT4_L plm_frm_ciao_baby_reg_frm0_char_3_i_3_ ( + .I0(plm_frm_N_61390), + .I1(plm_frm_reg_frm0_char_3_i_2_3_), + .I2(plm_frm_reg_frm0_char_3_i_3_3_), + .I3(plm_frm_reg_d2_td[27]), + .LO(plm_frm_N_51362_i) + ); + defparam plm_frm_ciao_baby_reg_frm0_char_3_0_m3_0_2_.INIT = 16'hC040; + LUT4_L plm_frm_ciao_baby_reg_frm0_char_3_0_m3_0_2_ ( + .I0(plm_frm_N_61390), + .I1(plm_frm_reg_frm0_char_3_0_m3_0_2[2]), + .I2(plm_frm_reg_frm0_char_3_0_m3_0_3[2]), + .I3(plm_frm_reg_d2_td[26]), + .LO(plm_frm_N_14936_i) + ); + defparam plm_frm_ciao_baby_N_85688_i.INIT = 16'hBF3F; + LUT4_L plm_frm_ciao_baby_N_85688_i ( + .I0(plm_frm_N_61390), + .I1(plm_frm_reg_frm0_char_3_i_m3_0_2[1]), + .I2(plm_frm_reg_frm0_char_3_i_m3_0_3[1]), + .I3(plm_frm_reg_d2_td[25]), + .LO(plm_frm_N_85688_i) + ); + defparam plm_frm_ciao_baby_N_85675_i.INIT = 16'hBF3F; + LUT4_L plm_frm_ciao_baby_N_85675_i ( + .I0(plm_frm_N_61390), + .I1(plm_frm_reg_frm0_char_3_0_2_0_), + .I2(plm_frm_reg_frm0_char_3_0_3_0_), + .I3(plm_frm_reg_d2_td[24]), + .LO(plm_frm_N_85675_i) + ); + defparam plm_frm_ciao_baby_N_85687_i.INIT = 16'hABFF; + LUT4_L plm_frm_ciao_baby_N_85687_i ( + .I0(plm_frm_N_57627), + .I1(plm_frm_un7_by4_frm1_char_i_o2[0]), + .I2(cmmp_negotiated_width[0]), + .I3(plm_frm_reg_frm0_is_k_3_0_2[1]), + .LO(plm_frm_N_85687_i) + ); + defparam plm_frm_ciao_baby_reg_frm0_is_k_3_i_m3_i_0_.INIT = 16'h5010; + LUT4_L plm_frm_ciao_baby_reg_frm0_is_k_3_i_m3_i_0_ ( + .I0(plm_frm_N_58415), + .I1(plm_frm_N_61390), + .I2(plm_frm_reg_frm0_is_k_3_i_m3_i_0[0]), + .I3(plm_frm_reg_d2_charisk_3__1663), + .LO(plm_frm_N_52046_i) + ); + defparam plm_frm_ciao_baby_N_85686_i.INIT = 16'hBF3F; + LUT4_L plm_frm_ciao_baby_N_85686_i ( + .I0(plm_frm_N_57634_1), + .I1(plm_frm_reg_frm0_char_3_0_2_14_), + .I2(plm_frm_reg_frm0_char_3_0_3_14_), + .I3(plm_frm_reg_d2_td[62]), + .LO(plm_frm_N_85686_i) + ); + defparam plm_frm_ciao_baby_reg_frm0_char_3_i_12_.INIT = 16'hC040; + LUT4_L plm_frm_ciao_baby_reg_frm0_char_3_i_12_ ( + .I0(plm_frm_N_57634_1), + .I1(plm_frm_reg_frm0_char_3_i_2_12_), + .I2(plm_frm_reg_frm0_char_3_i_3_12_), + .I3(plm_frm_reg_d2_td[60]), + .LO(plm_frm_N_51375_i) + ); + defparam plm_frm_ciao_baby_reg_frm0_char_3_i_11_.INIT = 16'hC040; + LUT4_L plm_frm_ciao_baby_reg_frm0_char_3_i_11_ ( + .I0(plm_frm_N_57634_1), + .I1(plm_frm_reg_frm0_char_3_i_2_11_), + .I2(plm_frm_reg_frm0_char_3_i_3_11_), + .I3(plm_frm_reg_d2_td[59]), + .LO(plm_frm_N_51373_i) + ); + defparam plm_frm_ciao_baby_reg_frm0_char_3_i_10_.INIT = 16'hC040; + LUT4_L plm_frm_ciao_baby_reg_frm0_char_3_i_10_ ( + .I0(plm_frm_N_57634_1), + .I1(plm_frm_reg_frm0_char_3_i_2_10_), + .I2(plm_frm_reg_frm0_char_3_i_3_10_), + .I3(plm_frm_reg_d2_td[58]), + .LO(plm_frm_N_51371_i) + ); + defparam plm_frm_ciao_baby_N_85682_i.INIT = 16'hBF3F; + LUT4_L plm_frm_ciao_baby_N_85682_i ( + .I0(plm_frm_N_57634_1), + .I1(plm_frm_reg_frm0_char_3_0_2_9_), + .I2(plm_frm_reg_frm0_char_3_0_3_9_), + .I3(plm_frm_reg_d2_td[57]), + .LO(plm_frm_N_85682_i) + ); + defparam plm_frm_ciao_baby_N_85681_i.INIT = 16'hBF3F; + LUT4_L plm_frm_ciao_baby_N_85681_i ( + .I0(plm_frm_N_57634_1), + .I1(plm_frm_reg_frm0_char_3_0_2_8_), + .I2(plm_frm_reg_frm0_char_3_0_3_8_), + .I3(plm_frm_reg_d2_td[56]), + .LO(plm_frm_N_85681_i) + ); + defparam plm_frm_delay_one_reg_d1_idleflag_hh_3.INIT = 16'h8000; + LUT4_L plm_frm_delay_one_reg_d1_idleflag_hh_3 ( + .I0(plm_frm_reg_d1_idleflag_hh_3_0), + .I1(plm_frm_reg_d1_idleflag_hh_3_4), + .I2(plm_frm_reg_d0_td[60]), + .I3(plm_frm_reg_d0_td[61]), + .LO(plm_frm_reg_d1_idleflag_hh_3) + ); + defparam plm_frm_delay_one_reg_d1_idleflag_hl_3.INIT = 16'h8000; + LUT4_L plm_frm_delay_one_reg_d1_idleflag_hl_3 ( + .I0(plm_frm_reg_d1_idleflag_hl_3_0), + .I1(plm_frm_reg_d1_idleflag_hl_3_4), + .I2(plm_frm_reg_d0_td[36]), + .I3(plm_frm_reg_d0_td[37]), + .LO(plm_frm_reg_d1_idleflag_hl_3) + ); + defparam plm_frm_delay_one_reg_d1_idleflag_lh_3.INIT = 16'h8000; + LUT4_L plm_frm_delay_one_reg_d1_idleflag_lh_3 ( + .I0(plm_frm_reg_d1_idleflag_lh_3_0), + .I1(plm_frm_reg_d1_idleflag_lh_3_4), + .I2(plm_frm_reg_d0_td[28]), + .I3(plm_frm_reg_d0_td[29]), + .LO(plm_frm_reg_d1_idleflag_lh_3) + ); + defparam plm_frm_delay_one_reg_d1_idleflag_ll_3.INIT = 16'h8000; + LUT4_L plm_frm_delay_one_reg_d1_idleflag_ll_3 ( + .I0(plm_frm_reg_d1_idleflag_ll_3_0), + .I1(plm_frm_reg_d1_idleflag_ll_3_4), + .I2(plm_frm_reg_d0_td[4]), + .I3(plm_frm_reg_d0_td[5]), + .LO(plm_frm_reg_d1_idleflag_ll_3) + ); + defparam plm_frm_N_11312_i_i.INIT = 4'h2; + LUT2_L plm_frm_N_11312_i_i ( + .I0(plm_frm_N_57042_i), + .I1(plm_frm_N_61261), + .LO(plm_frm_N_55314_i) + ); + defparam plm_frm_reg_d2_charisk_1_sqmuxa_i_0.INIT = 8'h04; + LUT3_L plm_frm_reg_d2_charisk_1_sqmuxa_i_0 ( + .I0(plm_frm_N_55866_i_0), + .I1(plm_frm_d1_end_h_1643), + .I2(plm_frm_reg_d1_idleflag_hl_1655), + .LO(plm_frm_N_51382_i) + ); + defparam plm_frm_reg_d2_charisk_1_sqmuxa_3_i_0.INIT = 8'h04; + LUT3_L plm_frm_reg_d2_charisk_1_sqmuxa_3_i_0 ( + .I0(plm_frm_N_55867_i_0), + .I1(plm_frm_d1_end_h_1643), + .I2(plm_frm_reg_d1_idleflag_lh_1656), + .LO(plm_frm_N_51388_i) + ); + defparam plm_frm_delay_two_b_N_87072_i.INIT = 16'hCE0A; + LUT4_L plm_frm_delay_two_b_N_87072_i ( + .I0(plm_frm_N_51384_i), + .I1(plm_frm_N_61261), + .I2(plm_frm_reg_d1_tctrl_l_1647), + .I3(plm_frm_reg_d1_td[63]), + .LO(plm_frm_N_87072_i) + ); + defparam plm_frm_delay_two_b_reg_d2_td_13_1_f0_i_62_.INIT = 16'h1302; + LUT4_L plm_frm_delay_two_b_reg_d2_td_13_1_f0_i_62_ ( + .I0(plm_frm_N_56105_i), + .I1(plm_frm_N_57648), + .I2(plm_frm_reg_d1_idleflag_hh_1654), + .I3(plm_frm_reg_d1_td[62]), + .LO(plm_frm_N_51438_i) + ); + defparam plm_frm_delay_two_b_N_87033_i.INIT = 16'hCE0A; + LUT4_L plm_frm_delay_two_b_N_87033_i ( + .I0(plm_frm_N_51384_i), + .I1(plm_frm_N_61261), + .I2(plm_frm_reg_d1_tctrl_l_1647), + .I3(plm_frm_reg_d1_td[61]), + .LO(plm_frm_N_87033_i) + ); + defparam plm_frm_delay_two_b_reg_d2_td_13_1_f0_i_60_.INIT = 16'h1302; + LUT4_L plm_frm_delay_two_b_reg_d2_td_13_1_f0_i_60_ ( + .I0(plm_frm_N_56105_i), + .I1(plm_frm_N_57648), + .I2(plm_frm_reg_d1_idleflag_hh_1654), + .I3(plm_frm_reg_d1_td[60]), + .LO(plm_frm_N_51436_i) + ); + defparam plm_frm_delay_two_b_reg_d2_td_13_1_f0_i_59_.INIT = 16'h1302; + LUT4_L plm_frm_delay_two_b_reg_d2_td_13_1_f0_i_59_ ( + .I0(plm_frm_N_56105_i), + .I1(plm_frm_N_57648), + .I2(plm_frm_reg_d1_idleflag_hh_1654), + .I3(plm_frm_reg_d1_td[59]), + .LO(plm_frm_N_51434_i) + ); + defparam plm_frm_delay_two_b_N_87073_i.INIT = 16'hECA0; + LUT4_L plm_frm_delay_two_b_N_87073_i ( + .I0(plm_frm_N_51384_i), + .I1(plm_frm_N_61261), + .I2(plm_frm_reg_d1_tctrl_l_1647), + .I3(plm_frm_reg_d1_td[58]), + .LO(plm_frm_N_87073_i) + ); + defparam plm_frm_delay_two_b_N_87034_i.INIT = 16'hCE0A; + LUT4_L plm_frm_delay_two_b_N_87034_i ( + .I0(plm_frm_N_51384_i), + .I1(plm_frm_N_61261), + .I2(plm_frm_reg_d1_tctrl_l_1647), + .I3(plm_frm_reg_d1_td[57]), + .LO(plm_frm_N_87034_i) + ); + defparam plm_frm_delay_two_b_N_87035_i.INIT = 16'hCE0A; + LUT4_L plm_frm_delay_two_b_N_87035_i ( + .I0(plm_frm_N_51384_i), + .I1(plm_frm_N_61261), + .I2(plm_frm_reg_d1_tctrl_l_1647), + .I3(plm_frm_reg_d1_td[56]), + .LO(plm_frm_N_87035_i) + ); + defparam plm_frm_delay_two_b_reg_d2_td_13_i_55_.INIT = 4'h8; + LUT2_L plm_frm_delay_two_b_reg_d2_td_13_i_55_ ( + .I0(plm_frm_N_63791_i), + .I1(plm_frm_reg_d1_td[55]), + .LO(plm_frm_N_51432_i) + ); + defparam plm_frm_delay_two_b_reg_d2_td_13_i_54_.INIT = 4'h8; + LUT2_L plm_frm_delay_two_b_reg_d2_td_13_i_54_ ( + .I0(plm_frm_N_63791_i), + .I1(plm_frm_reg_d1_td[54]), + .LO(plm_frm_N_51430_i) + ); + defparam plm_frm_delay_two_b_reg_d2_td_13_i_53_.INIT = 4'h8; + LUT2_L plm_frm_delay_two_b_reg_d2_td_13_i_53_ ( + .I0(plm_frm_N_63791_i), + .I1(plm_frm_reg_d1_td[53]), + .LO(plm_frm_N_51428_i) + ); + defparam plm_frm_delay_two_b_reg_d2_td_13_i_52_.INIT = 4'h8; + LUT2_L plm_frm_delay_two_b_reg_d2_td_13_i_52_ ( + .I0(plm_frm_N_63791_i), + .I1(plm_frm_reg_d1_td[52]), + .LO(plm_frm_N_51426_i) + ); + defparam plm_frm_delay_two_b_reg_d2_td_13_i_51_.INIT = 4'h8; + LUT2_L plm_frm_delay_two_b_reg_d2_td_13_i_51_ ( + .I0(plm_frm_N_63791_i), + .I1(plm_frm_reg_d1_td[51]), + .LO(plm_frm_N_51424_i) + ); + defparam plm_frm_delay_two_b_reg_d2_td_13_i_50_.INIT = 4'h8; + LUT2_L plm_frm_delay_two_b_reg_d2_td_13_i_50_ ( + .I0(plm_frm_N_63791_i), + .I1(plm_frm_reg_d1_td[50]), + .LO(plm_frm_N_51422_i) + ); + defparam plm_frm_delay_two_b_reg_d2_td_13_i_49_.INIT = 4'h8; + LUT2_L plm_frm_delay_two_b_reg_d2_td_13_i_49_ ( + .I0(plm_frm_N_63791_i), + .I1(plm_frm_reg_d1_td[49]), + .LO(plm_frm_N_51420_i) + ); + defparam plm_frm_delay_two_b_reg_d2_td_13_i_48_.INIT = 4'h8; + LUT2_L plm_frm_delay_two_b_reg_d2_td_13_i_48_ ( + .I0(plm_frm_N_63791_i), + .I1(plm_frm_reg_d1_td[48]), + .LO(plm_frm_N_51418_i) + ); + defparam plm_frm_delay_two_b_reg_d2_td_13_i_47_.INIT = 4'h8; + LUT2_L plm_frm_delay_two_b_reg_d2_td_13_i_47_ ( + .I0(plm_frm_N_63791_i), + .I1(plm_frm_reg_d1_td[47]), + .LO(plm_frm_N_51416_i) + ); + defparam plm_frm_delay_two_b_reg_d2_td_13_i_46_.INIT = 4'h8; + LUT2_L plm_frm_delay_two_b_reg_d2_td_13_i_46_ ( + .I0(plm_frm_N_63791_i), + .I1(plm_frm_reg_d1_td[46]), + .LO(plm_frm_N_51414_i) + ); + defparam plm_frm_delay_two_b_reg_d2_td_13_i_45_.INIT = 4'h8; + LUT2_L plm_frm_delay_two_b_reg_d2_td_13_i_45_ ( + .I0(plm_frm_N_63791_i), + .I1(plm_frm_reg_d1_td[45]), + .LO(plm_frm_N_51412_i) + ); + defparam plm_frm_delay_two_b_reg_d2_td_13_i_44_.INIT = 4'h8; + LUT2_L plm_frm_delay_two_b_reg_d2_td_13_i_44_ ( + .I0(plm_frm_N_63791_i), + .I1(plm_frm_reg_d1_td[44]), + .LO(plm_frm_N_51410_i) + ); + defparam plm_frm_delay_two_b_reg_d2_td_13_i_43_.INIT = 4'h8; + LUT2_L plm_frm_delay_two_b_reg_d2_td_13_i_43_ ( + .I0(plm_frm_N_63791_i), + .I1(plm_frm_reg_d1_td[43]), + .LO(plm_frm_N_51408_i) + ); + defparam plm_frm_delay_two_b_reg_d2_td_13_i_42_.INIT = 4'h8; + LUT2_L plm_frm_delay_two_b_reg_d2_td_13_i_42_ ( + .I0(plm_frm_N_63791_i), + .I1(plm_frm_reg_d1_td[42]), + .LO(plm_frm_N_51406_i) + ); + defparam plm_frm_delay_two_b_reg_d2_td_13_i_41_.INIT = 4'h8; + LUT2_L plm_frm_delay_two_b_reg_d2_td_13_i_41_ ( + .I0(plm_frm_N_63791_i), + .I1(plm_frm_reg_d1_td[41]), + .LO(plm_frm_N_51404_i) + ); + defparam plm_frm_delay_two_b_reg_d2_td_13_i_40_.INIT = 4'h8; + LUT2_L plm_frm_delay_two_b_reg_d2_td_13_i_40_ ( + .I0(plm_frm_N_63791_i), + .I1(plm_frm_reg_d1_td[40]), + .LO(plm_frm_N_51402_i) + ); + defparam plm_frm_delay_two_b_reg_d2_td_13_1_f0_i_39_.INIT = 16'hCC40; + LUT4_L plm_frm_delay_two_b_reg_d2_td_13_1_f0_i_39_ ( + .I0(plm_frm_N_55866_i_0), + .I1(plm_frm_N_63791_i), + .I2(plm_frm_d1_end_h_1643), + .I3(plm_frm_reg_d1_td[39]), + .LO(plm_frm_N_51400_i) + ); + defparam plm_frm_delay_two_b_reg_d2_td_13_1_f0_i_38_.INIT = 16'hCC40; + LUT4_L plm_frm_delay_two_b_reg_d2_td_13_1_f0_i_38_ ( + .I0(plm_frm_N_55866_i_0), + .I1(plm_frm_N_63791_i), + .I2(plm_frm_d1_end_h_1643), + .I3(plm_frm_reg_d1_td[38]), + .LO(plm_frm_N_51398_i) + ); + defparam plm_frm_delay_two_b_reg_d2_td_13_1_f0_i_37_.INIT = 16'hCC40; + LUT4_L plm_frm_delay_two_b_reg_d2_td_13_1_f0_i_37_ ( + .I0(plm_frm_N_55866_i_0), + .I1(plm_frm_N_63791_i), + .I2(plm_frm_d1_end_h_1643), + .I3(plm_frm_reg_d1_td[37]), + .LO(plm_frm_N_51396_i) + ); + defparam plm_frm_delay_two_b_reg_d2_td_13_1_f0_i_36_.INIT = 16'hCC40; + LUT4_L plm_frm_delay_two_b_reg_d2_td_13_1_f0_i_36_ ( + .I0(plm_frm_N_55866_i_0), + .I1(plm_frm_N_63791_i), + .I2(plm_frm_d1_end_h_1643), + .I3(plm_frm_reg_d1_td[36]), + .LO(plm_frm_N_51394_i) + ); + defparam plm_frm_delay_two_b_reg_d2_td_13_1_f0_i_35_.INIT = 16'hCC40; + LUT4_L plm_frm_delay_two_b_reg_d2_td_13_1_f0_i_35_ ( + .I0(plm_frm_N_55866_i_0), + .I1(plm_frm_N_63791_i), + .I2(plm_frm_d1_end_h_1643), + .I3(plm_frm_reg_d1_td[35]), + .LO(plm_frm_N_51392_i) + ); + defparam plm_frm_delay_two_b_reg_d2_td_13_1_f0_i_34_.INIT = 16'hCC40; + LUT4_L plm_frm_delay_two_b_reg_d2_td_13_1_f0_i_34_ ( + .I0(plm_frm_N_55866_i_0), + .I1(plm_frm_N_63791_i), + .I2(plm_frm_d1_end_h_1643), + .I3(plm_frm_reg_d1_td[34]), + .LO(plm_frm_N_51390_i) + ); + defparam plm_frm_delay_two_b_reg_d2_td_13_0_iv_0_33_.INIT = 8'h20; + LUT3_L plm_frm_delay_two_b_reg_d2_td_13_0_iv_0_33_ ( + .I0(plm_frm_N_57040_i), + .I1(plm_frm_d1_end_h_1643), + .I2(plm_frm_reg_d1_td[33]), + .LO(plm_frm_N_9897_i) + ); + defparam plm_frm_delay_two_b_reg_d2_td_13_0_iv_0_32_.INIT = 8'hA8; + LUT3_L plm_frm_delay_two_b_reg_d2_td_13_0_iv_0_32_ ( + .I0(plm_frm_N_57040_i), + .I1(plm_frm_d1_end_h_1643), + .I2(plm_frm_reg_d1_td[32]), + .LO(plm_frm_N_9899_i) + ); + defparam plm_frm_delay_two_b_reg_d2_td_24_0_iv_0_31_.INIT = 16'h2A08; + LUT4_L plm_frm_delay_two_b_reg_d2_td_24_0_iv_0_31_ ( + .I0(plm_frm_N_56109_i), + .I1(plm_frm_d1_end_h_1643), + .I2(plm_frm_reg_d1_tctrl_l_1647), + .I3(plm_frm_reg_d1_td[31]), + .LO(plm_frm_N_9882_i) + ); + defparam plm_frm_delay_two_b_reg_d2_td_24_1_f0_i_30_.INIT = 16'hCC40; + LUT4_L plm_frm_delay_two_b_reg_d2_td_24_1_f0_i_30_ ( + .I0(plm_frm_N_55867_i_0), + .I1(plm_frm_N_63777_i), + .I2(plm_frm_d1_end_h_1643), + .I3(plm_frm_reg_d1_td[30]), + .LO(plm_frm_N_51488_i) + ); + defparam plm_frm_delay_two_b_reg_d2_td_24_0_iv_0_29_.INIT = 16'h2A08; + LUT4_L plm_frm_delay_two_b_reg_d2_td_24_0_iv_0_29_ ( + .I0(plm_frm_N_56109_i), + .I1(plm_frm_d1_end_h_1643), + .I2(plm_frm_reg_d1_tctrl_l_1647), + .I3(plm_frm_reg_d1_td[29]), + .LO(plm_frm_N_9884_i) + ); + defparam plm_frm_delay_two_b_reg_d2_td_24_1_f0_i_28_.INIT = 16'hCC40; + LUT4_L plm_frm_delay_two_b_reg_d2_td_24_1_f0_i_28_ ( + .I0(plm_frm_N_55867_i_0), + .I1(plm_frm_N_63777_i), + .I2(plm_frm_d1_end_h_1643), + .I3(plm_frm_reg_d1_td[28]), + .LO(plm_frm_N_51486_i) + ); + defparam plm_frm_delay_two_b_reg_d2_td_24_1_f0_i_27_.INIT = 16'hCC40; + LUT4_L plm_frm_delay_two_b_reg_d2_td_24_1_f0_i_27_ ( + .I0(plm_frm_N_55867_i_0), + .I1(plm_frm_N_63777_i), + .I2(plm_frm_d1_end_h_1643), + .I3(plm_frm_reg_d1_td[27]), + .LO(plm_frm_N_51484_i) + ); + defparam plm_frm_delay_two_b_reg_d2_td_24_0_iv_0_26_.INIT = 16'hA280; + LUT4_L plm_frm_delay_two_b_reg_d2_td_24_0_iv_0_26_ ( + .I0(plm_frm_N_56109_i), + .I1(plm_frm_d1_end_h_1643), + .I2(plm_frm_reg_d1_tctrl_l_1647), + .I3(plm_frm_reg_d1_td[26]), + .LO(plm_frm_N_9885_i) + ); + defparam plm_frm_delay_two_b_reg_d2_td_24_0_iv_0_25_.INIT = 16'h2A08; + LUT4_L plm_frm_delay_two_b_reg_d2_td_24_0_iv_0_25_ ( + .I0(plm_frm_N_56109_i), + .I1(plm_frm_d1_end_h_1643), + .I2(plm_frm_reg_d1_tctrl_l_1647), + .I3(plm_frm_reg_d1_td[25]), + .LO(plm_frm_N_9886_i) + ); + defparam plm_frm_delay_two_b_reg_d2_td_24_0_iv_0_24_.INIT = 16'h2A08; + LUT4_L plm_frm_delay_two_b_reg_d2_td_24_0_iv_0_24_ ( + .I0(plm_frm_N_56109_i), + .I1(plm_frm_d1_end_h_1643), + .I2(plm_frm_reg_d1_tctrl_l_1647), + .I3(plm_frm_reg_d1_td[24]), + .LO(plm_frm_N_9887_i) + ); + defparam plm_frm_delay_two_b_reg_d2_td_24_i_23_.INIT = 4'h8; + LUT2_L plm_frm_delay_two_b_reg_d2_td_24_i_23_ ( + .I0(plm_frm_N_63777_i), + .I1(plm_frm_reg_d1_td[23]), + .LO(plm_frm_N_51482_i) + ); + defparam plm_frm_delay_two_b_reg_d2_td_24_i_22_.INIT = 4'h8; + LUT2_L plm_frm_delay_two_b_reg_d2_td_24_i_22_ ( + .I0(plm_frm_N_63777_i), + .I1(plm_frm_reg_d1_td[22]), + .LO(plm_frm_N_51480_i) + ); + defparam plm_frm_delay_two_b_reg_d2_td_24_i_21_.INIT = 4'h8; + LUT2_L plm_frm_delay_two_b_reg_d2_td_24_i_21_ ( + .I0(plm_frm_N_63777_i), + .I1(plm_frm_reg_d1_td[21]), + .LO(plm_frm_N_51478_i) + ); + defparam plm_frm_delay_two_b_reg_d2_td_24_i_20_.INIT = 4'h8; + LUT2_L plm_frm_delay_two_b_reg_d2_td_24_i_20_ ( + .I0(plm_frm_N_63777_i), + .I1(plm_frm_reg_d1_td[20]), + .LO(plm_frm_N_51476_i) + ); + defparam plm_frm_delay_two_b_reg_d2_td_24_i_19_.INIT = 4'h8; + LUT2_L plm_frm_delay_two_b_reg_d2_td_24_i_19_ ( + .I0(plm_frm_N_63777_i), + .I1(plm_frm_reg_d1_td[19]), + .LO(plm_frm_N_51474_i) + ); + defparam plm_frm_delay_two_b_reg_d2_td_24_i_18_.INIT = 4'h8; + LUT2_L plm_frm_delay_two_b_reg_d2_td_24_i_18_ ( + .I0(plm_frm_N_63777_i), + .I1(plm_frm_reg_d1_td[18]), + .LO(plm_frm_N_51472_i) + ); + defparam plm_frm_delay_two_b_reg_d2_td_24_i_17_.INIT = 4'h8; + LUT2_L plm_frm_delay_two_b_reg_d2_td_24_i_17_ ( + .I0(plm_frm_N_63777_i), + .I1(plm_frm_reg_d1_td[17]), + .LO(plm_frm_N_51470_i) + ); + defparam plm_frm_delay_two_b_reg_d2_td_24_i_16_.INIT = 4'h8; + LUT2_L plm_frm_delay_two_b_reg_d2_td_24_i_16_ ( + .I0(plm_frm_N_63777_i), + .I1(plm_frm_reg_d1_td[16]), + .LO(plm_frm_N_51468_i) + ); + defparam plm_frm_delay_two_b_reg_d2_td_24_i_15_.INIT = 4'h8; + LUT2_L plm_frm_delay_two_b_reg_d2_td_24_i_15_ ( + .I0(plm_frm_N_63777_i), + .I1(plm_frm_reg_d1_td[15]), + .LO(plm_frm_N_51466_i) + ); + defparam plm_frm_delay_two_b_reg_d2_td_24_i_14_.INIT = 4'h8; + LUT2_L plm_frm_delay_two_b_reg_d2_td_24_i_14_ ( + .I0(plm_frm_N_63777_i), + .I1(plm_frm_reg_d1_td[14]), + .LO(plm_frm_N_51464_i) + ); + defparam plm_frm_delay_two_b_reg_d2_td_24_i_13_.INIT = 4'h8; + LUT2_L plm_frm_delay_two_b_reg_d2_td_24_i_13_ ( + .I0(plm_frm_N_63777_i), + .I1(plm_frm_reg_d1_td[13]), + .LO(plm_frm_N_51462_i) + ); + defparam plm_frm_delay_two_b_reg_d2_td_24_i_12_.INIT = 4'h8; + LUT2_L plm_frm_delay_two_b_reg_d2_td_24_i_12_ ( + .I0(plm_frm_N_63777_i), + .I1(plm_frm_reg_d1_td[12]), + .LO(plm_frm_N_51460_i) + ); + defparam plm_frm_delay_two_b_reg_d2_td_24_i_11_.INIT = 4'h8; + LUT2_L plm_frm_delay_two_b_reg_d2_td_24_i_11_ ( + .I0(plm_frm_N_63777_i), + .I1(plm_frm_reg_d1_td[11]), + .LO(plm_frm_N_51458_i) + ); + defparam plm_frm_delay_two_b_reg_d2_td_24_i_10_.INIT = 4'h8; + LUT2_L plm_frm_delay_two_b_reg_d2_td_24_i_10_ ( + .I0(plm_frm_N_63777_i), + .I1(plm_frm_reg_d1_td[10]), + .LO(plm_frm_N_51456_i) + ); + defparam plm_frm_delay_two_b_reg_d2_td_24_i_9_.INIT = 4'h8; + LUT2_L plm_frm_delay_two_b_reg_d2_td_24_i_9_ ( + .I0(plm_frm_N_63777_i), + .I1(plm_frm_reg_d1_td[9]), + .LO(plm_frm_N_51454_i) + ); + defparam plm_frm_delay_two_b_reg_d2_td_24_i_8_.INIT = 4'h8; + LUT2_L plm_frm_delay_two_b_reg_d2_td_24_i_8_ ( + .I0(plm_frm_N_63777_i), + .I1(plm_frm_reg_d1_td[8]), + .LO(plm_frm_N_51452_i) + ); + defparam plm_frm_delay_two_b_reg_d2_td_24_1_f0_i_7_.INIT = 16'h1302; + LUT4_L plm_frm_delay_two_b_reg_d2_td_24_1_f0_i_7_ ( + .I0(plm_frm_N_56005_i), + .I1(plm_frm_N_57655), + .I2(plm_frm_reg_d1_idleflag_ll_1657), + .I3(plm_frm_reg_d1_td[7]), + .LO(plm_frm_N_51450_i) + ); + defparam plm_frm_delay_two_b_reg_d2_td_24_1_f0_i_6_.INIT = 16'h1302; + LUT4_L plm_frm_delay_two_b_reg_d2_td_24_1_f0_i_6_ ( + .I0(plm_frm_N_56005_i), + .I1(plm_frm_N_57655), + .I2(plm_frm_reg_d1_idleflag_ll_1657), + .I3(plm_frm_reg_d1_td[6]), + .LO(plm_frm_N_51448_i) + ); + defparam plm_frm_delay_two_b_reg_d2_td_24_1_f0_i_5_.INIT = 16'h1302; + LUT4_L plm_frm_delay_two_b_reg_d2_td_24_1_f0_i_5_ ( + .I0(plm_frm_N_56005_i), + .I1(plm_frm_N_57655), + .I2(plm_frm_reg_d1_idleflag_ll_1657), + .I3(plm_frm_reg_d1_td[5]), + .LO(plm_frm_N_51446_i) + ); + defparam plm_frm_delay_two_b_reg_d2_td_24_1_f0_i_4_.INIT = 16'h1302; + LUT4_L plm_frm_delay_two_b_reg_d2_td_24_1_f0_i_4_ ( + .I0(plm_frm_N_56005_i), + .I1(plm_frm_N_57655), + .I2(plm_frm_reg_d1_idleflag_ll_1657), + .I3(plm_frm_reg_d1_td[4]), + .LO(plm_frm_N_51444_i) + ); + defparam plm_frm_delay_two_b_reg_d2_td_24_1_f0_i_3_.INIT = 16'h1302; + LUT4_L plm_frm_delay_two_b_reg_d2_td_24_1_f0_i_3_ ( + .I0(plm_frm_N_56005_i), + .I1(plm_frm_N_57655), + .I2(plm_frm_reg_d1_idleflag_ll_1657), + .I3(plm_frm_reg_d1_td[3]), + .LO(plm_frm_N_51442_i) + ); + defparam plm_frm_delay_two_b_reg_d2_td_24_1_f0_i_2_.INIT = 16'h1302; + LUT4_L plm_frm_delay_two_b_reg_d2_td_24_1_f0_i_2_ ( + .I0(plm_frm_N_56005_i), + .I1(plm_frm_N_57655), + .I2(plm_frm_reg_d1_idleflag_ll_1657), + .I3(plm_frm_reg_d1_td[2]), + .LO(plm_frm_N_51440_i) + ); + defparam plm_frm_delay_two_b_reg_d2_td_24_0_iv_i_a2_1_.INIT = 8'h10; + LUT3_L plm_frm_delay_two_b_reg_d2_td_24_0_iv_i_a2_1_ ( + .I0(plm_frm_N_55867_i_0), + .I1(plm_frm_N_55996_i), + .I2(plm_frm_reg_d1_td[1]), + .LO(plm_frm_reg_d2_td_24_0_iv_i_a2[1]) + ); + defparam plm_frm_delay_two_b_N_87025_i.INIT = 16'hF1F0; + LUT4_L plm_frm_delay_two_b_N_87025_i ( + .I0(plm_frm_N_55867_i_0), + .I1(plm_frm_N_55996_i), + .I2(plm_frm_N_58272), + .I3(plm_frm_reg_d1_td[0]), + .LO(plm_frm_N_87025_i) + ); + defparam plm_frm_ciao_baby_N_85671_i_1.INIT = 16'h10F0; + LUT4 plm_frm_ciao_baby_N_85671_i_1 ( + .I0(plm_frm_N_61332), + .I1(plm_frm_N_61385), + .I2(plm_frm_reg_frm0_char_3_0_1[13]), + .I3(plm_frm_reg_d2_td[61]), + .O(plm_frm_N_85671_i_1) + ); + defparam plm_frm_ciao_baby_N_85690_i_1.INIT = 16'h10F0; + LUT4 plm_frm_ciao_baby_N_85690_i_1 ( + .I0(plm_frm_N_61332), + .I1(plm_frm_N_61385), + .I2(plm_frm_reg_frm0_char_3_i_m3_0_1[15]), + .I3(plm_frm_reg_d2_td[63]), + .O(plm_frm_N_85690_i_1) + ); + defparam plm_frm_ciao_baby_reg_frm0_char_3_0_4_1_5_.INIT = 16'h10F0; + LUT4_L plm_frm_ciao_baby_reg_frm0_char_3_0_4_1_5_ ( + .I0(plm_frm_N_61365), + .I1(plm_frm_N_61368), + .I2(plm_frm_reg_frm0_char_3_0_0_5_), + .I3(plm_frm_reg_d2_td[53]), + .LO(plm_frm_reg_frm0_char_3_0_4_1_5_) + ); + defparam plm_frm_ciao_baby_reg_frm0_char_3_0_4_5_.INIT = 16'h10F0; + LUT4 plm_frm_ciao_baby_reg_frm0_char_3_0_4_5_ ( + .I0(plm_frm_N_61366), + .I1(plm_frm_N_61367), + .I2(plm_frm_reg_frm0_char_3_0_4_1_5_), + .I3(plm_frm_reg_d2_td[21]), + .O(plm_frm_reg_frm0_char_3_0_4_5_) + ); + defparam plm_frm_ciao_baby_reg_frm0_char_3_0_4_1_7_.INIT = 16'h10F0; + LUT4_L plm_frm_ciao_baby_reg_frm0_char_3_0_4_1_7_ ( + .I0(plm_frm_N_61365), + .I1(plm_frm_N_61368), + .I2(plm_frm_reg_frm0_char_3_0_0_7_), + .I3(plm_frm_reg_d2_td[55]), + .LO(plm_frm_reg_frm0_char_3_0_4_1_7_) + ); + defparam plm_frm_ciao_baby_reg_frm0_char_3_0_4_7_.INIT = 16'h10F0; + LUT4 plm_frm_ciao_baby_reg_frm0_char_3_0_4_7_ ( + .I0(plm_frm_N_61366), + .I1(plm_frm_N_61367), + .I2(plm_frm_reg_frm0_char_3_0_4_1_7_), + .I3(plm_frm_reg_d2_td[23]), + .O(plm_frm_reg_frm0_char_3_0_4_7_) + ); + defparam plm_frm_delay_two_b_reg_d2_td_24_0_iv_i_o3_1_.INIT = 8'h28; + LUT3 plm_frm_delay_two_b_reg_d2_td_24_0_iv_i_o3_1_ ( + .I0(plm_frm_reg_d1_idleflag_lh_1656), + .I1(plm_frm_reg_d2_tframe_l_1653), + .I2(plm_frm_reg_d1_tframe_l_1652), + .O(plm_frm_N_55996_i) + ); + FDC plm_frm_reg_frm_atomic ( + .C(mgt_clk), + .D(plm_frm_N_51380_i), + .Q(plm_frm_atomic), + .CLR(plm_rst) + ); + FDC plm_frm_reg_frm0_char_7_ ( + .C(mgt_clk), + .D(plm_frm_N_85680_i), + .Q(plm_frm0_char[7]), + .CLR(plm_rst) + ); + FDC plm_frm_reg_frm0_char_6_ ( + .C(mgt_clk), + .D(plm_frm_N_85679_i), + .Q(plm_frm0_char[6]), + .CLR(plm_rst) + ); + FDC plm_frm_reg_frm0_char_5_ ( + .C(mgt_clk), + .D(plm_frm_N_85678_i), + .Q(plm_frm0_char[5]), + .CLR(plm_rst) + ); + FDC plm_frm_reg_frm0_char_4_ ( + .C(mgt_clk), + .D(plm_frm_N_51364_i), + .Q(plm_frm0_char[4]), + .CLR(plm_rst) + ); + FDC plm_frm_reg_frm0_char_3_ ( + .C(mgt_clk), + .D(plm_frm_N_51362_i), + .Q(plm_frm0_char[3]), + .CLR(plm_rst) + ); + FDC plm_frm_reg_frm0_char_2_ ( + .C(mgt_clk), + .D(plm_frm_N_14936_i), + .Q(plm_frm0_char[2]), + .CLR(plm_rst) + ); + FDC plm_frm_reg_frm0_char_1_ ( + .C(mgt_clk), + .D(plm_frm_N_85688_i), + .Q(plm_frm0_char[1]), + .CLR(plm_rst) + ); + FDC plm_frm_reg_frm0_char_0_ ( + .C(mgt_clk), + .D(plm_frm_N_85675_i), + .Q(plm_frm0_char[0]), + .CLR(plm_rst) + ); + FDC plm_frm_reg_frm0_is_k_1_ ( + .C(mgt_clk), + .D(plm_frm_N_85687_i), + .Q(plm_frm0_is_k[1]), + .CLR(plm_rst) + ); + FDC plm_frm_reg_frm0_is_k_0_ ( + .C(mgt_clk), + .D(plm_frm_N_52046_i), + .Q(plm_frm0_is_k[0]), + .CLR(plm_rst) + ); + FDC plm_frm_reg_frm1_char_2_ ( + .C(mgt_clk), + .D(plm_frm_N_58309_i), + .Q(plm_frm1_char[2]), + .CLR(plm_rst) + ); + FDC plm_frm_reg_frm1_char_1_ ( + .C(mgt_clk), + .D(plm_frm_by4_frm1_char_1_), + .Q(plm_frm1_char[1]), + .CLR(plm_rst) + ); + FDC plm_frm_reg_frm1_char_0_ ( + .C(mgt_clk), + .D(plm_frm_by4_frm1_char_0_), + .Q(plm_frm1_char[0]), + .CLR(plm_rst) + ); + FDC plm_frm_reg_frm3_is_k_1_ ( + .C(mgt_clk), + .D(plm_frm_N_87088_i), + .Q(plm_frm3_is_k[1]), + .CLR(plm_rst) + ); + FDC plm_frm_reg_frm3_is_k_0_ ( + .C(mgt_clk), + .D(plm_frm_N_58376_i), + .Q(plm_frm3_is_k[0]), + .CLR(plm_rst) + ); + FDC plm_frm_reg_frm2_is_k_1_ ( + .C(mgt_clk), + .D(plm_frm_N_86003_i), + .Q(plm_frm1_is_k[1]), + .CLR(plm_rst) + ); + FDC plm_frm_reg_frm2_is_k_0_ ( + .C(mgt_clk), + .D(plm_frm_N_55875_i), + .Q(plm_frm1_is_k[0]), + .CLR(plm_rst) + ); + FDC plm_frm_reg_frm0_char_15_ ( + .C(mgt_clk), + .D(plm_frm_N_85690_i), + .Q(plm_frm0_char[15]), + .CLR(plm_rst) + ); + FDC plm_frm_reg_frm0_char_14_ ( + .C(mgt_clk), + .D(plm_frm_N_85686_i), + .Q(plm_frm0_char[14]), + .CLR(plm_rst) + ); + FDC plm_frm_reg_frm0_char_13_ ( + .C(mgt_clk), + .D(plm_frm_N_85671_i), + .Q(plm_frm0_char[13]), + .CLR(plm_rst) + ); + FDC plm_frm_reg_frm0_char_12_ ( + .C(mgt_clk), + .D(plm_frm_N_51375_i), + .Q(plm_frm0_char[12]), + .CLR(plm_rst) + ); + FDC plm_frm_reg_frm0_char_11_ ( + .C(mgt_clk), + .D(plm_frm_N_51373_i), + .Q(plm_frm0_char[11]), + .CLR(plm_rst) + ); + FDC plm_frm_reg_frm0_char_10_ ( + .C(mgt_clk), + .D(plm_frm_N_51371_i), + .Q(plm_frm0_char[10]), + .CLR(plm_rst) + ); + FDC plm_frm_reg_frm0_char_9_ ( + .C(mgt_clk), + .D(plm_frm_N_85682_i), + .Q(plm_frm0_char[9]), + .CLR(plm_rst) + ); + FDC plm_frm_reg_frm0_char_8_ ( + .C(mgt_clk), + .D(plm_frm_N_85681_i), + .Q(plm_frm0_char[8]), + .CLR(plm_rst) + ); + FDC plm_frm_reg_frm2_char_1_ ( + .C(mgt_clk), + .D(plm_frm_by4_frm2_char_1_), + .Q(plm_frm2_char[1]), + .CLR(plm_rst) + ); + FDC plm_frm_reg_frm2_char_0_ ( + .C(mgt_clk), + .D(plm_frm_by4_frm2_char_0_), + .Q(plm_frm2_char[0]), + .CLR(plm_rst) + ); + FDC plm_frm_reg_frm1_char_15_ ( + .C(mgt_clk), + .D(plm_frm_N_51878_i), + .Q(plm_frm1_char[15]), + .CLR(plm_rst) + ); + FDC plm_frm_reg_frm1_char_14_ ( + .C(mgt_clk), + .D(plm_frm_N_51341_i), + .Q(plm_frm1_char[14]), + .CLR(plm_rst) + ); + FDC plm_frm_reg_frm1_char_13_ ( + .C(mgt_clk), + .D(plm_frm_N_51880_i), + .Q(plm_frm1_char[13]), + .CLR(plm_rst) + ); + FDC plm_frm_reg_frm1_char_12_ ( + .C(mgt_clk), + .D(plm_frm_N_86982_i), + .Q(plm_frm1_char[12]), + .CLR(plm_rst) + ); + FDC plm_frm_reg_frm1_char_11_ ( + .C(mgt_clk), + .D(plm_frm_N_86981_i), + .Q(plm_frm1_char[11]), + .CLR(plm_rst) + ); + FDC plm_frm_reg_frm1_char_10_ ( + .C(mgt_clk), + .D(plm_frm_N_86980_i), + .Q(plm_frm1_char[10]), + .CLR(plm_rst) + ); + FDC plm_frm_reg_frm1_char_9_ ( + .C(mgt_clk), + .D(plm_frm_N_51339_i), + .Q(plm_frm1_char[9]), + .CLR(plm_rst) + ); + FDC plm_frm_reg_frm1_char_8_ ( + .C(mgt_clk), + .D(plm_frm_N_51337_i), + .Q(plm_frm1_char[8]), + .CLR(plm_rst) + ); + FDC plm_frm_reg_frm1_char_7_ ( + .C(mgt_clk), + .D(plm_frm_N_86973_i), + .Q(plm_frm1_char[7]), + .CLR(plm_rst) + ); + FDC plm_frm_reg_frm1_char_6_ ( + .C(mgt_clk), + .D(plm_frm_by4_frm1_char_6_), + .Q(plm_frm1_char[6]), + .CLR(plm_rst) + ); + FDC plm_frm_reg_frm1_char_5_ ( + .C(mgt_clk), + .D(plm_frm_N_86974_i), + .Q(plm_frm1_char[5]), + .CLR(plm_rst) + ); + FDC plm_frm_reg_frm1_char_4_ ( + .C(mgt_clk), + .D(plm_frm_N_58311_i), + .Q(plm_frm1_char[4]), + .CLR(plm_rst) + ); + FDC plm_frm_reg_frm1_char_3_ ( + .C(mgt_clk), + .D(plm_frm_N_58310_i), + .Q(plm_frm1_char[3]), + .CLR(plm_rst) + ); + FDC plm_frm_reg_frm3_char_0_ ( + .C(mgt_clk), + .D(plm_frm_by4_frm3_char_0_), + .Q(plm_frm3_char[0]), + .CLR(plm_rst) + ); + FDC plm_frm_reg_frm2_char_15_ ( + .C(mgt_clk), + .D(plm_frm_N_51874_i), + .Q(plm_frm2_char[15]), + .CLR(plm_rst) + ); + FDC plm_frm_reg_frm2_char_14_ ( + .C(mgt_clk), + .D(plm_frm_N_51350_i), + .Q(plm_frm2_char[14]), + .CLR(plm_rst) + ); + FDC plm_frm_reg_frm2_char_13_ ( + .C(mgt_clk), + .D(plm_frm_N_51876_i), + .Q(plm_frm2_char[13]), + .CLR(plm_rst) + ); + FDC plm_frm_reg_frm2_char_12_ ( + .C(mgt_clk), + .D(plm_frm_N_86985_i), + .Q(plm_frm2_char[12]), + .CLR(plm_rst) + ); + FDC plm_frm_reg_frm2_char_11_ ( + .C(mgt_clk), + .D(plm_frm_N_86984_i), + .Q(plm_frm2_char[11]), + .CLR(plm_rst) + ); + FDC plm_frm_reg_frm2_char_10_ ( + .C(mgt_clk), + .D(plm_frm_N_86983_i), + .Q(plm_frm2_char[10]), + .CLR(plm_rst) + ); + FDC plm_frm_reg_frm2_char_9_ ( + .C(mgt_clk), + .D(plm_frm_N_51348_i), + .Q(plm_frm2_char[9]), + .CLR(plm_rst) + ); + FDC plm_frm_reg_frm2_char_8_ ( + .C(mgt_clk), + .D(plm_frm_N_51346_i), + .Q(plm_frm2_char[8]), + .CLR(plm_rst) + ); + FDC plm_frm_reg_frm2_char_7_ ( + .C(mgt_clk), + .D(plm_frm_N_86971_i), + .Q(plm_frm2_char[7]), + .CLR(plm_rst) + ); + FDC plm_frm_reg_frm2_char_6_ ( + .C(mgt_clk), + .D(plm_frm_by4_frm2_char_6_), + .Q(plm_frm2_char[6]), + .CLR(plm_rst) + ); + FDC plm_frm_reg_frm2_char_5_ ( + .C(mgt_clk), + .D(plm_frm_N_86972_i), + .Q(plm_frm2_char[5]), + .CLR(plm_rst) + ); + FDC plm_frm_reg_frm2_char_4_ ( + .C(mgt_clk), + .D(plm_frm_N_58314_i), + .Q(plm_frm2_char[4]), + .CLR(plm_rst) + ); + FDC plm_frm_reg_frm2_char_3_ ( + .C(mgt_clk), + .D(plm_frm_N_58313_i), + .Q(plm_frm2_char[3]), + .CLR(plm_rst) + ); + FDC plm_frm_reg_frm2_char_2_ ( + .C(mgt_clk), + .D(plm_frm_N_58312_i), + .Q(plm_frm2_char[2]), + .CLR(plm_rst) + ); + FDC plm_frm_reg_frm3_char_15_ ( + .C(mgt_clk), + .D(plm_frm_N_51870_i), + .Q(plm_frm3_char[15]), + .CLR(plm_rst) + ); + FDC plm_frm_reg_frm3_char_14_ ( + .C(mgt_clk), + .D(plm_frm_N_51359_i), + .Q(plm_frm3_char[14]), + .CLR(plm_rst) + ); + FDC plm_frm_reg_frm3_char_13_ ( + .C(mgt_clk), + .D(plm_frm_N_51872_i), + .Q(plm_frm3_char[13]), + .CLR(plm_rst) + ); + FDC plm_frm_reg_frm3_char_12_ ( + .C(mgt_clk), + .D(plm_frm_N_86988_i), + .Q(plm_frm3_char[12]), + .CLR(plm_rst) + ); + FDC plm_frm_reg_frm3_char_11_ ( + .C(mgt_clk), + .D(plm_frm_N_86987_i), + .Q(plm_frm3_char[11]), + .CLR(plm_rst) + ); + FDC plm_frm_reg_frm3_char_10_ ( + .C(mgt_clk), + .D(plm_frm_N_86986_i), + .Q(plm_frm3_char[10]), + .CLR(plm_rst) + ); + FDC plm_frm_reg_frm3_char_9_ ( + .C(mgt_clk), + .D(plm_frm_N_51357_i), + .Q(plm_frm3_char[9]), + .CLR(plm_rst) + ); + FDC plm_frm_reg_frm3_char_8_ ( + .C(mgt_clk), + .D(plm_frm_N_51355_i), + .Q(plm_frm3_char[8]), + .CLR(plm_rst) + ); + FDC plm_frm_reg_frm3_char_7_ ( + .C(mgt_clk), + .D(plm_frm_N_86969_i), + .Q(plm_frm3_char[7]), + .CLR(plm_rst) + ); + FDC plm_frm_reg_frm3_char_6_ ( + .C(mgt_clk), + .D(plm_frm_by4_frm3_char_6_), + .Q(plm_frm3_char[6]), + .CLR(plm_rst) + ); + FDC plm_frm_reg_frm3_char_5_ ( + .C(mgt_clk), + .D(plm_frm_N_86970_i), + .Q(plm_frm3_char[5]), + .CLR(plm_rst) + ); + FDC plm_frm_reg_frm3_char_4_ ( + .C(mgt_clk), + .D(plm_frm_N_58317_i), + .Q(plm_frm3_char[4]), + .CLR(plm_rst) + ); + FDC plm_frm_reg_frm3_char_3_ ( + .C(mgt_clk), + .D(plm_frm_N_58316_i), + .Q(plm_frm3_char[3]), + .CLR(plm_rst) + ); + FDC plm_frm_reg_frm3_char_2_ ( + .C(mgt_clk), + .D(plm_frm_N_58315_i), + .Q(plm_frm3_char[2]), + .CLR(plm_rst) + ); + FDC plm_frm_reg_frm3_char_1_ ( + .C(mgt_clk), + .D(plm_frm_by4_frm3_char_1_), + .Q(plm_frm3_char[1]), + .CLR(plm_rst) + ); + FDCE plm_frm_reg_d0_tctrl_h ( + .CE(plm_phy_cke_1_711), + .C(mgt_clk), + .D(phy_tctrl_h), + .Q(plm_frm_reg_d0_tctrl_h_1644), + .CLR(plm_rst) + ); + FDCE plm_frm_reg_d0_tctrl_l ( + .CE(plm_phy_cke_1_711), + .C(mgt_clk), + .D(phy_tctrl_l), + .Q(plm_frm_reg_d0_tctrl_l_1646), + .CLR(plm_rst) + ); + FDCE plm_frm_reg_d0_tframe_h ( + .CE(plm_phy_cke_2_710), + .C(mgt_clk), + .D(phy_tframe_h), + .Q(plm_frm_reg_d0_tframe_h_1648), + .CLR(plm_rst) + ); + FDCE plm_frm_reg_d0_tframe_l ( + .CE(plm_phy_cke_2_710), + .C(mgt_clk), + .D(phy_tframe_l), + .Q(plm_frm_reg_d0_tframe_l_1649), + .CLR(plm_rst) + ); + FDCE plm_frm_reg_d0_td_63_ ( + .CE(plm_phy_cke_2_710), + .C(mgt_clk), + .D(phy_td[63]), + .Q(plm_frm_reg_d0_td[63]), + .CLR(plm_rst) + ); + FDCE plm_frm_reg_d0_td_62_ ( + .CE(plm_phy_cke_2_710), + .C(mgt_clk), + .D(phy_td[62]), + .Q(plm_frm_reg_d0_td[62]), + .CLR(plm_rst) + ); + FDCE plm_frm_reg_d0_td_61_ ( + .CE(plm_phy_cke_2_710), + .C(mgt_clk), + .D(phy_td[61]), + .Q(plm_frm_reg_d0_td[61]), + .CLR(plm_rst) + ); + FDCE plm_frm_reg_d0_td_60_ ( + .CE(plm_phy_cke_2_710), + .C(mgt_clk), + .D(phy_td[60]), + .Q(plm_frm_reg_d0_td[60]), + .CLR(plm_rst) + ); + FDCE plm_frm_reg_d0_td_59_ ( + .CE(plm_phy_cke_2_710), + .C(mgt_clk), + .D(phy_td[59]), + .Q(plm_frm_reg_d0_td[59]), + .CLR(plm_rst) + ); + FDCE plm_frm_reg_d0_td_58_ ( + .CE(plm_phy_cke_2_710), + .C(mgt_clk), + .D(phy_td[58]), + .Q(plm_frm_reg_d0_td[58]), + .CLR(plm_rst) + ); + FDCE plm_frm_reg_d0_td_57_ ( + .CE(plm_phy_cke_2_710), + .C(mgt_clk), + .D(phy_td[57]), + .Q(plm_frm_reg_d0_td[57]), + .CLR(plm_rst) + ); + FDCE plm_frm_reg_d0_td_56_ ( + .CE(plm_phy_cke_2_710), + .C(mgt_clk), + .D(phy_td[56]), + .Q(plm_frm_reg_d0_td[56]), + .CLR(plm_rst) + ); + FDCE plm_frm_reg_d0_td_55_ ( + .CE(plm_phy_cke_2_710), + .C(mgt_clk), + .D(phy_td[55]), + .Q(plm_frm_reg_d0_td[55]), + .CLR(plm_rst) + ); + FDCE plm_frm_reg_d0_td_54_ ( + .CE(plm_phy_cke_2_710), + .C(mgt_clk), + .D(phy_td[54]), + .Q(plm_frm_reg_d0_td[54]), + .CLR(plm_rst) + ); + FDCE plm_frm_reg_d0_td_53_ ( + .CE(plm_phy_cke_2_710), + .C(mgt_clk), + .D(phy_td[53]), + .Q(plm_frm_reg_d0_td[53]), + .CLR(plm_rst) + ); + FDCE plm_frm_reg_d0_td_52_ ( + .CE(plm_phy_cke_2_710), + .C(mgt_clk), + .D(phy_td[52]), + .Q(plm_frm_reg_d0_td[52]), + .CLR(plm_rst) + ); + FDCE plm_frm_reg_d0_td_51_ ( + .CE(plm_phy_cke_2_710), + .C(mgt_clk), + .D(phy_td[51]), + .Q(plm_frm_reg_d0_td[51]), + .CLR(plm_rst) + ); + FDCE plm_frm_reg_d0_td_50_ ( + .CE(plm_phy_cke_2_710), + .C(mgt_clk), + .D(phy_td[50]), + .Q(plm_frm_reg_d0_td[50]), + .CLR(plm_rst) + ); + FDCE plm_frm_reg_d0_td_49_ ( + .CE(plm_phy_cke_2_710), + .C(mgt_clk), + .D(phy_td[49]), + .Q(plm_frm_reg_d0_td[49]), + .CLR(plm_rst) + ); + FDCE plm_frm_reg_d0_td_48_ ( + .CE(plm_phy_cke_1_711), + .C(mgt_clk), + .D(phy_td[48]), + .Q(plm_frm_reg_d0_td[48]), + .CLR(plm_rst) + ); + FDCE plm_frm_reg_d0_td_47_ ( + .CE(plm_phy_cke_1_711), + .C(mgt_clk), + .D(phy_td[47]), + .Q(plm_frm_reg_d0_td[47]), + .CLR(plm_rst) + ); + FDCE plm_frm_reg_d0_td_46_ ( + .CE(plm_phy_cke_1_711), + .C(mgt_clk), + .D(phy_td[46]), + .Q(plm_frm_reg_d0_td[46]), + .CLR(plm_rst) + ); + FDCE plm_frm_reg_d0_td_45_ ( + .CE(plm_phy_cke_1_711), + .C(mgt_clk), + .D(phy_td[45]), + .Q(plm_frm_reg_d0_td[45]), + .CLR(plm_rst) + ); + FDCE plm_frm_reg_d0_td_44_ ( + .CE(plm_phy_cke_1_711), + .C(mgt_clk), + .D(phy_td[44]), + .Q(plm_frm_reg_d0_td[44]), + .CLR(plm_rst) + ); + FDCE plm_frm_reg_d0_td_43_ ( + .CE(plm_phy_cke_1_711), + .C(mgt_clk), + .D(phy_td[43]), + .Q(plm_frm_reg_d0_td[43]), + .CLR(plm_rst) + ); + FDCE plm_frm_reg_d0_td_42_ ( + .CE(plm_phy_cke_1_711), + .C(mgt_clk), + .D(phy_td[42]), + .Q(plm_frm_reg_d0_td[42]), + .CLR(plm_rst) + ); + FDCE plm_frm_reg_d0_td_41_ ( + .CE(plm_phy_cke_1_711), + .C(mgt_clk), + .D(phy_td[41]), + .Q(plm_frm_reg_d0_td[41]), + .CLR(plm_rst) + ); + FDCE plm_frm_reg_d0_td_40_ ( + .CE(plm_phy_cke_1_711), + .C(mgt_clk), + .D(phy_td[40]), + .Q(plm_frm_reg_d0_td[40]), + .CLR(plm_rst) + ); + FDCE plm_frm_reg_d0_td_39_ ( + .CE(plm_phy_cke_1_711), + .C(mgt_clk), + .D(phy_td[39]), + .Q(plm_frm_reg_d0_td[39]), + .CLR(plm_rst) + ); + FDCE plm_frm_reg_d0_td_38_ ( + .CE(plm_phy_cke_1_711), + .C(mgt_clk), + .D(phy_td[38]), + .Q(plm_frm_reg_d0_td[38]), + .CLR(plm_rst) + ); + FDCE plm_frm_reg_d0_td_37_ ( + .CE(plm_phy_cke_1_711), + .C(mgt_clk), + .D(phy_td[37]), + .Q(plm_frm_reg_d0_td[37]), + .CLR(plm_rst) + ); + FDCE plm_frm_reg_d0_td_36_ ( + .CE(plm_phy_cke_1_711), + .C(mgt_clk), + .D(phy_td[36]), + .Q(plm_frm_reg_d0_td[36]), + .CLR(plm_rst) + ); + FDCE plm_frm_reg_d0_td_35_ ( + .CE(plm_phy_cke_1_711), + .C(mgt_clk), + .D(phy_td[35]), + .Q(plm_frm_reg_d0_td[35]), + .CLR(plm_rst) + ); + FDCE plm_frm_reg_d0_td_34_ ( + .CE(plm_phy_cke_1_711), + .C(mgt_clk), + .D(phy_td[34]), + .Q(plm_frm_reg_d0_td[34]), + .CLR(plm_rst) + ); + FDCE plm_frm_reg_d0_td_33_ ( + .CE(plm_phy_cke_1_711), + .C(mgt_clk), + .D(phy_td[33]), + .Q(plm_frm_reg_d0_td[33]), + .CLR(plm_rst) + ); + FDCE plm_frm_reg_d0_td_32_ ( + .CE(plm_phy_cke_1_711), + .C(mgt_clk), + .D(phy_td[32]), + .Q(plm_frm_reg_d0_td[32]), + .CLR(plm_rst) + ); + FDCE plm_frm_reg_d0_td_31_ ( + .CE(plm_phy_cke_1_711), + .C(mgt_clk), + .D(phy_td[31]), + .Q(plm_frm_reg_d0_td[31]), + .CLR(plm_rst) + ); + FDCE plm_frm_reg_d0_td_30_ ( + .CE(plm_phy_cke_1_711), + .C(mgt_clk), + .D(phy_td[30]), + .Q(plm_frm_reg_d0_td[30]), + .CLR(plm_rst) + ); + FDCE plm_frm_reg_d0_td_29_ ( + .CE(plm_phy_cke_1_711), + .C(mgt_clk), + .D(phy_td[29]), + .Q(plm_frm_reg_d0_td[29]), + .CLR(plm_rst) + ); + FDCE plm_frm_reg_d0_td_28_ ( + .CE(plm_phy_cke_1_711), + .C(mgt_clk), + .D(phy_td[28]), + .Q(plm_frm_reg_d0_td[28]), + .CLR(plm_rst) + ); + FDCE plm_frm_reg_d0_td_27_ ( + .CE(plm_phy_cke_1_711), + .C(mgt_clk), + .D(phy_td[27]), + .Q(plm_frm_reg_d0_td[27]), + .CLR(plm_rst) + ); + FDCE plm_frm_reg_d0_td_26_ ( + .CE(plm_phy_cke_1_711), + .C(mgt_clk), + .D(phy_td[26]), + .Q(plm_frm_reg_d0_td[26]), + .CLR(plm_rst) + ); + FDCE plm_frm_reg_d0_td_25_ ( + .CE(plm_phy_cke_1_711), + .C(mgt_clk), + .D(phy_td[25]), + .Q(plm_frm_reg_d0_td[25]), + .CLR(plm_rst) + ); + FDCE plm_frm_reg_d0_td_24_ ( + .CE(plm_phy_cke_1_711), + .C(mgt_clk), + .D(phy_td[24]), + .Q(plm_frm_reg_d0_td[24]), + .CLR(plm_rst) + ); + FDCE plm_frm_reg_d0_td_23_ ( + .CE(plm_phy_cke_1_711), + .C(mgt_clk), + .D(phy_td[23]), + .Q(plm_frm_reg_d0_td[23]), + .CLR(plm_rst) + ); + FDCE plm_frm_reg_d0_td_22_ ( + .CE(plm_phy_cke_1_711), + .C(mgt_clk), + .D(phy_td[22]), + .Q(plm_frm_reg_d0_td[22]), + .CLR(plm_rst) + ); + FDCE plm_frm_reg_d0_td_21_ ( + .CE(plm_phy_cke_1_711), + .C(mgt_clk), + .D(phy_td[21]), + .Q(plm_frm_reg_d0_td[21]), + .CLR(plm_rst) + ); + FDCE plm_frm_reg_d0_td_20_ ( + .CE(plm_phy_cke_1_711), + .C(mgt_clk), + .D(phy_td[20]), + .Q(plm_frm_reg_d0_td[20]), + .CLR(plm_rst) + ); + FDCE plm_frm_reg_d0_td_19_ ( + .CE(plm_phy_cke_1_711), + .C(mgt_clk), + .D(phy_td[19]), + .Q(plm_frm_reg_d0_td[19]), + .CLR(plm_rst) + ); + FDCE plm_frm_reg_d0_td_18_ ( + .CE(plm_phy_cke_1_711), + .C(mgt_clk), + .D(phy_td[18]), + .Q(plm_frm_reg_d0_td[18]), + .CLR(plm_rst) + ); + FDCE plm_frm_reg_d0_td_17_ ( + .CE(plm_phy_cke_1_711), + .C(mgt_clk), + .D(phy_td[17]), + .Q(plm_frm_reg_d0_td[17]), + .CLR(plm_rst) + ); + FDCE plm_frm_reg_d0_td_16_ ( + .CE(plm_phy_cke_1_711), + .C(mgt_clk), + .D(phy_td[16]), + .Q(plm_frm_reg_d0_td[16]), + .CLR(plm_rst) + ); + FDCE plm_frm_reg_d0_td_15_ ( + .CE(plm_phy_cke_1_711), + .C(mgt_clk), + .D(phy_td[15]), + .Q(plm_frm_reg_d0_td[15]), + .CLR(plm_rst) + ); + FDCE plm_frm_reg_d0_td_14_ ( + .CE(plm_phy_cke_1_711), + .C(mgt_clk), + .D(phy_td[14]), + .Q(plm_frm_reg_d0_td[14]), + .CLR(plm_rst) + ); + FDCE plm_frm_reg_d0_td_13_ ( + .CE(plm_phy_cke_1_711), + .C(mgt_clk), + .D(phy_td[13]), + .Q(plm_frm_reg_d0_td[13]), + .CLR(plm_rst) + ); + FDCE plm_frm_reg_d0_td_12_ ( + .CE(plm_phy_cke_1_711), + .C(mgt_clk), + .D(phy_td[12]), + .Q(plm_frm_reg_d0_td[12]), + .CLR(plm_rst) + ); + FDCE plm_frm_reg_d0_td_11_ ( + .CE(plm_phy_cke_1_711), + .C(mgt_clk), + .D(phy_td[11]), + .Q(plm_frm_reg_d0_td[11]), + .CLR(plm_rst) + ); + FDCE plm_frm_reg_d0_td_10_ ( + .CE(plm_phy_cke_1_711), + .C(mgt_clk), + .D(phy_td[10]), + .Q(plm_frm_reg_d0_td[10]), + .CLR(plm_rst) + ); + FDCE plm_frm_reg_d0_td_9_ ( + .CE(plm_phy_cke_1_711), + .C(mgt_clk), + .D(phy_td[9]), + .Q(plm_frm_reg_d0_td[9]), + .CLR(plm_rst) + ); + FDCE plm_frm_reg_d0_td_8_ ( + .CE(plm_phy_cke_1_711), + .C(mgt_clk), + .D(phy_td[8]), + .Q(plm_frm_reg_d0_td[8]), + .CLR(plm_rst) + ); + FDCE plm_frm_reg_d0_td_7_ ( + .CE(plm_phy_cke_1_711), + .C(mgt_clk), + .D(phy_td[7]), + .Q(plm_frm_reg_d0_td[7]), + .CLR(plm_rst) + ); + FDCE plm_frm_reg_d0_td_6_ ( + .CE(plm_phy_cke_1_711), + .C(mgt_clk), + .D(phy_td[6]), + .Q(plm_frm_reg_d0_td[6]), + .CLR(plm_rst) + ); + FDCE plm_frm_reg_d0_td_5_ ( + .CE(plm_phy_cke_1_711), + .C(mgt_clk), + .D(phy_td[5]), + .Q(plm_frm_reg_d0_td[5]), + .CLR(plm_rst) + ); + FDCE plm_frm_reg_d0_td_4_ ( + .CE(plm_phy_cke_1_711), + .C(mgt_clk), + .D(phy_td[4]), + .Q(plm_frm_reg_d0_td[4]), + .CLR(plm_rst) + ); + FDCE plm_frm_reg_d0_td_3_ ( + .CE(plm_phy_cke_1_711), + .C(mgt_clk), + .D(phy_td[3]), + .Q(plm_frm_reg_d0_td[3]), + .CLR(plm_rst) + ); + FDCE plm_frm_reg_d0_td_2_ ( + .CE(plm_phy_cke_1_711), + .C(mgt_clk), + .D(phy_td[2]), + .Q(plm_frm_reg_d0_td[2]), + .CLR(plm_rst) + ); + FDCE plm_frm_reg_d0_td_1_ ( + .CE(plm_phy_cke_1_711), + .C(mgt_clk), + .D(phy_td[1]), + .Q(plm_frm_reg_d0_td[1]), + .CLR(plm_rst) + ); + FDCE plm_frm_reg_d0_td_0_ ( + .CE(plm_phy_cke_1_711), + .C(mgt_clk), + .D(phy_td[0]), + .Q(plm_frm_reg_d0_td[0]), + .CLR(plm_rst) + ); + FDCE plm_frm_reg_d1_tctrl_h ( + .CE(plm_phy_cke_2_710), + .C(mgt_clk), + .D(plm_frm_reg_d0_tctrl_h_1644), + .Q(plm_frm_reg_d1_tctrl_h_1645), + .CLR(plm_rst) + ); + FDCE plm_frm_reg_d1_tctrl_l ( + .CE(plm_phy_cke_2_710), + .C(mgt_clk), + .D(plm_frm_reg_d0_tctrl_l_1646), + .Q(plm_frm_reg_d1_tctrl_l_1647), + .CLR(plm_rst) + ); + FDCE plm_frm_reg_d1_tframe_h ( + .CE(plm_phy_cke_3_709), + .C(mgt_clk), + .D(plm_frm_reg_d0_tframe_h_1648), + .Q(plm_frm_reg_d1_tframe_h_1650), + .CLR(plm_rst) + ); + FDCE plm_frm_reg_d1_tframe_l ( + .CE(plm_phy_cke_3_709), + .C(mgt_clk), + .D(plm_frm_reg_d0_tframe_l_1649), + .Q(plm_frm_reg_d1_tframe_l_1652), + .CLR(plm_rst) + ); + FDCE plm_frm_reg_d1_td_63_ ( + .CE(plm_phy_cke_3_709), + .C(mgt_clk), + .D(plm_frm_reg_d0_td[63]), + .Q(plm_frm_reg_d1_td[63]), + .CLR(plm_rst) + ); + FDCE plm_frm_reg_d1_td_62_ ( + .CE(plm_phy_cke_3_709), + .C(mgt_clk), + .D(plm_frm_reg_d0_td[62]), + .Q(plm_frm_reg_d1_td[62]), + .CLR(plm_rst) + ); + FDCE plm_frm_reg_d1_td_61_ ( + .CE(plm_phy_cke_3_709), + .C(mgt_clk), + .D(plm_frm_reg_d0_td[61]), + .Q(plm_frm_reg_d1_td[61]), + .CLR(plm_rst) + ); + FDCE plm_frm_reg_d1_td_60_ ( + .CE(plm_phy_cke_3_709), + .C(mgt_clk), + .D(plm_frm_reg_d0_td[60]), + .Q(plm_frm_reg_d1_td[60]), + .CLR(plm_rst) + ); + FDCE plm_frm_reg_d1_td_59_ ( + .CE(plm_phy_cke_3_709), + .C(mgt_clk), + .D(plm_frm_reg_d0_td[59]), + .Q(plm_frm_reg_d1_td[59]), + .CLR(plm_rst) + ); + FDCE plm_frm_reg_d1_td_58_ ( + .CE(plm_phy_cke_3_709), + .C(mgt_clk), + .D(plm_frm_reg_d0_td[58]), + .Q(plm_frm_reg_d1_td[58]), + .CLR(plm_rst) + ); + FDCE plm_frm_reg_d1_td_57_ ( + .CE(plm_phy_cke_2_710), + .C(mgt_clk), + .D(plm_frm_reg_d0_td[57]), + .Q(plm_frm_reg_d1_td[57]), + .CLR(plm_rst) + ); + FDCE plm_frm_reg_d1_td_56_ ( + .CE(plm_phy_cke_2_710), + .C(mgt_clk), + .D(plm_frm_reg_d0_td[56]), + .Q(plm_frm_reg_d1_td[56]), + .CLR(plm_rst) + ); + FDCE plm_frm_reg_d1_td_55_ ( + .CE(plm_phy_cke_2_710), + .C(mgt_clk), + .D(plm_frm_reg_d0_td[55]), + .Q(plm_frm_reg_d1_td[55]), + .CLR(plm_rst) + ); + FDCE plm_frm_reg_d1_td_54_ ( + .CE(plm_phy_cke_2_710), + .C(mgt_clk), + .D(plm_frm_reg_d0_td[54]), + .Q(plm_frm_reg_d1_td[54]), + .CLR(plm_rst) + ); + FDCE plm_frm_reg_d1_td_53_ ( + .CE(plm_phy_cke_2_710), + .C(mgt_clk), + .D(plm_frm_reg_d0_td[53]), + .Q(plm_frm_reg_d1_td[53]), + .CLR(plm_rst) + ); + FDCE plm_frm_reg_d1_td_52_ ( + .CE(plm_phy_cke_2_710), + .C(mgt_clk), + .D(plm_frm_reg_d0_td[52]), + .Q(plm_frm_reg_d1_td[52]), + .CLR(plm_rst) + ); + FDCE plm_frm_reg_d1_td_51_ ( + .CE(plm_phy_cke_2_710), + .C(mgt_clk), + .D(plm_frm_reg_d0_td[51]), + .Q(plm_frm_reg_d1_td[51]), + .CLR(plm_rst) + ); + FDCE plm_frm_reg_d1_td_50_ ( + .CE(plm_phy_cke_2_710), + .C(mgt_clk), + .D(plm_frm_reg_d0_td[50]), + .Q(plm_frm_reg_d1_td[50]), + .CLR(plm_rst) + ); + FDCE plm_frm_reg_d1_td_49_ ( + .CE(plm_phy_cke_2_710), + .C(mgt_clk), + .D(plm_frm_reg_d0_td[49]), + .Q(plm_frm_reg_d1_td[49]), + .CLR(plm_rst) + ); + FDCE plm_frm_reg_d1_td_48_ ( + .CE(plm_phy_cke_2_710), + .C(mgt_clk), + .D(plm_frm_reg_d0_td[48]), + .Q(plm_frm_reg_d1_td[48]), + .CLR(plm_rst) + ); + FDCE plm_frm_reg_d1_td_47_ ( + .CE(plm_phy_cke_2_710), + .C(mgt_clk), + .D(plm_frm_reg_d0_td[47]), + .Q(plm_frm_reg_d1_td[47]), + .CLR(plm_rst) + ); + FDCE plm_frm_reg_d1_td_46_ ( + .CE(plm_phy_cke_2_710), + .C(mgt_clk), + .D(plm_frm_reg_d0_td[46]), + .Q(plm_frm_reg_d1_td[46]), + .CLR(plm_rst) + ); + FDCE plm_frm_reg_d1_td_45_ ( + .CE(plm_phy_cke_2_710), + .C(mgt_clk), + .D(plm_frm_reg_d0_td[45]), + .Q(plm_frm_reg_d1_td[45]), + .CLR(plm_rst) + ); + FDCE plm_frm_reg_d1_td_44_ ( + .CE(plm_phy_cke_2_710), + .C(mgt_clk), + .D(plm_frm_reg_d0_td[44]), + .Q(plm_frm_reg_d1_td[44]), + .CLR(plm_rst) + ); + FDCE plm_frm_reg_d1_td_43_ ( + .CE(plm_phy_cke_2_710), + .C(mgt_clk), + .D(plm_frm_reg_d0_td[43]), + .Q(plm_frm_reg_d1_td[43]), + .CLR(plm_rst) + ); + FDCE plm_frm_reg_d1_td_42_ ( + .CE(plm_phy_cke_2_710), + .C(mgt_clk), + .D(plm_frm_reg_d0_td[42]), + .Q(plm_frm_reg_d1_td[42]), + .CLR(plm_rst) + ); + FDCE plm_frm_reg_d1_td_41_ ( + .CE(plm_phy_cke_2_710), + .C(mgt_clk), + .D(plm_frm_reg_d0_td[41]), + .Q(plm_frm_reg_d1_td[41]), + .CLR(plm_rst) + ); + FDCE plm_frm_reg_d1_td_40_ ( + .CE(plm_phy_cke_2_710), + .C(mgt_clk), + .D(plm_frm_reg_d0_td[40]), + .Q(plm_frm_reg_d1_td[40]), + .CLR(plm_rst) + ); + FDCE plm_frm_reg_d1_td_39_ ( + .CE(plm_phy_cke_2_710), + .C(mgt_clk), + .D(plm_frm_reg_d0_td[39]), + .Q(plm_frm_reg_d1_td[39]), + .CLR(plm_rst) + ); + FDCE plm_frm_reg_d1_td_38_ ( + .CE(plm_phy_cke_2_710), + .C(mgt_clk), + .D(plm_frm_reg_d0_td[38]), + .Q(plm_frm_reg_d1_td[38]), + .CLR(plm_rst) + ); + FDCE plm_frm_reg_d1_td_37_ ( + .CE(plm_phy_cke_2_710), + .C(mgt_clk), + .D(plm_frm_reg_d0_td[37]), + .Q(plm_frm_reg_d1_td[37]), + .CLR(plm_rst) + ); + FDCE plm_frm_reg_d1_td_36_ ( + .CE(plm_phy_cke_2_710), + .C(mgt_clk), + .D(plm_frm_reg_d0_td[36]), + .Q(plm_frm_reg_d1_td[36]), + .CLR(plm_rst) + ); + FDCE plm_frm_reg_d1_td_35_ ( + .CE(plm_phy_cke_2_710), + .C(mgt_clk), + .D(plm_frm_reg_d0_td[35]), + .Q(plm_frm_reg_d1_td[35]), + .CLR(plm_rst) + ); + FDCE plm_frm_reg_d1_td_34_ ( + .CE(plm_phy_cke_2_710), + .C(mgt_clk), + .D(plm_frm_reg_d0_td[34]), + .Q(plm_frm_reg_d1_td[34]), + .CLR(plm_rst) + ); + FDCE plm_frm_reg_d1_td_33_ ( + .CE(plm_phy_cke_2_710), + .C(mgt_clk), + .D(plm_frm_reg_d0_td[33]), + .Q(plm_frm_reg_d1_td[33]), + .CLR(plm_rst) + ); + FDCE plm_frm_reg_d1_td_32_ ( + .CE(plm_phy_cke_2_710), + .C(mgt_clk), + .D(plm_frm_reg_d0_td[32]), + .Q(plm_frm_reg_d1_td[32]), + .CLR(plm_rst) + ); + FDCE plm_frm_reg_d1_td_31_ ( + .CE(plm_phy_cke_2_710), + .C(mgt_clk), + .D(plm_frm_reg_d0_td[31]), + .Q(plm_frm_reg_d1_td[31]), + .CLR(plm_rst) + ); + FDCE plm_frm_reg_d1_td_30_ ( + .CE(plm_phy_cke_2_710), + .C(mgt_clk), + .D(plm_frm_reg_d0_td[30]), + .Q(plm_frm_reg_d1_td[30]), + .CLR(plm_rst) + ); + FDCE plm_frm_reg_d1_td_29_ ( + .CE(plm_phy_cke_2_710), + .C(mgt_clk), + .D(plm_frm_reg_d0_td[29]), + .Q(plm_frm_reg_d1_td[29]), + .CLR(plm_rst) + ); + FDCE plm_frm_reg_d1_td_28_ ( + .CE(plm_phy_cke_2_710), + .C(mgt_clk), + .D(plm_frm_reg_d0_td[28]), + .Q(plm_frm_reg_d1_td[28]), + .CLR(plm_rst) + ); + FDCE plm_frm_reg_d1_td_27_ ( + .CE(plm_phy_cke_2_710), + .C(mgt_clk), + .D(plm_frm_reg_d0_td[27]), + .Q(plm_frm_reg_d1_td[27]), + .CLR(plm_rst) + ); + FDCE plm_frm_reg_d1_td_26_ ( + .CE(plm_phy_cke_2_710), + .C(mgt_clk), + .D(plm_frm_reg_d0_td[26]), + .Q(plm_frm_reg_d1_td[26]), + .CLR(plm_rst) + ); + FDCE plm_frm_reg_d1_td_25_ ( + .CE(plm_phy_cke_2_710), + .C(mgt_clk), + .D(plm_frm_reg_d0_td[25]), + .Q(plm_frm_reg_d1_td[25]), + .CLR(plm_rst) + ); + FDCE plm_frm_reg_d1_td_24_ ( + .CE(plm_phy_cke_2_710), + .C(mgt_clk), + .D(plm_frm_reg_d0_td[24]), + .Q(plm_frm_reg_d1_td[24]), + .CLR(plm_rst) + ); + FDCE plm_frm_reg_d1_td_23_ ( + .CE(plm_phy_cke_2_710), + .C(mgt_clk), + .D(plm_frm_reg_d0_td[23]), + .Q(plm_frm_reg_d1_td[23]), + .CLR(plm_rst) + ); + FDCE plm_frm_reg_d1_td_22_ ( + .CE(plm_phy_cke_2_710), + .C(mgt_clk), + .D(plm_frm_reg_d0_td[22]), + .Q(plm_frm_reg_d1_td[22]), + .CLR(plm_rst) + ); + FDCE plm_frm_reg_d1_td_21_ ( + .CE(plm_phy_cke_2_710), + .C(mgt_clk), + .D(plm_frm_reg_d0_td[21]), + .Q(plm_frm_reg_d1_td[21]), + .CLR(plm_rst) + ); + FDCE plm_frm_reg_d1_td_20_ ( + .CE(plm_phy_cke_2_710), + .C(mgt_clk), + .D(plm_frm_reg_d0_td[20]), + .Q(plm_frm_reg_d1_td[20]), + .CLR(plm_rst) + ); + FDCE plm_frm_reg_d1_td_19_ ( + .CE(plm_phy_cke_2_710), + .C(mgt_clk), + .D(plm_frm_reg_d0_td[19]), + .Q(plm_frm_reg_d1_td[19]), + .CLR(plm_rst) + ); + FDCE plm_frm_reg_d1_td_18_ ( + .CE(plm_phy_cke_2_710), + .C(mgt_clk), + .D(plm_frm_reg_d0_td[18]), + .Q(plm_frm_reg_d1_td[18]), + .CLR(plm_rst) + ); + FDCE plm_frm_reg_d1_td_17_ ( + .CE(plm_phy_cke_2_710), + .C(mgt_clk), + .D(plm_frm_reg_d0_td[17]), + .Q(plm_frm_reg_d1_td[17]), + .CLR(plm_rst) + ); + FDCE plm_frm_reg_d1_td_16_ ( + .CE(plm_phy_cke_2_710), + .C(mgt_clk), + .D(plm_frm_reg_d0_td[16]), + .Q(plm_frm_reg_d1_td[16]), + .CLR(plm_rst) + ); + FDCE plm_frm_reg_d1_td_15_ ( + .CE(plm_phy_cke_2_710), + .C(mgt_clk), + .D(plm_frm_reg_d0_td[15]), + .Q(plm_frm_reg_d1_td[15]), + .CLR(plm_rst) + ); + FDCE plm_frm_reg_d1_td_14_ ( + .CE(plm_phy_cke_2_710), + .C(mgt_clk), + .D(plm_frm_reg_d0_td[14]), + .Q(plm_frm_reg_d1_td[14]), + .CLR(plm_rst) + ); + FDCE plm_frm_reg_d1_td_13_ ( + .CE(plm_phy_cke_2_710), + .C(mgt_clk), + .D(plm_frm_reg_d0_td[13]), + .Q(plm_frm_reg_d1_td[13]), + .CLR(plm_rst) + ); + FDCE plm_frm_reg_d1_td_12_ ( + .CE(plm_phy_cke_2_710), + .C(mgt_clk), + .D(plm_frm_reg_d0_td[12]), + .Q(plm_frm_reg_d1_td[12]), + .CLR(plm_rst) + ); + FDCE plm_frm_reg_d1_td_11_ ( + .CE(plm_phy_cke_2_710), + .C(mgt_clk), + .D(plm_frm_reg_d0_td[11]), + .Q(plm_frm_reg_d1_td[11]), + .CLR(plm_rst) + ); + FDCE plm_frm_reg_d1_td_10_ ( + .CE(plm_phy_cke_2_710), + .C(mgt_clk), + .D(plm_frm_reg_d0_td[10]), + .Q(plm_frm_reg_d1_td[10]), + .CLR(plm_rst) + ); + FDCE plm_frm_reg_d1_td_9_ ( + .CE(plm_phy_cke_2_710), + .C(mgt_clk), + .D(plm_frm_reg_d0_td[9]), + .Q(plm_frm_reg_d1_td[9]), + .CLR(plm_rst) + ); + FDCE plm_frm_reg_d1_td_8_ ( + .CE(plm_phy_cke_2_710), + .C(mgt_clk), + .D(plm_frm_reg_d0_td[8]), + .Q(plm_frm_reg_d1_td[8]), + .CLR(plm_rst) + ); + FDCE plm_frm_reg_d1_td_7_ ( + .CE(plm_phy_cke_2_710), + .C(mgt_clk), + .D(plm_frm_reg_d0_td[7]), + .Q(plm_frm_reg_d1_td[7]), + .CLR(plm_rst) + ); + FDCE plm_frm_reg_d1_td_6_ ( + .CE(plm_phy_cke_2_710), + .C(mgt_clk), + .D(plm_frm_reg_d0_td[6]), + .Q(plm_frm_reg_d1_td[6]), + .CLR(plm_rst) + ); + FDCE plm_frm_reg_d1_td_5_ ( + .CE(plm_phy_cke_2_710), + .C(mgt_clk), + .D(plm_frm_reg_d0_td[5]), + .Q(plm_frm_reg_d1_td[5]), + .CLR(plm_rst) + ); + FDCE plm_frm_reg_d1_td_4_ ( + .CE(plm_phy_cke_2_710), + .C(mgt_clk), + .D(plm_frm_reg_d0_td[4]), + .Q(plm_frm_reg_d1_td[4]), + .CLR(plm_rst) + ); + FDCE plm_frm_reg_d1_td_3_ ( + .CE(plm_phy_cke_2_710), + .C(mgt_clk), + .D(plm_frm_reg_d0_td[3]), + .Q(plm_frm_reg_d1_td[3]), + .CLR(plm_rst) + ); + FDCE plm_frm_reg_d1_td_2_ ( + .CE(plm_phy_cke_2_710), + .C(mgt_clk), + .D(plm_frm_reg_d0_td[2]), + .Q(plm_frm_reg_d1_td[2]), + .CLR(plm_rst) + ); + FDCE plm_frm_reg_d1_td_1_ ( + .CE(plm_phy_cke_2_710), + .C(mgt_clk), + .D(plm_frm_reg_d0_td[1]), + .Q(plm_frm_reg_d1_td[1]), + .CLR(plm_rst) + ); + FDCE plm_frm_reg_d1_td_0_ ( + .CE(plm_phy_cke_2_710), + .C(mgt_clk), + .D(plm_frm_reg_d0_td[0]), + .Q(plm_frm_reg_d1_td[0]), + .CLR(plm_rst) + ); + FDCE plm_frm_reg_d2_tframe_h ( + .CE(plm_phy_cke_3_709), + .C(mgt_clk), + .D(plm_frm_reg_d1_tframe_h_1650), + .Q(plm_frm_reg_d2_tframe_h_1651), + .CLR(plm_rst) + ); + FDCE plm_frm_reg_d2_tframe_l ( + .CE(plm_phy_cke_3_709), + .C(mgt_clk), + .D(plm_frm_reg_d1_tframe_l_1652), + .Q(plm_frm_reg_d2_tframe_l_1653), + .CLR(plm_rst) + ); + FDCE plm_frm_reg_d1_idleflag_hh ( + .CE(plm_phy_cke_2_710), + .C(mgt_clk), + .D(plm_frm_reg_d1_idleflag_hh_3), + .Q(plm_frm_reg_d1_idleflag_hh_1654), + .CLR(plm_rst) + ); + FDCE plm_frm_reg_d1_idleflag_hl ( + .CE(plm_phy_cke_2_710), + .C(mgt_clk), + .D(plm_frm_reg_d1_idleflag_hl_3), + .Q(plm_frm_reg_d1_idleflag_hl_1655), + .CLR(plm_rst) + ); + FDCE plm_frm_reg_d1_idleflag_lh ( + .CE(plm_phy_cke_2_710), + .C(mgt_clk), + .D(plm_frm_reg_d1_idleflag_lh_3), + .Q(plm_frm_reg_d1_idleflag_lh_1656), + .CLR(plm_rst) + ); + FDCE plm_frm_reg_d1_idleflag_ll ( + .CE(plm_phy_cke_2_710), + .C(mgt_clk), + .D(plm_frm_reg_d1_idleflag_ll_3), + .Q(plm_frm_reg_d1_idleflag_ll_1657), + .CLR(plm_rst) + ); + FDCE plm_frm_reg_d2_idle_h ( + .CE(plm_phy_cke_3_709), + .C(mgt_clk), + .D(plm_frm_N_55314_i), + .Q(plm_frm_reg_d2_idle_h_1658), + .CLR(plm_rst) + ); + FDCE plm_frm_reg_d2_idle_l ( + .CE(plm_phy_cke_3_709), + .C(mgt_clk), + .D(plm_frm_N_57067_i), + .Q(plm_frm_reg_d2_idle_l_1659), + .CLR(plm_rst) + ); + FDCE plm_frm_reg_d2_charisk_0_ ( + .CE(plm_phy_cke_3_709), + .C(mgt_clk), + .D(plm_frm_N_58272), + .Q(plm_frm_reg_d2_charisk_0__1660), + .CLR(plm_rst) + ); + FDCE plm_frm_reg_d2_charisk_7_ ( + .CE(plm_phy_cke_3_709), + .C(mgt_clk), + .D(plm_frm_N_51384_i), + .Q(plm_frm_reg_d2_charisk_7__1661), + .CLR(plm_rst) + ); + FDCE plm_frm_reg_d2_charisk_4_ ( + .CE(plm_phy_cke_3_709), + .C(mgt_clk), + .D(plm_frm_N_51382_i), + .Q(plm_frm_reg_d2_charisk_4__1662), + .CLR(plm_rst) + ); + FDCE plm_frm_reg_d2_charisk_3_ ( + .CE(plm_phy_cke_3_709), + .C(mgt_clk), + .D(plm_frm_N_51388_i), + .Q(plm_frm_reg_d2_charisk_3__1663), + .CLR(plm_rst) + ); + FDCE plm_frm_reg_d2_td_63_ ( + .CE(plm_phy_cke_3_709), + .C(mgt_clk), + .D(plm_frm_N_87072_i), + .Q(plm_frm_reg_d2_td[63]), + .CLR(plm_rst) + ); + FDCE plm_frm_reg_d2_td_62_ ( + .CE(plm_phy_cke_3_709), + .C(mgt_clk), + .D(plm_frm_N_51438_i), + .Q(plm_frm_reg_d2_td[62]), + .CLR(plm_rst) + ); + FDCE plm_frm_reg_d2_td_61_ ( + .CE(plm_phy_cke_3_709), + .C(mgt_clk), + .D(plm_frm_N_87033_i), + .Q(plm_frm_reg_d2_td[61]), + .CLR(plm_rst) + ); + FDCE plm_frm_reg_d2_td_60_ ( + .CE(plm_phy_cke_3_709), + .C(mgt_clk), + .D(plm_frm_N_51436_i), + .Q(plm_frm_reg_d2_td[60]), + .CLR(plm_rst) + ); + FDCE plm_frm_reg_d2_td_59_ ( + .CE(plm_phy_cke_3_709), + .C(mgt_clk), + .D(plm_frm_N_51434_i), + .Q(plm_frm_reg_d2_td[59]), + .CLR(plm_rst) + ); + FDCE plm_frm_reg_d2_td_58_ ( + .CE(plm_phy_cke_3_709), + .C(mgt_clk), + .D(plm_frm_N_87073_i), + .Q(plm_frm_reg_d2_td[58]), + .CLR(plm_rst) + ); + FDCE plm_frm_reg_d2_td_57_ ( + .CE(plm_phy_cke_3_709), + .C(mgt_clk), + .D(plm_frm_N_87034_i), + .Q(plm_frm_reg_d2_td[57]), + .CLR(plm_rst) + ); + FDCE plm_frm_reg_d2_td_56_ ( + .CE(plm_phy_cke_3_709), + .C(mgt_clk), + .D(plm_frm_N_87035_i), + .Q(plm_frm_reg_d2_td[56]), + .CLR(plm_rst) + ); + FDCE plm_frm_reg_d2_td_55_ ( + .CE(plm_phy_cke_3_709), + .C(mgt_clk), + .D(plm_frm_N_51432_i), + .Q(plm_frm_reg_d2_td[55]), + .CLR(plm_rst) + ); + FDCE plm_frm_reg_d2_td_54_ ( + .CE(plm_phy_cke_3_709), + .C(mgt_clk), + .D(plm_frm_N_51430_i), + .Q(plm_frm_reg_d2_td[54]), + .CLR(plm_rst) + ); + FDCE plm_frm_reg_d2_td_53_ ( + .CE(plm_phy_cke_3_709), + .C(mgt_clk), + .D(plm_frm_N_51428_i), + .Q(plm_frm_reg_d2_td[53]), + .CLR(plm_rst) + ); + FDCE plm_frm_reg_d2_td_52_ ( + .CE(plm_phy_cke_3_709), + .C(mgt_clk), + .D(plm_frm_N_51426_i), + .Q(plm_frm_reg_d2_td[52]), + .CLR(plm_rst) + ); + FDCE plm_frm_reg_d2_td_51_ ( + .CE(plm_phy_cke_3_709), + .C(mgt_clk), + .D(plm_frm_N_51424_i), + .Q(plm_frm_reg_d2_td[51]), + .CLR(plm_rst) + ); + FDCE plm_frm_reg_d2_td_50_ ( + .CE(plm_phy_cke_3_709), + .C(mgt_clk), + .D(plm_frm_N_51422_i), + .Q(plm_frm_reg_d2_td[50]), + .CLR(plm_rst) + ); + FDCE plm_frm_reg_d2_td_49_ ( + .CE(plm_phy_cke_3_709), + .C(mgt_clk), + .D(plm_frm_N_51420_i), + .Q(plm_frm_reg_d2_td[49]), + .CLR(plm_rst) + ); + FDCE plm_frm_reg_d2_td_48_ ( + .CE(plm_phy_cke_3_709), + .C(mgt_clk), + .D(plm_frm_N_51418_i), + .Q(plm_frm_reg_d2_td[48]), + .CLR(plm_rst) + ); + FDCE plm_frm_reg_d2_td_47_ ( + .CE(plm_phy_cke_3_709), + .C(mgt_clk), + .D(plm_frm_N_51416_i), + .Q(plm_frm_reg_d2_td[47]), + .CLR(plm_rst) + ); + FDCE plm_frm_reg_d2_td_46_ ( + .CE(plm_phy_cke_3_709), + .C(mgt_clk), + .D(plm_frm_N_51414_i), + .Q(plm_frm_reg_d2_td[46]), + .CLR(plm_rst) + ); + FDCE plm_frm_reg_d2_td_45_ ( + .CE(plm_phy_cke_3_709), + .C(mgt_clk), + .D(plm_frm_N_51412_i), + .Q(plm_frm_reg_d2_td[45]), + .CLR(plm_rst) + ); + FDCE plm_frm_reg_d2_td_44_ ( + .CE(plm_phy_cke_3_709), + .C(mgt_clk), + .D(plm_frm_N_51410_i), + .Q(plm_frm_reg_d2_td[44]), + .CLR(plm_rst) + ); + FDCE plm_frm_reg_d2_td_43_ ( + .CE(plm_phy_cke_3_709), + .C(mgt_clk), + .D(plm_frm_N_51408_i), + .Q(plm_frm_reg_d2_td[43]), + .CLR(plm_rst) + ); + FDCE plm_frm_reg_d2_td_42_ ( + .CE(plm_phy_cke_3_709), + .C(mgt_clk), + .D(plm_frm_N_51406_i), + .Q(plm_frm_reg_d2_td[42]), + .CLR(plm_rst) + ); + FDCE plm_frm_reg_d2_td_41_ ( + .CE(plm_phy_cke_3_709), + .C(mgt_clk), + .D(plm_frm_N_51404_i), + .Q(plm_frm_reg_d2_td[41]), + .CLR(plm_rst) + ); + FDCE plm_frm_reg_d2_td_40_ ( + .CE(plm_phy_cke_3_709), + .C(mgt_clk), + .D(plm_frm_N_51402_i), + .Q(plm_frm_reg_d2_td[40]), + .CLR(plm_rst) + ); + FDCE plm_frm_reg_d2_td_39_ ( + .CE(plm_phy_cke_3_709), + .C(mgt_clk), + .D(plm_frm_N_51400_i), + .Q(plm_frm_reg_d2_td[39]), + .CLR(plm_rst) + ); + FDCE plm_frm_reg_d2_td_38_ ( + .CE(plm_phy_cke_3_709), + .C(mgt_clk), + .D(plm_frm_N_51398_i), + .Q(plm_frm_reg_d2_td[38]), + .CLR(plm_rst) + ); + FDCE plm_frm_reg_d2_td_37_ ( + .CE(plm_phy_cke_3_709), + .C(mgt_clk), + .D(plm_frm_N_51396_i), + .Q(plm_frm_reg_d2_td[37]), + .CLR(plm_rst) + ); + FDCE plm_frm_reg_d2_td_36_ ( + .CE(plm_phy_cke_3_709), + .C(mgt_clk), + .D(plm_frm_N_51394_i), + .Q(plm_frm_reg_d2_td[36]), + .CLR(plm_rst) + ); + FDCE plm_frm_reg_d2_td_35_ ( + .CE(plm_phy_cke_3_709), + .C(mgt_clk), + .D(plm_frm_N_51392_i), + .Q(plm_frm_reg_d2_td[35]), + .CLR(plm_rst) + ); + FDCE plm_frm_reg_d2_td_34_ ( + .CE(plm_phy_cke_3_709), + .C(mgt_clk), + .D(plm_frm_N_51390_i), + .Q(plm_frm_reg_d2_td[34]), + .CLR(plm_rst) + ); + FDCE plm_frm_reg_d2_td_33_ ( + .CE(plm_phy_cke_3_709), + .C(mgt_clk), + .D(plm_frm_N_9897_i), + .Q(plm_frm_reg_d2_td[33]), + .CLR(plm_rst) + ); + FDCE plm_frm_reg_d2_td_32_ ( + .CE(plm_phy_cke_3_709), + .C(mgt_clk), + .D(plm_frm_N_9899_i), + .Q(plm_frm_reg_d2_td[32]), + .CLR(plm_rst) + ); + FDCE plm_frm_reg_d2_td_31_ ( + .CE(plm_phy_cke_3_709), + .C(mgt_clk), + .D(plm_frm_N_9882_i), + .Q(plm_frm_reg_d2_td[31]), + .CLR(plm_rst) + ); + FDCE plm_frm_reg_d2_td_30_ ( + .CE(plm_phy_cke_3_709), + .C(mgt_clk), + .D(plm_frm_N_51488_i), + .Q(plm_frm_reg_d2_td[30]), + .CLR(plm_rst) + ); + FDCE plm_frm_reg_d2_td_29_ ( + .CE(plm_phy_cke_3_709), + .C(mgt_clk), + .D(plm_frm_N_9884_i), + .Q(plm_frm_reg_d2_td[29]), + .CLR(plm_rst) + ); + FDCE plm_frm_reg_d2_td_28_ ( + .CE(plm_phy_cke_3_709), + .C(mgt_clk), + .D(plm_frm_N_51486_i), + .Q(plm_frm_reg_d2_td[28]), + .CLR(plm_rst) + ); + FDCE plm_frm_reg_d2_td_27_ ( + .CE(plm_phy_cke_3_709), + .C(mgt_clk), + .D(plm_frm_N_51484_i), + .Q(plm_frm_reg_d2_td[27]), + .CLR(plm_rst) + ); + FDCE plm_frm_reg_d2_td_26_ ( + .CE(plm_phy_cke_3_709), + .C(mgt_clk), + .D(plm_frm_N_9885_i), + .Q(plm_frm_reg_d2_td[26]), + .CLR(plm_rst) + ); + FDCE plm_frm_reg_d2_td_25_ ( + .CE(plm_phy_cke_3_709), + .C(mgt_clk), + .D(plm_frm_N_9886_i), + .Q(plm_frm_reg_d2_td[25]), + .CLR(plm_rst) + ); + FDCE plm_frm_reg_d2_td_24_ ( + .CE(plm_phy_cke_3_709), + .C(mgt_clk), + .D(plm_frm_N_9887_i), + .Q(plm_frm_reg_d2_td[24]), + .CLR(plm_rst) + ); + FDCE plm_frm_reg_d2_td_23_ ( + .CE(plm_phy_cke_3_709), + .C(mgt_clk), + .D(plm_frm_N_51482_i), + .Q(plm_frm_reg_d2_td[23]), + .CLR(plm_rst) + ); + FDCE plm_frm_reg_d2_td_22_ ( + .CE(plm_phy_cke_3_709), + .C(mgt_clk), + .D(plm_frm_N_51480_i), + .Q(plm_frm_reg_d2_td[22]), + .CLR(plm_rst) + ); + FDCE plm_frm_reg_d2_td_21_ ( + .CE(plm_phy_cke_3_709), + .C(mgt_clk), + .D(plm_frm_N_51478_i), + .Q(plm_frm_reg_d2_td[21]), + .CLR(plm_rst) + ); + FDCE plm_frm_reg_d2_td_20_ ( + .CE(plm_phy_cke_3_709), + .C(mgt_clk), + .D(plm_frm_N_51476_i), + .Q(plm_frm_reg_d2_td[20]), + .CLR(plm_rst) + ); + FDCE plm_frm_reg_d2_td_19_ ( + .CE(plm_phy_cke_3_709), + .C(mgt_clk), + .D(plm_frm_N_51474_i), + .Q(plm_frm_reg_d2_td[19]), + .CLR(plm_rst) + ); + FDCE plm_frm_reg_d2_td_18_ ( + .CE(plm_phy_cke_3_709), + .C(mgt_clk), + .D(plm_frm_N_51472_i), + .Q(plm_frm_reg_d2_td[18]), + .CLR(plm_rst) + ); + FDCE plm_frm_reg_d2_td_17_ ( + .CE(plm_phy_cke_3_709), + .C(mgt_clk), + .D(plm_frm_N_51470_i), + .Q(plm_frm_reg_d2_td[17]), + .CLR(plm_rst) + ); + FDCE plm_frm_reg_d2_td_16_ ( + .CE(plm_phy_cke_3_709), + .C(mgt_clk), + .D(plm_frm_N_51468_i), + .Q(plm_frm_reg_d2_td[16]), + .CLR(plm_rst) + ); + FDCE plm_frm_reg_d2_td_15_ ( + .CE(plm_phy_cke_3_709), + .C(mgt_clk), + .D(plm_frm_N_51466_i), + .Q(plm_frm_reg_d2_td[15]), + .CLR(plm_rst) + ); + FDCE plm_frm_reg_d2_td_14_ ( + .CE(plm_phy_cke_3_709), + .C(mgt_clk), + .D(plm_frm_N_51464_i), + .Q(plm_frm_reg_d2_td[14]), + .CLR(plm_rst) + ); + FDCE plm_frm_reg_d2_td_13_ ( + .CE(plm_phy_cke_3_709), + .C(mgt_clk), + .D(plm_frm_N_51462_i), + .Q(plm_frm_reg_d2_td[13]), + .CLR(plm_rst) + ); + FDCE plm_frm_reg_d2_td_12_ ( + .CE(plm_phy_cke_3_709), + .C(mgt_clk), + .D(plm_frm_N_51460_i), + .Q(plm_frm_reg_d2_td[12]), + .CLR(plm_rst) + ); + FDCE plm_frm_reg_d2_td_11_ ( + .CE(plm_phy_cke_3_709), + .C(mgt_clk), + .D(plm_frm_N_51458_i), + .Q(plm_frm_reg_d2_td[11]), + .CLR(plm_rst) + ); + FDCE plm_frm_reg_d2_td_10_ ( + .CE(plm_phy_cke_3_709), + .C(mgt_clk), + .D(plm_frm_N_51456_i), + .Q(plm_frm_reg_d2_td[10]), + .CLR(plm_rst) + ); + FDCE plm_frm_reg_d2_td_9_ ( + .CE(plm_phy_cke_3_709), + .C(mgt_clk), + .D(plm_frm_N_51454_i), + .Q(plm_frm_reg_d2_td[9]), + .CLR(plm_rst) + ); + FDCE plm_frm_reg_d2_td_8_ ( + .CE(plm_phy_cke_3_709), + .C(mgt_clk), + .D(plm_frm_N_51452_i), + .Q(plm_frm_reg_d2_td[8]), + .CLR(plm_rst) + ); + FDCE plm_frm_reg_d2_td_7_ ( + .CE(plm_phy_cke_3_709), + .C(mgt_clk), + .D(plm_frm_N_51450_i), + .Q(plm_frm_reg_d2_td[7]), + .CLR(plm_rst) + ); + FDCE plm_frm_reg_d2_td_6_ ( + .CE(plm_phy_cke_3_709), + .C(mgt_clk), + .D(plm_frm_N_51448_i), + .Q(plm_frm_reg_d2_td[6]), + .CLR(plm_rst) + ); + FDCE plm_frm_reg_d2_td_5_ ( + .CE(plm_phy_cke_3_709), + .C(mgt_clk), + .D(plm_frm_N_51446_i), + .Q(plm_frm_reg_d2_td[5]), + .CLR(plm_rst) + ); + FDCE plm_frm_reg_d2_td_4_ ( + .CE(plm_phy_cke_3_709), + .C(mgt_clk), + .D(plm_frm_N_51444_i), + .Q(plm_frm_reg_d2_td[4]), + .CLR(plm_rst) + ); + FDCE plm_frm_reg_d2_td_3_ ( + .CE(plm_phy_cke_3_709), + .C(mgt_clk), + .D(plm_frm_N_51442_i), + .Q(plm_frm_reg_d2_td[3]), + .CLR(plm_rst) + ); + FDCE plm_frm_reg_d2_td_2_ ( + .CE(plm_phy_cke_3_709), + .C(mgt_clk), + .D(plm_frm_N_51440_i), + .Q(plm_frm_reg_d2_td[2]), + .CLR(plm_rst) + ); + FDCE plm_frm_reg_d2_td_1_ ( + .CE(plm_phy_cke_3_709), + .C(mgt_clk), + .D(plm_frm_reg_d2_td_24_0_iv_i_a2[1]), + .Q(plm_frm_reg_d2_td[1]), + .CLR(plm_rst) + ); + FDCE plm_frm_reg_d2_td_0_ ( + .CE(plm_phy_cke_3_709), + .C(mgt_clk), + .D(plm_frm_N_87025_i), + .Q(plm_frm_reg_d2_td[0]), + .CLR(plm_rst) + ); + defparam plm_frm_ciao_baby_N_85671_i.INIT = 16'hDF5F; + LUT4_L plm_frm_ciao_baby_N_85671_i ( + .I0(plm_frm_N_14937_1_i), + .I1(plm_frm_N_61353), + .I2(plm_frm_N_85671_i_1), + .I3(plm_frm_reg_d2_td[45]), + .LO(plm_frm_N_85671_i) + ); + defparam plm_frm_ciao_baby_N_85690_i.INIT = 16'hDF5F; + LUT4_L plm_frm_ciao_baby_N_85690_i ( + .I0(plm_frm_N_14937_1_i), + .I1(plm_frm_N_61353), + .I2(plm_frm_N_85690_i_1), + .I3(plm_frm_reg_d2_td[47]), + .LO(plm_frm_N_85690_i) + ); + defparam plm_frm_frame1_sel_sequencer_reg_wd_sel_5_0_a2_0_a2_1_.INIT = 8'h06; + LUT3_L plm_frm_frame1_sel_sequencer_reg_wd_sel_5_0_a2_0_a2_1_ ( + .I0(plm_frm_reg_wd_sel[0]), + .I1(plm_frm_reg_wd_sel[1]), + .I2(plm_phy_cke_0_712), + .LO(plm_frm_frame1_reg_wd_sel_5[1]) + ); + defparam plm_frm_frame1_sel_sequencer_reg_wd_sel_5_0_a2_0_a2_0_.INIT = 4'h1; + LUT2_L plm_frm_frame1_sel_sequencer_reg_wd_sel_5_0_a2_0_a2_0_ ( + .I0(plm_frm_reg_wd_sel[0]), + .I1(plm_phy_cke_0_712), + .LO(plm_frm_frame1_reg_wd_sel_5[0]) + ); + FDC plm_frm_frame1_reg_byp3 ( + .C(mgt_clk), + .D(plm_frm_N_51332_i), + .Q(plm_frm_reg_byp3), + .CLR(plm_rst) + ); + FDC plm_frm_frame1_reg_byp1 ( + .C(mgt_clk), + .D(plm_frm_N_51330_i), + .Q(plm_frm_reg_byp1), + .CLR(plm_rst) + ); + FDC plm_frm_frame1_reg_wd_sel_1_ ( + .C(mgt_clk), + .D(plm_frm_frame1_reg_wd_sel_5[1]), + .Q(plm_frm_reg_wd_sel[1]), + .CLR(plm_rst) + ); + FDC plm_frm_frame1_reg_wd_sel_0_ ( + .C(mgt_clk), + .D(plm_frm_frame1_reg_wd_sel_5[0]), + .Q(plm_frm_reg_wd_sel[0]), + .CLR(plm_rst) + ); + defparam plm_frm_frame4_l_override_iv_i_o2.INIT = 8'h3E; + LUT3 plm_frm_frame4_l_override_iv_i_o2 ( + .I0(plm_frm_reg_frm_atomic_3_i_o3), + .I1(plm_frm_reg_state[0]), + .I2(plm_frm_reg_state[1]), + .O(plm_frm_N_55875_i) + ); + defparam plm_frm_frame4_un18_by4_frm3_char_iv_0_a2_0_7_.INIT = 16'h0002; + LUT4 plm_frm_frame4_un18_by4_frm3_char_iv_0_a2_0_7_ ( + .I0(plm_frm_reg_frm_atomic_3_i_o3), + .I1(plm_frm_reg_state[0]), + .I2(plm_frm_reg_state[1]), + .I3(plm_frm_reg_d2_idle_h_1658), + .O(plm_frm_frame4_N_58253) + ); + defparam plm_frm_frame4_un7_by4_frm1_char_i_o2_0_.INIT = 8'h01; + LUT3 plm_frm_frame4_un7_by4_frm1_char_i_o2_0_ ( + .I0(plm_frm_N_55915_i), + .I1(plm_frm_reg_state[0]), + .I2(plm_frm_reg_state[1]), + .O(plm_frm_un7_by4_frm1_char_i_o2[0]) + ); + defparam plm_frm_frame4_N_58309_i.INIT = 4'hE; + LUT2_L plm_frm_frame4_N_58309_i ( + .I0(plm_frm_N_55875_i), + .I1(plm_frm_reg_d2_td[18]), + .LO(plm_frm_N_58309_i) + ); + defparam plm_frm_frame4_un18_by4_frm1_char_0_a2_1_.INIT = 4'h4; + LUT2_L plm_frm_frame4_un18_by4_frm1_char_0_a2_1_ ( + .I0(plm_frm_N_55875_i), + .I1(plm_frm_reg_d2_td[17]), + .LO(plm_frm_by4_frm1_char_1_) + ); + defparam plm_frm_frame4_un18_by4_frm1_char_0_a2_0_.INIT = 4'h4; + LUT2_L plm_frm_frame4_un18_by4_frm1_char_0_a2_0_ ( + .I0(plm_frm_N_55875_i), + .I1(plm_frm_reg_d2_td[16]), + .LO(plm_frm_by4_frm1_char_0_) + ); + defparam plm_frm_frame4_N_87088_i.INIT = 4'hD; + LUT2_L plm_frm_frame4_N_87088_i ( + .I0(plm_frm_un7_by4_frm1_char_i_o2[0]), + .I1(plm_frm_reg_d2_charisk_4__1662), + .LO(plm_frm_N_87088_i) + ); + defparam plm_frm_frame4_N_58376_i.INIT = 4'hE; + LUT2_L plm_frm_frame4_N_58376_i ( + .I0(plm_frm_N_55875_i), + .I1(plm_frm_reg_d2_charisk_0__1660), + .LO(plm_frm_N_58376_i) + ); + defparam plm_frm_frame4_un18_by4_frm2_char_0_a2_1_.INIT = 4'h4; + LUT2_L plm_frm_frame4_un18_by4_frm2_char_0_a2_1_ ( + .I0(plm_frm_N_55875_i), + .I1(plm_frm_reg_d2_td[9]), + .LO(plm_frm_by4_frm2_char_1_) + ); + defparam plm_frm_frame4_un18_by4_frm2_char_0_a2_0_.INIT = 4'h4; + LUT2_L plm_frm_frame4_un18_by4_frm2_char_0_a2_0_ ( + .I0(plm_frm_N_55875_i), + .I1(plm_frm_reg_d2_td[8]), + .LO(plm_frm_by4_frm2_char_0_) + ); + defparam plm_frm_frame4_un7_by4_frm1_char_iv_i_7_.INIT = 16'h0302; + LUT4_L plm_frm_frame4_un7_by4_frm1_char_iv_i_7_ ( + .I0(plm_frm_N_55915_i), + .I1(plm_frm_reg_state[0]), + .I2(plm_frm_reg_state[1]), + .I3(plm_frm_reg_d2_td[55]), + .LO(plm_frm_N_51878_i) + ); + defparam plm_frm_frame4_un7_by4_frm1_char_i_6_.INIT = 4'h8; + LUT2_L plm_frm_frame4_un7_by4_frm1_char_i_6_ ( + .I0(plm_frm_un7_by4_frm1_char_i_o2[0]), + .I1(plm_frm_reg_d2_td[54]), + .LO(plm_frm_N_51341_i) + ); + defparam plm_frm_frame4_un7_by4_frm1_char_iv_i_5_.INIT = 16'h0302; + LUT4_L plm_frm_frame4_un7_by4_frm1_char_iv_i_5_ ( + .I0(plm_frm_N_55915_i), + .I1(plm_frm_reg_state[0]), + .I2(plm_frm_reg_state[1]), + .I3(plm_frm_reg_d2_td[53]), + .LO(plm_frm_N_51880_i) + ); + defparam plm_frm_frame4_N_86982_i.INIT = 4'hD; + LUT2_L plm_frm_frame4_N_86982_i ( + .I0(plm_frm_un7_by4_frm1_char_i_o2[0]), + .I1(plm_frm_reg_d2_td[52]), + .LO(plm_frm_N_86982_i) + ); + defparam plm_frm_frame4_N_86981_i.INIT = 4'hD; + LUT2_L plm_frm_frame4_N_86981_i ( + .I0(plm_frm_un7_by4_frm1_char_i_o2[0]), + .I1(plm_frm_reg_d2_td[51]), + .LO(plm_frm_N_86981_i) + ); + defparam plm_frm_frame4_N_86980_i.INIT = 4'hD; + LUT2_L plm_frm_frame4_N_86980_i ( + .I0(plm_frm_un7_by4_frm1_char_i_o2[0]), + .I1(plm_frm_reg_d2_td[50]), + .LO(plm_frm_N_86980_i) + ); + defparam plm_frm_frame4_un7_by4_frm1_char_i_1_.INIT = 4'h8; + LUT2_L plm_frm_frame4_un7_by4_frm1_char_i_1_ ( + .I0(plm_frm_un7_by4_frm1_char_i_o2[0]), + .I1(plm_frm_reg_d2_td[49]), + .LO(plm_frm_N_51339_i) + ); + defparam plm_frm_frame4_un7_by4_frm1_char_i_0_.INIT = 4'h8; + LUT2_L plm_frm_frame4_un7_by4_frm1_char_i_0_ ( + .I0(plm_frm_un7_by4_frm1_char_i_o2[0]), + .I1(plm_frm_reg_d2_td[48]), + .LO(plm_frm_N_51337_i) + ); + defparam plm_frm_frame4_N_86973_i.INIT = 8'hDC; + LUT3_L plm_frm_frame4_N_86973_i ( + .I0(plm_frm_N_55875_i), + .I1(plm_frm_frame4_N_58253), + .I2(plm_frm_reg_d2_td[23]), + .LO(plm_frm_N_86973_i) + ); + defparam plm_frm_frame4_un18_by4_frm1_char_0_a2_6_.INIT = 4'h4; + LUT2_L plm_frm_frame4_un18_by4_frm1_char_0_a2_6_ ( + .I0(plm_frm_N_55875_i), + .I1(plm_frm_reg_d2_td[22]), + .LO(plm_frm_by4_frm1_char_6_) + ); + defparam plm_frm_frame4_N_86974_i.INIT = 8'hDC; + LUT3_L plm_frm_frame4_N_86974_i ( + .I0(plm_frm_N_55875_i), + .I1(plm_frm_frame4_N_58253), + .I2(plm_frm_reg_d2_td[21]), + .LO(plm_frm_N_86974_i) + ); + defparam plm_frm_frame4_N_58311_i.INIT = 4'hE; + LUT2_L plm_frm_frame4_N_58311_i ( + .I0(plm_frm_N_55875_i), + .I1(plm_frm_reg_d2_td[20]), + .LO(plm_frm_N_58311_i) + ); + defparam plm_frm_frame4_N_58310_i.INIT = 4'hE; + LUT2_L plm_frm_frame4_N_58310_i ( + .I0(plm_frm_N_55875_i), + .I1(plm_frm_reg_d2_td[19]), + .LO(plm_frm_N_58310_i) + ); + defparam plm_frm_frame4_un18_by4_frm3_char_0_a2_0_.INIT = 4'h4; + LUT2_L plm_frm_frame4_un18_by4_frm3_char_0_a2_0_ ( + .I0(plm_frm_N_55875_i), + .I1(plm_frm_reg_d2_td[0]), + .LO(plm_frm_by4_frm3_char_0_) + ); + defparam plm_frm_frame4_un7_by4_frm2_char_iv_i_7_.INIT = 16'h0302; + LUT4_L plm_frm_frame4_un7_by4_frm2_char_iv_i_7_ ( + .I0(plm_frm_N_55915_i), + .I1(plm_frm_reg_state[0]), + .I2(plm_frm_reg_state[1]), + .I3(plm_frm_reg_d2_td[47]), + .LO(plm_frm_N_51874_i) + ); + defparam plm_frm_frame4_un7_by4_frm2_char_i_6_.INIT = 4'h8; + LUT2_L plm_frm_frame4_un7_by4_frm2_char_i_6_ ( + .I0(plm_frm_un7_by4_frm1_char_i_o2[0]), + .I1(plm_frm_reg_d2_td[46]), + .LO(plm_frm_N_51350_i) + ); + defparam plm_frm_frame4_un7_by4_frm2_char_iv_i_5_.INIT = 16'h0302; + LUT4_L plm_frm_frame4_un7_by4_frm2_char_iv_i_5_ ( + .I0(plm_frm_N_55915_i), + .I1(plm_frm_reg_state[0]), + .I2(plm_frm_reg_state[1]), + .I3(plm_frm_reg_d2_td[45]), + .LO(plm_frm_N_51876_i) + ); + defparam plm_frm_frame4_N_86985_i.INIT = 4'hD; + LUT2_L plm_frm_frame4_N_86985_i ( + .I0(plm_frm_un7_by4_frm1_char_i_o2[0]), + .I1(plm_frm_reg_d2_td[44]), + .LO(plm_frm_N_86985_i) + ); + defparam plm_frm_frame4_N_86984_i.INIT = 4'hD; + LUT2_L plm_frm_frame4_N_86984_i ( + .I0(plm_frm_un7_by4_frm1_char_i_o2[0]), + .I1(plm_frm_reg_d2_td[43]), + .LO(plm_frm_N_86984_i) + ); + defparam plm_frm_frame4_N_86983_i.INIT = 4'hD; + LUT2_L plm_frm_frame4_N_86983_i ( + .I0(plm_frm_un7_by4_frm1_char_i_o2[0]), + .I1(plm_frm_reg_d2_td[42]), + .LO(plm_frm_N_86983_i) + ); + defparam plm_frm_frame4_un7_by4_frm2_char_i_1_.INIT = 4'h8; + LUT2_L plm_frm_frame4_un7_by4_frm2_char_i_1_ ( + .I0(plm_frm_un7_by4_frm1_char_i_o2[0]), + .I1(plm_frm_reg_d2_td[41]), + .LO(plm_frm_N_51348_i) + ); + defparam plm_frm_frame4_un7_by4_frm2_char_i_0_.INIT = 4'h8; + LUT2_L plm_frm_frame4_un7_by4_frm2_char_i_0_ ( + .I0(plm_frm_un7_by4_frm1_char_i_o2[0]), + .I1(plm_frm_reg_d2_td[40]), + .LO(plm_frm_N_51346_i) + ); + defparam plm_frm_frame4_N_86971_i.INIT = 8'hDC; + LUT3_L plm_frm_frame4_N_86971_i ( + .I0(plm_frm_N_55875_i), + .I1(plm_frm_frame4_N_58253), + .I2(plm_frm_reg_d2_td[15]), + .LO(plm_frm_N_86971_i) + ); + defparam plm_frm_frame4_un18_by4_frm2_char_0_a2_6_.INIT = 4'h4; + LUT2_L plm_frm_frame4_un18_by4_frm2_char_0_a2_6_ ( + .I0(plm_frm_N_55875_i), + .I1(plm_frm_reg_d2_td[14]), + .LO(plm_frm_by4_frm2_char_6_) + ); + defparam plm_frm_frame4_N_86972_i.INIT = 8'hDC; + LUT3_L plm_frm_frame4_N_86972_i ( + .I0(plm_frm_N_55875_i), + .I1(plm_frm_frame4_N_58253), + .I2(plm_frm_reg_d2_td[13]), + .LO(plm_frm_N_86972_i) + ); + defparam plm_frm_frame4_N_58314_i.INIT = 4'hE; + LUT2_L plm_frm_frame4_N_58314_i ( + .I0(plm_frm_N_55875_i), + .I1(plm_frm_reg_d2_td[12]), + .LO(plm_frm_N_58314_i) + ); + defparam plm_frm_frame4_N_58313_i.INIT = 4'hE; + LUT2_L plm_frm_frame4_N_58313_i ( + .I0(plm_frm_N_55875_i), + .I1(plm_frm_reg_d2_td[11]), + .LO(plm_frm_N_58313_i) + ); + defparam plm_frm_frame4_N_58312_i.INIT = 4'hE; + LUT2_L plm_frm_frame4_N_58312_i ( + .I0(plm_frm_N_55875_i), + .I1(plm_frm_reg_d2_td[10]), + .LO(plm_frm_N_58312_i) + ); + defparam plm_frm_frame4_un7_by4_frm3_char_iv_i_7_.INIT = 16'h0302; + LUT4_L plm_frm_frame4_un7_by4_frm3_char_iv_i_7_ ( + .I0(plm_frm_N_55915_i), + .I1(plm_frm_reg_state[0]), + .I2(plm_frm_reg_state[1]), + .I3(plm_frm_reg_d2_td[39]), + .LO(plm_frm_N_51870_i) + ); + defparam plm_frm_frame4_un7_by4_frm3_char_i_6_.INIT = 4'h8; + LUT2_L plm_frm_frame4_un7_by4_frm3_char_i_6_ ( + .I0(plm_frm_un7_by4_frm1_char_i_o2[0]), + .I1(plm_frm_reg_d2_td[38]), + .LO(plm_frm_N_51359_i) + ); + defparam plm_frm_frame4_un7_by4_frm3_char_iv_i_5_.INIT = 16'h0302; + LUT4_L plm_frm_frame4_un7_by4_frm3_char_iv_i_5_ ( + .I0(plm_frm_N_55915_i), + .I1(plm_frm_reg_state[0]), + .I2(plm_frm_reg_state[1]), + .I3(plm_frm_reg_d2_td[37]), + .LO(plm_frm_N_51872_i) + ); + defparam plm_frm_frame4_N_86988_i.INIT = 4'hD; + LUT2_L plm_frm_frame4_N_86988_i ( + .I0(plm_frm_un7_by4_frm1_char_i_o2[0]), + .I1(plm_frm_reg_d2_td[36]), + .LO(plm_frm_N_86988_i) + ); + defparam plm_frm_frame4_N_86987_i.INIT = 4'hD; + LUT2_L plm_frm_frame4_N_86987_i ( + .I0(plm_frm_un7_by4_frm1_char_i_o2[0]), + .I1(plm_frm_reg_d2_td[35]), + .LO(plm_frm_N_86987_i) + ); + defparam plm_frm_frame4_N_86986_i.INIT = 4'hD; + LUT2_L plm_frm_frame4_N_86986_i ( + .I0(plm_frm_un7_by4_frm1_char_i_o2[0]), + .I1(plm_frm_reg_d2_td[34]), + .LO(plm_frm_N_86986_i) + ); + defparam plm_frm_frame4_un7_by4_frm3_char_i_1_.INIT = 4'h8; + LUT2_L plm_frm_frame4_un7_by4_frm3_char_i_1_ ( + .I0(plm_frm_un7_by4_frm1_char_i_o2[0]), + .I1(plm_frm_reg_d2_td[33]), + .LO(plm_frm_N_51357_i) + ); + defparam plm_frm_frame4_un7_by4_frm3_char_i_0_.INIT = 4'h8; + LUT2_L plm_frm_frame4_un7_by4_frm3_char_i_0_ ( + .I0(plm_frm_un7_by4_frm1_char_i_o2[0]), + .I1(plm_frm_reg_d2_td[32]), + .LO(plm_frm_N_51355_i) + ); + defparam plm_frm_frame4_N_86969_i.INIT = 8'hDC; + LUT3_L plm_frm_frame4_N_86969_i ( + .I0(plm_frm_N_55875_i), + .I1(plm_frm_frame4_N_58253), + .I2(plm_frm_reg_d2_td[7]), + .LO(plm_frm_N_86969_i) + ); + defparam plm_frm_frame4_un18_by4_frm3_char_0_a2_6_.INIT = 4'h4; + LUT2_L plm_frm_frame4_un18_by4_frm3_char_0_a2_6_ ( + .I0(plm_frm_N_55875_i), + .I1(plm_frm_reg_d2_td[6]), + .LO(plm_frm_by4_frm3_char_6_) + ); + defparam plm_frm_frame4_N_86970_i.INIT = 8'hDC; + LUT3_L plm_frm_frame4_N_86970_i ( + .I0(plm_frm_N_55875_i), + .I1(plm_frm_frame4_N_58253), + .I2(plm_frm_reg_d2_td[5]), + .LO(plm_frm_N_86970_i) + ); + defparam plm_frm_frame4_N_58317_i.INIT = 4'hE; + LUT2_L plm_frm_frame4_N_58317_i ( + .I0(plm_frm_N_55875_i), + .I1(plm_frm_reg_d2_td[4]), + .LO(plm_frm_N_58317_i) + ); + defparam plm_frm_frame4_N_58316_i.INIT = 4'hE; + LUT2_L plm_frm_frame4_N_58316_i ( + .I0(plm_frm_N_55875_i), + .I1(plm_frm_reg_d2_td[3]), + .LO(plm_frm_N_58316_i) + ); + defparam plm_frm_frame4_N_58315_i.INIT = 4'hE; + LUT2_L plm_frm_frame4_N_58315_i ( + .I0(plm_frm_N_55875_i), + .I1(plm_frm_reg_d2_td[2]), + .LO(plm_frm_N_58315_i) + ); + defparam plm_frm_frame4_un18_by4_frm3_char_0_a2_1_.INIT = 4'h4; + LUT2_L plm_frm_frame4_un18_by4_frm3_char_0_a2_1_ ( + .I0(plm_frm_N_55875_i), + .I1(plm_frm_reg_d2_td[1]), + .LO(plm_frm_by4_frm3_char_1_) + ); + defparam plm_frm_frame4_next_state_m2_i_1_.INIT = 16'h3032; + LUT4_L plm_frm_frame4_next_state_m2_i_1_ ( + .I0(plm_frm_reg_frm_atomic_3_i_o3), + .I1(plm_frm_reg_state[0]), + .I2(plm_frm_reg_state[1]), + .I3(plm_frm_reg_d2_idle_h_1658), + .LO(plm_frm_frame4_N_51496_i) + ); + defparam plm_frm_frame4_next_state_ss0_i.INIT = 8'h32; + LUT3_L plm_frm_frame4_next_state_ss0_i ( + .I0(plm_frm_N_55915_i), + .I1(plm_frm_reg_state[0]), + .I2(plm_frm_reg_state[1]), + .LO(plm_frm_frame4_N_51494_i) + ); + FDC plm_frm_frame4_reg_state_1_ ( + .C(mgt_clk), + .D(plm_frm_frame4_N_51496_i), + .Q(plm_frm_reg_state[1]), + .CLR(plm_rst) + ); + FDC plm_frm_frame4_reg_state_0_ ( + .C(mgt_clk), + .D(plm_frm_frame4_N_51494_i), + .Q(plm_frm_reg_state[0]), + .CLR(plm_rst) + ); + defparam plm_frm_frame4_N_86003_i.INIT = 8'hFE; + LUT3_L plm_frm_frame4_N_86003_i ( + .I0(plm_frm_reg_state[1]), + .I1(plm_frm_reg_state[0]), + .I2(plm_frm_N_55915_i), + .LO(plm_frm_N_86003_i) + ); + VCC plm_fsm_VCC ( + .P(plm_fsm_VCC_1796) + ); + defparam plm_fsm_un1_reg_state_19_i_0_o2_0.INIT = 4'h1; + LUT2 plm_fsm_un1_reg_state_19_i_0_o2_0 ( + .I0(plm_fsm_reg_state_14__1791), + .I1(plm_fsm_reg_state_15__1790), + .O(N_29556_i) + ); + defparam plm_fsm_un3_clw0_newv_1_0_x3_0_x3_0_x3_0_x3.INIT = 4'h6; + LUT2 plm_fsm_un3_clw0_newv_1_0_x3_0_x3_0_x3_0_x3 ( + .I0(plm_fsm_reg_rx0_old[1]), + .I1(plm_rx0_lane_num[1]), + .O(plm_fsm_N_56421_i_0) + ); + defparam plm_fsm_l0_exit_reason_0_0_0_a2_2.INIT = 4'h2; + LUT2 plm_fsm_l0_exit_reason_0_0_0_a2_2 ( + .I0(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_num[2]), + .I1(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_num_2_q[0]), + .O(l0_exit_reason_0_0_0_a2_2) + ); + defparam plm_fsm_fsm_vector_reg_state_141_0_0_1_iv_i_0_0_a3_0_1_10_.INIT = 4'h1; + LUT2 plm_fsm_fsm_vector_reg_state_141_0_0_1_iv_i_0_0_a3_0_1_10_ ( + .I0(plm_rx2_lane_pad), + .I1(plm_rx3_lane_pad), + .O(plm_fsm_N_61287_1) + ); + defparam plm_fsm_un1_reg_state_7_0_a2_0_a2_1_0_a2.INIT = 4'h1; + LUT2 plm_fsm_un1_reg_state_7_0_a2_0_a2_1_0_a2 ( + .I0(plm_fsm_reg_state_3__1781), + .I1(plm_fsm_reg_state_4__1780), + .O(plm_fsm_N_45455_1) + ); + defparam plm_fsm_reg_rx_clear_cs_2_sqmuxa_1_1.INIT = 4'h4; + LUT2 plm_fsm_reg_rx_clear_cs_2_sqmuxa_1_1 ( + .I0(plm_fsm_cc_cntrout0), + .I1(plm_fsm_reg_state_9__1795), + .O(plm_fsm_reg_rx_clear_cs_2_sqmuxa_1_1_1725) + ); + defparam plm_fsm_good_by4_1_0_a2_0_a3_0_a2.INIT = 4'h1; + LUT2 plm_fsm_good_by4_1_0_a2_0_a3_0_a2 ( + .I0(plm_rx2_link_pad), + .I1(plm_rx3_link_pad), + .O(plm_fsm_good_by4_1) + ); + defparam plm_fsm_reg_rx_clear_cs_0_sqmuxa_10_i_0_i_a2_0_a2_2.INIT = 4'h8; + LUT2 plm_fsm_reg_rx_clear_cs_0_sqmuxa_10_i_0_i_a2_0_a2_2 ( + .I0(plm_rx0_lane_pad), + .I1(plm_rx0_ts1_c), + .O(plm_fsm_reg_rx_clear_cs_0_sqmuxa_10_2) + ); + defparam plm_fsm_un1_reg_state_18_i_0_0_0_a3_1_1.INIT = 4'h8; + LUT2 plm_fsm_un1_reg_state_18_i_0_0_0_a3_1_1 ( + .I0(plm_tx2_lane_pad), + .I1(plm_tx2_link_pad), + .O(plm_fsm_N_61276_1) + ); + defparam plm_fsm_un1_reg_state_22_i_0_0_0_o2_0.INIT = 4'h1; + LUT2 plm_fsm_un1_reg_state_22_i_0_0_0_o2_0 ( + .I0(plm_fsm_reg_state_9__1795), + .I1(plm_fsm_reg_state_10__1792), + .O(N_56513_i) + ); + defparam plm_fsm_un3_xl_clw0_newv_1_0_x3_0_x3_0_x3_0_x3.INIT = 4'h6; + LUT2 plm_fsm_un3_xl_clw0_newv_1_0_x3_0_x3_0_x3_0_x3 ( + .I0(plm_fsm_reg_xl_rx0_old[1]), + .I1(plm_rx0_lane_num[1]), + .O(plm_fsm_N_56419_i_0) + ); + defparam plm_fsm_l0_exit_reason_0_0_0_o3.INIT = 4'h1; + LUT2 plm_fsm_l0_exit_reason_0_0_0_o3 ( + .I0(plm_reg_ts2_1_1), + .I1(plm_reg_ts1_1_1), + .O(plm_fsm_N_56214_i) + ); + defparam plm_fsm_l0_exit_reason_0_0_0_o2.INIT = 4'h1; + LUT2 plm_fsm_l0_exit_reason_0_0_0_o2 ( + .I0(plm_reg_ts2_1), + .I1(plm_reg_ts1_1), + .O(plm_fsm_N_56187_i) + ); + defparam plm_fsm_fsm_vector_N_36829_i_0_a3_0_o3_0.INIT = 4'h1; + LUT2 plm_fsm_fsm_vector_N_36829_i_0_a3_0_o3_0 ( + .I0(plm_tx0_lane_pad), + .I1(plm_tx0_link_pad), + .O(plm_fsm_N_56117_i) + ); + defparam plm_fsm_reg_rx_clear_cs_0_sqmuxa_3.INIT = 4'h8; + LUT2 plm_fsm_reg_rx_clear_cs_0_sqmuxa_3 ( + .I0(plm_fsm_rc_cntrout_ts2_0), + .I1(plm_fsm_reg_state_14__1791), + .O(plm_fsm_reg_rx_clear_cs_0_sqmuxa_3_1749) + ); + defparam plm_fsm_fsm_vector_reg_state_141_0_0_1_iv_i_0_0_a3_0_0_10_.INIT = 4'h1; + LUT2 plm_fsm_fsm_vector_reg_state_141_0_0_1_iv_i_0_0_a3_0_0_10_ ( + .I0(plm_rx1_link_pad), + .I1(plm_tx2_link_pad), + .O(plm_fsm_N_37129_7) + ); + defparam plm_fsm_reg_rx_clear_cs_1_sqmuxa_1_0.INIT = 4'h4; + LUT2 plm_fsm_reg_rx_clear_cs_1_sqmuxa_1_0 ( + .I0(plm_fsm_rc_cntrout_ts2_0), + .I1(plm_fsm_reg_state_14__1791), + .O(plm_fsm_reg_rx_clear_cs_1_sqmuxa_1_0_1752) + ); + defparam plm_fsm_ri_idle_data_i_o3_0.INIT = 4'h8; + LUT2_L plm_fsm_ri_idle_data_i_o3_0 ( + .I0(plm_fsm_ri_cntrout1), + .I1(plm_fsm_ri_cntrout3), + .LO(plm_fsm_ri_idle_data_i_o3_0_1676) + ); + defparam plm_fsm_ci_idle_data_i_o3_0.INIT = 4'h8; + LUT2_L plm_fsm_ci_idle_data_i_o3_0 ( + .I0(plm_fsm_ci_cntrout1), + .I1(plm_fsm_ci_cntrout3), + .LO(plm_fsm_ci_idle_data_i_o3_0_1677) + ); + defparam plm_fsm_hr_restart_0_0_0_a2_2_0.INIT = 4'h8; + LUT2_L plm_fsm_hr_restart_0_0_0_a2_2_0 ( + .I0(plm_rx1_linkctrl_0_), + .I1(plm_rx1_ts1_c), + .LO(plm_fsm_hr_restart_0_0_0_a2_2_0_1668) + ); + defparam plm_fsm_fsm_vector_reg_noscramble54_0_o3_i_o3_1.INIT = 4'h8; + LUT2_L plm_fsm_fsm_vector_reg_noscramble54_0_o3_i_o3_1 ( + .I0(plm_fsm_cc_cntrout0), + .I1(plm_fsm_cc_cntrout1), + .LO(plm_fsm_reg_noscramble54_0_o3_i_o3_1) + ); + defparam plm_fsm_fsm_vector_reg_rx_clear_cs273_0.INIT = 4'h8; + LUT2_L plm_fsm_fsm_vector_reg_rx_clear_cs273_0 ( + .I0(plm_fsm_rc_cntrout_ts2_2), + .I1(plm_fsm_rc_cntrout_ts2_3), + .LO(plm_fsm_reg_rx_clear_cs273_0) + ); + defparam plm_fsm_N_47404_i_0_o3_0.INIT = 4'h1; + LUT2 plm_fsm_N_47404_i_0_o3_0 ( + .I0(plm_rx0_lane_num[0]), + .I1(plm_rx0_lane_num[6]), + .O(plm_fsm_N_47404_i_0_o3_0_1665) + ); + defparam plm_fsm_fsm_vector_reg_123_link_pad_8_1.INIT = 4'h8; + LUT2 plm_fsm_fsm_vector_reg_123_link_pad_8_1 ( + .I0(plm_rx1_lane_pad), + .I1(plm_rx3_lane_pad), + .O(plm_fsm_reg_123_link_pad_8_1) + ); + defparam plm_fsm_N_11062_i.INIT = 4'hE; + LUT2 plm_fsm_N_11062_i ( + .I0(plm_fsm_reg_state_10__1792), + .I1(plm_fsm_reg_state_15__1790), + .O(plm_N_11062_i) + ); + defparam plm_fsm_xl_lanenum_changes_N_61243_i.INIT = 4'hE; + LUT2 plm_fsm_xl_lanenum_changes_N_61243_i ( + .I0(plm_fsm_reg_state_22__1785), + .I1(plm_fsm_reg_state_24__1783), + .O(plm_fsm_N_61243_i) + ); + defparam plm_fsm_lanenum_changes_N_61244_i.INIT = 4'hE; + LUT2 plm_fsm_lanenum_changes_N_61244_i ( + .I0(plm_fsm_reg_state_6__1778), + .I1(plm_fsm_reg_state_8__1776), + .O(plm_fsm_N_61244_i) + ); + defparam plm_fsm_l0_exit_reason_0_0_0_a2.INIT = 8'h0E; + LUT3 plm_fsm_l0_exit_reason_0_0_0_a2 ( + .I0(plm_reg_ts2_1_2), + .I1(plm_reg_ts1_1_2), + .I2(cmmp_negotiated_width[0]), + .O(plm_fsm_N_57532) + ); + defparam plm_fsm_fsm_vector_reg_send_command_28_0_a2_0_a2_1_0_.INIT = 8'h01; + LUT3 plm_fsm_fsm_vector_reg_send_command_28_0_a2_0_a2_1_0_ ( + .I0(plm_fsm_reg_state_0__1782), + .I1(plm_fsm_reg_state_11__608), + .I2(plm_fsm_reg_state_16__603), + .O(plm_fsm_reg_send_command_28_1[0]) + ); + defparam plm_fsm_un1_reg_state_22_i_0_0_0_o3.INIT = 8'h01; + LUT3 plm_fsm_un1_reg_state_22_i_0_0_0_o3 ( + .I0(plm_fsm_reg_state_11__608), + .I1(plm_fsm_reg_state_16__603), + .I2(plm_link_ctrl[0]), + .O(plm_fsm_N_56470_i) + ); + defparam plm_fsm_reg_state_1_sqmuxa_4_i_0_o2.INIT = 8'hC4; + LUT3 plm_fsm_reg_state_1_sqmuxa_4_i_0_o2 ( + .I0(NlwRenamedSig_OI_cfg_lcommand_7_), + .I1(plm_fsm_rl_cntrout0), + .I2(plm_fsm_rl_extdout), + .O(plm_fsm_N_14931_i) + ); + defparam plm_fsm_fsm_vector_reg_state_141_0_0_1_iv_i_0_0_a3_0_5_10_.INIT = 4'h8; + LUT2 plm_fsm_fsm_vector_reg_state_141_0_0_1_iv_i_0_0_a3_0_5_10_ ( + .I0(plm_fsm_N_37129_7), + .I1(plm_fsm_good_by4_1), + .O(plm_fsm_N_11035_2) + ); + defparam plm_fsm_fsm_vector_un1_rx0_lane_pad.INIT = 8'h08; + LUT3 plm_fsm_fsm_vector_un1_rx0_lane_pad ( + .I0(plm_reg_ts1_1), + .I1(plm_rx0_lane_pad), + .I2(plm_rx0_link_pad), + .O(plm_fsm_un1_rx0_lane_pad) + ); + defparam plm_fsm_fsm_vector_un1_rx0_lane_pad_1_0_o3.INIT = 4'h2; + LUT2 plm_fsm_fsm_vector_un1_rx0_lane_pad_1_0_o3 ( + .I0(plm_fsm_reg_rx_clear_cs_0_sqmuxa_10_2), + .I1(plm_rx0_link_pad), + .O(plm_fsm_N_36833_i) + ); + defparam plm_fsm_reg_rx_clear_cs_1_sqmuxa.INIT = 4'h8; + LUT2 plm_fsm_reg_rx_clear_cs_1_sqmuxa ( + .I0(plm_fsm_rc_cntrout_ts1_0), + .I1(plm_fsm_reg_rx_clear_cs_1_sqmuxa_1_0_1752), + .O(plm_fsm_reg_rx_clear_cs_1_sqmuxa_1727) + ); + defparam plm_fsm_fsm_vector_un1_rc_cntrout_ts1_0_1.INIT = 16'h0001; + LUT4 plm_fsm_fsm_vector_un1_rc_cntrout_ts1_0_1 ( + .I0(plm_fsm_rc_cntrout_ts1_0), + .I1(plm_fsm_rc_cntrout_ts1_1), + .I2(plm_fsm_rc_cntrout_ts1_2), + .I3(plm_fsm_rc_cntrout_ts1_3), + .O(plm_fsm_un1_rc_cntrout_ts1_0_1_i) + ); + defparam plm_fsm_fsm_vector_N_36977_1_i_0_0_o3.INIT = 16'h0001; + LUT4 plm_fsm_fsm_vector_N_36977_1_i_0_0_o3 ( + .I0(plm_rx0_ts1_c), + .I1(plm_rx1_ts1_c), + .I2(plm_rx2_ts1_c), + .I3(plm_rx3_ts1_c), + .O(plm_fsm_N_55942_i) + ); + defparam plm_fsm_reg_rx_clear_cs_2_sqmuxa_10_1_i_0_i_a3_i_o2.INIT = 16'h0001; + LUT4 plm_fsm_reg_rx_clear_cs_2_sqmuxa_10_1_i_0_i_a3_i_o2 ( + .I0(plm_rx0_ts2_c), + .I1(plm_rx1_ts2_c), + .I2(plm_rx2_ts2_c), + .I3(plm_rx3_ts2_c), + .O(plm_fsm_N_55883_i) + ); + defparam plm_fsm_un1_reg_state_15_i_0_0_o2.INIT = 8'h01; + LUT3 plm_fsm_un1_reg_state_15_i_0_0_o2 ( + .I0(plm_fsm_reg_state_0__1782), + .I1(plm_fsm_reg_state_1__425), + .I2(plm_fsm_reg_state_2__599), + .O(plm_fsm_N_56931_i) + ); + defparam plm_fsm_reg_state_0_sqmuxa_8_i_0_o2.INIT = 8'h80; + LUT3 plm_fsm_reg_state_0_sqmuxa_8_i_0_o2 ( + .I0(plm_fsm_rl_cntrout1), + .I1(plm_fsm_rl_cntrout2), + .I2(plm_fsm_rl_cntrout3), + .O(plm_fsm_N_38077_i) + ); + defparam plm_fsm_hr_restart_0_0_0_a2_1.INIT = 8'h40; + LUT3 plm_fsm_hr_restart_0_0_0_a2_1 ( + .I0(cmmp_negotiated_width[0]), + .I1(plm_rx2_linkctrl_0_), + .I2(plm_rx2_ts1_c), + .O(plm_fsm_N_57538) + ); + defparam plm_fsm_fsm_vector_reg_send_command_28_i_a2_1_1_.INIT = 8'h01; + LUT3 plm_fsm_fsm_vector_reg_send_command_28_i_a2_1_1_ ( + .I0(plm_fsm_reg_state_2__599), + .I1(plm_fsm_reg_state_9__1795), + .I2(plm_fsm_reg_state_10__1792), + .O(plm_fsm_N_3265_1_0) + ); + defparam plm_fsm_fsm_vector_reg_state67.INIT = 16'h0001; + LUT4 plm_fsm_fsm_vector_reg_state67 ( + .I0(plm_fsm_pa_cntrout0), + .I1(plm_fsm_pa_cntrout1), + .I2(plm_fsm_pa_cntrout2), + .I3(plm_fsm_pa_cntrout3), + .O(plm_fsm_N_11053) + ); + defparam plm_fsm_fsm_vector_reg_state_141_0_0_i_0_0_o3_1_.INIT = 16'h8000; + LUT4 plm_fsm_fsm_vector_reg_state_141_0_0_i_0_0_o3_1_ ( + .I0(plm_fsm_pa_cntrout0), + .I1(plm_fsm_pa_cntrout1), + .I2(plm_fsm_pa_cntrout2), + .I3(plm_fsm_pa_cntrout3), + .O(plm_fsm_N_56356_i) + ); + defparam plm_fsm_un1_reg_state_4.INIT = 8'h01; + LUT3 plm_fsm_un1_reg_state_4 ( + .I0(plm_fsm_reg_state_18__1789), + .I1(plm_fsm_reg_state_19__1788), + .I2(plm_fsm_reg_state_20__1787), + .O(plm_fsm_un1_reg_state_4_i) + ); + defparam plm_fsm_un2_ri_reconfig_0.INIT = 16'h0777; + LUT4 plm_fsm_un2_ri_reconfig_0 ( + .I0(plm_rx2_lane_pad), + .I1(plm_rx2_ts1_c), + .I2(plm_rx3_lane_pad), + .I3(plm_rx3_ts1_c), + .O(plm_fsm_un2_ri_reconfig_0_1666) + ); + defparam plm_fsm_N_47404_i_0_o3_4.INIT = 16'h0001; + LUT4 plm_fsm_N_47404_i_0_o3_4 ( + .I0(plm_rx0_lane_num[1]), + .I1(plm_rx0_lane_num[2]), + .I2(plm_rx0_lane_num[3]), + .I3(plm_rx0_lane_num[4]), + .O(plm_fsm_N_47404_i_0_o3_4_1664) + ); + defparam plm_fsm_un3_xl_clw2_newv_NE_0.INIT = 16'h8421; + LUT4 plm_fsm_un3_xl_clw2_newv_NE_0 ( + .I0(plm_fsm_reg_xl_rx2_old[4]), + .I1(plm_fsm_reg_xl_rx2_old[5]), + .I2(plm_rx2_lane_num[4]), + .I3(plm_rx2_lane_num[5]), + .O(plm_fsm_un3_xl_clw2_newv_NE_0_1698) + ); + defparam plm_fsm_un3_xl_clw2_newv_NE_1.INIT = 16'h8421; + LUT4 plm_fsm_un3_xl_clw2_newv_NE_1 ( + .I0(plm_fsm_reg_xl_rx2_old[2]), + .I1(plm_fsm_reg_xl_rx2_old[3]), + .I2(plm_rx2_lane_num[2]), + .I3(plm_rx2_lane_num[3]), + .O(plm_fsm_un3_xl_clw2_newv_NE_1_1697) + ); + defparam plm_fsm_un3_xl_clw2_newv_NE_2.INIT = 16'h8421; + LUT4 plm_fsm_un3_xl_clw2_newv_NE_2 ( + .I0(plm_fsm_reg_xl_rx2_old[1]), + .I1(plm_fsm_reg_xl_rx2_old[7]), + .I2(plm_rx2_lane_num[1]), + .I3(plm_rx2_lane_num[7]), + .O(plm_fsm_un3_xl_clw2_newv_NE_2_1696) + ); + defparam plm_fsm_un3_xl_clw1_newv_NE_0.INIT = 16'h8421; + LUT4 plm_fsm_un3_xl_clw1_newv_NE_0 ( + .I0(plm_fsm_reg_xl_rx1_old[1]), + .I1(plm_fsm_reg_xl_rx1_old[2]), + .I2(plm_rx1_lane_num[1]), + .I3(plm_rx1_lane_num[2]), + .O(plm_fsm_un3_xl_clw1_newv_NE_0_1767) + ); + defparam plm_fsm_un3_xl_clw1_newv_NE_1.INIT = 16'h8421; + LUT4 plm_fsm_un3_xl_clw1_newv_NE_1 ( + .I0(plm_fsm_reg_xl_rx1_old[0]), + .I1(plm_fsm_reg_xl_rx1_old[7]), + .I2(plm_rx1_lane_num[0]), + .I3(plm_rx1_lane_num[7]), + .O(plm_fsm_un3_xl_clw1_newv_NE_1_1769) + ); + defparam plm_fsm_un3_xl_clw1_newv_NE_2.INIT = 16'h8421; + LUT4 plm_fsm_un3_xl_clw1_newv_NE_2 ( + .I0(plm_fsm_reg_xl_rx1_old[3]), + .I1(plm_fsm_reg_xl_rx1_old[5]), + .I2(plm_rx1_lane_num[3]), + .I3(plm_rx1_lane_num[5]), + .O(plm_fsm_un3_xl_clw1_newv_NE_2_1768) + ); + defparam plm_fsm_un3_xl_clw1_newv_NE_3.INIT = 16'h8421; + LUT4 plm_fsm_un3_xl_clw1_newv_NE_3 ( + .I0(plm_fsm_reg_xl_rx1_old[4]), + .I1(plm_fsm_reg_xl_rx1_old[6]), + .I2(plm_rx1_lane_num[4]), + .I3(plm_rx1_lane_num[6]), + .O(plm_fsm_un3_xl_clw1_newv_NE_3_1766) + ); + defparam plm_fsm_un3_xl_clw3_newv_NE_0.INIT = 16'h8421; + LUT4 plm_fsm_un3_xl_clw3_newv_NE_0 ( + .I0(plm_fsm_reg_xl_rx3_old[3]), + .I1(plm_fsm_reg_xl_rx3_old[4]), + .I2(plm_rx3_lane_num[3]), + .I3(plm_rx3_lane_num[4]), + .O(plm_fsm_un3_xl_clw3_newv_NE_0_1762) + ); + defparam plm_fsm_un3_xl_clw3_newv_NE_1.INIT = 16'h8421; + LUT4 plm_fsm_un3_xl_clw3_newv_NE_1 ( + .I0(plm_fsm_reg_xl_rx3_old[0]), + .I1(plm_fsm_reg_xl_rx3_old[1]), + .I2(plm_rx3_lane_num[0]), + .I3(plm_rx3_lane_num[1]), + .O(plm_fsm_un3_xl_clw3_newv_NE_1_1761) + ); + defparam plm_fsm_un3_xl_clw3_newv_NE_2.INIT = 16'h8421; + LUT4 plm_fsm_un3_xl_clw3_newv_NE_2 ( + .I0(plm_fsm_reg_xl_rx3_old[5]), + .I1(plm_fsm_reg_xl_rx3_old[6]), + .I2(plm_rx3_lane_num[5]), + .I3(plm_rx3_lane_num[6]), + .O(plm_fsm_un3_xl_clw3_newv_NE_2_1764) + ); + defparam plm_fsm_un3_xl_clw3_newv_NE_3.INIT = 16'h8421; + LUT4 plm_fsm_un3_xl_clw3_newv_NE_3 ( + .I0(plm_fsm_reg_xl_rx3_old[2]), + .I1(plm_fsm_reg_xl_rx3_old[7]), + .I2(plm_rx3_lane_num[2]), + .I3(plm_rx3_lane_num[7]), + .O(plm_fsm_un3_xl_clw3_newv_NE_3_1763) + ); + defparam plm_fsm_un3_clw0_newv_NE_0.INIT = 16'h8421; + LUT4 plm_fsm_un3_clw0_newv_NE_0 ( + .I0(plm_fsm_reg_rx0_old[6]), + .I1(plm_fsm_reg_rx0_old[7]), + .I2(plm_rx0_lane_num[6]), + .I3(plm_rx0_lane_num[7]), + .O(plm_fsm_un3_clw0_newv_NE_0_1713) + ); + defparam plm_fsm_un3_clw0_newv_NE_1.INIT = 16'h8421; + LUT4 plm_fsm_un3_clw0_newv_NE_1 ( + .I0(plm_fsm_reg_rx0_old[4]), + .I1(plm_fsm_reg_rx0_old[5]), + .I2(plm_rx0_lane_num[4]), + .I3(plm_rx0_lane_num[5]), + .O(plm_fsm_un3_clw0_newv_NE_1_1670) + ); + defparam plm_fsm_un3_clw0_newv_NE_3.INIT = 16'h8421; + LUT4_L plm_fsm_un3_clw0_newv_NE_3 ( + .I0(plm_fsm_reg_rx0_old[0]), + .I1(plm_fsm_reg_rx0_old[3]), + .I2(plm_rx0_lane_num[0]), + .I3(plm_rx0_lane_num[3]), + .LO(plm_fsm_un3_clw0_newv_NE_3_1669) + ); + defparam plm_fsm_un3_xl_clw0_newv_NE_0.INIT = 16'h8421; + LUT4 plm_fsm_un3_xl_clw0_newv_NE_0 ( + .I0(plm_fsm_reg_xl_rx0_old[6]), + .I1(plm_fsm_reg_xl_rx0_old[7]), + .I2(plm_rx0_lane_num[6]), + .I3(plm_rx0_lane_num[7]), + .O(plm_fsm_un3_xl_clw0_newv_NE_0_1717) + ); + defparam plm_fsm_un3_xl_clw0_newv_NE_1.INIT = 16'h8421; + LUT4 plm_fsm_un3_xl_clw0_newv_NE_1 ( + .I0(plm_fsm_reg_xl_rx0_old[4]), + .I1(plm_fsm_reg_xl_rx0_old[5]), + .I2(plm_rx0_lane_num[4]), + .I3(plm_rx0_lane_num[5]), + .O(plm_fsm_un3_xl_clw0_newv_NE_1_1672) + ); + defparam plm_fsm_un3_xl_clw0_newv_NE_3.INIT = 16'h8421; + LUT4_L plm_fsm_un3_xl_clw0_newv_NE_3 ( + .I0(plm_fsm_reg_xl_rx0_old[0]), + .I1(plm_fsm_reg_xl_rx0_old[3]), + .I2(plm_rx0_lane_num[0]), + .I3(plm_rx0_lane_num[3]), + .LO(plm_fsm_un3_xl_clw0_newv_NE_3_1671) + ); + defparam plm_fsm_un3_clw3_newv_NE_0.INIT = 16'h8421; + LUT4 plm_fsm_un3_clw3_newv_NE_0 ( + .I0(plm_fsm_reg_rx3_old[3]), + .I1(plm_fsm_reg_rx3_old[4]), + .I2(plm_rx3_lane_num[3]), + .I3(plm_rx3_lane_num[4]), + .O(plm_fsm_un3_clw3_newv_NE_0_1701) + ); + defparam plm_fsm_un3_clw3_newv_NE_1.INIT = 16'h8421; + LUT4 plm_fsm_un3_clw3_newv_NE_1 ( + .I0(plm_fsm_reg_rx3_old[0]), + .I1(plm_fsm_reg_rx3_old[1]), + .I2(plm_rx3_lane_num[0]), + .I3(plm_rx3_lane_num[1]), + .O(plm_fsm_un3_clw3_newv_NE_1_1700) + ); + defparam plm_fsm_un3_clw3_newv_NE_2.INIT = 16'h8421; + LUT4 plm_fsm_un3_clw3_newv_NE_2 ( + .I0(plm_fsm_reg_rx3_old[5]), + .I1(plm_fsm_reg_rx3_old[6]), + .I2(plm_rx3_lane_num[5]), + .I3(plm_rx3_lane_num[6]), + .O(plm_fsm_un3_clw3_newv_NE_2_1699) + ); + defparam plm_fsm_un3_clw3_newv_NE_3.INIT = 16'h8421; + LUT4_L plm_fsm_un3_clw3_newv_NE_3 ( + .I0(plm_fsm_reg_rx3_old[2]), + .I1(plm_fsm_reg_rx3_old[7]), + .I2(plm_rx3_lane_num[2]), + .I3(plm_rx3_lane_num[7]), + .LO(plm_fsm_un3_clw3_newv_NE_3_1673) + ); + defparam plm_fsm_un1_linklanematch0_NE_0.INIT = 16'h8421; + LUT4 plm_fsm_un1_linklanematch0_NE_0 ( + .I0(plm_rx0_link_num[3]), + .I1(plm_rx0_link_num[7]), + .I2(plm_tx1_link_num[3]), + .I3(plm_tx1_link_num[7]), + .O(plm_fsm_un1_linklanematch0_NE_0_1693) + ); + defparam plm_fsm_un1_linklanematch0_NE_1.INIT = 16'h8421; + LUT4 plm_fsm_un1_linklanematch0_NE_1 ( + .I0(plm_rx0_link_num[5]), + .I1(plm_rx0_link_num[6]), + .I2(plm_tx1_link_num[5]), + .I3(plm_tx1_link_num[6]), + .O(plm_fsm_un1_linklanematch0_NE_1_1692) + ); + defparam plm_fsm_un1_linklanematch0_NE_2.INIT = 16'h8421; + LUT4 plm_fsm_un1_linklanematch0_NE_2 ( + .I0(plm_rx0_link_num[0]), + .I1(plm_rx0_link_num[2]), + .I2(plm_tx1_link_num[0]), + .I3(plm_tx1_link_num[2]), + .O(plm_fsm_un1_linklanematch0_NE_2_1691) + ); + defparam plm_fsm_un1_linklanematch0_NE_3.INIT = 16'h8421; + LUT4 plm_fsm_un1_linklanematch0_NE_3 ( + .I0(plm_rx0_link_num[1]), + .I1(plm_rx0_link_num[4]), + .I2(plm_tx1_link_num[1]), + .I3(plm_tx1_link_num[4]), + .O(plm_fsm_un1_linklanematch0_NE_3_1690) + ); + defparam plm_fsm_un2_ruined_by4_NE_0.INIT = 16'h8421; + LUT4 plm_fsm_un2_ruined_by4_NE_0 ( + .I0(plm_rx1_link_num[2]), + .I1(plm_rx1_link_num[7]), + .I2(plm_tx1_link_num[2]), + .I3(plm_tx1_link_num[7]), + .O(plm_fsm_un2_ruined_by4_NE_0_1681) + ); + defparam plm_fsm_un2_ruined_by4_NE_1.INIT = 16'h8421; + LUT4 plm_fsm_un2_ruined_by4_NE_1 ( + .I0(plm_rx1_link_num[5]), + .I1(plm_rx1_link_num[6]), + .I2(plm_tx1_link_num[5]), + .I3(plm_tx1_link_num[6]), + .O(plm_fsm_un2_ruined_by4_NE_1_1680) + ); + defparam plm_fsm_un2_ruined_by4_NE_2.INIT = 16'h8421; + LUT4 plm_fsm_un2_ruined_by4_NE_2 ( + .I0(plm_rx1_link_num[0]), + .I1(plm_rx1_link_num[3]), + .I2(plm_tx1_link_num[0]), + .I3(plm_tx1_link_num[3]), + .O(plm_fsm_un2_ruined_by4_NE_2_1679) + ); + defparam plm_fsm_un2_ruined_by4_NE_3.INIT = 16'h8421; + LUT4 plm_fsm_un2_ruined_by4_NE_3 ( + .I0(plm_rx1_link_num[1]), + .I1(plm_rx1_link_num[4]), + .I2(plm_tx1_link_num[1]), + .I3(plm_tx1_link_num[4]), + .O(plm_fsm_un2_ruined_by4_NE_3_1678) + ); + defparam plm_fsm_un4_ruined_by4_NE_0.INIT = 16'h8421; + LUT4 plm_fsm_un4_ruined_by4_NE_0 ( + .I0(plm_rx2_link_num[2]), + .I1(plm_rx2_link_num[7]), + .I2(plm_tx1_link_num[2]), + .I3(plm_tx1_link_num[7]), + .O(plm_fsm_un4_ruined_by4_NE_0_1685) + ); + defparam plm_fsm_un4_ruined_by4_NE_1.INIT = 16'h8421; + LUT4 plm_fsm_un4_ruined_by4_NE_1 ( + .I0(plm_rx2_link_num[5]), + .I1(plm_rx2_link_num[6]), + .I2(plm_tx1_link_num[5]), + .I3(plm_tx1_link_num[6]), + .O(plm_fsm_un4_ruined_by4_NE_1_1684) + ); + defparam plm_fsm_un4_ruined_by4_NE_2.INIT = 16'h8421; + LUT4 plm_fsm_un4_ruined_by4_NE_2 ( + .I0(plm_rx2_link_num[0]), + .I1(plm_rx2_link_num[3]), + .I2(plm_tx1_link_num[0]), + .I3(plm_tx1_link_num[3]), + .O(plm_fsm_un4_ruined_by4_NE_2_1683) + ); + defparam plm_fsm_un4_ruined_by4_NE_3.INIT = 16'h8421; + LUT4 plm_fsm_un4_ruined_by4_NE_3 ( + .I0(plm_rx2_link_num[1]), + .I1(plm_rx2_link_num[4]), + .I2(plm_tx1_link_num[1]), + .I3(plm_tx1_link_num[4]), + .O(plm_fsm_un4_ruined_by4_NE_3_1682) + ); + defparam plm_fsm_un6_ruined_by4_NE_0.INIT = 16'h8421; + LUT4 plm_fsm_un6_ruined_by4_NE_0 ( + .I0(plm_rx3_link_num[2]), + .I1(plm_rx3_link_num[7]), + .I2(plm_tx1_link_num[2]), + .I3(plm_tx1_link_num[7]), + .O(plm_fsm_un6_ruined_by4_NE_0_1689) + ); + defparam plm_fsm_un6_ruined_by4_NE_1.INIT = 16'h8421; + LUT4 plm_fsm_un6_ruined_by4_NE_1 ( + .I0(plm_rx3_link_num[5]), + .I1(plm_rx3_link_num[6]), + .I2(plm_tx1_link_num[5]), + .I3(plm_tx1_link_num[6]), + .O(plm_fsm_un6_ruined_by4_NE_1_1688) + ); + defparam plm_fsm_un6_ruined_by4_NE_2.INIT = 16'h8421; + LUT4 plm_fsm_un6_ruined_by4_NE_2 ( + .I0(plm_rx3_link_num[0]), + .I1(plm_rx3_link_num[3]), + .I2(plm_tx1_link_num[0]), + .I3(plm_tx1_link_num[3]), + .O(plm_fsm_un6_ruined_by4_NE_2_1687) + ); + defparam plm_fsm_un6_ruined_by4_NE_3.INIT = 16'h8421; + LUT4 plm_fsm_un6_ruined_by4_NE_3 ( + .I0(plm_rx3_link_num[1]), + .I1(plm_rx3_link_num[4]), + .I2(plm_tx1_link_num[1]), + .I3(plm_tx1_link_num[4]), + .O(plm_fsm_un6_ruined_by4_NE_3_1686) + ); + defparam plm_fsm_un3_clw2_newv_NE_0.INIT = 16'h8421; + LUT4 plm_fsm_un3_clw2_newv_NE_0 ( + .I0(plm_fsm_reg_rx2_old[4]), + .I1(plm_fsm_reg_rx2_old[5]), + .I2(plm_rx2_lane_num[4]), + .I3(plm_rx2_lane_num[5]), + .O(plm_fsm_un3_clw2_newv_NE_0_1710) + ); + defparam plm_fsm_un3_clw2_newv_NE_1.INIT = 16'h8421; + LUT4 plm_fsm_un3_clw2_newv_NE_1 ( + .I0(plm_fsm_reg_rx2_old[2]), + .I1(plm_fsm_reg_rx2_old[3]), + .I2(plm_rx2_lane_num[2]), + .I3(plm_rx2_lane_num[3]), + .O(plm_fsm_un3_clw2_newv_NE_1_1709) + ); + defparam plm_fsm_un3_clw2_newv_NE_2.INIT = 16'h8421; + LUT4 plm_fsm_un3_clw2_newv_NE_2 ( + .I0(plm_fsm_reg_rx2_old[1]), + .I1(plm_fsm_reg_rx2_old[7]), + .I2(plm_rx2_lane_num[1]), + .I3(plm_rx2_lane_num[7]), + .O(plm_fsm_un3_clw2_newv_NE_2_1708) + ); + defparam plm_fsm_un3_clw2_newv_NE_3.INIT = 16'h8421; + LUT4_L plm_fsm_un3_clw2_newv_NE_3 ( + .I0(plm_fsm_reg_rx2_old[0]), + .I1(plm_fsm_reg_rx2_old[6]), + .I2(plm_rx2_lane_num[0]), + .I3(plm_rx2_lane_num[6]), + .LO(plm_fsm_un3_clw2_newv_NE_3_1674) + ); + defparam plm_fsm_un3_clw1_newv_NE_0.INIT = 16'h8421; + LUT4 plm_fsm_un3_clw1_newv_NE_0 ( + .I0(plm_fsm_reg_rx1_old[1]), + .I1(plm_fsm_reg_rx1_old[2]), + .I2(plm_rx1_lane_num[1]), + .I3(plm_rx1_lane_num[2]), + .O(plm_fsm_un3_clw1_newv_NE_0_1706) + ); + defparam plm_fsm_un3_clw1_newv_NE_1.INIT = 16'h8421; + LUT4 plm_fsm_un3_clw1_newv_NE_1 ( + .I0(plm_fsm_reg_rx1_old[0]), + .I1(plm_fsm_reg_rx1_old[7]), + .I2(plm_rx1_lane_num[0]), + .I3(plm_rx1_lane_num[7]), + .O(plm_fsm_un3_clw1_newv_NE_1_1705) + ); + defparam plm_fsm_un3_clw1_newv_NE_2.INIT = 16'h8421; + LUT4 plm_fsm_un3_clw1_newv_NE_2 ( + .I0(plm_fsm_reg_rx1_old[3]), + .I1(plm_fsm_reg_rx1_old[5]), + .I2(plm_rx1_lane_num[3]), + .I3(plm_rx1_lane_num[5]), + .O(plm_fsm_un3_clw1_newv_NE_2_1704) + ); + defparam plm_fsm_un3_clw1_newv_NE_3.INIT = 16'h8421; + LUT4_L plm_fsm_un3_clw1_newv_NE_3 ( + .I0(plm_fsm_reg_rx1_old[4]), + .I1(plm_fsm_reg_rx1_old[6]), + .I2(plm_rx1_lane_num[4]), + .I3(plm_rx1_lane_num[6]), + .LO(plm_fsm_un3_clw1_newv_NE_3_1675) + ); + defparam plm_fsm_un1_reg_state_18_i_0_0_0_2_1_1.INIT = 8'h01; + LUT3 plm_fsm_un1_reg_state_18_i_0_0_0_2_1_1 ( + .I0(plm_fsm_reg_state_7__1777), + .I1(plm_fsm_reg_state_23__1784), + .I2(plm_link_l0), + .O(plm_fsm_un1_reg_state_18_i_0_0_0_2_1_1_1667) + ); + defparam plm_fsm_reg_rx_clear_cs_0_sqmuxa_6_0_0_a2_i.INIT = 4'h4; + LUT2 plm_fsm_reg_rx_clear_cs_0_sqmuxa_6_0_0_a2_i ( + .I0(plm_fsm_N_55942_i), + .I1(plm_fsm_reg_state_24__1783), + .O(plm_fsm_N_36528_i) + ); + defparam plm_fsm_reg_state_1_sqmuxa_2.INIT = 8'h80; + LUT3 plm_fsm_reg_state_1_sqmuxa_2 ( + .I0(plm_reg_ts1_1), + .I1(N_56496_i), + .I2(plm_fsm_reg_state_18__1789), + .O(plm_fsm_reg_state_1_sqmuxa_2_1745) + ); + defparam plm_fsm_reg_state_4_sqmuxa_2_1.INIT = 4'h4; + LUT2 plm_fsm_reg_state_4_sqmuxa_2_1 ( + .I0(plm_fsm_un1_rx0_lane_pad), + .I1(plm_fsm_reg_state_3__1781), + .O(plm_fsm_reg_state_4_sqmuxa_2_1_1724) + ); + defparam plm_fsm_un1_reg_state_15_i_a2.INIT = 4'h4; + LUT2 plm_fsm_un1_reg_state_15_i_a2 ( + .I0(plm_fsm_N_36833_i), + .I1(plm_fsm_reg_state_4__1780), + .O(plm_fsm_reg_rx_clear_cs_4_sqmuxa_1_0) + ); + defparam plm_fsm_reg_rx_clear_cs_1_sqmuxa_5.INIT = 4'h8; + LUT2 plm_fsm_reg_rx_clear_cs_1_sqmuxa_5 ( + .I0(plm_fsm_N_36833_i), + .I1(plm_fsm_reg_state_4__1780), + .O(plm_fsm_reg_rx_clear_cs_1_sqmuxa_5_1757) + ); + defparam plm_fsm_fsm_vector_reg_state_141_0_0_1_iv_i_0_0_a3_3_10_.INIT = 4'h4; + LUT2 plm_fsm_fsm_vector_reg_state_141_0_0_1_iv_i_0_0_a3_3_10_ ( + .I0(plm_fsm_N_55883_i), + .I1(plm_fsm_reg_state_8__1776), + .O(plm_fsm_N_61331) + ); + defparam plm_fsm_un1_reg_state_22_i_0_0_0_o2.INIT = 4'h2; + LUT2 plm_fsm_un1_reg_state_22_i_0_0_0_o2 ( + .I0(plm_fsm_N_56470_i), + .I1(plm_fsm_reg_state_8__1776), + .O(plm_fsm_N_56480_i) + ); + defparam plm_fsm_fsm_vector_N_36977_1_i_0_0_o2.INIT = 4'h8; + LUT2 plm_fsm_fsm_vector_N_36977_1_i_0_0_o2 ( + .I0(plm_fsm_N_55883_i), + .I1(plm_fsm_reg_state_8__1776), + .O(plm_fsm_N_57049_i) + ); + defparam plm_fsm_un8_cc_noscramb_i_0_0_a2.INIT = 16'h1555; + LUT4 plm_fsm_un8_cc_noscramb_i_0_0_a2 ( + .I0(cmmp_negotiated_width[0]), + .I1(plm_rx1_linkctrl_3_), + .I2(plm_rx2_linkctrl_3_), + .I3(plm_rx3_linkctrl_3_), + .O(plm_fsm_N_58729) + ); + defparam plm_fsm_fsm_vector_reg_state_141_0_0_1_iv_i_0_i_a3_i_a2_2_7_.INIT = 4'h8; + LUT2 plm_fsm_fsm_vector_reg_state_141_0_0_1_iv_i_0_i_a3_i_a2_2_7_ ( + .I0(plm_fsm_N_55883_i), + .I1(plm_fsm_reg_state_7__1777), + .O(plm_fsm_N_60908_2) + ); + defparam plm_fsm_fsm_vector_reg_noscramble54_0_o3_i_o3.INIT = 16'h8000; + LUT4 plm_fsm_fsm_vector_reg_noscramble54_0_o3_i_o3 ( + .I0(plm_chb_done), + .I1(plm_fsm_cc_cntrout2), + .I2(plm_fsm_cc_cntrout3), + .I3(plm_fsm_reg_noscramble54_0_o3_i_o3_1), + .O(plm_fsm_N_56359_i) + ); + defparam plm_fsm_N_47404_i_0_o3.INIT = 16'h0008; + LUT4 plm_fsm_N_47404_i_0_o3 ( + .I0(plm_fsm_N_47404_i_0_o3_0_1665), + .I1(plm_fsm_N_47404_i_0_o3_4_1664), + .I2(plm_rx0_lane_num[5]), + .I3(plm_rx0_lane_num[7]), + .O(N_55989_i) + ); + defparam plm_fsm_un2_ri_reconfig.INIT = 16'h0444; + LUT4 plm_fsm_un2_ri_reconfig ( + .I0(plm_fsm_reg_rx_clear_cs_0_sqmuxa_10_2), + .I1(plm_fsm_un2_ri_reconfig_0_1666), + .I2(plm_rx1_lane_pad), + .I3(plm_rx1_ts1_c), + .O(plm_fsm_N_11044) + ); + defparam plm_fsm_un1_reg_state_18_i_0_0_0_2_1.INIT = 8'h20; + LUT3 plm_fsm_un1_reg_state_18_i_0_0_0_2_1 ( + .I0(N_29556_i), + .I1(plm_fsm_reg_state_13__76), + .I2(plm_fsm_un1_reg_state_18_i_0_0_0_2_1_1_1667), + .O(plm_fsm_N_85520_1) + ); + defparam plm_fsm_fsm_vector_reg_123_link_pad_8.INIT = 16'h0800; + LUT4 plm_fsm_fsm_vector_reg_123_link_pad_8 ( + .I0(plm_fsm_reg_123_link_pad_8_1), + .I1(plm_fsm_good_by4_1), + .I2(plm_rx1_link_pad), + .I3(plm_rx2_lane_pad), + .O(plm_fsm_N_11048) + ); + defparam plm_fsm_fsm_vector_reg_rx_clear_cs273.INIT = 16'h8000; + LUT4 plm_fsm_fsm_vector_reg_rx_clear_cs273 ( + .I0(plm_chb_done), + .I1(plm_fsm_reg_rx_clear_cs273_0), + .I2(plm_fsm_rc_cntrout_ts2_0), + .I3(plm_fsm_rc_cntrout_ts2_1), + .O(plm_fsm_reg_rx_clear_cs273) + ); + defparam plm_fsm_hr_restart_0_0_0_1.INIT = 16'hABBB; + LUT4_L plm_fsm_hr_restart_0_0_0_1 ( + .I0(cmmp_negotiated_width[0]), + .I1(plm_fsm_hr_restart_0_0_0_a2_2_0_1668), + .I2(plm_rx3_linkctrl_0_), + .I3(plm_rx3_ts1_c), + .LO(plm_fsm_hr_restart_0_0_0_1_1695) + ); + defparam plm_fsm_un3_clw0_newv_NE_4.INIT = 8'h84; + LUT3 plm_fsm_un3_clw0_newv_NE_4 ( + .I0(plm_fsm_reg_rx0_old[8]), + .I1(plm_fsm_un3_clw0_newv_NE_3_1669), + .I2(plm_rx0_lane_pad), + .O(plm_fsm_un3_clw0_newv_NE_4_1712) + ); + defparam plm_fsm_un3_clw0_newv_NE_5.INIT = 16'h4010; + LUT4 plm_fsm_un3_clw0_newv_NE_5 ( + .I0(plm_fsm_N_56421_i_0), + .I1(plm_fsm_reg_rx0_old[2]), + .I2(plm_fsm_un3_clw0_newv_NE_1_1670), + .I3(plm_rx0_lane_num[2]), + .O(plm_fsm_un3_clw0_newv_NE_5_1711) + ); + defparam plm_fsm_un3_xl_clw0_newv_NE_4.INIT = 8'h84; + LUT3 plm_fsm_un3_xl_clw0_newv_NE_4 ( + .I0(plm_fsm_reg_xl_rx0_old[8]), + .I1(plm_fsm_un3_xl_clw0_newv_NE_3_1671), + .I2(plm_rx0_lane_pad), + .O(plm_fsm_un3_xl_clw0_newv_NE_4_1716) + ); + defparam plm_fsm_un3_xl_clw0_newv_NE_5.INIT = 16'h4010; + LUT4 plm_fsm_un3_xl_clw0_newv_NE_5 ( + .I0(plm_fsm_N_56419_i_0), + .I1(plm_fsm_reg_xl_rx0_old[2]), + .I2(plm_fsm_un3_xl_clw0_newv_NE_1_1672), + .I3(plm_rx0_lane_num[2]), + .O(plm_fsm_un3_xl_clw0_newv_NE_5_1715) + ); + defparam plm_fsm_un3_clw3_newv_NE_4.INIT = 8'h84; + LUT3 plm_fsm_un3_clw3_newv_NE_4 ( + .I0(plm_fsm_reg_rx3_old[8]), + .I1(plm_fsm_un3_clw3_newv_NE_3_1673), + .I2(plm_rx3_lane_pad), + .O(plm_fsm_un3_clw3_newv_NE_4_1720) + ); + defparam plm_fsm_un3_clw2_newv_NE_4.INIT = 8'h84; + LUT3_L plm_fsm_un3_clw2_newv_NE_4 ( + .I0(plm_fsm_reg_rx2_old[8]), + .I1(plm_fsm_un3_clw2_newv_NE_3_1674), + .I2(plm_rx2_lane_pad), + .LO(plm_fsm_un3_clw2_newv_NE_4_1707) + ); + defparam plm_fsm_un3_clw1_newv_NE_4.INIT = 8'h84; + LUT3_L plm_fsm_un3_clw1_newv_NE_4 ( + .I0(plm_fsm_reg_rx1_old[8]), + .I1(plm_fsm_un3_clw1_newv_NE_3_1675), + .I2(plm_rx1_lane_pad), + .LO(plm_fsm_un3_clw1_newv_NE_4_1703) + ); + defparam plm_fsm_l0_exit_reason_0_0_0_1.INIT = 16'hFF10; + LUT4_L plm_fsm_l0_exit_reason_0_0_0_1 ( + .I0(plm_reg_ts2_1_0), + .I1(plm_reg_ts1_1_0), + .I2(plm_fsm_N_56214_i), + .I3(cmmp_negotiated_width[0]), + .LO(plm_fsm_l0_exit_reason_0_0_0_1_1694) + ); + defparam plm_fsm_un1_reg_state_15_i_0_0_0.INIT = 4'h2; + LUT2 plm_fsm_un1_reg_state_15_i_0_0_0 ( + .I0(plm_fsm_N_56931_i), + .I1(plm_fsm_reg_state_3__1781), + .O(plm_fsm_un1_reg_state_15_i_0_0_0_1756) + ); + defparam plm_fsm_fsm_vector_reg_rx_clear_cs_98_0_0_1_iv_0_1_0.INIT = 16'h0103; + LUT4 plm_fsm_fsm_vector_reg_rx_clear_cs_98_0_0_1_iv_0_1_0 ( + .I0(plm_fsm_cc_cntrout0), + .I1(plm_fsm_reg_rx_clear_cs_0_sqmuxa_3_1749), + .I2(plm_fsm_reg_state_0__1782), + .I3(plm_fsm_reg_state_9__1795), + .O(plm_fsm_reg_rx_clear_cs_98_0_0_1_iv_0_1) + ); + defparam plm_fsm_N_60883_i.INIT = 8'hF7; + LUT3 plm_fsm_N_60883_i ( + .I0(plm_fsm_N_45455_1), + .I1(plm_fsm_N_56931_i), + .I2(plm_fsm_reg_state_18__1789), + .O(plm_fsm_N_60883_i_1802) + ); + defparam plm_fsm_N_60679_i.INIT = 4'h7; + LUT2 plm_fsm_N_60679_i ( + .I0(N_56513_i), + .I1(plm_fsm_N_56931_i), + .O(plm_fsm_N_60679_i_1794) + ); + defparam plm_fsm_N_60884_i.INIT = 8'hFD; + LUT3 plm_fsm_N_60884_i ( + .I0(plm_fsm_N_56931_i), + .I1(plm_fsm_reg_state_11__608), + .I2(plm_link_ctrl[0]), + .O(plm_fsm_N_60884_i_1793) + ); + defparam plm_fsm_fsm_vector_reg_rx_clear_cs45_i_a2.INIT = 16'h8002; + LUT4 plm_fsm_fsm_vector_reg_rx_clear_cs45_i_a2 ( + .I0(plm_fsm_pc_cntrout0), + .I1(plm_fsm_pc_cntrout1), + .I2(plm_fsm_pc_cntrout2), + .I3(plm_fsm_pc_cntrout3), + .O(plm_fsm_N_36967) + ); + defparam plm_fsm_reg_rx_clear_cs_0_sqmuxa_5.INIT = 4'h8; + LUT2 plm_fsm_reg_rx_clear_cs_0_sqmuxa_5 ( + .I0(plm_fsm_reg_rx_clear_cs273), + .I1(plm_fsm_reg_state_15__1790), + .O(plm_fsm_reg_rx_clear_cs_0_sqmuxa_5_1748) + ); + defparam plm_fsm_reg_rx_clear_cs_1_sqmuxa_3.INIT = 8'h10; + LUT3 plm_fsm_reg_rx_clear_cs_1_sqmuxa_3 ( + .I0(plm_fsm_reg_rx_clear_cs273), + .I1(plm_fsm_un1_rc_cntrout_ts1_0_1_i), + .I2(plm_fsm_reg_state_15__1790), + .O(plm_fsm_reg_rx_clear_cs_1_sqmuxa_3_1726) + ); + defparam plm_fsm_ri_idle_data_0_i.INIT = 16'hC888; + LUT4 plm_fsm_ri_idle_data_0_i ( + .I0(cmmp_negotiated_width[0]), + .I1(plm_fsm_ri_cntrout0), + .I2(plm_fsm_ri_cntrout2), + .I3(plm_fsm_ri_idle_data_i_o3_0_1676), + .O(plm_fsm_ri_idle_data_0_i_1754) + ); + defparam plm_fsm_reg_state_1_sqmuxa_4_i_0.INIT = 8'h80; + LUT3 plm_fsm_reg_state_1_sqmuxa_4_i_0 ( + .I0(plm_fsm_N_14931_i), + .I1(cmmp_negotiated_width[0]), + .I2(plm_fsm_reg_state_13__76), + .O(plm_fsm_reg_state_1_sqmuxa_4_i_0_1753) + ); + defparam plm_fsm_fsm_vector_N_36977_1_i_0_0.INIT = 4'h4; + LUT2 plm_fsm_fsm_vector_N_36977_1_i_0_0 ( + .I0(plm_fsm_N_55942_i), + .I1(plm_fsm_N_57049_i), + .O(plm_fsm_N_36977_1_i_i) + ); + defparam plm_fsm_fsm_vector_reg_state694.INIT = 8'h0D; + LUT3 plm_fsm_fsm_vector_reg_state694 ( + .I0(plm_fsm_N_14931_i), + .I1(cfg_cfg_6102[505]), + .I2(plm_fsm_reg_rl_throw_a_bone_1800), + .O(plm_fsm_N_11041) + ); + defparam plm_fsm_ci_idle_data_i_0.INIT = 16'hC888; + LUT4 plm_fsm_ci_idle_data_i_0 ( + .I0(cmmp_negotiated_width[0]), + .I1(plm_fsm_ci_cntrout0), + .I2(plm_fsm_ci_cntrout2), + .I3(plm_fsm_ci_idle_data_i_o3_0_1677), + .O(plm_fsm_N_47001_i) + ); + defparam plm_fsm_un2_ruined_by4_NE.INIT = 16'h8000; + LUT4 plm_fsm_un2_ruined_by4_NE ( + .I0(plm_fsm_un2_ruined_by4_NE_0_1681), + .I1(plm_fsm_un2_ruined_by4_NE_1_1680), + .I2(plm_fsm_un2_ruined_by4_NE_2_1679), + .I3(plm_fsm_un2_ruined_by4_NE_3_1678), + .O(N_9903) + ); + defparam plm_fsm_un4_ruined_by4_NE.INIT = 16'h8000; + LUT4 plm_fsm_un4_ruined_by4_NE ( + .I0(plm_fsm_un4_ruined_by4_NE_0_1685), + .I1(plm_fsm_un4_ruined_by4_NE_1_1684), + .I2(plm_fsm_un4_ruined_by4_NE_2_1683), + .I3(plm_fsm_un4_ruined_by4_NE_3_1682), + .O(N_9902) + ); + defparam plm_fsm_un6_ruined_by4_NE.INIT = 16'h8000; + LUT4 plm_fsm_un6_ruined_by4_NE ( + .I0(plm_fsm_un6_ruined_by4_NE_0_1689), + .I1(plm_fsm_un6_ruined_by4_NE_1_1688), + .I2(plm_fsm_un6_ruined_by4_NE_2_1687), + .I3(plm_fsm_un6_ruined_by4_NE_3_1686), + .O(N_9901) + ); + defparam plm_fsm_un1_linklanematch0_NE.INIT = 16'h8000; + LUT4 plm_fsm_un1_linklanematch0_NE ( + .I0(plm_fsm_un1_linklanematch0_NE_0_1693), + .I1(plm_fsm_un1_linklanematch0_NE_1_1692), + .I2(plm_fsm_un1_linklanematch0_NE_2_1691), + .I3(plm_fsm_un1_linklanematch0_NE_3_1690), + .O(N_9900) + ); + defparam plm_fsm_un1_reg_state_8_0_a2.INIT = 16'h0008; + LUT4 plm_fsm_un1_reg_state_8_0_a2 ( + .I0(N_29556_i), + .I1(plm_fsm_N_56470_i), + .I2(plm_fsm_reg_state_13__76), + .I3(plm_link_l0), + .O(plm_fsm_un1_reg_state_8_0_a2_1798) + ); + defparam plm_fsm_reg_state_0_sqmuxa_8_i_0.INIT = 16'h0800; + LUT4 plm_fsm_reg_state_0_sqmuxa_8_i_0 ( + .I0(plm_fsm_N_14931_i), + .I1(plm_fsm_N_38077_i), + .I2(cmmp_negotiated_width[0]), + .I3(plm_fsm_reg_state_13__76), + .O(plm_fsm_reg_state_0_sqmuxa_8_i_0_1751) + ); + defparam plm_fsm_l0_exit_reason_0_0_0.INIT = 16'h0200; + LUT4 plm_fsm_l0_exit_reason_0_0_0 ( + .I0(plm_fsm_N_56187_i), + .I1(plm_fsm_N_57532), + .I2(l0_exit_reason_0_0_0_a2_2), + .I3(plm_fsm_l0_exit_reason_0_0_0_1_1694), + .O(plm_fsm_l0_exit_reason_i) + ); + defparam plm_fsm_hr_restart_0_0_0.INIT = 16'h0444; + LUT4 plm_fsm_hr_restart_0_0_0 ( + .I0(plm_fsm_N_57538), + .I1(plm_fsm_hr_restart_0_0_0_1_1695), + .I2(plm_rx0_linkctrl_0_), + .I3(plm_rx0_ts1_c), + .O(plm_fsm_hr_restart_i) + ); + defparam plm_fsm_reg_rx_clear_cs_3_sqmuxa_3_1.INIT = 8'h40; + LUT3 plm_fsm_reg_rx_clear_cs_3_sqmuxa_3_1 ( + .I0(plm_fsm_reg_rx_clear_cs273), + .I1(plm_fsm_un1_rc_cntrout_ts1_0_1_i), + .I2(plm_fsm_reg_state_15__1790), + .O(plm_fsm_reg_rx_clear_cs_3_sqmuxa_3_1_1750) + ); + defparam plm_fsm_reg_state_4_sqmuxa_1_1.INIT = 16'h1300; + LUT4 plm_fsm_reg_state_4_sqmuxa_1_1 ( + .I0(plm_reg_ts1_1), + .I1(plm_fsm_N_36833_i), + .I2(N_56496_i), + .I3(plm_fsm_reg_state_18__1789), + .O(plm_fsm_reg_state_4_sqmuxa_1_1_1728) + ); + defparam plm_fsm_un3_xl_clw2_newv_NE_6.INIT = 8'h80; + LUT3 plm_fsm_un3_xl_clw2_newv_NE_6 ( + .I0(plm_fsm_un3_xl_clw2_newv_NE_0_1698), + .I1(plm_fsm_un3_xl_clw2_newv_NE_1_1697), + .I2(plm_fsm_un3_xl_clw2_newv_NE_2_1696), + .O(plm_fsm_un3_xl_clw2_newv_NE_6_1714) + ); + defparam plm_fsm_un3_clw3_newv_NE_6.INIT = 8'h80; + LUT3 plm_fsm_un3_clw3_newv_NE_6 ( + .I0(plm_fsm_un3_clw3_newv_NE_0_1701), + .I1(plm_fsm_un3_clw3_newv_NE_1_1700), + .I2(plm_fsm_un3_clw3_newv_NE_2_1699), + .O(plm_fsm_un3_clw3_newv_NE_6_1719) + ); + defparam plm_fsm_un1_reg_rx_clear_cs_0_sqmuxa_2_2_0_a2_0_0.INIT = 16'h8000; + LUT4 plm_fsm_un1_reg_rx_clear_cs_0_sqmuxa_2_2_0_a2_0_0 ( + .I0(I_5202_i_0_0_0_o3_4_353), + .I1(I_5202_i_0_0_0_o3_5_354), + .I2(N_47431_i), + .I3(N_56042_i_1), + .O(plm_fsm_un1_reg_rx_clear_cs_0_sqmuxa_2_2_0_a2_0_0_1722) + ); + defparam plm_fsm_fsm_vector_reg_state_141_0_0_1_iv_i_0_0_a3_1_0_10_.INIT = 16'h2000; + LUT4 plm_fsm_fsm_vector_reg_state_141_0_0_1_iv_i_0_0_a3_1_0_10_ ( + .I0(plm_fsm_N_37129_7), + .I1(plm_fsm_N_55942_i), + .I2(plm_fsm_N_61287_1), + .I3(plm_fsm_good_by4_1), + .O(plm_fsm_reg_state_141_0_0_1_iv_i_0_0_a3_1[10]) + ); + defparam plm_fsm_un1_reg_state_22_i_0_0_0_1.INIT = 8'h08; + LUT3 plm_fsm_un1_reg_state_22_i_0_0_0_1 ( + .I0(plm_fsm_N_56480_i), + .I1(N_56513_i), + .I2(plm_fsm_reg_state_24__1783), + .O(plm_fsm_un1_reg_state_22_i_0_0_0_1_1758) + ); + defparam plm_fsm_un1_reg_state_18_i_0_0_o3_2_0.INIT = 16'h444C; + LUT4_L plm_fsm_un1_reg_state_18_i_0_0_o3_2_0 ( + .I0(plm_fsm_N_55942_i), + .I1(plm_fsm_N_85520_1), + .I2(plm_fsm_reg_state_8__1776), + .I3(plm_fsm_reg_state_24__1783), + .LO(plm_fsm_un1_reg_state_18_i_0_0_o3_2_0_1718) + ); + defparam plm_fsm_fsm_vector_reg_rx_clear_cs_7_m_i_a2.INIT = 4'h4; + LUT2_L plm_fsm_fsm_vector_reg_rx_clear_cs_7_m_i_a2 ( + .I0(plm_fsm_N_56356_i), + .I1(plm_fsm_N_63251), + .LO(plm_fsm_N_14639) + ); + defparam plm_fsm_fsm_vector_reg_rx_clear_cs21.INIT = 8'h10; + LUT3 plm_fsm_fsm_vector_reg_rx_clear_cs21 ( + .I0(plm_fsm_N_56356_i), + .I1(plm_fsm_N_63251), + .I2(plm_fsm_reg_state_1__425), + .O(plm_fsm_reg_rx_clear_cs21) + ); + defparam plm_fsm_reg_state_5_sqmuxa_1.INIT = 4'h4; + LUT2 plm_fsm_reg_state_5_sqmuxa_1 ( + .I0(plm_fsm_N_36967), + .I1(plm_fsm_reg_state_2__599), + .O(plm_fsm_reg_state_5_sqmuxa_1_1741) + ); + defparam plm_fsm_reg_rx_clear_cs_0_sqmuxa_7_0_a2.INIT = 4'h8; + LUT2 plm_fsm_reg_rx_clear_cs_0_sqmuxa_7_0_a2 ( + .I0(plm_fsm_N_36967), + .I1(plm_fsm_reg_state_2__599), + .O(plm_fsm_reg_rx_clear_cs_0_sqmuxa_7) + ); + defparam plm_fsm_reg_state_2_sqmuxa_3_1.INIT = 4'h4; + LUT2 plm_fsm_reg_state_2_sqmuxa_3_1 ( + .I0(plm_fsm_N_47001_i), + .I1(plm_fsm_reg_state_11__608), + .O(plm_fsm_reg_state_2_sqmuxa_3_1_1755) + ); + defparam plm_fsm_un1_reg_rx_clear_cs_0_sqmuxa.INIT = 16'h153F; + LUT4 plm_fsm_un1_reg_rx_clear_cs_0_sqmuxa ( + .I0(plm_fsm_N_56359_i), + .I1(plm_fsm_cc_cntrout0), + .I2(plm_fsm_reg_state_9__1795), + .I3(plm_fsm_reg_state_10__1792), + .O(plm_fsm_N_11039) + ); + defparam plm_fsm_un1_reg_state_14.INIT = 4'h8; + LUT2 plm_fsm_un1_reg_state_14 ( + .I0(plm_fsm_hr_restart_i), + .I1(plm_link_ctrl[0]), + .O(plm_fsm_un1_reg_state_14_1702) + ); + defparam plm_fsm_fsm_vector_N_47397_i_0_o3.INIT = 4'h2; + LUT2 plm_fsm_fsm_vector_N_47397_i_0_o3 ( + .I0(N_9900), + .I1(plm_rx0_link_pad), + .O(plm_fsm_N_55934_i) + ); + defparam plm_fsm_xl_ruined_by4_1_0_a2.INIT = 4'h8; + LUT2 plm_fsm_xl_ruined_by4_1_0_a2 ( + .I0(N_9902), + .I1(N_9903), + .O(plm_fsm_N_11035_1) + ); + defparam plm_fsm_fsm_vector_reg_rx_clear_cs230_1.INIT = 16'h5700; + LUT4 plm_fsm_fsm_vector_reg_rx_clear_cs230_1 ( + .I0(plm_fsm_N_14931_i), + .I1(plm_fsm_N_38077_i), + .I2(cmmp_negotiated_width[0]), + .I3(plm_fsm_reg_state_13__76), + .O(plm_fsm_reg_rx_clear_cs230_1) + ); + defparam plm_fsm_fsm_vector_reg_rx_clear_cs_98_0_0_1_iv_0_a29_1_0.INIT = 8'h54; + LUT3 plm_fsm_fsm_vector_reg_rx_clear_cs_98_0_0_1_iv_0_a29_1_0 ( + .I0(plm_fsm_N_55942_i), + .I1(plm_fsm_N_57049_i), + .I2(plm_fsm_reg_state_24__1783), + .O(plm_fsm_N_7175_1) + ); + defparam plm_fsm_un3_clw1_newv_NE.INIT = 16'h8000; + LUT4 plm_fsm_un3_clw1_newv_NE ( + .I0(plm_fsm_un3_clw1_newv_NE_0_1706), + .I1(plm_fsm_un3_clw1_newv_NE_1_1705), + .I2(plm_fsm_un3_clw1_newv_NE_2_1704), + .I3(plm_fsm_un3_clw1_newv_NE_4_1703), + .O(plm_fsm_N_9904) + ); + defparam plm_fsm_un3_clw2_newv_NE.INIT = 16'h8000; + LUT4 plm_fsm_un3_clw2_newv_NE ( + .I0(plm_fsm_un3_clw2_newv_NE_0_1710), + .I1(plm_fsm_un3_clw2_newv_NE_1_1709), + .I2(plm_fsm_un3_clw2_newv_NE_2_1708), + .I3(plm_fsm_un3_clw2_newv_NE_4_1707), + .O(plm_fsm_N_9911) + ); + defparam plm_fsm_un1_reg_rx_clear_cs_0_sqmuxa_2_2_0_1.INIT = 8'h08; + LUT3 plm_fsm_un1_reg_rx_clear_cs_0_sqmuxa_2_2_0_1 ( + .I0(N_9901), + .I1(plm_fsm_N_37129_7), + .I2(plm_rx1_lane_pad), + .O(plm_fsm_N_85506_1) + ); + defparam plm_fsm_fsm_vector_reg_rx_clear_cs_98_0_0_1_iv_0_3.INIT = 16'h080A; + LUT4 plm_fsm_fsm_vector_reg_rx_clear_cs_98_0_0_1_iv_0_3 ( + .I0(plm_fsm_reg_rx_clear_cs_98_0_0_1_iv_0_1), + .I1(plm_fsm_un1_rc_cntrout_ts1_0_1_i), + .I2(plm_fsm_reg_rx_clear_cs_1_sqmuxa_1727), + .I3(plm_fsm_reg_state_15__1790), + .O(plm_fsm_reg_rx_clear_cs_98_0_0_1_iv_0_3) + ); + defparam plm_fsm_fsm_vector_reg_rx_clear_cs_98_0_0_1_iv_0_4.INIT = 8'h13; + LUT3_L plm_fsm_fsm_vector_reg_rx_clear_cs_98_0_0_1_iv_0_4 ( + .I0(plm_fsm_N_56359_i), + .I1(plm_fsm_reg_rx_clear_cs_1_sqmuxa_5_1757), + .I2(plm_fsm_reg_state_10__1792), + .LO(plm_fsm_reg_rx_clear_cs_98_0_0_1_iv_0_4) + ); + defparam plm_fsm_fsm_vector_reg_rx_clear_cs_98_0_0_1_iv_0_5.INIT = 4'h1; + LUT2 plm_fsm_fsm_vector_reg_rx_clear_cs_98_0_0_1_iv_0_5 ( + .I0(plm_fsm_reg_state_0_sqmuxa_8_i_0_1751), + .I1(plm_fsm_reg_rx_clear_cs_0_sqmuxa_5_1748), + .O(plm_fsm_reg_rx_clear_cs_98_0_0_1_iv_0_5) + ); + defparam plm_fsm_fsm_vector_reg_state_141_0_0_1_iv_i_0_0_a3_1_10_.INIT = 8'h40; + LUT3_L plm_fsm_fsm_vector_reg_state_141_0_0_1_iv_i_0_0_a3_1_10_ ( + .I0(plm_fsm_N_56359_i), + .I1(plm_fsm_N_63496), + .I2(plm_fsm_reg_state_10__1792), + .LO(plm_fsm_N_61291) + ); + defparam plm_fsm_fsm_vector_reg_state_141_0_0_1_iv_0_0_.INIT = 16'h0777; + LUT4 plm_fsm_fsm_vector_reg_state_141_0_0_1_iv_0_0_ ( + .I0(plm_fsm_N_36528_i), + .I1(N_56496_i), + .I2(plm_fsm_N_63256), + .I3(plm_fsm_reg_state_0__1782), + .O(plm_fsm_reg_state_141_0_0_1_iv_0_0_) + ); + defparam plm_fsm_fsm_vector_reg_rx_clear_cs114_i_0_o2_1_0_o3_0_o3.INIT = 16'h7F00; + LUT4_L plm_fsm_fsm_vector_reg_rx_clear_cs114_i_0_o2_1_0_o3_0_o3 ( + .I0(plm_fsm_un3_clw0_newv_NE_0_1713), + .I1(plm_fsm_un3_clw0_newv_NE_4_1712), + .I2(plm_fsm_un3_clw0_newv_NE_5_1711), + .I3(plm_rx0_ts1_c), + .LO(plm_fsm_N_55908_i) + ); + defparam plm_fsm_fsm_vector_reg_state1140.INIT = 8'h80; + LUT3 plm_fsm_fsm_vector_reg_state1140 ( + .I0(plm_reg_ts1_1), + .I1(plm_fsm_N_55934_i), + .I2(plm_rx0_lane_pad), + .O(plm_fsm_reg_state1140) + ); + defparam plm_fsm_reg_rx_clear_cs_2_sqmuxa_11_1_0_o2_0_0_0_a2_1.INIT = 8'h70; + LUT3 plm_fsm_reg_rx_clear_cs_2_sqmuxa_11_1_0_o2_0_0_0_a2_1 ( + .I0(plm_fsm_un3_xl_clw2_newv_NE_4_1771), + .I1(plm_fsm_un3_xl_clw2_newv_NE_6_1714), + .I2(plm_rx2_ts1_c), + .O(plm_fsm_N_58786) + ); + defparam plm_fsm_fsm_vector_reg_state_141_0_0_1_iv_i_0_0_a3_0_4_10_.INIT = 4'h2; + LUT2 plm_fsm_fsm_vector_reg_state_141_0_0_1_iv_i_0_0_a3_0_4_10_ ( + .I0(N_56043_i), + .I1(plm_rx1_lane_pad), + .O(plm_fsm_N_61287_4) + ); + defparam plm_fsm_fsm_vector_reg_state_141_0_0_1_iv_i_0_0_a3_0_2_10_.INIT = 4'h8; + LUT2 plm_fsm_fsm_vector_reg_state_141_0_0_1_iv_i_0_0_a3_0_2_10_ ( + .I0(N_55989_i), + .I1(N_56029_i), + .O(plm_fsm_N_61287_2) + ); + defparam plm_fsm_fsm_vector_N_36829_i_0_a3_0_o3.INIT = 4'h8; + LUT2 plm_fsm_fsm_vector_N_36829_i_0_a3_0_o3 ( + .I0(plm_fsm_N_55934_i), + .I1(plm_fsm_N_56117_i), + .O(plm_fsm_N_56333_i) + ); + defparam plm_fsm_reg_rx_clear_cs_2_sqmuxa_11_1_0_o2_0_0_0_a2.INIT = 16'h7F00; + LUT4 plm_fsm_reg_rx_clear_cs_2_sqmuxa_11_1_0_o2_0_0_0_a2 ( + .I0(plm_fsm_un3_xl_clw0_newv_NE_0_1717), + .I1(plm_fsm_un3_xl_clw0_newv_NE_4_1716), + .I2(plm_fsm_un3_xl_clw0_newv_NE_5_1715), + .I3(plm_rx0_ts1_c), + .O(plm_fsm_N_58784) + ); + defparam plm_fsm_fsm_vector_reg_rx_clear_cs230.INIT = 4'h4; + LUT2 plm_fsm_fsm_vector_reg_rx_clear_cs230 ( + .I0(plm_fsm_N_38054), + .I1(plm_fsm_reg_rx_clear_cs230_1), + .O(plm_fsm_reg_rx_clear_cs230) + ); + defparam plm_fsm_fsm_vector_reg_rx_clear_cs_98_0_0_1_iv_0_1.INIT = 16'h33BF; + LUT4 plm_fsm_fsm_vector_reg_rx_clear_cs_98_0_0_1_iv_0_1 ( + .I0(plm_fsm_rc_cntrout_ts1_0), + .I1(plm_fsm_rc_timeout), + .I2(plm_fsm_reg_rx_clear_cs_1_sqmuxa_1_0_1752), + .I3(plm_fsm_reg_rx_clear_cs_3_sqmuxa_3_1_1750), + .O(plm_fsm_N_9373_1) + ); + defparam plm_fsm_reg_state_2_sqmuxa_2_1.INIT = 4'h4; + LUT2 plm_fsm_reg_state_2_sqmuxa_2_1 ( + .I0(cfg_cfg_6102[505]), + .I1(plm_fsm_reg_rx_clear_cs_0_sqmuxa_7), + .O(plm_fsm_reg_state_2_sqmuxa_2_1_1729) + ); + defparam plm_fsm_reg_state_1_sqmuxa_6.INIT = 8'h20; + LUT3 plm_fsm_reg_state_1_sqmuxa_6 ( + .I0(cfg_cfg_6102[505]), + .I1(plm_fsm_pc_cntrout3), + .I2(plm_fsm_reg_rx_clear_cs_0_sqmuxa_7), + .O(plm_fsm_reg_state_1_sqmuxa_6_1723) + ); + defparam plm_fsm_reg_rx_clear_cs_5_sqmuxa_2_1_1.INIT = 8'h40; + LUT3 plm_fsm_reg_rx_clear_cs_5_sqmuxa_2_1_1 ( + .I0(plm_fsm_ri_idle_data_0_i_1754), + .I1(plm_fsm_hr_restart_i), + .I2(plm_fsm_reg_state_16__603), + .O(plm_fsm_reg_rx_clear_cs_5_sqmuxa_2_1_1_1721) + ); + defparam plm_fsm_ruined_by4_0.INIT = 8'h80; + LUT3 plm_fsm_ruined_by4_0 ( + .I0(plm_fsm_N_11035_1), + .I1(plm_fsm_N_61287_1), + .I2(plm_fsm_good_by4_1), + .O(plm_fsm_ruined_by4_0_1740) + ); + defparam plm_fsm_fsm_vector_reg_state_141_0_0_1_iv_i_0_12_.INIT = 16'h135F; + LUT4_L plm_fsm_fsm_vector_reg_state_141_0_0_1_iv_i_0_12_ ( + .I0(plm_fsm_N_47001_i), + .I1(plm_fsm_l0_exit_reason_i), + .I2(plm_fsm_reg_state_11__608), + .I3(plm_link_l0), + .LO(plm_fsm_reg_state_141_0_0_1_iv_i_0[12]) + ); + defparam plm_fsm_un1_reg_state_18_i_0_0_0_a2_0_1_0.INIT = 16'h8000; + LUT4 plm_fsm_un1_reg_state_18_i_0_0_0_a2_0_1_0 ( + .I0(N_55989_i), + .I1(N_56029_i), + .I2(plm_fsm_good_by4_1), + .I3(plm_fsm_reg_state_24__1783), + .O(plm_fsm_un1_reg_state_18_i_0_0_0_a2_0_1_1733) + ); + defparam plm_fsm_un1_reg_rx_clear_cs_0_sqmuxa_2_2_0_1_1.INIT = 16'h0080; + LUT4 plm_fsm_un1_reg_rx_clear_cs_0_sqmuxa_2_2_0_1_1 ( + .I0(plm_fsm_N_11035_1), + .I1(plm_fsm_N_61287_1), + .I2(plm_fsm_good_by4_1), + .I3(plm_tx2_lane_pad), + .O(plm_fsm_un1_reg_rx_clear_cs_0_sqmuxa_2_2_0_1_1730) + ); + defparam plm_fsm_un1_reg_state_18_i_0_0_o3_2_1.INIT = 16'h7F00; + LUT4 plm_fsm_un1_reg_state_18_i_0_0_o3_2_1 ( + .I0(N_55989_i), + .I1(plm_fsm_N_61276_1), + .I2(plm_fsm_reg_state_24__1783), + .I3(plm_fsm_un1_reg_state_18_i_0_0_o3_2_0_1718), + .O(plm_fsm_un1_reg_state_18_i_0_0_o3_2_1_1737) + ); + defparam plm_fsm_reg_rx_clear_cs_1_sqmuxa_2.INIT = 8'h20; + LUT3 plm_fsm_reg_rx_clear_cs_1_sqmuxa_2 ( + .I0(plm_fsm_N_36844_i), + .I1(plm_fsm_N_56359_i), + .I2(plm_fsm_reg_state_10__1792), + .O(plm_fsm_reg_rx_clear_cs_1_sqmuxa_2_1736) + ); + defparam plm_fsm_fsm_vector_reg_state_141_0_0_1_iv_2_39429.INIT = 16'h32FF; + LUT4_L plm_fsm_fsm_vector_reg_state_141_0_0_1_iv_2_39429 ( + .I0(plm_fsm_N_11053), + .I1(plm_fsm_N_56356_i), + .I2(plm_fsm_N_63251), + .I3(plm_fsm_reg_state_1__425), + .LO(plm_fsm_reg_state_141_0_0_1_iv_2_39429) + ); + defparam plm_fsm_fsm_vector_reg_state_141_0_0_2_iv_0_3_.INIT = 16'h4C5F; + LUT4_L plm_fsm_fsm_vector_reg_state_141_0_0_2_iv_0_3_ ( + .I0(plm_fsm_N_36833_i), + .I1(plm_fsm_cls_timeout), + .I2(plm_fsm_reg_state_18__1789), + .I3(plm_fsm_reg_state_4_sqmuxa_2_1_1724), + .LO(plm_fsm_reg_state_141_0_0_2_iv_0[3]) + ); + defparam plm_fsm_fsm_vector_reg_state_141_0_0_1_iv_2_0_.INIT = 16'h0777; + LUT4_L plm_fsm_fsm_vector_reg_state_141_0_0_1_iv_2_0_ ( + .I0(plm_fsm_N_36977_1_i_i), + .I1(N_56496_i), + .I2(plm_fsm_reg_state_4_sqmuxa_1_1_1728), + .I3(plm_fsm_xl_cls_timeout), + .LO(plm_fsm_reg_state_141_0_0_1_iv_2[0]) + ); + defparam plm_fsm_un1_reg_state_22_i_0_0_0_a2_0.INIT = 4'h8; + LUT2 plm_fsm_un1_reg_state_22_i_0_0_0_a2_0 ( + .I0(plm_fsm_N_56131_i), + .I1(plm_fsm_reg_state_22__1785), + .O(plm_fsm_N_58420) + ); + defparam plm_fsm_reg_state_2_sqmuxa_8.INIT = 4'h4; + LUT2 plm_fsm_reg_state_2_sqmuxa_8 ( + .I0(plm_fsm_N_11041), + .I1(plm_fsm_reg_rx_clear_cs230), + .O(plm_fsm_reg_state_2_sqmuxa_8_1746) + ); + defparam plm_fsm_reg_state_2_sqmuxa_7_1_i_o2_0_o2_0_o3_0_a2.INIT = 8'h08; + LUT3 plm_fsm_reg_state_2_sqmuxa_7_1_i_o2_0_o2_0_o3_0_a2 ( + .I0(plm_reg_ts1_1), + .I1(plm_fsm_N_55934_i), + .I2(plm_rx0_lane_pad), + .O(plm_fsm_N_60902) + ); + defparam plm_fsm_un1_reg_state_18_i_0_0_0_a2_0_1.INIT = 8'h08; + LUT3 plm_fsm_un1_reg_state_18_i_0_0_0_a2_0_1 ( + .I0(plm_fsm_N_37129_7), + .I1(N_56030_i), + .I2(plm_tx2_lane_pad), + .O(plm_fsm_N_61232_1) + ); + defparam plm_fsm_fsm_vector_reg_state_141_0_0_1_iv_i_a3_1_0_0_o3_i_a3_10_.INIT = 8'h08; + LUT3 plm_fsm_fsm_vector_reg_state_141_0_0_1_iv_i_a3_1_0_0_o3_i_a3_10_ ( + .I0(plm_fsm_N_55934_i), + .I1(plm_fsm_N_56117_i), + .I2(plm_rx0_lane_pad), + .O(plm_fsm_N_47451_i) + ); + defparam plm_fsm_reg_state_3_sqmuxa_5_1.INIT = 4'h4; + LUT2 plm_fsm_reg_state_3_sqmuxa_5_1 ( + .I0(plm_fsm_N_56131_i), + .I1(plm_fsm_reg_state_20__1787), + .O(plm_fsm_reg_state_3_sqmuxa_5_1_1744) + ); + defparam plm_fsm_fsm_vector_reg_state_141_0_0_1_iv_i_0_i_a3_i_a2_1_7_.INIT = 16'h4055; + LUT4 plm_fsm_fsm_vector_reg_state_141_0_0_1_iv_i_0_i_a3_i_a2_1_7_ ( + .I0(plm_fsm_N_55908_i), + .I1(plm_fsm_un3_clw3_newv_NE_4_1720), + .I2(plm_fsm_un3_clw3_newv_NE_6_1719), + .I3(plm_rx3_ts1_c), + .O(plm_fsm_N_60908_1) + ); + defparam plm_fsm_reg_rx_clear_cs_5_sqmuxa_2_1.INIT = 16'h2E00; + LUT4 plm_fsm_reg_rx_clear_cs_5_sqmuxa_2_1 ( + .I0(plm_fsm_N_11044), + .I1(cmmp_negotiated_width[0]), + .I2(plm_fsm_reg_rx_clear_cs_0_sqmuxa_10_2), + .I3(plm_fsm_reg_rx_clear_cs_5_sqmuxa_2_1_1_1721), + .O(plm_fsm_reg_rx_clear_cs_5_sqmuxa_2_1_1747) + ); + defparam plm_fsm_reg_rx_clear_cs_3_sqmuxa_4.INIT = 16'hD100; + LUT4 plm_fsm_reg_rx_clear_cs_3_sqmuxa_4 ( + .I0(plm_fsm_N_11044), + .I1(cmmp_negotiated_width[0]), + .I2(plm_fsm_reg_rx_clear_cs_0_sqmuxa_10_2), + .I3(plm_fsm_reg_rx_clear_cs_5_sqmuxa_2_1_1_1721), + .O(plm_fsm_reg_rx_clear_cs_3_sqmuxa_4_1731) + ); + defparam plm_fsm_fsm_vector_reg_rx_clear_cs_98_0_0_1_iv_0_o29_0_0_i_a2.INIT = 16'h0080; + LUT4 plm_fsm_fsm_vector_reg_rx_clear_cs_98_0_0_1_iv_0_o29_0_0_i_a2 ( + .I0(N_55989_i), + .I1(plm_fsm_N_56333_i), + .I2(plm_fsm_N_61276_1), + .I3(plm_rx0_lane_pad), + .O(plm_fsm_good_by1) + ); + defparam plm_fsm_un1_reg_rx_clear_cs_0_sqmuxa_2_2_0_a2_0.INIT = 8'h40; + LUT3_L plm_fsm_un1_reg_rx_clear_cs_0_sqmuxa_2_2_0_a2_0 ( + .I0(plm_fsm_N_57049_i), + .I1(plm_fsm_N_61287_2), + .I2(plm_fsm_un1_reg_rx_clear_cs_0_sqmuxa_2_2_0_a2_0_0_1722), + .LO(plm_fsm_N_21906) + ); + defparam plm_fsm_fsm_vector_reg_state_141_0_0_1_iv_0_39432.INIT = 8'h07; + LUT3 plm_fsm_fsm_vector_reg_state_141_0_0_1_iv_0_39432 ( + .I0(plm_fsm_N_11053), + .I1(plm_fsm_reg_rx_clear_cs21), + .I2(plm_fsm_hr_timeout), + .O(plm_fsm_reg_state_141_0_0_1_iv_0_39432) + ); + defparam plm_fsm_reg_rx_clear_cs_2_sqmuxa_11_1_0_o2_0_0_0_0.INIT = 4'h4; + LUT2_L plm_fsm_reg_rx_clear_cs_2_sqmuxa_11_1_0_o2_0_0_0_0 ( + .I0(plm_fsm_N_58786), + .I1(plm_fsm_reg_state_23__1784), + .LO(plm_fsm_reg_rx_clear_cs_2_sqmuxa_11_1_0_o2_0_0_0_0_1732) + ); + defparam plm_fsm_fsm_vector_reg_rx_clear_cs389_i_0_i2_0_0_a2_0_i_o3_0_a2_0_0.INIT = 8'h80; + LUT3_L plm_fsm_fsm_vector_reg_rx_clear_cs389_i_0_i2_0_0_a2_0_i_o3_0_a2_0_0 ( + .I0(plm_fsm_N_61287_1), + .I1(plm_fsm_N_61287_2), + .I2(plm_fsm_good_by4_1), + .LO(plm_fsm_reg_rx_clear_cs389_i_0_i2_0_0_a2_0_i_o3_0_a2_0_0) + ); + defparam plm_fsm_fsm_vector_reg_state_141_0_0_1_iv_i_0_0_a3_3_0_10_.INIT = 16'hA080; + LUT4 plm_fsm_fsm_vector_reg_state_141_0_0_1_iv_i_0_0_a3_3_0_10_ ( + .I0(plm_fsm_N_61287_4), + .I1(plm_fsm_N_61331), + .I2(plm_fsm_reg_state_141_0_0_1_iv_i_0_0_a3_1[10]), + .I3(plm_fsm_reg_state_24__1783), + .O(plm_fsm_reg_state_141_0_0_1_iv_i_0_0_a3_3[10]) + ); + defparam plm_fsm_fsm_vector_reg_rx_clear_cs_98_0_0_1_iv_0_9.INIT = 16'h4044; + LUT4 plm_fsm_fsm_vector_reg_rx_clear_cs_98_0_0_1_iv_0_9 ( + .I0(plm_fsm_reg_state_1_sqmuxa_4_i_0_1753), + .I1(plm_fsm_reg_rx_clear_cs_98_0_0_1_iv_0_3), + .I2(plm_fsm_l0_exit_reason_i), + .I3(plm_link_l0), + .O(plm_fsm_reg_rx_clear_cs_98_0_0_1_iv_0_9) + ); + defparam plm_fsm_fsm_vector_reg_rx_clear_cs_98_0_0_1_iv_0_10.INIT = 16'h4044; + LUT4 plm_fsm_fsm_vector_reg_rx_clear_cs_98_0_0_1_iv_0_10 ( + .I0(plm_fsm_N_14468_i), + .I1(plm_fsm_reg_rx_clear_cs_98_0_0_1_iv_0_4), + .I2(plm_fsm_hr_restart_i), + .I3(plm_fsm_reg_state_16__603), + .O(plm_fsm_reg_rx_clear_cs_98_0_0_1_iv_0_10) + ); + defparam plm_fsm_fsm_vector_reg_state_141_0_0_1_iv_i_0_i_i_m3_0_24_.INIT = 8'hE2; + LUT3 plm_fsm_fsm_vector_reg_state_141_0_0_1_iv_i_0_i_i_m3_0_24_ ( + .I0(plm_fsm_N_56333_i), + .I1(plm_rx0_lane_pad), + .I2(plm_rx0_link_pad), + .O(plm_fsm_N_57051) + ); + defparam plm_fsm_fsm_vector_reg_state_141_0_0_1_iv_0_9_.INIT = 8'h0B; + LUT3 plm_fsm_fsm_vector_reg_state_141_0_0_1_iv_0_9_ ( + .I0(plm_fsm_N_36844_i), + .I1(plm_fsm_reg_rx_clear_cs_2_sqmuxa_1_1_1725), + .I2(plm_fsm_reg_state_1_sqmuxa_6_1723), + .O(plm_fsm_reg_state_141_0_0_1_iv_0_9_) + ); + defparam plm_fsm_fsm_vector_reg_state_141_0_0_1_iv_4_0_.INIT = 16'h444C; + LUT4 plm_fsm_fsm_vector_reg_state_141_0_0_1_iv_4_0_ ( + .I0(plm_fsm_cls_timeout), + .I1(plm_fsm_reg_state_141_0_0_1_iv_2[0]), + .I2(plm_fsm_reg_rx_clear_cs_4_sqmuxa_1_0), + .I3(plm_fsm_reg_state_4_sqmuxa_2_1_1724), + .O(plm_fsm_reg_state_141_0_0_1_iv_4[0]) + ); + defparam plm_fsm_fsm_vector_reg_rx_clear_cs_98_0_0_1_iv_0_12.INIT = 16'h135F; + LUT4 plm_fsm_fsm_vector_reg_rx_clear_cs_98_0_0_1_iv_0_12 ( + .I0(plm_fsm_N_36844_i), + .I1(plm_fsm_pc_timeout_1), + .I2(plm_fsm_reg_rx_clear_cs_2_sqmuxa_1_1_1725), + .I3(plm_fsm_reg_state_5_sqmuxa_1_1741), + .O(plm_fsm_reg_state_141_0_0_1_iv_5[0]) + ); + defparam plm_fsm_N_87223_i.INIT = 8'h2F; + LUT3 plm_fsm_N_87223_i ( + .I0(N_56052_i), + .I1(plm_fsm_N_56187_i), + .I2(plm_fsm_reg_state_13__76), + .O(plm_fsm_N_87223_i_1799) + ); + defparam plm_fsm_un1_reg_state_15_i_0_0_a2_0_1.INIT = 16'hC4CC; + LUT4 plm_fsm_un1_reg_state_15_i_0_0_a2_0_1 ( + .I0(plm_fsm_N_55934_i), + .I1(plm_fsm_reg_state_6__1778), + .I2(plm_rx0_lane_pad), + .I3(plm_rx0_ts1_c), + .O(plm_fsm_N_59392_1) + ); + defparam plm_fsm_un1_reg_state_22_i_0_0_0_a2.INIT = 16'h0800; + LUT4 plm_fsm_un1_reg_state_22_i_0_0_0_a2 ( + .I0(plm_fsm_N_55934_i), + .I1(plm_fsm_reg_state_6__1778), + .I2(plm_rx0_lane_pad), + .I3(plm_rx0_ts1_c), + .O(plm_fsm_N_47500_i_0) + ); + defparam plm_fsm_reg_state_1_sqmuxa_11.INIT = 8'h10; + LUT3 plm_fsm_reg_state_1_sqmuxa_11 ( + .I0(plm_fsm_N_63249), + .I1(plm_fsm_reg_state1140), + .I2(plm_fsm_reg_state_21__1786), + .O(plm_fsm_reg_state_1_sqmuxa_11_1734) + ); + defparam plm_fsm_reg_state_2_sqmuxa_9.INIT = 8'h20; + LUT3 plm_fsm_reg_state_2_sqmuxa_9 ( + .I0(plm_fsm_N_63249), + .I1(plm_fsm_reg_state1140), + .I2(plm_fsm_reg_state_21__1786), + .O(plm_fsm_reg_state_2_sqmuxa_9_1743) + ); + defparam plm_fsm_fsm_vector_reg_123_link_pad_36_1.INIT = 16'h7F00; + LUT4_L plm_fsm_fsm_vector_reg_123_link_pad_36_1 ( + .I0(N_9901), + .I1(plm_fsm_N_11035_1), + .I2(plm_fsm_N_11035_2), + .I3(plm_fsm_N_58420), + .LO(plm_fsm_xl_ruined_by4_m) + ); + defparam plm_fsm_un1_reg_state_15_i_0_0_a2.INIT = 8'h10; + LUT3 plm_fsm_un1_reg_state_15_i_0_0_a2 ( + .I0(plm_fsm_N_56131_i), + .I1(plm_fsm_N_63249), + .I2(plm_fsm_reg_state_22__1785), + .O(plm_fsm_N_59391) + ); + defparam plm_fsm_reg_rx_clear_cs_2_sqmuxa_8.INIT = 8'h40; + LUT3 plm_fsm_reg_rx_clear_cs_2_sqmuxa_8 ( + .I0(plm_fsm_N_56131_i), + .I1(plm_fsm_N_63249), + .I2(plm_fsm_reg_state_22__1785), + .O(plm_fsm_reg_rx_clear_cs_2_sqmuxa_8_1742) + ); + defparam plm_fsm_reg_rx_clear_cs_4_sqmuxa_1.INIT = 8'h40; + LUT3 plm_fsm_reg_rx_clear_cs_4_sqmuxa_1 ( + .I0(plm_fsm_N_62888), + .I1(plm_fsm_reg_rx_clear_cs_5_sqmuxa_2_1_1747), + .I2(plm_fsm_reg_state_16__603), + .O(plm_fsm_reg_rx_clear_cs_4_sqmuxa_1_1739) + ); + defparam plm_fsm_un1_reg_state_18_i_0_0_0_a3_3.INIT = 8'h80; + LUT3 plm_fsm_un1_reg_state_18_i_0_0_0_a3_3 ( + .I0(plm_fsm_N_47451_i), + .I1(plm_fsm_N_55883_i), + .I2(plm_fsm_N_56470_i), + .O(plm_fsm_N_61272) + ); + defparam plm_fsm_fsm_vector_reg_state_141_0_0_1_iv_i_0_i_a3_i_o3_7_.INIT = 16'h7350; + LUT4 plm_fsm_fsm_vector_reg_state_141_0_0_1_iv_i_0_i_a3_i_o3_7_ ( + .I0(plm_fsm_N_9904), + .I1(plm_fsm_N_9911), + .I2(plm_rx1_ts1_c), + .I3(plm_rx2_ts1_c), + .O(plm_fsm_reg_state_141_0_0_1_iv_i_0_i_a3_i_o3[7]) + ); + defparam plm_fsm_fsm_vector_reg_state_141_0_0_1_iv_i_0_0_a3_0_1_0_10_.INIT = 16'h0080; + LUT4_L plm_fsm_fsm_vector_reg_state_141_0_0_1_iv_i_0_0_a3_0_1_0_10_ ( + .I0(plm_fsm_N_47451_i), + .I1(N_56030_i), + .I2(plm_fsm_N_61287_2), + .I3(plm_tx2_lane_pad), + .LO(plm_fsm_N_61287_1_0) + ); + defparam plm_fsm_fsm_vector_reg_state_141_0_0_0_0_18_.INIT = 8'h01; + LUT3 plm_fsm_fsm_vector_reg_state_141_0_0_0_0_18_ ( + .I0(plm_fsm_reg_rx_clear_cs_1_sqmuxa_1727), + .I1(plm_fsm_reg_rx_clear_cs_1_sqmuxa_3_1726), + .I2(plm_fsm_reg_rx_clear_cs_3_sqmuxa_4_1731), + .O(plm_fsm_N_10498) + ); + defparam plm_fsm_fsm_vector_reg_state_141_0_0_1_iv_i_0_i_i_2_0_24_.INIT = 8'h1F; + LUT3_L plm_fsm_fsm_vector_reg_state_141_0_0_1_iv_i_0_i_i_2_0_24_ ( + .I0(plm_fsm_N_58786), + .I1(plm_fsm_N_58787), + .I2(plm_fsm_reg_state_23__1784), + .LO(plm_fsm_reg_state_141_0_0_1_iv_i_0_i_i_2_0[24]) + ); + defparam plm_fsm_fsm_vector_reg_state_141_0_0_1_iv_i_0_0_a3_0_1_1_10_.INIT = 16'h8000; + LUT4 plm_fsm_fsm_vector_reg_state_141_0_0_1_iv_i_0_0_a3_0_1_1_10_ ( + .I0(plm_fsm_N_11035_2), + .I1(plm_fsm_N_61287_1), + .I2(plm_fsm_N_61287_4), + .I3(plm_fsm_N_61331), + .O(plm_fsm_reg_state_141_0_0_1_iv_i_0_0_a3_0_1[10]) + ); + defparam plm_fsm_fsm_vector_reg_state_141_0_0_2_iv_1_3_.INIT = 8'h8A; + LUT3 plm_fsm_fsm_vector_reg_state_141_0_0_2_iv_1_3_ ( + .I0(plm_fsm_reg_state_141_0_0_2_iv_0[3]), + .I1(plm_fsm_reg_link_mode_1797), + .I2(plm_fsm_reg_state_2_sqmuxa_2_1_1729), + .O(plm_fsm_reg_state_141_0_0_2_iv_1[3]) + ); + defparam plm_fsm_fsm_vector_reg_state_141_0_0_1_iv_0_18_.INIT = 16'h7707; + LUT4 plm_fsm_fsm_vector_reg_state_141_0_0_1_iv_0_18_ ( + .I0(plm_fsm_reg_link_mode_1797), + .I1(plm_fsm_reg_state_2_sqmuxa_2_1_1729), + .I2(plm_fsm_reg_state_4_sqmuxa_1_1_1728), + .I3(plm_fsm_xl_cls_timeout), + .O(plm_fsm_reg_state_141_0_0_1_iv_0_18_) + ); + defparam plm_fsm_un1_reg_rx_clear_cs_0_sqmuxa_2_2_0_4.INIT = 16'h2000; + LUT4 plm_fsm_un1_reg_rx_clear_cs_0_sqmuxa_2_2_0_4 ( + .I0(plm_fsm_N_7175_1), + .I1(plm_fsm_N_21906), + .I2(plm_fsm_N_85506_1), + .I3(plm_fsm_un1_reg_rx_clear_cs_0_sqmuxa_2_2_0_1_1730), + .O(plm_fsm_un1_reg_rx_clear_cs_0_sqmuxa_2_2_0_4_1735) + ); + defparam plm_fsm_fsm_vector_reg_rx_clear_cs_98_0_0_1_iv_0_14.INIT = 8'h02; + LUT3_L plm_fsm_fsm_vector_reg_rx_clear_cs_98_0_0_1_iv_0_14 ( + .I0(plm_fsm_N_9373_1), + .I1(plm_fsm_reg_rx_clear_cs230), + .I2(plm_fsm_reg_rx_clear_cs_3_sqmuxa_4_1731), + .LO(plm_fsm_reg_rx_clear_cs_98_0_0_1_iv_0_14) + ); + defparam plm_fsm_fsm_vector_reg_state_141_0_0_1_iv_6_0_.INIT = 16'h004C; + LUT4 plm_fsm_fsm_vector_reg_state_141_0_0_1_iv_6_0_ ( + .I0(plm_fsm_ci_timeout), + .I1(plm_fsm_reg_state_141_0_0_1_iv_0_0_), + .I2(plm_fsm_reg_state_2_sqmuxa_3_1_1755), + .I3(plm_fsm_reg_state_3_sqmuxa_4_1775), + .O(plm_fsm_reg_state_141_0_0_1_iv_6[0]) + ); + defparam plm_fsm_un1_reg_state_15_i_0_0_a2_0.INIT = 4'h2; + LUT2 plm_fsm_un1_reg_state_15_i_0_0_a2_0 ( + .I0(plm_fsm_N_59392_1), + .I1(plm_fsm_N_63481), + .O(plm_fsm_N_59392) + ); + defparam plm_fsm_un1_reg_state_18_i_0_0_0_o3_4.INIT = 16'h0F07; + LUT4_L plm_fsm_un1_reg_state_18_i_0_0_0_o3_4 ( + .I0(plm_fsm_N_55934_i), + .I1(plm_fsm_N_56480_i), + .I2(plm_fsm_N_61272), + .I3(plm_rx0_lane_pad), + .LO(plm_fsm_N_55846_i) + ); + defparam plm_fsm_fsm_vector_reg_state_141_0_0_1_iv_i_0_i_i_2_24_.INIT = 16'h10F0; + LUT4 plm_fsm_fsm_vector_reg_state_141_0_0_1_iv_i_0_i_i_2_24_ ( + .I0(plm_fsm_N_58784), + .I1(plm_fsm_N_58785), + .I2(plm_fsm_reg_state_141_0_0_1_iv_i_0_i_i_2_0[24]), + .I3(plm_fsm_reg_state_23__1784), + .O(plm_fsm_N_54682_2_i) + ); + defparam plm_fsm_reg_rx_clear_cs_2_sqmuxa_11_1_0_o2_0_0_0.INIT = 16'h0100; + LUT4 plm_fsm_reg_rx_clear_cs_2_sqmuxa_11_1_0_o2_0_0_0 ( + .I0(plm_fsm_N_58784), + .I1(plm_fsm_N_58785), + .I2(plm_fsm_N_58787), + .I3(plm_fsm_reg_rx_clear_cs_2_sqmuxa_11_1_0_o2_0_0_0_0_1732), + .O(plm_fsm_N_21891_i) + ); + defparam plm_fsm_un1_reg_state_18_i_0_0_0_a2_0.INIT = 16'h8000; + LUT4 plm_fsm_un1_reg_state_18_i_0_0_0_a2_0 ( + .I0(plm_fsm_N_61232_1), + .I1(plm_fsm_N_61287_1), + .I2(plm_fsm_N_61287_4), + .I3(plm_fsm_un1_reg_state_18_i_0_0_0_a2_0_1_1733), + .O(plm_fsm_N_58424) + ); + defparam plm_fsm_fsm_vector_reg_state_141_0_0_1_iv_i_0_i_a3_i_a2_7_.INIT = 16'h0080; + LUT4 plm_fsm_fsm_vector_reg_state_141_0_0_1_iv_i_0_i_a3_i_a2_7_ ( + .I0(plm_fsm_N_60908_1), + .I1(plm_fsm_N_60908_2), + .I2(plm_fsm_N_63492), + .I3(plm_fsm_reg_state_141_0_0_1_iv_i_0_i_a3_i_o3[7]), + .O(plm_fsm_N_60908) + ); + defparam plm_fsm_fsm_vector_reg_rx_clear_cs389_i_0_i2_0_0_a2_0_i_o3_0_a2_0.INIT = 8'h80; + LUT3 plm_fsm_fsm_vector_reg_rx_clear_cs389_i_0_i2_0_0_a2_0_i_o3_0_a2_0 ( + .I0(plm_fsm_N_61232_1), + .I1(plm_fsm_N_61287_4), + .I2(plm_fsm_reg_rx_clear_cs389_i_0_i2_0_0_a2_0_i_o3_0_a2_0_0), + .O(plm_fsm_N_60900) + ); + defparam plm_fsm_fsm_vector_reg_state_141_0_0_1_iv_0_o2_0_23_.INIT = 8'h07; + LUT3 plm_fsm_fsm_vector_reg_state_141_0_0_1_iv_0_o2_0_23_ ( + .I0(plm_fsm_N_36528_i), + .I1(plm_fsm_N_47451_i), + .I2(plm_fsm_N_58420), + .O(plm_fsm_reg_state_141_0_0_1_iv_0_o2_0[23]) + ); + defparam plm_fsm_fsm_vector_reg_state_141_0_0_1_iv_10_0_.INIT = 16'h0BFF; + LUT4_L plm_fsm_fsm_vector_reg_state_141_0_0_1_iv_10_0_ ( + .I0(plm_fsm_reg_state1140), + .I1(plm_fsm_reg_state_19__1788), + .I2(plm_fsm_reg_state_3_sqmuxa_5_1_1744), + .I3(plm_fsm_xl_cls_timeout), + .LO(plm_fsm_reg_state_141_0_0_1_iv_10[0]) + ); + defparam plm_fsm_fsm_vector_reg_state_141_0_0_1_iv_11_0_.INIT = 16'h00EF; + LUT4_L plm_fsm_fsm_vector_reg_state_141_0_0_1_iv_11_0_ ( + .I0(plm_fsm_N_60902), + .I1(plm_fsm_N_63481), + .I2(plm_fsm_reg_state_5__1779), + .I3(plm_fsm_reg_state_1_sqmuxa_11_1734), + .LO(plm_fsm_reg_state_141_0_0_1_iv_11[0]) + ); + defparam plm_fsm_fsm_vector_reg_rx_clear_cs_98_0_0_1_iv_0_15.INIT = 16'h0080; + LUT4 plm_fsm_fsm_vector_reg_rx_clear_cs_98_0_0_1_iv_0_15 ( + .I0(plm_fsm_reg_rx_clear_cs_98_0_0_1_iv_0_5), + .I1(plm_fsm_reg_rx_clear_cs_98_0_0_1_iv_0_9), + .I2(plm_fsm_reg_state_141_0_0_1_iv_5[0]), + .I3(plm_fsm_reg_rx_clear_cs_0_sqmuxa_7), + .O(plm_fsm_reg_rx_clear_cs_98_0_0_1_iv_0_15) + ); + defparam plm_fsm_fsm_vector_reg_state_141_0_0_1_iv_8_39434.INIT = 8'h73; + LUT3 plm_fsm_fsm_vector_reg_state_141_0_0_1_iv_8_39434 ( + .I0(plm_fsm_N_55942_i), + .I1(plm_fsm_N_57049_i), + .I2(plm_fsm_N_57051), + .O(plm_fsm_reg_state_141_0_0_1_iv_8_39434) + ); + defparam plm_fsm_reg_rx_clear_cs_0_sqmuxa_11.INIT = 4'h4; + LUT2 plm_fsm_reg_rx_clear_cs_0_sqmuxa_11 ( + .I0(plm_fsm_N_54760_i), + .I1(plm_fsm_reg_state_7__1777), + .O(plm_fsm_reg_rx_clear_cs_0_sqmuxa_11_1759) + ); + defparam plm_fsm_fsm_vector_reg_123_link_pad_36_sn_m2_0_a2_1_0.INIT = 8'h13; + LUT3 plm_fsm_fsm_vector_reg_123_link_pad_36_sn_m2_0_a2_1_0 ( + .I0(plm_fsm_N_47451_i), + .I1(plm_fsm_reg_state_10__1792), + .I2(plm_fsm_un1_reg_rx_clear_cs_0_sqmuxa_2_2_0_4_1735), + .O(plm_fsm_N_5866_1_0) + ); + defparam plm_fsm_fsm_vector_reg_123_link_pad_36_sn_m2_0_a2_1.INIT = 16'h0100; + LUT4 plm_fsm_fsm_vector_reg_123_link_pad_36_sn_m2_0_a2_1 ( + .I0(plm_fsm_N_58420), + .I1(plm_fsm_reg_rx_clear_cs_2_sqmuxa_8_1742), + .I2(plm_fsm_reg_state_21__1786), + .I3(plm_fsm_un1_reg_state_4_i), + .O(plm_fsm_reg_123_link_pad_36_sn_m2_0_a2_1) + ); + defparam plm_fsm_fsm_vector_reg_state_141_0_0_1_iv_12_0_.INIT = 16'h0080; + LUT4_L plm_fsm_fsm_vector_reg_state_141_0_0_1_iv_12_0_ ( + .I0(plm_fsm_N_9373_1), + .I1(plm_fsm_reg_state_141_0_0_1_iv_0_39432), + .I2(plm_fsm_reg_state_141_0_0_1_iv_10[0]), + .I3(plm_fsm_reg_rx_clear_cs_1_sqmuxa_2_1736), + .LO(plm_fsm_reg_state_141_0_0_1_iv_12[0]) + ); + defparam plm_fsm_fsm_vector_reg_123_lane_pad_35_iv_0.INIT = 16'h00D5; + LUT4 plm_fsm_fsm_vector_reg_123_lane_pad_35_iv_0 ( + .I0(plm_fsm_N_47500_i_0), + .I1(plm_fsm_N_85506_1), + .I2(plm_fsm_ruined_by4_0_1740), + .I3(plm_fsm_xl_ruined_by4_m), + .O(plm_fsm_reg_123_lane_pad_35_iv_0) + ); + defparam plm_fsm_fsm_vector_reg_rx_clear_cs_98_0_0_1_iv_0_18.INIT = 16'h0080; + LUT4 plm_fsm_fsm_vector_reg_rx_clear_cs_98_0_0_1_iv_0_18 ( + .I0(plm_fsm_N_54682_2_i), + .I1(plm_fsm_reg_rx_clear_cs_98_0_0_1_iv_0_10), + .I2(plm_fsm_reg_rx_clear_cs_98_0_0_1_iv_0_14), + .I3(plm_fsm_reg_rx_clear_cs_1_sqmuxa_2_1736), + .O(plm_fsm_reg_rx_clear_cs_98_0_0_1_iv_0_18) + ); + defparam plm_fsm_fsm_vector_reg_rx_clear_cs_98_0_0_1_iv_0_o29_0_0_i.INIT = 8'h07; + LUT3 plm_fsm_fsm_vector_reg_rx_clear_cs_98_0_0_1_iv_0_o29_0_0_i ( + .I0(plm_fsm_N_47451_i), + .I1(plm_fsm_N_60900), + .I2(plm_fsm_good_by1), + .O(plm_fsm_N_36409_i) + ); + defparam plm_fsm_fsm_vector_reg_123_link_pad_36_sn_m2_0_a2.INIT = 4'h8; + LUT2 plm_fsm_fsm_vector_reg_123_link_pad_36_sn_m2_0_a2 ( + .I0(plm_fsm_N_5866_1_0), + .I1(plm_fsm_reg_123_link_pad_36_sn_m2_0_a2_1), + .O(plm_fsm_N_5866) + ); + defparam plm_fsm_un1_reg_state_18_i_0_0_0_a2.INIT = 16'h80C0; + LUT4 plm_fsm_un1_reg_state_18_i_0_0_0_a2 ( + .I0(plm_fsm_N_55846_i), + .I1(plm_fsm_N_63481), + .I2(plm_fsm_reg_state_6__1778), + .I3(plm_rx0_ts1_c), + .O(plm_fsm_N_58423) + ); + defparam plm_fsm_un1_reg_state_18_i_0_0_o3_2_39428.INIT = 16'hF8FC; + LUT4_L plm_fsm_un1_reg_state_18_i_0_0_o3_2_39428 ( + .I0(plm_fsm_N_47451_i), + .I1(plm_fsm_N_56480_i), + .I2(plm_fsm_N_61272), + .I3(plm_fsm_reg_state_24__1783), + .LO(plm_fsm_un1_reg_state_18_i_0_0_o3_2_39428_1738) + ); + defparam plm_fsm_fsm_vector_reg_state_141_0_0_1_iv_13_0_.INIT = 16'hD0F0; + LUT4_L plm_fsm_fsm_vector_reg_state_141_0_0_1_iv_13_0_ ( + .I0(plm_fsm_N_21891_i), + .I1(plm_fsm_N_63400), + .I2(plm_fsm_reg_state_141_0_0_1_iv_11[0]), + .I3(plm_fsm_reg_state_23__1784), + .LO(plm_fsm_reg_state_141_0_0_1_iv_13[0]) + ); + defparam plm_fsm_fsm_vector_reg_state_141_0_0_1_iv_14_0_.INIT = 16'h8000; + LUT4_L plm_fsm_fsm_vector_reg_state_141_0_0_1_iv_14_0_ ( + .I0(plm_fsm_reg_state_141_0_0_1_iv_4[0]), + .I1(plm_fsm_reg_state_141_0_0_1_iv_5[0]), + .I2(plm_fsm_reg_state_141_0_0_1_iv_6[0]), + .I3(plm_fsm_reg_state_141_0_0_1_iv_12[0]), + .LO(plm_fsm_reg_state_141_0_0_1_iv_14[0]) + ); + defparam plm_fsm_un1_reg_state_18_i_0_0_o3_2.INIT = 8'h40; + LUT3 plm_fsm_un1_reg_state_18_i_0_0_o3_2 ( + .I0(plm_fsm_N_58424), + .I1(plm_fsm_un1_reg_state_18_i_0_0_o3_2_39428_1738), + .I2(plm_fsm_un1_reg_state_18_i_0_0_o3_2_1_1737), + .O(plm_fsm_N_47658_i) + ); + defparam plm_fsm_fsm_vector_reg_state_141_0_0_1_iv_15_0_.INIT = 16'h00D0; + LUT4 plm_fsm_fsm_vector_reg_state_141_0_0_1_iv_15_0_ ( + .I0(plm_fsm_N_54760_i), + .I1(plm_fsm_N_63492), + .I2(plm_fsm_reg_state_141_0_0_1_iv_13[0]), + .I3(plm_fsm_reg_rx_clear_cs_4_sqmuxa_1_1739), + .O(plm_fsm_reg_state_141_0_0_1_iv_15[0]) + ); + defparam plm_fsm_fsm_vector_reg_123_link_pad_36_2_0_am.INIT = 16'h7F00; + LUT4 plm_fsm_fsm_vector_reg_123_link_pad_36_2_0_am ( + .I0(N_9901), + .I1(plm_fsm_N_11035_1), + .I2(plm_fsm_N_11035_2), + .I3(plm_fsm_N_58420), + .O(plm_fsm_reg_123_link_pad_36_2_0_am) + ); + defparam plm_fsm_fsm_vector_reg_123_link_pad_36_2_0_bm.INIT = 16'h1DDD; + LUT4 plm_fsm_fsm_vector_reg_123_link_pad_36_2_0_bm ( + .I0(plm_fsm_N_11048), + .I1(plm_fsm_N_47500_i_0), + .I2(plm_fsm_N_85506_1), + .I3(plm_fsm_ruined_by4_0_1740), + .O(plm_fsm_reg_123_link_pad_36_2_0_bm) + ); + defparam plm_fsm_un1_reg_state_18_i_0_0_0.INIT = 8'h02; + LUT3 plm_fsm_un1_reg_state_18_i_0_0_0 ( + .I0(plm_fsm_N_47658_i), + .I1(plm_fsm_N_58423), + .I2(plm_fsm_reg_state_5__1779), + .O(plm_fsm_N_15478_i) + ); + MUXF5 plm_fsm_fsm_vector_reg_123_link_pad_36_2_0 ( + .I0(plm_fsm_reg_123_link_pad_36_2_0_am), + .I1(plm_fsm_reg_123_link_pad_36_2_0_bm), + .O(plm_fsm_N_5868), + .S(plm_fsm_N_5866) + ); + defparam plm_fsm_fsm_vector_N_9373_i.INIT = 16'h54FF; + LUT4_L plm_fsm_fsm_vector_N_9373_i ( + .I0(plm_fsm_N_36409_i), + .I1(plm_fsm_N_36528_i), + .I2(plm_fsm_N_61331), + .I3(plm_fsm_reg_rx_clear_cs_98_0_0_1_iv_0_21), + .LO(plm_fsm_N_9373_i) + ); + defparam plm_fsm_fsm_vector_N_10369_i.INIT = 16'hEF0F; + LUT4_L plm_fsm_fsm_vector_N_10369_i ( + .I0(plm_fsm_N_36528_i), + .I1(plm_fsm_N_61331), + .I2(plm_fsm_reg_state_141_0_0_1_iv_0_9_), + .I3(plm_fsm_good_by1), + .LO(plm_fsm_N_10369_i) + ); + defparam plm_fsm_fsm_vector_N_10368_i.INIT = 16'hFF8F; + LUT4_L plm_fsm_fsm_vector_N_10368_i ( + .I0(plm_fsm_N_36409_i), + .I1(plm_fsm_N_61331), + .I2(plm_fsm_reg_state_141_0_0_1_iv_8_39434), + .I3(plm_fsm_reg_rx_clear_cs_0_sqmuxa_11_1759), + .LO(plm_fsm_N_10368_i) + ); + defparam plm_fsm_fsm_vector_N_85499_i.INIT = 16'hFFF8; + LUT4_L plm_fsm_fsm_vector_N_85499_i ( + .I0(plm_fsm_N_36977_1_i_i), + .I1(plm_fsm_N_47451_i), + .I2(plm_fsm_N_47500_i_0), + .I3(plm_fsm_N_60908), + .LO(plm_fsm_N_85499_i) + ); + defparam plm_fsm_fsm_vector_N_87557_i.INIT = 16'hECA0; + LUT4_L plm_fsm_fsm_vector_N_87557_i ( + .I0(plm_fsm_N_59392_1), + .I1(plm_fsm_N_60902), + .I2(plm_fsm_N_63481), + .I3(plm_fsm_reg_state_5__1779), + .LO(plm_fsm_N_87557_i) + ); + defparam plm_fsm_fsm_vector_reg_state_141_0_0_0_iv_0_0_0_0_5_.INIT = 16'h5450; + LUT4_L plm_fsm_fsm_vector_reg_state_141_0_0_0_iv_0_0_0_0_5_ ( + .I0(plm_fsm_N_60902), + .I1(plm_fsm_N_63481), + .I2(plm_fsm_reg_rx_clear_cs_1_sqmuxa_5_1757), + .I3(plm_fsm_reg_state_5__1779), + .LO(plm_fsm_N_10496_i) + ); + defparam plm_fsm_fsm_vector_N_10497_i.INIT = 16'hECA0; + LUT4_L plm_fsm_fsm_vector_N_10497_i ( + .I0(plm_fsm_N_38052), + .I1(plm_fsm_un1_rx0_lane_pad), + .I2(plm_fsm_reg_rx_clear_cs_4_sqmuxa_1_0), + .I3(plm_fsm_reg_state_3__1781), + .LO(plm_fsm_N_10497_i) + ); + defparam plm_fsm_fsm_vector_N_10366_i.INIT = 16'h3F37; + LUT4_L plm_fsm_fsm_vector_N_10366_i ( + .I0(plm_fsm_N_10498), + .I1(plm_fsm_reg_state_141_0_0_2_iv_1[3]), + .I2(plm_fsm_reg_link_mode_1797), + .I3(plm_fsm_reg_state_2_sqmuxa_8_1746), + .LO(plm_fsm_N_10366_i) + ); + defparam plm_fsm_fsm_vector_N_10365_i.INIT = 8'h75; + LUT3_L plm_fsm_fsm_vector_N_10365_i ( + .I0(plm_fsm_reg_state_141_0_0_1_iv_2_39429), + .I1(plm_fsm_pc_timeout_1), + .I2(plm_fsm_reg_state_5_sqmuxa_1_1741), + .LO(plm_fsm_N_10365_i) + ); + defparam plm_fsm_fsm_vector_N_87545_i.INIT = 16'hBA30; + LUT4_L plm_fsm_fsm_vector_N_87545_i ( + .I0(plm_fsm_N_14639), + .I1(plm_fsm_N_63256), + .I2(plm_fsm_reg_state_0__1782), + .I3(plm_fsm_reg_state_1__425), + .LO(plm_fsm_N_87545_i) + ); + defparam plm_fsm_fsm_vector_N_10364_i.INIT = 16'hEFFF; + LUT4_L plm_fsm_fsm_vector_N_10364_i ( + .I0(plm_fsm_N_59391), + .I1(plm_fsm_N_59392), + .I2(plm_fsm_reg_state_141_0_0_1_iv_14[0]), + .I3(plm_fsm_reg_state_141_0_0_1_iv_15[0]), + .LO(plm_fsm_N_10364_i) + ); + defparam plm_fsm_fsm_vector_N_85511_i.INIT = 16'hDF55; + LUT4_L plm_fsm_fsm_vector_N_85511_i ( + .I0(plm_fsm_N_54682_2_i), + .I1(plm_fsm_N_55942_i), + .I2(plm_fsm_N_57051), + .I3(plm_fsm_reg_state_24__1783), + .LO(plm_fsm_N_85511_i) + ); + defparam plm_fsm_fsm_vector_N_10485_i.INIT = 8'hEC; + LUT3_L plm_fsm_fsm_vector_N_10485_i ( + .I0(plm_fsm_reg_state1140), + .I1(plm_fsm_reg_rx_clear_cs_2_sqmuxa_8_1742), + .I2(plm_fsm_reg_state_21__1786), + .LO(plm_fsm_N_10485_i) + ); + defparam plm_fsm_fsm_vector_N_10486_i.INIT = 8'hF8; + LUT3_L plm_fsm_fsm_vector_N_10486_i ( + .I0(plm_fsm_N_56131_i), + .I1(plm_fsm_reg_state_20__1787), + .I2(plm_fsm_reg_state_2_sqmuxa_9_1743), + .LO(plm_fsm_N_10486_i) + ); + defparam plm_fsm_fsm_vector_N_10487_i.INIT = 16'h88F8; + LUT4_L plm_fsm_fsm_vector_N_10487_i ( + .I0(plm_fsm_reg_state1140), + .I1(plm_fsm_reg_state_19__1788), + .I2(plm_fsm_reg_state_3_sqmuxa_5_1_1744), + .I3(plm_fsm_xl_cls_timeout), + .LO(plm_fsm_N_10487_i) + ); + defparam plm_fsm_fsm_vector_N_10488_i.INIT = 16'hF0F4; + LUT4_L plm_fsm_fsm_vector_N_10488_i ( + .I0(plm_fsm_reg_state1140), + .I1(plm_fsm_reg_state_19__1788), + .I2(plm_fsm_reg_state_1_sqmuxa_2_1745), + .I3(plm_fsm_xl_cls_timeout), + .LO(plm_fsm_N_10488_i) + ); + defparam plm_fsm_fsm_vector_N_10489_i.INIT = 16'hF373; + LUT4_L plm_fsm_fsm_vector_N_10489_i ( + .I0(plm_fsm_N_10498), + .I1(plm_fsm_reg_state_141_0_0_1_iv_0_18_), + .I2(plm_fsm_reg_link_mode_1797), + .I3(plm_fsm_reg_state_2_sqmuxa_8_1746), + .LO(plm_fsm_N_10489_i) + ); + defparam plm_fsm_fsm_vector_N_10491_i.INIT = 16'h7350; + LUT4_L plm_fsm_fsm_vector_N_10491_i ( + .I0(plm_fsm_hr_restart_i), + .I1(plm_fsm_hr_timeout), + .I2(plm_fsm_reg_state_16__603), + .I3(plm_link_ctrl[0]), + .LO(plm_fsm_N_10491_i) + ); + defparam plm_fsm_fsm_vector_N_10373_i.INIT = 16'hFEFC; + LUT4_L plm_fsm_fsm_vector_N_10373_i ( + .I0(plm_fsm_N_62888), + .I1(plm_fsm_reg_rx_clear_cs_0_sqmuxa_3_1749), + .I2(plm_fsm_reg_rx_clear_cs_0_sqmuxa_5_1748), + .I3(plm_fsm_reg_rx_clear_cs_5_sqmuxa_2_1_1747), + .LO(plm_fsm_N_10373_i) + ); + defparam plm_fsm_fsm_vector_N_10492_i.INIT = 8'hBA; + LUT3_L plm_fsm_fsm_vector_N_10492_i ( + .I0(plm_fsm_reg_state_0_sqmuxa_8_i_0_1751), + .I1(plm_fsm_rc_timeout), + .I2(plm_fsm_reg_rx_clear_cs_3_sqmuxa_3_1_1750), + .LO(plm_fsm_N_10492_i) + ); + defparam plm_fsm_fsm_vector_N_10493_i.INIT = 16'hABAA; + LUT4_L plm_fsm_fsm_vector_N_10493_i ( + .I0(plm_fsm_reg_state_1_sqmuxa_4_i_0_1753), + .I1(plm_fsm_rc_cntrout_ts1_0), + .I2(plm_fsm_rc_timeout), + .I3(plm_fsm_reg_rx_clear_cs_1_sqmuxa_1_0_1752), + .LO(plm_fsm_N_10493_i) + ); + defparam plm_fsm_fsm_vector_N_10494_i.INIT = 16'h8F88; + LUT4_L plm_fsm_fsm_vector_N_10494_i ( + .I0(plm_fsm_N_38054), + .I1(plm_fsm_reg_rx_clear_cs230_1), + .I2(plm_fsm_l0_exit_reason_i), + .I3(plm_link_l0), + .LO(plm_fsm_N_10494_i) + ); + defparam plm_fsm_fsm_vector_N_85497_i.INIT = 16'hB333; + LUT4_L plm_fsm_fsm_vector_N_85497_i ( + .I0(plm_fsm_ri_idle_data_0_i_1754), + .I1(plm_fsm_reg_state_141_0_0_1_iv_i_0[12]), + .I2(plm_fsm_hr_restart_i), + .I3(plm_fsm_reg_state_16__603), + .LO(plm_fsm_N_85497_i) + ); + defparam plm_fsm_fsm_vector_N_10371_i.INIT = 8'h75; + LUT3_L plm_fsm_fsm_vector_N_10371_i ( + .I0(plm_fsm_N_11039), + .I1(plm_fsm_ci_timeout), + .I2(plm_fsm_reg_state_2_sqmuxa_3_1_1755), + .LO(plm_fsm_N_10371_i) + ); + defparam plm_fsm_fsm_vector_N_85478_i.INIT = 16'hBBB3; + LUT4_L plm_fsm_fsm_vector_N_85478_i ( + .I0(plm_fsm_N_61287_1_0), + .I1(plm_fsm_reg_state_141_0_0_1_iv_i_0_0_0[10]), + .I2(plm_fsm_reg_state_141_0_0_1_iv_i_0_0_a3_0_1[10]), + .I3(plm_fsm_reg_state_141_0_0_1_iv_i_0_0_a3_3[10]), + .LO(plm_fsm_N_85478_i) + ); + defparam plm_fsm_fsm_vector_reg_send_command_28_0_a2_0_a2_0_a2_0_a3_0_a2_2_.INIT = 4'h2; + LUT2_L plm_fsm_fsm_vector_reg_send_command_28_0_a2_0_a2_0_a2_0_a3_0_a2_2_ ( + .I0(plm_fsm_reg_send_command_28_1[0]), + .I1(plm_link_l0), + .LO(plm_fsm_reg_send_command_28_2_) + ); + defparam plm_fsm_fsm_vector_N_3265_i.INIT = 4'h7; + LUT2_L plm_fsm_fsm_vector_N_3265_i ( + .I0(plm_fsm_N_3265_1_0), + .I1(N_29556_i_1), + .LO(plm_fsm_N_3265_i) + ); + defparam plm_fsm_fsm_vector_reg_send_command_28_0_a2_0_a2_0_.INIT = 8'h80; + LUT3_L plm_fsm_fsm_vector_reg_send_command_28_0_a2_0_a2_0_ ( + .I0(plm_fsm_N_3265_1_0), + .I1(N_29556_i_1), + .I2(plm_fsm_reg_send_command_28_1[0]), + .LO(plm_fsm_reg_send_command_28_0_) + ); + defparam plm_fsm_fsm_vector_reg_noscramble_27.INIT = 16'h5150; + LUT4_L plm_fsm_fsm_vector_reg_noscramble_27 ( + .I0(plm_fsm_N_11039), + .I1(plm_fsm_N_58729), + .I2(cfg_cfg_6102[510]), + .I3(plm_rx0_linkctrl_3_), + .LO(plm_fsm_reg_noscramble_27) + ); + defparam plm_fsm_invert_state_reg_rx0_polarity_3.INIT = 4'h6; + LUT2_L plm_fsm_invert_state_reg_rx0_polarity_3 ( + .I0(plm_rx0_inverted), + .I1(plm_rx0_polarity), + .LO(plm_fsm_reg_rx0_polarity_3) + ); + defparam plm_fsm_invert_state_reg_rx1_polarity_3.INIT = 4'h6; + LUT2_L plm_fsm_invert_state_reg_rx1_polarity_3 ( + .I0(plm_rx1_inverted), + .I1(plm_rx1_polarity), + .LO(plm_fsm_reg_rx1_polarity_3) + ); + defparam plm_fsm_invert_state_reg_rx2_polarity_3.INIT = 4'h6; + LUT2_L plm_fsm_invert_state_reg_rx2_polarity_3 ( + .I0(plm_rx2_inverted), + .I1(plm_rx2_polarity), + .LO(plm_fsm_reg_rx2_polarity_3) + ); + defparam plm_fsm_invert_state_reg_rx3_polarity_3.INIT = 4'h6; + LUT2_L plm_fsm_invert_state_reg_rx3_polarity_3 ( + .I0(plm_rx3_inverted), + .I1(plm_rx3_polarity), + .LO(plm_fsm_reg_rx3_polarity_3) + ); + defparam plm_fsm_fsm_vector_reg_tx_link_num_14_7_.INIT = 4'h8; + LUT2_L plm_fsm_fsm_vector_reg_tx_link_num_14_7_ ( + .I0(plm_fsm_reg_rx_clear_cs_1_sqmuxa_5_1757), + .I1(plm_rx0_link_num[7]), + .LO(plm_fsm_reg_tx_link_num_14[7]) + ); + defparam plm_fsm_fsm_vector_reg_tx_link_num_14_6_.INIT = 4'h8; + LUT2_L plm_fsm_fsm_vector_reg_tx_link_num_14_6_ ( + .I0(plm_fsm_reg_rx_clear_cs_1_sqmuxa_5_1757), + .I1(plm_rx0_link_num[6]), + .LO(plm_fsm_reg_tx_link_num_14[6]) + ); + defparam plm_fsm_fsm_vector_reg_tx_link_num_14_5_.INIT = 4'h8; + LUT2_L plm_fsm_fsm_vector_reg_tx_link_num_14_5_ ( + .I0(plm_fsm_reg_rx_clear_cs_1_sqmuxa_5_1757), + .I1(plm_rx0_link_num[5]), + .LO(plm_fsm_reg_tx_link_num_14[5]) + ); + defparam plm_fsm_fsm_vector_reg_tx_link_num_14_4_.INIT = 4'h8; + LUT2_L plm_fsm_fsm_vector_reg_tx_link_num_14_4_ ( + .I0(plm_fsm_reg_rx_clear_cs_1_sqmuxa_5_1757), + .I1(plm_rx0_link_num[4]), + .LO(plm_fsm_reg_tx_link_num_14[4]) + ); + defparam plm_fsm_fsm_vector_reg_tx_link_num_14_3_.INIT = 4'h8; + LUT2_L plm_fsm_fsm_vector_reg_tx_link_num_14_3_ ( + .I0(plm_fsm_reg_rx_clear_cs_1_sqmuxa_5_1757), + .I1(plm_rx0_link_num[3]), + .LO(plm_fsm_reg_tx_link_num_14[3]) + ); + defparam plm_fsm_fsm_vector_reg_tx_link_num_14_2_.INIT = 4'h8; + LUT2_L plm_fsm_fsm_vector_reg_tx_link_num_14_2_ ( + .I0(plm_fsm_reg_rx_clear_cs_1_sqmuxa_5_1757), + .I1(plm_rx0_link_num[2]), + .LO(plm_fsm_reg_tx_link_num_14[2]) + ); + defparam plm_fsm_fsm_vector_reg_tx_link_num_14_0_a2_0_a3_0_a2_1_.INIT = 4'h8; + LUT2_L plm_fsm_fsm_vector_reg_tx_link_num_14_0_a2_0_a3_0_a2_1_ ( + .I0(plm_fsm_reg_rx_clear_cs_1_sqmuxa_5_1757), + .I1(plm_rx0_link_num[1]), + .LO(plm_fsm_reg_tx_link_num_14[1]) + ); + defparam plm_fsm_fsm_vector_reg_tx_link_num_14_0_a2_0_a3_0_a2_0_.INIT = 4'h8; + LUT2_L plm_fsm_fsm_vector_reg_tx_link_num_14_0_a2_0_a3_0_a2_0_ ( + .I0(plm_fsm_reg_rx_clear_cs_1_sqmuxa_5_1757), + .I1(plm_rx0_link_num[0]), + .LO(plm_fsm_reg_tx_link_num_14[0]) + ); + defparam plm_fsm_fsm_vector_N_9912_i.INIT = 16'h02FF; + LUT4_L plm_fsm_fsm_vector_N_9912_i ( + .I0(plm_fsm_N_5866_1_0), + .I1(plm_fsm_N_47500_i_0), + .I2(plm_fsm_N_58420), + .I3(plm_fsm_reg_123_lane_pad_35_iv_0), + .LO(plm_fsm_N_9912_i) + ); + defparam plm_fsm_N_85500_i.INIT = 16'hFEFF; + LUT4_L plm_fsm_N_85500_i ( + .I0(plm_fsm_N_59391), + .I1(plm_fsm_N_59392), + .I2(plm_fsm_reg_rx_clear_cs_4_sqmuxa_1_0), + .I3(plm_fsm_un1_reg_state_15_i_0_0_0_1756), + .LO(plm_fsm_N_85500_i_1803) + ); + defparam plm_fsm_fsm_vector_N_9435_i.INIT = 16'hCCCE; + LUT4_L plm_fsm_fsm_vector_N_9435_i ( + .I0(plm_fsm_N_5866), + .I1(plm_fsm_N_5868), + .I2(plm_fsm_N_47500_i_0), + .I3(plm_fsm_reg_rx_clear_cs_1_sqmuxa_5_1757), + .LO(plm_fsm_N_9435_i) + ); + defparam plm_fsm_un1_reg_state_22_i_0_0_0.INIT = 16'h1000; + LUT4_L plm_fsm_un1_reg_state_22_i_0_0_0 ( + .I0(plm_fsm_N_47500_i_0), + .I1(plm_fsm_N_58420), + .I2(plm_fsm_N_85520_1), + .I3(plm_fsm_un1_reg_state_22_i_0_0_0_1_1758), + .LO(plm_fsm_N_15218_i) + ); + defparam plm_fsm_N_57535_i.INIT = 4'h1; + LUT1_L plm_fsm_N_57535_i ( + .I0(l0_exit_reason_0_0_0_a2_2), + .LO(N_57535_i) + ); + defparam plm_fsm_fsm_vector_reg_state_141_0_0_1_iv_0_1_23_.INIT = 16'h00EC; + LUT4_L plm_fsm_fsm_vector_reg_state_141_0_0_1_iv_0_1_23_ ( + .I0(N_55989_i), + .I1(plm_fsm_N_60900), + .I2(plm_fsm_N_61276_1), + .I3(plm_rx0_lane_pad), + .LO(plm_fsm_reg_state_141_0_0_1_iv_0_1[23]) + ); + defparam plm_fsm_fsm_vector_reg_rx_clear_cs_98_0_0_1_iv_0_21_1.INIT = 16'h0013; + LUT4_L plm_fsm_fsm_vector_reg_rx_clear_cs_98_0_0_1_iv_0_21_1 ( + .I0(plm_fsm_N_7175_1), + .I1(plm_fsm_N_47500_i_0), + .I2(plm_fsm_N_57051), + .I3(plm_fsm_N_58420), + .LO(plm_fsm_reg_rx_clear_cs_98_0_0_1_iv_0_21_1) + ); + defparam plm_fsm_fsm_vector_reg_rx_clear_cs_98_0_0_1_iv_0_21.INIT = 16'h0080; + LUT4 plm_fsm_fsm_vector_reg_rx_clear_cs_98_0_0_1_iv_0_21 ( + .I0(plm_fsm_reg_rx_clear_cs_98_0_0_1_iv_0_15), + .I1(plm_fsm_reg_rx_clear_cs_98_0_0_1_iv_0_18), + .I2(plm_fsm_reg_rx_clear_cs_98_0_0_1_iv_0_21_1), + .I3(plm_fsm_reg_rx_clear_cs_0_sqmuxa_11_1759), + .O(plm_fsm_reg_rx_clear_cs_98_0_0_1_iv_0_21) + ); + defparam plm_fsm_reg_rx_clear_cs_2_sqmuxa_10_1_i_0_i_a3_i_1.INIT = 8'h73; + LUT3 plm_fsm_reg_rx_clear_cs_2_sqmuxa_10_1_i_0_i_a3_i_1 ( + .I0(plm_fsm_N_9911), + .I1(plm_fsm_N_60908_2), + .I2(plm_rx2_ts1_c), + .O(plm_fsm_reg_rx_clear_cs_2_sqmuxa_10_1_i_0_i_a3_i_1_1760) + ); + defparam plm_fsm_reg_rx_clear_cs_2_sqmuxa_10_1_i_0_i_a3_i.INIT = 16'h080C; + LUT4 plm_fsm_reg_rx_clear_cs_2_sqmuxa_10_1_i_0_i_a3_i ( + .I0(plm_fsm_N_9904), + .I1(plm_fsm_N_60908_1), + .I2(plm_fsm_reg_rx_clear_cs_2_sqmuxa_10_1_i_0_i_a3_i_1_1760), + .I3(plm_rx1_ts1_c), + .O(plm_fsm_N_54760_i) + ); + defparam plm_fsm_fsm_vector_reg_state_141_0_0_1_iv_i_0_0_0_1_10_.INIT = 16'h7FFF; + LUT4 plm_fsm_fsm_vector_reg_state_141_0_0_1_iv_i_0_0_0_1_10_ ( + .I0(cfg_cfg_6102[505]), + .I1(plm_fsm_pc_cntrout1), + .I2(plm_fsm_pc_cntrout2), + .I3(plm_fsm_pc_cntrout3), + .O(plm_fsm_reg_state_141_0_0_1_iv_i_0_0_0_1[10]) + ); + defparam plm_fsm_fsm_vector_reg_state_141_0_0_1_iv_i_0_0_0_10_.INIT = 16'h4555; + LUT4 plm_fsm_fsm_vector_reg_state_141_0_0_1_iv_i_0_0_0_10_ ( + .I0(plm_fsm_N_61291), + .I1(plm_fsm_reg_state_141_0_0_1_iv_i_0_0_0_1[10]), + .I2(plm_fsm_pc_cntrout0), + .I3(plm_fsm_reg_state_2__599), + .O(plm_fsm_reg_state_141_0_0_1_iv_i_0_0_0[10]) + ); + defparam plm_fsm_reg_rx_clear_cs_2_sqmuxa_11_1_0_o2_0_0_0_a2_0_1.INIT = 16'h7FBF; + LUT4_L plm_fsm_reg_rx_clear_cs_2_sqmuxa_11_1_0_o2_0_0_0_a2_0_1 ( + .I0(plm_fsm_reg_xl_rx3_old[8]), + .I1(plm_fsm_un3_xl_clw3_newv_NE_0_1762), + .I2(plm_fsm_un3_xl_clw3_newv_NE_1_1761), + .I3(plm_rx3_lane_pad), + .LO(plm_fsm_reg_rx_clear_cs_2_sqmuxa_11_1_0_o2_0_0_0_a2_0_1_1765) + ); + defparam plm_fsm_reg_rx_clear_cs_2_sqmuxa_11_1_0_o2_0_0_0_a2_0.INIT = 16'hBF00; + LUT4 plm_fsm_reg_rx_clear_cs_2_sqmuxa_11_1_0_o2_0_0_0_a2_0 ( + .I0(plm_fsm_reg_rx_clear_cs_2_sqmuxa_11_1_0_o2_0_0_0_a2_0_1_1765), + .I1(plm_fsm_un3_xl_clw3_newv_NE_2_1764), + .I2(plm_fsm_un3_xl_clw3_newv_NE_3_1763), + .I3(plm_rx3_ts1_c), + .O(plm_fsm_N_58785) + ); + defparam plm_fsm_reg_rx_clear_cs_2_sqmuxa_11_1_0_o2_0_0_0_a2_2_1.INIT = 16'h7FBF; + LUT4_L plm_fsm_reg_rx_clear_cs_2_sqmuxa_11_1_0_o2_0_0_0_a2_2_1 ( + .I0(plm_fsm_reg_xl_rx1_old[8]), + .I1(plm_fsm_un3_xl_clw1_newv_NE_0_1767), + .I2(plm_fsm_un3_xl_clw1_newv_NE_3_1766), + .I3(plm_rx1_lane_pad), + .LO(plm_fsm_reg_rx_clear_cs_2_sqmuxa_11_1_0_o2_0_0_0_a2_2_1_1770) + ); + defparam plm_fsm_reg_rx_clear_cs_2_sqmuxa_11_1_0_o2_0_0_0_a2_2.INIT = 16'hBF00; + LUT4 plm_fsm_reg_rx_clear_cs_2_sqmuxa_11_1_0_o2_0_0_0_a2_2 ( + .I0(plm_fsm_reg_rx_clear_cs_2_sqmuxa_11_1_0_o2_0_0_0_a2_2_1_1770), + .I1(plm_fsm_un3_xl_clw1_newv_NE_1_1769), + .I2(plm_fsm_un3_xl_clw1_newv_NE_2_1768), + .I3(plm_rx1_ts1_c), + .O(plm_fsm_N_58787) + ); + defparam plm_fsm_un3_xl_clw2_newv_NE_4_1.INIT = 16'h7BDE; + LUT4_L plm_fsm_un3_xl_clw2_newv_NE_4_1 ( + .I0(plm_fsm_reg_xl_rx2_old[0]), + .I1(plm_fsm_reg_xl_rx2_old[6]), + .I2(plm_rx2_lane_num[0]), + .I3(plm_rx2_lane_num[6]), + .LO(plm_fsm_un3_xl_clw2_newv_NE_4_1_1772) + ); + defparam plm_fsm_un3_xl_clw2_newv_NE_4.INIT = 8'h21; + LUT3 plm_fsm_un3_xl_clw2_newv_NE_4 ( + .I0(plm_fsm_reg_xl_rx2_old[8]), + .I1(plm_fsm_un3_xl_clw2_newv_NE_4_1_1772), + .I2(plm_rx2_lane_pad), + .O(plm_fsm_un3_xl_clw2_newv_NE_4_1771) + ); + defparam plm_fsm_un1_reg_state_19_i_0_o2_0_1.INIT = 4'h1; + LUT2 plm_fsm_un1_reg_state_19_i_0_o2_0_1 ( + .I0(plm_fsm_reg_state_14__1791), + .I1(plm_fsm_reg_state_15__1790), + .O(N_29556_i_1) + ); + defparam plm_fsm_N_45455_1_i.INIT = 4'hE; + LUT2 plm_fsm_N_45455_1_i ( + .I0(plm_fsm_reg_state_4__1780), + .I1(plm_fsm_reg_state_3__1781), + .O(plm_fsm_N_45455_1_i_1773) + ); + defparam plm_fsm_un1_reg_state_15_i_o3_0_i_a3_0_o3.INIT = 8'h80; + LUT3 plm_fsm_un1_reg_state_15_i_o3_0_i_a3_0_o3 ( + .I0(plm_fsm_N_55934_i), + .I1(plm_rx0_ts1_c), + .I2(plm_rx0_lane_pad), + .O(plm_fsm_N_56131_i) + ); + defparam plm_fsm_un1_reg_state_4_i_i.INIT = 8'hFE; + LUT3 plm_fsm_un1_reg_state_4_i_i ( + .I0(plm_fsm_reg_state_20__1787), + .I1(plm_fsm_reg_state_19__1788), + .I2(plm_fsm_reg_state_18__1789), + .O(plm_fsm_un1_reg_state_4_i_i_1774) + ); + defparam plm_fsm_fsm_vector_reg_rx_clear_cs_7_m_i.INIT = 8'hA2; + LUT3 plm_fsm_fsm_vector_reg_rx_clear_cs_7_m_i ( + .I0(plm_fsm_reg_state_1__425), + .I1(plm_fsm_N_63251), + .I2(plm_fsm_N_56356_i), + .O(plm_fsm_N_14468_i) + ); + defparam plm_fsm_reg_state_3_sqmuxa_4.INIT = 8'h08; + LUT3 plm_fsm_reg_state_3_sqmuxa_4 ( + .I0(plm_fsm_N_11041), + .I1(plm_fsm_reg_rx_clear_cs230_1), + .I2(plm_fsm_N_38054), + .O(plm_fsm_reg_state_3_sqmuxa_4_1775) + ); + FDCE plm_fsm_reg_link_up_2 ( + .CE(plm_fsm_N_60884_i_1793), + .C(mgt_clk), + .D(plm_fsm_reg_state_11__608), + .Q(plm_link_up_2), + .CLR(plm_rst) + ); + FDCE plm_fsm_reg_link_up_1 ( + .CE(plm_fsm_N_60884_i_1793), + .C(mgt_clk), + .D(plm_fsm_reg_state_11__608), + .Q(plm_link_up_1), + .CLR(plm_rst) + ); + FDCE plm_fsm_reg_sel_by1_1 ( + .CE(plm_fsm_N_60679_i_1794), + .C(mgt_clk), + .D(plm_fsm_reg_state_9__1795), + .Q(cmmp_negotiated_width_1[0]), + .CLR(plm_rst) + ); + FDC plm_fsm_reg_fix_polarity ( + .C(mgt_clk), + .D(plm_fsm_N_14468_i), + .Q(plm_fsm_reg_fix_polarity_1801), + .CLR(plm_rst) + ); + FDP plm_fsm_reg_123_txinhibit ( + .PRE(plm_rst), + .C(mgt_clk), + .D(plm_fsm_reg_state_0__1782), + .Q(plm_tx1_txinhibit) + ); + FDP plm_fsm_reg_rx_clear_cs ( + .PRE(plm_rst), + .C(mgt_clk), + .D(plm_fsm_N_9373_i), + .Q(plm_rx_clear_cs) + ); + FDC plm_fsm_reg_state_9_ ( + .C(mgt_clk), + .D(plm_fsm_N_10369_i), + .Q(plm_fsm_reg_state_9__1795), + .CLR(plm_rst) + ); + FDC plm_fsm_reg_state_8_ ( + .C(mgt_clk), + .D(plm_fsm_N_10368_i), + .Q(plm_fsm_reg_state_8__1776), + .CLR(plm_rst) + ); + FDC plm_fsm_reg_state_7_ ( + .C(mgt_clk), + .D(plm_fsm_N_85499_i), + .Q(plm_fsm_reg_state_7__1777), + .CLR(plm_rst) + ); + FDC plm_fsm_reg_state_6_ ( + .C(mgt_clk), + .D(plm_fsm_N_87557_i), + .Q(plm_fsm_reg_state_6__1778), + .CLR(plm_rst) + ); + FDC plm_fsm_reg_state_5_ ( + .C(mgt_clk), + .D(plm_fsm_N_10496_i), + .Q(plm_fsm_reg_state_5__1779), + .CLR(plm_rst) + ); + FDC plm_fsm_reg_state_4_ ( + .C(mgt_clk), + .D(plm_fsm_N_10497_i), + .Q(plm_fsm_reg_state_4__1780), + .CLR(plm_rst) + ); + FDC plm_fsm_reg_state_3_ ( + .C(mgt_clk), + .D(plm_fsm_N_10366_i), + .Q(plm_fsm_reg_state_3__1781), + .CLR(plm_rst) + ); + FDC plm_fsm_reg_state_2_ ( + .C(mgt_clk), + .D(plm_fsm_N_10365_i), + .Q(plm_fsm_reg_state_2__599), + .CLR(plm_rst) + ); + FDC plm_fsm_reg_state_1_ ( + .C(mgt_clk), + .D(plm_fsm_N_87545_i), + .Q(plm_fsm_reg_state_1__425), + .CLR(plm_rst) + ); + FDP plm_fsm_reg_state_0_ ( + .PRE(plm_rst), + .C(mgt_clk), + .D(plm_fsm_N_10364_i), + .Q(plm_fsm_reg_state_0__1782) + ); + FDC plm_fsm_reg_state_24_ ( + .C(mgt_clk), + .D(plm_fsm_N_85511_i), + .Q(plm_fsm_reg_state_24__1783), + .CLR(plm_rst) + ); + FDC plm_fsm_reg_state_23_ ( + .C(mgt_clk), + .D(plm_fsm_N_10374_i), + .Q(plm_fsm_reg_state_23__1784), + .CLR(plm_rst) + ); + FDC plm_fsm_reg_state_22_ ( + .C(mgt_clk), + .D(plm_fsm_N_10485_i), + .Q(plm_fsm_reg_state_22__1785), + .CLR(plm_rst) + ); + FDC plm_fsm_reg_state_21_ ( + .C(mgt_clk), + .D(plm_fsm_N_10486_i), + .Q(plm_fsm_reg_state_21__1786), + .CLR(plm_rst) + ); + FDC plm_fsm_reg_state_20_ ( + .C(mgt_clk), + .D(plm_fsm_N_10487_i), + .Q(plm_fsm_reg_state_20__1787), + .CLR(plm_rst) + ); + FDC plm_fsm_reg_state_19_ ( + .C(mgt_clk), + .D(plm_fsm_N_10488_i), + .Q(plm_fsm_reg_state_19__1788), + .CLR(plm_rst) + ); + FDC plm_fsm_reg_state_18_ ( + .C(mgt_clk), + .D(plm_fsm_N_10489_i), + .Q(plm_fsm_reg_state_18__1789), + .CLR(plm_rst) + ); + FDC plm_fsm_reg_state_17_ ( + .C(mgt_clk), + .D(plm_fsm_N_10491_i), + .Q(plm_link_ctrl[0]), + .CLR(plm_rst) + ); + FDC plm_fsm_reg_state_16_ ( + .C(mgt_clk), + .D(plm_fsm_N_10373_i), + .Q(plm_fsm_reg_state_16__603), + .CLR(plm_rst) + ); + FDC plm_fsm_reg_state_15_ ( + .C(mgt_clk), + .D(plm_fsm_N_10492_i), + .Q(plm_fsm_reg_state_15__1790), + .CLR(plm_rst) + ); + FDC plm_fsm_reg_state_14_ ( + .C(mgt_clk), + .D(plm_fsm_N_10493_i), + .Q(plm_fsm_reg_state_14__1791), + .CLR(plm_rst) + ); + FDC plm_fsm_reg_state_13_ ( + .C(mgt_clk), + .D(plm_fsm_N_10494_i), + .Q(plm_fsm_reg_state_13__76), + .CLR(plm_rst) + ); + FDC plm_fsm_reg_state_12_ ( + .C(mgt_clk), + .D(plm_fsm_N_85497_i), + .Q(plm_link_l0), + .CLR(plm_rst) + ); + FDC plm_fsm_reg_state_11_ ( + .C(mgt_clk), + .D(plm_fsm_N_10371_i), + .Q(plm_fsm_reg_state_11__608), + .CLR(plm_rst) + ); + FDC plm_fsm_reg_state_10_ ( + .C(mgt_clk), + .D(plm_fsm_N_85478_i), + .Q(plm_fsm_reg_state_10__1792), + .CLR(plm_rst) + ); + FDC plm_fsm_reg_send_command_2_ ( + .C(mgt_clk), + .D(plm_fsm_reg_send_command_28_2_), + .Q(plm_send_command[2]), + .CLR(plm_rst) + ); + FDC plm_fsm_reg_send_command_1_ ( + .C(mgt_clk), + .D(plm_fsm_N_3265_i), + .Q(plm_send_command[1]), + .CLR(plm_rst) + ); + FDC plm_fsm_reg_send_command_0_ ( + .C(mgt_clk), + .D(plm_fsm_reg_send_command_28_0_), + .Q(plm_send_command[0]), + .CLR(plm_rst) + ); + FDCE plm_fsm_reg_rx0_old_8_ ( + .CE(plm_fsm_N_61244_i), + .C(mgt_clk), + .D(plm_rx0_lane_pad), + .Q(plm_fsm_reg_rx0_old[8]), + .CLR(plm_rst) + ); + FDCE plm_fsm_reg_rx0_old_7_ ( + .CE(plm_fsm_N_61244_i), + .C(mgt_clk), + .D(plm_rx0_lane_num[7]), + .Q(plm_fsm_reg_rx0_old[7]), + .CLR(plm_rst) + ); + FDCE plm_fsm_reg_rx0_old_6_ ( + .CE(plm_fsm_N_61244_i), + .C(mgt_clk), + .D(plm_rx0_lane_num[6]), + .Q(plm_fsm_reg_rx0_old[6]), + .CLR(plm_rst) + ); + FDCE plm_fsm_reg_rx0_old_5_ ( + .CE(plm_fsm_N_61244_i), + .C(mgt_clk), + .D(plm_rx0_lane_num[5]), + .Q(plm_fsm_reg_rx0_old[5]), + .CLR(plm_rst) + ); + FDCE plm_fsm_reg_rx0_old_4_ ( + .CE(plm_fsm_N_61244_i), + .C(mgt_clk), + .D(plm_rx0_lane_num[4]), + .Q(plm_fsm_reg_rx0_old[4]), + .CLR(plm_rst) + ); + FDCE plm_fsm_reg_rx0_old_3_ ( + .CE(plm_fsm_N_61244_i), + .C(mgt_clk), + .D(plm_rx0_lane_num[3]), + .Q(plm_fsm_reg_rx0_old[3]), + .CLR(plm_rst) + ); + FDCE plm_fsm_reg_rx0_old_2_ ( + .CE(plm_fsm_N_61244_i), + .C(mgt_clk), + .D(plm_rx0_lane_num[2]), + .Q(plm_fsm_reg_rx0_old[2]), + .CLR(plm_rst) + ); + FDCE plm_fsm_reg_rx0_old_1_ ( + .CE(plm_fsm_N_61244_i), + .C(mgt_clk), + .D(plm_rx0_lane_num[1]), + .Q(plm_fsm_reg_rx0_old[1]), + .CLR(plm_rst) + ); + FDCE plm_fsm_reg_rx0_old_0_ ( + .CE(plm_fsm_N_61244_i), + .C(mgt_clk), + .D(plm_rx0_lane_num[0]), + .Q(plm_fsm_reg_rx0_old[0]), + .CLR(plm_rst) + ); + FDCE plm_fsm_reg_rx1_old_8_ ( + .CE(plm_fsm_N_61244_i), + .C(mgt_clk), + .D(plm_rx1_lane_pad), + .Q(plm_fsm_reg_rx1_old[8]), + .CLR(plm_rst) + ); + FDCE plm_fsm_reg_rx1_old_7_ ( + .CE(plm_fsm_N_61244_i), + .C(mgt_clk), + .D(plm_rx1_lane_num[7]), + .Q(plm_fsm_reg_rx1_old[7]), + .CLR(plm_rst) + ); + FDCE plm_fsm_reg_rx1_old_6_ ( + .CE(plm_fsm_N_61244_i), + .C(mgt_clk), + .D(plm_rx1_lane_num[6]), + .Q(plm_fsm_reg_rx1_old[6]), + .CLR(plm_rst) + ); + FDCE plm_fsm_reg_rx1_old_5_ ( + .CE(plm_fsm_N_61244_i), + .C(mgt_clk), + .D(plm_rx1_lane_num[5]), + .Q(plm_fsm_reg_rx1_old[5]), + .CLR(plm_rst) + ); + FDCE plm_fsm_reg_rx1_old_4_ ( + .CE(plm_fsm_N_61244_i), + .C(mgt_clk), + .D(plm_rx1_lane_num[4]), + .Q(plm_fsm_reg_rx1_old[4]), + .CLR(plm_rst) + ); + FDCE plm_fsm_reg_rx1_old_3_ ( + .CE(plm_fsm_N_61244_i), + .C(mgt_clk), + .D(plm_rx1_lane_num[3]), + .Q(plm_fsm_reg_rx1_old[3]), + .CLR(plm_rst) + ); + FDCE plm_fsm_reg_rx1_old_2_ ( + .CE(plm_fsm_N_61244_i), + .C(mgt_clk), + .D(plm_rx1_lane_num[2]), + .Q(plm_fsm_reg_rx1_old[2]), + .CLR(plm_rst) + ); + FDCE plm_fsm_reg_rx1_old_1_ ( + .CE(plm_fsm_N_61244_i), + .C(mgt_clk), + .D(plm_rx1_lane_num[1]), + .Q(plm_fsm_reg_rx1_old[1]), + .CLR(plm_rst) + ); + FDCE plm_fsm_reg_rx1_old_0_ ( + .CE(plm_fsm_N_61244_i), + .C(mgt_clk), + .D(plm_rx1_lane_num[0]), + .Q(plm_fsm_reg_rx1_old[0]), + .CLR(plm_rst) + ); + FDCE plm_fsm_reg_rx2_old_8_ ( + .CE(plm_fsm_N_61244_i), + .C(mgt_clk), + .D(plm_rx2_lane_pad), + .Q(plm_fsm_reg_rx2_old[8]), + .CLR(plm_rst) + ); + FDCE plm_fsm_reg_rx2_old_7_ ( + .CE(plm_fsm_N_61244_i), + .C(mgt_clk), + .D(plm_rx2_lane_num[7]), + .Q(plm_fsm_reg_rx2_old[7]), + .CLR(plm_rst) + ); + FDCE plm_fsm_reg_rx2_old_6_ ( + .CE(plm_fsm_N_61244_i), + .C(mgt_clk), + .D(plm_rx2_lane_num[6]), + .Q(plm_fsm_reg_rx2_old[6]), + .CLR(plm_rst) + ); + FDCE plm_fsm_reg_rx2_old_5_ ( + .CE(plm_fsm_N_61244_i), + .C(mgt_clk), + .D(plm_rx2_lane_num[5]), + .Q(plm_fsm_reg_rx2_old[5]), + .CLR(plm_rst) + ); + FDCE plm_fsm_reg_rx2_old_4_ ( + .CE(plm_fsm_N_61244_i), + .C(mgt_clk), + .D(plm_rx2_lane_num[4]), + .Q(plm_fsm_reg_rx2_old[4]), + .CLR(plm_rst) + ); + FDCE plm_fsm_reg_rx2_old_3_ ( + .CE(plm_fsm_N_61244_i), + .C(mgt_clk), + .D(plm_rx2_lane_num[3]), + .Q(plm_fsm_reg_rx2_old[3]), + .CLR(plm_rst) + ); + FDCE plm_fsm_reg_rx2_old_2_ ( + .CE(plm_fsm_N_61244_i), + .C(mgt_clk), + .D(plm_rx2_lane_num[2]), + .Q(plm_fsm_reg_rx2_old[2]), + .CLR(plm_rst) + ); + FDCE plm_fsm_reg_rx2_old_1_ ( + .CE(plm_fsm_N_61244_i), + .C(mgt_clk), + .D(plm_rx2_lane_num[1]), + .Q(plm_fsm_reg_rx2_old[1]), + .CLR(plm_rst) + ); + FDCE plm_fsm_reg_rx2_old_0_ ( + .CE(plm_fsm_N_61244_i), + .C(mgt_clk), + .D(plm_rx2_lane_num[0]), + .Q(plm_fsm_reg_rx2_old[0]), + .CLR(plm_rst) + ); + FDCE plm_fsm_reg_rx3_old_8_ ( + .CE(plm_fsm_N_61244_i), + .C(mgt_clk), + .D(plm_rx3_lane_pad), + .Q(plm_fsm_reg_rx3_old[8]), + .CLR(plm_rst) + ); + FDCE plm_fsm_reg_rx3_old_7_ ( + .CE(plm_fsm_N_61244_i), + .C(mgt_clk), + .D(plm_rx3_lane_num[7]), + .Q(plm_fsm_reg_rx3_old[7]), + .CLR(plm_rst) + ); + FDCE plm_fsm_reg_rx3_old_6_ ( + .CE(plm_fsm_N_61244_i), + .C(mgt_clk), + .D(plm_rx3_lane_num[6]), + .Q(plm_fsm_reg_rx3_old[6]), + .CLR(plm_rst) + ); + FDCE plm_fsm_reg_rx3_old_5_ ( + .CE(plm_fsm_N_61244_i), + .C(mgt_clk), + .D(plm_rx3_lane_num[5]), + .Q(plm_fsm_reg_rx3_old[5]), + .CLR(plm_rst) + ); + FDCE plm_fsm_reg_rx3_old_4_ ( + .CE(plm_fsm_N_61244_i), + .C(mgt_clk), + .D(plm_rx3_lane_num[4]), + .Q(plm_fsm_reg_rx3_old[4]), + .CLR(plm_rst) + ); + FDCE plm_fsm_reg_rx3_old_3_ ( + .CE(plm_fsm_N_61244_i), + .C(mgt_clk), + .D(plm_rx3_lane_num[3]), + .Q(plm_fsm_reg_rx3_old[3]), + .CLR(plm_rst) + ); + FDCE plm_fsm_reg_rx3_old_2_ ( + .CE(plm_fsm_N_61244_i), + .C(mgt_clk), + .D(plm_rx3_lane_num[2]), + .Q(plm_fsm_reg_rx3_old[2]), + .CLR(plm_rst) + ); + FDCE plm_fsm_reg_rx3_old_1_ ( + .CE(plm_fsm_N_61244_i), + .C(mgt_clk), + .D(plm_rx3_lane_num[1]), + .Q(plm_fsm_reg_rx3_old[1]), + .CLR(plm_rst) + ); + FDCE plm_fsm_reg_rx3_old_0_ ( + .CE(plm_fsm_N_61244_i), + .C(mgt_clk), + .D(plm_rx3_lane_num[0]), + .Q(plm_fsm_reg_rx3_old[0]), + .CLR(plm_rst) + ); + FDCE plm_fsm_reg_xl_rx0_old_8_ ( + .CE(plm_fsm_N_61243_i), + .C(mgt_clk), + .D(plm_rx0_lane_pad), + .Q(plm_fsm_reg_xl_rx0_old[8]), + .CLR(plm_rst) + ); + FDCE plm_fsm_reg_xl_rx0_old_7_ ( + .CE(plm_fsm_N_61243_i), + .C(mgt_clk), + .D(plm_rx0_lane_num[7]), + .Q(plm_fsm_reg_xl_rx0_old[7]), + .CLR(plm_rst) + ); + FDCE plm_fsm_reg_xl_rx0_old_6_ ( + .CE(plm_fsm_N_61243_i), + .C(mgt_clk), + .D(plm_rx0_lane_num[6]), + .Q(plm_fsm_reg_xl_rx0_old[6]), + .CLR(plm_rst) + ); + FDCE plm_fsm_reg_xl_rx0_old_5_ ( + .CE(plm_fsm_N_61243_i), + .C(mgt_clk), + .D(plm_rx0_lane_num[5]), + .Q(plm_fsm_reg_xl_rx0_old[5]), + .CLR(plm_rst) + ); + FDCE plm_fsm_reg_xl_rx0_old_4_ ( + .CE(plm_fsm_N_61243_i), + .C(mgt_clk), + .D(plm_rx0_lane_num[4]), + .Q(plm_fsm_reg_xl_rx0_old[4]), + .CLR(plm_rst) + ); + FDCE plm_fsm_reg_xl_rx0_old_3_ ( + .CE(plm_fsm_N_61243_i), + .C(mgt_clk), + .D(plm_rx0_lane_num[3]), + .Q(plm_fsm_reg_xl_rx0_old[3]), + .CLR(plm_rst) + ); + FDCE plm_fsm_reg_xl_rx0_old_2_ ( + .CE(plm_fsm_N_61243_i), + .C(mgt_clk), + .D(plm_rx0_lane_num[2]), + .Q(plm_fsm_reg_xl_rx0_old[2]), + .CLR(plm_rst) + ); + FDCE plm_fsm_reg_xl_rx0_old_1_ ( + .CE(plm_fsm_N_61243_i), + .C(mgt_clk), + .D(plm_rx0_lane_num[1]), + .Q(plm_fsm_reg_xl_rx0_old[1]), + .CLR(plm_rst) + ); + FDCE plm_fsm_reg_xl_rx0_old_0_ ( + .CE(plm_fsm_N_61243_i), + .C(mgt_clk), + .D(plm_rx0_lane_num[0]), + .Q(plm_fsm_reg_xl_rx0_old[0]), + .CLR(plm_rst) + ); + FDCE plm_fsm_reg_xl_rx1_old_8_ ( + .CE(plm_fsm_N_61243_i), + .C(mgt_clk), + .D(plm_rx1_lane_pad), + .Q(plm_fsm_reg_xl_rx1_old[8]), + .CLR(plm_rst) + ); + FDCE plm_fsm_reg_xl_rx1_old_7_ ( + .CE(plm_fsm_N_61243_i), + .C(mgt_clk), + .D(plm_rx1_lane_num[7]), + .Q(plm_fsm_reg_xl_rx1_old[7]), + .CLR(plm_rst) + ); + FDCE plm_fsm_reg_xl_rx1_old_6_ ( + .CE(plm_fsm_N_61243_i), + .C(mgt_clk), + .D(plm_rx1_lane_num[6]), + .Q(plm_fsm_reg_xl_rx1_old[6]), + .CLR(plm_rst) + ); + FDCE plm_fsm_reg_xl_rx1_old_5_ ( + .CE(plm_fsm_N_61243_i), + .C(mgt_clk), + .D(plm_rx1_lane_num[5]), + .Q(plm_fsm_reg_xl_rx1_old[5]), + .CLR(plm_rst) + ); + FDCE plm_fsm_reg_xl_rx1_old_4_ ( + .CE(plm_fsm_N_61243_i), + .C(mgt_clk), + .D(plm_rx1_lane_num[4]), + .Q(plm_fsm_reg_xl_rx1_old[4]), + .CLR(plm_rst) + ); + FDCE plm_fsm_reg_xl_rx1_old_3_ ( + .CE(plm_fsm_N_61243_i), + .C(mgt_clk), + .D(plm_rx1_lane_num[3]), + .Q(plm_fsm_reg_xl_rx1_old[3]), + .CLR(plm_rst) + ); + FDCE plm_fsm_reg_xl_rx1_old_2_ ( + .CE(plm_fsm_N_61243_i), + .C(mgt_clk), + .D(plm_rx1_lane_num[2]), + .Q(plm_fsm_reg_xl_rx1_old[2]), + .CLR(plm_rst) + ); + FDCE plm_fsm_reg_xl_rx1_old_1_ ( + .CE(plm_fsm_N_61243_i), + .C(mgt_clk), + .D(plm_rx1_lane_num[1]), + .Q(plm_fsm_reg_xl_rx1_old[1]), + .CLR(plm_rst) + ); + FDCE plm_fsm_reg_xl_rx1_old_0_ ( + .CE(plm_fsm_N_61243_i), + .C(mgt_clk), + .D(plm_rx1_lane_num[0]), + .Q(plm_fsm_reg_xl_rx1_old[0]), + .CLR(plm_rst) + ); + FDCE plm_fsm_reg_xl_rx2_old_8_ ( + .CE(plm_fsm_N_61243_i), + .C(mgt_clk), + .D(plm_rx2_lane_pad), + .Q(plm_fsm_reg_xl_rx2_old[8]), + .CLR(plm_rst) + ); + FDCE plm_fsm_reg_xl_rx2_old_7_ ( + .CE(plm_fsm_N_61243_i), + .C(mgt_clk), + .D(plm_rx2_lane_num[7]), + .Q(plm_fsm_reg_xl_rx2_old[7]), + .CLR(plm_rst) + ); + FDCE plm_fsm_reg_xl_rx2_old_6_ ( + .CE(plm_fsm_N_61243_i), + .C(mgt_clk), + .D(plm_rx2_lane_num[6]), + .Q(plm_fsm_reg_xl_rx2_old[6]), + .CLR(plm_rst) + ); + FDCE plm_fsm_reg_xl_rx2_old_5_ ( + .CE(plm_fsm_N_61243_i), + .C(mgt_clk), + .D(plm_rx2_lane_num[5]), + .Q(plm_fsm_reg_xl_rx2_old[5]), + .CLR(plm_rst) + ); + FDCE plm_fsm_reg_xl_rx2_old_4_ ( + .CE(plm_fsm_N_61243_i), + .C(mgt_clk), + .D(plm_rx2_lane_num[4]), + .Q(plm_fsm_reg_xl_rx2_old[4]), + .CLR(plm_rst) + ); + FDCE plm_fsm_reg_xl_rx2_old_3_ ( + .CE(plm_fsm_N_61243_i), + .C(mgt_clk), + .D(plm_rx2_lane_num[3]), + .Q(plm_fsm_reg_xl_rx2_old[3]), + .CLR(plm_rst) + ); + FDCE plm_fsm_reg_xl_rx2_old_2_ ( + .CE(plm_fsm_N_61243_i), + .C(mgt_clk), + .D(plm_rx2_lane_num[2]), + .Q(plm_fsm_reg_xl_rx2_old[2]), + .CLR(plm_rst) + ); + FDCE plm_fsm_reg_xl_rx2_old_1_ ( + .CE(plm_fsm_N_61243_i), + .C(mgt_clk), + .D(plm_rx2_lane_num[1]), + .Q(plm_fsm_reg_xl_rx2_old[1]), + .CLR(plm_rst) + ); + FDCE plm_fsm_reg_xl_rx2_old_0_ ( + .CE(plm_fsm_N_61243_i), + .C(mgt_clk), + .D(plm_rx2_lane_num[0]), + .Q(plm_fsm_reg_xl_rx2_old[0]), + .CLR(plm_rst) + ); + FDCE plm_fsm_reg_xl_rx3_old_8_ ( + .CE(plm_fsm_N_61243_i), + .C(mgt_clk), + .D(plm_rx3_lane_pad), + .Q(plm_fsm_reg_xl_rx3_old[8]), + .CLR(plm_rst) + ); + FDCE plm_fsm_reg_xl_rx3_old_7_ ( + .CE(plm_fsm_N_61243_i), + .C(mgt_clk), + .D(plm_rx3_lane_num[7]), + .Q(plm_fsm_reg_xl_rx3_old[7]), + .CLR(plm_rst) + ); + FDCE plm_fsm_reg_xl_rx3_old_6_ ( + .CE(plm_fsm_N_61243_i), + .C(mgt_clk), + .D(plm_rx3_lane_num[6]), + .Q(plm_fsm_reg_xl_rx3_old[6]), + .CLR(plm_rst) + ); + FDCE plm_fsm_reg_xl_rx3_old_5_ ( + .CE(plm_fsm_N_61243_i), + .C(mgt_clk), + .D(plm_rx3_lane_num[5]), + .Q(plm_fsm_reg_xl_rx3_old[5]), + .CLR(plm_rst) + ); + FDCE plm_fsm_reg_xl_rx3_old_4_ ( + .CE(plm_fsm_N_61243_i), + .C(mgt_clk), + .D(plm_rx3_lane_num[4]), + .Q(plm_fsm_reg_xl_rx3_old[4]), + .CLR(plm_rst) + ); + FDCE plm_fsm_reg_xl_rx3_old_3_ ( + .CE(plm_fsm_N_61243_i), + .C(mgt_clk), + .D(plm_rx3_lane_num[3]), + .Q(plm_fsm_reg_xl_rx3_old[3]), + .CLR(plm_rst) + ); + FDCE plm_fsm_reg_xl_rx3_old_2_ ( + .CE(plm_fsm_N_61243_i), + .C(mgt_clk), + .D(plm_rx3_lane_num[2]), + .Q(plm_fsm_reg_xl_rx3_old[2]), + .CLR(plm_rst) + ); + FDCE plm_fsm_reg_xl_rx3_old_1_ ( + .CE(plm_fsm_N_61243_i), + .C(mgt_clk), + .D(plm_rx3_lane_num[1]), + .Q(plm_fsm_reg_xl_rx3_old[1]), + .CLR(plm_rst) + ); + FDCE plm_fsm_reg_xl_rx3_old_0_ ( + .CE(plm_fsm_N_61243_i), + .C(mgt_clk), + .D(plm_rx3_lane_num[0]), + .Q(plm_fsm_reg_xl_rx3_old[0]), + .CLR(plm_rst) + ); + FDCE plm_fsm_reg_link_up ( + .CE(plm_fsm_N_60884_i_1793), + .C(mgt_clk), + .D(plm_fsm_reg_state_11__608), + .Q(plm_link_up), + .CLR(plm_rst) + ); + FDCE plm_fsm_reg_sel_by1 ( + .CE(plm_fsm_N_60679_i_1794), + .C(mgt_clk), + .D(plm_fsm_reg_state_9__1795), + .Q(cmmp_negotiated_width[0]), + .CLR(plm_rst) + ); + FDC plm_fsm_reg_link_mode ( + .C(mgt_clk), + .D(plm_fsm_VCC_1796), + .Q(plm_fsm_reg_link_mode_1797), + .CLR(plm_rst) + ); + FDCE plm_fsm_reg_noscramble ( + .CE(plm_fsm_un1_reg_state_8_0_a2_1798), + .C(mgt_clk), + .D(plm_fsm_reg_noscramble_27), + .Q(plm_noscramble), + .CLR(plm_rst) + ); + FDCE plm_fsm_reg_rl_throw_a_bone ( + .CE(plm_fsm_N_87223_i_1799), + .C(mgt_clk), + .D(plm_fsm_reg_state_13__76), + .Q(plm_fsm_reg_rl_throw_a_bone_1800), + .CLR(plm_rst) + ); + FDCE plm_fsm_reg_rx0_polarity ( + .CE(plm_fsm_reg_fix_polarity_1801), + .C(mgt_clk), + .D(plm_fsm_reg_rx0_polarity_3), + .Q(plm_rx0_polarity), + .CLR(plm_rst) + ); + FDCE plm_fsm_reg_rx1_polarity ( + .CE(plm_fsm_reg_fix_polarity_1801), + .C(mgt_clk), + .D(plm_fsm_reg_rx1_polarity_3), + .Q(plm_rx1_polarity), + .CLR(plm_rst) + ); + FDCE plm_fsm_reg_rx2_polarity ( + .CE(plm_fsm_reg_fix_polarity_1801), + .C(mgt_clk), + .D(plm_fsm_reg_rx2_polarity_3), + .Q(plm_rx2_polarity), + .CLR(plm_rst) + ); + FDCE plm_fsm_reg_rx3_polarity ( + .CE(plm_fsm_reg_fix_polarity_1801), + .C(mgt_clk), + .D(plm_fsm_reg_rx3_polarity_3), + .Q(plm_rx3_polarity), + .CLR(plm_rst) + ); + FDCE plm_fsm_reg_tx_link_num_7_ ( + .CE(plm_fsm_N_60883_i_1802), + .C(mgt_clk), + .D(plm_fsm_reg_tx_link_num_14[7]), + .Q(plm_tx1_link_num[7]), + .CLR(plm_rst) + ); + FDCE plm_fsm_reg_tx_link_num_6_ ( + .CE(plm_fsm_N_60883_i_1802), + .C(mgt_clk), + .D(plm_fsm_reg_tx_link_num_14[6]), + .Q(plm_tx1_link_num[6]), + .CLR(plm_rst) + ); + FDCE plm_fsm_reg_tx_link_num_5_ ( + .CE(plm_fsm_N_60883_i_1802), + .C(mgt_clk), + .D(plm_fsm_reg_tx_link_num_14[5]), + .Q(plm_tx1_link_num[5]), + .CLR(plm_rst) + ); + FDCE plm_fsm_reg_tx_link_num_4_ ( + .CE(plm_fsm_N_60883_i_1802), + .C(mgt_clk), + .D(plm_fsm_reg_tx_link_num_14[4]), + .Q(plm_tx1_link_num[4]), + .CLR(plm_rst) + ); + FDCE plm_fsm_reg_tx_link_num_3_ ( + .CE(plm_fsm_N_60883_i_1802), + .C(mgt_clk), + .D(plm_fsm_reg_tx_link_num_14[3]), + .Q(plm_tx1_link_num[3]), + .CLR(plm_rst) + ); + FDCE plm_fsm_reg_tx_link_num_2_ ( + .CE(plm_fsm_N_60883_i_1802), + .C(mgt_clk), + .D(plm_fsm_reg_tx_link_num_14[2]), + .Q(plm_tx1_link_num[2]), + .CLR(plm_rst) + ); + FDCE plm_fsm_reg_tx_link_num_1_ ( + .CE(plm_fsm_N_60883_i_1802), + .C(mgt_clk), + .D(plm_fsm_reg_tx_link_num_14[1]), + .Q(plm_tx1_link_num[1]), + .CLR(plm_rst) + ); + FDCE plm_fsm_reg_tx_link_num_0_ ( + .CE(plm_fsm_N_60883_i_1802), + .C(mgt_clk), + .D(plm_fsm_reg_tx_link_num_14[0]), + .Q(plm_tx1_link_num[0]), + .CLR(plm_rst) + ); + FDPE plm_fsm_reg_123_lane_pad ( + .PRE(plm_rst), + .CE(plm_fsm_N_47658_i), + .C(mgt_clk), + .D(plm_fsm_N_9912_i), + .Q(plm_tx2_lane_pad) + ); + FDPE plm_fsm_reg_tx0_link_pad ( + .PRE(plm_rst), + .CE(plm_fsm_N_15478_i), + .C(mgt_clk), + .D(plm_fsm_N_85500_i_1803), + .Q(plm_tx0_link_pad) + ); + FDPE plm_fsm_reg_123_link_pad ( + .PRE(plm_rst), + .CE(plm_fsm_N_15478_i), + .C(mgt_clk), + .D(plm_fsm_N_9435_i), + .Q(plm_tx2_link_pad) + ); + FDPE plm_fsm_reg_tx0_lane_pad ( + .PRE(plm_rst), + .CE(plm_fsm_N_47658_i), + .C(mgt_clk), + .D(plm_fsm_N_15218_i), + .Q(plm_tx0_lane_pad) + ); + INV plm_fsm_N_56513_i_i ( + .I(N_56513_i), + .O(plm_fsm_N_56513_i_i_1804) + ); + defparam plm_fsm_fsm_vector_reg_state_141_0_0_1_iv_0_23_.INIT = 16'h888F; + LUT4_L plm_fsm_fsm_vector_reg_state_141_0_0_1_iv_0_23_ ( + .I0(plm_fsm_N_21891_i), + .I1(plm_fsm_N_63400), + .I2(plm_fsm_reg_state_141_0_0_1_iv_0_1[23]), + .I3(plm_fsm_reg_state_141_0_0_1_iv_0_o2_0[23]), + .LO(plm_fsm_N_10374_i) + ); + GND plm_fsm_dq_timer_GND ( + .G(plm_fsm_dq_timer_GND_1805) + ); + MUXCY_L plm_fsm_dq_timer_reg_count_cry_0_ ( + .CI(plm_fsm_reg_state_0__1782), + .DI(plm_fsm_dq_timer_GND_1805), + .LO(plm_fsm_dq_timer_reg_count_cry[0]), + .S(plm_fsm_dq_timer_reg_count_qxu[0]) + ); + XORCY plm_fsm_dq_timer_reg_count_s_0_ ( + .CI(plm_fsm_reg_state_0__1782), + .LI(plm_fsm_dq_timer_reg_count_qxu[0]), + .O(plm_fsm_dq_timer_reg_count_s[0]) + ); + MUXCY_L plm_fsm_dq_timer_reg_count_cry_1_ ( + .CI(plm_fsm_dq_timer_reg_count_cry[0]), + .DI(plm_fsm_dq_timer_GND_1805), + .LO(plm_fsm_dq_timer_reg_count_cry[1]), + .S(plm_fsm_dq_timer_reg_count_qxu[1]) + ); + XORCY plm_fsm_dq_timer_reg_count_s_1_ ( + .CI(plm_fsm_dq_timer_reg_count_cry[0]), + .LI(plm_fsm_dq_timer_reg_count_qxu[1]), + .O(plm_fsm_dq_timer_reg_count_s[1]) + ); + MUXCY_L plm_fsm_dq_timer_reg_count_cry_2_ ( + .CI(plm_fsm_dq_timer_reg_count_cry[1]), + .DI(plm_fsm_dq_timer_GND_1805), + .LO(plm_fsm_dq_timer_reg_count_cry[2]), + .S(plm_fsm_dq_timer_reg_count_qxu[2]) + ); + XORCY plm_fsm_dq_timer_reg_count_s_2_ ( + .CI(plm_fsm_dq_timer_reg_count_cry[1]), + .LI(plm_fsm_dq_timer_reg_count_qxu[2]), + .O(plm_fsm_dq_timer_reg_count_s[2]) + ); + MUXCY_L plm_fsm_dq_timer_reg_count_cry_3_ ( + .CI(plm_fsm_dq_timer_reg_count_cry[2]), + .DI(plm_fsm_dq_timer_GND_1805), + .LO(plm_fsm_dq_timer_reg_count_cry[3]), + .S(plm_fsm_dq_timer_reg_count_qxu[3]) + ); + XORCY plm_fsm_dq_timer_reg_count_s_3_ ( + .CI(plm_fsm_dq_timer_reg_count_cry[2]), + .LI(plm_fsm_dq_timer_reg_count_qxu[3]), + .O(plm_fsm_dq_timer_reg_count_s[3]) + ); + MUXCY_L plm_fsm_dq_timer_reg_count_cry_4_ ( + .CI(plm_fsm_dq_timer_reg_count_cry[3]), + .DI(plm_fsm_dq_timer_GND_1805), + .LO(plm_fsm_dq_timer_reg_count_cry[4]), + .S(plm_fsm_dq_timer_reg_count_qxu[4]) + ); + XORCY plm_fsm_dq_timer_reg_count_s_4_ ( + .CI(plm_fsm_dq_timer_reg_count_cry[3]), + .LI(plm_fsm_dq_timer_reg_count_qxu[4]), + .O(plm_fsm_dq_timer_reg_count_s[4]) + ); + MUXCY_L plm_fsm_dq_timer_reg_count_cry_5_ ( + .CI(plm_fsm_dq_timer_reg_count_cry[4]), + .DI(plm_fsm_dq_timer_GND_1805), + .LO(plm_fsm_dq_timer_reg_count_cry[5]), + .S(plm_fsm_dq_timer_reg_count_qxu[5]) + ); + XORCY plm_fsm_dq_timer_reg_count_s_5_ ( + .CI(plm_fsm_dq_timer_reg_count_cry[4]), + .LI(plm_fsm_dq_timer_reg_count_qxu[5]), + .O(plm_fsm_dq_timer_reg_count_s[5]) + ); + MUXCY_L plm_fsm_dq_timer_reg_count_cry_6_ ( + .CI(plm_fsm_dq_timer_reg_count_cry[5]), + .DI(plm_fsm_dq_timer_GND_1805), + .LO(plm_fsm_dq_timer_reg_count_cry[6]), + .S(plm_fsm_dq_timer_reg_count_qxu[6]) + ); + XORCY plm_fsm_dq_timer_reg_count_s_6_ ( + .CI(plm_fsm_dq_timer_reg_count_cry[5]), + .LI(plm_fsm_dq_timer_reg_count_qxu[6]), + .O(plm_fsm_dq_timer_reg_count_s[6]) + ); + MUXCY_L plm_fsm_dq_timer_reg_count_cry_7_ ( + .CI(plm_fsm_dq_timer_reg_count_cry[6]), + .DI(plm_fsm_dq_timer_GND_1805), + .LO(plm_fsm_dq_timer_reg_count_cry[7]), + .S(plm_fsm_dq_timer_reg_count_qxu[7]) + ); + XORCY plm_fsm_dq_timer_reg_count_s_7_ ( + .CI(plm_fsm_dq_timer_reg_count_cry[6]), + .LI(plm_fsm_dq_timer_reg_count_qxu[7]), + .O(plm_fsm_dq_timer_reg_count_s[7]) + ); + MUXCY_L plm_fsm_dq_timer_reg_count_cry_8_ ( + .CI(plm_fsm_dq_timer_reg_count_cry[7]), + .DI(plm_fsm_dq_timer_GND_1805), + .LO(plm_fsm_dq_timer_reg_count_cry[8]), + .S(plm_fsm_dq_timer_reg_count_qxu[8]) + ); + XORCY plm_fsm_dq_timer_reg_count_s_8_ ( + .CI(plm_fsm_dq_timer_reg_count_cry[7]), + .LI(plm_fsm_dq_timer_reg_count_qxu[8]), + .O(plm_fsm_dq_timer_reg_count_s[8]) + ); + MUXCY_L plm_fsm_dq_timer_reg_count_cry_9_ ( + .CI(plm_fsm_dq_timer_reg_count_cry[8]), + .DI(plm_fsm_dq_timer_GND_1805), + .LO(plm_fsm_dq_timer_reg_count_cry[9]), + .S(plm_fsm_dq_timer_reg_count_qxu[9]) + ); + XORCY plm_fsm_dq_timer_reg_count_s_9_ ( + .CI(plm_fsm_dq_timer_reg_count_cry[8]), + .LI(plm_fsm_dq_timer_reg_count_qxu[9]), + .O(plm_fsm_dq_timer_reg_count_s[9]) + ); + MUXCY_L plm_fsm_dq_timer_reg_count_cry_10_ ( + .CI(plm_fsm_dq_timer_reg_count_cry[9]), + .DI(plm_fsm_dq_timer_GND_1805), + .LO(plm_fsm_dq_timer_reg_count_cry[10]), + .S(plm_fsm_dq_timer_reg_count_qxu[10]) + ); + XORCY plm_fsm_dq_timer_reg_count_s_10_ ( + .CI(plm_fsm_dq_timer_reg_count_cry[9]), + .LI(plm_fsm_dq_timer_reg_count_qxu[10]), + .O(plm_fsm_dq_timer_reg_count_s[10]) + ); + MUXCY_L plm_fsm_dq_timer_reg_count_cry_11_ ( + .CI(plm_fsm_dq_timer_reg_count_cry[10]), + .DI(plm_fsm_dq_timer_GND_1805), + .LO(plm_fsm_dq_timer_reg_count_cry[11]), + .S(plm_fsm_dq_timer_reg_count_qxu[11]) + ); + XORCY plm_fsm_dq_timer_reg_count_s_11_ ( + .CI(plm_fsm_dq_timer_reg_count_cry[10]), + .LI(plm_fsm_dq_timer_reg_count_qxu[11]), + .O(plm_fsm_dq_timer_reg_count_s[11]) + ); + MUXCY_L plm_fsm_dq_timer_reg_count_cry_12_ ( + .CI(plm_fsm_dq_timer_reg_count_cry[11]), + .DI(plm_fsm_dq_timer_GND_1805), + .LO(plm_fsm_dq_timer_reg_count_cry[12]), + .S(plm_fsm_dq_timer_reg_count_qxu[12]) + ); + XORCY plm_fsm_dq_timer_reg_count_s_12_ ( + .CI(plm_fsm_dq_timer_reg_count_cry[11]), + .LI(plm_fsm_dq_timer_reg_count_qxu[12]), + .O(plm_fsm_dq_timer_reg_count_s[12]) + ); + MUXCY_L plm_fsm_dq_timer_reg_count_cry_13_ ( + .CI(plm_fsm_dq_timer_reg_count_cry[12]), + .DI(plm_fsm_dq_timer_GND_1805), + .LO(plm_fsm_dq_timer_reg_count_cry[13]), + .S(plm_fsm_dq_timer_reg_count_qxu[13]) + ); + XORCY plm_fsm_dq_timer_reg_count_s_13_ ( + .CI(plm_fsm_dq_timer_reg_count_cry[12]), + .LI(plm_fsm_dq_timer_reg_count_qxu[13]), + .O(plm_fsm_dq_timer_reg_count_s[13]) + ); + MUXCY_L plm_fsm_dq_timer_reg_count_cry_14_ ( + .CI(plm_fsm_dq_timer_reg_count_cry[13]), + .DI(plm_fsm_dq_timer_GND_1805), + .LO(plm_fsm_dq_timer_reg_count_cry[14]), + .S(plm_fsm_dq_timer_reg_count_qxu[14]) + ); + XORCY plm_fsm_dq_timer_reg_count_s_14_ ( + .CI(plm_fsm_dq_timer_reg_count_cry[13]), + .LI(plm_fsm_dq_timer_reg_count_qxu[14]), + .O(plm_fsm_dq_timer_reg_count_s[14]) + ); + MUXCY_L plm_fsm_dq_timer_reg_count_cry_15_ ( + .CI(plm_fsm_dq_timer_reg_count_cry[14]), + .DI(plm_fsm_dq_timer_GND_1805), + .LO(plm_fsm_dq_timer_reg_count_cry[15]), + .S(plm_fsm_dq_timer_reg_count_qxu[15]) + ); + XORCY plm_fsm_dq_timer_reg_count_s_15_ ( + .CI(plm_fsm_dq_timer_reg_count_cry[14]), + .LI(plm_fsm_dq_timer_reg_count_qxu[15]), + .O(plm_fsm_dq_timer_reg_count_s[15]) + ); + MUXCY_L plm_fsm_dq_timer_reg_count_cry_16_ ( + .CI(plm_fsm_dq_timer_reg_count_cry[15]), + .DI(plm_fsm_dq_timer_GND_1805), + .LO(plm_fsm_dq_timer_reg_count_cry[16]), + .S(plm_fsm_dq_timer_reg_count_qxu[16]) + ); + XORCY plm_fsm_dq_timer_reg_count_s_16_ ( + .CI(plm_fsm_dq_timer_reg_count_cry[15]), + .LI(plm_fsm_dq_timer_reg_count_qxu[16]), + .O(plm_fsm_dq_timer_reg_count_s[16]) + ); + MUXCY_L plm_fsm_dq_timer_reg_count_cry_17_ ( + .CI(plm_fsm_dq_timer_reg_count_cry[16]), + .DI(plm_fsm_dq_timer_GND_1805), + .LO(plm_fsm_dq_timer_reg_count_cry[17]), + .S(plm_fsm_dq_timer_reg_count_qxu[17]) + ); + XORCY plm_fsm_dq_timer_reg_count_s_17_ ( + .CI(plm_fsm_dq_timer_reg_count_cry[16]), + .LI(plm_fsm_dq_timer_reg_count_qxu[17]), + .O(plm_fsm_dq_timer_reg_count_s[17]) + ); + MUXCY_L plm_fsm_dq_timer_reg_count_cry_18_ ( + .CI(plm_fsm_dq_timer_reg_count_cry[17]), + .DI(plm_fsm_dq_timer_GND_1805), + .LO(plm_fsm_dq_timer_reg_count_cry[18]), + .S(plm_fsm_dq_timer_reg_count_qxu[18]) + ); + XORCY plm_fsm_dq_timer_reg_count_s_18_ ( + .CI(plm_fsm_dq_timer_reg_count_cry[17]), + .LI(plm_fsm_dq_timer_reg_count_qxu[18]), + .O(plm_fsm_dq_timer_reg_count_s[18]) + ); + MUXCY_L plm_fsm_dq_timer_reg_count_cry_19_ ( + .CI(plm_fsm_dq_timer_reg_count_cry[18]), + .DI(plm_fsm_dq_timer_GND_1805), + .LO(plm_fsm_dq_timer_reg_count_cry[19]), + .S(plm_fsm_dq_timer_reg_count_qxu[19]) + ); + XORCY plm_fsm_dq_timer_reg_count_s_19_ ( + .CI(plm_fsm_dq_timer_reg_count_cry[18]), + .LI(plm_fsm_dq_timer_reg_count_qxu[19]), + .O(plm_fsm_dq_timer_reg_count_s[19]) + ); + MUXCY_L plm_fsm_dq_timer_reg_count_cry_20_ ( + .CI(plm_fsm_dq_timer_reg_count_cry[19]), + .DI(plm_fsm_dq_timer_GND_1805), + .LO(plm_fsm_dq_timer_reg_count_cry[20]), + .S(plm_fsm_dq_timer_reg_count_qxu[20]) + ); + XORCY plm_fsm_dq_timer_reg_count_s_20_ ( + .CI(plm_fsm_dq_timer_reg_count_cry[19]), + .LI(plm_fsm_dq_timer_reg_count_qxu[20]), + .O(plm_fsm_dq_timer_reg_count_s[20]) + ); + MUXCY_L plm_fsm_dq_timer_reg_count_cry_21_ ( + .CI(plm_fsm_dq_timer_reg_count_cry[20]), + .DI(plm_fsm_dq_timer_GND_1805), + .LO(plm_fsm_dq_timer_reg_count_cry[21]), + .S(plm_fsm_dq_timer_reg_count_qxu[21]) + ); + XORCY plm_fsm_dq_timer_reg_count_s_21_ ( + .CI(plm_fsm_dq_timer_reg_count_cry[20]), + .LI(plm_fsm_dq_timer_reg_count_qxu[21]), + .O(plm_fsm_dq_timer_reg_count_s[21]) + ); + XORCY plm_fsm_dq_timer_reg_count_s_22_ ( + .CI(plm_fsm_dq_timer_reg_count_cry[21]), + .LI(plm_fsm_dq_timer_reg_count_qxu[22]), + .O(plm_fsm_dq_timer_reg_count_s[22]) + ); + defparam plm_fsm_dq_timer_count_i_m3_i_m3_0_20_.INIT = 8'hD8; + LUT3 plm_fsm_dq_timer_count_i_m3_i_m3_0_20_ ( + .I0(cfg_cfg_6102[507]), + .I1(plm_fsm_dq_timer_reg_count[12]), + .I2(plm_fsm_dq_timer_reg_count[20]), + .O(plm_fsm_dq_timer_N_63724) + ); + defparam plm_fsm_dq_timer_count_i_m3_i_m3_0_19_.INIT = 8'hD8; + LUT3 plm_fsm_dq_timer_count_i_m3_i_m3_0_19_ ( + .I0(cfg_cfg_6102[507]), + .I1(plm_fsm_dq_timer_reg_count[11]), + .I2(plm_fsm_dq_timer_reg_count[19]), + .O(plm_fsm_dq_timer_N_63723) + ); + defparam plm_fsm_dq_timer_count_i_m3_i_m3_0_22_.INIT = 8'hD8; + LUT3 plm_fsm_dq_timer_count_i_m3_i_m3_0_22_ ( + .I0(cfg_cfg_6102[507]), + .I1(plm_fsm_dq_timer_reg_count[14]), + .I2(plm_fsm_dq_timer_reg_count[22]), + .O(plm_fsm_dq_timer_N_63726) + ); + defparam plm_fsm_dq_timer_count_i_m3_i_m3_0_21_.INIT = 8'hD8; + LUT3 plm_fsm_dq_timer_count_i_m3_i_m3_0_21_ ( + .I0(cfg_cfg_6102[507]), + .I1(plm_fsm_dq_timer_reg_count[13]), + .I2(plm_fsm_dq_timer_reg_count[21]), + .O(plm_fsm_dq_timer_N_63725) + ); + defparam plm_fsm_dq_timer_un1_expired_12ms_0_a2_0_a2.INIT = 16'h0007; + LUT4 plm_fsm_dq_timer_un1_expired_12ms_0_a2_0_a2 ( + .I0(plm_fsm_dq_timer_N_63723), + .I1(plm_fsm_dq_timer_N_63724), + .I2(plm_fsm_dq_timer_N_63725), + .I3(plm_fsm_dq_timer_N_63726), + .O(plm_fsm_N_63256) + ); + FDC plm_fsm_dq_timer_reg_count_22_ ( + .C(mgt_clk), + .D(plm_fsm_dq_timer_reg_count_s[22]), + .Q(plm_fsm_dq_timer_reg_count[22]), + .CLR(plm_rst) + ); + FDC plm_fsm_dq_timer_reg_count_21_ ( + .C(mgt_clk), + .D(plm_fsm_dq_timer_reg_count_s[21]), + .Q(plm_fsm_dq_timer_reg_count[21]), + .CLR(plm_rst) + ); + FDC plm_fsm_dq_timer_reg_count_20_ ( + .C(mgt_clk), + .D(plm_fsm_dq_timer_reg_count_s[20]), + .Q(plm_fsm_dq_timer_reg_count[20]), + .CLR(plm_rst) + ); + FDC plm_fsm_dq_timer_reg_count_19_ ( + .C(mgt_clk), + .D(plm_fsm_dq_timer_reg_count_s[19]), + .Q(plm_fsm_dq_timer_reg_count[19]), + .CLR(plm_rst) + ); + FDC plm_fsm_dq_timer_reg_count_18_ ( + .C(mgt_clk), + .D(plm_fsm_dq_timer_reg_count_s[18]), + .Q(plm_fsm_dq_timer_reg_count[18]), + .CLR(plm_rst) + ); + FDC plm_fsm_dq_timer_reg_count_17_ ( + .C(mgt_clk), + .D(plm_fsm_dq_timer_reg_count_s[17]), + .Q(plm_fsm_dq_timer_reg_count[17]), + .CLR(plm_rst) + ); + FDC plm_fsm_dq_timer_reg_count_16_ ( + .C(mgt_clk), + .D(plm_fsm_dq_timer_reg_count_s[16]), + .Q(plm_fsm_dq_timer_reg_count[16]), + .CLR(plm_rst) + ); + FDC plm_fsm_dq_timer_reg_count_15_ ( + .C(mgt_clk), + .D(plm_fsm_dq_timer_reg_count_s[15]), + .Q(plm_fsm_dq_timer_reg_count[15]), + .CLR(plm_rst) + ); + FDC plm_fsm_dq_timer_reg_count_14_ ( + .C(mgt_clk), + .D(plm_fsm_dq_timer_reg_count_s[14]), + .Q(plm_fsm_dq_timer_reg_count[14]), + .CLR(plm_rst) + ); + FDC plm_fsm_dq_timer_reg_count_13_ ( + .C(mgt_clk), + .D(plm_fsm_dq_timer_reg_count_s[13]), + .Q(plm_fsm_dq_timer_reg_count[13]), + .CLR(plm_rst) + ); + FDC plm_fsm_dq_timer_reg_count_12_ ( + .C(mgt_clk), + .D(plm_fsm_dq_timer_reg_count_s[12]), + .Q(plm_fsm_dq_timer_reg_count[12]), + .CLR(plm_rst) + ); + FDC plm_fsm_dq_timer_reg_count_11_ ( + .C(mgt_clk), + .D(plm_fsm_dq_timer_reg_count_s[11]), + .Q(plm_fsm_dq_timer_reg_count[11]), + .CLR(plm_rst) + ); + FDC plm_fsm_dq_timer_reg_count_10_ ( + .C(mgt_clk), + .D(plm_fsm_dq_timer_reg_count_s[10]), + .Q(plm_fsm_dq_timer_reg_count[10]), + .CLR(plm_rst) + ); + FDC plm_fsm_dq_timer_reg_count_9_ ( + .C(mgt_clk), + .D(plm_fsm_dq_timer_reg_count_s[9]), + .Q(plm_fsm_dq_timer_reg_count[9]), + .CLR(plm_rst) + ); + FDC plm_fsm_dq_timer_reg_count_8_ ( + .C(mgt_clk), + .D(plm_fsm_dq_timer_reg_count_s[8]), + .Q(plm_fsm_dq_timer_reg_count[8]), + .CLR(plm_rst) + ); + FDC plm_fsm_dq_timer_reg_count_7_ ( + .C(mgt_clk), + .D(plm_fsm_dq_timer_reg_count_s[7]), + .Q(plm_fsm_dq_timer_reg_count[7]), + .CLR(plm_rst) + ); + FDC plm_fsm_dq_timer_reg_count_6_ ( + .C(mgt_clk), + .D(plm_fsm_dq_timer_reg_count_s[6]), + .Q(plm_fsm_dq_timer_reg_count[6]), + .CLR(plm_rst) + ); + FDC plm_fsm_dq_timer_reg_count_5_ ( + .C(mgt_clk), + .D(plm_fsm_dq_timer_reg_count_s[5]), + .Q(plm_fsm_dq_timer_reg_count[5]), + .CLR(plm_rst) + ); + FDC plm_fsm_dq_timer_reg_count_4_ ( + .C(mgt_clk), + .D(plm_fsm_dq_timer_reg_count_s[4]), + .Q(plm_fsm_dq_timer_reg_count[4]), + .CLR(plm_rst) + ); + FDC plm_fsm_dq_timer_reg_count_3_ ( + .C(mgt_clk), + .D(plm_fsm_dq_timer_reg_count_s[3]), + .Q(plm_fsm_dq_timer_reg_count[3]), + .CLR(plm_rst) + ); + FDC plm_fsm_dq_timer_reg_count_2_ ( + .C(mgt_clk), + .D(plm_fsm_dq_timer_reg_count_s[2]), + .Q(plm_fsm_dq_timer_reg_count[2]), + .CLR(plm_rst) + ); + FDC plm_fsm_dq_timer_reg_count_1_ ( + .C(mgt_clk), + .D(plm_fsm_dq_timer_reg_count_s[1]), + .Q(plm_fsm_dq_timer_reg_count[1]), + .CLR(plm_rst) + ); + FDC plm_fsm_dq_timer_reg_count_0_ ( + .C(mgt_clk), + .D(plm_fsm_dq_timer_reg_count_s[0]), + .Q(plm_fsm_dq_timer_reg_count[0]), + .CLR(plm_rst) + ); + defparam plm_fsm_dq_timer_reg_count_qxu_0_0_.INIT = 4'h8; + LUT2_L plm_fsm_dq_timer_reg_count_qxu_0_0_ ( + .I0(plm_fsm_dq_timer_reg_count[0]), + .I1(plm_fsm_reg_state_0__1782), + .LO(plm_fsm_dq_timer_reg_count_qxu[0]) + ); + defparam plm_fsm_dq_timer_reg_count_qxu_0_1_.INIT = 4'h8; + LUT2_L plm_fsm_dq_timer_reg_count_qxu_0_1_ ( + .I0(plm_fsm_dq_timer_reg_count[1]), + .I1(plm_fsm_reg_state_0__1782), + .LO(plm_fsm_dq_timer_reg_count_qxu[1]) + ); + defparam plm_fsm_dq_timer_reg_count_qxu_0_2_.INIT = 4'h8; + LUT2_L plm_fsm_dq_timer_reg_count_qxu_0_2_ ( + .I0(plm_fsm_dq_timer_reg_count[2]), + .I1(plm_fsm_reg_state_0__1782), + .LO(plm_fsm_dq_timer_reg_count_qxu[2]) + ); + defparam plm_fsm_dq_timer_reg_count_qxu_0_3_.INIT = 4'h8; + LUT2_L plm_fsm_dq_timer_reg_count_qxu_0_3_ ( + .I0(plm_fsm_dq_timer_reg_count[3]), + .I1(plm_fsm_reg_state_0__1782), + .LO(plm_fsm_dq_timer_reg_count_qxu[3]) + ); + defparam plm_fsm_dq_timer_reg_count_qxu_0_4_.INIT = 4'h8; + LUT2_L plm_fsm_dq_timer_reg_count_qxu_0_4_ ( + .I0(plm_fsm_dq_timer_reg_count[4]), + .I1(plm_fsm_reg_state_0__1782), + .LO(plm_fsm_dq_timer_reg_count_qxu[4]) + ); + defparam plm_fsm_dq_timer_reg_count_qxu_0_5_.INIT = 4'h8; + LUT2_L plm_fsm_dq_timer_reg_count_qxu_0_5_ ( + .I0(plm_fsm_dq_timer_reg_count[5]), + .I1(plm_fsm_reg_state_0__1782), + .LO(plm_fsm_dq_timer_reg_count_qxu[5]) + ); + defparam plm_fsm_dq_timer_reg_count_qxu_0_6_.INIT = 4'h8; + LUT2_L plm_fsm_dq_timer_reg_count_qxu_0_6_ ( + .I0(plm_fsm_dq_timer_reg_count[6]), + .I1(plm_fsm_reg_state_0__1782), + .LO(plm_fsm_dq_timer_reg_count_qxu[6]) + ); + defparam plm_fsm_dq_timer_reg_count_qxu_0_7_.INIT = 4'h8; + LUT2_L plm_fsm_dq_timer_reg_count_qxu_0_7_ ( + .I0(plm_fsm_dq_timer_reg_count[7]), + .I1(plm_fsm_reg_state_0__1782), + .LO(plm_fsm_dq_timer_reg_count_qxu[7]) + ); + defparam plm_fsm_dq_timer_reg_count_qxu_0_8_.INIT = 4'h8; + LUT2_L plm_fsm_dq_timer_reg_count_qxu_0_8_ ( + .I0(plm_fsm_dq_timer_reg_count[8]), + .I1(plm_fsm_reg_state_0__1782), + .LO(plm_fsm_dq_timer_reg_count_qxu[8]) + ); + defparam plm_fsm_dq_timer_reg_count_qxu_0_9_.INIT = 4'h8; + LUT2_L plm_fsm_dq_timer_reg_count_qxu_0_9_ ( + .I0(plm_fsm_dq_timer_reg_count[9]), + .I1(plm_fsm_reg_state_0__1782), + .LO(plm_fsm_dq_timer_reg_count_qxu[9]) + ); + defparam plm_fsm_dq_timer_reg_count_qxu_0_10_.INIT = 4'h8; + LUT2_L plm_fsm_dq_timer_reg_count_qxu_0_10_ ( + .I0(plm_fsm_dq_timer_reg_count[10]), + .I1(plm_fsm_reg_state_0__1782), + .LO(plm_fsm_dq_timer_reg_count_qxu[10]) + ); + defparam plm_fsm_dq_timer_reg_count_qxu_0_11_.INIT = 4'h8; + LUT2_L plm_fsm_dq_timer_reg_count_qxu_0_11_ ( + .I0(plm_fsm_dq_timer_reg_count[11]), + .I1(plm_fsm_reg_state_0__1782), + .LO(plm_fsm_dq_timer_reg_count_qxu[11]) + ); + defparam plm_fsm_dq_timer_reg_count_qxu_0_12_.INIT = 4'h8; + LUT2_L plm_fsm_dq_timer_reg_count_qxu_0_12_ ( + .I0(plm_fsm_dq_timer_reg_count[12]), + .I1(plm_fsm_reg_state_0__1782), + .LO(plm_fsm_dq_timer_reg_count_qxu[12]) + ); + defparam plm_fsm_dq_timer_reg_count_qxu_0_13_.INIT = 4'h8; + LUT2_L plm_fsm_dq_timer_reg_count_qxu_0_13_ ( + .I0(plm_fsm_dq_timer_reg_count[13]), + .I1(plm_fsm_reg_state_0__1782), + .LO(plm_fsm_dq_timer_reg_count_qxu[13]) + ); + defparam plm_fsm_dq_timer_reg_count_qxu_0_14_.INIT = 4'h8; + LUT2_L plm_fsm_dq_timer_reg_count_qxu_0_14_ ( + .I0(plm_fsm_dq_timer_reg_count[14]), + .I1(plm_fsm_reg_state_0__1782), + .LO(plm_fsm_dq_timer_reg_count_qxu[14]) + ); + defparam plm_fsm_dq_timer_reg_count_qxu_0_15_.INIT = 4'h8; + LUT2_L plm_fsm_dq_timer_reg_count_qxu_0_15_ ( + .I0(plm_fsm_dq_timer_reg_count[15]), + .I1(plm_fsm_reg_state_0__1782), + .LO(plm_fsm_dq_timer_reg_count_qxu[15]) + ); + defparam plm_fsm_dq_timer_reg_count_qxu_0_16_.INIT = 4'h8; + LUT2_L plm_fsm_dq_timer_reg_count_qxu_0_16_ ( + .I0(plm_fsm_dq_timer_reg_count[16]), + .I1(plm_fsm_reg_state_0__1782), + .LO(plm_fsm_dq_timer_reg_count_qxu[16]) + ); + defparam plm_fsm_dq_timer_reg_count_qxu_0_17_.INIT = 4'h8; + LUT2_L plm_fsm_dq_timer_reg_count_qxu_0_17_ ( + .I0(plm_fsm_dq_timer_reg_count[17]), + .I1(plm_fsm_reg_state_0__1782), + .LO(plm_fsm_dq_timer_reg_count_qxu[17]) + ); + defparam plm_fsm_dq_timer_reg_count_qxu_0_18_.INIT = 4'h8; + LUT2_L plm_fsm_dq_timer_reg_count_qxu_0_18_ ( + .I0(plm_fsm_dq_timer_reg_count[18]), + .I1(plm_fsm_reg_state_0__1782), + .LO(plm_fsm_dq_timer_reg_count_qxu[18]) + ); + defparam plm_fsm_dq_timer_reg_count_qxu_0_19_.INIT = 4'h8; + LUT2_L plm_fsm_dq_timer_reg_count_qxu_0_19_ ( + .I0(plm_fsm_dq_timer_reg_count[19]), + .I1(plm_fsm_reg_state_0__1782), + .LO(plm_fsm_dq_timer_reg_count_qxu[19]) + ); + defparam plm_fsm_dq_timer_reg_count_qxu_0_20_.INIT = 4'h8; + LUT2_L plm_fsm_dq_timer_reg_count_qxu_0_20_ ( + .I0(plm_fsm_dq_timer_reg_count[20]), + .I1(plm_fsm_reg_state_0__1782), + .LO(plm_fsm_dq_timer_reg_count_qxu[20]) + ); + defparam plm_fsm_dq_timer_reg_count_qxu_0_21_.INIT = 4'h8; + LUT2_L plm_fsm_dq_timer_reg_count_qxu_0_21_ ( + .I0(plm_fsm_dq_timer_reg_count[21]), + .I1(plm_fsm_reg_state_0__1782), + .LO(plm_fsm_dq_timer_reg_count_qxu[21]) + ); + defparam plm_fsm_dq_timer_reg_count_qxu_0_22_.INIT = 4'h8; + LUT2_L plm_fsm_dq_timer_reg_count_qxu_0_22_ ( + .I0(plm_fsm_dq_timer_reg_count[22]), + .I1(plm_fsm_reg_state_0__1782), + .LO(plm_fsm_dq_timer_reg_count_qxu[22]) + ); + GND plm_fsm_pa_timer_GND ( + .G(plm_fsm_pa_timer_GND_1806) + ); + MUXCY_L plm_fsm_pa_timer_reg_count_cry_0_ ( + .CI(plm_fsm_reg_state_1__425), + .DI(plm_fsm_pa_timer_GND_1806), + .LO(plm_fsm_pa_timer_reg_count_cry[0]), + .S(plm_fsm_pa_timer_reg_count_qxu[0]) + ); + XORCY plm_fsm_pa_timer_reg_count_s_0_ ( + .CI(plm_fsm_reg_state_1__425), + .LI(plm_fsm_pa_timer_reg_count_qxu[0]), + .O(plm_fsm_pa_timer_reg_count_s[0]) + ); + MUXCY_L plm_fsm_pa_timer_reg_count_cry_1_ ( + .CI(plm_fsm_pa_timer_reg_count_cry[0]), + .DI(plm_fsm_pa_timer_GND_1806), + .LO(plm_fsm_pa_timer_reg_count_cry[1]), + .S(plm_fsm_pa_timer_reg_count_qxu[1]) + ); + XORCY plm_fsm_pa_timer_reg_count_s_1_ ( + .CI(plm_fsm_pa_timer_reg_count_cry[0]), + .LI(plm_fsm_pa_timer_reg_count_qxu[1]), + .O(plm_fsm_pa_timer_reg_count_s[1]) + ); + MUXCY_L plm_fsm_pa_timer_reg_count_cry_2_ ( + .CI(plm_fsm_pa_timer_reg_count_cry[1]), + .DI(plm_fsm_pa_timer_GND_1806), + .LO(plm_fsm_pa_timer_reg_count_cry[2]), + .S(plm_fsm_pa_timer_reg_count_qxu[2]) + ); + XORCY plm_fsm_pa_timer_reg_count_s_2_ ( + .CI(plm_fsm_pa_timer_reg_count_cry[1]), + .LI(plm_fsm_pa_timer_reg_count_qxu[2]), + .O(plm_fsm_pa_timer_reg_count_s[2]) + ); + MUXCY_L plm_fsm_pa_timer_reg_count_cry_3_ ( + .CI(plm_fsm_pa_timer_reg_count_cry[2]), + .DI(plm_fsm_pa_timer_GND_1806), + .LO(plm_fsm_pa_timer_reg_count_cry[3]), + .S(plm_fsm_pa_timer_reg_count_qxu[3]) + ); + XORCY plm_fsm_pa_timer_reg_count_s_3_ ( + .CI(plm_fsm_pa_timer_reg_count_cry[2]), + .LI(plm_fsm_pa_timer_reg_count_qxu[3]), + .O(plm_fsm_pa_timer_reg_count_s[3]) + ); + MUXCY_L plm_fsm_pa_timer_reg_count_cry_4_ ( + .CI(plm_fsm_pa_timer_reg_count_cry[3]), + .DI(plm_fsm_pa_timer_GND_1806), + .LO(plm_fsm_pa_timer_reg_count_cry[4]), + .S(plm_fsm_pa_timer_reg_count_qxu[4]) + ); + XORCY plm_fsm_pa_timer_reg_count_s_4_ ( + .CI(plm_fsm_pa_timer_reg_count_cry[3]), + .LI(plm_fsm_pa_timer_reg_count_qxu[4]), + .O(plm_fsm_pa_timer_reg_count_s[4]) + ); + MUXCY_L plm_fsm_pa_timer_reg_count_cry_5_ ( + .CI(plm_fsm_pa_timer_reg_count_cry[4]), + .DI(plm_fsm_pa_timer_GND_1806), + .LO(plm_fsm_pa_timer_reg_count_cry[5]), + .S(plm_fsm_pa_timer_reg_count_qxu[5]) + ); + XORCY plm_fsm_pa_timer_reg_count_s_5_ ( + .CI(plm_fsm_pa_timer_reg_count_cry[4]), + .LI(plm_fsm_pa_timer_reg_count_qxu[5]), + .O(plm_fsm_pa_timer_reg_count_s[5]) + ); + MUXCY_L plm_fsm_pa_timer_reg_count_cry_6_ ( + .CI(plm_fsm_pa_timer_reg_count_cry[5]), + .DI(plm_fsm_pa_timer_GND_1806), + .LO(plm_fsm_pa_timer_reg_count_cry[6]), + .S(plm_fsm_pa_timer_reg_count_qxu[6]) + ); + XORCY plm_fsm_pa_timer_reg_count_s_6_ ( + .CI(plm_fsm_pa_timer_reg_count_cry[5]), + .LI(plm_fsm_pa_timer_reg_count_qxu[6]), + .O(plm_fsm_pa_timer_reg_count_s[6]) + ); + MUXCY_L plm_fsm_pa_timer_reg_count_cry_7_ ( + .CI(plm_fsm_pa_timer_reg_count_cry[6]), + .DI(plm_fsm_pa_timer_GND_1806), + .LO(plm_fsm_pa_timer_reg_count_cry[7]), + .S(plm_fsm_pa_timer_reg_count_qxu[7]) + ); + XORCY plm_fsm_pa_timer_reg_count_s_7_ ( + .CI(plm_fsm_pa_timer_reg_count_cry[6]), + .LI(plm_fsm_pa_timer_reg_count_qxu[7]), + .O(plm_fsm_pa_timer_reg_count_s[7]) + ); + MUXCY_L plm_fsm_pa_timer_reg_count_cry_8_ ( + .CI(plm_fsm_pa_timer_reg_count_cry[7]), + .DI(plm_fsm_pa_timer_GND_1806), + .LO(plm_fsm_pa_timer_reg_count_cry[8]), + .S(plm_fsm_pa_timer_reg_count_qxu[8]) + ); + XORCY plm_fsm_pa_timer_reg_count_s_8_ ( + .CI(plm_fsm_pa_timer_reg_count_cry[7]), + .LI(plm_fsm_pa_timer_reg_count_qxu[8]), + .O(plm_fsm_pa_timer_reg_count_s[8]) + ); + MUXCY_L plm_fsm_pa_timer_reg_count_cry_9_ ( + .CI(plm_fsm_pa_timer_reg_count_cry[8]), + .DI(plm_fsm_pa_timer_GND_1806), + .LO(plm_fsm_pa_timer_reg_count_cry[9]), + .S(plm_fsm_pa_timer_reg_count_qxu[9]) + ); + XORCY plm_fsm_pa_timer_reg_count_s_9_ ( + .CI(plm_fsm_pa_timer_reg_count_cry[8]), + .LI(plm_fsm_pa_timer_reg_count_qxu[9]), + .O(plm_fsm_pa_timer_reg_count_s[9]) + ); + MUXCY_L plm_fsm_pa_timer_reg_count_cry_10_ ( + .CI(plm_fsm_pa_timer_reg_count_cry[9]), + .DI(plm_fsm_pa_timer_GND_1806), + .LO(plm_fsm_pa_timer_reg_count_cry[10]), + .S(plm_fsm_pa_timer_reg_count_qxu[10]) + ); + XORCY plm_fsm_pa_timer_reg_count_s_10_ ( + .CI(plm_fsm_pa_timer_reg_count_cry[9]), + .LI(plm_fsm_pa_timer_reg_count_qxu[10]), + .O(plm_fsm_pa_timer_reg_count_s[10]) + ); + MUXCY_L plm_fsm_pa_timer_reg_count_cry_11_ ( + .CI(plm_fsm_pa_timer_reg_count_cry[10]), + .DI(plm_fsm_pa_timer_GND_1806), + .LO(plm_fsm_pa_timer_reg_count_cry[11]), + .S(plm_fsm_pa_timer_reg_count_qxu[11]) + ); + XORCY plm_fsm_pa_timer_reg_count_s_11_ ( + .CI(plm_fsm_pa_timer_reg_count_cry[10]), + .LI(plm_fsm_pa_timer_reg_count_qxu[11]), + .O(plm_fsm_pa_timer_reg_count_s[11]) + ); + MUXCY_L plm_fsm_pa_timer_reg_count_cry_12_ ( + .CI(plm_fsm_pa_timer_reg_count_cry[11]), + .DI(plm_fsm_pa_timer_GND_1806), + .LO(plm_fsm_pa_timer_reg_count_cry[12]), + .S(plm_fsm_pa_timer_reg_count_qxu[12]) + ); + XORCY plm_fsm_pa_timer_reg_count_s_12_ ( + .CI(plm_fsm_pa_timer_reg_count_cry[11]), + .LI(plm_fsm_pa_timer_reg_count_qxu[12]), + .O(plm_fsm_pa_timer_reg_count_s[12]) + ); + MUXCY_L plm_fsm_pa_timer_reg_count_cry_13_ ( + .CI(plm_fsm_pa_timer_reg_count_cry[12]), + .DI(plm_fsm_pa_timer_GND_1806), + .LO(plm_fsm_pa_timer_reg_count_cry[13]), + .S(plm_fsm_pa_timer_reg_count_qxu[13]) + ); + XORCY plm_fsm_pa_timer_reg_count_s_13_ ( + .CI(plm_fsm_pa_timer_reg_count_cry[12]), + .LI(plm_fsm_pa_timer_reg_count_qxu[13]), + .O(plm_fsm_pa_timer_reg_count_s[13]) + ); + MUXCY_L plm_fsm_pa_timer_reg_count_cry_14_ ( + .CI(plm_fsm_pa_timer_reg_count_cry[13]), + .DI(plm_fsm_pa_timer_GND_1806), + .LO(plm_fsm_pa_timer_reg_count_cry[14]), + .S(plm_fsm_pa_timer_reg_count_qxu[14]) + ); + XORCY plm_fsm_pa_timer_reg_count_s_14_ ( + .CI(plm_fsm_pa_timer_reg_count_cry[13]), + .LI(plm_fsm_pa_timer_reg_count_qxu[14]), + .O(plm_fsm_pa_timer_reg_count_s[14]) + ); + MUXCY_L plm_fsm_pa_timer_reg_count_cry_15_ ( + .CI(plm_fsm_pa_timer_reg_count_cry[14]), + .DI(plm_fsm_pa_timer_GND_1806), + .LO(plm_fsm_pa_timer_reg_count_cry[15]), + .S(plm_fsm_pa_timer_reg_count_qxu[15]) + ); + XORCY plm_fsm_pa_timer_reg_count_s_15_ ( + .CI(plm_fsm_pa_timer_reg_count_cry[14]), + .LI(plm_fsm_pa_timer_reg_count_qxu[15]), + .O(plm_fsm_pa_timer_reg_count_s[15]) + ); + MUXCY_L plm_fsm_pa_timer_reg_count_cry_16_ ( + .CI(plm_fsm_pa_timer_reg_count_cry[15]), + .DI(plm_fsm_pa_timer_GND_1806), + .LO(plm_fsm_pa_timer_reg_count_cry[16]), + .S(plm_fsm_pa_timer_reg_count_qxu[16]) + ); + XORCY plm_fsm_pa_timer_reg_count_s_16_ ( + .CI(plm_fsm_pa_timer_reg_count_cry[15]), + .LI(plm_fsm_pa_timer_reg_count_qxu[16]), + .O(plm_fsm_pa_timer_reg_count_s[16]) + ); + MUXCY_L plm_fsm_pa_timer_reg_count_cry_17_ ( + .CI(plm_fsm_pa_timer_reg_count_cry[16]), + .DI(plm_fsm_pa_timer_GND_1806), + .LO(plm_fsm_pa_timer_reg_count_cry[17]), + .S(plm_fsm_pa_timer_reg_count_qxu[17]) + ); + XORCY plm_fsm_pa_timer_reg_count_s_17_ ( + .CI(plm_fsm_pa_timer_reg_count_cry[16]), + .LI(plm_fsm_pa_timer_reg_count_qxu[17]), + .O(plm_fsm_pa_timer_reg_count_s[17]) + ); + MUXCY_L plm_fsm_pa_timer_reg_count_cry_18_ ( + .CI(plm_fsm_pa_timer_reg_count_cry[17]), + .DI(plm_fsm_pa_timer_GND_1806), + .LO(plm_fsm_pa_timer_reg_count_cry[18]), + .S(plm_fsm_pa_timer_reg_count_qxu[18]) + ); + XORCY plm_fsm_pa_timer_reg_count_s_18_ ( + .CI(plm_fsm_pa_timer_reg_count_cry[17]), + .LI(plm_fsm_pa_timer_reg_count_qxu[18]), + .O(plm_fsm_pa_timer_reg_count_s[18]) + ); + MUXCY_L plm_fsm_pa_timer_reg_count_cry_19_ ( + .CI(plm_fsm_pa_timer_reg_count_cry[18]), + .DI(plm_fsm_pa_timer_GND_1806), + .LO(plm_fsm_pa_timer_reg_count_cry[19]), + .S(plm_fsm_pa_timer_reg_count_qxu[19]) + ); + XORCY plm_fsm_pa_timer_reg_count_s_19_ ( + .CI(plm_fsm_pa_timer_reg_count_cry[18]), + .LI(plm_fsm_pa_timer_reg_count_qxu[19]), + .O(plm_fsm_pa_timer_reg_count_s[19]) + ); + MUXCY_L plm_fsm_pa_timer_reg_count_cry_20_ ( + .CI(plm_fsm_pa_timer_reg_count_cry[19]), + .DI(plm_fsm_pa_timer_GND_1806), + .LO(plm_fsm_pa_timer_reg_count_cry[20]), + .S(plm_fsm_pa_timer_reg_count_qxu[20]) + ); + XORCY plm_fsm_pa_timer_reg_count_s_20_ ( + .CI(plm_fsm_pa_timer_reg_count_cry[19]), + .LI(plm_fsm_pa_timer_reg_count_qxu[20]), + .O(plm_fsm_pa_timer_reg_count_s[20]) + ); + MUXCY_L plm_fsm_pa_timer_reg_count_cry_21_ ( + .CI(plm_fsm_pa_timer_reg_count_cry[20]), + .DI(plm_fsm_pa_timer_GND_1806), + .LO(plm_fsm_pa_timer_reg_count_cry[21]), + .S(plm_fsm_pa_timer_reg_count_qxu[21]) + ); + XORCY plm_fsm_pa_timer_reg_count_s_21_ ( + .CI(plm_fsm_pa_timer_reg_count_cry[20]), + .LI(plm_fsm_pa_timer_reg_count_qxu[21]), + .O(plm_fsm_pa_timer_reg_count_s[21]) + ); + XORCY plm_fsm_pa_timer_reg_count_s_22_ ( + .CI(plm_fsm_pa_timer_reg_count_cry[21]), + .LI(plm_fsm_pa_timer_reg_count_qxu[22]), + .O(plm_fsm_pa_timer_reg_count_s[22]) + ); + defparam plm_fsm_pa_timer_count_i_m3_i_m3_0_20_.INIT = 8'hD8; + LUT3_L plm_fsm_pa_timer_count_i_m3_i_m3_0_20_ ( + .I0(cfg_cfg_6102[507]), + .I1(plm_fsm_pa_timer_reg_count[12]), + .I2(plm_fsm_pa_timer_reg_count[20]), + .LO(plm_fsm_pa_timer_N_63727) + ); + defparam plm_fsm_pa_timer_un3_expired_24ms_0_a2_0_a2.INIT = 16'hA280; + LUT4_L plm_fsm_pa_timer_un3_expired_24ms_0_a2_0_a2 ( + .I0(plm_fsm_pa_timer_N_63727), + .I1(cfg_cfg_6102[507]), + .I2(plm_fsm_pa_timer_reg_count[13]), + .I3(plm_fsm_pa_timer_reg_count[21]), + .LO(plm_fsm_pa_timer_N_63250) + ); + defparam plm_fsm_pa_timer_un1_expired_24ms_0_a2_0_a2.INIT = 16'h0415; + LUT4 plm_fsm_pa_timer_un1_expired_24ms_0_a2_0_a2 ( + .I0(plm_fsm_pa_timer_N_63250), + .I1(cfg_cfg_6102[507]), + .I2(plm_fsm_pa_timer_reg_count[14]), + .I3(plm_fsm_pa_timer_reg_count[22]), + .O(plm_fsm_N_63251) + ); + FDC plm_fsm_pa_timer_reg_count_22_ ( + .C(mgt_clk), + .D(plm_fsm_pa_timer_reg_count_s[22]), + .Q(plm_fsm_pa_timer_reg_count[22]), + .CLR(plm_rst) + ); + FDC plm_fsm_pa_timer_reg_count_21_ ( + .C(mgt_clk), + .D(plm_fsm_pa_timer_reg_count_s[21]), + .Q(plm_fsm_pa_timer_reg_count[21]), + .CLR(plm_rst) + ); + FDC plm_fsm_pa_timer_reg_count_20_ ( + .C(mgt_clk), + .D(plm_fsm_pa_timer_reg_count_s[20]), + .Q(plm_fsm_pa_timer_reg_count[20]), + .CLR(plm_rst) + ); + FDC plm_fsm_pa_timer_reg_count_19_ ( + .C(mgt_clk), + .D(plm_fsm_pa_timer_reg_count_s[19]), + .Q(plm_fsm_pa_timer_reg_count[19]), + .CLR(plm_rst) + ); + FDC plm_fsm_pa_timer_reg_count_18_ ( + .C(mgt_clk), + .D(plm_fsm_pa_timer_reg_count_s[18]), + .Q(plm_fsm_pa_timer_reg_count[18]), + .CLR(plm_rst) + ); + FDC plm_fsm_pa_timer_reg_count_17_ ( + .C(mgt_clk), + .D(plm_fsm_pa_timer_reg_count_s[17]), + .Q(plm_fsm_pa_timer_reg_count[17]), + .CLR(plm_rst) + ); + FDC plm_fsm_pa_timer_reg_count_16_ ( + .C(mgt_clk), + .D(plm_fsm_pa_timer_reg_count_s[16]), + .Q(plm_fsm_pa_timer_reg_count[16]), + .CLR(plm_rst) + ); + FDC plm_fsm_pa_timer_reg_count_15_ ( + .C(mgt_clk), + .D(plm_fsm_pa_timer_reg_count_s[15]), + .Q(plm_fsm_pa_timer_reg_count[15]), + .CLR(plm_rst) + ); + FDC plm_fsm_pa_timer_reg_count_14_ ( + .C(mgt_clk), + .D(plm_fsm_pa_timer_reg_count_s[14]), + .Q(plm_fsm_pa_timer_reg_count[14]), + .CLR(plm_rst) + ); + FDC plm_fsm_pa_timer_reg_count_13_ ( + .C(mgt_clk), + .D(plm_fsm_pa_timer_reg_count_s[13]), + .Q(plm_fsm_pa_timer_reg_count[13]), + .CLR(plm_rst) + ); + FDC plm_fsm_pa_timer_reg_count_12_ ( + .C(mgt_clk), + .D(plm_fsm_pa_timer_reg_count_s[12]), + .Q(plm_fsm_pa_timer_reg_count[12]), + .CLR(plm_rst) + ); + FDC plm_fsm_pa_timer_reg_count_11_ ( + .C(mgt_clk), + .D(plm_fsm_pa_timer_reg_count_s[11]), + .Q(plm_fsm_pa_timer_reg_count[11]), + .CLR(plm_rst) + ); + FDC plm_fsm_pa_timer_reg_count_10_ ( + .C(mgt_clk), + .D(plm_fsm_pa_timer_reg_count_s[10]), + .Q(plm_fsm_pa_timer_reg_count[10]), + .CLR(plm_rst) + ); + FDC plm_fsm_pa_timer_reg_count_9_ ( + .C(mgt_clk), + .D(plm_fsm_pa_timer_reg_count_s[9]), + .Q(plm_fsm_pa_timer_reg_count[9]), + .CLR(plm_rst) + ); + FDC plm_fsm_pa_timer_reg_count_8_ ( + .C(mgt_clk), + .D(plm_fsm_pa_timer_reg_count_s[8]), + .Q(plm_fsm_pa_timer_reg_count[8]), + .CLR(plm_rst) + ); + FDC plm_fsm_pa_timer_reg_count_7_ ( + .C(mgt_clk), + .D(plm_fsm_pa_timer_reg_count_s[7]), + .Q(plm_fsm_pa_timer_reg_count[7]), + .CLR(plm_rst) + ); + FDC plm_fsm_pa_timer_reg_count_6_ ( + .C(mgt_clk), + .D(plm_fsm_pa_timer_reg_count_s[6]), + .Q(plm_fsm_pa_timer_reg_count[6]), + .CLR(plm_rst) + ); + FDC plm_fsm_pa_timer_reg_count_5_ ( + .C(mgt_clk), + .D(plm_fsm_pa_timer_reg_count_s[5]), + .Q(plm_fsm_pa_timer_reg_count[5]), + .CLR(plm_rst) + ); + FDC plm_fsm_pa_timer_reg_count_4_ ( + .C(mgt_clk), + .D(plm_fsm_pa_timer_reg_count_s[4]), + .Q(plm_fsm_pa_timer_reg_count[4]), + .CLR(plm_rst) + ); + FDC plm_fsm_pa_timer_reg_count_3_ ( + .C(mgt_clk), + .D(plm_fsm_pa_timer_reg_count_s[3]), + .Q(plm_fsm_pa_timer_reg_count[3]), + .CLR(plm_rst) + ); + FDC plm_fsm_pa_timer_reg_count_2_ ( + .C(mgt_clk), + .D(plm_fsm_pa_timer_reg_count_s[2]), + .Q(plm_fsm_pa_timer_reg_count[2]), + .CLR(plm_rst) + ); + FDC plm_fsm_pa_timer_reg_count_1_ ( + .C(mgt_clk), + .D(plm_fsm_pa_timer_reg_count_s[1]), + .Q(plm_fsm_pa_timer_reg_count[1]), + .CLR(plm_rst) + ); + FDC plm_fsm_pa_timer_reg_count_0_ ( + .C(mgt_clk), + .D(plm_fsm_pa_timer_reg_count_s[0]), + .Q(plm_fsm_pa_timer_reg_count[0]), + .CLR(plm_rst) + ); + defparam plm_fsm_pa_timer_reg_count_qxu_0_0_.INIT = 4'h8; + LUT2_L plm_fsm_pa_timer_reg_count_qxu_0_0_ ( + .I0(plm_fsm_pa_timer_reg_count[0]), + .I1(plm_fsm_reg_state_1__425), + .LO(plm_fsm_pa_timer_reg_count_qxu[0]) + ); + defparam plm_fsm_pa_timer_reg_count_qxu_0_1_.INIT = 4'h8; + LUT2_L plm_fsm_pa_timer_reg_count_qxu_0_1_ ( + .I0(plm_fsm_pa_timer_reg_count[1]), + .I1(plm_fsm_reg_state_1__425), + .LO(plm_fsm_pa_timer_reg_count_qxu[1]) + ); + defparam plm_fsm_pa_timer_reg_count_qxu_0_2_.INIT = 4'h8; + LUT2_L plm_fsm_pa_timer_reg_count_qxu_0_2_ ( + .I0(plm_fsm_pa_timer_reg_count[2]), + .I1(plm_fsm_reg_state_1__425), + .LO(plm_fsm_pa_timer_reg_count_qxu[2]) + ); + defparam plm_fsm_pa_timer_reg_count_qxu_0_3_.INIT = 4'h8; + LUT2_L plm_fsm_pa_timer_reg_count_qxu_0_3_ ( + .I0(plm_fsm_pa_timer_reg_count[3]), + .I1(plm_fsm_reg_state_1__425), + .LO(plm_fsm_pa_timer_reg_count_qxu[3]) + ); + defparam plm_fsm_pa_timer_reg_count_qxu_0_4_.INIT = 4'h8; + LUT2_L plm_fsm_pa_timer_reg_count_qxu_0_4_ ( + .I0(plm_fsm_pa_timer_reg_count[4]), + .I1(plm_fsm_reg_state_1__425), + .LO(plm_fsm_pa_timer_reg_count_qxu[4]) + ); + defparam plm_fsm_pa_timer_reg_count_qxu_0_5_.INIT = 4'h8; + LUT2_L plm_fsm_pa_timer_reg_count_qxu_0_5_ ( + .I0(plm_fsm_pa_timer_reg_count[5]), + .I1(plm_fsm_reg_state_1__425), + .LO(plm_fsm_pa_timer_reg_count_qxu[5]) + ); + defparam plm_fsm_pa_timer_reg_count_qxu_0_6_.INIT = 4'h8; + LUT2_L plm_fsm_pa_timer_reg_count_qxu_0_6_ ( + .I0(plm_fsm_pa_timer_reg_count[6]), + .I1(plm_fsm_reg_state_1__425), + .LO(plm_fsm_pa_timer_reg_count_qxu[6]) + ); + defparam plm_fsm_pa_timer_reg_count_qxu_0_7_.INIT = 4'h8; + LUT2_L plm_fsm_pa_timer_reg_count_qxu_0_7_ ( + .I0(plm_fsm_pa_timer_reg_count[7]), + .I1(plm_fsm_reg_state_1__425), + .LO(plm_fsm_pa_timer_reg_count_qxu[7]) + ); + defparam plm_fsm_pa_timer_reg_count_qxu_0_8_.INIT = 4'h8; + LUT2_L plm_fsm_pa_timer_reg_count_qxu_0_8_ ( + .I0(plm_fsm_pa_timer_reg_count[8]), + .I1(plm_fsm_reg_state_1__425), + .LO(plm_fsm_pa_timer_reg_count_qxu[8]) + ); + defparam plm_fsm_pa_timer_reg_count_qxu_0_9_.INIT = 4'h8; + LUT2_L plm_fsm_pa_timer_reg_count_qxu_0_9_ ( + .I0(plm_fsm_pa_timer_reg_count[9]), + .I1(plm_fsm_reg_state_1__425), + .LO(plm_fsm_pa_timer_reg_count_qxu[9]) + ); + defparam plm_fsm_pa_timer_reg_count_qxu_0_10_.INIT = 4'h8; + LUT2_L plm_fsm_pa_timer_reg_count_qxu_0_10_ ( + .I0(plm_fsm_pa_timer_reg_count[10]), + .I1(plm_fsm_reg_state_1__425), + .LO(plm_fsm_pa_timer_reg_count_qxu[10]) + ); + defparam plm_fsm_pa_timer_reg_count_qxu_0_11_.INIT = 4'h8; + LUT2_L plm_fsm_pa_timer_reg_count_qxu_0_11_ ( + .I0(plm_fsm_pa_timer_reg_count[11]), + .I1(plm_fsm_reg_state_1__425), + .LO(plm_fsm_pa_timer_reg_count_qxu[11]) + ); + defparam plm_fsm_pa_timer_reg_count_qxu_0_12_.INIT = 4'h8; + LUT2_L plm_fsm_pa_timer_reg_count_qxu_0_12_ ( + .I0(plm_fsm_pa_timer_reg_count[12]), + .I1(plm_fsm_reg_state_1__425), + .LO(plm_fsm_pa_timer_reg_count_qxu[12]) + ); + defparam plm_fsm_pa_timer_reg_count_qxu_0_13_.INIT = 4'h8; + LUT2_L plm_fsm_pa_timer_reg_count_qxu_0_13_ ( + .I0(plm_fsm_pa_timer_reg_count[13]), + .I1(plm_fsm_reg_state_1__425), + .LO(plm_fsm_pa_timer_reg_count_qxu[13]) + ); + defparam plm_fsm_pa_timer_reg_count_qxu_0_14_.INIT = 4'h8; + LUT2_L plm_fsm_pa_timer_reg_count_qxu_0_14_ ( + .I0(plm_fsm_pa_timer_reg_count[14]), + .I1(plm_fsm_reg_state_1__425), + .LO(plm_fsm_pa_timer_reg_count_qxu[14]) + ); + defparam plm_fsm_pa_timer_reg_count_qxu_0_15_.INIT = 4'h8; + LUT2_L plm_fsm_pa_timer_reg_count_qxu_0_15_ ( + .I0(plm_fsm_pa_timer_reg_count[15]), + .I1(plm_fsm_reg_state_1__425), + .LO(plm_fsm_pa_timer_reg_count_qxu[15]) + ); + defparam plm_fsm_pa_timer_reg_count_qxu_0_16_.INIT = 4'h8; + LUT2_L plm_fsm_pa_timer_reg_count_qxu_0_16_ ( + .I0(plm_fsm_pa_timer_reg_count[16]), + .I1(plm_fsm_reg_state_1__425), + .LO(plm_fsm_pa_timer_reg_count_qxu[16]) + ); + defparam plm_fsm_pa_timer_reg_count_qxu_0_17_.INIT = 4'h8; + LUT2_L plm_fsm_pa_timer_reg_count_qxu_0_17_ ( + .I0(plm_fsm_pa_timer_reg_count[17]), + .I1(plm_fsm_reg_state_1__425), + .LO(plm_fsm_pa_timer_reg_count_qxu[17]) + ); + defparam plm_fsm_pa_timer_reg_count_qxu_0_18_.INIT = 4'h8; + LUT2_L plm_fsm_pa_timer_reg_count_qxu_0_18_ ( + .I0(plm_fsm_pa_timer_reg_count[18]), + .I1(plm_fsm_reg_state_1__425), + .LO(plm_fsm_pa_timer_reg_count_qxu[18]) + ); + defparam plm_fsm_pa_timer_reg_count_qxu_0_19_.INIT = 4'h8; + LUT2_L plm_fsm_pa_timer_reg_count_qxu_0_19_ ( + .I0(plm_fsm_pa_timer_reg_count[19]), + .I1(plm_fsm_reg_state_1__425), + .LO(plm_fsm_pa_timer_reg_count_qxu[19]) + ); + defparam plm_fsm_pa_timer_reg_count_qxu_0_20_.INIT = 4'h8; + LUT2_L plm_fsm_pa_timer_reg_count_qxu_0_20_ ( + .I0(plm_fsm_pa_timer_reg_count[20]), + .I1(plm_fsm_reg_state_1__425), + .LO(plm_fsm_pa_timer_reg_count_qxu[20]) + ); + defparam plm_fsm_pa_timer_reg_count_qxu_0_21_.INIT = 4'h8; + LUT2_L plm_fsm_pa_timer_reg_count_qxu_0_21_ ( + .I0(plm_fsm_pa_timer_reg_count[21]), + .I1(plm_fsm_reg_state_1__425), + .LO(plm_fsm_pa_timer_reg_count_qxu[21]) + ); + defparam plm_fsm_pa_timer_reg_count_qxu_0_22_.INIT = 4'h8; + LUT2_L plm_fsm_pa_timer_reg_count_qxu_0_22_ ( + .I0(plm_fsm_pa_timer_reg_count[22]), + .I1(plm_fsm_reg_state_1__425), + .LO(plm_fsm_pa_timer_reg_count_qxu[22]) + ); + VCC plm_fsm_pa_counter0_VCC ( + .P(plm_fsm_pa_counter0_VCC_1807) + ); + MUXCY_L plm_fsm_pa_counter0_reg_rx_count_cry_0_ ( + .CI(N_15205_i_i_29), + .DI(plm_fsm_pa_counter0_VCC_1807), + .LO(plm_fsm_pa_counter0_reg_rx_count_cry[0]), + .S(plm_fsm_pa_counter0_reg_rx_count_qxu[0]) + ); + XORCY plm_fsm_pa_counter0_reg_rx_count_s_0_ ( + .CI(N_15205_i_i_29), + .LI(plm_fsm_pa_counter0_reg_rx_count_qxu[0]), + .O(plm_fsm_pa_counter0_reg_rx_count_s[0]) + ); + MUXCY_L plm_fsm_pa_counter0_reg_rx_count_cry_1_ ( + .CI(plm_fsm_pa_counter0_reg_rx_count_cry[0]), + .DI(plm_fsm_pa_counter0_VCC_1807), + .LO(plm_fsm_pa_counter0_reg_rx_count_cry[1]), + .S(plm_fsm_pa_counter0_reg_rx_count_qxu[1]) + ); + XORCY plm_fsm_pa_counter0_reg_rx_count_s_1_ ( + .CI(plm_fsm_pa_counter0_reg_rx_count_cry[0]), + .LI(plm_fsm_pa_counter0_reg_rx_count_qxu[1]), + .O(plm_fsm_pa_counter0_reg_rx_count_s[1]) + ); + MUXCY_L plm_fsm_pa_counter0_reg_rx_count_cry_2_ ( + .CI(plm_fsm_pa_counter0_reg_rx_count_cry[1]), + .DI(plm_fsm_pa_counter0_VCC_1807), + .LO(plm_fsm_pa_counter0_reg_rx_count_cry[2]), + .S(plm_fsm_pa_counter0_reg_rx_count_qxu[2]) + ); + XORCY plm_fsm_pa_counter0_reg_rx_count_s_2_ ( + .CI(plm_fsm_pa_counter0_reg_rx_count_cry[1]), + .LI(plm_fsm_pa_counter0_reg_rx_count_qxu[2]), + .O(plm_fsm_pa_counter0_reg_rx_count_s[2]) + ); + MUXCY_L plm_fsm_pa_counter0_reg_rx_count_cry_3_ ( + .CI(plm_fsm_pa_counter0_reg_rx_count_cry[2]), + .DI(plm_fsm_pa_counter0_VCC_1807), + .LO(plm_fsm_pa_counter0_reg_rx_count_cry[3]), + .S(plm_fsm_pa_counter0_reg_rx_count_qxu[3]) + ); + XORCY plm_fsm_pa_counter0_reg_rx_count_s_3_ ( + .CI(plm_fsm_pa_counter0_reg_rx_count_cry[2]), + .LI(plm_fsm_pa_counter0_reg_rx_count_qxu[3]), + .O(plm_fsm_pa_counter0_reg_rx_count_s[3]) + ); + MUXCY_L plm_fsm_pa_counter0_reg_rx_count_cry_4_ ( + .CI(plm_fsm_pa_counter0_reg_rx_count_cry[3]), + .DI(plm_fsm_pa_counter0_VCC_1807), + .LO(plm_fsm_pa_counter0_reg_rx_count_cry[4]), + .S(plm_fsm_pa_counter0_reg_rx_count_qxu[4]) + ); + XORCY plm_fsm_pa_counter0_reg_rx_count_s_4_ ( + .CI(plm_fsm_pa_counter0_reg_rx_count_cry[3]), + .LI(plm_fsm_pa_counter0_reg_rx_count_qxu[4]), + .O(plm_fsm_pa_counter0_reg_rx_count_s[4]) + ); + MUXCY_L plm_fsm_pa_counter0_reg_rx_count_cry_5_ ( + .CI(plm_fsm_pa_counter0_reg_rx_count_cry[4]), + .DI(plm_fsm_pa_counter0_VCC_1807), + .LO(plm_fsm_pa_counter0_reg_rx_count_cry[5]), + .S(plm_fsm_pa_counter0_reg_rx_count_qxu[5]) + ); + XORCY plm_fsm_pa_counter0_reg_rx_count_s_5_ ( + .CI(plm_fsm_pa_counter0_reg_rx_count_cry[4]), + .LI(plm_fsm_pa_counter0_reg_rx_count_qxu[5]), + .O(plm_fsm_pa_counter0_reg_rx_count_s[5]) + ); + MUXCY_L plm_fsm_pa_counter0_reg_rx_count_cry_6_ ( + .CI(plm_fsm_pa_counter0_reg_rx_count_cry[5]), + .DI(plm_fsm_pa_counter0_VCC_1807), + .LO(plm_fsm_pa_counter0_reg_rx_count_cry[6]), + .S(plm_fsm_pa_counter0_reg_rx_count_qxu[6]) + ); + XORCY plm_fsm_pa_counter0_reg_rx_count_s_6_ ( + .CI(plm_fsm_pa_counter0_reg_rx_count_cry[5]), + .LI(plm_fsm_pa_counter0_reg_rx_count_qxu[6]), + .O(plm_fsm_pa_counter0_reg_rx_count_s[6]) + ); + XORCY plm_fsm_pa_counter0_reg_rx_count_s_7_ ( + .CI(plm_fsm_pa_counter0_reg_rx_count_cry[6]), + .LI(plm_fsm_pa_counter0_reg_rx_count_qxu[7]), + .O(plm_fsm_pa_counter0_reg_rx_count_s[7]) + ); + MUXCY_L plm_fsm_pa_counter0_reg_tx_count_cry_0_ ( + .CI(plm_fsm_pa_counter0_un1_enable_1_i_1808), + .DI(plm_fsm_pa_counter0_VCC_1807), + .LO(plm_fsm_pa_counter0_reg_tx_count_cry[0]), + .S(plm_fsm_pa_counter0_reg_tx_count_qxu[0]) + ); + XORCY plm_fsm_pa_counter0_reg_tx_count_s_0_ ( + .CI(plm_fsm_pa_counter0_un1_enable_1_i_1808), + .LI(plm_fsm_pa_counter0_reg_tx_count_qxu[0]), + .O(plm_fsm_pa_counter0_reg_tx_count_s[0]) + ); + MUXCY_L plm_fsm_pa_counter0_reg_tx_count_cry_1_ ( + .CI(plm_fsm_pa_counter0_reg_tx_count_cry[0]), + .DI(plm_fsm_pa_counter0_VCC_1807), + .LO(plm_fsm_pa_counter0_reg_tx_count_cry[1]), + .S(plm_fsm_pa_counter0_reg_tx_count_qxu[1]) + ); + XORCY plm_fsm_pa_counter0_reg_tx_count_s_1_ ( + .CI(plm_fsm_pa_counter0_reg_tx_count_cry[0]), + .LI(plm_fsm_pa_counter0_reg_tx_count_qxu[1]), + .O(plm_fsm_pa_counter0_reg_tx_count_s[1]) + ); + MUXCY_L plm_fsm_pa_counter0_reg_tx_count_cry_2_ ( + .CI(plm_fsm_pa_counter0_reg_tx_count_cry[1]), + .DI(plm_fsm_pa_counter0_VCC_1807), + .LO(plm_fsm_pa_counter0_reg_tx_count_cry[2]), + .S(plm_fsm_pa_counter0_reg_tx_count_qxu[2]) + ); + XORCY plm_fsm_pa_counter0_reg_tx_count_s_2_ ( + .CI(plm_fsm_pa_counter0_reg_tx_count_cry[1]), + .LI(plm_fsm_pa_counter0_reg_tx_count_qxu[2]), + .O(plm_fsm_pa_counter0_reg_tx_count_s[2]) + ); + MUXCY_L plm_fsm_pa_counter0_reg_tx_count_cry_3_ ( + .CI(plm_fsm_pa_counter0_reg_tx_count_cry[2]), + .DI(plm_fsm_pa_counter0_VCC_1807), + .LO(plm_fsm_pa_counter0_reg_tx_count_cry[3]), + .S(plm_fsm_pa_counter0_reg_tx_count_qxu[3]) + ); + XORCY plm_fsm_pa_counter0_reg_tx_count_s_3_ ( + .CI(plm_fsm_pa_counter0_reg_tx_count_cry[2]), + .LI(plm_fsm_pa_counter0_reg_tx_count_qxu[3]), + .O(plm_fsm_pa_counter0_reg_tx_count_s[3]) + ); + MUXCY_L plm_fsm_pa_counter0_reg_tx_count_cry_4_ ( + .CI(plm_fsm_pa_counter0_reg_tx_count_cry[3]), + .DI(plm_fsm_pa_counter0_VCC_1807), + .LO(plm_fsm_pa_counter0_reg_tx_count_cry[4]), + .S(plm_fsm_pa_counter0_reg_tx_count_qxu[4]) + ); + XORCY plm_fsm_pa_counter0_reg_tx_count_s_4_ ( + .CI(plm_fsm_pa_counter0_reg_tx_count_cry[3]), + .LI(plm_fsm_pa_counter0_reg_tx_count_qxu[4]), + .O(plm_fsm_pa_counter0_reg_tx_count_s[4]) + ); + MUXCY_L plm_fsm_pa_counter0_reg_tx_count_cry_5_ ( + .CI(plm_fsm_pa_counter0_reg_tx_count_cry[4]), + .DI(plm_fsm_pa_counter0_VCC_1807), + .LO(plm_fsm_pa_counter0_reg_tx_count_cry[5]), + .S(plm_fsm_pa_counter0_reg_tx_count_qxu[5]) + ); + XORCY plm_fsm_pa_counter0_reg_tx_count_s_5_ ( + .CI(plm_fsm_pa_counter0_reg_tx_count_cry[4]), + .LI(plm_fsm_pa_counter0_reg_tx_count_qxu[5]), + .O(plm_fsm_pa_counter0_reg_tx_count_s[5]) + ); + MUXCY_L plm_fsm_pa_counter0_reg_tx_count_cry_6_ ( + .CI(plm_fsm_pa_counter0_reg_tx_count_cry[5]), + .DI(plm_fsm_pa_counter0_VCC_1807), + .LO(plm_fsm_pa_counter0_reg_tx_count_cry[6]), + .S(plm_fsm_pa_counter0_reg_tx_count_qxu[6]) + ); + XORCY plm_fsm_pa_counter0_reg_tx_count_s_6_ ( + .CI(plm_fsm_pa_counter0_reg_tx_count_cry[5]), + .LI(plm_fsm_pa_counter0_reg_tx_count_qxu[6]), + .O(plm_fsm_pa_counter0_reg_tx_count_s[6]) + ); + MUXCY_L plm_fsm_pa_counter0_reg_tx_count_cry_7_ ( + .CI(plm_fsm_pa_counter0_reg_tx_count_cry[6]), + .DI(plm_fsm_pa_counter0_VCC_1807), + .LO(plm_fsm_pa_counter0_reg_tx_count_cry[7]), + .S(plm_fsm_pa_counter0_reg_tx_count_qxu[7]) + ); + XORCY plm_fsm_pa_counter0_reg_tx_count_s_7_ ( + .CI(plm_fsm_pa_counter0_reg_tx_count_cry[6]), + .LI(plm_fsm_pa_counter0_reg_tx_count_qxu[7]), + .O(plm_fsm_pa_counter0_reg_tx_count_s[7]) + ); + MUXCY_L plm_fsm_pa_counter0_reg_tx_count_cry_8_ ( + .CI(plm_fsm_pa_counter0_reg_tx_count_cry[7]), + .DI(plm_fsm_pa_counter0_VCC_1807), + .LO(plm_fsm_pa_counter0_reg_tx_count_cry[8]), + .S(plm_fsm_pa_counter0_reg_tx_count_qxu[8]) + ); + XORCY plm_fsm_pa_counter0_reg_tx_count_s_8_ ( + .CI(plm_fsm_pa_counter0_reg_tx_count_cry[7]), + .LI(plm_fsm_pa_counter0_reg_tx_count_qxu[8]), + .O(plm_fsm_pa_counter0_reg_tx_count_s[8]) + ); + MUXCY_L plm_fsm_pa_counter0_reg_tx_count_cry_9_ ( + .CI(plm_fsm_pa_counter0_reg_tx_count_cry[8]), + .DI(plm_fsm_pa_counter0_VCC_1807), + .LO(plm_fsm_pa_counter0_reg_tx_count_cry[9]), + .S(plm_fsm_pa_counter0_reg_tx_count_qxu[9]) + ); + XORCY plm_fsm_pa_counter0_reg_tx_count_s_9_ ( + .CI(plm_fsm_pa_counter0_reg_tx_count_cry[8]), + .LI(plm_fsm_pa_counter0_reg_tx_count_qxu[9]), + .O(plm_fsm_pa_counter0_reg_tx_count_s[9]) + ); + MUXCY_L plm_fsm_pa_counter0_reg_tx_count_cry_10_ ( + .CI(plm_fsm_pa_counter0_reg_tx_count_cry[9]), + .DI(plm_fsm_pa_counter0_VCC_1807), + .LO(plm_fsm_pa_counter0_reg_tx_count_cry[10]), + .S(plm_fsm_pa_counter0_reg_tx_count_qxu[10]) + ); + XORCY plm_fsm_pa_counter0_reg_tx_count_s_10_ ( + .CI(plm_fsm_pa_counter0_reg_tx_count_cry[9]), + .LI(plm_fsm_pa_counter0_reg_tx_count_qxu[10]), + .O(plm_fsm_pa_counter0_reg_tx_count_s[10]) + ); + XORCY plm_fsm_pa_counter0_reg_tx_count_s_11_ ( + .CI(plm_fsm_pa_counter0_reg_tx_count_cry[10]), + .LI(plm_fsm_pa_counter0_reg_tx_count_qxu[11]), + .O(plm_fsm_pa_counter0_reg_tx_count_s[11]) + ); + defparam plm_fsm_pa_counter0_un1_enable_1_0_a2_0_a2_0_a2_0_a3_0_a2.INIT = 4'h4; + LUT2 plm_fsm_pa_counter0_un1_enable_1_0_a2_0_a2_0_a2_0_a3_0_a2 ( + .I0(plm_fsm_pa_counter0_reg_tx_expired_1810), + .I1(plm_fsm_reg_state_1__425), + .O(plm_fsm_pa_counter0_un1_enable_1) + ); + defparam plm_fsm_pa_counter0_un1_enable_2_i_i_0_0_a2_0.INIT = 4'h8; + LUT2 plm_fsm_pa_counter0_un1_enable_2_i_i_0_0_a2_0 ( + .I0(plm_fsm_pa_counter0_reg_rx_expired_424), + .I1(plm_fsm_reg_state_1__425), + .O(plm_fsm_pa_counter0_N_59124) + ); + defparam plm_fsm_pa_counter0_loadable_rx_counter_un1_reg_rx_count_0_a2_4.INIT = 16'h0001; + LUT4 plm_fsm_pa_counter0_loadable_rx_counter_un1_reg_rx_count_0_a2_4 ( + .I0(plm_fsm_pa_counter0_reg_rx_count[0]), + .I1(plm_fsm_pa_counter0_reg_rx_count[1]), + .I2(plm_fsm_pa_counter0_reg_rx_count[2]), + .I3(plm_fsm_pa_counter0_reg_rx_count[3]), + .O(plm_fsm_pa_counter0_un1_reg_rx_count_0_a2_4) + ); + defparam plm_fsm_pa_counter0_loadable_rx_counter_un1_reg_rx_count_0_a2_5.INIT = 16'h0001; + LUT4 plm_fsm_pa_counter0_loadable_rx_counter_un1_reg_rx_count_0_a2_5 ( + .I0(plm_fsm_pa_counter0_reg_rx_count[4]), + .I1(plm_fsm_pa_counter0_reg_rx_count[5]), + .I2(plm_fsm_pa_counter0_reg_rx_count[6]), + .I3(plm_fsm_pa_counter0_reg_rx_count[7]), + .O(plm_fsm_pa_counter0_un1_reg_rx_count_0_a2_5) + ); + defparam plm_fsm_pa_counter0_loadable_tx_counter_un1_reg_tx_count_0_a2_6.INIT = 16'h0001; + LUT4 plm_fsm_pa_counter0_loadable_tx_counter_un1_reg_tx_count_0_a2_6 ( + .I0(plm_fsm_pa_counter0_reg_tx_count[0]), + .I1(plm_fsm_pa_counter0_reg_tx_count[1]), + .I2(plm_fsm_pa_counter0_reg_tx_count[2]), + .I3(plm_fsm_pa_counter0_reg_tx_count[3]), + .O(plm_fsm_pa_counter0_un1_reg_tx_count_0_a2_6) + ); + defparam plm_fsm_pa_counter0_loadable_tx_counter_un1_reg_tx_count_0_a2_7.INIT = 16'h0001; + LUT4 plm_fsm_pa_counter0_loadable_tx_counter_un1_reg_tx_count_0_a2_7 ( + .I0(plm_fsm_pa_counter0_reg_tx_count[4]), + .I1(plm_fsm_pa_counter0_reg_tx_count[5]), + .I2(plm_fsm_pa_counter0_reg_tx_count[6]), + .I3(plm_fsm_pa_counter0_reg_tx_count[7]), + .O(plm_fsm_pa_counter0_un1_reg_tx_count_0_a2_7) + ); + defparam plm_fsm_pa_counter0_loadable_tx_counter_un1_reg_tx_count_0_a2_8.INIT = 16'h0001; + LUT4 plm_fsm_pa_counter0_loadable_tx_counter_un1_reg_tx_count_0_a2_8 ( + .I0(plm_fsm_pa_counter0_reg_tx_count[8]), + .I1(plm_fsm_pa_counter0_reg_tx_count[9]), + .I2(plm_fsm_pa_counter0_reg_tx_count[10]), + .I3(plm_fsm_pa_counter0_reg_tx_count[11]), + .O(plm_fsm_pa_counter0_un1_reg_tx_count_0_a2_8) + ); + defparam plm_fsm_pa_counter0_N_61004_i.INIT = 4'hB; + LUT2 plm_fsm_pa_counter0_N_61004_i ( + .I0(plm_reg_sym_sent_5_), + .I1(plm_fsm_pa_counter0_un1_enable_1), + .O(plm_fsm_pa_counter0_N_61004_i_1809) + ); + defparam plm_fsm_pa_counter0_loadable_rx_counter_un1_reg_rx_expired_1_i.INIT = 8'hDF; + LUT3 plm_fsm_pa_counter0_loadable_rx_counter_un1_reg_rx_expired_1_i ( + .I0(plm_fsm_N_56187_i), + .I1(plm_fsm_pa_counter0_reg_rx_expired_424), + .I2(plm_fsm_reg_state_1__425), + .O(plm_fsm_pa_counter0_un1_reg_rx_expired_1_i) + ); + defparam plm_fsm_pa_counter0_un1_enable_2_i_i_0_0.INIT = 16'h0105; + LUT4_L plm_fsm_pa_counter0_un1_enable_2_i_i_0_0 ( + .I0(N_15205_i), + .I1(plm_fsm_N_56187_i), + .I2(plm_fsm_pa_counter0_N_59124), + .I3(plm_fsm_reg_state_1__425), + .LO(plm_fsm_pa_counter0_N_28855_i) + ); + defparam plm_fsm_pa_counter0_loadable_rx_counter_N_60994_i.INIT = 8'h8F; + LUT3 plm_fsm_pa_counter0_loadable_rx_counter_N_60994_i ( + .I0(plm_fsm_pa_counter0_un1_reg_rx_count_0_a2_4), + .I1(plm_fsm_pa_counter0_un1_reg_rx_count_0_a2_5), + .I2(plm_fsm_reg_state_1__425), + .O(plm_fsm_pa_counter0_N_60994_i) + ); + defparam plm_fsm_pa_counter0_loadable_tx_counter_N_60995_i.INIT = 16'h80FF; + LUT4 plm_fsm_pa_counter0_loadable_tx_counter_N_60995_i ( + .I0(plm_fsm_pa_counter0_un1_reg_tx_count_0_a2_6), + .I1(plm_fsm_pa_counter0_un1_reg_tx_count_0_a2_7), + .I2(plm_fsm_pa_counter0_un1_reg_tx_count_0_a2_8), + .I3(plm_fsm_reg_state_1__425), + .O(plm_fsm_pa_counter0_N_60995_i) + ); + defparam plm_fsm_pa_counter0_flagit_reg_expired_5_0_a2_0_a2_0_a3_0_a2.INIT = 4'h8; + LUT2_L plm_fsm_pa_counter0_flagit_reg_expired_5_0_a2_0_a2_0_a3_0_a2 ( + .I0(plm_fsm_pa_counter0_N_59124), + .I1(plm_fsm_pa_counter0_reg_tx_expired_1810), + .LO(plm_fsm_pa_counter0_reg_expired_5) + ); + defparam plm_fsm_pa_counter0_un1_enable_1_i.INIT = 4'hD; + LUT2 plm_fsm_pa_counter0_un1_enable_1_i ( + .I0(plm_fsm_reg_state_1__425), + .I1(plm_fsm_pa_counter0_reg_tx_expired_1810), + .O(plm_fsm_pa_counter0_un1_enable_1_i_1808) + ); + FDCE plm_fsm_pa_counter0_reg_tx_count_11_ ( + .CE(plm_fsm_pa_counter0_N_61004_i_1809), + .C(mgt_clk), + .D(plm_fsm_pa_counter0_reg_tx_count_s[11]), + .Q(plm_fsm_pa_counter0_reg_tx_count[11]), + .CLR(plm_rst) + ); + FDCE plm_fsm_pa_counter0_reg_tx_count_10_ ( + .CE(plm_fsm_pa_counter0_N_61004_i_1809), + .C(mgt_clk), + .D(plm_fsm_pa_counter0_reg_tx_count_s[10]), + .Q(plm_fsm_pa_counter0_reg_tx_count[10]), + .CLR(plm_rst) + ); + FDCE plm_fsm_pa_counter0_reg_tx_count_9_ ( + .CE(plm_fsm_pa_counter0_N_61004_i_1809), + .C(mgt_clk), + .D(plm_fsm_pa_counter0_reg_tx_count_s[9]), + .Q(plm_fsm_pa_counter0_reg_tx_count[9]), + .CLR(plm_rst) + ); + FDCE plm_fsm_pa_counter0_reg_tx_count_8_ ( + .CE(plm_fsm_pa_counter0_N_61004_i_1809), + .C(mgt_clk), + .D(plm_fsm_pa_counter0_reg_tx_count_s[8]), + .Q(plm_fsm_pa_counter0_reg_tx_count[8]), + .CLR(plm_rst) + ); + FDCE plm_fsm_pa_counter0_reg_tx_count_7_ ( + .CE(plm_fsm_pa_counter0_N_61004_i_1809), + .C(mgt_clk), + .D(plm_fsm_pa_counter0_reg_tx_count_s[7]), + .Q(plm_fsm_pa_counter0_reg_tx_count[7]), + .CLR(plm_rst) + ); + FDCE plm_fsm_pa_counter0_reg_tx_count_6_ ( + .CE(plm_fsm_pa_counter0_N_61004_i_1809), + .C(mgt_clk), + .D(plm_fsm_pa_counter0_reg_tx_count_s[6]), + .Q(plm_fsm_pa_counter0_reg_tx_count[6]), + .CLR(plm_rst) + ); + FDCE plm_fsm_pa_counter0_reg_tx_count_5_ ( + .CE(plm_fsm_pa_counter0_N_61004_i_1809), + .C(mgt_clk), + .D(plm_fsm_pa_counter0_reg_tx_count_s[5]), + .Q(plm_fsm_pa_counter0_reg_tx_count[5]), + .CLR(plm_rst) + ); + FDCE plm_fsm_pa_counter0_reg_tx_count_4_ ( + .CE(plm_fsm_pa_counter0_N_61004_i_1809), + .C(mgt_clk), + .D(plm_fsm_pa_counter0_reg_tx_count_s[4]), + .Q(plm_fsm_pa_counter0_reg_tx_count[4]), + .CLR(plm_rst) + ); + FDCE plm_fsm_pa_counter0_reg_tx_count_3_ ( + .CE(plm_fsm_pa_counter0_N_61004_i_1809), + .C(mgt_clk), + .D(plm_fsm_pa_counter0_reg_tx_count_s[3]), + .Q(plm_fsm_pa_counter0_reg_tx_count[3]), + .CLR(plm_rst) + ); + FDCE plm_fsm_pa_counter0_reg_tx_count_2_ ( + .CE(plm_fsm_pa_counter0_N_61004_i_1809), + .C(mgt_clk), + .D(plm_fsm_pa_counter0_reg_tx_count_s[2]), + .Q(plm_fsm_pa_counter0_reg_tx_count[2]), + .CLR(plm_rst) + ); + FDCE plm_fsm_pa_counter0_reg_tx_count_1_ ( + .CE(plm_fsm_pa_counter0_N_61004_i_1809), + .C(mgt_clk), + .D(plm_fsm_pa_counter0_reg_tx_count_s[1]), + .Q(plm_fsm_pa_counter0_reg_tx_count[1]), + .CLR(plm_rst) + ); + FDCE plm_fsm_pa_counter0_reg_tx_count_0_ ( + .CE(plm_fsm_pa_counter0_N_61004_i_1809), + .C(mgt_clk), + .D(plm_fsm_pa_counter0_reg_tx_count_s[0]), + .Q(plm_fsm_pa_counter0_reg_tx_count[0]), + .CLR(plm_rst) + ); + FDCE plm_fsm_pa_counter0_reg_rx_count_7_ ( + .CE(plm_fsm_pa_counter0_un1_reg_rx_expired_1_i), + .C(mgt_clk), + .D(plm_fsm_pa_counter0_reg_rx_count_s[7]), + .Q(plm_fsm_pa_counter0_reg_rx_count[7]), + .CLR(plm_rst) + ); + FDCE plm_fsm_pa_counter0_reg_rx_count_6_ ( + .CE(plm_fsm_pa_counter0_un1_reg_rx_expired_1_i), + .C(mgt_clk), + .D(plm_fsm_pa_counter0_reg_rx_count_s[6]), + .Q(plm_fsm_pa_counter0_reg_rx_count[6]), + .CLR(plm_rst) + ); + FDCE plm_fsm_pa_counter0_reg_rx_count_5_ ( + .CE(plm_fsm_pa_counter0_un1_reg_rx_expired_1_i), + .C(mgt_clk), + .D(plm_fsm_pa_counter0_reg_rx_count_s[5]), + .Q(plm_fsm_pa_counter0_reg_rx_count[5]), + .CLR(plm_rst) + ); + FDCE plm_fsm_pa_counter0_reg_rx_count_4_ ( + .CE(plm_fsm_pa_counter0_un1_reg_rx_expired_1_i), + .C(mgt_clk), + .D(plm_fsm_pa_counter0_reg_rx_count_s[4]), + .Q(plm_fsm_pa_counter0_reg_rx_count[4]), + .CLR(plm_rst) + ); + FDCE plm_fsm_pa_counter0_reg_rx_count_3_ ( + .CE(plm_fsm_pa_counter0_un1_reg_rx_expired_1_i), + .C(mgt_clk), + .D(plm_fsm_pa_counter0_reg_rx_count_s[3]), + .Q(plm_fsm_pa_counter0_reg_rx_count[3]), + .CLR(plm_rst) + ); + FDCE plm_fsm_pa_counter0_reg_rx_count_2_ ( + .CE(plm_fsm_pa_counter0_un1_reg_rx_expired_1_i), + .C(mgt_clk), + .D(plm_fsm_pa_counter0_reg_rx_count_s[2]), + .Q(plm_fsm_pa_counter0_reg_rx_count[2]), + .CLR(plm_rst) + ); + FDCE plm_fsm_pa_counter0_reg_rx_count_1_ ( + .CE(plm_fsm_pa_counter0_un1_reg_rx_expired_1_i), + .C(mgt_clk), + .D(plm_fsm_pa_counter0_reg_rx_count_s[1]), + .Q(plm_fsm_pa_counter0_reg_rx_count[1]), + .CLR(plm_rst) + ); + FDCE plm_fsm_pa_counter0_reg_rx_count_0_ ( + .CE(plm_fsm_pa_counter0_un1_reg_rx_expired_1_i), + .C(mgt_clk), + .D(plm_fsm_pa_counter0_reg_rx_count_s[0]), + .Q(plm_fsm_pa_counter0_reg_rx_count[0]), + .CLR(plm_rst) + ); + FDC plm_fsm_pa_counter0_reg_expired ( + .C(mgt_clk), + .D(plm_fsm_pa_counter0_reg_expired_5), + .Q(plm_fsm_pa_cntrout0), + .CLR(plm_rst) + ); + FDCE plm_fsm_pa_counter0_reg_tx_expired ( + .CE(plm_fsm_pa_counter0_N_60995_i), + .C(mgt_clk), + .D(plm_fsm_reg_state_1__425), + .Q(plm_fsm_pa_counter0_reg_tx_expired_1810), + .CLR(plm_rst) + ); + FDCE plm_fsm_pa_counter0_reg_rx_expired ( + .CE(plm_fsm_pa_counter0_N_60994_i), + .C(mgt_clk), + .D(plm_fsm_reg_state_1__425), + .Q(plm_fsm_pa_counter0_reg_rx_expired_424), + .CLR(plm_rst) + ); + defparam plm_fsm_pa_counter0_reg_rx_count_qxu_0_0_.INIT = 4'h7; + LUT2_L plm_fsm_pa_counter0_reg_rx_count_qxu_0_0_ ( + .I0(N_15205_i), + .I1(plm_fsm_pa_counter0_reg_rx_count[0]), + .LO(plm_fsm_pa_counter0_reg_rx_count_qxu[0]) + ); + defparam plm_fsm_pa_counter0_reg_rx_count_qxu_0_1_.INIT = 4'h7; + LUT2_L plm_fsm_pa_counter0_reg_rx_count_qxu_0_1_ ( + .I0(N_15205_i), + .I1(plm_fsm_pa_counter0_reg_rx_count[1]), + .LO(plm_fsm_pa_counter0_reg_rx_count_qxu[1]) + ); + defparam plm_fsm_pa_counter0_reg_rx_count_qxu_0_2_.INIT = 4'h7; + LUT2_L plm_fsm_pa_counter0_reg_rx_count_qxu_0_2_ ( + .I0(N_15205_i), + .I1(plm_fsm_pa_counter0_reg_rx_count[2]), + .LO(plm_fsm_pa_counter0_reg_rx_count_qxu[2]) + ); + defparam plm_fsm_pa_counter0_reg_rx_count_qxu_0_3_.INIT = 8'h1B; + LUT3_L plm_fsm_pa_counter0_reg_rx_count_qxu_0_3_ ( + .I0(N_15205_i), + .I1(plm_fsm_pa_counter0_N_28855_i), + .I2(plm_fsm_pa_counter0_reg_rx_count[3]), + .LO(plm_fsm_pa_counter0_reg_rx_count_qxu[3]) + ); + defparam plm_fsm_pa_counter0_reg_rx_count_qxu_0_4_.INIT = 4'h7; + LUT2_L plm_fsm_pa_counter0_reg_rx_count_qxu_0_4_ ( + .I0(N_15205_i), + .I1(plm_fsm_pa_counter0_reg_rx_count[4]), + .LO(plm_fsm_pa_counter0_reg_rx_count_qxu[4]) + ); + defparam plm_fsm_pa_counter0_reg_rx_count_qxu_0_5_.INIT = 4'h7; + LUT2_L plm_fsm_pa_counter0_reg_rx_count_qxu_0_5_ ( + .I0(N_15205_i), + .I1(plm_fsm_pa_counter0_reg_rx_count[5]), + .LO(plm_fsm_pa_counter0_reg_rx_count_qxu[5]) + ); + defparam plm_fsm_pa_counter0_reg_rx_count_qxu_0_6_.INIT = 4'h7; + LUT2_L plm_fsm_pa_counter0_reg_rx_count_qxu_0_6_ ( + .I0(N_15205_i), + .I1(plm_fsm_pa_counter0_reg_rx_count[6]), + .LO(plm_fsm_pa_counter0_reg_rx_count_qxu[6]) + ); + defparam plm_fsm_pa_counter0_reg_rx_count_qxu_0_7_.INIT = 4'h7; + LUT2_L plm_fsm_pa_counter0_reg_rx_count_qxu_0_7_ ( + .I0(N_15205_i), + .I1(plm_fsm_pa_counter0_reg_rx_count[7]), + .LO(plm_fsm_pa_counter0_reg_rx_count_qxu[7]) + ); + defparam plm_fsm_pa_counter0_reg_tx_count_qxu_0_0_.INIT = 4'h7; + LUT2_L plm_fsm_pa_counter0_reg_tx_count_qxu_0_0_ ( + .I0(plm_fsm_pa_counter0_reg_tx_count[0]), + .I1(plm_fsm_pa_counter0_un1_enable_1), + .LO(plm_fsm_pa_counter0_reg_tx_count_qxu[0]) + ); + defparam plm_fsm_pa_counter0_reg_tx_count_qxu_0_1_.INIT = 4'h7; + LUT2_L plm_fsm_pa_counter0_reg_tx_count_qxu_0_1_ ( + .I0(plm_fsm_pa_counter0_reg_tx_count[1]), + .I1(plm_fsm_pa_counter0_un1_enable_1), + .LO(plm_fsm_pa_counter0_reg_tx_count_qxu[1]) + ); + defparam plm_fsm_pa_counter0_reg_tx_count_qxu_0_2_.INIT = 4'h7; + LUT2_L plm_fsm_pa_counter0_reg_tx_count_qxu_0_2_ ( + .I0(plm_fsm_pa_counter0_reg_tx_count[2]), + .I1(plm_fsm_pa_counter0_un1_enable_1), + .LO(plm_fsm_pa_counter0_reg_tx_count_qxu[2]) + ); + defparam plm_fsm_pa_counter0_reg_tx_count_qxu_0_3_.INIT = 4'h7; + LUT2_L plm_fsm_pa_counter0_reg_tx_count_qxu_0_3_ ( + .I0(plm_fsm_pa_counter0_reg_tx_count[3]), + .I1(plm_fsm_pa_counter0_un1_enable_1), + .LO(plm_fsm_pa_counter0_reg_tx_count_qxu[3]) + ); + defparam plm_fsm_pa_counter0_reg_tx_count_qxu_0_4_.INIT = 8'h35; + LUT3_L plm_fsm_pa_counter0_reg_tx_count_qxu_0_4_ ( + .I0(plm_fsm_reg_tx_count_6_4_), + .I1(plm_fsm_pa_counter0_reg_tx_count[4]), + .I2(plm_fsm_pa_counter0_un1_enable_1), + .LO(plm_fsm_pa_counter0_reg_tx_count_qxu[4]) + ); + defparam plm_fsm_pa_counter0_reg_tx_count_qxu_0_5_.INIT = 4'h7; + LUT2_L plm_fsm_pa_counter0_reg_tx_count_qxu_0_5_ ( + .I0(plm_fsm_pa_counter0_reg_tx_count[5]), + .I1(plm_fsm_pa_counter0_un1_enable_1), + .LO(plm_fsm_pa_counter0_reg_tx_count_qxu[5]) + ); + defparam plm_fsm_pa_counter0_reg_tx_count_qxu_0_6_.INIT = 4'h7; + LUT2_L plm_fsm_pa_counter0_reg_tx_count_qxu_0_6_ ( + .I0(plm_fsm_pa_counter0_reg_tx_count[6]), + .I1(plm_fsm_pa_counter0_un1_enable_1), + .LO(plm_fsm_pa_counter0_reg_tx_count_qxu[6]) + ); + defparam plm_fsm_pa_counter0_reg_tx_count_qxu_0_7_.INIT = 4'h7; + LUT2_L plm_fsm_pa_counter0_reg_tx_count_qxu_0_7_ ( + .I0(plm_fsm_pa_counter0_reg_tx_count[7]), + .I1(plm_fsm_pa_counter0_un1_enable_1), + .LO(plm_fsm_pa_counter0_reg_tx_count_qxu[7]) + ); + defparam plm_fsm_pa_counter0_reg_tx_count_qxu_0_8_.INIT = 4'h7; + LUT2_L plm_fsm_pa_counter0_reg_tx_count_qxu_0_8_ ( + .I0(plm_fsm_pa_counter0_reg_tx_count[8]), + .I1(plm_fsm_pa_counter0_un1_enable_1), + .LO(plm_fsm_pa_counter0_reg_tx_count_qxu[8]) + ); + defparam plm_fsm_pa_counter0_reg_tx_count_qxu_0_9_.INIT = 4'h7; + LUT2_L plm_fsm_pa_counter0_reg_tx_count_qxu_0_9_ ( + .I0(plm_fsm_pa_counter0_reg_tx_count[9]), + .I1(plm_fsm_pa_counter0_un1_enable_1), + .LO(plm_fsm_pa_counter0_reg_tx_count_qxu[9]) + ); + defparam plm_fsm_pa_counter0_reg_tx_count_qxu_0_10_.INIT = 8'h35; + LUT3_L plm_fsm_pa_counter0_reg_tx_count_qxu_0_10_ ( + .I0(plm_fsm_reg_tx_count_6_10_), + .I1(plm_fsm_pa_counter0_reg_tx_count[10]), + .I2(plm_fsm_pa_counter0_un1_enable_1), + .LO(plm_fsm_pa_counter0_reg_tx_count_qxu[10]) + ); + defparam plm_fsm_pa_counter0_reg_tx_count_qxu_0_11_.INIT = 4'h7; + LUT2_L plm_fsm_pa_counter0_reg_tx_count_qxu_0_11_ ( + .I0(plm_fsm_pa_counter0_reg_tx_count[11]), + .I1(plm_fsm_pa_counter0_un1_enable_1), + .LO(plm_fsm_pa_counter0_reg_tx_count_qxu[11]) + ); + VCC plm_fsm_pa_counter1_VCC ( + .P(plm_fsm_pa_counter1_VCC_1811) + ); + MUXCY_L plm_fsm_pa_counter1_reg_rx_count_cry_0_ ( + .CI(N_14474_i_i_85), + .DI(plm_fsm_pa_counter1_VCC_1811), + .LO(plm_fsm_pa_counter1_reg_rx_count_cry[0]), + .S(plm_fsm_pa_counter1_reg_rx_count_qxu[0]) + ); + XORCY plm_fsm_pa_counter1_reg_rx_count_s_0_ ( + .CI(N_14474_i_i_85), + .LI(plm_fsm_pa_counter1_reg_rx_count_qxu[0]), + .O(plm_fsm_pa_counter1_reg_rx_count_s[0]) + ); + MUXCY_L plm_fsm_pa_counter1_reg_rx_count_cry_1_ ( + .CI(plm_fsm_pa_counter1_reg_rx_count_cry[0]), + .DI(plm_fsm_pa_counter1_VCC_1811), + .LO(plm_fsm_pa_counter1_reg_rx_count_cry[1]), + .S(plm_fsm_pa_counter1_reg_rx_count_qxu[1]) + ); + XORCY plm_fsm_pa_counter1_reg_rx_count_s_1_ ( + .CI(plm_fsm_pa_counter1_reg_rx_count_cry[0]), + .LI(plm_fsm_pa_counter1_reg_rx_count_qxu[1]), + .O(plm_fsm_pa_counter1_reg_rx_count_s[1]) + ); + MUXCY_L plm_fsm_pa_counter1_reg_rx_count_cry_2_ ( + .CI(plm_fsm_pa_counter1_reg_rx_count_cry[1]), + .DI(plm_fsm_pa_counter1_VCC_1811), + .LO(plm_fsm_pa_counter1_reg_rx_count_cry[2]), + .S(plm_fsm_pa_counter1_reg_rx_count_qxu[2]) + ); + XORCY plm_fsm_pa_counter1_reg_rx_count_s_2_ ( + .CI(plm_fsm_pa_counter1_reg_rx_count_cry[1]), + .LI(plm_fsm_pa_counter1_reg_rx_count_qxu[2]), + .O(plm_fsm_pa_counter1_reg_rx_count_s[2]) + ); + MUXCY_L plm_fsm_pa_counter1_reg_rx_count_cry_3_ ( + .CI(plm_fsm_pa_counter1_reg_rx_count_cry[2]), + .DI(plm_fsm_pa_counter1_VCC_1811), + .LO(plm_fsm_pa_counter1_reg_rx_count_cry[3]), + .S(plm_fsm_pa_counter1_reg_rx_count_qxu[3]) + ); + XORCY plm_fsm_pa_counter1_reg_rx_count_s_3_ ( + .CI(plm_fsm_pa_counter1_reg_rx_count_cry[2]), + .LI(plm_fsm_pa_counter1_reg_rx_count_qxu[3]), + .O(plm_fsm_pa_counter1_reg_rx_count_s[3]) + ); + MUXCY_L plm_fsm_pa_counter1_reg_rx_count_cry_4_ ( + .CI(plm_fsm_pa_counter1_reg_rx_count_cry[3]), + .DI(plm_fsm_pa_counter1_VCC_1811), + .LO(plm_fsm_pa_counter1_reg_rx_count_cry[4]), + .S(plm_fsm_pa_counter1_reg_rx_count_qxu[4]) + ); + XORCY plm_fsm_pa_counter1_reg_rx_count_s_4_ ( + .CI(plm_fsm_pa_counter1_reg_rx_count_cry[3]), + .LI(plm_fsm_pa_counter1_reg_rx_count_qxu[4]), + .O(plm_fsm_pa_counter1_reg_rx_count_s[4]) + ); + MUXCY_L plm_fsm_pa_counter1_reg_rx_count_cry_5_ ( + .CI(plm_fsm_pa_counter1_reg_rx_count_cry[4]), + .DI(plm_fsm_pa_counter1_VCC_1811), + .LO(plm_fsm_pa_counter1_reg_rx_count_cry[5]), + .S(plm_fsm_pa_counter1_reg_rx_count_qxu[5]) + ); + XORCY plm_fsm_pa_counter1_reg_rx_count_s_5_ ( + .CI(plm_fsm_pa_counter1_reg_rx_count_cry[4]), + .LI(plm_fsm_pa_counter1_reg_rx_count_qxu[5]), + .O(plm_fsm_pa_counter1_reg_rx_count_s[5]) + ); + MUXCY_L plm_fsm_pa_counter1_reg_rx_count_cry_6_ ( + .CI(plm_fsm_pa_counter1_reg_rx_count_cry[5]), + .DI(plm_fsm_pa_counter1_VCC_1811), + .LO(plm_fsm_pa_counter1_reg_rx_count_cry[6]), + .S(plm_fsm_pa_counter1_reg_rx_count_qxu[6]) + ); + XORCY plm_fsm_pa_counter1_reg_rx_count_s_6_ ( + .CI(plm_fsm_pa_counter1_reg_rx_count_cry[5]), + .LI(plm_fsm_pa_counter1_reg_rx_count_qxu[6]), + .O(plm_fsm_pa_counter1_reg_rx_count_s[6]) + ); + XORCY plm_fsm_pa_counter1_reg_rx_count_s_7_ ( + .CI(plm_fsm_pa_counter1_reg_rx_count_cry[6]), + .LI(plm_fsm_pa_counter1_reg_rx_count_qxu[7]), + .O(plm_fsm_pa_counter1_reg_rx_count_s[7]) + ); + MUXCY_L plm_fsm_pa_counter1_reg_tx_count_cry_0_ ( + .CI(plm_fsm_pa_counter1_un1_enable_1_i_1812), + .DI(plm_fsm_pa_counter1_VCC_1811), + .LO(plm_fsm_pa_counter1_reg_tx_count_cry[0]), + .S(plm_fsm_pa_counter1_reg_tx_count_qxu[0]) + ); + XORCY plm_fsm_pa_counter1_reg_tx_count_s_0_ ( + .CI(plm_fsm_pa_counter1_un1_enable_1_i_1812), + .LI(plm_fsm_pa_counter1_reg_tx_count_qxu[0]), + .O(plm_fsm_pa_counter1_reg_tx_count_s[0]) + ); + MUXCY_L plm_fsm_pa_counter1_reg_tx_count_cry_1_ ( + .CI(plm_fsm_pa_counter1_reg_tx_count_cry[0]), + .DI(plm_fsm_pa_counter1_VCC_1811), + .LO(plm_fsm_pa_counter1_reg_tx_count_cry[1]), + .S(plm_fsm_pa_counter1_reg_tx_count_qxu[1]) + ); + XORCY plm_fsm_pa_counter1_reg_tx_count_s_1_ ( + .CI(plm_fsm_pa_counter1_reg_tx_count_cry[0]), + .LI(plm_fsm_pa_counter1_reg_tx_count_qxu[1]), + .O(plm_fsm_pa_counter1_reg_tx_count_s[1]) + ); + MUXCY_L plm_fsm_pa_counter1_reg_tx_count_cry_2_ ( + .CI(plm_fsm_pa_counter1_reg_tx_count_cry[1]), + .DI(plm_fsm_pa_counter1_VCC_1811), + .LO(plm_fsm_pa_counter1_reg_tx_count_cry[2]), + .S(plm_fsm_pa_counter1_reg_tx_count_qxu[2]) + ); + XORCY plm_fsm_pa_counter1_reg_tx_count_s_2_ ( + .CI(plm_fsm_pa_counter1_reg_tx_count_cry[1]), + .LI(plm_fsm_pa_counter1_reg_tx_count_qxu[2]), + .O(plm_fsm_pa_counter1_reg_tx_count_s[2]) + ); + MUXCY_L plm_fsm_pa_counter1_reg_tx_count_cry_3_ ( + .CI(plm_fsm_pa_counter1_reg_tx_count_cry[2]), + .DI(plm_fsm_pa_counter1_VCC_1811), + .LO(plm_fsm_pa_counter1_reg_tx_count_cry[3]), + .S(plm_fsm_pa_counter1_reg_tx_count_qxu[3]) + ); + XORCY plm_fsm_pa_counter1_reg_tx_count_s_3_ ( + .CI(plm_fsm_pa_counter1_reg_tx_count_cry[2]), + .LI(plm_fsm_pa_counter1_reg_tx_count_qxu[3]), + .O(plm_fsm_pa_counter1_reg_tx_count_s[3]) + ); + MUXCY_L plm_fsm_pa_counter1_reg_tx_count_cry_4_ ( + .CI(plm_fsm_pa_counter1_reg_tx_count_cry[3]), + .DI(plm_fsm_pa_counter1_VCC_1811), + .LO(plm_fsm_pa_counter1_reg_tx_count_cry[4]), + .S(plm_fsm_pa_counter1_reg_tx_count_qxu[4]) + ); + XORCY plm_fsm_pa_counter1_reg_tx_count_s_4_ ( + .CI(plm_fsm_pa_counter1_reg_tx_count_cry[3]), + .LI(plm_fsm_pa_counter1_reg_tx_count_qxu[4]), + .O(plm_fsm_pa_counter1_reg_tx_count_s[4]) + ); + MUXCY_L plm_fsm_pa_counter1_reg_tx_count_cry_5_ ( + .CI(plm_fsm_pa_counter1_reg_tx_count_cry[4]), + .DI(plm_fsm_pa_counter1_VCC_1811), + .LO(plm_fsm_pa_counter1_reg_tx_count_cry[5]), + .S(plm_fsm_pa_counter1_reg_tx_count_qxu[5]) + ); + XORCY plm_fsm_pa_counter1_reg_tx_count_s_5_ ( + .CI(plm_fsm_pa_counter1_reg_tx_count_cry[4]), + .LI(plm_fsm_pa_counter1_reg_tx_count_qxu[5]), + .O(plm_fsm_pa_counter1_reg_tx_count_s[5]) + ); + MUXCY_L plm_fsm_pa_counter1_reg_tx_count_cry_6_ ( + .CI(plm_fsm_pa_counter1_reg_tx_count_cry[5]), + .DI(plm_fsm_pa_counter1_VCC_1811), + .LO(plm_fsm_pa_counter1_reg_tx_count_cry[6]), + .S(plm_fsm_pa_counter1_reg_tx_count_qxu[6]) + ); + XORCY plm_fsm_pa_counter1_reg_tx_count_s_6_ ( + .CI(plm_fsm_pa_counter1_reg_tx_count_cry[5]), + .LI(plm_fsm_pa_counter1_reg_tx_count_qxu[6]), + .O(plm_fsm_pa_counter1_reg_tx_count_s[6]) + ); + MUXCY_L plm_fsm_pa_counter1_reg_tx_count_cry_7_ ( + .CI(plm_fsm_pa_counter1_reg_tx_count_cry[6]), + .DI(plm_fsm_pa_counter1_VCC_1811), + .LO(plm_fsm_pa_counter1_reg_tx_count_cry[7]), + .S(plm_fsm_pa_counter1_reg_tx_count_qxu[7]) + ); + XORCY plm_fsm_pa_counter1_reg_tx_count_s_7_ ( + .CI(plm_fsm_pa_counter1_reg_tx_count_cry[6]), + .LI(plm_fsm_pa_counter1_reg_tx_count_qxu[7]), + .O(plm_fsm_pa_counter1_reg_tx_count_s[7]) + ); + MUXCY_L plm_fsm_pa_counter1_reg_tx_count_cry_8_ ( + .CI(plm_fsm_pa_counter1_reg_tx_count_cry[7]), + .DI(plm_fsm_pa_counter1_VCC_1811), + .LO(plm_fsm_pa_counter1_reg_tx_count_cry[8]), + .S(plm_fsm_pa_counter1_reg_tx_count_qxu[8]) + ); + XORCY plm_fsm_pa_counter1_reg_tx_count_s_8_ ( + .CI(plm_fsm_pa_counter1_reg_tx_count_cry[7]), + .LI(plm_fsm_pa_counter1_reg_tx_count_qxu[8]), + .O(plm_fsm_pa_counter1_reg_tx_count_s[8]) + ); + MUXCY_L plm_fsm_pa_counter1_reg_tx_count_cry_9_ ( + .CI(plm_fsm_pa_counter1_reg_tx_count_cry[8]), + .DI(plm_fsm_pa_counter1_VCC_1811), + .LO(plm_fsm_pa_counter1_reg_tx_count_cry[9]), + .S(plm_fsm_pa_counter1_reg_tx_count_qxu[9]) + ); + XORCY plm_fsm_pa_counter1_reg_tx_count_s_9_ ( + .CI(plm_fsm_pa_counter1_reg_tx_count_cry[8]), + .LI(plm_fsm_pa_counter1_reg_tx_count_qxu[9]), + .O(plm_fsm_pa_counter1_reg_tx_count_s[9]) + ); + MUXCY_L plm_fsm_pa_counter1_reg_tx_count_cry_10_ ( + .CI(plm_fsm_pa_counter1_reg_tx_count_cry[9]), + .DI(plm_fsm_pa_counter1_VCC_1811), + .LO(plm_fsm_pa_counter1_reg_tx_count_cry[10]), + .S(plm_fsm_pa_counter1_reg_tx_count_qxu[10]) + ); + XORCY plm_fsm_pa_counter1_reg_tx_count_s_10_ ( + .CI(plm_fsm_pa_counter1_reg_tx_count_cry[9]), + .LI(plm_fsm_pa_counter1_reg_tx_count_qxu[10]), + .O(plm_fsm_pa_counter1_reg_tx_count_s[10]) + ); + XORCY plm_fsm_pa_counter1_reg_tx_count_s_11_ ( + .CI(plm_fsm_pa_counter1_reg_tx_count_cry[10]), + .LI(plm_fsm_pa_counter1_reg_tx_count_qxu[11]), + .O(plm_fsm_pa_counter1_reg_tx_count_s[11]) + ); + defparam plm_fsm_pa_counter1_un1_enable_1_0_a2_0_a2_0_a2_0_a3_0_a2.INIT = 4'h4; + LUT2 plm_fsm_pa_counter1_un1_enable_1_0_a2_0_a2_0_a2_0_a3_0_a2 ( + .I0(plm_fsm_pa_counter1_reg_tx_expired_1814), + .I1(plm_fsm_reg_state_1__425), + .O(plm_fsm_pa_counter1_un1_enable_1) + ); + defparam plm_fsm_pa_counter1_un1_enable_2_i_i_0_0_a2_0.INIT = 4'h8; + LUT2 plm_fsm_pa_counter1_un1_enable_2_i_i_0_0_a2_0 ( + .I0(plm_fsm_pa_counter1_reg_rx_expired_84), + .I1(plm_fsm_reg_state_1__425), + .O(plm_fsm_pa_counter1_N_59121) + ); + defparam plm_fsm_pa_counter1_un1_enable_2_i_i_0_0_a2_1.INIT = 8'h10; + LUT3 plm_fsm_pa_counter1_un1_enable_2_i_i_0_0_a2_1 ( + .I0(plm_reg_ts2_1_0), + .I1(plm_reg_ts1_1_0), + .I2(plm_fsm_reg_state_1__425), + .O(plm_fsm_pa_counter1_N_59122) + ); + defparam plm_fsm_pa_counter1_loadable_rx_counter_un1_reg_rx_count_0_a2_4.INIT = 16'h0001; + LUT4 plm_fsm_pa_counter1_loadable_rx_counter_un1_reg_rx_count_0_a2_4 ( + .I0(plm_fsm_pa_counter1_reg_rx_count[0]), + .I1(plm_fsm_pa_counter1_reg_rx_count[1]), + .I2(plm_fsm_pa_counter1_reg_rx_count[2]), + .I3(plm_fsm_pa_counter1_reg_rx_count[3]), + .O(plm_fsm_pa_counter1_un1_reg_rx_count_0_a2_4) + ); + defparam plm_fsm_pa_counter1_loadable_rx_counter_un1_reg_rx_count_0_a2_5.INIT = 16'h0001; + LUT4 plm_fsm_pa_counter1_loadable_rx_counter_un1_reg_rx_count_0_a2_5 ( + .I0(plm_fsm_pa_counter1_reg_rx_count[4]), + .I1(plm_fsm_pa_counter1_reg_rx_count[5]), + .I2(plm_fsm_pa_counter1_reg_rx_count[6]), + .I3(plm_fsm_pa_counter1_reg_rx_count[7]), + .O(plm_fsm_pa_counter1_un1_reg_rx_count_0_a2_5) + ); + defparam plm_fsm_pa_counter1_loadable_tx_counter_un1_reg_tx_count_0_a2_6.INIT = 16'h0001; + LUT4 plm_fsm_pa_counter1_loadable_tx_counter_un1_reg_tx_count_0_a2_6 ( + .I0(plm_fsm_pa_counter1_reg_tx_count[0]), + .I1(plm_fsm_pa_counter1_reg_tx_count[1]), + .I2(plm_fsm_pa_counter1_reg_tx_count[2]), + .I3(plm_fsm_pa_counter1_reg_tx_count[3]), + .O(plm_fsm_pa_counter1_un1_reg_tx_count_0_a2_6) + ); + defparam plm_fsm_pa_counter1_loadable_tx_counter_un1_reg_tx_count_0_a2_7.INIT = 16'h0001; + LUT4 plm_fsm_pa_counter1_loadable_tx_counter_un1_reg_tx_count_0_a2_7 ( + .I0(plm_fsm_pa_counter1_reg_tx_count[4]), + .I1(plm_fsm_pa_counter1_reg_tx_count[5]), + .I2(plm_fsm_pa_counter1_reg_tx_count[6]), + .I3(plm_fsm_pa_counter1_reg_tx_count[7]), + .O(plm_fsm_pa_counter1_un1_reg_tx_count_0_a2_7) + ); + defparam plm_fsm_pa_counter1_loadable_tx_counter_un1_reg_tx_count_0_a2_8.INIT = 16'h0001; + LUT4 plm_fsm_pa_counter1_loadable_tx_counter_un1_reg_tx_count_0_a2_8 ( + .I0(plm_fsm_pa_counter1_reg_tx_count[8]), + .I1(plm_fsm_pa_counter1_reg_tx_count[9]), + .I2(plm_fsm_pa_counter1_reg_tx_count[10]), + .I3(plm_fsm_pa_counter1_reg_tx_count[11]), + .O(plm_fsm_pa_counter1_un1_reg_tx_count_0_a2_8) + ); + defparam plm_fsm_pa_counter1_N_61005_i.INIT = 4'hB; + LUT2 plm_fsm_pa_counter1_N_61005_i ( + .I0(plm_reg_sym_sent_5_), + .I1(plm_fsm_pa_counter1_un1_enable_1), + .O(plm_fsm_pa_counter1_N_61005_i_1813) + ); + defparam plm_fsm_pa_counter1_loadable_rx_counter_un1_reg_rx_expired_1_i.INIT = 4'hD; + LUT2 plm_fsm_pa_counter1_loadable_rx_counter_un1_reg_rx_expired_1_i ( + .I0(plm_fsm_pa_counter1_N_59122), + .I1(plm_fsm_pa_counter1_reg_rx_expired_84), + .O(plm_fsm_pa_counter1_un1_reg_rx_expired_1_i) + ); + defparam plm_fsm_pa_counter1_un1_enable_2_i_i_0_0.INIT = 16'h0007; + LUT4 plm_fsm_pa_counter1_un1_enable_2_i_i_0_0 ( + .I0(N_14474_1_i), + .I1(N_14474_i_1), + .I2(plm_fsm_pa_counter1_N_59121), + .I3(plm_fsm_pa_counter1_N_59122), + .O(plm_fsm_pa_counter1_N_28853_i) + ); + defparam plm_fsm_pa_counter1_loadable_rx_counter_N_60991_i.INIT = 8'h8F; + LUT3 plm_fsm_pa_counter1_loadable_rx_counter_N_60991_i ( + .I0(plm_fsm_pa_counter1_un1_reg_rx_count_0_a2_4), + .I1(plm_fsm_pa_counter1_un1_reg_rx_count_0_a2_5), + .I2(plm_fsm_reg_state_1__425), + .O(plm_fsm_pa_counter1_N_60991_i) + ); + defparam plm_fsm_pa_counter1_loadable_tx_counter_N_60992_i.INIT = 16'h80FF; + LUT4 plm_fsm_pa_counter1_loadable_tx_counter_N_60992_i ( + .I0(plm_fsm_pa_counter1_un1_reg_tx_count_0_a2_6), + .I1(plm_fsm_pa_counter1_un1_reg_tx_count_0_a2_7), + .I2(plm_fsm_pa_counter1_un1_reg_tx_count_0_a2_8), + .I3(plm_fsm_reg_state_1__425), + .O(plm_fsm_pa_counter1_N_60992_i) + ); + defparam plm_fsm_pa_counter1_flagit_reg_expired_5_0_a2_0_a2_0_a3_0_a2.INIT = 4'h8; + LUT2_L plm_fsm_pa_counter1_flagit_reg_expired_5_0_a2_0_a2_0_a3_0_a2 ( + .I0(plm_fsm_pa_counter1_N_59121), + .I1(plm_fsm_pa_counter1_reg_tx_expired_1814), + .LO(plm_fsm_pa_counter1_reg_expired_5) + ); + defparam plm_fsm_pa_counter1_un1_enable_1_i.INIT = 4'hD; + LUT2 plm_fsm_pa_counter1_un1_enable_1_i ( + .I0(plm_fsm_reg_state_1__425), + .I1(plm_fsm_pa_counter1_reg_tx_expired_1814), + .O(plm_fsm_pa_counter1_un1_enable_1_i_1812) + ); + FDCE plm_fsm_pa_counter1_reg_tx_count_11_ ( + .CE(plm_fsm_pa_counter1_N_61005_i_1813), + .C(mgt_clk), + .D(plm_fsm_pa_counter1_reg_tx_count_s[11]), + .Q(plm_fsm_pa_counter1_reg_tx_count[11]), + .CLR(plm_rst) + ); + FDCE plm_fsm_pa_counter1_reg_tx_count_10_ ( + .CE(plm_fsm_pa_counter1_N_61005_i_1813), + .C(mgt_clk), + .D(plm_fsm_pa_counter1_reg_tx_count_s[10]), + .Q(plm_fsm_pa_counter1_reg_tx_count[10]), + .CLR(plm_rst) + ); + FDCE plm_fsm_pa_counter1_reg_tx_count_9_ ( + .CE(plm_fsm_pa_counter1_N_61005_i_1813), + .C(mgt_clk), + .D(plm_fsm_pa_counter1_reg_tx_count_s[9]), + .Q(plm_fsm_pa_counter1_reg_tx_count[9]), + .CLR(plm_rst) + ); + FDCE plm_fsm_pa_counter1_reg_tx_count_8_ ( + .CE(plm_fsm_pa_counter1_N_61005_i_1813), + .C(mgt_clk), + .D(plm_fsm_pa_counter1_reg_tx_count_s[8]), + .Q(plm_fsm_pa_counter1_reg_tx_count[8]), + .CLR(plm_rst) + ); + FDCE plm_fsm_pa_counter1_reg_tx_count_7_ ( + .CE(plm_fsm_pa_counter1_N_61005_i_1813), + .C(mgt_clk), + .D(plm_fsm_pa_counter1_reg_tx_count_s[7]), + .Q(plm_fsm_pa_counter1_reg_tx_count[7]), + .CLR(plm_rst) + ); + FDCE plm_fsm_pa_counter1_reg_tx_count_6_ ( + .CE(plm_fsm_pa_counter1_N_61005_i_1813), + .C(mgt_clk), + .D(plm_fsm_pa_counter1_reg_tx_count_s[6]), + .Q(plm_fsm_pa_counter1_reg_tx_count[6]), + .CLR(plm_rst) + ); + FDCE plm_fsm_pa_counter1_reg_tx_count_5_ ( + .CE(plm_fsm_pa_counter1_N_61005_i_1813), + .C(mgt_clk), + .D(plm_fsm_pa_counter1_reg_tx_count_s[5]), + .Q(plm_fsm_pa_counter1_reg_tx_count[5]), + .CLR(plm_rst) + ); + FDCE plm_fsm_pa_counter1_reg_tx_count_4_ ( + .CE(plm_fsm_pa_counter1_N_61005_i_1813), + .C(mgt_clk), + .D(plm_fsm_pa_counter1_reg_tx_count_s[4]), + .Q(plm_fsm_pa_counter1_reg_tx_count[4]), + .CLR(plm_rst) + ); + FDCE plm_fsm_pa_counter1_reg_tx_count_3_ ( + .CE(plm_fsm_pa_counter1_N_61005_i_1813), + .C(mgt_clk), + .D(plm_fsm_pa_counter1_reg_tx_count_s[3]), + .Q(plm_fsm_pa_counter1_reg_tx_count[3]), + .CLR(plm_rst) + ); + FDCE plm_fsm_pa_counter1_reg_tx_count_2_ ( + .CE(plm_fsm_pa_counter1_N_61005_i_1813), + .C(mgt_clk), + .D(plm_fsm_pa_counter1_reg_tx_count_s[2]), + .Q(plm_fsm_pa_counter1_reg_tx_count[2]), + .CLR(plm_rst) + ); + FDCE plm_fsm_pa_counter1_reg_tx_count_1_ ( + .CE(plm_fsm_pa_counter1_N_61005_i_1813), + .C(mgt_clk), + .D(plm_fsm_pa_counter1_reg_tx_count_s[1]), + .Q(plm_fsm_pa_counter1_reg_tx_count[1]), + .CLR(plm_rst) + ); + FDCE plm_fsm_pa_counter1_reg_tx_count_0_ ( + .CE(plm_fsm_pa_counter1_N_61005_i_1813), + .C(mgt_clk), + .D(plm_fsm_pa_counter1_reg_tx_count_s[0]), + .Q(plm_fsm_pa_counter1_reg_tx_count[0]), + .CLR(plm_rst) + ); + FDCE plm_fsm_pa_counter1_reg_rx_count_7_ ( + .CE(plm_fsm_pa_counter1_un1_reg_rx_expired_1_i), + .C(mgt_clk), + .D(plm_fsm_pa_counter1_reg_rx_count_s[7]), + .Q(plm_fsm_pa_counter1_reg_rx_count[7]), + .CLR(plm_rst) + ); + FDCE plm_fsm_pa_counter1_reg_rx_count_6_ ( + .CE(plm_fsm_pa_counter1_un1_reg_rx_expired_1_i), + .C(mgt_clk), + .D(plm_fsm_pa_counter1_reg_rx_count_s[6]), + .Q(plm_fsm_pa_counter1_reg_rx_count[6]), + .CLR(plm_rst) + ); + FDCE plm_fsm_pa_counter1_reg_rx_count_5_ ( + .CE(plm_fsm_pa_counter1_un1_reg_rx_expired_1_i), + .C(mgt_clk), + .D(plm_fsm_pa_counter1_reg_rx_count_s[5]), + .Q(plm_fsm_pa_counter1_reg_rx_count[5]), + .CLR(plm_rst) + ); + FDCE plm_fsm_pa_counter1_reg_rx_count_4_ ( + .CE(plm_fsm_pa_counter1_un1_reg_rx_expired_1_i), + .C(mgt_clk), + .D(plm_fsm_pa_counter1_reg_rx_count_s[4]), + .Q(plm_fsm_pa_counter1_reg_rx_count[4]), + .CLR(plm_rst) + ); + FDCE plm_fsm_pa_counter1_reg_rx_count_3_ ( + .CE(plm_fsm_pa_counter1_un1_reg_rx_expired_1_i), + .C(mgt_clk), + .D(plm_fsm_pa_counter1_reg_rx_count_s[3]), + .Q(plm_fsm_pa_counter1_reg_rx_count[3]), + .CLR(plm_rst) + ); + FDCE plm_fsm_pa_counter1_reg_rx_count_2_ ( + .CE(plm_fsm_pa_counter1_un1_reg_rx_expired_1_i), + .C(mgt_clk), + .D(plm_fsm_pa_counter1_reg_rx_count_s[2]), + .Q(plm_fsm_pa_counter1_reg_rx_count[2]), + .CLR(plm_rst) + ); + FDCE plm_fsm_pa_counter1_reg_rx_count_1_ ( + .CE(plm_fsm_pa_counter1_un1_reg_rx_expired_1_i), + .C(mgt_clk), + .D(plm_fsm_pa_counter1_reg_rx_count_s[1]), + .Q(plm_fsm_pa_counter1_reg_rx_count[1]), + .CLR(plm_rst) + ); + FDCE plm_fsm_pa_counter1_reg_rx_count_0_ ( + .CE(plm_fsm_pa_counter1_un1_reg_rx_expired_1_i), + .C(mgt_clk), + .D(plm_fsm_pa_counter1_reg_rx_count_s[0]), + .Q(plm_fsm_pa_counter1_reg_rx_count[0]), + .CLR(plm_rst) + ); + FDC plm_fsm_pa_counter1_reg_expired ( + .C(mgt_clk), + .D(plm_fsm_pa_counter1_reg_expired_5), + .Q(plm_fsm_pa_cntrout1), + .CLR(plm_rst) + ); + FDCE plm_fsm_pa_counter1_reg_tx_expired ( + .CE(plm_fsm_pa_counter1_N_60992_i), + .C(mgt_clk), + .D(plm_fsm_reg_state_1__425), + .Q(plm_fsm_pa_counter1_reg_tx_expired_1814), + .CLR(plm_rst) + ); + FDCE plm_fsm_pa_counter1_reg_rx_expired ( + .CE(plm_fsm_pa_counter1_N_60991_i), + .C(mgt_clk), + .D(plm_fsm_reg_state_1__425), + .Q(plm_fsm_pa_counter1_reg_rx_expired_84), + .CLR(plm_rst) + ); + defparam plm_fsm_pa_counter1_reg_rx_count_qxu_0_0_.INIT = 4'h7; + LUT2_L plm_fsm_pa_counter1_reg_rx_count_qxu_0_0_ ( + .I0(N_14474_i), + .I1(plm_fsm_pa_counter1_reg_rx_count[0]), + .LO(plm_fsm_pa_counter1_reg_rx_count_qxu[0]) + ); + defparam plm_fsm_pa_counter1_reg_rx_count_qxu_0_1_.INIT = 4'h7; + LUT2_L plm_fsm_pa_counter1_reg_rx_count_qxu_0_1_ ( + .I0(N_14474_i), + .I1(plm_fsm_pa_counter1_reg_rx_count[1]), + .LO(plm_fsm_pa_counter1_reg_rx_count_qxu[1]) + ); + defparam plm_fsm_pa_counter1_reg_rx_count_qxu_0_2_.INIT = 4'h7; + LUT2_L plm_fsm_pa_counter1_reg_rx_count_qxu_0_2_ ( + .I0(N_14474_i), + .I1(plm_fsm_pa_counter1_reg_rx_count[2]), + .LO(plm_fsm_pa_counter1_reg_rx_count_qxu[2]) + ); + defparam plm_fsm_pa_counter1_reg_rx_count_qxu_0_3_.INIT = 8'h1B; + LUT3_L plm_fsm_pa_counter1_reg_rx_count_qxu_0_3_ ( + .I0(N_14474_i), + .I1(plm_fsm_pa_counter1_N_28853_i), + .I2(plm_fsm_pa_counter1_reg_rx_count[3]), + .LO(plm_fsm_pa_counter1_reg_rx_count_qxu[3]) + ); + defparam plm_fsm_pa_counter1_reg_rx_count_qxu_0_4_.INIT = 4'h7; + LUT2_L plm_fsm_pa_counter1_reg_rx_count_qxu_0_4_ ( + .I0(N_14474_i), + .I1(plm_fsm_pa_counter1_reg_rx_count[4]), + .LO(plm_fsm_pa_counter1_reg_rx_count_qxu[4]) + ); + defparam plm_fsm_pa_counter1_reg_rx_count_qxu_0_5_.INIT = 4'h7; + LUT2_L plm_fsm_pa_counter1_reg_rx_count_qxu_0_5_ ( + .I0(N_14474_i), + .I1(plm_fsm_pa_counter1_reg_rx_count[5]), + .LO(plm_fsm_pa_counter1_reg_rx_count_qxu[5]) + ); + defparam plm_fsm_pa_counter1_reg_rx_count_qxu_0_6_.INIT = 4'h7; + LUT2_L plm_fsm_pa_counter1_reg_rx_count_qxu_0_6_ ( + .I0(N_14474_i), + .I1(plm_fsm_pa_counter1_reg_rx_count[6]), + .LO(plm_fsm_pa_counter1_reg_rx_count_qxu[6]) + ); + defparam plm_fsm_pa_counter1_reg_rx_count_qxu_0_7_.INIT = 4'h7; + LUT2_L plm_fsm_pa_counter1_reg_rx_count_qxu_0_7_ ( + .I0(N_14474_i), + .I1(plm_fsm_pa_counter1_reg_rx_count[7]), + .LO(plm_fsm_pa_counter1_reg_rx_count_qxu[7]) + ); + defparam plm_fsm_pa_counter1_reg_tx_count_qxu_0_0_.INIT = 4'h7; + LUT2_L plm_fsm_pa_counter1_reg_tx_count_qxu_0_0_ ( + .I0(plm_fsm_pa_counter1_reg_tx_count[0]), + .I1(plm_fsm_pa_counter1_un1_enable_1), + .LO(plm_fsm_pa_counter1_reg_tx_count_qxu[0]) + ); + defparam plm_fsm_pa_counter1_reg_tx_count_qxu_0_1_.INIT = 4'h7; + LUT2_L plm_fsm_pa_counter1_reg_tx_count_qxu_0_1_ ( + .I0(plm_fsm_pa_counter1_reg_tx_count[1]), + .I1(plm_fsm_pa_counter1_un1_enable_1), + .LO(plm_fsm_pa_counter1_reg_tx_count_qxu[1]) + ); + defparam plm_fsm_pa_counter1_reg_tx_count_qxu_0_2_.INIT = 4'h7; + LUT2_L plm_fsm_pa_counter1_reg_tx_count_qxu_0_2_ ( + .I0(plm_fsm_pa_counter1_reg_tx_count[2]), + .I1(plm_fsm_pa_counter1_un1_enable_1), + .LO(plm_fsm_pa_counter1_reg_tx_count_qxu[2]) + ); + defparam plm_fsm_pa_counter1_reg_tx_count_qxu_0_3_.INIT = 4'h7; + LUT2_L plm_fsm_pa_counter1_reg_tx_count_qxu_0_3_ ( + .I0(plm_fsm_pa_counter1_reg_tx_count[3]), + .I1(plm_fsm_pa_counter1_un1_enable_1), + .LO(plm_fsm_pa_counter1_reg_tx_count_qxu[3]) + ); + defparam plm_fsm_pa_counter1_reg_tx_count_qxu_0_4_.INIT = 8'h35; + LUT3_L plm_fsm_pa_counter1_reg_tx_count_qxu_0_4_ ( + .I0(plm_fsm_reg_tx_count_6_4_), + .I1(plm_fsm_pa_counter1_reg_tx_count[4]), + .I2(plm_fsm_pa_counter1_un1_enable_1), + .LO(plm_fsm_pa_counter1_reg_tx_count_qxu[4]) + ); + defparam plm_fsm_pa_counter1_reg_tx_count_qxu_0_5_.INIT = 4'h7; + LUT2_L plm_fsm_pa_counter1_reg_tx_count_qxu_0_5_ ( + .I0(plm_fsm_pa_counter1_reg_tx_count[5]), + .I1(plm_fsm_pa_counter1_un1_enable_1), + .LO(plm_fsm_pa_counter1_reg_tx_count_qxu[5]) + ); + defparam plm_fsm_pa_counter1_reg_tx_count_qxu_0_6_.INIT = 4'h7; + LUT2_L plm_fsm_pa_counter1_reg_tx_count_qxu_0_6_ ( + .I0(plm_fsm_pa_counter1_reg_tx_count[6]), + .I1(plm_fsm_pa_counter1_un1_enable_1), + .LO(plm_fsm_pa_counter1_reg_tx_count_qxu[6]) + ); + defparam plm_fsm_pa_counter1_reg_tx_count_qxu_0_7_.INIT = 4'h7; + LUT2_L plm_fsm_pa_counter1_reg_tx_count_qxu_0_7_ ( + .I0(plm_fsm_pa_counter1_reg_tx_count[7]), + .I1(plm_fsm_pa_counter1_un1_enable_1), + .LO(plm_fsm_pa_counter1_reg_tx_count_qxu[7]) + ); + defparam plm_fsm_pa_counter1_reg_tx_count_qxu_0_8_.INIT = 4'h7; + LUT2_L plm_fsm_pa_counter1_reg_tx_count_qxu_0_8_ ( + .I0(plm_fsm_pa_counter1_reg_tx_count[8]), + .I1(plm_fsm_pa_counter1_un1_enable_1), + .LO(plm_fsm_pa_counter1_reg_tx_count_qxu[8]) + ); + defparam plm_fsm_pa_counter1_reg_tx_count_qxu_0_9_.INIT = 4'h7; + LUT2_L plm_fsm_pa_counter1_reg_tx_count_qxu_0_9_ ( + .I0(plm_fsm_pa_counter1_reg_tx_count[9]), + .I1(plm_fsm_pa_counter1_un1_enable_1), + .LO(plm_fsm_pa_counter1_reg_tx_count_qxu[9]) + ); + defparam plm_fsm_pa_counter1_reg_tx_count_qxu_0_10_.INIT = 8'h35; + LUT3_L plm_fsm_pa_counter1_reg_tx_count_qxu_0_10_ ( + .I0(plm_fsm_reg_tx_count_6_10_), + .I1(plm_fsm_pa_counter1_reg_tx_count[10]), + .I2(plm_fsm_pa_counter1_un1_enable_1), + .LO(plm_fsm_pa_counter1_reg_tx_count_qxu[10]) + ); + defparam plm_fsm_pa_counter1_reg_tx_count_qxu_0_11_.INIT = 4'h7; + LUT2_L plm_fsm_pa_counter1_reg_tx_count_qxu_0_11_ ( + .I0(plm_fsm_pa_counter1_reg_tx_count[11]), + .I1(plm_fsm_pa_counter1_un1_enable_1), + .LO(plm_fsm_pa_counter1_reg_tx_count_qxu[11]) + ); + VCC plm_fsm_pa_counter2_VCC ( + .P(plm_fsm_pa_counter2_VCC_1815) + ); + MUXCY_L plm_fsm_pa_counter2_reg_rx_count_cry_0_ ( + .CI(N_22524_i_i_87), + .DI(plm_fsm_pa_counter2_VCC_1815), + .LO(plm_fsm_pa_counter2_reg_rx_count_cry[0]), + .S(plm_fsm_pa_counter2_reg_rx_count_qxu[0]) + ); + XORCY plm_fsm_pa_counter2_reg_rx_count_s_0_ ( + .CI(N_22524_i_i_87), + .LI(plm_fsm_pa_counter2_reg_rx_count_qxu[0]), + .O(plm_fsm_pa_counter2_reg_rx_count_s[0]) + ); + MUXCY_L plm_fsm_pa_counter2_reg_rx_count_cry_1_ ( + .CI(plm_fsm_pa_counter2_reg_rx_count_cry[0]), + .DI(plm_fsm_pa_counter2_VCC_1815), + .LO(plm_fsm_pa_counter2_reg_rx_count_cry[1]), + .S(plm_fsm_pa_counter2_reg_rx_count_qxu[1]) + ); + XORCY plm_fsm_pa_counter2_reg_rx_count_s_1_ ( + .CI(plm_fsm_pa_counter2_reg_rx_count_cry[0]), + .LI(plm_fsm_pa_counter2_reg_rx_count_qxu[1]), + .O(plm_fsm_pa_counter2_reg_rx_count_s[1]) + ); + MUXCY_L plm_fsm_pa_counter2_reg_rx_count_cry_2_ ( + .CI(plm_fsm_pa_counter2_reg_rx_count_cry[1]), + .DI(plm_fsm_pa_counter2_VCC_1815), + .LO(plm_fsm_pa_counter2_reg_rx_count_cry[2]), + .S(plm_fsm_pa_counter2_reg_rx_count_qxu[2]) + ); + XORCY plm_fsm_pa_counter2_reg_rx_count_s_2_ ( + .CI(plm_fsm_pa_counter2_reg_rx_count_cry[1]), + .LI(plm_fsm_pa_counter2_reg_rx_count_qxu[2]), + .O(plm_fsm_pa_counter2_reg_rx_count_s[2]) + ); + MUXCY_L plm_fsm_pa_counter2_reg_rx_count_cry_3_ ( + .CI(plm_fsm_pa_counter2_reg_rx_count_cry[2]), + .DI(plm_fsm_pa_counter2_VCC_1815), + .LO(plm_fsm_pa_counter2_reg_rx_count_cry[3]), + .S(plm_fsm_pa_counter2_reg_rx_count_qxu[3]) + ); + XORCY plm_fsm_pa_counter2_reg_rx_count_s_3_ ( + .CI(plm_fsm_pa_counter2_reg_rx_count_cry[2]), + .LI(plm_fsm_pa_counter2_reg_rx_count_qxu[3]), + .O(plm_fsm_pa_counter2_reg_rx_count_s[3]) + ); + MUXCY_L plm_fsm_pa_counter2_reg_rx_count_cry_4_ ( + .CI(plm_fsm_pa_counter2_reg_rx_count_cry[3]), + .DI(plm_fsm_pa_counter2_VCC_1815), + .LO(plm_fsm_pa_counter2_reg_rx_count_cry[4]), + .S(plm_fsm_pa_counter2_reg_rx_count_qxu[4]) + ); + XORCY plm_fsm_pa_counter2_reg_rx_count_s_4_ ( + .CI(plm_fsm_pa_counter2_reg_rx_count_cry[3]), + .LI(plm_fsm_pa_counter2_reg_rx_count_qxu[4]), + .O(plm_fsm_pa_counter2_reg_rx_count_s[4]) + ); + MUXCY_L plm_fsm_pa_counter2_reg_rx_count_cry_5_ ( + .CI(plm_fsm_pa_counter2_reg_rx_count_cry[4]), + .DI(plm_fsm_pa_counter2_VCC_1815), + .LO(plm_fsm_pa_counter2_reg_rx_count_cry[5]), + .S(plm_fsm_pa_counter2_reg_rx_count_qxu[5]) + ); + XORCY plm_fsm_pa_counter2_reg_rx_count_s_5_ ( + .CI(plm_fsm_pa_counter2_reg_rx_count_cry[4]), + .LI(plm_fsm_pa_counter2_reg_rx_count_qxu[5]), + .O(plm_fsm_pa_counter2_reg_rx_count_s[5]) + ); + MUXCY_L plm_fsm_pa_counter2_reg_rx_count_cry_6_ ( + .CI(plm_fsm_pa_counter2_reg_rx_count_cry[5]), + .DI(plm_fsm_pa_counter2_VCC_1815), + .LO(plm_fsm_pa_counter2_reg_rx_count_cry[6]), + .S(plm_fsm_pa_counter2_reg_rx_count_qxu[6]) + ); + XORCY plm_fsm_pa_counter2_reg_rx_count_s_6_ ( + .CI(plm_fsm_pa_counter2_reg_rx_count_cry[5]), + .LI(plm_fsm_pa_counter2_reg_rx_count_qxu[6]), + .O(plm_fsm_pa_counter2_reg_rx_count_s[6]) + ); + XORCY plm_fsm_pa_counter2_reg_rx_count_s_7_ ( + .CI(plm_fsm_pa_counter2_reg_rx_count_cry[6]), + .LI(plm_fsm_pa_counter2_reg_rx_count_qxu[7]), + .O(plm_fsm_pa_counter2_reg_rx_count_s[7]) + ); + MUXCY_L plm_fsm_pa_counter2_reg_tx_count_cry_0_ ( + .CI(plm_fsm_pa_counter2_un1_enable_1_i_1816), + .DI(plm_fsm_pa_counter2_VCC_1815), + .LO(plm_fsm_pa_counter2_reg_tx_count_cry[0]), + .S(plm_fsm_pa_counter2_reg_tx_count_qxu[0]) + ); + XORCY plm_fsm_pa_counter2_reg_tx_count_s_0_ ( + .CI(plm_fsm_pa_counter2_un1_enable_1_i_1816), + .LI(plm_fsm_pa_counter2_reg_tx_count_qxu[0]), + .O(plm_fsm_pa_counter2_reg_tx_count_s[0]) + ); + MUXCY_L plm_fsm_pa_counter2_reg_tx_count_cry_1_ ( + .CI(plm_fsm_pa_counter2_reg_tx_count_cry[0]), + .DI(plm_fsm_pa_counter2_VCC_1815), + .LO(plm_fsm_pa_counter2_reg_tx_count_cry[1]), + .S(plm_fsm_pa_counter2_reg_tx_count_qxu[1]) + ); + XORCY plm_fsm_pa_counter2_reg_tx_count_s_1_ ( + .CI(plm_fsm_pa_counter2_reg_tx_count_cry[0]), + .LI(plm_fsm_pa_counter2_reg_tx_count_qxu[1]), + .O(plm_fsm_pa_counter2_reg_tx_count_s[1]) + ); + MUXCY_L plm_fsm_pa_counter2_reg_tx_count_cry_2_ ( + .CI(plm_fsm_pa_counter2_reg_tx_count_cry[1]), + .DI(plm_fsm_pa_counter2_VCC_1815), + .LO(plm_fsm_pa_counter2_reg_tx_count_cry[2]), + .S(plm_fsm_pa_counter2_reg_tx_count_qxu[2]) + ); + XORCY plm_fsm_pa_counter2_reg_tx_count_s_2_ ( + .CI(plm_fsm_pa_counter2_reg_tx_count_cry[1]), + .LI(plm_fsm_pa_counter2_reg_tx_count_qxu[2]), + .O(plm_fsm_pa_counter2_reg_tx_count_s[2]) + ); + MUXCY_L plm_fsm_pa_counter2_reg_tx_count_cry_3_ ( + .CI(plm_fsm_pa_counter2_reg_tx_count_cry[2]), + .DI(plm_fsm_pa_counter2_VCC_1815), + .LO(plm_fsm_pa_counter2_reg_tx_count_cry[3]), + .S(plm_fsm_pa_counter2_reg_tx_count_qxu[3]) + ); + XORCY plm_fsm_pa_counter2_reg_tx_count_s_3_ ( + .CI(plm_fsm_pa_counter2_reg_tx_count_cry[2]), + .LI(plm_fsm_pa_counter2_reg_tx_count_qxu[3]), + .O(plm_fsm_pa_counter2_reg_tx_count_s[3]) + ); + MUXCY_L plm_fsm_pa_counter2_reg_tx_count_cry_4_ ( + .CI(plm_fsm_pa_counter2_reg_tx_count_cry[3]), + .DI(plm_fsm_pa_counter2_VCC_1815), + .LO(plm_fsm_pa_counter2_reg_tx_count_cry[4]), + .S(plm_fsm_pa_counter2_reg_tx_count_qxu[4]) + ); + XORCY plm_fsm_pa_counter2_reg_tx_count_s_4_ ( + .CI(plm_fsm_pa_counter2_reg_tx_count_cry[3]), + .LI(plm_fsm_pa_counter2_reg_tx_count_qxu[4]), + .O(plm_fsm_pa_counter2_reg_tx_count_s[4]) + ); + MUXCY_L plm_fsm_pa_counter2_reg_tx_count_cry_5_ ( + .CI(plm_fsm_pa_counter2_reg_tx_count_cry[4]), + .DI(plm_fsm_pa_counter2_VCC_1815), + .LO(plm_fsm_pa_counter2_reg_tx_count_cry[5]), + .S(plm_fsm_pa_counter2_reg_tx_count_qxu[5]) + ); + XORCY plm_fsm_pa_counter2_reg_tx_count_s_5_ ( + .CI(plm_fsm_pa_counter2_reg_tx_count_cry[4]), + .LI(plm_fsm_pa_counter2_reg_tx_count_qxu[5]), + .O(plm_fsm_pa_counter2_reg_tx_count_s[5]) + ); + MUXCY_L plm_fsm_pa_counter2_reg_tx_count_cry_6_ ( + .CI(plm_fsm_pa_counter2_reg_tx_count_cry[5]), + .DI(plm_fsm_pa_counter2_VCC_1815), + .LO(plm_fsm_pa_counter2_reg_tx_count_cry[6]), + .S(plm_fsm_pa_counter2_reg_tx_count_qxu[6]) + ); + XORCY plm_fsm_pa_counter2_reg_tx_count_s_6_ ( + .CI(plm_fsm_pa_counter2_reg_tx_count_cry[5]), + .LI(plm_fsm_pa_counter2_reg_tx_count_qxu[6]), + .O(plm_fsm_pa_counter2_reg_tx_count_s[6]) + ); + MUXCY_L plm_fsm_pa_counter2_reg_tx_count_cry_7_ ( + .CI(plm_fsm_pa_counter2_reg_tx_count_cry[6]), + .DI(plm_fsm_pa_counter2_VCC_1815), + .LO(plm_fsm_pa_counter2_reg_tx_count_cry[7]), + .S(plm_fsm_pa_counter2_reg_tx_count_qxu[7]) + ); + XORCY plm_fsm_pa_counter2_reg_tx_count_s_7_ ( + .CI(plm_fsm_pa_counter2_reg_tx_count_cry[6]), + .LI(plm_fsm_pa_counter2_reg_tx_count_qxu[7]), + .O(plm_fsm_pa_counter2_reg_tx_count_s[7]) + ); + MUXCY_L plm_fsm_pa_counter2_reg_tx_count_cry_8_ ( + .CI(plm_fsm_pa_counter2_reg_tx_count_cry[7]), + .DI(plm_fsm_pa_counter2_VCC_1815), + .LO(plm_fsm_pa_counter2_reg_tx_count_cry[8]), + .S(plm_fsm_pa_counter2_reg_tx_count_qxu[8]) + ); + XORCY plm_fsm_pa_counter2_reg_tx_count_s_8_ ( + .CI(plm_fsm_pa_counter2_reg_tx_count_cry[7]), + .LI(plm_fsm_pa_counter2_reg_tx_count_qxu[8]), + .O(plm_fsm_pa_counter2_reg_tx_count_s[8]) + ); + MUXCY_L plm_fsm_pa_counter2_reg_tx_count_cry_9_ ( + .CI(plm_fsm_pa_counter2_reg_tx_count_cry[8]), + .DI(plm_fsm_pa_counter2_VCC_1815), + .LO(plm_fsm_pa_counter2_reg_tx_count_cry[9]), + .S(plm_fsm_pa_counter2_reg_tx_count_qxu[9]) + ); + XORCY plm_fsm_pa_counter2_reg_tx_count_s_9_ ( + .CI(plm_fsm_pa_counter2_reg_tx_count_cry[8]), + .LI(plm_fsm_pa_counter2_reg_tx_count_qxu[9]), + .O(plm_fsm_pa_counter2_reg_tx_count_s[9]) + ); + MUXCY_L plm_fsm_pa_counter2_reg_tx_count_cry_10_ ( + .CI(plm_fsm_pa_counter2_reg_tx_count_cry[9]), + .DI(plm_fsm_pa_counter2_VCC_1815), + .LO(plm_fsm_pa_counter2_reg_tx_count_cry[10]), + .S(plm_fsm_pa_counter2_reg_tx_count_qxu[10]) + ); + XORCY plm_fsm_pa_counter2_reg_tx_count_s_10_ ( + .CI(plm_fsm_pa_counter2_reg_tx_count_cry[9]), + .LI(plm_fsm_pa_counter2_reg_tx_count_qxu[10]), + .O(plm_fsm_pa_counter2_reg_tx_count_s[10]) + ); + XORCY plm_fsm_pa_counter2_reg_tx_count_s_11_ ( + .CI(plm_fsm_pa_counter2_reg_tx_count_cry[10]), + .LI(plm_fsm_pa_counter2_reg_tx_count_qxu[11]), + .O(plm_fsm_pa_counter2_reg_tx_count_s[11]) + ); + defparam plm_fsm_pa_counter2_un1_enable_2_i_i_0_0_a2_0.INIT = 4'h8; + LUT2 plm_fsm_pa_counter2_un1_enable_2_i_i_0_0_a2_0 ( + .I0(plm_fsm_pa_counter2_reg_rx_expired_86), + .I1(plm_fsm_reg_state_1__425), + .O(plm_fsm_pa_counter2_N_59118) + ); + defparam plm_fsm_pa_counter2_un1_enable_1_0_a2_0_a2_0_a2_0_a3_0_a2.INIT = 4'h4; + LUT2 plm_fsm_pa_counter2_un1_enable_1_0_a2_0_a2_0_a2_0_a3_0_a2 ( + .I0(plm_fsm_pa_counter2_reg_tx_expired_1818), + .I1(plm_fsm_reg_state_1__425), + .O(plm_fsm_pa_counter2_un1_enable_1) + ); + defparam plm_fsm_pa_counter2_un1_enable_2_i_i_0_0_a2_1.INIT = 4'h8; + LUT2 plm_fsm_pa_counter2_un1_enable_2_i_i_0_0_a2_1 ( + .I0(plm_fsm_N_56214_i), + .I1(plm_fsm_reg_state_1__425), + .O(plm_fsm_pa_counter2_N_59119) + ); + defparam plm_fsm_pa_counter2_un1_enable_2_i_i_0_0_a2_1_0.INIT = 8'h40; + LUT3 plm_fsm_pa_counter2_un1_enable_2_i_i_0_0_a2_1_0 ( + .I0(N_56125_i), + .I1(plm_fsm_reg_state_1__425), + .I2(plm_rx2_lane_pad), + .O(N_59117_1) + ); + defparam plm_fsm_pa_counter2_loadable_rx_counter_un1_reg_rx_count_0_a2_4.INIT = 16'h0001; + LUT4 plm_fsm_pa_counter2_loadable_rx_counter_un1_reg_rx_count_0_a2_4 ( + .I0(plm_fsm_pa_counter2_reg_rx_count[0]), + .I1(plm_fsm_pa_counter2_reg_rx_count[1]), + .I2(plm_fsm_pa_counter2_reg_rx_count[2]), + .I3(plm_fsm_pa_counter2_reg_rx_count[3]), + .O(plm_fsm_pa_counter2_un1_reg_rx_count_0_a2_4) + ); + defparam plm_fsm_pa_counter2_loadable_rx_counter_un1_reg_rx_count_0_a2_5.INIT = 16'h0001; + LUT4 plm_fsm_pa_counter2_loadable_rx_counter_un1_reg_rx_count_0_a2_5 ( + .I0(plm_fsm_pa_counter2_reg_rx_count[4]), + .I1(plm_fsm_pa_counter2_reg_rx_count[5]), + .I2(plm_fsm_pa_counter2_reg_rx_count[6]), + .I3(plm_fsm_pa_counter2_reg_rx_count[7]), + .O(plm_fsm_pa_counter2_un1_reg_rx_count_0_a2_5) + ); + defparam plm_fsm_pa_counter2_loadable_tx_counter_un1_reg_tx_count_0_a2_6.INIT = 16'h0001; + LUT4 plm_fsm_pa_counter2_loadable_tx_counter_un1_reg_tx_count_0_a2_6 ( + .I0(plm_fsm_pa_counter2_reg_tx_count[0]), + .I1(plm_fsm_pa_counter2_reg_tx_count[1]), + .I2(plm_fsm_pa_counter2_reg_tx_count[2]), + .I3(plm_fsm_pa_counter2_reg_tx_count[3]), + .O(plm_fsm_pa_counter2_un1_reg_tx_count_0_a2_6) + ); + defparam plm_fsm_pa_counter2_loadable_tx_counter_un1_reg_tx_count_0_a2_7.INIT = 16'h0001; + LUT4 plm_fsm_pa_counter2_loadable_tx_counter_un1_reg_tx_count_0_a2_7 ( + .I0(plm_fsm_pa_counter2_reg_tx_count[4]), + .I1(plm_fsm_pa_counter2_reg_tx_count[5]), + .I2(plm_fsm_pa_counter2_reg_tx_count[6]), + .I3(plm_fsm_pa_counter2_reg_tx_count[7]), + .O(plm_fsm_pa_counter2_un1_reg_tx_count_0_a2_7) + ); + defparam plm_fsm_pa_counter2_loadable_tx_counter_un1_reg_tx_count_0_a2_8.INIT = 16'h0001; + LUT4 plm_fsm_pa_counter2_loadable_tx_counter_un1_reg_tx_count_0_a2_8 ( + .I0(plm_fsm_pa_counter2_reg_tx_count[8]), + .I1(plm_fsm_pa_counter2_reg_tx_count[9]), + .I2(plm_fsm_pa_counter2_reg_tx_count[10]), + .I3(plm_fsm_pa_counter2_reg_tx_count[11]), + .O(plm_fsm_pa_counter2_un1_reg_tx_count_0_a2_8) + ); + defparam plm_fsm_pa_counter2_N_61006_i.INIT = 4'hB; + LUT2 plm_fsm_pa_counter2_N_61006_i ( + .I0(plm_reg_sym_sent_5_), + .I1(plm_fsm_pa_counter2_un1_enable_1), + .O(plm_fsm_pa_counter2_N_61006_i_1817) + ); + defparam plm_fsm_pa_counter2_loadable_rx_counter_un1_reg_rx_expired_1_i.INIT = 4'hD; + LUT2 plm_fsm_pa_counter2_loadable_rx_counter_un1_reg_rx_expired_1_i ( + .I0(plm_fsm_pa_counter2_N_59119), + .I1(plm_fsm_pa_counter2_reg_rx_expired_86), + .O(plm_fsm_pa_counter2_un1_reg_rx_expired_1_i) + ); + defparam plm_fsm_pa_counter2_un1_enable_2_i_i_0_0.INIT = 16'h0103; + LUT4 plm_fsm_pa_counter2_un1_enable_2_i_i_0_0 ( + .I0(N_59117_1), + .I1(plm_fsm_pa_counter2_N_59118), + .I2(plm_fsm_pa_counter2_N_59119), + .I3(plm_rx2_link_pad), + .O(plm_fsm_pa_counter2_N_28851_i) + ); + defparam plm_fsm_pa_counter2_loadable_rx_counter_N_60988_i.INIT = 8'h8F; + LUT3 plm_fsm_pa_counter2_loadable_rx_counter_N_60988_i ( + .I0(plm_fsm_pa_counter2_un1_reg_rx_count_0_a2_4), + .I1(plm_fsm_pa_counter2_un1_reg_rx_count_0_a2_5), + .I2(plm_fsm_reg_state_1__425), + .O(plm_fsm_pa_counter2_N_60988_i) + ); + defparam plm_fsm_pa_counter2_loadable_tx_counter_N_60989_i.INIT = 16'h80FF; + LUT4 plm_fsm_pa_counter2_loadable_tx_counter_N_60989_i ( + .I0(plm_fsm_pa_counter2_un1_reg_tx_count_0_a2_6), + .I1(plm_fsm_pa_counter2_un1_reg_tx_count_0_a2_7), + .I2(plm_fsm_pa_counter2_un1_reg_tx_count_0_a2_8), + .I3(plm_fsm_reg_state_1__425), + .O(plm_fsm_pa_counter2_N_60989_i) + ); + defparam plm_fsm_pa_counter2_flagit_reg_expired_5_0_a2_0_a2_0_a3_0_a2.INIT = 4'h8; + LUT2_L plm_fsm_pa_counter2_flagit_reg_expired_5_0_a2_0_a2_0_a3_0_a2 ( + .I0(plm_fsm_pa_counter2_N_59118), + .I1(plm_fsm_pa_counter2_reg_tx_expired_1818), + .LO(plm_fsm_pa_counter2_reg_expired_5) + ); + defparam plm_fsm_pa_counter2_un1_enable_1_i.INIT = 4'hD; + LUT2 plm_fsm_pa_counter2_un1_enable_1_i ( + .I0(plm_fsm_reg_state_1__425), + .I1(plm_fsm_pa_counter2_reg_tx_expired_1818), + .O(plm_fsm_pa_counter2_un1_enable_1_i_1816) + ); + FDCE plm_fsm_pa_counter2_reg_tx_count_11_ ( + .CE(plm_fsm_pa_counter2_N_61006_i_1817), + .C(mgt_clk), + .D(plm_fsm_pa_counter2_reg_tx_count_s[11]), + .Q(plm_fsm_pa_counter2_reg_tx_count[11]), + .CLR(plm_rst) + ); + FDCE plm_fsm_pa_counter2_reg_tx_count_10_ ( + .CE(plm_fsm_pa_counter2_N_61006_i_1817), + .C(mgt_clk), + .D(plm_fsm_pa_counter2_reg_tx_count_s[10]), + .Q(plm_fsm_pa_counter2_reg_tx_count[10]), + .CLR(plm_rst) + ); + FDCE plm_fsm_pa_counter2_reg_tx_count_9_ ( + .CE(plm_fsm_pa_counter2_N_61006_i_1817), + .C(mgt_clk), + .D(plm_fsm_pa_counter2_reg_tx_count_s[9]), + .Q(plm_fsm_pa_counter2_reg_tx_count[9]), + .CLR(plm_rst) + ); + FDCE plm_fsm_pa_counter2_reg_tx_count_8_ ( + .CE(plm_fsm_pa_counter2_N_61006_i_1817), + .C(mgt_clk), + .D(plm_fsm_pa_counter2_reg_tx_count_s[8]), + .Q(plm_fsm_pa_counter2_reg_tx_count[8]), + .CLR(plm_rst) + ); + FDCE plm_fsm_pa_counter2_reg_tx_count_7_ ( + .CE(plm_fsm_pa_counter2_N_61006_i_1817), + .C(mgt_clk), + .D(plm_fsm_pa_counter2_reg_tx_count_s[7]), + .Q(plm_fsm_pa_counter2_reg_tx_count[7]), + .CLR(plm_rst) + ); + FDCE plm_fsm_pa_counter2_reg_tx_count_6_ ( + .CE(plm_fsm_pa_counter2_N_61006_i_1817), + .C(mgt_clk), + .D(plm_fsm_pa_counter2_reg_tx_count_s[6]), + .Q(plm_fsm_pa_counter2_reg_tx_count[6]), + .CLR(plm_rst) + ); + FDCE plm_fsm_pa_counter2_reg_tx_count_5_ ( + .CE(plm_fsm_pa_counter2_N_61006_i_1817), + .C(mgt_clk), + .D(plm_fsm_pa_counter2_reg_tx_count_s[5]), + .Q(plm_fsm_pa_counter2_reg_tx_count[5]), + .CLR(plm_rst) + ); + FDCE plm_fsm_pa_counter2_reg_tx_count_4_ ( + .CE(plm_fsm_pa_counter2_N_61006_i_1817), + .C(mgt_clk), + .D(plm_fsm_pa_counter2_reg_tx_count_s[4]), + .Q(plm_fsm_pa_counter2_reg_tx_count[4]), + .CLR(plm_rst) + ); + FDCE plm_fsm_pa_counter2_reg_tx_count_3_ ( + .CE(plm_fsm_pa_counter2_N_61006_i_1817), + .C(mgt_clk), + .D(plm_fsm_pa_counter2_reg_tx_count_s[3]), + .Q(plm_fsm_pa_counter2_reg_tx_count[3]), + .CLR(plm_rst) + ); + FDCE plm_fsm_pa_counter2_reg_tx_count_2_ ( + .CE(plm_fsm_pa_counter2_N_61006_i_1817), + .C(mgt_clk), + .D(plm_fsm_pa_counter2_reg_tx_count_s[2]), + .Q(plm_fsm_pa_counter2_reg_tx_count[2]), + .CLR(plm_rst) + ); + FDCE plm_fsm_pa_counter2_reg_tx_count_1_ ( + .CE(plm_fsm_pa_counter2_N_61006_i_1817), + .C(mgt_clk), + .D(plm_fsm_pa_counter2_reg_tx_count_s[1]), + .Q(plm_fsm_pa_counter2_reg_tx_count[1]), + .CLR(plm_rst) + ); + FDCE plm_fsm_pa_counter2_reg_tx_count_0_ ( + .CE(plm_fsm_pa_counter2_N_61006_i_1817), + .C(mgt_clk), + .D(plm_fsm_pa_counter2_reg_tx_count_s[0]), + .Q(plm_fsm_pa_counter2_reg_tx_count[0]), + .CLR(plm_rst) + ); + FDCE plm_fsm_pa_counter2_reg_rx_count_7_ ( + .CE(plm_fsm_pa_counter2_un1_reg_rx_expired_1_i), + .C(mgt_clk), + .D(plm_fsm_pa_counter2_reg_rx_count_s[7]), + .Q(plm_fsm_pa_counter2_reg_rx_count[7]), + .CLR(plm_rst) + ); + FDCE plm_fsm_pa_counter2_reg_rx_count_6_ ( + .CE(plm_fsm_pa_counter2_un1_reg_rx_expired_1_i), + .C(mgt_clk), + .D(plm_fsm_pa_counter2_reg_rx_count_s[6]), + .Q(plm_fsm_pa_counter2_reg_rx_count[6]), + .CLR(plm_rst) + ); + FDCE plm_fsm_pa_counter2_reg_rx_count_5_ ( + .CE(plm_fsm_pa_counter2_un1_reg_rx_expired_1_i), + .C(mgt_clk), + .D(plm_fsm_pa_counter2_reg_rx_count_s[5]), + .Q(plm_fsm_pa_counter2_reg_rx_count[5]), + .CLR(plm_rst) + ); + FDCE plm_fsm_pa_counter2_reg_rx_count_4_ ( + .CE(plm_fsm_pa_counter2_un1_reg_rx_expired_1_i), + .C(mgt_clk), + .D(plm_fsm_pa_counter2_reg_rx_count_s[4]), + .Q(plm_fsm_pa_counter2_reg_rx_count[4]), + .CLR(plm_rst) + ); + FDCE plm_fsm_pa_counter2_reg_rx_count_3_ ( + .CE(plm_fsm_pa_counter2_un1_reg_rx_expired_1_i), + .C(mgt_clk), + .D(plm_fsm_pa_counter2_reg_rx_count_s[3]), + .Q(plm_fsm_pa_counter2_reg_rx_count[3]), + .CLR(plm_rst) + ); + FDCE plm_fsm_pa_counter2_reg_rx_count_2_ ( + .CE(plm_fsm_pa_counter2_un1_reg_rx_expired_1_i), + .C(mgt_clk), + .D(plm_fsm_pa_counter2_reg_rx_count_s[2]), + .Q(plm_fsm_pa_counter2_reg_rx_count[2]), + .CLR(plm_rst) + ); + FDCE plm_fsm_pa_counter2_reg_rx_count_1_ ( + .CE(plm_fsm_pa_counter2_un1_reg_rx_expired_1_i), + .C(mgt_clk), + .D(plm_fsm_pa_counter2_reg_rx_count_s[1]), + .Q(plm_fsm_pa_counter2_reg_rx_count[1]), + .CLR(plm_rst) + ); + FDCE plm_fsm_pa_counter2_reg_rx_count_0_ ( + .CE(plm_fsm_pa_counter2_un1_reg_rx_expired_1_i), + .C(mgt_clk), + .D(plm_fsm_pa_counter2_reg_rx_count_s[0]), + .Q(plm_fsm_pa_counter2_reg_rx_count[0]), + .CLR(plm_rst) + ); + FDC plm_fsm_pa_counter2_reg_expired ( + .C(mgt_clk), + .D(plm_fsm_pa_counter2_reg_expired_5), + .Q(plm_fsm_pa_cntrout2), + .CLR(plm_rst) + ); + FDCE plm_fsm_pa_counter2_reg_tx_expired ( + .CE(plm_fsm_pa_counter2_N_60989_i), + .C(mgt_clk), + .D(plm_fsm_reg_state_1__425), + .Q(plm_fsm_pa_counter2_reg_tx_expired_1818), + .CLR(plm_rst) + ); + FDCE plm_fsm_pa_counter2_reg_rx_expired ( + .CE(plm_fsm_pa_counter2_N_60988_i), + .C(mgt_clk), + .D(plm_fsm_reg_state_1__425), + .Q(plm_fsm_pa_counter2_reg_rx_expired_86), + .CLR(plm_rst) + ); + defparam plm_fsm_pa_counter2_reg_rx_count_qxu_0_0_.INIT = 4'h7; + LUT2_L plm_fsm_pa_counter2_reg_rx_count_qxu_0_0_ ( + .I0(N_22524_i), + .I1(plm_fsm_pa_counter2_reg_rx_count[0]), + .LO(plm_fsm_pa_counter2_reg_rx_count_qxu[0]) + ); + defparam plm_fsm_pa_counter2_reg_rx_count_qxu_0_1_.INIT = 4'h7; + LUT2_L plm_fsm_pa_counter2_reg_rx_count_qxu_0_1_ ( + .I0(N_22524_i), + .I1(plm_fsm_pa_counter2_reg_rx_count[1]), + .LO(plm_fsm_pa_counter2_reg_rx_count_qxu[1]) + ); + defparam plm_fsm_pa_counter2_reg_rx_count_qxu_0_2_.INIT = 4'h7; + LUT2_L plm_fsm_pa_counter2_reg_rx_count_qxu_0_2_ ( + .I0(N_22524_i), + .I1(plm_fsm_pa_counter2_reg_rx_count[2]), + .LO(plm_fsm_pa_counter2_reg_rx_count_qxu[2]) + ); + defparam plm_fsm_pa_counter2_reg_rx_count_qxu_0_3_.INIT = 8'h1B; + LUT3_L plm_fsm_pa_counter2_reg_rx_count_qxu_0_3_ ( + .I0(N_22524_i), + .I1(plm_fsm_pa_counter2_N_28851_i), + .I2(plm_fsm_pa_counter2_reg_rx_count[3]), + .LO(plm_fsm_pa_counter2_reg_rx_count_qxu[3]) + ); + defparam plm_fsm_pa_counter2_reg_rx_count_qxu_0_4_.INIT = 4'h7; + LUT2_L plm_fsm_pa_counter2_reg_rx_count_qxu_0_4_ ( + .I0(N_22524_i), + .I1(plm_fsm_pa_counter2_reg_rx_count[4]), + .LO(plm_fsm_pa_counter2_reg_rx_count_qxu[4]) + ); + defparam plm_fsm_pa_counter2_reg_rx_count_qxu_0_5_.INIT = 4'h7; + LUT2_L plm_fsm_pa_counter2_reg_rx_count_qxu_0_5_ ( + .I0(N_22524_i), + .I1(plm_fsm_pa_counter2_reg_rx_count[5]), + .LO(plm_fsm_pa_counter2_reg_rx_count_qxu[5]) + ); + defparam plm_fsm_pa_counter2_reg_rx_count_qxu_0_6_.INIT = 4'h7; + LUT2_L plm_fsm_pa_counter2_reg_rx_count_qxu_0_6_ ( + .I0(N_22524_i), + .I1(plm_fsm_pa_counter2_reg_rx_count[6]), + .LO(plm_fsm_pa_counter2_reg_rx_count_qxu[6]) + ); + defparam plm_fsm_pa_counter2_reg_rx_count_qxu_0_7_.INIT = 4'h7; + LUT2_L plm_fsm_pa_counter2_reg_rx_count_qxu_0_7_ ( + .I0(N_22524_i), + .I1(plm_fsm_pa_counter2_reg_rx_count[7]), + .LO(plm_fsm_pa_counter2_reg_rx_count_qxu[7]) + ); + defparam plm_fsm_pa_counter2_reg_tx_count_qxu_0_0_.INIT = 4'h7; + LUT2_L plm_fsm_pa_counter2_reg_tx_count_qxu_0_0_ ( + .I0(plm_fsm_pa_counter2_reg_tx_count[0]), + .I1(plm_fsm_pa_counter2_un1_enable_1), + .LO(plm_fsm_pa_counter2_reg_tx_count_qxu[0]) + ); + defparam plm_fsm_pa_counter2_reg_tx_count_qxu_0_1_.INIT = 4'h7; + LUT2_L plm_fsm_pa_counter2_reg_tx_count_qxu_0_1_ ( + .I0(plm_fsm_pa_counter2_reg_tx_count[1]), + .I1(plm_fsm_pa_counter2_un1_enable_1), + .LO(plm_fsm_pa_counter2_reg_tx_count_qxu[1]) + ); + defparam plm_fsm_pa_counter2_reg_tx_count_qxu_0_2_.INIT = 4'h7; + LUT2_L plm_fsm_pa_counter2_reg_tx_count_qxu_0_2_ ( + .I0(plm_fsm_pa_counter2_reg_tx_count[2]), + .I1(plm_fsm_pa_counter2_un1_enable_1), + .LO(plm_fsm_pa_counter2_reg_tx_count_qxu[2]) + ); + defparam plm_fsm_pa_counter2_reg_tx_count_qxu_0_3_.INIT = 4'h7; + LUT2_L plm_fsm_pa_counter2_reg_tx_count_qxu_0_3_ ( + .I0(plm_fsm_pa_counter2_reg_tx_count[3]), + .I1(plm_fsm_pa_counter2_un1_enable_1), + .LO(plm_fsm_pa_counter2_reg_tx_count_qxu[3]) + ); + defparam plm_fsm_pa_counter2_reg_tx_count_qxu_0_4_.INIT = 8'h35; + LUT3_L plm_fsm_pa_counter2_reg_tx_count_qxu_0_4_ ( + .I0(plm_fsm_reg_tx_count_6_4_), + .I1(plm_fsm_pa_counter2_reg_tx_count[4]), + .I2(plm_fsm_pa_counter2_un1_enable_1), + .LO(plm_fsm_pa_counter2_reg_tx_count_qxu[4]) + ); + defparam plm_fsm_pa_counter2_reg_tx_count_qxu_0_5_.INIT = 4'h7; + LUT2_L plm_fsm_pa_counter2_reg_tx_count_qxu_0_5_ ( + .I0(plm_fsm_pa_counter2_reg_tx_count[5]), + .I1(plm_fsm_pa_counter2_un1_enable_1), + .LO(plm_fsm_pa_counter2_reg_tx_count_qxu[5]) + ); + defparam plm_fsm_pa_counter2_reg_tx_count_qxu_0_6_.INIT = 4'h7; + LUT2_L plm_fsm_pa_counter2_reg_tx_count_qxu_0_6_ ( + .I0(plm_fsm_pa_counter2_reg_tx_count[6]), + .I1(plm_fsm_pa_counter2_un1_enable_1), + .LO(plm_fsm_pa_counter2_reg_tx_count_qxu[6]) + ); + defparam plm_fsm_pa_counter2_reg_tx_count_qxu_0_7_.INIT = 4'h7; + LUT2_L plm_fsm_pa_counter2_reg_tx_count_qxu_0_7_ ( + .I0(plm_fsm_pa_counter2_reg_tx_count[7]), + .I1(plm_fsm_pa_counter2_un1_enable_1), + .LO(plm_fsm_pa_counter2_reg_tx_count_qxu[7]) + ); + defparam plm_fsm_pa_counter2_reg_tx_count_qxu_0_8_.INIT = 4'h7; + LUT2_L plm_fsm_pa_counter2_reg_tx_count_qxu_0_8_ ( + .I0(plm_fsm_pa_counter2_reg_tx_count[8]), + .I1(plm_fsm_pa_counter2_un1_enable_1), + .LO(plm_fsm_pa_counter2_reg_tx_count_qxu[8]) + ); + defparam plm_fsm_pa_counter2_reg_tx_count_qxu_0_9_.INIT = 4'h7; + LUT2_L plm_fsm_pa_counter2_reg_tx_count_qxu_0_9_ ( + .I0(plm_fsm_pa_counter2_reg_tx_count[9]), + .I1(plm_fsm_pa_counter2_un1_enable_1), + .LO(plm_fsm_pa_counter2_reg_tx_count_qxu[9]) + ); + defparam plm_fsm_pa_counter2_reg_tx_count_qxu_0_10_.INIT = 8'h35; + LUT3_L plm_fsm_pa_counter2_reg_tx_count_qxu_0_10_ ( + .I0(plm_fsm_reg_tx_count_6_10_), + .I1(plm_fsm_pa_counter2_reg_tx_count[10]), + .I2(plm_fsm_pa_counter2_un1_enable_1), + .LO(plm_fsm_pa_counter2_reg_tx_count_qxu[10]) + ); + defparam plm_fsm_pa_counter2_reg_tx_count_qxu_0_11_.INIT = 4'h7; + LUT2_L plm_fsm_pa_counter2_reg_tx_count_qxu_0_11_ ( + .I0(plm_fsm_pa_counter2_reg_tx_count[11]), + .I1(plm_fsm_pa_counter2_un1_enable_1), + .LO(plm_fsm_pa_counter2_reg_tx_count_qxu[11]) + ); + VCC plm_fsm_pa_counter3_VCC ( + .P(plm_fsm_pa_counter3_VCC_1819) + ); + MUXCY_L plm_fsm_pa_counter3_reg_rx_count_cry_0_ ( + .CI(N_22668_i_i_83), + .DI(plm_fsm_pa_counter3_VCC_1819), + .LO(plm_fsm_pa_counter3_reg_rx_count_cry[0]), + .S(plm_fsm_pa_counter3_reg_rx_count_qxu[0]) + ); + XORCY plm_fsm_pa_counter3_reg_rx_count_s_0_ ( + .CI(N_22668_i_i_83), + .LI(plm_fsm_pa_counter3_reg_rx_count_qxu[0]), + .O(plm_fsm_pa_counter3_reg_rx_count_s[0]) + ); + MUXCY_L plm_fsm_pa_counter3_reg_rx_count_cry_1_ ( + .CI(plm_fsm_pa_counter3_reg_rx_count_cry[0]), + .DI(plm_fsm_pa_counter3_VCC_1819), + .LO(plm_fsm_pa_counter3_reg_rx_count_cry[1]), + .S(plm_fsm_pa_counter3_reg_rx_count_qxu[1]) + ); + XORCY plm_fsm_pa_counter3_reg_rx_count_s_1_ ( + .CI(plm_fsm_pa_counter3_reg_rx_count_cry[0]), + .LI(plm_fsm_pa_counter3_reg_rx_count_qxu[1]), + .O(plm_fsm_pa_counter3_reg_rx_count_s[1]) + ); + MUXCY_L plm_fsm_pa_counter3_reg_rx_count_cry_2_ ( + .CI(plm_fsm_pa_counter3_reg_rx_count_cry[1]), + .DI(plm_fsm_pa_counter3_VCC_1819), + .LO(plm_fsm_pa_counter3_reg_rx_count_cry[2]), + .S(plm_fsm_pa_counter3_reg_rx_count_qxu[2]) + ); + XORCY plm_fsm_pa_counter3_reg_rx_count_s_2_ ( + .CI(plm_fsm_pa_counter3_reg_rx_count_cry[1]), + .LI(plm_fsm_pa_counter3_reg_rx_count_qxu[2]), + .O(plm_fsm_pa_counter3_reg_rx_count_s[2]) + ); + MUXCY_L plm_fsm_pa_counter3_reg_rx_count_cry_3_ ( + .CI(plm_fsm_pa_counter3_reg_rx_count_cry[2]), + .DI(plm_fsm_pa_counter3_VCC_1819), + .LO(plm_fsm_pa_counter3_reg_rx_count_cry[3]), + .S(plm_fsm_pa_counter3_reg_rx_count_qxu[3]) + ); + XORCY plm_fsm_pa_counter3_reg_rx_count_s_3_ ( + .CI(plm_fsm_pa_counter3_reg_rx_count_cry[2]), + .LI(plm_fsm_pa_counter3_reg_rx_count_qxu[3]), + .O(plm_fsm_pa_counter3_reg_rx_count_s[3]) + ); + MUXCY_L plm_fsm_pa_counter3_reg_rx_count_cry_4_ ( + .CI(plm_fsm_pa_counter3_reg_rx_count_cry[3]), + .DI(plm_fsm_pa_counter3_VCC_1819), + .LO(plm_fsm_pa_counter3_reg_rx_count_cry[4]), + .S(plm_fsm_pa_counter3_reg_rx_count_qxu[4]) + ); + XORCY plm_fsm_pa_counter3_reg_rx_count_s_4_ ( + .CI(plm_fsm_pa_counter3_reg_rx_count_cry[3]), + .LI(plm_fsm_pa_counter3_reg_rx_count_qxu[4]), + .O(plm_fsm_pa_counter3_reg_rx_count_s[4]) + ); + MUXCY_L plm_fsm_pa_counter3_reg_rx_count_cry_5_ ( + .CI(plm_fsm_pa_counter3_reg_rx_count_cry[4]), + .DI(plm_fsm_pa_counter3_VCC_1819), + .LO(plm_fsm_pa_counter3_reg_rx_count_cry[5]), + .S(plm_fsm_pa_counter3_reg_rx_count_qxu[5]) + ); + XORCY plm_fsm_pa_counter3_reg_rx_count_s_5_ ( + .CI(plm_fsm_pa_counter3_reg_rx_count_cry[4]), + .LI(plm_fsm_pa_counter3_reg_rx_count_qxu[5]), + .O(plm_fsm_pa_counter3_reg_rx_count_s[5]) + ); + MUXCY_L plm_fsm_pa_counter3_reg_rx_count_cry_6_ ( + .CI(plm_fsm_pa_counter3_reg_rx_count_cry[5]), + .DI(plm_fsm_pa_counter3_VCC_1819), + .LO(plm_fsm_pa_counter3_reg_rx_count_cry[6]), + .S(plm_fsm_pa_counter3_reg_rx_count_qxu[6]) + ); + XORCY plm_fsm_pa_counter3_reg_rx_count_s_6_ ( + .CI(plm_fsm_pa_counter3_reg_rx_count_cry[5]), + .LI(plm_fsm_pa_counter3_reg_rx_count_qxu[6]), + .O(plm_fsm_pa_counter3_reg_rx_count_s[6]) + ); + XORCY plm_fsm_pa_counter3_reg_rx_count_s_7_ ( + .CI(plm_fsm_pa_counter3_reg_rx_count_cry[6]), + .LI(plm_fsm_pa_counter3_reg_rx_count_qxu[7]), + .O(plm_fsm_pa_counter3_reg_rx_count_s[7]) + ); + MUXCY_L plm_fsm_pa_counter3_reg_tx_count_cry_0_ ( + .CI(plm_fsm_pa_counter3_un1_enable_1_i_1820), + .DI(plm_fsm_pa_counter3_VCC_1819), + .LO(plm_fsm_pa_counter3_reg_tx_count_cry[0]), + .S(plm_fsm_pa_counter3_reg_tx_count_qxu[0]) + ); + XORCY plm_fsm_pa_counter3_reg_tx_count_s_0_ ( + .CI(plm_fsm_pa_counter3_un1_enable_1_i_1820), + .LI(plm_fsm_pa_counter3_reg_tx_count_qxu[0]), + .O(plm_fsm_pa_counter3_reg_tx_count_s[0]) + ); + MUXCY_L plm_fsm_pa_counter3_reg_tx_count_cry_1_ ( + .CI(plm_fsm_pa_counter3_reg_tx_count_cry[0]), + .DI(plm_fsm_pa_counter3_VCC_1819), + .LO(plm_fsm_pa_counter3_reg_tx_count_cry[1]), + .S(plm_fsm_pa_counter3_reg_tx_count_qxu[1]) + ); + XORCY plm_fsm_pa_counter3_reg_tx_count_s_1_ ( + .CI(plm_fsm_pa_counter3_reg_tx_count_cry[0]), + .LI(plm_fsm_pa_counter3_reg_tx_count_qxu[1]), + .O(plm_fsm_pa_counter3_reg_tx_count_s[1]) + ); + MUXCY_L plm_fsm_pa_counter3_reg_tx_count_cry_2_ ( + .CI(plm_fsm_pa_counter3_reg_tx_count_cry[1]), + .DI(plm_fsm_pa_counter3_VCC_1819), + .LO(plm_fsm_pa_counter3_reg_tx_count_cry[2]), + .S(plm_fsm_pa_counter3_reg_tx_count_qxu[2]) + ); + XORCY plm_fsm_pa_counter3_reg_tx_count_s_2_ ( + .CI(plm_fsm_pa_counter3_reg_tx_count_cry[1]), + .LI(plm_fsm_pa_counter3_reg_tx_count_qxu[2]), + .O(plm_fsm_pa_counter3_reg_tx_count_s[2]) + ); + MUXCY_L plm_fsm_pa_counter3_reg_tx_count_cry_3_ ( + .CI(plm_fsm_pa_counter3_reg_tx_count_cry[2]), + .DI(plm_fsm_pa_counter3_VCC_1819), + .LO(plm_fsm_pa_counter3_reg_tx_count_cry[3]), + .S(plm_fsm_pa_counter3_reg_tx_count_qxu[3]) + ); + XORCY plm_fsm_pa_counter3_reg_tx_count_s_3_ ( + .CI(plm_fsm_pa_counter3_reg_tx_count_cry[2]), + .LI(plm_fsm_pa_counter3_reg_tx_count_qxu[3]), + .O(plm_fsm_pa_counter3_reg_tx_count_s[3]) + ); + MUXCY_L plm_fsm_pa_counter3_reg_tx_count_cry_4_ ( + .CI(plm_fsm_pa_counter3_reg_tx_count_cry[3]), + .DI(plm_fsm_pa_counter3_VCC_1819), + .LO(plm_fsm_pa_counter3_reg_tx_count_cry[4]), + .S(plm_fsm_pa_counter3_reg_tx_count_qxu[4]) + ); + XORCY plm_fsm_pa_counter3_reg_tx_count_s_4_ ( + .CI(plm_fsm_pa_counter3_reg_tx_count_cry[3]), + .LI(plm_fsm_pa_counter3_reg_tx_count_qxu[4]), + .O(plm_fsm_pa_counter3_reg_tx_count_s[4]) + ); + MUXCY_L plm_fsm_pa_counter3_reg_tx_count_cry_5_ ( + .CI(plm_fsm_pa_counter3_reg_tx_count_cry[4]), + .DI(plm_fsm_pa_counter3_VCC_1819), + .LO(plm_fsm_pa_counter3_reg_tx_count_cry[5]), + .S(plm_fsm_pa_counter3_reg_tx_count_qxu[5]) + ); + XORCY plm_fsm_pa_counter3_reg_tx_count_s_5_ ( + .CI(plm_fsm_pa_counter3_reg_tx_count_cry[4]), + .LI(plm_fsm_pa_counter3_reg_tx_count_qxu[5]), + .O(plm_fsm_pa_counter3_reg_tx_count_s[5]) + ); + MUXCY_L plm_fsm_pa_counter3_reg_tx_count_cry_6_ ( + .CI(plm_fsm_pa_counter3_reg_tx_count_cry[5]), + .DI(plm_fsm_pa_counter3_VCC_1819), + .LO(plm_fsm_pa_counter3_reg_tx_count_cry[6]), + .S(plm_fsm_pa_counter3_reg_tx_count_qxu[6]) + ); + XORCY plm_fsm_pa_counter3_reg_tx_count_s_6_ ( + .CI(plm_fsm_pa_counter3_reg_tx_count_cry[5]), + .LI(plm_fsm_pa_counter3_reg_tx_count_qxu[6]), + .O(plm_fsm_pa_counter3_reg_tx_count_s[6]) + ); + MUXCY_L plm_fsm_pa_counter3_reg_tx_count_cry_7_ ( + .CI(plm_fsm_pa_counter3_reg_tx_count_cry[6]), + .DI(plm_fsm_pa_counter3_VCC_1819), + .LO(plm_fsm_pa_counter3_reg_tx_count_cry[7]), + .S(plm_fsm_pa_counter3_reg_tx_count_qxu[7]) + ); + XORCY plm_fsm_pa_counter3_reg_tx_count_s_7_ ( + .CI(plm_fsm_pa_counter3_reg_tx_count_cry[6]), + .LI(plm_fsm_pa_counter3_reg_tx_count_qxu[7]), + .O(plm_fsm_pa_counter3_reg_tx_count_s[7]) + ); + MUXCY_L plm_fsm_pa_counter3_reg_tx_count_cry_8_ ( + .CI(plm_fsm_pa_counter3_reg_tx_count_cry[7]), + .DI(plm_fsm_pa_counter3_VCC_1819), + .LO(plm_fsm_pa_counter3_reg_tx_count_cry[8]), + .S(plm_fsm_pa_counter3_reg_tx_count_qxu[8]) + ); + XORCY plm_fsm_pa_counter3_reg_tx_count_s_8_ ( + .CI(plm_fsm_pa_counter3_reg_tx_count_cry[7]), + .LI(plm_fsm_pa_counter3_reg_tx_count_qxu[8]), + .O(plm_fsm_pa_counter3_reg_tx_count_s[8]) + ); + MUXCY_L plm_fsm_pa_counter3_reg_tx_count_cry_9_ ( + .CI(plm_fsm_pa_counter3_reg_tx_count_cry[8]), + .DI(plm_fsm_pa_counter3_VCC_1819), + .LO(plm_fsm_pa_counter3_reg_tx_count_cry[9]), + .S(plm_fsm_pa_counter3_reg_tx_count_qxu[9]) + ); + XORCY plm_fsm_pa_counter3_reg_tx_count_s_9_ ( + .CI(plm_fsm_pa_counter3_reg_tx_count_cry[8]), + .LI(plm_fsm_pa_counter3_reg_tx_count_qxu[9]), + .O(plm_fsm_pa_counter3_reg_tx_count_s[9]) + ); + MUXCY_L plm_fsm_pa_counter3_reg_tx_count_cry_10_ ( + .CI(plm_fsm_pa_counter3_reg_tx_count_cry[9]), + .DI(plm_fsm_pa_counter3_VCC_1819), + .LO(plm_fsm_pa_counter3_reg_tx_count_cry[10]), + .S(plm_fsm_pa_counter3_reg_tx_count_qxu[10]) + ); + XORCY plm_fsm_pa_counter3_reg_tx_count_s_10_ ( + .CI(plm_fsm_pa_counter3_reg_tx_count_cry[9]), + .LI(plm_fsm_pa_counter3_reg_tx_count_qxu[10]), + .O(plm_fsm_pa_counter3_reg_tx_count_s[10]) + ); + XORCY plm_fsm_pa_counter3_reg_tx_count_s_11_ ( + .CI(plm_fsm_pa_counter3_reg_tx_count_cry[10]), + .LI(plm_fsm_pa_counter3_reg_tx_count_qxu[11]), + .O(plm_fsm_pa_counter3_reg_tx_count_s[11]) + ); + defparam plm_fsm_pa_counter3_loadable_tx_counter_reg_tx_count_6_0_a2_0_a2_0_a2_0_a3_0_a2_4_.INIT = 4'h2; + LUT2 plm_fsm_pa_counter3_loadable_tx_counter_reg_tx_count_6_0_a2_0_a2_0_a2_0_a3_0_a2_4_ ( + .I0(cfg_cfg_6102[507]), + .I1(plm_fsm_reg_state_1__425), + .O(plm_fsm_reg_tx_count_6_4_) + ); + defparam plm_fsm_pa_counter3_loadable_tx_counter_reg_tx_count_6_0_a2_0_a2_0_a2_0_a3_0_a2_10_.INIT = 4'h1; + LUT2 plm_fsm_pa_counter3_loadable_tx_counter_reg_tx_count_6_0_a2_0_a2_0_a2_0_a3_0_a2_10_ ( + .I0(cfg_cfg_6102[507]), + .I1(plm_fsm_reg_state_1__425), + .O(plm_fsm_reg_tx_count_6_10_) + ); + defparam plm_fsm_pa_counter3_un1_enable_2_i_i_0_0_a2_0.INIT = 4'h8; + LUT2 plm_fsm_pa_counter3_un1_enable_2_i_i_0_0_a2_0 ( + .I0(plm_fsm_pa_counter3_reg_rx_expired_82), + .I1(plm_fsm_reg_state_1__425), + .O(plm_fsm_pa_counter3_N_59115) + ); + defparam plm_fsm_pa_counter3_un1_enable_1_0_a2_0_a2_0_a2_0_a3_0_a2.INIT = 4'h4; + LUT2 plm_fsm_pa_counter3_un1_enable_1_0_a2_0_a2_0_a2_0_a3_0_a2 ( + .I0(plm_fsm_pa_counter3_reg_tx_expired_1822), + .I1(plm_fsm_reg_state_1__425), + .O(plm_fsm_pa_counter3_un1_enable_1) + ); + defparam plm_fsm_pa_counter3_un1_enable_2_i_i_0_0_a2_1.INIT = 8'h10; + LUT3 plm_fsm_pa_counter3_un1_enable_2_i_i_0_0_a2_1 ( + .I0(plm_reg_ts2_1_2), + .I1(plm_reg_ts1_1_2), + .I2(plm_fsm_reg_state_1__425), + .O(plm_fsm_pa_counter3_N_59116) + ); + defparam plm_fsm_pa_counter3_un1_enable_2_i_i_0_0_a2_2.INIT = 4'h4; + LUT2 plm_fsm_pa_counter3_un1_enable_2_i_i_0_0_a2_2 ( + .I0(N_56124_i), + .I1(plm_fsm_reg_state_1__425), + .O(N_59114_2) + ); + defparam plm_fsm_pa_counter3_loadable_rx_counter_un1_reg_rx_count_0_a2_4.INIT = 16'h0001; + LUT4 plm_fsm_pa_counter3_loadable_rx_counter_un1_reg_rx_count_0_a2_4 ( + .I0(plm_fsm_pa_counter3_reg_rx_count[0]), + .I1(plm_fsm_pa_counter3_reg_rx_count[1]), + .I2(plm_fsm_pa_counter3_reg_rx_count[2]), + .I3(plm_fsm_pa_counter3_reg_rx_count[3]), + .O(plm_fsm_pa_counter3_un1_reg_rx_count_0_a2_4) + ); + defparam plm_fsm_pa_counter3_loadable_rx_counter_un1_reg_rx_count_0_a2_5.INIT = 16'h0001; + LUT4 plm_fsm_pa_counter3_loadable_rx_counter_un1_reg_rx_count_0_a2_5 ( + .I0(plm_fsm_pa_counter3_reg_rx_count[4]), + .I1(plm_fsm_pa_counter3_reg_rx_count[5]), + .I2(plm_fsm_pa_counter3_reg_rx_count[6]), + .I3(plm_fsm_pa_counter3_reg_rx_count[7]), + .O(plm_fsm_pa_counter3_un1_reg_rx_count_0_a2_5) + ); + defparam plm_fsm_pa_counter3_loadable_tx_counter_un1_reg_tx_count_0_a2_6.INIT = 16'h0001; + LUT4 plm_fsm_pa_counter3_loadable_tx_counter_un1_reg_tx_count_0_a2_6 ( + .I0(plm_fsm_pa_counter3_reg_tx_count[0]), + .I1(plm_fsm_pa_counter3_reg_tx_count[1]), + .I2(plm_fsm_pa_counter3_reg_tx_count[2]), + .I3(plm_fsm_pa_counter3_reg_tx_count[3]), + .O(plm_fsm_pa_counter3_un1_reg_tx_count_0_a2_6) + ); + defparam plm_fsm_pa_counter3_loadable_tx_counter_un1_reg_tx_count_0_a2_7.INIT = 16'h0001; + LUT4 plm_fsm_pa_counter3_loadable_tx_counter_un1_reg_tx_count_0_a2_7 ( + .I0(plm_fsm_pa_counter3_reg_tx_count[4]), + .I1(plm_fsm_pa_counter3_reg_tx_count[5]), + .I2(plm_fsm_pa_counter3_reg_tx_count[6]), + .I3(plm_fsm_pa_counter3_reg_tx_count[7]), + .O(plm_fsm_pa_counter3_un1_reg_tx_count_0_a2_7) + ); + defparam plm_fsm_pa_counter3_loadable_tx_counter_un1_reg_tx_count_0_a2_8.INIT = 16'h0001; + LUT4 plm_fsm_pa_counter3_loadable_tx_counter_un1_reg_tx_count_0_a2_8 ( + .I0(plm_fsm_pa_counter3_reg_tx_count[8]), + .I1(plm_fsm_pa_counter3_reg_tx_count[9]), + .I2(plm_fsm_pa_counter3_reg_tx_count[10]), + .I3(plm_fsm_pa_counter3_reg_tx_count[11]), + .O(plm_fsm_pa_counter3_un1_reg_tx_count_0_a2_8) + ); + defparam plm_fsm_pa_counter3_N_61007_i.INIT = 4'hB; + LUT2 plm_fsm_pa_counter3_N_61007_i ( + .I0(plm_reg_sym_sent_5_), + .I1(plm_fsm_pa_counter3_un1_enable_1), + .O(plm_fsm_pa_counter3_N_61007_i_1821) + ); + defparam plm_fsm_pa_counter3_loadable_rx_counter_un1_reg_rx_expired_1_i.INIT = 4'hD; + LUT2 plm_fsm_pa_counter3_loadable_rx_counter_un1_reg_rx_expired_1_i ( + .I0(plm_fsm_pa_counter3_N_59116), + .I1(plm_fsm_pa_counter3_reg_rx_expired_82), + .O(plm_fsm_pa_counter3_un1_reg_rx_expired_1_i) + ); + defparam plm_fsm_pa_counter3_un1_enable_2_i_i_0_0.INIT = 16'h0007; + LUT4 plm_fsm_pa_counter3_un1_enable_2_i_i_0_0 ( + .I0(N_22668_i_1), + .I1(N_59114_2), + .I2(plm_fsm_pa_counter3_N_59115), + .I3(plm_fsm_pa_counter3_N_59116), + .O(plm_fsm_pa_counter3_N_28849_i) + ); + defparam plm_fsm_pa_counter3_loadable_rx_counter_N_60985_i.INIT = 8'h8F; + LUT3 plm_fsm_pa_counter3_loadable_rx_counter_N_60985_i ( + .I0(plm_fsm_pa_counter3_un1_reg_rx_count_0_a2_4), + .I1(plm_fsm_pa_counter3_un1_reg_rx_count_0_a2_5), + .I2(plm_fsm_reg_state_1__425), + .O(plm_fsm_pa_counter3_N_60985_i) + ); + defparam plm_fsm_pa_counter3_loadable_tx_counter_N_60986_i.INIT = 16'h80FF; + LUT4 plm_fsm_pa_counter3_loadable_tx_counter_N_60986_i ( + .I0(plm_fsm_pa_counter3_un1_reg_tx_count_0_a2_6), + .I1(plm_fsm_pa_counter3_un1_reg_tx_count_0_a2_7), + .I2(plm_fsm_pa_counter3_un1_reg_tx_count_0_a2_8), + .I3(plm_fsm_reg_state_1__425), + .O(plm_fsm_pa_counter3_N_60986_i) + ); + defparam plm_fsm_pa_counter3_flagit_reg_expired_5_0_a2_0_a2_0_a3_0_a2.INIT = 4'h8; + LUT2_L plm_fsm_pa_counter3_flagit_reg_expired_5_0_a2_0_a2_0_a3_0_a2 ( + .I0(plm_fsm_pa_counter3_N_59115), + .I1(plm_fsm_pa_counter3_reg_tx_expired_1822), + .LO(plm_fsm_pa_counter3_reg_expired_5) + ); + defparam plm_fsm_pa_counter3_un1_enable_1_i.INIT = 4'hD; + LUT2 plm_fsm_pa_counter3_un1_enable_1_i ( + .I0(plm_fsm_reg_state_1__425), + .I1(plm_fsm_pa_counter3_reg_tx_expired_1822), + .O(plm_fsm_pa_counter3_un1_enable_1_i_1820) + ); + FDCE plm_fsm_pa_counter3_reg_tx_count_11_ ( + .CE(plm_fsm_pa_counter3_N_61007_i_1821), + .C(mgt_clk), + .D(plm_fsm_pa_counter3_reg_tx_count_s[11]), + .Q(plm_fsm_pa_counter3_reg_tx_count[11]), + .CLR(plm_rst) + ); + FDCE plm_fsm_pa_counter3_reg_tx_count_10_ ( + .CE(plm_fsm_pa_counter3_N_61007_i_1821), + .C(mgt_clk), + .D(plm_fsm_pa_counter3_reg_tx_count_s[10]), + .Q(plm_fsm_pa_counter3_reg_tx_count[10]), + .CLR(plm_rst) + ); + FDCE plm_fsm_pa_counter3_reg_tx_count_9_ ( + .CE(plm_fsm_pa_counter3_N_61007_i_1821), + .C(mgt_clk), + .D(plm_fsm_pa_counter3_reg_tx_count_s[9]), + .Q(plm_fsm_pa_counter3_reg_tx_count[9]), + .CLR(plm_rst) + ); + FDCE plm_fsm_pa_counter3_reg_tx_count_8_ ( + .CE(plm_fsm_pa_counter3_N_61007_i_1821), + .C(mgt_clk), + .D(plm_fsm_pa_counter3_reg_tx_count_s[8]), + .Q(plm_fsm_pa_counter3_reg_tx_count[8]), + .CLR(plm_rst) + ); + FDCE plm_fsm_pa_counter3_reg_tx_count_7_ ( + .CE(plm_fsm_pa_counter3_N_61007_i_1821), + .C(mgt_clk), + .D(plm_fsm_pa_counter3_reg_tx_count_s[7]), + .Q(plm_fsm_pa_counter3_reg_tx_count[7]), + .CLR(plm_rst) + ); + FDCE plm_fsm_pa_counter3_reg_tx_count_6_ ( + .CE(plm_fsm_pa_counter3_N_61007_i_1821), + .C(mgt_clk), + .D(plm_fsm_pa_counter3_reg_tx_count_s[6]), + .Q(plm_fsm_pa_counter3_reg_tx_count[6]), + .CLR(plm_rst) + ); + FDCE plm_fsm_pa_counter3_reg_tx_count_5_ ( + .CE(plm_fsm_pa_counter3_N_61007_i_1821), + .C(mgt_clk), + .D(plm_fsm_pa_counter3_reg_tx_count_s[5]), + .Q(plm_fsm_pa_counter3_reg_tx_count[5]), + .CLR(plm_rst) + ); + FDCE plm_fsm_pa_counter3_reg_tx_count_4_ ( + .CE(plm_fsm_pa_counter3_N_61007_i_1821), + .C(mgt_clk), + .D(plm_fsm_pa_counter3_reg_tx_count_s[4]), + .Q(plm_fsm_pa_counter3_reg_tx_count[4]), + .CLR(plm_rst) + ); + FDCE plm_fsm_pa_counter3_reg_tx_count_3_ ( + .CE(plm_fsm_pa_counter3_N_61007_i_1821), + .C(mgt_clk), + .D(plm_fsm_pa_counter3_reg_tx_count_s[3]), + .Q(plm_fsm_pa_counter3_reg_tx_count[3]), + .CLR(plm_rst) + ); + FDCE plm_fsm_pa_counter3_reg_tx_count_2_ ( + .CE(plm_fsm_pa_counter3_N_61007_i_1821), + .C(mgt_clk), + .D(plm_fsm_pa_counter3_reg_tx_count_s[2]), + .Q(plm_fsm_pa_counter3_reg_tx_count[2]), + .CLR(plm_rst) + ); + FDCE plm_fsm_pa_counter3_reg_tx_count_1_ ( + .CE(plm_fsm_pa_counter3_N_61007_i_1821), + .C(mgt_clk), + .D(plm_fsm_pa_counter3_reg_tx_count_s[1]), + .Q(plm_fsm_pa_counter3_reg_tx_count[1]), + .CLR(plm_rst) + ); + FDCE plm_fsm_pa_counter3_reg_tx_count_0_ ( + .CE(plm_fsm_pa_counter3_N_61007_i_1821), + .C(mgt_clk), + .D(plm_fsm_pa_counter3_reg_tx_count_s[0]), + .Q(plm_fsm_pa_counter3_reg_tx_count[0]), + .CLR(plm_rst) + ); + FDCE plm_fsm_pa_counter3_reg_rx_count_7_ ( + .CE(plm_fsm_pa_counter3_un1_reg_rx_expired_1_i), + .C(mgt_clk), + .D(plm_fsm_pa_counter3_reg_rx_count_s[7]), + .Q(plm_fsm_pa_counter3_reg_rx_count[7]), + .CLR(plm_rst) + ); + FDCE plm_fsm_pa_counter3_reg_rx_count_6_ ( + .CE(plm_fsm_pa_counter3_un1_reg_rx_expired_1_i), + .C(mgt_clk), + .D(plm_fsm_pa_counter3_reg_rx_count_s[6]), + .Q(plm_fsm_pa_counter3_reg_rx_count[6]), + .CLR(plm_rst) + ); + FDCE plm_fsm_pa_counter3_reg_rx_count_5_ ( + .CE(plm_fsm_pa_counter3_un1_reg_rx_expired_1_i), + .C(mgt_clk), + .D(plm_fsm_pa_counter3_reg_rx_count_s[5]), + .Q(plm_fsm_pa_counter3_reg_rx_count[5]), + .CLR(plm_rst) + ); + FDCE plm_fsm_pa_counter3_reg_rx_count_4_ ( + .CE(plm_fsm_pa_counter3_un1_reg_rx_expired_1_i), + .C(mgt_clk), + .D(plm_fsm_pa_counter3_reg_rx_count_s[4]), + .Q(plm_fsm_pa_counter3_reg_rx_count[4]), + .CLR(plm_rst) + ); + FDCE plm_fsm_pa_counter3_reg_rx_count_3_ ( + .CE(plm_fsm_pa_counter3_un1_reg_rx_expired_1_i), + .C(mgt_clk), + .D(plm_fsm_pa_counter3_reg_rx_count_s[3]), + .Q(plm_fsm_pa_counter3_reg_rx_count[3]), + .CLR(plm_rst) + ); + FDCE plm_fsm_pa_counter3_reg_rx_count_2_ ( + .CE(plm_fsm_pa_counter3_un1_reg_rx_expired_1_i), + .C(mgt_clk), + .D(plm_fsm_pa_counter3_reg_rx_count_s[2]), + .Q(plm_fsm_pa_counter3_reg_rx_count[2]), + .CLR(plm_rst) + ); + FDCE plm_fsm_pa_counter3_reg_rx_count_1_ ( + .CE(plm_fsm_pa_counter3_un1_reg_rx_expired_1_i), + .C(mgt_clk), + .D(plm_fsm_pa_counter3_reg_rx_count_s[1]), + .Q(plm_fsm_pa_counter3_reg_rx_count[1]), + .CLR(plm_rst) + ); + FDCE plm_fsm_pa_counter3_reg_rx_count_0_ ( + .CE(plm_fsm_pa_counter3_un1_reg_rx_expired_1_i), + .C(mgt_clk), + .D(plm_fsm_pa_counter3_reg_rx_count_s[0]), + .Q(plm_fsm_pa_counter3_reg_rx_count[0]), + .CLR(plm_rst) + ); + FDC plm_fsm_pa_counter3_reg_expired ( + .C(mgt_clk), + .D(plm_fsm_pa_counter3_reg_expired_5), + .Q(plm_fsm_pa_cntrout3), + .CLR(plm_rst) + ); + FDCE plm_fsm_pa_counter3_reg_tx_expired ( + .CE(plm_fsm_pa_counter3_N_60986_i), + .C(mgt_clk), + .D(plm_fsm_reg_state_1__425), + .Q(plm_fsm_pa_counter3_reg_tx_expired_1822), + .CLR(plm_rst) + ); + FDCE plm_fsm_pa_counter3_reg_rx_expired ( + .CE(plm_fsm_pa_counter3_N_60985_i), + .C(mgt_clk), + .D(plm_fsm_reg_state_1__425), + .Q(plm_fsm_pa_counter3_reg_rx_expired_82), + .CLR(plm_rst) + ); + defparam plm_fsm_pa_counter3_reg_rx_count_qxu_0_0_.INIT = 4'h7; + LUT2_L plm_fsm_pa_counter3_reg_rx_count_qxu_0_0_ ( + .I0(N_22668_i), + .I1(plm_fsm_pa_counter3_reg_rx_count[0]), + .LO(plm_fsm_pa_counter3_reg_rx_count_qxu[0]) + ); + defparam plm_fsm_pa_counter3_reg_rx_count_qxu_0_1_.INIT = 4'h7; + LUT2_L plm_fsm_pa_counter3_reg_rx_count_qxu_0_1_ ( + .I0(N_22668_i), + .I1(plm_fsm_pa_counter3_reg_rx_count[1]), + .LO(plm_fsm_pa_counter3_reg_rx_count_qxu[1]) + ); + defparam plm_fsm_pa_counter3_reg_rx_count_qxu_0_2_.INIT = 4'h7; + LUT2_L plm_fsm_pa_counter3_reg_rx_count_qxu_0_2_ ( + .I0(N_22668_i), + .I1(plm_fsm_pa_counter3_reg_rx_count[2]), + .LO(plm_fsm_pa_counter3_reg_rx_count_qxu[2]) + ); + defparam plm_fsm_pa_counter3_reg_rx_count_qxu_0_3_.INIT = 8'h1B; + LUT3_L plm_fsm_pa_counter3_reg_rx_count_qxu_0_3_ ( + .I0(N_22668_i), + .I1(plm_fsm_pa_counter3_N_28849_i), + .I2(plm_fsm_pa_counter3_reg_rx_count[3]), + .LO(plm_fsm_pa_counter3_reg_rx_count_qxu[3]) + ); + defparam plm_fsm_pa_counter3_reg_rx_count_qxu_0_4_.INIT = 4'h7; + LUT2_L plm_fsm_pa_counter3_reg_rx_count_qxu_0_4_ ( + .I0(N_22668_i), + .I1(plm_fsm_pa_counter3_reg_rx_count[4]), + .LO(plm_fsm_pa_counter3_reg_rx_count_qxu[4]) + ); + defparam plm_fsm_pa_counter3_reg_rx_count_qxu_0_5_.INIT = 4'h7; + LUT2_L plm_fsm_pa_counter3_reg_rx_count_qxu_0_5_ ( + .I0(N_22668_i), + .I1(plm_fsm_pa_counter3_reg_rx_count[5]), + .LO(plm_fsm_pa_counter3_reg_rx_count_qxu[5]) + ); + defparam plm_fsm_pa_counter3_reg_rx_count_qxu_0_6_.INIT = 4'h7; + LUT2_L plm_fsm_pa_counter3_reg_rx_count_qxu_0_6_ ( + .I0(N_22668_i), + .I1(plm_fsm_pa_counter3_reg_rx_count[6]), + .LO(plm_fsm_pa_counter3_reg_rx_count_qxu[6]) + ); + defparam plm_fsm_pa_counter3_reg_rx_count_qxu_0_7_.INIT = 4'h7; + LUT2_L plm_fsm_pa_counter3_reg_rx_count_qxu_0_7_ ( + .I0(N_22668_i), + .I1(plm_fsm_pa_counter3_reg_rx_count[7]), + .LO(plm_fsm_pa_counter3_reg_rx_count_qxu[7]) + ); + defparam plm_fsm_pa_counter3_reg_tx_count_qxu_0_0_.INIT = 4'h7; + LUT2_L plm_fsm_pa_counter3_reg_tx_count_qxu_0_0_ ( + .I0(plm_fsm_pa_counter3_reg_tx_count[0]), + .I1(plm_fsm_pa_counter3_un1_enable_1), + .LO(plm_fsm_pa_counter3_reg_tx_count_qxu[0]) + ); + defparam plm_fsm_pa_counter3_reg_tx_count_qxu_0_1_.INIT = 4'h7; + LUT2_L plm_fsm_pa_counter3_reg_tx_count_qxu_0_1_ ( + .I0(plm_fsm_pa_counter3_reg_tx_count[1]), + .I1(plm_fsm_pa_counter3_un1_enable_1), + .LO(plm_fsm_pa_counter3_reg_tx_count_qxu[1]) + ); + defparam plm_fsm_pa_counter3_reg_tx_count_qxu_0_2_.INIT = 4'h7; + LUT2_L plm_fsm_pa_counter3_reg_tx_count_qxu_0_2_ ( + .I0(plm_fsm_pa_counter3_reg_tx_count[2]), + .I1(plm_fsm_pa_counter3_un1_enable_1), + .LO(plm_fsm_pa_counter3_reg_tx_count_qxu[2]) + ); + defparam plm_fsm_pa_counter3_reg_tx_count_qxu_0_3_.INIT = 4'h7; + LUT2_L plm_fsm_pa_counter3_reg_tx_count_qxu_0_3_ ( + .I0(plm_fsm_pa_counter3_reg_tx_count[3]), + .I1(plm_fsm_pa_counter3_un1_enable_1), + .LO(plm_fsm_pa_counter3_reg_tx_count_qxu[3]) + ); + defparam plm_fsm_pa_counter3_reg_tx_count_qxu_0_4_.INIT = 8'h35; + LUT3_L plm_fsm_pa_counter3_reg_tx_count_qxu_0_4_ ( + .I0(plm_fsm_reg_tx_count_6_4_), + .I1(plm_fsm_pa_counter3_reg_tx_count[4]), + .I2(plm_fsm_pa_counter3_un1_enable_1), + .LO(plm_fsm_pa_counter3_reg_tx_count_qxu[4]) + ); + defparam plm_fsm_pa_counter3_reg_tx_count_qxu_0_5_.INIT = 4'h7; + LUT2_L plm_fsm_pa_counter3_reg_tx_count_qxu_0_5_ ( + .I0(plm_fsm_pa_counter3_reg_tx_count[5]), + .I1(plm_fsm_pa_counter3_un1_enable_1), + .LO(plm_fsm_pa_counter3_reg_tx_count_qxu[5]) + ); + defparam plm_fsm_pa_counter3_reg_tx_count_qxu_0_6_.INIT = 4'h7; + LUT2_L plm_fsm_pa_counter3_reg_tx_count_qxu_0_6_ ( + .I0(plm_fsm_pa_counter3_reg_tx_count[6]), + .I1(plm_fsm_pa_counter3_un1_enable_1), + .LO(plm_fsm_pa_counter3_reg_tx_count_qxu[6]) + ); + defparam plm_fsm_pa_counter3_reg_tx_count_qxu_0_7_.INIT = 4'h7; + LUT2_L plm_fsm_pa_counter3_reg_tx_count_qxu_0_7_ ( + .I0(plm_fsm_pa_counter3_reg_tx_count[7]), + .I1(plm_fsm_pa_counter3_un1_enable_1), + .LO(plm_fsm_pa_counter3_reg_tx_count_qxu[7]) + ); + defparam plm_fsm_pa_counter3_reg_tx_count_qxu_0_8_.INIT = 4'h7; + LUT2_L plm_fsm_pa_counter3_reg_tx_count_qxu_0_8_ ( + .I0(plm_fsm_pa_counter3_reg_tx_count[8]), + .I1(plm_fsm_pa_counter3_un1_enable_1), + .LO(plm_fsm_pa_counter3_reg_tx_count_qxu[8]) + ); + defparam plm_fsm_pa_counter3_reg_tx_count_qxu_0_9_.INIT = 4'h7; + LUT2_L plm_fsm_pa_counter3_reg_tx_count_qxu_0_9_ ( + .I0(plm_fsm_pa_counter3_reg_tx_count[9]), + .I1(plm_fsm_pa_counter3_un1_enable_1), + .LO(plm_fsm_pa_counter3_reg_tx_count_qxu[9]) + ); + defparam plm_fsm_pa_counter3_reg_tx_count_qxu_0_10_.INIT = 8'h35; + LUT3_L plm_fsm_pa_counter3_reg_tx_count_qxu_0_10_ ( + .I0(plm_fsm_reg_tx_count_6_10_), + .I1(plm_fsm_pa_counter3_reg_tx_count[10]), + .I2(plm_fsm_pa_counter3_un1_enable_1), + .LO(plm_fsm_pa_counter3_reg_tx_count_qxu[10]) + ); + defparam plm_fsm_pa_counter3_reg_tx_count_qxu_0_11_.INIT = 4'h7; + LUT2_L plm_fsm_pa_counter3_reg_tx_count_qxu_0_11_ ( + .I0(plm_fsm_pa_counter3_reg_tx_count[11]), + .I1(plm_fsm_pa_counter3_un1_enable_1), + .LO(plm_fsm_pa_counter3_reg_tx_count_qxu[11]) + ); + GND plm_fsm_pc_timer_GND ( + .G(plm_fsm_pc_timer_GND_1823) + ); + MUXCY_L plm_fsm_pc_timer_reg_count_cry_0_ ( + .CI(plm_fsm_reg_state_2__599), + .DI(plm_fsm_pc_timer_GND_1823), + .LO(plm_fsm_pc_timer_reg_count_cry[0]), + .S(plm_fsm_pc_timer_reg_count_qxu[0]) + ); + XORCY plm_fsm_pc_timer_reg_count_s_0_ ( + .CI(plm_fsm_reg_state_2__599), + .LI(plm_fsm_pc_timer_reg_count_qxu[0]), + .O(plm_fsm_pc_timer_reg_count_s[0]) + ); + MUXCY_L plm_fsm_pc_timer_reg_count_cry_1_ ( + .CI(plm_fsm_pc_timer_reg_count_cry[0]), + .DI(plm_fsm_pc_timer_GND_1823), + .LO(plm_fsm_pc_timer_reg_count_cry[1]), + .S(plm_fsm_pc_timer_reg_count_qxu[1]) + ); + XORCY plm_fsm_pc_timer_reg_count_s_1_ ( + .CI(plm_fsm_pc_timer_reg_count_cry[0]), + .LI(plm_fsm_pc_timer_reg_count_qxu[1]), + .O(plm_fsm_pc_timer_reg_count_s[1]) + ); + MUXCY_L plm_fsm_pc_timer_reg_count_cry_2_ ( + .CI(plm_fsm_pc_timer_reg_count_cry[1]), + .DI(plm_fsm_pc_timer_GND_1823), + .LO(plm_fsm_pc_timer_reg_count_cry[2]), + .S(plm_fsm_pc_timer_reg_count_qxu[2]) + ); + XORCY plm_fsm_pc_timer_reg_count_s_2_ ( + .CI(plm_fsm_pc_timer_reg_count_cry[1]), + .LI(plm_fsm_pc_timer_reg_count_qxu[2]), + .O(plm_fsm_pc_timer_reg_count_s[2]) + ); + MUXCY_L plm_fsm_pc_timer_reg_count_cry_3_ ( + .CI(plm_fsm_pc_timer_reg_count_cry[2]), + .DI(plm_fsm_pc_timer_GND_1823), + .LO(plm_fsm_pc_timer_reg_count_cry[3]), + .S(plm_fsm_pc_timer_reg_count_qxu[3]) + ); + XORCY plm_fsm_pc_timer_reg_count_s_3_ ( + .CI(plm_fsm_pc_timer_reg_count_cry[2]), + .LI(plm_fsm_pc_timer_reg_count_qxu[3]), + .O(plm_fsm_pc_timer_reg_count_s[3]) + ); + MUXCY_L plm_fsm_pc_timer_reg_count_cry_4_ ( + .CI(plm_fsm_pc_timer_reg_count_cry[3]), + .DI(plm_fsm_pc_timer_GND_1823), + .LO(plm_fsm_pc_timer_reg_count_cry[4]), + .S(plm_fsm_pc_timer_reg_count_qxu[4]) + ); + XORCY plm_fsm_pc_timer_reg_count_s_4_ ( + .CI(plm_fsm_pc_timer_reg_count_cry[3]), + .LI(plm_fsm_pc_timer_reg_count_qxu[4]), + .O(plm_fsm_pc_timer_reg_count_s[4]) + ); + MUXCY_L plm_fsm_pc_timer_reg_count_cry_5_ ( + .CI(plm_fsm_pc_timer_reg_count_cry[4]), + .DI(plm_fsm_pc_timer_GND_1823), + .LO(plm_fsm_pc_timer_reg_count_cry[5]), + .S(plm_fsm_pc_timer_reg_count_qxu[5]) + ); + XORCY plm_fsm_pc_timer_reg_count_s_5_ ( + .CI(plm_fsm_pc_timer_reg_count_cry[4]), + .LI(plm_fsm_pc_timer_reg_count_qxu[5]), + .O(plm_fsm_pc_timer_reg_count_s[5]) + ); + MUXCY_L plm_fsm_pc_timer_reg_count_cry_6_ ( + .CI(plm_fsm_pc_timer_reg_count_cry[5]), + .DI(plm_fsm_pc_timer_GND_1823), + .LO(plm_fsm_pc_timer_reg_count_cry[6]), + .S(plm_fsm_pc_timer_reg_count_qxu[6]) + ); + XORCY plm_fsm_pc_timer_reg_count_s_6_ ( + .CI(plm_fsm_pc_timer_reg_count_cry[5]), + .LI(plm_fsm_pc_timer_reg_count_qxu[6]), + .O(plm_fsm_pc_timer_reg_count_s[6]) + ); + MUXCY_L plm_fsm_pc_timer_reg_count_cry_7_ ( + .CI(plm_fsm_pc_timer_reg_count_cry[6]), + .DI(plm_fsm_pc_timer_GND_1823), + .LO(plm_fsm_pc_timer_reg_count_cry[7]), + .S(plm_fsm_pc_timer_reg_count_qxu[7]) + ); + XORCY plm_fsm_pc_timer_reg_count_s_7_ ( + .CI(plm_fsm_pc_timer_reg_count_cry[6]), + .LI(plm_fsm_pc_timer_reg_count_qxu[7]), + .O(plm_fsm_pc_timer_reg_count_s[7]) + ); + MUXCY_L plm_fsm_pc_timer_reg_count_cry_8_ ( + .CI(plm_fsm_pc_timer_reg_count_cry[7]), + .DI(plm_fsm_pc_timer_GND_1823), + .LO(plm_fsm_pc_timer_reg_count_cry[8]), + .S(plm_fsm_pc_timer_reg_count_qxu[8]) + ); + XORCY plm_fsm_pc_timer_reg_count_s_8_ ( + .CI(plm_fsm_pc_timer_reg_count_cry[7]), + .LI(plm_fsm_pc_timer_reg_count_qxu[8]), + .O(plm_fsm_pc_timer_reg_count_s[8]) + ); + MUXCY_L plm_fsm_pc_timer_reg_count_cry_9_ ( + .CI(plm_fsm_pc_timer_reg_count_cry[8]), + .DI(plm_fsm_pc_timer_GND_1823), + .LO(plm_fsm_pc_timer_reg_count_cry[9]), + .S(plm_fsm_pc_timer_reg_count_qxu[9]) + ); + XORCY plm_fsm_pc_timer_reg_count_s_9_ ( + .CI(plm_fsm_pc_timer_reg_count_cry[8]), + .LI(plm_fsm_pc_timer_reg_count_qxu[9]), + .O(plm_fsm_pc_timer_reg_count_s[9]) + ); + MUXCY_L plm_fsm_pc_timer_reg_count_cry_10_ ( + .CI(plm_fsm_pc_timer_reg_count_cry[9]), + .DI(plm_fsm_pc_timer_GND_1823), + .LO(plm_fsm_pc_timer_reg_count_cry[10]), + .S(plm_fsm_pc_timer_reg_count_qxu[10]) + ); + XORCY plm_fsm_pc_timer_reg_count_s_10_ ( + .CI(plm_fsm_pc_timer_reg_count_cry[9]), + .LI(plm_fsm_pc_timer_reg_count_qxu[10]), + .O(plm_fsm_pc_timer_reg_count_s[10]) + ); + MUXCY_L plm_fsm_pc_timer_reg_count_cry_11_ ( + .CI(plm_fsm_pc_timer_reg_count_cry[10]), + .DI(plm_fsm_pc_timer_GND_1823), + .LO(plm_fsm_pc_timer_reg_count_cry[11]), + .S(plm_fsm_pc_timer_reg_count_qxu[11]) + ); + XORCY plm_fsm_pc_timer_reg_count_s_11_ ( + .CI(plm_fsm_pc_timer_reg_count_cry[10]), + .LI(plm_fsm_pc_timer_reg_count_qxu[11]), + .O(plm_fsm_pc_timer_reg_count_s[11]) + ); + MUXCY_L plm_fsm_pc_timer_reg_count_cry_12_ ( + .CI(plm_fsm_pc_timer_reg_count_cry[11]), + .DI(plm_fsm_pc_timer_GND_1823), + .LO(plm_fsm_pc_timer_reg_count_cry[12]), + .S(plm_fsm_pc_timer_reg_count_qxu[12]) + ); + XORCY plm_fsm_pc_timer_reg_count_s_12_ ( + .CI(plm_fsm_pc_timer_reg_count_cry[11]), + .LI(plm_fsm_pc_timer_reg_count_qxu[12]), + .O(plm_fsm_pc_timer_reg_count_s[12]) + ); + MUXCY_L plm_fsm_pc_timer_reg_count_cry_13_ ( + .CI(plm_fsm_pc_timer_reg_count_cry[12]), + .DI(plm_fsm_pc_timer_GND_1823), + .LO(plm_fsm_pc_timer_reg_count_cry[13]), + .S(plm_fsm_pc_timer_reg_count_qxu[13]) + ); + XORCY plm_fsm_pc_timer_reg_count_s_13_ ( + .CI(plm_fsm_pc_timer_reg_count_cry[12]), + .LI(plm_fsm_pc_timer_reg_count_qxu[13]), + .O(plm_fsm_pc_timer_reg_count_s[13]) + ); + MUXCY_L plm_fsm_pc_timer_reg_count_cry_14_ ( + .CI(plm_fsm_pc_timer_reg_count_cry[13]), + .DI(plm_fsm_pc_timer_GND_1823), + .LO(plm_fsm_pc_timer_reg_count_cry[14]), + .S(plm_fsm_pc_timer_reg_count_qxu[14]) + ); + XORCY plm_fsm_pc_timer_reg_count_s_14_ ( + .CI(plm_fsm_pc_timer_reg_count_cry[13]), + .LI(plm_fsm_pc_timer_reg_count_qxu[14]), + .O(plm_fsm_pc_timer_reg_count_s[14]) + ); + MUXCY_L plm_fsm_pc_timer_reg_count_cry_15_ ( + .CI(plm_fsm_pc_timer_reg_count_cry[14]), + .DI(plm_fsm_pc_timer_GND_1823), + .LO(plm_fsm_pc_timer_reg_count_cry[15]), + .S(plm_fsm_pc_timer_reg_count_qxu[15]) + ); + XORCY plm_fsm_pc_timer_reg_count_s_15_ ( + .CI(plm_fsm_pc_timer_reg_count_cry[14]), + .LI(plm_fsm_pc_timer_reg_count_qxu[15]), + .O(plm_fsm_pc_timer_reg_count_s[15]) + ); + MUXCY_L plm_fsm_pc_timer_reg_count_cry_16_ ( + .CI(plm_fsm_pc_timer_reg_count_cry[15]), + .DI(plm_fsm_pc_timer_GND_1823), + .LO(plm_fsm_pc_timer_reg_count_cry[16]), + .S(plm_fsm_pc_timer_reg_count_qxu[16]) + ); + XORCY plm_fsm_pc_timer_reg_count_s_16_ ( + .CI(plm_fsm_pc_timer_reg_count_cry[15]), + .LI(plm_fsm_pc_timer_reg_count_qxu[16]), + .O(plm_fsm_pc_timer_reg_count_s[16]) + ); + MUXCY_L plm_fsm_pc_timer_reg_count_cry_17_ ( + .CI(plm_fsm_pc_timer_reg_count_cry[16]), + .DI(plm_fsm_pc_timer_GND_1823), + .LO(plm_fsm_pc_timer_reg_count_cry[17]), + .S(plm_fsm_pc_timer_reg_count_qxu[17]) + ); + XORCY plm_fsm_pc_timer_reg_count_s_17_ ( + .CI(plm_fsm_pc_timer_reg_count_cry[16]), + .LI(plm_fsm_pc_timer_reg_count_qxu[17]), + .O(plm_fsm_pc_timer_reg_count_s[17]) + ); + MUXCY_L plm_fsm_pc_timer_reg_count_cry_18_ ( + .CI(plm_fsm_pc_timer_reg_count_cry[17]), + .DI(plm_fsm_pc_timer_GND_1823), + .LO(plm_fsm_pc_timer_reg_count_cry[18]), + .S(plm_fsm_pc_timer_reg_count_qxu[18]) + ); + XORCY plm_fsm_pc_timer_reg_count_s_18_ ( + .CI(plm_fsm_pc_timer_reg_count_cry[17]), + .LI(plm_fsm_pc_timer_reg_count_qxu[18]), + .O(plm_fsm_pc_timer_reg_count_s[18]) + ); + MUXCY_L plm_fsm_pc_timer_reg_count_cry_19_ ( + .CI(plm_fsm_pc_timer_reg_count_cry[18]), + .DI(plm_fsm_pc_timer_GND_1823), + .LO(plm_fsm_pc_timer_reg_count_cry[19]), + .S(plm_fsm_pc_timer_reg_count_qxu[19]) + ); + XORCY plm_fsm_pc_timer_reg_count_s_19_ ( + .CI(plm_fsm_pc_timer_reg_count_cry[18]), + .LI(plm_fsm_pc_timer_reg_count_qxu[19]), + .O(plm_fsm_pc_timer_reg_count_s[19]) + ); + MUXCY_L plm_fsm_pc_timer_reg_count_cry_20_ ( + .CI(plm_fsm_pc_timer_reg_count_cry[19]), + .DI(plm_fsm_pc_timer_GND_1823), + .LO(plm_fsm_pc_timer_reg_count_cry[20]), + .S(plm_fsm_pc_timer_reg_count_qxu[20]) + ); + XORCY plm_fsm_pc_timer_reg_count_s_20_ ( + .CI(plm_fsm_pc_timer_reg_count_cry[19]), + .LI(plm_fsm_pc_timer_reg_count_qxu[20]), + .O(plm_fsm_pc_timer_reg_count_s[20]) + ); + MUXCY_L plm_fsm_pc_timer_reg_count_cry_21_ ( + .CI(plm_fsm_pc_timer_reg_count_cry[20]), + .DI(plm_fsm_pc_timer_GND_1823), + .LO(plm_fsm_pc_timer_reg_count_cry[21]), + .S(plm_fsm_pc_timer_reg_count_qxu[21]) + ); + XORCY plm_fsm_pc_timer_reg_count_s_21_ ( + .CI(plm_fsm_pc_timer_reg_count_cry[20]), + .LI(plm_fsm_pc_timer_reg_count_qxu[21]), + .O(plm_fsm_pc_timer_reg_count_s[21]) + ); + XORCY plm_fsm_pc_timer_reg_count_s_22_ ( + .CI(plm_fsm_pc_timer_reg_count_cry[21]), + .LI(plm_fsm_pc_timer_reg_count_qxu[22]), + .O(plm_fsm_pc_timer_reg_count_s[22]) + ); + defparam plm_fsm_pc_timer_count_i_m3_i_m3_0_21_.INIT = 8'hD8; + LUT3_L plm_fsm_pc_timer_count_i_m3_i_m3_0_21_ ( + .I0(cfg_cfg_6102[507]), + .I1(plm_fsm_pc_timer_reg_count[13]), + .I2(plm_fsm_pc_timer_reg_count[21]), + .LO(plm_fsm_pc_timer_N_63721) + ); + defparam plm_fsm_pc_timer_expired_1.INIT = 16'hA280; + LUT4 plm_fsm_pc_timer_expired_1 ( + .I0(plm_fsm_pc_timer_N_63721), + .I1(cfg_cfg_6102[507]), + .I2(plm_fsm_pc_timer_reg_count[14]), + .I3(plm_fsm_pc_timer_reg_count[22]), + .O(plm_fsm_pc_timeout_1) + ); + FDC plm_fsm_pc_timer_reg_count_22_ ( + .C(mgt_clk), + .D(plm_fsm_pc_timer_reg_count_s[22]), + .Q(plm_fsm_pc_timer_reg_count[22]), + .CLR(plm_rst) + ); + FDC plm_fsm_pc_timer_reg_count_21_ ( + .C(mgt_clk), + .D(plm_fsm_pc_timer_reg_count_s[21]), + .Q(plm_fsm_pc_timer_reg_count[21]), + .CLR(plm_rst) + ); + FDC plm_fsm_pc_timer_reg_count_20_ ( + .C(mgt_clk), + .D(plm_fsm_pc_timer_reg_count_s[20]), + .Q(plm_fsm_pc_timer_reg_count[20]), + .CLR(plm_rst) + ); + FDC plm_fsm_pc_timer_reg_count_19_ ( + .C(mgt_clk), + .D(plm_fsm_pc_timer_reg_count_s[19]), + .Q(plm_fsm_pc_timer_reg_count[19]), + .CLR(plm_rst) + ); + FDC plm_fsm_pc_timer_reg_count_18_ ( + .C(mgt_clk), + .D(plm_fsm_pc_timer_reg_count_s[18]), + .Q(plm_fsm_pc_timer_reg_count[18]), + .CLR(plm_rst) + ); + FDC plm_fsm_pc_timer_reg_count_17_ ( + .C(mgt_clk), + .D(plm_fsm_pc_timer_reg_count_s[17]), + .Q(plm_fsm_pc_timer_reg_count[17]), + .CLR(plm_rst) + ); + FDC plm_fsm_pc_timer_reg_count_16_ ( + .C(mgt_clk), + .D(plm_fsm_pc_timer_reg_count_s[16]), + .Q(plm_fsm_pc_timer_reg_count[16]), + .CLR(plm_rst) + ); + FDC plm_fsm_pc_timer_reg_count_15_ ( + .C(mgt_clk), + .D(plm_fsm_pc_timer_reg_count_s[15]), + .Q(plm_fsm_pc_timer_reg_count[15]), + .CLR(plm_rst) + ); + FDC plm_fsm_pc_timer_reg_count_14_ ( + .C(mgt_clk), + .D(plm_fsm_pc_timer_reg_count_s[14]), + .Q(plm_fsm_pc_timer_reg_count[14]), + .CLR(plm_rst) + ); + FDC plm_fsm_pc_timer_reg_count_13_ ( + .C(mgt_clk), + .D(plm_fsm_pc_timer_reg_count_s[13]), + .Q(plm_fsm_pc_timer_reg_count[13]), + .CLR(plm_rst) + ); + FDC plm_fsm_pc_timer_reg_count_12_ ( + .C(mgt_clk), + .D(plm_fsm_pc_timer_reg_count_s[12]), + .Q(plm_fsm_pc_timer_reg_count[12]), + .CLR(plm_rst) + ); + FDC plm_fsm_pc_timer_reg_count_11_ ( + .C(mgt_clk), + .D(plm_fsm_pc_timer_reg_count_s[11]), + .Q(plm_fsm_pc_timer_reg_count[11]), + .CLR(plm_rst) + ); + FDC plm_fsm_pc_timer_reg_count_10_ ( + .C(mgt_clk), + .D(plm_fsm_pc_timer_reg_count_s[10]), + .Q(plm_fsm_pc_timer_reg_count[10]), + .CLR(plm_rst) + ); + FDC plm_fsm_pc_timer_reg_count_9_ ( + .C(mgt_clk), + .D(plm_fsm_pc_timer_reg_count_s[9]), + .Q(plm_fsm_pc_timer_reg_count[9]), + .CLR(plm_rst) + ); + FDC plm_fsm_pc_timer_reg_count_8_ ( + .C(mgt_clk), + .D(plm_fsm_pc_timer_reg_count_s[8]), + .Q(plm_fsm_pc_timer_reg_count[8]), + .CLR(plm_rst) + ); + FDC plm_fsm_pc_timer_reg_count_7_ ( + .C(mgt_clk), + .D(plm_fsm_pc_timer_reg_count_s[7]), + .Q(plm_fsm_pc_timer_reg_count[7]), + .CLR(plm_rst) + ); + FDC plm_fsm_pc_timer_reg_count_6_ ( + .C(mgt_clk), + .D(plm_fsm_pc_timer_reg_count_s[6]), + .Q(plm_fsm_pc_timer_reg_count[6]), + .CLR(plm_rst) + ); + FDC plm_fsm_pc_timer_reg_count_5_ ( + .C(mgt_clk), + .D(plm_fsm_pc_timer_reg_count_s[5]), + .Q(plm_fsm_pc_timer_reg_count[5]), + .CLR(plm_rst) + ); + FDC plm_fsm_pc_timer_reg_count_4_ ( + .C(mgt_clk), + .D(plm_fsm_pc_timer_reg_count_s[4]), + .Q(plm_fsm_pc_timer_reg_count[4]), + .CLR(plm_rst) + ); + FDC plm_fsm_pc_timer_reg_count_3_ ( + .C(mgt_clk), + .D(plm_fsm_pc_timer_reg_count_s[3]), + .Q(plm_fsm_pc_timer_reg_count[3]), + .CLR(plm_rst) + ); + FDC plm_fsm_pc_timer_reg_count_2_ ( + .C(mgt_clk), + .D(plm_fsm_pc_timer_reg_count_s[2]), + .Q(plm_fsm_pc_timer_reg_count[2]), + .CLR(plm_rst) + ); + FDC plm_fsm_pc_timer_reg_count_1_ ( + .C(mgt_clk), + .D(plm_fsm_pc_timer_reg_count_s[1]), + .Q(plm_fsm_pc_timer_reg_count[1]), + .CLR(plm_rst) + ); + FDC plm_fsm_pc_timer_reg_count_0_ ( + .C(mgt_clk), + .D(plm_fsm_pc_timer_reg_count_s[0]), + .Q(plm_fsm_pc_timer_reg_count[0]), + .CLR(plm_rst) + ); + defparam plm_fsm_pc_timer_reg_count_qxu_0_0_.INIT = 4'h8; + LUT2_L plm_fsm_pc_timer_reg_count_qxu_0_0_ ( + .I0(plm_fsm_pc_timer_reg_count[0]), + .I1(plm_fsm_reg_state_2__599), + .LO(plm_fsm_pc_timer_reg_count_qxu[0]) + ); + defparam plm_fsm_pc_timer_reg_count_qxu_0_1_.INIT = 4'h8; + LUT2_L plm_fsm_pc_timer_reg_count_qxu_0_1_ ( + .I0(plm_fsm_pc_timer_reg_count[1]), + .I1(plm_fsm_reg_state_2__599), + .LO(plm_fsm_pc_timer_reg_count_qxu[1]) + ); + defparam plm_fsm_pc_timer_reg_count_qxu_0_2_.INIT = 4'h8; + LUT2_L plm_fsm_pc_timer_reg_count_qxu_0_2_ ( + .I0(plm_fsm_pc_timer_reg_count[2]), + .I1(plm_fsm_reg_state_2__599), + .LO(plm_fsm_pc_timer_reg_count_qxu[2]) + ); + defparam plm_fsm_pc_timer_reg_count_qxu_0_3_.INIT = 4'h8; + LUT2_L plm_fsm_pc_timer_reg_count_qxu_0_3_ ( + .I0(plm_fsm_pc_timer_reg_count[3]), + .I1(plm_fsm_reg_state_2__599), + .LO(plm_fsm_pc_timer_reg_count_qxu[3]) + ); + defparam plm_fsm_pc_timer_reg_count_qxu_0_4_.INIT = 4'h8; + LUT2_L plm_fsm_pc_timer_reg_count_qxu_0_4_ ( + .I0(plm_fsm_pc_timer_reg_count[4]), + .I1(plm_fsm_reg_state_2__599), + .LO(plm_fsm_pc_timer_reg_count_qxu[4]) + ); + defparam plm_fsm_pc_timer_reg_count_qxu_0_5_.INIT = 4'h8; + LUT2_L plm_fsm_pc_timer_reg_count_qxu_0_5_ ( + .I0(plm_fsm_pc_timer_reg_count[5]), + .I1(plm_fsm_reg_state_2__599), + .LO(plm_fsm_pc_timer_reg_count_qxu[5]) + ); + defparam plm_fsm_pc_timer_reg_count_qxu_0_6_.INIT = 4'h8; + LUT2_L plm_fsm_pc_timer_reg_count_qxu_0_6_ ( + .I0(plm_fsm_pc_timer_reg_count[6]), + .I1(plm_fsm_reg_state_2__599), + .LO(plm_fsm_pc_timer_reg_count_qxu[6]) + ); + defparam plm_fsm_pc_timer_reg_count_qxu_0_7_.INIT = 4'h8; + LUT2_L plm_fsm_pc_timer_reg_count_qxu_0_7_ ( + .I0(plm_fsm_pc_timer_reg_count[7]), + .I1(plm_fsm_reg_state_2__599), + .LO(plm_fsm_pc_timer_reg_count_qxu[7]) + ); + defparam plm_fsm_pc_timer_reg_count_qxu_0_8_.INIT = 4'h8; + LUT2_L plm_fsm_pc_timer_reg_count_qxu_0_8_ ( + .I0(plm_fsm_pc_timer_reg_count[8]), + .I1(plm_fsm_reg_state_2__599), + .LO(plm_fsm_pc_timer_reg_count_qxu[8]) + ); + defparam plm_fsm_pc_timer_reg_count_qxu_0_9_.INIT = 4'h8; + LUT2_L plm_fsm_pc_timer_reg_count_qxu_0_9_ ( + .I0(plm_fsm_pc_timer_reg_count[9]), + .I1(plm_fsm_reg_state_2__599), + .LO(plm_fsm_pc_timer_reg_count_qxu[9]) + ); + defparam plm_fsm_pc_timer_reg_count_qxu_0_10_.INIT = 4'h8; + LUT2_L plm_fsm_pc_timer_reg_count_qxu_0_10_ ( + .I0(plm_fsm_pc_timer_reg_count[10]), + .I1(plm_fsm_reg_state_2__599), + .LO(plm_fsm_pc_timer_reg_count_qxu[10]) + ); + defparam plm_fsm_pc_timer_reg_count_qxu_0_11_.INIT = 4'h8; + LUT2_L plm_fsm_pc_timer_reg_count_qxu_0_11_ ( + .I0(plm_fsm_pc_timer_reg_count[11]), + .I1(plm_fsm_reg_state_2__599), + .LO(plm_fsm_pc_timer_reg_count_qxu[11]) + ); + defparam plm_fsm_pc_timer_reg_count_qxu_0_12_.INIT = 4'h8; + LUT2_L plm_fsm_pc_timer_reg_count_qxu_0_12_ ( + .I0(plm_fsm_pc_timer_reg_count[12]), + .I1(plm_fsm_reg_state_2__599), + .LO(plm_fsm_pc_timer_reg_count_qxu[12]) + ); + defparam plm_fsm_pc_timer_reg_count_qxu_0_13_.INIT = 4'h8; + LUT2_L plm_fsm_pc_timer_reg_count_qxu_0_13_ ( + .I0(plm_fsm_pc_timer_reg_count[13]), + .I1(plm_fsm_reg_state_2__599), + .LO(plm_fsm_pc_timer_reg_count_qxu[13]) + ); + defparam plm_fsm_pc_timer_reg_count_qxu_0_14_.INIT = 4'h8; + LUT2_L plm_fsm_pc_timer_reg_count_qxu_0_14_ ( + .I0(plm_fsm_pc_timer_reg_count[14]), + .I1(plm_fsm_reg_state_2__599), + .LO(plm_fsm_pc_timer_reg_count_qxu[14]) + ); + defparam plm_fsm_pc_timer_reg_count_qxu_0_15_.INIT = 4'h8; + LUT2_L plm_fsm_pc_timer_reg_count_qxu_0_15_ ( + .I0(plm_fsm_pc_timer_reg_count[15]), + .I1(plm_fsm_reg_state_2__599), + .LO(plm_fsm_pc_timer_reg_count_qxu[15]) + ); + defparam plm_fsm_pc_timer_reg_count_qxu_0_16_.INIT = 4'h8; + LUT2_L plm_fsm_pc_timer_reg_count_qxu_0_16_ ( + .I0(plm_fsm_pc_timer_reg_count[16]), + .I1(plm_fsm_reg_state_2__599), + .LO(plm_fsm_pc_timer_reg_count_qxu[16]) + ); + defparam plm_fsm_pc_timer_reg_count_qxu_0_17_.INIT = 4'h8; + LUT2_L plm_fsm_pc_timer_reg_count_qxu_0_17_ ( + .I0(plm_fsm_pc_timer_reg_count[17]), + .I1(plm_fsm_reg_state_2__599), + .LO(plm_fsm_pc_timer_reg_count_qxu[17]) + ); + defparam plm_fsm_pc_timer_reg_count_qxu_0_18_.INIT = 4'h8; + LUT2_L plm_fsm_pc_timer_reg_count_qxu_0_18_ ( + .I0(plm_fsm_pc_timer_reg_count[18]), + .I1(plm_fsm_reg_state_2__599), + .LO(plm_fsm_pc_timer_reg_count_qxu[18]) + ); + defparam plm_fsm_pc_timer_reg_count_qxu_0_19_.INIT = 4'h8; + LUT2_L plm_fsm_pc_timer_reg_count_qxu_0_19_ ( + .I0(plm_fsm_pc_timer_reg_count[19]), + .I1(plm_fsm_reg_state_2__599), + .LO(plm_fsm_pc_timer_reg_count_qxu[19]) + ); + defparam plm_fsm_pc_timer_reg_count_qxu_0_20_.INIT = 4'h8; + LUT2_L plm_fsm_pc_timer_reg_count_qxu_0_20_ ( + .I0(plm_fsm_pc_timer_reg_count[20]), + .I1(plm_fsm_reg_state_2__599), + .LO(plm_fsm_pc_timer_reg_count_qxu[20]) + ); + defparam plm_fsm_pc_timer_reg_count_qxu_0_21_.INIT = 4'h8; + LUT2_L plm_fsm_pc_timer_reg_count_qxu_0_21_ ( + .I0(plm_fsm_pc_timer_reg_count[21]), + .I1(plm_fsm_reg_state_2__599), + .LO(plm_fsm_pc_timer_reg_count_qxu[21]) + ); + defparam plm_fsm_pc_timer_reg_count_qxu_0_22_.INIT = 4'h8; + LUT2_L plm_fsm_pc_timer_reg_count_qxu_0_22_ ( + .I0(plm_fsm_pc_timer_reg_count[22]), + .I1(plm_fsm_reg_state_2__599), + .LO(plm_fsm_pc_timer_reg_count_qxu[22]) + ); + VCC plm_fsm_pc_counter0_VCC ( + .P(plm_fsm_pc_counter0_VCC_1824) + ); + MUXCY_L plm_fsm_pc_counter0_reg_rx_count_cry_0_ ( + .CI(N_60997_i_31), + .DI(plm_fsm_pc_counter0_VCC_1824), + .LO(plm_fsm_pc_counter0_reg_rx_count_cry[0]), + .S(plm_fsm_pc_counter0_reg_rx_count_qxu[0]) + ); + XORCY plm_fsm_pc_counter0_reg_rx_count_s_0_ ( + .CI(N_60997_i_31), + .LI(plm_fsm_pc_counter0_reg_rx_count_qxu[0]), + .O(plm_fsm_pc_counter0_reg_rx_count_s[0]) + ); + MUXCY_L plm_fsm_pc_counter0_reg_rx_count_cry_1_ ( + .CI(plm_fsm_pc_counter0_reg_rx_count_cry[0]), + .DI(plm_fsm_pc_counter0_VCC_1824), + .LO(plm_fsm_pc_counter0_reg_rx_count_cry[1]), + .S(plm_fsm_pc_counter0_reg_rx_count_qxu[1]) + ); + XORCY plm_fsm_pc_counter0_reg_rx_count_s_1_ ( + .CI(plm_fsm_pc_counter0_reg_rx_count_cry[0]), + .LI(plm_fsm_pc_counter0_reg_rx_count_qxu[1]), + .O(plm_fsm_pc_counter0_reg_rx_count_s[1]) + ); + MUXCY_L plm_fsm_pc_counter0_reg_rx_count_cry_2_ ( + .CI(plm_fsm_pc_counter0_reg_rx_count_cry[1]), + .DI(plm_fsm_pc_counter0_VCC_1824), + .LO(plm_fsm_pc_counter0_reg_rx_count_cry[2]), + .S(plm_fsm_pc_counter0_reg_rx_count_qxu[2]) + ); + XORCY plm_fsm_pc_counter0_reg_rx_count_s_2_ ( + .CI(plm_fsm_pc_counter0_reg_rx_count_cry[1]), + .LI(plm_fsm_pc_counter0_reg_rx_count_qxu[2]), + .O(plm_fsm_pc_counter0_reg_rx_count_s[2]) + ); + MUXCY_L plm_fsm_pc_counter0_reg_rx_count_cry_3_ ( + .CI(plm_fsm_pc_counter0_reg_rx_count_cry[2]), + .DI(plm_fsm_pc_counter0_VCC_1824), + .LO(plm_fsm_pc_counter0_reg_rx_count_cry[3]), + .S(plm_fsm_pc_counter0_reg_rx_count_qxu[3]) + ); + XORCY plm_fsm_pc_counter0_reg_rx_count_s_3_ ( + .CI(plm_fsm_pc_counter0_reg_rx_count_cry[2]), + .LI(plm_fsm_pc_counter0_reg_rx_count_qxu[3]), + .O(plm_fsm_pc_counter0_reg_rx_count_s[3]) + ); + MUXCY_L plm_fsm_pc_counter0_reg_rx_count_cry_4_ ( + .CI(plm_fsm_pc_counter0_reg_rx_count_cry[3]), + .DI(plm_fsm_pc_counter0_VCC_1824), + .LO(plm_fsm_pc_counter0_reg_rx_count_cry[4]), + .S(plm_fsm_pc_counter0_reg_rx_count_qxu[4]) + ); + XORCY plm_fsm_pc_counter0_reg_rx_count_s_4_ ( + .CI(plm_fsm_pc_counter0_reg_rx_count_cry[3]), + .LI(plm_fsm_pc_counter0_reg_rx_count_qxu[4]), + .O(plm_fsm_pc_counter0_reg_rx_count_s[4]) + ); + MUXCY_L plm_fsm_pc_counter0_reg_rx_count_cry_5_ ( + .CI(plm_fsm_pc_counter0_reg_rx_count_cry[4]), + .DI(plm_fsm_pc_counter0_VCC_1824), + .LO(plm_fsm_pc_counter0_reg_rx_count_cry[5]), + .S(plm_fsm_pc_counter0_reg_rx_count_qxu[5]) + ); + XORCY plm_fsm_pc_counter0_reg_rx_count_s_5_ ( + .CI(plm_fsm_pc_counter0_reg_rx_count_cry[4]), + .LI(plm_fsm_pc_counter0_reg_rx_count_qxu[5]), + .O(plm_fsm_pc_counter0_reg_rx_count_s[5]) + ); + MUXCY_L plm_fsm_pc_counter0_reg_rx_count_cry_6_ ( + .CI(plm_fsm_pc_counter0_reg_rx_count_cry[5]), + .DI(plm_fsm_pc_counter0_VCC_1824), + .LO(plm_fsm_pc_counter0_reg_rx_count_cry[6]), + .S(plm_fsm_pc_counter0_reg_rx_count_qxu[6]) + ); + XORCY plm_fsm_pc_counter0_reg_rx_count_s_6_ ( + .CI(plm_fsm_pc_counter0_reg_rx_count_cry[5]), + .LI(plm_fsm_pc_counter0_reg_rx_count_qxu[6]), + .O(plm_fsm_pc_counter0_reg_rx_count_s[6]) + ); + XORCY plm_fsm_pc_counter0_reg_rx_count_s_7_ ( + .CI(plm_fsm_pc_counter0_reg_rx_count_cry[6]), + .LI(plm_fsm_pc_counter0_reg_rx_count_qxu[7]), + .O(plm_fsm_pc_counter0_reg_rx_count_s[7]) + ); + MUXCY_L plm_fsm_pc_counter0_reg_tx_count_cry_0_ ( + .CI(plm_fsm_pc_counter0_un1_enable_1_i_1825), + .DI(plm_fsm_pc_counter0_VCC_1824), + .LO(plm_fsm_pc_counter0_reg_tx_count_cry[0]), + .S(plm_fsm_pc_counter0_reg_tx_count_qxu[0]) + ); + XORCY plm_fsm_pc_counter0_reg_tx_count_s_0_ ( + .CI(plm_fsm_pc_counter0_un1_enable_1_i_1825), + .LI(plm_fsm_pc_counter0_reg_tx_count_qxu[0]), + .O(plm_fsm_pc_counter0_reg_tx_count_s[0]) + ); + MUXCY_L plm_fsm_pc_counter0_reg_tx_count_cry_1_ ( + .CI(plm_fsm_pc_counter0_reg_tx_count_cry[0]), + .DI(plm_fsm_pc_counter0_VCC_1824), + .LO(plm_fsm_pc_counter0_reg_tx_count_cry[1]), + .S(plm_fsm_pc_counter0_reg_tx_count_qxu[1]) + ); + XORCY plm_fsm_pc_counter0_reg_tx_count_s_1_ ( + .CI(plm_fsm_pc_counter0_reg_tx_count_cry[0]), + .LI(plm_fsm_pc_counter0_reg_tx_count_qxu[1]), + .O(plm_fsm_pc_counter0_reg_tx_count_s[1]) + ); + MUXCY_L plm_fsm_pc_counter0_reg_tx_count_cry_2_ ( + .CI(plm_fsm_pc_counter0_reg_tx_count_cry[1]), + .DI(plm_fsm_pc_counter0_VCC_1824), + .LO(plm_fsm_pc_counter0_reg_tx_count_cry[2]), + .S(plm_fsm_pc_counter0_reg_tx_count_qxu[2]) + ); + XORCY plm_fsm_pc_counter0_reg_tx_count_s_2_ ( + .CI(plm_fsm_pc_counter0_reg_tx_count_cry[1]), + .LI(plm_fsm_pc_counter0_reg_tx_count_qxu[2]), + .O(plm_fsm_pc_counter0_reg_tx_count_s[2]) + ); + MUXCY_L plm_fsm_pc_counter0_reg_tx_count_cry_3_ ( + .CI(plm_fsm_pc_counter0_reg_tx_count_cry[2]), + .DI(plm_fsm_pc_counter0_VCC_1824), + .LO(plm_fsm_pc_counter0_reg_tx_count_cry[3]), + .S(plm_fsm_pc_counter0_reg_tx_count_qxu[3]) + ); + XORCY plm_fsm_pc_counter0_reg_tx_count_s_3_ ( + .CI(plm_fsm_pc_counter0_reg_tx_count_cry[2]), + .LI(plm_fsm_pc_counter0_reg_tx_count_qxu[3]), + .O(plm_fsm_pc_counter0_reg_tx_count_s[3]) + ); + MUXCY_L plm_fsm_pc_counter0_reg_tx_count_cry_4_ ( + .CI(plm_fsm_pc_counter0_reg_tx_count_cry[3]), + .DI(plm_fsm_pc_counter0_VCC_1824), + .LO(plm_fsm_pc_counter0_reg_tx_count_cry[4]), + .S(plm_fsm_pc_counter0_reg_tx_count_qxu[4]) + ); + XORCY plm_fsm_pc_counter0_reg_tx_count_s_4_ ( + .CI(plm_fsm_pc_counter0_reg_tx_count_cry[3]), + .LI(plm_fsm_pc_counter0_reg_tx_count_qxu[4]), + .O(plm_fsm_pc_counter0_reg_tx_count_s[4]) + ); + MUXCY_L plm_fsm_pc_counter0_reg_tx_count_cry_5_ ( + .CI(plm_fsm_pc_counter0_reg_tx_count_cry[4]), + .DI(plm_fsm_pc_counter0_VCC_1824), + .LO(plm_fsm_pc_counter0_reg_tx_count_cry[5]), + .S(plm_fsm_pc_counter0_reg_tx_count_qxu[5]) + ); + XORCY plm_fsm_pc_counter0_reg_tx_count_s_5_ ( + .CI(plm_fsm_pc_counter0_reg_tx_count_cry[4]), + .LI(plm_fsm_pc_counter0_reg_tx_count_qxu[5]), + .O(plm_fsm_pc_counter0_reg_tx_count_s[5]) + ); + MUXCY_L plm_fsm_pc_counter0_reg_tx_count_cry_6_ ( + .CI(plm_fsm_pc_counter0_reg_tx_count_cry[5]), + .DI(plm_fsm_pc_counter0_VCC_1824), + .LO(plm_fsm_pc_counter0_reg_tx_count_cry[6]), + .S(plm_fsm_pc_counter0_reg_tx_count_qxu[6]) + ); + XORCY plm_fsm_pc_counter0_reg_tx_count_s_6_ ( + .CI(plm_fsm_pc_counter0_reg_tx_count_cry[5]), + .LI(plm_fsm_pc_counter0_reg_tx_count_qxu[6]), + .O(plm_fsm_pc_counter0_reg_tx_count_s[6]) + ); + XORCY plm_fsm_pc_counter0_reg_tx_count_s_7_ ( + .CI(plm_fsm_pc_counter0_reg_tx_count_cry[6]), + .LI(plm_fsm_pc_counter0_reg_tx_count_qxu[7]), + .O(plm_fsm_pc_counter0_reg_tx_count_s[7]) + ); + defparam plm_fsm_pc_counter0_loadable_tx_counter_reg_tx_count17_0_a2_0_a3_0_a2_0_a3_0_a2.INIT = 4'h8; + LUT2 plm_fsm_pc_counter0_loadable_tx_counter_reg_tx_count17_0_a2_0_a3_0_a2_0_a3_0_a2 ( + .I0(plm_fsm_pc_counter0_reg_oneshot_1827), + .I1(plm_fsm_reg_state_2__599), + .O(plm_fsm_pc_counter0_un1_reg_tx_count17) + ); + defparam plm_fsm_pc_counter0_oneshot_monitor_un1_enable_0_a2_0_a2_0_a3_0_a2.INIT = 4'h4; + LUT2 plm_fsm_pc_counter0_oneshot_monitor_un1_enable_0_a2_0_a2_0_a3_0_a2 ( + .I0(plm_reg_ts2_1), + .I1(plm_fsm_reg_state_2__599), + .O(plm_fsm_pc_counter0_un1_enable_0_a2_0_a2_0_a3_0_a2_6) + ); + defparam plm_fsm_pc_counter0_loadable_tx_counter_un1_reg_tx_count_0_a2_0_a3_4.INIT = 16'h0001; + LUT4 plm_fsm_pc_counter0_loadable_tx_counter_un1_reg_tx_count_0_a2_0_a3_4 ( + .I0(plm_fsm_pc_counter0_reg_tx_count[0]), + .I1(plm_fsm_pc_counter0_reg_tx_count[1]), + .I2(plm_fsm_pc_counter0_reg_tx_count[2]), + .I3(plm_fsm_pc_counter0_reg_tx_count[3]), + .O(plm_fsm_pc_counter0_un1_reg_tx_count_0_a2_0_a3_4) + ); + defparam plm_fsm_pc_counter0_loadable_tx_counter_un1_reg_tx_count_0_a2_0_a3_5.INIT = 16'h0001; + LUT4 plm_fsm_pc_counter0_loadable_tx_counter_un1_reg_tx_count_0_a2_0_a3_5 ( + .I0(plm_fsm_pc_counter0_reg_tx_count[4]), + .I1(plm_fsm_pc_counter0_reg_tx_count[5]), + .I2(plm_fsm_pc_counter0_reg_tx_count[6]), + .I3(plm_fsm_pc_counter0_reg_tx_count[7]), + .O(plm_fsm_pc_counter0_un1_reg_tx_count_0_a2_0_a3_5) + ); + defparam plm_fsm_pc_counter0_loadable_rx_counter_un1_reg_rx_count_0_a2_4.INIT = 16'h0001; + LUT4 plm_fsm_pc_counter0_loadable_rx_counter_un1_reg_rx_count_0_a2_4 ( + .I0(plm_fsm_pc_counter0_reg_rx_count[0]), + .I1(plm_fsm_pc_counter0_reg_rx_count[1]), + .I2(plm_fsm_pc_counter0_reg_rx_count[2]), + .I3(plm_fsm_pc_counter0_reg_rx_count[3]), + .O(plm_fsm_pc_counter0_un1_reg_rx_count_0_a2_4) + ); + defparam plm_fsm_pc_counter0_loadable_rx_counter_un1_reg_rx_count_0_a2_5.INIT = 16'h0001; + LUT4 plm_fsm_pc_counter0_loadable_rx_counter_un1_reg_rx_count_0_a2_5 ( + .I0(plm_fsm_pc_counter0_reg_rx_count[4]), + .I1(plm_fsm_pc_counter0_reg_rx_count[5]), + .I2(plm_fsm_pc_counter0_reg_rx_count[6]), + .I3(plm_fsm_pc_counter0_reg_rx_count[7]), + .O(plm_fsm_pc_counter0_un1_reg_rx_count_0_a2_5) + ); + defparam plm_fsm_pc_counter0_loadable_rx_counter_un1_rx_ts1_i.INIT = 4'hD; + LUT2 plm_fsm_pc_counter0_loadable_rx_counter_un1_rx_ts1_i ( + .I0(plm_fsm_pc_counter0_un1_enable_0_a2_0_a2_0_a3_0_a2_6), + .I1(plm_fsm_pc_counter0_reg_rx_expired_600), + .O(plm_fsm_pc_counter0_un1_rx_ts1_i) + ); + defparam plm_fsm_pc_counter0_N_87190_i.INIT = 16'h0F2F; + LUT4 plm_fsm_pc_counter0_N_87190_i ( + .I0(plm_reg_ts2_1), + .I1(plm_fsm_pc_counter0_reg_rx_expired_600), + .I2(plm_fsm_reg_state_2__599), + .I3(plm_rx0_ts2_c), + .O(plm_fsm_pc_counter0_N_87190_i_1830) + ); + defparam plm_fsm_pc_counter0_N_61023_i.INIT = 4'hB; + LUT2 plm_fsm_pc_counter0_N_61023_i ( + .I0(plm_reg_sym_sent_6_), + .I1(plm_fsm_pc_counter0_un1_enable_1), + .O(plm_fsm_pc_counter0_N_61023_i_1826) + ); + defparam plm_fsm_pc_counter0_un1_enable_2_i.INIT = 8'h8F; + LUT3 plm_fsm_pc_counter0_un1_enable_2_i ( + .I0(plm_fsm_pc_counter0_un1_reg_tx_count_0_a2_0_a3_4), + .I1(plm_fsm_pc_counter0_un1_reg_tx_count_0_a2_0_a3_5), + .I2(plm_fsm_pc_counter0_un1_reg_tx_count17), + .O(plm_fsm_pc_counter0_un1_enable_2_i_1828) + ); + defparam plm_fsm_pc_counter0_loadable_rx_counter_N_61034_i.INIT = 8'h8F; + LUT3 plm_fsm_pc_counter0_loadable_rx_counter_N_61034_i ( + .I0(plm_fsm_pc_counter0_un1_reg_rx_count_0_a2_4), + .I1(plm_fsm_pc_counter0_un1_reg_rx_count_0_a2_5), + .I2(plm_fsm_reg_state_2__599), + .O(plm_fsm_pc_counter0_N_61034_i) + ); + defparam plm_fsm_pc_counter0_flagit_reg_expired_5_0_a2_0_a2_0_a3_0_a2.INIT = 8'h80; + LUT3_L plm_fsm_pc_counter0_flagit_reg_expired_5_0_a2_0_a2_0_a3_0_a2 ( + .I0(plm_fsm_pc_counter0_reg_rx_expired_600), + .I1(plm_fsm_pc_counter0_reg_tx_expired_1829), + .I2(plm_fsm_reg_state_2__599), + .LO(plm_fsm_pc_counter0_reg_expired_5) + ); + defparam plm_fsm_pc_counter0_un1_enable_1_0_a3_0_a2_0_a3_0_a2.INIT = 8'h40; + LUT3 plm_fsm_pc_counter0_un1_enable_1_0_a3_0_a2_0_a3_0_a2 ( + .I0(plm_fsm_pc_counter0_reg_tx_expired_1829), + .I1(plm_fsm_reg_state_2__599), + .I2(plm_fsm_pc_counter0_reg_oneshot_1827), + .O(plm_fsm_pc_counter0_un1_enable_1) + ); + defparam plm_fsm_pc_counter0_un1_enable_1_i.INIT = 8'hF7; + LUT3 plm_fsm_pc_counter0_un1_enable_1_i ( + .I0(plm_fsm_pc_counter0_reg_oneshot_1827), + .I1(plm_fsm_reg_state_2__599), + .I2(plm_fsm_pc_counter0_reg_tx_expired_1829), + .O(plm_fsm_pc_counter0_un1_enable_1_i_1825) + ); + FDCE plm_fsm_pc_counter0_reg_tx_count_7_ ( + .CE(plm_fsm_pc_counter0_N_61023_i_1826), + .C(mgt_clk), + .D(plm_fsm_pc_counter0_reg_tx_count_s[7]), + .Q(plm_fsm_pc_counter0_reg_tx_count[7]), + .CLR(plm_rst) + ); + FDCE plm_fsm_pc_counter0_reg_tx_count_6_ ( + .CE(plm_fsm_pc_counter0_N_61023_i_1826), + .C(mgt_clk), + .D(plm_fsm_pc_counter0_reg_tx_count_s[6]), + .Q(plm_fsm_pc_counter0_reg_tx_count[6]), + .CLR(plm_rst) + ); + FDCE plm_fsm_pc_counter0_reg_tx_count_5_ ( + .CE(plm_fsm_pc_counter0_N_61023_i_1826), + .C(mgt_clk), + .D(plm_fsm_pc_counter0_reg_tx_count_s[5]), + .Q(plm_fsm_pc_counter0_reg_tx_count[5]), + .CLR(plm_rst) + ); + FDPE plm_fsm_pc_counter0_reg_tx_count_4_ ( + .PRE(plm_rst), + .CE(plm_fsm_pc_counter0_N_61023_i_1826), + .C(mgt_clk), + .D(plm_fsm_pc_counter0_reg_tx_count_s[4]), + .Q(plm_fsm_pc_counter0_reg_tx_count[4]) + ); + FDCE plm_fsm_pc_counter0_reg_tx_count_3_ ( + .CE(plm_fsm_pc_counter0_N_61023_i_1826), + .C(mgt_clk), + .D(plm_fsm_pc_counter0_reg_tx_count_s[3]), + .Q(plm_fsm_pc_counter0_reg_tx_count[3]), + .CLR(plm_rst) + ); + FDCE plm_fsm_pc_counter0_reg_tx_count_2_ ( + .CE(plm_fsm_pc_counter0_N_61023_i_1826), + .C(mgt_clk), + .D(plm_fsm_pc_counter0_reg_tx_count_s[2]), + .Q(plm_fsm_pc_counter0_reg_tx_count[2]), + .CLR(plm_rst) + ); + FDCE plm_fsm_pc_counter0_reg_tx_count_1_ ( + .CE(plm_fsm_pc_counter0_N_61023_i_1826), + .C(mgt_clk), + .D(plm_fsm_pc_counter0_reg_tx_count_s[1]), + .Q(plm_fsm_pc_counter0_reg_tx_count[1]), + .CLR(plm_rst) + ); + FDCE plm_fsm_pc_counter0_reg_tx_count_0_ ( + .CE(plm_fsm_pc_counter0_N_61023_i_1826), + .C(mgt_clk), + .D(plm_fsm_pc_counter0_reg_tx_count_s[0]), + .Q(plm_fsm_pc_counter0_reg_tx_count[0]), + .CLR(plm_rst) + ); + FDCE plm_fsm_pc_counter0_reg_rx_count_7_ ( + .CE(plm_fsm_pc_counter0_un1_rx_ts1_i), + .C(mgt_clk), + .D(plm_fsm_pc_counter0_reg_rx_count_s[7]), + .Q(plm_fsm_pc_counter0_reg_rx_count[7]), + .CLR(plm_rst) + ); + FDCE plm_fsm_pc_counter0_reg_rx_count_6_ ( + .CE(plm_fsm_pc_counter0_un1_rx_ts1_i), + .C(mgt_clk), + .D(plm_fsm_pc_counter0_reg_rx_count_s[6]), + .Q(plm_fsm_pc_counter0_reg_rx_count[6]), + .CLR(plm_rst) + ); + FDCE plm_fsm_pc_counter0_reg_rx_count_5_ ( + .CE(plm_fsm_pc_counter0_un1_rx_ts1_i), + .C(mgt_clk), + .D(plm_fsm_pc_counter0_reg_rx_count_s[5]), + .Q(plm_fsm_pc_counter0_reg_rx_count[5]), + .CLR(plm_rst) + ); + FDCE plm_fsm_pc_counter0_reg_rx_count_4_ ( + .CE(plm_fsm_pc_counter0_un1_rx_ts1_i), + .C(mgt_clk), + .D(plm_fsm_pc_counter0_reg_rx_count_s[4]), + .Q(plm_fsm_pc_counter0_reg_rx_count[4]), + .CLR(plm_rst) + ); + FDPE plm_fsm_pc_counter0_reg_rx_count_3_ ( + .PRE(plm_rst), + .CE(plm_fsm_pc_counter0_un1_rx_ts1_i), + .C(mgt_clk), + .D(plm_fsm_pc_counter0_reg_rx_count_s[3]), + .Q(plm_fsm_pc_counter0_reg_rx_count[3]) + ); + FDCE plm_fsm_pc_counter0_reg_rx_count_2_ ( + .CE(plm_fsm_pc_counter0_un1_rx_ts1_i), + .C(mgt_clk), + .D(plm_fsm_pc_counter0_reg_rx_count_s[2]), + .Q(plm_fsm_pc_counter0_reg_rx_count[2]), + .CLR(plm_rst) + ); + FDCE plm_fsm_pc_counter0_reg_rx_count_1_ ( + .CE(plm_fsm_pc_counter0_un1_rx_ts1_i), + .C(mgt_clk), + .D(plm_fsm_pc_counter0_reg_rx_count_s[1]), + .Q(plm_fsm_pc_counter0_reg_rx_count[1]), + .CLR(plm_rst) + ); + FDCE plm_fsm_pc_counter0_reg_rx_count_0_ ( + .CE(plm_fsm_pc_counter0_un1_rx_ts1_i), + .C(mgt_clk), + .D(plm_fsm_pc_counter0_reg_rx_count_s[0]), + .Q(plm_fsm_pc_counter0_reg_rx_count[0]), + .CLR(plm_rst) + ); + FDC plm_fsm_pc_counter0_reg_expired ( + .C(mgt_clk), + .D(plm_fsm_pc_counter0_reg_expired_5), + .Q(plm_fsm_pc_cntrout0), + .CLR(plm_rst) + ); + FDCE plm_fsm_pc_counter0_reg_oneshot ( + .CE(plm_fsm_pc_counter0_N_61035_i), + .C(mgt_clk), + .D(plm_fsm_reg_state_2__599), + .Q(plm_fsm_pc_counter0_reg_oneshot_1827), + .CLR(plm_rst) + ); + FDCE plm_fsm_pc_counter0_reg_rx_expired ( + .CE(plm_fsm_pc_counter0_N_61034_i), + .C(mgt_clk), + .D(plm_fsm_reg_state_2__599), + .Q(plm_fsm_pc_counter0_reg_rx_expired_600), + .CLR(plm_rst) + ); + FDCE plm_fsm_pc_counter0_reg_tx_expired ( + .CE(plm_fsm_pc_counter0_un1_enable_2_i_1828), + .C(mgt_clk), + .D(plm_fsm_pc_counter0_un1_reg_tx_count17), + .Q(plm_fsm_pc_counter0_reg_tx_expired_1829), + .CLR(plm_rst) + ); + INV plm_fsm_pc_counter0_oneshot_monitor_N_61035_i ( + .I(plm_fsm_pc_counter0_un1_enable_0_a2_0_a2_0_a3_0_a2_6), + .O(plm_fsm_pc_counter0_N_61035_i) + ); + defparam plm_fsm_pc_counter0_reg_rx_count_qxu_0_0_.INIT = 4'h7; + LUT2_L plm_fsm_pc_counter0_reg_rx_count_qxu_0_0_ ( + .I0(I_5033_0_a2_0_a2_0_a3_0_a2_30), + .I1(plm_fsm_pc_counter0_reg_rx_count[0]), + .LO(plm_fsm_pc_counter0_reg_rx_count_qxu[0]) + ); + defparam plm_fsm_pc_counter0_reg_rx_count_qxu_0_1_.INIT = 4'h7; + LUT2_L plm_fsm_pc_counter0_reg_rx_count_qxu_0_1_ ( + .I0(I_5033_0_a2_0_a2_0_a3_0_a2_30), + .I1(plm_fsm_pc_counter0_reg_rx_count[1]), + .LO(plm_fsm_pc_counter0_reg_rx_count_qxu[1]) + ); + defparam plm_fsm_pc_counter0_reg_rx_count_qxu_0_2_.INIT = 4'h7; + LUT2_L plm_fsm_pc_counter0_reg_rx_count_qxu_0_2_ ( + .I0(I_5033_0_a2_0_a2_0_a3_0_a2_30), + .I1(plm_fsm_pc_counter0_reg_rx_count[2]), + .LO(plm_fsm_pc_counter0_reg_rx_count_qxu[2]) + ); + defparam plm_fsm_pc_counter0_reg_rx_count_qxu_0_3_.INIT = 8'h1B; + LUT3_L plm_fsm_pc_counter0_reg_rx_count_qxu_0_3_ ( + .I0(I_5033_0_a2_0_a2_0_a3_0_a2_30), + .I1(plm_fsm_pc_counter0_N_87190_i_1830), + .I2(plm_fsm_pc_counter0_reg_rx_count[3]), + .LO(plm_fsm_pc_counter0_reg_rx_count_qxu[3]) + ); + defparam plm_fsm_pc_counter0_reg_rx_count_qxu_0_4_.INIT = 4'h7; + LUT2_L plm_fsm_pc_counter0_reg_rx_count_qxu_0_4_ ( + .I0(I_5033_0_a2_0_a2_0_a3_0_a2_30), + .I1(plm_fsm_pc_counter0_reg_rx_count[4]), + .LO(plm_fsm_pc_counter0_reg_rx_count_qxu[4]) + ); + defparam plm_fsm_pc_counter0_reg_rx_count_qxu_0_5_.INIT = 4'h7; + LUT2_L plm_fsm_pc_counter0_reg_rx_count_qxu_0_5_ ( + .I0(I_5033_0_a2_0_a2_0_a3_0_a2_30), + .I1(plm_fsm_pc_counter0_reg_rx_count[5]), + .LO(plm_fsm_pc_counter0_reg_rx_count_qxu[5]) + ); + defparam plm_fsm_pc_counter0_reg_rx_count_qxu_0_6_.INIT = 4'h7; + LUT2_L plm_fsm_pc_counter0_reg_rx_count_qxu_0_6_ ( + .I0(I_5033_0_a2_0_a2_0_a3_0_a2_30), + .I1(plm_fsm_pc_counter0_reg_rx_count[6]), + .LO(plm_fsm_pc_counter0_reg_rx_count_qxu[6]) + ); + defparam plm_fsm_pc_counter0_reg_rx_count_qxu_0_7_.INIT = 4'h7; + LUT2_L plm_fsm_pc_counter0_reg_rx_count_qxu_0_7_ ( + .I0(I_5033_0_a2_0_a2_0_a3_0_a2_30), + .I1(plm_fsm_pc_counter0_reg_rx_count[7]), + .LO(plm_fsm_pc_counter0_reg_rx_count_qxu[7]) + ); + defparam plm_fsm_pc_counter0_reg_tx_count_qxu_0_0_.INIT = 4'h7; + LUT2_L plm_fsm_pc_counter0_reg_tx_count_qxu_0_0_ ( + .I0(plm_fsm_pc_counter0_reg_tx_count[0]), + .I1(plm_fsm_pc_counter0_un1_enable_1), + .LO(plm_fsm_pc_counter0_reg_tx_count_qxu[0]) + ); + defparam plm_fsm_pc_counter0_reg_tx_count_qxu_0_1_.INIT = 4'h7; + LUT2_L plm_fsm_pc_counter0_reg_tx_count_qxu_0_1_ ( + .I0(plm_fsm_pc_counter0_reg_tx_count[1]), + .I1(plm_fsm_pc_counter0_un1_enable_1), + .LO(plm_fsm_pc_counter0_reg_tx_count_qxu[1]) + ); + defparam plm_fsm_pc_counter0_reg_tx_count_qxu_0_2_.INIT = 4'h7; + LUT2_L plm_fsm_pc_counter0_reg_tx_count_qxu_0_2_ ( + .I0(plm_fsm_pc_counter0_reg_tx_count[2]), + .I1(plm_fsm_pc_counter0_un1_enable_1), + .LO(plm_fsm_pc_counter0_reg_tx_count_qxu[2]) + ); + defparam plm_fsm_pc_counter0_reg_tx_count_qxu_0_3_.INIT = 4'h7; + LUT2_L plm_fsm_pc_counter0_reg_tx_count_qxu_0_3_ ( + .I0(plm_fsm_pc_counter0_reg_tx_count[3]), + .I1(plm_fsm_pc_counter0_un1_enable_1), + .LO(plm_fsm_pc_counter0_reg_tx_count_qxu[3]) + ); + defparam plm_fsm_pc_counter0_reg_tx_count_qxu_0_4_.INIT = 8'h74; + LUT3_L plm_fsm_pc_counter0_reg_tx_count_qxu_0_4_ ( + .I0(plm_fsm_pc_counter0_reg_tx_count[4]), + .I1(plm_fsm_pc_counter0_un1_enable_1), + .I2(plm_fsm_pc_counter0_un1_reg_tx_count17), + .LO(plm_fsm_pc_counter0_reg_tx_count_qxu[4]) + ); + defparam plm_fsm_pc_counter0_reg_tx_count_qxu_0_5_.INIT = 4'h7; + LUT2_L plm_fsm_pc_counter0_reg_tx_count_qxu_0_5_ ( + .I0(plm_fsm_pc_counter0_reg_tx_count[5]), + .I1(plm_fsm_pc_counter0_un1_enable_1), + .LO(plm_fsm_pc_counter0_reg_tx_count_qxu[5]) + ); + defparam plm_fsm_pc_counter0_reg_tx_count_qxu_0_6_.INIT = 4'h7; + LUT2_L plm_fsm_pc_counter0_reg_tx_count_qxu_0_6_ ( + .I0(plm_fsm_pc_counter0_reg_tx_count[6]), + .I1(plm_fsm_pc_counter0_un1_enable_1), + .LO(plm_fsm_pc_counter0_reg_tx_count_qxu[6]) + ); + defparam plm_fsm_pc_counter0_reg_tx_count_qxu_0_7_.INIT = 4'h7; + LUT2_L plm_fsm_pc_counter0_reg_tx_count_qxu_0_7_ ( + .I0(plm_fsm_pc_counter0_reg_tx_count[7]), + .I1(plm_fsm_pc_counter0_un1_enable_1), + .LO(plm_fsm_pc_counter0_reg_tx_count_qxu[7]) + ); + VCC plm_fsm_pc_counter1_VCC ( + .P(plm_fsm_pc_counter1_VCC_1831) + ); + MUXCY_L plm_fsm_pc_counter1_reg_rx_count_cry_0_ ( + .CI(N_60983_i_33), + .DI(plm_fsm_pc_counter1_VCC_1831), + .LO(plm_fsm_pc_counter1_reg_rx_count_cry[0]), + .S(plm_fsm_pc_counter1_reg_rx_count_qxu[0]) + ); + XORCY plm_fsm_pc_counter1_reg_rx_count_s_0_ ( + .CI(N_60983_i_33), + .LI(plm_fsm_pc_counter1_reg_rx_count_qxu[0]), + .O(plm_fsm_pc_counter1_reg_rx_count_s[0]) + ); + MUXCY_L plm_fsm_pc_counter1_reg_rx_count_cry_1_ ( + .CI(plm_fsm_pc_counter1_reg_rx_count_cry[0]), + .DI(plm_fsm_pc_counter1_VCC_1831), + .LO(plm_fsm_pc_counter1_reg_rx_count_cry[1]), + .S(plm_fsm_pc_counter1_reg_rx_count_qxu[1]) + ); + XORCY plm_fsm_pc_counter1_reg_rx_count_s_1_ ( + .CI(plm_fsm_pc_counter1_reg_rx_count_cry[0]), + .LI(plm_fsm_pc_counter1_reg_rx_count_qxu[1]), + .O(plm_fsm_pc_counter1_reg_rx_count_s[1]) + ); + MUXCY_L plm_fsm_pc_counter1_reg_rx_count_cry_2_ ( + .CI(plm_fsm_pc_counter1_reg_rx_count_cry[1]), + .DI(plm_fsm_pc_counter1_VCC_1831), + .LO(plm_fsm_pc_counter1_reg_rx_count_cry[2]), + .S(plm_fsm_pc_counter1_reg_rx_count_qxu[2]) + ); + XORCY plm_fsm_pc_counter1_reg_rx_count_s_2_ ( + .CI(plm_fsm_pc_counter1_reg_rx_count_cry[1]), + .LI(plm_fsm_pc_counter1_reg_rx_count_qxu[2]), + .O(plm_fsm_pc_counter1_reg_rx_count_s[2]) + ); + MUXCY_L plm_fsm_pc_counter1_reg_rx_count_cry_3_ ( + .CI(plm_fsm_pc_counter1_reg_rx_count_cry[2]), + .DI(plm_fsm_pc_counter1_VCC_1831), + .LO(plm_fsm_pc_counter1_reg_rx_count_cry[3]), + .S(plm_fsm_pc_counter1_reg_rx_count_qxu[3]) + ); + XORCY plm_fsm_pc_counter1_reg_rx_count_s_3_ ( + .CI(plm_fsm_pc_counter1_reg_rx_count_cry[2]), + .LI(plm_fsm_pc_counter1_reg_rx_count_qxu[3]), + .O(plm_fsm_pc_counter1_reg_rx_count_s[3]) + ); + MUXCY_L plm_fsm_pc_counter1_reg_rx_count_cry_4_ ( + .CI(plm_fsm_pc_counter1_reg_rx_count_cry[3]), + .DI(plm_fsm_pc_counter1_VCC_1831), + .LO(plm_fsm_pc_counter1_reg_rx_count_cry[4]), + .S(plm_fsm_pc_counter1_reg_rx_count_qxu[4]) + ); + XORCY plm_fsm_pc_counter1_reg_rx_count_s_4_ ( + .CI(plm_fsm_pc_counter1_reg_rx_count_cry[3]), + .LI(plm_fsm_pc_counter1_reg_rx_count_qxu[4]), + .O(plm_fsm_pc_counter1_reg_rx_count_s[4]) + ); + MUXCY_L plm_fsm_pc_counter1_reg_rx_count_cry_5_ ( + .CI(plm_fsm_pc_counter1_reg_rx_count_cry[4]), + .DI(plm_fsm_pc_counter1_VCC_1831), + .LO(plm_fsm_pc_counter1_reg_rx_count_cry[5]), + .S(plm_fsm_pc_counter1_reg_rx_count_qxu[5]) + ); + XORCY plm_fsm_pc_counter1_reg_rx_count_s_5_ ( + .CI(plm_fsm_pc_counter1_reg_rx_count_cry[4]), + .LI(plm_fsm_pc_counter1_reg_rx_count_qxu[5]), + .O(plm_fsm_pc_counter1_reg_rx_count_s[5]) + ); + MUXCY_L plm_fsm_pc_counter1_reg_rx_count_cry_6_ ( + .CI(plm_fsm_pc_counter1_reg_rx_count_cry[5]), + .DI(plm_fsm_pc_counter1_VCC_1831), + .LO(plm_fsm_pc_counter1_reg_rx_count_cry[6]), + .S(plm_fsm_pc_counter1_reg_rx_count_qxu[6]) + ); + XORCY plm_fsm_pc_counter1_reg_rx_count_s_6_ ( + .CI(plm_fsm_pc_counter1_reg_rx_count_cry[5]), + .LI(plm_fsm_pc_counter1_reg_rx_count_qxu[6]), + .O(plm_fsm_pc_counter1_reg_rx_count_s[6]) + ); + XORCY plm_fsm_pc_counter1_reg_rx_count_s_7_ ( + .CI(plm_fsm_pc_counter1_reg_rx_count_cry[6]), + .LI(plm_fsm_pc_counter1_reg_rx_count_qxu[7]), + .O(plm_fsm_pc_counter1_reg_rx_count_s[7]) + ); + MUXCY_L plm_fsm_pc_counter1_reg_tx_count_cry_0_ ( + .CI(plm_fsm_pc_counter1_un1_enable_1_i_1832), + .DI(plm_fsm_pc_counter1_VCC_1831), + .LO(plm_fsm_pc_counter1_reg_tx_count_cry[0]), + .S(plm_fsm_pc_counter1_reg_tx_count_qxu[0]) + ); + XORCY plm_fsm_pc_counter1_reg_tx_count_s_0_ ( + .CI(plm_fsm_pc_counter1_un1_enable_1_i_1832), + .LI(plm_fsm_pc_counter1_reg_tx_count_qxu[0]), + .O(plm_fsm_pc_counter1_reg_tx_count_s[0]) + ); + MUXCY_L plm_fsm_pc_counter1_reg_tx_count_cry_1_ ( + .CI(plm_fsm_pc_counter1_reg_tx_count_cry[0]), + .DI(plm_fsm_pc_counter1_VCC_1831), + .LO(plm_fsm_pc_counter1_reg_tx_count_cry[1]), + .S(plm_fsm_pc_counter1_reg_tx_count_qxu[1]) + ); + XORCY plm_fsm_pc_counter1_reg_tx_count_s_1_ ( + .CI(plm_fsm_pc_counter1_reg_tx_count_cry[0]), + .LI(plm_fsm_pc_counter1_reg_tx_count_qxu[1]), + .O(plm_fsm_pc_counter1_reg_tx_count_s[1]) + ); + MUXCY_L plm_fsm_pc_counter1_reg_tx_count_cry_2_ ( + .CI(plm_fsm_pc_counter1_reg_tx_count_cry[1]), + .DI(plm_fsm_pc_counter1_VCC_1831), + .LO(plm_fsm_pc_counter1_reg_tx_count_cry[2]), + .S(plm_fsm_pc_counter1_reg_tx_count_qxu[2]) + ); + XORCY plm_fsm_pc_counter1_reg_tx_count_s_2_ ( + .CI(plm_fsm_pc_counter1_reg_tx_count_cry[1]), + .LI(plm_fsm_pc_counter1_reg_tx_count_qxu[2]), + .O(plm_fsm_pc_counter1_reg_tx_count_s[2]) + ); + MUXCY_L plm_fsm_pc_counter1_reg_tx_count_cry_3_ ( + .CI(plm_fsm_pc_counter1_reg_tx_count_cry[2]), + .DI(plm_fsm_pc_counter1_VCC_1831), + .LO(plm_fsm_pc_counter1_reg_tx_count_cry[3]), + .S(plm_fsm_pc_counter1_reg_tx_count_qxu[3]) + ); + XORCY plm_fsm_pc_counter1_reg_tx_count_s_3_ ( + .CI(plm_fsm_pc_counter1_reg_tx_count_cry[2]), + .LI(plm_fsm_pc_counter1_reg_tx_count_qxu[3]), + .O(plm_fsm_pc_counter1_reg_tx_count_s[3]) + ); + MUXCY_L plm_fsm_pc_counter1_reg_tx_count_cry_4_ ( + .CI(plm_fsm_pc_counter1_reg_tx_count_cry[3]), + .DI(plm_fsm_pc_counter1_VCC_1831), + .LO(plm_fsm_pc_counter1_reg_tx_count_cry[4]), + .S(plm_fsm_pc_counter1_reg_tx_count_qxu[4]) + ); + XORCY plm_fsm_pc_counter1_reg_tx_count_s_4_ ( + .CI(plm_fsm_pc_counter1_reg_tx_count_cry[3]), + .LI(plm_fsm_pc_counter1_reg_tx_count_qxu[4]), + .O(plm_fsm_pc_counter1_reg_tx_count_s[4]) + ); + MUXCY_L plm_fsm_pc_counter1_reg_tx_count_cry_5_ ( + .CI(plm_fsm_pc_counter1_reg_tx_count_cry[4]), + .DI(plm_fsm_pc_counter1_VCC_1831), + .LO(plm_fsm_pc_counter1_reg_tx_count_cry[5]), + .S(plm_fsm_pc_counter1_reg_tx_count_qxu[5]) + ); + XORCY plm_fsm_pc_counter1_reg_tx_count_s_5_ ( + .CI(plm_fsm_pc_counter1_reg_tx_count_cry[4]), + .LI(plm_fsm_pc_counter1_reg_tx_count_qxu[5]), + .O(plm_fsm_pc_counter1_reg_tx_count_s[5]) + ); + MUXCY_L plm_fsm_pc_counter1_reg_tx_count_cry_6_ ( + .CI(plm_fsm_pc_counter1_reg_tx_count_cry[5]), + .DI(plm_fsm_pc_counter1_VCC_1831), + .LO(plm_fsm_pc_counter1_reg_tx_count_cry[6]), + .S(plm_fsm_pc_counter1_reg_tx_count_qxu[6]) + ); + XORCY plm_fsm_pc_counter1_reg_tx_count_s_6_ ( + .CI(plm_fsm_pc_counter1_reg_tx_count_cry[5]), + .LI(plm_fsm_pc_counter1_reg_tx_count_qxu[6]), + .O(plm_fsm_pc_counter1_reg_tx_count_s[6]) + ); + XORCY plm_fsm_pc_counter1_reg_tx_count_s_7_ ( + .CI(plm_fsm_pc_counter1_reg_tx_count_cry[6]), + .LI(plm_fsm_pc_counter1_reg_tx_count_qxu[7]), + .O(plm_fsm_pc_counter1_reg_tx_count_s[7]) + ); + defparam plm_fsm_pc_counter1_loadable_tx_counter_reg_tx_count17_0_a3_0_a2_0_a3_0_a2.INIT = 4'h8; + LUT2 plm_fsm_pc_counter1_loadable_tx_counter_reg_tx_count17_0_a3_0_a2_0_a3_0_a2 ( + .I0(plm_fsm_pc_counter1_reg_oneshot_1834), + .I1(plm_fsm_reg_state_2__599), + .O(plm_fsm_pc_counter1_un1_reg_tx_count17) + ); + defparam plm_fsm_pc_counter1_oneshot_monitor_un1_enable_0_a2_0_a2_0_a3_0_a2.INIT = 4'h4; + LUT2 plm_fsm_pc_counter1_oneshot_monitor_un1_enable_0_a2_0_a2_0_a3_0_a2 ( + .I0(plm_reg_ts2_1_0), + .I1(plm_fsm_reg_state_2__599), + .O(plm_fsm_pc_counter1_un1_enable_0_a2_0_a2_0_a3_0_a2_7) + ); + defparam plm_fsm_pc_counter1_loadable_tx_counter_un1_reg_tx_count_0_a2_4.INIT = 16'h0001; + LUT4 plm_fsm_pc_counter1_loadable_tx_counter_un1_reg_tx_count_0_a2_4 ( + .I0(plm_fsm_pc_counter1_reg_tx_count[0]), + .I1(plm_fsm_pc_counter1_reg_tx_count[1]), + .I2(plm_fsm_pc_counter1_reg_tx_count[2]), + .I3(plm_fsm_pc_counter1_reg_tx_count[3]), + .O(plm_fsm_pc_counter1_un1_reg_tx_count_0_a2_4) + ); + defparam plm_fsm_pc_counter1_loadable_tx_counter_un1_reg_tx_count_0_a2_5.INIT = 16'h0001; + LUT4 plm_fsm_pc_counter1_loadable_tx_counter_un1_reg_tx_count_0_a2_5 ( + .I0(plm_fsm_pc_counter1_reg_tx_count[4]), + .I1(plm_fsm_pc_counter1_reg_tx_count[5]), + .I2(plm_fsm_pc_counter1_reg_tx_count[6]), + .I3(plm_fsm_pc_counter1_reg_tx_count[7]), + .O(plm_fsm_pc_counter1_un1_reg_tx_count_0_a2_5) + ); + defparam plm_fsm_pc_counter1_loadable_rx_counter_un1_reg_rx_count_0_a2_4.INIT = 16'h0001; + LUT4 plm_fsm_pc_counter1_loadable_rx_counter_un1_reg_rx_count_0_a2_4 ( + .I0(plm_fsm_pc_counter1_reg_rx_count[0]), + .I1(plm_fsm_pc_counter1_reg_rx_count[1]), + .I2(plm_fsm_pc_counter1_reg_rx_count[2]), + .I3(plm_fsm_pc_counter1_reg_rx_count[3]), + .O(plm_fsm_pc_counter1_un1_reg_rx_count_0_a2_4) + ); + defparam plm_fsm_pc_counter1_loadable_rx_counter_un1_reg_rx_count_0_a2_5.INIT = 16'h0001; + LUT4 plm_fsm_pc_counter1_loadable_rx_counter_un1_reg_rx_count_0_a2_5 ( + .I0(plm_fsm_pc_counter1_reg_rx_count[4]), + .I1(plm_fsm_pc_counter1_reg_rx_count[5]), + .I2(plm_fsm_pc_counter1_reg_rx_count[6]), + .I3(plm_fsm_pc_counter1_reg_rx_count[7]), + .O(plm_fsm_pc_counter1_un1_reg_rx_count_0_a2_5) + ); + defparam plm_fsm_pc_counter1_loadable_rx_counter_un1_rx_ts1_i.INIT = 4'hD; + LUT2 plm_fsm_pc_counter1_loadable_rx_counter_un1_rx_ts1_i ( + .I0(plm_fsm_pc_counter1_un1_enable_0_a2_0_a2_0_a3_0_a2_7), + .I1(plm_fsm_pc_counter1_reg_rx_expired_601), + .O(plm_fsm_pc_counter1_un1_rx_ts1_i) + ); + defparam plm_fsm_pc_counter1_N_87194_i.INIT = 16'h0F2F; + LUT4 plm_fsm_pc_counter1_N_87194_i ( + .I0(plm_reg_ts2_1_0), + .I1(plm_fsm_pc_counter1_reg_rx_expired_601), + .I2(plm_fsm_reg_state_2__599), + .I3(plm_rx1_ts2_c), + .O(plm_fsm_pc_counter1_N_87194_i_1837) + ); + defparam plm_fsm_pc_counter1_N_61024_i.INIT = 4'hB; + LUT2 plm_fsm_pc_counter1_N_61024_i ( + .I0(plm_reg_sym_sent_6_), + .I1(plm_fsm_pc_counter1_un1_enable_1), + .O(plm_fsm_pc_counter1_N_61024_i_1833) + ); + defparam plm_fsm_pc_counter1_un1_enable_2_i.INIT = 8'h8F; + LUT3 plm_fsm_pc_counter1_un1_enable_2_i ( + .I0(plm_fsm_pc_counter1_un1_reg_tx_count_0_a2_4), + .I1(plm_fsm_pc_counter1_un1_reg_tx_count_0_a2_5), + .I2(plm_fsm_pc_counter1_un1_reg_tx_count17), + .O(plm_fsm_pc_counter1_un1_enable_2_i_1835) + ); + defparam plm_fsm_pc_counter1_loadable_rx_counter_N_61031_i.INIT = 8'h8F; + LUT3 plm_fsm_pc_counter1_loadable_rx_counter_N_61031_i ( + .I0(plm_fsm_pc_counter1_un1_reg_rx_count_0_a2_4), + .I1(plm_fsm_pc_counter1_un1_reg_rx_count_0_a2_5), + .I2(plm_fsm_reg_state_2__599), + .O(plm_fsm_pc_counter1_N_61031_i) + ); + defparam plm_fsm_pc_counter1_flagit_reg_expired_5_0_a2_0_a2_0_a3_0_a2.INIT = 8'h80; + LUT3_L plm_fsm_pc_counter1_flagit_reg_expired_5_0_a2_0_a2_0_a3_0_a2 ( + .I0(plm_fsm_pc_counter1_reg_rx_expired_601), + .I1(plm_fsm_pc_counter1_reg_tx_expired_1836), + .I2(plm_fsm_reg_state_2__599), + .LO(plm_fsm_pc_counter1_reg_expired_5) + ); + defparam plm_fsm_pc_counter1_un1_enable_1_0_a3_0_a2_0_a3_0_a2.INIT = 8'h40; + LUT3 plm_fsm_pc_counter1_un1_enable_1_0_a3_0_a2_0_a3_0_a2 ( + .I0(plm_fsm_pc_counter1_reg_tx_expired_1836), + .I1(plm_fsm_reg_state_2__599), + .I2(plm_fsm_pc_counter1_reg_oneshot_1834), + .O(plm_fsm_pc_counter1_un1_enable_1) + ); + defparam plm_fsm_pc_counter1_un1_enable_1_i.INIT = 8'hF7; + LUT3 plm_fsm_pc_counter1_un1_enable_1_i ( + .I0(plm_fsm_pc_counter1_reg_oneshot_1834), + .I1(plm_fsm_reg_state_2__599), + .I2(plm_fsm_pc_counter1_reg_tx_expired_1836), + .O(plm_fsm_pc_counter1_un1_enable_1_i_1832) + ); + FDCE plm_fsm_pc_counter1_reg_tx_count_7_ ( + .CE(plm_fsm_pc_counter1_N_61024_i_1833), + .C(mgt_clk), + .D(plm_fsm_pc_counter1_reg_tx_count_s[7]), + .Q(plm_fsm_pc_counter1_reg_tx_count[7]), + .CLR(plm_rst) + ); + FDCE plm_fsm_pc_counter1_reg_tx_count_6_ ( + .CE(plm_fsm_pc_counter1_N_61024_i_1833), + .C(mgt_clk), + .D(plm_fsm_pc_counter1_reg_tx_count_s[6]), + .Q(plm_fsm_pc_counter1_reg_tx_count[6]), + .CLR(plm_rst) + ); + FDCE plm_fsm_pc_counter1_reg_tx_count_5_ ( + .CE(plm_fsm_pc_counter1_N_61024_i_1833), + .C(mgt_clk), + .D(plm_fsm_pc_counter1_reg_tx_count_s[5]), + .Q(plm_fsm_pc_counter1_reg_tx_count[5]), + .CLR(plm_rst) + ); + FDPE plm_fsm_pc_counter1_reg_tx_count_4_ ( + .PRE(plm_rst), + .CE(plm_fsm_pc_counter1_N_61024_i_1833), + .C(mgt_clk), + .D(plm_fsm_pc_counter1_reg_tx_count_s[4]), + .Q(plm_fsm_pc_counter1_reg_tx_count[4]) + ); + FDCE plm_fsm_pc_counter1_reg_tx_count_3_ ( + .CE(plm_fsm_pc_counter1_N_61024_i_1833), + .C(mgt_clk), + .D(plm_fsm_pc_counter1_reg_tx_count_s[3]), + .Q(plm_fsm_pc_counter1_reg_tx_count[3]), + .CLR(plm_rst) + ); + FDCE plm_fsm_pc_counter1_reg_tx_count_2_ ( + .CE(plm_fsm_pc_counter1_N_61024_i_1833), + .C(mgt_clk), + .D(plm_fsm_pc_counter1_reg_tx_count_s[2]), + .Q(plm_fsm_pc_counter1_reg_tx_count[2]), + .CLR(plm_rst) + ); + FDCE plm_fsm_pc_counter1_reg_tx_count_1_ ( + .CE(plm_fsm_pc_counter1_N_61024_i_1833), + .C(mgt_clk), + .D(plm_fsm_pc_counter1_reg_tx_count_s[1]), + .Q(plm_fsm_pc_counter1_reg_tx_count[1]), + .CLR(plm_rst) + ); + FDCE plm_fsm_pc_counter1_reg_tx_count_0_ ( + .CE(plm_fsm_pc_counter1_N_61024_i_1833), + .C(mgt_clk), + .D(plm_fsm_pc_counter1_reg_tx_count_s[0]), + .Q(plm_fsm_pc_counter1_reg_tx_count[0]), + .CLR(plm_rst) + ); + FDCE plm_fsm_pc_counter1_reg_rx_count_7_ ( + .CE(plm_fsm_pc_counter1_un1_rx_ts1_i), + .C(mgt_clk), + .D(plm_fsm_pc_counter1_reg_rx_count_s[7]), + .Q(plm_fsm_pc_counter1_reg_rx_count[7]), + .CLR(plm_rst) + ); + FDCE plm_fsm_pc_counter1_reg_rx_count_6_ ( + .CE(plm_fsm_pc_counter1_un1_rx_ts1_i), + .C(mgt_clk), + .D(plm_fsm_pc_counter1_reg_rx_count_s[6]), + .Q(plm_fsm_pc_counter1_reg_rx_count[6]), + .CLR(plm_rst) + ); + FDCE plm_fsm_pc_counter1_reg_rx_count_5_ ( + .CE(plm_fsm_pc_counter1_un1_rx_ts1_i), + .C(mgt_clk), + .D(plm_fsm_pc_counter1_reg_rx_count_s[5]), + .Q(plm_fsm_pc_counter1_reg_rx_count[5]), + .CLR(plm_rst) + ); + FDCE plm_fsm_pc_counter1_reg_rx_count_4_ ( + .CE(plm_fsm_pc_counter1_un1_rx_ts1_i), + .C(mgt_clk), + .D(plm_fsm_pc_counter1_reg_rx_count_s[4]), + .Q(plm_fsm_pc_counter1_reg_rx_count[4]), + .CLR(plm_rst) + ); + FDPE plm_fsm_pc_counter1_reg_rx_count_3_ ( + .PRE(plm_rst), + .CE(plm_fsm_pc_counter1_un1_rx_ts1_i), + .C(mgt_clk), + .D(plm_fsm_pc_counter1_reg_rx_count_s[3]), + .Q(plm_fsm_pc_counter1_reg_rx_count[3]) + ); + FDCE plm_fsm_pc_counter1_reg_rx_count_2_ ( + .CE(plm_fsm_pc_counter1_un1_rx_ts1_i), + .C(mgt_clk), + .D(plm_fsm_pc_counter1_reg_rx_count_s[2]), + .Q(plm_fsm_pc_counter1_reg_rx_count[2]), + .CLR(plm_rst) + ); + FDCE plm_fsm_pc_counter1_reg_rx_count_1_ ( + .CE(plm_fsm_pc_counter1_un1_rx_ts1_i), + .C(mgt_clk), + .D(plm_fsm_pc_counter1_reg_rx_count_s[1]), + .Q(plm_fsm_pc_counter1_reg_rx_count[1]), + .CLR(plm_rst) + ); + FDCE plm_fsm_pc_counter1_reg_rx_count_0_ ( + .CE(plm_fsm_pc_counter1_un1_rx_ts1_i), + .C(mgt_clk), + .D(plm_fsm_pc_counter1_reg_rx_count_s[0]), + .Q(plm_fsm_pc_counter1_reg_rx_count[0]), + .CLR(plm_rst) + ); + FDC plm_fsm_pc_counter1_reg_expired ( + .C(mgt_clk), + .D(plm_fsm_pc_counter1_reg_expired_5), + .Q(plm_fsm_pc_cntrout1), + .CLR(plm_rst) + ); + FDCE plm_fsm_pc_counter1_reg_oneshot ( + .CE(plm_fsm_pc_counter1_N_61033_i), + .C(mgt_clk), + .D(plm_fsm_reg_state_2__599), + .Q(plm_fsm_pc_counter1_reg_oneshot_1834), + .CLR(plm_rst) + ); + FDCE plm_fsm_pc_counter1_reg_rx_expired ( + .CE(plm_fsm_pc_counter1_N_61031_i), + .C(mgt_clk), + .D(plm_fsm_reg_state_2__599), + .Q(plm_fsm_pc_counter1_reg_rx_expired_601), + .CLR(plm_rst) + ); + FDCE plm_fsm_pc_counter1_reg_tx_expired ( + .CE(plm_fsm_pc_counter1_un1_enable_2_i_1835), + .C(mgt_clk), + .D(plm_fsm_pc_counter1_un1_reg_tx_count17), + .Q(plm_fsm_pc_counter1_reg_tx_expired_1836), + .CLR(plm_rst) + ); + INV plm_fsm_pc_counter1_oneshot_monitor_N_61033_i ( + .I(plm_fsm_pc_counter1_un1_enable_0_a2_0_a2_0_a3_0_a2_7), + .O(plm_fsm_pc_counter1_N_61033_i) + ); + defparam plm_fsm_pc_counter1_reg_rx_count_qxu_0_0_.INIT = 4'h7; + LUT2_L plm_fsm_pc_counter1_reg_rx_count_qxu_0_0_ ( + .I0(I_5039_0_a2_0_a2_0_a3_0_a2_32), + .I1(plm_fsm_pc_counter1_reg_rx_count[0]), + .LO(plm_fsm_pc_counter1_reg_rx_count_qxu[0]) + ); + defparam plm_fsm_pc_counter1_reg_rx_count_qxu_0_1_.INIT = 4'h7; + LUT2_L plm_fsm_pc_counter1_reg_rx_count_qxu_0_1_ ( + .I0(I_5039_0_a2_0_a2_0_a3_0_a2_32), + .I1(plm_fsm_pc_counter1_reg_rx_count[1]), + .LO(plm_fsm_pc_counter1_reg_rx_count_qxu[1]) + ); + defparam plm_fsm_pc_counter1_reg_rx_count_qxu_0_2_.INIT = 4'h7; + LUT2_L plm_fsm_pc_counter1_reg_rx_count_qxu_0_2_ ( + .I0(I_5039_0_a2_0_a2_0_a3_0_a2_32), + .I1(plm_fsm_pc_counter1_reg_rx_count[2]), + .LO(plm_fsm_pc_counter1_reg_rx_count_qxu[2]) + ); + defparam plm_fsm_pc_counter1_reg_rx_count_qxu_0_3_.INIT = 8'h1B; + LUT3_L plm_fsm_pc_counter1_reg_rx_count_qxu_0_3_ ( + .I0(I_5039_0_a2_0_a2_0_a3_0_a2_32), + .I1(plm_fsm_pc_counter1_N_87194_i_1837), + .I2(plm_fsm_pc_counter1_reg_rx_count[3]), + .LO(plm_fsm_pc_counter1_reg_rx_count_qxu[3]) + ); + defparam plm_fsm_pc_counter1_reg_rx_count_qxu_0_4_.INIT = 4'h7; + LUT2_L plm_fsm_pc_counter1_reg_rx_count_qxu_0_4_ ( + .I0(I_5039_0_a2_0_a2_0_a3_0_a2_32), + .I1(plm_fsm_pc_counter1_reg_rx_count[4]), + .LO(plm_fsm_pc_counter1_reg_rx_count_qxu[4]) + ); + defparam plm_fsm_pc_counter1_reg_rx_count_qxu_0_5_.INIT = 4'h7; + LUT2_L plm_fsm_pc_counter1_reg_rx_count_qxu_0_5_ ( + .I0(I_5039_0_a2_0_a2_0_a3_0_a2_32), + .I1(plm_fsm_pc_counter1_reg_rx_count[5]), + .LO(plm_fsm_pc_counter1_reg_rx_count_qxu[5]) + ); + defparam plm_fsm_pc_counter1_reg_rx_count_qxu_0_6_.INIT = 4'h7; + LUT2_L plm_fsm_pc_counter1_reg_rx_count_qxu_0_6_ ( + .I0(I_5039_0_a2_0_a2_0_a3_0_a2_32), + .I1(plm_fsm_pc_counter1_reg_rx_count[6]), + .LO(plm_fsm_pc_counter1_reg_rx_count_qxu[6]) + ); + defparam plm_fsm_pc_counter1_reg_rx_count_qxu_0_7_.INIT = 4'h7; + LUT2_L plm_fsm_pc_counter1_reg_rx_count_qxu_0_7_ ( + .I0(I_5039_0_a2_0_a2_0_a3_0_a2_32), + .I1(plm_fsm_pc_counter1_reg_rx_count[7]), + .LO(plm_fsm_pc_counter1_reg_rx_count_qxu[7]) + ); + defparam plm_fsm_pc_counter1_reg_tx_count_qxu_0_0_.INIT = 4'h7; + LUT2_L plm_fsm_pc_counter1_reg_tx_count_qxu_0_0_ ( + .I0(plm_fsm_pc_counter1_reg_tx_count[0]), + .I1(plm_fsm_pc_counter1_un1_enable_1), + .LO(plm_fsm_pc_counter1_reg_tx_count_qxu[0]) + ); + defparam plm_fsm_pc_counter1_reg_tx_count_qxu_0_1_.INIT = 4'h7; + LUT2_L plm_fsm_pc_counter1_reg_tx_count_qxu_0_1_ ( + .I0(plm_fsm_pc_counter1_reg_tx_count[1]), + .I1(plm_fsm_pc_counter1_un1_enable_1), + .LO(plm_fsm_pc_counter1_reg_tx_count_qxu[1]) + ); + defparam plm_fsm_pc_counter1_reg_tx_count_qxu_0_2_.INIT = 4'h7; + LUT2_L plm_fsm_pc_counter1_reg_tx_count_qxu_0_2_ ( + .I0(plm_fsm_pc_counter1_reg_tx_count[2]), + .I1(plm_fsm_pc_counter1_un1_enable_1), + .LO(plm_fsm_pc_counter1_reg_tx_count_qxu[2]) + ); + defparam plm_fsm_pc_counter1_reg_tx_count_qxu_0_3_.INIT = 4'h7; + LUT2_L plm_fsm_pc_counter1_reg_tx_count_qxu_0_3_ ( + .I0(plm_fsm_pc_counter1_reg_tx_count[3]), + .I1(plm_fsm_pc_counter1_un1_enable_1), + .LO(plm_fsm_pc_counter1_reg_tx_count_qxu[3]) + ); + defparam plm_fsm_pc_counter1_reg_tx_count_qxu_0_4_.INIT = 8'h74; + LUT3_L plm_fsm_pc_counter1_reg_tx_count_qxu_0_4_ ( + .I0(plm_fsm_pc_counter1_reg_tx_count[4]), + .I1(plm_fsm_pc_counter1_un1_enable_1), + .I2(plm_fsm_pc_counter1_un1_reg_tx_count17), + .LO(plm_fsm_pc_counter1_reg_tx_count_qxu[4]) + ); + defparam plm_fsm_pc_counter1_reg_tx_count_qxu_0_5_.INIT = 4'h7; + LUT2_L plm_fsm_pc_counter1_reg_tx_count_qxu_0_5_ ( + .I0(plm_fsm_pc_counter1_reg_tx_count[5]), + .I1(plm_fsm_pc_counter1_un1_enable_1), + .LO(plm_fsm_pc_counter1_reg_tx_count_qxu[5]) + ); + defparam plm_fsm_pc_counter1_reg_tx_count_qxu_0_6_.INIT = 4'h7; + LUT2_L plm_fsm_pc_counter1_reg_tx_count_qxu_0_6_ ( + .I0(plm_fsm_pc_counter1_reg_tx_count[6]), + .I1(plm_fsm_pc_counter1_un1_enable_1), + .LO(plm_fsm_pc_counter1_reg_tx_count_qxu[6]) + ); + defparam plm_fsm_pc_counter1_reg_tx_count_qxu_0_7_.INIT = 4'h7; + LUT2_L plm_fsm_pc_counter1_reg_tx_count_qxu_0_7_ ( + .I0(plm_fsm_pc_counter1_reg_tx_count[7]), + .I1(plm_fsm_pc_counter1_un1_enable_1), + .LO(plm_fsm_pc_counter1_reg_tx_count_qxu[7]) + ); + VCC plm_fsm_pc_counter2_VCC ( + .P(plm_fsm_pc_counter2_VCC_1838) + ); + MUXCY_L plm_fsm_pc_counter2_reg_rx_count_cry_0_ ( + .CI(N_61022_i_35), + .DI(plm_fsm_pc_counter2_VCC_1838), + .LO(plm_fsm_pc_counter2_reg_rx_count_cry[0]), + .S(plm_fsm_pc_counter2_reg_rx_count_qxu[0]) + ); + XORCY plm_fsm_pc_counter2_reg_rx_count_s_0_ ( + .CI(N_61022_i_35), + .LI(plm_fsm_pc_counter2_reg_rx_count_qxu[0]), + .O(plm_fsm_pc_counter2_reg_rx_count_s[0]) + ); + MUXCY_L plm_fsm_pc_counter2_reg_rx_count_cry_1_ ( + .CI(plm_fsm_pc_counter2_reg_rx_count_cry[0]), + .DI(plm_fsm_pc_counter2_VCC_1838), + .LO(plm_fsm_pc_counter2_reg_rx_count_cry[1]), + .S(plm_fsm_pc_counter2_reg_rx_count_qxu[1]) + ); + XORCY plm_fsm_pc_counter2_reg_rx_count_s_1_ ( + .CI(plm_fsm_pc_counter2_reg_rx_count_cry[0]), + .LI(plm_fsm_pc_counter2_reg_rx_count_qxu[1]), + .O(plm_fsm_pc_counter2_reg_rx_count_s[1]) + ); + MUXCY_L plm_fsm_pc_counter2_reg_rx_count_cry_2_ ( + .CI(plm_fsm_pc_counter2_reg_rx_count_cry[1]), + .DI(plm_fsm_pc_counter2_VCC_1838), + .LO(plm_fsm_pc_counter2_reg_rx_count_cry[2]), + .S(plm_fsm_pc_counter2_reg_rx_count_qxu[2]) + ); + XORCY plm_fsm_pc_counter2_reg_rx_count_s_2_ ( + .CI(plm_fsm_pc_counter2_reg_rx_count_cry[1]), + .LI(plm_fsm_pc_counter2_reg_rx_count_qxu[2]), + .O(plm_fsm_pc_counter2_reg_rx_count_s[2]) + ); + MUXCY_L plm_fsm_pc_counter2_reg_rx_count_cry_3_ ( + .CI(plm_fsm_pc_counter2_reg_rx_count_cry[2]), + .DI(plm_fsm_pc_counter2_VCC_1838), + .LO(plm_fsm_pc_counter2_reg_rx_count_cry[3]), + .S(plm_fsm_pc_counter2_reg_rx_count_qxu[3]) + ); + XORCY plm_fsm_pc_counter2_reg_rx_count_s_3_ ( + .CI(plm_fsm_pc_counter2_reg_rx_count_cry[2]), + .LI(plm_fsm_pc_counter2_reg_rx_count_qxu[3]), + .O(plm_fsm_pc_counter2_reg_rx_count_s[3]) + ); + MUXCY_L plm_fsm_pc_counter2_reg_rx_count_cry_4_ ( + .CI(plm_fsm_pc_counter2_reg_rx_count_cry[3]), + .DI(plm_fsm_pc_counter2_VCC_1838), + .LO(plm_fsm_pc_counter2_reg_rx_count_cry[4]), + .S(plm_fsm_pc_counter2_reg_rx_count_qxu[4]) + ); + XORCY plm_fsm_pc_counter2_reg_rx_count_s_4_ ( + .CI(plm_fsm_pc_counter2_reg_rx_count_cry[3]), + .LI(plm_fsm_pc_counter2_reg_rx_count_qxu[4]), + .O(plm_fsm_pc_counter2_reg_rx_count_s[4]) + ); + MUXCY_L plm_fsm_pc_counter2_reg_rx_count_cry_5_ ( + .CI(plm_fsm_pc_counter2_reg_rx_count_cry[4]), + .DI(plm_fsm_pc_counter2_VCC_1838), + .LO(plm_fsm_pc_counter2_reg_rx_count_cry[5]), + .S(plm_fsm_pc_counter2_reg_rx_count_qxu[5]) + ); + XORCY plm_fsm_pc_counter2_reg_rx_count_s_5_ ( + .CI(plm_fsm_pc_counter2_reg_rx_count_cry[4]), + .LI(plm_fsm_pc_counter2_reg_rx_count_qxu[5]), + .O(plm_fsm_pc_counter2_reg_rx_count_s[5]) + ); + MUXCY_L plm_fsm_pc_counter2_reg_rx_count_cry_6_ ( + .CI(plm_fsm_pc_counter2_reg_rx_count_cry[5]), + .DI(plm_fsm_pc_counter2_VCC_1838), + .LO(plm_fsm_pc_counter2_reg_rx_count_cry[6]), + .S(plm_fsm_pc_counter2_reg_rx_count_qxu[6]) + ); + XORCY plm_fsm_pc_counter2_reg_rx_count_s_6_ ( + .CI(plm_fsm_pc_counter2_reg_rx_count_cry[5]), + .LI(plm_fsm_pc_counter2_reg_rx_count_qxu[6]), + .O(plm_fsm_pc_counter2_reg_rx_count_s[6]) + ); + XORCY plm_fsm_pc_counter2_reg_rx_count_s_7_ ( + .CI(plm_fsm_pc_counter2_reg_rx_count_cry[6]), + .LI(plm_fsm_pc_counter2_reg_rx_count_qxu[7]), + .O(plm_fsm_pc_counter2_reg_rx_count_s[7]) + ); + MUXCY_L plm_fsm_pc_counter2_reg_tx_count_cry_0_ ( + .CI(plm_fsm_pc_counter2_un1_enable_1_i_1839), + .DI(plm_fsm_pc_counter2_VCC_1838), + .LO(plm_fsm_pc_counter2_reg_tx_count_cry[0]), + .S(plm_fsm_pc_counter2_reg_tx_count_qxu[0]) + ); + XORCY plm_fsm_pc_counter2_reg_tx_count_s_0_ ( + .CI(plm_fsm_pc_counter2_un1_enable_1_i_1839), + .LI(plm_fsm_pc_counter2_reg_tx_count_qxu[0]), + .O(plm_fsm_pc_counter2_reg_tx_count_s[0]) + ); + MUXCY_L plm_fsm_pc_counter2_reg_tx_count_cry_1_ ( + .CI(plm_fsm_pc_counter2_reg_tx_count_cry[0]), + .DI(plm_fsm_pc_counter2_VCC_1838), + .LO(plm_fsm_pc_counter2_reg_tx_count_cry[1]), + .S(plm_fsm_pc_counter2_reg_tx_count_qxu[1]) + ); + XORCY plm_fsm_pc_counter2_reg_tx_count_s_1_ ( + .CI(plm_fsm_pc_counter2_reg_tx_count_cry[0]), + .LI(plm_fsm_pc_counter2_reg_tx_count_qxu[1]), + .O(plm_fsm_pc_counter2_reg_tx_count_s[1]) + ); + MUXCY_L plm_fsm_pc_counter2_reg_tx_count_cry_2_ ( + .CI(plm_fsm_pc_counter2_reg_tx_count_cry[1]), + .DI(plm_fsm_pc_counter2_VCC_1838), + .LO(plm_fsm_pc_counter2_reg_tx_count_cry[2]), + .S(plm_fsm_pc_counter2_reg_tx_count_qxu[2]) + ); + XORCY plm_fsm_pc_counter2_reg_tx_count_s_2_ ( + .CI(plm_fsm_pc_counter2_reg_tx_count_cry[1]), + .LI(plm_fsm_pc_counter2_reg_tx_count_qxu[2]), + .O(plm_fsm_pc_counter2_reg_tx_count_s[2]) + ); + MUXCY_L plm_fsm_pc_counter2_reg_tx_count_cry_3_ ( + .CI(plm_fsm_pc_counter2_reg_tx_count_cry[2]), + .DI(plm_fsm_pc_counter2_VCC_1838), + .LO(plm_fsm_pc_counter2_reg_tx_count_cry[3]), + .S(plm_fsm_pc_counter2_reg_tx_count_qxu[3]) + ); + XORCY plm_fsm_pc_counter2_reg_tx_count_s_3_ ( + .CI(plm_fsm_pc_counter2_reg_tx_count_cry[2]), + .LI(plm_fsm_pc_counter2_reg_tx_count_qxu[3]), + .O(plm_fsm_pc_counter2_reg_tx_count_s[3]) + ); + MUXCY_L plm_fsm_pc_counter2_reg_tx_count_cry_4_ ( + .CI(plm_fsm_pc_counter2_reg_tx_count_cry[3]), + .DI(plm_fsm_pc_counter2_VCC_1838), + .LO(plm_fsm_pc_counter2_reg_tx_count_cry[4]), + .S(plm_fsm_pc_counter2_reg_tx_count_qxu[4]) + ); + XORCY plm_fsm_pc_counter2_reg_tx_count_s_4_ ( + .CI(plm_fsm_pc_counter2_reg_tx_count_cry[3]), + .LI(plm_fsm_pc_counter2_reg_tx_count_qxu[4]), + .O(plm_fsm_pc_counter2_reg_tx_count_s[4]) + ); + MUXCY_L plm_fsm_pc_counter2_reg_tx_count_cry_5_ ( + .CI(plm_fsm_pc_counter2_reg_tx_count_cry[4]), + .DI(plm_fsm_pc_counter2_VCC_1838), + .LO(plm_fsm_pc_counter2_reg_tx_count_cry[5]), + .S(plm_fsm_pc_counter2_reg_tx_count_qxu[5]) + ); + XORCY plm_fsm_pc_counter2_reg_tx_count_s_5_ ( + .CI(plm_fsm_pc_counter2_reg_tx_count_cry[4]), + .LI(plm_fsm_pc_counter2_reg_tx_count_qxu[5]), + .O(plm_fsm_pc_counter2_reg_tx_count_s[5]) + ); + MUXCY_L plm_fsm_pc_counter2_reg_tx_count_cry_6_ ( + .CI(plm_fsm_pc_counter2_reg_tx_count_cry[5]), + .DI(plm_fsm_pc_counter2_VCC_1838), + .LO(plm_fsm_pc_counter2_reg_tx_count_cry[6]), + .S(plm_fsm_pc_counter2_reg_tx_count_qxu[6]) + ); + XORCY plm_fsm_pc_counter2_reg_tx_count_s_6_ ( + .CI(plm_fsm_pc_counter2_reg_tx_count_cry[5]), + .LI(plm_fsm_pc_counter2_reg_tx_count_qxu[6]), + .O(plm_fsm_pc_counter2_reg_tx_count_s[6]) + ); + XORCY plm_fsm_pc_counter2_reg_tx_count_s_7_ ( + .CI(plm_fsm_pc_counter2_reg_tx_count_cry[6]), + .LI(plm_fsm_pc_counter2_reg_tx_count_qxu[7]), + .O(plm_fsm_pc_counter2_reg_tx_count_s[7]) + ); + defparam plm_fsm_pc_counter2_loadable_tx_counter_reg_tx_count17_0_a3_0_a3_0_a2_0_a2_0_a3_0_a2.INIT = 4'h8; + LUT2 plm_fsm_pc_counter2_loadable_tx_counter_reg_tx_count17_0_a3_0_a3_0_a2_0_a2_0_a3_0_a2 ( + .I0(plm_fsm_pc_counter2_reg_oneshot_1841), + .I1(plm_fsm_reg_state_2__599), + .O(plm_fsm_pc_counter2_un1_reg_tx_count17) + ); + defparam plm_fsm_pc_counter2_oneshot_monitor_un1_enable_0_a3_0_a2_0_a3_0_a2.INIT = 4'h4; + LUT2 plm_fsm_pc_counter2_oneshot_monitor_un1_enable_0_a3_0_a2_0_a3_0_a2 ( + .I0(plm_reg_ts2_1_1), + .I1(plm_fsm_reg_state_2__599), + .O(plm_fsm_pc_counter2_un1_enable_0_a3_0_a2_0_a3_0_a2) + ); + defparam plm_fsm_pc_counter2_loadable_rx_counter_un1_reg_rx_count_0_a2_4.INIT = 16'h0001; + LUT4 plm_fsm_pc_counter2_loadable_rx_counter_un1_reg_rx_count_0_a2_4 ( + .I0(plm_fsm_pc_counter2_reg_rx_count[0]), + .I1(plm_fsm_pc_counter2_reg_rx_count[1]), + .I2(plm_fsm_pc_counter2_reg_rx_count[2]), + .I3(plm_fsm_pc_counter2_reg_rx_count[3]), + .O(plm_fsm_pc_counter2_un1_reg_rx_count_0_a2_4) + ); + defparam plm_fsm_pc_counter2_loadable_rx_counter_un1_reg_rx_count_0_a2_5.INIT = 16'h0001; + LUT4 plm_fsm_pc_counter2_loadable_rx_counter_un1_reg_rx_count_0_a2_5 ( + .I0(plm_fsm_pc_counter2_reg_rx_count[4]), + .I1(plm_fsm_pc_counter2_reg_rx_count[5]), + .I2(plm_fsm_pc_counter2_reg_rx_count[6]), + .I3(plm_fsm_pc_counter2_reg_rx_count[7]), + .O(plm_fsm_pc_counter2_un1_reg_rx_count_0_a2_5) + ); + defparam plm_fsm_pc_counter2_loadable_tx_counter_un1_reg_tx_count_0_a2_4.INIT = 16'h0001; + LUT4 plm_fsm_pc_counter2_loadable_tx_counter_un1_reg_tx_count_0_a2_4 ( + .I0(plm_fsm_pc_counter2_reg_tx_count[0]), + .I1(plm_fsm_pc_counter2_reg_tx_count[1]), + .I2(plm_fsm_pc_counter2_reg_tx_count[2]), + .I3(plm_fsm_pc_counter2_reg_tx_count[3]), + .O(plm_fsm_pc_counter2_un1_reg_tx_count_0_a2_4) + ); + defparam plm_fsm_pc_counter2_loadable_tx_counter_un1_reg_tx_count_0_a2_5.INIT = 16'h0001; + LUT4 plm_fsm_pc_counter2_loadable_tx_counter_un1_reg_tx_count_0_a2_5 ( + .I0(plm_fsm_pc_counter2_reg_tx_count[4]), + .I1(plm_fsm_pc_counter2_reg_tx_count[5]), + .I2(plm_fsm_pc_counter2_reg_tx_count[6]), + .I3(plm_fsm_pc_counter2_reg_tx_count[7]), + .O(plm_fsm_pc_counter2_un1_reg_tx_count_0_a2_5) + ); + defparam plm_fsm_pc_counter2_loadable_rx_counter_un1_rx_ts1_i.INIT = 4'hD; + LUT2 plm_fsm_pc_counter2_loadable_rx_counter_un1_rx_ts1_i ( + .I0(plm_fsm_pc_counter2_un1_enable_0_a3_0_a2_0_a3_0_a2), + .I1(plm_fsm_pc_counter2_reg_rx_expired_598), + .O(plm_fsm_pc_counter2_un1_rx_ts1_i) + ); + defparam plm_fsm_pc_counter2_N_87189_i.INIT = 16'h0F2F; + LUT4 plm_fsm_pc_counter2_N_87189_i ( + .I0(plm_reg_ts2_1_1), + .I1(plm_fsm_pc_counter2_reg_rx_expired_598), + .I2(plm_fsm_reg_state_2__599), + .I3(plm_rx2_ts2_c), + .O(plm_fsm_pc_counter2_N_87189_i_1844) + ); + defparam plm_fsm_pc_counter2_N_61025_i.INIT = 4'hB; + LUT2 plm_fsm_pc_counter2_N_61025_i ( + .I0(plm_reg_sym_sent_6_), + .I1(plm_fsm_pc_counter2_un1_enable_1), + .O(plm_fsm_pc_counter2_N_61025_i_1840) + ); + defparam plm_fsm_pc_counter2_un1_enable_2_i.INIT = 8'h8F; + LUT3 plm_fsm_pc_counter2_un1_enable_2_i ( + .I0(plm_fsm_pc_counter2_un1_reg_tx_count_0_a2_4), + .I1(plm_fsm_pc_counter2_un1_reg_tx_count_0_a2_5), + .I2(plm_fsm_pc_counter2_un1_reg_tx_count17), + .O(plm_fsm_pc_counter2_un1_enable_2_i_1842) + ); + defparam plm_fsm_pc_counter2_loadable_rx_counter_N_61029_i.INIT = 8'h8F; + LUT3 plm_fsm_pc_counter2_loadable_rx_counter_N_61029_i ( + .I0(plm_fsm_pc_counter2_un1_reg_rx_count_0_a2_4), + .I1(plm_fsm_pc_counter2_un1_reg_rx_count_0_a2_5), + .I2(plm_fsm_reg_state_2__599), + .O(plm_fsm_pc_counter2_N_61029_i) + ); + defparam plm_fsm_pc_counter2_flagit_reg_expired_5_0_a2_0_a2_0_a3_0_a2.INIT = 8'h80; + LUT3_L plm_fsm_pc_counter2_flagit_reg_expired_5_0_a2_0_a2_0_a3_0_a2 ( + .I0(plm_fsm_pc_counter2_reg_rx_expired_598), + .I1(plm_fsm_pc_counter2_reg_tx_expired_1843), + .I2(plm_fsm_reg_state_2__599), + .LO(plm_fsm_pc_counter2_reg_expired_5) + ); + defparam plm_fsm_pc_counter2_un1_enable_1_0_a3_0_a2_0_a3_0_a2.INIT = 8'h40; + LUT3 plm_fsm_pc_counter2_un1_enable_1_0_a3_0_a2_0_a3_0_a2 ( + .I0(plm_fsm_pc_counter2_reg_tx_expired_1843), + .I1(plm_fsm_reg_state_2__599), + .I2(plm_fsm_pc_counter2_reg_oneshot_1841), + .O(plm_fsm_pc_counter2_un1_enable_1) + ); + defparam plm_fsm_pc_counter2_un1_enable_1_i.INIT = 8'hF7; + LUT3 plm_fsm_pc_counter2_un1_enable_1_i ( + .I0(plm_fsm_pc_counter2_reg_oneshot_1841), + .I1(plm_fsm_reg_state_2__599), + .I2(plm_fsm_pc_counter2_reg_tx_expired_1843), + .O(plm_fsm_pc_counter2_un1_enable_1_i_1839) + ); + FDCE plm_fsm_pc_counter2_reg_tx_count_7_ ( + .CE(plm_fsm_pc_counter2_N_61025_i_1840), + .C(mgt_clk), + .D(plm_fsm_pc_counter2_reg_tx_count_s[7]), + .Q(plm_fsm_pc_counter2_reg_tx_count[7]), + .CLR(plm_rst) + ); + FDCE plm_fsm_pc_counter2_reg_tx_count_6_ ( + .CE(plm_fsm_pc_counter2_N_61025_i_1840), + .C(mgt_clk), + .D(plm_fsm_pc_counter2_reg_tx_count_s[6]), + .Q(plm_fsm_pc_counter2_reg_tx_count[6]), + .CLR(plm_rst) + ); + FDCE plm_fsm_pc_counter2_reg_tx_count_5_ ( + .CE(plm_fsm_pc_counter2_N_61025_i_1840), + .C(mgt_clk), + .D(plm_fsm_pc_counter2_reg_tx_count_s[5]), + .Q(plm_fsm_pc_counter2_reg_tx_count[5]), + .CLR(plm_rst) + ); + FDPE plm_fsm_pc_counter2_reg_tx_count_4_ ( + .PRE(plm_rst), + .CE(plm_fsm_pc_counter2_N_61025_i_1840), + .C(mgt_clk), + .D(plm_fsm_pc_counter2_reg_tx_count_s[4]), + .Q(plm_fsm_pc_counter2_reg_tx_count[4]) + ); + FDCE plm_fsm_pc_counter2_reg_tx_count_3_ ( + .CE(plm_fsm_pc_counter2_N_61025_i_1840), + .C(mgt_clk), + .D(plm_fsm_pc_counter2_reg_tx_count_s[3]), + .Q(plm_fsm_pc_counter2_reg_tx_count[3]), + .CLR(plm_rst) + ); + FDCE plm_fsm_pc_counter2_reg_tx_count_2_ ( + .CE(plm_fsm_pc_counter2_N_61025_i_1840), + .C(mgt_clk), + .D(plm_fsm_pc_counter2_reg_tx_count_s[2]), + .Q(plm_fsm_pc_counter2_reg_tx_count[2]), + .CLR(plm_rst) + ); + FDCE plm_fsm_pc_counter2_reg_tx_count_1_ ( + .CE(plm_fsm_pc_counter2_N_61025_i_1840), + .C(mgt_clk), + .D(plm_fsm_pc_counter2_reg_tx_count_s[1]), + .Q(plm_fsm_pc_counter2_reg_tx_count[1]), + .CLR(plm_rst) + ); + FDCE plm_fsm_pc_counter2_reg_tx_count_0_ ( + .CE(plm_fsm_pc_counter2_N_61025_i_1840), + .C(mgt_clk), + .D(plm_fsm_pc_counter2_reg_tx_count_s[0]), + .Q(plm_fsm_pc_counter2_reg_tx_count[0]), + .CLR(plm_rst) + ); + FDCE plm_fsm_pc_counter2_reg_rx_count_7_ ( + .CE(plm_fsm_pc_counter2_un1_rx_ts1_i), + .C(mgt_clk), + .D(plm_fsm_pc_counter2_reg_rx_count_s[7]), + .Q(plm_fsm_pc_counter2_reg_rx_count[7]), + .CLR(plm_rst) + ); + FDCE plm_fsm_pc_counter2_reg_rx_count_6_ ( + .CE(plm_fsm_pc_counter2_un1_rx_ts1_i), + .C(mgt_clk), + .D(plm_fsm_pc_counter2_reg_rx_count_s[6]), + .Q(plm_fsm_pc_counter2_reg_rx_count[6]), + .CLR(plm_rst) + ); + FDCE plm_fsm_pc_counter2_reg_rx_count_5_ ( + .CE(plm_fsm_pc_counter2_un1_rx_ts1_i), + .C(mgt_clk), + .D(plm_fsm_pc_counter2_reg_rx_count_s[5]), + .Q(plm_fsm_pc_counter2_reg_rx_count[5]), + .CLR(plm_rst) + ); + FDCE plm_fsm_pc_counter2_reg_rx_count_4_ ( + .CE(plm_fsm_pc_counter2_un1_rx_ts1_i), + .C(mgt_clk), + .D(plm_fsm_pc_counter2_reg_rx_count_s[4]), + .Q(plm_fsm_pc_counter2_reg_rx_count[4]), + .CLR(plm_rst) + ); + FDPE plm_fsm_pc_counter2_reg_rx_count_3_ ( + .PRE(plm_rst), + .CE(plm_fsm_pc_counter2_un1_rx_ts1_i), + .C(mgt_clk), + .D(plm_fsm_pc_counter2_reg_rx_count_s[3]), + .Q(plm_fsm_pc_counter2_reg_rx_count[3]) + ); + FDCE plm_fsm_pc_counter2_reg_rx_count_2_ ( + .CE(plm_fsm_pc_counter2_un1_rx_ts1_i), + .C(mgt_clk), + .D(plm_fsm_pc_counter2_reg_rx_count_s[2]), + .Q(plm_fsm_pc_counter2_reg_rx_count[2]), + .CLR(plm_rst) + ); + FDCE plm_fsm_pc_counter2_reg_rx_count_1_ ( + .CE(plm_fsm_pc_counter2_un1_rx_ts1_i), + .C(mgt_clk), + .D(plm_fsm_pc_counter2_reg_rx_count_s[1]), + .Q(plm_fsm_pc_counter2_reg_rx_count[1]), + .CLR(plm_rst) + ); + FDCE plm_fsm_pc_counter2_reg_rx_count_0_ ( + .CE(plm_fsm_pc_counter2_un1_rx_ts1_i), + .C(mgt_clk), + .D(plm_fsm_pc_counter2_reg_rx_count_s[0]), + .Q(plm_fsm_pc_counter2_reg_rx_count[0]), + .CLR(plm_rst) + ); + FDC plm_fsm_pc_counter2_reg_expired ( + .C(mgt_clk), + .D(plm_fsm_pc_counter2_reg_expired_5), + .Q(plm_fsm_pc_cntrout2), + .CLR(plm_rst) + ); + FDCE plm_fsm_pc_counter2_reg_oneshot ( + .CE(plm_fsm_pc_counter2_N_61039_i), + .C(mgt_clk), + .D(plm_fsm_reg_state_2__599), + .Q(plm_fsm_pc_counter2_reg_oneshot_1841), + .CLR(plm_rst) + ); + FDCE plm_fsm_pc_counter2_reg_rx_expired ( + .CE(plm_fsm_pc_counter2_N_61029_i), + .C(mgt_clk), + .D(plm_fsm_reg_state_2__599), + .Q(plm_fsm_pc_counter2_reg_rx_expired_598), + .CLR(plm_rst) + ); + FDCE plm_fsm_pc_counter2_reg_tx_expired ( + .CE(plm_fsm_pc_counter2_un1_enable_2_i_1842), + .C(mgt_clk), + .D(plm_fsm_pc_counter2_un1_reg_tx_count17), + .Q(plm_fsm_pc_counter2_reg_tx_expired_1843), + .CLR(plm_rst) + ); + INV plm_fsm_pc_counter2_oneshot_monitor_N_61039_i ( + .I(plm_fsm_pc_counter2_un1_enable_0_a3_0_a2_0_a3_0_a2), + .O(plm_fsm_pc_counter2_N_61039_i) + ); + defparam plm_fsm_pc_counter2_reg_rx_count_qxu_0_0_.INIT = 4'h7; + LUT2_L plm_fsm_pc_counter2_reg_rx_count_qxu_0_0_ ( + .I0(I_5045_0_a2_0_a2_0_a3_0_a2_34), + .I1(plm_fsm_pc_counter2_reg_rx_count[0]), + .LO(plm_fsm_pc_counter2_reg_rx_count_qxu[0]) + ); + defparam plm_fsm_pc_counter2_reg_rx_count_qxu_0_1_.INIT = 4'h7; + LUT2_L plm_fsm_pc_counter2_reg_rx_count_qxu_0_1_ ( + .I0(I_5045_0_a2_0_a2_0_a3_0_a2_34), + .I1(plm_fsm_pc_counter2_reg_rx_count[1]), + .LO(plm_fsm_pc_counter2_reg_rx_count_qxu[1]) + ); + defparam plm_fsm_pc_counter2_reg_rx_count_qxu_0_2_.INIT = 4'h7; + LUT2_L plm_fsm_pc_counter2_reg_rx_count_qxu_0_2_ ( + .I0(I_5045_0_a2_0_a2_0_a3_0_a2_34), + .I1(plm_fsm_pc_counter2_reg_rx_count[2]), + .LO(plm_fsm_pc_counter2_reg_rx_count_qxu[2]) + ); + defparam plm_fsm_pc_counter2_reg_rx_count_qxu_0_3_.INIT = 8'h1B; + LUT3_L plm_fsm_pc_counter2_reg_rx_count_qxu_0_3_ ( + .I0(I_5045_0_a2_0_a2_0_a3_0_a2_34), + .I1(plm_fsm_pc_counter2_N_87189_i_1844), + .I2(plm_fsm_pc_counter2_reg_rx_count[3]), + .LO(plm_fsm_pc_counter2_reg_rx_count_qxu[3]) + ); + defparam plm_fsm_pc_counter2_reg_rx_count_qxu_0_4_.INIT = 4'h7; + LUT2_L plm_fsm_pc_counter2_reg_rx_count_qxu_0_4_ ( + .I0(I_5045_0_a2_0_a2_0_a3_0_a2_34), + .I1(plm_fsm_pc_counter2_reg_rx_count[4]), + .LO(plm_fsm_pc_counter2_reg_rx_count_qxu[4]) + ); + defparam plm_fsm_pc_counter2_reg_rx_count_qxu_0_5_.INIT = 4'h7; + LUT2_L plm_fsm_pc_counter2_reg_rx_count_qxu_0_5_ ( + .I0(I_5045_0_a2_0_a2_0_a3_0_a2_34), + .I1(plm_fsm_pc_counter2_reg_rx_count[5]), + .LO(plm_fsm_pc_counter2_reg_rx_count_qxu[5]) + ); + defparam plm_fsm_pc_counter2_reg_rx_count_qxu_0_6_.INIT = 4'h7; + LUT2_L plm_fsm_pc_counter2_reg_rx_count_qxu_0_6_ ( + .I0(I_5045_0_a2_0_a2_0_a3_0_a2_34), + .I1(plm_fsm_pc_counter2_reg_rx_count[6]), + .LO(plm_fsm_pc_counter2_reg_rx_count_qxu[6]) + ); + defparam plm_fsm_pc_counter2_reg_rx_count_qxu_0_7_.INIT = 4'h7; + LUT2_L plm_fsm_pc_counter2_reg_rx_count_qxu_0_7_ ( + .I0(I_5045_0_a2_0_a2_0_a3_0_a2_34), + .I1(plm_fsm_pc_counter2_reg_rx_count[7]), + .LO(plm_fsm_pc_counter2_reg_rx_count_qxu[7]) + ); + defparam plm_fsm_pc_counter2_reg_tx_count_qxu_0_0_.INIT = 4'h7; + LUT2_L plm_fsm_pc_counter2_reg_tx_count_qxu_0_0_ ( + .I0(plm_fsm_pc_counter2_reg_tx_count[0]), + .I1(plm_fsm_pc_counter2_un1_enable_1), + .LO(plm_fsm_pc_counter2_reg_tx_count_qxu[0]) + ); + defparam plm_fsm_pc_counter2_reg_tx_count_qxu_0_1_.INIT = 4'h7; + LUT2_L plm_fsm_pc_counter2_reg_tx_count_qxu_0_1_ ( + .I0(plm_fsm_pc_counter2_reg_tx_count[1]), + .I1(plm_fsm_pc_counter2_un1_enable_1), + .LO(plm_fsm_pc_counter2_reg_tx_count_qxu[1]) + ); + defparam plm_fsm_pc_counter2_reg_tx_count_qxu_0_2_.INIT = 4'h7; + LUT2_L plm_fsm_pc_counter2_reg_tx_count_qxu_0_2_ ( + .I0(plm_fsm_pc_counter2_reg_tx_count[2]), + .I1(plm_fsm_pc_counter2_un1_enable_1), + .LO(plm_fsm_pc_counter2_reg_tx_count_qxu[2]) + ); + defparam plm_fsm_pc_counter2_reg_tx_count_qxu_0_3_.INIT = 4'h7; + LUT2_L plm_fsm_pc_counter2_reg_tx_count_qxu_0_3_ ( + .I0(plm_fsm_pc_counter2_reg_tx_count[3]), + .I1(plm_fsm_pc_counter2_un1_enable_1), + .LO(plm_fsm_pc_counter2_reg_tx_count_qxu[3]) + ); + defparam plm_fsm_pc_counter2_reg_tx_count_qxu_0_4_.INIT = 8'h74; + LUT3_L plm_fsm_pc_counter2_reg_tx_count_qxu_0_4_ ( + .I0(plm_fsm_pc_counter2_reg_tx_count[4]), + .I1(plm_fsm_pc_counter2_un1_enable_1), + .I2(plm_fsm_pc_counter2_un1_reg_tx_count17), + .LO(plm_fsm_pc_counter2_reg_tx_count_qxu[4]) + ); + defparam plm_fsm_pc_counter2_reg_tx_count_qxu_0_5_.INIT = 4'h7; + LUT2_L plm_fsm_pc_counter2_reg_tx_count_qxu_0_5_ ( + .I0(plm_fsm_pc_counter2_reg_tx_count[5]), + .I1(plm_fsm_pc_counter2_un1_enable_1), + .LO(plm_fsm_pc_counter2_reg_tx_count_qxu[5]) + ); + defparam plm_fsm_pc_counter2_reg_tx_count_qxu_0_6_.INIT = 4'h7; + LUT2_L plm_fsm_pc_counter2_reg_tx_count_qxu_0_6_ ( + .I0(plm_fsm_pc_counter2_reg_tx_count[6]), + .I1(plm_fsm_pc_counter2_un1_enable_1), + .LO(plm_fsm_pc_counter2_reg_tx_count_qxu[6]) + ); + defparam plm_fsm_pc_counter2_reg_tx_count_qxu_0_7_.INIT = 4'h7; + LUT2_L plm_fsm_pc_counter2_reg_tx_count_qxu_0_7_ ( + .I0(plm_fsm_pc_counter2_reg_tx_count[7]), + .I1(plm_fsm_pc_counter2_un1_enable_1), + .LO(plm_fsm_pc_counter2_reg_tx_count_qxu[7]) + ); + VCC plm_fsm_pc_counter3_VCC ( + .P(plm_fsm_pc_counter3_VCC_1845) + ); + MUXCY_L plm_fsm_pc_counter3_reg_rx_count_cry_0_ ( + .CI(N_60976_i_37), + .DI(plm_fsm_pc_counter3_VCC_1845), + .LO(plm_fsm_pc_counter3_reg_rx_count_cry[0]), + .S(plm_fsm_pc_counter3_reg_rx_count_qxu[0]) + ); + XORCY plm_fsm_pc_counter3_reg_rx_count_s_0_ ( + .CI(N_60976_i_37), + .LI(plm_fsm_pc_counter3_reg_rx_count_qxu[0]), + .O(plm_fsm_pc_counter3_reg_rx_count_s[0]) + ); + MUXCY_L plm_fsm_pc_counter3_reg_rx_count_cry_1_ ( + .CI(plm_fsm_pc_counter3_reg_rx_count_cry[0]), + .DI(plm_fsm_pc_counter3_VCC_1845), + .LO(plm_fsm_pc_counter3_reg_rx_count_cry[1]), + .S(plm_fsm_pc_counter3_reg_rx_count_qxu[1]) + ); + XORCY plm_fsm_pc_counter3_reg_rx_count_s_1_ ( + .CI(plm_fsm_pc_counter3_reg_rx_count_cry[0]), + .LI(plm_fsm_pc_counter3_reg_rx_count_qxu[1]), + .O(plm_fsm_pc_counter3_reg_rx_count_s[1]) + ); + MUXCY_L plm_fsm_pc_counter3_reg_rx_count_cry_2_ ( + .CI(plm_fsm_pc_counter3_reg_rx_count_cry[1]), + .DI(plm_fsm_pc_counter3_VCC_1845), + .LO(plm_fsm_pc_counter3_reg_rx_count_cry[2]), + .S(plm_fsm_pc_counter3_reg_rx_count_qxu[2]) + ); + XORCY plm_fsm_pc_counter3_reg_rx_count_s_2_ ( + .CI(plm_fsm_pc_counter3_reg_rx_count_cry[1]), + .LI(plm_fsm_pc_counter3_reg_rx_count_qxu[2]), + .O(plm_fsm_pc_counter3_reg_rx_count_s[2]) + ); + MUXCY_L plm_fsm_pc_counter3_reg_rx_count_cry_3_ ( + .CI(plm_fsm_pc_counter3_reg_rx_count_cry[2]), + .DI(plm_fsm_pc_counter3_VCC_1845), + .LO(plm_fsm_pc_counter3_reg_rx_count_cry[3]), + .S(plm_fsm_pc_counter3_reg_rx_count_qxu[3]) + ); + XORCY plm_fsm_pc_counter3_reg_rx_count_s_3_ ( + .CI(plm_fsm_pc_counter3_reg_rx_count_cry[2]), + .LI(plm_fsm_pc_counter3_reg_rx_count_qxu[3]), + .O(plm_fsm_pc_counter3_reg_rx_count_s[3]) + ); + MUXCY_L plm_fsm_pc_counter3_reg_rx_count_cry_4_ ( + .CI(plm_fsm_pc_counter3_reg_rx_count_cry[3]), + .DI(plm_fsm_pc_counter3_VCC_1845), + .LO(plm_fsm_pc_counter3_reg_rx_count_cry[4]), + .S(plm_fsm_pc_counter3_reg_rx_count_qxu[4]) + ); + XORCY plm_fsm_pc_counter3_reg_rx_count_s_4_ ( + .CI(plm_fsm_pc_counter3_reg_rx_count_cry[3]), + .LI(plm_fsm_pc_counter3_reg_rx_count_qxu[4]), + .O(plm_fsm_pc_counter3_reg_rx_count_s[4]) + ); + MUXCY_L plm_fsm_pc_counter3_reg_rx_count_cry_5_ ( + .CI(plm_fsm_pc_counter3_reg_rx_count_cry[4]), + .DI(plm_fsm_pc_counter3_VCC_1845), + .LO(plm_fsm_pc_counter3_reg_rx_count_cry[5]), + .S(plm_fsm_pc_counter3_reg_rx_count_qxu[5]) + ); + XORCY plm_fsm_pc_counter3_reg_rx_count_s_5_ ( + .CI(plm_fsm_pc_counter3_reg_rx_count_cry[4]), + .LI(plm_fsm_pc_counter3_reg_rx_count_qxu[5]), + .O(plm_fsm_pc_counter3_reg_rx_count_s[5]) + ); + MUXCY_L plm_fsm_pc_counter3_reg_rx_count_cry_6_ ( + .CI(plm_fsm_pc_counter3_reg_rx_count_cry[5]), + .DI(plm_fsm_pc_counter3_VCC_1845), + .LO(plm_fsm_pc_counter3_reg_rx_count_cry[6]), + .S(plm_fsm_pc_counter3_reg_rx_count_qxu[6]) + ); + XORCY plm_fsm_pc_counter3_reg_rx_count_s_6_ ( + .CI(plm_fsm_pc_counter3_reg_rx_count_cry[5]), + .LI(plm_fsm_pc_counter3_reg_rx_count_qxu[6]), + .O(plm_fsm_pc_counter3_reg_rx_count_s[6]) + ); + XORCY plm_fsm_pc_counter3_reg_rx_count_s_7_ ( + .CI(plm_fsm_pc_counter3_reg_rx_count_cry[6]), + .LI(plm_fsm_pc_counter3_reg_rx_count_qxu[7]), + .O(plm_fsm_pc_counter3_reg_rx_count_s[7]) + ); + MUXCY_L plm_fsm_pc_counter3_reg_tx_count_cry_0_ ( + .CI(plm_fsm_pc_counter3_un1_enable_1_i_1846), + .DI(plm_fsm_pc_counter3_VCC_1845), + .LO(plm_fsm_pc_counter3_reg_tx_count_cry[0]), + .S(plm_fsm_pc_counter3_reg_tx_count_qxu[0]) + ); + XORCY plm_fsm_pc_counter3_reg_tx_count_s_0_ ( + .CI(plm_fsm_pc_counter3_un1_enable_1_i_1846), + .LI(plm_fsm_pc_counter3_reg_tx_count_qxu[0]), + .O(plm_fsm_pc_counter3_reg_tx_count_s[0]) + ); + MUXCY_L plm_fsm_pc_counter3_reg_tx_count_cry_1_ ( + .CI(plm_fsm_pc_counter3_reg_tx_count_cry[0]), + .DI(plm_fsm_pc_counter3_VCC_1845), + .LO(plm_fsm_pc_counter3_reg_tx_count_cry[1]), + .S(plm_fsm_pc_counter3_reg_tx_count_qxu[1]) + ); + XORCY plm_fsm_pc_counter3_reg_tx_count_s_1_ ( + .CI(plm_fsm_pc_counter3_reg_tx_count_cry[0]), + .LI(plm_fsm_pc_counter3_reg_tx_count_qxu[1]), + .O(plm_fsm_pc_counter3_reg_tx_count_s[1]) + ); + MUXCY_L plm_fsm_pc_counter3_reg_tx_count_cry_2_ ( + .CI(plm_fsm_pc_counter3_reg_tx_count_cry[1]), + .DI(plm_fsm_pc_counter3_VCC_1845), + .LO(plm_fsm_pc_counter3_reg_tx_count_cry[2]), + .S(plm_fsm_pc_counter3_reg_tx_count_qxu[2]) + ); + XORCY plm_fsm_pc_counter3_reg_tx_count_s_2_ ( + .CI(plm_fsm_pc_counter3_reg_tx_count_cry[1]), + .LI(plm_fsm_pc_counter3_reg_tx_count_qxu[2]), + .O(plm_fsm_pc_counter3_reg_tx_count_s[2]) + ); + MUXCY_L plm_fsm_pc_counter3_reg_tx_count_cry_3_ ( + .CI(plm_fsm_pc_counter3_reg_tx_count_cry[2]), + .DI(plm_fsm_pc_counter3_VCC_1845), + .LO(plm_fsm_pc_counter3_reg_tx_count_cry[3]), + .S(plm_fsm_pc_counter3_reg_tx_count_qxu[3]) + ); + XORCY plm_fsm_pc_counter3_reg_tx_count_s_3_ ( + .CI(plm_fsm_pc_counter3_reg_tx_count_cry[2]), + .LI(plm_fsm_pc_counter3_reg_tx_count_qxu[3]), + .O(plm_fsm_pc_counter3_reg_tx_count_s[3]) + ); + MUXCY_L plm_fsm_pc_counter3_reg_tx_count_cry_4_ ( + .CI(plm_fsm_pc_counter3_reg_tx_count_cry[3]), + .DI(plm_fsm_pc_counter3_VCC_1845), + .LO(plm_fsm_pc_counter3_reg_tx_count_cry[4]), + .S(plm_fsm_pc_counter3_reg_tx_count_qxu[4]) + ); + XORCY plm_fsm_pc_counter3_reg_tx_count_s_4_ ( + .CI(plm_fsm_pc_counter3_reg_tx_count_cry[3]), + .LI(plm_fsm_pc_counter3_reg_tx_count_qxu[4]), + .O(plm_fsm_pc_counter3_reg_tx_count_s[4]) + ); + MUXCY_L plm_fsm_pc_counter3_reg_tx_count_cry_5_ ( + .CI(plm_fsm_pc_counter3_reg_tx_count_cry[4]), + .DI(plm_fsm_pc_counter3_VCC_1845), + .LO(plm_fsm_pc_counter3_reg_tx_count_cry[5]), + .S(plm_fsm_pc_counter3_reg_tx_count_qxu[5]) + ); + XORCY plm_fsm_pc_counter3_reg_tx_count_s_5_ ( + .CI(plm_fsm_pc_counter3_reg_tx_count_cry[4]), + .LI(plm_fsm_pc_counter3_reg_tx_count_qxu[5]), + .O(plm_fsm_pc_counter3_reg_tx_count_s[5]) + ); + MUXCY_L plm_fsm_pc_counter3_reg_tx_count_cry_6_ ( + .CI(plm_fsm_pc_counter3_reg_tx_count_cry[5]), + .DI(plm_fsm_pc_counter3_VCC_1845), + .LO(plm_fsm_pc_counter3_reg_tx_count_cry[6]), + .S(plm_fsm_pc_counter3_reg_tx_count_qxu[6]) + ); + XORCY plm_fsm_pc_counter3_reg_tx_count_s_6_ ( + .CI(plm_fsm_pc_counter3_reg_tx_count_cry[5]), + .LI(plm_fsm_pc_counter3_reg_tx_count_qxu[6]), + .O(plm_fsm_pc_counter3_reg_tx_count_s[6]) + ); + XORCY plm_fsm_pc_counter3_reg_tx_count_s_7_ ( + .CI(plm_fsm_pc_counter3_reg_tx_count_cry[6]), + .LI(plm_fsm_pc_counter3_reg_tx_count_qxu[7]), + .O(plm_fsm_pc_counter3_reg_tx_count_s[7]) + ); + defparam plm_fsm_pc_counter3_oneshot_monitor_un1_enable_0_a2_0_a2_0_a3_0_a2.INIT = 4'h4; + LUT2 plm_fsm_pc_counter3_oneshot_monitor_un1_enable_0_a2_0_a2_0_a3_0_a2 ( + .I0(plm_reg_ts2_1_2), + .I1(plm_fsm_reg_state_2__599), + .O(plm_fsm_pc_counter3_un1_enable_0_a2_0_a2_0_a3_0_a2_8) + ); + defparam plm_fsm_pc_counter3_loadable_tx_counter_reg_tx_count17_0_a3_0_a2_0_a3_0_a2.INIT = 4'h8; + LUT2 plm_fsm_pc_counter3_loadable_tx_counter_reg_tx_count17_0_a3_0_a2_0_a3_0_a2 ( + .I0(plm_fsm_pc_counter3_reg_oneshot_1848), + .I1(plm_fsm_reg_state_2__599), + .O(plm_fsm_pc_counter3_un1_reg_tx_count17) + ); + defparam plm_fsm_pc_counter3_loadable_tx_counter_un1_reg_tx_count_0_a2_4.INIT = 16'h0001; + LUT4 plm_fsm_pc_counter3_loadable_tx_counter_un1_reg_tx_count_0_a2_4 ( + .I0(plm_fsm_pc_counter3_reg_tx_count[0]), + .I1(plm_fsm_pc_counter3_reg_tx_count[1]), + .I2(plm_fsm_pc_counter3_reg_tx_count[2]), + .I3(plm_fsm_pc_counter3_reg_tx_count[3]), + .O(plm_fsm_pc_counter3_un1_reg_tx_count_0_a2_4) + ); + defparam plm_fsm_pc_counter3_loadable_tx_counter_un1_reg_tx_count_0_a2_5.INIT = 16'h0001; + LUT4 plm_fsm_pc_counter3_loadable_tx_counter_un1_reg_tx_count_0_a2_5 ( + .I0(plm_fsm_pc_counter3_reg_tx_count[4]), + .I1(plm_fsm_pc_counter3_reg_tx_count[5]), + .I2(plm_fsm_pc_counter3_reg_tx_count[6]), + .I3(plm_fsm_pc_counter3_reg_tx_count[7]), + .O(plm_fsm_pc_counter3_un1_reg_tx_count_0_a2_5) + ); + defparam plm_fsm_pc_counter3_loadable_rx_counter_un1_reg_rx_count_0_a2_4.INIT = 16'h0001; + LUT4 plm_fsm_pc_counter3_loadable_rx_counter_un1_reg_rx_count_0_a2_4 ( + .I0(plm_fsm_pc_counter3_reg_rx_count[0]), + .I1(plm_fsm_pc_counter3_reg_rx_count[1]), + .I2(plm_fsm_pc_counter3_reg_rx_count[2]), + .I3(plm_fsm_pc_counter3_reg_rx_count[3]), + .O(plm_fsm_pc_counter3_un1_reg_rx_count_0_a2_4) + ); + defparam plm_fsm_pc_counter3_loadable_rx_counter_un1_reg_rx_count_0_a2_5.INIT = 16'h0001; + LUT4 plm_fsm_pc_counter3_loadable_rx_counter_un1_reg_rx_count_0_a2_5 ( + .I0(plm_fsm_pc_counter3_reg_rx_count[4]), + .I1(plm_fsm_pc_counter3_reg_rx_count[5]), + .I2(plm_fsm_pc_counter3_reg_rx_count[6]), + .I3(plm_fsm_pc_counter3_reg_rx_count[7]), + .O(plm_fsm_pc_counter3_un1_reg_rx_count_0_a2_5) + ); + defparam plm_fsm_pc_counter3_loadable_rx_counter_un1_rx_ts1_i.INIT = 4'hD; + LUT2 plm_fsm_pc_counter3_loadable_rx_counter_un1_rx_ts1_i ( + .I0(plm_fsm_pc_counter3_un1_enable_0_a2_0_a2_0_a3_0_a2_8), + .I1(plm_fsm_pc_counter3_reg_rx_expired_602), + .O(plm_fsm_pc_counter3_un1_rx_ts1_i) + ); + defparam plm_fsm_pc_counter3_N_87193_i.INIT = 16'h0F2F; + LUT4 plm_fsm_pc_counter3_N_87193_i ( + .I0(plm_reg_ts2_1_2), + .I1(plm_fsm_pc_counter3_reg_rx_expired_602), + .I2(plm_fsm_reg_state_2__599), + .I3(plm_rx3_ts2_c), + .O(plm_fsm_pc_counter3_N_87193_i_1851) + ); + defparam plm_fsm_pc_counter3_N_61026_i.INIT = 4'hB; + LUT2 plm_fsm_pc_counter3_N_61026_i ( + .I0(plm_reg_sym_sent_6_), + .I1(plm_fsm_pc_counter3_un1_enable_1), + .O(plm_fsm_pc_counter3_N_61026_i_1847) + ); + defparam plm_fsm_pc_counter3_un1_enable_2_i.INIT = 8'h8F; + LUT3 plm_fsm_pc_counter3_un1_enable_2_i ( + .I0(plm_fsm_pc_counter3_un1_reg_tx_count_0_a2_4), + .I1(plm_fsm_pc_counter3_un1_reg_tx_count_0_a2_5), + .I2(plm_fsm_pc_counter3_un1_reg_tx_count17), + .O(plm_fsm_pc_counter3_un1_enable_2_i_1849) + ); + defparam plm_fsm_pc_counter3_loadable_rx_counter_N_61027_i.INIT = 8'h8F; + LUT3 plm_fsm_pc_counter3_loadable_rx_counter_N_61027_i ( + .I0(plm_fsm_pc_counter3_un1_reg_rx_count_0_a2_4), + .I1(plm_fsm_pc_counter3_un1_reg_rx_count_0_a2_5), + .I2(plm_fsm_reg_state_2__599), + .O(plm_fsm_pc_counter3_N_61027_i) + ); + defparam plm_fsm_pc_counter3_flagit_reg_expired_5_0_a2_0_a2_0_a3_0_a2.INIT = 8'h80; + LUT3_L plm_fsm_pc_counter3_flagit_reg_expired_5_0_a2_0_a2_0_a3_0_a2 ( + .I0(plm_fsm_pc_counter3_reg_rx_expired_602), + .I1(plm_fsm_pc_counter3_reg_tx_expired_1850), + .I2(plm_fsm_reg_state_2__599), + .LO(plm_fsm_pc_counter3_reg_expired_5) + ); + defparam plm_fsm_pc_counter3_un1_enable_1_0_a3_0_a2_0_a3_0_a2.INIT = 8'h40; + LUT3 plm_fsm_pc_counter3_un1_enable_1_0_a3_0_a2_0_a3_0_a2 ( + .I0(plm_fsm_pc_counter3_reg_tx_expired_1850), + .I1(plm_fsm_reg_state_2__599), + .I2(plm_fsm_pc_counter3_reg_oneshot_1848), + .O(plm_fsm_pc_counter3_un1_enable_1) + ); + defparam plm_fsm_pc_counter3_un1_enable_1_i.INIT = 8'hF7; + LUT3 plm_fsm_pc_counter3_un1_enable_1_i ( + .I0(plm_fsm_pc_counter3_reg_oneshot_1848), + .I1(plm_fsm_reg_state_2__599), + .I2(plm_fsm_pc_counter3_reg_tx_expired_1850), + .O(plm_fsm_pc_counter3_un1_enable_1_i_1846) + ); + FDCE plm_fsm_pc_counter3_reg_tx_count_7_ ( + .CE(plm_fsm_pc_counter3_N_61026_i_1847), + .C(mgt_clk), + .D(plm_fsm_pc_counter3_reg_tx_count_s[7]), + .Q(plm_fsm_pc_counter3_reg_tx_count[7]), + .CLR(plm_rst) + ); + FDCE plm_fsm_pc_counter3_reg_tx_count_6_ ( + .CE(plm_fsm_pc_counter3_N_61026_i_1847), + .C(mgt_clk), + .D(plm_fsm_pc_counter3_reg_tx_count_s[6]), + .Q(plm_fsm_pc_counter3_reg_tx_count[6]), + .CLR(plm_rst) + ); + FDCE plm_fsm_pc_counter3_reg_tx_count_5_ ( + .CE(plm_fsm_pc_counter3_N_61026_i_1847), + .C(mgt_clk), + .D(plm_fsm_pc_counter3_reg_tx_count_s[5]), + .Q(plm_fsm_pc_counter3_reg_tx_count[5]), + .CLR(plm_rst) + ); + FDPE plm_fsm_pc_counter3_reg_tx_count_4_ ( + .PRE(plm_rst), + .CE(plm_fsm_pc_counter3_N_61026_i_1847), + .C(mgt_clk), + .D(plm_fsm_pc_counter3_reg_tx_count_s[4]), + .Q(plm_fsm_pc_counter3_reg_tx_count[4]) + ); + FDCE plm_fsm_pc_counter3_reg_tx_count_3_ ( + .CE(plm_fsm_pc_counter3_N_61026_i_1847), + .C(mgt_clk), + .D(plm_fsm_pc_counter3_reg_tx_count_s[3]), + .Q(plm_fsm_pc_counter3_reg_tx_count[3]), + .CLR(plm_rst) + ); + FDCE plm_fsm_pc_counter3_reg_tx_count_2_ ( + .CE(plm_fsm_pc_counter3_N_61026_i_1847), + .C(mgt_clk), + .D(plm_fsm_pc_counter3_reg_tx_count_s[2]), + .Q(plm_fsm_pc_counter3_reg_tx_count[2]), + .CLR(plm_rst) + ); + FDCE plm_fsm_pc_counter3_reg_tx_count_1_ ( + .CE(plm_fsm_pc_counter3_N_61026_i_1847), + .C(mgt_clk), + .D(plm_fsm_pc_counter3_reg_tx_count_s[1]), + .Q(plm_fsm_pc_counter3_reg_tx_count[1]), + .CLR(plm_rst) + ); + FDCE plm_fsm_pc_counter3_reg_tx_count_0_ ( + .CE(plm_fsm_pc_counter3_N_61026_i_1847), + .C(mgt_clk), + .D(plm_fsm_pc_counter3_reg_tx_count_s[0]), + .Q(plm_fsm_pc_counter3_reg_tx_count[0]), + .CLR(plm_rst) + ); + FDCE plm_fsm_pc_counter3_reg_rx_count_7_ ( + .CE(plm_fsm_pc_counter3_un1_rx_ts1_i), + .C(mgt_clk), + .D(plm_fsm_pc_counter3_reg_rx_count_s[7]), + .Q(plm_fsm_pc_counter3_reg_rx_count[7]), + .CLR(plm_rst) + ); + FDCE plm_fsm_pc_counter3_reg_rx_count_6_ ( + .CE(plm_fsm_pc_counter3_un1_rx_ts1_i), + .C(mgt_clk), + .D(plm_fsm_pc_counter3_reg_rx_count_s[6]), + .Q(plm_fsm_pc_counter3_reg_rx_count[6]), + .CLR(plm_rst) + ); + FDCE plm_fsm_pc_counter3_reg_rx_count_5_ ( + .CE(plm_fsm_pc_counter3_un1_rx_ts1_i), + .C(mgt_clk), + .D(plm_fsm_pc_counter3_reg_rx_count_s[5]), + .Q(plm_fsm_pc_counter3_reg_rx_count[5]), + .CLR(plm_rst) + ); + FDCE plm_fsm_pc_counter3_reg_rx_count_4_ ( + .CE(plm_fsm_pc_counter3_un1_rx_ts1_i), + .C(mgt_clk), + .D(plm_fsm_pc_counter3_reg_rx_count_s[4]), + .Q(plm_fsm_pc_counter3_reg_rx_count[4]), + .CLR(plm_rst) + ); + FDPE plm_fsm_pc_counter3_reg_rx_count_3_ ( + .PRE(plm_rst), + .CE(plm_fsm_pc_counter3_un1_rx_ts1_i), + .C(mgt_clk), + .D(plm_fsm_pc_counter3_reg_rx_count_s[3]), + .Q(plm_fsm_pc_counter3_reg_rx_count[3]) + ); + FDCE plm_fsm_pc_counter3_reg_rx_count_2_ ( + .CE(plm_fsm_pc_counter3_un1_rx_ts1_i), + .C(mgt_clk), + .D(plm_fsm_pc_counter3_reg_rx_count_s[2]), + .Q(plm_fsm_pc_counter3_reg_rx_count[2]), + .CLR(plm_rst) + ); + FDCE plm_fsm_pc_counter3_reg_rx_count_1_ ( + .CE(plm_fsm_pc_counter3_un1_rx_ts1_i), + .C(mgt_clk), + .D(plm_fsm_pc_counter3_reg_rx_count_s[1]), + .Q(plm_fsm_pc_counter3_reg_rx_count[1]), + .CLR(plm_rst) + ); + FDCE plm_fsm_pc_counter3_reg_rx_count_0_ ( + .CE(plm_fsm_pc_counter3_un1_rx_ts1_i), + .C(mgt_clk), + .D(plm_fsm_pc_counter3_reg_rx_count_s[0]), + .Q(plm_fsm_pc_counter3_reg_rx_count[0]), + .CLR(plm_rst) + ); + FDC plm_fsm_pc_counter3_reg_expired ( + .C(mgt_clk), + .D(plm_fsm_pc_counter3_reg_expired_5), + .Q(plm_fsm_pc_cntrout3), + .CLR(plm_rst) + ); + FDCE plm_fsm_pc_counter3_reg_oneshot ( + .CE(plm_fsm_pc_counter3_N_61028_i), + .C(mgt_clk), + .D(plm_fsm_reg_state_2__599), + .Q(plm_fsm_pc_counter3_reg_oneshot_1848), + .CLR(plm_rst) + ); + FDCE plm_fsm_pc_counter3_reg_rx_expired ( + .CE(plm_fsm_pc_counter3_N_61027_i), + .C(mgt_clk), + .D(plm_fsm_reg_state_2__599), + .Q(plm_fsm_pc_counter3_reg_rx_expired_602), + .CLR(plm_rst) + ); + FDCE plm_fsm_pc_counter3_reg_tx_expired ( + .CE(plm_fsm_pc_counter3_un1_enable_2_i_1849), + .C(mgt_clk), + .D(plm_fsm_pc_counter3_un1_reg_tx_count17), + .Q(plm_fsm_pc_counter3_reg_tx_expired_1850), + .CLR(plm_rst) + ); + INV plm_fsm_pc_counter3_oneshot_monitor_N_61028_i ( + .I(plm_fsm_pc_counter3_un1_enable_0_a2_0_a2_0_a3_0_a2_8), + .O(plm_fsm_pc_counter3_N_61028_i) + ); + defparam plm_fsm_pc_counter3_reg_rx_count_qxu_0_0_.INIT = 4'h7; + LUT2_L plm_fsm_pc_counter3_reg_rx_count_qxu_0_0_ ( + .I0(I_5051_0_a2_0_a3_0_a2_36), + .I1(plm_fsm_pc_counter3_reg_rx_count[0]), + .LO(plm_fsm_pc_counter3_reg_rx_count_qxu[0]) + ); + defparam plm_fsm_pc_counter3_reg_rx_count_qxu_0_1_.INIT = 4'h7; + LUT2_L plm_fsm_pc_counter3_reg_rx_count_qxu_0_1_ ( + .I0(I_5051_0_a2_0_a3_0_a2_36), + .I1(plm_fsm_pc_counter3_reg_rx_count[1]), + .LO(plm_fsm_pc_counter3_reg_rx_count_qxu[1]) + ); + defparam plm_fsm_pc_counter3_reg_rx_count_qxu_0_2_.INIT = 4'h7; + LUT2_L plm_fsm_pc_counter3_reg_rx_count_qxu_0_2_ ( + .I0(I_5051_0_a2_0_a3_0_a2_36), + .I1(plm_fsm_pc_counter3_reg_rx_count[2]), + .LO(plm_fsm_pc_counter3_reg_rx_count_qxu[2]) + ); + defparam plm_fsm_pc_counter3_reg_rx_count_qxu_0_3_.INIT = 8'h1B; + LUT3_L plm_fsm_pc_counter3_reg_rx_count_qxu_0_3_ ( + .I0(I_5051_0_a2_0_a3_0_a2_36), + .I1(plm_fsm_pc_counter3_N_87193_i_1851), + .I2(plm_fsm_pc_counter3_reg_rx_count[3]), + .LO(plm_fsm_pc_counter3_reg_rx_count_qxu[3]) + ); + defparam plm_fsm_pc_counter3_reg_rx_count_qxu_0_4_.INIT = 4'h7; + LUT2_L plm_fsm_pc_counter3_reg_rx_count_qxu_0_4_ ( + .I0(I_5051_0_a2_0_a3_0_a2_36), + .I1(plm_fsm_pc_counter3_reg_rx_count[4]), + .LO(plm_fsm_pc_counter3_reg_rx_count_qxu[4]) + ); + defparam plm_fsm_pc_counter3_reg_rx_count_qxu_0_5_.INIT = 4'h7; + LUT2_L plm_fsm_pc_counter3_reg_rx_count_qxu_0_5_ ( + .I0(I_5051_0_a2_0_a3_0_a2_36), + .I1(plm_fsm_pc_counter3_reg_rx_count[5]), + .LO(plm_fsm_pc_counter3_reg_rx_count_qxu[5]) + ); + defparam plm_fsm_pc_counter3_reg_rx_count_qxu_0_6_.INIT = 4'h7; + LUT2_L plm_fsm_pc_counter3_reg_rx_count_qxu_0_6_ ( + .I0(I_5051_0_a2_0_a3_0_a2_36), + .I1(plm_fsm_pc_counter3_reg_rx_count[6]), + .LO(plm_fsm_pc_counter3_reg_rx_count_qxu[6]) + ); + defparam plm_fsm_pc_counter3_reg_rx_count_qxu_0_7_.INIT = 4'h7; + LUT2_L plm_fsm_pc_counter3_reg_rx_count_qxu_0_7_ ( + .I0(I_5051_0_a2_0_a3_0_a2_36), + .I1(plm_fsm_pc_counter3_reg_rx_count[7]), + .LO(plm_fsm_pc_counter3_reg_rx_count_qxu[7]) + ); + defparam plm_fsm_pc_counter3_reg_tx_count_qxu_0_0_.INIT = 4'h7; + LUT2_L plm_fsm_pc_counter3_reg_tx_count_qxu_0_0_ ( + .I0(plm_fsm_pc_counter3_reg_tx_count[0]), + .I1(plm_fsm_pc_counter3_un1_enable_1), + .LO(plm_fsm_pc_counter3_reg_tx_count_qxu[0]) + ); + defparam plm_fsm_pc_counter3_reg_tx_count_qxu_0_1_.INIT = 4'h7; + LUT2_L plm_fsm_pc_counter3_reg_tx_count_qxu_0_1_ ( + .I0(plm_fsm_pc_counter3_reg_tx_count[1]), + .I1(plm_fsm_pc_counter3_un1_enable_1), + .LO(plm_fsm_pc_counter3_reg_tx_count_qxu[1]) + ); + defparam plm_fsm_pc_counter3_reg_tx_count_qxu_0_2_.INIT = 4'h7; + LUT2_L plm_fsm_pc_counter3_reg_tx_count_qxu_0_2_ ( + .I0(plm_fsm_pc_counter3_reg_tx_count[2]), + .I1(plm_fsm_pc_counter3_un1_enable_1), + .LO(plm_fsm_pc_counter3_reg_tx_count_qxu[2]) + ); + defparam plm_fsm_pc_counter3_reg_tx_count_qxu_0_3_.INIT = 4'h7; + LUT2_L plm_fsm_pc_counter3_reg_tx_count_qxu_0_3_ ( + .I0(plm_fsm_pc_counter3_reg_tx_count[3]), + .I1(plm_fsm_pc_counter3_un1_enable_1), + .LO(plm_fsm_pc_counter3_reg_tx_count_qxu[3]) + ); + defparam plm_fsm_pc_counter3_reg_tx_count_qxu_0_4_.INIT = 8'h74; + LUT3_L plm_fsm_pc_counter3_reg_tx_count_qxu_0_4_ ( + .I0(plm_fsm_pc_counter3_reg_tx_count[4]), + .I1(plm_fsm_pc_counter3_un1_enable_1), + .I2(plm_fsm_pc_counter3_un1_reg_tx_count17), + .LO(plm_fsm_pc_counter3_reg_tx_count_qxu[4]) + ); + defparam plm_fsm_pc_counter3_reg_tx_count_qxu_0_5_.INIT = 4'h7; + LUT2_L plm_fsm_pc_counter3_reg_tx_count_qxu_0_5_ ( + .I0(plm_fsm_pc_counter3_reg_tx_count[5]), + .I1(plm_fsm_pc_counter3_un1_enable_1), + .LO(plm_fsm_pc_counter3_reg_tx_count_qxu[5]) + ); + defparam plm_fsm_pc_counter3_reg_tx_count_qxu_0_6_.INIT = 4'h7; + LUT2_L plm_fsm_pc_counter3_reg_tx_count_qxu_0_6_ ( + .I0(plm_fsm_pc_counter3_reg_tx_count[6]), + .I1(plm_fsm_pc_counter3_un1_enable_1), + .LO(plm_fsm_pc_counter3_reg_tx_count_qxu[6]) + ); + defparam plm_fsm_pc_counter3_reg_tx_count_qxu_0_7_.INIT = 4'h7; + LUT2_L plm_fsm_pc_counter3_reg_tx_count_qxu_0_7_ ( + .I0(plm_fsm_pc_counter3_reg_tx_count[7]), + .I1(plm_fsm_pc_counter3_un1_enable_1), + .LO(plm_fsm_pc_counter3_reg_tx_count_qxu[7]) + ); + GND plm_fsm_cls_timer_GND ( + .G(plm_fsm_cls_timer_GND_1852) + ); + MUXCY_L plm_fsm_cls_timer_reg_count_cry_0_ ( + .CI(plm_fsm_N_45455_1_i_1773), + .DI(plm_fsm_cls_timer_GND_1852), + .LO(plm_fsm_cls_timer_reg_count_cry[0]), + .S(plm_fsm_cls_timer_reg_count_qxu[0]) + ); + XORCY plm_fsm_cls_timer_reg_count_s_0_ ( + .CI(plm_fsm_N_45455_1_i_1773), + .LI(plm_fsm_cls_timer_reg_count_qxu[0]), + .O(plm_fsm_cls_timer_reg_count_s[0]) + ); + MUXCY_L plm_fsm_cls_timer_reg_count_cry_1_ ( + .CI(plm_fsm_cls_timer_reg_count_cry[0]), + .DI(plm_fsm_cls_timer_GND_1852), + .LO(plm_fsm_cls_timer_reg_count_cry[1]), + .S(plm_fsm_cls_timer_reg_count_qxu[1]) + ); + XORCY plm_fsm_cls_timer_reg_count_s_1_ ( + .CI(plm_fsm_cls_timer_reg_count_cry[0]), + .LI(plm_fsm_cls_timer_reg_count_qxu[1]), + .O(plm_fsm_cls_timer_reg_count_s[1]) + ); + MUXCY_L plm_fsm_cls_timer_reg_count_cry_2_ ( + .CI(plm_fsm_cls_timer_reg_count_cry[1]), + .DI(plm_fsm_cls_timer_GND_1852), + .LO(plm_fsm_cls_timer_reg_count_cry[2]), + .S(plm_fsm_cls_timer_reg_count_qxu[2]) + ); + XORCY plm_fsm_cls_timer_reg_count_s_2_ ( + .CI(plm_fsm_cls_timer_reg_count_cry[1]), + .LI(plm_fsm_cls_timer_reg_count_qxu[2]), + .O(plm_fsm_cls_timer_reg_count_s[2]) + ); + MUXCY_L plm_fsm_cls_timer_reg_count_cry_3_ ( + .CI(plm_fsm_cls_timer_reg_count_cry[2]), + .DI(plm_fsm_cls_timer_GND_1852), + .LO(plm_fsm_cls_timer_reg_count_cry[3]), + .S(plm_fsm_cls_timer_reg_count_qxu[3]) + ); + XORCY plm_fsm_cls_timer_reg_count_s_3_ ( + .CI(plm_fsm_cls_timer_reg_count_cry[2]), + .LI(plm_fsm_cls_timer_reg_count_qxu[3]), + .O(plm_fsm_cls_timer_reg_count_s[3]) + ); + MUXCY_L plm_fsm_cls_timer_reg_count_cry_4_ ( + .CI(plm_fsm_cls_timer_reg_count_cry[3]), + .DI(plm_fsm_cls_timer_GND_1852), + .LO(plm_fsm_cls_timer_reg_count_cry[4]), + .S(plm_fsm_cls_timer_reg_count_qxu[4]) + ); + XORCY plm_fsm_cls_timer_reg_count_s_4_ ( + .CI(plm_fsm_cls_timer_reg_count_cry[3]), + .LI(plm_fsm_cls_timer_reg_count_qxu[4]), + .O(plm_fsm_cls_timer_reg_count_s[4]) + ); + MUXCY_L plm_fsm_cls_timer_reg_count_cry_5_ ( + .CI(plm_fsm_cls_timer_reg_count_cry[4]), + .DI(plm_fsm_cls_timer_GND_1852), + .LO(plm_fsm_cls_timer_reg_count_cry[5]), + .S(plm_fsm_cls_timer_reg_count_qxu[5]) + ); + XORCY plm_fsm_cls_timer_reg_count_s_5_ ( + .CI(plm_fsm_cls_timer_reg_count_cry[4]), + .LI(plm_fsm_cls_timer_reg_count_qxu[5]), + .O(plm_fsm_cls_timer_reg_count_s[5]) + ); + MUXCY_L plm_fsm_cls_timer_reg_count_cry_6_ ( + .CI(plm_fsm_cls_timer_reg_count_cry[5]), + .DI(plm_fsm_cls_timer_GND_1852), + .LO(plm_fsm_cls_timer_reg_count_cry[6]), + .S(plm_fsm_cls_timer_reg_count_qxu[6]) + ); + XORCY plm_fsm_cls_timer_reg_count_s_6_ ( + .CI(plm_fsm_cls_timer_reg_count_cry[5]), + .LI(plm_fsm_cls_timer_reg_count_qxu[6]), + .O(plm_fsm_cls_timer_reg_count_s[6]) + ); + MUXCY_L plm_fsm_cls_timer_reg_count_cry_7_ ( + .CI(plm_fsm_cls_timer_reg_count_cry[6]), + .DI(plm_fsm_cls_timer_GND_1852), + .LO(plm_fsm_cls_timer_reg_count_cry[7]), + .S(plm_fsm_cls_timer_reg_count_qxu[7]) + ); + XORCY plm_fsm_cls_timer_reg_count_s_7_ ( + .CI(plm_fsm_cls_timer_reg_count_cry[6]), + .LI(plm_fsm_cls_timer_reg_count_qxu[7]), + .O(plm_fsm_cls_timer_reg_count_s[7]) + ); + MUXCY_L plm_fsm_cls_timer_reg_count_cry_8_ ( + .CI(plm_fsm_cls_timer_reg_count_cry[7]), + .DI(plm_fsm_cls_timer_GND_1852), + .LO(plm_fsm_cls_timer_reg_count_cry[8]), + .S(plm_fsm_cls_timer_reg_count_qxu[8]) + ); + XORCY plm_fsm_cls_timer_reg_count_s_8_ ( + .CI(plm_fsm_cls_timer_reg_count_cry[7]), + .LI(plm_fsm_cls_timer_reg_count_qxu[8]), + .O(plm_fsm_cls_timer_reg_count_s[8]) + ); + MUXCY_L plm_fsm_cls_timer_reg_count_cry_9_ ( + .CI(plm_fsm_cls_timer_reg_count_cry[8]), + .DI(plm_fsm_cls_timer_GND_1852), + .LO(plm_fsm_cls_timer_reg_count_cry[9]), + .S(plm_fsm_cls_timer_reg_count_qxu[9]) + ); + XORCY plm_fsm_cls_timer_reg_count_s_9_ ( + .CI(plm_fsm_cls_timer_reg_count_cry[8]), + .LI(plm_fsm_cls_timer_reg_count_qxu[9]), + .O(plm_fsm_cls_timer_reg_count_s[9]) + ); + MUXCY_L plm_fsm_cls_timer_reg_count_cry_10_ ( + .CI(plm_fsm_cls_timer_reg_count_cry[9]), + .DI(plm_fsm_cls_timer_GND_1852), + .LO(plm_fsm_cls_timer_reg_count_cry[10]), + .S(plm_fsm_cls_timer_reg_count_qxu[10]) + ); + XORCY plm_fsm_cls_timer_reg_count_s_10_ ( + .CI(plm_fsm_cls_timer_reg_count_cry[9]), + .LI(plm_fsm_cls_timer_reg_count_qxu[10]), + .O(plm_fsm_cls_timer_reg_count_s[10]) + ); + MUXCY_L plm_fsm_cls_timer_reg_count_cry_11_ ( + .CI(plm_fsm_cls_timer_reg_count_cry[10]), + .DI(plm_fsm_cls_timer_GND_1852), + .LO(plm_fsm_cls_timer_reg_count_cry[11]), + .S(plm_fsm_cls_timer_reg_count_qxu[11]) + ); + XORCY plm_fsm_cls_timer_reg_count_s_11_ ( + .CI(plm_fsm_cls_timer_reg_count_cry[10]), + .LI(plm_fsm_cls_timer_reg_count_qxu[11]), + .O(plm_fsm_cls_timer_reg_count_s[11]) + ); + MUXCY_L plm_fsm_cls_timer_reg_count_cry_12_ ( + .CI(plm_fsm_cls_timer_reg_count_cry[11]), + .DI(plm_fsm_cls_timer_GND_1852), + .LO(plm_fsm_cls_timer_reg_count_cry[12]), + .S(plm_fsm_cls_timer_reg_count_qxu[12]) + ); + XORCY plm_fsm_cls_timer_reg_count_s_12_ ( + .CI(plm_fsm_cls_timer_reg_count_cry[11]), + .LI(plm_fsm_cls_timer_reg_count_qxu[12]), + .O(plm_fsm_cls_timer_reg_count_s[12]) + ); + MUXCY_L plm_fsm_cls_timer_reg_count_cry_13_ ( + .CI(plm_fsm_cls_timer_reg_count_cry[12]), + .DI(plm_fsm_cls_timer_GND_1852), + .LO(plm_fsm_cls_timer_reg_count_cry[13]), + .S(plm_fsm_cls_timer_reg_count_qxu[13]) + ); + XORCY plm_fsm_cls_timer_reg_count_s_13_ ( + .CI(plm_fsm_cls_timer_reg_count_cry[12]), + .LI(plm_fsm_cls_timer_reg_count_qxu[13]), + .O(plm_fsm_cls_timer_reg_count_s[13]) + ); + MUXCY_L plm_fsm_cls_timer_reg_count_cry_14_ ( + .CI(plm_fsm_cls_timer_reg_count_cry[13]), + .DI(plm_fsm_cls_timer_GND_1852), + .LO(plm_fsm_cls_timer_reg_count_cry[14]), + .S(plm_fsm_cls_timer_reg_count_qxu[14]) + ); + XORCY plm_fsm_cls_timer_reg_count_s_14_ ( + .CI(plm_fsm_cls_timer_reg_count_cry[13]), + .LI(plm_fsm_cls_timer_reg_count_qxu[14]), + .O(plm_fsm_cls_timer_reg_count_s[14]) + ); + MUXCY_L plm_fsm_cls_timer_reg_count_cry_15_ ( + .CI(plm_fsm_cls_timer_reg_count_cry[14]), + .DI(plm_fsm_cls_timer_GND_1852), + .LO(plm_fsm_cls_timer_reg_count_cry[15]), + .S(plm_fsm_cls_timer_reg_count_qxu[15]) + ); + XORCY plm_fsm_cls_timer_reg_count_s_15_ ( + .CI(plm_fsm_cls_timer_reg_count_cry[14]), + .LI(plm_fsm_cls_timer_reg_count_qxu[15]), + .O(plm_fsm_cls_timer_reg_count_s[15]) + ); + MUXCY_L plm_fsm_cls_timer_reg_count_cry_16_ ( + .CI(plm_fsm_cls_timer_reg_count_cry[15]), + .DI(plm_fsm_cls_timer_GND_1852), + .LO(plm_fsm_cls_timer_reg_count_cry[16]), + .S(plm_fsm_cls_timer_reg_count_qxu[16]) + ); + XORCY plm_fsm_cls_timer_reg_count_s_16_ ( + .CI(plm_fsm_cls_timer_reg_count_cry[15]), + .LI(plm_fsm_cls_timer_reg_count_qxu[16]), + .O(plm_fsm_cls_timer_reg_count_s[16]) + ); + MUXCY_L plm_fsm_cls_timer_reg_count_cry_17_ ( + .CI(plm_fsm_cls_timer_reg_count_cry[16]), + .DI(plm_fsm_cls_timer_GND_1852), + .LO(plm_fsm_cls_timer_reg_count_cry[17]), + .S(plm_fsm_cls_timer_reg_count_qxu[17]) + ); + XORCY plm_fsm_cls_timer_reg_count_s_17_ ( + .CI(plm_fsm_cls_timer_reg_count_cry[16]), + .LI(plm_fsm_cls_timer_reg_count_qxu[17]), + .O(plm_fsm_cls_timer_reg_count_s[17]) + ); + MUXCY_L plm_fsm_cls_timer_reg_count_cry_18_ ( + .CI(plm_fsm_cls_timer_reg_count_cry[17]), + .DI(plm_fsm_cls_timer_GND_1852), + .LO(plm_fsm_cls_timer_reg_count_cry[18]), + .S(plm_fsm_cls_timer_reg_count_qxu[18]) + ); + XORCY plm_fsm_cls_timer_reg_count_s_18_ ( + .CI(plm_fsm_cls_timer_reg_count_cry[17]), + .LI(plm_fsm_cls_timer_reg_count_qxu[18]), + .O(plm_fsm_cls_timer_reg_count_s[18]) + ); + MUXCY_L plm_fsm_cls_timer_reg_count_cry_19_ ( + .CI(plm_fsm_cls_timer_reg_count_cry[18]), + .DI(plm_fsm_cls_timer_GND_1852), + .LO(plm_fsm_cls_timer_reg_count_cry[19]), + .S(plm_fsm_cls_timer_reg_count_qxu[19]) + ); + XORCY plm_fsm_cls_timer_reg_count_s_19_ ( + .CI(plm_fsm_cls_timer_reg_count_cry[18]), + .LI(plm_fsm_cls_timer_reg_count_qxu[19]), + .O(plm_fsm_cls_timer_reg_count_s[19]) + ); + MUXCY_L plm_fsm_cls_timer_reg_count_cry_20_ ( + .CI(plm_fsm_cls_timer_reg_count_cry[19]), + .DI(plm_fsm_cls_timer_GND_1852), + .LO(plm_fsm_cls_timer_reg_count_cry[20]), + .S(plm_fsm_cls_timer_reg_count_qxu[20]) + ); + XORCY plm_fsm_cls_timer_reg_count_s_20_ ( + .CI(plm_fsm_cls_timer_reg_count_cry[19]), + .LI(plm_fsm_cls_timer_reg_count_qxu[20]), + .O(plm_fsm_cls_timer_reg_count_s[20]) + ); + MUXCY_L plm_fsm_cls_timer_reg_count_cry_21_ ( + .CI(plm_fsm_cls_timer_reg_count_cry[20]), + .DI(plm_fsm_cls_timer_GND_1852), + .LO(plm_fsm_cls_timer_reg_count_cry[21]), + .S(plm_fsm_cls_timer_reg_count_qxu[21]) + ); + XORCY plm_fsm_cls_timer_reg_count_s_21_ ( + .CI(plm_fsm_cls_timer_reg_count_cry[20]), + .LI(plm_fsm_cls_timer_reg_count_qxu[21]), + .O(plm_fsm_cls_timer_reg_count_s[21]) + ); + XORCY plm_fsm_cls_timer_reg_count_s_22_ ( + .CI(plm_fsm_cls_timer_reg_count_cry[21]), + .LI(plm_fsm_cls_timer_reg_count_qxu[22]), + .O(plm_fsm_cls_timer_reg_count_s[22]) + ); + defparam plm_fsm_cls_timer_count_i_m3_i_m3_i_m3_0_20_.INIT = 8'hD8; + LUT3_L plm_fsm_cls_timer_count_i_m3_i_m3_i_m3_0_20_ ( + .I0(cfg_cfg_6102[507]), + .I1(plm_fsm_cls_timer_reg_count[12]), + .I2(plm_fsm_cls_timer_reg_count[20]), + .LO(plm_fsm_cls_timer_N_63732) + ); + defparam plm_fsm_cls_timer_un3_expired_24ms.INIT = 16'hA280; + LUT4_L plm_fsm_cls_timer_un3_expired_24ms ( + .I0(plm_fsm_cls_timer_N_63732), + .I1(cfg_cfg_6102[507]), + .I2(plm_fsm_cls_timer_reg_count[13]), + .I3(plm_fsm_cls_timer_reg_count[21]), + .LO(plm_fsm_cls_timer_N_38051) + ); + defparam plm_fsm_cls_timer_un1_expired_24ms.INIT = 16'h0415; + LUT4 plm_fsm_cls_timer_un1_expired_24ms ( + .I0(plm_fsm_cls_timer_N_38051), + .I1(cfg_cfg_6102[507]), + .I2(plm_fsm_cls_timer_reg_count[14]), + .I3(plm_fsm_cls_timer_reg_count[22]), + .O(plm_fsm_N_38052) + ); + defparam plm_fsm_cls_timer_expired.INIT = 4'h1; + LUT2 plm_fsm_cls_timer_expired ( + .I0(plm_fsm_N_38052), + .I1(plm_fsm_N_45455_1), + .O(plm_fsm_cls_timeout) + ); + FDC plm_fsm_cls_timer_reg_count_22_ ( + .C(mgt_clk), + .D(plm_fsm_cls_timer_reg_count_s[22]), + .Q(plm_fsm_cls_timer_reg_count[22]), + .CLR(plm_rst) + ); + FDC plm_fsm_cls_timer_reg_count_21_ ( + .C(mgt_clk), + .D(plm_fsm_cls_timer_reg_count_s[21]), + .Q(plm_fsm_cls_timer_reg_count[21]), + .CLR(plm_rst) + ); + FDC plm_fsm_cls_timer_reg_count_20_ ( + .C(mgt_clk), + .D(plm_fsm_cls_timer_reg_count_s[20]), + .Q(plm_fsm_cls_timer_reg_count[20]), + .CLR(plm_rst) + ); + FDC plm_fsm_cls_timer_reg_count_19_ ( + .C(mgt_clk), + .D(plm_fsm_cls_timer_reg_count_s[19]), + .Q(plm_fsm_cls_timer_reg_count[19]), + .CLR(plm_rst) + ); + FDC plm_fsm_cls_timer_reg_count_18_ ( + .C(mgt_clk), + .D(plm_fsm_cls_timer_reg_count_s[18]), + .Q(plm_fsm_cls_timer_reg_count[18]), + .CLR(plm_rst) + ); + FDC plm_fsm_cls_timer_reg_count_17_ ( + .C(mgt_clk), + .D(plm_fsm_cls_timer_reg_count_s[17]), + .Q(plm_fsm_cls_timer_reg_count[17]), + .CLR(plm_rst) + ); + FDC plm_fsm_cls_timer_reg_count_16_ ( + .C(mgt_clk), + .D(plm_fsm_cls_timer_reg_count_s[16]), + .Q(plm_fsm_cls_timer_reg_count[16]), + .CLR(plm_rst) + ); + FDC plm_fsm_cls_timer_reg_count_15_ ( + .C(mgt_clk), + .D(plm_fsm_cls_timer_reg_count_s[15]), + .Q(plm_fsm_cls_timer_reg_count[15]), + .CLR(plm_rst) + ); + FDC plm_fsm_cls_timer_reg_count_14_ ( + .C(mgt_clk), + .D(plm_fsm_cls_timer_reg_count_s[14]), + .Q(plm_fsm_cls_timer_reg_count[14]), + .CLR(plm_rst) + ); + FDC plm_fsm_cls_timer_reg_count_13_ ( + .C(mgt_clk), + .D(plm_fsm_cls_timer_reg_count_s[13]), + .Q(plm_fsm_cls_timer_reg_count[13]), + .CLR(plm_rst) + ); + FDC plm_fsm_cls_timer_reg_count_12_ ( + .C(mgt_clk), + .D(plm_fsm_cls_timer_reg_count_s[12]), + .Q(plm_fsm_cls_timer_reg_count[12]), + .CLR(plm_rst) + ); + FDC plm_fsm_cls_timer_reg_count_11_ ( + .C(mgt_clk), + .D(plm_fsm_cls_timer_reg_count_s[11]), + .Q(plm_fsm_cls_timer_reg_count[11]), + .CLR(plm_rst) + ); + FDC plm_fsm_cls_timer_reg_count_10_ ( + .C(mgt_clk), + .D(plm_fsm_cls_timer_reg_count_s[10]), + .Q(plm_fsm_cls_timer_reg_count[10]), + .CLR(plm_rst) + ); + FDC plm_fsm_cls_timer_reg_count_9_ ( + .C(mgt_clk), + .D(plm_fsm_cls_timer_reg_count_s[9]), + .Q(plm_fsm_cls_timer_reg_count[9]), + .CLR(plm_rst) + ); + FDC plm_fsm_cls_timer_reg_count_8_ ( + .C(mgt_clk), + .D(plm_fsm_cls_timer_reg_count_s[8]), + .Q(plm_fsm_cls_timer_reg_count[8]), + .CLR(plm_rst) + ); + FDC plm_fsm_cls_timer_reg_count_7_ ( + .C(mgt_clk), + .D(plm_fsm_cls_timer_reg_count_s[7]), + .Q(plm_fsm_cls_timer_reg_count[7]), + .CLR(plm_rst) + ); + FDC plm_fsm_cls_timer_reg_count_6_ ( + .C(mgt_clk), + .D(plm_fsm_cls_timer_reg_count_s[6]), + .Q(plm_fsm_cls_timer_reg_count[6]), + .CLR(plm_rst) + ); + FDC plm_fsm_cls_timer_reg_count_5_ ( + .C(mgt_clk), + .D(plm_fsm_cls_timer_reg_count_s[5]), + .Q(plm_fsm_cls_timer_reg_count[5]), + .CLR(plm_rst) + ); + FDC plm_fsm_cls_timer_reg_count_4_ ( + .C(mgt_clk), + .D(plm_fsm_cls_timer_reg_count_s[4]), + .Q(plm_fsm_cls_timer_reg_count[4]), + .CLR(plm_rst) + ); + FDC plm_fsm_cls_timer_reg_count_3_ ( + .C(mgt_clk), + .D(plm_fsm_cls_timer_reg_count_s[3]), + .Q(plm_fsm_cls_timer_reg_count[3]), + .CLR(plm_rst) + ); + FDC plm_fsm_cls_timer_reg_count_2_ ( + .C(mgt_clk), + .D(plm_fsm_cls_timer_reg_count_s[2]), + .Q(plm_fsm_cls_timer_reg_count[2]), + .CLR(plm_rst) + ); + FDC plm_fsm_cls_timer_reg_count_1_ ( + .C(mgt_clk), + .D(plm_fsm_cls_timer_reg_count_s[1]), + .Q(plm_fsm_cls_timer_reg_count[1]), + .CLR(plm_rst) + ); + FDC plm_fsm_cls_timer_reg_count_0_ ( + .C(mgt_clk), + .D(plm_fsm_cls_timer_reg_count_s[0]), + .Q(plm_fsm_cls_timer_reg_count[0]), + .CLR(plm_rst) + ); + defparam plm_fsm_cls_timer_reg_count_qxu_0_0_.INIT = 4'h4; + LUT2_L plm_fsm_cls_timer_reg_count_qxu_0_0_ ( + .I0(plm_fsm_N_45455_1), + .I1(plm_fsm_cls_timer_reg_count[0]), + .LO(plm_fsm_cls_timer_reg_count_qxu[0]) + ); + defparam plm_fsm_cls_timer_reg_count_qxu_0_1_.INIT = 4'h4; + LUT2_L plm_fsm_cls_timer_reg_count_qxu_0_1_ ( + .I0(plm_fsm_N_45455_1), + .I1(plm_fsm_cls_timer_reg_count[1]), + .LO(plm_fsm_cls_timer_reg_count_qxu[1]) + ); + defparam plm_fsm_cls_timer_reg_count_qxu_0_2_.INIT = 4'h4; + LUT2_L plm_fsm_cls_timer_reg_count_qxu_0_2_ ( + .I0(plm_fsm_N_45455_1), + .I1(plm_fsm_cls_timer_reg_count[2]), + .LO(plm_fsm_cls_timer_reg_count_qxu[2]) + ); + defparam plm_fsm_cls_timer_reg_count_qxu_0_3_.INIT = 4'h4; + LUT2_L plm_fsm_cls_timer_reg_count_qxu_0_3_ ( + .I0(plm_fsm_N_45455_1), + .I1(plm_fsm_cls_timer_reg_count[3]), + .LO(plm_fsm_cls_timer_reg_count_qxu[3]) + ); + defparam plm_fsm_cls_timer_reg_count_qxu_0_4_.INIT = 4'h4; + LUT2_L plm_fsm_cls_timer_reg_count_qxu_0_4_ ( + .I0(plm_fsm_N_45455_1), + .I1(plm_fsm_cls_timer_reg_count[4]), + .LO(plm_fsm_cls_timer_reg_count_qxu[4]) + ); + defparam plm_fsm_cls_timer_reg_count_qxu_0_5_.INIT = 4'h4; + LUT2_L plm_fsm_cls_timer_reg_count_qxu_0_5_ ( + .I0(plm_fsm_N_45455_1), + .I1(plm_fsm_cls_timer_reg_count[5]), + .LO(plm_fsm_cls_timer_reg_count_qxu[5]) + ); + defparam plm_fsm_cls_timer_reg_count_qxu_0_6_.INIT = 4'h4; + LUT2_L plm_fsm_cls_timer_reg_count_qxu_0_6_ ( + .I0(plm_fsm_N_45455_1), + .I1(plm_fsm_cls_timer_reg_count[6]), + .LO(plm_fsm_cls_timer_reg_count_qxu[6]) + ); + defparam plm_fsm_cls_timer_reg_count_qxu_0_7_.INIT = 4'h4; + LUT2_L plm_fsm_cls_timer_reg_count_qxu_0_7_ ( + .I0(plm_fsm_N_45455_1), + .I1(plm_fsm_cls_timer_reg_count[7]), + .LO(plm_fsm_cls_timer_reg_count_qxu[7]) + ); + defparam plm_fsm_cls_timer_reg_count_qxu_0_8_.INIT = 4'h4; + LUT2_L plm_fsm_cls_timer_reg_count_qxu_0_8_ ( + .I0(plm_fsm_N_45455_1), + .I1(plm_fsm_cls_timer_reg_count[8]), + .LO(plm_fsm_cls_timer_reg_count_qxu[8]) + ); + defparam plm_fsm_cls_timer_reg_count_qxu_0_9_.INIT = 4'h4; + LUT2_L plm_fsm_cls_timer_reg_count_qxu_0_9_ ( + .I0(plm_fsm_N_45455_1), + .I1(plm_fsm_cls_timer_reg_count[9]), + .LO(plm_fsm_cls_timer_reg_count_qxu[9]) + ); + defparam plm_fsm_cls_timer_reg_count_qxu_0_10_.INIT = 4'h4; + LUT2_L plm_fsm_cls_timer_reg_count_qxu_0_10_ ( + .I0(plm_fsm_N_45455_1), + .I1(plm_fsm_cls_timer_reg_count[10]), + .LO(plm_fsm_cls_timer_reg_count_qxu[10]) + ); + defparam plm_fsm_cls_timer_reg_count_qxu_0_11_.INIT = 4'h4; + LUT2_L plm_fsm_cls_timer_reg_count_qxu_0_11_ ( + .I0(plm_fsm_N_45455_1), + .I1(plm_fsm_cls_timer_reg_count[11]), + .LO(plm_fsm_cls_timer_reg_count_qxu[11]) + ); + defparam plm_fsm_cls_timer_reg_count_qxu_0_12_.INIT = 4'h4; + LUT2_L plm_fsm_cls_timer_reg_count_qxu_0_12_ ( + .I0(plm_fsm_N_45455_1), + .I1(plm_fsm_cls_timer_reg_count[12]), + .LO(plm_fsm_cls_timer_reg_count_qxu[12]) + ); + defparam plm_fsm_cls_timer_reg_count_qxu_0_13_.INIT = 4'h4; + LUT2_L plm_fsm_cls_timer_reg_count_qxu_0_13_ ( + .I0(plm_fsm_N_45455_1), + .I1(plm_fsm_cls_timer_reg_count[13]), + .LO(plm_fsm_cls_timer_reg_count_qxu[13]) + ); + defparam plm_fsm_cls_timer_reg_count_qxu_0_14_.INIT = 4'h4; + LUT2_L plm_fsm_cls_timer_reg_count_qxu_0_14_ ( + .I0(plm_fsm_N_45455_1), + .I1(plm_fsm_cls_timer_reg_count[14]), + .LO(plm_fsm_cls_timer_reg_count_qxu[14]) + ); + defparam plm_fsm_cls_timer_reg_count_qxu_0_15_.INIT = 4'h4; + LUT2_L plm_fsm_cls_timer_reg_count_qxu_0_15_ ( + .I0(plm_fsm_N_45455_1), + .I1(plm_fsm_cls_timer_reg_count[15]), + .LO(plm_fsm_cls_timer_reg_count_qxu[15]) + ); + defparam plm_fsm_cls_timer_reg_count_qxu_0_16_.INIT = 4'h4; + LUT2_L plm_fsm_cls_timer_reg_count_qxu_0_16_ ( + .I0(plm_fsm_N_45455_1), + .I1(plm_fsm_cls_timer_reg_count[16]), + .LO(plm_fsm_cls_timer_reg_count_qxu[16]) + ); + defparam plm_fsm_cls_timer_reg_count_qxu_0_17_.INIT = 4'h4; + LUT2_L plm_fsm_cls_timer_reg_count_qxu_0_17_ ( + .I0(plm_fsm_N_45455_1), + .I1(plm_fsm_cls_timer_reg_count[17]), + .LO(plm_fsm_cls_timer_reg_count_qxu[17]) + ); + defparam plm_fsm_cls_timer_reg_count_qxu_0_18_.INIT = 4'h4; + LUT2_L plm_fsm_cls_timer_reg_count_qxu_0_18_ ( + .I0(plm_fsm_N_45455_1), + .I1(plm_fsm_cls_timer_reg_count[18]), + .LO(plm_fsm_cls_timer_reg_count_qxu[18]) + ); + defparam plm_fsm_cls_timer_reg_count_qxu_0_19_.INIT = 4'h4; + LUT2_L plm_fsm_cls_timer_reg_count_qxu_0_19_ ( + .I0(plm_fsm_N_45455_1), + .I1(plm_fsm_cls_timer_reg_count[19]), + .LO(plm_fsm_cls_timer_reg_count_qxu[19]) + ); + defparam plm_fsm_cls_timer_reg_count_qxu_0_20_.INIT = 4'h4; + LUT2_L plm_fsm_cls_timer_reg_count_qxu_0_20_ ( + .I0(plm_fsm_N_45455_1), + .I1(plm_fsm_cls_timer_reg_count[20]), + .LO(plm_fsm_cls_timer_reg_count_qxu[20]) + ); + defparam plm_fsm_cls_timer_reg_count_qxu_0_21_.INIT = 4'h4; + LUT2_L plm_fsm_cls_timer_reg_count_qxu_0_21_ ( + .I0(plm_fsm_N_45455_1), + .I1(plm_fsm_cls_timer_reg_count[21]), + .LO(plm_fsm_cls_timer_reg_count_qxu[21]) + ); + defparam plm_fsm_cls_timer_reg_count_qxu_0_22_.INIT = 4'h4; + LUT2_L plm_fsm_cls_timer_reg_count_qxu_0_22_ ( + .I0(plm_fsm_N_45455_1), + .I1(plm_fsm_cls_timer_reg_count[22]), + .LO(plm_fsm_cls_timer_reg_count_qxu[22]) + ); + GND plm_fsm_cla_timer_GND ( + .G(plm_fsm_cla_timer_GND_1853) + ); + MUXCY_L plm_fsm_cla_timer_reg_count_cry_0_ ( + .CI(plm_fsm_cla_timer_un1_reg_state_1_i_i_1855), + .DI(plm_fsm_cla_timer_GND_1853), + .LO(plm_fsm_cla_timer_reg_count_cry[0]), + .S(plm_fsm_cla_timer_reg_count_qxu[0]) + ); + XORCY plm_fsm_cla_timer_reg_count_s_0_ ( + .CI(plm_fsm_cla_timer_un1_reg_state_1_i_i_1855), + .LI(plm_fsm_cla_timer_reg_count_qxu[0]), + .O(plm_fsm_cla_timer_reg_count_s[0]) + ); + MUXCY_L plm_fsm_cla_timer_reg_count_cry_1_ ( + .CI(plm_fsm_cla_timer_reg_count_cry[0]), + .DI(plm_fsm_cla_timer_GND_1853), + .LO(plm_fsm_cla_timer_reg_count_cry[1]), + .S(plm_fsm_cla_timer_reg_count_qxu[1]) + ); + XORCY plm_fsm_cla_timer_reg_count_s_1_ ( + .CI(plm_fsm_cla_timer_reg_count_cry[0]), + .LI(plm_fsm_cla_timer_reg_count_qxu[1]), + .O(plm_fsm_cla_timer_reg_count_s[1]) + ); + MUXCY_L plm_fsm_cla_timer_reg_count_cry_2_ ( + .CI(plm_fsm_cla_timer_reg_count_cry[1]), + .DI(plm_fsm_cla_timer_GND_1853), + .LO(plm_fsm_cla_timer_reg_count_cry[2]), + .S(plm_fsm_cla_timer_reg_count_qxu[2]) + ); + XORCY plm_fsm_cla_timer_reg_count_s_2_ ( + .CI(plm_fsm_cla_timer_reg_count_cry[1]), + .LI(plm_fsm_cla_timer_reg_count_qxu[2]), + .O(plm_fsm_cla_timer_reg_count_s[2]) + ); + MUXCY_L plm_fsm_cla_timer_reg_count_cry_3_ ( + .CI(plm_fsm_cla_timer_reg_count_cry[2]), + .DI(plm_fsm_cla_timer_GND_1853), + .LO(plm_fsm_cla_timer_reg_count_cry[3]), + .S(plm_fsm_cla_timer_reg_count_qxu[3]) + ); + XORCY plm_fsm_cla_timer_reg_count_s_3_ ( + .CI(plm_fsm_cla_timer_reg_count_cry[2]), + .LI(plm_fsm_cla_timer_reg_count_qxu[3]), + .O(plm_fsm_cla_timer_reg_count_s[3]) + ); + MUXCY_L plm_fsm_cla_timer_reg_count_cry_4_ ( + .CI(plm_fsm_cla_timer_reg_count_cry[3]), + .DI(plm_fsm_cla_timer_GND_1853), + .LO(plm_fsm_cla_timer_reg_count_cry[4]), + .S(plm_fsm_cla_timer_reg_count_qxu[4]) + ); + XORCY plm_fsm_cla_timer_reg_count_s_4_ ( + .CI(plm_fsm_cla_timer_reg_count_cry[3]), + .LI(plm_fsm_cla_timer_reg_count_qxu[4]), + .O(plm_fsm_cla_timer_reg_count_s[4]) + ); + MUXCY_L plm_fsm_cla_timer_reg_count_cry_5_ ( + .CI(plm_fsm_cla_timer_reg_count_cry[4]), + .DI(plm_fsm_cla_timer_GND_1853), + .LO(plm_fsm_cla_timer_reg_count_cry[5]), + .S(plm_fsm_cla_timer_reg_count_qxu[5]) + ); + XORCY plm_fsm_cla_timer_reg_count_s_5_ ( + .CI(plm_fsm_cla_timer_reg_count_cry[4]), + .LI(plm_fsm_cla_timer_reg_count_qxu[5]), + .O(plm_fsm_cla_timer_reg_count_s[5]) + ); + MUXCY_L plm_fsm_cla_timer_reg_count_cry_6_ ( + .CI(plm_fsm_cla_timer_reg_count_cry[5]), + .DI(plm_fsm_cla_timer_GND_1853), + .LO(plm_fsm_cla_timer_reg_count_cry[6]), + .S(plm_fsm_cla_timer_reg_count_qxu[6]) + ); + XORCY plm_fsm_cla_timer_reg_count_s_6_ ( + .CI(plm_fsm_cla_timer_reg_count_cry[5]), + .LI(plm_fsm_cla_timer_reg_count_qxu[6]), + .O(plm_fsm_cla_timer_reg_count_s[6]) + ); + MUXCY_L plm_fsm_cla_timer_reg_count_cry_7_ ( + .CI(plm_fsm_cla_timer_reg_count_cry[6]), + .DI(plm_fsm_cla_timer_GND_1853), + .LO(plm_fsm_cla_timer_reg_count_cry[7]), + .S(plm_fsm_cla_timer_reg_count_qxu[7]) + ); + XORCY plm_fsm_cla_timer_reg_count_s_7_ ( + .CI(plm_fsm_cla_timer_reg_count_cry[6]), + .LI(plm_fsm_cla_timer_reg_count_qxu[7]), + .O(plm_fsm_cla_timer_reg_count_s[7]) + ); + MUXCY_L plm_fsm_cla_timer_reg_count_cry_8_ ( + .CI(plm_fsm_cla_timer_reg_count_cry[7]), + .DI(plm_fsm_cla_timer_GND_1853), + .LO(plm_fsm_cla_timer_reg_count_cry[8]), + .S(plm_fsm_cla_timer_reg_count_qxu[8]) + ); + XORCY plm_fsm_cla_timer_reg_count_s_8_ ( + .CI(plm_fsm_cla_timer_reg_count_cry[7]), + .LI(plm_fsm_cla_timer_reg_count_qxu[8]), + .O(plm_fsm_cla_timer_reg_count_s[8]) + ); + MUXCY_L plm_fsm_cla_timer_reg_count_cry_9_ ( + .CI(plm_fsm_cla_timer_reg_count_cry[8]), + .DI(plm_fsm_cla_timer_GND_1853), + .LO(plm_fsm_cla_timer_reg_count_cry[9]), + .S(plm_fsm_cla_timer_reg_count_qxu[9]) + ); + XORCY plm_fsm_cla_timer_reg_count_s_9_ ( + .CI(plm_fsm_cla_timer_reg_count_cry[8]), + .LI(plm_fsm_cla_timer_reg_count_qxu[9]), + .O(plm_fsm_cla_timer_reg_count_s[9]) + ); + MUXCY_L plm_fsm_cla_timer_reg_count_cry_10_ ( + .CI(plm_fsm_cla_timer_reg_count_cry[9]), + .DI(plm_fsm_cla_timer_GND_1853), + .LO(plm_fsm_cla_timer_reg_count_cry[10]), + .S(plm_fsm_cla_timer_reg_count_qxu[10]) + ); + XORCY plm_fsm_cla_timer_reg_count_s_10_ ( + .CI(plm_fsm_cla_timer_reg_count_cry[9]), + .LI(plm_fsm_cla_timer_reg_count_qxu[10]), + .O(plm_fsm_cla_timer_reg_count_s[10]) + ); + MUXCY_L plm_fsm_cla_timer_reg_count_cry_11_ ( + .CI(plm_fsm_cla_timer_reg_count_cry[10]), + .DI(plm_fsm_cla_timer_GND_1853), + .LO(plm_fsm_cla_timer_reg_count_cry[11]), + .S(plm_fsm_cla_timer_reg_count_qxu[11]) + ); + XORCY plm_fsm_cla_timer_reg_count_s_11_ ( + .CI(plm_fsm_cla_timer_reg_count_cry[10]), + .LI(plm_fsm_cla_timer_reg_count_qxu[11]), + .O(plm_fsm_cla_timer_reg_count_s[11]) + ); + MUXCY_L plm_fsm_cla_timer_reg_count_cry_12_ ( + .CI(plm_fsm_cla_timer_reg_count_cry[11]), + .DI(plm_fsm_cla_timer_GND_1853), + .LO(plm_fsm_cla_timer_reg_count_cry[12]), + .S(plm_fsm_cla_timer_reg_count_qxu[12]) + ); + XORCY plm_fsm_cla_timer_reg_count_s_12_ ( + .CI(plm_fsm_cla_timer_reg_count_cry[11]), + .LI(plm_fsm_cla_timer_reg_count_qxu[12]), + .O(plm_fsm_cla_timer_reg_count_s[12]) + ); + MUXCY_L plm_fsm_cla_timer_reg_count_cry_13_ ( + .CI(plm_fsm_cla_timer_reg_count_cry[12]), + .DI(plm_fsm_cla_timer_GND_1853), + .LO(plm_fsm_cla_timer_reg_count_cry[13]), + .S(plm_fsm_cla_timer_reg_count_qxu[13]) + ); + XORCY plm_fsm_cla_timer_reg_count_s_13_ ( + .CI(plm_fsm_cla_timer_reg_count_cry[12]), + .LI(plm_fsm_cla_timer_reg_count_qxu[13]), + .O(plm_fsm_cla_timer_reg_count_s[13]) + ); + MUXCY_L plm_fsm_cla_timer_reg_count_cry_14_ ( + .CI(plm_fsm_cla_timer_reg_count_cry[13]), + .DI(plm_fsm_cla_timer_GND_1853), + .LO(plm_fsm_cla_timer_reg_count_cry[14]), + .S(plm_fsm_cla_timer_reg_count_qxu[14]) + ); + XORCY plm_fsm_cla_timer_reg_count_s_14_ ( + .CI(plm_fsm_cla_timer_reg_count_cry[13]), + .LI(plm_fsm_cla_timer_reg_count_qxu[14]), + .O(plm_fsm_cla_timer_reg_count_s[14]) + ); + MUXCY_L plm_fsm_cla_timer_reg_count_cry_15_ ( + .CI(plm_fsm_cla_timer_reg_count_cry[14]), + .DI(plm_fsm_cla_timer_GND_1853), + .LO(plm_fsm_cla_timer_reg_count_cry[15]), + .S(plm_fsm_cla_timer_reg_count_qxu[15]) + ); + XORCY plm_fsm_cla_timer_reg_count_s_15_ ( + .CI(plm_fsm_cla_timer_reg_count_cry[14]), + .LI(plm_fsm_cla_timer_reg_count_qxu[15]), + .O(plm_fsm_cla_timer_reg_count_s[15]) + ); + MUXCY_L plm_fsm_cla_timer_reg_count_cry_16_ ( + .CI(plm_fsm_cla_timer_reg_count_cry[15]), + .DI(plm_fsm_cla_timer_GND_1853), + .LO(plm_fsm_cla_timer_reg_count_cry[16]), + .S(plm_fsm_cla_timer_reg_count_qxu[16]) + ); + XORCY plm_fsm_cla_timer_reg_count_s_16_ ( + .CI(plm_fsm_cla_timer_reg_count_cry[15]), + .LI(plm_fsm_cla_timer_reg_count_qxu[16]), + .O(plm_fsm_cla_timer_reg_count_s[16]) + ); + MUXCY_L plm_fsm_cla_timer_reg_count_cry_17_ ( + .CI(plm_fsm_cla_timer_reg_count_cry[16]), + .DI(plm_fsm_cla_timer_GND_1853), + .LO(plm_fsm_cla_timer_reg_count_cry[17]), + .S(plm_fsm_cla_timer_reg_count_qxu[17]) + ); + XORCY plm_fsm_cla_timer_reg_count_s_17_ ( + .CI(plm_fsm_cla_timer_reg_count_cry[16]), + .LI(plm_fsm_cla_timer_reg_count_qxu[17]), + .O(plm_fsm_cla_timer_reg_count_s[17]) + ); + MUXCY_L plm_fsm_cla_timer_reg_count_cry_18_ ( + .CI(plm_fsm_cla_timer_reg_count_cry[17]), + .DI(plm_fsm_cla_timer_GND_1853), + .LO(plm_fsm_cla_timer_reg_count_cry[18]), + .S(plm_fsm_cla_timer_reg_count_qxu[18]) + ); + XORCY plm_fsm_cla_timer_reg_count_s_18_ ( + .CI(plm_fsm_cla_timer_reg_count_cry[17]), + .LI(plm_fsm_cla_timer_reg_count_qxu[18]), + .O(plm_fsm_cla_timer_reg_count_s[18]) + ); + MUXCY_L plm_fsm_cla_timer_reg_count_cry_19_ ( + .CI(plm_fsm_cla_timer_reg_count_cry[18]), + .DI(plm_fsm_cla_timer_GND_1853), + .LO(plm_fsm_cla_timer_reg_count_cry[19]), + .S(plm_fsm_cla_timer_reg_count_qxu[19]) + ); + XORCY plm_fsm_cla_timer_reg_count_s_19_ ( + .CI(plm_fsm_cla_timer_reg_count_cry[18]), + .LI(plm_fsm_cla_timer_reg_count_qxu[19]), + .O(plm_fsm_cla_timer_reg_count_s[19]) + ); + MUXCY_L plm_fsm_cla_timer_reg_count_cry_20_ ( + .CI(plm_fsm_cla_timer_reg_count_cry[19]), + .DI(plm_fsm_cla_timer_GND_1853), + .LO(plm_fsm_cla_timer_reg_count_cry[20]), + .S(plm_fsm_cla_timer_reg_count_qxu[20]) + ); + XORCY plm_fsm_cla_timer_reg_count_s_20_ ( + .CI(plm_fsm_cla_timer_reg_count_cry[19]), + .LI(plm_fsm_cla_timer_reg_count_qxu[20]), + .O(plm_fsm_cla_timer_reg_count_s[20]) + ); + MUXCY_L plm_fsm_cla_timer_reg_count_cry_21_ ( + .CI(plm_fsm_cla_timer_reg_count_cry[20]), + .DI(plm_fsm_cla_timer_GND_1853), + .LO(plm_fsm_cla_timer_reg_count_cry[21]), + .S(plm_fsm_cla_timer_reg_count_qxu[21]) + ); + XORCY plm_fsm_cla_timer_reg_count_s_21_ ( + .CI(plm_fsm_cla_timer_reg_count_cry[20]), + .LI(plm_fsm_cla_timer_reg_count_qxu[21]), + .O(plm_fsm_cla_timer_reg_count_s[21]) + ); + XORCY plm_fsm_cla_timer_reg_count_s_22_ ( + .CI(plm_fsm_cla_timer_reg_count_cry[21]), + .LI(plm_fsm_cla_timer_reg_count_qxu[22]), + .O(plm_fsm_cla_timer_reg_count_s[22]) + ); + defparam plm_fsm_cla_timer_count_i_m3_i_m3_i_m3_0_22_.INIT = 8'hD8; + LUT3_L plm_fsm_cla_timer_count_i_m3_i_m3_i_m3_0_22_ ( + .I0(cfg_cfg_6102[507]), + .I1(plm_fsm_cla_timer_reg_count[14]), + .I2(plm_fsm_cla_timer_reg_count[22]), + .LO(plm_fsm_cla_timer_N_63731) + ); + defparam plm_fsm_cla_timer_count_i_m3_i_m3_i_m3_i_m3_0_18_.INIT = 8'hD8; + LUT3 plm_fsm_cla_timer_count_i_m3_i_m3_i_m3_i_m3_0_18_ ( + .I0(cfg_cfg_6102[507]), + .I1(plm_fsm_cla_timer_reg_count[10]), + .I2(plm_fsm_cla_timer_reg_count[18]), + .O(plm_fsm_cla_timer_N_63740) + ); + defparam plm_fsm_cla_timer_count_i_m3_i_m3_i_m3_i_m3_0_20_.INIT = 8'hD8; + LUT3 plm_fsm_cla_timer_count_i_m3_i_m3_i_m3_i_m3_0_20_ ( + .I0(cfg_cfg_6102[507]), + .I1(plm_fsm_cla_timer_reg_count[12]), + .I2(plm_fsm_cla_timer_reg_count[20]), + .O(plm_fsm_cla_timer_N_63742) + ); + defparam plm_fsm_cla_timer_count_i_m3_i_m3_i_m3_0_21_.INIT = 8'hD8; + LUT3 plm_fsm_cla_timer_count_i_m3_i_m3_i_m3_0_21_ ( + .I0(cfg_cfg_6102[507]), + .I1(plm_fsm_cla_timer_reg_count[13]), + .I2(plm_fsm_cla_timer_reg_count[21]), + .O(plm_fsm_cla_timer_N_63730) + ); + defparam plm_fsm_cla_timer_un1_reg_state_1_i_i.INIT = 4'hE; + LUT2 plm_fsm_cla_timer_un1_reg_state_1_i_i ( + .I0(plm_fsm_reg_state_5__1779), + .I1(plm_fsm_reg_state_6__1778), + .O(plm_fsm_cla_timer_un1_reg_state_1_i_i_1855) + ); + defparam plm_fsm_cla_timer_un1_expired_2ms_0_a2_0_a3_0.INIT = 16'h0415; + LUT4_L plm_fsm_cla_timer_un1_expired_2ms_0_a2_0_a3_0 ( + .I0(plm_fsm_cla_timer_N_63731), + .I1(cfg_cfg_6102[507]), + .I2(plm_fsm_cla_timer_reg_count[11]), + .I3(plm_fsm_cla_timer_reg_count[19]), + .LO(plm_fsm_cla_timer_un1_expired_2ms_0_a2_0_a3_0_1854) + ); + defparam plm_fsm_cla_timer_un1_expired_2ms_0_a2_0_a3.INIT = 16'h0100; + LUT4 plm_fsm_cla_timer_un1_expired_2ms_0_a2_0_a3 ( + .I0(plm_fsm_cla_timer_N_63730), + .I1(plm_fsm_cla_timer_N_63740), + .I2(plm_fsm_cla_timer_N_63742), + .I3(plm_fsm_cla_timer_un1_expired_2ms_0_a2_0_a3_0_1854), + .O(plm_fsm_N_63481) + ); + FDC plm_fsm_cla_timer_reg_count_22_ ( + .C(mgt_clk), + .D(plm_fsm_cla_timer_reg_count_s[22]), + .Q(plm_fsm_cla_timer_reg_count[22]), + .CLR(plm_rst) + ); + FDC plm_fsm_cla_timer_reg_count_21_ ( + .C(mgt_clk), + .D(plm_fsm_cla_timer_reg_count_s[21]), + .Q(plm_fsm_cla_timer_reg_count[21]), + .CLR(plm_rst) + ); + FDC plm_fsm_cla_timer_reg_count_20_ ( + .C(mgt_clk), + .D(plm_fsm_cla_timer_reg_count_s[20]), + .Q(plm_fsm_cla_timer_reg_count[20]), + .CLR(plm_rst) + ); + FDC plm_fsm_cla_timer_reg_count_19_ ( + .C(mgt_clk), + .D(plm_fsm_cla_timer_reg_count_s[19]), + .Q(plm_fsm_cla_timer_reg_count[19]), + .CLR(plm_rst) + ); + FDC plm_fsm_cla_timer_reg_count_18_ ( + .C(mgt_clk), + .D(plm_fsm_cla_timer_reg_count_s[18]), + .Q(plm_fsm_cla_timer_reg_count[18]), + .CLR(plm_rst) + ); + FDC plm_fsm_cla_timer_reg_count_17_ ( + .C(mgt_clk), + .D(plm_fsm_cla_timer_reg_count_s[17]), + .Q(plm_fsm_cla_timer_reg_count[17]), + .CLR(plm_rst) + ); + FDC plm_fsm_cla_timer_reg_count_16_ ( + .C(mgt_clk), + .D(plm_fsm_cla_timer_reg_count_s[16]), + .Q(plm_fsm_cla_timer_reg_count[16]), + .CLR(plm_rst) + ); + FDC plm_fsm_cla_timer_reg_count_15_ ( + .C(mgt_clk), + .D(plm_fsm_cla_timer_reg_count_s[15]), + .Q(plm_fsm_cla_timer_reg_count[15]), + .CLR(plm_rst) + ); + FDC plm_fsm_cla_timer_reg_count_14_ ( + .C(mgt_clk), + .D(plm_fsm_cla_timer_reg_count_s[14]), + .Q(plm_fsm_cla_timer_reg_count[14]), + .CLR(plm_rst) + ); + FDC plm_fsm_cla_timer_reg_count_13_ ( + .C(mgt_clk), + .D(plm_fsm_cla_timer_reg_count_s[13]), + .Q(plm_fsm_cla_timer_reg_count[13]), + .CLR(plm_rst) + ); + FDC plm_fsm_cla_timer_reg_count_12_ ( + .C(mgt_clk), + .D(plm_fsm_cla_timer_reg_count_s[12]), + .Q(plm_fsm_cla_timer_reg_count[12]), + .CLR(plm_rst) + ); + FDC plm_fsm_cla_timer_reg_count_11_ ( + .C(mgt_clk), + .D(plm_fsm_cla_timer_reg_count_s[11]), + .Q(plm_fsm_cla_timer_reg_count[11]), + .CLR(plm_rst) + ); + FDC plm_fsm_cla_timer_reg_count_10_ ( + .C(mgt_clk), + .D(plm_fsm_cla_timer_reg_count_s[10]), + .Q(plm_fsm_cla_timer_reg_count[10]), + .CLR(plm_rst) + ); + FDC plm_fsm_cla_timer_reg_count_9_ ( + .C(mgt_clk), + .D(plm_fsm_cla_timer_reg_count_s[9]), + .Q(plm_fsm_cla_timer_reg_count[9]), + .CLR(plm_rst) + ); + FDC plm_fsm_cla_timer_reg_count_8_ ( + .C(mgt_clk), + .D(plm_fsm_cla_timer_reg_count_s[8]), + .Q(plm_fsm_cla_timer_reg_count[8]), + .CLR(plm_rst) + ); + FDC plm_fsm_cla_timer_reg_count_7_ ( + .C(mgt_clk), + .D(plm_fsm_cla_timer_reg_count_s[7]), + .Q(plm_fsm_cla_timer_reg_count[7]), + .CLR(plm_rst) + ); + FDC plm_fsm_cla_timer_reg_count_6_ ( + .C(mgt_clk), + .D(plm_fsm_cla_timer_reg_count_s[6]), + .Q(plm_fsm_cla_timer_reg_count[6]), + .CLR(plm_rst) + ); + FDC plm_fsm_cla_timer_reg_count_5_ ( + .C(mgt_clk), + .D(plm_fsm_cla_timer_reg_count_s[5]), + .Q(plm_fsm_cla_timer_reg_count[5]), + .CLR(plm_rst) + ); + FDC plm_fsm_cla_timer_reg_count_4_ ( + .C(mgt_clk), + .D(plm_fsm_cla_timer_reg_count_s[4]), + .Q(plm_fsm_cla_timer_reg_count[4]), + .CLR(plm_rst) + ); + FDC plm_fsm_cla_timer_reg_count_3_ ( + .C(mgt_clk), + .D(plm_fsm_cla_timer_reg_count_s[3]), + .Q(plm_fsm_cla_timer_reg_count[3]), + .CLR(plm_rst) + ); + FDC plm_fsm_cla_timer_reg_count_2_ ( + .C(mgt_clk), + .D(plm_fsm_cla_timer_reg_count_s[2]), + .Q(plm_fsm_cla_timer_reg_count[2]), + .CLR(plm_rst) + ); + FDC plm_fsm_cla_timer_reg_count_1_ ( + .C(mgt_clk), + .D(plm_fsm_cla_timer_reg_count_s[1]), + .Q(plm_fsm_cla_timer_reg_count[1]), + .CLR(plm_rst) + ); + FDC plm_fsm_cla_timer_reg_count_0_ ( + .C(mgt_clk), + .D(plm_fsm_cla_timer_reg_count_s[0]), + .Q(plm_fsm_cla_timer_reg_count[0]), + .CLR(plm_rst) + ); + defparam plm_fsm_cla_timer_reg_count_qxu_0_0_.INIT = 4'h8; + LUT2_L plm_fsm_cla_timer_reg_count_qxu_0_0_ ( + .I0(plm_fsm_cla_timer_reg_count[0]), + .I1(plm_fsm_cla_timer_un1_reg_state_1_i_i_1855), + .LO(plm_fsm_cla_timer_reg_count_qxu[0]) + ); + defparam plm_fsm_cla_timer_reg_count_qxu_0_1_.INIT = 4'h8; + LUT2_L plm_fsm_cla_timer_reg_count_qxu_0_1_ ( + .I0(plm_fsm_cla_timer_reg_count[1]), + .I1(plm_fsm_cla_timer_un1_reg_state_1_i_i_1855), + .LO(plm_fsm_cla_timer_reg_count_qxu[1]) + ); + defparam plm_fsm_cla_timer_reg_count_qxu_0_2_.INIT = 4'h8; + LUT2_L plm_fsm_cla_timer_reg_count_qxu_0_2_ ( + .I0(plm_fsm_cla_timer_reg_count[2]), + .I1(plm_fsm_cla_timer_un1_reg_state_1_i_i_1855), + .LO(plm_fsm_cla_timer_reg_count_qxu[2]) + ); + defparam plm_fsm_cla_timer_reg_count_qxu_0_3_.INIT = 4'h8; + LUT2_L plm_fsm_cla_timer_reg_count_qxu_0_3_ ( + .I0(plm_fsm_cla_timer_reg_count[3]), + .I1(plm_fsm_cla_timer_un1_reg_state_1_i_i_1855), + .LO(plm_fsm_cla_timer_reg_count_qxu[3]) + ); + defparam plm_fsm_cla_timer_reg_count_qxu_0_4_.INIT = 4'h8; + LUT2_L plm_fsm_cla_timer_reg_count_qxu_0_4_ ( + .I0(plm_fsm_cla_timer_reg_count[4]), + .I1(plm_fsm_cla_timer_un1_reg_state_1_i_i_1855), + .LO(plm_fsm_cla_timer_reg_count_qxu[4]) + ); + defparam plm_fsm_cla_timer_reg_count_qxu_0_5_.INIT = 4'h8; + LUT2_L plm_fsm_cla_timer_reg_count_qxu_0_5_ ( + .I0(plm_fsm_cla_timer_reg_count[5]), + .I1(plm_fsm_cla_timer_un1_reg_state_1_i_i_1855), + .LO(plm_fsm_cla_timer_reg_count_qxu[5]) + ); + defparam plm_fsm_cla_timer_reg_count_qxu_0_6_.INIT = 4'h8; + LUT2_L plm_fsm_cla_timer_reg_count_qxu_0_6_ ( + .I0(plm_fsm_cla_timer_reg_count[6]), + .I1(plm_fsm_cla_timer_un1_reg_state_1_i_i_1855), + .LO(plm_fsm_cla_timer_reg_count_qxu[6]) + ); + defparam plm_fsm_cla_timer_reg_count_qxu_0_7_.INIT = 4'h8; + LUT2_L plm_fsm_cla_timer_reg_count_qxu_0_7_ ( + .I0(plm_fsm_cla_timer_reg_count[7]), + .I1(plm_fsm_cla_timer_un1_reg_state_1_i_i_1855), + .LO(plm_fsm_cla_timer_reg_count_qxu[7]) + ); + defparam plm_fsm_cla_timer_reg_count_qxu_0_8_.INIT = 4'h8; + LUT2_L plm_fsm_cla_timer_reg_count_qxu_0_8_ ( + .I0(plm_fsm_cla_timer_reg_count[8]), + .I1(plm_fsm_cla_timer_un1_reg_state_1_i_i_1855), + .LO(plm_fsm_cla_timer_reg_count_qxu[8]) + ); + defparam plm_fsm_cla_timer_reg_count_qxu_0_9_.INIT = 4'h8; + LUT2_L plm_fsm_cla_timer_reg_count_qxu_0_9_ ( + .I0(plm_fsm_cla_timer_reg_count[9]), + .I1(plm_fsm_cla_timer_un1_reg_state_1_i_i_1855), + .LO(plm_fsm_cla_timer_reg_count_qxu[9]) + ); + defparam plm_fsm_cla_timer_reg_count_qxu_0_10_.INIT = 4'h8; + LUT2_L plm_fsm_cla_timer_reg_count_qxu_0_10_ ( + .I0(plm_fsm_cla_timer_reg_count[10]), + .I1(plm_fsm_cla_timer_un1_reg_state_1_i_i_1855), + .LO(plm_fsm_cla_timer_reg_count_qxu[10]) + ); + defparam plm_fsm_cla_timer_reg_count_qxu_0_11_.INIT = 4'h8; + LUT2_L plm_fsm_cla_timer_reg_count_qxu_0_11_ ( + .I0(plm_fsm_cla_timer_reg_count[11]), + .I1(plm_fsm_cla_timer_un1_reg_state_1_i_i_1855), + .LO(plm_fsm_cla_timer_reg_count_qxu[11]) + ); + defparam plm_fsm_cla_timer_reg_count_qxu_0_12_.INIT = 4'h8; + LUT2_L plm_fsm_cla_timer_reg_count_qxu_0_12_ ( + .I0(plm_fsm_cla_timer_reg_count[12]), + .I1(plm_fsm_cla_timer_un1_reg_state_1_i_i_1855), + .LO(plm_fsm_cla_timer_reg_count_qxu[12]) + ); + defparam plm_fsm_cla_timer_reg_count_qxu_0_13_.INIT = 4'h8; + LUT2_L plm_fsm_cla_timer_reg_count_qxu_0_13_ ( + .I0(plm_fsm_cla_timer_reg_count[13]), + .I1(plm_fsm_cla_timer_un1_reg_state_1_i_i_1855), + .LO(plm_fsm_cla_timer_reg_count_qxu[13]) + ); + defparam plm_fsm_cla_timer_reg_count_qxu_0_14_.INIT = 4'h8; + LUT2_L plm_fsm_cla_timer_reg_count_qxu_0_14_ ( + .I0(plm_fsm_cla_timer_reg_count[14]), + .I1(plm_fsm_cla_timer_un1_reg_state_1_i_i_1855), + .LO(plm_fsm_cla_timer_reg_count_qxu[14]) + ); + defparam plm_fsm_cla_timer_reg_count_qxu_0_15_.INIT = 4'h8; + LUT2_L plm_fsm_cla_timer_reg_count_qxu_0_15_ ( + .I0(plm_fsm_cla_timer_reg_count[15]), + .I1(plm_fsm_cla_timer_un1_reg_state_1_i_i_1855), + .LO(plm_fsm_cla_timer_reg_count_qxu[15]) + ); + defparam plm_fsm_cla_timer_reg_count_qxu_0_16_.INIT = 4'h8; + LUT2_L plm_fsm_cla_timer_reg_count_qxu_0_16_ ( + .I0(plm_fsm_cla_timer_reg_count[16]), + .I1(plm_fsm_cla_timer_un1_reg_state_1_i_i_1855), + .LO(plm_fsm_cla_timer_reg_count_qxu[16]) + ); + defparam plm_fsm_cla_timer_reg_count_qxu_0_17_.INIT = 4'h8; + LUT2_L plm_fsm_cla_timer_reg_count_qxu_0_17_ ( + .I0(plm_fsm_cla_timer_reg_count[17]), + .I1(plm_fsm_cla_timer_un1_reg_state_1_i_i_1855), + .LO(plm_fsm_cla_timer_reg_count_qxu[17]) + ); + defparam plm_fsm_cla_timer_reg_count_qxu_0_18_.INIT = 4'h8; + LUT2_L plm_fsm_cla_timer_reg_count_qxu_0_18_ ( + .I0(plm_fsm_cla_timer_reg_count[18]), + .I1(plm_fsm_cla_timer_un1_reg_state_1_i_i_1855), + .LO(plm_fsm_cla_timer_reg_count_qxu[18]) + ); + defparam plm_fsm_cla_timer_reg_count_qxu_0_19_.INIT = 4'h8; + LUT2_L plm_fsm_cla_timer_reg_count_qxu_0_19_ ( + .I0(plm_fsm_cla_timer_reg_count[19]), + .I1(plm_fsm_cla_timer_un1_reg_state_1_i_i_1855), + .LO(plm_fsm_cla_timer_reg_count_qxu[19]) + ); + defparam plm_fsm_cla_timer_reg_count_qxu_0_20_.INIT = 4'h8; + LUT2_L plm_fsm_cla_timer_reg_count_qxu_0_20_ ( + .I0(plm_fsm_cla_timer_reg_count[20]), + .I1(plm_fsm_cla_timer_un1_reg_state_1_i_i_1855), + .LO(plm_fsm_cla_timer_reg_count_qxu[20]) + ); + defparam plm_fsm_cla_timer_reg_count_qxu_0_21_.INIT = 4'h8; + LUT2_L plm_fsm_cla_timer_reg_count_qxu_0_21_ ( + .I0(plm_fsm_cla_timer_reg_count[21]), + .I1(plm_fsm_cla_timer_un1_reg_state_1_i_i_1855), + .LO(plm_fsm_cla_timer_reg_count_qxu[21]) + ); + defparam plm_fsm_cla_timer_reg_count_qxu_0_22_.INIT = 4'h8; + LUT2_L plm_fsm_cla_timer_reg_count_qxu_0_22_ ( + .I0(plm_fsm_cla_timer_reg_count[22]), + .I1(plm_fsm_cla_timer_un1_reg_state_1_i_i_1855), + .LO(plm_fsm_cla_timer_reg_count_qxu[22]) + ); + GND plm_fsm_clw_timer_GND ( + .G(plm_fsm_clw_timer_GND_1856) + ); + MUXCY_L plm_fsm_clw_timer_reg_count_cry_0_ ( + .CI(plm_fsm_reg_state_7__1777), + .DI(plm_fsm_clw_timer_GND_1856), + .LO(plm_fsm_clw_timer_reg_count_cry[0]), + .S(plm_fsm_clw_timer_reg_count_qxu[0]) + ); + XORCY plm_fsm_clw_timer_reg_count_s_0_ ( + .CI(plm_fsm_reg_state_7__1777), + .LI(plm_fsm_clw_timer_reg_count_qxu[0]), + .O(plm_fsm_clw_timer_reg_count_s[0]) + ); + MUXCY_L plm_fsm_clw_timer_reg_count_cry_1_ ( + .CI(plm_fsm_clw_timer_reg_count_cry[0]), + .DI(plm_fsm_clw_timer_GND_1856), + .LO(plm_fsm_clw_timer_reg_count_cry[1]), + .S(plm_fsm_clw_timer_reg_count_qxu[1]) + ); + XORCY plm_fsm_clw_timer_reg_count_s_1_ ( + .CI(plm_fsm_clw_timer_reg_count_cry[0]), + .LI(plm_fsm_clw_timer_reg_count_qxu[1]), + .O(plm_fsm_clw_timer_reg_count_s[1]) + ); + MUXCY_L plm_fsm_clw_timer_reg_count_cry_2_ ( + .CI(plm_fsm_clw_timer_reg_count_cry[1]), + .DI(plm_fsm_clw_timer_GND_1856), + .LO(plm_fsm_clw_timer_reg_count_cry[2]), + .S(plm_fsm_clw_timer_reg_count_qxu[2]) + ); + XORCY plm_fsm_clw_timer_reg_count_s_2_ ( + .CI(plm_fsm_clw_timer_reg_count_cry[1]), + .LI(plm_fsm_clw_timer_reg_count_qxu[2]), + .O(plm_fsm_clw_timer_reg_count_s[2]) + ); + MUXCY_L plm_fsm_clw_timer_reg_count_cry_3_ ( + .CI(plm_fsm_clw_timer_reg_count_cry[2]), + .DI(plm_fsm_clw_timer_GND_1856), + .LO(plm_fsm_clw_timer_reg_count_cry[3]), + .S(plm_fsm_clw_timer_reg_count_qxu[3]) + ); + XORCY plm_fsm_clw_timer_reg_count_s_3_ ( + .CI(plm_fsm_clw_timer_reg_count_cry[2]), + .LI(plm_fsm_clw_timer_reg_count_qxu[3]), + .O(plm_fsm_clw_timer_reg_count_s[3]) + ); + MUXCY_L plm_fsm_clw_timer_reg_count_cry_4_ ( + .CI(plm_fsm_clw_timer_reg_count_cry[3]), + .DI(plm_fsm_clw_timer_GND_1856), + .LO(plm_fsm_clw_timer_reg_count_cry[4]), + .S(plm_fsm_clw_timer_reg_count_qxu[4]) + ); + XORCY plm_fsm_clw_timer_reg_count_s_4_ ( + .CI(plm_fsm_clw_timer_reg_count_cry[3]), + .LI(plm_fsm_clw_timer_reg_count_qxu[4]), + .O(plm_fsm_clw_timer_reg_count_s[4]) + ); + MUXCY_L plm_fsm_clw_timer_reg_count_cry_5_ ( + .CI(plm_fsm_clw_timer_reg_count_cry[4]), + .DI(plm_fsm_clw_timer_GND_1856), + .LO(plm_fsm_clw_timer_reg_count_cry[5]), + .S(plm_fsm_clw_timer_reg_count_qxu[5]) + ); + XORCY plm_fsm_clw_timer_reg_count_s_5_ ( + .CI(plm_fsm_clw_timer_reg_count_cry[4]), + .LI(plm_fsm_clw_timer_reg_count_qxu[5]), + .O(plm_fsm_clw_timer_reg_count_s[5]) + ); + MUXCY_L plm_fsm_clw_timer_reg_count_cry_6_ ( + .CI(plm_fsm_clw_timer_reg_count_cry[5]), + .DI(plm_fsm_clw_timer_GND_1856), + .LO(plm_fsm_clw_timer_reg_count_cry[6]), + .S(plm_fsm_clw_timer_reg_count_qxu[6]) + ); + XORCY plm_fsm_clw_timer_reg_count_s_6_ ( + .CI(plm_fsm_clw_timer_reg_count_cry[5]), + .LI(plm_fsm_clw_timer_reg_count_qxu[6]), + .O(plm_fsm_clw_timer_reg_count_s[6]) + ); + MUXCY_L plm_fsm_clw_timer_reg_count_cry_7_ ( + .CI(plm_fsm_clw_timer_reg_count_cry[6]), + .DI(plm_fsm_clw_timer_GND_1856), + .LO(plm_fsm_clw_timer_reg_count_cry[7]), + .S(plm_fsm_clw_timer_reg_count_qxu[7]) + ); + XORCY plm_fsm_clw_timer_reg_count_s_7_ ( + .CI(plm_fsm_clw_timer_reg_count_cry[6]), + .LI(plm_fsm_clw_timer_reg_count_qxu[7]), + .O(plm_fsm_clw_timer_reg_count_s[7]) + ); + MUXCY_L plm_fsm_clw_timer_reg_count_cry_8_ ( + .CI(plm_fsm_clw_timer_reg_count_cry[7]), + .DI(plm_fsm_clw_timer_GND_1856), + .LO(plm_fsm_clw_timer_reg_count_cry[8]), + .S(plm_fsm_clw_timer_reg_count_qxu[8]) + ); + XORCY plm_fsm_clw_timer_reg_count_s_8_ ( + .CI(plm_fsm_clw_timer_reg_count_cry[7]), + .LI(plm_fsm_clw_timer_reg_count_qxu[8]), + .O(plm_fsm_clw_timer_reg_count_s[8]) + ); + MUXCY_L plm_fsm_clw_timer_reg_count_cry_9_ ( + .CI(plm_fsm_clw_timer_reg_count_cry[8]), + .DI(plm_fsm_clw_timer_GND_1856), + .LO(plm_fsm_clw_timer_reg_count_cry[9]), + .S(plm_fsm_clw_timer_reg_count_qxu[9]) + ); + XORCY plm_fsm_clw_timer_reg_count_s_9_ ( + .CI(plm_fsm_clw_timer_reg_count_cry[8]), + .LI(plm_fsm_clw_timer_reg_count_qxu[9]), + .O(plm_fsm_clw_timer_reg_count_s[9]) + ); + MUXCY_L plm_fsm_clw_timer_reg_count_cry_10_ ( + .CI(plm_fsm_clw_timer_reg_count_cry[9]), + .DI(plm_fsm_clw_timer_GND_1856), + .LO(plm_fsm_clw_timer_reg_count_cry[10]), + .S(plm_fsm_clw_timer_reg_count_qxu[10]) + ); + XORCY plm_fsm_clw_timer_reg_count_s_10_ ( + .CI(plm_fsm_clw_timer_reg_count_cry[9]), + .LI(plm_fsm_clw_timer_reg_count_qxu[10]), + .O(plm_fsm_clw_timer_reg_count_s[10]) + ); + MUXCY_L plm_fsm_clw_timer_reg_count_cry_11_ ( + .CI(plm_fsm_clw_timer_reg_count_cry[10]), + .DI(plm_fsm_clw_timer_GND_1856), + .LO(plm_fsm_clw_timer_reg_count_cry[11]), + .S(plm_fsm_clw_timer_reg_count_qxu[11]) + ); + XORCY plm_fsm_clw_timer_reg_count_s_11_ ( + .CI(plm_fsm_clw_timer_reg_count_cry[10]), + .LI(plm_fsm_clw_timer_reg_count_qxu[11]), + .O(plm_fsm_clw_timer_reg_count_s[11]) + ); + MUXCY_L plm_fsm_clw_timer_reg_count_cry_12_ ( + .CI(plm_fsm_clw_timer_reg_count_cry[11]), + .DI(plm_fsm_clw_timer_GND_1856), + .LO(plm_fsm_clw_timer_reg_count_cry[12]), + .S(plm_fsm_clw_timer_reg_count_qxu[12]) + ); + XORCY plm_fsm_clw_timer_reg_count_s_12_ ( + .CI(plm_fsm_clw_timer_reg_count_cry[11]), + .LI(plm_fsm_clw_timer_reg_count_qxu[12]), + .O(plm_fsm_clw_timer_reg_count_s[12]) + ); + MUXCY_L plm_fsm_clw_timer_reg_count_cry_13_ ( + .CI(plm_fsm_clw_timer_reg_count_cry[12]), + .DI(plm_fsm_clw_timer_GND_1856), + .LO(plm_fsm_clw_timer_reg_count_cry[13]), + .S(plm_fsm_clw_timer_reg_count_qxu[13]) + ); + XORCY plm_fsm_clw_timer_reg_count_s_13_ ( + .CI(plm_fsm_clw_timer_reg_count_cry[12]), + .LI(plm_fsm_clw_timer_reg_count_qxu[13]), + .O(plm_fsm_clw_timer_reg_count_s[13]) + ); + MUXCY_L plm_fsm_clw_timer_reg_count_cry_14_ ( + .CI(plm_fsm_clw_timer_reg_count_cry[13]), + .DI(plm_fsm_clw_timer_GND_1856), + .LO(plm_fsm_clw_timer_reg_count_cry[14]), + .S(plm_fsm_clw_timer_reg_count_qxu[14]) + ); + XORCY plm_fsm_clw_timer_reg_count_s_14_ ( + .CI(plm_fsm_clw_timer_reg_count_cry[13]), + .LI(plm_fsm_clw_timer_reg_count_qxu[14]), + .O(plm_fsm_clw_timer_reg_count_s[14]) + ); + MUXCY_L plm_fsm_clw_timer_reg_count_cry_15_ ( + .CI(plm_fsm_clw_timer_reg_count_cry[14]), + .DI(plm_fsm_clw_timer_GND_1856), + .LO(plm_fsm_clw_timer_reg_count_cry[15]), + .S(plm_fsm_clw_timer_reg_count_qxu[15]) + ); + XORCY plm_fsm_clw_timer_reg_count_s_15_ ( + .CI(plm_fsm_clw_timer_reg_count_cry[14]), + .LI(plm_fsm_clw_timer_reg_count_qxu[15]), + .O(plm_fsm_clw_timer_reg_count_s[15]) + ); + MUXCY_L plm_fsm_clw_timer_reg_count_cry_16_ ( + .CI(plm_fsm_clw_timer_reg_count_cry[15]), + .DI(plm_fsm_clw_timer_GND_1856), + .LO(plm_fsm_clw_timer_reg_count_cry[16]), + .S(plm_fsm_clw_timer_reg_count_qxu[16]) + ); + XORCY plm_fsm_clw_timer_reg_count_s_16_ ( + .CI(plm_fsm_clw_timer_reg_count_cry[15]), + .LI(plm_fsm_clw_timer_reg_count_qxu[16]), + .O(plm_fsm_clw_timer_reg_count_s[16]) + ); + MUXCY_L plm_fsm_clw_timer_reg_count_cry_17_ ( + .CI(plm_fsm_clw_timer_reg_count_cry[16]), + .DI(plm_fsm_clw_timer_GND_1856), + .LO(plm_fsm_clw_timer_reg_count_cry[17]), + .S(plm_fsm_clw_timer_reg_count_qxu[17]) + ); + XORCY plm_fsm_clw_timer_reg_count_s_17_ ( + .CI(plm_fsm_clw_timer_reg_count_cry[16]), + .LI(plm_fsm_clw_timer_reg_count_qxu[17]), + .O(plm_fsm_clw_timer_reg_count_s[17]) + ); + MUXCY_L plm_fsm_clw_timer_reg_count_cry_18_ ( + .CI(plm_fsm_clw_timer_reg_count_cry[17]), + .DI(plm_fsm_clw_timer_GND_1856), + .LO(plm_fsm_clw_timer_reg_count_cry[18]), + .S(plm_fsm_clw_timer_reg_count_qxu[18]) + ); + XORCY plm_fsm_clw_timer_reg_count_s_18_ ( + .CI(plm_fsm_clw_timer_reg_count_cry[17]), + .LI(plm_fsm_clw_timer_reg_count_qxu[18]), + .O(plm_fsm_clw_timer_reg_count_s[18]) + ); + MUXCY_L plm_fsm_clw_timer_reg_count_cry_19_ ( + .CI(plm_fsm_clw_timer_reg_count_cry[18]), + .DI(plm_fsm_clw_timer_GND_1856), + .LO(plm_fsm_clw_timer_reg_count_cry[19]), + .S(plm_fsm_clw_timer_reg_count_qxu[19]) + ); + XORCY plm_fsm_clw_timer_reg_count_s_19_ ( + .CI(plm_fsm_clw_timer_reg_count_cry[18]), + .LI(plm_fsm_clw_timer_reg_count_qxu[19]), + .O(plm_fsm_clw_timer_reg_count_s[19]) + ); + MUXCY_L plm_fsm_clw_timer_reg_count_cry_20_ ( + .CI(plm_fsm_clw_timer_reg_count_cry[19]), + .DI(plm_fsm_clw_timer_GND_1856), + .LO(plm_fsm_clw_timer_reg_count_cry[20]), + .S(plm_fsm_clw_timer_reg_count_qxu[20]) + ); + XORCY plm_fsm_clw_timer_reg_count_s_20_ ( + .CI(plm_fsm_clw_timer_reg_count_cry[19]), + .LI(plm_fsm_clw_timer_reg_count_qxu[20]), + .O(plm_fsm_clw_timer_reg_count_s[20]) + ); + MUXCY_L plm_fsm_clw_timer_reg_count_cry_21_ ( + .CI(plm_fsm_clw_timer_reg_count_cry[20]), + .DI(plm_fsm_clw_timer_GND_1856), + .LO(plm_fsm_clw_timer_reg_count_cry[21]), + .S(plm_fsm_clw_timer_reg_count_qxu[21]) + ); + XORCY plm_fsm_clw_timer_reg_count_s_21_ ( + .CI(plm_fsm_clw_timer_reg_count_cry[20]), + .LI(plm_fsm_clw_timer_reg_count_qxu[21]), + .O(plm_fsm_clw_timer_reg_count_s[21]) + ); + XORCY plm_fsm_clw_timer_reg_count_s_22_ ( + .CI(plm_fsm_clw_timer_reg_count_cry[21]), + .LI(plm_fsm_clw_timer_reg_count_qxu[22]), + .O(plm_fsm_clw_timer_reg_count_s[22]) + ); + defparam plm_fsm_clw_timer_count_i_m3_i_m3_0_18_.INIT = 8'hD8; + LUT3 plm_fsm_clw_timer_count_i_m3_i_m3_0_18_ ( + .I0(cfg_cfg_6102[507]), + .I1(plm_fsm_clw_timer_reg_count[10]), + .I2(plm_fsm_clw_timer_reg_count[18]), + .O(plm_fsm_clw_timer_N_63716) + ); + defparam plm_fsm_clw_timer_count_i_m3_i_m3_0_19_.INIT = 8'hD8; + LUT3_L plm_fsm_clw_timer_count_i_m3_i_m3_0_19_ ( + .I0(cfg_cfg_6102[507]), + .I1(plm_fsm_clw_timer_reg_count[11]), + .I2(plm_fsm_clw_timer_reg_count[19]), + .LO(plm_fsm_clw_timer_N_63717) + ); + defparam plm_fsm_clw_timer_count_i_m3_i_m3_0_20_.INIT = 8'hD8; + LUT3 plm_fsm_clw_timer_count_i_m3_i_m3_0_20_ ( + .I0(cfg_cfg_6102[507]), + .I1(plm_fsm_clw_timer_reg_count[12]), + .I2(plm_fsm_clw_timer_reg_count[20]), + .O(plm_fsm_clw_timer_N_63718) + ); + defparam plm_fsm_clw_timer_count_i_m3_i_m3_0_21_.INIT = 8'hD8; + LUT3 plm_fsm_clw_timer_count_i_m3_i_m3_0_21_ ( + .I0(cfg_cfg_6102[507]), + .I1(plm_fsm_clw_timer_reg_count[13]), + .I2(plm_fsm_clw_timer_reg_count[21]), + .O(plm_fsm_clw_timer_N_63719) + ); + defparam plm_fsm_clw_timer_un1_expired_2ms_0_a2_0_a3_0.INIT = 16'h0415; + LUT4_L plm_fsm_clw_timer_un1_expired_2ms_0_a2_0_a3_0 ( + .I0(plm_fsm_clw_timer_N_63717), + .I1(cfg_cfg_6102[507]), + .I2(plm_fsm_clw_timer_reg_count[14]), + .I3(plm_fsm_clw_timer_reg_count[22]), + .LO(plm_fsm_clw_timer_un1_expired_2ms_0_a2_0_a3_0_1857) + ); + defparam plm_fsm_clw_timer_un1_expired_2ms_0_a2_0_a3.INIT = 16'h0100; + LUT4 plm_fsm_clw_timer_un1_expired_2ms_0_a2_0_a3 ( + .I0(plm_fsm_clw_timer_N_63716), + .I1(plm_fsm_clw_timer_N_63718), + .I2(plm_fsm_clw_timer_N_63719), + .I3(plm_fsm_clw_timer_un1_expired_2ms_0_a2_0_a3_0_1857), + .O(plm_fsm_N_63492) + ); + FDC plm_fsm_clw_timer_reg_count_22_ ( + .C(mgt_clk), + .D(plm_fsm_clw_timer_reg_count_s[22]), + .Q(plm_fsm_clw_timer_reg_count[22]), + .CLR(plm_rst) + ); + FDC plm_fsm_clw_timer_reg_count_21_ ( + .C(mgt_clk), + .D(plm_fsm_clw_timer_reg_count_s[21]), + .Q(plm_fsm_clw_timer_reg_count[21]), + .CLR(plm_rst) + ); + FDC plm_fsm_clw_timer_reg_count_20_ ( + .C(mgt_clk), + .D(plm_fsm_clw_timer_reg_count_s[20]), + .Q(plm_fsm_clw_timer_reg_count[20]), + .CLR(plm_rst) + ); + FDC plm_fsm_clw_timer_reg_count_19_ ( + .C(mgt_clk), + .D(plm_fsm_clw_timer_reg_count_s[19]), + .Q(plm_fsm_clw_timer_reg_count[19]), + .CLR(plm_rst) + ); + FDC plm_fsm_clw_timer_reg_count_18_ ( + .C(mgt_clk), + .D(plm_fsm_clw_timer_reg_count_s[18]), + .Q(plm_fsm_clw_timer_reg_count[18]), + .CLR(plm_rst) + ); + FDC plm_fsm_clw_timer_reg_count_17_ ( + .C(mgt_clk), + .D(plm_fsm_clw_timer_reg_count_s[17]), + .Q(plm_fsm_clw_timer_reg_count[17]), + .CLR(plm_rst) + ); + FDC plm_fsm_clw_timer_reg_count_16_ ( + .C(mgt_clk), + .D(plm_fsm_clw_timer_reg_count_s[16]), + .Q(plm_fsm_clw_timer_reg_count[16]), + .CLR(plm_rst) + ); + FDC plm_fsm_clw_timer_reg_count_15_ ( + .C(mgt_clk), + .D(plm_fsm_clw_timer_reg_count_s[15]), + .Q(plm_fsm_clw_timer_reg_count[15]), + .CLR(plm_rst) + ); + FDC plm_fsm_clw_timer_reg_count_14_ ( + .C(mgt_clk), + .D(plm_fsm_clw_timer_reg_count_s[14]), + .Q(plm_fsm_clw_timer_reg_count[14]), + .CLR(plm_rst) + ); + FDC plm_fsm_clw_timer_reg_count_13_ ( + .C(mgt_clk), + .D(plm_fsm_clw_timer_reg_count_s[13]), + .Q(plm_fsm_clw_timer_reg_count[13]), + .CLR(plm_rst) + ); + FDC plm_fsm_clw_timer_reg_count_12_ ( + .C(mgt_clk), + .D(plm_fsm_clw_timer_reg_count_s[12]), + .Q(plm_fsm_clw_timer_reg_count[12]), + .CLR(plm_rst) + ); + FDC plm_fsm_clw_timer_reg_count_11_ ( + .C(mgt_clk), + .D(plm_fsm_clw_timer_reg_count_s[11]), + .Q(plm_fsm_clw_timer_reg_count[11]), + .CLR(plm_rst) + ); + FDC plm_fsm_clw_timer_reg_count_10_ ( + .C(mgt_clk), + .D(plm_fsm_clw_timer_reg_count_s[10]), + .Q(plm_fsm_clw_timer_reg_count[10]), + .CLR(plm_rst) + ); + FDC plm_fsm_clw_timer_reg_count_9_ ( + .C(mgt_clk), + .D(plm_fsm_clw_timer_reg_count_s[9]), + .Q(plm_fsm_clw_timer_reg_count[9]), + .CLR(plm_rst) + ); + FDC plm_fsm_clw_timer_reg_count_8_ ( + .C(mgt_clk), + .D(plm_fsm_clw_timer_reg_count_s[8]), + .Q(plm_fsm_clw_timer_reg_count[8]), + .CLR(plm_rst) + ); + FDC plm_fsm_clw_timer_reg_count_7_ ( + .C(mgt_clk), + .D(plm_fsm_clw_timer_reg_count_s[7]), + .Q(plm_fsm_clw_timer_reg_count[7]), + .CLR(plm_rst) + ); + FDC plm_fsm_clw_timer_reg_count_6_ ( + .C(mgt_clk), + .D(plm_fsm_clw_timer_reg_count_s[6]), + .Q(plm_fsm_clw_timer_reg_count[6]), + .CLR(plm_rst) + ); + FDC plm_fsm_clw_timer_reg_count_5_ ( + .C(mgt_clk), + .D(plm_fsm_clw_timer_reg_count_s[5]), + .Q(plm_fsm_clw_timer_reg_count[5]), + .CLR(plm_rst) + ); + FDC plm_fsm_clw_timer_reg_count_4_ ( + .C(mgt_clk), + .D(plm_fsm_clw_timer_reg_count_s[4]), + .Q(plm_fsm_clw_timer_reg_count[4]), + .CLR(plm_rst) + ); + FDC plm_fsm_clw_timer_reg_count_3_ ( + .C(mgt_clk), + .D(plm_fsm_clw_timer_reg_count_s[3]), + .Q(plm_fsm_clw_timer_reg_count[3]), + .CLR(plm_rst) + ); + FDC plm_fsm_clw_timer_reg_count_2_ ( + .C(mgt_clk), + .D(plm_fsm_clw_timer_reg_count_s[2]), + .Q(plm_fsm_clw_timer_reg_count[2]), + .CLR(plm_rst) + ); + FDC plm_fsm_clw_timer_reg_count_1_ ( + .C(mgt_clk), + .D(plm_fsm_clw_timer_reg_count_s[1]), + .Q(plm_fsm_clw_timer_reg_count[1]), + .CLR(plm_rst) + ); + FDC plm_fsm_clw_timer_reg_count_0_ ( + .C(mgt_clk), + .D(plm_fsm_clw_timer_reg_count_s[0]), + .Q(plm_fsm_clw_timer_reg_count[0]), + .CLR(plm_rst) + ); + defparam plm_fsm_clw_timer_reg_count_qxu_0_0_.INIT = 4'h8; + LUT2_L plm_fsm_clw_timer_reg_count_qxu_0_0_ ( + .I0(plm_fsm_clw_timer_reg_count[0]), + .I1(plm_fsm_reg_state_7__1777), + .LO(plm_fsm_clw_timer_reg_count_qxu[0]) + ); + defparam plm_fsm_clw_timer_reg_count_qxu_0_1_.INIT = 4'h8; + LUT2_L plm_fsm_clw_timer_reg_count_qxu_0_1_ ( + .I0(plm_fsm_clw_timer_reg_count[1]), + .I1(plm_fsm_reg_state_7__1777), + .LO(plm_fsm_clw_timer_reg_count_qxu[1]) + ); + defparam plm_fsm_clw_timer_reg_count_qxu_0_2_.INIT = 4'h8; + LUT2_L plm_fsm_clw_timer_reg_count_qxu_0_2_ ( + .I0(plm_fsm_clw_timer_reg_count[2]), + .I1(plm_fsm_reg_state_7__1777), + .LO(plm_fsm_clw_timer_reg_count_qxu[2]) + ); + defparam plm_fsm_clw_timer_reg_count_qxu_0_3_.INIT = 4'h8; + LUT2_L plm_fsm_clw_timer_reg_count_qxu_0_3_ ( + .I0(plm_fsm_clw_timer_reg_count[3]), + .I1(plm_fsm_reg_state_7__1777), + .LO(plm_fsm_clw_timer_reg_count_qxu[3]) + ); + defparam plm_fsm_clw_timer_reg_count_qxu_0_4_.INIT = 4'h8; + LUT2_L plm_fsm_clw_timer_reg_count_qxu_0_4_ ( + .I0(plm_fsm_clw_timer_reg_count[4]), + .I1(plm_fsm_reg_state_7__1777), + .LO(plm_fsm_clw_timer_reg_count_qxu[4]) + ); + defparam plm_fsm_clw_timer_reg_count_qxu_0_5_.INIT = 4'h8; + LUT2_L plm_fsm_clw_timer_reg_count_qxu_0_5_ ( + .I0(plm_fsm_clw_timer_reg_count[5]), + .I1(plm_fsm_reg_state_7__1777), + .LO(plm_fsm_clw_timer_reg_count_qxu[5]) + ); + defparam plm_fsm_clw_timer_reg_count_qxu_0_6_.INIT = 4'h8; + LUT2_L plm_fsm_clw_timer_reg_count_qxu_0_6_ ( + .I0(plm_fsm_clw_timer_reg_count[6]), + .I1(plm_fsm_reg_state_7__1777), + .LO(plm_fsm_clw_timer_reg_count_qxu[6]) + ); + defparam plm_fsm_clw_timer_reg_count_qxu_0_7_.INIT = 4'h8; + LUT2_L plm_fsm_clw_timer_reg_count_qxu_0_7_ ( + .I0(plm_fsm_clw_timer_reg_count[7]), + .I1(plm_fsm_reg_state_7__1777), + .LO(plm_fsm_clw_timer_reg_count_qxu[7]) + ); + defparam plm_fsm_clw_timer_reg_count_qxu_0_8_.INIT = 4'h8; + LUT2_L plm_fsm_clw_timer_reg_count_qxu_0_8_ ( + .I0(plm_fsm_clw_timer_reg_count[8]), + .I1(plm_fsm_reg_state_7__1777), + .LO(plm_fsm_clw_timer_reg_count_qxu[8]) + ); + defparam plm_fsm_clw_timer_reg_count_qxu_0_9_.INIT = 4'h8; + LUT2_L plm_fsm_clw_timer_reg_count_qxu_0_9_ ( + .I0(plm_fsm_clw_timer_reg_count[9]), + .I1(plm_fsm_reg_state_7__1777), + .LO(plm_fsm_clw_timer_reg_count_qxu[9]) + ); + defparam plm_fsm_clw_timer_reg_count_qxu_0_10_.INIT = 4'h8; + LUT2_L plm_fsm_clw_timer_reg_count_qxu_0_10_ ( + .I0(plm_fsm_clw_timer_reg_count[10]), + .I1(plm_fsm_reg_state_7__1777), + .LO(plm_fsm_clw_timer_reg_count_qxu[10]) + ); + defparam plm_fsm_clw_timer_reg_count_qxu_0_11_.INIT = 4'h8; + LUT2_L plm_fsm_clw_timer_reg_count_qxu_0_11_ ( + .I0(plm_fsm_clw_timer_reg_count[11]), + .I1(plm_fsm_reg_state_7__1777), + .LO(plm_fsm_clw_timer_reg_count_qxu[11]) + ); + defparam plm_fsm_clw_timer_reg_count_qxu_0_12_.INIT = 4'h8; + LUT2_L plm_fsm_clw_timer_reg_count_qxu_0_12_ ( + .I0(plm_fsm_clw_timer_reg_count[12]), + .I1(plm_fsm_reg_state_7__1777), + .LO(plm_fsm_clw_timer_reg_count_qxu[12]) + ); + defparam plm_fsm_clw_timer_reg_count_qxu_0_13_.INIT = 4'h8; + LUT2_L plm_fsm_clw_timer_reg_count_qxu_0_13_ ( + .I0(plm_fsm_clw_timer_reg_count[13]), + .I1(plm_fsm_reg_state_7__1777), + .LO(plm_fsm_clw_timer_reg_count_qxu[13]) + ); + defparam plm_fsm_clw_timer_reg_count_qxu_0_14_.INIT = 4'h8; + LUT2_L plm_fsm_clw_timer_reg_count_qxu_0_14_ ( + .I0(plm_fsm_clw_timer_reg_count[14]), + .I1(plm_fsm_reg_state_7__1777), + .LO(plm_fsm_clw_timer_reg_count_qxu[14]) + ); + defparam plm_fsm_clw_timer_reg_count_qxu_0_15_.INIT = 4'h8; + LUT2_L plm_fsm_clw_timer_reg_count_qxu_0_15_ ( + .I0(plm_fsm_clw_timer_reg_count[15]), + .I1(plm_fsm_reg_state_7__1777), + .LO(plm_fsm_clw_timer_reg_count_qxu[15]) + ); + defparam plm_fsm_clw_timer_reg_count_qxu_0_16_.INIT = 4'h8; + LUT2_L plm_fsm_clw_timer_reg_count_qxu_0_16_ ( + .I0(plm_fsm_clw_timer_reg_count[16]), + .I1(plm_fsm_reg_state_7__1777), + .LO(plm_fsm_clw_timer_reg_count_qxu[16]) + ); + defparam plm_fsm_clw_timer_reg_count_qxu_0_17_.INIT = 4'h8; + LUT2_L plm_fsm_clw_timer_reg_count_qxu_0_17_ ( + .I0(plm_fsm_clw_timer_reg_count[17]), + .I1(plm_fsm_reg_state_7__1777), + .LO(plm_fsm_clw_timer_reg_count_qxu[17]) + ); + defparam plm_fsm_clw_timer_reg_count_qxu_0_18_.INIT = 4'h8; + LUT2_L plm_fsm_clw_timer_reg_count_qxu_0_18_ ( + .I0(plm_fsm_clw_timer_reg_count[18]), + .I1(plm_fsm_reg_state_7__1777), + .LO(plm_fsm_clw_timer_reg_count_qxu[18]) + ); + defparam plm_fsm_clw_timer_reg_count_qxu_0_19_.INIT = 4'h8; + LUT2_L plm_fsm_clw_timer_reg_count_qxu_0_19_ ( + .I0(plm_fsm_clw_timer_reg_count[19]), + .I1(plm_fsm_reg_state_7__1777), + .LO(plm_fsm_clw_timer_reg_count_qxu[19]) + ); + defparam plm_fsm_clw_timer_reg_count_qxu_0_20_.INIT = 4'h8; + LUT2_L plm_fsm_clw_timer_reg_count_qxu_0_20_ ( + .I0(plm_fsm_clw_timer_reg_count[20]), + .I1(plm_fsm_reg_state_7__1777), + .LO(plm_fsm_clw_timer_reg_count_qxu[20]) + ); + defparam plm_fsm_clw_timer_reg_count_qxu_0_21_.INIT = 4'h8; + LUT2_L plm_fsm_clw_timer_reg_count_qxu_0_21_ ( + .I0(plm_fsm_clw_timer_reg_count[21]), + .I1(plm_fsm_reg_state_7__1777), + .LO(plm_fsm_clw_timer_reg_count_qxu[21]) + ); + defparam plm_fsm_clw_timer_reg_count_qxu_0_22_.INIT = 4'h8; + LUT2_L plm_fsm_clw_timer_reg_count_qxu_0_22_ ( + .I0(plm_fsm_clw_timer_reg_count[22]), + .I1(plm_fsm_reg_state_7__1777), + .LO(plm_fsm_clw_timer_reg_count_qxu[22]) + ); + GND plm_fsm_cc_timer_GND ( + .G(plm_fsm_cc_timer_GND_1858) + ); + MUXCY_L plm_fsm_cc_timer_reg_count_cry_0_ ( + .CI(plm_fsm_N_56513_i_i_1804), + .DI(plm_fsm_cc_timer_GND_1858), + .LO(plm_fsm_cc_timer_reg_count_cry[0]), + .S(plm_fsm_cc_timer_reg_count_qxu[0]) + ); + XORCY plm_fsm_cc_timer_reg_count_s_0_ ( + .CI(plm_fsm_N_56513_i_i_1804), + .LI(plm_fsm_cc_timer_reg_count_qxu[0]), + .O(plm_fsm_cc_timer_reg_count_s[0]) + ); + MUXCY_L plm_fsm_cc_timer_reg_count_cry_1_ ( + .CI(plm_fsm_cc_timer_reg_count_cry[0]), + .DI(plm_fsm_cc_timer_GND_1858), + .LO(plm_fsm_cc_timer_reg_count_cry[1]), + .S(plm_fsm_cc_timer_reg_count_qxu[1]) + ); + XORCY plm_fsm_cc_timer_reg_count_s_1_ ( + .CI(plm_fsm_cc_timer_reg_count_cry[0]), + .LI(plm_fsm_cc_timer_reg_count_qxu[1]), + .O(plm_fsm_cc_timer_reg_count_s[1]) + ); + MUXCY_L plm_fsm_cc_timer_reg_count_cry_2_ ( + .CI(plm_fsm_cc_timer_reg_count_cry[1]), + .DI(plm_fsm_cc_timer_GND_1858), + .LO(plm_fsm_cc_timer_reg_count_cry[2]), + .S(plm_fsm_cc_timer_reg_count_qxu[2]) + ); + XORCY plm_fsm_cc_timer_reg_count_s_2_ ( + .CI(plm_fsm_cc_timer_reg_count_cry[1]), + .LI(plm_fsm_cc_timer_reg_count_qxu[2]), + .O(plm_fsm_cc_timer_reg_count_s[2]) + ); + MUXCY_L plm_fsm_cc_timer_reg_count_cry_3_ ( + .CI(plm_fsm_cc_timer_reg_count_cry[2]), + .DI(plm_fsm_cc_timer_GND_1858), + .LO(plm_fsm_cc_timer_reg_count_cry[3]), + .S(plm_fsm_cc_timer_reg_count_qxu[3]) + ); + XORCY plm_fsm_cc_timer_reg_count_s_3_ ( + .CI(plm_fsm_cc_timer_reg_count_cry[2]), + .LI(plm_fsm_cc_timer_reg_count_qxu[3]), + .O(plm_fsm_cc_timer_reg_count_s[3]) + ); + MUXCY_L plm_fsm_cc_timer_reg_count_cry_4_ ( + .CI(plm_fsm_cc_timer_reg_count_cry[3]), + .DI(plm_fsm_cc_timer_GND_1858), + .LO(plm_fsm_cc_timer_reg_count_cry[4]), + .S(plm_fsm_cc_timer_reg_count_qxu[4]) + ); + XORCY plm_fsm_cc_timer_reg_count_s_4_ ( + .CI(plm_fsm_cc_timer_reg_count_cry[3]), + .LI(plm_fsm_cc_timer_reg_count_qxu[4]), + .O(plm_fsm_cc_timer_reg_count_s[4]) + ); + MUXCY_L plm_fsm_cc_timer_reg_count_cry_5_ ( + .CI(plm_fsm_cc_timer_reg_count_cry[4]), + .DI(plm_fsm_cc_timer_GND_1858), + .LO(plm_fsm_cc_timer_reg_count_cry[5]), + .S(plm_fsm_cc_timer_reg_count_qxu[5]) + ); + XORCY plm_fsm_cc_timer_reg_count_s_5_ ( + .CI(plm_fsm_cc_timer_reg_count_cry[4]), + .LI(plm_fsm_cc_timer_reg_count_qxu[5]), + .O(plm_fsm_cc_timer_reg_count_s[5]) + ); + MUXCY_L plm_fsm_cc_timer_reg_count_cry_6_ ( + .CI(plm_fsm_cc_timer_reg_count_cry[5]), + .DI(plm_fsm_cc_timer_GND_1858), + .LO(plm_fsm_cc_timer_reg_count_cry[6]), + .S(plm_fsm_cc_timer_reg_count_qxu[6]) + ); + XORCY plm_fsm_cc_timer_reg_count_s_6_ ( + .CI(plm_fsm_cc_timer_reg_count_cry[5]), + .LI(plm_fsm_cc_timer_reg_count_qxu[6]), + .O(plm_fsm_cc_timer_reg_count_s[6]) + ); + MUXCY_L plm_fsm_cc_timer_reg_count_cry_7_ ( + .CI(plm_fsm_cc_timer_reg_count_cry[6]), + .DI(plm_fsm_cc_timer_GND_1858), + .LO(plm_fsm_cc_timer_reg_count_cry[7]), + .S(plm_fsm_cc_timer_reg_count_qxu[7]) + ); + XORCY plm_fsm_cc_timer_reg_count_s_7_ ( + .CI(plm_fsm_cc_timer_reg_count_cry[6]), + .LI(plm_fsm_cc_timer_reg_count_qxu[7]), + .O(plm_fsm_cc_timer_reg_count_s[7]) + ); + MUXCY_L plm_fsm_cc_timer_reg_count_cry_8_ ( + .CI(plm_fsm_cc_timer_reg_count_cry[7]), + .DI(plm_fsm_cc_timer_GND_1858), + .LO(plm_fsm_cc_timer_reg_count_cry[8]), + .S(plm_fsm_cc_timer_reg_count_qxu[8]) + ); + XORCY plm_fsm_cc_timer_reg_count_s_8_ ( + .CI(plm_fsm_cc_timer_reg_count_cry[7]), + .LI(plm_fsm_cc_timer_reg_count_qxu[8]), + .O(plm_fsm_cc_timer_reg_count_s[8]) + ); + MUXCY_L plm_fsm_cc_timer_reg_count_cry_9_ ( + .CI(plm_fsm_cc_timer_reg_count_cry[8]), + .DI(plm_fsm_cc_timer_GND_1858), + .LO(plm_fsm_cc_timer_reg_count_cry[9]), + .S(plm_fsm_cc_timer_reg_count_qxu[9]) + ); + XORCY plm_fsm_cc_timer_reg_count_s_9_ ( + .CI(plm_fsm_cc_timer_reg_count_cry[8]), + .LI(plm_fsm_cc_timer_reg_count_qxu[9]), + .O(plm_fsm_cc_timer_reg_count_s[9]) + ); + MUXCY_L plm_fsm_cc_timer_reg_count_cry_10_ ( + .CI(plm_fsm_cc_timer_reg_count_cry[9]), + .DI(plm_fsm_cc_timer_GND_1858), + .LO(plm_fsm_cc_timer_reg_count_cry[10]), + .S(plm_fsm_cc_timer_reg_count_qxu[10]) + ); + XORCY plm_fsm_cc_timer_reg_count_s_10_ ( + .CI(plm_fsm_cc_timer_reg_count_cry[9]), + .LI(plm_fsm_cc_timer_reg_count_qxu[10]), + .O(plm_fsm_cc_timer_reg_count_s[10]) + ); + MUXCY_L plm_fsm_cc_timer_reg_count_cry_11_ ( + .CI(plm_fsm_cc_timer_reg_count_cry[10]), + .DI(plm_fsm_cc_timer_GND_1858), + .LO(plm_fsm_cc_timer_reg_count_cry[11]), + .S(plm_fsm_cc_timer_reg_count_qxu[11]) + ); + XORCY plm_fsm_cc_timer_reg_count_s_11_ ( + .CI(plm_fsm_cc_timer_reg_count_cry[10]), + .LI(plm_fsm_cc_timer_reg_count_qxu[11]), + .O(plm_fsm_cc_timer_reg_count_s[11]) + ); + MUXCY_L plm_fsm_cc_timer_reg_count_cry_12_ ( + .CI(plm_fsm_cc_timer_reg_count_cry[11]), + .DI(plm_fsm_cc_timer_GND_1858), + .LO(plm_fsm_cc_timer_reg_count_cry[12]), + .S(plm_fsm_cc_timer_reg_count_qxu[12]) + ); + XORCY plm_fsm_cc_timer_reg_count_s_12_ ( + .CI(plm_fsm_cc_timer_reg_count_cry[11]), + .LI(plm_fsm_cc_timer_reg_count_qxu[12]), + .O(plm_fsm_cc_timer_reg_count_s[12]) + ); + MUXCY_L plm_fsm_cc_timer_reg_count_cry_13_ ( + .CI(plm_fsm_cc_timer_reg_count_cry[12]), + .DI(plm_fsm_cc_timer_GND_1858), + .LO(plm_fsm_cc_timer_reg_count_cry[13]), + .S(plm_fsm_cc_timer_reg_count_qxu[13]) + ); + XORCY plm_fsm_cc_timer_reg_count_s_13_ ( + .CI(plm_fsm_cc_timer_reg_count_cry[12]), + .LI(plm_fsm_cc_timer_reg_count_qxu[13]), + .O(plm_fsm_cc_timer_reg_count_s[13]) + ); + MUXCY_L plm_fsm_cc_timer_reg_count_cry_14_ ( + .CI(plm_fsm_cc_timer_reg_count_cry[13]), + .DI(plm_fsm_cc_timer_GND_1858), + .LO(plm_fsm_cc_timer_reg_count_cry[14]), + .S(plm_fsm_cc_timer_reg_count_qxu[14]) + ); + XORCY plm_fsm_cc_timer_reg_count_s_14_ ( + .CI(plm_fsm_cc_timer_reg_count_cry[13]), + .LI(plm_fsm_cc_timer_reg_count_qxu[14]), + .O(plm_fsm_cc_timer_reg_count_s[14]) + ); + MUXCY_L plm_fsm_cc_timer_reg_count_cry_15_ ( + .CI(plm_fsm_cc_timer_reg_count_cry[14]), + .DI(plm_fsm_cc_timer_GND_1858), + .LO(plm_fsm_cc_timer_reg_count_cry[15]), + .S(plm_fsm_cc_timer_reg_count_qxu[15]) + ); + XORCY plm_fsm_cc_timer_reg_count_s_15_ ( + .CI(plm_fsm_cc_timer_reg_count_cry[14]), + .LI(plm_fsm_cc_timer_reg_count_qxu[15]), + .O(plm_fsm_cc_timer_reg_count_s[15]) + ); + MUXCY_L plm_fsm_cc_timer_reg_count_cry_16_ ( + .CI(plm_fsm_cc_timer_reg_count_cry[15]), + .DI(plm_fsm_cc_timer_GND_1858), + .LO(plm_fsm_cc_timer_reg_count_cry[16]), + .S(plm_fsm_cc_timer_reg_count_qxu[16]) + ); + XORCY plm_fsm_cc_timer_reg_count_s_16_ ( + .CI(plm_fsm_cc_timer_reg_count_cry[15]), + .LI(plm_fsm_cc_timer_reg_count_qxu[16]), + .O(plm_fsm_cc_timer_reg_count_s[16]) + ); + MUXCY_L plm_fsm_cc_timer_reg_count_cry_17_ ( + .CI(plm_fsm_cc_timer_reg_count_cry[16]), + .DI(plm_fsm_cc_timer_GND_1858), + .LO(plm_fsm_cc_timer_reg_count_cry[17]), + .S(plm_fsm_cc_timer_reg_count_qxu[17]) + ); + XORCY plm_fsm_cc_timer_reg_count_s_17_ ( + .CI(plm_fsm_cc_timer_reg_count_cry[16]), + .LI(plm_fsm_cc_timer_reg_count_qxu[17]), + .O(plm_fsm_cc_timer_reg_count_s[17]) + ); + MUXCY_L plm_fsm_cc_timer_reg_count_cry_18_ ( + .CI(plm_fsm_cc_timer_reg_count_cry[17]), + .DI(plm_fsm_cc_timer_GND_1858), + .LO(plm_fsm_cc_timer_reg_count_cry[18]), + .S(plm_fsm_cc_timer_reg_count_qxu[18]) + ); + XORCY plm_fsm_cc_timer_reg_count_s_18_ ( + .CI(plm_fsm_cc_timer_reg_count_cry[17]), + .LI(plm_fsm_cc_timer_reg_count_qxu[18]), + .O(plm_fsm_cc_timer_reg_count_s[18]) + ); + MUXCY_L plm_fsm_cc_timer_reg_count_cry_19_ ( + .CI(plm_fsm_cc_timer_reg_count_cry[18]), + .DI(plm_fsm_cc_timer_GND_1858), + .LO(plm_fsm_cc_timer_reg_count_cry[19]), + .S(plm_fsm_cc_timer_reg_count_qxu[19]) + ); + XORCY plm_fsm_cc_timer_reg_count_s_19_ ( + .CI(plm_fsm_cc_timer_reg_count_cry[18]), + .LI(plm_fsm_cc_timer_reg_count_qxu[19]), + .O(plm_fsm_cc_timer_reg_count_s[19]) + ); + MUXCY_L plm_fsm_cc_timer_reg_count_cry_20_ ( + .CI(plm_fsm_cc_timer_reg_count_cry[19]), + .DI(plm_fsm_cc_timer_GND_1858), + .LO(plm_fsm_cc_timer_reg_count_cry[20]), + .S(plm_fsm_cc_timer_reg_count_qxu[20]) + ); + XORCY plm_fsm_cc_timer_reg_count_s_20_ ( + .CI(plm_fsm_cc_timer_reg_count_cry[19]), + .LI(plm_fsm_cc_timer_reg_count_qxu[20]), + .O(plm_fsm_cc_timer_reg_count_s[20]) + ); + MUXCY_L plm_fsm_cc_timer_reg_count_cry_21_ ( + .CI(plm_fsm_cc_timer_reg_count_cry[20]), + .DI(plm_fsm_cc_timer_GND_1858), + .LO(plm_fsm_cc_timer_reg_count_cry[21]), + .S(plm_fsm_cc_timer_reg_count_qxu[21]) + ); + XORCY plm_fsm_cc_timer_reg_count_s_21_ ( + .CI(plm_fsm_cc_timer_reg_count_cry[20]), + .LI(plm_fsm_cc_timer_reg_count_qxu[21]), + .O(plm_fsm_cc_timer_reg_count_s[21]) + ); + XORCY plm_fsm_cc_timer_reg_count_s_22_ ( + .CI(plm_fsm_cc_timer_reg_count_cry[21]), + .LI(plm_fsm_cc_timer_reg_count_qxu[22]), + .O(plm_fsm_cc_timer_reg_count_s[22]) + ); + defparam plm_fsm_cc_timer_count_i_m3_i_m3_i_m3_i_m3_0_18_.INIT = 8'hD8; + LUT3 plm_fsm_cc_timer_count_i_m3_i_m3_i_m3_i_m3_0_18_ ( + .I0(cfg_cfg_6102[507]), + .I1(plm_fsm_cc_timer_reg_count[10]), + .I2(plm_fsm_cc_timer_reg_count[18]), + .O(plm_fsm_cc_timer_N_63743) + ); + defparam plm_fsm_cc_timer_count_i_m3_i_m3_i_m3_i_m3_0_19_.INIT = 8'hD8; + LUT3_L plm_fsm_cc_timer_count_i_m3_i_m3_i_m3_i_m3_0_19_ ( + .I0(cfg_cfg_6102[507]), + .I1(plm_fsm_cc_timer_reg_count[11]), + .I2(plm_fsm_cc_timer_reg_count[19]), + .LO(plm_fsm_cc_timer_N_63744) + ); + defparam plm_fsm_cc_timer_count_i_m3_i_m3_i_m3_i_m3_0_20_.INIT = 8'hD8; + LUT3_L plm_fsm_cc_timer_count_i_m3_i_m3_i_m3_i_m3_0_20_ ( + .I0(cfg_cfg_6102[507]), + .I1(plm_fsm_cc_timer_reg_count[12]), + .I2(plm_fsm_cc_timer_reg_count[20]), + .LO(plm_fsm_cc_timer_N_63745) + ); + defparam plm_fsm_cc_timer_un1_expired_2ms_0_a2_0_a3_0.INIT = 16'h0415; + LUT4 plm_fsm_cc_timer_un1_expired_2ms_0_a2_0_a3_0 ( + .I0(plm_fsm_cc_timer_N_63744), + .I1(cfg_cfg_6102[507]), + .I2(plm_fsm_cc_timer_reg_count[14]), + .I3(plm_fsm_cc_timer_reg_count[22]), + .O(plm_fsm_cc_timer_un1_expired_2ms_0_a2_0_a3_0_1860) + ); + defparam plm_fsm_cc_timer_un1_expired_2ms_0_a2_0_a3_1.INIT = 16'h0415; + LUT4 plm_fsm_cc_timer_un1_expired_2ms_0_a2_0_a3_1 ( + .I0(plm_fsm_cc_timer_N_63745), + .I1(cfg_cfg_6102[507]), + .I2(plm_fsm_cc_timer_reg_count[13]), + .I3(plm_fsm_cc_timer_reg_count[21]), + .O(plm_fsm_cc_timer_un1_expired_2ms_0_a2_0_a3_1_1859) + ); + defparam plm_fsm_cc_timer_un1_expired_2ms_0_a2_0_a3.INIT = 8'h40; + LUT3 plm_fsm_cc_timer_un1_expired_2ms_0_a2_0_a3 ( + .I0(plm_fsm_cc_timer_N_63743), + .I1(plm_fsm_cc_timer_un1_expired_2ms_0_a2_0_a3_0_1860), + .I2(plm_fsm_cc_timer_un1_expired_2ms_0_a2_0_a3_1_1859), + .O(plm_fsm_N_63496) + ); + defparam plm_fsm_cc_timer_expired_0_o3_0_0.INIT = 4'h1; + LUT2 plm_fsm_cc_timer_expired_0_o3_0_0 ( + .I0(N_56513_i), + .I1(plm_fsm_N_63496), + .O(plm_fsm_N_36844_i) + ); + FDC plm_fsm_cc_timer_reg_count_22_ ( + .C(mgt_clk), + .D(plm_fsm_cc_timer_reg_count_s[22]), + .Q(plm_fsm_cc_timer_reg_count[22]), + .CLR(plm_rst) + ); + FDC plm_fsm_cc_timer_reg_count_21_ ( + .C(mgt_clk), + .D(plm_fsm_cc_timer_reg_count_s[21]), + .Q(plm_fsm_cc_timer_reg_count[21]), + .CLR(plm_rst) + ); + FDC plm_fsm_cc_timer_reg_count_20_ ( + .C(mgt_clk), + .D(plm_fsm_cc_timer_reg_count_s[20]), + .Q(plm_fsm_cc_timer_reg_count[20]), + .CLR(plm_rst) + ); + FDC plm_fsm_cc_timer_reg_count_19_ ( + .C(mgt_clk), + .D(plm_fsm_cc_timer_reg_count_s[19]), + .Q(plm_fsm_cc_timer_reg_count[19]), + .CLR(plm_rst) + ); + FDC plm_fsm_cc_timer_reg_count_18_ ( + .C(mgt_clk), + .D(plm_fsm_cc_timer_reg_count_s[18]), + .Q(plm_fsm_cc_timer_reg_count[18]), + .CLR(plm_rst) + ); + FDC plm_fsm_cc_timer_reg_count_17_ ( + .C(mgt_clk), + .D(plm_fsm_cc_timer_reg_count_s[17]), + .Q(plm_fsm_cc_timer_reg_count[17]), + .CLR(plm_rst) + ); + FDC plm_fsm_cc_timer_reg_count_16_ ( + .C(mgt_clk), + .D(plm_fsm_cc_timer_reg_count_s[16]), + .Q(plm_fsm_cc_timer_reg_count[16]), + .CLR(plm_rst) + ); + FDC plm_fsm_cc_timer_reg_count_15_ ( + .C(mgt_clk), + .D(plm_fsm_cc_timer_reg_count_s[15]), + .Q(plm_fsm_cc_timer_reg_count[15]), + .CLR(plm_rst) + ); + FDC plm_fsm_cc_timer_reg_count_14_ ( + .C(mgt_clk), + .D(plm_fsm_cc_timer_reg_count_s[14]), + .Q(plm_fsm_cc_timer_reg_count[14]), + .CLR(plm_rst) + ); + FDC plm_fsm_cc_timer_reg_count_13_ ( + .C(mgt_clk), + .D(plm_fsm_cc_timer_reg_count_s[13]), + .Q(plm_fsm_cc_timer_reg_count[13]), + .CLR(plm_rst) + ); + FDC plm_fsm_cc_timer_reg_count_12_ ( + .C(mgt_clk), + .D(plm_fsm_cc_timer_reg_count_s[12]), + .Q(plm_fsm_cc_timer_reg_count[12]), + .CLR(plm_rst) + ); + FDC plm_fsm_cc_timer_reg_count_11_ ( + .C(mgt_clk), + .D(plm_fsm_cc_timer_reg_count_s[11]), + .Q(plm_fsm_cc_timer_reg_count[11]), + .CLR(plm_rst) + ); + FDC plm_fsm_cc_timer_reg_count_10_ ( + .C(mgt_clk), + .D(plm_fsm_cc_timer_reg_count_s[10]), + .Q(plm_fsm_cc_timer_reg_count[10]), + .CLR(plm_rst) + ); + FDC plm_fsm_cc_timer_reg_count_9_ ( + .C(mgt_clk), + .D(plm_fsm_cc_timer_reg_count_s[9]), + .Q(plm_fsm_cc_timer_reg_count[9]), + .CLR(plm_rst) + ); + FDC plm_fsm_cc_timer_reg_count_8_ ( + .C(mgt_clk), + .D(plm_fsm_cc_timer_reg_count_s[8]), + .Q(plm_fsm_cc_timer_reg_count[8]), + .CLR(plm_rst) + ); + FDC plm_fsm_cc_timer_reg_count_7_ ( + .C(mgt_clk), + .D(plm_fsm_cc_timer_reg_count_s[7]), + .Q(plm_fsm_cc_timer_reg_count[7]), + .CLR(plm_rst) + ); + FDC plm_fsm_cc_timer_reg_count_6_ ( + .C(mgt_clk), + .D(plm_fsm_cc_timer_reg_count_s[6]), + .Q(plm_fsm_cc_timer_reg_count[6]), + .CLR(plm_rst) + ); + FDC plm_fsm_cc_timer_reg_count_5_ ( + .C(mgt_clk), + .D(plm_fsm_cc_timer_reg_count_s[5]), + .Q(plm_fsm_cc_timer_reg_count[5]), + .CLR(plm_rst) + ); + FDC plm_fsm_cc_timer_reg_count_4_ ( + .C(mgt_clk), + .D(plm_fsm_cc_timer_reg_count_s[4]), + .Q(plm_fsm_cc_timer_reg_count[4]), + .CLR(plm_rst) + ); + FDC plm_fsm_cc_timer_reg_count_3_ ( + .C(mgt_clk), + .D(plm_fsm_cc_timer_reg_count_s[3]), + .Q(plm_fsm_cc_timer_reg_count[3]), + .CLR(plm_rst) + ); + FDC plm_fsm_cc_timer_reg_count_2_ ( + .C(mgt_clk), + .D(plm_fsm_cc_timer_reg_count_s[2]), + .Q(plm_fsm_cc_timer_reg_count[2]), + .CLR(plm_rst) + ); + FDC plm_fsm_cc_timer_reg_count_1_ ( + .C(mgt_clk), + .D(plm_fsm_cc_timer_reg_count_s[1]), + .Q(plm_fsm_cc_timer_reg_count[1]), + .CLR(plm_rst) + ); + FDC plm_fsm_cc_timer_reg_count_0_ ( + .C(mgt_clk), + .D(plm_fsm_cc_timer_reg_count_s[0]), + .Q(plm_fsm_cc_timer_reg_count[0]), + .CLR(plm_rst) + ); + defparam plm_fsm_cc_timer_reg_count_qxu_0_0_.INIT = 4'h4; + LUT2_L plm_fsm_cc_timer_reg_count_qxu_0_0_ ( + .I0(N_56513_i), + .I1(plm_fsm_cc_timer_reg_count[0]), + .LO(plm_fsm_cc_timer_reg_count_qxu[0]) + ); + defparam plm_fsm_cc_timer_reg_count_qxu_0_1_.INIT = 4'h4; + LUT2_L plm_fsm_cc_timer_reg_count_qxu_0_1_ ( + .I0(N_56513_i), + .I1(plm_fsm_cc_timer_reg_count[1]), + .LO(plm_fsm_cc_timer_reg_count_qxu[1]) + ); + defparam plm_fsm_cc_timer_reg_count_qxu_0_2_.INIT = 4'h4; + LUT2_L plm_fsm_cc_timer_reg_count_qxu_0_2_ ( + .I0(N_56513_i), + .I1(plm_fsm_cc_timer_reg_count[2]), + .LO(plm_fsm_cc_timer_reg_count_qxu[2]) + ); + defparam plm_fsm_cc_timer_reg_count_qxu_0_3_.INIT = 4'h4; + LUT2_L plm_fsm_cc_timer_reg_count_qxu_0_3_ ( + .I0(N_56513_i), + .I1(plm_fsm_cc_timer_reg_count[3]), + .LO(plm_fsm_cc_timer_reg_count_qxu[3]) + ); + defparam plm_fsm_cc_timer_reg_count_qxu_0_4_.INIT = 4'h4; + LUT2_L plm_fsm_cc_timer_reg_count_qxu_0_4_ ( + .I0(N_56513_i), + .I1(plm_fsm_cc_timer_reg_count[4]), + .LO(plm_fsm_cc_timer_reg_count_qxu[4]) + ); + defparam plm_fsm_cc_timer_reg_count_qxu_0_5_.INIT = 4'h4; + LUT2_L plm_fsm_cc_timer_reg_count_qxu_0_5_ ( + .I0(N_56513_i), + .I1(plm_fsm_cc_timer_reg_count[5]), + .LO(plm_fsm_cc_timer_reg_count_qxu[5]) + ); + defparam plm_fsm_cc_timer_reg_count_qxu_0_6_.INIT = 4'h4; + LUT2_L plm_fsm_cc_timer_reg_count_qxu_0_6_ ( + .I0(N_56513_i), + .I1(plm_fsm_cc_timer_reg_count[6]), + .LO(plm_fsm_cc_timer_reg_count_qxu[6]) + ); + defparam plm_fsm_cc_timer_reg_count_qxu_0_7_.INIT = 4'h4; + LUT2_L plm_fsm_cc_timer_reg_count_qxu_0_7_ ( + .I0(N_56513_i), + .I1(plm_fsm_cc_timer_reg_count[7]), + .LO(plm_fsm_cc_timer_reg_count_qxu[7]) + ); + defparam plm_fsm_cc_timer_reg_count_qxu_0_8_.INIT = 4'h4; + LUT2_L plm_fsm_cc_timer_reg_count_qxu_0_8_ ( + .I0(N_56513_i), + .I1(plm_fsm_cc_timer_reg_count[8]), + .LO(plm_fsm_cc_timer_reg_count_qxu[8]) + ); + defparam plm_fsm_cc_timer_reg_count_qxu_0_9_.INIT = 4'h4; + LUT2_L plm_fsm_cc_timer_reg_count_qxu_0_9_ ( + .I0(N_56513_i), + .I1(plm_fsm_cc_timer_reg_count[9]), + .LO(plm_fsm_cc_timer_reg_count_qxu[9]) + ); + defparam plm_fsm_cc_timer_reg_count_qxu_0_10_.INIT = 4'h4; + LUT2_L plm_fsm_cc_timer_reg_count_qxu_0_10_ ( + .I0(N_56513_i), + .I1(plm_fsm_cc_timer_reg_count[10]), + .LO(plm_fsm_cc_timer_reg_count_qxu[10]) + ); + defparam plm_fsm_cc_timer_reg_count_qxu_0_11_.INIT = 4'h4; + LUT2_L plm_fsm_cc_timer_reg_count_qxu_0_11_ ( + .I0(N_56513_i), + .I1(plm_fsm_cc_timer_reg_count[11]), + .LO(plm_fsm_cc_timer_reg_count_qxu[11]) + ); + defparam plm_fsm_cc_timer_reg_count_qxu_0_12_.INIT = 4'h4; + LUT2_L plm_fsm_cc_timer_reg_count_qxu_0_12_ ( + .I0(N_56513_i), + .I1(plm_fsm_cc_timer_reg_count[12]), + .LO(plm_fsm_cc_timer_reg_count_qxu[12]) + ); + defparam plm_fsm_cc_timer_reg_count_qxu_0_13_.INIT = 4'h4; + LUT2_L plm_fsm_cc_timer_reg_count_qxu_0_13_ ( + .I0(N_56513_i), + .I1(plm_fsm_cc_timer_reg_count[13]), + .LO(plm_fsm_cc_timer_reg_count_qxu[13]) + ); + defparam plm_fsm_cc_timer_reg_count_qxu_0_14_.INIT = 4'h4; + LUT2_L plm_fsm_cc_timer_reg_count_qxu_0_14_ ( + .I0(N_56513_i), + .I1(plm_fsm_cc_timer_reg_count[14]), + .LO(plm_fsm_cc_timer_reg_count_qxu[14]) + ); + defparam plm_fsm_cc_timer_reg_count_qxu_0_15_.INIT = 4'h4; + LUT2_L plm_fsm_cc_timer_reg_count_qxu_0_15_ ( + .I0(N_56513_i), + .I1(plm_fsm_cc_timer_reg_count[15]), + .LO(plm_fsm_cc_timer_reg_count_qxu[15]) + ); + defparam plm_fsm_cc_timer_reg_count_qxu_0_16_.INIT = 4'h4; + LUT2_L plm_fsm_cc_timer_reg_count_qxu_0_16_ ( + .I0(N_56513_i), + .I1(plm_fsm_cc_timer_reg_count[16]), + .LO(plm_fsm_cc_timer_reg_count_qxu[16]) + ); + defparam plm_fsm_cc_timer_reg_count_qxu_0_17_.INIT = 4'h4; + LUT2_L plm_fsm_cc_timer_reg_count_qxu_0_17_ ( + .I0(N_56513_i), + .I1(plm_fsm_cc_timer_reg_count[17]), + .LO(plm_fsm_cc_timer_reg_count_qxu[17]) + ); + defparam plm_fsm_cc_timer_reg_count_qxu_0_18_.INIT = 4'h4; + LUT2_L plm_fsm_cc_timer_reg_count_qxu_0_18_ ( + .I0(N_56513_i), + .I1(plm_fsm_cc_timer_reg_count[18]), + .LO(plm_fsm_cc_timer_reg_count_qxu[18]) + ); + defparam plm_fsm_cc_timer_reg_count_qxu_0_19_.INIT = 4'h4; + LUT2_L plm_fsm_cc_timer_reg_count_qxu_0_19_ ( + .I0(N_56513_i), + .I1(plm_fsm_cc_timer_reg_count[19]), + .LO(plm_fsm_cc_timer_reg_count_qxu[19]) + ); + defparam plm_fsm_cc_timer_reg_count_qxu_0_20_.INIT = 4'h4; + LUT2_L plm_fsm_cc_timer_reg_count_qxu_0_20_ ( + .I0(N_56513_i), + .I1(plm_fsm_cc_timer_reg_count[20]), + .LO(plm_fsm_cc_timer_reg_count_qxu[20]) + ); + defparam plm_fsm_cc_timer_reg_count_qxu_0_21_.INIT = 4'h4; + LUT2_L plm_fsm_cc_timer_reg_count_qxu_0_21_ ( + .I0(N_56513_i), + .I1(plm_fsm_cc_timer_reg_count[21]), + .LO(plm_fsm_cc_timer_reg_count_qxu[21]) + ); + defparam plm_fsm_cc_timer_reg_count_qxu_0_22_.INIT = 4'h4; + LUT2_L plm_fsm_cc_timer_reg_count_qxu_0_22_ ( + .I0(N_56513_i), + .I1(plm_fsm_cc_timer_reg_count[22]), + .LO(plm_fsm_cc_timer_reg_count_qxu[22]) + ); + VCC plm_fsm_cc_counter0_VCC ( + .P(plm_fsm_cc_counter0_VCC_1861) + ); + MUXCY_L plm_fsm_cc_counter0_reg_rx_count_cry_0_ ( + .CI(N_15208_i_i_72), + .DI(plm_fsm_cc_counter0_VCC_1861), + .LO(plm_fsm_cc_counter0_reg_rx_count_cry[0]), + .S(plm_fsm_cc_counter0_reg_rx_count_qxu[0]) + ); + XORCY plm_fsm_cc_counter0_reg_rx_count_s_0_ ( + .CI(N_15208_i_i_72), + .LI(plm_fsm_cc_counter0_reg_rx_count_qxu[0]), + .O(plm_fsm_cc_counter0_reg_rx_count_s[0]) + ); + MUXCY_L plm_fsm_cc_counter0_reg_rx_count_cry_1_ ( + .CI(plm_fsm_cc_counter0_reg_rx_count_cry[0]), + .DI(plm_fsm_cc_counter0_VCC_1861), + .LO(plm_fsm_cc_counter0_reg_rx_count_cry[1]), + .S(plm_fsm_cc_counter0_reg_rx_count_qxu[1]) + ); + XORCY plm_fsm_cc_counter0_reg_rx_count_s_1_ ( + .CI(plm_fsm_cc_counter0_reg_rx_count_cry[0]), + .LI(plm_fsm_cc_counter0_reg_rx_count_qxu[1]), + .O(plm_fsm_cc_counter0_reg_rx_count_s[1]) + ); + MUXCY_L plm_fsm_cc_counter0_reg_rx_count_cry_2_ ( + .CI(plm_fsm_cc_counter0_reg_rx_count_cry[1]), + .DI(plm_fsm_cc_counter0_VCC_1861), + .LO(plm_fsm_cc_counter0_reg_rx_count_cry[2]), + .S(plm_fsm_cc_counter0_reg_rx_count_qxu[2]) + ); + XORCY plm_fsm_cc_counter0_reg_rx_count_s_2_ ( + .CI(plm_fsm_cc_counter0_reg_rx_count_cry[1]), + .LI(plm_fsm_cc_counter0_reg_rx_count_qxu[2]), + .O(plm_fsm_cc_counter0_reg_rx_count_s[2]) + ); + MUXCY_L plm_fsm_cc_counter0_reg_rx_count_cry_3_ ( + .CI(plm_fsm_cc_counter0_reg_rx_count_cry[2]), + .DI(plm_fsm_cc_counter0_VCC_1861), + .LO(plm_fsm_cc_counter0_reg_rx_count_cry[3]), + .S(plm_fsm_cc_counter0_reg_rx_count_qxu[3]) + ); + XORCY plm_fsm_cc_counter0_reg_rx_count_s_3_ ( + .CI(plm_fsm_cc_counter0_reg_rx_count_cry[2]), + .LI(plm_fsm_cc_counter0_reg_rx_count_qxu[3]), + .O(plm_fsm_cc_counter0_reg_rx_count_s[3]) + ); + MUXCY_L plm_fsm_cc_counter0_reg_rx_count_cry_4_ ( + .CI(plm_fsm_cc_counter0_reg_rx_count_cry[3]), + .DI(plm_fsm_cc_counter0_VCC_1861), + .LO(plm_fsm_cc_counter0_reg_rx_count_cry[4]), + .S(plm_fsm_cc_counter0_reg_rx_count_qxu[4]) + ); + XORCY plm_fsm_cc_counter0_reg_rx_count_s_4_ ( + .CI(plm_fsm_cc_counter0_reg_rx_count_cry[3]), + .LI(plm_fsm_cc_counter0_reg_rx_count_qxu[4]), + .O(plm_fsm_cc_counter0_reg_rx_count_s[4]) + ); + MUXCY_L plm_fsm_cc_counter0_reg_rx_count_cry_5_ ( + .CI(plm_fsm_cc_counter0_reg_rx_count_cry[4]), + .DI(plm_fsm_cc_counter0_VCC_1861), + .LO(plm_fsm_cc_counter0_reg_rx_count_cry[5]), + .S(plm_fsm_cc_counter0_reg_rx_count_qxu[5]) + ); + XORCY plm_fsm_cc_counter0_reg_rx_count_s_5_ ( + .CI(plm_fsm_cc_counter0_reg_rx_count_cry[4]), + .LI(plm_fsm_cc_counter0_reg_rx_count_qxu[5]), + .O(plm_fsm_cc_counter0_reg_rx_count_s[5]) + ); + MUXCY_L plm_fsm_cc_counter0_reg_rx_count_cry_6_ ( + .CI(plm_fsm_cc_counter0_reg_rx_count_cry[5]), + .DI(plm_fsm_cc_counter0_VCC_1861), + .LO(plm_fsm_cc_counter0_reg_rx_count_cry[6]), + .S(plm_fsm_cc_counter0_reg_rx_count_qxu[6]) + ); + XORCY plm_fsm_cc_counter0_reg_rx_count_s_6_ ( + .CI(plm_fsm_cc_counter0_reg_rx_count_cry[5]), + .LI(plm_fsm_cc_counter0_reg_rx_count_qxu[6]), + .O(plm_fsm_cc_counter0_reg_rx_count_s[6]) + ); + XORCY plm_fsm_cc_counter0_reg_rx_count_s_7_ ( + .CI(plm_fsm_cc_counter0_reg_rx_count_cry[6]), + .LI(plm_fsm_cc_counter0_reg_rx_count_qxu[7]), + .O(plm_fsm_cc_counter0_reg_rx_count_s[7]) + ); + MUXCY_L plm_fsm_cc_counter0_reg_tx_count_cry_0_ ( + .CI(plm_fsm_cc_counter0_N_29090_i_i_1862), + .DI(plm_fsm_cc_counter0_VCC_1861), + .LO(plm_fsm_cc_counter0_reg_tx_count_cry[0]), + .S(plm_fsm_cc_counter0_reg_tx_count_qxu[0]) + ); + XORCY plm_fsm_cc_counter0_reg_tx_count_s_0_ ( + .CI(plm_fsm_cc_counter0_N_29090_i_i_1862), + .LI(plm_fsm_cc_counter0_reg_tx_count_qxu[0]), + .O(plm_fsm_cc_counter0_reg_tx_count_s[0]) + ); + MUXCY_L plm_fsm_cc_counter0_reg_tx_count_cry_1_ ( + .CI(plm_fsm_cc_counter0_reg_tx_count_cry[0]), + .DI(plm_fsm_cc_counter0_VCC_1861), + .LO(plm_fsm_cc_counter0_reg_tx_count_cry[1]), + .S(plm_fsm_cc_counter0_reg_tx_count_qxu[1]) + ); + XORCY plm_fsm_cc_counter0_reg_tx_count_s_1_ ( + .CI(plm_fsm_cc_counter0_reg_tx_count_cry[0]), + .LI(plm_fsm_cc_counter0_reg_tx_count_qxu[1]), + .O(plm_fsm_cc_counter0_reg_tx_count_s[1]) + ); + MUXCY_L plm_fsm_cc_counter0_reg_tx_count_cry_2_ ( + .CI(plm_fsm_cc_counter0_reg_tx_count_cry[1]), + .DI(plm_fsm_cc_counter0_VCC_1861), + .LO(plm_fsm_cc_counter0_reg_tx_count_cry[2]), + .S(plm_fsm_cc_counter0_reg_tx_count_qxu[2]) + ); + XORCY plm_fsm_cc_counter0_reg_tx_count_s_2_ ( + .CI(plm_fsm_cc_counter0_reg_tx_count_cry[1]), + .LI(plm_fsm_cc_counter0_reg_tx_count_qxu[2]), + .O(plm_fsm_cc_counter0_reg_tx_count_s[2]) + ); + MUXCY_L plm_fsm_cc_counter0_reg_tx_count_cry_3_ ( + .CI(plm_fsm_cc_counter0_reg_tx_count_cry[2]), + .DI(plm_fsm_cc_counter0_VCC_1861), + .LO(plm_fsm_cc_counter0_reg_tx_count_cry[3]), + .S(plm_fsm_cc_counter0_reg_tx_count_qxu[3]) + ); + XORCY plm_fsm_cc_counter0_reg_tx_count_s_3_ ( + .CI(plm_fsm_cc_counter0_reg_tx_count_cry[2]), + .LI(plm_fsm_cc_counter0_reg_tx_count_qxu[3]), + .O(plm_fsm_cc_counter0_reg_tx_count_s[3]) + ); + MUXCY_L plm_fsm_cc_counter0_reg_tx_count_cry_4_ ( + .CI(plm_fsm_cc_counter0_reg_tx_count_cry[3]), + .DI(plm_fsm_cc_counter0_VCC_1861), + .LO(plm_fsm_cc_counter0_reg_tx_count_cry[4]), + .S(plm_fsm_cc_counter0_reg_tx_count_qxu[4]) + ); + XORCY plm_fsm_cc_counter0_reg_tx_count_s_4_ ( + .CI(plm_fsm_cc_counter0_reg_tx_count_cry[3]), + .LI(plm_fsm_cc_counter0_reg_tx_count_qxu[4]), + .O(plm_fsm_cc_counter0_reg_tx_count_s[4]) + ); + MUXCY_L plm_fsm_cc_counter0_reg_tx_count_cry_5_ ( + .CI(plm_fsm_cc_counter0_reg_tx_count_cry[4]), + .DI(plm_fsm_cc_counter0_VCC_1861), + .LO(plm_fsm_cc_counter0_reg_tx_count_cry[5]), + .S(plm_fsm_cc_counter0_reg_tx_count_qxu[5]) + ); + XORCY plm_fsm_cc_counter0_reg_tx_count_s_5_ ( + .CI(plm_fsm_cc_counter0_reg_tx_count_cry[4]), + .LI(plm_fsm_cc_counter0_reg_tx_count_qxu[5]), + .O(plm_fsm_cc_counter0_reg_tx_count_s[5]) + ); + MUXCY_L plm_fsm_cc_counter0_reg_tx_count_cry_6_ ( + .CI(plm_fsm_cc_counter0_reg_tx_count_cry[5]), + .DI(plm_fsm_cc_counter0_VCC_1861), + .LO(plm_fsm_cc_counter0_reg_tx_count_cry[6]), + .S(plm_fsm_cc_counter0_reg_tx_count_qxu[6]) + ); + XORCY plm_fsm_cc_counter0_reg_tx_count_s_6_ ( + .CI(plm_fsm_cc_counter0_reg_tx_count_cry[5]), + .LI(plm_fsm_cc_counter0_reg_tx_count_qxu[6]), + .O(plm_fsm_cc_counter0_reg_tx_count_s[6]) + ); + XORCY plm_fsm_cc_counter0_reg_tx_count_s_7_ ( + .CI(plm_fsm_cc_counter0_reg_tx_count_cry[6]), + .LI(plm_fsm_cc_counter0_reg_tx_count_qxu[7]), + .O(plm_fsm_cc_counter0_reg_tx_count_s[7]) + ); + defparam plm_fsm_cc_counter0_loadable_rx_counter_un1_reg_rx_count_0_a3_4.INIT = 16'h0001; + LUT4 plm_fsm_cc_counter0_loadable_rx_counter_un1_reg_rx_count_0_a3_4 ( + .I0(plm_fsm_cc_counter0_reg_rx_count[0]), + .I1(plm_fsm_cc_counter0_reg_rx_count[1]), + .I2(plm_fsm_cc_counter0_reg_rx_count[2]), + .I3(plm_fsm_cc_counter0_reg_rx_count[3]), + .O(plm_fsm_cc_counter0_un1_reg_rx_count_0_a3_4) + ); + defparam plm_fsm_cc_counter0_loadable_rx_counter_un1_reg_rx_count_0_a3_5.INIT = 16'h0001; + LUT4 plm_fsm_cc_counter0_loadable_rx_counter_un1_reg_rx_count_0_a3_5 ( + .I0(plm_fsm_cc_counter0_reg_rx_count[4]), + .I1(plm_fsm_cc_counter0_reg_rx_count[5]), + .I2(plm_fsm_cc_counter0_reg_rx_count[6]), + .I3(plm_fsm_cc_counter0_reg_rx_count[7]), + .O(plm_fsm_cc_counter0_un1_reg_rx_count_0_a3_5) + ); + defparam plm_fsm_cc_counter0_loadable_tx_counter_un1_reg_tx_count_0_a3_4.INIT = 16'h0001; + LUT4 plm_fsm_cc_counter0_loadable_tx_counter_un1_reg_tx_count_0_a3_4 ( + .I0(plm_fsm_cc_counter0_reg_tx_count[0]), + .I1(plm_fsm_cc_counter0_reg_tx_count[1]), + .I2(plm_fsm_cc_counter0_reg_tx_count[2]), + .I3(plm_fsm_cc_counter0_reg_tx_count[3]), + .O(plm_fsm_cc_counter0_un1_reg_tx_count_0_a3_4) + ); + defparam plm_fsm_cc_counter0_loadable_tx_counter_un1_reg_tx_count_0_a3_5.INIT = 16'h0001; + LUT4 plm_fsm_cc_counter0_loadable_tx_counter_un1_reg_tx_count_0_a3_5 ( + .I0(plm_fsm_cc_counter0_reg_tx_count[4]), + .I1(plm_fsm_cc_counter0_reg_tx_count[5]), + .I2(plm_fsm_cc_counter0_reg_tx_count[6]), + .I3(plm_fsm_cc_counter0_reg_tx_count[7]), + .O(plm_fsm_cc_counter0_un1_reg_tx_count_0_a3_5) + ); + defparam plm_fsm_cc_counter0_un1_enable_1_0_a3_i_0_0.INIT = 4'h2; + LUT2 plm_fsm_cc_counter0_un1_enable_1_0_a3_i_0_0 ( + .I0(plm_fsm_cc_counter0_N_56149_i), + .I1(plm_fsm_cc_counter0_reg_tx_expired_1866), + .O(plm_fsm_cc_counter0_N_29090_i) + ); + defparam plm_fsm_cc_counter0_N_87204_i.INIT = 8'hD5; + LUT3 plm_fsm_cc_counter0_N_87204_i ( + .I0(plm_fsm_cc_counter0_N_56149_i), + .I1(plm_fsm_cc_counter0_un1_reg_tx_count_0_a3_4), + .I2(plm_fsm_cc_counter0_un1_reg_tx_count_0_a3_5), + .O(plm_fsm_cc_counter0_N_87204_i_1865) + ); + defparam plm_fsm_cc_counter0_loadable_rx_counter_N_87211_i.INIT = 8'hEA; + LUT3 plm_fsm_cc_counter0_loadable_rx_counter_N_87211_i ( + .I0(N_56513_i), + .I1(plm_fsm_cc_counter0_un1_reg_rx_count_0_a3_4), + .I2(plm_fsm_cc_counter0_un1_reg_rx_count_0_a3_5), + .O(plm_fsm_cc_counter0_N_87211_i) + ); + defparam plm_fsm_cc_counter0_N_87210_i.INIT = 16'hF0F2; + LUT4 plm_fsm_cc_counter0_N_87210_i ( + .I0(plm_reg_ts2_1), + .I1(N_56156_i), + .I2(N_56513_i), + .I3(plm_fsm_cc_counter0_reg_rx_expired_71), + .O(plm_fsm_cc_counter0_N_87210_i_1867) + ); + defparam plm_fsm_cc_counter0_flagit_reg_expired_5_i_0_0.INIT = 8'h40; + LUT3_L plm_fsm_cc_counter0_flagit_reg_expired_5_i_0_0 ( + .I0(N_56513_i), + .I1(plm_fsm_cc_counter0_reg_rx_expired_71), + .I2(plm_fsm_cc_counter0_reg_tx_expired_1866), + .LO(plm_fsm_cc_counter0_N_28777_i) + ); + defparam plm_fsm_cc_counter0_un1_enable_2_i_0_0_0_o2.INIT = 8'hA8; + LUT3 plm_fsm_cc_counter0_un1_enable_2_i_0_0_0_o2 ( + .I0(plm_fsm_cc_counter0_reg_oneshot_1864), + .I1(plm_fsm_reg_state_10__1792), + .I2(plm_fsm_reg_state_9__1795), + .O(plm_fsm_cc_counter0_N_56149_i) + ); + defparam plm_fsm_cc_counter0_loadable_rx_counter_N_87489_i.INIT = 8'hFE; + LUT3 plm_fsm_cc_counter0_loadable_rx_counter_N_87489_i ( + .I0(plm_fsm_cc_counter0_reg_rx_expired_71), + .I1(N_56513_i), + .I2(plm_reg_ts2_1), + .O(plm_fsm_cc_counter0_N_87489_i) + ); + defparam plm_fsm_cc_counter0_oneshot_monitor_N_87221_i.INIT = 4'hE; + LUT2 plm_fsm_cc_counter0_oneshot_monitor_N_87221_i ( + .I0(N_56513_i), + .I1(plm_reg_ts2_1), + .O(plm_fsm_cc_counter0_N_87221_i) + ); + defparam plm_fsm_cc_counter0_N_87485_i.INIT = 8'hEF; + LUT3 plm_fsm_cc_counter0_N_87485_i ( + .I0(plm_reg_sym_sent_6_), + .I1(plm_fsm_cc_counter0_reg_tx_expired_1866), + .I2(plm_fsm_cc_counter0_N_56149_i), + .O(plm_fsm_cc_counter0_N_87485_i_1863) + ); + defparam plm_fsm_cc_counter0_N_29090_i_i.INIT = 4'hB; + LUT2 plm_fsm_cc_counter0_N_29090_i_i ( + .I0(plm_fsm_cc_counter0_reg_tx_expired_1866), + .I1(plm_fsm_cc_counter0_N_56149_i), + .O(plm_fsm_cc_counter0_N_29090_i_i_1862) + ); + FDCE plm_fsm_cc_counter0_reg_tx_count_7_ ( + .CE(plm_fsm_cc_counter0_N_87485_i_1863), + .C(mgt_clk), + .D(plm_fsm_cc_counter0_reg_tx_count_s[7]), + .Q(plm_fsm_cc_counter0_reg_tx_count[7]), + .CLR(plm_rst) + ); + FDCE plm_fsm_cc_counter0_reg_tx_count_6_ ( + .CE(plm_fsm_cc_counter0_N_87485_i_1863), + .C(mgt_clk), + .D(plm_fsm_cc_counter0_reg_tx_count_s[6]), + .Q(plm_fsm_cc_counter0_reg_tx_count[6]), + .CLR(plm_rst) + ); + FDCE plm_fsm_cc_counter0_reg_tx_count_5_ ( + .CE(plm_fsm_cc_counter0_N_87485_i_1863), + .C(mgt_clk), + .D(plm_fsm_cc_counter0_reg_tx_count_s[5]), + .Q(plm_fsm_cc_counter0_reg_tx_count[5]), + .CLR(plm_rst) + ); + FDPE plm_fsm_cc_counter0_reg_tx_count_4_ ( + .PRE(plm_rst), + .CE(plm_fsm_cc_counter0_N_87485_i_1863), + .C(mgt_clk), + .D(plm_fsm_cc_counter0_reg_tx_count_s[4]), + .Q(plm_fsm_cc_counter0_reg_tx_count[4]) + ); + FDCE plm_fsm_cc_counter0_reg_tx_count_3_ ( + .CE(plm_fsm_cc_counter0_N_87485_i_1863), + .C(mgt_clk), + .D(plm_fsm_cc_counter0_reg_tx_count_s[3]), + .Q(plm_fsm_cc_counter0_reg_tx_count[3]), + .CLR(plm_rst) + ); + FDCE plm_fsm_cc_counter0_reg_tx_count_2_ ( + .CE(plm_fsm_cc_counter0_N_87485_i_1863), + .C(mgt_clk), + .D(plm_fsm_cc_counter0_reg_tx_count_s[2]), + .Q(plm_fsm_cc_counter0_reg_tx_count[2]), + .CLR(plm_rst) + ); + FDCE plm_fsm_cc_counter0_reg_tx_count_1_ ( + .CE(plm_fsm_cc_counter0_N_87485_i_1863), + .C(mgt_clk), + .D(plm_fsm_cc_counter0_reg_tx_count_s[1]), + .Q(plm_fsm_cc_counter0_reg_tx_count[1]), + .CLR(plm_rst) + ); + FDCE plm_fsm_cc_counter0_reg_tx_count_0_ ( + .CE(plm_fsm_cc_counter0_N_87485_i_1863), + .C(mgt_clk), + .D(plm_fsm_cc_counter0_reg_tx_count_s[0]), + .Q(plm_fsm_cc_counter0_reg_tx_count[0]), + .CLR(plm_rst) + ); + FDCE plm_fsm_cc_counter0_reg_rx_count_7_ ( + .CE(plm_fsm_cc_counter0_N_87489_i), + .C(mgt_clk), + .D(plm_fsm_cc_counter0_reg_rx_count_s[7]), + .Q(plm_fsm_cc_counter0_reg_rx_count[7]), + .CLR(plm_rst) + ); + FDCE plm_fsm_cc_counter0_reg_rx_count_6_ ( + .CE(plm_fsm_cc_counter0_N_87489_i), + .C(mgt_clk), + .D(plm_fsm_cc_counter0_reg_rx_count_s[6]), + .Q(plm_fsm_cc_counter0_reg_rx_count[6]), + .CLR(plm_rst) + ); + FDCE plm_fsm_cc_counter0_reg_rx_count_5_ ( + .CE(plm_fsm_cc_counter0_N_87489_i), + .C(mgt_clk), + .D(plm_fsm_cc_counter0_reg_rx_count_s[5]), + .Q(plm_fsm_cc_counter0_reg_rx_count[5]), + .CLR(plm_rst) + ); + FDCE plm_fsm_cc_counter0_reg_rx_count_4_ ( + .CE(plm_fsm_cc_counter0_N_87489_i), + .C(mgt_clk), + .D(plm_fsm_cc_counter0_reg_rx_count_s[4]), + .Q(plm_fsm_cc_counter0_reg_rx_count[4]), + .CLR(plm_rst) + ); + FDPE plm_fsm_cc_counter0_reg_rx_count_3_ ( + .PRE(plm_rst), + .CE(plm_fsm_cc_counter0_N_87489_i), + .C(mgt_clk), + .D(plm_fsm_cc_counter0_reg_rx_count_s[3]), + .Q(plm_fsm_cc_counter0_reg_rx_count[3]) + ); + FDCE plm_fsm_cc_counter0_reg_rx_count_2_ ( + .CE(plm_fsm_cc_counter0_N_87489_i), + .C(mgt_clk), + .D(plm_fsm_cc_counter0_reg_rx_count_s[2]), + .Q(plm_fsm_cc_counter0_reg_rx_count[2]), + .CLR(plm_rst) + ); + FDCE plm_fsm_cc_counter0_reg_rx_count_1_ ( + .CE(plm_fsm_cc_counter0_N_87489_i), + .C(mgt_clk), + .D(plm_fsm_cc_counter0_reg_rx_count_s[1]), + .Q(plm_fsm_cc_counter0_reg_rx_count[1]), + .CLR(plm_rst) + ); + FDCE plm_fsm_cc_counter0_reg_rx_count_0_ ( + .CE(plm_fsm_cc_counter0_N_87489_i), + .C(mgt_clk), + .D(plm_fsm_cc_counter0_reg_rx_count_s[0]), + .Q(plm_fsm_cc_counter0_reg_rx_count[0]), + .CLR(plm_rst) + ); + FDC plm_fsm_cc_counter0_reg_expired ( + .C(mgt_clk), + .D(plm_fsm_cc_counter0_N_28777_i), + .Q(plm_fsm_cc_cntrout0), + .CLR(plm_rst) + ); + FDCE plm_fsm_cc_counter0_reg_oneshot ( + .CE(plm_fsm_cc_counter0_N_87221_i), + .C(mgt_clk), + .D(plm_fsm_N_56513_i_i_1804), + .Q(plm_fsm_cc_counter0_reg_oneshot_1864), + .CLR(plm_rst) + ); + FDCE plm_fsm_cc_counter0_reg_rx_expired ( + .CE(plm_fsm_cc_counter0_N_87211_i), + .C(mgt_clk), + .D(plm_fsm_N_56513_i_i_1804), + .Q(plm_fsm_cc_counter0_reg_rx_expired_71), + .CLR(plm_rst) + ); + FDCE plm_fsm_cc_counter0_reg_tx_expired ( + .CE(plm_fsm_cc_counter0_N_87204_i_1865), + .C(mgt_clk), + .D(plm_fsm_cc_counter0_N_56149_i), + .Q(plm_fsm_cc_counter0_reg_tx_expired_1866), + .CLR(plm_rst) + ); + defparam plm_fsm_cc_counter0_reg_rx_count_qxu_0_0_.INIT = 4'h7; + LUT2_L plm_fsm_cc_counter0_reg_rx_count_qxu_0_0_ ( + .I0(N_15208_i), + .I1(plm_fsm_cc_counter0_reg_rx_count[0]), + .LO(plm_fsm_cc_counter0_reg_rx_count_qxu[0]) + ); + defparam plm_fsm_cc_counter0_reg_rx_count_qxu_0_1_.INIT = 4'h7; + LUT2_L plm_fsm_cc_counter0_reg_rx_count_qxu_0_1_ ( + .I0(N_15208_i), + .I1(plm_fsm_cc_counter0_reg_rx_count[1]), + .LO(plm_fsm_cc_counter0_reg_rx_count_qxu[1]) + ); + defparam plm_fsm_cc_counter0_reg_rx_count_qxu_0_2_.INIT = 4'h7; + LUT2_L plm_fsm_cc_counter0_reg_rx_count_qxu_0_2_ ( + .I0(N_15208_i), + .I1(plm_fsm_cc_counter0_reg_rx_count[2]), + .LO(plm_fsm_cc_counter0_reg_rx_count_qxu[2]) + ); + defparam plm_fsm_cc_counter0_reg_rx_count_qxu_0_3_.INIT = 8'h1B; + LUT3_L plm_fsm_cc_counter0_reg_rx_count_qxu_0_3_ ( + .I0(N_15208_i), + .I1(plm_fsm_cc_counter0_N_87210_i_1867), + .I2(plm_fsm_cc_counter0_reg_rx_count[3]), + .LO(plm_fsm_cc_counter0_reg_rx_count_qxu[3]) + ); + defparam plm_fsm_cc_counter0_reg_rx_count_qxu_0_4_.INIT = 4'h7; + LUT2_L plm_fsm_cc_counter0_reg_rx_count_qxu_0_4_ ( + .I0(N_15208_i), + .I1(plm_fsm_cc_counter0_reg_rx_count[4]), + .LO(plm_fsm_cc_counter0_reg_rx_count_qxu[4]) + ); + defparam plm_fsm_cc_counter0_reg_rx_count_qxu_0_5_.INIT = 4'h7; + LUT2_L plm_fsm_cc_counter0_reg_rx_count_qxu_0_5_ ( + .I0(N_15208_i), + .I1(plm_fsm_cc_counter0_reg_rx_count[5]), + .LO(plm_fsm_cc_counter0_reg_rx_count_qxu[5]) + ); + defparam plm_fsm_cc_counter0_reg_rx_count_qxu_0_6_.INIT = 4'h7; + LUT2_L plm_fsm_cc_counter0_reg_rx_count_qxu_0_6_ ( + .I0(N_15208_i), + .I1(plm_fsm_cc_counter0_reg_rx_count[6]), + .LO(plm_fsm_cc_counter0_reg_rx_count_qxu[6]) + ); + defparam plm_fsm_cc_counter0_reg_rx_count_qxu_0_7_.INIT = 4'h7; + LUT2_L plm_fsm_cc_counter0_reg_rx_count_qxu_0_7_ ( + .I0(N_15208_i), + .I1(plm_fsm_cc_counter0_reg_rx_count[7]), + .LO(plm_fsm_cc_counter0_reg_rx_count_qxu[7]) + ); + defparam plm_fsm_cc_counter0_reg_tx_count_qxu_0_0_.INIT = 4'h7; + LUT2_L plm_fsm_cc_counter0_reg_tx_count_qxu_0_0_ ( + .I0(plm_fsm_cc_counter0_N_29090_i), + .I1(plm_fsm_cc_counter0_reg_tx_count[0]), + .LO(plm_fsm_cc_counter0_reg_tx_count_qxu[0]) + ); + defparam plm_fsm_cc_counter0_reg_tx_count_qxu_0_1_.INIT = 4'h7; + LUT2_L plm_fsm_cc_counter0_reg_tx_count_qxu_0_1_ ( + .I0(plm_fsm_cc_counter0_N_29090_i), + .I1(plm_fsm_cc_counter0_reg_tx_count[1]), + .LO(plm_fsm_cc_counter0_reg_tx_count_qxu[1]) + ); + defparam plm_fsm_cc_counter0_reg_tx_count_qxu_0_2_.INIT = 4'h7; + LUT2_L plm_fsm_cc_counter0_reg_tx_count_qxu_0_2_ ( + .I0(plm_fsm_cc_counter0_N_29090_i), + .I1(plm_fsm_cc_counter0_reg_tx_count[2]), + .LO(plm_fsm_cc_counter0_reg_tx_count_qxu[2]) + ); + defparam plm_fsm_cc_counter0_reg_tx_count_qxu_0_3_.INIT = 4'h7; + LUT2_L plm_fsm_cc_counter0_reg_tx_count_qxu_0_3_ ( + .I0(plm_fsm_cc_counter0_N_29090_i), + .I1(plm_fsm_cc_counter0_reg_tx_count[3]), + .LO(plm_fsm_cc_counter0_reg_tx_count_qxu[3]) + ); + defparam plm_fsm_cc_counter0_reg_tx_count_qxu_0_4_.INIT = 8'h4E; + LUT3_L plm_fsm_cc_counter0_reg_tx_count_qxu_0_4_ ( + .I0(plm_fsm_cc_counter0_N_29090_i), + .I1(plm_fsm_cc_counter0_N_56149_i), + .I2(plm_fsm_cc_counter0_reg_tx_count[4]), + .LO(plm_fsm_cc_counter0_reg_tx_count_qxu[4]) + ); + defparam plm_fsm_cc_counter0_reg_tx_count_qxu_0_5_.INIT = 4'h7; + LUT2_L plm_fsm_cc_counter0_reg_tx_count_qxu_0_5_ ( + .I0(plm_fsm_cc_counter0_N_29090_i), + .I1(plm_fsm_cc_counter0_reg_tx_count[5]), + .LO(plm_fsm_cc_counter0_reg_tx_count_qxu[5]) + ); + defparam plm_fsm_cc_counter0_reg_tx_count_qxu_0_6_.INIT = 4'h7; + LUT2_L plm_fsm_cc_counter0_reg_tx_count_qxu_0_6_ ( + .I0(plm_fsm_cc_counter0_N_29090_i), + .I1(plm_fsm_cc_counter0_reg_tx_count[6]), + .LO(plm_fsm_cc_counter0_reg_tx_count_qxu[6]) + ); + defparam plm_fsm_cc_counter0_reg_tx_count_qxu_0_7_.INIT = 4'h7; + LUT2_L plm_fsm_cc_counter0_reg_tx_count_qxu_0_7_ ( + .I0(plm_fsm_cc_counter0_N_29090_i), + .I1(plm_fsm_cc_counter0_reg_tx_count[7]), + .LO(plm_fsm_cc_counter0_reg_tx_count_qxu[7]) + ); + VCC plm_fsm_cc_counter1_VCC ( + .P(plm_fsm_cc_counter1_VCC_1868) + ); + MUXCY_L plm_fsm_cc_counter1_reg_rx_count_cry_0_ ( + .CI(N_14477_i_i_18), + .DI(plm_fsm_cc_counter1_VCC_1868), + .LO(plm_fsm_cc_counter1_reg_rx_count_cry[0]), + .S(plm_fsm_cc_counter1_reg_rx_count_qxu[0]) + ); + XORCY plm_fsm_cc_counter1_reg_rx_count_s_0_ ( + .CI(N_14477_i_i_18), + .LI(plm_fsm_cc_counter1_reg_rx_count_qxu[0]), + .O(plm_fsm_cc_counter1_reg_rx_count_s[0]) + ); + MUXCY_L plm_fsm_cc_counter1_reg_rx_count_cry_1_ ( + .CI(plm_fsm_cc_counter1_reg_rx_count_cry[0]), + .DI(plm_fsm_cc_counter1_VCC_1868), + .LO(plm_fsm_cc_counter1_reg_rx_count_cry[1]), + .S(plm_fsm_cc_counter1_reg_rx_count_qxu[1]) + ); + XORCY plm_fsm_cc_counter1_reg_rx_count_s_1_ ( + .CI(plm_fsm_cc_counter1_reg_rx_count_cry[0]), + .LI(plm_fsm_cc_counter1_reg_rx_count_qxu[1]), + .O(plm_fsm_cc_counter1_reg_rx_count_s[1]) + ); + MUXCY_L plm_fsm_cc_counter1_reg_rx_count_cry_2_ ( + .CI(plm_fsm_cc_counter1_reg_rx_count_cry[1]), + .DI(plm_fsm_cc_counter1_VCC_1868), + .LO(plm_fsm_cc_counter1_reg_rx_count_cry[2]), + .S(plm_fsm_cc_counter1_reg_rx_count_qxu[2]) + ); + XORCY plm_fsm_cc_counter1_reg_rx_count_s_2_ ( + .CI(plm_fsm_cc_counter1_reg_rx_count_cry[1]), + .LI(plm_fsm_cc_counter1_reg_rx_count_qxu[2]), + .O(plm_fsm_cc_counter1_reg_rx_count_s[2]) + ); + MUXCY_L plm_fsm_cc_counter1_reg_rx_count_cry_3_ ( + .CI(plm_fsm_cc_counter1_reg_rx_count_cry[2]), + .DI(plm_fsm_cc_counter1_VCC_1868), + .LO(plm_fsm_cc_counter1_reg_rx_count_cry[3]), + .S(plm_fsm_cc_counter1_reg_rx_count_qxu[3]) + ); + XORCY plm_fsm_cc_counter1_reg_rx_count_s_3_ ( + .CI(plm_fsm_cc_counter1_reg_rx_count_cry[2]), + .LI(plm_fsm_cc_counter1_reg_rx_count_qxu[3]), + .O(plm_fsm_cc_counter1_reg_rx_count_s[3]) + ); + MUXCY_L plm_fsm_cc_counter1_reg_rx_count_cry_4_ ( + .CI(plm_fsm_cc_counter1_reg_rx_count_cry[3]), + .DI(plm_fsm_cc_counter1_VCC_1868), + .LO(plm_fsm_cc_counter1_reg_rx_count_cry[4]), + .S(plm_fsm_cc_counter1_reg_rx_count_qxu[4]) + ); + XORCY plm_fsm_cc_counter1_reg_rx_count_s_4_ ( + .CI(plm_fsm_cc_counter1_reg_rx_count_cry[3]), + .LI(plm_fsm_cc_counter1_reg_rx_count_qxu[4]), + .O(plm_fsm_cc_counter1_reg_rx_count_s[4]) + ); + MUXCY_L plm_fsm_cc_counter1_reg_rx_count_cry_5_ ( + .CI(plm_fsm_cc_counter1_reg_rx_count_cry[4]), + .DI(plm_fsm_cc_counter1_VCC_1868), + .LO(plm_fsm_cc_counter1_reg_rx_count_cry[5]), + .S(plm_fsm_cc_counter1_reg_rx_count_qxu[5]) + ); + XORCY plm_fsm_cc_counter1_reg_rx_count_s_5_ ( + .CI(plm_fsm_cc_counter1_reg_rx_count_cry[4]), + .LI(plm_fsm_cc_counter1_reg_rx_count_qxu[5]), + .O(plm_fsm_cc_counter1_reg_rx_count_s[5]) + ); + MUXCY_L plm_fsm_cc_counter1_reg_rx_count_cry_6_ ( + .CI(plm_fsm_cc_counter1_reg_rx_count_cry[5]), + .DI(plm_fsm_cc_counter1_VCC_1868), + .LO(plm_fsm_cc_counter1_reg_rx_count_cry[6]), + .S(plm_fsm_cc_counter1_reg_rx_count_qxu[6]) + ); + XORCY plm_fsm_cc_counter1_reg_rx_count_s_6_ ( + .CI(plm_fsm_cc_counter1_reg_rx_count_cry[5]), + .LI(plm_fsm_cc_counter1_reg_rx_count_qxu[6]), + .O(plm_fsm_cc_counter1_reg_rx_count_s[6]) + ); + XORCY plm_fsm_cc_counter1_reg_rx_count_s_7_ ( + .CI(plm_fsm_cc_counter1_reg_rx_count_cry[6]), + .LI(plm_fsm_cc_counter1_reg_rx_count_qxu[7]), + .O(plm_fsm_cc_counter1_reg_rx_count_s[7]) + ); + MUXCY_L plm_fsm_cc_counter1_reg_tx_count_cry_0_ ( + .CI(plm_fsm_cc_counter1_N_29088_i_i_1869), + .DI(plm_fsm_cc_counter1_VCC_1868), + .LO(plm_fsm_cc_counter1_reg_tx_count_cry[0]), + .S(plm_fsm_cc_counter1_reg_tx_count_qxu[0]) + ); + XORCY plm_fsm_cc_counter1_reg_tx_count_s_0_ ( + .CI(plm_fsm_cc_counter1_N_29088_i_i_1869), + .LI(plm_fsm_cc_counter1_reg_tx_count_qxu[0]), + .O(plm_fsm_cc_counter1_reg_tx_count_s[0]) + ); + MUXCY_L plm_fsm_cc_counter1_reg_tx_count_cry_1_ ( + .CI(plm_fsm_cc_counter1_reg_tx_count_cry[0]), + .DI(plm_fsm_cc_counter1_VCC_1868), + .LO(plm_fsm_cc_counter1_reg_tx_count_cry[1]), + .S(plm_fsm_cc_counter1_reg_tx_count_qxu[1]) + ); + XORCY plm_fsm_cc_counter1_reg_tx_count_s_1_ ( + .CI(plm_fsm_cc_counter1_reg_tx_count_cry[0]), + .LI(plm_fsm_cc_counter1_reg_tx_count_qxu[1]), + .O(plm_fsm_cc_counter1_reg_tx_count_s[1]) + ); + MUXCY_L plm_fsm_cc_counter1_reg_tx_count_cry_2_ ( + .CI(plm_fsm_cc_counter1_reg_tx_count_cry[1]), + .DI(plm_fsm_cc_counter1_VCC_1868), + .LO(plm_fsm_cc_counter1_reg_tx_count_cry[2]), + .S(plm_fsm_cc_counter1_reg_tx_count_qxu[2]) + ); + XORCY plm_fsm_cc_counter1_reg_tx_count_s_2_ ( + .CI(plm_fsm_cc_counter1_reg_tx_count_cry[1]), + .LI(plm_fsm_cc_counter1_reg_tx_count_qxu[2]), + .O(plm_fsm_cc_counter1_reg_tx_count_s[2]) + ); + MUXCY_L plm_fsm_cc_counter1_reg_tx_count_cry_3_ ( + .CI(plm_fsm_cc_counter1_reg_tx_count_cry[2]), + .DI(plm_fsm_cc_counter1_VCC_1868), + .LO(plm_fsm_cc_counter1_reg_tx_count_cry[3]), + .S(plm_fsm_cc_counter1_reg_tx_count_qxu[3]) + ); + XORCY plm_fsm_cc_counter1_reg_tx_count_s_3_ ( + .CI(plm_fsm_cc_counter1_reg_tx_count_cry[2]), + .LI(plm_fsm_cc_counter1_reg_tx_count_qxu[3]), + .O(plm_fsm_cc_counter1_reg_tx_count_s[3]) + ); + MUXCY_L plm_fsm_cc_counter1_reg_tx_count_cry_4_ ( + .CI(plm_fsm_cc_counter1_reg_tx_count_cry[3]), + .DI(plm_fsm_cc_counter1_VCC_1868), + .LO(plm_fsm_cc_counter1_reg_tx_count_cry[4]), + .S(plm_fsm_cc_counter1_reg_tx_count_qxu[4]) + ); + XORCY plm_fsm_cc_counter1_reg_tx_count_s_4_ ( + .CI(plm_fsm_cc_counter1_reg_tx_count_cry[3]), + .LI(plm_fsm_cc_counter1_reg_tx_count_qxu[4]), + .O(plm_fsm_cc_counter1_reg_tx_count_s[4]) + ); + MUXCY_L plm_fsm_cc_counter1_reg_tx_count_cry_5_ ( + .CI(plm_fsm_cc_counter1_reg_tx_count_cry[4]), + .DI(plm_fsm_cc_counter1_VCC_1868), + .LO(plm_fsm_cc_counter1_reg_tx_count_cry[5]), + .S(plm_fsm_cc_counter1_reg_tx_count_qxu[5]) + ); + XORCY plm_fsm_cc_counter1_reg_tx_count_s_5_ ( + .CI(plm_fsm_cc_counter1_reg_tx_count_cry[4]), + .LI(plm_fsm_cc_counter1_reg_tx_count_qxu[5]), + .O(plm_fsm_cc_counter1_reg_tx_count_s[5]) + ); + MUXCY_L plm_fsm_cc_counter1_reg_tx_count_cry_6_ ( + .CI(plm_fsm_cc_counter1_reg_tx_count_cry[5]), + .DI(plm_fsm_cc_counter1_VCC_1868), + .LO(plm_fsm_cc_counter1_reg_tx_count_cry[6]), + .S(plm_fsm_cc_counter1_reg_tx_count_qxu[6]) + ); + XORCY plm_fsm_cc_counter1_reg_tx_count_s_6_ ( + .CI(plm_fsm_cc_counter1_reg_tx_count_cry[5]), + .LI(plm_fsm_cc_counter1_reg_tx_count_qxu[6]), + .O(plm_fsm_cc_counter1_reg_tx_count_s[6]) + ); + XORCY plm_fsm_cc_counter1_reg_tx_count_s_7_ ( + .CI(plm_fsm_cc_counter1_reg_tx_count_cry[6]), + .LI(plm_fsm_cc_counter1_reg_tx_count_qxu[7]), + .O(plm_fsm_cc_counter1_reg_tx_count_s[7]) + ); + defparam plm_fsm_cc_counter1_loadable_rx_counter_un1_reg_rx_count_0_a3_4.INIT = 16'h0001; + LUT4 plm_fsm_cc_counter1_loadable_rx_counter_un1_reg_rx_count_0_a3_4 ( + .I0(plm_fsm_cc_counter1_reg_rx_count[0]), + .I1(plm_fsm_cc_counter1_reg_rx_count[1]), + .I2(plm_fsm_cc_counter1_reg_rx_count[2]), + .I3(plm_fsm_cc_counter1_reg_rx_count[3]), + .O(plm_fsm_cc_counter1_un1_reg_rx_count_0_a3_4) + ); + defparam plm_fsm_cc_counter1_loadable_rx_counter_un1_reg_rx_count_0_a3_5.INIT = 16'h0001; + LUT4 plm_fsm_cc_counter1_loadable_rx_counter_un1_reg_rx_count_0_a3_5 ( + .I0(plm_fsm_cc_counter1_reg_rx_count[4]), + .I1(plm_fsm_cc_counter1_reg_rx_count[5]), + .I2(plm_fsm_cc_counter1_reg_rx_count[6]), + .I3(plm_fsm_cc_counter1_reg_rx_count[7]), + .O(plm_fsm_cc_counter1_un1_reg_rx_count_0_a3_5) + ); + defparam plm_fsm_cc_counter1_loadable_tx_counter_un1_reg_tx_count_0_a2_0_a3_4.INIT = 16'h0001; + LUT4 plm_fsm_cc_counter1_loadable_tx_counter_un1_reg_tx_count_0_a2_0_a3_4 ( + .I0(plm_fsm_cc_counter1_reg_tx_count[0]), + .I1(plm_fsm_cc_counter1_reg_tx_count[1]), + .I2(plm_fsm_cc_counter1_reg_tx_count[2]), + .I3(plm_fsm_cc_counter1_reg_tx_count[3]), + .O(plm_fsm_cc_counter1_un1_reg_tx_count_0_a2_0_a3_4) + ); + defparam plm_fsm_cc_counter1_loadable_tx_counter_un1_reg_tx_count_0_a2_0_a3_5.INIT = 16'h0001; + LUT4 plm_fsm_cc_counter1_loadable_tx_counter_un1_reg_tx_count_0_a2_0_a3_5 ( + .I0(plm_fsm_cc_counter1_reg_tx_count[4]), + .I1(plm_fsm_cc_counter1_reg_tx_count[5]), + .I2(plm_fsm_cc_counter1_reg_tx_count[6]), + .I3(plm_fsm_cc_counter1_reg_tx_count[7]), + .O(plm_fsm_cc_counter1_un1_reg_tx_count_0_a2_0_a3_5) + ); + defparam plm_fsm_cc_counter1_un1_enable_1_0_a3_i_0_0.INIT = 4'h2; + LUT2 plm_fsm_cc_counter1_un1_enable_1_0_a3_i_0_0 ( + .I0(plm_fsm_cc_counter1_N_56152_i), + .I1(plm_fsm_cc_counter1_reg_tx_expired_1873), + .O(plm_fsm_cc_counter1_N_29088_i) + ); + defparam plm_fsm_cc_counter1_N_87218_i.INIT = 8'hD5; + LUT3 plm_fsm_cc_counter1_N_87218_i ( + .I0(plm_fsm_cc_counter1_N_56152_i), + .I1(plm_fsm_cc_counter1_un1_reg_tx_count_0_a2_0_a3_4), + .I2(plm_fsm_cc_counter1_un1_reg_tx_count_0_a2_0_a3_5), + .O(plm_fsm_cc_counter1_N_87218_i_1872) + ); + defparam plm_fsm_cc_counter1_loadable_rx_counter_N_87209_i.INIT = 8'hEA; + LUT3 plm_fsm_cc_counter1_loadable_rx_counter_N_87209_i ( + .I0(N_56513_i), + .I1(plm_fsm_cc_counter1_un1_reg_rx_count_0_a3_4), + .I2(plm_fsm_cc_counter1_un1_reg_rx_count_0_a3_5), + .O(plm_fsm_cc_counter1_N_87209_i) + ); + defparam plm_fsm_cc_counter1_un1_enable_4_i_0_0_a2_1.INIT = 8'h2A; + LUT3 plm_fsm_cc_counter1_un1_enable_4_i_0_0_a2_1 ( + .I0(plm_reg_ts2_1_0), + .I1(N_56029_i), + .I2(plm_rx1_ts2_c), + .O(plm_fsm_N_59112_1) + ); + defparam plm_fsm_cc_counter1_N_87208_i.INIT = 8'hAE; + LUT3_L plm_fsm_cc_counter1_N_87208_i ( + .I0(N_56513_i), + .I1(plm_fsm_N_59112_1), + .I2(plm_fsm_cc_counter1_reg_rx_expired_310), + .LO(plm_fsm_cc_counter1_N_87208_i_1874) + ); + defparam plm_fsm_cc_counter1_flagit_reg_expired_5_i_0_0.INIT = 8'h40; + LUT3_L plm_fsm_cc_counter1_flagit_reg_expired_5_i_0_0 ( + .I0(N_56513_i), + .I1(plm_fsm_cc_counter1_reg_rx_expired_310), + .I2(plm_fsm_cc_counter1_reg_tx_expired_1873), + .LO(plm_fsm_cc_counter1_N_28775_i) + ); + defparam plm_fsm_cc_counter1_reg_tx_countlde_0_a2_i_0_0_o2.INIT = 8'hA8; + LUT3 plm_fsm_cc_counter1_reg_tx_countlde_0_a2_i_0_0_o2 ( + .I0(plm_fsm_cc_counter1_reg_oneshot_1871), + .I1(plm_fsm_reg_state_10__1792), + .I2(plm_fsm_reg_state_9__1795), + .O(plm_fsm_cc_counter1_N_56152_i) + ); + defparam plm_fsm_cc_counter1_loadable_rx_counter_N_87480_i.INIT = 8'hFE; + LUT3 plm_fsm_cc_counter1_loadable_rx_counter_N_87480_i ( + .I0(plm_fsm_cc_counter1_reg_rx_expired_310), + .I1(N_56513_i), + .I2(plm_reg_ts2_1_0), + .O(plm_fsm_cc_counter1_N_87480_i) + ); + defparam plm_fsm_cc_counter1_oneshot_monitor_N_87220_i.INIT = 4'hE; + LUT2 plm_fsm_cc_counter1_oneshot_monitor_N_87220_i ( + .I0(N_56513_i), + .I1(plm_reg_ts2_1_0), + .O(plm_fsm_cc_counter1_N_87220_i) + ); + defparam plm_fsm_cc_counter1_N_87484_i.INIT = 8'hEF; + LUT3 plm_fsm_cc_counter1_N_87484_i ( + .I0(plm_reg_sym_sent_6_), + .I1(plm_fsm_cc_counter1_reg_tx_expired_1873), + .I2(plm_fsm_cc_counter1_N_56152_i), + .O(plm_fsm_cc_counter1_N_87484_i_1870) + ); + defparam plm_fsm_cc_counter1_N_29088_i_i.INIT = 4'hB; + LUT2 plm_fsm_cc_counter1_N_29088_i_i ( + .I0(plm_fsm_cc_counter1_reg_tx_expired_1873), + .I1(plm_fsm_cc_counter1_N_56152_i), + .O(plm_fsm_cc_counter1_N_29088_i_i_1869) + ); + FDCE plm_fsm_cc_counter1_reg_tx_count_7_ ( + .CE(plm_fsm_cc_counter1_N_87484_i_1870), + .C(mgt_clk), + .D(plm_fsm_cc_counter1_reg_tx_count_s[7]), + .Q(plm_fsm_cc_counter1_reg_tx_count[7]), + .CLR(plm_rst) + ); + FDCE plm_fsm_cc_counter1_reg_tx_count_6_ ( + .CE(plm_fsm_cc_counter1_N_87484_i_1870), + .C(mgt_clk), + .D(plm_fsm_cc_counter1_reg_tx_count_s[6]), + .Q(plm_fsm_cc_counter1_reg_tx_count[6]), + .CLR(plm_rst) + ); + FDCE plm_fsm_cc_counter1_reg_tx_count_5_ ( + .CE(plm_fsm_cc_counter1_N_87484_i_1870), + .C(mgt_clk), + .D(plm_fsm_cc_counter1_reg_tx_count_s[5]), + .Q(plm_fsm_cc_counter1_reg_tx_count[5]), + .CLR(plm_rst) + ); + FDPE plm_fsm_cc_counter1_reg_tx_count_4_ ( + .PRE(plm_rst), + .CE(plm_fsm_cc_counter1_N_87484_i_1870), + .C(mgt_clk), + .D(plm_fsm_cc_counter1_reg_tx_count_s[4]), + .Q(plm_fsm_cc_counter1_reg_tx_count[4]) + ); + FDCE plm_fsm_cc_counter1_reg_tx_count_3_ ( + .CE(plm_fsm_cc_counter1_N_87484_i_1870), + .C(mgt_clk), + .D(plm_fsm_cc_counter1_reg_tx_count_s[3]), + .Q(plm_fsm_cc_counter1_reg_tx_count[3]), + .CLR(plm_rst) + ); + FDCE plm_fsm_cc_counter1_reg_tx_count_2_ ( + .CE(plm_fsm_cc_counter1_N_87484_i_1870), + .C(mgt_clk), + .D(plm_fsm_cc_counter1_reg_tx_count_s[2]), + .Q(plm_fsm_cc_counter1_reg_tx_count[2]), + .CLR(plm_rst) + ); + FDCE plm_fsm_cc_counter1_reg_tx_count_1_ ( + .CE(plm_fsm_cc_counter1_N_87484_i_1870), + .C(mgt_clk), + .D(plm_fsm_cc_counter1_reg_tx_count_s[1]), + .Q(plm_fsm_cc_counter1_reg_tx_count[1]), + .CLR(plm_rst) + ); + FDCE plm_fsm_cc_counter1_reg_tx_count_0_ ( + .CE(plm_fsm_cc_counter1_N_87484_i_1870), + .C(mgt_clk), + .D(plm_fsm_cc_counter1_reg_tx_count_s[0]), + .Q(plm_fsm_cc_counter1_reg_tx_count[0]), + .CLR(plm_rst) + ); + FDCE plm_fsm_cc_counter1_reg_rx_count_7_ ( + .CE(plm_fsm_cc_counter1_N_87480_i), + .C(mgt_clk), + .D(plm_fsm_cc_counter1_reg_rx_count_s[7]), + .Q(plm_fsm_cc_counter1_reg_rx_count[7]), + .CLR(plm_rst) + ); + FDCE plm_fsm_cc_counter1_reg_rx_count_6_ ( + .CE(plm_fsm_cc_counter1_N_87480_i), + .C(mgt_clk), + .D(plm_fsm_cc_counter1_reg_rx_count_s[6]), + .Q(plm_fsm_cc_counter1_reg_rx_count[6]), + .CLR(plm_rst) + ); + FDCE plm_fsm_cc_counter1_reg_rx_count_5_ ( + .CE(plm_fsm_cc_counter1_N_87480_i), + .C(mgt_clk), + .D(plm_fsm_cc_counter1_reg_rx_count_s[5]), + .Q(plm_fsm_cc_counter1_reg_rx_count[5]), + .CLR(plm_rst) + ); + FDCE plm_fsm_cc_counter1_reg_rx_count_4_ ( + .CE(plm_fsm_cc_counter1_N_87480_i), + .C(mgt_clk), + .D(plm_fsm_cc_counter1_reg_rx_count_s[4]), + .Q(plm_fsm_cc_counter1_reg_rx_count[4]), + .CLR(plm_rst) + ); + FDPE plm_fsm_cc_counter1_reg_rx_count_3_ ( + .PRE(plm_rst), + .CE(plm_fsm_cc_counter1_N_87480_i), + .C(mgt_clk), + .D(plm_fsm_cc_counter1_reg_rx_count_s[3]), + .Q(plm_fsm_cc_counter1_reg_rx_count[3]) + ); + FDCE plm_fsm_cc_counter1_reg_rx_count_2_ ( + .CE(plm_fsm_cc_counter1_N_87480_i), + .C(mgt_clk), + .D(plm_fsm_cc_counter1_reg_rx_count_s[2]), + .Q(plm_fsm_cc_counter1_reg_rx_count[2]), + .CLR(plm_rst) + ); + FDCE plm_fsm_cc_counter1_reg_rx_count_1_ ( + .CE(plm_fsm_cc_counter1_N_87480_i), + .C(mgt_clk), + .D(plm_fsm_cc_counter1_reg_rx_count_s[1]), + .Q(plm_fsm_cc_counter1_reg_rx_count[1]), + .CLR(plm_rst) + ); + FDCE plm_fsm_cc_counter1_reg_rx_count_0_ ( + .CE(plm_fsm_cc_counter1_N_87480_i), + .C(mgt_clk), + .D(plm_fsm_cc_counter1_reg_rx_count_s[0]), + .Q(plm_fsm_cc_counter1_reg_rx_count[0]), + .CLR(plm_rst) + ); + FDC plm_fsm_cc_counter1_reg_expired ( + .C(mgt_clk), + .D(plm_fsm_cc_counter1_N_28775_i), + .Q(plm_fsm_cc_cntrout1), + .CLR(plm_rst) + ); + FDCE plm_fsm_cc_counter1_reg_oneshot ( + .CE(plm_fsm_cc_counter1_N_87220_i), + .C(mgt_clk), + .D(plm_fsm_N_56513_i_i_1804), + .Q(plm_fsm_cc_counter1_reg_oneshot_1871), + .CLR(plm_rst) + ); + FDCE plm_fsm_cc_counter1_reg_rx_expired ( + .CE(plm_fsm_cc_counter1_N_87209_i), + .C(mgt_clk), + .D(plm_fsm_N_56513_i_i_1804), + .Q(plm_fsm_cc_counter1_reg_rx_expired_310), + .CLR(plm_rst) + ); + FDCE plm_fsm_cc_counter1_reg_tx_expired ( + .CE(plm_fsm_cc_counter1_N_87218_i_1872), + .C(mgt_clk), + .D(plm_fsm_cc_counter1_N_56152_i), + .Q(plm_fsm_cc_counter1_reg_tx_expired_1873), + .CLR(plm_rst) + ); + defparam plm_fsm_cc_counter1_reg_rx_count_qxu_0_0_.INIT = 4'h7; + LUT2_L plm_fsm_cc_counter1_reg_rx_count_qxu_0_0_ ( + .I0(N_14477_i), + .I1(plm_fsm_cc_counter1_reg_rx_count[0]), + .LO(plm_fsm_cc_counter1_reg_rx_count_qxu[0]) + ); + defparam plm_fsm_cc_counter1_reg_rx_count_qxu_0_1_.INIT = 4'h7; + LUT2_L plm_fsm_cc_counter1_reg_rx_count_qxu_0_1_ ( + .I0(N_14477_i), + .I1(plm_fsm_cc_counter1_reg_rx_count[1]), + .LO(plm_fsm_cc_counter1_reg_rx_count_qxu[1]) + ); + defparam plm_fsm_cc_counter1_reg_rx_count_qxu_0_2_.INIT = 4'h7; + LUT2_L plm_fsm_cc_counter1_reg_rx_count_qxu_0_2_ ( + .I0(N_14477_i), + .I1(plm_fsm_cc_counter1_reg_rx_count[2]), + .LO(plm_fsm_cc_counter1_reg_rx_count_qxu[2]) + ); + defparam plm_fsm_cc_counter1_reg_rx_count_qxu_0_3_.INIT = 8'h1B; + LUT3_L plm_fsm_cc_counter1_reg_rx_count_qxu_0_3_ ( + .I0(N_14477_i), + .I1(plm_fsm_cc_counter1_N_87208_i_1874), + .I2(plm_fsm_cc_counter1_reg_rx_count[3]), + .LO(plm_fsm_cc_counter1_reg_rx_count_qxu[3]) + ); + defparam plm_fsm_cc_counter1_reg_rx_count_qxu_0_4_.INIT = 4'h7; + LUT2_L plm_fsm_cc_counter1_reg_rx_count_qxu_0_4_ ( + .I0(N_14477_i), + .I1(plm_fsm_cc_counter1_reg_rx_count[4]), + .LO(plm_fsm_cc_counter1_reg_rx_count_qxu[4]) + ); + defparam plm_fsm_cc_counter1_reg_rx_count_qxu_0_5_.INIT = 4'h7; + LUT2_L plm_fsm_cc_counter1_reg_rx_count_qxu_0_5_ ( + .I0(N_14477_i), + .I1(plm_fsm_cc_counter1_reg_rx_count[5]), + .LO(plm_fsm_cc_counter1_reg_rx_count_qxu[5]) + ); + defparam plm_fsm_cc_counter1_reg_rx_count_qxu_0_6_.INIT = 4'h7; + LUT2_L plm_fsm_cc_counter1_reg_rx_count_qxu_0_6_ ( + .I0(N_14477_i), + .I1(plm_fsm_cc_counter1_reg_rx_count[6]), + .LO(plm_fsm_cc_counter1_reg_rx_count_qxu[6]) + ); + defparam plm_fsm_cc_counter1_reg_rx_count_qxu_0_7_.INIT = 4'h7; + LUT2_L plm_fsm_cc_counter1_reg_rx_count_qxu_0_7_ ( + .I0(N_14477_i), + .I1(plm_fsm_cc_counter1_reg_rx_count[7]), + .LO(plm_fsm_cc_counter1_reg_rx_count_qxu[7]) + ); + defparam plm_fsm_cc_counter1_reg_tx_count_qxu_0_0_.INIT = 4'h7; + LUT2_L plm_fsm_cc_counter1_reg_tx_count_qxu_0_0_ ( + .I0(plm_fsm_cc_counter1_N_29088_i), + .I1(plm_fsm_cc_counter1_reg_tx_count[0]), + .LO(plm_fsm_cc_counter1_reg_tx_count_qxu[0]) + ); + defparam plm_fsm_cc_counter1_reg_tx_count_qxu_0_1_.INIT = 4'h7; + LUT2_L plm_fsm_cc_counter1_reg_tx_count_qxu_0_1_ ( + .I0(plm_fsm_cc_counter1_N_29088_i), + .I1(plm_fsm_cc_counter1_reg_tx_count[1]), + .LO(plm_fsm_cc_counter1_reg_tx_count_qxu[1]) + ); + defparam plm_fsm_cc_counter1_reg_tx_count_qxu_0_2_.INIT = 4'h7; + LUT2_L plm_fsm_cc_counter1_reg_tx_count_qxu_0_2_ ( + .I0(plm_fsm_cc_counter1_N_29088_i), + .I1(plm_fsm_cc_counter1_reg_tx_count[2]), + .LO(plm_fsm_cc_counter1_reg_tx_count_qxu[2]) + ); + defparam plm_fsm_cc_counter1_reg_tx_count_qxu_0_3_.INIT = 4'h7; + LUT2_L plm_fsm_cc_counter1_reg_tx_count_qxu_0_3_ ( + .I0(plm_fsm_cc_counter1_N_29088_i), + .I1(plm_fsm_cc_counter1_reg_tx_count[3]), + .LO(plm_fsm_cc_counter1_reg_tx_count_qxu[3]) + ); + defparam plm_fsm_cc_counter1_reg_tx_count_qxu_0_4_.INIT = 8'h4E; + LUT3_L plm_fsm_cc_counter1_reg_tx_count_qxu_0_4_ ( + .I0(plm_fsm_cc_counter1_N_29088_i), + .I1(plm_fsm_cc_counter1_N_56152_i), + .I2(plm_fsm_cc_counter1_reg_tx_count[4]), + .LO(plm_fsm_cc_counter1_reg_tx_count_qxu[4]) + ); + defparam plm_fsm_cc_counter1_reg_tx_count_qxu_0_5_.INIT = 4'h7; + LUT2_L plm_fsm_cc_counter1_reg_tx_count_qxu_0_5_ ( + .I0(plm_fsm_cc_counter1_N_29088_i), + .I1(plm_fsm_cc_counter1_reg_tx_count[5]), + .LO(plm_fsm_cc_counter1_reg_tx_count_qxu[5]) + ); + defparam plm_fsm_cc_counter1_reg_tx_count_qxu_0_6_.INIT = 4'h7; + LUT2_L plm_fsm_cc_counter1_reg_tx_count_qxu_0_6_ ( + .I0(plm_fsm_cc_counter1_N_29088_i), + .I1(plm_fsm_cc_counter1_reg_tx_count[6]), + .LO(plm_fsm_cc_counter1_reg_tx_count_qxu[6]) + ); + defparam plm_fsm_cc_counter1_reg_tx_count_qxu_0_7_.INIT = 4'h7; + LUT2_L plm_fsm_cc_counter1_reg_tx_count_qxu_0_7_ ( + .I0(plm_fsm_cc_counter1_N_29088_i), + .I1(plm_fsm_cc_counter1_reg_tx_count[7]), + .LO(plm_fsm_cc_counter1_reg_tx_count_qxu[7]) + ); + VCC plm_fsm_cc_counter2_VCC ( + .P(plm_fsm_cc_counter2_VCC_1875) + ); + MUXCY_L plm_fsm_cc_counter2_reg_rx_count_cry_0_ ( + .CI(N_28971_i_i_74), + .DI(plm_fsm_cc_counter2_VCC_1875), + .LO(plm_fsm_cc_counter2_reg_rx_count_cry[0]), + .S(plm_fsm_cc_counter2_reg_rx_count_qxu[0]) + ); + XORCY plm_fsm_cc_counter2_reg_rx_count_s_0_ ( + .CI(N_28971_i_i_74), + .LI(plm_fsm_cc_counter2_reg_rx_count_qxu[0]), + .O(plm_fsm_cc_counter2_reg_rx_count_s[0]) + ); + MUXCY_L plm_fsm_cc_counter2_reg_rx_count_cry_1_ ( + .CI(plm_fsm_cc_counter2_reg_rx_count_cry[0]), + .DI(plm_fsm_cc_counter2_VCC_1875), + .LO(plm_fsm_cc_counter2_reg_rx_count_cry[1]), + .S(plm_fsm_cc_counter2_reg_rx_count_qxu[1]) + ); + XORCY plm_fsm_cc_counter2_reg_rx_count_s_1_ ( + .CI(plm_fsm_cc_counter2_reg_rx_count_cry[0]), + .LI(plm_fsm_cc_counter2_reg_rx_count_qxu[1]), + .O(plm_fsm_cc_counter2_reg_rx_count_s[1]) + ); + MUXCY_L plm_fsm_cc_counter2_reg_rx_count_cry_2_ ( + .CI(plm_fsm_cc_counter2_reg_rx_count_cry[1]), + .DI(plm_fsm_cc_counter2_VCC_1875), + .LO(plm_fsm_cc_counter2_reg_rx_count_cry[2]), + .S(plm_fsm_cc_counter2_reg_rx_count_qxu[2]) + ); + XORCY plm_fsm_cc_counter2_reg_rx_count_s_2_ ( + .CI(plm_fsm_cc_counter2_reg_rx_count_cry[1]), + .LI(plm_fsm_cc_counter2_reg_rx_count_qxu[2]), + .O(plm_fsm_cc_counter2_reg_rx_count_s[2]) + ); + MUXCY_L plm_fsm_cc_counter2_reg_rx_count_cry_3_ ( + .CI(plm_fsm_cc_counter2_reg_rx_count_cry[2]), + .DI(plm_fsm_cc_counter2_VCC_1875), + .LO(plm_fsm_cc_counter2_reg_rx_count_cry[3]), + .S(plm_fsm_cc_counter2_reg_rx_count_qxu[3]) + ); + XORCY plm_fsm_cc_counter2_reg_rx_count_s_3_ ( + .CI(plm_fsm_cc_counter2_reg_rx_count_cry[2]), + .LI(plm_fsm_cc_counter2_reg_rx_count_qxu[3]), + .O(plm_fsm_cc_counter2_reg_rx_count_s[3]) + ); + MUXCY_L plm_fsm_cc_counter2_reg_rx_count_cry_4_ ( + .CI(plm_fsm_cc_counter2_reg_rx_count_cry[3]), + .DI(plm_fsm_cc_counter2_VCC_1875), + .LO(plm_fsm_cc_counter2_reg_rx_count_cry[4]), + .S(plm_fsm_cc_counter2_reg_rx_count_qxu[4]) + ); + XORCY plm_fsm_cc_counter2_reg_rx_count_s_4_ ( + .CI(plm_fsm_cc_counter2_reg_rx_count_cry[3]), + .LI(plm_fsm_cc_counter2_reg_rx_count_qxu[4]), + .O(plm_fsm_cc_counter2_reg_rx_count_s[4]) + ); + MUXCY_L plm_fsm_cc_counter2_reg_rx_count_cry_5_ ( + .CI(plm_fsm_cc_counter2_reg_rx_count_cry[4]), + .DI(plm_fsm_cc_counter2_VCC_1875), + .LO(plm_fsm_cc_counter2_reg_rx_count_cry[5]), + .S(plm_fsm_cc_counter2_reg_rx_count_qxu[5]) + ); + XORCY plm_fsm_cc_counter2_reg_rx_count_s_5_ ( + .CI(plm_fsm_cc_counter2_reg_rx_count_cry[4]), + .LI(plm_fsm_cc_counter2_reg_rx_count_qxu[5]), + .O(plm_fsm_cc_counter2_reg_rx_count_s[5]) + ); + MUXCY_L plm_fsm_cc_counter2_reg_rx_count_cry_6_ ( + .CI(plm_fsm_cc_counter2_reg_rx_count_cry[5]), + .DI(plm_fsm_cc_counter2_VCC_1875), + .LO(plm_fsm_cc_counter2_reg_rx_count_cry[6]), + .S(plm_fsm_cc_counter2_reg_rx_count_qxu[6]) + ); + XORCY plm_fsm_cc_counter2_reg_rx_count_s_6_ ( + .CI(plm_fsm_cc_counter2_reg_rx_count_cry[5]), + .LI(plm_fsm_cc_counter2_reg_rx_count_qxu[6]), + .O(plm_fsm_cc_counter2_reg_rx_count_s[6]) + ); + XORCY plm_fsm_cc_counter2_reg_rx_count_s_7_ ( + .CI(plm_fsm_cc_counter2_reg_rx_count_cry[6]), + .LI(plm_fsm_cc_counter2_reg_rx_count_qxu[7]), + .O(plm_fsm_cc_counter2_reg_rx_count_s[7]) + ); + MUXCY_L plm_fsm_cc_counter2_reg_tx_count_cry_0_ ( + .CI(plm_fsm_cc_counter2_N_29086_i_i_1876), + .DI(plm_fsm_cc_counter2_VCC_1875), + .LO(plm_fsm_cc_counter2_reg_tx_count_cry[0]), + .S(plm_fsm_cc_counter2_reg_tx_count_qxu[0]) + ); + XORCY plm_fsm_cc_counter2_reg_tx_count_s_0_ ( + .CI(plm_fsm_cc_counter2_N_29086_i_i_1876), + .LI(plm_fsm_cc_counter2_reg_tx_count_qxu[0]), + .O(plm_fsm_cc_counter2_reg_tx_count_s[0]) + ); + MUXCY_L plm_fsm_cc_counter2_reg_tx_count_cry_1_ ( + .CI(plm_fsm_cc_counter2_reg_tx_count_cry[0]), + .DI(plm_fsm_cc_counter2_VCC_1875), + .LO(plm_fsm_cc_counter2_reg_tx_count_cry[1]), + .S(plm_fsm_cc_counter2_reg_tx_count_qxu[1]) + ); + XORCY plm_fsm_cc_counter2_reg_tx_count_s_1_ ( + .CI(plm_fsm_cc_counter2_reg_tx_count_cry[0]), + .LI(plm_fsm_cc_counter2_reg_tx_count_qxu[1]), + .O(plm_fsm_cc_counter2_reg_tx_count_s[1]) + ); + MUXCY_L plm_fsm_cc_counter2_reg_tx_count_cry_2_ ( + .CI(plm_fsm_cc_counter2_reg_tx_count_cry[1]), + .DI(plm_fsm_cc_counter2_VCC_1875), + .LO(plm_fsm_cc_counter2_reg_tx_count_cry[2]), + .S(plm_fsm_cc_counter2_reg_tx_count_qxu[2]) + ); + XORCY plm_fsm_cc_counter2_reg_tx_count_s_2_ ( + .CI(plm_fsm_cc_counter2_reg_tx_count_cry[1]), + .LI(plm_fsm_cc_counter2_reg_tx_count_qxu[2]), + .O(plm_fsm_cc_counter2_reg_tx_count_s[2]) + ); + MUXCY_L plm_fsm_cc_counter2_reg_tx_count_cry_3_ ( + .CI(plm_fsm_cc_counter2_reg_tx_count_cry[2]), + .DI(plm_fsm_cc_counter2_VCC_1875), + .LO(plm_fsm_cc_counter2_reg_tx_count_cry[3]), + .S(plm_fsm_cc_counter2_reg_tx_count_qxu[3]) + ); + XORCY plm_fsm_cc_counter2_reg_tx_count_s_3_ ( + .CI(plm_fsm_cc_counter2_reg_tx_count_cry[2]), + .LI(plm_fsm_cc_counter2_reg_tx_count_qxu[3]), + .O(plm_fsm_cc_counter2_reg_tx_count_s[3]) + ); + MUXCY_L plm_fsm_cc_counter2_reg_tx_count_cry_4_ ( + .CI(plm_fsm_cc_counter2_reg_tx_count_cry[3]), + .DI(plm_fsm_cc_counter2_VCC_1875), + .LO(plm_fsm_cc_counter2_reg_tx_count_cry[4]), + .S(plm_fsm_cc_counter2_reg_tx_count_qxu[4]) + ); + XORCY plm_fsm_cc_counter2_reg_tx_count_s_4_ ( + .CI(plm_fsm_cc_counter2_reg_tx_count_cry[3]), + .LI(plm_fsm_cc_counter2_reg_tx_count_qxu[4]), + .O(plm_fsm_cc_counter2_reg_tx_count_s[4]) + ); + MUXCY_L plm_fsm_cc_counter2_reg_tx_count_cry_5_ ( + .CI(plm_fsm_cc_counter2_reg_tx_count_cry[4]), + .DI(plm_fsm_cc_counter2_VCC_1875), + .LO(plm_fsm_cc_counter2_reg_tx_count_cry[5]), + .S(plm_fsm_cc_counter2_reg_tx_count_qxu[5]) + ); + XORCY plm_fsm_cc_counter2_reg_tx_count_s_5_ ( + .CI(plm_fsm_cc_counter2_reg_tx_count_cry[4]), + .LI(plm_fsm_cc_counter2_reg_tx_count_qxu[5]), + .O(plm_fsm_cc_counter2_reg_tx_count_s[5]) + ); + MUXCY_L plm_fsm_cc_counter2_reg_tx_count_cry_6_ ( + .CI(plm_fsm_cc_counter2_reg_tx_count_cry[5]), + .DI(plm_fsm_cc_counter2_VCC_1875), + .LO(plm_fsm_cc_counter2_reg_tx_count_cry[6]), + .S(plm_fsm_cc_counter2_reg_tx_count_qxu[6]) + ); + XORCY plm_fsm_cc_counter2_reg_tx_count_s_6_ ( + .CI(plm_fsm_cc_counter2_reg_tx_count_cry[5]), + .LI(plm_fsm_cc_counter2_reg_tx_count_qxu[6]), + .O(plm_fsm_cc_counter2_reg_tx_count_s[6]) + ); + XORCY plm_fsm_cc_counter2_reg_tx_count_s_7_ ( + .CI(plm_fsm_cc_counter2_reg_tx_count_cry[6]), + .LI(plm_fsm_cc_counter2_reg_tx_count_qxu[7]), + .O(plm_fsm_cc_counter2_reg_tx_count_s[7]) + ); + defparam plm_fsm_cc_counter2_oneshot_monitor_un1_enable_i_o2_0_0.INIT = 4'h1; + LUT2 plm_fsm_cc_counter2_oneshot_monitor_un1_enable_i_o2_0_0 ( + .I0(plm_reg_ts2_1_1), + .I1(N_56513_i), + .O(plm_fsm_cc_counter2_un1_enable_i_o2_0_0) + ); + defparam plm_fsm_cc_counter2_loadable_rx_counter_un1_reg_rx_count_0_a3_4.INIT = 16'h0001; + LUT4 plm_fsm_cc_counter2_loadable_rx_counter_un1_reg_rx_count_0_a3_4 ( + .I0(plm_fsm_cc_counter2_reg_rx_count[0]), + .I1(plm_fsm_cc_counter2_reg_rx_count[1]), + .I2(plm_fsm_cc_counter2_reg_rx_count[2]), + .I3(plm_fsm_cc_counter2_reg_rx_count[3]), + .O(plm_fsm_cc_counter2_un1_reg_rx_count_0_a3_4) + ); + defparam plm_fsm_cc_counter2_loadable_rx_counter_un1_reg_rx_count_0_a3_5.INIT = 16'h0001; + LUT4 plm_fsm_cc_counter2_loadable_rx_counter_un1_reg_rx_count_0_a3_5 ( + .I0(plm_fsm_cc_counter2_reg_rx_count[4]), + .I1(plm_fsm_cc_counter2_reg_rx_count[5]), + .I2(plm_fsm_cc_counter2_reg_rx_count[6]), + .I3(plm_fsm_cc_counter2_reg_rx_count[7]), + .O(plm_fsm_cc_counter2_un1_reg_rx_count_0_a3_5) + ); + defparam plm_fsm_cc_counter2_loadable_tx_counter_un1_reg_tx_count_0_a2_0_a3_4.INIT = 16'h0001; + LUT4 plm_fsm_cc_counter2_loadable_tx_counter_un1_reg_tx_count_0_a2_0_a3_4 ( + .I0(plm_fsm_cc_counter2_reg_tx_count[0]), + .I1(plm_fsm_cc_counter2_reg_tx_count[1]), + .I2(plm_fsm_cc_counter2_reg_tx_count[2]), + .I3(plm_fsm_cc_counter2_reg_tx_count[3]), + .O(plm_fsm_cc_counter2_un1_reg_tx_count_0_a2_0_a3_4) + ); + defparam plm_fsm_cc_counter2_loadable_tx_counter_un1_reg_tx_count_0_a2_0_a3_5.INIT = 16'h0001; + LUT4 plm_fsm_cc_counter2_loadable_tx_counter_un1_reg_tx_count_0_a2_0_a3_5 ( + .I0(plm_fsm_cc_counter2_reg_tx_count[4]), + .I1(plm_fsm_cc_counter2_reg_tx_count[5]), + .I2(plm_fsm_cc_counter2_reg_tx_count[6]), + .I3(plm_fsm_cc_counter2_reg_tx_count[7]), + .O(plm_fsm_cc_counter2_un1_reg_tx_count_0_a2_0_a3_5) + ); + defparam plm_fsm_cc_counter2_un1_enable_1_0_a3_i_0_0.INIT = 4'h2; + LUT2 plm_fsm_cc_counter2_un1_enable_1_0_a3_i_0_0 ( + .I0(plm_fsm_cc_counter2_N_56150_i), + .I1(plm_fsm_cc_counter2_reg_tx_expired_1880), + .O(plm_fsm_cc_counter2_N_29086_i) + ); + defparam plm_fsm_cc_counter2_loadable_rx_counter_N_87481_i.INIT = 4'hD; + LUT2 plm_fsm_cc_counter2_loadable_rx_counter_N_87481_i ( + .I0(plm_fsm_cc_counter2_un1_enable_i_o2_0_0), + .I1(plm_fsm_cc_counter2_reg_rx_expired_73), + .O(plm_fsm_cc_counter2_N_87481_i) + ); + defparam plm_fsm_cc_counter2_N_87212_i.INIT = 8'hD5; + LUT3 plm_fsm_cc_counter2_N_87212_i ( + .I0(plm_fsm_cc_counter2_N_56150_i), + .I1(plm_fsm_cc_counter2_un1_reg_tx_count_0_a2_0_a3_4), + .I2(plm_fsm_cc_counter2_un1_reg_tx_count_0_a2_0_a3_5), + .O(plm_fsm_cc_counter2_N_87212_i_1879) + ); + defparam plm_fsm_cc_counter2_loadable_rx_counter_N_87555_i.INIT = 8'hEA; + LUT3 plm_fsm_cc_counter2_loadable_rx_counter_N_87555_i ( + .I0(N_56513_i), + .I1(plm_fsm_cc_counter2_un1_reg_rx_count_0_a3_4), + .I2(plm_fsm_cc_counter2_un1_reg_rx_count_0_a3_5), + .O(plm_fsm_cc_counter2_N_87555_i) + ); + defparam plm_fsm_cc_counter2_N_87207_i.INIT = 16'hF0F2; + LUT4 plm_fsm_cc_counter2_N_87207_i ( + .I0(plm_reg_ts2_1_1), + .I1(N_56155_i), + .I2(N_56513_i), + .I3(plm_fsm_cc_counter2_reg_rx_expired_73), + .O(plm_fsm_cc_counter2_N_87207_i_1881) + ); + defparam plm_fsm_cc_counter2_flagit_reg_expired_5_i_0_0.INIT = 8'h40; + LUT3_L plm_fsm_cc_counter2_flagit_reg_expired_5_i_0_0 ( + .I0(N_56513_i), + .I1(plm_fsm_cc_counter2_reg_rx_expired_73), + .I2(plm_fsm_cc_counter2_reg_tx_expired_1880), + .LO(plm_fsm_cc_counter2_N_28773_i) + ); + defparam plm_fsm_cc_counter2_un1_enable_2_0_a2_i_0_0_o2.INIT = 8'hA8; + LUT3 plm_fsm_cc_counter2_un1_enable_2_0_a2_i_0_0_o2 ( + .I0(plm_fsm_cc_counter2_reg_oneshot_1878), + .I1(plm_fsm_reg_state_10__1792), + .I2(plm_fsm_reg_state_9__1795), + .O(plm_fsm_cc_counter2_N_56150_i) + ); + defparam plm_fsm_cc_counter2_N_87483_i.INIT = 8'hEF; + LUT3 plm_fsm_cc_counter2_N_87483_i ( + .I0(plm_reg_sym_sent_6_), + .I1(plm_fsm_cc_counter2_reg_tx_expired_1880), + .I2(plm_fsm_cc_counter2_N_56150_i), + .O(plm_fsm_cc_counter2_N_87483_i_1877) + ); + defparam plm_fsm_cc_counter2_N_29086_i_i.INIT = 4'hB; + LUT2 plm_fsm_cc_counter2_N_29086_i_i ( + .I0(plm_fsm_cc_counter2_reg_tx_expired_1880), + .I1(plm_fsm_cc_counter2_N_56150_i), + .O(plm_fsm_cc_counter2_N_29086_i_i_1876) + ); + FDCE plm_fsm_cc_counter2_reg_tx_count_7_ ( + .CE(plm_fsm_cc_counter2_N_87483_i_1877), + .C(mgt_clk), + .D(plm_fsm_cc_counter2_reg_tx_count_s[7]), + .Q(plm_fsm_cc_counter2_reg_tx_count[7]), + .CLR(plm_rst) + ); + FDCE plm_fsm_cc_counter2_reg_tx_count_6_ ( + .CE(plm_fsm_cc_counter2_N_87483_i_1877), + .C(mgt_clk), + .D(plm_fsm_cc_counter2_reg_tx_count_s[6]), + .Q(plm_fsm_cc_counter2_reg_tx_count[6]), + .CLR(plm_rst) + ); + FDCE plm_fsm_cc_counter2_reg_tx_count_5_ ( + .CE(plm_fsm_cc_counter2_N_87483_i_1877), + .C(mgt_clk), + .D(plm_fsm_cc_counter2_reg_tx_count_s[5]), + .Q(plm_fsm_cc_counter2_reg_tx_count[5]), + .CLR(plm_rst) + ); + FDPE plm_fsm_cc_counter2_reg_tx_count_4_ ( + .PRE(plm_rst), + .CE(plm_fsm_cc_counter2_N_87483_i_1877), + .C(mgt_clk), + .D(plm_fsm_cc_counter2_reg_tx_count_s[4]), + .Q(plm_fsm_cc_counter2_reg_tx_count[4]) + ); + FDCE plm_fsm_cc_counter2_reg_tx_count_3_ ( + .CE(plm_fsm_cc_counter2_N_87483_i_1877), + .C(mgt_clk), + .D(plm_fsm_cc_counter2_reg_tx_count_s[3]), + .Q(plm_fsm_cc_counter2_reg_tx_count[3]), + .CLR(plm_rst) + ); + FDCE plm_fsm_cc_counter2_reg_tx_count_2_ ( + .CE(plm_fsm_cc_counter2_N_87483_i_1877), + .C(mgt_clk), + .D(plm_fsm_cc_counter2_reg_tx_count_s[2]), + .Q(plm_fsm_cc_counter2_reg_tx_count[2]), + .CLR(plm_rst) + ); + FDCE plm_fsm_cc_counter2_reg_tx_count_1_ ( + .CE(plm_fsm_cc_counter2_N_87483_i_1877), + .C(mgt_clk), + .D(plm_fsm_cc_counter2_reg_tx_count_s[1]), + .Q(plm_fsm_cc_counter2_reg_tx_count[1]), + .CLR(plm_rst) + ); + FDCE plm_fsm_cc_counter2_reg_tx_count_0_ ( + .CE(plm_fsm_cc_counter2_N_87483_i_1877), + .C(mgt_clk), + .D(plm_fsm_cc_counter2_reg_tx_count_s[0]), + .Q(plm_fsm_cc_counter2_reg_tx_count[0]), + .CLR(plm_rst) + ); + FDCE plm_fsm_cc_counter2_reg_rx_count_7_ ( + .CE(plm_fsm_cc_counter2_N_87481_i), + .C(mgt_clk), + .D(plm_fsm_cc_counter2_reg_rx_count_s[7]), + .Q(plm_fsm_cc_counter2_reg_rx_count[7]), + .CLR(plm_rst) + ); + FDCE plm_fsm_cc_counter2_reg_rx_count_6_ ( + .CE(plm_fsm_cc_counter2_N_87481_i), + .C(mgt_clk), + .D(plm_fsm_cc_counter2_reg_rx_count_s[6]), + .Q(plm_fsm_cc_counter2_reg_rx_count[6]), + .CLR(plm_rst) + ); + FDCE plm_fsm_cc_counter2_reg_rx_count_5_ ( + .CE(plm_fsm_cc_counter2_N_87481_i), + .C(mgt_clk), + .D(plm_fsm_cc_counter2_reg_rx_count_s[5]), + .Q(plm_fsm_cc_counter2_reg_rx_count[5]), + .CLR(plm_rst) + ); + FDCE plm_fsm_cc_counter2_reg_rx_count_4_ ( + .CE(plm_fsm_cc_counter2_N_87481_i), + .C(mgt_clk), + .D(plm_fsm_cc_counter2_reg_rx_count_s[4]), + .Q(plm_fsm_cc_counter2_reg_rx_count[4]), + .CLR(plm_rst) + ); + FDPE plm_fsm_cc_counter2_reg_rx_count_3_ ( + .PRE(plm_rst), + .CE(plm_fsm_cc_counter2_N_87481_i), + .C(mgt_clk), + .D(plm_fsm_cc_counter2_reg_rx_count_s[3]), + .Q(plm_fsm_cc_counter2_reg_rx_count[3]) + ); + FDCE plm_fsm_cc_counter2_reg_rx_count_2_ ( + .CE(plm_fsm_cc_counter2_N_87481_i), + .C(mgt_clk), + .D(plm_fsm_cc_counter2_reg_rx_count_s[2]), + .Q(plm_fsm_cc_counter2_reg_rx_count[2]), + .CLR(plm_rst) + ); + FDCE plm_fsm_cc_counter2_reg_rx_count_1_ ( + .CE(plm_fsm_cc_counter2_N_87481_i), + .C(mgt_clk), + .D(plm_fsm_cc_counter2_reg_rx_count_s[1]), + .Q(plm_fsm_cc_counter2_reg_rx_count[1]), + .CLR(plm_rst) + ); + FDCE plm_fsm_cc_counter2_reg_rx_count_0_ ( + .CE(plm_fsm_cc_counter2_N_87481_i), + .C(mgt_clk), + .D(plm_fsm_cc_counter2_reg_rx_count_s[0]), + .Q(plm_fsm_cc_counter2_reg_rx_count[0]), + .CLR(plm_rst) + ); + FDC plm_fsm_cc_counter2_reg_expired ( + .C(mgt_clk), + .D(plm_fsm_cc_counter2_N_28773_i), + .Q(plm_fsm_cc_cntrout2), + .CLR(plm_rst) + ); + FDCE plm_fsm_cc_counter2_reg_oneshot ( + .CE(plm_fsm_cc_counter2_N_87219_i), + .C(mgt_clk), + .D(plm_fsm_N_56513_i_i_1804), + .Q(plm_fsm_cc_counter2_reg_oneshot_1878), + .CLR(plm_rst) + ); + FDCE plm_fsm_cc_counter2_reg_rx_expired ( + .CE(plm_fsm_cc_counter2_N_87555_i), + .C(mgt_clk), + .D(plm_fsm_N_56513_i_i_1804), + .Q(plm_fsm_cc_counter2_reg_rx_expired_73), + .CLR(plm_rst) + ); + FDCE plm_fsm_cc_counter2_reg_tx_expired ( + .CE(plm_fsm_cc_counter2_N_87212_i_1879), + .C(mgt_clk), + .D(plm_fsm_cc_counter2_N_56150_i), + .Q(plm_fsm_cc_counter2_reg_tx_expired_1880), + .CLR(plm_rst) + ); + INV plm_fsm_cc_counter2_oneshot_monitor_N_87219_i ( + .I(plm_fsm_cc_counter2_un1_enable_i_o2_0_0), + .O(plm_fsm_cc_counter2_N_87219_i) + ); + defparam plm_fsm_cc_counter2_reg_rx_count_qxu_0_0_.INIT = 4'h7; + LUT2_L plm_fsm_cc_counter2_reg_rx_count_qxu_0_0_ ( + .I0(N_28971_i), + .I1(plm_fsm_cc_counter2_reg_rx_count[0]), + .LO(plm_fsm_cc_counter2_reg_rx_count_qxu[0]) + ); + defparam plm_fsm_cc_counter2_reg_rx_count_qxu_0_1_.INIT = 4'h7; + LUT2_L plm_fsm_cc_counter2_reg_rx_count_qxu_0_1_ ( + .I0(N_28971_i), + .I1(plm_fsm_cc_counter2_reg_rx_count[1]), + .LO(plm_fsm_cc_counter2_reg_rx_count_qxu[1]) + ); + defparam plm_fsm_cc_counter2_reg_rx_count_qxu_0_2_.INIT = 4'h7; + LUT2_L plm_fsm_cc_counter2_reg_rx_count_qxu_0_2_ ( + .I0(N_28971_i), + .I1(plm_fsm_cc_counter2_reg_rx_count[2]), + .LO(plm_fsm_cc_counter2_reg_rx_count_qxu[2]) + ); + defparam plm_fsm_cc_counter2_reg_rx_count_qxu_0_3_.INIT = 8'h1B; + LUT3_L plm_fsm_cc_counter2_reg_rx_count_qxu_0_3_ ( + .I0(N_28971_i), + .I1(plm_fsm_cc_counter2_N_87207_i_1881), + .I2(plm_fsm_cc_counter2_reg_rx_count[3]), + .LO(plm_fsm_cc_counter2_reg_rx_count_qxu[3]) + ); + defparam plm_fsm_cc_counter2_reg_rx_count_qxu_0_4_.INIT = 4'h7; + LUT2_L plm_fsm_cc_counter2_reg_rx_count_qxu_0_4_ ( + .I0(N_28971_i), + .I1(plm_fsm_cc_counter2_reg_rx_count[4]), + .LO(plm_fsm_cc_counter2_reg_rx_count_qxu[4]) + ); + defparam plm_fsm_cc_counter2_reg_rx_count_qxu_0_5_.INIT = 4'h7; + LUT2_L plm_fsm_cc_counter2_reg_rx_count_qxu_0_5_ ( + .I0(N_28971_i), + .I1(plm_fsm_cc_counter2_reg_rx_count[5]), + .LO(plm_fsm_cc_counter2_reg_rx_count_qxu[5]) + ); + defparam plm_fsm_cc_counter2_reg_rx_count_qxu_0_6_.INIT = 4'h7; + LUT2_L plm_fsm_cc_counter2_reg_rx_count_qxu_0_6_ ( + .I0(N_28971_i), + .I1(plm_fsm_cc_counter2_reg_rx_count[6]), + .LO(plm_fsm_cc_counter2_reg_rx_count_qxu[6]) + ); + defparam plm_fsm_cc_counter2_reg_rx_count_qxu_0_7_.INIT = 4'h7; + LUT2_L plm_fsm_cc_counter2_reg_rx_count_qxu_0_7_ ( + .I0(N_28971_i), + .I1(plm_fsm_cc_counter2_reg_rx_count[7]), + .LO(plm_fsm_cc_counter2_reg_rx_count_qxu[7]) + ); + defparam plm_fsm_cc_counter2_reg_tx_count_qxu_0_0_.INIT = 4'h7; + LUT2_L plm_fsm_cc_counter2_reg_tx_count_qxu_0_0_ ( + .I0(plm_fsm_cc_counter2_N_29086_i), + .I1(plm_fsm_cc_counter2_reg_tx_count[0]), + .LO(plm_fsm_cc_counter2_reg_tx_count_qxu[0]) + ); + defparam plm_fsm_cc_counter2_reg_tx_count_qxu_0_1_.INIT = 4'h7; + LUT2_L plm_fsm_cc_counter2_reg_tx_count_qxu_0_1_ ( + .I0(plm_fsm_cc_counter2_N_29086_i), + .I1(plm_fsm_cc_counter2_reg_tx_count[1]), + .LO(plm_fsm_cc_counter2_reg_tx_count_qxu[1]) + ); + defparam plm_fsm_cc_counter2_reg_tx_count_qxu_0_2_.INIT = 4'h7; + LUT2_L plm_fsm_cc_counter2_reg_tx_count_qxu_0_2_ ( + .I0(plm_fsm_cc_counter2_N_29086_i), + .I1(plm_fsm_cc_counter2_reg_tx_count[2]), + .LO(plm_fsm_cc_counter2_reg_tx_count_qxu[2]) + ); + defparam plm_fsm_cc_counter2_reg_tx_count_qxu_0_3_.INIT = 4'h7; + LUT2_L plm_fsm_cc_counter2_reg_tx_count_qxu_0_3_ ( + .I0(plm_fsm_cc_counter2_N_29086_i), + .I1(plm_fsm_cc_counter2_reg_tx_count[3]), + .LO(plm_fsm_cc_counter2_reg_tx_count_qxu[3]) + ); + defparam plm_fsm_cc_counter2_reg_tx_count_qxu_0_4_.INIT = 8'h4E; + LUT3_L plm_fsm_cc_counter2_reg_tx_count_qxu_0_4_ ( + .I0(plm_fsm_cc_counter2_N_29086_i), + .I1(plm_fsm_cc_counter2_N_56150_i), + .I2(plm_fsm_cc_counter2_reg_tx_count[4]), + .LO(plm_fsm_cc_counter2_reg_tx_count_qxu[4]) + ); + defparam plm_fsm_cc_counter2_reg_tx_count_qxu_0_5_.INIT = 4'h7; + LUT2_L plm_fsm_cc_counter2_reg_tx_count_qxu_0_5_ ( + .I0(plm_fsm_cc_counter2_N_29086_i), + .I1(plm_fsm_cc_counter2_reg_tx_count[5]), + .LO(plm_fsm_cc_counter2_reg_tx_count_qxu[5]) + ); + defparam plm_fsm_cc_counter2_reg_tx_count_qxu_0_6_.INIT = 4'h7; + LUT2_L plm_fsm_cc_counter2_reg_tx_count_qxu_0_6_ ( + .I0(plm_fsm_cc_counter2_N_29086_i), + .I1(plm_fsm_cc_counter2_reg_tx_count[6]), + .LO(plm_fsm_cc_counter2_reg_tx_count_qxu[6]) + ); + defparam plm_fsm_cc_counter2_reg_tx_count_qxu_0_7_.INIT = 4'h7; + LUT2_L plm_fsm_cc_counter2_reg_tx_count_qxu_0_7_ ( + .I0(plm_fsm_cc_counter2_N_29086_i), + .I1(plm_fsm_cc_counter2_reg_tx_count[7]), + .LO(plm_fsm_cc_counter2_reg_tx_count_qxu[7]) + ); + VCC plm_fsm_cc_counter3_VCC ( + .P(plm_fsm_cc_counter3_VCC_1882) + ); + MUXCY_L plm_fsm_cc_counter3_reg_rx_count_cry_0_ ( + .CI(N_22825_i_79), + .DI(plm_fsm_cc_counter3_VCC_1882), + .LO(plm_fsm_cc_counter3_reg_rx_count_cry[0]), + .S(plm_fsm_cc_counter3_reg_rx_count_qxu[0]) + ); + XORCY plm_fsm_cc_counter3_reg_rx_count_s_0_ ( + .CI(N_22825_i_79), + .LI(plm_fsm_cc_counter3_reg_rx_count_qxu[0]), + .O(plm_fsm_cc_counter3_reg_rx_count_s[0]) + ); + MUXCY_L plm_fsm_cc_counter3_reg_rx_count_cry_1_ ( + .CI(plm_fsm_cc_counter3_reg_rx_count_cry[0]), + .DI(plm_fsm_cc_counter3_VCC_1882), + .LO(plm_fsm_cc_counter3_reg_rx_count_cry[1]), + .S(plm_fsm_cc_counter3_reg_rx_count_qxu[1]) + ); + XORCY plm_fsm_cc_counter3_reg_rx_count_s_1_ ( + .CI(plm_fsm_cc_counter3_reg_rx_count_cry[0]), + .LI(plm_fsm_cc_counter3_reg_rx_count_qxu[1]), + .O(plm_fsm_cc_counter3_reg_rx_count_s[1]) + ); + MUXCY_L plm_fsm_cc_counter3_reg_rx_count_cry_2_ ( + .CI(plm_fsm_cc_counter3_reg_rx_count_cry[1]), + .DI(plm_fsm_cc_counter3_VCC_1882), + .LO(plm_fsm_cc_counter3_reg_rx_count_cry[2]), + .S(plm_fsm_cc_counter3_reg_rx_count_qxu[2]) + ); + XORCY plm_fsm_cc_counter3_reg_rx_count_s_2_ ( + .CI(plm_fsm_cc_counter3_reg_rx_count_cry[1]), + .LI(plm_fsm_cc_counter3_reg_rx_count_qxu[2]), + .O(plm_fsm_cc_counter3_reg_rx_count_s[2]) + ); + MUXCY_L plm_fsm_cc_counter3_reg_rx_count_cry_3_ ( + .CI(plm_fsm_cc_counter3_reg_rx_count_cry[2]), + .DI(plm_fsm_cc_counter3_VCC_1882), + .LO(plm_fsm_cc_counter3_reg_rx_count_cry[3]), + .S(plm_fsm_cc_counter3_reg_rx_count_qxu[3]) + ); + XORCY plm_fsm_cc_counter3_reg_rx_count_s_3_ ( + .CI(plm_fsm_cc_counter3_reg_rx_count_cry[2]), + .LI(plm_fsm_cc_counter3_reg_rx_count_qxu[3]), + .O(plm_fsm_cc_counter3_reg_rx_count_s[3]) + ); + MUXCY_L plm_fsm_cc_counter3_reg_rx_count_cry_4_ ( + .CI(plm_fsm_cc_counter3_reg_rx_count_cry[3]), + .DI(plm_fsm_cc_counter3_VCC_1882), + .LO(plm_fsm_cc_counter3_reg_rx_count_cry[4]), + .S(plm_fsm_cc_counter3_reg_rx_count_qxu[4]) + ); + XORCY plm_fsm_cc_counter3_reg_rx_count_s_4_ ( + .CI(plm_fsm_cc_counter3_reg_rx_count_cry[3]), + .LI(plm_fsm_cc_counter3_reg_rx_count_qxu[4]), + .O(plm_fsm_cc_counter3_reg_rx_count_s[4]) + ); + MUXCY_L plm_fsm_cc_counter3_reg_rx_count_cry_5_ ( + .CI(plm_fsm_cc_counter3_reg_rx_count_cry[4]), + .DI(plm_fsm_cc_counter3_VCC_1882), + .LO(plm_fsm_cc_counter3_reg_rx_count_cry[5]), + .S(plm_fsm_cc_counter3_reg_rx_count_qxu[5]) + ); + XORCY plm_fsm_cc_counter3_reg_rx_count_s_5_ ( + .CI(plm_fsm_cc_counter3_reg_rx_count_cry[4]), + .LI(plm_fsm_cc_counter3_reg_rx_count_qxu[5]), + .O(plm_fsm_cc_counter3_reg_rx_count_s[5]) + ); + MUXCY_L plm_fsm_cc_counter3_reg_rx_count_cry_6_ ( + .CI(plm_fsm_cc_counter3_reg_rx_count_cry[5]), + .DI(plm_fsm_cc_counter3_VCC_1882), + .LO(plm_fsm_cc_counter3_reg_rx_count_cry[6]), + .S(plm_fsm_cc_counter3_reg_rx_count_qxu[6]) + ); + XORCY plm_fsm_cc_counter3_reg_rx_count_s_6_ ( + .CI(plm_fsm_cc_counter3_reg_rx_count_cry[5]), + .LI(plm_fsm_cc_counter3_reg_rx_count_qxu[6]), + .O(plm_fsm_cc_counter3_reg_rx_count_s[6]) + ); + XORCY plm_fsm_cc_counter3_reg_rx_count_s_7_ ( + .CI(plm_fsm_cc_counter3_reg_rx_count_cry[6]), + .LI(plm_fsm_cc_counter3_reg_rx_count_qxu[7]), + .O(plm_fsm_cc_counter3_reg_rx_count_s[7]) + ); + MUXCY_L plm_fsm_cc_counter3_reg_tx_count_cry_0_ ( + .CI(plm_fsm_cc_counter3_N_29084_i_i_1883), + .DI(plm_fsm_cc_counter3_VCC_1882), + .LO(plm_fsm_cc_counter3_reg_tx_count_cry[0]), + .S(plm_fsm_cc_counter3_reg_tx_count_qxu[0]) + ); + XORCY plm_fsm_cc_counter3_reg_tx_count_s_0_ ( + .CI(plm_fsm_cc_counter3_N_29084_i_i_1883), + .LI(plm_fsm_cc_counter3_reg_tx_count_qxu[0]), + .O(plm_fsm_cc_counter3_reg_tx_count_s[0]) + ); + MUXCY_L plm_fsm_cc_counter3_reg_tx_count_cry_1_ ( + .CI(plm_fsm_cc_counter3_reg_tx_count_cry[0]), + .DI(plm_fsm_cc_counter3_VCC_1882), + .LO(plm_fsm_cc_counter3_reg_tx_count_cry[1]), + .S(plm_fsm_cc_counter3_reg_tx_count_qxu[1]) + ); + XORCY plm_fsm_cc_counter3_reg_tx_count_s_1_ ( + .CI(plm_fsm_cc_counter3_reg_tx_count_cry[0]), + .LI(plm_fsm_cc_counter3_reg_tx_count_qxu[1]), + .O(plm_fsm_cc_counter3_reg_tx_count_s[1]) + ); + MUXCY_L plm_fsm_cc_counter3_reg_tx_count_cry_2_ ( + .CI(plm_fsm_cc_counter3_reg_tx_count_cry[1]), + .DI(plm_fsm_cc_counter3_VCC_1882), + .LO(plm_fsm_cc_counter3_reg_tx_count_cry[2]), + .S(plm_fsm_cc_counter3_reg_tx_count_qxu[2]) + ); + XORCY plm_fsm_cc_counter3_reg_tx_count_s_2_ ( + .CI(plm_fsm_cc_counter3_reg_tx_count_cry[1]), + .LI(plm_fsm_cc_counter3_reg_tx_count_qxu[2]), + .O(plm_fsm_cc_counter3_reg_tx_count_s[2]) + ); + MUXCY_L plm_fsm_cc_counter3_reg_tx_count_cry_3_ ( + .CI(plm_fsm_cc_counter3_reg_tx_count_cry[2]), + .DI(plm_fsm_cc_counter3_VCC_1882), + .LO(plm_fsm_cc_counter3_reg_tx_count_cry[3]), + .S(plm_fsm_cc_counter3_reg_tx_count_qxu[3]) + ); + XORCY plm_fsm_cc_counter3_reg_tx_count_s_3_ ( + .CI(plm_fsm_cc_counter3_reg_tx_count_cry[2]), + .LI(plm_fsm_cc_counter3_reg_tx_count_qxu[3]), + .O(plm_fsm_cc_counter3_reg_tx_count_s[3]) + ); + MUXCY_L plm_fsm_cc_counter3_reg_tx_count_cry_4_ ( + .CI(plm_fsm_cc_counter3_reg_tx_count_cry[3]), + .DI(plm_fsm_cc_counter3_VCC_1882), + .LO(plm_fsm_cc_counter3_reg_tx_count_cry[4]), + .S(plm_fsm_cc_counter3_reg_tx_count_qxu[4]) + ); + XORCY plm_fsm_cc_counter3_reg_tx_count_s_4_ ( + .CI(plm_fsm_cc_counter3_reg_tx_count_cry[3]), + .LI(plm_fsm_cc_counter3_reg_tx_count_qxu[4]), + .O(plm_fsm_cc_counter3_reg_tx_count_s[4]) + ); + MUXCY_L plm_fsm_cc_counter3_reg_tx_count_cry_5_ ( + .CI(plm_fsm_cc_counter3_reg_tx_count_cry[4]), + .DI(plm_fsm_cc_counter3_VCC_1882), + .LO(plm_fsm_cc_counter3_reg_tx_count_cry[5]), + .S(plm_fsm_cc_counter3_reg_tx_count_qxu[5]) + ); + XORCY plm_fsm_cc_counter3_reg_tx_count_s_5_ ( + .CI(plm_fsm_cc_counter3_reg_tx_count_cry[4]), + .LI(plm_fsm_cc_counter3_reg_tx_count_qxu[5]), + .O(plm_fsm_cc_counter3_reg_tx_count_s[5]) + ); + MUXCY_L plm_fsm_cc_counter3_reg_tx_count_cry_6_ ( + .CI(plm_fsm_cc_counter3_reg_tx_count_cry[5]), + .DI(plm_fsm_cc_counter3_VCC_1882), + .LO(plm_fsm_cc_counter3_reg_tx_count_cry[6]), + .S(plm_fsm_cc_counter3_reg_tx_count_qxu[6]) + ); + XORCY plm_fsm_cc_counter3_reg_tx_count_s_6_ ( + .CI(plm_fsm_cc_counter3_reg_tx_count_cry[5]), + .LI(plm_fsm_cc_counter3_reg_tx_count_qxu[6]), + .O(plm_fsm_cc_counter3_reg_tx_count_s[6]) + ); + XORCY plm_fsm_cc_counter3_reg_tx_count_s_7_ ( + .CI(plm_fsm_cc_counter3_reg_tx_count_cry[6]), + .LI(plm_fsm_cc_counter3_reg_tx_count_qxu[7]), + .O(plm_fsm_cc_counter3_reg_tx_count_s[7]) + ); + defparam plm_fsm_cc_counter3_loadable_tx_counter_un1_reg_tx_count_0_a2_0_a3_4.INIT = 16'h0001; + LUT4 plm_fsm_cc_counter3_loadable_tx_counter_un1_reg_tx_count_0_a2_0_a3_4 ( + .I0(plm_fsm_cc_counter3_reg_tx_count[0]), + .I1(plm_fsm_cc_counter3_reg_tx_count[1]), + .I2(plm_fsm_cc_counter3_reg_tx_count[2]), + .I3(plm_fsm_cc_counter3_reg_tx_count[3]), + .O(plm_fsm_cc_counter3_un1_reg_tx_count_0_a2_0_a3_4) + ); + defparam plm_fsm_cc_counter3_loadable_tx_counter_un1_reg_tx_count_0_a2_0_a3_5.INIT = 16'h0001; + LUT4 plm_fsm_cc_counter3_loadable_tx_counter_un1_reg_tx_count_0_a2_0_a3_5 ( + .I0(plm_fsm_cc_counter3_reg_tx_count[4]), + .I1(plm_fsm_cc_counter3_reg_tx_count[5]), + .I2(plm_fsm_cc_counter3_reg_tx_count[6]), + .I3(plm_fsm_cc_counter3_reg_tx_count[7]), + .O(plm_fsm_cc_counter3_un1_reg_tx_count_0_a2_0_a3_5) + ); + defparam plm_fsm_cc_counter3_loadable_rx_counter_un1_reg_rx_count_0_a3_4.INIT = 16'h0001; + LUT4 plm_fsm_cc_counter3_loadable_rx_counter_un1_reg_rx_count_0_a3_4 ( + .I0(plm_fsm_cc_counter3_reg_rx_count[0]), + .I1(plm_fsm_cc_counter3_reg_rx_count[1]), + .I2(plm_fsm_cc_counter3_reg_rx_count[2]), + .I3(plm_fsm_cc_counter3_reg_rx_count[3]), + .O(plm_fsm_cc_counter3_un1_reg_rx_count_0_a3_4) + ); + defparam plm_fsm_cc_counter3_loadable_rx_counter_un1_reg_rx_count_0_a3_5.INIT = 16'h0001; + LUT4 plm_fsm_cc_counter3_loadable_rx_counter_un1_reg_rx_count_0_a3_5 ( + .I0(plm_fsm_cc_counter3_reg_rx_count[4]), + .I1(plm_fsm_cc_counter3_reg_rx_count[5]), + .I2(plm_fsm_cc_counter3_reg_rx_count[6]), + .I3(plm_fsm_cc_counter3_reg_rx_count[7]), + .O(plm_fsm_cc_counter3_un1_reg_rx_count_0_a3_5) + ); + defparam plm_fsm_cc_counter3_un1_enable_1_0_a3_i_0_0.INIT = 4'h2; + LUT2 plm_fsm_cc_counter3_un1_enable_1_0_a3_i_0_0 ( + .I0(plm_fsm_cc_counter3_N_56151_i), + .I1(plm_fsm_cc_counter3_reg_tx_expired_1887), + .O(plm_fsm_cc_counter3_N_29084_i) + ); + defparam plm_fsm_cc_counter3_N_87213_i.INIT = 8'hD5; + LUT3 plm_fsm_cc_counter3_N_87213_i ( + .I0(plm_fsm_cc_counter3_N_56151_i), + .I1(plm_fsm_cc_counter3_un1_reg_tx_count_0_a2_0_a3_4), + .I2(plm_fsm_cc_counter3_un1_reg_tx_count_0_a2_0_a3_5), + .O(plm_fsm_cc_counter3_N_87213_i_1886) + ); + defparam plm_fsm_cc_counter3_loadable_rx_counter_N_87206_i.INIT = 8'hEA; + LUT3 plm_fsm_cc_counter3_loadable_rx_counter_N_87206_i ( + .I0(N_56513_i), + .I1(plm_fsm_cc_counter3_un1_reg_rx_count_0_a3_4), + .I2(plm_fsm_cc_counter3_un1_reg_rx_count_0_a3_5), + .O(plm_fsm_cc_counter3_N_87206_i) + ); + defparam plm_fsm_cc_counter3_un1_enable_4_i_0_0_a2_1.INIT = 8'h2A; + LUT3 plm_fsm_cc_counter3_un1_enable_4_i_0_0_a2_1 ( + .I0(plm_reg_ts2_1_2), + .I1(N_56043_i), + .I2(plm_rx3_ts2_c), + .O(plm_fsm_N_59110_1) + ); + defparam plm_fsm_cc_counter3_N_87205_i.INIT = 8'hAE; + LUT3_L plm_fsm_cc_counter3_N_87205_i ( + .I0(N_56513_i), + .I1(plm_fsm_N_59110_1), + .I2(plm_fsm_cc_counter3_reg_rx_expired_78), + .LO(plm_fsm_cc_counter3_N_87205_i_1888) + ); + defparam plm_fsm_cc_counter3_flagit_reg_expired_5_i_0_0.INIT = 8'h40; + LUT3_L plm_fsm_cc_counter3_flagit_reg_expired_5_i_0_0 ( + .I0(N_56513_i), + .I1(plm_fsm_cc_counter3_reg_rx_expired_78), + .I2(plm_fsm_cc_counter3_reg_tx_expired_1887), + .LO(plm_fsm_cc_counter3_N_28771_i) + ); + defparam plm_fsm_cc_counter3_un1_enable_2_0_a2_i_0_0_o2.INIT = 8'hA8; + LUT3 plm_fsm_cc_counter3_un1_enable_2_0_a2_i_0_0_o2 ( + .I0(plm_fsm_cc_counter3_reg_oneshot_1885), + .I1(plm_fsm_reg_state_10__1792), + .I2(plm_fsm_reg_state_9__1795), + .O(plm_fsm_cc_counter3_N_56151_i) + ); + defparam plm_fsm_cc_counter3_loadable_rx_counter_N_87546_i.INIT = 8'hFE; + LUT3 plm_fsm_cc_counter3_loadable_rx_counter_N_87546_i ( + .I0(plm_fsm_cc_counter3_reg_rx_expired_78), + .I1(N_56513_i), + .I2(plm_reg_ts2_1_2), + .O(plm_fsm_cc_counter3_N_87546_i) + ); + defparam plm_fsm_cc_counter3_oneshot_monitor_N_28823_i_i.INIT = 4'hE; + LUT2 plm_fsm_cc_counter3_oneshot_monitor_N_28823_i_i ( + .I0(N_56513_i), + .I1(plm_reg_ts2_1_2), + .O(plm_fsm_cc_counter3_N_28823_i_i) + ); + defparam plm_fsm_cc_counter3_N_87482_i.INIT = 8'hEF; + LUT3 plm_fsm_cc_counter3_N_87482_i ( + .I0(plm_reg_sym_sent_6_), + .I1(plm_fsm_cc_counter3_reg_tx_expired_1887), + .I2(plm_fsm_cc_counter3_N_56151_i), + .O(plm_fsm_cc_counter3_N_87482_i_1884) + ); + defparam plm_fsm_cc_counter3_N_29084_i_i.INIT = 4'hB; + LUT2 plm_fsm_cc_counter3_N_29084_i_i ( + .I0(plm_fsm_cc_counter3_reg_tx_expired_1887), + .I1(plm_fsm_cc_counter3_N_56151_i), + .O(plm_fsm_cc_counter3_N_29084_i_i_1883) + ); + FDCE plm_fsm_cc_counter3_reg_tx_count_7_ ( + .CE(plm_fsm_cc_counter3_N_87482_i_1884), + .C(mgt_clk), + .D(plm_fsm_cc_counter3_reg_tx_count_s[7]), + .Q(plm_fsm_cc_counter3_reg_tx_count[7]), + .CLR(plm_rst) + ); + FDCE plm_fsm_cc_counter3_reg_tx_count_6_ ( + .CE(plm_fsm_cc_counter3_N_87482_i_1884), + .C(mgt_clk), + .D(plm_fsm_cc_counter3_reg_tx_count_s[6]), + .Q(plm_fsm_cc_counter3_reg_tx_count[6]), + .CLR(plm_rst) + ); + FDCE plm_fsm_cc_counter3_reg_tx_count_5_ ( + .CE(plm_fsm_cc_counter3_N_87482_i_1884), + .C(mgt_clk), + .D(plm_fsm_cc_counter3_reg_tx_count_s[5]), + .Q(plm_fsm_cc_counter3_reg_tx_count[5]), + .CLR(plm_rst) + ); + FDPE plm_fsm_cc_counter3_reg_tx_count_4_ ( + .PRE(plm_rst), + .CE(plm_fsm_cc_counter3_N_87482_i_1884), + .C(mgt_clk), + .D(plm_fsm_cc_counter3_reg_tx_count_s[4]), + .Q(plm_fsm_cc_counter3_reg_tx_count[4]) + ); + FDCE plm_fsm_cc_counter3_reg_tx_count_3_ ( + .CE(plm_fsm_cc_counter3_N_87482_i_1884), + .C(mgt_clk), + .D(plm_fsm_cc_counter3_reg_tx_count_s[3]), + .Q(plm_fsm_cc_counter3_reg_tx_count[3]), + .CLR(plm_rst) + ); + FDCE plm_fsm_cc_counter3_reg_tx_count_2_ ( + .CE(plm_fsm_cc_counter3_N_87482_i_1884), + .C(mgt_clk), + .D(plm_fsm_cc_counter3_reg_tx_count_s[2]), + .Q(plm_fsm_cc_counter3_reg_tx_count[2]), + .CLR(plm_rst) + ); + FDCE plm_fsm_cc_counter3_reg_tx_count_1_ ( + .CE(plm_fsm_cc_counter3_N_87482_i_1884), + .C(mgt_clk), + .D(plm_fsm_cc_counter3_reg_tx_count_s[1]), + .Q(plm_fsm_cc_counter3_reg_tx_count[1]), + .CLR(plm_rst) + ); + FDCE plm_fsm_cc_counter3_reg_tx_count_0_ ( + .CE(plm_fsm_cc_counter3_N_87482_i_1884), + .C(mgt_clk), + .D(plm_fsm_cc_counter3_reg_tx_count_s[0]), + .Q(plm_fsm_cc_counter3_reg_tx_count[0]), + .CLR(plm_rst) + ); + FDCE plm_fsm_cc_counter3_reg_rx_count_7_ ( + .CE(plm_fsm_cc_counter3_N_87546_i), + .C(mgt_clk), + .D(plm_fsm_cc_counter3_reg_rx_count_s[7]), + .Q(plm_fsm_cc_counter3_reg_rx_count[7]), + .CLR(plm_rst) + ); + FDCE plm_fsm_cc_counter3_reg_rx_count_6_ ( + .CE(plm_fsm_cc_counter3_N_87546_i), + .C(mgt_clk), + .D(plm_fsm_cc_counter3_reg_rx_count_s[6]), + .Q(plm_fsm_cc_counter3_reg_rx_count[6]), + .CLR(plm_rst) + ); + FDCE plm_fsm_cc_counter3_reg_rx_count_5_ ( + .CE(plm_fsm_cc_counter3_N_87546_i), + .C(mgt_clk), + .D(plm_fsm_cc_counter3_reg_rx_count_s[5]), + .Q(plm_fsm_cc_counter3_reg_rx_count[5]), + .CLR(plm_rst) + ); + FDCE plm_fsm_cc_counter3_reg_rx_count_4_ ( + .CE(plm_fsm_cc_counter3_N_87546_i), + .C(mgt_clk), + .D(plm_fsm_cc_counter3_reg_rx_count_s[4]), + .Q(plm_fsm_cc_counter3_reg_rx_count[4]), + .CLR(plm_rst) + ); + FDPE plm_fsm_cc_counter3_reg_rx_count_3_ ( + .PRE(plm_rst), + .CE(plm_fsm_cc_counter3_N_87546_i), + .C(mgt_clk), + .D(plm_fsm_cc_counter3_reg_rx_count_s[3]), + .Q(plm_fsm_cc_counter3_reg_rx_count[3]) + ); + FDCE plm_fsm_cc_counter3_reg_rx_count_2_ ( + .CE(plm_fsm_cc_counter3_N_87546_i), + .C(mgt_clk), + .D(plm_fsm_cc_counter3_reg_rx_count_s[2]), + .Q(plm_fsm_cc_counter3_reg_rx_count[2]), + .CLR(plm_rst) + ); + FDCE plm_fsm_cc_counter3_reg_rx_count_1_ ( + .CE(plm_fsm_cc_counter3_N_87546_i), + .C(mgt_clk), + .D(plm_fsm_cc_counter3_reg_rx_count_s[1]), + .Q(plm_fsm_cc_counter3_reg_rx_count[1]), + .CLR(plm_rst) + ); + FDCE plm_fsm_cc_counter3_reg_rx_count_0_ ( + .CE(plm_fsm_cc_counter3_N_87546_i), + .C(mgt_clk), + .D(plm_fsm_cc_counter3_reg_rx_count_s[0]), + .Q(plm_fsm_cc_counter3_reg_rx_count[0]), + .CLR(plm_rst) + ); + FDC plm_fsm_cc_counter3_reg_expired ( + .C(mgt_clk), + .D(plm_fsm_cc_counter3_N_28771_i), + .Q(plm_fsm_cc_cntrout3), + .CLR(plm_rst) + ); + FDCE plm_fsm_cc_counter3_reg_oneshot ( + .CE(plm_fsm_cc_counter3_N_28823_i_i), + .C(mgt_clk), + .D(plm_fsm_N_56513_i_i_1804), + .Q(plm_fsm_cc_counter3_reg_oneshot_1885), + .CLR(plm_rst) + ); + FDCE plm_fsm_cc_counter3_reg_rx_expired ( + .CE(plm_fsm_cc_counter3_N_87206_i), + .C(mgt_clk), + .D(plm_fsm_N_56513_i_i_1804), + .Q(plm_fsm_cc_counter3_reg_rx_expired_78), + .CLR(plm_rst) + ); + FDCE plm_fsm_cc_counter3_reg_tx_expired ( + .CE(plm_fsm_cc_counter3_N_87213_i_1886), + .C(mgt_clk), + .D(plm_fsm_cc_counter3_N_56151_i), + .Q(plm_fsm_cc_counter3_reg_tx_expired_1887), + .CLR(plm_rst) + ); + defparam plm_fsm_cc_counter3_reg_rx_count_qxu_0_0_.INIT = 4'h7; + LUT2_L plm_fsm_cc_counter3_reg_rx_count_qxu_0_0_ ( + .I0(N_22825), + .I1(plm_fsm_cc_counter3_reg_rx_count[0]), + .LO(plm_fsm_cc_counter3_reg_rx_count_qxu[0]) + ); + defparam plm_fsm_cc_counter3_reg_rx_count_qxu_0_1_.INIT = 4'h7; + LUT2_L plm_fsm_cc_counter3_reg_rx_count_qxu_0_1_ ( + .I0(N_22825), + .I1(plm_fsm_cc_counter3_reg_rx_count[1]), + .LO(plm_fsm_cc_counter3_reg_rx_count_qxu[1]) + ); + defparam plm_fsm_cc_counter3_reg_rx_count_qxu_0_2_.INIT = 4'h7; + LUT2_L plm_fsm_cc_counter3_reg_rx_count_qxu_0_2_ ( + .I0(N_22825), + .I1(plm_fsm_cc_counter3_reg_rx_count[2]), + .LO(plm_fsm_cc_counter3_reg_rx_count_qxu[2]) + ); + defparam plm_fsm_cc_counter3_reg_rx_count_qxu_0_3_.INIT = 8'h1B; + LUT3_L plm_fsm_cc_counter3_reg_rx_count_qxu_0_3_ ( + .I0(N_22825), + .I1(plm_fsm_cc_counter3_N_87205_i_1888), + .I2(plm_fsm_cc_counter3_reg_rx_count[3]), + .LO(plm_fsm_cc_counter3_reg_rx_count_qxu[3]) + ); + defparam plm_fsm_cc_counter3_reg_rx_count_qxu_0_4_.INIT = 4'h7; + LUT2_L plm_fsm_cc_counter3_reg_rx_count_qxu_0_4_ ( + .I0(N_22825), + .I1(plm_fsm_cc_counter3_reg_rx_count[4]), + .LO(plm_fsm_cc_counter3_reg_rx_count_qxu[4]) + ); + defparam plm_fsm_cc_counter3_reg_rx_count_qxu_0_5_.INIT = 4'h7; + LUT2_L plm_fsm_cc_counter3_reg_rx_count_qxu_0_5_ ( + .I0(N_22825), + .I1(plm_fsm_cc_counter3_reg_rx_count[5]), + .LO(plm_fsm_cc_counter3_reg_rx_count_qxu[5]) + ); + defparam plm_fsm_cc_counter3_reg_rx_count_qxu_0_6_.INIT = 4'h7; + LUT2_L plm_fsm_cc_counter3_reg_rx_count_qxu_0_6_ ( + .I0(N_22825), + .I1(plm_fsm_cc_counter3_reg_rx_count[6]), + .LO(plm_fsm_cc_counter3_reg_rx_count_qxu[6]) + ); + defparam plm_fsm_cc_counter3_reg_rx_count_qxu_0_7_.INIT = 4'h7; + LUT2_L plm_fsm_cc_counter3_reg_rx_count_qxu_0_7_ ( + .I0(N_22825), + .I1(plm_fsm_cc_counter3_reg_rx_count[7]), + .LO(plm_fsm_cc_counter3_reg_rx_count_qxu[7]) + ); + defparam plm_fsm_cc_counter3_reg_tx_count_qxu_0_0_.INIT = 4'h7; + LUT2_L plm_fsm_cc_counter3_reg_tx_count_qxu_0_0_ ( + .I0(plm_fsm_cc_counter3_N_29084_i), + .I1(plm_fsm_cc_counter3_reg_tx_count[0]), + .LO(plm_fsm_cc_counter3_reg_tx_count_qxu[0]) + ); + defparam plm_fsm_cc_counter3_reg_tx_count_qxu_0_1_.INIT = 4'h7; + LUT2_L plm_fsm_cc_counter3_reg_tx_count_qxu_0_1_ ( + .I0(plm_fsm_cc_counter3_N_29084_i), + .I1(plm_fsm_cc_counter3_reg_tx_count[1]), + .LO(plm_fsm_cc_counter3_reg_tx_count_qxu[1]) + ); + defparam plm_fsm_cc_counter3_reg_tx_count_qxu_0_2_.INIT = 4'h7; + LUT2_L plm_fsm_cc_counter3_reg_tx_count_qxu_0_2_ ( + .I0(plm_fsm_cc_counter3_N_29084_i), + .I1(plm_fsm_cc_counter3_reg_tx_count[2]), + .LO(plm_fsm_cc_counter3_reg_tx_count_qxu[2]) + ); + defparam plm_fsm_cc_counter3_reg_tx_count_qxu_0_3_.INIT = 4'h7; + LUT2_L plm_fsm_cc_counter3_reg_tx_count_qxu_0_3_ ( + .I0(plm_fsm_cc_counter3_N_29084_i), + .I1(plm_fsm_cc_counter3_reg_tx_count[3]), + .LO(plm_fsm_cc_counter3_reg_tx_count_qxu[3]) + ); + defparam plm_fsm_cc_counter3_reg_tx_count_qxu_0_4_.INIT = 8'h4E; + LUT3_L plm_fsm_cc_counter3_reg_tx_count_qxu_0_4_ ( + .I0(plm_fsm_cc_counter3_N_29084_i), + .I1(plm_fsm_cc_counter3_N_56151_i), + .I2(plm_fsm_cc_counter3_reg_tx_count[4]), + .LO(plm_fsm_cc_counter3_reg_tx_count_qxu[4]) + ); + defparam plm_fsm_cc_counter3_reg_tx_count_qxu_0_5_.INIT = 4'h7; + LUT2_L plm_fsm_cc_counter3_reg_tx_count_qxu_0_5_ ( + .I0(plm_fsm_cc_counter3_N_29084_i), + .I1(plm_fsm_cc_counter3_reg_tx_count[5]), + .LO(plm_fsm_cc_counter3_reg_tx_count_qxu[5]) + ); + defparam plm_fsm_cc_counter3_reg_tx_count_qxu_0_6_.INIT = 4'h7; + LUT2_L plm_fsm_cc_counter3_reg_tx_count_qxu_0_6_ ( + .I0(plm_fsm_cc_counter3_N_29084_i), + .I1(plm_fsm_cc_counter3_reg_tx_count[6]), + .LO(plm_fsm_cc_counter3_reg_tx_count_qxu[6]) + ); + defparam plm_fsm_cc_counter3_reg_tx_count_qxu_0_7_.INIT = 4'h7; + LUT2_L plm_fsm_cc_counter3_reg_tx_count_qxu_0_7_ ( + .I0(plm_fsm_cc_counter3_N_29084_i), + .I1(plm_fsm_cc_counter3_reg_tx_count[7]), + .LO(plm_fsm_cc_counter3_reg_tx_count_qxu[7]) + ); + GND plm_fsm_ci_timer_GND ( + .G(plm_fsm_ci_timer_GND_1889) + ); + MUXCY_L plm_fsm_ci_timer_reg_count_cry_0_ ( + .CI(plm_fsm_reg_state_11__608), + .DI(plm_fsm_ci_timer_GND_1889), + .LO(plm_fsm_ci_timer_reg_count_cry[0]), + .S(plm_fsm_ci_timer_reg_count_qxu[0]) + ); + XORCY plm_fsm_ci_timer_reg_count_s_0_ ( + .CI(plm_fsm_reg_state_11__608), + .LI(plm_fsm_ci_timer_reg_count_qxu[0]), + .O(plm_fsm_ci_timer_reg_count_s[0]) + ); + MUXCY_L plm_fsm_ci_timer_reg_count_cry_1_ ( + .CI(plm_fsm_ci_timer_reg_count_cry[0]), + .DI(plm_fsm_ci_timer_GND_1889), + .LO(plm_fsm_ci_timer_reg_count_cry[1]), + .S(plm_fsm_ci_timer_reg_count_qxu[1]) + ); + XORCY plm_fsm_ci_timer_reg_count_s_1_ ( + .CI(plm_fsm_ci_timer_reg_count_cry[0]), + .LI(plm_fsm_ci_timer_reg_count_qxu[1]), + .O(plm_fsm_ci_timer_reg_count_s[1]) + ); + MUXCY_L plm_fsm_ci_timer_reg_count_cry_2_ ( + .CI(plm_fsm_ci_timer_reg_count_cry[1]), + .DI(plm_fsm_ci_timer_GND_1889), + .LO(plm_fsm_ci_timer_reg_count_cry[2]), + .S(plm_fsm_ci_timer_reg_count_qxu[2]) + ); + XORCY plm_fsm_ci_timer_reg_count_s_2_ ( + .CI(plm_fsm_ci_timer_reg_count_cry[1]), + .LI(plm_fsm_ci_timer_reg_count_qxu[2]), + .O(plm_fsm_ci_timer_reg_count_s[2]) + ); + MUXCY_L plm_fsm_ci_timer_reg_count_cry_3_ ( + .CI(plm_fsm_ci_timer_reg_count_cry[2]), + .DI(plm_fsm_ci_timer_GND_1889), + .LO(plm_fsm_ci_timer_reg_count_cry[3]), + .S(plm_fsm_ci_timer_reg_count_qxu[3]) + ); + XORCY plm_fsm_ci_timer_reg_count_s_3_ ( + .CI(plm_fsm_ci_timer_reg_count_cry[2]), + .LI(plm_fsm_ci_timer_reg_count_qxu[3]), + .O(plm_fsm_ci_timer_reg_count_s[3]) + ); + MUXCY_L plm_fsm_ci_timer_reg_count_cry_4_ ( + .CI(plm_fsm_ci_timer_reg_count_cry[3]), + .DI(plm_fsm_ci_timer_GND_1889), + .LO(plm_fsm_ci_timer_reg_count_cry[4]), + .S(plm_fsm_ci_timer_reg_count_qxu[4]) + ); + XORCY plm_fsm_ci_timer_reg_count_s_4_ ( + .CI(plm_fsm_ci_timer_reg_count_cry[3]), + .LI(plm_fsm_ci_timer_reg_count_qxu[4]), + .O(plm_fsm_ci_timer_reg_count_s[4]) + ); + MUXCY_L plm_fsm_ci_timer_reg_count_cry_5_ ( + .CI(plm_fsm_ci_timer_reg_count_cry[4]), + .DI(plm_fsm_ci_timer_GND_1889), + .LO(plm_fsm_ci_timer_reg_count_cry[5]), + .S(plm_fsm_ci_timer_reg_count_qxu[5]) + ); + XORCY plm_fsm_ci_timer_reg_count_s_5_ ( + .CI(plm_fsm_ci_timer_reg_count_cry[4]), + .LI(plm_fsm_ci_timer_reg_count_qxu[5]), + .O(plm_fsm_ci_timer_reg_count_s[5]) + ); + MUXCY_L plm_fsm_ci_timer_reg_count_cry_6_ ( + .CI(plm_fsm_ci_timer_reg_count_cry[5]), + .DI(plm_fsm_ci_timer_GND_1889), + .LO(plm_fsm_ci_timer_reg_count_cry[6]), + .S(plm_fsm_ci_timer_reg_count_qxu[6]) + ); + XORCY plm_fsm_ci_timer_reg_count_s_6_ ( + .CI(plm_fsm_ci_timer_reg_count_cry[5]), + .LI(plm_fsm_ci_timer_reg_count_qxu[6]), + .O(plm_fsm_ci_timer_reg_count_s[6]) + ); + MUXCY_L plm_fsm_ci_timer_reg_count_cry_7_ ( + .CI(plm_fsm_ci_timer_reg_count_cry[6]), + .DI(plm_fsm_ci_timer_GND_1889), + .LO(plm_fsm_ci_timer_reg_count_cry[7]), + .S(plm_fsm_ci_timer_reg_count_qxu[7]) + ); + XORCY plm_fsm_ci_timer_reg_count_s_7_ ( + .CI(plm_fsm_ci_timer_reg_count_cry[6]), + .LI(plm_fsm_ci_timer_reg_count_qxu[7]), + .O(plm_fsm_ci_timer_reg_count_s[7]) + ); + MUXCY_L plm_fsm_ci_timer_reg_count_cry_8_ ( + .CI(plm_fsm_ci_timer_reg_count_cry[7]), + .DI(plm_fsm_ci_timer_GND_1889), + .LO(plm_fsm_ci_timer_reg_count_cry[8]), + .S(plm_fsm_ci_timer_reg_count_qxu[8]) + ); + XORCY plm_fsm_ci_timer_reg_count_s_8_ ( + .CI(plm_fsm_ci_timer_reg_count_cry[7]), + .LI(plm_fsm_ci_timer_reg_count_qxu[8]), + .O(plm_fsm_ci_timer_reg_count_s[8]) + ); + MUXCY_L plm_fsm_ci_timer_reg_count_cry_9_ ( + .CI(plm_fsm_ci_timer_reg_count_cry[8]), + .DI(plm_fsm_ci_timer_GND_1889), + .LO(plm_fsm_ci_timer_reg_count_cry[9]), + .S(plm_fsm_ci_timer_reg_count_qxu[9]) + ); + XORCY plm_fsm_ci_timer_reg_count_s_9_ ( + .CI(plm_fsm_ci_timer_reg_count_cry[8]), + .LI(plm_fsm_ci_timer_reg_count_qxu[9]), + .O(plm_fsm_ci_timer_reg_count_s[9]) + ); + MUXCY_L plm_fsm_ci_timer_reg_count_cry_10_ ( + .CI(plm_fsm_ci_timer_reg_count_cry[9]), + .DI(plm_fsm_ci_timer_GND_1889), + .LO(plm_fsm_ci_timer_reg_count_cry[10]), + .S(plm_fsm_ci_timer_reg_count_qxu[10]) + ); + XORCY plm_fsm_ci_timer_reg_count_s_10_ ( + .CI(plm_fsm_ci_timer_reg_count_cry[9]), + .LI(plm_fsm_ci_timer_reg_count_qxu[10]), + .O(plm_fsm_ci_timer_reg_count_s[10]) + ); + MUXCY_L plm_fsm_ci_timer_reg_count_cry_11_ ( + .CI(plm_fsm_ci_timer_reg_count_cry[10]), + .DI(plm_fsm_ci_timer_GND_1889), + .LO(plm_fsm_ci_timer_reg_count_cry[11]), + .S(plm_fsm_ci_timer_reg_count_qxu[11]) + ); + XORCY plm_fsm_ci_timer_reg_count_s_11_ ( + .CI(plm_fsm_ci_timer_reg_count_cry[10]), + .LI(plm_fsm_ci_timer_reg_count_qxu[11]), + .O(plm_fsm_ci_timer_reg_count_s[11]) + ); + MUXCY_L plm_fsm_ci_timer_reg_count_cry_12_ ( + .CI(plm_fsm_ci_timer_reg_count_cry[11]), + .DI(plm_fsm_ci_timer_GND_1889), + .LO(plm_fsm_ci_timer_reg_count_cry[12]), + .S(plm_fsm_ci_timer_reg_count_qxu[12]) + ); + XORCY plm_fsm_ci_timer_reg_count_s_12_ ( + .CI(plm_fsm_ci_timer_reg_count_cry[11]), + .LI(plm_fsm_ci_timer_reg_count_qxu[12]), + .O(plm_fsm_ci_timer_reg_count_s[12]) + ); + MUXCY_L plm_fsm_ci_timer_reg_count_cry_13_ ( + .CI(plm_fsm_ci_timer_reg_count_cry[12]), + .DI(plm_fsm_ci_timer_GND_1889), + .LO(plm_fsm_ci_timer_reg_count_cry[13]), + .S(plm_fsm_ci_timer_reg_count_qxu[13]) + ); + XORCY plm_fsm_ci_timer_reg_count_s_13_ ( + .CI(plm_fsm_ci_timer_reg_count_cry[12]), + .LI(plm_fsm_ci_timer_reg_count_qxu[13]), + .O(plm_fsm_ci_timer_reg_count_s[13]) + ); + MUXCY_L plm_fsm_ci_timer_reg_count_cry_14_ ( + .CI(plm_fsm_ci_timer_reg_count_cry[13]), + .DI(plm_fsm_ci_timer_GND_1889), + .LO(plm_fsm_ci_timer_reg_count_cry[14]), + .S(plm_fsm_ci_timer_reg_count_qxu[14]) + ); + XORCY plm_fsm_ci_timer_reg_count_s_14_ ( + .CI(plm_fsm_ci_timer_reg_count_cry[13]), + .LI(plm_fsm_ci_timer_reg_count_qxu[14]), + .O(plm_fsm_ci_timer_reg_count_s[14]) + ); + MUXCY_L plm_fsm_ci_timer_reg_count_cry_15_ ( + .CI(plm_fsm_ci_timer_reg_count_cry[14]), + .DI(plm_fsm_ci_timer_GND_1889), + .LO(plm_fsm_ci_timer_reg_count_cry[15]), + .S(plm_fsm_ci_timer_reg_count_qxu[15]) + ); + XORCY plm_fsm_ci_timer_reg_count_s_15_ ( + .CI(plm_fsm_ci_timer_reg_count_cry[14]), + .LI(plm_fsm_ci_timer_reg_count_qxu[15]), + .O(plm_fsm_ci_timer_reg_count_s[15]) + ); + MUXCY_L plm_fsm_ci_timer_reg_count_cry_16_ ( + .CI(plm_fsm_ci_timer_reg_count_cry[15]), + .DI(plm_fsm_ci_timer_GND_1889), + .LO(plm_fsm_ci_timer_reg_count_cry[16]), + .S(plm_fsm_ci_timer_reg_count_qxu[16]) + ); + XORCY plm_fsm_ci_timer_reg_count_s_16_ ( + .CI(plm_fsm_ci_timer_reg_count_cry[15]), + .LI(plm_fsm_ci_timer_reg_count_qxu[16]), + .O(plm_fsm_ci_timer_reg_count_s[16]) + ); + MUXCY_L plm_fsm_ci_timer_reg_count_cry_17_ ( + .CI(plm_fsm_ci_timer_reg_count_cry[16]), + .DI(plm_fsm_ci_timer_GND_1889), + .LO(plm_fsm_ci_timer_reg_count_cry[17]), + .S(plm_fsm_ci_timer_reg_count_qxu[17]) + ); + XORCY plm_fsm_ci_timer_reg_count_s_17_ ( + .CI(plm_fsm_ci_timer_reg_count_cry[16]), + .LI(plm_fsm_ci_timer_reg_count_qxu[17]), + .O(plm_fsm_ci_timer_reg_count_s[17]) + ); + MUXCY_L plm_fsm_ci_timer_reg_count_cry_18_ ( + .CI(plm_fsm_ci_timer_reg_count_cry[17]), + .DI(plm_fsm_ci_timer_GND_1889), + .LO(plm_fsm_ci_timer_reg_count_cry[18]), + .S(plm_fsm_ci_timer_reg_count_qxu[18]) + ); + XORCY plm_fsm_ci_timer_reg_count_s_18_ ( + .CI(plm_fsm_ci_timer_reg_count_cry[17]), + .LI(plm_fsm_ci_timer_reg_count_qxu[18]), + .O(plm_fsm_ci_timer_reg_count_s[18]) + ); + MUXCY_L plm_fsm_ci_timer_reg_count_cry_19_ ( + .CI(plm_fsm_ci_timer_reg_count_cry[18]), + .DI(plm_fsm_ci_timer_GND_1889), + .LO(plm_fsm_ci_timer_reg_count_cry[19]), + .S(plm_fsm_ci_timer_reg_count_qxu[19]) + ); + XORCY plm_fsm_ci_timer_reg_count_s_19_ ( + .CI(plm_fsm_ci_timer_reg_count_cry[18]), + .LI(plm_fsm_ci_timer_reg_count_qxu[19]), + .O(plm_fsm_ci_timer_reg_count_s[19]) + ); + MUXCY_L plm_fsm_ci_timer_reg_count_cry_20_ ( + .CI(plm_fsm_ci_timer_reg_count_cry[19]), + .DI(plm_fsm_ci_timer_GND_1889), + .LO(plm_fsm_ci_timer_reg_count_cry[20]), + .S(plm_fsm_ci_timer_reg_count_qxu[20]) + ); + XORCY plm_fsm_ci_timer_reg_count_s_20_ ( + .CI(plm_fsm_ci_timer_reg_count_cry[19]), + .LI(plm_fsm_ci_timer_reg_count_qxu[20]), + .O(plm_fsm_ci_timer_reg_count_s[20]) + ); + MUXCY_L plm_fsm_ci_timer_reg_count_cry_21_ ( + .CI(plm_fsm_ci_timer_reg_count_cry[20]), + .DI(plm_fsm_ci_timer_GND_1889), + .LO(plm_fsm_ci_timer_reg_count_cry[21]), + .S(plm_fsm_ci_timer_reg_count_qxu[21]) + ); + XORCY plm_fsm_ci_timer_reg_count_s_21_ ( + .CI(plm_fsm_ci_timer_reg_count_cry[20]), + .LI(plm_fsm_ci_timer_reg_count_qxu[21]), + .O(plm_fsm_ci_timer_reg_count_s[21]) + ); + XORCY plm_fsm_ci_timer_reg_count_s_22_ ( + .CI(plm_fsm_ci_timer_reg_count_cry[21]), + .LI(plm_fsm_ci_timer_reg_count_qxu[22]), + .O(plm_fsm_ci_timer_reg_count_s[22]) + ); + defparam plm_fsm_ci_timer_count_i_m3_i_m3_i_m3_i_m3_0_18_.INIT = 8'hD8; + LUT3 plm_fsm_ci_timer_count_i_m3_i_m3_i_m3_i_m3_0_18_ ( + .I0(cfg_cfg_6102[507]), + .I1(plm_fsm_ci_timer_reg_count[10]), + .I2(plm_fsm_ci_timer_reg_count[18]), + .O(plm_fsm_ci_timer_N_63735) + ); + defparam plm_fsm_ci_timer_count_i_m3_i_m3_i_m3_i_m3_0_19_.INIT = 8'hD8; + LUT3_L plm_fsm_ci_timer_count_i_m3_i_m3_i_m3_i_m3_0_19_ ( + .I0(cfg_cfg_6102[507]), + .I1(plm_fsm_ci_timer_reg_count[11]), + .I2(plm_fsm_ci_timer_reg_count[19]), + .LO(plm_fsm_ci_timer_N_63736) + ); + defparam plm_fsm_ci_timer_count_i_m3_i_m3_i_m3_i_m3_0_20_.INIT = 8'hD8; + LUT3_L plm_fsm_ci_timer_count_i_m3_i_m3_i_m3_i_m3_0_20_ ( + .I0(cfg_cfg_6102[507]), + .I1(plm_fsm_ci_timer_reg_count[12]), + .I2(plm_fsm_ci_timer_reg_count[20]), + .LO(plm_fsm_ci_timer_N_63737) + ); + defparam plm_fsm_ci_timer_un1_expired_2ms_0.INIT = 16'h0415; + LUT4 plm_fsm_ci_timer_un1_expired_2ms_0 ( + .I0(plm_fsm_ci_timer_N_63736), + .I1(cfg_cfg_6102[507]), + .I2(plm_fsm_ci_timer_reg_count[14]), + .I3(plm_fsm_ci_timer_reg_count[22]), + .O(plm_fsm_ci_timer_un1_expired_2ms_0_1891) + ); + defparam plm_fsm_ci_timer_un1_expired_2ms_1.INIT = 16'h0415; + LUT4 plm_fsm_ci_timer_un1_expired_2ms_1 ( + .I0(plm_fsm_ci_timer_N_63737), + .I1(cfg_cfg_6102[507]), + .I2(plm_fsm_ci_timer_reg_count[13]), + .I3(plm_fsm_ci_timer_reg_count[21]), + .O(plm_fsm_ci_timer_un1_expired_2ms_1_1890) + ); + defparam plm_fsm_ci_timer_expired.INIT = 16'hBF00; + LUT4 plm_fsm_ci_timer_expired ( + .I0(plm_fsm_ci_timer_N_63735), + .I1(plm_fsm_ci_timer_un1_expired_2ms_0_1891), + .I2(plm_fsm_ci_timer_un1_expired_2ms_1_1890), + .I3(plm_fsm_reg_state_11__608), + .O(plm_fsm_ci_timeout) + ); + FDC plm_fsm_ci_timer_reg_count_22_ ( + .C(mgt_clk), + .D(plm_fsm_ci_timer_reg_count_s[22]), + .Q(plm_fsm_ci_timer_reg_count[22]), + .CLR(plm_rst) + ); + FDC plm_fsm_ci_timer_reg_count_21_ ( + .C(mgt_clk), + .D(plm_fsm_ci_timer_reg_count_s[21]), + .Q(plm_fsm_ci_timer_reg_count[21]), + .CLR(plm_rst) + ); + FDC plm_fsm_ci_timer_reg_count_20_ ( + .C(mgt_clk), + .D(plm_fsm_ci_timer_reg_count_s[20]), + .Q(plm_fsm_ci_timer_reg_count[20]), + .CLR(plm_rst) + ); + FDC plm_fsm_ci_timer_reg_count_19_ ( + .C(mgt_clk), + .D(plm_fsm_ci_timer_reg_count_s[19]), + .Q(plm_fsm_ci_timer_reg_count[19]), + .CLR(plm_rst) + ); + FDC plm_fsm_ci_timer_reg_count_18_ ( + .C(mgt_clk), + .D(plm_fsm_ci_timer_reg_count_s[18]), + .Q(plm_fsm_ci_timer_reg_count[18]), + .CLR(plm_rst) + ); + FDC plm_fsm_ci_timer_reg_count_17_ ( + .C(mgt_clk), + .D(plm_fsm_ci_timer_reg_count_s[17]), + .Q(plm_fsm_ci_timer_reg_count[17]), + .CLR(plm_rst) + ); + FDC plm_fsm_ci_timer_reg_count_16_ ( + .C(mgt_clk), + .D(plm_fsm_ci_timer_reg_count_s[16]), + .Q(plm_fsm_ci_timer_reg_count[16]), + .CLR(plm_rst) + ); + FDC plm_fsm_ci_timer_reg_count_15_ ( + .C(mgt_clk), + .D(plm_fsm_ci_timer_reg_count_s[15]), + .Q(plm_fsm_ci_timer_reg_count[15]), + .CLR(plm_rst) + ); + FDC plm_fsm_ci_timer_reg_count_14_ ( + .C(mgt_clk), + .D(plm_fsm_ci_timer_reg_count_s[14]), + .Q(plm_fsm_ci_timer_reg_count[14]), + .CLR(plm_rst) + ); + FDC plm_fsm_ci_timer_reg_count_13_ ( + .C(mgt_clk), + .D(plm_fsm_ci_timer_reg_count_s[13]), + .Q(plm_fsm_ci_timer_reg_count[13]), + .CLR(plm_rst) + ); + FDC plm_fsm_ci_timer_reg_count_12_ ( + .C(mgt_clk), + .D(plm_fsm_ci_timer_reg_count_s[12]), + .Q(plm_fsm_ci_timer_reg_count[12]), + .CLR(plm_rst) + ); + FDC plm_fsm_ci_timer_reg_count_11_ ( + .C(mgt_clk), + .D(plm_fsm_ci_timer_reg_count_s[11]), + .Q(plm_fsm_ci_timer_reg_count[11]), + .CLR(plm_rst) + ); + FDC plm_fsm_ci_timer_reg_count_10_ ( + .C(mgt_clk), + .D(plm_fsm_ci_timer_reg_count_s[10]), + .Q(plm_fsm_ci_timer_reg_count[10]), + .CLR(plm_rst) + ); + FDC plm_fsm_ci_timer_reg_count_9_ ( + .C(mgt_clk), + .D(plm_fsm_ci_timer_reg_count_s[9]), + .Q(plm_fsm_ci_timer_reg_count[9]), + .CLR(plm_rst) + ); + FDC plm_fsm_ci_timer_reg_count_8_ ( + .C(mgt_clk), + .D(plm_fsm_ci_timer_reg_count_s[8]), + .Q(plm_fsm_ci_timer_reg_count[8]), + .CLR(plm_rst) + ); + FDC plm_fsm_ci_timer_reg_count_7_ ( + .C(mgt_clk), + .D(plm_fsm_ci_timer_reg_count_s[7]), + .Q(plm_fsm_ci_timer_reg_count[7]), + .CLR(plm_rst) + ); + FDC plm_fsm_ci_timer_reg_count_6_ ( + .C(mgt_clk), + .D(plm_fsm_ci_timer_reg_count_s[6]), + .Q(plm_fsm_ci_timer_reg_count[6]), + .CLR(plm_rst) + ); + FDC plm_fsm_ci_timer_reg_count_5_ ( + .C(mgt_clk), + .D(plm_fsm_ci_timer_reg_count_s[5]), + .Q(plm_fsm_ci_timer_reg_count[5]), + .CLR(plm_rst) + ); + FDC plm_fsm_ci_timer_reg_count_4_ ( + .C(mgt_clk), + .D(plm_fsm_ci_timer_reg_count_s[4]), + .Q(plm_fsm_ci_timer_reg_count[4]), + .CLR(plm_rst) + ); + FDC plm_fsm_ci_timer_reg_count_3_ ( + .C(mgt_clk), + .D(plm_fsm_ci_timer_reg_count_s[3]), + .Q(plm_fsm_ci_timer_reg_count[3]), + .CLR(plm_rst) + ); + FDC plm_fsm_ci_timer_reg_count_2_ ( + .C(mgt_clk), + .D(plm_fsm_ci_timer_reg_count_s[2]), + .Q(plm_fsm_ci_timer_reg_count[2]), + .CLR(plm_rst) + ); + FDC plm_fsm_ci_timer_reg_count_1_ ( + .C(mgt_clk), + .D(plm_fsm_ci_timer_reg_count_s[1]), + .Q(plm_fsm_ci_timer_reg_count[1]), + .CLR(plm_rst) + ); + FDC plm_fsm_ci_timer_reg_count_0_ ( + .C(mgt_clk), + .D(plm_fsm_ci_timer_reg_count_s[0]), + .Q(plm_fsm_ci_timer_reg_count[0]), + .CLR(plm_rst) + ); + defparam plm_fsm_ci_timer_reg_count_qxu_0_0_.INIT = 4'h8; + LUT2_L plm_fsm_ci_timer_reg_count_qxu_0_0_ ( + .I0(plm_fsm_ci_timer_reg_count[0]), + .I1(plm_fsm_reg_state_11__608), + .LO(plm_fsm_ci_timer_reg_count_qxu[0]) + ); + defparam plm_fsm_ci_timer_reg_count_qxu_0_1_.INIT = 4'h8; + LUT2_L plm_fsm_ci_timer_reg_count_qxu_0_1_ ( + .I0(plm_fsm_ci_timer_reg_count[1]), + .I1(plm_fsm_reg_state_11__608), + .LO(plm_fsm_ci_timer_reg_count_qxu[1]) + ); + defparam plm_fsm_ci_timer_reg_count_qxu_0_2_.INIT = 4'h8; + LUT2_L plm_fsm_ci_timer_reg_count_qxu_0_2_ ( + .I0(plm_fsm_ci_timer_reg_count[2]), + .I1(plm_fsm_reg_state_11__608), + .LO(plm_fsm_ci_timer_reg_count_qxu[2]) + ); + defparam plm_fsm_ci_timer_reg_count_qxu_0_3_.INIT = 4'h8; + LUT2_L plm_fsm_ci_timer_reg_count_qxu_0_3_ ( + .I0(plm_fsm_ci_timer_reg_count[3]), + .I1(plm_fsm_reg_state_11__608), + .LO(plm_fsm_ci_timer_reg_count_qxu[3]) + ); + defparam plm_fsm_ci_timer_reg_count_qxu_0_4_.INIT = 4'h8; + LUT2_L plm_fsm_ci_timer_reg_count_qxu_0_4_ ( + .I0(plm_fsm_ci_timer_reg_count[4]), + .I1(plm_fsm_reg_state_11__608), + .LO(plm_fsm_ci_timer_reg_count_qxu[4]) + ); + defparam plm_fsm_ci_timer_reg_count_qxu_0_5_.INIT = 4'h8; + LUT2_L plm_fsm_ci_timer_reg_count_qxu_0_5_ ( + .I0(plm_fsm_ci_timer_reg_count[5]), + .I1(plm_fsm_reg_state_11__608), + .LO(plm_fsm_ci_timer_reg_count_qxu[5]) + ); + defparam plm_fsm_ci_timer_reg_count_qxu_0_6_.INIT = 4'h8; + LUT2_L plm_fsm_ci_timer_reg_count_qxu_0_6_ ( + .I0(plm_fsm_ci_timer_reg_count[6]), + .I1(plm_fsm_reg_state_11__608), + .LO(plm_fsm_ci_timer_reg_count_qxu[6]) + ); + defparam plm_fsm_ci_timer_reg_count_qxu_0_7_.INIT = 4'h8; + LUT2_L plm_fsm_ci_timer_reg_count_qxu_0_7_ ( + .I0(plm_fsm_ci_timer_reg_count[7]), + .I1(plm_fsm_reg_state_11__608), + .LO(plm_fsm_ci_timer_reg_count_qxu[7]) + ); + defparam plm_fsm_ci_timer_reg_count_qxu_0_8_.INIT = 4'h8; + LUT2_L plm_fsm_ci_timer_reg_count_qxu_0_8_ ( + .I0(plm_fsm_ci_timer_reg_count[8]), + .I1(plm_fsm_reg_state_11__608), + .LO(plm_fsm_ci_timer_reg_count_qxu[8]) + ); + defparam plm_fsm_ci_timer_reg_count_qxu_0_9_.INIT = 4'h8; + LUT2_L plm_fsm_ci_timer_reg_count_qxu_0_9_ ( + .I0(plm_fsm_ci_timer_reg_count[9]), + .I1(plm_fsm_reg_state_11__608), + .LO(plm_fsm_ci_timer_reg_count_qxu[9]) + ); + defparam plm_fsm_ci_timer_reg_count_qxu_0_10_.INIT = 4'h8; + LUT2_L plm_fsm_ci_timer_reg_count_qxu_0_10_ ( + .I0(plm_fsm_ci_timer_reg_count[10]), + .I1(plm_fsm_reg_state_11__608), + .LO(plm_fsm_ci_timer_reg_count_qxu[10]) + ); + defparam plm_fsm_ci_timer_reg_count_qxu_0_11_.INIT = 4'h8; + LUT2_L plm_fsm_ci_timer_reg_count_qxu_0_11_ ( + .I0(plm_fsm_ci_timer_reg_count[11]), + .I1(plm_fsm_reg_state_11__608), + .LO(plm_fsm_ci_timer_reg_count_qxu[11]) + ); + defparam plm_fsm_ci_timer_reg_count_qxu_0_12_.INIT = 4'h8; + LUT2_L plm_fsm_ci_timer_reg_count_qxu_0_12_ ( + .I0(plm_fsm_ci_timer_reg_count[12]), + .I1(plm_fsm_reg_state_11__608), + .LO(plm_fsm_ci_timer_reg_count_qxu[12]) + ); + defparam plm_fsm_ci_timer_reg_count_qxu_0_13_.INIT = 4'h8; + LUT2_L plm_fsm_ci_timer_reg_count_qxu_0_13_ ( + .I0(plm_fsm_ci_timer_reg_count[13]), + .I1(plm_fsm_reg_state_11__608), + .LO(plm_fsm_ci_timer_reg_count_qxu[13]) + ); + defparam plm_fsm_ci_timer_reg_count_qxu_0_14_.INIT = 4'h8; + LUT2_L plm_fsm_ci_timer_reg_count_qxu_0_14_ ( + .I0(plm_fsm_ci_timer_reg_count[14]), + .I1(plm_fsm_reg_state_11__608), + .LO(plm_fsm_ci_timer_reg_count_qxu[14]) + ); + defparam plm_fsm_ci_timer_reg_count_qxu_0_15_.INIT = 4'h8; + LUT2_L plm_fsm_ci_timer_reg_count_qxu_0_15_ ( + .I0(plm_fsm_ci_timer_reg_count[15]), + .I1(plm_fsm_reg_state_11__608), + .LO(plm_fsm_ci_timer_reg_count_qxu[15]) + ); + defparam plm_fsm_ci_timer_reg_count_qxu_0_16_.INIT = 4'h8; + LUT2_L plm_fsm_ci_timer_reg_count_qxu_0_16_ ( + .I0(plm_fsm_ci_timer_reg_count[16]), + .I1(plm_fsm_reg_state_11__608), + .LO(plm_fsm_ci_timer_reg_count_qxu[16]) + ); + defparam plm_fsm_ci_timer_reg_count_qxu_0_17_.INIT = 4'h8; + LUT2_L plm_fsm_ci_timer_reg_count_qxu_0_17_ ( + .I0(plm_fsm_ci_timer_reg_count[17]), + .I1(plm_fsm_reg_state_11__608), + .LO(plm_fsm_ci_timer_reg_count_qxu[17]) + ); + defparam plm_fsm_ci_timer_reg_count_qxu_0_18_.INIT = 4'h8; + LUT2_L plm_fsm_ci_timer_reg_count_qxu_0_18_ ( + .I0(plm_fsm_ci_timer_reg_count[18]), + .I1(plm_fsm_reg_state_11__608), + .LO(plm_fsm_ci_timer_reg_count_qxu[18]) + ); + defparam plm_fsm_ci_timer_reg_count_qxu_0_19_.INIT = 4'h8; + LUT2_L plm_fsm_ci_timer_reg_count_qxu_0_19_ ( + .I0(plm_fsm_ci_timer_reg_count[19]), + .I1(plm_fsm_reg_state_11__608), + .LO(plm_fsm_ci_timer_reg_count_qxu[19]) + ); + defparam plm_fsm_ci_timer_reg_count_qxu_0_20_.INIT = 4'h8; + LUT2_L plm_fsm_ci_timer_reg_count_qxu_0_20_ ( + .I0(plm_fsm_ci_timer_reg_count[20]), + .I1(plm_fsm_reg_state_11__608), + .LO(plm_fsm_ci_timer_reg_count_qxu[20]) + ); + defparam plm_fsm_ci_timer_reg_count_qxu_0_21_.INIT = 4'h8; + LUT2_L plm_fsm_ci_timer_reg_count_qxu_0_21_ ( + .I0(plm_fsm_ci_timer_reg_count[21]), + .I1(plm_fsm_reg_state_11__608), + .LO(plm_fsm_ci_timer_reg_count_qxu[21]) + ); + defparam plm_fsm_ci_timer_reg_count_qxu_0_22_.INIT = 4'h8; + LUT2_L plm_fsm_ci_timer_reg_count_qxu_0_22_ ( + .I0(plm_fsm_ci_timer_reg_count[22]), + .I1(plm_fsm_reg_state_11__608), + .LO(plm_fsm_ci_timer_reg_count_qxu[22]) + ); + VCC plm_fsm_ci_counter0_VCC ( + .P(plm_fsm_ci_counter0_VCC_1892) + ); + MUXCY_L plm_fsm_ci_counter0_reg_rx_count_cry_0_ ( + .CI(N_61091_i_39), + .DI(plm_fsm_ci_counter0_VCC_1892), + .LO(plm_fsm_ci_counter0_reg_rx_count_cry[0]), + .S(plm_fsm_ci_counter0_reg_rx_count_qxu[0]) + ); + XORCY plm_fsm_ci_counter0_reg_rx_count_s_0_ ( + .CI(N_61091_i_39), + .LI(plm_fsm_ci_counter0_reg_rx_count_qxu[0]), + .O(plm_fsm_ci_counter0_reg_rx_count_s[0]) + ); + MUXCY_L plm_fsm_ci_counter0_reg_rx_count_cry_1_ ( + .CI(plm_fsm_ci_counter0_reg_rx_count_cry[0]), + .DI(plm_fsm_ci_counter0_VCC_1892), + .LO(plm_fsm_ci_counter0_reg_rx_count_cry[1]), + .S(plm_fsm_ci_counter0_reg_rx_count_qxu[1]) + ); + XORCY plm_fsm_ci_counter0_reg_rx_count_s_1_ ( + .CI(plm_fsm_ci_counter0_reg_rx_count_cry[0]), + .LI(plm_fsm_ci_counter0_reg_rx_count_qxu[1]), + .O(plm_fsm_ci_counter0_reg_rx_count_s[1]) + ); + MUXCY_L plm_fsm_ci_counter0_reg_rx_count_cry_2_ ( + .CI(plm_fsm_ci_counter0_reg_rx_count_cry[1]), + .DI(plm_fsm_ci_counter0_VCC_1892), + .LO(plm_fsm_ci_counter0_reg_rx_count_cry[2]), + .S(plm_fsm_ci_counter0_reg_rx_count_qxu[2]) + ); + XORCY plm_fsm_ci_counter0_reg_rx_count_s_2_ ( + .CI(plm_fsm_ci_counter0_reg_rx_count_cry[1]), + .LI(plm_fsm_ci_counter0_reg_rx_count_qxu[2]), + .O(plm_fsm_ci_counter0_reg_rx_count_s[2]) + ); + MUXCY_L plm_fsm_ci_counter0_reg_rx_count_cry_3_ ( + .CI(plm_fsm_ci_counter0_reg_rx_count_cry[2]), + .DI(plm_fsm_ci_counter0_VCC_1892), + .LO(plm_fsm_ci_counter0_reg_rx_count_cry[3]), + .S(plm_fsm_ci_counter0_reg_rx_count_qxu[3]) + ); + XORCY plm_fsm_ci_counter0_reg_rx_count_s_3_ ( + .CI(plm_fsm_ci_counter0_reg_rx_count_cry[2]), + .LI(plm_fsm_ci_counter0_reg_rx_count_qxu[3]), + .O(plm_fsm_ci_counter0_reg_rx_count_s[3]) + ); + MUXCY_L plm_fsm_ci_counter0_reg_rx_count_cry_4_ ( + .CI(plm_fsm_ci_counter0_reg_rx_count_cry[3]), + .DI(plm_fsm_ci_counter0_VCC_1892), + .LO(plm_fsm_ci_counter0_reg_rx_count_cry[4]), + .S(plm_fsm_ci_counter0_reg_rx_count_qxu[4]) + ); + XORCY plm_fsm_ci_counter0_reg_rx_count_s_4_ ( + .CI(plm_fsm_ci_counter0_reg_rx_count_cry[3]), + .LI(plm_fsm_ci_counter0_reg_rx_count_qxu[4]), + .O(plm_fsm_ci_counter0_reg_rx_count_s[4]) + ); + MUXCY_L plm_fsm_ci_counter0_reg_rx_count_cry_5_ ( + .CI(plm_fsm_ci_counter0_reg_rx_count_cry[4]), + .DI(plm_fsm_ci_counter0_VCC_1892), + .LO(plm_fsm_ci_counter0_reg_rx_count_cry[5]), + .S(plm_fsm_ci_counter0_reg_rx_count_qxu[5]) + ); + XORCY plm_fsm_ci_counter0_reg_rx_count_s_5_ ( + .CI(plm_fsm_ci_counter0_reg_rx_count_cry[4]), + .LI(plm_fsm_ci_counter0_reg_rx_count_qxu[5]), + .O(plm_fsm_ci_counter0_reg_rx_count_s[5]) + ); + MUXCY_L plm_fsm_ci_counter0_reg_rx_count_cry_6_ ( + .CI(plm_fsm_ci_counter0_reg_rx_count_cry[5]), + .DI(plm_fsm_ci_counter0_VCC_1892), + .LO(plm_fsm_ci_counter0_reg_rx_count_cry[6]), + .S(plm_fsm_ci_counter0_reg_rx_count_qxu[6]) + ); + XORCY plm_fsm_ci_counter0_reg_rx_count_s_6_ ( + .CI(plm_fsm_ci_counter0_reg_rx_count_cry[5]), + .LI(plm_fsm_ci_counter0_reg_rx_count_qxu[6]), + .O(plm_fsm_ci_counter0_reg_rx_count_s[6]) + ); + XORCY plm_fsm_ci_counter0_reg_rx_count_s_7_ ( + .CI(plm_fsm_ci_counter0_reg_rx_count_cry[6]), + .LI(plm_fsm_ci_counter0_reg_rx_count_qxu[7]), + .O(plm_fsm_ci_counter0_reg_rx_count_s[7]) + ); + MUXCY_L plm_fsm_ci_counter0_reg_tx_count_cry_0_ ( + .CI(plm_fsm_ci_counter0_N_61223_i_1897), + .DI(plm_fsm_ci_counter0_VCC_1892), + .LO(plm_fsm_ci_counter0_reg_tx_count_cry[0]), + .S(plm_fsm_ci_counter0_reg_tx_count_qxu[0]) + ); + XORCY plm_fsm_ci_counter0_reg_tx_count_s_0_ ( + .CI(plm_fsm_ci_counter0_N_61223_i_1897), + .LI(plm_fsm_ci_counter0_reg_tx_count_qxu[0]), + .O(plm_fsm_ci_counter0_reg_tx_count_s[0]) + ); + MUXCY_L plm_fsm_ci_counter0_reg_tx_count_cry_1_ ( + .CI(plm_fsm_ci_counter0_reg_tx_count_cry[0]), + .DI(plm_fsm_ci_counter0_VCC_1892), + .LO(plm_fsm_ci_counter0_reg_tx_count_cry[1]), + .S(plm_fsm_ci_counter0_reg_tx_count_qxu[1]) + ); + XORCY plm_fsm_ci_counter0_reg_tx_count_s_1_ ( + .CI(plm_fsm_ci_counter0_reg_tx_count_cry[0]), + .LI(plm_fsm_ci_counter0_reg_tx_count_qxu[1]), + .O(plm_fsm_ci_counter0_reg_tx_count_s[1]) + ); + MUXCY_L plm_fsm_ci_counter0_reg_tx_count_cry_2_ ( + .CI(plm_fsm_ci_counter0_reg_tx_count_cry[1]), + .DI(plm_fsm_ci_counter0_VCC_1892), + .LO(plm_fsm_ci_counter0_reg_tx_count_cry[2]), + .S(plm_fsm_ci_counter0_reg_tx_count_qxu[2]) + ); + XORCY plm_fsm_ci_counter0_reg_tx_count_s_2_ ( + .CI(plm_fsm_ci_counter0_reg_tx_count_cry[1]), + .LI(plm_fsm_ci_counter0_reg_tx_count_qxu[2]), + .O(plm_fsm_ci_counter0_reg_tx_count_s[2]) + ); + MUXCY_L plm_fsm_ci_counter0_reg_tx_count_cry_3_ ( + .CI(plm_fsm_ci_counter0_reg_tx_count_cry[2]), + .DI(plm_fsm_ci_counter0_VCC_1892), + .LO(plm_fsm_ci_counter0_reg_tx_count_cry[3]), + .S(plm_fsm_ci_counter0_reg_tx_count_qxu[3]) + ); + XORCY plm_fsm_ci_counter0_reg_tx_count_s_3_ ( + .CI(plm_fsm_ci_counter0_reg_tx_count_cry[2]), + .LI(plm_fsm_ci_counter0_reg_tx_count_qxu[3]), + .O(plm_fsm_ci_counter0_reg_tx_count_s[3]) + ); + MUXCY_L plm_fsm_ci_counter0_reg_tx_count_cry_4_ ( + .CI(plm_fsm_ci_counter0_reg_tx_count_cry[3]), + .DI(plm_fsm_ci_counter0_VCC_1892), + .LO(plm_fsm_ci_counter0_reg_tx_count_cry[4]), + .S(plm_fsm_ci_counter0_reg_tx_count_qxu[4]) + ); + XORCY plm_fsm_ci_counter0_reg_tx_count_s_4_ ( + .CI(plm_fsm_ci_counter0_reg_tx_count_cry[3]), + .LI(plm_fsm_ci_counter0_reg_tx_count_qxu[4]), + .O(plm_fsm_ci_counter0_reg_tx_count_s[4]) + ); + MUXCY_L plm_fsm_ci_counter0_reg_tx_count_cry_5_ ( + .CI(plm_fsm_ci_counter0_reg_tx_count_cry[4]), + .DI(plm_fsm_ci_counter0_VCC_1892), + .LO(plm_fsm_ci_counter0_reg_tx_count_cry[5]), + .S(plm_fsm_ci_counter0_reg_tx_count_qxu[5]) + ); + XORCY plm_fsm_ci_counter0_reg_tx_count_s_5_ ( + .CI(plm_fsm_ci_counter0_reg_tx_count_cry[4]), + .LI(plm_fsm_ci_counter0_reg_tx_count_qxu[5]), + .O(plm_fsm_ci_counter0_reg_tx_count_s[5]) + ); + MUXCY_L plm_fsm_ci_counter0_reg_tx_count_cry_6_ ( + .CI(plm_fsm_ci_counter0_reg_tx_count_cry[5]), + .DI(plm_fsm_ci_counter0_VCC_1892), + .LO(plm_fsm_ci_counter0_reg_tx_count_cry[6]), + .S(plm_fsm_ci_counter0_reg_tx_count_qxu[6]) + ); + XORCY plm_fsm_ci_counter0_reg_tx_count_s_6_ ( + .CI(plm_fsm_ci_counter0_reg_tx_count_cry[5]), + .LI(plm_fsm_ci_counter0_reg_tx_count_qxu[6]), + .O(plm_fsm_ci_counter0_reg_tx_count_s[6]) + ); + XORCY plm_fsm_ci_counter0_reg_tx_count_s_7_ ( + .CI(plm_fsm_ci_counter0_reg_tx_count_cry[6]), + .LI(plm_fsm_ci_counter0_reg_tx_count_qxu[7]), + .O(plm_fsm_ci_counter0_reg_tx_count_s[7]) + ); + defparam plm_fsm_ci_counter0_un1_enable_4_i_0_0_0_a2_1.INIT = 4'h2; + LUT2 plm_fsm_ci_counter0_un1_enable_4_i_0_0_0_a2_1 ( + .I0(plm_reg_rx_idl_1), + .I1(plm_rx0_idl_c), + .O(plm_fsm_N_58718_1) + ); + defparam plm_fsm_ci_counter0_loadable_tx_counter_reg_tx_count17_0_a2_0_a2_0_a3_0_a2.INIT = 4'h8; + LUT2 plm_fsm_ci_counter0_loadable_tx_counter_reg_tx_count17_0_a2_0_a2_0_a3_0_a2 ( + .I0(plm_fsm_ci_counter0_reg_oneshot_1894), + .I1(plm_fsm_reg_state_11__608), + .O(plm_fsm_ci_counter0_reg_tx_count17_0_a2_0_a2_0_a3_0_a2_0) + ); + defparam plm_fsm_ci_counter0_oneshot_monitor_N_61219_i.INIT = 4'hB; + LUT2 plm_fsm_ci_counter0_oneshot_monitor_N_61219_i ( + .I0(plm_reg_rx_idl_1), + .I1(plm_fsm_reg_state_11__608), + .O(plm_fsm_ci_counter0_N_61219_i) + ); + defparam plm_fsm_ci_counter0_loadable_rx_counter_un1_reg_rx_count_0_a2_4.INIT = 16'h0001; + LUT4 plm_fsm_ci_counter0_loadable_rx_counter_un1_reg_rx_count_0_a2_4 ( + .I0(plm_fsm_ci_counter0_reg_rx_count[0]), + .I1(plm_fsm_ci_counter0_reg_rx_count[1]), + .I2(plm_fsm_ci_counter0_reg_rx_count[2]), + .I3(plm_fsm_ci_counter0_reg_rx_count[3]), + .O(plm_fsm_ci_counter0_un1_reg_rx_count_0_a2_4) + ); + defparam plm_fsm_ci_counter0_loadable_rx_counter_un1_reg_rx_count_0_a2_5.INIT = 16'h0001; + LUT4 plm_fsm_ci_counter0_loadable_rx_counter_un1_reg_rx_count_0_a2_5 ( + .I0(plm_fsm_ci_counter0_reg_rx_count[4]), + .I1(plm_fsm_ci_counter0_reg_rx_count[5]), + .I2(plm_fsm_ci_counter0_reg_rx_count[6]), + .I3(plm_fsm_ci_counter0_reg_rx_count[7]), + .O(plm_fsm_ci_counter0_un1_reg_rx_count_0_a2_5) + ); + defparam plm_fsm_ci_counter0_loadable_tx_counter_un1_reg_tx_count_0_a2_4.INIT = 16'h0001; + LUT4 plm_fsm_ci_counter0_loadable_tx_counter_un1_reg_tx_count_0_a2_4 ( + .I0(plm_fsm_ci_counter0_reg_tx_count[0]), + .I1(plm_fsm_ci_counter0_reg_tx_count[1]), + .I2(plm_fsm_ci_counter0_reg_tx_count[2]), + .I3(plm_fsm_ci_counter0_reg_tx_count[3]), + .O(plm_fsm_ci_counter0_un1_reg_tx_count_0_a2_4) + ); + defparam plm_fsm_ci_counter0_loadable_tx_counter_un1_reg_tx_count_0_a2_5.INIT = 16'h0001; + LUT4 plm_fsm_ci_counter0_loadable_tx_counter_un1_reg_tx_count_0_a2_5 ( + .I0(plm_fsm_ci_counter0_reg_tx_count[4]), + .I1(plm_fsm_ci_counter0_reg_tx_count[5]), + .I2(plm_fsm_ci_counter0_reg_tx_count[6]), + .I3(plm_fsm_ci_counter0_reg_tx_count[7]), + .O(plm_fsm_ci_counter0_un1_reg_tx_count_0_a2_5) + ); + defparam plm_fsm_ci_counter0_loadable_rx_counter_N_61102_i.INIT = 8'hEF; + LUT3 plm_fsm_ci_counter0_loadable_rx_counter_N_61102_i ( + .I0(plm_reg_rx_idl_1), + .I1(plm_fsm_ci_counter0_reg_rx_expired_612), + .I2(plm_fsm_reg_state_11__608), + .O(plm_fsm_ci_counter0_N_61102_i) + ); + defparam plm_fsm_ci_counter0_N_87181_i.INIT = 8'h2F; + LUT3_L plm_fsm_ci_counter0_N_87181_i ( + .I0(plm_fsm_N_58718_1), + .I1(plm_fsm_ci_counter0_reg_rx_expired_612), + .I2(plm_fsm_reg_state_11__608), + .LO(plm_fsm_ci_counter0_N_87181_i_1898) + ); + defparam plm_fsm_ci_counter0_N_61093_i.INIT = 4'hB; + LUT2 plm_fsm_ci_counter0_N_61093_i ( + .I0(plm_reg_sym_sent_0_), + .I1(plm_fsm_ci_counter0_un1_enable_1_0_a2_0_a2_0_a3_0_a2_5), + .O(plm_fsm_ci_counter0_N_61093_i_1893) + ); + defparam plm_fsm_ci_counter0_N_61064_i.INIT = 8'hD5; + LUT3 plm_fsm_ci_counter0_N_61064_i ( + .I0(plm_fsm_ci_counter0_reg_tx_count17_0_a2_0_a2_0_a3_0_a2_0), + .I1(plm_fsm_ci_counter0_un1_reg_tx_count_0_a2_4), + .I2(plm_fsm_ci_counter0_un1_reg_tx_count_0_a2_5), + .O(plm_fsm_ci_counter0_N_61064_i_1895) + ); + defparam plm_fsm_ci_counter0_loadable_rx_counter_N_61153_i.INIT = 8'h8F; + LUT3 plm_fsm_ci_counter0_loadable_rx_counter_N_61153_i ( + .I0(plm_fsm_ci_counter0_un1_reg_rx_count_0_a2_4), + .I1(plm_fsm_ci_counter0_un1_reg_rx_count_0_a2_5), + .I2(plm_fsm_reg_state_11__608), + .O(plm_fsm_ci_counter0_N_61153_i) + ); + defparam plm_fsm_ci_counter0_flagit_reg_expired_5_0_a2_0_a2_0_a3_0_a2.INIT = 8'h80; + LUT3_L plm_fsm_ci_counter0_flagit_reg_expired_5_0_a2_0_a2_0_a3_0_a2 ( + .I0(plm_fsm_ci_counter0_reg_rx_expired_612), + .I1(plm_fsm_ci_counter0_reg_tx_expired_1896), + .I2(plm_fsm_reg_state_11__608), + .LO(plm_fsm_ci_counter0_reg_expired_5) + ); + defparam plm_fsm_ci_counter0_un1_enable_1_0_a2_0_a2_0_a3_0_a2.INIT = 8'h40; + LUT3 plm_fsm_ci_counter0_un1_enable_1_0_a2_0_a2_0_a3_0_a2 ( + .I0(plm_fsm_ci_counter0_reg_tx_expired_1896), + .I1(plm_fsm_reg_state_11__608), + .I2(plm_fsm_ci_counter0_reg_oneshot_1894), + .O(plm_fsm_ci_counter0_un1_enable_1_0_a2_0_a2_0_a3_0_a2_5) + ); + FDCE plm_fsm_ci_counter0_reg_tx_count_7_ ( + .CE(plm_fsm_ci_counter0_N_61093_i_1893), + .C(mgt_clk), + .D(plm_fsm_ci_counter0_reg_tx_count_s[7]), + .Q(plm_fsm_ci_counter0_reg_tx_count[7]), + .CLR(plm_rst) + ); + FDCE plm_fsm_ci_counter0_reg_tx_count_6_ ( + .CE(plm_fsm_ci_counter0_N_61093_i_1893), + .C(mgt_clk), + .D(plm_fsm_ci_counter0_reg_tx_count_s[6]), + .Q(plm_fsm_ci_counter0_reg_tx_count[6]), + .CLR(plm_rst) + ); + FDCE plm_fsm_ci_counter0_reg_tx_count_5_ ( + .CE(plm_fsm_ci_counter0_N_61093_i_1893), + .C(mgt_clk), + .D(plm_fsm_ci_counter0_reg_tx_count_s[5]), + .Q(plm_fsm_ci_counter0_reg_tx_count[5]), + .CLR(plm_rst) + ); + FDCE plm_fsm_ci_counter0_reg_tx_count_4_ ( + .CE(plm_fsm_ci_counter0_N_61093_i_1893), + .C(mgt_clk), + .D(plm_fsm_ci_counter0_reg_tx_count_s[4]), + .Q(plm_fsm_ci_counter0_reg_tx_count[4]), + .CLR(plm_rst) + ); + FDPE plm_fsm_ci_counter0_reg_tx_count_3_ ( + .PRE(plm_rst), + .CE(plm_fsm_ci_counter0_N_61093_i_1893), + .C(mgt_clk), + .D(plm_fsm_ci_counter0_reg_tx_count_s[3]), + .Q(plm_fsm_ci_counter0_reg_tx_count[3]) + ); + FDCE plm_fsm_ci_counter0_reg_tx_count_2_ ( + .CE(plm_fsm_ci_counter0_N_61093_i_1893), + .C(mgt_clk), + .D(plm_fsm_ci_counter0_reg_tx_count_s[2]), + .Q(plm_fsm_ci_counter0_reg_tx_count[2]), + .CLR(plm_rst) + ); + FDCE plm_fsm_ci_counter0_reg_tx_count_1_ ( + .CE(plm_fsm_ci_counter0_N_61093_i_1893), + .C(mgt_clk), + .D(plm_fsm_ci_counter0_reg_tx_count_s[1]), + .Q(plm_fsm_ci_counter0_reg_tx_count[1]), + .CLR(plm_rst) + ); + FDCE plm_fsm_ci_counter0_reg_tx_count_0_ ( + .CE(plm_fsm_ci_counter0_N_61093_i_1893), + .C(mgt_clk), + .D(plm_fsm_ci_counter0_reg_tx_count_s[0]), + .Q(plm_fsm_ci_counter0_reg_tx_count[0]), + .CLR(plm_rst) + ); + FDCE plm_fsm_ci_counter0_reg_rx_count_7_ ( + .CE(plm_fsm_ci_counter0_N_61102_i), + .C(mgt_clk), + .D(plm_fsm_ci_counter0_reg_rx_count_s[7]), + .Q(plm_fsm_ci_counter0_reg_rx_count[7]), + .CLR(plm_rst) + ); + FDCE plm_fsm_ci_counter0_reg_rx_count_6_ ( + .CE(plm_fsm_ci_counter0_N_61102_i), + .C(mgt_clk), + .D(plm_fsm_ci_counter0_reg_rx_count_s[6]), + .Q(plm_fsm_ci_counter0_reg_rx_count[6]), + .CLR(plm_rst) + ); + FDCE plm_fsm_ci_counter0_reg_rx_count_5_ ( + .CE(plm_fsm_ci_counter0_N_61102_i), + .C(mgt_clk), + .D(plm_fsm_ci_counter0_reg_rx_count_s[5]), + .Q(plm_fsm_ci_counter0_reg_rx_count[5]), + .CLR(plm_rst) + ); + FDCE plm_fsm_ci_counter0_reg_rx_count_4_ ( + .CE(plm_fsm_ci_counter0_N_61102_i), + .C(mgt_clk), + .D(plm_fsm_ci_counter0_reg_rx_count_s[4]), + .Q(plm_fsm_ci_counter0_reg_rx_count[4]), + .CLR(plm_rst) + ); + FDCE plm_fsm_ci_counter0_reg_rx_count_3_ ( + .CE(plm_fsm_ci_counter0_N_61102_i), + .C(mgt_clk), + .D(plm_fsm_ci_counter0_reg_rx_count_s[3]), + .Q(plm_fsm_ci_counter0_reg_rx_count[3]), + .CLR(plm_rst) + ); + FDPE plm_fsm_ci_counter0_reg_rx_count_2_ ( + .PRE(plm_rst), + .CE(plm_fsm_ci_counter0_N_61102_i), + .C(mgt_clk), + .D(plm_fsm_ci_counter0_reg_rx_count_s[2]), + .Q(plm_fsm_ci_counter0_reg_rx_count[2]) + ); + FDCE plm_fsm_ci_counter0_reg_rx_count_1_ ( + .CE(plm_fsm_ci_counter0_N_61102_i), + .C(mgt_clk), + .D(plm_fsm_ci_counter0_reg_rx_count_s[1]), + .Q(plm_fsm_ci_counter0_reg_rx_count[1]), + .CLR(plm_rst) + ); + FDCE plm_fsm_ci_counter0_reg_rx_count_0_ ( + .CE(plm_fsm_ci_counter0_N_61102_i), + .C(mgt_clk), + .D(plm_fsm_ci_counter0_reg_rx_count_s[0]), + .Q(plm_fsm_ci_counter0_reg_rx_count[0]), + .CLR(plm_rst) + ); + FDC plm_fsm_ci_counter0_reg_expired ( + .C(mgt_clk), + .D(plm_fsm_ci_counter0_reg_expired_5), + .Q(plm_fsm_ci_cntrout0), + .CLR(plm_rst) + ); + FDCE plm_fsm_ci_counter0_reg_oneshot ( + .CE(plm_fsm_ci_counter0_N_61219_i), + .C(mgt_clk), + .D(plm_fsm_reg_state_11__608), + .Q(plm_fsm_ci_counter0_reg_oneshot_1894), + .CLR(plm_rst) + ); + FDCE plm_fsm_ci_counter0_reg_rx_expired ( + .CE(plm_fsm_ci_counter0_N_61153_i), + .C(mgt_clk), + .D(plm_fsm_reg_state_11__608), + .Q(plm_fsm_ci_counter0_reg_rx_expired_612), + .CLR(plm_rst) + ); + FDCE plm_fsm_ci_counter0_reg_tx_expired ( + .CE(plm_fsm_ci_counter0_N_61064_i_1895), + .C(mgt_clk), + .D(plm_fsm_ci_counter0_reg_tx_count17_0_a2_0_a2_0_a3_0_a2_0), + .Q(plm_fsm_ci_counter0_reg_tx_expired_1896), + .CLR(plm_rst) + ); + INV plm_fsm_ci_counter0_N_61223_i ( + .I(plm_fsm_ci_counter0_un1_enable_1_0_a2_0_a2_0_a3_0_a2_5), + .O(plm_fsm_ci_counter0_N_61223_i_1897) + ); + defparam plm_fsm_ci_counter0_reg_rx_count_qxu_0_0_.INIT = 4'h7; + LUT2_L plm_fsm_ci_counter0_reg_rx_count_qxu_0_0_ ( + .I0(I_5129_0_a2_0_a2_0_a3_0_a2_38), + .I1(plm_fsm_ci_counter0_reg_rx_count[0]), + .LO(plm_fsm_ci_counter0_reg_rx_count_qxu[0]) + ); + defparam plm_fsm_ci_counter0_reg_rx_count_qxu_0_1_.INIT = 4'h7; + LUT2_L plm_fsm_ci_counter0_reg_rx_count_qxu_0_1_ ( + .I0(I_5129_0_a2_0_a2_0_a3_0_a2_38), + .I1(plm_fsm_ci_counter0_reg_rx_count[1]), + .LO(plm_fsm_ci_counter0_reg_rx_count_qxu[1]) + ); + defparam plm_fsm_ci_counter0_reg_rx_count_qxu_0_2_.INIT = 8'h1B; + LUT3_L plm_fsm_ci_counter0_reg_rx_count_qxu_0_2_ ( + .I0(I_5129_0_a2_0_a2_0_a3_0_a2_38), + .I1(plm_fsm_ci_counter0_N_87181_i_1898), + .I2(plm_fsm_ci_counter0_reg_rx_count[2]), + .LO(plm_fsm_ci_counter0_reg_rx_count_qxu[2]) + ); + defparam plm_fsm_ci_counter0_reg_rx_count_qxu_0_3_.INIT = 4'h7; + LUT2_L plm_fsm_ci_counter0_reg_rx_count_qxu_0_3_ ( + .I0(I_5129_0_a2_0_a2_0_a3_0_a2_38), + .I1(plm_fsm_ci_counter0_reg_rx_count[3]), + .LO(plm_fsm_ci_counter0_reg_rx_count_qxu[3]) + ); + defparam plm_fsm_ci_counter0_reg_rx_count_qxu_0_4_.INIT = 4'h7; + LUT2_L plm_fsm_ci_counter0_reg_rx_count_qxu_0_4_ ( + .I0(I_5129_0_a2_0_a2_0_a3_0_a2_38), + .I1(plm_fsm_ci_counter0_reg_rx_count[4]), + .LO(plm_fsm_ci_counter0_reg_rx_count_qxu[4]) + ); + defparam plm_fsm_ci_counter0_reg_rx_count_qxu_0_5_.INIT = 4'h7; + LUT2_L plm_fsm_ci_counter0_reg_rx_count_qxu_0_5_ ( + .I0(I_5129_0_a2_0_a2_0_a3_0_a2_38), + .I1(plm_fsm_ci_counter0_reg_rx_count[5]), + .LO(plm_fsm_ci_counter0_reg_rx_count_qxu[5]) + ); + defparam plm_fsm_ci_counter0_reg_rx_count_qxu_0_6_.INIT = 4'h7; + LUT2_L plm_fsm_ci_counter0_reg_rx_count_qxu_0_6_ ( + .I0(I_5129_0_a2_0_a2_0_a3_0_a2_38), + .I1(plm_fsm_ci_counter0_reg_rx_count[6]), + .LO(plm_fsm_ci_counter0_reg_rx_count_qxu[6]) + ); + defparam plm_fsm_ci_counter0_reg_rx_count_qxu_0_7_.INIT = 4'h7; + LUT2_L plm_fsm_ci_counter0_reg_rx_count_qxu_0_7_ ( + .I0(I_5129_0_a2_0_a2_0_a3_0_a2_38), + .I1(plm_fsm_ci_counter0_reg_rx_count[7]), + .LO(plm_fsm_ci_counter0_reg_rx_count_qxu[7]) + ); + defparam plm_fsm_ci_counter0_reg_tx_count_qxu_0_0_.INIT = 4'h7; + LUT2_L plm_fsm_ci_counter0_reg_tx_count_qxu_0_0_ ( + .I0(plm_fsm_ci_counter0_un1_enable_1_0_a2_0_a2_0_a3_0_a2_5), + .I1(plm_fsm_ci_counter0_reg_tx_count[0]), + .LO(plm_fsm_ci_counter0_reg_tx_count_qxu[0]) + ); + defparam plm_fsm_ci_counter0_reg_tx_count_qxu_0_1_.INIT = 4'h7; + LUT2_L plm_fsm_ci_counter0_reg_tx_count_qxu_0_1_ ( + .I0(plm_fsm_ci_counter0_un1_enable_1_0_a2_0_a2_0_a3_0_a2_5), + .I1(plm_fsm_ci_counter0_reg_tx_count[1]), + .LO(plm_fsm_ci_counter0_reg_tx_count_qxu[1]) + ); + defparam plm_fsm_ci_counter0_reg_tx_count_qxu_0_2_.INIT = 4'h7; + LUT2_L plm_fsm_ci_counter0_reg_tx_count_qxu_0_2_ ( + .I0(plm_fsm_ci_counter0_un1_enable_1_0_a2_0_a2_0_a3_0_a2_5), + .I1(plm_fsm_ci_counter0_reg_tx_count[2]), + .LO(plm_fsm_ci_counter0_reg_tx_count_qxu[2]) + ); + defparam plm_fsm_ci_counter0_reg_tx_count_qxu_0_3_.INIT = 8'h2E; + LUT3_L plm_fsm_ci_counter0_reg_tx_count_qxu_0_3_ ( + .I0(plm_fsm_ci_counter0_reg_tx_count17_0_a2_0_a2_0_a3_0_a2_0), + .I1(plm_fsm_ci_counter0_un1_enable_1_0_a2_0_a2_0_a3_0_a2_5), + .I2(plm_fsm_ci_counter0_reg_tx_count[3]), + .LO(plm_fsm_ci_counter0_reg_tx_count_qxu[3]) + ); + defparam plm_fsm_ci_counter0_reg_tx_count_qxu_0_4_.INIT = 4'h7; + LUT2_L plm_fsm_ci_counter0_reg_tx_count_qxu_0_4_ ( + .I0(plm_fsm_ci_counter0_un1_enable_1_0_a2_0_a2_0_a3_0_a2_5), + .I1(plm_fsm_ci_counter0_reg_tx_count[4]), + .LO(plm_fsm_ci_counter0_reg_tx_count_qxu[4]) + ); + defparam plm_fsm_ci_counter0_reg_tx_count_qxu_0_5_.INIT = 4'h7; + LUT2_L plm_fsm_ci_counter0_reg_tx_count_qxu_0_5_ ( + .I0(plm_fsm_ci_counter0_un1_enable_1_0_a2_0_a2_0_a3_0_a2_5), + .I1(plm_fsm_ci_counter0_reg_tx_count[5]), + .LO(plm_fsm_ci_counter0_reg_tx_count_qxu[5]) + ); + defparam plm_fsm_ci_counter0_reg_tx_count_qxu_0_6_.INIT = 4'h7; + LUT2_L plm_fsm_ci_counter0_reg_tx_count_qxu_0_6_ ( + .I0(plm_fsm_ci_counter0_un1_enable_1_0_a2_0_a2_0_a3_0_a2_5), + .I1(plm_fsm_ci_counter0_reg_tx_count[6]), + .LO(plm_fsm_ci_counter0_reg_tx_count_qxu[6]) + ); + defparam plm_fsm_ci_counter0_reg_tx_count_qxu_0_7_.INIT = 4'h7; + LUT2_L plm_fsm_ci_counter0_reg_tx_count_qxu_0_7_ ( + .I0(plm_fsm_ci_counter0_un1_enable_1_0_a2_0_a2_0_a3_0_a2_5), + .I1(plm_fsm_ci_counter0_reg_tx_count[7]), + .LO(plm_fsm_ci_counter0_reg_tx_count_qxu[7]) + ); + VCC plm_fsm_ci_counter1_VCC ( + .P(plm_fsm_ci_counter1_VCC_1899) + ); + MUXCY_L plm_fsm_ci_counter1_reg_rx_count_cry_0_ ( + .CI(N_61134_i_41), + .DI(plm_fsm_ci_counter1_VCC_1899), + .LO(plm_fsm_ci_counter1_reg_rx_count_cry[0]), + .S(plm_fsm_ci_counter1_reg_rx_count_qxu[0]) + ); + XORCY plm_fsm_ci_counter1_reg_rx_count_s_0_ ( + .CI(N_61134_i_41), + .LI(plm_fsm_ci_counter1_reg_rx_count_qxu[0]), + .O(plm_fsm_ci_counter1_reg_rx_count_s[0]) + ); + MUXCY_L plm_fsm_ci_counter1_reg_rx_count_cry_1_ ( + .CI(plm_fsm_ci_counter1_reg_rx_count_cry[0]), + .DI(plm_fsm_ci_counter1_VCC_1899), + .LO(plm_fsm_ci_counter1_reg_rx_count_cry[1]), + .S(plm_fsm_ci_counter1_reg_rx_count_qxu[1]) + ); + XORCY plm_fsm_ci_counter1_reg_rx_count_s_1_ ( + .CI(plm_fsm_ci_counter1_reg_rx_count_cry[0]), + .LI(plm_fsm_ci_counter1_reg_rx_count_qxu[1]), + .O(plm_fsm_ci_counter1_reg_rx_count_s[1]) + ); + MUXCY_L plm_fsm_ci_counter1_reg_rx_count_cry_2_ ( + .CI(plm_fsm_ci_counter1_reg_rx_count_cry[1]), + .DI(plm_fsm_ci_counter1_VCC_1899), + .LO(plm_fsm_ci_counter1_reg_rx_count_cry[2]), + .S(plm_fsm_ci_counter1_reg_rx_count_qxu[2]) + ); + XORCY plm_fsm_ci_counter1_reg_rx_count_s_2_ ( + .CI(plm_fsm_ci_counter1_reg_rx_count_cry[1]), + .LI(plm_fsm_ci_counter1_reg_rx_count_qxu[2]), + .O(plm_fsm_ci_counter1_reg_rx_count_s[2]) + ); + MUXCY_L plm_fsm_ci_counter1_reg_rx_count_cry_3_ ( + .CI(plm_fsm_ci_counter1_reg_rx_count_cry[2]), + .DI(plm_fsm_ci_counter1_VCC_1899), + .LO(plm_fsm_ci_counter1_reg_rx_count_cry[3]), + .S(plm_fsm_ci_counter1_reg_rx_count_qxu[3]) + ); + XORCY plm_fsm_ci_counter1_reg_rx_count_s_3_ ( + .CI(plm_fsm_ci_counter1_reg_rx_count_cry[2]), + .LI(plm_fsm_ci_counter1_reg_rx_count_qxu[3]), + .O(plm_fsm_ci_counter1_reg_rx_count_s[3]) + ); + MUXCY_L plm_fsm_ci_counter1_reg_rx_count_cry_4_ ( + .CI(plm_fsm_ci_counter1_reg_rx_count_cry[3]), + .DI(plm_fsm_ci_counter1_VCC_1899), + .LO(plm_fsm_ci_counter1_reg_rx_count_cry[4]), + .S(plm_fsm_ci_counter1_reg_rx_count_qxu[4]) + ); + XORCY plm_fsm_ci_counter1_reg_rx_count_s_4_ ( + .CI(plm_fsm_ci_counter1_reg_rx_count_cry[3]), + .LI(plm_fsm_ci_counter1_reg_rx_count_qxu[4]), + .O(plm_fsm_ci_counter1_reg_rx_count_s[4]) + ); + MUXCY_L plm_fsm_ci_counter1_reg_rx_count_cry_5_ ( + .CI(plm_fsm_ci_counter1_reg_rx_count_cry[4]), + .DI(plm_fsm_ci_counter1_VCC_1899), + .LO(plm_fsm_ci_counter1_reg_rx_count_cry[5]), + .S(plm_fsm_ci_counter1_reg_rx_count_qxu[5]) + ); + XORCY plm_fsm_ci_counter1_reg_rx_count_s_5_ ( + .CI(plm_fsm_ci_counter1_reg_rx_count_cry[4]), + .LI(plm_fsm_ci_counter1_reg_rx_count_qxu[5]), + .O(plm_fsm_ci_counter1_reg_rx_count_s[5]) + ); + MUXCY_L plm_fsm_ci_counter1_reg_rx_count_cry_6_ ( + .CI(plm_fsm_ci_counter1_reg_rx_count_cry[5]), + .DI(plm_fsm_ci_counter1_VCC_1899), + .LO(plm_fsm_ci_counter1_reg_rx_count_cry[6]), + .S(plm_fsm_ci_counter1_reg_rx_count_qxu[6]) + ); + XORCY plm_fsm_ci_counter1_reg_rx_count_s_6_ ( + .CI(plm_fsm_ci_counter1_reg_rx_count_cry[5]), + .LI(plm_fsm_ci_counter1_reg_rx_count_qxu[6]), + .O(plm_fsm_ci_counter1_reg_rx_count_s[6]) + ); + XORCY plm_fsm_ci_counter1_reg_rx_count_s_7_ ( + .CI(plm_fsm_ci_counter1_reg_rx_count_cry[6]), + .LI(plm_fsm_ci_counter1_reg_rx_count_qxu[7]), + .O(plm_fsm_ci_counter1_reg_rx_count_s[7]) + ); + MUXCY_L plm_fsm_ci_counter1_reg_tx_count_cry_0_ ( + .CI(plm_fsm_ci_counter1_N_61224_i_1904), + .DI(plm_fsm_ci_counter1_VCC_1899), + .LO(plm_fsm_ci_counter1_reg_tx_count_cry[0]), + .S(plm_fsm_ci_counter1_reg_tx_count_qxu[0]) + ); + XORCY plm_fsm_ci_counter1_reg_tx_count_s_0_ ( + .CI(plm_fsm_ci_counter1_N_61224_i_1904), + .LI(plm_fsm_ci_counter1_reg_tx_count_qxu[0]), + .O(plm_fsm_ci_counter1_reg_tx_count_s[0]) + ); + MUXCY_L plm_fsm_ci_counter1_reg_tx_count_cry_1_ ( + .CI(plm_fsm_ci_counter1_reg_tx_count_cry[0]), + .DI(plm_fsm_ci_counter1_VCC_1899), + .LO(plm_fsm_ci_counter1_reg_tx_count_cry[1]), + .S(plm_fsm_ci_counter1_reg_tx_count_qxu[1]) + ); + XORCY plm_fsm_ci_counter1_reg_tx_count_s_1_ ( + .CI(plm_fsm_ci_counter1_reg_tx_count_cry[0]), + .LI(plm_fsm_ci_counter1_reg_tx_count_qxu[1]), + .O(plm_fsm_ci_counter1_reg_tx_count_s[1]) + ); + MUXCY_L plm_fsm_ci_counter1_reg_tx_count_cry_2_ ( + .CI(plm_fsm_ci_counter1_reg_tx_count_cry[1]), + .DI(plm_fsm_ci_counter1_VCC_1899), + .LO(plm_fsm_ci_counter1_reg_tx_count_cry[2]), + .S(plm_fsm_ci_counter1_reg_tx_count_qxu[2]) + ); + XORCY plm_fsm_ci_counter1_reg_tx_count_s_2_ ( + .CI(plm_fsm_ci_counter1_reg_tx_count_cry[1]), + .LI(plm_fsm_ci_counter1_reg_tx_count_qxu[2]), + .O(plm_fsm_ci_counter1_reg_tx_count_s[2]) + ); + MUXCY_L plm_fsm_ci_counter1_reg_tx_count_cry_3_ ( + .CI(plm_fsm_ci_counter1_reg_tx_count_cry[2]), + .DI(plm_fsm_ci_counter1_VCC_1899), + .LO(plm_fsm_ci_counter1_reg_tx_count_cry[3]), + .S(plm_fsm_ci_counter1_reg_tx_count_qxu[3]) + ); + XORCY plm_fsm_ci_counter1_reg_tx_count_s_3_ ( + .CI(plm_fsm_ci_counter1_reg_tx_count_cry[2]), + .LI(plm_fsm_ci_counter1_reg_tx_count_qxu[3]), + .O(plm_fsm_ci_counter1_reg_tx_count_s[3]) + ); + MUXCY_L plm_fsm_ci_counter1_reg_tx_count_cry_4_ ( + .CI(plm_fsm_ci_counter1_reg_tx_count_cry[3]), + .DI(plm_fsm_ci_counter1_VCC_1899), + .LO(plm_fsm_ci_counter1_reg_tx_count_cry[4]), + .S(plm_fsm_ci_counter1_reg_tx_count_qxu[4]) + ); + XORCY plm_fsm_ci_counter1_reg_tx_count_s_4_ ( + .CI(plm_fsm_ci_counter1_reg_tx_count_cry[3]), + .LI(plm_fsm_ci_counter1_reg_tx_count_qxu[4]), + .O(plm_fsm_ci_counter1_reg_tx_count_s[4]) + ); + MUXCY_L plm_fsm_ci_counter1_reg_tx_count_cry_5_ ( + .CI(plm_fsm_ci_counter1_reg_tx_count_cry[4]), + .DI(plm_fsm_ci_counter1_VCC_1899), + .LO(plm_fsm_ci_counter1_reg_tx_count_cry[5]), + .S(plm_fsm_ci_counter1_reg_tx_count_qxu[5]) + ); + XORCY plm_fsm_ci_counter1_reg_tx_count_s_5_ ( + .CI(plm_fsm_ci_counter1_reg_tx_count_cry[4]), + .LI(plm_fsm_ci_counter1_reg_tx_count_qxu[5]), + .O(plm_fsm_ci_counter1_reg_tx_count_s[5]) + ); + MUXCY_L plm_fsm_ci_counter1_reg_tx_count_cry_6_ ( + .CI(plm_fsm_ci_counter1_reg_tx_count_cry[5]), + .DI(plm_fsm_ci_counter1_VCC_1899), + .LO(plm_fsm_ci_counter1_reg_tx_count_cry[6]), + .S(plm_fsm_ci_counter1_reg_tx_count_qxu[6]) + ); + XORCY plm_fsm_ci_counter1_reg_tx_count_s_6_ ( + .CI(plm_fsm_ci_counter1_reg_tx_count_cry[5]), + .LI(plm_fsm_ci_counter1_reg_tx_count_qxu[6]), + .O(plm_fsm_ci_counter1_reg_tx_count_s[6]) + ); + XORCY plm_fsm_ci_counter1_reg_tx_count_s_7_ ( + .CI(plm_fsm_ci_counter1_reg_tx_count_cry[6]), + .LI(plm_fsm_ci_counter1_reg_tx_count_qxu[7]), + .O(plm_fsm_ci_counter1_reg_tx_count_s[7]) + ); + defparam plm_fsm_ci_counter1_un1_enable_4_i_0_0_0_a2_1.INIT = 4'h2; + LUT2 plm_fsm_ci_counter1_un1_enable_4_i_0_0_0_a2_1 ( + .I0(plm_reg_rx_idl_1_0), + .I1(plm_rx1_idl_c), + .O(plm_fsm_N_58717_1) + ); + defparam plm_fsm_ci_counter1_oneshot_monitor_un1_enable_0_a2_0_a2_0_a3_0_a2.INIT = 4'h4; + LUT2 plm_fsm_ci_counter1_oneshot_monitor_un1_enable_0_a2_0_a2_0_a3_0_a2 ( + .I0(plm_reg_rx_idl_1_0), + .I1(plm_fsm_reg_state_11__608), + .O(plm_fsm_ci_counter1_un1_enable_0_a2_0_a2_0_a3_0_a2_0) + ); + defparam plm_fsm_ci_counter1_loadable_tx_counter_reg_tx_count17_0_a2_0_a2_0_a3_0_a2.INIT = 4'h8; + LUT2 plm_fsm_ci_counter1_loadable_tx_counter_reg_tx_count17_0_a2_0_a2_0_a3_0_a2 ( + .I0(plm_fsm_ci_counter1_reg_oneshot_1901), + .I1(plm_fsm_reg_state_11__608), + .O(plm_fsm_ci_counter1_reg_tx_count17_0_a2_0_a2_0_a3_0_a2_2) + ); + defparam plm_fsm_ci_counter1_loadable_tx_counter_un1_reg_tx_count_0_a2_4.INIT = 16'h0001; + LUT4 plm_fsm_ci_counter1_loadable_tx_counter_un1_reg_tx_count_0_a2_4 ( + .I0(plm_fsm_ci_counter1_reg_tx_count[0]), + .I1(plm_fsm_ci_counter1_reg_tx_count[1]), + .I2(plm_fsm_ci_counter1_reg_tx_count[2]), + .I3(plm_fsm_ci_counter1_reg_tx_count[3]), + .O(plm_fsm_ci_counter1_un1_reg_tx_count_0_a2_4) + ); + defparam plm_fsm_ci_counter1_loadable_tx_counter_un1_reg_tx_count_0_a2_5.INIT = 16'h0001; + LUT4 plm_fsm_ci_counter1_loadable_tx_counter_un1_reg_tx_count_0_a2_5 ( + .I0(plm_fsm_ci_counter1_reg_tx_count[4]), + .I1(plm_fsm_ci_counter1_reg_tx_count[5]), + .I2(plm_fsm_ci_counter1_reg_tx_count[6]), + .I3(plm_fsm_ci_counter1_reg_tx_count[7]), + .O(plm_fsm_ci_counter1_un1_reg_tx_count_0_a2_5) + ); + defparam plm_fsm_ci_counter1_loadable_rx_counter_un1_reg_rx_count_0_a2_4.INIT = 16'h0001; + LUT4 plm_fsm_ci_counter1_loadable_rx_counter_un1_reg_rx_count_0_a2_4 ( + .I0(plm_fsm_ci_counter1_reg_rx_count[0]), + .I1(plm_fsm_ci_counter1_reg_rx_count[1]), + .I2(plm_fsm_ci_counter1_reg_rx_count[2]), + .I3(plm_fsm_ci_counter1_reg_rx_count[3]), + .O(plm_fsm_ci_counter1_un1_reg_rx_count_0_a2_4) + ); + defparam plm_fsm_ci_counter1_loadable_rx_counter_un1_reg_rx_count_0_a2_5.INIT = 16'h0001; + LUT4 plm_fsm_ci_counter1_loadable_rx_counter_un1_reg_rx_count_0_a2_5 ( + .I0(plm_fsm_ci_counter1_reg_rx_count[4]), + .I1(plm_fsm_ci_counter1_reg_rx_count[5]), + .I2(plm_fsm_ci_counter1_reg_rx_count[6]), + .I3(plm_fsm_ci_counter1_reg_rx_count[7]), + .O(plm_fsm_ci_counter1_un1_reg_rx_count_0_a2_5) + ); + defparam plm_fsm_ci_counter1_N_87180_i.INIT = 8'h2F; + LUT3_L plm_fsm_ci_counter1_N_87180_i ( + .I0(plm_fsm_N_58717_1), + .I1(plm_fsm_ci_counter1_reg_rx_expired_610), + .I2(plm_fsm_reg_state_11__608), + .LO(plm_fsm_ci_counter1_N_87180_i_1905) + ); + defparam plm_fsm_ci_counter1_N_61094_i.INIT = 4'hB; + LUT2 plm_fsm_ci_counter1_N_61094_i ( + .I0(plm_reg_sym_sent_0_), + .I1(plm_fsm_ci_counter1_un1_enable_1_0_a2_0_a2_0_a3_0_a2_4), + .O(plm_fsm_ci_counter1_N_61094_i_1900) + ); + defparam plm_fsm_ci_counter1_N_61063_i.INIT = 8'hD5; + LUT3 plm_fsm_ci_counter1_N_61063_i ( + .I0(plm_fsm_ci_counter1_reg_tx_count17_0_a2_0_a2_0_a3_0_a2_2), + .I1(plm_fsm_ci_counter1_un1_reg_tx_count_0_a2_4), + .I2(plm_fsm_ci_counter1_un1_reg_tx_count_0_a2_5), + .O(plm_fsm_ci_counter1_N_61063_i_1902) + ); + defparam plm_fsm_ci_counter1_loadable_rx_counter_N_61151_i.INIT = 8'h8F; + LUT3 plm_fsm_ci_counter1_loadable_rx_counter_N_61151_i ( + .I0(plm_fsm_ci_counter1_un1_reg_rx_count_0_a2_4), + .I1(plm_fsm_ci_counter1_un1_reg_rx_count_0_a2_5), + .I2(plm_fsm_reg_state_11__608), + .O(plm_fsm_ci_counter1_N_61151_i) + ); + defparam plm_fsm_ci_counter1_flagit_reg_expired_5_0_a2_0_a2_0_a3_0_a2.INIT = 8'h80; + LUT3_L plm_fsm_ci_counter1_flagit_reg_expired_5_0_a2_0_a2_0_a3_0_a2 ( + .I0(plm_fsm_ci_counter1_reg_rx_expired_610), + .I1(plm_fsm_ci_counter1_reg_tx_expired_1903), + .I2(plm_fsm_reg_state_11__608), + .LO(plm_fsm_ci_counter1_reg_expired_5) + ); + defparam plm_fsm_ci_counter1_loadable_rx_counter_N_61152_i.INIT = 8'hFB; + LUT3 plm_fsm_ci_counter1_loadable_rx_counter_N_61152_i ( + .I0(plm_fsm_ci_counter1_reg_rx_expired_610), + .I1(plm_fsm_reg_state_11__608), + .I2(plm_reg_rx_idl_1_0), + .O(plm_fsm_ci_counter1_N_61152_i) + ); + defparam plm_fsm_ci_counter1_un1_enable_1_0_a2_0_a2_0_a3_0_a2.INIT = 8'h40; + LUT3 plm_fsm_ci_counter1_un1_enable_1_0_a2_0_a2_0_a3_0_a2 ( + .I0(plm_fsm_ci_counter1_reg_tx_expired_1903), + .I1(plm_fsm_reg_state_11__608), + .I2(plm_fsm_ci_counter1_reg_oneshot_1901), + .O(plm_fsm_ci_counter1_un1_enable_1_0_a2_0_a2_0_a3_0_a2_4) + ); + FDCE plm_fsm_ci_counter1_reg_tx_count_7_ ( + .CE(plm_fsm_ci_counter1_N_61094_i_1900), + .C(mgt_clk), + .D(plm_fsm_ci_counter1_reg_tx_count_s[7]), + .Q(plm_fsm_ci_counter1_reg_tx_count[7]), + .CLR(plm_rst) + ); + FDCE plm_fsm_ci_counter1_reg_tx_count_6_ ( + .CE(plm_fsm_ci_counter1_N_61094_i_1900), + .C(mgt_clk), + .D(plm_fsm_ci_counter1_reg_tx_count_s[6]), + .Q(plm_fsm_ci_counter1_reg_tx_count[6]), + .CLR(plm_rst) + ); + FDCE plm_fsm_ci_counter1_reg_tx_count_5_ ( + .CE(plm_fsm_ci_counter1_N_61094_i_1900), + .C(mgt_clk), + .D(plm_fsm_ci_counter1_reg_tx_count_s[5]), + .Q(plm_fsm_ci_counter1_reg_tx_count[5]), + .CLR(plm_rst) + ); + FDCE plm_fsm_ci_counter1_reg_tx_count_4_ ( + .CE(plm_fsm_ci_counter1_N_61094_i_1900), + .C(mgt_clk), + .D(plm_fsm_ci_counter1_reg_tx_count_s[4]), + .Q(plm_fsm_ci_counter1_reg_tx_count[4]), + .CLR(plm_rst) + ); + FDPE plm_fsm_ci_counter1_reg_tx_count_3_ ( + .PRE(plm_rst), + .CE(plm_fsm_ci_counter1_N_61094_i_1900), + .C(mgt_clk), + .D(plm_fsm_ci_counter1_reg_tx_count_s[3]), + .Q(plm_fsm_ci_counter1_reg_tx_count[3]) + ); + FDCE plm_fsm_ci_counter1_reg_tx_count_2_ ( + .CE(plm_fsm_ci_counter1_N_61094_i_1900), + .C(mgt_clk), + .D(plm_fsm_ci_counter1_reg_tx_count_s[2]), + .Q(plm_fsm_ci_counter1_reg_tx_count[2]), + .CLR(plm_rst) + ); + FDCE plm_fsm_ci_counter1_reg_tx_count_1_ ( + .CE(plm_fsm_ci_counter1_N_61094_i_1900), + .C(mgt_clk), + .D(plm_fsm_ci_counter1_reg_tx_count_s[1]), + .Q(plm_fsm_ci_counter1_reg_tx_count[1]), + .CLR(plm_rst) + ); + FDCE plm_fsm_ci_counter1_reg_tx_count_0_ ( + .CE(plm_fsm_ci_counter1_N_61094_i_1900), + .C(mgt_clk), + .D(plm_fsm_ci_counter1_reg_tx_count_s[0]), + .Q(plm_fsm_ci_counter1_reg_tx_count[0]), + .CLR(plm_rst) + ); + FDCE plm_fsm_ci_counter1_reg_rx_count_7_ ( + .CE(plm_fsm_ci_counter1_N_61152_i), + .C(mgt_clk), + .D(plm_fsm_ci_counter1_reg_rx_count_s[7]), + .Q(plm_fsm_ci_counter1_reg_rx_count[7]), + .CLR(plm_rst) + ); + FDCE plm_fsm_ci_counter1_reg_rx_count_6_ ( + .CE(plm_fsm_ci_counter1_N_61152_i), + .C(mgt_clk), + .D(plm_fsm_ci_counter1_reg_rx_count_s[6]), + .Q(plm_fsm_ci_counter1_reg_rx_count[6]), + .CLR(plm_rst) + ); + FDCE plm_fsm_ci_counter1_reg_rx_count_5_ ( + .CE(plm_fsm_ci_counter1_N_61152_i), + .C(mgt_clk), + .D(plm_fsm_ci_counter1_reg_rx_count_s[5]), + .Q(plm_fsm_ci_counter1_reg_rx_count[5]), + .CLR(plm_rst) + ); + FDCE plm_fsm_ci_counter1_reg_rx_count_4_ ( + .CE(plm_fsm_ci_counter1_N_61152_i), + .C(mgt_clk), + .D(plm_fsm_ci_counter1_reg_rx_count_s[4]), + .Q(plm_fsm_ci_counter1_reg_rx_count[4]), + .CLR(plm_rst) + ); + FDCE plm_fsm_ci_counter1_reg_rx_count_3_ ( + .CE(plm_fsm_ci_counter1_N_61152_i), + .C(mgt_clk), + .D(plm_fsm_ci_counter1_reg_rx_count_s[3]), + .Q(plm_fsm_ci_counter1_reg_rx_count[3]), + .CLR(plm_rst) + ); + FDPE plm_fsm_ci_counter1_reg_rx_count_2_ ( + .PRE(plm_rst), + .CE(plm_fsm_ci_counter1_N_61152_i), + .C(mgt_clk), + .D(plm_fsm_ci_counter1_reg_rx_count_s[2]), + .Q(plm_fsm_ci_counter1_reg_rx_count[2]) + ); + FDCE plm_fsm_ci_counter1_reg_rx_count_1_ ( + .CE(plm_fsm_ci_counter1_N_61152_i), + .C(mgt_clk), + .D(plm_fsm_ci_counter1_reg_rx_count_s[1]), + .Q(plm_fsm_ci_counter1_reg_rx_count[1]), + .CLR(plm_rst) + ); + FDCE plm_fsm_ci_counter1_reg_rx_count_0_ ( + .CE(plm_fsm_ci_counter1_N_61152_i), + .C(mgt_clk), + .D(plm_fsm_ci_counter1_reg_rx_count_s[0]), + .Q(plm_fsm_ci_counter1_reg_rx_count[0]), + .CLR(plm_rst) + ); + FDC plm_fsm_ci_counter1_reg_expired ( + .C(mgt_clk), + .D(plm_fsm_ci_counter1_reg_expired_5), + .Q(plm_fsm_ci_cntrout1), + .CLR(plm_rst) + ); + FDCE plm_fsm_ci_counter1_reg_oneshot ( + .CE(plm_fsm_ci_counter1_N_61221_i), + .C(mgt_clk), + .D(plm_fsm_reg_state_11__608), + .Q(plm_fsm_ci_counter1_reg_oneshot_1901), + .CLR(plm_rst) + ); + FDCE plm_fsm_ci_counter1_reg_rx_expired ( + .CE(plm_fsm_ci_counter1_N_61151_i), + .C(mgt_clk), + .D(plm_fsm_reg_state_11__608), + .Q(plm_fsm_ci_counter1_reg_rx_expired_610), + .CLR(plm_rst) + ); + FDCE plm_fsm_ci_counter1_reg_tx_expired ( + .CE(plm_fsm_ci_counter1_N_61063_i_1902), + .C(mgt_clk), + .D(plm_fsm_ci_counter1_reg_tx_count17_0_a2_0_a2_0_a3_0_a2_2), + .Q(plm_fsm_ci_counter1_reg_tx_expired_1903), + .CLR(plm_rst) + ); + INV plm_fsm_ci_counter1_oneshot_monitor_N_61221_i ( + .I(plm_fsm_ci_counter1_un1_enable_0_a2_0_a2_0_a3_0_a2_0), + .O(plm_fsm_ci_counter1_N_61221_i) + ); + INV plm_fsm_ci_counter1_N_61224_i ( + .I(plm_fsm_ci_counter1_un1_enable_1_0_a2_0_a2_0_a3_0_a2_4), + .O(plm_fsm_ci_counter1_N_61224_i_1904) + ); + defparam plm_fsm_ci_counter1_reg_rx_count_qxu_0_0_.INIT = 4'h7; + LUT2_L plm_fsm_ci_counter1_reg_rx_count_qxu_0_0_ ( + .I0(I_5135_0_a2_0_a2_0_a3_0_a2_40), + .I1(plm_fsm_ci_counter1_reg_rx_count[0]), + .LO(plm_fsm_ci_counter1_reg_rx_count_qxu[0]) + ); + defparam plm_fsm_ci_counter1_reg_rx_count_qxu_0_1_.INIT = 4'h7; + LUT2_L plm_fsm_ci_counter1_reg_rx_count_qxu_0_1_ ( + .I0(I_5135_0_a2_0_a2_0_a3_0_a2_40), + .I1(plm_fsm_ci_counter1_reg_rx_count[1]), + .LO(plm_fsm_ci_counter1_reg_rx_count_qxu[1]) + ); + defparam plm_fsm_ci_counter1_reg_rx_count_qxu_0_2_.INIT = 8'h1B; + LUT3_L plm_fsm_ci_counter1_reg_rx_count_qxu_0_2_ ( + .I0(I_5135_0_a2_0_a2_0_a3_0_a2_40), + .I1(plm_fsm_ci_counter1_N_87180_i_1905), + .I2(plm_fsm_ci_counter1_reg_rx_count[2]), + .LO(plm_fsm_ci_counter1_reg_rx_count_qxu[2]) + ); + defparam plm_fsm_ci_counter1_reg_rx_count_qxu_0_3_.INIT = 4'h7; + LUT2_L plm_fsm_ci_counter1_reg_rx_count_qxu_0_3_ ( + .I0(I_5135_0_a2_0_a2_0_a3_0_a2_40), + .I1(plm_fsm_ci_counter1_reg_rx_count[3]), + .LO(plm_fsm_ci_counter1_reg_rx_count_qxu[3]) + ); + defparam plm_fsm_ci_counter1_reg_rx_count_qxu_0_4_.INIT = 4'h7; + LUT2_L plm_fsm_ci_counter1_reg_rx_count_qxu_0_4_ ( + .I0(I_5135_0_a2_0_a2_0_a3_0_a2_40), + .I1(plm_fsm_ci_counter1_reg_rx_count[4]), + .LO(plm_fsm_ci_counter1_reg_rx_count_qxu[4]) + ); + defparam plm_fsm_ci_counter1_reg_rx_count_qxu_0_5_.INIT = 4'h7; + LUT2_L plm_fsm_ci_counter1_reg_rx_count_qxu_0_5_ ( + .I0(I_5135_0_a2_0_a2_0_a3_0_a2_40), + .I1(plm_fsm_ci_counter1_reg_rx_count[5]), + .LO(plm_fsm_ci_counter1_reg_rx_count_qxu[5]) + ); + defparam plm_fsm_ci_counter1_reg_rx_count_qxu_0_6_.INIT = 4'h7; + LUT2_L plm_fsm_ci_counter1_reg_rx_count_qxu_0_6_ ( + .I0(I_5135_0_a2_0_a2_0_a3_0_a2_40), + .I1(plm_fsm_ci_counter1_reg_rx_count[6]), + .LO(plm_fsm_ci_counter1_reg_rx_count_qxu[6]) + ); + defparam plm_fsm_ci_counter1_reg_rx_count_qxu_0_7_.INIT = 4'h7; + LUT2_L plm_fsm_ci_counter1_reg_rx_count_qxu_0_7_ ( + .I0(I_5135_0_a2_0_a2_0_a3_0_a2_40), + .I1(plm_fsm_ci_counter1_reg_rx_count[7]), + .LO(plm_fsm_ci_counter1_reg_rx_count_qxu[7]) + ); + defparam plm_fsm_ci_counter1_reg_tx_count_qxu_0_0_.INIT = 4'h7; + LUT2_L plm_fsm_ci_counter1_reg_tx_count_qxu_0_0_ ( + .I0(plm_fsm_ci_counter1_un1_enable_1_0_a2_0_a2_0_a3_0_a2_4), + .I1(plm_fsm_ci_counter1_reg_tx_count[0]), + .LO(plm_fsm_ci_counter1_reg_tx_count_qxu[0]) + ); + defparam plm_fsm_ci_counter1_reg_tx_count_qxu_0_1_.INIT = 4'h7; + LUT2_L plm_fsm_ci_counter1_reg_tx_count_qxu_0_1_ ( + .I0(plm_fsm_ci_counter1_un1_enable_1_0_a2_0_a2_0_a3_0_a2_4), + .I1(plm_fsm_ci_counter1_reg_tx_count[1]), + .LO(plm_fsm_ci_counter1_reg_tx_count_qxu[1]) + ); + defparam plm_fsm_ci_counter1_reg_tx_count_qxu_0_2_.INIT = 4'h7; + LUT2_L plm_fsm_ci_counter1_reg_tx_count_qxu_0_2_ ( + .I0(plm_fsm_ci_counter1_un1_enable_1_0_a2_0_a2_0_a3_0_a2_4), + .I1(plm_fsm_ci_counter1_reg_tx_count[2]), + .LO(plm_fsm_ci_counter1_reg_tx_count_qxu[2]) + ); + defparam plm_fsm_ci_counter1_reg_tx_count_qxu_0_3_.INIT = 8'h2E; + LUT3_L plm_fsm_ci_counter1_reg_tx_count_qxu_0_3_ ( + .I0(plm_fsm_ci_counter1_reg_tx_count17_0_a2_0_a2_0_a3_0_a2_2), + .I1(plm_fsm_ci_counter1_un1_enable_1_0_a2_0_a2_0_a3_0_a2_4), + .I2(plm_fsm_ci_counter1_reg_tx_count[3]), + .LO(plm_fsm_ci_counter1_reg_tx_count_qxu[3]) + ); + defparam plm_fsm_ci_counter1_reg_tx_count_qxu_0_4_.INIT = 4'h7; + LUT2_L plm_fsm_ci_counter1_reg_tx_count_qxu_0_4_ ( + .I0(plm_fsm_ci_counter1_un1_enable_1_0_a2_0_a2_0_a3_0_a2_4), + .I1(plm_fsm_ci_counter1_reg_tx_count[4]), + .LO(plm_fsm_ci_counter1_reg_tx_count_qxu[4]) + ); + defparam plm_fsm_ci_counter1_reg_tx_count_qxu_0_5_.INIT = 4'h7; + LUT2_L plm_fsm_ci_counter1_reg_tx_count_qxu_0_5_ ( + .I0(plm_fsm_ci_counter1_un1_enable_1_0_a2_0_a2_0_a3_0_a2_4), + .I1(plm_fsm_ci_counter1_reg_tx_count[5]), + .LO(plm_fsm_ci_counter1_reg_tx_count_qxu[5]) + ); + defparam plm_fsm_ci_counter1_reg_tx_count_qxu_0_6_.INIT = 4'h7; + LUT2_L plm_fsm_ci_counter1_reg_tx_count_qxu_0_6_ ( + .I0(plm_fsm_ci_counter1_un1_enable_1_0_a2_0_a2_0_a3_0_a2_4), + .I1(plm_fsm_ci_counter1_reg_tx_count[6]), + .LO(plm_fsm_ci_counter1_reg_tx_count_qxu[6]) + ); + defparam plm_fsm_ci_counter1_reg_tx_count_qxu_0_7_.INIT = 4'h7; + LUT2_L plm_fsm_ci_counter1_reg_tx_count_qxu_0_7_ ( + .I0(plm_fsm_ci_counter1_un1_enable_1_0_a2_0_a2_0_a3_0_a2_4), + .I1(plm_fsm_ci_counter1_reg_tx_count[7]), + .LO(plm_fsm_ci_counter1_reg_tx_count_qxu[7]) + ); + VCC plm_fsm_ci_counter2_VCC ( + .P(plm_fsm_ci_counter2_VCC_1906) + ); + MUXCY_L plm_fsm_ci_counter2_reg_rx_count_cry_0_ ( + .CI(N_61135_i_43), + .DI(plm_fsm_ci_counter2_VCC_1906), + .LO(plm_fsm_ci_counter2_reg_rx_count_cry[0]), + .S(plm_fsm_ci_counter2_reg_rx_count_qxu[0]) + ); + XORCY plm_fsm_ci_counter2_reg_rx_count_s_0_ ( + .CI(N_61135_i_43), + .LI(plm_fsm_ci_counter2_reg_rx_count_qxu[0]), + .O(plm_fsm_ci_counter2_reg_rx_count_s[0]) + ); + MUXCY_L plm_fsm_ci_counter2_reg_rx_count_cry_1_ ( + .CI(plm_fsm_ci_counter2_reg_rx_count_cry[0]), + .DI(plm_fsm_ci_counter2_VCC_1906), + .LO(plm_fsm_ci_counter2_reg_rx_count_cry[1]), + .S(plm_fsm_ci_counter2_reg_rx_count_qxu[1]) + ); + XORCY plm_fsm_ci_counter2_reg_rx_count_s_1_ ( + .CI(plm_fsm_ci_counter2_reg_rx_count_cry[0]), + .LI(plm_fsm_ci_counter2_reg_rx_count_qxu[1]), + .O(plm_fsm_ci_counter2_reg_rx_count_s[1]) + ); + MUXCY_L plm_fsm_ci_counter2_reg_rx_count_cry_2_ ( + .CI(plm_fsm_ci_counter2_reg_rx_count_cry[1]), + .DI(plm_fsm_ci_counter2_VCC_1906), + .LO(plm_fsm_ci_counter2_reg_rx_count_cry[2]), + .S(plm_fsm_ci_counter2_reg_rx_count_qxu[2]) + ); + XORCY plm_fsm_ci_counter2_reg_rx_count_s_2_ ( + .CI(plm_fsm_ci_counter2_reg_rx_count_cry[1]), + .LI(plm_fsm_ci_counter2_reg_rx_count_qxu[2]), + .O(plm_fsm_ci_counter2_reg_rx_count_s[2]) + ); + MUXCY_L plm_fsm_ci_counter2_reg_rx_count_cry_3_ ( + .CI(plm_fsm_ci_counter2_reg_rx_count_cry[2]), + .DI(plm_fsm_ci_counter2_VCC_1906), + .LO(plm_fsm_ci_counter2_reg_rx_count_cry[3]), + .S(plm_fsm_ci_counter2_reg_rx_count_qxu[3]) + ); + XORCY plm_fsm_ci_counter2_reg_rx_count_s_3_ ( + .CI(plm_fsm_ci_counter2_reg_rx_count_cry[2]), + .LI(plm_fsm_ci_counter2_reg_rx_count_qxu[3]), + .O(plm_fsm_ci_counter2_reg_rx_count_s[3]) + ); + MUXCY_L plm_fsm_ci_counter2_reg_rx_count_cry_4_ ( + .CI(plm_fsm_ci_counter2_reg_rx_count_cry[3]), + .DI(plm_fsm_ci_counter2_VCC_1906), + .LO(plm_fsm_ci_counter2_reg_rx_count_cry[4]), + .S(plm_fsm_ci_counter2_reg_rx_count_qxu[4]) + ); + XORCY plm_fsm_ci_counter2_reg_rx_count_s_4_ ( + .CI(plm_fsm_ci_counter2_reg_rx_count_cry[3]), + .LI(plm_fsm_ci_counter2_reg_rx_count_qxu[4]), + .O(plm_fsm_ci_counter2_reg_rx_count_s[4]) + ); + MUXCY_L plm_fsm_ci_counter2_reg_rx_count_cry_5_ ( + .CI(plm_fsm_ci_counter2_reg_rx_count_cry[4]), + .DI(plm_fsm_ci_counter2_VCC_1906), + .LO(plm_fsm_ci_counter2_reg_rx_count_cry[5]), + .S(plm_fsm_ci_counter2_reg_rx_count_qxu[5]) + ); + XORCY plm_fsm_ci_counter2_reg_rx_count_s_5_ ( + .CI(plm_fsm_ci_counter2_reg_rx_count_cry[4]), + .LI(plm_fsm_ci_counter2_reg_rx_count_qxu[5]), + .O(plm_fsm_ci_counter2_reg_rx_count_s[5]) + ); + MUXCY_L plm_fsm_ci_counter2_reg_rx_count_cry_6_ ( + .CI(plm_fsm_ci_counter2_reg_rx_count_cry[5]), + .DI(plm_fsm_ci_counter2_VCC_1906), + .LO(plm_fsm_ci_counter2_reg_rx_count_cry[6]), + .S(plm_fsm_ci_counter2_reg_rx_count_qxu[6]) + ); + XORCY plm_fsm_ci_counter2_reg_rx_count_s_6_ ( + .CI(plm_fsm_ci_counter2_reg_rx_count_cry[5]), + .LI(plm_fsm_ci_counter2_reg_rx_count_qxu[6]), + .O(plm_fsm_ci_counter2_reg_rx_count_s[6]) + ); + XORCY plm_fsm_ci_counter2_reg_rx_count_s_7_ ( + .CI(plm_fsm_ci_counter2_reg_rx_count_cry[6]), + .LI(plm_fsm_ci_counter2_reg_rx_count_qxu[7]), + .O(plm_fsm_ci_counter2_reg_rx_count_s[7]) + ); + MUXCY_L plm_fsm_ci_counter2_reg_tx_count_cry_0_ ( + .CI(plm_fsm_ci_counter2_N_61225_i_1911), + .DI(plm_fsm_ci_counter2_VCC_1906), + .LO(plm_fsm_ci_counter2_reg_tx_count_cry[0]), + .S(plm_fsm_ci_counter2_reg_tx_count_qxu[0]) + ); + XORCY plm_fsm_ci_counter2_reg_tx_count_s_0_ ( + .CI(plm_fsm_ci_counter2_N_61225_i_1911), + .LI(plm_fsm_ci_counter2_reg_tx_count_qxu[0]), + .O(plm_fsm_ci_counter2_reg_tx_count_s[0]) + ); + MUXCY_L plm_fsm_ci_counter2_reg_tx_count_cry_1_ ( + .CI(plm_fsm_ci_counter2_reg_tx_count_cry[0]), + .DI(plm_fsm_ci_counter2_VCC_1906), + .LO(plm_fsm_ci_counter2_reg_tx_count_cry[1]), + .S(plm_fsm_ci_counter2_reg_tx_count_qxu[1]) + ); + XORCY plm_fsm_ci_counter2_reg_tx_count_s_1_ ( + .CI(plm_fsm_ci_counter2_reg_tx_count_cry[0]), + .LI(plm_fsm_ci_counter2_reg_tx_count_qxu[1]), + .O(plm_fsm_ci_counter2_reg_tx_count_s[1]) + ); + MUXCY_L plm_fsm_ci_counter2_reg_tx_count_cry_2_ ( + .CI(plm_fsm_ci_counter2_reg_tx_count_cry[1]), + .DI(plm_fsm_ci_counter2_VCC_1906), + .LO(plm_fsm_ci_counter2_reg_tx_count_cry[2]), + .S(plm_fsm_ci_counter2_reg_tx_count_qxu[2]) + ); + XORCY plm_fsm_ci_counter2_reg_tx_count_s_2_ ( + .CI(plm_fsm_ci_counter2_reg_tx_count_cry[1]), + .LI(plm_fsm_ci_counter2_reg_tx_count_qxu[2]), + .O(plm_fsm_ci_counter2_reg_tx_count_s[2]) + ); + MUXCY_L plm_fsm_ci_counter2_reg_tx_count_cry_3_ ( + .CI(plm_fsm_ci_counter2_reg_tx_count_cry[2]), + .DI(plm_fsm_ci_counter2_VCC_1906), + .LO(plm_fsm_ci_counter2_reg_tx_count_cry[3]), + .S(plm_fsm_ci_counter2_reg_tx_count_qxu[3]) + ); + XORCY plm_fsm_ci_counter2_reg_tx_count_s_3_ ( + .CI(plm_fsm_ci_counter2_reg_tx_count_cry[2]), + .LI(plm_fsm_ci_counter2_reg_tx_count_qxu[3]), + .O(plm_fsm_ci_counter2_reg_tx_count_s[3]) + ); + MUXCY_L plm_fsm_ci_counter2_reg_tx_count_cry_4_ ( + .CI(plm_fsm_ci_counter2_reg_tx_count_cry[3]), + .DI(plm_fsm_ci_counter2_VCC_1906), + .LO(plm_fsm_ci_counter2_reg_tx_count_cry[4]), + .S(plm_fsm_ci_counter2_reg_tx_count_qxu[4]) + ); + XORCY plm_fsm_ci_counter2_reg_tx_count_s_4_ ( + .CI(plm_fsm_ci_counter2_reg_tx_count_cry[3]), + .LI(plm_fsm_ci_counter2_reg_tx_count_qxu[4]), + .O(plm_fsm_ci_counter2_reg_tx_count_s[4]) + ); + MUXCY_L plm_fsm_ci_counter2_reg_tx_count_cry_5_ ( + .CI(plm_fsm_ci_counter2_reg_tx_count_cry[4]), + .DI(plm_fsm_ci_counter2_VCC_1906), + .LO(plm_fsm_ci_counter2_reg_tx_count_cry[5]), + .S(plm_fsm_ci_counter2_reg_tx_count_qxu[5]) + ); + XORCY plm_fsm_ci_counter2_reg_tx_count_s_5_ ( + .CI(plm_fsm_ci_counter2_reg_tx_count_cry[4]), + .LI(plm_fsm_ci_counter2_reg_tx_count_qxu[5]), + .O(plm_fsm_ci_counter2_reg_tx_count_s[5]) + ); + MUXCY_L plm_fsm_ci_counter2_reg_tx_count_cry_6_ ( + .CI(plm_fsm_ci_counter2_reg_tx_count_cry[5]), + .DI(plm_fsm_ci_counter2_VCC_1906), + .LO(plm_fsm_ci_counter2_reg_tx_count_cry[6]), + .S(plm_fsm_ci_counter2_reg_tx_count_qxu[6]) + ); + XORCY plm_fsm_ci_counter2_reg_tx_count_s_6_ ( + .CI(plm_fsm_ci_counter2_reg_tx_count_cry[5]), + .LI(plm_fsm_ci_counter2_reg_tx_count_qxu[6]), + .O(plm_fsm_ci_counter2_reg_tx_count_s[6]) + ); + XORCY plm_fsm_ci_counter2_reg_tx_count_s_7_ ( + .CI(plm_fsm_ci_counter2_reg_tx_count_cry[6]), + .LI(plm_fsm_ci_counter2_reg_tx_count_qxu[7]), + .O(plm_fsm_ci_counter2_reg_tx_count_s[7]) + ); + defparam plm_fsm_ci_counter2_un1_enable_4_i_0_0_0_a2_1.INIT = 4'h2; + LUT2 plm_fsm_ci_counter2_un1_enable_4_i_0_0_0_a2_1 ( + .I0(plm_reg_rx_idl_1_1), + .I1(plm_rx2_idl_c), + .O(plm_fsm_N_58716_1) + ); + defparam plm_fsm_ci_counter2_oneshot_monitor_un1_enable_0_a2_0_a2_0_a3_0_a2.INIT = 4'h4; + LUT2 plm_fsm_ci_counter2_oneshot_monitor_un1_enable_0_a2_0_a2_0_a3_0_a2 ( + .I0(plm_reg_rx_idl_1_1), + .I1(plm_fsm_reg_state_11__608), + .O(plm_fsm_ci_counter2_un1_enable_0_a2_0_a2_0_a3_0_a2_3) + ); + defparam plm_fsm_ci_counter2_loadable_tx_counter_reg_tx_count17_0_a2_0_a2_0_a2_0_a3_0_a2.INIT = 4'h8; + LUT2 plm_fsm_ci_counter2_loadable_tx_counter_reg_tx_count17_0_a2_0_a2_0_a2_0_a3_0_a2 ( + .I0(plm_fsm_ci_counter2_reg_oneshot_1908), + .I1(plm_fsm_reg_state_11__608), + .O(plm_fsm_ci_counter2_reg_tx_count17_0_a2_0_a2_0_a2_0_a3_0_a2) + ); + defparam plm_fsm_ci_counter2_loadable_tx_counter_un1_reg_tx_count_0_a2_0_a3_4.INIT = 16'h0001; + LUT4 plm_fsm_ci_counter2_loadable_tx_counter_un1_reg_tx_count_0_a2_0_a3_4 ( + .I0(plm_fsm_ci_counter2_reg_tx_count[0]), + .I1(plm_fsm_ci_counter2_reg_tx_count[1]), + .I2(plm_fsm_ci_counter2_reg_tx_count[2]), + .I3(plm_fsm_ci_counter2_reg_tx_count[3]), + .O(plm_fsm_ci_counter2_un1_reg_tx_count_0_a2_0_a3_4) + ); + defparam plm_fsm_ci_counter2_loadable_tx_counter_un1_reg_tx_count_0_a2_0_a3_5.INIT = 16'h0001; + LUT4 plm_fsm_ci_counter2_loadable_tx_counter_un1_reg_tx_count_0_a2_0_a3_5 ( + .I0(plm_fsm_ci_counter2_reg_tx_count[4]), + .I1(plm_fsm_ci_counter2_reg_tx_count[5]), + .I2(plm_fsm_ci_counter2_reg_tx_count[6]), + .I3(plm_fsm_ci_counter2_reg_tx_count[7]), + .O(plm_fsm_ci_counter2_un1_reg_tx_count_0_a2_0_a3_5) + ); + defparam plm_fsm_ci_counter2_loadable_rx_counter_un1_reg_rx_count_0_a2_4.INIT = 16'h0001; + LUT4 plm_fsm_ci_counter2_loadable_rx_counter_un1_reg_rx_count_0_a2_4 ( + .I0(plm_fsm_ci_counter2_reg_rx_count[0]), + .I1(plm_fsm_ci_counter2_reg_rx_count[1]), + .I2(plm_fsm_ci_counter2_reg_rx_count[2]), + .I3(plm_fsm_ci_counter2_reg_rx_count[3]), + .O(plm_fsm_ci_counter2_un1_reg_rx_count_0_a2_4) + ); + defparam plm_fsm_ci_counter2_loadable_rx_counter_un1_reg_rx_count_0_a2_5.INIT = 16'h0001; + LUT4 plm_fsm_ci_counter2_loadable_rx_counter_un1_reg_rx_count_0_a2_5 ( + .I0(plm_fsm_ci_counter2_reg_rx_count[4]), + .I1(plm_fsm_ci_counter2_reg_rx_count[5]), + .I2(plm_fsm_ci_counter2_reg_rx_count[6]), + .I3(plm_fsm_ci_counter2_reg_rx_count[7]), + .O(plm_fsm_ci_counter2_un1_reg_rx_count_0_a2_5) + ); + defparam plm_fsm_ci_counter2_N_87179_i.INIT = 8'h2F; + LUT3_L plm_fsm_ci_counter2_N_87179_i ( + .I0(plm_fsm_N_58716_1), + .I1(plm_fsm_ci_counter2_reg_rx_expired_609), + .I2(plm_fsm_reg_state_11__608), + .LO(plm_fsm_ci_counter2_N_87179_i_1912) + ); + defparam plm_fsm_ci_counter2_N_61095_i.INIT = 4'hB; + LUT2 plm_fsm_ci_counter2_N_61095_i ( + .I0(plm_reg_sym_sent_0_), + .I1(plm_fsm_ci_counter2_un1_enable_1_0_a2_0_a2_0_a3_0_a2_3), + .O(plm_fsm_ci_counter2_N_61095_i_1907) + ); + defparam plm_fsm_ci_counter2_N_61106_i.INIT = 8'hD5; + LUT3 plm_fsm_ci_counter2_N_61106_i ( + .I0(plm_fsm_ci_counter2_reg_tx_count17_0_a2_0_a2_0_a2_0_a3_0_a2), + .I1(plm_fsm_ci_counter2_un1_reg_tx_count_0_a2_0_a3_4), + .I2(plm_fsm_ci_counter2_un1_reg_tx_count_0_a2_0_a3_5), + .O(plm_fsm_ci_counter2_N_61106_i_1909) + ); + defparam plm_fsm_ci_counter2_loadable_rx_counter_N_61149_i.INIT = 8'h8F; + LUT3 plm_fsm_ci_counter2_loadable_rx_counter_N_61149_i ( + .I0(plm_fsm_ci_counter2_un1_reg_rx_count_0_a2_4), + .I1(plm_fsm_ci_counter2_un1_reg_rx_count_0_a2_5), + .I2(plm_fsm_reg_state_11__608), + .O(plm_fsm_ci_counter2_N_61149_i) + ); + defparam plm_fsm_ci_counter2_flagit_reg_expired_5_0_a2_0_a2_0_a3_0_a2.INIT = 8'h80; + LUT3_L plm_fsm_ci_counter2_flagit_reg_expired_5_0_a2_0_a2_0_a3_0_a2 ( + .I0(plm_fsm_ci_counter2_reg_rx_expired_609), + .I1(plm_fsm_ci_counter2_reg_tx_expired_1910), + .I2(plm_fsm_reg_state_11__608), + .LO(plm_fsm_ci_counter2_reg_expired_5) + ); + defparam plm_fsm_ci_counter2_loadable_rx_counter_N_61150_i.INIT = 8'hFB; + LUT3 plm_fsm_ci_counter2_loadable_rx_counter_N_61150_i ( + .I0(plm_fsm_ci_counter2_reg_rx_expired_609), + .I1(plm_fsm_reg_state_11__608), + .I2(plm_reg_rx_idl_1_1), + .O(plm_fsm_ci_counter2_N_61150_i) + ); + defparam plm_fsm_ci_counter2_un1_enable_1_0_a2_0_a2_0_a3_0_a2.INIT = 8'h40; + LUT3 plm_fsm_ci_counter2_un1_enable_1_0_a2_0_a2_0_a3_0_a2 ( + .I0(plm_fsm_ci_counter2_reg_tx_expired_1910), + .I1(plm_fsm_reg_state_11__608), + .I2(plm_fsm_ci_counter2_reg_oneshot_1908), + .O(plm_fsm_ci_counter2_un1_enable_1_0_a2_0_a2_0_a3_0_a2_3) + ); + FDCE plm_fsm_ci_counter2_reg_tx_count_7_ ( + .CE(plm_fsm_ci_counter2_N_61095_i_1907), + .C(mgt_clk), + .D(plm_fsm_ci_counter2_reg_tx_count_s[7]), + .Q(plm_fsm_ci_counter2_reg_tx_count[7]), + .CLR(plm_rst) + ); + FDCE plm_fsm_ci_counter2_reg_tx_count_6_ ( + .CE(plm_fsm_ci_counter2_N_61095_i_1907), + .C(mgt_clk), + .D(plm_fsm_ci_counter2_reg_tx_count_s[6]), + .Q(plm_fsm_ci_counter2_reg_tx_count[6]), + .CLR(plm_rst) + ); + FDCE plm_fsm_ci_counter2_reg_tx_count_5_ ( + .CE(plm_fsm_ci_counter2_N_61095_i_1907), + .C(mgt_clk), + .D(plm_fsm_ci_counter2_reg_tx_count_s[5]), + .Q(plm_fsm_ci_counter2_reg_tx_count[5]), + .CLR(plm_rst) + ); + FDCE plm_fsm_ci_counter2_reg_tx_count_4_ ( + .CE(plm_fsm_ci_counter2_N_61095_i_1907), + .C(mgt_clk), + .D(plm_fsm_ci_counter2_reg_tx_count_s[4]), + .Q(plm_fsm_ci_counter2_reg_tx_count[4]), + .CLR(plm_rst) + ); + FDPE plm_fsm_ci_counter2_reg_tx_count_3_ ( + .PRE(plm_rst), + .CE(plm_fsm_ci_counter2_N_61095_i_1907), + .C(mgt_clk), + .D(plm_fsm_ci_counter2_reg_tx_count_s[3]), + .Q(plm_fsm_ci_counter2_reg_tx_count[3]) + ); + FDCE plm_fsm_ci_counter2_reg_tx_count_2_ ( + .CE(plm_fsm_ci_counter2_N_61095_i_1907), + .C(mgt_clk), + .D(plm_fsm_ci_counter2_reg_tx_count_s[2]), + .Q(plm_fsm_ci_counter2_reg_tx_count[2]), + .CLR(plm_rst) + ); + FDCE plm_fsm_ci_counter2_reg_tx_count_1_ ( + .CE(plm_fsm_ci_counter2_N_61095_i_1907), + .C(mgt_clk), + .D(plm_fsm_ci_counter2_reg_tx_count_s[1]), + .Q(plm_fsm_ci_counter2_reg_tx_count[1]), + .CLR(plm_rst) + ); + FDCE plm_fsm_ci_counter2_reg_tx_count_0_ ( + .CE(plm_fsm_ci_counter2_N_61095_i_1907), + .C(mgt_clk), + .D(plm_fsm_ci_counter2_reg_tx_count_s[0]), + .Q(plm_fsm_ci_counter2_reg_tx_count[0]), + .CLR(plm_rst) + ); + FDCE plm_fsm_ci_counter2_reg_rx_count_7_ ( + .CE(plm_fsm_ci_counter2_N_61150_i), + .C(mgt_clk), + .D(plm_fsm_ci_counter2_reg_rx_count_s[7]), + .Q(plm_fsm_ci_counter2_reg_rx_count[7]), + .CLR(plm_rst) + ); + FDCE plm_fsm_ci_counter2_reg_rx_count_6_ ( + .CE(plm_fsm_ci_counter2_N_61150_i), + .C(mgt_clk), + .D(plm_fsm_ci_counter2_reg_rx_count_s[6]), + .Q(plm_fsm_ci_counter2_reg_rx_count[6]), + .CLR(plm_rst) + ); + FDCE plm_fsm_ci_counter2_reg_rx_count_5_ ( + .CE(plm_fsm_ci_counter2_N_61150_i), + .C(mgt_clk), + .D(plm_fsm_ci_counter2_reg_rx_count_s[5]), + .Q(plm_fsm_ci_counter2_reg_rx_count[5]), + .CLR(plm_rst) + ); + FDCE plm_fsm_ci_counter2_reg_rx_count_4_ ( + .CE(plm_fsm_ci_counter2_N_61150_i), + .C(mgt_clk), + .D(plm_fsm_ci_counter2_reg_rx_count_s[4]), + .Q(plm_fsm_ci_counter2_reg_rx_count[4]), + .CLR(plm_rst) + ); + FDCE plm_fsm_ci_counter2_reg_rx_count_3_ ( + .CE(plm_fsm_ci_counter2_N_61150_i), + .C(mgt_clk), + .D(plm_fsm_ci_counter2_reg_rx_count_s[3]), + .Q(plm_fsm_ci_counter2_reg_rx_count[3]), + .CLR(plm_rst) + ); + FDPE plm_fsm_ci_counter2_reg_rx_count_2_ ( + .PRE(plm_rst), + .CE(plm_fsm_ci_counter2_N_61150_i), + .C(mgt_clk), + .D(plm_fsm_ci_counter2_reg_rx_count_s[2]), + .Q(plm_fsm_ci_counter2_reg_rx_count[2]) + ); + FDCE plm_fsm_ci_counter2_reg_rx_count_1_ ( + .CE(plm_fsm_ci_counter2_N_61150_i), + .C(mgt_clk), + .D(plm_fsm_ci_counter2_reg_rx_count_s[1]), + .Q(plm_fsm_ci_counter2_reg_rx_count[1]), + .CLR(plm_rst) + ); + FDCE plm_fsm_ci_counter2_reg_rx_count_0_ ( + .CE(plm_fsm_ci_counter2_N_61150_i), + .C(mgt_clk), + .D(plm_fsm_ci_counter2_reg_rx_count_s[0]), + .Q(plm_fsm_ci_counter2_reg_rx_count[0]), + .CLR(plm_rst) + ); + FDC plm_fsm_ci_counter2_reg_expired ( + .C(mgt_clk), + .D(plm_fsm_ci_counter2_reg_expired_5), + .Q(plm_fsm_ci_cntrout2), + .CLR(plm_rst) + ); + FDCE plm_fsm_ci_counter2_reg_oneshot ( + .CE(plm_fsm_ci_counter2_N_61217_i), + .C(mgt_clk), + .D(plm_fsm_reg_state_11__608), + .Q(plm_fsm_ci_counter2_reg_oneshot_1908), + .CLR(plm_rst) + ); + FDCE plm_fsm_ci_counter2_reg_rx_expired ( + .CE(plm_fsm_ci_counter2_N_61149_i), + .C(mgt_clk), + .D(plm_fsm_reg_state_11__608), + .Q(plm_fsm_ci_counter2_reg_rx_expired_609), + .CLR(plm_rst) + ); + FDCE plm_fsm_ci_counter2_reg_tx_expired ( + .CE(plm_fsm_ci_counter2_N_61106_i_1909), + .C(mgt_clk), + .D(plm_fsm_ci_counter2_reg_tx_count17_0_a2_0_a2_0_a2_0_a3_0_a2), + .Q(plm_fsm_ci_counter2_reg_tx_expired_1910), + .CLR(plm_rst) + ); + INV plm_fsm_ci_counter2_oneshot_monitor_N_61217_i ( + .I(plm_fsm_ci_counter2_un1_enable_0_a2_0_a2_0_a3_0_a2_3), + .O(plm_fsm_ci_counter2_N_61217_i) + ); + INV plm_fsm_ci_counter2_N_61225_i ( + .I(plm_fsm_ci_counter2_un1_enable_1_0_a2_0_a2_0_a3_0_a2_3), + .O(plm_fsm_ci_counter2_N_61225_i_1911) + ); + defparam plm_fsm_ci_counter2_reg_rx_count_qxu_0_0_.INIT = 4'h7; + LUT2_L plm_fsm_ci_counter2_reg_rx_count_qxu_0_0_ ( + .I0(I_5141_0_a2_0_a2_0_a3_0_a2_42), + .I1(plm_fsm_ci_counter2_reg_rx_count[0]), + .LO(plm_fsm_ci_counter2_reg_rx_count_qxu[0]) + ); + defparam plm_fsm_ci_counter2_reg_rx_count_qxu_0_1_.INIT = 4'h7; + LUT2_L plm_fsm_ci_counter2_reg_rx_count_qxu_0_1_ ( + .I0(I_5141_0_a2_0_a2_0_a3_0_a2_42), + .I1(plm_fsm_ci_counter2_reg_rx_count[1]), + .LO(plm_fsm_ci_counter2_reg_rx_count_qxu[1]) + ); + defparam plm_fsm_ci_counter2_reg_rx_count_qxu_0_2_.INIT = 8'h1B; + LUT3_L plm_fsm_ci_counter2_reg_rx_count_qxu_0_2_ ( + .I0(I_5141_0_a2_0_a2_0_a3_0_a2_42), + .I1(plm_fsm_ci_counter2_N_87179_i_1912), + .I2(plm_fsm_ci_counter2_reg_rx_count[2]), + .LO(plm_fsm_ci_counter2_reg_rx_count_qxu[2]) + ); + defparam plm_fsm_ci_counter2_reg_rx_count_qxu_0_3_.INIT = 4'h7; + LUT2_L plm_fsm_ci_counter2_reg_rx_count_qxu_0_3_ ( + .I0(I_5141_0_a2_0_a2_0_a3_0_a2_42), + .I1(plm_fsm_ci_counter2_reg_rx_count[3]), + .LO(plm_fsm_ci_counter2_reg_rx_count_qxu[3]) + ); + defparam plm_fsm_ci_counter2_reg_rx_count_qxu_0_4_.INIT = 4'h7; + LUT2_L plm_fsm_ci_counter2_reg_rx_count_qxu_0_4_ ( + .I0(I_5141_0_a2_0_a2_0_a3_0_a2_42), + .I1(plm_fsm_ci_counter2_reg_rx_count[4]), + .LO(plm_fsm_ci_counter2_reg_rx_count_qxu[4]) + ); + defparam plm_fsm_ci_counter2_reg_rx_count_qxu_0_5_.INIT = 4'h7; + LUT2_L plm_fsm_ci_counter2_reg_rx_count_qxu_0_5_ ( + .I0(I_5141_0_a2_0_a2_0_a3_0_a2_42), + .I1(plm_fsm_ci_counter2_reg_rx_count[5]), + .LO(plm_fsm_ci_counter2_reg_rx_count_qxu[5]) + ); + defparam plm_fsm_ci_counter2_reg_rx_count_qxu_0_6_.INIT = 4'h7; + LUT2_L plm_fsm_ci_counter2_reg_rx_count_qxu_0_6_ ( + .I0(I_5141_0_a2_0_a2_0_a3_0_a2_42), + .I1(plm_fsm_ci_counter2_reg_rx_count[6]), + .LO(plm_fsm_ci_counter2_reg_rx_count_qxu[6]) + ); + defparam plm_fsm_ci_counter2_reg_rx_count_qxu_0_7_.INIT = 4'h7; + LUT2_L plm_fsm_ci_counter2_reg_rx_count_qxu_0_7_ ( + .I0(I_5141_0_a2_0_a2_0_a3_0_a2_42), + .I1(plm_fsm_ci_counter2_reg_rx_count[7]), + .LO(plm_fsm_ci_counter2_reg_rx_count_qxu[7]) + ); + defparam plm_fsm_ci_counter2_reg_tx_count_qxu_0_0_.INIT = 4'h7; + LUT2_L plm_fsm_ci_counter2_reg_tx_count_qxu_0_0_ ( + .I0(plm_fsm_ci_counter2_un1_enable_1_0_a2_0_a2_0_a3_0_a2_3), + .I1(plm_fsm_ci_counter2_reg_tx_count[0]), + .LO(plm_fsm_ci_counter2_reg_tx_count_qxu[0]) + ); + defparam plm_fsm_ci_counter2_reg_tx_count_qxu_0_1_.INIT = 4'h7; + LUT2_L plm_fsm_ci_counter2_reg_tx_count_qxu_0_1_ ( + .I0(plm_fsm_ci_counter2_un1_enable_1_0_a2_0_a2_0_a3_0_a2_3), + .I1(plm_fsm_ci_counter2_reg_tx_count[1]), + .LO(plm_fsm_ci_counter2_reg_tx_count_qxu[1]) + ); + defparam plm_fsm_ci_counter2_reg_tx_count_qxu_0_2_.INIT = 4'h7; + LUT2_L plm_fsm_ci_counter2_reg_tx_count_qxu_0_2_ ( + .I0(plm_fsm_ci_counter2_un1_enable_1_0_a2_0_a2_0_a3_0_a2_3), + .I1(plm_fsm_ci_counter2_reg_tx_count[2]), + .LO(plm_fsm_ci_counter2_reg_tx_count_qxu[2]) + ); + defparam plm_fsm_ci_counter2_reg_tx_count_qxu_0_3_.INIT = 8'h2E; + LUT3_L plm_fsm_ci_counter2_reg_tx_count_qxu_0_3_ ( + .I0(plm_fsm_ci_counter2_reg_tx_count17_0_a2_0_a2_0_a2_0_a3_0_a2), + .I1(plm_fsm_ci_counter2_un1_enable_1_0_a2_0_a2_0_a3_0_a2_3), + .I2(plm_fsm_ci_counter2_reg_tx_count[3]), + .LO(plm_fsm_ci_counter2_reg_tx_count_qxu[3]) + ); + defparam plm_fsm_ci_counter2_reg_tx_count_qxu_0_4_.INIT = 4'h7; + LUT2_L plm_fsm_ci_counter2_reg_tx_count_qxu_0_4_ ( + .I0(plm_fsm_ci_counter2_un1_enable_1_0_a2_0_a2_0_a3_0_a2_3), + .I1(plm_fsm_ci_counter2_reg_tx_count[4]), + .LO(plm_fsm_ci_counter2_reg_tx_count_qxu[4]) + ); + defparam plm_fsm_ci_counter2_reg_tx_count_qxu_0_5_.INIT = 4'h7; + LUT2_L plm_fsm_ci_counter2_reg_tx_count_qxu_0_5_ ( + .I0(plm_fsm_ci_counter2_un1_enable_1_0_a2_0_a2_0_a3_0_a2_3), + .I1(plm_fsm_ci_counter2_reg_tx_count[5]), + .LO(plm_fsm_ci_counter2_reg_tx_count_qxu[5]) + ); + defparam plm_fsm_ci_counter2_reg_tx_count_qxu_0_6_.INIT = 4'h7; + LUT2_L plm_fsm_ci_counter2_reg_tx_count_qxu_0_6_ ( + .I0(plm_fsm_ci_counter2_un1_enable_1_0_a2_0_a2_0_a3_0_a2_3), + .I1(plm_fsm_ci_counter2_reg_tx_count[6]), + .LO(plm_fsm_ci_counter2_reg_tx_count_qxu[6]) + ); + defparam plm_fsm_ci_counter2_reg_tx_count_qxu_0_7_.INIT = 4'h7; + LUT2_L plm_fsm_ci_counter2_reg_tx_count_qxu_0_7_ ( + .I0(plm_fsm_ci_counter2_un1_enable_1_0_a2_0_a2_0_a3_0_a2_3), + .I1(plm_fsm_ci_counter2_reg_tx_count[7]), + .LO(plm_fsm_ci_counter2_reg_tx_count_qxu[7]) + ); + VCC plm_fsm_ci_counter3_VCC ( + .P(plm_fsm_ci_counter3_VCC_1913) + ); + MUXCY_L plm_fsm_ci_counter3_reg_rx_count_cry_0_ ( + .CI(N_61136_i_45), + .DI(plm_fsm_ci_counter3_VCC_1913), + .LO(plm_fsm_ci_counter3_reg_rx_count_cry[0]), + .S(plm_fsm_ci_counter3_reg_rx_count_qxu[0]) + ); + XORCY plm_fsm_ci_counter3_reg_rx_count_s_0_ ( + .CI(N_61136_i_45), + .LI(plm_fsm_ci_counter3_reg_rx_count_qxu[0]), + .O(plm_fsm_ci_counter3_reg_rx_count_s[0]) + ); + MUXCY_L plm_fsm_ci_counter3_reg_rx_count_cry_1_ ( + .CI(plm_fsm_ci_counter3_reg_rx_count_cry[0]), + .DI(plm_fsm_ci_counter3_VCC_1913), + .LO(plm_fsm_ci_counter3_reg_rx_count_cry[1]), + .S(plm_fsm_ci_counter3_reg_rx_count_qxu[1]) + ); + XORCY plm_fsm_ci_counter3_reg_rx_count_s_1_ ( + .CI(plm_fsm_ci_counter3_reg_rx_count_cry[0]), + .LI(plm_fsm_ci_counter3_reg_rx_count_qxu[1]), + .O(plm_fsm_ci_counter3_reg_rx_count_s[1]) + ); + MUXCY_L plm_fsm_ci_counter3_reg_rx_count_cry_2_ ( + .CI(plm_fsm_ci_counter3_reg_rx_count_cry[1]), + .DI(plm_fsm_ci_counter3_VCC_1913), + .LO(plm_fsm_ci_counter3_reg_rx_count_cry[2]), + .S(plm_fsm_ci_counter3_reg_rx_count_qxu[2]) + ); + XORCY plm_fsm_ci_counter3_reg_rx_count_s_2_ ( + .CI(plm_fsm_ci_counter3_reg_rx_count_cry[1]), + .LI(plm_fsm_ci_counter3_reg_rx_count_qxu[2]), + .O(plm_fsm_ci_counter3_reg_rx_count_s[2]) + ); + MUXCY_L plm_fsm_ci_counter3_reg_rx_count_cry_3_ ( + .CI(plm_fsm_ci_counter3_reg_rx_count_cry[2]), + .DI(plm_fsm_ci_counter3_VCC_1913), + .LO(plm_fsm_ci_counter3_reg_rx_count_cry[3]), + .S(plm_fsm_ci_counter3_reg_rx_count_qxu[3]) + ); + XORCY plm_fsm_ci_counter3_reg_rx_count_s_3_ ( + .CI(plm_fsm_ci_counter3_reg_rx_count_cry[2]), + .LI(plm_fsm_ci_counter3_reg_rx_count_qxu[3]), + .O(plm_fsm_ci_counter3_reg_rx_count_s[3]) + ); + MUXCY_L plm_fsm_ci_counter3_reg_rx_count_cry_4_ ( + .CI(plm_fsm_ci_counter3_reg_rx_count_cry[3]), + .DI(plm_fsm_ci_counter3_VCC_1913), + .LO(plm_fsm_ci_counter3_reg_rx_count_cry[4]), + .S(plm_fsm_ci_counter3_reg_rx_count_qxu[4]) + ); + XORCY plm_fsm_ci_counter3_reg_rx_count_s_4_ ( + .CI(plm_fsm_ci_counter3_reg_rx_count_cry[3]), + .LI(plm_fsm_ci_counter3_reg_rx_count_qxu[4]), + .O(plm_fsm_ci_counter3_reg_rx_count_s[4]) + ); + MUXCY_L plm_fsm_ci_counter3_reg_rx_count_cry_5_ ( + .CI(plm_fsm_ci_counter3_reg_rx_count_cry[4]), + .DI(plm_fsm_ci_counter3_VCC_1913), + .LO(plm_fsm_ci_counter3_reg_rx_count_cry[5]), + .S(plm_fsm_ci_counter3_reg_rx_count_qxu[5]) + ); + XORCY plm_fsm_ci_counter3_reg_rx_count_s_5_ ( + .CI(plm_fsm_ci_counter3_reg_rx_count_cry[4]), + .LI(plm_fsm_ci_counter3_reg_rx_count_qxu[5]), + .O(plm_fsm_ci_counter3_reg_rx_count_s[5]) + ); + MUXCY_L plm_fsm_ci_counter3_reg_rx_count_cry_6_ ( + .CI(plm_fsm_ci_counter3_reg_rx_count_cry[5]), + .DI(plm_fsm_ci_counter3_VCC_1913), + .LO(plm_fsm_ci_counter3_reg_rx_count_cry[6]), + .S(plm_fsm_ci_counter3_reg_rx_count_qxu[6]) + ); + XORCY plm_fsm_ci_counter3_reg_rx_count_s_6_ ( + .CI(plm_fsm_ci_counter3_reg_rx_count_cry[5]), + .LI(plm_fsm_ci_counter3_reg_rx_count_qxu[6]), + .O(plm_fsm_ci_counter3_reg_rx_count_s[6]) + ); + XORCY plm_fsm_ci_counter3_reg_rx_count_s_7_ ( + .CI(plm_fsm_ci_counter3_reg_rx_count_cry[6]), + .LI(plm_fsm_ci_counter3_reg_rx_count_qxu[7]), + .O(plm_fsm_ci_counter3_reg_rx_count_s[7]) + ); + MUXCY_L plm_fsm_ci_counter3_reg_tx_count_cry_0_ ( + .CI(plm_fsm_ci_counter3_N_61226_i_1918), + .DI(plm_fsm_ci_counter3_VCC_1913), + .LO(plm_fsm_ci_counter3_reg_tx_count_cry[0]), + .S(plm_fsm_ci_counter3_reg_tx_count_qxu[0]) + ); + XORCY plm_fsm_ci_counter3_reg_tx_count_s_0_ ( + .CI(plm_fsm_ci_counter3_N_61226_i_1918), + .LI(plm_fsm_ci_counter3_reg_tx_count_qxu[0]), + .O(plm_fsm_ci_counter3_reg_tx_count_s[0]) + ); + MUXCY_L plm_fsm_ci_counter3_reg_tx_count_cry_1_ ( + .CI(plm_fsm_ci_counter3_reg_tx_count_cry[0]), + .DI(plm_fsm_ci_counter3_VCC_1913), + .LO(plm_fsm_ci_counter3_reg_tx_count_cry[1]), + .S(plm_fsm_ci_counter3_reg_tx_count_qxu[1]) + ); + XORCY plm_fsm_ci_counter3_reg_tx_count_s_1_ ( + .CI(plm_fsm_ci_counter3_reg_tx_count_cry[0]), + .LI(plm_fsm_ci_counter3_reg_tx_count_qxu[1]), + .O(plm_fsm_ci_counter3_reg_tx_count_s[1]) + ); + MUXCY_L plm_fsm_ci_counter3_reg_tx_count_cry_2_ ( + .CI(plm_fsm_ci_counter3_reg_tx_count_cry[1]), + .DI(plm_fsm_ci_counter3_VCC_1913), + .LO(plm_fsm_ci_counter3_reg_tx_count_cry[2]), + .S(plm_fsm_ci_counter3_reg_tx_count_qxu[2]) + ); + XORCY plm_fsm_ci_counter3_reg_tx_count_s_2_ ( + .CI(plm_fsm_ci_counter3_reg_tx_count_cry[1]), + .LI(plm_fsm_ci_counter3_reg_tx_count_qxu[2]), + .O(plm_fsm_ci_counter3_reg_tx_count_s[2]) + ); + MUXCY_L plm_fsm_ci_counter3_reg_tx_count_cry_3_ ( + .CI(plm_fsm_ci_counter3_reg_tx_count_cry[2]), + .DI(plm_fsm_ci_counter3_VCC_1913), + .LO(plm_fsm_ci_counter3_reg_tx_count_cry[3]), + .S(plm_fsm_ci_counter3_reg_tx_count_qxu[3]) + ); + XORCY plm_fsm_ci_counter3_reg_tx_count_s_3_ ( + .CI(plm_fsm_ci_counter3_reg_tx_count_cry[2]), + .LI(plm_fsm_ci_counter3_reg_tx_count_qxu[3]), + .O(plm_fsm_ci_counter3_reg_tx_count_s[3]) + ); + MUXCY_L plm_fsm_ci_counter3_reg_tx_count_cry_4_ ( + .CI(plm_fsm_ci_counter3_reg_tx_count_cry[3]), + .DI(plm_fsm_ci_counter3_VCC_1913), + .LO(plm_fsm_ci_counter3_reg_tx_count_cry[4]), + .S(plm_fsm_ci_counter3_reg_tx_count_qxu[4]) + ); + XORCY plm_fsm_ci_counter3_reg_tx_count_s_4_ ( + .CI(plm_fsm_ci_counter3_reg_tx_count_cry[3]), + .LI(plm_fsm_ci_counter3_reg_tx_count_qxu[4]), + .O(plm_fsm_ci_counter3_reg_tx_count_s[4]) + ); + MUXCY_L plm_fsm_ci_counter3_reg_tx_count_cry_5_ ( + .CI(plm_fsm_ci_counter3_reg_tx_count_cry[4]), + .DI(plm_fsm_ci_counter3_VCC_1913), + .LO(plm_fsm_ci_counter3_reg_tx_count_cry[5]), + .S(plm_fsm_ci_counter3_reg_tx_count_qxu[5]) + ); + XORCY plm_fsm_ci_counter3_reg_tx_count_s_5_ ( + .CI(plm_fsm_ci_counter3_reg_tx_count_cry[4]), + .LI(plm_fsm_ci_counter3_reg_tx_count_qxu[5]), + .O(plm_fsm_ci_counter3_reg_tx_count_s[5]) + ); + MUXCY_L plm_fsm_ci_counter3_reg_tx_count_cry_6_ ( + .CI(plm_fsm_ci_counter3_reg_tx_count_cry[5]), + .DI(plm_fsm_ci_counter3_VCC_1913), + .LO(plm_fsm_ci_counter3_reg_tx_count_cry[6]), + .S(plm_fsm_ci_counter3_reg_tx_count_qxu[6]) + ); + XORCY plm_fsm_ci_counter3_reg_tx_count_s_6_ ( + .CI(plm_fsm_ci_counter3_reg_tx_count_cry[5]), + .LI(plm_fsm_ci_counter3_reg_tx_count_qxu[6]), + .O(plm_fsm_ci_counter3_reg_tx_count_s[6]) + ); + XORCY plm_fsm_ci_counter3_reg_tx_count_s_7_ ( + .CI(plm_fsm_ci_counter3_reg_tx_count_cry[6]), + .LI(plm_fsm_ci_counter3_reg_tx_count_qxu[7]), + .O(plm_fsm_ci_counter3_reg_tx_count_s[7]) + ); + defparam plm_fsm_ci_counter3_un1_enable_4_i_0_0_0_a2_1.INIT = 4'h2; + LUT2 plm_fsm_ci_counter3_un1_enable_4_i_0_0_0_a2_1 ( + .I0(plm_reg_rx_idl_1_2), + .I1(plm_rx3_idl_c), + .O(plm_fsm_N_58715_1) + ); + defparam plm_fsm_ci_counter3_oneshot_monitor_un1_enable_0_a2_0_a2_0_a3_0_a2.INIT = 4'h4; + LUT2 plm_fsm_ci_counter3_oneshot_monitor_un1_enable_0_a2_0_a2_0_a3_0_a2 ( + .I0(plm_reg_rx_idl_1_2), + .I1(plm_fsm_reg_state_11__608), + .O(plm_fsm_ci_counter3_un1_enable_0_a2_0_a2_0_a3_0_a2_5) + ); + defparam plm_fsm_ci_counter3_loadable_tx_counter_reg_tx_count17_0_a2_0_a2_0_a2_0_a3_0_a2.INIT = 4'h8; + LUT2 plm_fsm_ci_counter3_loadable_tx_counter_reg_tx_count17_0_a2_0_a2_0_a2_0_a3_0_a2 ( + .I0(plm_fsm_ci_counter3_reg_oneshot_1915), + .I1(plm_fsm_reg_state_11__608), + .O(plm_fsm_ci_counter3_reg_tx_count17_0_a2_0_a2_0_a2_0_a3_0_a2_0) + ); + defparam plm_fsm_ci_counter3_loadable_tx_counter_un1_reg_tx_count_0_a2_0_a3_4.INIT = 16'h0001; + LUT4 plm_fsm_ci_counter3_loadable_tx_counter_un1_reg_tx_count_0_a2_0_a3_4 ( + .I0(plm_fsm_ci_counter3_reg_tx_count[0]), + .I1(plm_fsm_ci_counter3_reg_tx_count[1]), + .I2(plm_fsm_ci_counter3_reg_tx_count[2]), + .I3(plm_fsm_ci_counter3_reg_tx_count[3]), + .O(plm_fsm_ci_counter3_un1_reg_tx_count_0_a2_0_a3_4) + ); + defparam plm_fsm_ci_counter3_loadable_tx_counter_un1_reg_tx_count_0_a2_0_a3_5.INIT = 16'h0001; + LUT4 plm_fsm_ci_counter3_loadable_tx_counter_un1_reg_tx_count_0_a2_0_a3_5 ( + .I0(plm_fsm_ci_counter3_reg_tx_count[4]), + .I1(plm_fsm_ci_counter3_reg_tx_count[5]), + .I2(plm_fsm_ci_counter3_reg_tx_count[6]), + .I3(plm_fsm_ci_counter3_reg_tx_count[7]), + .O(plm_fsm_ci_counter3_un1_reg_tx_count_0_a2_0_a3_5) + ); + defparam plm_fsm_ci_counter3_loadable_rx_counter_un1_reg_rx_count_0_a2_4.INIT = 16'h0001; + LUT4 plm_fsm_ci_counter3_loadable_rx_counter_un1_reg_rx_count_0_a2_4 ( + .I0(plm_fsm_ci_counter3_reg_rx_count[0]), + .I1(plm_fsm_ci_counter3_reg_rx_count[1]), + .I2(plm_fsm_ci_counter3_reg_rx_count[2]), + .I3(plm_fsm_ci_counter3_reg_rx_count[3]), + .O(plm_fsm_ci_counter3_un1_reg_rx_count_0_a2_4) + ); + defparam plm_fsm_ci_counter3_loadable_rx_counter_un1_reg_rx_count_0_a2_5.INIT = 16'h0001; + LUT4 plm_fsm_ci_counter3_loadable_rx_counter_un1_reg_rx_count_0_a2_5 ( + .I0(plm_fsm_ci_counter3_reg_rx_count[4]), + .I1(plm_fsm_ci_counter3_reg_rx_count[5]), + .I2(plm_fsm_ci_counter3_reg_rx_count[6]), + .I3(plm_fsm_ci_counter3_reg_rx_count[7]), + .O(plm_fsm_ci_counter3_un1_reg_rx_count_0_a2_5) + ); + defparam plm_fsm_ci_counter3_N_87178_i.INIT = 8'h2F; + LUT3_L plm_fsm_ci_counter3_N_87178_i ( + .I0(plm_fsm_N_58715_1), + .I1(plm_fsm_ci_counter3_reg_rx_expired_607), + .I2(plm_fsm_reg_state_11__608), + .LO(plm_fsm_ci_counter3_N_87178_i_1919) + ); + defparam plm_fsm_ci_counter3_N_61096_i.INIT = 4'hB; + LUT2 plm_fsm_ci_counter3_N_61096_i ( + .I0(plm_reg_sym_sent_0_), + .I1(plm_fsm_ci_counter3_un1_enable_1_0_a2_0_a2_0_a3_0_a2_2), + .O(plm_fsm_ci_counter3_N_61096_i_1914) + ); + defparam plm_fsm_ci_counter3_N_61104_i.INIT = 8'hD5; + LUT3 plm_fsm_ci_counter3_N_61104_i ( + .I0(plm_fsm_ci_counter3_reg_tx_count17_0_a2_0_a2_0_a2_0_a3_0_a2_0), + .I1(plm_fsm_ci_counter3_un1_reg_tx_count_0_a2_0_a3_4), + .I2(plm_fsm_ci_counter3_un1_reg_tx_count_0_a2_0_a3_5), + .O(plm_fsm_ci_counter3_N_61104_i_1916) + ); + defparam plm_fsm_ci_counter3_loadable_rx_counter_N_61147_i.INIT = 8'h8F; + LUT3 plm_fsm_ci_counter3_loadable_rx_counter_N_61147_i ( + .I0(plm_fsm_ci_counter3_un1_reg_rx_count_0_a2_4), + .I1(plm_fsm_ci_counter3_un1_reg_rx_count_0_a2_5), + .I2(plm_fsm_reg_state_11__608), + .O(plm_fsm_ci_counter3_N_61147_i) + ); + defparam plm_fsm_ci_counter3_flagit_reg_expired_5_0_a2_0_a2_0_a3_0_a2.INIT = 8'h80; + LUT3_L plm_fsm_ci_counter3_flagit_reg_expired_5_0_a2_0_a2_0_a3_0_a2 ( + .I0(plm_fsm_ci_counter3_reg_rx_expired_607), + .I1(plm_fsm_ci_counter3_reg_tx_expired_1917), + .I2(plm_fsm_reg_state_11__608), + .LO(plm_fsm_ci_counter3_reg_expired_5) + ); + defparam plm_fsm_ci_counter3_loadable_rx_counter_N_61148_i.INIT = 8'hFB; + LUT3 plm_fsm_ci_counter3_loadable_rx_counter_N_61148_i ( + .I0(plm_fsm_ci_counter3_reg_rx_expired_607), + .I1(plm_fsm_reg_state_11__608), + .I2(plm_reg_rx_idl_1_2), + .O(plm_fsm_ci_counter3_N_61148_i) + ); + defparam plm_fsm_ci_counter3_un1_enable_1_0_a2_0_a2_0_a3_0_a2.INIT = 8'h40; + LUT3 plm_fsm_ci_counter3_un1_enable_1_0_a2_0_a2_0_a3_0_a2 ( + .I0(plm_fsm_ci_counter3_reg_tx_expired_1917), + .I1(plm_fsm_reg_state_11__608), + .I2(plm_fsm_ci_counter3_reg_oneshot_1915), + .O(plm_fsm_ci_counter3_un1_enable_1_0_a2_0_a2_0_a3_0_a2_2) + ); + FDCE plm_fsm_ci_counter3_reg_tx_count_7_ ( + .CE(plm_fsm_ci_counter3_N_61096_i_1914), + .C(mgt_clk), + .D(plm_fsm_ci_counter3_reg_tx_count_s[7]), + .Q(plm_fsm_ci_counter3_reg_tx_count[7]), + .CLR(plm_rst) + ); + FDCE plm_fsm_ci_counter3_reg_tx_count_6_ ( + .CE(plm_fsm_ci_counter3_N_61096_i_1914), + .C(mgt_clk), + .D(plm_fsm_ci_counter3_reg_tx_count_s[6]), + .Q(plm_fsm_ci_counter3_reg_tx_count[6]), + .CLR(plm_rst) + ); + FDCE plm_fsm_ci_counter3_reg_tx_count_5_ ( + .CE(plm_fsm_ci_counter3_N_61096_i_1914), + .C(mgt_clk), + .D(plm_fsm_ci_counter3_reg_tx_count_s[5]), + .Q(plm_fsm_ci_counter3_reg_tx_count[5]), + .CLR(plm_rst) + ); + FDCE plm_fsm_ci_counter3_reg_tx_count_4_ ( + .CE(plm_fsm_ci_counter3_N_61096_i_1914), + .C(mgt_clk), + .D(plm_fsm_ci_counter3_reg_tx_count_s[4]), + .Q(plm_fsm_ci_counter3_reg_tx_count[4]), + .CLR(plm_rst) + ); + FDPE plm_fsm_ci_counter3_reg_tx_count_3_ ( + .PRE(plm_rst), + .CE(plm_fsm_ci_counter3_N_61096_i_1914), + .C(mgt_clk), + .D(plm_fsm_ci_counter3_reg_tx_count_s[3]), + .Q(plm_fsm_ci_counter3_reg_tx_count[3]) + ); + FDCE plm_fsm_ci_counter3_reg_tx_count_2_ ( + .CE(plm_fsm_ci_counter3_N_61096_i_1914), + .C(mgt_clk), + .D(plm_fsm_ci_counter3_reg_tx_count_s[2]), + .Q(plm_fsm_ci_counter3_reg_tx_count[2]), + .CLR(plm_rst) + ); + FDCE plm_fsm_ci_counter3_reg_tx_count_1_ ( + .CE(plm_fsm_ci_counter3_N_61096_i_1914), + .C(mgt_clk), + .D(plm_fsm_ci_counter3_reg_tx_count_s[1]), + .Q(plm_fsm_ci_counter3_reg_tx_count[1]), + .CLR(plm_rst) + ); + FDCE plm_fsm_ci_counter3_reg_tx_count_0_ ( + .CE(plm_fsm_ci_counter3_N_61096_i_1914), + .C(mgt_clk), + .D(plm_fsm_ci_counter3_reg_tx_count_s[0]), + .Q(plm_fsm_ci_counter3_reg_tx_count[0]), + .CLR(plm_rst) + ); + FDCE plm_fsm_ci_counter3_reg_rx_count_7_ ( + .CE(plm_fsm_ci_counter3_N_61148_i), + .C(mgt_clk), + .D(plm_fsm_ci_counter3_reg_rx_count_s[7]), + .Q(plm_fsm_ci_counter3_reg_rx_count[7]), + .CLR(plm_rst) + ); + FDCE plm_fsm_ci_counter3_reg_rx_count_6_ ( + .CE(plm_fsm_ci_counter3_N_61148_i), + .C(mgt_clk), + .D(plm_fsm_ci_counter3_reg_rx_count_s[6]), + .Q(plm_fsm_ci_counter3_reg_rx_count[6]), + .CLR(plm_rst) + ); + FDCE plm_fsm_ci_counter3_reg_rx_count_5_ ( + .CE(plm_fsm_ci_counter3_N_61148_i), + .C(mgt_clk), + .D(plm_fsm_ci_counter3_reg_rx_count_s[5]), + .Q(plm_fsm_ci_counter3_reg_rx_count[5]), + .CLR(plm_rst) + ); + FDCE plm_fsm_ci_counter3_reg_rx_count_4_ ( + .CE(plm_fsm_ci_counter3_N_61148_i), + .C(mgt_clk), + .D(plm_fsm_ci_counter3_reg_rx_count_s[4]), + .Q(plm_fsm_ci_counter3_reg_rx_count[4]), + .CLR(plm_rst) + ); + FDCE plm_fsm_ci_counter3_reg_rx_count_3_ ( + .CE(plm_fsm_ci_counter3_N_61148_i), + .C(mgt_clk), + .D(plm_fsm_ci_counter3_reg_rx_count_s[3]), + .Q(plm_fsm_ci_counter3_reg_rx_count[3]), + .CLR(plm_rst) + ); + FDPE plm_fsm_ci_counter3_reg_rx_count_2_ ( + .PRE(plm_rst), + .CE(plm_fsm_ci_counter3_N_61148_i), + .C(mgt_clk), + .D(plm_fsm_ci_counter3_reg_rx_count_s[2]), + .Q(plm_fsm_ci_counter3_reg_rx_count[2]) + ); + FDCE plm_fsm_ci_counter3_reg_rx_count_1_ ( + .CE(plm_fsm_ci_counter3_N_61148_i), + .C(mgt_clk), + .D(plm_fsm_ci_counter3_reg_rx_count_s[1]), + .Q(plm_fsm_ci_counter3_reg_rx_count[1]), + .CLR(plm_rst) + ); + FDCE plm_fsm_ci_counter3_reg_rx_count_0_ ( + .CE(plm_fsm_ci_counter3_N_61148_i), + .C(mgt_clk), + .D(plm_fsm_ci_counter3_reg_rx_count_s[0]), + .Q(plm_fsm_ci_counter3_reg_rx_count[0]), + .CLR(plm_rst) + ); + FDC plm_fsm_ci_counter3_reg_expired ( + .C(mgt_clk), + .D(plm_fsm_ci_counter3_reg_expired_5), + .Q(plm_fsm_ci_cntrout3), + .CLR(plm_rst) + ); + FDCE plm_fsm_ci_counter3_reg_oneshot ( + .CE(plm_fsm_ci_counter3_N_61215_i), + .C(mgt_clk), + .D(plm_fsm_reg_state_11__608), + .Q(plm_fsm_ci_counter3_reg_oneshot_1915), + .CLR(plm_rst) + ); + FDCE plm_fsm_ci_counter3_reg_rx_expired ( + .CE(plm_fsm_ci_counter3_N_61147_i), + .C(mgt_clk), + .D(plm_fsm_reg_state_11__608), + .Q(plm_fsm_ci_counter3_reg_rx_expired_607), + .CLR(plm_rst) + ); + FDCE plm_fsm_ci_counter3_reg_tx_expired ( + .CE(plm_fsm_ci_counter3_N_61104_i_1916), + .C(mgt_clk), + .D(plm_fsm_ci_counter3_reg_tx_count17_0_a2_0_a2_0_a2_0_a3_0_a2_0), + .Q(plm_fsm_ci_counter3_reg_tx_expired_1917), + .CLR(plm_rst) + ); + INV plm_fsm_ci_counter3_oneshot_monitor_N_61215_i ( + .I(plm_fsm_ci_counter3_un1_enable_0_a2_0_a2_0_a3_0_a2_5), + .O(plm_fsm_ci_counter3_N_61215_i) + ); + INV plm_fsm_ci_counter3_N_61226_i ( + .I(plm_fsm_ci_counter3_un1_enable_1_0_a2_0_a2_0_a3_0_a2_2), + .O(plm_fsm_ci_counter3_N_61226_i_1918) + ); + defparam plm_fsm_ci_counter3_reg_rx_count_qxu_0_0_.INIT = 4'h7; + LUT2_L plm_fsm_ci_counter3_reg_rx_count_qxu_0_0_ ( + .I0(I_5147_0_a2_0_a2_0_a3_0_a2_44), + .I1(plm_fsm_ci_counter3_reg_rx_count[0]), + .LO(plm_fsm_ci_counter3_reg_rx_count_qxu[0]) + ); + defparam plm_fsm_ci_counter3_reg_rx_count_qxu_0_1_.INIT = 4'h7; + LUT2_L plm_fsm_ci_counter3_reg_rx_count_qxu_0_1_ ( + .I0(I_5147_0_a2_0_a2_0_a3_0_a2_44), + .I1(plm_fsm_ci_counter3_reg_rx_count[1]), + .LO(plm_fsm_ci_counter3_reg_rx_count_qxu[1]) + ); + defparam plm_fsm_ci_counter3_reg_rx_count_qxu_0_2_.INIT = 8'h1B; + LUT3_L plm_fsm_ci_counter3_reg_rx_count_qxu_0_2_ ( + .I0(I_5147_0_a2_0_a2_0_a3_0_a2_44), + .I1(plm_fsm_ci_counter3_N_87178_i_1919), + .I2(plm_fsm_ci_counter3_reg_rx_count[2]), + .LO(plm_fsm_ci_counter3_reg_rx_count_qxu[2]) + ); + defparam plm_fsm_ci_counter3_reg_rx_count_qxu_0_3_.INIT = 4'h7; + LUT2_L plm_fsm_ci_counter3_reg_rx_count_qxu_0_3_ ( + .I0(I_5147_0_a2_0_a2_0_a3_0_a2_44), + .I1(plm_fsm_ci_counter3_reg_rx_count[3]), + .LO(plm_fsm_ci_counter3_reg_rx_count_qxu[3]) + ); + defparam plm_fsm_ci_counter3_reg_rx_count_qxu_0_4_.INIT = 4'h7; + LUT2_L plm_fsm_ci_counter3_reg_rx_count_qxu_0_4_ ( + .I0(I_5147_0_a2_0_a2_0_a3_0_a2_44), + .I1(plm_fsm_ci_counter3_reg_rx_count[4]), + .LO(plm_fsm_ci_counter3_reg_rx_count_qxu[4]) + ); + defparam plm_fsm_ci_counter3_reg_rx_count_qxu_0_5_.INIT = 4'h7; + LUT2_L plm_fsm_ci_counter3_reg_rx_count_qxu_0_5_ ( + .I0(I_5147_0_a2_0_a2_0_a3_0_a2_44), + .I1(plm_fsm_ci_counter3_reg_rx_count[5]), + .LO(plm_fsm_ci_counter3_reg_rx_count_qxu[5]) + ); + defparam plm_fsm_ci_counter3_reg_rx_count_qxu_0_6_.INIT = 4'h7; + LUT2_L plm_fsm_ci_counter3_reg_rx_count_qxu_0_6_ ( + .I0(I_5147_0_a2_0_a2_0_a3_0_a2_44), + .I1(plm_fsm_ci_counter3_reg_rx_count[6]), + .LO(plm_fsm_ci_counter3_reg_rx_count_qxu[6]) + ); + defparam plm_fsm_ci_counter3_reg_rx_count_qxu_0_7_.INIT = 4'h7; + LUT2_L plm_fsm_ci_counter3_reg_rx_count_qxu_0_7_ ( + .I0(I_5147_0_a2_0_a2_0_a3_0_a2_44), + .I1(plm_fsm_ci_counter3_reg_rx_count[7]), + .LO(plm_fsm_ci_counter3_reg_rx_count_qxu[7]) + ); + defparam plm_fsm_ci_counter3_reg_tx_count_qxu_0_0_.INIT = 4'h7; + LUT2_L plm_fsm_ci_counter3_reg_tx_count_qxu_0_0_ ( + .I0(plm_fsm_ci_counter3_un1_enable_1_0_a2_0_a2_0_a3_0_a2_2), + .I1(plm_fsm_ci_counter3_reg_tx_count[0]), + .LO(plm_fsm_ci_counter3_reg_tx_count_qxu[0]) + ); + defparam plm_fsm_ci_counter3_reg_tx_count_qxu_0_1_.INIT = 4'h7; + LUT2_L plm_fsm_ci_counter3_reg_tx_count_qxu_0_1_ ( + .I0(plm_fsm_ci_counter3_un1_enable_1_0_a2_0_a2_0_a3_0_a2_2), + .I1(plm_fsm_ci_counter3_reg_tx_count[1]), + .LO(plm_fsm_ci_counter3_reg_tx_count_qxu[1]) + ); + defparam plm_fsm_ci_counter3_reg_tx_count_qxu_0_2_.INIT = 4'h7; + LUT2_L plm_fsm_ci_counter3_reg_tx_count_qxu_0_2_ ( + .I0(plm_fsm_ci_counter3_un1_enable_1_0_a2_0_a2_0_a3_0_a2_2), + .I1(plm_fsm_ci_counter3_reg_tx_count[2]), + .LO(plm_fsm_ci_counter3_reg_tx_count_qxu[2]) + ); + defparam plm_fsm_ci_counter3_reg_tx_count_qxu_0_3_.INIT = 8'h2E; + LUT3_L plm_fsm_ci_counter3_reg_tx_count_qxu_0_3_ ( + .I0(plm_fsm_ci_counter3_reg_tx_count17_0_a2_0_a2_0_a2_0_a3_0_a2_0), + .I1(plm_fsm_ci_counter3_un1_enable_1_0_a2_0_a2_0_a3_0_a2_2), + .I2(plm_fsm_ci_counter3_reg_tx_count[3]), + .LO(plm_fsm_ci_counter3_reg_tx_count_qxu[3]) + ); + defparam plm_fsm_ci_counter3_reg_tx_count_qxu_0_4_.INIT = 4'h7; + LUT2_L plm_fsm_ci_counter3_reg_tx_count_qxu_0_4_ ( + .I0(plm_fsm_ci_counter3_un1_enable_1_0_a2_0_a2_0_a3_0_a2_2), + .I1(plm_fsm_ci_counter3_reg_tx_count[4]), + .LO(plm_fsm_ci_counter3_reg_tx_count_qxu[4]) + ); + defparam plm_fsm_ci_counter3_reg_tx_count_qxu_0_5_.INIT = 4'h7; + LUT2_L plm_fsm_ci_counter3_reg_tx_count_qxu_0_5_ ( + .I0(plm_fsm_ci_counter3_un1_enable_1_0_a2_0_a2_0_a3_0_a2_2), + .I1(plm_fsm_ci_counter3_reg_tx_count[5]), + .LO(plm_fsm_ci_counter3_reg_tx_count_qxu[5]) + ); + defparam plm_fsm_ci_counter3_reg_tx_count_qxu_0_6_.INIT = 4'h7; + LUT2_L plm_fsm_ci_counter3_reg_tx_count_qxu_0_6_ ( + .I0(plm_fsm_ci_counter3_un1_enable_1_0_a2_0_a2_0_a3_0_a2_2), + .I1(plm_fsm_ci_counter3_reg_tx_count[6]), + .LO(plm_fsm_ci_counter3_reg_tx_count_qxu[6]) + ); + defparam plm_fsm_ci_counter3_reg_tx_count_qxu_0_7_.INIT = 4'h7; + LUT2_L plm_fsm_ci_counter3_reg_tx_count_qxu_0_7_ ( + .I0(plm_fsm_ci_counter3_un1_enable_1_0_a2_0_a2_0_a3_0_a2_2), + .I1(plm_fsm_ci_counter3_reg_tx_count[7]), + .LO(plm_fsm_ci_counter3_reg_tx_count_qxu[7]) + ); + GND plm_fsm_rl_timer_GND ( + .G(plm_fsm_rl_timer_GND_1920) + ); + MUXCY_L plm_fsm_rl_timer_reg_count_cry_0_ ( + .CI(plm_fsm_reg_state_13__76), + .DI(plm_fsm_rl_timer_GND_1920), + .LO(plm_fsm_rl_timer_reg_count_cry[0]), + .S(plm_fsm_rl_timer_reg_count_qxu[0]) + ); + XORCY plm_fsm_rl_timer_reg_count_s_0_ ( + .CI(plm_fsm_reg_state_13__76), + .LI(plm_fsm_rl_timer_reg_count_qxu[0]), + .O(plm_fsm_rl_timer_reg_count_s[0]) + ); + MUXCY_L plm_fsm_rl_timer_reg_count_cry_1_ ( + .CI(plm_fsm_rl_timer_reg_count_cry[0]), + .DI(plm_fsm_rl_timer_GND_1920), + .LO(plm_fsm_rl_timer_reg_count_cry[1]), + .S(plm_fsm_rl_timer_reg_count_qxu[1]) + ); + XORCY plm_fsm_rl_timer_reg_count_s_1_ ( + .CI(plm_fsm_rl_timer_reg_count_cry[0]), + .LI(plm_fsm_rl_timer_reg_count_qxu[1]), + .O(plm_fsm_rl_timer_reg_count_s[1]) + ); + MUXCY_L plm_fsm_rl_timer_reg_count_cry_2_ ( + .CI(plm_fsm_rl_timer_reg_count_cry[1]), + .DI(plm_fsm_rl_timer_GND_1920), + .LO(plm_fsm_rl_timer_reg_count_cry[2]), + .S(plm_fsm_rl_timer_reg_count_qxu[2]) + ); + XORCY plm_fsm_rl_timer_reg_count_s_2_ ( + .CI(plm_fsm_rl_timer_reg_count_cry[1]), + .LI(plm_fsm_rl_timer_reg_count_qxu[2]), + .O(plm_fsm_rl_timer_reg_count_s[2]) + ); + MUXCY_L plm_fsm_rl_timer_reg_count_cry_3_ ( + .CI(plm_fsm_rl_timer_reg_count_cry[2]), + .DI(plm_fsm_rl_timer_GND_1920), + .LO(plm_fsm_rl_timer_reg_count_cry[3]), + .S(plm_fsm_rl_timer_reg_count_qxu[3]) + ); + XORCY plm_fsm_rl_timer_reg_count_s_3_ ( + .CI(plm_fsm_rl_timer_reg_count_cry[2]), + .LI(plm_fsm_rl_timer_reg_count_qxu[3]), + .O(plm_fsm_rl_timer_reg_count_s[3]) + ); + MUXCY_L plm_fsm_rl_timer_reg_count_cry_4_ ( + .CI(plm_fsm_rl_timer_reg_count_cry[3]), + .DI(plm_fsm_rl_timer_GND_1920), + .LO(plm_fsm_rl_timer_reg_count_cry[4]), + .S(plm_fsm_rl_timer_reg_count_qxu[4]) + ); + XORCY plm_fsm_rl_timer_reg_count_s_4_ ( + .CI(plm_fsm_rl_timer_reg_count_cry[3]), + .LI(plm_fsm_rl_timer_reg_count_qxu[4]), + .O(plm_fsm_rl_timer_reg_count_s[4]) + ); + MUXCY_L plm_fsm_rl_timer_reg_count_cry_5_ ( + .CI(plm_fsm_rl_timer_reg_count_cry[4]), + .DI(plm_fsm_rl_timer_GND_1920), + .LO(plm_fsm_rl_timer_reg_count_cry[5]), + .S(plm_fsm_rl_timer_reg_count_qxu[5]) + ); + XORCY plm_fsm_rl_timer_reg_count_s_5_ ( + .CI(plm_fsm_rl_timer_reg_count_cry[4]), + .LI(plm_fsm_rl_timer_reg_count_qxu[5]), + .O(plm_fsm_rl_timer_reg_count_s[5]) + ); + MUXCY_L plm_fsm_rl_timer_reg_count_cry_6_ ( + .CI(plm_fsm_rl_timer_reg_count_cry[5]), + .DI(plm_fsm_rl_timer_GND_1920), + .LO(plm_fsm_rl_timer_reg_count_cry[6]), + .S(plm_fsm_rl_timer_reg_count_qxu[6]) + ); + XORCY plm_fsm_rl_timer_reg_count_s_6_ ( + .CI(plm_fsm_rl_timer_reg_count_cry[5]), + .LI(plm_fsm_rl_timer_reg_count_qxu[6]), + .O(plm_fsm_rl_timer_reg_count_s[6]) + ); + MUXCY_L plm_fsm_rl_timer_reg_count_cry_7_ ( + .CI(plm_fsm_rl_timer_reg_count_cry[6]), + .DI(plm_fsm_rl_timer_GND_1920), + .LO(plm_fsm_rl_timer_reg_count_cry[7]), + .S(plm_fsm_rl_timer_reg_count_qxu[7]) + ); + XORCY plm_fsm_rl_timer_reg_count_s_7_ ( + .CI(plm_fsm_rl_timer_reg_count_cry[6]), + .LI(plm_fsm_rl_timer_reg_count_qxu[7]), + .O(plm_fsm_rl_timer_reg_count_s[7]) + ); + MUXCY_L plm_fsm_rl_timer_reg_count_cry_8_ ( + .CI(plm_fsm_rl_timer_reg_count_cry[7]), + .DI(plm_fsm_rl_timer_GND_1920), + .LO(plm_fsm_rl_timer_reg_count_cry[8]), + .S(plm_fsm_rl_timer_reg_count_qxu[8]) + ); + XORCY plm_fsm_rl_timer_reg_count_s_8_ ( + .CI(plm_fsm_rl_timer_reg_count_cry[7]), + .LI(plm_fsm_rl_timer_reg_count_qxu[8]), + .O(plm_fsm_rl_timer_reg_count_s[8]) + ); + MUXCY_L plm_fsm_rl_timer_reg_count_cry_9_ ( + .CI(plm_fsm_rl_timer_reg_count_cry[8]), + .DI(plm_fsm_rl_timer_GND_1920), + .LO(plm_fsm_rl_timer_reg_count_cry[9]), + .S(plm_fsm_rl_timer_reg_count_qxu[9]) + ); + XORCY plm_fsm_rl_timer_reg_count_s_9_ ( + .CI(plm_fsm_rl_timer_reg_count_cry[8]), + .LI(plm_fsm_rl_timer_reg_count_qxu[9]), + .O(plm_fsm_rl_timer_reg_count_s[9]) + ); + MUXCY_L plm_fsm_rl_timer_reg_count_cry_10_ ( + .CI(plm_fsm_rl_timer_reg_count_cry[9]), + .DI(plm_fsm_rl_timer_GND_1920), + .LO(plm_fsm_rl_timer_reg_count_cry[10]), + .S(plm_fsm_rl_timer_reg_count_qxu[10]) + ); + XORCY plm_fsm_rl_timer_reg_count_s_10_ ( + .CI(plm_fsm_rl_timer_reg_count_cry[9]), + .LI(plm_fsm_rl_timer_reg_count_qxu[10]), + .O(plm_fsm_rl_timer_reg_count_s[10]) + ); + MUXCY_L plm_fsm_rl_timer_reg_count_cry_11_ ( + .CI(plm_fsm_rl_timer_reg_count_cry[10]), + .DI(plm_fsm_rl_timer_GND_1920), + .LO(plm_fsm_rl_timer_reg_count_cry[11]), + .S(plm_fsm_rl_timer_reg_count_qxu[11]) + ); + XORCY plm_fsm_rl_timer_reg_count_s_11_ ( + .CI(plm_fsm_rl_timer_reg_count_cry[10]), + .LI(plm_fsm_rl_timer_reg_count_qxu[11]), + .O(plm_fsm_rl_timer_reg_count_s[11]) + ); + MUXCY_L plm_fsm_rl_timer_reg_count_cry_12_ ( + .CI(plm_fsm_rl_timer_reg_count_cry[11]), + .DI(plm_fsm_rl_timer_GND_1920), + .LO(plm_fsm_rl_timer_reg_count_cry[12]), + .S(plm_fsm_rl_timer_reg_count_qxu[12]) + ); + XORCY plm_fsm_rl_timer_reg_count_s_12_ ( + .CI(plm_fsm_rl_timer_reg_count_cry[11]), + .LI(plm_fsm_rl_timer_reg_count_qxu[12]), + .O(plm_fsm_rl_timer_reg_count_s[12]) + ); + MUXCY_L plm_fsm_rl_timer_reg_count_cry_13_ ( + .CI(plm_fsm_rl_timer_reg_count_cry[12]), + .DI(plm_fsm_rl_timer_GND_1920), + .LO(plm_fsm_rl_timer_reg_count_cry[13]), + .S(plm_fsm_rl_timer_reg_count_qxu[13]) + ); + XORCY plm_fsm_rl_timer_reg_count_s_13_ ( + .CI(plm_fsm_rl_timer_reg_count_cry[12]), + .LI(plm_fsm_rl_timer_reg_count_qxu[13]), + .O(plm_fsm_rl_timer_reg_count_s[13]) + ); + MUXCY_L plm_fsm_rl_timer_reg_count_cry_14_ ( + .CI(plm_fsm_rl_timer_reg_count_cry[13]), + .DI(plm_fsm_rl_timer_GND_1920), + .LO(plm_fsm_rl_timer_reg_count_cry[14]), + .S(plm_fsm_rl_timer_reg_count_qxu[14]) + ); + XORCY plm_fsm_rl_timer_reg_count_s_14_ ( + .CI(plm_fsm_rl_timer_reg_count_cry[13]), + .LI(plm_fsm_rl_timer_reg_count_qxu[14]), + .O(plm_fsm_rl_timer_reg_count_s[14]) + ); + MUXCY_L plm_fsm_rl_timer_reg_count_cry_15_ ( + .CI(plm_fsm_rl_timer_reg_count_cry[14]), + .DI(plm_fsm_rl_timer_GND_1920), + .LO(plm_fsm_rl_timer_reg_count_cry[15]), + .S(plm_fsm_rl_timer_reg_count_qxu[15]) + ); + XORCY plm_fsm_rl_timer_reg_count_s_15_ ( + .CI(plm_fsm_rl_timer_reg_count_cry[14]), + .LI(plm_fsm_rl_timer_reg_count_qxu[15]), + .O(plm_fsm_rl_timer_reg_count_s[15]) + ); + MUXCY_L plm_fsm_rl_timer_reg_count_cry_16_ ( + .CI(plm_fsm_rl_timer_reg_count_cry[15]), + .DI(plm_fsm_rl_timer_GND_1920), + .LO(plm_fsm_rl_timer_reg_count_cry[16]), + .S(plm_fsm_rl_timer_reg_count_qxu[16]) + ); + XORCY plm_fsm_rl_timer_reg_count_s_16_ ( + .CI(plm_fsm_rl_timer_reg_count_cry[15]), + .LI(plm_fsm_rl_timer_reg_count_qxu[16]), + .O(plm_fsm_rl_timer_reg_count_s[16]) + ); + MUXCY_L plm_fsm_rl_timer_reg_count_cry_17_ ( + .CI(plm_fsm_rl_timer_reg_count_cry[16]), + .DI(plm_fsm_rl_timer_GND_1920), + .LO(plm_fsm_rl_timer_reg_count_cry[17]), + .S(plm_fsm_rl_timer_reg_count_qxu[17]) + ); + XORCY plm_fsm_rl_timer_reg_count_s_17_ ( + .CI(plm_fsm_rl_timer_reg_count_cry[16]), + .LI(plm_fsm_rl_timer_reg_count_qxu[17]), + .O(plm_fsm_rl_timer_reg_count_s[17]) + ); + MUXCY_L plm_fsm_rl_timer_reg_count_cry_18_ ( + .CI(plm_fsm_rl_timer_reg_count_cry[17]), + .DI(plm_fsm_rl_timer_GND_1920), + .LO(plm_fsm_rl_timer_reg_count_cry[18]), + .S(plm_fsm_rl_timer_reg_count_qxu[18]) + ); + XORCY plm_fsm_rl_timer_reg_count_s_18_ ( + .CI(plm_fsm_rl_timer_reg_count_cry[17]), + .LI(plm_fsm_rl_timer_reg_count_qxu[18]), + .O(plm_fsm_rl_timer_reg_count_s[18]) + ); + MUXCY_L plm_fsm_rl_timer_reg_count_cry_19_ ( + .CI(plm_fsm_rl_timer_reg_count_cry[18]), + .DI(plm_fsm_rl_timer_GND_1920), + .LO(plm_fsm_rl_timer_reg_count_cry[19]), + .S(plm_fsm_rl_timer_reg_count_qxu[19]) + ); + XORCY plm_fsm_rl_timer_reg_count_s_19_ ( + .CI(plm_fsm_rl_timer_reg_count_cry[18]), + .LI(plm_fsm_rl_timer_reg_count_qxu[19]), + .O(plm_fsm_rl_timer_reg_count_s[19]) + ); + MUXCY_L plm_fsm_rl_timer_reg_count_cry_20_ ( + .CI(plm_fsm_rl_timer_reg_count_cry[19]), + .DI(plm_fsm_rl_timer_GND_1920), + .LO(plm_fsm_rl_timer_reg_count_cry[20]), + .S(plm_fsm_rl_timer_reg_count_qxu[20]) + ); + XORCY plm_fsm_rl_timer_reg_count_s_20_ ( + .CI(plm_fsm_rl_timer_reg_count_cry[19]), + .LI(plm_fsm_rl_timer_reg_count_qxu[20]), + .O(plm_fsm_rl_timer_reg_count_s[20]) + ); + MUXCY_L plm_fsm_rl_timer_reg_count_cry_21_ ( + .CI(plm_fsm_rl_timer_reg_count_cry[20]), + .DI(plm_fsm_rl_timer_GND_1920), + .LO(plm_fsm_rl_timer_reg_count_cry[21]), + .S(plm_fsm_rl_timer_reg_count_qxu[21]) + ); + XORCY plm_fsm_rl_timer_reg_count_s_21_ ( + .CI(plm_fsm_rl_timer_reg_count_cry[20]), + .LI(plm_fsm_rl_timer_reg_count_qxu[21]), + .O(plm_fsm_rl_timer_reg_count_s[21]) + ); + XORCY plm_fsm_rl_timer_reg_count_s_22_ ( + .CI(plm_fsm_rl_timer_reg_count_cry[21]), + .LI(plm_fsm_rl_timer_reg_count_qxu[22]), + .O(plm_fsm_rl_timer_reg_count_s[22]) + ); + defparam plm_fsm_rl_timer_count_i_m3_i_m3_0_20_.INIT = 8'hD8; + LUT3_L plm_fsm_rl_timer_count_i_m3_i_m3_0_20_ ( + .I0(cfg_cfg_6102[507]), + .I1(plm_fsm_rl_timer_reg_count[12]), + .I2(plm_fsm_rl_timer_reg_count[20]), + .LO(plm_fsm_rl_timer_N_63713) + ); + defparam plm_fsm_rl_timer_un3_expired_24ms.INIT = 16'hA280; + LUT4_L plm_fsm_rl_timer_un3_expired_24ms ( + .I0(plm_fsm_rl_timer_N_63713), + .I1(cfg_cfg_6102[507]), + .I2(plm_fsm_rl_timer_reg_count[13]), + .I3(plm_fsm_rl_timer_reg_count[21]), + .LO(plm_fsm_rl_timer_N_38053) + ); + defparam plm_fsm_rl_timer_un1_expired_24ms.INIT = 16'h0415; + LUT4 plm_fsm_rl_timer_un1_expired_24ms ( + .I0(plm_fsm_rl_timer_N_38053), + .I1(cfg_cfg_6102[507]), + .I2(plm_fsm_rl_timer_reg_count[14]), + .I3(plm_fsm_rl_timer_reg_count[22]), + .O(plm_fsm_N_38054) + ); + FDC plm_fsm_rl_timer_reg_count_22_ ( + .C(mgt_clk), + .D(plm_fsm_rl_timer_reg_count_s[22]), + .Q(plm_fsm_rl_timer_reg_count[22]), + .CLR(plm_rst) + ); + FDC plm_fsm_rl_timer_reg_count_21_ ( + .C(mgt_clk), + .D(plm_fsm_rl_timer_reg_count_s[21]), + .Q(plm_fsm_rl_timer_reg_count[21]), + .CLR(plm_rst) + ); + FDC plm_fsm_rl_timer_reg_count_20_ ( + .C(mgt_clk), + .D(plm_fsm_rl_timer_reg_count_s[20]), + .Q(plm_fsm_rl_timer_reg_count[20]), + .CLR(plm_rst) + ); + FDC plm_fsm_rl_timer_reg_count_19_ ( + .C(mgt_clk), + .D(plm_fsm_rl_timer_reg_count_s[19]), + .Q(plm_fsm_rl_timer_reg_count[19]), + .CLR(plm_rst) + ); + FDC plm_fsm_rl_timer_reg_count_18_ ( + .C(mgt_clk), + .D(plm_fsm_rl_timer_reg_count_s[18]), + .Q(plm_fsm_rl_timer_reg_count[18]), + .CLR(plm_rst) + ); + FDC plm_fsm_rl_timer_reg_count_17_ ( + .C(mgt_clk), + .D(plm_fsm_rl_timer_reg_count_s[17]), + .Q(plm_fsm_rl_timer_reg_count[17]), + .CLR(plm_rst) + ); + FDC plm_fsm_rl_timer_reg_count_16_ ( + .C(mgt_clk), + .D(plm_fsm_rl_timer_reg_count_s[16]), + .Q(plm_fsm_rl_timer_reg_count[16]), + .CLR(plm_rst) + ); + FDC plm_fsm_rl_timer_reg_count_15_ ( + .C(mgt_clk), + .D(plm_fsm_rl_timer_reg_count_s[15]), + .Q(plm_fsm_rl_timer_reg_count[15]), + .CLR(plm_rst) + ); + FDC plm_fsm_rl_timer_reg_count_14_ ( + .C(mgt_clk), + .D(plm_fsm_rl_timer_reg_count_s[14]), + .Q(plm_fsm_rl_timer_reg_count[14]), + .CLR(plm_rst) + ); + FDC plm_fsm_rl_timer_reg_count_13_ ( + .C(mgt_clk), + .D(plm_fsm_rl_timer_reg_count_s[13]), + .Q(plm_fsm_rl_timer_reg_count[13]), + .CLR(plm_rst) + ); + FDC plm_fsm_rl_timer_reg_count_12_ ( + .C(mgt_clk), + .D(plm_fsm_rl_timer_reg_count_s[12]), + .Q(plm_fsm_rl_timer_reg_count[12]), + .CLR(plm_rst) + ); + FDC plm_fsm_rl_timer_reg_count_11_ ( + .C(mgt_clk), + .D(plm_fsm_rl_timer_reg_count_s[11]), + .Q(plm_fsm_rl_timer_reg_count[11]), + .CLR(plm_rst) + ); + FDC plm_fsm_rl_timer_reg_count_10_ ( + .C(mgt_clk), + .D(plm_fsm_rl_timer_reg_count_s[10]), + .Q(plm_fsm_rl_timer_reg_count[10]), + .CLR(plm_rst) + ); + FDC plm_fsm_rl_timer_reg_count_9_ ( + .C(mgt_clk), + .D(plm_fsm_rl_timer_reg_count_s[9]), + .Q(plm_fsm_rl_timer_reg_count[9]), + .CLR(plm_rst) + ); + FDC plm_fsm_rl_timer_reg_count_8_ ( + .C(mgt_clk), + .D(plm_fsm_rl_timer_reg_count_s[8]), + .Q(plm_fsm_rl_timer_reg_count[8]), + .CLR(plm_rst) + ); + FDC plm_fsm_rl_timer_reg_count_7_ ( + .C(mgt_clk), + .D(plm_fsm_rl_timer_reg_count_s[7]), + .Q(plm_fsm_rl_timer_reg_count[7]), + .CLR(plm_rst) + ); + FDC plm_fsm_rl_timer_reg_count_6_ ( + .C(mgt_clk), + .D(plm_fsm_rl_timer_reg_count_s[6]), + .Q(plm_fsm_rl_timer_reg_count[6]), + .CLR(plm_rst) + ); + FDC plm_fsm_rl_timer_reg_count_5_ ( + .C(mgt_clk), + .D(plm_fsm_rl_timer_reg_count_s[5]), + .Q(plm_fsm_rl_timer_reg_count[5]), + .CLR(plm_rst) + ); + FDC plm_fsm_rl_timer_reg_count_4_ ( + .C(mgt_clk), + .D(plm_fsm_rl_timer_reg_count_s[4]), + .Q(plm_fsm_rl_timer_reg_count[4]), + .CLR(plm_rst) + ); + FDC plm_fsm_rl_timer_reg_count_3_ ( + .C(mgt_clk), + .D(plm_fsm_rl_timer_reg_count_s[3]), + .Q(plm_fsm_rl_timer_reg_count[3]), + .CLR(plm_rst) + ); + FDC plm_fsm_rl_timer_reg_count_2_ ( + .C(mgt_clk), + .D(plm_fsm_rl_timer_reg_count_s[2]), + .Q(plm_fsm_rl_timer_reg_count[2]), + .CLR(plm_rst) + ); + FDC plm_fsm_rl_timer_reg_count_1_ ( + .C(mgt_clk), + .D(plm_fsm_rl_timer_reg_count_s[1]), + .Q(plm_fsm_rl_timer_reg_count[1]), + .CLR(plm_rst) + ); + FDC plm_fsm_rl_timer_reg_count_0_ ( + .C(mgt_clk), + .D(plm_fsm_rl_timer_reg_count_s[0]), + .Q(plm_fsm_rl_timer_reg_count[0]), + .CLR(plm_rst) + ); + defparam plm_fsm_rl_timer_reg_count_qxu_0_0_.INIT = 4'h8; + LUT2_L plm_fsm_rl_timer_reg_count_qxu_0_0_ ( + .I0(plm_fsm_reg_state_13__76), + .I1(plm_fsm_rl_timer_reg_count[0]), + .LO(plm_fsm_rl_timer_reg_count_qxu[0]) + ); + defparam plm_fsm_rl_timer_reg_count_qxu_0_1_.INIT = 4'h8; + LUT2_L plm_fsm_rl_timer_reg_count_qxu_0_1_ ( + .I0(plm_fsm_reg_state_13__76), + .I1(plm_fsm_rl_timer_reg_count[1]), + .LO(plm_fsm_rl_timer_reg_count_qxu[1]) + ); + defparam plm_fsm_rl_timer_reg_count_qxu_0_2_.INIT = 4'h8; + LUT2_L plm_fsm_rl_timer_reg_count_qxu_0_2_ ( + .I0(plm_fsm_reg_state_13__76), + .I1(plm_fsm_rl_timer_reg_count[2]), + .LO(plm_fsm_rl_timer_reg_count_qxu[2]) + ); + defparam plm_fsm_rl_timer_reg_count_qxu_0_3_.INIT = 4'h8; + LUT2_L plm_fsm_rl_timer_reg_count_qxu_0_3_ ( + .I0(plm_fsm_reg_state_13__76), + .I1(plm_fsm_rl_timer_reg_count[3]), + .LO(plm_fsm_rl_timer_reg_count_qxu[3]) + ); + defparam plm_fsm_rl_timer_reg_count_qxu_0_4_.INIT = 4'h8; + LUT2_L plm_fsm_rl_timer_reg_count_qxu_0_4_ ( + .I0(plm_fsm_reg_state_13__76), + .I1(plm_fsm_rl_timer_reg_count[4]), + .LO(plm_fsm_rl_timer_reg_count_qxu[4]) + ); + defparam plm_fsm_rl_timer_reg_count_qxu_0_5_.INIT = 4'h8; + LUT2_L plm_fsm_rl_timer_reg_count_qxu_0_5_ ( + .I0(plm_fsm_reg_state_13__76), + .I1(plm_fsm_rl_timer_reg_count[5]), + .LO(plm_fsm_rl_timer_reg_count_qxu[5]) + ); + defparam plm_fsm_rl_timer_reg_count_qxu_0_6_.INIT = 4'h8; + LUT2_L plm_fsm_rl_timer_reg_count_qxu_0_6_ ( + .I0(plm_fsm_reg_state_13__76), + .I1(plm_fsm_rl_timer_reg_count[6]), + .LO(plm_fsm_rl_timer_reg_count_qxu[6]) + ); + defparam plm_fsm_rl_timer_reg_count_qxu_0_7_.INIT = 4'h8; + LUT2_L plm_fsm_rl_timer_reg_count_qxu_0_7_ ( + .I0(plm_fsm_reg_state_13__76), + .I1(plm_fsm_rl_timer_reg_count[7]), + .LO(plm_fsm_rl_timer_reg_count_qxu[7]) + ); + defparam plm_fsm_rl_timer_reg_count_qxu_0_8_.INIT = 4'h8; + LUT2_L plm_fsm_rl_timer_reg_count_qxu_0_8_ ( + .I0(plm_fsm_reg_state_13__76), + .I1(plm_fsm_rl_timer_reg_count[8]), + .LO(plm_fsm_rl_timer_reg_count_qxu[8]) + ); + defparam plm_fsm_rl_timer_reg_count_qxu_0_9_.INIT = 4'h8; + LUT2_L plm_fsm_rl_timer_reg_count_qxu_0_9_ ( + .I0(plm_fsm_reg_state_13__76), + .I1(plm_fsm_rl_timer_reg_count[9]), + .LO(plm_fsm_rl_timer_reg_count_qxu[9]) + ); + defparam plm_fsm_rl_timer_reg_count_qxu_0_10_.INIT = 4'h8; + LUT2_L plm_fsm_rl_timer_reg_count_qxu_0_10_ ( + .I0(plm_fsm_reg_state_13__76), + .I1(plm_fsm_rl_timer_reg_count[10]), + .LO(plm_fsm_rl_timer_reg_count_qxu[10]) + ); + defparam plm_fsm_rl_timer_reg_count_qxu_0_11_.INIT = 4'h8; + LUT2_L plm_fsm_rl_timer_reg_count_qxu_0_11_ ( + .I0(plm_fsm_reg_state_13__76), + .I1(plm_fsm_rl_timer_reg_count[11]), + .LO(plm_fsm_rl_timer_reg_count_qxu[11]) + ); + defparam plm_fsm_rl_timer_reg_count_qxu_0_12_.INIT = 4'h8; + LUT2_L plm_fsm_rl_timer_reg_count_qxu_0_12_ ( + .I0(plm_fsm_reg_state_13__76), + .I1(plm_fsm_rl_timer_reg_count[12]), + .LO(plm_fsm_rl_timer_reg_count_qxu[12]) + ); + defparam plm_fsm_rl_timer_reg_count_qxu_0_13_.INIT = 4'h8; + LUT2_L plm_fsm_rl_timer_reg_count_qxu_0_13_ ( + .I0(plm_fsm_reg_state_13__76), + .I1(plm_fsm_rl_timer_reg_count[13]), + .LO(plm_fsm_rl_timer_reg_count_qxu[13]) + ); + defparam plm_fsm_rl_timer_reg_count_qxu_0_14_.INIT = 4'h8; + LUT2_L plm_fsm_rl_timer_reg_count_qxu_0_14_ ( + .I0(plm_fsm_reg_state_13__76), + .I1(plm_fsm_rl_timer_reg_count[14]), + .LO(plm_fsm_rl_timer_reg_count_qxu[14]) + ); + defparam plm_fsm_rl_timer_reg_count_qxu_0_15_.INIT = 4'h8; + LUT2_L plm_fsm_rl_timer_reg_count_qxu_0_15_ ( + .I0(plm_fsm_reg_state_13__76), + .I1(plm_fsm_rl_timer_reg_count[15]), + .LO(plm_fsm_rl_timer_reg_count_qxu[15]) + ); + defparam plm_fsm_rl_timer_reg_count_qxu_0_16_.INIT = 4'h8; + LUT2_L plm_fsm_rl_timer_reg_count_qxu_0_16_ ( + .I0(plm_fsm_reg_state_13__76), + .I1(plm_fsm_rl_timer_reg_count[16]), + .LO(plm_fsm_rl_timer_reg_count_qxu[16]) + ); + defparam plm_fsm_rl_timer_reg_count_qxu_0_17_.INIT = 4'h8; + LUT2_L plm_fsm_rl_timer_reg_count_qxu_0_17_ ( + .I0(plm_fsm_reg_state_13__76), + .I1(plm_fsm_rl_timer_reg_count[17]), + .LO(plm_fsm_rl_timer_reg_count_qxu[17]) + ); + defparam plm_fsm_rl_timer_reg_count_qxu_0_18_.INIT = 4'h8; + LUT2_L plm_fsm_rl_timer_reg_count_qxu_0_18_ ( + .I0(plm_fsm_reg_state_13__76), + .I1(plm_fsm_rl_timer_reg_count[18]), + .LO(plm_fsm_rl_timer_reg_count_qxu[18]) + ); + defparam plm_fsm_rl_timer_reg_count_qxu_0_19_.INIT = 4'h8; + LUT2_L plm_fsm_rl_timer_reg_count_qxu_0_19_ ( + .I0(plm_fsm_reg_state_13__76), + .I1(plm_fsm_rl_timer_reg_count[19]), + .LO(plm_fsm_rl_timer_reg_count_qxu[19]) + ); + defparam plm_fsm_rl_timer_reg_count_qxu_0_20_.INIT = 4'h8; + LUT2_L plm_fsm_rl_timer_reg_count_qxu_0_20_ ( + .I0(plm_fsm_reg_state_13__76), + .I1(plm_fsm_rl_timer_reg_count[20]), + .LO(plm_fsm_rl_timer_reg_count_qxu[20]) + ); + defparam plm_fsm_rl_timer_reg_count_qxu_0_21_.INIT = 4'h8; + LUT2_L plm_fsm_rl_timer_reg_count_qxu_0_21_ ( + .I0(plm_fsm_reg_state_13__76), + .I1(plm_fsm_rl_timer_reg_count[21]), + .LO(plm_fsm_rl_timer_reg_count_qxu[21]) + ); + defparam plm_fsm_rl_timer_reg_count_qxu_0_22_.INIT = 4'h8; + LUT2_L plm_fsm_rl_timer_reg_count_qxu_0_22_ ( + .I0(plm_fsm_reg_state_13__76), + .I1(plm_fsm_rl_timer_reg_count[22]), + .LO(plm_fsm_rl_timer_reg_count_qxu[22]) + ); + VCC plm_fsm_rl_counterx_VCC ( + .P(plm_fsm_rl_counterx_VCC_1921) + ); + MUXCY_L plm_fsm_rl_counterx_reg_rx_count_cry_0_ ( + .CI(plm_fsm_rl_counterx_N_61252_i), + .DI(plm_fsm_rl_counterx_VCC_1921), + .LO(plm_fsm_rl_counterx_reg_rx_count_cry[0]), + .S(plm_fsm_rl_counterx_reg_rx_count_qxu[0]) + ); + XORCY plm_fsm_rl_counterx_reg_rx_count_s_0_ ( + .CI(plm_fsm_rl_counterx_N_61252_i), + .LI(plm_fsm_rl_counterx_reg_rx_count_qxu[0]), + .O(plm_fsm_rl_counterx_reg_rx_count_s[0]) + ); + MUXCY_L plm_fsm_rl_counterx_reg_rx_count_cry_1_ ( + .CI(plm_fsm_rl_counterx_reg_rx_count_cry[0]), + .DI(plm_fsm_rl_counterx_VCC_1921), + .LO(plm_fsm_rl_counterx_reg_rx_count_cry[1]), + .S(plm_fsm_rl_counterx_reg_rx_count_qxu[1]) + ); + XORCY plm_fsm_rl_counterx_reg_rx_count_s_1_ ( + .CI(plm_fsm_rl_counterx_reg_rx_count_cry[0]), + .LI(plm_fsm_rl_counterx_reg_rx_count_qxu[1]), + .O(plm_fsm_rl_counterx_reg_rx_count_s[1]) + ); + MUXCY_L plm_fsm_rl_counterx_reg_rx_count_cry_2_ ( + .CI(plm_fsm_rl_counterx_reg_rx_count_cry[1]), + .DI(plm_fsm_rl_counterx_VCC_1921), + .LO(plm_fsm_rl_counterx_reg_rx_count_cry[2]), + .S(plm_fsm_rl_counterx_reg_rx_count_qxu[2]) + ); + XORCY plm_fsm_rl_counterx_reg_rx_count_s_2_ ( + .CI(plm_fsm_rl_counterx_reg_rx_count_cry[1]), + .LI(plm_fsm_rl_counterx_reg_rx_count_qxu[2]), + .O(plm_fsm_rl_counterx_reg_rx_count_s[2]) + ); + MUXCY_L plm_fsm_rl_counterx_reg_rx_count_cry_3_ ( + .CI(plm_fsm_rl_counterx_reg_rx_count_cry[2]), + .DI(plm_fsm_rl_counterx_VCC_1921), + .LO(plm_fsm_rl_counterx_reg_rx_count_cry[3]), + .S(plm_fsm_rl_counterx_reg_rx_count_qxu[3]) + ); + XORCY plm_fsm_rl_counterx_reg_rx_count_s_3_ ( + .CI(plm_fsm_rl_counterx_reg_rx_count_cry[2]), + .LI(plm_fsm_rl_counterx_reg_rx_count_qxu[3]), + .O(plm_fsm_rl_counterx_reg_rx_count_s[3]) + ); + MUXCY_L plm_fsm_rl_counterx_reg_rx_count_cry_4_ ( + .CI(plm_fsm_rl_counterx_reg_rx_count_cry[3]), + .DI(plm_fsm_rl_counterx_VCC_1921), + .LO(plm_fsm_rl_counterx_reg_rx_count_cry[4]), + .S(plm_fsm_rl_counterx_reg_rx_count_qxu[4]) + ); + XORCY plm_fsm_rl_counterx_reg_rx_count_s_4_ ( + .CI(plm_fsm_rl_counterx_reg_rx_count_cry[3]), + .LI(plm_fsm_rl_counterx_reg_rx_count_qxu[4]), + .O(plm_fsm_rl_counterx_reg_rx_count_s[4]) + ); + MUXCY_L plm_fsm_rl_counterx_reg_rx_count_cry_5_ ( + .CI(plm_fsm_rl_counterx_reg_rx_count_cry[4]), + .DI(plm_fsm_rl_counterx_VCC_1921), + .LO(plm_fsm_rl_counterx_reg_rx_count_cry[5]), + .S(plm_fsm_rl_counterx_reg_rx_count_qxu[5]) + ); + XORCY plm_fsm_rl_counterx_reg_rx_count_s_5_ ( + .CI(plm_fsm_rl_counterx_reg_rx_count_cry[4]), + .LI(plm_fsm_rl_counterx_reg_rx_count_qxu[5]), + .O(plm_fsm_rl_counterx_reg_rx_count_s[5]) + ); + MUXCY_L plm_fsm_rl_counterx_reg_rx_count_cry_6_ ( + .CI(plm_fsm_rl_counterx_reg_rx_count_cry[5]), + .DI(plm_fsm_rl_counterx_VCC_1921), + .LO(plm_fsm_rl_counterx_reg_rx_count_cry[6]), + .S(plm_fsm_rl_counterx_reg_rx_count_qxu[6]) + ); + XORCY plm_fsm_rl_counterx_reg_rx_count_s_6_ ( + .CI(plm_fsm_rl_counterx_reg_rx_count_cry[5]), + .LI(plm_fsm_rl_counterx_reg_rx_count_qxu[6]), + .O(plm_fsm_rl_counterx_reg_rx_count_s[6]) + ); + XORCY plm_fsm_rl_counterx_reg_rx_count_s_7_ ( + .CI(plm_fsm_rl_counterx_reg_rx_count_cry[6]), + .LI(plm_fsm_rl_counterx_reg_rx_count_qxu[7]), + .O(plm_fsm_rl_counterx_reg_rx_count_s[7]) + ); + MUXCY_L plm_fsm_rl_counterx_reg_tx_count_cry_0_ ( + .CI(plm_fsm_rl_counterx_un1_enable_1_i_1925), + .DI(plm_fsm_rl_counterx_VCC_1921), + .LO(plm_fsm_rl_counterx_reg_tx_count_cry[0]), + .S(plm_fsm_rl_counterx_reg_tx_count_qxu[0]) + ); + XORCY plm_fsm_rl_counterx_reg_tx_count_s_0_ ( + .CI(plm_fsm_rl_counterx_un1_enable_1_i_1925), + .LI(plm_fsm_rl_counterx_reg_tx_count_qxu[0]), + .O(plm_fsm_rl_counterx_reg_tx_count_s[0]) + ); + MUXCY_L plm_fsm_rl_counterx_reg_tx_count_cry_1_ ( + .CI(plm_fsm_rl_counterx_reg_tx_count_cry[0]), + .DI(plm_fsm_rl_counterx_VCC_1921), + .LO(plm_fsm_rl_counterx_reg_tx_count_cry[1]), + .S(plm_fsm_rl_counterx_reg_tx_count_qxu[1]) + ); + XORCY plm_fsm_rl_counterx_reg_tx_count_s_1_ ( + .CI(plm_fsm_rl_counterx_reg_tx_count_cry[0]), + .LI(plm_fsm_rl_counterx_reg_tx_count_qxu[1]), + .O(plm_fsm_rl_counterx_reg_tx_count_s[1]) + ); + MUXCY_L plm_fsm_rl_counterx_reg_tx_count_cry_2_ ( + .CI(plm_fsm_rl_counterx_reg_tx_count_cry[1]), + .DI(plm_fsm_rl_counterx_VCC_1921), + .LO(plm_fsm_rl_counterx_reg_tx_count_cry[2]), + .S(plm_fsm_rl_counterx_reg_tx_count_qxu[2]) + ); + XORCY plm_fsm_rl_counterx_reg_tx_count_s_2_ ( + .CI(plm_fsm_rl_counterx_reg_tx_count_cry[1]), + .LI(plm_fsm_rl_counterx_reg_tx_count_qxu[2]), + .O(plm_fsm_rl_counterx_reg_tx_count_s[2]) + ); + MUXCY_L plm_fsm_rl_counterx_reg_tx_count_cry_3_ ( + .CI(plm_fsm_rl_counterx_reg_tx_count_cry[2]), + .DI(plm_fsm_rl_counterx_VCC_1921), + .LO(plm_fsm_rl_counterx_reg_tx_count_cry[3]), + .S(plm_fsm_rl_counterx_reg_tx_count_qxu[3]) + ); + XORCY plm_fsm_rl_counterx_reg_tx_count_s_3_ ( + .CI(plm_fsm_rl_counterx_reg_tx_count_cry[2]), + .LI(plm_fsm_rl_counterx_reg_tx_count_qxu[3]), + .O(plm_fsm_rl_counterx_reg_tx_count_s[3]) + ); + MUXCY_L plm_fsm_rl_counterx_reg_tx_count_cry_4_ ( + .CI(plm_fsm_rl_counterx_reg_tx_count_cry[3]), + .DI(plm_fsm_rl_counterx_VCC_1921), + .LO(plm_fsm_rl_counterx_reg_tx_count_cry[4]), + .S(plm_fsm_rl_counterx_reg_tx_count_qxu[4]) + ); + XORCY plm_fsm_rl_counterx_reg_tx_count_s_4_ ( + .CI(plm_fsm_rl_counterx_reg_tx_count_cry[3]), + .LI(plm_fsm_rl_counterx_reg_tx_count_qxu[4]), + .O(plm_fsm_rl_counterx_reg_tx_count_s[4]) + ); + MUXCY_L plm_fsm_rl_counterx_reg_tx_count_cry_5_ ( + .CI(plm_fsm_rl_counterx_reg_tx_count_cry[4]), + .DI(plm_fsm_rl_counterx_VCC_1921), + .LO(plm_fsm_rl_counterx_reg_tx_count_cry[5]), + .S(plm_fsm_rl_counterx_reg_tx_count_qxu[5]) + ); + XORCY plm_fsm_rl_counterx_reg_tx_count_s_5_ ( + .CI(plm_fsm_rl_counterx_reg_tx_count_cry[4]), + .LI(plm_fsm_rl_counterx_reg_tx_count_qxu[5]), + .O(plm_fsm_rl_counterx_reg_tx_count_s[5]) + ); + MUXCY_L plm_fsm_rl_counterx_reg_tx_count_cry_6_ ( + .CI(plm_fsm_rl_counterx_reg_tx_count_cry[5]), + .DI(plm_fsm_rl_counterx_VCC_1921), + .LO(plm_fsm_rl_counterx_reg_tx_count_cry[6]), + .S(plm_fsm_rl_counterx_reg_tx_count_qxu[6]) + ); + XORCY plm_fsm_rl_counterx_reg_tx_count_s_6_ ( + .CI(plm_fsm_rl_counterx_reg_tx_count_cry[5]), + .LI(plm_fsm_rl_counterx_reg_tx_count_qxu[6]), + .O(plm_fsm_rl_counterx_reg_tx_count_s[6]) + ); + MUXCY_L plm_fsm_rl_counterx_reg_tx_count_cry_7_ ( + .CI(plm_fsm_rl_counterx_reg_tx_count_cry[6]), + .DI(plm_fsm_rl_counterx_VCC_1921), + .LO(plm_fsm_rl_counterx_reg_tx_count_cry[7]), + .S(plm_fsm_rl_counterx_reg_tx_count_qxu[7]) + ); + XORCY plm_fsm_rl_counterx_reg_tx_count_s_7_ ( + .CI(plm_fsm_rl_counterx_reg_tx_count_cry[6]), + .LI(plm_fsm_rl_counterx_reg_tx_count_qxu[7]), + .O(plm_fsm_rl_counterx_reg_tx_count_s[7]) + ); + MUXCY_L plm_fsm_rl_counterx_reg_tx_count_cry_8_ ( + .CI(plm_fsm_rl_counterx_reg_tx_count_cry[7]), + .DI(plm_fsm_rl_counterx_VCC_1921), + .LO(plm_fsm_rl_counterx_reg_tx_count_cry[8]), + .S(plm_fsm_rl_counterx_reg_tx_count_qxu[8]) + ); + XORCY plm_fsm_rl_counterx_reg_tx_count_s_8_ ( + .CI(plm_fsm_rl_counterx_reg_tx_count_cry[7]), + .LI(plm_fsm_rl_counterx_reg_tx_count_qxu[8]), + .O(plm_fsm_rl_counterx_reg_tx_count_s[8]) + ); + MUXCY_L plm_fsm_rl_counterx_reg_tx_count_cry_9_ ( + .CI(plm_fsm_rl_counterx_reg_tx_count_cry[8]), + .DI(plm_fsm_rl_counterx_VCC_1921), + .LO(plm_fsm_rl_counterx_reg_tx_count_cry[9]), + .S(plm_fsm_rl_counterx_reg_tx_count_qxu[9]) + ); + XORCY plm_fsm_rl_counterx_reg_tx_count_s_9_ ( + .CI(plm_fsm_rl_counterx_reg_tx_count_cry[8]), + .LI(plm_fsm_rl_counterx_reg_tx_count_qxu[9]), + .O(plm_fsm_rl_counterx_reg_tx_count_s[9]) + ); + MUXCY_L plm_fsm_rl_counterx_reg_tx_count_cry_10_ ( + .CI(plm_fsm_rl_counterx_reg_tx_count_cry[9]), + .DI(plm_fsm_rl_counterx_VCC_1921), + .LO(plm_fsm_rl_counterx_reg_tx_count_cry[10]), + .S(plm_fsm_rl_counterx_reg_tx_count_qxu[10]) + ); + XORCY plm_fsm_rl_counterx_reg_tx_count_s_10_ ( + .CI(plm_fsm_rl_counterx_reg_tx_count_cry[9]), + .LI(plm_fsm_rl_counterx_reg_tx_count_qxu[10]), + .O(plm_fsm_rl_counterx_reg_tx_count_s[10]) + ); + XORCY plm_fsm_rl_counterx_reg_tx_count_s_11_ ( + .CI(plm_fsm_rl_counterx_reg_tx_count_cry[10]), + .LI(plm_fsm_rl_counterx_reg_tx_count_qxu[11]), + .O(plm_fsm_rl_counterx_reg_tx_count_s[11]) + ); + defparam plm_fsm_rl_counterx_loadable_rx_counter_un1_reg_rx_expired_0_a2_0_a2_0_a3_0_a2.INIT = 4'h2; + LUT2 plm_fsm_rl_counterx_loadable_rx_counter_un1_reg_rx_expired_0_a2_0_a2_0_a3_0_a2 ( + .I0(plm_fsm_reg_state_13__76), + .I1(plm_fsm_rl_counterx_reg_rx_expired_1924), + .O(plm_fsm_rl_counterx_un1_reg_rx_expired_0_a2_0_a2_0_a3_0_a2) + ); + defparam plm_fsm_rl_counterx_un1_enable_1_0_a2_0_a2_0_a3_0_a2.INIT = 4'h2; + LUT2 plm_fsm_rl_counterx_un1_enable_1_0_a2_0_a2_0_a3_0_a2 ( + .I0(plm_fsm_reg_state_13__76), + .I1(plm_fsm_rl_counterx_reg_tx_expired_1923), + .O(plm_fsm_rl_counterx_un1_enable_1) + ); + defparam plm_fsm_rl_counterx_loadable_rx_counter_un1_reg_rx_count_0_a2_4.INIT = 16'h0001; + LUT4 plm_fsm_rl_counterx_loadable_rx_counter_un1_reg_rx_count_0_a2_4 ( + .I0(plm_fsm_rl_counterx_reg_rx_count[0]), + .I1(plm_fsm_rl_counterx_reg_rx_count[1]), + .I2(plm_fsm_rl_counterx_reg_rx_count[2]), + .I3(plm_fsm_rl_counterx_reg_rx_count[3]), + .O(plm_fsm_rl_counterx_un1_reg_rx_count_0_a2_4) + ); + defparam plm_fsm_rl_counterx_loadable_rx_counter_un1_reg_rx_count_0_a2_5.INIT = 16'h0001; + LUT4 plm_fsm_rl_counterx_loadable_rx_counter_un1_reg_rx_count_0_a2_5 ( + .I0(plm_fsm_rl_counterx_reg_rx_count[4]), + .I1(plm_fsm_rl_counterx_reg_rx_count[5]), + .I2(plm_fsm_rl_counterx_reg_rx_count[6]), + .I3(plm_fsm_rl_counterx_reg_rx_count[7]), + .O(plm_fsm_rl_counterx_un1_reg_rx_count_0_a2_5) + ); + defparam plm_fsm_rl_counterx_loadable_tx_counter_un1_reg_tx_count_0_a2_6.INIT = 16'h0001; + LUT4 plm_fsm_rl_counterx_loadable_tx_counter_un1_reg_tx_count_0_a2_6 ( + .I0(plm_fsm_rl_counterx_reg_tx_count[0]), + .I1(plm_fsm_rl_counterx_reg_tx_count[1]), + .I2(plm_fsm_rl_counterx_reg_tx_count[2]), + .I3(plm_fsm_rl_counterx_reg_tx_count[3]), + .O(plm_fsm_rl_counterx_un1_reg_tx_count_0_a2_6) + ); + defparam plm_fsm_rl_counterx_loadable_tx_counter_un1_reg_tx_count_0_a2_7.INIT = 16'h0001; + LUT4 plm_fsm_rl_counterx_loadable_tx_counter_un1_reg_tx_count_0_a2_7 ( + .I0(plm_fsm_rl_counterx_reg_tx_count[4]), + .I1(plm_fsm_rl_counterx_reg_tx_count[5]), + .I2(plm_fsm_rl_counterx_reg_tx_count[6]), + .I3(plm_fsm_rl_counterx_reg_tx_count[7]), + .O(plm_fsm_rl_counterx_un1_reg_tx_count_0_a2_7) + ); + defparam plm_fsm_rl_counterx_loadable_tx_counter_un1_reg_tx_count_0_a2_8.INIT = 16'h0001; + LUT4 plm_fsm_rl_counterx_loadable_tx_counter_un1_reg_tx_count_0_a2_8 ( + .I0(plm_fsm_rl_counterx_reg_tx_count[8]), + .I1(plm_fsm_rl_counterx_reg_tx_count[9]), + .I2(plm_fsm_rl_counterx_reg_tx_count[10]), + .I3(plm_fsm_rl_counterx_reg_tx_count[11]), + .O(plm_fsm_rl_counterx_un1_reg_tx_count_0_a2_8) + ); + defparam plm_fsm_rl_counterx_N_61242_i.INIT = 4'hB; + LUT2 plm_fsm_rl_counterx_N_61242_i ( + .I0(plm_reg_sym_sent_5_), + .I1(plm_fsm_rl_counterx_un1_enable_1), + .O(plm_fsm_rl_counterx_N_61242_i_1922) + ); + defparam plm_fsm_rl_counterx_loadable_rx_counter_N_61250_i.INIT = 8'hD5; + LUT3 plm_fsm_rl_counterx_loadable_rx_counter_N_61250_i ( + .I0(plm_fsm_reg_state_13__76), + .I1(plm_fsm_rl_counterx_un1_reg_rx_count_0_a2_4), + .I2(plm_fsm_rl_counterx_un1_reg_rx_count_0_a2_5), + .O(plm_fsm_rl_counterx_N_61250_i) + ); + defparam plm_fsm_rl_counterx_loadable_tx_counter_N_61251_i.INIT = 16'hD555; + LUT4 plm_fsm_rl_counterx_loadable_tx_counter_N_61251_i ( + .I0(plm_fsm_reg_state_13__76), + .I1(plm_fsm_rl_counterx_un1_reg_tx_count_0_a2_6), + .I2(plm_fsm_rl_counterx_un1_reg_tx_count_0_a2_7), + .I3(plm_fsm_rl_counterx_un1_reg_tx_count_0_a2_8), + .O(plm_fsm_rl_counterx_N_61251_i) + ); + defparam plm_fsm_rl_counterx_flagit_reg_expired_5_0_a2_0_a2_0_a3_0_a2.INIT = 8'h80; + LUT3_L plm_fsm_rl_counterx_flagit_reg_expired_5_0_a2_0_a2_0_a3_0_a2 ( + .I0(plm_fsm_reg_state_13__76), + .I1(plm_fsm_rl_counterx_reg_rx_expired_1924), + .I2(plm_fsm_rl_counterx_reg_tx_expired_1923), + .LO(plm_fsm_rl_counterx_reg_expired_5) + ); + FDCE plm_fsm_rl_counterx_reg_tx_count_11_ ( + .CE(plm_fsm_rl_counterx_N_61242_i_1922), + .C(mgt_clk), + .D(plm_fsm_rl_counterx_reg_tx_count_s[11]), + .Q(plm_fsm_rl_counterx_reg_tx_count[11]), + .CLR(plm_rst) + ); + FDCE plm_fsm_rl_counterx_reg_tx_count_10_ ( + .CE(plm_fsm_rl_counterx_N_61242_i_1922), + .C(mgt_clk), + .D(plm_fsm_rl_counterx_reg_tx_count_s[10]), + .Q(plm_fsm_rl_counterx_reg_tx_count[10]), + .CLR(plm_rst) + ); + FDCE plm_fsm_rl_counterx_reg_tx_count_9_ ( + .CE(plm_fsm_rl_counterx_N_61242_i_1922), + .C(mgt_clk), + .D(plm_fsm_rl_counterx_reg_tx_count_s[9]), + .Q(plm_fsm_rl_counterx_reg_tx_count[9]), + .CLR(plm_rst) + ); + FDCE plm_fsm_rl_counterx_reg_tx_count_8_ ( + .CE(plm_fsm_rl_counterx_N_61242_i_1922), + .C(mgt_clk), + .D(plm_fsm_rl_counterx_reg_tx_count_s[8]), + .Q(plm_fsm_rl_counterx_reg_tx_count[8]), + .CLR(plm_rst) + ); + FDCE plm_fsm_rl_counterx_reg_tx_count_7_ ( + .CE(plm_fsm_rl_counterx_N_61242_i_1922), + .C(mgt_clk), + .D(plm_fsm_rl_counterx_reg_tx_count_s[7]), + .Q(plm_fsm_rl_counterx_reg_tx_count[7]), + .CLR(plm_rst) + ); + FDCE plm_fsm_rl_counterx_reg_tx_count_6_ ( + .CE(plm_fsm_rl_counterx_N_61242_i_1922), + .C(mgt_clk), + .D(plm_fsm_rl_counterx_reg_tx_count_s[6]), + .Q(plm_fsm_rl_counterx_reg_tx_count[6]), + .CLR(plm_rst) + ); + FDCE plm_fsm_rl_counterx_reg_tx_count_5_ ( + .CE(plm_fsm_rl_counterx_N_61242_i_1922), + .C(mgt_clk), + .D(plm_fsm_rl_counterx_reg_tx_count_s[5]), + .Q(plm_fsm_rl_counterx_reg_tx_count[5]), + .CLR(plm_rst) + ); + FDCE plm_fsm_rl_counterx_reg_tx_count_4_ ( + .CE(plm_fsm_rl_counterx_N_61242_i_1922), + .C(mgt_clk), + .D(plm_fsm_rl_counterx_reg_tx_count_s[4]), + .Q(plm_fsm_rl_counterx_reg_tx_count[4]), + .CLR(plm_rst) + ); + FDCE plm_fsm_rl_counterx_reg_tx_count_3_ ( + .CE(plm_fsm_rl_counterx_N_61242_i_1922), + .C(mgt_clk), + .D(plm_fsm_rl_counterx_reg_tx_count_s[3]), + .Q(plm_fsm_rl_counterx_reg_tx_count[3]), + .CLR(plm_rst) + ); + FDCE plm_fsm_rl_counterx_reg_tx_count_2_ ( + .CE(plm_fsm_rl_counterx_N_61242_i_1922), + .C(mgt_clk), + .D(plm_fsm_rl_counterx_reg_tx_count_s[2]), + .Q(plm_fsm_rl_counterx_reg_tx_count[2]), + .CLR(plm_rst) + ); + FDCE plm_fsm_rl_counterx_reg_tx_count_1_ ( + .CE(plm_fsm_rl_counterx_N_61242_i_1922), + .C(mgt_clk), + .D(plm_fsm_rl_counterx_reg_tx_count_s[1]), + .Q(plm_fsm_rl_counterx_reg_tx_count[1]), + .CLR(plm_rst) + ); + FDCE plm_fsm_rl_counterx_reg_tx_count_0_ ( + .CE(plm_fsm_rl_counterx_N_61242_i_1922), + .C(mgt_clk), + .D(plm_fsm_rl_counterx_reg_tx_count_s[0]), + .Q(plm_fsm_rl_counterx_reg_tx_count[0]), + .CLR(plm_rst) + ); + FDC plm_fsm_rl_counterx_reg_rx_count_7_ ( + .C(mgt_clk), + .D(plm_fsm_rl_counterx_reg_rx_count_s[7]), + .Q(plm_fsm_rl_counterx_reg_rx_count[7]), + .CLR(plm_rst) + ); + FDC plm_fsm_rl_counterx_reg_rx_count_6_ ( + .C(mgt_clk), + .D(plm_fsm_rl_counterx_reg_rx_count_s[6]), + .Q(plm_fsm_rl_counterx_reg_rx_count[6]), + .CLR(plm_rst) + ); + FDC plm_fsm_rl_counterx_reg_rx_count_5_ ( + .C(mgt_clk), + .D(plm_fsm_rl_counterx_reg_rx_count_s[5]), + .Q(plm_fsm_rl_counterx_reg_rx_count[5]), + .CLR(plm_rst) + ); + FDC plm_fsm_rl_counterx_reg_rx_count_4_ ( + .C(mgt_clk), + .D(plm_fsm_rl_counterx_reg_rx_count_s[4]), + .Q(plm_fsm_rl_counterx_reg_rx_count[4]), + .CLR(plm_rst) + ); + FDC plm_fsm_rl_counterx_reg_rx_count_3_ ( + .C(mgt_clk), + .D(plm_fsm_rl_counterx_reg_rx_count_s[3]), + .Q(plm_fsm_rl_counterx_reg_rx_count[3]), + .CLR(plm_rst) + ); + FDC plm_fsm_rl_counterx_reg_rx_count_2_ ( + .C(mgt_clk), + .D(plm_fsm_rl_counterx_reg_rx_count_s[2]), + .Q(plm_fsm_rl_counterx_reg_rx_count[2]), + .CLR(plm_rst) + ); + FDC plm_fsm_rl_counterx_reg_rx_count_1_ ( + .C(mgt_clk), + .D(plm_fsm_rl_counterx_reg_rx_count_s[1]), + .Q(plm_fsm_rl_counterx_reg_rx_count[1]), + .CLR(plm_rst) + ); + FDC plm_fsm_rl_counterx_reg_rx_count_0_ ( + .C(mgt_clk), + .D(plm_fsm_rl_counterx_reg_rx_count_s[0]), + .Q(plm_fsm_rl_counterx_reg_rx_count[0]), + .CLR(plm_rst) + ); + FDC plm_fsm_rl_counterx_reg_expired ( + .C(mgt_clk), + .D(plm_fsm_rl_counterx_reg_expired_5), + .Q(plm_fsm_rl_extdout), + .CLR(plm_rst) + ); + FDCE plm_fsm_rl_counterx_reg_tx_expired ( + .CE(plm_fsm_rl_counterx_N_61251_i), + .C(mgt_clk), + .D(plm_fsm_reg_state_13__76), + .Q(plm_fsm_rl_counterx_reg_tx_expired_1923), + .CLR(plm_rst) + ); + FDCE plm_fsm_rl_counterx_reg_rx_expired ( + .CE(plm_fsm_rl_counterx_N_61250_i), + .C(mgt_clk), + .D(plm_fsm_reg_state_13__76), + .Q(plm_fsm_rl_counterx_reg_rx_expired_1924), + .CLR(plm_rst) + ); + INV plm_fsm_rl_counterx_loadable_rx_counter_N_61252_i ( + .I(plm_fsm_rl_counterx_un1_reg_rx_expired_0_a2_0_a2_0_a3_0_a2), + .O(plm_fsm_rl_counterx_N_61252_i) + ); + INV plm_fsm_rl_counterx_un1_enable_1_i ( + .I(plm_fsm_rl_counterx_un1_enable_1), + .O(plm_fsm_rl_counterx_un1_enable_1_i_1925) + ); + defparam plm_fsm_rl_counterx_reg_rx_count_qxu_0_0_.INIT = 4'h7; + LUT2_L plm_fsm_rl_counterx_reg_rx_count_qxu_0_0_ ( + .I0(plm_fsm_rl_counterx_un1_reg_rx_expired_0_a2_0_a2_0_a3_0_a2), + .I1(plm_fsm_rl_counterx_reg_rx_count[0]), + .LO(plm_fsm_rl_counterx_reg_rx_count_qxu[0]) + ); + defparam plm_fsm_rl_counterx_reg_rx_count_qxu_0_1_.INIT = 4'h7; + LUT2_L plm_fsm_rl_counterx_reg_rx_count_qxu_0_1_ ( + .I0(plm_fsm_rl_counterx_un1_reg_rx_expired_0_a2_0_a2_0_a3_0_a2), + .I1(plm_fsm_rl_counterx_reg_rx_count[1]), + .LO(plm_fsm_rl_counterx_reg_rx_count_qxu[1]) + ); + defparam plm_fsm_rl_counterx_reg_rx_count_qxu_0_2_.INIT = 4'h7; + LUT2_L plm_fsm_rl_counterx_reg_rx_count_qxu_0_2_ ( + .I0(plm_fsm_rl_counterx_un1_reg_rx_expired_0_a2_0_a2_0_a3_0_a2), + .I1(plm_fsm_rl_counterx_reg_rx_count[2]), + .LO(plm_fsm_rl_counterx_reg_rx_count_qxu[2]) + ); + defparam plm_fsm_rl_counterx_reg_rx_count_qxu_0_3_.INIT = 8'h4E; + LUT3_L plm_fsm_rl_counterx_reg_rx_count_qxu_0_3_ ( + .I0(plm_fsm_rl_counterx_un1_reg_rx_expired_0_a2_0_a2_0_a3_0_a2), + .I1(plm_fsm_reg_state_13__76), + .I2(plm_fsm_rl_counterx_reg_rx_count[3]), + .LO(plm_fsm_rl_counterx_reg_rx_count_qxu[3]) + ); + defparam plm_fsm_rl_counterx_reg_rx_count_qxu_0_4_.INIT = 4'h7; + LUT2_L plm_fsm_rl_counterx_reg_rx_count_qxu_0_4_ ( + .I0(plm_fsm_rl_counterx_un1_reg_rx_expired_0_a2_0_a2_0_a3_0_a2), + .I1(plm_fsm_rl_counterx_reg_rx_count[4]), + .LO(plm_fsm_rl_counterx_reg_rx_count_qxu[4]) + ); + defparam plm_fsm_rl_counterx_reg_rx_count_qxu_0_5_.INIT = 4'h7; + LUT2_L plm_fsm_rl_counterx_reg_rx_count_qxu_0_5_ ( + .I0(plm_fsm_rl_counterx_un1_reg_rx_expired_0_a2_0_a2_0_a3_0_a2), + .I1(plm_fsm_rl_counterx_reg_rx_count[5]), + .LO(plm_fsm_rl_counterx_reg_rx_count_qxu[5]) + ); + defparam plm_fsm_rl_counterx_reg_rx_count_qxu_0_6_.INIT = 4'h7; + LUT2_L plm_fsm_rl_counterx_reg_rx_count_qxu_0_6_ ( + .I0(plm_fsm_rl_counterx_un1_reg_rx_expired_0_a2_0_a2_0_a3_0_a2), + .I1(plm_fsm_rl_counterx_reg_rx_count[6]), + .LO(plm_fsm_rl_counterx_reg_rx_count_qxu[6]) + ); + defparam plm_fsm_rl_counterx_reg_rx_count_qxu_0_7_.INIT = 4'h7; + LUT2_L plm_fsm_rl_counterx_reg_rx_count_qxu_0_7_ ( + .I0(plm_fsm_rl_counterx_un1_reg_rx_expired_0_a2_0_a2_0_a3_0_a2), + .I1(plm_fsm_rl_counterx_reg_rx_count[7]), + .LO(plm_fsm_rl_counterx_reg_rx_count_qxu[7]) + ); + defparam plm_fsm_rl_counterx_reg_tx_count_qxu_0_0_.INIT = 4'h7; + LUT2_L plm_fsm_rl_counterx_reg_tx_count_qxu_0_0_ ( + .I0(plm_fsm_rl_counterx_reg_tx_count[0]), + .I1(plm_fsm_rl_counterx_un1_enable_1), + .LO(plm_fsm_rl_counterx_reg_tx_count_qxu[0]) + ); + defparam plm_fsm_rl_counterx_reg_tx_count_qxu_0_1_.INIT = 4'h7; + LUT2_L plm_fsm_rl_counterx_reg_tx_count_qxu_0_1_ ( + .I0(plm_fsm_rl_counterx_reg_tx_count[1]), + .I1(plm_fsm_rl_counterx_un1_enable_1), + .LO(plm_fsm_rl_counterx_reg_tx_count_qxu[1]) + ); + defparam plm_fsm_rl_counterx_reg_tx_count_qxu_0_2_.INIT = 4'h7; + LUT2_L plm_fsm_rl_counterx_reg_tx_count_qxu_0_2_ ( + .I0(plm_fsm_rl_counterx_reg_tx_count[2]), + .I1(plm_fsm_rl_counterx_un1_enable_1), + .LO(plm_fsm_rl_counterx_reg_tx_count_qxu[2]) + ); + defparam plm_fsm_rl_counterx_reg_tx_count_qxu_0_3_.INIT = 4'h7; + LUT2_L plm_fsm_rl_counterx_reg_tx_count_qxu_0_3_ ( + .I0(plm_fsm_rl_counterx_reg_tx_count[3]), + .I1(plm_fsm_rl_counterx_un1_enable_1), + .LO(plm_fsm_rl_counterx_reg_tx_count_qxu[3]) + ); + defparam plm_fsm_rl_counterx_reg_tx_count_qxu_0_4_.INIT = 4'h7; + LUT2_L plm_fsm_rl_counterx_reg_tx_count_qxu_0_4_ ( + .I0(plm_fsm_rl_counterx_reg_tx_count[4]), + .I1(plm_fsm_rl_counterx_un1_enable_1), + .LO(plm_fsm_rl_counterx_reg_tx_count_qxu[4]) + ); + defparam plm_fsm_rl_counterx_reg_tx_count_qxu_0_5_.INIT = 4'h7; + LUT2_L plm_fsm_rl_counterx_reg_tx_count_qxu_0_5_ ( + .I0(plm_fsm_rl_counterx_reg_tx_count[5]), + .I1(plm_fsm_rl_counterx_un1_enable_1), + .LO(plm_fsm_rl_counterx_reg_tx_count_qxu[5]) + ); + defparam plm_fsm_rl_counterx_reg_tx_count_qxu_0_6_.INIT = 4'h7; + LUT2_L plm_fsm_rl_counterx_reg_tx_count_qxu_0_6_ ( + .I0(plm_fsm_rl_counterx_reg_tx_count[6]), + .I1(plm_fsm_rl_counterx_un1_enable_1), + .LO(plm_fsm_rl_counterx_reg_tx_count_qxu[6]) + ); + defparam plm_fsm_rl_counterx_reg_tx_count_qxu_0_7_.INIT = 4'h7; + LUT2_L plm_fsm_rl_counterx_reg_tx_count_qxu_0_7_ ( + .I0(plm_fsm_rl_counterx_reg_tx_count[7]), + .I1(plm_fsm_rl_counterx_un1_enable_1), + .LO(plm_fsm_rl_counterx_reg_tx_count_qxu[7]) + ); + defparam plm_fsm_rl_counterx_reg_tx_count_qxu_0_8_.INIT = 4'h7; + LUT2_L plm_fsm_rl_counterx_reg_tx_count_qxu_0_8_ ( + .I0(plm_fsm_rl_counterx_reg_tx_count[8]), + .I1(plm_fsm_rl_counterx_un1_enable_1), + .LO(plm_fsm_rl_counterx_reg_tx_count_qxu[8]) + ); + defparam plm_fsm_rl_counterx_reg_tx_count_qxu_0_9_.INIT = 4'h7; + LUT2_L plm_fsm_rl_counterx_reg_tx_count_qxu_0_9_ ( + .I0(plm_fsm_rl_counterx_reg_tx_count[9]), + .I1(plm_fsm_rl_counterx_un1_enable_1), + .LO(plm_fsm_rl_counterx_reg_tx_count_qxu[9]) + ); + defparam plm_fsm_rl_counterx_reg_tx_count_qxu_0_10_.INIT = 8'h3A; + LUT3_L plm_fsm_rl_counterx_reg_tx_count_qxu_0_10_ ( + .I0(plm_fsm_reg_state_13__76), + .I1(plm_fsm_rl_counterx_reg_tx_count[10]), + .I2(plm_fsm_rl_counterx_un1_enable_1), + .LO(plm_fsm_rl_counterx_reg_tx_count_qxu[10]) + ); + defparam plm_fsm_rl_counterx_reg_tx_count_qxu_0_11_.INIT = 4'h7; + LUT2_L plm_fsm_rl_counterx_reg_tx_count_qxu_0_11_ ( + .I0(plm_fsm_rl_counterx_reg_tx_count[11]), + .I1(plm_fsm_rl_counterx_un1_enable_1), + .LO(plm_fsm_rl_counterx_reg_tx_count_qxu[11]) + ); + VCC plm_fsm_rl_counter0_VCC ( + .P(plm_fsm_rl_counter0_VCC_1926) + ); + MUXCY_L plm_fsm_rl_counter0_reg_rx_count_cry_0_ ( + .CI(N_15210_i_i_77), + .DI(plm_fsm_rl_counter0_VCC_1926), + .LO(plm_fsm_rl_counter0_reg_rx_count_cry[0]), + .S(plm_fsm_rl_counter0_reg_rx_count_qxu[0]) + ); + XORCY plm_fsm_rl_counter0_reg_rx_count_s_0_ ( + .CI(N_15210_i_i_77), + .LI(plm_fsm_rl_counter0_reg_rx_count_qxu[0]), + .O(plm_fsm_rl_counter0_reg_rx_count_s[0]) + ); + MUXCY_L plm_fsm_rl_counter0_reg_rx_count_cry_1_ ( + .CI(plm_fsm_rl_counter0_reg_rx_count_cry[0]), + .DI(plm_fsm_rl_counter0_VCC_1926), + .LO(plm_fsm_rl_counter0_reg_rx_count_cry[1]), + .S(plm_fsm_rl_counter0_reg_rx_count_qxu[1]) + ); + XORCY plm_fsm_rl_counter0_reg_rx_count_s_1_ ( + .CI(plm_fsm_rl_counter0_reg_rx_count_cry[0]), + .LI(plm_fsm_rl_counter0_reg_rx_count_qxu[1]), + .O(plm_fsm_rl_counter0_reg_rx_count_s[1]) + ); + MUXCY_L plm_fsm_rl_counter0_reg_rx_count_cry_2_ ( + .CI(plm_fsm_rl_counter0_reg_rx_count_cry[1]), + .DI(plm_fsm_rl_counter0_VCC_1926), + .LO(plm_fsm_rl_counter0_reg_rx_count_cry[2]), + .S(plm_fsm_rl_counter0_reg_rx_count_qxu[2]) + ); + XORCY plm_fsm_rl_counter0_reg_rx_count_s_2_ ( + .CI(plm_fsm_rl_counter0_reg_rx_count_cry[1]), + .LI(plm_fsm_rl_counter0_reg_rx_count_qxu[2]), + .O(plm_fsm_rl_counter0_reg_rx_count_s[2]) + ); + MUXCY_L plm_fsm_rl_counter0_reg_rx_count_cry_3_ ( + .CI(plm_fsm_rl_counter0_reg_rx_count_cry[2]), + .DI(plm_fsm_rl_counter0_VCC_1926), + .LO(plm_fsm_rl_counter0_reg_rx_count_cry[3]), + .S(plm_fsm_rl_counter0_reg_rx_count_qxu[3]) + ); + XORCY plm_fsm_rl_counter0_reg_rx_count_s_3_ ( + .CI(plm_fsm_rl_counter0_reg_rx_count_cry[2]), + .LI(plm_fsm_rl_counter0_reg_rx_count_qxu[3]), + .O(plm_fsm_rl_counter0_reg_rx_count_s[3]) + ); + MUXCY_L plm_fsm_rl_counter0_reg_rx_count_cry_4_ ( + .CI(plm_fsm_rl_counter0_reg_rx_count_cry[3]), + .DI(plm_fsm_rl_counter0_VCC_1926), + .LO(plm_fsm_rl_counter0_reg_rx_count_cry[4]), + .S(plm_fsm_rl_counter0_reg_rx_count_qxu[4]) + ); + XORCY plm_fsm_rl_counter0_reg_rx_count_s_4_ ( + .CI(plm_fsm_rl_counter0_reg_rx_count_cry[3]), + .LI(plm_fsm_rl_counter0_reg_rx_count_qxu[4]), + .O(plm_fsm_rl_counter0_reg_rx_count_s[4]) + ); + MUXCY_L plm_fsm_rl_counter0_reg_rx_count_cry_5_ ( + .CI(plm_fsm_rl_counter0_reg_rx_count_cry[4]), + .DI(plm_fsm_rl_counter0_VCC_1926), + .LO(plm_fsm_rl_counter0_reg_rx_count_cry[5]), + .S(plm_fsm_rl_counter0_reg_rx_count_qxu[5]) + ); + XORCY plm_fsm_rl_counter0_reg_rx_count_s_5_ ( + .CI(plm_fsm_rl_counter0_reg_rx_count_cry[4]), + .LI(plm_fsm_rl_counter0_reg_rx_count_qxu[5]), + .O(plm_fsm_rl_counter0_reg_rx_count_s[5]) + ); + MUXCY_L plm_fsm_rl_counter0_reg_rx_count_cry_6_ ( + .CI(plm_fsm_rl_counter0_reg_rx_count_cry[5]), + .DI(plm_fsm_rl_counter0_VCC_1926), + .LO(plm_fsm_rl_counter0_reg_rx_count_cry[6]), + .S(plm_fsm_rl_counter0_reg_rx_count_qxu[6]) + ); + XORCY plm_fsm_rl_counter0_reg_rx_count_s_6_ ( + .CI(plm_fsm_rl_counter0_reg_rx_count_cry[5]), + .LI(plm_fsm_rl_counter0_reg_rx_count_qxu[6]), + .O(plm_fsm_rl_counter0_reg_rx_count_s[6]) + ); + XORCY plm_fsm_rl_counter0_reg_rx_count_s_7_ ( + .CI(plm_fsm_rl_counter0_reg_rx_count_cry[6]), + .LI(plm_fsm_rl_counter0_reg_rx_count_qxu[7]), + .O(plm_fsm_rl_counter0_reg_rx_count_s[7]) + ); + defparam plm_fsm_rl_counter0_un1_enable_2_i_i_0_0_a2_0.INIT = 4'h8; + LUT2 plm_fsm_rl_counter0_un1_enable_2_i_i_0_0_a2_0 ( + .I0(plm_fsm_reg_state_13__76), + .I1(plm_fsm_rl_counter0_reg_rx_expired_75), + .O(plm_fsm_rl_counter0_N_59397) + ); + defparam plm_fsm_rl_counter0_loadable_rx_counter_un1_reg_rx_count_0_a2_4.INIT = 16'h0001; + LUT4 plm_fsm_rl_counter0_loadable_rx_counter_un1_reg_rx_count_0_a2_4 ( + .I0(plm_fsm_rl_counter0_reg_rx_count[0]), + .I1(plm_fsm_rl_counter0_reg_rx_count[1]), + .I2(plm_fsm_rl_counter0_reg_rx_count[2]), + .I3(plm_fsm_rl_counter0_reg_rx_count[3]), + .O(plm_fsm_rl_counter0_un1_reg_rx_count_0_a2_4) + ); + defparam plm_fsm_rl_counter0_loadable_rx_counter_un1_reg_rx_count_0_a2_5.INIT = 16'h0001; + LUT4 plm_fsm_rl_counter0_loadable_rx_counter_un1_reg_rx_count_0_a2_5 ( + .I0(plm_fsm_rl_counter0_reg_rx_count[4]), + .I1(plm_fsm_rl_counter0_reg_rx_count[5]), + .I2(plm_fsm_rl_counter0_reg_rx_count[6]), + .I3(plm_fsm_rl_counter0_reg_rx_count[7]), + .O(plm_fsm_rl_counter0_un1_reg_rx_count_0_a2_5) + ); + defparam plm_fsm_rl_counter0_loadable_tx_counter_N_61249_i.INIT = 8'h57; + LUT3 plm_fsm_rl_counter0_loadable_tx_counter_N_61249_i ( + .I0(plm_fsm_reg_state_13__76), + .I1(plm_fsm_reg_tx_count_4_), + .I2(plm_fsm_reg_tx_count_10_), + .O(plm_fsm_N_61249_i) + ); + defparam plm_fsm_rl_counter0_loadable_rx_counter_un1_reg_rx_expired_1_i.INIT = 4'hD; + LUT2 plm_fsm_rl_counter0_loadable_rx_counter_un1_reg_rx_expired_1_i ( + .I0(plm_fsm_rl_counter0_N_59398), + .I1(plm_fsm_rl_counter0_reg_rx_expired_75), + .O(plm_fsm_rl_counter0_un1_reg_rx_expired_1_i) + ); + defparam plm_fsm_rl_counter0_loadable_rx_counter_N_61248_i.INIT = 8'hD5; + LUT3 plm_fsm_rl_counter0_loadable_rx_counter_N_61248_i ( + .I0(plm_fsm_reg_state_13__76), + .I1(plm_fsm_rl_counter0_un1_reg_rx_count_0_a2_4), + .I2(plm_fsm_rl_counter0_un1_reg_rx_count_0_a2_5), + .O(plm_fsm_rl_counter0_N_61248_i) + ); + defparam plm_fsm_rl_counter0_un1_enable_2_i_i_0_0_a2_1_0.INIT = 4'h2; + LUT2 plm_fsm_rl_counter0_un1_enable_2_i_i_0_0_a2_1_0 ( + .I0(N_56052_i), + .I1(N_56123_i), + .O(N_59396_1) + ); + defparam plm_fsm_rl_counter0_un1_enable_2_i_i_0_0_a2.INIT = 4'h8; + LUT2_L plm_fsm_rl_counter0_un1_enable_2_i_i_0_0_a2 ( + .I0(N_59396_1), + .I1(plm_fsm_reg_state_13__76), + .LO(plm_fsm_rl_counter0_N_59396) + ); + defparam plm_fsm_rl_counter0_un1_enable_2_i_i_0_0.INIT = 8'h01; + LUT3_L plm_fsm_rl_counter0_un1_enable_2_i_i_0_0 ( + .I0(plm_fsm_rl_counter0_N_59396), + .I1(plm_fsm_rl_counter0_N_59397), + .I2(plm_fsm_rl_counter0_N_59398), + .LO(plm_fsm_rl_counter0_N_36497_i) + ); + defparam plm_fsm_rl_counter0_flagit_reg_expired_5_0_a2_0_a2_0_a3_0_a2.INIT = 4'h8; + LUT2_L plm_fsm_rl_counter0_flagit_reg_expired_5_0_a2_0_a2_0_a3_0_a2 ( + .I0(plm_fsm_rl_counter0_N_59397), + .I1(plm_fsm_reg_tx_expired), + .LO(plm_fsm_rl_counter0_reg_expired_5) + ); + defparam plm_fsm_rl_counter0_loadable_tx_counter_reg_tx_count_6_0_a2_0_a2_0_a2_0_a3_0_a2_10_.INIT = 4'h1; + LUT2_L plm_fsm_rl_counter0_loadable_tx_counter_reg_tx_count_6_0_a2_0_a2_0_a2_0_a3_0_a2_10_ ( + .I0(cfg_cfg_6102[507]), + .I1(plm_fsm_reg_state_13__76), + .LO(plm_fsm_reg_tx_count_6_0[10]) + ); + defparam plm_fsm_rl_counter0_un1_enable_2_i_i_0_0_a2_1.INIT = 8'h02; + LUT3 plm_fsm_rl_counter0_un1_enable_2_i_i_0_0_a2_1 ( + .I0(plm_fsm_reg_state_13__76), + .I1(plm_reg_ts1_1), + .I2(plm_reg_ts2_1), + .O(plm_fsm_rl_counter0_N_59398) + ); + FDCE plm_fsm_rl_counter0_reg_rx_count_7_ ( + .CE(plm_fsm_rl_counter0_un1_reg_rx_expired_1_i), + .C(mgt_clk), + .D(plm_fsm_rl_counter0_reg_rx_count_s[7]), + .Q(plm_fsm_rl_counter0_reg_rx_count[7]), + .CLR(plm_rst) + ); + FDCE plm_fsm_rl_counter0_reg_rx_count_6_ ( + .CE(plm_fsm_rl_counter0_un1_reg_rx_expired_1_i), + .C(mgt_clk), + .D(plm_fsm_rl_counter0_reg_rx_count_s[6]), + .Q(plm_fsm_rl_counter0_reg_rx_count[6]), + .CLR(plm_rst) + ); + FDCE plm_fsm_rl_counter0_reg_rx_count_5_ ( + .CE(plm_fsm_rl_counter0_un1_reg_rx_expired_1_i), + .C(mgt_clk), + .D(plm_fsm_rl_counter0_reg_rx_count_s[5]), + .Q(plm_fsm_rl_counter0_reg_rx_count[5]), + .CLR(plm_rst) + ); + FDCE plm_fsm_rl_counter0_reg_rx_count_4_ ( + .CE(plm_fsm_rl_counter0_un1_reg_rx_expired_1_i), + .C(mgt_clk), + .D(plm_fsm_rl_counter0_reg_rx_count_s[4]), + .Q(plm_fsm_rl_counter0_reg_rx_count[4]), + .CLR(plm_rst) + ); + FDCE plm_fsm_rl_counter0_reg_rx_count_3_ ( + .CE(plm_fsm_rl_counter0_un1_reg_rx_expired_1_i), + .C(mgt_clk), + .D(plm_fsm_rl_counter0_reg_rx_count_s[3]), + .Q(plm_fsm_rl_counter0_reg_rx_count[3]), + .CLR(plm_rst) + ); + FDCE plm_fsm_rl_counter0_reg_rx_count_2_ ( + .CE(plm_fsm_rl_counter0_un1_reg_rx_expired_1_i), + .C(mgt_clk), + .D(plm_fsm_rl_counter0_reg_rx_count_s[2]), + .Q(plm_fsm_rl_counter0_reg_rx_count[2]), + .CLR(plm_rst) + ); + FDCE plm_fsm_rl_counter0_reg_rx_count_1_ ( + .CE(plm_fsm_rl_counter0_un1_reg_rx_expired_1_i), + .C(mgt_clk), + .D(plm_fsm_rl_counter0_reg_rx_count_s[1]), + .Q(plm_fsm_rl_counter0_reg_rx_count[1]), + .CLR(plm_rst) + ); + FDCE plm_fsm_rl_counter0_reg_rx_count_0_ ( + .CE(plm_fsm_rl_counter0_un1_reg_rx_expired_1_i), + .C(mgt_clk), + .D(plm_fsm_rl_counter0_reg_rx_count_s[0]), + .Q(plm_fsm_rl_counter0_reg_rx_count[0]), + .CLR(plm_rst) + ); + FDC plm_fsm_rl_counter0_reg_expired ( + .C(mgt_clk), + .D(plm_fsm_rl_counter0_reg_expired_5), + .Q(plm_fsm_rl_cntrout0), + .CLR(plm_rst) + ); + FDCE plm_fsm_rl_counter0_reg_rx_expired ( + .CE(plm_fsm_rl_counter0_N_61248_i), + .C(mgt_clk), + .D(plm_fsm_reg_state_13__76), + .Q(plm_fsm_rl_counter0_reg_rx_expired_75), + .CLR(plm_rst) + ); + defparam plm_fsm_rl_counter0_reg_rx_count_qxu_0_0_.INIT = 4'h7; + LUT2_L plm_fsm_rl_counter0_reg_rx_count_qxu_0_0_ ( + .I0(N_15210_i), + .I1(plm_fsm_rl_counter0_reg_rx_count[0]), + .LO(plm_fsm_rl_counter0_reg_rx_count_qxu[0]) + ); + defparam plm_fsm_rl_counter0_reg_rx_count_qxu_0_1_.INIT = 4'h7; + LUT2_L plm_fsm_rl_counter0_reg_rx_count_qxu_0_1_ ( + .I0(N_15210_i), + .I1(plm_fsm_rl_counter0_reg_rx_count[1]), + .LO(plm_fsm_rl_counter0_reg_rx_count_qxu[1]) + ); + defparam plm_fsm_rl_counter0_reg_rx_count_qxu_0_2_.INIT = 4'h7; + LUT2_L plm_fsm_rl_counter0_reg_rx_count_qxu_0_2_ ( + .I0(N_15210_i), + .I1(plm_fsm_rl_counter0_reg_rx_count[2]), + .LO(plm_fsm_rl_counter0_reg_rx_count_qxu[2]) + ); + defparam plm_fsm_rl_counter0_reg_rx_count_qxu_0_3_.INIT = 8'h1B; + LUT3_L plm_fsm_rl_counter0_reg_rx_count_qxu_0_3_ ( + .I0(N_15210_i), + .I1(plm_fsm_rl_counter0_N_36497_i), + .I2(plm_fsm_rl_counter0_reg_rx_count[3]), + .LO(plm_fsm_rl_counter0_reg_rx_count_qxu[3]) + ); + defparam plm_fsm_rl_counter0_reg_rx_count_qxu_0_4_.INIT = 4'h7; + LUT2_L plm_fsm_rl_counter0_reg_rx_count_qxu_0_4_ ( + .I0(N_15210_i), + .I1(plm_fsm_rl_counter0_reg_rx_count[4]), + .LO(plm_fsm_rl_counter0_reg_rx_count_qxu[4]) + ); + defparam plm_fsm_rl_counter0_reg_rx_count_qxu_0_5_.INIT = 4'h7; + LUT2_L plm_fsm_rl_counter0_reg_rx_count_qxu_0_5_ ( + .I0(N_15210_i), + .I1(plm_fsm_rl_counter0_reg_rx_count[5]), + .LO(plm_fsm_rl_counter0_reg_rx_count_qxu[5]) + ); + defparam plm_fsm_rl_counter0_reg_rx_count_qxu_0_6_.INIT = 4'h7; + LUT2_L plm_fsm_rl_counter0_reg_rx_count_qxu_0_6_ ( + .I0(N_15210_i), + .I1(plm_fsm_rl_counter0_reg_rx_count[6]), + .LO(plm_fsm_rl_counter0_reg_rx_count_qxu[6]) + ); + defparam plm_fsm_rl_counter0_reg_rx_count_qxu_0_7_.INIT = 4'h7; + LUT2_L plm_fsm_rl_counter0_reg_rx_count_qxu_0_7_ ( + .I0(N_15210_i), + .I1(plm_fsm_rl_counter0_reg_rx_count[7]), + .LO(plm_fsm_rl_counter0_reg_rx_count_qxu[7]) + ); + VCC plm_fsm_rl_counter1_VCC ( + .P(plm_fsm_rl_counter1_VCC_1927) + ); + MUXCY_L plm_fsm_rl_counter1_reg_rx_count_cry_0_ ( + .CI(N_14480_i_i_23), + .DI(plm_fsm_rl_counter1_VCC_1927), + .LO(plm_fsm_rl_counter1_reg_rx_count_cry[0]), + .S(plm_fsm_rl_counter1_reg_rx_count_qxu[0]) + ); + XORCY plm_fsm_rl_counter1_reg_rx_count_s_0_ ( + .CI(N_14480_i_i_23), + .LI(plm_fsm_rl_counter1_reg_rx_count_qxu[0]), + .O(plm_fsm_rl_counter1_reg_rx_count_s[0]) + ); + MUXCY_L plm_fsm_rl_counter1_reg_rx_count_cry_1_ ( + .CI(plm_fsm_rl_counter1_reg_rx_count_cry[0]), + .DI(plm_fsm_rl_counter1_VCC_1927), + .LO(plm_fsm_rl_counter1_reg_rx_count_cry[1]), + .S(plm_fsm_rl_counter1_reg_rx_count_qxu[1]) + ); + XORCY plm_fsm_rl_counter1_reg_rx_count_s_1_ ( + .CI(plm_fsm_rl_counter1_reg_rx_count_cry[0]), + .LI(plm_fsm_rl_counter1_reg_rx_count_qxu[1]), + .O(plm_fsm_rl_counter1_reg_rx_count_s[1]) + ); + MUXCY_L plm_fsm_rl_counter1_reg_rx_count_cry_2_ ( + .CI(plm_fsm_rl_counter1_reg_rx_count_cry[1]), + .DI(plm_fsm_rl_counter1_VCC_1927), + .LO(plm_fsm_rl_counter1_reg_rx_count_cry[2]), + .S(plm_fsm_rl_counter1_reg_rx_count_qxu[2]) + ); + XORCY plm_fsm_rl_counter1_reg_rx_count_s_2_ ( + .CI(plm_fsm_rl_counter1_reg_rx_count_cry[1]), + .LI(plm_fsm_rl_counter1_reg_rx_count_qxu[2]), + .O(plm_fsm_rl_counter1_reg_rx_count_s[2]) + ); + MUXCY_L plm_fsm_rl_counter1_reg_rx_count_cry_3_ ( + .CI(plm_fsm_rl_counter1_reg_rx_count_cry[2]), + .DI(plm_fsm_rl_counter1_VCC_1927), + .LO(plm_fsm_rl_counter1_reg_rx_count_cry[3]), + .S(plm_fsm_rl_counter1_reg_rx_count_qxu[3]) + ); + XORCY plm_fsm_rl_counter1_reg_rx_count_s_3_ ( + .CI(plm_fsm_rl_counter1_reg_rx_count_cry[2]), + .LI(plm_fsm_rl_counter1_reg_rx_count_qxu[3]), + .O(plm_fsm_rl_counter1_reg_rx_count_s[3]) + ); + MUXCY_L plm_fsm_rl_counter1_reg_rx_count_cry_4_ ( + .CI(plm_fsm_rl_counter1_reg_rx_count_cry[3]), + .DI(plm_fsm_rl_counter1_VCC_1927), + .LO(plm_fsm_rl_counter1_reg_rx_count_cry[4]), + .S(plm_fsm_rl_counter1_reg_rx_count_qxu[4]) + ); + XORCY plm_fsm_rl_counter1_reg_rx_count_s_4_ ( + .CI(plm_fsm_rl_counter1_reg_rx_count_cry[3]), + .LI(plm_fsm_rl_counter1_reg_rx_count_qxu[4]), + .O(plm_fsm_rl_counter1_reg_rx_count_s[4]) + ); + MUXCY_L plm_fsm_rl_counter1_reg_rx_count_cry_5_ ( + .CI(plm_fsm_rl_counter1_reg_rx_count_cry[4]), + .DI(plm_fsm_rl_counter1_VCC_1927), + .LO(plm_fsm_rl_counter1_reg_rx_count_cry[5]), + .S(plm_fsm_rl_counter1_reg_rx_count_qxu[5]) + ); + XORCY plm_fsm_rl_counter1_reg_rx_count_s_5_ ( + .CI(plm_fsm_rl_counter1_reg_rx_count_cry[4]), + .LI(plm_fsm_rl_counter1_reg_rx_count_qxu[5]), + .O(plm_fsm_rl_counter1_reg_rx_count_s[5]) + ); + MUXCY_L plm_fsm_rl_counter1_reg_rx_count_cry_6_ ( + .CI(plm_fsm_rl_counter1_reg_rx_count_cry[5]), + .DI(plm_fsm_rl_counter1_VCC_1927), + .LO(plm_fsm_rl_counter1_reg_rx_count_cry[6]), + .S(plm_fsm_rl_counter1_reg_rx_count_qxu[6]) + ); + XORCY plm_fsm_rl_counter1_reg_rx_count_s_6_ ( + .CI(plm_fsm_rl_counter1_reg_rx_count_cry[5]), + .LI(plm_fsm_rl_counter1_reg_rx_count_qxu[6]), + .O(plm_fsm_rl_counter1_reg_rx_count_s[6]) + ); + XORCY plm_fsm_rl_counter1_reg_rx_count_s_7_ ( + .CI(plm_fsm_rl_counter1_reg_rx_count_cry[6]), + .LI(plm_fsm_rl_counter1_reg_rx_count_qxu[7]), + .O(plm_fsm_rl_counter1_reg_rx_count_s[7]) + ); + defparam plm_fsm_rl_counter1_un1_enable_2_i_i_0_0_a2_0.INIT = 4'h8; + LUT2 plm_fsm_rl_counter1_un1_enable_2_i_i_0_0_a2_0 ( + .I0(plm_fsm_reg_state_13__76), + .I1(plm_fsm_rl_counter1_reg_rx_expired_314), + .O(plm_fsm_rl_counter1_N_59394) + ); + defparam plm_fsm_rl_counter1_un1_enable_2_i_i_0_0_a2_1.INIT = 8'h10; + LUT3 plm_fsm_rl_counter1_un1_enable_2_i_i_0_0_a2_1 ( + .I0(plm_reg_ts2_1_0), + .I1(plm_reg_ts1_1_0), + .I2(plm_fsm_reg_state_13__76), + .O(plm_fsm_rl_counter1_N_59395) + ); + defparam plm_fsm_rl_counter1_loadable_rx_counter_un1_reg_rx_count_0_a2_4.INIT = 16'h0001; + LUT4 plm_fsm_rl_counter1_loadable_rx_counter_un1_reg_rx_count_0_a2_4 ( + .I0(plm_fsm_rl_counter1_reg_rx_count[0]), + .I1(plm_fsm_rl_counter1_reg_rx_count[1]), + .I2(plm_fsm_rl_counter1_reg_rx_count[2]), + .I3(plm_fsm_rl_counter1_reg_rx_count[3]), + .O(plm_fsm_rl_counter1_un1_reg_rx_count_0_a2_4) + ); + defparam plm_fsm_rl_counter1_loadable_rx_counter_un1_reg_rx_count_0_a2_5.INIT = 16'h0001; + LUT4 plm_fsm_rl_counter1_loadable_rx_counter_un1_reg_rx_count_0_a2_5 ( + .I0(plm_fsm_rl_counter1_reg_rx_count[4]), + .I1(plm_fsm_rl_counter1_reg_rx_count[5]), + .I2(plm_fsm_rl_counter1_reg_rx_count[6]), + .I3(plm_fsm_rl_counter1_reg_rx_count[7]), + .O(plm_fsm_rl_counter1_un1_reg_rx_count_0_a2_5) + ); + defparam plm_fsm_rl_counter1_loadable_rx_counter_un1_reg_rx_expired_1_i.INIT = 4'hD; + LUT2 plm_fsm_rl_counter1_loadable_rx_counter_un1_reg_rx_expired_1_i ( + .I0(plm_fsm_rl_counter1_N_59395), + .I1(plm_fsm_rl_counter1_reg_rx_expired_314), + .O(plm_fsm_rl_counter1_un1_reg_rx_expired_1_i) + ); + defparam plm_fsm_rl_counter1_loadable_rx_counter_N_61247_i.INIT = 8'hD5; + LUT3 plm_fsm_rl_counter1_loadable_rx_counter_N_61247_i ( + .I0(plm_fsm_reg_state_13__76), + .I1(plm_fsm_rl_counter1_un1_reg_rx_count_0_a2_4), + .I2(plm_fsm_rl_counter1_un1_reg_rx_count_0_a2_5), + .O(plm_fsm_rl_counter1_N_61247_i) + ); + defparam plm_fsm_rl_counter1_un1_enable_2_i_i_0_0.INIT = 8'h01; + LUT3_L plm_fsm_rl_counter1_un1_enable_2_i_i_0_0 ( + .I0(N_14480_i), + .I1(plm_fsm_rl_counter1_N_59394), + .I2(plm_fsm_rl_counter1_N_59395), + .LO(plm_fsm_rl_counter1_N_36495_i) + ); + defparam plm_fsm_rl_counter1_flagit_reg_expired_5_0_a2_0_a2_0_a3_0_a2.INIT = 4'h8; + LUT2_L plm_fsm_rl_counter1_flagit_reg_expired_5_0_a2_0_a2_0_a3_0_a2 ( + .I0(plm_fsm_rl_counter1_N_59394), + .I1(plm_fsm_reg_tx_expired), + .LO(plm_fsm_rl_counter1_reg_expired_5) + ); + FDCE plm_fsm_rl_counter1_reg_rx_count_7_ ( + .CE(plm_fsm_rl_counter1_un1_reg_rx_expired_1_i), + .C(mgt_clk), + .D(plm_fsm_rl_counter1_reg_rx_count_s[7]), + .Q(plm_fsm_rl_counter1_reg_rx_count[7]), + .CLR(plm_rst) + ); + FDCE plm_fsm_rl_counter1_reg_rx_count_6_ ( + .CE(plm_fsm_rl_counter1_un1_reg_rx_expired_1_i), + .C(mgt_clk), + .D(plm_fsm_rl_counter1_reg_rx_count_s[6]), + .Q(plm_fsm_rl_counter1_reg_rx_count[6]), + .CLR(plm_rst) + ); + FDCE plm_fsm_rl_counter1_reg_rx_count_5_ ( + .CE(plm_fsm_rl_counter1_un1_reg_rx_expired_1_i), + .C(mgt_clk), + .D(plm_fsm_rl_counter1_reg_rx_count_s[5]), + .Q(plm_fsm_rl_counter1_reg_rx_count[5]), + .CLR(plm_rst) + ); + FDCE plm_fsm_rl_counter1_reg_rx_count_4_ ( + .CE(plm_fsm_rl_counter1_un1_reg_rx_expired_1_i), + .C(mgt_clk), + .D(plm_fsm_rl_counter1_reg_rx_count_s[4]), + .Q(plm_fsm_rl_counter1_reg_rx_count[4]), + .CLR(plm_rst) + ); + FDCE plm_fsm_rl_counter1_reg_rx_count_3_ ( + .CE(plm_fsm_rl_counter1_un1_reg_rx_expired_1_i), + .C(mgt_clk), + .D(plm_fsm_rl_counter1_reg_rx_count_s[3]), + .Q(plm_fsm_rl_counter1_reg_rx_count[3]), + .CLR(plm_rst) + ); + FDCE plm_fsm_rl_counter1_reg_rx_count_2_ ( + .CE(plm_fsm_rl_counter1_un1_reg_rx_expired_1_i), + .C(mgt_clk), + .D(plm_fsm_rl_counter1_reg_rx_count_s[2]), + .Q(plm_fsm_rl_counter1_reg_rx_count[2]), + .CLR(plm_rst) + ); + FDCE plm_fsm_rl_counter1_reg_rx_count_1_ ( + .CE(plm_fsm_rl_counter1_un1_reg_rx_expired_1_i), + .C(mgt_clk), + .D(plm_fsm_rl_counter1_reg_rx_count_s[1]), + .Q(plm_fsm_rl_counter1_reg_rx_count[1]), + .CLR(plm_rst) + ); + FDCE plm_fsm_rl_counter1_reg_rx_count_0_ ( + .CE(plm_fsm_rl_counter1_un1_reg_rx_expired_1_i), + .C(mgt_clk), + .D(plm_fsm_rl_counter1_reg_rx_count_s[0]), + .Q(plm_fsm_rl_counter1_reg_rx_count[0]), + .CLR(plm_rst) + ); + FDC plm_fsm_rl_counter1_reg_expired ( + .C(mgt_clk), + .D(plm_fsm_rl_counter1_reg_expired_5), + .Q(plm_fsm_rl_cntrout1), + .CLR(plm_rst) + ); + FDCE plm_fsm_rl_counter1_reg_rx_expired ( + .CE(plm_fsm_rl_counter1_N_61247_i), + .C(mgt_clk), + .D(plm_fsm_reg_state_13__76), + .Q(plm_fsm_rl_counter1_reg_rx_expired_314), + .CLR(plm_rst) + ); + defparam plm_fsm_rl_counter1_reg_rx_count_qxu_0_0_.INIT = 4'h7; + LUT2_L plm_fsm_rl_counter1_reg_rx_count_qxu_0_0_ ( + .I0(N_14480_i), + .I1(plm_fsm_rl_counter1_reg_rx_count[0]), + .LO(plm_fsm_rl_counter1_reg_rx_count_qxu[0]) + ); + defparam plm_fsm_rl_counter1_reg_rx_count_qxu_0_1_.INIT = 4'h7; + LUT2_L plm_fsm_rl_counter1_reg_rx_count_qxu_0_1_ ( + .I0(N_14480_i), + .I1(plm_fsm_rl_counter1_reg_rx_count[1]), + .LO(plm_fsm_rl_counter1_reg_rx_count_qxu[1]) + ); + defparam plm_fsm_rl_counter1_reg_rx_count_qxu_0_2_.INIT = 4'h7; + LUT2_L plm_fsm_rl_counter1_reg_rx_count_qxu_0_2_ ( + .I0(N_14480_i), + .I1(plm_fsm_rl_counter1_reg_rx_count[2]), + .LO(plm_fsm_rl_counter1_reg_rx_count_qxu[2]) + ); + defparam plm_fsm_rl_counter1_reg_rx_count_qxu_0_3_.INIT = 8'h1B; + LUT3_L plm_fsm_rl_counter1_reg_rx_count_qxu_0_3_ ( + .I0(N_14480_i), + .I1(plm_fsm_rl_counter1_N_36495_i), + .I2(plm_fsm_rl_counter1_reg_rx_count[3]), + .LO(plm_fsm_rl_counter1_reg_rx_count_qxu[3]) + ); + defparam plm_fsm_rl_counter1_reg_rx_count_qxu_0_4_.INIT = 4'h7; + LUT2_L plm_fsm_rl_counter1_reg_rx_count_qxu_0_4_ ( + .I0(N_14480_i), + .I1(plm_fsm_rl_counter1_reg_rx_count[4]), + .LO(plm_fsm_rl_counter1_reg_rx_count_qxu[4]) + ); + defparam plm_fsm_rl_counter1_reg_rx_count_qxu_0_5_.INIT = 4'h7; + LUT2_L plm_fsm_rl_counter1_reg_rx_count_qxu_0_5_ ( + .I0(N_14480_i), + .I1(plm_fsm_rl_counter1_reg_rx_count[5]), + .LO(plm_fsm_rl_counter1_reg_rx_count_qxu[5]) + ); + defparam plm_fsm_rl_counter1_reg_rx_count_qxu_0_6_.INIT = 4'h7; + LUT2_L plm_fsm_rl_counter1_reg_rx_count_qxu_0_6_ ( + .I0(N_14480_i), + .I1(plm_fsm_rl_counter1_reg_rx_count[6]), + .LO(plm_fsm_rl_counter1_reg_rx_count_qxu[6]) + ); + defparam plm_fsm_rl_counter1_reg_rx_count_qxu_0_7_.INIT = 4'h7; + LUT2_L plm_fsm_rl_counter1_reg_rx_count_qxu_0_7_ ( + .I0(N_14480_i), + .I1(plm_fsm_rl_counter1_reg_rx_count[7]), + .LO(plm_fsm_rl_counter1_reg_rx_count_qxu[7]) + ); + VCC plm_fsm_rl_counter2_VCC ( + .P(plm_fsm_rl_counter2_VCC_1928) + ); + MUXCY_L plm_fsm_rl_counter2_reg_rx_count_cry_0_ ( + .CI(N_22527_i_i_22), + .DI(plm_fsm_rl_counter2_VCC_1928), + .LO(plm_fsm_rl_counter2_reg_rx_count_cry[0]), + .S(plm_fsm_rl_counter2_reg_rx_count_qxu[0]) + ); + XORCY plm_fsm_rl_counter2_reg_rx_count_s_0_ ( + .CI(N_22527_i_i_22), + .LI(plm_fsm_rl_counter2_reg_rx_count_qxu[0]), + .O(plm_fsm_rl_counter2_reg_rx_count_s[0]) + ); + MUXCY_L plm_fsm_rl_counter2_reg_rx_count_cry_1_ ( + .CI(plm_fsm_rl_counter2_reg_rx_count_cry[0]), + .DI(plm_fsm_rl_counter2_VCC_1928), + .LO(plm_fsm_rl_counter2_reg_rx_count_cry[1]), + .S(plm_fsm_rl_counter2_reg_rx_count_qxu[1]) + ); + XORCY plm_fsm_rl_counter2_reg_rx_count_s_1_ ( + .CI(plm_fsm_rl_counter2_reg_rx_count_cry[0]), + .LI(plm_fsm_rl_counter2_reg_rx_count_qxu[1]), + .O(plm_fsm_rl_counter2_reg_rx_count_s[1]) + ); + MUXCY_L plm_fsm_rl_counter2_reg_rx_count_cry_2_ ( + .CI(plm_fsm_rl_counter2_reg_rx_count_cry[1]), + .DI(plm_fsm_rl_counter2_VCC_1928), + .LO(plm_fsm_rl_counter2_reg_rx_count_cry[2]), + .S(plm_fsm_rl_counter2_reg_rx_count_qxu[2]) + ); + XORCY plm_fsm_rl_counter2_reg_rx_count_s_2_ ( + .CI(plm_fsm_rl_counter2_reg_rx_count_cry[1]), + .LI(plm_fsm_rl_counter2_reg_rx_count_qxu[2]), + .O(plm_fsm_rl_counter2_reg_rx_count_s[2]) + ); + MUXCY_L plm_fsm_rl_counter2_reg_rx_count_cry_3_ ( + .CI(plm_fsm_rl_counter2_reg_rx_count_cry[2]), + .DI(plm_fsm_rl_counter2_VCC_1928), + .LO(plm_fsm_rl_counter2_reg_rx_count_cry[3]), + .S(plm_fsm_rl_counter2_reg_rx_count_qxu[3]) + ); + XORCY plm_fsm_rl_counter2_reg_rx_count_s_3_ ( + .CI(plm_fsm_rl_counter2_reg_rx_count_cry[2]), + .LI(plm_fsm_rl_counter2_reg_rx_count_qxu[3]), + .O(plm_fsm_rl_counter2_reg_rx_count_s[3]) + ); + MUXCY_L plm_fsm_rl_counter2_reg_rx_count_cry_4_ ( + .CI(plm_fsm_rl_counter2_reg_rx_count_cry[3]), + .DI(plm_fsm_rl_counter2_VCC_1928), + .LO(plm_fsm_rl_counter2_reg_rx_count_cry[4]), + .S(plm_fsm_rl_counter2_reg_rx_count_qxu[4]) + ); + XORCY plm_fsm_rl_counter2_reg_rx_count_s_4_ ( + .CI(plm_fsm_rl_counter2_reg_rx_count_cry[3]), + .LI(plm_fsm_rl_counter2_reg_rx_count_qxu[4]), + .O(plm_fsm_rl_counter2_reg_rx_count_s[4]) + ); + MUXCY_L plm_fsm_rl_counter2_reg_rx_count_cry_5_ ( + .CI(plm_fsm_rl_counter2_reg_rx_count_cry[4]), + .DI(plm_fsm_rl_counter2_VCC_1928), + .LO(plm_fsm_rl_counter2_reg_rx_count_cry[5]), + .S(plm_fsm_rl_counter2_reg_rx_count_qxu[5]) + ); + XORCY plm_fsm_rl_counter2_reg_rx_count_s_5_ ( + .CI(plm_fsm_rl_counter2_reg_rx_count_cry[4]), + .LI(plm_fsm_rl_counter2_reg_rx_count_qxu[5]), + .O(plm_fsm_rl_counter2_reg_rx_count_s[5]) + ); + MUXCY_L plm_fsm_rl_counter2_reg_rx_count_cry_6_ ( + .CI(plm_fsm_rl_counter2_reg_rx_count_cry[5]), + .DI(plm_fsm_rl_counter2_VCC_1928), + .LO(plm_fsm_rl_counter2_reg_rx_count_cry[6]), + .S(plm_fsm_rl_counter2_reg_rx_count_qxu[6]) + ); + XORCY plm_fsm_rl_counter2_reg_rx_count_s_6_ ( + .CI(plm_fsm_rl_counter2_reg_rx_count_cry[5]), + .LI(plm_fsm_rl_counter2_reg_rx_count_qxu[6]), + .O(plm_fsm_rl_counter2_reg_rx_count_s[6]) + ); + XORCY plm_fsm_rl_counter2_reg_rx_count_s_7_ ( + .CI(plm_fsm_rl_counter2_reg_rx_count_cry[6]), + .LI(plm_fsm_rl_counter2_reg_rx_count_qxu[7]), + .O(plm_fsm_rl_counter2_reg_rx_count_s[7]) + ); + defparam plm_fsm_rl_counter2_un1_enable_2_0_0_0_0_a2_0.INIT = 4'h8; + LUT2 plm_fsm_rl_counter2_un1_enable_2_0_0_0_0_a2_0 ( + .I0(plm_fsm_reg_state_13__76), + .I1(plm_fsm_rl_counter2_reg_rx_expired_313), + .O(plm_fsm_rl_counter2_N_58374) + ); + defparam plm_fsm_rl_counter2_un1_enable_2_0_0_0_0_o3.INIT = 4'h1; + LUT2 plm_fsm_rl_counter2_un1_enable_2_0_0_0_0_o3 ( + .I0(plm_rx2_ts1_c), + .I1(plm_rx2_ts2_c), + .O(N_56125_i) + ); + defparam plm_fsm_rl_counter2_un1_enable_2_0_0_0_0_a2_1.INIT = 4'h8; + LUT2 plm_fsm_rl_counter2_un1_enable_2_0_0_0_0_a2_1 ( + .I0(plm_fsm_N_56214_i), + .I1(plm_fsm_reg_state_13__76), + .O(plm_fsm_rl_counter2_N_58375) + ); + defparam plm_fsm_rl_counter2_loadable_rx_counter_un1_reg_rx_count_0_a2_4.INIT = 16'h0001; + LUT4 plm_fsm_rl_counter2_loadable_rx_counter_un1_reg_rx_count_0_a2_4 ( + .I0(plm_fsm_rl_counter2_reg_rx_count[0]), + .I1(plm_fsm_rl_counter2_reg_rx_count[1]), + .I2(plm_fsm_rl_counter2_reg_rx_count[2]), + .I3(plm_fsm_rl_counter2_reg_rx_count[3]), + .O(plm_fsm_rl_counter2_un1_reg_rx_count_0_a2_4) + ); + defparam plm_fsm_rl_counter2_loadable_rx_counter_un1_reg_rx_count_0_a2_5.INIT = 16'h0001; + LUT4 plm_fsm_rl_counter2_loadable_rx_counter_un1_reg_rx_count_0_a2_5 ( + .I0(plm_fsm_rl_counter2_reg_rx_count[4]), + .I1(plm_fsm_rl_counter2_reg_rx_count[5]), + .I2(plm_fsm_rl_counter2_reg_rx_count[6]), + .I3(plm_fsm_rl_counter2_reg_rx_count[7]), + .O(plm_fsm_rl_counter2_un1_reg_rx_count_0_a2_5) + ); + defparam plm_fsm_rl_counter2_loadable_rx_counter_un1_reg_rx_expired_1_i.INIT = 4'hD; + LUT2 plm_fsm_rl_counter2_loadable_rx_counter_un1_reg_rx_expired_1_i ( + .I0(plm_fsm_rl_counter2_N_58375), + .I1(plm_fsm_rl_counter2_reg_rx_expired_313), + .O(plm_fsm_rl_counter2_un1_reg_rx_expired_1_i) + ); + defparam plm_fsm_rl_counter2_loadable_rx_counter_N_61246_i.INIT = 8'hD5; + LUT3 plm_fsm_rl_counter2_loadable_rx_counter_N_61246_i ( + .I0(plm_fsm_reg_state_13__76), + .I1(plm_fsm_rl_counter2_un1_reg_rx_count_0_a2_4), + .I2(plm_fsm_rl_counter2_un1_reg_rx_count_0_a2_5), + .O(plm_fsm_rl_counter2_N_61246_i) + ); + defparam plm_fsm_rl_counter2_un1_enable_2_0_0_0_0.INIT = 8'h01; + LUT3_L plm_fsm_rl_counter2_un1_enable_2_0_0_0_0 ( + .I0(N_22527_i), + .I1(plm_fsm_rl_counter2_N_58374), + .I2(plm_fsm_rl_counter2_N_58375), + .LO(plm_fsm_rl_counter2_N_11166_i) + ); + defparam plm_fsm_rl_counter2_flagit_reg_expired_5_0_a2_0_a2_0_a3_0_a2.INIT = 4'h8; + LUT2_L plm_fsm_rl_counter2_flagit_reg_expired_5_0_a2_0_a2_0_a3_0_a2 ( + .I0(plm_fsm_rl_counter2_N_58374), + .I1(plm_fsm_reg_tx_expired), + .LO(plm_fsm_rl_counter2_reg_expired_5) + ); + FDCE plm_fsm_rl_counter2_reg_rx_count_7_ ( + .CE(plm_fsm_rl_counter2_un1_reg_rx_expired_1_i), + .C(mgt_clk), + .D(plm_fsm_rl_counter2_reg_rx_count_s[7]), + .Q(plm_fsm_rl_counter2_reg_rx_count[7]), + .CLR(plm_rst) + ); + FDCE plm_fsm_rl_counter2_reg_rx_count_6_ ( + .CE(plm_fsm_rl_counter2_un1_reg_rx_expired_1_i), + .C(mgt_clk), + .D(plm_fsm_rl_counter2_reg_rx_count_s[6]), + .Q(plm_fsm_rl_counter2_reg_rx_count[6]), + .CLR(plm_rst) + ); + FDCE plm_fsm_rl_counter2_reg_rx_count_5_ ( + .CE(plm_fsm_rl_counter2_un1_reg_rx_expired_1_i), + .C(mgt_clk), + .D(plm_fsm_rl_counter2_reg_rx_count_s[5]), + .Q(plm_fsm_rl_counter2_reg_rx_count[5]), + .CLR(plm_rst) + ); + FDCE plm_fsm_rl_counter2_reg_rx_count_4_ ( + .CE(plm_fsm_rl_counter2_un1_reg_rx_expired_1_i), + .C(mgt_clk), + .D(plm_fsm_rl_counter2_reg_rx_count_s[4]), + .Q(plm_fsm_rl_counter2_reg_rx_count[4]), + .CLR(plm_rst) + ); + FDCE plm_fsm_rl_counter2_reg_rx_count_3_ ( + .CE(plm_fsm_rl_counter2_un1_reg_rx_expired_1_i), + .C(mgt_clk), + .D(plm_fsm_rl_counter2_reg_rx_count_s[3]), + .Q(plm_fsm_rl_counter2_reg_rx_count[3]), + .CLR(plm_rst) + ); + FDCE plm_fsm_rl_counter2_reg_rx_count_2_ ( + .CE(plm_fsm_rl_counter2_un1_reg_rx_expired_1_i), + .C(mgt_clk), + .D(plm_fsm_rl_counter2_reg_rx_count_s[2]), + .Q(plm_fsm_rl_counter2_reg_rx_count[2]), + .CLR(plm_rst) + ); + FDCE plm_fsm_rl_counter2_reg_rx_count_1_ ( + .CE(plm_fsm_rl_counter2_un1_reg_rx_expired_1_i), + .C(mgt_clk), + .D(plm_fsm_rl_counter2_reg_rx_count_s[1]), + .Q(plm_fsm_rl_counter2_reg_rx_count[1]), + .CLR(plm_rst) + ); + FDCE plm_fsm_rl_counter2_reg_rx_count_0_ ( + .CE(plm_fsm_rl_counter2_un1_reg_rx_expired_1_i), + .C(mgt_clk), + .D(plm_fsm_rl_counter2_reg_rx_count_s[0]), + .Q(plm_fsm_rl_counter2_reg_rx_count[0]), + .CLR(plm_rst) + ); + FDC plm_fsm_rl_counter2_reg_expired ( + .C(mgt_clk), + .D(plm_fsm_rl_counter2_reg_expired_5), + .Q(plm_fsm_rl_cntrout2), + .CLR(plm_rst) + ); + FDCE plm_fsm_rl_counter2_reg_rx_expired ( + .CE(plm_fsm_rl_counter2_N_61246_i), + .C(mgt_clk), + .D(plm_fsm_reg_state_13__76), + .Q(plm_fsm_rl_counter2_reg_rx_expired_313), + .CLR(plm_rst) + ); + defparam plm_fsm_rl_counter2_reg_rx_count_qxu_0_0_.INIT = 4'h7; + LUT2_L plm_fsm_rl_counter2_reg_rx_count_qxu_0_0_ ( + .I0(N_22527_i), + .I1(plm_fsm_rl_counter2_reg_rx_count[0]), + .LO(plm_fsm_rl_counter2_reg_rx_count_qxu[0]) + ); + defparam plm_fsm_rl_counter2_reg_rx_count_qxu_0_1_.INIT = 4'h7; + LUT2_L plm_fsm_rl_counter2_reg_rx_count_qxu_0_1_ ( + .I0(N_22527_i), + .I1(plm_fsm_rl_counter2_reg_rx_count[1]), + .LO(plm_fsm_rl_counter2_reg_rx_count_qxu[1]) + ); + defparam plm_fsm_rl_counter2_reg_rx_count_qxu_0_2_.INIT = 4'h7; + LUT2_L plm_fsm_rl_counter2_reg_rx_count_qxu_0_2_ ( + .I0(N_22527_i), + .I1(plm_fsm_rl_counter2_reg_rx_count[2]), + .LO(plm_fsm_rl_counter2_reg_rx_count_qxu[2]) + ); + defparam plm_fsm_rl_counter2_reg_rx_count_qxu_0_3_.INIT = 8'h1D; + LUT3_L plm_fsm_rl_counter2_reg_rx_count_qxu_0_3_ ( + .I0(plm_fsm_rl_counter2_N_11166_i), + .I1(N_22527_i), + .I2(plm_fsm_rl_counter2_reg_rx_count[3]), + .LO(plm_fsm_rl_counter2_reg_rx_count_qxu[3]) + ); + defparam plm_fsm_rl_counter2_reg_rx_count_qxu_0_4_.INIT = 4'h7; + LUT2_L plm_fsm_rl_counter2_reg_rx_count_qxu_0_4_ ( + .I0(N_22527_i), + .I1(plm_fsm_rl_counter2_reg_rx_count[4]), + .LO(plm_fsm_rl_counter2_reg_rx_count_qxu[4]) + ); + defparam plm_fsm_rl_counter2_reg_rx_count_qxu_0_5_.INIT = 4'h7; + LUT2_L plm_fsm_rl_counter2_reg_rx_count_qxu_0_5_ ( + .I0(N_22527_i), + .I1(plm_fsm_rl_counter2_reg_rx_count[5]), + .LO(plm_fsm_rl_counter2_reg_rx_count_qxu[5]) + ); + defparam plm_fsm_rl_counter2_reg_rx_count_qxu_0_6_.INIT = 4'h7; + LUT2_L plm_fsm_rl_counter2_reg_rx_count_qxu_0_6_ ( + .I0(N_22527_i), + .I1(plm_fsm_rl_counter2_reg_rx_count[6]), + .LO(plm_fsm_rl_counter2_reg_rx_count_qxu[6]) + ); + defparam plm_fsm_rl_counter2_reg_rx_count_qxu_0_7_.INIT = 4'h7; + LUT2_L plm_fsm_rl_counter2_reg_rx_count_qxu_0_7_ ( + .I0(N_22527_i), + .I1(plm_fsm_rl_counter2_reg_rx_count[7]), + .LO(plm_fsm_rl_counter2_reg_rx_count_qxu[7]) + ); + VCC plm_fsm_rl_counter3_VCC ( + .P(plm_fsm_rl_counter3_VCC_1929) + ); + MUXCY_L plm_fsm_rl_counter3_reg_rx_count_cry_0_ ( + .CI(N_22672_i_i_21), + .DI(plm_fsm_rl_counter3_VCC_1929), + .LO(plm_fsm_rl_counter3_reg_rx_count_cry[0]), + .S(plm_fsm_rl_counter3_reg_rx_count_qxu[0]) + ); + XORCY plm_fsm_rl_counter3_reg_rx_count_s_0_ ( + .CI(N_22672_i_i_21), + .LI(plm_fsm_rl_counter3_reg_rx_count_qxu[0]), + .O(plm_fsm_rl_counter3_reg_rx_count_s[0]) + ); + MUXCY_L plm_fsm_rl_counter3_reg_rx_count_cry_1_ ( + .CI(plm_fsm_rl_counter3_reg_rx_count_cry[0]), + .DI(plm_fsm_rl_counter3_VCC_1929), + .LO(plm_fsm_rl_counter3_reg_rx_count_cry[1]), + .S(plm_fsm_rl_counter3_reg_rx_count_qxu[1]) + ); + XORCY plm_fsm_rl_counter3_reg_rx_count_s_1_ ( + .CI(plm_fsm_rl_counter3_reg_rx_count_cry[0]), + .LI(plm_fsm_rl_counter3_reg_rx_count_qxu[1]), + .O(plm_fsm_rl_counter3_reg_rx_count_s[1]) + ); + MUXCY_L plm_fsm_rl_counter3_reg_rx_count_cry_2_ ( + .CI(plm_fsm_rl_counter3_reg_rx_count_cry[1]), + .DI(plm_fsm_rl_counter3_VCC_1929), + .LO(plm_fsm_rl_counter3_reg_rx_count_cry[2]), + .S(plm_fsm_rl_counter3_reg_rx_count_qxu[2]) + ); + XORCY plm_fsm_rl_counter3_reg_rx_count_s_2_ ( + .CI(plm_fsm_rl_counter3_reg_rx_count_cry[1]), + .LI(plm_fsm_rl_counter3_reg_rx_count_qxu[2]), + .O(plm_fsm_rl_counter3_reg_rx_count_s[2]) + ); + MUXCY_L plm_fsm_rl_counter3_reg_rx_count_cry_3_ ( + .CI(plm_fsm_rl_counter3_reg_rx_count_cry[2]), + .DI(plm_fsm_rl_counter3_VCC_1929), + .LO(plm_fsm_rl_counter3_reg_rx_count_cry[3]), + .S(plm_fsm_rl_counter3_reg_rx_count_qxu[3]) + ); + XORCY plm_fsm_rl_counter3_reg_rx_count_s_3_ ( + .CI(plm_fsm_rl_counter3_reg_rx_count_cry[2]), + .LI(plm_fsm_rl_counter3_reg_rx_count_qxu[3]), + .O(plm_fsm_rl_counter3_reg_rx_count_s[3]) + ); + MUXCY_L plm_fsm_rl_counter3_reg_rx_count_cry_4_ ( + .CI(plm_fsm_rl_counter3_reg_rx_count_cry[3]), + .DI(plm_fsm_rl_counter3_VCC_1929), + .LO(plm_fsm_rl_counter3_reg_rx_count_cry[4]), + .S(plm_fsm_rl_counter3_reg_rx_count_qxu[4]) + ); + XORCY plm_fsm_rl_counter3_reg_rx_count_s_4_ ( + .CI(plm_fsm_rl_counter3_reg_rx_count_cry[3]), + .LI(plm_fsm_rl_counter3_reg_rx_count_qxu[4]), + .O(plm_fsm_rl_counter3_reg_rx_count_s[4]) + ); + MUXCY_L plm_fsm_rl_counter3_reg_rx_count_cry_5_ ( + .CI(plm_fsm_rl_counter3_reg_rx_count_cry[4]), + .DI(plm_fsm_rl_counter3_VCC_1929), + .LO(plm_fsm_rl_counter3_reg_rx_count_cry[5]), + .S(plm_fsm_rl_counter3_reg_rx_count_qxu[5]) + ); + XORCY plm_fsm_rl_counter3_reg_rx_count_s_5_ ( + .CI(plm_fsm_rl_counter3_reg_rx_count_cry[4]), + .LI(plm_fsm_rl_counter3_reg_rx_count_qxu[5]), + .O(plm_fsm_rl_counter3_reg_rx_count_s[5]) + ); + MUXCY_L plm_fsm_rl_counter3_reg_rx_count_cry_6_ ( + .CI(plm_fsm_rl_counter3_reg_rx_count_cry[5]), + .DI(plm_fsm_rl_counter3_VCC_1929), + .LO(plm_fsm_rl_counter3_reg_rx_count_cry[6]), + .S(plm_fsm_rl_counter3_reg_rx_count_qxu[6]) + ); + XORCY plm_fsm_rl_counter3_reg_rx_count_s_6_ ( + .CI(plm_fsm_rl_counter3_reg_rx_count_cry[5]), + .LI(plm_fsm_rl_counter3_reg_rx_count_qxu[6]), + .O(plm_fsm_rl_counter3_reg_rx_count_s[6]) + ); + XORCY plm_fsm_rl_counter3_reg_rx_count_s_7_ ( + .CI(plm_fsm_rl_counter3_reg_rx_count_cry[6]), + .LI(plm_fsm_rl_counter3_reg_rx_count_qxu[7]), + .O(plm_fsm_rl_counter3_reg_rx_count_s[7]) + ); + defparam plm_fsm_rl_counter3_un1_enable_2_0_0_0_0_o3.INIT = 4'h1; + LUT2 plm_fsm_rl_counter3_un1_enable_2_0_0_0_0_o3 ( + .I0(plm_rx3_ts1_c), + .I1(plm_rx3_ts2_c), + .O(N_56124_i) + ); + defparam plm_fsm_rl_counter3_un1_enable_2_0_0_0_0_a2_0.INIT = 4'h8; + LUT2 plm_fsm_rl_counter3_un1_enable_2_0_0_0_0_a2_0 ( + .I0(plm_fsm_reg_state_13__76), + .I1(plm_fsm_rl_counter3_reg_rx_expired_312), + .O(plm_fsm_rl_counter3_N_58371) + ); + defparam plm_fsm_rl_counter3_un1_enable_2_0_0_0_0_a2_1.INIT = 8'h10; + LUT3 plm_fsm_rl_counter3_un1_enable_2_0_0_0_0_a2_1 ( + .I0(plm_reg_ts2_1_2), + .I1(plm_reg_ts1_1_2), + .I2(plm_fsm_reg_state_13__76), + .O(plm_fsm_rl_counter3_N_58372) + ); + defparam plm_fsm_rl_counter3_loadable_rx_counter_un1_reg_rx_count_0_a2_4.INIT = 16'h0001; + LUT4 plm_fsm_rl_counter3_loadable_rx_counter_un1_reg_rx_count_0_a2_4 ( + .I0(plm_fsm_rl_counter3_reg_rx_count[0]), + .I1(plm_fsm_rl_counter3_reg_rx_count[1]), + .I2(plm_fsm_rl_counter3_reg_rx_count[2]), + .I3(plm_fsm_rl_counter3_reg_rx_count[3]), + .O(plm_fsm_rl_counter3_un1_reg_rx_count_0_a2_4) + ); + defparam plm_fsm_rl_counter3_loadable_rx_counter_un1_reg_rx_count_0_a2_5.INIT = 16'h0001; + LUT4 plm_fsm_rl_counter3_loadable_rx_counter_un1_reg_rx_count_0_a2_5 ( + .I0(plm_fsm_rl_counter3_reg_rx_count[4]), + .I1(plm_fsm_rl_counter3_reg_rx_count[5]), + .I2(plm_fsm_rl_counter3_reg_rx_count[6]), + .I3(plm_fsm_rl_counter3_reg_rx_count[7]), + .O(plm_fsm_rl_counter3_un1_reg_rx_count_0_a2_5) + ); + defparam plm_fsm_rl_counter3_loadable_rx_counter_N_61008_i.INIT = 4'hD; + LUT2 plm_fsm_rl_counter3_loadable_rx_counter_N_61008_i ( + .I0(plm_fsm_rl_counter3_N_58372), + .I1(plm_fsm_rl_counter3_reg_rx_expired_312), + .O(plm_fsm_rl_counter3_N_61008_i) + ); + defparam plm_fsm_rl_counter3_loadable_rx_counter_N_61245_i.INIT = 8'hD5; + LUT3 plm_fsm_rl_counter3_loadable_rx_counter_N_61245_i ( + .I0(plm_fsm_reg_state_13__76), + .I1(plm_fsm_rl_counter3_un1_reg_rx_count_0_a2_4), + .I2(plm_fsm_rl_counter3_un1_reg_rx_count_0_a2_5), + .O(plm_fsm_rl_counter3_N_61245_i) + ); + defparam plm_fsm_rl_counter3_un1_enable_2_0_0_0_0.INIT = 8'h01; + LUT3_L plm_fsm_rl_counter3_un1_enable_2_0_0_0_0 ( + .I0(N_22672_i), + .I1(plm_fsm_rl_counter3_N_58371), + .I2(plm_fsm_rl_counter3_N_58372), + .LO(plm_fsm_rl_counter3_N_11159_i) + ); + defparam plm_fsm_rl_counter3_flagit_reg_expired_5_0_a2_0_a2_0_a3_0_a2.INIT = 4'h8; + LUT2_L plm_fsm_rl_counter3_flagit_reg_expired_5_0_a2_0_a2_0_a3_0_a2 ( + .I0(plm_fsm_rl_counter3_N_58371), + .I1(plm_fsm_reg_tx_expired), + .LO(plm_fsm_rl_counter3_reg_expired_5) + ); + FDCE plm_fsm_rl_counter3_reg_rx_count_7_ ( + .CE(plm_fsm_rl_counter3_N_61008_i), + .C(mgt_clk), + .D(plm_fsm_rl_counter3_reg_rx_count_s[7]), + .Q(plm_fsm_rl_counter3_reg_rx_count[7]), + .CLR(plm_rst) + ); + FDCE plm_fsm_rl_counter3_reg_rx_count_6_ ( + .CE(plm_fsm_rl_counter3_N_61008_i), + .C(mgt_clk), + .D(plm_fsm_rl_counter3_reg_rx_count_s[6]), + .Q(plm_fsm_rl_counter3_reg_rx_count[6]), + .CLR(plm_rst) + ); + FDCE plm_fsm_rl_counter3_reg_rx_count_5_ ( + .CE(plm_fsm_rl_counter3_N_61008_i), + .C(mgt_clk), + .D(plm_fsm_rl_counter3_reg_rx_count_s[5]), + .Q(plm_fsm_rl_counter3_reg_rx_count[5]), + .CLR(plm_rst) + ); + FDCE plm_fsm_rl_counter3_reg_rx_count_4_ ( + .CE(plm_fsm_rl_counter3_N_61008_i), + .C(mgt_clk), + .D(plm_fsm_rl_counter3_reg_rx_count_s[4]), + .Q(plm_fsm_rl_counter3_reg_rx_count[4]), + .CLR(plm_rst) + ); + FDCE plm_fsm_rl_counter3_reg_rx_count_3_ ( + .CE(plm_fsm_rl_counter3_N_61008_i), + .C(mgt_clk), + .D(plm_fsm_rl_counter3_reg_rx_count_s[3]), + .Q(plm_fsm_rl_counter3_reg_rx_count[3]), + .CLR(plm_rst) + ); + FDCE plm_fsm_rl_counter3_reg_rx_count_2_ ( + .CE(plm_fsm_rl_counter3_N_61008_i), + .C(mgt_clk), + .D(plm_fsm_rl_counter3_reg_rx_count_s[2]), + .Q(plm_fsm_rl_counter3_reg_rx_count[2]), + .CLR(plm_rst) + ); + FDCE plm_fsm_rl_counter3_reg_rx_count_1_ ( + .CE(plm_fsm_rl_counter3_N_61008_i), + .C(mgt_clk), + .D(plm_fsm_rl_counter3_reg_rx_count_s[1]), + .Q(plm_fsm_rl_counter3_reg_rx_count[1]), + .CLR(plm_rst) + ); + FDCE plm_fsm_rl_counter3_reg_rx_count_0_ ( + .CE(plm_fsm_rl_counter3_N_61008_i), + .C(mgt_clk), + .D(plm_fsm_rl_counter3_reg_rx_count_s[0]), + .Q(plm_fsm_rl_counter3_reg_rx_count[0]), + .CLR(plm_rst) + ); + FDC plm_fsm_rl_counter3_reg_expired ( + .C(mgt_clk), + .D(plm_fsm_rl_counter3_reg_expired_5), + .Q(plm_fsm_rl_cntrout3), + .CLR(plm_rst) + ); + FDC plm_fsm_rl_counter3_reg_tx_count_10_ ( + .C(mgt_clk), + .D(plm_fsm_reg_tx_count_6_0[10]), + .Q(plm_fsm_reg_tx_count_10_), + .CLR(plm_rst) + ); + FDC plm_fsm_rl_counter3_reg_tx_count_4_ ( + .C(mgt_clk), + .D(plm_fsm_rl_counter3_loadable_tx_counter_reg_tx_count_6[4]), + .Q(plm_fsm_reg_tx_count_4_), + .CLR(plm_rst) + ); + FDCE plm_fsm_rl_counter3_reg_tx_expired ( + .CE(plm_fsm_N_61249_i), + .C(mgt_clk), + .D(plm_fsm_reg_state_13__76), + .Q(plm_fsm_reg_tx_expired), + .CLR(plm_rst) + ); + FDCE plm_fsm_rl_counter3_reg_rx_expired ( + .CE(plm_fsm_rl_counter3_N_61245_i), + .C(mgt_clk), + .D(plm_fsm_reg_state_13__76), + .Q(plm_fsm_rl_counter3_reg_rx_expired_312), + .CLR(plm_rst) + ); + defparam plm_fsm_rl_counter3_reg_rx_count_qxu_0_0_.INIT = 4'h7; + LUT2_L plm_fsm_rl_counter3_reg_rx_count_qxu_0_0_ ( + .I0(N_22672_i), + .I1(plm_fsm_rl_counter3_reg_rx_count[0]), + .LO(plm_fsm_rl_counter3_reg_rx_count_qxu[0]) + ); + defparam plm_fsm_rl_counter3_reg_rx_count_qxu_0_1_.INIT = 4'h7; + LUT2_L plm_fsm_rl_counter3_reg_rx_count_qxu_0_1_ ( + .I0(N_22672_i), + .I1(plm_fsm_rl_counter3_reg_rx_count[1]), + .LO(plm_fsm_rl_counter3_reg_rx_count_qxu[1]) + ); + defparam plm_fsm_rl_counter3_reg_rx_count_qxu_0_2_.INIT = 4'h7; + LUT2_L plm_fsm_rl_counter3_reg_rx_count_qxu_0_2_ ( + .I0(N_22672_i), + .I1(plm_fsm_rl_counter3_reg_rx_count[2]), + .LO(plm_fsm_rl_counter3_reg_rx_count_qxu[2]) + ); + defparam plm_fsm_rl_counter3_reg_rx_count_qxu_0_3_.INIT = 8'h1D; + LUT3_L plm_fsm_rl_counter3_reg_rx_count_qxu_0_3_ ( + .I0(plm_fsm_rl_counter3_N_11159_i), + .I1(N_22672_i), + .I2(plm_fsm_rl_counter3_reg_rx_count[3]), + .LO(plm_fsm_rl_counter3_reg_rx_count_qxu[3]) + ); + defparam plm_fsm_rl_counter3_reg_rx_count_qxu_0_4_.INIT = 4'h7; + LUT2_L plm_fsm_rl_counter3_reg_rx_count_qxu_0_4_ ( + .I0(N_22672_i), + .I1(plm_fsm_rl_counter3_reg_rx_count[4]), + .LO(plm_fsm_rl_counter3_reg_rx_count_qxu[4]) + ); + defparam plm_fsm_rl_counter3_reg_rx_count_qxu_0_5_.INIT = 4'h7; + LUT2_L plm_fsm_rl_counter3_reg_rx_count_qxu_0_5_ ( + .I0(N_22672_i), + .I1(plm_fsm_rl_counter3_reg_rx_count[5]), + .LO(plm_fsm_rl_counter3_reg_rx_count_qxu[5]) + ); + defparam plm_fsm_rl_counter3_reg_rx_count_qxu_0_6_.INIT = 4'h7; + LUT2_L plm_fsm_rl_counter3_reg_rx_count_qxu_0_6_ ( + .I0(N_22672_i), + .I1(plm_fsm_rl_counter3_reg_rx_count[6]), + .LO(plm_fsm_rl_counter3_reg_rx_count_qxu[6]) + ); + defparam plm_fsm_rl_counter3_reg_rx_count_qxu_0_7_.INIT = 4'h7; + LUT2_L plm_fsm_rl_counter3_reg_rx_count_qxu_0_7_ ( + .I0(N_22672_i), + .I1(plm_fsm_rl_counter3_reg_rx_count[7]), + .LO(plm_fsm_rl_counter3_reg_rx_count_qxu[7]) + ); + GND plm_fsm_rc_timer_GND ( + .G(plm_fsm_rc_timer_GND_1930) + ); + MUXCY_L plm_fsm_rc_timer_reg_count_cry_0_ ( + .CI(N_29556_i_0), + .DI(plm_fsm_rc_timer_GND_1930), + .LO(plm_fsm_rc_timer_reg_count_cry[0]), + .S(plm_fsm_rc_timer_reg_count_qxu[0]) + ); + XORCY plm_fsm_rc_timer_reg_count_s_0_ ( + .CI(N_29556_i_0), + .LI(plm_fsm_rc_timer_reg_count_qxu[0]), + .O(plm_fsm_rc_timer_reg_count_s[0]) + ); + MUXCY_L plm_fsm_rc_timer_reg_count_cry_1_ ( + .CI(plm_fsm_rc_timer_reg_count_cry[0]), + .DI(plm_fsm_rc_timer_GND_1930), + .LO(plm_fsm_rc_timer_reg_count_cry[1]), + .S(plm_fsm_rc_timer_reg_count_qxu[1]) + ); + XORCY plm_fsm_rc_timer_reg_count_s_1_ ( + .CI(plm_fsm_rc_timer_reg_count_cry[0]), + .LI(plm_fsm_rc_timer_reg_count_qxu[1]), + .O(plm_fsm_rc_timer_reg_count_s[1]) + ); + MUXCY_L plm_fsm_rc_timer_reg_count_cry_2_ ( + .CI(plm_fsm_rc_timer_reg_count_cry[1]), + .DI(plm_fsm_rc_timer_GND_1930), + .LO(plm_fsm_rc_timer_reg_count_cry[2]), + .S(plm_fsm_rc_timer_reg_count_qxu[2]) + ); + XORCY plm_fsm_rc_timer_reg_count_s_2_ ( + .CI(plm_fsm_rc_timer_reg_count_cry[1]), + .LI(plm_fsm_rc_timer_reg_count_qxu[2]), + .O(plm_fsm_rc_timer_reg_count_s[2]) + ); + MUXCY_L plm_fsm_rc_timer_reg_count_cry_3_ ( + .CI(plm_fsm_rc_timer_reg_count_cry[2]), + .DI(plm_fsm_rc_timer_GND_1930), + .LO(plm_fsm_rc_timer_reg_count_cry[3]), + .S(plm_fsm_rc_timer_reg_count_qxu[3]) + ); + XORCY plm_fsm_rc_timer_reg_count_s_3_ ( + .CI(plm_fsm_rc_timer_reg_count_cry[2]), + .LI(plm_fsm_rc_timer_reg_count_qxu[3]), + .O(plm_fsm_rc_timer_reg_count_s[3]) + ); + MUXCY_L plm_fsm_rc_timer_reg_count_cry_4_ ( + .CI(plm_fsm_rc_timer_reg_count_cry[3]), + .DI(plm_fsm_rc_timer_GND_1930), + .LO(plm_fsm_rc_timer_reg_count_cry[4]), + .S(plm_fsm_rc_timer_reg_count_qxu[4]) + ); + XORCY plm_fsm_rc_timer_reg_count_s_4_ ( + .CI(plm_fsm_rc_timer_reg_count_cry[3]), + .LI(plm_fsm_rc_timer_reg_count_qxu[4]), + .O(plm_fsm_rc_timer_reg_count_s[4]) + ); + MUXCY_L plm_fsm_rc_timer_reg_count_cry_5_ ( + .CI(plm_fsm_rc_timer_reg_count_cry[4]), + .DI(plm_fsm_rc_timer_GND_1930), + .LO(plm_fsm_rc_timer_reg_count_cry[5]), + .S(plm_fsm_rc_timer_reg_count_qxu[5]) + ); + XORCY plm_fsm_rc_timer_reg_count_s_5_ ( + .CI(plm_fsm_rc_timer_reg_count_cry[4]), + .LI(plm_fsm_rc_timer_reg_count_qxu[5]), + .O(plm_fsm_rc_timer_reg_count_s[5]) + ); + MUXCY_L plm_fsm_rc_timer_reg_count_cry_6_ ( + .CI(plm_fsm_rc_timer_reg_count_cry[5]), + .DI(plm_fsm_rc_timer_GND_1930), + .LO(plm_fsm_rc_timer_reg_count_cry[6]), + .S(plm_fsm_rc_timer_reg_count_qxu[6]) + ); + XORCY plm_fsm_rc_timer_reg_count_s_6_ ( + .CI(plm_fsm_rc_timer_reg_count_cry[5]), + .LI(plm_fsm_rc_timer_reg_count_qxu[6]), + .O(plm_fsm_rc_timer_reg_count_s[6]) + ); + MUXCY_L plm_fsm_rc_timer_reg_count_cry_7_ ( + .CI(plm_fsm_rc_timer_reg_count_cry[6]), + .DI(plm_fsm_rc_timer_GND_1930), + .LO(plm_fsm_rc_timer_reg_count_cry[7]), + .S(plm_fsm_rc_timer_reg_count_qxu[7]) + ); + XORCY plm_fsm_rc_timer_reg_count_s_7_ ( + .CI(plm_fsm_rc_timer_reg_count_cry[6]), + .LI(plm_fsm_rc_timer_reg_count_qxu[7]), + .O(plm_fsm_rc_timer_reg_count_s[7]) + ); + MUXCY_L plm_fsm_rc_timer_reg_count_cry_8_ ( + .CI(plm_fsm_rc_timer_reg_count_cry[7]), + .DI(plm_fsm_rc_timer_GND_1930), + .LO(plm_fsm_rc_timer_reg_count_cry[8]), + .S(plm_fsm_rc_timer_reg_count_qxu[8]) + ); + XORCY plm_fsm_rc_timer_reg_count_s_8_ ( + .CI(plm_fsm_rc_timer_reg_count_cry[7]), + .LI(plm_fsm_rc_timer_reg_count_qxu[8]), + .O(plm_fsm_rc_timer_reg_count_s[8]) + ); + MUXCY_L plm_fsm_rc_timer_reg_count_cry_9_ ( + .CI(plm_fsm_rc_timer_reg_count_cry[8]), + .DI(plm_fsm_rc_timer_GND_1930), + .LO(plm_fsm_rc_timer_reg_count_cry[9]), + .S(plm_fsm_rc_timer_reg_count_qxu[9]) + ); + XORCY plm_fsm_rc_timer_reg_count_s_9_ ( + .CI(plm_fsm_rc_timer_reg_count_cry[8]), + .LI(plm_fsm_rc_timer_reg_count_qxu[9]), + .O(plm_fsm_rc_timer_reg_count_s[9]) + ); + MUXCY_L plm_fsm_rc_timer_reg_count_cry_10_ ( + .CI(plm_fsm_rc_timer_reg_count_cry[9]), + .DI(plm_fsm_rc_timer_GND_1930), + .LO(plm_fsm_rc_timer_reg_count_cry[10]), + .S(plm_fsm_rc_timer_reg_count_qxu[10]) + ); + XORCY plm_fsm_rc_timer_reg_count_s_10_ ( + .CI(plm_fsm_rc_timer_reg_count_cry[9]), + .LI(plm_fsm_rc_timer_reg_count_qxu[10]), + .O(plm_fsm_rc_timer_reg_count_s[10]) + ); + MUXCY_L plm_fsm_rc_timer_reg_count_cry_11_ ( + .CI(plm_fsm_rc_timer_reg_count_cry[10]), + .DI(plm_fsm_rc_timer_GND_1930), + .LO(plm_fsm_rc_timer_reg_count_cry[11]), + .S(plm_fsm_rc_timer_reg_count_qxu[11]) + ); + XORCY plm_fsm_rc_timer_reg_count_s_11_ ( + .CI(plm_fsm_rc_timer_reg_count_cry[10]), + .LI(plm_fsm_rc_timer_reg_count_qxu[11]), + .O(plm_fsm_rc_timer_reg_count_s[11]) + ); + MUXCY_L plm_fsm_rc_timer_reg_count_cry_12_ ( + .CI(plm_fsm_rc_timer_reg_count_cry[11]), + .DI(plm_fsm_rc_timer_GND_1930), + .LO(plm_fsm_rc_timer_reg_count_cry[12]), + .S(plm_fsm_rc_timer_reg_count_qxu[12]) + ); + XORCY plm_fsm_rc_timer_reg_count_s_12_ ( + .CI(plm_fsm_rc_timer_reg_count_cry[11]), + .LI(plm_fsm_rc_timer_reg_count_qxu[12]), + .O(plm_fsm_rc_timer_reg_count_s[12]) + ); + MUXCY_L plm_fsm_rc_timer_reg_count_cry_13_ ( + .CI(plm_fsm_rc_timer_reg_count_cry[12]), + .DI(plm_fsm_rc_timer_GND_1930), + .LO(plm_fsm_rc_timer_reg_count_cry[13]), + .S(plm_fsm_rc_timer_reg_count_qxu[13]) + ); + XORCY plm_fsm_rc_timer_reg_count_s_13_ ( + .CI(plm_fsm_rc_timer_reg_count_cry[12]), + .LI(plm_fsm_rc_timer_reg_count_qxu[13]), + .O(plm_fsm_rc_timer_reg_count_s[13]) + ); + MUXCY_L plm_fsm_rc_timer_reg_count_cry_14_ ( + .CI(plm_fsm_rc_timer_reg_count_cry[13]), + .DI(plm_fsm_rc_timer_GND_1930), + .LO(plm_fsm_rc_timer_reg_count_cry[14]), + .S(plm_fsm_rc_timer_reg_count_qxu[14]) + ); + XORCY plm_fsm_rc_timer_reg_count_s_14_ ( + .CI(plm_fsm_rc_timer_reg_count_cry[13]), + .LI(plm_fsm_rc_timer_reg_count_qxu[14]), + .O(plm_fsm_rc_timer_reg_count_s[14]) + ); + MUXCY_L plm_fsm_rc_timer_reg_count_cry_15_ ( + .CI(plm_fsm_rc_timer_reg_count_cry[14]), + .DI(plm_fsm_rc_timer_GND_1930), + .LO(plm_fsm_rc_timer_reg_count_cry[15]), + .S(plm_fsm_rc_timer_reg_count_qxu[15]) + ); + XORCY plm_fsm_rc_timer_reg_count_s_15_ ( + .CI(plm_fsm_rc_timer_reg_count_cry[14]), + .LI(plm_fsm_rc_timer_reg_count_qxu[15]), + .O(plm_fsm_rc_timer_reg_count_s[15]) + ); + MUXCY_L plm_fsm_rc_timer_reg_count_cry_16_ ( + .CI(plm_fsm_rc_timer_reg_count_cry[15]), + .DI(plm_fsm_rc_timer_GND_1930), + .LO(plm_fsm_rc_timer_reg_count_cry[16]), + .S(plm_fsm_rc_timer_reg_count_qxu[16]) + ); + XORCY plm_fsm_rc_timer_reg_count_s_16_ ( + .CI(plm_fsm_rc_timer_reg_count_cry[15]), + .LI(plm_fsm_rc_timer_reg_count_qxu[16]), + .O(plm_fsm_rc_timer_reg_count_s[16]) + ); + MUXCY_L plm_fsm_rc_timer_reg_count_cry_17_ ( + .CI(plm_fsm_rc_timer_reg_count_cry[16]), + .DI(plm_fsm_rc_timer_GND_1930), + .LO(plm_fsm_rc_timer_reg_count_cry[17]), + .S(plm_fsm_rc_timer_reg_count_qxu[17]) + ); + XORCY plm_fsm_rc_timer_reg_count_s_17_ ( + .CI(plm_fsm_rc_timer_reg_count_cry[16]), + .LI(plm_fsm_rc_timer_reg_count_qxu[17]), + .O(plm_fsm_rc_timer_reg_count_s[17]) + ); + MUXCY_L plm_fsm_rc_timer_reg_count_cry_18_ ( + .CI(plm_fsm_rc_timer_reg_count_cry[17]), + .DI(plm_fsm_rc_timer_GND_1930), + .LO(plm_fsm_rc_timer_reg_count_cry[18]), + .S(plm_fsm_rc_timer_reg_count_qxu[18]) + ); + XORCY plm_fsm_rc_timer_reg_count_s_18_ ( + .CI(plm_fsm_rc_timer_reg_count_cry[17]), + .LI(plm_fsm_rc_timer_reg_count_qxu[18]), + .O(plm_fsm_rc_timer_reg_count_s[18]) + ); + MUXCY_L plm_fsm_rc_timer_reg_count_cry_19_ ( + .CI(plm_fsm_rc_timer_reg_count_cry[18]), + .DI(plm_fsm_rc_timer_GND_1930), + .LO(plm_fsm_rc_timer_reg_count_cry[19]), + .S(plm_fsm_rc_timer_reg_count_qxu[19]) + ); + XORCY plm_fsm_rc_timer_reg_count_s_19_ ( + .CI(plm_fsm_rc_timer_reg_count_cry[18]), + .LI(plm_fsm_rc_timer_reg_count_qxu[19]), + .O(plm_fsm_rc_timer_reg_count_s[19]) + ); + MUXCY_L plm_fsm_rc_timer_reg_count_cry_20_ ( + .CI(plm_fsm_rc_timer_reg_count_cry[19]), + .DI(plm_fsm_rc_timer_GND_1930), + .LO(plm_fsm_rc_timer_reg_count_cry[20]), + .S(plm_fsm_rc_timer_reg_count_qxu[20]) + ); + XORCY plm_fsm_rc_timer_reg_count_s_20_ ( + .CI(plm_fsm_rc_timer_reg_count_cry[19]), + .LI(plm_fsm_rc_timer_reg_count_qxu[20]), + .O(plm_fsm_rc_timer_reg_count_s[20]) + ); + MUXCY_L plm_fsm_rc_timer_reg_count_cry_21_ ( + .CI(plm_fsm_rc_timer_reg_count_cry[20]), + .DI(plm_fsm_rc_timer_GND_1930), + .LO(plm_fsm_rc_timer_reg_count_cry[21]), + .S(plm_fsm_rc_timer_reg_count_qxu[21]) + ); + XORCY plm_fsm_rc_timer_reg_count_s_21_ ( + .CI(plm_fsm_rc_timer_reg_count_cry[20]), + .LI(plm_fsm_rc_timer_reg_count_qxu[21]), + .O(plm_fsm_rc_timer_reg_count_s[21]) + ); + XORCY plm_fsm_rc_timer_reg_count_s_22_ ( + .CI(plm_fsm_rc_timer_reg_count_cry[21]), + .LI(plm_fsm_rc_timer_reg_count_qxu[22]), + .O(plm_fsm_rc_timer_reg_count_s[22]) + ); + defparam plm_fsm_rc_timer_expired_0.INIT = 16'h5140; + LUT4_L plm_fsm_rc_timer_expired_0 ( + .I0(N_29556_i), + .I1(cfg_cfg_6102[507]), + .I2(plm_fsm_rc_timer_reg_count[14]), + .I3(plm_fsm_rc_timer_reg_count[22]), + .LO(plm_fsm_rc_timer_expired_0_1931) + ); + defparam plm_fsm_rc_timer_expired.INIT = 16'hC480; + LUT4 plm_fsm_rc_timer_expired ( + .I0(cfg_cfg_6102[507]), + .I1(plm_fsm_rc_timer_expired_0_1931), + .I2(plm_fsm_rc_timer_reg_count[13]), + .I3(plm_fsm_rc_timer_reg_count[21]), + .O(plm_fsm_rc_timeout) + ); + FDC plm_fsm_rc_timer_reg_count_22_ ( + .C(mgt_clk), + .D(plm_fsm_rc_timer_reg_count_s[22]), + .Q(plm_fsm_rc_timer_reg_count[22]), + .CLR(plm_rst) + ); + FDC plm_fsm_rc_timer_reg_count_21_ ( + .C(mgt_clk), + .D(plm_fsm_rc_timer_reg_count_s[21]), + .Q(plm_fsm_rc_timer_reg_count[21]), + .CLR(plm_rst) + ); + FDC plm_fsm_rc_timer_reg_count_20_ ( + .C(mgt_clk), + .D(plm_fsm_rc_timer_reg_count_s[20]), + .Q(plm_fsm_rc_timer_reg_count[20]), + .CLR(plm_rst) + ); + FDC plm_fsm_rc_timer_reg_count_19_ ( + .C(mgt_clk), + .D(plm_fsm_rc_timer_reg_count_s[19]), + .Q(plm_fsm_rc_timer_reg_count[19]), + .CLR(plm_rst) + ); + FDC plm_fsm_rc_timer_reg_count_18_ ( + .C(mgt_clk), + .D(plm_fsm_rc_timer_reg_count_s[18]), + .Q(plm_fsm_rc_timer_reg_count[18]), + .CLR(plm_rst) + ); + FDC plm_fsm_rc_timer_reg_count_17_ ( + .C(mgt_clk), + .D(plm_fsm_rc_timer_reg_count_s[17]), + .Q(plm_fsm_rc_timer_reg_count[17]), + .CLR(plm_rst) + ); + FDC plm_fsm_rc_timer_reg_count_16_ ( + .C(mgt_clk), + .D(plm_fsm_rc_timer_reg_count_s[16]), + .Q(plm_fsm_rc_timer_reg_count[16]), + .CLR(plm_rst) + ); + FDC plm_fsm_rc_timer_reg_count_15_ ( + .C(mgt_clk), + .D(plm_fsm_rc_timer_reg_count_s[15]), + .Q(plm_fsm_rc_timer_reg_count[15]), + .CLR(plm_rst) + ); + FDC plm_fsm_rc_timer_reg_count_14_ ( + .C(mgt_clk), + .D(plm_fsm_rc_timer_reg_count_s[14]), + .Q(plm_fsm_rc_timer_reg_count[14]), + .CLR(plm_rst) + ); + FDC plm_fsm_rc_timer_reg_count_13_ ( + .C(mgt_clk), + .D(plm_fsm_rc_timer_reg_count_s[13]), + .Q(plm_fsm_rc_timer_reg_count[13]), + .CLR(plm_rst) + ); + FDC plm_fsm_rc_timer_reg_count_12_ ( + .C(mgt_clk), + .D(plm_fsm_rc_timer_reg_count_s[12]), + .Q(plm_fsm_rc_timer_reg_count[12]), + .CLR(plm_rst) + ); + FDC plm_fsm_rc_timer_reg_count_11_ ( + .C(mgt_clk), + .D(plm_fsm_rc_timer_reg_count_s[11]), + .Q(plm_fsm_rc_timer_reg_count[11]), + .CLR(plm_rst) + ); + FDC plm_fsm_rc_timer_reg_count_10_ ( + .C(mgt_clk), + .D(plm_fsm_rc_timer_reg_count_s[10]), + .Q(plm_fsm_rc_timer_reg_count[10]), + .CLR(plm_rst) + ); + FDC plm_fsm_rc_timer_reg_count_9_ ( + .C(mgt_clk), + .D(plm_fsm_rc_timer_reg_count_s[9]), + .Q(plm_fsm_rc_timer_reg_count[9]), + .CLR(plm_rst) + ); + FDC plm_fsm_rc_timer_reg_count_8_ ( + .C(mgt_clk), + .D(plm_fsm_rc_timer_reg_count_s[8]), + .Q(plm_fsm_rc_timer_reg_count[8]), + .CLR(plm_rst) + ); + FDC plm_fsm_rc_timer_reg_count_7_ ( + .C(mgt_clk), + .D(plm_fsm_rc_timer_reg_count_s[7]), + .Q(plm_fsm_rc_timer_reg_count[7]), + .CLR(plm_rst) + ); + FDC plm_fsm_rc_timer_reg_count_6_ ( + .C(mgt_clk), + .D(plm_fsm_rc_timer_reg_count_s[6]), + .Q(plm_fsm_rc_timer_reg_count[6]), + .CLR(plm_rst) + ); + FDC plm_fsm_rc_timer_reg_count_5_ ( + .C(mgt_clk), + .D(plm_fsm_rc_timer_reg_count_s[5]), + .Q(plm_fsm_rc_timer_reg_count[5]), + .CLR(plm_rst) + ); + FDC plm_fsm_rc_timer_reg_count_4_ ( + .C(mgt_clk), + .D(plm_fsm_rc_timer_reg_count_s[4]), + .Q(plm_fsm_rc_timer_reg_count[4]), + .CLR(plm_rst) + ); + FDC plm_fsm_rc_timer_reg_count_3_ ( + .C(mgt_clk), + .D(plm_fsm_rc_timer_reg_count_s[3]), + .Q(plm_fsm_rc_timer_reg_count[3]), + .CLR(plm_rst) + ); + FDC plm_fsm_rc_timer_reg_count_2_ ( + .C(mgt_clk), + .D(plm_fsm_rc_timer_reg_count_s[2]), + .Q(plm_fsm_rc_timer_reg_count[2]), + .CLR(plm_rst) + ); + FDC plm_fsm_rc_timer_reg_count_1_ ( + .C(mgt_clk), + .D(plm_fsm_rc_timer_reg_count_s[1]), + .Q(plm_fsm_rc_timer_reg_count[1]), + .CLR(plm_rst) + ); + FDC plm_fsm_rc_timer_reg_count_0_ ( + .C(mgt_clk), + .D(plm_fsm_rc_timer_reg_count_s[0]), + .Q(plm_fsm_rc_timer_reg_count[0]), + .CLR(plm_rst) + ); + defparam plm_fsm_rc_timer_reg_count_qxu_0_0_.INIT = 4'h4; + LUT2_L plm_fsm_rc_timer_reg_count_qxu_0_0_ ( + .I0(N_29556_i_1), + .I1(plm_fsm_rc_timer_reg_count[0]), + .LO(plm_fsm_rc_timer_reg_count_qxu[0]) + ); + defparam plm_fsm_rc_timer_reg_count_qxu_0_1_.INIT = 4'h4; + LUT2_L plm_fsm_rc_timer_reg_count_qxu_0_1_ ( + .I0(N_29556_i_1), + .I1(plm_fsm_rc_timer_reg_count[1]), + .LO(plm_fsm_rc_timer_reg_count_qxu[1]) + ); + defparam plm_fsm_rc_timer_reg_count_qxu_0_2_.INIT = 4'h4; + LUT2_L plm_fsm_rc_timer_reg_count_qxu_0_2_ ( + .I0(N_29556_i_1), + .I1(plm_fsm_rc_timer_reg_count[2]), + .LO(plm_fsm_rc_timer_reg_count_qxu[2]) + ); + defparam plm_fsm_rc_timer_reg_count_qxu_0_3_.INIT = 4'h4; + LUT2_L plm_fsm_rc_timer_reg_count_qxu_0_3_ ( + .I0(N_29556_i_1), + .I1(plm_fsm_rc_timer_reg_count[3]), + .LO(plm_fsm_rc_timer_reg_count_qxu[3]) + ); + defparam plm_fsm_rc_timer_reg_count_qxu_0_4_.INIT = 4'h4; + LUT2_L plm_fsm_rc_timer_reg_count_qxu_0_4_ ( + .I0(N_29556_i_1), + .I1(plm_fsm_rc_timer_reg_count[4]), + .LO(plm_fsm_rc_timer_reg_count_qxu[4]) + ); + defparam plm_fsm_rc_timer_reg_count_qxu_0_5_.INIT = 4'h4; + LUT2_L plm_fsm_rc_timer_reg_count_qxu_0_5_ ( + .I0(N_29556_i_1), + .I1(plm_fsm_rc_timer_reg_count[5]), + .LO(plm_fsm_rc_timer_reg_count_qxu[5]) + ); + defparam plm_fsm_rc_timer_reg_count_qxu_0_6_.INIT = 4'h4; + LUT2_L plm_fsm_rc_timer_reg_count_qxu_0_6_ ( + .I0(N_29556_i_1), + .I1(plm_fsm_rc_timer_reg_count[6]), + .LO(plm_fsm_rc_timer_reg_count_qxu[6]) + ); + defparam plm_fsm_rc_timer_reg_count_qxu_0_7_.INIT = 4'h4; + LUT2_L plm_fsm_rc_timer_reg_count_qxu_0_7_ ( + .I0(N_29556_i_1), + .I1(plm_fsm_rc_timer_reg_count[7]), + .LO(plm_fsm_rc_timer_reg_count_qxu[7]) + ); + defparam plm_fsm_rc_timer_reg_count_qxu_0_8_.INIT = 4'h4; + LUT2_L plm_fsm_rc_timer_reg_count_qxu_0_8_ ( + .I0(N_29556_i_1), + .I1(plm_fsm_rc_timer_reg_count[8]), + .LO(plm_fsm_rc_timer_reg_count_qxu[8]) + ); + defparam plm_fsm_rc_timer_reg_count_qxu_0_9_.INIT = 4'h4; + LUT2_L plm_fsm_rc_timer_reg_count_qxu_0_9_ ( + .I0(N_29556_i_1), + .I1(plm_fsm_rc_timer_reg_count[9]), + .LO(plm_fsm_rc_timer_reg_count_qxu[9]) + ); + defparam plm_fsm_rc_timer_reg_count_qxu_0_10_.INIT = 4'h4; + LUT2_L plm_fsm_rc_timer_reg_count_qxu_0_10_ ( + .I0(N_29556_i_1), + .I1(plm_fsm_rc_timer_reg_count[10]), + .LO(plm_fsm_rc_timer_reg_count_qxu[10]) + ); + defparam plm_fsm_rc_timer_reg_count_qxu_0_11_.INIT = 4'h4; + LUT2_L plm_fsm_rc_timer_reg_count_qxu_0_11_ ( + .I0(N_29556_i_1), + .I1(plm_fsm_rc_timer_reg_count[11]), + .LO(plm_fsm_rc_timer_reg_count_qxu[11]) + ); + defparam plm_fsm_rc_timer_reg_count_qxu_0_12_.INIT = 4'h4; + LUT2_L plm_fsm_rc_timer_reg_count_qxu_0_12_ ( + .I0(N_29556_i_1), + .I1(plm_fsm_rc_timer_reg_count[12]), + .LO(plm_fsm_rc_timer_reg_count_qxu[12]) + ); + defparam plm_fsm_rc_timer_reg_count_qxu_0_13_.INIT = 4'h4; + LUT2_L plm_fsm_rc_timer_reg_count_qxu_0_13_ ( + .I0(N_29556_i_1), + .I1(plm_fsm_rc_timer_reg_count[13]), + .LO(plm_fsm_rc_timer_reg_count_qxu[13]) + ); + defparam plm_fsm_rc_timer_reg_count_qxu_0_14_.INIT = 4'h4; + LUT2_L plm_fsm_rc_timer_reg_count_qxu_0_14_ ( + .I0(N_29556_i_1), + .I1(plm_fsm_rc_timer_reg_count[14]), + .LO(plm_fsm_rc_timer_reg_count_qxu[14]) + ); + defparam plm_fsm_rc_timer_reg_count_qxu_0_15_.INIT = 4'h4; + LUT2_L plm_fsm_rc_timer_reg_count_qxu_0_15_ ( + .I0(N_29556_i_1), + .I1(plm_fsm_rc_timer_reg_count[15]), + .LO(plm_fsm_rc_timer_reg_count_qxu[15]) + ); + defparam plm_fsm_rc_timer_reg_count_qxu_0_16_.INIT = 4'h4; + LUT2_L plm_fsm_rc_timer_reg_count_qxu_0_16_ ( + .I0(N_29556_i_1), + .I1(plm_fsm_rc_timer_reg_count[16]), + .LO(plm_fsm_rc_timer_reg_count_qxu[16]) + ); + defparam plm_fsm_rc_timer_reg_count_qxu_0_17_.INIT = 4'h4; + LUT2_L plm_fsm_rc_timer_reg_count_qxu_0_17_ ( + .I0(N_29556_i_1), + .I1(plm_fsm_rc_timer_reg_count[17]), + .LO(plm_fsm_rc_timer_reg_count_qxu[17]) + ); + defparam plm_fsm_rc_timer_reg_count_qxu_0_18_.INIT = 4'h4; + LUT2_L plm_fsm_rc_timer_reg_count_qxu_0_18_ ( + .I0(N_29556_i_1), + .I1(plm_fsm_rc_timer_reg_count[18]), + .LO(plm_fsm_rc_timer_reg_count_qxu[18]) + ); + defparam plm_fsm_rc_timer_reg_count_qxu_0_19_.INIT = 4'h4; + LUT2_L plm_fsm_rc_timer_reg_count_qxu_0_19_ ( + .I0(N_29556_i_1), + .I1(plm_fsm_rc_timer_reg_count[19]), + .LO(plm_fsm_rc_timer_reg_count_qxu[19]) + ); + defparam plm_fsm_rc_timer_reg_count_qxu_0_20_.INIT = 4'h4; + LUT2_L plm_fsm_rc_timer_reg_count_qxu_0_20_ ( + .I0(N_29556_i_1), + .I1(plm_fsm_rc_timer_reg_count[20]), + .LO(plm_fsm_rc_timer_reg_count_qxu[20]) + ); + defparam plm_fsm_rc_timer_reg_count_qxu_0_21_.INIT = 4'h4; + LUT2_L plm_fsm_rc_timer_reg_count_qxu_0_21_ ( + .I0(N_29556_i_1), + .I1(plm_fsm_rc_timer_reg_count[21]), + .LO(plm_fsm_rc_timer_reg_count_qxu[21]) + ); + defparam plm_fsm_rc_timer_reg_count_qxu_0_22_.INIT = 4'h4; + LUT2_L plm_fsm_rc_timer_reg_count_qxu_0_22_ ( + .I0(N_29556_i_1), + .I1(plm_fsm_rc_timer_reg_count[22]), + .LO(plm_fsm_rc_timer_reg_count_qxu[22]) + ); + VCC plm_fsm_rc_counter_ts1_0_VCC ( + .P(plm_fsm_rc_counter_ts1_0_VCC_1932) + ); + MUXCY_L plm_fsm_rc_counter_ts1_0_reg_rx_count_cry_0_ ( + .CI(N_28800_i_i_24), + .DI(plm_fsm_rc_counter_ts1_0_VCC_1932), + .LO(plm_fsm_rc_counter_ts1_0_reg_rx_count_cry[0]), + .S(plm_fsm_rc_counter_ts1_0_reg_rx_count_qxu[0]) + ); + XORCY plm_fsm_rc_counter_ts1_0_reg_rx_count_s_0_ ( + .CI(N_28800_i_i_24), + .LI(plm_fsm_rc_counter_ts1_0_reg_rx_count_qxu[0]), + .O(plm_fsm_rc_counter_ts1_0_reg_rx_count_s[0]) + ); + MUXCY_L plm_fsm_rc_counter_ts1_0_reg_rx_count_cry_1_ ( + .CI(plm_fsm_rc_counter_ts1_0_reg_rx_count_cry[0]), + .DI(plm_fsm_rc_counter_ts1_0_VCC_1932), + .LO(plm_fsm_rc_counter_ts1_0_reg_rx_count_cry[1]), + .S(plm_fsm_rc_counter_ts1_0_reg_rx_count_qxu[1]) + ); + XORCY plm_fsm_rc_counter_ts1_0_reg_rx_count_s_1_ ( + .CI(plm_fsm_rc_counter_ts1_0_reg_rx_count_cry[0]), + .LI(plm_fsm_rc_counter_ts1_0_reg_rx_count_qxu[1]), + .O(plm_fsm_rc_counter_ts1_0_reg_rx_count_s[1]) + ); + MUXCY_L plm_fsm_rc_counter_ts1_0_reg_rx_count_cry_2_ ( + .CI(plm_fsm_rc_counter_ts1_0_reg_rx_count_cry[1]), + .DI(plm_fsm_rc_counter_ts1_0_VCC_1932), + .LO(plm_fsm_rc_counter_ts1_0_reg_rx_count_cry[2]), + .S(plm_fsm_rc_counter_ts1_0_reg_rx_count_qxu[2]) + ); + XORCY plm_fsm_rc_counter_ts1_0_reg_rx_count_s_2_ ( + .CI(plm_fsm_rc_counter_ts1_0_reg_rx_count_cry[1]), + .LI(plm_fsm_rc_counter_ts1_0_reg_rx_count_qxu[2]), + .O(plm_fsm_rc_counter_ts1_0_reg_rx_count_s[2]) + ); + MUXCY_L plm_fsm_rc_counter_ts1_0_reg_rx_count_cry_3_ ( + .CI(plm_fsm_rc_counter_ts1_0_reg_rx_count_cry[2]), + .DI(plm_fsm_rc_counter_ts1_0_VCC_1932), + .LO(plm_fsm_rc_counter_ts1_0_reg_rx_count_cry[3]), + .S(plm_fsm_rc_counter_ts1_0_reg_rx_count_qxu[3]) + ); + XORCY plm_fsm_rc_counter_ts1_0_reg_rx_count_s_3_ ( + .CI(plm_fsm_rc_counter_ts1_0_reg_rx_count_cry[2]), + .LI(plm_fsm_rc_counter_ts1_0_reg_rx_count_qxu[3]), + .O(plm_fsm_rc_counter_ts1_0_reg_rx_count_s[3]) + ); + MUXCY_L plm_fsm_rc_counter_ts1_0_reg_rx_count_cry_4_ ( + .CI(plm_fsm_rc_counter_ts1_0_reg_rx_count_cry[3]), + .DI(plm_fsm_rc_counter_ts1_0_VCC_1932), + .LO(plm_fsm_rc_counter_ts1_0_reg_rx_count_cry[4]), + .S(plm_fsm_rc_counter_ts1_0_reg_rx_count_qxu[4]) + ); + XORCY plm_fsm_rc_counter_ts1_0_reg_rx_count_s_4_ ( + .CI(plm_fsm_rc_counter_ts1_0_reg_rx_count_cry[3]), + .LI(plm_fsm_rc_counter_ts1_0_reg_rx_count_qxu[4]), + .O(plm_fsm_rc_counter_ts1_0_reg_rx_count_s[4]) + ); + MUXCY_L plm_fsm_rc_counter_ts1_0_reg_rx_count_cry_5_ ( + .CI(plm_fsm_rc_counter_ts1_0_reg_rx_count_cry[4]), + .DI(plm_fsm_rc_counter_ts1_0_VCC_1932), + .LO(plm_fsm_rc_counter_ts1_0_reg_rx_count_cry[5]), + .S(plm_fsm_rc_counter_ts1_0_reg_rx_count_qxu[5]) + ); + XORCY plm_fsm_rc_counter_ts1_0_reg_rx_count_s_5_ ( + .CI(plm_fsm_rc_counter_ts1_0_reg_rx_count_cry[4]), + .LI(plm_fsm_rc_counter_ts1_0_reg_rx_count_qxu[5]), + .O(plm_fsm_rc_counter_ts1_0_reg_rx_count_s[5]) + ); + MUXCY_L plm_fsm_rc_counter_ts1_0_reg_rx_count_cry_6_ ( + .CI(plm_fsm_rc_counter_ts1_0_reg_rx_count_cry[5]), + .DI(plm_fsm_rc_counter_ts1_0_VCC_1932), + .LO(plm_fsm_rc_counter_ts1_0_reg_rx_count_cry[6]), + .S(plm_fsm_rc_counter_ts1_0_reg_rx_count_qxu[6]) + ); + XORCY plm_fsm_rc_counter_ts1_0_reg_rx_count_s_6_ ( + .CI(plm_fsm_rc_counter_ts1_0_reg_rx_count_cry[5]), + .LI(plm_fsm_rc_counter_ts1_0_reg_rx_count_qxu[6]), + .O(plm_fsm_rc_counter_ts1_0_reg_rx_count_s[6]) + ); + XORCY plm_fsm_rc_counter_ts1_0_reg_rx_count_s_7_ ( + .CI(plm_fsm_rc_counter_ts1_0_reg_rx_count_cry[6]), + .LI(plm_fsm_rc_counter_ts1_0_reg_rx_count_qxu[7]), + .O(plm_fsm_rc_counter_ts1_0_reg_rx_count_s[7]) + ); + MUXCY_L plm_fsm_rc_counter_ts1_0_reg_tx_count_cry_0_ ( + .CI(plm_fsm_rc_counter_ts1_0_N_60924_i_1933), + .DI(plm_fsm_rc_counter_ts1_0_VCC_1932), + .LO(plm_fsm_rc_counter_ts1_0_reg_tx_count_cry[0]), + .S(plm_fsm_rc_counter_ts1_0_reg_tx_count_qxu[0]) + ); + XORCY plm_fsm_rc_counter_ts1_0_reg_tx_count_s_0_ ( + .CI(plm_fsm_rc_counter_ts1_0_N_60924_i_1933), + .LI(plm_fsm_rc_counter_ts1_0_reg_tx_count_qxu[0]), + .O(plm_fsm_rc_counter_ts1_0_reg_tx_count_s[0]) + ); + MUXCY_L plm_fsm_rc_counter_ts1_0_reg_tx_count_cry_1_ ( + .CI(plm_fsm_rc_counter_ts1_0_reg_tx_count_cry[0]), + .DI(plm_fsm_rc_counter_ts1_0_VCC_1932), + .LO(plm_fsm_rc_counter_ts1_0_reg_tx_count_cry[1]), + .S(plm_fsm_rc_counter_ts1_0_reg_tx_count_qxu[1]) + ); + XORCY plm_fsm_rc_counter_ts1_0_reg_tx_count_s_1_ ( + .CI(plm_fsm_rc_counter_ts1_0_reg_tx_count_cry[0]), + .LI(plm_fsm_rc_counter_ts1_0_reg_tx_count_qxu[1]), + .O(plm_fsm_rc_counter_ts1_0_reg_tx_count_s[1]) + ); + MUXCY_L plm_fsm_rc_counter_ts1_0_reg_tx_count_cry_2_ ( + .CI(plm_fsm_rc_counter_ts1_0_reg_tx_count_cry[1]), + .DI(plm_fsm_rc_counter_ts1_0_VCC_1932), + .LO(plm_fsm_rc_counter_ts1_0_reg_tx_count_cry[2]), + .S(plm_fsm_rc_counter_ts1_0_reg_tx_count_qxu[2]) + ); + XORCY plm_fsm_rc_counter_ts1_0_reg_tx_count_s_2_ ( + .CI(plm_fsm_rc_counter_ts1_0_reg_tx_count_cry[1]), + .LI(plm_fsm_rc_counter_ts1_0_reg_tx_count_qxu[2]), + .O(plm_fsm_rc_counter_ts1_0_reg_tx_count_s[2]) + ); + MUXCY_L plm_fsm_rc_counter_ts1_0_reg_tx_count_cry_3_ ( + .CI(plm_fsm_rc_counter_ts1_0_reg_tx_count_cry[2]), + .DI(plm_fsm_rc_counter_ts1_0_VCC_1932), + .LO(plm_fsm_rc_counter_ts1_0_reg_tx_count_cry[3]), + .S(plm_fsm_rc_counter_ts1_0_reg_tx_count_qxu[3]) + ); + XORCY plm_fsm_rc_counter_ts1_0_reg_tx_count_s_3_ ( + .CI(plm_fsm_rc_counter_ts1_0_reg_tx_count_cry[2]), + .LI(plm_fsm_rc_counter_ts1_0_reg_tx_count_qxu[3]), + .O(plm_fsm_rc_counter_ts1_0_reg_tx_count_s[3]) + ); + MUXCY_L plm_fsm_rc_counter_ts1_0_reg_tx_count_cry_4_ ( + .CI(plm_fsm_rc_counter_ts1_0_reg_tx_count_cry[3]), + .DI(plm_fsm_rc_counter_ts1_0_VCC_1932), + .LO(plm_fsm_rc_counter_ts1_0_reg_tx_count_cry[4]), + .S(plm_fsm_rc_counter_ts1_0_reg_tx_count_qxu[4]) + ); + XORCY plm_fsm_rc_counter_ts1_0_reg_tx_count_s_4_ ( + .CI(plm_fsm_rc_counter_ts1_0_reg_tx_count_cry[3]), + .LI(plm_fsm_rc_counter_ts1_0_reg_tx_count_qxu[4]), + .O(plm_fsm_rc_counter_ts1_0_reg_tx_count_s[4]) + ); + MUXCY_L plm_fsm_rc_counter_ts1_0_reg_tx_count_cry_5_ ( + .CI(plm_fsm_rc_counter_ts1_0_reg_tx_count_cry[4]), + .DI(plm_fsm_rc_counter_ts1_0_VCC_1932), + .LO(plm_fsm_rc_counter_ts1_0_reg_tx_count_cry[5]), + .S(plm_fsm_rc_counter_ts1_0_reg_tx_count_qxu[5]) + ); + XORCY plm_fsm_rc_counter_ts1_0_reg_tx_count_s_5_ ( + .CI(plm_fsm_rc_counter_ts1_0_reg_tx_count_cry[4]), + .LI(plm_fsm_rc_counter_ts1_0_reg_tx_count_qxu[5]), + .O(plm_fsm_rc_counter_ts1_0_reg_tx_count_s[5]) + ); + MUXCY_L plm_fsm_rc_counter_ts1_0_reg_tx_count_cry_6_ ( + .CI(plm_fsm_rc_counter_ts1_0_reg_tx_count_cry[5]), + .DI(plm_fsm_rc_counter_ts1_0_VCC_1932), + .LO(plm_fsm_rc_counter_ts1_0_reg_tx_count_cry[6]), + .S(plm_fsm_rc_counter_ts1_0_reg_tx_count_qxu[6]) + ); + XORCY plm_fsm_rc_counter_ts1_0_reg_tx_count_s_6_ ( + .CI(plm_fsm_rc_counter_ts1_0_reg_tx_count_cry[5]), + .LI(plm_fsm_rc_counter_ts1_0_reg_tx_count_qxu[6]), + .O(plm_fsm_rc_counter_ts1_0_reg_tx_count_s[6]) + ); + XORCY plm_fsm_rc_counter_ts1_0_reg_tx_count_s_7_ ( + .CI(plm_fsm_rc_counter_ts1_0_reg_tx_count_cry[6]), + .LI(plm_fsm_rc_counter_ts1_0_reg_tx_count_qxu[7]), + .O(plm_fsm_rc_counter_ts1_0_reg_tx_count_s[7]) + ); + defparam plm_fsm_rc_counter_ts1_0_un1_enable_4_i_0_0_0_a2_0_1.INIT = 4'h2; + LUT2 plm_fsm_rc_counter_ts1_0_un1_enable_4_i_0_0_0_a2_0_1 ( + .I0(plm_reg_ts1_1), + .I1(plm_fsm_rc_counter_ts1_0_reg_rx_expired_318), + .O(plm_fsm_rc_counter_ts1_0_N_58806_1) + ); + defparam plm_fsm_rc_counter_ts1_0_un1_enable_1_0_a2_i_o2_i_a3_0_a2.INIT = 4'h4; + LUT2 plm_fsm_rc_counter_ts1_0_un1_enable_1_0_a2_i_o2_i_a3_0_a2 ( + .I0(N_29556_i), + .I1(plm_fsm_rc_counter_ts1_0_reg_oneshot_1935), + .O(plm_fsm_rc_counter_ts1_0_un1_enable_1_0_a2_i_o2_i_a3_0_a2_6) + ); + defparam plm_fsm_rc_counter_ts1_0_loadable_tx_counter_un1_reg_tx_count_0_a2_0_a3_4.INIT = 16'h0001; + LUT4 plm_fsm_rc_counter_ts1_0_loadable_tx_counter_un1_reg_tx_count_0_a2_0_a3_4 ( + .I0(plm_fsm_rc_counter_ts1_0_reg_tx_count[0]), + .I1(plm_fsm_rc_counter_ts1_0_reg_tx_count[1]), + .I2(plm_fsm_rc_counter_ts1_0_reg_tx_count[2]), + .I3(plm_fsm_rc_counter_ts1_0_reg_tx_count[3]), + .O(plm_fsm_rc_counter_ts1_0_un1_reg_tx_count_0_a2_0_a3_4) + ); + defparam plm_fsm_rc_counter_ts1_0_loadable_tx_counter_un1_reg_tx_count_0_a2_0_a3_5.INIT = 16'h0001; + LUT4 plm_fsm_rc_counter_ts1_0_loadable_tx_counter_un1_reg_tx_count_0_a2_0_a3_5 ( + .I0(plm_fsm_rc_counter_ts1_0_reg_tx_count[4]), + .I1(plm_fsm_rc_counter_ts1_0_reg_tx_count[5]), + .I2(plm_fsm_rc_counter_ts1_0_reg_tx_count[6]), + .I3(plm_fsm_rc_counter_ts1_0_reg_tx_count[7]), + .O(plm_fsm_rc_counter_ts1_0_un1_reg_tx_count_0_a2_0_a3_5) + ); + defparam plm_fsm_rc_counter_ts1_0_loadable_rx_counter_un1_reg_rx_count_0_a2_0_a3_4.INIT = 16'h0001; + LUT4 plm_fsm_rc_counter_ts1_0_loadable_rx_counter_un1_reg_rx_count_0_a2_0_a3_4 ( + .I0(plm_fsm_rc_counter_ts1_0_reg_rx_count[0]), + .I1(plm_fsm_rc_counter_ts1_0_reg_rx_count[1]), + .I2(plm_fsm_rc_counter_ts1_0_reg_rx_count[2]), + .I3(plm_fsm_rc_counter_ts1_0_reg_rx_count[3]), + .O(plm_fsm_rc_counter_ts1_0_un1_reg_rx_count_0_a2_0_a3_4) + ); + defparam plm_fsm_rc_counter_ts1_0_loadable_rx_counter_un1_reg_rx_count_0_a2_0_a3_5.INIT = 16'h0001; + LUT4 plm_fsm_rc_counter_ts1_0_loadable_rx_counter_un1_reg_rx_count_0_a2_0_a3_5 ( + .I0(plm_fsm_rc_counter_ts1_0_reg_rx_count[4]), + .I1(plm_fsm_rc_counter_ts1_0_reg_rx_count[5]), + .I2(plm_fsm_rc_counter_ts1_0_reg_rx_count[6]), + .I3(plm_fsm_rc_counter_ts1_0_reg_rx_count[7]), + .O(plm_fsm_rc_counter_ts1_0_un1_reg_rx_count_0_a2_0_a3_5) + ); + defparam plm_fsm_rc_counter_ts1_0_un1_enable_1_0_a2_i_i_a3_0_a2.INIT = 4'h2; + LUT2 plm_fsm_rc_counter_ts1_0_un1_enable_1_0_a2_i_i_a3_0_a2 ( + .I0(plm_fsm_rc_counter_ts1_0_un1_enable_1_0_a2_i_o2_i_a3_0_a2_6), + .I1(plm_fsm_rc_counter_ts1_0_reg_tx_expired_1937), + .O(plm_fsm_rc_counter_ts1_0_un1_enable_1_0_a2_i_i_a3_0_a2_1939) + ); + defparam plm_fsm_rc_counter_ts1_0_N_60925_i.INIT = 16'hFFEF; + LUT4 plm_fsm_rc_counter_ts1_0_N_60925_i ( + .I0(plm_reg_sym_sent_6_), + .I1(N_29556_i), + .I2(plm_fsm_rc_counter_ts1_0_reg_oneshot_1935), + .I3(plm_fsm_rc_counter_ts1_0_reg_tx_expired_1937), + .O(plm_fsm_rc_counter_ts1_0_N_60925_i_1934) + ); + defparam plm_fsm_rc_counter_ts1_0_N_60949_i.INIT = 8'hD5; + LUT3 plm_fsm_rc_counter_ts1_0_N_60949_i ( + .I0(plm_fsm_rc_counter_ts1_0_un1_enable_1_0_a2_i_o2_i_a3_0_a2_6), + .I1(plm_fsm_rc_counter_ts1_0_un1_reg_tx_count_0_a2_0_a3_4), + .I2(plm_fsm_rc_counter_ts1_0_un1_reg_tx_count_0_a2_0_a3_5), + .O(plm_fsm_rc_counter_ts1_0_N_60949_i_1936) + ); + defparam plm_fsm_rc_counter_ts1_0_loadable_rx_counter_N_60964_i.INIT = 8'hEA; + LUT3 plm_fsm_rc_counter_ts1_0_loadable_rx_counter_N_60964_i ( + .I0(N_29556_i), + .I1(plm_fsm_rc_counter_ts1_0_un1_reg_rx_count_0_a2_0_a3_4), + .I2(plm_fsm_rc_counter_ts1_0_un1_reg_rx_count_0_a2_0_a3_5), + .O(plm_fsm_rc_counter_ts1_0_N_60964_i) + ); + defparam plm_fsm_rc_counter_ts1_0_N_85508_i.INIT = 16'hEAFA; + LUT4 plm_fsm_rc_counter_ts1_0_N_85508_i ( + .I0(N_29556_i), + .I1(N_56052_i), + .I2(plm_fsm_rc_counter_ts1_0_N_58806_1), + .I3(plm_rx0_ts1_c), + .O(plm_fsm_rc_counter_ts1_0_N_85508_i_1938) + ); + defparam plm_fsm_rc_counter_ts1_0_flagit_reg_expired_5_0_a2_i_i_a3_0_a2.INIT = 8'h40; + LUT3_L plm_fsm_rc_counter_ts1_0_flagit_reg_expired_5_0_a2_i_i_a3_0_a2 ( + .I0(N_29556_i_1), + .I1(plm_fsm_rc_counter_ts1_0_reg_rx_expired_318), + .I2(plm_fsm_rc_counter_ts1_0_reg_tx_expired_1937), + .LO(plm_fsm_rc_counter_ts1_0_reg_expired_5_0_a2_i_i_a3_0_a2) + ); + defparam plm_fsm_rc_counter_ts1_0_loadable_rx_counter_N_60907_i.INIT = 8'hFE; + LUT3 plm_fsm_rc_counter_ts1_0_loadable_rx_counter_N_60907_i ( + .I0(plm_fsm_rc_counter_ts1_0_reg_rx_expired_318), + .I1(N_29556_i), + .I2(plm_reg_ts1_1), + .O(plm_fsm_rc_counter_ts1_0_N_60907_i) + ); + defparam plm_fsm_rc_counter_ts1_0_oneshot_monitor_N_60965_i.INIT = 4'hE; + LUT2 plm_fsm_rc_counter_ts1_0_oneshot_monitor_N_60965_i ( + .I0(N_29556_i), + .I1(plm_reg_ts1_1), + .O(plm_fsm_rc_counter_ts1_0_N_60965_i) + ); + defparam plm_fsm_rc_counter_ts1_0_N_60924_i.INIT = 4'hB; + LUT2 plm_fsm_rc_counter_ts1_0_N_60924_i ( + .I0(plm_fsm_rc_counter_ts1_0_reg_tx_expired_1937), + .I1(plm_fsm_rc_counter_ts1_0_un1_enable_1_0_a2_i_o2_i_a3_0_a2_6), + .O(plm_fsm_rc_counter_ts1_0_N_60924_i_1933) + ); + FDCE plm_fsm_rc_counter_ts1_0_reg_tx_count_7_ ( + .CE(plm_fsm_rc_counter_ts1_0_N_60925_i_1934), + .C(mgt_clk), + .D(plm_fsm_rc_counter_ts1_0_reg_tx_count_s[7]), + .Q(plm_fsm_rc_counter_ts1_0_reg_tx_count[7]), + .CLR(plm_rst) + ); + FDCE plm_fsm_rc_counter_ts1_0_reg_tx_count_6_ ( + .CE(plm_fsm_rc_counter_ts1_0_N_60925_i_1934), + .C(mgt_clk), + .D(plm_fsm_rc_counter_ts1_0_reg_tx_count_s[6]), + .Q(plm_fsm_rc_counter_ts1_0_reg_tx_count[6]), + .CLR(plm_rst) + ); + FDCE plm_fsm_rc_counter_ts1_0_reg_tx_count_5_ ( + .CE(plm_fsm_rc_counter_ts1_0_N_60925_i_1934), + .C(mgt_clk), + .D(plm_fsm_rc_counter_ts1_0_reg_tx_count_s[5]), + .Q(plm_fsm_rc_counter_ts1_0_reg_tx_count[5]), + .CLR(plm_rst) + ); + FDPE plm_fsm_rc_counter_ts1_0_reg_tx_count_4_ ( + .PRE(plm_rst), + .CE(plm_fsm_rc_counter_ts1_0_N_60925_i_1934), + .C(mgt_clk), + .D(plm_fsm_rc_counter_ts1_0_reg_tx_count_s[4]), + .Q(plm_fsm_rc_counter_ts1_0_reg_tx_count[4]) + ); + FDCE plm_fsm_rc_counter_ts1_0_reg_tx_count_3_ ( + .CE(plm_fsm_rc_counter_ts1_0_N_60925_i_1934), + .C(mgt_clk), + .D(plm_fsm_rc_counter_ts1_0_reg_tx_count_s[3]), + .Q(plm_fsm_rc_counter_ts1_0_reg_tx_count[3]), + .CLR(plm_rst) + ); + FDCE plm_fsm_rc_counter_ts1_0_reg_tx_count_2_ ( + .CE(plm_fsm_rc_counter_ts1_0_N_60925_i_1934), + .C(mgt_clk), + .D(plm_fsm_rc_counter_ts1_0_reg_tx_count_s[2]), + .Q(plm_fsm_rc_counter_ts1_0_reg_tx_count[2]), + .CLR(plm_rst) + ); + FDCE plm_fsm_rc_counter_ts1_0_reg_tx_count_1_ ( + .CE(plm_fsm_rc_counter_ts1_0_N_60925_i_1934), + .C(mgt_clk), + .D(plm_fsm_rc_counter_ts1_0_reg_tx_count_s[1]), + .Q(plm_fsm_rc_counter_ts1_0_reg_tx_count[1]), + .CLR(plm_rst) + ); + FDCE plm_fsm_rc_counter_ts1_0_reg_tx_count_0_ ( + .CE(plm_fsm_rc_counter_ts1_0_N_60925_i_1934), + .C(mgt_clk), + .D(plm_fsm_rc_counter_ts1_0_reg_tx_count_s[0]), + .Q(plm_fsm_rc_counter_ts1_0_reg_tx_count[0]), + .CLR(plm_rst) + ); + FDCE plm_fsm_rc_counter_ts1_0_reg_rx_count_7_ ( + .CE(plm_fsm_rc_counter_ts1_0_N_60907_i), + .C(mgt_clk), + .D(plm_fsm_rc_counter_ts1_0_reg_rx_count_s[7]), + .Q(plm_fsm_rc_counter_ts1_0_reg_rx_count[7]), + .CLR(plm_rst) + ); + FDCE plm_fsm_rc_counter_ts1_0_reg_rx_count_6_ ( + .CE(plm_fsm_rc_counter_ts1_0_N_60907_i), + .C(mgt_clk), + .D(plm_fsm_rc_counter_ts1_0_reg_rx_count_s[6]), + .Q(plm_fsm_rc_counter_ts1_0_reg_rx_count[6]), + .CLR(plm_rst) + ); + FDCE plm_fsm_rc_counter_ts1_0_reg_rx_count_5_ ( + .CE(plm_fsm_rc_counter_ts1_0_N_60907_i), + .C(mgt_clk), + .D(plm_fsm_rc_counter_ts1_0_reg_rx_count_s[5]), + .Q(plm_fsm_rc_counter_ts1_0_reg_rx_count[5]), + .CLR(plm_rst) + ); + FDCE plm_fsm_rc_counter_ts1_0_reg_rx_count_4_ ( + .CE(plm_fsm_rc_counter_ts1_0_N_60907_i), + .C(mgt_clk), + .D(plm_fsm_rc_counter_ts1_0_reg_rx_count_s[4]), + .Q(plm_fsm_rc_counter_ts1_0_reg_rx_count[4]), + .CLR(plm_rst) + ); + FDPE plm_fsm_rc_counter_ts1_0_reg_rx_count_3_ ( + .PRE(plm_rst), + .CE(plm_fsm_rc_counter_ts1_0_N_60907_i), + .C(mgt_clk), + .D(plm_fsm_rc_counter_ts1_0_reg_rx_count_s[3]), + .Q(plm_fsm_rc_counter_ts1_0_reg_rx_count[3]) + ); + FDCE plm_fsm_rc_counter_ts1_0_reg_rx_count_2_ ( + .CE(plm_fsm_rc_counter_ts1_0_N_60907_i), + .C(mgt_clk), + .D(plm_fsm_rc_counter_ts1_0_reg_rx_count_s[2]), + .Q(plm_fsm_rc_counter_ts1_0_reg_rx_count[2]), + .CLR(plm_rst) + ); + FDCE plm_fsm_rc_counter_ts1_0_reg_rx_count_1_ ( + .CE(plm_fsm_rc_counter_ts1_0_N_60907_i), + .C(mgt_clk), + .D(plm_fsm_rc_counter_ts1_0_reg_rx_count_s[1]), + .Q(plm_fsm_rc_counter_ts1_0_reg_rx_count[1]), + .CLR(plm_rst) + ); + FDCE plm_fsm_rc_counter_ts1_0_reg_rx_count_0_ ( + .CE(plm_fsm_rc_counter_ts1_0_N_60907_i), + .C(mgt_clk), + .D(plm_fsm_rc_counter_ts1_0_reg_rx_count_s[0]), + .Q(plm_fsm_rc_counter_ts1_0_reg_rx_count[0]), + .CLR(plm_rst) + ); + FDC plm_fsm_rc_counter_ts1_0_reg_expired ( + .C(mgt_clk), + .D(plm_fsm_rc_counter_ts1_0_reg_expired_5_0_a2_i_i_a3_0_a2), + .Q(plm_fsm_rc_cntrout_ts1_0), + .CLR(plm_rst) + ); + FDCE plm_fsm_rc_counter_ts1_0_reg_oneshot ( + .CE(plm_fsm_rc_counter_ts1_0_N_60965_i), + .C(mgt_clk), + .D(N_29556_i_0), + .Q(plm_fsm_rc_counter_ts1_0_reg_oneshot_1935), + .CLR(plm_rst) + ); + FDCE plm_fsm_rc_counter_ts1_0_reg_rx_expired ( + .CE(plm_fsm_rc_counter_ts1_0_N_60964_i), + .C(mgt_clk), + .D(N_29556_i_0), + .Q(plm_fsm_rc_counter_ts1_0_reg_rx_expired_318), + .CLR(plm_rst) + ); + FDCE plm_fsm_rc_counter_ts1_0_reg_tx_expired ( + .CE(plm_fsm_rc_counter_ts1_0_N_60949_i_1936), + .C(mgt_clk), + .D(plm_fsm_rc_counter_ts1_0_un1_enable_1_0_a2_i_o2_i_a3_0_a2_6), + .Q(plm_fsm_rc_counter_ts1_0_reg_tx_expired_1937), + .CLR(plm_rst) + ); + defparam plm_fsm_rc_counter_ts1_0_reg_rx_count_qxu_0_0_.INIT = 4'h7; + LUT2_L plm_fsm_rc_counter_ts1_0_reg_rx_count_qxu_0_0_ ( + .I0(N_28800_i), + .I1(plm_fsm_rc_counter_ts1_0_reg_rx_count[0]), + .LO(plm_fsm_rc_counter_ts1_0_reg_rx_count_qxu[0]) + ); + defparam plm_fsm_rc_counter_ts1_0_reg_rx_count_qxu_0_1_.INIT = 4'h7; + LUT2_L plm_fsm_rc_counter_ts1_0_reg_rx_count_qxu_0_1_ ( + .I0(N_28800_i), + .I1(plm_fsm_rc_counter_ts1_0_reg_rx_count[1]), + .LO(plm_fsm_rc_counter_ts1_0_reg_rx_count_qxu[1]) + ); + defparam plm_fsm_rc_counter_ts1_0_reg_rx_count_qxu_0_2_.INIT = 4'h7; + LUT2_L plm_fsm_rc_counter_ts1_0_reg_rx_count_qxu_0_2_ ( + .I0(N_28800_i), + .I1(plm_fsm_rc_counter_ts1_0_reg_rx_count[2]), + .LO(plm_fsm_rc_counter_ts1_0_reg_rx_count_qxu[2]) + ); + defparam plm_fsm_rc_counter_ts1_0_reg_rx_count_qxu_0_3_.INIT = 8'h1B; + LUT3_L plm_fsm_rc_counter_ts1_0_reg_rx_count_qxu_0_3_ ( + .I0(N_28800_i), + .I1(plm_fsm_rc_counter_ts1_0_N_85508_i_1938), + .I2(plm_fsm_rc_counter_ts1_0_reg_rx_count[3]), + .LO(plm_fsm_rc_counter_ts1_0_reg_rx_count_qxu[3]) + ); + defparam plm_fsm_rc_counter_ts1_0_reg_rx_count_qxu_0_4_.INIT = 4'h7; + LUT2_L plm_fsm_rc_counter_ts1_0_reg_rx_count_qxu_0_4_ ( + .I0(N_28800_i), + .I1(plm_fsm_rc_counter_ts1_0_reg_rx_count[4]), + .LO(plm_fsm_rc_counter_ts1_0_reg_rx_count_qxu[4]) + ); + defparam plm_fsm_rc_counter_ts1_0_reg_rx_count_qxu_0_5_.INIT = 4'h7; + LUT2_L plm_fsm_rc_counter_ts1_0_reg_rx_count_qxu_0_5_ ( + .I0(N_28800_i), + .I1(plm_fsm_rc_counter_ts1_0_reg_rx_count[5]), + .LO(plm_fsm_rc_counter_ts1_0_reg_rx_count_qxu[5]) + ); + defparam plm_fsm_rc_counter_ts1_0_reg_rx_count_qxu_0_6_.INIT = 4'h7; + LUT2_L plm_fsm_rc_counter_ts1_0_reg_rx_count_qxu_0_6_ ( + .I0(N_28800_i), + .I1(plm_fsm_rc_counter_ts1_0_reg_rx_count[6]), + .LO(plm_fsm_rc_counter_ts1_0_reg_rx_count_qxu[6]) + ); + defparam plm_fsm_rc_counter_ts1_0_reg_rx_count_qxu_0_7_.INIT = 4'h7; + LUT2_L plm_fsm_rc_counter_ts1_0_reg_rx_count_qxu_0_7_ ( + .I0(N_28800_i), + .I1(plm_fsm_rc_counter_ts1_0_reg_rx_count[7]), + .LO(plm_fsm_rc_counter_ts1_0_reg_rx_count_qxu[7]) + ); + defparam plm_fsm_rc_counter_ts1_0_reg_tx_count_qxu_0_0_.INIT = 4'h7; + LUT2_L plm_fsm_rc_counter_ts1_0_reg_tx_count_qxu_0_0_ ( + .I0(plm_fsm_rc_counter_ts1_0_un1_enable_1_0_a2_i_i_a3_0_a2_1939), + .I1(plm_fsm_rc_counter_ts1_0_reg_tx_count[0]), + .LO(plm_fsm_rc_counter_ts1_0_reg_tx_count_qxu[0]) + ); + defparam plm_fsm_rc_counter_ts1_0_reg_tx_count_qxu_0_1_.INIT = 4'h7; + LUT2_L plm_fsm_rc_counter_ts1_0_reg_tx_count_qxu_0_1_ ( + .I0(plm_fsm_rc_counter_ts1_0_un1_enable_1_0_a2_i_i_a3_0_a2_1939), + .I1(plm_fsm_rc_counter_ts1_0_reg_tx_count[1]), + .LO(plm_fsm_rc_counter_ts1_0_reg_tx_count_qxu[1]) + ); + defparam plm_fsm_rc_counter_ts1_0_reg_tx_count_qxu_0_2_.INIT = 4'h7; + LUT2_L plm_fsm_rc_counter_ts1_0_reg_tx_count_qxu_0_2_ ( + .I0(plm_fsm_rc_counter_ts1_0_un1_enable_1_0_a2_i_i_a3_0_a2_1939), + .I1(plm_fsm_rc_counter_ts1_0_reg_tx_count[2]), + .LO(plm_fsm_rc_counter_ts1_0_reg_tx_count_qxu[2]) + ); + defparam plm_fsm_rc_counter_ts1_0_reg_tx_count_qxu_0_3_.INIT = 4'h7; + LUT2_L plm_fsm_rc_counter_ts1_0_reg_tx_count_qxu_0_3_ ( + .I0(plm_fsm_rc_counter_ts1_0_un1_enable_1_0_a2_i_i_a3_0_a2_1939), + .I1(plm_fsm_rc_counter_ts1_0_reg_tx_count[3]), + .LO(plm_fsm_rc_counter_ts1_0_reg_tx_count_qxu[3]) + ); + defparam plm_fsm_rc_counter_ts1_0_reg_tx_count_qxu_0_4_.INIT = 8'h4E; + LUT3_L plm_fsm_rc_counter_ts1_0_reg_tx_count_qxu_0_4_ ( + .I0(plm_fsm_rc_counter_ts1_0_un1_enable_1_0_a2_i_i_a3_0_a2_1939), + .I1(plm_fsm_rc_counter_ts1_0_un1_enable_1_0_a2_i_o2_i_a3_0_a2_6), + .I2(plm_fsm_rc_counter_ts1_0_reg_tx_count[4]), + .LO(plm_fsm_rc_counter_ts1_0_reg_tx_count_qxu[4]) + ); + defparam plm_fsm_rc_counter_ts1_0_reg_tx_count_qxu_0_5_.INIT = 4'h7; + LUT2_L plm_fsm_rc_counter_ts1_0_reg_tx_count_qxu_0_5_ ( + .I0(plm_fsm_rc_counter_ts1_0_un1_enable_1_0_a2_i_i_a3_0_a2_1939), + .I1(plm_fsm_rc_counter_ts1_0_reg_tx_count[5]), + .LO(plm_fsm_rc_counter_ts1_0_reg_tx_count_qxu[5]) + ); + defparam plm_fsm_rc_counter_ts1_0_reg_tx_count_qxu_0_6_.INIT = 4'h7; + LUT2_L plm_fsm_rc_counter_ts1_0_reg_tx_count_qxu_0_6_ ( + .I0(plm_fsm_rc_counter_ts1_0_un1_enable_1_0_a2_i_i_a3_0_a2_1939), + .I1(plm_fsm_rc_counter_ts1_0_reg_tx_count[6]), + .LO(plm_fsm_rc_counter_ts1_0_reg_tx_count_qxu[6]) + ); + defparam plm_fsm_rc_counter_ts1_0_reg_tx_count_qxu_0_7_.INIT = 4'h7; + LUT2_L plm_fsm_rc_counter_ts1_0_reg_tx_count_qxu_0_7_ ( + .I0(plm_fsm_rc_counter_ts1_0_un1_enable_1_0_a2_i_i_a3_0_a2_1939), + .I1(plm_fsm_rc_counter_ts1_0_reg_tx_count[7]), + .LO(plm_fsm_rc_counter_ts1_0_reg_tx_count_qxu[7]) + ); + VCC plm_fsm_rc_counter_ts1_1_VCC ( + .P(plm_fsm_rc_counter_ts1_1_VCC_1940) + ); + MUXCY_L plm_fsm_rc_counter_ts1_1_reg_rx_count_cry_0_ ( + .CI(N_22977_i_i_25), + .DI(plm_fsm_rc_counter_ts1_1_VCC_1940), + .LO(plm_fsm_rc_counter_ts1_1_reg_rx_count_cry[0]), + .S(plm_fsm_rc_counter_ts1_1_reg_rx_count_qxu[0]) + ); + XORCY plm_fsm_rc_counter_ts1_1_reg_rx_count_s_0_ ( + .CI(N_22977_i_i_25), + .LI(plm_fsm_rc_counter_ts1_1_reg_rx_count_qxu[0]), + .O(plm_fsm_rc_counter_ts1_1_reg_rx_count_s[0]) + ); + MUXCY_L plm_fsm_rc_counter_ts1_1_reg_rx_count_cry_1_ ( + .CI(plm_fsm_rc_counter_ts1_1_reg_rx_count_cry[0]), + .DI(plm_fsm_rc_counter_ts1_1_VCC_1940), + .LO(plm_fsm_rc_counter_ts1_1_reg_rx_count_cry[1]), + .S(plm_fsm_rc_counter_ts1_1_reg_rx_count_qxu[1]) + ); + XORCY plm_fsm_rc_counter_ts1_1_reg_rx_count_s_1_ ( + .CI(plm_fsm_rc_counter_ts1_1_reg_rx_count_cry[0]), + .LI(plm_fsm_rc_counter_ts1_1_reg_rx_count_qxu[1]), + .O(plm_fsm_rc_counter_ts1_1_reg_rx_count_s[1]) + ); + MUXCY_L plm_fsm_rc_counter_ts1_1_reg_rx_count_cry_2_ ( + .CI(plm_fsm_rc_counter_ts1_1_reg_rx_count_cry[1]), + .DI(plm_fsm_rc_counter_ts1_1_VCC_1940), + .LO(plm_fsm_rc_counter_ts1_1_reg_rx_count_cry[2]), + .S(plm_fsm_rc_counter_ts1_1_reg_rx_count_qxu[2]) + ); + XORCY plm_fsm_rc_counter_ts1_1_reg_rx_count_s_2_ ( + .CI(plm_fsm_rc_counter_ts1_1_reg_rx_count_cry[1]), + .LI(plm_fsm_rc_counter_ts1_1_reg_rx_count_qxu[2]), + .O(plm_fsm_rc_counter_ts1_1_reg_rx_count_s[2]) + ); + MUXCY_L plm_fsm_rc_counter_ts1_1_reg_rx_count_cry_3_ ( + .CI(plm_fsm_rc_counter_ts1_1_reg_rx_count_cry[2]), + .DI(plm_fsm_rc_counter_ts1_1_VCC_1940), + .LO(plm_fsm_rc_counter_ts1_1_reg_rx_count_cry[3]), + .S(plm_fsm_rc_counter_ts1_1_reg_rx_count_qxu[3]) + ); + XORCY plm_fsm_rc_counter_ts1_1_reg_rx_count_s_3_ ( + .CI(plm_fsm_rc_counter_ts1_1_reg_rx_count_cry[2]), + .LI(plm_fsm_rc_counter_ts1_1_reg_rx_count_qxu[3]), + .O(plm_fsm_rc_counter_ts1_1_reg_rx_count_s[3]) + ); + MUXCY_L plm_fsm_rc_counter_ts1_1_reg_rx_count_cry_4_ ( + .CI(plm_fsm_rc_counter_ts1_1_reg_rx_count_cry[3]), + .DI(plm_fsm_rc_counter_ts1_1_VCC_1940), + .LO(plm_fsm_rc_counter_ts1_1_reg_rx_count_cry[4]), + .S(plm_fsm_rc_counter_ts1_1_reg_rx_count_qxu[4]) + ); + XORCY plm_fsm_rc_counter_ts1_1_reg_rx_count_s_4_ ( + .CI(plm_fsm_rc_counter_ts1_1_reg_rx_count_cry[3]), + .LI(plm_fsm_rc_counter_ts1_1_reg_rx_count_qxu[4]), + .O(plm_fsm_rc_counter_ts1_1_reg_rx_count_s[4]) + ); + MUXCY_L plm_fsm_rc_counter_ts1_1_reg_rx_count_cry_5_ ( + .CI(plm_fsm_rc_counter_ts1_1_reg_rx_count_cry[4]), + .DI(plm_fsm_rc_counter_ts1_1_VCC_1940), + .LO(plm_fsm_rc_counter_ts1_1_reg_rx_count_cry[5]), + .S(plm_fsm_rc_counter_ts1_1_reg_rx_count_qxu[5]) + ); + XORCY plm_fsm_rc_counter_ts1_1_reg_rx_count_s_5_ ( + .CI(plm_fsm_rc_counter_ts1_1_reg_rx_count_cry[4]), + .LI(plm_fsm_rc_counter_ts1_1_reg_rx_count_qxu[5]), + .O(plm_fsm_rc_counter_ts1_1_reg_rx_count_s[5]) + ); + MUXCY_L plm_fsm_rc_counter_ts1_1_reg_rx_count_cry_6_ ( + .CI(plm_fsm_rc_counter_ts1_1_reg_rx_count_cry[5]), + .DI(plm_fsm_rc_counter_ts1_1_VCC_1940), + .LO(plm_fsm_rc_counter_ts1_1_reg_rx_count_cry[6]), + .S(plm_fsm_rc_counter_ts1_1_reg_rx_count_qxu[6]) + ); + XORCY plm_fsm_rc_counter_ts1_1_reg_rx_count_s_6_ ( + .CI(plm_fsm_rc_counter_ts1_1_reg_rx_count_cry[5]), + .LI(plm_fsm_rc_counter_ts1_1_reg_rx_count_qxu[6]), + .O(plm_fsm_rc_counter_ts1_1_reg_rx_count_s[6]) + ); + XORCY plm_fsm_rc_counter_ts1_1_reg_rx_count_s_7_ ( + .CI(plm_fsm_rc_counter_ts1_1_reg_rx_count_cry[6]), + .LI(plm_fsm_rc_counter_ts1_1_reg_rx_count_qxu[7]), + .O(plm_fsm_rc_counter_ts1_1_reg_rx_count_s[7]) + ); + MUXCY_L plm_fsm_rc_counter_ts1_1_reg_tx_count_cry_0_ ( + .CI(plm_fsm_rc_counter_ts1_1_N_60923_i_1941), + .DI(plm_fsm_rc_counter_ts1_1_VCC_1940), + .LO(plm_fsm_rc_counter_ts1_1_reg_tx_count_cry[0]), + .S(plm_fsm_rc_counter_ts1_1_reg_tx_count_qxu[0]) + ); + XORCY plm_fsm_rc_counter_ts1_1_reg_tx_count_s_0_ ( + .CI(plm_fsm_rc_counter_ts1_1_N_60923_i_1941), + .LI(plm_fsm_rc_counter_ts1_1_reg_tx_count_qxu[0]), + .O(plm_fsm_rc_counter_ts1_1_reg_tx_count_s[0]) + ); + MUXCY_L plm_fsm_rc_counter_ts1_1_reg_tx_count_cry_1_ ( + .CI(plm_fsm_rc_counter_ts1_1_reg_tx_count_cry[0]), + .DI(plm_fsm_rc_counter_ts1_1_VCC_1940), + .LO(plm_fsm_rc_counter_ts1_1_reg_tx_count_cry[1]), + .S(plm_fsm_rc_counter_ts1_1_reg_tx_count_qxu[1]) + ); + XORCY plm_fsm_rc_counter_ts1_1_reg_tx_count_s_1_ ( + .CI(plm_fsm_rc_counter_ts1_1_reg_tx_count_cry[0]), + .LI(plm_fsm_rc_counter_ts1_1_reg_tx_count_qxu[1]), + .O(plm_fsm_rc_counter_ts1_1_reg_tx_count_s[1]) + ); + MUXCY_L plm_fsm_rc_counter_ts1_1_reg_tx_count_cry_2_ ( + .CI(plm_fsm_rc_counter_ts1_1_reg_tx_count_cry[1]), + .DI(plm_fsm_rc_counter_ts1_1_VCC_1940), + .LO(plm_fsm_rc_counter_ts1_1_reg_tx_count_cry[2]), + .S(plm_fsm_rc_counter_ts1_1_reg_tx_count_qxu[2]) + ); + XORCY plm_fsm_rc_counter_ts1_1_reg_tx_count_s_2_ ( + .CI(plm_fsm_rc_counter_ts1_1_reg_tx_count_cry[1]), + .LI(plm_fsm_rc_counter_ts1_1_reg_tx_count_qxu[2]), + .O(plm_fsm_rc_counter_ts1_1_reg_tx_count_s[2]) + ); + MUXCY_L plm_fsm_rc_counter_ts1_1_reg_tx_count_cry_3_ ( + .CI(plm_fsm_rc_counter_ts1_1_reg_tx_count_cry[2]), + .DI(plm_fsm_rc_counter_ts1_1_VCC_1940), + .LO(plm_fsm_rc_counter_ts1_1_reg_tx_count_cry[3]), + .S(plm_fsm_rc_counter_ts1_1_reg_tx_count_qxu[3]) + ); + XORCY plm_fsm_rc_counter_ts1_1_reg_tx_count_s_3_ ( + .CI(plm_fsm_rc_counter_ts1_1_reg_tx_count_cry[2]), + .LI(plm_fsm_rc_counter_ts1_1_reg_tx_count_qxu[3]), + .O(plm_fsm_rc_counter_ts1_1_reg_tx_count_s[3]) + ); + MUXCY_L plm_fsm_rc_counter_ts1_1_reg_tx_count_cry_4_ ( + .CI(plm_fsm_rc_counter_ts1_1_reg_tx_count_cry[3]), + .DI(plm_fsm_rc_counter_ts1_1_VCC_1940), + .LO(plm_fsm_rc_counter_ts1_1_reg_tx_count_cry[4]), + .S(plm_fsm_rc_counter_ts1_1_reg_tx_count_qxu[4]) + ); + XORCY plm_fsm_rc_counter_ts1_1_reg_tx_count_s_4_ ( + .CI(plm_fsm_rc_counter_ts1_1_reg_tx_count_cry[3]), + .LI(plm_fsm_rc_counter_ts1_1_reg_tx_count_qxu[4]), + .O(plm_fsm_rc_counter_ts1_1_reg_tx_count_s[4]) + ); + MUXCY_L plm_fsm_rc_counter_ts1_1_reg_tx_count_cry_5_ ( + .CI(plm_fsm_rc_counter_ts1_1_reg_tx_count_cry[4]), + .DI(plm_fsm_rc_counter_ts1_1_VCC_1940), + .LO(plm_fsm_rc_counter_ts1_1_reg_tx_count_cry[5]), + .S(plm_fsm_rc_counter_ts1_1_reg_tx_count_qxu[5]) + ); + XORCY plm_fsm_rc_counter_ts1_1_reg_tx_count_s_5_ ( + .CI(plm_fsm_rc_counter_ts1_1_reg_tx_count_cry[4]), + .LI(plm_fsm_rc_counter_ts1_1_reg_tx_count_qxu[5]), + .O(plm_fsm_rc_counter_ts1_1_reg_tx_count_s[5]) + ); + MUXCY_L plm_fsm_rc_counter_ts1_1_reg_tx_count_cry_6_ ( + .CI(plm_fsm_rc_counter_ts1_1_reg_tx_count_cry[5]), + .DI(plm_fsm_rc_counter_ts1_1_VCC_1940), + .LO(plm_fsm_rc_counter_ts1_1_reg_tx_count_cry[6]), + .S(plm_fsm_rc_counter_ts1_1_reg_tx_count_qxu[6]) + ); + XORCY plm_fsm_rc_counter_ts1_1_reg_tx_count_s_6_ ( + .CI(plm_fsm_rc_counter_ts1_1_reg_tx_count_cry[5]), + .LI(plm_fsm_rc_counter_ts1_1_reg_tx_count_qxu[6]), + .O(plm_fsm_rc_counter_ts1_1_reg_tx_count_s[6]) + ); + XORCY plm_fsm_rc_counter_ts1_1_reg_tx_count_s_7_ ( + .CI(plm_fsm_rc_counter_ts1_1_reg_tx_count_cry[6]), + .LI(plm_fsm_rc_counter_ts1_1_reg_tx_count_qxu[7]), + .O(plm_fsm_rc_counter_ts1_1_reg_tx_count_s[7]) + ); + defparam plm_fsm_rc_counter_ts1_1_un1_enable_4_i_0_0_a2_0_1.INIT = 4'h2; + LUT2 plm_fsm_rc_counter_ts1_1_un1_enable_4_i_0_0_a2_0_1 ( + .I0(plm_reg_ts1_1_0), + .I1(plm_fsm_rc_counter_ts1_1_reg_rx_expired_316), + .O(plm_fsm_rc_counter_ts1_1_N_59109_1) + ); + defparam plm_fsm_rc_counter_ts1_1_un1_enable_1_0_a2_i_o2_i_a3_0_a2.INIT = 4'h4; + LUT2 plm_fsm_rc_counter_ts1_1_un1_enable_1_0_a2_i_o2_i_a3_0_a2 ( + .I0(N_29556_i), + .I1(plm_fsm_rc_counter_ts1_1_reg_oneshot_1943), + .O(plm_fsm_rc_counter_ts1_1_un1_enable_1_0_a2_i_o2_i_a3_0_a2_5) + ); + defparam plm_fsm_rc_counter_ts1_1_loadable_rx_counter_un1_reg_rx_count_0_a2_0_a3_4.INIT = 16'h0001; + LUT4 plm_fsm_rc_counter_ts1_1_loadable_rx_counter_un1_reg_rx_count_0_a2_0_a3_4 ( + .I0(plm_fsm_rc_counter_ts1_1_reg_rx_count[0]), + .I1(plm_fsm_rc_counter_ts1_1_reg_rx_count[1]), + .I2(plm_fsm_rc_counter_ts1_1_reg_rx_count[2]), + .I3(plm_fsm_rc_counter_ts1_1_reg_rx_count[3]), + .O(plm_fsm_rc_counter_ts1_1_un1_reg_rx_count_0_a2_0_a3_4) + ); + defparam plm_fsm_rc_counter_ts1_1_loadable_rx_counter_un1_reg_rx_count_0_a2_0_a3_5.INIT = 16'h0001; + LUT4 plm_fsm_rc_counter_ts1_1_loadable_rx_counter_un1_reg_rx_count_0_a2_0_a3_5 ( + .I0(plm_fsm_rc_counter_ts1_1_reg_rx_count[4]), + .I1(plm_fsm_rc_counter_ts1_1_reg_rx_count[5]), + .I2(plm_fsm_rc_counter_ts1_1_reg_rx_count[6]), + .I3(plm_fsm_rc_counter_ts1_1_reg_rx_count[7]), + .O(plm_fsm_rc_counter_ts1_1_un1_reg_rx_count_0_a2_0_a3_5) + ); + defparam plm_fsm_rc_counter_ts1_1_loadable_tx_counter_un1_reg_tx_count_0_a2_0_a3_4.INIT = 16'h0001; + LUT4 plm_fsm_rc_counter_ts1_1_loadable_tx_counter_un1_reg_tx_count_0_a2_0_a3_4 ( + .I0(plm_fsm_rc_counter_ts1_1_reg_tx_count[0]), + .I1(plm_fsm_rc_counter_ts1_1_reg_tx_count[1]), + .I2(plm_fsm_rc_counter_ts1_1_reg_tx_count[2]), + .I3(plm_fsm_rc_counter_ts1_1_reg_tx_count[3]), + .O(plm_fsm_rc_counter_ts1_1_un1_reg_tx_count_0_a2_0_a3_4) + ); + defparam plm_fsm_rc_counter_ts1_1_loadable_tx_counter_un1_reg_tx_count_0_a2_0_a3_5.INIT = 16'h0001; + LUT4 plm_fsm_rc_counter_ts1_1_loadable_tx_counter_un1_reg_tx_count_0_a2_0_a3_5 ( + .I0(plm_fsm_rc_counter_ts1_1_reg_tx_count[4]), + .I1(plm_fsm_rc_counter_ts1_1_reg_tx_count[5]), + .I2(plm_fsm_rc_counter_ts1_1_reg_tx_count[6]), + .I3(plm_fsm_rc_counter_ts1_1_reg_tx_count[7]), + .O(plm_fsm_rc_counter_ts1_1_un1_reg_tx_count_0_a2_0_a3_5) + ); + defparam plm_fsm_rc_counter_ts1_1_un1_enable_1_0_a2_i_i_a3_0_a2.INIT = 4'h2; + LUT2 plm_fsm_rc_counter_ts1_1_un1_enable_1_0_a2_i_i_a3_0_a2 ( + .I0(plm_fsm_rc_counter_ts1_1_un1_enable_1_0_a2_i_o2_i_a3_0_a2_5), + .I1(plm_fsm_rc_counter_ts1_1_reg_tx_expired_1945), + .O(plm_fsm_rc_counter_ts1_1_un1_enable_1_0_a2_i_i_a3_0_a2_0) + ); + defparam plm_fsm_rc_counter_ts1_1_N_60926_i.INIT = 16'hFFEF; + LUT4 plm_fsm_rc_counter_ts1_1_N_60926_i ( + .I0(plm_reg_sym_sent_6_), + .I1(N_29556_i), + .I2(plm_fsm_rc_counter_ts1_1_reg_oneshot_1943), + .I3(plm_fsm_rc_counter_ts1_1_reg_tx_expired_1945), + .O(plm_fsm_rc_counter_ts1_1_N_60926_i_1942) + ); + defparam plm_fsm_rc_counter_ts1_1_N_60947_i.INIT = 8'hD5; + LUT3 plm_fsm_rc_counter_ts1_1_N_60947_i ( + .I0(plm_fsm_rc_counter_ts1_1_un1_enable_1_0_a2_i_o2_i_a3_0_a2_5), + .I1(plm_fsm_rc_counter_ts1_1_un1_reg_tx_count_0_a2_0_a3_4), + .I2(plm_fsm_rc_counter_ts1_1_un1_reg_tx_count_0_a2_0_a3_5), + .O(plm_fsm_rc_counter_ts1_1_N_60947_i_1944) + ); + defparam plm_fsm_rc_counter_ts1_1_loadable_rx_counter_N_60962_i.INIT = 8'hEA; + LUT3 plm_fsm_rc_counter_ts1_1_loadable_rx_counter_N_60962_i ( + .I0(N_29556_i), + .I1(plm_fsm_rc_counter_ts1_1_un1_reg_rx_count_0_a2_0_a3_4), + .I2(plm_fsm_rc_counter_ts1_1_un1_reg_rx_count_0_a2_0_a3_5), + .O(plm_fsm_rc_counter_ts1_1_N_60962_i) + ); + defparam plm_fsm_rc_counter_ts1_1_N_85658_i.INIT = 16'hEAFA; + LUT4 plm_fsm_rc_counter_ts1_1_N_85658_i ( + .I0(N_29556_i), + .I1(N_56029_i), + .I2(plm_fsm_rc_counter_ts1_1_N_59109_1), + .I3(plm_rx1_ts1_c), + .O(plm_fsm_rc_counter_ts1_1_N_85658_i_1946) + ); + defparam plm_fsm_rc_counter_ts1_1_flagit_reg_expired_5_0_a2_i_i_a3_0_a2.INIT = 8'h40; + LUT3_L plm_fsm_rc_counter_ts1_1_flagit_reg_expired_5_0_a2_i_i_a3_0_a2 ( + .I0(N_29556_i_1), + .I1(plm_fsm_rc_counter_ts1_1_reg_rx_expired_316), + .I2(plm_fsm_rc_counter_ts1_1_reg_tx_expired_1945), + .LO(plm_fsm_rc_counter_ts1_1_reg_expired_5_0_a2_i_i_a3_0_a2_0) + ); + defparam plm_fsm_rc_counter_ts1_1_loadable_rx_counter_N_60909_i.INIT = 8'hFE; + LUT3 plm_fsm_rc_counter_ts1_1_loadable_rx_counter_N_60909_i ( + .I0(plm_fsm_rc_counter_ts1_1_reg_rx_expired_316), + .I1(N_29556_i), + .I2(plm_reg_ts1_1_0), + .O(plm_fsm_rc_counter_ts1_1_N_60909_i) + ); + defparam plm_fsm_rc_counter_ts1_1_oneshot_monitor_N_60963_i.INIT = 4'hE; + LUT2 plm_fsm_rc_counter_ts1_1_oneshot_monitor_N_60963_i ( + .I0(N_29556_i), + .I1(plm_reg_ts1_1_0), + .O(plm_fsm_rc_counter_ts1_1_N_60963_i) + ); + defparam plm_fsm_rc_counter_ts1_1_N_60923_i.INIT = 4'hB; + LUT2 plm_fsm_rc_counter_ts1_1_N_60923_i ( + .I0(plm_fsm_rc_counter_ts1_1_reg_tx_expired_1945), + .I1(plm_fsm_rc_counter_ts1_1_un1_enable_1_0_a2_i_o2_i_a3_0_a2_5), + .O(plm_fsm_rc_counter_ts1_1_N_60923_i_1941) + ); + FDCE plm_fsm_rc_counter_ts1_1_reg_tx_count_7_ ( + .CE(plm_fsm_rc_counter_ts1_1_N_60926_i_1942), + .C(mgt_clk), + .D(plm_fsm_rc_counter_ts1_1_reg_tx_count_s[7]), + .Q(plm_fsm_rc_counter_ts1_1_reg_tx_count[7]), + .CLR(plm_rst) + ); + FDCE plm_fsm_rc_counter_ts1_1_reg_tx_count_6_ ( + .CE(plm_fsm_rc_counter_ts1_1_N_60926_i_1942), + .C(mgt_clk), + .D(plm_fsm_rc_counter_ts1_1_reg_tx_count_s[6]), + .Q(plm_fsm_rc_counter_ts1_1_reg_tx_count[6]), + .CLR(plm_rst) + ); + FDCE plm_fsm_rc_counter_ts1_1_reg_tx_count_5_ ( + .CE(plm_fsm_rc_counter_ts1_1_N_60926_i_1942), + .C(mgt_clk), + .D(plm_fsm_rc_counter_ts1_1_reg_tx_count_s[5]), + .Q(plm_fsm_rc_counter_ts1_1_reg_tx_count[5]), + .CLR(plm_rst) + ); + FDPE plm_fsm_rc_counter_ts1_1_reg_tx_count_4_ ( + .PRE(plm_rst), + .CE(plm_fsm_rc_counter_ts1_1_N_60926_i_1942), + .C(mgt_clk), + .D(plm_fsm_rc_counter_ts1_1_reg_tx_count_s[4]), + .Q(plm_fsm_rc_counter_ts1_1_reg_tx_count[4]) + ); + FDCE plm_fsm_rc_counter_ts1_1_reg_tx_count_3_ ( + .CE(plm_fsm_rc_counter_ts1_1_N_60926_i_1942), + .C(mgt_clk), + .D(plm_fsm_rc_counter_ts1_1_reg_tx_count_s[3]), + .Q(plm_fsm_rc_counter_ts1_1_reg_tx_count[3]), + .CLR(plm_rst) + ); + FDCE plm_fsm_rc_counter_ts1_1_reg_tx_count_2_ ( + .CE(plm_fsm_rc_counter_ts1_1_N_60926_i_1942), + .C(mgt_clk), + .D(plm_fsm_rc_counter_ts1_1_reg_tx_count_s[2]), + .Q(plm_fsm_rc_counter_ts1_1_reg_tx_count[2]), + .CLR(plm_rst) + ); + FDCE plm_fsm_rc_counter_ts1_1_reg_tx_count_1_ ( + .CE(plm_fsm_rc_counter_ts1_1_N_60926_i_1942), + .C(mgt_clk), + .D(plm_fsm_rc_counter_ts1_1_reg_tx_count_s[1]), + .Q(plm_fsm_rc_counter_ts1_1_reg_tx_count[1]), + .CLR(plm_rst) + ); + FDCE plm_fsm_rc_counter_ts1_1_reg_tx_count_0_ ( + .CE(plm_fsm_rc_counter_ts1_1_N_60926_i_1942), + .C(mgt_clk), + .D(plm_fsm_rc_counter_ts1_1_reg_tx_count_s[0]), + .Q(plm_fsm_rc_counter_ts1_1_reg_tx_count[0]), + .CLR(plm_rst) + ); + FDCE plm_fsm_rc_counter_ts1_1_reg_rx_count_7_ ( + .CE(plm_fsm_rc_counter_ts1_1_N_60909_i), + .C(mgt_clk), + .D(plm_fsm_rc_counter_ts1_1_reg_rx_count_s[7]), + .Q(plm_fsm_rc_counter_ts1_1_reg_rx_count[7]), + .CLR(plm_rst) + ); + FDCE plm_fsm_rc_counter_ts1_1_reg_rx_count_6_ ( + .CE(plm_fsm_rc_counter_ts1_1_N_60909_i), + .C(mgt_clk), + .D(plm_fsm_rc_counter_ts1_1_reg_rx_count_s[6]), + .Q(plm_fsm_rc_counter_ts1_1_reg_rx_count[6]), + .CLR(plm_rst) + ); + FDCE plm_fsm_rc_counter_ts1_1_reg_rx_count_5_ ( + .CE(plm_fsm_rc_counter_ts1_1_N_60909_i), + .C(mgt_clk), + .D(plm_fsm_rc_counter_ts1_1_reg_rx_count_s[5]), + .Q(plm_fsm_rc_counter_ts1_1_reg_rx_count[5]), + .CLR(plm_rst) + ); + FDCE plm_fsm_rc_counter_ts1_1_reg_rx_count_4_ ( + .CE(plm_fsm_rc_counter_ts1_1_N_60909_i), + .C(mgt_clk), + .D(plm_fsm_rc_counter_ts1_1_reg_rx_count_s[4]), + .Q(plm_fsm_rc_counter_ts1_1_reg_rx_count[4]), + .CLR(plm_rst) + ); + FDPE plm_fsm_rc_counter_ts1_1_reg_rx_count_3_ ( + .PRE(plm_rst), + .CE(plm_fsm_rc_counter_ts1_1_N_60909_i), + .C(mgt_clk), + .D(plm_fsm_rc_counter_ts1_1_reg_rx_count_s[3]), + .Q(plm_fsm_rc_counter_ts1_1_reg_rx_count[3]) + ); + FDCE plm_fsm_rc_counter_ts1_1_reg_rx_count_2_ ( + .CE(plm_fsm_rc_counter_ts1_1_N_60909_i), + .C(mgt_clk), + .D(plm_fsm_rc_counter_ts1_1_reg_rx_count_s[2]), + .Q(plm_fsm_rc_counter_ts1_1_reg_rx_count[2]), + .CLR(plm_rst) + ); + FDCE plm_fsm_rc_counter_ts1_1_reg_rx_count_1_ ( + .CE(plm_fsm_rc_counter_ts1_1_N_60909_i), + .C(mgt_clk), + .D(plm_fsm_rc_counter_ts1_1_reg_rx_count_s[1]), + .Q(plm_fsm_rc_counter_ts1_1_reg_rx_count[1]), + .CLR(plm_rst) + ); + FDCE plm_fsm_rc_counter_ts1_1_reg_rx_count_0_ ( + .CE(plm_fsm_rc_counter_ts1_1_N_60909_i), + .C(mgt_clk), + .D(plm_fsm_rc_counter_ts1_1_reg_rx_count_s[0]), + .Q(plm_fsm_rc_counter_ts1_1_reg_rx_count[0]), + .CLR(plm_rst) + ); + FDC plm_fsm_rc_counter_ts1_1_reg_expired ( + .C(mgt_clk), + .D(plm_fsm_rc_counter_ts1_1_reg_expired_5_0_a2_i_i_a3_0_a2_0), + .Q(plm_fsm_rc_cntrout_ts1_1), + .CLR(plm_rst) + ); + FDCE plm_fsm_rc_counter_ts1_1_reg_oneshot ( + .CE(plm_fsm_rc_counter_ts1_1_N_60963_i), + .C(mgt_clk), + .D(N_29556_i_0), + .Q(plm_fsm_rc_counter_ts1_1_reg_oneshot_1943), + .CLR(plm_rst) + ); + FDCE plm_fsm_rc_counter_ts1_1_reg_rx_expired ( + .CE(plm_fsm_rc_counter_ts1_1_N_60962_i), + .C(mgt_clk), + .D(N_29556_i_0), + .Q(plm_fsm_rc_counter_ts1_1_reg_rx_expired_316), + .CLR(plm_rst) + ); + FDCE plm_fsm_rc_counter_ts1_1_reg_tx_expired ( + .CE(plm_fsm_rc_counter_ts1_1_N_60947_i_1944), + .C(mgt_clk), + .D(plm_fsm_rc_counter_ts1_1_un1_enable_1_0_a2_i_o2_i_a3_0_a2_5), + .Q(plm_fsm_rc_counter_ts1_1_reg_tx_expired_1945), + .CLR(plm_rst) + ); + defparam plm_fsm_rc_counter_ts1_1_reg_rx_count_qxu_0_0_.INIT = 4'h7; + LUT2_L plm_fsm_rc_counter_ts1_1_reg_rx_count_qxu_0_0_ ( + .I0(N_22977_i), + .I1(plm_fsm_rc_counter_ts1_1_reg_rx_count[0]), + .LO(plm_fsm_rc_counter_ts1_1_reg_rx_count_qxu[0]) + ); + defparam plm_fsm_rc_counter_ts1_1_reg_rx_count_qxu_0_1_.INIT = 4'h7; + LUT2_L plm_fsm_rc_counter_ts1_1_reg_rx_count_qxu_0_1_ ( + .I0(N_22977_i), + .I1(plm_fsm_rc_counter_ts1_1_reg_rx_count[1]), + .LO(plm_fsm_rc_counter_ts1_1_reg_rx_count_qxu[1]) + ); + defparam plm_fsm_rc_counter_ts1_1_reg_rx_count_qxu_0_2_.INIT = 4'h7; + LUT2_L plm_fsm_rc_counter_ts1_1_reg_rx_count_qxu_0_2_ ( + .I0(N_22977_i), + .I1(plm_fsm_rc_counter_ts1_1_reg_rx_count[2]), + .LO(plm_fsm_rc_counter_ts1_1_reg_rx_count_qxu[2]) + ); + defparam plm_fsm_rc_counter_ts1_1_reg_rx_count_qxu_0_3_.INIT = 8'h1B; + LUT3_L plm_fsm_rc_counter_ts1_1_reg_rx_count_qxu_0_3_ ( + .I0(N_22977_i), + .I1(plm_fsm_rc_counter_ts1_1_N_85658_i_1946), + .I2(plm_fsm_rc_counter_ts1_1_reg_rx_count[3]), + .LO(plm_fsm_rc_counter_ts1_1_reg_rx_count_qxu[3]) + ); + defparam plm_fsm_rc_counter_ts1_1_reg_rx_count_qxu_0_4_.INIT = 4'h7; + LUT2_L plm_fsm_rc_counter_ts1_1_reg_rx_count_qxu_0_4_ ( + .I0(N_22977_i), + .I1(plm_fsm_rc_counter_ts1_1_reg_rx_count[4]), + .LO(plm_fsm_rc_counter_ts1_1_reg_rx_count_qxu[4]) + ); + defparam plm_fsm_rc_counter_ts1_1_reg_rx_count_qxu_0_5_.INIT = 4'h7; + LUT2_L plm_fsm_rc_counter_ts1_1_reg_rx_count_qxu_0_5_ ( + .I0(N_22977_i), + .I1(plm_fsm_rc_counter_ts1_1_reg_rx_count[5]), + .LO(plm_fsm_rc_counter_ts1_1_reg_rx_count_qxu[5]) + ); + defparam plm_fsm_rc_counter_ts1_1_reg_rx_count_qxu_0_6_.INIT = 4'h7; + LUT2_L plm_fsm_rc_counter_ts1_1_reg_rx_count_qxu_0_6_ ( + .I0(N_22977_i), + .I1(plm_fsm_rc_counter_ts1_1_reg_rx_count[6]), + .LO(plm_fsm_rc_counter_ts1_1_reg_rx_count_qxu[6]) + ); + defparam plm_fsm_rc_counter_ts1_1_reg_rx_count_qxu_0_7_.INIT = 4'h7; + LUT2_L plm_fsm_rc_counter_ts1_1_reg_rx_count_qxu_0_7_ ( + .I0(N_22977_i), + .I1(plm_fsm_rc_counter_ts1_1_reg_rx_count[7]), + .LO(plm_fsm_rc_counter_ts1_1_reg_rx_count_qxu[7]) + ); + defparam plm_fsm_rc_counter_ts1_1_reg_tx_count_qxu_0_0_.INIT = 4'h7; + LUT2_L plm_fsm_rc_counter_ts1_1_reg_tx_count_qxu_0_0_ ( + .I0(plm_fsm_rc_counter_ts1_1_un1_enable_1_0_a2_i_i_a3_0_a2_0), + .I1(plm_fsm_rc_counter_ts1_1_reg_tx_count[0]), + .LO(plm_fsm_rc_counter_ts1_1_reg_tx_count_qxu[0]) + ); + defparam plm_fsm_rc_counter_ts1_1_reg_tx_count_qxu_0_1_.INIT = 4'h7; + LUT2_L plm_fsm_rc_counter_ts1_1_reg_tx_count_qxu_0_1_ ( + .I0(plm_fsm_rc_counter_ts1_1_un1_enable_1_0_a2_i_i_a3_0_a2_0), + .I1(plm_fsm_rc_counter_ts1_1_reg_tx_count[1]), + .LO(plm_fsm_rc_counter_ts1_1_reg_tx_count_qxu[1]) + ); + defparam plm_fsm_rc_counter_ts1_1_reg_tx_count_qxu_0_2_.INIT = 4'h7; + LUT2_L plm_fsm_rc_counter_ts1_1_reg_tx_count_qxu_0_2_ ( + .I0(plm_fsm_rc_counter_ts1_1_un1_enable_1_0_a2_i_i_a3_0_a2_0), + .I1(plm_fsm_rc_counter_ts1_1_reg_tx_count[2]), + .LO(plm_fsm_rc_counter_ts1_1_reg_tx_count_qxu[2]) + ); + defparam plm_fsm_rc_counter_ts1_1_reg_tx_count_qxu_0_3_.INIT = 4'h7; + LUT2_L plm_fsm_rc_counter_ts1_1_reg_tx_count_qxu_0_3_ ( + .I0(plm_fsm_rc_counter_ts1_1_un1_enable_1_0_a2_i_i_a3_0_a2_0), + .I1(plm_fsm_rc_counter_ts1_1_reg_tx_count[3]), + .LO(plm_fsm_rc_counter_ts1_1_reg_tx_count_qxu[3]) + ); + defparam plm_fsm_rc_counter_ts1_1_reg_tx_count_qxu_0_4_.INIT = 8'h4E; + LUT3_L plm_fsm_rc_counter_ts1_1_reg_tx_count_qxu_0_4_ ( + .I0(plm_fsm_rc_counter_ts1_1_un1_enable_1_0_a2_i_i_a3_0_a2_0), + .I1(plm_fsm_rc_counter_ts1_1_un1_enable_1_0_a2_i_o2_i_a3_0_a2_5), + .I2(plm_fsm_rc_counter_ts1_1_reg_tx_count[4]), + .LO(plm_fsm_rc_counter_ts1_1_reg_tx_count_qxu[4]) + ); + defparam plm_fsm_rc_counter_ts1_1_reg_tx_count_qxu_0_5_.INIT = 4'h7; + LUT2_L plm_fsm_rc_counter_ts1_1_reg_tx_count_qxu_0_5_ ( + .I0(plm_fsm_rc_counter_ts1_1_un1_enable_1_0_a2_i_i_a3_0_a2_0), + .I1(plm_fsm_rc_counter_ts1_1_reg_tx_count[5]), + .LO(plm_fsm_rc_counter_ts1_1_reg_tx_count_qxu[5]) + ); + defparam plm_fsm_rc_counter_ts1_1_reg_tx_count_qxu_0_6_.INIT = 4'h7; + LUT2_L plm_fsm_rc_counter_ts1_1_reg_tx_count_qxu_0_6_ ( + .I0(plm_fsm_rc_counter_ts1_1_un1_enable_1_0_a2_i_i_a3_0_a2_0), + .I1(plm_fsm_rc_counter_ts1_1_reg_tx_count[6]), + .LO(plm_fsm_rc_counter_ts1_1_reg_tx_count_qxu[6]) + ); + defparam plm_fsm_rc_counter_ts1_1_reg_tx_count_qxu_0_7_.INIT = 4'h7; + LUT2_L plm_fsm_rc_counter_ts1_1_reg_tx_count_qxu_0_7_ ( + .I0(plm_fsm_rc_counter_ts1_1_un1_enable_1_0_a2_i_i_a3_0_a2_0), + .I1(plm_fsm_rc_counter_ts1_1_reg_tx_count[7]), + .LO(plm_fsm_rc_counter_ts1_1_reg_tx_count_qxu[7]) + ); + VCC plm_fsm_rc_counter_ts1_2_VCC ( + .P(plm_fsm_rc_counter_ts1_2_VCC_1947) + ); + MUXCY_L plm_fsm_rc_counter_ts1_2_reg_rx_count_cry_0_ ( + .CI(N_15212_i_i_26), + .DI(plm_fsm_rc_counter_ts1_2_VCC_1947), + .LO(plm_fsm_rc_counter_ts1_2_reg_rx_count_cry[0]), + .S(plm_fsm_rc_counter_ts1_2_reg_rx_count_qxu[0]) + ); + XORCY plm_fsm_rc_counter_ts1_2_reg_rx_count_s_0_ ( + .CI(N_15212_i_i_26), + .LI(plm_fsm_rc_counter_ts1_2_reg_rx_count_qxu[0]), + .O(plm_fsm_rc_counter_ts1_2_reg_rx_count_s[0]) + ); + MUXCY_L plm_fsm_rc_counter_ts1_2_reg_rx_count_cry_1_ ( + .CI(plm_fsm_rc_counter_ts1_2_reg_rx_count_cry[0]), + .DI(plm_fsm_rc_counter_ts1_2_VCC_1947), + .LO(plm_fsm_rc_counter_ts1_2_reg_rx_count_cry[1]), + .S(plm_fsm_rc_counter_ts1_2_reg_rx_count_qxu[1]) + ); + XORCY plm_fsm_rc_counter_ts1_2_reg_rx_count_s_1_ ( + .CI(plm_fsm_rc_counter_ts1_2_reg_rx_count_cry[0]), + .LI(plm_fsm_rc_counter_ts1_2_reg_rx_count_qxu[1]), + .O(plm_fsm_rc_counter_ts1_2_reg_rx_count_s[1]) + ); + MUXCY_L plm_fsm_rc_counter_ts1_2_reg_rx_count_cry_2_ ( + .CI(plm_fsm_rc_counter_ts1_2_reg_rx_count_cry[1]), + .DI(plm_fsm_rc_counter_ts1_2_VCC_1947), + .LO(plm_fsm_rc_counter_ts1_2_reg_rx_count_cry[2]), + .S(plm_fsm_rc_counter_ts1_2_reg_rx_count_qxu[2]) + ); + XORCY plm_fsm_rc_counter_ts1_2_reg_rx_count_s_2_ ( + .CI(plm_fsm_rc_counter_ts1_2_reg_rx_count_cry[1]), + .LI(plm_fsm_rc_counter_ts1_2_reg_rx_count_qxu[2]), + .O(plm_fsm_rc_counter_ts1_2_reg_rx_count_s[2]) + ); + MUXCY_L plm_fsm_rc_counter_ts1_2_reg_rx_count_cry_3_ ( + .CI(plm_fsm_rc_counter_ts1_2_reg_rx_count_cry[2]), + .DI(plm_fsm_rc_counter_ts1_2_VCC_1947), + .LO(plm_fsm_rc_counter_ts1_2_reg_rx_count_cry[3]), + .S(plm_fsm_rc_counter_ts1_2_reg_rx_count_qxu[3]) + ); + XORCY plm_fsm_rc_counter_ts1_2_reg_rx_count_s_3_ ( + .CI(plm_fsm_rc_counter_ts1_2_reg_rx_count_cry[2]), + .LI(plm_fsm_rc_counter_ts1_2_reg_rx_count_qxu[3]), + .O(plm_fsm_rc_counter_ts1_2_reg_rx_count_s[3]) + ); + MUXCY_L plm_fsm_rc_counter_ts1_2_reg_rx_count_cry_4_ ( + .CI(plm_fsm_rc_counter_ts1_2_reg_rx_count_cry[3]), + .DI(plm_fsm_rc_counter_ts1_2_VCC_1947), + .LO(plm_fsm_rc_counter_ts1_2_reg_rx_count_cry[4]), + .S(plm_fsm_rc_counter_ts1_2_reg_rx_count_qxu[4]) + ); + XORCY plm_fsm_rc_counter_ts1_2_reg_rx_count_s_4_ ( + .CI(plm_fsm_rc_counter_ts1_2_reg_rx_count_cry[3]), + .LI(plm_fsm_rc_counter_ts1_2_reg_rx_count_qxu[4]), + .O(plm_fsm_rc_counter_ts1_2_reg_rx_count_s[4]) + ); + MUXCY_L plm_fsm_rc_counter_ts1_2_reg_rx_count_cry_5_ ( + .CI(plm_fsm_rc_counter_ts1_2_reg_rx_count_cry[4]), + .DI(plm_fsm_rc_counter_ts1_2_VCC_1947), + .LO(plm_fsm_rc_counter_ts1_2_reg_rx_count_cry[5]), + .S(plm_fsm_rc_counter_ts1_2_reg_rx_count_qxu[5]) + ); + XORCY plm_fsm_rc_counter_ts1_2_reg_rx_count_s_5_ ( + .CI(plm_fsm_rc_counter_ts1_2_reg_rx_count_cry[4]), + .LI(plm_fsm_rc_counter_ts1_2_reg_rx_count_qxu[5]), + .O(plm_fsm_rc_counter_ts1_2_reg_rx_count_s[5]) + ); + MUXCY_L plm_fsm_rc_counter_ts1_2_reg_rx_count_cry_6_ ( + .CI(plm_fsm_rc_counter_ts1_2_reg_rx_count_cry[5]), + .DI(plm_fsm_rc_counter_ts1_2_VCC_1947), + .LO(plm_fsm_rc_counter_ts1_2_reg_rx_count_cry[6]), + .S(plm_fsm_rc_counter_ts1_2_reg_rx_count_qxu[6]) + ); + XORCY plm_fsm_rc_counter_ts1_2_reg_rx_count_s_6_ ( + .CI(plm_fsm_rc_counter_ts1_2_reg_rx_count_cry[5]), + .LI(plm_fsm_rc_counter_ts1_2_reg_rx_count_qxu[6]), + .O(plm_fsm_rc_counter_ts1_2_reg_rx_count_s[6]) + ); + XORCY plm_fsm_rc_counter_ts1_2_reg_rx_count_s_7_ ( + .CI(plm_fsm_rc_counter_ts1_2_reg_rx_count_cry[6]), + .LI(plm_fsm_rc_counter_ts1_2_reg_rx_count_qxu[7]), + .O(plm_fsm_rc_counter_ts1_2_reg_rx_count_s[7]) + ); + MUXCY_L plm_fsm_rc_counter_ts1_2_reg_tx_count_cry_0_ ( + .CI(plm_fsm_rc_counter_ts1_2_N_60922_i_1948), + .DI(plm_fsm_rc_counter_ts1_2_VCC_1947), + .LO(plm_fsm_rc_counter_ts1_2_reg_tx_count_cry[0]), + .S(plm_fsm_rc_counter_ts1_2_reg_tx_count_qxu[0]) + ); + XORCY plm_fsm_rc_counter_ts1_2_reg_tx_count_s_0_ ( + .CI(plm_fsm_rc_counter_ts1_2_N_60922_i_1948), + .LI(plm_fsm_rc_counter_ts1_2_reg_tx_count_qxu[0]), + .O(plm_fsm_rc_counter_ts1_2_reg_tx_count_s[0]) + ); + MUXCY_L plm_fsm_rc_counter_ts1_2_reg_tx_count_cry_1_ ( + .CI(plm_fsm_rc_counter_ts1_2_reg_tx_count_cry[0]), + .DI(plm_fsm_rc_counter_ts1_2_VCC_1947), + .LO(plm_fsm_rc_counter_ts1_2_reg_tx_count_cry[1]), + .S(plm_fsm_rc_counter_ts1_2_reg_tx_count_qxu[1]) + ); + XORCY plm_fsm_rc_counter_ts1_2_reg_tx_count_s_1_ ( + .CI(plm_fsm_rc_counter_ts1_2_reg_tx_count_cry[0]), + .LI(plm_fsm_rc_counter_ts1_2_reg_tx_count_qxu[1]), + .O(plm_fsm_rc_counter_ts1_2_reg_tx_count_s[1]) + ); + MUXCY_L plm_fsm_rc_counter_ts1_2_reg_tx_count_cry_2_ ( + .CI(plm_fsm_rc_counter_ts1_2_reg_tx_count_cry[1]), + .DI(plm_fsm_rc_counter_ts1_2_VCC_1947), + .LO(plm_fsm_rc_counter_ts1_2_reg_tx_count_cry[2]), + .S(plm_fsm_rc_counter_ts1_2_reg_tx_count_qxu[2]) + ); + XORCY plm_fsm_rc_counter_ts1_2_reg_tx_count_s_2_ ( + .CI(plm_fsm_rc_counter_ts1_2_reg_tx_count_cry[1]), + .LI(plm_fsm_rc_counter_ts1_2_reg_tx_count_qxu[2]), + .O(plm_fsm_rc_counter_ts1_2_reg_tx_count_s[2]) + ); + MUXCY_L plm_fsm_rc_counter_ts1_2_reg_tx_count_cry_3_ ( + .CI(plm_fsm_rc_counter_ts1_2_reg_tx_count_cry[2]), + .DI(plm_fsm_rc_counter_ts1_2_VCC_1947), + .LO(plm_fsm_rc_counter_ts1_2_reg_tx_count_cry[3]), + .S(plm_fsm_rc_counter_ts1_2_reg_tx_count_qxu[3]) + ); + XORCY plm_fsm_rc_counter_ts1_2_reg_tx_count_s_3_ ( + .CI(plm_fsm_rc_counter_ts1_2_reg_tx_count_cry[2]), + .LI(plm_fsm_rc_counter_ts1_2_reg_tx_count_qxu[3]), + .O(plm_fsm_rc_counter_ts1_2_reg_tx_count_s[3]) + ); + MUXCY_L plm_fsm_rc_counter_ts1_2_reg_tx_count_cry_4_ ( + .CI(plm_fsm_rc_counter_ts1_2_reg_tx_count_cry[3]), + .DI(plm_fsm_rc_counter_ts1_2_VCC_1947), + .LO(plm_fsm_rc_counter_ts1_2_reg_tx_count_cry[4]), + .S(plm_fsm_rc_counter_ts1_2_reg_tx_count_qxu[4]) + ); + XORCY plm_fsm_rc_counter_ts1_2_reg_tx_count_s_4_ ( + .CI(plm_fsm_rc_counter_ts1_2_reg_tx_count_cry[3]), + .LI(plm_fsm_rc_counter_ts1_2_reg_tx_count_qxu[4]), + .O(plm_fsm_rc_counter_ts1_2_reg_tx_count_s[4]) + ); + MUXCY_L plm_fsm_rc_counter_ts1_2_reg_tx_count_cry_5_ ( + .CI(plm_fsm_rc_counter_ts1_2_reg_tx_count_cry[4]), + .DI(plm_fsm_rc_counter_ts1_2_VCC_1947), + .LO(plm_fsm_rc_counter_ts1_2_reg_tx_count_cry[5]), + .S(plm_fsm_rc_counter_ts1_2_reg_tx_count_qxu[5]) + ); + XORCY plm_fsm_rc_counter_ts1_2_reg_tx_count_s_5_ ( + .CI(plm_fsm_rc_counter_ts1_2_reg_tx_count_cry[4]), + .LI(plm_fsm_rc_counter_ts1_2_reg_tx_count_qxu[5]), + .O(plm_fsm_rc_counter_ts1_2_reg_tx_count_s[5]) + ); + MUXCY_L plm_fsm_rc_counter_ts1_2_reg_tx_count_cry_6_ ( + .CI(plm_fsm_rc_counter_ts1_2_reg_tx_count_cry[5]), + .DI(plm_fsm_rc_counter_ts1_2_VCC_1947), + .LO(plm_fsm_rc_counter_ts1_2_reg_tx_count_cry[6]), + .S(plm_fsm_rc_counter_ts1_2_reg_tx_count_qxu[6]) + ); + XORCY plm_fsm_rc_counter_ts1_2_reg_tx_count_s_6_ ( + .CI(plm_fsm_rc_counter_ts1_2_reg_tx_count_cry[5]), + .LI(plm_fsm_rc_counter_ts1_2_reg_tx_count_qxu[6]), + .O(plm_fsm_rc_counter_ts1_2_reg_tx_count_s[6]) + ); + XORCY plm_fsm_rc_counter_ts1_2_reg_tx_count_s_7_ ( + .CI(plm_fsm_rc_counter_ts1_2_reg_tx_count_cry[6]), + .LI(plm_fsm_rc_counter_ts1_2_reg_tx_count_qxu[7]), + .O(plm_fsm_rc_counter_ts1_2_reg_tx_count_s[7]) + ); + defparam plm_fsm_rc_counter_ts1_2_un1_enable_4_i_0_0_a2_0_1.INIT = 4'h2; + LUT2 plm_fsm_rc_counter_ts1_2_un1_enable_4_i_0_0_a2_0_1 ( + .I0(plm_reg_ts1_1_1), + .I1(plm_fsm_rc_counter_ts1_2_reg_rx_expired_315), + .O(plm_fsm_rc_counter_ts1_2_N_59107_1) + ); + defparam plm_fsm_rc_counter_ts1_2_un1_enable_1_0_a2_i_o2_i_a3_0_a2.INIT = 4'h4; + LUT2 plm_fsm_rc_counter_ts1_2_un1_enable_1_0_a2_i_o2_i_a3_0_a2 ( + .I0(N_29556_i), + .I1(plm_fsm_rc_counter_ts1_2_reg_oneshot_1950), + .O(plm_fsm_rc_counter_ts1_2_un1_enable_1_0_a2_i_o2_i_a3_0_a2_4) + ); + defparam plm_fsm_rc_counter_ts1_2_oneshot_monitor_un1_enable_0_a2_i_i_a3_0_a2.INIT = 4'h1; + LUT2 plm_fsm_rc_counter_ts1_2_oneshot_monitor_un1_enable_0_a2_i_i_a3_0_a2 ( + .I0(plm_reg_ts1_1_1), + .I1(N_29556_i), + .O(plm_fsm_rc_counter_ts1_2_un1_enable_0_a2_i_i_a3_0_a2) + ); + defparam plm_fsm_rc_counter_ts1_2_loadable_tx_counter_un1_reg_tx_count_0_a2_0_a3_4.INIT = 16'h0001; + LUT4 plm_fsm_rc_counter_ts1_2_loadable_tx_counter_un1_reg_tx_count_0_a2_0_a3_4 ( + .I0(plm_fsm_rc_counter_ts1_2_reg_tx_count[0]), + .I1(plm_fsm_rc_counter_ts1_2_reg_tx_count[1]), + .I2(plm_fsm_rc_counter_ts1_2_reg_tx_count[2]), + .I3(plm_fsm_rc_counter_ts1_2_reg_tx_count[3]), + .O(plm_fsm_rc_counter_ts1_2_un1_reg_tx_count_0_a2_0_a3_4) + ); + defparam plm_fsm_rc_counter_ts1_2_loadable_tx_counter_un1_reg_tx_count_0_a2_0_a3_5.INIT = 16'h0001; + LUT4 plm_fsm_rc_counter_ts1_2_loadable_tx_counter_un1_reg_tx_count_0_a2_0_a3_5 ( + .I0(plm_fsm_rc_counter_ts1_2_reg_tx_count[4]), + .I1(plm_fsm_rc_counter_ts1_2_reg_tx_count[5]), + .I2(plm_fsm_rc_counter_ts1_2_reg_tx_count[6]), + .I3(plm_fsm_rc_counter_ts1_2_reg_tx_count[7]), + .O(plm_fsm_rc_counter_ts1_2_un1_reg_tx_count_0_a2_0_a3_5) + ); + defparam plm_fsm_rc_counter_ts1_2_loadable_rx_counter_un1_reg_rx_count_0_a2_0_a3_4.INIT = 16'h0001; + LUT4 plm_fsm_rc_counter_ts1_2_loadable_rx_counter_un1_reg_rx_count_0_a2_0_a3_4 ( + .I0(plm_fsm_rc_counter_ts1_2_reg_rx_count[0]), + .I1(plm_fsm_rc_counter_ts1_2_reg_rx_count[1]), + .I2(plm_fsm_rc_counter_ts1_2_reg_rx_count[2]), + .I3(plm_fsm_rc_counter_ts1_2_reg_rx_count[3]), + .O(plm_fsm_rc_counter_ts1_2_un1_reg_rx_count_0_a2_0_a3_4) + ); + defparam plm_fsm_rc_counter_ts1_2_loadable_rx_counter_un1_reg_rx_count_0_a2_0_a3_5.INIT = 16'h0001; + LUT4 plm_fsm_rc_counter_ts1_2_loadable_rx_counter_un1_reg_rx_count_0_a2_0_a3_5 ( + .I0(plm_fsm_rc_counter_ts1_2_reg_rx_count[4]), + .I1(plm_fsm_rc_counter_ts1_2_reg_rx_count[5]), + .I2(plm_fsm_rc_counter_ts1_2_reg_rx_count[6]), + .I3(plm_fsm_rc_counter_ts1_2_reg_rx_count[7]), + .O(plm_fsm_rc_counter_ts1_2_un1_reg_rx_count_0_a2_0_a3_5) + ); + defparam plm_fsm_rc_counter_ts1_2_un1_enable_1_0_a2_i_i_a3_0_a2.INIT = 4'h2; + LUT2 plm_fsm_rc_counter_ts1_2_un1_enable_1_0_a2_i_i_a3_0_a2 ( + .I0(plm_fsm_rc_counter_ts1_2_un1_enable_1_0_a2_i_o2_i_a3_0_a2_4), + .I1(plm_fsm_rc_counter_ts1_2_reg_tx_expired_1952), + .O(plm_fsm_rc_counter_ts1_2_un1_enable_1_0_a2_i_i_a3_0_a2_1) + ); + defparam plm_fsm_rc_counter_ts1_2_loadable_rx_counter_N_60914_i.INIT = 4'hD; + LUT2 plm_fsm_rc_counter_ts1_2_loadable_rx_counter_N_60914_i ( + .I0(plm_fsm_rc_counter_ts1_2_un1_enable_0_a2_i_i_a3_0_a2), + .I1(plm_fsm_rc_counter_ts1_2_reg_rx_expired_315), + .O(plm_fsm_rc_counter_ts1_2_N_60914_i) + ); + defparam plm_fsm_rc_counter_ts1_2_N_60927_i.INIT = 16'hFFEF; + LUT4 plm_fsm_rc_counter_ts1_2_N_60927_i ( + .I0(plm_reg_sym_sent_6_), + .I1(N_29556_i), + .I2(plm_fsm_rc_counter_ts1_2_reg_oneshot_1950), + .I3(plm_fsm_rc_counter_ts1_2_reg_tx_expired_1952), + .O(plm_fsm_rc_counter_ts1_2_N_60927_i_1949) + ); + defparam plm_fsm_rc_counter_ts1_2_N_60945_i.INIT = 8'hD5; + LUT3 plm_fsm_rc_counter_ts1_2_N_60945_i ( + .I0(plm_fsm_rc_counter_ts1_2_un1_enable_1_0_a2_i_o2_i_a3_0_a2_4), + .I1(plm_fsm_rc_counter_ts1_2_un1_reg_tx_count_0_a2_0_a3_4), + .I2(plm_fsm_rc_counter_ts1_2_un1_reg_tx_count_0_a2_0_a3_5), + .O(plm_fsm_rc_counter_ts1_2_N_60945_i_1951) + ); + defparam plm_fsm_rc_counter_ts1_2_loadable_rx_counter_N_60960_i.INIT = 8'hEA; + LUT3 plm_fsm_rc_counter_ts1_2_loadable_rx_counter_N_60960_i ( + .I0(N_29556_i), + .I1(plm_fsm_rc_counter_ts1_2_un1_reg_rx_count_0_a2_0_a3_4), + .I2(plm_fsm_rc_counter_ts1_2_un1_reg_rx_count_0_a2_0_a3_5), + .O(plm_fsm_rc_counter_ts1_2_N_60960_i) + ); + defparam plm_fsm_rc_counter_ts1_2_N_85532_i.INIT = 16'hEAFA; + LUT4 plm_fsm_rc_counter_ts1_2_N_85532_i ( + .I0(N_29556_i), + .I1(N_56030_i), + .I2(plm_fsm_rc_counter_ts1_2_N_59107_1), + .I3(plm_rx2_ts1_c), + .O(plm_fsm_rc_counter_ts1_2_N_85532_i_1953) + ); + defparam plm_fsm_rc_counter_ts1_2_flagit_reg_expired_5_0_a2_i_i_a3_0_a2.INIT = 8'h40; + LUT3_L plm_fsm_rc_counter_ts1_2_flagit_reg_expired_5_0_a2_i_i_a3_0_a2 ( + .I0(N_29556_i_1), + .I1(plm_fsm_rc_counter_ts1_2_reg_rx_expired_315), + .I2(plm_fsm_rc_counter_ts1_2_reg_tx_expired_1952), + .LO(plm_fsm_rc_counter_ts1_2_reg_expired_5_0_a2_i_i_a3_0_a2_1) + ); + defparam plm_fsm_rc_counter_ts1_2_N_60922_i.INIT = 4'hB; + LUT2 plm_fsm_rc_counter_ts1_2_N_60922_i ( + .I0(plm_fsm_rc_counter_ts1_2_reg_tx_expired_1952), + .I1(plm_fsm_rc_counter_ts1_2_un1_enable_1_0_a2_i_o2_i_a3_0_a2_4), + .O(plm_fsm_rc_counter_ts1_2_N_60922_i_1948) + ); + FDCE plm_fsm_rc_counter_ts1_2_reg_tx_count_7_ ( + .CE(plm_fsm_rc_counter_ts1_2_N_60927_i_1949), + .C(mgt_clk), + .D(plm_fsm_rc_counter_ts1_2_reg_tx_count_s[7]), + .Q(plm_fsm_rc_counter_ts1_2_reg_tx_count[7]), + .CLR(plm_rst) + ); + FDCE plm_fsm_rc_counter_ts1_2_reg_tx_count_6_ ( + .CE(plm_fsm_rc_counter_ts1_2_N_60927_i_1949), + .C(mgt_clk), + .D(plm_fsm_rc_counter_ts1_2_reg_tx_count_s[6]), + .Q(plm_fsm_rc_counter_ts1_2_reg_tx_count[6]), + .CLR(plm_rst) + ); + FDCE plm_fsm_rc_counter_ts1_2_reg_tx_count_5_ ( + .CE(plm_fsm_rc_counter_ts1_2_N_60927_i_1949), + .C(mgt_clk), + .D(plm_fsm_rc_counter_ts1_2_reg_tx_count_s[5]), + .Q(plm_fsm_rc_counter_ts1_2_reg_tx_count[5]), + .CLR(plm_rst) + ); + FDPE plm_fsm_rc_counter_ts1_2_reg_tx_count_4_ ( + .PRE(plm_rst), + .CE(plm_fsm_rc_counter_ts1_2_N_60927_i_1949), + .C(mgt_clk), + .D(plm_fsm_rc_counter_ts1_2_reg_tx_count_s[4]), + .Q(plm_fsm_rc_counter_ts1_2_reg_tx_count[4]) + ); + FDCE plm_fsm_rc_counter_ts1_2_reg_tx_count_3_ ( + .CE(plm_fsm_rc_counter_ts1_2_N_60927_i_1949), + .C(mgt_clk), + .D(plm_fsm_rc_counter_ts1_2_reg_tx_count_s[3]), + .Q(plm_fsm_rc_counter_ts1_2_reg_tx_count[3]), + .CLR(plm_rst) + ); + FDCE plm_fsm_rc_counter_ts1_2_reg_tx_count_2_ ( + .CE(plm_fsm_rc_counter_ts1_2_N_60927_i_1949), + .C(mgt_clk), + .D(plm_fsm_rc_counter_ts1_2_reg_tx_count_s[2]), + .Q(plm_fsm_rc_counter_ts1_2_reg_tx_count[2]), + .CLR(plm_rst) + ); + FDCE plm_fsm_rc_counter_ts1_2_reg_tx_count_1_ ( + .CE(plm_fsm_rc_counter_ts1_2_N_60927_i_1949), + .C(mgt_clk), + .D(plm_fsm_rc_counter_ts1_2_reg_tx_count_s[1]), + .Q(plm_fsm_rc_counter_ts1_2_reg_tx_count[1]), + .CLR(plm_rst) + ); + FDCE plm_fsm_rc_counter_ts1_2_reg_tx_count_0_ ( + .CE(plm_fsm_rc_counter_ts1_2_N_60927_i_1949), + .C(mgt_clk), + .D(plm_fsm_rc_counter_ts1_2_reg_tx_count_s[0]), + .Q(plm_fsm_rc_counter_ts1_2_reg_tx_count[0]), + .CLR(plm_rst) + ); + FDCE plm_fsm_rc_counter_ts1_2_reg_rx_count_7_ ( + .CE(plm_fsm_rc_counter_ts1_2_N_60914_i), + .C(mgt_clk), + .D(plm_fsm_rc_counter_ts1_2_reg_rx_count_s[7]), + .Q(plm_fsm_rc_counter_ts1_2_reg_rx_count[7]), + .CLR(plm_rst) + ); + FDCE plm_fsm_rc_counter_ts1_2_reg_rx_count_6_ ( + .CE(plm_fsm_rc_counter_ts1_2_N_60914_i), + .C(mgt_clk), + .D(plm_fsm_rc_counter_ts1_2_reg_rx_count_s[6]), + .Q(plm_fsm_rc_counter_ts1_2_reg_rx_count[6]), + .CLR(plm_rst) + ); + FDCE plm_fsm_rc_counter_ts1_2_reg_rx_count_5_ ( + .CE(plm_fsm_rc_counter_ts1_2_N_60914_i), + .C(mgt_clk), + .D(plm_fsm_rc_counter_ts1_2_reg_rx_count_s[5]), + .Q(plm_fsm_rc_counter_ts1_2_reg_rx_count[5]), + .CLR(plm_rst) + ); + FDCE plm_fsm_rc_counter_ts1_2_reg_rx_count_4_ ( + .CE(plm_fsm_rc_counter_ts1_2_N_60914_i), + .C(mgt_clk), + .D(plm_fsm_rc_counter_ts1_2_reg_rx_count_s[4]), + .Q(plm_fsm_rc_counter_ts1_2_reg_rx_count[4]), + .CLR(plm_rst) + ); + FDPE plm_fsm_rc_counter_ts1_2_reg_rx_count_3_ ( + .PRE(plm_rst), + .CE(plm_fsm_rc_counter_ts1_2_N_60914_i), + .C(mgt_clk), + .D(plm_fsm_rc_counter_ts1_2_reg_rx_count_s[3]), + .Q(plm_fsm_rc_counter_ts1_2_reg_rx_count[3]) + ); + FDCE plm_fsm_rc_counter_ts1_2_reg_rx_count_2_ ( + .CE(plm_fsm_rc_counter_ts1_2_N_60914_i), + .C(mgt_clk), + .D(plm_fsm_rc_counter_ts1_2_reg_rx_count_s[2]), + .Q(plm_fsm_rc_counter_ts1_2_reg_rx_count[2]), + .CLR(plm_rst) + ); + FDCE plm_fsm_rc_counter_ts1_2_reg_rx_count_1_ ( + .CE(plm_fsm_rc_counter_ts1_2_N_60914_i), + .C(mgt_clk), + .D(plm_fsm_rc_counter_ts1_2_reg_rx_count_s[1]), + .Q(plm_fsm_rc_counter_ts1_2_reg_rx_count[1]), + .CLR(plm_rst) + ); + FDCE plm_fsm_rc_counter_ts1_2_reg_rx_count_0_ ( + .CE(plm_fsm_rc_counter_ts1_2_N_60914_i), + .C(mgt_clk), + .D(plm_fsm_rc_counter_ts1_2_reg_rx_count_s[0]), + .Q(plm_fsm_rc_counter_ts1_2_reg_rx_count[0]), + .CLR(plm_rst) + ); + FDC plm_fsm_rc_counter_ts1_2_reg_expired ( + .C(mgt_clk), + .D(plm_fsm_rc_counter_ts1_2_reg_expired_5_0_a2_i_i_a3_0_a2_1), + .Q(plm_fsm_rc_cntrout_ts1_2), + .CLR(plm_rst) + ); + FDCE plm_fsm_rc_counter_ts1_2_reg_oneshot ( + .CE(plm_fsm_rc_counter_ts1_2_N_60961_i), + .C(mgt_clk), + .D(N_29556_i_0), + .Q(plm_fsm_rc_counter_ts1_2_reg_oneshot_1950), + .CLR(plm_rst) + ); + FDCE plm_fsm_rc_counter_ts1_2_reg_rx_expired ( + .CE(plm_fsm_rc_counter_ts1_2_N_60960_i), + .C(mgt_clk), + .D(N_29556_i_0), + .Q(plm_fsm_rc_counter_ts1_2_reg_rx_expired_315), + .CLR(plm_rst) + ); + FDCE plm_fsm_rc_counter_ts1_2_reg_tx_expired ( + .CE(plm_fsm_rc_counter_ts1_2_N_60945_i_1951), + .C(mgt_clk), + .D(plm_fsm_rc_counter_ts1_2_un1_enable_1_0_a2_i_o2_i_a3_0_a2_4), + .Q(plm_fsm_rc_counter_ts1_2_reg_tx_expired_1952), + .CLR(plm_rst) + ); + INV plm_fsm_rc_counter_ts1_2_oneshot_monitor_N_60961_i ( + .I(plm_fsm_rc_counter_ts1_2_un1_enable_0_a2_i_i_a3_0_a2), + .O(plm_fsm_rc_counter_ts1_2_N_60961_i) + ); + defparam plm_fsm_rc_counter_ts1_2_reg_rx_count_qxu_0_0_.INIT = 4'h7; + LUT2_L plm_fsm_rc_counter_ts1_2_reg_rx_count_qxu_0_0_ ( + .I0(N_15212_i), + .I1(plm_fsm_rc_counter_ts1_2_reg_rx_count[0]), + .LO(plm_fsm_rc_counter_ts1_2_reg_rx_count_qxu[0]) + ); + defparam plm_fsm_rc_counter_ts1_2_reg_rx_count_qxu_0_1_.INIT = 4'h7; + LUT2_L plm_fsm_rc_counter_ts1_2_reg_rx_count_qxu_0_1_ ( + .I0(N_15212_i), + .I1(plm_fsm_rc_counter_ts1_2_reg_rx_count[1]), + .LO(plm_fsm_rc_counter_ts1_2_reg_rx_count_qxu[1]) + ); + defparam plm_fsm_rc_counter_ts1_2_reg_rx_count_qxu_0_2_.INIT = 4'h7; + LUT2_L plm_fsm_rc_counter_ts1_2_reg_rx_count_qxu_0_2_ ( + .I0(N_15212_i), + .I1(plm_fsm_rc_counter_ts1_2_reg_rx_count[2]), + .LO(plm_fsm_rc_counter_ts1_2_reg_rx_count_qxu[2]) + ); + defparam plm_fsm_rc_counter_ts1_2_reg_rx_count_qxu_0_3_.INIT = 8'h1B; + LUT3_L plm_fsm_rc_counter_ts1_2_reg_rx_count_qxu_0_3_ ( + .I0(N_15212_i), + .I1(plm_fsm_rc_counter_ts1_2_N_85532_i_1953), + .I2(plm_fsm_rc_counter_ts1_2_reg_rx_count[3]), + .LO(plm_fsm_rc_counter_ts1_2_reg_rx_count_qxu[3]) + ); + defparam plm_fsm_rc_counter_ts1_2_reg_rx_count_qxu_0_4_.INIT = 4'h7; + LUT2_L plm_fsm_rc_counter_ts1_2_reg_rx_count_qxu_0_4_ ( + .I0(N_15212_i), + .I1(plm_fsm_rc_counter_ts1_2_reg_rx_count[4]), + .LO(plm_fsm_rc_counter_ts1_2_reg_rx_count_qxu[4]) + ); + defparam plm_fsm_rc_counter_ts1_2_reg_rx_count_qxu_0_5_.INIT = 4'h7; + LUT2_L plm_fsm_rc_counter_ts1_2_reg_rx_count_qxu_0_5_ ( + .I0(N_15212_i), + .I1(plm_fsm_rc_counter_ts1_2_reg_rx_count[5]), + .LO(plm_fsm_rc_counter_ts1_2_reg_rx_count_qxu[5]) + ); + defparam plm_fsm_rc_counter_ts1_2_reg_rx_count_qxu_0_6_.INIT = 4'h7; + LUT2_L plm_fsm_rc_counter_ts1_2_reg_rx_count_qxu_0_6_ ( + .I0(N_15212_i), + .I1(plm_fsm_rc_counter_ts1_2_reg_rx_count[6]), + .LO(plm_fsm_rc_counter_ts1_2_reg_rx_count_qxu[6]) + ); + defparam plm_fsm_rc_counter_ts1_2_reg_rx_count_qxu_0_7_.INIT = 4'h7; + LUT2_L plm_fsm_rc_counter_ts1_2_reg_rx_count_qxu_0_7_ ( + .I0(N_15212_i), + .I1(plm_fsm_rc_counter_ts1_2_reg_rx_count[7]), + .LO(plm_fsm_rc_counter_ts1_2_reg_rx_count_qxu[7]) + ); + defparam plm_fsm_rc_counter_ts1_2_reg_tx_count_qxu_0_0_.INIT = 4'h7; + LUT2_L plm_fsm_rc_counter_ts1_2_reg_tx_count_qxu_0_0_ ( + .I0(plm_fsm_rc_counter_ts1_2_un1_enable_1_0_a2_i_i_a3_0_a2_1), + .I1(plm_fsm_rc_counter_ts1_2_reg_tx_count[0]), + .LO(plm_fsm_rc_counter_ts1_2_reg_tx_count_qxu[0]) + ); + defparam plm_fsm_rc_counter_ts1_2_reg_tx_count_qxu_0_1_.INIT = 4'h7; + LUT2_L plm_fsm_rc_counter_ts1_2_reg_tx_count_qxu_0_1_ ( + .I0(plm_fsm_rc_counter_ts1_2_un1_enable_1_0_a2_i_i_a3_0_a2_1), + .I1(plm_fsm_rc_counter_ts1_2_reg_tx_count[1]), + .LO(plm_fsm_rc_counter_ts1_2_reg_tx_count_qxu[1]) + ); + defparam plm_fsm_rc_counter_ts1_2_reg_tx_count_qxu_0_2_.INIT = 4'h7; + LUT2_L plm_fsm_rc_counter_ts1_2_reg_tx_count_qxu_0_2_ ( + .I0(plm_fsm_rc_counter_ts1_2_un1_enable_1_0_a2_i_i_a3_0_a2_1), + .I1(plm_fsm_rc_counter_ts1_2_reg_tx_count[2]), + .LO(plm_fsm_rc_counter_ts1_2_reg_tx_count_qxu[2]) + ); + defparam plm_fsm_rc_counter_ts1_2_reg_tx_count_qxu_0_3_.INIT = 4'h7; + LUT2_L plm_fsm_rc_counter_ts1_2_reg_tx_count_qxu_0_3_ ( + .I0(plm_fsm_rc_counter_ts1_2_un1_enable_1_0_a2_i_i_a3_0_a2_1), + .I1(plm_fsm_rc_counter_ts1_2_reg_tx_count[3]), + .LO(plm_fsm_rc_counter_ts1_2_reg_tx_count_qxu[3]) + ); + defparam plm_fsm_rc_counter_ts1_2_reg_tx_count_qxu_0_4_.INIT = 8'h4E; + LUT3_L plm_fsm_rc_counter_ts1_2_reg_tx_count_qxu_0_4_ ( + .I0(plm_fsm_rc_counter_ts1_2_un1_enable_1_0_a2_i_i_a3_0_a2_1), + .I1(plm_fsm_rc_counter_ts1_2_un1_enable_1_0_a2_i_o2_i_a3_0_a2_4), + .I2(plm_fsm_rc_counter_ts1_2_reg_tx_count[4]), + .LO(plm_fsm_rc_counter_ts1_2_reg_tx_count_qxu[4]) + ); + defparam plm_fsm_rc_counter_ts1_2_reg_tx_count_qxu_0_5_.INIT = 4'h7; + LUT2_L plm_fsm_rc_counter_ts1_2_reg_tx_count_qxu_0_5_ ( + .I0(plm_fsm_rc_counter_ts1_2_un1_enable_1_0_a2_i_i_a3_0_a2_1), + .I1(plm_fsm_rc_counter_ts1_2_reg_tx_count[5]), + .LO(plm_fsm_rc_counter_ts1_2_reg_tx_count_qxu[5]) + ); + defparam plm_fsm_rc_counter_ts1_2_reg_tx_count_qxu_0_6_.INIT = 4'h7; + LUT2_L plm_fsm_rc_counter_ts1_2_reg_tx_count_qxu_0_6_ ( + .I0(plm_fsm_rc_counter_ts1_2_un1_enable_1_0_a2_i_i_a3_0_a2_1), + .I1(plm_fsm_rc_counter_ts1_2_reg_tx_count[6]), + .LO(plm_fsm_rc_counter_ts1_2_reg_tx_count_qxu[6]) + ); + defparam plm_fsm_rc_counter_ts1_2_reg_tx_count_qxu_0_7_.INIT = 4'h7; + LUT2_L plm_fsm_rc_counter_ts1_2_reg_tx_count_qxu_0_7_ ( + .I0(plm_fsm_rc_counter_ts1_2_un1_enable_1_0_a2_i_i_a3_0_a2_1), + .I1(plm_fsm_rc_counter_ts1_2_reg_tx_count[7]), + .LO(plm_fsm_rc_counter_ts1_2_reg_tx_count_qxu[7]) + ); + VCC plm_fsm_rc_counter_ts1_3_VCC ( + .P(plm_fsm_rc_counter_ts1_3_VCC_1954) + ); + MUXCY_L plm_fsm_rc_counter_ts1_3_reg_rx_count_cry_0_ ( + .CI(N_28802_i_i_27), + .DI(plm_fsm_rc_counter_ts1_3_VCC_1954), + .LO(plm_fsm_rc_counter_ts1_3_reg_rx_count_cry[0]), + .S(plm_fsm_rc_counter_ts1_3_reg_rx_count_qxu[0]) + ); + XORCY plm_fsm_rc_counter_ts1_3_reg_rx_count_s_0_ ( + .CI(N_28802_i_i_27), + .LI(plm_fsm_rc_counter_ts1_3_reg_rx_count_qxu[0]), + .O(plm_fsm_rc_counter_ts1_3_reg_rx_count_s[0]) + ); + MUXCY_L plm_fsm_rc_counter_ts1_3_reg_rx_count_cry_1_ ( + .CI(plm_fsm_rc_counter_ts1_3_reg_rx_count_cry[0]), + .DI(plm_fsm_rc_counter_ts1_3_VCC_1954), + .LO(plm_fsm_rc_counter_ts1_3_reg_rx_count_cry[1]), + .S(plm_fsm_rc_counter_ts1_3_reg_rx_count_qxu[1]) + ); + XORCY plm_fsm_rc_counter_ts1_3_reg_rx_count_s_1_ ( + .CI(plm_fsm_rc_counter_ts1_3_reg_rx_count_cry[0]), + .LI(plm_fsm_rc_counter_ts1_3_reg_rx_count_qxu[1]), + .O(plm_fsm_rc_counter_ts1_3_reg_rx_count_s[1]) + ); + MUXCY_L plm_fsm_rc_counter_ts1_3_reg_rx_count_cry_2_ ( + .CI(plm_fsm_rc_counter_ts1_3_reg_rx_count_cry[1]), + .DI(plm_fsm_rc_counter_ts1_3_VCC_1954), + .LO(plm_fsm_rc_counter_ts1_3_reg_rx_count_cry[2]), + .S(plm_fsm_rc_counter_ts1_3_reg_rx_count_qxu[2]) + ); + XORCY plm_fsm_rc_counter_ts1_3_reg_rx_count_s_2_ ( + .CI(plm_fsm_rc_counter_ts1_3_reg_rx_count_cry[1]), + .LI(plm_fsm_rc_counter_ts1_3_reg_rx_count_qxu[2]), + .O(plm_fsm_rc_counter_ts1_3_reg_rx_count_s[2]) + ); + MUXCY_L plm_fsm_rc_counter_ts1_3_reg_rx_count_cry_3_ ( + .CI(plm_fsm_rc_counter_ts1_3_reg_rx_count_cry[2]), + .DI(plm_fsm_rc_counter_ts1_3_VCC_1954), + .LO(plm_fsm_rc_counter_ts1_3_reg_rx_count_cry[3]), + .S(plm_fsm_rc_counter_ts1_3_reg_rx_count_qxu[3]) + ); + XORCY plm_fsm_rc_counter_ts1_3_reg_rx_count_s_3_ ( + .CI(plm_fsm_rc_counter_ts1_3_reg_rx_count_cry[2]), + .LI(plm_fsm_rc_counter_ts1_3_reg_rx_count_qxu[3]), + .O(plm_fsm_rc_counter_ts1_3_reg_rx_count_s[3]) + ); + MUXCY_L plm_fsm_rc_counter_ts1_3_reg_rx_count_cry_4_ ( + .CI(plm_fsm_rc_counter_ts1_3_reg_rx_count_cry[3]), + .DI(plm_fsm_rc_counter_ts1_3_VCC_1954), + .LO(plm_fsm_rc_counter_ts1_3_reg_rx_count_cry[4]), + .S(plm_fsm_rc_counter_ts1_3_reg_rx_count_qxu[4]) + ); + XORCY plm_fsm_rc_counter_ts1_3_reg_rx_count_s_4_ ( + .CI(plm_fsm_rc_counter_ts1_3_reg_rx_count_cry[3]), + .LI(plm_fsm_rc_counter_ts1_3_reg_rx_count_qxu[4]), + .O(plm_fsm_rc_counter_ts1_3_reg_rx_count_s[4]) + ); + MUXCY_L plm_fsm_rc_counter_ts1_3_reg_rx_count_cry_5_ ( + .CI(plm_fsm_rc_counter_ts1_3_reg_rx_count_cry[4]), + .DI(plm_fsm_rc_counter_ts1_3_VCC_1954), + .LO(plm_fsm_rc_counter_ts1_3_reg_rx_count_cry[5]), + .S(plm_fsm_rc_counter_ts1_3_reg_rx_count_qxu[5]) + ); + XORCY plm_fsm_rc_counter_ts1_3_reg_rx_count_s_5_ ( + .CI(plm_fsm_rc_counter_ts1_3_reg_rx_count_cry[4]), + .LI(plm_fsm_rc_counter_ts1_3_reg_rx_count_qxu[5]), + .O(plm_fsm_rc_counter_ts1_3_reg_rx_count_s[5]) + ); + MUXCY_L plm_fsm_rc_counter_ts1_3_reg_rx_count_cry_6_ ( + .CI(plm_fsm_rc_counter_ts1_3_reg_rx_count_cry[5]), + .DI(plm_fsm_rc_counter_ts1_3_VCC_1954), + .LO(plm_fsm_rc_counter_ts1_3_reg_rx_count_cry[6]), + .S(plm_fsm_rc_counter_ts1_3_reg_rx_count_qxu[6]) + ); + XORCY plm_fsm_rc_counter_ts1_3_reg_rx_count_s_6_ ( + .CI(plm_fsm_rc_counter_ts1_3_reg_rx_count_cry[5]), + .LI(plm_fsm_rc_counter_ts1_3_reg_rx_count_qxu[6]), + .O(plm_fsm_rc_counter_ts1_3_reg_rx_count_s[6]) + ); + XORCY plm_fsm_rc_counter_ts1_3_reg_rx_count_s_7_ ( + .CI(plm_fsm_rc_counter_ts1_3_reg_rx_count_cry[6]), + .LI(plm_fsm_rc_counter_ts1_3_reg_rx_count_qxu[7]), + .O(plm_fsm_rc_counter_ts1_3_reg_rx_count_s[7]) + ); + MUXCY_L plm_fsm_rc_counter_ts1_3_reg_tx_count_cry_0_ ( + .CI(plm_fsm_rc_counter_ts1_3_N_60921_i_1955), + .DI(plm_fsm_rc_counter_ts1_3_VCC_1954), + .LO(plm_fsm_rc_counter_ts1_3_reg_tx_count_cry[0]), + .S(plm_fsm_rc_counter_ts1_3_reg_tx_count_qxu[0]) + ); + XORCY plm_fsm_rc_counter_ts1_3_reg_tx_count_s_0_ ( + .CI(plm_fsm_rc_counter_ts1_3_N_60921_i_1955), + .LI(plm_fsm_rc_counter_ts1_3_reg_tx_count_qxu[0]), + .O(plm_fsm_rc_counter_ts1_3_reg_tx_count_s[0]) + ); + MUXCY_L plm_fsm_rc_counter_ts1_3_reg_tx_count_cry_1_ ( + .CI(plm_fsm_rc_counter_ts1_3_reg_tx_count_cry[0]), + .DI(plm_fsm_rc_counter_ts1_3_VCC_1954), + .LO(plm_fsm_rc_counter_ts1_3_reg_tx_count_cry[1]), + .S(plm_fsm_rc_counter_ts1_3_reg_tx_count_qxu[1]) + ); + XORCY plm_fsm_rc_counter_ts1_3_reg_tx_count_s_1_ ( + .CI(plm_fsm_rc_counter_ts1_3_reg_tx_count_cry[0]), + .LI(plm_fsm_rc_counter_ts1_3_reg_tx_count_qxu[1]), + .O(plm_fsm_rc_counter_ts1_3_reg_tx_count_s[1]) + ); + MUXCY_L plm_fsm_rc_counter_ts1_3_reg_tx_count_cry_2_ ( + .CI(plm_fsm_rc_counter_ts1_3_reg_tx_count_cry[1]), + .DI(plm_fsm_rc_counter_ts1_3_VCC_1954), + .LO(plm_fsm_rc_counter_ts1_3_reg_tx_count_cry[2]), + .S(plm_fsm_rc_counter_ts1_3_reg_tx_count_qxu[2]) + ); + XORCY plm_fsm_rc_counter_ts1_3_reg_tx_count_s_2_ ( + .CI(plm_fsm_rc_counter_ts1_3_reg_tx_count_cry[1]), + .LI(plm_fsm_rc_counter_ts1_3_reg_tx_count_qxu[2]), + .O(plm_fsm_rc_counter_ts1_3_reg_tx_count_s[2]) + ); + MUXCY_L plm_fsm_rc_counter_ts1_3_reg_tx_count_cry_3_ ( + .CI(plm_fsm_rc_counter_ts1_3_reg_tx_count_cry[2]), + .DI(plm_fsm_rc_counter_ts1_3_VCC_1954), + .LO(plm_fsm_rc_counter_ts1_3_reg_tx_count_cry[3]), + .S(plm_fsm_rc_counter_ts1_3_reg_tx_count_qxu[3]) + ); + XORCY plm_fsm_rc_counter_ts1_3_reg_tx_count_s_3_ ( + .CI(plm_fsm_rc_counter_ts1_3_reg_tx_count_cry[2]), + .LI(plm_fsm_rc_counter_ts1_3_reg_tx_count_qxu[3]), + .O(plm_fsm_rc_counter_ts1_3_reg_tx_count_s[3]) + ); + MUXCY_L plm_fsm_rc_counter_ts1_3_reg_tx_count_cry_4_ ( + .CI(plm_fsm_rc_counter_ts1_3_reg_tx_count_cry[3]), + .DI(plm_fsm_rc_counter_ts1_3_VCC_1954), + .LO(plm_fsm_rc_counter_ts1_3_reg_tx_count_cry[4]), + .S(plm_fsm_rc_counter_ts1_3_reg_tx_count_qxu[4]) + ); + XORCY plm_fsm_rc_counter_ts1_3_reg_tx_count_s_4_ ( + .CI(plm_fsm_rc_counter_ts1_3_reg_tx_count_cry[3]), + .LI(plm_fsm_rc_counter_ts1_3_reg_tx_count_qxu[4]), + .O(plm_fsm_rc_counter_ts1_3_reg_tx_count_s[4]) + ); + MUXCY_L plm_fsm_rc_counter_ts1_3_reg_tx_count_cry_5_ ( + .CI(plm_fsm_rc_counter_ts1_3_reg_tx_count_cry[4]), + .DI(plm_fsm_rc_counter_ts1_3_VCC_1954), + .LO(plm_fsm_rc_counter_ts1_3_reg_tx_count_cry[5]), + .S(plm_fsm_rc_counter_ts1_3_reg_tx_count_qxu[5]) + ); + XORCY plm_fsm_rc_counter_ts1_3_reg_tx_count_s_5_ ( + .CI(plm_fsm_rc_counter_ts1_3_reg_tx_count_cry[4]), + .LI(plm_fsm_rc_counter_ts1_3_reg_tx_count_qxu[5]), + .O(plm_fsm_rc_counter_ts1_3_reg_tx_count_s[5]) + ); + MUXCY_L plm_fsm_rc_counter_ts1_3_reg_tx_count_cry_6_ ( + .CI(plm_fsm_rc_counter_ts1_3_reg_tx_count_cry[5]), + .DI(plm_fsm_rc_counter_ts1_3_VCC_1954), + .LO(plm_fsm_rc_counter_ts1_3_reg_tx_count_cry[6]), + .S(plm_fsm_rc_counter_ts1_3_reg_tx_count_qxu[6]) + ); + XORCY plm_fsm_rc_counter_ts1_3_reg_tx_count_s_6_ ( + .CI(plm_fsm_rc_counter_ts1_3_reg_tx_count_cry[5]), + .LI(plm_fsm_rc_counter_ts1_3_reg_tx_count_qxu[6]), + .O(plm_fsm_rc_counter_ts1_3_reg_tx_count_s[6]) + ); + XORCY plm_fsm_rc_counter_ts1_3_reg_tx_count_s_7_ ( + .CI(plm_fsm_rc_counter_ts1_3_reg_tx_count_cry[6]), + .LI(plm_fsm_rc_counter_ts1_3_reg_tx_count_qxu[7]), + .O(plm_fsm_rc_counter_ts1_3_reg_tx_count_s[7]) + ); + defparam plm_fsm_rc_counter_ts1_3_un1_enable_4_i_0_0_a2_0_1.INIT = 4'h2; + LUT2 plm_fsm_rc_counter_ts1_3_un1_enable_4_i_0_0_a2_0_1 ( + .I0(plm_reg_ts1_1_2), + .I1(plm_fsm_rc_counter_ts1_3_reg_rx_expired_317), + .O(plm_fsm_rc_counter_ts1_3_N_59105_1) + ); + defparam plm_fsm_rc_counter_ts1_3_un1_enable_1_0_a2_i_o2_i_a3_0_a2.INIT = 4'h4; + LUT2 plm_fsm_rc_counter_ts1_3_un1_enable_1_0_a2_i_o2_i_a3_0_a2 ( + .I0(N_29556_i), + .I1(plm_fsm_rc_counter_ts1_3_reg_oneshot_1957), + .O(plm_fsm_rc_counter_ts1_3_un1_enable_1_0_a2_i_o2_i_a3_0_a2_3) + ); + defparam plm_fsm_rc_counter_ts1_3_loadable_rx_counter_un1_reg_rx_count_0_a2_0_a3_4.INIT = 16'h0001; + LUT4 plm_fsm_rc_counter_ts1_3_loadable_rx_counter_un1_reg_rx_count_0_a2_0_a3_4 ( + .I0(plm_fsm_rc_counter_ts1_3_reg_rx_count[0]), + .I1(plm_fsm_rc_counter_ts1_3_reg_rx_count[1]), + .I2(plm_fsm_rc_counter_ts1_3_reg_rx_count[2]), + .I3(plm_fsm_rc_counter_ts1_3_reg_rx_count[3]), + .O(plm_fsm_rc_counter_ts1_3_un1_reg_rx_count_0_a2_0_a3_4) + ); + defparam plm_fsm_rc_counter_ts1_3_loadable_rx_counter_un1_reg_rx_count_0_a2_0_a3_5.INIT = 16'h0001; + LUT4 plm_fsm_rc_counter_ts1_3_loadable_rx_counter_un1_reg_rx_count_0_a2_0_a3_5 ( + .I0(plm_fsm_rc_counter_ts1_3_reg_rx_count[4]), + .I1(plm_fsm_rc_counter_ts1_3_reg_rx_count[5]), + .I2(plm_fsm_rc_counter_ts1_3_reg_rx_count[6]), + .I3(plm_fsm_rc_counter_ts1_3_reg_rx_count[7]), + .O(plm_fsm_rc_counter_ts1_3_un1_reg_rx_count_0_a2_0_a3_5) + ); + defparam plm_fsm_rc_counter_ts1_3_loadable_tx_counter_un1_reg_tx_count_0_a2_0_a3_4.INIT = 16'h0001; + LUT4 plm_fsm_rc_counter_ts1_3_loadable_tx_counter_un1_reg_tx_count_0_a2_0_a3_4 ( + .I0(plm_fsm_rc_counter_ts1_3_reg_tx_count[0]), + .I1(plm_fsm_rc_counter_ts1_3_reg_tx_count[1]), + .I2(plm_fsm_rc_counter_ts1_3_reg_tx_count[2]), + .I3(plm_fsm_rc_counter_ts1_3_reg_tx_count[3]), + .O(plm_fsm_rc_counter_ts1_3_un1_reg_tx_count_0_a2_0_a3_4) + ); + defparam plm_fsm_rc_counter_ts1_3_loadable_tx_counter_un1_reg_tx_count_0_a2_0_a3_5.INIT = 16'h0001; + LUT4 plm_fsm_rc_counter_ts1_3_loadable_tx_counter_un1_reg_tx_count_0_a2_0_a3_5 ( + .I0(plm_fsm_rc_counter_ts1_3_reg_tx_count[4]), + .I1(plm_fsm_rc_counter_ts1_3_reg_tx_count[5]), + .I2(plm_fsm_rc_counter_ts1_3_reg_tx_count[6]), + .I3(plm_fsm_rc_counter_ts1_3_reg_tx_count[7]), + .O(plm_fsm_rc_counter_ts1_3_un1_reg_tx_count_0_a2_0_a3_5) + ); + defparam plm_fsm_rc_counter_ts1_3_un1_enable_1_0_a2_i_i_a3_0_a2.INIT = 4'h2; + LUT2 plm_fsm_rc_counter_ts1_3_un1_enable_1_0_a2_i_i_a3_0_a2 ( + .I0(plm_fsm_rc_counter_ts1_3_un1_enable_1_0_a2_i_o2_i_a3_0_a2_3), + .I1(plm_fsm_rc_counter_ts1_3_reg_tx_expired_1959), + .O(plm_fsm_rc_counter_ts1_3_un1_enable_1_0_a2_i_i_a3_0_a2_2) + ); + defparam plm_fsm_rc_counter_ts1_3_N_60928_i.INIT = 16'hFFEF; + LUT4 plm_fsm_rc_counter_ts1_3_N_60928_i ( + .I0(plm_reg_sym_sent_6_), + .I1(N_29556_i), + .I2(plm_fsm_rc_counter_ts1_3_reg_oneshot_1957), + .I3(plm_fsm_rc_counter_ts1_3_reg_tx_expired_1959), + .O(plm_fsm_rc_counter_ts1_3_N_60928_i_1956) + ); + defparam plm_fsm_rc_counter_ts1_3_N_60943_i.INIT = 8'hD5; + LUT3 plm_fsm_rc_counter_ts1_3_N_60943_i ( + .I0(plm_fsm_rc_counter_ts1_3_un1_enable_1_0_a2_i_o2_i_a3_0_a2_3), + .I1(plm_fsm_rc_counter_ts1_3_un1_reg_tx_count_0_a2_0_a3_4), + .I2(plm_fsm_rc_counter_ts1_3_un1_reg_tx_count_0_a2_0_a3_5), + .O(plm_fsm_rc_counter_ts1_3_N_60943_i_1958) + ); + defparam plm_fsm_rc_counter_ts1_3_loadable_rx_counter_N_60958_i.INIT = 8'hEA; + LUT3 plm_fsm_rc_counter_ts1_3_loadable_rx_counter_N_60958_i ( + .I0(N_29556_i), + .I1(plm_fsm_rc_counter_ts1_3_un1_reg_rx_count_0_a2_0_a3_4), + .I2(plm_fsm_rc_counter_ts1_3_un1_reg_rx_count_0_a2_0_a3_5), + .O(plm_fsm_rc_counter_ts1_3_N_60958_i) + ); + defparam plm_fsm_rc_counter_ts1_3_N_85659_i.INIT = 16'hEAFA; + LUT4 plm_fsm_rc_counter_ts1_3_N_85659_i ( + .I0(N_29556_i), + .I1(N_56043_i), + .I2(plm_fsm_rc_counter_ts1_3_N_59105_1), + .I3(plm_rx3_ts1_c), + .O(plm_fsm_rc_counter_ts1_3_N_85659_i_1960) + ); + defparam plm_fsm_rc_counter_ts1_3_flagit_reg_expired_5_0_a2_i_i_a3_0_a2.INIT = 8'h40; + LUT3_L plm_fsm_rc_counter_ts1_3_flagit_reg_expired_5_0_a2_i_i_a3_0_a2 ( + .I0(N_29556_i_1), + .I1(plm_fsm_rc_counter_ts1_3_reg_rx_expired_317), + .I2(plm_fsm_rc_counter_ts1_3_reg_tx_expired_1959), + .LO(plm_fsm_rc_counter_ts1_3_reg_expired_5_0_a2_i_i_a3_0_a2_2) + ); + defparam plm_fsm_rc_counter_ts1_3_loadable_rx_counter_N_60913_i.INIT = 8'hFE; + LUT3 plm_fsm_rc_counter_ts1_3_loadable_rx_counter_N_60913_i ( + .I0(plm_fsm_rc_counter_ts1_3_reg_rx_expired_317), + .I1(N_29556_i), + .I2(plm_reg_ts1_1_2), + .O(plm_fsm_rc_counter_ts1_3_N_60913_i) + ); + defparam plm_fsm_rc_counter_ts1_3_oneshot_monitor_N_60959_i.INIT = 4'hE; + LUT2 plm_fsm_rc_counter_ts1_3_oneshot_monitor_N_60959_i ( + .I0(N_29556_i), + .I1(plm_reg_ts1_1_2), + .O(plm_fsm_rc_counter_ts1_3_N_60959_i) + ); + defparam plm_fsm_rc_counter_ts1_3_N_60921_i.INIT = 4'hB; + LUT2 plm_fsm_rc_counter_ts1_3_N_60921_i ( + .I0(plm_fsm_rc_counter_ts1_3_reg_tx_expired_1959), + .I1(plm_fsm_rc_counter_ts1_3_un1_enable_1_0_a2_i_o2_i_a3_0_a2_3), + .O(plm_fsm_rc_counter_ts1_3_N_60921_i_1955) + ); + FDCE plm_fsm_rc_counter_ts1_3_reg_tx_count_7_ ( + .CE(plm_fsm_rc_counter_ts1_3_N_60928_i_1956), + .C(mgt_clk), + .D(plm_fsm_rc_counter_ts1_3_reg_tx_count_s[7]), + .Q(plm_fsm_rc_counter_ts1_3_reg_tx_count[7]), + .CLR(plm_rst) + ); + FDCE plm_fsm_rc_counter_ts1_3_reg_tx_count_6_ ( + .CE(plm_fsm_rc_counter_ts1_3_N_60928_i_1956), + .C(mgt_clk), + .D(plm_fsm_rc_counter_ts1_3_reg_tx_count_s[6]), + .Q(plm_fsm_rc_counter_ts1_3_reg_tx_count[6]), + .CLR(plm_rst) + ); + FDCE plm_fsm_rc_counter_ts1_3_reg_tx_count_5_ ( + .CE(plm_fsm_rc_counter_ts1_3_N_60928_i_1956), + .C(mgt_clk), + .D(plm_fsm_rc_counter_ts1_3_reg_tx_count_s[5]), + .Q(plm_fsm_rc_counter_ts1_3_reg_tx_count[5]), + .CLR(plm_rst) + ); + FDPE plm_fsm_rc_counter_ts1_3_reg_tx_count_4_ ( + .PRE(plm_rst), + .CE(plm_fsm_rc_counter_ts1_3_N_60928_i_1956), + .C(mgt_clk), + .D(plm_fsm_rc_counter_ts1_3_reg_tx_count_s[4]), + .Q(plm_fsm_rc_counter_ts1_3_reg_tx_count[4]) + ); + FDCE plm_fsm_rc_counter_ts1_3_reg_tx_count_3_ ( + .CE(plm_fsm_rc_counter_ts1_3_N_60928_i_1956), + .C(mgt_clk), + .D(plm_fsm_rc_counter_ts1_3_reg_tx_count_s[3]), + .Q(plm_fsm_rc_counter_ts1_3_reg_tx_count[3]), + .CLR(plm_rst) + ); + FDCE plm_fsm_rc_counter_ts1_3_reg_tx_count_2_ ( + .CE(plm_fsm_rc_counter_ts1_3_N_60928_i_1956), + .C(mgt_clk), + .D(plm_fsm_rc_counter_ts1_3_reg_tx_count_s[2]), + .Q(plm_fsm_rc_counter_ts1_3_reg_tx_count[2]), + .CLR(plm_rst) + ); + FDCE plm_fsm_rc_counter_ts1_3_reg_tx_count_1_ ( + .CE(plm_fsm_rc_counter_ts1_3_N_60928_i_1956), + .C(mgt_clk), + .D(plm_fsm_rc_counter_ts1_3_reg_tx_count_s[1]), + .Q(plm_fsm_rc_counter_ts1_3_reg_tx_count[1]), + .CLR(plm_rst) + ); + FDCE plm_fsm_rc_counter_ts1_3_reg_tx_count_0_ ( + .CE(plm_fsm_rc_counter_ts1_3_N_60928_i_1956), + .C(mgt_clk), + .D(plm_fsm_rc_counter_ts1_3_reg_tx_count_s[0]), + .Q(plm_fsm_rc_counter_ts1_3_reg_tx_count[0]), + .CLR(plm_rst) + ); + FDCE plm_fsm_rc_counter_ts1_3_reg_rx_count_7_ ( + .CE(plm_fsm_rc_counter_ts1_3_N_60913_i), + .C(mgt_clk), + .D(plm_fsm_rc_counter_ts1_3_reg_rx_count_s[7]), + .Q(plm_fsm_rc_counter_ts1_3_reg_rx_count[7]), + .CLR(plm_rst) + ); + FDCE plm_fsm_rc_counter_ts1_3_reg_rx_count_6_ ( + .CE(plm_fsm_rc_counter_ts1_3_N_60913_i), + .C(mgt_clk), + .D(plm_fsm_rc_counter_ts1_3_reg_rx_count_s[6]), + .Q(plm_fsm_rc_counter_ts1_3_reg_rx_count[6]), + .CLR(plm_rst) + ); + FDCE plm_fsm_rc_counter_ts1_3_reg_rx_count_5_ ( + .CE(plm_fsm_rc_counter_ts1_3_N_60913_i), + .C(mgt_clk), + .D(plm_fsm_rc_counter_ts1_3_reg_rx_count_s[5]), + .Q(plm_fsm_rc_counter_ts1_3_reg_rx_count[5]), + .CLR(plm_rst) + ); + FDCE plm_fsm_rc_counter_ts1_3_reg_rx_count_4_ ( + .CE(plm_fsm_rc_counter_ts1_3_N_60913_i), + .C(mgt_clk), + .D(plm_fsm_rc_counter_ts1_3_reg_rx_count_s[4]), + .Q(plm_fsm_rc_counter_ts1_3_reg_rx_count[4]), + .CLR(plm_rst) + ); + FDPE plm_fsm_rc_counter_ts1_3_reg_rx_count_3_ ( + .PRE(plm_rst), + .CE(plm_fsm_rc_counter_ts1_3_N_60913_i), + .C(mgt_clk), + .D(plm_fsm_rc_counter_ts1_3_reg_rx_count_s[3]), + .Q(plm_fsm_rc_counter_ts1_3_reg_rx_count[3]) + ); + FDCE plm_fsm_rc_counter_ts1_3_reg_rx_count_2_ ( + .CE(plm_fsm_rc_counter_ts1_3_N_60913_i), + .C(mgt_clk), + .D(plm_fsm_rc_counter_ts1_3_reg_rx_count_s[2]), + .Q(plm_fsm_rc_counter_ts1_3_reg_rx_count[2]), + .CLR(plm_rst) + ); + FDCE plm_fsm_rc_counter_ts1_3_reg_rx_count_1_ ( + .CE(plm_fsm_rc_counter_ts1_3_N_60913_i), + .C(mgt_clk), + .D(plm_fsm_rc_counter_ts1_3_reg_rx_count_s[1]), + .Q(plm_fsm_rc_counter_ts1_3_reg_rx_count[1]), + .CLR(plm_rst) + ); + FDCE plm_fsm_rc_counter_ts1_3_reg_rx_count_0_ ( + .CE(plm_fsm_rc_counter_ts1_3_N_60913_i), + .C(mgt_clk), + .D(plm_fsm_rc_counter_ts1_3_reg_rx_count_s[0]), + .Q(plm_fsm_rc_counter_ts1_3_reg_rx_count[0]), + .CLR(plm_rst) + ); + FDC plm_fsm_rc_counter_ts1_3_reg_expired ( + .C(mgt_clk), + .D(plm_fsm_rc_counter_ts1_3_reg_expired_5_0_a2_i_i_a3_0_a2_2), + .Q(plm_fsm_rc_cntrout_ts1_3), + .CLR(plm_rst) + ); + FDCE plm_fsm_rc_counter_ts1_3_reg_oneshot ( + .CE(plm_fsm_rc_counter_ts1_3_N_60959_i), + .C(mgt_clk), + .D(N_29556_i_0), + .Q(plm_fsm_rc_counter_ts1_3_reg_oneshot_1957), + .CLR(plm_rst) + ); + FDCE plm_fsm_rc_counter_ts1_3_reg_rx_expired ( + .CE(plm_fsm_rc_counter_ts1_3_N_60958_i), + .C(mgt_clk), + .D(N_29556_i_0), + .Q(plm_fsm_rc_counter_ts1_3_reg_rx_expired_317), + .CLR(plm_rst) + ); + FDCE plm_fsm_rc_counter_ts1_3_reg_tx_expired ( + .CE(plm_fsm_rc_counter_ts1_3_N_60943_i_1958), + .C(mgt_clk), + .D(plm_fsm_rc_counter_ts1_3_un1_enable_1_0_a2_i_o2_i_a3_0_a2_3), + .Q(plm_fsm_rc_counter_ts1_3_reg_tx_expired_1959), + .CLR(plm_rst) + ); + defparam plm_fsm_rc_counter_ts1_3_reg_rx_count_qxu_0_0_.INIT = 4'h7; + LUT2_L plm_fsm_rc_counter_ts1_3_reg_rx_count_qxu_0_0_ ( + .I0(N_28802_i), + .I1(plm_fsm_rc_counter_ts1_3_reg_rx_count[0]), + .LO(plm_fsm_rc_counter_ts1_3_reg_rx_count_qxu[0]) + ); + defparam plm_fsm_rc_counter_ts1_3_reg_rx_count_qxu_0_1_.INIT = 4'h7; + LUT2_L plm_fsm_rc_counter_ts1_3_reg_rx_count_qxu_0_1_ ( + .I0(N_28802_i), + .I1(plm_fsm_rc_counter_ts1_3_reg_rx_count[1]), + .LO(plm_fsm_rc_counter_ts1_3_reg_rx_count_qxu[1]) + ); + defparam plm_fsm_rc_counter_ts1_3_reg_rx_count_qxu_0_2_.INIT = 4'h7; + LUT2_L plm_fsm_rc_counter_ts1_3_reg_rx_count_qxu_0_2_ ( + .I0(N_28802_i), + .I1(plm_fsm_rc_counter_ts1_3_reg_rx_count[2]), + .LO(plm_fsm_rc_counter_ts1_3_reg_rx_count_qxu[2]) + ); + defparam plm_fsm_rc_counter_ts1_3_reg_rx_count_qxu_0_3_.INIT = 8'h1B; + LUT3_L plm_fsm_rc_counter_ts1_3_reg_rx_count_qxu_0_3_ ( + .I0(N_28802_i), + .I1(plm_fsm_rc_counter_ts1_3_N_85659_i_1960), + .I2(plm_fsm_rc_counter_ts1_3_reg_rx_count[3]), + .LO(plm_fsm_rc_counter_ts1_3_reg_rx_count_qxu[3]) + ); + defparam plm_fsm_rc_counter_ts1_3_reg_rx_count_qxu_0_4_.INIT = 4'h7; + LUT2_L plm_fsm_rc_counter_ts1_3_reg_rx_count_qxu_0_4_ ( + .I0(N_28802_i), + .I1(plm_fsm_rc_counter_ts1_3_reg_rx_count[4]), + .LO(plm_fsm_rc_counter_ts1_3_reg_rx_count_qxu[4]) + ); + defparam plm_fsm_rc_counter_ts1_3_reg_rx_count_qxu_0_5_.INIT = 4'h7; + LUT2_L plm_fsm_rc_counter_ts1_3_reg_rx_count_qxu_0_5_ ( + .I0(N_28802_i), + .I1(plm_fsm_rc_counter_ts1_3_reg_rx_count[5]), + .LO(plm_fsm_rc_counter_ts1_3_reg_rx_count_qxu[5]) + ); + defparam plm_fsm_rc_counter_ts1_3_reg_rx_count_qxu_0_6_.INIT = 4'h7; + LUT2_L plm_fsm_rc_counter_ts1_3_reg_rx_count_qxu_0_6_ ( + .I0(N_28802_i), + .I1(plm_fsm_rc_counter_ts1_3_reg_rx_count[6]), + .LO(plm_fsm_rc_counter_ts1_3_reg_rx_count_qxu[6]) + ); + defparam plm_fsm_rc_counter_ts1_3_reg_rx_count_qxu_0_7_.INIT = 4'h7; + LUT2_L plm_fsm_rc_counter_ts1_3_reg_rx_count_qxu_0_7_ ( + .I0(N_28802_i), + .I1(plm_fsm_rc_counter_ts1_3_reg_rx_count[7]), + .LO(plm_fsm_rc_counter_ts1_3_reg_rx_count_qxu[7]) + ); + defparam plm_fsm_rc_counter_ts1_3_reg_tx_count_qxu_0_0_.INIT = 4'h7; + LUT2_L plm_fsm_rc_counter_ts1_3_reg_tx_count_qxu_0_0_ ( + .I0(plm_fsm_rc_counter_ts1_3_un1_enable_1_0_a2_i_i_a3_0_a2_2), + .I1(plm_fsm_rc_counter_ts1_3_reg_tx_count[0]), + .LO(plm_fsm_rc_counter_ts1_3_reg_tx_count_qxu[0]) + ); + defparam plm_fsm_rc_counter_ts1_3_reg_tx_count_qxu_0_1_.INIT = 4'h7; + LUT2_L plm_fsm_rc_counter_ts1_3_reg_tx_count_qxu_0_1_ ( + .I0(plm_fsm_rc_counter_ts1_3_un1_enable_1_0_a2_i_i_a3_0_a2_2), + .I1(plm_fsm_rc_counter_ts1_3_reg_tx_count[1]), + .LO(plm_fsm_rc_counter_ts1_3_reg_tx_count_qxu[1]) + ); + defparam plm_fsm_rc_counter_ts1_3_reg_tx_count_qxu_0_2_.INIT = 4'h7; + LUT2_L plm_fsm_rc_counter_ts1_3_reg_tx_count_qxu_0_2_ ( + .I0(plm_fsm_rc_counter_ts1_3_un1_enable_1_0_a2_i_i_a3_0_a2_2), + .I1(plm_fsm_rc_counter_ts1_3_reg_tx_count[2]), + .LO(plm_fsm_rc_counter_ts1_3_reg_tx_count_qxu[2]) + ); + defparam plm_fsm_rc_counter_ts1_3_reg_tx_count_qxu_0_3_.INIT = 4'h7; + LUT2_L plm_fsm_rc_counter_ts1_3_reg_tx_count_qxu_0_3_ ( + .I0(plm_fsm_rc_counter_ts1_3_un1_enable_1_0_a2_i_i_a3_0_a2_2), + .I1(plm_fsm_rc_counter_ts1_3_reg_tx_count[3]), + .LO(plm_fsm_rc_counter_ts1_3_reg_tx_count_qxu[3]) + ); + defparam plm_fsm_rc_counter_ts1_3_reg_tx_count_qxu_0_4_.INIT = 8'h4E; + LUT3_L plm_fsm_rc_counter_ts1_3_reg_tx_count_qxu_0_4_ ( + .I0(plm_fsm_rc_counter_ts1_3_un1_enable_1_0_a2_i_i_a3_0_a2_2), + .I1(plm_fsm_rc_counter_ts1_3_un1_enable_1_0_a2_i_o2_i_a3_0_a2_3), + .I2(plm_fsm_rc_counter_ts1_3_reg_tx_count[4]), + .LO(plm_fsm_rc_counter_ts1_3_reg_tx_count_qxu[4]) + ); + defparam plm_fsm_rc_counter_ts1_3_reg_tx_count_qxu_0_5_.INIT = 4'h7; + LUT2_L plm_fsm_rc_counter_ts1_3_reg_tx_count_qxu_0_5_ ( + .I0(plm_fsm_rc_counter_ts1_3_un1_enable_1_0_a2_i_i_a3_0_a2_2), + .I1(plm_fsm_rc_counter_ts1_3_reg_tx_count[5]), + .LO(plm_fsm_rc_counter_ts1_3_reg_tx_count_qxu[5]) + ); + defparam plm_fsm_rc_counter_ts1_3_reg_tx_count_qxu_0_6_.INIT = 4'h7; + LUT2_L plm_fsm_rc_counter_ts1_3_reg_tx_count_qxu_0_6_ ( + .I0(plm_fsm_rc_counter_ts1_3_un1_enable_1_0_a2_i_i_a3_0_a2_2), + .I1(plm_fsm_rc_counter_ts1_3_reg_tx_count[6]), + .LO(plm_fsm_rc_counter_ts1_3_reg_tx_count_qxu[6]) + ); + defparam plm_fsm_rc_counter_ts1_3_reg_tx_count_qxu_0_7_.INIT = 4'h7; + LUT2_L plm_fsm_rc_counter_ts1_3_reg_tx_count_qxu_0_7_ ( + .I0(plm_fsm_rc_counter_ts1_3_un1_enable_1_0_a2_i_i_a3_0_a2_2), + .I1(plm_fsm_rc_counter_ts1_3_reg_tx_count[7]), + .LO(plm_fsm_rc_counter_ts1_3_reg_tx_count_qxu[7]) + ); + VCC plm_fsm_rc_counter_ts2_0_VCC ( + .P(plm_fsm_rc_counter_ts2_0_VCC_1961) + ); + MUXCY_L plm_fsm_rc_counter_ts2_0_reg_rx_count_cry_0_ ( + .CI(N_60905_i_70), + .DI(plm_fsm_rc_counter_ts2_0_VCC_1961), + .LO(plm_fsm_rc_counter_ts2_0_reg_rx_count_cry[0]), + .S(plm_fsm_rc_counter_ts2_0_reg_rx_count_qxu[0]) + ); + XORCY plm_fsm_rc_counter_ts2_0_reg_rx_count_s_0_ ( + .CI(N_60905_i_70), + .LI(plm_fsm_rc_counter_ts2_0_reg_rx_count_qxu[0]), + .O(plm_fsm_rc_counter_ts2_0_reg_rx_count_s[0]) + ); + MUXCY_L plm_fsm_rc_counter_ts2_0_reg_rx_count_cry_1_ ( + .CI(plm_fsm_rc_counter_ts2_0_reg_rx_count_cry[0]), + .DI(plm_fsm_rc_counter_ts2_0_VCC_1961), + .LO(plm_fsm_rc_counter_ts2_0_reg_rx_count_cry[1]), + .S(plm_fsm_rc_counter_ts2_0_reg_rx_count_qxu[1]) + ); + XORCY plm_fsm_rc_counter_ts2_0_reg_rx_count_s_1_ ( + .CI(plm_fsm_rc_counter_ts2_0_reg_rx_count_cry[0]), + .LI(plm_fsm_rc_counter_ts2_0_reg_rx_count_qxu[1]), + .O(plm_fsm_rc_counter_ts2_0_reg_rx_count_s[1]) + ); + MUXCY_L plm_fsm_rc_counter_ts2_0_reg_rx_count_cry_2_ ( + .CI(plm_fsm_rc_counter_ts2_0_reg_rx_count_cry[1]), + .DI(plm_fsm_rc_counter_ts2_0_VCC_1961), + .LO(plm_fsm_rc_counter_ts2_0_reg_rx_count_cry[2]), + .S(plm_fsm_rc_counter_ts2_0_reg_rx_count_qxu[2]) + ); + XORCY plm_fsm_rc_counter_ts2_0_reg_rx_count_s_2_ ( + .CI(plm_fsm_rc_counter_ts2_0_reg_rx_count_cry[1]), + .LI(plm_fsm_rc_counter_ts2_0_reg_rx_count_qxu[2]), + .O(plm_fsm_rc_counter_ts2_0_reg_rx_count_s[2]) + ); + MUXCY_L plm_fsm_rc_counter_ts2_0_reg_rx_count_cry_3_ ( + .CI(plm_fsm_rc_counter_ts2_0_reg_rx_count_cry[2]), + .DI(plm_fsm_rc_counter_ts2_0_VCC_1961), + .LO(plm_fsm_rc_counter_ts2_0_reg_rx_count_cry[3]), + .S(plm_fsm_rc_counter_ts2_0_reg_rx_count_qxu[3]) + ); + XORCY plm_fsm_rc_counter_ts2_0_reg_rx_count_s_3_ ( + .CI(plm_fsm_rc_counter_ts2_0_reg_rx_count_cry[2]), + .LI(plm_fsm_rc_counter_ts2_0_reg_rx_count_qxu[3]), + .O(plm_fsm_rc_counter_ts2_0_reg_rx_count_s[3]) + ); + MUXCY_L plm_fsm_rc_counter_ts2_0_reg_rx_count_cry_4_ ( + .CI(plm_fsm_rc_counter_ts2_0_reg_rx_count_cry[3]), + .DI(plm_fsm_rc_counter_ts2_0_VCC_1961), + .LO(plm_fsm_rc_counter_ts2_0_reg_rx_count_cry[4]), + .S(plm_fsm_rc_counter_ts2_0_reg_rx_count_qxu[4]) + ); + XORCY plm_fsm_rc_counter_ts2_0_reg_rx_count_s_4_ ( + .CI(plm_fsm_rc_counter_ts2_0_reg_rx_count_cry[3]), + .LI(plm_fsm_rc_counter_ts2_0_reg_rx_count_qxu[4]), + .O(plm_fsm_rc_counter_ts2_0_reg_rx_count_s[4]) + ); + MUXCY_L plm_fsm_rc_counter_ts2_0_reg_rx_count_cry_5_ ( + .CI(plm_fsm_rc_counter_ts2_0_reg_rx_count_cry[4]), + .DI(plm_fsm_rc_counter_ts2_0_VCC_1961), + .LO(plm_fsm_rc_counter_ts2_0_reg_rx_count_cry[5]), + .S(plm_fsm_rc_counter_ts2_0_reg_rx_count_qxu[5]) + ); + XORCY plm_fsm_rc_counter_ts2_0_reg_rx_count_s_5_ ( + .CI(plm_fsm_rc_counter_ts2_0_reg_rx_count_cry[4]), + .LI(plm_fsm_rc_counter_ts2_0_reg_rx_count_qxu[5]), + .O(plm_fsm_rc_counter_ts2_0_reg_rx_count_s[5]) + ); + MUXCY_L plm_fsm_rc_counter_ts2_0_reg_rx_count_cry_6_ ( + .CI(plm_fsm_rc_counter_ts2_0_reg_rx_count_cry[5]), + .DI(plm_fsm_rc_counter_ts2_0_VCC_1961), + .LO(plm_fsm_rc_counter_ts2_0_reg_rx_count_cry[6]), + .S(plm_fsm_rc_counter_ts2_0_reg_rx_count_qxu[6]) + ); + XORCY plm_fsm_rc_counter_ts2_0_reg_rx_count_s_6_ ( + .CI(plm_fsm_rc_counter_ts2_0_reg_rx_count_cry[5]), + .LI(plm_fsm_rc_counter_ts2_0_reg_rx_count_qxu[6]), + .O(plm_fsm_rc_counter_ts2_0_reg_rx_count_s[6]) + ); + XORCY plm_fsm_rc_counter_ts2_0_reg_rx_count_s_7_ ( + .CI(plm_fsm_rc_counter_ts2_0_reg_rx_count_cry[6]), + .LI(plm_fsm_rc_counter_ts2_0_reg_rx_count_qxu[7]), + .O(plm_fsm_rc_counter_ts2_0_reg_rx_count_s[7]) + ); + MUXCY_L plm_fsm_rc_counter_ts2_0_reg_tx_count_cry_0_ ( + .CI(plm_fsm_rc_counter_ts2_0_N_60920_i_1962), + .DI(plm_fsm_rc_counter_ts2_0_VCC_1961), + .LO(plm_fsm_rc_counter_ts2_0_reg_tx_count_cry[0]), + .S(plm_fsm_rc_counter_ts2_0_reg_tx_count_qxu[0]) + ); + XORCY plm_fsm_rc_counter_ts2_0_reg_tx_count_s_0_ ( + .CI(plm_fsm_rc_counter_ts2_0_N_60920_i_1962), + .LI(plm_fsm_rc_counter_ts2_0_reg_tx_count_qxu[0]), + .O(plm_fsm_rc_counter_ts2_0_reg_tx_count_s[0]) + ); + MUXCY_L plm_fsm_rc_counter_ts2_0_reg_tx_count_cry_1_ ( + .CI(plm_fsm_rc_counter_ts2_0_reg_tx_count_cry[0]), + .DI(plm_fsm_rc_counter_ts2_0_VCC_1961), + .LO(plm_fsm_rc_counter_ts2_0_reg_tx_count_cry[1]), + .S(plm_fsm_rc_counter_ts2_0_reg_tx_count_qxu[1]) + ); + XORCY plm_fsm_rc_counter_ts2_0_reg_tx_count_s_1_ ( + .CI(plm_fsm_rc_counter_ts2_0_reg_tx_count_cry[0]), + .LI(plm_fsm_rc_counter_ts2_0_reg_tx_count_qxu[1]), + .O(plm_fsm_rc_counter_ts2_0_reg_tx_count_s[1]) + ); + MUXCY_L plm_fsm_rc_counter_ts2_0_reg_tx_count_cry_2_ ( + .CI(plm_fsm_rc_counter_ts2_0_reg_tx_count_cry[1]), + .DI(plm_fsm_rc_counter_ts2_0_VCC_1961), + .LO(plm_fsm_rc_counter_ts2_0_reg_tx_count_cry[2]), + .S(plm_fsm_rc_counter_ts2_0_reg_tx_count_qxu[2]) + ); + XORCY plm_fsm_rc_counter_ts2_0_reg_tx_count_s_2_ ( + .CI(plm_fsm_rc_counter_ts2_0_reg_tx_count_cry[1]), + .LI(plm_fsm_rc_counter_ts2_0_reg_tx_count_qxu[2]), + .O(plm_fsm_rc_counter_ts2_0_reg_tx_count_s[2]) + ); + MUXCY_L plm_fsm_rc_counter_ts2_0_reg_tx_count_cry_3_ ( + .CI(plm_fsm_rc_counter_ts2_0_reg_tx_count_cry[2]), + .DI(plm_fsm_rc_counter_ts2_0_VCC_1961), + .LO(plm_fsm_rc_counter_ts2_0_reg_tx_count_cry[3]), + .S(plm_fsm_rc_counter_ts2_0_reg_tx_count_qxu[3]) + ); + XORCY plm_fsm_rc_counter_ts2_0_reg_tx_count_s_3_ ( + .CI(plm_fsm_rc_counter_ts2_0_reg_tx_count_cry[2]), + .LI(plm_fsm_rc_counter_ts2_0_reg_tx_count_qxu[3]), + .O(plm_fsm_rc_counter_ts2_0_reg_tx_count_s[3]) + ); + MUXCY_L plm_fsm_rc_counter_ts2_0_reg_tx_count_cry_4_ ( + .CI(plm_fsm_rc_counter_ts2_0_reg_tx_count_cry[3]), + .DI(plm_fsm_rc_counter_ts2_0_VCC_1961), + .LO(plm_fsm_rc_counter_ts2_0_reg_tx_count_cry[4]), + .S(plm_fsm_rc_counter_ts2_0_reg_tx_count_qxu[4]) + ); + XORCY plm_fsm_rc_counter_ts2_0_reg_tx_count_s_4_ ( + .CI(plm_fsm_rc_counter_ts2_0_reg_tx_count_cry[3]), + .LI(plm_fsm_rc_counter_ts2_0_reg_tx_count_qxu[4]), + .O(plm_fsm_rc_counter_ts2_0_reg_tx_count_s[4]) + ); + MUXCY_L plm_fsm_rc_counter_ts2_0_reg_tx_count_cry_5_ ( + .CI(plm_fsm_rc_counter_ts2_0_reg_tx_count_cry[4]), + .DI(plm_fsm_rc_counter_ts2_0_VCC_1961), + .LO(plm_fsm_rc_counter_ts2_0_reg_tx_count_cry[5]), + .S(plm_fsm_rc_counter_ts2_0_reg_tx_count_qxu[5]) + ); + XORCY plm_fsm_rc_counter_ts2_0_reg_tx_count_s_5_ ( + .CI(plm_fsm_rc_counter_ts2_0_reg_tx_count_cry[4]), + .LI(plm_fsm_rc_counter_ts2_0_reg_tx_count_qxu[5]), + .O(plm_fsm_rc_counter_ts2_0_reg_tx_count_s[5]) + ); + MUXCY_L plm_fsm_rc_counter_ts2_0_reg_tx_count_cry_6_ ( + .CI(plm_fsm_rc_counter_ts2_0_reg_tx_count_cry[5]), + .DI(plm_fsm_rc_counter_ts2_0_VCC_1961), + .LO(plm_fsm_rc_counter_ts2_0_reg_tx_count_cry[6]), + .S(plm_fsm_rc_counter_ts2_0_reg_tx_count_qxu[6]) + ); + XORCY plm_fsm_rc_counter_ts2_0_reg_tx_count_s_6_ ( + .CI(plm_fsm_rc_counter_ts2_0_reg_tx_count_cry[5]), + .LI(plm_fsm_rc_counter_ts2_0_reg_tx_count_qxu[6]), + .O(plm_fsm_rc_counter_ts2_0_reg_tx_count_s[6]) + ); + XORCY plm_fsm_rc_counter_ts2_0_reg_tx_count_s_7_ ( + .CI(plm_fsm_rc_counter_ts2_0_reg_tx_count_cry[6]), + .LI(plm_fsm_rc_counter_ts2_0_reg_tx_count_qxu[7]), + .O(plm_fsm_rc_counter_ts2_0_reg_tx_count_s[7]) + ); + defparam plm_fsm_rc_counter_ts2_0_un1_enable_1_0_a2_i_o2_i_a3_0_a2.INIT = 4'h4; + LUT2 plm_fsm_rc_counter_ts2_0_un1_enable_1_0_a2_i_o2_i_a3_0_a2 ( + .I0(N_29556_i), + .I1(plm_fsm_rc_counter_ts2_0_reg_oneshot_1964), + .O(plm_fsm_rc_counter_ts2_0_un1_enable_1_0_a2_i_o2_i_a3_0_a2_2) + ); + defparam plm_fsm_rc_counter_ts2_0_loadable_rx_counter_un1_reg_rx_count_0_a2_0_a3_4.INIT = 16'h0001; + LUT4 plm_fsm_rc_counter_ts2_0_loadable_rx_counter_un1_reg_rx_count_0_a2_0_a3_4 ( + .I0(plm_fsm_rc_counter_ts2_0_reg_rx_count[0]), + .I1(plm_fsm_rc_counter_ts2_0_reg_rx_count[1]), + .I2(plm_fsm_rc_counter_ts2_0_reg_rx_count[2]), + .I3(plm_fsm_rc_counter_ts2_0_reg_rx_count[3]), + .O(plm_fsm_rc_counter_ts2_0_un1_reg_rx_count_0_a2_0_a3_4) + ); + defparam plm_fsm_rc_counter_ts2_0_loadable_rx_counter_un1_reg_rx_count_0_a2_0_a3_5.INIT = 16'h0001; + LUT4 plm_fsm_rc_counter_ts2_0_loadable_rx_counter_un1_reg_rx_count_0_a2_0_a3_5 ( + .I0(plm_fsm_rc_counter_ts2_0_reg_rx_count[4]), + .I1(plm_fsm_rc_counter_ts2_0_reg_rx_count[5]), + .I2(plm_fsm_rc_counter_ts2_0_reg_rx_count[6]), + .I3(plm_fsm_rc_counter_ts2_0_reg_rx_count[7]), + .O(plm_fsm_rc_counter_ts2_0_un1_reg_rx_count_0_a2_0_a3_5) + ); + defparam plm_fsm_rc_counter_ts2_0_loadable_tx_counter_un1_reg_tx_count_0_a2_0_a3_4.INIT = 16'h0001; + LUT4 plm_fsm_rc_counter_ts2_0_loadable_tx_counter_un1_reg_tx_count_0_a2_0_a3_4 ( + .I0(plm_fsm_rc_counter_ts2_0_reg_tx_count[0]), + .I1(plm_fsm_rc_counter_ts2_0_reg_tx_count[1]), + .I2(plm_fsm_rc_counter_ts2_0_reg_tx_count[2]), + .I3(plm_fsm_rc_counter_ts2_0_reg_tx_count[3]), + .O(plm_fsm_rc_counter_ts2_0_un1_reg_tx_count_0_a2_0_a3_4) + ); + defparam plm_fsm_rc_counter_ts2_0_loadable_tx_counter_un1_reg_tx_count_0_a2_0_a3_5.INIT = 16'h0001; + LUT4 plm_fsm_rc_counter_ts2_0_loadable_tx_counter_un1_reg_tx_count_0_a2_0_a3_5 ( + .I0(plm_fsm_rc_counter_ts2_0_reg_tx_count[4]), + .I1(plm_fsm_rc_counter_ts2_0_reg_tx_count[5]), + .I2(plm_fsm_rc_counter_ts2_0_reg_tx_count[6]), + .I3(plm_fsm_rc_counter_ts2_0_reg_tx_count[7]), + .O(plm_fsm_rc_counter_ts2_0_un1_reg_tx_count_0_a2_0_a3_5) + ); + defparam plm_fsm_rc_counter_ts2_0_un1_enable_1_0_a2_i_i_a3_0_a2.INIT = 4'h2; + LUT2 plm_fsm_rc_counter_ts2_0_un1_enable_1_0_a2_i_i_a3_0_a2 ( + .I0(plm_fsm_rc_counter_ts2_0_un1_enable_1_0_a2_i_o2_i_a3_0_a2_2), + .I1(plm_fsm_rc_counter_ts2_0_reg_tx_expired_1966), + .O(plm_fsm_rc_counter_ts2_0_un1_enable_1_0_a2_i_i_a3_0_a2_3) + ); + defparam plm_fsm_rc_counter_ts2_0_N_60929_i.INIT = 16'hFFEF; + LUT4 plm_fsm_rc_counter_ts2_0_N_60929_i ( + .I0(plm_reg_sym_sent_6_), + .I1(N_29556_i), + .I2(plm_fsm_rc_counter_ts2_0_reg_oneshot_1964), + .I3(plm_fsm_rc_counter_ts2_0_reg_tx_expired_1966), + .O(plm_fsm_rc_counter_ts2_0_N_60929_i_1963) + ); + defparam plm_fsm_rc_counter_ts2_0_N_60941_i.INIT = 8'hD5; + LUT3 plm_fsm_rc_counter_ts2_0_N_60941_i ( + .I0(plm_fsm_rc_counter_ts2_0_un1_enable_1_0_a2_i_o2_i_a3_0_a2_2), + .I1(plm_fsm_rc_counter_ts2_0_un1_reg_tx_count_0_a2_0_a3_4), + .I2(plm_fsm_rc_counter_ts2_0_un1_reg_tx_count_0_a2_0_a3_5), + .O(plm_fsm_rc_counter_ts2_0_N_60941_i_1965) + ); + defparam plm_fsm_rc_counter_ts2_0_loadable_rx_counter_N_60956_i.INIT = 8'hEA; + LUT3 plm_fsm_rc_counter_ts2_0_loadable_rx_counter_N_60956_i ( + .I0(N_29556_i), + .I1(plm_fsm_rc_counter_ts2_0_un1_reg_rx_count_0_a2_0_a3_4), + .I2(plm_fsm_rc_counter_ts2_0_un1_reg_rx_count_0_a2_0_a3_5), + .O(plm_fsm_rc_counter_ts2_0_N_60956_i) + ); + defparam plm_fsm_rc_counter_ts2_0_N_87192_i.INIT = 16'hCCCE; + LUT4 plm_fsm_rc_counter_ts2_0_N_87192_i ( + .I0(plm_reg_ts2_1), + .I1(N_29556_i), + .I2(N_56156_i), + .I3(plm_fsm_rc_counter_ts2_0_reg_rx_expired_69), + .O(plm_fsm_rc_counter_ts2_0_N_87192_i_1967) + ); + defparam plm_fsm_rc_counter_ts2_0_flagit_reg_expired_5_0_a2_i_i_a3_0_a2.INIT = 8'h40; + LUT3_L plm_fsm_rc_counter_ts2_0_flagit_reg_expired_5_0_a2_i_i_a3_0_a2 ( + .I0(N_29556_i_1), + .I1(plm_fsm_rc_counter_ts2_0_reg_rx_expired_69), + .I2(plm_fsm_rc_counter_ts2_0_reg_tx_expired_1966), + .LO(plm_fsm_rc_counter_ts2_0_reg_expired_5_0_a2_i_i_a3_0_a2_3) + ); + defparam plm_fsm_rc_counter_ts2_0_loadable_rx_counter_N_60906_i.INIT = 8'hFE; + LUT3 plm_fsm_rc_counter_ts2_0_loadable_rx_counter_N_60906_i ( + .I0(plm_fsm_rc_counter_ts2_0_reg_rx_expired_69), + .I1(N_29556_i), + .I2(plm_reg_ts2_1), + .O(plm_fsm_rc_counter_ts2_0_N_60906_i) + ); + defparam plm_fsm_rc_counter_ts2_0_oneshot_monitor_N_60957_i.INIT = 4'hE; + LUT2 plm_fsm_rc_counter_ts2_0_oneshot_monitor_N_60957_i ( + .I0(N_29556_i), + .I1(plm_reg_ts2_1), + .O(plm_fsm_rc_counter_ts2_0_N_60957_i) + ); + defparam plm_fsm_rc_counter_ts2_0_N_60920_i.INIT = 4'hB; + LUT2 plm_fsm_rc_counter_ts2_0_N_60920_i ( + .I0(plm_fsm_rc_counter_ts2_0_reg_tx_expired_1966), + .I1(plm_fsm_rc_counter_ts2_0_un1_enable_1_0_a2_i_o2_i_a3_0_a2_2), + .O(plm_fsm_rc_counter_ts2_0_N_60920_i_1962) + ); + FDCE plm_fsm_rc_counter_ts2_0_reg_tx_count_7_ ( + .CE(plm_fsm_rc_counter_ts2_0_N_60929_i_1963), + .C(mgt_clk), + .D(plm_fsm_rc_counter_ts2_0_reg_tx_count_s[7]), + .Q(plm_fsm_rc_counter_ts2_0_reg_tx_count[7]), + .CLR(plm_rst) + ); + FDCE plm_fsm_rc_counter_ts2_0_reg_tx_count_6_ ( + .CE(plm_fsm_rc_counter_ts2_0_N_60929_i_1963), + .C(mgt_clk), + .D(plm_fsm_rc_counter_ts2_0_reg_tx_count_s[6]), + .Q(plm_fsm_rc_counter_ts2_0_reg_tx_count[6]), + .CLR(plm_rst) + ); + FDCE plm_fsm_rc_counter_ts2_0_reg_tx_count_5_ ( + .CE(plm_fsm_rc_counter_ts2_0_N_60929_i_1963), + .C(mgt_clk), + .D(plm_fsm_rc_counter_ts2_0_reg_tx_count_s[5]), + .Q(plm_fsm_rc_counter_ts2_0_reg_tx_count[5]), + .CLR(plm_rst) + ); + FDPE plm_fsm_rc_counter_ts2_0_reg_tx_count_4_ ( + .PRE(plm_rst), + .CE(plm_fsm_rc_counter_ts2_0_N_60929_i_1963), + .C(mgt_clk), + .D(plm_fsm_rc_counter_ts2_0_reg_tx_count_s[4]), + .Q(plm_fsm_rc_counter_ts2_0_reg_tx_count[4]) + ); + FDCE plm_fsm_rc_counter_ts2_0_reg_tx_count_3_ ( + .CE(plm_fsm_rc_counter_ts2_0_N_60929_i_1963), + .C(mgt_clk), + .D(plm_fsm_rc_counter_ts2_0_reg_tx_count_s[3]), + .Q(plm_fsm_rc_counter_ts2_0_reg_tx_count[3]), + .CLR(plm_rst) + ); + FDCE plm_fsm_rc_counter_ts2_0_reg_tx_count_2_ ( + .CE(plm_fsm_rc_counter_ts2_0_N_60929_i_1963), + .C(mgt_clk), + .D(plm_fsm_rc_counter_ts2_0_reg_tx_count_s[2]), + .Q(plm_fsm_rc_counter_ts2_0_reg_tx_count[2]), + .CLR(plm_rst) + ); + FDCE plm_fsm_rc_counter_ts2_0_reg_tx_count_1_ ( + .CE(plm_fsm_rc_counter_ts2_0_N_60929_i_1963), + .C(mgt_clk), + .D(plm_fsm_rc_counter_ts2_0_reg_tx_count_s[1]), + .Q(plm_fsm_rc_counter_ts2_0_reg_tx_count[1]), + .CLR(plm_rst) + ); + FDCE plm_fsm_rc_counter_ts2_0_reg_tx_count_0_ ( + .CE(plm_fsm_rc_counter_ts2_0_N_60929_i_1963), + .C(mgt_clk), + .D(plm_fsm_rc_counter_ts2_0_reg_tx_count_s[0]), + .Q(plm_fsm_rc_counter_ts2_0_reg_tx_count[0]), + .CLR(plm_rst) + ); + FDCE plm_fsm_rc_counter_ts2_0_reg_rx_count_7_ ( + .CE(plm_fsm_rc_counter_ts2_0_N_60906_i), + .C(mgt_clk), + .D(plm_fsm_rc_counter_ts2_0_reg_rx_count_s[7]), + .Q(plm_fsm_rc_counter_ts2_0_reg_rx_count[7]), + .CLR(plm_rst) + ); + FDCE plm_fsm_rc_counter_ts2_0_reg_rx_count_6_ ( + .CE(plm_fsm_rc_counter_ts2_0_N_60906_i), + .C(mgt_clk), + .D(plm_fsm_rc_counter_ts2_0_reg_rx_count_s[6]), + .Q(plm_fsm_rc_counter_ts2_0_reg_rx_count[6]), + .CLR(plm_rst) + ); + FDCE plm_fsm_rc_counter_ts2_0_reg_rx_count_5_ ( + .CE(plm_fsm_rc_counter_ts2_0_N_60906_i), + .C(mgt_clk), + .D(plm_fsm_rc_counter_ts2_0_reg_rx_count_s[5]), + .Q(plm_fsm_rc_counter_ts2_0_reg_rx_count[5]), + .CLR(plm_rst) + ); + FDCE plm_fsm_rc_counter_ts2_0_reg_rx_count_4_ ( + .CE(plm_fsm_rc_counter_ts2_0_N_60906_i), + .C(mgt_clk), + .D(plm_fsm_rc_counter_ts2_0_reg_rx_count_s[4]), + .Q(plm_fsm_rc_counter_ts2_0_reg_rx_count[4]), + .CLR(plm_rst) + ); + FDPE plm_fsm_rc_counter_ts2_0_reg_rx_count_3_ ( + .PRE(plm_rst), + .CE(plm_fsm_rc_counter_ts2_0_N_60906_i), + .C(mgt_clk), + .D(plm_fsm_rc_counter_ts2_0_reg_rx_count_s[3]), + .Q(plm_fsm_rc_counter_ts2_0_reg_rx_count[3]) + ); + FDCE plm_fsm_rc_counter_ts2_0_reg_rx_count_2_ ( + .CE(plm_fsm_rc_counter_ts2_0_N_60906_i), + .C(mgt_clk), + .D(plm_fsm_rc_counter_ts2_0_reg_rx_count_s[2]), + .Q(plm_fsm_rc_counter_ts2_0_reg_rx_count[2]), + .CLR(plm_rst) + ); + FDCE plm_fsm_rc_counter_ts2_0_reg_rx_count_1_ ( + .CE(plm_fsm_rc_counter_ts2_0_N_60906_i), + .C(mgt_clk), + .D(plm_fsm_rc_counter_ts2_0_reg_rx_count_s[1]), + .Q(plm_fsm_rc_counter_ts2_0_reg_rx_count[1]), + .CLR(plm_rst) + ); + FDCE plm_fsm_rc_counter_ts2_0_reg_rx_count_0_ ( + .CE(plm_fsm_rc_counter_ts2_0_N_60906_i), + .C(mgt_clk), + .D(plm_fsm_rc_counter_ts2_0_reg_rx_count_s[0]), + .Q(plm_fsm_rc_counter_ts2_0_reg_rx_count[0]), + .CLR(plm_rst) + ); + FDC plm_fsm_rc_counter_ts2_0_reg_expired ( + .C(mgt_clk), + .D(plm_fsm_rc_counter_ts2_0_reg_expired_5_0_a2_i_i_a3_0_a2_3), + .Q(plm_fsm_rc_cntrout_ts2_0), + .CLR(plm_rst) + ); + FDCE plm_fsm_rc_counter_ts2_0_reg_oneshot ( + .CE(plm_fsm_rc_counter_ts2_0_N_60957_i), + .C(mgt_clk), + .D(N_29556_i_0), + .Q(plm_fsm_rc_counter_ts2_0_reg_oneshot_1964), + .CLR(plm_rst) + ); + FDCE plm_fsm_rc_counter_ts2_0_reg_rx_expired ( + .CE(plm_fsm_rc_counter_ts2_0_N_60956_i), + .C(mgt_clk), + .D(N_29556_i_0), + .Q(plm_fsm_rc_counter_ts2_0_reg_rx_expired_69), + .CLR(plm_rst) + ); + FDCE plm_fsm_rc_counter_ts2_0_reg_tx_expired ( + .CE(plm_fsm_rc_counter_ts2_0_N_60941_i_1965), + .C(mgt_clk), + .D(plm_fsm_rc_counter_ts2_0_un1_enable_1_0_a2_i_o2_i_a3_0_a2_2), + .Q(plm_fsm_rc_counter_ts2_0_reg_tx_expired_1966), + .CLR(plm_rst) + ); + defparam plm_fsm_rc_counter_ts2_0_reg_rx_count_qxu_0_0_.INIT = 4'h7; + LUT2_L plm_fsm_rc_counter_ts2_0_reg_rx_count_qxu_0_0_ ( + .I0(I_5318_i_0_i_a3_0_a2_308), + .I1(plm_fsm_rc_counter_ts2_0_reg_rx_count[0]), + .LO(plm_fsm_rc_counter_ts2_0_reg_rx_count_qxu[0]) + ); + defparam plm_fsm_rc_counter_ts2_0_reg_rx_count_qxu_0_1_.INIT = 4'h7; + LUT2_L plm_fsm_rc_counter_ts2_0_reg_rx_count_qxu_0_1_ ( + .I0(I_5318_i_0_i_a3_0_a2_308), + .I1(plm_fsm_rc_counter_ts2_0_reg_rx_count[1]), + .LO(plm_fsm_rc_counter_ts2_0_reg_rx_count_qxu[1]) + ); + defparam plm_fsm_rc_counter_ts2_0_reg_rx_count_qxu_0_2_.INIT = 4'h7; + LUT2_L plm_fsm_rc_counter_ts2_0_reg_rx_count_qxu_0_2_ ( + .I0(I_5318_i_0_i_a3_0_a2_308), + .I1(plm_fsm_rc_counter_ts2_0_reg_rx_count[2]), + .LO(plm_fsm_rc_counter_ts2_0_reg_rx_count_qxu[2]) + ); + defparam plm_fsm_rc_counter_ts2_0_reg_rx_count_qxu_0_3_.INIT = 8'h1B; + LUT3_L plm_fsm_rc_counter_ts2_0_reg_rx_count_qxu_0_3_ ( + .I0(I_5318_i_0_i_a3_0_a2_308), + .I1(plm_fsm_rc_counter_ts2_0_N_87192_i_1967), + .I2(plm_fsm_rc_counter_ts2_0_reg_rx_count[3]), + .LO(plm_fsm_rc_counter_ts2_0_reg_rx_count_qxu[3]) + ); + defparam plm_fsm_rc_counter_ts2_0_reg_rx_count_qxu_0_4_.INIT = 4'h7; + LUT2_L plm_fsm_rc_counter_ts2_0_reg_rx_count_qxu_0_4_ ( + .I0(I_5318_i_0_i_a3_0_a2_308), + .I1(plm_fsm_rc_counter_ts2_0_reg_rx_count[4]), + .LO(plm_fsm_rc_counter_ts2_0_reg_rx_count_qxu[4]) + ); + defparam plm_fsm_rc_counter_ts2_0_reg_rx_count_qxu_0_5_.INIT = 4'h7; + LUT2_L plm_fsm_rc_counter_ts2_0_reg_rx_count_qxu_0_5_ ( + .I0(I_5318_i_0_i_a3_0_a2_308), + .I1(plm_fsm_rc_counter_ts2_0_reg_rx_count[5]), + .LO(plm_fsm_rc_counter_ts2_0_reg_rx_count_qxu[5]) + ); + defparam plm_fsm_rc_counter_ts2_0_reg_rx_count_qxu_0_6_.INIT = 4'h7; + LUT2_L plm_fsm_rc_counter_ts2_0_reg_rx_count_qxu_0_6_ ( + .I0(I_5318_i_0_i_a3_0_a2_308), + .I1(plm_fsm_rc_counter_ts2_0_reg_rx_count[6]), + .LO(plm_fsm_rc_counter_ts2_0_reg_rx_count_qxu[6]) + ); + defparam plm_fsm_rc_counter_ts2_0_reg_rx_count_qxu_0_7_.INIT = 4'h7; + LUT2_L plm_fsm_rc_counter_ts2_0_reg_rx_count_qxu_0_7_ ( + .I0(I_5318_i_0_i_a3_0_a2_308), + .I1(plm_fsm_rc_counter_ts2_0_reg_rx_count[7]), + .LO(plm_fsm_rc_counter_ts2_0_reg_rx_count_qxu[7]) + ); + defparam plm_fsm_rc_counter_ts2_0_reg_tx_count_qxu_0_0_.INIT = 4'h7; + LUT2_L plm_fsm_rc_counter_ts2_0_reg_tx_count_qxu_0_0_ ( + .I0(plm_fsm_rc_counter_ts2_0_un1_enable_1_0_a2_i_i_a3_0_a2_3), + .I1(plm_fsm_rc_counter_ts2_0_reg_tx_count[0]), + .LO(plm_fsm_rc_counter_ts2_0_reg_tx_count_qxu[0]) + ); + defparam plm_fsm_rc_counter_ts2_0_reg_tx_count_qxu_0_1_.INIT = 4'h7; + LUT2_L plm_fsm_rc_counter_ts2_0_reg_tx_count_qxu_0_1_ ( + .I0(plm_fsm_rc_counter_ts2_0_un1_enable_1_0_a2_i_i_a3_0_a2_3), + .I1(plm_fsm_rc_counter_ts2_0_reg_tx_count[1]), + .LO(plm_fsm_rc_counter_ts2_0_reg_tx_count_qxu[1]) + ); + defparam plm_fsm_rc_counter_ts2_0_reg_tx_count_qxu_0_2_.INIT = 4'h7; + LUT2_L plm_fsm_rc_counter_ts2_0_reg_tx_count_qxu_0_2_ ( + .I0(plm_fsm_rc_counter_ts2_0_un1_enable_1_0_a2_i_i_a3_0_a2_3), + .I1(plm_fsm_rc_counter_ts2_0_reg_tx_count[2]), + .LO(plm_fsm_rc_counter_ts2_0_reg_tx_count_qxu[2]) + ); + defparam plm_fsm_rc_counter_ts2_0_reg_tx_count_qxu_0_3_.INIT = 4'h7; + LUT2_L plm_fsm_rc_counter_ts2_0_reg_tx_count_qxu_0_3_ ( + .I0(plm_fsm_rc_counter_ts2_0_un1_enable_1_0_a2_i_i_a3_0_a2_3), + .I1(plm_fsm_rc_counter_ts2_0_reg_tx_count[3]), + .LO(plm_fsm_rc_counter_ts2_0_reg_tx_count_qxu[3]) + ); + defparam plm_fsm_rc_counter_ts2_0_reg_tx_count_qxu_0_4_.INIT = 8'h4E; + LUT3_L plm_fsm_rc_counter_ts2_0_reg_tx_count_qxu_0_4_ ( + .I0(plm_fsm_rc_counter_ts2_0_un1_enable_1_0_a2_i_i_a3_0_a2_3), + .I1(plm_fsm_rc_counter_ts2_0_un1_enable_1_0_a2_i_o2_i_a3_0_a2_2), + .I2(plm_fsm_rc_counter_ts2_0_reg_tx_count[4]), + .LO(plm_fsm_rc_counter_ts2_0_reg_tx_count_qxu[4]) + ); + defparam plm_fsm_rc_counter_ts2_0_reg_tx_count_qxu_0_5_.INIT = 4'h7; + LUT2_L plm_fsm_rc_counter_ts2_0_reg_tx_count_qxu_0_5_ ( + .I0(plm_fsm_rc_counter_ts2_0_un1_enable_1_0_a2_i_i_a3_0_a2_3), + .I1(plm_fsm_rc_counter_ts2_0_reg_tx_count[5]), + .LO(plm_fsm_rc_counter_ts2_0_reg_tx_count_qxu[5]) + ); + defparam plm_fsm_rc_counter_ts2_0_reg_tx_count_qxu_0_6_.INIT = 4'h7; + LUT2_L plm_fsm_rc_counter_ts2_0_reg_tx_count_qxu_0_6_ ( + .I0(plm_fsm_rc_counter_ts2_0_un1_enable_1_0_a2_i_i_a3_0_a2_3), + .I1(plm_fsm_rc_counter_ts2_0_reg_tx_count[6]), + .LO(plm_fsm_rc_counter_ts2_0_reg_tx_count_qxu[6]) + ); + defparam plm_fsm_rc_counter_ts2_0_reg_tx_count_qxu_0_7_.INIT = 4'h7; + LUT2_L plm_fsm_rc_counter_ts2_0_reg_tx_count_qxu_0_7_ ( + .I0(plm_fsm_rc_counter_ts2_0_un1_enable_1_0_a2_i_i_a3_0_a2_3), + .I1(plm_fsm_rc_counter_ts2_0_reg_tx_count[7]), + .LO(plm_fsm_rc_counter_ts2_0_reg_tx_count_qxu[7]) + ); + VCC plm_fsm_rc_counter_ts2_1_VCC ( + .P(plm_fsm_rc_counter_ts2_1_VCC_1968) + ); + MUXCY_L plm_fsm_rc_counter_ts2_1_reg_rx_count_cry_0_ ( + .CI(N_60904_i_20), + .DI(plm_fsm_rc_counter_ts2_1_VCC_1968), + .LO(plm_fsm_rc_counter_ts2_1_reg_rx_count_cry[0]), + .S(plm_fsm_rc_counter_ts2_1_reg_rx_count_qxu[0]) + ); + XORCY plm_fsm_rc_counter_ts2_1_reg_rx_count_s_0_ ( + .CI(N_60904_i_20), + .LI(plm_fsm_rc_counter_ts2_1_reg_rx_count_qxu[0]), + .O(plm_fsm_rc_counter_ts2_1_reg_rx_count_s[0]) + ); + MUXCY_L plm_fsm_rc_counter_ts2_1_reg_rx_count_cry_1_ ( + .CI(plm_fsm_rc_counter_ts2_1_reg_rx_count_cry[0]), + .DI(plm_fsm_rc_counter_ts2_1_VCC_1968), + .LO(plm_fsm_rc_counter_ts2_1_reg_rx_count_cry[1]), + .S(plm_fsm_rc_counter_ts2_1_reg_rx_count_qxu[1]) + ); + XORCY plm_fsm_rc_counter_ts2_1_reg_rx_count_s_1_ ( + .CI(plm_fsm_rc_counter_ts2_1_reg_rx_count_cry[0]), + .LI(plm_fsm_rc_counter_ts2_1_reg_rx_count_qxu[1]), + .O(plm_fsm_rc_counter_ts2_1_reg_rx_count_s[1]) + ); + MUXCY_L plm_fsm_rc_counter_ts2_1_reg_rx_count_cry_2_ ( + .CI(plm_fsm_rc_counter_ts2_1_reg_rx_count_cry[1]), + .DI(plm_fsm_rc_counter_ts2_1_VCC_1968), + .LO(plm_fsm_rc_counter_ts2_1_reg_rx_count_cry[2]), + .S(plm_fsm_rc_counter_ts2_1_reg_rx_count_qxu[2]) + ); + XORCY plm_fsm_rc_counter_ts2_1_reg_rx_count_s_2_ ( + .CI(plm_fsm_rc_counter_ts2_1_reg_rx_count_cry[1]), + .LI(plm_fsm_rc_counter_ts2_1_reg_rx_count_qxu[2]), + .O(plm_fsm_rc_counter_ts2_1_reg_rx_count_s[2]) + ); + MUXCY_L plm_fsm_rc_counter_ts2_1_reg_rx_count_cry_3_ ( + .CI(plm_fsm_rc_counter_ts2_1_reg_rx_count_cry[2]), + .DI(plm_fsm_rc_counter_ts2_1_VCC_1968), + .LO(plm_fsm_rc_counter_ts2_1_reg_rx_count_cry[3]), + .S(plm_fsm_rc_counter_ts2_1_reg_rx_count_qxu[3]) + ); + XORCY plm_fsm_rc_counter_ts2_1_reg_rx_count_s_3_ ( + .CI(plm_fsm_rc_counter_ts2_1_reg_rx_count_cry[2]), + .LI(plm_fsm_rc_counter_ts2_1_reg_rx_count_qxu[3]), + .O(plm_fsm_rc_counter_ts2_1_reg_rx_count_s[3]) + ); + MUXCY_L plm_fsm_rc_counter_ts2_1_reg_rx_count_cry_4_ ( + .CI(plm_fsm_rc_counter_ts2_1_reg_rx_count_cry[3]), + .DI(plm_fsm_rc_counter_ts2_1_VCC_1968), + .LO(plm_fsm_rc_counter_ts2_1_reg_rx_count_cry[4]), + .S(plm_fsm_rc_counter_ts2_1_reg_rx_count_qxu[4]) + ); + XORCY plm_fsm_rc_counter_ts2_1_reg_rx_count_s_4_ ( + .CI(plm_fsm_rc_counter_ts2_1_reg_rx_count_cry[3]), + .LI(plm_fsm_rc_counter_ts2_1_reg_rx_count_qxu[4]), + .O(plm_fsm_rc_counter_ts2_1_reg_rx_count_s[4]) + ); + MUXCY_L plm_fsm_rc_counter_ts2_1_reg_rx_count_cry_5_ ( + .CI(plm_fsm_rc_counter_ts2_1_reg_rx_count_cry[4]), + .DI(plm_fsm_rc_counter_ts2_1_VCC_1968), + .LO(plm_fsm_rc_counter_ts2_1_reg_rx_count_cry[5]), + .S(plm_fsm_rc_counter_ts2_1_reg_rx_count_qxu[5]) + ); + XORCY plm_fsm_rc_counter_ts2_1_reg_rx_count_s_5_ ( + .CI(plm_fsm_rc_counter_ts2_1_reg_rx_count_cry[4]), + .LI(plm_fsm_rc_counter_ts2_1_reg_rx_count_qxu[5]), + .O(plm_fsm_rc_counter_ts2_1_reg_rx_count_s[5]) + ); + MUXCY_L plm_fsm_rc_counter_ts2_1_reg_rx_count_cry_6_ ( + .CI(plm_fsm_rc_counter_ts2_1_reg_rx_count_cry[5]), + .DI(plm_fsm_rc_counter_ts2_1_VCC_1968), + .LO(plm_fsm_rc_counter_ts2_1_reg_rx_count_cry[6]), + .S(plm_fsm_rc_counter_ts2_1_reg_rx_count_qxu[6]) + ); + XORCY plm_fsm_rc_counter_ts2_1_reg_rx_count_s_6_ ( + .CI(plm_fsm_rc_counter_ts2_1_reg_rx_count_cry[5]), + .LI(plm_fsm_rc_counter_ts2_1_reg_rx_count_qxu[6]), + .O(plm_fsm_rc_counter_ts2_1_reg_rx_count_s[6]) + ); + XORCY plm_fsm_rc_counter_ts2_1_reg_rx_count_s_7_ ( + .CI(plm_fsm_rc_counter_ts2_1_reg_rx_count_cry[6]), + .LI(plm_fsm_rc_counter_ts2_1_reg_rx_count_qxu[7]), + .O(plm_fsm_rc_counter_ts2_1_reg_rx_count_s[7]) + ); + MUXCY_L plm_fsm_rc_counter_ts2_1_reg_tx_count_cry_0_ ( + .CI(plm_fsm_rc_counter_ts2_1_N_60919_i_1969), + .DI(plm_fsm_rc_counter_ts2_1_VCC_1968), + .LO(plm_fsm_rc_counter_ts2_1_reg_tx_count_cry[0]), + .S(plm_fsm_rc_counter_ts2_1_reg_tx_count_qxu[0]) + ); + XORCY plm_fsm_rc_counter_ts2_1_reg_tx_count_s_0_ ( + .CI(plm_fsm_rc_counter_ts2_1_N_60919_i_1969), + .LI(plm_fsm_rc_counter_ts2_1_reg_tx_count_qxu[0]), + .O(plm_fsm_rc_counter_ts2_1_reg_tx_count_s[0]) + ); + MUXCY_L plm_fsm_rc_counter_ts2_1_reg_tx_count_cry_1_ ( + .CI(plm_fsm_rc_counter_ts2_1_reg_tx_count_cry[0]), + .DI(plm_fsm_rc_counter_ts2_1_VCC_1968), + .LO(plm_fsm_rc_counter_ts2_1_reg_tx_count_cry[1]), + .S(plm_fsm_rc_counter_ts2_1_reg_tx_count_qxu[1]) + ); + XORCY plm_fsm_rc_counter_ts2_1_reg_tx_count_s_1_ ( + .CI(plm_fsm_rc_counter_ts2_1_reg_tx_count_cry[0]), + .LI(plm_fsm_rc_counter_ts2_1_reg_tx_count_qxu[1]), + .O(plm_fsm_rc_counter_ts2_1_reg_tx_count_s[1]) + ); + MUXCY_L plm_fsm_rc_counter_ts2_1_reg_tx_count_cry_2_ ( + .CI(plm_fsm_rc_counter_ts2_1_reg_tx_count_cry[1]), + .DI(plm_fsm_rc_counter_ts2_1_VCC_1968), + .LO(plm_fsm_rc_counter_ts2_1_reg_tx_count_cry[2]), + .S(plm_fsm_rc_counter_ts2_1_reg_tx_count_qxu[2]) + ); + XORCY plm_fsm_rc_counter_ts2_1_reg_tx_count_s_2_ ( + .CI(plm_fsm_rc_counter_ts2_1_reg_tx_count_cry[1]), + .LI(plm_fsm_rc_counter_ts2_1_reg_tx_count_qxu[2]), + .O(plm_fsm_rc_counter_ts2_1_reg_tx_count_s[2]) + ); + MUXCY_L plm_fsm_rc_counter_ts2_1_reg_tx_count_cry_3_ ( + .CI(plm_fsm_rc_counter_ts2_1_reg_tx_count_cry[2]), + .DI(plm_fsm_rc_counter_ts2_1_VCC_1968), + .LO(plm_fsm_rc_counter_ts2_1_reg_tx_count_cry[3]), + .S(plm_fsm_rc_counter_ts2_1_reg_tx_count_qxu[3]) + ); + XORCY plm_fsm_rc_counter_ts2_1_reg_tx_count_s_3_ ( + .CI(plm_fsm_rc_counter_ts2_1_reg_tx_count_cry[2]), + .LI(plm_fsm_rc_counter_ts2_1_reg_tx_count_qxu[3]), + .O(plm_fsm_rc_counter_ts2_1_reg_tx_count_s[3]) + ); + MUXCY_L plm_fsm_rc_counter_ts2_1_reg_tx_count_cry_4_ ( + .CI(plm_fsm_rc_counter_ts2_1_reg_tx_count_cry[3]), + .DI(plm_fsm_rc_counter_ts2_1_VCC_1968), + .LO(plm_fsm_rc_counter_ts2_1_reg_tx_count_cry[4]), + .S(plm_fsm_rc_counter_ts2_1_reg_tx_count_qxu[4]) + ); + XORCY plm_fsm_rc_counter_ts2_1_reg_tx_count_s_4_ ( + .CI(plm_fsm_rc_counter_ts2_1_reg_tx_count_cry[3]), + .LI(plm_fsm_rc_counter_ts2_1_reg_tx_count_qxu[4]), + .O(plm_fsm_rc_counter_ts2_1_reg_tx_count_s[4]) + ); + MUXCY_L plm_fsm_rc_counter_ts2_1_reg_tx_count_cry_5_ ( + .CI(plm_fsm_rc_counter_ts2_1_reg_tx_count_cry[4]), + .DI(plm_fsm_rc_counter_ts2_1_VCC_1968), + .LO(plm_fsm_rc_counter_ts2_1_reg_tx_count_cry[5]), + .S(plm_fsm_rc_counter_ts2_1_reg_tx_count_qxu[5]) + ); + XORCY plm_fsm_rc_counter_ts2_1_reg_tx_count_s_5_ ( + .CI(plm_fsm_rc_counter_ts2_1_reg_tx_count_cry[4]), + .LI(plm_fsm_rc_counter_ts2_1_reg_tx_count_qxu[5]), + .O(plm_fsm_rc_counter_ts2_1_reg_tx_count_s[5]) + ); + MUXCY_L plm_fsm_rc_counter_ts2_1_reg_tx_count_cry_6_ ( + .CI(plm_fsm_rc_counter_ts2_1_reg_tx_count_cry[5]), + .DI(plm_fsm_rc_counter_ts2_1_VCC_1968), + .LO(plm_fsm_rc_counter_ts2_1_reg_tx_count_cry[6]), + .S(plm_fsm_rc_counter_ts2_1_reg_tx_count_qxu[6]) + ); + XORCY plm_fsm_rc_counter_ts2_1_reg_tx_count_s_6_ ( + .CI(plm_fsm_rc_counter_ts2_1_reg_tx_count_cry[5]), + .LI(plm_fsm_rc_counter_ts2_1_reg_tx_count_qxu[6]), + .O(plm_fsm_rc_counter_ts2_1_reg_tx_count_s[6]) + ); + XORCY plm_fsm_rc_counter_ts2_1_reg_tx_count_s_7_ ( + .CI(plm_fsm_rc_counter_ts2_1_reg_tx_count_cry[6]), + .LI(plm_fsm_rc_counter_ts2_1_reg_tx_count_qxu[7]), + .O(plm_fsm_rc_counter_ts2_1_reg_tx_count_s[7]) + ); + defparam plm_fsm_rc_counter_ts2_1_un1_enable_1_0_a2_i_o2_i_a3_0_a2.INIT = 4'h4; + LUT2 plm_fsm_rc_counter_ts2_1_un1_enable_1_0_a2_i_o2_i_a3_0_a2 ( + .I0(N_29556_i), + .I1(plm_fsm_rc_counter_ts2_1_reg_oneshot_1971), + .O(plm_fsm_rc_counter_ts2_1_un1_enable_1_0_a2_i_o2_i_a3_0_a2_1) + ); + defparam plm_fsm_rc_counter_ts2_1_loadable_tx_counter_un1_reg_tx_count_0_a2_0_a3_4.INIT = 16'h0001; + LUT4 plm_fsm_rc_counter_ts2_1_loadable_tx_counter_un1_reg_tx_count_0_a2_0_a3_4 ( + .I0(plm_fsm_rc_counter_ts2_1_reg_tx_count[0]), + .I1(plm_fsm_rc_counter_ts2_1_reg_tx_count[1]), + .I2(plm_fsm_rc_counter_ts2_1_reg_tx_count[2]), + .I3(plm_fsm_rc_counter_ts2_1_reg_tx_count[3]), + .O(plm_fsm_rc_counter_ts2_1_un1_reg_tx_count_0_a2_0_a3_4) + ); + defparam plm_fsm_rc_counter_ts2_1_loadable_tx_counter_un1_reg_tx_count_0_a2_0_a3_5.INIT = 16'h0001; + LUT4 plm_fsm_rc_counter_ts2_1_loadable_tx_counter_un1_reg_tx_count_0_a2_0_a3_5 ( + .I0(plm_fsm_rc_counter_ts2_1_reg_tx_count[4]), + .I1(plm_fsm_rc_counter_ts2_1_reg_tx_count[5]), + .I2(plm_fsm_rc_counter_ts2_1_reg_tx_count[6]), + .I3(plm_fsm_rc_counter_ts2_1_reg_tx_count[7]), + .O(plm_fsm_rc_counter_ts2_1_un1_reg_tx_count_0_a2_0_a3_5) + ); + defparam plm_fsm_rc_counter_ts2_1_loadable_rx_counter_un1_reg_rx_count_0_a2_0_a3_4.INIT = 16'h0001; + LUT4 plm_fsm_rc_counter_ts2_1_loadable_rx_counter_un1_reg_rx_count_0_a2_0_a3_4 ( + .I0(plm_fsm_rc_counter_ts2_1_reg_rx_count[0]), + .I1(plm_fsm_rc_counter_ts2_1_reg_rx_count[1]), + .I2(plm_fsm_rc_counter_ts2_1_reg_rx_count[2]), + .I3(plm_fsm_rc_counter_ts2_1_reg_rx_count[3]), + .O(plm_fsm_rc_counter_ts2_1_un1_reg_rx_count_0_a2_0_a3_4) + ); + defparam plm_fsm_rc_counter_ts2_1_loadable_rx_counter_un1_reg_rx_count_0_a2_0_a3_5.INIT = 16'h0001; + LUT4 plm_fsm_rc_counter_ts2_1_loadable_rx_counter_un1_reg_rx_count_0_a2_0_a3_5 ( + .I0(plm_fsm_rc_counter_ts2_1_reg_rx_count[4]), + .I1(plm_fsm_rc_counter_ts2_1_reg_rx_count[5]), + .I2(plm_fsm_rc_counter_ts2_1_reg_rx_count[6]), + .I3(plm_fsm_rc_counter_ts2_1_reg_rx_count[7]), + .O(plm_fsm_rc_counter_ts2_1_un1_reg_rx_count_0_a2_0_a3_5) + ); + defparam plm_fsm_rc_counter_ts2_1_un1_enable_1_0_a2_i_i_a3_0_a2.INIT = 4'h2; + LUT2 plm_fsm_rc_counter_ts2_1_un1_enable_1_0_a2_i_i_a3_0_a2 ( + .I0(plm_fsm_rc_counter_ts2_1_un1_enable_1_0_a2_i_o2_i_a3_0_a2_1), + .I1(plm_fsm_rc_counter_ts2_1_reg_tx_expired_1973), + .O(plm_fsm_rc_counter_ts2_1_un1_enable_1_0_a2_i_i_a3_0_a2_4) + ); + defparam plm_fsm_rc_counter_ts2_1_N_60930_i.INIT = 16'hFFEF; + LUT4 plm_fsm_rc_counter_ts2_1_N_60930_i ( + .I0(plm_reg_sym_sent_6_), + .I1(N_29556_i), + .I2(plm_fsm_rc_counter_ts2_1_reg_oneshot_1971), + .I3(plm_fsm_rc_counter_ts2_1_reg_tx_expired_1973), + .O(plm_fsm_rc_counter_ts2_1_N_60930_i_1970) + ); + defparam plm_fsm_rc_counter_ts2_1_N_60939_i.INIT = 8'hD5; + LUT3 plm_fsm_rc_counter_ts2_1_N_60939_i ( + .I0(plm_fsm_rc_counter_ts2_1_un1_enable_1_0_a2_i_o2_i_a3_0_a2_1), + .I1(plm_fsm_rc_counter_ts2_1_un1_reg_tx_count_0_a2_0_a3_4), + .I2(plm_fsm_rc_counter_ts2_1_un1_reg_tx_count_0_a2_0_a3_5), + .O(plm_fsm_rc_counter_ts2_1_N_60939_i_1972) + ); + defparam plm_fsm_rc_counter_ts2_1_loadable_rx_counter_N_60954_i.INIT = 8'hEA; + LUT3 plm_fsm_rc_counter_ts2_1_loadable_rx_counter_N_60954_i ( + .I0(N_29556_i), + .I1(plm_fsm_rc_counter_ts2_1_un1_reg_rx_count_0_a2_0_a3_4), + .I2(plm_fsm_rc_counter_ts2_1_un1_reg_rx_count_0_a2_0_a3_5), + .O(plm_fsm_rc_counter_ts2_1_N_60954_i) + ); + defparam plm_fsm_rc_counter_ts2_1_N_87191_i.INIT = 8'hAE; + LUT3_L plm_fsm_rc_counter_ts2_1_N_87191_i ( + .I0(N_29556_i), + .I1(plm_fsm_N_59112_1), + .I2(plm_fsm_rc_counter_ts2_1_reg_rx_expired_309), + .LO(plm_fsm_rc_counter_ts2_1_N_87191_i_1974) + ); + defparam plm_fsm_rc_counter_ts2_1_flagit_reg_expired_5_0_a2_i_i_a3_0_a2.INIT = 8'h40; + LUT3_L plm_fsm_rc_counter_ts2_1_flagit_reg_expired_5_0_a2_i_i_a3_0_a2 ( + .I0(N_29556_i_1), + .I1(plm_fsm_rc_counter_ts2_1_reg_rx_expired_309), + .I2(plm_fsm_rc_counter_ts2_1_reg_tx_expired_1973), + .LO(plm_fsm_rc_counter_ts2_1_reg_expired_5_0_a2_i_i_a3_0_a2_4) + ); + defparam plm_fsm_rc_counter_ts2_1_loadable_rx_counter_N_60934_i.INIT = 8'hFE; + LUT3 plm_fsm_rc_counter_ts2_1_loadable_rx_counter_N_60934_i ( + .I0(plm_fsm_rc_counter_ts2_1_reg_rx_expired_309), + .I1(N_29556_i), + .I2(plm_reg_ts2_1_0), + .O(plm_fsm_rc_counter_ts2_1_N_60934_i) + ); + defparam plm_fsm_rc_counter_ts2_1_oneshot_monitor_N_60955_i.INIT = 4'hE; + LUT2 plm_fsm_rc_counter_ts2_1_oneshot_monitor_N_60955_i ( + .I0(N_29556_i), + .I1(plm_reg_ts2_1_0), + .O(plm_fsm_rc_counter_ts2_1_N_60955_i) + ); + defparam plm_fsm_rc_counter_ts2_1_N_60919_i.INIT = 4'hB; + LUT2 plm_fsm_rc_counter_ts2_1_N_60919_i ( + .I0(plm_fsm_rc_counter_ts2_1_reg_tx_expired_1973), + .I1(plm_fsm_rc_counter_ts2_1_un1_enable_1_0_a2_i_o2_i_a3_0_a2_1), + .O(plm_fsm_rc_counter_ts2_1_N_60919_i_1969) + ); + FDCE plm_fsm_rc_counter_ts2_1_reg_tx_count_7_ ( + .CE(plm_fsm_rc_counter_ts2_1_N_60930_i_1970), + .C(mgt_clk), + .D(plm_fsm_rc_counter_ts2_1_reg_tx_count_s[7]), + .Q(plm_fsm_rc_counter_ts2_1_reg_tx_count[7]), + .CLR(plm_rst) + ); + FDCE plm_fsm_rc_counter_ts2_1_reg_tx_count_6_ ( + .CE(plm_fsm_rc_counter_ts2_1_N_60930_i_1970), + .C(mgt_clk), + .D(plm_fsm_rc_counter_ts2_1_reg_tx_count_s[6]), + .Q(plm_fsm_rc_counter_ts2_1_reg_tx_count[6]), + .CLR(plm_rst) + ); + FDCE plm_fsm_rc_counter_ts2_1_reg_tx_count_5_ ( + .CE(plm_fsm_rc_counter_ts2_1_N_60930_i_1970), + .C(mgt_clk), + .D(plm_fsm_rc_counter_ts2_1_reg_tx_count_s[5]), + .Q(plm_fsm_rc_counter_ts2_1_reg_tx_count[5]), + .CLR(plm_rst) + ); + FDPE plm_fsm_rc_counter_ts2_1_reg_tx_count_4_ ( + .PRE(plm_rst), + .CE(plm_fsm_rc_counter_ts2_1_N_60930_i_1970), + .C(mgt_clk), + .D(plm_fsm_rc_counter_ts2_1_reg_tx_count_s[4]), + .Q(plm_fsm_rc_counter_ts2_1_reg_tx_count[4]) + ); + FDCE plm_fsm_rc_counter_ts2_1_reg_tx_count_3_ ( + .CE(plm_fsm_rc_counter_ts2_1_N_60930_i_1970), + .C(mgt_clk), + .D(plm_fsm_rc_counter_ts2_1_reg_tx_count_s[3]), + .Q(plm_fsm_rc_counter_ts2_1_reg_tx_count[3]), + .CLR(plm_rst) + ); + FDCE plm_fsm_rc_counter_ts2_1_reg_tx_count_2_ ( + .CE(plm_fsm_rc_counter_ts2_1_N_60930_i_1970), + .C(mgt_clk), + .D(plm_fsm_rc_counter_ts2_1_reg_tx_count_s[2]), + .Q(plm_fsm_rc_counter_ts2_1_reg_tx_count[2]), + .CLR(plm_rst) + ); + FDCE plm_fsm_rc_counter_ts2_1_reg_tx_count_1_ ( + .CE(plm_fsm_rc_counter_ts2_1_N_60930_i_1970), + .C(mgt_clk), + .D(plm_fsm_rc_counter_ts2_1_reg_tx_count_s[1]), + .Q(plm_fsm_rc_counter_ts2_1_reg_tx_count[1]), + .CLR(plm_rst) + ); + FDCE plm_fsm_rc_counter_ts2_1_reg_tx_count_0_ ( + .CE(plm_fsm_rc_counter_ts2_1_N_60930_i_1970), + .C(mgt_clk), + .D(plm_fsm_rc_counter_ts2_1_reg_tx_count_s[0]), + .Q(plm_fsm_rc_counter_ts2_1_reg_tx_count[0]), + .CLR(plm_rst) + ); + FDCE plm_fsm_rc_counter_ts2_1_reg_rx_count_7_ ( + .CE(plm_fsm_rc_counter_ts2_1_N_60934_i), + .C(mgt_clk), + .D(plm_fsm_rc_counter_ts2_1_reg_rx_count_s[7]), + .Q(plm_fsm_rc_counter_ts2_1_reg_rx_count[7]), + .CLR(plm_rst) + ); + FDCE plm_fsm_rc_counter_ts2_1_reg_rx_count_6_ ( + .CE(plm_fsm_rc_counter_ts2_1_N_60934_i), + .C(mgt_clk), + .D(plm_fsm_rc_counter_ts2_1_reg_rx_count_s[6]), + .Q(plm_fsm_rc_counter_ts2_1_reg_rx_count[6]), + .CLR(plm_rst) + ); + FDCE plm_fsm_rc_counter_ts2_1_reg_rx_count_5_ ( + .CE(plm_fsm_rc_counter_ts2_1_N_60934_i), + .C(mgt_clk), + .D(plm_fsm_rc_counter_ts2_1_reg_rx_count_s[5]), + .Q(plm_fsm_rc_counter_ts2_1_reg_rx_count[5]), + .CLR(plm_rst) + ); + FDCE plm_fsm_rc_counter_ts2_1_reg_rx_count_4_ ( + .CE(plm_fsm_rc_counter_ts2_1_N_60934_i), + .C(mgt_clk), + .D(plm_fsm_rc_counter_ts2_1_reg_rx_count_s[4]), + .Q(plm_fsm_rc_counter_ts2_1_reg_rx_count[4]), + .CLR(plm_rst) + ); + FDPE plm_fsm_rc_counter_ts2_1_reg_rx_count_3_ ( + .PRE(plm_rst), + .CE(plm_fsm_rc_counter_ts2_1_N_60934_i), + .C(mgt_clk), + .D(plm_fsm_rc_counter_ts2_1_reg_rx_count_s[3]), + .Q(plm_fsm_rc_counter_ts2_1_reg_rx_count[3]) + ); + FDCE plm_fsm_rc_counter_ts2_1_reg_rx_count_2_ ( + .CE(plm_fsm_rc_counter_ts2_1_N_60934_i), + .C(mgt_clk), + .D(plm_fsm_rc_counter_ts2_1_reg_rx_count_s[2]), + .Q(plm_fsm_rc_counter_ts2_1_reg_rx_count[2]), + .CLR(plm_rst) + ); + FDCE plm_fsm_rc_counter_ts2_1_reg_rx_count_1_ ( + .CE(plm_fsm_rc_counter_ts2_1_N_60934_i), + .C(mgt_clk), + .D(plm_fsm_rc_counter_ts2_1_reg_rx_count_s[1]), + .Q(plm_fsm_rc_counter_ts2_1_reg_rx_count[1]), + .CLR(plm_rst) + ); + FDCE plm_fsm_rc_counter_ts2_1_reg_rx_count_0_ ( + .CE(plm_fsm_rc_counter_ts2_1_N_60934_i), + .C(mgt_clk), + .D(plm_fsm_rc_counter_ts2_1_reg_rx_count_s[0]), + .Q(plm_fsm_rc_counter_ts2_1_reg_rx_count[0]), + .CLR(plm_rst) + ); + FDC plm_fsm_rc_counter_ts2_1_reg_expired ( + .C(mgt_clk), + .D(plm_fsm_rc_counter_ts2_1_reg_expired_5_0_a2_i_i_a3_0_a2_4), + .Q(plm_fsm_rc_cntrout_ts2_1), + .CLR(plm_rst) + ); + FDCE plm_fsm_rc_counter_ts2_1_reg_oneshot ( + .CE(plm_fsm_rc_counter_ts2_1_N_60955_i), + .C(mgt_clk), + .D(N_29556_i_0), + .Q(plm_fsm_rc_counter_ts2_1_reg_oneshot_1971), + .CLR(plm_rst) + ); + FDCE plm_fsm_rc_counter_ts2_1_reg_rx_expired ( + .CE(plm_fsm_rc_counter_ts2_1_N_60954_i), + .C(mgt_clk), + .D(N_29556_i_0), + .Q(plm_fsm_rc_counter_ts2_1_reg_rx_expired_309), + .CLR(plm_rst) + ); + FDCE plm_fsm_rc_counter_ts2_1_reg_tx_expired ( + .CE(plm_fsm_rc_counter_ts2_1_N_60939_i_1972), + .C(mgt_clk), + .D(plm_fsm_rc_counter_ts2_1_un1_enable_1_0_a2_i_o2_i_a3_0_a2_1), + .Q(plm_fsm_rc_counter_ts2_1_reg_tx_expired_1973), + .CLR(plm_rst) + ); + defparam plm_fsm_rc_counter_ts2_1_reg_rx_count_qxu_0_0_.INIT = 4'h7; + LUT2_L plm_fsm_rc_counter_ts2_1_reg_rx_count_qxu_0_0_ ( + .I0(I_5336_i_0_i_a3_0_a2_19), + .I1(plm_fsm_rc_counter_ts2_1_reg_rx_count[0]), + .LO(plm_fsm_rc_counter_ts2_1_reg_rx_count_qxu[0]) + ); + defparam plm_fsm_rc_counter_ts2_1_reg_rx_count_qxu_0_1_.INIT = 4'h7; + LUT2_L plm_fsm_rc_counter_ts2_1_reg_rx_count_qxu_0_1_ ( + .I0(I_5336_i_0_i_a3_0_a2_19), + .I1(plm_fsm_rc_counter_ts2_1_reg_rx_count[1]), + .LO(plm_fsm_rc_counter_ts2_1_reg_rx_count_qxu[1]) + ); + defparam plm_fsm_rc_counter_ts2_1_reg_rx_count_qxu_0_2_.INIT = 4'h7; + LUT2_L plm_fsm_rc_counter_ts2_1_reg_rx_count_qxu_0_2_ ( + .I0(I_5336_i_0_i_a3_0_a2_19), + .I1(plm_fsm_rc_counter_ts2_1_reg_rx_count[2]), + .LO(plm_fsm_rc_counter_ts2_1_reg_rx_count_qxu[2]) + ); + defparam plm_fsm_rc_counter_ts2_1_reg_rx_count_qxu_0_3_.INIT = 8'h1B; + LUT3_L plm_fsm_rc_counter_ts2_1_reg_rx_count_qxu_0_3_ ( + .I0(I_5336_i_0_i_a3_0_a2_19), + .I1(plm_fsm_rc_counter_ts2_1_N_87191_i_1974), + .I2(plm_fsm_rc_counter_ts2_1_reg_rx_count[3]), + .LO(plm_fsm_rc_counter_ts2_1_reg_rx_count_qxu[3]) + ); + defparam plm_fsm_rc_counter_ts2_1_reg_rx_count_qxu_0_4_.INIT = 4'h7; + LUT2_L plm_fsm_rc_counter_ts2_1_reg_rx_count_qxu_0_4_ ( + .I0(I_5336_i_0_i_a3_0_a2_19), + .I1(plm_fsm_rc_counter_ts2_1_reg_rx_count[4]), + .LO(plm_fsm_rc_counter_ts2_1_reg_rx_count_qxu[4]) + ); + defparam plm_fsm_rc_counter_ts2_1_reg_rx_count_qxu_0_5_.INIT = 4'h7; + LUT2_L plm_fsm_rc_counter_ts2_1_reg_rx_count_qxu_0_5_ ( + .I0(I_5336_i_0_i_a3_0_a2_19), + .I1(plm_fsm_rc_counter_ts2_1_reg_rx_count[5]), + .LO(plm_fsm_rc_counter_ts2_1_reg_rx_count_qxu[5]) + ); + defparam plm_fsm_rc_counter_ts2_1_reg_rx_count_qxu_0_6_.INIT = 4'h7; + LUT2_L plm_fsm_rc_counter_ts2_1_reg_rx_count_qxu_0_6_ ( + .I0(I_5336_i_0_i_a3_0_a2_19), + .I1(plm_fsm_rc_counter_ts2_1_reg_rx_count[6]), + .LO(plm_fsm_rc_counter_ts2_1_reg_rx_count_qxu[6]) + ); + defparam plm_fsm_rc_counter_ts2_1_reg_rx_count_qxu_0_7_.INIT = 4'h7; + LUT2_L plm_fsm_rc_counter_ts2_1_reg_rx_count_qxu_0_7_ ( + .I0(I_5336_i_0_i_a3_0_a2_19), + .I1(plm_fsm_rc_counter_ts2_1_reg_rx_count[7]), + .LO(plm_fsm_rc_counter_ts2_1_reg_rx_count_qxu[7]) + ); + defparam plm_fsm_rc_counter_ts2_1_reg_tx_count_qxu_0_0_.INIT = 4'h7; + LUT2_L plm_fsm_rc_counter_ts2_1_reg_tx_count_qxu_0_0_ ( + .I0(plm_fsm_rc_counter_ts2_1_un1_enable_1_0_a2_i_i_a3_0_a2_4), + .I1(plm_fsm_rc_counter_ts2_1_reg_tx_count[0]), + .LO(plm_fsm_rc_counter_ts2_1_reg_tx_count_qxu[0]) + ); + defparam plm_fsm_rc_counter_ts2_1_reg_tx_count_qxu_0_1_.INIT = 4'h7; + LUT2_L plm_fsm_rc_counter_ts2_1_reg_tx_count_qxu_0_1_ ( + .I0(plm_fsm_rc_counter_ts2_1_un1_enable_1_0_a2_i_i_a3_0_a2_4), + .I1(plm_fsm_rc_counter_ts2_1_reg_tx_count[1]), + .LO(plm_fsm_rc_counter_ts2_1_reg_tx_count_qxu[1]) + ); + defparam plm_fsm_rc_counter_ts2_1_reg_tx_count_qxu_0_2_.INIT = 4'h7; + LUT2_L plm_fsm_rc_counter_ts2_1_reg_tx_count_qxu_0_2_ ( + .I0(plm_fsm_rc_counter_ts2_1_un1_enable_1_0_a2_i_i_a3_0_a2_4), + .I1(plm_fsm_rc_counter_ts2_1_reg_tx_count[2]), + .LO(plm_fsm_rc_counter_ts2_1_reg_tx_count_qxu[2]) + ); + defparam plm_fsm_rc_counter_ts2_1_reg_tx_count_qxu_0_3_.INIT = 4'h7; + LUT2_L plm_fsm_rc_counter_ts2_1_reg_tx_count_qxu_0_3_ ( + .I0(plm_fsm_rc_counter_ts2_1_un1_enable_1_0_a2_i_i_a3_0_a2_4), + .I1(plm_fsm_rc_counter_ts2_1_reg_tx_count[3]), + .LO(plm_fsm_rc_counter_ts2_1_reg_tx_count_qxu[3]) + ); + defparam plm_fsm_rc_counter_ts2_1_reg_tx_count_qxu_0_4_.INIT = 8'h4E; + LUT3_L plm_fsm_rc_counter_ts2_1_reg_tx_count_qxu_0_4_ ( + .I0(plm_fsm_rc_counter_ts2_1_un1_enable_1_0_a2_i_i_a3_0_a2_4), + .I1(plm_fsm_rc_counter_ts2_1_un1_enable_1_0_a2_i_o2_i_a3_0_a2_1), + .I2(plm_fsm_rc_counter_ts2_1_reg_tx_count[4]), + .LO(plm_fsm_rc_counter_ts2_1_reg_tx_count_qxu[4]) + ); + defparam plm_fsm_rc_counter_ts2_1_reg_tx_count_qxu_0_5_.INIT = 4'h7; + LUT2_L plm_fsm_rc_counter_ts2_1_reg_tx_count_qxu_0_5_ ( + .I0(plm_fsm_rc_counter_ts2_1_un1_enable_1_0_a2_i_i_a3_0_a2_4), + .I1(plm_fsm_rc_counter_ts2_1_reg_tx_count[5]), + .LO(plm_fsm_rc_counter_ts2_1_reg_tx_count_qxu[5]) + ); + defparam plm_fsm_rc_counter_ts2_1_reg_tx_count_qxu_0_6_.INIT = 4'h7; + LUT2_L plm_fsm_rc_counter_ts2_1_reg_tx_count_qxu_0_6_ ( + .I0(plm_fsm_rc_counter_ts2_1_un1_enable_1_0_a2_i_i_a3_0_a2_4), + .I1(plm_fsm_rc_counter_ts2_1_reg_tx_count[6]), + .LO(plm_fsm_rc_counter_ts2_1_reg_tx_count_qxu[6]) + ); + defparam plm_fsm_rc_counter_ts2_1_reg_tx_count_qxu_0_7_.INIT = 4'h7; + LUT2_L plm_fsm_rc_counter_ts2_1_reg_tx_count_qxu_0_7_ ( + .I0(plm_fsm_rc_counter_ts2_1_un1_enable_1_0_a2_i_i_a3_0_a2_4), + .I1(plm_fsm_rc_counter_ts2_1_reg_tx_count[7]), + .LO(plm_fsm_rc_counter_ts2_1_reg_tx_count_qxu[7]) + ); + VCC plm_fsm_rc_counter_ts2_2_VCC ( + .P(plm_fsm_rc_counter_ts2_2_VCC_1975) + ); + MUXCY_L plm_fsm_rc_counter_ts2_2_reg_rx_count_cry_0_ ( + .CI(N_60915_i_68), + .DI(plm_fsm_rc_counter_ts2_2_VCC_1975), + .LO(plm_fsm_rc_counter_ts2_2_reg_rx_count_cry[0]), + .S(plm_fsm_rc_counter_ts2_2_reg_rx_count_qxu[0]) + ); + XORCY plm_fsm_rc_counter_ts2_2_reg_rx_count_s_0_ ( + .CI(N_60915_i_68), + .LI(plm_fsm_rc_counter_ts2_2_reg_rx_count_qxu[0]), + .O(plm_fsm_rc_counter_ts2_2_reg_rx_count_s[0]) + ); + MUXCY_L plm_fsm_rc_counter_ts2_2_reg_rx_count_cry_1_ ( + .CI(plm_fsm_rc_counter_ts2_2_reg_rx_count_cry[0]), + .DI(plm_fsm_rc_counter_ts2_2_VCC_1975), + .LO(plm_fsm_rc_counter_ts2_2_reg_rx_count_cry[1]), + .S(plm_fsm_rc_counter_ts2_2_reg_rx_count_qxu[1]) + ); + XORCY plm_fsm_rc_counter_ts2_2_reg_rx_count_s_1_ ( + .CI(plm_fsm_rc_counter_ts2_2_reg_rx_count_cry[0]), + .LI(plm_fsm_rc_counter_ts2_2_reg_rx_count_qxu[1]), + .O(plm_fsm_rc_counter_ts2_2_reg_rx_count_s[1]) + ); + MUXCY_L plm_fsm_rc_counter_ts2_2_reg_rx_count_cry_2_ ( + .CI(plm_fsm_rc_counter_ts2_2_reg_rx_count_cry[1]), + .DI(plm_fsm_rc_counter_ts2_2_VCC_1975), + .LO(plm_fsm_rc_counter_ts2_2_reg_rx_count_cry[2]), + .S(plm_fsm_rc_counter_ts2_2_reg_rx_count_qxu[2]) + ); + XORCY plm_fsm_rc_counter_ts2_2_reg_rx_count_s_2_ ( + .CI(plm_fsm_rc_counter_ts2_2_reg_rx_count_cry[1]), + .LI(plm_fsm_rc_counter_ts2_2_reg_rx_count_qxu[2]), + .O(plm_fsm_rc_counter_ts2_2_reg_rx_count_s[2]) + ); + MUXCY_L plm_fsm_rc_counter_ts2_2_reg_rx_count_cry_3_ ( + .CI(plm_fsm_rc_counter_ts2_2_reg_rx_count_cry[2]), + .DI(plm_fsm_rc_counter_ts2_2_VCC_1975), + .LO(plm_fsm_rc_counter_ts2_2_reg_rx_count_cry[3]), + .S(plm_fsm_rc_counter_ts2_2_reg_rx_count_qxu[3]) + ); + XORCY plm_fsm_rc_counter_ts2_2_reg_rx_count_s_3_ ( + .CI(plm_fsm_rc_counter_ts2_2_reg_rx_count_cry[2]), + .LI(plm_fsm_rc_counter_ts2_2_reg_rx_count_qxu[3]), + .O(plm_fsm_rc_counter_ts2_2_reg_rx_count_s[3]) + ); + MUXCY_L plm_fsm_rc_counter_ts2_2_reg_rx_count_cry_4_ ( + .CI(plm_fsm_rc_counter_ts2_2_reg_rx_count_cry[3]), + .DI(plm_fsm_rc_counter_ts2_2_VCC_1975), + .LO(plm_fsm_rc_counter_ts2_2_reg_rx_count_cry[4]), + .S(plm_fsm_rc_counter_ts2_2_reg_rx_count_qxu[4]) + ); + XORCY plm_fsm_rc_counter_ts2_2_reg_rx_count_s_4_ ( + .CI(plm_fsm_rc_counter_ts2_2_reg_rx_count_cry[3]), + .LI(plm_fsm_rc_counter_ts2_2_reg_rx_count_qxu[4]), + .O(plm_fsm_rc_counter_ts2_2_reg_rx_count_s[4]) + ); + MUXCY_L plm_fsm_rc_counter_ts2_2_reg_rx_count_cry_5_ ( + .CI(plm_fsm_rc_counter_ts2_2_reg_rx_count_cry[4]), + .DI(plm_fsm_rc_counter_ts2_2_VCC_1975), + .LO(plm_fsm_rc_counter_ts2_2_reg_rx_count_cry[5]), + .S(plm_fsm_rc_counter_ts2_2_reg_rx_count_qxu[5]) + ); + XORCY plm_fsm_rc_counter_ts2_2_reg_rx_count_s_5_ ( + .CI(plm_fsm_rc_counter_ts2_2_reg_rx_count_cry[4]), + .LI(plm_fsm_rc_counter_ts2_2_reg_rx_count_qxu[5]), + .O(plm_fsm_rc_counter_ts2_2_reg_rx_count_s[5]) + ); + MUXCY_L plm_fsm_rc_counter_ts2_2_reg_rx_count_cry_6_ ( + .CI(plm_fsm_rc_counter_ts2_2_reg_rx_count_cry[5]), + .DI(plm_fsm_rc_counter_ts2_2_VCC_1975), + .LO(plm_fsm_rc_counter_ts2_2_reg_rx_count_cry[6]), + .S(plm_fsm_rc_counter_ts2_2_reg_rx_count_qxu[6]) + ); + XORCY plm_fsm_rc_counter_ts2_2_reg_rx_count_s_6_ ( + .CI(plm_fsm_rc_counter_ts2_2_reg_rx_count_cry[5]), + .LI(plm_fsm_rc_counter_ts2_2_reg_rx_count_qxu[6]), + .O(plm_fsm_rc_counter_ts2_2_reg_rx_count_s[6]) + ); + XORCY plm_fsm_rc_counter_ts2_2_reg_rx_count_s_7_ ( + .CI(plm_fsm_rc_counter_ts2_2_reg_rx_count_cry[6]), + .LI(plm_fsm_rc_counter_ts2_2_reg_rx_count_qxu[7]), + .O(plm_fsm_rc_counter_ts2_2_reg_rx_count_s[7]) + ); + MUXCY_L plm_fsm_rc_counter_ts2_2_reg_tx_count_cry_0_ ( + .CI(plm_fsm_rc_counter_ts2_2_N_60917_i_1976), + .DI(plm_fsm_rc_counter_ts2_2_VCC_1975), + .LO(plm_fsm_rc_counter_ts2_2_reg_tx_count_cry[0]), + .S(plm_fsm_rc_counter_ts2_2_reg_tx_count_qxu[0]) + ); + XORCY plm_fsm_rc_counter_ts2_2_reg_tx_count_s_0_ ( + .CI(plm_fsm_rc_counter_ts2_2_N_60917_i_1976), + .LI(plm_fsm_rc_counter_ts2_2_reg_tx_count_qxu[0]), + .O(plm_fsm_rc_counter_ts2_2_reg_tx_count_s[0]) + ); + MUXCY_L plm_fsm_rc_counter_ts2_2_reg_tx_count_cry_1_ ( + .CI(plm_fsm_rc_counter_ts2_2_reg_tx_count_cry[0]), + .DI(plm_fsm_rc_counter_ts2_2_VCC_1975), + .LO(plm_fsm_rc_counter_ts2_2_reg_tx_count_cry[1]), + .S(plm_fsm_rc_counter_ts2_2_reg_tx_count_qxu[1]) + ); + XORCY plm_fsm_rc_counter_ts2_2_reg_tx_count_s_1_ ( + .CI(plm_fsm_rc_counter_ts2_2_reg_tx_count_cry[0]), + .LI(plm_fsm_rc_counter_ts2_2_reg_tx_count_qxu[1]), + .O(plm_fsm_rc_counter_ts2_2_reg_tx_count_s[1]) + ); + MUXCY_L plm_fsm_rc_counter_ts2_2_reg_tx_count_cry_2_ ( + .CI(plm_fsm_rc_counter_ts2_2_reg_tx_count_cry[1]), + .DI(plm_fsm_rc_counter_ts2_2_VCC_1975), + .LO(plm_fsm_rc_counter_ts2_2_reg_tx_count_cry[2]), + .S(plm_fsm_rc_counter_ts2_2_reg_tx_count_qxu[2]) + ); + XORCY plm_fsm_rc_counter_ts2_2_reg_tx_count_s_2_ ( + .CI(plm_fsm_rc_counter_ts2_2_reg_tx_count_cry[1]), + .LI(plm_fsm_rc_counter_ts2_2_reg_tx_count_qxu[2]), + .O(plm_fsm_rc_counter_ts2_2_reg_tx_count_s[2]) + ); + MUXCY_L plm_fsm_rc_counter_ts2_2_reg_tx_count_cry_3_ ( + .CI(plm_fsm_rc_counter_ts2_2_reg_tx_count_cry[2]), + .DI(plm_fsm_rc_counter_ts2_2_VCC_1975), + .LO(plm_fsm_rc_counter_ts2_2_reg_tx_count_cry[3]), + .S(plm_fsm_rc_counter_ts2_2_reg_tx_count_qxu[3]) + ); + XORCY plm_fsm_rc_counter_ts2_2_reg_tx_count_s_3_ ( + .CI(plm_fsm_rc_counter_ts2_2_reg_tx_count_cry[2]), + .LI(plm_fsm_rc_counter_ts2_2_reg_tx_count_qxu[3]), + .O(plm_fsm_rc_counter_ts2_2_reg_tx_count_s[3]) + ); + MUXCY_L plm_fsm_rc_counter_ts2_2_reg_tx_count_cry_4_ ( + .CI(plm_fsm_rc_counter_ts2_2_reg_tx_count_cry[3]), + .DI(plm_fsm_rc_counter_ts2_2_VCC_1975), + .LO(plm_fsm_rc_counter_ts2_2_reg_tx_count_cry[4]), + .S(plm_fsm_rc_counter_ts2_2_reg_tx_count_qxu[4]) + ); + XORCY plm_fsm_rc_counter_ts2_2_reg_tx_count_s_4_ ( + .CI(plm_fsm_rc_counter_ts2_2_reg_tx_count_cry[3]), + .LI(plm_fsm_rc_counter_ts2_2_reg_tx_count_qxu[4]), + .O(plm_fsm_rc_counter_ts2_2_reg_tx_count_s[4]) + ); + MUXCY_L plm_fsm_rc_counter_ts2_2_reg_tx_count_cry_5_ ( + .CI(plm_fsm_rc_counter_ts2_2_reg_tx_count_cry[4]), + .DI(plm_fsm_rc_counter_ts2_2_VCC_1975), + .LO(plm_fsm_rc_counter_ts2_2_reg_tx_count_cry[5]), + .S(plm_fsm_rc_counter_ts2_2_reg_tx_count_qxu[5]) + ); + XORCY plm_fsm_rc_counter_ts2_2_reg_tx_count_s_5_ ( + .CI(plm_fsm_rc_counter_ts2_2_reg_tx_count_cry[4]), + .LI(plm_fsm_rc_counter_ts2_2_reg_tx_count_qxu[5]), + .O(plm_fsm_rc_counter_ts2_2_reg_tx_count_s[5]) + ); + MUXCY_L plm_fsm_rc_counter_ts2_2_reg_tx_count_cry_6_ ( + .CI(plm_fsm_rc_counter_ts2_2_reg_tx_count_cry[5]), + .DI(plm_fsm_rc_counter_ts2_2_VCC_1975), + .LO(plm_fsm_rc_counter_ts2_2_reg_tx_count_cry[6]), + .S(plm_fsm_rc_counter_ts2_2_reg_tx_count_qxu[6]) + ); + XORCY plm_fsm_rc_counter_ts2_2_reg_tx_count_s_6_ ( + .CI(plm_fsm_rc_counter_ts2_2_reg_tx_count_cry[5]), + .LI(plm_fsm_rc_counter_ts2_2_reg_tx_count_qxu[6]), + .O(plm_fsm_rc_counter_ts2_2_reg_tx_count_s[6]) + ); + XORCY plm_fsm_rc_counter_ts2_2_reg_tx_count_s_7_ ( + .CI(plm_fsm_rc_counter_ts2_2_reg_tx_count_cry[6]), + .LI(plm_fsm_rc_counter_ts2_2_reg_tx_count_qxu[7]), + .O(plm_fsm_rc_counter_ts2_2_reg_tx_count_s[7]) + ); + defparam plm_fsm_rc_counter_ts2_2_un1_enable_1_0_a2_i_o2_i_a3_0_a2.INIT = 4'h4; + LUT2 plm_fsm_rc_counter_ts2_2_un1_enable_1_0_a2_i_o2_i_a3_0_a2 ( + .I0(N_29556_i), + .I1(plm_fsm_rc_counter_ts2_2_reg_oneshot_1978), + .O(plm_fsm_rc_counter_ts2_2_un1_enable_1_0_a2_i_o2_i_a3_0_a2_0) + ); + defparam plm_fsm_rc_counter_ts2_2_oneshot_monitor_un1_enable_0_a2_i_i_a3_0_a2.INIT = 4'h1; + LUT2 plm_fsm_rc_counter_ts2_2_oneshot_monitor_un1_enable_0_a2_i_i_a3_0_a2 ( + .I0(plm_reg_ts2_1_1), + .I1(N_29556_i), + .O(plm_fsm_rc_counter_ts2_2_un1_enable_0_a2_i_i_a3_0_a2_0) + ); + defparam plm_fsm_rc_counter_ts2_2_loadable_tx_counter_un1_reg_tx_count_0_a2_0_a3_4.INIT = 16'h0001; + LUT4 plm_fsm_rc_counter_ts2_2_loadable_tx_counter_un1_reg_tx_count_0_a2_0_a3_4 ( + .I0(plm_fsm_rc_counter_ts2_2_reg_tx_count[0]), + .I1(plm_fsm_rc_counter_ts2_2_reg_tx_count[1]), + .I2(plm_fsm_rc_counter_ts2_2_reg_tx_count[2]), + .I3(plm_fsm_rc_counter_ts2_2_reg_tx_count[3]), + .O(plm_fsm_rc_counter_ts2_2_un1_reg_tx_count_0_a2_0_a3_4) + ); + defparam plm_fsm_rc_counter_ts2_2_loadable_tx_counter_un1_reg_tx_count_0_a2_0_a3_5.INIT = 16'h0001; + LUT4 plm_fsm_rc_counter_ts2_2_loadable_tx_counter_un1_reg_tx_count_0_a2_0_a3_5 ( + .I0(plm_fsm_rc_counter_ts2_2_reg_tx_count[4]), + .I1(plm_fsm_rc_counter_ts2_2_reg_tx_count[5]), + .I2(plm_fsm_rc_counter_ts2_2_reg_tx_count[6]), + .I3(plm_fsm_rc_counter_ts2_2_reg_tx_count[7]), + .O(plm_fsm_rc_counter_ts2_2_un1_reg_tx_count_0_a2_0_a3_5) + ); + defparam plm_fsm_rc_counter_ts2_2_loadable_rx_counter_un1_reg_rx_count_0_a2_0_a3_4.INIT = 16'h0001; + LUT4 plm_fsm_rc_counter_ts2_2_loadable_rx_counter_un1_reg_rx_count_0_a2_0_a3_4 ( + .I0(plm_fsm_rc_counter_ts2_2_reg_rx_count[0]), + .I1(plm_fsm_rc_counter_ts2_2_reg_rx_count[1]), + .I2(plm_fsm_rc_counter_ts2_2_reg_rx_count[2]), + .I3(plm_fsm_rc_counter_ts2_2_reg_rx_count[3]), + .O(plm_fsm_rc_counter_ts2_2_un1_reg_rx_count_0_a2_0_a3_4) + ); + defparam plm_fsm_rc_counter_ts2_2_loadable_rx_counter_un1_reg_rx_count_0_a2_0_a3_5.INIT = 16'h0001; + LUT4 plm_fsm_rc_counter_ts2_2_loadable_rx_counter_un1_reg_rx_count_0_a2_0_a3_5 ( + .I0(plm_fsm_rc_counter_ts2_2_reg_rx_count[4]), + .I1(plm_fsm_rc_counter_ts2_2_reg_rx_count[5]), + .I2(plm_fsm_rc_counter_ts2_2_reg_rx_count[6]), + .I3(plm_fsm_rc_counter_ts2_2_reg_rx_count[7]), + .O(plm_fsm_rc_counter_ts2_2_un1_reg_rx_count_0_a2_0_a3_5) + ); + defparam plm_fsm_rc_counter_ts2_2_un1_enable_1_0_a2_i_i_a3_0_a2.INIT = 4'h2; + LUT2 plm_fsm_rc_counter_ts2_2_un1_enable_1_0_a2_i_i_a3_0_a2 ( + .I0(plm_fsm_rc_counter_ts2_2_un1_enable_1_0_a2_i_o2_i_a3_0_a2_0), + .I1(plm_fsm_rc_counter_ts2_2_reg_tx_expired_1980), + .O(plm_fsm_rc_counter_ts2_2_un1_enable_1_0_a2_i_i_a3_0_a2_5) + ); + defparam plm_fsm_rc_counter_ts2_2_loadable_rx_counter_N_60933_i.INIT = 4'hD; + LUT2 plm_fsm_rc_counter_ts2_2_loadable_rx_counter_N_60933_i ( + .I0(plm_fsm_rc_counter_ts2_2_un1_enable_0_a2_i_i_a3_0_a2_0), + .I1(plm_fsm_rc_counter_ts2_2_reg_rx_expired_67), + .O(plm_fsm_rc_counter_ts2_2_N_60933_i) + ); + defparam plm_fsm_rc_counter_ts2_2_N_60931_i.INIT = 16'hFFEF; + LUT4 plm_fsm_rc_counter_ts2_2_N_60931_i ( + .I0(plm_reg_sym_sent_6_), + .I1(N_29556_i), + .I2(plm_fsm_rc_counter_ts2_2_reg_oneshot_1978), + .I3(plm_fsm_rc_counter_ts2_2_reg_tx_expired_1980), + .O(plm_fsm_rc_counter_ts2_2_N_60931_i_1977) + ); + defparam plm_fsm_rc_counter_ts2_2_N_60918_i.INIT = 8'hD5; + LUT3 plm_fsm_rc_counter_ts2_2_N_60918_i ( + .I0(plm_fsm_rc_counter_ts2_2_un1_enable_1_0_a2_i_o2_i_a3_0_a2_0), + .I1(plm_fsm_rc_counter_ts2_2_un1_reg_tx_count_0_a2_0_a3_4), + .I2(plm_fsm_rc_counter_ts2_2_un1_reg_tx_count_0_a2_0_a3_5), + .O(plm_fsm_rc_counter_ts2_2_N_60918_i_1979) + ); + defparam plm_fsm_rc_counter_ts2_2_loadable_rx_counter_N_60952_i.INIT = 8'hEA; + LUT3 plm_fsm_rc_counter_ts2_2_loadable_rx_counter_N_60952_i ( + .I0(N_29556_i), + .I1(plm_fsm_rc_counter_ts2_2_un1_reg_rx_count_0_a2_0_a3_4), + .I2(plm_fsm_rc_counter_ts2_2_un1_reg_rx_count_0_a2_0_a3_5), + .O(plm_fsm_rc_counter_ts2_2_N_60952_i) + ); + defparam plm_fsm_rc_counter_ts2_2_N_87234_i.INIT = 16'hCCCE; + LUT4 plm_fsm_rc_counter_ts2_2_N_87234_i ( + .I0(plm_reg_ts2_1_1), + .I1(N_29556_i), + .I2(N_56155_i), + .I3(plm_fsm_rc_counter_ts2_2_reg_rx_expired_67), + .O(plm_fsm_rc_counter_ts2_2_N_87234_i_1981) + ); + defparam plm_fsm_rc_counter_ts2_2_flagit_reg_expired_5_0_a2_i_i_a3_0_a2.INIT = 8'h40; + LUT3_L plm_fsm_rc_counter_ts2_2_flagit_reg_expired_5_0_a2_i_i_a3_0_a2 ( + .I0(N_29556_i_1), + .I1(plm_fsm_rc_counter_ts2_2_reg_rx_expired_67), + .I2(plm_fsm_rc_counter_ts2_2_reg_tx_expired_1980), + .LO(plm_fsm_rc_counter_ts2_2_reg_expired_5_0_a2_i_i_a3_0_a2_5) + ); + defparam plm_fsm_rc_counter_ts2_2_N_60917_i.INIT = 4'hB; + LUT2 plm_fsm_rc_counter_ts2_2_N_60917_i ( + .I0(plm_fsm_rc_counter_ts2_2_reg_tx_expired_1980), + .I1(plm_fsm_rc_counter_ts2_2_un1_enable_1_0_a2_i_o2_i_a3_0_a2_0), + .O(plm_fsm_rc_counter_ts2_2_N_60917_i_1976) + ); + FDCE plm_fsm_rc_counter_ts2_2_reg_tx_count_7_ ( + .CE(plm_fsm_rc_counter_ts2_2_N_60931_i_1977), + .C(mgt_clk), + .D(plm_fsm_rc_counter_ts2_2_reg_tx_count_s[7]), + .Q(plm_fsm_rc_counter_ts2_2_reg_tx_count[7]), + .CLR(plm_rst) + ); + FDCE plm_fsm_rc_counter_ts2_2_reg_tx_count_6_ ( + .CE(plm_fsm_rc_counter_ts2_2_N_60931_i_1977), + .C(mgt_clk), + .D(plm_fsm_rc_counter_ts2_2_reg_tx_count_s[6]), + .Q(plm_fsm_rc_counter_ts2_2_reg_tx_count[6]), + .CLR(plm_rst) + ); + FDCE plm_fsm_rc_counter_ts2_2_reg_tx_count_5_ ( + .CE(plm_fsm_rc_counter_ts2_2_N_60931_i_1977), + .C(mgt_clk), + .D(plm_fsm_rc_counter_ts2_2_reg_tx_count_s[5]), + .Q(plm_fsm_rc_counter_ts2_2_reg_tx_count[5]), + .CLR(plm_rst) + ); + FDPE plm_fsm_rc_counter_ts2_2_reg_tx_count_4_ ( + .PRE(plm_rst), + .CE(plm_fsm_rc_counter_ts2_2_N_60931_i_1977), + .C(mgt_clk), + .D(plm_fsm_rc_counter_ts2_2_reg_tx_count_s[4]), + .Q(plm_fsm_rc_counter_ts2_2_reg_tx_count[4]) + ); + FDCE plm_fsm_rc_counter_ts2_2_reg_tx_count_3_ ( + .CE(plm_fsm_rc_counter_ts2_2_N_60931_i_1977), + .C(mgt_clk), + .D(plm_fsm_rc_counter_ts2_2_reg_tx_count_s[3]), + .Q(plm_fsm_rc_counter_ts2_2_reg_tx_count[3]), + .CLR(plm_rst) + ); + FDCE plm_fsm_rc_counter_ts2_2_reg_tx_count_2_ ( + .CE(plm_fsm_rc_counter_ts2_2_N_60931_i_1977), + .C(mgt_clk), + .D(plm_fsm_rc_counter_ts2_2_reg_tx_count_s[2]), + .Q(plm_fsm_rc_counter_ts2_2_reg_tx_count[2]), + .CLR(plm_rst) + ); + FDCE plm_fsm_rc_counter_ts2_2_reg_tx_count_1_ ( + .CE(plm_fsm_rc_counter_ts2_2_N_60931_i_1977), + .C(mgt_clk), + .D(plm_fsm_rc_counter_ts2_2_reg_tx_count_s[1]), + .Q(plm_fsm_rc_counter_ts2_2_reg_tx_count[1]), + .CLR(plm_rst) + ); + FDCE plm_fsm_rc_counter_ts2_2_reg_tx_count_0_ ( + .CE(plm_fsm_rc_counter_ts2_2_N_60931_i_1977), + .C(mgt_clk), + .D(plm_fsm_rc_counter_ts2_2_reg_tx_count_s[0]), + .Q(plm_fsm_rc_counter_ts2_2_reg_tx_count[0]), + .CLR(plm_rst) + ); + FDCE plm_fsm_rc_counter_ts2_2_reg_rx_count_7_ ( + .CE(plm_fsm_rc_counter_ts2_2_N_60933_i), + .C(mgt_clk), + .D(plm_fsm_rc_counter_ts2_2_reg_rx_count_s[7]), + .Q(plm_fsm_rc_counter_ts2_2_reg_rx_count[7]), + .CLR(plm_rst) + ); + FDCE plm_fsm_rc_counter_ts2_2_reg_rx_count_6_ ( + .CE(plm_fsm_rc_counter_ts2_2_N_60933_i), + .C(mgt_clk), + .D(plm_fsm_rc_counter_ts2_2_reg_rx_count_s[6]), + .Q(plm_fsm_rc_counter_ts2_2_reg_rx_count[6]), + .CLR(plm_rst) + ); + FDCE plm_fsm_rc_counter_ts2_2_reg_rx_count_5_ ( + .CE(plm_fsm_rc_counter_ts2_2_N_60933_i), + .C(mgt_clk), + .D(plm_fsm_rc_counter_ts2_2_reg_rx_count_s[5]), + .Q(plm_fsm_rc_counter_ts2_2_reg_rx_count[5]), + .CLR(plm_rst) + ); + FDCE plm_fsm_rc_counter_ts2_2_reg_rx_count_4_ ( + .CE(plm_fsm_rc_counter_ts2_2_N_60933_i), + .C(mgt_clk), + .D(plm_fsm_rc_counter_ts2_2_reg_rx_count_s[4]), + .Q(plm_fsm_rc_counter_ts2_2_reg_rx_count[4]), + .CLR(plm_rst) + ); + FDPE plm_fsm_rc_counter_ts2_2_reg_rx_count_3_ ( + .PRE(plm_rst), + .CE(plm_fsm_rc_counter_ts2_2_N_60933_i), + .C(mgt_clk), + .D(plm_fsm_rc_counter_ts2_2_reg_rx_count_s[3]), + .Q(plm_fsm_rc_counter_ts2_2_reg_rx_count[3]) + ); + FDCE plm_fsm_rc_counter_ts2_2_reg_rx_count_2_ ( + .CE(plm_fsm_rc_counter_ts2_2_N_60933_i), + .C(mgt_clk), + .D(plm_fsm_rc_counter_ts2_2_reg_rx_count_s[2]), + .Q(plm_fsm_rc_counter_ts2_2_reg_rx_count[2]), + .CLR(plm_rst) + ); + FDCE plm_fsm_rc_counter_ts2_2_reg_rx_count_1_ ( + .CE(plm_fsm_rc_counter_ts2_2_N_60933_i), + .C(mgt_clk), + .D(plm_fsm_rc_counter_ts2_2_reg_rx_count_s[1]), + .Q(plm_fsm_rc_counter_ts2_2_reg_rx_count[1]), + .CLR(plm_rst) + ); + FDCE plm_fsm_rc_counter_ts2_2_reg_rx_count_0_ ( + .CE(plm_fsm_rc_counter_ts2_2_N_60933_i), + .C(mgt_clk), + .D(plm_fsm_rc_counter_ts2_2_reg_rx_count_s[0]), + .Q(plm_fsm_rc_counter_ts2_2_reg_rx_count[0]), + .CLR(plm_rst) + ); + FDC plm_fsm_rc_counter_ts2_2_reg_expired ( + .C(mgt_clk), + .D(plm_fsm_rc_counter_ts2_2_reg_expired_5_0_a2_i_i_a3_0_a2_5), + .Q(plm_fsm_rc_cntrout_ts2_2), + .CLR(plm_rst) + ); + FDCE plm_fsm_rc_counter_ts2_2_reg_oneshot ( + .CE(plm_fsm_rc_counter_ts2_2_N_60953_i), + .C(mgt_clk), + .D(N_29556_i_0), + .Q(plm_fsm_rc_counter_ts2_2_reg_oneshot_1978), + .CLR(plm_rst) + ); + FDCE plm_fsm_rc_counter_ts2_2_reg_rx_expired ( + .CE(plm_fsm_rc_counter_ts2_2_N_60952_i), + .C(mgt_clk), + .D(N_29556_i_0), + .Q(plm_fsm_rc_counter_ts2_2_reg_rx_expired_67), + .CLR(plm_rst) + ); + FDCE plm_fsm_rc_counter_ts2_2_reg_tx_expired ( + .CE(plm_fsm_rc_counter_ts2_2_N_60918_i_1979), + .C(mgt_clk), + .D(plm_fsm_rc_counter_ts2_2_un1_enable_1_0_a2_i_o2_i_a3_0_a2_0), + .Q(plm_fsm_rc_counter_ts2_2_reg_tx_expired_1980), + .CLR(plm_rst) + ); + INV plm_fsm_rc_counter_ts2_2_oneshot_monitor_N_60953_i ( + .I(plm_fsm_rc_counter_ts2_2_un1_enable_0_a2_i_i_a3_0_a2_0), + .O(plm_fsm_rc_counter_ts2_2_N_60953_i) + ); + defparam plm_fsm_rc_counter_ts2_2_reg_rx_count_qxu_0_0_.INIT = 4'h7; + LUT2_L plm_fsm_rc_counter_ts2_2_reg_rx_count_qxu_0_0_ ( + .I0(I_5354_0_a2_i_i_a3_0_a2_307), + .I1(plm_fsm_rc_counter_ts2_2_reg_rx_count[0]), + .LO(plm_fsm_rc_counter_ts2_2_reg_rx_count_qxu[0]) + ); + defparam plm_fsm_rc_counter_ts2_2_reg_rx_count_qxu_0_1_.INIT = 4'h7; + LUT2_L plm_fsm_rc_counter_ts2_2_reg_rx_count_qxu_0_1_ ( + .I0(I_5354_0_a2_i_i_a3_0_a2_307), + .I1(plm_fsm_rc_counter_ts2_2_reg_rx_count[1]), + .LO(plm_fsm_rc_counter_ts2_2_reg_rx_count_qxu[1]) + ); + defparam plm_fsm_rc_counter_ts2_2_reg_rx_count_qxu_0_2_.INIT = 4'h7; + LUT2_L plm_fsm_rc_counter_ts2_2_reg_rx_count_qxu_0_2_ ( + .I0(I_5354_0_a2_i_i_a3_0_a2_307), + .I1(plm_fsm_rc_counter_ts2_2_reg_rx_count[2]), + .LO(plm_fsm_rc_counter_ts2_2_reg_rx_count_qxu[2]) + ); + defparam plm_fsm_rc_counter_ts2_2_reg_rx_count_qxu_0_3_.INIT = 8'h1B; + LUT3_L plm_fsm_rc_counter_ts2_2_reg_rx_count_qxu_0_3_ ( + .I0(I_5354_0_a2_i_i_a3_0_a2_307), + .I1(plm_fsm_rc_counter_ts2_2_N_87234_i_1981), + .I2(plm_fsm_rc_counter_ts2_2_reg_rx_count[3]), + .LO(plm_fsm_rc_counter_ts2_2_reg_rx_count_qxu[3]) + ); + defparam plm_fsm_rc_counter_ts2_2_reg_rx_count_qxu_0_4_.INIT = 4'h7; + LUT2_L plm_fsm_rc_counter_ts2_2_reg_rx_count_qxu_0_4_ ( + .I0(I_5354_0_a2_i_i_a3_0_a2_307), + .I1(plm_fsm_rc_counter_ts2_2_reg_rx_count[4]), + .LO(plm_fsm_rc_counter_ts2_2_reg_rx_count_qxu[4]) + ); + defparam plm_fsm_rc_counter_ts2_2_reg_rx_count_qxu_0_5_.INIT = 4'h7; + LUT2_L plm_fsm_rc_counter_ts2_2_reg_rx_count_qxu_0_5_ ( + .I0(I_5354_0_a2_i_i_a3_0_a2_307), + .I1(plm_fsm_rc_counter_ts2_2_reg_rx_count[5]), + .LO(plm_fsm_rc_counter_ts2_2_reg_rx_count_qxu[5]) + ); + defparam plm_fsm_rc_counter_ts2_2_reg_rx_count_qxu_0_6_.INIT = 4'h7; + LUT2_L plm_fsm_rc_counter_ts2_2_reg_rx_count_qxu_0_6_ ( + .I0(I_5354_0_a2_i_i_a3_0_a2_307), + .I1(plm_fsm_rc_counter_ts2_2_reg_rx_count[6]), + .LO(plm_fsm_rc_counter_ts2_2_reg_rx_count_qxu[6]) + ); + defparam plm_fsm_rc_counter_ts2_2_reg_rx_count_qxu_0_7_.INIT = 4'h7; + LUT2_L plm_fsm_rc_counter_ts2_2_reg_rx_count_qxu_0_7_ ( + .I0(I_5354_0_a2_i_i_a3_0_a2_307), + .I1(plm_fsm_rc_counter_ts2_2_reg_rx_count[7]), + .LO(plm_fsm_rc_counter_ts2_2_reg_rx_count_qxu[7]) + ); + defparam plm_fsm_rc_counter_ts2_2_reg_tx_count_qxu_0_0_.INIT = 4'h7; + LUT2_L plm_fsm_rc_counter_ts2_2_reg_tx_count_qxu_0_0_ ( + .I0(plm_fsm_rc_counter_ts2_2_un1_enable_1_0_a2_i_i_a3_0_a2_5), + .I1(plm_fsm_rc_counter_ts2_2_reg_tx_count[0]), + .LO(plm_fsm_rc_counter_ts2_2_reg_tx_count_qxu[0]) + ); + defparam plm_fsm_rc_counter_ts2_2_reg_tx_count_qxu_0_1_.INIT = 4'h7; + LUT2_L plm_fsm_rc_counter_ts2_2_reg_tx_count_qxu_0_1_ ( + .I0(plm_fsm_rc_counter_ts2_2_un1_enable_1_0_a2_i_i_a3_0_a2_5), + .I1(plm_fsm_rc_counter_ts2_2_reg_tx_count[1]), + .LO(plm_fsm_rc_counter_ts2_2_reg_tx_count_qxu[1]) + ); + defparam plm_fsm_rc_counter_ts2_2_reg_tx_count_qxu_0_2_.INIT = 4'h7; + LUT2_L plm_fsm_rc_counter_ts2_2_reg_tx_count_qxu_0_2_ ( + .I0(plm_fsm_rc_counter_ts2_2_un1_enable_1_0_a2_i_i_a3_0_a2_5), + .I1(plm_fsm_rc_counter_ts2_2_reg_tx_count[2]), + .LO(plm_fsm_rc_counter_ts2_2_reg_tx_count_qxu[2]) + ); + defparam plm_fsm_rc_counter_ts2_2_reg_tx_count_qxu_0_3_.INIT = 4'h7; + LUT2_L plm_fsm_rc_counter_ts2_2_reg_tx_count_qxu_0_3_ ( + .I0(plm_fsm_rc_counter_ts2_2_un1_enable_1_0_a2_i_i_a3_0_a2_5), + .I1(plm_fsm_rc_counter_ts2_2_reg_tx_count[3]), + .LO(plm_fsm_rc_counter_ts2_2_reg_tx_count_qxu[3]) + ); + defparam plm_fsm_rc_counter_ts2_2_reg_tx_count_qxu_0_4_.INIT = 8'h4E; + LUT3_L plm_fsm_rc_counter_ts2_2_reg_tx_count_qxu_0_4_ ( + .I0(plm_fsm_rc_counter_ts2_2_un1_enable_1_0_a2_i_i_a3_0_a2_5), + .I1(plm_fsm_rc_counter_ts2_2_un1_enable_1_0_a2_i_o2_i_a3_0_a2_0), + .I2(plm_fsm_rc_counter_ts2_2_reg_tx_count[4]), + .LO(plm_fsm_rc_counter_ts2_2_reg_tx_count_qxu[4]) + ); + defparam plm_fsm_rc_counter_ts2_2_reg_tx_count_qxu_0_5_.INIT = 4'h7; + LUT2_L plm_fsm_rc_counter_ts2_2_reg_tx_count_qxu_0_5_ ( + .I0(plm_fsm_rc_counter_ts2_2_un1_enable_1_0_a2_i_i_a3_0_a2_5), + .I1(plm_fsm_rc_counter_ts2_2_reg_tx_count[5]), + .LO(plm_fsm_rc_counter_ts2_2_reg_tx_count_qxu[5]) + ); + defparam plm_fsm_rc_counter_ts2_2_reg_tx_count_qxu_0_6_.INIT = 4'h7; + LUT2_L plm_fsm_rc_counter_ts2_2_reg_tx_count_qxu_0_6_ ( + .I0(plm_fsm_rc_counter_ts2_2_un1_enable_1_0_a2_i_i_a3_0_a2_5), + .I1(plm_fsm_rc_counter_ts2_2_reg_tx_count[6]), + .LO(plm_fsm_rc_counter_ts2_2_reg_tx_count_qxu[6]) + ); + defparam plm_fsm_rc_counter_ts2_2_reg_tx_count_qxu_0_7_.INIT = 4'h7; + LUT2_L plm_fsm_rc_counter_ts2_2_reg_tx_count_qxu_0_7_ ( + .I0(plm_fsm_rc_counter_ts2_2_un1_enable_1_0_a2_i_i_a3_0_a2_5), + .I1(plm_fsm_rc_counter_ts2_2_reg_tx_count[7]), + .LO(plm_fsm_rc_counter_ts2_2_reg_tx_count_qxu[7]) + ); + VCC plm_fsm_rc_counter_ts2_3_VCC ( + .P(plm_fsm_rc_counter_ts2_3_VCC_1982) + ); + MUXCY_L plm_fsm_rc_counter_ts2_3_reg_rx_count_cry_0_ ( + .CI(N_22826_i_28), + .DI(plm_fsm_rc_counter_ts2_3_VCC_1982), + .LO(plm_fsm_rc_counter_ts2_3_reg_rx_count_cry[0]), + .S(plm_fsm_rc_counter_ts2_3_reg_rx_count_qxu[0]) + ); + XORCY plm_fsm_rc_counter_ts2_3_reg_rx_count_s_0_ ( + .CI(N_22826_i_28), + .LI(plm_fsm_rc_counter_ts2_3_reg_rx_count_qxu[0]), + .O(plm_fsm_rc_counter_ts2_3_reg_rx_count_s[0]) + ); + MUXCY_L plm_fsm_rc_counter_ts2_3_reg_rx_count_cry_1_ ( + .CI(plm_fsm_rc_counter_ts2_3_reg_rx_count_cry[0]), + .DI(plm_fsm_rc_counter_ts2_3_VCC_1982), + .LO(plm_fsm_rc_counter_ts2_3_reg_rx_count_cry[1]), + .S(plm_fsm_rc_counter_ts2_3_reg_rx_count_qxu[1]) + ); + XORCY plm_fsm_rc_counter_ts2_3_reg_rx_count_s_1_ ( + .CI(plm_fsm_rc_counter_ts2_3_reg_rx_count_cry[0]), + .LI(plm_fsm_rc_counter_ts2_3_reg_rx_count_qxu[1]), + .O(plm_fsm_rc_counter_ts2_3_reg_rx_count_s[1]) + ); + MUXCY_L plm_fsm_rc_counter_ts2_3_reg_rx_count_cry_2_ ( + .CI(plm_fsm_rc_counter_ts2_3_reg_rx_count_cry[1]), + .DI(plm_fsm_rc_counter_ts2_3_VCC_1982), + .LO(plm_fsm_rc_counter_ts2_3_reg_rx_count_cry[2]), + .S(plm_fsm_rc_counter_ts2_3_reg_rx_count_qxu[2]) + ); + XORCY plm_fsm_rc_counter_ts2_3_reg_rx_count_s_2_ ( + .CI(plm_fsm_rc_counter_ts2_3_reg_rx_count_cry[1]), + .LI(plm_fsm_rc_counter_ts2_3_reg_rx_count_qxu[2]), + .O(plm_fsm_rc_counter_ts2_3_reg_rx_count_s[2]) + ); + MUXCY_L plm_fsm_rc_counter_ts2_3_reg_rx_count_cry_3_ ( + .CI(plm_fsm_rc_counter_ts2_3_reg_rx_count_cry[2]), + .DI(plm_fsm_rc_counter_ts2_3_VCC_1982), + .LO(plm_fsm_rc_counter_ts2_3_reg_rx_count_cry[3]), + .S(plm_fsm_rc_counter_ts2_3_reg_rx_count_qxu[3]) + ); + XORCY plm_fsm_rc_counter_ts2_3_reg_rx_count_s_3_ ( + .CI(plm_fsm_rc_counter_ts2_3_reg_rx_count_cry[2]), + .LI(plm_fsm_rc_counter_ts2_3_reg_rx_count_qxu[3]), + .O(plm_fsm_rc_counter_ts2_3_reg_rx_count_s[3]) + ); + MUXCY_L plm_fsm_rc_counter_ts2_3_reg_rx_count_cry_4_ ( + .CI(plm_fsm_rc_counter_ts2_3_reg_rx_count_cry[3]), + .DI(plm_fsm_rc_counter_ts2_3_VCC_1982), + .LO(plm_fsm_rc_counter_ts2_3_reg_rx_count_cry[4]), + .S(plm_fsm_rc_counter_ts2_3_reg_rx_count_qxu[4]) + ); + XORCY plm_fsm_rc_counter_ts2_3_reg_rx_count_s_4_ ( + .CI(plm_fsm_rc_counter_ts2_3_reg_rx_count_cry[3]), + .LI(plm_fsm_rc_counter_ts2_3_reg_rx_count_qxu[4]), + .O(plm_fsm_rc_counter_ts2_3_reg_rx_count_s[4]) + ); + MUXCY_L plm_fsm_rc_counter_ts2_3_reg_rx_count_cry_5_ ( + .CI(plm_fsm_rc_counter_ts2_3_reg_rx_count_cry[4]), + .DI(plm_fsm_rc_counter_ts2_3_VCC_1982), + .LO(plm_fsm_rc_counter_ts2_3_reg_rx_count_cry[5]), + .S(plm_fsm_rc_counter_ts2_3_reg_rx_count_qxu[5]) + ); + XORCY plm_fsm_rc_counter_ts2_3_reg_rx_count_s_5_ ( + .CI(plm_fsm_rc_counter_ts2_3_reg_rx_count_cry[4]), + .LI(plm_fsm_rc_counter_ts2_3_reg_rx_count_qxu[5]), + .O(plm_fsm_rc_counter_ts2_3_reg_rx_count_s[5]) + ); + MUXCY_L plm_fsm_rc_counter_ts2_3_reg_rx_count_cry_6_ ( + .CI(plm_fsm_rc_counter_ts2_3_reg_rx_count_cry[5]), + .DI(plm_fsm_rc_counter_ts2_3_VCC_1982), + .LO(plm_fsm_rc_counter_ts2_3_reg_rx_count_cry[6]), + .S(plm_fsm_rc_counter_ts2_3_reg_rx_count_qxu[6]) + ); + XORCY plm_fsm_rc_counter_ts2_3_reg_rx_count_s_6_ ( + .CI(plm_fsm_rc_counter_ts2_3_reg_rx_count_cry[5]), + .LI(plm_fsm_rc_counter_ts2_3_reg_rx_count_qxu[6]), + .O(plm_fsm_rc_counter_ts2_3_reg_rx_count_s[6]) + ); + XORCY plm_fsm_rc_counter_ts2_3_reg_rx_count_s_7_ ( + .CI(plm_fsm_rc_counter_ts2_3_reg_rx_count_cry[6]), + .LI(plm_fsm_rc_counter_ts2_3_reg_rx_count_qxu[7]), + .O(plm_fsm_rc_counter_ts2_3_reg_rx_count_s[7]) + ); + MUXCY_L plm_fsm_rc_counter_ts2_3_reg_tx_count_cry_0_ ( + .CI(plm_fsm_rc_counter_ts2_3_N_60916_i_1983), + .DI(plm_fsm_rc_counter_ts2_3_VCC_1982), + .LO(plm_fsm_rc_counter_ts2_3_reg_tx_count_cry[0]), + .S(plm_fsm_rc_counter_ts2_3_reg_tx_count_qxu[0]) + ); + XORCY plm_fsm_rc_counter_ts2_3_reg_tx_count_s_0_ ( + .CI(plm_fsm_rc_counter_ts2_3_N_60916_i_1983), + .LI(plm_fsm_rc_counter_ts2_3_reg_tx_count_qxu[0]), + .O(plm_fsm_rc_counter_ts2_3_reg_tx_count_s[0]) + ); + MUXCY_L plm_fsm_rc_counter_ts2_3_reg_tx_count_cry_1_ ( + .CI(plm_fsm_rc_counter_ts2_3_reg_tx_count_cry[0]), + .DI(plm_fsm_rc_counter_ts2_3_VCC_1982), + .LO(plm_fsm_rc_counter_ts2_3_reg_tx_count_cry[1]), + .S(plm_fsm_rc_counter_ts2_3_reg_tx_count_qxu[1]) + ); + XORCY plm_fsm_rc_counter_ts2_3_reg_tx_count_s_1_ ( + .CI(plm_fsm_rc_counter_ts2_3_reg_tx_count_cry[0]), + .LI(plm_fsm_rc_counter_ts2_3_reg_tx_count_qxu[1]), + .O(plm_fsm_rc_counter_ts2_3_reg_tx_count_s[1]) + ); + MUXCY_L plm_fsm_rc_counter_ts2_3_reg_tx_count_cry_2_ ( + .CI(plm_fsm_rc_counter_ts2_3_reg_tx_count_cry[1]), + .DI(plm_fsm_rc_counter_ts2_3_VCC_1982), + .LO(plm_fsm_rc_counter_ts2_3_reg_tx_count_cry[2]), + .S(plm_fsm_rc_counter_ts2_3_reg_tx_count_qxu[2]) + ); + XORCY plm_fsm_rc_counter_ts2_3_reg_tx_count_s_2_ ( + .CI(plm_fsm_rc_counter_ts2_3_reg_tx_count_cry[1]), + .LI(plm_fsm_rc_counter_ts2_3_reg_tx_count_qxu[2]), + .O(plm_fsm_rc_counter_ts2_3_reg_tx_count_s[2]) + ); + MUXCY_L plm_fsm_rc_counter_ts2_3_reg_tx_count_cry_3_ ( + .CI(plm_fsm_rc_counter_ts2_3_reg_tx_count_cry[2]), + .DI(plm_fsm_rc_counter_ts2_3_VCC_1982), + .LO(plm_fsm_rc_counter_ts2_3_reg_tx_count_cry[3]), + .S(plm_fsm_rc_counter_ts2_3_reg_tx_count_qxu[3]) + ); + XORCY plm_fsm_rc_counter_ts2_3_reg_tx_count_s_3_ ( + .CI(plm_fsm_rc_counter_ts2_3_reg_tx_count_cry[2]), + .LI(plm_fsm_rc_counter_ts2_3_reg_tx_count_qxu[3]), + .O(plm_fsm_rc_counter_ts2_3_reg_tx_count_s[3]) + ); + MUXCY_L plm_fsm_rc_counter_ts2_3_reg_tx_count_cry_4_ ( + .CI(plm_fsm_rc_counter_ts2_3_reg_tx_count_cry[3]), + .DI(plm_fsm_rc_counter_ts2_3_VCC_1982), + .LO(plm_fsm_rc_counter_ts2_3_reg_tx_count_cry[4]), + .S(plm_fsm_rc_counter_ts2_3_reg_tx_count_qxu[4]) + ); + XORCY plm_fsm_rc_counter_ts2_3_reg_tx_count_s_4_ ( + .CI(plm_fsm_rc_counter_ts2_3_reg_tx_count_cry[3]), + .LI(plm_fsm_rc_counter_ts2_3_reg_tx_count_qxu[4]), + .O(plm_fsm_rc_counter_ts2_3_reg_tx_count_s[4]) + ); + MUXCY_L plm_fsm_rc_counter_ts2_3_reg_tx_count_cry_5_ ( + .CI(plm_fsm_rc_counter_ts2_3_reg_tx_count_cry[4]), + .DI(plm_fsm_rc_counter_ts2_3_VCC_1982), + .LO(plm_fsm_rc_counter_ts2_3_reg_tx_count_cry[5]), + .S(plm_fsm_rc_counter_ts2_3_reg_tx_count_qxu[5]) + ); + XORCY plm_fsm_rc_counter_ts2_3_reg_tx_count_s_5_ ( + .CI(plm_fsm_rc_counter_ts2_3_reg_tx_count_cry[4]), + .LI(plm_fsm_rc_counter_ts2_3_reg_tx_count_qxu[5]), + .O(plm_fsm_rc_counter_ts2_3_reg_tx_count_s[5]) + ); + MUXCY_L plm_fsm_rc_counter_ts2_3_reg_tx_count_cry_6_ ( + .CI(plm_fsm_rc_counter_ts2_3_reg_tx_count_cry[5]), + .DI(plm_fsm_rc_counter_ts2_3_VCC_1982), + .LO(plm_fsm_rc_counter_ts2_3_reg_tx_count_cry[6]), + .S(plm_fsm_rc_counter_ts2_3_reg_tx_count_qxu[6]) + ); + XORCY plm_fsm_rc_counter_ts2_3_reg_tx_count_s_6_ ( + .CI(plm_fsm_rc_counter_ts2_3_reg_tx_count_cry[5]), + .LI(plm_fsm_rc_counter_ts2_3_reg_tx_count_qxu[6]), + .O(plm_fsm_rc_counter_ts2_3_reg_tx_count_s[6]) + ); + XORCY plm_fsm_rc_counter_ts2_3_reg_tx_count_s_7_ ( + .CI(plm_fsm_rc_counter_ts2_3_reg_tx_count_cry[6]), + .LI(plm_fsm_rc_counter_ts2_3_reg_tx_count_qxu[7]), + .O(plm_fsm_rc_counter_ts2_3_reg_tx_count_s[7]) + ); + defparam plm_fsm_rc_counter_ts2_3_un1_enable_1_0_a2_i_o2_i_a3_0_a2.INIT = 4'h4; + LUT2 plm_fsm_rc_counter_ts2_3_un1_enable_1_0_a2_i_o2_i_a3_0_a2 ( + .I0(N_29556_i), + .I1(plm_fsm_rc_counter_ts2_3_reg_oneshot_1985), + .O(plm_fsm_rc_counter_ts2_3_un1_enable_1_0_a2_i_o2_i_a3_0_a2_1989) + ); + defparam plm_fsm_rc_counter_ts2_3_loadable_tx_counter_un1_reg_tx_count_0_a2_0_a3_4.INIT = 16'h0001; + LUT4 plm_fsm_rc_counter_ts2_3_loadable_tx_counter_un1_reg_tx_count_0_a2_0_a3_4 ( + .I0(plm_fsm_rc_counter_ts2_3_reg_tx_count[0]), + .I1(plm_fsm_rc_counter_ts2_3_reg_tx_count[1]), + .I2(plm_fsm_rc_counter_ts2_3_reg_tx_count[2]), + .I3(plm_fsm_rc_counter_ts2_3_reg_tx_count[3]), + .O(plm_fsm_rc_counter_ts2_3_un1_reg_tx_count_0_a2_0_a3_4) + ); + defparam plm_fsm_rc_counter_ts2_3_loadable_tx_counter_un1_reg_tx_count_0_a2_0_a3_5.INIT = 16'h0001; + LUT4 plm_fsm_rc_counter_ts2_3_loadable_tx_counter_un1_reg_tx_count_0_a2_0_a3_5 ( + .I0(plm_fsm_rc_counter_ts2_3_reg_tx_count[4]), + .I1(plm_fsm_rc_counter_ts2_3_reg_tx_count[5]), + .I2(plm_fsm_rc_counter_ts2_3_reg_tx_count[6]), + .I3(plm_fsm_rc_counter_ts2_3_reg_tx_count[7]), + .O(plm_fsm_rc_counter_ts2_3_un1_reg_tx_count_0_a2_0_a3_5) + ); + defparam plm_fsm_rc_counter_ts2_3_loadable_rx_counter_un1_reg_rx_count_0_a2_0_a3_4.INIT = 16'h0001; + LUT4 plm_fsm_rc_counter_ts2_3_loadable_rx_counter_un1_reg_rx_count_0_a2_0_a3_4 ( + .I0(plm_fsm_rc_counter_ts2_3_reg_rx_count[0]), + .I1(plm_fsm_rc_counter_ts2_3_reg_rx_count[1]), + .I2(plm_fsm_rc_counter_ts2_3_reg_rx_count[2]), + .I3(plm_fsm_rc_counter_ts2_3_reg_rx_count[3]), + .O(plm_fsm_rc_counter_ts2_3_un1_reg_rx_count_0_a2_0_a3_4) + ); + defparam plm_fsm_rc_counter_ts2_3_loadable_rx_counter_un1_reg_rx_count_0_a2_0_a3_5.INIT = 16'h0001; + LUT4 plm_fsm_rc_counter_ts2_3_loadable_rx_counter_un1_reg_rx_count_0_a2_0_a3_5 ( + .I0(plm_fsm_rc_counter_ts2_3_reg_rx_count[4]), + .I1(plm_fsm_rc_counter_ts2_3_reg_rx_count[5]), + .I2(plm_fsm_rc_counter_ts2_3_reg_rx_count[6]), + .I3(plm_fsm_rc_counter_ts2_3_reg_rx_count[7]), + .O(plm_fsm_rc_counter_ts2_3_un1_reg_rx_count_0_a2_0_a3_5) + ); + defparam plm_fsm_rc_counter_ts2_3_oneshot_monitor_N_60951_i.INIT = 4'hE; + LUT2 plm_fsm_rc_counter_ts2_3_oneshot_monitor_N_60951_i ( + .I0(plm_reg_ts2_1_2), + .I1(N_29556_i), + .O(plm_fsm_rc_counter_ts2_3_N_60951_i) + ); + defparam plm_fsm_rc_counter_ts2_3_un1_enable_1_0_a2_i_i_a3_0_a2.INIT = 4'h2; + LUT2 plm_fsm_rc_counter_ts2_3_un1_enable_1_0_a2_i_i_a3_0_a2 ( + .I0(plm_fsm_rc_counter_ts2_3_un1_enable_1_0_a2_i_o2_i_a3_0_a2_1989), + .I1(plm_fsm_rc_counter_ts2_3_reg_tx_expired_1987), + .O(plm_fsm_rc_counter_ts2_3_un1_enable_1_0_a2_i_i_a3_0_a2_6) + ); + defparam plm_fsm_rc_counter_ts2_3_loadable_rx_counter_N_11106_i.INIT = 8'hFE; + LUT3 plm_fsm_rc_counter_ts2_3_loadable_rx_counter_N_11106_i ( + .I0(plm_reg_ts2_1_2), + .I1(N_29556_i), + .I2(plm_fsm_rc_counter_ts2_3_reg_rx_expired_319), + .O(plm_fsm_rc_counter_ts2_3_N_11106_i) + ); + defparam plm_fsm_rc_counter_ts2_3_N_60932_i.INIT = 16'hFFEF; + LUT4 plm_fsm_rc_counter_ts2_3_N_60932_i ( + .I0(plm_reg_sym_sent_6_), + .I1(N_29556_i), + .I2(plm_fsm_rc_counter_ts2_3_reg_oneshot_1985), + .I3(plm_fsm_rc_counter_ts2_3_reg_tx_expired_1987), + .O(plm_fsm_rc_counter_ts2_3_N_60932_i_1984) + ); + defparam plm_fsm_rc_counter_ts2_3_N_60936_i.INIT = 8'hD5; + LUT3 plm_fsm_rc_counter_ts2_3_N_60936_i ( + .I0(plm_fsm_rc_counter_ts2_3_un1_enable_1_0_a2_i_o2_i_a3_0_a2_1989), + .I1(plm_fsm_rc_counter_ts2_3_un1_reg_tx_count_0_a2_0_a3_4), + .I2(plm_fsm_rc_counter_ts2_3_un1_reg_tx_count_0_a2_0_a3_5), + .O(plm_fsm_rc_counter_ts2_3_N_60936_i_1986) + ); + defparam plm_fsm_rc_counter_ts2_3_loadable_rx_counter_N_60950_i.INIT = 8'hEA; + LUT3 plm_fsm_rc_counter_ts2_3_loadable_rx_counter_N_60950_i ( + .I0(N_29556_i), + .I1(plm_fsm_rc_counter_ts2_3_un1_reg_rx_count_0_a2_0_a3_4), + .I2(plm_fsm_rc_counter_ts2_3_un1_reg_rx_count_0_a2_0_a3_5), + .O(plm_fsm_rc_counter_ts2_3_N_60950_i) + ); + defparam plm_fsm_rc_counter_ts2_3_N_87551_i.INIT = 8'hAE; + LUT3_L plm_fsm_rc_counter_ts2_3_N_87551_i ( + .I0(N_29556_i), + .I1(plm_fsm_N_59110_1), + .I2(plm_fsm_rc_counter_ts2_3_reg_rx_expired_319), + .LO(plm_fsm_rc_counter_ts2_3_N_87551_i_1988) + ); + defparam plm_fsm_rc_counter_ts2_3_flagit_reg_expired_5_0_a2_i_i_a3_0_a2.INIT = 8'h40; + LUT3_L plm_fsm_rc_counter_ts2_3_flagit_reg_expired_5_0_a2_i_i_a3_0_a2 ( + .I0(N_29556_i_1), + .I1(plm_fsm_rc_counter_ts2_3_reg_rx_expired_319), + .I2(plm_fsm_rc_counter_ts2_3_reg_tx_expired_1987), + .LO(plm_fsm_rc_counter_ts2_3_reg_expired_5_0_a2_i_i_a3_0_a2_6) + ); + defparam plm_fsm_rc_counter_ts2_3_N_60916_i.INIT = 4'hB; + LUT2 plm_fsm_rc_counter_ts2_3_N_60916_i ( + .I0(plm_fsm_rc_counter_ts2_3_reg_tx_expired_1987), + .I1(plm_fsm_rc_counter_ts2_3_un1_enable_1_0_a2_i_o2_i_a3_0_a2_1989), + .O(plm_fsm_rc_counter_ts2_3_N_60916_i_1983) + ); + FDCE plm_fsm_rc_counter_ts2_3_reg_tx_count_7_ ( + .CE(plm_fsm_rc_counter_ts2_3_N_60932_i_1984), + .C(mgt_clk), + .D(plm_fsm_rc_counter_ts2_3_reg_tx_count_s[7]), + .Q(plm_fsm_rc_counter_ts2_3_reg_tx_count[7]), + .CLR(plm_rst) + ); + FDCE plm_fsm_rc_counter_ts2_3_reg_tx_count_6_ ( + .CE(plm_fsm_rc_counter_ts2_3_N_60932_i_1984), + .C(mgt_clk), + .D(plm_fsm_rc_counter_ts2_3_reg_tx_count_s[6]), + .Q(plm_fsm_rc_counter_ts2_3_reg_tx_count[6]), + .CLR(plm_rst) + ); + FDCE plm_fsm_rc_counter_ts2_3_reg_tx_count_5_ ( + .CE(plm_fsm_rc_counter_ts2_3_N_60932_i_1984), + .C(mgt_clk), + .D(plm_fsm_rc_counter_ts2_3_reg_tx_count_s[5]), + .Q(plm_fsm_rc_counter_ts2_3_reg_tx_count[5]), + .CLR(plm_rst) + ); + FDPE plm_fsm_rc_counter_ts2_3_reg_tx_count_4_ ( + .PRE(plm_rst), + .CE(plm_fsm_rc_counter_ts2_3_N_60932_i_1984), + .C(mgt_clk), + .D(plm_fsm_rc_counter_ts2_3_reg_tx_count_s[4]), + .Q(plm_fsm_rc_counter_ts2_3_reg_tx_count[4]) + ); + FDCE plm_fsm_rc_counter_ts2_3_reg_tx_count_3_ ( + .CE(plm_fsm_rc_counter_ts2_3_N_60932_i_1984), + .C(mgt_clk), + .D(plm_fsm_rc_counter_ts2_3_reg_tx_count_s[3]), + .Q(plm_fsm_rc_counter_ts2_3_reg_tx_count[3]), + .CLR(plm_rst) + ); + FDCE plm_fsm_rc_counter_ts2_3_reg_tx_count_2_ ( + .CE(plm_fsm_rc_counter_ts2_3_N_60932_i_1984), + .C(mgt_clk), + .D(plm_fsm_rc_counter_ts2_3_reg_tx_count_s[2]), + .Q(plm_fsm_rc_counter_ts2_3_reg_tx_count[2]), + .CLR(plm_rst) + ); + FDCE plm_fsm_rc_counter_ts2_3_reg_tx_count_1_ ( + .CE(plm_fsm_rc_counter_ts2_3_N_60932_i_1984), + .C(mgt_clk), + .D(plm_fsm_rc_counter_ts2_3_reg_tx_count_s[1]), + .Q(plm_fsm_rc_counter_ts2_3_reg_tx_count[1]), + .CLR(plm_rst) + ); + FDCE plm_fsm_rc_counter_ts2_3_reg_tx_count_0_ ( + .CE(plm_fsm_rc_counter_ts2_3_N_60932_i_1984), + .C(mgt_clk), + .D(plm_fsm_rc_counter_ts2_3_reg_tx_count_s[0]), + .Q(plm_fsm_rc_counter_ts2_3_reg_tx_count[0]), + .CLR(plm_rst) + ); + FDCE plm_fsm_rc_counter_ts2_3_reg_rx_count_7_ ( + .CE(plm_fsm_rc_counter_ts2_3_N_11106_i), + .C(mgt_clk), + .D(plm_fsm_rc_counter_ts2_3_reg_rx_count_s[7]), + .Q(plm_fsm_rc_counter_ts2_3_reg_rx_count[7]), + .CLR(plm_rst) + ); + FDCE plm_fsm_rc_counter_ts2_3_reg_rx_count_6_ ( + .CE(plm_fsm_rc_counter_ts2_3_N_11106_i), + .C(mgt_clk), + .D(plm_fsm_rc_counter_ts2_3_reg_rx_count_s[6]), + .Q(plm_fsm_rc_counter_ts2_3_reg_rx_count[6]), + .CLR(plm_rst) + ); + FDCE plm_fsm_rc_counter_ts2_3_reg_rx_count_5_ ( + .CE(plm_fsm_rc_counter_ts2_3_N_11106_i), + .C(mgt_clk), + .D(plm_fsm_rc_counter_ts2_3_reg_rx_count_s[5]), + .Q(plm_fsm_rc_counter_ts2_3_reg_rx_count[5]), + .CLR(plm_rst) + ); + FDCE plm_fsm_rc_counter_ts2_3_reg_rx_count_4_ ( + .CE(plm_fsm_rc_counter_ts2_3_N_11106_i), + .C(mgt_clk), + .D(plm_fsm_rc_counter_ts2_3_reg_rx_count_s[4]), + .Q(plm_fsm_rc_counter_ts2_3_reg_rx_count[4]), + .CLR(plm_rst) + ); + FDPE plm_fsm_rc_counter_ts2_3_reg_rx_count_3_ ( + .PRE(plm_rst), + .CE(plm_fsm_rc_counter_ts2_3_N_11106_i), + .C(mgt_clk), + .D(plm_fsm_rc_counter_ts2_3_reg_rx_count_s[3]), + .Q(plm_fsm_rc_counter_ts2_3_reg_rx_count[3]) + ); + FDCE plm_fsm_rc_counter_ts2_3_reg_rx_count_2_ ( + .CE(plm_fsm_rc_counter_ts2_3_N_11106_i), + .C(mgt_clk), + .D(plm_fsm_rc_counter_ts2_3_reg_rx_count_s[2]), + .Q(plm_fsm_rc_counter_ts2_3_reg_rx_count[2]), + .CLR(plm_rst) + ); + FDCE plm_fsm_rc_counter_ts2_3_reg_rx_count_1_ ( + .CE(plm_fsm_rc_counter_ts2_3_N_11106_i), + .C(mgt_clk), + .D(plm_fsm_rc_counter_ts2_3_reg_rx_count_s[1]), + .Q(plm_fsm_rc_counter_ts2_3_reg_rx_count[1]), + .CLR(plm_rst) + ); + FDCE plm_fsm_rc_counter_ts2_3_reg_rx_count_0_ ( + .CE(plm_fsm_rc_counter_ts2_3_N_11106_i), + .C(mgt_clk), + .D(plm_fsm_rc_counter_ts2_3_reg_rx_count_s[0]), + .Q(plm_fsm_rc_counter_ts2_3_reg_rx_count[0]), + .CLR(plm_rst) + ); + FDC plm_fsm_rc_counter_ts2_3_reg_expired ( + .C(mgt_clk), + .D(plm_fsm_rc_counter_ts2_3_reg_expired_5_0_a2_i_i_a3_0_a2_6), + .Q(plm_fsm_rc_cntrout_ts2_3), + .CLR(plm_rst) + ); + FDCE plm_fsm_rc_counter_ts2_3_reg_oneshot ( + .CE(plm_fsm_rc_counter_ts2_3_N_60951_i), + .C(mgt_clk), + .D(N_29556_i_0), + .Q(plm_fsm_rc_counter_ts2_3_reg_oneshot_1985), + .CLR(plm_rst) + ); + FDCE plm_fsm_rc_counter_ts2_3_reg_rx_expired ( + .CE(plm_fsm_rc_counter_ts2_3_N_60950_i), + .C(mgt_clk), + .D(N_29556_i_0), + .Q(plm_fsm_rc_counter_ts2_3_reg_rx_expired_319), + .CLR(plm_rst) + ); + FDCE plm_fsm_rc_counter_ts2_3_reg_tx_expired ( + .CE(plm_fsm_rc_counter_ts2_3_N_60936_i_1986), + .C(mgt_clk), + .D(plm_fsm_rc_counter_ts2_3_un1_enable_1_0_a2_i_o2_i_a3_0_a2_1989), + .Q(plm_fsm_rc_counter_ts2_3_reg_tx_expired_1987), + .CLR(plm_rst) + ); + defparam plm_fsm_rc_counter_ts2_3_reg_rx_count_qxu_0_0_.INIT = 4'h7; + LUT2_L plm_fsm_rc_counter_ts2_3_reg_rx_count_qxu_0_0_ ( + .I0(N_22826), + .I1(plm_fsm_rc_counter_ts2_3_reg_rx_count[0]), + .LO(plm_fsm_rc_counter_ts2_3_reg_rx_count_qxu[0]) + ); + defparam plm_fsm_rc_counter_ts2_3_reg_rx_count_qxu_0_1_.INIT = 4'h7; + LUT2_L plm_fsm_rc_counter_ts2_3_reg_rx_count_qxu_0_1_ ( + .I0(N_22826), + .I1(plm_fsm_rc_counter_ts2_3_reg_rx_count[1]), + .LO(plm_fsm_rc_counter_ts2_3_reg_rx_count_qxu[1]) + ); + defparam plm_fsm_rc_counter_ts2_3_reg_rx_count_qxu_0_2_.INIT = 4'h7; + LUT2_L plm_fsm_rc_counter_ts2_3_reg_rx_count_qxu_0_2_ ( + .I0(N_22826), + .I1(plm_fsm_rc_counter_ts2_3_reg_rx_count[2]), + .LO(plm_fsm_rc_counter_ts2_3_reg_rx_count_qxu[2]) + ); + defparam plm_fsm_rc_counter_ts2_3_reg_rx_count_qxu_0_3_.INIT = 8'h1B; + LUT3_L plm_fsm_rc_counter_ts2_3_reg_rx_count_qxu_0_3_ ( + .I0(N_22826), + .I1(plm_fsm_rc_counter_ts2_3_N_87551_i_1988), + .I2(plm_fsm_rc_counter_ts2_3_reg_rx_count[3]), + .LO(plm_fsm_rc_counter_ts2_3_reg_rx_count_qxu[3]) + ); + defparam plm_fsm_rc_counter_ts2_3_reg_rx_count_qxu_0_4_.INIT = 4'h7; + LUT2_L plm_fsm_rc_counter_ts2_3_reg_rx_count_qxu_0_4_ ( + .I0(N_22826), + .I1(plm_fsm_rc_counter_ts2_3_reg_rx_count[4]), + .LO(plm_fsm_rc_counter_ts2_3_reg_rx_count_qxu[4]) + ); + defparam plm_fsm_rc_counter_ts2_3_reg_rx_count_qxu_0_5_.INIT = 4'h7; + LUT2_L plm_fsm_rc_counter_ts2_3_reg_rx_count_qxu_0_5_ ( + .I0(N_22826), + .I1(plm_fsm_rc_counter_ts2_3_reg_rx_count[5]), + .LO(plm_fsm_rc_counter_ts2_3_reg_rx_count_qxu[5]) + ); + defparam plm_fsm_rc_counter_ts2_3_reg_rx_count_qxu_0_6_.INIT = 4'h7; + LUT2_L plm_fsm_rc_counter_ts2_3_reg_rx_count_qxu_0_6_ ( + .I0(N_22826), + .I1(plm_fsm_rc_counter_ts2_3_reg_rx_count[6]), + .LO(plm_fsm_rc_counter_ts2_3_reg_rx_count_qxu[6]) + ); + defparam plm_fsm_rc_counter_ts2_3_reg_rx_count_qxu_0_7_.INIT = 4'h7; + LUT2_L plm_fsm_rc_counter_ts2_3_reg_rx_count_qxu_0_7_ ( + .I0(N_22826), + .I1(plm_fsm_rc_counter_ts2_3_reg_rx_count[7]), + .LO(plm_fsm_rc_counter_ts2_3_reg_rx_count_qxu[7]) + ); + defparam plm_fsm_rc_counter_ts2_3_reg_tx_count_qxu_0_0_.INIT = 4'h7; + LUT2_L plm_fsm_rc_counter_ts2_3_reg_tx_count_qxu_0_0_ ( + .I0(plm_fsm_rc_counter_ts2_3_un1_enable_1_0_a2_i_i_a3_0_a2_6), + .I1(plm_fsm_rc_counter_ts2_3_reg_tx_count[0]), + .LO(plm_fsm_rc_counter_ts2_3_reg_tx_count_qxu[0]) + ); + defparam plm_fsm_rc_counter_ts2_3_reg_tx_count_qxu_0_1_.INIT = 4'h7; + LUT2_L plm_fsm_rc_counter_ts2_3_reg_tx_count_qxu_0_1_ ( + .I0(plm_fsm_rc_counter_ts2_3_un1_enable_1_0_a2_i_i_a3_0_a2_6), + .I1(plm_fsm_rc_counter_ts2_3_reg_tx_count[1]), + .LO(plm_fsm_rc_counter_ts2_3_reg_tx_count_qxu[1]) + ); + defparam plm_fsm_rc_counter_ts2_3_reg_tx_count_qxu_0_2_.INIT = 4'h7; + LUT2_L plm_fsm_rc_counter_ts2_3_reg_tx_count_qxu_0_2_ ( + .I0(plm_fsm_rc_counter_ts2_3_un1_enable_1_0_a2_i_i_a3_0_a2_6), + .I1(plm_fsm_rc_counter_ts2_3_reg_tx_count[2]), + .LO(plm_fsm_rc_counter_ts2_3_reg_tx_count_qxu[2]) + ); + defparam plm_fsm_rc_counter_ts2_3_reg_tx_count_qxu_0_3_.INIT = 4'h7; + LUT2_L plm_fsm_rc_counter_ts2_3_reg_tx_count_qxu_0_3_ ( + .I0(plm_fsm_rc_counter_ts2_3_un1_enable_1_0_a2_i_i_a3_0_a2_6), + .I1(plm_fsm_rc_counter_ts2_3_reg_tx_count[3]), + .LO(plm_fsm_rc_counter_ts2_3_reg_tx_count_qxu[3]) + ); + defparam plm_fsm_rc_counter_ts2_3_reg_tx_count_qxu_0_4_.INIT = 8'h4E; + LUT3_L plm_fsm_rc_counter_ts2_3_reg_tx_count_qxu_0_4_ ( + .I0(plm_fsm_rc_counter_ts2_3_un1_enable_1_0_a2_i_i_a3_0_a2_6), + .I1(plm_fsm_rc_counter_ts2_3_un1_enable_1_0_a2_i_o2_i_a3_0_a2_1989), + .I2(plm_fsm_rc_counter_ts2_3_reg_tx_count[4]), + .LO(plm_fsm_rc_counter_ts2_3_reg_tx_count_qxu[4]) + ); + defparam plm_fsm_rc_counter_ts2_3_reg_tx_count_qxu_0_5_.INIT = 4'h7; + LUT2_L plm_fsm_rc_counter_ts2_3_reg_tx_count_qxu_0_5_ ( + .I0(plm_fsm_rc_counter_ts2_3_un1_enable_1_0_a2_i_i_a3_0_a2_6), + .I1(plm_fsm_rc_counter_ts2_3_reg_tx_count[5]), + .LO(plm_fsm_rc_counter_ts2_3_reg_tx_count_qxu[5]) + ); + defparam plm_fsm_rc_counter_ts2_3_reg_tx_count_qxu_0_6_.INIT = 4'h7; + LUT2_L plm_fsm_rc_counter_ts2_3_reg_tx_count_qxu_0_6_ ( + .I0(plm_fsm_rc_counter_ts2_3_un1_enable_1_0_a2_i_i_a3_0_a2_6), + .I1(plm_fsm_rc_counter_ts2_3_reg_tx_count[6]), + .LO(plm_fsm_rc_counter_ts2_3_reg_tx_count_qxu[6]) + ); + defparam plm_fsm_rc_counter_ts2_3_reg_tx_count_qxu_0_7_.INIT = 4'h7; + LUT2_L plm_fsm_rc_counter_ts2_3_reg_tx_count_qxu_0_7_ ( + .I0(plm_fsm_rc_counter_ts2_3_un1_enable_1_0_a2_i_i_a3_0_a2_6), + .I1(plm_fsm_rc_counter_ts2_3_reg_tx_count[7]), + .LO(plm_fsm_rc_counter_ts2_3_reg_tx_count_qxu[7]) + ); + GND plm_fsm_ri_timer_GND ( + .G(plm_fsm_ri_timer_GND_1990) + ); + MUXCY_L plm_fsm_ri_timer_reg_count_cry_0_ ( + .CI(plm_fsm_reg_state_16__603), + .DI(plm_fsm_ri_timer_GND_1990), + .LO(plm_fsm_ri_timer_reg_count_cry[0]), + .S(plm_fsm_ri_timer_reg_count_qxu[0]) + ); + XORCY plm_fsm_ri_timer_reg_count_s_0_ ( + .CI(plm_fsm_reg_state_16__603), + .LI(plm_fsm_ri_timer_reg_count_qxu[0]), + .O(plm_fsm_ri_timer_reg_count_s[0]) + ); + MUXCY_L plm_fsm_ri_timer_reg_count_cry_1_ ( + .CI(plm_fsm_ri_timer_reg_count_cry[0]), + .DI(plm_fsm_ri_timer_GND_1990), + .LO(plm_fsm_ri_timer_reg_count_cry[1]), + .S(plm_fsm_ri_timer_reg_count_qxu[1]) + ); + XORCY plm_fsm_ri_timer_reg_count_s_1_ ( + .CI(plm_fsm_ri_timer_reg_count_cry[0]), + .LI(plm_fsm_ri_timer_reg_count_qxu[1]), + .O(plm_fsm_ri_timer_reg_count_s[1]) + ); + MUXCY_L plm_fsm_ri_timer_reg_count_cry_2_ ( + .CI(plm_fsm_ri_timer_reg_count_cry[1]), + .DI(plm_fsm_ri_timer_GND_1990), + .LO(plm_fsm_ri_timer_reg_count_cry[2]), + .S(plm_fsm_ri_timer_reg_count_qxu[2]) + ); + XORCY plm_fsm_ri_timer_reg_count_s_2_ ( + .CI(plm_fsm_ri_timer_reg_count_cry[1]), + .LI(plm_fsm_ri_timer_reg_count_qxu[2]), + .O(plm_fsm_ri_timer_reg_count_s[2]) + ); + MUXCY_L plm_fsm_ri_timer_reg_count_cry_3_ ( + .CI(plm_fsm_ri_timer_reg_count_cry[2]), + .DI(plm_fsm_ri_timer_GND_1990), + .LO(plm_fsm_ri_timer_reg_count_cry[3]), + .S(plm_fsm_ri_timer_reg_count_qxu[3]) + ); + XORCY plm_fsm_ri_timer_reg_count_s_3_ ( + .CI(plm_fsm_ri_timer_reg_count_cry[2]), + .LI(plm_fsm_ri_timer_reg_count_qxu[3]), + .O(plm_fsm_ri_timer_reg_count_s[3]) + ); + MUXCY_L plm_fsm_ri_timer_reg_count_cry_4_ ( + .CI(plm_fsm_ri_timer_reg_count_cry[3]), + .DI(plm_fsm_ri_timer_GND_1990), + .LO(plm_fsm_ri_timer_reg_count_cry[4]), + .S(plm_fsm_ri_timer_reg_count_qxu[4]) + ); + XORCY plm_fsm_ri_timer_reg_count_s_4_ ( + .CI(plm_fsm_ri_timer_reg_count_cry[3]), + .LI(plm_fsm_ri_timer_reg_count_qxu[4]), + .O(plm_fsm_ri_timer_reg_count_s[4]) + ); + MUXCY_L plm_fsm_ri_timer_reg_count_cry_5_ ( + .CI(plm_fsm_ri_timer_reg_count_cry[4]), + .DI(plm_fsm_ri_timer_GND_1990), + .LO(plm_fsm_ri_timer_reg_count_cry[5]), + .S(plm_fsm_ri_timer_reg_count_qxu[5]) + ); + XORCY plm_fsm_ri_timer_reg_count_s_5_ ( + .CI(plm_fsm_ri_timer_reg_count_cry[4]), + .LI(plm_fsm_ri_timer_reg_count_qxu[5]), + .O(plm_fsm_ri_timer_reg_count_s[5]) + ); + MUXCY_L plm_fsm_ri_timer_reg_count_cry_6_ ( + .CI(plm_fsm_ri_timer_reg_count_cry[5]), + .DI(plm_fsm_ri_timer_GND_1990), + .LO(plm_fsm_ri_timer_reg_count_cry[6]), + .S(plm_fsm_ri_timer_reg_count_qxu[6]) + ); + XORCY plm_fsm_ri_timer_reg_count_s_6_ ( + .CI(plm_fsm_ri_timer_reg_count_cry[5]), + .LI(plm_fsm_ri_timer_reg_count_qxu[6]), + .O(plm_fsm_ri_timer_reg_count_s[6]) + ); + MUXCY_L plm_fsm_ri_timer_reg_count_cry_7_ ( + .CI(plm_fsm_ri_timer_reg_count_cry[6]), + .DI(plm_fsm_ri_timer_GND_1990), + .LO(plm_fsm_ri_timer_reg_count_cry[7]), + .S(plm_fsm_ri_timer_reg_count_qxu[7]) + ); + XORCY plm_fsm_ri_timer_reg_count_s_7_ ( + .CI(plm_fsm_ri_timer_reg_count_cry[6]), + .LI(plm_fsm_ri_timer_reg_count_qxu[7]), + .O(plm_fsm_ri_timer_reg_count_s[7]) + ); + MUXCY_L plm_fsm_ri_timer_reg_count_cry_8_ ( + .CI(plm_fsm_ri_timer_reg_count_cry[7]), + .DI(plm_fsm_ri_timer_GND_1990), + .LO(plm_fsm_ri_timer_reg_count_cry[8]), + .S(plm_fsm_ri_timer_reg_count_qxu[8]) + ); + XORCY plm_fsm_ri_timer_reg_count_s_8_ ( + .CI(plm_fsm_ri_timer_reg_count_cry[7]), + .LI(plm_fsm_ri_timer_reg_count_qxu[8]), + .O(plm_fsm_ri_timer_reg_count_s[8]) + ); + MUXCY_L plm_fsm_ri_timer_reg_count_cry_9_ ( + .CI(plm_fsm_ri_timer_reg_count_cry[8]), + .DI(plm_fsm_ri_timer_GND_1990), + .LO(plm_fsm_ri_timer_reg_count_cry[9]), + .S(plm_fsm_ri_timer_reg_count_qxu[9]) + ); + XORCY plm_fsm_ri_timer_reg_count_s_9_ ( + .CI(plm_fsm_ri_timer_reg_count_cry[8]), + .LI(plm_fsm_ri_timer_reg_count_qxu[9]), + .O(plm_fsm_ri_timer_reg_count_s[9]) + ); + MUXCY_L plm_fsm_ri_timer_reg_count_cry_10_ ( + .CI(plm_fsm_ri_timer_reg_count_cry[9]), + .DI(plm_fsm_ri_timer_GND_1990), + .LO(plm_fsm_ri_timer_reg_count_cry[10]), + .S(plm_fsm_ri_timer_reg_count_qxu[10]) + ); + XORCY plm_fsm_ri_timer_reg_count_s_10_ ( + .CI(plm_fsm_ri_timer_reg_count_cry[9]), + .LI(plm_fsm_ri_timer_reg_count_qxu[10]), + .O(plm_fsm_ri_timer_reg_count_s[10]) + ); + MUXCY_L plm_fsm_ri_timer_reg_count_cry_11_ ( + .CI(plm_fsm_ri_timer_reg_count_cry[10]), + .DI(plm_fsm_ri_timer_GND_1990), + .LO(plm_fsm_ri_timer_reg_count_cry[11]), + .S(plm_fsm_ri_timer_reg_count_qxu[11]) + ); + XORCY plm_fsm_ri_timer_reg_count_s_11_ ( + .CI(plm_fsm_ri_timer_reg_count_cry[10]), + .LI(plm_fsm_ri_timer_reg_count_qxu[11]), + .O(plm_fsm_ri_timer_reg_count_s[11]) + ); + MUXCY_L plm_fsm_ri_timer_reg_count_cry_12_ ( + .CI(plm_fsm_ri_timer_reg_count_cry[11]), + .DI(plm_fsm_ri_timer_GND_1990), + .LO(plm_fsm_ri_timer_reg_count_cry[12]), + .S(plm_fsm_ri_timer_reg_count_qxu[12]) + ); + XORCY plm_fsm_ri_timer_reg_count_s_12_ ( + .CI(plm_fsm_ri_timer_reg_count_cry[11]), + .LI(plm_fsm_ri_timer_reg_count_qxu[12]), + .O(plm_fsm_ri_timer_reg_count_s[12]) + ); + MUXCY_L plm_fsm_ri_timer_reg_count_cry_13_ ( + .CI(plm_fsm_ri_timer_reg_count_cry[12]), + .DI(plm_fsm_ri_timer_GND_1990), + .LO(plm_fsm_ri_timer_reg_count_cry[13]), + .S(plm_fsm_ri_timer_reg_count_qxu[13]) + ); + XORCY plm_fsm_ri_timer_reg_count_s_13_ ( + .CI(plm_fsm_ri_timer_reg_count_cry[12]), + .LI(plm_fsm_ri_timer_reg_count_qxu[13]), + .O(plm_fsm_ri_timer_reg_count_s[13]) + ); + MUXCY_L plm_fsm_ri_timer_reg_count_cry_14_ ( + .CI(plm_fsm_ri_timer_reg_count_cry[13]), + .DI(plm_fsm_ri_timer_GND_1990), + .LO(plm_fsm_ri_timer_reg_count_cry[14]), + .S(plm_fsm_ri_timer_reg_count_qxu[14]) + ); + XORCY plm_fsm_ri_timer_reg_count_s_14_ ( + .CI(plm_fsm_ri_timer_reg_count_cry[13]), + .LI(plm_fsm_ri_timer_reg_count_qxu[14]), + .O(plm_fsm_ri_timer_reg_count_s[14]) + ); + MUXCY_L plm_fsm_ri_timer_reg_count_cry_15_ ( + .CI(plm_fsm_ri_timer_reg_count_cry[14]), + .DI(plm_fsm_ri_timer_GND_1990), + .LO(plm_fsm_ri_timer_reg_count_cry[15]), + .S(plm_fsm_ri_timer_reg_count_qxu[15]) + ); + XORCY plm_fsm_ri_timer_reg_count_s_15_ ( + .CI(plm_fsm_ri_timer_reg_count_cry[14]), + .LI(plm_fsm_ri_timer_reg_count_qxu[15]), + .O(plm_fsm_ri_timer_reg_count_s[15]) + ); + MUXCY_L plm_fsm_ri_timer_reg_count_cry_16_ ( + .CI(plm_fsm_ri_timer_reg_count_cry[15]), + .DI(plm_fsm_ri_timer_GND_1990), + .LO(plm_fsm_ri_timer_reg_count_cry[16]), + .S(plm_fsm_ri_timer_reg_count_qxu[16]) + ); + XORCY plm_fsm_ri_timer_reg_count_s_16_ ( + .CI(plm_fsm_ri_timer_reg_count_cry[15]), + .LI(plm_fsm_ri_timer_reg_count_qxu[16]), + .O(plm_fsm_ri_timer_reg_count_s[16]) + ); + MUXCY_L plm_fsm_ri_timer_reg_count_cry_17_ ( + .CI(plm_fsm_ri_timer_reg_count_cry[16]), + .DI(plm_fsm_ri_timer_GND_1990), + .LO(plm_fsm_ri_timer_reg_count_cry[17]), + .S(plm_fsm_ri_timer_reg_count_qxu[17]) + ); + XORCY plm_fsm_ri_timer_reg_count_s_17_ ( + .CI(plm_fsm_ri_timer_reg_count_cry[16]), + .LI(plm_fsm_ri_timer_reg_count_qxu[17]), + .O(plm_fsm_ri_timer_reg_count_s[17]) + ); + MUXCY_L plm_fsm_ri_timer_reg_count_cry_18_ ( + .CI(plm_fsm_ri_timer_reg_count_cry[17]), + .DI(plm_fsm_ri_timer_GND_1990), + .LO(plm_fsm_ri_timer_reg_count_cry[18]), + .S(plm_fsm_ri_timer_reg_count_qxu[18]) + ); + XORCY plm_fsm_ri_timer_reg_count_s_18_ ( + .CI(plm_fsm_ri_timer_reg_count_cry[17]), + .LI(plm_fsm_ri_timer_reg_count_qxu[18]), + .O(plm_fsm_ri_timer_reg_count_s[18]) + ); + MUXCY_L plm_fsm_ri_timer_reg_count_cry_19_ ( + .CI(plm_fsm_ri_timer_reg_count_cry[18]), + .DI(plm_fsm_ri_timer_GND_1990), + .LO(plm_fsm_ri_timer_reg_count_cry[19]), + .S(plm_fsm_ri_timer_reg_count_qxu[19]) + ); + XORCY plm_fsm_ri_timer_reg_count_s_19_ ( + .CI(plm_fsm_ri_timer_reg_count_cry[18]), + .LI(plm_fsm_ri_timer_reg_count_qxu[19]), + .O(plm_fsm_ri_timer_reg_count_s[19]) + ); + MUXCY_L plm_fsm_ri_timer_reg_count_cry_20_ ( + .CI(plm_fsm_ri_timer_reg_count_cry[19]), + .DI(plm_fsm_ri_timer_GND_1990), + .LO(plm_fsm_ri_timer_reg_count_cry[20]), + .S(plm_fsm_ri_timer_reg_count_qxu[20]) + ); + XORCY plm_fsm_ri_timer_reg_count_s_20_ ( + .CI(plm_fsm_ri_timer_reg_count_cry[19]), + .LI(plm_fsm_ri_timer_reg_count_qxu[20]), + .O(plm_fsm_ri_timer_reg_count_s[20]) + ); + MUXCY_L plm_fsm_ri_timer_reg_count_cry_21_ ( + .CI(plm_fsm_ri_timer_reg_count_cry[20]), + .DI(plm_fsm_ri_timer_GND_1990), + .LO(plm_fsm_ri_timer_reg_count_cry[21]), + .S(plm_fsm_ri_timer_reg_count_qxu[21]) + ); + XORCY plm_fsm_ri_timer_reg_count_s_21_ ( + .CI(plm_fsm_ri_timer_reg_count_cry[20]), + .LI(plm_fsm_ri_timer_reg_count_qxu[21]), + .O(plm_fsm_ri_timer_reg_count_s[21]) + ); + XORCY plm_fsm_ri_timer_reg_count_s_22_ ( + .CI(plm_fsm_ri_timer_reg_count_cry[21]), + .LI(plm_fsm_ri_timer_reg_count_qxu[22]), + .O(plm_fsm_ri_timer_reg_count_s[22]) + ); + defparam plm_fsm_ri_timer_count_i_m3_i_m3_0_21_.INIT = 8'hD8; + LUT3 plm_fsm_ri_timer_count_i_m3_i_m3_0_21_ ( + .I0(cfg_cfg_6102[507]), + .I1(plm_fsm_ri_timer_reg_count[13]), + .I2(plm_fsm_ri_timer_reg_count[21]), + .O(plm_fsm_ri_timer_N_63709) + ); + defparam plm_fsm_ri_timer_count_i_m3_i_m3_0_20_.INIT = 8'hD8; + LUT3 plm_fsm_ri_timer_count_i_m3_i_m3_0_20_ ( + .I0(cfg_cfg_6102[507]), + .I1(plm_fsm_ri_timer_reg_count[12]), + .I2(plm_fsm_ri_timer_reg_count[20]), + .O(plm_fsm_ri_timer_N_63708) + ); + defparam plm_fsm_ri_timer_count_i_m3_i_m3_0_19_.INIT = 8'hD8; + LUT3_L plm_fsm_ri_timer_count_i_m3_i_m3_0_19_ ( + .I0(cfg_cfg_6102[507]), + .I1(plm_fsm_ri_timer_reg_count[11]), + .I2(plm_fsm_ri_timer_reg_count[19]), + .LO(plm_fsm_ri_timer_N_63707) + ); + defparam plm_fsm_ri_timer_count_i_m3_i_m3_0_18_.INIT = 8'hD8; + LUT3 plm_fsm_ri_timer_count_i_m3_i_m3_0_18_ ( + .I0(cfg_cfg_6102[507]), + .I1(plm_fsm_ri_timer_reg_count[10]), + .I2(plm_fsm_ri_timer_reg_count[18]), + .O(plm_fsm_ri_timer_N_63706) + ); + defparam plm_fsm_ri_timer_un1_expired_2ms_0.INIT = 16'h0415; + LUT4_L plm_fsm_ri_timer_un1_expired_2ms_0 ( + .I0(plm_fsm_ri_timer_N_63707), + .I1(cfg_cfg_6102[507]), + .I2(plm_fsm_ri_timer_reg_count[14]), + .I3(plm_fsm_ri_timer_reg_count[22]), + .LO(plm_fsm_ri_timer_un1_expired_2ms_0_1991) + ); + defparam plm_fsm_ri_timer_un1_expired_2ms.INIT = 16'h0100; + LUT4 plm_fsm_ri_timer_un1_expired_2ms ( + .I0(plm_fsm_ri_timer_N_63706), + .I1(plm_fsm_ri_timer_N_63708), + .I2(plm_fsm_ri_timer_N_63709), + .I3(plm_fsm_ri_timer_un1_expired_2ms_0_1991), + .O(plm_fsm_N_62888) + ); + FDC plm_fsm_ri_timer_reg_count_22_ ( + .C(mgt_clk), + .D(plm_fsm_ri_timer_reg_count_s[22]), + .Q(plm_fsm_ri_timer_reg_count[22]), + .CLR(plm_rst) + ); + FDC plm_fsm_ri_timer_reg_count_21_ ( + .C(mgt_clk), + .D(plm_fsm_ri_timer_reg_count_s[21]), + .Q(plm_fsm_ri_timer_reg_count[21]), + .CLR(plm_rst) + ); + FDC plm_fsm_ri_timer_reg_count_20_ ( + .C(mgt_clk), + .D(plm_fsm_ri_timer_reg_count_s[20]), + .Q(plm_fsm_ri_timer_reg_count[20]), + .CLR(plm_rst) + ); + FDC plm_fsm_ri_timer_reg_count_19_ ( + .C(mgt_clk), + .D(plm_fsm_ri_timer_reg_count_s[19]), + .Q(plm_fsm_ri_timer_reg_count[19]), + .CLR(plm_rst) + ); + FDC plm_fsm_ri_timer_reg_count_18_ ( + .C(mgt_clk), + .D(plm_fsm_ri_timer_reg_count_s[18]), + .Q(plm_fsm_ri_timer_reg_count[18]), + .CLR(plm_rst) + ); + FDC plm_fsm_ri_timer_reg_count_17_ ( + .C(mgt_clk), + .D(plm_fsm_ri_timer_reg_count_s[17]), + .Q(plm_fsm_ri_timer_reg_count[17]), + .CLR(plm_rst) + ); + FDC plm_fsm_ri_timer_reg_count_16_ ( + .C(mgt_clk), + .D(plm_fsm_ri_timer_reg_count_s[16]), + .Q(plm_fsm_ri_timer_reg_count[16]), + .CLR(plm_rst) + ); + FDC plm_fsm_ri_timer_reg_count_15_ ( + .C(mgt_clk), + .D(plm_fsm_ri_timer_reg_count_s[15]), + .Q(plm_fsm_ri_timer_reg_count[15]), + .CLR(plm_rst) + ); + FDC plm_fsm_ri_timer_reg_count_14_ ( + .C(mgt_clk), + .D(plm_fsm_ri_timer_reg_count_s[14]), + .Q(plm_fsm_ri_timer_reg_count[14]), + .CLR(plm_rst) + ); + FDC plm_fsm_ri_timer_reg_count_13_ ( + .C(mgt_clk), + .D(plm_fsm_ri_timer_reg_count_s[13]), + .Q(plm_fsm_ri_timer_reg_count[13]), + .CLR(plm_rst) + ); + FDC plm_fsm_ri_timer_reg_count_12_ ( + .C(mgt_clk), + .D(plm_fsm_ri_timer_reg_count_s[12]), + .Q(plm_fsm_ri_timer_reg_count[12]), + .CLR(plm_rst) + ); + FDC plm_fsm_ri_timer_reg_count_11_ ( + .C(mgt_clk), + .D(plm_fsm_ri_timer_reg_count_s[11]), + .Q(plm_fsm_ri_timer_reg_count[11]), + .CLR(plm_rst) + ); + FDC plm_fsm_ri_timer_reg_count_10_ ( + .C(mgt_clk), + .D(plm_fsm_ri_timer_reg_count_s[10]), + .Q(plm_fsm_ri_timer_reg_count[10]), + .CLR(plm_rst) + ); + FDC plm_fsm_ri_timer_reg_count_9_ ( + .C(mgt_clk), + .D(plm_fsm_ri_timer_reg_count_s[9]), + .Q(plm_fsm_ri_timer_reg_count[9]), + .CLR(plm_rst) + ); + FDC plm_fsm_ri_timer_reg_count_8_ ( + .C(mgt_clk), + .D(plm_fsm_ri_timer_reg_count_s[8]), + .Q(plm_fsm_ri_timer_reg_count[8]), + .CLR(plm_rst) + ); + FDC plm_fsm_ri_timer_reg_count_7_ ( + .C(mgt_clk), + .D(plm_fsm_ri_timer_reg_count_s[7]), + .Q(plm_fsm_ri_timer_reg_count[7]), + .CLR(plm_rst) + ); + FDC plm_fsm_ri_timer_reg_count_6_ ( + .C(mgt_clk), + .D(plm_fsm_ri_timer_reg_count_s[6]), + .Q(plm_fsm_ri_timer_reg_count[6]), + .CLR(plm_rst) + ); + FDC plm_fsm_ri_timer_reg_count_5_ ( + .C(mgt_clk), + .D(plm_fsm_ri_timer_reg_count_s[5]), + .Q(plm_fsm_ri_timer_reg_count[5]), + .CLR(plm_rst) + ); + FDC plm_fsm_ri_timer_reg_count_4_ ( + .C(mgt_clk), + .D(plm_fsm_ri_timer_reg_count_s[4]), + .Q(plm_fsm_ri_timer_reg_count[4]), + .CLR(plm_rst) + ); + FDC plm_fsm_ri_timer_reg_count_3_ ( + .C(mgt_clk), + .D(plm_fsm_ri_timer_reg_count_s[3]), + .Q(plm_fsm_ri_timer_reg_count[3]), + .CLR(plm_rst) + ); + FDC plm_fsm_ri_timer_reg_count_2_ ( + .C(mgt_clk), + .D(plm_fsm_ri_timer_reg_count_s[2]), + .Q(plm_fsm_ri_timer_reg_count[2]), + .CLR(plm_rst) + ); + FDC plm_fsm_ri_timer_reg_count_1_ ( + .C(mgt_clk), + .D(plm_fsm_ri_timer_reg_count_s[1]), + .Q(plm_fsm_ri_timer_reg_count[1]), + .CLR(plm_rst) + ); + FDC plm_fsm_ri_timer_reg_count_0_ ( + .C(mgt_clk), + .D(plm_fsm_ri_timer_reg_count_s[0]), + .Q(plm_fsm_ri_timer_reg_count[0]), + .CLR(plm_rst) + ); + defparam plm_fsm_ri_timer_reg_count_qxu_0_0_.INIT = 4'h8; + LUT2_L plm_fsm_ri_timer_reg_count_qxu_0_0_ ( + .I0(plm_fsm_reg_state_16__603), + .I1(plm_fsm_ri_timer_reg_count[0]), + .LO(plm_fsm_ri_timer_reg_count_qxu[0]) + ); + defparam plm_fsm_ri_timer_reg_count_qxu_0_1_.INIT = 4'h8; + LUT2_L plm_fsm_ri_timer_reg_count_qxu_0_1_ ( + .I0(plm_fsm_reg_state_16__603), + .I1(plm_fsm_ri_timer_reg_count[1]), + .LO(plm_fsm_ri_timer_reg_count_qxu[1]) + ); + defparam plm_fsm_ri_timer_reg_count_qxu_0_2_.INIT = 4'h8; + LUT2_L plm_fsm_ri_timer_reg_count_qxu_0_2_ ( + .I0(plm_fsm_reg_state_16__603), + .I1(plm_fsm_ri_timer_reg_count[2]), + .LO(plm_fsm_ri_timer_reg_count_qxu[2]) + ); + defparam plm_fsm_ri_timer_reg_count_qxu_0_3_.INIT = 4'h8; + LUT2_L plm_fsm_ri_timer_reg_count_qxu_0_3_ ( + .I0(plm_fsm_reg_state_16__603), + .I1(plm_fsm_ri_timer_reg_count[3]), + .LO(plm_fsm_ri_timer_reg_count_qxu[3]) + ); + defparam plm_fsm_ri_timer_reg_count_qxu_0_4_.INIT = 4'h8; + LUT2_L plm_fsm_ri_timer_reg_count_qxu_0_4_ ( + .I0(plm_fsm_reg_state_16__603), + .I1(plm_fsm_ri_timer_reg_count[4]), + .LO(plm_fsm_ri_timer_reg_count_qxu[4]) + ); + defparam plm_fsm_ri_timer_reg_count_qxu_0_5_.INIT = 4'h8; + LUT2_L plm_fsm_ri_timer_reg_count_qxu_0_5_ ( + .I0(plm_fsm_reg_state_16__603), + .I1(plm_fsm_ri_timer_reg_count[5]), + .LO(plm_fsm_ri_timer_reg_count_qxu[5]) + ); + defparam plm_fsm_ri_timer_reg_count_qxu_0_6_.INIT = 4'h8; + LUT2_L plm_fsm_ri_timer_reg_count_qxu_0_6_ ( + .I0(plm_fsm_reg_state_16__603), + .I1(plm_fsm_ri_timer_reg_count[6]), + .LO(plm_fsm_ri_timer_reg_count_qxu[6]) + ); + defparam plm_fsm_ri_timer_reg_count_qxu_0_7_.INIT = 4'h8; + LUT2_L plm_fsm_ri_timer_reg_count_qxu_0_7_ ( + .I0(plm_fsm_reg_state_16__603), + .I1(plm_fsm_ri_timer_reg_count[7]), + .LO(plm_fsm_ri_timer_reg_count_qxu[7]) + ); + defparam plm_fsm_ri_timer_reg_count_qxu_0_8_.INIT = 4'h8; + LUT2_L plm_fsm_ri_timer_reg_count_qxu_0_8_ ( + .I0(plm_fsm_reg_state_16__603), + .I1(plm_fsm_ri_timer_reg_count[8]), + .LO(plm_fsm_ri_timer_reg_count_qxu[8]) + ); + defparam plm_fsm_ri_timer_reg_count_qxu_0_9_.INIT = 4'h8; + LUT2_L plm_fsm_ri_timer_reg_count_qxu_0_9_ ( + .I0(plm_fsm_reg_state_16__603), + .I1(plm_fsm_ri_timer_reg_count[9]), + .LO(plm_fsm_ri_timer_reg_count_qxu[9]) + ); + defparam plm_fsm_ri_timer_reg_count_qxu_0_10_.INIT = 4'h8; + LUT2_L plm_fsm_ri_timer_reg_count_qxu_0_10_ ( + .I0(plm_fsm_reg_state_16__603), + .I1(plm_fsm_ri_timer_reg_count[10]), + .LO(plm_fsm_ri_timer_reg_count_qxu[10]) + ); + defparam plm_fsm_ri_timer_reg_count_qxu_0_11_.INIT = 4'h8; + LUT2_L plm_fsm_ri_timer_reg_count_qxu_0_11_ ( + .I0(plm_fsm_reg_state_16__603), + .I1(plm_fsm_ri_timer_reg_count[11]), + .LO(plm_fsm_ri_timer_reg_count_qxu[11]) + ); + defparam plm_fsm_ri_timer_reg_count_qxu_0_12_.INIT = 4'h8; + LUT2_L plm_fsm_ri_timer_reg_count_qxu_0_12_ ( + .I0(plm_fsm_reg_state_16__603), + .I1(plm_fsm_ri_timer_reg_count[12]), + .LO(plm_fsm_ri_timer_reg_count_qxu[12]) + ); + defparam plm_fsm_ri_timer_reg_count_qxu_0_13_.INIT = 4'h8; + LUT2_L plm_fsm_ri_timer_reg_count_qxu_0_13_ ( + .I0(plm_fsm_reg_state_16__603), + .I1(plm_fsm_ri_timer_reg_count[13]), + .LO(plm_fsm_ri_timer_reg_count_qxu[13]) + ); + defparam plm_fsm_ri_timer_reg_count_qxu_0_14_.INIT = 4'h8; + LUT2_L plm_fsm_ri_timer_reg_count_qxu_0_14_ ( + .I0(plm_fsm_reg_state_16__603), + .I1(plm_fsm_ri_timer_reg_count[14]), + .LO(plm_fsm_ri_timer_reg_count_qxu[14]) + ); + defparam plm_fsm_ri_timer_reg_count_qxu_0_15_.INIT = 4'h8; + LUT2_L plm_fsm_ri_timer_reg_count_qxu_0_15_ ( + .I0(plm_fsm_reg_state_16__603), + .I1(plm_fsm_ri_timer_reg_count[15]), + .LO(plm_fsm_ri_timer_reg_count_qxu[15]) + ); + defparam plm_fsm_ri_timer_reg_count_qxu_0_16_.INIT = 4'h8; + LUT2_L plm_fsm_ri_timer_reg_count_qxu_0_16_ ( + .I0(plm_fsm_reg_state_16__603), + .I1(plm_fsm_ri_timer_reg_count[16]), + .LO(plm_fsm_ri_timer_reg_count_qxu[16]) + ); + defparam plm_fsm_ri_timer_reg_count_qxu_0_17_.INIT = 4'h8; + LUT2_L plm_fsm_ri_timer_reg_count_qxu_0_17_ ( + .I0(plm_fsm_reg_state_16__603), + .I1(plm_fsm_ri_timer_reg_count[17]), + .LO(plm_fsm_ri_timer_reg_count_qxu[17]) + ); + defparam plm_fsm_ri_timer_reg_count_qxu_0_18_.INIT = 4'h8; + LUT2_L plm_fsm_ri_timer_reg_count_qxu_0_18_ ( + .I0(plm_fsm_reg_state_16__603), + .I1(plm_fsm_ri_timer_reg_count[18]), + .LO(plm_fsm_ri_timer_reg_count_qxu[18]) + ); + defparam plm_fsm_ri_timer_reg_count_qxu_0_19_.INIT = 4'h8; + LUT2_L plm_fsm_ri_timer_reg_count_qxu_0_19_ ( + .I0(plm_fsm_reg_state_16__603), + .I1(plm_fsm_ri_timer_reg_count[19]), + .LO(plm_fsm_ri_timer_reg_count_qxu[19]) + ); + defparam plm_fsm_ri_timer_reg_count_qxu_0_20_.INIT = 4'h8; + LUT2_L plm_fsm_ri_timer_reg_count_qxu_0_20_ ( + .I0(plm_fsm_reg_state_16__603), + .I1(plm_fsm_ri_timer_reg_count[20]), + .LO(plm_fsm_ri_timer_reg_count_qxu[20]) + ); + defparam plm_fsm_ri_timer_reg_count_qxu_0_21_.INIT = 4'h8; + LUT2_L plm_fsm_ri_timer_reg_count_qxu_0_21_ ( + .I0(plm_fsm_reg_state_16__603), + .I1(plm_fsm_ri_timer_reg_count[21]), + .LO(plm_fsm_ri_timer_reg_count_qxu[21]) + ); + defparam plm_fsm_ri_timer_reg_count_qxu_0_22_.INIT = 4'h8; + LUT2_L plm_fsm_ri_timer_reg_count_qxu_0_22_ ( + .I0(plm_fsm_reg_state_16__603), + .I1(plm_fsm_ri_timer_reg_count[22]), + .LO(plm_fsm_ri_timer_reg_count_qxu[22]) + ); + VCC plm_fsm_ri_counter0_VCC ( + .P(plm_fsm_ri_counter0_VCC_1992) + ); + MUXCY_L plm_fsm_ri_counter0_reg_rx_count_cry_0_ ( + .CI(N_61092_i_47), + .DI(plm_fsm_ri_counter0_VCC_1992), + .LO(plm_fsm_ri_counter0_reg_rx_count_cry[0]), + .S(plm_fsm_ri_counter0_reg_rx_count_qxu[0]) + ); + XORCY plm_fsm_ri_counter0_reg_rx_count_s_0_ ( + .CI(N_61092_i_47), + .LI(plm_fsm_ri_counter0_reg_rx_count_qxu[0]), + .O(plm_fsm_ri_counter0_reg_rx_count_s[0]) + ); + MUXCY_L plm_fsm_ri_counter0_reg_rx_count_cry_1_ ( + .CI(plm_fsm_ri_counter0_reg_rx_count_cry[0]), + .DI(plm_fsm_ri_counter0_VCC_1992), + .LO(plm_fsm_ri_counter0_reg_rx_count_cry[1]), + .S(plm_fsm_ri_counter0_reg_rx_count_qxu[1]) + ); + XORCY plm_fsm_ri_counter0_reg_rx_count_s_1_ ( + .CI(plm_fsm_ri_counter0_reg_rx_count_cry[0]), + .LI(plm_fsm_ri_counter0_reg_rx_count_qxu[1]), + .O(plm_fsm_ri_counter0_reg_rx_count_s[1]) + ); + MUXCY_L plm_fsm_ri_counter0_reg_rx_count_cry_2_ ( + .CI(plm_fsm_ri_counter0_reg_rx_count_cry[1]), + .DI(plm_fsm_ri_counter0_VCC_1992), + .LO(plm_fsm_ri_counter0_reg_rx_count_cry[2]), + .S(plm_fsm_ri_counter0_reg_rx_count_qxu[2]) + ); + XORCY plm_fsm_ri_counter0_reg_rx_count_s_2_ ( + .CI(plm_fsm_ri_counter0_reg_rx_count_cry[1]), + .LI(plm_fsm_ri_counter0_reg_rx_count_qxu[2]), + .O(plm_fsm_ri_counter0_reg_rx_count_s[2]) + ); + MUXCY_L plm_fsm_ri_counter0_reg_rx_count_cry_3_ ( + .CI(plm_fsm_ri_counter0_reg_rx_count_cry[2]), + .DI(plm_fsm_ri_counter0_VCC_1992), + .LO(plm_fsm_ri_counter0_reg_rx_count_cry[3]), + .S(plm_fsm_ri_counter0_reg_rx_count_qxu[3]) + ); + XORCY plm_fsm_ri_counter0_reg_rx_count_s_3_ ( + .CI(plm_fsm_ri_counter0_reg_rx_count_cry[2]), + .LI(plm_fsm_ri_counter0_reg_rx_count_qxu[3]), + .O(plm_fsm_ri_counter0_reg_rx_count_s[3]) + ); + MUXCY_L plm_fsm_ri_counter0_reg_rx_count_cry_4_ ( + .CI(plm_fsm_ri_counter0_reg_rx_count_cry[3]), + .DI(plm_fsm_ri_counter0_VCC_1992), + .LO(plm_fsm_ri_counter0_reg_rx_count_cry[4]), + .S(plm_fsm_ri_counter0_reg_rx_count_qxu[4]) + ); + XORCY plm_fsm_ri_counter0_reg_rx_count_s_4_ ( + .CI(plm_fsm_ri_counter0_reg_rx_count_cry[3]), + .LI(plm_fsm_ri_counter0_reg_rx_count_qxu[4]), + .O(plm_fsm_ri_counter0_reg_rx_count_s[4]) + ); + MUXCY_L plm_fsm_ri_counter0_reg_rx_count_cry_5_ ( + .CI(plm_fsm_ri_counter0_reg_rx_count_cry[4]), + .DI(plm_fsm_ri_counter0_VCC_1992), + .LO(plm_fsm_ri_counter0_reg_rx_count_cry[5]), + .S(plm_fsm_ri_counter0_reg_rx_count_qxu[5]) + ); + XORCY plm_fsm_ri_counter0_reg_rx_count_s_5_ ( + .CI(plm_fsm_ri_counter0_reg_rx_count_cry[4]), + .LI(plm_fsm_ri_counter0_reg_rx_count_qxu[5]), + .O(plm_fsm_ri_counter0_reg_rx_count_s[5]) + ); + MUXCY_L plm_fsm_ri_counter0_reg_rx_count_cry_6_ ( + .CI(plm_fsm_ri_counter0_reg_rx_count_cry[5]), + .DI(plm_fsm_ri_counter0_VCC_1992), + .LO(plm_fsm_ri_counter0_reg_rx_count_cry[6]), + .S(plm_fsm_ri_counter0_reg_rx_count_qxu[6]) + ); + XORCY plm_fsm_ri_counter0_reg_rx_count_s_6_ ( + .CI(plm_fsm_ri_counter0_reg_rx_count_cry[5]), + .LI(plm_fsm_ri_counter0_reg_rx_count_qxu[6]), + .O(plm_fsm_ri_counter0_reg_rx_count_s[6]) + ); + XORCY plm_fsm_ri_counter0_reg_rx_count_s_7_ ( + .CI(plm_fsm_ri_counter0_reg_rx_count_cry[6]), + .LI(plm_fsm_ri_counter0_reg_rx_count_qxu[7]), + .O(plm_fsm_ri_counter0_reg_rx_count_s[7]) + ); + MUXCY_L plm_fsm_ri_counter0_reg_tx_count_cry_0_ ( + .CI(plm_fsm_ri_counter0_N_61227_i_1993), + .DI(plm_fsm_ri_counter0_VCC_1992), + .LO(plm_fsm_ri_counter0_reg_tx_count_cry[0]), + .S(plm_fsm_ri_counter0_reg_tx_count_qxu[0]) + ); + XORCY plm_fsm_ri_counter0_reg_tx_count_s_0_ ( + .CI(plm_fsm_ri_counter0_N_61227_i_1993), + .LI(plm_fsm_ri_counter0_reg_tx_count_qxu[0]), + .O(plm_fsm_ri_counter0_reg_tx_count_s[0]) + ); + MUXCY_L plm_fsm_ri_counter0_reg_tx_count_cry_1_ ( + .CI(plm_fsm_ri_counter0_reg_tx_count_cry[0]), + .DI(plm_fsm_ri_counter0_VCC_1992), + .LO(plm_fsm_ri_counter0_reg_tx_count_cry[1]), + .S(plm_fsm_ri_counter0_reg_tx_count_qxu[1]) + ); + XORCY plm_fsm_ri_counter0_reg_tx_count_s_1_ ( + .CI(plm_fsm_ri_counter0_reg_tx_count_cry[0]), + .LI(plm_fsm_ri_counter0_reg_tx_count_qxu[1]), + .O(plm_fsm_ri_counter0_reg_tx_count_s[1]) + ); + MUXCY_L plm_fsm_ri_counter0_reg_tx_count_cry_2_ ( + .CI(plm_fsm_ri_counter0_reg_tx_count_cry[1]), + .DI(plm_fsm_ri_counter0_VCC_1992), + .LO(plm_fsm_ri_counter0_reg_tx_count_cry[2]), + .S(plm_fsm_ri_counter0_reg_tx_count_qxu[2]) + ); + XORCY plm_fsm_ri_counter0_reg_tx_count_s_2_ ( + .CI(plm_fsm_ri_counter0_reg_tx_count_cry[1]), + .LI(plm_fsm_ri_counter0_reg_tx_count_qxu[2]), + .O(plm_fsm_ri_counter0_reg_tx_count_s[2]) + ); + MUXCY_L plm_fsm_ri_counter0_reg_tx_count_cry_3_ ( + .CI(plm_fsm_ri_counter0_reg_tx_count_cry[2]), + .DI(plm_fsm_ri_counter0_VCC_1992), + .LO(plm_fsm_ri_counter0_reg_tx_count_cry[3]), + .S(plm_fsm_ri_counter0_reg_tx_count_qxu[3]) + ); + XORCY plm_fsm_ri_counter0_reg_tx_count_s_3_ ( + .CI(plm_fsm_ri_counter0_reg_tx_count_cry[2]), + .LI(plm_fsm_ri_counter0_reg_tx_count_qxu[3]), + .O(plm_fsm_ri_counter0_reg_tx_count_s[3]) + ); + MUXCY_L plm_fsm_ri_counter0_reg_tx_count_cry_4_ ( + .CI(plm_fsm_ri_counter0_reg_tx_count_cry[3]), + .DI(plm_fsm_ri_counter0_VCC_1992), + .LO(plm_fsm_ri_counter0_reg_tx_count_cry[4]), + .S(plm_fsm_ri_counter0_reg_tx_count_qxu[4]) + ); + XORCY plm_fsm_ri_counter0_reg_tx_count_s_4_ ( + .CI(plm_fsm_ri_counter0_reg_tx_count_cry[3]), + .LI(plm_fsm_ri_counter0_reg_tx_count_qxu[4]), + .O(plm_fsm_ri_counter0_reg_tx_count_s[4]) + ); + MUXCY_L plm_fsm_ri_counter0_reg_tx_count_cry_5_ ( + .CI(plm_fsm_ri_counter0_reg_tx_count_cry[4]), + .DI(plm_fsm_ri_counter0_VCC_1992), + .LO(plm_fsm_ri_counter0_reg_tx_count_cry[5]), + .S(plm_fsm_ri_counter0_reg_tx_count_qxu[5]) + ); + XORCY plm_fsm_ri_counter0_reg_tx_count_s_5_ ( + .CI(plm_fsm_ri_counter0_reg_tx_count_cry[4]), + .LI(plm_fsm_ri_counter0_reg_tx_count_qxu[5]), + .O(plm_fsm_ri_counter0_reg_tx_count_s[5]) + ); + MUXCY_L plm_fsm_ri_counter0_reg_tx_count_cry_6_ ( + .CI(plm_fsm_ri_counter0_reg_tx_count_cry[5]), + .DI(plm_fsm_ri_counter0_VCC_1992), + .LO(plm_fsm_ri_counter0_reg_tx_count_cry[6]), + .S(plm_fsm_ri_counter0_reg_tx_count_qxu[6]) + ); + XORCY plm_fsm_ri_counter0_reg_tx_count_s_6_ ( + .CI(plm_fsm_ri_counter0_reg_tx_count_cry[5]), + .LI(plm_fsm_ri_counter0_reg_tx_count_qxu[6]), + .O(plm_fsm_ri_counter0_reg_tx_count_s[6]) + ); + XORCY plm_fsm_ri_counter0_reg_tx_count_s_7_ ( + .CI(plm_fsm_ri_counter0_reg_tx_count_cry[6]), + .LI(plm_fsm_ri_counter0_reg_tx_count_qxu[7]), + .O(plm_fsm_ri_counter0_reg_tx_count_s[7]) + ); + defparam plm_fsm_ri_counter0_oneshot_monitor_un1_enable_0_a2_0_a2_0_a3_0_a2.INIT = 4'h4; + LUT2 plm_fsm_ri_counter0_oneshot_monitor_un1_enable_0_a2_0_a2_0_a3_0_a2 ( + .I0(plm_reg_rx_idl_1), + .I1(plm_fsm_reg_state_16__603), + .O(plm_fsm_ri_counter0_un1_enable_0_a2_0_a2_0_a3_0_a2) + ); + defparam plm_fsm_ri_counter0_loadable_tx_counter_reg_tx_count17_0_a2_0_a2_0_a3_0_a2.INIT = 4'h8; + LUT2 plm_fsm_ri_counter0_loadable_tx_counter_reg_tx_count17_0_a2_0_a2_0_a3_0_a2 ( + .I0(plm_fsm_reg_state_16__603), + .I1(plm_fsm_ri_counter0_reg_oneshot_1995), + .O(plm_fsm_ri_counter0_reg_tx_count17_0_a2_0_a2_0_a3_0_a2_3) + ); + defparam plm_fsm_ri_counter0_un1_enable_1_0_a2_0_a2_0_a3_0_a2.INIT = 4'h2; + LUT2 plm_fsm_ri_counter0_un1_enable_1_0_a2_0_a2_0_a3_0_a2 ( + .I0(plm_fsm_ri_counter0_reg_tx_count17_0_a2_0_a2_0_a3_0_a2_3), + .I1(plm_fsm_ri_counter0_reg_tx_expired_1997), + .O(plm_fsm_ri_counter0_un1_enable_1_0_a2_0_a2_0_a3_0_a2_1) + ); + defparam plm_fsm_ri_counter0_loadable_tx_counter_un1_reg_tx_count_0_a3_4.INIT = 16'h0001; + LUT4 plm_fsm_ri_counter0_loadable_tx_counter_un1_reg_tx_count_0_a3_4 ( + .I0(plm_fsm_ri_counter0_reg_tx_count[0]), + .I1(plm_fsm_ri_counter0_reg_tx_count[1]), + .I2(plm_fsm_ri_counter0_reg_tx_count[2]), + .I3(plm_fsm_ri_counter0_reg_tx_count[3]), + .O(plm_fsm_ri_counter0_un1_reg_tx_count_0_a3_4) + ); + defparam plm_fsm_ri_counter0_loadable_tx_counter_un1_reg_tx_count_0_a3_5.INIT = 16'h0001; + LUT4 plm_fsm_ri_counter0_loadable_tx_counter_un1_reg_tx_count_0_a3_5 ( + .I0(plm_fsm_ri_counter0_reg_tx_count[4]), + .I1(plm_fsm_ri_counter0_reg_tx_count[5]), + .I2(plm_fsm_ri_counter0_reg_tx_count[6]), + .I3(plm_fsm_ri_counter0_reg_tx_count[7]), + .O(plm_fsm_ri_counter0_un1_reg_tx_count_0_a3_5) + ); + defparam plm_fsm_ri_counter0_loadable_rx_counter_un1_reg_rx_count_0_a2_4.INIT = 16'h0001; + LUT4 plm_fsm_ri_counter0_loadable_rx_counter_un1_reg_rx_count_0_a2_4 ( + .I0(plm_fsm_ri_counter0_reg_rx_count[0]), + .I1(plm_fsm_ri_counter0_reg_rx_count[1]), + .I2(plm_fsm_ri_counter0_reg_rx_count[2]), + .I3(plm_fsm_ri_counter0_reg_rx_count[3]), + .O(plm_fsm_ri_counter0_un1_reg_rx_count_0_a2_4) + ); + defparam plm_fsm_ri_counter0_loadable_rx_counter_un1_reg_rx_count_0_a2_5.INIT = 16'h0001; + LUT4 plm_fsm_ri_counter0_loadable_rx_counter_un1_reg_rx_count_0_a2_5 ( + .I0(plm_fsm_ri_counter0_reg_rx_count[4]), + .I1(plm_fsm_ri_counter0_reg_rx_count[5]), + .I2(plm_fsm_ri_counter0_reg_rx_count[6]), + .I3(plm_fsm_ri_counter0_reg_rx_count[7]), + .O(plm_fsm_ri_counter0_un1_reg_rx_count_0_a2_5) + ); + defparam plm_fsm_ri_counter0_N_87177_i.INIT = 8'h3B; + LUT3_L plm_fsm_ri_counter0_N_87177_i ( + .I0(plm_fsm_N_58718_1), + .I1(plm_fsm_reg_state_16__603), + .I2(plm_fsm_ri_counter0_reg_rx_expired_611), + .LO(plm_fsm_ri_counter0_N_87177_i_1998) + ); + defparam plm_fsm_ri_counter0_N_61097_i.INIT = 4'hB; + LUT2 plm_fsm_ri_counter0_N_61097_i ( + .I0(plm_reg_sym_sent_0_), + .I1(plm_fsm_ri_counter0_un1_enable_1_0_a2_0_a2_0_a3_0_a2_1), + .O(plm_fsm_ri_counter0_N_61097_i_1994) + ); + defparam plm_fsm_ri_counter0_N_61055_i.INIT = 8'hD5; + LUT3 plm_fsm_ri_counter0_N_61055_i ( + .I0(plm_fsm_ri_counter0_reg_tx_count17_0_a2_0_a2_0_a3_0_a2_3), + .I1(plm_fsm_ri_counter0_un1_reg_tx_count_0_a3_4), + .I2(plm_fsm_ri_counter0_un1_reg_tx_count_0_a3_5), + .O(plm_fsm_ri_counter0_N_61055_i_1996) + ); + defparam plm_fsm_ri_counter0_loadable_rx_counter_N_61146_i.INIT = 8'hD5; + LUT3 plm_fsm_ri_counter0_loadable_rx_counter_N_61146_i ( + .I0(plm_fsm_reg_state_16__603), + .I1(plm_fsm_ri_counter0_un1_reg_rx_count_0_a2_4), + .I2(plm_fsm_ri_counter0_un1_reg_rx_count_0_a2_5), + .O(plm_fsm_ri_counter0_N_61146_i) + ); + defparam plm_fsm_ri_counter0_flagit_reg_expired_5_0_a2_0_a3_0_a2.INIT = 8'h80; + LUT3_L plm_fsm_ri_counter0_flagit_reg_expired_5_0_a2_0_a3_0_a2 ( + .I0(plm_fsm_reg_state_16__603), + .I1(plm_fsm_ri_counter0_reg_rx_expired_611), + .I2(plm_fsm_ri_counter0_reg_tx_expired_1997), + .LO(plm_fsm_ri_counter0_reg_expired_5) + ); + defparam plm_fsm_ri_counter0_loadable_rx_counter_N_61101_i.INIT = 8'hFB; + LUT3 plm_fsm_ri_counter0_loadable_rx_counter_N_61101_i ( + .I0(plm_fsm_ri_counter0_reg_rx_expired_611), + .I1(plm_fsm_reg_state_16__603), + .I2(plm_reg_rx_idl_1), + .O(plm_fsm_ri_counter0_N_61101_i) + ); + defparam plm_fsm_ri_counter0_N_61227_i.INIT = 4'hB; + LUT2 plm_fsm_ri_counter0_N_61227_i ( + .I0(plm_fsm_ri_counter0_reg_tx_expired_1997), + .I1(plm_fsm_ri_counter0_reg_tx_count17_0_a2_0_a2_0_a3_0_a2_3), + .O(plm_fsm_ri_counter0_N_61227_i_1993) + ); + FDCE plm_fsm_ri_counter0_reg_tx_count_7_ ( + .CE(plm_fsm_ri_counter0_N_61097_i_1994), + .C(mgt_clk), + .D(plm_fsm_ri_counter0_reg_tx_count_s[7]), + .Q(plm_fsm_ri_counter0_reg_tx_count[7]), + .CLR(plm_rst) + ); + FDCE plm_fsm_ri_counter0_reg_tx_count_6_ ( + .CE(plm_fsm_ri_counter0_N_61097_i_1994), + .C(mgt_clk), + .D(plm_fsm_ri_counter0_reg_tx_count_s[6]), + .Q(plm_fsm_ri_counter0_reg_tx_count[6]), + .CLR(plm_rst) + ); + FDCE plm_fsm_ri_counter0_reg_tx_count_5_ ( + .CE(plm_fsm_ri_counter0_N_61097_i_1994), + .C(mgt_clk), + .D(plm_fsm_ri_counter0_reg_tx_count_s[5]), + .Q(plm_fsm_ri_counter0_reg_tx_count[5]), + .CLR(plm_rst) + ); + FDCE plm_fsm_ri_counter0_reg_tx_count_4_ ( + .CE(plm_fsm_ri_counter0_N_61097_i_1994), + .C(mgt_clk), + .D(plm_fsm_ri_counter0_reg_tx_count_s[4]), + .Q(plm_fsm_ri_counter0_reg_tx_count[4]), + .CLR(plm_rst) + ); + FDPE plm_fsm_ri_counter0_reg_tx_count_3_ ( + .PRE(plm_rst), + .CE(plm_fsm_ri_counter0_N_61097_i_1994), + .C(mgt_clk), + .D(plm_fsm_ri_counter0_reg_tx_count_s[3]), + .Q(plm_fsm_ri_counter0_reg_tx_count[3]) + ); + FDCE plm_fsm_ri_counter0_reg_tx_count_2_ ( + .CE(plm_fsm_ri_counter0_N_61097_i_1994), + .C(mgt_clk), + .D(plm_fsm_ri_counter0_reg_tx_count_s[2]), + .Q(plm_fsm_ri_counter0_reg_tx_count[2]), + .CLR(plm_rst) + ); + FDCE plm_fsm_ri_counter0_reg_tx_count_1_ ( + .CE(plm_fsm_ri_counter0_N_61097_i_1994), + .C(mgt_clk), + .D(plm_fsm_ri_counter0_reg_tx_count_s[1]), + .Q(plm_fsm_ri_counter0_reg_tx_count[1]), + .CLR(plm_rst) + ); + FDCE plm_fsm_ri_counter0_reg_tx_count_0_ ( + .CE(plm_fsm_ri_counter0_N_61097_i_1994), + .C(mgt_clk), + .D(plm_fsm_ri_counter0_reg_tx_count_s[0]), + .Q(plm_fsm_ri_counter0_reg_tx_count[0]), + .CLR(plm_rst) + ); + FDCE plm_fsm_ri_counter0_reg_rx_count_7_ ( + .CE(plm_fsm_ri_counter0_N_61101_i), + .C(mgt_clk), + .D(plm_fsm_ri_counter0_reg_rx_count_s[7]), + .Q(plm_fsm_ri_counter0_reg_rx_count[7]), + .CLR(plm_rst) + ); + FDCE plm_fsm_ri_counter0_reg_rx_count_6_ ( + .CE(plm_fsm_ri_counter0_N_61101_i), + .C(mgt_clk), + .D(plm_fsm_ri_counter0_reg_rx_count_s[6]), + .Q(plm_fsm_ri_counter0_reg_rx_count[6]), + .CLR(plm_rst) + ); + FDCE plm_fsm_ri_counter0_reg_rx_count_5_ ( + .CE(plm_fsm_ri_counter0_N_61101_i), + .C(mgt_clk), + .D(plm_fsm_ri_counter0_reg_rx_count_s[5]), + .Q(plm_fsm_ri_counter0_reg_rx_count[5]), + .CLR(plm_rst) + ); + FDCE plm_fsm_ri_counter0_reg_rx_count_4_ ( + .CE(plm_fsm_ri_counter0_N_61101_i), + .C(mgt_clk), + .D(plm_fsm_ri_counter0_reg_rx_count_s[4]), + .Q(plm_fsm_ri_counter0_reg_rx_count[4]), + .CLR(plm_rst) + ); + FDCE plm_fsm_ri_counter0_reg_rx_count_3_ ( + .CE(plm_fsm_ri_counter0_N_61101_i), + .C(mgt_clk), + .D(plm_fsm_ri_counter0_reg_rx_count_s[3]), + .Q(plm_fsm_ri_counter0_reg_rx_count[3]), + .CLR(plm_rst) + ); + FDPE plm_fsm_ri_counter0_reg_rx_count_2_ ( + .PRE(plm_rst), + .CE(plm_fsm_ri_counter0_N_61101_i), + .C(mgt_clk), + .D(plm_fsm_ri_counter0_reg_rx_count_s[2]), + .Q(plm_fsm_ri_counter0_reg_rx_count[2]) + ); + FDCE plm_fsm_ri_counter0_reg_rx_count_1_ ( + .CE(plm_fsm_ri_counter0_N_61101_i), + .C(mgt_clk), + .D(plm_fsm_ri_counter0_reg_rx_count_s[1]), + .Q(plm_fsm_ri_counter0_reg_rx_count[1]), + .CLR(plm_rst) + ); + FDCE plm_fsm_ri_counter0_reg_rx_count_0_ ( + .CE(plm_fsm_ri_counter0_N_61101_i), + .C(mgt_clk), + .D(plm_fsm_ri_counter0_reg_rx_count_s[0]), + .Q(plm_fsm_ri_counter0_reg_rx_count[0]), + .CLR(plm_rst) + ); + FDC plm_fsm_ri_counter0_reg_expired ( + .C(mgt_clk), + .D(plm_fsm_ri_counter0_reg_expired_5), + .Q(plm_fsm_ri_cntrout0), + .CLR(plm_rst) + ); + FDCE plm_fsm_ri_counter0_reg_oneshot ( + .CE(plm_fsm_ri_counter0_N_61222_i), + .C(mgt_clk), + .D(plm_fsm_reg_state_16__603), + .Q(plm_fsm_ri_counter0_reg_oneshot_1995), + .CLR(plm_rst) + ); + FDCE plm_fsm_ri_counter0_reg_rx_expired ( + .CE(plm_fsm_ri_counter0_N_61146_i), + .C(mgt_clk), + .D(plm_fsm_reg_state_16__603), + .Q(plm_fsm_ri_counter0_reg_rx_expired_611), + .CLR(plm_rst) + ); + FDCE plm_fsm_ri_counter0_reg_tx_expired ( + .CE(plm_fsm_ri_counter0_N_61055_i_1996), + .C(mgt_clk), + .D(plm_fsm_ri_counter0_reg_tx_count17_0_a2_0_a2_0_a3_0_a2_3), + .Q(plm_fsm_ri_counter0_reg_tx_expired_1997), + .CLR(plm_rst) + ); + INV plm_fsm_ri_counter0_oneshot_monitor_N_61222_i ( + .I(plm_fsm_ri_counter0_un1_enable_0_a2_0_a2_0_a3_0_a2), + .O(plm_fsm_ri_counter0_N_61222_i) + ); + defparam plm_fsm_ri_counter0_reg_rx_count_qxu_0_0_.INIT = 4'h7; + LUT2_L plm_fsm_ri_counter0_reg_rx_count_qxu_0_0_ ( + .I0(I_5377_0_a2_0_a2_0_a3_0_a2_46), + .I1(plm_fsm_ri_counter0_reg_rx_count[0]), + .LO(plm_fsm_ri_counter0_reg_rx_count_qxu[0]) + ); + defparam plm_fsm_ri_counter0_reg_rx_count_qxu_0_1_.INIT = 4'h7; + LUT2_L plm_fsm_ri_counter0_reg_rx_count_qxu_0_1_ ( + .I0(I_5377_0_a2_0_a2_0_a3_0_a2_46), + .I1(plm_fsm_ri_counter0_reg_rx_count[1]), + .LO(plm_fsm_ri_counter0_reg_rx_count_qxu[1]) + ); + defparam plm_fsm_ri_counter0_reg_rx_count_qxu_0_2_.INIT = 8'h1B; + LUT3_L plm_fsm_ri_counter0_reg_rx_count_qxu_0_2_ ( + .I0(I_5377_0_a2_0_a2_0_a3_0_a2_46), + .I1(plm_fsm_ri_counter0_N_87177_i_1998), + .I2(plm_fsm_ri_counter0_reg_rx_count[2]), + .LO(plm_fsm_ri_counter0_reg_rx_count_qxu[2]) + ); + defparam plm_fsm_ri_counter0_reg_rx_count_qxu_0_3_.INIT = 4'h7; + LUT2_L plm_fsm_ri_counter0_reg_rx_count_qxu_0_3_ ( + .I0(I_5377_0_a2_0_a2_0_a3_0_a2_46), + .I1(plm_fsm_ri_counter0_reg_rx_count[3]), + .LO(plm_fsm_ri_counter0_reg_rx_count_qxu[3]) + ); + defparam plm_fsm_ri_counter0_reg_rx_count_qxu_0_4_.INIT = 4'h7; + LUT2_L plm_fsm_ri_counter0_reg_rx_count_qxu_0_4_ ( + .I0(I_5377_0_a2_0_a2_0_a3_0_a2_46), + .I1(plm_fsm_ri_counter0_reg_rx_count[4]), + .LO(plm_fsm_ri_counter0_reg_rx_count_qxu[4]) + ); + defparam plm_fsm_ri_counter0_reg_rx_count_qxu_0_5_.INIT = 4'h7; + LUT2_L plm_fsm_ri_counter0_reg_rx_count_qxu_0_5_ ( + .I0(I_5377_0_a2_0_a2_0_a3_0_a2_46), + .I1(plm_fsm_ri_counter0_reg_rx_count[5]), + .LO(plm_fsm_ri_counter0_reg_rx_count_qxu[5]) + ); + defparam plm_fsm_ri_counter0_reg_rx_count_qxu_0_6_.INIT = 4'h7; + LUT2_L plm_fsm_ri_counter0_reg_rx_count_qxu_0_6_ ( + .I0(I_5377_0_a2_0_a2_0_a3_0_a2_46), + .I1(plm_fsm_ri_counter0_reg_rx_count[6]), + .LO(plm_fsm_ri_counter0_reg_rx_count_qxu[6]) + ); + defparam plm_fsm_ri_counter0_reg_rx_count_qxu_0_7_.INIT = 4'h7; + LUT2_L plm_fsm_ri_counter0_reg_rx_count_qxu_0_7_ ( + .I0(I_5377_0_a2_0_a2_0_a3_0_a2_46), + .I1(plm_fsm_ri_counter0_reg_rx_count[7]), + .LO(plm_fsm_ri_counter0_reg_rx_count_qxu[7]) + ); + defparam plm_fsm_ri_counter0_reg_tx_count_qxu_0_0_.INIT = 4'h7; + LUT2_L plm_fsm_ri_counter0_reg_tx_count_qxu_0_0_ ( + .I0(plm_fsm_ri_counter0_un1_enable_1_0_a2_0_a2_0_a3_0_a2_1), + .I1(plm_fsm_ri_counter0_reg_tx_count[0]), + .LO(plm_fsm_ri_counter0_reg_tx_count_qxu[0]) + ); + defparam plm_fsm_ri_counter0_reg_tx_count_qxu_0_1_.INIT = 4'h7; + LUT2_L plm_fsm_ri_counter0_reg_tx_count_qxu_0_1_ ( + .I0(plm_fsm_ri_counter0_un1_enable_1_0_a2_0_a2_0_a3_0_a2_1), + .I1(plm_fsm_ri_counter0_reg_tx_count[1]), + .LO(plm_fsm_ri_counter0_reg_tx_count_qxu[1]) + ); + defparam plm_fsm_ri_counter0_reg_tx_count_qxu_0_2_.INIT = 4'h7; + LUT2_L plm_fsm_ri_counter0_reg_tx_count_qxu_0_2_ ( + .I0(plm_fsm_ri_counter0_un1_enable_1_0_a2_0_a2_0_a3_0_a2_1), + .I1(plm_fsm_ri_counter0_reg_tx_count[2]), + .LO(plm_fsm_ri_counter0_reg_tx_count_qxu[2]) + ); + defparam plm_fsm_ri_counter0_reg_tx_count_qxu_0_3_.INIT = 8'h2E; + LUT3_L plm_fsm_ri_counter0_reg_tx_count_qxu_0_3_ ( + .I0(plm_fsm_ri_counter0_reg_tx_count17_0_a2_0_a2_0_a3_0_a2_3), + .I1(plm_fsm_ri_counter0_un1_enable_1_0_a2_0_a2_0_a3_0_a2_1), + .I2(plm_fsm_ri_counter0_reg_tx_count[3]), + .LO(plm_fsm_ri_counter0_reg_tx_count_qxu[3]) + ); + defparam plm_fsm_ri_counter0_reg_tx_count_qxu_0_4_.INIT = 4'h7; + LUT2_L plm_fsm_ri_counter0_reg_tx_count_qxu_0_4_ ( + .I0(plm_fsm_ri_counter0_un1_enable_1_0_a2_0_a2_0_a3_0_a2_1), + .I1(plm_fsm_ri_counter0_reg_tx_count[4]), + .LO(plm_fsm_ri_counter0_reg_tx_count_qxu[4]) + ); + defparam plm_fsm_ri_counter0_reg_tx_count_qxu_0_5_.INIT = 4'h7; + LUT2_L plm_fsm_ri_counter0_reg_tx_count_qxu_0_5_ ( + .I0(plm_fsm_ri_counter0_un1_enable_1_0_a2_0_a2_0_a3_0_a2_1), + .I1(plm_fsm_ri_counter0_reg_tx_count[5]), + .LO(plm_fsm_ri_counter0_reg_tx_count_qxu[5]) + ); + defparam plm_fsm_ri_counter0_reg_tx_count_qxu_0_6_.INIT = 4'h7; + LUT2_L plm_fsm_ri_counter0_reg_tx_count_qxu_0_6_ ( + .I0(plm_fsm_ri_counter0_un1_enable_1_0_a2_0_a2_0_a3_0_a2_1), + .I1(plm_fsm_ri_counter0_reg_tx_count[6]), + .LO(plm_fsm_ri_counter0_reg_tx_count_qxu[6]) + ); + defparam plm_fsm_ri_counter0_reg_tx_count_qxu_0_7_.INIT = 4'h7; + LUT2_L plm_fsm_ri_counter0_reg_tx_count_qxu_0_7_ ( + .I0(plm_fsm_ri_counter0_un1_enable_1_0_a2_0_a2_0_a3_0_a2_1), + .I1(plm_fsm_ri_counter0_reg_tx_count[7]), + .LO(plm_fsm_ri_counter0_reg_tx_count_qxu[7]) + ); + VCC plm_fsm_ri_counter1_VCC ( + .P(plm_fsm_ri_counter1_VCC_1999) + ); + MUXCY_L plm_fsm_ri_counter1_reg_rx_count_cry_0_ ( + .CI(N_61137_i_49), + .DI(plm_fsm_ri_counter1_VCC_1999), + .LO(plm_fsm_ri_counter1_reg_rx_count_cry[0]), + .S(plm_fsm_ri_counter1_reg_rx_count_qxu[0]) + ); + XORCY plm_fsm_ri_counter1_reg_rx_count_s_0_ ( + .CI(N_61137_i_49), + .LI(plm_fsm_ri_counter1_reg_rx_count_qxu[0]), + .O(plm_fsm_ri_counter1_reg_rx_count_s[0]) + ); + MUXCY_L plm_fsm_ri_counter1_reg_rx_count_cry_1_ ( + .CI(plm_fsm_ri_counter1_reg_rx_count_cry[0]), + .DI(plm_fsm_ri_counter1_VCC_1999), + .LO(plm_fsm_ri_counter1_reg_rx_count_cry[1]), + .S(plm_fsm_ri_counter1_reg_rx_count_qxu[1]) + ); + XORCY plm_fsm_ri_counter1_reg_rx_count_s_1_ ( + .CI(plm_fsm_ri_counter1_reg_rx_count_cry[0]), + .LI(plm_fsm_ri_counter1_reg_rx_count_qxu[1]), + .O(plm_fsm_ri_counter1_reg_rx_count_s[1]) + ); + MUXCY_L plm_fsm_ri_counter1_reg_rx_count_cry_2_ ( + .CI(plm_fsm_ri_counter1_reg_rx_count_cry[1]), + .DI(plm_fsm_ri_counter1_VCC_1999), + .LO(plm_fsm_ri_counter1_reg_rx_count_cry[2]), + .S(plm_fsm_ri_counter1_reg_rx_count_qxu[2]) + ); + XORCY plm_fsm_ri_counter1_reg_rx_count_s_2_ ( + .CI(plm_fsm_ri_counter1_reg_rx_count_cry[1]), + .LI(plm_fsm_ri_counter1_reg_rx_count_qxu[2]), + .O(plm_fsm_ri_counter1_reg_rx_count_s[2]) + ); + MUXCY_L plm_fsm_ri_counter1_reg_rx_count_cry_3_ ( + .CI(plm_fsm_ri_counter1_reg_rx_count_cry[2]), + .DI(plm_fsm_ri_counter1_VCC_1999), + .LO(plm_fsm_ri_counter1_reg_rx_count_cry[3]), + .S(plm_fsm_ri_counter1_reg_rx_count_qxu[3]) + ); + XORCY plm_fsm_ri_counter1_reg_rx_count_s_3_ ( + .CI(plm_fsm_ri_counter1_reg_rx_count_cry[2]), + .LI(plm_fsm_ri_counter1_reg_rx_count_qxu[3]), + .O(plm_fsm_ri_counter1_reg_rx_count_s[3]) + ); + MUXCY_L plm_fsm_ri_counter1_reg_rx_count_cry_4_ ( + .CI(plm_fsm_ri_counter1_reg_rx_count_cry[3]), + .DI(plm_fsm_ri_counter1_VCC_1999), + .LO(plm_fsm_ri_counter1_reg_rx_count_cry[4]), + .S(plm_fsm_ri_counter1_reg_rx_count_qxu[4]) + ); + XORCY plm_fsm_ri_counter1_reg_rx_count_s_4_ ( + .CI(plm_fsm_ri_counter1_reg_rx_count_cry[3]), + .LI(plm_fsm_ri_counter1_reg_rx_count_qxu[4]), + .O(plm_fsm_ri_counter1_reg_rx_count_s[4]) + ); + MUXCY_L plm_fsm_ri_counter1_reg_rx_count_cry_5_ ( + .CI(plm_fsm_ri_counter1_reg_rx_count_cry[4]), + .DI(plm_fsm_ri_counter1_VCC_1999), + .LO(plm_fsm_ri_counter1_reg_rx_count_cry[5]), + .S(plm_fsm_ri_counter1_reg_rx_count_qxu[5]) + ); + XORCY plm_fsm_ri_counter1_reg_rx_count_s_5_ ( + .CI(plm_fsm_ri_counter1_reg_rx_count_cry[4]), + .LI(plm_fsm_ri_counter1_reg_rx_count_qxu[5]), + .O(plm_fsm_ri_counter1_reg_rx_count_s[5]) + ); + MUXCY_L plm_fsm_ri_counter1_reg_rx_count_cry_6_ ( + .CI(plm_fsm_ri_counter1_reg_rx_count_cry[5]), + .DI(plm_fsm_ri_counter1_VCC_1999), + .LO(plm_fsm_ri_counter1_reg_rx_count_cry[6]), + .S(plm_fsm_ri_counter1_reg_rx_count_qxu[6]) + ); + XORCY plm_fsm_ri_counter1_reg_rx_count_s_6_ ( + .CI(plm_fsm_ri_counter1_reg_rx_count_cry[5]), + .LI(plm_fsm_ri_counter1_reg_rx_count_qxu[6]), + .O(plm_fsm_ri_counter1_reg_rx_count_s[6]) + ); + XORCY plm_fsm_ri_counter1_reg_rx_count_s_7_ ( + .CI(plm_fsm_ri_counter1_reg_rx_count_cry[6]), + .LI(plm_fsm_ri_counter1_reg_rx_count_qxu[7]), + .O(plm_fsm_ri_counter1_reg_rx_count_s[7]) + ); + MUXCY_L plm_fsm_ri_counter1_reg_tx_count_cry_0_ ( + .CI(plm_fsm_ri_counter1_N_61228_i_2000), + .DI(plm_fsm_ri_counter1_VCC_1999), + .LO(plm_fsm_ri_counter1_reg_tx_count_cry[0]), + .S(plm_fsm_ri_counter1_reg_tx_count_qxu[0]) + ); + XORCY plm_fsm_ri_counter1_reg_tx_count_s_0_ ( + .CI(plm_fsm_ri_counter1_N_61228_i_2000), + .LI(plm_fsm_ri_counter1_reg_tx_count_qxu[0]), + .O(plm_fsm_ri_counter1_reg_tx_count_s[0]) + ); + MUXCY_L plm_fsm_ri_counter1_reg_tx_count_cry_1_ ( + .CI(plm_fsm_ri_counter1_reg_tx_count_cry[0]), + .DI(plm_fsm_ri_counter1_VCC_1999), + .LO(plm_fsm_ri_counter1_reg_tx_count_cry[1]), + .S(plm_fsm_ri_counter1_reg_tx_count_qxu[1]) + ); + XORCY plm_fsm_ri_counter1_reg_tx_count_s_1_ ( + .CI(plm_fsm_ri_counter1_reg_tx_count_cry[0]), + .LI(plm_fsm_ri_counter1_reg_tx_count_qxu[1]), + .O(plm_fsm_ri_counter1_reg_tx_count_s[1]) + ); + MUXCY_L plm_fsm_ri_counter1_reg_tx_count_cry_2_ ( + .CI(plm_fsm_ri_counter1_reg_tx_count_cry[1]), + .DI(plm_fsm_ri_counter1_VCC_1999), + .LO(plm_fsm_ri_counter1_reg_tx_count_cry[2]), + .S(plm_fsm_ri_counter1_reg_tx_count_qxu[2]) + ); + XORCY plm_fsm_ri_counter1_reg_tx_count_s_2_ ( + .CI(plm_fsm_ri_counter1_reg_tx_count_cry[1]), + .LI(plm_fsm_ri_counter1_reg_tx_count_qxu[2]), + .O(plm_fsm_ri_counter1_reg_tx_count_s[2]) + ); + MUXCY_L plm_fsm_ri_counter1_reg_tx_count_cry_3_ ( + .CI(plm_fsm_ri_counter1_reg_tx_count_cry[2]), + .DI(plm_fsm_ri_counter1_VCC_1999), + .LO(plm_fsm_ri_counter1_reg_tx_count_cry[3]), + .S(plm_fsm_ri_counter1_reg_tx_count_qxu[3]) + ); + XORCY plm_fsm_ri_counter1_reg_tx_count_s_3_ ( + .CI(plm_fsm_ri_counter1_reg_tx_count_cry[2]), + .LI(plm_fsm_ri_counter1_reg_tx_count_qxu[3]), + .O(plm_fsm_ri_counter1_reg_tx_count_s[3]) + ); + MUXCY_L plm_fsm_ri_counter1_reg_tx_count_cry_4_ ( + .CI(plm_fsm_ri_counter1_reg_tx_count_cry[3]), + .DI(plm_fsm_ri_counter1_VCC_1999), + .LO(plm_fsm_ri_counter1_reg_tx_count_cry[4]), + .S(plm_fsm_ri_counter1_reg_tx_count_qxu[4]) + ); + XORCY plm_fsm_ri_counter1_reg_tx_count_s_4_ ( + .CI(plm_fsm_ri_counter1_reg_tx_count_cry[3]), + .LI(plm_fsm_ri_counter1_reg_tx_count_qxu[4]), + .O(plm_fsm_ri_counter1_reg_tx_count_s[4]) + ); + MUXCY_L plm_fsm_ri_counter1_reg_tx_count_cry_5_ ( + .CI(plm_fsm_ri_counter1_reg_tx_count_cry[4]), + .DI(plm_fsm_ri_counter1_VCC_1999), + .LO(plm_fsm_ri_counter1_reg_tx_count_cry[5]), + .S(plm_fsm_ri_counter1_reg_tx_count_qxu[5]) + ); + XORCY plm_fsm_ri_counter1_reg_tx_count_s_5_ ( + .CI(plm_fsm_ri_counter1_reg_tx_count_cry[4]), + .LI(plm_fsm_ri_counter1_reg_tx_count_qxu[5]), + .O(plm_fsm_ri_counter1_reg_tx_count_s[5]) + ); + MUXCY_L plm_fsm_ri_counter1_reg_tx_count_cry_6_ ( + .CI(plm_fsm_ri_counter1_reg_tx_count_cry[5]), + .DI(plm_fsm_ri_counter1_VCC_1999), + .LO(plm_fsm_ri_counter1_reg_tx_count_cry[6]), + .S(plm_fsm_ri_counter1_reg_tx_count_qxu[6]) + ); + XORCY plm_fsm_ri_counter1_reg_tx_count_s_6_ ( + .CI(plm_fsm_ri_counter1_reg_tx_count_cry[5]), + .LI(plm_fsm_ri_counter1_reg_tx_count_qxu[6]), + .O(plm_fsm_ri_counter1_reg_tx_count_s[6]) + ); + XORCY plm_fsm_ri_counter1_reg_tx_count_s_7_ ( + .CI(plm_fsm_ri_counter1_reg_tx_count_cry[6]), + .LI(plm_fsm_ri_counter1_reg_tx_count_qxu[7]), + .O(plm_fsm_ri_counter1_reg_tx_count_s[7]) + ); + defparam plm_fsm_ri_counter1_oneshot_monitor_un1_enable_0_a2_0_a2_0_a3_0_a2.INIT = 4'h4; + LUT2 plm_fsm_ri_counter1_oneshot_monitor_un1_enable_0_a2_0_a2_0_a3_0_a2 ( + .I0(plm_reg_rx_idl_1_0), + .I1(plm_fsm_reg_state_16__603), + .O(plm_fsm_ri_counter1_un1_enable_0_a2_0_a2_0_a3_0_a2_1) + ); + defparam plm_fsm_ri_counter1_loadable_tx_counter_reg_tx_count17_0_a2_0_a2_0_a3_0_a2.INIT = 4'h8; + LUT2 plm_fsm_ri_counter1_loadable_tx_counter_reg_tx_count17_0_a2_0_a2_0_a3_0_a2 ( + .I0(plm_fsm_reg_state_16__603), + .I1(plm_fsm_ri_counter1_reg_oneshot_2002), + .O(plm_fsm_ri_counter1_reg_tx_count17_0_a2_0_a2_0_a3_0_a2) + ); + defparam plm_fsm_ri_counter1_un1_enable_1_0_a2_0_a2_0_a3_0_a2.INIT = 4'h2; + LUT2 plm_fsm_ri_counter1_un1_enable_1_0_a2_0_a2_0_a3_0_a2 ( + .I0(plm_fsm_ri_counter1_reg_tx_count17_0_a2_0_a2_0_a3_0_a2), + .I1(plm_fsm_ri_counter1_reg_tx_expired_2004), + .O(plm_fsm_ri_counter1_un1_enable_1_0_a2_0_a2_0_a3_0_a2_0) + ); + defparam plm_fsm_ri_counter1_loadable_tx_counter_un1_reg_tx_count_0_a2_4.INIT = 16'h0001; + LUT4 plm_fsm_ri_counter1_loadable_tx_counter_un1_reg_tx_count_0_a2_4 ( + .I0(plm_fsm_ri_counter1_reg_tx_count[0]), + .I1(plm_fsm_ri_counter1_reg_tx_count[1]), + .I2(plm_fsm_ri_counter1_reg_tx_count[2]), + .I3(plm_fsm_ri_counter1_reg_tx_count[3]), + .O(plm_fsm_ri_counter1_un1_reg_tx_count_0_a2_4) + ); + defparam plm_fsm_ri_counter1_loadable_tx_counter_un1_reg_tx_count_0_a2_5.INIT = 16'h0001; + LUT4 plm_fsm_ri_counter1_loadable_tx_counter_un1_reg_tx_count_0_a2_5 ( + .I0(plm_fsm_ri_counter1_reg_tx_count[4]), + .I1(plm_fsm_ri_counter1_reg_tx_count[5]), + .I2(plm_fsm_ri_counter1_reg_tx_count[6]), + .I3(plm_fsm_ri_counter1_reg_tx_count[7]), + .O(plm_fsm_ri_counter1_un1_reg_tx_count_0_a2_5) + ); + defparam plm_fsm_ri_counter1_loadable_rx_counter_un1_reg_rx_count_0_a2_4.INIT = 16'h0001; + LUT4 plm_fsm_ri_counter1_loadable_rx_counter_un1_reg_rx_count_0_a2_4 ( + .I0(plm_fsm_ri_counter1_reg_rx_count[0]), + .I1(plm_fsm_ri_counter1_reg_rx_count[1]), + .I2(plm_fsm_ri_counter1_reg_rx_count[2]), + .I3(plm_fsm_ri_counter1_reg_rx_count[3]), + .O(plm_fsm_ri_counter1_un1_reg_rx_count_0_a2_4) + ); + defparam plm_fsm_ri_counter1_loadable_rx_counter_un1_reg_rx_count_0_a2_5.INIT = 16'h0001; + LUT4 plm_fsm_ri_counter1_loadable_rx_counter_un1_reg_rx_count_0_a2_5 ( + .I0(plm_fsm_ri_counter1_reg_rx_count[4]), + .I1(plm_fsm_ri_counter1_reg_rx_count[5]), + .I2(plm_fsm_ri_counter1_reg_rx_count[6]), + .I3(plm_fsm_ri_counter1_reg_rx_count[7]), + .O(plm_fsm_ri_counter1_un1_reg_rx_count_0_a2_5) + ); + defparam plm_fsm_ri_counter1_N_87176_i.INIT = 8'h3B; + LUT3_L plm_fsm_ri_counter1_N_87176_i ( + .I0(plm_fsm_N_58717_1), + .I1(plm_fsm_reg_state_16__603), + .I2(plm_fsm_ri_counter1_reg_rx_expired_606), + .LO(plm_fsm_ri_counter1_N_87176_i_2005) + ); + defparam plm_fsm_ri_counter1_N_61098_i.INIT = 4'hB; + LUT2 plm_fsm_ri_counter1_N_61098_i ( + .I0(plm_reg_sym_sent_0_), + .I1(plm_fsm_ri_counter1_un1_enable_1_0_a2_0_a2_0_a3_0_a2_0), + .O(plm_fsm_ri_counter1_N_61098_i_2001) + ); + defparam plm_fsm_ri_counter1_N_61062_i.INIT = 8'hD5; + LUT3 plm_fsm_ri_counter1_N_61062_i ( + .I0(plm_fsm_ri_counter1_reg_tx_count17_0_a2_0_a2_0_a3_0_a2), + .I1(plm_fsm_ri_counter1_un1_reg_tx_count_0_a2_4), + .I2(plm_fsm_ri_counter1_un1_reg_tx_count_0_a2_5), + .O(plm_fsm_ri_counter1_N_61062_i_2003) + ); + defparam plm_fsm_ri_counter1_loadable_rx_counter_N_61144_i.INIT = 8'hD5; + LUT3 plm_fsm_ri_counter1_loadable_rx_counter_N_61144_i ( + .I0(plm_fsm_reg_state_16__603), + .I1(plm_fsm_ri_counter1_un1_reg_rx_count_0_a2_4), + .I2(plm_fsm_ri_counter1_un1_reg_rx_count_0_a2_5), + .O(plm_fsm_ri_counter1_N_61144_i) + ); + defparam plm_fsm_ri_counter1_flagit_reg_expired_5_0_a2_0_a2_0_a3_0_a2.INIT = 8'h80; + LUT3_L plm_fsm_ri_counter1_flagit_reg_expired_5_0_a2_0_a2_0_a3_0_a2 ( + .I0(plm_fsm_reg_state_16__603), + .I1(plm_fsm_ri_counter1_reg_rx_expired_606), + .I2(plm_fsm_ri_counter1_reg_tx_expired_2004), + .LO(plm_fsm_ri_counter1_reg_expired_5) + ); + defparam plm_fsm_ri_counter1_loadable_rx_counter_N_61145_i.INIT = 8'hFB; + LUT3 plm_fsm_ri_counter1_loadable_rx_counter_N_61145_i ( + .I0(plm_fsm_ri_counter1_reg_rx_expired_606), + .I1(plm_fsm_reg_state_16__603), + .I2(plm_reg_rx_idl_1_0), + .O(plm_fsm_ri_counter1_N_61145_i) + ); + defparam plm_fsm_ri_counter1_N_61228_i.INIT = 4'hB; + LUT2 plm_fsm_ri_counter1_N_61228_i ( + .I0(plm_fsm_ri_counter1_reg_tx_expired_2004), + .I1(plm_fsm_ri_counter1_reg_tx_count17_0_a2_0_a2_0_a3_0_a2), + .O(plm_fsm_ri_counter1_N_61228_i_2000) + ); + FDCE plm_fsm_ri_counter1_reg_tx_count_7_ ( + .CE(plm_fsm_ri_counter1_N_61098_i_2001), + .C(mgt_clk), + .D(plm_fsm_ri_counter1_reg_tx_count_s[7]), + .Q(plm_fsm_ri_counter1_reg_tx_count[7]), + .CLR(plm_rst) + ); + FDCE plm_fsm_ri_counter1_reg_tx_count_6_ ( + .CE(plm_fsm_ri_counter1_N_61098_i_2001), + .C(mgt_clk), + .D(plm_fsm_ri_counter1_reg_tx_count_s[6]), + .Q(plm_fsm_ri_counter1_reg_tx_count[6]), + .CLR(plm_rst) + ); + FDCE plm_fsm_ri_counter1_reg_tx_count_5_ ( + .CE(plm_fsm_ri_counter1_N_61098_i_2001), + .C(mgt_clk), + .D(plm_fsm_ri_counter1_reg_tx_count_s[5]), + .Q(plm_fsm_ri_counter1_reg_tx_count[5]), + .CLR(plm_rst) + ); + FDCE plm_fsm_ri_counter1_reg_tx_count_4_ ( + .CE(plm_fsm_ri_counter1_N_61098_i_2001), + .C(mgt_clk), + .D(plm_fsm_ri_counter1_reg_tx_count_s[4]), + .Q(plm_fsm_ri_counter1_reg_tx_count[4]), + .CLR(plm_rst) + ); + FDPE plm_fsm_ri_counter1_reg_tx_count_3_ ( + .PRE(plm_rst), + .CE(plm_fsm_ri_counter1_N_61098_i_2001), + .C(mgt_clk), + .D(plm_fsm_ri_counter1_reg_tx_count_s[3]), + .Q(plm_fsm_ri_counter1_reg_tx_count[3]) + ); + FDCE plm_fsm_ri_counter1_reg_tx_count_2_ ( + .CE(plm_fsm_ri_counter1_N_61098_i_2001), + .C(mgt_clk), + .D(plm_fsm_ri_counter1_reg_tx_count_s[2]), + .Q(plm_fsm_ri_counter1_reg_tx_count[2]), + .CLR(plm_rst) + ); + FDCE plm_fsm_ri_counter1_reg_tx_count_1_ ( + .CE(plm_fsm_ri_counter1_N_61098_i_2001), + .C(mgt_clk), + .D(plm_fsm_ri_counter1_reg_tx_count_s[1]), + .Q(plm_fsm_ri_counter1_reg_tx_count[1]), + .CLR(plm_rst) + ); + FDCE plm_fsm_ri_counter1_reg_tx_count_0_ ( + .CE(plm_fsm_ri_counter1_N_61098_i_2001), + .C(mgt_clk), + .D(plm_fsm_ri_counter1_reg_tx_count_s[0]), + .Q(plm_fsm_ri_counter1_reg_tx_count[0]), + .CLR(plm_rst) + ); + FDCE plm_fsm_ri_counter1_reg_rx_count_7_ ( + .CE(plm_fsm_ri_counter1_N_61145_i), + .C(mgt_clk), + .D(plm_fsm_ri_counter1_reg_rx_count_s[7]), + .Q(plm_fsm_ri_counter1_reg_rx_count[7]), + .CLR(plm_rst) + ); + FDCE plm_fsm_ri_counter1_reg_rx_count_6_ ( + .CE(plm_fsm_ri_counter1_N_61145_i), + .C(mgt_clk), + .D(plm_fsm_ri_counter1_reg_rx_count_s[6]), + .Q(plm_fsm_ri_counter1_reg_rx_count[6]), + .CLR(plm_rst) + ); + FDCE plm_fsm_ri_counter1_reg_rx_count_5_ ( + .CE(plm_fsm_ri_counter1_N_61145_i), + .C(mgt_clk), + .D(plm_fsm_ri_counter1_reg_rx_count_s[5]), + .Q(plm_fsm_ri_counter1_reg_rx_count[5]), + .CLR(plm_rst) + ); + FDCE plm_fsm_ri_counter1_reg_rx_count_4_ ( + .CE(plm_fsm_ri_counter1_N_61145_i), + .C(mgt_clk), + .D(plm_fsm_ri_counter1_reg_rx_count_s[4]), + .Q(plm_fsm_ri_counter1_reg_rx_count[4]), + .CLR(plm_rst) + ); + FDCE plm_fsm_ri_counter1_reg_rx_count_3_ ( + .CE(plm_fsm_ri_counter1_N_61145_i), + .C(mgt_clk), + .D(plm_fsm_ri_counter1_reg_rx_count_s[3]), + .Q(plm_fsm_ri_counter1_reg_rx_count[3]), + .CLR(plm_rst) + ); + FDPE plm_fsm_ri_counter1_reg_rx_count_2_ ( + .PRE(plm_rst), + .CE(plm_fsm_ri_counter1_N_61145_i), + .C(mgt_clk), + .D(plm_fsm_ri_counter1_reg_rx_count_s[2]), + .Q(plm_fsm_ri_counter1_reg_rx_count[2]) + ); + FDCE plm_fsm_ri_counter1_reg_rx_count_1_ ( + .CE(plm_fsm_ri_counter1_N_61145_i), + .C(mgt_clk), + .D(plm_fsm_ri_counter1_reg_rx_count_s[1]), + .Q(plm_fsm_ri_counter1_reg_rx_count[1]), + .CLR(plm_rst) + ); + FDCE plm_fsm_ri_counter1_reg_rx_count_0_ ( + .CE(plm_fsm_ri_counter1_N_61145_i), + .C(mgt_clk), + .D(plm_fsm_ri_counter1_reg_rx_count_s[0]), + .Q(plm_fsm_ri_counter1_reg_rx_count[0]), + .CLR(plm_rst) + ); + FDC plm_fsm_ri_counter1_reg_expired ( + .C(mgt_clk), + .D(plm_fsm_ri_counter1_reg_expired_5), + .Q(plm_fsm_ri_cntrout1), + .CLR(plm_rst) + ); + FDCE plm_fsm_ri_counter1_reg_oneshot ( + .CE(plm_fsm_ri_counter1_N_61220_i), + .C(mgt_clk), + .D(plm_fsm_reg_state_16__603), + .Q(plm_fsm_ri_counter1_reg_oneshot_2002), + .CLR(plm_rst) + ); + FDCE plm_fsm_ri_counter1_reg_rx_expired ( + .CE(plm_fsm_ri_counter1_N_61144_i), + .C(mgt_clk), + .D(plm_fsm_reg_state_16__603), + .Q(plm_fsm_ri_counter1_reg_rx_expired_606), + .CLR(plm_rst) + ); + FDCE plm_fsm_ri_counter1_reg_tx_expired ( + .CE(plm_fsm_ri_counter1_N_61062_i_2003), + .C(mgt_clk), + .D(plm_fsm_ri_counter1_reg_tx_count17_0_a2_0_a2_0_a3_0_a2), + .Q(plm_fsm_ri_counter1_reg_tx_expired_2004), + .CLR(plm_rst) + ); + INV plm_fsm_ri_counter1_oneshot_monitor_N_61220_i ( + .I(plm_fsm_ri_counter1_un1_enable_0_a2_0_a2_0_a3_0_a2_1), + .O(plm_fsm_ri_counter1_N_61220_i) + ); + defparam plm_fsm_ri_counter1_reg_rx_count_qxu_0_0_.INIT = 4'h7; + LUT2_L plm_fsm_ri_counter1_reg_rx_count_qxu_0_0_ ( + .I0(I_5383_0_a2_0_a2_0_a3_0_a2_48), + .I1(plm_fsm_ri_counter1_reg_rx_count[0]), + .LO(plm_fsm_ri_counter1_reg_rx_count_qxu[0]) + ); + defparam plm_fsm_ri_counter1_reg_rx_count_qxu_0_1_.INIT = 4'h7; + LUT2_L plm_fsm_ri_counter1_reg_rx_count_qxu_0_1_ ( + .I0(I_5383_0_a2_0_a2_0_a3_0_a2_48), + .I1(plm_fsm_ri_counter1_reg_rx_count[1]), + .LO(plm_fsm_ri_counter1_reg_rx_count_qxu[1]) + ); + defparam plm_fsm_ri_counter1_reg_rx_count_qxu_0_2_.INIT = 8'h1B; + LUT3_L plm_fsm_ri_counter1_reg_rx_count_qxu_0_2_ ( + .I0(I_5383_0_a2_0_a2_0_a3_0_a2_48), + .I1(plm_fsm_ri_counter1_N_87176_i_2005), + .I2(plm_fsm_ri_counter1_reg_rx_count[2]), + .LO(plm_fsm_ri_counter1_reg_rx_count_qxu[2]) + ); + defparam plm_fsm_ri_counter1_reg_rx_count_qxu_0_3_.INIT = 4'h7; + LUT2_L plm_fsm_ri_counter1_reg_rx_count_qxu_0_3_ ( + .I0(I_5383_0_a2_0_a2_0_a3_0_a2_48), + .I1(plm_fsm_ri_counter1_reg_rx_count[3]), + .LO(plm_fsm_ri_counter1_reg_rx_count_qxu[3]) + ); + defparam plm_fsm_ri_counter1_reg_rx_count_qxu_0_4_.INIT = 4'h7; + LUT2_L plm_fsm_ri_counter1_reg_rx_count_qxu_0_4_ ( + .I0(I_5383_0_a2_0_a2_0_a3_0_a2_48), + .I1(plm_fsm_ri_counter1_reg_rx_count[4]), + .LO(plm_fsm_ri_counter1_reg_rx_count_qxu[4]) + ); + defparam plm_fsm_ri_counter1_reg_rx_count_qxu_0_5_.INIT = 4'h7; + LUT2_L plm_fsm_ri_counter1_reg_rx_count_qxu_0_5_ ( + .I0(I_5383_0_a2_0_a2_0_a3_0_a2_48), + .I1(plm_fsm_ri_counter1_reg_rx_count[5]), + .LO(plm_fsm_ri_counter1_reg_rx_count_qxu[5]) + ); + defparam plm_fsm_ri_counter1_reg_rx_count_qxu_0_6_.INIT = 4'h7; + LUT2_L plm_fsm_ri_counter1_reg_rx_count_qxu_0_6_ ( + .I0(I_5383_0_a2_0_a2_0_a3_0_a2_48), + .I1(plm_fsm_ri_counter1_reg_rx_count[6]), + .LO(plm_fsm_ri_counter1_reg_rx_count_qxu[6]) + ); + defparam plm_fsm_ri_counter1_reg_rx_count_qxu_0_7_.INIT = 4'h7; + LUT2_L plm_fsm_ri_counter1_reg_rx_count_qxu_0_7_ ( + .I0(I_5383_0_a2_0_a2_0_a3_0_a2_48), + .I1(plm_fsm_ri_counter1_reg_rx_count[7]), + .LO(plm_fsm_ri_counter1_reg_rx_count_qxu[7]) + ); + defparam plm_fsm_ri_counter1_reg_tx_count_qxu_0_0_.INIT = 4'h7; + LUT2_L plm_fsm_ri_counter1_reg_tx_count_qxu_0_0_ ( + .I0(plm_fsm_ri_counter1_un1_enable_1_0_a2_0_a2_0_a3_0_a2_0), + .I1(plm_fsm_ri_counter1_reg_tx_count[0]), + .LO(plm_fsm_ri_counter1_reg_tx_count_qxu[0]) + ); + defparam plm_fsm_ri_counter1_reg_tx_count_qxu_0_1_.INIT = 4'h7; + LUT2_L plm_fsm_ri_counter1_reg_tx_count_qxu_0_1_ ( + .I0(plm_fsm_ri_counter1_un1_enable_1_0_a2_0_a2_0_a3_0_a2_0), + .I1(plm_fsm_ri_counter1_reg_tx_count[1]), + .LO(plm_fsm_ri_counter1_reg_tx_count_qxu[1]) + ); + defparam plm_fsm_ri_counter1_reg_tx_count_qxu_0_2_.INIT = 4'h7; + LUT2_L plm_fsm_ri_counter1_reg_tx_count_qxu_0_2_ ( + .I0(plm_fsm_ri_counter1_un1_enable_1_0_a2_0_a2_0_a3_0_a2_0), + .I1(plm_fsm_ri_counter1_reg_tx_count[2]), + .LO(plm_fsm_ri_counter1_reg_tx_count_qxu[2]) + ); + defparam plm_fsm_ri_counter1_reg_tx_count_qxu_0_3_.INIT = 8'h2E; + LUT3_L plm_fsm_ri_counter1_reg_tx_count_qxu_0_3_ ( + .I0(plm_fsm_ri_counter1_reg_tx_count17_0_a2_0_a2_0_a3_0_a2), + .I1(plm_fsm_ri_counter1_un1_enable_1_0_a2_0_a2_0_a3_0_a2_0), + .I2(plm_fsm_ri_counter1_reg_tx_count[3]), + .LO(plm_fsm_ri_counter1_reg_tx_count_qxu[3]) + ); + defparam plm_fsm_ri_counter1_reg_tx_count_qxu_0_4_.INIT = 4'h7; + LUT2_L plm_fsm_ri_counter1_reg_tx_count_qxu_0_4_ ( + .I0(plm_fsm_ri_counter1_un1_enable_1_0_a2_0_a2_0_a3_0_a2_0), + .I1(plm_fsm_ri_counter1_reg_tx_count[4]), + .LO(plm_fsm_ri_counter1_reg_tx_count_qxu[4]) + ); + defparam plm_fsm_ri_counter1_reg_tx_count_qxu_0_5_.INIT = 4'h7; + LUT2_L plm_fsm_ri_counter1_reg_tx_count_qxu_0_5_ ( + .I0(plm_fsm_ri_counter1_un1_enable_1_0_a2_0_a2_0_a3_0_a2_0), + .I1(plm_fsm_ri_counter1_reg_tx_count[5]), + .LO(plm_fsm_ri_counter1_reg_tx_count_qxu[5]) + ); + defparam plm_fsm_ri_counter1_reg_tx_count_qxu_0_6_.INIT = 4'h7; + LUT2_L plm_fsm_ri_counter1_reg_tx_count_qxu_0_6_ ( + .I0(plm_fsm_ri_counter1_un1_enable_1_0_a2_0_a2_0_a3_0_a2_0), + .I1(plm_fsm_ri_counter1_reg_tx_count[6]), + .LO(plm_fsm_ri_counter1_reg_tx_count_qxu[6]) + ); + defparam plm_fsm_ri_counter1_reg_tx_count_qxu_0_7_.INIT = 4'h7; + LUT2_L plm_fsm_ri_counter1_reg_tx_count_qxu_0_7_ ( + .I0(plm_fsm_ri_counter1_un1_enable_1_0_a2_0_a2_0_a3_0_a2_0), + .I1(plm_fsm_ri_counter1_reg_tx_count[7]), + .LO(plm_fsm_ri_counter1_reg_tx_count_qxu[7]) + ); + VCC plm_fsm_ri_counter2_VCC ( + .P(plm_fsm_ri_counter2_VCC_2006) + ); + MUXCY_L plm_fsm_ri_counter2_reg_rx_count_cry_0_ ( + .CI(N_61138_i_51), + .DI(plm_fsm_ri_counter2_VCC_2006), + .LO(plm_fsm_ri_counter2_reg_rx_count_cry[0]), + .S(plm_fsm_ri_counter2_reg_rx_count_qxu[0]) + ); + XORCY plm_fsm_ri_counter2_reg_rx_count_s_0_ ( + .CI(N_61138_i_51), + .LI(plm_fsm_ri_counter2_reg_rx_count_qxu[0]), + .O(plm_fsm_ri_counter2_reg_rx_count_s[0]) + ); + MUXCY_L plm_fsm_ri_counter2_reg_rx_count_cry_1_ ( + .CI(plm_fsm_ri_counter2_reg_rx_count_cry[0]), + .DI(plm_fsm_ri_counter2_VCC_2006), + .LO(plm_fsm_ri_counter2_reg_rx_count_cry[1]), + .S(plm_fsm_ri_counter2_reg_rx_count_qxu[1]) + ); + XORCY plm_fsm_ri_counter2_reg_rx_count_s_1_ ( + .CI(plm_fsm_ri_counter2_reg_rx_count_cry[0]), + .LI(plm_fsm_ri_counter2_reg_rx_count_qxu[1]), + .O(plm_fsm_ri_counter2_reg_rx_count_s[1]) + ); + MUXCY_L plm_fsm_ri_counter2_reg_rx_count_cry_2_ ( + .CI(plm_fsm_ri_counter2_reg_rx_count_cry[1]), + .DI(plm_fsm_ri_counter2_VCC_2006), + .LO(plm_fsm_ri_counter2_reg_rx_count_cry[2]), + .S(plm_fsm_ri_counter2_reg_rx_count_qxu[2]) + ); + XORCY plm_fsm_ri_counter2_reg_rx_count_s_2_ ( + .CI(plm_fsm_ri_counter2_reg_rx_count_cry[1]), + .LI(plm_fsm_ri_counter2_reg_rx_count_qxu[2]), + .O(plm_fsm_ri_counter2_reg_rx_count_s[2]) + ); + MUXCY_L plm_fsm_ri_counter2_reg_rx_count_cry_3_ ( + .CI(plm_fsm_ri_counter2_reg_rx_count_cry[2]), + .DI(plm_fsm_ri_counter2_VCC_2006), + .LO(plm_fsm_ri_counter2_reg_rx_count_cry[3]), + .S(plm_fsm_ri_counter2_reg_rx_count_qxu[3]) + ); + XORCY plm_fsm_ri_counter2_reg_rx_count_s_3_ ( + .CI(plm_fsm_ri_counter2_reg_rx_count_cry[2]), + .LI(plm_fsm_ri_counter2_reg_rx_count_qxu[3]), + .O(plm_fsm_ri_counter2_reg_rx_count_s[3]) + ); + MUXCY_L plm_fsm_ri_counter2_reg_rx_count_cry_4_ ( + .CI(plm_fsm_ri_counter2_reg_rx_count_cry[3]), + .DI(plm_fsm_ri_counter2_VCC_2006), + .LO(plm_fsm_ri_counter2_reg_rx_count_cry[4]), + .S(plm_fsm_ri_counter2_reg_rx_count_qxu[4]) + ); + XORCY plm_fsm_ri_counter2_reg_rx_count_s_4_ ( + .CI(plm_fsm_ri_counter2_reg_rx_count_cry[3]), + .LI(plm_fsm_ri_counter2_reg_rx_count_qxu[4]), + .O(plm_fsm_ri_counter2_reg_rx_count_s[4]) + ); + MUXCY_L plm_fsm_ri_counter2_reg_rx_count_cry_5_ ( + .CI(plm_fsm_ri_counter2_reg_rx_count_cry[4]), + .DI(plm_fsm_ri_counter2_VCC_2006), + .LO(plm_fsm_ri_counter2_reg_rx_count_cry[5]), + .S(plm_fsm_ri_counter2_reg_rx_count_qxu[5]) + ); + XORCY plm_fsm_ri_counter2_reg_rx_count_s_5_ ( + .CI(plm_fsm_ri_counter2_reg_rx_count_cry[4]), + .LI(plm_fsm_ri_counter2_reg_rx_count_qxu[5]), + .O(plm_fsm_ri_counter2_reg_rx_count_s[5]) + ); + MUXCY_L plm_fsm_ri_counter2_reg_rx_count_cry_6_ ( + .CI(plm_fsm_ri_counter2_reg_rx_count_cry[5]), + .DI(plm_fsm_ri_counter2_VCC_2006), + .LO(plm_fsm_ri_counter2_reg_rx_count_cry[6]), + .S(plm_fsm_ri_counter2_reg_rx_count_qxu[6]) + ); + XORCY plm_fsm_ri_counter2_reg_rx_count_s_6_ ( + .CI(plm_fsm_ri_counter2_reg_rx_count_cry[5]), + .LI(plm_fsm_ri_counter2_reg_rx_count_qxu[6]), + .O(plm_fsm_ri_counter2_reg_rx_count_s[6]) + ); + XORCY plm_fsm_ri_counter2_reg_rx_count_s_7_ ( + .CI(plm_fsm_ri_counter2_reg_rx_count_cry[6]), + .LI(plm_fsm_ri_counter2_reg_rx_count_qxu[7]), + .O(plm_fsm_ri_counter2_reg_rx_count_s[7]) + ); + MUXCY_L plm_fsm_ri_counter2_reg_tx_count_cry_0_ ( + .CI(plm_fsm_ri_counter2_N_61229_i_2007), + .DI(plm_fsm_ri_counter2_VCC_2006), + .LO(plm_fsm_ri_counter2_reg_tx_count_cry[0]), + .S(plm_fsm_ri_counter2_reg_tx_count_qxu[0]) + ); + XORCY plm_fsm_ri_counter2_reg_tx_count_s_0_ ( + .CI(plm_fsm_ri_counter2_N_61229_i_2007), + .LI(plm_fsm_ri_counter2_reg_tx_count_qxu[0]), + .O(plm_fsm_ri_counter2_reg_tx_count_s[0]) + ); + MUXCY_L plm_fsm_ri_counter2_reg_tx_count_cry_1_ ( + .CI(plm_fsm_ri_counter2_reg_tx_count_cry[0]), + .DI(plm_fsm_ri_counter2_VCC_2006), + .LO(plm_fsm_ri_counter2_reg_tx_count_cry[1]), + .S(plm_fsm_ri_counter2_reg_tx_count_qxu[1]) + ); + XORCY plm_fsm_ri_counter2_reg_tx_count_s_1_ ( + .CI(plm_fsm_ri_counter2_reg_tx_count_cry[0]), + .LI(plm_fsm_ri_counter2_reg_tx_count_qxu[1]), + .O(plm_fsm_ri_counter2_reg_tx_count_s[1]) + ); + MUXCY_L plm_fsm_ri_counter2_reg_tx_count_cry_2_ ( + .CI(plm_fsm_ri_counter2_reg_tx_count_cry[1]), + .DI(plm_fsm_ri_counter2_VCC_2006), + .LO(plm_fsm_ri_counter2_reg_tx_count_cry[2]), + .S(plm_fsm_ri_counter2_reg_tx_count_qxu[2]) + ); + XORCY plm_fsm_ri_counter2_reg_tx_count_s_2_ ( + .CI(plm_fsm_ri_counter2_reg_tx_count_cry[1]), + .LI(plm_fsm_ri_counter2_reg_tx_count_qxu[2]), + .O(plm_fsm_ri_counter2_reg_tx_count_s[2]) + ); + MUXCY_L plm_fsm_ri_counter2_reg_tx_count_cry_3_ ( + .CI(plm_fsm_ri_counter2_reg_tx_count_cry[2]), + .DI(plm_fsm_ri_counter2_VCC_2006), + .LO(plm_fsm_ri_counter2_reg_tx_count_cry[3]), + .S(plm_fsm_ri_counter2_reg_tx_count_qxu[3]) + ); + XORCY plm_fsm_ri_counter2_reg_tx_count_s_3_ ( + .CI(plm_fsm_ri_counter2_reg_tx_count_cry[2]), + .LI(plm_fsm_ri_counter2_reg_tx_count_qxu[3]), + .O(plm_fsm_ri_counter2_reg_tx_count_s[3]) + ); + MUXCY_L plm_fsm_ri_counter2_reg_tx_count_cry_4_ ( + .CI(plm_fsm_ri_counter2_reg_tx_count_cry[3]), + .DI(plm_fsm_ri_counter2_VCC_2006), + .LO(plm_fsm_ri_counter2_reg_tx_count_cry[4]), + .S(plm_fsm_ri_counter2_reg_tx_count_qxu[4]) + ); + XORCY plm_fsm_ri_counter2_reg_tx_count_s_4_ ( + .CI(plm_fsm_ri_counter2_reg_tx_count_cry[3]), + .LI(plm_fsm_ri_counter2_reg_tx_count_qxu[4]), + .O(plm_fsm_ri_counter2_reg_tx_count_s[4]) + ); + MUXCY_L plm_fsm_ri_counter2_reg_tx_count_cry_5_ ( + .CI(plm_fsm_ri_counter2_reg_tx_count_cry[4]), + .DI(plm_fsm_ri_counter2_VCC_2006), + .LO(plm_fsm_ri_counter2_reg_tx_count_cry[5]), + .S(plm_fsm_ri_counter2_reg_tx_count_qxu[5]) + ); + XORCY plm_fsm_ri_counter2_reg_tx_count_s_5_ ( + .CI(plm_fsm_ri_counter2_reg_tx_count_cry[4]), + .LI(plm_fsm_ri_counter2_reg_tx_count_qxu[5]), + .O(plm_fsm_ri_counter2_reg_tx_count_s[5]) + ); + MUXCY_L plm_fsm_ri_counter2_reg_tx_count_cry_6_ ( + .CI(plm_fsm_ri_counter2_reg_tx_count_cry[5]), + .DI(plm_fsm_ri_counter2_VCC_2006), + .LO(plm_fsm_ri_counter2_reg_tx_count_cry[6]), + .S(plm_fsm_ri_counter2_reg_tx_count_qxu[6]) + ); + XORCY plm_fsm_ri_counter2_reg_tx_count_s_6_ ( + .CI(plm_fsm_ri_counter2_reg_tx_count_cry[5]), + .LI(plm_fsm_ri_counter2_reg_tx_count_qxu[6]), + .O(plm_fsm_ri_counter2_reg_tx_count_s[6]) + ); + XORCY plm_fsm_ri_counter2_reg_tx_count_s_7_ ( + .CI(plm_fsm_ri_counter2_reg_tx_count_cry[6]), + .LI(plm_fsm_ri_counter2_reg_tx_count_qxu[7]), + .O(plm_fsm_ri_counter2_reg_tx_count_s[7]) + ); + defparam plm_fsm_ri_counter2_oneshot_monitor_un1_enable_0_a2_0_a2_0_a3_0_a2.INIT = 4'h4; + LUT2 plm_fsm_ri_counter2_oneshot_monitor_un1_enable_0_a2_0_a2_0_a3_0_a2 ( + .I0(plm_reg_rx_idl_1_1), + .I1(plm_fsm_reg_state_16__603), + .O(plm_fsm_ri_counter2_un1_enable_0_a2_0_a2_0_a3_0_a2_4) + ); + defparam plm_fsm_ri_counter2_loadable_tx_counter_reg_tx_count17_0_a2_0_a2_0_a3_0_a2.INIT = 4'h8; + LUT2 plm_fsm_ri_counter2_loadable_tx_counter_reg_tx_count17_0_a2_0_a2_0_a3_0_a2 ( + .I0(plm_fsm_reg_state_16__603), + .I1(plm_fsm_ri_counter2_reg_oneshot_2009), + .O(plm_fsm_ri_counter2_reg_tx_count17_0_a2_0_a2_0_a3_0_a2_1) + ); + defparam plm_fsm_ri_counter2_un1_enable_1_0_a2_0_a2_0_a3_0_a2.INIT = 4'h2; + LUT2 plm_fsm_ri_counter2_un1_enable_1_0_a2_0_a2_0_a3_0_a2 ( + .I0(plm_fsm_ri_counter2_reg_tx_count17_0_a2_0_a2_0_a3_0_a2_1), + .I1(plm_fsm_ri_counter2_reg_tx_expired_2011), + .O(plm_fsm_ri_counter2_un1_enable_1_0_a2_0_a2_0_a3_0_a2_2013) + ); + defparam plm_fsm_ri_counter2_loadable_rx_counter_un1_reg_rx_count_0_a2_4.INIT = 16'h0001; + LUT4 plm_fsm_ri_counter2_loadable_rx_counter_un1_reg_rx_count_0_a2_4 ( + .I0(plm_fsm_ri_counter2_reg_rx_count[0]), + .I1(plm_fsm_ri_counter2_reg_rx_count[1]), + .I2(plm_fsm_ri_counter2_reg_rx_count[2]), + .I3(plm_fsm_ri_counter2_reg_rx_count[3]), + .O(plm_fsm_ri_counter2_un1_reg_rx_count_0_a2_4) + ); + defparam plm_fsm_ri_counter2_loadable_rx_counter_un1_reg_rx_count_0_a2_5.INIT = 16'h0001; + LUT4 plm_fsm_ri_counter2_loadable_rx_counter_un1_reg_rx_count_0_a2_5 ( + .I0(plm_fsm_ri_counter2_reg_rx_count[4]), + .I1(plm_fsm_ri_counter2_reg_rx_count[5]), + .I2(plm_fsm_ri_counter2_reg_rx_count[6]), + .I3(plm_fsm_ri_counter2_reg_rx_count[7]), + .O(plm_fsm_ri_counter2_un1_reg_rx_count_0_a2_5) + ); + defparam plm_fsm_ri_counter2_loadable_tx_counter_un1_reg_tx_count_0_a2_0_a3_4.INIT = 16'h0001; + LUT4 plm_fsm_ri_counter2_loadable_tx_counter_un1_reg_tx_count_0_a2_0_a3_4 ( + .I0(plm_fsm_ri_counter2_reg_tx_count[0]), + .I1(plm_fsm_ri_counter2_reg_tx_count[1]), + .I2(plm_fsm_ri_counter2_reg_tx_count[2]), + .I3(plm_fsm_ri_counter2_reg_tx_count[3]), + .O(plm_fsm_ri_counter2_un1_reg_tx_count_0_a2_0_a3_4) + ); + defparam plm_fsm_ri_counter2_loadable_tx_counter_un1_reg_tx_count_0_a2_0_a3_5.INIT = 16'h0001; + LUT4 plm_fsm_ri_counter2_loadable_tx_counter_un1_reg_tx_count_0_a2_0_a3_5 ( + .I0(plm_fsm_ri_counter2_reg_tx_count[4]), + .I1(plm_fsm_ri_counter2_reg_tx_count[5]), + .I2(plm_fsm_ri_counter2_reg_tx_count[6]), + .I3(plm_fsm_ri_counter2_reg_tx_count[7]), + .O(plm_fsm_ri_counter2_un1_reg_tx_count_0_a2_0_a3_5) + ); + defparam plm_fsm_ri_counter2_N_87175_i.INIT = 8'h3B; + LUT3_L plm_fsm_ri_counter2_N_87175_i ( + .I0(plm_fsm_N_58716_1), + .I1(plm_fsm_reg_state_16__603), + .I2(plm_fsm_ri_counter2_reg_rx_expired_605), + .LO(plm_fsm_ri_counter2_N_87175_i_2012) + ); + defparam plm_fsm_ri_counter2_N_61099_i.INIT = 4'hB; + LUT2 plm_fsm_ri_counter2_N_61099_i ( + .I0(plm_reg_sym_sent_0_), + .I1(plm_fsm_ri_counter2_un1_enable_1_0_a2_0_a2_0_a3_0_a2_2013), + .O(plm_fsm_ri_counter2_N_61099_i_2008) + ); + defparam plm_fsm_ri_counter2_N_61060_i.INIT = 8'hD5; + LUT3 plm_fsm_ri_counter2_N_61060_i ( + .I0(plm_fsm_ri_counter2_reg_tx_count17_0_a2_0_a2_0_a3_0_a2_1), + .I1(plm_fsm_ri_counter2_un1_reg_tx_count_0_a2_0_a3_4), + .I2(plm_fsm_ri_counter2_un1_reg_tx_count_0_a2_0_a3_5), + .O(plm_fsm_ri_counter2_N_61060_i_2010) + ); + defparam plm_fsm_ri_counter2_loadable_rx_counter_N_61142_i.INIT = 8'hD5; + LUT3 plm_fsm_ri_counter2_loadable_rx_counter_N_61142_i ( + .I0(plm_fsm_reg_state_16__603), + .I1(plm_fsm_ri_counter2_un1_reg_rx_count_0_a2_4), + .I2(plm_fsm_ri_counter2_un1_reg_rx_count_0_a2_5), + .O(plm_fsm_ri_counter2_N_61142_i) + ); + defparam plm_fsm_ri_counter2_flagit_reg_expired_5_0_a2_0_a2_0_a3_0_a2.INIT = 8'h80; + LUT3_L plm_fsm_ri_counter2_flagit_reg_expired_5_0_a2_0_a2_0_a3_0_a2 ( + .I0(plm_fsm_reg_state_16__603), + .I1(plm_fsm_ri_counter2_reg_rx_expired_605), + .I2(plm_fsm_ri_counter2_reg_tx_expired_2011), + .LO(plm_fsm_ri_counter2_reg_expired_5) + ); + defparam plm_fsm_ri_counter2_loadable_rx_counter_N_61143_i.INIT = 8'hFB; + LUT3 plm_fsm_ri_counter2_loadable_rx_counter_N_61143_i ( + .I0(plm_fsm_ri_counter2_reg_rx_expired_605), + .I1(plm_fsm_reg_state_16__603), + .I2(plm_reg_rx_idl_1_1), + .O(plm_fsm_ri_counter2_N_61143_i) + ); + defparam plm_fsm_ri_counter2_N_61229_i.INIT = 4'hB; + LUT2 plm_fsm_ri_counter2_N_61229_i ( + .I0(plm_fsm_ri_counter2_reg_tx_expired_2011), + .I1(plm_fsm_ri_counter2_reg_tx_count17_0_a2_0_a2_0_a3_0_a2_1), + .O(plm_fsm_ri_counter2_N_61229_i_2007) + ); + FDCE plm_fsm_ri_counter2_reg_tx_count_7_ ( + .CE(plm_fsm_ri_counter2_N_61099_i_2008), + .C(mgt_clk), + .D(plm_fsm_ri_counter2_reg_tx_count_s[7]), + .Q(plm_fsm_ri_counter2_reg_tx_count[7]), + .CLR(plm_rst) + ); + FDCE plm_fsm_ri_counter2_reg_tx_count_6_ ( + .CE(plm_fsm_ri_counter2_N_61099_i_2008), + .C(mgt_clk), + .D(plm_fsm_ri_counter2_reg_tx_count_s[6]), + .Q(plm_fsm_ri_counter2_reg_tx_count[6]), + .CLR(plm_rst) + ); + FDCE plm_fsm_ri_counter2_reg_tx_count_5_ ( + .CE(plm_fsm_ri_counter2_N_61099_i_2008), + .C(mgt_clk), + .D(plm_fsm_ri_counter2_reg_tx_count_s[5]), + .Q(plm_fsm_ri_counter2_reg_tx_count[5]), + .CLR(plm_rst) + ); + FDCE plm_fsm_ri_counter2_reg_tx_count_4_ ( + .CE(plm_fsm_ri_counter2_N_61099_i_2008), + .C(mgt_clk), + .D(plm_fsm_ri_counter2_reg_tx_count_s[4]), + .Q(plm_fsm_ri_counter2_reg_tx_count[4]), + .CLR(plm_rst) + ); + FDPE plm_fsm_ri_counter2_reg_tx_count_3_ ( + .PRE(plm_rst), + .CE(plm_fsm_ri_counter2_N_61099_i_2008), + .C(mgt_clk), + .D(plm_fsm_ri_counter2_reg_tx_count_s[3]), + .Q(plm_fsm_ri_counter2_reg_tx_count[3]) + ); + FDCE plm_fsm_ri_counter2_reg_tx_count_2_ ( + .CE(plm_fsm_ri_counter2_N_61099_i_2008), + .C(mgt_clk), + .D(plm_fsm_ri_counter2_reg_tx_count_s[2]), + .Q(plm_fsm_ri_counter2_reg_tx_count[2]), + .CLR(plm_rst) + ); + FDCE plm_fsm_ri_counter2_reg_tx_count_1_ ( + .CE(plm_fsm_ri_counter2_N_61099_i_2008), + .C(mgt_clk), + .D(plm_fsm_ri_counter2_reg_tx_count_s[1]), + .Q(plm_fsm_ri_counter2_reg_tx_count[1]), + .CLR(plm_rst) + ); + FDCE plm_fsm_ri_counter2_reg_tx_count_0_ ( + .CE(plm_fsm_ri_counter2_N_61099_i_2008), + .C(mgt_clk), + .D(plm_fsm_ri_counter2_reg_tx_count_s[0]), + .Q(plm_fsm_ri_counter2_reg_tx_count[0]), + .CLR(plm_rst) + ); + FDCE plm_fsm_ri_counter2_reg_rx_count_7_ ( + .CE(plm_fsm_ri_counter2_N_61143_i), + .C(mgt_clk), + .D(plm_fsm_ri_counter2_reg_rx_count_s[7]), + .Q(plm_fsm_ri_counter2_reg_rx_count[7]), + .CLR(plm_rst) + ); + FDCE plm_fsm_ri_counter2_reg_rx_count_6_ ( + .CE(plm_fsm_ri_counter2_N_61143_i), + .C(mgt_clk), + .D(plm_fsm_ri_counter2_reg_rx_count_s[6]), + .Q(plm_fsm_ri_counter2_reg_rx_count[6]), + .CLR(plm_rst) + ); + FDCE plm_fsm_ri_counter2_reg_rx_count_5_ ( + .CE(plm_fsm_ri_counter2_N_61143_i), + .C(mgt_clk), + .D(plm_fsm_ri_counter2_reg_rx_count_s[5]), + .Q(plm_fsm_ri_counter2_reg_rx_count[5]), + .CLR(plm_rst) + ); + FDCE plm_fsm_ri_counter2_reg_rx_count_4_ ( + .CE(plm_fsm_ri_counter2_N_61143_i), + .C(mgt_clk), + .D(plm_fsm_ri_counter2_reg_rx_count_s[4]), + .Q(plm_fsm_ri_counter2_reg_rx_count[4]), + .CLR(plm_rst) + ); + FDCE plm_fsm_ri_counter2_reg_rx_count_3_ ( + .CE(plm_fsm_ri_counter2_N_61143_i), + .C(mgt_clk), + .D(plm_fsm_ri_counter2_reg_rx_count_s[3]), + .Q(plm_fsm_ri_counter2_reg_rx_count[3]), + .CLR(plm_rst) + ); + FDPE plm_fsm_ri_counter2_reg_rx_count_2_ ( + .PRE(plm_rst), + .CE(plm_fsm_ri_counter2_N_61143_i), + .C(mgt_clk), + .D(plm_fsm_ri_counter2_reg_rx_count_s[2]), + .Q(plm_fsm_ri_counter2_reg_rx_count[2]) + ); + FDCE plm_fsm_ri_counter2_reg_rx_count_1_ ( + .CE(plm_fsm_ri_counter2_N_61143_i), + .C(mgt_clk), + .D(plm_fsm_ri_counter2_reg_rx_count_s[1]), + .Q(plm_fsm_ri_counter2_reg_rx_count[1]), + .CLR(plm_rst) + ); + FDCE plm_fsm_ri_counter2_reg_rx_count_0_ ( + .CE(plm_fsm_ri_counter2_N_61143_i), + .C(mgt_clk), + .D(plm_fsm_ri_counter2_reg_rx_count_s[0]), + .Q(plm_fsm_ri_counter2_reg_rx_count[0]), + .CLR(plm_rst) + ); + FDC plm_fsm_ri_counter2_reg_expired ( + .C(mgt_clk), + .D(plm_fsm_ri_counter2_reg_expired_5), + .Q(plm_fsm_ri_cntrout2), + .CLR(plm_rst) + ); + FDCE plm_fsm_ri_counter2_reg_oneshot ( + .CE(plm_fsm_ri_counter2_N_61216_i), + .C(mgt_clk), + .D(plm_fsm_reg_state_16__603), + .Q(plm_fsm_ri_counter2_reg_oneshot_2009), + .CLR(plm_rst) + ); + FDCE plm_fsm_ri_counter2_reg_rx_expired ( + .CE(plm_fsm_ri_counter2_N_61142_i), + .C(mgt_clk), + .D(plm_fsm_reg_state_16__603), + .Q(plm_fsm_ri_counter2_reg_rx_expired_605), + .CLR(plm_rst) + ); + FDCE plm_fsm_ri_counter2_reg_tx_expired ( + .CE(plm_fsm_ri_counter2_N_61060_i_2010), + .C(mgt_clk), + .D(plm_fsm_ri_counter2_reg_tx_count17_0_a2_0_a2_0_a3_0_a2_1), + .Q(plm_fsm_ri_counter2_reg_tx_expired_2011), + .CLR(plm_rst) + ); + INV plm_fsm_ri_counter2_oneshot_monitor_N_61216_i ( + .I(plm_fsm_ri_counter2_un1_enable_0_a2_0_a2_0_a3_0_a2_4), + .O(plm_fsm_ri_counter2_N_61216_i) + ); + defparam plm_fsm_ri_counter2_reg_rx_count_qxu_0_0_.INIT = 4'h7; + LUT2_L plm_fsm_ri_counter2_reg_rx_count_qxu_0_0_ ( + .I0(I_5389_0_a2_0_a2_0_a3_0_a2_50), + .I1(plm_fsm_ri_counter2_reg_rx_count[0]), + .LO(plm_fsm_ri_counter2_reg_rx_count_qxu[0]) + ); + defparam plm_fsm_ri_counter2_reg_rx_count_qxu_0_1_.INIT = 4'h7; + LUT2_L plm_fsm_ri_counter2_reg_rx_count_qxu_0_1_ ( + .I0(I_5389_0_a2_0_a2_0_a3_0_a2_50), + .I1(plm_fsm_ri_counter2_reg_rx_count[1]), + .LO(plm_fsm_ri_counter2_reg_rx_count_qxu[1]) + ); + defparam plm_fsm_ri_counter2_reg_rx_count_qxu_0_2_.INIT = 8'h1B; + LUT3_L plm_fsm_ri_counter2_reg_rx_count_qxu_0_2_ ( + .I0(I_5389_0_a2_0_a2_0_a3_0_a2_50), + .I1(plm_fsm_ri_counter2_N_87175_i_2012), + .I2(plm_fsm_ri_counter2_reg_rx_count[2]), + .LO(plm_fsm_ri_counter2_reg_rx_count_qxu[2]) + ); + defparam plm_fsm_ri_counter2_reg_rx_count_qxu_0_3_.INIT = 4'h7; + LUT2_L plm_fsm_ri_counter2_reg_rx_count_qxu_0_3_ ( + .I0(I_5389_0_a2_0_a2_0_a3_0_a2_50), + .I1(plm_fsm_ri_counter2_reg_rx_count[3]), + .LO(plm_fsm_ri_counter2_reg_rx_count_qxu[3]) + ); + defparam plm_fsm_ri_counter2_reg_rx_count_qxu_0_4_.INIT = 4'h7; + LUT2_L plm_fsm_ri_counter2_reg_rx_count_qxu_0_4_ ( + .I0(I_5389_0_a2_0_a2_0_a3_0_a2_50), + .I1(plm_fsm_ri_counter2_reg_rx_count[4]), + .LO(plm_fsm_ri_counter2_reg_rx_count_qxu[4]) + ); + defparam plm_fsm_ri_counter2_reg_rx_count_qxu_0_5_.INIT = 4'h7; + LUT2_L plm_fsm_ri_counter2_reg_rx_count_qxu_0_5_ ( + .I0(I_5389_0_a2_0_a2_0_a3_0_a2_50), + .I1(plm_fsm_ri_counter2_reg_rx_count[5]), + .LO(plm_fsm_ri_counter2_reg_rx_count_qxu[5]) + ); + defparam plm_fsm_ri_counter2_reg_rx_count_qxu_0_6_.INIT = 4'h7; + LUT2_L plm_fsm_ri_counter2_reg_rx_count_qxu_0_6_ ( + .I0(I_5389_0_a2_0_a2_0_a3_0_a2_50), + .I1(plm_fsm_ri_counter2_reg_rx_count[6]), + .LO(plm_fsm_ri_counter2_reg_rx_count_qxu[6]) + ); + defparam plm_fsm_ri_counter2_reg_rx_count_qxu_0_7_.INIT = 4'h7; + LUT2_L plm_fsm_ri_counter2_reg_rx_count_qxu_0_7_ ( + .I0(I_5389_0_a2_0_a2_0_a3_0_a2_50), + .I1(plm_fsm_ri_counter2_reg_rx_count[7]), + .LO(plm_fsm_ri_counter2_reg_rx_count_qxu[7]) + ); + defparam plm_fsm_ri_counter2_reg_tx_count_qxu_0_0_.INIT = 4'h7; + LUT2_L plm_fsm_ri_counter2_reg_tx_count_qxu_0_0_ ( + .I0(plm_fsm_ri_counter2_un1_enable_1_0_a2_0_a2_0_a3_0_a2_2013), + .I1(plm_fsm_ri_counter2_reg_tx_count[0]), + .LO(plm_fsm_ri_counter2_reg_tx_count_qxu[0]) + ); + defparam plm_fsm_ri_counter2_reg_tx_count_qxu_0_1_.INIT = 4'h7; + LUT2_L plm_fsm_ri_counter2_reg_tx_count_qxu_0_1_ ( + .I0(plm_fsm_ri_counter2_un1_enable_1_0_a2_0_a2_0_a3_0_a2_2013), + .I1(plm_fsm_ri_counter2_reg_tx_count[1]), + .LO(plm_fsm_ri_counter2_reg_tx_count_qxu[1]) + ); + defparam plm_fsm_ri_counter2_reg_tx_count_qxu_0_2_.INIT = 4'h7; + LUT2_L plm_fsm_ri_counter2_reg_tx_count_qxu_0_2_ ( + .I0(plm_fsm_ri_counter2_un1_enable_1_0_a2_0_a2_0_a3_0_a2_2013), + .I1(plm_fsm_ri_counter2_reg_tx_count[2]), + .LO(plm_fsm_ri_counter2_reg_tx_count_qxu[2]) + ); + defparam plm_fsm_ri_counter2_reg_tx_count_qxu_0_3_.INIT = 8'h2E; + LUT3_L plm_fsm_ri_counter2_reg_tx_count_qxu_0_3_ ( + .I0(plm_fsm_ri_counter2_reg_tx_count17_0_a2_0_a2_0_a3_0_a2_1), + .I1(plm_fsm_ri_counter2_un1_enable_1_0_a2_0_a2_0_a3_0_a2_2013), + .I2(plm_fsm_ri_counter2_reg_tx_count[3]), + .LO(plm_fsm_ri_counter2_reg_tx_count_qxu[3]) + ); + defparam plm_fsm_ri_counter2_reg_tx_count_qxu_0_4_.INIT = 4'h7; + LUT2_L plm_fsm_ri_counter2_reg_tx_count_qxu_0_4_ ( + .I0(plm_fsm_ri_counter2_un1_enable_1_0_a2_0_a2_0_a3_0_a2_2013), + .I1(plm_fsm_ri_counter2_reg_tx_count[4]), + .LO(plm_fsm_ri_counter2_reg_tx_count_qxu[4]) + ); + defparam plm_fsm_ri_counter2_reg_tx_count_qxu_0_5_.INIT = 4'h7; + LUT2_L plm_fsm_ri_counter2_reg_tx_count_qxu_0_5_ ( + .I0(plm_fsm_ri_counter2_un1_enable_1_0_a2_0_a2_0_a3_0_a2_2013), + .I1(plm_fsm_ri_counter2_reg_tx_count[5]), + .LO(plm_fsm_ri_counter2_reg_tx_count_qxu[5]) + ); + defparam plm_fsm_ri_counter2_reg_tx_count_qxu_0_6_.INIT = 4'h7; + LUT2_L plm_fsm_ri_counter2_reg_tx_count_qxu_0_6_ ( + .I0(plm_fsm_ri_counter2_un1_enable_1_0_a2_0_a2_0_a3_0_a2_2013), + .I1(plm_fsm_ri_counter2_reg_tx_count[6]), + .LO(plm_fsm_ri_counter2_reg_tx_count_qxu[6]) + ); + defparam plm_fsm_ri_counter2_reg_tx_count_qxu_0_7_.INIT = 4'h7; + LUT2_L plm_fsm_ri_counter2_reg_tx_count_qxu_0_7_ ( + .I0(plm_fsm_ri_counter2_un1_enable_1_0_a2_0_a2_0_a3_0_a2_2013), + .I1(plm_fsm_ri_counter2_reg_tx_count[7]), + .LO(plm_fsm_ri_counter2_reg_tx_count_qxu[7]) + ); + VCC plm_fsm_ri_counter3_VCC ( + .P(plm_fsm_ri_counter3_VCC_2014) + ); + MUXCY_L plm_fsm_ri_counter3_reg_rx_count_cry_0_ ( + .CI(N_61139_i_53), + .DI(plm_fsm_ri_counter3_VCC_2014), + .LO(plm_fsm_ri_counter3_reg_rx_count_cry[0]), + .S(plm_fsm_ri_counter3_reg_rx_count_qxu[0]) + ); + XORCY plm_fsm_ri_counter3_reg_rx_count_s_0_ ( + .CI(N_61139_i_53), + .LI(plm_fsm_ri_counter3_reg_rx_count_qxu[0]), + .O(plm_fsm_ri_counter3_reg_rx_count_s[0]) + ); + MUXCY_L plm_fsm_ri_counter3_reg_rx_count_cry_1_ ( + .CI(plm_fsm_ri_counter3_reg_rx_count_cry[0]), + .DI(plm_fsm_ri_counter3_VCC_2014), + .LO(plm_fsm_ri_counter3_reg_rx_count_cry[1]), + .S(plm_fsm_ri_counter3_reg_rx_count_qxu[1]) + ); + XORCY plm_fsm_ri_counter3_reg_rx_count_s_1_ ( + .CI(plm_fsm_ri_counter3_reg_rx_count_cry[0]), + .LI(plm_fsm_ri_counter3_reg_rx_count_qxu[1]), + .O(plm_fsm_ri_counter3_reg_rx_count_s[1]) + ); + MUXCY_L plm_fsm_ri_counter3_reg_rx_count_cry_2_ ( + .CI(plm_fsm_ri_counter3_reg_rx_count_cry[1]), + .DI(plm_fsm_ri_counter3_VCC_2014), + .LO(plm_fsm_ri_counter3_reg_rx_count_cry[2]), + .S(plm_fsm_ri_counter3_reg_rx_count_qxu[2]) + ); + XORCY plm_fsm_ri_counter3_reg_rx_count_s_2_ ( + .CI(plm_fsm_ri_counter3_reg_rx_count_cry[1]), + .LI(plm_fsm_ri_counter3_reg_rx_count_qxu[2]), + .O(plm_fsm_ri_counter3_reg_rx_count_s[2]) + ); + MUXCY_L plm_fsm_ri_counter3_reg_rx_count_cry_3_ ( + .CI(plm_fsm_ri_counter3_reg_rx_count_cry[2]), + .DI(plm_fsm_ri_counter3_VCC_2014), + .LO(plm_fsm_ri_counter3_reg_rx_count_cry[3]), + .S(plm_fsm_ri_counter3_reg_rx_count_qxu[3]) + ); + XORCY plm_fsm_ri_counter3_reg_rx_count_s_3_ ( + .CI(plm_fsm_ri_counter3_reg_rx_count_cry[2]), + .LI(plm_fsm_ri_counter3_reg_rx_count_qxu[3]), + .O(plm_fsm_ri_counter3_reg_rx_count_s[3]) + ); + MUXCY_L plm_fsm_ri_counter3_reg_rx_count_cry_4_ ( + .CI(plm_fsm_ri_counter3_reg_rx_count_cry[3]), + .DI(plm_fsm_ri_counter3_VCC_2014), + .LO(plm_fsm_ri_counter3_reg_rx_count_cry[4]), + .S(plm_fsm_ri_counter3_reg_rx_count_qxu[4]) + ); + XORCY plm_fsm_ri_counter3_reg_rx_count_s_4_ ( + .CI(plm_fsm_ri_counter3_reg_rx_count_cry[3]), + .LI(plm_fsm_ri_counter3_reg_rx_count_qxu[4]), + .O(plm_fsm_ri_counter3_reg_rx_count_s[4]) + ); + MUXCY_L plm_fsm_ri_counter3_reg_rx_count_cry_5_ ( + .CI(plm_fsm_ri_counter3_reg_rx_count_cry[4]), + .DI(plm_fsm_ri_counter3_VCC_2014), + .LO(plm_fsm_ri_counter3_reg_rx_count_cry[5]), + .S(plm_fsm_ri_counter3_reg_rx_count_qxu[5]) + ); + XORCY plm_fsm_ri_counter3_reg_rx_count_s_5_ ( + .CI(plm_fsm_ri_counter3_reg_rx_count_cry[4]), + .LI(plm_fsm_ri_counter3_reg_rx_count_qxu[5]), + .O(plm_fsm_ri_counter3_reg_rx_count_s[5]) + ); + MUXCY_L plm_fsm_ri_counter3_reg_rx_count_cry_6_ ( + .CI(plm_fsm_ri_counter3_reg_rx_count_cry[5]), + .DI(plm_fsm_ri_counter3_VCC_2014), + .LO(plm_fsm_ri_counter3_reg_rx_count_cry[6]), + .S(plm_fsm_ri_counter3_reg_rx_count_qxu[6]) + ); + XORCY plm_fsm_ri_counter3_reg_rx_count_s_6_ ( + .CI(plm_fsm_ri_counter3_reg_rx_count_cry[5]), + .LI(plm_fsm_ri_counter3_reg_rx_count_qxu[6]), + .O(plm_fsm_ri_counter3_reg_rx_count_s[6]) + ); + XORCY plm_fsm_ri_counter3_reg_rx_count_s_7_ ( + .CI(plm_fsm_ri_counter3_reg_rx_count_cry[6]), + .LI(plm_fsm_ri_counter3_reg_rx_count_qxu[7]), + .O(plm_fsm_ri_counter3_reg_rx_count_s[7]) + ); + MUXCY_L plm_fsm_ri_counter3_reg_tx_count_cry_0_ ( + .CI(plm_fsm_ri_counter3_N_61230_i_2015), + .DI(plm_fsm_ri_counter3_VCC_2014), + .LO(plm_fsm_ri_counter3_reg_tx_count_cry[0]), + .S(plm_fsm_ri_counter3_reg_tx_count_qxu[0]) + ); + XORCY plm_fsm_ri_counter3_reg_tx_count_s_0_ ( + .CI(plm_fsm_ri_counter3_N_61230_i_2015), + .LI(plm_fsm_ri_counter3_reg_tx_count_qxu[0]), + .O(plm_fsm_ri_counter3_reg_tx_count_s[0]) + ); + MUXCY_L plm_fsm_ri_counter3_reg_tx_count_cry_1_ ( + .CI(plm_fsm_ri_counter3_reg_tx_count_cry[0]), + .DI(plm_fsm_ri_counter3_VCC_2014), + .LO(plm_fsm_ri_counter3_reg_tx_count_cry[1]), + .S(plm_fsm_ri_counter3_reg_tx_count_qxu[1]) + ); + XORCY plm_fsm_ri_counter3_reg_tx_count_s_1_ ( + .CI(plm_fsm_ri_counter3_reg_tx_count_cry[0]), + .LI(plm_fsm_ri_counter3_reg_tx_count_qxu[1]), + .O(plm_fsm_ri_counter3_reg_tx_count_s[1]) + ); + MUXCY_L plm_fsm_ri_counter3_reg_tx_count_cry_2_ ( + .CI(plm_fsm_ri_counter3_reg_tx_count_cry[1]), + .DI(plm_fsm_ri_counter3_VCC_2014), + .LO(plm_fsm_ri_counter3_reg_tx_count_cry[2]), + .S(plm_fsm_ri_counter3_reg_tx_count_qxu[2]) + ); + XORCY plm_fsm_ri_counter3_reg_tx_count_s_2_ ( + .CI(plm_fsm_ri_counter3_reg_tx_count_cry[1]), + .LI(plm_fsm_ri_counter3_reg_tx_count_qxu[2]), + .O(plm_fsm_ri_counter3_reg_tx_count_s[2]) + ); + MUXCY_L plm_fsm_ri_counter3_reg_tx_count_cry_3_ ( + .CI(plm_fsm_ri_counter3_reg_tx_count_cry[2]), + .DI(plm_fsm_ri_counter3_VCC_2014), + .LO(plm_fsm_ri_counter3_reg_tx_count_cry[3]), + .S(plm_fsm_ri_counter3_reg_tx_count_qxu[3]) + ); + XORCY plm_fsm_ri_counter3_reg_tx_count_s_3_ ( + .CI(plm_fsm_ri_counter3_reg_tx_count_cry[2]), + .LI(plm_fsm_ri_counter3_reg_tx_count_qxu[3]), + .O(plm_fsm_ri_counter3_reg_tx_count_s[3]) + ); + MUXCY_L plm_fsm_ri_counter3_reg_tx_count_cry_4_ ( + .CI(plm_fsm_ri_counter3_reg_tx_count_cry[3]), + .DI(plm_fsm_ri_counter3_VCC_2014), + .LO(plm_fsm_ri_counter3_reg_tx_count_cry[4]), + .S(plm_fsm_ri_counter3_reg_tx_count_qxu[4]) + ); + XORCY plm_fsm_ri_counter3_reg_tx_count_s_4_ ( + .CI(plm_fsm_ri_counter3_reg_tx_count_cry[3]), + .LI(plm_fsm_ri_counter3_reg_tx_count_qxu[4]), + .O(plm_fsm_ri_counter3_reg_tx_count_s[4]) + ); + MUXCY_L plm_fsm_ri_counter3_reg_tx_count_cry_5_ ( + .CI(plm_fsm_ri_counter3_reg_tx_count_cry[4]), + .DI(plm_fsm_ri_counter3_VCC_2014), + .LO(plm_fsm_ri_counter3_reg_tx_count_cry[5]), + .S(plm_fsm_ri_counter3_reg_tx_count_qxu[5]) + ); + XORCY plm_fsm_ri_counter3_reg_tx_count_s_5_ ( + .CI(plm_fsm_ri_counter3_reg_tx_count_cry[4]), + .LI(plm_fsm_ri_counter3_reg_tx_count_qxu[5]), + .O(plm_fsm_ri_counter3_reg_tx_count_s[5]) + ); + MUXCY_L plm_fsm_ri_counter3_reg_tx_count_cry_6_ ( + .CI(plm_fsm_ri_counter3_reg_tx_count_cry[5]), + .DI(plm_fsm_ri_counter3_VCC_2014), + .LO(plm_fsm_ri_counter3_reg_tx_count_cry[6]), + .S(plm_fsm_ri_counter3_reg_tx_count_qxu[6]) + ); + XORCY plm_fsm_ri_counter3_reg_tx_count_s_6_ ( + .CI(plm_fsm_ri_counter3_reg_tx_count_cry[5]), + .LI(plm_fsm_ri_counter3_reg_tx_count_qxu[6]), + .O(plm_fsm_ri_counter3_reg_tx_count_s[6]) + ); + XORCY plm_fsm_ri_counter3_reg_tx_count_s_7_ ( + .CI(plm_fsm_ri_counter3_reg_tx_count_cry[6]), + .LI(plm_fsm_ri_counter3_reg_tx_count_qxu[7]), + .O(plm_fsm_ri_counter3_reg_tx_count_s[7]) + ); + defparam plm_fsm_ri_counter3_oneshot_monitor_un1_enable_0_a2_0_a2_0_a3_0_a2.INIT = 4'h4; + LUT2 plm_fsm_ri_counter3_oneshot_monitor_un1_enable_0_a2_0_a2_0_a3_0_a2 ( + .I0(plm_reg_rx_idl_1_2), + .I1(plm_fsm_reg_state_16__603), + .O(plm_fsm_ri_counter3_un1_enable_0_a2_0_a2_0_a3_0_a2_2) + ); + defparam plm_fsm_ri_counter3_loadable_tx_counter_reg_tx_count17_0_a3_0_a2_0_a2_0_a3_0_a2.INIT = 4'h8; + LUT2 plm_fsm_ri_counter3_loadable_tx_counter_reg_tx_count17_0_a3_0_a2_0_a2_0_a3_0_a2 ( + .I0(plm_fsm_reg_state_16__603), + .I1(plm_fsm_ri_counter3_reg_oneshot_2017), + .O(plm_fsm_ri_counter3_reg_tx_count17_0_a3_0_a2_0_a2_0_a3_0_a2) + ); + defparam plm_fsm_ri_counter3_un1_enable_1_0_a2_0_a2_0_a2_0_a3_0_a2.INIT = 4'h2; + LUT2 plm_fsm_ri_counter3_un1_enable_1_0_a2_0_a2_0_a2_0_a3_0_a2 ( + .I0(plm_fsm_ri_counter3_reg_tx_count17_0_a3_0_a2_0_a2_0_a3_0_a2), + .I1(plm_fsm_ri_counter3_reg_tx_expired_2019), + .O(plm_fsm_ri_counter3_un1_enable_1_0_a2_0_a2_0_a2_0_a3_0_a2_2021) + ); + defparam plm_fsm_ri_counter3_loadable_tx_counter_un1_reg_tx_count_0_a2_0_a3_4.INIT = 16'h0001; + LUT4 plm_fsm_ri_counter3_loadable_tx_counter_un1_reg_tx_count_0_a2_0_a3_4 ( + .I0(plm_fsm_ri_counter3_reg_tx_count[0]), + .I1(plm_fsm_ri_counter3_reg_tx_count[1]), + .I2(plm_fsm_ri_counter3_reg_tx_count[2]), + .I3(plm_fsm_ri_counter3_reg_tx_count[3]), + .O(plm_fsm_ri_counter3_un1_reg_tx_count_0_a2_0_a3_4) + ); + defparam plm_fsm_ri_counter3_loadable_tx_counter_un1_reg_tx_count_0_a2_0_a3_5.INIT = 16'h0001; + LUT4 plm_fsm_ri_counter3_loadable_tx_counter_un1_reg_tx_count_0_a2_0_a3_5 ( + .I0(plm_fsm_ri_counter3_reg_tx_count[4]), + .I1(plm_fsm_ri_counter3_reg_tx_count[5]), + .I2(plm_fsm_ri_counter3_reg_tx_count[6]), + .I3(plm_fsm_ri_counter3_reg_tx_count[7]), + .O(plm_fsm_ri_counter3_un1_reg_tx_count_0_a2_0_a3_5) + ); + defparam plm_fsm_ri_counter3_loadable_rx_counter_un1_reg_rx_count_0_a2_4.INIT = 16'h0001; + LUT4 plm_fsm_ri_counter3_loadable_rx_counter_un1_reg_rx_count_0_a2_4 ( + .I0(plm_fsm_ri_counter3_reg_rx_count[0]), + .I1(plm_fsm_ri_counter3_reg_rx_count[1]), + .I2(plm_fsm_ri_counter3_reg_rx_count[2]), + .I3(plm_fsm_ri_counter3_reg_rx_count[3]), + .O(plm_fsm_ri_counter3_un1_reg_rx_count_0_a2_4) + ); + defparam plm_fsm_ri_counter3_loadable_rx_counter_un1_reg_rx_count_0_a2_5.INIT = 16'h0001; + LUT4 plm_fsm_ri_counter3_loadable_rx_counter_un1_reg_rx_count_0_a2_5 ( + .I0(plm_fsm_ri_counter3_reg_rx_count[4]), + .I1(plm_fsm_ri_counter3_reg_rx_count[5]), + .I2(plm_fsm_ri_counter3_reg_rx_count[6]), + .I3(plm_fsm_ri_counter3_reg_rx_count[7]), + .O(plm_fsm_ri_counter3_un1_reg_rx_count_0_a2_5) + ); + defparam plm_fsm_ri_counter3_N_87174_i.INIT = 8'h3B; + LUT3_L plm_fsm_ri_counter3_N_87174_i ( + .I0(plm_fsm_N_58715_1), + .I1(plm_fsm_reg_state_16__603), + .I2(plm_fsm_ri_counter3_reg_rx_expired_604), + .LO(plm_fsm_ri_counter3_N_87174_i_2020) + ); + defparam plm_fsm_ri_counter3_N_61100_i.INIT = 4'hB; + LUT2 plm_fsm_ri_counter3_N_61100_i ( + .I0(plm_reg_sym_sent_0_), + .I1(plm_fsm_ri_counter3_un1_enable_1_0_a2_0_a2_0_a2_0_a3_0_a2_2021), + .O(plm_fsm_ri_counter3_N_61100_i_2016) + ); + defparam plm_fsm_ri_counter3_N_61058_i.INIT = 8'hD5; + LUT3 plm_fsm_ri_counter3_N_61058_i ( + .I0(plm_fsm_ri_counter3_reg_tx_count17_0_a3_0_a2_0_a2_0_a3_0_a2), + .I1(plm_fsm_ri_counter3_un1_reg_tx_count_0_a2_0_a3_4), + .I2(plm_fsm_ri_counter3_un1_reg_tx_count_0_a2_0_a3_5), + .O(plm_fsm_ri_counter3_N_61058_i_2018) + ); + defparam plm_fsm_ri_counter3_loadable_rx_counter_N_61140_i.INIT = 8'hD5; + LUT3 plm_fsm_ri_counter3_loadable_rx_counter_N_61140_i ( + .I0(plm_fsm_reg_state_16__603), + .I1(plm_fsm_ri_counter3_un1_reg_rx_count_0_a2_4), + .I2(plm_fsm_ri_counter3_un1_reg_rx_count_0_a2_5), + .O(plm_fsm_ri_counter3_N_61140_i) + ); + defparam plm_fsm_ri_counter3_flagit_reg_expired_5_0_a2_0_a2_0_a3_0_a2.INIT = 8'h80; + LUT3_L plm_fsm_ri_counter3_flagit_reg_expired_5_0_a2_0_a2_0_a3_0_a2 ( + .I0(plm_fsm_reg_state_16__603), + .I1(plm_fsm_ri_counter3_reg_rx_expired_604), + .I2(plm_fsm_ri_counter3_reg_tx_expired_2019), + .LO(plm_fsm_ri_counter3_reg_expired_5) + ); + defparam plm_fsm_ri_counter3_loadable_rx_counter_N_61141_i.INIT = 8'hFB; + LUT3 plm_fsm_ri_counter3_loadable_rx_counter_N_61141_i ( + .I0(plm_fsm_ri_counter3_reg_rx_expired_604), + .I1(plm_fsm_reg_state_16__603), + .I2(plm_reg_rx_idl_1_2), + .O(plm_fsm_ri_counter3_N_61141_i) + ); + defparam plm_fsm_ri_counter3_N_61230_i.INIT = 4'hB; + LUT2 plm_fsm_ri_counter3_N_61230_i ( + .I0(plm_fsm_ri_counter3_reg_tx_expired_2019), + .I1(plm_fsm_ri_counter3_reg_tx_count17_0_a3_0_a2_0_a2_0_a3_0_a2), + .O(plm_fsm_ri_counter3_N_61230_i_2015) + ); + FDCE plm_fsm_ri_counter3_reg_tx_count_7_ ( + .CE(plm_fsm_ri_counter3_N_61100_i_2016), + .C(mgt_clk), + .D(plm_fsm_ri_counter3_reg_tx_count_s[7]), + .Q(plm_fsm_ri_counter3_reg_tx_count[7]), + .CLR(plm_rst) + ); + FDCE plm_fsm_ri_counter3_reg_tx_count_6_ ( + .CE(plm_fsm_ri_counter3_N_61100_i_2016), + .C(mgt_clk), + .D(plm_fsm_ri_counter3_reg_tx_count_s[6]), + .Q(plm_fsm_ri_counter3_reg_tx_count[6]), + .CLR(plm_rst) + ); + FDCE plm_fsm_ri_counter3_reg_tx_count_5_ ( + .CE(plm_fsm_ri_counter3_N_61100_i_2016), + .C(mgt_clk), + .D(plm_fsm_ri_counter3_reg_tx_count_s[5]), + .Q(plm_fsm_ri_counter3_reg_tx_count[5]), + .CLR(plm_rst) + ); + FDCE plm_fsm_ri_counter3_reg_tx_count_4_ ( + .CE(plm_fsm_ri_counter3_N_61100_i_2016), + .C(mgt_clk), + .D(plm_fsm_ri_counter3_reg_tx_count_s[4]), + .Q(plm_fsm_ri_counter3_reg_tx_count[4]), + .CLR(plm_rst) + ); + FDPE plm_fsm_ri_counter3_reg_tx_count_3_ ( + .PRE(plm_rst), + .CE(plm_fsm_ri_counter3_N_61100_i_2016), + .C(mgt_clk), + .D(plm_fsm_ri_counter3_reg_tx_count_s[3]), + .Q(plm_fsm_ri_counter3_reg_tx_count[3]) + ); + FDCE plm_fsm_ri_counter3_reg_tx_count_2_ ( + .CE(plm_fsm_ri_counter3_N_61100_i_2016), + .C(mgt_clk), + .D(plm_fsm_ri_counter3_reg_tx_count_s[2]), + .Q(plm_fsm_ri_counter3_reg_tx_count[2]), + .CLR(plm_rst) + ); + FDCE plm_fsm_ri_counter3_reg_tx_count_1_ ( + .CE(plm_fsm_ri_counter3_N_61100_i_2016), + .C(mgt_clk), + .D(plm_fsm_ri_counter3_reg_tx_count_s[1]), + .Q(plm_fsm_ri_counter3_reg_tx_count[1]), + .CLR(plm_rst) + ); + FDCE plm_fsm_ri_counter3_reg_tx_count_0_ ( + .CE(plm_fsm_ri_counter3_N_61100_i_2016), + .C(mgt_clk), + .D(plm_fsm_ri_counter3_reg_tx_count_s[0]), + .Q(plm_fsm_ri_counter3_reg_tx_count[0]), + .CLR(plm_rst) + ); + FDCE plm_fsm_ri_counter3_reg_rx_count_7_ ( + .CE(plm_fsm_ri_counter3_N_61141_i), + .C(mgt_clk), + .D(plm_fsm_ri_counter3_reg_rx_count_s[7]), + .Q(plm_fsm_ri_counter3_reg_rx_count[7]), + .CLR(plm_rst) + ); + FDCE plm_fsm_ri_counter3_reg_rx_count_6_ ( + .CE(plm_fsm_ri_counter3_N_61141_i), + .C(mgt_clk), + .D(plm_fsm_ri_counter3_reg_rx_count_s[6]), + .Q(plm_fsm_ri_counter3_reg_rx_count[6]), + .CLR(plm_rst) + ); + FDCE plm_fsm_ri_counter3_reg_rx_count_5_ ( + .CE(plm_fsm_ri_counter3_N_61141_i), + .C(mgt_clk), + .D(plm_fsm_ri_counter3_reg_rx_count_s[5]), + .Q(plm_fsm_ri_counter3_reg_rx_count[5]), + .CLR(plm_rst) + ); + FDCE plm_fsm_ri_counter3_reg_rx_count_4_ ( + .CE(plm_fsm_ri_counter3_N_61141_i), + .C(mgt_clk), + .D(plm_fsm_ri_counter3_reg_rx_count_s[4]), + .Q(plm_fsm_ri_counter3_reg_rx_count[4]), + .CLR(plm_rst) + ); + FDCE plm_fsm_ri_counter3_reg_rx_count_3_ ( + .CE(plm_fsm_ri_counter3_N_61141_i), + .C(mgt_clk), + .D(plm_fsm_ri_counter3_reg_rx_count_s[3]), + .Q(plm_fsm_ri_counter3_reg_rx_count[3]), + .CLR(plm_rst) + ); + FDPE plm_fsm_ri_counter3_reg_rx_count_2_ ( + .PRE(plm_rst), + .CE(plm_fsm_ri_counter3_N_61141_i), + .C(mgt_clk), + .D(plm_fsm_ri_counter3_reg_rx_count_s[2]), + .Q(plm_fsm_ri_counter3_reg_rx_count[2]) + ); + FDCE plm_fsm_ri_counter3_reg_rx_count_1_ ( + .CE(plm_fsm_ri_counter3_N_61141_i), + .C(mgt_clk), + .D(plm_fsm_ri_counter3_reg_rx_count_s[1]), + .Q(plm_fsm_ri_counter3_reg_rx_count[1]), + .CLR(plm_rst) + ); + FDCE plm_fsm_ri_counter3_reg_rx_count_0_ ( + .CE(plm_fsm_ri_counter3_N_61141_i), + .C(mgt_clk), + .D(plm_fsm_ri_counter3_reg_rx_count_s[0]), + .Q(plm_fsm_ri_counter3_reg_rx_count[0]), + .CLR(plm_rst) + ); + FDC plm_fsm_ri_counter3_reg_expired ( + .C(mgt_clk), + .D(plm_fsm_ri_counter3_reg_expired_5), + .Q(plm_fsm_ri_cntrout3), + .CLR(plm_rst) + ); + FDCE plm_fsm_ri_counter3_reg_oneshot ( + .CE(plm_fsm_ri_counter3_N_61218_i), + .C(mgt_clk), + .D(plm_fsm_reg_state_16__603), + .Q(plm_fsm_ri_counter3_reg_oneshot_2017), + .CLR(plm_rst) + ); + FDCE plm_fsm_ri_counter3_reg_rx_expired ( + .CE(plm_fsm_ri_counter3_N_61140_i), + .C(mgt_clk), + .D(plm_fsm_reg_state_16__603), + .Q(plm_fsm_ri_counter3_reg_rx_expired_604), + .CLR(plm_rst) + ); + FDCE plm_fsm_ri_counter3_reg_tx_expired ( + .CE(plm_fsm_ri_counter3_N_61058_i_2018), + .C(mgt_clk), + .D(plm_fsm_ri_counter3_reg_tx_count17_0_a3_0_a2_0_a2_0_a3_0_a2), + .Q(plm_fsm_ri_counter3_reg_tx_expired_2019), + .CLR(plm_rst) + ); + INV plm_fsm_ri_counter3_oneshot_monitor_N_61218_i ( + .I(plm_fsm_ri_counter3_un1_enable_0_a2_0_a2_0_a3_0_a2_2), + .O(plm_fsm_ri_counter3_N_61218_i) + ); + defparam plm_fsm_ri_counter3_reg_rx_count_qxu_0_0_.INIT = 4'h7; + LUT2_L plm_fsm_ri_counter3_reg_rx_count_qxu_0_0_ ( + .I0(I_5395_0_a2_0_a2_0_a3_0_a2_52), + .I1(plm_fsm_ri_counter3_reg_rx_count[0]), + .LO(plm_fsm_ri_counter3_reg_rx_count_qxu[0]) + ); + defparam plm_fsm_ri_counter3_reg_rx_count_qxu_0_1_.INIT = 4'h7; + LUT2_L plm_fsm_ri_counter3_reg_rx_count_qxu_0_1_ ( + .I0(I_5395_0_a2_0_a2_0_a3_0_a2_52), + .I1(plm_fsm_ri_counter3_reg_rx_count[1]), + .LO(plm_fsm_ri_counter3_reg_rx_count_qxu[1]) + ); + defparam plm_fsm_ri_counter3_reg_rx_count_qxu_0_2_.INIT = 8'h1B; + LUT3_L plm_fsm_ri_counter3_reg_rx_count_qxu_0_2_ ( + .I0(I_5395_0_a2_0_a2_0_a3_0_a2_52), + .I1(plm_fsm_ri_counter3_N_87174_i_2020), + .I2(plm_fsm_ri_counter3_reg_rx_count[2]), + .LO(plm_fsm_ri_counter3_reg_rx_count_qxu[2]) + ); + defparam plm_fsm_ri_counter3_reg_rx_count_qxu_0_3_.INIT = 4'h7; + LUT2_L plm_fsm_ri_counter3_reg_rx_count_qxu_0_3_ ( + .I0(I_5395_0_a2_0_a2_0_a3_0_a2_52), + .I1(plm_fsm_ri_counter3_reg_rx_count[3]), + .LO(plm_fsm_ri_counter3_reg_rx_count_qxu[3]) + ); + defparam plm_fsm_ri_counter3_reg_rx_count_qxu_0_4_.INIT = 4'h7; + LUT2_L plm_fsm_ri_counter3_reg_rx_count_qxu_0_4_ ( + .I0(I_5395_0_a2_0_a2_0_a3_0_a2_52), + .I1(plm_fsm_ri_counter3_reg_rx_count[4]), + .LO(plm_fsm_ri_counter3_reg_rx_count_qxu[4]) + ); + defparam plm_fsm_ri_counter3_reg_rx_count_qxu_0_5_.INIT = 4'h7; + LUT2_L plm_fsm_ri_counter3_reg_rx_count_qxu_0_5_ ( + .I0(I_5395_0_a2_0_a2_0_a3_0_a2_52), + .I1(plm_fsm_ri_counter3_reg_rx_count[5]), + .LO(plm_fsm_ri_counter3_reg_rx_count_qxu[5]) + ); + defparam plm_fsm_ri_counter3_reg_rx_count_qxu_0_6_.INIT = 4'h7; + LUT2_L plm_fsm_ri_counter3_reg_rx_count_qxu_0_6_ ( + .I0(I_5395_0_a2_0_a2_0_a3_0_a2_52), + .I1(plm_fsm_ri_counter3_reg_rx_count[6]), + .LO(plm_fsm_ri_counter3_reg_rx_count_qxu[6]) + ); + defparam plm_fsm_ri_counter3_reg_rx_count_qxu_0_7_.INIT = 4'h7; + LUT2_L plm_fsm_ri_counter3_reg_rx_count_qxu_0_7_ ( + .I0(I_5395_0_a2_0_a2_0_a3_0_a2_52), + .I1(plm_fsm_ri_counter3_reg_rx_count[7]), + .LO(plm_fsm_ri_counter3_reg_rx_count_qxu[7]) + ); + defparam plm_fsm_ri_counter3_reg_tx_count_qxu_0_0_.INIT = 4'h7; + LUT2_L plm_fsm_ri_counter3_reg_tx_count_qxu_0_0_ ( + .I0(plm_fsm_ri_counter3_un1_enable_1_0_a2_0_a2_0_a2_0_a3_0_a2_2021), + .I1(plm_fsm_ri_counter3_reg_tx_count[0]), + .LO(plm_fsm_ri_counter3_reg_tx_count_qxu[0]) + ); + defparam plm_fsm_ri_counter3_reg_tx_count_qxu_0_1_.INIT = 4'h7; + LUT2_L plm_fsm_ri_counter3_reg_tx_count_qxu_0_1_ ( + .I0(plm_fsm_ri_counter3_un1_enable_1_0_a2_0_a2_0_a2_0_a3_0_a2_2021), + .I1(plm_fsm_ri_counter3_reg_tx_count[1]), + .LO(plm_fsm_ri_counter3_reg_tx_count_qxu[1]) + ); + defparam plm_fsm_ri_counter3_reg_tx_count_qxu_0_2_.INIT = 4'h7; + LUT2_L plm_fsm_ri_counter3_reg_tx_count_qxu_0_2_ ( + .I0(plm_fsm_ri_counter3_un1_enable_1_0_a2_0_a2_0_a2_0_a3_0_a2_2021), + .I1(plm_fsm_ri_counter3_reg_tx_count[2]), + .LO(plm_fsm_ri_counter3_reg_tx_count_qxu[2]) + ); + defparam plm_fsm_ri_counter3_reg_tx_count_qxu_0_3_.INIT = 8'h2E; + LUT3_L plm_fsm_ri_counter3_reg_tx_count_qxu_0_3_ ( + .I0(plm_fsm_ri_counter3_reg_tx_count17_0_a3_0_a2_0_a2_0_a3_0_a2), + .I1(plm_fsm_ri_counter3_un1_enable_1_0_a2_0_a2_0_a2_0_a3_0_a2_2021), + .I2(plm_fsm_ri_counter3_reg_tx_count[3]), + .LO(plm_fsm_ri_counter3_reg_tx_count_qxu[3]) + ); + defparam plm_fsm_ri_counter3_reg_tx_count_qxu_0_4_.INIT = 4'h7; + LUT2_L plm_fsm_ri_counter3_reg_tx_count_qxu_0_4_ ( + .I0(plm_fsm_ri_counter3_un1_enable_1_0_a2_0_a2_0_a2_0_a3_0_a2_2021), + .I1(plm_fsm_ri_counter3_reg_tx_count[4]), + .LO(plm_fsm_ri_counter3_reg_tx_count_qxu[4]) + ); + defparam plm_fsm_ri_counter3_reg_tx_count_qxu_0_5_.INIT = 4'h7; + LUT2_L plm_fsm_ri_counter3_reg_tx_count_qxu_0_5_ ( + .I0(plm_fsm_ri_counter3_un1_enable_1_0_a2_0_a2_0_a2_0_a3_0_a2_2021), + .I1(plm_fsm_ri_counter3_reg_tx_count[5]), + .LO(plm_fsm_ri_counter3_reg_tx_count_qxu[5]) + ); + defparam plm_fsm_ri_counter3_reg_tx_count_qxu_0_6_.INIT = 4'h7; + LUT2_L plm_fsm_ri_counter3_reg_tx_count_qxu_0_6_ ( + .I0(plm_fsm_ri_counter3_un1_enable_1_0_a2_0_a2_0_a2_0_a3_0_a2_2021), + .I1(plm_fsm_ri_counter3_reg_tx_count[6]), + .LO(plm_fsm_ri_counter3_reg_tx_count_qxu[6]) + ); + defparam plm_fsm_ri_counter3_reg_tx_count_qxu_0_7_.INIT = 4'h7; + LUT2_L plm_fsm_ri_counter3_reg_tx_count_qxu_0_7_ ( + .I0(plm_fsm_ri_counter3_un1_enable_1_0_a2_0_a2_0_a2_0_a3_0_a2_2021), + .I1(plm_fsm_ri_counter3_reg_tx_count[7]), + .LO(plm_fsm_ri_counter3_reg_tx_count_qxu[7]) + ); + GND plm_fsm_hr_timer_GND ( + .G(plm_fsm_hr_timer_GND_2022) + ); + MUXCY_L plm_fsm_hr_timer_reg_count_cry_0_ ( + .CI(plm_fsm_un1_reg_state_14_1702), + .DI(plm_fsm_hr_timer_GND_2022), + .LO(plm_fsm_hr_timer_reg_count_cry[0]), + .S(plm_fsm_hr_timer_reg_count_qxu[0]) + ); + XORCY plm_fsm_hr_timer_reg_count_s_0_ ( + .CI(plm_fsm_un1_reg_state_14_1702), + .LI(plm_fsm_hr_timer_reg_count_qxu[0]), + .O(plm_fsm_hr_timer_reg_count_s[0]) + ); + MUXCY_L plm_fsm_hr_timer_reg_count_cry_1_ ( + .CI(plm_fsm_hr_timer_reg_count_cry[0]), + .DI(plm_fsm_hr_timer_GND_2022), + .LO(plm_fsm_hr_timer_reg_count_cry[1]), + .S(plm_fsm_hr_timer_reg_count_qxu[1]) + ); + XORCY plm_fsm_hr_timer_reg_count_s_1_ ( + .CI(plm_fsm_hr_timer_reg_count_cry[0]), + .LI(plm_fsm_hr_timer_reg_count_qxu[1]), + .O(plm_fsm_hr_timer_reg_count_s[1]) + ); + MUXCY_L plm_fsm_hr_timer_reg_count_cry_2_ ( + .CI(plm_fsm_hr_timer_reg_count_cry[1]), + .DI(plm_fsm_hr_timer_GND_2022), + .LO(plm_fsm_hr_timer_reg_count_cry[2]), + .S(plm_fsm_hr_timer_reg_count_qxu[2]) + ); + XORCY plm_fsm_hr_timer_reg_count_s_2_ ( + .CI(plm_fsm_hr_timer_reg_count_cry[1]), + .LI(plm_fsm_hr_timer_reg_count_qxu[2]), + .O(plm_fsm_hr_timer_reg_count_s[2]) + ); + MUXCY_L plm_fsm_hr_timer_reg_count_cry_3_ ( + .CI(plm_fsm_hr_timer_reg_count_cry[2]), + .DI(plm_fsm_hr_timer_GND_2022), + .LO(plm_fsm_hr_timer_reg_count_cry[3]), + .S(plm_fsm_hr_timer_reg_count_qxu[3]) + ); + XORCY plm_fsm_hr_timer_reg_count_s_3_ ( + .CI(plm_fsm_hr_timer_reg_count_cry[2]), + .LI(plm_fsm_hr_timer_reg_count_qxu[3]), + .O(plm_fsm_hr_timer_reg_count_s[3]) + ); + MUXCY_L plm_fsm_hr_timer_reg_count_cry_4_ ( + .CI(plm_fsm_hr_timer_reg_count_cry[3]), + .DI(plm_fsm_hr_timer_GND_2022), + .LO(plm_fsm_hr_timer_reg_count_cry[4]), + .S(plm_fsm_hr_timer_reg_count_qxu[4]) + ); + XORCY plm_fsm_hr_timer_reg_count_s_4_ ( + .CI(plm_fsm_hr_timer_reg_count_cry[3]), + .LI(plm_fsm_hr_timer_reg_count_qxu[4]), + .O(plm_fsm_hr_timer_reg_count_s[4]) + ); + MUXCY_L plm_fsm_hr_timer_reg_count_cry_5_ ( + .CI(plm_fsm_hr_timer_reg_count_cry[4]), + .DI(plm_fsm_hr_timer_GND_2022), + .LO(plm_fsm_hr_timer_reg_count_cry[5]), + .S(plm_fsm_hr_timer_reg_count_qxu[5]) + ); + XORCY plm_fsm_hr_timer_reg_count_s_5_ ( + .CI(plm_fsm_hr_timer_reg_count_cry[4]), + .LI(plm_fsm_hr_timer_reg_count_qxu[5]), + .O(plm_fsm_hr_timer_reg_count_s[5]) + ); + MUXCY_L plm_fsm_hr_timer_reg_count_cry_6_ ( + .CI(plm_fsm_hr_timer_reg_count_cry[5]), + .DI(plm_fsm_hr_timer_GND_2022), + .LO(plm_fsm_hr_timer_reg_count_cry[6]), + .S(plm_fsm_hr_timer_reg_count_qxu[6]) + ); + XORCY plm_fsm_hr_timer_reg_count_s_6_ ( + .CI(plm_fsm_hr_timer_reg_count_cry[5]), + .LI(plm_fsm_hr_timer_reg_count_qxu[6]), + .O(plm_fsm_hr_timer_reg_count_s[6]) + ); + MUXCY_L plm_fsm_hr_timer_reg_count_cry_7_ ( + .CI(plm_fsm_hr_timer_reg_count_cry[6]), + .DI(plm_fsm_hr_timer_GND_2022), + .LO(plm_fsm_hr_timer_reg_count_cry[7]), + .S(plm_fsm_hr_timer_reg_count_qxu[7]) + ); + XORCY plm_fsm_hr_timer_reg_count_s_7_ ( + .CI(plm_fsm_hr_timer_reg_count_cry[6]), + .LI(plm_fsm_hr_timer_reg_count_qxu[7]), + .O(plm_fsm_hr_timer_reg_count_s[7]) + ); + MUXCY_L plm_fsm_hr_timer_reg_count_cry_8_ ( + .CI(plm_fsm_hr_timer_reg_count_cry[7]), + .DI(plm_fsm_hr_timer_GND_2022), + .LO(plm_fsm_hr_timer_reg_count_cry[8]), + .S(plm_fsm_hr_timer_reg_count_qxu[8]) + ); + XORCY plm_fsm_hr_timer_reg_count_s_8_ ( + .CI(plm_fsm_hr_timer_reg_count_cry[7]), + .LI(plm_fsm_hr_timer_reg_count_qxu[8]), + .O(plm_fsm_hr_timer_reg_count_s[8]) + ); + MUXCY_L plm_fsm_hr_timer_reg_count_cry_9_ ( + .CI(plm_fsm_hr_timer_reg_count_cry[8]), + .DI(plm_fsm_hr_timer_GND_2022), + .LO(plm_fsm_hr_timer_reg_count_cry[9]), + .S(plm_fsm_hr_timer_reg_count_qxu[9]) + ); + XORCY plm_fsm_hr_timer_reg_count_s_9_ ( + .CI(plm_fsm_hr_timer_reg_count_cry[8]), + .LI(plm_fsm_hr_timer_reg_count_qxu[9]), + .O(plm_fsm_hr_timer_reg_count_s[9]) + ); + MUXCY_L plm_fsm_hr_timer_reg_count_cry_10_ ( + .CI(plm_fsm_hr_timer_reg_count_cry[9]), + .DI(plm_fsm_hr_timer_GND_2022), + .LO(plm_fsm_hr_timer_reg_count_cry[10]), + .S(plm_fsm_hr_timer_reg_count_qxu[10]) + ); + XORCY plm_fsm_hr_timer_reg_count_s_10_ ( + .CI(plm_fsm_hr_timer_reg_count_cry[9]), + .LI(plm_fsm_hr_timer_reg_count_qxu[10]), + .O(plm_fsm_hr_timer_reg_count_s[10]) + ); + MUXCY_L plm_fsm_hr_timer_reg_count_cry_11_ ( + .CI(plm_fsm_hr_timer_reg_count_cry[10]), + .DI(plm_fsm_hr_timer_GND_2022), + .LO(plm_fsm_hr_timer_reg_count_cry[11]), + .S(plm_fsm_hr_timer_reg_count_qxu[11]) + ); + XORCY plm_fsm_hr_timer_reg_count_s_11_ ( + .CI(plm_fsm_hr_timer_reg_count_cry[10]), + .LI(plm_fsm_hr_timer_reg_count_qxu[11]), + .O(plm_fsm_hr_timer_reg_count_s[11]) + ); + MUXCY_L plm_fsm_hr_timer_reg_count_cry_12_ ( + .CI(plm_fsm_hr_timer_reg_count_cry[11]), + .DI(plm_fsm_hr_timer_GND_2022), + .LO(plm_fsm_hr_timer_reg_count_cry[12]), + .S(plm_fsm_hr_timer_reg_count_qxu[12]) + ); + XORCY plm_fsm_hr_timer_reg_count_s_12_ ( + .CI(plm_fsm_hr_timer_reg_count_cry[11]), + .LI(plm_fsm_hr_timer_reg_count_qxu[12]), + .O(plm_fsm_hr_timer_reg_count_s[12]) + ); + MUXCY_L plm_fsm_hr_timer_reg_count_cry_13_ ( + .CI(plm_fsm_hr_timer_reg_count_cry[12]), + .DI(plm_fsm_hr_timer_GND_2022), + .LO(plm_fsm_hr_timer_reg_count_cry[13]), + .S(plm_fsm_hr_timer_reg_count_qxu[13]) + ); + XORCY plm_fsm_hr_timer_reg_count_s_13_ ( + .CI(plm_fsm_hr_timer_reg_count_cry[12]), + .LI(plm_fsm_hr_timer_reg_count_qxu[13]), + .O(plm_fsm_hr_timer_reg_count_s[13]) + ); + MUXCY_L plm_fsm_hr_timer_reg_count_cry_14_ ( + .CI(plm_fsm_hr_timer_reg_count_cry[13]), + .DI(plm_fsm_hr_timer_GND_2022), + .LO(plm_fsm_hr_timer_reg_count_cry[14]), + .S(plm_fsm_hr_timer_reg_count_qxu[14]) + ); + XORCY plm_fsm_hr_timer_reg_count_s_14_ ( + .CI(plm_fsm_hr_timer_reg_count_cry[13]), + .LI(plm_fsm_hr_timer_reg_count_qxu[14]), + .O(plm_fsm_hr_timer_reg_count_s[14]) + ); + MUXCY_L plm_fsm_hr_timer_reg_count_cry_15_ ( + .CI(plm_fsm_hr_timer_reg_count_cry[14]), + .DI(plm_fsm_hr_timer_GND_2022), + .LO(plm_fsm_hr_timer_reg_count_cry[15]), + .S(plm_fsm_hr_timer_reg_count_qxu[15]) + ); + XORCY plm_fsm_hr_timer_reg_count_s_15_ ( + .CI(plm_fsm_hr_timer_reg_count_cry[14]), + .LI(plm_fsm_hr_timer_reg_count_qxu[15]), + .O(plm_fsm_hr_timer_reg_count_s[15]) + ); + MUXCY_L plm_fsm_hr_timer_reg_count_cry_16_ ( + .CI(plm_fsm_hr_timer_reg_count_cry[15]), + .DI(plm_fsm_hr_timer_GND_2022), + .LO(plm_fsm_hr_timer_reg_count_cry[16]), + .S(plm_fsm_hr_timer_reg_count_qxu[16]) + ); + XORCY plm_fsm_hr_timer_reg_count_s_16_ ( + .CI(plm_fsm_hr_timer_reg_count_cry[15]), + .LI(plm_fsm_hr_timer_reg_count_qxu[16]), + .O(plm_fsm_hr_timer_reg_count_s[16]) + ); + MUXCY_L plm_fsm_hr_timer_reg_count_cry_17_ ( + .CI(plm_fsm_hr_timer_reg_count_cry[16]), + .DI(plm_fsm_hr_timer_GND_2022), + .LO(plm_fsm_hr_timer_reg_count_cry[17]), + .S(plm_fsm_hr_timer_reg_count_qxu[17]) + ); + XORCY plm_fsm_hr_timer_reg_count_s_17_ ( + .CI(plm_fsm_hr_timer_reg_count_cry[16]), + .LI(plm_fsm_hr_timer_reg_count_qxu[17]), + .O(plm_fsm_hr_timer_reg_count_s[17]) + ); + MUXCY_L plm_fsm_hr_timer_reg_count_cry_18_ ( + .CI(plm_fsm_hr_timer_reg_count_cry[17]), + .DI(plm_fsm_hr_timer_GND_2022), + .LO(plm_fsm_hr_timer_reg_count_cry[18]), + .S(plm_fsm_hr_timer_reg_count_qxu[18]) + ); + XORCY plm_fsm_hr_timer_reg_count_s_18_ ( + .CI(plm_fsm_hr_timer_reg_count_cry[17]), + .LI(plm_fsm_hr_timer_reg_count_qxu[18]), + .O(plm_fsm_hr_timer_reg_count_s[18]) + ); + MUXCY_L plm_fsm_hr_timer_reg_count_cry_19_ ( + .CI(plm_fsm_hr_timer_reg_count_cry[18]), + .DI(plm_fsm_hr_timer_GND_2022), + .LO(plm_fsm_hr_timer_reg_count_cry[19]), + .S(plm_fsm_hr_timer_reg_count_qxu[19]) + ); + XORCY plm_fsm_hr_timer_reg_count_s_19_ ( + .CI(plm_fsm_hr_timer_reg_count_cry[18]), + .LI(plm_fsm_hr_timer_reg_count_qxu[19]), + .O(plm_fsm_hr_timer_reg_count_s[19]) + ); + MUXCY_L plm_fsm_hr_timer_reg_count_cry_20_ ( + .CI(plm_fsm_hr_timer_reg_count_cry[19]), + .DI(plm_fsm_hr_timer_GND_2022), + .LO(plm_fsm_hr_timer_reg_count_cry[20]), + .S(plm_fsm_hr_timer_reg_count_qxu[20]) + ); + XORCY plm_fsm_hr_timer_reg_count_s_20_ ( + .CI(plm_fsm_hr_timer_reg_count_cry[19]), + .LI(plm_fsm_hr_timer_reg_count_qxu[20]), + .O(plm_fsm_hr_timer_reg_count_s[20]) + ); + MUXCY_L plm_fsm_hr_timer_reg_count_cry_21_ ( + .CI(plm_fsm_hr_timer_reg_count_cry[20]), + .DI(plm_fsm_hr_timer_GND_2022), + .LO(plm_fsm_hr_timer_reg_count_cry[21]), + .S(plm_fsm_hr_timer_reg_count_qxu[21]) + ); + XORCY plm_fsm_hr_timer_reg_count_s_21_ ( + .CI(plm_fsm_hr_timer_reg_count_cry[20]), + .LI(plm_fsm_hr_timer_reg_count_qxu[21]), + .O(plm_fsm_hr_timer_reg_count_s[21]) + ); + XORCY plm_fsm_hr_timer_reg_count_s_22_ ( + .CI(plm_fsm_hr_timer_reg_count_cry[21]), + .LI(plm_fsm_hr_timer_reg_count_qxu[22]), + .O(plm_fsm_hr_timer_reg_count_s[22]) + ); + defparam plm_fsm_hr_timer_count_i_m3_i_m3_0_18_.INIT = 8'hD8; + LUT3 plm_fsm_hr_timer_count_i_m3_i_m3_0_18_ ( + .I0(cfg_cfg_6102[507]), + .I1(plm_fsm_hr_timer_reg_count[10]), + .I2(plm_fsm_hr_timer_reg_count[18]), + .O(plm_fsm_hr_timer_N_63701) + ); + defparam plm_fsm_hr_timer_count_i_m3_i_m3_0_19_.INIT = 8'hD8; + LUT3_L plm_fsm_hr_timer_count_i_m3_i_m3_0_19_ ( + .I0(cfg_cfg_6102[507]), + .I1(plm_fsm_hr_timer_reg_count[11]), + .I2(plm_fsm_hr_timer_reg_count[19]), + .LO(plm_fsm_hr_timer_N_63702) + ); + defparam plm_fsm_hr_timer_count_i_m3_i_m3_0_20_.INIT = 8'hD8; + LUT3_L plm_fsm_hr_timer_count_i_m3_i_m3_0_20_ ( + .I0(cfg_cfg_6102[507]), + .I1(plm_fsm_hr_timer_reg_count[12]), + .I2(plm_fsm_hr_timer_reg_count[20]), + .LO(plm_fsm_hr_timer_N_63703) + ); + defparam plm_fsm_hr_timer_un1_expired_2ms_0.INIT = 16'h0415; + LUT4 plm_fsm_hr_timer_un1_expired_2ms_0 ( + .I0(plm_fsm_hr_timer_N_63702), + .I1(cfg_cfg_6102[507]), + .I2(plm_fsm_hr_timer_reg_count[14]), + .I3(plm_fsm_hr_timer_reg_count[22]), + .O(plm_fsm_hr_timer_un1_expired_2ms_0_2024) + ); + defparam plm_fsm_hr_timer_un1_expired_2ms_1.INIT = 16'h0415; + LUT4 plm_fsm_hr_timer_un1_expired_2ms_1 ( + .I0(plm_fsm_hr_timer_N_63703), + .I1(cfg_cfg_6102[507]), + .I2(plm_fsm_hr_timer_reg_count[13]), + .I3(plm_fsm_hr_timer_reg_count[21]), + .O(plm_fsm_hr_timer_un1_expired_2ms_1_2023) + ); + defparam plm_fsm_hr_timer_expired.INIT = 16'hBF00; + LUT4 plm_fsm_hr_timer_expired ( + .I0(plm_fsm_hr_timer_N_63701), + .I1(plm_fsm_hr_timer_un1_expired_2ms_0_2024), + .I2(plm_fsm_hr_timer_un1_expired_2ms_1_2023), + .I3(plm_fsm_un1_reg_state_14_1702), + .O(plm_fsm_hr_timeout) + ); + FDC plm_fsm_hr_timer_reg_count_22_ ( + .C(mgt_clk), + .D(plm_fsm_hr_timer_reg_count_s[22]), + .Q(plm_fsm_hr_timer_reg_count[22]), + .CLR(plm_rst) + ); + FDC plm_fsm_hr_timer_reg_count_21_ ( + .C(mgt_clk), + .D(plm_fsm_hr_timer_reg_count_s[21]), + .Q(plm_fsm_hr_timer_reg_count[21]), + .CLR(plm_rst) + ); + FDC plm_fsm_hr_timer_reg_count_20_ ( + .C(mgt_clk), + .D(plm_fsm_hr_timer_reg_count_s[20]), + .Q(plm_fsm_hr_timer_reg_count[20]), + .CLR(plm_rst) + ); + FDC plm_fsm_hr_timer_reg_count_19_ ( + .C(mgt_clk), + .D(plm_fsm_hr_timer_reg_count_s[19]), + .Q(plm_fsm_hr_timer_reg_count[19]), + .CLR(plm_rst) + ); + FDC plm_fsm_hr_timer_reg_count_18_ ( + .C(mgt_clk), + .D(plm_fsm_hr_timer_reg_count_s[18]), + .Q(plm_fsm_hr_timer_reg_count[18]), + .CLR(plm_rst) + ); + FDC plm_fsm_hr_timer_reg_count_17_ ( + .C(mgt_clk), + .D(plm_fsm_hr_timer_reg_count_s[17]), + .Q(plm_fsm_hr_timer_reg_count[17]), + .CLR(plm_rst) + ); + FDC plm_fsm_hr_timer_reg_count_16_ ( + .C(mgt_clk), + .D(plm_fsm_hr_timer_reg_count_s[16]), + .Q(plm_fsm_hr_timer_reg_count[16]), + .CLR(plm_rst) + ); + FDC plm_fsm_hr_timer_reg_count_15_ ( + .C(mgt_clk), + .D(plm_fsm_hr_timer_reg_count_s[15]), + .Q(plm_fsm_hr_timer_reg_count[15]), + .CLR(plm_rst) + ); + FDC plm_fsm_hr_timer_reg_count_14_ ( + .C(mgt_clk), + .D(plm_fsm_hr_timer_reg_count_s[14]), + .Q(plm_fsm_hr_timer_reg_count[14]), + .CLR(plm_rst) + ); + FDC plm_fsm_hr_timer_reg_count_13_ ( + .C(mgt_clk), + .D(plm_fsm_hr_timer_reg_count_s[13]), + .Q(plm_fsm_hr_timer_reg_count[13]), + .CLR(plm_rst) + ); + FDC plm_fsm_hr_timer_reg_count_12_ ( + .C(mgt_clk), + .D(plm_fsm_hr_timer_reg_count_s[12]), + .Q(plm_fsm_hr_timer_reg_count[12]), + .CLR(plm_rst) + ); + FDC plm_fsm_hr_timer_reg_count_11_ ( + .C(mgt_clk), + .D(plm_fsm_hr_timer_reg_count_s[11]), + .Q(plm_fsm_hr_timer_reg_count[11]), + .CLR(plm_rst) + ); + FDC plm_fsm_hr_timer_reg_count_10_ ( + .C(mgt_clk), + .D(plm_fsm_hr_timer_reg_count_s[10]), + .Q(plm_fsm_hr_timer_reg_count[10]), + .CLR(plm_rst) + ); + FDC plm_fsm_hr_timer_reg_count_9_ ( + .C(mgt_clk), + .D(plm_fsm_hr_timer_reg_count_s[9]), + .Q(plm_fsm_hr_timer_reg_count[9]), + .CLR(plm_rst) + ); + FDC plm_fsm_hr_timer_reg_count_8_ ( + .C(mgt_clk), + .D(plm_fsm_hr_timer_reg_count_s[8]), + .Q(plm_fsm_hr_timer_reg_count[8]), + .CLR(plm_rst) + ); + FDC plm_fsm_hr_timer_reg_count_7_ ( + .C(mgt_clk), + .D(plm_fsm_hr_timer_reg_count_s[7]), + .Q(plm_fsm_hr_timer_reg_count[7]), + .CLR(plm_rst) + ); + FDC plm_fsm_hr_timer_reg_count_6_ ( + .C(mgt_clk), + .D(plm_fsm_hr_timer_reg_count_s[6]), + .Q(plm_fsm_hr_timer_reg_count[6]), + .CLR(plm_rst) + ); + FDC plm_fsm_hr_timer_reg_count_5_ ( + .C(mgt_clk), + .D(plm_fsm_hr_timer_reg_count_s[5]), + .Q(plm_fsm_hr_timer_reg_count[5]), + .CLR(plm_rst) + ); + FDC plm_fsm_hr_timer_reg_count_4_ ( + .C(mgt_clk), + .D(plm_fsm_hr_timer_reg_count_s[4]), + .Q(plm_fsm_hr_timer_reg_count[4]), + .CLR(plm_rst) + ); + FDC plm_fsm_hr_timer_reg_count_3_ ( + .C(mgt_clk), + .D(plm_fsm_hr_timer_reg_count_s[3]), + .Q(plm_fsm_hr_timer_reg_count[3]), + .CLR(plm_rst) + ); + FDC plm_fsm_hr_timer_reg_count_2_ ( + .C(mgt_clk), + .D(plm_fsm_hr_timer_reg_count_s[2]), + .Q(plm_fsm_hr_timer_reg_count[2]), + .CLR(plm_rst) + ); + FDC plm_fsm_hr_timer_reg_count_1_ ( + .C(mgt_clk), + .D(plm_fsm_hr_timer_reg_count_s[1]), + .Q(plm_fsm_hr_timer_reg_count[1]), + .CLR(plm_rst) + ); + FDC plm_fsm_hr_timer_reg_count_0_ ( + .C(mgt_clk), + .D(plm_fsm_hr_timer_reg_count_s[0]), + .Q(plm_fsm_hr_timer_reg_count[0]), + .CLR(plm_rst) + ); + defparam plm_fsm_hr_timer_reg_count_qxu_0_0_.INIT = 4'h8; + LUT2_L plm_fsm_hr_timer_reg_count_qxu_0_0_ ( + .I0(plm_fsm_hr_timer_reg_count[0]), + .I1(plm_fsm_un1_reg_state_14_1702), + .LO(plm_fsm_hr_timer_reg_count_qxu[0]) + ); + defparam plm_fsm_hr_timer_reg_count_qxu_0_1_.INIT = 4'h8; + LUT2_L plm_fsm_hr_timer_reg_count_qxu_0_1_ ( + .I0(plm_fsm_hr_timer_reg_count[1]), + .I1(plm_fsm_un1_reg_state_14_1702), + .LO(plm_fsm_hr_timer_reg_count_qxu[1]) + ); + defparam plm_fsm_hr_timer_reg_count_qxu_0_2_.INIT = 4'h8; + LUT2_L plm_fsm_hr_timer_reg_count_qxu_0_2_ ( + .I0(plm_fsm_hr_timer_reg_count[2]), + .I1(plm_fsm_un1_reg_state_14_1702), + .LO(plm_fsm_hr_timer_reg_count_qxu[2]) + ); + defparam plm_fsm_hr_timer_reg_count_qxu_0_3_.INIT = 4'h8; + LUT2_L plm_fsm_hr_timer_reg_count_qxu_0_3_ ( + .I0(plm_fsm_hr_timer_reg_count[3]), + .I1(plm_fsm_un1_reg_state_14_1702), + .LO(plm_fsm_hr_timer_reg_count_qxu[3]) + ); + defparam plm_fsm_hr_timer_reg_count_qxu_0_4_.INIT = 4'h8; + LUT2_L plm_fsm_hr_timer_reg_count_qxu_0_4_ ( + .I0(plm_fsm_hr_timer_reg_count[4]), + .I1(plm_fsm_un1_reg_state_14_1702), + .LO(plm_fsm_hr_timer_reg_count_qxu[4]) + ); + defparam plm_fsm_hr_timer_reg_count_qxu_0_5_.INIT = 4'h8; + LUT2_L plm_fsm_hr_timer_reg_count_qxu_0_5_ ( + .I0(plm_fsm_hr_timer_reg_count[5]), + .I1(plm_fsm_un1_reg_state_14_1702), + .LO(plm_fsm_hr_timer_reg_count_qxu[5]) + ); + defparam plm_fsm_hr_timer_reg_count_qxu_0_6_.INIT = 4'h8; + LUT2_L plm_fsm_hr_timer_reg_count_qxu_0_6_ ( + .I0(plm_fsm_hr_timer_reg_count[6]), + .I1(plm_fsm_un1_reg_state_14_1702), + .LO(plm_fsm_hr_timer_reg_count_qxu[6]) + ); + defparam plm_fsm_hr_timer_reg_count_qxu_0_7_.INIT = 4'h8; + LUT2_L plm_fsm_hr_timer_reg_count_qxu_0_7_ ( + .I0(plm_fsm_hr_timer_reg_count[7]), + .I1(plm_fsm_un1_reg_state_14_1702), + .LO(plm_fsm_hr_timer_reg_count_qxu[7]) + ); + defparam plm_fsm_hr_timer_reg_count_qxu_0_8_.INIT = 4'h8; + LUT2_L plm_fsm_hr_timer_reg_count_qxu_0_8_ ( + .I0(plm_fsm_hr_timer_reg_count[8]), + .I1(plm_fsm_un1_reg_state_14_1702), + .LO(plm_fsm_hr_timer_reg_count_qxu[8]) + ); + defparam plm_fsm_hr_timer_reg_count_qxu_0_9_.INIT = 4'h8; + LUT2_L plm_fsm_hr_timer_reg_count_qxu_0_9_ ( + .I0(plm_fsm_hr_timer_reg_count[9]), + .I1(plm_fsm_un1_reg_state_14_1702), + .LO(plm_fsm_hr_timer_reg_count_qxu[9]) + ); + defparam plm_fsm_hr_timer_reg_count_qxu_0_10_.INIT = 4'h8; + LUT2_L plm_fsm_hr_timer_reg_count_qxu_0_10_ ( + .I0(plm_fsm_hr_timer_reg_count[10]), + .I1(plm_fsm_un1_reg_state_14_1702), + .LO(plm_fsm_hr_timer_reg_count_qxu[10]) + ); + defparam plm_fsm_hr_timer_reg_count_qxu_0_11_.INIT = 4'h8; + LUT2_L plm_fsm_hr_timer_reg_count_qxu_0_11_ ( + .I0(plm_fsm_hr_timer_reg_count[11]), + .I1(plm_fsm_un1_reg_state_14_1702), + .LO(plm_fsm_hr_timer_reg_count_qxu[11]) + ); + defparam plm_fsm_hr_timer_reg_count_qxu_0_12_.INIT = 4'h8; + LUT2_L plm_fsm_hr_timer_reg_count_qxu_0_12_ ( + .I0(plm_fsm_hr_timer_reg_count[12]), + .I1(plm_fsm_un1_reg_state_14_1702), + .LO(plm_fsm_hr_timer_reg_count_qxu[12]) + ); + defparam plm_fsm_hr_timer_reg_count_qxu_0_13_.INIT = 4'h8; + LUT2_L plm_fsm_hr_timer_reg_count_qxu_0_13_ ( + .I0(plm_fsm_hr_timer_reg_count[13]), + .I1(plm_fsm_un1_reg_state_14_1702), + .LO(plm_fsm_hr_timer_reg_count_qxu[13]) + ); + defparam plm_fsm_hr_timer_reg_count_qxu_0_14_.INIT = 4'h8; + LUT2_L plm_fsm_hr_timer_reg_count_qxu_0_14_ ( + .I0(plm_fsm_hr_timer_reg_count[14]), + .I1(plm_fsm_un1_reg_state_14_1702), + .LO(plm_fsm_hr_timer_reg_count_qxu[14]) + ); + defparam plm_fsm_hr_timer_reg_count_qxu_0_15_.INIT = 4'h8; + LUT2_L plm_fsm_hr_timer_reg_count_qxu_0_15_ ( + .I0(plm_fsm_hr_timer_reg_count[15]), + .I1(plm_fsm_un1_reg_state_14_1702), + .LO(plm_fsm_hr_timer_reg_count_qxu[15]) + ); + defparam plm_fsm_hr_timer_reg_count_qxu_0_16_.INIT = 4'h8; + LUT2_L plm_fsm_hr_timer_reg_count_qxu_0_16_ ( + .I0(plm_fsm_hr_timer_reg_count[16]), + .I1(plm_fsm_un1_reg_state_14_1702), + .LO(plm_fsm_hr_timer_reg_count_qxu[16]) + ); + defparam plm_fsm_hr_timer_reg_count_qxu_0_17_.INIT = 4'h8; + LUT2_L plm_fsm_hr_timer_reg_count_qxu_0_17_ ( + .I0(plm_fsm_hr_timer_reg_count[17]), + .I1(plm_fsm_un1_reg_state_14_1702), + .LO(plm_fsm_hr_timer_reg_count_qxu[17]) + ); + defparam plm_fsm_hr_timer_reg_count_qxu_0_18_.INIT = 4'h8; + LUT2_L plm_fsm_hr_timer_reg_count_qxu_0_18_ ( + .I0(plm_fsm_hr_timer_reg_count[18]), + .I1(plm_fsm_un1_reg_state_14_1702), + .LO(plm_fsm_hr_timer_reg_count_qxu[18]) + ); + defparam plm_fsm_hr_timer_reg_count_qxu_0_19_.INIT = 4'h8; + LUT2_L plm_fsm_hr_timer_reg_count_qxu_0_19_ ( + .I0(plm_fsm_hr_timer_reg_count[19]), + .I1(plm_fsm_un1_reg_state_14_1702), + .LO(plm_fsm_hr_timer_reg_count_qxu[19]) + ); + defparam plm_fsm_hr_timer_reg_count_qxu_0_20_.INIT = 4'h8; + LUT2_L plm_fsm_hr_timer_reg_count_qxu_0_20_ ( + .I0(plm_fsm_hr_timer_reg_count[20]), + .I1(plm_fsm_un1_reg_state_14_1702), + .LO(plm_fsm_hr_timer_reg_count_qxu[20]) + ); + defparam plm_fsm_hr_timer_reg_count_qxu_0_21_.INIT = 4'h8; + LUT2_L plm_fsm_hr_timer_reg_count_qxu_0_21_ ( + .I0(plm_fsm_hr_timer_reg_count[21]), + .I1(plm_fsm_un1_reg_state_14_1702), + .LO(plm_fsm_hr_timer_reg_count_qxu[21]) + ); + defparam plm_fsm_hr_timer_reg_count_qxu_0_22_.INIT = 4'h8; + LUT2_L plm_fsm_hr_timer_reg_count_qxu_0_22_ ( + .I0(plm_fsm_hr_timer_reg_count[22]), + .I1(plm_fsm_un1_reg_state_14_1702), + .LO(plm_fsm_hr_timer_reg_count_qxu[22]) + ); + GND plm_fsm_xl_cls_timer_GND ( + .G(plm_fsm_xl_cls_timer_GND_2025) + ); + MUXCY_L plm_fsm_xl_cls_timer_reg_count_cry_0_ ( + .CI(plm_fsm_un1_reg_state_4_i_i_1774), + .DI(plm_fsm_xl_cls_timer_GND_2025), + .LO(plm_fsm_xl_cls_timer_reg_count_cry[0]), + .S(plm_fsm_xl_cls_timer_reg_count_qxu[0]) + ); + XORCY plm_fsm_xl_cls_timer_reg_count_s_0_ ( + .CI(plm_fsm_un1_reg_state_4_i_i_1774), + .LI(plm_fsm_xl_cls_timer_reg_count_qxu[0]), + .O(plm_fsm_xl_cls_timer_reg_count_s[0]) + ); + MUXCY_L plm_fsm_xl_cls_timer_reg_count_cry_1_ ( + .CI(plm_fsm_xl_cls_timer_reg_count_cry[0]), + .DI(plm_fsm_xl_cls_timer_GND_2025), + .LO(plm_fsm_xl_cls_timer_reg_count_cry[1]), + .S(plm_fsm_xl_cls_timer_reg_count_qxu[1]) + ); + XORCY plm_fsm_xl_cls_timer_reg_count_s_1_ ( + .CI(plm_fsm_xl_cls_timer_reg_count_cry[0]), + .LI(plm_fsm_xl_cls_timer_reg_count_qxu[1]), + .O(plm_fsm_xl_cls_timer_reg_count_s[1]) + ); + MUXCY_L plm_fsm_xl_cls_timer_reg_count_cry_2_ ( + .CI(plm_fsm_xl_cls_timer_reg_count_cry[1]), + .DI(plm_fsm_xl_cls_timer_GND_2025), + .LO(plm_fsm_xl_cls_timer_reg_count_cry[2]), + .S(plm_fsm_xl_cls_timer_reg_count_qxu[2]) + ); + XORCY plm_fsm_xl_cls_timer_reg_count_s_2_ ( + .CI(plm_fsm_xl_cls_timer_reg_count_cry[1]), + .LI(plm_fsm_xl_cls_timer_reg_count_qxu[2]), + .O(plm_fsm_xl_cls_timer_reg_count_s[2]) + ); + MUXCY_L plm_fsm_xl_cls_timer_reg_count_cry_3_ ( + .CI(plm_fsm_xl_cls_timer_reg_count_cry[2]), + .DI(plm_fsm_xl_cls_timer_GND_2025), + .LO(plm_fsm_xl_cls_timer_reg_count_cry[3]), + .S(plm_fsm_xl_cls_timer_reg_count_qxu[3]) + ); + XORCY plm_fsm_xl_cls_timer_reg_count_s_3_ ( + .CI(plm_fsm_xl_cls_timer_reg_count_cry[2]), + .LI(plm_fsm_xl_cls_timer_reg_count_qxu[3]), + .O(plm_fsm_xl_cls_timer_reg_count_s[3]) + ); + MUXCY_L plm_fsm_xl_cls_timer_reg_count_cry_4_ ( + .CI(plm_fsm_xl_cls_timer_reg_count_cry[3]), + .DI(plm_fsm_xl_cls_timer_GND_2025), + .LO(plm_fsm_xl_cls_timer_reg_count_cry[4]), + .S(plm_fsm_xl_cls_timer_reg_count_qxu[4]) + ); + XORCY plm_fsm_xl_cls_timer_reg_count_s_4_ ( + .CI(plm_fsm_xl_cls_timer_reg_count_cry[3]), + .LI(plm_fsm_xl_cls_timer_reg_count_qxu[4]), + .O(plm_fsm_xl_cls_timer_reg_count_s[4]) + ); + MUXCY_L plm_fsm_xl_cls_timer_reg_count_cry_5_ ( + .CI(plm_fsm_xl_cls_timer_reg_count_cry[4]), + .DI(plm_fsm_xl_cls_timer_GND_2025), + .LO(plm_fsm_xl_cls_timer_reg_count_cry[5]), + .S(plm_fsm_xl_cls_timer_reg_count_qxu[5]) + ); + XORCY plm_fsm_xl_cls_timer_reg_count_s_5_ ( + .CI(plm_fsm_xl_cls_timer_reg_count_cry[4]), + .LI(plm_fsm_xl_cls_timer_reg_count_qxu[5]), + .O(plm_fsm_xl_cls_timer_reg_count_s[5]) + ); + MUXCY_L plm_fsm_xl_cls_timer_reg_count_cry_6_ ( + .CI(plm_fsm_xl_cls_timer_reg_count_cry[5]), + .DI(plm_fsm_xl_cls_timer_GND_2025), + .LO(plm_fsm_xl_cls_timer_reg_count_cry[6]), + .S(plm_fsm_xl_cls_timer_reg_count_qxu[6]) + ); + XORCY plm_fsm_xl_cls_timer_reg_count_s_6_ ( + .CI(plm_fsm_xl_cls_timer_reg_count_cry[5]), + .LI(plm_fsm_xl_cls_timer_reg_count_qxu[6]), + .O(plm_fsm_xl_cls_timer_reg_count_s[6]) + ); + MUXCY_L plm_fsm_xl_cls_timer_reg_count_cry_7_ ( + .CI(plm_fsm_xl_cls_timer_reg_count_cry[6]), + .DI(plm_fsm_xl_cls_timer_GND_2025), + .LO(plm_fsm_xl_cls_timer_reg_count_cry[7]), + .S(plm_fsm_xl_cls_timer_reg_count_qxu[7]) + ); + XORCY plm_fsm_xl_cls_timer_reg_count_s_7_ ( + .CI(plm_fsm_xl_cls_timer_reg_count_cry[6]), + .LI(plm_fsm_xl_cls_timer_reg_count_qxu[7]), + .O(plm_fsm_xl_cls_timer_reg_count_s[7]) + ); + MUXCY_L plm_fsm_xl_cls_timer_reg_count_cry_8_ ( + .CI(plm_fsm_xl_cls_timer_reg_count_cry[7]), + .DI(plm_fsm_xl_cls_timer_GND_2025), + .LO(plm_fsm_xl_cls_timer_reg_count_cry[8]), + .S(plm_fsm_xl_cls_timer_reg_count_qxu[8]) + ); + XORCY plm_fsm_xl_cls_timer_reg_count_s_8_ ( + .CI(plm_fsm_xl_cls_timer_reg_count_cry[7]), + .LI(plm_fsm_xl_cls_timer_reg_count_qxu[8]), + .O(plm_fsm_xl_cls_timer_reg_count_s[8]) + ); + MUXCY_L plm_fsm_xl_cls_timer_reg_count_cry_9_ ( + .CI(plm_fsm_xl_cls_timer_reg_count_cry[8]), + .DI(plm_fsm_xl_cls_timer_GND_2025), + .LO(plm_fsm_xl_cls_timer_reg_count_cry[9]), + .S(plm_fsm_xl_cls_timer_reg_count_qxu[9]) + ); + XORCY plm_fsm_xl_cls_timer_reg_count_s_9_ ( + .CI(plm_fsm_xl_cls_timer_reg_count_cry[8]), + .LI(plm_fsm_xl_cls_timer_reg_count_qxu[9]), + .O(plm_fsm_xl_cls_timer_reg_count_s[9]) + ); + MUXCY_L plm_fsm_xl_cls_timer_reg_count_cry_10_ ( + .CI(plm_fsm_xl_cls_timer_reg_count_cry[9]), + .DI(plm_fsm_xl_cls_timer_GND_2025), + .LO(plm_fsm_xl_cls_timer_reg_count_cry[10]), + .S(plm_fsm_xl_cls_timer_reg_count_qxu[10]) + ); + XORCY plm_fsm_xl_cls_timer_reg_count_s_10_ ( + .CI(plm_fsm_xl_cls_timer_reg_count_cry[9]), + .LI(plm_fsm_xl_cls_timer_reg_count_qxu[10]), + .O(plm_fsm_xl_cls_timer_reg_count_s[10]) + ); + MUXCY_L plm_fsm_xl_cls_timer_reg_count_cry_11_ ( + .CI(plm_fsm_xl_cls_timer_reg_count_cry[10]), + .DI(plm_fsm_xl_cls_timer_GND_2025), + .LO(plm_fsm_xl_cls_timer_reg_count_cry[11]), + .S(plm_fsm_xl_cls_timer_reg_count_qxu[11]) + ); + XORCY plm_fsm_xl_cls_timer_reg_count_s_11_ ( + .CI(plm_fsm_xl_cls_timer_reg_count_cry[10]), + .LI(plm_fsm_xl_cls_timer_reg_count_qxu[11]), + .O(plm_fsm_xl_cls_timer_reg_count_s[11]) + ); + MUXCY_L plm_fsm_xl_cls_timer_reg_count_cry_12_ ( + .CI(plm_fsm_xl_cls_timer_reg_count_cry[11]), + .DI(plm_fsm_xl_cls_timer_GND_2025), + .LO(plm_fsm_xl_cls_timer_reg_count_cry[12]), + .S(plm_fsm_xl_cls_timer_reg_count_qxu[12]) + ); + XORCY plm_fsm_xl_cls_timer_reg_count_s_12_ ( + .CI(plm_fsm_xl_cls_timer_reg_count_cry[11]), + .LI(plm_fsm_xl_cls_timer_reg_count_qxu[12]), + .O(plm_fsm_xl_cls_timer_reg_count_s[12]) + ); + MUXCY_L plm_fsm_xl_cls_timer_reg_count_cry_13_ ( + .CI(plm_fsm_xl_cls_timer_reg_count_cry[12]), + .DI(plm_fsm_xl_cls_timer_GND_2025), + .LO(plm_fsm_xl_cls_timer_reg_count_cry[13]), + .S(plm_fsm_xl_cls_timer_reg_count_qxu[13]) + ); + XORCY plm_fsm_xl_cls_timer_reg_count_s_13_ ( + .CI(plm_fsm_xl_cls_timer_reg_count_cry[12]), + .LI(plm_fsm_xl_cls_timer_reg_count_qxu[13]), + .O(plm_fsm_xl_cls_timer_reg_count_s[13]) + ); + MUXCY_L plm_fsm_xl_cls_timer_reg_count_cry_14_ ( + .CI(plm_fsm_xl_cls_timer_reg_count_cry[13]), + .DI(plm_fsm_xl_cls_timer_GND_2025), + .LO(plm_fsm_xl_cls_timer_reg_count_cry[14]), + .S(plm_fsm_xl_cls_timer_reg_count_qxu[14]) + ); + XORCY plm_fsm_xl_cls_timer_reg_count_s_14_ ( + .CI(plm_fsm_xl_cls_timer_reg_count_cry[13]), + .LI(plm_fsm_xl_cls_timer_reg_count_qxu[14]), + .O(plm_fsm_xl_cls_timer_reg_count_s[14]) + ); + MUXCY_L plm_fsm_xl_cls_timer_reg_count_cry_15_ ( + .CI(plm_fsm_xl_cls_timer_reg_count_cry[14]), + .DI(plm_fsm_xl_cls_timer_GND_2025), + .LO(plm_fsm_xl_cls_timer_reg_count_cry[15]), + .S(plm_fsm_xl_cls_timer_reg_count_qxu[15]) + ); + XORCY plm_fsm_xl_cls_timer_reg_count_s_15_ ( + .CI(plm_fsm_xl_cls_timer_reg_count_cry[14]), + .LI(plm_fsm_xl_cls_timer_reg_count_qxu[15]), + .O(plm_fsm_xl_cls_timer_reg_count_s[15]) + ); + MUXCY_L plm_fsm_xl_cls_timer_reg_count_cry_16_ ( + .CI(plm_fsm_xl_cls_timer_reg_count_cry[15]), + .DI(plm_fsm_xl_cls_timer_GND_2025), + .LO(plm_fsm_xl_cls_timer_reg_count_cry[16]), + .S(plm_fsm_xl_cls_timer_reg_count_qxu[16]) + ); + XORCY plm_fsm_xl_cls_timer_reg_count_s_16_ ( + .CI(plm_fsm_xl_cls_timer_reg_count_cry[15]), + .LI(plm_fsm_xl_cls_timer_reg_count_qxu[16]), + .O(plm_fsm_xl_cls_timer_reg_count_s[16]) + ); + MUXCY_L plm_fsm_xl_cls_timer_reg_count_cry_17_ ( + .CI(plm_fsm_xl_cls_timer_reg_count_cry[16]), + .DI(plm_fsm_xl_cls_timer_GND_2025), + .LO(plm_fsm_xl_cls_timer_reg_count_cry[17]), + .S(plm_fsm_xl_cls_timer_reg_count_qxu[17]) + ); + XORCY plm_fsm_xl_cls_timer_reg_count_s_17_ ( + .CI(plm_fsm_xl_cls_timer_reg_count_cry[16]), + .LI(plm_fsm_xl_cls_timer_reg_count_qxu[17]), + .O(plm_fsm_xl_cls_timer_reg_count_s[17]) + ); + MUXCY_L plm_fsm_xl_cls_timer_reg_count_cry_18_ ( + .CI(plm_fsm_xl_cls_timer_reg_count_cry[17]), + .DI(plm_fsm_xl_cls_timer_GND_2025), + .LO(plm_fsm_xl_cls_timer_reg_count_cry[18]), + .S(plm_fsm_xl_cls_timer_reg_count_qxu[18]) + ); + XORCY plm_fsm_xl_cls_timer_reg_count_s_18_ ( + .CI(plm_fsm_xl_cls_timer_reg_count_cry[17]), + .LI(plm_fsm_xl_cls_timer_reg_count_qxu[18]), + .O(plm_fsm_xl_cls_timer_reg_count_s[18]) + ); + MUXCY_L plm_fsm_xl_cls_timer_reg_count_cry_19_ ( + .CI(plm_fsm_xl_cls_timer_reg_count_cry[18]), + .DI(plm_fsm_xl_cls_timer_GND_2025), + .LO(plm_fsm_xl_cls_timer_reg_count_cry[19]), + .S(plm_fsm_xl_cls_timer_reg_count_qxu[19]) + ); + XORCY plm_fsm_xl_cls_timer_reg_count_s_19_ ( + .CI(plm_fsm_xl_cls_timer_reg_count_cry[18]), + .LI(plm_fsm_xl_cls_timer_reg_count_qxu[19]), + .O(plm_fsm_xl_cls_timer_reg_count_s[19]) + ); + MUXCY_L plm_fsm_xl_cls_timer_reg_count_cry_20_ ( + .CI(plm_fsm_xl_cls_timer_reg_count_cry[19]), + .DI(plm_fsm_xl_cls_timer_GND_2025), + .LO(plm_fsm_xl_cls_timer_reg_count_cry[20]), + .S(plm_fsm_xl_cls_timer_reg_count_qxu[20]) + ); + XORCY plm_fsm_xl_cls_timer_reg_count_s_20_ ( + .CI(plm_fsm_xl_cls_timer_reg_count_cry[19]), + .LI(plm_fsm_xl_cls_timer_reg_count_qxu[20]), + .O(plm_fsm_xl_cls_timer_reg_count_s[20]) + ); + MUXCY_L plm_fsm_xl_cls_timer_reg_count_cry_21_ ( + .CI(plm_fsm_xl_cls_timer_reg_count_cry[20]), + .DI(plm_fsm_xl_cls_timer_GND_2025), + .LO(plm_fsm_xl_cls_timer_reg_count_cry[21]), + .S(plm_fsm_xl_cls_timer_reg_count_qxu[21]) + ); + XORCY plm_fsm_xl_cls_timer_reg_count_s_21_ ( + .CI(plm_fsm_xl_cls_timer_reg_count_cry[20]), + .LI(plm_fsm_xl_cls_timer_reg_count_qxu[21]), + .O(plm_fsm_xl_cls_timer_reg_count_s[21]) + ); + XORCY plm_fsm_xl_cls_timer_reg_count_s_22_ ( + .CI(plm_fsm_xl_cls_timer_reg_count_cry[21]), + .LI(plm_fsm_xl_cls_timer_reg_count_qxu[22]), + .O(plm_fsm_xl_cls_timer_reg_count_s[22]) + ); + defparam plm_fsm_xl_cls_timer_count_i_m3_i_m3_0_20_.INIT = 8'hD8; + LUT3 plm_fsm_xl_cls_timer_count_i_m3_i_m3_0_20_ ( + .I0(cfg_cfg_6102[507]), + .I1(plm_fsm_xl_cls_timer_reg_count[12]), + .I2(plm_fsm_xl_cls_timer_reg_count[20]), + .O(plm_fsm_xl_cls_timer_N_63688) + ); + defparam plm_fsm_xl_cls_timer_count_i_m3_i_m3_0_21_.INIT = 8'hD8; + LUT3 plm_fsm_xl_cls_timer_count_i_m3_i_m3_0_21_ ( + .I0(cfg_cfg_6102[507]), + .I1(plm_fsm_xl_cls_timer_reg_count[13]), + .I2(plm_fsm_xl_cls_timer_reg_count[21]), + .O(plm_fsm_xl_cls_timer_N_63689) + ); + defparam plm_fsm_xl_cls_timer_count_i_m3_i_m3_0_22_.INIT = 8'hD8; + LUT3 plm_fsm_xl_cls_timer_count_i_m3_i_m3_0_22_ ( + .I0(cfg_cfg_6102[507]), + .I1(plm_fsm_xl_cls_timer_reg_count[14]), + .I2(plm_fsm_xl_cls_timer_reg_count[22]), + .O(plm_fsm_xl_cls_timer_N_63690) + ); + defparam plm_fsm_xl_cls_timer_expired.INIT = 16'h00F8; + LUT4 plm_fsm_xl_cls_timer_expired ( + .I0(plm_fsm_xl_cls_timer_N_63688), + .I1(plm_fsm_xl_cls_timer_N_63689), + .I2(plm_fsm_xl_cls_timer_N_63690), + .I3(plm_fsm_un1_reg_state_4_i), + .O(plm_fsm_xl_cls_timeout) + ); + FDC plm_fsm_xl_cls_timer_reg_count_22_ ( + .C(mgt_clk), + .D(plm_fsm_xl_cls_timer_reg_count_s[22]), + .Q(plm_fsm_xl_cls_timer_reg_count[22]), + .CLR(plm_rst) + ); + FDC plm_fsm_xl_cls_timer_reg_count_21_ ( + .C(mgt_clk), + .D(plm_fsm_xl_cls_timer_reg_count_s[21]), + .Q(plm_fsm_xl_cls_timer_reg_count[21]), + .CLR(plm_rst) + ); + FDC plm_fsm_xl_cls_timer_reg_count_20_ ( + .C(mgt_clk), + .D(plm_fsm_xl_cls_timer_reg_count_s[20]), + .Q(plm_fsm_xl_cls_timer_reg_count[20]), + .CLR(plm_rst) + ); + FDC plm_fsm_xl_cls_timer_reg_count_19_ ( + .C(mgt_clk), + .D(plm_fsm_xl_cls_timer_reg_count_s[19]), + .Q(plm_fsm_xl_cls_timer_reg_count[19]), + .CLR(plm_rst) + ); + FDC plm_fsm_xl_cls_timer_reg_count_18_ ( + .C(mgt_clk), + .D(plm_fsm_xl_cls_timer_reg_count_s[18]), + .Q(plm_fsm_xl_cls_timer_reg_count[18]), + .CLR(plm_rst) + ); + FDC plm_fsm_xl_cls_timer_reg_count_17_ ( + .C(mgt_clk), + .D(plm_fsm_xl_cls_timer_reg_count_s[17]), + .Q(plm_fsm_xl_cls_timer_reg_count[17]), + .CLR(plm_rst) + ); + FDC plm_fsm_xl_cls_timer_reg_count_16_ ( + .C(mgt_clk), + .D(plm_fsm_xl_cls_timer_reg_count_s[16]), + .Q(plm_fsm_xl_cls_timer_reg_count[16]), + .CLR(plm_rst) + ); + FDC plm_fsm_xl_cls_timer_reg_count_15_ ( + .C(mgt_clk), + .D(plm_fsm_xl_cls_timer_reg_count_s[15]), + .Q(plm_fsm_xl_cls_timer_reg_count[15]), + .CLR(plm_rst) + ); + FDC plm_fsm_xl_cls_timer_reg_count_14_ ( + .C(mgt_clk), + .D(plm_fsm_xl_cls_timer_reg_count_s[14]), + .Q(plm_fsm_xl_cls_timer_reg_count[14]), + .CLR(plm_rst) + ); + FDC plm_fsm_xl_cls_timer_reg_count_13_ ( + .C(mgt_clk), + .D(plm_fsm_xl_cls_timer_reg_count_s[13]), + .Q(plm_fsm_xl_cls_timer_reg_count[13]), + .CLR(plm_rst) + ); + FDC plm_fsm_xl_cls_timer_reg_count_12_ ( + .C(mgt_clk), + .D(plm_fsm_xl_cls_timer_reg_count_s[12]), + .Q(plm_fsm_xl_cls_timer_reg_count[12]), + .CLR(plm_rst) + ); + FDC plm_fsm_xl_cls_timer_reg_count_11_ ( + .C(mgt_clk), + .D(plm_fsm_xl_cls_timer_reg_count_s[11]), + .Q(plm_fsm_xl_cls_timer_reg_count[11]), + .CLR(plm_rst) + ); + FDC plm_fsm_xl_cls_timer_reg_count_10_ ( + .C(mgt_clk), + .D(plm_fsm_xl_cls_timer_reg_count_s[10]), + .Q(plm_fsm_xl_cls_timer_reg_count[10]), + .CLR(plm_rst) + ); + FDC plm_fsm_xl_cls_timer_reg_count_9_ ( + .C(mgt_clk), + .D(plm_fsm_xl_cls_timer_reg_count_s[9]), + .Q(plm_fsm_xl_cls_timer_reg_count[9]), + .CLR(plm_rst) + ); + FDC plm_fsm_xl_cls_timer_reg_count_8_ ( + .C(mgt_clk), + .D(plm_fsm_xl_cls_timer_reg_count_s[8]), + .Q(plm_fsm_xl_cls_timer_reg_count[8]), + .CLR(plm_rst) + ); + FDC plm_fsm_xl_cls_timer_reg_count_7_ ( + .C(mgt_clk), + .D(plm_fsm_xl_cls_timer_reg_count_s[7]), + .Q(plm_fsm_xl_cls_timer_reg_count[7]), + .CLR(plm_rst) + ); + FDC plm_fsm_xl_cls_timer_reg_count_6_ ( + .C(mgt_clk), + .D(plm_fsm_xl_cls_timer_reg_count_s[6]), + .Q(plm_fsm_xl_cls_timer_reg_count[6]), + .CLR(plm_rst) + ); + FDC plm_fsm_xl_cls_timer_reg_count_5_ ( + .C(mgt_clk), + .D(plm_fsm_xl_cls_timer_reg_count_s[5]), + .Q(plm_fsm_xl_cls_timer_reg_count[5]), + .CLR(plm_rst) + ); + FDC plm_fsm_xl_cls_timer_reg_count_4_ ( + .C(mgt_clk), + .D(plm_fsm_xl_cls_timer_reg_count_s[4]), + .Q(plm_fsm_xl_cls_timer_reg_count[4]), + .CLR(plm_rst) + ); + FDC plm_fsm_xl_cls_timer_reg_count_3_ ( + .C(mgt_clk), + .D(plm_fsm_xl_cls_timer_reg_count_s[3]), + .Q(plm_fsm_xl_cls_timer_reg_count[3]), + .CLR(plm_rst) + ); + FDC plm_fsm_xl_cls_timer_reg_count_2_ ( + .C(mgt_clk), + .D(plm_fsm_xl_cls_timer_reg_count_s[2]), + .Q(plm_fsm_xl_cls_timer_reg_count[2]), + .CLR(plm_rst) + ); + FDC plm_fsm_xl_cls_timer_reg_count_1_ ( + .C(mgt_clk), + .D(plm_fsm_xl_cls_timer_reg_count_s[1]), + .Q(plm_fsm_xl_cls_timer_reg_count[1]), + .CLR(plm_rst) + ); + FDC plm_fsm_xl_cls_timer_reg_count_0_ ( + .C(mgt_clk), + .D(plm_fsm_xl_cls_timer_reg_count_s[0]), + .Q(plm_fsm_xl_cls_timer_reg_count[0]), + .CLR(plm_rst) + ); + defparam plm_fsm_xl_cls_timer_reg_count_qxu_0_0_.INIT = 4'h4; + LUT2_L plm_fsm_xl_cls_timer_reg_count_qxu_0_0_ ( + .I0(plm_fsm_un1_reg_state_4_i), + .I1(plm_fsm_xl_cls_timer_reg_count[0]), + .LO(plm_fsm_xl_cls_timer_reg_count_qxu[0]) + ); + defparam plm_fsm_xl_cls_timer_reg_count_qxu_0_1_.INIT = 4'h4; + LUT2_L plm_fsm_xl_cls_timer_reg_count_qxu_0_1_ ( + .I0(plm_fsm_un1_reg_state_4_i), + .I1(plm_fsm_xl_cls_timer_reg_count[1]), + .LO(plm_fsm_xl_cls_timer_reg_count_qxu[1]) + ); + defparam plm_fsm_xl_cls_timer_reg_count_qxu_0_2_.INIT = 4'h4; + LUT2_L plm_fsm_xl_cls_timer_reg_count_qxu_0_2_ ( + .I0(plm_fsm_un1_reg_state_4_i), + .I1(plm_fsm_xl_cls_timer_reg_count[2]), + .LO(plm_fsm_xl_cls_timer_reg_count_qxu[2]) + ); + defparam plm_fsm_xl_cls_timer_reg_count_qxu_0_3_.INIT = 4'h4; + LUT2_L plm_fsm_xl_cls_timer_reg_count_qxu_0_3_ ( + .I0(plm_fsm_un1_reg_state_4_i), + .I1(plm_fsm_xl_cls_timer_reg_count[3]), + .LO(plm_fsm_xl_cls_timer_reg_count_qxu[3]) + ); + defparam plm_fsm_xl_cls_timer_reg_count_qxu_0_4_.INIT = 4'h4; + LUT2_L plm_fsm_xl_cls_timer_reg_count_qxu_0_4_ ( + .I0(plm_fsm_un1_reg_state_4_i), + .I1(plm_fsm_xl_cls_timer_reg_count[4]), + .LO(plm_fsm_xl_cls_timer_reg_count_qxu[4]) + ); + defparam plm_fsm_xl_cls_timer_reg_count_qxu_0_5_.INIT = 4'h4; + LUT2_L plm_fsm_xl_cls_timer_reg_count_qxu_0_5_ ( + .I0(plm_fsm_un1_reg_state_4_i), + .I1(plm_fsm_xl_cls_timer_reg_count[5]), + .LO(plm_fsm_xl_cls_timer_reg_count_qxu[5]) + ); + defparam plm_fsm_xl_cls_timer_reg_count_qxu_0_6_.INIT = 4'h4; + LUT2_L plm_fsm_xl_cls_timer_reg_count_qxu_0_6_ ( + .I0(plm_fsm_un1_reg_state_4_i), + .I1(plm_fsm_xl_cls_timer_reg_count[6]), + .LO(plm_fsm_xl_cls_timer_reg_count_qxu[6]) + ); + defparam plm_fsm_xl_cls_timer_reg_count_qxu_0_7_.INIT = 4'h4; + LUT2_L plm_fsm_xl_cls_timer_reg_count_qxu_0_7_ ( + .I0(plm_fsm_un1_reg_state_4_i), + .I1(plm_fsm_xl_cls_timer_reg_count[7]), + .LO(plm_fsm_xl_cls_timer_reg_count_qxu[7]) + ); + defparam plm_fsm_xl_cls_timer_reg_count_qxu_0_8_.INIT = 4'h4; + LUT2_L plm_fsm_xl_cls_timer_reg_count_qxu_0_8_ ( + .I0(plm_fsm_un1_reg_state_4_i), + .I1(plm_fsm_xl_cls_timer_reg_count[8]), + .LO(plm_fsm_xl_cls_timer_reg_count_qxu[8]) + ); + defparam plm_fsm_xl_cls_timer_reg_count_qxu_0_9_.INIT = 4'h4; + LUT2_L plm_fsm_xl_cls_timer_reg_count_qxu_0_9_ ( + .I0(plm_fsm_un1_reg_state_4_i), + .I1(plm_fsm_xl_cls_timer_reg_count[9]), + .LO(plm_fsm_xl_cls_timer_reg_count_qxu[9]) + ); + defparam plm_fsm_xl_cls_timer_reg_count_qxu_0_10_.INIT = 4'h4; + LUT2_L plm_fsm_xl_cls_timer_reg_count_qxu_0_10_ ( + .I0(plm_fsm_un1_reg_state_4_i), + .I1(plm_fsm_xl_cls_timer_reg_count[10]), + .LO(plm_fsm_xl_cls_timer_reg_count_qxu[10]) + ); + defparam plm_fsm_xl_cls_timer_reg_count_qxu_0_11_.INIT = 4'h4; + LUT2_L plm_fsm_xl_cls_timer_reg_count_qxu_0_11_ ( + .I0(plm_fsm_un1_reg_state_4_i), + .I1(plm_fsm_xl_cls_timer_reg_count[11]), + .LO(plm_fsm_xl_cls_timer_reg_count_qxu[11]) + ); + defparam plm_fsm_xl_cls_timer_reg_count_qxu_0_12_.INIT = 4'h4; + LUT2_L plm_fsm_xl_cls_timer_reg_count_qxu_0_12_ ( + .I0(plm_fsm_un1_reg_state_4_i), + .I1(plm_fsm_xl_cls_timer_reg_count[12]), + .LO(plm_fsm_xl_cls_timer_reg_count_qxu[12]) + ); + defparam plm_fsm_xl_cls_timer_reg_count_qxu_0_13_.INIT = 4'h4; + LUT2_L plm_fsm_xl_cls_timer_reg_count_qxu_0_13_ ( + .I0(plm_fsm_un1_reg_state_4_i), + .I1(plm_fsm_xl_cls_timer_reg_count[13]), + .LO(plm_fsm_xl_cls_timer_reg_count_qxu[13]) + ); + defparam plm_fsm_xl_cls_timer_reg_count_qxu_0_14_.INIT = 4'h4; + LUT2_L plm_fsm_xl_cls_timer_reg_count_qxu_0_14_ ( + .I0(plm_fsm_un1_reg_state_4_i), + .I1(plm_fsm_xl_cls_timer_reg_count[14]), + .LO(plm_fsm_xl_cls_timer_reg_count_qxu[14]) + ); + defparam plm_fsm_xl_cls_timer_reg_count_qxu_0_15_.INIT = 4'h4; + LUT2_L plm_fsm_xl_cls_timer_reg_count_qxu_0_15_ ( + .I0(plm_fsm_un1_reg_state_4_i), + .I1(plm_fsm_xl_cls_timer_reg_count[15]), + .LO(plm_fsm_xl_cls_timer_reg_count_qxu[15]) + ); + defparam plm_fsm_xl_cls_timer_reg_count_qxu_0_16_.INIT = 4'h4; + LUT2_L plm_fsm_xl_cls_timer_reg_count_qxu_0_16_ ( + .I0(plm_fsm_un1_reg_state_4_i), + .I1(plm_fsm_xl_cls_timer_reg_count[16]), + .LO(plm_fsm_xl_cls_timer_reg_count_qxu[16]) + ); + defparam plm_fsm_xl_cls_timer_reg_count_qxu_0_17_.INIT = 4'h4; + LUT2_L plm_fsm_xl_cls_timer_reg_count_qxu_0_17_ ( + .I0(plm_fsm_un1_reg_state_4_i), + .I1(plm_fsm_xl_cls_timer_reg_count[17]), + .LO(plm_fsm_xl_cls_timer_reg_count_qxu[17]) + ); + defparam plm_fsm_xl_cls_timer_reg_count_qxu_0_18_.INIT = 4'h4; + LUT2_L plm_fsm_xl_cls_timer_reg_count_qxu_0_18_ ( + .I0(plm_fsm_un1_reg_state_4_i), + .I1(plm_fsm_xl_cls_timer_reg_count[18]), + .LO(plm_fsm_xl_cls_timer_reg_count_qxu[18]) + ); + defparam plm_fsm_xl_cls_timer_reg_count_qxu_0_19_.INIT = 4'h4; + LUT2_L plm_fsm_xl_cls_timer_reg_count_qxu_0_19_ ( + .I0(plm_fsm_un1_reg_state_4_i), + .I1(plm_fsm_xl_cls_timer_reg_count[19]), + .LO(plm_fsm_xl_cls_timer_reg_count_qxu[19]) + ); + defparam plm_fsm_xl_cls_timer_reg_count_qxu_0_20_.INIT = 4'h4; + LUT2_L plm_fsm_xl_cls_timer_reg_count_qxu_0_20_ ( + .I0(plm_fsm_un1_reg_state_4_i), + .I1(plm_fsm_xl_cls_timer_reg_count[20]), + .LO(plm_fsm_xl_cls_timer_reg_count_qxu[20]) + ); + defparam plm_fsm_xl_cls_timer_reg_count_qxu_0_21_.INIT = 4'h4; + LUT2_L plm_fsm_xl_cls_timer_reg_count_qxu_0_21_ ( + .I0(plm_fsm_un1_reg_state_4_i), + .I1(plm_fsm_xl_cls_timer_reg_count[21]), + .LO(plm_fsm_xl_cls_timer_reg_count_qxu[21]) + ); + defparam plm_fsm_xl_cls_timer_reg_count_qxu_0_22_.INIT = 4'h4; + LUT2_L plm_fsm_xl_cls_timer_reg_count_qxu_0_22_ ( + .I0(plm_fsm_un1_reg_state_4_i), + .I1(plm_fsm_xl_cls_timer_reg_count[22]), + .LO(plm_fsm_xl_cls_timer_reg_count_qxu[22]) + ); + GND plm_fsm_xl_cla_timer_GND ( + .G(plm_fsm_xl_cla_timer_GND_2026) + ); + MUXCY_L plm_fsm_xl_cla_timer_reg_count_cry_0_ ( + .CI(plm_fsm_xl_cla_timer_un1_reg_state_5_i_i_2028), + .DI(plm_fsm_xl_cla_timer_GND_2026), + .LO(plm_fsm_xl_cla_timer_reg_count_cry[0]), + .S(plm_fsm_xl_cla_timer_reg_count_qxu[0]) + ); + XORCY plm_fsm_xl_cla_timer_reg_count_s_0_ ( + .CI(plm_fsm_xl_cla_timer_un1_reg_state_5_i_i_2028), + .LI(plm_fsm_xl_cla_timer_reg_count_qxu[0]), + .O(plm_fsm_xl_cla_timer_reg_count_s[0]) + ); + MUXCY_L plm_fsm_xl_cla_timer_reg_count_cry_1_ ( + .CI(plm_fsm_xl_cla_timer_reg_count_cry[0]), + .DI(plm_fsm_xl_cla_timer_GND_2026), + .LO(plm_fsm_xl_cla_timer_reg_count_cry[1]), + .S(plm_fsm_xl_cla_timer_reg_count_qxu[1]) + ); + XORCY plm_fsm_xl_cla_timer_reg_count_s_1_ ( + .CI(plm_fsm_xl_cla_timer_reg_count_cry[0]), + .LI(plm_fsm_xl_cla_timer_reg_count_qxu[1]), + .O(plm_fsm_xl_cla_timer_reg_count_s[1]) + ); + MUXCY_L plm_fsm_xl_cla_timer_reg_count_cry_2_ ( + .CI(plm_fsm_xl_cla_timer_reg_count_cry[1]), + .DI(plm_fsm_xl_cla_timer_GND_2026), + .LO(plm_fsm_xl_cla_timer_reg_count_cry[2]), + .S(plm_fsm_xl_cla_timer_reg_count_qxu[2]) + ); + XORCY plm_fsm_xl_cla_timer_reg_count_s_2_ ( + .CI(plm_fsm_xl_cla_timer_reg_count_cry[1]), + .LI(plm_fsm_xl_cla_timer_reg_count_qxu[2]), + .O(plm_fsm_xl_cla_timer_reg_count_s[2]) + ); + MUXCY_L plm_fsm_xl_cla_timer_reg_count_cry_3_ ( + .CI(plm_fsm_xl_cla_timer_reg_count_cry[2]), + .DI(plm_fsm_xl_cla_timer_GND_2026), + .LO(plm_fsm_xl_cla_timer_reg_count_cry[3]), + .S(plm_fsm_xl_cla_timer_reg_count_qxu[3]) + ); + XORCY plm_fsm_xl_cla_timer_reg_count_s_3_ ( + .CI(plm_fsm_xl_cla_timer_reg_count_cry[2]), + .LI(plm_fsm_xl_cla_timer_reg_count_qxu[3]), + .O(plm_fsm_xl_cla_timer_reg_count_s[3]) + ); + MUXCY_L plm_fsm_xl_cla_timer_reg_count_cry_4_ ( + .CI(plm_fsm_xl_cla_timer_reg_count_cry[3]), + .DI(plm_fsm_xl_cla_timer_GND_2026), + .LO(plm_fsm_xl_cla_timer_reg_count_cry[4]), + .S(plm_fsm_xl_cla_timer_reg_count_qxu[4]) + ); + XORCY plm_fsm_xl_cla_timer_reg_count_s_4_ ( + .CI(plm_fsm_xl_cla_timer_reg_count_cry[3]), + .LI(plm_fsm_xl_cla_timer_reg_count_qxu[4]), + .O(plm_fsm_xl_cla_timer_reg_count_s[4]) + ); + MUXCY_L plm_fsm_xl_cla_timer_reg_count_cry_5_ ( + .CI(plm_fsm_xl_cla_timer_reg_count_cry[4]), + .DI(plm_fsm_xl_cla_timer_GND_2026), + .LO(plm_fsm_xl_cla_timer_reg_count_cry[5]), + .S(plm_fsm_xl_cla_timer_reg_count_qxu[5]) + ); + XORCY plm_fsm_xl_cla_timer_reg_count_s_5_ ( + .CI(plm_fsm_xl_cla_timer_reg_count_cry[4]), + .LI(plm_fsm_xl_cla_timer_reg_count_qxu[5]), + .O(plm_fsm_xl_cla_timer_reg_count_s[5]) + ); + MUXCY_L plm_fsm_xl_cla_timer_reg_count_cry_6_ ( + .CI(plm_fsm_xl_cla_timer_reg_count_cry[5]), + .DI(plm_fsm_xl_cla_timer_GND_2026), + .LO(plm_fsm_xl_cla_timer_reg_count_cry[6]), + .S(plm_fsm_xl_cla_timer_reg_count_qxu[6]) + ); + XORCY plm_fsm_xl_cla_timer_reg_count_s_6_ ( + .CI(plm_fsm_xl_cla_timer_reg_count_cry[5]), + .LI(plm_fsm_xl_cla_timer_reg_count_qxu[6]), + .O(plm_fsm_xl_cla_timer_reg_count_s[6]) + ); + MUXCY_L plm_fsm_xl_cla_timer_reg_count_cry_7_ ( + .CI(plm_fsm_xl_cla_timer_reg_count_cry[6]), + .DI(plm_fsm_xl_cla_timer_GND_2026), + .LO(plm_fsm_xl_cla_timer_reg_count_cry[7]), + .S(plm_fsm_xl_cla_timer_reg_count_qxu[7]) + ); + XORCY plm_fsm_xl_cla_timer_reg_count_s_7_ ( + .CI(plm_fsm_xl_cla_timer_reg_count_cry[6]), + .LI(plm_fsm_xl_cla_timer_reg_count_qxu[7]), + .O(plm_fsm_xl_cla_timer_reg_count_s[7]) + ); + MUXCY_L plm_fsm_xl_cla_timer_reg_count_cry_8_ ( + .CI(plm_fsm_xl_cla_timer_reg_count_cry[7]), + .DI(plm_fsm_xl_cla_timer_GND_2026), + .LO(plm_fsm_xl_cla_timer_reg_count_cry[8]), + .S(plm_fsm_xl_cla_timer_reg_count_qxu[8]) + ); + XORCY plm_fsm_xl_cla_timer_reg_count_s_8_ ( + .CI(plm_fsm_xl_cla_timer_reg_count_cry[7]), + .LI(plm_fsm_xl_cla_timer_reg_count_qxu[8]), + .O(plm_fsm_xl_cla_timer_reg_count_s[8]) + ); + MUXCY_L plm_fsm_xl_cla_timer_reg_count_cry_9_ ( + .CI(plm_fsm_xl_cla_timer_reg_count_cry[8]), + .DI(plm_fsm_xl_cla_timer_GND_2026), + .LO(plm_fsm_xl_cla_timer_reg_count_cry[9]), + .S(plm_fsm_xl_cla_timer_reg_count_qxu[9]) + ); + XORCY plm_fsm_xl_cla_timer_reg_count_s_9_ ( + .CI(plm_fsm_xl_cla_timer_reg_count_cry[8]), + .LI(plm_fsm_xl_cla_timer_reg_count_qxu[9]), + .O(plm_fsm_xl_cla_timer_reg_count_s[9]) + ); + MUXCY_L plm_fsm_xl_cla_timer_reg_count_cry_10_ ( + .CI(plm_fsm_xl_cla_timer_reg_count_cry[9]), + .DI(plm_fsm_xl_cla_timer_GND_2026), + .LO(plm_fsm_xl_cla_timer_reg_count_cry[10]), + .S(plm_fsm_xl_cla_timer_reg_count_qxu[10]) + ); + XORCY plm_fsm_xl_cla_timer_reg_count_s_10_ ( + .CI(plm_fsm_xl_cla_timer_reg_count_cry[9]), + .LI(plm_fsm_xl_cla_timer_reg_count_qxu[10]), + .O(plm_fsm_xl_cla_timer_reg_count_s[10]) + ); + MUXCY_L plm_fsm_xl_cla_timer_reg_count_cry_11_ ( + .CI(plm_fsm_xl_cla_timer_reg_count_cry[10]), + .DI(plm_fsm_xl_cla_timer_GND_2026), + .LO(plm_fsm_xl_cla_timer_reg_count_cry[11]), + .S(plm_fsm_xl_cla_timer_reg_count_qxu[11]) + ); + XORCY plm_fsm_xl_cla_timer_reg_count_s_11_ ( + .CI(plm_fsm_xl_cla_timer_reg_count_cry[10]), + .LI(plm_fsm_xl_cla_timer_reg_count_qxu[11]), + .O(plm_fsm_xl_cla_timer_reg_count_s[11]) + ); + MUXCY_L plm_fsm_xl_cla_timer_reg_count_cry_12_ ( + .CI(plm_fsm_xl_cla_timer_reg_count_cry[11]), + .DI(plm_fsm_xl_cla_timer_GND_2026), + .LO(plm_fsm_xl_cla_timer_reg_count_cry[12]), + .S(plm_fsm_xl_cla_timer_reg_count_qxu[12]) + ); + XORCY plm_fsm_xl_cla_timer_reg_count_s_12_ ( + .CI(plm_fsm_xl_cla_timer_reg_count_cry[11]), + .LI(plm_fsm_xl_cla_timer_reg_count_qxu[12]), + .O(plm_fsm_xl_cla_timer_reg_count_s[12]) + ); + MUXCY_L plm_fsm_xl_cla_timer_reg_count_cry_13_ ( + .CI(plm_fsm_xl_cla_timer_reg_count_cry[12]), + .DI(plm_fsm_xl_cla_timer_GND_2026), + .LO(plm_fsm_xl_cla_timer_reg_count_cry[13]), + .S(plm_fsm_xl_cla_timer_reg_count_qxu[13]) + ); + XORCY plm_fsm_xl_cla_timer_reg_count_s_13_ ( + .CI(plm_fsm_xl_cla_timer_reg_count_cry[12]), + .LI(plm_fsm_xl_cla_timer_reg_count_qxu[13]), + .O(plm_fsm_xl_cla_timer_reg_count_s[13]) + ); + MUXCY_L plm_fsm_xl_cla_timer_reg_count_cry_14_ ( + .CI(plm_fsm_xl_cla_timer_reg_count_cry[13]), + .DI(plm_fsm_xl_cla_timer_GND_2026), + .LO(plm_fsm_xl_cla_timer_reg_count_cry[14]), + .S(plm_fsm_xl_cla_timer_reg_count_qxu[14]) + ); + XORCY plm_fsm_xl_cla_timer_reg_count_s_14_ ( + .CI(plm_fsm_xl_cla_timer_reg_count_cry[13]), + .LI(plm_fsm_xl_cla_timer_reg_count_qxu[14]), + .O(plm_fsm_xl_cla_timer_reg_count_s[14]) + ); + MUXCY_L plm_fsm_xl_cla_timer_reg_count_cry_15_ ( + .CI(plm_fsm_xl_cla_timer_reg_count_cry[14]), + .DI(plm_fsm_xl_cla_timer_GND_2026), + .LO(plm_fsm_xl_cla_timer_reg_count_cry[15]), + .S(plm_fsm_xl_cla_timer_reg_count_qxu[15]) + ); + XORCY plm_fsm_xl_cla_timer_reg_count_s_15_ ( + .CI(plm_fsm_xl_cla_timer_reg_count_cry[14]), + .LI(plm_fsm_xl_cla_timer_reg_count_qxu[15]), + .O(plm_fsm_xl_cla_timer_reg_count_s[15]) + ); + MUXCY_L plm_fsm_xl_cla_timer_reg_count_cry_16_ ( + .CI(plm_fsm_xl_cla_timer_reg_count_cry[15]), + .DI(plm_fsm_xl_cla_timer_GND_2026), + .LO(plm_fsm_xl_cla_timer_reg_count_cry[16]), + .S(plm_fsm_xl_cla_timer_reg_count_qxu[16]) + ); + XORCY plm_fsm_xl_cla_timer_reg_count_s_16_ ( + .CI(plm_fsm_xl_cla_timer_reg_count_cry[15]), + .LI(plm_fsm_xl_cla_timer_reg_count_qxu[16]), + .O(plm_fsm_xl_cla_timer_reg_count_s[16]) + ); + MUXCY_L plm_fsm_xl_cla_timer_reg_count_cry_17_ ( + .CI(plm_fsm_xl_cla_timer_reg_count_cry[16]), + .DI(plm_fsm_xl_cla_timer_GND_2026), + .LO(plm_fsm_xl_cla_timer_reg_count_cry[17]), + .S(plm_fsm_xl_cla_timer_reg_count_qxu[17]) + ); + XORCY plm_fsm_xl_cla_timer_reg_count_s_17_ ( + .CI(plm_fsm_xl_cla_timer_reg_count_cry[16]), + .LI(plm_fsm_xl_cla_timer_reg_count_qxu[17]), + .O(plm_fsm_xl_cla_timer_reg_count_s[17]) + ); + MUXCY_L plm_fsm_xl_cla_timer_reg_count_cry_18_ ( + .CI(plm_fsm_xl_cla_timer_reg_count_cry[17]), + .DI(plm_fsm_xl_cla_timer_GND_2026), + .LO(plm_fsm_xl_cla_timer_reg_count_cry[18]), + .S(plm_fsm_xl_cla_timer_reg_count_qxu[18]) + ); + XORCY plm_fsm_xl_cla_timer_reg_count_s_18_ ( + .CI(plm_fsm_xl_cla_timer_reg_count_cry[17]), + .LI(plm_fsm_xl_cla_timer_reg_count_qxu[18]), + .O(plm_fsm_xl_cla_timer_reg_count_s[18]) + ); + MUXCY_L plm_fsm_xl_cla_timer_reg_count_cry_19_ ( + .CI(plm_fsm_xl_cla_timer_reg_count_cry[18]), + .DI(plm_fsm_xl_cla_timer_GND_2026), + .LO(plm_fsm_xl_cla_timer_reg_count_cry[19]), + .S(plm_fsm_xl_cla_timer_reg_count_qxu[19]) + ); + XORCY plm_fsm_xl_cla_timer_reg_count_s_19_ ( + .CI(plm_fsm_xl_cla_timer_reg_count_cry[18]), + .LI(plm_fsm_xl_cla_timer_reg_count_qxu[19]), + .O(plm_fsm_xl_cla_timer_reg_count_s[19]) + ); + MUXCY_L plm_fsm_xl_cla_timer_reg_count_cry_20_ ( + .CI(plm_fsm_xl_cla_timer_reg_count_cry[19]), + .DI(plm_fsm_xl_cla_timer_GND_2026), + .LO(plm_fsm_xl_cla_timer_reg_count_cry[20]), + .S(plm_fsm_xl_cla_timer_reg_count_qxu[20]) + ); + XORCY plm_fsm_xl_cla_timer_reg_count_s_20_ ( + .CI(plm_fsm_xl_cla_timer_reg_count_cry[19]), + .LI(plm_fsm_xl_cla_timer_reg_count_qxu[20]), + .O(plm_fsm_xl_cla_timer_reg_count_s[20]) + ); + MUXCY_L plm_fsm_xl_cla_timer_reg_count_cry_21_ ( + .CI(plm_fsm_xl_cla_timer_reg_count_cry[20]), + .DI(plm_fsm_xl_cla_timer_GND_2026), + .LO(plm_fsm_xl_cla_timer_reg_count_cry[21]), + .S(plm_fsm_xl_cla_timer_reg_count_qxu[21]) + ); + XORCY plm_fsm_xl_cla_timer_reg_count_s_21_ ( + .CI(plm_fsm_xl_cla_timer_reg_count_cry[20]), + .LI(plm_fsm_xl_cla_timer_reg_count_qxu[21]), + .O(plm_fsm_xl_cla_timer_reg_count_s[21]) + ); + XORCY plm_fsm_xl_cla_timer_reg_count_s_22_ ( + .CI(plm_fsm_xl_cla_timer_reg_count_cry[21]), + .LI(plm_fsm_xl_cla_timer_reg_count_qxu[22]), + .O(plm_fsm_xl_cla_timer_reg_count_s[22]) + ); + defparam plm_fsm_xl_cla_timer_count_i_m3_i_m3_0_18_.INIT = 8'hD8; + LUT3 plm_fsm_xl_cla_timer_count_i_m3_i_m3_0_18_ ( + .I0(cfg_cfg_6102[507]), + .I1(plm_fsm_xl_cla_timer_reg_count[10]), + .I2(plm_fsm_xl_cla_timer_reg_count[18]), + .O(plm_fsm_xl_cla_timer_N_63691) + ); + defparam plm_fsm_xl_cla_timer_count_i_m3_i_m3_0_19_.INIT = 8'hD8; + LUT3_L plm_fsm_xl_cla_timer_count_i_m3_i_m3_0_19_ ( + .I0(cfg_cfg_6102[507]), + .I1(plm_fsm_xl_cla_timer_reg_count[11]), + .I2(plm_fsm_xl_cla_timer_reg_count[19]), + .LO(plm_fsm_xl_cla_timer_N_63692) + ); + defparam plm_fsm_xl_cla_timer_count_i_m3_i_m3_0_21_.INIT = 8'hD8; + LUT3 plm_fsm_xl_cla_timer_count_i_m3_i_m3_0_21_ ( + .I0(cfg_cfg_6102[507]), + .I1(plm_fsm_xl_cla_timer_reg_count[13]), + .I2(plm_fsm_xl_cla_timer_reg_count[21]), + .O(plm_fsm_xl_cla_timer_N_63694) + ); + defparam plm_fsm_xl_cla_timer_count_i_m3_i_m3_0_20_.INIT = 8'hD8; + LUT3 plm_fsm_xl_cla_timer_count_i_m3_i_m3_0_20_ ( + .I0(cfg_cfg_6102[507]), + .I1(plm_fsm_xl_cla_timer_reg_count[12]), + .I2(plm_fsm_xl_cla_timer_reg_count[20]), + .O(plm_fsm_xl_cla_timer_N_63693) + ); + defparam plm_fsm_xl_cla_timer_un1_reg_state_5_i_i.INIT = 4'hE; + LUT2 plm_fsm_xl_cla_timer_un1_reg_state_5_i_i ( + .I0(plm_fsm_reg_state_21__1786), + .I1(plm_fsm_reg_state_22__1785), + .O(plm_fsm_xl_cla_timer_un1_reg_state_5_i_i_2028) + ); + defparam plm_fsm_xl_cla_timer_un1_expired_2ms_0_a2_0.INIT = 16'h0415; + LUT4_L plm_fsm_xl_cla_timer_un1_expired_2ms_0_a2_0 ( + .I0(plm_fsm_xl_cla_timer_N_63692), + .I1(cfg_cfg_6102[507]), + .I2(plm_fsm_xl_cla_timer_reg_count[14]), + .I3(plm_fsm_xl_cla_timer_reg_count[22]), + .LO(plm_fsm_xl_cla_timer_un1_expired_2ms_0_a2_0_2027) + ); + defparam plm_fsm_xl_cla_timer_un1_expired_2ms_0_a2.INIT = 16'h0100; + LUT4 plm_fsm_xl_cla_timer_un1_expired_2ms_0_a2 ( + .I0(plm_fsm_xl_cla_timer_N_63691), + .I1(plm_fsm_xl_cla_timer_N_63693), + .I2(plm_fsm_xl_cla_timer_N_63694), + .I3(plm_fsm_xl_cla_timer_un1_expired_2ms_0_a2_0_2027), + .O(plm_fsm_N_63249) + ); + FDC plm_fsm_xl_cla_timer_reg_count_22_ ( + .C(mgt_clk), + .D(plm_fsm_xl_cla_timer_reg_count_s[22]), + .Q(plm_fsm_xl_cla_timer_reg_count[22]), + .CLR(plm_rst) + ); + FDC plm_fsm_xl_cla_timer_reg_count_21_ ( + .C(mgt_clk), + .D(plm_fsm_xl_cla_timer_reg_count_s[21]), + .Q(plm_fsm_xl_cla_timer_reg_count[21]), + .CLR(plm_rst) + ); + FDC plm_fsm_xl_cla_timer_reg_count_20_ ( + .C(mgt_clk), + .D(plm_fsm_xl_cla_timer_reg_count_s[20]), + .Q(plm_fsm_xl_cla_timer_reg_count[20]), + .CLR(plm_rst) + ); + FDC plm_fsm_xl_cla_timer_reg_count_19_ ( + .C(mgt_clk), + .D(plm_fsm_xl_cla_timer_reg_count_s[19]), + .Q(plm_fsm_xl_cla_timer_reg_count[19]), + .CLR(plm_rst) + ); + FDC plm_fsm_xl_cla_timer_reg_count_18_ ( + .C(mgt_clk), + .D(plm_fsm_xl_cla_timer_reg_count_s[18]), + .Q(plm_fsm_xl_cla_timer_reg_count[18]), + .CLR(plm_rst) + ); + FDC plm_fsm_xl_cla_timer_reg_count_17_ ( + .C(mgt_clk), + .D(plm_fsm_xl_cla_timer_reg_count_s[17]), + .Q(plm_fsm_xl_cla_timer_reg_count[17]), + .CLR(plm_rst) + ); + FDC plm_fsm_xl_cla_timer_reg_count_16_ ( + .C(mgt_clk), + .D(plm_fsm_xl_cla_timer_reg_count_s[16]), + .Q(plm_fsm_xl_cla_timer_reg_count[16]), + .CLR(plm_rst) + ); + FDC plm_fsm_xl_cla_timer_reg_count_15_ ( + .C(mgt_clk), + .D(plm_fsm_xl_cla_timer_reg_count_s[15]), + .Q(plm_fsm_xl_cla_timer_reg_count[15]), + .CLR(plm_rst) + ); + FDC plm_fsm_xl_cla_timer_reg_count_14_ ( + .C(mgt_clk), + .D(plm_fsm_xl_cla_timer_reg_count_s[14]), + .Q(plm_fsm_xl_cla_timer_reg_count[14]), + .CLR(plm_rst) + ); + FDC plm_fsm_xl_cla_timer_reg_count_13_ ( + .C(mgt_clk), + .D(plm_fsm_xl_cla_timer_reg_count_s[13]), + .Q(plm_fsm_xl_cla_timer_reg_count[13]), + .CLR(plm_rst) + ); + FDC plm_fsm_xl_cla_timer_reg_count_12_ ( + .C(mgt_clk), + .D(plm_fsm_xl_cla_timer_reg_count_s[12]), + .Q(plm_fsm_xl_cla_timer_reg_count[12]), + .CLR(plm_rst) + ); + FDC plm_fsm_xl_cla_timer_reg_count_11_ ( + .C(mgt_clk), + .D(plm_fsm_xl_cla_timer_reg_count_s[11]), + .Q(plm_fsm_xl_cla_timer_reg_count[11]), + .CLR(plm_rst) + ); + FDC plm_fsm_xl_cla_timer_reg_count_10_ ( + .C(mgt_clk), + .D(plm_fsm_xl_cla_timer_reg_count_s[10]), + .Q(plm_fsm_xl_cla_timer_reg_count[10]), + .CLR(plm_rst) + ); + FDC plm_fsm_xl_cla_timer_reg_count_9_ ( + .C(mgt_clk), + .D(plm_fsm_xl_cla_timer_reg_count_s[9]), + .Q(plm_fsm_xl_cla_timer_reg_count[9]), + .CLR(plm_rst) + ); + FDC plm_fsm_xl_cla_timer_reg_count_8_ ( + .C(mgt_clk), + .D(plm_fsm_xl_cla_timer_reg_count_s[8]), + .Q(plm_fsm_xl_cla_timer_reg_count[8]), + .CLR(plm_rst) + ); + FDC plm_fsm_xl_cla_timer_reg_count_7_ ( + .C(mgt_clk), + .D(plm_fsm_xl_cla_timer_reg_count_s[7]), + .Q(plm_fsm_xl_cla_timer_reg_count[7]), + .CLR(plm_rst) + ); + FDC plm_fsm_xl_cla_timer_reg_count_6_ ( + .C(mgt_clk), + .D(plm_fsm_xl_cla_timer_reg_count_s[6]), + .Q(plm_fsm_xl_cla_timer_reg_count[6]), + .CLR(plm_rst) + ); + FDC plm_fsm_xl_cla_timer_reg_count_5_ ( + .C(mgt_clk), + .D(plm_fsm_xl_cla_timer_reg_count_s[5]), + .Q(plm_fsm_xl_cla_timer_reg_count[5]), + .CLR(plm_rst) + ); + FDC plm_fsm_xl_cla_timer_reg_count_4_ ( + .C(mgt_clk), + .D(plm_fsm_xl_cla_timer_reg_count_s[4]), + .Q(plm_fsm_xl_cla_timer_reg_count[4]), + .CLR(plm_rst) + ); + FDC plm_fsm_xl_cla_timer_reg_count_3_ ( + .C(mgt_clk), + .D(plm_fsm_xl_cla_timer_reg_count_s[3]), + .Q(plm_fsm_xl_cla_timer_reg_count[3]), + .CLR(plm_rst) + ); + FDC plm_fsm_xl_cla_timer_reg_count_2_ ( + .C(mgt_clk), + .D(plm_fsm_xl_cla_timer_reg_count_s[2]), + .Q(plm_fsm_xl_cla_timer_reg_count[2]), + .CLR(plm_rst) + ); + FDC plm_fsm_xl_cla_timer_reg_count_1_ ( + .C(mgt_clk), + .D(plm_fsm_xl_cla_timer_reg_count_s[1]), + .Q(plm_fsm_xl_cla_timer_reg_count[1]), + .CLR(plm_rst) + ); + FDC plm_fsm_xl_cla_timer_reg_count_0_ ( + .C(mgt_clk), + .D(plm_fsm_xl_cla_timer_reg_count_s[0]), + .Q(plm_fsm_xl_cla_timer_reg_count[0]), + .CLR(plm_rst) + ); + defparam plm_fsm_xl_cla_timer_reg_count_qxu_0_0_.INIT = 4'h8; + LUT2_L plm_fsm_xl_cla_timer_reg_count_qxu_0_0_ ( + .I0(plm_fsm_xl_cla_timer_un1_reg_state_5_i_i_2028), + .I1(plm_fsm_xl_cla_timer_reg_count[0]), + .LO(plm_fsm_xl_cla_timer_reg_count_qxu[0]) + ); + defparam plm_fsm_xl_cla_timer_reg_count_qxu_0_1_.INIT = 4'h8; + LUT2_L plm_fsm_xl_cla_timer_reg_count_qxu_0_1_ ( + .I0(plm_fsm_xl_cla_timer_un1_reg_state_5_i_i_2028), + .I1(plm_fsm_xl_cla_timer_reg_count[1]), + .LO(plm_fsm_xl_cla_timer_reg_count_qxu[1]) + ); + defparam plm_fsm_xl_cla_timer_reg_count_qxu_0_2_.INIT = 4'h8; + LUT2_L plm_fsm_xl_cla_timer_reg_count_qxu_0_2_ ( + .I0(plm_fsm_xl_cla_timer_un1_reg_state_5_i_i_2028), + .I1(plm_fsm_xl_cla_timer_reg_count[2]), + .LO(plm_fsm_xl_cla_timer_reg_count_qxu[2]) + ); + defparam plm_fsm_xl_cla_timer_reg_count_qxu_0_3_.INIT = 4'h8; + LUT2_L plm_fsm_xl_cla_timer_reg_count_qxu_0_3_ ( + .I0(plm_fsm_xl_cla_timer_un1_reg_state_5_i_i_2028), + .I1(plm_fsm_xl_cla_timer_reg_count[3]), + .LO(plm_fsm_xl_cla_timer_reg_count_qxu[3]) + ); + defparam plm_fsm_xl_cla_timer_reg_count_qxu_0_4_.INIT = 4'h8; + LUT2_L plm_fsm_xl_cla_timer_reg_count_qxu_0_4_ ( + .I0(plm_fsm_xl_cla_timer_un1_reg_state_5_i_i_2028), + .I1(plm_fsm_xl_cla_timer_reg_count[4]), + .LO(plm_fsm_xl_cla_timer_reg_count_qxu[4]) + ); + defparam plm_fsm_xl_cla_timer_reg_count_qxu_0_5_.INIT = 4'h8; + LUT2_L plm_fsm_xl_cla_timer_reg_count_qxu_0_5_ ( + .I0(plm_fsm_xl_cla_timer_un1_reg_state_5_i_i_2028), + .I1(plm_fsm_xl_cla_timer_reg_count[5]), + .LO(plm_fsm_xl_cla_timer_reg_count_qxu[5]) + ); + defparam plm_fsm_xl_cla_timer_reg_count_qxu_0_6_.INIT = 4'h8; + LUT2_L plm_fsm_xl_cla_timer_reg_count_qxu_0_6_ ( + .I0(plm_fsm_xl_cla_timer_un1_reg_state_5_i_i_2028), + .I1(plm_fsm_xl_cla_timer_reg_count[6]), + .LO(plm_fsm_xl_cla_timer_reg_count_qxu[6]) + ); + defparam plm_fsm_xl_cla_timer_reg_count_qxu_0_7_.INIT = 4'h8; + LUT2_L plm_fsm_xl_cla_timer_reg_count_qxu_0_7_ ( + .I0(plm_fsm_xl_cla_timer_un1_reg_state_5_i_i_2028), + .I1(plm_fsm_xl_cla_timer_reg_count[7]), + .LO(plm_fsm_xl_cla_timer_reg_count_qxu[7]) + ); + defparam plm_fsm_xl_cla_timer_reg_count_qxu_0_8_.INIT = 4'h8; + LUT2_L plm_fsm_xl_cla_timer_reg_count_qxu_0_8_ ( + .I0(plm_fsm_xl_cla_timer_un1_reg_state_5_i_i_2028), + .I1(plm_fsm_xl_cla_timer_reg_count[8]), + .LO(plm_fsm_xl_cla_timer_reg_count_qxu[8]) + ); + defparam plm_fsm_xl_cla_timer_reg_count_qxu_0_9_.INIT = 4'h8; + LUT2_L plm_fsm_xl_cla_timer_reg_count_qxu_0_9_ ( + .I0(plm_fsm_xl_cla_timer_un1_reg_state_5_i_i_2028), + .I1(plm_fsm_xl_cla_timer_reg_count[9]), + .LO(plm_fsm_xl_cla_timer_reg_count_qxu[9]) + ); + defparam plm_fsm_xl_cla_timer_reg_count_qxu_0_10_.INIT = 4'h8; + LUT2_L plm_fsm_xl_cla_timer_reg_count_qxu_0_10_ ( + .I0(plm_fsm_xl_cla_timer_un1_reg_state_5_i_i_2028), + .I1(plm_fsm_xl_cla_timer_reg_count[10]), + .LO(plm_fsm_xl_cla_timer_reg_count_qxu[10]) + ); + defparam plm_fsm_xl_cla_timer_reg_count_qxu_0_11_.INIT = 4'h8; + LUT2_L plm_fsm_xl_cla_timer_reg_count_qxu_0_11_ ( + .I0(plm_fsm_xl_cla_timer_un1_reg_state_5_i_i_2028), + .I1(plm_fsm_xl_cla_timer_reg_count[11]), + .LO(plm_fsm_xl_cla_timer_reg_count_qxu[11]) + ); + defparam plm_fsm_xl_cla_timer_reg_count_qxu_0_12_.INIT = 4'h8; + LUT2_L plm_fsm_xl_cla_timer_reg_count_qxu_0_12_ ( + .I0(plm_fsm_xl_cla_timer_un1_reg_state_5_i_i_2028), + .I1(plm_fsm_xl_cla_timer_reg_count[12]), + .LO(plm_fsm_xl_cla_timer_reg_count_qxu[12]) + ); + defparam plm_fsm_xl_cla_timer_reg_count_qxu_0_13_.INIT = 4'h8; + LUT2_L plm_fsm_xl_cla_timer_reg_count_qxu_0_13_ ( + .I0(plm_fsm_xl_cla_timer_un1_reg_state_5_i_i_2028), + .I1(plm_fsm_xl_cla_timer_reg_count[13]), + .LO(plm_fsm_xl_cla_timer_reg_count_qxu[13]) + ); + defparam plm_fsm_xl_cla_timer_reg_count_qxu_0_14_.INIT = 4'h8; + LUT2_L plm_fsm_xl_cla_timer_reg_count_qxu_0_14_ ( + .I0(plm_fsm_xl_cla_timer_un1_reg_state_5_i_i_2028), + .I1(plm_fsm_xl_cla_timer_reg_count[14]), + .LO(plm_fsm_xl_cla_timer_reg_count_qxu[14]) + ); + defparam plm_fsm_xl_cla_timer_reg_count_qxu_0_15_.INIT = 4'h8; + LUT2_L plm_fsm_xl_cla_timer_reg_count_qxu_0_15_ ( + .I0(plm_fsm_xl_cla_timer_un1_reg_state_5_i_i_2028), + .I1(plm_fsm_xl_cla_timer_reg_count[15]), + .LO(plm_fsm_xl_cla_timer_reg_count_qxu[15]) + ); + defparam plm_fsm_xl_cla_timer_reg_count_qxu_0_16_.INIT = 4'h8; + LUT2_L plm_fsm_xl_cla_timer_reg_count_qxu_0_16_ ( + .I0(plm_fsm_xl_cla_timer_un1_reg_state_5_i_i_2028), + .I1(plm_fsm_xl_cla_timer_reg_count[16]), + .LO(plm_fsm_xl_cla_timer_reg_count_qxu[16]) + ); + defparam plm_fsm_xl_cla_timer_reg_count_qxu_0_17_.INIT = 4'h8; + LUT2_L plm_fsm_xl_cla_timer_reg_count_qxu_0_17_ ( + .I0(plm_fsm_xl_cla_timer_un1_reg_state_5_i_i_2028), + .I1(plm_fsm_xl_cla_timer_reg_count[17]), + .LO(plm_fsm_xl_cla_timer_reg_count_qxu[17]) + ); + defparam plm_fsm_xl_cla_timer_reg_count_qxu_0_18_.INIT = 4'h8; + LUT2_L plm_fsm_xl_cla_timer_reg_count_qxu_0_18_ ( + .I0(plm_fsm_xl_cla_timer_un1_reg_state_5_i_i_2028), + .I1(plm_fsm_xl_cla_timer_reg_count[18]), + .LO(plm_fsm_xl_cla_timer_reg_count_qxu[18]) + ); + defparam plm_fsm_xl_cla_timer_reg_count_qxu_0_19_.INIT = 4'h8; + LUT2_L plm_fsm_xl_cla_timer_reg_count_qxu_0_19_ ( + .I0(plm_fsm_xl_cla_timer_un1_reg_state_5_i_i_2028), + .I1(plm_fsm_xl_cla_timer_reg_count[19]), + .LO(plm_fsm_xl_cla_timer_reg_count_qxu[19]) + ); + defparam plm_fsm_xl_cla_timer_reg_count_qxu_0_20_.INIT = 4'h8; + LUT2_L plm_fsm_xl_cla_timer_reg_count_qxu_0_20_ ( + .I0(plm_fsm_xl_cla_timer_un1_reg_state_5_i_i_2028), + .I1(plm_fsm_xl_cla_timer_reg_count[20]), + .LO(plm_fsm_xl_cla_timer_reg_count_qxu[20]) + ); + defparam plm_fsm_xl_cla_timer_reg_count_qxu_0_21_.INIT = 4'h8; + LUT2_L plm_fsm_xl_cla_timer_reg_count_qxu_0_21_ ( + .I0(plm_fsm_xl_cla_timer_un1_reg_state_5_i_i_2028), + .I1(plm_fsm_xl_cla_timer_reg_count[21]), + .LO(plm_fsm_xl_cla_timer_reg_count_qxu[21]) + ); + defparam plm_fsm_xl_cla_timer_reg_count_qxu_0_22_.INIT = 4'h8; + LUT2_L plm_fsm_xl_cla_timer_reg_count_qxu_0_22_ ( + .I0(plm_fsm_xl_cla_timer_un1_reg_state_5_i_i_2028), + .I1(plm_fsm_xl_cla_timer_reg_count[22]), + .LO(plm_fsm_xl_cla_timer_reg_count_qxu[22]) + ); + GND plm_fsm_xl_clw_timer_GND ( + .G(plm_fsm_xl_clw_timer_GND_2029) + ); + MUXCY_L plm_fsm_xl_clw_timer_reg_count_cry_0_ ( + .CI(plm_fsm_reg_state_23__1784), + .DI(plm_fsm_xl_clw_timer_GND_2029), + .LO(plm_fsm_xl_clw_timer_reg_count_cry[0]), + .S(plm_fsm_xl_clw_timer_reg_count_qxu[0]) + ); + XORCY plm_fsm_xl_clw_timer_reg_count_s_0_ ( + .CI(plm_fsm_reg_state_23__1784), + .LI(plm_fsm_xl_clw_timer_reg_count_qxu[0]), + .O(plm_fsm_xl_clw_timer_reg_count_s[0]) + ); + MUXCY_L plm_fsm_xl_clw_timer_reg_count_cry_1_ ( + .CI(plm_fsm_xl_clw_timer_reg_count_cry[0]), + .DI(plm_fsm_xl_clw_timer_GND_2029), + .LO(plm_fsm_xl_clw_timer_reg_count_cry[1]), + .S(plm_fsm_xl_clw_timer_reg_count_qxu[1]) + ); + XORCY plm_fsm_xl_clw_timer_reg_count_s_1_ ( + .CI(plm_fsm_xl_clw_timer_reg_count_cry[0]), + .LI(plm_fsm_xl_clw_timer_reg_count_qxu[1]), + .O(plm_fsm_xl_clw_timer_reg_count_s[1]) + ); + MUXCY_L plm_fsm_xl_clw_timer_reg_count_cry_2_ ( + .CI(plm_fsm_xl_clw_timer_reg_count_cry[1]), + .DI(plm_fsm_xl_clw_timer_GND_2029), + .LO(plm_fsm_xl_clw_timer_reg_count_cry[2]), + .S(plm_fsm_xl_clw_timer_reg_count_qxu[2]) + ); + XORCY plm_fsm_xl_clw_timer_reg_count_s_2_ ( + .CI(plm_fsm_xl_clw_timer_reg_count_cry[1]), + .LI(plm_fsm_xl_clw_timer_reg_count_qxu[2]), + .O(plm_fsm_xl_clw_timer_reg_count_s[2]) + ); + MUXCY_L plm_fsm_xl_clw_timer_reg_count_cry_3_ ( + .CI(plm_fsm_xl_clw_timer_reg_count_cry[2]), + .DI(plm_fsm_xl_clw_timer_GND_2029), + .LO(plm_fsm_xl_clw_timer_reg_count_cry[3]), + .S(plm_fsm_xl_clw_timer_reg_count_qxu[3]) + ); + XORCY plm_fsm_xl_clw_timer_reg_count_s_3_ ( + .CI(plm_fsm_xl_clw_timer_reg_count_cry[2]), + .LI(plm_fsm_xl_clw_timer_reg_count_qxu[3]), + .O(plm_fsm_xl_clw_timer_reg_count_s[3]) + ); + MUXCY_L plm_fsm_xl_clw_timer_reg_count_cry_4_ ( + .CI(plm_fsm_xl_clw_timer_reg_count_cry[3]), + .DI(plm_fsm_xl_clw_timer_GND_2029), + .LO(plm_fsm_xl_clw_timer_reg_count_cry[4]), + .S(plm_fsm_xl_clw_timer_reg_count_qxu[4]) + ); + XORCY plm_fsm_xl_clw_timer_reg_count_s_4_ ( + .CI(plm_fsm_xl_clw_timer_reg_count_cry[3]), + .LI(plm_fsm_xl_clw_timer_reg_count_qxu[4]), + .O(plm_fsm_xl_clw_timer_reg_count_s[4]) + ); + MUXCY_L plm_fsm_xl_clw_timer_reg_count_cry_5_ ( + .CI(plm_fsm_xl_clw_timer_reg_count_cry[4]), + .DI(plm_fsm_xl_clw_timer_GND_2029), + .LO(plm_fsm_xl_clw_timer_reg_count_cry[5]), + .S(plm_fsm_xl_clw_timer_reg_count_qxu[5]) + ); + XORCY plm_fsm_xl_clw_timer_reg_count_s_5_ ( + .CI(plm_fsm_xl_clw_timer_reg_count_cry[4]), + .LI(plm_fsm_xl_clw_timer_reg_count_qxu[5]), + .O(plm_fsm_xl_clw_timer_reg_count_s[5]) + ); + MUXCY_L plm_fsm_xl_clw_timer_reg_count_cry_6_ ( + .CI(plm_fsm_xl_clw_timer_reg_count_cry[5]), + .DI(plm_fsm_xl_clw_timer_GND_2029), + .LO(plm_fsm_xl_clw_timer_reg_count_cry[6]), + .S(plm_fsm_xl_clw_timer_reg_count_qxu[6]) + ); + XORCY plm_fsm_xl_clw_timer_reg_count_s_6_ ( + .CI(plm_fsm_xl_clw_timer_reg_count_cry[5]), + .LI(plm_fsm_xl_clw_timer_reg_count_qxu[6]), + .O(plm_fsm_xl_clw_timer_reg_count_s[6]) + ); + MUXCY_L plm_fsm_xl_clw_timer_reg_count_cry_7_ ( + .CI(plm_fsm_xl_clw_timer_reg_count_cry[6]), + .DI(plm_fsm_xl_clw_timer_GND_2029), + .LO(plm_fsm_xl_clw_timer_reg_count_cry[7]), + .S(plm_fsm_xl_clw_timer_reg_count_qxu[7]) + ); + XORCY plm_fsm_xl_clw_timer_reg_count_s_7_ ( + .CI(plm_fsm_xl_clw_timer_reg_count_cry[6]), + .LI(plm_fsm_xl_clw_timer_reg_count_qxu[7]), + .O(plm_fsm_xl_clw_timer_reg_count_s[7]) + ); + MUXCY_L plm_fsm_xl_clw_timer_reg_count_cry_8_ ( + .CI(plm_fsm_xl_clw_timer_reg_count_cry[7]), + .DI(plm_fsm_xl_clw_timer_GND_2029), + .LO(plm_fsm_xl_clw_timer_reg_count_cry[8]), + .S(plm_fsm_xl_clw_timer_reg_count_qxu[8]) + ); + XORCY plm_fsm_xl_clw_timer_reg_count_s_8_ ( + .CI(plm_fsm_xl_clw_timer_reg_count_cry[7]), + .LI(plm_fsm_xl_clw_timer_reg_count_qxu[8]), + .O(plm_fsm_xl_clw_timer_reg_count_s[8]) + ); + MUXCY_L plm_fsm_xl_clw_timer_reg_count_cry_9_ ( + .CI(plm_fsm_xl_clw_timer_reg_count_cry[8]), + .DI(plm_fsm_xl_clw_timer_GND_2029), + .LO(plm_fsm_xl_clw_timer_reg_count_cry[9]), + .S(plm_fsm_xl_clw_timer_reg_count_qxu[9]) + ); + XORCY plm_fsm_xl_clw_timer_reg_count_s_9_ ( + .CI(plm_fsm_xl_clw_timer_reg_count_cry[8]), + .LI(plm_fsm_xl_clw_timer_reg_count_qxu[9]), + .O(plm_fsm_xl_clw_timer_reg_count_s[9]) + ); + MUXCY_L plm_fsm_xl_clw_timer_reg_count_cry_10_ ( + .CI(plm_fsm_xl_clw_timer_reg_count_cry[9]), + .DI(plm_fsm_xl_clw_timer_GND_2029), + .LO(plm_fsm_xl_clw_timer_reg_count_cry[10]), + .S(plm_fsm_xl_clw_timer_reg_count_qxu[10]) + ); + XORCY plm_fsm_xl_clw_timer_reg_count_s_10_ ( + .CI(plm_fsm_xl_clw_timer_reg_count_cry[9]), + .LI(plm_fsm_xl_clw_timer_reg_count_qxu[10]), + .O(plm_fsm_xl_clw_timer_reg_count_s[10]) + ); + MUXCY_L plm_fsm_xl_clw_timer_reg_count_cry_11_ ( + .CI(plm_fsm_xl_clw_timer_reg_count_cry[10]), + .DI(plm_fsm_xl_clw_timer_GND_2029), + .LO(plm_fsm_xl_clw_timer_reg_count_cry[11]), + .S(plm_fsm_xl_clw_timer_reg_count_qxu[11]) + ); + XORCY plm_fsm_xl_clw_timer_reg_count_s_11_ ( + .CI(plm_fsm_xl_clw_timer_reg_count_cry[10]), + .LI(plm_fsm_xl_clw_timer_reg_count_qxu[11]), + .O(plm_fsm_xl_clw_timer_reg_count_s[11]) + ); + MUXCY_L plm_fsm_xl_clw_timer_reg_count_cry_12_ ( + .CI(plm_fsm_xl_clw_timer_reg_count_cry[11]), + .DI(plm_fsm_xl_clw_timer_GND_2029), + .LO(plm_fsm_xl_clw_timer_reg_count_cry[12]), + .S(plm_fsm_xl_clw_timer_reg_count_qxu[12]) + ); + XORCY plm_fsm_xl_clw_timer_reg_count_s_12_ ( + .CI(plm_fsm_xl_clw_timer_reg_count_cry[11]), + .LI(plm_fsm_xl_clw_timer_reg_count_qxu[12]), + .O(plm_fsm_xl_clw_timer_reg_count_s[12]) + ); + MUXCY_L plm_fsm_xl_clw_timer_reg_count_cry_13_ ( + .CI(plm_fsm_xl_clw_timer_reg_count_cry[12]), + .DI(plm_fsm_xl_clw_timer_GND_2029), + .LO(plm_fsm_xl_clw_timer_reg_count_cry[13]), + .S(plm_fsm_xl_clw_timer_reg_count_qxu[13]) + ); + XORCY plm_fsm_xl_clw_timer_reg_count_s_13_ ( + .CI(plm_fsm_xl_clw_timer_reg_count_cry[12]), + .LI(plm_fsm_xl_clw_timer_reg_count_qxu[13]), + .O(plm_fsm_xl_clw_timer_reg_count_s[13]) + ); + MUXCY_L plm_fsm_xl_clw_timer_reg_count_cry_14_ ( + .CI(plm_fsm_xl_clw_timer_reg_count_cry[13]), + .DI(plm_fsm_xl_clw_timer_GND_2029), + .LO(plm_fsm_xl_clw_timer_reg_count_cry[14]), + .S(plm_fsm_xl_clw_timer_reg_count_qxu[14]) + ); + XORCY plm_fsm_xl_clw_timer_reg_count_s_14_ ( + .CI(plm_fsm_xl_clw_timer_reg_count_cry[13]), + .LI(plm_fsm_xl_clw_timer_reg_count_qxu[14]), + .O(plm_fsm_xl_clw_timer_reg_count_s[14]) + ); + MUXCY_L plm_fsm_xl_clw_timer_reg_count_cry_15_ ( + .CI(plm_fsm_xl_clw_timer_reg_count_cry[14]), + .DI(plm_fsm_xl_clw_timer_GND_2029), + .LO(plm_fsm_xl_clw_timer_reg_count_cry[15]), + .S(plm_fsm_xl_clw_timer_reg_count_qxu[15]) + ); + XORCY plm_fsm_xl_clw_timer_reg_count_s_15_ ( + .CI(plm_fsm_xl_clw_timer_reg_count_cry[14]), + .LI(plm_fsm_xl_clw_timer_reg_count_qxu[15]), + .O(plm_fsm_xl_clw_timer_reg_count_s[15]) + ); + MUXCY_L plm_fsm_xl_clw_timer_reg_count_cry_16_ ( + .CI(plm_fsm_xl_clw_timer_reg_count_cry[15]), + .DI(plm_fsm_xl_clw_timer_GND_2029), + .LO(plm_fsm_xl_clw_timer_reg_count_cry[16]), + .S(plm_fsm_xl_clw_timer_reg_count_qxu[16]) + ); + XORCY plm_fsm_xl_clw_timer_reg_count_s_16_ ( + .CI(plm_fsm_xl_clw_timer_reg_count_cry[15]), + .LI(plm_fsm_xl_clw_timer_reg_count_qxu[16]), + .O(plm_fsm_xl_clw_timer_reg_count_s[16]) + ); + MUXCY_L plm_fsm_xl_clw_timer_reg_count_cry_17_ ( + .CI(plm_fsm_xl_clw_timer_reg_count_cry[16]), + .DI(plm_fsm_xl_clw_timer_GND_2029), + .LO(plm_fsm_xl_clw_timer_reg_count_cry[17]), + .S(plm_fsm_xl_clw_timer_reg_count_qxu[17]) + ); + XORCY plm_fsm_xl_clw_timer_reg_count_s_17_ ( + .CI(plm_fsm_xl_clw_timer_reg_count_cry[16]), + .LI(plm_fsm_xl_clw_timer_reg_count_qxu[17]), + .O(plm_fsm_xl_clw_timer_reg_count_s[17]) + ); + MUXCY_L plm_fsm_xl_clw_timer_reg_count_cry_18_ ( + .CI(plm_fsm_xl_clw_timer_reg_count_cry[17]), + .DI(plm_fsm_xl_clw_timer_GND_2029), + .LO(plm_fsm_xl_clw_timer_reg_count_cry[18]), + .S(plm_fsm_xl_clw_timer_reg_count_qxu[18]) + ); + XORCY plm_fsm_xl_clw_timer_reg_count_s_18_ ( + .CI(plm_fsm_xl_clw_timer_reg_count_cry[17]), + .LI(plm_fsm_xl_clw_timer_reg_count_qxu[18]), + .O(plm_fsm_xl_clw_timer_reg_count_s[18]) + ); + MUXCY_L plm_fsm_xl_clw_timer_reg_count_cry_19_ ( + .CI(plm_fsm_xl_clw_timer_reg_count_cry[18]), + .DI(plm_fsm_xl_clw_timer_GND_2029), + .LO(plm_fsm_xl_clw_timer_reg_count_cry[19]), + .S(plm_fsm_xl_clw_timer_reg_count_qxu[19]) + ); + XORCY plm_fsm_xl_clw_timer_reg_count_s_19_ ( + .CI(plm_fsm_xl_clw_timer_reg_count_cry[18]), + .LI(plm_fsm_xl_clw_timer_reg_count_qxu[19]), + .O(plm_fsm_xl_clw_timer_reg_count_s[19]) + ); + MUXCY_L plm_fsm_xl_clw_timer_reg_count_cry_20_ ( + .CI(plm_fsm_xl_clw_timer_reg_count_cry[19]), + .DI(plm_fsm_xl_clw_timer_GND_2029), + .LO(plm_fsm_xl_clw_timer_reg_count_cry[20]), + .S(plm_fsm_xl_clw_timer_reg_count_qxu[20]) + ); + XORCY plm_fsm_xl_clw_timer_reg_count_s_20_ ( + .CI(plm_fsm_xl_clw_timer_reg_count_cry[19]), + .LI(plm_fsm_xl_clw_timer_reg_count_qxu[20]), + .O(plm_fsm_xl_clw_timer_reg_count_s[20]) + ); + MUXCY_L plm_fsm_xl_clw_timer_reg_count_cry_21_ ( + .CI(plm_fsm_xl_clw_timer_reg_count_cry[20]), + .DI(plm_fsm_xl_clw_timer_GND_2029), + .LO(plm_fsm_xl_clw_timer_reg_count_cry[21]), + .S(plm_fsm_xl_clw_timer_reg_count_qxu[21]) + ); + XORCY plm_fsm_xl_clw_timer_reg_count_s_21_ ( + .CI(plm_fsm_xl_clw_timer_reg_count_cry[20]), + .LI(plm_fsm_xl_clw_timer_reg_count_qxu[21]), + .O(plm_fsm_xl_clw_timer_reg_count_s[21]) + ); + XORCY plm_fsm_xl_clw_timer_reg_count_s_22_ ( + .CI(plm_fsm_xl_clw_timer_reg_count_cry[21]), + .LI(plm_fsm_xl_clw_timer_reg_count_qxu[22]), + .O(plm_fsm_xl_clw_timer_reg_count_s[22]) + ); + defparam plm_fsm_xl_clw_timer_count_i_m3_i_m3_0_18_.INIT = 8'hD8; + LUT3 plm_fsm_xl_clw_timer_count_i_m3_i_m3_0_18_ ( + .I0(cfg_cfg_6102[507]), + .I1(plm_fsm_xl_clw_timer_reg_count[10]), + .I2(plm_fsm_xl_clw_timer_reg_count[18]), + .O(plm_fsm_xl_clw_timer_N_63696) + ); + defparam plm_fsm_xl_clw_timer_count_i_m3_i_m3_0_19_.INIT = 8'hD8; + LUT3_L plm_fsm_xl_clw_timer_count_i_m3_i_m3_0_19_ ( + .I0(cfg_cfg_6102[507]), + .I1(plm_fsm_xl_clw_timer_reg_count[11]), + .I2(plm_fsm_xl_clw_timer_reg_count[19]), + .LO(plm_fsm_xl_clw_timer_N_63697) + ); + defparam plm_fsm_xl_clw_timer_count_i_m3_i_m3_0_20_.INIT = 8'hD8; + LUT3 plm_fsm_xl_clw_timer_count_i_m3_i_m3_0_20_ ( + .I0(cfg_cfg_6102[507]), + .I1(plm_fsm_xl_clw_timer_reg_count[12]), + .I2(plm_fsm_xl_clw_timer_reg_count[20]), + .O(plm_fsm_xl_clw_timer_N_63698) + ); + defparam plm_fsm_xl_clw_timer_count_i_m3_i_m3_0_21_.INIT = 8'hD8; + LUT3 plm_fsm_xl_clw_timer_count_i_m3_i_m3_0_21_ ( + .I0(cfg_cfg_6102[507]), + .I1(plm_fsm_xl_clw_timer_reg_count[13]), + .I2(plm_fsm_xl_clw_timer_reg_count[21]), + .O(plm_fsm_xl_clw_timer_N_63699) + ); + defparam plm_fsm_xl_clw_timer_un1_expired_2ms_0_a2_0_a3_0.INIT = 16'h0415; + LUT4_L plm_fsm_xl_clw_timer_un1_expired_2ms_0_a2_0_a3_0 ( + .I0(plm_fsm_xl_clw_timer_N_63697), + .I1(cfg_cfg_6102[507]), + .I2(plm_fsm_xl_clw_timer_reg_count[14]), + .I3(plm_fsm_xl_clw_timer_reg_count[22]), + .LO(plm_fsm_xl_clw_timer_un1_expired_2ms_0_a2_0_a3_0_2030) + ); + defparam plm_fsm_xl_clw_timer_un1_expired_2ms_0_a2_0_a3.INIT = 16'h0100; + LUT4 plm_fsm_xl_clw_timer_un1_expired_2ms_0_a2_0_a3 ( + .I0(plm_fsm_xl_clw_timer_N_63696), + .I1(plm_fsm_xl_clw_timer_N_63698), + .I2(plm_fsm_xl_clw_timer_N_63699), + .I3(plm_fsm_xl_clw_timer_un1_expired_2ms_0_a2_0_a3_0_2030), + .O(plm_fsm_N_63400) + ); + FDC plm_fsm_xl_clw_timer_reg_count_22_ ( + .C(mgt_clk), + .D(plm_fsm_xl_clw_timer_reg_count_s[22]), + .Q(plm_fsm_xl_clw_timer_reg_count[22]), + .CLR(plm_rst) + ); + FDC plm_fsm_xl_clw_timer_reg_count_21_ ( + .C(mgt_clk), + .D(plm_fsm_xl_clw_timer_reg_count_s[21]), + .Q(plm_fsm_xl_clw_timer_reg_count[21]), + .CLR(plm_rst) + ); + FDC plm_fsm_xl_clw_timer_reg_count_20_ ( + .C(mgt_clk), + .D(plm_fsm_xl_clw_timer_reg_count_s[20]), + .Q(plm_fsm_xl_clw_timer_reg_count[20]), + .CLR(plm_rst) + ); + FDC plm_fsm_xl_clw_timer_reg_count_19_ ( + .C(mgt_clk), + .D(plm_fsm_xl_clw_timer_reg_count_s[19]), + .Q(plm_fsm_xl_clw_timer_reg_count[19]), + .CLR(plm_rst) + ); + FDC plm_fsm_xl_clw_timer_reg_count_18_ ( + .C(mgt_clk), + .D(plm_fsm_xl_clw_timer_reg_count_s[18]), + .Q(plm_fsm_xl_clw_timer_reg_count[18]), + .CLR(plm_rst) + ); + FDC plm_fsm_xl_clw_timer_reg_count_17_ ( + .C(mgt_clk), + .D(plm_fsm_xl_clw_timer_reg_count_s[17]), + .Q(plm_fsm_xl_clw_timer_reg_count[17]), + .CLR(plm_rst) + ); + FDC plm_fsm_xl_clw_timer_reg_count_16_ ( + .C(mgt_clk), + .D(plm_fsm_xl_clw_timer_reg_count_s[16]), + .Q(plm_fsm_xl_clw_timer_reg_count[16]), + .CLR(plm_rst) + ); + FDC plm_fsm_xl_clw_timer_reg_count_15_ ( + .C(mgt_clk), + .D(plm_fsm_xl_clw_timer_reg_count_s[15]), + .Q(plm_fsm_xl_clw_timer_reg_count[15]), + .CLR(plm_rst) + ); + FDC plm_fsm_xl_clw_timer_reg_count_14_ ( + .C(mgt_clk), + .D(plm_fsm_xl_clw_timer_reg_count_s[14]), + .Q(plm_fsm_xl_clw_timer_reg_count[14]), + .CLR(plm_rst) + ); + FDC plm_fsm_xl_clw_timer_reg_count_13_ ( + .C(mgt_clk), + .D(plm_fsm_xl_clw_timer_reg_count_s[13]), + .Q(plm_fsm_xl_clw_timer_reg_count[13]), + .CLR(plm_rst) + ); + FDC plm_fsm_xl_clw_timer_reg_count_12_ ( + .C(mgt_clk), + .D(plm_fsm_xl_clw_timer_reg_count_s[12]), + .Q(plm_fsm_xl_clw_timer_reg_count[12]), + .CLR(plm_rst) + ); + FDC plm_fsm_xl_clw_timer_reg_count_11_ ( + .C(mgt_clk), + .D(plm_fsm_xl_clw_timer_reg_count_s[11]), + .Q(plm_fsm_xl_clw_timer_reg_count[11]), + .CLR(plm_rst) + ); + FDC plm_fsm_xl_clw_timer_reg_count_10_ ( + .C(mgt_clk), + .D(plm_fsm_xl_clw_timer_reg_count_s[10]), + .Q(plm_fsm_xl_clw_timer_reg_count[10]), + .CLR(plm_rst) + ); + FDC plm_fsm_xl_clw_timer_reg_count_9_ ( + .C(mgt_clk), + .D(plm_fsm_xl_clw_timer_reg_count_s[9]), + .Q(plm_fsm_xl_clw_timer_reg_count[9]), + .CLR(plm_rst) + ); + FDC plm_fsm_xl_clw_timer_reg_count_8_ ( + .C(mgt_clk), + .D(plm_fsm_xl_clw_timer_reg_count_s[8]), + .Q(plm_fsm_xl_clw_timer_reg_count[8]), + .CLR(plm_rst) + ); + FDC plm_fsm_xl_clw_timer_reg_count_7_ ( + .C(mgt_clk), + .D(plm_fsm_xl_clw_timer_reg_count_s[7]), + .Q(plm_fsm_xl_clw_timer_reg_count[7]), + .CLR(plm_rst) + ); + FDC plm_fsm_xl_clw_timer_reg_count_6_ ( + .C(mgt_clk), + .D(plm_fsm_xl_clw_timer_reg_count_s[6]), + .Q(plm_fsm_xl_clw_timer_reg_count[6]), + .CLR(plm_rst) + ); + FDC plm_fsm_xl_clw_timer_reg_count_5_ ( + .C(mgt_clk), + .D(plm_fsm_xl_clw_timer_reg_count_s[5]), + .Q(plm_fsm_xl_clw_timer_reg_count[5]), + .CLR(plm_rst) + ); + FDC plm_fsm_xl_clw_timer_reg_count_4_ ( + .C(mgt_clk), + .D(plm_fsm_xl_clw_timer_reg_count_s[4]), + .Q(plm_fsm_xl_clw_timer_reg_count[4]), + .CLR(plm_rst) + ); + FDC plm_fsm_xl_clw_timer_reg_count_3_ ( + .C(mgt_clk), + .D(plm_fsm_xl_clw_timer_reg_count_s[3]), + .Q(plm_fsm_xl_clw_timer_reg_count[3]), + .CLR(plm_rst) + ); + FDC plm_fsm_xl_clw_timer_reg_count_2_ ( + .C(mgt_clk), + .D(plm_fsm_xl_clw_timer_reg_count_s[2]), + .Q(plm_fsm_xl_clw_timer_reg_count[2]), + .CLR(plm_rst) + ); + FDC plm_fsm_xl_clw_timer_reg_count_1_ ( + .C(mgt_clk), + .D(plm_fsm_xl_clw_timer_reg_count_s[1]), + .Q(plm_fsm_xl_clw_timer_reg_count[1]), + .CLR(plm_rst) + ); + FDC plm_fsm_xl_clw_timer_reg_count_0_ ( + .C(mgt_clk), + .D(plm_fsm_xl_clw_timer_reg_count_s[0]), + .Q(plm_fsm_xl_clw_timer_reg_count[0]), + .CLR(plm_rst) + ); + defparam plm_fsm_xl_clw_timer_reg_count_qxu_0_0_.INIT = 4'h8; + LUT2_L plm_fsm_xl_clw_timer_reg_count_qxu_0_0_ ( + .I0(plm_fsm_reg_state_23__1784), + .I1(plm_fsm_xl_clw_timer_reg_count[0]), + .LO(plm_fsm_xl_clw_timer_reg_count_qxu[0]) + ); + defparam plm_fsm_xl_clw_timer_reg_count_qxu_0_1_.INIT = 4'h8; + LUT2_L plm_fsm_xl_clw_timer_reg_count_qxu_0_1_ ( + .I0(plm_fsm_reg_state_23__1784), + .I1(plm_fsm_xl_clw_timer_reg_count[1]), + .LO(plm_fsm_xl_clw_timer_reg_count_qxu[1]) + ); + defparam plm_fsm_xl_clw_timer_reg_count_qxu_0_2_.INIT = 4'h8; + LUT2_L plm_fsm_xl_clw_timer_reg_count_qxu_0_2_ ( + .I0(plm_fsm_reg_state_23__1784), + .I1(plm_fsm_xl_clw_timer_reg_count[2]), + .LO(plm_fsm_xl_clw_timer_reg_count_qxu[2]) + ); + defparam plm_fsm_xl_clw_timer_reg_count_qxu_0_3_.INIT = 4'h8; + LUT2_L plm_fsm_xl_clw_timer_reg_count_qxu_0_3_ ( + .I0(plm_fsm_reg_state_23__1784), + .I1(plm_fsm_xl_clw_timer_reg_count[3]), + .LO(plm_fsm_xl_clw_timer_reg_count_qxu[3]) + ); + defparam plm_fsm_xl_clw_timer_reg_count_qxu_0_4_.INIT = 4'h8; + LUT2_L plm_fsm_xl_clw_timer_reg_count_qxu_0_4_ ( + .I0(plm_fsm_reg_state_23__1784), + .I1(plm_fsm_xl_clw_timer_reg_count[4]), + .LO(plm_fsm_xl_clw_timer_reg_count_qxu[4]) + ); + defparam plm_fsm_xl_clw_timer_reg_count_qxu_0_5_.INIT = 4'h8; + LUT2_L plm_fsm_xl_clw_timer_reg_count_qxu_0_5_ ( + .I0(plm_fsm_reg_state_23__1784), + .I1(plm_fsm_xl_clw_timer_reg_count[5]), + .LO(plm_fsm_xl_clw_timer_reg_count_qxu[5]) + ); + defparam plm_fsm_xl_clw_timer_reg_count_qxu_0_6_.INIT = 4'h8; + LUT2_L plm_fsm_xl_clw_timer_reg_count_qxu_0_6_ ( + .I0(plm_fsm_reg_state_23__1784), + .I1(plm_fsm_xl_clw_timer_reg_count[6]), + .LO(plm_fsm_xl_clw_timer_reg_count_qxu[6]) + ); + defparam plm_fsm_xl_clw_timer_reg_count_qxu_0_7_.INIT = 4'h8; + LUT2_L plm_fsm_xl_clw_timer_reg_count_qxu_0_7_ ( + .I0(plm_fsm_reg_state_23__1784), + .I1(plm_fsm_xl_clw_timer_reg_count[7]), + .LO(plm_fsm_xl_clw_timer_reg_count_qxu[7]) + ); + defparam plm_fsm_xl_clw_timer_reg_count_qxu_0_8_.INIT = 4'h8; + LUT2_L plm_fsm_xl_clw_timer_reg_count_qxu_0_8_ ( + .I0(plm_fsm_reg_state_23__1784), + .I1(plm_fsm_xl_clw_timer_reg_count[8]), + .LO(plm_fsm_xl_clw_timer_reg_count_qxu[8]) + ); + defparam plm_fsm_xl_clw_timer_reg_count_qxu_0_9_.INIT = 4'h8; + LUT2_L plm_fsm_xl_clw_timer_reg_count_qxu_0_9_ ( + .I0(plm_fsm_reg_state_23__1784), + .I1(plm_fsm_xl_clw_timer_reg_count[9]), + .LO(plm_fsm_xl_clw_timer_reg_count_qxu[9]) + ); + defparam plm_fsm_xl_clw_timer_reg_count_qxu_0_10_.INIT = 4'h8; + LUT2_L plm_fsm_xl_clw_timer_reg_count_qxu_0_10_ ( + .I0(plm_fsm_reg_state_23__1784), + .I1(plm_fsm_xl_clw_timer_reg_count[10]), + .LO(plm_fsm_xl_clw_timer_reg_count_qxu[10]) + ); + defparam plm_fsm_xl_clw_timer_reg_count_qxu_0_11_.INIT = 4'h8; + LUT2_L plm_fsm_xl_clw_timer_reg_count_qxu_0_11_ ( + .I0(plm_fsm_reg_state_23__1784), + .I1(plm_fsm_xl_clw_timer_reg_count[11]), + .LO(plm_fsm_xl_clw_timer_reg_count_qxu[11]) + ); + defparam plm_fsm_xl_clw_timer_reg_count_qxu_0_12_.INIT = 4'h8; + LUT2_L plm_fsm_xl_clw_timer_reg_count_qxu_0_12_ ( + .I0(plm_fsm_reg_state_23__1784), + .I1(plm_fsm_xl_clw_timer_reg_count[12]), + .LO(plm_fsm_xl_clw_timer_reg_count_qxu[12]) + ); + defparam plm_fsm_xl_clw_timer_reg_count_qxu_0_13_.INIT = 4'h8; + LUT2_L plm_fsm_xl_clw_timer_reg_count_qxu_0_13_ ( + .I0(plm_fsm_reg_state_23__1784), + .I1(plm_fsm_xl_clw_timer_reg_count[13]), + .LO(plm_fsm_xl_clw_timer_reg_count_qxu[13]) + ); + defparam plm_fsm_xl_clw_timer_reg_count_qxu_0_14_.INIT = 4'h8; + LUT2_L plm_fsm_xl_clw_timer_reg_count_qxu_0_14_ ( + .I0(plm_fsm_reg_state_23__1784), + .I1(plm_fsm_xl_clw_timer_reg_count[14]), + .LO(plm_fsm_xl_clw_timer_reg_count_qxu[14]) + ); + defparam plm_fsm_xl_clw_timer_reg_count_qxu_0_15_.INIT = 4'h8; + LUT2_L plm_fsm_xl_clw_timer_reg_count_qxu_0_15_ ( + .I0(plm_fsm_reg_state_23__1784), + .I1(plm_fsm_xl_clw_timer_reg_count[15]), + .LO(plm_fsm_xl_clw_timer_reg_count_qxu[15]) + ); + defparam plm_fsm_xl_clw_timer_reg_count_qxu_0_16_.INIT = 4'h8; + LUT2_L plm_fsm_xl_clw_timer_reg_count_qxu_0_16_ ( + .I0(plm_fsm_reg_state_23__1784), + .I1(plm_fsm_xl_clw_timer_reg_count[16]), + .LO(plm_fsm_xl_clw_timer_reg_count_qxu[16]) + ); + defparam plm_fsm_xl_clw_timer_reg_count_qxu_0_17_.INIT = 4'h8; + LUT2_L plm_fsm_xl_clw_timer_reg_count_qxu_0_17_ ( + .I0(plm_fsm_reg_state_23__1784), + .I1(plm_fsm_xl_clw_timer_reg_count[17]), + .LO(plm_fsm_xl_clw_timer_reg_count_qxu[17]) + ); + defparam plm_fsm_xl_clw_timer_reg_count_qxu_0_18_.INIT = 4'h8; + LUT2_L plm_fsm_xl_clw_timer_reg_count_qxu_0_18_ ( + .I0(plm_fsm_reg_state_23__1784), + .I1(plm_fsm_xl_clw_timer_reg_count[18]), + .LO(plm_fsm_xl_clw_timer_reg_count_qxu[18]) + ); + defparam plm_fsm_xl_clw_timer_reg_count_qxu_0_19_.INIT = 4'h8; + LUT2_L plm_fsm_xl_clw_timer_reg_count_qxu_0_19_ ( + .I0(plm_fsm_reg_state_23__1784), + .I1(plm_fsm_xl_clw_timer_reg_count[19]), + .LO(plm_fsm_xl_clw_timer_reg_count_qxu[19]) + ); + defparam plm_fsm_xl_clw_timer_reg_count_qxu_0_20_.INIT = 4'h8; + LUT2_L plm_fsm_xl_clw_timer_reg_count_qxu_0_20_ ( + .I0(plm_fsm_reg_state_23__1784), + .I1(plm_fsm_xl_clw_timer_reg_count[20]), + .LO(plm_fsm_xl_clw_timer_reg_count_qxu[20]) + ); + defparam plm_fsm_xl_clw_timer_reg_count_qxu_0_21_.INIT = 4'h8; + LUT2_L plm_fsm_xl_clw_timer_reg_count_qxu_0_21_ ( + .I0(plm_fsm_reg_state_23__1784), + .I1(plm_fsm_xl_clw_timer_reg_count[21]), + .LO(plm_fsm_xl_clw_timer_reg_count_qxu[21]) + ); + defparam plm_fsm_xl_clw_timer_reg_count_qxu_0_22_.INIT = 4'h8; + LUT2_L plm_fsm_xl_clw_timer_reg_count_qxu_0_22_ ( + .I0(plm_fsm_reg_state_23__1784), + .I1(plm_fsm_xl_clw_timer_reg_count[22]), + .LO(plm_fsm_xl_clw_timer_reg_count_qxu[22]) + ); + FDP com_llm_cmml_protocol_err_n ( + .PRE(plm_link_up_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_rx_dllp_range_err_n), + .Q(com_cmml_protocol_err_n) + ); + FDR com_llm_llm_tx_top_cmml_suspend_ok ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_N_51188_i), + .Q(com_cmml_suspend_ok), + .R(plm_link_up_i) + ); + defparam com_llm_llm_tx_top_cmml_suspend_ok_4_i.INIT = 16'hD050; + LUT4_L com_llm_llm_tx_top_cmml_suspend_ok_4_i ( + .I0(com_cmml_suspend_now_n), + .I1(com_llm_llm_tx_top_reg_tx_djefe_idle), + .I2(com_llm_llm_tx_top_reg_tx_pp_idle), + .I3(com_llm_llm_tx_top_reg_tx_tkomp_idle), + .LO(com_llm_llm_tx_top_N_51188_i) + ); + VCC com_llm_llm_tx_top_llmx08_tx_tlp_komp_VCC ( + .P(com_llm_llm_tx_top_llmx08_tx_tlp_komp_VCC_2041) + ); + GND com_llm_llm_tx_top_llmx08_tx_tlp_komp_GND ( + .G(com_llm_llm_tx_top_llmx08_tx_tlp_komp_GND_2040) + ); + FDS com_llm_llm_tx_top_llmx08_tx_tlp_komp_lnk_tdst_rdy_n ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_N_85587_i_2039), + .Q(com_lnk_tdst_rdy_n), + .S(plm_link_up_i) + ); + FDSE com_llm_llm_tx_top_llmx08_tx_tlp_komp_reg_tx_tkomp_idle ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_N_57527_i_2034), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_N_57527_1), + .Q(com_llm_llm_tx_top_reg_tx_tkomp_idle), + .S(plm_link_up_i) + ); + FDSE com_llm_llm_tx_top_llmx08_tx_tlp_komp_sof_n_pipe_0_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_0), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_sof_n_mux_i_i_2038), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_sof_n_pipe[0]), + .S(plm_link_up_i) + ); + FDSE com_llm_llm_tx_top_llmx08_tx_tlp_komp_sof_n_pipe_1_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_0), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_sof_n_pipe[0]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_sof_n_pipe[1]), + .S(plm_link_up_i) + ); + FDSE com_llm_llm_tx_top_llmx08_tx_tlp_komp_sof_n_pipe_2_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_0), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_sof_n_pipe[1]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_sof_n_pipe[2]), + .S(plm_link_up_i) + ); + FDSE com_llm_llm_tx_top_llmx08_tx_tlp_komp_sof_n_pipe_3_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_0), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_sof_n_pipe[2]), + .Q(com_llm_llm_tx_top_tx_tlp_sof_pre_n), + .S(plm_link_up_i) + ); + FDSE com_llm_llm_tx_top_llmx08_tx_tlp_komp_sof_n_pipe_4_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_0), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_tx_tlp_sof_pre_n), + .Q(com_llm_llm_tx_top_tx_tlp_sof_n), + .S(plm_link_up_i) + ); + FDSE com_llm_llm_tx_top_llmx08_tx_tlp_komp_rem_pipe_0_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_0), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_N_86845_i_2035), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_rem_pipe_6115[0]), + .S(plm_link_up_i) + ); + FDSE com_llm_llm_tx_top_llmx08_tx_tlp_komp_rem_pipe_4_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_0), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_rem_pipe[3]), + .Q(com_llm_llm_tx_top_rem_pipe[4]), + .S(plm_link_up_i) + ); + FDSE com_llm_llm_tx_top_llmx08_tx_tlp_komp_rem_pipe_5_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_0), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_rem_pipe[4]), + .Q(com_llm_llm_tx_top_tx_tlp_vld_l_n_i), + .S(plm_link_up_i) + ); + FDSE com_llm_llm_tx_top_llmx08_tx_tlp_komp_eof_n_pipe_0_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_0), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_N_30495_i), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_eof_n_pipe_6114[0]), + .S(plm_link_up_i) + ); + FDSE com_llm_llm_tx_top_llmx08_tx_tlp_komp_eof_n_pipe_1_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_0), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_eof_n_pipe_6114[0]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_eof_n_pipe_6114[1]), + .S(plm_link_up_i) + ); + FDSE com_llm_llm_tx_top_llmx08_tx_tlp_komp_eof_n_pipe_5_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_0), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_eof_n_pipe[4]), + .Q(com_llm_llm_tx_top_tx_tlp_eof_n), + .S(plm_link_up_i) + ); + FDRSE com_llm_llm_tx_top_llmx08_tx_tlp_komp_holy_stashed_data ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_0), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_GND_2040), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_holy_stashed_data_2036), + .R(plm_link_up_i), + .S(com_llm_llm_tx_top_llmx08_tx_tlp_komp_un1_tx_pipe_full_0_a2_0_a2_0_a2_2033) + ); + FDSE com_llm_llm_tx_top_llmx08_tx_tlp_komp_bat_sof_n ( + .CE(com_lnk_tdst_rdy_n_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_lnk_tsof_i), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_bat_sof_n_2031), + .S(plm_link_up_i) + ); + FDSE com_llm_llm_tx_top_llmx08_tx_tlp_komp_bat_rem ( + .CE(com_lnk_tdst_rdy_n_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_lnk_trem[0]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_bat_rem_2037), + .S(plm_link_up_i) + ); + FDSE com_llm_llm_tx_top_llmx08_tx_tlp_komp_bat_eof_n ( + .CE(com_lnk_tdst_rdy_n_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_lnk_teof_i), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_bat_eof_n_2032), + .S(plm_link_up_i) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_un1_reg_tx_tkomp_idle_0_o3.INIT = 4'h8; + LUT2 com_llm_llm_tx_top_llmx08_tx_tlp_komp_un1_reg_tx_tkomp_idle_0_o3 ( + .I0(com_llm_llm_tx_top_tx_tlp_sof_n), + .I1(com_llm_llm_tx_top_tx_tlp_sof_pre_n), + .O(com_llm_llm_tx_top_N_56164_i) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_bat_td3_0_a2_0_a2_0_a2.INIT = 4'h4; + LUT2 com_llm_llm_tx_top_llmx08_tx_tlp_komp_bat_td3_0_a2_0_a2_0_a2 ( + .I0(com_lnk_tdst_rdy_n), + .I1(plm_link_up_1), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_bat_td3) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_d_2_o3_0_.INIT = 8'h70; + LUT3 com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_d_2_o3_0_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_eof_n_pipe[4]), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_rem_pipe[3]), + .I2(com_llm_llm_tx_top_tx_tlp_sof_pre_n), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_d_2_o3[0]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_d_i_0_a3_0_40_.INIT = 4'h2; + LUT2 com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_d_i_0_a3_0_40_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_N_55885_i), + .I1(com_llm_llm_tx_top_rem_pipe[4]), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_N_61377) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_d_2_a3_0_0_.INIT = 8'h20; + LUT3 com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_d_2_a3_0_0_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_eof_n_pipe[4]), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_rem_pipe[3]), + .I2(com_llm_llm_tx_top_tx_tlp_sof_pre_n), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_N_61392) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_crcint_i_0_0_o2.INIT = 16'h4744; + LUT4 com_llm_llm_tx_top_llmx08_tx_tlp_komp_crcint_i_0_0_o2 ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_bat_sof_n_2031), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_holy_stashed_data_2036), + .I2(com_lnk_tdst_rdy_n), + .I3(com_lnk_tsof), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_sof_n_mux_i) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_lnk_tdst_rdy_n_d_i_0_o2_0.INIT = 16'hB8BB; + LUT4 com_llm_llm_tx_top_llmx08_tx_tlp_komp_lnk_tdst_rdy_n_d_i_0_o2_0 ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_bat_eof_n_2032), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_holy_stashed_data_2036), + .I2(com_lnk_tdst_rdy_n), + .I3(com_lnk_teof), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_N_30495_i) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_un1_tx_pipe_full_0_a2_0_a2_0_a2.INIT = 4'h2; + LUT2 com_llm_llm_tx_top_llmx08_tx_tlp_komp_un1_tx_pipe_full_0_a2_0_a2_0_a2 ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full), + .I1(com_lnk_tdst_rdy_n), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_un1_tx_pipe_full_0_a2_0_a2_0_a2_2033) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_un1_reg_tx_tkomp_idle_0_a2_1.INIT = 16'h8000; + LUT4 com_llm_llm_tx_top_llmx08_tx_tlp_komp_un1_reg_tx_tkomp_idle_0_a2_1 ( + .I0(com_llm_llm_tx_top_N_56164_i), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_sof_n_pipe[0]), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_sof_n_pipe[1]), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_sof_n_pipe[2]), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_N_57527_1) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_d_i_0_0_50_.INIT = 16'hEEF0; + LUT4 com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_d_i_0_0_50_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_d_i_o3[52]), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_266_), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tsn_pipe_46_), + .I3(com_llm_llm_tx_top_tx_tlp_sof_pre_n), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_d_i_0_0[50]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_d_i_0_0_47_.INIT = 16'hEEF0; + LUT4 com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_d_i_0_0_47_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_d_i_o3[52]), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_263_), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tsn_pipe_43_), + .I3(com_llm_llm_tx_top_tx_tlp_sof_pre_n), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_d_i_0_0[47]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_d_i_0_0_40_.INIT = 16'hEEF0; + LUT4 com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_d_i_0_0_40_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_d_i_o3[52]), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_256_), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tsn_pipe_36_), + .I3(com_llm_llm_tx_top_tx_tlp_sof_pre_n), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_d_i_0_0[40]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_d_i_0_0_45_.INIT = 16'hEEF0; + LUT4 com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_d_i_0_0_45_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_d_i_o3[52]), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_261_), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tsn_pipe_41_), + .I3(com_llm_llm_tx_top_tx_tlp_sof_pre_n), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_d_i_0_0[45]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_d_i_0_0_48_.INIT = 16'hEEF0; + LUT4 com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_d_i_0_0_48_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_d_i_o3[52]), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_264_), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tsn_pipe_44_), + .I3(com_llm_llm_tx_top_tx_tlp_sof_pre_n), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_d_i_0_0[48]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_d_i_0_0_49_.INIT = 16'hEEF0; + LUT4 com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_d_i_0_0_49_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_d_i_o3[52]), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_265_), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tsn_pipe_45_), + .I3(com_llm_llm_tx_top_tx_tlp_sof_pre_n), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_d_i_0_0[49]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_d_i_0_0_42_.INIT = 16'hEEF0; + LUT4 com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_d_i_0_0_42_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_d_i_o3[52]), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_258_), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tsn_pipe_38_), + .I3(com_llm_llm_tx_top_tx_tlp_sof_pre_n), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_d_i_0_0[42]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_d_i_0_0_41_.INIT = 16'hEEF0; + LUT4 com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_d_i_0_0_41_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_d_i_o3[52]), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_257_), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tsn_pipe_37_), + .I3(com_llm_llm_tx_top_tx_tlp_sof_pre_n), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_d_i_0_0[41]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_d_i_0_0_46_.INIT = 16'hEEF0; + LUT4 com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_d_i_0_0_46_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_d_i_o3[52]), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_262_), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tsn_pipe_42_), + .I3(com_llm_llm_tx_top_tx_tlp_sof_pre_n), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_d_i_0_0[46]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_d_i_0_0_44_.INIT = 16'hEEF0; + LUT4 com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_d_i_0_0_44_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_d_i_o3[52]), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_260_), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tsn_pipe_40_), + .I3(com_llm_llm_tx_top_tx_tlp_sof_pre_n), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_d_i_0_0[44]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_d_i_0_0_43_.INIT = 16'hEEF0; + LUT4 com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_d_i_0_0_43_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_d_i_o3[52]), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_259_), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tsn_pipe_39_), + .I3(com_llm_llm_tx_top_tx_tlp_sof_pre_n), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_d_i_0_0[43]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_d_i_0_0_51_.INIT = 16'hEEF0; + LUT4 com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_d_i_0_0_51_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_d_i_o3[52]), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_267_), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tsn_pipe_47_), + .I3(com_llm_llm_tx_top_tx_tlp_sof_pre_n), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_d_i_0_0[51]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_N_57527_i.INIT = 4'h7; + LUT2 com_llm_llm_tx_top_llmx08_tx_tlp_komp_N_57527_i ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_N_57527_1), + .I1(com_llm_llm_tx_top_tx_tlp_eof_n), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_N_57527_i_2034) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_td_mux_i_m3_i_m3_0_10_.INIT = 8'hB8; + LUT3_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_td_mux_i_m3_i_m3_0_10_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_bat_td[10]), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_holy_stashed_data_2036), + .I2(com_lnk_td[10]), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_td_mux_i_m3_i_m3_0[10]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_td_mux_i_m3_i_m3_0_9_.INIT = 8'hB8; + LUT3_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_td_mux_i_m3_i_m3_0_9_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_bat_td[9]), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_holy_stashed_data_2036), + .I2(com_lnk_td[9]), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_td_mux_i_m3_i_m3_0[9]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_td_mux_i_m3_i_m3_0_8_.INIT = 8'hB8; + LUT3_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_td_mux_i_m3_i_m3_0_8_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_bat_td[8]), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_holy_stashed_data_2036), + .I2(com_lnk_td[8]), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_td_mux_i_m3_i_m3_0[8]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_td_mux_i_m3_i_m3_i_m3_0_7_.INIT = 8'hB8; + LUT3_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_td_mux_i_m3_i_m3_i_m3_0_7_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_bat_td[7]), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_holy_stashed_data_2036), + .I2(com_lnk_td[7]), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_td_mux_i_m3_i_m3_i_m3_0[7]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_td_mux_i_m3_i_m3_i_m3_0_6_.INIT = 8'hB8; + LUT3_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_td_mux_i_m3_i_m3_i_m3_0_6_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_bat_td[6]), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_holy_stashed_data_2036), + .I2(com_lnk_td[6]), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_td_mux_i_m3_i_m3_i_m3_0[6]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_td_mux_i_m3_i_m3_i_m3_0_5_.INIT = 8'hB8; + LUT3_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_td_mux_i_m3_i_m3_i_m3_0_5_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_bat_td[5]), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_holy_stashed_data_2036), + .I2(com_lnk_td[5]), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_td_mux_i_m3_i_m3_i_m3_0[5]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_td_mux_i_m3_i_m3_i_m3_0_4_.INIT = 8'hB8; + LUT3_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_td_mux_i_m3_i_m3_i_m3_0_4_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_bat_td[4]), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_holy_stashed_data_2036), + .I2(com_lnk_td[4]), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_td_mux_i_m3_i_m3_i_m3_0[4]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_td_mux_i_m3_i_m3_i_m3_0_3_.INIT = 8'hB8; + LUT3_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_td_mux_i_m3_i_m3_i_m3_0_3_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_bat_td[3]), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_holy_stashed_data_2036), + .I2(com_lnk_td[3]), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_td_mux_i_m3_i_m3_i_m3_0[3]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_td_mux_i_m3_i_m3_i_m3_0_2_.INIT = 8'hB8; + LUT3_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_td_mux_i_m3_i_m3_i_m3_0_2_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_bat_td[2]), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_holy_stashed_data_2036), + .I2(com_lnk_td[2]), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_td_mux_i_m3_i_m3_i_m3_0[2]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_td_mux_i_m3_i_m3_i_m3_0_1_.INIT = 8'hB8; + LUT3_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_td_mux_i_m3_i_m3_i_m3_0_1_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_bat_td[1]), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_holy_stashed_data_2036), + .I2(com_lnk_td[1]), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_td_mux_i_m3_i_m3_i_m3_0[1]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_td_mux_i_m3_i_m3_i_m3_0_0_.INIT = 8'hB8; + LUT3_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_td_mux_i_m3_i_m3_i_m3_0_0_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_bat_td[0]), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_holy_stashed_data_2036), + .I2(com_lnk_td[0]), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_td_mux_i_m3_i_m3_i_m3_0[0]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_td_mux_i_m3_i_m3_0_25_.INIT = 8'hB8; + LUT3_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_td_mux_i_m3_i_m3_0_25_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_bat_td[25]), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_holy_stashed_data_2036), + .I2(com_lnk_td[25]), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_td_mux_i_m3_i_m3_0[25]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_td_mux_i_m3_i_m3_0_24_.INIT = 8'hB8; + LUT3_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_td_mux_i_m3_i_m3_0_24_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_bat_td[24]), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_holy_stashed_data_2036), + .I2(com_lnk_td[24]), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_td_mux_i_m3_i_m3_0[24]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_td_mux_i_m3_i_m3_0_23_.INIT = 8'hB8; + LUT3_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_td_mux_i_m3_i_m3_0_23_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_bat_td[23]), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_holy_stashed_data_2036), + .I2(com_lnk_td[23]), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_td_mux_i_m3_i_m3_0[23]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_td_mux_i_m3_i_m3_0_22_.INIT = 8'hB8; + LUT3_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_td_mux_i_m3_i_m3_0_22_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_bat_td[22]), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_holy_stashed_data_2036), + .I2(com_lnk_td[22]), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_td_mux_i_m3_i_m3_0[22]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_td_mux_i_m3_i_m3_0_21_.INIT = 8'hB8; + LUT3_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_td_mux_i_m3_i_m3_0_21_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_bat_td[21]), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_holy_stashed_data_2036), + .I2(com_lnk_td[21]), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_td_mux_i_m3_i_m3_0[21]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_td_mux_i_m3_i_m3_0_20_.INIT = 8'hB8; + LUT3_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_td_mux_i_m3_i_m3_0_20_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_bat_td[20]), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_holy_stashed_data_2036), + .I2(com_lnk_td[20]), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_td_mux_i_m3_i_m3_0[20]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_td_mux_i_m3_i_m3_0_19_.INIT = 8'hB8; + LUT3_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_td_mux_i_m3_i_m3_0_19_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_bat_td[19]), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_holy_stashed_data_2036), + .I2(com_lnk_td[19]), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_td_mux_i_m3_i_m3_0[19]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_td_mux_i_m3_i_m3_0_18_.INIT = 8'hB8; + LUT3_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_td_mux_i_m3_i_m3_0_18_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_bat_td[18]), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_holy_stashed_data_2036), + .I2(com_lnk_td[18]), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_td_mux_i_m3_i_m3_0[18]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_td_mux_i_m3_i_m3_0_17_.INIT = 8'hB8; + LUT3_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_td_mux_i_m3_i_m3_0_17_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_bat_td[17]), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_holy_stashed_data_2036), + .I2(com_lnk_td[17]), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_td_mux_i_m3_i_m3_0[17]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_td_mux_i_m3_i_m3_0_16_.INIT = 8'hB8; + LUT3_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_td_mux_i_m3_i_m3_0_16_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_bat_td[16]), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_holy_stashed_data_2036), + .I2(com_lnk_td[16]), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_td_mux_i_m3_i_m3_0[16]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_td_mux_i_m3_i_m3_0_15_.INIT = 8'hB8; + LUT3_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_td_mux_i_m3_i_m3_0_15_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_bat_td[15]), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_holy_stashed_data_2036), + .I2(com_lnk_td[15]), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_td_mux_i_m3_i_m3_0[15]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_td_mux_i_m3_i_m3_0_14_.INIT = 8'hB8; + LUT3_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_td_mux_i_m3_i_m3_0_14_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_bat_td[14]), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_holy_stashed_data_2036), + .I2(com_lnk_td[14]), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_td_mux_i_m3_i_m3_0[14]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_td_mux_i_m3_i_m3_0_13_.INIT = 8'hB8; + LUT3_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_td_mux_i_m3_i_m3_0_13_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_bat_td[13]), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_holy_stashed_data_2036), + .I2(com_lnk_td[13]), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_td_mux_i_m3_i_m3_0[13]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_td_mux_i_m3_i_m3_0_12_.INIT = 8'hB8; + LUT3_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_td_mux_i_m3_i_m3_0_12_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_bat_td[12]), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_holy_stashed_data_2036), + .I2(com_lnk_td[12]), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_td_mux_i_m3_i_m3_0[12]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_td_mux_i_m3_i_m3_0_11_.INIT = 8'hB8; + LUT3_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_td_mux_i_m3_i_m3_0_11_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_bat_td[11]), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_holy_stashed_data_2036), + .I2(com_lnk_td[11]), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_td_mux_i_m3_i_m3_0[11]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_td_mux_i_m3_i_m3_0_40_.INIT = 8'hB8; + LUT3_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_td_mux_i_m3_i_m3_0_40_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_bat_td[40]), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_holy_stashed_data_2036), + .I2(com_lnk_td[40]), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_td_mux_i_m3_i_m3_0[40]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_td_mux_i_m3_i_m3_0_39_.INIT = 8'hB8; + LUT3_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_td_mux_i_m3_i_m3_0_39_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_bat_td[39]), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_holy_stashed_data_2036), + .I2(com_lnk_td[39]), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_td_mux_i_m3_i_m3_0[39]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_td_mux_i_m3_i_m3_0_38_.INIT = 8'hB8; + LUT3_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_td_mux_i_m3_i_m3_0_38_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_bat_td[38]), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_holy_stashed_data_2036), + .I2(com_lnk_td[38]), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_td_mux_i_m3_i_m3_0[38]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_td_mux_i_m3_i_m3_0_37_.INIT = 8'hB8; + LUT3_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_td_mux_i_m3_i_m3_0_37_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_bat_td[37]), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_holy_stashed_data_2036), + .I2(com_lnk_td[37]), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_td_mux_i_m3_i_m3_0[37]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_td_mux_i_m3_i_m3_0_36_.INIT = 8'hB8; + LUT3_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_td_mux_i_m3_i_m3_0_36_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_bat_td[36]), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_holy_stashed_data_2036), + .I2(com_lnk_td[36]), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_td_mux_i_m3_i_m3_0[36]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_td_mux_i_m3_i_m3_0_35_.INIT = 8'hB8; + LUT3_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_td_mux_i_m3_i_m3_0_35_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_bat_td[35]), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_holy_stashed_data_2036), + .I2(com_lnk_td[35]), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_td_mux_i_m3_i_m3_0[35]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_td_mux_i_m3_i_m3_0_34_.INIT = 8'hB8; + LUT3_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_td_mux_i_m3_i_m3_0_34_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_bat_td[34]), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_holy_stashed_data_2036), + .I2(com_lnk_td[34]), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_td_mux_i_m3_i_m3_0[34]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_td_mux_i_m3_i_m3_0_33_.INIT = 8'hB8; + LUT3_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_td_mux_i_m3_i_m3_0_33_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_bat_td[33]), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_holy_stashed_data_2036), + .I2(com_lnk_td[33]), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_td_mux_i_m3_i_m3_0[33]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_td_mux_i_m3_i_m3_0_32_.INIT = 8'hB8; + LUT3_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_td_mux_i_m3_i_m3_0_32_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_bat_td[32]), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_holy_stashed_data_2036), + .I2(com_lnk_td[32]), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_td_mux_i_m3_i_m3_0[32]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_td_mux_i_m3_i_m3_0_31_.INIT = 8'hB8; + LUT3_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_td_mux_i_m3_i_m3_0_31_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_bat_td[31]), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_holy_stashed_data_2036), + .I2(com_lnk_td[31]), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_td_mux_i_m3_i_m3_0[31]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_td_mux_i_m3_i_m3_0_30_.INIT = 8'hB8; + LUT3_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_td_mux_i_m3_i_m3_0_30_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_bat_td[30]), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_holy_stashed_data_2036), + .I2(com_lnk_td[30]), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_td_mux_i_m3_i_m3_0[30]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_td_mux_i_m3_i_m3_0_29_.INIT = 8'hB8; + LUT3_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_td_mux_i_m3_i_m3_0_29_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_bat_td[29]), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_holy_stashed_data_2036), + .I2(com_lnk_td[29]), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_td_mux_i_m3_i_m3_0[29]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_td_mux_i_m3_i_m3_0_28_.INIT = 8'hB8; + LUT3_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_td_mux_i_m3_i_m3_0_28_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_bat_td[28]), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_holy_stashed_data_2036), + .I2(com_lnk_td[28]), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_td_mux_i_m3_i_m3_0[28]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_td_mux_i_m3_i_m3_0_27_.INIT = 8'hB8; + LUT3_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_td_mux_i_m3_i_m3_0_27_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_bat_td[27]), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_holy_stashed_data_2036), + .I2(com_lnk_td[27]), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_td_mux_i_m3_i_m3_0[27]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_td_mux_i_m3_i_m3_0_26_.INIT = 8'hB8; + LUT3_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_td_mux_i_m3_i_m3_0_26_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_bat_td[26]), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_holy_stashed_data_2036), + .I2(com_lnk_td[26]), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_td_mux_i_m3_i_m3_0[26]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_td_mux_i_m3_i_m3_0_55_.INIT = 8'hB8; + LUT3_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_td_mux_i_m3_i_m3_0_55_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_bat_td[55]), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_holy_stashed_data_2036), + .I2(com_lnk_td[55]), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_td_mux_i_m3_i_m3_0[55]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_td_mux_i_m3_i_m3_0_54_.INIT = 8'hB8; + LUT3_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_td_mux_i_m3_i_m3_0_54_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_bat_td[54]), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_holy_stashed_data_2036), + .I2(com_lnk_td[54]), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_td_mux_i_m3_i_m3_0[54]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_td_mux_i_m3_i_m3_0_53_.INIT = 8'hB8; + LUT3_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_td_mux_i_m3_i_m3_0_53_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_bat_td[53]), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_holy_stashed_data_2036), + .I2(com_lnk_td[53]), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_td_mux_i_m3_i_m3_0[53]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_td_mux_i_m3_i_m3_0_52_.INIT = 8'hB8; + LUT3_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_td_mux_i_m3_i_m3_0_52_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_bat_td[52]), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_holy_stashed_data_2036), + .I2(com_lnk_td[52]), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_td_mux_i_m3_i_m3_0[52]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_td_mux_i_m3_i_m3_0_51_.INIT = 8'hB8; + LUT3_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_td_mux_i_m3_i_m3_0_51_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_bat_td[51]), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_holy_stashed_data_2036), + .I2(com_lnk_td[51]), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_td_mux_i_m3_i_m3_0[51]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_td_mux_i_m3_i_m3_0_50_.INIT = 8'hB8; + LUT3_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_td_mux_i_m3_i_m3_0_50_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_bat_td[50]), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_holy_stashed_data_2036), + .I2(com_lnk_td[50]), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_td_mux_i_m3_i_m3_0[50]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_td_mux_i_m3_i_m3_0_49_.INIT = 8'hB8; + LUT3_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_td_mux_i_m3_i_m3_0_49_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_bat_td[49]), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_holy_stashed_data_2036), + .I2(com_lnk_td[49]), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_td_mux_i_m3_i_m3_0[49]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_td_mux_i_m3_i_m3_0_48_.INIT = 8'hB8; + LUT3_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_td_mux_i_m3_i_m3_0_48_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_bat_td[48]), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_holy_stashed_data_2036), + .I2(com_lnk_td[48]), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_td_mux_i_m3_i_m3_0[48]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_td_mux_i_m3_i_m3_0_47_.INIT = 8'hB8; + LUT3_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_td_mux_i_m3_i_m3_0_47_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_bat_td[47]), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_holy_stashed_data_2036), + .I2(com_lnk_td[47]), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_td_mux_i_m3_i_m3_0[47]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_td_mux_i_m3_i_m3_0_46_.INIT = 8'hB8; + LUT3_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_td_mux_i_m3_i_m3_0_46_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_bat_td[46]), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_holy_stashed_data_2036), + .I2(com_lnk_td[46]), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_td_mux_i_m3_i_m3_0[46]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_td_mux_i_m3_i_m3_0_45_.INIT = 8'hB8; + LUT3_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_td_mux_i_m3_i_m3_0_45_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_bat_td[45]), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_holy_stashed_data_2036), + .I2(com_lnk_td[45]), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_td_mux_i_m3_i_m3_0[45]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_td_mux_i_m3_i_m3_0_44_.INIT = 8'hB8; + LUT3_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_td_mux_i_m3_i_m3_0_44_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_bat_td[44]), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_holy_stashed_data_2036), + .I2(com_lnk_td[44]), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_td_mux_i_m3_i_m3_0[44]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_td_mux_i_m3_i_m3_0_43_.INIT = 8'hB8; + LUT3_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_td_mux_i_m3_i_m3_0_43_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_bat_td[43]), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_holy_stashed_data_2036), + .I2(com_lnk_td[43]), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_td_mux_i_m3_i_m3_0[43]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_td_mux_i_m3_i_m3_0_42_.INIT = 8'hB8; + LUT3_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_td_mux_i_m3_i_m3_0_42_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_bat_td[42]), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_holy_stashed_data_2036), + .I2(com_lnk_td[42]), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_td_mux_i_m3_i_m3_0[42]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_td_mux_i_m3_i_m3_0_41_.INIT = 8'hB8; + LUT3_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_td_mux_i_m3_i_m3_0_41_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_bat_td[41]), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_holy_stashed_data_2036), + .I2(com_lnk_td[41]), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_td_mux_i_m3_i_m3_0[41]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_td_mux_i_m3_i_m3_0_63_.INIT = 8'hB8; + LUT3_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_td_mux_i_m3_i_m3_0_63_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_bat_td[63]), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_holy_stashed_data_2036), + .I2(com_lnk_td[63]), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_td_mux_i_m3_i_m3_0[63]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_td_mux_i_m3_i_m3_0_62_.INIT = 8'hB8; + LUT3_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_td_mux_i_m3_i_m3_0_62_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_bat_td[62]), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_holy_stashed_data_2036), + .I2(com_lnk_td[62]), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_td_mux_i_m3_i_m3_0[62]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_td_mux_i_m3_i_m3_0_61_.INIT = 8'hB8; + LUT3_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_td_mux_i_m3_i_m3_0_61_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_bat_td[61]), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_holy_stashed_data_2036), + .I2(com_lnk_td[61]), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_td_mux_i_m3_i_m3_0[61]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_td_mux_i_m3_i_m3_0_60_.INIT = 8'hB8; + LUT3_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_td_mux_i_m3_i_m3_0_60_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_bat_td[60]), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_holy_stashed_data_2036), + .I2(com_lnk_td[60]), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_td_mux_i_m3_i_m3_0[60]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_td_mux_i_m3_i_m3_0_59_.INIT = 8'hB8; + LUT3_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_td_mux_i_m3_i_m3_0_59_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_bat_td[59]), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_holy_stashed_data_2036), + .I2(com_lnk_td[59]), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_td_mux_i_m3_i_m3_0[59]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_td_mux_i_m3_i_m3_0_58_.INIT = 8'hB8; + LUT3_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_td_mux_i_m3_i_m3_0_58_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_bat_td[58]), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_holy_stashed_data_2036), + .I2(com_lnk_td[58]), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_td_mux_i_m3_i_m3_0[58]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_td_mux_i_m3_i_m3_0_57_.INIT = 8'hB8; + LUT3_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_td_mux_i_m3_i_m3_0_57_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_bat_td[57]), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_holy_stashed_data_2036), + .I2(com_lnk_td[57]), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_td_mux_i_m3_i_m3_0[57]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_td_mux_i_m3_i_m3_0_56_.INIT = 8'hB8; + LUT3_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_td_mux_i_m3_i_m3_0_56_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_bat_td[56]), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_holy_stashed_data_2036), + .I2(com_lnk_td[56]), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_td_mux_i_m3_i_m3_0[56]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_crcint_i_0_0.INIT = 4'h2; + LUT2_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_crcint_i_0_0 ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_sof_n_mux_i), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_N_16899_i) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_N_86845_i.INIT = 16'hBBB8; + LUT4_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_N_86845_i ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_bat_rem_2037), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_holy_stashed_data_2036), + .I2(com_lnk_tdst_rdy_n), + .I3(com_lnk_trem[0]), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_N_86845_i_2035) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_sof_n_mux_i_i.INIT = 4'h1; + LUT1_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_sof_n_mux_i_i ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_sof_n_mux_i), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_sof_n_mux_i_i_2038) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_N_85587_i.INIT = 16'hFF57; + LUT4_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_N_85587_i ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_N_30495_i), + .I1(com_link_status[2]), + .I2(com_link_status[3]), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_N_85587_i_2039) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_d_i_0_63_.INIT = 16'hE400; + LUT4_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_d_i_0_63_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_d_i_o3[52]), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_279_), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_crc[23]), + .I3(com_llm_llm_tx_top_tx_tlp_sof_pre_n), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_N_25962_i) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_d_i_0_62_.INIT = 16'hE400; + LUT4_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_d_i_0_62_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_d_i_o3[52]), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_278_), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_crc[22]), + .I3(com_llm_llm_tx_top_tx_tlp_sof_pre_n), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_N_25960_i) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_d_i_0_61_.INIT = 16'hE400; + LUT4_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_d_i_0_61_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_d_i_o3[52]), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_277_), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_crc[21]), + .I3(com_llm_llm_tx_top_tx_tlp_sof_pre_n), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_N_25958_i) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_d_i_0_60_.INIT = 16'hE400; + LUT4_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_d_i_0_60_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_d_i_o3[52]), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_276_), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_crc[20]), + .I3(com_llm_llm_tx_top_tx_tlp_sof_pre_n), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_N_25956_i) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_d_i_0_59_.INIT = 16'hE400; + LUT4_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_d_i_0_59_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_d_i_o3[52]), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_275_), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_crc[19]), + .I3(com_llm_llm_tx_top_tx_tlp_sof_pre_n), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_N_25954_i) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_d_i_0_58_.INIT = 16'hE400; + LUT4_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_d_i_0_58_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_d_i_o3[52]), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_274_), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_crc[18]), + .I3(com_llm_llm_tx_top_tx_tlp_sof_pre_n), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_N_25952_i) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_d_i_57_.INIT = 16'hE400; + LUT4_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_d_i_57_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_d_i_o3[52]), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_273_), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_crc[17]), + .I3(com_llm_llm_tx_top_tx_tlp_sof_pre_n), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_N_51730_i) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_d_i_0_56_.INIT = 16'hE400; + LUT4_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_d_i_0_56_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_d_i_o3[52]), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_272_), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_crc[16]), + .I3(com_llm_llm_tx_top_tx_tlp_sof_pre_n), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_N_25950_i) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_d_i_0_55_.INIT = 16'hE400; + LUT4_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_d_i_0_55_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_d_i_o3[52]), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_271_), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_crc[15]), + .I3(com_llm_llm_tx_top_tx_tlp_sof_pre_n), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_N_25948_i) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_d_i_54_.INIT = 16'hE400; + LUT4_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_d_i_54_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_d_i_o3[52]), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_270_), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_crc[14]), + .I3(com_llm_llm_tx_top_tx_tlp_sof_pre_n), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_N_51728_i) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_d_i_53_.INIT = 16'hE400; + LUT4_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_d_i_53_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_d_i_o3[52]), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_269_), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_crc[13]), + .I3(com_llm_llm_tx_top_tx_tlp_sof_pre_n), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_N_51726_i) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_d_i_52_.INIT = 16'hE400; + LUT4_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_d_i_52_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_d_i_o3[52]), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_268_), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_crc[12]), + .I3(com_llm_llm_tx_top_tx_tlp_sof_pre_n), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_N_51724_i) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_d_i_0_51_.INIT = 8'hD0; + LUT3_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_d_i_0_51_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_N_61377), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_crc[11]), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_d_i_0_0[51]), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_N_25946_i) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_d_i_0_50_.INIT = 8'hD0; + LUT3_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_d_i_0_50_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_N_61377), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_crc[10]), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_d_i_0_0[50]), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_N_25944_i) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_d_i_0_49_.INIT = 8'hD0; + LUT3_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_d_i_0_49_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_N_61377), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_crc[9]), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_d_i_0_0[49]), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_N_25942_i) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_d_i_0_48_.INIT = 8'hD0; + LUT3_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_d_i_0_48_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_N_61377), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_crc[8]), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_d_i_0_0[48]), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_N_25940_i) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_d_i_0_47_.INIT = 8'hD0; + LUT3_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_d_i_0_47_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_N_61377), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_crc[7]), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_d_i_0_0[47]), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_N_25938_i) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_d_i_0_46_.INIT = 8'hD0; + LUT3_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_d_i_0_46_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_N_61377), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_crc[6]), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_d_i_0_0[46]), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_N_25936_i) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_d_i_0_45_.INIT = 8'hD0; + LUT3_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_d_i_0_45_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_N_61377), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_crc[5]), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_d_i_0_0[45]), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_N_25934_i) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_d_i_0_44_.INIT = 8'hD0; + LUT3_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_d_i_0_44_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_N_61377), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_crc[4]), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_d_i_0_0[44]), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_N_25932_i) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_d_i_0_43_.INIT = 8'hD0; + LUT3_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_d_i_0_43_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_N_61377), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_crc[3]), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_d_i_0_0[43]), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_N_25930_i) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_d_i_0_42_.INIT = 8'hD0; + LUT3_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_d_i_0_42_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_N_61377), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_crc[2]), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_d_i_0_0[42]), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_N_25928_i) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_d_i_0_41_.INIT = 8'hD0; + LUT3_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_d_i_0_41_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_N_61377), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_crc[1]), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_d_i_0_0[41]), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_N_25926_i) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_d_i_0_40_.INIT = 8'hD0; + LUT3_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_d_i_0_40_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_N_61377), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_crc[0]), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_d_i_0_0[40]), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_N_25924_i) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_N_86895_i.INIT = 16'h44E4; + LUT4_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_N_86895_i ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_N_55885_i), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_255_), + .I2(com_llm_llm_tx_top_rem_pipe[4]), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_sw_early_crc[31]), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_N_86895_i_2070) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_N_86894_i.INIT = 16'h44E4; + LUT4_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_N_86894_i ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_N_55885_i), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_254_), + .I2(com_llm_llm_tx_top_rem_pipe[4]), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_sw_early_crc[30]), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_N_86894_i_2071) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_N_86893_i.INIT = 16'h44E4; + LUT4_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_N_86893_i ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_N_55885_i), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_253_), + .I2(com_llm_llm_tx_top_rem_pipe[4]), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_sw_early_crc[29]), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_N_86893_i_2072) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_N_86892_i.INIT = 16'h44E4; + LUT4_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_N_86892_i ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_N_55885_i), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_252_), + .I2(com_llm_llm_tx_top_rem_pipe[4]), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_sw_early_crc[28]), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_N_86892_i_2073) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_N_86891_i.INIT = 16'h44E4; + LUT4_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_N_86891_i ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_N_55885_i), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_251_), + .I2(com_llm_llm_tx_top_rem_pipe[4]), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_sw_early_crc[27]), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_N_86891_i_2074) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_N_86890_i.INIT = 16'h44E4; + LUT4_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_N_86890_i ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_N_55885_i), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_250_), + .I2(com_llm_llm_tx_top_rem_pipe[4]), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_sw_early_crc[26]), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_N_86890_i_2075) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_N_86889_i.INIT = 16'h44E4; + LUT4_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_N_86889_i ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_N_55885_i), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_249_), + .I2(com_llm_llm_tx_top_rem_pipe[4]), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_sw_early_crc[25]), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_N_86889_i_2076) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_N_86888_i.INIT = 16'h44E4; + LUT4_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_N_86888_i ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_N_55885_i), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_248_), + .I2(com_llm_llm_tx_top_rem_pipe[4]), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_sw_early_crc[24]), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_N_86888_i_2077) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_N_86887_i.INIT = 16'h44E4; + LUT4_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_N_86887_i ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_N_55885_i), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_247_), + .I2(com_llm_llm_tx_top_rem_pipe[4]), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_sw_early_crc[23]), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_N_86887_i_2078) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_N_86886_i.INIT = 16'h44E4; + LUT4_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_N_86886_i ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_N_55885_i), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_246_), + .I2(com_llm_llm_tx_top_rem_pipe[4]), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_sw_early_crc[22]), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_N_86886_i_2079) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_N_86885_i.INIT = 16'h44E4; + LUT4_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_N_86885_i ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_N_55885_i), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_245_), + .I2(com_llm_llm_tx_top_rem_pipe[4]), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_sw_early_crc[21]), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_N_86885_i_2080) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_N_86884_i.INIT = 16'h44E4; + LUT4_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_N_86884_i ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_N_55885_i), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_244_), + .I2(com_llm_llm_tx_top_rem_pipe[4]), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_sw_early_crc[20]), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_N_86884_i_2081) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_N_86883_i.INIT = 16'h44E4; + LUT4_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_N_86883_i ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_N_55885_i), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_243_), + .I2(com_llm_llm_tx_top_rem_pipe[4]), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_sw_early_crc[19]), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_N_86883_i_2082) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_N_86882_i.INIT = 16'h44E4; + LUT4_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_N_86882_i ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_N_55885_i), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_242_), + .I2(com_llm_llm_tx_top_rem_pipe[4]), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_sw_early_crc[18]), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_N_86882_i_2083) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_N_86881_i.INIT = 16'h44E4; + LUT4_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_N_86881_i ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_N_55885_i), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_241_), + .I2(com_llm_llm_tx_top_rem_pipe[4]), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_sw_early_crc[17]), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_N_86881_i_2084) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_N_86880_i.INIT = 16'h44E4; + LUT4_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_N_86880_i ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_N_55885_i), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_240_), + .I2(com_llm_llm_tx_top_rem_pipe[4]), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_sw_early_crc[16]), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_N_86880_i_2085) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_N_86879_i.INIT = 16'h44E4; + LUT4_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_N_86879_i ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_N_55885_i), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_239_), + .I2(com_llm_llm_tx_top_rem_pipe[4]), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_sw_early_crc[15]), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_N_86879_i_2086) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_N_86878_i.INIT = 16'h44E4; + LUT4_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_N_86878_i ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_N_55885_i), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_238_), + .I2(com_llm_llm_tx_top_rem_pipe[4]), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_sw_early_crc[14]), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_N_86878_i_2087) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_N_86877_i.INIT = 16'h44E4; + LUT4_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_N_86877_i ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_N_55885_i), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_237_), + .I2(com_llm_llm_tx_top_rem_pipe[4]), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_sw_early_crc[13]), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_N_86877_i_2088) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_N_86876_i.INIT = 16'h44E4; + LUT4_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_N_86876_i ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_N_55885_i), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_236_), + .I2(com_llm_llm_tx_top_rem_pipe[4]), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_sw_early_crc[12]), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_N_86876_i_2089) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_N_86875_i.INIT = 16'h44E4; + LUT4_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_N_86875_i ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_N_55885_i), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_235_), + .I2(com_llm_llm_tx_top_rem_pipe[4]), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_sw_early_crc[11]), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_N_86875_i_2090) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_N_86874_i.INIT = 16'h44E4; + LUT4_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_N_86874_i ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_N_55885_i), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_234_), + .I2(com_llm_llm_tx_top_rem_pipe[4]), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_sw_early_crc[10]), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_N_86874_i_2091) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_N_86873_i.INIT = 16'h44E4; + LUT4_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_N_86873_i ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_N_55885_i), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_233_), + .I2(com_llm_llm_tx_top_rem_pipe[4]), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_sw_early_crc[9]), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_N_86873_i_2092) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_N_86872_i.INIT = 16'h44E4; + LUT4_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_N_86872_i ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_N_55885_i), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_232_), + .I2(com_llm_llm_tx_top_rem_pipe[4]), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_sw_early_crc[8]), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_N_86872_i_2093) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_N_86871_i.INIT = 16'h44E4; + LUT4_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_N_86871_i ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_N_55885_i), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_231_), + .I2(com_llm_llm_tx_top_rem_pipe[4]), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_sw_early_crc[7]), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_N_86871_i_2094) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_N_86870_i.INIT = 16'h44E4; + LUT4_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_N_86870_i ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_N_55885_i), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_230_), + .I2(com_llm_llm_tx_top_rem_pipe[4]), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_sw_early_crc[6]), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_N_86870_i_2095) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_N_86869_i.INIT = 16'h44E4; + LUT4_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_N_86869_i ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_N_55885_i), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_229_), + .I2(com_llm_llm_tx_top_rem_pipe[4]), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_sw_early_crc[5]), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_N_86869_i_2096) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_N_86868_i.INIT = 16'h44E4; + LUT4_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_N_86868_i ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_N_55885_i), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_228_), + .I2(com_llm_llm_tx_top_rem_pipe[4]), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_sw_early_crc[4]), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_N_86868_i_2097) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_N_86867_i.INIT = 16'h44E4; + LUT4_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_N_86867_i ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_N_55885_i), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_227_), + .I2(com_llm_llm_tx_top_rem_pipe[4]), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_sw_early_crc[3]), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_N_86867_i_2098) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_N_86866_i.INIT = 16'h44E4; + LUT4_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_N_86866_i ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_N_55885_i), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_226_), + .I2(com_llm_llm_tx_top_rem_pipe[4]), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_sw_early_crc[2]), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_N_86866_i_2099) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_N_86865_i.INIT = 16'h44E4; + LUT4_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_N_86865_i ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_N_55885_i), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_225_), + .I2(com_llm_llm_tx_top_rem_pipe[4]), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_sw_early_crc[1]), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_N_86865_i_2100) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_N_86864_i.INIT = 16'h44E4; + LUT4_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_N_86864_i ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_N_55885_i), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_224_), + .I2(com_llm_llm_tx_top_rem_pipe[4]), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_sw_early_crc[0]), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_N_86864_i_2101) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_N_86863_i.INIT = 16'h30BA; + LUT4_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_N_86863_i ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_N_61392), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_d_2_o3[0]), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_223_), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_sw_early_crc[31]), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_N_86863_i_2102) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_N_86862_i.INIT = 16'h30BA; + LUT4_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_N_86862_i ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_N_61392), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_d_2_o3[0]), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_222_), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_sw_early_crc[30]), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_N_86862_i_2103) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_N_86861_i.INIT = 16'h30BA; + LUT4_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_N_86861_i ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_N_61392), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_d_2_o3[0]), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_221_), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_sw_early_crc[29]), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_N_86861_i_2104) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_N_86860_i.INIT = 16'h30BA; + LUT4_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_N_86860_i ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_N_61392), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_d_2_o3[0]), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_220_), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_sw_early_crc[28]), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_N_86860_i_2105) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_N_86859_i.INIT = 16'h30BA; + LUT4_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_N_86859_i ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_N_61392), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_d_2_o3[0]), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_219_), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_sw_early_crc[27]), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_N_86859_i_2106) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_N_86858_i.INIT = 16'h30BA; + LUT4_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_N_86858_i ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_N_61392), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_d_2_o3[0]), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_218_), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_sw_early_crc[26]), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_N_86858_i_2107) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_N_86857_i.INIT = 16'h30BA; + LUT4_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_N_86857_i ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_N_61392), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_d_2_o3[0]), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_217_), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_sw_early_crc[25]), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_N_86857_i_2108) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_N_86856_i.INIT = 16'h30BA; + LUT4_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_N_86856_i ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_N_61392), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_d_2_o3[0]), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_216_), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_sw_early_crc[24]), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_N_86856_i_2109) + ); + SRL16E com_llm_llm_tx_top_llmx08_tx_tlp_komp_rem_pipe_I_1 ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_i_65), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_rem_pipe_6115[0]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_rem_pipe_tmp_d_array_0[0]), + .CLK(NlwRenamedSig_OI_trn_clk), + .A0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_VCC_2041), + .A1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_GND_2040), + .A2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_GND_2040), + .A3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_GND_2040) + ); + SRL16E com_llm_llm_tx_top_llmx08_tx_tlp_komp_eof_n_pipe_I_1 ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_i_65), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_eof_n_pipe_6114[1]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_eof_n_pipe_N_6), + .CLK(NlwRenamedSig_OI_trn_clk), + .A0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_VCC_2041), + .A1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_GND_2040), + .A2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_GND_2040), + .A3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_GND_2040) + ); + SRL16E com_llm_llm_tx_top_llmx08_tx_tlp_komp_tsn_pipe_I_1 ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_i_65), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tsn_pipe_0__2069), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tsn_pipe_N_6), + .CLK(NlwRenamedSig_OI_trn_clk), + .A0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_VCC_2041), + .A1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_GND_2040), + .A2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_GND_2040), + .A3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_GND_2040) + ); + SRL16E com_llm_llm_tx_top_llmx08_tx_tlp_komp_tsn_pipe_0_I_1 ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_i_65), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tsn_pipe_1__2068), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tsn_pipe_0_N_6), + .CLK(NlwRenamedSig_OI_trn_clk), + .A0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_VCC_2041), + .A1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_GND_2040), + .A2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_GND_2040), + .A3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_GND_2040) + ); + SRL16E com_llm_llm_tx_top_llmx08_tx_tlp_komp_tsn_pipe_1_I_1 ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_i_65), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tsn_pipe_2__2067), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tsn_pipe_1_N_6), + .CLK(NlwRenamedSig_OI_trn_clk), + .A0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_VCC_2041), + .A1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_GND_2040), + .A2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_GND_2040), + .A3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_GND_2040) + ); + SRL16E com_llm_llm_tx_top_llmx08_tx_tlp_komp_tsn_pipe_2_I_1 ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_i_65), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tsn_pipe_3__2066), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tsn_pipe_2_N_6), + .CLK(NlwRenamedSig_OI_trn_clk), + .A0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_VCC_2041), + .A1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_GND_2040), + .A2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_GND_2040), + .A3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_GND_2040) + ); + SRL16E com_llm_llm_tx_top_llmx08_tx_tlp_komp_tsn_pipe_3_I_1 ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_i_65), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tsn_pipe_4__2065), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tsn_pipe_3_N_6), + .CLK(NlwRenamedSig_OI_trn_clk), + .A0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_VCC_2041), + .A1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_GND_2040), + .A2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_GND_2040), + .A3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_GND_2040) + ); + SRL16E com_llm_llm_tx_top_llmx08_tx_tlp_komp_tsn_pipe_4_I_1 ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_i_65), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tsn_pipe_5__2064), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tsn_pipe_4_N_6), + .CLK(NlwRenamedSig_OI_trn_clk), + .A0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_VCC_2041), + .A1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_GND_2040), + .A2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_GND_2040), + .A3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_GND_2040) + ); + SRL16E com_llm_llm_tx_top_llmx08_tx_tlp_komp_tsn_pipe_5_I_1 ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_i_65), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tsn_pipe_6__2063), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tsn_pipe_5_N_6), + .CLK(NlwRenamedSig_OI_trn_clk), + .A0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_VCC_2041), + .A1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_GND_2040), + .A2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_GND_2040), + .A3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_GND_2040) + ); + SRL16E com_llm_llm_tx_top_llmx08_tx_tlp_komp_tsn_pipe_6_I_1 ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_i_65), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tsn_pipe_7__2062), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tsn_pipe_6_N_6), + .CLK(NlwRenamedSig_OI_trn_clk), + .A0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_VCC_2041), + .A1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_GND_2040), + .A2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_GND_2040), + .A3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_GND_2040) + ); + SRL16E com_llm_llm_tx_top_llmx08_tx_tlp_komp_tsn_pipe_7_I_1 ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_i_65), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tsn_pipe_8__2061), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tsn_pipe_7_N_6), + .CLK(NlwRenamedSig_OI_trn_clk), + .A0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_VCC_2041), + .A1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_GND_2040), + .A2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_GND_2040), + .A3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_GND_2040) + ); + SRL16E com_llm_llm_tx_top_llmx08_tx_tlp_komp_tsn_pipe_8_I_1 ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_i_65), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tsn_pipe_9__2060), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tsn_pipe_8_N_6), + .CLK(NlwRenamedSig_OI_trn_clk), + .A0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_VCC_2041), + .A1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_GND_2040), + .A2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_GND_2040), + .A3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_GND_2040) + ); + SRL16E com_llm_llm_tx_top_llmx08_tx_tlp_komp_tsn_pipe_9_I_1 ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_i_65), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tsn_pipe_10__2059), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tsn_pipe_9_N_6), + .CLK(NlwRenamedSig_OI_trn_clk), + .A0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_VCC_2041), + .A1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_GND_2040), + .A2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_GND_2040), + .A3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_GND_2040) + ); + SRL16E com_llm_llm_tx_top_llmx08_tx_tlp_komp_tsn_pipe_10_I_1 ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_i_65), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tsn_pipe_11__2058), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tsn_pipe_10_N_6), + .CLK(NlwRenamedSig_OI_trn_clk), + .A0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_VCC_2041), + .A1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_GND_2040), + .A2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_GND_2040), + .A3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_GND_2040) + ); + SRL16E com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_I_1 ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_i_65), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_d16_sw[13]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_N_6), + .CLK(NlwRenamedSig_OI_trn_clk), + .A0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_VCC_2041), + .A1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_GND_2040), + .A2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_GND_2040), + .A3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_GND_2040) + ); + SRL16E com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_0_I_1 ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_i_65), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_d16_sw[12]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_0_N_6), + .CLK(NlwRenamedSig_OI_trn_clk), + .A0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_VCC_2041), + .A1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_GND_2040), + .A2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_GND_2040), + .A3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_GND_2040) + ); + SRL16E com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_1_I_1 ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_i_65), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_d16_sw[11]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_1_N_6), + .CLK(NlwRenamedSig_OI_trn_clk), + .A0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_VCC_2041), + .A1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_GND_2040), + .A2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_GND_2040), + .A3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_GND_2040) + ); + SRL16E com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_2_I_1 ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_i_65), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_d16_sw[10]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_2_N_6), + .CLK(NlwRenamedSig_OI_trn_clk), + .A0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_VCC_2041), + .A1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_GND_2040), + .A2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_GND_2040), + .A3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_GND_2040) + ); + SRL16E com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_3_I_1 ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_i_65), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_d16_sw[9]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_3_N_6), + .CLK(NlwRenamedSig_OI_trn_clk), + .A0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_VCC_2041), + .A1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_GND_2040), + .A2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_GND_2040), + .A3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_GND_2040) + ); + SRL16E com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_4_I_1 ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_i_65), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_d16_sw[8]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_4_N_6), + .CLK(NlwRenamedSig_OI_trn_clk), + .A0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_VCC_2041), + .A1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_GND_2040), + .A2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_GND_2040), + .A3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_GND_2040) + ); + SRL16E com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_5_I_1 ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_i_65), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_d32_sw[7]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_5_tmp_d_array_0[0]), + .CLK(NlwRenamedSig_OI_trn_clk), + .A0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_GND_2040), + .A1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_VCC_2041), + .A2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_GND_2040), + .A3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_GND_2040) + ); + SRL16E com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_6_I_1 ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_i_65), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_d32_sw[6]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_6_N_6), + .CLK(NlwRenamedSig_OI_trn_clk), + .A0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_GND_2040), + .A1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_VCC_2041), + .A2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_GND_2040), + .A3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_GND_2040) + ); + SRL16E com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_7_I_1 ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_i_65), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_d32_sw[5]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_7_N_6), + .CLK(NlwRenamedSig_OI_trn_clk), + .A0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_GND_2040), + .A1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_VCC_2041), + .A2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_GND_2040), + .A3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_GND_2040) + ); + SRL16E com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_8_I_1 ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_i_65), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_d32_sw[4]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_8_N_6), + .CLK(NlwRenamedSig_OI_trn_clk), + .A0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_GND_2040), + .A1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_VCC_2041), + .A2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_GND_2040), + .A3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_GND_2040) + ); + SRL16E com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_9_I_1 ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_i_65), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_d32_sw[3]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_9_N_6), + .CLK(NlwRenamedSig_OI_trn_clk), + .A0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_GND_2040), + .A1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_VCC_2041), + .A2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_GND_2040), + .A3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_GND_2040) + ); + SRL16E com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_10_I_1 ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_i_65), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_d32_sw[2]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_10_N_6), + .CLK(NlwRenamedSig_OI_trn_clk), + .A0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_GND_2040), + .A1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_VCC_2041), + .A2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_GND_2040), + .A3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_GND_2040) + ); + SRL16E com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_11_I_1 ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_i_65), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_d32_sw[1]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_11_N_6), + .CLK(NlwRenamedSig_OI_trn_clk), + .A0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_GND_2040), + .A1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_VCC_2041), + .A2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_GND_2040), + .A3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_GND_2040) + ); + SRL16E com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_12_I_1 ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_i_65), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_d32_sw[0]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_12_N_6), + .CLK(NlwRenamedSig_OI_trn_clk), + .A0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_GND_2040), + .A1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_VCC_2041), + .A2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_GND_2040), + .A3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_GND_2040) + ); + SRL16E com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_13_I_1 ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_i_65), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_d64_sw[44]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_13_N_6), + .CLK(NlwRenamedSig_OI_trn_clk), + .A0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_VCC_2041), + .A1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_GND_2040), + .A2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_GND_2040), + .A3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_GND_2040) + ); + SRL16E com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_14_I_1 ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_i_65), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_d64_sw[43]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_14_N_6), + .CLK(NlwRenamedSig_OI_trn_clk), + .A0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_VCC_2041), + .A1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_GND_2040), + .A2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_GND_2040), + .A3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_GND_2040) + ); + SRL16E com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_15_I_1 ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_i_65), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_d64_sw[42]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_15_N_6), + .CLK(NlwRenamedSig_OI_trn_clk), + .A0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_VCC_2041), + .A1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_GND_2040), + .A2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_GND_2040), + .A3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_GND_2040) + ); + SRL16E com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_16_I_1 ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_i_65), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_d64_sw[41]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_16_N_6), + .CLK(NlwRenamedSig_OI_trn_clk), + .A0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_VCC_2041), + .A1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_GND_2040), + .A2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_GND_2040), + .A3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_GND_2040) + ); + SRL16E com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_17_I_1 ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_i_65), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_d64_sw[40]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_17_N_6), + .CLK(NlwRenamedSig_OI_trn_clk), + .A0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_VCC_2041), + .A1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_GND_2040), + .A2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_GND_2040), + .A3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_GND_2040) + ); + SRL16E com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_18_I_1 ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_i_65), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_d16_sw[7]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_18_N_6), + .CLK(NlwRenamedSig_OI_trn_clk), + .A0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_VCC_2041), + .A1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_GND_2040), + .A2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_GND_2040), + .A3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_GND_2040) + ); + SRL16E com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_19_I_1 ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_i_65), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_d16_sw[6]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_19_N_6), + .CLK(NlwRenamedSig_OI_trn_clk), + .A0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_VCC_2041), + .A1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_GND_2040), + .A2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_GND_2040), + .A3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_GND_2040) + ); + SRL16E com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_20_I_1 ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_i_65), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_d16_sw[5]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_20_N_6), + .CLK(NlwRenamedSig_OI_trn_clk), + .A0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_VCC_2041), + .A1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_GND_2040), + .A2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_GND_2040), + .A3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_GND_2040) + ); + SRL16E com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_21_I_1 ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_i_65), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_d16_sw[4]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_21_N_6), + .CLK(NlwRenamedSig_OI_trn_clk), + .A0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_VCC_2041), + .A1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_GND_2040), + .A2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_GND_2040), + .A3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_GND_2040) + ); + SRL16E com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_22_I_1 ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_i_65), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_d16_sw[3]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_22_N_6), + .CLK(NlwRenamedSig_OI_trn_clk), + .A0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_VCC_2041), + .A1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_GND_2040), + .A2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_GND_2040), + .A3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_GND_2040) + ); + SRL16E com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_23_I_1 ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_i_65), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_d16_sw[2]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_23_N_6), + .CLK(NlwRenamedSig_OI_trn_clk), + .A0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_VCC_2041), + .A1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_GND_2040), + .A2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_GND_2040), + .A3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_GND_2040) + ); + SRL16E com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_24_I_1 ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_i_65), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_d16_sw[1]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_24_N_6), + .CLK(NlwRenamedSig_OI_trn_clk), + .A0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_VCC_2041), + .A1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_GND_2040), + .A2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_GND_2040), + .A3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_GND_2040) + ); + SRL16E com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_25_I_1 ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_i_65), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_d16_sw[0]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_25_N_6), + .CLK(NlwRenamedSig_OI_trn_clk), + .A0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_VCC_2041), + .A1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_GND_2040), + .A2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_GND_2040), + .A3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_GND_2040) + ); + SRL16E com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_26_I_1 ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_i_65), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_d16_sw[15]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_26_N_6), + .CLK(NlwRenamedSig_OI_trn_clk), + .A0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_VCC_2041), + .A1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_GND_2040), + .A2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_GND_2040), + .A3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_GND_2040) + ); + SRL16E com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_27_I_1 ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_i_65), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_d16_sw[14]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_27_N_6), + .CLK(NlwRenamedSig_OI_trn_clk), + .A0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_VCC_2041), + .A1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_GND_2040), + .A2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_GND_2040), + .A3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_GND_2040) + ); + SRL16E com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_28_I_1 ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_d32_sw[27]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_28_N_6), + .CLK(NlwRenamedSig_OI_trn_clk), + .A0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_VCC_2041), + .A1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_GND_2040), + .A2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_GND_2040), + .A3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_GND_2040) + ); + SRL16E com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_29_I_1 ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_d32_sw[26]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_29_N_6), + .CLK(NlwRenamedSig_OI_trn_clk), + .A0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_VCC_2041), + .A1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_GND_2040), + .A2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_GND_2040), + .A3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_GND_2040) + ); + SRL16E com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_30_I_1 ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_d32_sw[25]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_30_N_6), + .CLK(NlwRenamedSig_OI_trn_clk), + .A0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_VCC_2041), + .A1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_GND_2040), + .A2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_GND_2040), + .A3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_GND_2040) + ); + SRL16E com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_31_I_1 ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_d32_sw[24]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_31_N_6), + .CLK(NlwRenamedSig_OI_trn_clk), + .A0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_VCC_2041), + .A1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_GND_2040), + .A2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_GND_2040), + .A3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_GND_2040) + ); + SRL16E com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_32_I_1 ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_d64_sw[39]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_32_N_6), + .CLK(NlwRenamedSig_OI_trn_clk), + .A0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_VCC_2041), + .A1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_GND_2040), + .A2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_GND_2040), + .A3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_GND_2040) + ); + SRL16E com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_33_I_1 ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_d64_sw[38]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_33_N_6), + .CLK(NlwRenamedSig_OI_trn_clk), + .A0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_VCC_2041), + .A1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_GND_2040), + .A2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_GND_2040), + .A3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_GND_2040) + ); + SRL16E com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_34_I_1 ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_d64_sw[37]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_34_N_6), + .CLK(NlwRenamedSig_OI_trn_clk), + .A0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_VCC_2041), + .A1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_GND_2040), + .A2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_GND_2040), + .A3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_GND_2040) + ); + SRL16E com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_35_I_1 ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_d64_sw[36]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_35_N_6), + .CLK(NlwRenamedSig_OI_trn_clk), + .A0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_VCC_2041), + .A1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_GND_2040), + .A2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_GND_2040), + .A3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_GND_2040) + ); + SRL16E com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_36_I_1 ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_d64_sw[35]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_36_N_6), + .CLK(NlwRenamedSig_OI_trn_clk), + .A0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_VCC_2041), + .A1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_GND_2040), + .A2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_GND_2040), + .A3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_GND_2040) + ); + SRL16E com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_37_I_1 ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_d64_sw[34]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_37_N_6), + .CLK(NlwRenamedSig_OI_trn_clk), + .A0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_VCC_2041), + .A1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_GND_2040), + .A2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_GND_2040), + .A3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_GND_2040) + ); + SRL16E com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_38_I_1 ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_d64_sw[33]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_38_N_6), + .CLK(NlwRenamedSig_OI_trn_clk), + .A0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_VCC_2041), + .A1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_GND_2040), + .A2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_GND_2040), + .A3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_GND_2040) + ); + SRL16E com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_39_I_1 ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_d64_sw[32]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_39_N_6), + .CLK(NlwRenamedSig_OI_trn_clk), + .A0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_VCC_2041), + .A1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_GND_2040), + .A2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_GND_2040), + .A3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_GND_2040) + ); + SRL16E com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_40_I_1 ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_d64_sw[47]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_40_N_6), + .CLK(NlwRenamedSig_OI_trn_clk), + .A0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_VCC_2041), + .A1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_GND_2040), + .A2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_GND_2040), + .A3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_GND_2040) + ); + SRL16E com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_41_I_1 ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_d64_sw[46]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_41_N_6), + .CLK(NlwRenamedSig_OI_trn_clk), + .A0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_VCC_2041), + .A1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_GND_2040), + .A2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_GND_2040), + .A3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_GND_2040) + ); + SRL16E com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_42_I_1 ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_d64_sw[45]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_42_N_6), + .CLK(NlwRenamedSig_OI_trn_clk), + .A0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_VCC_2041), + .A1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_GND_2040), + .A2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_GND_2040), + .A3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_GND_2040) + ); + SRL16E com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_43_I_1 ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_d32_sw[10]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_43_N_6), + .CLK(NlwRenamedSig_OI_trn_clk), + .A0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_VCC_2041), + .A1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_GND_2040), + .A2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_GND_2040), + .A3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_GND_2040) + ); + SRL16E com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_44_I_1 ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_d32_sw[9]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_44_N_6), + .CLK(NlwRenamedSig_OI_trn_clk), + .A0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_VCC_2041), + .A1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_GND_2040), + .A2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_GND_2040), + .A3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_GND_2040) + ); + SRL16E com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_45_I_1 ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_d32_sw[8]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_45_N_6), + .CLK(NlwRenamedSig_OI_trn_clk), + .A0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_VCC_2041), + .A1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_GND_2040), + .A2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_GND_2040), + .A3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_GND_2040) + ); + SRL16E com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_46_I_1 ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_d32_sw[23]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_46_N_6), + .CLK(NlwRenamedSig_OI_trn_clk), + .A0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_VCC_2041), + .A1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_GND_2040), + .A2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_GND_2040), + .A3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_GND_2040) + ); + SRL16E com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_47_I_1 ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_d32_sw[22]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_47_N_6), + .CLK(NlwRenamedSig_OI_trn_clk), + .A0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_VCC_2041), + .A1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_GND_2040), + .A2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_GND_2040), + .A3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_GND_2040) + ); + SRL16E com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_48_I_1 ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_d32_sw[21]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_48_N_6), + .CLK(NlwRenamedSig_OI_trn_clk), + .A0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_VCC_2041), + .A1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_GND_2040), + .A2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_GND_2040), + .A3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_GND_2040) + ); + SRL16E com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_49_I_1 ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_d32_sw[20]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_49_N_6), + .CLK(NlwRenamedSig_OI_trn_clk), + .A0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_VCC_2041), + .A1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_GND_2040), + .A2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_GND_2040), + .A3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_GND_2040) + ); + SRL16E com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_50_I_1 ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_d32_sw[19]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_50_N_6), + .CLK(NlwRenamedSig_OI_trn_clk), + .A0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_VCC_2041), + .A1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_GND_2040), + .A2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_GND_2040), + .A3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_GND_2040) + ); + SRL16E com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_51_I_1 ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_d32_sw[18]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_51_N_6), + .CLK(NlwRenamedSig_OI_trn_clk), + .A0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_VCC_2041), + .A1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_GND_2040), + .A2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_GND_2040), + .A3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_GND_2040) + ); + SRL16E com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_52_I_1 ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_d32_sw[17]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_52_N_6), + .CLK(NlwRenamedSig_OI_trn_clk), + .A0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_VCC_2041), + .A1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_GND_2040), + .A2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_GND_2040), + .A3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_GND_2040) + ); + SRL16E com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_53_I_1 ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_d32_sw[16]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_53_N_6), + .CLK(NlwRenamedSig_OI_trn_clk), + .A0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_VCC_2041), + .A1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_GND_2040), + .A2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_GND_2040), + .A3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_GND_2040) + ); + SRL16E com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_54_I_1 ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_d32_sw[31]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_54_N_6), + .CLK(NlwRenamedSig_OI_trn_clk), + .A0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_VCC_2041), + .A1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_GND_2040), + .A2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_GND_2040), + .A3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_GND_2040) + ); + SRL16E com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_55_I_1 ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_d32_sw[30]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_55_N_6), + .CLK(NlwRenamedSig_OI_trn_clk), + .A0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_VCC_2041), + .A1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_GND_2040), + .A2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_GND_2040), + .A3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_GND_2040) + ); + SRL16E com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_56_I_1 ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_d32_sw[29]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_56_N_6), + .CLK(NlwRenamedSig_OI_trn_clk), + .A0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_VCC_2041), + .A1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_GND_2040), + .A2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_GND_2040), + .A3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_GND_2040) + ); + SRL16E com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_57_I_1 ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_d32_sw[28]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_57_N_6), + .CLK(NlwRenamedSig_OI_trn_clk), + .A0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_VCC_2041), + .A1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_GND_2040), + .A2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_GND_2040), + .A3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_GND_2040) + ); + SRL16E com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_58_I_1 ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_d32_sw[15]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_58_N_6), + .CLK(NlwRenamedSig_OI_trn_clk), + .A0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_VCC_2041), + .A1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_GND_2040), + .A2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_GND_2040), + .A3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_GND_2040) + ); + SRL16E com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_59_I_1 ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_d32_sw[14]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_59_N_6), + .CLK(NlwRenamedSig_OI_trn_clk), + .A0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_VCC_2041), + .A1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_GND_2040), + .A2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_GND_2040), + .A3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_GND_2040) + ); + SRL16E com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_60_I_1 ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_d32_sw[13]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_60_N_6), + .CLK(NlwRenamedSig_OI_trn_clk), + .A0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_VCC_2041), + .A1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_GND_2040), + .A2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_GND_2040), + .A3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_GND_2040) + ); + SRL16E com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_61_I_1 ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_d32_sw[12]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_61_N_6), + .CLK(NlwRenamedSig_OI_trn_clk), + .A0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_VCC_2041), + .A1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_GND_2040), + .A2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_GND_2040), + .A3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_GND_2040) + ); + SRL16E com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_62_I_1 ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_d32_sw[11]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_62_N_6), + .CLK(NlwRenamedSig_OI_trn_clk), + .A0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_VCC_2041), + .A1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_GND_2040), + .A2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_GND_2040), + .A3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_GND_2040) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_crcint_i_0_0_a2_1.INIT = 4'h8; + LUT2 com_llm_llm_tx_top_llmx08_tx_tlp_komp_crcint_i_0_0_a2_1 ( + .I0(com_llm_llm_tx_top_N_59251_1), + .I1(com_llm_llm_tx_top_tx_tlp_vld_l_n_i), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_1) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_crcint_i_0_0_a2_2.INIT = 4'h8; + LUT2 com_llm_llm_tx_top_llmx08_tx_tlp_komp_crcint_i_0_0_a2_2 ( + .I0(com_llm_llm_tx_top_N_59251_1), + .I1(com_llm_llm_tx_top_tx_tlp_vld_l_n_i), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_2) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_crcint_i_0_0_a2_3.INIT = 4'h8; + LUT2 com_llm_llm_tx_top_llmx08_tx_tlp_komp_crcint_i_0_0_a2_3 ( + .I0(com_llm_llm_tx_top_N_59251_1), + .I1(com_llm_llm_tx_top_tx_tlp_vld_l_n_i), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_3) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_crcint_i_0_0_a2_4.INIT = 4'h8; + LUT2 com_llm_llm_tx_top_llmx08_tx_tlp_komp_crcint_i_0_0_a2_4 ( + .I0(com_llm_llm_tx_top_N_59251_1), + .I1(com_llm_llm_tx_top_tx_tlp_vld_l_n_i), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_4) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_crcint_i_0_0_a2_5.INIT = 4'h8; + LUT2 com_llm_llm_tx_top_llmx08_tx_tlp_komp_crcint_i_0_0_a2_5 ( + .I0(com_llm_llm_tx_top_N_59251_1), + .I1(com_llm_llm_tx_top_tx_tlp_vld_l_n_i), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_5) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_crcint_i_0_0_a2.INIT = 8'h02; + LUT3 com_llm_llm_tx_top_llmx08_tx_tlp_komp_crcint_i_0_0_a2 ( + .I0(com_llm_llm_tx_top_tx_tlp_vld_l_n_i), + .I1(com_llm_llm_tx_top_tx_tlp_sof_n), + .I2(com_llm_llm_tx_top_arb_state[2]), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_d_i_o3_52_.INIT = 8'h04; + LUT3 com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_d_i_o3_52_ ( + .I0(com_llm_llm_tx_top_rem_pipe[4]), + .I1(G_39716_66), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_eof_n_pipe_DOUT[0]), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_d_i_o3[52]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_d_0_o3_8_.INIT = 8'h08; + LUT3 com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_d_0_o3_8_ ( + .I0(com_llm_llm_tx_top_tx_tlp_sof_pre_n), + .I1(G_39716_66), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_eof_n_pipe_DOUT[0]), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_N_55885_i) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_62_DOUT_0_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_62_N_6), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_220_) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_61_DOUT_0_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_61_N_6), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_219_) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_60_DOUT_0_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_60_N_6), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_218_) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_59_DOUT_0_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_59_N_6), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_217_) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_58_DOUT_0_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_58_N_6), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_216_) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_57_DOUT_0_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_57_N_6), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_235_) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_56_DOUT_0_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_56_N_6), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_234_) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_55_DOUT_0_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_55_N_6), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_233_) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_54_DOUT_0_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_54_N_6), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_232_) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_53_DOUT_0_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_53_N_6), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_231_) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_52_DOUT_0_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_52_N_6), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_230_) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_51_DOUT_0_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_51_N_6), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_229_) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_50_DOUT_0_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_50_N_6), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_228_) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_49_DOUT_0_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_49_N_6), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_227_) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_48_DOUT_0_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_48_N_6), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_226_) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_47_DOUT_0_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_47_N_6), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_225_) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_46_DOUT_0_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_46_N_6), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_224_) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_45_DOUT_0_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_45_N_6), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_223_) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_44_DOUT_0_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_44_N_6), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_222_) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_43_DOUT_0_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_43_N_6), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_221_) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_42_DOUT_0_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_42_N_6), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_250_) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_41_DOUT_0_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_41_N_6), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_249_) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_40_DOUT_0_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_40_N_6), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_248_) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_39_DOUT_0_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_39_N_6), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_247_) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_38_DOUT_0_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_38_N_6), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_246_) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_37_DOUT_0_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_37_N_6), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_245_) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_36_DOUT_0_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_36_N_6), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_244_) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_35_DOUT_0_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_35_N_6), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_243_) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_34_DOUT_0_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_34_N_6), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_242_) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_33_DOUT_0_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_33_N_6), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_241_) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_32_DOUT_0_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_32_N_6), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_240_) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_31_DOUT_0_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_31_N_6), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_239_) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_30_DOUT_0_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_30_N_6), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_238_) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_29_DOUT_0_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_29_N_6), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_237_) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_28_DOUT_0_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_28_N_6), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_236_) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_27_DOUT_0_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_i_65), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_27_N_6), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_265_) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_26_DOUT_0_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_i_65), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_26_N_6), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_264_) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_25_DOUT_0_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_i_65), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_25_N_6), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_263_) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_24_DOUT_0_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_i_65), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_24_N_6), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_262_) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_23_DOUT_0_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_i_65), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_23_N_6), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_261_) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_22_DOUT_0_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_i_65), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_22_N_6), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_260_) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_21_DOUT_0_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_i_65), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_21_N_6), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_259_) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_20_DOUT_0_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_i_65), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_20_N_6), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_258_) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_19_DOUT_0_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_i_65), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_19_N_6), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_257_) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_18_DOUT_0_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_i_65), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_18_N_6), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_256_) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_17_DOUT_0_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_i_65), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_17_N_6), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_255_) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_16_DOUT_0_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_i_65), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_16_N_6), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_254_) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_15_DOUT_0_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_i_65), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_15_N_6), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_253_) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_14_DOUT_0_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_i_65), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_14_N_6), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_252_) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_13_DOUT_0_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_i_65), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_13_N_6), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_251_) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_12_DOUT_0_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_i_65), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_12_N_6), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_279_) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_11_DOUT_0_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_i_65), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_11_N_6), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_278_) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_10_DOUT_0_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_i_65), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_10_N_6), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_277_) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_9_DOUT_0_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_i_65), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_9_N_6), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_276_) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_8_DOUT_0_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_i_65), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_8_N_6), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_275_) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_7_DOUT_0_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_i_65), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_7_N_6), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_274_) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_6_DOUT_0_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_i_65), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_6_N_6), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_273_) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_5_DOUT_0_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_i_65), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_5_tmp_d_array_0[0]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_272_) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_4_DOUT_0_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_i_65), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_4_N_6), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_271_) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_3_DOUT_0_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_i_65), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_3_N_6), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_270_) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_2_DOUT_0_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_i_65), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_2_N_6), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_269_) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_1_DOUT_0_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_i_65), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_1_N_6), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_268_) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_0_DOUT_0_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_i_65), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_0_N_6), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_267_) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_DOUT_0_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_i_65), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_N_6), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_266_) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_tsn_pipe_10_DOUT_0_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_i_65), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tsn_pipe_10_N_6), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tsn_pipe_47_) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_tsn_pipe_9_DOUT_0_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_i_65), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tsn_pipe_9_N_6), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tsn_pipe_46_) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_tsn_pipe_8_DOUT_0_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_i_65), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tsn_pipe_8_N_6), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tsn_pipe_45_) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_tsn_pipe_7_DOUT_0_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_i_65), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tsn_pipe_7_N_6), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tsn_pipe_44_) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_tsn_pipe_6_DOUT_0_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_i_65), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tsn_pipe_6_N_6), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tsn_pipe_43_) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_tsn_pipe_5_DOUT_0_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_i_65), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tsn_pipe_5_N_6), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tsn_pipe_42_) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_tsn_pipe_4_DOUT_0_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_i_65), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tsn_pipe_4_N_6), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tsn_pipe_41_) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_tsn_pipe_3_DOUT_0_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_i_65), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tsn_pipe_3_N_6), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tsn_pipe_40_) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_tsn_pipe_2_DOUT_0_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_i_65), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tsn_pipe_2_N_6), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tsn_pipe_39_) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_tsn_pipe_1_DOUT_0_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_i_65), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tsn_pipe_1_N_6), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tsn_pipe_38_) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_tsn_pipe_0_DOUT_0_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_i_65), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tsn_pipe_0_N_6), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tsn_pipe_37_) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_tsn_pipe_DOUT_0_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_i_65), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tsn_pipe_N_6), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tsn_pipe_36_) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_eof_n_pipe_DOUT_0_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_i_65), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_eof_n_pipe_N_6), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_eof_n_pipe_DOUT[0]) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_rem_pipe_DOUT_0_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_i_65), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_rem_pipe_tmp_d_array_0[0]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_rem_pipe_DOUT[0]) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_10_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_3), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_td_mux_i_m3_i_m3_0[10]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_10__2054) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_9_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_3), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_td_mux_i_m3_i_m3_0[9]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_9__2055) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_8_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_3), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_td_mux_i_m3_i_m3_0[8]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_8__2056) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_7_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_3), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_td_mux_i_m3_i_m3_i_m3_0[7]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_7__2057) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_6_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_3), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_td_mux_i_m3_i_m3_i_m3_0[6]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_6__2042) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_5_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_3), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_td_mux_i_m3_i_m3_i_m3_0[5]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_5__2043) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_4_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_3), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_td_mux_i_m3_i_m3_i_m3_0[4]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_4__2044) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_3_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_3), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_td_mux_i_m3_i_m3_i_m3_0[3]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_3__2045) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_2_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_3), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_td_mux_i_m3_i_m3_i_m3_0[2]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_2__2046) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_1_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_3), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_td_mux_i_m3_i_m3_i_m3_0[1]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_1__2047) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_0_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_3), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_td_mux_i_m3_i_m3_i_m3_0[0]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_0__2048) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_25_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_3), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_td_mux_i_m3_i_m3_0[25]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_d32_sw[14]) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_24_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_3), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_td_mux_i_m3_i_m3_0[24]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_d32_sw[15]) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_23_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_3), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_td_mux_i_m3_i_m3_0[23]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_d32_sw[0]) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_22_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_3), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_td_mux_i_m3_i_m3_0[22]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_d32_sw[1]) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_21_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_3), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_td_mux_i_m3_i_m3_0[21]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_d32_sw[2]) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_20_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_3), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_td_mux_i_m3_i_m3_0[20]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_d32_sw[3]) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_19_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_3), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_td_mux_i_m3_i_m3_0[19]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_d32_sw[4]) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_18_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_3), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_td_mux_i_m3_i_m3_0[18]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_d32_sw[5]) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_17_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_3), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_td_mux_i_m3_i_m3_0[17]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_d32_sw[6]) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_16_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_3), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_td_mux_i_m3_i_m3_0[16]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_d32_sw[7]) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_15_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_3), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_td_mux_i_m3_i_m3_0[15]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_15__2049) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_14_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_3), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_td_mux_i_m3_i_m3_0[14]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_14__2050) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_13_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_3), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_td_mux_i_m3_i_m3_0[13]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_13__2051) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_12_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_3), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_td_mux_i_m3_i_m3_0[12]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_12__2052) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_11_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_3), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_td_mux_i_m3_i_m3_0[11]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_11__2053) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_40_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_3), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_td_mux_i_m3_i_m3_0[40]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_d32_sw[31]) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_39_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_3), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_td_mux_i_m3_i_m3_0[39]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_d32_sw[16]) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_38_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_3), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_td_mux_i_m3_i_m3_0[38]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_d32_sw[17]) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_37_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_3), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_td_mux_i_m3_i_m3_0[37]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_d32_sw[18]) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_36_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_3), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_td_mux_i_m3_i_m3_0[36]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_d32_sw[19]) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_35_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_3), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_td_mux_i_m3_i_m3_0[35]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_d32_sw[20]) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_34_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_3), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_td_mux_i_m3_i_m3_0[34]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_d32_sw[21]) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_33_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_3), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_td_mux_i_m3_i_m3_0[33]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_d32_sw[22]) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_32_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_3), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_td_mux_i_m3_i_m3_0[32]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_d32_sw[23]) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_31_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_3), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_td_mux_i_m3_i_m3_0[31]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_d32_sw[8]) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_30_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_3), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_td_mux_i_m3_i_m3_0[30]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_d32_sw[9]) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_29_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_3), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_td_mux_i_m3_i_m3_0[29]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_d32_sw[10]) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_28_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_3), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_td_mux_i_m3_i_m3_0[28]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_d32_sw[11]) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_27_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_3), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_td_mux_i_m3_i_m3_0[27]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_d32_sw[12]) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_26_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_3), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_td_mux_i_m3_i_m3_0[26]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_d32_sw[13]) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_55_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_3), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_td_mux_i_m3_i_m3_0[55]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_d64_sw[32]) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_54_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_3), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_td_mux_i_m3_i_m3_0[54]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_d64_sw[33]) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_53_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_3), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_td_mux_i_m3_i_m3_0[53]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_d64_sw[34]) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_52_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_3), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_td_mux_i_m3_i_m3_0[52]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_d64_sw[35]) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_51_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_3), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_td_mux_i_m3_i_m3_0[51]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_d64_sw[36]) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_50_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_3), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_td_mux_i_m3_i_m3_0[50]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_d64_sw[37]) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_49_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_3), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_td_mux_i_m3_i_m3_0[49]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_d64_sw[38]) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_48_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_3), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_td_mux_i_m3_i_m3_0[48]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_d64_sw[39]) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_47_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_3), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_td_mux_i_m3_i_m3_0[47]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_d32_sw[24]) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_46_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_3), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_td_mux_i_m3_i_m3_0[46]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_d32_sw[25]) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_45_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_3), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_td_mux_i_m3_i_m3_0[45]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_d32_sw[26]) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_44_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_3), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_td_mux_i_m3_i_m3_0[44]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_d32_sw[27]) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_43_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_3), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_td_mux_i_m3_i_m3_0[43]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_d32_sw[28]) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_42_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_3), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_td_mux_i_m3_i_m3_0[42]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_d32_sw[29]) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_41_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_3), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_td_mux_i_m3_i_m3_0[41]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_d32_sw[30]) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_70_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_3), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_6__2042), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_d16_sw[1]) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_69_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_3), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_5__2043), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_d16_sw[2]) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_68_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_3), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_4__2044), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_d16_sw[3]) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_67_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_3), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_3__2045), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_d16_sw[4]) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_66_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_3), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_2__2046), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_d16_sw[5]) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_65_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_3), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_1__2047), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_d16_sw[6]) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_64_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_3), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_0__2048), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_d16_sw[7]) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_63_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_3), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_td_mux_i_m3_i_m3_0[63]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_d64_sw[40]) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_62_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_3), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_td_mux_i_m3_i_m3_0[62]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_d64_sw[41]) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_61_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_3), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_td_mux_i_m3_i_m3_0[61]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_d64_sw[42]) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_60_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_3), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_td_mux_i_m3_i_m3_0[60]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_d64_sw[43]) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_59_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_3), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_td_mux_i_m3_i_m3_0[59]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_d64_sw[44]) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_58_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_3), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_td_mux_i_m3_i_m3_0[58]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_d64_sw[45]) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_57_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_3), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_td_mux_i_m3_i_m3_0[57]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_d64_sw[46]) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_56_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_3), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_td_mux_i_m3_i_m3_0[56]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_d64_sw[47]) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_79_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_3), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_15__2049), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_d16_sw[8]) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_78_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_3), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_14__2050), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_d16_sw[9]) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_77_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_3), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_13__2051), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_d16_sw[10]) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_76_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_3), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_12__2052), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_d16_sw[11]) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_75_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_3), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_11__2053), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_d16_sw[12]) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_74_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_3), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_10__2054), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_d16_sw[13]) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_73_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_3), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_9__2055), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_d16_sw[14]) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_72_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_3), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_8__2056), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_d16_sw[15]) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_71_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_3), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_data_pipe_7__2057), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_d16_sw[0]) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_bat_td_63_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_bat_td3), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_lnk_td[63]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_bat_td[63]) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_bat_td_62_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_bat_td3), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_lnk_td[62]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_bat_td[62]) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_bat_td_61_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_bat_td3), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_lnk_td[61]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_bat_td[61]) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_bat_td_60_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_bat_td3), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_lnk_td[60]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_bat_td[60]) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_bat_td_59_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_bat_td3), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_lnk_td[59]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_bat_td[59]) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_bat_td_58_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_bat_td3), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_lnk_td[58]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_bat_td[58]) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_bat_td_57_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_bat_td3), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_lnk_td[57]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_bat_td[57]) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_bat_td_56_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_bat_td3), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_lnk_td[56]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_bat_td[56]) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_bat_td_55_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_bat_td3), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_lnk_td[55]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_bat_td[55]) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_bat_td_54_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_bat_td3), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_lnk_td[54]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_bat_td[54]) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_bat_td_53_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_bat_td3), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_lnk_td[53]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_bat_td[53]) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_bat_td_52_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_bat_td3), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_lnk_td[52]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_bat_td[52]) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_bat_td_51_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_bat_td3), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_lnk_td[51]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_bat_td[51]) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_bat_td_50_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_bat_td3), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_lnk_td[50]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_bat_td[50]) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_bat_td_49_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_bat_td3), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_lnk_td[49]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_bat_td[49]) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_bat_td_48_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_bat_td3), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_lnk_td[48]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_bat_td[48]) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_bat_td_47_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_bat_td3), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_lnk_td[47]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_bat_td[47]) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_bat_td_46_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_bat_td3), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_lnk_td[46]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_bat_td[46]) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_bat_td_45_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_bat_td3), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_lnk_td[45]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_bat_td[45]) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_bat_td_44_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_bat_td3), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_lnk_td[44]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_bat_td[44]) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_bat_td_43_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_bat_td3), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_lnk_td[43]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_bat_td[43]) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_bat_td_42_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_bat_td3), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_lnk_td[42]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_bat_td[42]) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_bat_td_41_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_bat_td3), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_lnk_td[41]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_bat_td[41]) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_bat_td_40_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_bat_td3), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_lnk_td[40]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_bat_td[40]) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_bat_td_39_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_bat_td3), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_lnk_td[39]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_bat_td[39]) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_bat_td_38_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_bat_td3), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_lnk_td[38]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_bat_td[38]) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_bat_td_37_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_bat_td3), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_lnk_td[37]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_bat_td[37]) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_bat_td_36_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_bat_td3), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_lnk_td[36]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_bat_td[36]) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_bat_td_35_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_bat_td3), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_lnk_td[35]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_bat_td[35]) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_bat_td_34_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_bat_td3), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_lnk_td[34]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_bat_td[34]) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_bat_td_33_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_bat_td3), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_lnk_td[33]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_bat_td[33]) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_bat_td_32_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_bat_td3), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_lnk_td[32]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_bat_td[32]) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_bat_td_31_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_bat_td3), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_lnk_td[31]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_bat_td[31]) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_bat_td_30_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_bat_td3), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_lnk_td[30]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_bat_td[30]) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_bat_td_29_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_bat_td3), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_lnk_td[29]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_bat_td[29]) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_bat_td_28_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_bat_td3), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_lnk_td[28]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_bat_td[28]) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_bat_td_27_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_bat_td3), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_lnk_td[27]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_bat_td[27]) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_bat_td_26_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_bat_td3), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_lnk_td[26]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_bat_td[26]) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_bat_td_25_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_bat_td3), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_lnk_td[25]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_bat_td[25]) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_bat_td_24_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_bat_td3), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_lnk_td[24]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_bat_td[24]) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_bat_td_23_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_bat_td3), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_lnk_td[23]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_bat_td[23]) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_bat_td_22_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_bat_td3), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_lnk_td[22]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_bat_td[22]) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_bat_td_21_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_bat_td3), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_lnk_td[21]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_bat_td[21]) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_bat_td_20_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_bat_td3), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_lnk_td[20]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_bat_td[20]) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_bat_td_19_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_bat_td3), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_lnk_td[19]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_bat_td[19]) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_bat_td_18_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_bat_td3), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_lnk_td[18]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_bat_td[18]) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_bat_td_17_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_bat_td3), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_lnk_td[17]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_bat_td[17]) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_bat_td_16_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_bat_td3), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_lnk_td[16]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_bat_td[16]) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_bat_td_15_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_bat_td3), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_lnk_td[15]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_bat_td[15]) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_bat_td_14_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_bat_td3), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_lnk_td[14]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_bat_td[14]) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_bat_td_13_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_bat_td3), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_lnk_td[13]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_bat_td[13]) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_bat_td_12_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_bat_td3), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_lnk_td[12]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_bat_td[12]) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_bat_td_11_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_bat_td3), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_lnk_td[11]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_bat_td[11]) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_bat_td_10_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_bat_td3), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_lnk_td[10]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_bat_td[10]) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_bat_td_9_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_bat_td3), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_lnk_td[9]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_bat_td[9]) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_bat_td_8_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_bat_td3), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_lnk_td[8]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_bat_td[8]) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_bat_td_7_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_bat_td3), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_lnk_td[7]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_bat_td[7]) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_bat_td_6_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_bat_td3), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_lnk_td[6]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_bat_td[6]) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_bat_td_5_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_bat_td3), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_lnk_td[5]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_bat_td[5]) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_bat_td_4_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_bat_td3), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_lnk_td[4]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_bat_td[4]) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_bat_td_3_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_bat_td3), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_lnk_td[3]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_bat_td[3]) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_bat_td_2_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_bat_td3), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_lnk_td[2]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_bat_td[2]) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_bat_td_1_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_bat_td3), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_lnk_td[1]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_bat_td[1]) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_bat_td_0_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_bat_td3), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_lnk_td[0]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_bat_td[0]) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_tsn_pipe_11_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_0), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_lnk_ttrans_seq[11]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tsn_pipe_11__2058) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_tsn_pipe_10_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_0), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_lnk_ttrans_seq[10]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tsn_pipe_10__2059) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_tsn_pipe_9_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_0), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_lnk_ttrans_seq[9]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tsn_pipe_9__2060) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_tsn_pipe_8_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_0), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_lnk_ttrans_seq[8]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tsn_pipe_8__2061) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_tsn_pipe_7_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_0), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_lnk_ttrans_seq[7]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tsn_pipe_7__2062) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_tsn_pipe_6_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_0), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_lnk_ttrans_seq[6]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tsn_pipe_6__2063) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_tsn_pipe_5_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_0), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_lnk_ttrans_seq[5]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tsn_pipe_5__2064) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_tsn_pipe_4_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_0), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_lnk_ttrans_seq[4]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tsn_pipe_4__2065) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_tsn_pipe_3_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_0), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_lnk_ttrans_seq[3]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tsn_pipe_3__2066) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_tsn_pipe_2_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_0), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_lnk_ttrans_seq[2]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tsn_pipe_2__2067) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_tsn_pipe_1_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_0), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_lnk_ttrans_seq[1]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tsn_pipe_1__2068) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_tsn_pipe_0_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_0), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_lnk_ttrans_seq[0]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tsn_pipe_0__2069) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_crc_23_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_0), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_sw_early_crc_i[23]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_crc[23]) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_crc_22_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_0), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_sw_early_crc_i[22]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_crc[22]) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_crc_21_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_0), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_sw_early_crc_i[21]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_crc[21]) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_crc_20_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_0), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_sw_early_crc_i[20]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_crc[20]) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_crc_19_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_0), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_sw_early_crc_i[19]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_crc[19]) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_crc_18_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_0), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_sw_early_crc_i[18]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_crc[18]) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_crc_17_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_0), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_sw_early_crc_i[17]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_crc[17]) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_crc_16_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_0), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_sw_early_crc_i[16]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_crc[16]) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_crc_15_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_0), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_sw_early_crc_i[15]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_crc[15]) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_crc_14_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_0), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_sw_early_crc_i[14]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_crc[14]) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_crc_13_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_0), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_sw_early_crc_i[13]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_crc[13]) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_crc_12_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_0), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_sw_early_crc_i[12]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_crc[12]) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_crc_11_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_0), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_sw_early_crc_i[11]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_crc[11]) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_crc_10_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_0), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_sw_early_crc_i[10]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_crc[10]) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_crc_9_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_0), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_sw_early_crc_i[9]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_crc[9]) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_crc_8_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_0), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_sw_early_crc_i[8]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_crc[8]) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_crc_7_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_0), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_sw_early_crc_i[7]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_crc[7]) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_crc_6_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_0), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_sw_early_crc_i[6]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_crc[6]) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_crc_5_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_0), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_sw_early_crc_i[5]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_crc[5]) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_crc_4_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_0), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_sw_early_crc_i[4]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_crc[4]) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_crc_3_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_0), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_sw_early_crc_i[3]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_crc[3]) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_crc_2_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_0), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_sw_early_crc_i[2]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_crc[2]) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_crc_1_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_0), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_sw_early_crc_i[1]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_crc[1]) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_crc_0_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_0), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_sw_early_crc_i[0]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_crc[0]) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_63_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_0), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_N_25962_i), + .Q(com_llm_llm_tx_top_tx_tlp_td[63]) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_62_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_0), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_N_25960_i), + .Q(com_llm_llm_tx_top_tx_tlp_td[62]) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_61_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_0), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_N_25958_i), + .Q(com_llm_llm_tx_top_tx_tlp_td[61]) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_60_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_0), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_N_25956_i), + .Q(com_llm_llm_tx_top_tx_tlp_td[60]) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_59_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_0), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_N_25954_i), + .Q(com_llm_llm_tx_top_tx_tlp_td[59]) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_58_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_0), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_N_25952_i), + .Q(com_llm_llm_tx_top_tx_tlp_td[58]) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_57_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_0), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_N_51730_i), + .Q(com_llm_llm_tx_top_tx_tlp_td[57]) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_56_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_0), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_N_25950_i), + .Q(com_llm_llm_tx_top_tx_tlp_td[56]) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_55_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_0), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_N_25948_i), + .Q(com_llm_llm_tx_top_tx_tlp_td[55]) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_54_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_0), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_N_51728_i), + .Q(com_llm_llm_tx_top_tx_tlp_td[54]) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_53_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_0), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_N_51726_i), + .Q(com_llm_llm_tx_top_tx_tlp_td[53]) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_52_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_0), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_N_51724_i), + .Q(com_llm_llm_tx_top_tx_tlp_td[52]) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_51_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_0), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_N_25946_i), + .Q(com_llm_llm_tx_top_tx_tlp_td[51]) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_50_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_0), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_N_25944_i), + .Q(com_llm_llm_tx_top_tx_tlp_td[50]) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_49_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_0), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_N_25942_i), + .Q(com_llm_llm_tx_top_tx_tlp_td[49]) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_48_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_0), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_N_25940_i), + .Q(com_llm_llm_tx_top_tx_tlp_td[48]) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_47_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_0), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_N_25938_i), + .Q(com_llm_llm_tx_top_tx_tlp_td[47]) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_46_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_0), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_N_25936_i), + .Q(com_llm_llm_tx_top_tx_tlp_td[46]) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_45_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_0), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_N_25934_i), + .Q(com_llm_llm_tx_top_tx_tlp_td[45]) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_44_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_0), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_N_25932_i), + .Q(com_llm_llm_tx_top_tx_tlp_td[44]) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_43_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_0), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_N_25930_i), + .Q(com_llm_llm_tx_top_tx_tlp_td[43]) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_42_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_0), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_N_25928_i), + .Q(com_llm_llm_tx_top_tx_tlp_td[42]) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_41_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_0), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_N_25926_i), + .Q(com_llm_llm_tx_top_tx_tlp_td[41]) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_40_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_0), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_N_25924_i), + .Q(com_llm_llm_tx_top_tx_tlp_td[40]) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_39_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_0), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_N_86895_i_2070), + .Q(com_llm_llm_tx_top_tx_tlp_td[39]) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_38_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_0), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_N_86894_i_2071), + .Q(com_llm_llm_tx_top_tx_tlp_td[38]) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_37_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_0), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_N_86893_i_2072), + .Q(com_llm_llm_tx_top_tx_tlp_td[37]) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_36_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_0), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_N_86892_i_2073), + .Q(com_llm_llm_tx_top_tx_tlp_td[36]) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_35_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_0), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_N_86891_i_2074), + .Q(com_llm_llm_tx_top_tx_tlp_td[35]) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_34_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_0), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_N_86890_i_2075), + .Q(com_llm_llm_tx_top_tx_tlp_td[34]) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_33_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_0), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_N_86889_i_2076), + .Q(com_llm_llm_tx_top_tx_tlp_td[33]) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_32_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_0), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_N_86888_i_2077), + .Q(com_llm_llm_tx_top_tx_tlp_td[32]) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_31_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_0), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_N_86887_i_2078), + .Q(com_llm_llm_tx_top_tx_tlp_td[31]) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_30_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_0), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_N_86886_i_2079), + .Q(com_llm_llm_tx_top_tx_tlp_td[30]) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_29_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_0), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_N_86885_i_2080), + .Q(com_llm_llm_tx_top_tx_tlp_td[29]) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_28_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_0), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_N_86884_i_2081), + .Q(com_llm_llm_tx_top_tx_tlp_td[28]) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_27_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_0), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_N_86883_i_2082), + .Q(com_llm_llm_tx_top_tx_tlp_td[27]) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_26_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_0), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_N_86882_i_2083), + .Q(com_llm_llm_tx_top_tx_tlp_td[26]) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_25_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_0), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_N_86881_i_2084), + .Q(com_llm_llm_tx_top_tx_tlp_td[25]) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_24_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_0), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_N_86880_i_2085), + .Q(com_llm_llm_tx_top_tx_tlp_td[24]) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_23_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_0), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_N_86879_i_2086), + .Q(com_llm_llm_tx_top_tx_tlp_td[23]) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_22_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_0), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_N_86878_i_2087), + .Q(com_llm_llm_tx_top_tx_tlp_td[22]) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_21_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_N_86877_i_2088), + .Q(com_llm_llm_tx_top_tx_tlp_td[21]) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_20_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_N_86876_i_2089), + .Q(com_llm_llm_tx_top_tx_tlp_td[20]) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_19_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_N_86875_i_2090), + .Q(com_llm_llm_tx_top_tx_tlp_td[19]) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_18_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_N_86874_i_2091), + .Q(com_llm_llm_tx_top_tx_tlp_td[18]) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_17_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_N_86873_i_2092), + .Q(com_llm_llm_tx_top_tx_tlp_td[17]) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_16_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_N_86872_i_2093), + .Q(com_llm_llm_tx_top_tx_tlp_td[16]) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_15_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_N_86871_i_2094), + .Q(com_llm_llm_tx_top_tx_tlp_td[15]) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_14_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_N_86870_i_2095), + .Q(com_llm_llm_tx_top_tx_tlp_td[14]) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_13_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_N_86869_i_2096), + .Q(com_llm_llm_tx_top_tx_tlp_td[13]) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_12_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_N_86868_i_2097), + .Q(com_llm_llm_tx_top_tx_tlp_td[12]) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_11_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_N_86867_i_2098), + .Q(com_llm_llm_tx_top_tx_tlp_td[11]) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_10_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_N_86866_i_2099), + .Q(com_llm_llm_tx_top_tx_tlp_td[10]) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_9_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_N_86865_i_2100), + .Q(com_llm_llm_tx_top_tx_tlp_td[9]) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_8_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_N_86864_i_2101), + .Q(com_llm_llm_tx_top_tx_tlp_td[8]) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_7_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_N_86863_i_2102), + .Q(com_llm_llm_tx_top_tx_tlp_td[7]) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_6_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_N_86862_i_2103), + .Q(com_llm_llm_tx_top_tx_tlp_td[6]) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_5_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_N_86861_i_2104), + .Q(com_llm_llm_tx_top_tx_tlp_td[5]) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_4_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_N_86860_i_2105), + .Q(com_llm_llm_tx_top_tx_tlp_td[4]) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_3_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_N_86859_i_2106), + .Q(com_llm_llm_tx_top_tx_tlp_td[3]) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_2_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_N_86858_i_2107), + .Q(com_llm_llm_tx_top_tx_tlp_td[2]) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_1_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_N_86857_i_2108), + .Q(com_llm_llm_tx_top_tx_tlp_td[1]) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_tlp_td_0_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_N_86856_i_2109), + .Q(com_llm_llm_tx_top_tx_tlp_td[0]) + ); + INV com_llm_llm_tx_top_llmx08_tx_tlp_komp_lnk_tdst_rdy_n_i ( + .I(com_lnk_tdst_rdy_n), + .O(com_lnk_tdst_rdy_n_i) + ); + INV com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_i ( + .I(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_i_65) + ); + FDSE com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crc32_d64_feedback_0_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_1), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_26538_i_2199), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crc32_d64_feedback[0]), + .S(plm_link_up_i) + ); + FDSE com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crc32_d64_feedback_1_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_1), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_26537_i_2198), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crc32_d64_feedback[1]), + .S(plm_link_up_i) + ); + FDSE com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crc32_d64_feedback_2_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_1), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_26536_i_2197), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crc32_d64_feedback[2]), + .S(plm_link_up_i) + ); + FDSE com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crc32_d64_feedback_3_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_1), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_26535_i_2196), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crc32_d64_feedback[3]), + .S(plm_link_up_i) + ); + FDSE com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crc32_d64_feedback_4_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_1), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_26534_i_2195), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crc32_d64_feedback[4]), + .S(plm_link_up_i) + ); + FDSE com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crc32_d64_feedback_5_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_1), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_26533_i_2194), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crc32_d64_feedback[5]), + .S(plm_link_up_i) + ); + FDSE com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crc32_d64_feedback_6_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_1), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_26564_i_2193), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crc32_d64_feedback[6]), + .S(plm_link_up_i) + ); + FDSE com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crc32_d64_feedback_7_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_1), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_26563_i_2192), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crc32_d64_feedback[7]), + .S(plm_link_up_i) + ); + FDSE com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crc32_d64_feedback_8_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_1), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_26562_i_2191), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crc32_d64_feedback[8]), + .S(plm_link_up_i) + ); + FDSE com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crc32_d64_feedback_9_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_1), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_26561_i_2190), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crc32_d64_feedback[9]), + .S(plm_link_up_i) + ); + FDSE com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crc32_d64_feedback_10_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_1), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_26560_i_2189), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crc32_d64_feedback[10]), + .S(plm_link_up_i) + ); + FDSE com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crc32_d64_feedback_11_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_1), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_26559_i_2188), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crc32_d64_feedback[11]), + .S(plm_link_up_i) + ); + FDSE com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crc32_d64_feedback_12_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_1), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_26558_i_2187), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crc32_d64_feedback[12]), + .S(plm_link_up_i) + ); + FDSE com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crc32_d64_feedback_13_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_1), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_26557_i_2186), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crc32_d64_feedback[13]), + .S(plm_link_up_i) + ); + FDSE com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crc32_d64_feedback_14_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_1), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_26556_i_2185), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crc32_d64_feedback[14]), + .S(plm_link_up_i) + ); + FDSE com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crc32_d64_feedback_15_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_1), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_26555_i_2184), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crc32_d64_feedback[15]), + .S(plm_link_up_i) + ); + FDSE com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crc32_d64_feedback_16_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_1), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_26554_i_2183), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crc32_d64_feedback[16]), + .S(plm_link_up_i) + ); + FDSE com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crc32_d64_feedback_17_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_1), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_26553_i_2182), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crc32_d64_feedback[17]), + .S(plm_link_up_i) + ); + FDSE com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crc32_d64_feedback_18_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_1), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_26552_i_2181), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crc32_d64_feedback[18]), + .S(plm_link_up_i) + ); + FDSE com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crc32_d64_feedback_19_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_1), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_26532_i_2180), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crc32_d64_feedback[19]), + .S(plm_link_up_i) + ); + FDSE com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crc32_d64_feedback_20_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_1), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_26531_i_2179), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crc32_d64_feedback[20]), + .S(plm_link_up_i) + ); + FDSE com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crc32_d64_feedback_21_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_1), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_26530_i_2178), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crc32_d64_feedback[21]), + .S(plm_link_up_i) + ); + FDSE com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crc32_d64_feedback_22_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_1), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_26529_i_2177), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crc32_d64_feedback[22]), + .S(plm_link_up_i) + ); + FDSE com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crc32_d64_feedback_23_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_1), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_26528_i_2176), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crc32_d64_feedback[23]), + .S(plm_link_up_i) + ); + FDSE com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crc32_d64_feedback_24_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_1), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_26527_i_2175), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crc32_d64_feedback[24]), + .S(plm_link_up_i) + ); + FDSE com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crc32_d64_feedback_25_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_1), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_26526_i_2174), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crc32_d64_feedback[25]), + .S(plm_link_up_i) + ); + FDSE com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crc32_d64_feedback_26_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_1), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_26525_i_2173), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crc32_d64_feedback[26]), + .S(plm_link_up_i) + ); + FDSE com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crc32_d64_feedback_27_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_1), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_26524_i_2172), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crc32_d64_feedback[27]), + .S(plm_link_up_i) + ); + FDSE com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crc32_d64_feedback_28_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_1), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_26523_i_2171), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crc32_d64_feedback[28]), + .S(plm_link_up_i) + ); + FDSE com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crc32_d64_feedback_29_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_1), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_26522_i_2170), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crc32_d64_feedback[29]), + .S(plm_link_up_i) + ); + FDSE com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crc32_d64_feedback_30_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_2), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_26521_i_2169), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crc32_d64_feedback[30]), + .S(plm_link_up_i) + ); + FDSE com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crc32_d64_feedback_31_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_2), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_26520_i_2168), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crc32_d64_feedback[31]), + .S(plm_link_up_i) + ); + FDSE com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_0_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_2), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4[0]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_sw_early_crc[7]), + .S(plm_link_up_i) + ); + FDSE com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_1_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_2), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4[1]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_sw_early_crc[6]), + .S(plm_link_up_i) + ); + FDSE com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_2_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_2), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4[2]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_sw_early_crc[5]), + .S(plm_link_up_i) + ); + FDSE com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_3_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_2), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4[3]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_sw_early_crc[4]), + .S(plm_link_up_i) + ); + FDSE com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_2), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4[4]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_sw_early_crc[3]), + .S(plm_link_up_i) + ); + FDSE com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_5_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_2), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4[5]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_sw_early_crc[2]), + .S(plm_link_up_i) + ); + FDSE com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_6_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_2), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4[6]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_sw_early_crc[1]), + .S(plm_link_up_i) + ); + FDSE com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_7_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_2), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4[7]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_sw_early_crc[0]), + .S(plm_link_up_i) + ); + FDSE com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_8_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_2), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4[8]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_sw_early_crc[15]), + .S(plm_link_up_i) + ); + FDSE com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_9_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_2), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4[9]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_sw_early_crc[14]), + .S(plm_link_up_i) + ); + FDSE com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_10_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_2), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4[10]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_sw_early_crc[13]), + .S(plm_link_up_i) + ); + FDSE com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_11_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_2), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4[11]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_sw_early_crc[12]), + .S(plm_link_up_i) + ); + FDSE com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_12_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_2), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4[12]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_sw_early_crc[11]), + .S(plm_link_up_i) + ); + FDSE com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_13_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_2), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4[13]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_sw_early_crc[10]), + .S(plm_link_up_i) + ); + FDSE com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_14_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_2), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4[14]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_sw_early_crc[9]), + .S(plm_link_up_i) + ); + FDSE com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_15_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_2), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4[15]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_sw_early_crc[8]), + .S(plm_link_up_i) + ); + FDSE com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_16_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_2), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4[16]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_sw_early_crc[23]), + .S(plm_link_up_i) + ); + FDSE com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_17_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_2), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4[17]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_sw_early_crc[22]), + .S(plm_link_up_i) + ); + FDSE com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_18_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_2), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4[18]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_sw_early_crc[21]), + .S(plm_link_up_i) + ); + FDSE com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_19_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_2), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4[19]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_sw_early_crc[20]), + .S(plm_link_up_i) + ); + FDSE com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_20_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_2), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4[20]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_sw_early_crc[19]), + .S(plm_link_up_i) + ); + FDSE com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_21_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_2), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4[21]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_sw_early_crc[18]), + .S(plm_link_up_i) + ); + FDSE com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_22_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_2), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4[22]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_sw_early_crc[17]), + .S(plm_link_up_i) + ); + FDSE com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_23_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_2), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4[23]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_sw_early_crc[16]), + .S(plm_link_up_i) + ); + FDSE com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_24_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_2), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4[24]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_sw_early_crc[31]), + .S(plm_link_up_i) + ); + FDSE com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_25_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_2), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4[25]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_sw_early_crc[30]), + .S(plm_link_up_i) + ); + FDSE com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_26_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_2), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4[26]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_sw_early_crc[29]), + .S(plm_link_up_i) + ); + FDSE com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_27_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_2), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4[27]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_sw_early_crc[28]), + .S(plm_link_up_i) + ); + FDSE com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_28_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_2), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4[28]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_sw_early_crc[27]), + .S(plm_link_up_i) + ); + FDSE com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_29_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_2), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4[29]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_sw_early_crc[26]), + .S(plm_link_up_i) + ); + FDSE com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_30_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_2), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4[30]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_sw_early_crc[25]), + .S(plm_link_up_i) + ); + FDSE com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_31_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_2), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4[31]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_sw_early_crc[24]), + .S(plm_link_up_i) + ); + FDRE com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crcdatawidth_qq_2_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_2), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crcdatawidth_q[2]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crcdatawidth_qq[2]), + .R(plm_link_up_i) + ); + FDRE com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crcint_qq ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_2), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mgt_tx_crcint), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crcint_qq_2200), + .R(plm_link_up_i) + ); + FDSE com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q_0_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_2), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_new_c32_d64[0]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[0]), + .S(plm_link_up_i) + ); + FDSE com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q_1_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_2), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_new_c32_d64[1]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[1]), + .S(plm_link_up_i) + ); + FDSE com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q_2_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_2), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_new_c32_d64[2]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[2]), + .S(plm_link_up_i) + ); + FDSE com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q_3_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_2), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_new_c32_d64[3]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[3]), + .S(plm_link_up_i) + ); + FDSE com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q_4_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_2), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_new_c32_d64[4]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[4]), + .S(plm_link_up_i) + ); + FDSE com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q_5_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_2), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_new_c32_d64[5]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[5]), + .S(plm_link_up_i) + ); + FDSE com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q_6_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_2), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_new_c32_d64[6]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[6]), + .S(plm_link_up_i) + ); + FDSE com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q_7_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_2), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_new_c32_d64[7]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[7]), + .S(plm_link_up_i) + ); + FDSE com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q_8_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_2), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_new_c32_d64[8]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[8]), + .S(plm_link_up_i) + ); + FDSE com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q_9_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_2), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_new_c32_d64[9]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[9]), + .S(plm_link_up_i) + ); + FDSE com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q_10_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_2), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_new_c32_d64[10]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[10]), + .S(plm_link_up_i) + ); + FDSE com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q_11_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_2), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_new_c32_d64[11]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[11]), + .S(plm_link_up_i) + ); + FDSE com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q_12_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_2), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_new_c32_d64[12]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[12]), + .S(plm_link_up_i) + ); + FDSE com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q_13_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_2), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_new_c32_d64[13]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[13]), + .S(plm_link_up_i) + ); + FDSE com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q_14_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_2), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_new_c32_d64[14]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[14]), + .S(plm_link_up_i) + ); + FDSE com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q_15_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_2), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_new_c32_d64[15]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[15]), + .S(plm_link_up_i) + ); + FDSE com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q_16_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_2), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_new_c32_d64[16]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[16]), + .S(plm_link_up_i) + ); + FDSE com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q_17_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_2), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_new_c32_d64[17]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[17]), + .S(plm_link_up_i) + ); + FDSE com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q_18_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_2), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_new_c32_d64[18]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[18]), + .S(plm_link_up_i) + ); + FDSE com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q_19_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_2), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_new_c32_d64[19]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[19]), + .S(plm_link_up_i) + ); + FDSE com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q_20_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_2), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_new_c32_d64[20]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[20]), + .S(plm_link_up_i) + ); + FDSE com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q_21_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_2), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_new_c32_d64[21]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[21]), + .S(plm_link_up_i) + ); + FDSE com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q_22_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_2), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_new_c32_d64[22]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[22]), + .S(plm_link_up_i) + ); + FDSE com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q_23_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_2), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_new_c32_d64[23]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[23]), + .S(plm_link_up_i) + ); + FDSE com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q_24_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_2), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_new_c32_d64[24]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[24]), + .S(plm_link_up_i) + ); + FDSE com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q_25_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_2), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_new_c32_d64[25]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[25]), + .S(plm_link_up_i) + ); + FDSE com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q_26_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_2), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_new_c32_d64[26]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[26]), + .S(plm_link_up_i) + ); + FDSE com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q_27_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_2), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_new_c32_d64[27]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[27]), + .S(plm_link_up_i) + ); + FDSE com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q_28_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_2), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_new_c32_d64[28]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[28]), + .S(plm_link_up_i) + ); + FDSE com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q_29_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_2), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_new_c32_d64[29]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[29]), + .S(plm_link_up_i) + ); + FDSE com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q_30_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_2), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_new_c32_d64[30]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[30]), + .S(plm_link_up_i) + ); + FDSE com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q_31_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_2), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_new_c32_d64[31]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[31]), + .S(plm_link_up_i) + ); + FDRE com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crcint_q ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_2), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_N_16899_i), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mgt_tx_crcint), + .R(plm_link_up_i) + ); + FDRE com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crcdatawidth_q_2_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_2), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_eof_n_pipe_6114[1]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crcdatawidth_q[2]), + .R(plm_link_up_i) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_i_o3_0_56_.INIT = 4'h8; + LUT2 com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_i_o3_0_56_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_eof_n_pipe_6114[1]), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_rem_pipe_6115[0]), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_55887_i) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_i_a3_0_.INIT = 4'h2; + LUT2 com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_i_a3_0_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_eof_n_pipe_6114[1]), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_rem_pipe_6115[0]), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_61310) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_i_a2_16_.INIT = 4'h1; + LUT2 com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_i_a2_16_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_eof_n_pipe_6114[1]), + .I1(com_reset_i_q), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_58164) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_i_m3_0_47_.INIT = 8'hB8; + LUT3 com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_i_m3_0_47_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_d16_sw[15]), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_sof_n_pipe[0]), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tsn_pipe_8__2061), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_56429) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_i_m3_0_46_.INIT = 8'hB8; + LUT3 com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_i_m3_0_46_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_d16_sw[14]), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_sof_n_pipe[0]), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tsn_pipe_9__2060), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_56430) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_i_m3_0_45_.INIT = 8'hB8; + LUT3 com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_i_m3_0_45_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_d16_sw[13]), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_sof_n_pipe[0]), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tsn_pipe_10__2059), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_56431) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_i_m3_0_44_.INIT = 8'hB8; + LUT3 com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_i_m3_0_44_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_d16_sw[12]), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_sof_n_pipe[0]), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tsn_pipe_11__2058), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_56432) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_i_m3_0_39_.INIT = 8'hB8; + LUT3 com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_i_m3_0_39_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_d16_sw[7]), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_sof_n_pipe[0]), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tsn_pipe_0__2069), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_56433) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_i_m3_0_38_.INIT = 8'hB8; + LUT3 com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_i_m3_0_38_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_d16_sw[6]), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_sof_n_pipe[0]), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tsn_pipe_1__2068), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_56434) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_i_m3_0_37_.INIT = 8'hB8; + LUT3 com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_i_m3_0_37_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_d16_sw[5]), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_sof_n_pipe[0]), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tsn_pipe_2__2067), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_56435) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_i_m3_0_36_.INIT = 8'hB8; + LUT3 com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_i_m3_0_36_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_d16_sw[4]), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_sof_n_pipe[0]), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tsn_pipe_3__2066), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_56436) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_i_m3_0_35_.INIT = 8'hB8; + LUT3 com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_i_m3_0_35_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_d16_sw[3]), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_sof_n_pipe[0]), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tsn_pipe_4__2065), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_56437) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_i_m3_0_34_.INIT = 8'hB8; + LUT3 com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_i_m3_0_34_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_d16_sw[2]), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_sof_n_pipe[0]), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tsn_pipe_5__2064), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_56438) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_i_m3_0_33_.INIT = 8'hB8; + LUT3 com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_i_m3_0_33_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_d16_sw[1]), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_sof_n_pipe[0]), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tsn_pipe_6__2063), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_56439) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_i_m3_0_32_.INIT = 8'hB8; + LUT3 com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_i_m3_0_32_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_d16_sw[0]), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_sof_n_pipe[0]), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tsn_pipe_7__2062), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_56440) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_i_m2_i_a2_30_.INIT = 4'h2; + LUT2_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_i_m2_i_a2_30_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_55887_i), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_d32_sw[30]), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_58778) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_i_m2_i_a2_31_.INIT = 4'h2; + LUT2_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_i_m2_i_a2_31_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_55887_i), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_d32_sw[31]), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_58776) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_i_m2_i_a2_29_.INIT = 4'h2; + LUT2_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_i_m2_i_a2_29_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_55887_i), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_d32_sw[29]), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_58774) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_i_a2_0_47_.INIT = 4'h2; + LUT2_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_i_a2_0_47_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_55887_i), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_d64_sw[47]), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_58222) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_i_a2_0_46_.INIT = 4'h2; + LUT2_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_i_a2_0_46_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_55887_i), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_d64_sw[46]), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_58220) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_i_a2_0_45_.INIT = 4'h2; + LUT2_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_i_a2_0_45_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_55887_i), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_d64_sw[45]), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_58218) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_i_a2_0_44_.INIT = 4'h2; + LUT2_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_i_a2_0_44_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_55887_i), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_d64_sw[44]), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_58216) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_i_a2_0_39_.INIT = 4'h2; + LUT2_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_i_a2_0_39_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_55887_i), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_d64_sw[39]), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_58206) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_i_a2_0_38_.INIT = 4'h2; + LUT2_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_i_a2_0_38_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_55887_i), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_d64_sw[38]), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_58204) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_i_a2_0_37_.INIT = 4'h2; + LUT2_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_i_a2_0_37_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_55887_i), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_d64_sw[37]), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_58202) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_i_a2_0_36_.INIT = 4'h2; + LUT2_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_i_a2_0_36_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_55887_i), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_d64_sw[36]), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_58200) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_i_a2_0_35_.INIT = 4'h2; + LUT2_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_i_a2_0_35_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_55887_i), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_d64_sw[35]), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_58198) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_i_a2_0_34_.INIT = 4'h2; + LUT2_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_i_a2_0_34_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_55887_i), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_d64_sw[34]), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_58196) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_i_a2_0_33_.INIT = 4'h2; + LUT2_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_i_a2_0_33_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_55887_i), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_d64_sw[33]), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_58194) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_i_a2_0_32_.INIT = 4'h2; + LUT2_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_i_a2_0_32_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_55887_i), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_d64_sw[32]), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_58192) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_i_a2_28_.INIT = 4'h2; + LUT2_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_i_a2_28_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_55887_i), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_d32_sw[28]), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_58189) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_i_a2_27_.INIT = 4'h2; + LUT2_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_i_a2_27_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_55887_i), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_d32_sw[27]), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_58187) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_i_a2_26_.INIT = 4'h2; + LUT2_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_i_a2_26_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_55887_i), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_d32_sw[26]), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_58185) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_i_a2_25_.INIT = 4'h2; + LUT2_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_i_a2_25_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_55887_i), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_d32_sw[25]), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_58183) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_i_a2_24_.INIT = 4'h2; + LUT2_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_i_a2_24_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_55887_i), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_d32_sw[24]), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_58181) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_i_a2_23_.INIT = 4'h2; + LUT2_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_i_a2_23_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_55887_i), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_d32_sw[23]), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_58179) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_i_a2_22_.INIT = 4'h2; + LUT2_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_i_a2_22_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_55887_i), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_d32_sw[22]), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_58177) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_i_a2_21_.INIT = 4'h2; + LUT2_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_i_a2_21_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_55887_i), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_d32_sw[21]), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_58175) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_i_a2_20_.INIT = 4'h2; + LUT2_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_i_a2_20_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_55887_i), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_d32_sw[20]), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_58173) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_i_a2_19_.INIT = 4'h2; + LUT2_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_i_a2_19_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_55887_i), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_d32_sw[19]), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_58171) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_i_a2_18_.INIT = 4'h2; + LUT2_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_i_a2_18_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_55887_i), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_d32_sw[18]), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_58169) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_i_a2_17_.INIT = 4'h2; + LUT2_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_i_a2_17_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_55887_i), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_d32_sw[17]), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_58167) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_i_a2_0_16_.INIT = 4'h2; + LUT2_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_i_a2_0_16_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_55887_i), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_d32_sw[16]), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_58165) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_i_o3_56_.INIT = 8'h27; + LUT3 com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_i_o3_56_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_55887_i), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_sof_n_pipe[0]), + .I2(com_reset_i_q), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_56044_i) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_i_0_11_.INIT = 16'hFACA; + LUT4 com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_i_0_11_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_d16_sw[11]), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_d32_sw[27]), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_eof_n_pipe_6114[1]), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_rem_pipe_6115[0]), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_i_0_11__2209) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_i_0_15_.INIT = 16'hFACA; + LUT4 com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_i_0_15_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_d16_sw[15]), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_d32_sw[31]), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_eof_n_pipe_6114[1]), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_rem_pipe_6115[0]), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_i_0_15__2205) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_i_0_13_.INIT = 16'hFACA; + LUT4 com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_i_0_13_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_d16_sw[13]), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_d32_sw[29]), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_eof_n_pipe_6114[1]), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_rem_pipe_6115[0]), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_i_0_13__2207) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_i_0_4_.INIT = 16'hFACA; + LUT4 com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_i_0_4_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_d16_sw[4]), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_d32_sw[20]), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_eof_n_pipe_6114[1]), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_rem_pipe_6115[0]), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_i_0_4__2216) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_i_0_3_.INIT = 16'hFACA; + LUT4 com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_i_0_3_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_d16_sw[3]), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_d32_sw[19]), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_eof_n_pipe_6114[1]), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_rem_pipe_6115[0]), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_i_0_3__2217) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_i_0_12_.INIT = 16'hFACA; + LUT4 com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_i_0_12_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_d16_sw[12]), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_d32_sw[28]), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_eof_n_pipe_6114[1]), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_rem_pipe_6115[0]), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_i_0_12__2208) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_i_0_1_.INIT = 16'hFACA; + LUT4 com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_i_0_1_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_d16_sw[1]), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_d32_sw[17]), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_eof_n_pipe_6114[1]), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_rem_pipe_6115[0]), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_i_0_1__2219) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_i_0_2_.INIT = 16'hFACA; + LUT4 com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_i_0_2_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_d16_sw[2]), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_d32_sw[18]), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_eof_n_pipe_6114[1]), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_rem_pipe_6115[0]), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_i_0_2__2218) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_i_0_14_.INIT = 16'hFACA; + LUT4 com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_i_0_14_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_d16_sw[14]), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_d32_sw[30]), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_eof_n_pipe_6114[1]), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_rem_pipe_6115[0]), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_i_0_14__2206) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_i_0_6_.INIT = 16'hFACA; + LUT4 com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_i_0_6_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_d16_sw[6]), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_d32_sw[22]), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_eof_n_pipe_6114[1]), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_rem_pipe_6115[0]), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_i_0_6__2214) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_i_0_8_.INIT = 16'hFACA; + LUT4 com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_i_0_8_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_d16_sw[8]), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_d32_sw[24]), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_eof_n_pipe_6114[1]), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_rem_pipe_6115[0]), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_i_0_8__2212) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_i_0_5_.INIT = 16'hFACA; + LUT4 com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_i_0_5_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_d16_sw[5]), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_d32_sw[21]), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_eof_n_pipe_6114[1]), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_rem_pipe_6115[0]), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_i_0_5__2215) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_i_0_7_.INIT = 16'hFACA; + LUT4 com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_i_0_7_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_d16_sw[7]), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_d32_sw[23]), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_eof_n_pipe_6114[1]), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_rem_pipe_6115[0]), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_i_0_7__2213) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_i_0_0_.INIT = 16'hFACA; + LUT4 com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_i_0_0_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_d16_sw[0]), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_d32_sw[16]), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_eof_n_pipe_6114[1]), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_rem_pipe_6115[0]), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_i_0_0__2220) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_i_0_10_.INIT = 16'hFACA; + LUT4 com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_i_0_10_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_d16_sw[10]), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_d32_sw[26]), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_eof_n_pipe_6114[1]), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_rem_pipe_6115[0]), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_i_0_10__2210) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_i_0_9_.INIT = 16'hFACA; + LUT4 com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_i_0_9_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_d16_sw[9]), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_d32_sw[25]), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_eof_n_pipe_6114[1]), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_rem_pipe_6115[0]), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_i_0_9__2211) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_i_0_42_.INIT = 16'hCFAF; + LUT4 com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_i_0_42_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_d16_sw[10]), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_d64_sw[42]), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_eof_n_pipe_6114[1]), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_rem_pipe_6115[0]), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_i_0_42__2202) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_i_0_43_.INIT = 16'hCFAF; + LUT4 com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_i_0_43_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_d16_sw[11]), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_d64_sw[43]), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_eof_n_pipe_6114[1]), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_rem_pipe_6115[0]), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_i_0_43__2201) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_i_0_41_.INIT = 16'hCFAF; + LUT4 com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_i_0_41_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_d16_sw[9]), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_d64_sw[41]), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_eof_n_pipe_6114[1]), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_rem_pipe_6115[0]), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_i_0_41__2203) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_i_0_40_.INIT = 16'hCFAF; + LUT4 com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_i_0_40_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_d16_sw[8]), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_d64_sw[40]), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_eof_n_pipe_6114[1]), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_rem_pipe_6115[0]), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_i_0_40__2204) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_am_1_.INIT = 8'h96; + LUT3 com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_am_1_ ( + .I0(N_45), + .I1(N_104), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_d64_c_q_1__2257), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_am_1__2111) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_bm_1_.INIT = 16'h6996; + LUT4 com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_bm_1_ ( + .I0(N_71), + .I1(N_83), + .I2(N_12040), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_new_c48_1_1_1_), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_bm_1__2110) + ); + MUXF5 com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_1_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_am_1__2111), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_bm_1__2110), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4[1]), + .S(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crcdatawidth_qq[2]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_am_6_.INIT = 16'h6996; + LUT4 com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_am_6_ ( + .I0(N_43), + .I1(N_85), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[24]), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_d64_c_q_6__2254), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_am_6__2113) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_bm_6_.INIT = 16'h6996; + LUT4 com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_bm_6_ ( + .I0(N_69), + .I1(N_97), + .I2(N_167), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_new_c48_1_1_6_), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_bm_6__2112) + ); + MUXF5 com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_6_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_am_6__2113), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_bm_6__2112), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4[6]), + .S(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crcdatawidth_qq[2]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_bm_10_.INIT = 16'h6996; + LUT4 com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_bm_10_ ( + .I0(N_47), + .I1(N_81), + .I2(N_12042), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_new_c48_1_1_10_), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_bm_10__2114) + ); + MUXF5 com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_10_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_am_10__2167), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_bm_10__2114), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4[10]), + .S(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crcdatawidth_qq[2]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_am_12_.INIT = 16'h6996; + LUT4 com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_am_12_ ( + .I0(N_68), + .I1(N_80), + .I2(N_95), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_d64_c_q_12__2248), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_am_12__2115) + ); + MUXF5 com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_12_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_am_12__2115), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_bm_12__2227), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4[12]), + .S(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crcdatawidth_qq[2]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_am_13_.INIT = 16'h6996; + LUT4 com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_am_13_ ( + .I0(N_43), + .I1(N_12041), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[26]), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_new_c16_1_0[13]), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_am_13__2116) + ); + MUXF5 com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_13_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_am_13__2116), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_bm_13__2225), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4[13]), + .S(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crcdatawidth_qq[2]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_am_14_.INIT = 4'h6; + LUT2 com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_am_14_ ( + .I0(N_43), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_new_c16_1_1_14_), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_am_14__2118) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_bm_14_.INIT = 16'h6996; + LUT4 com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_bm_14_ ( + .I0(N_82), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[28]), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_new_c48_1_0_14_), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_new_c48_1_2_14_), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_bm_14__2117) + ); + MUXF5 com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_14_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_am_14__2118), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_bm_14__2117), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4[14]), + .S(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crcdatawidth_qq[2]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_am_15_.INIT = 16'h6996; + LUT4 com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_am_15_ ( + .I0(N_44), + .I1(N_11851), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[25]), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_d64_c_q_15__2245), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_am_15__2120) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_bm_15_.INIT = 8'h96; + LUT3 com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_bm_15_ ( + .I0(N_12167), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_new_c48_1_1_15_), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_new_c48_1_3_15_), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_bm_15__2119) + ); + MUXF5 com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_15_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_am_15__2120), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_bm_15__2119), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4[15]), + .S(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crcdatawidth_qq[2]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_am_16_.INIT = 8'h96; + LUT3 com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_am_16_ ( + .I0(N_102), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[0]), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_new_c16_1_1_16_), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_am_16__2122) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_bm_16_.INIT = 16'h6996; + LUT4 com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_bm_16_ ( + .I0(N_70), + .I1(N_11864), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_new_c48_1_1_16_), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_new_c48_1_2_16_), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_bm_16__2121) + ); + MUXF5 com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_16_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_am_16__2122), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_bm_16__2121), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4[16]), + .S(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crcdatawidth_qq[2]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_am_17_.INIT = 16'h6996; + LUT4 com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_am_17_ ( + .I0(N_80), + .I1(N_152), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[22]), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_d64_c_q_17__2243), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_am_17__2124) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_bm_17_.INIT = 16'h6996; + LUT4 com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_bm_17_ ( + .I0(N_69), + .I1(N_11850), + .I2(N_12167), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_new_c48_1_2_17_), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_bm_17__2123) + ); + MUXF5 com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_17_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_am_17__2124), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_bm_17__2123), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4[17]), + .S(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crcdatawidth_qq[2]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_am_18_.INIT = 8'h96; + LUT3 com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_am_18_ ( + .I0(N_43), + .I1(N_72), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_d64_c_q_18__2242), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_am_18__2126) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_bm_18_.INIT = 16'h6996; + LUT4 com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_bm_18_ ( + .I0(N_46), + .I1(N_12173), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[3]), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_new_c48_1_1_18_), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_bm_18__2125) + ); + MUXF5 com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_18_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_am_18__2126), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_bm_18__2125), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4[18]), + .S(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crcdatawidth_qq[2]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_am_19_.INIT = 16'h6996; + LUT4 com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_am_19_ ( + .I0(N_44), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[3]), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[27]), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_d64_c_q_19__2241), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_am_19__2128) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_bm_19_.INIT = 16'h6996; + LUT4 com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_bm_19_ ( + .I0(N_69), + .I1(N_81_1), + .I2(N_83), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_new_c48_1_1_19_), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_bm_19__2127) + ); + MUXF5 com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_19_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_am_19__2128), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_bm_19__2127), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4[19]), + .S(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crcdatawidth_qq[2]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_am_20_.INIT = 16'h6996; + LUT4 com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_am_20_ ( + .I0(N_100), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[4]), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[25]), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_d64_c_q_20__2240), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_am_20__2130) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_bm_20_.INIT = 16'h6996; + LUT4 com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_bm_20_ ( + .I0(N_47), + .I1(N_84), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_new_c48_1_2_20_), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_new_c32_d16_1_25_), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_bm_20__2129) + ); + MUXF5 com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_20_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_am_20__2130), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_bm_20__2129), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4[20]), + .S(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crcdatawidth_qq[2]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_am_21_.INIT = 16'h6996; + LUT4 com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_am_21_ ( + .I0(N_143), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[21]), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[26]), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_d64_c_q_21__2239), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_am_21__2132) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_bm_21_.INIT = 16'h6996; + LUT4 com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_bm_21_ ( + .I0(N_98), + .I1(N_119), + .I2(N_12042), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_new_c48_1_0_21_), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_bm_21__2131) + ); + MUXF5 com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_21_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_am_21__2132), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_bm_21__2131), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4[21]), + .S(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crcdatawidth_qq[2]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_am_27_.INIT = 16'h6996; + LUT4 com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_am_27_ ( + .I0(N_85), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[11]), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[23]), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_d64_c_q_27__2233), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_am_27__2134) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_bm_27_.INIT = 16'h6996; + LUT4 com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_bm_27_ ( + .I0(N_48), + .I1(N_99), + .I2(N_103), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_new_c48_1_2_27_), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_bm_27__2133) + ); + MUXF5 com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_27_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_am_27__2134), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_bm_27__2133), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4[27]), + .S(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crcdatawidth_qq[2]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_am_28_.INIT = 16'h6996; + LUT4 com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_am_28_ ( + .I0(N_95), + .I1(N_12095), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[24]), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_d64_c_q_28__2232), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_am_28__2136) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_bm_28_.INIT = 16'h6996; + LUT4 com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_bm_28_ ( + .I0(N_84), + .I1(N_98), + .I2(N_11864), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_new_c48_1_2_28_), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_bm_28__2135) + ); + MUXF5 com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_28_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_am_28__2136), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_bm_28__2135), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4[28]), + .S(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crcdatawidth_qq[2]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_am_0_.INIT = 16'h6996; + LUT4 com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_am_0_ ( + .I0(N_96), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[25]), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[28]), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_d64_c_q_0__2258), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_am_0__2138) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_bm_0_.INIT = 16'h6996; + LUT4 com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_bm_0_ ( + .I0(N_102), + .I1(N_12121), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[0]), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_new_c48_1_2_0_), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_bm_0__2137) + ); + MUXF5 com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_0_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_am_0__2138), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_bm_0__2137), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4[0]), + .S(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crcdatawidth_qq[2]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_am_2_.INIT = 16'h6996; + LUT4 com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_am_2_ ( + .I0(N_43), + .I1(N_80), + .I2(N_105), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[24]), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_am_2__2140) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_bm_2_.INIT = 16'h6996; + LUT4 com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_bm_2_ ( + .I0(N_47), + .I1(N_93), + .I2(N_11962), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_new_c48_1_1_2_), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_bm_2__2139) + ); + MUXF5 com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_2_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_am_2__2140), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_bm_2__2139), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4[2]), + .S(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crcdatawidth_qq[2]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_bm_3_.INIT = 16'h6996; + LUT4 com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_bm_3_ ( + .I0(N_99), + .I1(N_11962), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_new_c48_1_1_3_), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_new_c32_d16_1_5_), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_bm_3__2141) + ); + MUXF5 com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_3_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_am_3__2166), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_bm_3__2141), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4[3]), + .S(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crcdatawidth_qq[2]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_am_4_.INIT = 8'h96; + LUT3 com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_am_4_ ( + .I0(N_68), + .I1(N_11855), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_new_c16_1_1_4_), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_am_4__2143) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_bm_4_.INIT = 16'h6996; + LUT4 com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_bm_4_ ( + .I0(N_45), + .I1(N_97), + .I2(N_12076), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_new_c48_1_1_4_), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_bm_4__2142) + ); + MUXF5 com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_4_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_am_4__2143), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_bm_4__2142), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4[4]), + .S(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crcdatawidth_qq[2]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_am_5_.INIT = 16'h6996; + LUT4 com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_am_5_ ( + .I0(N_12099), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[19]), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[20]), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_new_c32_d16_1_5_), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_am_5__2145) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_bm_5_.INIT = 16'h6996; + LUT4 com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_bm_5_ ( + .I0(N_46), + .I1(N_97), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[3]), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_new_c48_1_1_5_), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_bm_5__2144) + ); + MUXF5 com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_5_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_am_5__2145), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_bm_5__2144), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4[5]), + .S(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crcdatawidth_qq[2]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_am_7_.INIT = 8'h96; + LUT3 com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_am_7_ ( + .I0(N_102), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_d64_c_q_7__2253), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_new_c32_d16_1_3_), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_am_7__2147) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_bm_7_.INIT = 16'h6996; + LUT4 com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_bm_7_ ( + .I0(N_46), + .I1(N_103), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_new_c48_1_1_7_), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_new_c48_1_3_7_), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_bm_7__2146) + ); + MUXF5 com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_7_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_am_7__2147), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_bm_7__2146), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4[7]), + .S(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crcdatawidth_qq[2]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_am_8_.INIT = 8'h96; + LUT3 com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_am_8_ ( + .I0(N_81), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_d64_c_q_8__2252), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_new_c16_1_1_8_), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_am_8__2148) + ); + MUXF5 com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_8_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_am_8__2148), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_bm_8__2223), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4[8]), + .S(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crcdatawidth_qq[2]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_am_9_.INIT = 16'h6996; + LUT4 com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_am_9_ ( + .I0(N_80), + .I1(N_11851), + .I2(N_11855), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_d64_c_q_9__2251), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_am_9__2150) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_bm_9_.INIT = 16'h6996; + LUT4 com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_bm_9_ ( + .I0(N_43), + .I1(N_68), + .I2(N_82), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_new_c48_1_0_9_), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_bm_9__2149) + ); + MUXF5 com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_9_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_am_9__2150), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_bm_9__2149), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4[9]), + .S(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crcdatawidth_qq[2]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_am_11_.INIT = 16'h6996; + LUT4 com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_am_11_ ( + .I0(N_68), + .I1(N_86), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[19]), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_d64_c_q_11__2249), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_am_11__2152) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_bm_11_.INIT = 16'h6996; + LUT4 com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_bm_11_ ( + .I0(N_67), + .I1(N_80), + .I2(N_98), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_new_c48_1_1_11_), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_bm_11__2151) + ); + MUXF5 com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_11_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_am_11__2152), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_bm_11__2151), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4[11]), + .S(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crcdatawidth_qq[2]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_am_22_.INIT = 16'h6996; + LUT4 com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_am_22_ ( + .I0(N_104), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[6]), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[30]), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_d64_c_q_22__2238), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_am_22__2154) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_bm_22_.INIT = 16'h6996; + LUT4 com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_bm_22_ ( + .I0(N_70), + .I1(N_11850), + .I2(N_12043), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_new_c48_1_3_22_), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_bm_22__2153) + ); + MUXF5 com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_22_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_am_22__2154), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_bm_22__2153), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4[22]), + .S(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crcdatawidth_qq[2]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_am_23_.INIT = 8'h96; + LUT3 com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_am_23_ ( + .I0(N_80), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[22]), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_new_c16_1_1_23_), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_am_23__2156) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_bm_23_.INIT = 16'h6996; + LUT4 com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_bm_23_ ( + .I0(N_43), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[26]), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_new_c48_1_1_23_), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_new_c32_d48_1[23]), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_bm_23__2155) + ); + MUXF5 com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_23_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_am_23__2156), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_bm_23__2155), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4[23]), + .S(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crcdatawidth_qq[2]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_am_24_.INIT = 4'h6; + LUT2 com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_am_24_ ( + .I0(N_49), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_new_c16_1_2[24]), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_am_24__2157) + ); + MUXF5 com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_24_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_am_24__2157), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_bm_24__2221), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4[24]), + .S(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crcdatawidth_qq[2]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_bm_25_.INIT = 16'h6996; + LUT4 com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_bm_25_ ( + .I0(N_84), + .I1(N_93), + .I2(N_11962), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_new_c48_1_2_25_), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_bm_25__2158) + ); + MUXF5 com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_25_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_am_25__2165), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_bm_25__2158), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4[25]), + .S(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crcdatawidth_qq[2]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_am_26_.INIT = 4'h6; + LUT2 com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_am_26_ ( + .I0(N_96), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_new_c16_1_1_26_), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_am_26__2160) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_bm_26_.INIT = 16'h6996; + LUT4 com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_bm_26_ ( + .I0(N_48), + .I1(N_94), + .I2(N_12076), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_new_c48_1_1_26_), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_bm_26__2159) + ); + MUXF5 com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_26_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_am_26__2160), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_bm_26__2159), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4[26]), + .S(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crcdatawidth_qq[2]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_am_29_.INIT = 16'h6996; + LUT4 com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_am_29_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[13]), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[25]), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[29]), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_new_c16_1_1_29_), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_am_29__2162) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_bm_29_.INIT = 8'h96; + LUT3 com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_bm_29_ ( + .I0(N_119), + .I1(N_12121), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_new_c48_1_2_29_), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_bm_29__2161) + ); + MUXF5 com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_29_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_am_29__2162), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_bm_29__2161), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4[29]), + .S(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crcdatawidth_qq[2]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_am_31_.INIT = 4'h6; + LUT2 com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_am_31_ ( + .I0(N_73), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_new_c16_1_1_31_), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_am_31__2164) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_bm_31_.INIT = 8'h96; + LUT3 com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_bm_31_ ( + .I0(N_151), + .I1(N_12121), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_new_c48_1_1_31_), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_bm_31__2163) + ); + MUXF5 com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_31_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_am_31__2164), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_bm_31__2163), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4[31]), + .S(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crcdatawidth_qq[2]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_am_25_.INIT = 16'h6996; + LUT4 com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_am_25_ ( + .I0(N_73), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[19]), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_d64_c_q_25__2235), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_new_c32_d16_1_25_), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_am_25__2165) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_am_3_.INIT = 8'h96; + LUT3 com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_am_3_ ( + .I0(N_86), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_d64_c_q_3__2256), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_new_c32_d16_1_3_), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_am_3__2166) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_am_10_.INIT = 16'h6996; + LUT4 com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_am_10_ ( + .I0(N_12041), + .I1(N_12173), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[25]), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_d64_c_q_10__2250), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_am_10__2167) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_30_.INIT = 16'hDE12; + LUT4_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_30_ ( + .I0(N_49), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crcdatawidth_qq[2]), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_new_c16_1_1_30_), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_new_c32_d48[30]), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4[30]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_26520_i.INIT = 4'hE; + LUT2_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_26520_i ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crcint_qq_2200), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_new_c32_d64[31]), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_26520_i_2168) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_26521_i.INIT = 4'hE; + LUT2_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_26521_i ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crcint_qq_2200), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_new_c32_d64[30]), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_26521_i_2169) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_26522_i.INIT = 4'hE; + LUT2_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_26522_i ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crcint_qq_2200), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_new_c32_d64[29]), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_26522_i_2170) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_26523_i.INIT = 4'hE; + LUT2_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_26523_i ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crcint_qq_2200), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_new_c32_d64[28]), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_26523_i_2171) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_26524_i.INIT = 4'hE; + LUT2_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_26524_i ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crcint_qq_2200), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_new_c32_d64[27]), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_26524_i_2172) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_26525_i.INIT = 4'hE; + LUT2_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_26525_i ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crcint_qq_2200), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_new_c32_d64[26]), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_26525_i_2173) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_26526_i.INIT = 4'hE; + LUT2_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_26526_i ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crcint_qq_2200), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_new_c32_d64[25]), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_26526_i_2174) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_26527_i.INIT = 4'hE; + LUT2_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_26527_i ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crcint_qq_2200), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_new_c32_d64[24]), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_26527_i_2175) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_26528_i.INIT = 4'hE; + LUT2_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_26528_i ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crcint_qq_2200), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_new_c32_d64[23]), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_26528_i_2176) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_26529_i.INIT = 4'hE; + LUT2_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_26529_i ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crcint_qq_2200), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_new_c32_d64[22]), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_26529_i_2177) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_26530_i.INIT = 4'hE; + LUT2_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_26530_i ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crcint_qq_2200), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_new_c32_d64[21]), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_26530_i_2178) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_26531_i.INIT = 4'hE; + LUT2_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_26531_i ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crcint_qq_2200), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_new_c32_d64[20]), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_26531_i_2179) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_26532_i.INIT = 4'hE; + LUT2_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_26532_i ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crcint_qq_2200), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_new_c32_d64[19]), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_26532_i_2180) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_26552_i.INIT = 4'hE; + LUT2_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_26552_i ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crcint_qq_2200), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_new_c32_d64[18]), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_26552_i_2181) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_26553_i.INIT = 4'hE; + LUT2_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_26553_i ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crcint_qq_2200), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_new_c32_d64[17]), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_26553_i_2182) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_26554_i.INIT = 4'hE; + LUT2_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_26554_i ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crcint_qq_2200), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_new_c32_d64[16]), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_26554_i_2183) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_26555_i.INIT = 4'hE; + LUT2_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_26555_i ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crcint_qq_2200), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_new_c32_d64[15]), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_26555_i_2184) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_26556_i.INIT = 4'hE; + LUT2_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_26556_i ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crcint_qq_2200), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_new_c32_d64[14]), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_26556_i_2185) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_26557_i.INIT = 4'hE; + LUT2_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_26557_i ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crcint_qq_2200), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_new_c32_d64[13]), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_26557_i_2186) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_26558_i.INIT = 4'hE; + LUT2_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_26558_i ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crcint_qq_2200), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_new_c32_d64[12]), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_26558_i_2187) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_26559_i.INIT = 4'hE; + LUT2_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_26559_i ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crcint_qq_2200), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_new_c32_d64[11]), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_26559_i_2188) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_26560_i.INIT = 4'hE; + LUT2_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_26560_i ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crcint_qq_2200), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_new_c32_d64[10]), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_26560_i_2189) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_26561_i.INIT = 4'hE; + LUT2_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_26561_i ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crcint_qq_2200), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_new_c32_d64[9]), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_26561_i_2190) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_26562_i.INIT = 4'hE; + LUT2_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_26562_i ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crcint_qq_2200), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_new_c32_d64[8]), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_26562_i_2191) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_26563_i.INIT = 4'hE; + LUT2_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_26563_i ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crcint_qq_2200), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_new_c32_d64[7]), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_26563_i_2192) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_26564_i.INIT = 4'hE; + LUT2_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_26564_i ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crcint_qq_2200), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_new_c32_d64[6]), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_26564_i_2193) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_26533_i.INIT = 4'hE; + LUT2_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_26533_i ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crcint_qq_2200), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_new_c32_d64[5]), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_26533_i_2194) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_26534_i.INIT = 4'hE; + LUT2_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_26534_i ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crcint_qq_2200), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_new_c32_d64[4]), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_26534_i_2195) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_26535_i.INIT = 4'hE; + LUT2_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_26535_i ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crcint_qq_2200), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_new_c32_d64[3]), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_26535_i_2196) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_26536_i.INIT = 4'hE; + LUT2_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_26536_i ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crcint_qq_2200), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_new_c32_d64[2]), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_26536_i_2197) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_26537_i.INIT = 4'hE; + LUT2_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_26537_i ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crcint_qq_2200), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_new_c32_d64[1]), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_26537_i_2198) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_26538_i.INIT = 4'hE; + LUT2_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_26538_i ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crcint_qq_2200), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_new_c32_d64[0]), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_26538_i_2199) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_i_m3_0_63_.INIT = 8'hD8; + LUT3_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_i_m3_0_63_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_55887_i), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_56429), + .I2(com_reset_i_q), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_i_m3_0_63__2259) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_i_m3_0_62_.INIT = 8'hD8; + LUT3_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_i_m3_0_62_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_55887_i), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_56430), + .I2(com_reset_i_q), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_i_m3_0_62__2260) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_i_m3_0_61_.INIT = 8'hD8; + LUT3_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_i_m3_0_61_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_55887_i), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_56431), + .I2(com_reset_i_q), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_i_m3_0_61__2261) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_i_m3_0_60_.INIT = 8'hD8; + LUT3_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_i_m3_0_60_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_55887_i), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_56432), + .I2(com_reset_i_q), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_i_m3_0_60__2262) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_i_59_.INIT = 8'h31; + LUT3_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_i_59_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_55887_i), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_56044_i), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_d16_sw[11]), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_51318_i) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_i_58_.INIT = 8'h31; + LUT3_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_i_58_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_55887_i), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_56044_i), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_d16_sw[10]), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_51316_i) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_i_57_.INIT = 8'h31; + LUT3_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_i_57_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_55887_i), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_56044_i), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_d16_sw[9]), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_51314_i) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_i_56_.INIT = 8'h31; + LUT3_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_i_56_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_55887_i), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_56044_i), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_d16_sw[8]), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_51312_i) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_i_m3_0_55_.INIT = 8'hD8; + LUT3_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_i_m3_0_55_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_55887_i), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_56433), + .I2(com_reset_i_q), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_i_m3_0_55__2263) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_i_m3_0_54_.INIT = 8'hD8; + LUT3_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_i_m3_0_54_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_55887_i), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_56434), + .I2(com_reset_i_q), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_i_m3_0_54__2264) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_i_m3_0_53_.INIT = 8'hD8; + LUT3_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_i_m3_0_53_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_55887_i), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_56435), + .I2(com_reset_i_q), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_i_m3_0_53__2265) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_i_m3_0_52_.INIT = 8'hD8; + LUT3_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_i_m3_0_52_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_55887_i), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_56436), + .I2(com_reset_i_q), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_i_m3_0_52__2266) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_i_m3_0_51_.INIT = 8'hD8; + LUT3_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_i_m3_0_51_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_55887_i), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_56437), + .I2(com_reset_i_q), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_i_m3_0_51__2267) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_i_m3_0_50_.INIT = 8'hD8; + LUT3_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_i_m3_0_50_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_55887_i), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_56438), + .I2(com_reset_i_q), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_i_m3_0_50__2268) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_i_m3_0_49_.INIT = 8'hD8; + LUT3_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_i_m3_0_49_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_55887_i), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_56439), + .I2(com_reset_i_q), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_i_m3_0_49__2269) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_i_m3_0_48_.INIT = 8'hD8; + LUT3_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_i_m3_0_48_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_55887_i), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_56440), + .I2(com_reset_i_q), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_i_m3_0_48__2270) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_i_47_.INIT = 16'h0203; + LUT4_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_i_47_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_56429), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_58164), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_58222), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_61310), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_51820_i) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_i_46_.INIT = 16'h0203; + LUT4_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_i_46_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_56430), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_58164), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_58220), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_61310), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_51818_i) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_i_45_.INIT = 16'h0203; + LUT4_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_i_45_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_56431), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_58164), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_58218), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_61310), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_51816_i) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_i_44_.INIT = 16'h0203; + LUT4_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_i_44_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_56432), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_58164), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_58216), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_61310), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_51814_i) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_i_43_.INIT = 16'h5010; + LUT4_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_i_43_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_58164), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_61310), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_i_0_43__2201), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_sof_n_pipe[0]), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_51812_i) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_i_42_.INIT = 16'h5010; + LUT4_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_i_42_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_58164), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_61310), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_i_0_42__2202), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_sof_n_pipe[0]), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_51810_i) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_i_41_.INIT = 16'h5010; + LUT4_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_i_41_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_58164), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_61310), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_i_0_41__2203), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_sof_n_pipe[0]), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_51808_i) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_i_40_.INIT = 16'h5010; + LUT4_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_i_40_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_58164), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_61310), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_i_0_40__2204), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_sof_n_pipe[0]), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_51806_i) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_i_39_.INIT = 16'h0203; + LUT4_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_i_39_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_56433), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_58164), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_58206), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_61310), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_51804_i) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_i_38_.INIT = 16'h0203; + LUT4_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_i_38_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_56434), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_58164), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_58204), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_61310), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_51802_i) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_i_37_.INIT = 16'h0203; + LUT4_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_i_37_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_56435), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_58164), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_58202), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_61310), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_51800_i) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_i_36_.INIT = 16'h0203; + LUT4_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_i_36_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_56436), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_58164), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_58200), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_61310), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_51798_i) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_i_35_.INIT = 16'h0203; + LUT4_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_i_35_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_56437), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_58164), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_58198), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_61310), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_51796_i) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_i_34_.INIT = 16'h0203; + LUT4_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_i_34_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_56438), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_58164), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_58196), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_61310), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_51794_i) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_i_33_.INIT = 16'h0203; + LUT4_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_i_33_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_56439), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_58164), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_58194), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_61310), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_51792_i) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_i_32_.INIT = 16'h0203; + LUT4_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_i_32_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_56440), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_58164), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_58192), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_61310), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_51790_i) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_i_m2_i_31_.INIT = 16'h1101; + LUT4_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_i_m2_i_31_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_58164), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_58776), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_61310), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_d64_sw[47]), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_52366_i) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_i_m2_i_30_.INIT = 16'h1101; + LUT4_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_i_m2_i_30_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_58164), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_58778), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_61310), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_d64_sw[46]), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_52368_i) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_i_m2_i_29_.INIT = 16'h1101; + LUT4_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_i_m2_i_29_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_58164), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_58774), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_61310), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_d64_sw[45]), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_52364_i) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_i_28_.INIT = 16'h1101; + LUT4_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_i_28_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_58164), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_58189), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_61310), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_d64_sw[44]), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_51788_i) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_i_27_.INIT = 16'h1101; + LUT4_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_i_27_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_58164), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_58187), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_61310), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_d64_sw[43]), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_51786_i) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_i_26_.INIT = 16'h1101; + LUT4_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_i_26_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_58164), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_58185), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_61310), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_d64_sw[42]), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_51784_i) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_i_25_.INIT = 16'h1101; + LUT4_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_i_25_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_58164), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_58183), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_61310), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_d64_sw[41]), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_51782_i) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_i_24_.INIT = 16'h1101; + LUT4_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_i_24_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_58164), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_58181), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_61310), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_d64_sw[40]), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_51780_i) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_i_23_.INIT = 16'h1101; + LUT4_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_i_23_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_58164), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_58179), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_61310), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_d64_sw[39]), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_51778_i) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_i_22_.INIT = 16'h1101; + LUT4_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_i_22_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_58164), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_58177), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_61310), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_d64_sw[38]), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_51776_i) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_i_21_.INIT = 16'h1101; + LUT4_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_i_21_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_58164), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_58175), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_61310), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_d64_sw[37]), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_51774_i) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_i_20_.INIT = 16'h1101; + LUT4_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_i_20_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_58164), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_58173), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_61310), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_d64_sw[36]), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_51772_i) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_i_19_.INIT = 16'h1101; + LUT4_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_i_19_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_58164), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_58171), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_61310), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_d64_sw[35]), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_51770_i) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_i_18_.INIT = 16'h1101; + LUT4_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_i_18_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_58164), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_58169), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_61310), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_d64_sw[34]), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_51768_i) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_i_17_.INIT = 16'h1101; + LUT4_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_i_17_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_58164), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_58167), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_61310), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_d64_sw[33]), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_51766_i) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_i_16_.INIT = 16'h1101; + LUT4_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_i_16_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_58164), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_58165), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_61310), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_d64_sw[32]), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_51764_i) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_i_15_.INIT = 8'hD0; + LUT3_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_i_15_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_55887_i), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_d32_sw[15]), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_i_0_15__2205), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_51762_i) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_i_14_.INIT = 8'hD0; + LUT3_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_i_14_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_55887_i), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_d32_sw[14]), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_i_0_14__2206), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_51760_i) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_i_13_.INIT = 8'hD0; + LUT3_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_i_13_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_55887_i), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_d32_sw[13]), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_i_0_13__2207), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_51758_i) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_i_12_.INIT = 8'hD0; + LUT3_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_i_12_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_55887_i), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_d32_sw[12]), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_i_0_12__2208), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_51756_i) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_i_11_.INIT = 8'hD0; + LUT3_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_i_11_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_55887_i), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_d32_sw[11]), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_i_0_11__2209), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_51754_i) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_i_10_.INIT = 8'hD0; + LUT3_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_i_10_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_55887_i), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_d32_sw[10]), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_i_0_10__2210), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_51752_i) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_i_9_.INIT = 8'hD0; + LUT3_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_i_9_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_55887_i), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_d32_sw[9]), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_i_0_9__2211), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_51750_i) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_i_8_.INIT = 8'hD0; + LUT3_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_i_8_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_55887_i), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_d32_sw[8]), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_i_0_8__2212), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_51748_i) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_i_7_.INIT = 8'hD0; + LUT3_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_i_7_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_55887_i), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_d32_sw[7]), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_i_0_7__2213), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_51746_i) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_i_6_.INIT = 8'hD0; + LUT3_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_i_6_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_55887_i), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_d32_sw[6]), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_i_0_6__2214), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_51744_i) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_i_5_.INIT = 8'hD0; + LUT3_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_i_5_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_55887_i), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_d32_sw[5]), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_i_0_5__2215), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_51742_i) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_i_4_.INIT = 8'hD0; + LUT3_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_i_4_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_55887_i), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_d32_sw[4]), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_i_0_4__2216), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_51740_i) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_i_3_.INIT = 8'hD0; + LUT3_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_i_3_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_55887_i), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_d32_sw[3]), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_i_0_3__2217), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_51738_i) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_i_2_.INIT = 8'hD0; + LUT3_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_i_2_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_55887_i), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_d32_sw[2]), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_i_0_2__2218), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_51736_i) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_i_1_.INIT = 8'hD0; + LUT3_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_i_1_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_55887_i), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_d32_sw[1]), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_i_0_1__2219), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_51734_i) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_i_0_.INIT = 8'hD0; + LUT3_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_i_0_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_55887_i), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_d32_sw[0]), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_i_0_0__2220), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_51732_i) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_sw_early_crc_i_23_.INIT = 4'h1; + LUT1_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_sw_early_crc_i_23_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_sw_early_crc[23]), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_sw_early_crc_i[23]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_sw_early_crc_i_22_.INIT = 4'h1; + LUT1_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_sw_early_crc_i_22_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_sw_early_crc[22]), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_sw_early_crc_i[22]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_sw_early_crc_i_21_.INIT = 4'h1; + LUT1_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_sw_early_crc_i_21_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_sw_early_crc[21]), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_sw_early_crc_i[21]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_sw_early_crc_i_20_.INIT = 4'h1; + LUT1_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_sw_early_crc_i_20_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_sw_early_crc[20]), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_sw_early_crc_i[20]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_sw_early_crc_i_19_.INIT = 4'h1; + LUT1_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_sw_early_crc_i_19_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_sw_early_crc[19]), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_sw_early_crc_i[19]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_sw_early_crc_i_18_.INIT = 4'h1; + LUT1_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_sw_early_crc_i_18_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_sw_early_crc[18]), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_sw_early_crc_i[18]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_sw_early_crc_i_17_.INIT = 4'h1; + LUT1_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_sw_early_crc_i_17_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_sw_early_crc[17]), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_sw_early_crc_i[17]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_sw_early_crc_i_16_.INIT = 4'h1; + LUT1_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_sw_early_crc_i_16_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_sw_early_crc[16]), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_sw_early_crc_i[16]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_sw_early_crc_i_15_.INIT = 4'h1; + LUT1_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_sw_early_crc_i_15_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_sw_early_crc[15]), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_sw_early_crc_i[15]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_sw_early_crc_i_14_.INIT = 4'h1; + LUT1_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_sw_early_crc_i_14_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_sw_early_crc[14]), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_sw_early_crc_i[14]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_sw_early_crc_i_13_.INIT = 4'h1; + LUT1_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_sw_early_crc_i_13_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_sw_early_crc[13]), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_sw_early_crc_i[13]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_sw_early_crc_i_12_.INIT = 4'h1; + LUT1_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_sw_early_crc_i_12_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_sw_early_crc[12]), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_sw_early_crc_i[12]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_sw_early_crc_i_11_.INIT = 4'h1; + LUT1_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_sw_early_crc_i_11_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_sw_early_crc[11]), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_sw_early_crc_i[11]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_sw_early_crc_i_10_.INIT = 4'h1; + LUT1_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_sw_early_crc_i_10_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_sw_early_crc[10]), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_sw_early_crc_i[10]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_sw_early_crc_i_9_.INIT = 4'h1; + LUT1_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_sw_early_crc_i_9_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_sw_early_crc[9]), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_sw_early_crc_i[9]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_sw_early_crc_i_8_.INIT = 4'h1; + LUT1_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_sw_early_crc_i_8_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_sw_early_crc[8]), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_sw_early_crc_i[8]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_sw_early_crc_i_7_.INIT = 4'h1; + LUT1_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_sw_early_crc_i_7_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_sw_early_crc[7]), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_sw_early_crc_i[7]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_sw_early_crc_i_6_.INIT = 4'h1; + LUT1_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_sw_early_crc_i_6_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_sw_early_crc[6]), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_sw_early_crc_i[6]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_sw_early_crc_i_5_.INIT = 4'h1; + LUT1_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_sw_early_crc_i_5_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_sw_early_crc[5]), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_sw_early_crc_i[5]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_sw_early_crc_i_4_.INIT = 4'h1; + LUT1_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_sw_early_crc_i_4_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_sw_early_crc[4]), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_sw_early_crc_i[4]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_sw_early_crc_i_3_.INIT = 4'h1; + LUT1_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_sw_early_crc_i_3_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_sw_early_crc[3]), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_sw_early_crc_i[3]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_sw_early_crc_i_2_.INIT = 4'h1; + LUT1_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_sw_early_crc_i_2_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_sw_early_crc[2]), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_sw_early_crc_i[2]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_sw_early_crc_i_1_.INIT = 4'h1; + LUT1_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_sw_early_crc_i_1_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_sw_early_crc[1]), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_sw_early_crc_i[1]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_sw_early_crc_i_0_.INIT = 4'h1; + LUT1_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_sw_early_crc_i_0_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_sw_early_crc[0]), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_sw_early_crc_i[0]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_bm_1_24_.INIT = 16'h6996; + LUT4 com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_bm_1_24_ ( + .I0(N_102), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[2]), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[12]), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_d64_c_q_24__2236), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_bm_1_24__2222) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_bm_24_.INIT = 16'h6996; + LUT4 com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_bm_24_ ( + .I0(N_44), + .I1(N_167), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_bm_1_24__2222), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_new_c32_d48_1[23]), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_bm_24__2221) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_bm_1_8_.INIT = 16'h6996; + LUT4 com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_bm_1_8_ ( + .I0(N_94), + .I1(N_11855), + .I2(N_12041), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[15]), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_bm_1_8__2224) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_bm_8_.INIT = 16'h6996; + LUT4 com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_bm_8_ ( + .I0(N_81), + .I1(N_152), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_d64_c_q_8__2252), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_bm_1_8__2224), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_bm_8__2223) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_bm_1_13_.INIT = 16'h6996; + LUT4 com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_bm_1_13_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[0]), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[12]), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[15]), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_d64_c_q_13__2247), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_bm_1_13__2226) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_bm_13_.INIT = 16'h6996; + LUT4 com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_bm_13_ ( + .I0(N_72), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[27]), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_new_c48_1_2_13_), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_bm_1_13__2226), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_bm_13__2225) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_bm_1_12_.INIT = 16'h6996; + LUT4 com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_bm_1_12_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[1]), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[5]), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[15]), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_d64_c_q_12__2248), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_bm_1_12__2228) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_bm_12_.INIT = 16'h6996; + LUT4 com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_bm_12_ ( + .I0(N_72), + .I1(N_151), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[25]), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_bm_1_12__2228), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_mux_c32_d48_d16_q_4_0_bm_12__2227) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_d64_c_q_31_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_3), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_d64_c[31]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_d64_c_q_31__2229) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_d64_c_q_30_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_3), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_d64_c[30]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_d64_c_q_30__2230) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_d64_c_q_29_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_3), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_d64_c[29]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_d64_c_q_29__2231) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_d64_c_q_28_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_3), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_d64_c[28]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_d64_c_q_28__2232) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_d64_c_q_27_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_3), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_d64_c[27]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_d64_c_q_27__2233) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_d64_c_q_26_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_3), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_d64_c[26]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_d64_c_q_26__2234) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_d64_c_q_25_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_3), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_d64_c[25]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_d64_c_q_25__2235) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_d64_c_q_24_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_3), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_d64_c[24]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_d64_c_q_24__2236) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_d64_c_q_23_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_3), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_d64_c[23]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_d64_c_q_23__2237) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_d64_c_q_22_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_3), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_d64_c[22]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_d64_c_q_22__2238) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_d64_c_q_21_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_3), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_d64_c[21]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_d64_c_q_21__2239) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_d64_c_q_20_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_2), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_d64_c[20]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_d64_c_q_20__2240) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_d64_c_q_19_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_2), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_d64_c[19]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_d64_c_q_19__2241) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_d64_c_q_18_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_2), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_d64_c[18]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_d64_c_q_18__2242) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_d64_c_q_17_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_2), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_d64_c[17]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_d64_c_q_17__2243) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_d64_c_q_16_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_2), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_d64_c[16]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_d64_c_q_16__2244) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_d64_c_q_15_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_2), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_d64_c[15]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_d64_c_q_15__2245) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_d64_c_q_14_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_2), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_d64_c[14]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_d64_c_q_14__2246) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_d64_c_q_13_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_2), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_d64_c[13]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_d64_c_q_13__2247) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_d64_c_q_12_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_2), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_d64_c[12]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_d64_c_q_12__2248) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_d64_c_q_11_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_2), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_d64_c[11]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_d64_c_q_11__2249) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_d64_c_q_10_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_2), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_d64_c[10]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_d64_c_q_10__2250) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_d64_c_q_9_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_2), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_d64_c[9]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_d64_c_q_9__2251) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_d64_c_q_8_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_2), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_d64_c[8]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_d64_c_q_8__2252) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_d64_c_q_7_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_2), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_d64_c[7]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_d64_c_q_7__2253) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_d64_c_q_6_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_2), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_d64_c[6]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_d64_c_q_6__2254) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_d64_c_q_5_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_2), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_d64_c[5]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_d64_c_q_5__632) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_d64_c_q_4_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_2), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_d64_c[4]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_d64_c_q_4__2255) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_d64_c_q_3_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_2), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_d64_c[3]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_d64_c_q_3__2256) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_d64_c_q_2_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_2), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_d64_c[2]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_d64_c_q_2__631) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_d64_c_q_1_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_2), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_d64_c[1]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_d64_c_q_1__2257) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_d64_c_q_0_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_2), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_d64_c[0]), + .Q(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_d64_c_q_0__2258) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_63_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_1), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_i_m3_0_63__2259), + .Q(data_in_q[63]) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_62_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_1), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_i_m3_0_62__2260), + .Q(data_in_q[62]) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_61_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_1), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_i_m3_0_61__2261), + .Q(data_in_q[61]) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_60_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_1), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_i_m3_0_60__2262), + .Q(data_in_q[60]) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_59_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_1), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_51318_i), + .Q(data_in_q[59]) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_58_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_1), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_51316_i), + .Q(data_in_q[58]) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_57_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_1), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_51314_i), + .Q(data_in_q[57]) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_56_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_1), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_51312_i), + .Q(data_in_q[56]) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_55_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_1), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_i_m3_0_55__2263), + .Q(data_in_q[55]) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_54_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_1), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_i_m3_0_54__2264), + .Q(data_in_q[54]) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_53_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_1), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_i_m3_0_53__2265), + .Q(data_in_q[53]) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_52_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_1), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_i_m3_0_52__2266), + .Q(data_in_q[52]) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_51_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_1), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_i_m3_0_51__2267), + .Q(data_in_q[51]) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_50_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_1), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_i_m3_0_50__2268), + .Q(data_in_q[50]) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_49_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_1), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_i_m3_0_49__2269), + .Q(data_in_q[49]) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_48_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_1), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_i_m3_0_48__2270), + .Q(data_in_q[48]) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_47_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_1), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_51820_i), + .Q(data_in_q[47]) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_46_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_1), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_51818_i), + .Q(data_in_q[46]) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_45_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_1), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_51816_i), + .Q(data_in_q[45]) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_44_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_1), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_51814_i), + .Q(data_in_q[44]) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_43_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_1), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_51812_i), + .Q(data_in_q[43]) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_42_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_1), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_51810_i), + .Q(data_in_q[42]) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_41_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_1), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_51808_i), + .Q(data_in_q[41]) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_40_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_1), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_51806_i), + .Q(data_in_q[40]) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_39_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_1), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_51804_i), + .Q(data_in_q[39]) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_38_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_1), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_51802_i), + .Q(data_in_q[38]) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_37_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_1), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_51800_i), + .Q(data_in_q[37]) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_36_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_1), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_51798_i), + .Q(data_in_q[36]) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_35_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_1), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_51796_i), + .Q(data_in_q[35]) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_34_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_1), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_51794_i), + .Q(data_in_q[34]) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_33_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_1), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_51792_i), + .Q(data_in_q[33]) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_32_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_1), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_51790_i), + .Q(data_in_q[32]) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_31_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_1), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_52366_i), + .Q(data_in_q[31]) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_30_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_1), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_52368_i), + .Q(data_in_q[30]) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_29_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_1), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_52364_i), + .Q(data_in_q[29]) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_28_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_1), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_51788_i), + .Q(data_in_q[28]) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_27_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_1), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_51786_i), + .Q(data_in_q[27]) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_26_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_1), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_51784_i), + .Q(data_in_q[26]) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_25_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_1), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_51782_i), + .Q(data_in_q[25]) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_24_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_1), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_51780_i), + .Q(data_in_q[24]) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_23_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_1), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_51778_i), + .Q(data_in_q[23]) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_22_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_1), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_51776_i), + .Q(data_in_q[22]) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_21_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_1), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_51774_i), + .Q(data_in_q[21]) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_20_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_1), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_51772_i), + .Q(data_in_q[20]) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_19_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_1), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_51770_i), + .Q(data_in_q[19]) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_18_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_1), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_51768_i), + .Q(data_in_q[18]) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_17_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_1), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_51766_i), + .Q(data_in_q[17]) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_16_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_1), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_51764_i), + .Q(data_in_q[16]) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_15_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_1), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_51762_i), + .Q(data_in_q[15]) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_14_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_1), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_51760_i), + .Q(data_in_q[14]) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_13_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_1), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_51758_i), + .Q(data_in_q[13]) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_12_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_1), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_51756_i), + .Q(data_in_q[12]) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_11_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_1), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_51754_i), + .Q(data_in_q[11]) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_10_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_1), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_51752_i), + .Q(data_in_q[10]) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_9_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_1), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_51750_i), + .Q(data_in_q[9]) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_8_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_1), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_51748_i), + .Q(data_in_q[8]) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_7_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_1), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_51746_i), + .Q(data_in_q[7]) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_6_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_1), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_51744_i), + .Q(data_in_q[6]) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_5_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_1), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_51742_i), + .Q(data_in_q[5]) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_4_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_1), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_51740_i), + .Q(data_in_q[4]) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_3_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_1), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_51738_i), + .Q(data_in_q[3]) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_2_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_1), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_51736_i), + .Q(data_in_q[2]) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_1_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_0), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_51734_i), + .Q(data_in_q[1]) + ); + FDE com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_data_in_q_0_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_tlp_komp_tx_pipe_full_0_0), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_N_51732_i), + .Q(data_in_q[0]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_1_23_.INIT = 4'h6; + LUT2 com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_1_23_ ( + .I0(data_in_q[15]), + .I1(data_in_q[17]), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_23__2277) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_0_20_.INIT = 4'h6; + LUT2 com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_0_20_ ( + .I0(data_in_q[39]), + .I1(data_in_q[55]), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_0_20__2272) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_0_24_.INIT = 4'h6; + LUT2 com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_0_24_ ( + .I0(data_in_q[20]), + .I1(data_in_q[47]), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_0_24__2271) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_0_13_.INIT = 4'h6; + LUT2 com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_0_13_ ( + .I0(data_in_q[5]), + .I1(data_in_q[28]), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_0_13__2284) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_1_18_.INIT = 16'h6996; + LUT4 com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_1_18_ ( + .I0(data_in_q[21]), + .I1(data_in_q[26]), + .I2(data_in_q[34]), + .I3(data_in_q[50]), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_18__2303) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_3_25_.INIT = 16'h6996; + LUT4 com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_3_25_ ( + .I0(data_in_q[11]), + .I1(data_in_q[19]), + .I2(data_in_q[38]), + .I3(data_in_q[58]), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_3_25__2274) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_1_31_.INIT = 4'h6; + LUT2 com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_1_31_ ( + .I0(N_11881_1), + .I1(G_477_678), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_1_31__2288) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_2_10_.INIT = 16'h6996; + LUT4 com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_2_10_ ( + .I0(data_in_q[14]), + .I1(data_in_q[16]), + .I2(data_in_q[28]), + .I3(data_in_q[33]), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_2_10__2275) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_2_2_.INIT = 16'h6996; + LUT4 com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_2_2_ ( + .I0(data_in_q[8]), + .I1(data_in_q[18]), + .I2(data_in_q[37]), + .I3(data_in_q[44]), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_2_2__2276) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_1_6_.INIT = 8'h96; + LUT3 com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_1_6_ ( + .I0(data_in_q[11]), + .I1(data_in_q[25]), + .I2(data_in_q[42]), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_1_6__2278) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_2_15_.INIT = 16'h6996; + LUT4 com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_2_15_ ( + .I0(data_in_q[12]), + .I1(data_in_q[16]), + .I2(data_in_q[34]), + .I3(data_in_q[49]), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_2_15__2279) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_2_17_.INIT = 16'h6996; + LUT4 com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_2_17_ ( + .I0(data_in_q[14]), + .I1(data_in_q[22]), + .I2(data_in_q[23]), + .I3(data_in_q[27]), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_2_17__2308) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_2_14_.INIT = 16'h6996; + LUT4 com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_2_14_ ( + .I0(data_in_q[17]), + .I1(data_in_q[26]), + .I2(data_in_q[32]), + .I3(data_in_q[44]), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_2_14__2280) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_2_30_.INIT = 8'h96; + LUT3 com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_2_30_ ( + .I0(data_in_q[23]), + .I1(data_in_q[45]), + .I2(data_in_q[61]), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_2_30__2282) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_1_9_.INIT = 8'h96; + LUT3 com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_1_9_ ( + .I0(data_in_q[13]), + .I1(data_in_q[35]), + .I2(data_in_q[41]), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_1_9__2283) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_1_2_.INIT = 4'h6; + LUT2 com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_1_2_ ( + .I0(N_129), + .I1(N_191), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_2__2334) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_1_13_.INIT = 4'h6; + LUT2 com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_1_13_ ( + .I0(N_162), + .I1(data_in_q[31]), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_13__2314) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_1_16_.INIT = 4'h6; + LUT2 com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_1_16_ ( + .I0(N_147), + .I1(data_in_q[56]), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_16__2310) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_1_17_.INIT = 4'h6; + LUT2 com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_1_17_ ( + .I0(N_137), + .I1(G_228_585), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_17__2316) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_1_26_.INIT = 4'h6; + LUT2 com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_1_26_ ( + .I0(N_132), + .I1(data_in_q[41]), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_26__2294) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_1_20_.INIT = 16'h6996; + LUT4 com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_1_20_ ( + .I0(N_132), + .I1(data_in_q[8]), + .I2(data_in_q[16]), + .I3(data_in_q[41]), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_20__2326) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_1_1_.INIT = 16'h6996; + LUT4 com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_1_1_ ( + .I0(N_11929_2), + .I1(data_in_q[46]), + .I2(data_in_q[47]), + .I3(data_in_q[49]), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_1__2298) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_1_24_.INIT = 16'h6996; + LUT4 com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_1_24_ ( + .I0(G_111_384), + .I1(data_in_q[17]), + .I2(data_in_q[36]), + .I3(data_in_q[37]), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_24__2296) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_2_18_.INIT = 4'h6; + LUT2 com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_2_18_ ( + .I0(G_285_550), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_18__2303), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_2_18__2306) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_1_3_.INIT = 8'h96; + LUT3 com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_1_3_ ( + .I0(G_207_583), + .I1(G_395_685), + .I2(data_in_q[53]), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_1_3__2332) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_5_25_.INIT = 4'h6; + LUT2_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_5_25_ ( + .I0(N_137), + .I1(N_157), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_5_25__2273) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_4_17_.INIT = 4'h6; + LUT2 com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_4_17_ ( + .I0(G_150_440), + .I1(G_235_617), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_4_17__2307) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_2_16_.INIT = 16'h6996; + LUT4 com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_2_16_ ( + .I0(G_286_551), + .I1(G_294_698), + .I2(data_in_q[21]), + .I3(data_in_q[48]), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_2_16__2309) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_2_22_.INIT = 16'h6996; + LUT4 com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_2_22_ ( + .I0(G_398_619), + .I1(data_in_q[34]), + .I2(data_in_q[35]), + .I3(data_in_q[37]), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_2_22__2300) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_2_8_.INIT = 16'h6996; + LUT4 com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_2_8_ ( + .I0(G_166_590), + .I1(data_in_q[10]), + .I2(data_in_q[50]), + .I3(data_in_q[63]), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_2_8__2323) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_2_26_.INIT = 16'h6996; + LUT4 com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_2_26_ ( + .I0(N_11891_1), + .I1(G_395_685), + .I2(data_in_q[6]), + .I3(data_in_q[18]), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_2_26__2286) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_2_29_.INIT = 16'h6996; + LUT4 com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_2_29_ ( + .I0(N_194), + .I1(data_in_q[34]), + .I2(data_in_q[42]), + .I3(data_in_q[51]), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_2_29__2281) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_3_24_.INIT = 16'h6996; + LUT4 com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_3_24_ ( + .I0(N_159), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_0_24__2271), + .I2(data_in_q[39]), + .I3(data_in_q[40]), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_3_24__2295) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_3_27_.INIT = 16'h6996; + LUT4 com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_3_27_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_2_27__2340), + .I1(data_in_q[4]), + .I2(data_in_q[42]), + .I3(data_in_q[53]), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_3_27__2293) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_4_27_.INIT = 4'h6; + LUT2 com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_4_27_ ( + .I0(N_193), + .I1(G_233_586), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_4_27__2292) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_3_9_.INIT = 16'h6996; + LUT4 com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_3_9_ ( + .I0(N_135), + .I1(N_11876_1), + .I2(data_in_q[34]), + .I3(data_in_q[61]), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_3_9__2321) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_2_0_.INIT = 16'h6996; + LUT4 com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_2_0_ ( + .I0(N_237_1), + .I1(G_482_480), + .I2(data_in_q[37]), + .I3(data_in_q[48]), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_2_0__2339) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_3_0_.INIT = 16'h6996; + LUT4 com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_3_0_ ( + .I0(N_134), + .I1(data_in_q[10]), + .I2(data_in_q[50]), + .I3(data_in_q[63]), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_3_0__2338) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_4_0_.INIT = 16'h6996; + LUT4 com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_4_0_ ( + .I0(G_151_587), + .I1(N_11876_1), + .I2(data_in_q[34]), + .I3(data_in_q[61]), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_4_0__2337) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_2_11_.INIT = 4'h6; + LUT2_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_2_11_ ( + .I0(N_157), + .I1(G_166_590), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_2_11__2285) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_1_12_.INIT = 8'h96; + LUT3 com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_1_12_ ( + .I0(G_255_576), + .I1(G_272_700), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_23__2277), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_1_12__2315) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_4_18_.INIT = 16'h6996; + LUT4_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_4_18_ ( + .I0(G_151_587), + .I1(G_295_554), + .I2(data_in_q[23]), + .I3(data_in_q[59]), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_4_18__2305) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_6_3_.INIT = 16'h6996; + LUT4_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_6_3_ ( + .I0(N_135), + .I1(N_165), + .I2(N_190), + .I3(G_204_581), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_6_3__2331) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_4_20_.INIT = 16'h6996; + LUT4 com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_4_20_ ( + .I0(N_146), + .I1(G_294_698), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_0_20__2272), + .I3(data_in_q[61]), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_4_20__2302) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_7_25_.INIT = 16'h6996; + LUT4_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_7_25_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_3_25__2274), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_5_25__2273), + .I2(data_in_q[48]), + .I3(data_in_q[61]), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_7[25]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_3_1_.INIT = 16'h6996; + LUT4_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_3_1_ ( + .I0(G_207_583), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_1__2298), + .I2(data_in_q[12]), + .I3(data_in_q[33]), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_3_1__2336) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_4_1_.INIT = 16'h6996; + LUT4 com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_4_1_ ( + .I0(N_114), + .I1(N_191), + .I2(N_194), + .I3(data_in_q[11]), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_4_1__2335) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_4_31_.INIT = 16'h6996; + LUT4_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_4_31_ ( + .I0(N_163), + .I1(N_165_1), + .I2(G_164_616), + .I3(data_in_q[47]), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_4_31__2287) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_6_10_.INIT = 16'h6996; + LUT4 com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_6_10_ ( + .I0(N_114), + .I1(G_272_700), + .I2(G_286_551), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_2_10__2275), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_6_10__2319) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_3_21_.INIT = 16'h6996; + LUT4 com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_3_21_ ( + .I0(N_137), + .I1(N_162), + .I2(G_293_699), + .I3(data_in_q[34]), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_3_21__2301) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_4_7_.INIT = 16'h6996; + LUT4 com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_4_7_ ( + .I0(G_111_384), + .I1(G_295_554), + .I2(G_475_481), + .I3(data_in_q[54]), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_4_7__2325) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_5_7_.INIT = 16'h6996; + LUT4_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_5_7_ ( + .I0(N_117), + .I1(N_193), + .I2(G_149_379), + .I3(G_271_618), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_5_7__2324) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_6_2_.INIT = 16'h6996; + LUT4_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_6_2_ ( + .I0(N_172), + .I1(N_237), + .I2(N_11888_1), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_2_2__2276), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_6_2__2333) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_2_19_.INIT = 16'h6996; + LUT4_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_2_19_ ( + .I0(N_134), + .I1(N_148), + .I2(N_212_1), + .I3(G_236_575), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_2_19__2304) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_3_23_.INIT = 16'h6996; + LUT4_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_3_23_ ( + .I0(N_202), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_2__2334), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_23__2277), + .I3(data_in_q[13]), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_3_23__2297) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_5_6_.INIT = 16'h6996; + LUT4 com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_5_6_ ( + .I0(N_148), + .I1(N_11871_1), + .I2(G_256_577), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_1_6__2278), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_5_6__2327) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_5_15_.INIT = 16'h6996; + LUT4 com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_5_15_ ( + .I0(N_193), + .I1(G_164_616), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_2_15__2279), + .I3(data_in_q[18]), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_5_15__2311) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_4_22_.INIT = 8'h96; + LUT3 com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_4_22_ ( + .I0(N_133), + .I1(N_163), + .I2(G_256_577), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_4_22__2299) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_3_8_.INIT = 16'h6996; + LUT4_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_3_8_ ( + .I0(N_11872_1), + .I1(G_234_615), + .I2(G_271_618), + .I3(G_293_699), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_3_8__2322) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_5_14_.INIT = 16'h6996; + LUT4_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_5_14_ ( + .I0(N_165), + .I1(N_173), + .I2(G_398_619), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_2_14__2280), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_5_14__2312) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_3_29_.INIT = 4'h6; + LUT2_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_3_29_ ( + .I0(G_159_588), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_2_29__2281), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_3_29__2290) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_5_30_.INIT = 16'h6996; + LUT4_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_5_30_ ( + .I0(G_457_430), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_2_30__2282), + .I2(data_in_q[24]), + .I3(data_in_q[42]), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_5_30__2289) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_4_9_.INIT = 16'h6996; + LUT4 com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_4_9_ ( + .I0(G_287_99), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_1_9__2283), + .I2(data_in_q[9]), + .I3(data_in_q[36]), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_4_9__2320) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_3_4_.INIT = 16'h6996; + LUT4 com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_3_4_ ( + .I0(N_189), + .I1(G_235_617), + .I2(G_255_576), + .I3(data_in_q[6]), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_3_4__2330) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_4_4_.INIT = 16'h6996; + LUT4_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_4_4_ ( + .I0(N_174), + .I1(G_149_379), + .I2(G_164_616), + .I3(data_in_q[18]), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_4_4__2329) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_3_13_.INIT = 16'h6996; + LUT4 com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_3_13_ ( + .I0(N_136), + .I1(N_174_1), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_0_13__2284), + .I3(data_in_q[54]), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_3_13__2313) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_4_11_.INIT = 16'h6996; + LUT4 com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_4_11_ ( + .I0(G_112_381), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_2_11__2285), + .I2(data_in_q[20]), + .I3(data_in_q[27]), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_4_11__2318) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_3_28_.INIT = 16'h6996; + LUT4_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_3_28_ ( + .I0(N_163), + .I1(N_199_1), + .I2(G_482_480), + .I3(data_in_q[5]), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_3_28__2291) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_4_5_.INIT = 16'h6996; + LUT4_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_4_5_ ( + .I0(N_147), + .I1(N_157), + .I2(G_161_589), + .I3(G_454_436), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_4_5__2328) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_7_26_.INIT = 16'h6996; + LUT4_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_7_26_ ( + .I0(N_130), + .I1(G_285_550), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_13__2314), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_2_26__2286), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_7[26]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_6_11_.INIT = 8'h96; + LUT3_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_6_11_ ( + .I0(N_12054_1), + .I1(G_426_88), + .I2(data_in_q[48]), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_6_11__2317) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_31_.INIT = 16'h6996; + LUT4_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_31_ ( + .I0(N_200), + .I1(G_467_442), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_1_31__2288), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_4_31__2287), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_d64_c[31]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_30_.INIT = 16'h6996; + LUT4_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_30_ ( + .I0(N_159), + .I1(G_425_382), + .I2(G_475_481), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_5_30__2289), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_d64_c[30]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_29_.INIT = 16'h6996; + LUT4_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_29_ ( + .I0(N_12084_1), + .I1(G_468_441), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_26__2294), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_3_29__2290), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_d64_c[29]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_28_.INIT = 16'h6996; + LUT4_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_28_ ( + .I0(N_157), + .I1(G_236_575), + .I2(G_453_385), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_3_28__2291), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_d64_c[28]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_27_.INIT = 16'h6996; + LUT4_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_27_ ( + .I0(G_397_380), + .I1(G_407_421), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_3_27__2293), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_4_27__2292), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_d64_c[27]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_26_.INIT = 16'h6996; + LUT4_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_26_ ( + .I0(G_161_589), + .I1(G_165_437), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_26__2294), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_7[26]), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_d64_c[26]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_25_.INIT = 16'h6996; + LUT4_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_25_ ( + .I0(N_165), + .I1(G_159_588), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_24__2296), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_7[25]), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_d64_c[25]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_24_.INIT = 16'h6996; + LUT4_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_24_ ( + .I0(G_392_378), + .I1(G_454_436), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_24__2296), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_3_24__2295), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_d64_c[24]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_23_.INIT = 16'h6996; + LUT4_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_23_ ( + .I0(G_204_581), + .I1(G_407_421), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_1__2298), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_3_23__2297), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_d64_c[23]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_22_.INIT = 16'h6996; + LUT4_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_22_ ( + .I0(G_461_438), + .I1(G_514_428), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_2_22__2300), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_4_22__2299), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_d64_c[22]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_21_.INIT = 16'h6996; + LUT4_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_21_ ( + .I0(N_200), + .I1(G_233_586), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_16__2310), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_3_21__2301), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_d64_c[21]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_20_.INIT = 16'h6996; + LUT4_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_20_ ( + .I0(G_205_582), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_18__2303), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_20__2326), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_4_20__2302), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_d64_c[20]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_19_.INIT = 16'h6996; + LUT4_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_19_ ( + .I0(N_191), + .I1(N_12054_1), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_2_19__2304), + .I3(data_in_q[11]), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_d64_c[19]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_18_.INIT = 16'h6996; + LUT4_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_18_ ( + .I0(N_172), + .I1(N_190), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_2_18__2306), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_4_18__2305), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_d64_c[18]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_17_.INIT = 16'h6996; + LUT4_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_17_ ( + .I0(G_205_582), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_17__2316), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_2_17__2308), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_4_17__2307), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_d64_c[17]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_16_.INIT = 16'h6996; + LUT4_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_16_ ( + .I0(G_457_430), + .I1(G_461_438), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_16__2310), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_2_16__2309), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_d64_c[16]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_15_.INIT = 16'h6996; + LUT4_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_15_ ( + .I0(N_165), + .I1(N_212), + .I2(G_522_376), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_5_15__2311), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_d64_c[15]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_14_.INIT = 8'h96; + LUT3_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_14_ ( + .I0(G_425_382), + .I1(G_427_422), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_5_14__2312), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_d64_c[14]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_13_.INIT = 16'h6996; + LUT4_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_13_ ( + .I0(G_392_378), + .I1(G_468_441), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_13__2314), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_3_13__2313), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_d64_c[13]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_12_.INIT = 16'h6996; + LUT4_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_12_ ( + .I0(N_212), + .I1(G_453_385), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_17__2316), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_1_12__2315), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_d64_c[12]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_11_.INIT = 16'h6996; + LUT4_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_11_ ( + .I0(N_146), + .I1(N_237), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_4_11__2318), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_6_11__2317), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_d64_c[11]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_10_.INIT = 16'h6996; + LUT4_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_10_ ( + .I0(N_174), + .I1(G_161_589), + .I2(G_514_428), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_6_10__2319), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_d64_c[10]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_9_.INIT = 16'h6996; + LUT4_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_9_ ( + .I0(G_394_443), + .I1(G_397_380), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_3_9__2321), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_4_9__2320), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_d64_c[9]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_8_.INIT = 16'h6996; + LUT4_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_8_ ( + .I0(G_394_443), + .I1(G_467_442), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_2_8__2323), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_3_8__2322), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_d64_c[8]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_7_.INIT = 8'h96; + LUT3_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_7_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_20__2326), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_4_7__2325), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_5_7__2324), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_d64_c[7]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_6_.INIT = 16'h6996; + LUT4_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_6_ ( + .I0(N_173), + .I1(G_228_585), + .I2(G_522_376), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_5_6__2327), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_d64_c[6]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_5_.INIT = 16'h6996; + LUT4_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_5_ ( + .I0(N_202), + .I1(G_287_99), + .I2(G_427_422), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_4_5__2328), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_d64_c[5]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_4_.INIT = 16'h6996; + LUT4_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_4_ ( + .I0(N_12054_1), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_3_4__2330), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_4_4__2329), + .I3(data_in_q[48]), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_d64_c[4]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_3_.INIT = 16'h6996; + LUT4_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_3_ ( + .I0(G_112_381), + .I1(G_234_615), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_1_3__2332), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_6_3__2331), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_d64_c[3]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_2_.INIT = 16'h6996; + LUT4_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_2_ ( + .I0(N_136), + .I1(G_150_440), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_2__2334), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_6_2__2333), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_d64_c[2]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_1_.INIT = 16'h6996; + LUT4_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_1_ ( + .I0(N_147), + .I1(G_151_587), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_3_1__2336), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_4_1__2335), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_d64_c[1]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_0_.INIT = 16'h6996; + LUT4_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_0_ ( + .I0(G_426_88), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_2_0__2339), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_3_0__2338), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_4_0__2337), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_d64_c[0]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_2_27_.INIT = 8'h96; + LUT3_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_2_27_ ( + .I0(G_477_678), + .I1(data_in_q[63]), + .I2(data_in_q[48]), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_data_d64_c_1_2_27__2340) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c16_new_c16_1_1_25_.INIT = 4'h6; + LUT2 com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c16_new_c16_1_1_25_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[9]), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[18]), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_new_c32_d16_1_25_) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c16_new_c16_1_1_30_.INIT = 16'h6996; + LUT4 com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c16_new_c16_1_1_30_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[14]), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[20]), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[24]), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_d64_c_q_30__2230), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_new_c16_1_1_30_) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c16_new_c16_1_1_26_.INIT = 16'h6996; + LUT4 com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c16_new_c16_1_1_26_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[10]), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[19]), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[20]), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_d64_c_q_26__2234), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_new_c16_1_1_26_) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c16_new_c16_1_2_24_.INIT = 16'h6996; + LUT4 com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c16_new_c16_1_2_24_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[8]), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[17]), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[18]), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_d64_c_q_24__2236), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_new_c16_1_2[24]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c16_new_c16_1_1_29_.INIT = 8'h96; + LUT3_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c16_new_c16_1_1_29_ ( + .I0(N_12040), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[23]), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_d64_c_q_29__2231), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_new_c16_1_1_29_) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c16_new_c16_1_1_31_.INIT = 16'h6996; + LUT4 com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c16_new_c16_1_1_31_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[15]), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[21]), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[25]), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_d64_c_q_31__2229), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_new_c16_1_1_31_) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c16_new_c16_1_1_4_.INIT = 8'h96; + LUT3_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c16_new_c16_1_1_4_ ( + .I0(N_12040), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[24]), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_d64_c_q_4__2255), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_new_c16_1_1_4_) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c16_new_c16_1_1_0_8_.INIT = 16'h6996; + LUT4 com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c16_new_c16_1_1_0_8_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[19]), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[20]), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[27]), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[28]), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_new_c16_1_1_8_) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c16_new_c16_1_0_13_.INIT = 8'h96; + LUT3 com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c16_new_c16_1_0_13_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[17]), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[21]), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_d64_c_q_13__2247), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_new_c16_1_0[13]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c16_new_c16_1_1_23_.INIT = 16'h6996; + LUT4 com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c16_new_c16_1_1_23_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[7]), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[16]), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[31]), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_d64_c_q_23__2237), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_new_c16_1_1_23_) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c16_new_c16_1_1_3_.INIT = 8'h96; + LUT3 com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c16_new_c16_1_1_3_ ( + .I0(N_44), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[18]), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[26]), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_new_c32_d16_1_3_) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c16_new_c16_1_1_0_16_.INIT = 8'h96; + LUT3_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c16_new_c16_1_1_0_16_ ( + .I0(N_100), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[29]), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_d64_c_q_16__2244), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_new_c16_1_1_16_) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c16_new_c16_1_1_14_.INIT = 16'h6996; + LUT4_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c16_new_c16_1_1_14_ ( + .I0(N_73), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[19]), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[20]), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_d64_c_q_14__2246), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_new_c16_1_1_14_) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c16_new_c16_1_1_5_.INIT = 8'h96; + LUT3 com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c16_new_c16_1_1_5_ ( + .I0(N_45), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[21]), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[16]), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_new_c32_d16_1_5_) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c48_new_c48_1_0_14_.INIT = 4'h6; + LUT2 com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c48_new_c48_1_0_14_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[10]), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_d64_c_q_14__2246), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_new_c48_1_0_14_) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c48_new_c48_1_2_14_.INIT = 16'h6996; + LUT4 com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c48_new_c48_1_2_14_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[1]), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[3]), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[4]), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[16]), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_new_c48_1_2_14_) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c48_new_c48_1_2_13_.INIT = 16'h6996; + LUT4 com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c48_new_c48_1_2_13_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[3]), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[6]), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[9]), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[16]), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_new_c48_1_2_13_) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c48_new_c48_1_2_17_.INIT = 16'h6996; + LUT4 com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c48_new_c48_1_2_17_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[14]), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[15]), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[17]), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_d64_c_q_17__2243), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_new_c48_1_2_17_) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c48_new_c48_1_1_15_.INIT = 8'h96; + LUT3 com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c48_new_c48_1_1_15_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[5]), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[28]), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_d64_c_q_15__2245), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_new_c48_1_1_15_) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c48_new_c48_1_1_16_.INIT = 8'h96; + LUT3 com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c48_new_c48_1_1_16_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[8]), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[19]), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_d64_c_q_16__2244), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_new_c48_1_1_16_) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c48_new_c48_1_2_16_.INIT = 8'h96; + LUT3_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c48_new_c48_1_2_16_ ( + .I0(N_102), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[1]), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[5]), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_new_c48_1_2_16_) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c48_new_c48_1_2_27_.INIT = 16'h6996; + LUT4 com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c48_new_c48_1_2_27_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[5]), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[13]), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[29]), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_d64_c_q_27__2233), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_new_c48_1_2_27_) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c48_new_c48_1_1_10_.INIT = 16'h6996; + LUT4 com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c48_new_c48_1_1_10_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[3]), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[12]), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[13]), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_d64_c_q_10__2250), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_new_c48_1_1_10_) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c48_new_c48_1_0_21_.INIT = 8'h96; + LUT3_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c48_new_c48_1_0_21_ ( + .I0(N_11962), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[21]), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_d64_c_q_21__2239), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_new_c48_1_0_21_) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c48_new_c48_1_1_1_.INIT = 8'h96; + LUT3_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c48_new_c48_1_1_1_ ( + .I0(N_12095), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[1]), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_d64_c_q_1__2257), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_new_c48_1_1_1_) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c48_new_c48_1_1_6_.INIT = 8'h96; + LUT3 com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c48_new_c48_1_1_6_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[26]), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[29]), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_d64_c_q_6__2254), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_new_c48_1_1_6_) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c48_new_c48_1_2_20_.INIT = 16'h6996; + LUT4 com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c48_new_c48_1_2_20_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[1]), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[7]), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[14]), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_d64_c_q_20__2240), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_new_c48_1_2_20_) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c48_new_c48_1_1_19_.INIT = 16'h6996; + LUT4 com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c48_new_c48_1_1_19_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[4]), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[13]), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[19]), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_d64_c_q_19__2241), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_new_c48_1_1_19_) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c48_new_c48_1_0_30_.INIT = 8'h96; + LUT3 com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c48_new_c48_1_0_30_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[6]), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[12]), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_d64_c_q_30__2230), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c48_new_c48_1_0[30]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c48_new_c48_1_1_30_.INIT = 8'h96; + LUT3_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c48_new_c48_1_1_30_ ( + .I0(N_12041), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[10]), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[13]), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c48_new_c48_1_1_30__2344) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c48_new_c48_1_2_28_.INIT = 16'h6996; + LUT4 com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c48_new_c48_1_2_28_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[4]), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[9]), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[27]), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_d64_c_q_28__2232), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_new_c48_1_2_28_) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c48_new_c48_1_1_7_.INIT = 16'h6996; + LUT4 com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c48_new_c48_1_1_7_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[0]), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[6]), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[9]), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_d64_c_q_7__2253), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_new_c48_1_1_7_) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c48_new_c48_1_1_0_18_.INIT = 16'h6996; + LUT4 com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c48_new_c48_1_1_0_18_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[7]), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[10]), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[15]), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_d64_c_q_18__2242), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_new_c48_1_1_18_) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c48_new_c48_1_1_25_.INIT = 16'h6996; + LUT4_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c48_new_c48_1_1_25_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[6]), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[20]), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[24]), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_d64_c_q_25__2235), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c48_new_c48_1_1_25__2341) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c48_new_c48_1_1_3_.INIT = 8'h96; + LUT3 com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c48_new_c48_1_1_3_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[15]), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[20]), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_d64_c_q_3__2256), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_new_c48_1_1_3_) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c48_new_c48_1_1_4_.INIT = 16'h6996; + LUT4 com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c48_new_c48_1_1_4_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[8]), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[14]), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[30]), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_d64_c_q_4__2255), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_new_c48_1_1_4_) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c48_new_c48_1_1_26_.INIT = 8'h96; + LUT3 com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c48_new_c48_1_1_26_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[25]), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[26]), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_d64_c_q_26__2234), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_new_c48_1_1_26_) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c48_new_c48_1_1_29_.INIT = 16'h6996; + LUT4 com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c48_new_c48_1_1_29_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[7]), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[10]), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[11]), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_d64_c_q_29__2231), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c48_new_c48_1_1_29__2342) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c48_new_c48_1_1_0_.INIT = 16'h6996; + LUT4_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c48_new_c48_1_1_0_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[8]), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[10]), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[13]), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_d64_c_q_0__2258), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c48_new_c48_1_1_0__2343) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c48_new_c48_1_1_23_.INIT = 4'h6; + LUT2 com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c48_new_c48_1_1_23_ ( + .I0(N_109), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[11]), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_new_c32_d48_1[23]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c48_new_c48_1_3_15_.INIT = 16'h6996; + LUT4_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c48_new_c48_1_3_15_ ( + .I0(N_83), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[14]), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[18]), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[29]), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_new_c48_1_3_15_) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c48_new_c48_1_3_22_.INIT = 16'h6996; + LUT4_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c48_new_c48_1_3_22_ ( + .I0(N_93), + .I1(N_11855), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[0]), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_d64_c_q_22__2238), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_new_c48_1_3_22_) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c48_new_c48_1_0_9_.INIT = 4'h6; + LUT2_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c48_new_c48_1_0_9_ ( + .I0(N_12043), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_d64_c_q_9__2251), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_new_c48_1_0_9_) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c48_new_c48_1_3_7_.INIT = 16'h6996; + LUT4_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c48_new_c48_1_3_7_ ( + .I0(N_71), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[13]), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[25]), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[29]), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_new_c48_1_3_7_) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c48_new_c48_1_1_11_.INIT = 16'h6996; + LUT4_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c48_new_c48_1_1_11_ ( + .I0(N_109), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[12]), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[27]), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_d64_c_q_11__2249), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_new_c48_1_1_11_) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c48_new_c48_1_1_5_.INIT = 16'h6996; + LUT4_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c48_new_c48_1_1_5_ ( + .I0(N_12099), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[21]), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[28]), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[30]), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_new_c48_1_1_5_) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c48_new_c48_1_2_25_.INIT = 8'h96; + LUT3_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c48_new_c48_1_2_25_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[3]), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[13]), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c48_new_c48_1_1_25__2341), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_new_c48_1_2_25_) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c48_new_c48_1_1_0_2_.INIT = 16'h6996; + LUT4_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c48_new_c48_1_1_0_2_ ( + .I0(N_105), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[8]), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[14]), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[19]), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_new_c48_1_1_2_) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c48_new_c48_1_2_29_.INIT = 4'h6; + LUT2 com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c48_new_c48_1_2_29_ ( + .I0(N_143), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c48_new_c48_1_1_29__2342), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_new_c48_1_2_29_) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c48_new_c48_1_2_0_.INIT = 16'h6996; + LUT4 com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c48_new_c48_1_2_0_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[14]), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[18]), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[29]), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c48_new_c48_1_1_0__2343), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_new_c48_1_2_0_) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c48_new_c48_1_1_31_.INIT = 8'h96; + LUT3 com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c48_new_c48_1_1_31_ ( + .I0(N_82), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_c32_d64_q[20]), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_d64_c_q_31__2229), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_new_c48_1_1_31_) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c48_new_c48_1_1_0_23_.INIT = 8'h96; + LUT3 com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c48_new_c48_1_1_0_23_ ( + .I0(N_70), + .I1(N_12042), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_d64_c_q_23__2237), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_new_c48_1_1_23_) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c48_new_c48_1_30_.INIT = 16'h6996; + LUT4_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c48_new_c48_1_30_ ( + .I0(N_103), + .I1(N_151), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c48_new_c48_1_0[30]), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c48_new_c48_1_1_30__2344), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_new_c32_d48[30]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c64_new_c64_1_0_16_.INIT = 4'h6; + LUT2 com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c64_new_c64_1_0_16_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crc32_d64_feedback[24]), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_d64_c_q_16__2244), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c64_new_c64_1_0_16__2346) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c64_new_c64_1_0_25_.INIT = 4'h6; + LUT2_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c64_new_c64_1_0_25_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crc32_d64_feedback[4]), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_d64_c_q_25__2235), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c64_new_c64_1_0_25__2345) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c64_new_c64_1_1_4_.INIT = 8'h96; + LUT3 com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c64_new_c64_1_1_4_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crc32_d64_feedback[7]), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crc32_d64_feedback[18]), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crc32_d64_feedback[31]), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c64_new_c32_d64_1_4_) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c64_new_c64_1_1_17_.INIT = 8'h96; + LUT3 com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c64_new_c64_1_1_17_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crc32_d64_feedback[17]), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crc32_d64_feedback[26]), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_d64_c_q_17__2243), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c64_new_c64_1_1_17__2347) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c64_new_c64_1_2_19_.INIT = 16'h6996; + LUT4 com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c64_new_c64_1_2_19_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crc32_d64_feedback[1]), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crc32_d64_feedback[19]), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crc32_d64_feedback[28]), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_d64_c_q_19__2241), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c64_new_c64_1_2_19__2348) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c64_new_c64_1_1_20_.INIT = 8'h96; + LUT3 com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c64_new_c64_1_1_20_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crc32_d64_feedback[28]), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crc32_d64_feedback[29]), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_d64_c_q_20__2240), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c64_new_c64_1_1_20__2349) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c64_new_c64_1_1_21_.INIT = 8'h96; + LUT3 com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c64_new_c64_1_1_21_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crc32_d64_feedback[5]), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crc32_d64_feedback[30]), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_d64_c_q_21__2239), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c64_new_c64_1_1_21__2350) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c64_new_c64_1_1_29_.INIT = 8'h96; + LUT3 com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c64_new_c64_1_1_29_ ( + .I0(N_12104), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crc32_d64_feedback[31]), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_d64_c_q_29__2231), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c64_new_c64_1_1_29__2352) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c64_new_c64_1_1_31_.INIT = 8'h96; + LUT3 com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c64_new_c64_1_1_31_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crc32_d64_feedback[14]), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crc32_d64_feedback[21]), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_d64_c_q_31__2229), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c64_new_c64_1_1_31__2351) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c64_new_c64_1_2_22_.INIT = 16'h6996; + LUT4 com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c64_new_c64_1_2_22_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crc32_d64_feedback[4]), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crc32_d64_feedback[5]), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crc32_d64_feedback[11]), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_d64_c_q_22__2238), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c64_new_c64_1_2_22__2370) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c64_new_c64_1_0_23_.INIT = 8'h96; + LUT3 com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c64_new_c64_1_0_23_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crc32_d64_feedback[2]), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crc32_d64_feedback[6]), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_d64_c_q_23__2237), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c64_new_c64_1_0_23__2371) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c64_new_c64_1_1_0_6_.INIT = 16'h6996; + LUT4 com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c64_new_c64_1_1_0_6_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crc32_d64_feedback[10]), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crc32_d64_feedback[11]), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crc32_d64_feedback[15]), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_d64_c_q_6__2254), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c64_new_c64_1_1_6__2360) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c64_new_c64_1_1_18_.INIT = 16'h6996; + LUT4 com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c64_new_c64_1_1_18_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crc32_d64_feedback[14]), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crc32_d64_feedback[17]), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crc32_d64_feedback[27]), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_d64_c_q_18__2242), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c64_new_c64_1_1_18__2354) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c64_new_c64_1_1_0_2_.INIT = 8'h96; + LUT3 com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c64_new_c64_1_1_0_2_ ( + .I0(N_12064), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crc32_d64_feedback[12]), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_d64_c_q_2__631), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c64_new_c64_1_1_2__2353) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c64_new_c64_1_1_10_.INIT = 8'h96; + LUT3 com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c64_new_c64_1_1_10_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crc32_d64_feedback[18]), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crc32_d64_feedback[31]), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_d64_c_q_10__2250), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c64_new_c64_1_1_10__2364) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c64_new_c64_1_1_28_.INIT = 8'h96; + LUT3 com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c64_new_c64_1_1_28_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crc32_d64_feedback[24]), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crc32_d64_feedback[30]), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_d64_c_q_28__2232), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c64_new_c64_1_1_28__2375) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c64_new_c64_1_2_7_.INIT = 16'h6996; + LUT4 com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c64_new_c64_1_2_7_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crc32_d64_feedback[2]), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crc32_d64_feedback[9]), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crc32_d64_feedback[15]), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_d64_c_q_7__2253), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c64_new_c64_1_2_7__2361) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c64_new_c64_1_1_24_.INIT = 8'h96; + LUT3 com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c64_new_c64_1_1_24_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crc32_d64_feedback[16]), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crc32_d64_feedback[23]), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_d64_c_q_24__2236), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c64_new_c64_1_1_24__2372) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c64_new_c64_1_1_0_14_.INIT = 8'h96; + LUT3 com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c64_new_c64_1_1_0_14_ ( + .I0(N_11939_1), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crc32_d64_feedback[11]), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_d64_c_q_14__2246), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c64_new_c64_1_1_14__2368) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c64_new_c64_1_2_5_.INIT = 16'h6996; + LUT4 com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c64_new_c64_1_2_5_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crc32_d64_feedback[5]), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crc32_d64_feedback[8]), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crc32_d64_feedback[21]), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_d64_c_q_5__632), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c64_new_c64_1_2_5__2359) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c64_new_c64_1_1_15_.INIT = 8'h96; + LUT3 com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c64_new_c64_1_1_15_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crc32_d64_feedback[23]), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crc32_d64_feedback[25]), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_d64_c_q_15__2245), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c64_new_c64_1_1_15__2369) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c64_new_c64_1_1_14_.INIT = 4'h6; + LUT2 com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c64_new_c64_1_1_14_ ( + .I0(N_181), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crc32_d64_feedback[1]), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c64_new_c32_d64_1_14_) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c64_new_c64_1_1_6_.INIT = 4'h6; + LUT2 com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c64_new_c64_1_1_6_ ( + .I0(N_11877), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crc32_d64_feedback[30]), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c64_new_c32_d64_1_6_) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c64_new_c64_1_1_2_.INIT = 4'h6; + LUT2 com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c64_new_c64_1_1_2_ ( + .I0(N_11949), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crc32_d64_feedback[0]), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c64_new_c32_d64_1_2_) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c64_new_c64_1_1_7_.INIT = 16'h6996; + LUT4 com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c64_new_c64_1_1_7_ ( + .I0(N_184), + .I1(N_12147_1), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crc32_d64_feedback[0]), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crc32_d64_feedback[10]), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c64_new_c32_d64_1_7_) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c64_new_c64_1_1_30_.INIT = 4'h6; + LUT2_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c64_new_c64_1_1_30_ ( + .I0(N_206), + .I1(N_223), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c64_new_c64_1_1_30__2376) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c64_new_c64_1_2_4_.INIT = 16'h6996; + LUT4 com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c64_new_c64_1_2_4_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crc32_d64_feedback[8]), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crc32_d64_feedback[16]), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_d64_c_q_4__2255), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c64_new_c32_d64_1_4_), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c64_new_c64_1_2_4__2358) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c64_new_c64_1_3_25_.INIT = 16'h6996; + LUT4_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c64_new_c64_1_3_25_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crc32_d64_feedback[6]), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crc32_d64_feedback[9]), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crc32_d64_feedback[20]), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c64_new_c64_1_0_25__2345), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c64_new_c64_1_3[25]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c64_new_c64_1_2_11_.INIT = 16'h6996; + LUT4 com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c64_new_c64_1_2_11_ ( + .I0(N_11884_1), + .I1(N_12064), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crc32_d64_feedback[9]), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_d64_c_q_11__2249), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c64_new_c64_1_2_11__2365) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c64_new_c64_1_2_1_.INIT = 16'h6996; + LUT4_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c64_new_c64_1_2_1_ ( + .I0(N_11926), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crc32_d64_feedback[2]), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crc32_d64_feedback[3]), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_d64_c_q_1__2257), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c64_new_c64_1_2_1__2356) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c64_new_c64_1_2_9_.INIT = 16'h6996; + LUT4 com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c64_new_c64_1_2_9_ ( + .I0(N_11926), + .I1(N_12169), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crc32_d64_feedback[9]), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_d64_c_q_9__2251), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c64_new_c64_1_2_9__2363) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c64_new_c64_1_4_22_.INIT = 4'h6; + LUT2_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c64_new_c64_1_4_22_ ( + .I0(N_222), + .I1(N_12156), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c64_new_c64_1_4[22]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c64_new_c64_1_2_3_.INIT = 16'h6996; + LUT4_L com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c64_new_c64_1_2_3_ ( + .I0(N_11934), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crc32_d64_feedback[5]), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crc32_d64_feedback[6]), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_d64_c_q_3__2256), + .LO(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c64_new_c64_1_2_3__2357) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c64_new_c64_1_2_27_.INIT = 16'h6996; + LUT4 com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c64_new_c64_1_2_27_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crc32_d64_feedback[21]), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crc32_d64_feedback[26]), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_d64_c_q_27__2233), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c64_new_c32_d64_1_4_), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c64_new_c64_1_2_27__2374) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c64_new_c64_1_1_12_.INIT = 8'h96; + LUT3 com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c64_new_c64_1_1_12_ ( + .I0(N_187), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crc32_d64_feedback[10]), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_d64_c_q_12__2248), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c64_new_c64_1_1_12__2366) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c64_new_c64_1_1_26_.INIT = 8'h96; + LUT3 com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c64_new_c64_1_1_26_ ( + .I0(N_222), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crc32_d64_feedback[6]), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_d64_c_q_26__2234), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c64_new_c64_1_1_26__2373) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c64_new_c64_1_1_13_.INIT = 8'h96; + LUT3 com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c64_new_c64_1_1_13_ ( + .I0(N_11934), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crc32_d64_feedback[20]), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_d64_c_q_13__2247), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c64_new_c64_1_1_13__2367) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c64_new_c64_1_16_.INIT = 16'h6996; + LUT4 com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c64_new_c64_1_16_ ( + .I0(N_188), + .I1(N_11970), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crc32_d64_feedback[14]), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c64_new_c64_1_0_16__2346), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_new_c32_d64[16]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c64_new_c64_1_17_.INIT = 16'h6996; + LUT4 com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c64_new_c64_1_17_ ( + .I0(N_11927_1), + .I1(N_11939), + .I2(N_12088_1), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c64_new_c64_1_1_17__2347), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_new_c32_d64[17]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c64_new_c64_1_19_.INIT = 16'h6996; + LUT4 com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c64_new_c64_1_19_ ( + .I0(N_182), + .I1(N_11919), + .I2(N_11970_1), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c64_new_c64_1_2_19__2348), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_new_c32_d64[19]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c64_new_c64_1_20_.INIT = 16'h6996; + LUT4 com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c64_new_c64_1_20_ ( + .I0(N_186), + .I1(N_11939), + .I2(N_12169), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c64_new_c64_1_1_20__2349), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_new_c32_d64[20]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c64_new_c64_1_21_.INIT = 16'h6996; + LUT4 com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c64_new_c64_1_21_ ( + .I0(N_183), + .I1(N_185), + .I2(N_12104), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c64_new_c64_1_1_21__2350), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_new_c32_d64[21]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c64_new_c64_1_31_.INIT = 16'h6996; + LUT4 com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c64_new_c64_1_31_ ( + .I0(N_181), + .I1(N_11924), + .I2(N_11940), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c64_new_c64_1_1_31__2351), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_new_c32_d64[31]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c64_new_c64_1_29_.INIT = 16'h6996; + LUT4 com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c64_new_c64_1_29_ ( + .I0(N_186), + .I1(N_11924), + .I2(N_11925), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c64_new_c64_1_1_29__2352), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_new_c32_d64[29]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c64_new_c64_1_2_0_.INIT = 16'h6996; + LUT4 com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c64_new_c64_1_2_0_ ( + .I0(N_221), + .I1(N_11928), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crc32_d64_feedback[16]), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_d64_c_q_0__2258), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c64_new_c64_1_2_0__2355) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c64_new_c64_1_1_8_.INIT = 8'h96; + LUT3 com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c64_new_c64_1_1_8_ ( + .I0(N_11928), + .I1(N_12156), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_d64_c_q_8__2252), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c64_new_c64_1_1_8__2362) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c64_new_c64_1_2_.INIT = 16'h6996; + LUT4 com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c64_new_c64_1_2_ ( + .I0(N_185), + .I1(N_12088), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c64_new_c64_1_1_2__2353), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c64_new_c32_d64_1_2_), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_new_c32_d64[2]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c64_new_c64_1_18_.INIT = 16'h6996; + LUT4 com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c64_new_c64_1_18_ ( + .I0(N_221), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crc32_d64_feedback[16]), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c64_new_c64_1_1_18__2354), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c64_new_c32_d64_1_2_), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_new_c32_d64[18]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c64_new_c64_1_0_.INIT = 8'h96; + LUT3 com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c64_new_c64_1_0_ ( + .I0(N_11885), + .I1(N_11927), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c64_new_c64_1_2_0__2355), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_new_c32_d64[0]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c64_new_c64_1_1_.INIT = 16'h6996; + LUT4 com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c64_new_c64_1_1_ ( + .I0(N_182), + .I1(N_187), + .I2(N_11923), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c64_new_c64_1_2_1__2356), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_new_c32_d64[1]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c64_new_c64_1_3_.INIT = 16'h6996; + LUT4 com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c64_new_c64_1_3_ ( + .I0(N_204), + .I1(N_11884), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crc32_d64_feedback[13]), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c64_new_c64_1_2_3__2357), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_new_c32_d64[3]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c64_new_c64_1_4_.INIT = 16'h6996; + LUT4 com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c64_new_c64_1_4_ ( + .I0(N_11925), + .I1(N_11941), + .I2(N_12088), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c64_new_c64_1_2_4__2358), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_new_c32_d64[4]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c64_new_c64_1_5_.INIT = 16'h6996; + LUT4 com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c64_new_c64_1_5_ ( + .I0(N_186), + .I1(N_223), + .I2(N_12124), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c64_new_c64_1_2_5__2359), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_new_c32_d64[5]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c64_new_c64_1_6_.INIT = 16'h6996; + LUT4 com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c64_new_c64_1_6_ ( + .I0(N_186), + .I1(N_11919), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c64_new_c64_1_1_6__2360), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c64_new_c32_d64_1_6_), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_new_c32_d64[6]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c64_new_c64_1_7_.INIT = 16'h6996; + LUT4 com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c64_new_c64_1_7_ ( + .I0(N_11877), + .I1(N_11949), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c64_new_c64_1_2_7__2361), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c64_new_c32_d64_1_7_), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_new_c32_d64[7]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c64_new_c64_1_8_.INIT = 16'h6996; + LUT4 com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c64_new_c64_1_8_ ( + .I0(N_11884), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crc32_d64_feedback[13]), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c64_new_c64_1_1_8__2362), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c64_new_c32_d64_1_7_), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_new_c32_d64[8]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c64_new_c64_1_9_.INIT = 16'h6996; + LUT4 com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c64_new_c64_1_9_ ( + .I0(N_185), + .I1(N_11885), + .I2(N_11940), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c64_new_c64_1_2_9__2363), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_new_c32_d64[9]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c64_new_c64_1_10_.INIT = 16'h6996; + LUT4 com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c64_new_c64_1_10_ ( + .I0(N_11884), + .I1(N_11934_1), + .I2(N_12182), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c64_new_c64_1_1_10__2364), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_new_c32_d64[10]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c64_new_c64_1_11_.INIT = 16'h6996; + LUT4 com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c64_new_c64_1_11_ ( + .I0(N_184), + .I1(N_206), + .I2(N_11927), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c64_new_c64_1_2_11__2365), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_new_c32_d64[11]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c64_new_c64_1_12_.INIT = 16'h6996; + LUT4 com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c64_new_c64_1_12_ ( + .I0(N_182), + .I1(N_222), + .I2(N_12147_1), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c64_new_c64_1_1_12__2366), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_new_c32_d64[12]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c64_new_c64_1_13_.INIT = 16'h6996; + LUT4 com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c64_new_c64_1_13_ ( + .I0(N_184), + .I1(N_12103), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crc32_d64_feedback[15]), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c64_new_c64_1_1_13__2367), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_new_c32_d64[13]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c64_new_c64_1_14_.INIT = 16'h6996; + LUT4 com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c64_new_c64_1_14_ ( + .I0(N_187), + .I1(N_11885), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c64_new_c64_1_1_14__2368), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c64_new_c32_d64_1_14_), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_new_c32_d64[14]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c64_new_c64_1_15_.INIT = 16'h6996; + LUT4 com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c64_new_c64_1_15_ ( + .I0(N_221), + .I1(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c64_new_c64_1_1_15__2369), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c64_new_c32_d64_1_6_), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c64_new_c32_d64_1_14_), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_new_c32_d64[15]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c64_new_c64_1_22_.INIT = 16'h6996; + LUT4 com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c64_new_c64_1_22_ ( + .I0(N_215), + .I1(N_11925), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c64_new_c64_1_2_22__2370), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c64_new_c64_1_4[22]), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_new_c32_d64[22]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c64_new_c64_1_23_.INIT = 16'h6996; + LUT4 com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c64_new_c64_1_23_ ( + .I0(N_182), + .I1(N_12147_1), + .I2(N_12182), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c64_new_c64_1_0_23__2371), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_new_c32_d64[23]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c64_new_c64_1_24_.INIT = 16'h6996; + LUT4 com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c64_new_c64_1_24_ ( + .I0(N_204), + .I1(N_11970), + .I2(N_12181), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c64_new_c64_1_1_24__2372), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_new_c32_d64[24]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c64_new_c64_1_25_.INIT = 16'h6996; + LUT4 com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c64_new_c64_1_25_ ( + .I0(N_183), + .I1(N_188), + .I2(N_11923), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c64_new_c64_1_3[25]), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_new_c32_d64[25]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c64_new_c64_1_26_.INIT = 16'h6996; + LUT4 com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c64_new_c64_1_26_ ( + .I0(N_12103), + .I1(N_12124), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_crc32_d64_feedback[15]), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c64_new_c64_1_1_26__2373), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_new_c32_d64[26]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c64_new_c64_1_27_.INIT = 16'h6996; + LUT4 com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c64_new_c64_1_27_ ( + .I0(N_183), + .I1(N_12086), + .I2(N_12103), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c64_new_c64_1_2_27__2374), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_new_c32_d64[27]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c64_new_c64_1_28_.INIT = 16'h6996; + LUT4 com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c64_new_c64_1_28_ ( + .I0(N_181), + .I1(N_11941), + .I2(N_12181), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c64_new_c64_1_1_28__2375), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_new_c32_d64[28]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c64_new_c64_1_30_.INIT = 16'h6996; + LUT4 com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c64_new_c64_1_30_ ( + .I0(N_185), + .I1(N_12086), + .I2(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_d64_c_q_30__2230), + .I3(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_llm_crc32_c64_new_c64_1_1_30__2376), + .O(com_llm_llm_tx_top_llmx08_tx_tlp_komp_llm_crc_32_tx_new_c32_d64[30]) + ); + GND com_llm_llm_tx_top_llmx08_tx_dllp_jefe_GND ( + .G(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_GND_2377) + ); + FDR com_llm_llm_tx_top_llmx08_tx_dllp_jefe_an_next_q_or_tx_fc_valid_q ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_N_85641_i_2402), + .Q(com_llm_llm_tx_top_tx_dllp_tx_next_pre), + .R(plm_link_up_i) + ); + FDRE com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_dllp_tx_next ( + .CE(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_N_60686_i_2379), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_N_15732_i), + .Q(com_llm_llm_tx_top_tx_dllp_tx_next), + .R(plm_link_up_i) + ); + FDRE com_llm_llm_tx_top_llmx08_tx_dllp_jefe_an_vld_q ( + .CE(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_N_85585_i_2385), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_N_56478_i_i_2399), + .Q(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_an_vld_q_2397), + .R(plm_link_up_i) + ); + FDR com_llm_llm_tx_top_llmx08_tx_dllp_jefe_an_next_q ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_an_next_q_5_0_a2_i_i_a2_0_a2_2398), + .Q(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_an_next_q_2401), + .R(plm_link_up_i) + ); + FDRE com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_expired_lbits ( + .CE(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_expired_lbits_1_sqmuxa_i_2386), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_N_87282_i_2431), + .Q(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_expired_lbits_2380), + .R(plm_link_up_i) + ); + FDRE com_llm_llm_tx_top_llmx08_tx_dllp_jefe_crc_an_vld_q ( + .CE(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_N_60686_i_2379), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_N_15708_i), + .Q(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_crc_an_vld_q_2378), + .R(plm_link_up_i) + ); + FDRE com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_expired_hbits ( + .CE(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_expired_hbits_1_sqmuxa_i_2390), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_N_87282_i_2431), + .Q(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_expired_hbits_2381), + .R(plm_link_up_i) + ); + FDRE com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_fc_valid_q ( + .CE(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_N_56110_i_i_2432), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_fc_queue_empty_i), + .Q(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_fc_valid_q_2396), + .R(plm_link_up_i) + ); + FDS com_llm_llm_tx_top_llmx08_tx_dllp_jefe_reg_tx_djefe_idle ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_reg_tx_djefe_idle_3), + .Q(com_llm_llm_tx_top_reg_tx_djefe_idle), + .S(plm_link_up_i) + ); + FDSE com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_dllp_vld_n ( + .CE(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_N_60686_i_2379), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_N_86940_i_2395), + .Q(com_llm_llm_tx_top_tx_dllp_vld_n), + .S(plm_link_up_i) + ); + MUXCY_L com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_latency_timer_cry_0_ ( + .CI(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_N_87282_i_2431), + .DI(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_GND_2377), + .LO(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_latency_timer_cry[0]), + .S(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_latency_timer_qxu[0]) + ); + XORCY com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_latency_timer_s_0_ ( + .CI(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_N_87282_i_2431), + .LI(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_latency_timer_qxu[0]), + .O(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_latency_timer_s[0]) + ); + FDR com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_latency_timer_0_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_latency_timer_s[0]), + .Q(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_latency_timer[0]), + .R(plm_link_up_i) + ); + MUXCY_L com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_latency_timer_cry_1_ ( + .CI(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_latency_timer_cry[0]), + .DI(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_GND_2377), + .LO(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_latency_timer_cry[1]), + .S(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_latency_timer_qxu[1]) + ); + XORCY com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_latency_timer_s_1_ ( + .CI(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_latency_timer_cry[0]), + .LI(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_latency_timer_qxu[1]), + .O(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_latency_timer_s[1]) + ); + FDR com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_latency_timer_1_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_latency_timer_s[1]), + .Q(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_latency_timer[1]), + .R(plm_link_up_i) + ); + MUXCY_L com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_latency_timer_cry_2_ ( + .CI(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_latency_timer_cry[1]), + .DI(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_GND_2377), + .LO(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_latency_timer_cry[2]), + .S(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_latency_timer_qxu[2]) + ); + XORCY com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_latency_timer_s_2_ ( + .CI(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_latency_timer_cry[1]), + .LI(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_latency_timer_qxu[2]), + .O(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_latency_timer_s[2]) + ); + FDR com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_latency_timer_2_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_latency_timer_s[2]), + .Q(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_latency_timer[2]), + .R(plm_link_up_i) + ); + MUXCY_L com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_latency_timer_cry_3_ ( + .CI(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_latency_timer_cry[2]), + .DI(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_GND_2377), + .LO(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_latency_timer_cry[3]), + .S(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_latency_timer_qxu[3]) + ); + XORCY com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_latency_timer_s_3_ ( + .CI(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_latency_timer_cry[2]), + .LI(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_latency_timer_qxu[3]), + .O(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_latency_timer_s[3]) + ); + FDR com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_latency_timer_3_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_latency_timer_s[3]), + .Q(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_latency_timer[3]), + .R(plm_link_up_i) + ); + MUXCY_L com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_latency_timer_cry_4_ ( + .CI(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_latency_timer_cry[3]), + .DI(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_GND_2377), + .LO(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_latency_timer_cry[4]), + .S(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_latency_timer_qxu[4]) + ); + XORCY com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_latency_timer_s_4_ ( + .CI(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_latency_timer_cry[3]), + .LI(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_latency_timer_qxu[4]), + .O(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_latency_timer_s[4]) + ); + FDR com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_latency_timer_4_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_latency_timer_s[4]), + .Q(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_latency_timer[4]), + .R(plm_link_up_i) + ); + MUXCY_L com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_latency_timer_cry_5_ ( + .CI(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_latency_timer_cry[4]), + .DI(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_GND_2377), + .LO(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_latency_timer_cry[5]), + .S(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_latency_timer_qxu[5]) + ); + XORCY com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_latency_timer_s_5_ ( + .CI(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_latency_timer_cry[4]), + .LI(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_latency_timer_qxu[5]), + .O(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_latency_timer_s[5]) + ); + FDR com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_latency_timer_5_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_latency_timer_s[5]), + .Q(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_latency_timer[5]), + .R(plm_link_up_i) + ); + MUXCY_L com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_latency_timer_cry_6_ ( + .CI(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_latency_timer_cry[5]), + .DI(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_GND_2377), + .LO(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_latency_timer_cry[6]), + .S(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_latency_timer_qxu[6]) + ); + XORCY com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_latency_timer_s_6_ ( + .CI(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_latency_timer_cry[5]), + .LI(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_latency_timer_qxu[6]), + .O(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_latency_timer_s[6]) + ); + FDR com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_latency_timer_6_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_latency_timer_s[6]), + .Q(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_latency_timer[6]), + .R(plm_link_up_i) + ); + MUXCY_L com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_latency_timer_cry_7_ ( + .CI(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_latency_timer_cry[6]), + .DI(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_GND_2377), + .LO(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_latency_timer_cry[7]), + .S(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_latency_timer_qxu[7]) + ); + XORCY com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_latency_timer_s_7_ ( + .CI(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_latency_timer_cry[6]), + .LI(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_latency_timer_qxu[7]), + .O(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_latency_timer_s[7]) + ); + FDR com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_latency_timer_7_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_latency_timer_s[7]), + .Q(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_latency_timer[7]), + .R(plm_link_up_i) + ); + MUXCY_L com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_latency_timer_cry_8_ ( + .CI(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_latency_timer_cry[7]), + .DI(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_GND_2377), + .LO(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_latency_timer_cry[8]), + .S(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_latency_timer_qxu[8]) + ); + XORCY com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_latency_timer_s_8_ ( + .CI(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_latency_timer_cry[7]), + .LI(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_latency_timer_qxu[8]), + .O(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_latency_timer_s[8]) + ); + FDR com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_latency_timer_8_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_latency_timer_s[8]), + .Q(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_latency_timer[8]), + .R(plm_link_up_i) + ); + MUXCY_L com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_latency_timer_cry_9_ ( + .CI(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_latency_timer_cry[8]), + .DI(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_GND_2377), + .LO(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_latency_timer_cry[9]), + .S(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_latency_timer_qxu[9]) + ); + XORCY com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_latency_timer_s_9_ ( + .CI(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_latency_timer_cry[8]), + .LI(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_latency_timer_qxu[9]), + .O(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_latency_timer_s[9]) + ); + FDR com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_latency_timer_9_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_latency_timer_s[9]), + .Q(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_latency_timer[9]), + .R(plm_link_up_i) + ); + MUXCY_L com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_latency_timer_cry_10_ ( + .CI(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_latency_timer_cry[9]), + .DI(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_GND_2377), + .LO(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_latency_timer_cry[10]), + .S(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_latency_timer_qxu[10]) + ); + XORCY com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_latency_timer_s_10_ ( + .CI(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_latency_timer_cry[9]), + .LI(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_latency_timer_qxu[10]), + .O(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_latency_timer_s[10]) + ); + FDR com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_latency_timer_10_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_latency_timer_s[10]), + .Q(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_latency_timer[10]), + .R(plm_link_up_i) + ); + MUXCY_L com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_latency_timer_cry_11_ ( + .CI(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_latency_timer_cry[10]), + .DI(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_GND_2377), + .LO(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_latency_timer_cry[11]), + .S(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_latency_timer_qxu[11]) + ); + XORCY com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_latency_timer_s_11_ ( + .CI(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_latency_timer_cry[10]), + .LI(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_latency_timer_qxu[11]), + .O(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_latency_timer_s[11]) + ); + FDR com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_latency_timer_11_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_latency_timer_s[11]), + .Q(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_latency_timer[11]), + .R(plm_link_up_i) + ); + MUXCY_L com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_latency_timer_cry_12_ ( + .CI(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_latency_timer_cry[11]), + .DI(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_GND_2377), + .LO(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_latency_timer_cry[12]), + .S(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_latency_timer_qxu[12]) + ); + XORCY com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_latency_timer_s_12_ ( + .CI(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_latency_timer_cry[11]), + .LI(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_latency_timer_qxu[12]), + .O(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_latency_timer_s[12]) + ); + FDR com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_latency_timer_12_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_latency_timer_s[12]), + .Q(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_latency_timer[12]), + .R(plm_link_up_i) + ); + MUXCY_L com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_latency_timer_cry_13_ ( + .CI(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_latency_timer_cry[12]), + .DI(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_GND_2377), + .LO(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_latency_timer_cry[13]), + .S(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_latency_timer_qxu[13]) + ); + XORCY com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_latency_timer_s_13_ ( + .CI(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_latency_timer_cry[12]), + .LI(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_latency_timer_qxu[13]), + .O(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_latency_timer_s[13]) + ); + FDR com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_latency_timer_13_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_latency_timer_s[13]), + .Q(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_latency_timer[13]), + .R(plm_link_up_i) + ); + XORCY com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_latency_timer_s_14_ ( + .CI(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_latency_timer_cry[13]), + .LI(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_latency_timer_qxu[14]), + .O(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_latency_timer_s[14]) + ); + FDR com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_latency_timer_14_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_latency_timer_s[14]), + .Q(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_latency_timer[14]), + .R(plm_link_up_i) + ); + FDS com_llm_llm_tx_top_llmx08_tx_dllp_jefe_pm_type_q_2_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_pm_type_q_4_i_0_0_0_a2[2]), + .Q(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_pm_type_q[2]), + .S(plm_link_up_i) + ); + FDS com_llm_llm_tx_top_llmx08_tx_dllp_jefe_lnk_tfc_sent_n ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_N_86007_i_2394), + .Q(com_lnk_tfc_sent_n), + .S(com_llm_link_status[0]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_dllp_jefe_un1_an_vld_q_1_i_0_0_0_0_o3.INIT = 4'h1; + LUT2 com_llm_llm_tx_top_llmx08_tx_dllp_jefe_un1_an_vld_q_1_i_0_0_0_0_o3 ( + .I0(com_llm_llm_tx_top_tx_dllp_accepted), + .I1(com_llm_llm_tx_top_tx_dllp_vld_n), + .O(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_N_55923_i) + ); + defparam com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_dllp_tx_next_1_sqmuxa_i_0_0_0_0_o2.INIT = 4'h4; + LUT2 com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_dllp_tx_next_1_sqmuxa_i_0_0_0_0_o2 ( + .I0(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_an_next_q_2401), + .I1(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_fc_valid_q_2396), + .O(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_N_55904_i) + ); + defparam com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_dllp_tx_next_0_sqmuxa_i_0_0_0_a3.INIT = 4'h1; + LUT2 com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_dllp_tx_next_0_sqmuxa_i_0_0_0_a3 ( + .I0(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_an_next_q_2401), + .I1(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_an_vld_q_2397), + .O(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_N_61418) + ); + defparam com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_dllp_pre_i_0_0_0_a2_0_.INIT = 4'h1; + LUT2 com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_dllp_pre_i_0_0_0_a2_0_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_an_vld_q_2397), + .I1(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_fc_valid_q_2396), + .O(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_N_58432) + ); + defparam com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_expired_lbits12_0.INIT = 4'h6; + LUT2 com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_expired_lbits12_0 ( + .I0(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_latency_timer[0]), + .I1(com_llm_reg_ack_to_val[0]), + .O(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_expired_lbits12_0_2384) + ); + defparam com_llm_llm_tx_top_llmx08_tx_dllp_jefe_un1_an_vld_q_1_i_0_0_0_0_1.INIT = 4'h1; + LUT2 com_llm_llm_tx_top_llmx08_tx_dllp_jefe_un1_an_vld_q_1_i_0_0_0_0_1 ( + .I0(com_llm_reg_tx_dllp_dup_vld), + .I1(com_llm_reg_tx_dllp_nak_vld), + .O(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_N_85585_1) + ); + defparam com_llm_llm_tx_top_llmx08_tx_dllp_jefe_un1_link_status_1_i_0_0_a3.INIT = 4'h8; + LUT2 com_llm_llm_tx_top_llmx08_tx_dllp_jefe_un1_link_status_1_i_0_0_a3 ( + .I0(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_N_58432), + .I1(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_pm_type_q[2]), + .O(com_llm_llm_tx_top_un1_link_status_1_i_0_0_a3) + ); + defparam com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_latency_timer17_i_o2_0_o2_0_o2_0_o2.INIT = 8'h51; + LUT3 com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_latency_timer17_i_o2_0_o2_0_o2_0_o2 ( + .I0(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_an_vld_q_2397), + .I1(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_crc_an_vld_q_2378), + .I2(com_llm_llm_tx_top_tx_dllp_accepted), + .O(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_latency_timer17_i_o2_0_o2_0_o2_0_o2_2433) + ); + defparam com_llm_llm_tx_top_llmx08_tx_dllp_jefe_pm_type_q_4_i_0_0_0_a2_2_.INIT = 8'h01; + LUT3 com_llm_llm_tx_top_llmx08_tx_dllp_jefe_pm_type_q_4_i_0_0_0_a2_2_ ( + .I0(com_st_pm_13_), + .I1(com_st_pm_17_), + .I2(com_st_pm_27_), + .O(com_pm_type_q_4_i_0_0_0_a2[2]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_expired_hbits12_NE_0.INIT = 16'h8421; + LUT4 com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_expired_hbits12_NE_0 ( + .I0(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_latency_timer[13]), + .I1(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_latency_timer[14]), + .I2(com_llm_reg_ack_to_val[13]), + .I3(com_llm_reg_ack_to_val[14]), + .O(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_expired_hbits12_NE_0_2393) + ); + defparam com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_expired_hbits12_NE_1.INIT = 16'h8421; + LUT4 com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_expired_hbits12_NE_1 ( + .I0(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_latency_timer[11]), + .I1(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_latency_timer[12]), + .I2(com_llm_reg_ack_to_val[11]), + .I3(com_llm_reg_ack_to_val[12]), + .O(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_expired_hbits12_NE_1_2392) + ); + defparam com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_expired_hbits12_NE_2.INIT = 16'h8421; + LUT4_L com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_expired_hbits12_NE_2 ( + .I0(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_latency_timer[8]), + .I1(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_latency_timer[10]), + .I2(com_llm_reg_ack_to_val[8]), + .I3(com_llm_reg_ack_to_val[10]), + .LO(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_expired_hbits12_NE_2_2382) + ); + defparam com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_expired_lbits12_NE_0.INIT = 16'h8421; + LUT4 com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_expired_lbits12_NE_0 ( + .I0(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_latency_timer[6]), + .I1(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_latency_timer[7]), + .I2(com_llm_reg_ack_to_val[6]), + .I3(com_llm_reg_ack_to_val[7]), + .O(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_expired_lbits12_NE_0_2389) + ); + defparam com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_expired_lbits12_NE_1.INIT = 16'h8421; + LUT4 com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_expired_lbits12_NE_1 ( + .I0(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_latency_timer[4]), + .I1(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_latency_timer[5]), + .I2(com_llm_reg_ack_to_val[4]), + .I3(com_llm_reg_ack_to_val[5]), + .O(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_expired_lbits12_NE_1_2388) + ); + defparam com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_expired_lbits12_NE_2.INIT = 16'h8421; + LUT4 com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_expired_lbits12_NE_2 ( + .I0(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_latency_timer[2]), + .I1(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_latency_timer[3]), + .I2(com_llm_reg_ack_to_val[2]), + .I3(com_llm_reg_ack_to_val[3]), + .O(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_expired_lbits12_NE_2_2383) + ); + defparam com_llm_llm_tx_top_llmx08_tx_dllp_jefe_N_60686_i.INIT = 8'hDF; + LUT3 com_llm_llm_tx_top_llmx08_tx_dllp_jefe_N_60686_i ( + .I0(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_N_55923_i), + .I1(com_llm_link_status[0]), + .I2(plm_link_up_1), + .O(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_N_60686_i_2379) + ); + defparam com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_fc_valid_q8_i_0_0_0_o3.INIT = 8'hE0; + LUT3 com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_fc_valid_q8_i_0_0_0_o3 ( + .I0(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_N_55923_i), + .I1(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_an_next_q_2401), + .I2(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_fc_valid_q_2396), + .O(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_N_56110_i) + ); + defparam com_llm_llm_tx_top_llmx08_tx_dllp_jefe_an_next_q_or_tx_fc_valid_q_7_u_0_i_i_0_o3.INIT = 16'h2AAA; + LUT4 com_llm_llm_tx_top_llmx08_tx_dllp_jefe_an_next_q_or_tx_fc_valid_q_7_u_0_i_i_0_o3 ( + .I0(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_N_85585_1), + .I1(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_expired_hbits_2381), + .I2(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_expired_lbits_2380), + .I3(com_llm_reg_tx_dllp_ack_vld), + .O(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_an_next_q_or_tx_fc_valid_q_7_u_0_i_i_0_o3_2404) + ); + defparam com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_dllp_tx_next_0_sqmuxa_i_0_0_0_o2.INIT = 8'h01; + LUT3 com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_dllp_tx_next_0_sqmuxa_i_0_0_0_o2 ( + .I0(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_N_55904_i), + .I1(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_N_55923_i), + .I2(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_N_61418), + .O(com_llm_N_56478_i) + ); + defparam com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_expired_hbits12_NE_3.INIT = 8'h82; + LUT3 com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_expired_hbits12_NE_3 ( + .I0(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_expired_hbits12_NE_2_2382), + .I1(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_latency_timer[9]), + .I2(com_llm_reg_ack_to_val[9]), + .O(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_expired_hbits12_NE_3_2391) + ); + defparam com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_expired_lbits12_NE_4.INIT = 16'h4004; + LUT4 com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_expired_lbits12_NE_4 ( + .I0(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_expired_lbits12_0_2384), + .I1(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_expired_lbits12_NE_2_2383), + .I2(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_latency_timer[1]), + .I3(com_llm_reg_ack_to_val[1]), + .O(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_expired_lbits12_NE_4_2387) + ); + defparam com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_dllp_tx_next_9_f0_i_0_0_0_0.INIT = 16'h5540; + LUT4 com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_dllp_tx_next_9_f0_i_0_0_0_0 ( + .I0(com_llm_link_status[0]), + .I1(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_an_next_q_2401), + .I2(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_an_vld_q_2397), + .I3(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_fc_valid_q_2396), + .O(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_dllp_tx_next_9_f0_i_0_0_0_0_2400) + ); + defparam com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_fc_valid_q8_i_0_0_0.INIT = 4'h4; + LUT2 com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_fc_valid_q8_i_0_0_0 ( + .I0(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_N_56110_i), + .I1(plm_link_up_1), + .O(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_N_15711_i) + ); + defparam com_llm_llm_tx_top_llmx08_tx_dllp_jefe_N_85585_i.INIT = 8'hFB; + LUT3 com_llm_llm_tx_top_llmx08_tx_dllp_jefe_N_85585_i ( + .I0(com_llm_N_56478_i), + .I1(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_N_85585_1), + .I2(com_llm_reg_tx_dllp_ack_vld), + .O(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_N_85585_i_2385) + ); + defparam com_llm_llm_tx_top_llmx08_tx_dllp_jefe_an_next_q_or_tx_fc_valid_q_7_u_0_i_i_0_2.INIT = 16'h4050; + LUT4_L com_llm_llm_tx_top_llmx08_tx_dllp_jefe_an_next_q_or_tx_fc_valid_q_7_u_0_i_i_0_2 ( + .I0(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_N_56110_i), + .I1(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_an_next_q_or_tx_fc_valid_q_7_u_0_i_i_0_o3_2404), + .I2(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_fc_queue_empty), + .I3(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_fc_valid_q_2396), + .LO(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_an_next_q_or_tx_fc_valid_q_7_u_0_i_i_0_2_2403) + ); + defparam com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_expired_lbits_1_sqmuxa_i.INIT = 16'hEAAA; + LUT4 com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_expired_lbits_1_sqmuxa_i ( + .I0(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_latency_timer17_i_o2_0_o2_0_o2_0_o2_2433), + .I1(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_expired_lbits12_NE_0_2389), + .I2(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_expired_lbits12_NE_1_2388), + .I3(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_expired_lbits12_NE_4_2387), + .O(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_expired_lbits_1_sqmuxa_i_2386) + ); + defparam com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_expired_hbits_1_sqmuxa_i.INIT = 16'hEAAA; + LUT4 com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_expired_hbits_1_sqmuxa_i ( + .I0(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_latency_timer17_i_o2_0_o2_0_o2_0_o2_2433), + .I1(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_expired_hbits12_NE_0_2393), + .I2(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_expired_hbits12_NE_1_2392), + .I3(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_expired_hbits12_NE_3_2391), + .O(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_expired_hbits_1_sqmuxa_i_2390) + ); + defparam com_llm_llm_tx_top_llmx08_tx_dllp_jefe_N_86007_i.INIT = 8'hDF; + LUT3_L com_llm_llm_tx_top_llmx08_tx_dllp_jefe_N_86007_i ( + .I0(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_N_55904_i), + .I1(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_N_55923_i), + .I2(plm_link_up_1), + .LO(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_N_86007_i_2394) + ); + defparam com_llm_llm_tx_top_llmx08_tx_dllp_jefe_pm_type_d24_0_a2_0_a2_0_a2_0_a2.INIT = 8'h02; + LUT3_L com_llm_llm_tx_top_llmx08_tx_dllp_jefe_pm_type_d24_0_a2_0_a2_0_a2_0_a2 ( + .I0(com_st_pm_13_), + .I1(com_st_pm_17_), + .I2(com_st_pm_27_), + .LO(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_pm_type_d24) + ); + defparam com_llm_llm_tx_top_llmx08_tx_dllp_jefe_N_86940_i.INIT = 4'hE; + LUT2_L com_llm_llm_tx_top_llmx08_tx_dllp_jefe_N_86940_i ( + .I0(com_llm_llm_tx_top_un1_link_status_1_i_0_0_a3), + .I1(com_llm_link_status[0]), + .LO(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_N_86940_i_2395) + ); + defparam com_llm_llm_tx_top_llmx08_tx_dllp_jefe_reg_tx_djefe_idle_3_0_a2_0_a2_0_a2_0_a2.INIT = 8'h80; + LUT3_L com_llm_llm_tx_top_llmx08_tx_dllp_jefe_reg_tx_djefe_idle_3_0_a2_0_a2_0_a2_0_a2 ( + .I0(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_N_58432), + .I1(com_pm_type_q_4_i_0_0_0_a2[2]), + .I2(com_llm_llm_tx_top_tx_dllp_vld_n), + .LO(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_reg_tx_djefe_idle_3) + ); + defparam com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_dllp_tx_next_0_sqmuxa_i_0_0_0.INIT = 8'h20; + LUT3_L com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_dllp_tx_next_0_sqmuxa_i_0_0_0 ( + .I0(com_llm_N_56478_i), + .I1(com_llm_link_status[0]), + .I2(plm_link_up_2), + .LO(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_N_15708_i) + ); + defparam com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_dllp_pre_0_a2_0_a2_0_a2_0_a2_31_.INIT = 4'h8; + LUT2_L com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_dllp_pre_0_a2_0_a2_0_a2_0_a2_31_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_N_55904_i), + .I1(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_fc_data_q_31__2405), + .LO(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_dllp_pre_31_) + ); + defparam com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_dllp_pre_0_a2_0_a2_0_a2_0_a2_30_.INIT = 4'h8; + LUT2_L com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_dllp_pre_0_a2_0_a2_0_a2_0_a2_30_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_N_55904_i), + .I1(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_fc_data_q_30__2406), + .LO(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_dllp_pre_30_) + ); + defparam com_llm_llm_tx_top_llmx08_tx_dllp_jefe_N_87143_i.INIT = 8'hEC; + LUT3_L com_llm_llm_tx_top_llmx08_tx_dllp_jefe_N_87143_i ( + .I0(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_N_55904_i), + .I1(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_N_58432), + .I2(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_fc_data_q_29__2407), + .LO(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_N_87143_i_2429) + ); + defparam com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_dllp_pre_i_0_0_0_28_.INIT = 16'h3120; + LUT4_L com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_dllp_pre_i_0_0_0_28_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_N_55904_i), + .I1(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_N_58432), + .I2(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_fc_data_q_28__2408), + .I3(com_llm_reg_tx_dllp_nak_vld), + .LO(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_N_15769_i) + ); + defparam com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_dllp_pre_i_0_0_0_25_.INIT = 8'h04; + LUT3_L com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_dllp_pre_i_0_0_0_25_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_an_vld_q_2397), + .I1(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_pm_type_q[1]), + .I2(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_fc_valid_q_2396), + .LO(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_N_15767_i) + ); + defparam com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_dllp_pre_i_0_0_0_24_.INIT = 8'h04; + LUT3_L com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_dllp_pre_i_0_0_0_24_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_an_vld_q_2397), + .I1(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_pm_type_q[0]), + .I2(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_fc_valid_q_2396), + .LO(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_N_15765_i) + ); + defparam com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_dllp_pre_0_a2_0_a2_0_a2_0_a2_21_.INIT = 4'h8; + LUT2_L com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_dllp_pre_0_a2_0_a2_0_a2_0_a2_21_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_N_55904_i), + .I1(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_fc_data_q_21__2409), + .LO(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_dllp_pre_21_) + ); + defparam com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_dllp_pre_0_a2_0_a2_0_a2_0_a2_20_.INIT = 4'h8; + LUT2_L com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_dllp_pre_0_a2_0_a2_0_a2_0_a2_20_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_N_55904_i), + .I1(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_fc_data_q_20__2410), + .LO(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_dllp_pre_20_) + ); + defparam com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_dllp_pre_0_a2_0_a2_0_a2_0_a2_19_.INIT = 4'h8; + LUT2_L com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_dllp_pre_0_a2_0_a2_0_a2_0_a2_19_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_N_55904_i), + .I1(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_fc_data_q_19__2411), + .LO(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_dllp_pre_19_) + ); + defparam com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_dllp_pre_0_a2_0_a2_0_a2_0_a2_18_.INIT = 4'h8; + LUT2_L com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_dllp_pre_0_a2_0_a2_0_a2_0_a2_18_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_N_55904_i), + .I1(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_fc_data_q_18__2412), + .LO(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_dllp_pre_18_) + ); + defparam com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_dllp_pre_0_a2_0_a2_0_a2_0_a2_17_.INIT = 4'h8; + LUT2_L com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_dllp_pre_0_a2_0_a2_0_a2_0_a2_17_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_N_55904_i), + .I1(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_fc_data_q_17__2413), + .LO(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_dllp_pre_17_) + ); + defparam com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_dllp_pre_0_a2_0_a2_0_a2_0_a2_16_.INIT = 4'h8; + LUT2_L com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_dllp_pre_0_a2_0_a2_0_a2_0_a2_16_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_N_55904_i), + .I1(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_fc_data_q_16__2414), + .LO(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_dllp_pre_16_) + ); + defparam com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_dllp_pre_0_a2_0_a2_0_a2_0_a2_15_.INIT = 4'h8; + LUT2_L com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_dllp_pre_0_a2_0_a2_0_a2_0_a2_15_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_N_55904_i), + .I1(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_fc_data_q_15__2415), + .LO(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_dllp_pre_15_) + ); + defparam com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_dllp_pre_0_a2_0_a2_0_a2_0_a2_14_.INIT = 4'h8; + LUT2_L com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_dllp_pre_0_a2_0_a2_0_a2_0_a2_14_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_N_55904_i), + .I1(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_fc_data_q_14__2416), + .LO(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_dllp_pre_14_) + ); + defparam com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_dllp_pre_i_0_0_0_11_.INIT = 16'h3120; + LUT4_L com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_dllp_pre_i_0_0_0_11_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_N_55904_i), + .I1(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_N_58432), + .I2(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_fc_data_q_11__2417), + .I3(com_llm_reg_tx_dllp_tsn[11]), + .LO(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_N_15763_i) + ); + defparam com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_dllp_pre_i_0_0_0_10_.INIT = 16'h3120; + LUT4_L com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_dllp_pre_i_0_0_0_10_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_N_55904_i), + .I1(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_N_58432), + .I2(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_fc_data_q_10__2418), + .I3(com_llm_reg_tx_dllp_tsn[10]), + .LO(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_N_15761_i) + ); + defparam com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_dllp_pre_i_0_0_0_9_.INIT = 16'h3120; + LUT4_L com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_dllp_pre_i_0_0_0_9_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_N_55904_i), + .I1(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_N_58432), + .I2(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_fc_data_q_9__2419), + .I3(com_llm_reg_tx_dllp_tsn[9]), + .LO(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_N_15759_i) + ); + defparam com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_dllp_pre_i_0_0_0_8_.INIT = 16'h3120; + LUT4_L com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_dllp_pre_i_0_0_0_8_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_N_55904_i), + .I1(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_N_58432), + .I2(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_fc_data_q_8__2420), + .I3(com_llm_reg_tx_dllp_tsn[8]), + .LO(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_N_15757_i) + ); + defparam com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_dllp_pre_i_0_0_0_7_.INIT = 16'h3120; + LUT4_L com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_dllp_pre_i_0_0_0_7_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_N_55904_i), + .I1(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_N_58432), + .I2(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_fc_data_q_7__2421), + .I3(com_llm_reg_tx_dllp_tsn[7]), + .LO(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_N_15755_i) + ); + defparam com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_dllp_pre_i_0_0_0_6_.INIT = 16'h3120; + LUT4_L com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_dllp_pre_i_0_0_0_6_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_N_55904_i), + .I1(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_N_58432), + .I2(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_fc_data_q_6__2422), + .I3(com_llm_reg_tx_dllp_tsn[6]), + .LO(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_N_15753_i) + ); + defparam com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_dllp_pre_i_0_0_0_5_.INIT = 16'h3120; + LUT4_L com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_dllp_pre_i_0_0_0_5_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_N_55904_i), + .I1(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_N_58432), + .I2(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_fc_data_q_5__2423), + .I3(com_llm_reg_tx_dllp_tsn[5]), + .LO(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_N_15751_i) + ); + defparam com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_dllp_pre_i_0_0_0_4_.INIT = 16'h3120; + LUT4_L com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_dllp_pre_i_0_0_0_4_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_N_55904_i), + .I1(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_N_58432), + .I2(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_fc_data_q_4__2424), + .I3(com_llm_reg_tx_dllp_tsn[4]), + .LO(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_N_15749_i) + ); + defparam com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_dllp_pre_i_0_0_0_3_.INIT = 16'h3120; + LUT4_L com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_dllp_pre_i_0_0_0_3_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_N_55904_i), + .I1(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_N_58432), + .I2(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_fc_data_q_3__2425), + .I3(com_llm_reg_tx_dllp_tsn[3]), + .LO(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_N_15747_i) + ); + defparam com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_dllp_pre_i_0_0_0_2_.INIT = 16'h3120; + LUT4_L com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_dllp_pre_i_0_0_0_2_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_N_55904_i), + .I1(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_N_58432), + .I2(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_fc_data_q_2__2426), + .I3(com_llm_reg_tx_dllp_tsn[2]), + .LO(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_N_15745_i) + ); + defparam com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_dllp_pre_i_0_0_0_1_.INIT = 16'h3120; + LUT4_L com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_dllp_pre_i_0_0_0_1_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_N_55904_i), + .I1(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_N_58432), + .I2(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_fc_data_q_1__2427), + .I3(com_llm_reg_tx_dllp_tsn[1]), + .LO(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_N_15743_i) + ); + defparam com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_dllp_pre_i_0_0_0_0_.INIT = 16'h3120; + LUT4_L com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_dllp_pre_i_0_0_0_0_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_N_55904_i), + .I1(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_N_58432), + .I2(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_fc_data_q_0__2428), + .I3(com_llm_reg_tx_dllp_tsn[0]), + .LO(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_N_15741_i) + ); + defparam com_llm_llm_tx_top_llmx08_tx_dllp_jefe_an_next_q_5_0_a2_i_i_a2_0_a2.INIT = 4'h1; + LUT2_L com_llm_llm_tx_top_llmx08_tx_dllp_jefe_an_next_q_5_0_a2_i_i_a2_0_a2 ( + .I0(com_llm_N_56478_i), + .I1(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_an_next_q_or_tx_fc_valid_q_7_u_0_i_i_0_o3_2404), + .LO(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_an_next_q_5_0_a2_i_i_a2_0_a2_2398) + ); + defparam com_llm_llm_tx_top_llmx08_tx_dllp_jefe_N_56478_i_i.INIT = 4'h1; + LUT1_L com_llm_llm_tx_top_llmx08_tx_dllp_jefe_N_56478_i_i ( + .I0(com_llm_N_56478_i), + .LO(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_N_56478_i_i_2399) + ); + defparam com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_dllp_tx_next_9_f0_i_0_0_0.INIT = 16'hD0C0; + LUT4_L com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_dllp_tx_next_9_f0_i_0_0_0 ( + .I0(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_N_55923_i), + .I1(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_an_next_q_2401), + .I2(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_dllp_tx_next_9_f0_i_0_0_0_0_2400), + .I3(plm_link_up_2), + .LO(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_N_15732_i) + ); + defparam com_llm_llm_tx_top_llmx08_tx_dllp_jefe_N_85641_i.INIT = 16'h0EFF; + LUT4_L com_llm_llm_tx_top_llmx08_tx_dllp_jefe_N_85641_i ( + .I0(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_N_55923_i), + .I1(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_N_61418), + .I2(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_an_next_q_or_tx_fc_valid_q_7_u_0_i_i_0_o3_2404), + .I3(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_an_next_q_or_tx_fc_valid_q_7_u_0_i_i_0_2_2403), + .LO(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_N_85641_i_2402) + ); + FD com_llm_llm_tx_top_llmx08_tx_dllp_jefe_pm_type_q_1_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_pm_type_d24), + .Q(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_pm_type_q[1]) + ); + FD com_llm_llm_tx_top_llmx08_tx_dllp_jefe_pm_type_q_0_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_st_pm_i[17]), + .Q(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_pm_type_q[0]) + ); + FDE com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_fc_data_q_31_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_N_15711_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_fc_dout_31_), + .Q(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_fc_data_q_31__2405) + ); + FDE com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_fc_data_q_30_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_N_15711_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_fc_dout_30_), + .Q(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_fc_data_q_30__2406) + ); + FDE com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_fc_data_q_29_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_N_15711_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_fc_dout_29_), + .Q(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_fc_data_q_29__2407) + ); + FDE com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_fc_data_q_28_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_N_15711_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_fc_dout_28_), + .Q(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_fc_data_q_28__2408) + ); + FDE com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_fc_data_q_21_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_N_15711_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_fc_dout_21_), + .Q(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_fc_data_q_21__2409) + ); + FDE com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_fc_data_q_20_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_N_15711_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_fc_dout_20_), + .Q(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_fc_data_q_20__2410) + ); + FDE com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_fc_data_q_19_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_N_15711_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_fc_dout_19_), + .Q(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_fc_data_q_19__2411) + ); + FDE com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_fc_data_q_18_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_N_15711_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_fc_dout_18_), + .Q(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_fc_data_q_18__2412) + ); + FDE com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_fc_data_q_17_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_N_15711_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_fc_dout_17_), + .Q(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_fc_data_q_17__2413) + ); + FDE com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_fc_data_q_16_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_N_15711_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_fc_dout_16_), + .Q(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_fc_data_q_16__2414) + ); + FDE com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_fc_data_q_15_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_N_15711_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_fc_dout_15_), + .Q(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_fc_data_q_15__2415) + ); + FDE com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_fc_data_q_14_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_N_15711_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_fc_dout_14_), + .Q(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_fc_data_q_14__2416) + ); + FDE com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_fc_data_q_11_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_N_15711_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_fc_dout_11_), + .Q(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_fc_data_q_11__2417) + ); + FDE com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_fc_data_q_10_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_N_15711_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_fc_dout_10_), + .Q(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_fc_data_q_10__2418) + ); + FDE com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_fc_data_q_9_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_N_15711_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_fc_dout_9_), + .Q(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_fc_data_q_9__2419) + ); + FDE com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_fc_data_q_8_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_N_15711_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_fc_dout_8_), + .Q(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_fc_data_q_8__2420) + ); + FDE com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_fc_data_q_7_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_N_15711_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_fc_dout_7_), + .Q(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_fc_data_q_7__2421) + ); + FDE com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_fc_data_q_6_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_N_15711_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_fc_dout_6_), + .Q(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_fc_data_q_6__2422) + ); + FDE com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_fc_data_q_5_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_N_15711_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_fc_dout_5_), + .Q(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_fc_data_q_5__2423) + ); + FDE com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_fc_data_q_4_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_N_15711_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_fc_dout_4_), + .Q(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_fc_data_q_4__2424) + ); + FDE com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_fc_data_q_3_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_N_15711_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_fc_dout_3_), + .Q(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_fc_data_q_3__2425) + ); + FDE com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_fc_data_q_2_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_N_15711_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_fc_dout_2_), + .Q(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_fc_data_q_2__2426) + ); + FDE com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_fc_data_q_1_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_N_15711_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_fc_dout_1_), + .Q(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_fc_data_q_1__2427) + ); + FDE com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_fc_data_q_0_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_N_15711_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_fc_dout_0_), + .Q(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_fc_data_q_0__2428) + ); + FDE com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_dllp_td_1_55_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_N_55923_i_i_2430), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_dllp_pre_31_), + .Q(com_llm_llm_tx_top_tx_dllp_td_55_) + ); + FDE com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_dllp_td_1_54_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_N_55923_i_i_2430), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_dllp_pre_30_), + .Q(com_llm_llm_tx_top_tx_dllp_td_54_) + ); + FDE com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_dllp_td_1_53_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_N_55923_i_i_2430), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_N_87143_i_2429), + .Q(com_llm_llm_tx_top_tx_dllp_td_53_) + ); + FDE com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_dllp_td_1_52_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_N_55923_i_i_2430), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_N_15769_i), + .Q(com_llm_llm_tx_top_tx_dllp_td_52_) + ); + FDE com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_dllp_td_1_49_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_N_55923_i_i_2430), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_N_15767_i), + .Q(com_llm_llm_tx_top_tx_dllp_td_49_) + ); + FDE com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_dllp_td_1_48_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_N_55923_i_i_2430), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_N_15765_i), + .Q(com_llm_llm_tx_top_tx_dllp_td_48_) + ); + FDE com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_dllp_td_1_45_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_N_55923_i_i_2430), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_dllp_pre_21_), + .Q(com_llm_llm_tx_top_tx_dllp_td_45_) + ); + FDE com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_dllp_td_1_44_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_N_55923_i_i_2430), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_dllp_pre_20_), + .Q(com_llm_llm_tx_top_tx_dllp_td_44_) + ); + FDE com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_dllp_td_1_43_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_N_55923_i_i_2430), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_dllp_pre_19_), + .Q(com_llm_llm_tx_top_tx_dllp_td_43_) + ); + FDE com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_dllp_td_1_42_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_N_55923_i_i_2430), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_dllp_pre_18_), + .Q(com_llm_llm_tx_top_tx_dllp_td_42_) + ); + FDE com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_dllp_td_1_41_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_N_55923_i_i_2430), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_dllp_pre_17_), + .Q(com_llm_llm_tx_top_tx_dllp_td_41_) + ); + FDE com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_dllp_td_1_40_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_N_55923_i_i_2430), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_dllp_pre_16_), + .Q(com_llm_llm_tx_top_tx_dllp_td_40_) + ); + FDE com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_dllp_td_1_39_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_N_55923_i_i_2430), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_dllp_pre_15_), + .Q(com_llm_llm_tx_top_tx_dllp_td_39_) + ); + FDE com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_dllp_td_1_38_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_N_55923_i_i_2430), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_dllp_pre_14_), + .Q(com_llm_llm_tx_top_tx_dllp_td_38_) + ); + FDE com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_dllp_td_1_35_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_N_55923_i_i_2430), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_N_15763_i), + .Q(com_llm_llm_tx_top_tx_dllp_td_35_) + ); + FDE com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_dllp_td_1_34_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_N_55923_i_i_2430), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_N_15761_i), + .Q(com_llm_llm_tx_top_tx_dllp_td_34_) + ); + FDE com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_dllp_td_1_33_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_N_55923_i_i_2430), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_N_15759_i), + .Q(com_llm_llm_tx_top_tx_dllp_td_33_) + ); + FDE com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_dllp_td_1_32_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_N_55923_i_i_2430), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_N_15757_i), + .Q(com_llm_llm_tx_top_tx_dllp_td_32_) + ); + FDE com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_dllp_td_1_31_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_N_55923_i_i_2430), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_N_15755_i), + .Q(com_llm_llm_tx_top_tx_dllp_td_31_) + ); + FDE com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_dllp_td_1_30_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_N_55923_i_i_2430), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_N_15753_i), + .Q(com_llm_llm_tx_top_tx_dllp_td_30_) + ); + FDE com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_dllp_td_1_29_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_N_55923_i_i_2430), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_N_15751_i), + .Q(com_llm_llm_tx_top_tx_dllp_td_29_) + ); + FDE com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_dllp_td_1_28_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_N_55923_i_i_2430), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_N_15749_i), + .Q(com_llm_llm_tx_top_tx_dllp_td_28_) + ); + FDE com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_dllp_td_1_27_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_N_55923_i_i_2430), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_N_15747_i), + .Q(com_llm_llm_tx_top_tx_dllp_td_27_) + ); + FDE com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_dllp_td_1_26_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_N_55923_i_i_2430), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_N_15745_i), + .Q(com_llm_llm_tx_top_tx_dllp_td_26_) + ); + FDE com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_dllp_td_1_25_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_N_55923_i_i_2430), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_N_15743_i), + .Q(com_llm_llm_tx_top_tx_dllp_td_25_) + ); + FDE com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_dllp_td_1_24_ ( + .CE(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_N_55923_i_i_2430), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_N_15741_i), + .Q(com_llm_llm_tx_top_tx_dllp_td_24_) + ); + INV com_llm_llm_tx_top_llmx08_tx_dllp_jefe_N_55923_i_i ( + .I(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_N_55923_i), + .O(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_N_55923_i_i_2430) + ); + INV com_llm_llm_tx_top_llmx08_tx_dllp_jefe_N_87282_i ( + .I(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_latency_timer17_i_o2_0_o2_0_o2_0_o2_2433), + .O(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_N_87282_i_2431) + ); + INV com_llm_llm_tx_top_llmx08_tx_dllp_jefe_N_56110_i_i ( + .I(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_N_56110_i), + .O(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_N_56110_i_i_2432) + ); + defparam com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_latency_timer_qxu_0_14_.INIT = 4'h4; + LUT2_L com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_latency_timer_qxu_0_14_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_latency_timer17_i_o2_0_o2_0_o2_0_o2_2433), + .I1(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_latency_timer[14]), + .LO(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_latency_timer_qxu[14]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_latency_timer_qxu_0_13_.INIT = 4'h4; + LUT2_L com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_latency_timer_qxu_0_13_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_latency_timer17_i_o2_0_o2_0_o2_0_o2_2433), + .I1(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_latency_timer[13]), + .LO(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_latency_timer_qxu[13]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_latency_timer_qxu_0_12_.INIT = 4'h4; + LUT2_L com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_latency_timer_qxu_0_12_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_latency_timer17_i_o2_0_o2_0_o2_0_o2_2433), + .I1(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_latency_timer[12]), + .LO(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_latency_timer_qxu[12]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_latency_timer_qxu_0_11_.INIT = 4'h4; + LUT2_L com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_latency_timer_qxu_0_11_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_latency_timer17_i_o2_0_o2_0_o2_0_o2_2433), + .I1(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_latency_timer[11]), + .LO(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_latency_timer_qxu[11]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_latency_timer_qxu_0_10_.INIT = 4'h4; + LUT2_L com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_latency_timer_qxu_0_10_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_latency_timer17_i_o2_0_o2_0_o2_0_o2_2433), + .I1(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_latency_timer[10]), + .LO(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_latency_timer_qxu[10]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_latency_timer_qxu_0_9_.INIT = 4'h4; + LUT2_L com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_latency_timer_qxu_0_9_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_latency_timer17_i_o2_0_o2_0_o2_0_o2_2433), + .I1(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_latency_timer[9]), + .LO(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_latency_timer_qxu[9]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_latency_timer_qxu_0_8_.INIT = 4'h4; + LUT2_L com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_latency_timer_qxu_0_8_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_latency_timer17_i_o2_0_o2_0_o2_0_o2_2433), + .I1(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_latency_timer[8]), + .LO(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_latency_timer_qxu[8]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_latency_timer_qxu_0_7_.INIT = 4'h4; + LUT2_L com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_latency_timer_qxu_0_7_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_latency_timer17_i_o2_0_o2_0_o2_0_o2_2433), + .I1(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_latency_timer[7]), + .LO(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_latency_timer_qxu[7]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_latency_timer_qxu_0_6_.INIT = 4'h4; + LUT2_L com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_latency_timer_qxu_0_6_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_latency_timer17_i_o2_0_o2_0_o2_0_o2_2433), + .I1(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_latency_timer[6]), + .LO(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_latency_timer_qxu[6]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_latency_timer_qxu_0_5_.INIT = 4'h4; + LUT2_L com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_latency_timer_qxu_0_5_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_latency_timer17_i_o2_0_o2_0_o2_0_o2_2433), + .I1(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_latency_timer[5]), + .LO(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_latency_timer_qxu[5]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_latency_timer_qxu_0_4_.INIT = 4'h4; + LUT2_L com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_latency_timer_qxu_0_4_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_latency_timer17_i_o2_0_o2_0_o2_0_o2_2433), + .I1(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_latency_timer[4]), + .LO(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_latency_timer_qxu[4]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_latency_timer_qxu_0_3_.INIT = 4'h4; + LUT2_L com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_latency_timer_qxu_0_3_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_latency_timer17_i_o2_0_o2_0_o2_0_o2_2433), + .I1(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_latency_timer[3]), + .LO(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_latency_timer_qxu[3]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_latency_timer_qxu_0_2_.INIT = 4'h4; + LUT2_L com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_latency_timer_qxu_0_2_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_latency_timer17_i_o2_0_o2_0_o2_0_o2_2433), + .I1(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_latency_timer[2]), + .LO(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_latency_timer_qxu[2]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_latency_timer_qxu_0_1_.INIT = 4'h4; + LUT2_L com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_latency_timer_qxu_0_1_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_latency_timer17_i_o2_0_o2_0_o2_0_o2_2433), + .I1(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_latency_timer[1]), + .LO(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_latency_timer_qxu[1]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_latency_timer_qxu_0_0_.INIT = 4'h4; + LUT2_L com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_latency_timer_qxu_0_0_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_latency_timer17_i_o2_0_o2_0_o2_0_o2_2433), + .I1(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_latency_timer[0]), + .LO(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_ack_nak_latency_timer_qxu[0]) + ); + GND com_llm_llm_tx_top_llmx08_tx_dllp_jefe_llm32_fc_fifo_GND ( + .G(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_llm32_fc_fifo_GND_2434) + ); + FDR com_llm_llm_tx_top_llmx08_tx_dllp_jefe_llm32_fc_fifo_data_count_0_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_llm32_fc_fifo_un1_data_count_3_axb_0_2442), + .Q(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_llm32_fc_fifo_data_count[0]), + .R(plm_link_up_i) + ); + FDR com_llm_llm_tx_top_llmx08_tx_dllp_jefe_llm32_fc_fifo_data_count_1_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_llm32_fc_fifo_un1_data_count_3_s_1_2435), + .Q(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_llm32_fc_fifo_data_count[1]), + .R(plm_link_up_i) + ); + FDR com_llm_llm_tx_top_llmx08_tx_dllp_jefe_llm32_fc_fifo_data_count_2_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_llm32_fc_fifo_un1_data_count_3_s_2_2437), + .Q(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_llm32_fc_fifo_data_count[2]), + .R(plm_link_up_i) + ); + FDR com_llm_llm_tx_top_llmx08_tx_dllp_jefe_llm32_fc_fifo_data_count_3_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_llm32_fc_fifo_un1_data_count_3_s_3_2439), + .Q(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_llm32_fc_fifo_data_count[3]), + .R(plm_link_up_i) + ); + FDSE com_llm_llm_tx_top_llmx08_tx_dllp_jefe_llm32_fc_fifo_empty ( + .CE(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_llm32_fc_fifo_N_87129_i_2441), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_N_63252_i), + .Q(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_fc_queue_empty), + .S(plm_link_up_i) + ); + FDRE com_llm_llm_tx_top_llmx08_tx_dllp_jefe_llm32_fc_fifo_full ( + .CE(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_llm32_fc_fifo_un1_rd_en_4_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_N_56110_i), + .Q(com_lnk_tfc_dst_rdy_n), + .R(plm_link_up_i) + ); + MUXCY_L com_llm_llm_tx_top_llmx08_tx_dllp_jefe_llm32_fc_fifo_un1_data_count_3_cry_0 ( + .CI(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_llm32_fc_fifo_GND_2434), + .DI(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_llm32_fc_fifo_data_count[0]), + .LO(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_llm32_fc_fifo_un1_data_count_3_cry_0_2436), + .S(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_llm32_fc_fifo_un1_data_count_3_axb_0_2442) + ); + MUXCY_L com_llm_llm_tx_top_llmx08_tx_dllp_jefe_llm32_fc_fifo_un1_data_count_3_cry_1 ( + .CI(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_llm32_fc_fifo_un1_data_count_3_cry_0_2436), + .DI(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_llm32_fc_fifo_data_count[1]), + .LO(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_llm32_fc_fifo_un1_data_count_3_cry_1_2438), + .S(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_llm32_fc_fifo_un1_data_count_3_axb_1_2445) + ); + XORCY com_llm_llm_tx_top_llmx08_tx_dllp_jefe_llm32_fc_fifo_un1_data_count_3_s_1 ( + .CI(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_llm32_fc_fifo_un1_data_count_3_cry_0_2436), + .LI(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_llm32_fc_fifo_un1_data_count_3_axb_1_2445), + .O(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_llm32_fc_fifo_un1_data_count_3_s_1_2435) + ); + MUXCY_L com_llm_llm_tx_top_llmx08_tx_dllp_jefe_llm32_fc_fifo_un1_data_count_3_cry_2 ( + .CI(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_llm32_fc_fifo_un1_data_count_3_cry_1_2438), + .DI(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_llm32_fc_fifo_data_count[2]), + .LO(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_llm32_fc_fifo_un1_data_count_3_cry_2_2440), + .S(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_llm32_fc_fifo_un1_data_count_3_axb_2_2444) + ); + XORCY com_llm_llm_tx_top_llmx08_tx_dllp_jefe_llm32_fc_fifo_un1_data_count_3_s_2 ( + .CI(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_llm32_fc_fifo_un1_data_count_3_cry_1_2438), + .LI(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_llm32_fc_fifo_un1_data_count_3_axb_2_2444), + .O(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_llm32_fc_fifo_un1_data_count_3_s_2_2437) + ); + XORCY com_llm_llm_tx_top_llmx08_tx_dllp_jefe_llm32_fc_fifo_un1_data_count_3_s_3 ( + .CI(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_llm32_fc_fifo_un1_data_count_3_cry_2_2440), + .LI(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_llm32_fc_fifo_un1_data_count_3_axb_3_2443), + .O(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_llm32_fc_fifo_un1_data_count_3_s_3_2439) + ); + defparam com_llm_llm_tx_top_llmx08_tx_dllp_jefe_llm32_fc_fifo_un1_wr_en_7_0_0_0_0_a2_1_0_.INIT = 16'h0001; + LUT4 com_llm_llm_tx_top_llmx08_tx_dllp_jefe_llm32_fc_fifo_un1_wr_en_7_0_0_0_0_a2_1_0_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_llm32_fc_fifo_data_count[0]), + .I1(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_llm32_fc_fifo_data_count[1]), + .I2(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_llm32_fc_fifo_data_count[2]), + .I3(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_llm32_fc_fifo_data_count[3]), + .O(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_llm32_fc_fifo_N_58429_2) + ); + defparam com_llm_llm_tx_top_llmx08_tx_dllp_jefe_llm32_fc_fifo_un1_wr_en_7_0_0_0_0_0_0_.INIT = 16'h1D0C; + LUT4 com_llm_llm_tx_top_llmx08_tx_dllp_jefe_llm32_fc_fifo_un1_wr_en_7_0_0_0_0_0_0_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_llm32_fc_fifo_N_58429_2), + .I1(com_un1_lnk_tfc_dst_rdy_i_0_o2_i_a2), + .I2(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_fc_queue_empty), + .I3(plm_link_up_1), + .O(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_llm32_fc_fifo_un1_wr_en_7_0_0_0_0_0[0]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_dllp_jefe_llm32_fc_fifo_N_87129_i.INIT = 16'hF404; + LUT4 com_llm_llm_tx_top_llmx08_tx_dllp_jefe_llm32_fc_fifo_N_87129_i ( + .I0(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_N_56110_i), + .I1(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_llm32_fc_fifo_N_58429_2), + .I2(com_un1_lnk_tfc_dst_rdy_i_0_o2_i_a2), + .I3(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_fc_queue_empty), + .O(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_llm32_fc_fifo_N_87129_i_2441) + ); + defparam com_llm_llm_tx_top_llmx08_tx_dllp_jefe_llm32_fc_fifo_un1_data_count_3_axb_0.INIT = 16'h6F90; + LUT4 com_llm_llm_tx_top_llmx08_tx_dllp_jefe_llm32_fc_fifo_un1_data_count_3_axb_0 ( + .I0(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_N_56110_i), + .I1(com_un1_lnk_tfc_dst_rdy_i_0_o2_i_a2), + .I2(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_llm32_fc_fifo_un1_wr_en_7_0_0_0_0_0[0]), + .I3(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_llm32_fc_fifo_data_count[0]), + .O(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_llm32_fc_fifo_un1_data_count_3_axb_0_2442) + ); + defparam com_llm_llm_tx_top_llmx08_tx_dllp_jefe_llm32_fc_fifo_un1_data_count_3_axb_3.INIT = 16'hFD02; + LUT4_L com_llm_llm_tx_top_llmx08_tx_dllp_jefe_llm32_fc_fifo_un1_data_count_3_axb_3 ( + .I0(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_N_15711_i), + .I1(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_llm32_fc_fifo_N_58429_2), + .I2(com_un1_lnk_tfc_dst_rdy_i_0_o2_i_a2), + .I3(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_llm32_fc_fifo_data_count[3]), + .LO(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_llm32_fc_fifo_un1_data_count_3_axb_3_2443) + ); + defparam com_llm_llm_tx_top_llmx08_tx_dllp_jefe_llm32_fc_fifo_un1_data_count_3_axb_2.INIT = 16'hFD02; + LUT4_L com_llm_llm_tx_top_llmx08_tx_dllp_jefe_llm32_fc_fifo_un1_data_count_3_axb_2 ( + .I0(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_N_15711_i), + .I1(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_llm32_fc_fifo_N_58429_2), + .I2(com_un1_lnk_tfc_dst_rdy_i_0_o2_i_a2), + .I3(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_llm32_fc_fifo_data_count[2]), + .LO(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_llm32_fc_fifo_un1_data_count_3_axb_2_2444) + ); + defparam com_llm_llm_tx_top_llmx08_tx_dllp_jefe_llm32_fc_fifo_un1_data_count_3_axb_1.INIT = 16'hFD02; + LUT4_L com_llm_llm_tx_top_llmx08_tx_dllp_jefe_llm32_fc_fifo_un1_data_count_3_axb_1 ( + .I0(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_N_15711_i), + .I1(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_llm32_fc_fifo_N_58429_2), + .I2(com_un1_lnk_tfc_dst_rdy_i_0_o2_i_a2), + .I3(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_llm32_fc_fifo_data_count[1]), + .LO(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_llm32_fc_fifo_un1_data_count_3_axb_1_2445) + ); + defparam com_llm_llm_tx_top_llmx08_tx_dllp_jefe_llm32_fc_fifo_tx_fc_queue_empty_i.INIT = 4'h1; + LUT1_L com_llm_llm_tx_top_llmx08_tx_dllp_jefe_llm32_fc_fifo_tx_fc_queue_empty_i ( + .I0(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_fc_queue_empty), + .LO(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_fc_queue_empty_i) + ); + defparam com_llm_llm_tx_top_llmx08_tx_dllp_jefe_llm32_fc_fifo_un1_rd_en_4_0_0_0_0_1.INIT = 8'h40; + LUT3 com_llm_llm_tx_top_llmx08_tx_dllp_jefe_llm32_fc_fifo_un1_rd_en_4_0_0_0_0_1 ( + .I0(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_llm32_fc_fifo_data_count[0]), + .I1(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_llm32_fc_fifo_data_count[1]), + .I2(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_llm32_fc_fifo_data_count[2]), + .O(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_llm32_fc_fifo_un1_rd_en_4_0_0_0_0_1_2446) + ); + defparam com_llm_llm_tx_top_llmx08_tx_dllp_jefe_llm32_fc_fifo_un1_rd_en_4_0_0_0_0.INIT = 16'h9111; + LUT4 com_llm_llm_tx_top_llmx08_tx_dllp_jefe_llm32_fc_fifo_un1_rd_en_4_0_0_0_0 ( + .I0(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_N_56110_i), + .I1(com_un1_lnk_tfc_dst_rdy_i_0_o2_i_a2), + .I2(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_llm32_fc_fifo_un1_rd_en_4_0_0_0_0_1_2446), + .I3(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_llm32_fc_fifo_data_count[3]), + .O(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_llm32_fc_fifo_un1_rd_en_4_i) + ); + SRL16E com_llm_llm_tx_top_llmx08_tx_dllp_jefe_llm32_fc_fifo_llm32_fifo16_srl_regBank_I_1 ( + .CE(com_un1_lnk_tfc_dst_rdy_i_0_o2_i_a2), + .D(com_lnk_tfc_type[2]), + .Q(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_fc_dout_30_), + .CLK(NlwRenamedSig_OI_trn_clk), + .A0(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_llm32_fc_fifo_data_count[0]), + .A1(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_llm32_fc_fifo_data_count[1]), + .A2(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_llm32_fc_fifo_data_count[2]), + .A3(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_llm32_fc_fifo_data_count[3]) + ); + SRL16E com_llm_llm_tx_top_llmx08_tx_dllp_jefe_llm32_fc_fifo_llm32_fifo16_srl_regBank_I_2 ( + .CE(com_un1_lnk_tfc_dst_rdy_i_0_o2_i_a2), + .D(com_lnk_tfc_type[1]), + .Q(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_fc_dout_29_), + .CLK(NlwRenamedSig_OI_trn_clk), + .A0(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_llm32_fc_fifo_data_count[0]), + .A1(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_llm32_fc_fifo_data_count[1]), + .A2(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_llm32_fc_fifo_data_count[2]), + .A3(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_llm32_fc_fifo_data_count[3]) + ); + SRL16E com_llm_llm_tx_top_llmx08_tx_dllp_jefe_llm32_fc_fifo_llm32_fifo16_srl_regBank_I_3 ( + .CE(com_un1_lnk_tfc_dst_rdy_i_0_o2_i_a2), + .D(com_lnk_tfc_header[5]), + .Q(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_fc_dout_19_), + .CLK(NlwRenamedSig_OI_trn_clk), + .A0(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_llm32_fc_fifo_data_count[0]), + .A1(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_llm32_fc_fifo_data_count[1]), + .A2(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_llm32_fc_fifo_data_count[2]), + .A3(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_llm32_fc_fifo_data_count[3]) + ); + SRL16E com_llm_llm_tx_top_llmx08_tx_dllp_jefe_llm32_fc_fifo_llm32_fifo16_srl_regBank_I_4 ( + .CE(com_un1_lnk_tfc_dst_rdy_i_0_o2_i_a2), + .D(com_lnk_tfc_data[8]), + .Q(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_fc_dout_8_), + .CLK(NlwRenamedSig_OI_trn_clk), + .A0(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_llm32_fc_fifo_data_count[0]), + .A1(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_llm32_fc_fifo_data_count[1]), + .A2(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_llm32_fc_fifo_data_count[2]), + .A3(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_llm32_fc_fifo_data_count[3]) + ); + SRL16E com_llm_llm_tx_top_llmx08_tx_dllp_jefe_llm32_fc_fifo_llm32_fifo16_srl_regBank_I_5 ( + .CE(com_un1_lnk_tfc_dst_rdy_i_0_o2_i_a2), + .D(com_lnk_tfc_data[2]), + .Q(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_fc_dout_2_), + .CLK(NlwRenamedSig_OI_trn_clk), + .A0(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_llm32_fc_fifo_data_count[0]), + .A1(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_llm32_fc_fifo_data_count[1]), + .A2(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_llm32_fc_fifo_data_count[2]), + .A3(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_llm32_fc_fifo_data_count[3]) + ); + SRL16E com_llm_llm_tx_top_llmx08_tx_dllp_jefe_llm32_fc_fifo_llm32_fifo16_srl_regBank_I_6 ( + .CE(com_un1_lnk_tfc_dst_rdy_i_0_o2_i_a2), + .D(com_lnk_tfc_data[9]), + .Q(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_fc_dout_9_), + .CLK(NlwRenamedSig_OI_trn_clk), + .A0(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_llm32_fc_fifo_data_count[0]), + .A1(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_llm32_fc_fifo_data_count[1]), + .A2(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_llm32_fc_fifo_data_count[2]), + .A3(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_llm32_fc_fifo_data_count[3]) + ); + SRL16E com_llm_llm_tx_top_llmx08_tx_dllp_jefe_llm32_fc_fifo_llm32_fifo16_srl_regBank_I_7 ( + .CE(com_un1_lnk_tfc_dst_rdy_i_0_o2_i_a2), + .D(com_lnk_tfc_data[6]), + .Q(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_fc_dout_6_), + .CLK(NlwRenamedSig_OI_trn_clk), + .A0(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_llm32_fc_fifo_data_count[0]), + .A1(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_llm32_fc_fifo_data_count[1]), + .A2(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_llm32_fc_fifo_data_count[2]), + .A3(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_llm32_fc_fifo_data_count[3]) + ); + SRL16E com_llm_llm_tx_top_llmx08_tx_dllp_jefe_llm32_fc_fifo_llm32_fifo16_srl_regBank_I_8 ( + .CE(com_un1_lnk_tfc_dst_rdy_i_0_o2_i_a2), + .D(com_lnk_tfc_data[10]), + .Q(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_fc_dout_10_), + .CLK(NlwRenamedSig_OI_trn_clk), + .A0(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_llm32_fc_fifo_data_count[0]), + .A1(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_llm32_fc_fifo_data_count[1]), + .A2(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_llm32_fc_fifo_data_count[2]), + .A3(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_llm32_fc_fifo_data_count[3]) + ); + SRL16E com_llm_llm_tx_top_llmx08_tx_dllp_jefe_llm32_fc_fifo_llm32_fifo16_srl_regBank_I_9 ( + .CE(com_un1_lnk_tfc_dst_rdy_i_0_o2_i_a2), + .D(com_lnk_tfc_data[4]), + .Q(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_fc_dout_4_), + .CLK(NlwRenamedSig_OI_trn_clk), + .A0(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_llm32_fc_fifo_data_count[0]), + .A1(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_llm32_fc_fifo_data_count[1]), + .A2(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_llm32_fc_fifo_data_count[2]), + .A3(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_llm32_fc_fifo_data_count[3]) + ); + SRL16E com_llm_llm_tx_top_llmx08_tx_dllp_jefe_llm32_fc_fifo_llm32_fifo16_srl_regBank_I_10 ( + .CE(com_un1_lnk_tfc_dst_rdy_i_0_o2_i_a2), + .D(com_lnk_tfc_data[11]), + .Q(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_fc_dout_11_), + .CLK(NlwRenamedSig_OI_trn_clk), + .A0(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_llm32_fc_fifo_data_count[0]), + .A1(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_llm32_fc_fifo_data_count[1]), + .A2(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_llm32_fc_fifo_data_count[2]), + .A3(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_llm32_fc_fifo_data_count[3]) + ); + SRL16E com_llm_llm_tx_top_llmx08_tx_dllp_jefe_llm32_fc_fifo_llm32_fifo16_srl_regBank_I_11 ( + .CE(com_un1_lnk_tfc_dst_rdy_i_0_o2_i_a2), + .D(com_lnk_tfc_data[5]), + .Q(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_fc_dout_5_), + .CLK(NlwRenamedSig_OI_trn_clk), + .A0(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_llm32_fc_fifo_data_count[0]), + .A1(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_llm32_fc_fifo_data_count[1]), + .A2(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_llm32_fc_fifo_data_count[2]), + .A3(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_llm32_fc_fifo_data_count[3]) + ); + SRL16E com_llm_llm_tx_top_llmx08_tx_dllp_jefe_llm32_fc_fifo_llm32_fifo16_srl_regBank_I_13 ( + .CE(com_un1_lnk_tfc_dst_rdy_i_0_o2_i_a2), + .D(com_lnk_tfc_type[3]), + .Q(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_fc_dout_31_), + .CLK(NlwRenamedSig_OI_trn_clk), + .A0(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_llm32_fc_fifo_data_count[0]), + .A1(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_llm32_fc_fifo_data_count[1]), + .A2(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_llm32_fc_fifo_data_count[2]), + .A3(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_llm32_fc_fifo_data_count[3]) + ); + SRL16E com_llm_llm_tx_top_llmx08_tx_dllp_jefe_llm32_fc_fifo_llm32_fifo16_srl_regBank_I_15 ( + .CE(com_un1_lnk_tfc_dst_rdy_i_0_o2_i_a2), + .D(com_lnk_tfc_header[6]), + .Q(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_fc_dout_20_), + .CLK(NlwRenamedSig_OI_trn_clk), + .A0(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_llm32_fc_fifo_data_count[0]), + .A1(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_llm32_fc_fifo_data_count[1]), + .A2(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_llm32_fc_fifo_data_count[2]), + .A3(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_llm32_fc_fifo_data_count[3]) + ); + SRL16E com_llm_llm_tx_top_llmx08_tx_dllp_jefe_llm32_fc_fifo_llm32_fifo16_srl_regBank_I_16 ( + .CE(com_un1_lnk_tfc_dst_rdy_i_0_o2_i_a2), + .D(com_lnk_tfc_header[0]), + .Q(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_fc_dout_14_), + .CLK(NlwRenamedSig_OI_trn_clk), + .A0(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_llm32_fc_fifo_data_count[0]), + .A1(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_llm32_fc_fifo_data_count[1]), + .A2(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_llm32_fc_fifo_data_count[2]), + .A3(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_llm32_fc_fifo_data_count[3]) + ); + SRL16E com_llm_llm_tx_top_llmx08_tx_dllp_jefe_llm32_fc_fifo_llm32_fifo16_srl_regBank_I_17 ( + .CE(com_un1_lnk_tfc_dst_rdy_i_0_o2_i_a2), + .D(com_lnk_tfc_header[7]), + .Q(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_fc_dout_21_), + .CLK(NlwRenamedSig_OI_trn_clk), + .A0(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_llm32_fc_fifo_data_count[0]), + .A1(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_llm32_fc_fifo_data_count[1]), + .A2(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_llm32_fc_fifo_data_count[2]), + .A3(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_llm32_fc_fifo_data_count[3]) + ); + SRL16E com_llm_llm_tx_top_llmx08_tx_dllp_jefe_llm32_fc_fifo_llm32_fifo16_srl_regBank_I_18 ( + .CE(com_un1_lnk_tfc_dst_rdy_i_0_o2_i_a2), + .D(com_lnk_tfc_header[1]), + .Q(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_fc_dout_15_), + .CLK(NlwRenamedSig_OI_trn_clk), + .A0(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_llm32_fc_fifo_data_count[0]), + .A1(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_llm32_fc_fifo_data_count[1]), + .A2(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_llm32_fc_fifo_data_count[2]), + .A3(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_llm32_fc_fifo_data_count[3]) + ); + SRL16E com_llm_llm_tx_top_llmx08_tx_dllp_jefe_llm32_fc_fifo_llm32_fifo16_srl_regBank_I_20 ( + .CE(com_un1_lnk_tfc_dst_rdy_i_0_o2_i_a2), + .D(com_lnk_tfc_data[0]), + .Q(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_fc_dout_0_), + .CLK(NlwRenamedSig_OI_trn_clk), + .A0(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_llm32_fc_fifo_data_count[0]), + .A1(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_llm32_fc_fifo_data_count[1]), + .A2(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_llm32_fc_fifo_data_count[2]), + .A3(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_llm32_fc_fifo_data_count[3]) + ); + SRL16E com_llm_llm_tx_top_llmx08_tx_dllp_jefe_llm32_fc_fifo_llm32_fifo16_srl_regBank_I_22 ( + .CE(com_un1_lnk_tfc_dst_rdy_i_0_o2_i_a2), + .D(com_lnk_tfc_header[3]), + .Q(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_fc_dout_17_), + .CLK(NlwRenamedSig_OI_trn_clk), + .A0(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_llm32_fc_fifo_data_count[0]), + .A1(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_llm32_fc_fifo_data_count[1]), + .A2(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_llm32_fc_fifo_data_count[2]), + .A3(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_llm32_fc_fifo_data_count[3]) + ); + SRL16E com_llm_llm_tx_top_llmx08_tx_dllp_jefe_llm32_fc_fifo_llm32_fifo16_srl_regBank_I_24 ( + .CE(com_un1_lnk_tfc_dst_rdy_i_0_o2_i_a2), + .D(com_lnk_tfc_header[4]), + .Q(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_fc_dout_18_), + .CLK(NlwRenamedSig_OI_trn_clk), + .A0(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_llm32_fc_fifo_data_count[0]), + .A1(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_llm32_fc_fifo_data_count[1]), + .A2(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_llm32_fc_fifo_data_count[2]), + .A3(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_llm32_fc_fifo_data_count[3]) + ); + SRL16E com_llm_llm_tx_top_llmx08_tx_dllp_jefe_llm32_fc_fifo_llm32_fifo16_srl_regBank_I_26 ( + .CE(com_un1_lnk_tfc_dst_rdy_i_0_o2_i_a2), + .D(com_lnk_tfc_header[2]), + .Q(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_fc_dout_16_), + .CLK(NlwRenamedSig_OI_trn_clk), + .A0(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_llm32_fc_fifo_data_count[0]), + .A1(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_llm32_fc_fifo_data_count[1]), + .A2(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_llm32_fc_fifo_data_count[2]), + .A3(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_llm32_fc_fifo_data_count[3]) + ); + SRL16E com_llm_llm_tx_top_llmx08_tx_dllp_jefe_llm32_fc_fifo_llm32_fifo16_srl_regBank_I_29 ( + .CE(com_un1_lnk_tfc_dst_rdy_i_0_o2_i_a2), + .D(com_lnk_tfc_type[0]), + .Q(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_fc_dout_28_), + .CLK(NlwRenamedSig_OI_trn_clk), + .A0(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_llm32_fc_fifo_data_count[0]), + .A1(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_llm32_fc_fifo_data_count[1]), + .A2(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_llm32_fc_fifo_data_count[2]), + .A3(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_llm32_fc_fifo_data_count[3]) + ); + SRL16E com_llm_llm_tx_top_llmx08_tx_dllp_jefe_llm32_fc_fifo_llm32_fifo16_srl_regBank_I_30 ( + .CE(com_un1_lnk_tfc_dst_rdy_i_0_o2_i_a2), + .D(com_lnk_tfc_data[3]), + .Q(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_fc_dout_3_), + .CLK(NlwRenamedSig_OI_trn_clk), + .A0(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_llm32_fc_fifo_data_count[0]), + .A1(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_llm32_fc_fifo_data_count[1]), + .A2(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_llm32_fc_fifo_data_count[2]), + .A3(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_llm32_fc_fifo_data_count[3]) + ); + SRL16E com_llm_llm_tx_top_llmx08_tx_dllp_jefe_llm32_fc_fifo_llm32_fifo16_srl_regBank_I_31 ( + .CE(com_un1_lnk_tfc_dst_rdy_i_0_o2_i_a2), + .D(com_lnk_tfc_data[1]), + .Q(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_fc_dout_1_), + .CLK(NlwRenamedSig_OI_trn_clk), + .A0(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_llm32_fc_fifo_data_count[0]), + .A1(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_llm32_fc_fifo_data_count[1]), + .A2(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_llm32_fc_fifo_data_count[2]), + .A3(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_llm32_fc_fifo_data_count[3]) + ); + SRL16E com_llm_llm_tx_top_llmx08_tx_dllp_jefe_llm32_fc_fifo_llm32_fifo16_srl_regBank_I_32 ( + .CE(com_un1_lnk_tfc_dst_rdy_i_0_o2_i_a2), + .D(com_lnk_tfc_data[7]), + .Q(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_tx_fc_dout_7_), + .CLK(NlwRenamedSig_OI_trn_clk), + .A0(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_llm32_fc_fifo_data_count[0]), + .A1(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_llm32_fc_fifo_data_count[1]), + .A2(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_llm32_fc_fifo_data_count[2]), + .A3(com_llm_llm_tx_top_llmx08_tx_dllp_jefe_llm32_fc_fifo_data_count[3]) + ); + FDS com_llm_llm_tx_top_llmx08_tx_packet_packer_arb_state_0_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_85695_i_2493), + .Q(com_llm_llm_tx_top_reg_tx_pp_idle), + .S(plm_link_up_i) + ); + FDR com_llm_llm_tx_top_llmx08_tx_packet_packer_arb_state_1_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_33961_i), + .Q(com_llm_llm_tx_top_tx_dllp_accepted), + .R(plm_link_up_i) + ); + FDR com_llm_llm_tx_top_llmx08_tx_packet_packer_arb_state_2_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_33959_i), + .Q(com_llm_llm_tx_top_arb_state[2]), + .R(plm_link_up_i) + ); + FDS com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_0_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_51197_i), + .Q(phy_td[0]), + .S(plm_link_up_i) + ); + FDS com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_1_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_51199_i), + .Q(phy_td[1]), + .S(plm_link_up_i) + ); + FDS com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_2_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_51201_i), + .Q(phy_td[2]), + .S(plm_link_up_i) + ); + FDS com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_3_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_51203_i), + .Q(phy_td[3]), + .S(plm_link_up_i) + ); + FDS com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_51205_i), + .Q(phy_td[4]), + .S(plm_link_up_i) + ); + FDS com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_5_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_51207_i), + .Q(phy_td[5]), + .S(plm_link_up_i) + ); + FDS com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_6_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_51209_i), + .Q(phy_td[6]), + .S(plm_link_up_i) + ); + FDS com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_7_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_51211_i), + .Q(phy_td[7]), + .S(plm_link_up_i) + ); + FDR com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_8_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_51213_i), + .Q(phy_td[8]), + .R(plm_link_up_i) + ); + FDR com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_9_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_51215_i), + .Q(phy_td[9]), + .R(plm_link_up_i) + ); + FDR com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_10_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_51217_i), + .Q(phy_td[10]), + .R(plm_link_up_i) + ); + FDR com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_11_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_51219_i), + .Q(phy_td[11]), + .R(plm_link_up_i) + ); + FDR com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_12_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_51221_i), + .Q(phy_td[12]), + .R(plm_link_up_i) + ); + FDR com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_13_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_51223_i), + .Q(phy_td[13]), + .R(plm_link_up_i) + ); + FDR com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_14_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_51225_i), + .Q(phy_td[14]), + .R(plm_link_up_i) + ); + FDR com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_15_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_51227_i), + .Q(phy_td[15]), + .R(plm_link_up_i) + ); + FDR com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_16_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_51229_i), + .Q(phy_td[16]), + .R(plm_link_up_i) + ); + FDR com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_17_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_51231_i), + .Q(phy_td[17]), + .R(plm_link_up_i) + ); + FDR com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_18_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_51233_i), + .Q(phy_td[18]), + .R(plm_link_up_i) + ); + FDR com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_19_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_51235_i), + .Q(phy_td[19]), + .R(plm_link_up_i) + ); + FDR com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_20_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_51237_i), + .Q(phy_td[20]), + .R(plm_link_up_i) + ); + FDR com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_21_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_51239_i), + .Q(phy_td[21]), + .R(plm_link_up_i) + ); + FDR com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_22_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_51241_i), + .Q(phy_td[22]), + .R(plm_link_up_i) + ); + FDR com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_23_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_51243_i), + .Q(phy_td[23]), + .R(plm_link_up_i) + ); + FDR com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_24_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_85711_i_2489), + .Q(phy_td[24]), + .R(plm_link_up_i) + ); + FDR com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_25_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_85712_i_2488), + .Q(phy_td[25]), + .R(plm_link_up_i) + ); + FDR com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_26_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_85713_i_2487), + .Q(phy_td[26]), + .R(plm_link_up_i) + ); + FDR com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_27_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_85714_i_2486), + .Q(phy_td[27]), + .R(plm_link_up_i) + ); + FDR com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_28_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_85715_i_2485), + .Q(phy_td[28]), + .R(plm_link_up_i) + ); + FDR com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_29_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_85716_i_2484), + .Q(phy_td[29]), + .R(plm_link_up_i) + ); + FDR com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_30_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_85717_i_2483), + .Q(phy_td[30]), + .R(plm_link_up_i) + ); + FDR com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_31_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_85718_i_2482), + .Q(phy_td[31]), + .R(plm_link_up_i) + ); + FDR com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_32_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_85719_i_2481), + .Q(phy_td[32]), + .R(plm_link_up_i) + ); + FDR com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_33_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_85720_i_2480), + .Q(phy_td[33]), + .R(plm_link_up_i) + ); + FDR com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_34_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_85721_i_2479), + .Q(phy_td[34]), + .R(plm_link_up_i) + ); + FDR com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_35_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_85722_i_2478), + .Q(phy_td[35]), + .R(plm_link_up_i) + ); + FDR com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_36_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_85723_i_2477), + .Q(phy_td[36]), + .R(plm_link_up_i) + ); + FDR com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_37_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_85724_i_2476), + .Q(phy_td[37]), + .R(plm_link_up_i) + ); + FDR com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_38_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_85700_i_2475), + .Q(phy_td[38]), + .R(plm_link_up_i) + ); + FDR com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_39_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_85699_i_2474), + .Q(phy_td[39]), + .R(plm_link_up_i) + ); + FDR com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_40_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_85725_i_2473), + .Q(phy_td[40]), + .R(plm_link_up_i) + ); + FDR com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_41_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_85726_i_2472), + .Q(phy_td[41]), + .R(plm_link_up_i) + ); + FDR com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_42_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_85727_i_2471), + .Q(phy_td[42]), + .R(plm_link_up_i) + ); + FDR com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_43_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_85728_i_2470), + .Q(phy_td[43]), + .R(plm_link_up_i) + ); + FDR com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_44_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_85729_i_2469), + .Q(phy_td[44]), + .R(plm_link_up_i) + ); + FDR com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_45_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_85730_i_2468), + .Q(phy_td[45]), + .R(plm_link_up_i) + ); + FDR com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_46_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_85731_i_2467), + .Q(phy_td[46]), + .R(plm_link_up_i) + ); + FDR com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_47_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_85732_i_2466), + .Q(phy_td[47]), + .R(plm_link_up_i) + ); + FDR com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_48_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_85733_i_2465), + .Q(phy_td[48]), + .R(plm_link_up_i) + ); + FDR com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_49_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_85698_i_2464), + .Q(phy_td[49]), + .R(plm_link_up_i) + ); + FDR com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_50_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_85734_i_2463), + .Q(phy_td[50]), + .R(plm_link_up_i) + ); + FDR com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_51_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_85735_i_2462), + .Q(phy_td[51]), + .R(plm_link_up_i) + ); + FDR com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_52_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_85736_i_2461), + .Q(phy_td[52]), + .R(plm_link_up_i) + ); + FDR com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_53_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_85737_i_2460), + .Q(phy_td[53]), + .R(plm_link_up_i) + ); + FDR com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_54_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_85738_i_2459), + .Q(phy_td[54]), + .R(plm_link_up_i) + ); + FDR com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_55_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_85739_i_2458), + .Q(phy_td[55]), + .R(plm_link_up_i) + ); + FDS com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_56_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_51277_i), + .Q(phy_td[56]), + .S(plm_link_up_i) + ); + FDS com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_57_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_51279_i), + .Q(phy_td[57]), + .S(plm_link_up_i) + ); + FDS com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_58_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_51281_i), + .Q(phy_td[58]), + .S(plm_link_up_i) + ); + FDS com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_59_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_51283_i), + .Q(phy_td[59]), + .S(plm_link_up_i) + ); + FDS com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_60_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_51285_i), + .Q(phy_td[60]), + .S(plm_link_up_i) + ); + FDS com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_61_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_51287_i), + .Q(phy_td[61]), + .S(plm_link_up_i) + ); + FDS com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_62_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_51289_i), + .Q(phy_td[62]), + .S(plm_link_up_i) + ); + FDS com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_63_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_51291_i), + .Q(phy_td[63]), + .S(plm_link_up_i) + ); + FDR com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_tframe_l ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_51195_i), + .Q(phy_tframe_l), + .R(plm_link_up_i) + ); + FDR com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_tframe_h ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_51193_i), + .Q(phy_tframe_h), + .R(plm_link_up_i) + ); + FDS com_llm_llm_tx_top_llmx08_tx_packet_packer_prev_td_0_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_86916_i_2457), + .Q(com_llm_llm_tx_top_llmx08_tx_packet_packer_prev_td[0]), + .S(plm_link_up_i) + ); + FDS com_llm_llm_tx_top_llmx08_tx_packet_packer_prev_td_1_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_86915_i_2456), + .Q(com_llm_llm_tx_top_llmx08_tx_packet_packer_prev_td[1]), + .S(plm_link_up_i) + ); + FDS com_llm_llm_tx_top_llmx08_tx_packet_packer_prev_td_2_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_86914_i_2455), + .Q(com_llm_llm_tx_top_llmx08_tx_packet_packer_prev_td[2]), + .S(plm_link_up_i) + ); + FDS com_llm_llm_tx_top_llmx08_tx_packet_packer_prev_td_3_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_86913_i_2454), + .Q(com_llm_llm_tx_top_llmx08_tx_packet_packer_prev_td[3]), + .S(plm_link_up_i) + ); + FDS com_llm_llm_tx_top_llmx08_tx_packet_packer_prev_td_4_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_86912_i_2453), + .Q(com_llm_llm_tx_top_llmx08_tx_packet_packer_prev_td[4]), + .S(plm_link_up_i) + ); + FDS com_llm_llm_tx_top_llmx08_tx_packet_packer_prev_td_5_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_86911_i_2452), + .Q(com_llm_llm_tx_top_llmx08_tx_packet_packer_prev_td[5]), + .S(plm_link_up_i) + ); + FDS com_llm_llm_tx_top_llmx08_tx_packet_packer_prev_td_6_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_86939_i_2451), + .Q(com_llm_llm_tx_top_llmx08_tx_packet_packer_prev_td[6]), + .S(plm_link_up_i) + ); + FDS com_llm_llm_tx_top_llmx08_tx_packet_packer_prev_td_7_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_86910_i_2450), + .Q(com_llm_llm_tx_top_llmx08_tx_packet_packer_prev_td[7]), + .S(plm_link_up_i) + ); + FDR com_llm_llm_tx_top_llmx08_tx_packet_packer_prev_td_8_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_packet_packer_current_td[8]), + .Q(com_llm_llm_tx_top_llmx08_tx_packet_packer_prev_td[8]), + .R(plm_link_up_i) + ); + FDR com_llm_llm_tx_top_llmx08_tx_packet_packer_prev_td_9_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_packet_packer_current_td[9]), + .Q(com_llm_llm_tx_top_llmx08_tx_packet_packer_prev_td[9]), + .R(plm_link_up_i) + ); + FDR com_llm_llm_tx_top_llmx08_tx_packet_packer_prev_td_10_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_packet_packer_current_td[10]), + .Q(com_llm_llm_tx_top_llmx08_tx_packet_packer_prev_td[10]), + .R(plm_link_up_i) + ); + FDR com_llm_llm_tx_top_llmx08_tx_packet_packer_prev_td_11_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_packet_packer_current_td[11]), + .Q(com_llm_llm_tx_top_llmx08_tx_packet_packer_prev_td[11]), + .R(plm_link_up_i) + ); + FDR com_llm_llm_tx_top_llmx08_tx_packet_packer_prev_td_12_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_packet_packer_current_td[12]), + .Q(com_llm_llm_tx_top_llmx08_tx_packet_packer_prev_td[12]), + .R(plm_link_up_i) + ); + FDR com_llm_llm_tx_top_llmx08_tx_packet_packer_prev_td_13_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_packet_packer_current_td[13]), + .Q(com_llm_llm_tx_top_llmx08_tx_packet_packer_prev_td[13]), + .R(plm_link_up_i) + ); + FDR com_llm_llm_tx_top_llmx08_tx_packet_packer_prev_td_14_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_packet_packer_current_td[14]), + .Q(com_llm_llm_tx_top_llmx08_tx_packet_packer_prev_td[14]), + .R(plm_link_up_i) + ); + FDR com_llm_llm_tx_top_llmx08_tx_packet_packer_prev_td_15_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_packet_packer_current_td[15]), + .Q(com_llm_llm_tx_top_llmx08_tx_packet_packer_prev_td[15]), + .R(plm_link_up_i) + ); + FDR com_llm_llm_tx_top_llmx08_tx_packet_packer_prev_td_16_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_packet_packer_current_td[16]), + .Q(com_llm_llm_tx_top_llmx08_tx_packet_packer_prev_td[16]), + .R(plm_link_up_i) + ); + FDR com_llm_llm_tx_top_llmx08_tx_packet_packer_prev_td_17_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_packet_packer_current_td[17]), + .Q(com_llm_llm_tx_top_llmx08_tx_packet_packer_prev_td[17]), + .R(plm_link_up_i) + ); + FDR com_llm_llm_tx_top_llmx08_tx_packet_packer_prev_td_18_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_packet_packer_current_td[18]), + .Q(com_llm_llm_tx_top_llmx08_tx_packet_packer_prev_td[18]), + .R(plm_link_up_i) + ); + FDR com_llm_llm_tx_top_llmx08_tx_packet_packer_prev_td_19_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_packet_packer_current_td[19]), + .Q(com_llm_llm_tx_top_llmx08_tx_packet_packer_prev_td[19]), + .R(plm_link_up_i) + ); + FDR com_llm_llm_tx_top_llmx08_tx_packet_packer_prev_td_20_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_packet_packer_current_td[20]), + .Q(com_llm_llm_tx_top_llmx08_tx_packet_packer_prev_td[20]), + .R(plm_link_up_i) + ); + FDR com_llm_llm_tx_top_llmx08_tx_packet_packer_prev_td_21_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_packet_packer_current_td[21]), + .Q(com_llm_llm_tx_top_llmx08_tx_packet_packer_prev_td[21]), + .R(plm_link_up_i) + ); + FDR com_llm_llm_tx_top_llmx08_tx_packet_packer_prev_td_22_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_packet_packer_current_td[22]), + .Q(com_llm_llm_tx_top_llmx08_tx_packet_packer_prev_td[22]), + .R(plm_link_up_i) + ); + FDR com_llm_llm_tx_top_llmx08_tx_packet_packer_prev_td_23_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_packet_packer_current_td[23]), + .Q(com_llm_llm_tx_top_llmx08_tx_packet_packer_prev_td[23]), + .R(plm_link_up_i) + ); + FDR com_llm_llm_tx_top_llmx08_tx_packet_packer_prev_td_24_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_51668_i), + .Q(com_llm_llm_tx_top_llmx08_tx_packet_packer_prev_td[24]), + .R(plm_link_up_i) + ); + FDR com_llm_llm_tx_top_llmx08_tx_packet_packer_prev_td_25_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_51670_i), + .Q(com_llm_llm_tx_top_llmx08_tx_packet_packer_prev_td[25]), + .R(plm_link_up_i) + ); + FDR com_llm_llm_tx_top_llmx08_tx_packet_packer_prev_td_26_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_51672_i), + .Q(com_llm_llm_tx_top_llmx08_tx_packet_packer_prev_td[26]), + .R(plm_link_up_i) + ); + FDR com_llm_llm_tx_top_llmx08_tx_packet_packer_prev_td_27_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_51674_i), + .Q(com_llm_llm_tx_top_llmx08_tx_packet_packer_prev_td[27]), + .R(plm_link_up_i) + ); + FDR com_llm_llm_tx_top_llmx08_tx_packet_packer_prev_td_28_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_51676_i), + .Q(com_llm_llm_tx_top_llmx08_tx_packet_packer_prev_td[28]), + .R(plm_link_up_i) + ); + FDR com_llm_llm_tx_top_llmx08_tx_packet_packer_prev_td_29_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_51678_i), + .Q(com_llm_llm_tx_top_llmx08_tx_packet_packer_prev_td[29]), + .R(plm_link_up_i) + ); + FDR com_llm_llm_tx_top_llmx08_tx_packet_packer_prev_td_30_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_51680_i), + .Q(com_llm_llm_tx_top_llmx08_tx_packet_packer_prev_td[30]), + .R(plm_link_up_i) + ); + FDR com_llm_llm_tx_top_llmx08_tx_packet_packer_prev_td_31_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_51682_i), + .Q(com_llm_llm_tx_top_llmx08_tx_packet_packer_prev_td[31]), + .R(plm_link_up_i) + ); + FDS com_llm_llm_tx_top_llmx08_tx_packet_packer_aligned ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_86829_i_2448), + .Q(com_llm_llm_tx_top_llmx08_tx_packet_packer_aligned_2490), + .S(plm_link_up_i) + ); + FDS com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_tctrl_h ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_56522_i_2447), + .Q(phy_tctrl_h), + .S(plm_link_up_i) + ); + FDRSE com_llm_llm_tx_top_llmx08_tx_packet_packer_tx_idle_next ( + .CE(com_llm_llm_tx_top_llmx08_tx_packet_packer_next_arb_state_0_sqmuxa), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmml_suspend_now_n_i), + .Q(com_llm_llm_tx_top_llmx08_tx_packet_packer_tx_idle_next_2494), + .R(plm_link_up_i), + .S(phy_tstall_n_i) + ); + FDR com_llm_llm_tx_top_llmx08_tx_packet_packer_trans_non_aligned ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_56163_i), + .Q(com_llm_llm_tx_top_llmx08_tx_packet_packer_trans_non_aligned_2449), + .R(plm_link_up_i) + ); + FDS com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_tctrl_l ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_tx_top_llmx08_tx_packet_packer_arb_state_i[2]), + .Q(phy_tctrl_l), + .S(plm_link_up_i) + ); + defparam com_llm_llm_tx_top_llmx08_tx_packet_packer_next_arb_state_i_i_0_o3_2_.INIT = 4'h8; + LUT2 com_llm_llm_tx_top_llmx08_tx_packet_packer_next_arb_state_i_i_0_o3_2_ ( + .I0(com_llm_llm_tx_top_arb_state[2]), + .I1(com_llm_llm_tx_top_tx_tlp_eof_n), + .O(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_56059_i) + ); + defparam com_llm_llm_tx_top_llmx08_tx_packet_packer_next_arb_state_0_i_0_0_a2_3_1_0_.INIT = 4'h1; + LUT2 com_llm_llm_tx_top_llmx08_tx_packet_packer_next_arb_state_0_i_0_0_a2_3_1_0_ ( + .I0(com_llm_llm_tx_top_tx_dllp_tx_next), + .I1(com_llm_llm_tx_top_tx_dllp_tx_next_pre), + .O(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_59258_1) + ); + defparam com_llm_llm_tx_top_llmx08_tx_packet_packer_next_arb_state_0_i_0_0_a2_0_1_0_.INIT = 4'h2; + LUT2 com_llm_llm_tx_top_llmx08_tx_packet_packer_next_arb_state_0_i_0_0_a2_0_1_0_ ( + .I0(com_llm_llm_tx_top_tx_dllp_accepted), + .I1(com_llm_llm_tx_top_tx_dllp_tx_next_pre), + .O(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_59255_1) + ); + defparam com_llm_llm_tx_top_llmx08_tx_packet_packer_next_arb_state_i_i_0_a2_1_1_1_.INIT = 4'h1; + LUT2 com_llm_llm_tx_top_llmx08_tx_packet_packer_next_arb_state_i_i_0_a2_1_1_1_ ( + .I0(com_llm_llm_tx_top_arb_state[2]), + .I1(com_llm_llm_tx_top_tx_tlp_sof_n), + .O(com_llm_llm_tx_top_N_59251_1) + ); + defparam com_llm_llm_tx_top_llmx08_tx_packet_packer_N_44119_i_0_o3.INIT = 4'h2; + LUT2 com_llm_llm_tx_top_llmx08_tx_packet_packer_N_44119_i_0_o3 ( + .I0(com_llm_llm_tx_top_llmx08_tx_packet_packer_aligned_2490), + .I1(com_llm_llm_tx_top_rem_pipe[4]), + .O(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_56163_i) + ); + defparam com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_i_a3_0_.INIT = 4'h4; + LUT2 com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_i_a3_0_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_packet_packer_aligned_2490), + .I1(com_llm_llm_tx_top_reg_tx_pp_idle), + .O(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_61349) + ); + defparam com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_0_a3_24_.INIT = 4'h4; + LUT2 com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_0_a3_24_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_packet_packer_aligned_2490), + .I1(com_llm_llm_tx_top_arb_state[2]), + .O(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_61327) + ); + defparam com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_i_a3_0_0_.INIT = 4'h2; + LUT2 com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_i_a3_0_0_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_packet_packer_aligned_2490), + .I1(com_llm_llm_tx_top_reg_tx_pp_idle), + .O(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_61304) + ); + defparam com_llm_llm_tx_top_llmx08_tx_packet_packer_next_arb_state_0_sqmuxa_0_a2.INIT = 4'h8; + LUT2 com_llm_llm_tx_top_llmx08_tx_packet_packer_next_arb_state_0_sqmuxa_0_a2 ( + .I0(com_llm_llm_tx_top_llmx08_tx_packet_packer_tx_idle_next_2494), + .I1(com_llm_llm_tx_top_reg_tx_pp_idle), + .O(com_llm_llm_tx_top_llmx08_tx_packet_packer_next_arb_state_0_sqmuxa) + ); + defparam com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_0_m3_0_51_.INIT = 4'h8; + LUT2 com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_0_m3_0_51_ ( + .I0(com_llm_llm_tx_top_arb_state[2]), + .I1(com_llm_llm_tx_top_tx_tlp_td[51]), + .O(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_56445) + ); + defparam com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_0_m3_0_50_.INIT = 4'h8; + LUT2 com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_0_m3_0_50_ ( + .I0(com_llm_llm_tx_top_arb_state[2]), + .I1(com_llm_llm_tx_top_tx_tlp_td[50]), + .O(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_56446) + ); + defparam com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_0_m3_0_47_.INIT = 4'h8; + LUT2 com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_0_m3_0_47_ ( + .I0(com_llm_llm_tx_top_arb_state[2]), + .I1(com_llm_llm_tx_top_tx_tlp_td[47]), + .O(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_56449) + ); + defparam com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_0_m3_0_46_.INIT = 4'h8; + LUT2 com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_0_m3_0_46_ ( + .I0(com_llm_llm_tx_top_arb_state[2]), + .I1(com_llm_llm_tx_top_tx_tlp_td[46]), + .O(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_56450) + ); + defparam com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_0_m3_0_55_.INIT = 8'hE4; + LUT3 com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_0_m3_0_55_ ( + .I0(com_llm_llm_tx_top_arb_state[2]), + .I1(com_llm_llm_tx_top_tx_dllp_td_55_), + .I2(com_llm_llm_tx_top_tx_tlp_td[55]), + .O(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_56441) + ); + defparam com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_0_m3_0_54_.INIT = 8'hE4; + LUT3 com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_0_m3_0_54_ ( + .I0(com_llm_llm_tx_top_arb_state[2]), + .I1(com_llm_llm_tx_top_tx_dllp_td_54_), + .I2(com_llm_llm_tx_top_tx_tlp_td[54]), + .O(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_56442) + ); + defparam com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_0_m3_0_53_.INIT = 8'hE4; + LUT3 com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_0_m3_0_53_ ( + .I0(com_llm_llm_tx_top_arb_state[2]), + .I1(com_llm_llm_tx_top_tx_dllp_td_53_), + .I2(com_llm_llm_tx_top_tx_tlp_td[53]), + .O(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_56443) + ); + defparam com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_0_m3_0_52_.INIT = 8'hE4; + LUT3 com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_0_m3_0_52_ ( + .I0(com_llm_llm_tx_top_arb_state[2]), + .I1(com_llm_llm_tx_top_tx_dllp_td_52_), + .I2(com_llm_llm_tx_top_tx_tlp_td[52]), + .O(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_56444) + ); + defparam com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_0_m3_0_48_.INIT = 8'hE4; + LUT3 com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_0_m3_0_48_ ( + .I0(com_llm_llm_tx_top_arb_state[2]), + .I1(com_llm_llm_tx_top_tx_dllp_td_48_), + .I2(com_llm_llm_tx_top_tx_tlp_td[48]), + .O(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_56448) + ); + defparam com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_0_m3_0_45_.INIT = 8'hE4; + LUT3 com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_0_m3_0_45_ ( + .I0(com_llm_llm_tx_top_arb_state[2]), + .I1(com_llm_llm_tx_top_tx_dllp_td_45_), + .I2(com_llm_llm_tx_top_tx_tlp_td[45]), + .O(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_56451) + ); + defparam com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_0_m3_0_43_.INIT = 8'hE4; + LUT3 com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_0_m3_0_43_ ( + .I0(com_llm_llm_tx_top_arb_state[2]), + .I1(com_llm_llm_tx_top_tx_dllp_td_43_), + .I2(com_llm_llm_tx_top_tx_tlp_td[43]), + .O(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_56453) + ); + defparam com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_0_m3_0_42_.INIT = 8'hE4; + LUT3 com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_0_m3_0_42_ ( + .I0(com_llm_llm_tx_top_arb_state[2]), + .I1(com_llm_llm_tx_top_tx_dllp_td_42_), + .I2(com_llm_llm_tx_top_tx_tlp_td[42]), + .O(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_56454) + ); + defparam com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_0_m3_0_41_.INIT = 8'hE4; + LUT3 com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_0_m3_0_41_ ( + .I0(com_llm_llm_tx_top_arb_state[2]), + .I1(com_llm_llm_tx_top_tx_dllp_td_41_), + .I2(com_llm_llm_tx_top_tx_tlp_td[41]), + .O(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_56455) + ); + defparam com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_0_m3_0_40_.INIT = 8'hE4; + LUT3 com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_0_m3_0_40_ ( + .I0(com_llm_llm_tx_top_arb_state[2]), + .I1(com_llm_llm_tx_top_tx_dllp_td_40_), + .I2(com_llm_llm_tx_top_tx_tlp_td[40]), + .O(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_56456) + ); + defparam com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_0_m3_0_35_.INIT = 8'hE4; + LUT3 com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_0_m3_0_35_ ( + .I0(com_llm_llm_tx_top_arb_state[2]), + .I1(com_llm_llm_tx_top_tx_dllp_td_35_), + .I2(com_llm_llm_tx_top_tx_tlp_td[35]), + .O(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_56461) + ); + defparam com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_0_m3_0_34_.INIT = 8'hE4; + LUT3 com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_0_m3_0_34_ ( + .I0(com_llm_llm_tx_top_arb_state[2]), + .I1(com_llm_llm_tx_top_tx_dllp_td_34_), + .I2(com_llm_llm_tx_top_tx_tlp_td[34]), + .O(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_56462) + ); + defparam com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_0_m3_0_33_.INIT = 8'hE4; + LUT3 com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_0_m3_0_33_ ( + .I0(com_llm_llm_tx_top_arb_state[2]), + .I1(com_llm_llm_tx_top_tx_dllp_td_33_), + .I2(com_llm_llm_tx_top_tx_tlp_td[33]), + .O(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_56463) + ); + defparam com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_0_m3_0_32_.INIT = 8'hE4; + LUT3 com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_0_m3_0_32_ ( + .I0(com_llm_llm_tx_top_arb_state[2]), + .I1(com_llm_llm_tx_top_tx_dllp_td_32_), + .I2(com_llm_llm_tx_top_tx_tlp_td[32]), + .O(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_56464) + ); + defparam com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_0_m3_0_38_.INIT = 8'hE4; + LUT3 com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_0_m3_0_38_ ( + .I0(com_llm_llm_tx_top_arb_state[2]), + .I1(com_llm_llm_tx_top_tx_dllp_td_38_), + .I2(com_llm_llm_tx_top_tx_tlp_td[38]), + .O(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_56458) + ); + defparam com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_0_m3_0_39_.INIT = 8'hE4; + LUT3 com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_0_m3_0_39_ ( + .I0(com_llm_llm_tx_top_arb_state[2]), + .I1(com_llm_llm_tx_top_tx_dllp_td_39_), + .I2(com_llm_llm_tx_top_tx_tlp_td[39]), + .O(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_56457) + ); + defparam com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_0_m3_0_44_.INIT = 8'hE4; + LUT3 com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_0_m3_0_44_ ( + .I0(com_llm_llm_tx_top_arb_state[2]), + .I1(com_llm_llm_tx_top_tx_dllp_td_44_), + .I2(com_llm_llm_tx_top_tx_tlp_td[44]), + .O(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_56452) + ); + defparam com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_0_m3_0_49_.INIT = 8'hE4; + LUT3 com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_0_m3_0_49_ ( + .I0(com_llm_llm_tx_top_arb_state[2]), + .I1(com_llm_llm_tx_top_tx_dllp_td_49_), + .I2(com_llm_llm_tx_top_tx_tlp_td[49]), + .O(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_56447) + ); + defparam com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_i_a2_0_7_.INIT = 4'h2; + LUT2_L com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_i_a2_0_7_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_61304), + .I1(com_llm_llm_tx_top_tx_tlp_td[7]), + .LO(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_57409) + ); + defparam com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_i_a2_0_6_.INIT = 4'h2; + LUT2_L com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_i_a2_0_6_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_61304), + .I1(com_llm_llm_tx_top_tx_tlp_td[6]), + .LO(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_57407) + ); + defparam com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_i_a2_5_.INIT = 8'h15; + LUT3 com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_i_a2_5_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_packet_packer_aligned_2490), + .I1(com_llm_llm_tx_top_arb_state[2]), + .I2(com_llm_llm_tx_top_tx_tlp_td[37]), + .O(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_57404) + ); + defparam com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_i_a2_4_.INIT = 8'h15; + LUT3 com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_i_a2_4_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_packet_packer_aligned_2490), + .I1(com_llm_llm_tx_top_arb_state[2]), + .I2(com_llm_llm_tx_top_tx_tlp_td[36]), + .O(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_57402) + ); + defparam com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_i_a2_0_3_.INIT = 4'h2; + LUT2_L com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_i_a2_0_3_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_61304), + .I1(com_llm_llm_tx_top_tx_tlp_td[3]), + .LO(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_57401) + ); + defparam com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_i_a2_0_2_.INIT = 4'h2; + LUT2_L com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_i_a2_0_2_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_61304), + .I1(com_llm_llm_tx_top_tx_tlp_td[2]), + .LO(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_57399) + ); + defparam com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_i_a2_0_1_.INIT = 4'h2; + LUT2_L com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_i_a2_0_1_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_61304), + .I1(com_llm_llm_tx_top_tx_tlp_td[1]), + .LO(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_57397) + ); + defparam com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_i_a2_0_0_.INIT = 4'h2; + LUT2_L com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_i_a2_0_0_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_61304), + .I1(com_llm_llm_tx_top_tx_tlp_td[0]), + .LO(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_57395) + ); + defparam com_llm_llm_tx_top_llmx08_tx_packet_packer_next_arb_state_0_i_0_0_a2_3_5_0_.INIT = 8'h20; + LUT3 com_llm_llm_tx_top_llmx08_tx_packet_packer_next_arb_state_0_i_0_0_a2_3_5_0_ ( + .I0(com_llm_llm_tx_top_arb_state[2]), + .I1(com_llm_llm_tx_top_tx_tlp_eof_n), + .I2(com_llm_llm_tx_top_tx_tlp_sof_pre_n), + .O(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_59258_5) + ); + defparam com_llm_llm_tx_top_llmx08_tx_packet_packer_next_arb_state_0_i_0_0_a2_0_0_0_.INIT = 4'h8; + LUT2 com_llm_llm_tx_top_llmx08_tx_packet_packer_next_arb_state_0_i_0_0_a2_0_0_0_ ( + .I0(com_llm_llm_tx_top_N_56164_i), + .I1(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_59255_1), + .O(com_llm_llm_tx_top_llmx08_tx_packet_packer_next_arb_state_0_i_0_0_a2_0_0[0]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_0_a2_31_.INIT = 16'hA820; + LUT4_L com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_0_a2_31_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_61304), + .I1(com_llm_llm_tx_top_arb_state[2]), + .I2(com_llm_llm_tx_top_tx_dllp_td_31_), + .I3(com_llm_llm_tx_top_tx_tlp_td[31]), + .LO(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_57425) + ); + defparam com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_0_a2_30_.INIT = 16'hA820; + LUT4_L com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_0_a2_30_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_61304), + .I1(com_llm_llm_tx_top_arb_state[2]), + .I2(com_llm_llm_tx_top_tx_dllp_td_30_), + .I3(com_llm_llm_tx_top_tx_tlp_td[30]), + .LO(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_57423) + ); + defparam com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_0_a2_29_.INIT = 16'hA820; + LUT4_L com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_0_a2_29_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_61304), + .I1(com_llm_llm_tx_top_arb_state[2]), + .I2(com_llm_llm_tx_top_tx_dllp_td_29_), + .I3(com_llm_llm_tx_top_tx_tlp_td[29]), + .LO(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_57421) + ); + defparam com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_0_a2_28_.INIT = 16'hA820; + LUT4_L com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_0_a2_28_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_61304), + .I1(com_llm_llm_tx_top_arb_state[2]), + .I2(com_llm_llm_tx_top_tx_dllp_td_28_), + .I3(com_llm_llm_tx_top_tx_tlp_td[28]), + .LO(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_57419) + ); + defparam com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_0_a2_27_.INIT = 16'hA820; + LUT4_L com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_0_a2_27_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_61304), + .I1(com_llm_llm_tx_top_arb_state[2]), + .I2(com_llm_llm_tx_top_tx_dllp_td_27_), + .I3(com_llm_llm_tx_top_tx_tlp_td[27]), + .LO(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_57417) + ); + defparam com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_0_a2_26_.INIT = 16'hA820; + LUT4_L com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_0_a2_26_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_61304), + .I1(com_llm_llm_tx_top_arb_state[2]), + .I2(com_llm_llm_tx_top_tx_dllp_td_26_), + .I3(com_llm_llm_tx_top_tx_tlp_td[26]), + .LO(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_57415) + ); + defparam com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_0_a2_25_.INIT = 16'hA820; + LUT4_L com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_0_a2_25_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_61304), + .I1(com_llm_llm_tx_top_arb_state[2]), + .I2(com_llm_llm_tx_top_tx_dllp_td_25_), + .I3(com_llm_llm_tx_top_tx_tlp_td[25]), + .LO(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_57413) + ); + defparam com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_0_a2_24_.INIT = 16'hA820; + LUT4_L com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_0_a2_24_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_61304), + .I1(com_llm_llm_tx_top_arb_state[2]), + .I2(com_llm_llm_tx_top_tx_dllp_td_24_), + .I3(com_llm_llm_tx_top_tx_tlp_td[24]), + .LO(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_57410) + ); + defparam com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_i_o2_0_.INIT = 8'hAD; + LUT3 com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_i_o2_0_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_packet_packer_aligned_2490), + .I1(com_llm_llm_tx_top_arb_state[2]), + .I2(com_llm_llm_tx_top_reg_tx_pp_idle), + .O(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_56006_i) + ); + defparam com_llm_llm_tx_top_llmx08_tx_packet_packer_next_arb_state_i_i_0_o3_1_.INIT = 16'h0100; + LUT4 com_llm_llm_tx_top_llmx08_tx_packet_packer_next_arb_state_i_i_0_o3_1_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_56163_i), + .I1(com_llm_llm_tx_top_reg_tx_pp_idle), + .I2(com_llm_llm_tx_top_tx_dllp_accepted), + .I3(com_llm_llm_tx_top_tx_tlp_eof_n), + .O(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_56940_i) + ); + defparam com_llm_llm_tx_top_llmx08_tx_packet_packer_next_arb_state_i_i_0_a2_3_2_.INIT = 16'h0200; + LUT4_L com_llm_llm_tx_top_llmx08_tx_packet_packer_next_arb_state_i_i_0_a2_3_2_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_61304), + .I1(com_llm_llm_tx_top_rem_pipe[4]), + .I2(com_llm_llm_tx_top_tx_dllp_accepted), + .I3(com_llm_llm_tx_top_tx_tlp_eof_n), + .LO(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_59248) + ); + defparam com_llm_llm_tx_top_llmx08_tx_packet_packer_next_arb_state_i_i_0_2_39366.INIT = 16'h2223; + LUT4 com_llm_llm_tx_top_llmx08_tx_packet_packer_next_arb_state_i_i_0_2_39366 ( + .I0(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_56059_i), + .I1(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_59258_5), + .I2(com_llm_llm_tx_top_llmx08_tx_packet_packer_tx_idle_next_2494), + .I3(com_llm_llm_tx_top_tx_dllp_tx_next_pre), + .O(com_llm_llm_tx_top_llmx08_tx_packet_packer_next_arb_state_i_i_0_2_39366_2492) + ); + defparam com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_0_0_53_.INIT = 16'hABFB; + LUT4 com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_0_0_53_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_packet_packer_aligned_2490), + .I1(com_llm_llm_tx_top_llmx08_tx_packet_packer_prev_td[21]), + .I2(com_llm_llm_tx_top_llmx08_tx_packet_packer_trans_non_aligned_2449), + .I3(com_llm_llm_tx_top_tx_tlp_td[53]), + .O(com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_0_0[53]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_0_0_45_.INIT = 16'hABFB; + LUT4 com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_0_0_45_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_packet_packer_aligned_2490), + .I1(com_llm_llm_tx_top_llmx08_tx_packet_packer_prev_td[13]), + .I2(com_llm_llm_tx_top_llmx08_tx_packet_packer_trans_non_aligned_2449), + .I3(com_llm_llm_tx_top_tx_tlp_td[45]), + .O(com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_0_0[45]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_0_0_37_.INIT = 16'hABFB; + LUT4 com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_0_0_37_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_packet_packer_aligned_2490), + .I1(com_llm_llm_tx_top_llmx08_tx_packet_packer_prev_td[5]), + .I2(com_llm_llm_tx_top_llmx08_tx_packet_packer_trans_non_aligned_2449), + .I3(com_llm_llm_tx_top_tx_tlp_td[37]), + .O(com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_0_0[37]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_0_0_49_.INIT = 16'hABFB; + LUT4 com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_0_0_49_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_packet_packer_aligned_2490), + .I1(com_llm_llm_tx_top_llmx08_tx_packet_packer_prev_td[17]), + .I2(com_llm_llm_tx_top_llmx08_tx_packet_packer_trans_non_aligned_2449), + .I3(com_llm_llm_tx_top_tx_tlp_td[49]), + .O(com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_0_0[49]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_0_0_51_.INIT = 16'hABFB; + LUT4 com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_0_0_51_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_packet_packer_aligned_2490), + .I1(com_llm_llm_tx_top_llmx08_tx_packet_packer_prev_td[19]), + .I2(com_llm_llm_tx_top_llmx08_tx_packet_packer_trans_non_aligned_2449), + .I3(com_llm_llm_tx_top_tx_tlp_td[51]), + .O(com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_0_0[51]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_0_0_52_.INIT = 16'hABFB; + LUT4 com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_0_0_52_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_packet_packer_aligned_2490), + .I1(com_llm_llm_tx_top_llmx08_tx_packet_packer_prev_td[20]), + .I2(com_llm_llm_tx_top_llmx08_tx_packet_packer_trans_non_aligned_2449), + .I3(com_llm_llm_tx_top_tx_tlp_td[52]), + .O(com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_0_0[52]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_0_0_42_.INIT = 16'hABFB; + LUT4 com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_0_0_42_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_packet_packer_aligned_2490), + .I1(com_llm_llm_tx_top_llmx08_tx_packet_packer_prev_td[10]), + .I2(com_llm_llm_tx_top_llmx08_tx_packet_packer_trans_non_aligned_2449), + .I3(com_llm_llm_tx_top_tx_tlp_td[42]), + .O(com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_0_0[42]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_0_0_55_.INIT = 16'hABFB; + LUT4 com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_0_0_55_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_packet_packer_aligned_2490), + .I1(com_llm_llm_tx_top_llmx08_tx_packet_packer_prev_td[23]), + .I2(com_llm_llm_tx_top_llmx08_tx_packet_packer_trans_non_aligned_2449), + .I3(com_llm_llm_tx_top_tx_tlp_td[55]), + .O(com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_0_0[55]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_0_0_43_.INIT = 16'hABFB; + LUT4 com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_0_0_43_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_packet_packer_aligned_2490), + .I1(com_llm_llm_tx_top_llmx08_tx_packet_packer_prev_td[11]), + .I2(com_llm_llm_tx_top_llmx08_tx_packet_packer_trans_non_aligned_2449), + .I3(com_llm_llm_tx_top_tx_tlp_td[43]), + .O(com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_0_0[43]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_0_0_36_.INIT = 16'hABFB; + LUT4 com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_0_0_36_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_packet_packer_aligned_2490), + .I1(com_llm_llm_tx_top_llmx08_tx_packet_packer_prev_td[4]), + .I2(com_llm_llm_tx_top_llmx08_tx_packet_packer_trans_non_aligned_2449), + .I3(com_llm_llm_tx_top_tx_tlp_td[36]), + .O(com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_0_0[36]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_0_0_41_.INIT = 16'hABFB; + LUT4 com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_0_0_41_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_packet_packer_aligned_2490), + .I1(com_llm_llm_tx_top_llmx08_tx_packet_packer_prev_td[9]), + .I2(com_llm_llm_tx_top_llmx08_tx_packet_packer_trans_non_aligned_2449), + .I3(com_llm_llm_tx_top_tx_tlp_td[41]), + .O(com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_0_0[41]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_0_0_44_.INIT = 16'hABFB; + LUT4 com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_0_0_44_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_packet_packer_aligned_2490), + .I1(com_llm_llm_tx_top_llmx08_tx_packet_packer_prev_td[12]), + .I2(com_llm_llm_tx_top_llmx08_tx_packet_packer_trans_non_aligned_2449), + .I3(com_llm_llm_tx_top_tx_tlp_td[44]), + .O(com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_0_0[44]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_0_0_34_.INIT = 16'hABFB; + LUT4 com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_0_0_34_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_packet_packer_aligned_2490), + .I1(com_llm_llm_tx_top_llmx08_tx_packet_packer_prev_td[2]), + .I2(com_llm_llm_tx_top_llmx08_tx_packet_packer_trans_non_aligned_2449), + .I3(com_llm_llm_tx_top_tx_tlp_td[34]), + .O(com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_0_0[34]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_0_0_35_.INIT = 16'hABFB; + LUT4 com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_0_0_35_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_packet_packer_aligned_2490), + .I1(com_llm_llm_tx_top_llmx08_tx_packet_packer_prev_td[3]), + .I2(com_llm_llm_tx_top_llmx08_tx_packet_packer_trans_non_aligned_2449), + .I3(com_llm_llm_tx_top_tx_tlp_td[35]), + .O(com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_0_0[35]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_0_0_33_.INIT = 16'hABFB; + LUT4 com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_0_0_33_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_packet_packer_aligned_2490), + .I1(com_llm_llm_tx_top_llmx08_tx_packet_packer_prev_td[1]), + .I2(com_llm_llm_tx_top_llmx08_tx_packet_packer_trans_non_aligned_2449), + .I3(com_llm_llm_tx_top_tx_tlp_td[33]), + .O(com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_0_0[33]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_0_0_54_.INIT = 16'hABFB; + LUT4 com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_0_0_54_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_packet_packer_aligned_2490), + .I1(com_llm_llm_tx_top_llmx08_tx_packet_packer_prev_td[22]), + .I2(com_llm_llm_tx_top_llmx08_tx_packet_packer_trans_non_aligned_2449), + .I3(com_llm_llm_tx_top_tx_tlp_td[54]), + .O(com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_0_0[54]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_0_0_38_.INIT = 16'hABFB; + LUT4 com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_0_0_38_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_packet_packer_aligned_2490), + .I1(com_llm_llm_tx_top_llmx08_tx_packet_packer_prev_td[6]), + .I2(com_llm_llm_tx_top_llmx08_tx_packet_packer_trans_non_aligned_2449), + .I3(com_llm_llm_tx_top_tx_tlp_td[38]), + .O(com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_0_0[38]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_0_0_50_.INIT = 16'hABFB; + LUT4 com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_0_0_50_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_packet_packer_aligned_2490), + .I1(com_llm_llm_tx_top_llmx08_tx_packet_packer_prev_td[18]), + .I2(com_llm_llm_tx_top_llmx08_tx_packet_packer_trans_non_aligned_2449), + .I3(com_llm_llm_tx_top_tx_tlp_td[50]), + .O(com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_0_0[50]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_0_0_48_.INIT = 16'hABFB; + LUT4 com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_0_0_48_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_packet_packer_aligned_2490), + .I1(com_llm_llm_tx_top_llmx08_tx_packet_packer_prev_td[16]), + .I2(com_llm_llm_tx_top_llmx08_tx_packet_packer_trans_non_aligned_2449), + .I3(com_llm_llm_tx_top_tx_tlp_td[48]), + .O(com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_0_0[48]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_0_0_39_.INIT = 16'hABFB; + LUT4 com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_0_0_39_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_packet_packer_aligned_2490), + .I1(com_llm_llm_tx_top_llmx08_tx_packet_packer_prev_td[7]), + .I2(com_llm_llm_tx_top_llmx08_tx_packet_packer_trans_non_aligned_2449), + .I3(com_llm_llm_tx_top_tx_tlp_td[39]), + .O(com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_0_0[39]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_0_0_47_.INIT = 16'hABFB; + LUT4 com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_0_0_47_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_packet_packer_aligned_2490), + .I1(com_llm_llm_tx_top_llmx08_tx_packet_packer_prev_td[15]), + .I2(com_llm_llm_tx_top_llmx08_tx_packet_packer_trans_non_aligned_2449), + .I3(com_llm_llm_tx_top_tx_tlp_td[47]), + .O(com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_0_0[47]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_0_0_40_.INIT = 16'hABFB; + LUT4 com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_0_0_40_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_packet_packer_aligned_2490), + .I1(com_llm_llm_tx_top_llmx08_tx_packet_packer_prev_td[8]), + .I2(com_llm_llm_tx_top_llmx08_tx_packet_packer_trans_non_aligned_2449), + .I3(com_llm_llm_tx_top_tx_tlp_td[40]), + .O(com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_0_0[40]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_0_0_32_.INIT = 16'hABFB; + LUT4 com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_0_0_32_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_packet_packer_aligned_2490), + .I1(com_llm_llm_tx_top_llmx08_tx_packet_packer_prev_td[0]), + .I2(com_llm_llm_tx_top_llmx08_tx_packet_packer_trans_non_aligned_2449), + .I3(com_llm_llm_tx_top_tx_tlp_td[32]), + .O(com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_0_0[32]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_0_0_46_.INIT = 16'hABFB; + LUT4 com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_0_0_46_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_packet_packer_aligned_2490), + .I1(com_llm_llm_tx_top_llmx08_tx_packet_packer_prev_td[14]), + .I2(com_llm_llm_tx_top_llmx08_tx_packet_packer_trans_non_aligned_2449), + .I3(com_llm_llm_tx_top_tx_tlp_td[46]), + .O(com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_0_0[46]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_i_0_59_.INIT = 16'hFEAE; + LUT4 com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_i_0_59_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_packet_packer_aligned_2490), + .I1(com_llm_llm_tx_top_llmx08_tx_packet_packer_prev_td[27]), + .I2(com_llm_llm_tx_top_llmx08_tx_packet_packer_trans_non_aligned_2449), + .I3(com_llm_llm_tx_top_tx_tlp_td[59]), + .O(com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_i_0[59]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_i_0_60_.INIT = 16'hFEAE; + LUT4 com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_i_0_60_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_packet_packer_aligned_2490), + .I1(com_llm_llm_tx_top_llmx08_tx_packet_packer_prev_td[28]), + .I2(com_llm_llm_tx_top_llmx08_tx_packet_packer_trans_non_aligned_2449), + .I3(com_llm_llm_tx_top_tx_tlp_td[60]), + .O(com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_i_0[60]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_i_0_62_.INIT = 16'hFEAE; + LUT4 com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_i_0_62_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_packet_packer_aligned_2490), + .I1(com_llm_llm_tx_top_llmx08_tx_packet_packer_prev_td[30]), + .I2(com_llm_llm_tx_top_llmx08_tx_packet_packer_trans_non_aligned_2449), + .I3(com_llm_llm_tx_top_tx_tlp_td[62]), + .O(com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_i_0[62]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_i_0_61_.INIT = 16'hFEAE; + LUT4 com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_i_0_61_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_packet_packer_aligned_2490), + .I1(com_llm_llm_tx_top_llmx08_tx_packet_packer_prev_td[29]), + .I2(com_llm_llm_tx_top_llmx08_tx_packet_packer_trans_non_aligned_2449), + .I3(com_llm_llm_tx_top_tx_tlp_td[61]), + .O(com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_i_0[61]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_i_0_58_.INIT = 16'hFEAE; + LUT4 com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_i_0_58_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_packet_packer_aligned_2490), + .I1(com_llm_llm_tx_top_llmx08_tx_packet_packer_prev_td[26]), + .I2(com_llm_llm_tx_top_llmx08_tx_packet_packer_trans_non_aligned_2449), + .I3(com_llm_llm_tx_top_tx_tlp_td[58]), + .O(com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_i_0[58]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_i_0_56_.INIT = 16'hFEAE; + LUT4 com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_i_0_56_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_packet_packer_aligned_2490), + .I1(com_llm_llm_tx_top_llmx08_tx_packet_packer_prev_td[24]), + .I2(com_llm_llm_tx_top_llmx08_tx_packet_packer_trans_non_aligned_2449), + .I3(com_llm_llm_tx_top_tx_tlp_td[56]), + .O(com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_i_0[56]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_i_0_57_.INIT = 16'hFEAE; + LUT4 com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_i_0_57_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_packet_packer_aligned_2490), + .I1(com_llm_llm_tx_top_llmx08_tx_packet_packer_prev_td[25]), + .I2(com_llm_llm_tx_top_llmx08_tx_packet_packer_trans_non_aligned_2449), + .I3(com_llm_llm_tx_top_tx_tlp_td[57]), + .O(com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_i_0[57]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_i_0_63_.INIT = 16'hFEAE; + LUT4 com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_i_0_63_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_packet_packer_aligned_2490), + .I1(com_llm_llm_tx_top_llmx08_tx_packet_packer_prev_td[31]), + .I2(com_llm_llm_tx_top_llmx08_tx_packet_packer_trans_non_aligned_2449), + .I3(com_llm_llm_tx_top_tx_tlp_td[63]), + .O(com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_i_0[63]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_packet_packer_next_arb_state_i_i_0_a2_3_1_.INIT = 8'h80; + LUT3 com_llm_llm_tx_top_llmx08_tx_packet_packer_next_arb_state_i_i_0_a2_3_1_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_59258_1), + .I1(com_llm_llm_tx_top_un1_link_status_1_i_0_0_a3), + .I2(com_llm_llm_tx_top_tx_dllp_vld_n), + .O(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_59258_4) + ); + defparam com_llm_llm_tx_top_llmx08_tx_packet_packer_next_arb_state_i_i_0_a2_2_1_.INIT = 8'h80; + LUT3 com_llm_llm_tx_top_llmx08_tx_packet_packer_next_arb_state_i_i_0_a2_2_1_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_56059_i), + .I1(com_llm_llm_tx_top_un1_link_status_1_i_0_0_a3), + .I2(com_llm_llm_tx_top_tx_dllp_vld_n), + .O(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_59252) + ); + defparam com_llm_llm_tx_top_llmx08_tx_packet_packer_next_arb_state_i_i_0_a2_1_.INIT = 8'hC4; + LUT3 com_llm_llm_tx_top_llmx08_tx_packet_packer_next_arb_state_i_i_0_a2_1_ ( + .I0(com_llm_llm_tx_top_N_56164_i), + .I1(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_59255_1), + .I2(com_llm_llm_tx_top_un1_link_status_1_i_0_0_a3), + .O(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_59249) + ); + defparam com_llm_llm_tx_top_llmx08_tx_packet_packer_next_arb_state_i_i_0_2_39368.INIT = 16'h3233; + LUT4_L com_llm_llm_tx_top_llmx08_tx_packet_packer_next_arb_state_i_i_0_2_39368 ( + .I0(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_56059_i), + .I1(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_59248), + .I2(com_llm_llm_tx_top_tx_dllp_accepted), + .I3(com_llm_llm_tx_top_tx_dllp_tx_next), + .LO(com_llm_llm_tx_top_llmx08_tx_packet_packer_next_arb_state_i_i_0_2_39368_2491) + ); + defparam com_llm_llm_tx_top_llmx08_tx_packet_packer_next_arb_state_0_i_0_0_0_0_.INIT = 16'h2A3F; + LUT4 com_llm_llm_tx_top_llmx08_tx_packet_packer_next_arb_state_0_i_0_0_0_0_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_56940_i), + .I1(com_llm_llm_tx_top_un1_link_status_1_i_0_0_a3), + .I2(com_llm_llm_tx_top_llmx08_tx_packet_packer_next_arb_state_0_i_0_0_a2_0_0[0]), + .I3(com_llm_llm_tx_top_llmx08_tx_packet_packer_tx_idle_next_2494), + .O(com_llm_llm_tx_top_llmx08_tx_packet_packer_next_arb_state_0_i_0_0_0[0]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_packet_packer_current_td_0_i_m3_0_15_.INIT = 16'hBE14; + LUT4 com_llm_llm_tx_top_llmx08_tx_packet_packer_current_td_0_i_m3_0_15_ ( + .I0(com_llm_llm_tx_top_arb_state[2]), + .I1(com_llm_llm_tx_top_llmx08_tx_packet_packer_new_c32_1_2_0_), + .I2(com_llm_llm_tx_top_llmx08_tx_packet_packer_new_c32_1_3_0_), + .I3(com_llm_llm_tx_top_tx_tlp_td[15]), + .O(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_63510) + ); + defparam com_llm_llm_tx_top_llmx08_tx_packet_packer_current_td_0_i_m3_0_16_.INIT = 16'hED21; + LUT4 com_llm_llm_tx_top_llmx08_tx_packet_packer_current_td_0_i_m3_0_16_ ( + .I0(N_12165), + .I1(com_llm_llm_tx_top_arb_state[2]), + .I2(com_llm_llm_tx_top_llmx08_tx_packet_packer_new_c32_1_2_15_), + .I3(com_llm_llm_tx_top_tx_tlp_td[16]), + .O(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_63511) + ); + defparam com_llm_llm_tx_top_llmx08_tx_packet_packer_current_td_0_i_m3_0_18_.INIT = 16'hDE12; + LUT4 com_llm_llm_tx_top_llmx08_tx_packet_packer_current_td_0_i_m3_0_18_ ( + .I0(N_12170), + .I1(com_llm_llm_tx_top_arb_state[2]), + .I2(com_llm_llm_tx_top_llmx08_tx_packet_packer_new_c32_1_1_13_), + .I3(com_llm_llm_tx_top_tx_tlp_td[18]), + .O(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_63513) + ); + defparam com_llm_llm_tx_top_llmx08_tx_packet_packer_current_td_0_i_m3_0_19_.INIT = 16'hDE12; + LUT4 com_llm_llm_tx_top_llmx08_tx_packet_packer_current_td_0_i_m3_0_19_ ( + .I0(N_11973), + .I1(com_llm_llm_tx_top_arb_state[2]), + .I2(com_llm_llm_tx_top_llmx08_tx_packet_packer_new_c32_1_0_12_), + .I3(com_llm_llm_tx_top_tx_tlp_td[19]), + .O(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_63514) + ); + defparam com_llm_llm_tx_top_llmx08_tx_packet_packer_next_arb_state_0_i_0_0_2_0_.INIT = 16'h373F; + LUT4_L com_llm_llm_tx_top_llmx08_tx_packet_packer_next_arb_state_0_i_0_0_2_0_ ( + .I0(com_llm_llm_tx_top_N_56164_i), + .I1(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_59258_4), + .I2(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_59258_5), + .I3(com_llm_llm_tx_top_reg_tx_pp_idle), + .LO(com_llm_llm_tx_top_llmx08_tx_packet_packer_next_arb_state_0_i_0_0_2[0]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_packet_packer_current_td_0_i_m3_0_9_.INIT = 16'hED21; + LUT4 com_llm_llm_tx_top_llmx08_tx_packet_packer_current_td_0_i_m3_0_9_ ( + .I0(N_12120), + .I1(com_llm_llm_tx_top_arb_state[2]), + .I2(com_llm_llm_tx_top_llmx08_tx_packet_packer_new_c32_1_1_6_), + .I3(com_llm_llm_tx_top_tx_tlp_td[9]), + .O(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_63504) + ); + defparam com_llm_llm_tx_top_llmx08_tx_packet_packer_current_td_0_i_m3_0_11_.INIT = 16'hDE12; + LUT4 com_llm_llm_tx_top_llmx08_tx_packet_packer_current_td_0_i_m3_0_11_ ( + .I0(N_12090), + .I1(com_llm_llm_tx_top_arb_state[2]), + .I2(com_llm_llm_tx_top_llmx08_tx_packet_packer_new_c32_1_2_4_), + .I3(com_llm_llm_tx_top_tx_tlp_td[11]), + .O(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_63506) + ); + defparam com_llm_llm_tx_top_llmx08_tx_packet_packer_current_td_0_i_m3_0_13_.INIT = 16'hED21; + LUT4 com_llm_llm_tx_top_llmx08_tx_packet_packer_current_td_0_i_m3_0_13_ ( + .I0(N_12109), + .I1(com_llm_llm_tx_top_arb_state[2]), + .I2(com_llm_llm_tx_top_llmx08_tx_packet_packer_new_c32_1_1_2_), + .I3(com_llm_llm_tx_top_tx_tlp_td[13]), + .O(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_63508) + ); + defparam com_llm_llm_tx_top_llmx08_tx_packet_packer_current_td_0_i_m3_0_14_.INIT = 16'hED21; + LUT4 com_llm_llm_tx_top_llmx08_tx_packet_packer_current_td_0_i_m3_0_14_ ( + .I0(N_12170), + .I1(com_llm_llm_tx_top_arb_state[2]), + .I2(com_llm_llm_tx_top_llmx08_tx_packet_packer_new_c32_1_2_1_), + .I3(com_llm_llm_tx_top_tx_tlp_td[14]), + .O(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_63509) + ); + defparam com_llm_llm_tx_top_llmx08_tx_packet_packer_current_td_0_i_m3_0_17_.INIT = 8'hB1; + LUT3 com_llm_llm_tx_top_llmx08_tx_packet_packer_current_td_0_i_m3_0_17_ ( + .I0(com_llm_llm_tx_top_arb_state[2]), + .I1(com_llm_llm_tx_top_llmx08_tx_packet_packer_new_c32_14_), + .I2(com_llm_llm_tx_top_tx_tlp_td[17]), + .O(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_63512) + ); + defparam com_llm_llm_tx_top_llmx08_tx_packet_packer_current_td_0_i_m3_0_20_.INIT = 8'hB1; + LUT3 com_llm_llm_tx_top_llmx08_tx_packet_packer_current_td_0_i_m3_0_20_ ( + .I0(com_llm_llm_tx_top_arb_state[2]), + .I1(com_llm_llm_tx_top_llmx08_tx_packet_packer_new_c32_11_), + .I2(com_llm_llm_tx_top_tx_tlp_td[20]), + .O(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_63515) + ); + defparam com_llm_llm_tx_top_llmx08_tx_packet_packer_current_td_0_i_m3_0_21_.INIT = 16'hED21; + LUT4 com_llm_llm_tx_top_llmx08_tx_packet_packer_current_td_0_i_m3_0_21_ ( + .I0(N_12082), + .I1(com_llm_llm_tx_top_arb_state[2]), + .I2(com_llm_llm_tx_top_llmx08_tx_packet_packer_new_c32_1_0_10_), + .I3(com_llm_llm_tx_top_tx_tlp_td[21]), + .O(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_63516) + ); + defparam com_llm_llm_tx_top_llmx08_tx_packet_packer_current_td_0_i_m3_0_22_.INIT = 8'hE4; + LUT3 com_llm_llm_tx_top_llmx08_tx_packet_packer_current_td_0_i_m3_0_22_ ( + .I0(com_llm_llm_tx_top_arb_state[2]), + .I1(com_llm_llm_tx_top_llmx08_tx_packet_packer_new_c32_1_i[9]), + .I2(com_llm_llm_tx_top_tx_tlp_td[22]), + .O(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_63517) + ); + defparam com_llm_llm_tx_top_llmx08_tx_packet_packer_current_td_0_i_m3_0_23_.INIT = 16'hED21; + LUT4 com_llm_llm_tx_top_llmx08_tx_packet_packer_current_td_0_i_m3_0_23_ ( + .I0(N_12082), + .I1(com_llm_llm_tx_top_arb_state[2]), + .I2(com_llm_llm_tx_top_llmx08_tx_packet_packer_new_c32_1_2_8_), + .I3(com_llm_llm_tx_top_tx_tlp_td[23]), + .O(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_63518) + ); + defparam com_llm_llm_tx_top_llmx08_tx_packet_packer_current_td_0_i_m3_0_10_.INIT = 16'hDE12; + LUT4 com_llm_llm_tx_top_llmx08_tx_packet_packer_current_td_0_i_m3_0_10_ ( + .I0(N_12109), + .I1(com_llm_llm_tx_top_arb_state[2]), + .I2(com_llm_llm_tx_top_llmx08_tx_packet_packer_new_c32_1_2_5_), + .I3(com_llm_llm_tx_top_tx_tlp_td[10]), + .O(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_63505) + ); + defparam com_llm_llm_tx_top_llmx08_tx_packet_packer_current_td_0_i_m3_0_12_.INIT = 16'hDE12; + LUT4 com_llm_llm_tx_top_llmx08_tx_packet_packer_current_td_0_i_m3_0_12_ ( + .I0(N_12120), + .I1(com_llm_llm_tx_top_arb_state[2]), + .I2(com_llm_llm_tx_top_llmx08_tx_packet_packer_new_c32_1_3_3_), + .I3(com_llm_llm_tx_top_tx_tlp_td[12]), + .O(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_63507) + ); + defparam com_llm_llm_tx_top_llmx08_tx_packet_packer_arb_state_i_2_.INIT = 4'h1; + LUT1_L com_llm_llm_tx_top_llmx08_tx_packet_packer_arb_state_i_2_ ( + .I0(com_llm_llm_tx_top_arb_state[2]), + .LO(com_llm_llm_tx_top_llmx08_tx_packet_packer_arb_state_i[2]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_packet_packer_N_56522_i.INIT = 8'h72; + LUT3_L com_llm_llm_tx_top_llmx08_tx_packet_packer_N_56522_i ( + .I0(com_llm_llm_tx_top_llmx08_tx_packet_packer_aligned_2490), + .I1(com_llm_llm_tx_top_arb_state[2]), + .I2(phy_tctrl_l), + .LO(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_56522_i_2447) + ); + defparam com_llm_llm_tx_top_llmx08_tx_packet_packer_N_86829_i.INIT = 16'hA0B1; + LUT4_L com_llm_llm_tx_top_llmx08_tx_packet_packer_N_86829_i ( + .I0(com_llm_llm_tx_top_llmx08_tx_packet_packer_aligned_2490), + .I1(com_llm_llm_tx_top_llmx08_tx_packet_packer_trans_non_aligned_2449), + .I2(com_llm_llm_tx_top_rem_pipe[4]), + .I3(com_llm_llm_tx_top_tx_tlp_vld_l_n_i), + .LO(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_86829_i_2448) + ); + defparam com_llm_llm_tx_top_llmx08_tx_packet_packer_current_td_i_31_.INIT = 16'h3210; + LUT4_L com_llm_llm_tx_top_llmx08_tx_packet_packer_current_td_i_31_ ( + .I0(com_llm_llm_tx_top_arb_state[2]), + .I1(com_llm_llm_tx_top_reg_tx_pp_idle), + .I2(com_llm_llm_tx_top_tx_dllp_td_31_), + .I3(com_llm_llm_tx_top_tx_tlp_td[31]), + .LO(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_51682_i) + ); + defparam com_llm_llm_tx_top_llmx08_tx_packet_packer_current_td_i_30_.INIT = 16'h3210; + LUT4_L com_llm_llm_tx_top_llmx08_tx_packet_packer_current_td_i_30_ ( + .I0(com_llm_llm_tx_top_arb_state[2]), + .I1(com_llm_llm_tx_top_reg_tx_pp_idle), + .I2(com_llm_llm_tx_top_tx_dllp_td_30_), + .I3(com_llm_llm_tx_top_tx_tlp_td[30]), + .LO(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_51680_i) + ); + defparam com_llm_llm_tx_top_llmx08_tx_packet_packer_current_td_i_29_.INIT = 16'h3210; + LUT4_L com_llm_llm_tx_top_llmx08_tx_packet_packer_current_td_i_29_ ( + .I0(com_llm_llm_tx_top_arb_state[2]), + .I1(com_llm_llm_tx_top_reg_tx_pp_idle), + .I2(com_llm_llm_tx_top_tx_dllp_td_29_), + .I3(com_llm_llm_tx_top_tx_tlp_td[29]), + .LO(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_51678_i) + ); + defparam com_llm_llm_tx_top_llmx08_tx_packet_packer_current_td_i_28_.INIT = 16'h3210; + LUT4_L com_llm_llm_tx_top_llmx08_tx_packet_packer_current_td_i_28_ ( + .I0(com_llm_llm_tx_top_arb_state[2]), + .I1(com_llm_llm_tx_top_reg_tx_pp_idle), + .I2(com_llm_llm_tx_top_tx_dllp_td_28_), + .I3(com_llm_llm_tx_top_tx_tlp_td[28]), + .LO(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_51676_i) + ); + defparam com_llm_llm_tx_top_llmx08_tx_packet_packer_current_td_i_27_.INIT = 16'h3210; + LUT4_L com_llm_llm_tx_top_llmx08_tx_packet_packer_current_td_i_27_ ( + .I0(com_llm_llm_tx_top_arb_state[2]), + .I1(com_llm_llm_tx_top_reg_tx_pp_idle), + .I2(com_llm_llm_tx_top_tx_dllp_td_27_), + .I3(com_llm_llm_tx_top_tx_tlp_td[27]), + .LO(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_51674_i) + ); + defparam com_llm_llm_tx_top_llmx08_tx_packet_packer_current_td_i_26_.INIT = 16'h3210; + LUT4_L com_llm_llm_tx_top_llmx08_tx_packet_packer_current_td_i_26_ ( + .I0(com_llm_llm_tx_top_arb_state[2]), + .I1(com_llm_llm_tx_top_reg_tx_pp_idle), + .I2(com_llm_llm_tx_top_tx_dllp_td_26_), + .I3(com_llm_llm_tx_top_tx_tlp_td[26]), + .LO(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_51672_i) + ); + defparam com_llm_llm_tx_top_llmx08_tx_packet_packer_current_td_i_25_.INIT = 16'h3210; + LUT4_L com_llm_llm_tx_top_llmx08_tx_packet_packer_current_td_i_25_ ( + .I0(com_llm_llm_tx_top_arb_state[2]), + .I1(com_llm_llm_tx_top_reg_tx_pp_idle), + .I2(com_llm_llm_tx_top_tx_dllp_td_25_), + .I3(com_llm_llm_tx_top_tx_tlp_td[25]), + .LO(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_51670_i) + ); + defparam com_llm_llm_tx_top_llmx08_tx_packet_packer_current_td_i_24_.INIT = 16'h3210; + LUT4_L com_llm_llm_tx_top_llmx08_tx_packet_packer_current_td_i_24_ ( + .I0(com_llm_llm_tx_top_arb_state[2]), + .I1(com_llm_llm_tx_top_reg_tx_pp_idle), + .I2(com_llm_llm_tx_top_tx_dllp_td_24_), + .I3(com_llm_llm_tx_top_tx_tlp_td[24]), + .LO(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_51668_i) + ); + defparam com_llm_llm_tx_top_llmx08_tx_packet_packer_current_td_1_a2_23_.INIT = 4'h2; + LUT2_L com_llm_llm_tx_top_llmx08_tx_packet_packer_current_td_1_a2_23_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_63518), + .I1(com_llm_llm_tx_top_reg_tx_pp_idle), + .LO(com_llm_llm_tx_top_llmx08_tx_packet_packer_current_td[23]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_packet_packer_current_td_1_a2_22_.INIT = 4'h2; + LUT2_L com_llm_llm_tx_top_llmx08_tx_packet_packer_current_td_1_a2_22_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_63517), + .I1(com_llm_llm_tx_top_reg_tx_pp_idle), + .LO(com_llm_llm_tx_top_llmx08_tx_packet_packer_current_td[22]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_packet_packer_current_td_1_a2_21_.INIT = 4'h2; + LUT2_L com_llm_llm_tx_top_llmx08_tx_packet_packer_current_td_1_a2_21_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_63516), + .I1(com_llm_llm_tx_top_reg_tx_pp_idle), + .LO(com_llm_llm_tx_top_llmx08_tx_packet_packer_current_td[21]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_packet_packer_current_td_1_a2_20_.INIT = 4'h2; + LUT2_L com_llm_llm_tx_top_llmx08_tx_packet_packer_current_td_1_a2_20_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_63515), + .I1(com_llm_llm_tx_top_reg_tx_pp_idle), + .LO(com_llm_llm_tx_top_llmx08_tx_packet_packer_current_td[20]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_packet_packer_current_td_1_a2_19_.INIT = 4'h2; + LUT2_L com_llm_llm_tx_top_llmx08_tx_packet_packer_current_td_1_a2_19_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_63514), + .I1(com_llm_llm_tx_top_reg_tx_pp_idle), + .LO(com_llm_llm_tx_top_llmx08_tx_packet_packer_current_td[19]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_packet_packer_current_td_1_a2_18_.INIT = 4'h2; + LUT2_L com_llm_llm_tx_top_llmx08_tx_packet_packer_current_td_1_a2_18_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_63513), + .I1(com_llm_llm_tx_top_reg_tx_pp_idle), + .LO(com_llm_llm_tx_top_llmx08_tx_packet_packer_current_td[18]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_packet_packer_current_td_1_a2_17_.INIT = 4'h2; + LUT2_L com_llm_llm_tx_top_llmx08_tx_packet_packer_current_td_1_a2_17_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_63512), + .I1(com_llm_llm_tx_top_reg_tx_pp_idle), + .LO(com_llm_llm_tx_top_llmx08_tx_packet_packer_current_td[17]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_packet_packer_current_td_1_a2_16_.INIT = 4'h2; + LUT2_L com_llm_llm_tx_top_llmx08_tx_packet_packer_current_td_1_a2_16_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_63511), + .I1(com_llm_llm_tx_top_reg_tx_pp_idle), + .LO(com_llm_llm_tx_top_llmx08_tx_packet_packer_current_td[16]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_packet_packer_current_td_1_a2_15_.INIT = 4'h2; + LUT2_L com_llm_llm_tx_top_llmx08_tx_packet_packer_current_td_1_a2_15_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_63510), + .I1(com_llm_llm_tx_top_reg_tx_pp_idle), + .LO(com_llm_llm_tx_top_llmx08_tx_packet_packer_current_td[15]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_packet_packer_current_td_1_a2_14_.INIT = 4'h2; + LUT2_L com_llm_llm_tx_top_llmx08_tx_packet_packer_current_td_1_a2_14_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_63509), + .I1(com_llm_llm_tx_top_reg_tx_pp_idle), + .LO(com_llm_llm_tx_top_llmx08_tx_packet_packer_current_td[14]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_packet_packer_current_td_1_a2_13_.INIT = 4'h2; + LUT2_L com_llm_llm_tx_top_llmx08_tx_packet_packer_current_td_1_a2_13_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_63508), + .I1(com_llm_llm_tx_top_reg_tx_pp_idle), + .LO(com_llm_llm_tx_top_llmx08_tx_packet_packer_current_td[13]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_packet_packer_current_td_1_a2_12_.INIT = 4'h2; + LUT2_L com_llm_llm_tx_top_llmx08_tx_packet_packer_current_td_1_a2_12_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_63507), + .I1(com_llm_llm_tx_top_reg_tx_pp_idle), + .LO(com_llm_llm_tx_top_llmx08_tx_packet_packer_current_td[12]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_packet_packer_current_td_1_a2_11_.INIT = 4'h2; + LUT2_L com_llm_llm_tx_top_llmx08_tx_packet_packer_current_td_1_a2_11_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_63506), + .I1(com_llm_llm_tx_top_reg_tx_pp_idle), + .LO(com_llm_llm_tx_top_llmx08_tx_packet_packer_current_td[11]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_packet_packer_current_td_1_a2_10_.INIT = 4'h2; + LUT2_L com_llm_llm_tx_top_llmx08_tx_packet_packer_current_td_1_a2_10_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_63505), + .I1(com_llm_llm_tx_top_reg_tx_pp_idle), + .LO(com_llm_llm_tx_top_llmx08_tx_packet_packer_current_td[10]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_packet_packer_current_td_1_a2_9_.INIT = 4'h2; + LUT2_L com_llm_llm_tx_top_llmx08_tx_packet_packer_current_td_1_a2_9_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_63504), + .I1(com_llm_llm_tx_top_reg_tx_pp_idle), + .LO(com_llm_llm_tx_top_llmx08_tx_packet_packer_current_td[9]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_packet_packer_current_td_1_a2_8_.INIT = 4'h2; + LUT2_L com_llm_llm_tx_top_llmx08_tx_packet_packer_current_td_1_a2_8_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_63503), + .I1(com_llm_llm_tx_top_reg_tx_pp_idle), + .LO(com_llm_llm_tx_top_llmx08_tx_packet_packer_current_td[8]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_packet_packer_N_86910_i.INIT = 8'hEC; + LUT3_L com_llm_llm_tx_top_llmx08_tx_packet_packer_N_86910_i ( + .I0(com_llm_llm_tx_top_arb_state[2]), + .I1(com_llm_llm_tx_top_reg_tx_pp_idle), + .I2(com_llm_llm_tx_top_tx_tlp_td[7]), + .LO(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_86910_i_2450) + ); + defparam com_llm_llm_tx_top_llmx08_tx_packet_packer_N_86939_i.INIT = 8'hEC; + LUT3_L com_llm_llm_tx_top_llmx08_tx_packet_packer_N_86939_i ( + .I0(com_llm_llm_tx_top_arb_state[2]), + .I1(com_llm_llm_tx_top_reg_tx_pp_idle), + .I2(com_llm_llm_tx_top_tx_tlp_td[6]), + .LO(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_86939_i_2451) + ); + defparam com_llm_llm_tx_top_llmx08_tx_packet_packer_N_86911_i.INIT = 8'hEC; + LUT3_L com_llm_llm_tx_top_llmx08_tx_packet_packer_N_86911_i ( + .I0(com_llm_llm_tx_top_arb_state[2]), + .I1(com_llm_llm_tx_top_reg_tx_pp_idle), + .I2(com_llm_llm_tx_top_tx_tlp_td[5]), + .LO(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_86911_i_2452) + ); + defparam com_llm_llm_tx_top_llmx08_tx_packet_packer_N_86912_i.INIT = 8'hEC; + LUT3_L com_llm_llm_tx_top_llmx08_tx_packet_packer_N_86912_i ( + .I0(com_llm_llm_tx_top_arb_state[2]), + .I1(com_llm_llm_tx_top_reg_tx_pp_idle), + .I2(com_llm_llm_tx_top_tx_tlp_td[4]), + .LO(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_86912_i_2453) + ); + defparam com_llm_llm_tx_top_llmx08_tx_packet_packer_N_86913_i.INIT = 8'hEC; + LUT3_L com_llm_llm_tx_top_llmx08_tx_packet_packer_N_86913_i ( + .I0(com_llm_llm_tx_top_arb_state[2]), + .I1(com_llm_llm_tx_top_reg_tx_pp_idle), + .I2(com_llm_llm_tx_top_tx_tlp_td[3]), + .LO(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_86913_i_2454) + ); + defparam com_llm_llm_tx_top_llmx08_tx_packet_packer_N_86914_i.INIT = 8'hEC; + LUT3_L com_llm_llm_tx_top_llmx08_tx_packet_packer_N_86914_i ( + .I0(com_llm_llm_tx_top_arb_state[2]), + .I1(com_llm_llm_tx_top_reg_tx_pp_idle), + .I2(com_llm_llm_tx_top_tx_tlp_td[2]), + .LO(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_86914_i_2455) + ); + defparam com_llm_llm_tx_top_llmx08_tx_packet_packer_N_86915_i.INIT = 8'hEC; + LUT3_L com_llm_llm_tx_top_llmx08_tx_packet_packer_N_86915_i ( + .I0(com_llm_llm_tx_top_arb_state[2]), + .I1(com_llm_llm_tx_top_reg_tx_pp_idle), + .I2(com_llm_llm_tx_top_tx_tlp_td[1]), + .LO(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_86915_i_2456) + ); + defparam com_llm_llm_tx_top_llmx08_tx_packet_packer_N_86916_i.INIT = 8'hEC; + LUT3_L com_llm_llm_tx_top_llmx08_tx_packet_packer_N_86916_i ( + .I0(com_llm_llm_tx_top_arb_state[2]), + .I1(com_llm_llm_tx_top_reg_tx_pp_idle), + .I2(com_llm_llm_tx_top_tx_tlp_td[0]), + .LO(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_86916_i_2457) + ); + defparam com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_tframe_h_3_i.INIT = 16'hD52A; + LUT4_L com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_tframe_h_3_i ( + .I0(com_llm_llm_tx_top_llmx08_tx_packet_packer_aligned_2490), + .I1(com_llm_llm_tx_top_arb_state[2]), + .I2(com_llm_llm_tx_top_tx_tlp_sof_n), + .I3(phy_tframe_h), + .LO(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_51193_i) + ); + defparam com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_tframe_l_3_i.INIT = 16'hEA15; + LUT4_L com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_tframe_l_3_i ( + .I0(com_llm_llm_tx_top_llmx08_tx_packet_packer_aligned_2490), + .I1(com_llm_llm_tx_top_arb_state[2]), + .I2(com_llm_llm_tx_top_tx_tlp_sof_n), + .I3(phy_tframe_l), + .LO(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_51195_i) + ); + defparam com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_i_63_.INIT = 16'hD050; + LUT4_L com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_i_63_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_61304), + .I1(com_llm_llm_tx_top_arb_state[2]), + .I2(com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_i_0[63]), + .I3(com_llm_llm_tx_top_tx_tlp_td[63]), + .LO(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_51291_i) + ); + defparam com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_i_62_.INIT = 16'hD050; + LUT4_L com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_i_62_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_61304), + .I1(com_llm_llm_tx_top_arb_state[2]), + .I2(com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_i_0[62]), + .I3(com_llm_llm_tx_top_tx_tlp_td[62]), + .LO(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_51289_i) + ); + defparam com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_i_61_.INIT = 16'hD050; + LUT4_L com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_i_61_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_61304), + .I1(com_llm_llm_tx_top_arb_state[2]), + .I2(com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_i_0[61]), + .I3(com_llm_llm_tx_top_tx_tlp_td[61]), + .LO(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_51287_i) + ); + defparam com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_i_60_.INIT = 16'hD050; + LUT4_L com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_i_60_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_61304), + .I1(com_llm_llm_tx_top_arb_state[2]), + .I2(com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_i_0[60]), + .I3(com_llm_llm_tx_top_tx_tlp_td[60]), + .LO(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_51285_i) + ); + defparam com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_i_59_.INIT = 16'hD050; + LUT4_L com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_i_59_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_61304), + .I1(com_llm_llm_tx_top_arb_state[2]), + .I2(com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_i_0[59]), + .I3(com_llm_llm_tx_top_tx_tlp_td[59]), + .LO(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_51283_i) + ); + defparam com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_i_58_.INIT = 16'hD050; + LUT4_L com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_i_58_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_61304), + .I1(com_llm_llm_tx_top_arb_state[2]), + .I2(com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_i_0[58]), + .I3(com_llm_llm_tx_top_tx_tlp_td[58]), + .LO(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_51281_i) + ); + defparam com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_i_57_.INIT = 16'hD050; + LUT4_L com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_i_57_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_61304), + .I1(com_llm_llm_tx_top_arb_state[2]), + .I2(com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_i_0[57]), + .I3(com_llm_llm_tx_top_tx_tlp_td[57]), + .LO(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_51279_i) + ); + defparam com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_i_56_.INIT = 16'hD050; + LUT4_L com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_i_56_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_61304), + .I1(com_llm_llm_tx_top_arb_state[2]), + .I2(com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_i_0[56]), + .I3(com_llm_llm_tx_top_tx_tlp_td[56]), + .LO(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_51277_i) + ); + defparam com_llm_llm_tx_top_llmx08_tx_packet_packer_N_85739_i.INIT = 8'h8F; + LUT3_L com_llm_llm_tx_top_llmx08_tx_packet_packer_N_85739_i ( + .I0(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_56441), + .I1(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_61304), + .I2(com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_0_0[55]), + .LO(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_85739_i_2458) + ); + defparam com_llm_llm_tx_top_llmx08_tx_packet_packer_N_85738_i.INIT = 8'h8F; + LUT3_L com_llm_llm_tx_top_llmx08_tx_packet_packer_N_85738_i ( + .I0(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_56442), + .I1(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_61304), + .I2(com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_0_0[54]), + .LO(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_85738_i_2459) + ); + defparam com_llm_llm_tx_top_llmx08_tx_packet_packer_N_85737_i.INIT = 8'h8F; + LUT3_L com_llm_llm_tx_top_llmx08_tx_packet_packer_N_85737_i ( + .I0(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_56443), + .I1(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_61304), + .I2(com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_0_0[53]), + .LO(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_85737_i_2460) + ); + defparam com_llm_llm_tx_top_llmx08_tx_packet_packer_N_85736_i.INIT = 8'h8F; + LUT3_L com_llm_llm_tx_top_llmx08_tx_packet_packer_N_85736_i ( + .I0(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_56444), + .I1(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_61304), + .I2(com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_0_0[52]), + .LO(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_85736_i_2461) + ); + defparam com_llm_llm_tx_top_llmx08_tx_packet_packer_N_85735_i.INIT = 8'h8F; + LUT3_L com_llm_llm_tx_top_llmx08_tx_packet_packer_N_85735_i ( + .I0(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_56445), + .I1(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_61304), + .I2(com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_0_0[51]), + .LO(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_85735_i_2462) + ); + defparam com_llm_llm_tx_top_llmx08_tx_packet_packer_N_85734_i.INIT = 8'h8F; + LUT3_L com_llm_llm_tx_top_llmx08_tx_packet_packer_N_85734_i ( + .I0(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_56446), + .I1(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_61304), + .I2(com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_0_0[50]), + .LO(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_85734_i_2463) + ); + defparam com_llm_llm_tx_top_llmx08_tx_packet_packer_N_85698_i.INIT = 8'h8F; + LUT3_L com_llm_llm_tx_top_llmx08_tx_packet_packer_N_85698_i ( + .I0(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_56447), + .I1(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_61304), + .I2(com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_0_0[49]), + .LO(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_85698_i_2464) + ); + defparam com_llm_llm_tx_top_llmx08_tx_packet_packer_N_85733_i.INIT = 8'h8F; + LUT3_L com_llm_llm_tx_top_llmx08_tx_packet_packer_N_85733_i ( + .I0(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_56448), + .I1(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_61304), + .I2(com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_0_0[48]), + .LO(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_85733_i_2465) + ); + defparam com_llm_llm_tx_top_llmx08_tx_packet_packer_N_85732_i.INIT = 8'h8F; + LUT3_L com_llm_llm_tx_top_llmx08_tx_packet_packer_N_85732_i ( + .I0(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_56449), + .I1(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_61304), + .I2(com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_0_0[47]), + .LO(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_85732_i_2466) + ); + defparam com_llm_llm_tx_top_llmx08_tx_packet_packer_N_85731_i.INIT = 8'h8F; + LUT3_L com_llm_llm_tx_top_llmx08_tx_packet_packer_N_85731_i ( + .I0(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_56450), + .I1(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_61304), + .I2(com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_0_0[46]), + .LO(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_85731_i_2467) + ); + defparam com_llm_llm_tx_top_llmx08_tx_packet_packer_N_85730_i.INIT = 8'h8F; + LUT3_L com_llm_llm_tx_top_llmx08_tx_packet_packer_N_85730_i ( + .I0(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_56451), + .I1(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_61304), + .I2(com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_0_0[45]), + .LO(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_85730_i_2468) + ); + defparam com_llm_llm_tx_top_llmx08_tx_packet_packer_N_85729_i.INIT = 8'h8F; + LUT3_L com_llm_llm_tx_top_llmx08_tx_packet_packer_N_85729_i ( + .I0(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_56452), + .I1(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_61304), + .I2(com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_0_0[44]), + .LO(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_85729_i_2469) + ); + defparam com_llm_llm_tx_top_llmx08_tx_packet_packer_N_85728_i.INIT = 8'h8F; + LUT3_L com_llm_llm_tx_top_llmx08_tx_packet_packer_N_85728_i ( + .I0(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_56453), + .I1(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_61304), + .I2(com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_0_0[43]), + .LO(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_85728_i_2470) + ); + defparam com_llm_llm_tx_top_llmx08_tx_packet_packer_N_85727_i.INIT = 8'h8F; + LUT3_L com_llm_llm_tx_top_llmx08_tx_packet_packer_N_85727_i ( + .I0(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_56454), + .I1(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_61304), + .I2(com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_0_0[42]), + .LO(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_85727_i_2471) + ); + defparam com_llm_llm_tx_top_llmx08_tx_packet_packer_N_85726_i.INIT = 8'h8F; + LUT3_L com_llm_llm_tx_top_llmx08_tx_packet_packer_N_85726_i ( + .I0(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_56455), + .I1(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_61304), + .I2(com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_0_0[41]), + .LO(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_85726_i_2472) + ); + defparam com_llm_llm_tx_top_llmx08_tx_packet_packer_N_85725_i.INIT = 8'h8F; + LUT3_L com_llm_llm_tx_top_llmx08_tx_packet_packer_N_85725_i ( + .I0(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_56456), + .I1(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_61304), + .I2(com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_0_0[40]), + .LO(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_85725_i_2473) + ); + defparam com_llm_llm_tx_top_llmx08_tx_packet_packer_N_85699_i.INIT = 8'h8F; + LUT3_L com_llm_llm_tx_top_llmx08_tx_packet_packer_N_85699_i ( + .I0(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_56457), + .I1(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_61304), + .I2(com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_0_0[39]), + .LO(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_85699_i_2474) + ); + defparam com_llm_llm_tx_top_llmx08_tx_packet_packer_N_85700_i.INIT = 8'h8F; + LUT3_L com_llm_llm_tx_top_llmx08_tx_packet_packer_N_85700_i ( + .I0(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_56458), + .I1(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_61304), + .I2(com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_0_0[38]), + .LO(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_85700_i_2475) + ); + defparam com_llm_llm_tx_top_llmx08_tx_packet_packer_N_85724_i.INIT = 16'h8F0F; + LUT4_L com_llm_llm_tx_top_llmx08_tx_packet_packer_N_85724_i ( + .I0(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_61304), + .I1(com_llm_llm_tx_top_arb_state[2]), + .I2(com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_0_0[37]), + .I3(com_llm_llm_tx_top_tx_tlp_td[37]), + .LO(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_85724_i_2476) + ); + defparam com_llm_llm_tx_top_llmx08_tx_packet_packer_N_85723_i.INIT = 16'h8F0F; + LUT4_L com_llm_llm_tx_top_llmx08_tx_packet_packer_N_85723_i ( + .I0(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_61304), + .I1(com_llm_llm_tx_top_arb_state[2]), + .I2(com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_0_0[36]), + .I3(com_llm_llm_tx_top_tx_tlp_td[36]), + .LO(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_85723_i_2477) + ); + defparam com_llm_llm_tx_top_llmx08_tx_packet_packer_N_85722_i.INIT = 8'h8F; + LUT3_L com_llm_llm_tx_top_llmx08_tx_packet_packer_N_85722_i ( + .I0(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_56461), + .I1(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_61304), + .I2(com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_0_0[35]), + .LO(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_85722_i_2478) + ); + defparam com_llm_llm_tx_top_llmx08_tx_packet_packer_N_85721_i.INIT = 8'h8F; + LUT3_L com_llm_llm_tx_top_llmx08_tx_packet_packer_N_85721_i ( + .I0(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_56462), + .I1(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_61304), + .I2(com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_0_0[34]), + .LO(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_85721_i_2479) + ); + defparam com_llm_llm_tx_top_llmx08_tx_packet_packer_N_85720_i.INIT = 8'h8F; + LUT3_L com_llm_llm_tx_top_llmx08_tx_packet_packer_N_85720_i ( + .I0(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_56463), + .I1(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_61304), + .I2(com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_0_0[33]), + .LO(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_85720_i_2480) + ); + defparam com_llm_llm_tx_top_llmx08_tx_packet_packer_N_85719_i.INIT = 8'h8F; + LUT3_L com_llm_llm_tx_top_llmx08_tx_packet_packer_N_85719_i ( + .I0(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_56464), + .I1(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_61304), + .I2(com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_0_0[32]), + .LO(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_85719_i_2481) + ); + defparam com_llm_llm_tx_top_llmx08_tx_packet_packer_N_85718_i.INIT = 16'hFEFA; + LUT4_L com_llm_llm_tx_top_llmx08_tx_packet_packer_N_85718_i ( + .I0(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_57425), + .I1(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_61327), + .I2(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_61349), + .I3(com_llm_llm_tx_top_tx_tlp_td[63]), + .LO(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_85718_i_2482) + ); + defparam com_llm_llm_tx_top_llmx08_tx_packet_packer_N_85717_i.INIT = 16'hFEFA; + LUT4_L com_llm_llm_tx_top_llmx08_tx_packet_packer_N_85717_i ( + .I0(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_57423), + .I1(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_61327), + .I2(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_61349), + .I3(com_llm_llm_tx_top_tx_tlp_td[62]), + .LO(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_85717_i_2483) + ); + defparam com_llm_llm_tx_top_llmx08_tx_packet_packer_N_85716_i.INIT = 16'hFEFA; + LUT4_L com_llm_llm_tx_top_llmx08_tx_packet_packer_N_85716_i ( + .I0(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_57421), + .I1(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_61327), + .I2(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_61349), + .I3(com_llm_llm_tx_top_tx_tlp_td[61]), + .LO(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_85716_i_2484) + ); + defparam com_llm_llm_tx_top_llmx08_tx_packet_packer_N_85715_i.INIT = 16'hFEFA; + LUT4_L com_llm_llm_tx_top_llmx08_tx_packet_packer_N_85715_i ( + .I0(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_57419), + .I1(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_61327), + .I2(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_61349), + .I3(com_llm_llm_tx_top_tx_tlp_td[60]), + .LO(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_85715_i_2485) + ); + defparam com_llm_llm_tx_top_llmx08_tx_packet_packer_N_85714_i.INIT = 16'hFEFA; + LUT4_L com_llm_llm_tx_top_llmx08_tx_packet_packer_N_85714_i ( + .I0(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_57417), + .I1(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_61327), + .I2(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_61349), + .I3(com_llm_llm_tx_top_tx_tlp_td[59]), + .LO(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_85714_i_2486) + ); + defparam com_llm_llm_tx_top_llmx08_tx_packet_packer_N_85713_i.INIT = 16'hFEFA; + LUT4_L com_llm_llm_tx_top_llmx08_tx_packet_packer_N_85713_i ( + .I0(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_57415), + .I1(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_61327), + .I2(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_61349), + .I3(com_llm_llm_tx_top_tx_tlp_td[58]), + .LO(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_85713_i_2487) + ); + defparam com_llm_llm_tx_top_llmx08_tx_packet_packer_N_85712_i.INIT = 16'hFEFA; + LUT4_L com_llm_llm_tx_top_llmx08_tx_packet_packer_N_85712_i ( + .I0(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_57413), + .I1(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_61327), + .I2(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_61349), + .I3(com_llm_llm_tx_top_tx_tlp_td[57]), + .LO(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_85712_i_2488) + ); + defparam com_llm_llm_tx_top_llmx08_tx_packet_packer_N_85711_i.INIT = 16'hFEFA; + LUT4_L com_llm_llm_tx_top_llmx08_tx_packet_packer_N_85711_i ( + .I0(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_57410), + .I1(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_61327), + .I2(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_61349), + .I3(com_llm_llm_tx_top_tx_tlp_td[56]), + .LO(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_85711_i_2489) + ); + defparam com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_i_23_.INIT = 16'h00CA; + LUT4_L com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_i_23_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_56441), + .I1(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_63518), + .I2(com_llm_llm_tx_top_llmx08_tx_packet_packer_aligned_2490), + .I3(com_llm_llm_tx_top_reg_tx_pp_idle), + .LO(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_51243_i) + ); + defparam com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_i_22_.INIT = 16'h00CA; + LUT4_L com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_i_22_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_56442), + .I1(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_63517), + .I2(com_llm_llm_tx_top_llmx08_tx_packet_packer_aligned_2490), + .I3(com_llm_llm_tx_top_reg_tx_pp_idle), + .LO(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_51241_i) + ); + defparam com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_i_21_.INIT = 16'h00CA; + LUT4_L com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_i_21_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_56443), + .I1(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_63516), + .I2(com_llm_llm_tx_top_llmx08_tx_packet_packer_aligned_2490), + .I3(com_llm_llm_tx_top_reg_tx_pp_idle), + .LO(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_51239_i) + ); + defparam com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_i_20_.INIT = 16'h00CA; + LUT4_L com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_i_20_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_56444), + .I1(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_63515), + .I2(com_llm_llm_tx_top_llmx08_tx_packet_packer_aligned_2490), + .I3(com_llm_llm_tx_top_reg_tx_pp_idle), + .LO(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_51237_i) + ); + defparam com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_i_19_.INIT = 16'h00CA; + LUT4_L com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_i_19_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_56445), + .I1(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_63514), + .I2(com_llm_llm_tx_top_llmx08_tx_packet_packer_aligned_2490), + .I3(com_llm_llm_tx_top_reg_tx_pp_idle), + .LO(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_51235_i) + ); + defparam com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_i_18_.INIT = 16'h00CA; + LUT4_L com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_i_18_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_56446), + .I1(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_63513), + .I2(com_llm_llm_tx_top_llmx08_tx_packet_packer_aligned_2490), + .I3(com_llm_llm_tx_top_reg_tx_pp_idle), + .LO(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_51233_i) + ); + defparam com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_i_17_.INIT = 16'h00CA; + LUT4_L com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_i_17_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_56447), + .I1(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_63512), + .I2(com_llm_llm_tx_top_llmx08_tx_packet_packer_aligned_2490), + .I3(com_llm_llm_tx_top_reg_tx_pp_idle), + .LO(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_51231_i) + ); + defparam com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_i_16_.INIT = 16'h00CA; + LUT4_L com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_i_16_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_56448), + .I1(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_63511), + .I2(com_llm_llm_tx_top_llmx08_tx_packet_packer_aligned_2490), + .I3(com_llm_llm_tx_top_reg_tx_pp_idle), + .LO(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_51229_i) + ); + defparam com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_i_15_.INIT = 16'h00CA; + LUT4_L com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_i_15_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_56449), + .I1(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_63510), + .I2(com_llm_llm_tx_top_llmx08_tx_packet_packer_aligned_2490), + .I3(com_llm_llm_tx_top_reg_tx_pp_idle), + .LO(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_51227_i) + ); + defparam com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_i_14_.INIT = 16'h00CA; + LUT4_L com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_i_14_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_56450), + .I1(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_63509), + .I2(com_llm_llm_tx_top_llmx08_tx_packet_packer_aligned_2490), + .I3(com_llm_llm_tx_top_reg_tx_pp_idle), + .LO(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_51225_i) + ); + defparam com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_i_13_.INIT = 16'h00CA; + LUT4_L com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_i_13_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_56451), + .I1(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_63508), + .I2(com_llm_llm_tx_top_llmx08_tx_packet_packer_aligned_2490), + .I3(com_llm_llm_tx_top_reg_tx_pp_idle), + .LO(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_51223_i) + ); + defparam com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_i_12_.INIT = 16'h00CA; + LUT4_L com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_i_12_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_56452), + .I1(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_63507), + .I2(com_llm_llm_tx_top_llmx08_tx_packet_packer_aligned_2490), + .I3(com_llm_llm_tx_top_reg_tx_pp_idle), + .LO(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_51221_i) + ); + defparam com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_i_11_.INIT = 16'h00CA; + LUT4_L com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_i_11_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_56453), + .I1(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_63506), + .I2(com_llm_llm_tx_top_llmx08_tx_packet_packer_aligned_2490), + .I3(com_llm_llm_tx_top_reg_tx_pp_idle), + .LO(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_51219_i) + ); + defparam com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_i_10_.INIT = 16'h00CA; + LUT4_L com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_i_10_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_56454), + .I1(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_63505), + .I2(com_llm_llm_tx_top_llmx08_tx_packet_packer_aligned_2490), + .I3(com_llm_llm_tx_top_reg_tx_pp_idle), + .LO(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_51217_i) + ); + defparam com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_i_9_.INIT = 16'h00CA; + LUT4_L com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_i_9_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_56455), + .I1(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_63504), + .I2(com_llm_llm_tx_top_llmx08_tx_packet_packer_aligned_2490), + .I3(com_llm_llm_tx_top_reg_tx_pp_idle), + .LO(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_51215_i) + ); + defparam com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_i_8_.INIT = 16'h00CA; + LUT4_L com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_i_8_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_56456), + .I1(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_63503), + .I2(com_llm_llm_tx_top_llmx08_tx_packet_packer_aligned_2490), + .I3(com_llm_llm_tx_top_reg_tx_pp_idle), + .LO(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_51213_i) + ); + defparam com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_i_7_.INIT = 16'h0A08; + LUT4_L com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_i_7_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_56006_i), + .I1(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_56457), + .I2(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_57409), + .I3(com_llm_llm_tx_top_llmx08_tx_packet_packer_aligned_2490), + .LO(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_51211_i) + ); + defparam com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_i_6_.INIT = 16'h0A08; + LUT4_L com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_i_6_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_56006_i), + .I1(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_56458), + .I2(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_57407), + .I3(com_llm_llm_tx_top_llmx08_tx_packet_packer_aligned_2490), + .LO(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_51209_i) + ); + defparam com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_i_5_.INIT = 16'h2202; + LUT4_L com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_i_5_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_56006_i), + .I1(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_57404), + .I2(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_61304), + .I3(com_llm_llm_tx_top_tx_tlp_td[5]), + .LO(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_51207_i) + ); + defparam com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_i_4_.INIT = 16'h2202; + LUT4_L com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_i_4_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_56006_i), + .I1(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_57402), + .I2(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_61304), + .I3(com_llm_llm_tx_top_tx_tlp_td[4]), + .LO(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_51205_i) + ); + defparam com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_i_3_.INIT = 16'h0A08; + LUT4_L com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_i_3_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_56006_i), + .I1(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_56461), + .I2(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_57401), + .I3(com_llm_llm_tx_top_llmx08_tx_packet_packer_aligned_2490), + .LO(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_51203_i) + ); + defparam com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_i_2_.INIT = 16'h0A08; + LUT4_L com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_i_2_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_56006_i), + .I1(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_56462), + .I2(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_57399), + .I3(com_llm_llm_tx_top_llmx08_tx_packet_packer_aligned_2490), + .LO(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_51201_i) + ); + defparam com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_i_1_.INIT = 16'h0A08; + LUT4_L com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_i_1_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_56006_i), + .I1(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_56463), + .I2(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_57397), + .I3(com_llm_llm_tx_top_llmx08_tx_packet_packer_aligned_2490), + .LO(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_51199_i) + ); + defparam com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_i_0_.INIT = 16'h0A08; + LUT4_L com_llm_llm_tx_top_llmx08_tx_packet_packer_phy_td_4_i_0_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_56006_i), + .I1(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_56464), + .I2(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_57395), + .I3(com_llm_llm_tx_top_llmx08_tx_packet_packer_aligned_2490), + .LO(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_51197_i) + ); + defparam com_llm_llm_tx_top_llmx08_tx_packet_packer_next_arb_state_i_i_0_2_.INIT = 16'hC040; + LUT4_L com_llm_llm_tx_top_llmx08_tx_packet_packer_next_arb_state_i_i_0_2_ ( + .I0(com_llm_llm_tx_top_N_56164_i), + .I1(com_llm_llm_tx_top_llmx08_tx_packet_packer_next_arb_state_i_i_0_2_39366_2492), + .I2(com_llm_llm_tx_top_llmx08_tx_packet_packer_next_arb_state_i_i_0_2_39368_2491), + .I3(com_llm_llm_tx_top_arb_state[2]), + .LO(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_33959_i) + ); + defparam com_llm_llm_tx_top_llmx08_tx_packet_packer_next_arb_state_i_i_0_1_.INIT = 16'h0100; + LUT4_L com_llm_llm_tx_top_llmx08_tx_packet_packer_next_arb_state_i_i_0_1_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_59249), + .I1(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_59252), + .I2(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_59258_4), + .I3(com_llm_llm_tx_top_llmx08_tx_packet_packer_next_arb_state_i_i_0_2[1]), + .LO(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_33961_i) + ); + defparam com_llm_llm_tx_top_llmx08_tx_packet_packer_N_85695_i.INIT = 16'h8FFF; + LUT4_L com_llm_llm_tx_top_llmx08_tx_packet_packer_N_85695_i ( + .I0(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_56163_i), + .I1(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_59252), + .I2(com_llm_llm_tx_top_llmx08_tx_packet_packer_next_arb_state_0_i_0_0_0[0]), + .I3(com_llm_llm_tx_top_llmx08_tx_packet_packer_next_arb_state_0_i_0_0_2[0]), + .LO(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_85695_i_2493) + ); + defparam com_llm_llm_tx_top_llmx08_tx_packet_packer_current_td_0_i_m3_0_1_8_.INIT = 16'h6996; + LUT4 com_llm_llm_tx_top_llmx08_tx_packet_packer_current_td_0_i_m3_0_1_8_ ( + .I0(G_462_1_1), + .I1(N_220), + .I2(N_11947), + .I3(com_llm_llm_tx_top_llmx08_tx_packet_packer_new_c32_1_0_7_), + .O(com_llm_llm_tx_top_llmx08_tx_packet_packer_current_td_0_i_m3_0_1[8]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_packet_packer_current_td_0_i_m3_0_8_.INIT = 16'hDE12; + LUT4 com_llm_llm_tx_top_llmx08_tx_packet_packer_current_td_0_i_m3_0_8_ ( + .I0(N_12165), + .I1(com_llm_llm_tx_top_arb_state[2]), + .I2(com_llm_llm_tx_top_llmx08_tx_packet_packer_current_td_0_i_m3_0_1[8]), + .I3(com_llm_llm_tx_top_tx_tlp_td[8]), + .O(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_63503) + ); + defparam com_llm_llm_tx_top_llmx08_tx_packet_packer_next_arb_state_i_i_0_2_1_1_.INIT = 8'h32; + LUT3 com_llm_llm_tx_top_llmx08_tx_packet_packer_next_arb_state_i_i_0_2_1_1_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_56059_i), + .I1(com_llm_llm_tx_top_N_59251_1), + .I2(com_llm_llm_tx_top_tx_tlp_sof_pre_n), + .O(com_llm_llm_tx_top_llmx08_tx_packet_packer_next_arb_state_i_i_0_2_1[1]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_packet_packer_next_arb_state_i_i_0_2_1_.INIT = 16'h0051; + LUT4 com_llm_llm_tx_top_llmx08_tx_packet_packer_next_arb_state_i_i_0_2_1_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_56940_i), + .I1(com_llm_llm_tx_top_llmx08_tx_packet_packer_N_59258_1), + .I2(com_llm_llm_tx_top_llmx08_tx_packet_packer_next_arb_state_i_i_0_2_1[1]), + .I3(com_llm_llm_tx_top_llmx08_tx_packet_packer_tx_idle_next_2494), + .O(com_llm_llm_tx_top_llmx08_tx_packet_packer_next_arb_state_i_i_0_2[1]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_packet_packer_llm_rx_crc16_d32_new_c32_1_0_10_.INIT = 4'h6; + LUT2 com_llm_llm_tx_top_llmx08_tx_packet_packer_llm_rx_crc16_d32_new_c32_1_0_10_ ( + .I0(com_llm_llm_tx_top_tx_dllp_td_42_), + .I1(com_llm_llm_tx_top_tx_dllp_td_55_), + .O(G_462_1_1) + ); + defparam com_llm_llm_tx_top_llmx08_tx_packet_packer_llm_rx_crc16_d32_new_c32_1_0_3_.INIT = 4'h6; + LUT2 com_llm_llm_tx_top_llmx08_tx_packet_packer_llm_rx_crc16_d32_new_c32_1_0_3_ ( + .I0(com_llm_llm_tx_top_tx_dllp_td_29_), + .I1(com_llm_llm_tx_top_tx_dllp_td_31_), + .O(com_llm_llm_tx_top_llmx08_tx_packet_packer_llm_rx_crc16_d32_new_c32_1_0_3__2501) + ); + defparam com_llm_llm_tx_top_llmx08_tx_packet_packer_llm_rx_crc16_d32_new_c32_1_0_9_.INIT = 16'h6996; + LUT4_L com_llm_llm_tx_top_llmx08_tx_packet_packer_llm_rx_crc16_d32_new_c32_1_0_9_ ( + .I0(com_llm_llm_tx_top_tx_dllp_td_38_), + .I1(com_llm_llm_tx_top_tx_dllp_td_39_), + .I2(com_llm_llm_tx_top_tx_dllp_td_41_), + .I3(com_llm_llm_tx_top_tx_dllp_td_49_), + .LO(com_llm_llm_tx_top_llmx08_tx_packet_packer_llm_rx_crc16_d32_new_c32_1_0_9__2495) + ); + defparam com_llm_llm_tx_top_llmx08_tx_packet_packer_llm_rx_crc16_d32_new_c32_1_1_8_.INIT = 16'h6996; + LUT4_L com_llm_llm_tx_top_llmx08_tx_packet_packer_llm_rx_crc16_d32_new_c32_1_1_8_ ( + .I0(com_llm_llm_tx_top_tx_dllp_td_26_), + .I1(com_llm_llm_tx_top_tx_dllp_td_39_), + .I2(com_llm_llm_tx_top_tx_dllp_td_41_), + .I3(com_llm_llm_tx_top_tx_dllp_td_49_), + .LO(com_llm_llm_tx_top_llmx08_tx_packet_packer_llm_rx_crc16_d32_new_c32_1_1_8__2496) + ); + defparam com_llm_llm_tx_top_llmx08_tx_packet_packer_llm_rx_crc16_d32_new_c32_1_2_0_.INIT = 16'h6996; + LUT4 com_llm_llm_tx_top_llmx08_tx_packet_packer_llm_rx_crc16_d32_new_c32_1_2_0_ ( + .I0(N_11973_1), + .I1(com_llm_llm_tx_top_tx_dllp_td_32_), + .I2(com_llm_llm_tx_top_tx_dllp_td_34_), + .I3(com_llm_llm_tx_top_tx_dllp_td_39_), + .O(com_llm_llm_tx_top_llmx08_tx_packet_packer_new_c32_1_2_0_) + ); + defparam com_llm_llm_tx_top_llmx08_tx_packet_packer_llm_rx_crc16_d32_new_c32_1_3_0_.INIT = 16'h6996; + LUT4_L com_llm_llm_tx_top_llmx08_tx_packet_packer_llm_rx_crc16_d32_new_c32_1_3_0_ ( + .I0(N_196), + .I1(com_llm_llm_tx_top_tx_dllp_td_35_), + .I2(com_llm_llm_tx_top_tx_dllp_td_42_), + .I3(com_llm_llm_tx_top_tx_dllp_td_53_), + .LO(com_llm_llm_tx_top_llmx08_tx_packet_packer_new_c32_1_3_0_) + ); + defparam com_llm_llm_tx_top_llmx08_tx_packet_packer_llm_rx_crc16_d32_new_c32_1_0_12_.INIT = 16'h6996; + LUT4 com_llm_llm_tx_top_llmx08_tx_packet_packer_llm_rx_crc16_d32_new_c32_1_0_12_ ( + .I0(N_177), + .I1(com_llm_llm_tx_top_tx_dllp_td_38_), + .I2(com_llm_llm_tx_top_tx_dllp_td_41_), + .I3(com_llm_llm_tx_top_tx_dllp_td_55_), + .O(com_llm_llm_tx_top_llmx08_tx_packet_packer_new_c32_1_0_12_) + ); + defparam com_llm_llm_tx_top_llmx08_tx_packet_packer_llm_rx_crc16_d32_new_c32_1_0_11_.INIT = 4'h6; + LUT2_L com_llm_llm_tx_top_llmx08_tx_packet_packer_llm_rx_crc16_d32_new_c32_1_0_11_ ( + .I0(N_196), + .I1(N_11906), + .LO(com_llm_llm_tx_top_llmx08_tx_packet_packer_llm_rx_crc16_d32_new_c32_1_0_11__2499) + ); + defparam com_llm_llm_tx_top_llmx08_tx_packet_packer_llm_rx_crc16_d32_new_c32_1_1_13_.INIT = 16'h6996; + LUT4 com_llm_llm_tx_top_llmx08_tx_packet_packer_llm_rx_crc16_d32_new_c32_1_1_13_ ( + .I0(N_11916_1), + .I1(com_llm_llm_tx_top_tx_dllp_td_38_), + .I2(com_llm_llm_tx_top_tx_dllp_td_45_), + .I3(com_llm_llm_tx_top_tx_dllp_td_54_), + .O(com_llm_llm_tx_top_llmx08_tx_packet_packer_new_c32_1_1_13_) + ); + defparam com_llm_llm_tx_top_llmx08_tx_packet_packer_llm_rx_crc16_d32_new_c32_1_1_9_.INIT = 16'h6996; + LUT4_L com_llm_llm_tx_top_llmx08_tx_packet_packer_llm_rx_crc16_d32_new_c32_1_1_9_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_packet_packer_llm_rx_crc16_d32_new_c32_1_0_9__2495), + .I1(com_llm_llm_tx_top_tx_dllp_td_34_), + .I2(com_llm_llm_tx_top_tx_dllp_td_52_), + .I3(com_llm_llm_tx_top_tx_dllp_td_55_), + .LO(com_llm_llm_tx_top_llmx08_tx_packet_packer_llm_rx_crc16_d32_new_c32_1_1_9__2498) + ); + defparam com_llm_llm_tx_top_llmx08_tx_packet_packer_llm_rx_crc16_d32_new_c32_1_2_15_.INIT = 16'h6996; + LUT4_L com_llm_llm_tx_top_llmx08_tx_packet_packer_llm_rx_crc16_d32_new_c32_1_2_15_ ( + .I0(N_11936), + .I1(com_llm_llm_tx_top_tx_dllp_td_28_), + .I2(com_llm_llm_tx_top_tx_dllp_td_35_), + .I3(com_llm_llm_tx_top_tx_dllp_td_43_), + .LO(com_llm_llm_tx_top_llmx08_tx_packet_packer_new_c32_1_2_15_) + ); + defparam com_llm_llm_tx_top_llmx08_tx_packet_packer_llm_rx_crc16_d32_new_c32_1_0_7_.INIT = 16'h6996; + LUT4 com_llm_llm_tx_top_llmx08_tx_packet_packer_llm_rx_crc16_d32_new_c32_1_0_7_ ( + .I0(com_llm_llm_tx_top_tx_dllp_td_27_), + .I1(com_llm_llm_tx_top_tx_dllp_td_39_), + .I2(com_llm_llm_tx_top_tx_dllp_td_41_), + .I3(com_llm_llm_tx_top_tx_dllp_td_53_), + .O(com_llm_llm_tx_top_llmx08_tx_packet_packer_new_c32_1_0_7_) + ); + defparam com_llm_llm_tx_top_llmx08_tx_packet_packer_llm_rx_crc16_d32_new_c32_1_1_2_.INIT = 16'h6996; + LUT4 com_llm_llm_tx_top_llmx08_tx_packet_packer_llm_rx_crc16_d32_new_c32_1_1_2_ ( + .I0(N_11933), + .I1(com_llm_llm_tx_top_tx_dllp_td_38_), + .I2(com_llm_llm_tx_top_tx_dllp_td_42_), + .I3(com_llm_llm_tx_top_tx_dllp_td_54_), + .O(com_llm_llm_tx_top_llmx08_tx_packet_packer_new_c32_1_1_2_) + ); + defparam com_llm_llm_tx_top_llmx08_tx_packet_packer_llm_rx_crc16_d32_new_c32_1_0_0_10_.INIT = 4'h6; + LUT2_L com_llm_llm_tx_top_llmx08_tx_packet_packer_llm_rx_crc16_d32_new_c32_1_0_0_10_ ( + .I0(G_462_1_1), + .I1(N_11936), + .LO(com_llm_llm_tx_top_llmx08_tx_packet_packer_new_c32_1_0_10_) + ); + defparam com_llm_llm_tx_top_llmx08_tx_packet_packer_llm_rx_crc16_d32_new_c32_1_1_4_.INIT = 16'h6996; + LUT4_L com_llm_llm_tx_top_llmx08_tx_packet_packer_llm_rx_crc16_d32_new_c32_1_1_4_ ( + .I0(N_11878), + .I1(com_llm_llm_tx_top_tx_dllp_td_38_), + .I2(com_llm_llm_tx_top_tx_dllp_td_41_), + .I3(com_llm_llm_tx_top_tx_dllp_td_55_), + .LO(com_llm_llm_tx_top_llmx08_tx_packet_packer_llm_rx_crc16_d32_new_c32_1_1_4__2497) + ); + defparam com_llm_llm_tx_top_llmx08_tx_packet_packer_llm_rx_crc16_d32_new_c32_1_0_5_.INIT = 16'h6996; + LUT4 com_llm_llm_tx_top_llmx08_tx_packet_packer_llm_rx_crc16_d32_new_c32_1_0_5_ ( + .I0(com_llm_llm_tx_top_tx_dllp_td_27_), + .I1(com_llm_llm_tx_top_tx_dllp_td_41_), + .I2(com_llm_llm_tx_top_tx_dllp_td_44_), + .I3(com_llm_llm_tx_top_tx_dllp_td_53_), + .O(com_llm_llm_tx_top_llmx08_tx_packet_packer_llm_rx_crc16_d32_new_c32_1_0_5__2500) + ); + defparam com_llm_llm_tx_top_llmx08_tx_packet_packer_llm_rx_crc16_d32_new_c32_1_2_8_.INIT = 16'h6996; + LUT4 com_llm_llm_tx_top_llmx08_tx_packet_packer_llm_rx_crc16_d32_new_c32_1_2_8_ ( + .I0(com_llm_llm_tx_top_llmx08_tx_packet_packer_llm_rx_crc16_d32_new_c32_1_1_8__2496), + .I1(com_llm_llm_tx_top_tx_dllp_td_35_), + .I2(com_llm_llm_tx_top_tx_dllp_td_42_), + .I3(com_llm_llm_tx_top_tx_dllp_td_53_), + .O(com_llm_llm_tx_top_llmx08_tx_packet_packer_new_c32_1_2_8_) + ); + defparam com_llm_llm_tx_top_llmx08_tx_packet_packer_llm_rx_crc16_d32_new_c32_1_2_1_.INIT = 16'h6996; + LUT4_L com_llm_llm_tx_top_llmx08_tx_packet_packer_llm_rx_crc16_d32_new_c32_1_2_1_ ( + .I0(N_11906), + .I1(N_11916), + .I2(N_11973), + .I3(com_llm_llm_tx_top_tx_dllp_td_52_), + .LO(com_llm_llm_tx_top_llmx08_tx_packet_packer_new_c32_1_2_1_) + ); + defparam com_llm_llm_tx_top_llmx08_tx_packet_packer_llm_rx_crc16_d32_new_c32_1_1_6_.INIT = 16'h6996; + LUT4_L com_llm_llm_tx_top_llmx08_tx_packet_packer_llm_rx_crc16_d32_new_c32_1_1_6_ ( + .I0(N_177), + .I1(N_11897), + .I2(N_11916), + .I3(com_llm_llm_tx_top_tx_dllp_td_28_), + .LO(com_llm_llm_tx_top_llmx08_tx_packet_packer_new_c32_1_1_6_) + ); + defparam com_llm_llm_tx_top_llmx08_tx_packet_packer_llm_rx_crc16_d32_new_c32_1_2_4_.INIT = 8'h96; + LUT3_L com_llm_llm_tx_top_llmx08_tx_packet_packer_llm_rx_crc16_d32_new_c32_1_2_4_ ( + .I0(N_11933), + .I1(com_llm_llm_tx_top_llmx08_tx_packet_packer_llm_rx_crc16_d32_new_c32_1_1_4__2497), + .I2(com_llm_llm_tx_top_tx_dllp_td_26_), + .LO(com_llm_llm_tx_top_llmx08_tx_packet_packer_new_c32_1_2_4_) + ); + defparam com_llm_llm_tx_top_llmx08_tx_packet_packer_llm_rx_crc16_d32_new_c32_1_9_.INIT = 16'h6996; + LUT4_L com_llm_llm_tx_top_llmx08_tx_packet_packer_llm_rx_crc16_d32_new_c32_1_9_ ( + .I0(N_196), + .I1(N_11878), + .I2(N_11947), + .I3(com_llm_llm_tx_top_llmx08_tx_packet_packer_llm_rx_crc16_d32_new_c32_1_1_9__2498), + .LO(com_llm_llm_tx_top_llmx08_tx_packet_packer_new_c32_1_i[9]) + ); + defparam com_llm_llm_tx_top_llmx08_tx_packet_packer_llm_rx_crc16_d32_new_c32_1_11_.INIT = 16'h6996; + LUT4_L com_llm_llm_tx_top_llmx08_tx_packet_packer_llm_rx_crc16_d32_new_c32_1_11_ ( + .I0(N_232), + .I1(N_11878), + .I2(com_llm_llm_tx_top_llmx08_tx_packet_packer_llm_rx_crc16_d32_new_c32_1_0_11__2499), + .I3(com_llm_llm_tx_top_tx_dllp_td_49_), + .LO(com_llm_llm_tx_top_llmx08_tx_packet_packer_new_c32_11_) + ); + defparam com_llm_llm_tx_top_llmx08_tx_packet_packer_llm_rx_crc16_d32_new_c32_1_14_.INIT = 16'h6996; + LUT4_L com_llm_llm_tx_top_llmx08_tx_packet_packer_llm_rx_crc16_d32_new_c32_1_14_ ( + .I0(N_11878), + .I1(N_12109_1), + .I2(com_llm_llm_tx_top_tx_dllp_td_25_), + .I3(com_llm_llm_tx_top_tx_dllp_td_49_), + .LO(com_llm_llm_tx_top_llmx08_tx_packet_packer_new_c32_14_) + ); + defparam com_llm_llm_tx_top_llmx08_tx_packet_packer_llm_rx_crc16_d32_new_c32_1_2_5_.INIT = 16'h6996; + LUT4 com_llm_llm_tx_top_llmx08_tx_packet_packer_llm_rx_crc16_d32_new_c32_1_2_5_ ( + .I0(N_220), + .I1(N_232), + .I2(com_llm_llm_tx_top_llmx08_tx_packet_packer_llm_rx_crc16_d32_new_c32_1_0_5__2500), + .I3(com_llm_llm_tx_top_tx_dllp_td_38_), + .O(com_llm_llm_tx_top_llmx08_tx_packet_packer_new_c32_1_2_5_) + ); + defparam com_llm_llm_tx_top_llmx08_tx_packet_packer_llm_rx_crc16_d32_new_c32_1_3_3_.INIT = 16'h6996; + LUT4_L com_llm_llm_tx_top_llmx08_tx_packet_packer_llm_rx_crc16_d32_new_c32_1_3_3_ ( + .I0(N_11936_1), + .I1(N_12090), + .I2(com_llm_llm_tx_top_llmx08_tx_packet_packer_llm_rx_crc16_d32_new_c32_1_0_3__2501), + .I3(com_llm_llm_tx_top_tx_dllp_td_49_), + .LO(com_llm_llm_tx_top_llmx08_tx_packet_packer_new_c32_1_3_3_) + ); + FDS com_llm_llm_rx_top_llm_rx_demux_tlp_eof_n_qq ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_demux_N_85313_i_2552), + .Q(com_llm_llm_rx_top_rx_tlp_eof_n), + .S(plm_link_up_i) + ); + defparam com_llm_llm_rx_top_llm_rx_demux_dllp_vld_h_n_q_11_iv_i_a2_0_3.INIT = 4'h4; + LUT2 com_llm_llm_rx_top_llm_rx_demux_dllp_vld_h_n_q_11_iv_i_a2_0_3 ( + .I0(com_llm_llm_rx_top_llm_rx_demux_long_dllp_u_q_2544), + .I1(phy_rferr_h_n), + .O(com_llm_llm_rx_top_llm_rx_demux_N_16012_3) + ); + defparam com_llm_llm_rx_top_llm_rx_demux_tlp_ferr_n_q_9_u_i_o2.INIT = 4'h1; + LUT2 com_llm_llm_rx_top_llm_rx_demux_tlp_ferr_n_q_9_u_i_o2 ( + .I0(phy_rctrl_h), + .I1(phy_rferr_h_n), + .O(com_llm_llm_rx_top_llm_rx_demux_N_15979_i) + ); + defparam com_llm_llm_rx_top_llm_rx_demux_phy_frame_h_t.INIT = 4'h6; + LUT2 com_llm_llm_rx_top_llm_rx_demux_phy_frame_h_t ( + .I0(com_llm_llm_rx_top_llm_rx_demux_phy_frame_h_q_2521), + .I1(phy_rframe_h), + .O(com_llm_llm_rx_top_llm_rx_demux_phy_frame_h_t_2551) + ); + defparam com_llm_llm_rx_top_llm_rx_demux_phy_frame_l_t.INIT = 4'h6; + LUT2 com_llm_llm_rx_top_llm_rx_demux_phy_frame_l_t ( + .I0(com_llm_llm_rx_top_llm_rx_demux_phy_frame_l_q_2520), + .I1(phy_rframe_l), + .O(com_llm_llm_rx_top_llm_rx_demux_phy_frame_l_t_2518) + ); + defparam com_llm_llm_rx_top_llm_rx_demux_un5_idle_a_n_0.INIT = 4'h8; + LUT2 com_llm_llm_rx_top_llm_rx_demux_un5_idle_a_n_0 ( + .I0(phy_rd[56]), + .I1(phy_rd[57]), + .O(com_llm_llm_rx_top_llm_rx_demux_un5_idle_a_n_0_2502) + ); + defparam com_llm_llm_rx_top_llm_rx_demux_un10_idle_a_n_0.INIT = 4'h8; + LUT2 com_llm_llm_rx_top_llm_rx_demux_un10_idle_a_n_0 ( + .I0(phy_rd[0]), + .I1(phy_rd[1]), + .O(com_llm_llm_rx_top_llm_rx_demux_un10_idle_a_n_0_2503) + ); + defparam com_llm_llm_rx_top_llm_rx_demux_un4_idle_on_low_n_0.INIT = 4'h8; + LUT2 com_llm_llm_rx_top_llm_rx_demux_un4_idle_on_low_n_0 ( + .I0(phy_rd[24]), + .I1(phy_rd[25]), + .O(com_llm_llm_rx_top_llm_rx_demux_un4_idle_on_low_n_0_2504) + ); + defparam com_llm_llm_rx_top_llm_rx_demux_tlp_vld_h_n_qq_7_f0_i_o2.INIT = 4'h8; + LUT2 com_llm_llm_rx_top_llm_rx_demux_tlp_vld_h_n_qq_7_f0_i_o2 ( + .I0(com_llm_llm_rx_top_llm_rx_demux_phy_frame_h_t_2551), + .I1(com_llm_llm_rx_top_llm_rx_demux_tlp_align_q_2525), + .O(com_llm_llm_rx_top_llm_rx_demux_N_15985_i) + ); + defparam com_llm_llm_rx_top_llm_rx_demux_tlp_eof_n_q18_i_0_o2.INIT = 4'h4; + LUT2 com_llm_llm_rx_top_llm_rx_demux_tlp_eof_n_q18_i_0_o2 ( + .I0(com_llm_llm_rx_top_llm_rx_demux_phy_frame_h_t_2551), + .I1(com_llm_llm_rx_top_llm_rx_demux_phy_frame_l_t_2518), + .O(com_llm_llm_rx_top_llm_rx_demux_N_15978_i) + ); + defparam com_llm_llm_rx_top_llm_rx_demux_tlp_unalign_q13_i_a2.INIT = 4'h2; + LUT2 com_llm_llm_rx_top_llm_rx_demux_tlp_unalign_q13_i_a2 ( + .I0(com_llm_llm_rx_top_llm_rx_demux_phy_frame_l_t_2518), + .I1(phy_rctrl_l), + .O(com_llm_llm_rx_top_llm_rx_demux_tlp_unalign_q13_i_a2_2532) + ); + defparam com_llm_llm_rx_top_llm_rx_demux_un4_idle_on_high_n_1.INIT = 8'h80; + LUT3 com_llm_llm_rx_top_llm_rx_demux_un4_idle_on_high_n_1 ( + .I0(phy_rd[32]), + .I1(phy_rd[33]), + .I2(phy_rd[34]), + .O(com_llm_llm_rx_top_llm_rx_demux_un4_idle_on_high_n_1_2505) + ); + defparam com_llm_llm_rx_top_llm_rx_demux_dllp_vld_l_n_qq_7_i_o2.INIT = 16'hF531; + LUT4 com_llm_llm_rx_top_llm_rx_demux_dllp_vld_l_n_qq_7_i_o2 ( + .I0(com_llm_llm_rx_top_llm_rx_demux_dllp_a_2527), + .I1(com_llm_llm_rx_top_llm_rx_demux_dllp_u_2531), + .I2(com_llm_llm_rx_top_llm_rx_demux_phy_frame_h_t_2551), + .I3(phy_rferr_h_n), + .O(com_llm_llm_rx_top_llm_rx_demux_N_15983_i) + ); + defparam com_llm_llm_rx_top_llm_rx_demux_tlp_vld_l_n_q_13_0_o2_0.INIT = 4'h2; + LUT2_L com_llm_llm_rx_top_llm_rx_demux_tlp_vld_l_n_q_13_0_o2_0 ( + .I0(com_llm_llm_rx_top_llm_rx_demux_N_15980_i), + .I1(phy_rctrl_h), + .LO(com_llm_llm_rx_top_llm_rx_demux_N_15981_i) + ); + defparam com_llm_llm_rx_top_llm_rx_demux_tlp_eof_n_qq_2_i_a2_1_1.INIT = 4'h2; + LUT2 com_llm_llm_rx_top_llm_rx_demux_tlp_eof_n_qq_2_i_a2_1_1 ( + .I0(com_llm_llm_rx_top_llm_rx_demux_N_15978_i), + .I1(phy_rctrl_h), + .O(com_llm_llm_rx_top_llm_rx_demux_N_16020_1) + ); + defparam com_llm_llm_rx_top_llm_rx_demux_N_15996_i.INIT = 4'hD; + LUT2 com_llm_llm_rx_top_llm_rx_demux_N_15996_i ( + .I0(com_llm_llm_rx_top_llm_rx_demux_N_15977_i), + .I1(com_llm_llm_rx_top_llm_rx_demux_dllp_u_2531), + .O(com_llm_llm_rx_top_llm_rx_demux_N_15996_i_2543) + ); + defparam com_llm_llm_rx_top_llm_rx_demux_tlp_ip_flag_5_iv_i_a2.INIT = 16'h00CE; + LUT4 com_llm_llm_rx_top_llm_rx_demux_tlp_ip_flag_5_iv_i_a2 ( + .I0(com_llm_llm_rx_top_llm_rx_demux_phy_frame_h_t_2551), + .I1(com_llm_llm_rx_top_llm_rx_demux_phy_frame_l_t_2518), + .I2(phy_rctrl_h), + .I3(phy_rctrl_l), + .O(com_llm_llm_rx_top_llm_rx_demux_tlp_ip_flag_5_iv_i_a2_2517) + ); + defparam com_llm_llm_rx_top_llm_rx_demux_tlp_ferr_h_n_q_9_0_39369.INIT = 16'h3777; + LUT4_L com_llm_llm_rx_top_llm_rx_demux_tlp_ferr_h_n_q_9_0_39369 ( + .I0(com_llm_llm_rx_top_llm_rx_demux_N_15978_i), + .I1(com_llm_llm_rx_top_llm_rx_demux_N_15979_i), + .I2(com_llm_llm_rx_top_llm_rx_demux_N_15980_i), + .I3(com_llm_llm_rx_top_llm_rx_demux_phy_frame_h_t_2551), + .LO(com_llm_llm_rx_top_llm_rx_demux_tlp_ferr_h_n_q_9_0_39369_2514) + ); + defparam com_llm_llm_rx_top_llm_rx_demux_N_16008_i.INIT = 4'hD; + LUT2 com_llm_llm_rx_top_llm_rx_demux_N_16008_i ( + .I0(com_llm_llm_rx_top_llm_rx_demux_N_15977_i), + .I1(com_llm_llm_rx_top_llm_rx_demux_tlp_ip_flag_2547), + .O(com_llm_llm_rx_top_llm_rx_demux_N_16008_i_2548) + ); + defparam com_llm_llm_rx_top_llm_rx_demux_un5_idle_a_n_3.INIT = 16'h8000; + LUT4 com_llm_llm_rx_top_llm_rx_demux_un5_idle_a_n_3 ( + .I0(com_llm_llm_rx_top_llm_rx_demux_un5_idle_a_n_0_2502), + .I1(phy_rd[58]), + .I2(phy_rd[59]), + .I3(phy_rd[60]), + .O(com_llm_llm_rx_top_llm_rx_demux_un5_idle_a_n_3_2507) + ); + defparam com_llm_llm_rx_top_llm_rx_demux_un10_idle_a_n_3.INIT = 16'h8000; + LUT4 com_llm_llm_rx_top_llm_rx_demux_un10_idle_a_n_3 ( + .I0(com_llm_llm_rx_top_llm_rx_demux_un10_idle_a_n_0_2503), + .I1(phy_rd[2]), + .I2(phy_rd[3]), + .I3(phy_rd[4]), + .O(com_llm_llm_rx_top_llm_rx_demux_un10_idle_a_n_3_2506) + ); + defparam com_llm_llm_rx_top_llm_rx_demux_un4_idle_on_low_n_3.INIT = 16'h8000; + LUT4 com_llm_llm_rx_top_llm_rx_demux_un4_idle_on_low_n_3 ( + .I0(com_llm_llm_rx_top_llm_rx_demux_un4_idle_on_low_n_0_2504), + .I1(phy_rd[26]), + .I2(phy_rd[27]), + .I3(phy_rd[28]), + .O(com_llm_llm_rx_top_llm_rx_demux_un4_idle_on_low_n_3_2508) + ); + defparam com_llm_llm_rx_top_llm_rx_demux_tlp_ferr_n_qq_8_u_i_1.INIT = 16'h1303; + LUT4_L com_llm_llm_rx_top_llm_rx_demux_tlp_ferr_n_qq_8_u_i_1 ( + .I0(com_llm_llm_rx_top_llm_rx_demux_N_15977_i), + .I1(com_llm_llm_rx_top_llm_rx_demux_N_15985_i), + .I2(com_llm_llm_rx_top_llm_rx_demux_tlp_ferr_n_q_2542), + .I3(com_llm_llm_rx_top_llm_rx_demux_tlp_unalign_q_2533), + .LO(com_llm_llm_rx_top_llm_rx_demux_tlp_ferr_n_qq_8_u_i_1_2515) + ); + defparam com_llm_llm_rx_top_llm_rx_demux_tlp_ferr_n_q_9_u_i_39421.INIT = 16'hFFB8; + LUT4_L com_llm_llm_rx_top_llm_rx_demux_tlp_ferr_n_q_9_u_i_39421 ( + .I0(com_llm_llm_rx_top_llm_rx_demux_N_15981_i), + .I1(com_llm_llm_rx_top_llm_rx_demux_phy_frame_h_t_2551), + .I2(com_llm_llm_rx_top_llm_rx_demux_phy_frame_l_t_2518), + .I3(com_llm_llm_rx_top_llm_rx_demux_tlp_ip_flag_2547), + .LO(com_llm_llm_rx_top_llm_rx_demux_tlp_ferr_n_q_9_u_i_39421_2516) + ); + defparam com_llm_llm_rx_top_llm_rx_demux_un4_idle_on_high_n_4.INIT = 16'h8000; + LUT4 com_llm_llm_rx_top_llm_rx_demux_un4_idle_on_high_n_4 ( + .I0(com_llm_llm_rx_top_llm_rx_demux_un4_idle_on_high_n_1_2505), + .I1(phy_rd[35]), + .I2(phy_rd[36]), + .I3(phy_rd[37]), + .O(com_llm_llm_rx_top_llm_rx_demux_un4_idle_on_high_n_4_2509) + ); + defparam com_llm_llm_rx_top_llm_rx_demux_un10_idle_a_n.INIT = 16'h8000; + LUT4 com_llm_llm_rx_top_llm_rx_demux_un10_idle_a_n ( + .I0(com_llm_llm_rx_top_llm_rx_demux_un10_idle_a_n_3_2506), + .I1(phy_rd[5]), + .I2(phy_rd[6]), + .I3(phy_rd[7]), + .O(com_llm_llm_rx_top_llm_rx_demux_un10_idle_a_n_2510) + ); + defparam com_llm_llm_rx_top_llm_rx_demux_un5_idle_a_n.INIT = 16'h8000; + LUT4 com_llm_llm_rx_top_llm_rx_demux_un5_idle_a_n ( + .I0(com_llm_llm_rx_top_llm_rx_demux_un5_idle_a_n_3_2507), + .I1(phy_rd[61]), + .I2(phy_rd[62]), + .I3(phy_rd[63]), + .O(com_llm_llm_rx_top_llm_rx_demux_un5_idle_a_n_2512) + ); + defparam com_llm_llm_rx_top_llm_rx_demux_un4_idle_on_low_n.INIT = 16'h8000; + LUT4 com_llm_llm_rx_top_llm_rx_demux_un4_idle_on_low_n ( + .I0(com_llm_llm_rx_top_llm_rx_demux_un4_idle_on_low_n_3_2508), + .I1(phy_rd[29]), + .I2(phy_rd[30]), + .I3(phy_rd[31]), + .O(com_llm_llm_rx_top_llm_rx_demux_un4_idle_on_low_n_2511) + ); + defparam com_llm_llm_rx_top_llm_rx_demux_dllp_vld_h_n_q_11_iv_i_a2_0_0.INIT = 16'h4CCC; + LUT4 com_llm_llm_rx_top_llm_rx_demux_dllp_vld_h_n_q_11_iv_i_a2_0_0 ( + .I0(com_llm_llm_rx_top_llm_rx_demux_un4_idle_on_high_n_4_2509), + .I1(phy_rctrl_h), + .I2(phy_rd[38]), + .I3(phy_rd[39]), + .O(com_llm_llm_rx_top_llm_rx_demux_dllp_vld_h_n_q_11_iv_i_a2_0) + ); + defparam com_llm_llm_rx_top_llm_rx_demux_dllp_vld_h_n_q_11_iv_i_a2_0_1_2.INIT = 16'h4000; + LUT4 com_llm_llm_rx_top_llm_rx_demux_dllp_vld_h_n_q_11_iv_i_a2_0_1_2 ( + .I0(com_llm_llm_rx_top_llm_rx_demux_un10_idle_a_n_2510), + .I1(phy_rctrl_h), + .I2(phy_rctrl_l), + .I3(phy_rferr_l_n), + .O(com_llm_llm_rx_top_llm_rx_demux_dllp_vld_h_n_q_11_iv_i_a2_0_1_2_2513) + ); + defparam com_llm_llm_rx_top_llm_rx_demux_dllp_sof_n_q_0_sqmuxa_0_a2.INIT = 16'h2000; + LUT4 com_llm_llm_rx_top_llm_rx_demux_dllp_sof_n_q_0_sqmuxa_0_a2 ( + .I0(com_llm_llm_rx_top_llm_rx_demux_phy_frame_l_t_2518), + .I1(com_llm_llm_rx_top_llm_rx_demux_un4_idle_on_low_n_2511), + .I2(phy_rctrl_l), + .I3(phy_rferr_l_n), + .O(com_llm_llm_rx_top_llm_rx_demux_dllp_sof_n_q_0_sqmuxa) + ); + defparam com_llm_llm_rx_top_llm_rx_demux_dllp_vld_h_n_q_11_iv_i_a2_0_1.INIT = 16'h0008; + LUT4 com_llm_llm_rx_top_llm_rx_demux_dllp_vld_h_n_q_11_iv_i_a2_0_1 ( + .I0(com_llm_llm_rx_top_llm_rx_demux_dllp_vld_h_n_q_11_iv_i_a2_0_1_2_2513), + .I1(com_llm_llm_rx_top_llm_rx_demux_phy_frame_h_t_2551), + .I2(com_llm_llm_rx_top_llm_rx_demux_phy_frame_l_t_2518), + .I3(com_llm_llm_rx_top_llm_rx_demux_un5_idle_a_n_2512), + .O(com_llm_llm_rx_top_llm_rx_demux_N_16012_1) + ); + defparam com_llm_llm_rx_top_llm_rx_demux_dllp_sof_n_q26_m_0_0_a2.INIT = 4'h8; + LUT2 com_llm_llm_rx_top_llm_rx_demux_dllp_sof_n_q26_m_0_0_a2 ( + .I0(com_llm_llm_rx_top_llm_rx_demux_N_16012_1), + .I1(phy_rferr_h_n), + .O(com_llm_llm_rx_top_llm_rx_demux_dllp_sof_n_q26_m_0) + ); + defparam com_llm_llm_rx_top_llm_rx_demux_dllp_eof_n_qq_5_i.INIT = 8'h4C; + LUT3_L com_llm_llm_rx_top_llm_rx_demux_dllp_eof_n_qq_5_i ( + .I0(com_llm_llm_rx_top_llm_rx_demux_dllp_a_2527), + .I1(com_llm_llm_rx_top_llm_rx_demux_dllp_eof_n_q_2524), + .I2(com_llm_llm_rx_top_llm_rx_demux_phy_frame_h_t_2551), + .LO(com_llm_llm_rx_top_llm_rx_demux_N_15935_i) + ); + defparam com_llm_llm_rx_top_llm_rx_demux_dllp_eof_n_q13_i.INIT = 8'h7F; + LUT3_L com_llm_llm_rx_top_llm_rx_demux_dllp_eof_n_q13_i ( + .I0(com_llm_llm_rx_top_llm_rx_demux_N_15978_i), + .I1(com_llm_llm_rx_top_llm_rx_demux_dllp_u_2531), + .I2(phy_rferr_h_n), + .LO(com_llm_llm_rx_top_llm_rx_demux_dllp_eof_n_q13_i_2523) + ); + defparam com_llm_llm_rx_top_llm_rx_demux_N_86947_i.INIT = 16'hFDFC; + LUT4_L com_llm_llm_rx_top_llm_rx_demux_N_86947_i ( + .I0(com_llm_llm_rx_top_llm_rx_demux_N_15977_i), + .I1(com_llm_llm_rx_top_llm_rx_demux_N_15985_i), + .I2(com_llm_llm_rx_top_llm_rx_demux_tlp_sof_n_q_2529), + .I3(com_llm_llm_rx_top_llm_rx_demux_tlp_unalign_q_2533), + .LO(com_llm_llm_rx_top_llm_rx_demux_N_86947_i_2526) + ); + defparam com_llm_llm_rx_top_llm_rx_demux_N_16009_i.INIT = 4'h1; + LUT1_L com_llm_llm_rx_top_llm_rx_demux_N_16009_i ( + .I0(com_llm_llm_rx_top_llm_rx_demux_tlp_ip_flag_5_iv_i_a2_2517), + .LO(com_llm_llm_rx_top_llm_rx_demux_N_16009_i_2528) + ); + defparam com_llm_llm_rx_top_llm_rx_demux_N_86946_i.INIT = 4'hD; + LUT2_L com_llm_llm_rx_top_llm_rx_demux_N_86946_i ( + .I0(com_llm_llm_rx_top_llm_rx_demux_N_15983_i), + .I1(com_llm_llm_rx_top_llm_rx_demux_dllp_vld_h_n_q_2540), + .LO(com_llm_llm_rx_top_llm_rx_demux_N_86946_i_2530) + ); + defparam com_llm_llm_rx_top_llm_rx_demux_dllp_sof_n_q_10_iv_i.INIT = 4'h1; + LUT2_L com_llm_llm_rx_top_llm_rx_demux_dllp_sof_n_q_10_iv_i ( + .I0(com_llm_llm_rx_top_llm_rx_demux_dllp_sof_n_q26_m_0), + .I1(com_llm_llm_rx_top_llm_rx_demux_dllp_sof_n_q_0_sqmuxa), + .LO(com_llm_llm_rx_top_llm_rx_demux_N_15949_i) + ); + defparam com_llm_llm_rx_top_llm_rx_demux_tlp_vld_h_n_qq_7_f0_i.INIT = 16'h3F2A; + LUT4_L com_llm_llm_rx_top_llm_rx_demux_tlp_vld_h_n_qq_7_f0_i ( + .I0(com_llm_llm_rx_top_llm_rx_demux_N_15985_i), + .I1(com_llm_llm_rx_top_llm_rx_demux_phy_frame_l_t_2518), + .I2(com_llm_llm_rx_top_llm_rx_demux_tlp_unalign_q_2533), + .I3(com_llm_llm_rx_top_llm_rx_demux_tlp_vld_h_n_q_2545), + .LO(com_llm_llm_rx_top_llm_rx_demux_N_15941_i) + ); + defparam com_llm_llm_rx_top_llm_rx_demux_tlp_ferr_h_n_q_9_0.INIT = 8'hA2; + LUT3_L com_llm_llm_rx_top_llm_rx_demux_tlp_ferr_h_n_q_9_0 ( + .I0(com_llm_llm_rx_top_llm_rx_demux_tlp_ferr_h_n_q_9_0_39369_2514), + .I1(com_llm_llm_rx_top_llm_rx_demux_tlp_ip_flag_2547), + .I2(phy_rferr_h_n), + .LO(com_llm_llm_rx_top_llm_rx_demux_N_10984_i) + ); + defparam com_llm_llm_rx_top_llm_rx_demux_tlp_sof_n_q_and_tlp_ip_flag_6_u_0_a2.INIT = 4'h8; + LUT2_L com_llm_llm_rx_top_llm_rx_demux_tlp_sof_n_q_and_tlp_ip_flag_6_u_0_a2 ( + .I0(com_llm_llm_rx_top_llm_rx_demux_N_15977_i), + .I1(com_llm_llm_rx_top_llm_rx_demux_tlp_sof_n_q_2529), + .LO(com_llm_llm_rx_top_llm_rx_demux_tlp_sof_n_q_and_tlp_ip_flag_6) + ); + defparam com_llm_llm_rx_top_llm_rx_demux_N_85692_i.INIT = 16'h4F0F; + LUT4_L com_llm_llm_rx_top_llm_rx_demux_N_85692_i ( + .I0(com_llm_llm_rx_top_llm_rx_demux_N_15977_i), + .I1(com_llm_llm_rx_top_llm_rx_demux_tlp_ferr_h_n_q_2535), + .I2(com_llm_llm_rx_top_llm_rx_demux_tlp_ferr_n_qq_8_u_i_1_2515), + .I3(com_llm_llm_rx_top_llm_rx_demux_tlp_unalign_q_2533), + .LO(com_llm_llm_rx_top_llm_rx_demux_N_85692_i_2536) + ); + defparam com_llm_llm_rx_top_llm_rx_demux_N_85691_i.INIT = 16'hF5F7; + LUT4_L com_llm_llm_rx_top_llm_rx_demux_N_85691_i ( + .I0(com_llm_llm_rx_top_llm_rx_demux_N_16020_1), + .I1(com_llm_llm_rx_top_llm_rx_demux_tlp_ip_flag_2547), + .I2(com_llm_llm_rx_top_llm_rx_demux_tlp_unalign_q_2533), + .I3(phy_rctrl_l), + .LO(com_llm_llm_rx_top_llm_rx_demux_N_85691_i_2537) + ); + defparam com_llm_llm_rx_top_llm_rx_demux_N_85673_i.INIT = 16'hF7F3; + LUT4_L com_llm_llm_rx_top_llm_rx_demux_N_85673_i ( + .I0(com_llm_llm_rx_top_llm_rx_demux_N_15978_i), + .I1(com_llm_llm_rx_top_llm_rx_demux_N_15983_i), + .I2(com_llm_llm_rx_top_llm_rx_demux_dllp_sof_n_q_2534), + .I3(com_llm_llm_rx_top_llm_rx_demux_dllp_u_2531), + .LO(com_llm_llm_rx_top_llm_rx_demux_N_85673_i_2538) + ); + defparam com_llm_llm_rx_top_llm_rx_demux_N_86948_i.INIT = 16'hFFDC; + LUT4_L com_llm_llm_rx_top_llm_rx_demux_N_86948_i ( + .I0(com_llm_llm_rx_top_llm_rx_demux_N_15977_i), + .I1(com_llm_llm_rx_top_llm_rx_demux_N_15985_i), + .I2(com_llm_llm_rx_top_llm_rx_demux_tlp_unalign_q_2533), + .I3(com_llm_llm_rx_top_llm_rx_demux_tlp_vld_l_n_q_2549), + .LO(com_llm_llm_rx_top_llm_rx_demux_N_86948_i_2539) + ); + defparam com_llm_llm_rx_top_llm_rx_demux_dllp_vld_h_n_q_11_iv_i.INIT = 16'h1F3F; + LUT4_L com_llm_llm_rx_top_llm_rx_demux_dllp_vld_h_n_q_11_iv_i ( + .I0(com_llm_llm_rx_top_llm_rx_demux_N_15978_i), + .I1(com_llm_llm_rx_top_llm_rx_demux_N_16012_1), + .I2(com_llm_llm_rx_top_llm_rx_demux_N_16012_3), + .I3(com_llm_llm_rx_top_llm_rx_demux_dllp_vld_h_n_q_11_iv_i_a2_0), + .LO(com_llm_llm_rx_top_llm_rx_demux_N_15953_i) + ); + defparam com_llm_llm_rx_top_llm_rx_demux_N_85694_i.INIT = 16'h7773; + LUT4_L com_llm_llm_rx_top_llm_rx_demux_N_85694_i ( + .I0(com_llm_llm_rx_top_llm_rx_demux_N_15979_i), + .I1(com_llm_llm_rx_top_llm_rx_demux_tlp_ferr_n_q_9_u_i_39421_2516), + .I2(phy_rctrl_l), + .I3(phy_rferr_l_n), + .LO(com_llm_llm_rx_top_llm_rx_demux_N_85694_i_2541) + ); + defparam com_llm_llm_rx_top_llm_rx_demux_long_dllp_u_q13_0_a2.INIT = 4'h8; + LUT2_L com_llm_llm_rx_top_llm_rx_demux_long_dllp_u_q13_0_a2 ( + .I0(com_llm_llm_rx_top_llm_rx_demux_N_15977_i), + .I1(com_llm_llm_rx_top_llm_rx_demux_dllp_u_2531), + .LO(com_llm_llm_rx_top_llm_rx_demux_long_dllp_u_q13) + ); + defparam com_llm_llm_rx_top_llm_rx_demux_un1_long_dllp_u_q14_2_i.INIT = 16'hAAA8; + LUT4_L com_llm_llm_rx_top_llm_rx_demux_un1_long_dllp_u_q14_2_i ( + .I0(com_llm_llm_rx_top_llm_rx_demux_un1_long_dllp_u_q14_2_i_1_2519), + .I1(com_llm_llm_rx_top_llm_rx_demux_phy_frame_h_t_2551), + .I2(com_llm_llm_rx_top_llm_rx_demux_tlp_unalign_q_2533), + .I3(phy_rctrl_h), + .LO(com_llm_llm_rx_top_llm_rx_demux_N_15967_i) + ); + defparam com_llm_llm_rx_top_llm_rx_demux_N_86944_i.INIT = 8'hEC; + LUT3_L com_llm_llm_rx_top_llm_rx_demux_N_86944_i ( + .I0(com_llm_llm_rx_top_llm_rx_demux_N_15977_i), + .I1(com_llm_llm_rx_top_llm_rx_demux_tlp_ip_flag_5_iv_i_a2_2517), + .I2(com_llm_llm_rx_top_llm_rx_demux_tlp_ip_flag_2547), + .LO(com_llm_llm_rx_top_llm_rx_demux_N_86944_i_2546) + ); + defparam com_llm_llm_rx_top_llm_rx_demux_tlp_vld_l_n_q_13_0.INIT = 8'hC4; + LUT3_L com_llm_llm_rx_top_llm_rx_demux_tlp_vld_l_n_q_13_0 ( + .I0(com_llm_llm_rx_top_llm_rx_demux_tlp_unalign_q13_i_a2_2532), + .I1(com_llm_llm_rx_top_llm_rx_demux_un1_long_dllp_u_q14_2_i_1_2519), + .I2(com_llm_llm_rx_top_llm_rx_demux_tlp_unalign_q_2533), + .LO(com_llm_llm_rx_top_llm_rx_demux_N_10987_i) + ); + defparam com_llm_llm_rx_top_llm_rx_demux_rx_dllp_sof_n_i.INIT = 4'h1; + LUT1_L com_llm_llm_rx_top_llm_rx_demux_rx_dllp_sof_n_i ( + .I0(com_llm_llm_rx_top_rx_dllp_sof_n), + .LO(com_llm_llm_rx_top_rx_dllp_sof_n_i) + ); + defparam com_llm_llm_rx_top_llm_rx_demux_rx_tferr_n_i.INIT = 4'h1; + LUT1_L com_llm_llm_rx_top_llm_rx_demux_rx_tferr_n_i ( + .I0(com_llm_llm_rx_top_llm_rx_demux_rx_tferr_n), + .LO(com_llm_llm_rx_top_rx_tferr_n_i) + ); + defparam com_llm_llm_rx_top_llm_rx_demux_N_85313_i_1.INIT = 16'h5775; + LUT4 com_llm_llm_rx_top_llm_rx_demux_N_85313_i_1 ( + .I0(com_llm_llm_rx_top_llm_rx_demux_phy_frame_h_t_2551), + .I1(com_llm_llm_rx_top_llm_rx_demux_phy_frame_l_t_2518), + .I2(phy_rctrl_h), + .I3(phy_rctrl_l), + .O(com_llm_llm_rx_top_llm_rx_demux_N_85313_i_1_2555) + ); + defparam com_llm_llm_rx_top_llm_rx_demux_tlp_vld_l_n_q_13_0_o2.INIT = 8'h41; + LUT3 com_llm_llm_rx_top_llm_rx_demux_tlp_vld_l_n_q_13_0_o2 ( + .I0(com_llm_llm_rx_top_llm_rx_demux_phy_frame_l_t_2518), + .I1(phy_rframe_h), + .I2(com_llm_llm_rx_top_llm_rx_demux_phy_frame_h_q_2521), + .O(com_llm_llm_rx_top_llm_rx_demux_N_15977_i) + ); + defparam com_llm_llm_rx_top_llm_rx_demux_tlp_ferr_h_n_q_9_0_o3.INIT = 8'h41; + LUT3 com_llm_llm_rx_top_llm_rx_demux_tlp_ferr_h_n_q_9_0_o3 ( + .I0(phy_rctrl_l), + .I1(phy_rframe_l), + .I2(com_llm_llm_rx_top_llm_rx_demux_phy_frame_l_q_2520), + .O(com_llm_llm_rx_top_llm_rx_demux_N_15980_i) + ); + defparam com_llm_llm_rx_top_llm_rx_demux_un1_long_dllp_u_q14_2_i_1.INIT = 8'h45; + LUT3 com_llm_llm_rx_top_llm_rx_demux_un1_long_dllp_u_q14_2_i_1 ( + .I0(com_llm_llm_rx_top_llm_rx_demux_N_15977_i), + .I1(phy_rctrl_h), + .I2(com_llm_llm_rx_top_llm_rx_demux_N_15980_i), + .O(com_llm_llm_rx_top_llm_rx_demux_un1_long_dllp_u_q14_2_i_1_2519) + ); + FDC com_llm_llm_rx_top_llm_rx_demux_phy_frame_l_q ( + .C(NlwRenamedSig_OI_trn_clk), + .D(phy_rframe_l), + .Q(com_llm_llm_rx_top_llm_rx_demux_phy_frame_l_q_2520), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_demux_phy_frame_h_q ( + .C(NlwRenamedSig_OI_trn_clk), + .D(phy_rframe_h), + .Q(com_llm_llm_rx_top_llm_rx_demux_phy_frame_h_q_2521), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_demux_phy_rbad_frm_qq ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_demux_phy_rbad_frm_q_2522), + .Q(com_llm_llm_rx_top_rx_tlp_nullified), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_demux_phy_rbad_frm_q ( + .C(NlwRenamedSig_OI_trn_clk), + .D(N_62716_i), + .Q(com_llm_llm_rx_top_llm_rx_demux_phy_rbad_frm_q_2522), + .CLR(plm_link_up_i) + ); + FDP com_llm_llm_rx_top_llm_rx_demux_dllp_eof_n_qq ( + .PRE(plm_link_up_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_demux_N_15935_i), + .Q(com_llm_llm_rx_top_rx_dllp_eof_n) + ); + FDP com_llm_llm_rx_top_llm_rx_demux_dllp_eof_n_q ( + .PRE(plm_link_up_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_demux_dllp_eof_n_q13_i_2523), + .Q(com_llm_llm_rx_top_llm_rx_demux_dllp_eof_n_q_2524) + ); + FDC com_llm_llm_rx_top_llm_rx_demux_tlp_align_q ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_demux_tlp_align_q13), + .Q(com_llm_llm_rx_top_llm_rx_demux_tlp_align_q_2525), + .CLR(plm_link_up_i) + ); + FDP com_llm_llm_rx_top_llm_rx_demux_tlp_sof_n_qq ( + .PRE(plm_link_up_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_demux_N_86947_i_2526), + .Q(com_llm_llm_rx_top_rx_tlp_sof_n) + ); + FDC com_llm_llm_rx_top_llm_rx_demux_dllp_a ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_demux_dllp_sof_n_q26_m_0), + .Q(com_llm_llm_rx_top_llm_rx_demux_dllp_a_2527), + .CLR(plm_link_up_i) + ); + FDP com_llm_llm_rx_top_llm_rx_demux_tlp_sof_n_q ( + .PRE(plm_link_up_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_demux_N_16009_i_2528), + .Q(com_llm_llm_rx_top_llm_rx_demux_tlp_sof_n_q_2529) + ); + FDP com_llm_llm_rx_top_llm_rx_demux_dllp_vld_h_n_qq ( + .PRE(plm_link_up_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_demux_N_86946_i_2530), + .Q(com_llm_llm_rx_top_rx_dllp_vld_h_n) + ); + FDC com_llm_llm_rx_top_llm_rx_demux_dllp_u ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_demux_dllp_sof_n_q_0_sqmuxa), + .Q(com_llm_llm_rx_top_llm_rx_demux_dllp_u_2531), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_demux_tlp_unalign_q ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_demux_tlp_unalign_q13_i_a2_2532), + .Q(com_llm_llm_rx_top_llm_rx_demux_tlp_unalign_q_2533), + .CLR(plm_link_up_i) + ); + FDP com_llm_llm_rx_top_llm_rx_demux_dllp_sof_n_q ( + .PRE(plm_link_up_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_demux_N_15949_i), + .Q(com_llm_llm_rx_top_llm_rx_demux_dllp_sof_n_q_2534) + ); + FDP com_llm_llm_rx_top_llm_rx_demux_tlp_vld_h_n_qq ( + .PRE(plm_link_up_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_demux_N_15941_i), + .Q(com_llm_llm_rx_top_rx_tlp_vld_h_n) + ); + FDP com_llm_llm_rx_top_llm_rx_demux_tlp_ferr_h_n_q ( + .PRE(plm_link_up_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_demux_N_10984_i), + .Q(com_llm_llm_rx_top_llm_rx_demux_tlp_ferr_h_n_q_2535) + ); + FDC com_llm_llm_rx_top_llm_rx_demux_tlp_sof_n_q_and_tlp_ip_flag ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_demux_tlp_sof_n_q_and_tlp_ip_flag_6), + .Q(com_llm_llm_rx_top_llm_rx_demux_tlp_sof_n_q_and_tlp_ip_flag_2553), + .CLR(plm_link_up_i) + ); + FDP com_llm_llm_rx_top_llm_rx_demux_tlp_ferr_n_qq ( + .PRE(plm_link_up_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_demux_N_85692_i_2536), + .Q(com_llm_llm_rx_top_llm_rx_demux_rx_tferr_n) + ); + FDP com_llm_llm_rx_top_llm_rx_demux_tlp_eof_n_q ( + .PRE(plm_link_up_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_demux_N_85691_i_2537), + .Q(com_llm_llm_rx_top_llm_rx_demux_tlp_eof_n_q_2554) + ); + FDP com_llm_llm_rx_top_llm_rx_demux_dllp_sof_n_qq ( + .PRE(plm_link_up_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_demux_N_85673_i_2538), + .Q(com_llm_llm_rx_top_rx_dllp_sof_n) + ); + FDP com_llm_llm_rx_top_llm_rx_demux_tlp_vld_l_n_qq ( + .PRE(plm_link_up_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_demux_N_86948_i_2539), + .Q(com_llm_llm_rx_top_rx_tlp_vld_l_n) + ); + FDP com_llm_llm_rx_top_llm_rx_demux_dllp_vld_h_n_q ( + .PRE(plm_link_up_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_demux_N_15953_i), + .Q(com_llm_llm_rx_top_llm_rx_demux_dllp_vld_h_n_q_2540) + ); + FDP com_llm_llm_rx_top_llm_rx_demux_tlp_ferr_n_q ( + .PRE(plm_link_up_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_demux_N_85694_i_2541), + .Q(com_llm_llm_rx_top_llm_rx_demux_tlp_ferr_n_q_2542) + ); + FD com_llm_llm_rx_top_llm_rx_demux_phy_rd_q_0__9_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(phy_rd[9]), + .Q(com_llm_llm_rx_top_llm_rx_demux_phy_rd_q_0_[9]) + ); + FD com_llm_llm_rx_top_llm_rx_demux_phy_rd_q_0__8_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(phy_rd[8]), + .Q(com_llm_llm_rx_top_llm_rx_demux_phy_rd_q_0_[8]) + ); + FD com_llm_llm_rx_top_llm_rx_demux_phy_rd_q_0__7_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(phy_rd[7]), + .Q(com_llm_llm_rx_top_llm_rx_demux_phy_rd_q_0_[7]) + ); + FD com_llm_llm_rx_top_llm_rx_demux_phy_rd_q_0__6_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(phy_rd[6]), + .Q(com_llm_llm_rx_top_llm_rx_demux_phy_rd_q_0_[6]) + ); + FD com_llm_llm_rx_top_llm_rx_demux_phy_rd_q_0__5_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(phy_rd[5]), + .Q(com_llm_llm_rx_top_llm_rx_demux_phy_rd_q_0_[5]) + ); + FD com_llm_llm_rx_top_llm_rx_demux_phy_rd_q_0__4_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(phy_rd[4]), + .Q(com_llm_llm_rx_top_llm_rx_demux_phy_rd_q_0_[4]) + ); + FD com_llm_llm_rx_top_llm_rx_demux_phy_rd_q_0__3_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(phy_rd[3]), + .Q(com_llm_llm_rx_top_llm_rx_demux_phy_rd_q_0_[3]) + ); + FD com_llm_llm_rx_top_llm_rx_demux_phy_rd_q_0__2_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(phy_rd[2]), + .Q(com_llm_llm_rx_top_llm_rx_demux_phy_rd_q_0_[2]) + ); + FD com_llm_llm_rx_top_llm_rx_demux_phy_rd_q_0__1_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(phy_rd[1]), + .Q(com_llm_llm_rx_top_llm_rx_demux_phy_rd_q_0_[1]) + ); + FD com_llm_llm_rx_top_llm_rx_demux_phy_rd_q_0__0_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(phy_rd[0]), + .Q(com_llm_llm_rx_top_llm_rx_demux_phy_rd_q_0_[0]) + ); + FD com_llm_llm_rx_top_llm_rx_demux_phy_rd_q_0__24_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(phy_rd[24]), + .Q(com_llm_llm_rx_top_llm_rx_demux_phy_rd_q_0_[24]) + ); + FD com_llm_llm_rx_top_llm_rx_demux_phy_rd_q_0__23_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(phy_rd[23]), + .Q(com_llm_llm_rx_top_llm_rx_demux_phy_rd_q_0_[23]) + ); + FD com_llm_llm_rx_top_llm_rx_demux_phy_rd_q_0__22_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(phy_rd[22]), + .Q(com_llm_llm_rx_top_llm_rx_demux_phy_rd_q_0_[22]) + ); + FD com_llm_llm_rx_top_llm_rx_demux_phy_rd_q_0__21_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(phy_rd[21]), + .Q(com_llm_llm_rx_top_llm_rx_demux_phy_rd_q_0_[21]) + ); + FD com_llm_llm_rx_top_llm_rx_demux_phy_rd_q_0__20_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(phy_rd[20]), + .Q(com_llm_llm_rx_top_llm_rx_demux_phy_rd_q_0_[20]) + ); + FD com_llm_llm_rx_top_llm_rx_demux_phy_rd_q_0__19_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(phy_rd[19]), + .Q(com_llm_llm_rx_top_llm_rx_demux_phy_rd_q_0_[19]) + ); + FD com_llm_llm_rx_top_llm_rx_demux_phy_rd_q_0__18_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(phy_rd[18]), + .Q(com_llm_llm_rx_top_llm_rx_demux_phy_rd_q_0_[18]) + ); + FD com_llm_llm_rx_top_llm_rx_demux_phy_rd_q_0__17_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(phy_rd[17]), + .Q(com_llm_llm_rx_top_llm_rx_demux_phy_rd_q_0_[17]) + ); + FD com_llm_llm_rx_top_llm_rx_demux_phy_rd_q_0__16_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(phy_rd[16]), + .Q(com_llm_llm_rx_top_llm_rx_demux_phy_rd_q_0_[16]) + ); + FD com_llm_llm_rx_top_llm_rx_demux_phy_rd_q_0__15_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(phy_rd[15]), + .Q(com_llm_llm_rx_top_llm_rx_demux_phy_rd_q_0_[15]) + ); + FD com_llm_llm_rx_top_llm_rx_demux_phy_rd_q_0__14_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(phy_rd[14]), + .Q(com_llm_llm_rx_top_llm_rx_demux_phy_rd_q_0_[14]) + ); + FD com_llm_llm_rx_top_llm_rx_demux_phy_rd_q_0__13_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(phy_rd[13]), + .Q(com_llm_llm_rx_top_llm_rx_demux_phy_rd_q_0_[13]) + ); + FD com_llm_llm_rx_top_llm_rx_demux_phy_rd_q_0__12_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(phy_rd[12]), + .Q(com_llm_llm_rx_top_llm_rx_demux_phy_rd_q_0_[12]) + ); + FD com_llm_llm_rx_top_llm_rx_demux_phy_rd_q_0__11_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(phy_rd[11]), + .Q(com_llm_llm_rx_top_llm_rx_demux_phy_rd_q_0_[11]) + ); + FD com_llm_llm_rx_top_llm_rx_demux_phy_rd_q_0__10_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(phy_rd[10]), + .Q(com_llm_llm_rx_top_llm_rx_demux_phy_rd_q_0_[10]) + ); + FD com_llm_llm_rx_top_llm_rx_demux_phy_rd_q_0__39_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(phy_rd[39]), + .Q(com_llm_llm_rx_top_llm_rx_demux_phy_rd_q_0_[39]) + ); + FD com_llm_llm_rx_top_llm_rx_demux_phy_rd_q_0__38_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(phy_rd[38]), + .Q(com_llm_llm_rx_top_llm_rx_demux_phy_rd_q_0_[38]) + ); + FD com_llm_llm_rx_top_llm_rx_demux_phy_rd_q_0__37_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(phy_rd[37]), + .Q(com_llm_llm_rx_top_llm_rx_demux_phy_rd_q_0_[37]) + ); + FD com_llm_llm_rx_top_llm_rx_demux_phy_rd_q_0__36_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(phy_rd[36]), + .Q(com_llm_llm_rx_top_llm_rx_demux_phy_rd_q_0_[36]) + ); + FD com_llm_llm_rx_top_llm_rx_demux_phy_rd_q_0__35_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(phy_rd[35]), + .Q(com_llm_llm_rx_top_llm_rx_demux_phy_rd_q_0_[35]) + ); + FD com_llm_llm_rx_top_llm_rx_demux_phy_rd_q_0__34_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(phy_rd[34]), + .Q(com_llm_llm_rx_top_llm_rx_demux_phy_rd_q_0_[34]) + ); + FD com_llm_llm_rx_top_llm_rx_demux_phy_rd_q_0__33_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(phy_rd[33]), + .Q(com_llm_llm_rx_top_llm_rx_demux_phy_rd_q_0_[33]) + ); + FD com_llm_llm_rx_top_llm_rx_demux_phy_rd_q_0__32_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(phy_rd[32]), + .Q(com_llm_llm_rx_top_llm_rx_demux_phy_rd_q_0_[32]) + ); + FD com_llm_llm_rx_top_llm_rx_demux_phy_rd_q_0__31_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(phy_rd[31]), + .Q(com_llm_llm_rx_top_llm_rx_demux_phy_rd_q_0_[31]) + ); + FD com_llm_llm_rx_top_llm_rx_demux_phy_rd_q_0__30_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(phy_rd[30]), + .Q(com_llm_llm_rx_top_llm_rx_demux_phy_rd_q_0_[30]) + ); + FD com_llm_llm_rx_top_llm_rx_demux_phy_rd_q_0__29_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(phy_rd[29]), + .Q(com_llm_llm_rx_top_llm_rx_demux_phy_rd_q_0_[29]) + ); + FD com_llm_llm_rx_top_llm_rx_demux_phy_rd_q_0__28_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(phy_rd[28]), + .Q(com_llm_llm_rx_top_llm_rx_demux_phy_rd_q_0_[28]) + ); + FD com_llm_llm_rx_top_llm_rx_demux_phy_rd_q_0__27_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(phy_rd[27]), + .Q(com_llm_llm_rx_top_llm_rx_demux_phy_rd_q_0_[27]) + ); + FD com_llm_llm_rx_top_llm_rx_demux_phy_rd_q_0__26_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(phy_rd[26]), + .Q(com_llm_llm_rx_top_llm_rx_demux_phy_rd_q_0_[26]) + ); + FD com_llm_llm_rx_top_llm_rx_demux_phy_rd_q_0__25_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(phy_rd[25]), + .Q(com_llm_llm_rx_top_llm_rx_demux_phy_rd_q_0_[25]) + ); + FD com_llm_llm_rx_top_llm_rx_demux_phy_rd_q_0__54_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(phy_rd[54]), + .Q(com_llm_llm_rx_top_llm_rx_demux_phy_rd_q_0_[54]) + ); + FD com_llm_llm_rx_top_llm_rx_demux_phy_rd_q_0__53_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(phy_rd[53]), + .Q(com_llm_llm_rx_top_llm_rx_demux_phy_rd_q_0_[53]) + ); + FD com_llm_llm_rx_top_llm_rx_demux_phy_rd_q_0__52_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(phy_rd[52]), + .Q(com_llm_llm_rx_top_llm_rx_demux_phy_rd_q_0_[52]) + ); + FD com_llm_llm_rx_top_llm_rx_demux_phy_rd_q_0__51_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(phy_rd[51]), + .Q(com_llm_llm_rx_top_llm_rx_demux_phy_rd_q_0_[51]) + ); + FD com_llm_llm_rx_top_llm_rx_demux_phy_rd_q_0__50_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(phy_rd[50]), + .Q(com_llm_llm_rx_top_llm_rx_demux_phy_rd_q_0_[50]) + ); + FD com_llm_llm_rx_top_llm_rx_demux_phy_rd_q_0__49_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(phy_rd[49]), + .Q(com_llm_llm_rx_top_llm_rx_demux_phy_rd_q_0_[49]) + ); + FD com_llm_llm_rx_top_llm_rx_demux_phy_rd_q_0__48_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(phy_rd[48]), + .Q(com_llm_llm_rx_top_llm_rx_demux_phy_rd_q_0_[48]) + ); + FD com_llm_llm_rx_top_llm_rx_demux_phy_rd_q_0__47_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(phy_rd[47]), + .Q(com_llm_llm_rx_top_llm_rx_demux_phy_rd_q_0_[47]) + ); + FD com_llm_llm_rx_top_llm_rx_demux_phy_rd_q_0__46_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(phy_rd[46]), + .Q(com_llm_llm_rx_top_llm_rx_demux_phy_rd_q_0_[46]) + ); + FD com_llm_llm_rx_top_llm_rx_demux_phy_rd_q_0__45_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(phy_rd[45]), + .Q(com_llm_llm_rx_top_llm_rx_demux_phy_rd_q_0_[45]) + ); + FD com_llm_llm_rx_top_llm_rx_demux_phy_rd_q_0__44_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(phy_rd[44]), + .Q(com_llm_llm_rx_top_llm_rx_demux_phy_rd_q_0_[44]) + ); + FD com_llm_llm_rx_top_llm_rx_demux_phy_rd_q_0__43_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(phy_rd[43]), + .Q(com_llm_llm_rx_top_llm_rx_demux_phy_rd_q_0_[43]) + ); + FD com_llm_llm_rx_top_llm_rx_demux_phy_rd_q_0__42_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(phy_rd[42]), + .Q(com_llm_llm_rx_top_llm_rx_demux_phy_rd_q_0_[42]) + ); + FD com_llm_llm_rx_top_llm_rx_demux_phy_rd_q_0__41_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(phy_rd[41]), + .Q(com_llm_llm_rx_top_llm_rx_demux_phy_rd_q_0_[41]) + ); + FD com_llm_llm_rx_top_llm_rx_demux_phy_rd_q_0__40_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(phy_rd[40]), + .Q(com_llm_llm_rx_top_llm_rx_demux_phy_rd_q_0_[40]) + ); + FD com_llm_llm_rx_top_llm_rx_demux_phy_rd_q_1__5_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_demux_phy_rd_q_0_[5]), + .Q(com_llm_llm_rx_top_rx_data_5_) + ); + FD com_llm_llm_rx_top_llm_rx_demux_phy_rd_q_1__4_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_demux_phy_rd_q_0_[4]), + .Q(com_llm_llm_rx_top_rx_data_4_) + ); + FD com_llm_llm_rx_top_llm_rx_demux_phy_rd_q_1__3_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_demux_phy_rd_q_0_[3]), + .Q(com_llm_llm_rx_top_rx_data_3_) + ); + FD com_llm_llm_rx_top_llm_rx_demux_phy_rd_q_1__2_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_demux_phy_rd_q_0_[2]), + .Q(com_llm_llm_rx_top_rx_data_2_) + ); + FD com_llm_llm_rx_top_llm_rx_demux_phy_rd_q_1__1_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_demux_phy_rd_q_0_[1]), + .Q(com_llm_llm_rx_top_rx_data_1_) + ); + FD com_llm_llm_rx_top_llm_rx_demux_phy_rd_q_1__0_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_demux_phy_rd_q_0_[0]), + .Q(com_llm_llm_rx_top_rx_data_0_) + ); + FD com_llm_llm_rx_top_llm_rx_demux_phy_rd_q_0__63_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(phy_rd[63]), + .Q(com_llm_llm_rx_top_llm_rx_demux_phy_rd_q_0_[63]) + ); + FD com_llm_llm_rx_top_llm_rx_demux_phy_rd_q_0__62_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(phy_rd[62]), + .Q(com_llm_llm_rx_top_llm_rx_demux_phy_rd_q_0_[62]) + ); + FD com_llm_llm_rx_top_llm_rx_demux_phy_rd_q_0__61_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(phy_rd[61]), + .Q(com_llm_llm_rx_top_llm_rx_demux_phy_rd_q_0_[61]) + ); + FD com_llm_llm_rx_top_llm_rx_demux_phy_rd_q_0__60_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(phy_rd[60]), + .Q(com_llm_llm_rx_top_llm_rx_demux_phy_rd_q_0_[60]) + ); + FD com_llm_llm_rx_top_llm_rx_demux_phy_rd_q_0__59_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(phy_rd[59]), + .Q(com_llm_llm_rx_top_llm_rx_demux_phy_rd_q_0_[59]) + ); + FD com_llm_llm_rx_top_llm_rx_demux_phy_rd_q_0__58_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(phy_rd[58]), + .Q(com_llm_llm_rx_top_llm_rx_demux_phy_rd_q_0_[58]) + ); + FD com_llm_llm_rx_top_llm_rx_demux_phy_rd_q_0__57_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(phy_rd[57]), + .Q(com_llm_llm_rx_top_llm_rx_demux_phy_rd_q_0_[57]) + ); + FD com_llm_llm_rx_top_llm_rx_demux_phy_rd_q_0__56_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(phy_rd[56]), + .Q(com_llm_llm_rx_top_llm_rx_demux_phy_rd_q_0_[56]) + ); + FD com_llm_llm_rx_top_llm_rx_demux_phy_rd_q_0__55_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(phy_rd[55]), + .Q(com_llm_llm_rx_top_llm_rx_demux_phy_rd_q_0_[55]) + ); + FD com_llm_llm_rx_top_llm_rx_demux_phy_rd_q_1__20_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_demux_phy_rd_q_0_[20]), + .Q(com_llm_llm_rx_top_rx_data_20_) + ); + FD com_llm_llm_rx_top_llm_rx_demux_phy_rd_q_1__19_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_demux_phy_rd_q_0_[19]), + .Q(com_llm_llm_rx_top_rx_data_19_) + ); + FD com_llm_llm_rx_top_llm_rx_demux_phy_rd_q_1__18_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_demux_phy_rd_q_0_[18]), + .Q(com_llm_llm_rx_top_rx_data_18_) + ); + FD com_llm_llm_rx_top_llm_rx_demux_phy_rd_q_1__17_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_demux_phy_rd_q_0_[17]), + .Q(com_llm_llm_rx_top_rx_data_17_) + ); + FD com_llm_llm_rx_top_llm_rx_demux_phy_rd_q_1__16_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_demux_phy_rd_q_0_[16]), + .Q(com_llm_llm_rx_top_rx_data_16_) + ); + FD com_llm_llm_rx_top_llm_rx_demux_phy_rd_q_1__15_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_demux_phy_rd_q_0_[15]), + .Q(com_llm_llm_rx_top_rx_data_15_) + ); + FD com_llm_llm_rx_top_llm_rx_demux_phy_rd_q_1__14_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_demux_phy_rd_q_0_[14]), + .Q(com_llm_llm_rx_top_rx_data_14_) + ); + FD com_llm_llm_rx_top_llm_rx_demux_phy_rd_q_1__13_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_demux_phy_rd_q_0_[13]), + .Q(com_llm_llm_rx_top_rx_data_13_) + ); + FD com_llm_llm_rx_top_llm_rx_demux_phy_rd_q_1__12_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_demux_phy_rd_q_0_[12]), + .Q(com_llm_llm_rx_top_rx_data_12_) + ); + FD com_llm_llm_rx_top_llm_rx_demux_phy_rd_q_1__11_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_demux_phy_rd_q_0_[11]), + .Q(com_llm_llm_rx_top_rx_data_11_) + ); + FD com_llm_llm_rx_top_llm_rx_demux_phy_rd_q_1__10_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_demux_phy_rd_q_0_[10]), + .Q(com_llm_llm_rx_top_rx_data_10_) + ); + FD com_llm_llm_rx_top_llm_rx_demux_phy_rd_q_1__9_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_demux_phy_rd_q_0_[9]), + .Q(com_llm_llm_rx_top_rx_data_9_) + ); + FD com_llm_llm_rx_top_llm_rx_demux_phy_rd_q_1__8_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_demux_phy_rd_q_0_[8]), + .Q(com_llm_llm_rx_top_rx_data_8_) + ); + FD com_llm_llm_rx_top_llm_rx_demux_phy_rd_q_1__7_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_demux_phy_rd_q_0_[7]), + .Q(com_llm_llm_rx_top_rx_data_7_) + ); + FD com_llm_llm_rx_top_llm_rx_demux_phy_rd_q_1__6_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_demux_phy_rd_q_0_[6]), + .Q(com_llm_llm_rx_top_rx_data_6_) + ); + FD com_llm_llm_rx_top_llm_rx_demux_phy_rd_q_1__35_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_demux_phy_rd_q_0_[35]), + .Q(com_llm_llm_rx_top_rx_data_35_) + ); + FD com_llm_llm_rx_top_llm_rx_demux_phy_rd_q_1__34_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_demux_phy_rd_q_0_[34]), + .Q(com_llm_llm_rx_top_rx_data_34_) + ); + FD com_llm_llm_rx_top_llm_rx_demux_phy_rd_q_1__33_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_demux_phy_rd_q_0_[33]), + .Q(com_llm_llm_rx_top_rx_data_33_) + ); + FD com_llm_llm_rx_top_llm_rx_demux_phy_rd_q_1__32_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_demux_phy_rd_q_0_[32]), + .Q(com_llm_llm_rx_top_rx_data_32_) + ); + FD com_llm_llm_rx_top_llm_rx_demux_phy_rd_q_1__31_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_demux_phy_rd_q_0_[31]), + .Q(com_llm_llm_rx_top_rx_data_31_) + ); + FD com_llm_llm_rx_top_llm_rx_demux_phy_rd_q_1__30_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_demux_phy_rd_q_0_[30]), + .Q(com_llm_llm_rx_top_rx_data_30_) + ); + FD com_llm_llm_rx_top_llm_rx_demux_phy_rd_q_1__29_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_demux_phy_rd_q_0_[29]), + .Q(com_llm_llm_rx_top_rx_data_29_) + ); + FD com_llm_llm_rx_top_llm_rx_demux_phy_rd_q_1__28_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_demux_phy_rd_q_0_[28]), + .Q(com_llm_llm_rx_top_rx_data_28_) + ); + FD com_llm_llm_rx_top_llm_rx_demux_phy_rd_q_1__27_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_demux_phy_rd_q_0_[27]), + .Q(com_llm_llm_rx_top_rx_data_27_) + ); + FD com_llm_llm_rx_top_llm_rx_demux_phy_rd_q_1__26_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_demux_phy_rd_q_0_[26]), + .Q(com_llm_llm_rx_top_rx_data_26_) + ); + FD com_llm_llm_rx_top_llm_rx_demux_phy_rd_q_1__25_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_demux_phy_rd_q_0_[25]), + .Q(com_llm_llm_rx_top_rx_data_25_) + ); + FD com_llm_llm_rx_top_llm_rx_demux_phy_rd_q_1__24_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_demux_phy_rd_q_0_[24]), + .Q(com_llm_llm_rx_top_rx_data_24_) + ); + FD com_llm_llm_rx_top_llm_rx_demux_phy_rd_q_1__23_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_demux_phy_rd_q_0_[23]), + .Q(com_llm_llm_rx_top_rx_data_23_) + ); + FD com_llm_llm_rx_top_llm_rx_demux_phy_rd_q_1__22_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_demux_phy_rd_q_0_[22]), + .Q(com_llm_llm_rx_top_rx_data_22_) + ); + FD com_llm_llm_rx_top_llm_rx_demux_phy_rd_q_1__21_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_demux_phy_rd_q_0_[21]), + .Q(com_llm_llm_rx_top_rx_data_21_) + ); + FD com_llm_llm_rx_top_llm_rx_demux_phy_rd_q_1__50_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_demux_phy_rd_q_0_[50]), + .Q(com_llm_llm_rx_top_rx_data_50_) + ); + FD com_llm_llm_rx_top_llm_rx_demux_phy_rd_q_1__49_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_demux_phy_rd_q_0_[49]), + .Q(com_llm_llm_rx_top_rx_data_49_) + ); + FD com_llm_llm_rx_top_llm_rx_demux_phy_rd_q_1__48_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_demux_phy_rd_q_0_[48]), + .Q(com_llm_llm_rx_top_rx_data_48_) + ); + FD com_llm_llm_rx_top_llm_rx_demux_phy_rd_q_1__47_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_demux_phy_rd_q_0_[47]), + .Q(com_llm_llm_rx_top_rx_data_47_) + ); + FD com_llm_llm_rx_top_llm_rx_demux_phy_rd_q_1__46_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_demux_phy_rd_q_0_[46]), + .Q(com_llm_llm_rx_top_rx_data_46_) + ); + FD com_llm_llm_rx_top_llm_rx_demux_phy_rd_q_1__45_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_demux_phy_rd_q_0_[45]), + .Q(com_llm_llm_rx_top_rx_data_45_) + ); + FD com_llm_llm_rx_top_llm_rx_demux_phy_rd_q_1__44_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_demux_phy_rd_q_0_[44]), + .Q(com_llm_llm_rx_top_rx_data_44_) + ); + FD com_llm_llm_rx_top_llm_rx_demux_phy_rd_q_1__43_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_demux_phy_rd_q_0_[43]), + .Q(com_llm_llm_rx_top_rx_data_43_) + ); + FD com_llm_llm_rx_top_llm_rx_demux_phy_rd_q_1__42_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_demux_phy_rd_q_0_[42]), + .Q(com_llm_llm_rx_top_rx_data_42_) + ); + FD com_llm_llm_rx_top_llm_rx_demux_phy_rd_q_1__41_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_demux_phy_rd_q_0_[41]), + .Q(com_llm_llm_rx_top_rx_data_41_) + ); + FD com_llm_llm_rx_top_llm_rx_demux_phy_rd_q_1__40_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_demux_phy_rd_q_0_[40]), + .Q(com_llm_llm_rx_top_rx_data_40_) + ); + FD com_llm_llm_rx_top_llm_rx_demux_phy_rd_q_1__39_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_demux_phy_rd_q_0_[39]), + .Q(com_llm_llm_rx_top_rx_data_39_) + ); + FD com_llm_llm_rx_top_llm_rx_demux_phy_rd_q_1__38_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_demux_phy_rd_q_0_[38]), + .Q(com_llm_llm_rx_top_rx_data_38_) + ); + FD com_llm_llm_rx_top_llm_rx_demux_phy_rd_q_1__37_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_demux_phy_rd_q_0_[37]), + .Q(com_llm_llm_rx_top_rx_data_37_) + ); + FD com_llm_llm_rx_top_llm_rx_demux_phy_rd_q_1__36_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_demux_phy_rd_q_0_[36]), + .Q(com_llm_llm_rx_top_rx_data_36_) + ); + FD com_llm_llm_rx_top_llm_rx_demux_phy_rd_q_1__63_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_demux_phy_rd_q_0_[63]), + .Q(com_llm_llm_rx_top_rx_data_63_) + ); + FD com_llm_llm_rx_top_llm_rx_demux_phy_rd_q_1__62_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_demux_phy_rd_q_0_[62]), + .Q(com_llm_llm_rx_top_rx_data_62_) + ); + FD com_llm_llm_rx_top_llm_rx_demux_phy_rd_q_1__61_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_demux_phy_rd_q_0_[61]), + .Q(com_llm_llm_rx_top_rx_data_61_) + ); + FD com_llm_llm_rx_top_llm_rx_demux_phy_rd_q_1__60_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_demux_phy_rd_q_0_[60]), + .Q(com_llm_llm_rx_top_rx_data_60_) + ); + FD com_llm_llm_rx_top_llm_rx_demux_phy_rd_q_1__59_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_demux_phy_rd_q_0_[59]), + .Q(com_llm_llm_rx_top_rx_data_59_) + ); + FD com_llm_llm_rx_top_llm_rx_demux_phy_rd_q_1__58_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_demux_phy_rd_q_0_[58]), + .Q(com_llm_llm_rx_top_rx_data_58_) + ); + FD com_llm_llm_rx_top_llm_rx_demux_phy_rd_q_1__57_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_demux_phy_rd_q_0_[57]), + .Q(com_llm_llm_rx_top_rx_data_57_) + ); + FD com_llm_llm_rx_top_llm_rx_demux_phy_rd_q_1__56_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_demux_phy_rd_q_0_[56]), + .Q(com_llm_llm_rx_top_rx_data_56_) + ); + FD com_llm_llm_rx_top_llm_rx_demux_phy_rd_q_1__55_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_demux_phy_rd_q_0_[55]), + .Q(com_llm_llm_rx_top_rx_data_55_) + ); + FD com_llm_llm_rx_top_llm_rx_demux_phy_rd_q_1__54_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_demux_phy_rd_q_0_[54]), + .Q(com_llm_llm_rx_top_rx_data_54_) + ); + FD com_llm_llm_rx_top_llm_rx_demux_phy_rd_q_1__53_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_demux_phy_rd_q_0_[53]), + .Q(com_llm_llm_rx_top_rx_data_53_) + ); + FD com_llm_llm_rx_top_llm_rx_demux_phy_rd_q_1__52_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_demux_phy_rd_q_0_[52]), + .Q(com_llm_llm_rx_top_rx_data_52_) + ); + FD com_llm_llm_rx_top_llm_rx_demux_phy_rd_q_1__51_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_demux_phy_rd_q_0_[51]), + .Q(com_llm_llm_rx_top_rx_data_51_) + ); + FDCE com_llm_llm_rx_top_llm_rx_demux_long_dllp_u_q ( + .CE(com_llm_llm_rx_top_llm_rx_demux_N_15996_i_2543), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_demux_long_dllp_u_q13), + .Q(com_llm_llm_rx_top_llm_rx_demux_long_dllp_u_q_2544), + .CLR(plm_link_up_i) + ); + FDPE com_llm_llm_rx_top_llm_rx_demux_tlp_vld_h_n_q ( + .PRE(plm_link_up_i), + .CE(com_llm_llm_rx_top_llm_rx_demux_N_16008_i_2548), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_demux_N_15967_i), + .Q(com_llm_llm_rx_top_llm_rx_demux_tlp_vld_h_n_q_2545) + ); + FDCE com_llm_llm_rx_top_llm_rx_demux_tlp_ip_flag ( + .CE(com_llm_llm_rx_top_llm_rx_demux_N_15977_i_i_2550), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_demux_N_86944_i_2546), + .Q(com_llm_llm_rx_top_llm_rx_demux_tlp_ip_flag_2547), + .CLR(plm_link_up_i) + ); + FDPE com_llm_llm_rx_top_llm_rx_demux_tlp_vld_l_n_q ( + .PRE(plm_link_up_i), + .CE(com_llm_llm_rx_top_llm_rx_demux_N_16008_i_2548), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_demux_N_10987_i), + .Q(com_llm_llm_rx_top_llm_rx_demux_tlp_vld_l_n_q_2549) + ); + INV com_llm_llm_rx_top_llm_rx_demux_rx_tlp_sof_n_i ( + .I(com_llm_llm_rx_top_rx_tlp_sof_n), + .O(com_llm_llm_rx_top_rx_tlp_sof_n_i) + ); + INV com_llm_llm_rx_top_llm_rx_demux_rx_tlp_eof_n_i ( + .I(com_llm_llm_rx_top_rx_tlp_eof_n), + .O(com_llm_llm_rx_top_rx_tlp_eof_n_i) + ); + INV com_llm_llm_rx_top_llm_rx_demux_N_15977_i_i ( + .I(com_llm_llm_rx_top_llm_rx_demux_N_15977_i), + .O(com_llm_llm_rx_top_llm_rx_demux_N_15977_i_i_2550) + ); + defparam com_llm_llm_rx_top_llm_rx_demux_tlp_align_q13_0_a2.INIT = 8'h20; + LUT3_L com_llm_llm_rx_top_llm_rx_demux_tlp_align_q13_0_a2 ( + .I0(com_llm_llm_rx_top_llm_rx_demux_phy_frame_h_t_2551), + .I1(phy_rctrl_h), + .I2(com_llm_llm_rx_top_llm_rx_demux_N_15980_i), + .LO(com_llm_llm_rx_top_llm_rx_demux_tlp_align_q13) + ); + defparam com_llm_llm_rx_top_llm_rx_demux_N_85313_i.INIT = 16'hEAF0; + LUT4_L com_llm_llm_rx_top_llm_rx_demux_N_85313_i ( + .I0(com_llm_llm_rx_top_llm_rx_demux_N_16020_1), + .I1(com_llm_llm_rx_top_llm_rx_demux_N_85313_i_1_2555), + .I2(com_llm_llm_rx_top_llm_rx_demux_tlp_eof_n_q_2554), + .I3(com_llm_llm_rx_top_llm_rx_demux_tlp_sof_n_q_and_tlp_ip_flag_2553), + .LO(com_llm_llm_rx_top_llm_rx_demux_N_85313_i_2552) + ); + VCC com_llm_llm_rx_top_llm_rx_dllp_crc_VCC ( + .P(com_llm_llm_rx_top_llm_rx_dllp_crc_VCC_2565) + ); + GND com_llm_llm_rx_top_llm_rx_dllp_crc_GND ( + .G(com_llm_llm_rx_top_llm_rx_dllp_crc_GND_2568) + ); + MUXCY_L com_llm_llm_rx_top_llm_rx_dllp_crc_crc16_ok_0_I_1 ( + .CI(com_llm_llm_rx_top_llm_rx_dllp_crc_VCC_2565), + .DI(com_llm_llm_rx_top_llm_rx_dllp_crc_GND_2568), + .LO(com_llm_llm_rx_top_llm_rx_dllp_crc_data_tmp[0]), + .S(com_llm_llm_rx_top_llm_rx_dllp_crc_N_59) + ); + MUXCY_L com_llm_llm_rx_top_llm_rx_dllp_crc_crc16_ok_0_I_10 ( + .CI(com_llm_llm_rx_top_llm_rx_dllp_crc_data_tmp[0]), + .DI(com_llm_llm_rx_top_llm_rx_dllp_crc_GND_2568), + .LO(com_llm_llm_rx_top_llm_rx_dllp_crc_data_tmp[1]), + .S(com_llm_llm_rx_top_llm_rx_dllp_crc_N_51) + ); + MUXCY_L com_llm_llm_rx_top_llm_rx_dllp_crc_crc16_ok_0_I_19 ( + .CI(com_llm_llm_rx_top_llm_rx_dllp_crc_data_tmp[1]), + .DI(com_llm_llm_rx_top_llm_rx_dllp_crc_GND_2568), + .LO(com_llm_llm_rx_top_llm_rx_dllp_crc_data_tmp[2]), + .S(com_llm_llm_rx_top_llm_rx_dllp_crc_N_43) + ); + MUXCY_L com_llm_llm_rx_top_llm_rx_dllp_crc_crc16_ok_0_I_28 ( + .CI(com_llm_llm_rx_top_llm_rx_dllp_crc_data_tmp[3]), + .DI(com_llm_llm_rx_top_llm_rx_dllp_crc_GND_2568), + .LO(com_llm_llm_rx_top_llm_rx_dllp_crc_data_tmp[4]), + .S(com_llm_llm_rx_top_llm_rx_dllp_crc_N_35) + ); + MUXCY_L com_llm_llm_rx_top_llm_rx_dllp_crc_crc16_ok_0_I_46 ( + .CI(com_llm_llm_rx_top_llm_rx_dllp_crc_data_tmp[4]), + .DI(com_llm_llm_rx_top_llm_rx_dllp_crc_GND_2568), + .LO(com_llm_llm_rx_top_llm_rx_dllp_crc_data_tmp[5]), + .S(com_llm_llm_rx_top_llm_rx_dllp_crc_N_19) + ); + MUXCY_L com_llm_llm_rx_top_llm_rx_dllp_crc_crc16_ok_0_I_55 ( + .CI(com_llm_llm_rx_top_llm_rx_dllp_crc_data_tmp[5]), + .DI(com_llm_llm_rx_top_llm_rx_dllp_crc_GND_2568), + .LO(com_llm_llm_rx_top_llm_rx_dllp_crc_data_tmp[6]), + .S(com_llm_llm_rx_top_llm_rx_dllp_crc_N_11) + ); + MUXCY_L com_llm_llm_rx_top_llm_rx_dllp_crc_crc16_ok_0_I_64 ( + .CI(com_llm_llm_rx_top_llm_rx_dllp_crc_data_tmp[2]), + .DI(com_llm_llm_rx_top_llm_rx_dllp_crc_GND_2568), + .LO(com_llm_llm_rx_top_llm_rx_dllp_crc_data_tmp[3]), + .S(com_llm_llm_rx_top_llm_rx_dllp_crc_N_3) + ); + MUXCY_L com_llm_llm_rx_top_llm_rx_dllp_crc_RX_DLLP_LOW_M1_2_cry_0 ( + .CI(com_llm_llm_rx_top_llm_rx_dllp_crc_GND_2568), + .DI(com_llm_llm_rx_top_llm_rx_dllp_crc_VCC_2565), + .LO(com_llm_llm_rx_top_llm_rx_dllp_crc_RX_DLLP_LOW_M1_2_cry_0_2556), + .S(N_71026_i_17) + ); + MUXCY_L com_llm_llm_rx_top_llm_rx_dllp_crc_RX_DLLP_LOW_M1_2_cry_1 ( + .CI(com_llm_llm_rx_top_llm_rx_dllp_crc_RX_DLLP_LOW_M1_2_cry_0_2556), + .DI(com_llm_llm_rx_top_llm_rx_dllp_crc_VCC_2565), + .LO(com_llm_llm_rx_top_llm_rx_dllp_crc_RX_DLLP_LOW_M1_2_cry_1_2557), + .S(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_dllp_d_i[1]) + ); + XORCY com_llm_llm_rx_top_llm_rx_dllp_crc_RX_DLLP_LOW_M1_2_s_1 ( + .CI(com_llm_llm_rx_top_llm_rx_dllp_crc_RX_DLLP_LOW_M1_2_cry_0_2556), + .LI(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_dllp_d_i[1]), + .O(com_llm_llm_rx_top_llm_rx_dllp_crc_RX_DLLP_LOW_M1_2[1]) + ); + MUXCY_L com_llm_llm_rx_top_llm_rx_dllp_crc_RX_DLLP_LOW_M1_2_cry_2 ( + .CI(com_llm_llm_rx_top_llm_rx_dllp_crc_RX_DLLP_LOW_M1_2_cry_1_2557), + .DI(com_llm_llm_rx_top_llm_rx_dllp_crc_VCC_2565), + .LO(com_llm_llm_rx_top_llm_rx_dllp_crc_RX_DLLP_LOW_M1_2_cry_2_2558), + .S(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_dllp_d_i[2]) + ); + XORCY com_llm_llm_rx_top_llm_rx_dllp_crc_RX_DLLP_LOW_M1_2_s_2 ( + .CI(com_llm_llm_rx_top_llm_rx_dllp_crc_RX_DLLP_LOW_M1_2_cry_1_2557), + .LI(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_dllp_d_i[2]), + .O(com_llm_llm_rx_top_llm_rx_dllp_crc_RX_DLLP_LOW_M1_2[2]) + ); + MUXCY_L com_llm_llm_rx_top_llm_rx_dllp_crc_RX_DLLP_LOW_M1_2_cry_3 ( + .CI(com_llm_llm_rx_top_llm_rx_dllp_crc_RX_DLLP_LOW_M1_2_cry_2_2558), + .DI(com_llm_llm_rx_top_llm_rx_dllp_crc_VCC_2565), + .LO(com_llm_llm_rx_top_llm_rx_dllp_crc_RX_DLLP_LOW_M1_2_cry_3_2559), + .S(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_dllp_d_i[3]) + ); + XORCY com_llm_llm_rx_top_llm_rx_dllp_crc_RX_DLLP_LOW_M1_2_s_3 ( + .CI(com_llm_llm_rx_top_llm_rx_dllp_crc_RX_DLLP_LOW_M1_2_cry_2_2558), + .LI(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_dllp_d_i[3]), + .O(com_llm_llm_rx_top_llm_rx_dllp_crc_RX_DLLP_LOW_M1_2[3]) + ); + MUXCY_L com_llm_llm_rx_top_llm_rx_dllp_crc_RX_DLLP_LOW_M1_2_cry_4 ( + .CI(com_llm_llm_rx_top_llm_rx_dllp_crc_RX_DLLP_LOW_M1_2_cry_3_2559), + .DI(com_llm_llm_rx_top_llm_rx_dllp_crc_VCC_2565), + .LO(com_llm_llm_rx_top_llm_rx_dllp_crc_RX_DLLP_LOW_M1_2_cry_4_2560), + .S(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_dllp_d_i[4]) + ); + XORCY com_llm_llm_rx_top_llm_rx_dllp_crc_RX_DLLP_LOW_M1_2_s_4 ( + .CI(com_llm_llm_rx_top_llm_rx_dllp_crc_RX_DLLP_LOW_M1_2_cry_3_2559), + .LI(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_dllp_d_i[4]), + .O(com_llm_llm_rx_top_llm_rx_dllp_crc_RX_DLLP_LOW_M1_2[4]) + ); + MUXCY_L com_llm_llm_rx_top_llm_rx_dllp_crc_RX_DLLP_LOW_M1_2_cry_5 ( + .CI(com_llm_llm_rx_top_llm_rx_dllp_crc_RX_DLLP_LOW_M1_2_cry_4_2560), + .DI(com_llm_llm_rx_top_llm_rx_dllp_crc_VCC_2565), + .LO(com_llm_llm_rx_top_llm_rx_dllp_crc_RX_DLLP_LOW_M1_2_cry_5_2561), + .S(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_dllp_d_i[5]) + ); + XORCY com_llm_llm_rx_top_llm_rx_dllp_crc_RX_DLLP_LOW_M1_2_s_5 ( + .CI(com_llm_llm_rx_top_llm_rx_dllp_crc_RX_DLLP_LOW_M1_2_cry_4_2560), + .LI(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_dllp_d_i[5]), + .O(com_llm_llm_rx_top_llm_rx_dllp_crc_RX_DLLP_LOW_M1_2[5]) + ); + MUXCY_L com_llm_llm_rx_top_llm_rx_dllp_crc_RX_DLLP_LOW_M1_2_cry_6 ( + .CI(com_llm_llm_rx_top_llm_rx_dllp_crc_RX_DLLP_LOW_M1_2_cry_5_2561), + .DI(com_llm_llm_rx_top_llm_rx_dllp_crc_VCC_2565), + .LO(com_llm_llm_rx_top_llm_rx_dllp_crc_RX_DLLP_LOW_M1_2_cry_6_2562), + .S(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_dllp_d_i[6]) + ); + XORCY com_llm_llm_rx_top_llm_rx_dllp_crc_RX_DLLP_LOW_M1_2_s_6 ( + .CI(com_llm_llm_rx_top_llm_rx_dllp_crc_RX_DLLP_LOW_M1_2_cry_5_2561), + .LI(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_dllp_d_i[6]), + .O(com_llm_llm_rx_top_llm_rx_dllp_crc_RX_DLLP_LOW_M1_2[6]) + ); + MUXCY_L com_llm_llm_rx_top_llm_rx_dllp_crc_RX_DLLP_LOW_M1_2_cry_7 ( + .CI(com_llm_llm_rx_top_llm_rx_dllp_crc_RX_DLLP_LOW_M1_2_cry_6_2562), + .DI(com_llm_llm_rx_top_llm_rx_dllp_crc_VCC_2565), + .LO(com_llm_llm_rx_top_llm_rx_dllp_crc_RX_DLLP_LOW_M1_2_cry_7_2563), + .S(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_dllp_d_i[7]) + ); + XORCY com_llm_llm_rx_top_llm_rx_dllp_crc_RX_DLLP_LOW_M1_2_s_7 ( + .CI(com_llm_llm_rx_top_llm_rx_dllp_crc_RX_DLLP_LOW_M1_2_cry_6_2562), + .LI(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_dllp_d_i[7]), + .O(com_llm_llm_rx_top_llm_rx_dllp_crc_RX_DLLP_LOW_M1_2[7]) + ); + MUXCY_L com_llm_llm_rx_top_llm_rx_dllp_crc_RX_DLLP_LOW_M1_2_cry_8 ( + .CI(com_llm_llm_rx_top_llm_rx_dllp_crc_RX_DLLP_LOW_M1_2_cry_7_2563), + .DI(com_llm_llm_rx_top_llm_rx_dllp_crc_VCC_2565), + .LO(com_llm_llm_rx_top_llm_rx_dllp_crc_RX_DLLP_LOW_M1_2_cry_8_2564), + .S(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_dllp_d_i[8]) + ); + XORCY com_llm_llm_rx_top_llm_rx_dllp_crc_RX_DLLP_LOW_M1_2_s_8 ( + .CI(com_llm_llm_rx_top_llm_rx_dllp_crc_RX_DLLP_LOW_M1_2_cry_7_2563), + .LI(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_dllp_d_i[8]), + .O(com_llm_llm_rx_top_llm_rx_dllp_crc_RX_DLLP_LOW_M1_2[8]) + ); + MUXCY_L com_llm_llm_rx_top_llm_rx_dllp_crc_RX_DLLP_LOW_M1_2_cry_9 ( + .CI(com_llm_llm_rx_top_llm_rx_dllp_crc_RX_DLLP_LOW_M1_2_cry_8_2564), + .DI(com_llm_llm_rx_top_llm_rx_dllp_crc_VCC_2565), + .LO(com_llm_llm_rx_top_llm_rx_dllp_crc_RX_DLLP_LOW_M1_2_cry_9_2566), + .S(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_dllp_d_i[9]) + ); + XORCY com_llm_llm_rx_top_llm_rx_dllp_crc_RX_DLLP_LOW_M1_2_s_9 ( + .CI(com_llm_llm_rx_top_llm_rx_dllp_crc_RX_DLLP_LOW_M1_2_cry_8_2564), + .LI(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_dllp_d_i[9]), + .O(com_llm_llm_rx_top_llm_rx_dllp_crc_RX_DLLP_LOW_M1_2[9]) + ); + MUXCY_L com_llm_llm_rx_top_llm_rx_dllp_crc_RX_DLLP_LOW_M1_2_cry_10 ( + .CI(com_llm_llm_rx_top_llm_rx_dllp_crc_RX_DLLP_LOW_M1_2_cry_9_2566), + .DI(com_llm_llm_rx_top_llm_rx_dllp_crc_VCC_2565), + .LO(com_llm_llm_rx_top_llm_rx_dllp_crc_RX_DLLP_LOW_M1_2_cry_10_2567), + .S(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_dllp_d_i[10]) + ); + XORCY com_llm_llm_rx_top_llm_rx_dllp_crc_RX_DLLP_LOW_M1_2_s_10 ( + .CI(com_llm_llm_rx_top_llm_rx_dllp_crc_RX_DLLP_LOW_M1_2_cry_9_2566), + .LI(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_dllp_d_i[10]), + .O(com_llm_llm_rx_top_llm_rx_dllp_crc_RX_DLLP_LOW_M1_2[10]) + ); + XORCY com_llm_llm_rx_top_llm_rx_dllp_crc_RX_DLLP_LOW_M1_2_s_11 ( + .CI(com_llm_llm_rx_top_llm_rx_dllp_crc_RX_DLLP_LOW_M1_2_cry_10_2567), + .LI(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_dllp_d_i[11]), + .O(com_llm_llm_rx_top_llm_rx_dllp_crc_RX_DLLP_LOW_M1_2[11]) + ); + defparam com_llm_llm_rx_top_llm_rx_dllp_crc_un1_crc16_ok_0_15_.INIT = 8'hCA; + LUT3 com_llm_llm_rx_top_llm_rx_dllp_crc_un1_crc16_ok_0_15_ ( + .I0(com_llm_llm_rx_top_llm_rx_dllp_crc_crc16_d32_nst[8]), + .I1(com_llm_llm_rx_top_llm_rx_dllp_crc_crc16_d32_st[8]), + .I2(com_llm_llm_rx_top_llm_rx_dllp_crc_fr_straddle_q_2569), + .O(com_llm_llm_rx_top_llm_rx_dllp_crc_un1_crc16_ok_0[15]) + ); + defparam com_llm_llm_rx_top_llm_rx_dllp_crc_un1_crc16_ok_0_14_.INIT = 8'hCA; + LUT3 com_llm_llm_rx_top_llm_rx_dllp_crc_un1_crc16_ok_0_14_ ( + .I0(com_llm_llm_rx_top_llm_rx_dllp_crc_crc16_d32_nst[9]), + .I1(com_llm_llm_rx_top_llm_rx_dllp_crc_crc16_d32_st[9]), + .I2(com_llm_llm_rx_top_llm_rx_dllp_crc_fr_straddle_q_2569), + .O(com_llm_llm_rx_top_llm_rx_dllp_crc_un1_crc16_ok_0[14]) + ); + defparam com_llm_llm_rx_top_llm_rx_dllp_crc_un1_crc16_ok_0_13_.INIT = 8'hCA; + LUT3 com_llm_llm_rx_top_llm_rx_dllp_crc_un1_crc16_ok_0_13_ ( + .I0(com_llm_llm_rx_top_llm_rx_dllp_crc_crc16_d32_nst[10]), + .I1(com_llm_llm_rx_top_llm_rx_dllp_crc_crc16_d32_st[10]), + .I2(com_llm_llm_rx_top_llm_rx_dllp_crc_fr_straddle_q_2569), + .O(com_llm_llm_rx_top_llm_rx_dllp_crc_un1_crc16_ok_0[13]) + ); + defparam com_llm_llm_rx_top_llm_rx_dllp_crc_un1_crc16_ok_0_12_.INIT = 8'hCA; + LUT3 com_llm_llm_rx_top_llm_rx_dllp_crc_un1_crc16_ok_0_12_ ( + .I0(com_llm_llm_rx_top_llm_rx_dllp_crc_crc16_d32_nst[11]), + .I1(com_llm_llm_rx_top_llm_rx_dllp_crc_crc16_d32_st[11]), + .I2(com_llm_llm_rx_top_llm_rx_dllp_crc_fr_straddle_q_2569), + .O(com_llm_llm_rx_top_llm_rx_dllp_crc_un1_crc16_ok_0[12]) + ); + defparam com_llm_llm_rx_top_llm_rx_dllp_crc_un1_crc16_ok_0_11_.INIT = 8'hCA; + LUT3 com_llm_llm_rx_top_llm_rx_dllp_crc_un1_crc16_ok_0_11_ ( + .I0(com_llm_llm_rx_top_llm_rx_dllp_crc_crc16_d32_nst[12]), + .I1(com_llm_llm_rx_top_llm_rx_dllp_crc_crc16_d32_st[12]), + .I2(com_llm_llm_rx_top_llm_rx_dllp_crc_fr_straddle_q_2569), + .O(com_llm_llm_rx_top_llm_rx_dllp_crc_un1_crc16_ok_0[11]) + ); + defparam com_llm_llm_rx_top_llm_rx_dllp_crc_un1_crc16_ok_0_10_.INIT = 8'hCA; + LUT3 com_llm_llm_rx_top_llm_rx_dllp_crc_un1_crc16_ok_0_10_ ( + .I0(com_llm_llm_rx_top_llm_rx_dllp_crc_crc16_d32_nst[13]), + .I1(com_llm_llm_rx_top_llm_rx_dllp_crc_crc16_d32_st[13]), + .I2(com_llm_llm_rx_top_llm_rx_dllp_crc_fr_straddle_q_2569), + .O(com_llm_llm_rx_top_llm_rx_dllp_crc_un1_crc16_ok_0[10]) + ); + defparam com_llm_llm_rx_top_llm_rx_dllp_crc_un1_crc16_ok_0_9_.INIT = 8'hCA; + LUT3 com_llm_llm_rx_top_llm_rx_dllp_crc_un1_crc16_ok_0_9_ ( + .I0(com_llm_llm_rx_top_llm_rx_dllp_crc_crc16_d32_nst[14]), + .I1(com_llm_llm_rx_top_llm_rx_dllp_crc_crc16_d32_st[14]), + .I2(com_llm_llm_rx_top_llm_rx_dllp_crc_fr_straddle_q_2569), + .O(com_llm_llm_rx_top_llm_rx_dllp_crc_un1_crc16_ok_0[9]) + ); + defparam com_llm_llm_rx_top_llm_rx_dllp_crc_un1_crc16_ok_0_8_.INIT = 8'hCA; + LUT3 com_llm_llm_rx_top_llm_rx_dllp_crc_un1_crc16_ok_0_8_ ( + .I0(com_llm_llm_rx_top_llm_rx_dllp_crc_crc16_d32_nst[15]), + .I1(com_llm_llm_rx_top_llm_rx_dllp_crc_crc16_d32_st[15]), + .I2(com_llm_llm_rx_top_llm_rx_dllp_crc_fr_straddle_q_2569), + .O(com_llm_llm_rx_top_llm_rx_dllp_crc_un1_crc16_ok_0[8]) + ); + defparam com_llm_llm_rx_top_llm_rx_dllp_crc_un1_crc16_ok_0_7_.INIT = 8'hCA; + LUT3 com_llm_llm_rx_top_llm_rx_dllp_crc_un1_crc16_ok_0_7_ ( + .I0(com_llm_llm_rx_top_llm_rx_dllp_crc_crc16_d32_nst[0]), + .I1(com_llm_llm_rx_top_llm_rx_dllp_crc_crc16_d32_st[0]), + .I2(com_llm_llm_rx_top_llm_rx_dllp_crc_fr_straddle_q_2569), + .O(com_llm_llm_rx_top_llm_rx_dllp_crc_un1_crc16_ok_0[7]) + ); + defparam com_llm_llm_rx_top_llm_rx_dllp_crc_un1_crc16_ok_0_6_.INIT = 8'hCA; + LUT3 com_llm_llm_rx_top_llm_rx_dllp_crc_un1_crc16_ok_0_6_ ( + .I0(com_llm_llm_rx_top_llm_rx_dllp_crc_crc16_d32_nst[1]), + .I1(com_llm_llm_rx_top_llm_rx_dllp_crc_crc16_d32_st[1]), + .I2(com_llm_llm_rx_top_llm_rx_dllp_crc_fr_straddle_q_2569), + .O(com_llm_llm_rx_top_llm_rx_dllp_crc_un1_crc16_ok_0[6]) + ); + defparam com_llm_llm_rx_top_llm_rx_dllp_crc_un1_crc16_ok_0_5_.INIT = 8'hCA; + LUT3 com_llm_llm_rx_top_llm_rx_dllp_crc_un1_crc16_ok_0_5_ ( + .I0(com_llm_llm_rx_top_llm_rx_dllp_crc_crc16_d32_nst[2]), + .I1(com_llm_llm_rx_top_llm_rx_dllp_crc_crc16_d32_st[2]), + .I2(com_llm_llm_rx_top_llm_rx_dllp_crc_fr_straddle_q_2569), + .O(com_llm_llm_rx_top_llm_rx_dllp_crc_un1_crc16_ok_0[5]) + ); + defparam com_llm_llm_rx_top_llm_rx_dllp_crc_un1_crc16_ok_0_4_.INIT = 8'hCA; + LUT3 com_llm_llm_rx_top_llm_rx_dllp_crc_un1_crc16_ok_0_4_ ( + .I0(com_llm_llm_rx_top_llm_rx_dllp_crc_crc16_d32_nst[3]), + .I1(com_llm_llm_rx_top_llm_rx_dllp_crc_crc16_d32_st[3]), + .I2(com_llm_llm_rx_top_llm_rx_dllp_crc_fr_straddle_q_2569), + .O(com_llm_llm_rx_top_llm_rx_dllp_crc_un1_crc16_ok_0[4]) + ); + defparam com_llm_llm_rx_top_llm_rx_dllp_crc_un1_crc16_ok_0_3_.INIT = 8'hCA; + LUT3 com_llm_llm_rx_top_llm_rx_dllp_crc_un1_crc16_ok_0_3_ ( + .I0(com_llm_llm_rx_top_llm_rx_dllp_crc_crc16_d32_nst[4]), + .I1(com_llm_llm_rx_top_llm_rx_dllp_crc_crc16_d32_st[4]), + .I2(com_llm_llm_rx_top_llm_rx_dllp_crc_fr_straddle_q_2569), + .O(com_llm_llm_rx_top_llm_rx_dllp_crc_un1_crc16_ok_0[3]) + ); + defparam com_llm_llm_rx_top_llm_rx_dllp_crc_un1_crc16_ok_0_2_.INIT = 8'hCA; + LUT3 com_llm_llm_rx_top_llm_rx_dllp_crc_un1_crc16_ok_0_2_ ( + .I0(com_llm_llm_rx_top_llm_rx_dllp_crc_crc16_d32_nst[5]), + .I1(com_llm_llm_rx_top_llm_rx_dllp_crc_crc16_d32_st[5]), + .I2(com_llm_llm_rx_top_llm_rx_dllp_crc_fr_straddle_q_2569), + .O(com_llm_llm_rx_top_llm_rx_dllp_crc_un1_crc16_ok_0[2]) + ); + defparam com_llm_llm_rx_top_llm_rx_dllp_crc_un1_crc16_ok_0_1_.INIT = 8'hCA; + LUT3 com_llm_llm_rx_top_llm_rx_dllp_crc_un1_crc16_ok_0_1_ ( + .I0(com_llm_llm_rx_top_llm_rx_dllp_crc_crc16_d32_nst[6]), + .I1(com_llm_llm_rx_top_llm_rx_dllp_crc_crc16_d32_st[6]), + .I2(com_llm_llm_rx_top_llm_rx_dllp_crc_fr_straddle_q_2569), + .O(com_llm_llm_rx_top_llm_rx_dllp_crc_un1_crc16_ok_0[1]) + ); + defparam com_llm_llm_rx_top_llm_rx_dllp_crc_un1_crc16_ok_0_0_.INIT = 8'hCA; + LUT3 com_llm_llm_rx_top_llm_rx_dllp_crc_un1_crc16_ok_0_0_ ( + .I0(com_llm_llm_rx_top_llm_rx_dllp_crc_crc16_d32_nst[7]), + .I1(com_llm_llm_rx_top_llm_rx_dllp_crc_crc16_d32_st[7]), + .I2(com_llm_llm_rx_top_llm_rx_dllp_crc_fr_straddle_q_2569), + .O(com_llm_llm_rx_top_llm_rx_dllp_crc_un1_crc16_ok_0[0]) + ); + defparam com_llm_llm_rx_top_llm_rx_dllp_crc_N_87608_i.INIT = 16'h0C32; + LUT4 com_llm_llm_rx_top_llm_rx_dllp_crc_N_87608_i ( + .I0(com_llm_llm_rx_top_llm_rx_dllp_crc_fr_straddle_2614), + .I1(com_llm_llm_rx_top_rx_dllp_eof_n), + .I2(com_llm_llm_rx_top_rx_dllp_sof_n), + .I3(com_llm_llm_rx_top_rx_dllp_vld_h_n), + .O(com_llm_llm_rx_top_llm_rx_dllp_crc_N_87608_i_2613) + ); + defparam com_llm_llm_rx_top_llm_rx_dllp_crc_str_dllp_0_a2_0_a2.INIT = 4'h2; + LUT2_L com_llm_llm_rx_top_llm_rx_dllp_crc_str_dllp_0_a2_0_a2 ( + .I0(com_llm_llm_rx_top_llm_rx_dllp_crc_fr_straddle_2614), + .I1(com_llm_llm_rx_top_rx_dllp_eof_n), + .LO(com_llm_llm_rx_top_llm_rx_dllp_crc_str_dllp) + ); + defparam com_llm_llm_rx_top_llm_rx_dllp_crc_reg_dllp_0_a2.INIT = 4'h1; + LUT2_L com_llm_llm_rx_top_llm_rx_dllp_crc_reg_dllp_0_a2 ( + .I0(com_llm_llm_rx_top_llm_rx_dllp_crc_fr_straddle_2614), + .I1(com_llm_llm_rx_top_rx_dllp_eof_n), + .LO(com_llm_llm_rx_top_llm_rx_dllp_crc_reg_dllp) + ); + defparam com_llm_llm_rx_top_llm_rx_dllp_crc_N_27234_i.INIT = 8'hAB; + LUT3_L com_llm_llm_rx_top_llm_rx_dllp_crc_N_27234_i ( + .I0(com_llm_llm_rx_top_llm_rx_dllp_crc_crc16_ok), + .I1(com_llm_llm_rx_top_llm_rx_dllp_crc_reg_dllp_qq_2570), + .I2(com_llm_llm_rx_top_llm_rx_dllp_crc_str_dllp_q_2571), + .LO(com_llm_llm_rx_top_llm_rx_dllp_crc_N_27234_i_2573) + ); + defparam com_llm_llm_rx_top_llm_rx_dllp_crc_RX_DLLP_VLD_5_0_a2.INIT = 8'hA8; + LUT3_L com_llm_llm_rx_top_llm_rx_dllp_crc_RX_DLLP_VLD_5_0_a2 ( + .I0(com_llm_llm_rx_top_llm_rx_dllp_crc_crc16_ok), + .I1(com_llm_llm_rx_top_llm_rx_dllp_crc_reg_dllp_qq_2570), + .I2(com_llm_llm_rx_top_llm_rx_dllp_crc_str_dllp_q_2571), + .LO(com_llm_llm_rx_top_llm_rx_dllp_crc_RX_DLLP_VLD_5) + ); + defparam com_llm_llm_rx_top_llm_rx_dllp_crc_rx_dllp_d_4_i_m3_0_0_.INIT = 8'hE4; + LUT3_L com_llm_llm_rx_top_llm_rx_dllp_crc_rx_dllp_d_4_i_m3_0_0_ ( + .I0(com_llm_llm_rx_top_llm_rx_dllp_crc_fr_straddle_2614), + .I1(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_24_), + .I2(com_llm_llm_rx_top_rx_data_56_), + .LO(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_dllp_d_4_i_m3_0_0__2574) + ); + defparam com_llm_llm_rx_top_llm_rx_dllp_crc_rx_dllp_d_4_i_m3_0_17_.INIT = 8'hD8; + LUT3_L com_llm_llm_rx_top_llm_rx_dllp_crc_rx_dllp_d_4_i_m3_0_17_ ( + .I0(com_llm_llm_rx_top_llm_rx_dllp_crc_fr_straddle_2614), + .I1(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_9_), + .I2(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_41_), + .LO(com_llm_llm_rx_top_rx_dllp_d_4_i_m3_0_17_) + ); + defparam com_llm_llm_rx_top_llm_rx_dllp_crc_rx_dllp_d_4_i_m2_i_m3_0_16_.INIT = 8'hD8; + LUT3_L com_llm_llm_rx_top_llm_rx_dllp_crc_rx_dllp_d_4_i_m2_i_m3_0_16_ ( + .I0(com_llm_llm_rx_top_llm_rx_dllp_crc_fr_straddle_2614), + .I1(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_8_), + .I2(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_40_), + .LO(com_llm_llm_rx_top_rx_dllp_d_4_i_m2_i_m3_0_16_) + ); + defparam com_llm_llm_rx_top_llm_rx_dllp_crc_rx_dllp_d_4_i_m3_0_15_.INIT = 8'hD8; + LUT3_L com_llm_llm_rx_top_llm_rx_dllp_crc_rx_dllp_d_4_i_m3_0_15_ ( + .I0(com_llm_llm_rx_top_llm_rx_dllp_crc_fr_straddle_2614), + .I1(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_7_), + .I2(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_39_), + .LO(com_llm_llm_rx_top_rx_dllp_d_4_i_m3_0_15_) + ); + defparam com_llm_llm_rx_top_llm_rx_dllp_crc_rx_dllp_d_4_i_m3_0_14_.INIT = 8'hD8; + LUT3_L com_llm_llm_rx_top_llm_rx_dllp_crc_rx_dllp_d_4_i_m3_0_14_ ( + .I0(com_llm_llm_rx_top_llm_rx_dllp_crc_fr_straddle_2614), + .I1(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_6_), + .I2(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_38_), + .LO(com_llm_llm_rx_top_rx_dllp_d_4_i_m3_0_14_) + ); + defparam com_llm_llm_rx_top_llm_rx_dllp_crc_rx_dllp_d_4_i_m3_0_11_.INIT = 8'hD8; + LUT3_L com_llm_llm_rx_top_llm_rx_dllp_crc_rx_dllp_d_4_i_m3_0_11_ ( + .I0(com_llm_llm_rx_top_llm_rx_dllp_crc_fr_straddle_2614), + .I1(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_3_), + .I2(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_35_), + .LO(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_dllp_d_4_i_m3_0_11__2575) + ); + defparam com_llm_llm_rx_top_llm_rx_dllp_crc_rx_dllp_d_4_i_m3_0_10_.INIT = 8'hD8; + LUT3_L com_llm_llm_rx_top_llm_rx_dllp_crc_rx_dllp_d_4_i_m3_0_10_ ( + .I0(com_llm_llm_rx_top_llm_rx_dllp_crc_fr_straddle_2614), + .I1(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_2_), + .I2(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_34_), + .LO(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_dllp_d_4_i_m3_0_10__2576) + ); + defparam com_llm_llm_rx_top_llm_rx_dllp_crc_rx_dllp_d_4_i_m3_0_9_.INIT = 8'hD8; + LUT3_L com_llm_llm_rx_top_llm_rx_dllp_crc_rx_dllp_d_4_i_m3_0_9_ ( + .I0(com_llm_llm_rx_top_llm_rx_dllp_crc_fr_straddle_2614), + .I1(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_1_), + .I2(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_33_), + .LO(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_dllp_d_4_i_m3_0_9__2577) + ); + defparam com_llm_llm_rx_top_llm_rx_dllp_crc_rx_dllp_d_4_i_m3_0_8_.INIT = 8'hD8; + LUT3_L com_llm_llm_rx_top_llm_rx_dllp_crc_rx_dllp_d_4_i_m3_0_8_ ( + .I0(com_llm_llm_rx_top_llm_rx_dllp_crc_fr_straddle_2614), + .I1(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_0_), + .I2(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_32_), + .LO(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_dllp_d_4_i_m3_0_8__2578) + ); + defparam com_llm_llm_rx_top_llm_rx_dllp_crc_rx_dllp_d_4_i_m2_i_m3_0_7_.INIT = 8'hE4; + LUT3_L com_llm_llm_rx_top_llm_rx_dllp_crc_rx_dllp_d_4_i_m2_i_m3_0_7_ ( + .I0(com_llm_llm_rx_top_llm_rx_dllp_crc_fr_straddle_2614), + .I1(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_31_), + .I2(com_llm_llm_rx_top_rx_data_63_), + .LO(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_dllp_d_4_i_m2_i_m3_0_7__2579) + ); + defparam com_llm_llm_rx_top_llm_rx_dllp_crc_rx_dllp_d_4_i_m3_0_6_.INIT = 8'hE4; + LUT3_L com_llm_llm_rx_top_llm_rx_dllp_crc_rx_dllp_d_4_i_m3_0_6_ ( + .I0(com_llm_llm_rx_top_llm_rx_dllp_crc_fr_straddle_2614), + .I1(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_30_), + .I2(com_llm_llm_rx_top_rx_data_62_), + .LO(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_dllp_d_4_i_m3_0_6__2580) + ); + defparam com_llm_llm_rx_top_llm_rx_dllp_crc_rx_dllp_d_4_i_m3_0_5_.INIT = 8'hE4; + LUT3_L com_llm_llm_rx_top_llm_rx_dllp_crc_rx_dllp_d_4_i_m3_0_5_ ( + .I0(com_llm_llm_rx_top_llm_rx_dllp_crc_fr_straddle_2614), + .I1(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_29_), + .I2(com_llm_llm_rx_top_rx_data_61_), + .LO(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_dllp_d_4_i_m3_0_5__2581) + ); + defparam com_llm_llm_rx_top_llm_rx_dllp_crc_rx_dllp_d_4_i_m3_0_4_.INIT = 8'hE4; + LUT3_L com_llm_llm_rx_top_llm_rx_dllp_crc_rx_dllp_d_4_i_m3_0_4_ ( + .I0(com_llm_llm_rx_top_llm_rx_dllp_crc_fr_straddle_2614), + .I1(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q[28]), + .I2(com_llm_llm_rx_top_rx_data_60_), + .LO(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_dllp_d_4_i_m3_0_4__2582) + ); + defparam com_llm_llm_rx_top_llm_rx_dllp_crc_rx_dllp_d_4_i_m3_0_3_.INIT = 8'hE4; + LUT3_L com_llm_llm_rx_top_llm_rx_dllp_crc_rx_dllp_d_4_i_m3_0_3_ ( + .I0(com_llm_llm_rx_top_llm_rx_dllp_crc_fr_straddle_2614), + .I1(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_27_), + .I2(com_llm_llm_rx_top_rx_data_59_), + .LO(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_dllp_d_4_i_m3_0_3__2583) + ); + defparam com_llm_llm_rx_top_llm_rx_dllp_crc_rx_dllp_d_4_i_m3_0_2_.INIT = 8'hE4; + LUT3_L com_llm_llm_rx_top_llm_rx_dllp_crc_rx_dllp_d_4_i_m3_0_2_ ( + .I0(com_llm_llm_rx_top_llm_rx_dllp_crc_fr_straddle_2614), + .I1(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_26_), + .I2(com_llm_llm_rx_top_rx_data_58_), + .LO(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_dllp_d_4_i_m3_0_2__2584) + ); + defparam com_llm_llm_rx_top_llm_rx_dllp_crc_rx_dllp_d_4_i_m3_0_1_.INIT = 8'hE4; + LUT3_L com_llm_llm_rx_top_llm_rx_dllp_crc_rx_dllp_d_4_i_m3_0_1_ ( + .I0(com_llm_llm_rx_top_llm_rx_dllp_crc_fr_straddle_2614), + .I1(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_25_), + .I2(com_llm_llm_rx_top_rx_data_57_), + .LO(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_dllp_d_4_i_m3_0_1__2585) + ); + defparam com_llm_llm_rx_top_llm_rx_dllp_crc_rx_dllp_d_i_3_.INIT = 4'h1; + LUT1_L com_llm_llm_rx_top_llm_rx_dllp_crc_rx_dllp_d_i_3_ ( + .I0(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_dllp_d_3__2597), + .LO(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_dllp_d_i[3]) + ); + defparam com_llm_llm_rx_top_llm_rx_dllp_crc_rx_dllp_d_i_2_.INIT = 4'h1; + LUT1_L com_llm_llm_rx_top_llm_rx_dllp_crc_rx_dllp_d_i_2_ ( + .I0(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_dllp_d_2__2598), + .LO(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_dllp_d_i[2]) + ); + defparam com_llm_llm_rx_top_llm_rx_dllp_crc_rx_dllp_d_i_1_.INIT = 4'h1; + LUT1_L com_llm_llm_rx_top_llm_rx_dllp_crc_rx_dllp_d_i_1_ ( + .I0(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_dllp_d_1__2599), + .LO(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_dllp_d_i[1]) + ); + defparam com_llm_llm_rx_top_llm_rx_dllp_crc_rx_dllp_d_4_i_m3_0_31_.INIT = 8'hD8; + LUT3_L com_llm_llm_rx_top_llm_rx_dllp_crc_rx_dllp_d_4_i_m3_0_31_ ( + .I0(com_llm_llm_rx_top_llm_rx_dllp_crc_fr_straddle_2614), + .I1(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_23_), + .I2(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_55_), + .LO(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_dllp_d_4_i_m3_0_31__2586) + ); + defparam com_llm_llm_rx_top_llm_rx_dllp_crc_rx_dllp_d_4_i_m2_i_m3_0_30_.INIT = 8'hD8; + LUT3_L com_llm_llm_rx_top_llm_rx_dllp_crc_rx_dllp_d_4_i_m2_i_m3_0_30_ ( + .I0(com_llm_llm_rx_top_llm_rx_dllp_crc_fr_straddle_2614), + .I1(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_22_), + .I2(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_54_), + .LO(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_dllp_d_4_i_m2_i_m3_0_30__2587) + ); + defparam com_llm_llm_rx_top_llm_rx_dllp_crc_rx_dllp_d_4_i_m2_i_m3_0_29_.INIT = 8'hD8; + LUT3_L com_llm_llm_rx_top_llm_rx_dllp_crc_rx_dllp_d_4_i_m2_i_m3_0_29_ ( + .I0(com_llm_llm_rx_top_llm_rx_dllp_crc_fr_straddle_2614), + .I1(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_21_), + .I2(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_53_), + .LO(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_dllp_d_4_i_m2_i_m3_0_29__2588) + ); + defparam com_llm_llm_rx_top_llm_rx_dllp_crc_rx_dllp_d_4_i_m2_i_m3_0_28_.INIT = 8'hD8; + LUT3_L com_llm_llm_rx_top_llm_rx_dllp_crc_rx_dllp_d_4_i_m2_i_m3_0_28_ ( + .I0(com_llm_llm_rx_top_llm_rx_dllp_crc_fr_straddle_2614), + .I1(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_20_), + .I2(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_52_), + .LO(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_dllp_d_4_i_m2_i_m3_0_28__2589) + ); + defparam com_llm_llm_rx_top_llm_rx_dllp_crc_rx_dllp_d_4_i_m3_0_27_.INIT = 8'hD8; + LUT3_L com_llm_llm_rx_top_llm_rx_dllp_crc_rx_dllp_d_4_i_m3_0_27_ ( + .I0(com_llm_llm_rx_top_llm_rx_dllp_crc_fr_straddle_2614), + .I1(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_19_), + .I2(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_51_), + .LO(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_dllp_d_4_i_m3_0_27__2590) + ); + defparam com_llm_llm_rx_top_llm_rx_dllp_crc_rx_dllp_d_4_i_m3_0_26_.INIT = 8'hD8; + LUT3_L com_llm_llm_rx_top_llm_rx_dllp_crc_rx_dllp_d_4_i_m3_0_26_ ( + .I0(com_llm_llm_rx_top_llm_rx_dllp_crc_fr_straddle_2614), + .I1(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_18_), + .I2(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_50_), + .LO(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_dllp_d_4_i_m3_0_26__2591) + ); + defparam com_llm_llm_rx_top_llm_rx_dllp_crc_rx_dllp_d_4_i_m3_0_25_.INIT = 8'hD8; + LUT3_L com_llm_llm_rx_top_llm_rx_dllp_crc_rx_dllp_d_4_i_m3_0_25_ ( + .I0(com_llm_llm_rx_top_llm_rx_dllp_crc_fr_straddle_2614), + .I1(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_17_), + .I2(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_49_), + .LO(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_dllp_d_4_i_m3_0_25__2592) + ); + defparam com_llm_llm_rx_top_llm_rx_dllp_crc_rx_dllp_d_4_i_m3_0_24_.INIT = 8'hD8; + LUT3_L com_llm_llm_rx_top_llm_rx_dllp_crc_rx_dllp_d_4_i_m3_0_24_ ( + .I0(com_llm_llm_rx_top_llm_rx_dllp_crc_fr_straddle_2614), + .I1(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_16_), + .I2(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_48_), + .LO(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_dllp_d_4_i_m3_0_24__2593) + ); + defparam com_llm_llm_rx_top_llm_rx_dllp_crc_rx_dllp_d_4_i_m2_i_m3_0_21_.INIT = 8'hD8; + LUT3_L com_llm_llm_rx_top_llm_rx_dllp_crc_rx_dllp_d_4_i_m2_i_m3_0_21_ ( + .I0(com_llm_llm_rx_top_llm_rx_dllp_crc_fr_straddle_2614), + .I1(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_13_), + .I2(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_45_), + .LO(com_llm_llm_rx_top_rx_dllp_d_4_i_m2_i_m3_0_21_) + ); + defparam com_llm_llm_rx_top_llm_rx_dllp_crc_rx_dllp_d_4_i_m2_i_m3_0_20_.INIT = 8'hD8; + LUT3_L com_llm_llm_rx_top_llm_rx_dllp_crc_rx_dllp_d_4_i_m2_i_m3_0_20_ ( + .I0(com_llm_llm_rx_top_llm_rx_dllp_crc_fr_straddle_2614), + .I1(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_12_), + .I2(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_44_), + .LO(com_llm_llm_rx_top_rx_dllp_d_4_i_m2_i_m3_0_20_) + ); + defparam com_llm_llm_rx_top_llm_rx_dllp_crc_rx_dllp_d_4_i_m2_i_m3_0_19_.INIT = 8'hD8; + LUT3_L com_llm_llm_rx_top_llm_rx_dllp_crc_rx_dllp_d_4_i_m2_i_m3_0_19_ ( + .I0(com_llm_llm_rx_top_llm_rx_dllp_crc_fr_straddle_2614), + .I1(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_11_), + .I2(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_43_), + .LO(com_llm_llm_rx_top_rx_dllp_d_4_i_m2_i_m3_0_19_) + ); + defparam com_llm_llm_rx_top_llm_rx_dllp_crc_rx_dllp_d_4_i_m2_i_m3_0_18_.INIT = 8'hD8; + LUT3_L com_llm_llm_rx_top_llm_rx_dllp_crc_rx_dllp_d_4_i_m2_i_m3_0_18_ ( + .I0(com_llm_llm_rx_top_llm_rx_dllp_crc_fr_straddle_2614), + .I1(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_10_), + .I2(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_42_), + .LO(com_llm_llm_rx_top_rx_dllp_d_4_i_m2_i_m3_0_18_) + ); + defparam com_llm_llm_rx_top_llm_rx_dllp_crc_rx_dllp_d_i_11_.INIT = 4'h1; + LUT1_L com_llm_llm_rx_top_llm_rx_dllp_crc_rx_dllp_d_i_11_ ( + .I0(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_dllp_d_11__2602), + .LO(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_dllp_d_i[11]) + ); + defparam com_llm_llm_rx_top_llm_rx_dllp_crc_rx_dllp_d_i_10_.INIT = 4'h1; + LUT1_L com_llm_llm_rx_top_llm_rx_dllp_crc_rx_dllp_d_i_10_ ( + .I0(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_dllp_d_10__2603), + .LO(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_dllp_d_i[10]) + ); + defparam com_llm_llm_rx_top_llm_rx_dllp_crc_rx_dllp_d_i_9_.INIT = 4'h1; + LUT1_L com_llm_llm_rx_top_llm_rx_dllp_crc_rx_dllp_d_i_9_ ( + .I0(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_dllp_d_9__2604), + .LO(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_dllp_d_i[9]) + ); + defparam com_llm_llm_rx_top_llm_rx_dllp_crc_rx_dllp_d_i_8_.INIT = 4'h1; + LUT1_L com_llm_llm_rx_top_llm_rx_dllp_crc_rx_dllp_d_i_8_ ( + .I0(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_dllp_d_8__2605), + .LO(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_dllp_d_i[8]) + ); + defparam com_llm_llm_rx_top_llm_rx_dllp_crc_rx_dllp_d_i_7_.INIT = 4'h1; + LUT1_L com_llm_llm_rx_top_llm_rx_dllp_crc_rx_dllp_d_i_7_ ( + .I0(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_dllp_d_7__2606), + .LO(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_dllp_d_i[7]) + ); + defparam com_llm_llm_rx_top_llm_rx_dllp_crc_rx_dllp_d_i_6_.INIT = 4'h1; + LUT1_L com_llm_llm_rx_top_llm_rx_dllp_crc_rx_dllp_d_i_6_ ( + .I0(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_dllp_d_6__2594), + .LO(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_dllp_d_i[6]) + ); + defparam com_llm_llm_rx_top_llm_rx_dllp_crc_rx_dllp_d_i_5_.INIT = 4'h1; + LUT1_L com_llm_llm_rx_top_llm_rx_dllp_crc_rx_dllp_d_i_5_ ( + .I0(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_dllp_d_5__2595), + .LO(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_dllp_d_i[5]) + ); + defparam com_llm_llm_rx_top_llm_rx_dllp_crc_rx_dllp_d_i_4_.INIT = 4'h1; + LUT1_L com_llm_llm_rx_top_llm_rx_dllp_crc_rx_dllp_d_i_4_ ( + .I0(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_dllp_d_4__2596), + .LO(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_dllp_d_i[4]) + ); + defparam com_llm_llm_rx_top_llm_rx_dllp_crc_crc16_ori_4_i_m3_0_8_.INIT = 8'hE4; + LUT3_L com_llm_llm_rx_top_llm_rx_dllp_crc_crc16_ori_4_i_m3_0_8_ ( + .I0(com_llm_llm_rx_top_llm_rx_dllp_crc_fr_straddle_2614), + .I1(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_16_), + .I2(com_llm_llm_rx_top_rx_data_48_), + .LO(com_llm_llm_rx_top_llm_rx_dllp_crc_crc16_ori_4_i_m3_0[8]) + ); + defparam com_llm_llm_rx_top_llm_rx_dllp_crc_crc16_ori_4_i_m3_0_7_.INIT = 8'hE4; + LUT3_L com_llm_llm_rx_top_llm_rx_dllp_crc_crc16_ori_4_i_m3_0_7_ ( + .I0(com_llm_llm_rx_top_llm_rx_dllp_crc_fr_straddle_2614), + .I1(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_15_), + .I2(com_llm_llm_rx_top_rx_data_47_), + .LO(com_llm_llm_rx_top_llm_rx_dllp_crc_crc16_ori_4_i_m3_0[7]) + ); + defparam com_llm_llm_rx_top_llm_rx_dllp_crc_crc16_ori_4_i_m3_0_6_.INIT = 8'hE4; + LUT3_L com_llm_llm_rx_top_llm_rx_dllp_crc_crc16_ori_4_i_m3_0_6_ ( + .I0(com_llm_llm_rx_top_llm_rx_dllp_crc_fr_straddle_2614), + .I1(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_14_), + .I2(com_llm_llm_rx_top_rx_data_46_), + .LO(com_llm_llm_rx_top_llm_rx_dllp_crc_crc16_ori_4_i_m3_0[6]) + ); + defparam com_llm_llm_rx_top_llm_rx_dllp_crc_crc16_ori_4_i_m3_0_5_.INIT = 8'hE4; + LUT3_L com_llm_llm_rx_top_llm_rx_dllp_crc_crc16_ori_4_i_m3_0_5_ ( + .I0(com_llm_llm_rx_top_llm_rx_dllp_crc_fr_straddle_2614), + .I1(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_13_), + .I2(com_llm_llm_rx_top_rx_data_45_), + .LO(com_llm_llm_rx_top_llm_rx_dllp_crc_crc16_ori_4_i_m3_0[5]) + ); + defparam com_llm_llm_rx_top_llm_rx_dllp_crc_crc16_ori_4_i_m3_0_4_.INIT = 8'hE4; + LUT3_L com_llm_llm_rx_top_llm_rx_dllp_crc_crc16_ori_4_i_m3_0_4_ ( + .I0(com_llm_llm_rx_top_llm_rx_dllp_crc_fr_straddle_2614), + .I1(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_12_), + .I2(com_llm_llm_rx_top_rx_data_44_), + .LO(com_llm_llm_rx_top_llm_rx_dllp_crc_crc16_ori_4_i_m3_0[4]) + ); + defparam com_llm_llm_rx_top_llm_rx_dllp_crc_crc16_ori_4_i_m3_0_3_.INIT = 8'hE4; + LUT3_L com_llm_llm_rx_top_llm_rx_dllp_crc_crc16_ori_4_i_m3_0_3_ ( + .I0(com_llm_llm_rx_top_llm_rx_dllp_crc_fr_straddle_2614), + .I1(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_11_), + .I2(com_llm_llm_rx_top_rx_data_43_), + .LO(com_llm_llm_rx_top_llm_rx_dllp_crc_crc16_ori_4_i_m3_0[3]) + ); + defparam com_llm_llm_rx_top_llm_rx_dllp_crc_crc16_ori_4_i_m3_0_2_.INIT = 8'hE4; + LUT3_L com_llm_llm_rx_top_llm_rx_dllp_crc_crc16_ori_4_i_m3_0_2_ ( + .I0(com_llm_llm_rx_top_llm_rx_dllp_crc_fr_straddle_2614), + .I1(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_10_), + .I2(com_llm_llm_rx_top_rx_data_42_), + .LO(com_llm_llm_rx_top_llm_rx_dllp_crc_crc16_ori_4_i_m3_0[2]) + ); + defparam com_llm_llm_rx_top_llm_rx_dllp_crc_crc16_ori_4_i_m3_0_1_.INIT = 8'hE4; + LUT3_L com_llm_llm_rx_top_llm_rx_dllp_crc_crc16_ori_4_i_m3_0_1_ ( + .I0(com_llm_llm_rx_top_llm_rx_dllp_crc_fr_straddle_2614), + .I1(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_9_), + .I2(com_llm_llm_rx_top_rx_data_41_), + .LO(com_llm_llm_rx_top_llm_rx_dllp_crc_crc16_ori_4_i_m3_0[1]) + ); + defparam com_llm_llm_rx_top_llm_rx_dllp_crc_crc16_ori_4_i_m3_0_0_.INIT = 8'hE4; + LUT3_L com_llm_llm_rx_top_llm_rx_dllp_crc_crc16_ori_4_i_m3_0_0_ ( + .I0(com_llm_llm_rx_top_llm_rx_dllp_crc_fr_straddle_2614), + .I1(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_8_), + .I2(com_llm_llm_rx_top_rx_data_40_), + .LO(com_llm_llm_rx_top_llm_rx_dllp_crc_crc16_ori_4_i_m3_0[0]) + ); + defparam com_llm_llm_rx_top_llm_rx_dllp_crc_crc16_ori_4_i_m3_0_15_.INIT = 8'hE4; + LUT3_L com_llm_llm_rx_top_llm_rx_dllp_crc_crc16_ori_4_i_m3_0_15_ ( + .I0(com_llm_llm_rx_top_llm_rx_dllp_crc_fr_straddle_2614), + .I1(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_23_), + .I2(com_llm_llm_rx_top_rx_data_55_), + .LO(com_llm_llm_rx_top_llm_rx_dllp_crc_crc16_ori_4_i_m3_0[15]) + ); + defparam com_llm_llm_rx_top_llm_rx_dllp_crc_crc16_ori_4_i_m3_0_14_.INIT = 8'hE4; + LUT3_L com_llm_llm_rx_top_llm_rx_dllp_crc_crc16_ori_4_i_m3_0_14_ ( + .I0(com_llm_llm_rx_top_llm_rx_dllp_crc_fr_straddle_2614), + .I1(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_22_), + .I2(com_llm_llm_rx_top_rx_data_54_), + .LO(com_llm_llm_rx_top_llm_rx_dllp_crc_crc16_ori_4_i_m3_0[14]) + ); + defparam com_llm_llm_rx_top_llm_rx_dllp_crc_crc16_ori_4_i_m3_0_13_.INIT = 8'hE4; + LUT3_L com_llm_llm_rx_top_llm_rx_dllp_crc_crc16_ori_4_i_m3_0_13_ ( + .I0(com_llm_llm_rx_top_llm_rx_dllp_crc_fr_straddle_2614), + .I1(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_21_), + .I2(com_llm_llm_rx_top_rx_data_53_), + .LO(com_llm_llm_rx_top_llm_rx_dllp_crc_crc16_ori_4_i_m3_0[13]) + ); + defparam com_llm_llm_rx_top_llm_rx_dllp_crc_crc16_ori_4_i_m3_0_12_.INIT = 8'hE4; + LUT3_L com_llm_llm_rx_top_llm_rx_dllp_crc_crc16_ori_4_i_m3_0_12_ ( + .I0(com_llm_llm_rx_top_llm_rx_dllp_crc_fr_straddle_2614), + .I1(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_20_), + .I2(com_llm_llm_rx_top_rx_data_52_), + .LO(com_llm_llm_rx_top_llm_rx_dllp_crc_crc16_ori_4_i_m3_0[12]) + ); + defparam com_llm_llm_rx_top_llm_rx_dllp_crc_crc16_ori_4_i_m3_0_11_.INIT = 8'hE4; + LUT3_L com_llm_llm_rx_top_llm_rx_dllp_crc_crc16_ori_4_i_m3_0_11_ ( + .I0(com_llm_llm_rx_top_llm_rx_dllp_crc_fr_straddle_2614), + .I1(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_19_), + .I2(com_llm_llm_rx_top_rx_data_51_), + .LO(com_llm_llm_rx_top_llm_rx_dllp_crc_crc16_ori_4_i_m3_0[11]) + ); + defparam com_llm_llm_rx_top_llm_rx_dllp_crc_crc16_ori_4_i_m3_0_10_.INIT = 8'hE4; + LUT3_L com_llm_llm_rx_top_llm_rx_dllp_crc_crc16_ori_4_i_m3_0_10_ ( + .I0(com_llm_llm_rx_top_llm_rx_dllp_crc_fr_straddle_2614), + .I1(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_18_), + .I2(com_llm_llm_rx_top_rx_data_50_), + .LO(com_llm_llm_rx_top_llm_rx_dllp_crc_crc16_ori_4_i_m3_0[10]) + ); + defparam com_llm_llm_rx_top_llm_rx_dllp_crc_crc16_ori_4_i_m3_0_9_.INIT = 8'hE4; + LUT3_L com_llm_llm_rx_top_llm_rx_dllp_crc_crc16_ori_4_i_m3_0_9_ ( + .I0(com_llm_llm_rx_top_llm_rx_dllp_crc_fr_straddle_2614), + .I1(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_17_), + .I2(com_llm_llm_rx_top_rx_data_49_), + .LO(com_llm_llm_rx_top_llm_rx_dllp_crc_crc16_ori_4_i_m3_0[9]) + ); + MUXCY com_llm_llm_rx_top_llm_rx_dllp_crc_crc16_ok_0_I_37 ( + .CI(com_llm_llm_rx_top_llm_rx_dllp_crc_data_tmp[6]), + .DI(com_llm_llm_rx_top_llm_rx_dllp_crc_GND_2568), + .O(com_llm_llm_rx_top_llm_rx_dllp_crc_crc16_ok), + .S(com_llm_llm_rx_top_llm_rx_dllp_crc_N_27) + ); + FD com_llm_llm_rx_top_llm_rx_dllp_crc_fr_straddle_q ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_dllp_crc_fr_straddle_2614), + .Q(com_llm_llm_rx_top_llm_rx_dllp_crc_fr_straddle_q_2569) + ); + FDC com_llm_llm_rx_top_llm_rx_dllp_crc_reg_dllp_qq ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_dllp_crc_reg_dllp_q_2572), + .Q(com_llm_llm_rx_top_llm_rx_dllp_crc_reg_dllp_qq_2570), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_dllp_crc_str_dllp_q ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_dllp_crc_str_dllp), + .Q(com_llm_llm_rx_top_llm_rx_dllp_crc_str_dllp_q_2571), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_dllp_crc_reg_dllp_q ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_dllp_crc_reg_dllp), + .Q(com_llm_llm_rx_top_llm_rx_dllp_crc_reg_dllp_q_2572), + .CLR(plm_link_up_i) + ); + FDP com_llm_llm_rx_top_llm_rx_dllp_crc_RX_DLLP_CRC_ERR_N ( + .PRE(plm_link_up_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_dllp_crc_N_27234_i_2573), + .Q(com_cmml_bad_dllp_err_n) + ); + FDC com_llm_llm_rx_top_llm_rx_dllp_crc_RX_DLLP_VLD ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_dllp_crc_RX_DLLP_VLD_5), + .Q(com_llm_rx_dllp_vld), + .CLR(plm_link_up_i) + ); + FD com_llm_llm_rx_top_llm_rx_dllp_crc_rx_dllp_d_0_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_dllp_d_4_i_m3_0_0__2574), + .Q(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_dllp_d[0]) + ); + FD com_llm_llm_rx_top_llm_rx_dllp_crc_rx_dllp_d_11_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_dllp_d_4_i_m3_0_11__2575), + .Q(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_dllp_d_11__2602) + ); + FD com_llm_llm_rx_top_llm_rx_dllp_crc_rx_dllp_d_10_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_dllp_d_4_i_m3_0_10__2576), + .Q(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_dllp_d_10__2603) + ); + FD com_llm_llm_rx_top_llm_rx_dllp_crc_rx_dllp_d_9_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_dllp_d_4_i_m3_0_9__2577), + .Q(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_dllp_d_9__2604) + ); + FD com_llm_llm_rx_top_llm_rx_dllp_crc_rx_dllp_d_8_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_dllp_d_4_i_m3_0_8__2578), + .Q(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_dllp_d_8__2605) + ); + FD com_llm_llm_rx_top_llm_rx_dllp_crc_rx_dllp_d_7_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_dllp_d_4_i_m2_i_m3_0_7__2579), + .Q(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_dllp_d_7__2606) + ); + FD com_llm_llm_rx_top_llm_rx_dllp_crc_rx_dllp_d_6_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_dllp_d_4_i_m3_0_6__2580), + .Q(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_dllp_d_6__2594) + ); + FD com_llm_llm_rx_top_llm_rx_dllp_crc_rx_dllp_d_5_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_dllp_d_4_i_m3_0_5__2581), + .Q(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_dllp_d_5__2595) + ); + FD com_llm_llm_rx_top_llm_rx_dllp_crc_rx_dllp_d_4_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_dllp_d_4_i_m3_0_4__2582), + .Q(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_dllp_d_4__2596) + ); + FD com_llm_llm_rx_top_llm_rx_dllp_crc_rx_dllp_d_3_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_dllp_d_4_i_m3_0_3__2583), + .Q(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_dllp_d_3__2597) + ); + FD com_llm_llm_rx_top_llm_rx_dllp_crc_rx_dllp_d_2_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_dllp_d_4_i_m3_0_2__2584), + .Q(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_dllp_d_2__2598) + ); + FD com_llm_llm_rx_top_llm_rx_dllp_crc_rx_dllp_d_1_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_dllp_d_4_i_m3_0_1__2585), + .Q(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_dllp_d_1__2599) + ); + FD com_llm_llm_rx_top_llm_rx_dllp_crc_RX_DLLP_LOW_M1_1_3_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_dllp_crc_RX_DLLP_LOW_M1_2[3]), + .Q(com_llm_reg_rx_dllp_tsn_m1[3]) + ); + FD com_llm_llm_rx_top_llm_rx_dllp_crc_RX_DLLP_LOW_M1_1_2_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_dllp_crc_RX_DLLP_LOW_M1_2[2]), + .Q(com_llm_reg_rx_dllp_tsn_m1[2]) + ); + FD com_llm_llm_rx_top_llm_rx_dllp_crc_RX_DLLP_LOW_M1_1_1_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_dllp_crc_RX_DLLP_LOW_M1_2[1]), + .Q(com_llm_reg_rx_dllp_tsn_m1[1]) + ); + FD com_llm_llm_rx_top_llm_rx_dllp_crc_rx_dllp_d_31_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_dllp_d_4_i_m3_0_31__2586), + .Q(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_dllp_d_31__2607) + ); + FD com_llm_llm_rx_top_llm_rx_dllp_crc_rx_dllp_d_30_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_dllp_d_4_i_m2_i_m3_0_30__2587), + .Q(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_dllp_d_30__2608) + ); + FD com_llm_llm_rx_top_llm_rx_dllp_crc_rx_dllp_d_29_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_dllp_d_4_i_m2_i_m3_0_29__2588), + .Q(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_dllp_d_29__2609) + ); + FD com_llm_llm_rx_top_llm_rx_dllp_crc_rx_dllp_d_28_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_dllp_d_4_i_m2_i_m3_0_28__2589), + .Q(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_dllp_d_28__2610) + ); + FD com_llm_llm_rx_top_llm_rx_dllp_crc_rx_dllp_d_27_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_dllp_d_4_i_m3_0_27__2590), + .Q(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_dllp_d_27__2611) + ); + FD com_llm_llm_rx_top_llm_rx_dllp_crc_rx_dllp_d_26_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_dllp_d_4_i_m3_0_26__2591), + .Q(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_dllp_d_26__2612) + ); + FD com_llm_llm_rx_top_llm_rx_dllp_crc_rx_dllp_d_25_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_dllp_d_4_i_m3_0_25__2592), + .Q(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_dllp_d_25__2600) + ); + FD com_llm_llm_rx_top_llm_rx_dllp_crc_rx_dllp_d_24_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_dllp_d_4_i_m3_0_24__2593), + .Q(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_dllp_d_24__2601) + ); + FD com_llm_llm_rx_top_llm_rx_dllp_crc_RX_DLLP_6_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_dllp_d_6__2594), + .Q(com_llm_reg_rx_dllp_tsn[6]) + ); + FD com_llm_llm_rx_top_llm_rx_dllp_crc_RX_DLLP_5_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_dllp_d_5__2595), + .Q(com_llm_reg_rx_dllp_tsn[5]) + ); + FD com_llm_llm_rx_top_llm_rx_dllp_crc_RX_DLLP_4_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_dllp_d_4__2596), + .Q(com_llm_reg_rx_dllp_tsn[4]) + ); + FD com_llm_llm_rx_top_llm_rx_dllp_crc_RX_DLLP_3_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_dllp_d_3__2597), + .Q(com_llm_reg_rx_dllp_tsn[3]) + ); + FD com_llm_llm_rx_top_llm_rx_dllp_crc_RX_DLLP_2_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_dllp_d_2__2598), + .Q(com_llm_reg_rx_dllp_tsn[2]) + ); + FD com_llm_llm_rx_top_llm_rx_dllp_crc_RX_DLLP_1_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_dllp_d_1__2599), + .Q(com_llm_reg_rx_dllp_tsn[1]) + ); + FD com_llm_llm_rx_top_llm_rx_dllp_crc_RX_DLLP_0_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_dllp_d[0]), + .Q(com_llm_reg_rx_dllp_tsn[0]) + ); + FD com_llm_llm_rx_top_llm_rx_dllp_crc_RX_DLLP_LOW_M1_1_11_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_dllp_crc_RX_DLLP_LOW_M1_2[11]), + .Q(com_llm_reg_rx_dllp_tsn_m1[11]) + ); + FD com_llm_llm_rx_top_llm_rx_dllp_crc_RX_DLLP_LOW_M1_1_10_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_dllp_crc_RX_DLLP_LOW_M1_2[10]), + .Q(com_llm_reg_rx_dllp_tsn_m1[10]) + ); + FD com_llm_llm_rx_top_llm_rx_dllp_crc_RX_DLLP_LOW_M1_1_9_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_dllp_crc_RX_DLLP_LOW_M1_2[9]), + .Q(com_llm_reg_rx_dllp_tsn_m1[9]) + ); + FD com_llm_llm_rx_top_llm_rx_dllp_crc_RX_DLLP_LOW_M1_1_8_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_dllp_crc_RX_DLLP_LOW_M1_2[8]), + .Q(com_llm_reg_rx_dllp_tsn_m1[8]) + ); + FD com_llm_llm_rx_top_llm_rx_dllp_crc_RX_DLLP_LOW_M1_1_7_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_dllp_crc_RX_DLLP_LOW_M1_2[7]), + .Q(com_llm_reg_rx_dllp_tsn_m1[7]) + ); + FD com_llm_llm_rx_top_llm_rx_dllp_crc_RX_DLLP_LOW_M1_1_6_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_dllp_crc_RX_DLLP_LOW_M1_2[6]), + .Q(com_llm_reg_rx_dllp_tsn_m1[6]) + ); + FD com_llm_llm_rx_top_llm_rx_dllp_crc_RX_DLLP_LOW_M1_1_5_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_dllp_crc_RX_DLLP_LOW_M1_2[5]), + .Q(com_llm_reg_rx_dllp_tsn_m1[5]) + ); + FD com_llm_llm_rx_top_llm_rx_dllp_crc_RX_DLLP_LOW_M1_1_4_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_dllp_crc_RX_DLLP_LOW_M1_2[4]), + .Q(com_llm_reg_rx_dllp_tsn_m1[4]) + ); + FD com_llm_llm_rx_top_llm_rx_dllp_crc_RX_DLLP_25_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_dllp_d_25__2600), + .Q(com_llm_llm_rx_top_rx_dllp[25]) + ); + FD com_llm_llm_rx_top_llm_rx_dllp_crc_RX_DLLP_24_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_dllp_d_24__2601), + .Q(com_llm_llm_rx_top_rx_dllp[24]) + ); + FD com_llm_llm_rx_top_llm_rx_dllp_crc_RX_DLLP_11_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_dllp_d_11__2602), + .Q(com_llm_reg_rx_dllp_tsn[11]) + ); + FD com_llm_llm_rx_top_llm_rx_dllp_crc_RX_DLLP_10_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_dllp_d_10__2603), + .Q(com_llm_reg_rx_dllp_tsn[10]) + ); + FD com_llm_llm_rx_top_llm_rx_dllp_crc_RX_DLLP_9_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_dllp_d_9__2604), + .Q(com_llm_reg_rx_dllp_tsn[9]) + ); + FD com_llm_llm_rx_top_llm_rx_dllp_crc_RX_DLLP_8_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_dllp_d_8__2605), + .Q(com_llm_reg_rx_dllp_tsn[8]) + ); + FD com_llm_llm_rx_top_llm_rx_dllp_crc_RX_DLLP_7_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_dllp_d_7__2606), + .Q(com_llm_reg_rx_dllp_tsn[7]) + ); + FD com_llm_llm_rx_top_llm_rx_dllp_crc_crc16_d32_nst_8_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_dllp_crc_new_c32_nst_i_8_), + .Q(com_llm_llm_rx_top_llm_rx_dllp_crc_crc16_d32_nst[8]) + ); + FD com_llm_llm_rx_top_llm_rx_dllp_crc_crc16_d32_nst_7_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_dllp_crc_new_c32_1_i_0_7_), + .Q(com_llm_llm_rx_top_llm_rx_dllp_crc_crc16_d32_nst[7]) + ); + FD com_llm_llm_rx_top_llm_rx_dllp_crc_crc16_d32_nst_6_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_dllp_crc_new_c32_nst_i_6_), + .Q(com_llm_llm_rx_top_llm_rx_dllp_crc_crc16_d32_nst[6]) + ); + FD com_llm_llm_rx_top_llm_rx_dllp_crc_crc16_d32_nst_5_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_dllp_crc_new_c32_1_i_0_5_), + .Q(com_llm_llm_rx_top_llm_rx_dllp_crc_crc16_d32_nst[5]) + ); + FD com_llm_llm_rx_top_llm_rx_dllp_crc_crc16_d32_nst_4_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_dllp_crc_new_c32_1_i_0_4_), + .Q(com_llm_llm_rx_top_llm_rx_dllp_crc_crc16_d32_nst[4]) + ); + FD com_llm_llm_rx_top_llm_rx_dllp_crc_crc16_d32_nst_3_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_dllp_crc_new_c32_1_i_0_3_), + .Q(com_llm_llm_rx_top_llm_rx_dllp_crc_crc16_d32_nst[3]) + ); + FD com_llm_llm_rx_top_llm_rx_dllp_crc_crc16_d32_nst_2_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_dllp_crc_new_c32_nst_i_2_), + .Q(com_llm_llm_rx_top_llm_rx_dllp_crc_crc16_d32_nst[2]) + ); + FD com_llm_llm_rx_top_llm_rx_dllp_crc_crc16_d32_nst_1_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_dllp_crc_new_c32_nst_i_1_), + .Q(com_llm_llm_rx_top_llm_rx_dllp_crc_crc16_d32_nst[1]) + ); + FD com_llm_llm_rx_top_llm_rx_dllp_crc_crc16_d32_nst_0_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_dllp_crc_new_c32_1_i_0_0_), + .Q(com_llm_llm_rx_top_llm_rx_dllp_crc_crc16_d32_nst[0]) + ); + FD com_llm_llm_rx_top_llm_rx_dllp_crc_RX_DLLP_31_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_dllp_d_31__2607), + .Q(com_llm_rx_dllp[31]) + ); + FD com_llm_llm_rx_top_llm_rx_dllp_crc_RX_DLLP_30_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_dllp_d_30__2608), + .Q(com_llm_rx_dllp[30]) + ); + FD com_llm_llm_rx_top_llm_rx_dllp_crc_RX_DLLP_29_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_dllp_d_29__2609), + .Q(com_llm_rx_dllp[29]) + ); + FD com_llm_llm_rx_top_llm_rx_dllp_crc_RX_DLLP_28_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_dllp_d_28__2610), + .Q(com_llm_llm_rx_top_rx_dllp[28]) + ); + FD com_llm_llm_rx_top_llm_rx_dllp_crc_RX_DLLP_27_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_dllp_d_27__2611), + .Q(com_llm_llm_rx_top_rx_dllp[27]) + ); + FD com_llm_llm_rx_top_llm_rx_dllp_crc_RX_DLLP_26_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_dllp_d_26__2612), + .Q(com_llm_llm_rx_top_rx_dllp[26]) + ); + FD com_llm_llm_rx_top_llm_rx_dllp_crc_crc16_d32_st_7_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_dllp_crc_new_c32_1_i_7_), + .Q(com_llm_llm_rx_top_llm_rx_dllp_crc_crc16_d32_st[7]) + ); + FD com_llm_llm_rx_top_llm_rx_dllp_crc_crc16_d32_st_6_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_dllp_crc_new_c32_st_i_6_), + .Q(com_llm_llm_rx_top_llm_rx_dllp_crc_crc16_d32_st[6]) + ); + FD com_llm_llm_rx_top_llm_rx_dllp_crc_crc16_d32_st_5_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_dllp_crc_new_c32_1_i_5_), + .Q(com_llm_llm_rx_top_llm_rx_dllp_crc_crc16_d32_st[5]) + ); + FD com_llm_llm_rx_top_llm_rx_dllp_crc_crc16_d32_st_4_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_dllp_crc_new_c32_1_i_4_), + .Q(com_llm_llm_rx_top_llm_rx_dllp_crc_crc16_d32_st[4]) + ); + FD com_llm_llm_rx_top_llm_rx_dllp_crc_crc16_d32_st_3_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_dllp_crc_new_c32_1_i_3_), + .Q(com_llm_llm_rx_top_llm_rx_dllp_crc_crc16_d32_st[3]) + ); + FD com_llm_llm_rx_top_llm_rx_dllp_crc_crc16_d32_st_2_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_dllp_crc_new_c32_st_i_2_), + .Q(com_llm_llm_rx_top_llm_rx_dllp_crc_crc16_d32_st[2]) + ); + FD com_llm_llm_rx_top_llm_rx_dllp_crc_crc16_d32_st_1_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_dllp_crc_new_c32_st_i_1_), + .Q(com_llm_llm_rx_top_llm_rx_dllp_crc_crc16_d32_st[1]) + ); + FD com_llm_llm_rx_top_llm_rx_dllp_crc_crc16_d32_st_0_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_dllp_crc_new_c32_1_i_0_), + .Q(com_llm_llm_rx_top_llm_rx_dllp_crc_crc16_d32_st[0]) + ); + FD com_llm_llm_rx_top_llm_rx_dllp_crc_crc16_d32_nst_15_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_dllp_crc_new_c32_nst_i_15_), + .Q(com_llm_llm_rx_top_llm_rx_dllp_crc_crc16_d32_nst[15]) + ); + FD com_llm_llm_rx_top_llm_rx_dllp_crc_crc16_d32_nst_14_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_dllp_crc_new_c32_nst_i_14_), + .Q(com_llm_llm_rx_top_llm_rx_dllp_crc_crc16_d32_nst[14]) + ); + FD com_llm_llm_rx_top_llm_rx_dllp_crc_crc16_d32_nst_13_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_dllp_crc_new_c32_1_i_0_13_), + .Q(com_llm_llm_rx_top_llm_rx_dllp_crc_crc16_d32_nst[13]) + ); + FD com_llm_llm_rx_top_llm_rx_dllp_crc_crc16_d32_nst_12_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_dllp_crc_new_c32_1_i_0_12_), + .Q(com_llm_llm_rx_top_llm_rx_dllp_crc_crc16_d32_nst[12]) + ); + FD com_llm_llm_rx_top_llm_rx_dllp_crc_crc16_d32_nst_11_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_dllp_crc_new_c32_nst_i_11_), + .Q(com_llm_llm_rx_top_llm_rx_dllp_crc_crc16_d32_nst[11]) + ); + FD com_llm_llm_rx_top_llm_rx_dllp_crc_crc16_d32_nst_10_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_dllp_crc_new_c32_nst_i_10_), + .Q(com_llm_llm_rx_top_llm_rx_dllp_crc_crc16_d32_nst[10]) + ); + FD com_llm_llm_rx_top_llm_rx_dllp_crc_crc16_d32_nst_9_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_dllp_crc_new_c32_1_i_0_9_), + .Q(com_llm_llm_rx_top_llm_rx_dllp_crc_crc16_d32_nst[9]) + ); + FD com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_bit_swap_q_6_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_rx_data_1_), + .Q(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_1_) + ); + FD com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_bit_swap_q_5_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_rx_data_2_), + .Q(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_2_) + ); + FD com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_bit_swap_q_4_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_rx_data_3_), + .Q(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_3_) + ); + FD com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_bit_swap_q_3_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_rx_data_4_), + .Q(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_4_) + ); + FD com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_bit_swap_q_2_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_rx_data_5_), + .Q(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_5_) + ); + FD com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_bit_swap_q_1_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_rx_data_6_), + .Q(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_6_) + ); + FD com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_bit_swap_q_0_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_rx_data_7_), + .Q(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_7_) + ); + FD com_llm_llm_rx_top_llm_rx_dllp_crc_crc16_d32_st_15_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_dllp_crc_new_c32_st_i_15_), + .Q(com_llm_llm_rx_top_llm_rx_dllp_crc_crc16_d32_st[15]) + ); + FD com_llm_llm_rx_top_llm_rx_dllp_crc_crc16_d32_st_14_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_dllp_crc_new_c32_st_i_14_), + .Q(com_llm_llm_rx_top_llm_rx_dllp_crc_crc16_d32_st[14]) + ); + FD com_llm_llm_rx_top_llm_rx_dllp_crc_crc16_d32_st_13_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_dllp_crc_new_c32_1_i_13_), + .Q(com_llm_llm_rx_top_llm_rx_dllp_crc_crc16_d32_st[13]) + ); + FD com_llm_llm_rx_top_llm_rx_dllp_crc_crc16_d32_st_12_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_dllp_crc_new_c32_1_i_12_), + .Q(com_llm_llm_rx_top_llm_rx_dllp_crc_crc16_d32_st[12]) + ); + FD com_llm_llm_rx_top_llm_rx_dllp_crc_crc16_d32_st_11_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_dllp_crc_new_c32_st_i_11_), + .Q(com_llm_llm_rx_top_llm_rx_dllp_crc_crc16_d32_st[11]) + ); + FD com_llm_llm_rx_top_llm_rx_dllp_crc_crc16_d32_st_10_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_dllp_crc_new_c32_st_i_10_), + .Q(com_llm_llm_rx_top_llm_rx_dllp_crc_crc16_d32_st[10]) + ); + FD com_llm_llm_rx_top_llm_rx_dllp_crc_crc16_d32_st_9_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_dllp_crc_new_c32_1_i_9_), + .Q(com_llm_llm_rx_top_llm_rx_dllp_crc_crc16_d32_st[9]) + ); + FD com_llm_llm_rx_top_llm_rx_dllp_crc_crc16_d32_st_8_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_dllp_crc_new_c32_st_i_8_), + .Q(com_llm_llm_rx_top_llm_rx_dllp_crc_crc16_d32_st[8]) + ); + FD com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_bit_swap_q_21_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_rx_data_18_), + .Q(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_18_) + ); + FD com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_bit_swap_q_20_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_rx_data_19_), + .Q(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_19_) + ); + FD com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_bit_swap_q_19_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_rx_data_20_), + .Q(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_20_) + ); + FD com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_bit_swap_q_18_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_rx_data_21_), + .Q(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_21_) + ); + FD com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_bit_swap_q_17_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_rx_data_22_), + .Q(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_22_) + ); + FD com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_bit_swap_q_16_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_rx_data_23_), + .Q(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_23_) + ); + FD com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_bit_swap_q_15_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_rx_data_8_), + .Q(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_8_) + ); + FD com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_bit_swap_q_14_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_rx_data_9_), + .Q(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_9_) + ); + FD com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_bit_swap_q_13_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_rx_data_10_), + .Q(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_10_) + ); + FD com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_bit_swap_q_12_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_rx_data_11_), + .Q(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_11_) + ); + FD com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_bit_swap_q_11_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_rx_data_12_), + .Q(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_12_) + ); + FD com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_bit_swap_q_10_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_rx_data_13_), + .Q(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_13_) + ); + FD com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_bit_swap_q_9_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_rx_data_14_), + .Q(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_14_) + ); + FD com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_bit_swap_q_8_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_rx_data_15_), + .Q(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_15_) + ); + FD com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_bit_swap_q_7_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_rx_data_0_), + .Q(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_0_) + ); + FD com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_bit_swap_q_36_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_rx_data_35_), + .Q(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_35_) + ); + FD com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_bit_swap_q_35_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_rx_data_36_), + .Q(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_36_) + ); + FD com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_bit_swap_q_34_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_rx_data_37_), + .Q(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_37_) + ); + FD com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_bit_swap_q_33_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_rx_data_38_), + .Q(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_38_) + ); + FD com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_bit_swap_q_32_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_rx_data_39_), + .Q(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_39_) + ); + FD com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_bit_swap_q_31_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_rx_data_24_), + .Q(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_24_) + ); + FD com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_bit_swap_q_30_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_rx_data_25_), + .Q(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_25_) + ); + FD com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_bit_swap_q_29_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_rx_data_26_), + .Q(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_26_) + ); + FD com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_bit_swap_q_28_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_rx_data_27_), + .Q(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_27_) + ); + FD com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_bit_swap_q_27_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_rx_data_28_), + .Q(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q[28]) + ); + FD com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_bit_swap_q_26_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_rx_data_29_), + .Q(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_29_) + ); + FD com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_bit_swap_q_25_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_rx_data_30_), + .Q(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_30_) + ); + FD com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_bit_swap_q_24_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_rx_data_31_), + .Q(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_31_) + ); + FD com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_bit_swap_q_23_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_rx_data_16_), + .Q(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_16_) + ); + FD com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_bit_swap_q_22_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_rx_data_17_), + .Q(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_17_) + ); + FD com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_bit_swap_q_51_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_rx_data_52_), + .Q(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_52_) + ); + FD com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_bit_swap_q_50_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_rx_data_53_), + .Q(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_53_) + ); + FD com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_bit_swap_q_49_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_rx_data_54_), + .Q(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_54_) + ); + FD com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_bit_swap_q_48_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_rx_data_55_), + .Q(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_55_) + ); + FD com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_bit_swap_q_47_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_rx_data_40_), + .Q(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_40_) + ); + FD com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_bit_swap_q_46_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_rx_data_41_), + .Q(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_41_) + ); + FD com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_bit_swap_q_45_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_rx_data_42_), + .Q(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_42_) + ); + FD com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_bit_swap_q_44_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_rx_data_43_), + .Q(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_43_) + ); + FD com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_bit_swap_q_43_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_rx_data_44_), + .Q(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_44_) + ); + FD com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_bit_swap_q_42_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_rx_data_45_), + .Q(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_45_) + ); + FD com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_bit_swap_q_41_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_rx_data_46_), + .Q(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_46_) + ); + FD com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_bit_swap_q_40_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_rx_data_47_), + .Q(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_47_) + ); + FD com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_bit_swap_q_39_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_rx_data_32_), + .Q(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_32_) + ); + FD com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_bit_swap_q_38_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_rx_data_33_), + .Q(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_33_) + ); + FD com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_bit_swap_q_37_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_rx_data_34_), + .Q(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_34_) + ); + FD com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_bit_swap_q_55_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_rx_data_48_), + .Q(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_48_) + ); + FD com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_bit_swap_q_54_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_rx_data_49_), + .Q(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_49_) + ); + FD com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_bit_swap_q_53_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_rx_data_50_), + .Q(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_50_) + ); + FD com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_bit_swap_q_52_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_rx_data_51_), + .Q(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_51_) + ); + FD com_llm_llm_rx_top_llm_rx_dllp_crc_crc16_ori_8_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_dllp_crc_crc16_ori_4_i_m3_0[8]), + .Q(com_llm_llm_rx_top_llm_rx_dllp_crc_crc16_ori[8]) + ); + FD com_llm_llm_rx_top_llm_rx_dllp_crc_crc16_ori_7_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_dllp_crc_crc16_ori_4_i_m3_0[7]), + .Q(com_llm_llm_rx_top_llm_rx_dllp_crc_crc16_ori[7]) + ); + FD com_llm_llm_rx_top_llm_rx_dllp_crc_crc16_ori_6_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_dllp_crc_crc16_ori_4_i_m3_0[6]), + .Q(com_llm_llm_rx_top_llm_rx_dllp_crc_crc16_ori[6]) + ); + FD com_llm_llm_rx_top_llm_rx_dllp_crc_crc16_ori_5_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_dllp_crc_crc16_ori_4_i_m3_0[5]), + .Q(com_llm_llm_rx_top_llm_rx_dllp_crc_crc16_ori[5]) + ); + FD com_llm_llm_rx_top_llm_rx_dllp_crc_crc16_ori_4_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_dllp_crc_crc16_ori_4_i_m3_0[4]), + .Q(com_llm_llm_rx_top_llm_rx_dllp_crc_crc16_ori[4]) + ); + FD com_llm_llm_rx_top_llm_rx_dllp_crc_crc16_ori_3_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_dllp_crc_crc16_ori_4_i_m3_0[3]), + .Q(com_llm_llm_rx_top_llm_rx_dllp_crc_crc16_ori[3]) + ); + FD com_llm_llm_rx_top_llm_rx_dllp_crc_crc16_ori_2_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_dllp_crc_crc16_ori_4_i_m3_0[2]), + .Q(com_llm_llm_rx_top_llm_rx_dllp_crc_crc16_ori[2]) + ); + FD com_llm_llm_rx_top_llm_rx_dllp_crc_crc16_ori_1_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_dllp_crc_crc16_ori_4_i_m3_0[1]), + .Q(com_llm_llm_rx_top_llm_rx_dllp_crc_crc16_ori[1]) + ); + FD com_llm_llm_rx_top_llm_rx_dllp_crc_crc16_ori_0_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_dllp_crc_crc16_ori_4_i_m3_0[0]), + .Q(com_llm_llm_rx_top_llm_rx_dllp_crc_crc16_ori[0]) + ); + FD com_llm_llm_rx_top_llm_rx_dllp_crc_crc16_ori_15_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_dllp_crc_crc16_ori_4_i_m3_0[15]), + .Q(com_llm_llm_rx_top_llm_rx_dllp_crc_crc16_ori[15]) + ); + FD com_llm_llm_rx_top_llm_rx_dllp_crc_crc16_ori_14_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_dllp_crc_crc16_ori_4_i_m3_0[14]), + .Q(com_llm_llm_rx_top_llm_rx_dllp_crc_crc16_ori[14]) + ); + FD com_llm_llm_rx_top_llm_rx_dllp_crc_crc16_ori_13_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_dllp_crc_crc16_ori_4_i_m3_0[13]), + .Q(com_llm_llm_rx_top_llm_rx_dllp_crc_crc16_ori[13]) + ); + FD com_llm_llm_rx_top_llm_rx_dllp_crc_crc16_ori_12_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_dllp_crc_crc16_ori_4_i_m3_0[12]), + .Q(com_llm_llm_rx_top_llm_rx_dllp_crc_crc16_ori[12]) + ); + FD com_llm_llm_rx_top_llm_rx_dllp_crc_crc16_ori_11_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_dllp_crc_crc16_ori_4_i_m3_0[11]), + .Q(com_llm_llm_rx_top_llm_rx_dllp_crc_crc16_ori[11]) + ); + FD com_llm_llm_rx_top_llm_rx_dllp_crc_crc16_ori_10_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_dllp_crc_crc16_ori_4_i_m3_0[10]), + .Q(com_llm_llm_rx_top_llm_rx_dllp_crc_crc16_ori[10]) + ); + FD com_llm_llm_rx_top_llm_rx_dllp_crc_crc16_ori_9_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_dllp_crc_crc16_ori_4_i_m3_0[9]), + .Q(com_llm_llm_rx_top_llm_rx_dllp_crc_crc16_ori[9]) + ); + FDCE com_llm_llm_rx_top_llm_rx_dllp_crc_fr_straddle ( + .CE(com_llm_llm_rx_top_llm_rx_dllp_crc_N_87608_i_2613), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_rx_dllp_sof_n_i), + .Q(com_llm_llm_rx_top_llm_rx_dllp_crc_fr_straddle_2614), + .CLR(plm_link_up_i) + ); + defparam com_llm_llm_rx_top_llm_rx_dllp_crc_crc16_ok_0_I_45.INIT = 16'h8421; + LUT4 com_llm_llm_rx_top_llm_rx_dllp_crc_crc16_ok_0_I_45 ( + .I0(com_llm_llm_rx_top_llm_rx_dllp_crc_un1_crc16_ok_0[14]), + .I1(com_llm_llm_rx_top_llm_rx_dllp_crc_un1_crc16_ok_0[15]), + .I2(com_llm_llm_rx_top_llm_rx_dllp_crc_crc16_ori[14]), + .I3(com_llm_llm_rx_top_llm_rx_dllp_crc_crc16_ori[15]), + .O(com_llm_llm_rx_top_llm_rx_dllp_crc_N_27) + ); + defparam com_llm_llm_rx_top_llm_rx_dllp_crc_crc16_ok_0_I_72.INIT = 16'h8421; + LUT4 com_llm_llm_rx_top_llm_rx_dllp_crc_crc16_ok_0_I_72 ( + .I0(com_llm_llm_rx_top_llm_rx_dllp_crc_un1_crc16_ok_0[6]), + .I1(com_llm_llm_rx_top_llm_rx_dllp_crc_un1_crc16_ok_0[7]), + .I2(com_llm_llm_rx_top_llm_rx_dllp_crc_crc16_ori[6]), + .I3(com_llm_llm_rx_top_llm_rx_dllp_crc_crc16_ori[7]), + .O(com_llm_llm_rx_top_llm_rx_dllp_crc_N_3) + ); + defparam com_llm_llm_rx_top_llm_rx_dllp_crc_crc16_ok_0_I_63.INIT = 16'h8421; + LUT4 com_llm_llm_rx_top_llm_rx_dllp_crc_crc16_ok_0_I_63 ( + .I0(com_llm_llm_rx_top_llm_rx_dllp_crc_un1_crc16_ok_0[12]), + .I1(com_llm_llm_rx_top_llm_rx_dllp_crc_un1_crc16_ok_0[13]), + .I2(com_llm_llm_rx_top_llm_rx_dllp_crc_crc16_ori[12]), + .I3(com_llm_llm_rx_top_llm_rx_dllp_crc_crc16_ori[13]), + .O(com_llm_llm_rx_top_llm_rx_dllp_crc_N_11) + ); + defparam com_llm_llm_rx_top_llm_rx_dllp_crc_crc16_ok_0_I_54.INIT = 16'h8421; + LUT4 com_llm_llm_rx_top_llm_rx_dllp_crc_crc16_ok_0_I_54 ( + .I0(com_llm_llm_rx_top_llm_rx_dllp_crc_un1_crc16_ok_0[10]), + .I1(com_llm_llm_rx_top_llm_rx_dllp_crc_un1_crc16_ok_0[11]), + .I2(com_llm_llm_rx_top_llm_rx_dllp_crc_crc16_ori[10]), + .I3(com_llm_llm_rx_top_llm_rx_dllp_crc_crc16_ori[11]), + .O(com_llm_llm_rx_top_llm_rx_dllp_crc_N_19) + ); + defparam com_llm_llm_rx_top_llm_rx_dllp_crc_crc16_ok_0_I_36.INIT = 16'h8421; + LUT4 com_llm_llm_rx_top_llm_rx_dllp_crc_crc16_ok_0_I_36 ( + .I0(com_llm_llm_rx_top_llm_rx_dllp_crc_un1_crc16_ok_0[8]), + .I1(com_llm_llm_rx_top_llm_rx_dllp_crc_un1_crc16_ok_0[9]), + .I2(com_llm_llm_rx_top_llm_rx_dllp_crc_crc16_ori[8]), + .I3(com_llm_llm_rx_top_llm_rx_dllp_crc_crc16_ori[9]), + .O(com_llm_llm_rx_top_llm_rx_dllp_crc_N_35) + ); + defparam com_llm_llm_rx_top_llm_rx_dllp_crc_crc16_ok_0_I_27.INIT = 16'h8421; + LUT4 com_llm_llm_rx_top_llm_rx_dllp_crc_crc16_ok_0_I_27 ( + .I0(com_llm_llm_rx_top_llm_rx_dllp_crc_un1_crc16_ok_0[4]), + .I1(com_llm_llm_rx_top_llm_rx_dllp_crc_un1_crc16_ok_0[5]), + .I2(com_llm_llm_rx_top_llm_rx_dllp_crc_crc16_ori[4]), + .I3(com_llm_llm_rx_top_llm_rx_dllp_crc_crc16_ori[5]), + .O(com_llm_llm_rx_top_llm_rx_dllp_crc_N_43) + ); + defparam com_llm_llm_rx_top_llm_rx_dllp_crc_crc16_ok_0_I_18.INIT = 16'h8421; + LUT4 com_llm_llm_rx_top_llm_rx_dllp_crc_crc16_ok_0_I_18 ( + .I0(com_llm_llm_rx_top_llm_rx_dllp_crc_un1_crc16_ok_0[2]), + .I1(com_llm_llm_rx_top_llm_rx_dllp_crc_un1_crc16_ok_0[3]), + .I2(com_llm_llm_rx_top_llm_rx_dllp_crc_crc16_ori[2]), + .I3(com_llm_llm_rx_top_llm_rx_dllp_crc_crc16_ori[3]), + .O(com_llm_llm_rx_top_llm_rx_dllp_crc_N_51) + ); + defparam com_llm_llm_rx_top_llm_rx_dllp_crc_crc16_ok_0_I_9.INIT = 16'h8421; + LUT4 com_llm_llm_rx_top_llm_rx_dllp_crc_crc16_ok_0_I_9 ( + .I0(com_llm_llm_rx_top_llm_rx_dllp_crc_un1_crc16_ok_0[0]), + .I1(com_llm_llm_rx_top_llm_rx_dllp_crc_un1_crc16_ok_0[1]), + .I2(com_llm_llm_rx_top_llm_rx_dllp_crc_crc16_ori[0]), + .I3(com_llm_llm_rx_top_llm_rx_dllp_crc_crc16_ori[1]), + .O(com_llm_llm_rx_top_llm_rx_dllp_crc_N_59) + ); + defparam com_llm_llm_rx_top_llm_rx_dllp_crc_llm_rx_crc16_d32_st_new_c32_1_2_15_.INIT = 16'h6996; + LUT4 com_llm_llm_rx_top_llm_rx_dllp_crc_llm_rx_crc16_d32_st_new_c32_1_2_15_ ( + .I0(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_3_), + .I1(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_11_), + .I2(com_llm_llm_rx_top_rx_data_56_), + .I3(com_llm_llm_rx_top_rx_data_60_), + .O(com_llm_llm_rx_top_llm_rx_dllp_crc_llm_rx_crc16_d32_st_new_c32_1_2_15__2621) + ); + defparam com_llm_llm_rx_top_llm_rx_dllp_crc_llm_rx_crc16_d32_st_new_c32_1_1_13_.INIT = 16'h6996; + LUT4 com_llm_llm_rx_top_llm_rx_dllp_crc_llm_rx_crc16_d32_st_new_c32_1_1_13_ ( + .I0(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_5_), + .I1(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_13_), + .I2(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_21_), + .I3(com_llm_llm_rx_top_rx_data_58_), + .O(com_llm_llm_rx_top_llm_rx_dllp_crc_llm_rx_crc16_d32_st_new_c32_1_1_13__2622) + ); + defparam com_llm_llm_rx_top_llm_rx_dllp_crc_llm_rx_crc16_d32_st_new_c32_1_1_0_0_.INIT = 8'h96; + LUT3_L com_llm_llm_rx_top_llm_rx_dllp_crc_llm_rx_crc16_d32_st_new_c32_1_1_0_0_ ( + .I0(N_11975_1), + .I1(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_0_), + .I2(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_2_), + .LO(com_llm_llm_rx_top_llm_rx_dllp_crc_llm_rx_crc16_d32_st_new_c32_1_1_0_) + ); + defparam com_llm_llm_rx_top_llm_rx_dllp_crc_llm_rx_crc16_d32_st_new_c32_1_1_10_.INIT = 8'h96; + LUT3 com_llm_llm_rx_top_llm_rx_dllp_crc_llm_rx_crc16_d32_st_new_c32_1_1_10_ ( + .I0(N_11901_1), + .I1(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_6_), + .I2(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_18_), + .O(com_llm_llm_rx_top_llm_rx_dllp_crc_llm_rx_crc16_d32_st_new_c32_1_1_10__2624) + ); + defparam com_llm_llm_rx_top_llm_rx_dllp_crc_llm_rx_crc16_d32_st_new_c32_1_1_3_3_.INIT = 16'h6996; + LUT4 com_llm_llm_rx_top_llm_rx_dllp_crc_llm_rx_crc16_d32_st_new_c32_1_1_3_3_ ( + .I0(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_9_), + .I1(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_16_), + .I2(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_17_), + .I3(com_llm_llm_rx_top_rx_data_61_), + .O(com_llm_llm_rx_top_llm_rx_dllp_crc_llm_rx_crc16_d32_st_new_c32_1_1_3__2618) + ); + defparam com_llm_llm_rx_top_llm_rx_dllp_crc_llm_rx_crc16_d32_st_new_c32_1_1_4_.INIT = 16'h6996; + LUT4 com_llm_llm_rx_top_llm_rx_dllp_crc_llm_rx_crc16_d32_st_new_c32_1_1_4_ ( + .I0(G_203_433), + .I1(N_11902_1), + .I2(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_6_), + .I3(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_14_), + .O(com_llm_llm_rx_top_llm_rx_dllp_crc_llm_rx_crc16_d32_st_new_c32_1_i_1[4]) + ); + defparam com_llm_llm_rx_top_llm_rx_dllp_crc_llm_rx_crc16_d32_st_new_c32_1_0_12_.INIT = 16'h6996; + LUT4 com_llm_llm_rx_top_llm_rx_dllp_crc_llm_rx_crc16_d32_st_new_c32_1_0_12_ ( + .I0(N_11902_1), + .I1(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_6_), + .I2(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_14_), + .I3(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_23_), + .O(com_llm_llm_rx_top_llm_rx_dllp_crc_llm_rx_crc16_d32_st_new_c32_1_0[12]) + ); + defparam com_llm_llm_rx_top_llm_rx_dllp_crc_llm_rx_crc16_d32_st_new_c32_1_1_2_3_.INIT = 16'h6996; + LUT4_L com_llm_llm_rx_top_llm_rx_dllp_crc_llm_rx_crc16_d32_st_new_c32_1_1_2_3_ ( + .I0(G_241_439), + .I1(N_11901_1), + .I2(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_15_), + .I3(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_23_), + .LO(com_llm_llm_rx_top_llm_rx_dllp_crc_llm_rx_crc16_d32_st_new_c32_1_1_2[3]) + ); + defparam com_llm_llm_rx_top_llm_rx_dllp_crc_llm_rx_crc16_d32_st_new_c32_1_1_1_.INIT = 16'h6996; + LUT4_L com_llm_llm_rx_top_llm_rx_dllp_crc_llm_rx_crc16_d32_st_new_c32_1_1_1_ ( + .I0(N_11902_1), + .I1(G_317_593), + .I2(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_0_), + .I3(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_23_), + .LO(com_llm_llm_rx_top_llm_rx_dllp_crc_llm_rx_crc16_d32_st_new_c32_1_1_1__2620) + ); + defparam com_llm_llm_rx_top_llm_rx_dllp_crc_llm_rx_crc16_d32_st_new_c32_1_1_11_.INIT = 16'h6996; + LUT4 com_llm_llm_rx_top_llm_rx_dllp_crc_llm_rx_crc16_d32_st_new_c32_1_1_11_ ( + .I0(N_231), + .I1(N_11902_1), + .I2(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_0_), + .I3(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_23_), + .O(com_llm_llm_rx_top_llm_rx_dllp_crc_llm_rx_crc16_d32_st_new_c32_1_1_11__2623) + ); + defparam com_llm_llm_rx_top_llm_rx_dllp_crc_llm_rx_crc16_d32_st_new_c32_1_2_8_.INIT = 16'h6996; + LUT4_L com_llm_llm_rx_top_llm_rx_dllp_crc_llm_rx_crc16_d32_st_new_c32_1_2_8_ ( + .I0(G_241_439), + .I1(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_6_), + .I2(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_17_), + .I3(com_llm_llm_rx_top_rx_data_58_), + .LO(com_llm_llm_rx_top_llm_rx_dllp_crc_llm_rx_crc16_d32_st_new_c32_1_2_8__2626) + ); + defparam com_llm_llm_rx_top_llm_rx_dllp_crc_llm_rx_crc16_d32_st_new_c32_1_1_7_.INIT = 16'h6996; + LUT4 com_llm_llm_rx_top_llm_rx_dllp_crc_llm_rx_crc16_d32_st_new_c32_1_1_7_ ( + .I0(N_11901_1), + .I1(G_290_553), + .I2(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_15_), + .I3(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_23_), + .O(com_llm_llm_rx_top_llm_rx_dllp_crc_llm_rx_crc16_d32_st_new_c32_1_1_7__2615) + ); + defparam com_llm_llm_rx_top_llm_rx_dllp_crc_llm_rx_crc16_d32_st_new_c32_1_2_4_.INIT = 16'h6996; + LUT4 com_llm_llm_rx_top_llm_rx_dllp_crc_llm_rx_crc16_d32_st_new_c32_1_2_4_ ( + .I0(G_273_594), + .I1(com_llm_llm_rx_top_rx_data_58_), + .I2(com_llm_llm_rx_top_rx_data_59_), + .I3(com_llm_llm_rx_top_rx_data_60_), + .O(com_llm_llm_rx_top_llm_rx_dllp_crc_llm_rx_crc16_d32_st_new_c32_1_2_4__2617) + ); + defparam com_llm_llm_rx_top_llm_rx_dllp_crc_llm_rx_crc16_d32_st_new_c32_1_1_5_.INIT = 8'h96; + LUT3 com_llm_llm_rx_top_llm_rx_dllp_crc_llm_rx_crc16_d32_st_new_c32_1_1_5_ ( + .I0(G_264_596), + .I1(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_6_), + .I2(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_12_), + .O(com_llm_llm_rx_top_llm_rx_dllp_crc_llm_rx_crc16_d32_st_new_c32_1_1_5__2616) + ); + defparam com_llm_llm_rx_top_llm_rx_dllp_crc_llm_rx_crc16_d32_st_new_c32_1_1_3_.INIT = 16'h6996; + LUT4 com_llm_llm_rx_top_llm_rx_dllp_crc_llm_rx_crc16_d32_st_new_c32_1_1_3_ ( + .I0(N_218), + .I1(com_llm_llm_rx_top_llm_rx_dllp_crc_llm_rx_crc16_d32_st_new_c32_1_1_2[3]), + .I2(com_llm_llm_rx_top_rx_data_57_), + .I3(com_llm_llm_rx_top_rx_data_60_), + .O(com_llm_llm_rx_top_llm_rx_dllp_crc_llm_rx_crc16_d32_st_new_c32_1_i_1[3]) + ); + defparam com_llm_llm_rx_top_llm_rx_dllp_crc_llm_rx_crc16_d32_st_new_c32_1_1_9_.INIT = 8'h96; + LUT3 com_llm_llm_rx_top_llm_rx_dllp_crc_llm_rx_crc16_d32_st_new_c32_1_1_9_ ( + .I0(N_176), + .I1(G_290_553), + .I2(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_17_), + .O(com_llm_llm_rx_top_llm_rx_dllp_crc_llm_rx_crc16_d32_st_new_c32_1_1_9__2625) + ); + defparam com_llm_llm_rx_top_llm_rx_dllp_crc_llm_rx_crc16_d32_st_new_c32_1_2_2_.INIT = 16'h6996; + LUT4 com_llm_llm_rx_top_llm_rx_dllp_crc_llm_rx_crc16_d32_st_new_c32_1_2_2_ ( + .I0(N_230), + .I1(G_273_594), + .I2(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_10_), + .I3(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_19_), + .O(com_llm_llm_rx_top_llm_rx_dllp_crc_llm_rx_crc16_d32_st_new_c32_1_2_2__2619) + ); + defparam com_llm_llm_rx_top_llm_rx_dllp_crc_llm_rx_crc16_d32_st_new_c32_1_7_.INIT = 16'h6996; + LUT4_L com_llm_llm_rx_top_llm_rx_dllp_crc_llm_rx_crc16_d32_st_new_c32_1_7_ ( + .I0(N_11899_1), + .I1(G_264_596), + .I2(G_443_89), + .I3(com_llm_llm_rx_top_llm_rx_dllp_crc_llm_rx_crc16_d32_st_new_c32_1_1_7__2615), + .LO(com_llm_llm_rx_top_llm_rx_dllp_crc_new_c32_1_i_7_) + ); + defparam com_llm_llm_rx_top_llm_rx_dllp_crc_llm_rx_crc16_d32_st_new_c32_st_i_6_.INIT = 8'h69; + LUT3_L com_llm_llm_rx_top_llm_rx_dllp_crc_llm_rx_crc16_d32_st_new_c32_st_i_6_ ( + .I0(N_175), + .I1(G_260_579), + .I2(com_llm_llm_rx_top_llm_rx_dllp_crc_llm_rx_crc16_d32_st_new_c32_1_i_1[3]), + .LO(com_llm_llm_rx_top_llm_rx_dllp_crc_new_c32_st_i_6_) + ); + defparam com_llm_llm_rx_top_llm_rx_dllp_crc_llm_rx_crc16_d32_st_new_c32_1_5_.INIT = 16'h6996; + LUT4_L com_llm_llm_rx_top_llm_rx_dllp_crc_llm_rx_crc16_d32_st_new_c32_1_5_ ( + .I0(N_218), + .I1(N_231), + .I2(G_450_389), + .I3(com_llm_llm_rx_top_llm_rx_dllp_crc_llm_rx_crc16_d32_st_new_c32_1_1_5__2616), + .LO(com_llm_llm_rx_top_llm_rx_dllp_crc_new_c32_1_i_5_) + ); + defparam com_llm_llm_rx_top_llm_rx_dllp_crc_llm_rx_crc16_d32_st_new_c32_1_4_.INIT = 16'h6996; + LUT4_L com_llm_llm_rx_top_llm_rx_dllp_crc_llm_rx_crc16_d32_st_new_c32_1_4_ ( + .I0(N_231), + .I1(N_31578_i_0), + .I2(com_llm_llm_rx_top_llm_rx_dllp_crc_llm_rx_crc16_d32_st_new_c32_1_2_4__2617), + .I3(com_llm_llm_rx_top_llm_rx_dllp_crc_llm_rx_crc16_d32_st_new_c32_1_i_1[4]), + .LO(com_llm_llm_rx_top_llm_rx_dllp_crc_new_c32_1_i_4_) + ); + defparam com_llm_llm_rx_top_llm_rx_dllp_crc_llm_rx_crc16_d32_st_new_c32_1_3_.INIT = 16'h6996; + LUT4_L com_llm_llm_rx_top_llm_rx_dllp_crc_llm_rx_crc16_d32_st_new_c32_1_3_ ( + .I0(N_231), + .I1(N_11975_1), + .I2(com_llm_llm_rx_top_llm_rx_dllp_crc_llm_rx_crc16_d32_st_new_c32_1_1_3__2618), + .I3(com_llm_llm_rx_top_llm_rx_dllp_crc_llm_rx_crc16_d32_st_new_c32_1_i_1[3]), + .LO(com_llm_llm_rx_top_llm_rx_dllp_crc_new_c32_1_i_3_) + ); + defparam com_llm_llm_rx_top_llm_rx_dllp_crc_llm_rx_crc16_d32_st_new_c32_st_i_2_.INIT = 4'h9; + LUT2_L com_llm_llm_rx_top_llm_rx_dllp_crc_llm_rx_crc16_d32_st_new_c32_st_i_2_ ( + .I0(G_450_389), + .I1(com_llm_llm_rx_top_llm_rx_dllp_crc_llm_rx_crc16_d32_st_new_c32_1_2_2__2619), + .LO(com_llm_llm_rx_top_llm_rx_dllp_crc_new_c32_st_i_2_) + ); + defparam com_llm_llm_rx_top_llm_rx_dllp_crc_llm_rx_crc16_d32_st_new_c32_st_i_1_.INIT = 16'h9669; + LUT4_L com_llm_llm_rx_top_llm_rx_dllp_crc_llm_rx_crc16_d32_st_new_c32_st_i_1_ ( + .I0(G_260_579), + .I1(G_510_423), + .I2(com_llm_llm_rx_top_llm_rx_dllp_crc_llm_rx_crc16_d32_st_new_c32_1_1_1__2620), + .I3(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_20_), + .LO(com_llm_llm_rx_top_llm_rx_dllp_crc_new_c32_st_i_1_) + ); + defparam com_llm_llm_rx_top_llm_rx_dllp_crc_llm_rx_crc16_d32_st_new_c32_1_0_.INIT = 16'h6996; + LUT4_L com_llm_llm_rx_top_llm_rx_dllp_crc_llm_rx_crc16_d32_st_new_c32_1_0_ ( + .I0(N_198), + .I1(G_252_614), + .I2(com_llm_llm_rx_top_llm_rx_dllp_crc_llm_rx_crc16_d32_st_new_c32_1_1_0_), + .I3(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_7_), + .LO(com_llm_llm_rx_top_llm_rx_dllp_crc_new_c32_1_i_0_) + ); + defparam com_llm_llm_rx_top_llm_rx_dllp_crc_llm_rx_crc16_d32_st_new_c32_st_i_15_.INIT = 16'h9669; + LUT4_L com_llm_llm_rx_top_llm_rx_dllp_crc_llm_rx_crc16_d32_st_new_c32_st_i_15_ ( + .I0(N_175), + .I1(G_279_548), + .I2(com_llm_llm_rx_top_llm_rx_dllp_crc_llm_rx_crc16_d32_st_new_c32_1_2_15__2621), + .I3(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_4_), + .LO(com_llm_llm_rx_top_llm_rx_dllp_crc_new_c32_st_i_15_) + ); + defparam com_llm_llm_rx_top_llm_rx_dllp_crc_llm_rx_crc16_d32_st_new_c32_st_i_14_.INIT = 16'h9669; + LUT4_L com_llm_llm_rx_top_llm_rx_dllp_crc_llm_rx_crc16_d32_st_new_c32_st_i_14_ ( + .I0(N_176), + .I1(G_439_434), + .I2(com_llm_llm_rx_top_rx_data_57_), + .I3(com_llm_llm_rx_top_rx_data_61_), + .LO(com_llm_llm_rx_top_llm_rx_dllp_crc_new_c32_st_i_14_) + ); + defparam com_llm_llm_rx_top_llm_rx_dllp_crc_llm_rx_crc16_d32_st_new_c32_1_13_.INIT = 8'h96; + LUT3_L com_llm_llm_rx_top_llm_rx_dllp_crc_llm_rx_crc16_d32_st_new_c32_1_13_ ( + .I0(N_230), + .I1(G_510_423), + .I2(com_llm_llm_rx_top_llm_rx_dllp_crc_llm_rx_crc16_d32_st_new_c32_1_1_13__2622), + .LO(com_llm_llm_rx_top_llm_rx_dllp_crc_new_c32_1_i_13_) + ); + defparam com_llm_llm_rx_top_llm_rx_dllp_crc_llm_rx_crc16_d32_st_new_c32_1_12_.INIT = 16'h6996; + LUT4_L com_llm_llm_rx_top_llm_rx_dllp_crc_llm_rx_crc16_d32_st_new_c32_1_12_ ( + .I0(N_175), + .I1(G_317_593), + .I2(com_llm_llm_rx_top_llm_rx_dllp_crc_llm_rx_crc16_d32_st_new_c32_1_0[12]), + .I3(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_4_), + .LO(com_llm_llm_rx_top_llm_rx_dllp_crc_new_c32_1_i_12_) + ); + defparam com_llm_llm_rx_top_llm_rx_dllp_crc_llm_rx_crc16_d32_st_new_c32_st_i_11_.INIT = 16'h9669; + LUT4_L com_llm_llm_rx_top_llm_rx_dllp_crc_llm_rx_crc16_d32_st_new_c32_st_i_11_ ( + .I0(N_198), + .I1(G_439_434), + .I2(com_llm_llm_rx_top_llm_rx_dllp_crc_llm_rx_crc16_d32_st_new_c32_1_1_11__2623), + .I3(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_5_), + .LO(com_llm_llm_rx_top_llm_rx_dllp_crc_new_c32_st_i_11_) + ); + defparam com_llm_llm_rx_top_llm_rx_dllp_crc_llm_rx_crc16_d32_st_new_c32_st_i_10_.INIT = 16'h9669; + LUT4_L com_llm_llm_rx_top_llm_rx_dllp_crc_llm_rx_crc16_d32_st_new_c32_st_i_10_ ( + .I0(G_279_548), + .I1(N_12101_1), + .I2(N_31578_i_0), + .I3(com_llm_llm_rx_top_llm_rx_dllp_crc_llm_rx_crc16_d32_st_new_c32_1_1_10__2624), + .LO(com_llm_llm_rx_top_llm_rx_dllp_crc_new_c32_st_i_10_) + ); + defparam com_llm_llm_rx_top_llm_rx_dllp_crc_llm_rx_crc16_d32_st_new_c32_1_9_.INIT = 16'h6996; + LUT4_L com_llm_llm_rx_top_llm_rx_dllp_crc_llm_rx_crc16_d32_st_new_c32_1_9_ ( + .I0(N_198), + .I1(com_llm_llm_rx_top_llm_rx_dllp_crc_llm_rx_crc16_d32_st_new_c32_1_1_9__2625), + .I2(com_llm_llm_rx_top_llm_rx_dllp_crc_llm_rx_crc16_d32_st_new_c32_1_i_1[4]), + .I3(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_7_), + .LO(com_llm_llm_rx_top_llm_rx_dllp_crc_new_c32_1_i_9_) + ); + defparam com_llm_llm_rx_top_llm_rx_dllp_crc_llm_rx_crc16_d32_st_new_c32_st_i_8_.INIT = 16'h9669; + LUT4_L com_llm_llm_rx_top_llm_rx_dllp_crc_llm_rx_crc16_d32_st_new_c32_st_i_8_ ( + .I0(N_11902_1), + .I1(G_252_614), + .I2(G_443_89), + .I3(com_llm_llm_rx_top_llm_rx_dllp_crc_llm_rx_crc16_d32_st_new_c32_1_2_8__2626), + .LO(com_llm_llm_rx_top_llm_rx_dllp_crc_new_c32_st_i_8_) + ); + defparam com_llm_llm_rx_top_llm_rx_dllp_crc_llm_rx_crc16_d32_nst_new_c32_1_0_2_.INIT = 4'h6; + LUT2 com_llm_llm_rx_top_llm_rx_dllp_crc_llm_rx_crc16_d32_nst_new_c32_1_0_2_ ( + .I0(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_42_), + .I1(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_51_), + .O(com_llm_llm_rx_top_llm_rx_dllp_crc_llm_rx_crc16_d32_nst_new_c32_1_0_2__2632) + ); + defparam com_llm_llm_rx_top_llm_rx_dllp_crc_llm_rx_crc16_d32_nst_new_c32_1_2_15_.INIT = 16'h6996; + LUT4 com_llm_llm_rx_top_llm_rx_dllp_crc_llm_rx_crc16_d32_nst_new_c32_1_2_15_ ( + .I0(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_24_), + .I1(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q[28]), + .I2(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_35_), + .I3(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_43_), + .O(com_llm_llm_rx_top_llm_rx_dllp_crc_llm_rx_crc16_d32_nst_new_c32_1_2_15__2634) + ); + defparam com_llm_llm_rx_top_llm_rx_dllp_crc_llm_rx_crc16_d32_nst_new_c32_1_1_0_0_.INIT = 8'h96; + LUT3_L com_llm_llm_rx_top_llm_rx_dllp_crc_llm_rx_crc16_d32_nst_new_c32_1_1_0_0_ ( + .I0(N_31583_i_0), + .I1(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_32_), + .I2(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_34_), + .LO(com_llm_llm_rx_top_llm_rx_dllp_crc_llm_rx_crc16_d32_nst_new_c32_1_1_0_) + ); + defparam com_llm_llm_rx_top_llm_rx_dllp_crc_llm_rx_crc16_d32_nst_new_c32_1_1_13_.INIT = 16'h6996; + LUT4 com_llm_llm_rx_top_llm_rx_dllp_crc_llm_rx_crc16_d32_nst_new_c32_1_1_13_ ( + .I0(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_26_), + .I1(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_37_), + .I2(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_45_), + .I3(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_53_), + .O(com_llm_llm_rx_top_llm_rx_dllp_crc_llm_rx_crc16_d32_nst_new_c32_1_1_13__2635) + ); + defparam com_llm_llm_rx_top_llm_rx_dllp_crc_llm_rx_crc16_d32_nst_new_c32_1_1_3_3_.INIT = 16'h6996; + LUT4 com_llm_llm_rx_top_llm_rx_dllp_crc_llm_rx_crc16_d32_nst_new_c32_1_1_3_3_ ( + .I0(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_29_), + .I1(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_41_), + .I2(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_48_), + .I3(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_49_), + .O(com_llm_llm_rx_top_llm_rx_dllp_crc_llm_rx_crc16_d32_nst_new_c32_1_1_3__2631) + ); + defparam com_llm_llm_rx_top_llm_rx_dllp_crc_llm_rx_crc16_d32_nst_new_c32_1_1_4_.INIT = 16'h6996; + LUT4 com_llm_llm_rx_top_llm_rx_dllp_crc_llm_rx_crc16_d32_nst_new_c32_1_1_4_ ( + .I0(G_202_431), + .I1(N_11904_1), + .I2(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_38_), + .I3(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_46_), + .O(com_llm_llm_rx_top_llm_rx_dllp_crc_llm_rx_crc16_d32_nst_new_c32_1_i_1[4]) + ); + defparam com_llm_llm_rx_top_llm_rx_dllp_crc_llm_rx_crc16_d32_nst_new_c32_1_0_12_.INIT = 16'h6996; + LUT4 com_llm_llm_rx_top_llm_rx_dllp_crc_llm_rx_crc16_d32_nst_new_c32_1_0_12_ ( + .I0(N_11904_1), + .I1(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_38_), + .I2(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_46_), + .I3(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_55_), + .O(com_llm_llm_rx_top_llm_rx_dllp_crc_llm_rx_crc16_d32_nst_new_c32_1_0_12__2636) + ); + defparam com_llm_llm_rx_top_llm_rx_dllp_crc_llm_rx_crc16_d32_nst_new_c32_1_1_2_3_.INIT = 4'h6; + LUT2_L com_llm_llm_rx_top_llm_rx_dllp_crc_llm_rx_crc16_d32_nst_new_c32_1_1_2_3_ ( + .I0(G_237_435), + .I1(G_245_591), + .LO(com_llm_llm_rx_top_llm_rx_dllp_crc_llm_rx_crc16_d32_nst_new_c32_1_1_2[3]) + ); + defparam com_llm_llm_rx_top_llm_rx_dllp_crc_llm_rx_crc16_d32_nst_new_c32_1_1_1_.INIT = 16'h6996; + LUT4_L com_llm_llm_rx_top_llm_rx_dllp_crc_llm_rx_crc16_d32_nst_new_c32_1_1_1_ ( + .I0(N_11904_1), + .I1(G_316_595), + .I2(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_32_), + .I3(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_55_), + .LO(com_llm_llm_rx_top_llm_rx_dllp_crc_llm_rx_crc16_d32_nst_new_c32_1_1_1__2633) + ); + defparam com_llm_llm_rx_top_llm_rx_dllp_crc_llm_rx_crc16_d32_nst_new_c32_1_1_11_.INIT = 16'h6996; + LUT4 com_llm_llm_rx_top_llm_rx_dllp_crc_llm_rx_crc16_d32_nst_new_c32_1_1_11_ ( + .I0(G_227_584), + .I1(N_11904_1), + .I2(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_32_), + .I3(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_55_), + .O(com_llm_llm_rx_top_llm_rx_dllp_crc_llm_rx_crc16_d32_nst_new_c32_1_1_11__2637) + ); + defparam com_llm_llm_rx_top_llm_rx_dllp_crc_llm_rx_crc16_d32_nst_new_c32_1_2_10_.INIT = 16'h6996; + LUT4 com_llm_llm_rx_top_llm_rx_dllp_crc_llm_rx_crc16_d32_nst_new_c32_1_2_10_ ( + .I0(N_11903_1), + .I1(G_280_549), + .I2(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_38_), + .I3(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_50_), + .O(com_llm_llm_rx_top_llm_rx_dllp_crc_llm_rx_crc16_d32_nst_new_c32_1_2_10__2638) + ); + defparam com_llm_llm_rx_top_llm_rx_dllp_crc_llm_rx_crc16_d32_nst_new_c32_1_2_4_.INIT = 16'h6996; + LUT4 com_llm_llm_rx_top_llm_rx_dllp_crc_llm_rx_crc16_d32_nst_new_c32_1_2_4_ ( + .I0(G_274_580), + .I1(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_26_), + .I2(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_27_), + .I3(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q[28]), + .O(com_llm_llm_rx_top_llm_rx_dllp_crc_llm_rx_crc16_d32_nst_new_c32_1_2_4__2630) + ); + defparam com_llm_llm_rx_top_llm_rx_dllp_crc_llm_rx_crc16_d32_nst_new_c32_1_0_7_.INIT = 8'h96; + LUT3 com_llm_llm_rx_top_llm_rx_dllp_crc_llm_rx_crc16_d32_nst_new_c32_1_0_7_ ( + .I0(G_262_597), + .I1(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_24_), + .I2(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_36_), + .O(com_llm_llm_rx_top_llm_rx_dllp_crc_llm_rx_crc16_d32_nst_new_c32_1_0_7__2628) + ); + defparam com_llm_llm_rx_top_llm_rx_dllp_crc_llm_rx_crc16_d32_nst_new_c32_1_1_8_.INIT = 16'h6996; + LUT4 com_llm_llm_rx_top_llm_rx_dllp_crc_llm_rx_crc16_d32_nst_new_c32_1_1_8_ ( + .I0(N_11904_1), + .I1(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_26_), + .I2(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_38_), + .I3(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_49_), + .O(com_llm_llm_rx_top_llm_rx_dllp_crc_llm_rx_crc16_d32_nst_new_c32_1_1_8__2627) + ); + defparam com_llm_llm_rx_top_llm_rx_dllp_crc_llm_rx_crc16_d32_nst_new_c32_1_1_5_.INIT = 8'h96; + LUT3 com_llm_llm_rx_top_llm_rx_dllp_crc_llm_rx_crc16_d32_nst_new_c32_1_1_5_ ( + .I0(G_262_597), + .I1(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_38_), + .I2(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_44_), + .O(com_llm_llm_rx_top_llm_rx_dllp_crc_llm_rx_crc16_d32_nst_new_c32_1_1_5__2629) + ); + defparam com_llm_llm_rx_top_llm_rx_dllp_crc_llm_rx_crc16_d32_nst_new_c32_1_1_3_.INIT = 16'h6996; + LUT4 com_llm_llm_rx_top_llm_rx_dllp_crc_llm_rx_crc16_d32_nst_new_c32_1_1_3_ ( + .I0(N_219), + .I1(com_llm_llm_rx_top_llm_rx_dllp_crc_llm_rx_crc16_d32_nst_new_c32_1_1_2[3]), + .I2(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_25_), + .I3(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q[28]), + .O(com_llm_llm_rx_top_llm_rx_dllp_crc_llm_rx_crc16_d32_nst_new_c32_1_i_1[3]) + ); + defparam com_llm_llm_rx_top_llm_rx_dllp_crc_llm_rx_crc16_d32_nst_new_c32_1_1_9_.INIT = 8'h96; + LUT3 com_llm_llm_rx_top_llm_rx_dllp_crc_llm_rx_crc16_d32_nst_new_c32_1_1_9_ ( + .I0(N_180), + .I1(G_288_552), + .I2(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_49_), + .O(com_llm_llm_rx_top_llm_rx_dllp_crc_llm_rx_crc16_d32_nst_new_c32_1_1_9__2639) + ); + defparam com_llm_llm_rx_top_llm_rx_dllp_crc_llm_rx_crc16_d32_nst_new_c32_nst_i_8_.INIT = 16'h9669; + LUT4_L com_llm_llm_rx_top_llm_rx_dllp_crc_llm_rx_crc16_d32_nst_new_c32_nst_i_8_ ( + .I0(G_237_435), + .I1(G_253_613), + .I2(G_442_390), + .I3(com_llm_llm_rx_top_llm_rx_dllp_crc_llm_rx_crc16_d32_nst_new_c32_1_1_8__2627), + .LO(com_llm_llm_rx_top_llm_rx_dllp_crc_new_c32_nst_i_8_) + ); + defparam com_llm_llm_rx_top_llm_rx_dllp_crc_llm_rx_crc16_d32_nst_new_c32_1_7_.INIT = 16'h6996; + LUT4_L com_llm_llm_rx_top_llm_rx_dllp_crc_llm_rx_crc16_d32_nst_new_c32_1_7_ ( + .I0(G_245_591), + .I1(G_288_552), + .I2(G_442_390), + .I3(com_llm_llm_rx_top_llm_rx_dllp_crc_llm_rx_crc16_d32_nst_new_c32_1_0_7__2628), + .LO(com_llm_llm_rx_top_llm_rx_dllp_crc_new_c32_1_i_0_7_) + ); + defparam com_llm_llm_rx_top_llm_rx_dllp_crc_llm_rx_crc16_d32_nst_new_c32_nst_i_6_.INIT = 8'h69; + LUT3_L com_llm_llm_rx_top_llm_rx_dllp_crc_llm_rx_crc16_d32_nst_new_c32_nst_i_6_ ( + .I0(N_179), + .I1(G_259_578), + .I2(com_llm_llm_rx_top_llm_rx_dllp_crc_llm_rx_crc16_d32_nst_new_c32_1_i_1[3]), + .LO(com_llm_llm_rx_top_llm_rx_dllp_crc_new_c32_nst_i_6_) + ); + defparam com_llm_llm_rx_top_llm_rx_dllp_crc_llm_rx_crc16_d32_nst_new_c32_1_5_.INIT = 16'h6996; + LUT4_L com_llm_llm_rx_top_llm_rx_dllp_crc_llm_rx_crc16_d32_nst_new_c32_1_5_ ( + .I0(N_219), + .I1(G_227_584), + .I2(G_452_387), + .I3(com_llm_llm_rx_top_llm_rx_dllp_crc_llm_rx_crc16_d32_nst_new_c32_1_1_5__2629), + .LO(com_llm_llm_rx_top_llm_rx_dllp_crc_new_c32_1_i_0_5_) + ); + defparam com_llm_llm_rx_top_llm_rx_dllp_crc_llm_rx_crc16_d32_nst_new_c32_1_4_.INIT = 16'h6996; + LUT4_L com_llm_llm_rx_top_llm_rx_dllp_crc_llm_rx_crc16_d32_nst_new_c32_1_4_ ( + .I0(G_227_584), + .I1(N_31577_i_0), + .I2(com_llm_llm_rx_top_llm_rx_dllp_crc_llm_rx_crc16_d32_nst_new_c32_1_2_4__2630), + .I3(com_llm_llm_rx_top_llm_rx_dllp_crc_llm_rx_crc16_d32_nst_new_c32_1_i_1[4]), + .LO(com_llm_llm_rx_top_llm_rx_dllp_crc_new_c32_1_i_0_4_) + ); + defparam com_llm_llm_rx_top_llm_rx_dllp_crc_llm_rx_crc16_d32_nst_new_c32_1_3_.INIT = 16'h6996; + LUT4_L com_llm_llm_rx_top_llm_rx_dllp_crc_llm_rx_crc16_d32_nst_new_c32_1_3_ ( + .I0(G_227_584), + .I1(N_31583_i_0), + .I2(com_llm_llm_rx_top_llm_rx_dllp_crc_llm_rx_crc16_d32_nst_new_c32_1_1_3__2631), + .I3(com_llm_llm_rx_top_llm_rx_dllp_crc_llm_rx_crc16_d32_nst_new_c32_1_i_1[3]), + .LO(com_llm_llm_rx_top_llm_rx_dllp_crc_new_c32_1_i_0_3_) + ); + defparam com_llm_llm_rx_top_llm_rx_dllp_crc_llm_rx_crc16_d32_nst_new_c32_nst_i_2_.INIT = 16'h9669; + LUT4_L com_llm_llm_rx_top_llm_rx_dllp_crc_llm_rx_crc16_d32_nst_new_c32_nst_i_2_ ( + .I0(G_222_592), + .I1(G_274_580), + .I2(G_452_387), + .I3(com_llm_llm_rx_top_llm_rx_dllp_crc_llm_rx_crc16_d32_nst_new_c32_1_0_2__2632), + .LO(com_llm_llm_rx_top_llm_rx_dllp_crc_new_c32_nst_i_2_) + ); + defparam com_llm_llm_rx_top_llm_rx_dllp_crc_llm_rx_crc16_d32_nst_new_c32_nst_i_1_.INIT = 16'h9669; + LUT4_L com_llm_llm_rx_top_llm_rx_dllp_crc_llm_rx_crc16_d32_nst_new_c32_nst_i_1_ ( + .I0(G_259_578), + .I1(G_513_420), + .I2(com_llm_llm_rx_top_llm_rx_dllp_crc_llm_rx_crc16_d32_nst_new_c32_1_1_1__2633), + .I3(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_52_), + .LO(com_llm_llm_rx_top_llm_rx_dllp_crc_new_c32_nst_i_1_) + ); + defparam com_llm_llm_rx_top_llm_rx_dllp_crc_llm_rx_crc16_d32_nst_new_c32_1_0_.INIT = 16'h6996; + LUT4_L com_llm_llm_rx_top_llm_rx_dllp_crc_llm_rx_crc16_d32_nst_new_c32_1_0_ ( + .I0(N_197), + .I1(G_253_613), + .I2(com_llm_llm_rx_top_llm_rx_dllp_crc_llm_rx_crc16_d32_nst_new_c32_1_1_0_), + .I3(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_39_), + .LO(com_llm_llm_rx_top_llm_rx_dllp_crc_new_c32_1_i_0_0_) + ); + defparam com_llm_llm_rx_top_llm_rx_dllp_crc_llm_rx_crc16_d32_nst_new_c32_nst_i_15_.INIT = 16'h9669; + LUT4_L com_llm_llm_rx_top_llm_rx_dllp_crc_llm_rx_crc16_d32_nst_new_c32_nst_i_15_ ( + .I0(N_179), + .I1(G_280_549), + .I2(com_llm_llm_rx_top_llm_rx_dllp_crc_llm_rx_crc16_d32_nst_new_c32_1_2_15__2634), + .I3(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_36_), + .LO(com_llm_llm_rx_top_llm_rx_dllp_crc_new_c32_nst_i_15_) + ); + defparam com_llm_llm_rx_top_llm_rx_dllp_crc_llm_rx_crc16_d32_nst_new_c32_nst_i_14_.INIT = 16'h9669; + LUT4_L com_llm_llm_rx_top_llm_rx_dllp_crc_llm_rx_crc16_d32_nst_new_c32_nst_i_14_ ( + .I0(N_180), + .I1(G_440_432), + .I2(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_25_), + .I3(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_29_), + .LO(com_llm_llm_rx_top_llm_rx_dllp_crc_new_c32_nst_i_14_) + ); + defparam com_llm_llm_rx_top_llm_rx_dllp_crc_llm_rx_crc16_d32_nst_new_c32_1_13_.INIT = 8'h96; + LUT3_L com_llm_llm_rx_top_llm_rx_dllp_crc_llm_rx_crc16_d32_nst_new_c32_1_13_ ( + .I0(G_222_592), + .I1(G_513_420), + .I2(com_llm_llm_rx_top_llm_rx_dllp_crc_llm_rx_crc16_d32_nst_new_c32_1_1_13__2635), + .LO(com_llm_llm_rx_top_llm_rx_dllp_crc_new_c32_1_i_0_13_) + ); + defparam com_llm_llm_rx_top_llm_rx_dllp_crc_llm_rx_crc16_d32_nst_new_c32_1_12_.INIT = 16'h6996; + LUT4_L com_llm_llm_rx_top_llm_rx_dllp_crc_llm_rx_crc16_d32_nst_new_c32_1_12_ ( + .I0(N_179), + .I1(G_316_595), + .I2(com_llm_llm_rx_top_llm_rx_dllp_crc_llm_rx_crc16_d32_nst_new_c32_1_0_12__2636), + .I3(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_36_), + .LO(com_llm_llm_rx_top_llm_rx_dllp_crc_new_c32_1_i_0_12_) + ); + defparam com_llm_llm_rx_top_llm_rx_dllp_crc_llm_rx_crc16_d32_nst_new_c32_nst_i_11_.INIT = 16'h9669; + LUT4_L com_llm_llm_rx_top_llm_rx_dllp_crc_llm_rx_crc16_d32_nst_new_c32_nst_i_11_ ( + .I0(N_197), + .I1(G_440_432), + .I2(com_llm_llm_rx_top_llm_rx_dllp_crc_llm_rx_crc16_d32_nst_new_c32_1_1_11__2637), + .I3(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_37_), + .LO(com_llm_llm_rx_top_llm_rx_dllp_crc_new_c32_nst_i_11_) + ); + defparam com_llm_llm_rx_top_llm_rx_dllp_crc_llm_rx_crc16_d32_nst_new_c32_nst_i_10_.INIT = 16'h9669; + LUT4_L com_llm_llm_rx_top_llm_rx_dllp_crc_llm_rx_crc16_d32_nst_new_c32_nst_i_10_ ( + .I0(N_179), + .I1(N_219), + .I2(N_31577_i_0), + .I3(com_llm_llm_rx_top_llm_rx_dllp_crc_llm_rx_crc16_d32_nst_new_c32_1_2_10__2638), + .LO(com_llm_llm_rx_top_llm_rx_dllp_crc_new_c32_nst_i_10_) + ); + defparam com_llm_llm_rx_top_llm_rx_dllp_crc_llm_rx_crc16_d32_nst_new_c32_1_9_.INIT = 16'h6996; + LUT4_L com_llm_llm_rx_top_llm_rx_dllp_crc_llm_rx_crc16_d32_nst_new_c32_1_9_ ( + .I0(N_197), + .I1(com_llm_llm_rx_top_llm_rx_dllp_crc_llm_rx_crc16_d32_nst_new_c32_1_1_9__2639), + .I2(com_llm_llm_rx_top_llm_rx_dllp_crc_llm_rx_crc16_d32_nst_new_c32_1_i_1[4]), + .I3(com_llm_llm_rx_top_llm_rx_dllp_crc_rx_data_q_39_), + .LO(com_llm_llm_rx_top_llm_rx_dllp_crc_new_c32_1_i_0_9_) + ); + VCC com_llm_llm_rx_top_llm_rx_dllp_decode_VCC ( + .P(com_llm_llm_rx_top_llm_rx_dllp_decode_VCC_2642) + ); + GND com_llm_llm_rx_top_llm_rx_dllp_decode_GND ( + .G(com_llm_llm_rx_top_llm_rx_dllp_decode_GND_2641) + ); + defparam com_llm_llm_rx_top_llm_rx_dllp_decode_lnk_rfc_vc_n_20_u_i_0_0_0_m3_0_0_.INIT = 8'hB8; + LUT3 com_llm_llm_rx_top_llm_rx_dllp_decode_lnk_rfc_vc_n_20_u_i_0_0_0_m3_0_0_ ( + .I0(com_link_status[1]), + .I1(com_llm_rx_dllp[30]), + .I2(com_llm_rx_dllp[31]), + .O(com_llm_llm_rx_top_llm_rx_dllp_decode_N_56536) + ); + defparam com_llm_llm_rx_top_llm_rx_dllp_decode_link_update_fc_rcv_3_i_0_0_0_0_o2.INIT = 8'h70; + LUT3 com_llm_llm_rx_top_llm_rx_dllp_decode_link_update_fc_rcv_3_i_0_0_0_0_o2 ( + .I0(com_llm_llm_rx_top_rx_dllp[28]), + .I1(com_llm_rx_dllp[29]), + .I2(com_llm_rx_dllp_vld), + .O(com_llm_llm_rx_top_llm_rx_dllp_decode_N_56229_i) + ); + defparam com_llm_llm_rx_top_llm_rx_dllp_decode_link_li1_cpl_rcv_3_0_a2_0_a2_0_a3_0_a2_1_0.INIT = 8'h40; + LUT3 com_llm_llm_rx_top_llm_rx_dllp_decode_link_li1_cpl_rcv_3_0_a2_0_a2_0_a3_0_a2_1_0 ( + .I0(com_llm_llm_rx_top_rx_dllp[28]), + .I1(com_llm_rx_dllp[29]), + .I2(com_llm_rx_dllp_vld), + .O(com_llm_llm_rx_top_llm_rx_dllp_decode_link_li1_cpl_rcv_3_1_0) + ); + defparam com_llm_llm_rx_top_llm_rx_dllp_decode_lnk_rfc_vc_n_20_u_i_0_0_0_o2_0_.INIT = 16'h0001; + LUT4 com_llm_llm_rx_top_llm_rx_dllp_decode_lnk_rfc_vc_n_20_u_i_0_0_0_o2_0_ ( + .I0(com_llm_llm_rx_top_rx_dllp[24]), + .I1(com_llm_llm_rx_top_rx_dllp[25]), + .I2(com_llm_llm_rx_top_rx_dllp[26]), + .I3(com_llm_llm_rx_top_rx_dllp[27]), + .O(com_llm_N_56326_i) + ); + defparam com_llm_llm_rx_top_llm_rx_dllp_decode_cmml_rpm_ra_3_0_a2_0_a2_0_a3_0_a2_1_0.INIT = 16'h0002; + LUT4_L com_llm_llm_rx_top_llm_rx_dllp_decode_cmml_rpm_ra_3_0_a2_0_a2_0_a3_0_a2_1_0 ( + .I0(com_llm_llm_rx_top_llm_rx_dllp_decode_link_li1_cpl_rcv_3_1_0), + .I1(com_llm_llm_rx_top_rx_dllp[24]), + .I2(com_llm_llm_rx_top_rx_dllp[25]), + .I3(com_llm_llm_rx_top_rx_dllp[27]), + .LO(com_llm_llm_rx_top_llm_rx_dllp_decode_cmml_rpm_ra_3_0_a2_0_a2_0_a3_0_a2_1) + ); + defparam com_llm_llm_rx_top_llm_rx_dllp_decode_link_update_fc_rcv_3_i_0_0_0_0.INIT = 8'h20; + LUT3_L com_llm_llm_rx_top_llm_rx_dllp_decode_link_update_fc_rcv_3_i_0_0_0_0 ( + .I0(com_llm_llm_rx_top_llm_rx_dllp_decode_N_56229_i), + .I1(com_llm_rx_dllp[30]), + .I2(com_llm_rx_dllp[31]), + .LO(com_llm_llm_rx_top_llm_rx_dllp_decode_N_16043_i) + ); + defparam com_llm_llm_rx_top_llm_rx_dllp_decode_cmml_rpm_ra_3_0_a2_0_a2_0_a3_0_a2.INIT = 16'h0008; + LUT4_L com_llm_llm_rx_top_llm_rx_dllp_decode_cmml_rpm_ra_3_0_a2_0_a2_0_a3_0_a2 ( + .I0(com_llm_llm_rx_top_llm_rx_dllp_decode_cmml_rpm_ra_3_0_a2_0_a2_0_a3_0_a2_1), + .I1(com_llm_llm_rx_top_rx_dllp[26]), + .I2(com_llm_rx_dllp[30]), + .I3(com_llm_rx_dllp[31]), + .LO(com_llm_llm_rx_top_llm_rx_dllp_decode_cmml_rpm_ra_3) + ); + defparam com_llm_llm_rx_top_llm_rx_dllp_decode_link_li2_rcv_3_i_0_0_0.INIT = 8'h80; + LUT3_L com_llm_llm_rx_top_llm_rx_dllp_decode_link_li2_rcv_3_i_0_0_0 ( + .I0(com_llm_llm_rx_top_llm_rx_dllp_decode_N_56229_i), + .I1(com_llm_rx_dllp[30]), + .I2(com_llm_rx_dllp[31]), + .LO(com_llm_llm_rx_top_llm_rx_dllp_decode_N_16048_i) + ); + defparam com_llm_llm_rx_top_llm_rx_dllp_decode_link_li1_cpl_rcv_3_0_a2_0_a2_0_a3_0_a2.INIT = 4'h8; + LUT2_L com_llm_llm_rx_top_llm_rx_dllp_decode_link_li1_cpl_rcv_3_0_a2_0_a2_0_a3_0_a2 ( + .I0(com_llm_llm_rx_top_llm_rx_dllp_decode_link_li1_cpl_rcv_3_1_0), + .I1(com_llm_rx_dllp[30]), + .LO(com_llm_llm_rx_top_llm_rx_dllp_decode_link_li1_cpl_rcv_3) + ); + defparam com_llm_llm_rx_top_llm_rx_dllp_decode_link_li1_np_rcv_3_0_a2_0_a2_0_a2_0_a2.INIT = 16'h2000; + LUT4_L com_llm_llm_rx_top_llm_rx_dllp_decode_link_li1_np_rcv_3_0_a2_0_a2_0_a2_0_a2 ( + .I0(com_llm_llm_rx_top_rx_dllp[28]), + .I1(com_llm_rx_dllp[29]), + .I2(com_llm_rx_dllp[30]), + .I3(com_llm_rx_dllp_vld), + .LO(com_llm_llm_rx_top_llm_rx_dllp_decode_link_li1_np_rcv_3) + ); + defparam com_llm_llm_rx_top_llm_rx_dllp_decode_link_li1_p_rcv_3_0_a2_0_a2_0_a2_0_a2.INIT = 16'h1000; + LUT4_L com_llm_llm_rx_top_llm_rx_dllp_decode_link_li1_p_rcv_3_0_a2_0_a2_0_a2_0_a2 ( + .I0(com_llm_llm_rx_top_rx_dllp[28]), + .I1(com_llm_rx_dllp[29]), + .I2(com_llm_rx_dllp[30]), + .I3(com_llm_rx_dllp_vld), + .LO(com_llm_llm_rx_top_llm_rx_dllp_decode_link_li1_p_rcv_3) + ); + defparam com_llm_llm_rx_top_llm_rx_dllp_decode_reg_rx_dllp_nak_vld_0_a2_0_a2_0_a3_0_a2.INIT = 8'h80; + LUT3_L com_llm_llm_rx_top_llm_rx_dllp_decode_reg_rx_dllp_nak_vld_0_a2_0_a2_0_a3_0_a2 ( + .I0(com_llm_N_56326_i), + .I1(com_llm_ANSeqNum_Eq_AckdSeq_5_0_a2_0_a2_0_a3_0_a2_1_0_0), + .I2(com_llm_llm_rx_top_rx_dllp[28]), + .LO(com_llm_reg_rx_dllp_nak_vld) + ); + defparam com_llm_llm_rx_top_llm_rx_dllp_decode_reg_rx_dllp_ack_vld_0_a2_0_a2_0_a3_0_a2.INIT = 8'h08; + LUT3_L com_llm_llm_rx_top_llm_rx_dllp_decode_reg_rx_dllp_ack_vld_0_a2_0_a2_0_a3_0_a2 ( + .I0(com_llm_N_56326_i), + .I1(com_llm_ANSeqNum_Eq_AckdSeq_5_0_a2_0_a2_0_a3_0_a2_1_0_0), + .I2(com_llm_llm_rx_top_rx_dllp[28]), + .LO(com_llm_reg_rx_dllp_ack_vld) + ); + defparam com_llm_llm_rx_top_llm_rx_dllp_decode_N_85888_i.INIT = 8'h7F; + LUT3_L com_llm_llm_rx_top_llm_rx_dllp_decode_N_85888_i ( + .I0(com_llm_llm_rx_top_llm_rx_dllp_decode_N_56229_i), + .I1(com_llm_N_56326_i), + .I2(com_llm_llm_rx_top_llm_rx_dllp_decode_N_56536), + .LO(com_llm_llm_rx_top_llm_rx_dllp_decode_N_85888_i_2640) + ); + FD com_llm_llm_rx_top_llm_rx_dllp_decode_lnk_rfc_header_6_DOUT_0_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_dllp_decode_lnk_rfc_header_6_N_6), + .Q(com_lnk_rfc_header[7]) + ); + FD com_llm_llm_rx_top_llm_rx_dllp_decode_lnk_rfc_header_5_DOUT_0_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_dllp_decode_lnk_rfc_header_5_N_6), + .Q(com_lnk_rfc_header[6]) + ); + FD com_llm_llm_rx_top_llm_rx_dllp_decode_lnk_rfc_header_4_DOUT_0_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_dllp_decode_lnk_rfc_header_4_N_6), + .Q(com_lnk_rfc_header[5]) + ); + FD com_llm_llm_rx_top_llm_rx_dllp_decode_lnk_rfc_header_3_DOUT_0_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_dllp_decode_lnk_rfc_header_3_N_6), + .Q(com_lnk_rfc_header[4]) + ); + FD com_llm_llm_rx_top_llm_rx_dllp_decode_lnk_rfc_header_2_DOUT_0_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_dllp_decode_lnk_rfc_header_2_N_6), + .Q(com_lnk_rfc_header[3]) + ); + FD com_llm_llm_rx_top_llm_rx_dllp_decode_lnk_rfc_header_1_DOUT_0_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_dllp_decode_lnk_rfc_header_1_N_6), + .Q(com_lnk_rfc_header[2]) + ); + FD com_llm_llm_rx_top_llm_rx_dllp_decode_lnk_rfc_header_0_DOUT_0_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_dllp_decode_lnk_rfc_header_0_N_6), + .Q(com_lnk_rfc_header[1]) + ); + FD com_llm_llm_rx_top_llm_rx_dllp_decode_lnk_rfc_header_DOUT_0_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_dllp_decode_lnk_rfc_header_N_6), + .Q(com_lnk_rfc_header[0]) + ); + FDC com_llm_llm_rx_top_llm_rx_dllp_decode_link_update_fc_rcv ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_dllp_decode_N_16043_i), + .Q(com_llm_link_update_fc_rcv), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_dllp_decode_cmml_rpm_ra ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_dllp_decode_cmml_rpm_ra_3), + .Q(com_cmml_rpm_ra), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_dllp_decode_link_li2_rcv ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_dllp_decode_N_16048_i), + .Q(com_llm_link_li2_rcv), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_dllp_decode_link_li1_cpl_rcv ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_dllp_decode_link_li1_cpl_rcv_3), + .Q(com_llm_link_li1_cpl_rcv), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_dllp_decode_link_li1_np_rcv ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_dllp_decode_link_li1_np_rcv_3), + .Q(com_llm_link_li1_np_rcv), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_dllp_decode_link_li1_p_rcv ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_dllp_decode_link_li1_p_rcv_3), + .Q(com_llm_link_li1_p_rcv), + .CLR(plm_link_up_i) + ); + FD com_llm_llm_rx_top_llm_rx_dllp_decode_lnk_rfc_data_8_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_reg_rx_dllp_tsn[8]), + .Q(com_lnk_rfc_data[8]) + ); + FD com_llm_llm_rx_top_llm_rx_dllp_decode_lnk_rfc_data_7_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_reg_rx_dllp_tsn[7]), + .Q(com_lnk_rfc_data[7]) + ); + FD com_llm_llm_rx_top_llm_rx_dllp_decode_lnk_rfc_data_6_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_reg_rx_dllp_tsn[6]), + .Q(com_lnk_rfc_data[6]) + ); + FD com_llm_llm_rx_top_llm_rx_dllp_decode_lnk_rfc_data_5_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_reg_rx_dllp_tsn[5]), + .Q(com_lnk_rfc_data[5]) + ); + FD com_llm_llm_rx_top_llm_rx_dllp_decode_lnk_rfc_data_4_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_reg_rx_dllp_tsn[4]), + .Q(com_lnk_rfc_data[4]) + ); + FD com_llm_llm_rx_top_llm_rx_dllp_decode_lnk_rfc_data_3_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_reg_rx_dllp_tsn[3]), + .Q(com_lnk_rfc_data[3]) + ); + FD com_llm_llm_rx_top_llm_rx_dllp_decode_lnk_rfc_data_2_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_reg_rx_dllp_tsn[2]), + .Q(com_lnk_rfc_data[2]) + ); + FD com_llm_llm_rx_top_llm_rx_dllp_decode_lnk_rfc_data_1_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_reg_rx_dllp_tsn[1]), + .Q(com_lnk_rfc_data[1]) + ); + FD com_llm_llm_rx_top_llm_rx_dllp_decode_lnk_rfc_data_0_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_reg_rx_dllp_tsn[0]), + .Q(com_lnk_rfc_data[0]) + ); + FDP com_llm_llm_rx_top_llm_rx_dllp_decode_lnk_rfc_vc_n_0_ ( + .PRE(plm_link_up_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_dllp_decode_N_85888_i_2640), + .Q(com_lnk_rfc_vc_n[0]) + ); + FDC com_llm_llm_rx_top_llm_rx_dllp_decode_link_vc_rcv_0_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_N_56326_i), + .Q(com_llm_link_vc_rcv[0]), + .CLR(plm_link_up_i) + ); + FD com_llm_llm_rx_top_llm_rx_dllp_decode_lnk_rfc_type_2_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_rx_dllp[30]), + .Q(com_lnk_rfc_type[2]) + ); + FD com_llm_llm_rx_top_llm_rx_dllp_decode_lnk_rfc_type_1_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_rx_dllp[29]), + .Q(com_lnk_rfc_type[1]) + ); + FD com_llm_llm_rx_top_llm_rx_dllp_decode_lnk_rfc_type_0_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_rx_dllp[28]), + .Q(com_lnk_rfc_type[0]) + ); + FD com_llm_llm_rx_top_llm_rx_dllp_decode_lnk_rfc_data_11_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_reg_rx_dllp_tsn[11]), + .Q(com_lnk_rfc_data[11]) + ); + FD com_llm_llm_rx_top_llm_rx_dllp_decode_lnk_rfc_data_10_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_reg_rx_dllp_tsn[10]), + .Q(com_lnk_rfc_data[10]) + ); + FD com_llm_llm_rx_top_llm_rx_dllp_decode_lnk_rfc_data_9_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_reg_rx_dllp_tsn[9]), + .Q(com_lnk_rfc_data[9]) + ); + SRL16 com_llm_llm_rx_top_llm_rx_dllp_decode_lnk_rfc_header_6_I_1 ( + .D(com_llm_llm_rx_top_rx_dllp_d_4_i_m2_i_m3_0_21_), + .Q(com_llm_llm_rx_top_llm_rx_dllp_decode_lnk_rfc_header_6_N_6), + .CLK(NlwRenamedSig_OI_trn_clk), + .A0(com_llm_llm_rx_top_llm_rx_dllp_decode_VCC_2642), + .A1(com_llm_llm_rx_top_llm_rx_dllp_decode_GND_2641), + .A2(com_llm_llm_rx_top_llm_rx_dllp_decode_GND_2641), + .A3(com_llm_llm_rx_top_llm_rx_dllp_decode_GND_2641) + ); + SRL16 com_llm_llm_rx_top_llm_rx_dllp_decode_lnk_rfc_header_5_I_1 ( + .D(com_llm_llm_rx_top_rx_dllp_d_4_i_m2_i_m3_0_20_), + .Q(com_llm_llm_rx_top_llm_rx_dllp_decode_lnk_rfc_header_5_N_6), + .CLK(NlwRenamedSig_OI_trn_clk), + .A0(com_llm_llm_rx_top_llm_rx_dllp_decode_VCC_2642), + .A1(com_llm_llm_rx_top_llm_rx_dllp_decode_GND_2641), + .A2(com_llm_llm_rx_top_llm_rx_dllp_decode_GND_2641), + .A3(com_llm_llm_rx_top_llm_rx_dllp_decode_GND_2641) + ); + SRL16 com_llm_llm_rx_top_llm_rx_dllp_decode_lnk_rfc_header_4_I_1 ( + .D(com_llm_llm_rx_top_rx_dllp_d_4_i_m2_i_m3_0_19_), + .Q(com_llm_llm_rx_top_llm_rx_dllp_decode_lnk_rfc_header_4_N_6), + .CLK(NlwRenamedSig_OI_trn_clk), + .A0(com_llm_llm_rx_top_llm_rx_dllp_decode_VCC_2642), + .A1(com_llm_llm_rx_top_llm_rx_dllp_decode_GND_2641), + .A2(com_llm_llm_rx_top_llm_rx_dllp_decode_GND_2641), + .A3(com_llm_llm_rx_top_llm_rx_dllp_decode_GND_2641) + ); + SRL16 com_llm_llm_rx_top_llm_rx_dllp_decode_lnk_rfc_header_3_I_1 ( + .D(com_llm_llm_rx_top_rx_dllp_d_4_i_m2_i_m3_0_18_), + .Q(com_llm_llm_rx_top_llm_rx_dllp_decode_lnk_rfc_header_3_N_6), + .CLK(NlwRenamedSig_OI_trn_clk), + .A0(com_llm_llm_rx_top_llm_rx_dllp_decode_VCC_2642), + .A1(com_llm_llm_rx_top_llm_rx_dllp_decode_GND_2641), + .A2(com_llm_llm_rx_top_llm_rx_dllp_decode_GND_2641), + .A3(com_llm_llm_rx_top_llm_rx_dllp_decode_GND_2641) + ); + SRL16 com_llm_llm_rx_top_llm_rx_dllp_decode_lnk_rfc_header_2_I_1 ( + .D(com_llm_llm_rx_top_rx_dllp_d_4_i_m3_0_17_), + .Q(com_llm_llm_rx_top_llm_rx_dllp_decode_lnk_rfc_header_2_N_6), + .CLK(NlwRenamedSig_OI_trn_clk), + .A0(com_llm_llm_rx_top_llm_rx_dllp_decode_VCC_2642), + .A1(com_llm_llm_rx_top_llm_rx_dllp_decode_GND_2641), + .A2(com_llm_llm_rx_top_llm_rx_dllp_decode_GND_2641), + .A3(com_llm_llm_rx_top_llm_rx_dllp_decode_GND_2641) + ); + SRL16 com_llm_llm_rx_top_llm_rx_dllp_decode_lnk_rfc_header_1_I_1 ( + .D(com_llm_llm_rx_top_rx_dllp_d_4_i_m2_i_m3_0_16_), + .Q(com_llm_llm_rx_top_llm_rx_dllp_decode_lnk_rfc_header_1_N_6), + .CLK(NlwRenamedSig_OI_trn_clk), + .A0(com_llm_llm_rx_top_llm_rx_dllp_decode_VCC_2642), + .A1(com_llm_llm_rx_top_llm_rx_dllp_decode_GND_2641), + .A2(com_llm_llm_rx_top_llm_rx_dllp_decode_GND_2641), + .A3(com_llm_llm_rx_top_llm_rx_dllp_decode_GND_2641) + ); + SRL16 com_llm_llm_rx_top_llm_rx_dllp_decode_lnk_rfc_header_0_I_1 ( + .D(com_llm_llm_rx_top_rx_dllp_d_4_i_m3_0_15_), + .Q(com_llm_llm_rx_top_llm_rx_dllp_decode_lnk_rfc_header_0_N_6), + .CLK(NlwRenamedSig_OI_trn_clk), + .A0(com_llm_llm_rx_top_llm_rx_dllp_decode_VCC_2642), + .A1(com_llm_llm_rx_top_llm_rx_dllp_decode_GND_2641), + .A2(com_llm_llm_rx_top_llm_rx_dllp_decode_GND_2641), + .A3(com_llm_llm_rx_top_llm_rx_dllp_decode_GND_2641) + ); + SRL16 com_llm_llm_rx_top_llm_rx_dllp_decode_lnk_rfc_header_I_1 ( + .D(com_llm_llm_rx_top_rx_dllp_d_4_i_m3_0_14_), + .Q(com_llm_llm_rx_top_llm_rx_dllp_decode_lnk_rfc_header_N_6), + .CLK(NlwRenamedSig_OI_trn_clk), + .A0(com_llm_llm_rx_top_llm_rx_dllp_decode_VCC_2642), + .A1(com_llm_llm_rx_top_llm_rx_dllp_decode_GND_2641), + .A2(com_llm_llm_rx_top_llm_rx_dllp_decode_GND_2641), + .A3(com_llm_llm_rx_top_llm_rx_dllp_decode_GND_2641) + ); + VCC com_llm_llm_rx_top_llm_rx_tlp_crc_VCC ( + .P(com_llm_llm_rx_top_llm_rx_tlp_crc_VCC_2650) + ); + GND com_llm_llm_rx_top_llm_rx_tlp_crc_GND ( + .G(com_llm_llm_rx_top_llm_rx_tlp_crc_GND_2664) + ); + MUXCY_L com_llm_llm_rx_top_llm_rx_tlp_crc_un4_crc32_com_ok_0_I_1 ( + .CI(com_llm_llm_rx_top_llm_rx_tlp_crc_VCC_2650), + .DI(com_llm_llm_rx_top_llm_rx_tlp_crc_GND_2664), + .LO(com_llm_llm_rx_top_llm_rx_tlp_crc_data_tmp_0[0]), + .S(com_llm_llm_rx_top_llm_rx_tlp_crc_N_123) + ); + MUXCY_L com_llm_llm_rx_top_llm_rx_tlp_crc_un4_crc32_com_ok_0_I_10 ( + .CI(com_llm_llm_rx_top_llm_rx_tlp_crc_data_tmp_0[0]), + .DI(com_llm_llm_rx_top_llm_rx_tlp_crc_GND_2664), + .LO(com_llm_llm_rx_top_llm_rx_tlp_crc_data_tmp_0[1]), + .S(com_llm_llm_rx_top_llm_rx_tlp_crc_N_115) + ); + MUXCY_L com_llm_llm_rx_top_llm_rx_tlp_crc_un4_crc32_com_ok_0_I_19 ( + .CI(com_llm_llm_rx_top_llm_rx_tlp_crc_data_tmp_0[1]), + .DI(com_llm_llm_rx_top_llm_rx_tlp_crc_GND_2664), + .LO(com_llm_llm_rx_top_llm_rx_tlp_crc_data_tmp_0[2]), + .S(com_llm_llm_rx_top_llm_rx_tlp_crc_N_107) + ); + MUXCY_L com_llm_llm_rx_top_llm_rx_tlp_crc_un4_crc32_com_ok_0_I_37 ( + .CI(com_llm_llm_rx_top_llm_rx_tlp_crc_data_tmp_0[10]), + .DI(com_llm_llm_rx_top_llm_rx_tlp_crc_GND_2664), + .LO(com_llm_llm_rx_top_llm_rx_tlp_crc_data_tmp_0[11]), + .S(com_llm_llm_rx_top_llm_rx_tlp_crc_N_91) + ); + MUXCY_L com_llm_llm_rx_top_llm_rx_tlp_crc_un4_crc32_com_ok_0_I_46 ( + .CI(com_llm_llm_rx_top_llm_rx_tlp_crc_data_tmp_0[4]), + .DI(com_llm_llm_rx_top_llm_rx_tlp_crc_GND_2664), + .LO(com_llm_llm_rx_top_llm_rx_tlp_crc_data_tmp_0[5]), + .S(com_llm_llm_rx_top_llm_rx_tlp_crc_N_83) + ); + MUXCY_L com_llm_llm_rx_top_llm_rx_tlp_crc_un4_crc32_com_ok_0_I_55 ( + .CI(com_llm_llm_rx_top_llm_rx_tlp_crc_data_tmp_0[5]), + .DI(com_llm_llm_rx_top_llm_rx_tlp_crc_GND_2664), + .LO(com_llm_llm_rx_top_llm_rx_tlp_crc_data_tmp_0[6]), + .S(com_llm_llm_rx_top_llm_rx_tlp_crc_N_75) + ); + MUXCY_L com_llm_llm_rx_top_llm_rx_tlp_crc_un4_crc32_com_ok_0_I_64 ( + .CI(com_llm_llm_rx_top_llm_rx_tlp_crc_data_tmp_0[11]), + .DI(com_llm_llm_rx_top_llm_rx_tlp_crc_GND_2664), + .LO(com_llm_llm_rx_top_llm_rx_tlp_crc_data_tmp_0[12]), + .S(com_llm_llm_rx_top_llm_rx_tlp_crc_N_67) + ); + MUXCY_L com_llm_llm_rx_top_llm_rx_tlp_crc_un4_crc32_com_ok_0_I_73 ( + .CI(com_llm_llm_rx_top_llm_rx_tlp_crc_data_tmp_0[6]), + .DI(com_llm_llm_rx_top_llm_rx_tlp_crc_GND_2664), + .LO(com_llm_llm_rx_top_llm_rx_tlp_crc_data_tmp_0[7]), + .S(com_llm_llm_rx_top_llm_rx_tlp_crc_N_59) + ); + MUXCY_L com_llm_llm_rx_top_llm_rx_tlp_crc_un4_crc32_com_ok_0_I_82 ( + .CI(com_llm_llm_rx_top_llm_rx_tlp_crc_data_tmp_0[8]), + .DI(com_llm_llm_rx_top_llm_rx_tlp_crc_GND_2664), + .LO(com_llm_llm_rx_top_llm_rx_tlp_crc_data_tmp_0[9]), + .S(com_llm_llm_rx_top_llm_rx_tlp_crc_N_51) + ); + MUXCY_L com_llm_llm_rx_top_llm_rx_tlp_crc_un4_crc32_com_ok_0_I_91 ( + .CI(com_llm_llm_rx_top_llm_rx_tlp_crc_data_tmp_0[9]), + .DI(com_llm_llm_rx_top_llm_rx_tlp_crc_GND_2664), + .LO(com_llm_llm_rx_top_llm_rx_tlp_crc_data_tmp_0[10]), + .S(com_llm_llm_rx_top_llm_rx_tlp_crc_N_43) + ); + MUXCY_L com_llm_llm_rx_top_llm_rx_tlp_crc_un4_crc32_com_ok_0_I_100 ( + .CI(com_llm_llm_rx_top_llm_rx_tlp_crc_data_tmp_0[7]), + .DI(com_llm_llm_rx_top_llm_rx_tlp_crc_GND_2664), + .LO(com_llm_llm_rx_top_llm_rx_tlp_crc_data_tmp_0[8]), + .S(com_llm_llm_rx_top_llm_rx_tlp_crc_N_35) + ); + MUXCY_L com_llm_llm_rx_top_llm_rx_tlp_crc_un4_crc32_com_ok_0_I_109 ( + .CI(com_llm_llm_rx_top_llm_rx_tlp_crc_data_tmp_0[2]), + .DI(com_llm_llm_rx_top_llm_rx_tlp_crc_GND_2664), + .LO(com_llm_llm_rx_top_llm_rx_tlp_crc_data_tmp_0[3]), + .S(com_llm_llm_rx_top_llm_rx_tlp_crc_N_27) + ); + MUXCY_L com_llm_llm_rx_top_llm_rx_tlp_crc_un4_crc32_com_ok_0_I_118 ( + .CI(com_llm_llm_rx_top_llm_rx_tlp_crc_data_tmp_0[12]), + .DI(com_llm_llm_rx_top_llm_rx_tlp_crc_GND_2664), + .LO(com_llm_llm_rx_top_llm_rx_tlp_crc_data_tmp_0[13]), + .S(com_llm_llm_rx_top_llm_rx_tlp_crc_N_19) + ); + MUXCY_L com_llm_llm_rx_top_llm_rx_tlp_crc_un4_crc32_com_ok_0_I_127 ( + .CI(com_llm_llm_rx_top_llm_rx_tlp_crc_data_tmp_0[13]), + .DI(com_llm_llm_rx_top_llm_rx_tlp_crc_GND_2664), + .LO(com_llm_llm_rx_top_llm_rx_tlp_crc_data_tmp[14]), + .S(com_llm_llm_rx_top_llm_rx_tlp_crc_N_11) + ); + MUXCY_L com_llm_llm_rx_top_llm_rx_tlp_crc_un4_crc32_com_ok_0_I_136 ( + .CI(com_llm_llm_rx_top_llm_rx_tlp_crc_data_tmp_0[3]), + .DI(com_llm_llm_rx_top_llm_rx_tlp_crc_GND_2664), + .LO(com_llm_llm_rx_top_llm_rx_tlp_crc_data_tmp_0[4]), + .S(com_llm_llm_rx_top_llm_rx_tlp_crc_N_3) + ); + MUXCY_L com_llm_llm_rx_top_llm_rx_tlp_crc_un3_crc32_com_ok_0_I_1 ( + .CI(com_llm_llm_rx_top_llm_rx_tlp_crc_VCC_2650), + .DI(com_llm_llm_rx_top_llm_rx_tlp_crc_GND_2664), + .LO(com_llm_llm_rx_top_llm_rx_tlp_crc_data_tmp[0]), + .S(com_llm_llm_rx_top_llm_rx_tlp_crc_N_123_0) + ); + MUXCY_L com_llm_llm_rx_top_llm_rx_tlp_crc_un3_crc32_com_ok_0_I_10 ( + .CI(com_llm_llm_rx_top_llm_rx_tlp_crc_data_tmp[0]), + .DI(com_llm_llm_rx_top_llm_rx_tlp_crc_GND_2664), + .LO(com_llm_llm_rx_top_llm_rx_tlp_crc_data_tmp[1]), + .S(com_llm_llm_rx_top_llm_rx_tlp_crc_N_115_0) + ); + MUXCY_L com_llm_llm_rx_top_llm_rx_tlp_crc_un3_crc32_com_ok_0_I_19 ( + .CI(com_llm_llm_rx_top_llm_rx_tlp_crc_data_tmp[1]), + .DI(com_llm_llm_rx_top_llm_rx_tlp_crc_GND_2664), + .LO(com_llm_llm_rx_top_llm_rx_tlp_crc_data_tmp[2]), + .S(com_llm_llm_rx_top_llm_rx_tlp_crc_N_107_0) + ); + MUXCY_L com_llm_llm_rx_top_llm_rx_tlp_crc_un3_crc32_com_ok_0_I_37 ( + .CI(com_llm_llm_rx_top_llm_rx_tlp_crc_data_tmp[10]), + .DI(com_llm_llm_rx_top_llm_rx_tlp_crc_GND_2664), + .LO(com_llm_llm_rx_top_llm_rx_tlp_crc_data_tmp[11]), + .S(com_llm_llm_rx_top_llm_rx_tlp_crc_N_91_0) + ); + MUXCY_L com_llm_llm_rx_top_llm_rx_tlp_crc_un3_crc32_com_ok_0_I_46 ( + .CI(com_llm_llm_rx_top_llm_rx_tlp_crc_data_tmp[4]), + .DI(com_llm_llm_rx_top_llm_rx_tlp_crc_GND_2664), + .LO(com_llm_llm_rx_top_llm_rx_tlp_crc_data_tmp[5]), + .S(com_llm_llm_rx_top_llm_rx_tlp_crc_N_83_0) + ); + MUXCY_L com_llm_llm_rx_top_llm_rx_tlp_crc_un3_crc32_com_ok_0_I_55 ( + .CI(com_llm_llm_rx_top_llm_rx_tlp_crc_data_tmp[5]), + .DI(com_llm_llm_rx_top_llm_rx_tlp_crc_GND_2664), + .LO(com_llm_llm_rx_top_llm_rx_tlp_crc_data_tmp[6]), + .S(com_llm_llm_rx_top_llm_rx_tlp_crc_N_75_0) + ); + MUXCY_L com_llm_llm_rx_top_llm_rx_tlp_crc_un3_crc32_com_ok_0_I_64 ( + .CI(com_llm_llm_rx_top_llm_rx_tlp_crc_data_tmp[11]), + .DI(com_llm_llm_rx_top_llm_rx_tlp_crc_GND_2664), + .LO(com_llm_llm_rx_top_llm_rx_tlp_crc_data_tmp[12]), + .S(com_llm_llm_rx_top_llm_rx_tlp_crc_N_67_0) + ); + MUXCY_L com_llm_llm_rx_top_llm_rx_tlp_crc_un3_crc32_com_ok_0_I_73 ( + .CI(com_llm_llm_rx_top_llm_rx_tlp_crc_data_tmp[6]), + .DI(com_llm_llm_rx_top_llm_rx_tlp_crc_GND_2664), + .LO(com_llm_llm_rx_top_llm_rx_tlp_crc_data_tmp[7]), + .S(com_llm_llm_rx_top_llm_rx_tlp_crc_N_59_0) + ); + MUXCY_L com_llm_llm_rx_top_llm_rx_tlp_crc_un3_crc32_com_ok_0_I_82 ( + .CI(com_llm_llm_rx_top_llm_rx_tlp_crc_data_tmp[8]), + .DI(com_llm_llm_rx_top_llm_rx_tlp_crc_GND_2664), + .LO(com_llm_llm_rx_top_llm_rx_tlp_crc_data_tmp[9]), + .S(com_llm_llm_rx_top_llm_rx_tlp_crc_N_51_0) + ); + MUXCY_L com_llm_llm_rx_top_llm_rx_tlp_crc_un3_crc32_com_ok_0_I_91 ( + .CI(com_llm_llm_rx_top_llm_rx_tlp_crc_data_tmp[9]), + .DI(com_llm_llm_rx_top_llm_rx_tlp_crc_GND_2664), + .LO(com_llm_llm_rx_top_llm_rx_tlp_crc_data_tmp[10]), + .S(com_llm_llm_rx_top_llm_rx_tlp_crc_N_43_0) + ); + MUXCY_L com_llm_llm_rx_top_llm_rx_tlp_crc_un3_crc32_com_ok_0_I_100 ( + .CI(com_llm_llm_rx_top_llm_rx_tlp_crc_data_tmp[7]), + .DI(com_llm_llm_rx_top_llm_rx_tlp_crc_GND_2664), + .LO(com_llm_llm_rx_top_llm_rx_tlp_crc_data_tmp[8]), + .S(com_llm_llm_rx_top_llm_rx_tlp_crc_N_35_0) + ); + MUXCY_L com_llm_llm_rx_top_llm_rx_tlp_crc_un3_crc32_com_ok_0_I_109 ( + .CI(com_llm_llm_rx_top_llm_rx_tlp_crc_data_tmp[2]), + .DI(com_llm_llm_rx_top_llm_rx_tlp_crc_GND_2664), + .LO(com_llm_llm_rx_top_llm_rx_tlp_crc_data_tmp[3]), + .S(com_llm_llm_rx_top_llm_rx_tlp_crc_N_27_0) + ); + MUXCY_L com_llm_llm_rx_top_llm_rx_tlp_crc_un3_crc32_com_ok_0_I_118 ( + .CI(com_llm_llm_rx_top_llm_rx_tlp_crc_data_tmp[12]), + .DI(com_llm_llm_rx_top_llm_rx_tlp_crc_GND_2664), + .LO(com_llm_llm_rx_top_llm_rx_tlp_crc_data_tmp[13]), + .S(com_llm_llm_rx_top_llm_rx_tlp_crc_N_19_0) + ); + MUXCY_L com_llm_llm_rx_top_llm_rx_tlp_crc_un3_crc32_com_ok_0_I_127 ( + .CI(com_llm_llm_rx_top_llm_rx_tlp_crc_data_tmp[13]), + .DI(com_llm_llm_rx_top_llm_rx_tlp_crc_GND_2664), + .LO(com_llm_llm_rx_top_llm_rx_tlp_crc_data_tmp_0[14]), + .S(com_llm_llm_rx_top_llm_rx_tlp_crc_N_11_0) + ); + MUXCY_L com_llm_llm_rx_top_llm_rx_tlp_crc_un3_crc32_com_ok_0_I_136 ( + .CI(com_llm_llm_rx_top_llm_rx_tlp_crc_data_tmp[3]), + .DI(com_llm_llm_rx_top_llm_rx_tlp_crc_GND_2664), + .LO(com_llm_llm_rx_top_llm_rx_tlp_crc_data_tmp[4]), + .S(com_llm_llm_rx_top_llm_rx_tlp_crc_N_3_0) + ); + MUXCY_L com_llm_llm_rx_top_llm_rx_tlp_crc_un6_crc32_res_ok_0 ( + .CI(com_llm_llm_rx_top_llm_rx_tlp_crc_VCC_2650), + .DI(com_llm_llm_rx_top_llm_rx_tlp_crc_GND_2664), + .LO(com_llm_llm_rx_top_llm_rx_tlp_crc_un6_crc32_res_ok_0_2643), + .S(com_llm_llm_rx_top_llm_rx_tlp_crc_un6_crc32_res_ok_0_and) + ); + MUXCY_L com_llm_llm_rx_top_llm_rx_tlp_crc_un6_crc32_res_ok_1 ( + .CI(com_llm_llm_rx_top_llm_rx_tlp_crc_un6_crc32_res_ok_0_2643), + .DI(com_llm_llm_rx_top_llm_rx_tlp_crc_GND_2664), + .LO(com_llm_llm_rx_top_llm_rx_tlp_crc_un6_crc32_res_ok_1_2644), + .S(com_llm_llm_rx_top_llm_rx_tlp_crc_un6_crc32_res_ok_1_and) + ); + MUXCY_L com_llm_llm_rx_top_llm_rx_tlp_crc_un6_crc32_res_ok_2 ( + .CI(com_llm_llm_rx_top_llm_rx_tlp_crc_un6_crc32_res_ok_1_2644), + .DI(com_llm_llm_rx_top_llm_rx_tlp_crc_GND_2664), + .LO(com_llm_llm_rx_top_llm_rx_tlp_crc_un6_crc32_res_ok_2_2645), + .S(com_llm_llm_rx_top_llm_rx_tlp_crc_un6_crc32_res_ok_2_and) + ); + MUXCY_L com_llm_llm_rx_top_llm_rx_tlp_crc_un6_crc32_res_ok_3 ( + .CI(com_llm_llm_rx_top_llm_rx_tlp_crc_un6_crc32_res_ok_2_2645), + .DI(com_llm_llm_rx_top_llm_rx_tlp_crc_GND_2664), + .LO(com_llm_llm_rx_top_llm_rx_tlp_crc_un6_crc32_res_ok_3_2646), + .S(com_llm_llm_rx_top_llm_rx_tlp_crc_un6_crc32_res_ok_3_and) + ); + MUXCY_L com_llm_llm_rx_top_llm_rx_tlp_crc_un6_crc32_res_ok_4 ( + .CI(com_llm_llm_rx_top_llm_rx_tlp_crc_un6_crc32_res_ok_3_2646), + .DI(com_llm_llm_rx_top_llm_rx_tlp_crc_GND_2664), + .LO(com_llm_llm_rx_top_llm_rx_tlp_crc_un6_crc32_res_ok_4_2647), + .S(com_llm_llm_rx_top_llm_rx_tlp_crc_un6_crc32_res_ok_4_and) + ); + MUXCY_L com_llm_llm_rx_top_llm_rx_tlp_crc_un6_crc32_res_ok_5 ( + .CI(com_llm_llm_rx_top_llm_rx_tlp_crc_un6_crc32_res_ok_4_2647), + .DI(com_llm_llm_rx_top_llm_rx_tlp_crc_GND_2664), + .LO(com_llm_llm_rx_top_llm_rx_tlp_crc_un6_crc32_res_ok_5_2648), + .S(com_llm_llm_rx_top_llm_rx_tlp_crc_un6_crc32_res_ok_5_and) + ); + MUXCY_L com_llm_llm_rx_top_llm_rx_tlp_crc_un6_crc32_res_ok_6 ( + .CI(com_llm_llm_rx_top_llm_rx_tlp_crc_un6_crc32_res_ok_5_2648), + .DI(com_llm_llm_rx_top_llm_rx_tlp_crc_GND_2664), + .LO(com_llm_llm_rx_top_llm_rx_tlp_crc_un6_crc32_res_ok_6_2649), + .S(com_llm_llm_rx_top_llm_rx_tlp_crc_un6_crc32_res_ok_6_and) + ); + MUXCY com_llm_llm_rx_top_llm_rx_tlp_crc_un6_crc32_res_ok_7 ( + .CI(com_llm_llm_rx_top_llm_rx_tlp_crc_un6_crc32_res_ok_6_2649), + .DI(com_llm_llm_rx_top_llm_rx_tlp_crc_GND_2664), + .O(com_llm_llm_rx_top_llm_rx_tlp_crc_un6_crc32_res_ok_7_2658), + .S(com_llm_llm_rx_top_llm_rx_tlp_crc_un6_crc32_res_ok_7_and) + ); + MUXCY_L com_llm_llm_rx_top_llm_rx_tlp_crc_un3_crc32_res_ok_0 ( + .CI(com_llm_llm_rx_top_llm_rx_tlp_crc_VCC_2650), + .DI(com_llm_llm_rx_top_llm_rx_tlp_crc_GND_2664), + .LO(com_llm_llm_rx_top_llm_rx_tlp_crc_un3_crc32_res_ok_0_2651), + .S(com_llm_llm_rx_top_llm_rx_tlp_crc_un3_crc32_res_ok_0_and) + ); + MUXCY_L com_llm_llm_rx_top_llm_rx_tlp_crc_un3_crc32_res_ok_1 ( + .CI(com_llm_llm_rx_top_llm_rx_tlp_crc_un3_crc32_res_ok_0_2651), + .DI(com_llm_llm_rx_top_llm_rx_tlp_crc_GND_2664), + .LO(com_llm_llm_rx_top_llm_rx_tlp_crc_un3_crc32_res_ok_1_2652), + .S(com_llm_llm_rx_top_llm_rx_tlp_crc_un3_crc32_res_ok_1_and) + ); + MUXCY_L com_llm_llm_rx_top_llm_rx_tlp_crc_un3_crc32_res_ok_2 ( + .CI(com_llm_llm_rx_top_llm_rx_tlp_crc_un3_crc32_res_ok_1_2652), + .DI(com_llm_llm_rx_top_llm_rx_tlp_crc_GND_2664), + .LO(com_llm_llm_rx_top_llm_rx_tlp_crc_un3_crc32_res_ok_2_2653), + .S(com_llm_llm_rx_top_llm_rx_tlp_crc_un3_crc32_res_ok_2_and) + ); + MUXCY_L com_llm_llm_rx_top_llm_rx_tlp_crc_un3_crc32_res_ok_3 ( + .CI(com_llm_llm_rx_top_llm_rx_tlp_crc_un3_crc32_res_ok_2_2653), + .DI(com_llm_llm_rx_top_llm_rx_tlp_crc_GND_2664), + .LO(com_llm_llm_rx_top_llm_rx_tlp_crc_un3_crc32_res_ok_3_2654), + .S(com_llm_llm_rx_top_llm_rx_tlp_crc_un3_crc32_res_ok_3_and) + ); + MUXCY_L com_llm_llm_rx_top_llm_rx_tlp_crc_un3_crc32_res_ok_4 ( + .CI(com_llm_llm_rx_top_llm_rx_tlp_crc_un3_crc32_res_ok_3_2654), + .DI(com_llm_llm_rx_top_llm_rx_tlp_crc_GND_2664), + .LO(com_llm_llm_rx_top_llm_rx_tlp_crc_un3_crc32_res_ok_4_2655), + .S(com_llm_llm_rx_top_llm_rx_tlp_crc_un3_crc32_res_ok_4_and) + ); + MUXCY_L com_llm_llm_rx_top_llm_rx_tlp_crc_un3_crc32_res_ok_5 ( + .CI(com_llm_llm_rx_top_llm_rx_tlp_crc_un3_crc32_res_ok_4_2655), + .DI(com_llm_llm_rx_top_llm_rx_tlp_crc_GND_2664), + .LO(com_llm_llm_rx_top_llm_rx_tlp_crc_un3_crc32_res_ok_5_2656), + .S(com_llm_llm_rx_top_llm_rx_tlp_crc_un3_crc32_res_ok_5_and) + ); + MUXCY_L com_llm_llm_rx_top_llm_rx_tlp_crc_un3_crc32_res_ok_6 ( + .CI(com_llm_llm_rx_top_llm_rx_tlp_crc_un3_crc32_res_ok_5_2656), + .DI(com_llm_llm_rx_top_llm_rx_tlp_crc_GND_2664), + .LO(com_llm_llm_rx_top_llm_rx_tlp_crc_un3_crc32_res_ok_6_2657), + .S(com_llm_llm_rx_top_llm_rx_tlp_crc_un3_crc32_res_ok_6_and) + ); + MUXCY com_llm_llm_rx_top_llm_rx_tlp_crc_un3_crc32_res_ok_7 ( + .CI(com_llm_llm_rx_top_llm_rx_tlp_crc_un3_crc32_res_ok_6_2657), + .DI(com_llm_llm_rx_top_llm_rx_tlp_crc_GND_2664), + .O(com_llm_llm_rx_top_llm_rx_tlp_crc_un3_crc32_res_ok_7_2659), + .S(com_llm_llm_rx_top_llm_rx_tlp_crc_un3_crc32_res_ok_7_and) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_c64_0_a2_0_a2_17_.INIT = 4'h1; + LUT2 com_llm_llm_rx_top_llm_rx_tlp_crc_c64_0_a2_0_a2_17_ ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d64_17__471), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_initial_64_97), + .O(c64_0_a2_0_a2_17_) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_rx_tlp_tsn_dd_5_i_o4_0_.INIT = 4'h2; + LUT2 com_llm_llm_rx_top_llm_rx_tlp_crc_rx_tlp_tsn_dd_5_i_o4_0_ ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_tlp_eof_nq_2749), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_tlp_vld_h_nq_2669), + .O(com_llm_llm_rx_top_llm_rx_tlp_crc_N_31558_i) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_rx_tlp_eof_nq6_0_0_o3.INIT = 4'h1; + LUT2 com_llm_llm_rx_top_llm_rx_tlp_crc_rx_tlp_eof_nq6_0_0_o3 ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_tlp_in_progress_2745), + .I1(com_llm_llm_rx_top_rx_tlp_sof_n), + .O(com_llm_llm_rx_top_llm_rx_tlp_crc_N_31569_i) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_un1_tlp_in_progress13_i_x4_0_x4.INIT = 4'h6; + LUT2 com_llm_llm_rx_top_llm_rx_tlp_crc_un1_tlp_in_progress13_i_x4_0_x4 ( + .I0(com_llm_llm_rx_top_rx_tlp_eof_n), + .I1(com_llm_llm_rx_top_rx_tlp_sof_n), + .O(com_llm_llm_rx_top_llm_rx_tlp_crc_N_31582_i_0) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_c64_0_a2_0_a2_1_.INIT = 4'h1; + LUT2 com_llm_llm_rx_top_llm_rx_tlp_crc_c64_0_a2_0_a2_1_ ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d64_1__2739), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_initial_64_97), + .O(c64_0_a2_0_a2_1_) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_c64_0_a2_0_a2_2_.INIT = 4'h1; + LUT2 com_llm_llm_rx_top_llm_rx_tlp_crc_c64_0_a2_0_a2_2_ ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d64_2__2738), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_initial_64_97), + .O(c64_0_a2_0_a2_2_) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_c64_0_a2_0_a2_3_.INIT = 4'h1; + LUT2 com_llm_llm_rx_top_llm_rx_tlp_crc_c64_0_a2_0_a2_3_ ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d64_3__2737), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_initial_64_97), + .O(c64_0_a2_0_a2_3_) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_c64_0_a2_0_a2_5_.INIT = 4'h1; + LUT2 com_llm_llm_rx_top_llm_rx_tlp_crc_c64_0_a2_0_a2_5_ ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d64_5__98), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_initial_64_97), + .O(com_llm_llm_rx_top_llm_rx_tlp_crc_c64_0_a2_0_a2[5]) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_c64_0_a2_0_a2_10_.INIT = 4'h1; + LUT2 com_llm_llm_rx_top_llm_rx_tlp_crc_c64_0_a2_0_a2_10_ ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d64_10__2736), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_initial_64_97), + .O(c64_0_a2_0_a2_10_) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_c64_0_a2_0_a2_23_.INIT = 4'h1; + LUT2 com_llm_llm_rx_top_llm_rx_tlp_crc_c64_0_a2_0_a2_23_ ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d64_23__454), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_initial_64_97), + .O(c64_0_a2_0_a2_23_) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_c64_0_a2_0_a2_26_.INIT = 4'h1; + LUT2 com_llm_llm_rx_top_llm_rx_tlp_crc_c64_0_a2_0_a2_26_ ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d64_26__447), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_initial_64_97), + .O(c64_0_a2_0_a2_26_) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_c64_0_a2_0_a2_27_.INIT = 4'h1; + LUT2 com_llm_llm_rx_top_llm_rx_tlp_crc_c64_0_a2_0_a2_27_ ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d64_27__460), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_initial_64_97), + .O(c64_0_a2_0_a2_27_) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_un1_RX_RSRC_DSC_N17_0_0_o3.INIT = 4'h1; + LUT2 com_llm_llm_rx_top_llm_rx_tlp_crc_un1_RX_RSRC_DSC_N17_0_0_o3 ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_end_low_latch_2742), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_start_high_latch_qq_2670), + .O(com_llm_llm_rx_top_llm_rx_tlp_crc_N_31560_i) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_d16_i_m3_0_3_.INIT = 8'hCA; + LUT3 com_llm_llm_rx_top_llm_rx_tlp_crc_d16_i_m3_0_3_ ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_4__2691), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_36__2713), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_start_high_latch_q_450), + .O(d16_i_m3_0_3_) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_d64_i_m3_0_19_.INIT = 8'hB8; + LUT3 com_llm_llm_rx_top_llm_rx_tlp_crc_d64_i_m3_0_19_ ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_4__2691), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_start_high_latch_452), + .I2(com_llm_llm_rx_top_rx_data_44_), + .O(d64_i_m3_0_19_) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_d64_i_m3_0_23_.INIT = 8'hB8; + LUT3 com_llm_llm_rx_top_llm_rx_tlp_crc_d64_i_m3_0_23_ ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_0__455), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_start_high_latch_452), + .I2(com_llm_llm_rx_top_rx_data_40_), + .O(d64_i_m3_0_23_) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_d64_i_m3_0_51_.INIT = 8'hCA; + LUT3_L com_llm_llm_rx_top_llm_rx_tlp_crc_d64_i_m3_0_51_ ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_4__2691), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_36__2713), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_start_high_latch_452), + .LO(N_31638) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_d64_i_m3_0_55_.INIT = 8'hCA; + LUT3 com_llm_llm_rx_top_llm_rx_tlp_crc_d64_i_m3_0_55_ ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_0__455), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_32__456), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_start_high_latch_452), + .O(d64_i_m3_0_55_) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_d16_i_m3_i_m3_0_0_.INIT = 8'hCA; + LUT3 com_llm_llm_rx_top_llm_rx_tlp_crc_d16_i_m3_i_m3_0_0_ ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_7__2689), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_39__2711), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_start_high_latch_q_450), + .O(d16_i_m3_i_m3_0_0_) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_d64_i_m3_i_m3_0_48_.INIT = 8'hCA; + LUT3 com_llm_llm_rx_top_llm_rx_tlp_crc_d64_i_m3_i_m3_0_48_ ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_7__2689), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_39__2711), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_start_high_latch_452), + .O(d64_i_m3_i_m3_0_48_) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_d16_i_m3_0_8_.INIT = 8'hCA; + LUT3 com_llm_llm_rx_top_llm_rx_tlp_crc_d16_i_m3_0_8_ ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_15__2684), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_47__2706), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_start_high_latch_q_450), + .O(d16_i_m3_0_8_) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_d64_i_m3_0_24_.INIT = 8'hB8; + LUT3 com_llm_llm_rx_top_llm_rx_tlp_crc_d64_i_m3_0_24_ ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_15__2684), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_start_high_latch_452), + .I2(com_llm_llm_rx_top_rx_data_55_), + .O(d64_i_m3_0_24_) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_d64_i_m3_0_56_.INIT = 8'hCA; + LUT3_L com_llm_llm_rx_top_llm_rx_tlp_crc_d64_i_m3_0_56_ ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_15__2684), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_47__2706), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_start_high_latch_452), + .LO(N_31643) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_d16_i_m3_0_6_.INIT = 8'hCA; + LUT3 com_llm_llm_rx_top_llm_rx_tlp_crc_d16_i_m3_0_6_ ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_1__2680), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_33__2692), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_start_high_latch_q_450), + .O(d16_i_m3_0_6_) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_d64_i_m3_0_1_.INIT = 8'hE4; + LUT3 com_llm_llm_rx_top_llm_rx_tlp_crc_d64_i_m3_0_1_ ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_start_high_latch_452), + .I1(com_llm_llm_rx_top_rx_data_30_), + .I2(com_llm_llm_rx_top_rx_data_62_), + .O(d64_i_m3_0_1_) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_d64_i_m3_0_4_.INIT = 8'hE4; + LUT3 com_llm_llm_rx_top_llm_rx_tlp_crc_d64_i_m3_0_4_ ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_start_high_latch_452), + .I1(com_llm_llm_rx_top_rx_data_27_), + .I2(com_llm_llm_rx_top_rx_data_59_), + .O(d64_i_m3_0_4_) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_d64_i_m3_0_22_.INIT = 8'hB8; + LUT3 com_llm_llm_rx_top_llm_rx_tlp_crc_d64_i_m3_0_22_ ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_1__2680), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_start_high_latch_452), + .I2(com_llm_llm_rx_top_rx_data_41_), + .O(d64_i_m3_0_22_) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_d64_i_m3_0_33_.INIT = 8'hB8; + LUT3 com_llm_llm_rx_top_llm_rx_tlp_crc_d64_i_m3_0_33_ ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_22__2702), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_start_high_latch_452), + .I2(com_llm_llm_rx_top_rx_data_62_), + .O(d64_i_m3_0_33_) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_d64_i_m2_i_m3_0_36_.INIT = 8'hB8; + LUT3 com_llm_llm_rx_top_llm_rx_tlp_crc_d64_i_m2_i_m3_0_36_ ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_19__2704), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_start_high_latch_452), + .I2(com_llm_llm_rx_top_rx_data_59_), + .O(d64_i_m2_i_m3_0_36_) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_d64_i_m3_0_40_.INIT = 8'hCA; + LUT3_L com_llm_llm_rx_top_llm_rx_tlp_crc_d64_i_m3_0_40_ ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_data_q_7__2714), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_31__2693), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_start_high_latch_452), + .LO(N_31629) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_d64_i_m3_0_53_.INIT = 8'hCA; + LUT3_L com_llm_llm_rx_top_llm_rx_tlp_crc_d64_i_m3_0_53_ ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_2__476), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_34__477), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_start_high_latch_452), + .LO(N_31640) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_d64_i_m2_i_m3_0_32_.INIT = 8'hB8; + LUT3_L com_llm_llm_rx_top_llm_rx_tlp_crc_d64_i_m2_i_m3_0_32_ ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_23__2701), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_start_high_latch_452), + .I2(com_llm_llm_rx_top_rx_data_63_), + .LO(N_31794) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_d64_i_m3_0_7_.INIT = 8'hE4; + LUT3 com_llm_llm_rx_top_llm_rx_tlp_crc_d64_i_m3_0_7_ ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_start_high_latch_452), + .I1(com_llm_llm_rx_top_rx_data_24_), + .I2(com_llm_llm_rx_top_rx_data_56_), + .O(d64_i_m3_0_7_) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_d64_i_m3_0_39_.INIT = 8'hB8; + LUT3 com_llm_llm_rx_top_llm_rx_tlp_crc_d64_i_m3_0_39_ ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_16__2683), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_start_high_latch_452), + .I2(com_llm_llm_rx_top_rx_data_56_), + .O(d64_i_m3_0_39_) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_d64_i_m3_0_9_.INIT = 8'hB8; + LUT3 com_llm_llm_rx_top_llm_rx_tlp_crc_d64_i_m3_0_9_ ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_data_q_6__2716), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_start_high_latch_452), + .I2(com_llm_llm_rx_top_rx_data_38_), + .O(d64_i_m3_0_9_) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_d64_i_m3_0_58_.INIT = 8'hCA; + LUT3 com_llm_llm_rx_top_llm_rx_tlp_crc_d64_i_m3_0_58_ ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_13__448), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_45__449), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_start_high_latch_452), + .O(d64_i_m3_0_58_) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_d64_i_m2_i_m3_0_27_.INIT = 8'hB8; + LUT3 com_llm_llm_rx_top_llm_rx_tlp_crc_d64_i_m2_i_m3_0_27_ ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_12__461), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_start_high_latch_452), + .I2(com_llm_llm_rx_top_rx_data_52_), + .O(d64_i_m2_i_m3_0_27_) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_d64_i_m3_0_28_.INIT = 8'hB8; + LUT3 com_llm_llm_rx_top_llm_rx_tlp_crc_d64_i_m3_0_28_ ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_11__2685), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_start_high_latch_452), + .I2(com_llm_llm_rx_top_rx_data_51_), + .O(d64_i_m3_0_28_) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_d64_i_m3_i_m3_0_60_.INIT = 8'hCA; + LUT3 com_llm_llm_rx_top_llm_rx_tlp_crc_d64_i_m3_i_m3_0_60_ ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_11__2685), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_43__2707), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_start_high_latch_452), + .O(d64_i_m3_i_m3_0_60_) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_d16_i_m3_i_m3_0_15_.INIT = 8'hCA; + LUT3 com_llm_llm_rx_top_llm_rx_tlp_crc_d16_i_m3_i_m3_0_15_ ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_8__2688), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_40__2710), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_start_high_latch_q_450), + .O(d16_i_m3_i_m3_0_15_) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_d64_i_m3_i_m3_0_31_.INIT = 8'hB8; + LUT3 com_llm_llm_rx_top_llm_rx_tlp_crc_d64_i_m3_i_m3_0_31_ ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_8__2688), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_start_high_latch_452), + .I2(com_llm_llm_rx_top_rx_data_48_), + .O(d64_i_m3_i_m3_0_31_) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_d64_i_m3_i_m3_0_63_.INIT = 8'hCA; + LUT3_L com_llm_llm_rx_top_llm_rx_tlp_crc_d64_i_m3_i_m3_0_63_ ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_8__2688), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_40__2710), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_start_high_latch_452), + .LO(N_31762) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_d64_i_m2_i_m3_0_59_.INIT = 8'hCA; + LUT3 com_llm_llm_rx_top_llm_rx_tlp_crc_d64_i_m2_i_m3_0_59_ ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_12__461), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_44__462), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_start_high_latch_452), + .O(d64_i_m2_i_m3_0_59_) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_d64_i_m2_i_m3_0_26_.INIT = 8'hB8; + LUT3 com_llm_llm_rx_top_llm_rx_tlp_crc_d64_i_m2_i_m3_0_26_ ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_13__448), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_start_high_latch_452), + .I2(com_llm_llm_rx_top_rx_data_53_), + .O(d64_i_m2_i_m3_0_26_) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_d64_i_m3_i_m3_0_62_.INIT = 8'hCA; + LUT3_L com_llm_llm_rx_top_llm_rx_tlp_crc_d64_i_m3_i_m3_0_62_ ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_9__2687), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_41__2709), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_start_high_latch_452), + .LO(d64_i_m3_i_m3_0_62_) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_d64_i_m3_i_m3_0_61_.INIT = 8'hCA; + LUT3_L com_llm_llm_rx_top_llm_rx_tlp_crc_d64_i_m3_i_m3_0_61_ ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_10__2686), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_42__2708), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_start_high_latch_452), + .LO(d64_i_m3_i_m3_0_61_) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_d64_i_m3_i_m3_0_49_.INIT = 8'hCA; + LUT3 com_llm_llm_rx_top_llm_rx_tlp_crc_d64_i_m3_i_m3_0_49_ ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_6__472), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_38__473), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_start_high_latch_452), + .O(d64_i_m3_i_m3_0_49_) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_d64_i_m3_i_m3_0_30_.INIT = 8'hB8; + LUT3 com_llm_llm_rx_top_llm_rx_tlp_crc_d64_i_m3_i_m3_0_30_ ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_9__2687), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_start_high_latch_452), + .I2(com_llm_llm_rx_top_rx_data_49_), + .O(d64_i_m3_i_m3_0_30_) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_d16_i_m3_i_m3_0_14_.INIT = 8'hCA; + LUT3 com_llm_llm_rx_top_llm_rx_tlp_crc_d16_i_m3_i_m3_0_14_ ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_9__2687), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_41__2709), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_start_high_latch_q_450), + .O(d16_i_m3_i_m3_0_14_) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_d16_i_m3_i_m3_0_13_.INIT = 8'hCA; + LUT3 com_llm_llm_rx_top_llm_rx_tlp_crc_d16_i_m3_i_m3_0_13_ ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_10__2686), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_42__2708), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_start_high_latch_q_450), + .O(d16_i_m3_i_m3_0_13_) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_d64_i_m3_0_57_.INIT = 8'hCA; + LUT3_L com_llm_llm_rx_top_llm_rx_tlp_crc_d64_i_m3_0_57_ ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_14__469), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_46__470), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_start_high_latch_452), + .LO(d64_i_m3_0_57_) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_d64_i_m3_0_54_.INIT = 8'hCA; + LUT3_L com_llm_llm_rx_top_llm_rx_tlp_crc_d64_i_m3_0_54_ ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_1__2680), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_33__2692), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_start_high_latch_452), + .LO(d64_i_m3_0_54_) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_d64_i_m3_0_52_.INIT = 8'hCA; + LUT3 com_llm_llm_rx_top_llm_rx_tlp_crc_d64_i_m3_0_52_ ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_3__478), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_35__479), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_start_high_latch_452), + .O(d64_i_m3_0_52_) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_d64_i_m3_0_50_.INIT = 8'hCA; + LUT3_L com_llm_llm_rx_top_llm_rx_tlp_crc_d64_i_m3_0_50_ ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_5__2690), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_37__2712), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_start_high_latch_452), + .LO(d64_i_m3_0_50_) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_d64_i_m3_0_47_.INIT = 8'hCA; + LUT3 com_llm_llm_rx_top_llm_rx_tlp_crc_d64_i_m3_0_47_ ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_data_q_0__2727), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_24__2700), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_start_high_latch_452), + .O(d64_i_m3_0_47_) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_d64_i_m3_0_46_.INIT = 8'hCA; + LUT3_L com_llm_llm_rx_top_llm_rx_tlp_crc_d64_i_m3_0_46_ ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_data_q_1__2725), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_25__2699), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_start_high_latch_452), + .LO(d64_i_m3_0_46_) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_d64_i_m3_0_45_.INIT = 8'hCA; + LUT3_L com_llm_llm_rx_top_llm_rx_tlp_crc_d64_i_m3_0_45_ ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_data_q[2]), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_26__2698), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_start_high_latch_452), + .LO(d64_i_m3_0_45_) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_d64_i_m3_0_44_.INIT = 8'hCA; + LUT3_L com_llm_llm_rx_top_llm_rx_tlp_crc_d64_i_m3_0_44_ ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_data_q_3__2722), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_27__2697), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_start_high_latch_452), + .LO(d64_i_m3_0_44_) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_d64_i_m3_0_43_.INIT = 8'hCA; + LUT3_L com_llm_llm_rx_top_llm_rx_tlp_crc_d64_i_m3_0_43_ ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_data_q_4__2720), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_28__2696), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_start_high_latch_452), + .LO(d64_i_m3_0_43_) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_d64_i_m3_0_42_.INIT = 8'hCA; + LUT3 com_llm_llm_rx_top_llm_rx_tlp_crc_d64_i_m3_0_42_ ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_data_q_5__2718), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_29__2695), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_start_high_latch_452), + .O(d64_i_m3_0_42_) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_d64_i_m3_0_41_.INIT = 8'hCA; + LUT3_L com_llm_llm_rx_top_llm_rx_tlp_crc_d64_i_m3_0_41_ ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_data_q_6__2716), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_30__2694), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_start_high_latch_452), + .LO(d64_i_m3_0_41_) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_d64_i_m3_0_38_.INIT = 8'hB8; + LUT3_L com_llm_llm_rx_top_llm_rx_tlp_crc_d64_i_m3_0_38_ ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_17__2682), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_start_high_latch_452), + .I2(com_llm_llm_rx_top_rx_data_57_), + .LO(d64_i_m3_0_38_) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_d64_i_m3_0_37_.INIT = 8'hB8; + LUT3 com_llm_llm_rx_top_llm_rx_tlp_crc_d64_i_m3_0_37_ ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_18__2681), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_start_high_latch_452), + .I2(com_llm_llm_rx_top_rx_data_58_), + .O(d64_i_m3_0_37_) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_d64_i_m3_0_35_.INIT = 8'hB8; + LUT3 com_llm_llm_rx_top_llm_rx_tlp_crc_d64_i_m3_0_35_ ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_20__2703), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_start_high_latch_452), + .I2(com_llm_llm_rx_top_rx_data_60_), + .O(d64_i_m3_0_35_) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_d64_i_m3_0_34_.INIT = 8'hB8; + LUT3 com_llm_llm_rx_top_llm_rx_tlp_crc_d64_i_m3_0_34_ ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_21__451), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_start_high_latch_452), + .I2(com_llm_llm_rx_top_rx_data_61_), + .O(d64_i_m3_0_34_) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_d64_i_m3_0_29_.INIT = 8'hB8; + LUT3 com_llm_llm_rx_top_llm_rx_tlp_crc_d64_i_m3_0_29_ ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_10__2686), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_start_high_latch_452), + .I2(com_llm_llm_rx_top_rx_data_50_), + .O(d64_i_m3_0_29_) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_d64_i_m3_0_25_.INIT = 8'hB8; + LUT3 com_llm_llm_rx_top_llm_rx_tlp_crc_d64_i_m3_0_25_ ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_14__469), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_start_high_latch_452), + .I2(com_llm_llm_rx_top_rx_data_54_), + .O(d64_i_m3_0_25_) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_d64_i_m3_0_20_.INIT = 8'hB8; + LUT3 com_llm_llm_rx_top_llm_rx_tlp_crc_d64_i_m3_0_20_ ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_3__478), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_start_high_latch_452), + .I2(com_llm_llm_rx_top_rx_data_43_), + .O(d64_i_m3_0_20_) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_d64_i_m3_0_18_.INIT = 8'hB8; + LUT3 com_llm_llm_rx_top_llm_rx_tlp_crc_d64_i_m3_0_18_ ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_5__2690), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_start_high_latch_452), + .I2(com_llm_llm_rx_top_rx_data_45_), + .O(d64_i_m3_0_18_) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_d64_i_m3_0_17_.INIT = 8'hB8; + LUT3 com_llm_llm_rx_top_llm_rx_tlp_crc_d64_i_m3_0_17_ ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_6__472), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_start_high_latch_452), + .I2(com_llm_llm_rx_top_rx_data_46_), + .O(d64_i_m3_0_17_) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_d64_i_m3_0_16_.INIT = 8'hB8; + LUT3 com_llm_llm_rx_top_llm_rx_tlp_crc_d64_i_m3_0_16_ ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_7__2689), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_start_high_latch_452), + .I2(com_llm_llm_rx_top_rx_data_47_), + .O(d64_i_m3_0_16_) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_d64_i_m3_0_15_.INIT = 8'hB8; + LUT3 com_llm_llm_rx_top_llm_rx_tlp_crc_d64_i_m3_0_15_ ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_data_q_0__2727), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_start_high_latch_452), + .I2(com_llm_llm_rx_top_rx_data_32_), + .O(d64_i_m3_0_15_) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_d64_i_m3_0_14_.INIT = 8'hB8; + LUT3 com_llm_llm_rx_top_llm_rx_tlp_crc_d64_i_m3_0_14_ ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_data_q_1__2725), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_start_high_latch_452), + .I2(com_llm_llm_rx_top_rx_data_33_), + .O(d64_i_m3_0_14_) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_d64_i_m3_0_13_.INIT = 8'hB8; + LUT3 com_llm_llm_rx_top_llm_rx_tlp_crc_d64_i_m3_0_13_ ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_data_q[2]), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_start_high_latch_452), + .I2(com_llm_llm_rx_top_rx_data_34_), + .O(d64_i_m3_0_13_) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_d64_i_m3_0_11_.INIT = 8'hB8; + LUT3 com_llm_llm_rx_top_llm_rx_tlp_crc_d64_i_m3_0_11_ ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_data_q_4__2720), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_start_high_latch_452), + .I2(com_llm_llm_rx_top_rx_data_36_), + .O(d64_i_m3_0_11_) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_d64_i_m3_0_10_.INIT = 8'hB8; + LUT3 com_llm_llm_rx_top_llm_rx_tlp_crc_d64_i_m3_0_10_ ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_data_q_5__2718), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_start_high_latch_452), + .I2(com_llm_llm_rx_top_rx_data_37_), + .O(d64_i_m3_0_10_) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_d64_i_m3_0_8_.INIT = 8'hB8; + LUT3 com_llm_llm_rx_top_llm_rx_tlp_crc_d64_i_m3_0_8_ ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_data_q_7__2714), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_start_high_latch_452), + .I2(com_llm_llm_rx_top_rx_data_39_), + .O(d64_i_m3_0_8_) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_d64_i_m3_0_6_.INIT = 8'hE4; + LUT3 com_llm_llm_rx_top_llm_rx_tlp_crc_d64_i_m3_0_6_ ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_start_high_latch_452), + .I1(com_llm_llm_rx_top_rx_data_25_), + .I2(com_llm_llm_rx_top_rx_data_57_), + .O(d64_i_m3_0_6_) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_d64_i_m3_0_5_.INIT = 8'hE4; + LUT3 com_llm_llm_rx_top_llm_rx_tlp_crc_d64_i_m3_0_5_ ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_start_high_latch_452), + .I1(com_llm_llm_rx_top_rx_data_26_), + .I2(com_llm_llm_rx_top_rx_data_58_), + .O(d64_i_m3_0_5_) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_d64_i_m3_0_3_.INIT = 8'hE4; + LUT3 com_llm_llm_rx_top_llm_rx_tlp_crc_d64_i_m3_0_3_ ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_start_high_latch_452), + .I1(com_llm_llm_rx_top_rx_data_28_), + .I2(com_llm_llm_rx_top_rx_data_60_), + .O(d64_i_m3_0_3_) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_d64_i_m3_0_2_.INIT = 8'hE4; + LUT3 com_llm_llm_rx_top_llm_rx_tlp_crc_d64_i_m3_0_2_ ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_start_high_latch_452), + .I1(com_llm_llm_rx_top_rx_data_29_), + .I2(com_llm_llm_rx_top_rx_data_61_), + .O(d64_i_m3_0_2_) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_d64_i_m3_0_0_.INIT = 8'hE4; + LUT3 com_llm_llm_rx_top_llm_rx_tlp_crc_d64_i_m3_0_0_ ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_start_high_latch_452), + .I1(com_llm_llm_rx_top_rx_data_31_), + .I2(com_llm_llm_rx_top_rx_data_63_), + .O(d64_i_m3_0_0_) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_d16_i_m3_0_2_.INIT = 8'hCA; + LUT3 com_llm_llm_rx_top_llm_rx_tlp_crc_d16_i_m3_0_2_ ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_5__2690), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_37__2712), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_start_high_latch_q_450), + .O(d16_i_m3_0_2_) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_un1_RX_RSRC_DSC_N17_0_0_m2_0.INIT = 8'hE4; + LUT3 com_llm_llm_rx_top_llm_rx_tlp_crc_un1_RX_RSRC_DSC_N17_0_0_m2_0 ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_dw_3q_2678), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_frame_error_latch_2741), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_frame_error_latch_q_2672), + .O(com_llm_llm_rx_top_llm_rx_tlp_crc_un1_RX_RSRC_DSC_N17_0_0_m2_0_2756) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_d64_i_m3_0_21_.INIT = 8'hB8; + LUT3 com_llm_llm_rx_top_llm_rx_tlp_crc_d64_i_m3_0_21_ ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_2__476), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_start_high_latch_452), + .I2(com_llm_llm_rx_top_rx_data_42_), + .O(d64_i_m3_0_21_) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_d64_i_m3_0_12_.INIT = 8'hB8; + LUT3 com_llm_llm_rx_top_llm_rx_tlp_crc_d64_i_m3_0_12_ ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_data_q_3__2722), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_start_high_latch_452), + .I2(com_llm_llm_rx_top_rx_data_35_), + .O(d64_i_m3_0_12_) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_N_59482_i.INIT = 4'h7; + LUT2 com_llm_llm_rx_top_llm_rx_tlp_crc_N_59482_i ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rsof_nd_2744), + .I1(com_llm_rx_reof_n), + .O(com_llm_llm_rx_top_llm_rx_tlp_crc_N_59482_i_2743) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_un6_crc32_res_ok_1_and_0_a2_1.INIT = 8'h01; + LUT3 com_llm_llm_rx_top_llm_rx_tlp_crc_un6_crc32_res_ok_1_and_0_a2_1 ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d16[16]), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d16[17]), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d16[19]), + .O(com_llm_llm_rx_top_llm_rx_tlp_crc_un6_crc32_res_ok_1_and_1) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_un3_crc32_res_ok_5_and_0_a2_1_0.INIT = 8'h01; + LUT3 com_llm_llm_rx_top_llm_rx_tlp_crc_un3_crc32_res_ok_5_and_0_a2_1_0 ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d16[21]), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d16[22]), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d16[23]), + .O(com_llm_llm_rx_top_llm_rx_tlp_crc_un3_crc32_res_ok_5_and_1_0) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_dw_3_0_a2_0_o4.INIT = 8'h01; + LUT3 com_llm_llm_rx_top_llm_rx_tlp_crc_dw_3_0_a2_0_o4 ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_tlp_sof_nq_2751), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_tlp_vld_l_nq_2668), + .I2(com_llm_llm_rx_top_rx_tlp_vld_h_n), + .O(com_llm_llm_rx_top_llm_rx_tlp_crc_N_31572_i) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_un4_crc32_com_ok_0_I_141.INIT = 16'hC693; + LUT4 com_llm_llm_rx_top_llm_rx_tlp_crc_un4_crc32_com_ok_0_I_141 ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_aligned_aligned_2671), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d16[15]), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl[8]), + .I3(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_40__2710), + .O(com_llm_llm_rx_top_llm_rx_tlp_crc_N_7) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_un4_crc32_com_ok_0_I_140.INIT = 16'hC693; + LUT4 com_llm_llm_rx_top_llm_rx_tlp_crc_un4_crc32_com_ok_0_I_140 ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_aligned_aligned_2671), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d16[14]), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl[9]), + .I3(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_41__2709), + .O(com_llm_llm_rx_top_llm_rx_tlp_crc_N_6) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_un4_crc32_com_ok_0_I_51.INIT = 16'hC693; + LUT4 com_llm_llm_rx_top_llm_rx_tlp_crc_un4_crc32_com_ok_0_I_51 ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_aligned_aligned_2671), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d16[13]), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl[10]), + .I3(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_42__2708), + .O(com_llm_llm_rx_top_llm_rx_tlp_crc_N_87) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_un4_crc32_com_ok_0_I_50.INIT = 16'hC693; + LUT4 com_llm_llm_rx_top_llm_rx_tlp_crc_un4_crc32_com_ok_0_I_50 ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_aligned_aligned_2671), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d16[12]), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl[11]), + .I3(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_43__2707), + .O(com_llm_llm_rx_top_llm_rx_tlp_crc_N_86) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_un4_crc32_com_ok_0_I_123.INIT = 16'hC693; + LUT4 com_llm_llm_rx_top_llm_rx_tlp_crc_un4_crc32_com_ok_0_I_123 ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_aligned_aligned_2671), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d16[29]), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl[26]), + .I3(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_58__2724), + .O(com_llm_llm_rx_top_llm_rx_tlp_crc_N_23) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_un4_crc32_com_ok_0_I_122.INIT = 16'hC693; + LUT4 com_llm_llm_rx_top_llm_rx_tlp_crc_un4_crc32_com_ok_0_I_122 ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_aligned_aligned_2671), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d16[28]), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl[27]), + .I3(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_59__2723), + .O(com_llm_llm_rx_top_llm_rx_tlp_crc_N_22) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_un4_crc32_com_ok_0_I_69.INIT = 16'hC693; + LUT4 com_llm_llm_rx_top_llm_rx_tlp_crc_un4_crc32_com_ok_0_I_69 ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_aligned_aligned_2671), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d16[31]), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl[24]), + .I3(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_56__2728), + .O(com_llm_llm_rx_top_llm_rx_tlp_crc_N_71) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_un4_crc32_com_ok_0_I_68.INIT = 16'hC693; + LUT4 com_llm_llm_rx_top_llm_rx_tlp_crc_un4_crc32_com_ok_0_I_68 ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_aligned_aligned_2671), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d16[30]), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl[25]), + .I3(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_57__2726), + .O(com_llm_llm_rx_top_llm_rx_tlp_crc_N_70) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_un4_crc32_com_ok_0_I_87.INIT = 16'hC693; + LUT4 com_llm_llm_rx_top_llm_rx_tlp_crc_un4_crc32_com_ok_0_I_87 ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_aligned_aligned_2671), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d16[21]), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl[18]), + .I3(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_50__2734), + .O(com_llm_llm_rx_top_llm_rx_tlp_crc_N_55) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_un4_crc32_com_ok_0_I_78.INIT = 16'hC693; + LUT4 com_llm_llm_rx_top_llm_rx_tlp_crc_un4_crc32_com_ok_0_I_78 ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_aligned_aligned_2671), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d16[9]), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl[14]), + .I3(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_46__470), + .O(com_llm_llm_rx_top_llm_rx_tlp_crc_N_63) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_un4_crc32_com_ok_0_I_60.INIT = 16'hC693; + LUT4 com_llm_llm_rx_top_llm_rx_tlp_crc_un4_crc32_com_ok_0_I_60 ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_aligned_aligned_2671), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d16[11]), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl[12]), + .I3(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_44__462), + .O(com_llm_llm_rx_top_llm_rx_tlp_crc_N_79) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_un4_crc32_com_ok_0_I_59.INIT = 16'hC693; + LUT4 com_llm_llm_rx_top_llm_rx_tlp_crc_un4_crc32_com_ok_0_I_59 ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_aligned_aligned_2671), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d16[10]), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl[13]), + .I3(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_45__449), + .O(com_llm_llm_rx_top_llm_rx_tlp_crc_N_78) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_un4_crc32_com_ok_0_I_42.INIT = 16'hC693; + LUT4 com_llm_llm_rx_top_llm_rx_tlp_crc_un4_crc32_com_ok_0_I_42 ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_aligned_aligned_2671), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d16[17]), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl[22]), + .I3(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_54__2730), + .O(com_llm_llm_rx_top_llm_rx_tlp_crc_N_95) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_un4_crc32_com_ok_0_I_41.INIT = 16'hC693; + LUT4 com_llm_llm_rx_top_llm_rx_tlp_crc_un4_crc32_com_ok_0_I_41 ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_aligned_aligned_2671), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d16[16]), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl[23]), + .I3(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_55__2729), + .O(com_llm_llm_rx_top_llm_rx_tlp_crc_N_94) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_un4_crc32_com_ok_0_I_95.INIT = 16'hC693; + LUT4 com_llm_llm_rx_top_llm_rx_tlp_crc_un4_crc32_com_ok_0_I_95 ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_aligned_aligned_2671), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d16[18]), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl[21]), + .I3(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_53__2731), + .O(com_llm_llm_rx_top_llm_rx_tlp_crc_N_46) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_un4_crc32_com_ok_0_I_96.INIT = 16'hC693; + LUT4 com_llm_llm_rx_top_llm_rx_tlp_crc_un4_crc32_com_ok_0_I_96 ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_aligned_aligned_2671), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d16[19]), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl[20]), + .I3(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_52__2732), + .O(com_llm_llm_rx_top_llm_rx_tlp_crc_N_47) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_un4_crc32_com_ok_0_I_32.INIT = 16'hC693; + LUT4 com_llm_llm_rx_top_llm_rx_tlp_crc_un4_crc32_com_ok_0_I_32 ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_aligned_aligned_2671), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d16[24]), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl[31]), + .I3(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_63__2715), + .O(com_llm_llm_rx_top_llm_rx_tlp_crc_N_102) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_un4_crc32_com_ok_0_I_33.INIT = 16'hC693; + LUT4 com_llm_llm_rx_top_llm_rx_tlp_crc_un4_crc32_com_ok_0_I_33 ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_aligned_aligned_2671), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d16[25]), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl[30]), + .I3(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_62__2717), + .O(com_llm_llm_rx_top_llm_rx_tlp_crc_N_103) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_un4_crc32_com_ok_0_I_86.INIT = 16'hC693; + LUT4 com_llm_llm_rx_top_llm_rx_tlp_crc_un4_crc32_com_ok_0_I_86 ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_aligned_aligned_2671), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d16[20]), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl[19]), + .I3(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_51__2733), + .O(com_llm_llm_rx_top_llm_rx_tlp_crc_N_54) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_un4_crc32_com_ok_0_I_104.INIT = 16'hC693; + LUT4 com_llm_llm_rx_top_llm_rx_tlp_crc_un4_crc32_com_ok_0_I_104 ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_aligned_aligned_2671), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d16[22]), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl[17]), + .I3(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_49__2735), + .O(com_llm_llm_rx_top_llm_rx_tlp_crc_N_38) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_un4_crc32_com_ok_0_I_105.INIT = 16'hC693; + LUT4 com_llm_llm_rx_top_llm_rx_tlp_crc_un4_crc32_com_ok_0_I_105 ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_aligned_aligned_2671), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d16[23]), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl[16]), + .I3(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_48__2705), + .O(com_llm_llm_rx_top_llm_rx_tlp_crc_N_39) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_un4_crc32_com_ok_0_I_113.INIT = 16'hC693; + LUT4 com_llm_llm_rx_top_llm_rx_tlp_crc_un4_crc32_com_ok_0_I_113 ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_aligned_aligned_2671), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d16[0]), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl[7]), + .I3(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_39__2711), + .O(com_llm_llm_rx_top_llm_rx_tlp_crc_N_30) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_un4_crc32_com_ok_0_I_114.INIT = 16'hC693; + LUT4 com_llm_llm_rx_top_llm_rx_tlp_crc_un4_crc32_com_ok_0_I_114 ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_aligned_aligned_2671), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d16[1]), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl[6]), + .I3(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_38__473), + .O(com_llm_llm_rx_top_llm_rx_tlp_crc_N_31) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_un4_crc32_com_ok_0_I_131.INIT = 16'hC693; + LUT4 com_llm_llm_rx_top_llm_rx_tlp_crc_un4_crc32_com_ok_0_I_131 ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_aligned_aligned_2671), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d16[26]), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl[29]), + .I3(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_61__2719), + .O(com_llm_llm_rx_top_llm_rx_tlp_crc_N_14) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_un4_crc32_com_ok_0_I_132.INIT = 16'hC693; + LUT4 com_llm_llm_rx_top_llm_rx_tlp_crc_un4_crc32_com_ok_0_I_132 ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_aligned_aligned_2671), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d16[27]), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl[28]), + .I3(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_60__2721), + .O(com_llm_llm_rx_top_llm_rx_tlp_crc_N_15) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_un4_crc32_com_ok_0_I_77.INIT = 16'hC693; + LUT4 com_llm_llm_rx_top_llm_rx_tlp_crc_un4_crc32_com_ok_0_I_77 ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_aligned_aligned_2671), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d16[8]), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl[15]), + .I3(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_47__2706), + .O(com_llm_llm_rx_top_llm_rx_tlp_crc_N_62) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_un4_crc32_com_ok_0_I_5.INIT = 16'hC693; + LUT4 com_llm_llm_rx_top_llm_rx_tlp_crc_un4_crc32_com_ok_0_I_5 ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_aligned_aligned_2671), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d16[6]), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl[1]), + .I3(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_33__2692), + .O(com_llm_llm_rx_top_llm_rx_tlp_crc_N_126) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_un4_crc32_com_ok_0_I_6.INIT = 16'hC693; + LUT4 com_llm_llm_rx_top_llm_rx_tlp_crc_un4_crc32_com_ok_0_I_6 ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_aligned_aligned_2671), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d16[7]), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl[0]), + .I3(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_32__456), + .O(com_llm_llm_rx_top_llm_rx_tlp_crc_N_127) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_un4_crc32_com_ok_0_I_14.INIT = 16'hC693; + LUT4 com_llm_llm_rx_top_llm_rx_tlp_crc_un4_crc32_com_ok_0_I_14 ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_aligned_aligned_2671), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d16[4]), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl[3]), + .I3(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_35__479), + .O(com_llm_llm_rx_top_llm_rx_tlp_crc_N_118) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_un4_crc32_com_ok_0_I_15.INIT = 16'hC693; + LUT4 com_llm_llm_rx_top_llm_rx_tlp_crc_un4_crc32_com_ok_0_I_15 ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_aligned_aligned_2671), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d16[5]), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl[2]), + .I3(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_34__477), + .O(com_llm_llm_rx_top_llm_rx_tlp_crc_N_119) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_un4_crc32_com_ok_0_I_24.INIT = 16'hC693; + LUT4 com_llm_llm_rx_top_llm_rx_tlp_crc_un4_crc32_com_ok_0_I_24 ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_aligned_aligned_2671), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d16[3]), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl[4]), + .I3(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_36__2713), + .O(com_llm_llm_rx_top_llm_rx_tlp_crc_N_111) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_un4_crc32_com_ok_0_I_23.INIT = 16'hC693; + LUT4 com_llm_llm_rx_top_llm_rx_tlp_crc_un4_crc32_com_ok_0_I_23 ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_aligned_aligned_2671), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d16[2]), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl[5]), + .I3(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_37__2712), + .O(com_llm_llm_rx_top_llm_rx_tlp_crc_N_110) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_un1_RX_RSRC_DSC_N17_0_0_0.INIT = 8'h51; + LUT3 com_llm_llm_rx_top_llm_rx_tlp_crc_un1_RX_RSRC_DSC_N17_0_0_0 ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_un1_RX_RSRC_DSC_N17_0_0_m2_0_2756), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rsrc_dsc_nd_2666), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_tlp_nullified_q_2667), + .O(com_llm_llm_rx_top_llm_rx_tlp_crc_un1_RX_RSRC_DSC_N17_0_0_0_2661) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_RX_TLP_CRC_ERR_N_6_i_0_o3.INIT = 8'h02; + LUT3 com_llm_llm_rx_top_llm_rx_tlp_crc_RX_TLP_CRC_ERR_N_6_i_0_o3 ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_N_31560_i), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_dw_3q_2678), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_tlp_eof_nq_2749), + .O(com_llm_llm_rx_top_llm_rx_tlp_crc_RX_TLP_CRC_ERR_N_6_i_0_o3_2754) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_RX_TLP_CRC_ERR_N_6_i_0_m2_0_1.INIT = 16'h193B; + LUT4 com_llm_llm_rx_top_llm_rx_tlp_crc_RX_TLP_CRC_ERR_N_6_i_0_m2_0_1 ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_RX_TLP_CRC_ERR_N_6_i_0_o3_0_2663), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_tlp_nullified_latch_2740), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_un3_crc32_res_ok_7_2659), + .I3(com_llm_llm_rx_top_llm_rx_tlp_crc_un6_crc32_res_ok_7_2658), + .O(com_llm_llm_rx_top_llm_rx_tlp_crc_RX_TLP_CRC_ERR_N_6_i_0_m2_0_1_2660) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_RX_TLP_CRC_ERR_N_6_i_0_m2_0.INIT = 16'h7632; + LUT4 com_llm_llm_rx_top_llm_rx_tlp_crc_RX_TLP_CRC_ERR_N_6_i_0_m2_0 ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_RX_TLP_CRC_ERR_N_6_i_0_o3_0_2663), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_RX_TLP_CRC_ERR_N_6_i_0_m2_0_1_2660), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_I_28), + .I3(com_llm_llm_rx_top_llm_rx_tlp_crc_I_28_0), + .O(com_llm_llm_rx_top_llm_rx_tlp_crc_RX_TLP_CRC_ERR_N_6_i_0_m2_0_2755) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_RX_TLP_FERR_N_6_u_i_0_m2_0.INIT = 16'hF2D0; + LUT4 com_llm_llm_rx_top_llm_rx_tlp_crc_RX_TLP_FERR_N_6_u_i_0_m2_0 ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_N_31560_i), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_dw_3q_2678), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_reof_nd_2677), + .I3(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_tlp_eof_nq_2749), + .O(com_llm_llm_rx_top_llm_rx_tlp_crc_RX_REOF_N_5) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_N_87781_i.INIT = 16'h23FF; + LUT4 com_llm_llm_rx_top_llm_rx_tlp_crc_N_87781_i ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_N_31558_i), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_N_31569_i), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_N_31572_i), + .I3(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_tlp_eof_nq6_0_0_o2_2662), + .O(com_llm_llm_rx_top_llm_rx_tlp_crc_N_87781_i_2748) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_N_87782_i.INIT = 16'h00BF; + LUT4 com_llm_llm_rx_top_llm_rx_tlp_crc_N_87782_i ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_N_31558_i), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_N_31572_i), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_tlp_eof_nq6_0_0_o2_2662), + .I3(com_llm_llm_rx_top_llm_rx_tlp_crc_tlp_64_q_2673), + .O(com_llm_llm_rx_top_llm_rx_tlp_crc_N_87782_i_2746) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_rx_tlp_nullified_q_i.INIT = 4'h1; + LUT1_L com_llm_llm_rx_top_llm_rx_tlp_crc_rx_tlp_nullified_q_i ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_tlp_nullified_q_2667), + .LO(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_tlp_nullified_q_i_2665) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_aligned_aligned_3_0_a2_0_a2.INIT = 4'h8; + LUT2_L com_llm_llm_rx_top_llm_rx_tlp_crc_aligned_aligned_3_0_a2_0_a2 ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_end_low_latch_2742), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_start_high_latch_q_450), + .LO(com_llm_llm_rx_top_llm_rx_tlp_crc_aligned_aligned_3) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_RX_RREM13_i_0.INIT = 8'h41; + LUT3_L com_llm_llm_rx_top_llm_rx_tlp_crc_RX_RREM13_i_0 ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_dw_3q_2678), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_end_low_latch_2742), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_start_high_latch_qq_2670), + .LO(com_llm_llm_rx_top_llm_rx_tlp_crc_N_16213_i) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_tlp_64_0_a2_0_a2.INIT = 4'h2; + LUT2_L com_llm_llm_rx_top_llm_rx_tlp_crc_tlp_64_0_a2_0_a2 ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_N_31569_i), + .I1(com_llm_llm_rx_top_rx_tlp_eof_n), + .LO(com_llm_llm_rx_top_llm_rx_tlp_crc_tlp_64) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_unaligned_aligned_3_0_a2_0_a2.INIT = 4'h2; + LUT2_L com_llm_llm_rx_top_llm_rx_tlp_crc_unaligned_aligned_3_0_a2_0_a2 ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_end_low_latch_2742), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_start_high_latch_q_450), + .LO(com_llm_llm_rx_top_llm_rx_tlp_crc_unaligned_aligned_3) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_aligned_unaligned_3_0_a2_0_a2.INIT = 4'h4; + LUT2_L com_llm_llm_rx_top_llm_rx_tlp_crc_aligned_unaligned_3_0_a2_0_a2 ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_end_low_latch_2742), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_start_high_latch_q_450), + .LO(com_llm_llm_rx_top_llm_rx_tlp_crc_aligned_unaligned_3) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_N_87780_i.INIT = 4'hD; + LUT2_L com_llm_llm_rx_top_llm_rx_tlp_crc_N_87780_i ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_un1_RX_RSRC_DSC_N17_0_0_m2_0_2756), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_RX_REOF_N_5), + .LO(com_llm_llm_rx_top_llm_rx_tlp_crc_N_87780_i_2676) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_dw_3_0_a2_0_a2.INIT = 8'h02; + LUT3_L com_llm_llm_rx_top_llm_rx_tlp_crc_dw_3_0_a2_0_a2 ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_N_31572_i), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_tlp_vld_h_nq_2669), + .I2(com_llm_llm_rx_top_rx_tlp_eof_n), + .LO(com_llm_llm_rx_top_llm_rx_tlp_crc_dw_3) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_N_85331_i.INIT = 16'h73FF; + LUT4_L com_llm_llm_rx_top_llm_rx_tlp_crc_N_85331_i ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_N_31560_i), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_RX_TLP_CRC_ERR_N_6_i_0_m2_0_2755), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rsrc_dsc_nd_2666), + .I3(com_llm_llm_rx_top_llm_rx_tlp_crc_un1_RX_RSRC_DSC_N17_0_0_0_2661), + .LO(com_llm_llm_rx_top_llm_rx_tlp_crc_N_85331_i_2679) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m3_0_6_.INIT = 8'hCA; + LUT3_L com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m3_0_6_ ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl[6]), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl[38]), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_start_high_latch_qq_2670), + .LO(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m3_0[6]) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m3_0_5_.INIT = 8'hCA; + LUT3_L com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m3_0_5_ ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl[5]), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl[37]), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_start_high_latch_qq_2670), + .LO(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m3_0[5]) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m3_0_4_.INIT = 8'hCA; + LUT3_L com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m3_0_4_ ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl[4]), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl[36]), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_start_high_latch_qq_2670), + .LO(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m3_0[4]) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m3_0_3_.INIT = 8'hCA; + LUT3_L com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m3_0_3_ ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl[3]), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl[35]), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_start_high_latch_qq_2670), + .LO(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m3_0[3]) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m3_0_2_.INIT = 8'hCA; + LUT3_L com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m3_0_2_ ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl[2]), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl[34]), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_start_high_latch_qq_2670), + .LO(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m3_0[2]) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m3_0_1_.INIT = 8'hCA; + LUT3_L com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m3_0_1_ ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl[1]), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl[33]), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_start_high_latch_qq_2670), + .LO(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m3_0[1]) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m3_0_0_.INIT = 8'hCA; + LUT3_L com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m3_0_0_ ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl[0]), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl[32]), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_start_high_latch_qq_2670), + .LO(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m3_0[0]) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m3_0_21_.INIT = 8'hCA; + LUT3_L com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m3_0_21_ ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl[21]), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl[53]), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_start_high_latch_qq_2670), + .LO(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m3_0[21]) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m3_0_20_.INIT = 8'hCA; + LUT3_L com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m3_0_20_ ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl[20]), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl[52]), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_start_high_latch_qq_2670), + .LO(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m3_0[20]) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m3_0_19_.INIT = 8'hCA; + LUT3_L com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m3_0_19_ ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl[19]), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl[51]), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_start_high_latch_qq_2670), + .LO(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m3_0[19]) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m3_0_18_.INIT = 8'hCA; + LUT3_L com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m3_0_18_ ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl[18]), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl[50]), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_start_high_latch_qq_2670), + .LO(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m3_0[18]) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m3_0_17_.INIT = 8'hCA; + LUT3_L com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m3_0_17_ ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl[17]), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl[49]), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_start_high_latch_qq_2670), + .LO(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m3_0[17]) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m3_0_16_.INIT = 8'hCA; + LUT3_L com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m3_0_16_ ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl[16]), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl[48]), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_start_high_latch_qq_2670), + .LO(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m3_0[16]) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m3_0_15_.INIT = 8'hCA; + LUT3_L com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m3_0_15_ ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl[15]), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl[47]), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_start_high_latch_qq_2670), + .LO(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m3_0[15]) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m3_0_14_.INIT = 8'hCA; + LUT3_L com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m3_0_14_ ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl[14]), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl[46]), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_start_high_latch_qq_2670), + .LO(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m3_0[14]) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m3_0_13_.INIT = 8'hCA; + LUT3_L com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m3_0_13_ ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl[13]), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl[45]), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_start_high_latch_qq_2670), + .LO(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m3_0[13]) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m3_0_12_.INIT = 8'hCA; + LUT3_L com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m3_0_12_ ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl[12]), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl[44]), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_start_high_latch_qq_2670), + .LO(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m3_0[12]) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m3_0_11_.INIT = 8'hCA; + LUT3_L com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m3_0_11_ ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl[11]), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl[43]), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_start_high_latch_qq_2670), + .LO(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m3_0[11]) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m3_0_10_.INIT = 8'hCA; + LUT3_L com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m3_0_10_ ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl[10]), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl[42]), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_start_high_latch_qq_2670), + .LO(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m3_0[10]) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m3_0_9_.INIT = 8'hCA; + LUT3_L com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m3_0_9_ ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl[9]), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl[41]), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_start_high_latch_qq_2670), + .LO(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m3_0[9]) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m3_0_8_.INIT = 8'hCA; + LUT3_L com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m3_0_8_ ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl[8]), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl[40]), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_start_high_latch_qq_2670), + .LO(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m3_0[8]) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m3_0_7_.INIT = 8'hCA; + LUT3_L com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m3_0_7_ ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl[7]), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl[39]), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_start_high_latch_qq_2670), + .LO(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m3_0[7]) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m3_0_36_.INIT = 8'hAC; + LUT3_L com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m3_0_36_ ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sh[36]), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl[36]), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_start_high_latch_qq_2670), + .LO(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m3_0[36]) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m3_0_35_.INIT = 8'hAC; + LUT3_L com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m3_0_35_ ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sh[35]), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl[35]), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_start_high_latch_qq_2670), + .LO(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m3_0[35]) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m3_0_34_.INIT = 8'hAC; + LUT3_L com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m3_0_34_ ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sh[34]), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl[34]), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_start_high_latch_qq_2670), + .LO(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m3_0[34]) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m3_0_33_.INIT = 8'hAC; + LUT3_L com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m3_0_33_ ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sh[33]), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl[33]), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_start_high_latch_qq_2670), + .LO(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m3_0[33]) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m3_0_32_.INIT = 8'hAC; + LUT3_L com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m3_0_32_ ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sh[32]), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl[32]), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_start_high_latch_qq_2670), + .LO(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m3_0[32]) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m3_0_31_.INIT = 8'hCA; + LUT3_L com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m3_0_31_ ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl[31]), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl[63]), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_start_high_latch_qq_2670), + .LO(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m3_0[31]) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m3_0_30_.INIT = 8'hCA; + LUT3_L com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m3_0_30_ ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl[30]), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl[62]), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_start_high_latch_qq_2670), + .LO(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m3_0[30]) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m3_0_29_.INIT = 8'hCA; + LUT3_L com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m3_0_29_ ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl[29]), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl[61]), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_start_high_latch_qq_2670), + .LO(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m3_0[29]) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m3_0_28_.INIT = 8'hCA; + LUT3_L com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m3_0_28_ ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl[28]), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl[60]), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_start_high_latch_qq_2670), + .LO(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m3_0[28]) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m3_0_27_.INIT = 8'hCA; + LUT3_L com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m3_0_27_ ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl[27]), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl[59]), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_start_high_latch_qq_2670), + .LO(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m3_0[27]) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m3_0_26_.INIT = 8'hCA; + LUT3_L com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m3_0_26_ ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl[26]), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl[58]), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_start_high_latch_qq_2670), + .LO(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m3_0[26]) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m3_0_25_.INIT = 8'hCA; + LUT3_L com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m3_0_25_ ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl[25]), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl[57]), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_start_high_latch_qq_2670), + .LO(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m3_0[25]) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m3_0_24_.INIT = 8'hCA; + LUT3_L com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m3_0_24_ ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl[24]), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl[56]), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_start_high_latch_qq_2670), + .LO(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m3_0[24]) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m3_0_23_.INIT = 8'hCA; + LUT3_L com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m3_0_23_ ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl[23]), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl[55]), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_start_high_latch_qq_2670), + .LO(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m3_0[23]) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m3_0_22_.INIT = 8'hCA; + LUT3_L com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m3_0_22_ ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl[22]), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl[54]), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_start_high_latch_qq_2670), + .LO(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m3_0[22]) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m3_0_51_.INIT = 8'hAC; + LUT3_L com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m3_0_51_ ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sh[51]), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl[51]), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_start_high_latch_qq_2670), + .LO(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m3_0[51]) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m3_0_50_.INIT = 8'hAC; + LUT3_L com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m3_0_50_ ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sh[50]), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl[50]), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_start_high_latch_qq_2670), + .LO(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m3_0[50]) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m3_0_49_.INIT = 8'hAC; + LUT3_L com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m3_0_49_ ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sh[49]), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl[49]), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_start_high_latch_qq_2670), + .LO(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m3_0[49]) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m3_0_48_.INIT = 8'hAC; + LUT3_L com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m3_0_48_ ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sh[48]), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl[48]), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_start_high_latch_qq_2670), + .LO(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m3_0[48]) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m3_0_47_.INIT = 8'hAC; + LUT3_L com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m3_0_47_ ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sh[47]), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl[47]), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_start_high_latch_qq_2670), + .LO(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m3_0[47]) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m3_0_46_.INIT = 8'hAC; + LUT3_L com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m3_0_46_ ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sh[46]), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl[46]), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_start_high_latch_qq_2670), + .LO(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m3_0[46]) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m3_0_45_.INIT = 8'hAC; + LUT3_L com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m3_0_45_ ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sh[45]), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl[45]), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_start_high_latch_qq_2670), + .LO(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m3_0[45]) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m3_0_44_.INIT = 8'hAC; + LUT3_L com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m3_0_44_ ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sh[44]), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl[44]), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_start_high_latch_qq_2670), + .LO(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m3_0[44]) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m3_0_43_.INIT = 8'hAC; + LUT3_L com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m3_0_43_ ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sh[43]), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl[43]), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_start_high_latch_qq_2670), + .LO(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m3_0[43]) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m3_0_42_.INIT = 8'hAC; + LUT3_L com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m3_0_42_ ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sh[42]), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl[42]), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_start_high_latch_qq_2670), + .LO(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m3_0[42]) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m3_0_41_.INIT = 8'hAC; + LUT3_L com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m3_0_41_ ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sh[41]), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl[41]), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_start_high_latch_qq_2670), + .LO(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m3_0[41]) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m3_0_40_.INIT = 8'hAC; + LUT3_L com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m3_0_40_ ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sh[40]), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl[40]), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_start_high_latch_qq_2670), + .LO(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m3_0[40]) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m3_0_39_.INIT = 8'hAC; + LUT3_L com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m3_0_39_ ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sh[39]), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl[39]), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_start_high_latch_qq_2670), + .LO(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m3_0[39]) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m3_0_38_.INIT = 8'hAC; + LUT3_L com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m3_0_38_ ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sh[38]), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl[38]), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_start_high_latch_qq_2670), + .LO(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m3_0[38]) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m3_0_37_.INIT = 8'hAC; + LUT3_L com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m3_0_37_ ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sh[37]), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl[37]), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_start_high_latch_qq_2670), + .LO(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m3_0[37]) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m3_0_63_.INIT = 8'hAC; + LUT3_L com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m3_0_63_ ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sh[63]), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl[63]), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_start_high_latch_qq_2670), + .LO(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m3_0[63]) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m3_0_62_.INIT = 8'hAC; + LUT3_L com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m3_0_62_ ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sh[62]), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl[62]), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_start_high_latch_qq_2670), + .LO(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m3_0[62]) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m3_0_61_.INIT = 8'hAC; + LUT3_L com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m3_0_61_ ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sh[61]), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl[61]), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_start_high_latch_qq_2670), + .LO(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m3_0[61]) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m3_0_60_.INIT = 8'hAC; + LUT3_L com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m3_0_60_ ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sh[60]), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl[60]), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_start_high_latch_qq_2670), + .LO(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m3_0[60]) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m3_0_59_.INIT = 8'hAC; + LUT3_L com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m3_0_59_ ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sh[59]), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl[59]), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_start_high_latch_qq_2670), + .LO(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m3_0[59]) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m3_0_58_.INIT = 8'hAC; + LUT3_L com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m3_0_58_ ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sh[58]), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl[58]), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_start_high_latch_qq_2670), + .LO(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m3_0[58]) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m3_0_57_.INIT = 8'hAC; + LUT3_L com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m3_0_57_ ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sh[57]), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl[57]), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_start_high_latch_qq_2670), + .LO(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m3_0[57]) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m3_0_56_.INIT = 8'hAC; + LUT3_L com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m3_0_56_ ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sh[56]), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl[56]), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_start_high_latch_qq_2670), + .LO(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m3_0[56]) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m3_0_55_.INIT = 8'hAC; + LUT3_L com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m3_0_55_ ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sh[55]), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl[55]), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_start_high_latch_qq_2670), + .LO(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m3_0[55]) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m3_0_54_.INIT = 8'hAC; + LUT3_L com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m3_0_54_ ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sh[54]), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl[54]), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_start_high_latch_qq_2670), + .LO(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m3_0[54]) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m3_0_53_.INIT = 8'hAC; + LUT3_L com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m3_0_53_ ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sh[53]), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl[53]), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_start_high_latch_qq_2670), + .LO(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m3_0[53]) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m3_0_52_.INIT = 8'hAC; + LUT3_L com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m3_0_52_ ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sh[52]), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl[52]), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_start_high_latch_qq_2670), + .LO(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m3_0[52]) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_start_high_latch_3_0_a2_0_a2.INIT = 4'h2; + LUT2_L com_llm_llm_rx_top_llm_rx_tlp_crc_start_high_latch_3_0_a2_0_a2 ( + .I0(com_llm_llm_rx_top_rx_tlp_eof_n), + .I1(com_llm_llm_rx_top_rx_tlp_vld_h_n), + .LO(com_llm_llm_rx_top_llm_rx_tlp_crc_start_high_latch_3) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_rx_tlp_tsn_dd_5_i_m3_i_m3_0_11_.INIT = 8'hE4; + LUT3_L com_llm_llm_rx_top_llm_rx_tlp_crc_rx_tlp_tsn_dd_5_i_m3_i_m3_0_11_ ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_N_31558_i), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_11__2685), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_43__2707), + .LO(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_tlp_tsn_dd_5_i_m3_i_m3_0[11]) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_rx_tlp_tsn_dd_5_i_m3_i_m3_0_10_.INIT = 8'hE4; + LUT3_L com_llm_llm_rx_top_llm_rx_tlp_crc_rx_tlp_tsn_dd_5_i_m3_i_m3_0_10_ ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_N_31558_i), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_10__2686), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_42__2708), + .LO(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_tlp_tsn_dd_5_i_m3_i_m3_0[10]) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_rx_tlp_tsn_dd_5_i_m3_i_m3_0_9_.INIT = 8'hE4; + LUT3_L com_llm_llm_rx_top_llm_rx_tlp_crc_rx_tlp_tsn_dd_5_i_m3_i_m3_0_9_ ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_N_31558_i), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_9__2687), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_41__2709), + .LO(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_tlp_tsn_dd_5_i_m3_i_m3_0[9]) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_rx_tlp_tsn_dd_5_i_m3_i_m3_0_8_.INIT = 8'hE4; + LUT3_L com_llm_llm_rx_top_llm_rx_tlp_crc_rx_tlp_tsn_dd_5_i_m3_i_m3_0_8_ ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_N_31558_i), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_8__2688), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_40__2710), + .LO(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_tlp_tsn_dd_5_i_m3_i_m3_0[8]) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_rx_tlp_tsn_dd_5_i_m3_i_m3_0_7_.INIT = 8'hE4; + LUT3_L com_llm_llm_rx_top_llm_rx_tlp_crc_rx_tlp_tsn_dd_5_i_m3_i_m3_0_7_ ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_N_31558_i), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_7__2689), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_39__2711), + .LO(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_tlp_tsn_dd_5_i_m3_i_m3_0[7]) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_rx_tlp_tsn_dd_5_i_m3_i_m3_0_6_.INIT = 8'hE4; + LUT3_L com_llm_llm_rx_top_llm_rx_tlp_crc_rx_tlp_tsn_dd_5_i_m3_i_m3_0_6_ ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_N_31558_i), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_6__472), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_38__473), + .LO(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_tlp_tsn_dd_5_i_m3_i_m3_0[6]) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_rx_tlp_tsn_dd_5_i_m3_0_5_.INIT = 8'hE4; + LUT3_L com_llm_llm_rx_top_llm_rx_tlp_crc_rx_tlp_tsn_dd_5_i_m3_0_5_ ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_N_31558_i), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_5__2690), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_37__2712), + .LO(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_tlp_tsn_dd_5_i_m3_0[5]) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_rx_tlp_tsn_dd_5_i_m3_0_4_.INIT = 8'hE4; + LUT3_L com_llm_llm_rx_top_llm_rx_tlp_crc_rx_tlp_tsn_dd_5_i_m3_0_4_ ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_N_31558_i), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_4__2691), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_36__2713), + .LO(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_tlp_tsn_dd_5_i_m3_0[4]) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_rx_tlp_tsn_dd_5_i_m3_0_3_.INIT = 8'hE4; + LUT3_L com_llm_llm_rx_top_llm_rx_tlp_crc_rx_tlp_tsn_dd_5_i_m3_0_3_ ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_N_31558_i), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_3__478), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_35__479), + .LO(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_tlp_tsn_dd_5_i_m3_0[3]) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_rx_tlp_tsn_dd_5_i_m3_0_2_.INIT = 8'hE4; + LUT3_L com_llm_llm_rx_top_llm_rx_tlp_crc_rx_tlp_tsn_dd_5_i_m3_0_2_ ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_N_31558_i), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_2__476), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_34__477), + .LO(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_tlp_tsn_dd_5_i_m3_0[2]) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_rx_tlp_tsn_dd_5_i_m3_0_1_.INIT = 8'hE4; + LUT3_L com_llm_llm_rx_top_llm_rx_tlp_crc_rx_tlp_tsn_dd_5_i_m3_0_1_ ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_N_31558_i), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_1__2680), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_33__2692), + .LO(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_tlp_tsn_dd_5_i_m3_0[1]) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_rx_tlp_tsn_dd_5_i_m3_0_0_.INIT = 8'hE4; + LUT3_L com_llm_llm_rx_top_llm_rx_tlp_crc_rx_tlp_tsn_dd_5_i_m3_0_0_ ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_N_31558_i), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_0__455), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_32__456), + .LO(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_tlp_tsn_dd_5_i_m3_0[0]) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_N_85330_i_1.INIT = 16'h0F0E; + LUT4 com_llm_llm_rx_top_llm_rx_tlp_crc_N_85330_i_1 ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_aligned_aligned_2671), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_aligned_unaligned_2675), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_reof_nd_2677), + .I3(com_llm_llm_rx_top_llm_rx_tlp_crc_unaligned_aligned_2674), + .O(com_llm_llm_rx_top_llm_rx_tlp_crc_N_85330_i_1_2753) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_rx_tlp_eof_nq6_0_0_o2.INIT = 8'h45; + LUT3 com_llm_llm_rx_top_llm_rx_tlp_crc_rx_tlp_eof_nq6_0_0_o2 ( + .I0(com_llm_llm_rx_top_rx_tlp_eof_n), + .I1(com_llm_llm_rx_top_rx_tlp_vld_l_n), + .I2(com_llm_llm_rx_top_rx_tlp_sof_n), + .O(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_tlp_eof_nq6_0_0_o2_2662) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_RX_TLP_CRC_ERR_N_6_i_0_o3_0.INIT = 8'h54; + LUT3 com_llm_llm_rx_top_llm_rx_tlp_crc_RX_TLP_CRC_ERR_N_6_i_0_o3_0 ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_aligned_aligned_2671), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_start_high_latch_qq_2670), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_end_low_latch_2742), + .O(com_llm_llm_rx_top_llm_rx_tlp_crc_RX_TLP_CRC_ERR_N_6_i_0_o3_0_2663) + ); + MUXCY com_llm_llm_rx_top_llm_rx_tlp_crc_un3_crc32_com_ok_0_I_28 ( + .CI(com_llm_llm_rx_top_llm_rx_tlp_crc_data_tmp_0[14]), + .DI(com_llm_llm_rx_top_llm_rx_tlp_crc_GND_2664), + .O(com_llm_llm_rx_top_llm_rx_tlp_crc_I_28), + .S(com_llm_llm_rx_top_llm_rx_tlp_crc_N_99) + ); + MUXCY com_llm_llm_rx_top_llm_rx_tlp_crc_un4_crc32_com_ok_0_I_28 ( + .CI(com_llm_llm_rx_top_llm_rx_tlp_crc_data_tmp[14]), + .DI(com_llm_llm_rx_top_llm_rx_tlp_crc_GND_2664), + .O(com_llm_llm_rx_top_llm_rx_tlp_crc_I_28_0), + .S(com_llm_llm_rx_top_llm_rx_tlp_crc_N_99_0) + ); + FDP com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rsrc_dsc_nd ( + .PRE(plm_link_up_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_tlp_nullified_q_i_2665), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rsrc_dsc_nd_2666) + ); + FDP com_llm_llm_rx_top_llm_rx_tlp_crc_RX_RSOF_N ( + .PRE(plm_link_up_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rsof_nd_2744), + .Q(com_llm_llm_rx_top_rx_sof_n) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_rx_tlp_nullified_q ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_rx_tlp_nullified), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_tlp_nullified_q_2667), + .CLR(plm_link_up_i) + ); + FDP com_llm_llm_rx_top_llm_rx_tlp_crc_rx_tlp_vld_l_nq ( + .PRE(plm_link_up_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_rx_tlp_vld_l_n), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_tlp_vld_l_nq_2668) + ); + FDP com_llm_llm_rx_top_llm_rx_tlp_crc_rx_tlp_vld_h_nq ( + .PRE(plm_link_up_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_rx_tlp_vld_h_n), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_tlp_vld_h_nq_2669) + ); + FDP com_llm_llm_rx_top_llm_rx_tlp_crc_rx_tlp_sof_nq ( + .PRE(plm_link_up_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_rx_tlp_sof_n), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_tlp_sof_nq_2751) + ); + FDP com_llm_llm_rx_top_llm_rx_tlp_crc_start_high_latch_qq ( + .PRE(plm_link_up_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_start_high_latch_q_450), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_start_high_latch_qq_2670) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_initial_64 ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_rx_tlp_sof_n_i), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_initial_64_97), + .CLR(plm_link_up_i) + ); + FDP com_llm_llm_rx_top_llm_rx_tlp_crc_aligned_aligned ( + .PRE(plm_link_up_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_aligned_aligned_3), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_aligned_aligned_2671) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_frame_error_latch_q ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_frame_error_latch_2741), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_frame_error_latch_q_2672), + .CLR(plm_link_up_i) + ); + FDP com_llm_llm_rx_top_llm_rx_tlp_crc_RX_RREM_1_2_ ( + .PRE(plm_link_up_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_N_16213_i), + .Q(com_llm_llm_rx_top_rx_rrem[2]) + ); + FDP com_llm_llm_rx_top_llm_rx_tlp_crc_start_high_latch_q ( + .PRE(plm_link_up_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_start_high_latch_452), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_start_high_latch_q_450) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_tlp_64_q ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_tlp_64), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_tlp_64_q_2673), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_unaligned_aligned ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_unaligned_aligned_3), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_unaligned_aligned_2674), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_aligned_unaligned ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_aligned_unaligned_3), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_aligned_unaligned_2675), + .CLR(plm_link_up_i) + ); + FDP com_llm_llm_rx_top_llm_rx_tlp_crc_RX_TLP_CRC_ERR_N ( + .PRE(plm_link_up_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_N_85330_i_2752), + .Q(com_llm_llm_rx_top_rx_tlp_crc_err_n) + ); + FDP com_llm_llm_rx_top_llm_rx_tlp_crc_RX_TLP_FERR_N ( + .PRE(plm_link_up_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_N_87780_i_2676), + .Q(com_llm_llm_rx_top_rx_tlp_ferr_n) + ); + FDP com_llm_llm_rx_top_llm_rx_tlp_crc_rx_reof_nd ( + .PRE(plm_link_up_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_tlp_eof_nq_2749), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_reof_nd_2677) + ); + FDP com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rsof_nd ( + .PRE(plm_link_up_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_tlp_sof_nqq_2747), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rsof_nd_2744) + ); + FDP com_llm_llm_rx_top_llm_rx_tlp_crc_RX_REOF_N ( + .PRE(plm_link_up_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_RX_REOF_N_5), + .Q(com_llm_rx_reof_n) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_dw_3q ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_dw_3), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_dw_3q_2678), + .CLR(plm_link_up_i) + ); + FDP com_llm_llm_rx_top_llm_rx_tlp_crc_RX_RSRC_DSC_N ( + .PRE(plm_link_up_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_N_85331_i_2679), + .Q(com_llm_rx_rsrc_dsc_n) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_rx_tlp_tsn_d_8_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_tlp_tsn_dd[8]), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_tlp_tsn_d[8]), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_rx_tlp_tsn_d_7_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_tlp_tsn_dd[7]), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_tlp_tsn_d[7]), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_rx_tlp_tsn_d_6_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_tlp_tsn_dd[6]), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_tlp_tsn_d[6]), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_rx_tlp_tsn_d_5_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_tlp_tsn_dd[5]), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_tlp_tsn_d[5]), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_rx_tlp_tsn_d_4_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_tlp_tsn_dd[4]), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_tlp_tsn_d[4]), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_rx_tlp_tsn_d_3_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_tlp_tsn_dd[3]), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_tlp_tsn_d[3]), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_rx_tlp_tsn_d_2_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_tlp_tsn_dd[2]), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_tlp_tsn_d[2]), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_rx_tlp_tsn_d_1_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_tlp_tsn_dd[1]), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_tlp_tsn_d[1]), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_rx_tlp_tsn_d_0_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_tlp_tsn_dd[0]), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_tlp_tsn_d[0]), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_rx_tlp_tsn_d_11_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_tlp_tsn_dd[11]), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_tlp_tsn_d[11]), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_rx_tlp_tsn_d_10_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_tlp_tsn_dd[10]), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_tlp_tsn_d[10]), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_rx_tlp_tsn_d_9_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_tlp_tsn_dd[9]), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_tlp_tsn_d[9]), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_RX_RD_6_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m3_0[6]), + .Q(com_llm_llm_rx_top_rx_rd[6]), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_RX_RD_5_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m3_0[5]), + .Q(com_llm_llm_rx_top_rx_rd[5]), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_RX_RD_4_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m3_0[4]), + .Q(com_llm_llm_rx_top_rx_rd[4]), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_RX_RD_3_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m3_0[3]), + .Q(com_llm_llm_rx_top_rx_rd[3]), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_RX_RD_2_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m3_0[2]), + .Q(com_llm_llm_rx_top_rx_rd[2]), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_RX_RD_1_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m3_0[1]), + .Q(com_llm_llm_rx_top_rx_rd[1]), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_RX_RD_0_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m3_0[0]), + .Q(com_llm_llm_rx_top_rx_rd[0]), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_RX_RD_21_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m3_0[21]), + .Q(com_llm_llm_rx_top_rx_rd[21]), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_RX_RD_20_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m3_0[20]), + .Q(com_llm_llm_rx_top_rx_rd[20]), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_RX_RD_19_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m3_0[19]), + .Q(com_llm_llm_rx_top_rx_rd[19]), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_RX_RD_18_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m3_0[18]), + .Q(com_llm_llm_rx_top_rx_rd[18]), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_RX_RD_17_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m3_0[17]), + .Q(com_llm_llm_rx_top_rx_rd[17]), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_RX_RD_16_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m3_0[16]), + .Q(com_llm_llm_rx_top_rx_rd[16]), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_RX_RD_15_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m3_0[15]), + .Q(com_llm_llm_rx_top_rx_rd[15]), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_RX_RD_14_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m3_0[14]), + .Q(com_llm_llm_rx_top_rx_rd[14]), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_RX_RD_13_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m3_0[13]), + .Q(com_llm_llm_rx_top_rx_rd[13]), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_RX_RD_12_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m3_0[12]), + .Q(com_llm_llm_rx_top_rx_rd[12]), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_RX_RD_11_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m3_0[11]), + .Q(com_llm_llm_rx_top_rx_rd[11]), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_RX_RD_10_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m3_0[10]), + .Q(com_llm_llm_rx_top_rx_rd[10]), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_RX_RD_9_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m3_0[9]), + .Q(com_llm_llm_rx_top_rx_rd[9]), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_RX_RD_8_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m3_0[8]), + .Q(com_llm_llm_rx_top_rx_rd[8]), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_RX_RD_7_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m3_0[7]), + .Q(com_llm_llm_rx_top_rx_rd[7]), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_RX_RD_36_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m3_0[36]), + .Q(com_llm_llm_rx_top_rx_rd[36]), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_RX_RD_35_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m3_0[35]), + .Q(com_llm_llm_rx_top_rx_rd[35]), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_RX_RD_34_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m3_0[34]), + .Q(com_llm_llm_rx_top_rx_rd[34]), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_RX_RD_33_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m3_0[33]), + .Q(com_llm_llm_rx_top_rx_rd[33]), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_RX_RD_32_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m3_0[32]), + .Q(com_llm_llm_rx_top_rx_rd[32]), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_RX_RD_31_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m3_0[31]), + .Q(com_llm_llm_rx_top_rx_rd[31]), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_RX_RD_30_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m3_0[30]), + .Q(com_llm_llm_rx_top_rx_rd[30]), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_RX_RD_29_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m3_0[29]), + .Q(com_llm_llm_rx_top_rx_rd[29]), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_RX_RD_28_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m3_0[28]), + .Q(com_llm_llm_rx_top_rx_rd[28]), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_RX_RD_27_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m3_0[27]), + .Q(com_llm_llm_rx_top_rx_rd[27]), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_RX_RD_26_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m3_0[26]), + .Q(com_llm_llm_rx_top_rx_rd[26]), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_RX_RD_25_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m3_0[25]), + .Q(com_llm_llm_rx_top_rx_rd[25]), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_RX_RD_24_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m3_0[24]), + .Q(com_llm_llm_rx_top_rx_rd[24]), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_RX_RD_23_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m3_0[23]), + .Q(com_llm_llm_rx_top_rx_rd[23]), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_RX_RD_22_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m3_0[22]), + .Q(com_llm_llm_rx_top_rx_rd[22]), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_RX_RD_51_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m3_0[51]), + .Q(com_llm_llm_rx_top_rx_rd[51]), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_RX_RD_50_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m3_0[50]), + .Q(com_llm_llm_rx_top_rx_rd[50]), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_RX_RD_49_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m3_0[49]), + .Q(com_llm_llm_rx_top_rx_rd[49]), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_RX_RD_48_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m3_0[48]), + .Q(com_llm_llm_rx_top_rx_rd[48]), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_RX_RD_47_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m3_0[47]), + .Q(com_llm_llm_rx_top_rx_rd[47]), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_RX_RD_46_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m3_0[46]), + .Q(com_llm_llm_rx_top_rx_rd[46]), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_RX_RD_45_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m3_0[45]), + .Q(com_llm_llm_rx_top_rx_rd[45]), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_RX_RD_44_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m3_0[44]), + .Q(com_llm_llm_rx_top_rx_rd[44]), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_RX_RD_43_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m3_0[43]), + .Q(com_llm_llm_rx_top_rx_rd[43]), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_RX_RD_42_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m3_0[42]), + .Q(com_llm_llm_rx_top_rx_rd[42]), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_RX_RD_41_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m3_0[41]), + .Q(com_llm_llm_rx_top_rx_rd[41]), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_RX_RD_40_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m3_0[40]), + .Q(com_llm_llm_rx_top_rx_rd[40]), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_RX_RD_39_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m3_0[39]), + .Q(com_llm_llm_rx_top_rx_rd[39]), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_RX_RD_38_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m3_0[38]), + .Q(com_llm_llm_rx_top_rx_rd[38]), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_RX_RD_37_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m3_0[37]), + .Q(com_llm_llm_rx_top_rx_rd[37]), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sh_34_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl[2]), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sh[34]), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sh_33_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl[1]), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sh[33]), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sh_32_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl[0]), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sh[32]), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_RX_RD_63_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m3_0[63]), + .Q(com_llm_llm_rx_top_rx_rd[63]), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_RX_RD_62_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m3_0[62]), + .Q(com_llm_llm_rx_top_rx_rd[62]), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_RX_RD_61_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m3_0[61]), + .Q(com_llm_llm_rx_top_rx_rd[61]), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_RX_RD_60_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m3_0[60]), + .Q(com_llm_llm_rx_top_rx_rd[60]), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_RX_RD_59_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m3_0[59]), + .Q(com_llm_llm_rx_top_rx_rd[59]), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_RX_RD_58_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m3_0[58]), + .Q(com_llm_llm_rx_top_rx_rd[58]), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_RX_RD_57_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m3_0[57]), + .Q(com_llm_llm_rx_top_rx_rd[57]), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_RX_RD_56_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m3_0[56]), + .Q(com_llm_llm_rx_top_rx_rd[56]), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_RX_RD_55_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m3_0[55]), + .Q(com_llm_llm_rx_top_rx_rd[55]), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_RX_RD_54_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m3_0[54]), + .Q(com_llm_llm_rx_top_rx_rd[54]), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_RX_RD_53_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m3_0[53]), + .Q(com_llm_llm_rx_top_rx_rd[53]), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_RX_RD_52_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_d_i_m3_0[52]), + .Q(com_llm_llm_rx_top_rx_rd[52]), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sh_49_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl[17]), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sh[49]), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sh_48_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl[16]), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sh[48]), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sh_47_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl[15]), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sh[47]), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sh_46_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl[14]), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sh[46]), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sh_45_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl[13]), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sh[45]), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sh_44_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl[12]), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sh[44]), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sh_43_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl[11]), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sh[43]), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sh_42_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl[10]), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sh[42]), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sh_41_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl[9]), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sh[41]), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sh_40_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl[8]), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sh[40]), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sh_39_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl[7]), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sh[39]), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sh_38_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl[6]), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sh[38]), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sh_37_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl[5]), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sh[37]), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sh_36_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl[4]), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sh[36]), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sh_35_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl[3]), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sh[35]), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_rx_data_q_0_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_rx_data_0_), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_data_q_0__2727), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sh_63_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl[31]), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sh[63]), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sh_62_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl[30]), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sh[62]), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sh_61_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl[29]), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sh[61]), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sh_60_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl[28]), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sh[60]), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sh_59_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl[27]), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sh[59]), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sh_58_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl[26]), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sh[58]), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sh_57_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl[25]), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sh[57]), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sh_56_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl[24]), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sh[56]), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sh_55_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl[23]), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sh[55]), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sh_54_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl[22]), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sh[54]), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sh_53_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl[21]), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sh[53]), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sh_52_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl[20]), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sh[52]), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sh_51_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl[19]), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sh[51]), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sh_50_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl[18]), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sh[50]), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_7_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_7__2689), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl[7]), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_6_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_6__472), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl[6]), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_5_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_5__2690), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl[5]), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_4_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_4__2691), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl[4]), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_3_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_3__478), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl[3]), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_2_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_2__476), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl[2]), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_1_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_1__2680), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl[1]), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_0_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_0__455), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl[0]), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_rx_data_q_7_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_rx_data_7_), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_data_q_7__2714), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_rx_data_q_6_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_rx_data_6_), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_data_q_6__2716), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_rx_data_q_5_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_rx_data_5_), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_data_q_5__2718), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_rx_data_q_4_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_rx_data_4_), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_data_q_4__2720), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_rx_data_q_3_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_rx_data_3_), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_data_q_3__2722), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_rx_data_q_2_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_rx_data_2_), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_data_q[2]), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_rx_data_q_1_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_rx_data_1_), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_data_q_1__2725), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_22_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_22__2702), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl[22]), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_21_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_21__451), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl[21]), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_20_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_20__2703), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl[20]), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_19_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_19__2704), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl[19]), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_18_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_18__2681), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl[18]), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_17_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_17__2682), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl[17]), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_16_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_16__2683), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl[16]), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_15_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_15__2684), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl[15]), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_14_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_14__469), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl[14]), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_13_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_13__448), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl[13]), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_12_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_12__461), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl[12]), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_11_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_11__2685), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl[11]), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_10_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_10__2686), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl[10]), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_9_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_9__2687), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl[9]), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_8_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_8__2688), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl[8]), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_37_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_37__2712), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl[37]), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_36_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_36__2713), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl[36]), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_35_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_35__479), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl[35]), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_34_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_34__477), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl[34]), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_33_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_33__2692), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl[33]), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_32_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_32__456), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl[32]), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_31_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_31__2693), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl[31]), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_30_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_30__2694), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl[30]), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_29_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_29__2695), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl[29]), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_28_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_28__2696), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl[28]), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_27_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_27__2697), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl[27]), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_26_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_26__2698), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl[26]), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_25_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_25__2699), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl[25]), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_24_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_24__2700), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl[24]), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_23_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_23__2701), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl[23]), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_52_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_52__2732), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl[52]), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_51_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_51__2733), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl[51]), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_50_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_50__2734), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl[50]), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_49_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_49__2735), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl[49]), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_48_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_48__2705), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl[48]), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_47_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_47__2706), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl[47]), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_46_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_46__470), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl[46]), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_45_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_45__449), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl[45]), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_44_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_44__462), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl[44]), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_43_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_43__2707), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl[43]), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_42_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_42__2708), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl[42]), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_41_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_41__2709), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl[41]), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_40_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_40__2710), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl[40]), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_39_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_39__2711), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl[39]), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_38_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_38__473), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl[38]), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_RX_TLP_TSN_3_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_tlp_tsn_d[3]), + .Q(com_llm_llm_rx_top_rx_tlp_tsn[3]), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_RX_TLP_TSN_2_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_tlp_tsn_d[2]), + .Q(com_llm_llm_rx_top_rx_tlp_tsn[2]), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_RX_TLP_TSN_1_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_tlp_tsn_d[1]), + .Q(com_llm_llm_rx_top_rx_tlp_tsn[1]), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_RX_TLP_TSN_0_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_tlp_tsn_d[0]), + .Q(com_llm_llm_rx_top_rx_tlp_tsn[0]), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_63_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_63__2715), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl[63]), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_62_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_62__2717), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl[62]), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_61_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_61__2719), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl[61]), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_60_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_60__2721), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl[60]), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_59_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_59__2723), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl[59]), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_58_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_58__2724), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl[58]), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_57_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_57__2726), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl[57]), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_56_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_56__2728), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl[56]), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_55_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_55__2729), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl[55]), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_54_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_54__2730), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl[54]), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_53_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_53__2731), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl[53]), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_RX_TLP_TSN_11_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_tlp_tsn_d[11]), + .Q(com_llm_llm_rx_top_rx_tlp_tsn[11]), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_RX_TLP_TSN_10_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_tlp_tsn_d[10]), + .Q(com_llm_llm_rx_top_rx_tlp_tsn[10]), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_RX_TLP_TSN_9_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_tlp_tsn_d[9]), + .Q(com_llm_llm_rx_top_rx_tlp_tsn[9]), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_RX_TLP_TSN_8_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_tlp_tsn_d[8]), + .Q(com_llm_llm_rx_top_rx_tlp_tsn[8]), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_RX_TLP_TSN_7_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_tlp_tsn_d[7]), + .Q(com_llm_llm_rx_top_rx_tlp_tsn[7]), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_RX_TLP_TSN_6_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_tlp_tsn_d[6]), + .Q(com_llm_llm_rx_top_rx_tlp_tsn[6]), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_RX_TLP_TSN_5_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_tlp_tsn_d[5]), + .Q(com_llm_llm_rx_top_rx_tlp_tsn[5]), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_RX_TLP_TSN_4_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_tlp_tsn_d[4]), + .Q(com_llm_llm_rx_top_rx_tlp_tsn[4]), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_3_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_rx_data_11_), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_3__478), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_2_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_rx_data_10_), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_2__476), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_1_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_rx_data_9_), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_1__2680), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_0_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_rx_data_8_), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_0__455), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_18_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_rx_data_26_), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_18__2681), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_17_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_rx_data_25_), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_17__2682), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_16_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_rx_data_24_), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_16__2683), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_15_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_rx_data_23_), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_15__2684), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_14_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_rx_data_22_), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_14__469), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_13_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_rx_data_21_), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_13__448), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_12_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_rx_data_20_), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_12__461), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_11_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_rx_data_19_), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_11__2685), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_10_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_rx_data_18_), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_10__2686), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_9_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_rx_data_17_), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_9__2687), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_8_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_rx_data_16_), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_8__2688), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_7_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_rx_data_15_), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_7__2689), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_6_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_rx_data_14_), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_6__472), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_5_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_rx_data_13_), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_5__2690), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_4_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_rx_data_12_), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_4__2691), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_33_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_rx_data_41_), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_33__2692), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_32_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_rx_data_40_), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_32__456), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_31_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_rx_data_39_), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_31__2693), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_30_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_rx_data_38_), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_30__2694), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_29_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_rx_data_37_), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_29__2695), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_28_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_rx_data_36_), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_28__2696), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_27_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_rx_data_35_), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_27__2697), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_26_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_rx_data_34_), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_26__2698), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_25_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_rx_data_33_), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_25__2699), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_24_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_rx_data_32_), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_24__2700), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_23_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_rx_data_31_), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_23__2701), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_22_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_rx_data_30_), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_22__2702), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_21_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_rx_data_29_), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_21__451), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_20_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_rx_data_28_), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_20__2703), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_19_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_rx_data_27_), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_19__2704), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_48_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_rx_data_56_), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_48__2705), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_47_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_rx_data_55_), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_47__2706), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_46_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_rx_data_54_), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_46__470), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_45_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_rx_data_53_), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_45__449), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_44_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_rx_data_52_), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_44__462), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_43_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_rx_data_51_), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_43__2707), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_42_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_rx_data_50_), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_42__2708), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_41_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_rx_data_49_), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_41__2709), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_40_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_rx_data_48_), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_40__2710), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_39_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_rx_data_47_), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_39__2711), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_38_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_rx_data_46_), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_38__473), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_37_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_rx_data_45_), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_37__2712), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_36_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_rx_data_44_), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_36__2713), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_35_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_rx_data_43_), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_35__479), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_34_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_rx_data_42_), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_34__477), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_63_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_data_q_7__2714), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_63__2715), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_62_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_data_q_6__2716), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_62__2717), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_61_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_data_q_5__2718), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_61__2719), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_60_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_data_q_4__2720), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_60__2721), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_59_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_data_q_3__2722), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_59__2723), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_58_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_data_q[2]), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_58__2724), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_57_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_data_q_1__2725), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_57__2726), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_56_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_data_q_0__2727), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_56__2728), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_55_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_rx_data_63_), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_55__2729), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_54_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_rx_data_62_), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_54__2730), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_53_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_rx_data_61_), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_53__2731), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_52_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_rx_data_60_), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_52__2732), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_51_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_rx_data_59_), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_51__2733), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_50_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_rx_data_58_), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_50__2734), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_49_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_rx_data_57_), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_49__2735), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d64_14_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_new_c64[14]), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d64_14__467), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d64_13_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_new_c64[13]), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d64_13__468), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d64_12_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_new_c64[12]), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d64_12__464), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d64_11_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_new_c64[11]), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d64_11__475), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d64_10_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_new_c64[10]), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d64_10__2736), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d64_9_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_new_c64[9]), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d64_9__466), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d64_8_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_new_c64[8]), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d64_8__457), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d64_7_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_new_c64[7]), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d64_7__405), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d64_6_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_new_c64[6]), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d64_6__474), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d64_5_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_new_c64[5]), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d64_5__98), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d64_4_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_new_c64[4]), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d64_4__364), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d64_3_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_new_c64[3]), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d64_3__2737), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d64_2_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_new_c64[2]), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d64_2__2738), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d64_1_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_new_c64[1]), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d64_1__2739), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d64_0_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_new_c64[0]), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d64_0__458), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d64_29_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_new_c64[29]), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d64_29__369), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d64_28_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_new_c64[28]), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d64_28__401), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d64_27_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_new_c64[27]), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d64_27__460), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d64_26_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_new_c64[26]), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d64_26__447), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d64_25_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_new_c64[25]), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d64_25__465), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d64_24_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_new_c64[24]), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d64_24__395), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d64_23_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_new_c64[23]), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d64_23__454), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d64_22_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_new_c64[22]), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d64_22__393), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d64_21_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_new_c64[21]), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d64_21__459), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d64_20_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_new_c64[20]), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d64_20__403), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d64_19_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_new_c64[19]), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d64_19__94), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d64_18_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_new_c64[18]), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d64_18__394), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d64_17_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_new_c64[17]), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d64_17__471), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d64_16_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_new_c64[16]), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d64_16__92), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d64_15_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_new_c64[15]), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d64_15__355), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d16_12_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_new_c16[12]), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d16[12]), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d16_11_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_new_c16[11]), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d16[11]), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d16_10_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_new_c16[10]), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d16[10]), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d16_9_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_new_c16[9]), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d16[9]), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d16_8_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_new_c16[8]), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d16[8]), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d16_7_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_new_c16[7]), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d16[7]), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d16_6_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_new_c16[6]), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d16[6]), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d16_5_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_new_c16[5]), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d16[5]), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d16_4_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_new_c16[4]), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d16[4]), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d16_3_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_new_c16[3]), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d16[3]), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d16_2_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_new_c16[2]), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d16[2]), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d16_1_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_new_c16[1]), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d16[1]), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d16_0_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_new_c16[0]), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d16[0]), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d64_31_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_new_c64[31]), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d64_31__463), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d64_30_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_new_c64[30]), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d64_30__359), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d16_27_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_new_c16[27]), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d16[27]), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d16_26_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_new_c16[26]), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d16[26]), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d16_25_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_new_c16[25]), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d16[25]), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d16_24_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_new_c16[24]), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d16[24]), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d16_23_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_new_c16[23]), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d16[23]), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d16_22_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_new_c16[22]), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d16[22]), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d16_21_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_new_c16[21]), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d16[21]), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d16_20_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_new_c16[20]), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d16[20]), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d16_19_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_new_c16[19]), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d16[19]), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d16_18_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_new_c16[18]), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d16[18]), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d16_17_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_new_c16[17]), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d16[17]), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d16_16_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_new_c16[16]), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d16[16]), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d16_15_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_new_c16[15]), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d16[15]), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d16_14_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_new_c16[14]), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d16[14]), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d16_13_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_new_c16[13]), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d16[13]), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d16_31_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_new_c16[31]), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d16[31]), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d16_30_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_new_c16[30]), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d16[30]), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d16_29_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_new_c16[29]), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d16[29]), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d16_28_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_new_c16[28]), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d16[28]), + .CLR(plm_link_up_i) + ); + FDCE com_llm_llm_rx_top_llm_rx_tlp_crc_tlp_nullified_latch ( + .CE(com_llm_llm_rx_top_rx_tlp_eof_n_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_rx_tlp_nullified), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_tlp_nullified_latch_2740), + .CLR(plm_link_up_i) + ); + FDCE com_llm_llm_rx_top_llm_rx_tlp_crc_frame_error_latch ( + .CE(com_llm_llm_rx_top_rx_tlp_eof_n_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_rx_tferr_n_i), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_frame_error_latch_2741), + .CLR(plm_link_up_i) + ); + FDPE com_llm_llm_rx_top_llm_rx_tlp_crc_start_high_latch ( + .PRE(plm_link_up_i), + .CE(com_llm_llm_rx_top_rx_tlp_sof_n_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_start_high_latch_3), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_start_high_latch_452) + ); + FDCE com_llm_llm_rx_top_llm_rx_tlp_crc_end_low_latch ( + .CE(com_llm_llm_rx_top_rx_tlp_eof_n_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_end_low_latch_3), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_end_low_latch_2742), + .CLR(plm_link_up_i) + ); + FDPE com_llm_llm_rx_top_llm_rx_tlp_crc_RX_RSRC_RDY_N ( + .PRE(plm_link_up_i), + .CE(com_llm_llm_rx_top_llm_rx_tlp_crc_N_59482_i_2743), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rsof_nd_2744), + .Q(com_llm_rx_rsrc_rdy_n) + ); + FDCE com_llm_llm_rx_top_llm_rx_tlp_crc_tlp_in_progress ( + .CE(com_llm_llm_rx_top_llm_rx_tlp_crc_N_31582_i_0), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_rx_tlp_eof_n), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_tlp_in_progress_2745), + .CLR(plm_link_up_i) + ); + FDCE com_llm_llm_rx_top_llm_rx_tlp_crc_rx_tlp_tsn_dd_11_ ( + .CE(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_tlp_sof_nq_i_2750), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_tlp_tsn_dd_5_i_m3_i_m3_0[11]), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_tlp_tsn_dd[11]), + .CLR(plm_link_up_i) + ); + FDCE com_llm_llm_rx_top_llm_rx_tlp_crc_rx_tlp_tsn_dd_10_ ( + .CE(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_tlp_sof_nq_i_2750), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_tlp_tsn_dd_5_i_m3_i_m3_0[10]), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_tlp_tsn_dd[10]), + .CLR(plm_link_up_i) + ); + FDCE com_llm_llm_rx_top_llm_rx_tlp_crc_rx_tlp_tsn_dd_9_ ( + .CE(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_tlp_sof_nq_i_2750), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_tlp_tsn_dd_5_i_m3_i_m3_0[9]), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_tlp_tsn_dd[9]), + .CLR(plm_link_up_i) + ); + FDCE com_llm_llm_rx_top_llm_rx_tlp_crc_rx_tlp_tsn_dd_8_ ( + .CE(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_tlp_sof_nq_i_2750), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_tlp_tsn_dd_5_i_m3_i_m3_0[8]), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_tlp_tsn_dd[8]), + .CLR(plm_link_up_i) + ); + FDCE com_llm_llm_rx_top_llm_rx_tlp_crc_rx_tlp_tsn_dd_7_ ( + .CE(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_tlp_sof_nq_i_2750), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_tlp_tsn_dd_5_i_m3_i_m3_0[7]), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_tlp_tsn_dd[7]), + .CLR(plm_link_up_i) + ); + FDCE com_llm_llm_rx_top_llm_rx_tlp_crc_rx_tlp_tsn_dd_6_ ( + .CE(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_tlp_sof_nq_i_2750), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_tlp_tsn_dd_5_i_m3_i_m3_0[6]), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_tlp_tsn_dd[6]), + .CLR(plm_link_up_i) + ); + FDCE com_llm_llm_rx_top_llm_rx_tlp_crc_rx_tlp_tsn_dd_5_ ( + .CE(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_tlp_sof_nq_i_2750), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_tlp_tsn_dd_5_i_m3_0[5]), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_tlp_tsn_dd[5]), + .CLR(plm_link_up_i) + ); + FDCE com_llm_llm_rx_top_llm_rx_tlp_crc_rx_tlp_tsn_dd_4_ ( + .CE(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_tlp_sof_nq_i_2750), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_tlp_tsn_dd_5_i_m3_0[4]), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_tlp_tsn_dd[4]), + .CLR(plm_link_up_i) + ); + FDCE com_llm_llm_rx_top_llm_rx_tlp_crc_rx_tlp_tsn_dd_3_ ( + .CE(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_tlp_sof_nq_i_2750), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_tlp_tsn_dd_5_i_m3_0[3]), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_tlp_tsn_dd[3]), + .CLR(plm_link_up_i) + ); + FDCE com_llm_llm_rx_top_llm_rx_tlp_crc_rx_tlp_tsn_dd_2_ ( + .CE(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_tlp_sof_nq_i_2750), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_tlp_tsn_dd_5_i_m3_0[2]), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_tlp_tsn_dd[2]), + .CLR(plm_link_up_i) + ); + FDCE com_llm_llm_rx_top_llm_rx_tlp_crc_rx_tlp_tsn_dd_1_ ( + .CE(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_tlp_sof_nq_i_2750), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_tlp_tsn_dd_5_i_m3_0[1]), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_tlp_tsn_dd[1]), + .CLR(plm_link_up_i) + ); + FDCE com_llm_llm_rx_top_llm_rx_tlp_crc_rx_tlp_tsn_dd_0_ ( + .CE(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_tlp_sof_nq_i_2750), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_tlp_tsn_dd_5_i_m3_0[0]), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_tlp_tsn_dd[0]), + .CLR(plm_link_up_i) + ); + FDPE com_llm_llm_rx_top_llm_rx_tlp_crc_rx_tlp_sof_nqq ( + .PRE(plm_link_up_i), + .CE(com_llm_llm_rx_top_llm_rx_tlp_crc_N_87782_i_2746), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_tlp_sof_nq_2751), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_tlp_sof_nqq_2747) + ); + FDPE com_llm_llm_rx_top_llm_rx_tlp_crc_rx_tlp_eof_nq ( + .PRE(plm_link_up_i), + .CE(com_llm_llm_rx_top_llm_rx_tlp_crc_N_87781_i_2748), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_rx_tlp_eof_n), + .Q(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_tlp_eof_nq_2749) + ); + INV com_llm_llm_rx_top_llm_rx_tlp_crc_rx_tlp_sof_nq_i ( + .I(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_tlp_sof_nq_2751), + .O(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_tlp_sof_nq_i_2750) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_end_low_latch_3_0_a2_0_a2.INIT = 4'h2; + LUT2_L com_llm_llm_rx_top_llm_rx_tlp_crc_end_low_latch_3_0_a2_0_a2 ( + .I0(com_llm_llm_rx_top_rx_tlp_sof_n), + .I1(com_llm_llm_rx_top_rx_tlp_vld_l_n), + .LO(com_llm_llm_rx_top_llm_rx_tlp_crc_end_low_latch_3) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_N_85330_i.INIT = 16'hEEEF; + LUT4_L com_llm_llm_rx_top_llm_rx_tlp_crc_N_85330_i ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_un1_RX_RSRC_DSC_N17_0_0_m2_0_2756), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_RX_TLP_CRC_ERR_N_6_i_0_m2_0_2755), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_RX_TLP_CRC_ERR_N_6_i_0_o3_2754), + .I3(com_llm_llm_rx_top_llm_rx_tlp_crc_N_85330_i_1_2753), + .LO(com_llm_llm_rx_top_llm_rx_tlp_crc_N_85330_i_2752) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_un4_crc32_com_ok_0_I_36.INIT = 4'h1; + LUT2 com_llm_llm_rx_top_llm_rx_tlp_crc_un4_crc32_com_ok_0_I_36 ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_N_102), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_N_103), + .O(com_llm_llm_rx_top_llm_rx_tlp_crc_N_99_0) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_un3_crc32_com_ok_0_I_36.INIT = 4'h8; + LUT2 com_llm_llm_rx_top_llm_rx_tlp_crc_un3_crc32_com_ok_0_I_36 ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_N_102), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_N_103), + .O(com_llm_llm_rx_top_llm_rx_tlp_crc_N_99) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_un3_crc32_res_ok_7_and_0_a2.INIT = 16'h0001; + LUT4 com_llm_llm_rx_top_llm_rx_tlp_crc_un3_crc32_res_ok_7_and_0_a2 ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d16[28]), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d16[29]), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d16[30]), + .I3(com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d16[31]), + .O(com_llm_llm_rx_top_llm_rx_tlp_crc_un3_crc32_res_ok_7_and) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_un3_crc32_res_ok_6_and_0_a2.INIT = 16'h0001; + LUT4 com_llm_llm_rx_top_llm_rx_tlp_crc_un3_crc32_res_ok_6_and_0_a2 ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d16[24]), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d16[25]), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d16[26]), + .I3(com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d16[27]), + .O(com_llm_llm_rx_top_llm_rx_tlp_crc_un3_crc32_res_ok_6_and) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_un3_crc32_res_ok_5_and_0_a2.INIT = 4'h4; + LUT2 com_llm_llm_rx_top_llm_rx_tlp_crc_un3_crc32_res_ok_5_and_0_a2 ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d16[20]), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_un3_crc32_res_ok_5_and_1_0), + .O(com_llm_llm_rx_top_llm_rx_tlp_crc_un3_crc32_res_ok_5_and) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_un3_crc32_res_ok_4_and_0_a2.INIT = 4'h4; + LUT2 com_llm_llm_rx_top_llm_rx_tlp_crc_un3_crc32_res_ok_4_and_0_a2 ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d16[18]), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_un6_crc32_res_ok_1_and_1), + .O(com_llm_llm_rx_top_llm_rx_tlp_crc_un3_crc32_res_ok_4_and) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_un3_crc32_res_ok_3_and_0_a2.INIT = 16'h0001; + LUT4 com_llm_llm_rx_top_llm_rx_tlp_crc_un3_crc32_res_ok_3_and_0_a2 ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d16[12]), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d16[13]), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d16[14]), + .I3(com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d16[15]), + .O(com_llm_llm_rx_top_llm_rx_tlp_crc_un3_crc32_res_ok_3_and) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_un3_crc32_res_ok_2_and_0_a2.INIT = 16'h0001; + LUT4 com_llm_llm_rx_top_llm_rx_tlp_crc_un3_crc32_res_ok_2_and_0_a2 ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d16[8]), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d16[9]), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d16[10]), + .I3(com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d16[11]), + .O(com_llm_llm_rx_top_llm_rx_tlp_crc_un3_crc32_res_ok_2_and) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_un3_crc32_res_ok_1_and_0_a2.INIT = 16'h0001; + LUT4 com_llm_llm_rx_top_llm_rx_tlp_crc_un3_crc32_res_ok_1_and_0_a2 ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d16[4]), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d16[5]), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d16[6]), + .I3(com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d16[7]), + .O(com_llm_llm_rx_top_llm_rx_tlp_crc_un3_crc32_res_ok_1_and) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_un3_crc32_res_ok_0_and_0_a2.INIT = 16'h0001; + LUT4 com_llm_llm_rx_top_llm_rx_tlp_crc_un3_crc32_res_ok_0_and_0_a2 ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d16[0]), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d16[1]), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d16[2]), + .I3(com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d16[3]), + .O(com_llm_llm_rx_top_llm_rx_tlp_crc_un3_crc32_res_ok_0_and) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_un6_crc32_res_ok_7_and_0_a2.INIT = 16'h8000; + LUT4 com_llm_llm_rx_top_llm_rx_tlp_crc_un6_crc32_res_ok_7_and_0_a2 ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d16[25]), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d16[26]), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d16[30]), + .I3(com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d16[31]), + .O(com_llm_llm_rx_top_llm_rx_tlp_crc_un6_crc32_res_ok_7_and) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_un6_crc32_res_ok_6_and_0_a2.INIT = 16'h8000; + LUT4 com_llm_llm_rx_top_llm_rx_tlp_crc_un6_crc32_res_ok_6_and_0_a2 ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d16[14]), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d16[15]), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d16[18]), + .I3(com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d16[24]), + .O(com_llm_llm_rx_top_llm_rx_tlp_crc_un6_crc32_res_ok_6_and) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_un6_crc32_res_ok_5_and_0_a2.INIT = 16'h8000; + LUT4 com_llm_llm_rx_top_llm_rx_tlp_crc_un6_crc32_res_ok_5_and_0_a2 ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d16[8]), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d16[10]), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d16[11]), + .I3(com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d16[12]), + .O(com_llm_llm_rx_top_llm_rx_tlp_crc_un6_crc32_res_ok_5_and) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_un6_crc32_res_ok_4_and_0_a2.INIT = 16'h8000; + LUT4 com_llm_llm_rx_top_llm_rx_tlp_crc_un6_crc32_res_ok_4_and_0_a2 ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d16[3]), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d16[4]), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d16[5]), + .I3(com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d16[6]), + .O(com_llm_llm_rx_top_llm_rx_tlp_crc_un6_crc32_res_ok_4_and) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_un6_crc32_res_ok_3_and_0_a2.INIT = 16'h0008; + LUT4 com_llm_llm_rx_top_llm_rx_tlp_crc_un6_crc32_res_ok_3_and_0_a2 ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d16[0]), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d16[1]), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d16[28]), + .I3(com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d16[29]), + .O(com_llm_llm_rx_top_llm_rx_tlp_crc_un6_crc32_res_ok_3_and) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_un6_crc32_res_ok_2_and_0_a2.INIT = 4'h4; + LUT2 com_llm_llm_rx_top_llm_rx_tlp_crc_un6_crc32_res_ok_2_and_0_a2 ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d16[27]), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_un3_crc32_res_ok_5_and_1_0), + .O(com_llm_llm_rx_top_llm_rx_tlp_crc_un6_crc32_res_ok_2_and) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_un6_crc32_res_ok_1_and_0_a2.INIT = 4'h4; + LUT2 com_llm_llm_rx_top_llm_rx_tlp_crc_un6_crc32_res_ok_1_and_0_a2 ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d16[20]), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_un6_crc32_res_ok_1_and_1), + .O(com_llm_llm_rx_top_llm_rx_tlp_crc_un6_crc32_res_ok_1_and) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_un6_crc32_res_ok_0_and_0_a2.INIT = 16'h0001; + LUT4 com_llm_llm_rx_top_llm_rx_tlp_crc_un6_crc32_res_ok_0_and_0_a2 ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d16[2]), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d16[7]), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d16[9]), + .I3(com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d16[13]), + .O(com_llm_llm_rx_top_llm_rx_tlp_crc_un6_crc32_res_ok_0_and) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_un3_crc32_com_ok_0_I_144.INIT = 4'h8; + LUT2 com_llm_llm_rx_top_llm_rx_tlp_crc_un3_crc32_com_ok_0_I_144 ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_N_6), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_N_7), + .O(com_llm_llm_rx_top_llm_rx_tlp_crc_N_3_0) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_un3_crc32_com_ok_0_I_135.INIT = 4'h8; + LUT2 com_llm_llm_rx_top_llm_rx_tlp_crc_un3_crc32_com_ok_0_I_135 ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_N_14), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_N_15), + .O(com_llm_llm_rx_top_llm_rx_tlp_crc_N_11_0) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_un3_crc32_com_ok_0_I_126.INIT = 4'h8; + LUT2 com_llm_llm_rx_top_llm_rx_tlp_crc_un3_crc32_com_ok_0_I_126 ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_N_22), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_N_23), + .O(com_llm_llm_rx_top_llm_rx_tlp_crc_N_19_0) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_un3_crc32_com_ok_0_I_117.INIT = 4'h8; + LUT2 com_llm_llm_rx_top_llm_rx_tlp_crc_un3_crc32_com_ok_0_I_117 ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_N_30), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_N_31), + .O(com_llm_llm_rx_top_llm_rx_tlp_crc_N_27_0) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_un3_crc32_com_ok_0_I_108.INIT = 4'h8; + LUT2 com_llm_llm_rx_top_llm_rx_tlp_crc_un3_crc32_com_ok_0_I_108 ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_N_38), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_N_39), + .O(com_llm_llm_rx_top_llm_rx_tlp_crc_N_35_0) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_un3_crc32_com_ok_0_I_99.INIT = 4'h8; + LUT2 com_llm_llm_rx_top_llm_rx_tlp_crc_un3_crc32_com_ok_0_I_99 ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_N_46), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_N_47), + .O(com_llm_llm_rx_top_llm_rx_tlp_crc_N_43_0) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_un3_crc32_com_ok_0_I_90.INIT = 4'h8; + LUT2 com_llm_llm_rx_top_llm_rx_tlp_crc_un3_crc32_com_ok_0_I_90 ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_N_54), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_N_55), + .O(com_llm_llm_rx_top_llm_rx_tlp_crc_N_51_0) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_un3_crc32_com_ok_0_I_81.INIT = 4'h8; + LUT2 com_llm_llm_rx_top_llm_rx_tlp_crc_un3_crc32_com_ok_0_I_81 ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_N_62), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_N_63), + .O(com_llm_llm_rx_top_llm_rx_tlp_crc_N_59_0) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_un3_crc32_com_ok_0_I_72.INIT = 4'h8; + LUT2 com_llm_llm_rx_top_llm_rx_tlp_crc_un3_crc32_com_ok_0_I_72 ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_N_70), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_N_71), + .O(com_llm_llm_rx_top_llm_rx_tlp_crc_N_67_0) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_un3_crc32_com_ok_0_I_63.INIT = 4'h8; + LUT2 com_llm_llm_rx_top_llm_rx_tlp_crc_un3_crc32_com_ok_0_I_63 ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_N_78), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_N_79), + .O(com_llm_llm_rx_top_llm_rx_tlp_crc_N_75_0) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_un3_crc32_com_ok_0_I_54.INIT = 4'h8; + LUT2 com_llm_llm_rx_top_llm_rx_tlp_crc_un3_crc32_com_ok_0_I_54 ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_N_86), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_N_87), + .O(com_llm_llm_rx_top_llm_rx_tlp_crc_N_83_0) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_un3_crc32_com_ok_0_I_45.INIT = 4'h8; + LUT2 com_llm_llm_rx_top_llm_rx_tlp_crc_un3_crc32_com_ok_0_I_45 ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_N_94), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_N_95), + .O(com_llm_llm_rx_top_llm_rx_tlp_crc_N_91_0) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_un3_crc32_com_ok_0_I_27.INIT = 4'h8; + LUT2 com_llm_llm_rx_top_llm_rx_tlp_crc_un3_crc32_com_ok_0_I_27 ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_N_110), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_N_111), + .O(com_llm_llm_rx_top_llm_rx_tlp_crc_N_107_0) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_un3_crc32_com_ok_0_I_18.INIT = 4'h8; + LUT2 com_llm_llm_rx_top_llm_rx_tlp_crc_un3_crc32_com_ok_0_I_18 ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_N_118), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_N_119), + .O(com_llm_llm_rx_top_llm_rx_tlp_crc_N_115_0) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_un3_crc32_com_ok_0_I_9.INIT = 4'h8; + LUT2 com_llm_llm_rx_top_llm_rx_tlp_crc_un3_crc32_com_ok_0_I_9 ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_N_126), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_N_127), + .O(com_llm_llm_rx_top_llm_rx_tlp_crc_N_123_0) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_un4_crc32_com_ok_0_I_144.INIT = 4'h1; + LUT2 com_llm_llm_rx_top_llm_rx_tlp_crc_un4_crc32_com_ok_0_I_144 ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_N_6), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_N_7), + .O(com_llm_llm_rx_top_llm_rx_tlp_crc_N_3) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_un4_crc32_com_ok_0_I_135.INIT = 4'h1; + LUT2 com_llm_llm_rx_top_llm_rx_tlp_crc_un4_crc32_com_ok_0_I_135 ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_N_14), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_N_15), + .O(com_llm_llm_rx_top_llm_rx_tlp_crc_N_11) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_un4_crc32_com_ok_0_I_126.INIT = 4'h1; + LUT2 com_llm_llm_rx_top_llm_rx_tlp_crc_un4_crc32_com_ok_0_I_126 ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_N_22), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_N_23), + .O(com_llm_llm_rx_top_llm_rx_tlp_crc_N_19) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_un4_crc32_com_ok_0_I_117.INIT = 4'h1; + LUT2 com_llm_llm_rx_top_llm_rx_tlp_crc_un4_crc32_com_ok_0_I_117 ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_N_30), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_N_31), + .O(com_llm_llm_rx_top_llm_rx_tlp_crc_N_27) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_un4_crc32_com_ok_0_I_108.INIT = 4'h1; + LUT2 com_llm_llm_rx_top_llm_rx_tlp_crc_un4_crc32_com_ok_0_I_108 ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_N_38), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_N_39), + .O(com_llm_llm_rx_top_llm_rx_tlp_crc_N_35) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_un4_crc32_com_ok_0_I_99.INIT = 4'h1; + LUT2 com_llm_llm_rx_top_llm_rx_tlp_crc_un4_crc32_com_ok_0_I_99 ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_N_46), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_N_47), + .O(com_llm_llm_rx_top_llm_rx_tlp_crc_N_43) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_un4_crc32_com_ok_0_I_90.INIT = 4'h1; + LUT2 com_llm_llm_rx_top_llm_rx_tlp_crc_un4_crc32_com_ok_0_I_90 ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_N_54), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_N_55), + .O(com_llm_llm_rx_top_llm_rx_tlp_crc_N_51) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_un4_crc32_com_ok_0_I_81.INIT = 4'h1; + LUT2 com_llm_llm_rx_top_llm_rx_tlp_crc_un4_crc32_com_ok_0_I_81 ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_N_62), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_N_63), + .O(com_llm_llm_rx_top_llm_rx_tlp_crc_N_59) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_un4_crc32_com_ok_0_I_72.INIT = 4'h1; + LUT2 com_llm_llm_rx_top_llm_rx_tlp_crc_un4_crc32_com_ok_0_I_72 ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_N_70), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_N_71), + .O(com_llm_llm_rx_top_llm_rx_tlp_crc_N_67) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_un4_crc32_com_ok_0_I_63.INIT = 4'h1; + LUT2 com_llm_llm_rx_top_llm_rx_tlp_crc_un4_crc32_com_ok_0_I_63 ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_N_78), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_N_79), + .O(com_llm_llm_rx_top_llm_rx_tlp_crc_N_75) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_un4_crc32_com_ok_0_I_54.INIT = 4'h1; + LUT2 com_llm_llm_rx_top_llm_rx_tlp_crc_un4_crc32_com_ok_0_I_54 ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_N_86), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_N_87), + .O(com_llm_llm_rx_top_llm_rx_tlp_crc_N_83) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_un4_crc32_com_ok_0_I_45.INIT = 4'h1; + LUT2 com_llm_llm_rx_top_llm_rx_tlp_crc_un4_crc32_com_ok_0_I_45 ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_N_94), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_N_95), + .O(com_llm_llm_rx_top_llm_rx_tlp_crc_N_91) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_un4_crc32_com_ok_0_I_27.INIT = 4'h1; + LUT2 com_llm_llm_rx_top_llm_rx_tlp_crc_un4_crc32_com_ok_0_I_27 ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_N_110), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_N_111), + .O(com_llm_llm_rx_top_llm_rx_tlp_crc_N_107) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_un4_crc32_com_ok_0_I_18.INIT = 4'h1; + LUT2 com_llm_llm_rx_top_llm_rx_tlp_crc_un4_crc32_com_ok_0_I_18 ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_N_118), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_N_119), + .O(com_llm_llm_rx_top_llm_rx_tlp_crc_N_115) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_un4_crc32_com_ok_0_I_9.INIT = 4'h1; + LUT2 com_llm_llm_rx_top_llm_rx_tlp_crc_un4_crc32_com_ok_0_I_9 ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_N_126), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_N_127), + .O(com_llm_llm_rx_top_llm_rx_tlp_crc_N_123) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d16_new_c16_1_0_17_.INIT = 4'h6; + LUT2 com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d16_new_c16_1_0_17_ ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d64_1__2739), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d64_30__359), + .O(com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d16_new_c16_1_0_17__2762) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d16_new_c16_1_1_18_.INIT = 4'h6; + LUT2 com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d16_new_c16_1_1_18_ ( + .I0(d16_i_m3_0_6_), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d64_22__393), + .O(com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d16_new_c16_1_18__2766) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d16_new_c16_1_1_0_11_.INIT = 16'h5A66; + LUT4 com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d16_new_c16_1_1_0_11_ ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d64_28__401), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_11__2685), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_rx_rd_sl_d_43__2707), + .I3(com_llm_llm_rx_top_llm_rx_tlp_crc_start_high_latch_q_450), + .O(N_12105_1) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d16_new_c16_1_0_26_.INIT = 4'h6; + LUT2 com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d16_new_c16_1_0_26_ ( + .I0(d16_i_m3_i_m3_0_0_), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d64_10__2736), + .O(com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d16_new_c16_1_0_26__2760) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d16_new_c16_1_0_9_.INIT = 4'h6; + LUT2 com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d16_new_c16_1_0_9_ ( + .I0(N_12048_1), + .I1(N_12105_1), + .O(com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d16_new_c16_1_0_9__2757) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d16_new_c16_1_1_19_.INIT = 16'h6996; + LUT4 com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d16_new_c16_1_1_19_ ( + .I0(G_302_95), + .I1(N_11978_1), + .I2(d16_i_m3_0_8_), + .I3(com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d64_24__395), + .O(com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d16_new_c16_1_19__2761) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d16_new_c16_1_1_20_.INIT = 8'h96; + LUT3 com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d16_new_c16_1_1_20_ ( + .I0(G_308_414), + .I1(N_11969_1), + .I2(N_12105_1), + .O(com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d16_new_c16_1_20__2764) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d16_new_c16_1_2_31_.INIT = 16'h6996; + LUT4 com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d16_new_c16_1_2_31_ ( + .I0(N_11969_1), + .I1(N_12048_1), + .I2(N_12128_1), + .I3(com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d64_15__355), + .O(com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d16_new_c16_1_2[31]) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d16_new_c16_1_1_16_.INIT = 16'h6996; + LUT4 com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d16_new_c16_1_1_16_ ( + .I0(N_12128_1), + .I1(d16_i_m3_i_m3_0_13_), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d64_0__458), + .I3(com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d64_29__369), + .O(com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d16_new_c16_1_1_16__2763) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d16_new_c16_1_1_3_.INIT = 8'h96; + LUT3 com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d16_new_c16_1_1_3_ ( + .I0(N_11969_1), + .I1(N_11972_1), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d64_24__395), + .O(com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d16_new_c16_1_1_3__2759) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d16_new_c16_1_1_4_.INIT = 8'h96; + LUT3 com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d16_new_c16_1_1_4_ ( + .I0(N_12045_1), + .I1(G_471_419), + .I2(d16_i_m3_0_8_), + .O(com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d16_new_c16_1_1_4__2758) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d16_new_c16_1_1_17_.INIT = 4'h6; + LUT2 com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d16_new_c16_1_1_17_ ( + .I0(G_484_374), + .I1(d16_i_m3_0_6_), + .O(com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d16_new_c16_1_17__2765) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d16_new_c16_1_12_.INIT = 16'h6996; + LUT4_L com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d16_new_c16_1_12_ ( + .I0(G_299_410), + .I1(N_12127_1), + .I2(G_471_419), + .I3(com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d16_new_c16_1_11__2767), + .LO(com_llm_llm_rx_top_llm_rx_tlp_crc_new_c16[12]) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d16_new_c16_1_11_.INIT = 8'h96; + LUT3_L com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d16_new_c16_1_11_ ( + .I0(G_313_415), + .I1(G_387_360), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d16_new_c16_1_11__2767), + .LO(com_llm_llm_rx_top_llm_rx_tlp_crc_new_c16[11]) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d16_new_c16_1_10_.INIT = 16'h6996; + LUT4_L com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d16_new_c16_1_10_ ( + .I0(G_299_410), + .I1(N_11963_1), + .I2(G_387_360), + .I3(d16_i_m3_i_m3_0_0_), + .LO(com_llm_llm_rx_top_llm_rx_tlp_crc_new_c16[10]) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d16_new_c16_1_9_.INIT = 16'h6996; + LUT4_L com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d16_new_c16_1_9_ ( + .I0(G_299_410), + .I1(G_305_413), + .I2(G_313_415), + .I3(com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d16_new_c16_1_0_9__2757), + .LO(com_llm_llm_rx_top_llm_rx_tlp_crc_new_c16[9]) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d16_new_c16_1_8_.INIT = 16'h9669; + LUT4_L com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d16_new_c16_1_8_ ( + .I0(G_308_414), + .I1(G_314_416), + .I2(N_12045_1), + .I3(N_31590_i_0), + .LO(com_llm_llm_rx_top_llm_rx_tlp_crc_new_c16[8]) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d16_new_c16_1_7_.INIT = 8'h96; + LUT3_L com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d16_new_c16_1_7_ ( + .I0(G_299_410), + .I1(G_319_93), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d16_new_c16_1_19__2761), + .LO(com_llm_llm_rx_top_llm_rx_tlp_crc_new_c16[7]) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d16_new_c16_1_6_.INIT = 16'h6996; + LUT4_L com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d16_new_c16_1_6_ ( + .I0(G_297_361), + .I1(G_313_415), + .I2(G_390_418), + .I3(G_470_81), + .LO(com_llm_llm_rx_top_llm_rx_tlp_crc_new_c16[6]) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d16_new_c16_1_5_.INIT = 16'h6996; + LUT4_L com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d16_new_c16_1_5_ ( + .I0(G_302_95), + .I1(G_319_93), + .I2(G_471_419), + .I3(G_484_374), + .LO(com_llm_llm_rx_top_llm_rx_tlp_crc_new_c16[5]) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d16_new_c16_1_4_.INIT = 16'h9669; + LUT4_L com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d16_new_c16_1_4_ ( + .I0(G_250_80), + .I1(N_11978_1), + .I2(N_31590_i_0), + .I3(com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d16_new_c16_1_1_4__2758), + .LO(com_llm_llm_rx_top_llm_rx_tlp_crc_new_c16[4]) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d16_new_c16_1_3_.INIT = 16'h6996; + LUT4_L com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d16_new_c16_1_3_ ( + .I0(G_386_334), + .I1(N_12045_1), + .I2(d16_i_m3_0_8_), + .I3(com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d16_new_c16_1_1_3__2759), + .LO(com_llm_llm_rx_top_llm_rx_tlp_crc_new_c16[3]) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d16_new_c16_1_2_.INIT = 8'h96; + LUT3_L com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d16_new_c16_1_2_ ( + .I0(G_301_411), + .I1(N_12047_1), + .I2(G_469_96), + .LO(com_llm_llm_rx_top_llm_rx_tlp_crc_new_c16[2]) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d16_new_c16_1_1_.INIT = 16'h6996; + LUT4_L com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d16_new_c16_1_1_ ( + .I0(G_303_412), + .I1(N_12127_1), + .I2(d16_i_m3_0_6_), + .I3(com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d16_new_c16_1_1_1[11]), + .LO(com_llm_llm_rx_top_llm_rx_tlp_crc_new_c16[1]) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d16_new_c16_1_0_.INIT = 16'h6996; + LUT4_L com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d16_new_c16_1_0_ ( + .I0(G_251_396), + .I1(N_11969_1), + .I2(N_12105_1), + .I3(N_12127_2), + .LO(com_llm_llm_rx_top_llm_rx_tlp_crc_new_c16[0]) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d16_new_c16_1_27_.INIT = 16'h6996; + LUT4_L com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d16_new_c16_1_27_ ( + .I0(G_303_412), + .I1(G_313_415), + .I2(N_12128_1), + .I3(com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d64_11__475), + .LO(com_llm_llm_rx_top_llm_rx_tlp_crc_new_c16[27]) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d16_new_c16_1_26_.INIT = 16'h6996; + LUT4_L com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d16_new_c16_1_26_ ( + .I0(G_251_396), + .I1(N_12045_1), + .I2(G_471_419), + .I3(com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d16_new_c16_1_0_26__2760), + .LO(com_llm_llm_rx_top_llm_rx_tlp_crc_new_c16[26]) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d16_new_c16_1_25_.INIT = 16'h6996; + LUT4_L com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d16_new_c16_1_25_ ( + .I0(G_301_411), + .I1(G_401_371), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d64_9__466), + .I3(com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d64_18__394), + .LO(com_llm_llm_rx_top_llm_rx_tlp_crc_new_c16[25]) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d16_new_c16_1_24_.INIT = 8'h96; + LUT3_L com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d16_new_c16_1_24_ ( + .I0(G_314_416), + .I1(G_389_372), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d64_8__457), + .LO(com_llm_llm_rx_top_llm_rx_tlp_crc_new_c16[24]) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d16_new_c16_1_23_.INIT = 8'h96; + LUT3_L com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d16_new_c16_1_23_ ( + .I0(N_11978_1), + .I1(G_469_96), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d64_7__405), + .LO(com_llm_llm_rx_top_llm_rx_tlp_crc_new_c16[23]) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d16_new_c16_1_22_.INIT = 16'h6996; + LUT4_L com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d16_new_c16_1_22_ ( + .I0(G_298_358), + .I1(G_390_418), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d64_6__474), + .I3(com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d16_new_c16_1_1_1[11]), + .LO(com_llm_llm_rx_top_llm_rx_tlp_crc_new_c16[22]) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d16_new_c16_1_21_.INIT = 16'h6996; + LUT4_L com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d16_new_c16_1_21_ ( + .I0(G_386_0_91), + .I1(G_305_413), + .I2(N_12128_1), + .I3(com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d64_5__98), + .LO(com_llm_llm_rx_top_llm_rx_tlp_crc_new_c16[21]) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d16_new_c16_1_20_.INIT = 4'h6; + LUT2_L com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d16_new_c16_1_20_ ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d64_4__364), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d16_new_c16_1_20__2764), + .LO(com_llm_llm_rx_top_llm_rx_tlp_crc_new_c16[20]) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d16_new_c16_1_19_.INIT = 8'h96; + LUT3_L com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d16_new_c16_1_19_ ( + .I0(N_12048_1), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d64_3__2737), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d16_new_c16_1_19__2761), + .LO(com_llm_llm_rx_top_llm_rx_tlp_crc_new_c16[19]) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d16_new_c16_1_18_.INIT = 8'h96; + LUT3_L com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d16_new_c16_1_18_ ( + .I0(G_386_334), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d64_2__2738), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d16_new_c16_1_18__2766), + .LO(com_llm_llm_rx_top_llm_rx_tlp_crc_new_c16[18]) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d16_new_c16_1_17_.INIT = 16'h6996; + LUT4_L com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d16_new_c16_1_17_ ( + .I0(N_11969_1), + .I1(d16_i_m3_i_m3_0_14_), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d16_new_c16_1_0_17__2762), + .I3(com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d16_new_c16_1_17__2765), + .LO(com_llm_llm_rx_top_llm_rx_tlp_crc_new_c16[17]) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d16_new_c16_1_16_.INIT = 16'h6996; + LUT4_L com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d16_new_c16_1_16_ ( + .I0(G_308_414), + .I1(N_11977_2), + .I2(N_12105_1), + .I3(com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d16_new_c16_1_1_16__2763), + .LO(com_llm_llm_rx_top_llm_rx_tlp_crc_new_c16[16]) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d16_new_c16_1_15_.INIT = 16'h6996; + LUT4_L com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d16_new_c16_1_15_ ( + .I0(G_302_95), + .I1(N_11978_1), + .I2(N_12128_1), + .I3(com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d16_new_c16_1_20__2764), + .LO(com_llm_llm_rx_top_llm_rx_tlp_crc_new_c16[15]) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d16_new_c16_1_14_.INIT = 8'h96; + LUT3_L com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d16_new_c16_1_14_ ( + .I0(G_388_362), + .I1(G_401_371), + .I2(N_12128_2), + .LO(com_llm_llm_rx_top_llm_rx_tlp_crc_new_c16[14]) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d16_new_c16_1_13_.INIT = 16'h6996; + LUT4_L com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d16_new_c16_1_13_ ( + .I0(G_386_0_91), + .I1(N_12045_1), + .I2(G_389_372), + .I3(com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d16_new_c16_1_17__2765), + .LO(com_llm_llm_rx_top_llm_rx_tlp_crc_new_c16[13]) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d16_new_c16_1_31_.INIT = 16'h6996; + LUT4_L com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d16_new_c16_1_31_ ( + .I0(N_11978_1), + .I1(d16_i_m3_0_8_), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d64_24__395), + .I3(com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d16_new_c16_1_2[31]), + .LO(com_llm_llm_rx_top_llm_rx_tlp_crc_new_c16[31]) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d16_new_c16_1_30_.INIT = 16'h6996; + LUT4_L com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d16_new_c16_1_30_ ( + .I0(G_386_0_91), + .I1(G_388_362), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d64_14__467), + .I3(com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d64_24__395), + .LO(com_llm_llm_rx_top_llm_rx_tlp_crc_new_c16[30]) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d16_new_c16_1_29_.INIT = 16'h6996; + LUT4_L com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d16_new_c16_1_29_ ( + .I0(G_302_95), + .I1(G_305_413), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d64_13__468), + .I3(com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d16_new_c16_1_18__2766), + .LO(com_llm_llm_rx_top_llm_rx_tlp_crc_new_c16[29]) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d16_new_c16_1_28_.INIT = 16'h6996; + LUT4_L com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d16_new_c16_1_28_ ( + .I0(N_12105_1), + .I1(G_470_81), + .I2(d16_i_m3_0_8_), + .I3(com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d64_12__464), + .LO(com_llm_llm_rx_top_llm_rx_tlp_crc_new_c16[28]) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d16_new_c16_1_1_11_.INIT = 8'h96; + LUT3 com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d16_new_c16_1_1_11_ ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d16_new_c16_1_1_1[11]), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d64_31__463), + .I2(d16_i_m3_i_m3_0_15_), + .O(com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d16_new_c16_1_11__2767) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_23_39373.INIT = 4'h6; + LUT2 com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_23_39373 ( + .I0(d64_i_m2_i_m3_0_27_), + .I1(d64_i_m2_i_m3_0_59_), + .O(com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_23_39373_2779) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_0_8_.INIT = 4'h6; + LUT2 com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_0_8_ ( + .I0(d64_i_m3_0_0_), + .I1(d64_i_m3_0_17_), + .O(com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_0_8__2775) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_0_30_.INIT = 8'h56; + LUT3 com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_0_30_ ( + .I0(d64_i_m3_i_m3_0_30_), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d64_16__92), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_initial_64_97), + .O(com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_0_30__2777) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_0_13_.INIT = 4'h6; + LUT2 com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_0_13_ ( + .I0(d64_i_m3_0_13_), + .I1(d64_i_m3_0_25_), + .O(com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_0_13__2782) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_3_1_2_.INIT = 16'h6996; + LUT4 com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_3_1_2_ ( + .I0(d64_i_m3_0_18_), + .I1(d64_i_m3_0_35_), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_c64_0_a2_0_a2[5]), + .I3(c64_0_a2_0_a2_3_), + .O(com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_3_1[2]) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_1_17_.INIT = 8'h96; + LUT3_L com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_1_17_ ( + .I0(N_141_1), + .I1(d64_i_m3_0_22_), + .I2(d64_i_m3_i_m3_0_49_), + .LO(com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_1_17__2768) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_1_0_5_.INIT = 16'h9996; + LUT4 com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_1_0_5_ ( + .I0(d64_i_m3_0_10_), + .I1(d64_i_m3_0_20_), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d64_7__405), + .I3(com_llm_llm_rx_top_llm_rx_tlp_crc_initial_64_97), + .O(com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_1_5__2773) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_1_9_.INIT = 8'h69; + LUT3 com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_1_9_ ( + .I0(G_409_0_m3_0_453), + .I1(c64_0_a2_0_a2_2_), + .I2(c64_0_a2_0_a2_1_), + .O(com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_1_9__2774) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_2_29_.INIT = 8'h96; + LUT3 com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_2_29_ ( + .I0(N_11870_1), + .I1(d64_i_m3_0_21_), + .I2(d64_i_m2_i_m3_0_26_), + .O(com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_2_29__2781) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_1_1_.INIT = 16'h6996; + LUT4 com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_1_1_ ( + .I0(G_11_408), + .I1(N_12033_1), + .I2(d64_i_m3_0_6_), + .I3(d64_i_m3_0_58_), + .O(com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_1__2824) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_2_2_.INIT = 4'h6; + LUT2 com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_2_2_ ( + .I0(N_12), + .I1(N_36), + .O(com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_2_2_) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_1_5_.INIT = 8'h96; + LUT3 com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_1_5_ ( + .I0(G_84_0_446), + .I1(N_107_1), + .I2(d64_i_m3_0_3_), + .O(com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_5__2785) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_1_8_.INIT = 4'h6; + LUT2 com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_1_8_ ( + .I0(G_24_335), + .I1(d64_i_m3_0_4_), + .O(com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_8__2808) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_1_14_.INIT = 4'h6; + LUT2 com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_1_14_ ( + .I0(N_15), + .I1(d64_i_m3_0_17_), + .O(com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_14__2795) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_1_18_.INIT = 4'h6; + LUT2 com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_1_18_ ( + .I0(G_70_399), + .I1(d64_i_m3_0_34_), + .O(com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_18__2864) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_1_20_.INIT = 16'h6996; + LUT4 com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_1_20_ ( + .I0(N_55), + .I1(N_12149_1), + .I2(d64_i_m3_0_12_), + .I3(d64_i_m3_0_25_), + .O(com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_20__2863) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_3_2_.INIT = 8'h96; + LUT3 com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_3_2_ ( + .I0(N_11845_1), + .I1(N_12033_1), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_3_1[2]), + .O(com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_3[2]) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_1_26_.INIT = 16'h6996; + LUT4 com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_1_26_ ( + .I0(N_53), + .I1(N_12149_1), + .I2(d64_i_m3_0_10_), + .I3(d64_i_m3_0_42_), + .O(com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_26__2858) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_1_0_6_.INIT = 16'h9996; + LUT4 com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_1_0_6_ ( + .I0(N_35_1), + .I1(N_12116_1), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_crc32_d64_15__355), + .I3(com_llm_llm_rx_top_llm_rx_tlp_crc_initial_64_97), + .O(com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_1_0_6__2769) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_1_0_7_.INIT = 16'h9669; + LUT4_L com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_1_0_7_ ( + .I0(N_35_1), + .I1(N_12116_1), + .I2(d64_i_m3_0_34_), + .I3(c64_0_a2_0_a2_2_), + .LO(com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_1_0_7__2770) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_2_17_.INIT = 16'h6996; + LUT4 com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_2_17_ ( + .I0(N_12033_1), + .I1(d64_i_m3_0_6_), + .I2(d64_i_m3_0_58_), + .I3(com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_1_17__2768), + .O(com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_2_17__2852) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_3_17_.INIT = 16'h6996; + LUT4 com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_3_17_ ( + .I0(N_62), + .I1(N_160_1), + .I2(d64_i_m3_0_9_), + .I3(d64_i_m2_i_m3_0_27_), + .O(com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_3_17__2771) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_1_25_.INIT = 4'h6; + LUT2 com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_1_25_ ( + .I0(N_14), + .I1(N_75), + .O(com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_1_25__2838) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_2_25_.INIT = 16'h9669; + LUT4 com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_2_25_ ( + .I0(N_140_1), + .I1(N_12175_1), + .I2(d64_i_m3_0_15_), + .I3(c64_0_a2_0_a2_26_), + .O(com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_2_25__2837) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_1_2_6_.INIT = 16'h6996; + LUT4 com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_1_2_6_ ( + .I0(N_107_1), + .I1(d64_i_m3_0_1_), + .I2(d64_i_m3_0_2_), + .I3(d64_i_m3_0_5_), + .O(com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_1_6__2871) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_2_24_.INIT = 16'h6996; + LUT4_L com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_2_24_ ( + .I0(G_50_0_445), + .I1(N_39_1), + .I2(N_140_1), + .I3(N_12071_1), + .LO(com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_2_24__2772) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_2_0_1_.INIT = 16'h6996; + LUT4 com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_2_0_1_ ( + .I0(N_77), + .I1(N_90_1), + .I2(d64_i_m3_0_16_), + .I3(d64_i_m3_0_28_), + .O(com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_2_1_) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_1_19_.INIT = 16'h6996; + LUT4 com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_1_19_ ( + .I0(N_75_1), + .I1(d64_i_m3_0_22_), + .I2(d64_i_m3_0_25_), + .I3(d64_i_m3_0_29_), + .O(com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_1_19__2861) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_2_0_2_.INIT = 4'h6; + LUT2_L com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_2_0_2_ ( + .I0(N_90), + .I1(N_112), + .LO(com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_2_2__2776) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_2_0_.INIT = 8'h96; + LUT3_L com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_2_0_ ( + .I0(G_50_0_445), + .I1(N_57), + .I2(N_12071_1), + .LO(com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_2_0__2778) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_2_27_.INIT = 16'h6996; + LUT4 com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_2_27_ ( + .I0(G_84_0_446), + .I1(N_10_1), + .I2(N_107_1), + .I3(N_11842_1), + .O(com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_2_27__2832) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_4_27_.INIT = 8'h96; + LUT3 com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_4_27_ ( + .I0(N_75), + .I1(N_160_1), + .I2(N_11870_1), + .O(com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_4_27__2831) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_1_1_7_.INIT = 16'h6996; + LUT4_L com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_1_1_7_ ( + .I0(N_33), + .I1(d64_i_m3_0_10_), + .I2(d64_i_m3_0_42_), + .I3(d64_i_m3_0_52_), + .LO(com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_1_7__2793) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_3_7_.INIT = 8'h96; + LUT3 com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_3_7_ ( + .I0(N_140_1), + .I1(G_5_346), + .I2(d64_i_m3_0_15_), + .O(com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_3_7__2813) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_2_28_.INIT = 16'h9669; + LUT4 com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_2_28_ ( + .I0(N_107_1), + .I1(d64_i_m3_0_22_), + .I2(d64_i_m2_i_m3_0_27_), + .I3(c64_0_a2_0_a2_1_), + .O(com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_2_28__2788) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_3_28_.INIT = 8'h96; + LUT3 com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_3_28_ ( + .I0(N_37), + .I1(N_12116_1), + .I2(d64_i_m3_0_33_), + .O(com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_3_28__2787) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_0_4_.INIT = 4'h6; + LUT2 com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_0_4_ ( + .I0(N_107), + .I1(d64_i_m3_0_8_), + .O(com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_0_4__2790) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_1_4_.INIT = 16'h6996; + LUT4 com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_1_4_ ( + .I0(N_91_1), + .I1(N_113_1), + .I2(N_11848_1), + .I3(d64_i_m3_0_15_), + .O(com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_1_4__2789) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_2_10_.INIT = 4'h6; + LUT2 com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_2_10_ ( + .I0(G_3_340), + .I1(G_156_397), + .O(com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_2_10__2807) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_4_29_.INIT = 16'h6996; + LUT4_L com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_4_29_ ( + .I0(N_160_1), + .I1(G_14_338), + .I2(d64_i_m3_0_9_), + .I3(d64_i_m2_i_m3_0_27_), + .LO(com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_4_29__2780) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_3_13_.INIT = 16'h6996; + LUT4 com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_3_13_ ( + .I0(G_50_0_445), + .I1(N_91_1), + .I2(N_12071_1), + .I3(d64_i_m3_0_16_), + .O(com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_3_13__2799) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_2_21_.INIT = 16'h6996; + LUT4 com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_2_21_ ( + .I0(N_3_1), + .I1(N_107_1), + .I2(d64_i_m3_0_10_), + .I3(d64_i_m3_0_24_), + .O(com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_2_21__2850) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_1_0_14_.INIT = 8'h96; + LUT3 com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_1_0_14_ ( + .I0(N_87), + .I1(N_12116_1), + .I2(d64_i_m3_0_33_), + .O(com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_1_14__2791) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_3_11_.INIT = 16'h6996; + LUT4 com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_3_11_ ( + .I0(N_90_1), + .I1(G_7_323), + .I2(d64_i_m3_0_16_), + .I3(d64_i_m3_0_28_), + .O(com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_3_11__2804) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_1_2_.INIT = 16'h6996; + LUT4 com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_1_2_ ( + .I0(N_3), + .I1(N_50), + .I2(d64_i_m3_0_52_), + .I3(d64_i_m2_i_m3_0_59_), + .O(com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_2__2821) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_2_14_.INIT = 16'h6996; + LUT4 com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_2_14_ ( + .I0(N_50), + .I1(G_2_332), + .I2(d64_i_m3_0_52_), + .I3(d64_i_m2_i_m3_0_59_), + .O(com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_2_14_) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_1_12_.INIT = 16'h6996; + LUT4 com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_1_12_ ( + .I0(N_62), + .I1(N_12034_1), + .I2(d64_i_m3_0_42_), + .I3(d64_i_m3_0_52_), + .O(com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_12__2848) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_1_6_.INIT = 8'h96; + LUT3 com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_1_6_ ( + .I0(N_19), + .I1(G_15_409), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_1_0_6__2769), + .O(com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_6__2870) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_1_7_.INIT = 8'h96; + LUT3 com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_1_7_ ( + .I0(N_53), + .I1(d64_i_m3_i_m3_0_60_), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_1_0_7__2770), + .O(com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_7__2786) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_1_2_10_.INIT = 16'h6996; + LUT4_L com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_1_2_10_ ( + .I0(N_10_1), + .I1(N_22), + .I2(N_11842_1), + .I3(d64_i_m3_0_16_), + .LO(com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_1_2[10]) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_6_17_.INIT = 16'h9669; + LUT4_L com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_6_17_ ( + .I0(N_15), + .I1(N_12175_1), + .I2(c64_0_a2_0_a2_26_), + .I3(com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_3_17__2771), + .LO(com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_6_17__2851) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_4_16_.INIT = 16'h6996; + LUT4 com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_4_16_ ( + .I0(N_39_1), + .I1(N_79), + .I2(N_140_1), + .I3(com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_1_16__2794), + .O(com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_4_16__2854) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_5_16_.INIT = 16'h6996; + LUT4_L com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_5_16_ ( + .I0(G_391_0_444), + .I1(N_40), + .I2(N_61), + .I3(G_7_323), + .LO(com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_5_16__2853) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_5_25_.INIT = 16'h6996; + LUT4 com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_5_25_ ( + .I0(G_391_0_444), + .I1(N_32), + .I2(G_7_323), + .I3(G_14_338), + .O(com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_5_25__2836) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_3_3_.INIT = 16'h6996; + LUT4 com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_3_3_ ( + .I0(N_22), + .I1(N_35_1), + .I2(N_160_1), + .I3(d64_i_m3_0_25_), + .O(com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_3_3__2820) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_4_3_.INIT = 16'h6996; + LUT4 com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_4_3_ ( + .I0(N_24), + .I1(N_59), + .I2(N_90), + .I3(G_6_402), + .O(com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_4_3__2819) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_5_3_.INIT = 8'h96; + LUT3_L com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_5_3_ ( + .I0(G_2_332), + .I1(G_487_365), + .I2(d64_i_m3_0_7_), + .LO(com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_5_3__2818) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_4_24_.INIT = 16'h6996; + LUT4_L com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_4_24_ ( + .I0(N_107), + .I1(N_12149_1), + .I2(d64_i_m3_0_17_), + .I3(com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_2_24__2772), + .LO(com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_4_24__2783) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_5_24_.INIT = 16'h6996; + LUT4 com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_5_24_ ( + .I0(N_52), + .I1(N_58), + .I2(G_4_326), + .I3(d64_i_m3_i_m3_0_60_), + .O(com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_5_24__2840) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_3_22_.INIT = 16'h6996; + LUT4_L com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_3_22_ ( + .I0(G_5_346), + .I1(G_429_392), + .I2(d64_i_m3_0_37_), + .I3(d64_i_m2_i_m3_0_36_), + .LO(com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_3_22__2847) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_4_22_.INIT = 8'h96; + LUT3 com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_4_22_ ( + .I0(N_52), + .I1(G_121_398), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_3[2]), + .O(com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_4_22__2846) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_5_22_.INIT = 16'h9669; + LUT4 com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_5_22_ ( + .I0(N_32), + .I1(N_92), + .I2(G_14_338), + .I3(c64_0_a2_0_a2_23_), + .O(com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_5_22__2845) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_6_22_.INIT = 16'h6996; + LUT4 com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_6_22_ ( + .I0(G_374_0_325), + .I1(N_3), + .I2(N_57), + .I3(d64_i_m3_0_12_), + .O(com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_6_22__2844) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_5_5_.INIT = 16'h6996; + LUT4 com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_5_5_ ( + .I0(N_51), + .I1(N_140_1), + .I2(G_156_397), + .I3(com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_1_5__2773), + .O(com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_5_5__2816) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_6_5_.INIT = 16'h6996; + LUT4 com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_6_5_ ( + .I0(N_30), + .I1(N_42), + .I2(N_92), + .I3(d64_i_m3_0_39_), + .O(com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_6_5__2815) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_7_5_.INIT = 4'h6; + LUT2_L com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_7_5_ ( + .I0(G_491_373), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_5__2785), + .LO(com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_7_5__2814) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_3_1_.INIT = 16'h6996; + LUT4 com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_3_1_ ( + .I0(G_70_399), + .I1(G_124_90), + .I2(d64_i_m3_0_7_), + .I3(d64_i_m3_i_m3_0_60_), + .O(com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_3_1__2825) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_6_1_.INIT = 8'h69; + LUT3_L com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_6_1_ ( + .I0(G_5_346), + .I1(N_12034_1), + .I2(c64_0_a2_0_a2_3_), + .LO(com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_6_1__2784) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_2_15_.INIT = 8'h96; + LUT3_L com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_2_15_ ( + .I0(N_78), + .I1(N_160_1), + .I2(G_368_363), + .LO(com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_2_15__2856) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_3_15_.INIT = 16'h6996; + LUT4 com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_3_15_ ( + .I0(N_37), + .I1(N_57), + .I2(N_108), + .I3(d64_i_m3_0_12_), + .O(com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_3_15__2855) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_3_18_.INIT = 16'h6996; + LUT4 com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_3_18_ ( + .I0(N_12), + .I1(N_78), + .I2(G_429_392), + .I3(d64_i_m3_i_m3_0_48_), + .O(com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_3_18__2865) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_6_9_.INIT = 16'h6996; + LUT4 com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_6_9_ ( + .I0(N_63), + .I1(N_92_1), + .I2(N_11862_1), + .I3(com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_1_9__2774), + .O(com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_6_9__2792) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_4_8_.INIT = 16'h6996; + LUT4 com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_4_8_ ( + .I0(N_160_1), + .I1(G_6_402), + .I2(G_11_408), + .I3(com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_0_8__2775), + .O(com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_4_8__2810) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_3_2_2_.INIT = 16'h6996; + LUT4_L com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_3_2_2_ ( + .I0(N_65), + .I1(d64_i_m3_0_8_), + .I2(d64_i_m3_0_13_), + .I3(com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_2_2__2776), + .LO(com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_3_2__2823) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_4_2_.INIT = 8'h96; + LUT3 com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_4_2_ ( + .I0(N_30), + .I1(d64_i_m3_0_39_), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_3[2]), + .O(com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_4_2__2822) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_3_30_.INIT = 16'h6996; + LUT4 com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_3_30_ ( + .I0(N_40), + .I1(N_11858_1), + .I2(d64_i_m3_0_4_), + .I3(com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_0_30__2777), + .O(com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_3_30__2860) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_4_30_.INIT = 16'h6996; + LUT4_L com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_4_30_ ( + .I0(N_52), + .I1(N_160_1), + .I2(N_11870_1), + .I3(com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_2_2_), + .LO(com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_4_30__2859) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_3_0_.INIT = 8'h69; + LUT3 com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_3_0_ ( + .I0(N_23), + .I1(N_112), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_c64_0_a2_0_a2[5]), + .O(com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_3_0__2827) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_4_0_.INIT = 16'h6996; + LUT4 com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_4_0_ ( + .I0(N_87), + .I1(N_160_1), + .I2(d64_i_m3_0_25_), + .I3(com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_2_0__2778), + .O(com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_4_0__2826) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_3_23_.INIT = 16'h6996; + LUT4 com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_3_23_ ( + .I0(N_89), + .I1(N_11858_1), + .I2(d64_i_m2_i_m3_0_36_), + .I3(com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_23_39373_2779), + .O(com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_3_23__2843) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_4_23_.INIT = 16'h6996; + LUT4 com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_4_23_ ( + .I0(N_77), + .I1(N_11845_1), + .I2(N_12033_1), + .I3(G_459_356), + .O(com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_4_23__2842) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_3_10_.INIT = 16'h6996; + LUT4 com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_3_10_ ( + .I0(N_19_1), + .I1(N_42_1), + .I2(N_65_1), + .I3(G_368_363), + .O(com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_3_10__2806) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_6_29_.INIT = 16'h9669; + LUT4 com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_6_29_ ( + .I0(d64_i_m3_0_7_), + .I1(G_409_0_m3_0_453), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_2_29__2781), + .I3(com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_4_29__2780), + .O(com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_6_29__2829) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_7_29_.INIT = 8'h96; + LUT3_L com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_7_29_ ( + .I0(N_41), + .I1(N_53), + .I2(G_459_356), + .LO(com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_7_29__2828) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_4_13_.INIT = 16'h6996; + LUT4 com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_4_13_ ( + .I0(N_63), + .I1(N_66), + .I2(d64_i_m3_0_18_), + .I3(com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_0_13__2782), + .O(com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_4_13__2798) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_2_31_.INIT = 16'h6996; + LUT4 com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_2_31_ ( + .I0(N_42), + .I1(N_79), + .I2(G_122_404), + .I3(d64_i_m2_i_m3_0_36_), + .O(com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_2_31__2857) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_5_21_.INIT = 16'h6996; + LUT4_L com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_5_21_ ( + .I0(G_15_409), + .I1(N_12149_1), + .I2(d64_i_m3_0_17_), + .I3(com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_18__2864), + .LO(com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_5_21__2849) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_2_12_.INIT = 16'h6996; + LUT4 com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_2_12_ ( + .I0(N_89), + .I1(N_92_1), + .I2(G_491_373), + .I3(d64_i_m3_0_6_), + .O(com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_2_12__2801) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_2_0_14_.INIT = 16'h6996; + LUT4 com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_2_0_14_ ( + .I0(N_66), + .I1(N_113_1), + .I2(d64_i_m3_0_11_), + .I3(d64_i_m3_0_15_), + .O(com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_2_14__2797) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_2_26_.INIT = 16'h6996; + LUT4 com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_2_26_ ( + .I0(N_58), + .I1(N_108), + .I2(G_375_417), + .I3(d64_i_m3_i_m3_0_48_), + .O(com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_2_26__2834) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_3_26_.INIT = 8'h69; + LUT3 com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_3_26_ ( + .I0(N_92), + .I1(c64_0_a2_0_a2_23_), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_26__2858), + .O(com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_3_26__2833) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_4_11_.INIT = 16'h6996; + LUT4 com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_4_11_ ( + .I0(N_91), + .I1(N_92_1), + .I2(G_145_406), + .I3(N_12116_1), + .O(com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_4_11__2803) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_5_11_.INIT = 16'h6996; + LUT4 com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_5_11_ ( + .I0(G_460_1_1_330), + .I1(N_12), + .I2(N_23), + .I3(N_11843_1), + .O(com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_5_11__2802) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_6_25_.INIT = 16'h6996; + LUT4_L com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_6_25_ ( + .I0(N_55), + .I1(N_59), + .I2(N_91), + .I3(N_31587_i_0), + .LO(com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_6_25__2835) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_6_24_.INIT = 16'h9669; + LUT4_L com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_6_24_ ( + .I0(N_142), + .I1(G_486_367), + .I2(c64_0_a2_0_a2_3_), + .I3(com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_4_24__2783), + .LO(com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_6_24__2839) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_8_1_.INIT = 16'h6996; + LUT4_L com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_8_1_ ( + .I0(G_14_338), + .I1(N_12061_1), + .I2(d64_i_m2_i_m3_0_59_), + .I3(com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_6_1__2784), + .LO(com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_8[1]) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_7_8_.INIT = 16'h6996; + LUT4 com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_7_8_ ( + .I0(N_60), + .I1(G_124_90), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_5__2785), + .I3(com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_7__2786), + .O(com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_7_8__2809) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_6_7_.INIT = 16'h6996; + LUT4_L com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_6_7_ ( + .I0(G_2_332), + .I1(d64_i_m3_0_7_), + .I2(d64_i_m3_0_39_), + .I3(com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_7__2786), + .LO(com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_6_7__2811) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_6_28_.INIT = 16'h6996; + LUT4 com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_6_28_ ( + .I0(G_24_335), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_2_28__2788), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_3_28__2787), + .I3(com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_20__2863), + .O(com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_6_28__2830) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_4_4_.INIT = 16'h6996; + LUT4_L com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_4_4_ ( + .I0(N_22), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_0_4__2790), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_1_4__2789), + .I3(com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_1__2824), + .LO(com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_4_4__2817) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_5_12_.INIT = 8'h96; + LUT3_L com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_5_12_ ( + .I0(N_31587_i_0), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_8__2808), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_12__2848), + .LO(com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_5_12__2800) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_5_14_.INIT = 8'h96; + LUT3_L com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_5_14_ ( + .I0(N_12029_1), + .I1(G_404_344), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_1_14__2791), + .LO(com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_5_14__2796) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_11_39376.INIT = 16'h6996; + LUT4_L com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_11_39376 ( + .I0(N_30), + .I1(N_39_1), + .I2(N_160_1), + .I3(G_372_322), + .LO(com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_11_39376_2805) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_10_9_.INIT = 16'h9669; + LUT4_L com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_10_9_ ( + .I0(G_5_346), + .I1(G_404_344), + .I2(c64_0_a2_0_a2_3_), + .I3(com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_6_9__2792), + .LO(com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_10[9]) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_1_10_.INIT = 8'h96; + LUT3 com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_1_10_ ( + .I0(N_40), + .I1(G_4_326), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_1_2[10]), + .O(com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_10__2841) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_4_7_.INIT = 8'h96; + LUT3 com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_4_7_ ( + .I0(N_61), + .I1(N_65), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_1_7__2793), + .O(com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_4_7__2812) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_1_16_.INIT = 8'h96; + LUT3 com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_1_16_ ( + .I0(d64_i_m3_0_4_), + .I1(d64_i_m3_0_13_), + .I2(d64_i_m3_0_19_), + .O(com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_1_16__2794) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_14_.INIT = 16'h6996; + LUT4_L com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_14_ ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_2_14__2797), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_5_14__2796), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_14__2795), + .I3(com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_2_14_), + .LO(com_llm_llm_rx_top_llm_rx_tlp_crc_new_c64[14]) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_13_.INIT = 16'h6996; + LUT4_L com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_13_ ( + .I0(G_479_327), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_3_13__2799), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_4_13__2798), + .I3(com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_6__2870), + .LO(com_llm_llm_rx_top_llm_rx_tlp_crc_new_c64[13]) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_12_.INIT = 8'h96; + LUT3_L com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_12_ ( + .I0(G_370_331), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_2_12__2801), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_5_12__2800), + .LO(com_llm_llm_rx_top_llm_rx_tlp_crc_new_c64[12]) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_11_.INIT = 16'h6996; + LUT4_L com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_11_ ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_11_39376_2805), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_3_11__2804), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_4_11__2803), + .I3(com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_5_11__2802), + .LO(com_llm_llm_rx_top_llm_rx_tlp_crc_new_c64[11]) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_10_.INIT = 16'h6996; + LUT4_L com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_10_ ( + .I0(G_413_329), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_2_10__2807), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_3_10__2806), + .I3(com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_10__2841), + .LO(com_llm_llm_rx_top_llm_rx_tlp_crc_new_c64[10]) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_8_.INIT = 16'h6996; + LUT4_L com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_8_ ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_4_8__2810), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_7_8__2809), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_2__2821), + .I3(com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_8__2808), + .LO(com_llm_llm_rx_top_llm_rx_tlp_crc_new_c64[8]) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_7_.INIT = 16'h6996; + LUT4_L com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_7_ ( + .I0(G_403_328), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_3_7__2813), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_4_7__2812), + .I3(com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_6_7__2811), + .LO(com_llm_llm_rx_top_llm_rx_tlp_crc_new_c64[7]) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_5_.INIT = 16'h6996; + LUT4_L com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_5_ ( + .I0(G_373_336), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_5_5__2816), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_6_5__2815), + .I3(com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_7_5__2814), + .LO(com_llm_llm_rx_top_llm_rx_tlp_crc_new_c64[5]) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_4_.INIT = 8'h96; + LUT3_L com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_4_ ( + .I0(G_370_331), + .I1(G_403_328), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_4_4__2817), + .LO(com_llm_llm_rx_top_llm_rx_tlp_crc_new_c64[4]) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_3_.INIT = 16'h6996; + LUT4_L com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_3_ ( + .I0(G_413_329), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_3_3__2820), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_4_3__2819), + .I3(com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_5_3__2818), + .LO(com_llm_llm_rx_top_llm_rx_tlp_crc_new_c64[3]) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_2_.INIT = 16'h6996; + LUT4_L com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_2_ ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_3_2__2823), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_4_2__2822), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_2__2821), + .I3(com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_2_2_), + .LO(com_llm_llm_rx_top_llm_rx_tlp_crc_new_c64[2]) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_1_.INIT = 16'h6996; + LUT4_L com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_1_ ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_2_1_), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_3_1__2825), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_8[1]), + .I3(com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_1__2824), + .LO(com_llm_llm_rx_top_llm_rx_tlp_crc_new_c64[1]) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_0_.INIT = 16'h6996; + LUT4_L com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_0_ ( + .I0(G_378_343), + .I1(G_460_345), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_3_0__2827), + .I3(com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_4_0__2826), + .LO(com_llm_llm_rx_top_llm_rx_tlp_crc_new_c64[0]) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_29_.INIT = 8'h96; + LUT3_L com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_29_ ( + .I0(G_479_327), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_6_29__2829), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_7_29__2828), + .LO(com_llm_llm_rx_top_llm_rx_tlp_crc_new_c64[29]) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_28_.INIT = 8'h96; + LUT3_L com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_28_ ( + .I0(G_371_342), + .I1(G_473_324), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_6_28__2830), + .LO(com_llm_llm_rx_top_llm_rx_tlp_crc_new_c64[28]) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_27_.INIT = 16'h6996; + LUT4_L com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_27_ ( + .I0(G_378_343), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_2_27__2832), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_4_27__2831), + .I3(com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_7_27__2862), + .LO(com_llm_llm_rx_top_llm_rx_tlp_crc_new_c64[27]) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_26_.INIT = 16'h6996; + LUT4_L com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_26_ ( + .I0(G_371_342), + .I1(G_465_347), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_2_26__2834), + .I3(com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_3_26__2833), + .LO(com_llm_llm_rx_top_llm_rx_tlp_crc_new_c64[26]) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_25_.INIT = 16'h6996; + LUT4_L com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_25_ ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_1_25__2838), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_2_25__2837), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_5_25__2836), + .I3(com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_6_25__2835), + .LO(com_llm_llm_rx_top_llm_rx_tlp_crc_new_c64[25]) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_24_.INIT = 8'h96; + LUT3_L com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_24_ ( + .I0(G_473_324), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_5_24__2840), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_6_24__2839), + .LO(com_llm_llm_rx_top_llm_rx_tlp_crc_new_c64[24]) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_23_.INIT = 16'h6996; + LUT4_L com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_23_ ( + .I0(G_380_357), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_3_23__2843), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_4_23__2842), + .I3(com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_10__2841), + .LO(com_llm_llm_rx_top_llm_rx_tlp_crc_new_c64[23]) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_22_.INIT = 16'h6996; + LUT4_L com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_22_ ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_3_22__2847), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_4_22__2846), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_5_22__2845), + .I3(com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_6_22__2844), + .LO(com_llm_llm_rx_top_llm_rx_tlp_crc_new_c64[22]) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_21_.INIT = 16'h6996; + LUT4_L com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_21_ ( + .I0(N_40), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_2_21__2850), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_5_21__2849), + .I3(com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_12__2848), + .LO(com_llm_llm_rx_top_llm_rx_tlp_crc_new_c64[21]) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_17_.INIT = 16'h6996; + LUT4_L com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_17_ ( + .I0(N_12123_1), + .I1(G_486_367), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_2_17__2852), + .I3(com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_6_17__2851), + .LO(com_llm_llm_rx_top_llm_rx_tlp_crc_new_c64[17]) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_16_.INIT = 8'h96; + LUT3_L com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_16_ ( + .I0(G_460_345), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_4_16__2854), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_5_16__2853), + .LO(com_llm_llm_rx_top_llm_rx_tlp_crc_new_c64[16]) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_15_.INIT = 16'h6996; + LUT4_L com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_15_ ( + .I0(G_393_339), + .I1(G_485_333), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_2_15__2856), + .I3(com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_3_15__2855), + .LO(com_llm_llm_rx_top_llm_rx_tlp_crc_new_c64[15]) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_31_.INIT = 16'h6996; + LUT4_L com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_31_ ( + .I0(G_393_339), + .I1(G_465_347), + .I2(G_487_365), + .I3(com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_2_31__2857), + .LO(com_llm_llm_rx_top_llm_rx_tlp_crc_new_c64[31]) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_30_.INIT = 16'h6996; + LUT4_L com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_30_ ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_3_30__2860), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_4_30__2859), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_26__2858), + .I3(com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_2_14_), + .LO(com_llm_llm_rx_top_llm_rx_tlp_crc_new_c64[30]) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_1_0_18_.INIT = 16'h6996; + LUT4 com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_1_0_18_ ( + .I0(G_50_0_445), + .I1(N_22), + .I2(N_12071_1), + .I3(d64_i_m3_0_2_), + .O(com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_1_18__2866) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_1_0_19_.INIT = 16'h6996; + LUT4 com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_1_0_19_ ( + .I0(N_50), + .I1(N_60), + .I2(N_142), + .I3(com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_1_19__2861), + .O(com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_1_0_19__2867) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_1_0_20_.INIT = 16'h6996; + LUT4 com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_1_0_20_ ( + .I0(N_51), + .I1(N_57), + .I2(d64_i_m3_i_m3_0_30_), + .I3(d64_i_m2_i_m3_0_26_), + .O(com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_1_0_20__2869) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_1_1_6_.INIT = 16'h6996; + LUT4 com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_1_1_6_ ( + .I0(N_41), + .I1(N_51), + .I2(G_121_398), + .I3(G_375_417), + .O(com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_1_1[6]) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_1_0_9_.INIT = 16'h6996; + LUT4 com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_1_0_9_ ( + .I0(N_50), + .I1(N_11858_1), + .I2(G_122_404), + .I3(d64_i_m3_0_4_), + .O(com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_1_0_9__2872) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_7_1_27_.INIT = 16'h6996; + LUT4_L com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_7_1_27_ ( + .I0(N_36), + .I1(G_145_406), + .I2(d64_i_m3_0_23_), + .I3(c64_0_a2_0_a2_10_), + .LO(com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_7_1[27]) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_7_27_.INIT = 16'h9669; + LUT4_L com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_7_27_ ( + .I0(N_52), + .I1(N_58), + .I2(N_61), + .I3(com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_7_1[27]), + .LO(com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_7_27__2862) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_4_20_.INIT = 8'h96; + LUT3_L com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_4_20_ ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_20__2863), + .I1(d64_i_m3_0_17_), + .I2(N_15), + .LO(com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_4_20__2868) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_18_.INIT = 16'h6996; + LUT4_L com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_18_ ( + .I0(G_373_336), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_1_18__2866), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_3_18__2865), + .I3(com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_18__2864), + .LO(com_llm_llm_rx_top_llm_rx_tlp_crc_new_c64[18]) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_19_.INIT = 16'h6996; + LUT4_L com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_19_ ( + .I0(G_5_346), + .I1(G_372_322), + .I2(G_380_357), + .I3(com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_1_0_19__2867), + .LO(com_llm_llm_rx_top_llm_rx_tlp_crc_new_c64[19]) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_20_.INIT = 16'h6996; + LUT4_L com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_20_ ( + .I0(G_4_326), + .I1(G_499_341), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_1_0_20__2869), + .I3(com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_4_20__2868), + .LO(com_llm_llm_rx_top_llm_rx_tlp_crc_new_c64[20]) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_6_.INIT = 16'h6996; + LUT4_L com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_6_ ( + .I0(G_485_333), + .I1(com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_1_6__2871), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_1_1[6]), + .I3(com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_6__2870), + .LO(com_llm_llm_rx_top_llm_rx_tlp_crc_new_c64[6]) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_9_.INIT = 16'h6996; + LUT4_L com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_9_ ( + .I0(N_59), + .I1(G_499_341), + .I2(com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_1_0_9__2872), + .I3(com_llm_llm_rx_top_llm_rx_tlp_crc_llm_rx_crc32_d64_new_c64_1_10[9]), + .LO(com_llm_llm_rx_top_llm_rx_tlp_crc_new_c64[9]) + ); + VCC com_llm_llm_rx_top_llm_rx_tlp_sm_VCC ( + .P(com_llm_llm_rx_top_llm_rx_tlp_sm_VCC_2873) + ); + GND com_llm_llm_rx_top_llm_rx_tlp_sm_GND ( + .G(com_llm_llm_rx_top_llm_rx_tlp_sm_GND_2886) + ); + MUXCY_L com_llm_llm_rx_top_llm_rx_tlp_sm_tsn_eq_0_I_1 ( + .CI(com_llm_llm_rx_top_llm_rx_tlp_sm_VCC_2873), + .DI(com_llm_llm_rx_top_llm_rx_tlp_sm_GND_2886), + .LO(com_llm_llm_rx_top_llm_rx_tlp_sm_data_tmp[0]), + .S(com_llm_llm_rx_top_llm_rx_tlp_sm_N_43) + ); + MUXCY_L com_llm_llm_rx_top_llm_rx_tlp_sm_tsn_eq_0_I_10 ( + .CI(com_llm_llm_rx_top_llm_rx_tlp_sm_data_tmp[1]), + .DI(com_llm_llm_rx_top_llm_rx_tlp_sm_GND_2886), + .LO(com_llm_llm_rx_top_llm_rx_tlp_sm_data_tmp[2]), + .S(com_llm_llm_rx_top_llm_rx_tlp_sm_N_35) + ); + MUXCY_L com_llm_llm_rx_top_llm_rx_tlp_sm_tsn_eq_0_I_28 ( + .CI(com_llm_llm_rx_top_llm_rx_tlp_sm_data_tmp[2]), + .DI(com_llm_llm_rx_top_llm_rx_tlp_sm_GND_2886), + .LO(com_llm_llm_rx_top_llm_rx_tlp_sm_data_tmp[3]), + .S(com_llm_llm_rx_top_llm_rx_tlp_sm_N_19) + ); + MUXCY_L com_llm_llm_rx_top_llm_rx_tlp_sm_tsn_eq_0_I_37 ( + .CI(com_llm_llm_rx_top_llm_rx_tlp_sm_data_tmp[3]), + .DI(com_llm_llm_rx_top_llm_rx_tlp_sm_GND_2886), + .LO(com_llm_llm_rx_top_llm_rx_tlp_sm_data_tmp[4]), + .S(com_llm_llm_rx_top_llm_rx_tlp_sm_N_11) + ); + MUXCY_L com_llm_llm_rx_top_llm_rx_tlp_sm_tsn_eq_0_I_46 ( + .CI(com_llm_llm_rx_top_llm_rx_tlp_sm_data_tmp[0]), + .DI(com_llm_llm_rx_top_llm_rx_tlp_sm_GND_2886), + .LO(com_llm_llm_rx_top_llm_rx_tlp_sm_data_tmp[1]), + .S(com_llm_llm_rx_top_llm_rx_tlp_sm_N_3) + ); + MUXCY_L com_llm_llm_rx_top_llm_rx_tlp_sm_tlp_diff_tsn_cry_0 ( + .CI(com_llm_llm_rx_top_llm_rx_tlp_sm_VCC_2873), + .DI(com_llm_reg_next_rcv_tsn[0]), + .LO(com_llm_llm_rx_top_llm_rx_tlp_sm_tlp_diff_tsn_cry_0_2874), + .S(com_llm_llm_rx_top_llm_rx_tlp_sm_tlp_diff_tsn_axb_0_2910) + ); + MUXCY_L com_llm_llm_rx_top_llm_rx_tlp_sm_tlp_diff_tsn_cry_1 ( + .CI(com_llm_llm_rx_top_llm_rx_tlp_sm_tlp_diff_tsn_cry_0_2874), + .DI(com_llm_reg_next_rcv_tsn[1]), + .LO(com_llm_llm_rx_top_llm_rx_tlp_sm_tlp_diff_tsn_cry_1_2875), + .S(com_llm_llm_rx_top_llm_rx_tlp_sm_tlp_diff_tsn_axb_1_2909) + ); + MUXCY_L com_llm_llm_rx_top_llm_rx_tlp_sm_tlp_diff_tsn_cry_2 ( + .CI(com_llm_llm_rx_top_llm_rx_tlp_sm_tlp_diff_tsn_cry_1_2875), + .DI(com_llm_reg_next_rcv_tsn[2]), + .LO(com_llm_llm_rx_top_llm_rx_tlp_sm_tlp_diff_tsn_cry_2_2876), + .S(com_llm_llm_rx_top_llm_rx_tlp_sm_tlp_diff_tsn_axb_2_2908) + ); + MUXCY_L com_llm_llm_rx_top_llm_rx_tlp_sm_tlp_diff_tsn_cry_3 ( + .CI(com_llm_llm_rx_top_llm_rx_tlp_sm_tlp_diff_tsn_cry_2_2876), + .DI(com_llm_reg_next_rcv_tsn[3]), + .LO(com_llm_llm_rx_top_llm_rx_tlp_sm_tlp_diff_tsn_cry_3_2877), + .S(com_llm_llm_rx_top_llm_rx_tlp_sm_tlp_diff_tsn_axb_3_2907) + ); + MUXCY_L com_llm_llm_rx_top_llm_rx_tlp_sm_tlp_diff_tsn_cry_4 ( + .CI(com_llm_llm_rx_top_llm_rx_tlp_sm_tlp_diff_tsn_cry_3_2877), + .DI(com_llm_reg_next_rcv_tsn[4]), + .LO(com_llm_llm_rx_top_llm_rx_tlp_sm_tlp_diff_tsn_cry_4_2878), + .S(com_llm_llm_rx_top_llm_rx_tlp_sm_tlp_diff_tsn_axb_4_2906) + ); + MUXCY_L com_llm_llm_rx_top_llm_rx_tlp_sm_tlp_diff_tsn_cry_5 ( + .CI(com_llm_llm_rx_top_llm_rx_tlp_sm_tlp_diff_tsn_cry_4_2878), + .DI(com_llm_reg_next_rcv_tsn[5]), + .LO(com_llm_llm_rx_top_llm_rx_tlp_sm_tlp_diff_tsn_cry_5_2879), + .S(com_llm_llm_rx_top_llm_rx_tlp_sm_tlp_diff_tsn_axb_5_2905) + ); + MUXCY_L com_llm_llm_rx_top_llm_rx_tlp_sm_tlp_diff_tsn_cry_6 ( + .CI(com_llm_llm_rx_top_llm_rx_tlp_sm_tlp_diff_tsn_cry_5_2879), + .DI(com_llm_reg_next_rcv_tsn[6]), + .LO(com_llm_llm_rx_top_llm_rx_tlp_sm_tlp_diff_tsn_cry_6_2880), + .S(com_llm_llm_rx_top_llm_rx_tlp_sm_tlp_diff_tsn_axb_6_2904) + ); + MUXCY_L com_llm_llm_rx_top_llm_rx_tlp_sm_tlp_diff_tsn_cry_7 ( + .CI(com_llm_llm_rx_top_llm_rx_tlp_sm_tlp_diff_tsn_cry_6_2880), + .DI(com_llm_reg_next_rcv_tsn[7]), + .LO(com_llm_llm_rx_top_llm_rx_tlp_sm_tlp_diff_tsn_cry_7_2881), + .S(com_llm_llm_rx_top_llm_rx_tlp_sm_tlp_diff_tsn_axb_7_2903) + ); + MUXCY_L com_llm_llm_rx_top_llm_rx_tlp_sm_tlp_diff_tsn_cry_8 ( + .CI(com_llm_llm_rx_top_llm_rx_tlp_sm_tlp_diff_tsn_cry_7_2881), + .DI(com_llm_reg_next_rcv_tsn[8]), + .LO(com_llm_llm_rx_top_llm_rx_tlp_sm_tlp_diff_tsn_cry_8_2882), + .S(com_llm_llm_rx_top_llm_rx_tlp_sm_tlp_diff_tsn_axb_8_2902) + ); + MUXCY_L com_llm_llm_rx_top_llm_rx_tlp_sm_tlp_diff_tsn_cry_9 ( + .CI(com_llm_llm_rx_top_llm_rx_tlp_sm_tlp_diff_tsn_cry_8_2882), + .DI(com_llm_reg_next_rcv_tsn[9]), + .LO(com_llm_llm_rx_top_llm_rx_tlp_sm_tlp_diff_tsn_cry_9_2883), + .S(com_llm_llm_rx_top_llm_rx_tlp_sm_tlp_diff_tsn_axb_9_2901) + ); + MUXCY_L com_llm_llm_rx_top_llm_rx_tlp_sm_tlp_diff_tsn_cry_10 ( + .CI(com_llm_llm_rx_top_llm_rx_tlp_sm_tlp_diff_tsn_cry_9_2883), + .DI(com_llm_reg_next_rcv_tsn[10]), + .LO(com_llm_llm_rx_top_llm_rx_tlp_sm_tlp_diff_tsn_cry_10_2884), + .S(com_llm_llm_rx_top_llm_rx_tlp_sm_tlp_diff_tsn_axb_10_2900) + ); + XORCY com_llm_llm_rx_top_llm_rx_tlp_sm_tlp_diff_tsn_s_11 ( + .CI(com_llm_llm_rx_top_llm_rx_tlp_sm_tlp_diff_tsn_cry_10_2884), + .LI(com_llm_llm_rx_top_llm_rx_tlp_sm_tlp_diff_tsn_axb_11_2885), + .O(com_llm_llm_rx_top_llm_rx_tlp_sm_tlp_diff_tsn[11]) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_sm_lnk_rsrc_dsc_n_6_i_0_0_0_o2.INIT = 4'h8; + LUT2 com_llm_llm_rx_top_llm_rx_tlp_sm_lnk_rsrc_dsc_n_6_i_0_0_0_o2 ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_sm_link_up_2888), + .I1(com_llm_llm_rx_top_llm_rx_tlp_sm_tsn_eq), + .O(com_llm_N_56500_i) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_sm_reg_rx_tlp_tsn_err_lrfc_3_i_0_0_0_a3.INIT = 4'h8; + LUT2 com_llm_llm_rx_top_llm_rx_tlp_sm_reg_rx_tlp_tsn_err_lrfc_3_i_0_0_0_a3 ( + .I0(com_llm_llm_rx_top_rx_tlp_crc_err_n), + .I1(com_llm_llm_rx_top_rx_tlp_ferr_n), + .O(com_llm_N_62468) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_sm_lnk_rsrc_rdy_n_7_i_0_0_0_a2.INIT = 4'h1; + LUT2 com_llm_llm_rx_top_llm_rx_tlp_sm_lnk_rsrc_rdy_n_7_i_0_0_0_a2 ( + .I0(com_llm_rx_reof_n), + .I1(com_llm_llm_rx_top_rx_sof_n), + .O(com_llm_llm_rx_top_llm_rx_tlp_sm_N_58447) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_sm_tlp_diff_tsn_axb_11.INIT = 4'h9; + LUT2 com_llm_llm_rx_top_llm_rx_tlp_sm_tlp_diff_tsn_axb_11 ( + .I0(com_llm_llm_rx_top_rx_tlp_tsn[11]), + .I1(com_llm_reg_next_rcv_tsn[11]), + .O(com_llm_llm_rx_top_llm_rx_tlp_sm_tlp_diff_tsn_axb_11_2885) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_sm_reg_rx_tlp_tsn_err_lrx_3_0_a2_0_a2_0_a2_0_a2.INIT = 8'h02; + LUT3 com_llm_llm_rx_top_llm_rx_tlp_sm_reg_rx_tlp_tsn_err_lrx_3_0_a2_0_a2_0_a2_0_a2 ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_sm_link_up_2888), + .I1(com_llm_llm_rx_top_rx_sof_n), + .I2(com_llm_reg_dllr_in_progress), + .O(com_llm_llm_rx_top_llm_rx_tlp_sm_reg_rx_tlp_tsn_err_lrx_3) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_sm_reg_rx_tlp_tsn_err_0_a2_0_a2_0_a2_0_a2.INIT = 8'h15; + LUT3 com_llm_llm_rx_top_llm_rx_tlp_sm_reg_rx_tlp_tsn_err_0_a2_0_a2_0_a2_0_a2 ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_sm_reg_rx_tlp_tsn_err_lrfc_2890), + .I1(com_llm_llm_rx_top_llm_rx_tlp_sm_reg_rx_tlp_tsn_err_lrx_2887), + .I2(com_llm_llm_rx_top_llm_rx_tlp_sm_reg_rx_tlp_tsn_err_t_2894), + .O(com_llm_reg_rx_tlp_tsn_err_0_a2_0_a2_0_a2_0_a2) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_sm_un1_rx_reof_n_1_i_0_0_0_a2_0.INIT = 8'h02; + LUT3 com_llm_llm_rx_top_llm_rx_tlp_sm_un1_rx_reof_n_1_i_0_0_0_a2_0 ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_sm_tlp_diff_tsn[11]), + .I1(com_llm_llm_rx_top_rx_sof_n), + .I2(com_llm_reg_dllr_in_progress), + .O(com_llm_llm_rx_top_llm_rx_tlp_sm_tlp_range_error17) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_sm_lnk_rsrc_rdy_n_7_i_0_0_0_m3_0.INIT = 16'hCCE4; + LUT4_L com_llm_llm_rx_top_llm_rx_tlp_sm_lnk_rsrc_rdy_n_7_i_0_0_0_m3_0 ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_sm_link_up_2888), + .I1(com_llm_llm_rx_top_llm_rx_tlp_sm_tlp_ip_q_2899), + .I2(com_llm_llm_rx_top_llm_rx_tlp_sm_tsn_eq), + .I3(com_llm_llm_rx_top_rx_sof_n), + .LO(com_llm_llm_rx_top_llm_rx_tlp_sm_N_56982) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_sm_un1_tlp_ip_q17_5_i_i_a2_i_0_a2.INIT = 16'h0008; + LUT4 com_llm_llm_rx_top_llm_rx_tlp_sm_un1_tlp_ip_q17_5_i_i_a2_i_0_a2 ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_sm_link_up_2888), + .I1(com_llm_llm_rx_top_llm_rx_tlp_sm_tsn_eq), + .I2(com_llm_rx_rsrc_rdy_n), + .I3(com_llm_llm_rx_top_rx_sof_n), + .O(com_llm_llm_rx_top_llm_rx_tlp_sm_N_59418) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_sm_N_85557_i.INIT = 16'hCFEF; + LUT4 com_llm_llm_rx_top_llm_rx_tlp_sm_N_85557_i ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_sm_tlp_range_error_2897), + .I1(com_llm_llm_rx_top_llm_rx_tlp_sm_tlp_range_error17), + .I2(com_llm_rx_reof_n), + .I3(com_llm_llm_rx_top_rx_tlp_crc_err_n), + .O(com_llm_llm_rx_top_llm_rx_tlp_sm_N_85557_i_2896) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_sm_tlp_ip_q18_0_a2_0_a2_0_a2_0_a2.INIT = 4'h8; + LUT2 com_llm_llm_rx_top_llm_rx_tlp_sm_tlp_ip_q18_0_a2_0_a2_0_a2_0_a2 ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_sm_N_59418), + .I1(com_llm_rx_reof_n), + .O(com_llm_llm_rx_top_llm_rx_tlp_sm_tlp_ip_q18) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_sm_N_85574_i.INIT = 8'hEF; + LUT3 com_llm_llm_rx_top_llm_rx_tlp_sm_N_85574_i ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_sm_N_58447), + .I1(com_llm_llm_rx_top_llm_rx_tlp_sm_N_59418), + .I2(com_lnk_reof_n), + .O(com_llm_llm_rx_top_llm_rx_tlp_sm_N_85574_i_2898) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_sm_lnk_reof_n22_i.INIT = 16'hFDFF; + LUT4_L com_llm_llm_rx_top_llm_rx_tlp_sm_lnk_reof_n22_i ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_sm_tlp_ip_q_2899), + .I1(com_llm_rx_reof_n), + .I2(com_llm_rx_rsrc_rdy_n), + .I3(com_llm_llm_rx_top_rx_sof_n), + .LO(com_llm_llm_rx_top_llm_rx_tlp_sm_lnk_reof_n22_i_2889) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_sm_rx_tlp_tsn_err_crc_or_ferr_3_i_i_a2_i_0.INIT = 8'h01; + LUT3_L com_llm_llm_rx_top_llm_rx_tlp_sm_rx_tlp_tsn_err_crc_or_ferr_3_i_i_a2_i_0 ( + .I0(com_N_56127_i), + .I1(com_llm_N_62468), + .I2(com_llm_reg_dllr_in_progress), + .LO(com_llm_llm_rx_top_llm_rx_tlp_sm_N_39351_i) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_sm_reg_rx_tlp_tsn_err_lrfc_3_i_0_0_0.INIT = 8'h04; + LUT3_L com_llm_llm_rx_top_llm_rx_tlp_sm_reg_rx_tlp_tsn_err_lrfc_3_i_0_0_0 ( + .I0(com_llm_N_62468), + .I1(com_llm_llm_rx_top_llm_rx_tlp_sm_link_up_2888), + .I2(com_llm_reg_dllr_in_progress), + .LO(com_llm_llm_rx_top_llm_rx_tlp_sm_N_16443_i) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_sm_N_59478_i.INIT = 8'hF7; + LUT3_L com_llm_llm_rx_top_llm_rx_tlp_sm_N_59478_i ( + .I0(com_llm_N_62468), + .I1(com_llm_llm_rx_top_llm_rx_tlp_sm_tlp_range_error_2897), + .I2(com_llm_rx_reof_n), + .LO(com_llm_llm_rx_top_llm_rx_tlp_sm_N_59478_i_2891) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_sm_N_85556_i.INIT = 8'hFD; + LUT3_L com_llm_llm_rx_top_llm_rx_tlp_sm_N_85556_i ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_sm_N_56982), + .I1(com_llm_llm_rx_top_llm_rx_tlp_sm_N_58447), + .I2(com_llm_rx_rsrc_rdy_n), + .LO(com_llm_llm_rx_top_llm_rx_tlp_sm_N_85556_i_2892) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_sm_reg_rx_tlp_tsn_dup_3_0_a2_0_a2_0_a2_0_a2.INIT = 16'h0008; + LUT4_L com_llm_llm_rx_top_llm_rx_tlp_sm_reg_rx_tlp_tsn_dup_3_0_a2_0_a2_0_a2_0_a2 ( + .I0(com_llm_reg_rx_tlp_tsn_err_0_a2_0_a2_0_a2_0_a2), + .I1(com_llm_llm_rx_top_llm_rx_tlp_sm_reg_rx_tlp_tsn_err_lrx_3), + .I2(com_llm_llm_rx_top_llm_rx_tlp_sm_tlp_diff_tsn[11]), + .I3(com_llm_llm_rx_top_llm_rx_tlp_sm_tsn_eq), + .LO(com_llm_llm_rx_top_llm_rx_tlp_sm_reg_rx_tlp_tsn_dup_3) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_sm_tlp_ip_q18_i.INIT = 4'h1; + LUT1_L com_llm_llm_rx_top_llm_rx_tlp_sm_tlp_ip_q18_i ( + .I0(com_llm_llm_rx_top_llm_rx_tlp_sm_tlp_ip_q18), + .LO(com_llm_llm_rx_top_llm_rx_tlp_sm_tlp_ip_q18_i_2893) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_sm_N_85525_i.INIT = 16'hFDDD; + LUT4_L com_llm_llm_rx_top_llm_rx_tlp_sm_N_85525_i ( + .I0(com_llm_N_56500_i), + .I1(com_llm_llm_rx_top_llm_rx_tlp_sm_N_58447), + .I2(com_llm_N_62468), + .I3(com_llm_rx_rsrc_dsc_n), + .LO(com_llm_llm_rx_top_llm_rx_tlp_sm_N_85525_i_2895) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_sm_N_63255_i.INIT = 4'h1; + LUT1_L com_llm_llm_rx_top_llm_rx_tlp_sm_N_63255_i ( + .I0(com_llm_reg_rx_tlp_tsn_err_0_a2_0_a2_0_a2_0_a2), + .LO(com_llm_N_63255_i) + ); + MUXCY com_llm_llm_rx_top_llm_rx_tlp_sm_tsn_eq_0_I_19 ( + .CI(com_llm_llm_rx_top_llm_rx_tlp_sm_data_tmp[4]), + .DI(com_llm_llm_rx_top_llm_rx_tlp_sm_GND_2886), + .O(com_llm_llm_rx_top_llm_rx_tlp_sm_tsn_eq), + .S(com_llm_llm_rx_top_llm_rx_tlp_sm_N_27) + ); + FD com_llm_llm_rx_top_llm_rx_tlp_sm_lnk_rrem_reg_2_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_rx_rrem[2]), + .Q(com_lnk_rrem[0]) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_sm_reg_rx_tlp_tsn_err_lrx ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_sm_reg_rx_tlp_tsn_err_lrx_3), + .Q(com_llm_llm_rx_top_llm_rx_tlp_sm_reg_rx_tlp_tsn_err_lrx_2887), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_sm_link_up ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_trn_lnk_up_n_i), + .Q(com_llm_llm_rx_top_llm_rx_tlp_sm_link_up_2888), + .CLR(plm_link_up_i) + ); + FDP com_llm_llm_rx_top_llm_rx_tlp_sm_lnk_reof_n ( + .PRE(plm_link_up_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_sm_lnk_reof_n22_i_2889), + .Q(com_lnk_reof_n) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_sm_rx_tlp_tsn_err_crc_or_ferr ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_sm_N_39351_i), + .Q(com_rx_tlp_tsn_err_crc_or_ferr), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_sm_reg_rx_tlp_tsn_err_lrfc ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_sm_N_16443_i), + .Q(com_llm_llm_rx_top_llm_rx_tlp_sm_reg_rx_tlp_tsn_err_lrfc_2890), + .CLR(plm_link_up_i) + ); + FDP com_llm_llm_rx_top_llm_rx_tlp_sm_rx_tlp_range_err_n ( + .PRE(plm_link_up_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_sm_N_59478_i_2891), + .Q(com_rx_tlp_range_err_n) + ); + FDP com_llm_llm_rx_top_llm_rx_tlp_sm_lnk_rsrc_rdy_n ( + .PRE(plm_link_up_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_sm_N_85556_i_2892), + .Q(com_lnk_rsrc_rdy_n) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_sm_reg_rx_tlp_tsn_dup ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_sm_reg_rx_tlp_tsn_dup_3), + .Q(com_llm_reg_rx_tlp_tsn_dup), + .CLR(plm_link_up_i) + ); + FDP com_llm_llm_rx_top_llm_rx_tlp_sm_lnk_rsof_n ( + .PRE(plm_link_up_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_sm_tlp_ip_q18_i_2893), + .Q(com_lnk_rsof_n) + ); + FDC com_llm_llm_rx_top_llm_rx_tlp_sm_reg_rx_tlp_tsn_err_t ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_sm_tlp_diff_tsn[11]), + .Q(com_llm_llm_rx_top_llm_rx_tlp_sm_reg_rx_tlp_tsn_err_t_2894), + .CLR(plm_link_up_i) + ); + FDP com_llm_llm_rx_top_llm_rx_tlp_sm_lnk_rsrc_dsc_n ( + .PRE(plm_link_up_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_sm_N_85525_i_2895), + .Q(com_lnk_rsrc_dsc_n) + ); + FDCE com_llm_llm_rx_top_llm_rx_tlp_sm_tlp_range_error ( + .CE(com_llm_llm_rx_top_llm_rx_tlp_sm_N_85557_i_2896), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_sm_tlp_range_error17), + .Q(com_llm_llm_rx_top_llm_rx_tlp_sm_tlp_range_error_2897), + .CLR(plm_link_up_i) + ); + FD com_llm_llm_rx_top_llm_rx_tlp_sm_lnk_rd_12_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_rx_rd[12]), + .Q(com_lnk_rd_6113[12]) + ); + FD com_llm_llm_rx_top_llm_rx_tlp_sm_lnk_rd_11_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_rx_rd[11]), + .Q(com_lnk_rd_6113[11]) + ); + FD com_llm_llm_rx_top_llm_rx_tlp_sm_lnk_rd_10_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_rx_rd[10]), + .Q(com_lnk_rd_6113[10]) + ); + FD com_llm_llm_rx_top_llm_rx_tlp_sm_lnk_rd_9_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_rx_rd[9]), + .Q(com_lnk_rd_6113[9]) + ); + FD com_llm_llm_rx_top_llm_rx_tlp_sm_lnk_rd_8_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_rx_rd[8]), + .Q(com_lnk_rd_6113[8]) + ); + FD com_llm_llm_rx_top_llm_rx_tlp_sm_lnk_rd_7_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_rx_rd[7]), + .Q(com_lnk_rd[7]) + ); + FD com_llm_llm_rx_top_llm_rx_tlp_sm_lnk_rd_6_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_rx_rd[6]), + .Q(com_lnk_rd[6]) + ); + FD com_llm_llm_rx_top_llm_rx_tlp_sm_lnk_rd_5_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_rx_rd[5]), + .Q(com_lnk_rd[5]) + ); + FD com_llm_llm_rx_top_llm_rx_tlp_sm_lnk_rd_4_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_rx_rd[4]), + .Q(com_lnk_rd[4]) + ); + FD com_llm_llm_rx_top_llm_rx_tlp_sm_lnk_rd_3_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_rx_rd[3]), + .Q(com_lnk_rd[3]) + ); + FD com_llm_llm_rx_top_llm_rx_tlp_sm_lnk_rd_2_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_rx_rd[2]), + .Q(com_lnk_rd[2]) + ); + FD com_llm_llm_rx_top_llm_rx_tlp_sm_lnk_rd_1_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_rx_rd[1]), + .Q(com_lnk_rd[1]) + ); + FD com_llm_llm_rx_top_llm_rx_tlp_sm_lnk_rd_0_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_rx_rd[0]), + .Q(com_lnk_rd[0]) + ); + FD com_llm_llm_rx_top_llm_rx_tlp_sm_lnk_rd_27_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_rx_rd[27]), + .Q(com_lnk_rd_6113[27]) + ); + FD com_llm_llm_rx_top_llm_rx_tlp_sm_lnk_rd_26_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_rx_rd[26]), + .Q(com_lnk_rd_6113[26]) + ); + FD com_llm_llm_rx_top_llm_rx_tlp_sm_lnk_rd_25_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_rx_rd[25]), + .Q(com_lnk_rd_6113[25]) + ); + FD com_llm_llm_rx_top_llm_rx_tlp_sm_lnk_rd_24_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_rx_rd[24]), + .Q(com_lnk_rd_6113[24]) + ); + FD com_llm_llm_rx_top_llm_rx_tlp_sm_lnk_rd_23_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_rx_rd[23]), + .Q(com_lnk_rd_6113[23]) + ); + FD com_llm_llm_rx_top_llm_rx_tlp_sm_lnk_rd_22_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_rx_rd[22]), + .Q(com_lnk_rd_6113[22]) + ); + FD com_llm_llm_rx_top_llm_rx_tlp_sm_lnk_rd_21_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_rx_rd[21]), + .Q(com_lnk_rd_6113[21]) + ); + FD com_llm_llm_rx_top_llm_rx_tlp_sm_lnk_rd_20_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_rx_rd[20]), + .Q(com_lnk_rd_6113[20]) + ); + FD com_llm_llm_rx_top_llm_rx_tlp_sm_lnk_rd_19_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_rx_rd[19]), + .Q(com_lnk_rd_6113[19]) + ); + FD com_llm_llm_rx_top_llm_rx_tlp_sm_lnk_rd_18_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_rx_rd[18]), + .Q(com_lnk_rd_6113[18]) + ); + FD com_llm_llm_rx_top_llm_rx_tlp_sm_lnk_rd_17_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_rx_rd[17]), + .Q(com_lnk_rd_6113[17]) + ); + FD com_llm_llm_rx_top_llm_rx_tlp_sm_lnk_rd_16_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_rx_rd[16]), + .Q(com_lnk_rd_6113[16]) + ); + FD com_llm_llm_rx_top_llm_rx_tlp_sm_lnk_rd_15_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_rx_rd[15]), + .Q(com_lnk_rd_6113[15]) + ); + FD com_llm_llm_rx_top_llm_rx_tlp_sm_lnk_rd_14_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_rx_rd[14]), + .Q(com_lnk_rd_6113[14]) + ); + FD com_llm_llm_rx_top_llm_rx_tlp_sm_lnk_rd_13_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_rx_rd[13]), + .Q(com_lnk_rd_6113[13]) + ); + FD com_llm_llm_rx_top_llm_rx_tlp_sm_lnk_rd_42_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_rx_rd[42]), + .Q(com_lnk_rd_6113[42]) + ); + FD com_llm_llm_rx_top_llm_rx_tlp_sm_lnk_rd_41_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_rx_rd[41]), + .Q(com_lnk_rd_6113[41]) + ); + FD com_llm_llm_rx_top_llm_rx_tlp_sm_lnk_rd_40_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_rx_rd[40]), + .Q(com_lnk_rd_6113[40]) + ); + FD com_llm_llm_rx_top_llm_rx_tlp_sm_lnk_rd_39_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_rx_rd[39]), + .Q(com_lnk_rd_6113[39]) + ); + FD com_llm_llm_rx_top_llm_rx_tlp_sm_lnk_rd_38_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_rx_rd[38]), + .Q(com_lnk_rd_6113[38]) + ); + FD com_llm_llm_rx_top_llm_rx_tlp_sm_lnk_rd_37_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_rx_rd[37]), + .Q(com_lnk_rd_6113[37]) + ); + FD com_llm_llm_rx_top_llm_rx_tlp_sm_lnk_rd_36_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_rx_rd[36]), + .Q(com_lnk_rd_6113[36]) + ); + FD com_llm_llm_rx_top_llm_rx_tlp_sm_lnk_rd_35_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_rx_rd[35]), + .Q(com_lnk_rd_6113[35]) + ); + FD com_llm_llm_rx_top_llm_rx_tlp_sm_lnk_rd_34_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_rx_rd[34]), + .Q(com_lnk_rd_6113[34]) + ); + FD com_llm_llm_rx_top_llm_rx_tlp_sm_lnk_rd_33_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_rx_rd[33]), + .Q(com_lnk_rd_6113[33]) + ); + FD com_llm_llm_rx_top_llm_rx_tlp_sm_lnk_rd_32_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_rx_rd[32]), + .Q(com_lnk_rd_6113[32]) + ); + FD com_llm_llm_rx_top_llm_rx_tlp_sm_lnk_rd_31_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_rx_rd[31]), + .Q(com_lnk_rd_6113[31]) + ); + FD com_llm_llm_rx_top_llm_rx_tlp_sm_lnk_rd_30_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_rx_rd[30]), + .Q(com_lnk_rd_6113[30]) + ); + FD com_llm_llm_rx_top_llm_rx_tlp_sm_lnk_rd_29_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_rx_rd[29]), + .Q(com_lnk_rd_6113[29]) + ); + FD com_llm_llm_rx_top_llm_rx_tlp_sm_lnk_rd_28_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_rx_rd[28]), + .Q(com_lnk_rd_6113[28]) + ); + FD com_llm_llm_rx_top_llm_rx_tlp_sm_lnk_rd_57_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_rx_rd[57]), + .Q(com_lnk_rd_6113[57]) + ); + FD com_llm_llm_rx_top_llm_rx_tlp_sm_lnk_rd_56_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_rx_rd[56]), + .Q(com_lnk_rd_6113[56]) + ); + FD com_llm_llm_rx_top_llm_rx_tlp_sm_lnk_rd_55_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_rx_rd[55]), + .Q(com_lnk_rd_6113[55]) + ); + FD com_llm_llm_rx_top_llm_rx_tlp_sm_lnk_rd_54_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_rx_rd[54]), + .Q(com_lnk_rd_6113[54]) + ); + FD com_llm_llm_rx_top_llm_rx_tlp_sm_lnk_rd_53_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_rx_rd[53]), + .Q(com_lnk_rd_6113[53]) + ); + FD com_llm_llm_rx_top_llm_rx_tlp_sm_lnk_rd_52_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_rx_rd[52]), + .Q(com_lnk_rd_6113[52]) + ); + FD com_llm_llm_rx_top_llm_rx_tlp_sm_lnk_rd_51_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_rx_rd[51]), + .Q(com_lnk_rd_6113[51]) + ); + FD com_llm_llm_rx_top_llm_rx_tlp_sm_lnk_rd_50_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_rx_rd[50]), + .Q(com_lnk_rd_6113[50]) + ); + FD com_llm_llm_rx_top_llm_rx_tlp_sm_lnk_rd_49_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_rx_rd[49]), + .Q(com_lnk_rd_6113[49]) + ); + FD com_llm_llm_rx_top_llm_rx_tlp_sm_lnk_rd_48_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_rx_rd[48]), + .Q(com_lnk_rd_6113[48]) + ); + FD com_llm_llm_rx_top_llm_rx_tlp_sm_lnk_rd_47_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_rx_rd[47]), + .Q(com_lnk_rd_6113[47]) + ); + FD com_llm_llm_rx_top_llm_rx_tlp_sm_lnk_rd_46_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_rx_rd[46]), + .Q(com_lnk_rd_6113[46]) + ); + FD com_llm_llm_rx_top_llm_rx_tlp_sm_lnk_rd_45_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_rx_rd[45]), + .Q(com_lnk_rd_6113[45]) + ); + FD com_llm_llm_rx_top_llm_rx_tlp_sm_lnk_rd_44_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_rx_rd[44]), + .Q(com_lnk_rd_6113[44]) + ); + FD com_llm_llm_rx_top_llm_rx_tlp_sm_lnk_rd_43_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_rx_rd[43]), + .Q(com_lnk_rd_6113[43]) + ); + FD com_llm_llm_rx_top_llm_rx_tlp_sm_lnk_rd_63_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_rx_rd[63]), + .Q(com_lnk_rd_6113[63]) + ); + FD com_llm_llm_rx_top_llm_rx_tlp_sm_lnk_rd_62_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_rx_rd[62]), + .Q(com_lnk_rd_6113[62]) + ); + FD com_llm_llm_rx_top_llm_rx_tlp_sm_lnk_rd_61_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_rx_rd[61]), + .Q(com_lnk_rd_6113[61]) + ); + FD com_llm_llm_rx_top_llm_rx_tlp_sm_lnk_rd_60_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_rx_rd[60]), + .Q(com_lnk_rd_6113[60]) + ); + FD com_llm_llm_rx_top_llm_rx_tlp_sm_lnk_rd_59_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_rx_rd[59]), + .Q(com_lnk_rd_6113[59]) + ); + FD com_llm_llm_rx_top_llm_rx_tlp_sm_lnk_rd_58_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_rx_rd[58]), + .Q(com_lnk_rd_6113[58]) + ); + FDCE com_llm_llm_rx_top_llm_rx_tlp_sm_tlp_ip_q ( + .CE(com_llm_llm_rx_top_llm_rx_tlp_sm_N_85574_i_2898), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_rx_top_llm_rx_tlp_sm_tlp_ip_q18), + .Q(com_llm_llm_rx_top_llm_rx_tlp_sm_tlp_ip_q_2899), + .CLR(plm_link_up_i) + ); + INV com_llm_llm_rx_top_llm_rx_tlp_sm_lnk_rsof_n_i ( + .I(com_lnk_rsof_n), + .O(com_lnk_rsof_n_i) + ); + INV com_llm_llm_rx_top_llm_rx_tlp_sm_lnk_rsrc_rdy_n_i ( + .I(com_lnk_rsrc_rdy_n), + .O(com_lnk_rsrc_rdy_n_i) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_sm_tsn_eq_0_I_27.INIT = 16'h8421; + LUT4 com_llm_llm_rx_top_llm_rx_tlp_sm_tsn_eq_0_I_27 ( + .I0(com_llm_llm_rx_top_rx_tlp_tsn[10]), + .I1(com_llm_llm_rx_top_rx_tlp_tsn[11]), + .I2(com_llm_reg_next_rcv_tsn[10]), + .I3(com_llm_reg_next_rcv_tsn[11]), + .O(com_llm_llm_rx_top_llm_rx_tlp_sm_N_27) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_sm_tlp_diff_tsn_axb_10.INIT = 4'h9; + LUT2 com_llm_llm_rx_top_llm_rx_tlp_sm_tlp_diff_tsn_axb_10 ( + .I0(com_llm_llm_rx_top_rx_tlp_tsn[10]), + .I1(com_llm_reg_next_rcv_tsn[10]), + .O(com_llm_llm_rx_top_llm_rx_tlp_sm_tlp_diff_tsn_axb_10_2900) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_sm_tlp_diff_tsn_axb_9.INIT = 4'h9; + LUT2 com_llm_llm_rx_top_llm_rx_tlp_sm_tlp_diff_tsn_axb_9 ( + .I0(com_llm_llm_rx_top_rx_tlp_tsn[9]), + .I1(com_llm_reg_next_rcv_tsn[9]), + .O(com_llm_llm_rx_top_llm_rx_tlp_sm_tlp_diff_tsn_axb_9_2901) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_sm_tlp_diff_tsn_axb_8.INIT = 4'h9; + LUT2 com_llm_llm_rx_top_llm_rx_tlp_sm_tlp_diff_tsn_axb_8 ( + .I0(com_llm_llm_rx_top_rx_tlp_tsn[8]), + .I1(com_llm_reg_next_rcv_tsn[8]), + .O(com_llm_llm_rx_top_llm_rx_tlp_sm_tlp_diff_tsn_axb_8_2902) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_sm_tlp_diff_tsn_axb_7.INIT = 4'h9; + LUT2 com_llm_llm_rx_top_llm_rx_tlp_sm_tlp_diff_tsn_axb_7 ( + .I0(com_llm_llm_rx_top_rx_tlp_tsn[7]), + .I1(com_llm_reg_next_rcv_tsn[7]), + .O(com_llm_llm_rx_top_llm_rx_tlp_sm_tlp_diff_tsn_axb_7_2903) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_sm_tlp_diff_tsn_axb_6.INIT = 4'h9; + LUT2 com_llm_llm_rx_top_llm_rx_tlp_sm_tlp_diff_tsn_axb_6 ( + .I0(com_llm_llm_rx_top_rx_tlp_tsn[6]), + .I1(com_llm_reg_next_rcv_tsn[6]), + .O(com_llm_llm_rx_top_llm_rx_tlp_sm_tlp_diff_tsn_axb_6_2904) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_sm_tlp_diff_tsn_axb_5.INIT = 4'h9; + LUT2 com_llm_llm_rx_top_llm_rx_tlp_sm_tlp_diff_tsn_axb_5 ( + .I0(com_llm_llm_rx_top_rx_tlp_tsn[5]), + .I1(com_llm_reg_next_rcv_tsn[5]), + .O(com_llm_llm_rx_top_llm_rx_tlp_sm_tlp_diff_tsn_axb_5_2905) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_sm_tlp_diff_tsn_axb_4.INIT = 4'h9; + LUT2 com_llm_llm_rx_top_llm_rx_tlp_sm_tlp_diff_tsn_axb_4 ( + .I0(com_llm_llm_rx_top_rx_tlp_tsn[4]), + .I1(com_llm_reg_next_rcv_tsn[4]), + .O(com_llm_llm_rx_top_llm_rx_tlp_sm_tlp_diff_tsn_axb_4_2906) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_sm_tlp_diff_tsn_axb_3.INIT = 4'h9; + LUT2 com_llm_llm_rx_top_llm_rx_tlp_sm_tlp_diff_tsn_axb_3 ( + .I0(com_llm_llm_rx_top_rx_tlp_tsn[3]), + .I1(com_llm_reg_next_rcv_tsn[3]), + .O(com_llm_llm_rx_top_llm_rx_tlp_sm_tlp_diff_tsn_axb_3_2907) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_sm_tlp_diff_tsn_axb_2.INIT = 4'h9; + LUT2 com_llm_llm_rx_top_llm_rx_tlp_sm_tlp_diff_tsn_axb_2 ( + .I0(com_llm_llm_rx_top_rx_tlp_tsn[2]), + .I1(com_llm_reg_next_rcv_tsn[2]), + .O(com_llm_llm_rx_top_llm_rx_tlp_sm_tlp_diff_tsn_axb_2_2908) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_sm_tlp_diff_tsn_axb_1.INIT = 4'h9; + LUT2 com_llm_llm_rx_top_llm_rx_tlp_sm_tlp_diff_tsn_axb_1 ( + .I0(com_llm_llm_rx_top_rx_tlp_tsn[1]), + .I1(com_llm_reg_next_rcv_tsn[1]), + .O(com_llm_llm_rx_top_llm_rx_tlp_sm_tlp_diff_tsn_axb_1_2909) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_sm_tlp_diff_tsn_axb_0.INIT = 4'h9; + LUT2 com_llm_llm_rx_top_llm_rx_tlp_sm_tlp_diff_tsn_axb_0 ( + .I0(com_llm_llm_rx_top_rx_tlp_tsn[0]), + .I1(com_llm_reg_next_rcv_tsn[0]), + .O(com_llm_llm_rx_top_llm_rx_tlp_sm_tlp_diff_tsn_axb_0_2910) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_sm_tsn_eq_0_I_54.INIT = 16'h8421; + LUT4 com_llm_llm_rx_top_llm_rx_tlp_sm_tsn_eq_0_I_54 ( + .I0(com_llm_llm_rx_top_rx_tlp_tsn[2]), + .I1(com_llm_llm_rx_top_rx_tlp_tsn[3]), + .I2(com_llm_reg_next_rcv_tsn[2]), + .I3(com_llm_reg_next_rcv_tsn[3]), + .O(com_llm_llm_rx_top_llm_rx_tlp_sm_N_3) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_sm_tsn_eq_0_I_45.INIT = 16'h8421; + LUT4 com_llm_llm_rx_top_llm_rx_tlp_sm_tsn_eq_0_I_45 ( + .I0(com_llm_llm_rx_top_rx_tlp_tsn[8]), + .I1(com_llm_llm_rx_top_rx_tlp_tsn[9]), + .I2(com_llm_reg_next_rcv_tsn[8]), + .I3(com_llm_reg_next_rcv_tsn[9]), + .O(com_llm_llm_rx_top_llm_rx_tlp_sm_N_11) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_sm_tsn_eq_0_I_36.INIT = 16'h8421; + LUT4 com_llm_llm_rx_top_llm_rx_tlp_sm_tsn_eq_0_I_36 ( + .I0(com_llm_llm_rx_top_rx_tlp_tsn[6]), + .I1(com_llm_llm_rx_top_rx_tlp_tsn[7]), + .I2(com_llm_reg_next_rcv_tsn[6]), + .I3(com_llm_reg_next_rcv_tsn[7]), + .O(com_llm_llm_rx_top_llm_rx_tlp_sm_N_19) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_sm_tsn_eq_0_I_18.INIT = 16'h8421; + LUT4 com_llm_llm_rx_top_llm_rx_tlp_sm_tsn_eq_0_I_18 ( + .I0(com_llm_llm_rx_top_rx_tlp_tsn[4]), + .I1(com_llm_llm_rx_top_rx_tlp_tsn[5]), + .I2(com_llm_reg_next_rcv_tsn[4]), + .I3(com_llm_reg_next_rcv_tsn[5]), + .O(com_llm_llm_rx_top_llm_rx_tlp_sm_N_35) + ); + defparam com_llm_llm_rx_top_llm_rx_tlp_sm_tsn_eq_0_I_9.INIT = 16'h8421; + LUT4 com_llm_llm_rx_top_llm_rx_tlp_sm_tsn_eq_0_I_9 ( + .I0(com_llm_llm_rx_top_rx_tlp_tsn[0]), + .I1(com_llm_llm_rx_top_rx_tlp_tsn[1]), + .I2(com_llm_reg_next_rcv_tsn[0]), + .I3(com_llm_reg_next_rcv_tsn[1]), + .O(com_llm_llm_rx_top_llm_rx_tlp_sm_N_43) + ); + defparam com_llm_llm_common_reg_replay_to_val_3_13_.INIT = 4'h8; + LUT2_L com_llm_llm_common_reg_replay_to_val_3_13_ ( + .I0(cfg_cfg_6102[461]), + .I1(cfg_cfg_6102[463]), + .LO(com_llm_llm_common_reg_replay_to_val_3[13]) + ); + defparam com_llm_llm_common_reg_replay_to_val_3_12_.INIT = 4'h8; + LUT2_L com_llm_llm_common_reg_replay_to_val_3_12_ ( + .I0(cfg_cfg_6102[460]), + .I1(cfg_cfg_6102[463]), + .LO(com_llm_llm_common_reg_replay_to_val_3[12]) + ); + defparam com_llm_llm_common_reg_replay_to_val_3_11_.INIT = 4'h8; + LUT2_L com_llm_llm_common_reg_replay_to_val_3_11_ ( + .I0(cfg_cfg_6102[459]), + .I1(cfg_cfg_6102[463]), + .LO(com_llm_llm_common_reg_replay_to_val_3[11]) + ); + defparam com_llm_llm_common_reg_replay_to_val_3_10_.INIT = 4'h8; + LUT2_L com_llm_llm_common_reg_replay_to_val_3_10_ ( + .I0(cfg_cfg_6102[458]), + .I1(cfg_cfg_6102[463]), + .LO(com_llm_llm_common_reg_replay_to_val_3[10]) + ); + defparam com_llm_llm_common_reg_replay_to_val_3_9_.INIT = 4'h8; + LUT2_L com_llm_llm_common_reg_replay_to_val_3_9_ ( + .I0(cfg_cfg_6102[457]), + .I1(cfg_cfg_6102[463]), + .LO(com_llm_llm_common_reg_replay_to_val_3[9]) + ); + defparam com_llm_llm_common_reg_replay_to_val_3_8_.INIT = 4'h8; + LUT2_L com_llm_llm_common_reg_replay_to_val_3_8_ ( + .I0(cfg_cfg_6102[456]), + .I1(cfg_cfg_6102[463]), + .LO(com_llm_llm_common_reg_replay_to_val_3[8]) + ); + defparam com_llm_llm_common_reg_replay_to_val_3_0_7_.INIT = 8'hB8; + LUT3_L com_llm_llm_common_reg_replay_to_val_3_0_7_ ( + .I0(cfg_cfg_6102[455]), + .I1(cfg_cfg_6102[463]), + .I2(com_llm_llm_common_val_1[7]), + .LO(com_llm_llm_common_reg_replay_to_val_3[7]) + ); + defparam com_llm_llm_common_reg_replay_to_val_3_0_6_.INIT = 8'hB8; + LUT3_L com_llm_llm_common_reg_replay_to_val_3_0_6_ ( + .I0(cfg_cfg_6102[454]), + .I1(cfg_cfg_6102[463]), + .I2(com_llm_llm_common_val_1[6]), + .LO(com_llm_llm_common_reg_replay_to_val_3[6]) + ); + defparam com_llm_llm_common_reg_replay_to_val_3_0_5_.INIT = 8'hB8; + LUT3_L com_llm_llm_common_reg_replay_to_val_3_0_5_ ( + .I0(cfg_cfg_6102[453]), + .I1(cfg_cfg_6102[463]), + .I2(com_llm_llm_common_val_1[5]), + .LO(com_llm_llm_common_reg_replay_to_val_3[5]) + ); + defparam com_llm_llm_common_reg_replay_to_val_3_0_4_.INIT = 8'hB8; + LUT3_L com_llm_llm_common_reg_replay_to_val_3_0_4_ ( + .I0(cfg_cfg_6102[452]), + .I1(cfg_cfg_6102[463]), + .I2(com_llm_llm_common_val_1[4]), + .LO(com_llm_llm_common_reg_replay_to_val_3[4]) + ); + defparam com_llm_llm_common_reg_replay_to_val_3_0_3_.INIT = 8'hB8; + LUT3_L com_llm_llm_common_reg_replay_to_val_3_0_3_ ( + .I0(cfg_cfg_6102[451]), + .I1(cfg_cfg_6102[463]), + .I2(com_llm_llm_common_val_1[3]), + .LO(com_llm_llm_common_reg_replay_to_val_3[3]) + ); + defparam com_llm_llm_common_reg_replay_to_val_3_0_2_.INIT = 8'hB8; + LUT3_L com_llm_llm_common_reg_replay_to_val_3_0_2_ ( + .I0(cfg_cfg_6102[450]), + .I1(cfg_cfg_6102[463]), + .I2(com_llm_llm_common_val_1[2]), + .LO(com_llm_llm_common_reg_replay_to_val_3[2]) + ); + defparam com_llm_llm_common_reg_replay_to_val_3_0_1_.INIT = 8'hB8; + LUT3_L com_llm_llm_common_reg_replay_to_val_3_0_1_ ( + .I0(cfg_cfg_6102[449]), + .I1(cfg_cfg_6102[463]), + .I2(com_llm_llm_common_val_1[1]), + .LO(com_llm_llm_common_reg_replay_to_val_3[1]) + ); + defparam com_llm_llm_common_reg_replay_to_val_3_0_0_.INIT = 8'hB8; + LUT3_L com_llm_llm_common_reg_replay_to_val_3_0_0_ ( + .I0(cfg_cfg_6102[448]), + .I1(cfg_cfg_6102[463]), + .I2(com_llm_llm_common_val_1[0]), + .LO(com_llm_llm_common_reg_replay_to_val_3[0]) + ); + defparam com_llm_llm_common_reg_ack_to_val_3_13_.INIT = 16'hB888; + LUT4_L com_llm_llm_common_reg_ack_to_val_3_13_ ( + .I0(cfg_cfg_6102[445]), + .I1(cfg_cfg_6102[447]), + .I2(NlwRenamedSig_OI_cfg_lcommand_7_), + .I3(com_llm_llm_common_val_1[5]), + .LO(com_llm_llm_common_reg_ack_to_val_3[13]) + ); + defparam com_llm_llm_common_reg_ack_to_val_3_12_.INIT = 4'h8; + LUT2_L com_llm_llm_common_reg_ack_to_val_3_12_ ( + .I0(cfg_cfg_6102[444]), + .I1(cfg_cfg_6102[447]), + .LO(com_llm_llm_common_reg_ack_to_val_3[12]) + ); + defparam com_llm_llm_common_reg_ack_to_val_3_11_.INIT = 16'hB888; + LUT4_L com_llm_llm_common_reg_ack_to_val_3_11_ ( + .I0(cfg_cfg_6102[443]), + .I1(cfg_cfg_6102[447]), + .I2(NlwRenamedSig_OI_cfg_lcommand_7_), + .I3(com_llm_llm_common_val_3_7_), + .LO(com_llm_llm_common_reg_ack_to_val_3[11]) + ); + defparam com_llm_llm_common_reg_ack_to_val_3_0_10_.INIT = 4'h8; + LUT2_L com_llm_llm_common_reg_ack_to_val_3_0_10_ ( + .I0(cfg_cfg_6102[442]), + .I1(cfg_cfg_6102[447]), + .LO(com_llm_llm_common_reg_ack_to_val_3[10]) + ); + defparam com_llm_llm_common_reg_ack_to_val_3_1_9_.INIT = 16'h8B88; + LUT4_L com_llm_llm_common_reg_ack_to_val_3_1_9_ ( + .I0(cfg_cfg_6102[441]), + .I1(cfg_cfg_6102[447]), + .I2(NlwRenamedSig_OI_cfg_lcommand_7_), + .I3(com_llm_llm_common_val_1[5]), + .LO(com_llm_llm_common_reg_ack_to_val_3[9]) + ); + defparam com_llm_llm_common_reg_ack_to_val_3_8_.INIT = 4'h8; + LUT2_L com_llm_llm_common_reg_ack_to_val_3_8_ ( + .I0(cfg_cfg_6102[440]), + .I1(cfg_cfg_6102[447]), + .LO(com_llm_llm_common_reg_ack_to_val_3[8]) + ); + defparam com_llm_llm_common_reg_ack_to_val_3_1_7_.INIT = 16'h8B88; + LUT4_L com_llm_llm_common_reg_ack_to_val_3_1_7_ ( + .I0(cfg_cfg_6102[439]), + .I1(cfg_cfg_6102[447]), + .I2(NlwRenamedSig_OI_cfg_lcommand_7_), + .I3(com_llm_llm_common_val_3_7_), + .LO(com_llm_llm_common_reg_ack_to_val_3[7]) + ); + defparam com_llm_llm_common_reg_ack_to_val_3_0_0_6_.INIT = 8'hB8; + LUT3_L com_llm_llm_common_reg_ack_to_val_3_0_0_6_ ( + .I0(cfg_cfg_6102[438]), + .I1(cfg_cfg_6102[447]), + .I2(com_llm_llm_common_val_2_6_), + .LO(com_llm_llm_common_reg_ack_to_val_3_0_0[6]) + ); + defparam com_llm_llm_common_reg_ack_to_val_3_0_0_5_.INIT = 8'hB8; + LUT3_L com_llm_llm_common_reg_ack_to_val_3_0_0_5_ ( + .I0(cfg_cfg_6102[437]), + .I1(cfg_cfg_6102[447]), + .I2(com_llm_llm_common_val_3_5_), + .LO(com_llm_llm_common_reg_ack_to_val_3_0_0[5]) + ); + defparam com_llm_llm_common_reg_ack_to_val_3_0_0_4_.INIT = 8'hB8; + LUT3_L com_llm_llm_common_reg_ack_to_val_3_0_0_4_ ( + .I0(cfg_cfg_6102[436]), + .I1(cfg_cfg_6102[447]), + .I2(com_llm_llm_common_val_3_4_), + .LO(com_llm_llm_common_reg_ack_to_val_3_0_0[4]) + ); + defparam com_llm_llm_common_reg_ack_to_val_3_0_0_3_.INIT = 8'hB8; + LUT3_L com_llm_llm_common_reg_ack_to_val_3_0_0_3_ ( + .I0(cfg_cfg_6102[435]), + .I1(cfg_cfg_6102[447]), + .I2(com_llm_llm_common_val_3_3_), + .LO(com_llm_llm_common_reg_ack_to_val_3_0_0[3]) + ); + defparam com_llm_llm_common_reg_ack_to_val_3_0_0_2_.INIT = 8'hB8; + LUT3_L com_llm_llm_common_reg_ack_to_val_3_0_0_2_ ( + .I0(cfg_cfg_6102[434]), + .I1(cfg_cfg_6102[447]), + .I2(com_llm_llm_common_val_2_2_), + .LO(com_llm_llm_common_reg_ack_to_val_3_0_0[2]) + ); + defparam com_llm_llm_common_reg_ack_to_val_3_0_0_1_.INIT = 8'hB8; + LUT3_L com_llm_llm_common_reg_ack_to_val_3_0_0_1_ ( + .I0(cfg_cfg_6102[433]), + .I1(cfg_cfg_6102[447]), + .I2(com_llm_llm_common_val_2_1_), + .LO(com_llm_llm_common_reg_ack_to_val_3_0_0[1]) + ); + defparam com_llm_llm_common_reg_ack_to_val_3_0_0_0_.INIT = 8'hB8; + LUT3_L com_llm_llm_common_reg_ack_to_val_3_0_0_0_ ( + .I0(cfg_cfg_6102[432]), + .I1(cfg_cfg_6102[447]), + .I2(com_llm_llm_common_val_3_0_), + .LO(com_llm_llm_common_reg_ack_to_val_3_0_0[0]) + ); + defparam com_llm_llm_common_reg_replay_to_val_3_14_.INIT = 4'h8; + LUT2_L com_llm_llm_common_reg_replay_to_val_3_14_ ( + .I0(cfg_cfg_6102[462]), + .I1(cfg_cfg_6102[463]), + .LO(com_llm_llm_common_reg_replay_to_val_3[14]) + ); + defparam com_llm_llm_common_reg_ack_to_val_3_0_14_.INIT = 4'h8; + LUT2_L com_llm_llm_common_reg_ack_to_val_3_0_14_ ( + .I0(cfg_cfg_6102[446]), + .I1(cfg_cfg_6102[447]), + .LO(com_llm_llm_common_reg_ack_to_val_3[14]) + ); + FDC com_llm_llm_common_reg_tx_update_retry_q ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_reg_tx_update_retry_int), + .Q(com_reg_tx_update_retry_q), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_common_reg_replay_to_val_13_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_common_reg_replay_to_val_3[13]), + .Q(com_llm_llm_common_reg_replay_to_val[13]), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_common_reg_replay_to_val_12_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_common_reg_replay_to_val_3[12]), + .Q(com_llm_llm_common_reg_replay_to_val[12]), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_common_reg_replay_to_val_11_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_common_reg_replay_to_val_3[11]), + .Q(com_llm_llm_common_reg_replay_to_val[11]), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_common_reg_replay_to_val_10_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_common_reg_replay_to_val_3[10]), + .Q(com_llm_llm_common_reg_replay_to_val[10]), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_common_reg_replay_to_val_9_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_common_reg_replay_to_val_3[9]), + .Q(com_llm_llm_common_reg_replay_to_val[9]), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_common_reg_replay_to_val_8_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_common_reg_replay_to_val_3[8]), + .Q(com_llm_llm_common_reg_replay_to_val[8]), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_common_reg_replay_to_val_7_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_common_reg_replay_to_val_3[7]), + .Q(com_llm_llm_common_reg_replay_to_val[7]), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_common_reg_replay_to_val_6_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_common_reg_replay_to_val_3[6]), + .Q(com_llm_llm_common_reg_replay_to_val[6]), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_common_reg_replay_to_val_5_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_common_reg_replay_to_val_3[5]), + .Q(com_llm_llm_common_reg_replay_to_val[5]), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_common_reg_replay_to_val_4_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_common_reg_replay_to_val_3[4]), + .Q(com_llm_llm_common_reg_replay_to_val[4]), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_common_reg_replay_to_val_3_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_common_reg_replay_to_val_3[3]), + .Q(com_llm_llm_common_reg_replay_to_val[3]), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_common_reg_replay_to_val_2_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_common_reg_replay_to_val_3[2]), + .Q(com_llm_llm_common_reg_replay_to_val[2]), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_common_reg_replay_to_val_1_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_common_reg_replay_to_val_3[1]), + .Q(com_llm_llm_common_reg_replay_to_val[1]), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_common_reg_replay_to_val_0_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_common_reg_replay_to_val_3[0]), + .Q(com_llm_llm_common_reg_replay_to_val[0]), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_common_reg_ack_to_val_13_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_common_reg_ack_to_val_3[13]), + .Q(com_llm_reg_ack_to_val[13]), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_common_reg_ack_to_val_12_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_common_reg_ack_to_val_3[12]), + .Q(com_llm_reg_ack_to_val[12]), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_common_reg_ack_to_val_11_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_common_reg_ack_to_val_3[11]), + .Q(com_llm_reg_ack_to_val[11]), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_common_reg_ack_to_val_10_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_common_reg_ack_to_val_3[10]), + .Q(com_llm_reg_ack_to_val[10]), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_common_reg_ack_to_val_9_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_common_reg_ack_to_val_3[9]), + .Q(com_llm_reg_ack_to_val[9]), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_common_reg_ack_to_val_8_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_common_reg_ack_to_val_3[8]), + .Q(com_llm_reg_ack_to_val[8]), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_common_reg_ack_to_val_7_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_common_reg_ack_to_val_3[7]), + .Q(com_llm_reg_ack_to_val[7]), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_common_reg_ack_to_val_6_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_common_reg_ack_to_val_3_0_0[6]), + .Q(com_llm_reg_ack_to_val[6]), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_common_reg_ack_to_val_5_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_common_reg_ack_to_val_3_0_0[5]), + .Q(com_llm_reg_ack_to_val[5]), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_common_reg_ack_to_val_4_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_common_reg_ack_to_val_3_0_0[4]), + .Q(com_llm_reg_ack_to_val[4]), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_common_reg_ack_to_val_3_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_common_reg_ack_to_val_3_0_0[3]), + .Q(com_llm_reg_ack_to_val[3]), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_common_reg_ack_to_val_2_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_common_reg_ack_to_val_3_0_0[2]), + .Q(com_llm_reg_ack_to_val[2]), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_common_reg_ack_to_val_1_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_common_reg_ack_to_val_3_0_0[1]), + .Q(com_llm_reg_ack_to_val[1]), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_common_reg_ack_to_val_0_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_common_reg_ack_to_val_3_0_0[0]), + .Q(com_llm_reg_ack_to_val[0]), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_common_reg_replay_to_val_14_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_common_reg_replay_to_val_3[14]), + .Q(com_llm_llm_common_reg_replay_to_val[14]), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_common_reg_ack_to_val_14_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_common_reg_ack_to_val_3[14]), + .Q(com_llm_reg_ack_to_val[14]), + .CLR(plm_link_up_i) + ); + FDS com_llm_llm_common_replay_table_lat_o_1_6_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_common_replay_table_N_86015_i_2912), + .Q(com_llm_llm_common_val_1[6]), + .S(NlwRenamedSig_OI_cfg_dcommand[6]) + ); + FDS com_llm_llm_common_replay_table_lat_o_1_4_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_N_56202_i), + .Q(com_llm_llm_common_val_1[4]), + .S(com_N_3206_i_i) + ); + FDR com_llm_llm_common_replay_table_lat_o_1_3_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_common_replay_table_lat_o_1c_i), + .Q(com_llm_llm_common_val_1[3]), + .R(NlwRenamedSig_OI_cfg_dcommand[6]) + ); + FDR com_llm_llm_common_replay_table_lat_o_1_1_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(NlwRenamedSig_OI_cfg_lstatus_6_), + .Q(com_llm_llm_common_val_1[1]), + .R(com_N_56034_i) + ); + FDS com_llm_llm_common_replay_table_lat_o_1_0_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(NlwRenamedSig_OI_cfg_lstatus_6_), + .Q(com_llm_llm_common_val_1[0]), + .S(com_N_56034_i_i) + ); + FDS com_llm_llm_common_replay_table_lat_o_1_7_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_common_replay_table_N_86017_i_2911), + .Q(com_llm_llm_common_val_1[7]), + .S(NlwRenamedSig_OI_cfg_dcommand[6]) + ); + defparam com_llm_llm_common_replay_table_lat_d_i_a2_i_0_0_o3_4_.INIT = 4'h8; + LUT2 com_llm_llm_common_replay_table_lat_d_i_a2_i_0_0_o3_4_ ( + .I0(com_N_56034_i), + .I1(NlwRenamedSig_OI_cfg_dcommand[5]), + .O(com_N_56202_i) + ); + defparam com_llm_llm_common_replay_table_N_56202_i_i.INIT = 4'h1; + LUT1_L com_llm_llm_common_replay_table_N_56202_i_i ( + .I0(com_N_56202_i), + .LO(com_llm_llm_common_N_56202_i_i) + ); + defparam com_llm_llm_common_replay_table_N_86017_i.INIT = 4'hE; + LUT2_L com_llm_llm_common_replay_table_N_86017_i ( + .I0(NlwRenamedSig_OI_cfg_dcommand[5]), + .I1(NlwRenamedSig_OI_cfg_dcommand[7]), + .LO(com_llm_llm_common_replay_table_N_86017_i_2911) + ); + defparam com_llm_llm_common_replay_table_lat_o_1c.INIT = 8'h07; + LUT3_L com_llm_llm_common_replay_table_lat_o_1c ( + .I0(NlwRenamedSig_OI_cfg_lstatus_6_), + .I1(NlwRenamedSig_OI_cfg_dcommand[5]), + .I2(NlwRenamedSig_OI_cfg_dcommand[7]), + .LO(com_llm_llm_common_replay_table_lat_o_1c_i) + ); + defparam com_llm_llm_common_replay_table_N_86015_i.INIT = 4'hD; + LUT2_L com_llm_llm_common_replay_table_N_86015_i ( + .I0(NlwRenamedSig_OI_cfg_dcommand[5]), + .I1(NlwRenamedSig_OI_cfg_dcommand[7]), + .LO(com_llm_llm_common_replay_table_N_86015_i_2912) + ); + defparam com_llm_llm_common_replay_table_N_56486_i_0_i.INIT = 4'h6; + LUT2_L com_llm_llm_common_replay_table_N_56486_i_0_i ( + .I0(NlwRenamedSig_OI_cfg_lstatus_6_), + .I1(com_N_56202_i), + .LO(com_llm_llm_common_replay_table_N_56486_i_0_i_2913) + ); + FD com_llm_llm_common_replay_table_lat_o_1_2_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_common_replay_table_N_56486_i_0_i_2913), + .Q(com_llm_llm_common_val_1[2]) + ); + FDR com_llm_llm_common_ack_synch_table_lat_o_1_5_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_common_ack_synch_table_lat_o_1c_0_i), + .Q(com_llm_llm_common_val_3_5_), + .R(NlwRenamedSig_OI_cfg_dcommand[6]) + ); + FDR com_llm_llm_common_ack_synch_table_lat_o_1_4_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_common_ack_synch_table_lat_o_1c_i), + .Q(com_llm_llm_common_val_3_4_), + .R(NlwRenamedSig_OI_cfg_dcommand[6]) + ); + defparam com_llm_llm_common_ack_synch_table_lat_o_1c.INIT = 8'h0D; + LUT3_L com_llm_llm_common_ack_synch_table_lat_o_1c ( + .I0(NlwRenamedSig_OI_cfg_lstatus_6_), + .I1(NlwRenamedSig_OI_cfg_dcommand[5]), + .I2(NlwRenamedSig_OI_cfg_dcommand[7]), + .LO(com_llm_llm_common_ack_synch_table_lat_o_1c_i) + ); + defparam com_llm_llm_common_ack_synch_table_lat_o_1c_0.INIT = 8'h0E; + LUT3_L com_llm_llm_common_ack_synch_table_lat_o_1c_0 ( + .I0(NlwRenamedSig_OI_cfg_lstatus_6_), + .I1(NlwRenamedSig_OI_cfg_dcommand[5]), + .I2(NlwRenamedSig_OI_cfg_dcommand[7]), + .LO(com_llm_llm_common_ack_synch_table_lat_o_1c_0_i) + ); + defparam com_llm_llm_common_ack_synch_table_N_56484_i_0_i.INIT = 4'h6; + LUT2_L com_llm_llm_common_ack_synch_table_N_56484_i_0_i ( + .I0(NlwRenamedSig_OI_cfg_lstatus_6_), + .I1(com_N_56233_i), + .LO(com_llm_llm_common_ack_synch_table_N_56484_i_0_i_2914) + ); + FD com_llm_llm_common_ack_synch_table_lat_o_1_11_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_N_3206_i_i), + .Q(com_llm_llm_common_val_3_7_) + ); + FD com_llm_llm_common_ack_synch_table_lat_o_1_3_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_common_ack_synch_table_N_56484_i_0_i_2914), + .Q(com_llm_llm_common_val_3_3_) + ); + FD com_llm_llm_common_ack_synch_table_lat_o_1_0_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_common_lat_d_i_i_m3_i_m4_i_m3_0[0]), + .Q(com_llm_llm_common_val_3_0_) + ); + FDS com_llm_llm_common_ack_no_synch_table_lat_o_1_6_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(NlwRenamedSig_OI_cfg_dcommand[7]), + .Q(com_llm_llm_common_val_2_6_), + .S(NlwRenamedSig_OI_cfg_dcommand[6]) + ); + FDS com_llm_llm_common_ack_no_synch_table_lat_o_1_2_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_common_N_56202_i_i), + .Q(com_llm_llm_common_val_2_2_), + .S(com_N_3206_i_i) + ); + FDR com_llm_llm_common_ack_no_synch_table_lat_o_1_1_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_N_56202_i), + .Q(com_llm_llm_common_val_2_1_), + .R(com_N_3206_i_i) + ); + defparam com_llm_llm_common_ack_no_synch_table_lat_d_0_0_0_0_o2_5_.INIT = 4'h1; + LUT2 com_llm_llm_common_ack_no_synch_table_lat_d_0_0_0_0_o2_5_ ( + .I0(NlwRenamedSig_OI_cfg_dcommand[6]), + .I1(NlwRenamedSig_OI_cfg_dcommand[7]), + .O(com_N_56034_i) + ); + defparam com_llm_llm_common_ack_no_synch_table_lat_d_i_o2_0_o3_i_o4_i_o3_0_.INIT = 4'h2; + LUT2 com_llm_llm_common_ack_no_synch_table_lat_d_i_o2_0_o3_i_o4_i_o3_0_ ( + .I0(com_N_56034_i), + .I1(NlwRenamedSig_OI_cfg_dcommand[5]), + .O(com_N_56233_i) + ); + defparam com_llm_llm_common_ack_no_synch_table_lat_d_i_i_m3_i_m4_i_m3_0_0_.INIT = 8'hB7; + LUT3_L com_llm_llm_common_ack_no_synch_table_lat_d_i_i_m3_i_m4_i_m3_0_0_ ( + .I0(NlwRenamedSig_OI_cfg_lstatus_6_), + .I1(com_N_56034_i), + .I2(NlwRenamedSig_OI_cfg_dcommand[5]), + .LO(com_llm_llm_common_lat_d_i_i_m3_i_m4_i_m3_0[0]) + ); + FD com_llm_llm_common_ack_no_synch_table_lat_o_1_9_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(NlwRenamedSig_OI_cfg_lstatus_6_), + .Q(com_llm_llm_common_val_1[5]) + ); + INV com_llm_llm_common_ack_no_synch_table_N_56034_i_i ( + .I(com_N_56034_i), + .O(com_N_56034_i_i) + ); + defparam com_llm_llm_common_llm_link_sm_llm_link_main_sm_ns_link_i_i_0_0_0_a2_1_.INIT = 8'h13; + LUT3 com_llm_llm_common_llm_link_sm_llm_link_main_sm_ns_link_i_i_0_0_0_a2_1_ ( + .I0(com_llm_link_status[0]), + .I1(com_link_status[1]), + .I2(plm_link_l0), + .O(com_llm_llm_common_llm_link_sm_llm_link_main_sm_N_58438) + ); + defparam com_llm_llm_common_llm_link_sm_llm_link_main_sm_ns_link_i_0_0_0_i_o3_0_2_.INIT = 16'h8000; + LUT4 com_llm_llm_common_llm_link_sm_llm_link_main_sm_ns_link_i_0_0_0_i_o3_0_2_ ( + .I0(com_llm_llm_common_llm_link_sm_llm_link_main_sm_link_fccpl_rcvq), + .I1(com_llm_llm_common_llm_link_sm_llm_link_main_sm_link_fcnp_rcvq), + .I2(com_llm_llm_common_llm_link_sm_llm_link_main_sm_link_fcp_rcvq), + .I3(plm_link_l0), + .O(com_llm_llm_common_llm_link_sm_llm_link_main_sm_N_56934_i) + ); + defparam com_llm_llm_common_llm_link_sm_llm_link_main_sm_ns_link_i_0_0_0_i_o3_1_2_.INIT = 16'h001F; + LUT4 com_llm_llm_common_llm_link_sm_llm_link_main_sm_ns_link_i_0_0_0_i_o3_1_2_ ( + .I0(com_llm_link_li2_rcv), + .I1(com_llm_link_update_fc_rcv), + .I2(com_llm_link_vc_rcv[0]), + .I3(com_lnk_tfc_vc_hit), + .O(com_llm_llm_common_llm_link_sm_llm_link_main_sm_N_56977_i) + ); + defparam com_llm_llm_common_llm_link_sm_llm_link_main_sm_ns_link_i_i_i_a2_i_0_a2_3_.INIT = 4'h8; + LUT2_L com_llm_llm_common_llm_link_sm_llm_link_main_sm_ns_link_i_i_i_a2_i_0_a2_3_ ( + .I0(com_N_56127_i), + .I1(com_llm_llm_common_llm_link_sm_llm_link_main_sm_N_56977_i), + .LO(com_llm_llm_common_llm_link_sm_llm_link_main_sm_N_60893) + ); + defparam com_llm_llm_common_llm_link_sm_llm_link_main_sm_ns_link_i_0_0_0_i_1_2_.INIT = 16'hF800; + LUT4_L com_llm_llm_common_llm_link_sm_llm_link_main_sm_ns_link_i_0_0_0_i_1_2_ ( + .I0(com_llm_llm_common_llm_link_sm_llm_link_main_sm_N_56934_i), + .I1(com_link_status[1]), + .I2(com_link_status[2]), + .I3(plm_link_up_1), + .LO(com_llm_llm_common_llm_link_sm_llm_link_main_sm_ns_link_i_0_0_0_i_1[2]) + ); + defparam com_llm_llm_common_llm_link_sm_llm_link_main_sm_trn_lnk_up_n_i.INIT = 4'h1; + LUT1_L com_llm_llm_common_llm_link_sm_llm_link_main_sm_trn_lnk_up_n_i ( + .I0(NlwRenamedSig_OI_trn_lnk_up_n), + .LO(com_llm_trn_lnk_up_n_i) + ); + defparam com_llm_llm_common_llm_link_sm_llm_link_main_sm_N_87093_i.INIT = 8'h2F; + LUT3_L com_llm_llm_common_llm_link_sm_llm_link_main_sm_N_87093_i ( + .I0(com_llm_link_status[0]), + .I1(plm_link_l0), + .I2(plm_link_up_2), + .LO(com_llm_llm_common_llm_link_sm_llm_link_main_sm_N_87093_i_2915) + ); + defparam com_llm_llm_common_llm_link_sm_llm_link_main_sm_ns_link_i_i_i_a2_i_0_4_.INIT = 8'h10; + LUT3_L com_llm_llm_common_llm_link_sm_llm_link_main_sm_ns_link_i_i_i_a2_i_0_4_ ( + .I0(com_N_56127_i), + .I1(plm_link_l0), + .I2(plm_link_up_2), + .LO(com_llm_llm_common_llm_link_sm_llm_link_main_sm_N_46610_i) + ); + defparam com_llm_llm_common_llm_link_sm_llm_link_main_sm_ns_link_i_i_i_a2_i_0_3_.INIT = 16'h0040; + LUT4_L com_llm_llm_common_llm_link_sm_llm_link_main_sm_ns_link_i_i_i_a2_i_0_3_ ( + .I0(com_llm_llm_common_llm_link_sm_llm_link_main_sm_N_60893), + .I1(plm_link_l0), + .I2(plm_link_up_2), + .I3(NlwRenamedSig_OI_trn_lnk_up_n), + .LO(com_llm_llm_common_llm_link_sm_llm_link_main_sm_N_46513_i) + ); + defparam com_llm_llm_common_llm_link_sm_llm_link_main_sm_ns_link_i_0_0_0_i_2_.INIT = 16'hB0F0; + LUT4_L com_llm_llm_common_llm_link_sm_llm_link_main_sm_ns_link_i_0_0_0_i_2_ ( + .I0(com_llm_llm_common_llm_link_sm_llm_link_main_sm_N_56977_i), + .I1(com_link_status[2]), + .I2(com_llm_llm_common_llm_link_sm_llm_link_main_sm_ns_link_i_0_0_0_i_1[2]), + .I3(plm_link_l0), + .LO(com_llm_llm_common_llm_link_sm_llm_link_main_sm_N_51954_i) + ); + defparam com_llm_llm_common_llm_link_sm_llm_link_main_sm_ns_link_i_i_0_0_0_1_.INIT = 16'h3100; + LUT4_L com_llm_llm_common_llm_link_sm_llm_link_main_sm_ns_link_i_i_0_0_0_1_ ( + .I0(com_llm_llm_common_llm_link_sm_llm_link_main_sm_N_56934_i), + .I1(com_llm_llm_common_llm_link_sm_llm_link_main_sm_N_58438), + .I2(com_llm_link_status[0]), + .I3(plm_link_up_2), + .LO(com_llm_llm_common_llm_link_sm_llm_link_main_sm_N_16055_i) + ); + defparam com_llm_llm_common_llm_link_sm_llm_link_main_sm_ns_link_i_i_i_a2_i_0_a2_0_3_.INIT = 8'h01; + LUT3 com_llm_llm_common_llm_link_sm_llm_link_main_sm_ns_link_i_i_i_a2_i_0_a2_0_3_ ( + .I0(com_link_status[2]), + .I1(com_link_status[4]), + .I2(com_link_status[3]), + .O(NlwRenamedSig_OI_trn_lnk_up_n) + ); + FDP com_llm_llm_common_llm_link_sm_llm_link_main_sm_link_status_0_ ( + .PRE(plm_link_up_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_common_llm_link_sm_llm_link_main_sm_N_87093_i_2915), + .Q(com_llm_link_status[0]) + ); + FDC com_llm_llm_common_llm_link_sm_llm_link_main_sm_link_status_4_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_common_llm_link_sm_llm_link_main_sm_N_46610_i), + .Q(com_link_status[4]), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_common_llm_link_sm_llm_link_main_sm_link_status_3_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_common_llm_link_sm_llm_link_main_sm_N_46513_i), + .Q(com_link_status[3]), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_common_llm_link_sm_llm_link_main_sm_link_status_2_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_common_llm_link_sm_llm_link_main_sm_N_51954_i), + .Q(com_link_status[2]), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_common_llm_link_sm_llm_link_main_sm_link_status_1_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_common_llm_link_sm_llm_link_main_sm_N_16055_i), + .Q(com_link_status[1]), + .CLR(plm_link_up_i) + ); + INV com_llm_llm_common_llm_link_sm_llm_link_main_sm_link_status_i_0_ ( + .I(com_llm_link_status[0]), + .O(com_llm_llm_common_link_status_i[0]) + ); + FDRE com_llm_llm_common_llm_link_sm_llm_link_main_sm_sticky0_q ( + .CE(com_llm_llm_common_llm_link_sm_llm_link_main_sm_sticky0_q5_i_2916), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_common_llm_link_sm_llm_link_main_sm_sticky0_qc_2917), + .Q(com_llm_llm_common_llm_link_sm_llm_link_main_sm_link_fcp_rcvq), + .R(com_llm_link_status[0]) + ); + defparam com_llm_llm_common_llm_link_sm_llm_link_main_sm_sticky0_q5_i.INIT = 4'hB; + LUT2 com_llm_llm_common_llm_link_sm_llm_link_main_sm_sticky0_q5_i ( + .I0(com_llm_link_status[0]), + .I1(com_llm_llm_common_llm_link_sm_llm_link_main_sm_link_fcp_rcvq), + .O(com_llm_llm_common_llm_link_sm_llm_link_main_sm_sticky0_q5_i_2916) + ); + defparam com_llm_llm_common_llm_link_sm_llm_link_main_sm_sticky0_qc.INIT = 4'h8; + LUT2_L com_llm_llm_common_llm_link_sm_llm_link_main_sm_sticky0_qc ( + .I0(com_llm_link_li1_p_rcv), + .I1(com_llm_link_vc_rcv[0]), + .LO(com_llm_llm_common_llm_link_sm_llm_link_main_sm_sticky0_qc_2917) + ); + FDRE com_llm_llm_common_llm_link_sm_llm_link_main_sm_sticky1_q ( + .CE(com_llm_llm_common_llm_link_sm_llm_link_main_sm_sticky1_q5_i_2918), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_common_llm_link_sm_llm_link_main_sm_sticky1_qc_2919), + .Q(com_llm_llm_common_llm_link_sm_llm_link_main_sm_link_fcnp_rcvq), + .R(com_llm_link_status[0]) + ); + defparam com_llm_llm_common_llm_link_sm_llm_link_main_sm_sticky1_q5_i.INIT = 4'hB; + LUT2 com_llm_llm_common_llm_link_sm_llm_link_main_sm_sticky1_q5_i ( + .I0(com_llm_link_status[0]), + .I1(com_llm_llm_common_llm_link_sm_llm_link_main_sm_link_fcnp_rcvq), + .O(com_llm_llm_common_llm_link_sm_llm_link_main_sm_sticky1_q5_i_2918) + ); + defparam com_llm_llm_common_llm_link_sm_llm_link_main_sm_sticky1_qc.INIT = 4'h8; + LUT2_L com_llm_llm_common_llm_link_sm_llm_link_main_sm_sticky1_qc ( + .I0(com_llm_link_li1_np_rcv), + .I1(com_llm_link_vc_rcv[0]), + .LO(com_llm_llm_common_llm_link_sm_llm_link_main_sm_sticky1_qc_2919) + ); + FDRE com_llm_llm_common_llm_link_sm_llm_link_main_sm_sticky2_q ( + .CE(com_llm_llm_common_llm_link_sm_llm_link_main_sm_sticky2_q5_i_2920), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_common_llm_link_sm_llm_link_main_sm_sticky2_qc_2921), + .Q(com_llm_llm_common_llm_link_sm_llm_link_main_sm_link_fccpl_rcvq), + .R(com_llm_link_status[0]) + ); + defparam com_llm_llm_common_llm_link_sm_llm_link_main_sm_sticky2_q5_i.INIT = 4'hB; + LUT2 com_llm_llm_common_llm_link_sm_llm_link_main_sm_sticky2_q5_i ( + .I0(com_llm_link_status[0]), + .I1(com_llm_llm_common_llm_link_sm_llm_link_main_sm_link_fccpl_rcvq), + .O(com_llm_llm_common_llm_link_sm_llm_link_main_sm_sticky2_q5_i_2920) + ); + defparam com_llm_llm_common_llm_link_sm_llm_link_main_sm_sticky2_qc.INIT = 4'h8; + LUT2_L com_llm_llm_common_llm_link_sm_llm_link_main_sm_sticky2_qc ( + .I0(com_llm_link_li1_cpl_rcv), + .I1(com_llm_link_vc_rcv[0]), + .LO(com_llm_llm_common_llm_link_sm_llm_link_main_sm_sticky2_qc_2921) + ); + VCC com_llm_llm_common_llm_common_reg_VCC ( + .P(com_llm_llm_common_llm_common_reg_VCC_2933) + ); + GND com_llm_llm_common_llm_common_reg_GND ( + .G(com_llm_llm_common_llm_common_reg_GND_2982) + ); + FDS com_llm_llm_common_llm_common_reg_reg_tx_curr_tsn_0_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_common_llm_common_reg_N_60742_i_2981), + .Q(com_llm_llm_common_llm_common_reg_reg_tx_curr_tsn[0]), + .S(plm_link_up_i) + ); + FDS com_llm_llm_common_llm_common_reg_reg_tx_curr_tsn_1_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_common_llm_common_reg_N_60741_i_2980), + .Q(com_llm_llm_common_llm_common_reg_reg_tx_curr_tsn[1]), + .S(plm_link_up_i) + ); + FDS com_llm_llm_common_llm_common_reg_reg_tx_curr_tsn_2_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_common_llm_common_reg_N_60740_i_2979), + .Q(com_llm_llm_common_llm_common_reg_reg_tx_curr_tsn[2]), + .S(plm_link_up_i) + ); + FDS com_llm_llm_common_llm_common_reg_reg_tx_curr_tsn_3_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_common_llm_common_reg_N_60739_i_2978), + .Q(com_llm_llm_common_llm_common_reg_reg_tx_curr_tsn[3]), + .S(plm_link_up_i) + ); + FDS com_llm_llm_common_llm_common_reg_reg_tx_curr_tsn_4_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_common_llm_common_reg_N_60738_i_2977), + .Q(com_llm_llm_common_llm_common_reg_reg_tx_curr_tsn[4]), + .S(plm_link_up_i) + ); + FDS com_llm_llm_common_llm_common_reg_reg_tx_curr_tsn_5_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_common_llm_common_reg_N_60737_i_2976), + .Q(com_llm_llm_common_llm_common_reg_reg_tx_curr_tsn[5]), + .S(plm_link_up_i) + ); + FDS com_llm_llm_common_llm_common_reg_reg_tx_curr_tsn_6_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_common_llm_common_reg_N_60736_i_2975), + .Q(com_llm_llm_common_llm_common_reg_reg_tx_curr_tsn[6]), + .S(plm_link_up_i) + ); + FDS com_llm_llm_common_llm_common_reg_reg_tx_curr_tsn_7_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_common_llm_common_reg_N_60735_i_2974), + .Q(com_llm_llm_common_llm_common_reg_reg_tx_curr_tsn[7]), + .S(plm_link_up_i) + ); + FDS com_llm_llm_common_llm_common_reg_reg_tx_curr_tsn_8_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_common_llm_common_reg_N_60734_i_2973), + .Q(com_llm_llm_common_llm_common_reg_reg_tx_curr_tsn[8]), + .S(plm_link_up_i) + ); + FDS com_llm_llm_common_llm_common_reg_reg_tx_curr_tsn_9_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_common_llm_common_reg_N_60733_i_2972), + .Q(com_llm_llm_common_llm_common_reg_reg_tx_curr_tsn[9]), + .S(plm_link_up_i) + ); + FDS com_llm_llm_common_llm_common_reg_reg_tx_curr_tsn_10_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_common_llm_common_reg_N_60732_i_2971), + .Q(com_llm_llm_common_llm_common_reg_reg_tx_curr_tsn[10]), + .S(plm_link_up_i) + ); + FDS com_llm_llm_common_llm_common_reg_reg_tx_curr_tsn_11_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_common_llm_common_reg_N_60731_i_2970), + .Q(com_llm_llm_common_llm_common_reg_reg_tx_curr_tsn[11]), + .S(plm_link_up_i) + ); + MUXCY_L com_llm_llm_common_llm_common_reg_rx_tsn_eq_sent_tsn_3_0_I_1 ( + .CI(com_llm_llm_common_llm_common_reg_VCC_2933), + .DI(com_llm_llm_common_llm_common_reg_GND_2982), + .LO(com_llm_llm_common_llm_common_reg_data_tmp_2[0]), + .S(com_llm_llm_common_llm_common_reg_N_43) + ); + MUXCY_L com_llm_llm_common_llm_common_reg_rx_tsn_eq_sent_tsn_3_0_I_10 ( + .CI(com_llm_llm_common_llm_common_reg_data_tmp_2[1]), + .DI(com_llm_llm_common_llm_common_reg_GND_2982), + .LO(com_llm_llm_common_llm_common_reg_data_tmp_2[2]), + .S(com_llm_llm_common_llm_common_reg_N_35) + ); + MUXCY_L com_llm_llm_common_llm_common_reg_rx_tsn_eq_sent_tsn_3_0_I_28 ( + .CI(com_llm_llm_common_llm_common_reg_data_tmp_2[2]), + .DI(com_llm_llm_common_llm_common_reg_GND_2982), + .LO(com_llm_llm_common_llm_common_reg_data_tmp_2[3]), + .S(com_llm_llm_common_llm_common_reg_N_19) + ); + MUXCY_L com_llm_llm_common_llm_common_reg_rx_tsn_eq_sent_tsn_3_0_I_37 ( + .CI(com_llm_llm_common_llm_common_reg_data_tmp_2[3]), + .DI(com_llm_llm_common_llm_common_reg_GND_2982), + .LO(com_llm_llm_common_llm_common_reg_data_tmp[4]), + .S(com_llm_llm_common_llm_common_reg_N_11) + ); + MUXCY_L com_llm_llm_common_llm_common_reg_rx_tsn_eq_sent_tsn_3_0_I_46 ( + .CI(com_llm_llm_common_llm_common_reg_data_tmp_2[0]), + .DI(com_llm_llm_common_llm_common_reg_GND_2982), + .LO(com_llm_llm_common_llm_common_reg_data_tmp_2[1]), + .S(com_llm_llm_common_llm_common_reg_N_3) + ); + MUXCY_L com_llm_llm_common_llm_common_reg_next_eq_mark_q_3_0_I_1 ( + .CI(com_llm_llm_common_llm_common_reg_VCC_2933), + .DI(com_llm_llm_common_llm_common_reg_GND_2982), + .LO(com_llm_llm_common_llm_common_reg_data_tmp_1[0]), + .S(com_llm_llm_common_llm_common_reg_N_43_0) + ); + MUXCY_L com_llm_llm_common_llm_common_reg_next_eq_mark_q_3_0_I_10 ( + .CI(com_llm_llm_common_llm_common_reg_data_tmp_1[1]), + .DI(com_llm_llm_common_llm_common_reg_GND_2982), + .LO(com_llm_llm_common_llm_common_reg_data_tmp_1[2]), + .S(com_llm_llm_common_llm_common_reg_N_35_0) + ); + MUXCY_L com_llm_llm_common_llm_common_reg_next_eq_mark_q_3_0_I_28 ( + .CI(com_llm_llm_common_llm_common_reg_data_tmp_1[2]), + .DI(com_llm_llm_common_llm_common_reg_GND_2982), + .LO(com_llm_llm_common_llm_common_reg_data_tmp_1[3]), + .S(com_llm_llm_common_llm_common_reg_N_19_0) + ); + MUXCY_L com_llm_llm_common_llm_common_reg_next_eq_mark_q_3_0_I_37 ( + .CI(com_llm_llm_common_llm_common_reg_data_tmp_1[3]), + .DI(com_llm_llm_common_llm_common_reg_GND_2982), + .LO(com_llm_llm_common_llm_common_reg_data_tmp_0[4]), + .S(com_llm_llm_common_llm_common_reg_N_11_0) + ); + MUXCY_L com_llm_llm_common_llm_common_reg_next_eq_mark_q_3_0_I_46 ( + .CI(com_llm_llm_common_llm_common_reg_data_tmp_1[0]), + .DI(com_llm_llm_common_llm_common_reg_GND_2982), + .LO(com_llm_llm_common_llm_common_reg_data_tmp_1[1]), + .S(com_llm_llm_common_llm_common_reg_N_3_0) + ); + MUXCY_L com_llm_llm_common_llm_common_reg_curr_eq_mark_q_3_0_I_1 ( + .CI(com_llm_llm_common_llm_common_reg_VCC_2933), + .DI(com_llm_llm_common_llm_common_reg_GND_2982), + .LO(com_llm_llm_common_llm_common_reg_data_tmp_0[0]), + .S(com_llm_llm_common_llm_common_reg_N_43_1) + ); + MUXCY_L com_llm_llm_common_llm_common_reg_curr_eq_mark_q_3_0_I_10 ( + .CI(com_llm_llm_common_llm_common_reg_data_tmp_0[1]), + .DI(com_llm_llm_common_llm_common_reg_GND_2982), + .LO(com_llm_llm_common_llm_common_reg_data_tmp_0[2]), + .S(com_llm_llm_common_llm_common_reg_N_35_1) + ); + MUXCY_L com_llm_llm_common_llm_common_reg_curr_eq_mark_q_3_0_I_28 ( + .CI(com_llm_llm_common_llm_common_reg_data_tmp_0[2]), + .DI(com_llm_llm_common_llm_common_reg_GND_2982), + .LO(com_llm_llm_common_llm_common_reg_data_tmp_0[3]), + .S(com_llm_llm_common_llm_common_reg_N_19_1) + ); + MUXCY_L com_llm_llm_common_llm_common_reg_curr_eq_mark_q_3_0_I_37 ( + .CI(com_llm_llm_common_llm_common_reg_data_tmp_0[3]), + .DI(com_llm_llm_common_llm_common_reg_GND_2982), + .LO(com_llm_llm_common_llm_common_reg_data_tmp_1[4]), + .S(com_llm_llm_common_llm_common_reg_N_11_1) + ); + MUXCY_L com_llm_llm_common_llm_common_reg_curr_eq_mark_q_3_0_I_46 ( + .CI(com_llm_llm_common_llm_common_reg_data_tmp_0[0]), + .DI(com_llm_llm_common_llm_common_reg_GND_2982), + .LO(com_llm_llm_common_llm_common_reg_data_tmp_0[1]), + .S(com_llm_llm_common_llm_common_reg_N_3_1) + ); + MUXCY_L com_llm_llm_common_llm_common_reg_ANSeqNum_Eq_AckdSeq_wire_0_I_1 ( + .CI(com_llm_llm_common_llm_common_reg_VCC_2933), + .DI(com_llm_llm_common_llm_common_reg_GND_2982), + .LO(com_llm_llm_common_llm_common_reg_data_tmp[0]), + .S(com_llm_llm_common_llm_common_reg_N_43_2) + ); + MUXCY_L com_llm_llm_common_llm_common_reg_ANSeqNum_Eq_AckdSeq_wire_0_I_10 ( + .CI(com_llm_llm_common_llm_common_reg_data_tmp[1]), + .DI(com_llm_llm_common_llm_common_reg_GND_2982), + .LO(com_llm_llm_common_llm_common_reg_data_tmp[2]), + .S(com_llm_llm_common_llm_common_reg_N_35_2) + ); + MUXCY_L com_llm_llm_common_llm_common_reg_ANSeqNum_Eq_AckdSeq_wire_0_I_28 ( + .CI(com_llm_llm_common_llm_common_reg_data_tmp[2]), + .DI(com_llm_llm_common_llm_common_reg_GND_2982), + .LO(com_llm_llm_common_llm_common_reg_data_tmp[3]), + .S(com_llm_llm_common_llm_common_reg_N_19_2) + ); + MUXCY_L com_llm_llm_common_llm_common_reg_ANSeqNum_Eq_AckdSeq_wire_0_I_37 ( + .CI(com_llm_llm_common_llm_common_reg_data_tmp[3]), + .DI(com_llm_llm_common_llm_common_reg_GND_2982), + .LO(com_llm_llm_common_llm_common_reg_data_tmp_2[4]), + .S(com_llm_llm_common_llm_common_reg_N_11_2) + ); + MUXCY_L com_llm_llm_common_llm_common_reg_ANSeqNum_Eq_AckdSeq_wire_0_I_46 ( + .CI(com_llm_llm_common_llm_common_reg_data_tmp[0]), + .DI(com_llm_llm_common_llm_common_reg_GND_2982), + .LO(com_llm_llm_common_llm_common_reg_data_tmp[1]), + .S(com_llm_llm_common_llm_common_reg_N_3_2) + ); + MUXCY_L com_llm_llm_common_llm_common_reg_un3_ttrans_st_hiwater_cry_0 ( + .CI(com_llm_llm_common_llm_common_reg_VCC_2933), + .DI(com_lnk_ttrans_seq[0]), + .LO(com_llm_llm_common_llm_common_reg_un3_ttrans_st_hiwater_cry_0_2922), + .S(com_llm_llm_common_llm_common_reg_un3_ttrans_st_hiwater_axb_0_3061) + ); + MUXCY_L com_llm_llm_common_llm_common_reg_un3_ttrans_st_hiwater_cry_1 ( + .CI(com_llm_llm_common_llm_common_reg_un3_ttrans_st_hiwater_cry_0_2922), + .DI(com_lnk_ttrans_seq[1]), + .LO(com_llm_llm_common_llm_common_reg_un3_ttrans_st_hiwater_cry_1_2923), + .S(com_llm_llm_common_llm_common_reg_un3_ttrans_st_hiwater_axb_1_3060) + ); + MUXCY_L com_llm_llm_common_llm_common_reg_un3_ttrans_st_hiwater_cry_2 ( + .CI(com_llm_llm_common_llm_common_reg_un3_ttrans_st_hiwater_cry_1_2923), + .DI(com_lnk_ttrans_seq[2]), + .LO(com_llm_llm_common_llm_common_reg_un3_ttrans_st_hiwater_cry_2_2924), + .S(com_llm_llm_common_llm_common_reg_un3_ttrans_st_hiwater_axb_2_3059) + ); + MUXCY_L com_llm_llm_common_llm_common_reg_un3_ttrans_st_hiwater_cry_3 ( + .CI(com_llm_llm_common_llm_common_reg_un3_ttrans_st_hiwater_cry_2_2924), + .DI(com_lnk_ttrans_seq[3]), + .LO(com_llm_llm_common_llm_common_reg_un3_ttrans_st_hiwater_cry_3_2925), + .S(com_llm_llm_common_llm_common_reg_un3_ttrans_st_hiwater_axb_3_3058) + ); + MUXCY_L com_llm_llm_common_llm_common_reg_un3_ttrans_st_hiwater_cry_4 ( + .CI(com_llm_llm_common_llm_common_reg_un3_ttrans_st_hiwater_cry_3_2925), + .DI(com_lnk_ttrans_seq[4]), + .LO(com_llm_llm_common_llm_common_reg_un3_ttrans_st_hiwater_cry_4_2926), + .S(com_llm_llm_common_llm_common_reg_un3_ttrans_st_hiwater_axb_4_3057) + ); + MUXCY_L com_llm_llm_common_llm_common_reg_un3_ttrans_st_hiwater_cry_5 ( + .CI(com_llm_llm_common_llm_common_reg_un3_ttrans_st_hiwater_cry_4_2926), + .DI(com_lnk_ttrans_seq[5]), + .LO(com_llm_llm_common_llm_common_reg_un3_ttrans_st_hiwater_cry_5_2927), + .S(com_llm_llm_common_llm_common_reg_un3_ttrans_st_hiwater_axb_5_3056) + ); + MUXCY_L com_llm_llm_common_llm_common_reg_un3_ttrans_st_hiwater_cry_6 ( + .CI(com_llm_llm_common_llm_common_reg_un3_ttrans_st_hiwater_cry_5_2927), + .DI(com_lnk_ttrans_seq[6]), + .LO(com_llm_llm_common_llm_common_reg_un3_ttrans_st_hiwater_cry_6_2928), + .S(com_llm_llm_common_llm_common_reg_un3_ttrans_st_hiwater_axb_6_3055) + ); + MUXCY_L com_llm_llm_common_llm_common_reg_un3_ttrans_st_hiwater_cry_7 ( + .CI(com_llm_llm_common_llm_common_reg_un3_ttrans_st_hiwater_cry_6_2928), + .DI(com_lnk_ttrans_seq[7]), + .LO(com_llm_llm_common_llm_common_reg_un3_ttrans_st_hiwater_cry_7_2929), + .S(com_llm_llm_common_llm_common_reg_un3_ttrans_st_hiwater_axb_7_3054) + ); + MUXCY_L com_llm_llm_common_llm_common_reg_un3_ttrans_st_hiwater_cry_8 ( + .CI(com_llm_llm_common_llm_common_reg_un3_ttrans_st_hiwater_cry_7_2929), + .DI(com_lnk_ttrans_seq[8]), + .LO(com_llm_llm_common_llm_common_reg_un3_ttrans_st_hiwater_cry_8_2930), + .S(com_llm_llm_common_llm_common_reg_un3_ttrans_st_hiwater_axb_8_3053) + ); + MUXCY_L com_llm_llm_common_llm_common_reg_un3_ttrans_st_hiwater_cry_9 ( + .CI(com_llm_llm_common_llm_common_reg_un3_ttrans_st_hiwater_cry_8_2930), + .DI(com_lnk_ttrans_seq[9]), + .LO(com_llm_llm_common_llm_common_reg_un3_ttrans_st_hiwater_cry_9_2931), + .S(com_llm_llm_common_llm_common_reg_un3_ttrans_st_hiwater_axb_9_3052) + ); + MUXCY_L com_llm_llm_common_llm_common_reg_un3_ttrans_st_hiwater_cry_10 ( + .CI(com_llm_llm_common_llm_common_reg_un3_ttrans_st_hiwater_cry_9_2931), + .DI(com_lnk_ttrans_seq[10]), + .LO(com_llm_llm_common_llm_common_reg_un3_ttrans_st_hiwater_cry_10_2932), + .S(com_llm_llm_common_llm_common_reg_un3_ttrans_st_hiwater_axb_10_3051) + ); + XORCY com_llm_llm_common_llm_common_reg_un3_ttrans_st_hiwater_s_11 ( + .CI(com_llm_llm_common_llm_common_reg_un3_ttrans_st_hiwater_cry_10_2932), + .LI(com_llm_llm_common_llm_common_reg_un3_ttrans_st_hiwater_axb_11_2957), + .O(com_llm_llm_common_llm_common_reg_un3_ttrans_st_hiwater_s_11_2992) + ); + MUXCY_L com_llm_llm_common_llm_common_reg_un3_tmp_result_cry_0 ( + .CI(com_llm_llm_common_llm_common_reg_VCC_2933), + .DI(com_lnk_ttrans_seq[0]), + .LO(com_llm_llm_common_llm_common_reg_un3_tmp_result_cry_0_2934), + .S(com_llm_llm_common_llm_common_reg_un3_tmp_result_axb_0_3050) + ); + MUXCY_L com_llm_llm_common_llm_common_reg_un3_tmp_result_cry_1 ( + .CI(com_llm_llm_common_llm_common_reg_un3_tmp_result_cry_0_2934), + .DI(com_lnk_ttrans_seq[1]), + .LO(com_llm_llm_common_llm_common_reg_un3_tmp_result_cry_1_2935), + .S(com_llm_llm_common_llm_common_reg_un3_tmp_result_axb_1_3049) + ); + MUXCY_L com_llm_llm_common_llm_common_reg_un3_tmp_result_cry_2 ( + .CI(com_llm_llm_common_llm_common_reg_un3_tmp_result_cry_1_2935), + .DI(com_lnk_ttrans_seq[2]), + .LO(com_llm_llm_common_llm_common_reg_un3_tmp_result_cry_2_2936), + .S(com_llm_llm_common_llm_common_reg_un3_tmp_result_axb_2_3048) + ); + MUXCY_L com_llm_llm_common_llm_common_reg_un3_tmp_result_cry_3 ( + .CI(com_llm_llm_common_llm_common_reg_un3_tmp_result_cry_2_2936), + .DI(com_lnk_ttrans_seq[3]), + .LO(com_llm_llm_common_llm_common_reg_un3_tmp_result_cry_3_2937), + .S(com_llm_llm_common_llm_common_reg_un3_tmp_result_axb_3_3047) + ); + MUXCY_L com_llm_llm_common_llm_common_reg_un3_tmp_result_cry_4 ( + .CI(com_llm_llm_common_llm_common_reg_un3_tmp_result_cry_3_2937), + .DI(com_lnk_ttrans_seq[4]), + .LO(com_llm_llm_common_llm_common_reg_un3_tmp_result_cry_4_2938), + .S(com_llm_llm_common_llm_common_reg_un3_tmp_result_axb_4_3046) + ); + MUXCY_L com_llm_llm_common_llm_common_reg_un3_tmp_result_cry_5 ( + .CI(com_llm_llm_common_llm_common_reg_un3_tmp_result_cry_4_2938), + .DI(com_lnk_ttrans_seq[5]), + .LO(com_llm_llm_common_llm_common_reg_un3_tmp_result_cry_5_2939), + .S(com_llm_llm_common_llm_common_reg_un3_tmp_result_axb_5_3045) + ); + MUXCY_L com_llm_llm_common_llm_common_reg_un3_tmp_result_cry_6 ( + .CI(com_llm_llm_common_llm_common_reg_un3_tmp_result_cry_5_2939), + .DI(com_lnk_ttrans_seq[6]), + .LO(com_llm_llm_common_llm_common_reg_un3_tmp_result_cry_6_2940), + .S(com_llm_llm_common_llm_common_reg_un3_tmp_result_axb_6_3044) + ); + MUXCY_L com_llm_llm_common_llm_common_reg_un3_tmp_result_cry_7 ( + .CI(com_llm_llm_common_llm_common_reg_un3_tmp_result_cry_6_2940), + .DI(com_lnk_ttrans_seq[7]), + .LO(com_llm_llm_common_llm_common_reg_un3_tmp_result_cry_7_2941), + .S(com_llm_llm_common_llm_common_reg_un3_tmp_result_axb_7_3043) + ); + MUXCY_L com_llm_llm_common_llm_common_reg_un3_tmp_result_cry_8 ( + .CI(com_llm_llm_common_llm_common_reg_un3_tmp_result_cry_7_2941), + .DI(com_lnk_ttrans_seq[8]), + .LO(com_llm_llm_common_llm_common_reg_un3_tmp_result_cry_8_2942), + .S(com_llm_llm_common_llm_common_reg_un3_tmp_result_axb_8_3042) + ); + MUXCY_L com_llm_llm_common_llm_common_reg_un3_tmp_result_cry_9 ( + .CI(com_llm_llm_common_llm_common_reg_un3_tmp_result_cry_8_2942), + .DI(com_lnk_ttrans_seq[9]), + .LO(com_llm_llm_common_llm_common_reg_un3_tmp_result_cry_9_2943), + .S(com_llm_llm_common_llm_common_reg_un3_tmp_result_axb_9_3041) + ); + MUXCY_L com_llm_llm_common_llm_common_reg_un3_tmp_result_cry_10 ( + .CI(com_llm_llm_common_llm_common_reg_un3_tmp_result_cry_9_2943), + .DI(com_lnk_ttrans_seq[10]), + .LO(com_llm_llm_common_llm_common_reg_un3_tmp_result_cry_10_2944), + .S(com_llm_llm_common_llm_common_reg_un3_tmp_result_axb_10_3040) + ); + XORCY com_llm_llm_common_llm_common_reg_un3_tmp_result_s_11 ( + .CI(com_llm_llm_common_llm_common_reg_un3_tmp_result_cry_10_2944), + .LI(com_llm_llm_common_llm_common_reg_un3_tmp_result_axb_11_2958), + .O(com_llm_llm_common_llm_common_reg_un3_tmp_result_s_11_2993) + ); + MUXCY_L com_llm_llm_common_llm_common_reg_reg_tx_next_tsn_4_cry_0 ( + .CI(plm_link_up_1), + .DI(com_llm_llm_common_llm_common_reg_GND_2982), + .LO(com_llm_llm_common_llm_common_reg_reg_tx_next_tsn_4_cry_0_2945), + .S(com_llm_llm_common_llm_common_reg_reg_tx_next_tsn_4_axb_0_3039) + ); + MUXCY_L com_llm_llm_common_llm_common_reg_reg_tx_next_tsn_4_cry_1 ( + .CI(com_llm_llm_common_llm_common_reg_reg_tx_next_tsn_4_cry_0_2945), + .DI(com_llm_llm_common_llm_common_reg_GND_2982), + .LO(com_llm_llm_common_llm_common_reg_reg_tx_next_tsn_4_cry_1_2946), + .S(com_llm_llm_common_llm_common_reg_reg_tx_next_tsn_4_axb_1_2969) + ); + XORCY com_llm_llm_common_llm_common_reg_reg_tx_next_tsn_4_s_1 ( + .CI(com_llm_llm_common_llm_common_reg_reg_tx_next_tsn_4_cry_0_2945), + .LI(com_llm_llm_common_llm_common_reg_reg_tx_next_tsn_4_axb_1_2969), + .O(com_llm_llm_common_llm_common_reg_reg_tx_next_tsn_4[1]) + ); + MUXCY_L com_llm_llm_common_llm_common_reg_reg_tx_next_tsn_4_cry_2 ( + .CI(com_llm_llm_common_llm_common_reg_reg_tx_next_tsn_4_cry_1_2946), + .DI(com_llm_llm_common_llm_common_reg_GND_2982), + .LO(com_llm_llm_common_llm_common_reg_reg_tx_next_tsn_4_cry_2_2947), + .S(com_llm_llm_common_llm_common_reg_reg_tx_next_tsn_4_axb_2_2968) + ); + XORCY com_llm_llm_common_llm_common_reg_reg_tx_next_tsn_4_s_2 ( + .CI(com_llm_llm_common_llm_common_reg_reg_tx_next_tsn_4_cry_1_2946), + .LI(com_llm_llm_common_llm_common_reg_reg_tx_next_tsn_4_axb_2_2968), + .O(com_llm_llm_common_llm_common_reg_reg_tx_next_tsn_4[2]) + ); + MUXCY_L com_llm_llm_common_llm_common_reg_reg_tx_next_tsn_4_cry_3 ( + .CI(com_llm_llm_common_llm_common_reg_reg_tx_next_tsn_4_cry_2_2947), + .DI(com_llm_llm_common_llm_common_reg_GND_2982), + .LO(com_llm_llm_common_llm_common_reg_reg_tx_next_tsn_4_cry_3_2948), + .S(com_llm_llm_common_llm_common_reg_reg_tx_next_tsn_4_axb_3_2967) + ); + XORCY com_llm_llm_common_llm_common_reg_reg_tx_next_tsn_4_s_3 ( + .CI(com_llm_llm_common_llm_common_reg_reg_tx_next_tsn_4_cry_2_2947), + .LI(com_llm_llm_common_llm_common_reg_reg_tx_next_tsn_4_axb_3_2967), + .O(com_llm_llm_common_llm_common_reg_reg_tx_next_tsn_4[3]) + ); + MUXCY_L com_llm_llm_common_llm_common_reg_reg_tx_next_tsn_4_cry_4 ( + .CI(com_llm_llm_common_llm_common_reg_reg_tx_next_tsn_4_cry_3_2948), + .DI(com_llm_llm_common_llm_common_reg_GND_2982), + .LO(com_llm_llm_common_llm_common_reg_reg_tx_next_tsn_4_cry_4_2949), + .S(com_llm_llm_common_llm_common_reg_reg_tx_next_tsn_4_axb_4_2966) + ); + XORCY com_llm_llm_common_llm_common_reg_reg_tx_next_tsn_4_s_4 ( + .CI(com_llm_llm_common_llm_common_reg_reg_tx_next_tsn_4_cry_3_2948), + .LI(com_llm_llm_common_llm_common_reg_reg_tx_next_tsn_4_axb_4_2966), + .O(com_llm_llm_common_llm_common_reg_reg_tx_next_tsn_4[4]) + ); + MUXCY_L com_llm_llm_common_llm_common_reg_reg_tx_next_tsn_4_cry_5 ( + .CI(com_llm_llm_common_llm_common_reg_reg_tx_next_tsn_4_cry_4_2949), + .DI(com_llm_llm_common_llm_common_reg_GND_2982), + .LO(com_llm_llm_common_llm_common_reg_reg_tx_next_tsn_4_cry_5_2950), + .S(com_llm_llm_common_llm_common_reg_reg_tx_next_tsn_4_axb_5_2965) + ); + XORCY com_llm_llm_common_llm_common_reg_reg_tx_next_tsn_4_s_5 ( + .CI(com_llm_llm_common_llm_common_reg_reg_tx_next_tsn_4_cry_4_2949), + .LI(com_llm_llm_common_llm_common_reg_reg_tx_next_tsn_4_axb_5_2965), + .O(com_llm_llm_common_llm_common_reg_reg_tx_next_tsn_4[5]) + ); + MUXCY_L com_llm_llm_common_llm_common_reg_reg_tx_next_tsn_4_cry_6 ( + .CI(com_llm_llm_common_llm_common_reg_reg_tx_next_tsn_4_cry_5_2950), + .DI(com_llm_llm_common_llm_common_reg_GND_2982), + .LO(com_llm_llm_common_llm_common_reg_reg_tx_next_tsn_4_cry_6_2951), + .S(com_llm_llm_common_llm_common_reg_reg_tx_next_tsn_4_axb_6_2964) + ); + XORCY com_llm_llm_common_llm_common_reg_reg_tx_next_tsn_4_s_6 ( + .CI(com_llm_llm_common_llm_common_reg_reg_tx_next_tsn_4_cry_5_2950), + .LI(com_llm_llm_common_llm_common_reg_reg_tx_next_tsn_4_axb_6_2964), + .O(com_llm_llm_common_llm_common_reg_reg_tx_next_tsn_4[6]) + ); + MUXCY_L com_llm_llm_common_llm_common_reg_reg_tx_next_tsn_4_cry_7 ( + .CI(com_llm_llm_common_llm_common_reg_reg_tx_next_tsn_4_cry_6_2951), + .DI(com_llm_llm_common_llm_common_reg_GND_2982), + .LO(com_llm_llm_common_llm_common_reg_reg_tx_next_tsn_4_cry_7_2952), + .S(com_llm_llm_common_llm_common_reg_reg_tx_next_tsn_4_axb_7_2963) + ); + XORCY com_llm_llm_common_llm_common_reg_reg_tx_next_tsn_4_s_7 ( + .CI(com_llm_llm_common_llm_common_reg_reg_tx_next_tsn_4_cry_6_2951), + .LI(com_llm_llm_common_llm_common_reg_reg_tx_next_tsn_4_axb_7_2963), + .O(com_llm_llm_common_llm_common_reg_reg_tx_next_tsn_4[7]) + ); + MUXCY_L com_llm_llm_common_llm_common_reg_reg_tx_next_tsn_4_cry_8 ( + .CI(com_llm_llm_common_llm_common_reg_reg_tx_next_tsn_4_cry_7_2952), + .DI(com_llm_llm_common_llm_common_reg_GND_2982), + .LO(com_llm_llm_common_llm_common_reg_reg_tx_next_tsn_4_cry_8_2953), + .S(com_llm_llm_common_llm_common_reg_reg_tx_next_tsn_4_axb_8_2962) + ); + XORCY com_llm_llm_common_llm_common_reg_reg_tx_next_tsn_4_s_8 ( + .CI(com_llm_llm_common_llm_common_reg_reg_tx_next_tsn_4_cry_7_2952), + .LI(com_llm_llm_common_llm_common_reg_reg_tx_next_tsn_4_axb_8_2962), + .O(com_llm_llm_common_llm_common_reg_reg_tx_next_tsn_4[8]) + ); + MUXCY_L com_llm_llm_common_llm_common_reg_reg_tx_next_tsn_4_cry_9 ( + .CI(com_llm_llm_common_llm_common_reg_reg_tx_next_tsn_4_cry_8_2953), + .DI(com_llm_llm_common_llm_common_reg_GND_2982), + .LO(com_llm_llm_common_llm_common_reg_reg_tx_next_tsn_4_cry_9_2954), + .S(com_llm_llm_common_llm_common_reg_reg_tx_next_tsn_4_axb_9_2961) + ); + XORCY com_llm_llm_common_llm_common_reg_reg_tx_next_tsn_4_s_9 ( + .CI(com_llm_llm_common_llm_common_reg_reg_tx_next_tsn_4_cry_8_2953), + .LI(com_llm_llm_common_llm_common_reg_reg_tx_next_tsn_4_axb_9_2961), + .O(com_llm_llm_common_llm_common_reg_reg_tx_next_tsn_4[9]) + ); + MUXCY_L com_llm_llm_common_llm_common_reg_reg_tx_next_tsn_4_cry_10 ( + .CI(com_llm_llm_common_llm_common_reg_reg_tx_next_tsn_4_cry_9_2954), + .DI(com_llm_llm_common_llm_common_reg_GND_2982), + .LO(com_llm_llm_common_llm_common_reg_reg_tx_next_tsn_4_cry_10_2955), + .S(com_llm_llm_common_llm_common_reg_reg_tx_next_tsn_4_axb_10_2960) + ); + XORCY com_llm_llm_common_llm_common_reg_reg_tx_next_tsn_4_s_10 ( + .CI(com_llm_llm_common_llm_common_reg_reg_tx_next_tsn_4_cry_9_2954), + .LI(com_llm_llm_common_llm_common_reg_reg_tx_next_tsn_4_axb_10_2960), + .O(com_llm_llm_common_llm_common_reg_reg_tx_next_tsn_4[10]) + ); + XORCY com_llm_llm_common_llm_common_reg_reg_tx_next_tsn_4_s_11 ( + .CI(com_llm_llm_common_llm_common_reg_reg_tx_next_tsn_4_cry_10_2955), + .LI(com_llm_llm_common_llm_common_reg_reg_tx_next_tsn_4_axb_11_2959), + .O(com_llm_llm_common_llm_common_reg_reg_tx_next_tsn_4[11]) + ); + FDR com_llm_llm_common_llm_common_reg_reg_tx_next_tsn_0_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_lnk_ttrans_seq_i[0]), + .Q(com_llm_llm_common_llm_common_reg_reg_tx_next_tsn[0]), + .R(plm_link_up_i) + ); + defparam com_llm_llm_common_llm_common_reg_un1_curr_eq_mark_q_i_0_0_a2.INIT = 4'h8; + LUT2 com_llm_llm_common_llm_common_reg_un1_curr_eq_mark_q_i_0_0_a2 ( + .I0(com_llm_llm_common_llm_common_reg_reg_tx_update_clr_q_2983), + .I1(com_reg_tx_update_retry_q), + .O(com_llm_llm_common_llm_common_reg_N_58796) + ); + defparam com_llm_llm_common_llm_common_reg_lnk_sys_reset_n_0_a2_0_a2_0_a2_0_a2.INIT = 4'h2; + LUT2 com_llm_llm_common_llm_common_reg_lnk_sys_reset_n_0_a2_0_a2_0_a2_0_a2 ( + .I0(com_llm_link_status[0]), + .I1(plm_link_up_1), + .O(com_llm_llm_common_llm_common_reg_lnk_sys_reset_n_0_a2_0_a2_0_a2_0_a2_2956) + ); + defparam com_llm_llm_common_llm_common_reg_NxtTxTSN_ANSeqNum_i_0_0.INIT = 4'h4; + LUT2 com_llm_llm_common_llm_common_reg_NxtTxTSN_ANSeqNum_i_0_0 ( + .I0(com_llm_llm_common_llm_common_reg_N_56212_i), + .I1(com_llm_llm_common_llm_common_reg_NxtTxTSN_ANSeqNum_wire_2986), + .O(com_llm_llm_common_llm_common_reg_N_22173_i) + ); + defparam com_llm_llm_common_llm_common_reg_ANSeqNum_Eq_AckdSeq_5_0_a2_0_a2_0_a3_0_a2_1_0_0.INIT = 16'h0100; + LUT4 com_llm_llm_common_llm_common_reg_ANSeqNum_Eq_AckdSeq_5_0_a2_0_a2_0_a3_0_a2_1_0_0 ( + .I0(com_llm_rx_dllp[29]), + .I1(com_llm_rx_dllp[30]), + .I2(com_llm_rx_dllp[31]), + .I3(com_llm_rx_dllp_vld), + .O(com_llm_ANSeqNum_Eq_AckdSeq_5_0_a2_0_a2_0_a3_0_a2_1_0_0) + ); + defparam com_llm_llm_common_llm_common_reg_N_87603_i.INIT = 16'hAAAB; + LUT4 com_llm_llm_common_llm_common_reg_N_87603_i ( + .I0(com_llm_link_status[0]), + .I1(com_llm_llm_common_llm_common_reg_replay_ip_3011), + .I2(com_llm_llm_common_llm_common_reg_ttrans_st_hiwater[11]), + .I3(com_lnk_tretry), + .O(com_llm_llm_common_llm_common_reg_N_87603_i_3023) + ); + defparam com_llm_llm_common_llm_common_reg_N_85479_i.INIT = 16'hFFFE; + LUT4 com_llm_llm_common_llm_common_reg_N_85479_i ( + .I0(com_llm_llm_common_llm_common_reg_N_58796), + .I1(com_llm_link_status[0]), + .I2(com_llm_llm_common_llm_common_reg_curr_eq_mark_q_2990), + .I3(com_llm_llm_common_llm_common_reg_next_eq_mark_q_2989), + .O(com_llm_llm_common_llm_common_reg_N_85479_i_3010) + ); + defparam com_llm_llm_common_llm_common_reg_N_87604_i.INIT = 16'hF0F4; + LUT4 com_llm_llm_common_llm_common_reg_N_87604_i ( + .I0(com_llm_llm_common_llm_common_reg_N_56212_i), + .I1(com_llm_llm_common_llm_common_reg_N_58798_1), + .I2(com_llm_link_status[0]), + .I3(com_llm_llm_common_llm_common_reg_tmp_result[11]), + .O(com_llm_llm_common_llm_common_reg_N_87604_i_3036) + ); + defparam com_llm_llm_common_llm_common_reg_un1_reg_tx_dllp_ack_clr_i_0_0_i_o3_1.INIT = 8'h70; + LUT3 com_llm_llm_common_llm_common_reg_un1_reg_tx_dllp_ack_clr_i_0_0_i_o3_1 ( + .I0(com_llm_llm_common_llm_common_reg_N_58446_2), + .I1(com_llm_N_62468), + .I2(com_llm_reg_rx_tlp_tsn_err_0_a2_0_a2_0_a2_0_a2), + .O(com_llm_llm_common_llm_common_reg_N_62715_1_i) + ); + defparam com_llm_llm_common_llm_common_reg_N_87517_i.INIT = 8'hB3; + LUT3 com_llm_llm_common_llm_common_reg_N_87517_i ( + .I0(com_llm_N_56478_i), + .I1(com_llm_reg_rx_tlp_tsn_err_0_a2_0_a2_0_a2_0_a2), + .I2(com_llm_reg_tx_dllp_nak_vld), + .O(com_llm_llm_common_llm_common_reg_N_87517_i_2995) + ); + defparam com_llm_llm_common_llm_common_reg_un1_reg_tx_dllp_ack_clr_i_0_0_i_o3.INIT = 16'h0C04; + LUT4 com_llm_llm_common_llm_common_reg_un1_reg_tx_dllp_ack_clr_i_0_0_i_o3 ( + .I0(com_llm_N_56478_i), + .I1(com_llm_llm_common_llm_common_reg_N_62715_1_i), + .I2(com_llm_reg_rx_tlp_tsn_dup), + .I3(com_llm_reg_tx_dllp_nak_vld), + .O(com_llm_llm_common_llm_common_reg_N_62715_i) + ); + defparam com_llm_llm_common_llm_common_reg_N_87591_i.INIT = 4'hD; + LUT2 com_llm_llm_common_llm_common_reg_N_87591_i ( + .I0(com_llm_llm_common_llm_common_reg_N_62715_1_i), + .I1(com_llm_link_status[0]), + .O(com_llm_llm_common_llm_common_reg_N_87591_i_2996) + ); + defparam com_llm_llm_common_llm_common_reg_N_58434_i.INIT = 4'hD; + LUT2 com_llm_llm_common_llm_common_reg_N_58434_i ( + .I0(com_llm_llm_common_llm_common_reg_N_62715_i), + .I1(com_llm_reg_dllr_in_progress), + .O(com_llm_llm_common_llm_common_reg_N_58434_i_3009) + ); + defparam com_llm_llm_common_llm_common_reg_ANSeqNum_AckdSeq_i_0_0.INIT = 4'h4; + LUT2_L com_llm_llm_common_llm_common_reg_ANSeqNum_AckdSeq_i_0_0 ( + .I0(com_llm_llm_common_llm_common_reg_N_56212_i), + .I1(com_llm_llm_common_llm_common_reg_ANSeqNum_AckdSeq_wire_2987), + .LO(com_llm_llm_common_llm_common_reg_N_22175_i) + ); + defparam com_llm_llm_common_llm_common_reg_ANSeqNum_Eq_AckdSeq_5_0_a2_0_a2_0_a3_0_a2.INIT = 8'h80; + LUT3_L com_llm_llm_common_llm_common_reg_ANSeqNum_Eq_AckdSeq_5_0_a2_0_a2_0_a3_0_a2 ( + .I0(com_llm_N_56326_i), + .I1(com_llm_ANSeqNum_Eq_AckdSeq_5_0_a2_0_a2_0_a3_0_a2_1_0_0), + .I2(com_llm_llm_common_llm_common_reg_ANSeqNum_Eq_AckdSeq_wire), + .LO(com_llm_llm_common_llm_common_reg_ANSeqNum_Eq_AckdSeq_5) + ); + defparam com_llm_llm_common_llm_common_reg_un3_ttrans_st_hiwater_axb_11.INIT = 4'h9; + LUT2_L com_llm_llm_common_llm_common_reg_un3_ttrans_st_hiwater_axb_11 ( + .I0(com_llm_llm_common_llm_common_reg_hi_water_mark[11]), + .I1(com_lnk_ttrans_seq[11]), + .LO(com_llm_llm_common_llm_common_reg_un3_ttrans_st_hiwater_axb_11_2957) + ); + defparam com_llm_llm_common_llm_common_reg_un3_tmp_result_axb_11.INIT = 4'h9; + LUT2_L com_llm_llm_common_llm_common_reg_un3_tmp_result_axb_11 ( + .I0(com_llm_reg_rx_dllp_tsn_m1[11]), + .I1(com_lnk_ttrans_seq[11]), + .LO(com_llm_llm_common_llm_common_reg_un3_tmp_result_axb_11_2958) + ); + defparam com_llm_llm_common_llm_common_reg_N_85483_i.INIT = 16'hFEEE; + LUT4_L com_llm_llm_common_llm_common_reg_N_85483_i ( + .I0(com_llm_llm_common_llm_common_reg_N_56212_i), + .I1(com_llm_link_status[0]), + .I2(com_llm_llm_common_llm_common_reg_ANSeqNum_AckdSeq_wire_2987), + .I3(com_llm_llm_common_llm_common_reg_NxtTxTSN_ANSeqNum_wire_2986), + .LO(com_llm_llm_common_llm_common_reg_N_85483_i_2994) + ); + defparam com_llm_llm_common_llm_common_reg_reg_tx_next_tsn_4_axb_11.INIT = 4'h8; + LUT2_L com_llm_llm_common_llm_common_reg_reg_tx_next_tsn_4_axb_11 ( + .I0(com_lnk_ttrans_seq[11]), + .I1(plm_link_up_2), + .LO(com_llm_llm_common_llm_common_reg_reg_tx_next_tsn_4_axb_11_2959) + ); + defparam com_llm_llm_common_llm_common_reg_reg_tx_next_tsn_4_axb_10.INIT = 4'h8; + LUT2_L com_llm_llm_common_llm_common_reg_reg_tx_next_tsn_4_axb_10 ( + .I0(com_lnk_ttrans_seq[10]), + .I1(plm_link_up_2), + .LO(com_llm_llm_common_llm_common_reg_reg_tx_next_tsn_4_axb_10_2960) + ); + defparam com_llm_llm_common_llm_common_reg_reg_tx_next_tsn_4_axb_9.INIT = 4'h8; + LUT2_L com_llm_llm_common_llm_common_reg_reg_tx_next_tsn_4_axb_9 ( + .I0(com_lnk_ttrans_seq[9]), + .I1(plm_link_up_2), + .LO(com_llm_llm_common_llm_common_reg_reg_tx_next_tsn_4_axb_9_2961) + ); + defparam com_llm_llm_common_llm_common_reg_reg_tx_next_tsn_4_axb_8.INIT = 4'h8; + LUT2_L com_llm_llm_common_llm_common_reg_reg_tx_next_tsn_4_axb_8 ( + .I0(com_lnk_ttrans_seq[8]), + .I1(plm_link_up_2), + .LO(com_llm_llm_common_llm_common_reg_reg_tx_next_tsn_4_axb_8_2962) + ); + defparam com_llm_llm_common_llm_common_reg_reg_tx_next_tsn_4_axb_7.INIT = 4'h8; + LUT2_L com_llm_llm_common_llm_common_reg_reg_tx_next_tsn_4_axb_7 ( + .I0(com_lnk_ttrans_seq[7]), + .I1(plm_link_up_2), + .LO(com_llm_llm_common_llm_common_reg_reg_tx_next_tsn_4_axb_7_2963) + ); + defparam com_llm_llm_common_llm_common_reg_reg_tx_next_tsn_4_axb_6.INIT = 4'h8; + LUT2_L com_llm_llm_common_llm_common_reg_reg_tx_next_tsn_4_axb_6 ( + .I0(com_lnk_ttrans_seq[6]), + .I1(plm_link_up_2), + .LO(com_llm_llm_common_llm_common_reg_reg_tx_next_tsn_4_axb_6_2964) + ); + defparam com_llm_llm_common_llm_common_reg_reg_tx_next_tsn_4_axb_5.INIT = 4'h8; + LUT2_L com_llm_llm_common_llm_common_reg_reg_tx_next_tsn_4_axb_5 ( + .I0(com_lnk_ttrans_seq[5]), + .I1(plm_link_up_2), + .LO(com_llm_llm_common_llm_common_reg_reg_tx_next_tsn_4_axb_5_2965) + ); + defparam com_llm_llm_common_llm_common_reg_reg_tx_next_tsn_4_axb_4.INIT = 4'h8; + LUT2_L com_llm_llm_common_llm_common_reg_reg_tx_next_tsn_4_axb_4 ( + .I0(com_lnk_ttrans_seq[4]), + .I1(plm_link_up_2), + .LO(com_llm_llm_common_llm_common_reg_reg_tx_next_tsn_4_axb_4_2966) + ); + defparam com_llm_llm_common_llm_common_reg_reg_tx_next_tsn_4_axb_3.INIT = 4'h8; + LUT2_L com_llm_llm_common_llm_common_reg_reg_tx_next_tsn_4_axb_3 ( + .I0(com_lnk_ttrans_seq[3]), + .I1(plm_link_up_2), + .LO(com_llm_llm_common_llm_common_reg_reg_tx_next_tsn_4_axb_3_2967) + ); + defparam com_llm_llm_common_llm_common_reg_reg_tx_next_tsn_4_axb_2.INIT = 4'h8; + LUT2_L com_llm_llm_common_llm_common_reg_reg_tx_next_tsn_4_axb_2 ( + .I0(com_lnk_ttrans_seq[2]), + .I1(plm_link_up_2), + .LO(com_llm_llm_common_llm_common_reg_reg_tx_next_tsn_4_axb_2_2968) + ); + defparam com_llm_llm_common_llm_common_reg_reg_tx_next_tsn_4_axb_1.INIT = 4'h8; + LUT2_L com_llm_llm_common_llm_common_reg_reg_tx_next_tsn_4_axb_1 ( + .I0(com_lnk_ttrans_seq[1]), + .I1(plm_link_up_2), + .LO(com_llm_llm_common_llm_common_reg_reg_tx_next_tsn_4_axb_1_2969) + ); + defparam com_llm_llm_common_llm_common_reg_reg_dllr_in_progress17_0_a2_0_a2_0_a2_0_a2.INIT = 4'h1; + LUT2_L com_llm_llm_common_llm_common_reg_reg_dllr_in_progress17_0_a2_0_a2_0_a2_0_a2 ( + .I0(com_llm_reg_rx_tlp_tsn_err_0_a2_0_a2_0_a2_0_a2), + .I1(com_llm_link_status[0]), + .LO(com_llm_llm_common_llm_common_reg_reg_dllr_in_progress17) + ); + defparam com_llm_llm_common_llm_common_reg_N_60731_i.INIT = 4'hB; + LUT2_L com_llm_llm_common_llm_common_reg_N_60731_i ( + .I0(com_lnk_ttrans_seq[11]), + .I1(plm_link_up_2), + .LO(com_llm_llm_common_llm_common_reg_N_60731_i_2970) + ); + defparam com_llm_llm_common_llm_common_reg_N_60732_i.INIT = 4'hB; + LUT2_L com_llm_llm_common_llm_common_reg_N_60732_i ( + .I0(com_lnk_ttrans_seq[10]), + .I1(plm_link_up_2), + .LO(com_llm_llm_common_llm_common_reg_N_60732_i_2971) + ); + defparam com_llm_llm_common_llm_common_reg_N_60733_i.INIT = 4'hB; + LUT2_L com_llm_llm_common_llm_common_reg_N_60733_i ( + .I0(com_lnk_ttrans_seq[9]), + .I1(plm_link_up_2), + .LO(com_llm_llm_common_llm_common_reg_N_60733_i_2972) + ); + defparam com_llm_llm_common_llm_common_reg_N_60734_i.INIT = 4'hB; + LUT2_L com_llm_llm_common_llm_common_reg_N_60734_i ( + .I0(com_lnk_ttrans_seq[8]), + .I1(plm_link_up_2), + .LO(com_llm_llm_common_llm_common_reg_N_60734_i_2973) + ); + defparam com_llm_llm_common_llm_common_reg_N_60735_i.INIT = 4'hB; + LUT2_L com_llm_llm_common_llm_common_reg_N_60735_i ( + .I0(com_lnk_ttrans_seq[7]), + .I1(plm_link_up_2), + .LO(com_llm_llm_common_llm_common_reg_N_60735_i_2974) + ); + defparam com_llm_llm_common_llm_common_reg_N_60736_i.INIT = 4'hB; + LUT2_L com_llm_llm_common_llm_common_reg_N_60736_i ( + .I0(com_lnk_ttrans_seq[6]), + .I1(plm_link_up_2), + .LO(com_llm_llm_common_llm_common_reg_N_60736_i_2975) + ); + defparam com_llm_llm_common_llm_common_reg_N_60737_i.INIT = 4'hB; + LUT2_L com_llm_llm_common_llm_common_reg_N_60737_i ( + .I0(com_lnk_ttrans_seq[5]), + .I1(plm_link_up_2), + .LO(com_llm_llm_common_llm_common_reg_N_60737_i_2976) + ); + defparam com_llm_llm_common_llm_common_reg_N_60738_i.INIT = 4'hB; + LUT2_L com_llm_llm_common_llm_common_reg_N_60738_i ( + .I0(com_lnk_ttrans_seq[4]), + .I1(plm_link_up_2), + .LO(com_llm_llm_common_llm_common_reg_N_60738_i_2977) + ); + defparam com_llm_llm_common_llm_common_reg_N_60739_i.INIT = 4'hB; + LUT2_L com_llm_llm_common_llm_common_reg_N_60739_i ( + .I0(com_lnk_ttrans_seq[3]), + .I1(plm_link_up_2), + .LO(com_llm_llm_common_llm_common_reg_N_60739_i_2978) + ); + defparam com_llm_llm_common_llm_common_reg_N_60740_i.INIT = 4'hB; + LUT2_L com_llm_llm_common_llm_common_reg_N_60740_i ( + .I0(com_lnk_ttrans_seq[2]), + .I1(plm_link_up_2), + .LO(com_llm_llm_common_llm_common_reg_N_60740_i_2979) + ); + defparam com_llm_llm_common_llm_common_reg_N_60741_i.INIT = 4'hB; + LUT2_L com_llm_llm_common_llm_common_reg_N_60741_i ( + .I0(com_lnk_ttrans_seq[1]), + .I1(plm_link_up_2), + .LO(com_llm_llm_common_llm_common_reg_N_60741_i_2980) + ); + defparam com_llm_llm_common_llm_common_reg_N_60742_i.INIT = 4'hB; + LUT2_L com_llm_llm_common_llm_common_reg_N_60742_i ( + .I0(com_lnk_ttrans_seq[0]), + .I1(plm_link_up_2), + .LO(com_llm_llm_common_llm_common_reg_N_60742_i_2981) + ); + defparam com_llm_llm_common_llm_common_reg_N_60707_i.INIT = 4'hE; + LUT2_L com_llm_llm_common_llm_common_reg_N_60707_i ( + .I0(com_llm_link_status[0]), + .I1(com_llm_reg_next_rcv_tsn[11]), + .LO(com_llm_llm_common_llm_common_reg_N_60707_i_2997) + ); + defparam com_llm_llm_common_llm_common_reg_N_60708_i.INIT = 4'hE; + LUT2_L com_llm_llm_common_llm_common_reg_N_60708_i ( + .I0(com_llm_link_status[0]), + .I1(com_llm_reg_next_rcv_tsn[10]), + .LO(com_llm_llm_common_llm_common_reg_N_60708_i_2998) + ); + defparam com_llm_llm_common_llm_common_reg_N_60709_i.INIT = 4'hE; + LUT2_L com_llm_llm_common_llm_common_reg_N_60709_i ( + .I0(com_llm_link_status[0]), + .I1(com_llm_reg_next_rcv_tsn[9]), + .LO(com_llm_llm_common_llm_common_reg_N_60709_i_2999) + ); + defparam com_llm_llm_common_llm_common_reg_N_60710_i.INIT = 4'hE; + LUT2_L com_llm_llm_common_llm_common_reg_N_60710_i ( + .I0(com_llm_link_status[0]), + .I1(com_llm_reg_next_rcv_tsn[8]), + .LO(com_llm_llm_common_llm_common_reg_N_60710_i_3000) + ); + defparam com_llm_llm_common_llm_common_reg_N_60711_i.INIT = 4'hE; + LUT2_L com_llm_llm_common_llm_common_reg_N_60711_i ( + .I0(com_llm_link_status[0]), + .I1(com_llm_reg_next_rcv_tsn[7]), + .LO(com_llm_llm_common_llm_common_reg_N_60711_i_3001) + ); + defparam com_llm_llm_common_llm_common_reg_N_60712_i.INIT = 4'hE; + LUT2_L com_llm_llm_common_llm_common_reg_N_60712_i ( + .I0(com_llm_link_status[0]), + .I1(com_llm_reg_next_rcv_tsn[6]), + .LO(com_llm_llm_common_llm_common_reg_N_60712_i_3002) + ); + defparam com_llm_llm_common_llm_common_reg_N_60713_i.INIT = 4'hE; + LUT2_L com_llm_llm_common_llm_common_reg_N_60713_i ( + .I0(com_llm_link_status[0]), + .I1(com_llm_reg_next_rcv_tsn[5]), + .LO(com_llm_llm_common_llm_common_reg_N_60713_i_3003) + ); + defparam com_llm_llm_common_llm_common_reg_N_60714_i.INIT = 4'hE; + LUT2_L com_llm_llm_common_llm_common_reg_N_60714_i ( + .I0(com_llm_link_status[0]), + .I1(com_llm_reg_next_rcv_tsn[4]), + .LO(com_llm_llm_common_llm_common_reg_N_60714_i_3004) + ); + defparam com_llm_llm_common_llm_common_reg_N_60715_i.INIT = 4'hE; + LUT2_L com_llm_llm_common_llm_common_reg_N_60715_i ( + .I0(com_llm_link_status[0]), + .I1(com_llm_reg_next_rcv_tsn[3]), + .LO(com_llm_llm_common_llm_common_reg_N_60715_i_3005) + ); + defparam com_llm_llm_common_llm_common_reg_N_60716_i.INIT = 4'hE; + LUT2_L com_llm_llm_common_llm_common_reg_N_60716_i ( + .I0(com_llm_link_status[0]), + .I1(com_llm_reg_next_rcv_tsn[2]), + .LO(com_llm_llm_common_llm_common_reg_N_60716_i_3006) + ); + defparam com_llm_llm_common_llm_common_reg_N_60717_i.INIT = 4'hE; + LUT2_L com_llm_llm_common_llm_common_reg_N_60717_i ( + .I0(com_llm_link_status[0]), + .I1(com_llm_reg_next_rcv_tsn[1]), + .LO(com_llm_llm_common_llm_common_reg_N_60717_i_3007) + ); + defparam com_llm_llm_common_llm_common_reg_N_60718_i.INIT = 4'hE; + LUT2_L com_llm_llm_common_llm_common_reg_N_60718_i ( + .I0(com_llm_link_status[0]), + .I1(com_llm_reg_next_rcv_tsn[0]), + .LO(com_llm_llm_common_llm_common_reg_N_60718_i_3008) + ); + defparam com_llm_llm_common_llm_common_reg_reg_tx_dllp_ack_vld18_0_a2_0_a2_0_a2_0_a2.INIT = 16'h0080; + LUT4_L com_llm_llm_common_llm_common_reg_reg_tx_dllp_ack_vld18_0_a2_0_a2_0_a2_0_a2 ( + .I0(com_llm_llm_common_llm_common_reg_N_58446_2), + .I1(com_llm_N_62468), + .I2(com_llm_reg_rx_tlp_tsn_err_0_a2_0_a2_0_a2_0_a2), + .I3(com_llm_reg_rx_tlp_tsn_dup), + .LO(com_llm_llm_common_llm_common_reg_reg_tx_dllp_ack_vld18) + ); + defparam com_llm_llm_common_llm_common_reg_reg_tx_dllp_dup_vld18_i_0_0_0.INIT = 8'h20; + LUT3_L com_llm_llm_common_llm_common_reg_reg_tx_dllp_dup_vld18_i_0_0_0 ( + .I0(com_llm_llm_common_llm_common_reg_N_62715_1_i), + .I1(com_llm_reg_dllr_in_progress), + .I2(com_llm_reg_rx_tlp_tsn_dup), + .LO(com_llm_llm_common_llm_common_reg_N_15705_i) + ); + defparam com_llm_llm_common_llm_common_reg_replay_ip21_0_a2_0_a2_0_a2.INIT = 4'h2; + LUT2_L com_llm_llm_common_llm_common_reg_replay_ip21_0_a2_0_a2_0_a2 ( + .I0(com_llm_llm_common_llm_common_reg_N_58796), + .I1(com_llm_link_status[0]), + .LO(com_llm_llm_common_llm_common_reg_replay_ip21) + ); + defparam com_llm_llm_common_llm_common_reg_N_60719_i.INIT = 4'hE; + LUT2_L com_llm_llm_common_llm_common_reg_N_60719_i ( + .I0(com_llm_link_status[0]), + .I1(com_lnk_ttrans_seq[11]), + .LO(com_llm_llm_common_llm_common_reg_N_60719_i_3012) + ); + defparam com_llm_llm_common_llm_common_reg_N_60720_i.INIT = 4'hE; + LUT2_L com_llm_llm_common_llm_common_reg_N_60720_i ( + .I0(com_llm_link_status[0]), + .I1(com_lnk_ttrans_seq[10]), + .LO(com_llm_llm_common_llm_common_reg_N_60720_i_3013) + ); + defparam com_llm_llm_common_llm_common_reg_N_60721_i.INIT = 4'hE; + LUT2_L com_llm_llm_common_llm_common_reg_N_60721_i ( + .I0(com_llm_link_status[0]), + .I1(com_lnk_ttrans_seq[9]), + .LO(com_llm_llm_common_llm_common_reg_N_60721_i_3014) + ); + defparam com_llm_llm_common_llm_common_reg_N_60722_i.INIT = 4'hE; + LUT2_L com_llm_llm_common_llm_common_reg_N_60722_i ( + .I0(com_llm_link_status[0]), + .I1(com_lnk_ttrans_seq[8]), + .LO(com_llm_llm_common_llm_common_reg_N_60722_i_3015) + ); + defparam com_llm_llm_common_llm_common_reg_N_60723_i.INIT = 4'hE; + LUT2_L com_llm_llm_common_llm_common_reg_N_60723_i ( + .I0(com_llm_link_status[0]), + .I1(com_lnk_ttrans_seq[7]), + .LO(com_llm_llm_common_llm_common_reg_N_60723_i_3016) + ); + defparam com_llm_llm_common_llm_common_reg_N_60724_i.INIT = 4'hE; + LUT2_L com_llm_llm_common_llm_common_reg_N_60724_i ( + .I0(com_llm_link_status[0]), + .I1(com_lnk_ttrans_seq[6]), + .LO(com_llm_llm_common_llm_common_reg_N_60724_i_3017) + ); + defparam com_llm_llm_common_llm_common_reg_N_60725_i.INIT = 4'hE; + LUT2_L com_llm_llm_common_llm_common_reg_N_60725_i ( + .I0(com_llm_link_status[0]), + .I1(com_lnk_ttrans_seq[5]), + .LO(com_llm_llm_common_llm_common_reg_N_60725_i_3018) + ); + defparam com_llm_llm_common_llm_common_reg_N_60726_i.INIT = 4'hE; + LUT2_L com_llm_llm_common_llm_common_reg_N_60726_i ( + .I0(com_llm_link_status[0]), + .I1(com_lnk_ttrans_seq[4]), + .LO(com_llm_llm_common_llm_common_reg_N_60726_i_3019) + ); + defparam com_llm_llm_common_llm_common_reg_N_60727_i.INIT = 4'hE; + LUT2_L com_llm_llm_common_llm_common_reg_N_60727_i ( + .I0(com_llm_link_status[0]), + .I1(com_lnk_ttrans_seq[3]), + .LO(com_llm_llm_common_llm_common_reg_N_60727_i_3020) + ); + defparam com_llm_llm_common_llm_common_reg_N_60728_i.INIT = 4'hE; + LUT2_L com_llm_llm_common_llm_common_reg_N_60728_i ( + .I0(com_llm_link_status[0]), + .I1(com_lnk_ttrans_seq[2]), + .LO(com_llm_llm_common_llm_common_reg_N_60728_i_3021) + ); + defparam com_llm_llm_common_llm_common_reg_N_60729_i.INIT = 4'hE; + LUT2_L com_llm_llm_common_llm_common_reg_N_60729_i ( + .I0(com_llm_link_status[0]), + .I1(com_lnk_ttrans_seq[1]), + .LO(com_llm_llm_common_llm_common_reg_N_60729_i_3022) + ); + defparam com_llm_llm_common_llm_common_reg_N_60730_i.INIT = 4'hE; + LUT2_L com_llm_llm_common_llm_common_reg_N_60730_i ( + .I0(com_llm_link_status[0]), + .I1(com_lnk_ttrans_seq[0]), + .LO(com_llm_llm_common_llm_common_reg_N_60730_i_3024) + ); + defparam com_llm_llm_common_llm_common_reg_N_60743_i.INIT = 4'hE; + LUT2_L com_llm_llm_common_llm_common_reg_N_60743_i ( + .I0(com_llm_link_status[0]), + .I1(com_llm_llm_common_llm_common_reg_reg_rx_dllp_tsn_q[11]), + .LO(com_llm_llm_common_llm_common_reg_N_60743_i_3025) + ); + defparam com_llm_llm_common_llm_common_reg_N_60744_i.INIT = 4'hE; + LUT2_L com_llm_llm_common_llm_common_reg_N_60744_i ( + .I0(com_llm_link_status[0]), + .I1(com_llm_llm_common_llm_common_reg_reg_rx_dllp_tsn_q[10]), + .LO(com_llm_llm_common_llm_common_reg_N_60744_i_3026) + ); + defparam com_llm_llm_common_llm_common_reg_N_60745_i.INIT = 4'hE; + LUT2_L com_llm_llm_common_llm_common_reg_N_60745_i ( + .I0(com_llm_link_status[0]), + .I1(com_llm_llm_common_llm_common_reg_reg_rx_dllp_tsn_q[9]), + .LO(com_llm_llm_common_llm_common_reg_N_60745_i_3027) + ); + defparam com_llm_llm_common_llm_common_reg_N_60746_i.INIT = 4'hE; + LUT2_L com_llm_llm_common_llm_common_reg_N_60746_i ( + .I0(com_llm_link_status[0]), + .I1(com_llm_llm_common_llm_common_reg_reg_rx_dllp_tsn_q[8]), + .LO(com_llm_llm_common_llm_common_reg_N_60746_i_3028) + ); + defparam com_llm_llm_common_llm_common_reg_N_60747_i.INIT = 4'hE; + LUT2_L com_llm_llm_common_llm_common_reg_N_60747_i ( + .I0(com_llm_link_status[0]), + .I1(com_llm_llm_common_llm_common_reg_reg_rx_dllp_tsn_q[7]), + .LO(com_llm_llm_common_llm_common_reg_N_60747_i_3029) + ); + defparam com_llm_llm_common_llm_common_reg_N_60748_i.INIT = 4'hE; + LUT2_L com_llm_llm_common_llm_common_reg_N_60748_i ( + .I0(com_llm_link_status[0]), + .I1(com_llm_llm_common_llm_common_reg_reg_rx_dllp_tsn_q[6]), + .LO(com_llm_llm_common_llm_common_reg_N_60748_i_3030) + ); + defparam com_llm_llm_common_llm_common_reg_N_60749_i.INIT = 4'hE; + LUT2_L com_llm_llm_common_llm_common_reg_N_60749_i ( + .I0(com_llm_link_status[0]), + .I1(com_llm_llm_common_llm_common_reg_reg_rx_dllp_tsn_q[5]), + .LO(com_llm_llm_common_llm_common_reg_N_60749_i_3031) + ); + defparam com_llm_llm_common_llm_common_reg_N_60750_i.INIT = 4'hE; + LUT2_L com_llm_llm_common_llm_common_reg_N_60750_i ( + .I0(com_llm_link_status[0]), + .I1(com_llm_llm_common_llm_common_reg_reg_rx_dllp_tsn_q[4]), + .LO(com_llm_llm_common_llm_common_reg_N_60750_i_3032) + ); + defparam com_llm_llm_common_llm_common_reg_N_60751_i.INIT = 4'hE; + LUT2_L com_llm_llm_common_llm_common_reg_N_60751_i ( + .I0(com_llm_link_status[0]), + .I1(com_llm_llm_common_llm_common_reg_reg_rx_dllp_tsn_q[3]), + .LO(com_llm_llm_common_llm_common_reg_N_60751_i_3033) + ); + defparam com_llm_llm_common_llm_common_reg_N_60752_i.INIT = 4'hE; + LUT2_L com_llm_llm_common_llm_common_reg_N_60752_i ( + .I0(com_llm_link_status[0]), + .I1(com_llm_llm_common_llm_common_reg_reg_rx_dllp_tsn_q[2]), + .LO(com_llm_llm_common_llm_common_reg_N_60752_i_3034) + ); + defparam com_llm_llm_common_llm_common_reg_N_60753_i.INIT = 4'hE; + LUT2_L com_llm_llm_common_llm_common_reg_N_60753_i ( + .I0(com_llm_link_status[0]), + .I1(com_llm_llm_common_llm_common_reg_reg_rx_dllp_tsn_q[1]), + .LO(com_llm_llm_common_llm_common_reg_N_60753_i_3035) + ); + defparam com_llm_llm_common_llm_common_reg_N_60754_i.INIT = 4'hE; + LUT2_L com_llm_llm_common_llm_common_reg_N_60754_i ( + .I0(com_llm_link_status[0]), + .I1(com_llm_llm_common_llm_common_reg_reg_rx_dllp_tsn_q[0]), + .LO(com_llm_llm_common_llm_common_reg_N_60754_i_3037) + ); + MUXCY com_llm_llm_common_llm_common_reg_ANSeqNum_Eq_AckdSeq_wire_0_I_19 ( + .CI(com_llm_llm_common_llm_common_reg_data_tmp_2[4]), + .DI(com_llm_llm_common_llm_common_reg_GND_2982), + .O(com_llm_llm_common_llm_common_reg_ANSeqNum_Eq_AckdSeq_wire), + .S(com_llm_llm_common_llm_common_reg_N_27) + ); + MUXCY com_llm_llm_common_llm_common_reg_curr_eq_mark_q_3_0_I_19 ( + .CI(com_llm_llm_common_llm_common_reg_data_tmp_1[4]), + .DI(com_llm_llm_common_llm_common_reg_GND_2982), + .O(com_llm_llm_common_llm_common_reg_curr_eq_mark_q_3), + .S(com_llm_llm_common_llm_common_reg_N_27_0) + ); + MUXCY com_llm_llm_common_llm_common_reg_next_eq_mark_q_3_0_I_19 ( + .CI(com_llm_llm_common_llm_common_reg_data_tmp_0[4]), + .DI(com_llm_llm_common_llm_common_reg_GND_2982), + .O(com_llm_llm_common_llm_common_reg_next_eq_mark_q_3), + .S(com_llm_llm_common_llm_common_reg_N_27_1) + ); + MUXCY com_llm_llm_common_llm_common_reg_rx_tsn_eq_sent_tsn_3_0_I_19 ( + .CI(com_llm_llm_common_llm_common_reg_data_tmp[4]), + .DI(com_llm_llm_common_llm_common_reg_GND_2982), + .O(com_llm_llm_common_llm_common_reg_rx_tsn_eq_sent_tsn_3), + .S(com_llm_llm_common_llm_common_reg_N_27_2) + ); + FDC com_llm_llm_common_llm_common_reg_reg_tx_update_clr_q ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_lnk_tretry), + .Q(com_llm_llm_common_llm_common_reg_reg_tx_update_clr_q_2983), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_common_llm_common_reg_reg_rx_dllp_nak_vld_q ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_reg_rx_dllp_nak_vld), + .Q(com_llm_llm_common_llm_common_reg_reg_rx_dllp_nak_vld_q_2984), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_common_llm_common_reg_reg_rx_dllp_ack_vld_q ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_reg_rx_dllp_ack_vld), + .Q(com_llm_llm_common_llm_common_reg_reg_rx_dllp_ack_vld_q_2985), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_common_llm_common_reg_NxtTxTSN_ANSeqNum_wire ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_common_llm_common_reg_result_i_0[11]), + .Q(com_llm_llm_common_llm_common_reg_NxtTxTSN_ANSeqNum_wire_2986), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_common_llm_common_reg_ANSeqNum_AckdSeq_wire ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_common_llm_common_reg_result_i[11]), + .Q(com_llm_llm_common_llm_common_reg_ANSeqNum_AckdSeq_wire_2987), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_common_llm_common_reg_ANSeqNum_Eq_AckdSeq ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_common_llm_common_reg_ANSeqNum_Eq_AckdSeq_5), + .Q(com_llm_llm_common_llm_common_reg_ANSeqNum_Eq_AckdSeq_2988), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_common_llm_common_reg_next_eq_mark_q ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_common_llm_common_reg_next_eq_mark_q_3), + .Q(com_llm_llm_common_llm_common_reg_next_eq_mark_q_2989), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_common_llm_common_reg_curr_eq_mark_q ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_common_llm_common_reg_curr_eq_mark_q_3), + .Q(com_llm_llm_common_llm_common_reg_curr_eq_mark_q_2990), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_common_llm_common_reg_rx_tsn_eq_sent_tsn ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_common_llm_common_reg_rx_tsn_eq_sent_tsn_3), + .Q(com_llm_llm_common_llm_common_reg_rx_tsn_eq_sent_tsn_2991), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_common_llm_common_reg_ttrans_st_hiwater_11_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_common_llm_common_reg_un3_ttrans_st_hiwater_s_11_2992), + .Q(com_llm_llm_common_llm_common_reg_ttrans_st_hiwater[11]), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_common_llm_common_reg_tmp_result_11_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_common_llm_common_reg_un3_tmp_result_s_11_2993), + .Q(com_llm_llm_common_llm_common_reg_tmp_result[11]), + .CLR(plm_link_up_i) + ); + FDP com_llm_llm_common_llm_common_reg_rx_dllp_range_err_n ( + .PRE(plm_link_up_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_common_llm_common_reg_N_85483_i_2994), + .Q(com_llm_rx_dllp_range_err_n) + ); + FDC com_llm_llm_common_llm_common_reg_reg_rx_dllp_tsn_q_0_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_reg_rx_dllp_tsn[0]), + .Q(com_llm_llm_common_llm_common_reg_reg_rx_dllp_tsn_q[0]), + .CLR(plm_link_up_i) + ); + FD com_llm_llm_common_llm_common_reg_reg_tx_next_tsn_11_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_common_llm_common_reg_reg_tx_next_tsn_4[11]), + .Q(com_llm_llm_common_llm_common_reg_reg_tx_next_tsn[11]) + ); + FD com_llm_llm_common_llm_common_reg_reg_tx_next_tsn_10_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_common_llm_common_reg_reg_tx_next_tsn_4[10]), + .Q(com_llm_llm_common_llm_common_reg_reg_tx_next_tsn[10]) + ); + FD com_llm_llm_common_llm_common_reg_reg_tx_next_tsn_9_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_common_llm_common_reg_reg_tx_next_tsn_4[9]), + .Q(com_llm_llm_common_llm_common_reg_reg_tx_next_tsn[9]) + ); + FD com_llm_llm_common_llm_common_reg_reg_tx_next_tsn_8_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_common_llm_common_reg_reg_tx_next_tsn_4[8]), + .Q(com_llm_llm_common_llm_common_reg_reg_tx_next_tsn[8]) + ); + FD com_llm_llm_common_llm_common_reg_reg_tx_next_tsn_7_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_common_llm_common_reg_reg_tx_next_tsn_4[7]), + .Q(com_llm_llm_common_llm_common_reg_reg_tx_next_tsn[7]) + ); + FD com_llm_llm_common_llm_common_reg_reg_tx_next_tsn_6_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_common_llm_common_reg_reg_tx_next_tsn_4[6]), + .Q(com_llm_llm_common_llm_common_reg_reg_tx_next_tsn[6]) + ); + FD com_llm_llm_common_llm_common_reg_reg_tx_next_tsn_5_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_common_llm_common_reg_reg_tx_next_tsn_4[5]), + .Q(com_llm_llm_common_llm_common_reg_reg_tx_next_tsn[5]) + ); + FD com_llm_llm_common_llm_common_reg_reg_tx_next_tsn_4_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_common_llm_common_reg_reg_tx_next_tsn_4[4]), + .Q(com_llm_llm_common_llm_common_reg_reg_tx_next_tsn[4]) + ); + FD com_llm_llm_common_llm_common_reg_reg_tx_next_tsn_3_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_common_llm_common_reg_reg_tx_next_tsn_4[3]), + .Q(com_llm_llm_common_llm_common_reg_reg_tx_next_tsn[3]) + ); + FD com_llm_llm_common_llm_common_reg_reg_tx_next_tsn_2_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_common_llm_common_reg_reg_tx_next_tsn_4[2]), + .Q(com_llm_llm_common_llm_common_reg_reg_tx_next_tsn[2]) + ); + FD com_llm_llm_common_llm_common_reg_reg_tx_next_tsn_1_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_common_llm_common_reg_reg_tx_next_tsn_4[1]), + .Q(com_llm_llm_common_llm_common_reg_reg_tx_next_tsn[1]) + ); + FDC com_llm_llm_common_llm_common_reg_reg_rx_dllp_tsn_q_11_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_reg_rx_dllp_tsn[11]), + .Q(com_llm_llm_common_llm_common_reg_reg_rx_dllp_tsn_q[11]), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_common_llm_common_reg_reg_rx_dllp_tsn_q_10_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_reg_rx_dllp_tsn[10]), + .Q(com_llm_llm_common_llm_common_reg_reg_rx_dllp_tsn_q[10]), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_common_llm_common_reg_reg_rx_dllp_tsn_q_9_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_reg_rx_dllp_tsn[9]), + .Q(com_llm_llm_common_llm_common_reg_reg_rx_dllp_tsn_q[9]), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_common_llm_common_reg_reg_rx_dllp_tsn_q_8_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_reg_rx_dllp_tsn[8]), + .Q(com_llm_llm_common_llm_common_reg_reg_rx_dllp_tsn_q[8]), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_common_llm_common_reg_reg_rx_dllp_tsn_q_7_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_reg_rx_dllp_tsn[7]), + .Q(com_llm_llm_common_llm_common_reg_reg_rx_dllp_tsn_q[7]), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_common_llm_common_reg_reg_rx_dllp_tsn_q_6_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_reg_rx_dllp_tsn[6]), + .Q(com_llm_llm_common_llm_common_reg_reg_rx_dllp_tsn_q[6]), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_common_llm_common_reg_reg_rx_dllp_tsn_q_5_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_reg_rx_dllp_tsn[5]), + .Q(com_llm_llm_common_llm_common_reg_reg_rx_dllp_tsn_q[5]), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_common_llm_common_reg_reg_rx_dllp_tsn_q_4_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_reg_rx_dllp_tsn[4]), + .Q(com_llm_llm_common_llm_common_reg_reg_rx_dllp_tsn_q[4]), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_common_llm_common_reg_reg_rx_dllp_tsn_q_3_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_reg_rx_dllp_tsn[3]), + .Q(com_llm_llm_common_llm_common_reg_reg_rx_dllp_tsn_q[3]), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_common_llm_common_reg_reg_rx_dllp_tsn_q_2_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_reg_rx_dllp_tsn[2]), + .Q(com_llm_llm_common_llm_common_reg_reg_rx_dllp_tsn_q[2]), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_common_llm_common_reg_reg_rx_dllp_tsn_q_1_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_reg_rx_dllp_tsn[1]), + .Q(com_llm_llm_common_llm_common_reg_reg_rx_dllp_tsn_q[1]), + .CLR(plm_link_up_i) + ); + FDCE com_llm_llm_common_llm_common_reg_reg_tx_dllp_nak_vld ( + .CE(com_llm_llm_common_llm_common_reg_N_87517_i_2995), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_N_63255_i), + .Q(com_llm_reg_tx_dllp_nak_vld), + .CLR(plm_link_up_i) + ); + FDCE com_llm_llm_common_llm_common_reg_reg_dllr_in_progress ( + .CE(com_llm_llm_common_llm_common_reg_N_87591_i_2996), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_common_llm_common_reg_reg_dllr_in_progress17), + .Q(com_llm_reg_dllr_in_progress), + .CLR(plm_link_up_i) + ); + FDPE com_llm_llm_common_llm_common_reg_reg_tx_dllp_tsn_11_ ( + .PRE(plm_link_up_i), + .CE(com_llm_llm_common_llm_common_reg_N_87516_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_common_llm_common_reg_N_60707_i_2997), + .Q(com_llm_reg_tx_dllp_tsn[11]) + ); + FDPE com_llm_llm_common_llm_common_reg_reg_tx_dllp_tsn_10_ ( + .PRE(plm_link_up_i), + .CE(com_llm_llm_common_llm_common_reg_N_87516_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_common_llm_common_reg_N_60708_i_2998), + .Q(com_llm_reg_tx_dllp_tsn[10]) + ); + FDPE com_llm_llm_common_llm_common_reg_reg_tx_dllp_tsn_9_ ( + .PRE(plm_link_up_i), + .CE(com_llm_llm_common_llm_common_reg_N_87516_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_common_llm_common_reg_N_60709_i_2999), + .Q(com_llm_reg_tx_dllp_tsn[9]) + ); + FDPE com_llm_llm_common_llm_common_reg_reg_tx_dllp_tsn_8_ ( + .PRE(plm_link_up_i), + .CE(com_llm_llm_common_llm_common_reg_N_87516_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_common_llm_common_reg_N_60710_i_3000), + .Q(com_llm_reg_tx_dllp_tsn[8]) + ); + FDPE com_llm_llm_common_llm_common_reg_reg_tx_dllp_tsn_7_ ( + .PRE(plm_link_up_i), + .CE(com_llm_llm_common_llm_common_reg_N_87516_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_common_llm_common_reg_N_60711_i_3001), + .Q(com_llm_reg_tx_dllp_tsn[7]) + ); + FDPE com_llm_llm_common_llm_common_reg_reg_tx_dllp_tsn_6_ ( + .PRE(plm_link_up_i), + .CE(com_llm_llm_common_llm_common_reg_N_87516_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_common_llm_common_reg_N_60712_i_3002), + .Q(com_llm_reg_tx_dllp_tsn[6]) + ); + FDPE com_llm_llm_common_llm_common_reg_reg_tx_dllp_tsn_5_ ( + .PRE(plm_link_up_i), + .CE(com_llm_llm_common_llm_common_reg_N_87516_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_common_llm_common_reg_N_60713_i_3003), + .Q(com_llm_reg_tx_dllp_tsn[5]) + ); + FDPE com_llm_llm_common_llm_common_reg_reg_tx_dllp_tsn_4_ ( + .PRE(plm_link_up_i), + .CE(com_llm_llm_common_llm_common_reg_N_87516_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_common_llm_common_reg_N_60714_i_3004), + .Q(com_llm_reg_tx_dllp_tsn[4]) + ); + FDPE com_llm_llm_common_llm_common_reg_reg_tx_dllp_tsn_3_ ( + .PRE(plm_link_up_i), + .CE(com_llm_llm_common_llm_common_reg_N_87516_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_common_llm_common_reg_N_60715_i_3005), + .Q(com_llm_reg_tx_dllp_tsn[3]) + ); + FDPE com_llm_llm_common_llm_common_reg_reg_tx_dllp_tsn_2_ ( + .PRE(plm_link_up_i), + .CE(com_llm_llm_common_llm_common_reg_N_87516_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_common_llm_common_reg_N_60716_i_3006), + .Q(com_llm_reg_tx_dllp_tsn[2]) + ); + FDPE com_llm_llm_common_llm_common_reg_reg_tx_dllp_tsn_1_ ( + .PRE(plm_link_up_i), + .CE(com_llm_llm_common_llm_common_reg_N_87516_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_common_llm_common_reg_N_60717_i_3007), + .Q(com_llm_reg_tx_dllp_tsn[1]) + ); + FDPE com_llm_llm_common_llm_common_reg_reg_tx_dllp_tsn_0_ ( + .PRE(plm_link_up_i), + .CE(com_llm_llm_common_llm_common_reg_N_87516_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_common_llm_common_reg_N_60718_i_3008), + .Q(com_llm_reg_tx_dllp_tsn[0]) + ); + FDCE com_llm_llm_common_llm_common_reg_reg_tx_dllp_ack_vld ( + .CE(com_llm_llm_common_llm_common_reg_N_62715_i_i_3038), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_common_llm_common_reg_reg_tx_dllp_ack_vld18), + .Q(com_llm_reg_tx_dllp_ack_vld), + .CLR(plm_link_up_i) + ); + FDCE com_llm_llm_common_llm_common_reg_reg_tx_dllp_dup_vld ( + .CE(com_llm_llm_common_llm_common_reg_N_58434_i_3009), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_common_llm_common_reg_N_15705_i), + .Q(com_llm_reg_tx_dllp_dup_vld), + .CLR(plm_link_up_i) + ); + FDCE com_llm_llm_common_llm_common_reg_replay_ip ( + .CE(com_llm_llm_common_llm_common_reg_N_85479_i_3010), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_common_llm_common_reg_replay_ip21), + .Q(com_llm_llm_common_llm_common_reg_replay_ip_3011), + .CLR(plm_link_up_i) + ); + FDPE com_llm_llm_common_llm_common_reg_hi_water_mark_11_ ( + .PRE(plm_link_up_i), + .CE(com_llm_llm_common_llm_common_reg_N_87603_i_3023), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_common_llm_common_reg_N_60719_i_3012), + .Q(com_llm_llm_common_llm_common_reg_hi_water_mark[11]) + ); + FDPE com_llm_llm_common_llm_common_reg_hi_water_mark_10_ ( + .PRE(plm_link_up_i), + .CE(com_llm_llm_common_llm_common_reg_N_87603_i_3023), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_common_llm_common_reg_N_60720_i_3013), + .Q(com_llm_llm_common_llm_common_reg_hi_water_mark[10]) + ); + FDPE com_llm_llm_common_llm_common_reg_hi_water_mark_9_ ( + .PRE(plm_link_up_i), + .CE(com_llm_llm_common_llm_common_reg_N_87603_i_3023), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_common_llm_common_reg_N_60721_i_3014), + .Q(com_llm_llm_common_llm_common_reg_hi_water_mark[9]) + ); + FDPE com_llm_llm_common_llm_common_reg_hi_water_mark_8_ ( + .PRE(plm_link_up_i), + .CE(com_llm_llm_common_llm_common_reg_N_87603_i_3023), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_common_llm_common_reg_N_60722_i_3015), + .Q(com_llm_llm_common_llm_common_reg_hi_water_mark[8]) + ); + FDPE com_llm_llm_common_llm_common_reg_hi_water_mark_7_ ( + .PRE(plm_link_up_i), + .CE(com_llm_llm_common_llm_common_reg_N_87603_i_3023), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_common_llm_common_reg_N_60723_i_3016), + .Q(com_llm_llm_common_llm_common_reg_hi_water_mark[7]) + ); + FDPE com_llm_llm_common_llm_common_reg_hi_water_mark_6_ ( + .PRE(plm_link_up_i), + .CE(com_llm_llm_common_llm_common_reg_N_87603_i_3023), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_common_llm_common_reg_N_60724_i_3017), + .Q(com_llm_llm_common_llm_common_reg_hi_water_mark[6]) + ); + FDPE com_llm_llm_common_llm_common_reg_hi_water_mark_5_ ( + .PRE(plm_link_up_i), + .CE(com_llm_llm_common_llm_common_reg_N_87603_i_3023), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_common_llm_common_reg_N_60725_i_3018), + .Q(com_llm_llm_common_llm_common_reg_hi_water_mark[5]) + ); + FDPE com_llm_llm_common_llm_common_reg_hi_water_mark_4_ ( + .PRE(plm_link_up_i), + .CE(com_llm_llm_common_llm_common_reg_N_87603_i_3023), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_common_llm_common_reg_N_60726_i_3019), + .Q(com_llm_llm_common_llm_common_reg_hi_water_mark[4]) + ); + FDPE com_llm_llm_common_llm_common_reg_hi_water_mark_3_ ( + .PRE(plm_link_up_i), + .CE(com_llm_llm_common_llm_common_reg_N_87603_i_3023), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_common_llm_common_reg_N_60727_i_3020), + .Q(com_llm_llm_common_llm_common_reg_hi_water_mark[3]) + ); + FDPE com_llm_llm_common_llm_common_reg_hi_water_mark_2_ ( + .PRE(plm_link_up_i), + .CE(com_llm_llm_common_llm_common_reg_N_87603_i_3023), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_common_llm_common_reg_N_60728_i_3021), + .Q(com_llm_llm_common_llm_common_reg_hi_water_mark[2]) + ); + FDPE com_llm_llm_common_llm_common_reg_hi_water_mark_1_ ( + .PRE(plm_link_up_i), + .CE(com_llm_llm_common_llm_common_reg_N_87603_i_3023), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_common_llm_common_reg_N_60729_i_3022), + .Q(com_llm_llm_common_llm_common_reg_hi_water_mark[1]) + ); + FDPE com_llm_llm_common_llm_common_reg_hi_water_mark_0_ ( + .PRE(plm_link_up_i), + .CE(com_llm_llm_common_llm_common_reg_N_87603_i_3023), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_common_llm_common_reg_N_60730_i_3024), + .Q(com_llm_llm_common_llm_common_reg_hi_water_mark[0]) + ); + FDPE com_llm_llm_common_llm_common_reg_reg_tx_ackd_tsn_11_ ( + .PRE(plm_link_up_i), + .CE(com_llm_llm_common_llm_common_reg_N_87604_i_3036), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_common_llm_common_reg_N_60743_i_3025), + .Q(com_lnk_tupdate_seq[11]) + ); + FDPE com_llm_llm_common_llm_common_reg_reg_tx_ackd_tsn_10_ ( + .PRE(plm_link_up_i), + .CE(com_llm_llm_common_llm_common_reg_N_87604_i_3036), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_common_llm_common_reg_N_60744_i_3026), + .Q(com_lnk_tupdate_seq[10]) + ); + FDPE com_llm_llm_common_llm_common_reg_reg_tx_ackd_tsn_9_ ( + .PRE(plm_link_up_i), + .CE(com_llm_llm_common_llm_common_reg_N_87604_i_3036), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_common_llm_common_reg_N_60745_i_3027), + .Q(com_lnk_tupdate_seq[9]) + ); + FDPE com_llm_llm_common_llm_common_reg_reg_tx_ackd_tsn_8_ ( + .PRE(plm_link_up_i), + .CE(com_llm_llm_common_llm_common_reg_N_87604_i_3036), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_common_llm_common_reg_N_60746_i_3028), + .Q(com_lnk_tupdate_seq[8]) + ); + FDPE com_llm_llm_common_llm_common_reg_reg_tx_ackd_tsn_7_ ( + .PRE(plm_link_up_i), + .CE(com_llm_llm_common_llm_common_reg_N_87604_i_3036), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_common_llm_common_reg_N_60747_i_3029), + .Q(com_lnk_tupdate_seq[7]) + ); + FDPE com_llm_llm_common_llm_common_reg_reg_tx_ackd_tsn_6_ ( + .PRE(plm_link_up_i), + .CE(com_llm_llm_common_llm_common_reg_N_87604_i_3036), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_common_llm_common_reg_N_60748_i_3030), + .Q(com_lnk_tupdate_seq[6]) + ); + FDPE com_llm_llm_common_llm_common_reg_reg_tx_ackd_tsn_5_ ( + .PRE(plm_link_up_i), + .CE(com_llm_llm_common_llm_common_reg_N_87604_i_3036), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_common_llm_common_reg_N_60749_i_3031), + .Q(com_lnk_tupdate_seq[5]) + ); + FDPE com_llm_llm_common_llm_common_reg_reg_tx_ackd_tsn_4_ ( + .PRE(plm_link_up_i), + .CE(com_llm_llm_common_llm_common_reg_N_87604_i_3036), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_common_llm_common_reg_N_60750_i_3032), + .Q(com_lnk_tupdate_seq[4]) + ); + FDPE com_llm_llm_common_llm_common_reg_reg_tx_ackd_tsn_3_ ( + .PRE(plm_link_up_i), + .CE(com_llm_llm_common_llm_common_reg_N_87604_i_3036), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_common_llm_common_reg_N_60751_i_3033), + .Q(com_lnk_tupdate_seq[3]) + ); + FDPE com_llm_llm_common_llm_common_reg_reg_tx_ackd_tsn_2_ ( + .PRE(plm_link_up_i), + .CE(com_llm_llm_common_llm_common_reg_N_87604_i_3036), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_common_llm_common_reg_N_60752_i_3034), + .Q(com_lnk_tupdate_seq[2]) + ); + FDPE com_llm_llm_common_llm_common_reg_reg_tx_ackd_tsn_1_ ( + .PRE(plm_link_up_i), + .CE(com_llm_llm_common_llm_common_reg_N_87604_i_3036), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_common_llm_common_reg_N_60753_i_3035), + .Q(com_lnk_tupdate_seq[1]) + ); + FDPE com_llm_llm_common_llm_common_reg_reg_tx_ackd_tsn_0_ ( + .PRE(plm_link_up_i), + .CE(com_llm_llm_common_llm_common_reg_N_87604_i_3036), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_common_llm_common_reg_N_60754_i_3037), + .Q(com_lnk_tupdate_seq[0]) + ); + INV com_llm_llm_common_llm_common_reg_N_62715_i_i ( + .I(com_llm_llm_common_llm_common_reg_N_62715_i), + .O(com_llm_llm_common_llm_common_reg_N_62715_i_i_3038) + ); + defparam com_llm_llm_common_llm_common_reg_rx_tsn_eq_sent_tsn_3_0_I_27.INIT = 16'h8421; + LUT4 com_llm_llm_common_llm_common_reg_rx_tsn_eq_sent_tsn_3_0_I_27 ( + .I0(com_llm_reg_rx_dllp_tsn[10]), + .I1(com_llm_reg_rx_dllp_tsn[11]), + .I2(com_lnk_ttrans_seq[10]), + .I3(com_lnk_ttrans_seq[11]), + .O(com_llm_llm_common_llm_common_reg_N_27_2) + ); + defparam com_llm_llm_common_llm_common_reg_next_eq_mark_q_3_0_I_27.INIT = 16'h8421; + LUT4 com_llm_llm_common_llm_common_reg_next_eq_mark_q_3_0_I_27 ( + .I0(com_llm_llm_common_llm_common_reg_hi_water_mark[10]), + .I1(com_llm_llm_common_llm_common_reg_hi_water_mark[11]), + .I2(com_llm_llm_common_llm_common_reg_reg_tx_next_tsn[10]), + .I3(com_llm_llm_common_llm_common_reg_reg_tx_next_tsn[11]), + .O(com_llm_llm_common_llm_common_reg_N_27_1) + ); + defparam com_llm_llm_common_llm_common_reg_curr_eq_mark_q_3_0_I_27.INIT = 16'h8421; + LUT4 com_llm_llm_common_llm_common_reg_curr_eq_mark_q_3_0_I_27 ( + .I0(com_llm_llm_common_llm_common_reg_hi_water_mark[10]), + .I1(com_llm_llm_common_llm_common_reg_hi_water_mark[11]), + .I2(com_llm_llm_common_llm_common_reg_reg_tx_curr_tsn[10]), + .I3(com_llm_llm_common_llm_common_reg_reg_tx_curr_tsn[11]), + .O(com_llm_llm_common_llm_common_reg_N_27_0) + ); + defparam com_llm_llm_common_llm_common_reg_ANSeqNum_Eq_AckdSeq_wire_0_I_27.INIT = 16'h8421; + LUT4 com_llm_llm_common_llm_common_reg_ANSeqNum_Eq_AckdSeq_wire_0_I_27 ( + .I0(com_llm_reg_rx_dllp_tsn[10]), + .I1(com_llm_reg_rx_dllp_tsn[11]), + .I2(com_lnk_tupdate_seq[10]), + .I3(com_lnk_tupdate_seq[11]), + .O(com_llm_llm_common_llm_common_reg_N_27) + ); + defparam com_llm_llm_common_llm_common_reg_reg_tx_next_tsn_4_axb_0.INIT = 4'h9; + LUT2 com_llm_llm_common_llm_common_reg_reg_tx_next_tsn_4_axb_0 ( + .I0(com_lnk_ttrans_seq[0]), + .I1(plm_link_up_1), + .O(com_llm_llm_common_llm_common_reg_reg_tx_next_tsn_4_axb_0_3039) + ); + defparam com_llm_llm_common_llm_common_reg_un3_tmp_result_axb_10.INIT = 4'h9; + LUT2 com_llm_llm_common_llm_common_reg_un3_tmp_result_axb_10 ( + .I0(com_llm_reg_rx_dllp_tsn_m1[10]), + .I1(com_lnk_ttrans_seq[10]), + .O(com_llm_llm_common_llm_common_reg_un3_tmp_result_axb_10_3040) + ); + defparam com_llm_llm_common_llm_common_reg_un3_tmp_result_axb_9.INIT = 4'h9; + LUT2 com_llm_llm_common_llm_common_reg_un3_tmp_result_axb_9 ( + .I0(com_llm_reg_rx_dllp_tsn_m1[9]), + .I1(com_lnk_ttrans_seq[9]), + .O(com_llm_llm_common_llm_common_reg_un3_tmp_result_axb_9_3041) + ); + defparam com_llm_llm_common_llm_common_reg_un3_tmp_result_axb_8.INIT = 4'h9; + LUT2 com_llm_llm_common_llm_common_reg_un3_tmp_result_axb_8 ( + .I0(com_llm_reg_rx_dllp_tsn_m1[8]), + .I1(com_lnk_ttrans_seq[8]), + .O(com_llm_llm_common_llm_common_reg_un3_tmp_result_axb_8_3042) + ); + defparam com_llm_llm_common_llm_common_reg_un3_tmp_result_axb_7.INIT = 4'h9; + LUT2 com_llm_llm_common_llm_common_reg_un3_tmp_result_axb_7 ( + .I0(com_llm_reg_rx_dllp_tsn_m1[7]), + .I1(com_lnk_ttrans_seq[7]), + .O(com_llm_llm_common_llm_common_reg_un3_tmp_result_axb_7_3043) + ); + defparam com_llm_llm_common_llm_common_reg_un3_tmp_result_axb_6.INIT = 4'h9; + LUT2 com_llm_llm_common_llm_common_reg_un3_tmp_result_axb_6 ( + .I0(com_llm_reg_rx_dllp_tsn_m1[6]), + .I1(com_lnk_ttrans_seq[6]), + .O(com_llm_llm_common_llm_common_reg_un3_tmp_result_axb_6_3044) + ); + defparam com_llm_llm_common_llm_common_reg_un3_tmp_result_axb_5.INIT = 4'h9; + LUT2 com_llm_llm_common_llm_common_reg_un3_tmp_result_axb_5 ( + .I0(com_llm_reg_rx_dllp_tsn_m1[5]), + .I1(com_lnk_ttrans_seq[5]), + .O(com_llm_llm_common_llm_common_reg_un3_tmp_result_axb_5_3045) + ); + defparam com_llm_llm_common_llm_common_reg_un3_tmp_result_axb_4.INIT = 4'h9; + LUT2 com_llm_llm_common_llm_common_reg_un3_tmp_result_axb_4 ( + .I0(com_llm_reg_rx_dllp_tsn_m1[4]), + .I1(com_lnk_ttrans_seq[4]), + .O(com_llm_llm_common_llm_common_reg_un3_tmp_result_axb_4_3046) + ); + defparam com_llm_llm_common_llm_common_reg_un3_tmp_result_axb_3.INIT = 4'h9; + LUT2 com_llm_llm_common_llm_common_reg_un3_tmp_result_axb_3 ( + .I0(com_llm_reg_rx_dllp_tsn_m1[3]), + .I1(com_lnk_ttrans_seq[3]), + .O(com_llm_llm_common_llm_common_reg_un3_tmp_result_axb_3_3047) + ); + defparam com_llm_llm_common_llm_common_reg_un3_tmp_result_axb_2.INIT = 4'h9; + LUT2 com_llm_llm_common_llm_common_reg_un3_tmp_result_axb_2 ( + .I0(com_llm_reg_rx_dllp_tsn_m1[2]), + .I1(com_lnk_ttrans_seq[2]), + .O(com_llm_llm_common_llm_common_reg_un3_tmp_result_axb_2_3048) + ); + defparam com_llm_llm_common_llm_common_reg_un3_tmp_result_axb_1.INIT = 4'h9; + LUT2 com_llm_llm_common_llm_common_reg_un3_tmp_result_axb_1 ( + .I0(com_llm_reg_rx_dllp_tsn_m1[1]), + .I1(com_lnk_ttrans_seq[1]), + .O(com_llm_llm_common_llm_common_reg_un3_tmp_result_axb_1_3049) + ); + defparam com_llm_llm_common_llm_common_reg_un3_tmp_result_axb_0.INIT = 4'h6; + LUT2 com_llm_llm_common_llm_common_reg_un3_tmp_result_axb_0 ( + .I0(com_llm_reg_rx_dllp_tsn[0]), + .I1(com_lnk_ttrans_seq[0]), + .O(com_llm_llm_common_llm_common_reg_un3_tmp_result_axb_0_3050) + ); + defparam com_llm_llm_common_llm_common_reg_un3_ttrans_st_hiwater_axb_10.INIT = 4'h9; + LUT2 com_llm_llm_common_llm_common_reg_un3_ttrans_st_hiwater_axb_10 ( + .I0(com_llm_llm_common_llm_common_reg_hi_water_mark[10]), + .I1(com_lnk_ttrans_seq[10]), + .O(com_llm_llm_common_llm_common_reg_un3_ttrans_st_hiwater_axb_10_3051) + ); + defparam com_llm_llm_common_llm_common_reg_un3_ttrans_st_hiwater_axb_9.INIT = 4'h9; + LUT2 com_llm_llm_common_llm_common_reg_un3_ttrans_st_hiwater_axb_9 ( + .I0(com_llm_llm_common_llm_common_reg_hi_water_mark[9]), + .I1(com_lnk_ttrans_seq[9]), + .O(com_llm_llm_common_llm_common_reg_un3_ttrans_st_hiwater_axb_9_3052) + ); + defparam com_llm_llm_common_llm_common_reg_un3_ttrans_st_hiwater_axb_8.INIT = 4'h9; + LUT2 com_llm_llm_common_llm_common_reg_un3_ttrans_st_hiwater_axb_8 ( + .I0(com_llm_llm_common_llm_common_reg_hi_water_mark[8]), + .I1(com_lnk_ttrans_seq[8]), + .O(com_llm_llm_common_llm_common_reg_un3_ttrans_st_hiwater_axb_8_3053) + ); + defparam com_llm_llm_common_llm_common_reg_un3_ttrans_st_hiwater_axb_7.INIT = 4'h9; + LUT2 com_llm_llm_common_llm_common_reg_un3_ttrans_st_hiwater_axb_7 ( + .I0(com_llm_llm_common_llm_common_reg_hi_water_mark[7]), + .I1(com_lnk_ttrans_seq[7]), + .O(com_llm_llm_common_llm_common_reg_un3_ttrans_st_hiwater_axb_7_3054) + ); + defparam com_llm_llm_common_llm_common_reg_un3_ttrans_st_hiwater_axb_6.INIT = 4'h9; + LUT2 com_llm_llm_common_llm_common_reg_un3_ttrans_st_hiwater_axb_6 ( + .I0(com_llm_llm_common_llm_common_reg_hi_water_mark[6]), + .I1(com_lnk_ttrans_seq[6]), + .O(com_llm_llm_common_llm_common_reg_un3_ttrans_st_hiwater_axb_6_3055) + ); + defparam com_llm_llm_common_llm_common_reg_un3_ttrans_st_hiwater_axb_5.INIT = 4'h9; + LUT2 com_llm_llm_common_llm_common_reg_un3_ttrans_st_hiwater_axb_5 ( + .I0(com_llm_llm_common_llm_common_reg_hi_water_mark[5]), + .I1(com_lnk_ttrans_seq[5]), + .O(com_llm_llm_common_llm_common_reg_un3_ttrans_st_hiwater_axb_5_3056) + ); + defparam com_llm_llm_common_llm_common_reg_un3_ttrans_st_hiwater_axb_4.INIT = 4'h9; + LUT2 com_llm_llm_common_llm_common_reg_un3_ttrans_st_hiwater_axb_4 ( + .I0(com_llm_llm_common_llm_common_reg_hi_water_mark[4]), + .I1(com_lnk_ttrans_seq[4]), + .O(com_llm_llm_common_llm_common_reg_un3_ttrans_st_hiwater_axb_4_3057) + ); + defparam com_llm_llm_common_llm_common_reg_un3_ttrans_st_hiwater_axb_3.INIT = 4'h9; + LUT2 com_llm_llm_common_llm_common_reg_un3_ttrans_st_hiwater_axb_3 ( + .I0(com_llm_llm_common_llm_common_reg_hi_water_mark[3]), + .I1(com_lnk_ttrans_seq[3]), + .O(com_llm_llm_common_llm_common_reg_un3_ttrans_st_hiwater_axb_3_3058) + ); + defparam com_llm_llm_common_llm_common_reg_un3_ttrans_st_hiwater_axb_2.INIT = 4'h9; + LUT2 com_llm_llm_common_llm_common_reg_un3_ttrans_st_hiwater_axb_2 ( + .I0(com_llm_llm_common_llm_common_reg_hi_water_mark[2]), + .I1(com_lnk_ttrans_seq[2]), + .O(com_llm_llm_common_llm_common_reg_un3_ttrans_st_hiwater_axb_2_3059) + ); + defparam com_llm_llm_common_llm_common_reg_un3_ttrans_st_hiwater_axb_1.INIT = 4'h9; + LUT2 com_llm_llm_common_llm_common_reg_un3_ttrans_st_hiwater_axb_1 ( + .I0(com_llm_llm_common_llm_common_reg_hi_water_mark[1]), + .I1(com_lnk_ttrans_seq[1]), + .O(com_llm_llm_common_llm_common_reg_un3_ttrans_st_hiwater_axb_1_3060) + ); + defparam com_llm_llm_common_llm_common_reg_un3_ttrans_st_hiwater_axb_0.INIT = 4'h9; + LUT2 com_llm_llm_common_llm_common_reg_un3_ttrans_st_hiwater_axb_0 ( + .I0(com_llm_llm_common_llm_common_reg_hi_water_mark[0]), + .I1(com_lnk_ttrans_seq[0]), + .O(com_llm_llm_common_llm_common_reg_un3_ttrans_st_hiwater_axb_0_3061) + ); + defparam com_llm_llm_common_llm_common_reg_ANSeqNum_Eq_AckdSeq_wire_0_I_54.INIT = 16'h8421; + LUT4 com_llm_llm_common_llm_common_reg_ANSeqNum_Eq_AckdSeq_wire_0_I_54 ( + .I0(com_llm_reg_rx_dllp_tsn[2]), + .I1(com_llm_reg_rx_dllp_tsn[3]), + .I2(com_lnk_tupdate_seq[2]), + .I3(com_lnk_tupdate_seq[3]), + .O(com_llm_llm_common_llm_common_reg_N_3_2) + ); + defparam com_llm_llm_common_llm_common_reg_ANSeqNum_Eq_AckdSeq_wire_0_I_45.INIT = 16'h8421; + LUT4 com_llm_llm_common_llm_common_reg_ANSeqNum_Eq_AckdSeq_wire_0_I_45 ( + .I0(com_llm_reg_rx_dllp_tsn[8]), + .I1(com_llm_reg_rx_dllp_tsn[9]), + .I2(com_lnk_tupdate_seq[8]), + .I3(com_lnk_tupdate_seq[9]), + .O(com_llm_llm_common_llm_common_reg_N_11_2) + ); + defparam com_llm_llm_common_llm_common_reg_ANSeqNum_Eq_AckdSeq_wire_0_I_36.INIT = 16'h8421; + LUT4 com_llm_llm_common_llm_common_reg_ANSeqNum_Eq_AckdSeq_wire_0_I_36 ( + .I0(com_llm_reg_rx_dllp_tsn[6]), + .I1(com_llm_reg_rx_dllp_tsn[7]), + .I2(com_lnk_tupdate_seq[6]), + .I3(com_lnk_tupdate_seq[7]), + .O(com_llm_llm_common_llm_common_reg_N_19_2) + ); + defparam com_llm_llm_common_llm_common_reg_ANSeqNum_Eq_AckdSeq_wire_0_I_18.INIT = 16'h8421; + LUT4 com_llm_llm_common_llm_common_reg_ANSeqNum_Eq_AckdSeq_wire_0_I_18 ( + .I0(com_llm_reg_rx_dllp_tsn[4]), + .I1(com_llm_reg_rx_dllp_tsn[5]), + .I2(com_lnk_tupdate_seq[4]), + .I3(com_lnk_tupdate_seq[5]), + .O(com_llm_llm_common_llm_common_reg_N_35_2) + ); + defparam com_llm_llm_common_llm_common_reg_ANSeqNum_Eq_AckdSeq_wire_0_I_9.INIT = 16'h8421; + LUT4 com_llm_llm_common_llm_common_reg_ANSeqNum_Eq_AckdSeq_wire_0_I_9 ( + .I0(com_llm_reg_rx_dllp_tsn[0]), + .I1(com_llm_reg_rx_dllp_tsn[1]), + .I2(com_lnk_tupdate_seq[0]), + .I3(com_lnk_tupdate_seq[1]), + .O(com_llm_llm_common_llm_common_reg_N_43_2) + ); + defparam com_llm_llm_common_llm_common_reg_curr_eq_mark_q_3_0_I_54.INIT = 16'h8421; + LUT4 com_llm_llm_common_llm_common_reg_curr_eq_mark_q_3_0_I_54 ( + .I0(com_llm_llm_common_llm_common_reg_hi_water_mark[2]), + .I1(com_llm_llm_common_llm_common_reg_hi_water_mark[3]), + .I2(com_llm_llm_common_llm_common_reg_reg_tx_curr_tsn[2]), + .I3(com_llm_llm_common_llm_common_reg_reg_tx_curr_tsn[3]), + .O(com_llm_llm_common_llm_common_reg_N_3_1) + ); + defparam com_llm_llm_common_llm_common_reg_curr_eq_mark_q_3_0_I_45.INIT = 16'h8421; + LUT4 com_llm_llm_common_llm_common_reg_curr_eq_mark_q_3_0_I_45 ( + .I0(com_llm_llm_common_llm_common_reg_hi_water_mark[8]), + .I1(com_llm_llm_common_llm_common_reg_hi_water_mark[9]), + .I2(com_llm_llm_common_llm_common_reg_reg_tx_curr_tsn[8]), + .I3(com_llm_llm_common_llm_common_reg_reg_tx_curr_tsn[9]), + .O(com_llm_llm_common_llm_common_reg_N_11_1) + ); + defparam com_llm_llm_common_llm_common_reg_curr_eq_mark_q_3_0_I_36.INIT = 16'h8421; + LUT4 com_llm_llm_common_llm_common_reg_curr_eq_mark_q_3_0_I_36 ( + .I0(com_llm_llm_common_llm_common_reg_hi_water_mark[6]), + .I1(com_llm_llm_common_llm_common_reg_hi_water_mark[7]), + .I2(com_llm_llm_common_llm_common_reg_reg_tx_curr_tsn[6]), + .I3(com_llm_llm_common_llm_common_reg_reg_tx_curr_tsn[7]), + .O(com_llm_llm_common_llm_common_reg_N_19_1) + ); + defparam com_llm_llm_common_llm_common_reg_curr_eq_mark_q_3_0_I_18.INIT = 16'h8421; + LUT4 com_llm_llm_common_llm_common_reg_curr_eq_mark_q_3_0_I_18 ( + .I0(com_llm_llm_common_llm_common_reg_hi_water_mark[4]), + .I1(com_llm_llm_common_llm_common_reg_hi_water_mark[5]), + .I2(com_llm_llm_common_llm_common_reg_reg_tx_curr_tsn[4]), + .I3(com_llm_llm_common_llm_common_reg_reg_tx_curr_tsn[5]), + .O(com_llm_llm_common_llm_common_reg_N_35_1) + ); + defparam com_llm_llm_common_llm_common_reg_curr_eq_mark_q_3_0_I_9.INIT = 16'h8421; + LUT4 com_llm_llm_common_llm_common_reg_curr_eq_mark_q_3_0_I_9 ( + .I0(com_llm_llm_common_llm_common_reg_hi_water_mark[0]), + .I1(com_llm_llm_common_llm_common_reg_hi_water_mark[1]), + .I2(com_llm_llm_common_llm_common_reg_reg_tx_curr_tsn[0]), + .I3(com_llm_llm_common_llm_common_reg_reg_tx_curr_tsn[1]), + .O(com_llm_llm_common_llm_common_reg_N_43_1) + ); + defparam com_llm_llm_common_llm_common_reg_next_eq_mark_q_3_0_I_54.INIT = 16'h8421; + LUT4 com_llm_llm_common_llm_common_reg_next_eq_mark_q_3_0_I_54 ( + .I0(com_llm_llm_common_llm_common_reg_hi_water_mark[2]), + .I1(com_llm_llm_common_llm_common_reg_hi_water_mark[3]), + .I2(com_llm_llm_common_llm_common_reg_reg_tx_next_tsn[2]), + .I3(com_llm_llm_common_llm_common_reg_reg_tx_next_tsn[3]), + .O(com_llm_llm_common_llm_common_reg_N_3_0) + ); + defparam com_llm_llm_common_llm_common_reg_next_eq_mark_q_3_0_I_45.INIT = 16'h8421; + LUT4 com_llm_llm_common_llm_common_reg_next_eq_mark_q_3_0_I_45 ( + .I0(com_llm_llm_common_llm_common_reg_hi_water_mark[8]), + .I1(com_llm_llm_common_llm_common_reg_hi_water_mark[9]), + .I2(com_llm_llm_common_llm_common_reg_reg_tx_next_tsn[8]), + .I3(com_llm_llm_common_llm_common_reg_reg_tx_next_tsn[9]), + .O(com_llm_llm_common_llm_common_reg_N_11_0) + ); + defparam com_llm_llm_common_llm_common_reg_next_eq_mark_q_3_0_I_36.INIT = 16'h8421; + LUT4 com_llm_llm_common_llm_common_reg_next_eq_mark_q_3_0_I_36 ( + .I0(com_llm_llm_common_llm_common_reg_hi_water_mark[6]), + .I1(com_llm_llm_common_llm_common_reg_hi_water_mark[7]), + .I2(com_llm_llm_common_llm_common_reg_reg_tx_next_tsn[6]), + .I3(com_llm_llm_common_llm_common_reg_reg_tx_next_tsn[7]), + .O(com_llm_llm_common_llm_common_reg_N_19_0) + ); + defparam com_llm_llm_common_llm_common_reg_next_eq_mark_q_3_0_I_18.INIT = 16'h8421; + LUT4 com_llm_llm_common_llm_common_reg_next_eq_mark_q_3_0_I_18 ( + .I0(com_llm_llm_common_llm_common_reg_hi_water_mark[4]), + .I1(com_llm_llm_common_llm_common_reg_hi_water_mark[5]), + .I2(com_llm_llm_common_llm_common_reg_reg_tx_next_tsn[4]), + .I3(com_llm_llm_common_llm_common_reg_reg_tx_next_tsn[5]), + .O(com_llm_llm_common_llm_common_reg_N_35_0) + ); + defparam com_llm_llm_common_llm_common_reg_next_eq_mark_q_3_0_I_9.INIT = 16'h8421; + LUT4 com_llm_llm_common_llm_common_reg_next_eq_mark_q_3_0_I_9 ( + .I0(com_llm_llm_common_llm_common_reg_hi_water_mark[0]), + .I1(com_llm_llm_common_llm_common_reg_hi_water_mark[1]), + .I2(com_llm_llm_common_llm_common_reg_reg_tx_next_tsn[0]), + .I3(com_llm_llm_common_llm_common_reg_reg_tx_next_tsn[1]), + .O(com_llm_llm_common_llm_common_reg_N_43_0) + ); + defparam com_llm_llm_common_llm_common_reg_rx_tsn_eq_sent_tsn_3_0_I_54.INIT = 16'h8421; + LUT4 com_llm_llm_common_llm_common_reg_rx_tsn_eq_sent_tsn_3_0_I_54 ( + .I0(com_llm_reg_rx_dllp_tsn[2]), + .I1(com_llm_reg_rx_dllp_tsn[3]), + .I2(com_lnk_ttrans_seq[2]), + .I3(com_lnk_ttrans_seq[3]), + .O(com_llm_llm_common_llm_common_reg_N_3) + ); + defparam com_llm_llm_common_llm_common_reg_rx_tsn_eq_sent_tsn_3_0_I_45.INIT = 16'h8421; + LUT4 com_llm_llm_common_llm_common_reg_rx_tsn_eq_sent_tsn_3_0_I_45 ( + .I0(com_llm_reg_rx_dllp_tsn[8]), + .I1(com_llm_reg_rx_dllp_tsn[9]), + .I2(com_lnk_ttrans_seq[8]), + .I3(com_lnk_ttrans_seq[9]), + .O(com_llm_llm_common_llm_common_reg_N_11) + ); + defparam com_llm_llm_common_llm_common_reg_rx_tsn_eq_sent_tsn_3_0_I_36.INIT = 16'h8421; + LUT4 com_llm_llm_common_llm_common_reg_rx_tsn_eq_sent_tsn_3_0_I_36 ( + .I0(com_llm_reg_rx_dllp_tsn[6]), + .I1(com_llm_reg_rx_dllp_tsn[7]), + .I2(com_lnk_ttrans_seq[6]), + .I3(com_lnk_ttrans_seq[7]), + .O(com_llm_llm_common_llm_common_reg_N_19) + ); + defparam com_llm_llm_common_llm_common_reg_rx_tsn_eq_sent_tsn_3_0_I_18.INIT = 16'h8421; + LUT4 com_llm_llm_common_llm_common_reg_rx_tsn_eq_sent_tsn_3_0_I_18 ( + .I0(com_llm_reg_rx_dllp_tsn[4]), + .I1(com_llm_reg_rx_dllp_tsn[5]), + .I2(com_lnk_ttrans_seq[4]), + .I3(com_lnk_ttrans_seq[5]), + .O(com_llm_llm_common_llm_common_reg_N_35) + ); + defparam com_llm_llm_common_llm_common_reg_rx_tsn_eq_sent_tsn_3_0_I_9.INIT = 16'h8421; + LUT4 com_llm_llm_common_llm_common_reg_rx_tsn_eq_sent_tsn_3_0_I_9 ( + .I0(com_llm_reg_rx_dllp_tsn[0]), + .I1(com_llm_reg_rx_dllp_tsn[1]), + .I2(com_lnk_ttrans_seq[0]), + .I3(com_lnk_ttrans_seq[1]), + .O(com_llm_llm_common_llm_common_reg_N_43) + ); + VCC com_llm_llm_common_llm_common_reg_compare_1_VCC ( + .P(com_llm_llm_common_llm_common_reg_compare_1_VCC_3062) + ); + MUXCY_L com_llm_llm_common_llm_common_reg_compare_1_result_cry_0 ( + .CI(com_llm_llm_common_llm_common_reg_compare_1_VCC_3062), + .DI(com_llm_llm_common_llm_common_reg_hi_water_mark[0]), + .LO(com_llm_llm_common_llm_common_reg_compare_1_result_cry_0_3063), + .S(com_llm_llm_common_llm_common_reg_compare_1_result_axb_0_3085) + ); + MUXCY_L com_llm_llm_common_llm_common_reg_compare_1_result_cry_1 ( + .CI(com_llm_llm_common_llm_common_reg_compare_1_result_cry_0_3063), + .DI(com_llm_llm_common_llm_common_reg_hi_water_mark[1]), + .LO(com_llm_llm_common_llm_common_reg_compare_1_result_cry_1_3064), + .S(com_llm_llm_common_llm_common_reg_compare_1_result_axb_1_3084) + ); + MUXCY_L com_llm_llm_common_llm_common_reg_compare_1_result_cry_2 ( + .CI(com_llm_llm_common_llm_common_reg_compare_1_result_cry_1_3064), + .DI(com_llm_llm_common_llm_common_reg_hi_water_mark[2]), + .LO(com_llm_llm_common_llm_common_reg_compare_1_result_cry_2_3065), + .S(com_llm_llm_common_llm_common_reg_compare_1_result_axb_2_3083) + ); + MUXCY_L com_llm_llm_common_llm_common_reg_compare_1_result_cry_3 ( + .CI(com_llm_llm_common_llm_common_reg_compare_1_result_cry_2_3065), + .DI(com_llm_llm_common_llm_common_reg_hi_water_mark[3]), + .LO(com_llm_llm_common_llm_common_reg_compare_1_result_cry_3_3066), + .S(com_llm_llm_common_llm_common_reg_compare_1_result_axb_3_3082) + ); + MUXCY_L com_llm_llm_common_llm_common_reg_compare_1_result_cry_4 ( + .CI(com_llm_llm_common_llm_common_reg_compare_1_result_cry_3_3066), + .DI(com_llm_llm_common_llm_common_reg_hi_water_mark[4]), + .LO(com_llm_llm_common_llm_common_reg_compare_1_result_cry_4_3067), + .S(com_llm_llm_common_llm_common_reg_compare_1_result_axb_4_3081) + ); + MUXCY_L com_llm_llm_common_llm_common_reg_compare_1_result_cry_5 ( + .CI(com_llm_llm_common_llm_common_reg_compare_1_result_cry_4_3067), + .DI(com_llm_llm_common_llm_common_reg_hi_water_mark[5]), + .LO(com_llm_llm_common_llm_common_reg_compare_1_result_cry_5_3068), + .S(com_llm_llm_common_llm_common_reg_compare_1_result_axb_5_3080) + ); + MUXCY_L com_llm_llm_common_llm_common_reg_compare_1_result_cry_6 ( + .CI(com_llm_llm_common_llm_common_reg_compare_1_result_cry_5_3068), + .DI(com_llm_llm_common_llm_common_reg_hi_water_mark[6]), + .LO(com_llm_llm_common_llm_common_reg_compare_1_result_cry_6_3069), + .S(com_llm_llm_common_llm_common_reg_compare_1_result_axb_6_3079) + ); + MUXCY_L com_llm_llm_common_llm_common_reg_compare_1_result_cry_7 ( + .CI(com_llm_llm_common_llm_common_reg_compare_1_result_cry_6_3069), + .DI(com_llm_llm_common_llm_common_reg_hi_water_mark[7]), + .LO(com_llm_llm_common_llm_common_reg_compare_1_result_cry_7_3070), + .S(com_llm_llm_common_llm_common_reg_compare_1_result_axb_7_3078) + ); + MUXCY_L com_llm_llm_common_llm_common_reg_compare_1_result_cry_8 ( + .CI(com_llm_llm_common_llm_common_reg_compare_1_result_cry_7_3070), + .DI(com_llm_llm_common_llm_common_reg_hi_water_mark[8]), + .LO(com_llm_llm_common_llm_common_reg_compare_1_result_cry_8_3071), + .S(com_llm_llm_common_llm_common_reg_compare_1_result_axb_8_3077) + ); + MUXCY_L com_llm_llm_common_llm_common_reg_compare_1_result_cry_9 ( + .CI(com_llm_llm_common_llm_common_reg_compare_1_result_cry_8_3071), + .DI(com_llm_llm_common_llm_common_reg_hi_water_mark[9]), + .LO(com_llm_llm_common_llm_common_reg_compare_1_result_cry_9_3072), + .S(com_llm_llm_common_llm_common_reg_compare_1_result_axb_9_3076) + ); + MUXCY_L com_llm_llm_common_llm_common_reg_compare_1_result_cry_10 ( + .CI(com_llm_llm_common_llm_common_reg_compare_1_result_cry_9_3072), + .DI(com_llm_llm_common_llm_common_reg_hi_water_mark[10]), + .LO(com_llm_llm_common_llm_common_reg_compare_1_result_cry_10_3073), + .S(com_llm_llm_common_llm_common_reg_compare_1_result_axb_10_3075) + ); + XORCY com_llm_llm_common_llm_common_reg_compare_1_result_s_11 ( + .CI(com_llm_llm_common_llm_common_reg_compare_1_result_cry_10_3073), + .LI(com_llm_llm_common_llm_common_reg_compare_1_result_axb_11_3074), + .O(com_llm_llm_common_llm_common_reg_compare_1_result[11]) + ); + defparam com_llm_llm_common_llm_common_reg_compare_1_result_axb_11.INIT = 4'h9; + LUT2 com_llm_llm_common_llm_common_reg_compare_1_result_axb_11 ( + .I0(com_llm_llm_common_llm_common_reg_hi_water_mark[11]), + .I1(com_llm_reg_rx_dllp_tsn[11]), + .O(com_llm_llm_common_llm_common_reg_compare_1_result_axb_11_3074) + ); + defparam com_llm_llm_common_llm_common_reg_compare_1_result_i_11_.INIT = 4'h1; + LUT1_L com_llm_llm_common_llm_common_reg_compare_1_result_i_11_ ( + .I0(com_llm_llm_common_llm_common_reg_compare_1_result[11]), + .LO(com_llm_llm_common_llm_common_reg_result_i_0[11]) + ); + defparam com_llm_llm_common_llm_common_reg_compare_1_result_axb_10.INIT = 4'h9; + LUT2 com_llm_llm_common_llm_common_reg_compare_1_result_axb_10 ( + .I0(com_llm_llm_common_llm_common_reg_hi_water_mark[10]), + .I1(com_llm_reg_rx_dllp_tsn[10]), + .O(com_llm_llm_common_llm_common_reg_compare_1_result_axb_10_3075) + ); + defparam com_llm_llm_common_llm_common_reg_compare_1_result_axb_9.INIT = 4'h9; + LUT2 com_llm_llm_common_llm_common_reg_compare_1_result_axb_9 ( + .I0(com_llm_llm_common_llm_common_reg_hi_water_mark[9]), + .I1(com_llm_reg_rx_dllp_tsn[9]), + .O(com_llm_llm_common_llm_common_reg_compare_1_result_axb_9_3076) + ); + defparam com_llm_llm_common_llm_common_reg_compare_1_result_axb_8.INIT = 4'h9; + LUT2 com_llm_llm_common_llm_common_reg_compare_1_result_axb_8 ( + .I0(com_llm_llm_common_llm_common_reg_hi_water_mark[8]), + .I1(com_llm_reg_rx_dllp_tsn[8]), + .O(com_llm_llm_common_llm_common_reg_compare_1_result_axb_8_3077) + ); + defparam com_llm_llm_common_llm_common_reg_compare_1_result_axb_7.INIT = 4'h9; + LUT2 com_llm_llm_common_llm_common_reg_compare_1_result_axb_7 ( + .I0(com_llm_llm_common_llm_common_reg_hi_water_mark[7]), + .I1(com_llm_reg_rx_dllp_tsn[7]), + .O(com_llm_llm_common_llm_common_reg_compare_1_result_axb_7_3078) + ); + defparam com_llm_llm_common_llm_common_reg_compare_1_result_axb_6.INIT = 4'h9; + LUT2 com_llm_llm_common_llm_common_reg_compare_1_result_axb_6 ( + .I0(com_llm_llm_common_llm_common_reg_hi_water_mark[6]), + .I1(com_llm_reg_rx_dllp_tsn[6]), + .O(com_llm_llm_common_llm_common_reg_compare_1_result_axb_6_3079) + ); + defparam com_llm_llm_common_llm_common_reg_compare_1_result_axb_5.INIT = 4'h9; + LUT2 com_llm_llm_common_llm_common_reg_compare_1_result_axb_5 ( + .I0(com_llm_llm_common_llm_common_reg_hi_water_mark[5]), + .I1(com_llm_reg_rx_dllp_tsn[5]), + .O(com_llm_llm_common_llm_common_reg_compare_1_result_axb_5_3080) + ); + defparam com_llm_llm_common_llm_common_reg_compare_1_result_axb_4.INIT = 4'h9; + LUT2 com_llm_llm_common_llm_common_reg_compare_1_result_axb_4 ( + .I0(com_llm_llm_common_llm_common_reg_hi_water_mark[4]), + .I1(com_llm_reg_rx_dllp_tsn[4]), + .O(com_llm_llm_common_llm_common_reg_compare_1_result_axb_4_3081) + ); + defparam com_llm_llm_common_llm_common_reg_compare_1_result_axb_3.INIT = 4'h9; + LUT2 com_llm_llm_common_llm_common_reg_compare_1_result_axb_3 ( + .I0(com_llm_llm_common_llm_common_reg_hi_water_mark[3]), + .I1(com_llm_reg_rx_dllp_tsn[3]), + .O(com_llm_llm_common_llm_common_reg_compare_1_result_axb_3_3082) + ); + defparam com_llm_llm_common_llm_common_reg_compare_1_result_axb_2.INIT = 4'h9; + LUT2 com_llm_llm_common_llm_common_reg_compare_1_result_axb_2 ( + .I0(com_llm_llm_common_llm_common_reg_hi_water_mark[2]), + .I1(com_llm_reg_rx_dllp_tsn[2]), + .O(com_llm_llm_common_llm_common_reg_compare_1_result_axb_2_3083) + ); + defparam com_llm_llm_common_llm_common_reg_compare_1_result_axb_1.INIT = 4'h9; + LUT2 com_llm_llm_common_llm_common_reg_compare_1_result_axb_1 ( + .I0(com_llm_llm_common_llm_common_reg_hi_water_mark[1]), + .I1(com_llm_reg_rx_dllp_tsn[1]), + .O(com_llm_llm_common_llm_common_reg_compare_1_result_axb_1_3084) + ); + defparam com_llm_llm_common_llm_common_reg_compare_1_result_axb_0.INIT = 4'h9; + LUT2 com_llm_llm_common_llm_common_reg_compare_1_result_axb_0 ( + .I0(com_llm_llm_common_llm_common_reg_hi_water_mark[0]), + .I1(com_llm_reg_rx_dllp_tsn[0]), + .O(com_llm_llm_common_llm_common_reg_compare_1_result_axb_0_3085) + ); + VCC com_llm_llm_common_llm_common_reg_compare_2_VCC ( + .P(com_llm_llm_common_llm_common_reg_compare_2_VCC_3086) + ); + MUXCY_L com_llm_llm_common_llm_common_reg_compare_2_result_cry_0 ( + .CI(com_llm_llm_common_llm_common_reg_compare_2_VCC_3086), + .DI(com_llm_reg_rx_dllp_tsn[0]), + .LO(com_llm_llm_common_llm_common_reg_compare_2_result_cry_0_3087), + .S(com_llm_llm_common_llm_common_reg_compare_2_result_axb_0_3109) + ); + MUXCY_L com_llm_llm_common_llm_common_reg_compare_2_result_cry_1 ( + .CI(com_llm_llm_common_llm_common_reg_compare_2_result_cry_0_3087), + .DI(com_llm_reg_rx_dllp_tsn[1]), + .LO(com_llm_llm_common_llm_common_reg_compare_2_result_cry_1_3088), + .S(com_llm_llm_common_llm_common_reg_compare_2_result_axb_1_3108) + ); + MUXCY_L com_llm_llm_common_llm_common_reg_compare_2_result_cry_2 ( + .CI(com_llm_llm_common_llm_common_reg_compare_2_result_cry_1_3088), + .DI(com_llm_reg_rx_dllp_tsn[2]), + .LO(com_llm_llm_common_llm_common_reg_compare_2_result_cry_2_3089), + .S(com_llm_llm_common_llm_common_reg_compare_2_result_axb_2_3107) + ); + MUXCY_L com_llm_llm_common_llm_common_reg_compare_2_result_cry_3 ( + .CI(com_llm_llm_common_llm_common_reg_compare_2_result_cry_2_3089), + .DI(com_llm_reg_rx_dllp_tsn[3]), + .LO(com_llm_llm_common_llm_common_reg_compare_2_result_cry_3_3090), + .S(com_llm_llm_common_llm_common_reg_compare_2_result_axb_3_3106) + ); + MUXCY_L com_llm_llm_common_llm_common_reg_compare_2_result_cry_4 ( + .CI(com_llm_llm_common_llm_common_reg_compare_2_result_cry_3_3090), + .DI(com_llm_reg_rx_dllp_tsn[4]), + .LO(com_llm_llm_common_llm_common_reg_compare_2_result_cry_4_3091), + .S(com_llm_llm_common_llm_common_reg_compare_2_result_axb_4_3105) + ); + MUXCY_L com_llm_llm_common_llm_common_reg_compare_2_result_cry_5 ( + .CI(com_llm_llm_common_llm_common_reg_compare_2_result_cry_4_3091), + .DI(com_llm_reg_rx_dllp_tsn[5]), + .LO(com_llm_llm_common_llm_common_reg_compare_2_result_cry_5_3092), + .S(com_llm_llm_common_llm_common_reg_compare_2_result_axb_5_3104) + ); + MUXCY_L com_llm_llm_common_llm_common_reg_compare_2_result_cry_6 ( + .CI(com_llm_llm_common_llm_common_reg_compare_2_result_cry_5_3092), + .DI(com_llm_reg_rx_dllp_tsn[6]), + .LO(com_llm_llm_common_llm_common_reg_compare_2_result_cry_6_3093), + .S(com_llm_llm_common_llm_common_reg_compare_2_result_axb_6_3103) + ); + MUXCY_L com_llm_llm_common_llm_common_reg_compare_2_result_cry_7 ( + .CI(com_llm_llm_common_llm_common_reg_compare_2_result_cry_6_3093), + .DI(com_llm_reg_rx_dllp_tsn[7]), + .LO(com_llm_llm_common_llm_common_reg_compare_2_result_cry_7_3094), + .S(com_llm_llm_common_llm_common_reg_compare_2_result_axb_7_3102) + ); + MUXCY_L com_llm_llm_common_llm_common_reg_compare_2_result_cry_8 ( + .CI(com_llm_llm_common_llm_common_reg_compare_2_result_cry_7_3094), + .DI(com_llm_reg_rx_dllp_tsn[8]), + .LO(com_llm_llm_common_llm_common_reg_compare_2_result_cry_8_3095), + .S(com_llm_llm_common_llm_common_reg_compare_2_result_axb_8_3101) + ); + MUXCY_L com_llm_llm_common_llm_common_reg_compare_2_result_cry_9 ( + .CI(com_llm_llm_common_llm_common_reg_compare_2_result_cry_8_3095), + .DI(com_llm_reg_rx_dllp_tsn[9]), + .LO(com_llm_llm_common_llm_common_reg_compare_2_result_cry_9_3096), + .S(com_llm_llm_common_llm_common_reg_compare_2_result_axb_9_3100) + ); + MUXCY_L com_llm_llm_common_llm_common_reg_compare_2_result_cry_10 ( + .CI(com_llm_llm_common_llm_common_reg_compare_2_result_cry_9_3096), + .DI(com_llm_reg_rx_dllp_tsn[10]), + .LO(com_llm_llm_common_llm_common_reg_compare_2_result_cry_10_3097), + .S(com_llm_llm_common_llm_common_reg_compare_2_result_axb_10_3099) + ); + XORCY com_llm_llm_common_llm_common_reg_compare_2_result_s_11 ( + .CI(com_llm_llm_common_llm_common_reg_compare_2_result_cry_10_3097), + .LI(com_llm_llm_common_llm_common_reg_compare_2_result_axb_11_3098), + .O(com_llm_llm_common_llm_common_reg_compare_2_result[11]) + ); + defparam com_llm_llm_common_llm_common_reg_compare_2_result_axb_11.INIT = 4'h9; + LUT2 com_llm_llm_common_llm_common_reg_compare_2_result_axb_11 ( + .I0(com_llm_reg_rx_dllp_tsn[11]), + .I1(com_lnk_tupdate_seq[11]), + .O(com_llm_llm_common_llm_common_reg_compare_2_result_axb_11_3098) + ); + defparam com_llm_llm_common_llm_common_reg_compare_2_result_i_11_.INIT = 4'h1; + LUT1_L com_llm_llm_common_llm_common_reg_compare_2_result_i_11_ ( + .I0(com_llm_llm_common_llm_common_reg_compare_2_result[11]), + .LO(com_llm_llm_common_llm_common_reg_result_i[11]) + ); + defparam com_llm_llm_common_llm_common_reg_compare_2_result_axb_10.INIT = 4'h9; + LUT2 com_llm_llm_common_llm_common_reg_compare_2_result_axb_10 ( + .I0(com_llm_reg_rx_dllp_tsn[10]), + .I1(com_lnk_tupdate_seq[10]), + .O(com_llm_llm_common_llm_common_reg_compare_2_result_axb_10_3099) + ); + defparam com_llm_llm_common_llm_common_reg_compare_2_result_axb_9.INIT = 4'h9; + LUT2 com_llm_llm_common_llm_common_reg_compare_2_result_axb_9 ( + .I0(com_llm_reg_rx_dllp_tsn[9]), + .I1(com_lnk_tupdate_seq[9]), + .O(com_llm_llm_common_llm_common_reg_compare_2_result_axb_9_3100) + ); + defparam com_llm_llm_common_llm_common_reg_compare_2_result_axb_8.INIT = 4'h9; + LUT2 com_llm_llm_common_llm_common_reg_compare_2_result_axb_8 ( + .I0(com_llm_reg_rx_dllp_tsn[8]), + .I1(com_lnk_tupdate_seq[8]), + .O(com_llm_llm_common_llm_common_reg_compare_2_result_axb_8_3101) + ); + defparam com_llm_llm_common_llm_common_reg_compare_2_result_axb_7.INIT = 4'h9; + LUT2 com_llm_llm_common_llm_common_reg_compare_2_result_axb_7 ( + .I0(com_llm_reg_rx_dllp_tsn[7]), + .I1(com_lnk_tupdate_seq[7]), + .O(com_llm_llm_common_llm_common_reg_compare_2_result_axb_7_3102) + ); + defparam com_llm_llm_common_llm_common_reg_compare_2_result_axb_6.INIT = 4'h9; + LUT2 com_llm_llm_common_llm_common_reg_compare_2_result_axb_6 ( + .I0(com_llm_reg_rx_dllp_tsn[6]), + .I1(com_lnk_tupdate_seq[6]), + .O(com_llm_llm_common_llm_common_reg_compare_2_result_axb_6_3103) + ); + defparam com_llm_llm_common_llm_common_reg_compare_2_result_axb_5.INIT = 4'h9; + LUT2 com_llm_llm_common_llm_common_reg_compare_2_result_axb_5 ( + .I0(com_llm_reg_rx_dllp_tsn[5]), + .I1(com_lnk_tupdate_seq[5]), + .O(com_llm_llm_common_llm_common_reg_compare_2_result_axb_5_3104) + ); + defparam com_llm_llm_common_llm_common_reg_compare_2_result_axb_4.INIT = 4'h9; + LUT2 com_llm_llm_common_llm_common_reg_compare_2_result_axb_4 ( + .I0(com_llm_reg_rx_dllp_tsn[4]), + .I1(com_lnk_tupdate_seq[4]), + .O(com_llm_llm_common_llm_common_reg_compare_2_result_axb_4_3105) + ); + defparam com_llm_llm_common_llm_common_reg_compare_2_result_axb_3.INIT = 4'h9; + LUT2 com_llm_llm_common_llm_common_reg_compare_2_result_axb_3 ( + .I0(com_llm_reg_rx_dllp_tsn[3]), + .I1(com_lnk_tupdate_seq[3]), + .O(com_llm_llm_common_llm_common_reg_compare_2_result_axb_3_3106) + ); + defparam com_llm_llm_common_llm_common_reg_compare_2_result_axb_2.INIT = 4'h9; + LUT2 com_llm_llm_common_llm_common_reg_compare_2_result_axb_2 ( + .I0(com_llm_reg_rx_dllp_tsn[2]), + .I1(com_lnk_tupdate_seq[2]), + .O(com_llm_llm_common_llm_common_reg_compare_2_result_axb_2_3107) + ); + defparam com_llm_llm_common_llm_common_reg_compare_2_result_axb_1.INIT = 4'h9; + LUT2 com_llm_llm_common_llm_common_reg_compare_2_result_axb_1 ( + .I0(com_llm_reg_rx_dllp_tsn[1]), + .I1(com_lnk_tupdate_seq[1]), + .O(com_llm_llm_common_llm_common_reg_compare_2_result_axb_1_3108) + ); + defparam com_llm_llm_common_llm_common_reg_compare_2_result_axb_0.INIT = 4'h9; + LUT2 com_llm_llm_common_llm_common_reg_compare_2_result_axb_0 ( + .I0(com_llm_reg_rx_dllp_tsn[0]), + .I1(com_lnk_tupdate_seq[0]), + .O(com_llm_llm_common_llm_common_reg_compare_2_result_axb_0_3109) + ); + defparam com_llm_llm_common_llm_common_reg_llm_ack_nak_buf_ack_pending_7_iv_0_0_0_o3.INIT = 4'h1; + LUT2 com_llm_llm_common_llm_common_reg_llm_ack_nak_buf_ack_pending_7_iv_0_0_0_o3 ( + .I0(com_llm_llm_common_llm_common_reg_reg_rx_dllp_ack_vld_q_2985), + .I1(com_llm_llm_common_llm_common_reg_reg_rx_dllp_nak_vld_q_2984), + .O(com_llm_llm_common_llm_common_reg_N_56212_i) + ); + defparam com_llm_llm_common_llm_common_reg_llm_ack_nak_buf_nak_pending_8_0_a2_0_a3_0_a2_2.INIT = 4'h1; + LUT2 com_llm_llm_common_llm_common_reg_llm_ack_nak_buf_nak_pending_8_0_a2_0_a3_0_a2_2 ( + .I0(com_llm_llm_common_llm_common_reg_nak_pending), + .I1(com_reg_tx_update_retry_int), + .O(com_llm_llm_common_llm_common_reg_nak_pending_8_2) + ); + defparam com_llm_llm_common_llm_common_reg_llm_ack_nak_buf_un1_clr_ack_buffer_i_0_0_a2_0.INIT = 4'h8; + LUT2 com_llm_llm_common_llm_common_reg_llm_ack_nak_buf_un1_clr_ack_buffer_i_0_0_a2_0 ( + .I0(com_llm_llm_common_llm_common_reg_N_58798_1), + .I1(com_llm_llm_common_llm_common_reg_reg_rx_dllp_ack_vld_q_2985), + .O(com_llm_llm_common_llm_common_reg_N_58792) + ); + defparam com_llm_llm_common_llm_common_reg_llm_ack_nak_buf_nak_pending_8_0_a2_0_a3_0_a2_4.INIT = 16'h8000; + LUT4 com_llm_llm_common_llm_common_reg_llm_ack_nak_buf_nak_pending_8_0_a2_0_a3_0_a2_4 ( + .I0(com_llm_llm_common_llm_common_reg_ANSeqNum_AckdSeq_wire_2987), + .I1(com_llm_llm_common_llm_common_reg_NxtTxTSN_ANSeqNum_wire_2986), + .I2(com_llm_llm_common_llm_common_reg_nak_pending_8_2), + .I3(com_llm_llm_common_llm_common_reg_reg_rx_dllp_nak_vld_q_2984), + .O(com_llm_llm_common_llm_common_reg_llm_ack_nak_buf_nak_pending_8_4) + ); + defparam com_llm_llm_common_llm_common_reg_llm_ack_nak_buf_N_85484_i.INIT = 8'hFE; + LUT3 com_llm_llm_common_llm_common_reg_llm_ack_nak_buf_N_85484_i ( + .I0(com_llm_link_status[0]), + .I1(com_llm_llm_common_llm_common_reg_llm_ack_nak_buf_nak_pending_8_4), + .I2(com_reg_tx_update_retry_int), + .O(com_llm_llm_common_llm_common_reg_llm_ack_nak_buf_N_85484_i_3111) + ); + defparam com_llm_llm_common_llm_common_reg_llm_ack_nak_buf_acknak_state_q_5_0_a2_0_a2_0_a2_0_a2_1_.INIT = 4'h4; + LUT2_L com_llm_llm_common_llm_common_reg_llm_ack_nak_buf_acknak_state_q_5_0_a2_0_a2_0_a2_0_a2_1_ ( + .I0(com_llm_link_status[0]), + .I1(com_reg_tx_update_ack), + .LO(com_llm_llm_common_llm_common_reg_llm_ack_nak_buf_acknak_state_q_5[1]) + ); + defparam com_llm_llm_common_llm_common_reg_llm_ack_nak_buf_nak_pending_8_0_a2_0_a3_0_a2.INIT = 16'h0004; + LUT4_L com_llm_llm_common_llm_common_reg_llm_ack_nak_buf_nak_pending_8_0_a2_0_a3_0_a2 ( + .I0(com_llm_link_status[0]), + .I1(com_llm_llm_common_llm_common_reg_llm_ack_nak_buf_nak_pending_8_4), + .I2(com_llm_llm_common_llm_common_reg_rx_tsn_eq_sent_tsn_2991), + .I3(com_llm_llm_common_llm_common_reg_tmp_result[11]), + .LO(com_llm_llm_common_llm_common_reg_llm_ack_nak_buf_nak_pending_8) + ); + defparam com_llm_llm_common_llm_common_reg_llm_ack_nak_buf_ack_pending_7_iv_0_0_0_1.INIT = 16'h5F57; + LUT4 com_llm_llm_common_llm_common_reg_llm_ack_nak_buf_ack_pending_7_iv_0_0_0_1 ( + .I0(com_llm_llm_common_llm_common_reg_ANSeqNum_AckdSeq_wire_2987), + .I1(com_llm_llm_common_llm_common_reg_reg_rx_dllp_ack_vld_q_2985), + .I2(com_llm_llm_common_llm_common_reg_rx_tsn_eq_sent_tsn_2991), + .I3(com_llm_llm_common_llm_common_reg_tmp_result[11]), + .O(com_llm_llm_common_llm_common_reg_llm_ack_nak_buf_ack_pending_7_iv_0_0_0_1_3113) + ); + defparam com_llm_llm_common_llm_common_reg_llm_ack_nak_buf_N_85480_i_1.INIT = 16'h1333; + LUT4 com_llm_llm_common_llm_common_reg_llm_ack_nak_buf_N_85480_i_1 ( + .I0(com_llm_llm_common_llm_common_reg_N_58798_1), + .I1(com_llm_link_status[0]), + .I2(com_llm_llm_common_llm_common_reg_reg_rx_dllp_nak_vld_q_2984), + .I3(com_llm_llm_common_llm_common_reg_rx_tsn_eq_sent_tsn_2991), + .O(com_llm_llm_common_llm_common_reg_llm_ack_nak_buf_N_85480_i_1_3110) + ); + defparam com_llm_llm_common_llm_common_reg_llm_ack_nak_buf_N_85480_i.INIT = 16'hBFBB; + LUT4 com_llm_llm_common_llm_common_reg_llm_ack_nak_buf_N_85480_i ( + .I0(com_llm_llm_common_llm_common_reg_N_58792), + .I1(com_llm_llm_common_llm_common_reg_llm_ack_nak_buf_N_85480_i_1_3110), + .I2(com_llm_llm_common_llm_common_reg_llm_ack_nak_buf_acknak_state_q[1]), + .I3(com_reg_tx_update_ack), + .O(com_llm_llm_common_llm_common_reg_llm_ack_nak_buf_N_85480_i_3112) + ); + FDC com_llm_llm_common_llm_common_reg_llm_ack_nak_buf_acknak_state_q_1_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_common_llm_common_reg_llm_ack_nak_buf_acknak_state_q_5[1]), + .Q(com_llm_llm_common_llm_common_reg_llm_ack_nak_buf_acknak_state_q[1]), + .CLR(plm_link_up_i) + ); + FDCE com_llm_llm_common_llm_common_reg_llm_ack_nak_buf_nak_pending ( + .CE(com_llm_llm_common_llm_common_reg_llm_ack_nak_buf_N_85484_i_3111), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_common_llm_common_reg_llm_ack_nak_buf_nak_pending_8), + .Q(com_llm_llm_common_llm_common_reg_nak_pending), + .CLR(plm_link_up_i) + ); + FDCE com_llm_llm_common_llm_common_reg_llm_ack_nak_buf_ack_pending ( + .CE(com_llm_llm_common_llm_common_reg_llm_ack_nak_buf_N_85480_i_3112), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_common_llm_common_reg_llm_ack_nak_buf_N_9920_i), + .Q(com_llm_llm_common_llm_common_reg_ack_pending), + .CLR(plm_link_up_i) + ); + defparam com_llm_llm_common_llm_common_reg_llm_ack_nak_buf_ack_pending_7_iv_0_0_0.INIT = 16'h0002; + LUT4_L com_llm_llm_common_llm_common_reg_llm_ack_nak_buf_ack_pending_7_iv_0_0_0 ( + .I0(com_llm_llm_common_llm_common_reg_N_22173_i), + .I1(com_llm_link_status[0]), + .I2(com_llm_llm_common_llm_common_reg_ANSeqNum_Eq_AckdSeq_2988), + .I3(com_llm_llm_common_llm_common_reg_llm_ack_nak_buf_ack_pending_7_iv_0_0_0_1_3113), + .LO(com_llm_llm_common_llm_common_reg_llm_ack_nak_buf_N_9920_i) + ); + defparam com_llm_llm_common_llm_common_reg_llm_ack_nak_fsm_CS_ACKNAKFSM_cs_acknakfsm_5_0_a2_0_a3_0_a2_1_1_.INIT = 4'h1; + LUT2 com_llm_llm_common_llm_common_reg_llm_ack_nak_fsm_CS_ACKNAKFSM_cs_acknakfsm_5_0_a2_0_a3_0_a2_1_1_ ( + .I0(com_llm_llm_common_llm_common_reg_nak_pending), + .I1(com_llm_llm_common_llm_common_reg_replay_timeout_flag), + .O(com_llm_llm_common_llm_common_reg_llm_ack_nak_fsm_cs_acknakfsm_5_1[1]) + ); + defparam com_llm_llm_common_llm_common_reg_llm_ack_nak_fsm_CS_ACKNAKFSM_cs_acknakfsm_5_i_0_0_1_0_.INIT = 16'h0105; + LUT4 com_llm_llm_common_llm_common_reg_llm_ack_nak_fsm_CS_ACKNAKFSM_cs_acknakfsm_5_i_0_0_1_0_ ( + .I0(com_llm_link_status[0]), + .I1(com_reg_tx_update_retry_int), + .I2(com_reg_tx_update_ack), + .I3(com_lnk_tretry), + .O(com_llm_llm_common_llm_common_reg_llm_ack_nak_fsm_cs_acknakfsm_5_i_0_0_1[0]) + ); + defparam com_llm_llm_common_llm_common_reg_llm_ack_nak_fsm_CS_ACKNAKFSM_cs_acknakfsm_5_i_0_0_2_.INIT = 8'hA2; + LUT3_L com_llm_llm_common_llm_common_reg_llm_ack_nak_fsm_CS_ACKNAKFSM_cs_acknakfsm_5_i_0_0_2_ ( + .I0(com_llm_llm_common_llm_common_reg_llm_ack_nak_fsm_cs_acknakfsm_5_i_0_0_1[0]), + .I1(com_llm_llm_common_llm_common_reg_llm_ack_nak_fsm_cs_acknakfsm_5_1[1]), + .I2(com_reg_tx_update_retry_int), + .LO(com_llm_llm_common_llm_common_reg_llm_ack_nak_fsm_N_22182_i) + ); + defparam com_llm_llm_common_llm_common_reg_llm_ack_nak_fsm_CS_ACKNAKFSM_cs_acknakfsm_5_0_a2_0_a3_0_a2_1_.INIT = 16'h4000; + LUT4_L com_llm_llm_common_llm_common_reg_llm_ack_nak_fsm_CS_ACKNAKFSM_cs_acknakfsm_5_0_a2_0_a3_0_a2_1_ ( + .I0(com_llm_link_status[0]), + .I1(com_llm_llm_common_llm_common_reg_ack_pending), + .I2(com_llm_llm_common_llm_common_reg_llm_ack_nak_fsm_acknak_state[0]), + .I3(com_llm_llm_common_llm_common_reg_llm_ack_nak_fsm_cs_acknakfsm_5_1[1]), + .LO(com_llm_llm_common_llm_common_reg_llm_ack_nak_fsm_cs_acknakfsm_5[1]) + ); + defparam com_llm_llm_common_llm_common_reg_llm_ack_nak_fsm_CS_ACKNAKFSM_N_87593_i.INIT = 16'h5575; + LUT4_L com_llm_llm_common_llm_common_reg_llm_ack_nak_fsm_CS_ACKNAKFSM_N_87593_i ( + .I0(com_llm_llm_common_llm_common_reg_llm_ack_nak_fsm_cs_acknakfsm_5_i_0_0_1[0]), + .I1(com_llm_llm_common_llm_common_reg_ack_pending), + .I2(com_llm_llm_common_llm_common_reg_nak_pending_8_2), + .I3(com_llm_llm_common_llm_common_reg_replay_timeout_flag), + .LO(com_llm_llm_common_llm_common_reg_llm_ack_nak_fsm_N_87593_i) + ); + FDC com_llm_llm_common_llm_common_reg_llm_ack_nak_fsm_cs_acknakfsm_2_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_common_llm_common_reg_llm_ack_nak_fsm_N_22182_i), + .Q(com_reg_tx_update_retry_int), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_common_llm_common_reg_llm_ack_nak_fsm_cs_acknakfsm_1_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_common_llm_common_reg_llm_ack_nak_fsm_cs_acknakfsm_5[1]), + .Q(com_reg_tx_update_ack), + .CLR(plm_link_up_i) + ); + FDP com_llm_llm_common_llm_common_reg_llm_ack_nak_fsm_cs_acknakfsm_0_ ( + .PRE(plm_link_up_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_common_llm_common_reg_llm_ack_nak_fsm_N_87593_i), + .Q(com_llm_llm_common_llm_common_reg_llm_ack_nak_fsm_acknak_state[0]) + ); + VCC com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_VCC ( + .P(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_VCC_3114) + ); + GND com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_GND ( + .G(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_GND_3120) + ); + FDR com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_clear ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_N_85482_i_3119), + .Q(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_clear_3117), + .R(plm_link_up_i) + ); + FDR com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_q_0_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer[0]), + .Q(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_q[0]), + .R(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_N_10950_i_3116) + ); + FDR com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_q_1_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer[1]), + .Q(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_q[1]), + .R(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_N_10950_i_3116) + ); + FDR com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_q_2_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer[2]), + .Q(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_q[2]), + .R(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_N_10950_i_3116) + ); + FDR com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_q_3_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer[3]), + .Q(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_q[3]), + .R(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_N_10950_i_3116) + ); + FDR com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_q_4_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer[4]), + .Q(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_q[4]), + .R(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_N_10950_i_3116) + ); + FDR com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_q_5_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer[5]), + .Q(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_q[5]), + .R(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_N_10950_i_3116) + ); + FDR com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_q_6_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer[6]), + .Q(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_q[6]), + .R(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_N_10950_i_3116) + ); + FDR com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_q_7_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer[7]), + .Q(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_q[7]), + .R(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_N_10950_i_3116) + ); + FDR com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_q_8_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer[8]), + .Q(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_q[8]), + .R(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_N_10950_i_3116) + ); + FDR com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_q_9_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer[9]), + .Q(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_q[9]), + .R(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_N_10950_i_3116) + ); + FDR com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_q_10_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer[10]), + .Q(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_q[10]), + .R(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_N_10950_i_3116) + ); + FDR com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_q_11_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer[11]), + .Q(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_q[11]), + .R(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_N_10950_i_3116) + ); + FDR com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_q_12_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer[12]), + .Q(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_q[12]), + .R(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_N_10950_i_3116) + ); + FDR com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_q_13_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer[13]), + .Q(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_q[13]), + .R(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_N_10950_i_3116) + ); + FDR com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_q_14_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer[14]), + .Q(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_q[14]), + .R(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_N_10950_i_3116) + ); + FDR com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_set ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_set_3), + .Q(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_set_3115), + .R(plm_link_up_i) + ); + MUXCY_L com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_un1_diff_flag_0_I_1 ( + .CI(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_VCC_3114), + .DI(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_GND_3120), + .LO(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_data_tmp_1[0]), + .S(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_N_43) + ); + MUXCY_L com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_un1_diff_flag_0_I_10 ( + .CI(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_data_tmp_1[1]), + .DI(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_GND_3120), + .LO(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_data_tmp_1[2]), + .S(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_N_35) + ); + MUXCY_L com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_un1_diff_flag_0_I_28 ( + .CI(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_data_tmp_1[2]), + .DI(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_GND_3120), + .LO(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_data_tmp_1[3]), + .S(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_N_19) + ); + MUXCY_L com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_un1_diff_flag_0_I_37 ( + .CI(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_data_tmp_1[3]), + .DI(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_GND_3120), + .LO(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_data_tmp[4]), + .S(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_N_11) + ); + MUXCY_L com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_un1_diff_flag_0_I_46 ( + .CI(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_data_tmp_1[0]), + .DI(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_GND_3120), + .LO(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_data_tmp_1[1]), + .S(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_N_3) + ); + MUXCY_L com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_expire_pre_4_0_I_1 ( + .CI(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_VCC_3114), + .DI(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_GND_3120), + .LO(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_data_tmp_0[0]), + .S(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_N_57) + ); + MUXCY_L com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_expire_pre_4_0_I_10 ( + .CI(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_data_tmp_0[0]), + .DI(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_GND_3120), + .LO(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_data_tmp_0[1]), + .S(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_N_49) + ); + MUXCY_L com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_expire_pre_4_0_I_19 ( + .CI(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_data_tmp_0[1]), + .DI(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_GND_3120), + .LO(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_data_tmp_0[2]), + .S(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_N_41) + ); + MUXCY_L com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_expire_pre_4_0_I_28 ( + .CI(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_data_tmp_0[2]), + .DI(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_GND_3120), + .LO(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_data_tmp_0[3]), + .S(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_N_33) + ); + MUXCY_L com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_expire_pre_4_0_I_37 ( + .CI(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_data_tmp_0[3]), + .DI(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_GND_3120), + .LO(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_data_tmp_1[4]), + .S(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_N_25) + ); + MUXCY_L com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_expire_pre_4_0_I_46 ( + .CI(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_data_tmp_1[4]), + .DI(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_GND_3120), + .LO(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_data_tmp[5]), + .S(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_N_17) + ); + MUXCY_L com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_expire_pre_4_0_I_55 ( + .CI(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_data_tmp[5]), + .DI(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_GND_3120), + .LO(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_data_tmp[6]), + .S(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_N_9) + ); + MUXCY_L com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_reg_same_last_ackd_tsn_3_0_I_1 ( + .CI(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_VCC_3114), + .DI(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_GND_3120), + .LO(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_data_tmp[0]), + .S(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_N_43_0) + ); + MUXCY_L com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_reg_same_last_ackd_tsn_3_0_I_10 ( + .CI(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_data_tmp[1]), + .DI(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_GND_3120), + .LO(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_data_tmp[2]), + .S(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_N_35_0) + ); + MUXCY_L com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_reg_same_last_ackd_tsn_3_0_I_28 ( + .CI(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_data_tmp[2]), + .DI(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_GND_3120), + .LO(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_data_tmp[3]), + .S(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_N_19_0) + ); + MUXCY_L com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_reg_same_last_ackd_tsn_3_0_I_37 ( + .CI(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_data_tmp[3]), + .DI(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_GND_3120), + .LO(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_data_tmp_0[4]), + .S(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_N_11_0) + ); + MUXCY_L com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_reg_same_last_ackd_tsn_3_0_I_46 ( + .CI(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_data_tmp[0]), + .DI(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_GND_3120), + .LO(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_data_tmp[1]), + .S(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_N_3_0) + ); + FDRE com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_0_ ( + .CE(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_set_3115), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_s[0]), + .Q(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer[0]), + .R(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_N_10950_i_3116) + ); + MUXCY_L com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_cry_1_ ( + .CI(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer[0]), + .DI(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_GND_3120), + .LO(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_cry[1]), + .S(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_qxu[1]) + ); + XORCY com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_s_1_ ( + .CI(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer[0]), + .LI(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_qxu[1]), + .O(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_s[1]) + ); + FDRE com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_1_ ( + .CE(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_set_3115), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_s[1]), + .Q(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer[1]), + .R(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_N_10950_i_3116) + ); + MUXCY_L com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_cry_2_ ( + .CI(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_cry[1]), + .DI(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_GND_3120), + .LO(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_cry[2]), + .S(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_qxu[2]) + ); + XORCY com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_s_2_ ( + .CI(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_cry[1]), + .LI(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_qxu[2]), + .O(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_s[2]) + ); + FDRE com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_2_ ( + .CE(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_set_3115), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_s[2]), + .Q(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer[2]), + .R(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_N_10950_i_3116) + ); + MUXCY_L com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_cry_3_ ( + .CI(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_cry[2]), + .DI(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_GND_3120), + .LO(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_cry[3]), + .S(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_qxu[3]) + ); + XORCY com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_s_3_ ( + .CI(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_cry[2]), + .LI(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_qxu[3]), + .O(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_s[3]) + ); + FDRE com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_3_ ( + .CE(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_set_3115), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_s[3]), + .Q(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer[3]), + .R(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_N_10950_i_3116) + ); + MUXCY_L com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_cry_4_ ( + .CI(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_cry[3]), + .DI(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_GND_3120), + .LO(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_cry[4]), + .S(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_qxu[4]) + ); + XORCY com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_s_4_ ( + .CI(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_cry[3]), + .LI(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_qxu[4]), + .O(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_s[4]) + ); + FDRE com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_4_ ( + .CE(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_set_3115), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_s[4]), + .Q(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer[4]), + .R(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_N_10950_i_3116) + ); + MUXCY_L com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_cry_5_ ( + .CI(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_cry[4]), + .DI(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_GND_3120), + .LO(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_cry[5]), + .S(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_qxu[5]) + ); + XORCY com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_s_5_ ( + .CI(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_cry[4]), + .LI(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_qxu[5]), + .O(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_s[5]) + ); + FDRE com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_5_ ( + .CE(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_set_3115), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_s[5]), + .Q(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer[5]), + .R(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_N_10950_i_3116) + ); + MUXCY_L com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_cry_6_ ( + .CI(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_cry[5]), + .DI(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_GND_3120), + .LO(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_cry[6]), + .S(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_qxu[6]) + ); + XORCY com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_s_6_ ( + .CI(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_cry[5]), + .LI(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_qxu[6]), + .O(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_s[6]) + ); + FDRE com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_6_ ( + .CE(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_set_3115), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_s[6]), + .Q(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer[6]), + .R(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_N_10950_i_3116) + ); + MUXCY_L com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_cry_7_ ( + .CI(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_cry[6]), + .DI(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_GND_3120), + .LO(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_cry[7]), + .S(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_qxu[7]) + ); + XORCY com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_s_7_ ( + .CI(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_cry[6]), + .LI(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_qxu[7]), + .O(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_s[7]) + ); + FDRE com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_7_ ( + .CE(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_set_3115), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_s[7]), + .Q(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer[7]), + .R(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_N_10950_i_3116) + ); + MUXCY_L com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_cry_8_ ( + .CI(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_cry[7]), + .DI(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_GND_3120), + .LO(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_cry[8]), + .S(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_qxu[8]) + ); + XORCY com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_s_8_ ( + .CI(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_cry[7]), + .LI(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_qxu[8]), + .O(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_s[8]) + ); + FDRE com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_8_ ( + .CE(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_set_3115), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_s[8]), + .Q(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer[8]), + .R(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_N_10950_i_3116) + ); + MUXCY_L com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_cry_9_ ( + .CI(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_cry[8]), + .DI(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_GND_3120), + .LO(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_cry[9]), + .S(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_qxu[9]) + ); + XORCY com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_s_9_ ( + .CI(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_cry[8]), + .LI(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_qxu[9]), + .O(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_s[9]) + ); + FDRE com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_9_ ( + .CE(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_set_3115), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_s[9]), + .Q(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer[9]), + .R(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_N_10950_i_3116) + ); + MUXCY_L com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_cry_10_ ( + .CI(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_cry[9]), + .DI(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_GND_3120), + .LO(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_cry[10]), + .S(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_qxu[10]) + ); + XORCY com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_s_10_ ( + .CI(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_cry[9]), + .LI(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_qxu[10]), + .O(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_s[10]) + ); + FDRE com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_10_ ( + .CE(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_set_3115), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_s[10]), + .Q(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer[10]), + .R(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_N_10950_i_3116) + ); + MUXCY_L com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_cry_11_ ( + .CI(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_cry[10]), + .DI(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_GND_3120), + .LO(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_cry[11]), + .S(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_qxu[11]) + ); + XORCY com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_s_11_ ( + .CI(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_cry[10]), + .LI(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_qxu[11]), + .O(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_s[11]) + ); + FDRE com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_11_ ( + .CE(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_set_3115), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_s[11]), + .Q(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer[11]), + .R(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_N_10950_i_3116) + ); + MUXCY_L com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_cry_12_ ( + .CI(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_cry[11]), + .DI(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_GND_3120), + .LO(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_cry[12]), + .S(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_qxu[12]) + ); + XORCY com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_s_12_ ( + .CI(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_cry[11]), + .LI(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_qxu[12]), + .O(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_s[12]) + ); + FDRE com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_12_ ( + .CE(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_set_3115), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_s[12]), + .Q(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer[12]), + .R(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_N_10950_i_3116) + ); + MUXCY_L com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_cry_13_ ( + .CI(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_cry[12]), + .DI(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_GND_3120), + .LO(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_cry[13]), + .S(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_qxu[13]) + ); + XORCY com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_s_13_ ( + .CI(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_cry[12]), + .LI(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_qxu[13]), + .O(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_s[13]) + ); + FDRE com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_13_ ( + .CE(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_set_3115), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_s[13]), + .Q(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer[13]), + .R(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_N_10950_i_3116) + ); + XORCY com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_s_14_ ( + .CI(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_cry[13]), + .LI(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_qxu[14]), + .O(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_s[14]) + ); + FDRE com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_14_ ( + .CE(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_set_3115), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_s[14]), + .Q(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer[14]), + .R(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_N_10950_i_3116) + ); + defparam com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_num21_0_a2.INIT = 4'h8; + LUT2 com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_num21_0_a2 ( + .I0(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_reg_same_last_ackd_tsn_3125), + .I1(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_vld_q_3126), + .O(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_num21) + ); + defparam com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_un1_replay_num21_4_1_0_a2.INIT = 4'h8; + LUT2 com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_un1_replay_num21_4_1_0_a2 ( + .I0(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_ANSeqNum_AckdSeq_q_3124), + .I1(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_NxtTxTSN_ANSeqNum_q_3122), + .O(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_N_9376_1) + ); + defparam com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_expire_5_0_a2_0_a2_0_a2_0_a2.INIT = 4'h4; + LUT2 com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_expire_5_0_a2_0_a2_0_a2_0_a2 ( + .I0(com_llm_link_status[0]), + .I1(com_replay_timer_expire_pre), + .O(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_expire_5) + ); + defparam com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_clear_3_i_0_0_0_a2_0_1.INIT = 8'h20; + LUT3 com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_clear_3_i_0_0_0_a2_0_1 ( + .I0(com_llm_llm_common_llm_common_reg_ANSeqNum_AckdSeq_wire_2987), + .I1(com_llm_llm_common_llm_common_reg_ANSeqNum_Eq_AckdSeq_2988), + .I2(com_llm_llm_common_llm_common_reg_NxtTxTSN_ANSeqNum_wire_2986), + .O(com_llm_llm_common_llm_common_reg_N_58798_1) + ); + defparam com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_N_10950_i.INIT = 4'hB; + LUT2 com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_N_10950_i ( + .I0(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_clear_3117), + .I1(plm_link_up_1), + .O(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_N_10950_i_3116) + ); + defparam com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_N_87599_i.INIT = 8'hEC; + LUT3 com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_N_87599_i ( + .I0(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_waiting_3141), + .I1(com_reg_tx_update_retry_int), + .I2(com_reg_tx_update_retry_q), + .O(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_N_87599_i_3140) + ); + defparam com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_un1_replay_num21_1_i.INIT = 16'h007F; + LUT4 com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_un1_replay_num21_1_i ( + .I0(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_N_9376_1), + .I1(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_ANSeqNum_Eq_AckdSeq_q_3123), + .I2(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_reg_rx_dllp_nak_vld_qq_3121), + .I3(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_num21), + .O(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_un1_replay_num21_1_i_3118) + ); + defparam com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_num_7_i_o2_1_.INIT = 8'h02; + LUT3 com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_num_7_i_o2_1_ ( + .I0(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_N_9376_1), + .I1(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_ANSeqNum_Eq_AckdSeq_q_3123), + .I2(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_num21), + .O(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_N_22392_i) + ); + defparam com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_N_85487_i.INIT = 16'hEEFE; + LUT4 com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_N_85487_i ( + .I0(com_llm_link_status[0]), + .I1(com_replay_vld), + .I2(com_llm_llm_common_llm_common_reg_replay_timeout_flag), + .I3(com_reg_tx_update_retry_int), + .O(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_N_85487_i_3139) + ); + defparam com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_un1_replay_num_ac0.INIT = 4'h4; + LUT2 com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_un1_replay_num_ac0 ( + .I0(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_un1_replay_num21_1_i_3118), + .I1(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_num_6116[0]), + .O(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_un1_replay_num_c1) + ); + defparam com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_expire_pre_5_0_a2_0_a2_0_a2_0_a2.INIT = 4'h4; + LUT2_L com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_expire_pre_5_0_a2_0_a2_0_a2_0_a2 ( + .I0(com_llm_link_status[0]), + .I1(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_expire_pre_4), + .LO(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_expire_pre_5) + ); + defparam com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_N_60706_i.INIT = 4'hE; + LUT2_L com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_N_60706_i ( + .I0(com_llm_link_status[0]), + .I1(com_lnk_tupdate_seq[0]), + .LO(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_N_60706_i_3127) + ); + defparam com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_num_7_i_2_.INIT = 16'h1450; + LUT4_L com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_num_7_i_2_ ( + .I0(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_N_22392_i), + .I1(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_num_6116[1]), + .I2(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_num[2]), + .I3(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_un1_replay_num_c1), + .LO(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_N_22385_i) + ); + defparam com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_num_7_i_1_.INIT = 8'h14; + LUT3_L com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_num_7_i_1_ ( + .I0(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_N_22392_i), + .I1(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_num_6116[1]), + .I2(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_un1_replay_num_c1), + .LO(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_N_22383_i) + ); + defparam com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_num_7_iv_0_m2_0_0_.INIT = 16'hE4B1; + LUT4_L com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_num_7_iv_0_m2_0_0_ ( + .I0(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_N_22392_i), + .I1(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_un1_replay_num21_1_i_3118), + .I2(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_reg_rx_dllp_nak_vld_qq_3121), + .I3(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_num_6116[0]), + .LO(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_num_7_iv_0_m2_0[0]) + ); + defparam com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_N_60695_i.INIT = 4'hE; + LUT2_L com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_N_60695_i ( + .I0(com_llm_link_status[0]), + .I1(com_lnk_tupdate_seq[11]), + .LO(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_N_60695_i_3128) + ); + defparam com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_N_60696_i.INIT = 4'hE; + LUT2_L com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_N_60696_i ( + .I0(com_llm_link_status[0]), + .I1(com_lnk_tupdate_seq[10]), + .LO(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_N_60696_i_3129) + ); + defparam com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_N_60697_i.INIT = 4'hE; + LUT2_L com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_N_60697_i ( + .I0(com_llm_link_status[0]), + .I1(com_lnk_tupdate_seq[9]), + .LO(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_N_60697_i_3130) + ); + defparam com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_N_60698_i.INIT = 4'hE; + LUT2_L com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_N_60698_i ( + .I0(com_llm_link_status[0]), + .I1(com_lnk_tupdate_seq[8]), + .LO(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_N_60698_i_3131) + ); + defparam com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_N_60699_i.INIT = 4'hE; + LUT2_L com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_N_60699_i ( + .I0(com_llm_link_status[0]), + .I1(com_lnk_tupdate_seq[7]), + .LO(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_N_60699_i_3132) + ); + defparam com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_N_60700_i.INIT = 4'hE; + LUT2_L com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_N_60700_i ( + .I0(com_llm_link_status[0]), + .I1(com_lnk_tupdate_seq[6]), + .LO(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_N_60700_i_3133) + ); + defparam com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_N_60701_i.INIT = 4'hE; + LUT2_L com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_N_60701_i ( + .I0(com_llm_link_status[0]), + .I1(com_lnk_tupdate_seq[5]), + .LO(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_N_60701_i_3134) + ); + defparam com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_N_60702_i.INIT = 4'hE; + LUT2_L com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_N_60702_i ( + .I0(com_llm_link_status[0]), + .I1(com_lnk_tupdate_seq[4]), + .LO(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_N_60702_i_3135) + ); + defparam com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_N_60703_i.INIT = 4'hE; + LUT2_L com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_N_60703_i ( + .I0(com_llm_link_status[0]), + .I1(com_lnk_tupdate_seq[3]), + .LO(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_N_60703_i_3136) + ); + defparam com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_N_60704_i.INIT = 4'hE; + LUT2_L com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_N_60704_i ( + .I0(com_llm_link_status[0]), + .I1(com_lnk_tupdate_seq[2]), + .LO(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_N_60704_i_3137) + ); + defparam com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_N_60705_i.INIT = 4'hE; + LUT2_L com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_N_60705_i ( + .I0(com_llm_link_status[0]), + .I1(com_lnk_tupdate_seq[1]), + .LO(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_N_60705_i_3138) + ); + defparam com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timeout_flag17_0_a2_0_a2_0_a2_0_a2.INIT = 4'h4; + LUT2_L com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timeout_flag17_0_a2_0_a2_0_a2_0_a2 ( + .I0(com_replay_timer_expire), + .I1(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_expire_5), + .LO(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timeout_flag17) + ); + defparam com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_set_3_0_a2_0_a2_0_a3_0_a2.INIT = 4'h4; + LUT2_L com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_set_3_0_a2_0_a2_0_a3_0_a2 ( + .I0(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_I_19), + .I1(plm_link_l0), + .LO(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_set_3) + ); + defparam com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_N_85482_i.INIT = 16'hFECC; + LUT4_L com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_N_85482_i ( + .I0(com_llm_llm_common_llm_common_reg_N_58792), + .I1(com_llm_link_status[0]), + .I2(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_waiting_3141), + .I3(plm_link_l0), + .LO(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_N_85482_i_3119) + ); + MUXCY com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_reg_same_last_ackd_tsn_3_0_I_19 ( + .CI(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_data_tmp_0[4]), + .DI(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_GND_3120), + .O(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_reg_same_last_ackd_tsn_3), + .S(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_N_27) + ); + MUXCY com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_expire_pre_4_0_I_64 ( + .CI(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_data_tmp[6]), + .DI(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_GND_3120), + .O(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_expire_pre_4), + .S(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_N_7_i) + ); + MUXCY com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_un1_diff_flag_0_I_19 ( + .CI(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_data_tmp[4]), + .DI(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_GND_3120), + .O(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_I_19), + .S(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_N_27_0) + ); + FDC com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_reg_rx_dllp_nak_vld_qq ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_common_llm_common_reg_reg_rx_dllp_nak_vld_q_2984), + .Q(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_reg_rx_dllp_nak_vld_qq_3121), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_NxtTxTSN_ANSeqNum_q ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_common_llm_common_reg_N_22173_i), + .Q(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_NxtTxTSN_ANSeqNum_q_3122), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_ANSeqNum_Eq_AckdSeq_q ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_common_llm_common_reg_ANSeqNum_Eq_AckdSeq_2988), + .Q(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_ANSeqNum_Eq_AckdSeq_q_3123), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_ANSeqNum_AckdSeq_q ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_common_llm_common_reg_N_22175_i), + .Q(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_ANSeqNum_AckdSeq_q_3124), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_expire_pre ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_expire_pre_5), + .Q(com_replay_timer_expire_pre), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_reg_same_last_ackd_tsn ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_reg_same_last_ackd_tsn_3), + .Q(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_reg_same_last_ackd_tsn_3125), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_expire ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_expire_5), + .Q(com_replay_timer_expire), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_vld_q ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_replay_vld), + .Q(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_vld_q_3126), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_num_2_q_0_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_num[2]), + .Q(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_num_2_q[0]), + .CLR(plm_link_up_i) + ); + FDP com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_reg_tx_ackd_tsn_q_0_ ( + .PRE(plm_link_up_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_N_60706_i_3127), + .Q(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_reg_tx_ackd_tsn_q[0]) + ); + FDC com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_num_2_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_N_22385_i), + .Q(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_num[2]), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_num_1_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_N_22383_i), + .Q(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_num_6116[1]), + .CLR(plm_link_up_i) + ); + FDC com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_num_0_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_num_7_iv_0_m2_0[0]), + .Q(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_num_6116[0]), + .CLR(plm_link_up_i) + ); + FDP com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_reg_tx_ackd_tsn_q_11_ ( + .PRE(plm_link_up_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_N_60695_i_3128), + .Q(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_reg_tx_ackd_tsn_q[11]) + ); + FDP com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_reg_tx_ackd_tsn_q_10_ ( + .PRE(plm_link_up_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_N_60696_i_3129), + .Q(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_reg_tx_ackd_tsn_q[10]) + ); + FDP com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_reg_tx_ackd_tsn_q_9_ ( + .PRE(plm_link_up_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_N_60697_i_3130), + .Q(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_reg_tx_ackd_tsn_q[9]) + ); + FDP com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_reg_tx_ackd_tsn_q_8_ ( + .PRE(plm_link_up_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_N_60698_i_3131), + .Q(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_reg_tx_ackd_tsn_q[8]) + ); + FDP com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_reg_tx_ackd_tsn_q_7_ ( + .PRE(plm_link_up_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_N_60699_i_3132), + .Q(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_reg_tx_ackd_tsn_q[7]) + ); + FDP com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_reg_tx_ackd_tsn_q_6_ ( + .PRE(plm_link_up_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_N_60700_i_3133), + .Q(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_reg_tx_ackd_tsn_q[6]) + ); + FDP com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_reg_tx_ackd_tsn_q_5_ ( + .PRE(plm_link_up_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_N_60701_i_3134), + .Q(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_reg_tx_ackd_tsn_q[5]) + ); + FDP com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_reg_tx_ackd_tsn_q_4_ ( + .PRE(plm_link_up_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_N_60702_i_3135), + .Q(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_reg_tx_ackd_tsn_q[4]) + ); + FDP com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_reg_tx_ackd_tsn_q_3_ ( + .PRE(plm_link_up_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_N_60703_i_3136), + .Q(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_reg_tx_ackd_tsn_q[3]) + ); + FDP com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_reg_tx_ackd_tsn_q_2_ ( + .PRE(plm_link_up_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_N_60704_i_3137), + .Q(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_reg_tx_ackd_tsn_q[2]) + ); + FDP com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_reg_tx_ackd_tsn_q_1_ ( + .PRE(plm_link_up_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_N_60705_i_3138), + .Q(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_reg_tx_ackd_tsn_q[1]) + ); + FDCE com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timeout_flag ( + .CE(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_N_85487_i_3139), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timeout_flag17), + .Q(com_llm_llm_common_llm_common_reg_replay_timeout_flag), + .CLR(plm_link_up_i) + ); + FDCE com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_waiting ( + .CE(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_N_87599_i_3140), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_reg_tx_update_retry_int), + .Q(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_waiting_3141), + .CLR(plm_link_up_i) + ); + defparam com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_qxu_0_0_.INIT = 4'h2; + LUT1_L com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_qxu_0_0_ ( + .I0(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer[0]), + .LO(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_qxu[0]) + ); + defparam com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_qxu_0_14_.INIT = 4'h2; + LUT1_L com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_qxu_0_14_ ( + .I0(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer[14]), + .LO(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_qxu[14]) + ); + defparam com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_qxu_0_13_.INIT = 4'h2; + LUT1_L com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_qxu_0_13_ ( + .I0(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer[13]), + .LO(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_qxu[13]) + ); + defparam com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_qxu_0_12_.INIT = 4'h2; + LUT1_L com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_qxu_0_12_ ( + .I0(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer[12]), + .LO(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_qxu[12]) + ); + defparam com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_qxu_0_11_.INIT = 4'h2; + LUT1_L com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_qxu_0_11_ ( + .I0(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer[11]), + .LO(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_qxu[11]) + ); + defparam com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_qxu_0_10_.INIT = 4'h2; + LUT1_L com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_qxu_0_10_ ( + .I0(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer[10]), + .LO(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_qxu[10]) + ); + defparam com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_qxu_0_9_.INIT = 4'h2; + LUT1_L com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_qxu_0_9_ ( + .I0(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer[9]), + .LO(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_qxu[9]) + ); + defparam com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_qxu_0_8_.INIT = 4'h2; + LUT1_L com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_qxu_0_8_ ( + .I0(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer[8]), + .LO(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_qxu[8]) + ); + defparam com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_qxu_0_7_.INIT = 4'h2; + LUT1_L com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_qxu_0_7_ ( + .I0(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer[7]), + .LO(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_qxu[7]) + ); + defparam com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_qxu_0_6_.INIT = 4'h2; + LUT1_L com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_qxu_0_6_ ( + .I0(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer[6]), + .LO(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_qxu[6]) + ); + defparam com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_qxu_0_5_.INIT = 4'h2; + LUT1_L com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_qxu_0_5_ ( + .I0(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer[5]), + .LO(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_qxu[5]) + ); + defparam com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_qxu_0_4_.INIT = 4'h2; + LUT1_L com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_qxu_0_4_ ( + .I0(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer[4]), + .LO(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_qxu[4]) + ); + defparam com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_qxu_0_3_.INIT = 4'h2; + LUT1_L com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_qxu_0_3_ ( + .I0(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer[3]), + .LO(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_qxu[3]) + ); + defparam com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_qxu_0_2_.INIT = 4'h2; + LUT1_L com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_qxu_0_2_ ( + .I0(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer[2]), + .LO(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_qxu[2]) + ); + defparam com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_qxu_0_1_.INIT = 4'h2; + LUT1_L com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_qxu_0_1_ ( + .I0(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer[1]), + .LO(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_qxu[1]) + ); + defparam com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_s_0_.INIT = 4'h1; + LUT1_L com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_s_0_ ( + .I0(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_qxu[0]), + .LO(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_s[0]) + ); + defparam com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_un1_diff_flag_0_I_27.INIT = 16'h8421; + LUT4 com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_un1_diff_flag_0_I_27 ( + .I0(com_lnk_ttrans_seq[10]), + .I1(com_lnk_ttrans_seq[11]), + .I2(com_lnk_tupdate_seq[10]), + .I3(com_lnk_tupdate_seq[11]), + .O(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_N_27_0) + ); + defparam com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_expire_pre_4_0_N_7_i.INIT = 4'h9; + LUT2 com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_expire_pre_4_0_N_7_i ( + .I0(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_q[14]), + .I1(com_llm_llm_common_reg_replay_to_val[14]), + .O(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_N_7_i) + ); + defparam com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_reg_same_last_ackd_tsn_3_0_I_27.INIT = 16'h8421; + LUT4 com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_reg_same_last_ackd_tsn_3_0_I_27 ( + .I0(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_reg_tx_ackd_tsn_q[10]), + .I1(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_reg_tx_ackd_tsn_q[11]), + .I2(com_lnk_tupdate_seq[10]), + .I3(com_lnk_tupdate_seq[11]), + .O(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_N_27) + ); + defparam com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_reg_same_last_ackd_tsn_3_0_I_54.INIT = 16'h8421; + LUT4 com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_reg_same_last_ackd_tsn_3_0_I_54 ( + .I0(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_reg_tx_ackd_tsn_q[2]), + .I1(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_reg_tx_ackd_tsn_q[3]), + .I2(com_lnk_tupdate_seq[2]), + .I3(com_lnk_tupdate_seq[3]), + .O(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_N_3_0) + ); + defparam com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_reg_same_last_ackd_tsn_3_0_I_45.INIT = 16'h8421; + LUT4 com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_reg_same_last_ackd_tsn_3_0_I_45 ( + .I0(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_reg_tx_ackd_tsn_q[8]), + .I1(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_reg_tx_ackd_tsn_q[9]), + .I2(com_lnk_tupdate_seq[8]), + .I3(com_lnk_tupdate_seq[9]), + .O(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_N_11_0) + ); + defparam com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_reg_same_last_ackd_tsn_3_0_I_36.INIT = 16'h8421; + LUT4 com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_reg_same_last_ackd_tsn_3_0_I_36 ( + .I0(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_reg_tx_ackd_tsn_q[6]), + .I1(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_reg_tx_ackd_tsn_q[7]), + .I2(com_lnk_tupdate_seq[6]), + .I3(com_lnk_tupdate_seq[7]), + .O(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_N_19_0) + ); + defparam com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_reg_same_last_ackd_tsn_3_0_I_18.INIT = 16'h8421; + LUT4 com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_reg_same_last_ackd_tsn_3_0_I_18 ( + .I0(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_reg_tx_ackd_tsn_q[4]), + .I1(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_reg_tx_ackd_tsn_q[5]), + .I2(com_lnk_tupdate_seq[4]), + .I3(com_lnk_tupdate_seq[5]), + .O(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_N_35_0) + ); + defparam com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_reg_same_last_ackd_tsn_3_0_I_9.INIT = 16'h8421; + LUT4 com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_reg_same_last_ackd_tsn_3_0_I_9 ( + .I0(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_reg_tx_ackd_tsn_q[0]), + .I1(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_reg_tx_ackd_tsn_q[1]), + .I2(com_lnk_tupdate_seq[0]), + .I3(com_lnk_tupdate_seq[1]), + .O(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_N_43_0) + ); + defparam com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_expire_pre_4_0_I_63.INIT = 16'h8421; + LUT4 com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_expire_pre_4_0_I_63 ( + .I0(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_q[12]), + .I1(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_q[13]), + .I2(com_llm_llm_common_reg_replay_to_val[12]), + .I3(com_llm_llm_common_reg_replay_to_val[13]), + .O(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_N_9) + ); + defparam com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_expire_pre_4_0_I_54.INIT = 16'h8421; + LUT4 com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_expire_pre_4_0_I_54 ( + .I0(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_q[10]), + .I1(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_q[11]), + .I2(com_llm_llm_common_reg_replay_to_val[10]), + .I3(com_llm_llm_common_reg_replay_to_val[11]), + .O(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_N_17) + ); + defparam com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_expire_pre_4_0_I_45.INIT = 16'h8421; + LUT4 com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_expire_pre_4_0_I_45 ( + .I0(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_q[8]), + .I1(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_q[9]), + .I2(com_llm_llm_common_reg_replay_to_val[8]), + .I3(com_llm_llm_common_reg_replay_to_val[9]), + .O(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_N_25) + ); + defparam com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_expire_pre_4_0_I_36.INIT = 16'h8421; + LUT4 com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_expire_pre_4_0_I_36 ( + .I0(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_q[6]), + .I1(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_q[7]), + .I2(com_llm_llm_common_reg_replay_to_val[6]), + .I3(com_llm_llm_common_reg_replay_to_val[7]), + .O(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_N_33) + ); + defparam com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_expire_pre_4_0_I_27.INIT = 16'h8421; + LUT4 com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_expire_pre_4_0_I_27 ( + .I0(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_q[4]), + .I1(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_q[5]), + .I2(com_llm_llm_common_reg_replay_to_val[4]), + .I3(com_llm_llm_common_reg_replay_to_val[5]), + .O(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_N_41) + ); + defparam com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_expire_pre_4_0_I_18.INIT = 16'h8421; + LUT4 com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_expire_pre_4_0_I_18 ( + .I0(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_q[2]), + .I1(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_q[3]), + .I2(com_llm_llm_common_reg_replay_to_val[2]), + .I3(com_llm_llm_common_reg_replay_to_val[3]), + .O(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_N_49) + ); + defparam com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_expire_pre_4_0_I_9.INIT = 16'h8421; + LUT4 com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_expire_pre_4_0_I_9 ( + .I0(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_q[0]), + .I1(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_replay_timer_q[1]), + .I2(com_llm_llm_common_reg_replay_to_val[0]), + .I3(com_llm_llm_common_reg_replay_to_val[1]), + .O(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_N_57) + ); + defparam com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_un1_diff_flag_0_I_54.INIT = 16'h8421; + LUT4 com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_un1_diff_flag_0_I_54 ( + .I0(com_lnk_ttrans_seq[2]), + .I1(com_lnk_ttrans_seq[3]), + .I2(com_lnk_tupdate_seq[2]), + .I3(com_lnk_tupdate_seq[3]), + .O(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_N_3) + ); + defparam com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_un1_diff_flag_0_I_45.INIT = 16'h8421; + LUT4 com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_un1_diff_flag_0_I_45 ( + .I0(com_lnk_ttrans_seq[8]), + .I1(com_lnk_ttrans_seq[9]), + .I2(com_lnk_tupdate_seq[8]), + .I3(com_lnk_tupdate_seq[9]), + .O(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_N_11) + ); + defparam com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_un1_diff_flag_0_I_36.INIT = 16'h8421; + LUT4 com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_un1_diff_flag_0_I_36 ( + .I0(com_lnk_ttrans_seq[6]), + .I1(com_lnk_ttrans_seq[7]), + .I2(com_lnk_tupdate_seq[6]), + .I3(com_lnk_tupdate_seq[7]), + .O(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_N_19) + ); + defparam com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_un1_diff_flag_0_I_18.INIT = 16'h8421; + LUT4 com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_un1_diff_flag_0_I_18 ( + .I0(com_lnk_ttrans_seq[4]), + .I1(com_lnk_ttrans_seq[5]), + .I2(com_lnk_tupdate_seq[4]), + .I3(com_lnk_tupdate_seq[5]), + .O(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_N_35) + ); + defparam com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_un1_diff_flag_0_I_9.INIT = 16'h8421; + LUT4 com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_un1_diff_flag_0_I_9 ( + .I0(com_lnk_ttrans_seq[0]), + .I1(com_lnk_ttrans_seq[1]), + .I2(com_lnk_tupdate_seq[0]), + .I3(com_lnk_tupdate_seq[1]), + .O(com_llm_llm_common_llm_common_reg_llm_ack_nak_timer_N_43) + ); + GND com_llm_llm_common_llm_common_reg_llm_next_rcv_tsn_GND ( + .G(com_llm_llm_common_llm_common_reg_llm_next_rcv_tsn_GND_3142) + ); + MUXCY_L com_llm_llm_common_llm_common_reg_llm_next_rcv_tsn_out_cry_0_ ( + .CI(com_llm_llm_common_link_status_i[0]), + .DI(com_llm_llm_common_llm_common_reg_llm_next_rcv_tsn_GND_3142), + .LO(com_llm_llm_common_llm_common_reg_llm_next_rcv_tsn_out_cry[0]), + .S(com_llm_llm_common_llm_common_reg_llm_next_rcv_tsn_out_qxu[0]) + ); + XORCY com_llm_llm_common_llm_common_reg_llm_next_rcv_tsn_out_s_0_ ( + .CI(com_llm_llm_common_link_status_i[0]), + .LI(com_llm_llm_common_llm_common_reg_llm_next_rcv_tsn_out_qxu[0]), + .O(com_llm_llm_common_llm_common_reg_llm_next_rcv_tsn_out_s[0]) + ); + MUXCY_L com_llm_llm_common_llm_common_reg_llm_next_rcv_tsn_out_cry_1_ ( + .CI(com_llm_llm_common_llm_common_reg_llm_next_rcv_tsn_out_cry[0]), + .DI(com_llm_llm_common_llm_common_reg_llm_next_rcv_tsn_GND_3142), + .LO(com_llm_llm_common_llm_common_reg_llm_next_rcv_tsn_out_cry[1]), + .S(com_llm_llm_common_llm_common_reg_llm_next_rcv_tsn_out_qxu[1]) + ); + XORCY com_llm_llm_common_llm_common_reg_llm_next_rcv_tsn_out_s_1_ ( + .CI(com_llm_llm_common_llm_common_reg_llm_next_rcv_tsn_out_cry[0]), + .LI(com_llm_llm_common_llm_common_reg_llm_next_rcv_tsn_out_qxu[1]), + .O(com_llm_llm_common_llm_common_reg_llm_next_rcv_tsn_out_s[1]) + ); + MUXCY_L com_llm_llm_common_llm_common_reg_llm_next_rcv_tsn_out_cry_2_ ( + .CI(com_llm_llm_common_llm_common_reg_llm_next_rcv_tsn_out_cry[1]), + .DI(com_llm_llm_common_llm_common_reg_llm_next_rcv_tsn_GND_3142), + .LO(com_llm_llm_common_llm_common_reg_llm_next_rcv_tsn_out_cry[2]), + .S(com_llm_llm_common_llm_common_reg_llm_next_rcv_tsn_out_qxu[2]) + ); + XORCY com_llm_llm_common_llm_common_reg_llm_next_rcv_tsn_out_s_2_ ( + .CI(com_llm_llm_common_llm_common_reg_llm_next_rcv_tsn_out_cry[1]), + .LI(com_llm_llm_common_llm_common_reg_llm_next_rcv_tsn_out_qxu[2]), + .O(com_llm_llm_common_llm_common_reg_llm_next_rcv_tsn_out_s[2]) + ); + MUXCY_L com_llm_llm_common_llm_common_reg_llm_next_rcv_tsn_out_cry_3_ ( + .CI(com_llm_llm_common_llm_common_reg_llm_next_rcv_tsn_out_cry[2]), + .DI(com_llm_llm_common_llm_common_reg_llm_next_rcv_tsn_GND_3142), + .LO(com_llm_llm_common_llm_common_reg_llm_next_rcv_tsn_out_cry[3]), + .S(com_llm_llm_common_llm_common_reg_llm_next_rcv_tsn_out_qxu[3]) + ); + XORCY com_llm_llm_common_llm_common_reg_llm_next_rcv_tsn_out_s_3_ ( + .CI(com_llm_llm_common_llm_common_reg_llm_next_rcv_tsn_out_cry[2]), + .LI(com_llm_llm_common_llm_common_reg_llm_next_rcv_tsn_out_qxu[3]), + .O(com_llm_llm_common_llm_common_reg_llm_next_rcv_tsn_out_s[3]) + ); + MUXCY_L com_llm_llm_common_llm_common_reg_llm_next_rcv_tsn_out_cry_4_ ( + .CI(com_llm_llm_common_llm_common_reg_llm_next_rcv_tsn_out_cry[3]), + .DI(com_llm_llm_common_llm_common_reg_llm_next_rcv_tsn_GND_3142), + .LO(com_llm_llm_common_llm_common_reg_llm_next_rcv_tsn_out_cry[4]), + .S(com_llm_llm_common_llm_common_reg_llm_next_rcv_tsn_out_qxu[4]) + ); + XORCY com_llm_llm_common_llm_common_reg_llm_next_rcv_tsn_out_s_4_ ( + .CI(com_llm_llm_common_llm_common_reg_llm_next_rcv_tsn_out_cry[3]), + .LI(com_llm_llm_common_llm_common_reg_llm_next_rcv_tsn_out_qxu[4]), + .O(com_llm_llm_common_llm_common_reg_llm_next_rcv_tsn_out_s[4]) + ); + MUXCY_L com_llm_llm_common_llm_common_reg_llm_next_rcv_tsn_out_cry_5_ ( + .CI(com_llm_llm_common_llm_common_reg_llm_next_rcv_tsn_out_cry[4]), + .DI(com_llm_llm_common_llm_common_reg_llm_next_rcv_tsn_GND_3142), + .LO(com_llm_llm_common_llm_common_reg_llm_next_rcv_tsn_out_cry[5]), + .S(com_llm_llm_common_llm_common_reg_llm_next_rcv_tsn_out_qxu[5]) + ); + XORCY com_llm_llm_common_llm_common_reg_llm_next_rcv_tsn_out_s_5_ ( + .CI(com_llm_llm_common_llm_common_reg_llm_next_rcv_tsn_out_cry[4]), + .LI(com_llm_llm_common_llm_common_reg_llm_next_rcv_tsn_out_qxu[5]), + .O(com_llm_llm_common_llm_common_reg_llm_next_rcv_tsn_out_s[5]) + ); + MUXCY_L com_llm_llm_common_llm_common_reg_llm_next_rcv_tsn_out_cry_6_ ( + .CI(com_llm_llm_common_llm_common_reg_llm_next_rcv_tsn_out_cry[5]), + .DI(com_llm_llm_common_llm_common_reg_llm_next_rcv_tsn_GND_3142), + .LO(com_llm_llm_common_llm_common_reg_llm_next_rcv_tsn_out_cry[6]), + .S(com_llm_llm_common_llm_common_reg_llm_next_rcv_tsn_out_qxu[6]) + ); + XORCY com_llm_llm_common_llm_common_reg_llm_next_rcv_tsn_out_s_6_ ( + .CI(com_llm_llm_common_llm_common_reg_llm_next_rcv_tsn_out_cry[5]), + .LI(com_llm_llm_common_llm_common_reg_llm_next_rcv_tsn_out_qxu[6]), + .O(com_llm_llm_common_llm_common_reg_llm_next_rcv_tsn_out_s[6]) + ); + MUXCY_L com_llm_llm_common_llm_common_reg_llm_next_rcv_tsn_out_cry_7_ ( + .CI(com_llm_llm_common_llm_common_reg_llm_next_rcv_tsn_out_cry[6]), + .DI(com_llm_llm_common_llm_common_reg_llm_next_rcv_tsn_GND_3142), + .LO(com_llm_llm_common_llm_common_reg_llm_next_rcv_tsn_out_cry[7]), + .S(com_llm_llm_common_llm_common_reg_llm_next_rcv_tsn_out_qxu[7]) + ); + XORCY com_llm_llm_common_llm_common_reg_llm_next_rcv_tsn_out_s_7_ ( + .CI(com_llm_llm_common_llm_common_reg_llm_next_rcv_tsn_out_cry[6]), + .LI(com_llm_llm_common_llm_common_reg_llm_next_rcv_tsn_out_qxu[7]), + .O(com_llm_llm_common_llm_common_reg_llm_next_rcv_tsn_out_s[7]) + ); + MUXCY_L com_llm_llm_common_llm_common_reg_llm_next_rcv_tsn_out_cry_8_ ( + .CI(com_llm_llm_common_llm_common_reg_llm_next_rcv_tsn_out_cry[7]), + .DI(com_llm_llm_common_llm_common_reg_llm_next_rcv_tsn_GND_3142), + .LO(com_llm_llm_common_llm_common_reg_llm_next_rcv_tsn_out_cry[8]), + .S(com_llm_llm_common_llm_common_reg_llm_next_rcv_tsn_out_qxu[8]) + ); + XORCY com_llm_llm_common_llm_common_reg_llm_next_rcv_tsn_out_s_8_ ( + .CI(com_llm_llm_common_llm_common_reg_llm_next_rcv_tsn_out_cry[7]), + .LI(com_llm_llm_common_llm_common_reg_llm_next_rcv_tsn_out_qxu[8]), + .O(com_llm_llm_common_llm_common_reg_llm_next_rcv_tsn_out_s[8]) + ); + MUXCY_L com_llm_llm_common_llm_common_reg_llm_next_rcv_tsn_out_cry_9_ ( + .CI(com_llm_llm_common_llm_common_reg_llm_next_rcv_tsn_out_cry[8]), + .DI(com_llm_llm_common_llm_common_reg_llm_next_rcv_tsn_GND_3142), + .LO(com_llm_llm_common_llm_common_reg_llm_next_rcv_tsn_out_cry[9]), + .S(com_llm_llm_common_llm_common_reg_llm_next_rcv_tsn_out_qxu[9]) + ); + XORCY com_llm_llm_common_llm_common_reg_llm_next_rcv_tsn_out_s_9_ ( + .CI(com_llm_llm_common_llm_common_reg_llm_next_rcv_tsn_out_cry[8]), + .LI(com_llm_llm_common_llm_common_reg_llm_next_rcv_tsn_out_qxu[9]), + .O(com_llm_llm_common_llm_common_reg_llm_next_rcv_tsn_out_s[9]) + ); + MUXCY_L com_llm_llm_common_llm_common_reg_llm_next_rcv_tsn_out_cry_10_ ( + .CI(com_llm_llm_common_llm_common_reg_llm_next_rcv_tsn_out_cry[9]), + .DI(com_llm_llm_common_llm_common_reg_llm_next_rcv_tsn_GND_3142), + .LO(com_llm_llm_common_llm_common_reg_llm_next_rcv_tsn_out_cry[10]), + .S(com_llm_llm_common_llm_common_reg_llm_next_rcv_tsn_out_qxu[10]) + ); + XORCY com_llm_llm_common_llm_common_reg_llm_next_rcv_tsn_out_s_10_ ( + .CI(com_llm_llm_common_llm_common_reg_llm_next_rcv_tsn_out_cry[9]), + .LI(com_llm_llm_common_llm_common_reg_llm_next_rcv_tsn_out_qxu[10]), + .O(com_llm_llm_common_llm_common_reg_llm_next_rcv_tsn_out_s[10]) + ); + XORCY com_llm_llm_common_llm_common_reg_llm_next_rcv_tsn_out_s_11_ ( + .CI(com_llm_llm_common_llm_common_reg_llm_next_rcv_tsn_out_cry[10]), + .LI(com_llm_llm_common_llm_common_reg_llm_next_rcv_tsn_out_qxu[11]), + .O(com_llm_llm_common_llm_common_reg_llm_next_rcv_tsn_out_s[11]) + ); + defparam com_llm_llm_common_llm_common_reg_llm_next_rcv_tsn_outlde_i_0_0_0_a2_2.INIT = 16'h0020; + LUT4 com_llm_llm_common_llm_common_reg_llm_next_rcv_tsn_outlde_i_0_0_0_a2_2 ( + .I0(com_llm_N_56500_i), + .I1(com_llm_rx_reof_n), + .I2(com_llm_rx_rsrc_dsc_n), + .I3(com_llm_rx_rsrc_rdy_n), + .O(com_llm_llm_common_llm_common_reg_N_58446_2) + ); + defparam com_llm_llm_common_llm_common_reg_llm_next_rcv_tsn_N_87516_i.INIT = 16'hFF80; + LUT4 com_llm_llm_common_llm_common_reg_llm_next_rcv_tsn_N_87516_i ( + .I0(com_llm_llm_common_llm_common_reg_N_58446_2), + .I1(com_llm_N_62468), + .I2(com_llm_reg_rx_tlp_tsn_err_0_a2_0_a2_0_a2_0_a2), + .I3(com_llm_link_status[0]), + .O(com_llm_llm_common_llm_common_reg_N_87516_i) + ); + FDCE com_llm_llm_common_llm_common_reg_llm_next_rcv_tsn_out_11_ ( + .CE(com_llm_llm_common_llm_common_reg_N_87516_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_common_llm_common_reg_llm_next_rcv_tsn_out_s[11]), + .Q(com_llm_reg_next_rcv_tsn[11]), + .CLR(com_llm_llm_common_llm_common_reg_lnk_sys_reset_n_0_a2_0_a2_0_a2_0_a2_2956) + ); + FDCE com_llm_llm_common_llm_common_reg_llm_next_rcv_tsn_out_10_ ( + .CE(com_llm_llm_common_llm_common_reg_N_87516_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_common_llm_common_reg_llm_next_rcv_tsn_out_s[10]), + .Q(com_llm_reg_next_rcv_tsn[10]), + .CLR(com_llm_llm_common_llm_common_reg_lnk_sys_reset_n_0_a2_0_a2_0_a2_0_a2_2956) + ); + FDCE com_llm_llm_common_llm_common_reg_llm_next_rcv_tsn_out_9_ ( + .CE(com_llm_llm_common_llm_common_reg_N_87516_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_common_llm_common_reg_llm_next_rcv_tsn_out_s[9]), + .Q(com_llm_reg_next_rcv_tsn[9]), + .CLR(com_llm_llm_common_llm_common_reg_lnk_sys_reset_n_0_a2_0_a2_0_a2_0_a2_2956) + ); + FDCE com_llm_llm_common_llm_common_reg_llm_next_rcv_tsn_out_8_ ( + .CE(com_llm_llm_common_llm_common_reg_N_87516_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_common_llm_common_reg_llm_next_rcv_tsn_out_s[8]), + .Q(com_llm_reg_next_rcv_tsn[8]), + .CLR(com_llm_llm_common_llm_common_reg_lnk_sys_reset_n_0_a2_0_a2_0_a2_0_a2_2956) + ); + FDCE com_llm_llm_common_llm_common_reg_llm_next_rcv_tsn_out_7_ ( + .CE(com_llm_llm_common_llm_common_reg_N_87516_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_common_llm_common_reg_llm_next_rcv_tsn_out_s[7]), + .Q(com_llm_reg_next_rcv_tsn[7]), + .CLR(com_llm_llm_common_llm_common_reg_lnk_sys_reset_n_0_a2_0_a2_0_a2_0_a2_2956) + ); + FDCE com_llm_llm_common_llm_common_reg_llm_next_rcv_tsn_out_6_ ( + .CE(com_llm_llm_common_llm_common_reg_N_87516_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_common_llm_common_reg_llm_next_rcv_tsn_out_s[6]), + .Q(com_llm_reg_next_rcv_tsn[6]), + .CLR(com_llm_llm_common_llm_common_reg_lnk_sys_reset_n_0_a2_0_a2_0_a2_0_a2_2956) + ); + FDCE com_llm_llm_common_llm_common_reg_llm_next_rcv_tsn_out_5_ ( + .CE(com_llm_llm_common_llm_common_reg_N_87516_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_common_llm_common_reg_llm_next_rcv_tsn_out_s[5]), + .Q(com_llm_reg_next_rcv_tsn[5]), + .CLR(com_llm_llm_common_llm_common_reg_lnk_sys_reset_n_0_a2_0_a2_0_a2_0_a2_2956) + ); + FDCE com_llm_llm_common_llm_common_reg_llm_next_rcv_tsn_out_4_ ( + .CE(com_llm_llm_common_llm_common_reg_N_87516_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_common_llm_common_reg_llm_next_rcv_tsn_out_s[4]), + .Q(com_llm_reg_next_rcv_tsn[4]), + .CLR(com_llm_llm_common_llm_common_reg_lnk_sys_reset_n_0_a2_0_a2_0_a2_0_a2_2956) + ); + FDCE com_llm_llm_common_llm_common_reg_llm_next_rcv_tsn_out_3_ ( + .CE(com_llm_llm_common_llm_common_reg_N_87516_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_common_llm_common_reg_llm_next_rcv_tsn_out_s[3]), + .Q(com_llm_reg_next_rcv_tsn[3]), + .CLR(com_llm_llm_common_llm_common_reg_lnk_sys_reset_n_0_a2_0_a2_0_a2_0_a2_2956) + ); + FDCE com_llm_llm_common_llm_common_reg_llm_next_rcv_tsn_out_2_ ( + .CE(com_llm_llm_common_llm_common_reg_N_87516_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_common_llm_common_reg_llm_next_rcv_tsn_out_s[2]), + .Q(com_llm_reg_next_rcv_tsn[2]), + .CLR(com_llm_llm_common_llm_common_reg_lnk_sys_reset_n_0_a2_0_a2_0_a2_0_a2_2956) + ); + FDCE com_llm_llm_common_llm_common_reg_llm_next_rcv_tsn_out_1_ ( + .CE(com_llm_llm_common_llm_common_reg_N_87516_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_common_llm_common_reg_llm_next_rcv_tsn_out_s[1]), + .Q(com_llm_reg_next_rcv_tsn[1]), + .CLR(com_llm_llm_common_llm_common_reg_lnk_sys_reset_n_0_a2_0_a2_0_a2_0_a2_2956) + ); + FDCE com_llm_llm_common_llm_common_reg_llm_next_rcv_tsn_out_0_ ( + .CE(com_llm_llm_common_llm_common_reg_N_87516_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_llm_llm_common_llm_common_reg_llm_next_rcv_tsn_out_s[0]), + .Q(com_llm_reg_next_rcv_tsn[0]), + .CLR(com_llm_llm_common_llm_common_reg_lnk_sys_reset_n_0_a2_0_a2_0_a2_0_a2_2956) + ); + defparam com_llm_llm_common_llm_common_reg_llm_next_rcv_tsn_out_qxu_0_0_.INIT = 4'h4; + LUT2_L com_llm_llm_common_llm_common_reg_llm_next_rcv_tsn_out_qxu_0_0_ ( + .I0(com_llm_link_status[0]), + .I1(com_llm_reg_next_rcv_tsn[0]), + .LO(com_llm_llm_common_llm_common_reg_llm_next_rcv_tsn_out_qxu[0]) + ); + defparam com_llm_llm_common_llm_common_reg_llm_next_rcv_tsn_out_qxu_0_1_.INIT = 4'h4; + LUT2_L com_llm_llm_common_llm_common_reg_llm_next_rcv_tsn_out_qxu_0_1_ ( + .I0(com_llm_link_status[0]), + .I1(com_llm_reg_next_rcv_tsn[1]), + .LO(com_llm_llm_common_llm_common_reg_llm_next_rcv_tsn_out_qxu[1]) + ); + defparam com_llm_llm_common_llm_common_reg_llm_next_rcv_tsn_out_qxu_0_2_.INIT = 4'h4; + LUT2_L com_llm_llm_common_llm_common_reg_llm_next_rcv_tsn_out_qxu_0_2_ ( + .I0(com_llm_link_status[0]), + .I1(com_llm_reg_next_rcv_tsn[2]), + .LO(com_llm_llm_common_llm_common_reg_llm_next_rcv_tsn_out_qxu[2]) + ); + defparam com_llm_llm_common_llm_common_reg_llm_next_rcv_tsn_out_qxu_0_3_.INIT = 4'h4; + LUT2_L com_llm_llm_common_llm_common_reg_llm_next_rcv_tsn_out_qxu_0_3_ ( + .I0(com_llm_link_status[0]), + .I1(com_llm_reg_next_rcv_tsn[3]), + .LO(com_llm_llm_common_llm_common_reg_llm_next_rcv_tsn_out_qxu[3]) + ); + defparam com_llm_llm_common_llm_common_reg_llm_next_rcv_tsn_out_qxu_0_4_.INIT = 4'h4; + LUT2_L com_llm_llm_common_llm_common_reg_llm_next_rcv_tsn_out_qxu_0_4_ ( + .I0(com_llm_link_status[0]), + .I1(com_llm_reg_next_rcv_tsn[4]), + .LO(com_llm_llm_common_llm_common_reg_llm_next_rcv_tsn_out_qxu[4]) + ); + defparam com_llm_llm_common_llm_common_reg_llm_next_rcv_tsn_out_qxu_0_5_.INIT = 4'h4; + LUT2_L com_llm_llm_common_llm_common_reg_llm_next_rcv_tsn_out_qxu_0_5_ ( + .I0(com_llm_link_status[0]), + .I1(com_llm_reg_next_rcv_tsn[5]), + .LO(com_llm_llm_common_llm_common_reg_llm_next_rcv_tsn_out_qxu[5]) + ); + defparam com_llm_llm_common_llm_common_reg_llm_next_rcv_tsn_out_qxu_0_6_.INIT = 4'h4; + LUT2_L com_llm_llm_common_llm_common_reg_llm_next_rcv_tsn_out_qxu_0_6_ ( + .I0(com_llm_link_status[0]), + .I1(com_llm_reg_next_rcv_tsn[6]), + .LO(com_llm_llm_common_llm_common_reg_llm_next_rcv_tsn_out_qxu[6]) + ); + defparam com_llm_llm_common_llm_common_reg_llm_next_rcv_tsn_out_qxu_0_7_.INIT = 4'h4; + LUT2_L com_llm_llm_common_llm_common_reg_llm_next_rcv_tsn_out_qxu_0_7_ ( + .I0(com_llm_link_status[0]), + .I1(com_llm_reg_next_rcv_tsn[7]), + .LO(com_llm_llm_common_llm_common_reg_llm_next_rcv_tsn_out_qxu[7]) + ); + defparam com_llm_llm_common_llm_common_reg_llm_next_rcv_tsn_out_qxu_0_8_.INIT = 4'h4; + LUT2_L com_llm_llm_common_llm_common_reg_llm_next_rcv_tsn_out_qxu_0_8_ ( + .I0(com_llm_link_status[0]), + .I1(com_llm_reg_next_rcv_tsn[8]), + .LO(com_llm_llm_common_llm_common_reg_llm_next_rcv_tsn_out_qxu[8]) + ); + defparam com_llm_llm_common_llm_common_reg_llm_next_rcv_tsn_out_qxu_0_9_.INIT = 4'h4; + LUT2_L com_llm_llm_common_llm_common_reg_llm_next_rcv_tsn_out_qxu_0_9_ ( + .I0(com_llm_link_status[0]), + .I1(com_llm_reg_next_rcv_tsn[9]), + .LO(com_llm_llm_common_llm_common_reg_llm_next_rcv_tsn_out_qxu[9]) + ); + defparam com_llm_llm_common_llm_common_reg_llm_next_rcv_tsn_out_qxu_0_10_.INIT = 4'h4; + LUT2_L com_llm_llm_common_llm_common_reg_llm_next_rcv_tsn_out_qxu_0_10_ ( + .I0(com_llm_link_status[0]), + .I1(com_llm_reg_next_rcv_tsn[10]), + .LO(com_llm_llm_common_llm_common_reg_llm_next_rcv_tsn_out_qxu[10]) + ); + defparam com_llm_llm_common_llm_common_reg_llm_next_rcv_tsn_out_qxu_0_11_.INIT = 4'h4; + LUT2_L com_llm_llm_common_llm_common_reg_llm_next_rcv_tsn_out_qxu_0_11_ ( + .I0(com_llm_link_status[0]), + .I1(com_llm_reg_next_rcv_tsn[11]), + .LO(com_llm_llm_common_llm_common_reg_llm_next_rcv_tsn_out_qxu[11]) + ); + GND com_tlm_u_tlm_tx_data_src_GND ( + .G(com_tlm_u_tlm_tx_data_src_GND_3144) + ); + FDR com_tlm_u_tlm_tx_data_src_stat_tlp_wr_ep_o ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_data_src_N_30212_i), + .Q(com_cmmt_stat_tlp_tx_wr_ep), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_tx_data_src_cfg_sent_o ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_data_src_cfg_sent_d_3143), + .Q(com_tlm_u_tlm_tx_cfg_sent), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_tx_data_src_cfg_sent_d ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_data_src_cfg_sent_d_3), + .Q(com_tlm_u_tlm_tx_data_src_cfg_sent_d_3143), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_tx_data_src_buf_src_rdy_o ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_data_src_buf_src_rdy_o_3), + .Q(com_tlm_u_tlm_tx_ds_buf_src_rdy), + .R(plm_link_up_i) + ); + FDSE com_tlm_u_tlm_tx_data_src_lnk_trem_o ( + .CE(com_tlm_u_tlm_tx_data_src_N_59170_i_3145), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_data_src_N_59176_i_3146), + .Q(com_lnk_trem[0]), + .S(plm_link_up_i) + ); + FDRE com_tlm_u_tlm_tx_data_src_lnk_tsof_o ( + .CE(com_tlm_u_tlm_tx_data_src_N_59170_i_3145), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_data_src_lnk_tsof_o_5), + .Q(com_lnk_tsof), + .R(plm_link_up_i) + ); + FDRE com_tlm_u_tlm_tx_data_src_lnk_tretry_o ( + .CE(com_tlm_u_tlm_tx_data_src_N_59170_i_3145), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_data_src_lnk_tretry_o_5), + .Q(com_lnk_tretry), + .R(plm_link_up_i) + ); + FDRE com_tlm_u_tlm_tx_data_src_lnk_teof_o ( + .CE(com_tlm_u_tlm_tx_data_src_N_59170_i_3145), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_data_src_lnk_teof_o_5), + .Q(com_lnk_teof), + .R(plm_link_up_i) + ); + FDSE com_tlm_u_tlm_tx_data_src_lnk_ttrans_seq_o_0_ ( + .CE(com_tlm_u_tlm_tx_data_src_un5_lnk_tsrc_rdy_o_0_a2_0_a3_0_a3_3148), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_data_src_lnk_ttrans_seq_o_4_i_m2_i_m3_i_m3_0[0]), + .Q(com_lnk_ttrans_seq[0]), + .S(plm_link_up_i) + ); + FDSE com_tlm_u_tlm_tx_data_src_lnk_ttrans_seq_o_1_ ( + .CE(com_tlm_u_tlm_tx_data_src_un5_lnk_tsrc_rdy_o_0_a2_0_a3_0_a3_3148), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_data_src_lnk_ttrans_seq_o_4_i_m2_i_m3_i_m3_0[1]), + .Q(com_lnk_ttrans_seq[1]), + .S(plm_link_up_i) + ); + FDSE com_tlm_u_tlm_tx_data_src_lnk_ttrans_seq_o_2_ ( + .CE(com_tlm_u_tlm_tx_data_src_un5_lnk_tsrc_rdy_o_0_a2_0_a3_0_a3_3148), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_data_src_lnk_ttrans_seq_o_4_i_m2_i_m3_i_m3_0[2]), + .Q(com_lnk_ttrans_seq[2]), + .S(plm_link_up_i) + ); + FDSE com_tlm_u_tlm_tx_data_src_lnk_ttrans_seq_o_3_ ( + .CE(com_tlm_u_tlm_tx_data_src_un5_lnk_tsrc_rdy_o_0_a2_0_a3_0_a3_3148), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_data_src_lnk_ttrans_seq_o_4_i_m2_i_m3_i_m3_0[3]), + .Q(com_lnk_ttrans_seq[3]), + .S(plm_link_up_i) + ); + FDSE com_tlm_u_tlm_tx_data_src_lnk_ttrans_seq_o_4_ ( + .CE(com_tlm_u_tlm_tx_data_src_un5_lnk_tsrc_rdy_o_0_a2_0_a3_0_a3_3148), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_data_src_lnk_ttrans_seq_o_4_i_m2_i_m3_i_m3_0[4]), + .Q(com_lnk_ttrans_seq[4]), + .S(plm_link_up_i) + ); + FDSE com_tlm_u_tlm_tx_data_src_lnk_ttrans_seq_o_5_ ( + .CE(com_tlm_u_tlm_tx_data_src_un5_lnk_tsrc_rdy_o_0_a2_0_a3_0_a3_3148), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_data_src_lnk_ttrans_seq_o_4_i_m2_i_m3_i_m3_0[5]), + .Q(com_lnk_ttrans_seq[5]), + .S(plm_link_up_i) + ); + FDSE com_tlm_u_tlm_tx_data_src_lnk_ttrans_seq_o_6_ ( + .CE(com_tlm_u_tlm_tx_data_src_un5_lnk_tsrc_rdy_o_0_a2_0_a3_0_a3_3148), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_data_src_lnk_ttrans_seq_o_4_i_m2_i_m3_i_m3_0[6]), + .Q(com_lnk_ttrans_seq[6]), + .S(plm_link_up_i) + ); + FDSE com_tlm_u_tlm_tx_data_src_lnk_ttrans_seq_o_7_ ( + .CE(com_tlm_u_tlm_tx_data_src_un5_lnk_tsrc_rdy_o_0_a2_0_a3_0_a3_3148), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_data_src_lnk_ttrans_seq_o_4_i_m2_i_m3_i_m3_0[7]), + .Q(com_lnk_ttrans_seq[7]), + .S(plm_link_up_i) + ); + FDSE com_tlm_u_tlm_tx_data_src_lnk_ttrans_seq_o_8_ ( + .CE(com_tlm_u_tlm_tx_data_src_un5_lnk_tsrc_rdy_o_0_a2_0_a3_0_a3_3148), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_data_src_lnk_ttrans_seq_o_4_i_m2_i_m3_i_m3_0[8]), + .Q(com_lnk_ttrans_seq[8]), + .S(plm_link_up_i) + ); + FDSE com_tlm_u_tlm_tx_data_src_lnk_ttrans_seq_o_9_ ( + .CE(com_tlm_u_tlm_tx_data_src_un5_lnk_tsrc_rdy_o_0_a2_0_a3_0_a3_3148), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_data_src_lnk_ttrans_seq_o_4_i_m2_i_m3_i_m3_0[9]), + .Q(com_lnk_ttrans_seq[9]), + .S(plm_link_up_i) + ); + FDSE com_tlm_u_tlm_tx_data_src_lnk_ttrans_seq_o_10_ ( + .CE(com_tlm_u_tlm_tx_data_src_un5_lnk_tsrc_rdy_o_0_a2_0_a3_0_a3_3148), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_data_src_lnk_ttrans_seq_o_4_i_m2_i_m3_i_m3_0[10]), + .Q(com_lnk_ttrans_seq[10]), + .S(plm_link_up_i) + ); + FDSE com_tlm_u_tlm_tx_data_src_lnk_ttrans_seq_o_11_ ( + .CE(com_tlm_u_tlm_tx_data_src_un5_lnk_tsrc_rdy_o_0_a2_0_a3_0_a3_3148), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_data_src_lnk_ttrans_seq_o_4_i_m2_i_m3_i_m3_0[11]), + .Q(com_lnk_ttrans_seq[11]), + .S(plm_link_up_i) + ); + FDRE com_tlm_u_tlm_tx_data_src_lnk_tsrc_rdy_o ( + .CE(com_lnk_tdst_rdy_n_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_src_rdy), + .Q(com_tlm_u_tlm_tx_data_src_lnk_tsrc_rdy), + .R(plm_link_up_i) + ); + MUXCY_L com_tlm_u_tlm_tx_data_src_tsn_cnt_cry_0_ ( + .CI(com_tlm_u_tlm_tx_vc0_retry_i), + .DI(com_tlm_u_tlm_tx_data_src_GND_3144), + .LO(com_tlm_u_tlm_tx_data_src_tsn_cnt_cry[0]), + .S(com_tlm_u_tlm_tx_data_src_tsn_cnt_qxu[0]) + ); + XORCY com_tlm_u_tlm_tx_data_src_tsn_cnt_s_0_ ( + .CI(com_tlm_u_tlm_tx_vc0_retry_i), + .LI(com_tlm_u_tlm_tx_data_src_tsn_cnt_qxu[0]), + .O(com_tlm_u_tlm_tx_data_src_tsn_cnt_s[0]) + ); + FDRE com_tlm_u_tlm_tx_data_src_tsn_cnt_0_ ( + .CE(com_tlm_u_tlm_tx_data_src_lnk_teof_o_5), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_data_src_tsn_cnt_s[0]), + .Q(com_tlm_u_tlm_tx_data_src_tsn_cnt[0]), + .R(plm_link_up_i) + ); + MUXCY_L com_tlm_u_tlm_tx_data_src_tsn_cnt_cry_1_ ( + .CI(com_tlm_u_tlm_tx_data_src_tsn_cnt_cry[0]), + .DI(com_tlm_u_tlm_tx_data_src_GND_3144), + .LO(com_tlm_u_tlm_tx_data_src_tsn_cnt_cry[1]), + .S(com_tlm_u_tlm_tx_data_src_tsn_cnt_qxu[1]) + ); + XORCY com_tlm_u_tlm_tx_data_src_tsn_cnt_s_1_ ( + .CI(com_tlm_u_tlm_tx_data_src_tsn_cnt_cry[0]), + .LI(com_tlm_u_tlm_tx_data_src_tsn_cnt_qxu[1]), + .O(com_tlm_u_tlm_tx_data_src_tsn_cnt_s[1]) + ); + FDRE com_tlm_u_tlm_tx_data_src_tsn_cnt_1_ ( + .CE(com_tlm_u_tlm_tx_data_src_lnk_teof_o_5), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_data_src_tsn_cnt_s[1]), + .Q(com_tlm_u_tlm_tx_data_src_tsn_cnt[1]), + .R(plm_link_up_i) + ); + MUXCY_L com_tlm_u_tlm_tx_data_src_tsn_cnt_cry_2_ ( + .CI(com_tlm_u_tlm_tx_data_src_tsn_cnt_cry[1]), + .DI(com_tlm_u_tlm_tx_data_src_GND_3144), + .LO(com_tlm_u_tlm_tx_data_src_tsn_cnt_cry[2]), + .S(com_tlm_u_tlm_tx_data_src_tsn_cnt_qxu[2]) + ); + XORCY com_tlm_u_tlm_tx_data_src_tsn_cnt_s_2_ ( + .CI(com_tlm_u_tlm_tx_data_src_tsn_cnt_cry[1]), + .LI(com_tlm_u_tlm_tx_data_src_tsn_cnt_qxu[2]), + .O(com_tlm_u_tlm_tx_data_src_tsn_cnt_s[2]) + ); + FDRE com_tlm_u_tlm_tx_data_src_tsn_cnt_2_ ( + .CE(com_tlm_u_tlm_tx_data_src_lnk_teof_o_5), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_data_src_tsn_cnt_s[2]), + .Q(com_tlm_u_tlm_tx_data_src_tsn_cnt[2]), + .R(plm_link_up_i) + ); + MUXCY_L com_tlm_u_tlm_tx_data_src_tsn_cnt_cry_3_ ( + .CI(com_tlm_u_tlm_tx_data_src_tsn_cnt_cry[2]), + .DI(com_tlm_u_tlm_tx_data_src_GND_3144), + .LO(com_tlm_u_tlm_tx_data_src_tsn_cnt_cry[3]), + .S(com_tlm_u_tlm_tx_data_src_tsn_cnt_qxu[3]) + ); + XORCY com_tlm_u_tlm_tx_data_src_tsn_cnt_s_3_ ( + .CI(com_tlm_u_tlm_tx_data_src_tsn_cnt_cry[2]), + .LI(com_tlm_u_tlm_tx_data_src_tsn_cnt_qxu[3]), + .O(com_tlm_u_tlm_tx_data_src_tsn_cnt_s[3]) + ); + FDRE com_tlm_u_tlm_tx_data_src_tsn_cnt_3_ ( + .CE(com_tlm_u_tlm_tx_data_src_lnk_teof_o_5), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_data_src_tsn_cnt_s[3]), + .Q(com_tlm_u_tlm_tx_data_src_tsn_cnt[3]), + .R(plm_link_up_i) + ); + MUXCY_L com_tlm_u_tlm_tx_data_src_tsn_cnt_cry_4_ ( + .CI(com_tlm_u_tlm_tx_data_src_tsn_cnt_cry[3]), + .DI(com_tlm_u_tlm_tx_data_src_GND_3144), + .LO(com_tlm_u_tlm_tx_data_src_tsn_cnt_cry[4]), + .S(com_tlm_u_tlm_tx_data_src_tsn_cnt_qxu[4]) + ); + XORCY com_tlm_u_tlm_tx_data_src_tsn_cnt_s_4_ ( + .CI(com_tlm_u_tlm_tx_data_src_tsn_cnt_cry[3]), + .LI(com_tlm_u_tlm_tx_data_src_tsn_cnt_qxu[4]), + .O(com_tlm_u_tlm_tx_data_src_tsn_cnt_s[4]) + ); + FDRE com_tlm_u_tlm_tx_data_src_tsn_cnt_4_ ( + .CE(com_tlm_u_tlm_tx_data_src_lnk_teof_o_5), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_data_src_tsn_cnt_s[4]), + .Q(com_tlm_u_tlm_tx_data_src_tsn_cnt[4]), + .R(plm_link_up_i) + ); + MUXCY_L com_tlm_u_tlm_tx_data_src_tsn_cnt_cry_5_ ( + .CI(com_tlm_u_tlm_tx_data_src_tsn_cnt_cry[4]), + .DI(com_tlm_u_tlm_tx_data_src_GND_3144), + .LO(com_tlm_u_tlm_tx_data_src_tsn_cnt_cry[5]), + .S(com_tlm_u_tlm_tx_data_src_tsn_cnt_qxu[5]) + ); + XORCY com_tlm_u_tlm_tx_data_src_tsn_cnt_s_5_ ( + .CI(com_tlm_u_tlm_tx_data_src_tsn_cnt_cry[4]), + .LI(com_tlm_u_tlm_tx_data_src_tsn_cnt_qxu[5]), + .O(com_tlm_u_tlm_tx_data_src_tsn_cnt_s[5]) + ); + FDRE com_tlm_u_tlm_tx_data_src_tsn_cnt_5_ ( + .CE(com_tlm_u_tlm_tx_data_src_lnk_teof_o_5), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_data_src_tsn_cnt_s[5]), + .Q(com_tlm_u_tlm_tx_data_src_tsn_cnt[5]), + .R(plm_link_up_i) + ); + MUXCY_L com_tlm_u_tlm_tx_data_src_tsn_cnt_cry_6_ ( + .CI(com_tlm_u_tlm_tx_data_src_tsn_cnt_cry[5]), + .DI(com_tlm_u_tlm_tx_data_src_GND_3144), + .LO(com_tlm_u_tlm_tx_data_src_tsn_cnt_cry[6]), + .S(com_tlm_u_tlm_tx_data_src_tsn_cnt_qxu[6]) + ); + XORCY com_tlm_u_tlm_tx_data_src_tsn_cnt_s_6_ ( + .CI(com_tlm_u_tlm_tx_data_src_tsn_cnt_cry[5]), + .LI(com_tlm_u_tlm_tx_data_src_tsn_cnt_qxu[6]), + .O(com_tlm_u_tlm_tx_data_src_tsn_cnt_s[6]) + ); + FDRE com_tlm_u_tlm_tx_data_src_tsn_cnt_6_ ( + .CE(com_tlm_u_tlm_tx_data_src_lnk_teof_o_5), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_data_src_tsn_cnt_s[6]), + .Q(com_tlm_u_tlm_tx_data_src_tsn_cnt[6]), + .R(plm_link_up_i) + ); + MUXCY_L com_tlm_u_tlm_tx_data_src_tsn_cnt_cry_7_ ( + .CI(com_tlm_u_tlm_tx_data_src_tsn_cnt_cry[6]), + .DI(com_tlm_u_tlm_tx_data_src_GND_3144), + .LO(com_tlm_u_tlm_tx_data_src_tsn_cnt_cry[7]), + .S(com_tlm_u_tlm_tx_data_src_tsn_cnt_qxu[7]) + ); + XORCY com_tlm_u_tlm_tx_data_src_tsn_cnt_s_7_ ( + .CI(com_tlm_u_tlm_tx_data_src_tsn_cnt_cry[6]), + .LI(com_tlm_u_tlm_tx_data_src_tsn_cnt_qxu[7]), + .O(com_tlm_u_tlm_tx_data_src_tsn_cnt_s[7]) + ); + FDRE com_tlm_u_tlm_tx_data_src_tsn_cnt_7_ ( + .CE(com_tlm_u_tlm_tx_data_src_lnk_teof_o_5), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_data_src_tsn_cnt_s[7]), + .Q(com_tlm_u_tlm_tx_data_src_tsn_cnt[7]), + .R(plm_link_up_i) + ); + MUXCY_L com_tlm_u_tlm_tx_data_src_tsn_cnt_cry_8_ ( + .CI(com_tlm_u_tlm_tx_data_src_tsn_cnt_cry[7]), + .DI(com_tlm_u_tlm_tx_data_src_GND_3144), + .LO(com_tlm_u_tlm_tx_data_src_tsn_cnt_cry[8]), + .S(com_tlm_u_tlm_tx_data_src_tsn_cnt_qxu[8]) + ); + XORCY com_tlm_u_tlm_tx_data_src_tsn_cnt_s_8_ ( + .CI(com_tlm_u_tlm_tx_data_src_tsn_cnt_cry[7]), + .LI(com_tlm_u_tlm_tx_data_src_tsn_cnt_qxu[8]), + .O(com_tlm_u_tlm_tx_data_src_tsn_cnt_s[8]) + ); + FDRE com_tlm_u_tlm_tx_data_src_tsn_cnt_8_ ( + .CE(com_tlm_u_tlm_tx_data_src_lnk_teof_o_5), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_data_src_tsn_cnt_s[8]), + .Q(com_tlm_u_tlm_tx_data_src_tsn_cnt[8]), + .R(plm_link_up_i) + ); + MUXCY_L com_tlm_u_tlm_tx_data_src_tsn_cnt_cry_9_ ( + .CI(com_tlm_u_tlm_tx_data_src_tsn_cnt_cry[8]), + .DI(com_tlm_u_tlm_tx_data_src_GND_3144), + .LO(com_tlm_u_tlm_tx_data_src_tsn_cnt_cry[9]), + .S(com_tlm_u_tlm_tx_data_src_tsn_cnt_qxu[9]) + ); + XORCY com_tlm_u_tlm_tx_data_src_tsn_cnt_s_9_ ( + .CI(com_tlm_u_tlm_tx_data_src_tsn_cnt_cry[8]), + .LI(com_tlm_u_tlm_tx_data_src_tsn_cnt_qxu[9]), + .O(com_tlm_u_tlm_tx_data_src_tsn_cnt_s[9]) + ); + FDRE com_tlm_u_tlm_tx_data_src_tsn_cnt_9_ ( + .CE(com_tlm_u_tlm_tx_data_src_lnk_teof_o_5), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_data_src_tsn_cnt_s[9]), + .Q(com_tlm_u_tlm_tx_data_src_tsn_cnt[9]), + .R(plm_link_up_i) + ); + MUXCY_L com_tlm_u_tlm_tx_data_src_tsn_cnt_cry_10_ ( + .CI(com_tlm_u_tlm_tx_data_src_tsn_cnt_cry[9]), + .DI(com_tlm_u_tlm_tx_data_src_GND_3144), + .LO(com_tlm_u_tlm_tx_data_src_tsn_cnt_cry[10]), + .S(com_tlm_u_tlm_tx_data_src_tsn_cnt_qxu[10]) + ); + XORCY com_tlm_u_tlm_tx_data_src_tsn_cnt_s_10_ ( + .CI(com_tlm_u_tlm_tx_data_src_tsn_cnt_cry[9]), + .LI(com_tlm_u_tlm_tx_data_src_tsn_cnt_qxu[10]), + .O(com_tlm_u_tlm_tx_data_src_tsn_cnt_s[10]) + ); + FDRE com_tlm_u_tlm_tx_data_src_tsn_cnt_10_ ( + .CE(com_tlm_u_tlm_tx_data_src_lnk_teof_o_5), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_data_src_tsn_cnt_s[10]), + .Q(com_tlm_u_tlm_tx_data_src_tsn_cnt[10]), + .R(plm_link_up_i) + ); + XORCY com_tlm_u_tlm_tx_data_src_tsn_cnt_s_11_ ( + .CI(com_tlm_u_tlm_tx_data_src_tsn_cnt_cry[10]), + .LI(com_tlm_u_tlm_tx_data_src_tsn_cnt_qxu[11]), + .O(com_tlm_u_tlm_tx_data_src_tsn_cnt_s[11]) + ); + FDRE com_tlm_u_tlm_tx_data_src_tsn_cnt_11_ ( + .CE(com_tlm_u_tlm_tx_data_src_lnk_teof_o_5), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_data_src_tsn_cnt_s[11]), + .Q(com_tlm_u_tlm_tx_data_src_tsn_cnt[11]), + .R(plm_link_up_i) + ); + defparam com_tlm_u_tlm_tx_data_src_stat_tlp_wr_ep_o_5_0_a2_i_0_o2.INIT = 4'h4; + LUT2 com_tlm_u_tlm_tx_data_src_stat_tlp_wr_ep_o_5_0_a2_i_0_o2 ( + .I0(com_tlm_u_tlm_tx_vc0_retry), + .I1(com_tlm_u_tlm_tx_vc0_sof), + .O(com_tlm_u_tlm_tx_data_src_N_57190_i) + ); + defparam com_tlm_u_tlm_tx_data_src_un5_lnk_tsrc_rdy_o_0_a2_0_a3_0_a3.INIT = 4'h4; + LUT2 com_tlm_u_tlm_tx_data_src_un5_lnk_tsrc_rdy_o_0_a2_0_a3_0_a3 ( + .I0(com_lnk_tdst_rdy_n), + .I1(com_tlm_u_tlm_tx_vc0_src_rdy), + .O(com_tlm_u_tlm_tx_data_src_un5_lnk_tsrc_rdy_o_0_a2_0_a3_0_a3_3148) + ); + defparam com_tlm_u_tlm_tx_data_src_N_59170_i.INIT = 4'h7; + LUT2 com_tlm_u_tlm_tx_data_src_N_59170_i ( + .I0(com_lnk_tdst_rdy_n), + .I1(com_tlm_u_tlm_tx_data_src_lnk_tsrc_rdy), + .O(com_tlm_u_tlm_tx_data_src_N_59170_i_3145) + ); + defparam com_tlm_u_tlm_tx_data_src_lnk_teof_o_5_0_a2_0_a2_0_a2.INIT = 4'h8; + LUT2 com_tlm_u_tlm_tx_data_src_lnk_teof_o_5_0_a2_0_a2_0_a2 ( + .I0(com_tlm_u_tlm_tx_data_src_un5_lnk_tsrc_rdy_o_0_a2_0_a3_0_a3_3148), + .I1(com_tlm_u_tlm_tx_vc0_eof), + .O(com_tlm_u_tlm_tx_data_src_lnk_teof_o_5) + ); + defparam com_tlm_u_tlm_tx_data_src_lnk_ttrans_seq_i_0_.INIT = 4'h1; + LUT1_L com_tlm_u_tlm_tx_data_src_lnk_ttrans_seq_i_0_ ( + .I0(com_lnk_ttrans_seq[0]), + .LO(com_lnk_ttrans_seq_i[0]) + ); + defparam com_tlm_u_tlm_tx_data_src_lnk_teof_i.INIT = 4'h1; + LUT1_L com_tlm_u_tlm_tx_data_src_lnk_teof_i ( + .I0(com_lnk_teof), + .LO(com_lnk_teof_i) + ); + defparam com_tlm_u_tlm_tx_data_src_lnk_tsof_i.INIT = 4'h1; + LUT1_L com_tlm_u_tlm_tx_data_src_lnk_tsof_i ( + .I0(com_lnk_tsof), + .LO(com_lnk_tsof_i) + ); + defparam com_tlm_u_tlm_tx_data_src_lnk_ttrans_seq_o_4_i_m2_i_m3_i_m3_0_11_.INIT = 8'hE2; + LUT3_L com_tlm_u_tlm_tx_data_src_lnk_ttrans_seq_o_4_i_m2_i_m3_i_m3_0_11_ ( + .I0(com_tlm_u_tlm_tx_data_src_tsn_cnt[11]), + .I1(com_tlm_u_tlm_tx_vc0_retry), + .I2(com_tlm_u_tlm_tx_vc0_retry_tsn[11]), + .LO(com_tlm_u_tlm_tx_data_src_lnk_ttrans_seq_o_4_i_m2_i_m3_i_m3_0[11]) + ); + defparam com_tlm_u_tlm_tx_data_src_lnk_ttrans_seq_o_4_i_m2_i_m3_i_m3_0_10_.INIT = 8'hE2; + LUT3_L com_tlm_u_tlm_tx_data_src_lnk_ttrans_seq_o_4_i_m2_i_m3_i_m3_0_10_ ( + .I0(com_tlm_u_tlm_tx_data_src_tsn_cnt[10]), + .I1(com_tlm_u_tlm_tx_vc0_retry), + .I2(com_tlm_u_tlm_tx_vc0_retry_tsn[10]), + .LO(com_tlm_u_tlm_tx_data_src_lnk_ttrans_seq_o_4_i_m2_i_m3_i_m3_0[10]) + ); + defparam com_tlm_u_tlm_tx_data_src_lnk_ttrans_seq_o_4_i_m2_i_m3_i_m3_0_9_.INIT = 8'hE2; + LUT3_L com_tlm_u_tlm_tx_data_src_lnk_ttrans_seq_o_4_i_m2_i_m3_i_m3_0_9_ ( + .I0(com_tlm_u_tlm_tx_data_src_tsn_cnt[9]), + .I1(com_tlm_u_tlm_tx_vc0_retry), + .I2(com_tlm_u_tlm_tx_vc0_retry_tsn[9]), + .LO(com_tlm_u_tlm_tx_data_src_lnk_ttrans_seq_o_4_i_m2_i_m3_i_m3_0[9]) + ); + defparam com_tlm_u_tlm_tx_data_src_lnk_ttrans_seq_o_4_i_m2_i_m3_i_m3_0_8_.INIT = 8'hE2; + LUT3_L com_tlm_u_tlm_tx_data_src_lnk_ttrans_seq_o_4_i_m2_i_m3_i_m3_0_8_ ( + .I0(com_tlm_u_tlm_tx_data_src_tsn_cnt[8]), + .I1(com_tlm_u_tlm_tx_vc0_retry), + .I2(com_tlm_u_tlm_tx_vc0_retry_tsn[8]), + .LO(com_tlm_u_tlm_tx_data_src_lnk_ttrans_seq_o_4_i_m2_i_m3_i_m3_0[8]) + ); + defparam com_tlm_u_tlm_tx_data_src_lnk_ttrans_seq_o_4_i_m2_i_m3_i_m3_0_7_.INIT = 8'hE2; + LUT3_L com_tlm_u_tlm_tx_data_src_lnk_ttrans_seq_o_4_i_m2_i_m3_i_m3_0_7_ ( + .I0(com_tlm_u_tlm_tx_data_src_tsn_cnt[7]), + .I1(com_tlm_u_tlm_tx_vc0_retry), + .I2(com_tlm_u_tlm_tx_vc0_retry_tsn[7]), + .LO(com_tlm_u_tlm_tx_data_src_lnk_ttrans_seq_o_4_i_m2_i_m3_i_m3_0[7]) + ); + defparam com_tlm_u_tlm_tx_data_src_lnk_ttrans_seq_o_4_i_m2_i_m3_i_m3_0_6_.INIT = 8'hE2; + LUT3_L com_tlm_u_tlm_tx_data_src_lnk_ttrans_seq_o_4_i_m2_i_m3_i_m3_0_6_ ( + .I0(com_tlm_u_tlm_tx_data_src_tsn_cnt[6]), + .I1(com_tlm_u_tlm_tx_vc0_retry), + .I2(com_tlm_u_tlm_tx_vc0_retry_tsn[6]), + .LO(com_tlm_u_tlm_tx_data_src_lnk_ttrans_seq_o_4_i_m2_i_m3_i_m3_0[6]) + ); + defparam com_tlm_u_tlm_tx_data_src_lnk_ttrans_seq_o_4_i_m2_i_m3_i_m3_0_5_.INIT = 8'hE2; + LUT3_L com_tlm_u_tlm_tx_data_src_lnk_ttrans_seq_o_4_i_m2_i_m3_i_m3_0_5_ ( + .I0(com_tlm_u_tlm_tx_data_src_tsn_cnt[5]), + .I1(com_tlm_u_tlm_tx_vc0_retry), + .I2(com_tlm_u_tlm_tx_vc0_retry_tsn[5]), + .LO(com_tlm_u_tlm_tx_data_src_lnk_ttrans_seq_o_4_i_m2_i_m3_i_m3_0[5]) + ); + defparam com_tlm_u_tlm_tx_data_src_lnk_ttrans_seq_o_4_i_m2_i_m3_i_m3_0_4_.INIT = 8'hE2; + LUT3_L com_tlm_u_tlm_tx_data_src_lnk_ttrans_seq_o_4_i_m2_i_m3_i_m3_0_4_ ( + .I0(com_tlm_u_tlm_tx_data_src_tsn_cnt[4]), + .I1(com_tlm_u_tlm_tx_vc0_retry), + .I2(com_tlm_u_tlm_tx_vc0_retry_tsn[4]), + .LO(com_tlm_u_tlm_tx_data_src_lnk_ttrans_seq_o_4_i_m2_i_m3_i_m3_0[4]) + ); + defparam com_tlm_u_tlm_tx_data_src_lnk_ttrans_seq_o_4_i_m2_i_m3_i_m3_0_3_.INIT = 8'hE2; + LUT3_L com_tlm_u_tlm_tx_data_src_lnk_ttrans_seq_o_4_i_m2_i_m3_i_m3_0_3_ ( + .I0(com_tlm_u_tlm_tx_data_src_tsn_cnt[3]), + .I1(com_tlm_u_tlm_tx_vc0_retry), + .I2(com_tlm_u_tlm_tx_vc0_retry_tsn[3]), + .LO(com_tlm_u_tlm_tx_data_src_lnk_ttrans_seq_o_4_i_m2_i_m3_i_m3_0[3]) + ); + defparam com_tlm_u_tlm_tx_data_src_lnk_ttrans_seq_o_4_i_m2_i_m3_i_m3_0_2_.INIT = 8'hE2; + LUT3_L com_tlm_u_tlm_tx_data_src_lnk_ttrans_seq_o_4_i_m2_i_m3_i_m3_0_2_ ( + .I0(com_tlm_u_tlm_tx_data_src_tsn_cnt[2]), + .I1(com_tlm_u_tlm_tx_vc0_retry), + .I2(com_tlm_u_tlm_tx_vc0_retry_tsn[2]), + .LO(com_tlm_u_tlm_tx_data_src_lnk_ttrans_seq_o_4_i_m2_i_m3_i_m3_0[2]) + ); + defparam com_tlm_u_tlm_tx_data_src_lnk_ttrans_seq_o_4_i_m2_i_m3_i_m3_0_1_.INIT = 8'hE2; + LUT3_L com_tlm_u_tlm_tx_data_src_lnk_ttrans_seq_o_4_i_m2_i_m3_i_m3_0_1_ ( + .I0(com_tlm_u_tlm_tx_data_src_tsn_cnt[1]), + .I1(com_tlm_u_tlm_tx_vc0_retry), + .I2(com_tlm_u_tlm_tx_vc0_retry_tsn[1]), + .LO(com_tlm_u_tlm_tx_data_src_lnk_ttrans_seq_o_4_i_m2_i_m3_i_m3_0[1]) + ); + defparam com_tlm_u_tlm_tx_data_src_lnk_ttrans_seq_o_4_i_m2_i_m3_i_m3_0_0_.INIT = 8'hE2; + LUT3_L com_tlm_u_tlm_tx_data_src_lnk_ttrans_seq_o_4_i_m2_i_m3_i_m3_0_0_ ( + .I0(com_tlm_u_tlm_tx_data_src_tsn_cnt[0]), + .I1(com_tlm_u_tlm_tx_vc0_retry), + .I2(com_tlm_u_tlm_tx_vc0_retry_tsn[0]), + .LO(com_tlm_u_tlm_tx_data_src_lnk_ttrans_seq_o_4_i_m2_i_m3_i_m3_0[0]) + ); + defparam com_tlm_u_tlm_tx_data_src_lnk_tretry_o_5_0_a2_0_a2_0_a2.INIT = 4'h8; + LUT2_L com_tlm_u_tlm_tx_data_src_lnk_tretry_o_5_0_a2_0_a2_0_a2 ( + .I0(com_tlm_u_tlm_tx_data_src_un5_lnk_tsrc_rdy_o_0_a2_0_a3_0_a3_3148), + .I1(com_tlm_u_tlm_tx_vc0_retry), + .LO(com_tlm_u_tlm_tx_data_src_lnk_tretry_o_5) + ); + defparam com_tlm_u_tlm_tx_data_src_lnk_tsof_o_5_0_a2_0_a2_0_a2.INIT = 4'h8; + LUT2_L com_tlm_u_tlm_tx_data_src_lnk_tsof_o_5_0_a2_0_a2_0_a2 ( + .I0(com_tlm_u_tlm_tx_data_src_un5_lnk_tsrc_rdy_o_0_a2_0_a3_0_a3_3148), + .I1(com_tlm_u_tlm_tx_vc0_sof), + .LO(com_tlm_u_tlm_tx_data_src_lnk_tsof_o_5) + ); + defparam com_tlm_u_tlm_tx_data_src_N_59176_i.INIT = 4'hD; + LUT2_L com_tlm_u_tlm_tx_data_src_N_59176_i ( + .I0(com_tlm_u_tlm_tx_data_src_un5_lnk_tsrc_rdy_o_0_a2_0_a3_0_a3_3148), + .I1(com_tlm_u_tlm_tx_vc0_rem), + .LO(com_tlm_u_tlm_tx_data_src_N_59176_i_3146) + ); + defparam com_tlm_u_tlm_tx_data_src_N_59169_i.INIT = 8'hEA; + LUT3_L com_tlm_u_tlm_tx_data_src_N_59169_i ( + .I0(com_tlm_u_tlm_tx_vc0_d[46]), + .I1(com_tlm_u_tlm_tx_vc0_errfwd), + .I2(com_tlm_u_tlm_tx_vc0_sof), + .LO(com_tlm_u_tlm_tx_data_src_N_59169_i_3147) + ); + defparam com_tlm_u_tlm_tx_data_src_stat_tlp_wr_ep_o_5_0_a2_i_0.INIT = 16'h8880; + LUT4_L com_tlm_u_tlm_tx_data_src_stat_tlp_wr_ep_o_5_0_a2_i_0 ( + .I0(com_tlm_u_tlm_tx_data_src_N_57190_i), + .I1(com_tlm_u_tlm_tx_data_src_un5_lnk_tsrc_rdy_o_0_a2_0_a3_0_a3_3148), + .I2(com_tlm_u_tlm_tx_vc0_d[46]), + .I3(com_tlm_u_tlm_tx_vc0_errfwd), + .LO(com_tlm_u_tlm_tx_data_src_N_30212_i) + ); + FD com_tlm_u_tlm_tx_data_src_buf_num_o_3_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_buf_num[3]), + .Q(com_tlm_u_tlm_tx_ds_buf_num[3]) + ); + FD com_tlm_u_tlm_tx_data_src_buf_num_o_2_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_buf_num[2]), + .Q(com_tlm_u_tlm_tx_ds_buf_num[2]) + ); + FD com_tlm_u_tlm_tx_data_src_buf_num_o_1_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_buf_num[1]), + .Q(com_tlm_u_tlm_tx_ds_buf_num[1]) + ); + FD com_tlm_u_tlm_tx_data_src_buf_num_o_0_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_buf_num[0]), + .Q(com_tlm_u_tlm_tx_ds_buf_num[0]) + ); + FDE com_tlm_u_tlm_tx_data_src_lnk_td_o_63_ ( + .CE(com_tlm_u_tlm_tx_data_src_un5_lnk_tsrc_rdy_o_0_a2_0_a3_0_a3_3148), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_d[63]), + .Q(com_lnk_td[63]) + ); + FDE com_tlm_u_tlm_tx_data_src_lnk_td_o_62_ ( + .CE(com_tlm_u_tlm_tx_data_src_un5_lnk_tsrc_rdy_o_0_a2_0_a3_0_a3_3148), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_d[62]), + .Q(com_lnk_td[62]) + ); + FDE com_tlm_u_tlm_tx_data_src_lnk_td_o_61_ ( + .CE(com_tlm_u_tlm_tx_data_src_un5_lnk_tsrc_rdy_o_0_a2_0_a3_0_a3_3148), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_d[61]), + .Q(com_lnk_td[61]) + ); + FDE com_tlm_u_tlm_tx_data_src_lnk_td_o_60_ ( + .CE(com_tlm_u_tlm_tx_data_src_un5_lnk_tsrc_rdy_o_0_a2_0_a3_0_a3_3148), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_d[60]), + .Q(com_lnk_td[60]) + ); + FDE com_tlm_u_tlm_tx_data_src_lnk_td_o_59_ ( + .CE(com_tlm_u_tlm_tx_data_src_un5_lnk_tsrc_rdy_o_0_a2_0_a3_0_a3_3148), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_d[59]), + .Q(com_lnk_td[59]) + ); + FDE com_tlm_u_tlm_tx_data_src_lnk_td_o_58_ ( + .CE(com_tlm_u_tlm_tx_data_src_un5_lnk_tsrc_rdy_o_0_a2_0_a3_0_a3_3148), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_d[58]), + .Q(com_lnk_td[58]) + ); + FDE com_tlm_u_tlm_tx_data_src_lnk_td_o_57_ ( + .CE(com_tlm_u_tlm_tx_data_src_un5_lnk_tsrc_rdy_o_0_a2_0_a3_0_a3_3148), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_d[57]), + .Q(com_lnk_td[57]) + ); + FDE com_tlm_u_tlm_tx_data_src_lnk_td_o_56_ ( + .CE(com_tlm_u_tlm_tx_data_src_un5_lnk_tsrc_rdy_o_0_a2_0_a3_0_a3_3148), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_d[56]), + .Q(com_lnk_td[56]) + ); + FDE com_tlm_u_tlm_tx_data_src_lnk_td_o_55_ ( + .CE(com_tlm_u_tlm_tx_data_src_un5_lnk_tsrc_rdy_o_0_a2_0_a3_0_a3_3148), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_d[55]), + .Q(com_lnk_td[55]) + ); + FDE com_tlm_u_tlm_tx_data_src_lnk_td_o_54_ ( + .CE(com_tlm_u_tlm_tx_data_src_un5_lnk_tsrc_rdy_o_0_a2_0_a3_0_a3_3148), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_d[54]), + .Q(com_lnk_td[54]) + ); + FDE com_tlm_u_tlm_tx_data_src_lnk_td_o_53_ ( + .CE(com_tlm_u_tlm_tx_data_src_un5_lnk_tsrc_rdy_o_0_a2_0_a3_0_a3_3148), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_d[53]), + .Q(com_lnk_td[53]) + ); + FDE com_tlm_u_tlm_tx_data_src_lnk_td_o_52_ ( + .CE(com_tlm_u_tlm_tx_data_src_un5_lnk_tsrc_rdy_o_0_a2_0_a3_0_a3_3148), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_d[52]), + .Q(com_lnk_td[52]) + ); + FDE com_tlm_u_tlm_tx_data_src_lnk_td_o_51_ ( + .CE(com_tlm_u_tlm_tx_data_src_un5_lnk_tsrc_rdy_o_0_a2_0_a3_0_a3_3148), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_d[51]), + .Q(com_lnk_td[51]) + ); + FDE com_tlm_u_tlm_tx_data_src_lnk_td_o_50_ ( + .CE(com_tlm_u_tlm_tx_data_src_un5_lnk_tsrc_rdy_o_0_a2_0_a3_0_a3_3148), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_d[50]), + .Q(com_lnk_td[50]) + ); + FDE com_tlm_u_tlm_tx_data_src_lnk_td_o_49_ ( + .CE(com_tlm_u_tlm_tx_data_src_un5_lnk_tsrc_rdy_o_0_a2_0_a3_0_a3_3148), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_d[49]), + .Q(com_lnk_td[49]) + ); + FDE com_tlm_u_tlm_tx_data_src_lnk_td_o_48_ ( + .CE(com_tlm_u_tlm_tx_data_src_un5_lnk_tsrc_rdy_o_0_a2_0_a3_0_a3_3148), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_d[48]), + .Q(com_lnk_td[48]) + ); + FDE com_tlm_u_tlm_tx_data_src_lnk_td_o_47_ ( + .CE(com_tlm_u_tlm_tx_data_src_un5_lnk_tsrc_rdy_o_0_a2_0_a3_0_a3_3148), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_d[47]), + .Q(com_lnk_td[47]) + ); + FDE com_tlm_u_tlm_tx_data_src_lnk_td_o_46_ ( + .CE(com_tlm_u_tlm_tx_data_src_un5_lnk_tsrc_rdy_o_0_a2_0_a3_0_a3_3148), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_data_src_N_59169_i_3147), + .Q(com_lnk_td[46]) + ); + FDE com_tlm_u_tlm_tx_data_src_lnk_td_o_45_ ( + .CE(com_tlm_u_tlm_tx_data_src_un5_lnk_tsrc_rdy_o_0_a2_0_a3_0_a3_3148), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_d[45]), + .Q(com_lnk_td[45]) + ); + FDE com_tlm_u_tlm_tx_data_src_lnk_td_o_44_ ( + .CE(com_tlm_u_tlm_tx_data_src_un5_lnk_tsrc_rdy_o_0_a2_0_a3_0_a3_3148), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_d[44]), + .Q(com_lnk_td[44]) + ); + FDE com_tlm_u_tlm_tx_data_src_lnk_td_o_43_ ( + .CE(com_tlm_u_tlm_tx_data_src_un5_lnk_tsrc_rdy_o_0_a2_0_a3_0_a3_3148), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_d[43]), + .Q(com_lnk_td[43]) + ); + FDE com_tlm_u_tlm_tx_data_src_lnk_td_o_42_ ( + .CE(com_tlm_u_tlm_tx_data_src_un5_lnk_tsrc_rdy_o_0_a2_0_a3_0_a3_3148), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_d[42]), + .Q(com_lnk_td[42]) + ); + FDE com_tlm_u_tlm_tx_data_src_lnk_td_o_41_ ( + .CE(com_tlm_u_tlm_tx_data_src_un5_lnk_tsrc_rdy_o_0_a2_0_a3_0_a3_3148), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_d[41]), + .Q(com_lnk_td[41]) + ); + FDE com_tlm_u_tlm_tx_data_src_lnk_td_o_40_ ( + .CE(com_tlm_u_tlm_tx_data_src_un5_lnk_tsrc_rdy_o_0_a2_0_a3_0_a3_3148), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_d[40]), + .Q(com_lnk_td[40]) + ); + FDE com_tlm_u_tlm_tx_data_src_lnk_td_o_39_ ( + .CE(com_tlm_u_tlm_tx_data_src_un5_lnk_tsrc_rdy_o_0_a2_0_a3_0_a3_3148), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_d[39]), + .Q(com_lnk_td[39]) + ); + FDE com_tlm_u_tlm_tx_data_src_lnk_td_o_38_ ( + .CE(com_tlm_u_tlm_tx_data_src_un5_lnk_tsrc_rdy_o_0_a2_0_a3_0_a3_3148), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_d[38]), + .Q(com_lnk_td[38]) + ); + FDE com_tlm_u_tlm_tx_data_src_lnk_td_o_37_ ( + .CE(com_tlm_u_tlm_tx_data_src_un5_lnk_tsrc_rdy_o_0_a2_0_a3_0_a3_3148), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_d[37]), + .Q(com_lnk_td[37]) + ); + FDE com_tlm_u_tlm_tx_data_src_lnk_td_o_36_ ( + .CE(com_tlm_u_tlm_tx_data_src_un5_lnk_tsrc_rdy_o_0_a2_0_a3_0_a3_3148), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_d[36]), + .Q(com_lnk_td[36]) + ); + FDE com_tlm_u_tlm_tx_data_src_lnk_td_o_35_ ( + .CE(com_tlm_u_tlm_tx_data_src_un5_lnk_tsrc_rdy_o_0_a2_0_a3_0_a3_3148), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_d[35]), + .Q(com_lnk_td[35]) + ); + FDE com_tlm_u_tlm_tx_data_src_lnk_td_o_34_ ( + .CE(com_tlm_u_tlm_tx_data_src_un5_lnk_tsrc_rdy_o_0_a2_0_a3_0_a3_3148), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_d[34]), + .Q(com_lnk_td[34]) + ); + FDE com_tlm_u_tlm_tx_data_src_lnk_td_o_33_ ( + .CE(com_tlm_u_tlm_tx_data_src_un5_lnk_tsrc_rdy_o_0_a2_0_a3_0_a3_3148), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_d[33]), + .Q(com_lnk_td[33]) + ); + FDE com_tlm_u_tlm_tx_data_src_lnk_td_o_32_ ( + .CE(com_tlm_u_tlm_tx_data_src_un5_lnk_tsrc_rdy_o_0_a2_0_a3_0_a3_3148), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_d[32]), + .Q(com_lnk_td[32]) + ); + FDE com_tlm_u_tlm_tx_data_src_lnk_td_o_31_ ( + .CE(com_tlm_u_tlm_tx_data_src_un5_lnk_tsrc_rdy_o_0_a2_0_a3_0_a3_3148), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_d[31]), + .Q(com_lnk_td[31]) + ); + FDE com_tlm_u_tlm_tx_data_src_lnk_td_o_30_ ( + .CE(com_tlm_u_tlm_tx_data_src_un5_lnk_tsrc_rdy_o_0_a2_0_a3_0_a3_3148), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_d[30]), + .Q(com_lnk_td[30]) + ); + FDE com_tlm_u_tlm_tx_data_src_lnk_td_o_29_ ( + .CE(com_tlm_u_tlm_tx_data_src_un5_lnk_tsrc_rdy_o_0_a2_0_a3_0_a3_3148), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_d[29]), + .Q(com_lnk_td[29]) + ); + FDE com_tlm_u_tlm_tx_data_src_lnk_td_o_28_ ( + .CE(com_tlm_u_tlm_tx_data_src_un5_lnk_tsrc_rdy_o_0_a2_0_a3_0_a3_3148), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_d[28]), + .Q(com_lnk_td[28]) + ); + FDE com_tlm_u_tlm_tx_data_src_lnk_td_o_27_ ( + .CE(com_tlm_u_tlm_tx_data_src_un5_lnk_tsrc_rdy_o_0_a2_0_a3_0_a3_3148), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_d[27]), + .Q(com_lnk_td[27]) + ); + FDE com_tlm_u_tlm_tx_data_src_lnk_td_o_26_ ( + .CE(com_tlm_u_tlm_tx_data_src_un5_lnk_tsrc_rdy_o_0_a2_0_a3_0_a3_3148), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_d[26]), + .Q(com_lnk_td[26]) + ); + FDE com_tlm_u_tlm_tx_data_src_lnk_td_o_25_ ( + .CE(com_tlm_u_tlm_tx_data_src_un5_lnk_tsrc_rdy_o_0_a2_0_a3_0_a3_3148), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_d[25]), + .Q(com_lnk_td[25]) + ); + FDE com_tlm_u_tlm_tx_data_src_lnk_td_o_24_ ( + .CE(com_tlm_u_tlm_tx_data_src_un5_lnk_tsrc_rdy_o_0_a2_0_a3_0_a3_3148), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_d[24]), + .Q(com_lnk_td[24]) + ); + FDE com_tlm_u_tlm_tx_data_src_lnk_td_o_23_ ( + .CE(com_tlm_u_tlm_tx_data_src_un5_lnk_tsrc_rdy_o_0_a2_0_a3_0_a3_3148), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_d[23]), + .Q(com_lnk_td[23]) + ); + FDE com_tlm_u_tlm_tx_data_src_lnk_td_o_22_ ( + .CE(com_tlm_u_tlm_tx_data_src_un5_lnk_tsrc_rdy_o_0_a2_0_a3_0_a3_3148), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_d[22]), + .Q(com_lnk_td[22]) + ); + FDE com_tlm_u_tlm_tx_data_src_lnk_td_o_21_ ( + .CE(com_tlm_u_tlm_tx_data_src_un5_lnk_tsrc_rdy_o_0_a2_0_a3_0_a3_3148), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_d[21]), + .Q(com_lnk_td[21]) + ); + FDE com_tlm_u_tlm_tx_data_src_lnk_td_o_20_ ( + .CE(com_tlm_u_tlm_tx_data_src_un5_lnk_tsrc_rdy_o_0_a2_0_a3_0_a3_3148), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_d[20]), + .Q(com_lnk_td[20]) + ); + FDE com_tlm_u_tlm_tx_data_src_lnk_td_o_19_ ( + .CE(com_tlm_u_tlm_tx_data_src_un5_lnk_tsrc_rdy_o_0_a2_0_a3_0_a3_3148), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_d[19]), + .Q(com_lnk_td[19]) + ); + FDE com_tlm_u_tlm_tx_data_src_lnk_td_o_18_ ( + .CE(com_tlm_u_tlm_tx_data_src_un5_lnk_tsrc_rdy_o_0_a2_0_a3_0_a3_3148), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_d[18]), + .Q(com_lnk_td[18]) + ); + FDE com_tlm_u_tlm_tx_data_src_lnk_td_o_17_ ( + .CE(com_tlm_u_tlm_tx_data_src_un5_lnk_tsrc_rdy_o_0_a2_0_a3_0_a3_3148), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_d[17]), + .Q(com_lnk_td[17]) + ); + FDE com_tlm_u_tlm_tx_data_src_lnk_td_o_16_ ( + .CE(com_tlm_u_tlm_tx_data_src_un5_lnk_tsrc_rdy_o_0_a2_0_a3_0_a3_3148), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_d[16]), + .Q(com_lnk_td[16]) + ); + FDE com_tlm_u_tlm_tx_data_src_lnk_td_o_15_ ( + .CE(com_tlm_u_tlm_tx_data_src_un5_lnk_tsrc_rdy_o_0_a2_0_a3_0_a3_3148), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_d[15]), + .Q(com_lnk_td[15]) + ); + FDE com_tlm_u_tlm_tx_data_src_lnk_td_o_14_ ( + .CE(com_tlm_u_tlm_tx_data_src_un5_lnk_tsrc_rdy_o_0_a2_0_a3_0_a3_3148), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_d[14]), + .Q(com_lnk_td[14]) + ); + FDE com_tlm_u_tlm_tx_data_src_lnk_td_o_13_ ( + .CE(com_tlm_u_tlm_tx_data_src_un5_lnk_tsrc_rdy_o_0_a2_0_a3_0_a3_3148), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_d[13]), + .Q(com_lnk_td[13]) + ); + FDE com_tlm_u_tlm_tx_data_src_lnk_td_o_12_ ( + .CE(com_tlm_u_tlm_tx_data_src_un5_lnk_tsrc_rdy_o_0_a2_0_a3_0_a3_3148), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_d[12]), + .Q(com_lnk_td[12]) + ); + FDE com_tlm_u_tlm_tx_data_src_lnk_td_o_11_ ( + .CE(com_tlm_u_tlm_tx_data_src_un5_lnk_tsrc_rdy_o_0_a2_0_a3_0_a3_3148), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_d[11]), + .Q(com_lnk_td[11]) + ); + FDE com_tlm_u_tlm_tx_data_src_lnk_td_o_10_ ( + .CE(com_tlm_u_tlm_tx_data_src_un5_lnk_tsrc_rdy_o_0_a2_0_a3_0_a3_3148), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_d[10]), + .Q(com_lnk_td[10]) + ); + FDE com_tlm_u_tlm_tx_data_src_lnk_td_o_9_ ( + .CE(com_tlm_u_tlm_tx_data_src_un5_lnk_tsrc_rdy_o_0_a2_0_a3_0_a3_3148), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_d[9]), + .Q(com_lnk_td[9]) + ); + FDE com_tlm_u_tlm_tx_data_src_lnk_td_o_8_ ( + .CE(com_tlm_u_tlm_tx_data_src_un5_lnk_tsrc_rdy_o_0_a2_0_a3_0_a3_3148), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_d[8]), + .Q(com_lnk_td[8]) + ); + FDE com_tlm_u_tlm_tx_data_src_lnk_td_o_7_ ( + .CE(com_tlm_u_tlm_tx_data_src_un5_lnk_tsrc_rdy_o_0_a2_0_a3_0_a3_3148), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_d[7]), + .Q(com_lnk_td[7]) + ); + FDE com_tlm_u_tlm_tx_data_src_lnk_td_o_6_ ( + .CE(com_tlm_u_tlm_tx_data_src_un5_lnk_tsrc_rdy_o_0_a2_0_a3_0_a3_3148), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_d[6]), + .Q(com_lnk_td[6]) + ); + FDE com_tlm_u_tlm_tx_data_src_lnk_td_o_5_ ( + .CE(com_tlm_u_tlm_tx_data_src_un5_lnk_tsrc_rdy_o_0_a2_0_a3_0_a3_3148), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_d[5]), + .Q(com_lnk_td[5]) + ); + FDE com_tlm_u_tlm_tx_data_src_lnk_td_o_4_ ( + .CE(com_tlm_u_tlm_tx_data_src_un5_lnk_tsrc_rdy_o_0_a2_0_a3_0_a3_3148), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_d[4]), + .Q(com_lnk_td[4]) + ); + FDE com_tlm_u_tlm_tx_data_src_lnk_td_o_3_ ( + .CE(com_tlm_u_tlm_tx_data_src_un5_lnk_tsrc_rdy_o_0_a2_0_a3_0_a3_3148), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_d[3]), + .Q(com_lnk_td[3]) + ); + FDE com_tlm_u_tlm_tx_data_src_lnk_td_o_2_ ( + .CE(com_tlm_u_tlm_tx_data_src_un5_lnk_tsrc_rdy_o_0_a2_0_a3_0_a3_3148), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_d[2]), + .Q(com_lnk_td[2]) + ); + FDE com_tlm_u_tlm_tx_data_src_lnk_td_o_1_ ( + .CE(com_tlm_u_tlm_tx_data_src_un5_lnk_tsrc_rdy_o_0_a2_0_a3_0_a3_3148), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_d[1]), + .Q(com_lnk_td[1]) + ); + FDE com_tlm_u_tlm_tx_data_src_lnk_td_o_0_ ( + .CE(com_tlm_u_tlm_tx_data_src_un5_lnk_tsrc_rdy_o_0_a2_0_a3_0_a3_3148), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_d[0]), + .Q(com_lnk_td[0]) + ); + defparam com_tlm_u_tlm_tx_data_src_tsn_cnt_qxu_0_11_.INIT = 4'h2; + LUT1_L com_tlm_u_tlm_tx_data_src_tsn_cnt_qxu_0_11_ ( + .I0(com_tlm_u_tlm_tx_data_src_tsn_cnt[11]), + .LO(com_tlm_u_tlm_tx_data_src_tsn_cnt_qxu[11]) + ); + defparam com_tlm_u_tlm_tx_data_src_tsn_cnt_qxu_0_10_.INIT = 4'h2; + LUT1_L com_tlm_u_tlm_tx_data_src_tsn_cnt_qxu_0_10_ ( + .I0(com_tlm_u_tlm_tx_data_src_tsn_cnt[10]), + .LO(com_tlm_u_tlm_tx_data_src_tsn_cnt_qxu[10]) + ); + defparam com_tlm_u_tlm_tx_data_src_tsn_cnt_qxu_0_9_.INIT = 4'h2; + LUT1_L com_tlm_u_tlm_tx_data_src_tsn_cnt_qxu_0_9_ ( + .I0(com_tlm_u_tlm_tx_data_src_tsn_cnt[9]), + .LO(com_tlm_u_tlm_tx_data_src_tsn_cnt_qxu[9]) + ); + defparam com_tlm_u_tlm_tx_data_src_tsn_cnt_qxu_0_8_.INIT = 4'h2; + LUT1_L com_tlm_u_tlm_tx_data_src_tsn_cnt_qxu_0_8_ ( + .I0(com_tlm_u_tlm_tx_data_src_tsn_cnt[8]), + .LO(com_tlm_u_tlm_tx_data_src_tsn_cnt_qxu[8]) + ); + defparam com_tlm_u_tlm_tx_data_src_tsn_cnt_qxu_0_7_.INIT = 4'h2; + LUT1_L com_tlm_u_tlm_tx_data_src_tsn_cnt_qxu_0_7_ ( + .I0(com_tlm_u_tlm_tx_data_src_tsn_cnt[7]), + .LO(com_tlm_u_tlm_tx_data_src_tsn_cnt_qxu[7]) + ); + defparam com_tlm_u_tlm_tx_data_src_tsn_cnt_qxu_0_6_.INIT = 4'h2; + LUT1_L com_tlm_u_tlm_tx_data_src_tsn_cnt_qxu_0_6_ ( + .I0(com_tlm_u_tlm_tx_data_src_tsn_cnt[6]), + .LO(com_tlm_u_tlm_tx_data_src_tsn_cnt_qxu[6]) + ); + defparam com_tlm_u_tlm_tx_data_src_tsn_cnt_qxu_0_5_.INIT = 4'h2; + LUT1_L com_tlm_u_tlm_tx_data_src_tsn_cnt_qxu_0_5_ ( + .I0(com_tlm_u_tlm_tx_data_src_tsn_cnt[5]), + .LO(com_tlm_u_tlm_tx_data_src_tsn_cnt_qxu[5]) + ); + defparam com_tlm_u_tlm_tx_data_src_tsn_cnt_qxu_0_4_.INIT = 4'h2; + LUT1_L com_tlm_u_tlm_tx_data_src_tsn_cnt_qxu_0_4_ ( + .I0(com_tlm_u_tlm_tx_data_src_tsn_cnt[4]), + .LO(com_tlm_u_tlm_tx_data_src_tsn_cnt_qxu[4]) + ); + defparam com_tlm_u_tlm_tx_data_src_tsn_cnt_qxu_0_3_.INIT = 4'h2; + LUT1_L com_tlm_u_tlm_tx_data_src_tsn_cnt_qxu_0_3_ ( + .I0(com_tlm_u_tlm_tx_data_src_tsn_cnt[3]), + .LO(com_tlm_u_tlm_tx_data_src_tsn_cnt_qxu[3]) + ); + defparam com_tlm_u_tlm_tx_data_src_tsn_cnt_qxu_0_2_.INIT = 4'h2; + LUT1_L com_tlm_u_tlm_tx_data_src_tsn_cnt_qxu_0_2_ ( + .I0(com_tlm_u_tlm_tx_data_src_tsn_cnt[2]), + .LO(com_tlm_u_tlm_tx_data_src_tsn_cnt_qxu[2]) + ); + defparam com_tlm_u_tlm_tx_data_src_tsn_cnt_qxu_0_1_.INIT = 4'h2; + LUT1_L com_tlm_u_tlm_tx_data_src_tsn_cnt_qxu_0_1_ ( + .I0(com_tlm_u_tlm_tx_data_src_tsn_cnt[1]), + .LO(com_tlm_u_tlm_tx_data_src_tsn_cnt_qxu[1]) + ); + defparam com_tlm_u_tlm_tx_data_src_tsn_cnt_qxu_0_0_.INIT = 4'h2; + LUT1_L com_tlm_u_tlm_tx_data_src_tsn_cnt_qxu_0_0_ ( + .I0(com_tlm_u_tlm_tx_data_src_tsn_cnt[0]), + .LO(com_tlm_u_tlm_tx_data_src_tsn_cnt_qxu[0]) + ); + defparam com_tlm_u_tlm_tx_data_src_buf_src_rdy_o_3_0_a2_0_a2_0_a2.INIT = 4'h8; + LUT2_L com_tlm_u_tlm_tx_data_src_buf_src_rdy_o_3_0_a2_0_a2_0_a2 ( + .I0(com_tlm_u_tlm_tx_data_src_N_57190_i), + .I1(com_tlm_u_tlm_tx_data_src_un5_lnk_tsrc_rdy_o_0_a2_0_a3_0_a3_3148), + .LO(com_tlm_u_tlm_tx_data_src_buf_src_rdy_o_3) + ); + defparam com_tlm_u_tlm_tx_data_src_cfg_sent_d_3_0_a2_0_a2_0_a2.INIT = 8'h80; + LUT3_L com_tlm_u_tlm_tx_data_src_cfg_sent_d_3_0_a2_0_a2_0_a2 ( + .I0(com_tlm_u_tlm_tx_vc0_cfg), + .I1(com_tlm_u_tlm_tx_data_src_un5_lnk_tsrc_rdy_o_0_a2_0_a3_0_a3_3148), + .I2(com_tlm_u_tlm_tx_data_src_N_57190_i), + .LO(com_tlm_u_tlm_tx_data_src_cfg_sent_d_3) + ); + VCC com_tlm_u_tlm_tx_ack_mgr_VCC ( + .P(com_tlm_u_tlm_tx_ack_mgr_VCC_3160) + ); + GND com_tlm_u_tlm_tx_ack_mgr_GND ( + .G(com_tlm_u_tlm_tx_ack_mgr_GND_3228) + ); + FDR com_tlm_u_tlm_tx_ack_mgr_jump_retry_tsn ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_ack_mgr_N_87598_i_3223), + .Q(com_tlm_u_tlm_tx_ack_mgr_jump_retry_tsn_3244), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_tx_ack_mgr_retry_src_rdy_o ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_ack_mgr_N_85579_i_3221), + .Q(com_tlm_u_tlm_tx_am_retry_src_rdy), + .R(plm_link_up_i) + ); + FDRSE com_tlm_u_tlm_tx_ack_mgr_retry_lock_o ( + .CE(com_tlm_u_tlm_tx_ack_mgr_N_87236_i_3189), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_ack_mgr_GND_3228), + .Q(com_tlm_u_tlm_tx_am_retry_lock), + .R(plm_link_up_i), + .S(com_tlm_u_tlm_tx_ack_mgr_N_55889_i) + ); + FDRE com_tlm_u_tlm_tx_ack_mgr_retry_tsn_o_0_ ( + .CE(com_tlm_u_tlm_tx_ack_mgr_N_87231_i_3186), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_ack_mgr_N_56649_i_3220), + .Q(com_tlm_u_tlm_tx_am_retry_tsn[0]), + .R(plm_link_up_i) + ); + FDRE com_tlm_u_tlm_tx_ack_mgr_retry_tsn_o_1_ ( + .CE(com_tlm_u_tlm_tx_ack_mgr_N_87231_i_3186), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_ack_mgr_un4_retry_tsn_o_s_1_3161), + .Q(com_tlm_u_tlm_tx_am_retry_tsn[1]), + .R(plm_link_up_i) + ); + FDRE com_tlm_u_tlm_tx_ack_mgr_retry_tsn_o_2_ ( + .CE(com_tlm_u_tlm_tx_ack_mgr_N_87231_i_3186), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_ack_mgr_un4_retry_tsn_o_s_2_3163), + .Q(com_tlm_u_tlm_tx_am_retry_tsn[2]), + .R(plm_link_up_i) + ); + FDRE com_tlm_u_tlm_tx_ack_mgr_retry_tsn_o_3_ ( + .CE(com_tlm_u_tlm_tx_ack_mgr_N_87231_i_3186), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_ack_mgr_un4_retry_tsn_o_s_3_3165), + .Q(com_tlm_u_tlm_tx_am_retry_tsn[3]), + .R(plm_link_up_i) + ); + FDRE com_tlm_u_tlm_tx_ack_mgr_retry_tsn_o_4_ ( + .CE(com_tlm_u_tlm_tx_ack_mgr_N_87231_i_3186), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_ack_mgr_un4_retry_tsn_o_s_4_3167), + .Q(com_tlm_u_tlm_tx_am_retry_tsn[4]), + .R(plm_link_up_i) + ); + FDRE com_tlm_u_tlm_tx_ack_mgr_retry_tsn_o_5_ ( + .CE(com_tlm_u_tlm_tx_ack_mgr_N_87231_i_3186), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_ack_mgr_un4_retry_tsn_o_s_5_3169), + .Q(com_tlm_u_tlm_tx_am_retry_tsn[5]), + .R(plm_link_up_i) + ); + FDRE com_tlm_u_tlm_tx_ack_mgr_retry_tsn_o_6_ ( + .CE(com_tlm_u_tlm_tx_ack_mgr_N_87231_i_3186), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_ack_mgr_un4_retry_tsn_o_s_6_3171), + .Q(com_tlm_u_tlm_tx_am_retry_tsn[6]), + .R(plm_link_up_i) + ); + FDRE com_tlm_u_tlm_tx_ack_mgr_retry_tsn_o_7_ ( + .CE(com_tlm_u_tlm_tx_ack_mgr_N_87231_i_3186), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_ack_mgr_un4_retry_tsn_o_s_7_3173), + .Q(com_tlm_u_tlm_tx_am_retry_tsn[7]), + .R(plm_link_up_i) + ); + FDRE com_tlm_u_tlm_tx_ack_mgr_retry_tsn_o_8_ ( + .CE(com_tlm_u_tlm_tx_ack_mgr_N_87231_i_3186), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_ack_mgr_un4_retry_tsn_o_s_8_3175), + .Q(com_tlm_u_tlm_tx_am_retry_tsn[8]), + .R(plm_link_up_i) + ); + FDRE com_tlm_u_tlm_tx_ack_mgr_retry_tsn_o_9_ ( + .CE(com_tlm_u_tlm_tx_ack_mgr_N_87231_i_3186), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_ack_mgr_un4_retry_tsn_o_s_9_3177), + .Q(com_tlm_u_tlm_tx_am_retry_tsn[9]), + .R(plm_link_up_i) + ); + FDRE com_tlm_u_tlm_tx_ack_mgr_retry_tsn_o_10_ ( + .CE(com_tlm_u_tlm_tx_ack_mgr_N_87231_i_3186), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_ack_mgr_un4_retry_tsn_o_s_10_3179), + .Q(com_tlm_u_tlm_tx_am_retry_tsn[10]), + .R(plm_link_up_i) + ); + FDRE com_tlm_u_tlm_tx_ack_mgr_retry_tsn_o_11_ ( + .CE(com_tlm_u_tlm_tx_ack_mgr_N_87231_i_3186), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_ack_mgr_un4_retry_tsn_o_s_11_3181), + .Q(com_tlm_u_tlm_tx_am_retry_tsn[11]), + .R(plm_link_up_i) + ); + FDRE com_tlm_u_tlm_tx_ack_mgr_nak_in_retry ( + .CE(com_tlm_u_tlm_tx_ack_mgr_N_87602_i_3188), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_ack_mgr_nak_in_retry19), + .Q(com_tlm_u_tlm_tx_ack_mgr_nak_in_retry_3224), + .R(plm_link_up_i) + ); + FDRSE com_tlm_u_tlm_tx_ack_mgr_nak_req ( + .CE(com_tlm_u_tlm_tx_ack_mgr_un1_lnk_rupdate_ack_i_0_a2_0_a2_3183), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_ack_mgr_GND_3228), + .Q(com_tlm_u_tlm_tx_ack_mgr_nak_req_3225), + .R(plm_link_up_i), + .S(com_tlm_u_tlm_tx_ack_mgr_N_55889_i) + ); + FDRE com_tlm_u_tlm_tx_ack_mgr_ack_pending_o ( + .CE(com_tlm_u_tlm_tx_ack_mgr_mgr_state_0__3185), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_ack_mgr_N_60497_i_3208), + .Q(com_tlm_u_tlm_tx_ack_pending), + .R(plm_link_up_i) + ); + FDSE com_tlm_u_tlm_tx_ack_mgr_latest_ack_tsn_0_ ( + .CE(com_tlm_u_tlm_tx_ack_mgr_N_10925_i_i_i_3227), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_lnk_tupdate_seq[0]), + .Q(com_tlm_u_tlm_tx_ack_mgr_latest_ack_tsn[0]), + .S(plm_link_up_i) + ); + FDSE com_tlm_u_tlm_tx_ack_mgr_latest_ack_tsn_1_ ( + .CE(com_tlm_u_tlm_tx_ack_mgr_N_10925_i_i_i_3227), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_lnk_tupdate_seq[1]), + .Q(com_tlm_u_tlm_tx_ack_mgr_latest_ack_tsn[1]), + .S(plm_link_up_i) + ); + FDSE com_tlm_u_tlm_tx_ack_mgr_latest_ack_tsn_2_ ( + .CE(com_tlm_u_tlm_tx_ack_mgr_N_10925_i_i_i_3227), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_lnk_tupdate_seq[2]), + .Q(com_tlm_u_tlm_tx_ack_mgr_latest_ack_tsn[2]), + .S(plm_link_up_i) + ); + FDSE com_tlm_u_tlm_tx_ack_mgr_latest_ack_tsn_3_ ( + .CE(com_tlm_u_tlm_tx_ack_mgr_N_10925_i_i_i_3227), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_lnk_tupdate_seq[3]), + .Q(com_tlm_u_tlm_tx_ack_mgr_latest_ack_tsn[3]), + .S(plm_link_up_i) + ); + FDSE com_tlm_u_tlm_tx_ack_mgr_latest_ack_tsn_4_ ( + .CE(com_tlm_u_tlm_tx_ack_mgr_N_10925_i_i_i_3227), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_lnk_tupdate_seq[4]), + .Q(com_tlm_u_tlm_tx_ack_mgr_latest_ack_tsn[4]), + .S(plm_link_up_i) + ); + FDSE com_tlm_u_tlm_tx_ack_mgr_latest_ack_tsn_5_ ( + .CE(com_tlm_u_tlm_tx_ack_mgr_N_10925_i_i_i_3227), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_lnk_tupdate_seq[5]), + .Q(com_tlm_u_tlm_tx_ack_mgr_latest_ack_tsn[5]), + .S(plm_link_up_i) + ); + FDSE com_tlm_u_tlm_tx_ack_mgr_latest_ack_tsn_6_ ( + .CE(com_tlm_u_tlm_tx_ack_mgr_N_10925_i_i_i_3227), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_lnk_tupdate_seq[6]), + .Q(com_tlm_u_tlm_tx_ack_mgr_latest_ack_tsn[6]), + .S(plm_link_up_i) + ); + FDSE com_tlm_u_tlm_tx_ack_mgr_latest_ack_tsn_7_ ( + .CE(com_tlm_u_tlm_tx_ack_mgr_N_10925_i_i_i_3227), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_lnk_tupdate_seq[7]), + .Q(com_tlm_u_tlm_tx_ack_mgr_latest_ack_tsn[7]), + .S(plm_link_up_i) + ); + FDSE com_tlm_u_tlm_tx_ack_mgr_latest_ack_tsn_8_ ( + .CE(com_tlm_u_tlm_tx_ack_mgr_N_10925_i_i_i_3227), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_lnk_tupdate_seq[8]), + .Q(com_tlm_u_tlm_tx_ack_mgr_latest_ack_tsn[8]), + .S(plm_link_up_i) + ); + FDSE com_tlm_u_tlm_tx_ack_mgr_latest_ack_tsn_9_ ( + .CE(com_tlm_u_tlm_tx_ack_mgr_N_10925_i_i_i_3227), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_lnk_tupdate_seq[9]), + .Q(com_tlm_u_tlm_tx_ack_mgr_latest_ack_tsn[9]), + .S(plm_link_up_i) + ); + FDSE com_tlm_u_tlm_tx_ack_mgr_latest_ack_tsn_10_ ( + .CE(com_tlm_u_tlm_tx_ack_mgr_N_10925_i_i_i_3227), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_lnk_tupdate_seq[10]), + .Q(com_tlm_u_tlm_tx_ack_mgr_latest_ack_tsn[10]), + .S(plm_link_up_i) + ); + FDSE com_tlm_u_tlm_tx_ack_mgr_latest_ack_tsn_11_ ( + .CE(com_tlm_u_tlm_tx_ack_mgr_N_10925_i_i_i_3227), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_lnk_tupdate_seq[11]), + .Q(com_tlm_u_tlm_tx_ack_mgr_latest_ack_tsn[11]), + .S(plm_link_up_i) + ); + FDSE com_tlm_u_tlm_tx_ack_mgr_lnk_rupdate_seq_q_0_ ( + .CE(com_tlm_u_tlm_tx_ack_mgr_N_55889_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_lnk_tupdate_seq[0]), + .Q(com_tlm_u_tlm_tx_ack_mgr_lnk_rupdate_seq_q[0]), + .S(plm_link_up_i) + ); + FDSE com_tlm_u_tlm_tx_ack_mgr_lnk_rupdate_seq_q_1_ ( + .CE(com_tlm_u_tlm_tx_ack_mgr_N_55889_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_lnk_tupdate_seq[1]), + .Q(com_tlm_u_tlm_tx_ack_mgr_lnk_rupdate_seq_q[1]), + .S(plm_link_up_i) + ); + FDSE com_tlm_u_tlm_tx_ack_mgr_lnk_rupdate_seq_q_2_ ( + .CE(com_tlm_u_tlm_tx_ack_mgr_N_55889_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_lnk_tupdate_seq[2]), + .Q(com_tlm_u_tlm_tx_ack_mgr_lnk_rupdate_seq_q[2]), + .S(plm_link_up_i) + ); + FDSE com_tlm_u_tlm_tx_ack_mgr_lnk_rupdate_seq_q_3_ ( + .CE(com_tlm_u_tlm_tx_ack_mgr_N_55889_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_lnk_tupdate_seq[3]), + .Q(com_tlm_u_tlm_tx_ack_mgr_lnk_rupdate_seq_q[3]), + .S(plm_link_up_i) + ); + FDSE com_tlm_u_tlm_tx_ack_mgr_lnk_rupdate_seq_q_4_ ( + .CE(com_tlm_u_tlm_tx_ack_mgr_N_55889_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_lnk_tupdate_seq[4]), + .Q(com_tlm_u_tlm_tx_ack_mgr_lnk_rupdate_seq_q[4]), + .S(plm_link_up_i) + ); + FDSE com_tlm_u_tlm_tx_ack_mgr_lnk_rupdate_seq_q_5_ ( + .CE(com_tlm_u_tlm_tx_ack_mgr_N_55889_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_lnk_tupdate_seq[5]), + .Q(com_tlm_u_tlm_tx_ack_mgr_lnk_rupdate_seq_q[5]), + .S(plm_link_up_i) + ); + FDSE com_tlm_u_tlm_tx_ack_mgr_lnk_rupdate_seq_q_6_ ( + .CE(com_tlm_u_tlm_tx_ack_mgr_N_55889_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_lnk_tupdate_seq[6]), + .Q(com_tlm_u_tlm_tx_ack_mgr_lnk_rupdate_seq_q[6]), + .S(plm_link_up_i) + ); + FDSE com_tlm_u_tlm_tx_ack_mgr_lnk_rupdate_seq_q_7_ ( + .CE(com_tlm_u_tlm_tx_ack_mgr_N_55889_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_lnk_tupdate_seq[7]), + .Q(com_tlm_u_tlm_tx_ack_mgr_lnk_rupdate_seq_q[7]), + .S(plm_link_up_i) + ); + FDSE com_tlm_u_tlm_tx_ack_mgr_lnk_rupdate_seq_q_8_ ( + .CE(com_tlm_u_tlm_tx_ack_mgr_N_55889_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_lnk_tupdate_seq[8]), + .Q(com_tlm_u_tlm_tx_ack_mgr_lnk_rupdate_seq_q[8]), + .S(plm_link_up_i) + ); + FDSE com_tlm_u_tlm_tx_ack_mgr_lnk_rupdate_seq_q_9_ ( + .CE(com_tlm_u_tlm_tx_ack_mgr_N_55889_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_lnk_tupdate_seq[9]), + .Q(com_tlm_u_tlm_tx_ack_mgr_lnk_rupdate_seq_q[9]), + .S(plm_link_up_i) + ); + FDSE com_tlm_u_tlm_tx_ack_mgr_lnk_rupdate_seq_q_10_ ( + .CE(com_tlm_u_tlm_tx_ack_mgr_N_55889_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_lnk_tupdate_seq[10]), + .Q(com_tlm_u_tlm_tx_ack_mgr_lnk_rupdate_seq_q[10]), + .S(plm_link_up_i) + ); + FDSE com_tlm_u_tlm_tx_ack_mgr_lnk_rupdate_seq_q_11_ ( + .CE(com_tlm_u_tlm_tx_ack_mgr_N_55889_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_lnk_tupdate_seq[11]), + .Q(com_tlm_u_tlm_tx_ack_mgr_lnk_rupdate_seq_q[11]), + .S(plm_link_up_i) + ); + MUXCY_L com_tlm_u_tlm_tx_ack_mgr_unreg_frees_pend_un1_frees_pending_0_I_1 ( + .CI(com_tlm_u_tlm_tx_ack_mgr_VCC_3160), + .DI(com_tlm_u_tlm_tx_ack_mgr_GND_3228), + .LO(com_tlm_u_tlm_tx_ack_mgr_data_tmp_0[0]), + .S(com_tlm_u_tlm_tx_ack_mgr_N_43) + ); + MUXCY_L com_tlm_u_tlm_tx_ack_mgr_unreg_frees_pend_un1_frees_pending_0_I_10 ( + .CI(com_tlm_u_tlm_tx_ack_mgr_data_tmp_0[1]), + .DI(com_tlm_u_tlm_tx_ack_mgr_GND_3228), + .LO(com_tlm_u_tlm_tx_ack_mgr_data_tmp_0[2]), + .S(com_tlm_u_tlm_tx_ack_mgr_N_35) + ); + MUXCY_L com_tlm_u_tlm_tx_ack_mgr_unreg_frees_pend_un1_frees_pending_0_I_28 ( + .CI(com_tlm_u_tlm_tx_ack_mgr_data_tmp_0[2]), + .DI(com_tlm_u_tlm_tx_ack_mgr_GND_3228), + .LO(com_tlm_u_tlm_tx_ack_mgr_data_tmp_0[3]), + .S(com_tlm_u_tlm_tx_ack_mgr_N_19) + ); + MUXCY_L com_tlm_u_tlm_tx_ack_mgr_unreg_frees_pend_un1_frees_pending_0_I_37 ( + .CI(com_tlm_u_tlm_tx_ack_mgr_data_tmp_0[3]), + .DI(com_tlm_u_tlm_tx_ack_mgr_GND_3228), + .LO(com_tlm_u_tlm_tx_ack_mgr_data_tmp[4]), + .S(com_tlm_u_tlm_tx_ack_mgr_N_11) + ); + MUXCY_L com_tlm_u_tlm_tx_ack_mgr_unreg_frees_pend_un1_frees_pending_0_I_46 ( + .CI(com_tlm_u_tlm_tx_ack_mgr_data_tmp_0[0]), + .DI(com_tlm_u_tlm_tx_ack_mgr_GND_3228), + .LO(com_tlm_u_tlm_tx_ack_mgr_data_tmp_0[1]), + .S(com_tlm_u_tlm_tx_ack_mgr_N_3) + ); + MUXCY_L com_tlm_u_tlm_tx_ack_mgr_unreg_skips_pend_un1_skips_pending_0_I_1 ( + .CI(com_tlm_u_tlm_tx_ack_mgr_VCC_3160), + .DI(com_tlm_u_tlm_tx_ack_mgr_GND_3228), + .LO(com_tlm_u_tlm_tx_ack_mgr_data_tmp[0]), + .S(com_tlm_u_tlm_tx_ack_mgr_N_43_0) + ); + MUXCY_L com_tlm_u_tlm_tx_ack_mgr_unreg_skips_pend_un1_skips_pending_0_I_10 ( + .CI(com_tlm_u_tlm_tx_ack_mgr_data_tmp[1]), + .DI(com_tlm_u_tlm_tx_ack_mgr_GND_3228), + .LO(com_tlm_u_tlm_tx_ack_mgr_data_tmp[2]), + .S(com_tlm_u_tlm_tx_ack_mgr_N_35_0) + ); + MUXCY_L com_tlm_u_tlm_tx_ack_mgr_unreg_skips_pend_un1_skips_pending_0_I_28 ( + .CI(com_tlm_u_tlm_tx_ack_mgr_data_tmp[2]), + .DI(com_tlm_u_tlm_tx_ack_mgr_GND_3228), + .LO(com_tlm_u_tlm_tx_ack_mgr_data_tmp[3]), + .S(com_tlm_u_tlm_tx_ack_mgr_N_19_0) + ); + MUXCY_L com_tlm_u_tlm_tx_ack_mgr_unreg_skips_pend_un1_skips_pending_0_I_37 ( + .CI(com_tlm_u_tlm_tx_ack_mgr_data_tmp[3]), + .DI(com_tlm_u_tlm_tx_ack_mgr_GND_3228), + .LO(com_tlm_u_tlm_tx_ack_mgr_data_tmp_0[4]), + .S(com_tlm_u_tlm_tx_ack_mgr_N_11_0) + ); + MUXCY_L com_tlm_u_tlm_tx_ack_mgr_unreg_skips_pend_un1_skips_pending_0_I_46 ( + .CI(com_tlm_u_tlm_tx_ack_mgr_data_tmp[0]), + .DI(com_tlm_u_tlm_tx_ack_mgr_GND_3228), + .LO(com_tlm_u_tlm_tx_ack_mgr_data_tmp[1]), + .S(com_tlm_u_tlm_tx_ack_mgr_N_3_0) + ); + MUXCY_L com_tlm_u_tlm_tx_ack_mgr_un1_oldest_tsn_1_cry_0 ( + .CI(com_tlm_u_tlm_tx_ack_mgr_N_51909_i), + .DI(com_tlm_u_tlm_tx_ack_mgr_GND_3228), + .LO(com_tlm_u_tlm_tx_ack_mgr_un1_oldest_tsn_1_cry_0_3149), + .S(com_tlm_u_tlm_tx_ack_mgr_un1_oldest_tsn_1_axb_0_3207) + ); + XORCY com_tlm_u_tlm_tx_ack_mgr_un1_oldest_tsn_1_s_0 ( + .CI(com_tlm_u_tlm_tx_ack_mgr_N_51909_i), + .LI(com_tlm_u_tlm_tx_ack_mgr_un1_oldest_tsn_1_axb_0_3207), + .O(com_tlm_u_tlm_tx_ack_mgr_un1_oldest_tsn_1_s_0_3240) + ); + MUXCY_L com_tlm_u_tlm_tx_ack_mgr_un1_oldest_tsn_1_cry_1 ( + .CI(com_tlm_u_tlm_tx_ack_mgr_un1_oldest_tsn_1_cry_0_3149), + .DI(com_tlm_u_tlm_tx_ack_mgr_GND_3228), + .LO(com_tlm_u_tlm_tx_ack_mgr_un1_oldest_tsn_1_cry_1_3150), + .S(com_tlm_u_tlm_tx_ack_mgr_un1_oldest_tsn_1_axb_1_3206) + ); + XORCY com_tlm_u_tlm_tx_ack_mgr_un1_oldest_tsn_1_s_1 ( + .CI(com_tlm_u_tlm_tx_ack_mgr_un1_oldest_tsn_1_cry_0_3149), + .LI(com_tlm_u_tlm_tx_ack_mgr_un1_oldest_tsn_1_axb_1_3206), + .O(com_tlm_u_tlm_tx_ack_mgr_un1_oldest_tsn_1_s_1_3239) + ); + MUXCY_L com_tlm_u_tlm_tx_ack_mgr_un1_oldest_tsn_1_cry_2 ( + .CI(com_tlm_u_tlm_tx_ack_mgr_un1_oldest_tsn_1_cry_1_3150), + .DI(com_tlm_u_tlm_tx_ack_mgr_GND_3228), + .LO(com_tlm_u_tlm_tx_ack_mgr_un1_oldest_tsn_1_cry_2_3151), + .S(com_tlm_u_tlm_tx_ack_mgr_un1_oldest_tsn_1_axb_2_3205) + ); + XORCY com_tlm_u_tlm_tx_ack_mgr_un1_oldest_tsn_1_s_2 ( + .CI(com_tlm_u_tlm_tx_ack_mgr_un1_oldest_tsn_1_cry_1_3150), + .LI(com_tlm_u_tlm_tx_ack_mgr_un1_oldest_tsn_1_axb_2_3205), + .O(com_tlm_u_tlm_tx_ack_mgr_un1_oldest_tsn_1_s_2_3238) + ); + MUXCY_L com_tlm_u_tlm_tx_ack_mgr_un1_oldest_tsn_1_cry_3 ( + .CI(com_tlm_u_tlm_tx_ack_mgr_un1_oldest_tsn_1_cry_2_3151), + .DI(com_tlm_u_tlm_tx_ack_mgr_GND_3228), + .LO(com_tlm_u_tlm_tx_ack_mgr_un1_oldest_tsn_1_cry_3_3152), + .S(com_tlm_u_tlm_tx_ack_mgr_un1_oldest_tsn_1_axb_3_3204) + ); + XORCY com_tlm_u_tlm_tx_ack_mgr_un1_oldest_tsn_1_s_3 ( + .CI(com_tlm_u_tlm_tx_ack_mgr_un1_oldest_tsn_1_cry_2_3151), + .LI(com_tlm_u_tlm_tx_ack_mgr_un1_oldest_tsn_1_axb_3_3204), + .O(com_tlm_u_tlm_tx_ack_mgr_un1_oldest_tsn_1_s_3_3237) + ); + MUXCY_L com_tlm_u_tlm_tx_ack_mgr_un1_oldest_tsn_1_cry_4 ( + .CI(com_tlm_u_tlm_tx_ack_mgr_un1_oldest_tsn_1_cry_3_3152), + .DI(com_tlm_u_tlm_tx_ack_mgr_GND_3228), + .LO(com_tlm_u_tlm_tx_ack_mgr_un1_oldest_tsn_1_cry_4_3153), + .S(com_tlm_u_tlm_tx_ack_mgr_un1_oldest_tsn_1_axb_4_3203) + ); + XORCY com_tlm_u_tlm_tx_ack_mgr_un1_oldest_tsn_1_s_4 ( + .CI(com_tlm_u_tlm_tx_ack_mgr_un1_oldest_tsn_1_cry_3_3152), + .LI(com_tlm_u_tlm_tx_ack_mgr_un1_oldest_tsn_1_axb_4_3203), + .O(com_tlm_u_tlm_tx_ack_mgr_un1_oldest_tsn_1_s_4_3236) + ); + MUXCY_L com_tlm_u_tlm_tx_ack_mgr_un1_oldest_tsn_1_cry_5 ( + .CI(com_tlm_u_tlm_tx_ack_mgr_un1_oldest_tsn_1_cry_4_3153), + .DI(com_tlm_u_tlm_tx_ack_mgr_GND_3228), + .LO(com_tlm_u_tlm_tx_ack_mgr_un1_oldest_tsn_1_cry_5_3154), + .S(com_tlm_u_tlm_tx_ack_mgr_un1_oldest_tsn_1_axb_5_3202) + ); + XORCY com_tlm_u_tlm_tx_ack_mgr_un1_oldest_tsn_1_s_5 ( + .CI(com_tlm_u_tlm_tx_ack_mgr_un1_oldest_tsn_1_cry_4_3153), + .LI(com_tlm_u_tlm_tx_ack_mgr_un1_oldest_tsn_1_axb_5_3202), + .O(com_tlm_u_tlm_tx_ack_mgr_un1_oldest_tsn_1_s_5_3235) + ); + MUXCY_L com_tlm_u_tlm_tx_ack_mgr_un1_oldest_tsn_1_cry_6 ( + .CI(com_tlm_u_tlm_tx_ack_mgr_un1_oldest_tsn_1_cry_5_3154), + .DI(com_tlm_u_tlm_tx_ack_mgr_GND_3228), + .LO(com_tlm_u_tlm_tx_ack_mgr_un1_oldest_tsn_1_cry_6_3155), + .S(com_tlm_u_tlm_tx_ack_mgr_un1_oldest_tsn_1_axb_6_3201) + ); + XORCY com_tlm_u_tlm_tx_ack_mgr_un1_oldest_tsn_1_s_6 ( + .CI(com_tlm_u_tlm_tx_ack_mgr_un1_oldest_tsn_1_cry_5_3154), + .LI(com_tlm_u_tlm_tx_ack_mgr_un1_oldest_tsn_1_axb_6_3201), + .O(com_tlm_u_tlm_tx_ack_mgr_un1_oldest_tsn_1_s_6_3234) + ); + MUXCY_L com_tlm_u_tlm_tx_ack_mgr_un1_oldest_tsn_1_cry_7 ( + .CI(com_tlm_u_tlm_tx_ack_mgr_un1_oldest_tsn_1_cry_6_3155), + .DI(com_tlm_u_tlm_tx_ack_mgr_GND_3228), + .LO(com_tlm_u_tlm_tx_ack_mgr_un1_oldest_tsn_1_cry_7_3156), + .S(com_tlm_u_tlm_tx_ack_mgr_un1_oldest_tsn_1_axb_7_3200) + ); + XORCY com_tlm_u_tlm_tx_ack_mgr_un1_oldest_tsn_1_s_7 ( + .CI(com_tlm_u_tlm_tx_ack_mgr_un1_oldest_tsn_1_cry_6_3155), + .LI(com_tlm_u_tlm_tx_ack_mgr_un1_oldest_tsn_1_axb_7_3200), + .O(com_tlm_u_tlm_tx_ack_mgr_un1_oldest_tsn_1_s_7_3233) + ); + MUXCY_L com_tlm_u_tlm_tx_ack_mgr_un1_oldest_tsn_1_cry_8 ( + .CI(com_tlm_u_tlm_tx_ack_mgr_un1_oldest_tsn_1_cry_7_3156), + .DI(com_tlm_u_tlm_tx_ack_mgr_GND_3228), + .LO(com_tlm_u_tlm_tx_ack_mgr_un1_oldest_tsn_1_cry_8_3157), + .S(com_tlm_u_tlm_tx_ack_mgr_un1_oldest_tsn_1_axb_8_3199) + ); + XORCY com_tlm_u_tlm_tx_ack_mgr_un1_oldest_tsn_1_s_8 ( + .CI(com_tlm_u_tlm_tx_ack_mgr_un1_oldest_tsn_1_cry_7_3156), + .LI(com_tlm_u_tlm_tx_ack_mgr_un1_oldest_tsn_1_axb_8_3199), + .O(com_tlm_u_tlm_tx_ack_mgr_un1_oldest_tsn_1_s_8_3232) + ); + MUXCY_L com_tlm_u_tlm_tx_ack_mgr_un1_oldest_tsn_1_cry_9 ( + .CI(com_tlm_u_tlm_tx_ack_mgr_un1_oldest_tsn_1_cry_8_3157), + .DI(com_tlm_u_tlm_tx_ack_mgr_GND_3228), + .LO(com_tlm_u_tlm_tx_ack_mgr_un1_oldest_tsn_1_cry_9_3158), + .S(com_tlm_u_tlm_tx_ack_mgr_un1_oldest_tsn_1_axb_9_3198) + ); + XORCY com_tlm_u_tlm_tx_ack_mgr_un1_oldest_tsn_1_s_9 ( + .CI(com_tlm_u_tlm_tx_ack_mgr_un1_oldest_tsn_1_cry_8_3157), + .LI(com_tlm_u_tlm_tx_ack_mgr_un1_oldest_tsn_1_axb_9_3198), + .O(com_tlm_u_tlm_tx_ack_mgr_un1_oldest_tsn_1_s_9_3231) + ); + MUXCY_L com_tlm_u_tlm_tx_ack_mgr_un1_oldest_tsn_1_cry_10 ( + .CI(com_tlm_u_tlm_tx_ack_mgr_un1_oldest_tsn_1_cry_9_3158), + .DI(com_tlm_u_tlm_tx_ack_mgr_GND_3228), + .LO(com_tlm_u_tlm_tx_ack_mgr_un1_oldest_tsn_1_cry_10_3159), + .S(com_tlm_u_tlm_tx_ack_mgr_un1_oldest_tsn_1_axb_10_3197) + ); + XORCY com_tlm_u_tlm_tx_ack_mgr_un1_oldest_tsn_1_s_10 ( + .CI(com_tlm_u_tlm_tx_ack_mgr_un1_oldest_tsn_1_cry_9_3158), + .LI(com_tlm_u_tlm_tx_ack_mgr_un1_oldest_tsn_1_axb_10_3197), + .O(com_tlm_u_tlm_tx_ack_mgr_un1_oldest_tsn_1_s_10_3230) + ); + XORCY com_tlm_u_tlm_tx_ack_mgr_un1_oldest_tsn_1_s_11 ( + .CI(com_tlm_u_tlm_tx_ack_mgr_un1_oldest_tsn_1_cry_10_3159), + .LI(com_tlm_u_tlm_tx_ack_mgr_un1_oldest_tsn_1_axb_11_3196), + .O(com_tlm_u_tlm_tx_ack_mgr_un1_oldest_tsn_1_s_11_3229) + ); + MUXCY_L com_tlm_u_tlm_tx_ack_mgr_un4_retry_tsn_o_cry_0 ( + .CI(com_tlm_u_tlm_tx_ack_mgr_VCC_3160), + .DI(com_tlm_u_tlm_tx_ack_mgr_GND_3228), + .LO(com_tlm_u_tlm_tx_ack_mgr_un4_retry_tsn_o_cry_0_3162), + .S(com_tlm_u_tlm_tx_ack_mgr_un4_retry_tsn_o_axb_0_3243) + ); + MUXCY_L com_tlm_u_tlm_tx_ack_mgr_un4_retry_tsn_o_cry_1 ( + .CI(com_tlm_u_tlm_tx_ack_mgr_un4_retry_tsn_o_cry_0_3162), + .DI(com_tlm_u_tlm_tx_ack_mgr_GND_3228), + .LO(com_tlm_u_tlm_tx_ack_mgr_un4_retry_tsn_o_cry_1_3164), + .S(com_tlm_u_tlm_tx_ack_mgr_un4_retry_tsn_o_axb_1_3219) + ); + XORCY com_tlm_u_tlm_tx_ack_mgr_un4_retry_tsn_o_s_1 ( + .CI(com_tlm_u_tlm_tx_ack_mgr_un4_retry_tsn_o_cry_0_3162), + .LI(com_tlm_u_tlm_tx_ack_mgr_un4_retry_tsn_o_axb_1_3219), + .O(com_tlm_u_tlm_tx_ack_mgr_un4_retry_tsn_o_s_1_3161) + ); + MUXCY_L com_tlm_u_tlm_tx_ack_mgr_un4_retry_tsn_o_cry_2 ( + .CI(com_tlm_u_tlm_tx_ack_mgr_un4_retry_tsn_o_cry_1_3164), + .DI(com_tlm_u_tlm_tx_ack_mgr_GND_3228), + .LO(com_tlm_u_tlm_tx_ack_mgr_un4_retry_tsn_o_cry_2_3166), + .S(com_tlm_u_tlm_tx_ack_mgr_un4_retry_tsn_o_axb_2_3218) + ); + XORCY com_tlm_u_tlm_tx_ack_mgr_un4_retry_tsn_o_s_2 ( + .CI(com_tlm_u_tlm_tx_ack_mgr_un4_retry_tsn_o_cry_1_3164), + .LI(com_tlm_u_tlm_tx_ack_mgr_un4_retry_tsn_o_axb_2_3218), + .O(com_tlm_u_tlm_tx_ack_mgr_un4_retry_tsn_o_s_2_3163) + ); + MUXCY_L com_tlm_u_tlm_tx_ack_mgr_un4_retry_tsn_o_cry_3 ( + .CI(com_tlm_u_tlm_tx_ack_mgr_un4_retry_tsn_o_cry_2_3166), + .DI(com_tlm_u_tlm_tx_ack_mgr_GND_3228), + .LO(com_tlm_u_tlm_tx_ack_mgr_un4_retry_tsn_o_cry_3_3168), + .S(com_tlm_u_tlm_tx_ack_mgr_un4_retry_tsn_o_axb_3_3217) + ); + XORCY com_tlm_u_tlm_tx_ack_mgr_un4_retry_tsn_o_s_3 ( + .CI(com_tlm_u_tlm_tx_ack_mgr_un4_retry_tsn_o_cry_2_3166), + .LI(com_tlm_u_tlm_tx_ack_mgr_un4_retry_tsn_o_axb_3_3217), + .O(com_tlm_u_tlm_tx_ack_mgr_un4_retry_tsn_o_s_3_3165) + ); + MUXCY_L com_tlm_u_tlm_tx_ack_mgr_un4_retry_tsn_o_cry_4 ( + .CI(com_tlm_u_tlm_tx_ack_mgr_un4_retry_tsn_o_cry_3_3168), + .DI(com_tlm_u_tlm_tx_ack_mgr_GND_3228), + .LO(com_tlm_u_tlm_tx_ack_mgr_un4_retry_tsn_o_cry_4_3170), + .S(com_tlm_u_tlm_tx_ack_mgr_un4_retry_tsn_o_axb_4_3216) + ); + XORCY com_tlm_u_tlm_tx_ack_mgr_un4_retry_tsn_o_s_4 ( + .CI(com_tlm_u_tlm_tx_ack_mgr_un4_retry_tsn_o_cry_3_3168), + .LI(com_tlm_u_tlm_tx_ack_mgr_un4_retry_tsn_o_axb_4_3216), + .O(com_tlm_u_tlm_tx_ack_mgr_un4_retry_tsn_o_s_4_3167) + ); + MUXCY_L com_tlm_u_tlm_tx_ack_mgr_un4_retry_tsn_o_cry_5 ( + .CI(com_tlm_u_tlm_tx_ack_mgr_un4_retry_tsn_o_cry_4_3170), + .DI(com_tlm_u_tlm_tx_ack_mgr_GND_3228), + .LO(com_tlm_u_tlm_tx_ack_mgr_un4_retry_tsn_o_cry_5_3172), + .S(com_tlm_u_tlm_tx_ack_mgr_un4_retry_tsn_o_axb_5_3215) + ); + XORCY com_tlm_u_tlm_tx_ack_mgr_un4_retry_tsn_o_s_5 ( + .CI(com_tlm_u_tlm_tx_ack_mgr_un4_retry_tsn_o_cry_4_3170), + .LI(com_tlm_u_tlm_tx_ack_mgr_un4_retry_tsn_o_axb_5_3215), + .O(com_tlm_u_tlm_tx_ack_mgr_un4_retry_tsn_o_s_5_3169) + ); + MUXCY_L com_tlm_u_tlm_tx_ack_mgr_un4_retry_tsn_o_cry_6 ( + .CI(com_tlm_u_tlm_tx_ack_mgr_un4_retry_tsn_o_cry_5_3172), + .DI(com_tlm_u_tlm_tx_ack_mgr_GND_3228), + .LO(com_tlm_u_tlm_tx_ack_mgr_un4_retry_tsn_o_cry_6_3174), + .S(com_tlm_u_tlm_tx_ack_mgr_un4_retry_tsn_o_axb_6_3214) + ); + XORCY com_tlm_u_tlm_tx_ack_mgr_un4_retry_tsn_o_s_6 ( + .CI(com_tlm_u_tlm_tx_ack_mgr_un4_retry_tsn_o_cry_5_3172), + .LI(com_tlm_u_tlm_tx_ack_mgr_un4_retry_tsn_o_axb_6_3214), + .O(com_tlm_u_tlm_tx_ack_mgr_un4_retry_tsn_o_s_6_3171) + ); + MUXCY_L com_tlm_u_tlm_tx_ack_mgr_un4_retry_tsn_o_cry_7 ( + .CI(com_tlm_u_tlm_tx_ack_mgr_un4_retry_tsn_o_cry_6_3174), + .DI(com_tlm_u_tlm_tx_ack_mgr_GND_3228), + .LO(com_tlm_u_tlm_tx_ack_mgr_un4_retry_tsn_o_cry_7_3176), + .S(com_tlm_u_tlm_tx_ack_mgr_un4_retry_tsn_o_axb_7_3213) + ); + XORCY com_tlm_u_tlm_tx_ack_mgr_un4_retry_tsn_o_s_7 ( + .CI(com_tlm_u_tlm_tx_ack_mgr_un4_retry_tsn_o_cry_6_3174), + .LI(com_tlm_u_tlm_tx_ack_mgr_un4_retry_tsn_o_axb_7_3213), + .O(com_tlm_u_tlm_tx_ack_mgr_un4_retry_tsn_o_s_7_3173) + ); + MUXCY_L com_tlm_u_tlm_tx_ack_mgr_un4_retry_tsn_o_cry_8 ( + .CI(com_tlm_u_tlm_tx_ack_mgr_un4_retry_tsn_o_cry_7_3176), + .DI(com_tlm_u_tlm_tx_ack_mgr_GND_3228), + .LO(com_tlm_u_tlm_tx_ack_mgr_un4_retry_tsn_o_cry_8_3178), + .S(com_tlm_u_tlm_tx_ack_mgr_un4_retry_tsn_o_axb_8_3212) + ); + XORCY com_tlm_u_tlm_tx_ack_mgr_un4_retry_tsn_o_s_8 ( + .CI(com_tlm_u_tlm_tx_ack_mgr_un4_retry_tsn_o_cry_7_3176), + .LI(com_tlm_u_tlm_tx_ack_mgr_un4_retry_tsn_o_axb_8_3212), + .O(com_tlm_u_tlm_tx_ack_mgr_un4_retry_tsn_o_s_8_3175) + ); + MUXCY_L com_tlm_u_tlm_tx_ack_mgr_un4_retry_tsn_o_cry_9 ( + .CI(com_tlm_u_tlm_tx_ack_mgr_un4_retry_tsn_o_cry_8_3178), + .DI(com_tlm_u_tlm_tx_ack_mgr_GND_3228), + .LO(com_tlm_u_tlm_tx_ack_mgr_un4_retry_tsn_o_cry_9_3180), + .S(com_tlm_u_tlm_tx_ack_mgr_un4_retry_tsn_o_axb_9_3211) + ); + XORCY com_tlm_u_tlm_tx_ack_mgr_un4_retry_tsn_o_s_9 ( + .CI(com_tlm_u_tlm_tx_ack_mgr_un4_retry_tsn_o_cry_8_3178), + .LI(com_tlm_u_tlm_tx_ack_mgr_un4_retry_tsn_o_axb_9_3211), + .O(com_tlm_u_tlm_tx_ack_mgr_un4_retry_tsn_o_s_9_3177) + ); + MUXCY_L com_tlm_u_tlm_tx_ack_mgr_un4_retry_tsn_o_cry_10 ( + .CI(com_tlm_u_tlm_tx_ack_mgr_un4_retry_tsn_o_cry_9_3180), + .DI(com_tlm_u_tlm_tx_ack_mgr_GND_3228), + .LO(com_tlm_u_tlm_tx_ack_mgr_un4_retry_tsn_o_cry_10_3182), + .S(com_tlm_u_tlm_tx_ack_mgr_un4_retry_tsn_o_axb_10_3210) + ); + XORCY com_tlm_u_tlm_tx_ack_mgr_un4_retry_tsn_o_s_10 ( + .CI(com_tlm_u_tlm_tx_ack_mgr_un4_retry_tsn_o_cry_9_3180), + .LI(com_tlm_u_tlm_tx_ack_mgr_un4_retry_tsn_o_axb_10_3210), + .O(com_tlm_u_tlm_tx_ack_mgr_un4_retry_tsn_o_s_10_3179) + ); + XORCY com_tlm_u_tlm_tx_ack_mgr_un4_retry_tsn_o_s_11 ( + .CI(com_tlm_u_tlm_tx_ack_mgr_un4_retry_tsn_o_cry_10_3182), + .LI(com_tlm_u_tlm_tx_ack_mgr_un4_retry_tsn_o_axb_11_3209), + .O(com_tlm_u_tlm_tx_ack_mgr_un4_retry_tsn_o_s_11_3181) + ); + FDSE com_tlm_u_tlm_tx_ack_mgr_newest_freed_tsn_0_ ( + .CE(com_tlm_u_tlm_tx_ack_mgr_N_56106_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_ack_mgr_newest_freed_tsn_s[0]), + .Q(com_tlm_u_tlm_tx_ack_mgr_newest_freed_tsn[0]), + .S(plm_link_up_i) + ); + MUXCY_L com_tlm_u_tlm_tx_ack_mgr_newest_freed_tsn_cry_1_ ( + .CI(com_tlm_u_tlm_tx_ack_mgr_newest_freed_tsn[0]), + .DI(com_tlm_u_tlm_tx_ack_mgr_GND_3228), + .LO(com_tlm_u_tlm_tx_ack_mgr_newest_freed_tsn_cry[1]), + .S(com_tlm_u_tlm_tx_ack_mgr_newest_freed_tsn_qxu[1]) + ); + XORCY com_tlm_u_tlm_tx_ack_mgr_newest_freed_tsn_s_1_ ( + .CI(com_tlm_u_tlm_tx_ack_mgr_newest_freed_tsn[0]), + .LI(com_tlm_u_tlm_tx_ack_mgr_newest_freed_tsn_qxu[1]), + .O(com_tlm_u_tlm_tx_ack_mgr_newest_freed_tsn_s[1]) + ); + FDSE com_tlm_u_tlm_tx_ack_mgr_newest_freed_tsn_1_ ( + .CE(com_tlm_u_tlm_tx_ack_mgr_N_56106_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_ack_mgr_newest_freed_tsn_s[1]), + .Q(com_tlm_u_tlm_tx_ack_mgr_newest_freed_tsn[1]), + .S(plm_link_up_i) + ); + MUXCY_L com_tlm_u_tlm_tx_ack_mgr_newest_freed_tsn_cry_2_ ( + .CI(com_tlm_u_tlm_tx_ack_mgr_newest_freed_tsn_cry[1]), + .DI(com_tlm_u_tlm_tx_ack_mgr_GND_3228), + .LO(com_tlm_u_tlm_tx_ack_mgr_newest_freed_tsn_cry[2]), + .S(com_tlm_u_tlm_tx_ack_mgr_newest_freed_tsn_qxu[2]) + ); + XORCY com_tlm_u_tlm_tx_ack_mgr_newest_freed_tsn_s_2_ ( + .CI(com_tlm_u_tlm_tx_ack_mgr_newest_freed_tsn_cry[1]), + .LI(com_tlm_u_tlm_tx_ack_mgr_newest_freed_tsn_qxu[2]), + .O(com_tlm_u_tlm_tx_ack_mgr_newest_freed_tsn_s[2]) + ); + FDSE com_tlm_u_tlm_tx_ack_mgr_newest_freed_tsn_2_ ( + .CE(com_tlm_u_tlm_tx_ack_mgr_N_56106_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_ack_mgr_newest_freed_tsn_s[2]), + .Q(com_tlm_u_tlm_tx_ack_mgr_newest_freed_tsn[2]), + .S(plm_link_up_i) + ); + MUXCY_L com_tlm_u_tlm_tx_ack_mgr_newest_freed_tsn_cry_3_ ( + .CI(com_tlm_u_tlm_tx_ack_mgr_newest_freed_tsn_cry[2]), + .DI(com_tlm_u_tlm_tx_ack_mgr_GND_3228), + .LO(com_tlm_u_tlm_tx_ack_mgr_newest_freed_tsn_cry[3]), + .S(com_tlm_u_tlm_tx_ack_mgr_newest_freed_tsn_qxu[3]) + ); + XORCY com_tlm_u_tlm_tx_ack_mgr_newest_freed_tsn_s_3_ ( + .CI(com_tlm_u_tlm_tx_ack_mgr_newest_freed_tsn_cry[2]), + .LI(com_tlm_u_tlm_tx_ack_mgr_newest_freed_tsn_qxu[3]), + .O(com_tlm_u_tlm_tx_ack_mgr_newest_freed_tsn_s[3]) + ); + FDSE com_tlm_u_tlm_tx_ack_mgr_newest_freed_tsn_3_ ( + .CE(com_tlm_u_tlm_tx_ack_mgr_N_56106_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_ack_mgr_newest_freed_tsn_s[3]), + .Q(com_tlm_u_tlm_tx_ack_mgr_newest_freed_tsn[3]), + .S(plm_link_up_i) + ); + MUXCY_L com_tlm_u_tlm_tx_ack_mgr_newest_freed_tsn_cry_4_ ( + .CI(com_tlm_u_tlm_tx_ack_mgr_newest_freed_tsn_cry[3]), + .DI(com_tlm_u_tlm_tx_ack_mgr_GND_3228), + .LO(com_tlm_u_tlm_tx_ack_mgr_newest_freed_tsn_cry[4]), + .S(com_tlm_u_tlm_tx_ack_mgr_newest_freed_tsn_qxu[4]) + ); + XORCY com_tlm_u_tlm_tx_ack_mgr_newest_freed_tsn_s_4_ ( + .CI(com_tlm_u_tlm_tx_ack_mgr_newest_freed_tsn_cry[3]), + .LI(com_tlm_u_tlm_tx_ack_mgr_newest_freed_tsn_qxu[4]), + .O(com_tlm_u_tlm_tx_ack_mgr_newest_freed_tsn_s[4]) + ); + FDSE com_tlm_u_tlm_tx_ack_mgr_newest_freed_tsn_4_ ( + .CE(com_tlm_u_tlm_tx_ack_mgr_N_56106_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_ack_mgr_newest_freed_tsn_s[4]), + .Q(com_tlm_u_tlm_tx_ack_mgr_newest_freed_tsn[4]), + .S(plm_link_up_i) + ); + MUXCY_L com_tlm_u_tlm_tx_ack_mgr_newest_freed_tsn_cry_5_ ( + .CI(com_tlm_u_tlm_tx_ack_mgr_newest_freed_tsn_cry[4]), + .DI(com_tlm_u_tlm_tx_ack_mgr_GND_3228), + .LO(com_tlm_u_tlm_tx_ack_mgr_newest_freed_tsn_cry[5]), + .S(com_tlm_u_tlm_tx_ack_mgr_newest_freed_tsn_qxu[5]) + ); + XORCY com_tlm_u_tlm_tx_ack_mgr_newest_freed_tsn_s_5_ ( + .CI(com_tlm_u_tlm_tx_ack_mgr_newest_freed_tsn_cry[4]), + .LI(com_tlm_u_tlm_tx_ack_mgr_newest_freed_tsn_qxu[5]), + .O(com_tlm_u_tlm_tx_ack_mgr_newest_freed_tsn_s[5]) + ); + FDSE com_tlm_u_tlm_tx_ack_mgr_newest_freed_tsn_5_ ( + .CE(com_tlm_u_tlm_tx_ack_mgr_N_56106_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_ack_mgr_newest_freed_tsn_s[5]), + .Q(com_tlm_u_tlm_tx_ack_mgr_newest_freed_tsn[5]), + .S(plm_link_up_i) + ); + MUXCY_L com_tlm_u_tlm_tx_ack_mgr_newest_freed_tsn_cry_6_ ( + .CI(com_tlm_u_tlm_tx_ack_mgr_newest_freed_tsn_cry[5]), + .DI(com_tlm_u_tlm_tx_ack_mgr_GND_3228), + .LO(com_tlm_u_tlm_tx_ack_mgr_newest_freed_tsn_cry[6]), + .S(com_tlm_u_tlm_tx_ack_mgr_newest_freed_tsn_qxu[6]) + ); + XORCY com_tlm_u_tlm_tx_ack_mgr_newest_freed_tsn_s_6_ ( + .CI(com_tlm_u_tlm_tx_ack_mgr_newest_freed_tsn_cry[5]), + .LI(com_tlm_u_tlm_tx_ack_mgr_newest_freed_tsn_qxu[6]), + .O(com_tlm_u_tlm_tx_ack_mgr_newest_freed_tsn_s[6]) + ); + FDSE com_tlm_u_tlm_tx_ack_mgr_newest_freed_tsn_6_ ( + .CE(com_tlm_u_tlm_tx_ack_mgr_N_56106_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_ack_mgr_newest_freed_tsn_s[6]), + .Q(com_tlm_u_tlm_tx_ack_mgr_newest_freed_tsn[6]), + .S(plm_link_up_i) + ); + MUXCY_L com_tlm_u_tlm_tx_ack_mgr_newest_freed_tsn_cry_7_ ( + .CI(com_tlm_u_tlm_tx_ack_mgr_newest_freed_tsn_cry[6]), + .DI(com_tlm_u_tlm_tx_ack_mgr_GND_3228), + .LO(com_tlm_u_tlm_tx_ack_mgr_newest_freed_tsn_cry[7]), + .S(com_tlm_u_tlm_tx_ack_mgr_newest_freed_tsn_qxu[7]) + ); + XORCY com_tlm_u_tlm_tx_ack_mgr_newest_freed_tsn_s_7_ ( + .CI(com_tlm_u_tlm_tx_ack_mgr_newest_freed_tsn_cry[6]), + .LI(com_tlm_u_tlm_tx_ack_mgr_newest_freed_tsn_qxu[7]), + .O(com_tlm_u_tlm_tx_ack_mgr_newest_freed_tsn_s[7]) + ); + FDSE com_tlm_u_tlm_tx_ack_mgr_newest_freed_tsn_7_ ( + .CE(com_tlm_u_tlm_tx_ack_mgr_N_56106_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_ack_mgr_newest_freed_tsn_s[7]), + .Q(com_tlm_u_tlm_tx_ack_mgr_newest_freed_tsn[7]), + .S(plm_link_up_i) + ); + MUXCY_L com_tlm_u_tlm_tx_ack_mgr_newest_freed_tsn_cry_8_ ( + .CI(com_tlm_u_tlm_tx_ack_mgr_newest_freed_tsn_cry[7]), + .DI(com_tlm_u_tlm_tx_ack_mgr_GND_3228), + .LO(com_tlm_u_tlm_tx_ack_mgr_newest_freed_tsn_cry[8]), + .S(com_tlm_u_tlm_tx_ack_mgr_newest_freed_tsn_qxu[8]) + ); + XORCY com_tlm_u_tlm_tx_ack_mgr_newest_freed_tsn_s_8_ ( + .CI(com_tlm_u_tlm_tx_ack_mgr_newest_freed_tsn_cry[7]), + .LI(com_tlm_u_tlm_tx_ack_mgr_newest_freed_tsn_qxu[8]), + .O(com_tlm_u_tlm_tx_ack_mgr_newest_freed_tsn_s[8]) + ); + FDSE com_tlm_u_tlm_tx_ack_mgr_newest_freed_tsn_8_ ( + .CE(com_tlm_u_tlm_tx_ack_mgr_N_56106_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_ack_mgr_newest_freed_tsn_s[8]), + .Q(com_tlm_u_tlm_tx_ack_mgr_newest_freed_tsn[8]), + .S(plm_link_up_i) + ); + MUXCY_L com_tlm_u_tlm_tx_ack_mgr_newest_freed_tsn_cry_9_ ( + .CI(com_tlm_u_tlm_tx_ack_mgr_newest_freed_tsn_cry[8]), + .DI(com_tlm_u_tlm_tx_ack_mgr_GND_3228), + .LO(com_tlm_u_tlm_tx_ack_mgr_newest_freed_tsn_cry[9]), + .S(com_tlm_u_tlm_tx_ack_mgr_newest_freed_tsn_qxu[9]) + ); + XORCY com_tlm_u_tlm_tx_ack_mgr_newest_freed_tsn_s_9_ ( + .CI(com_tlm_u_tlm_tx_ack_mgr_newest_freed_tsn_cry[8]), + .LI(com_tlm_u_tlm_tx_ack_mgr_newest_freed_tsn_qxu[9]), + .O(com_tlm_u_tlm_tx_ack_mgr_newest_freed_tsn_s[9]) + ); + FDSE com_tlm_u_tlm_tx_ack_mgr_newest_freed_tsn_9_ ( + .CE(com_tlm_u_tlm_tx_ack_mgr_N_56106_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_ack_mgr_newest_freed_tsn_s[9]), + .Q(com_tlm_u_tlm_tx_ack_mgr_newest_freed_tsn[9]), + .S(plm_link_up_i) + ); + MUXCY_L com_tlm_u_tlm_tx_ack_mgr_newest_freed_tsn_cry_10_ ( + .CI(com_tlm_u_tlm_tx_ack_mgr_newest_freed_tsn_cry[9]), + .DI(com_tlm_u_tlm_tx_ack_mgr_GND_3228), + .LO(com_tlm_u_tlm_tx_ack_mgr_newest_freed_tsn_cry[10]), + .S(com_tlm_u_tlm_tx_ack_mgr_newest_freed_tsn_qxu[10]) + ); + XORCY com_tlm_u_tlm_tx_ack_mgr_newest_freed_tsn_s_10_ ( + .CI(com_tlm_u_tlm_tx_ack_mgr_newest_freed_tsn_cry[9]), + .LI(com_tlm_u_tlm_tx_ack_mgr_newest_freed_tsn_qxu[10]), + .O(com_tlm_u_tlm_tx_ack_mgr_newest_freed_tsn_s[10]) + ); + FDSE com_tlm_u_tlm_tx_ack_mgr_newest_freed_tsn_10_ ( + .CE(com_tlm_u_tlm_tx_ack_mgr_N_56106_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_ack_mgr_newest_freed_tsn_s[10]), + .Q(com_tlm_u_tlm_tx_ack_mgr_newest_freed_tsn[10]), + .S(plm_link_up_i) + ); + XORCY com_tlm_u_tlm_tx_ack_mgr_newest_freed_tsn_s_11_ ( + .CI(com_tlm_u_tlm_tx_ack_mgr_newest_freed_tsn_cry[10]), + .LI(com_tlm_u_tlm_tx_ack_mgr_newest_freed_tsn_qxu[11]), + .O(com_tlm_u_tlm_tx_ack_mgr_newest_freed_tsn_s[11]) + ); + FDSE com_tlm_u_tlm_tx_ack_mgr_newest_freed_tsn_11_ ( + .CE(com_tlm_u_tlm_tx_ack_mgr_N_56106_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_ack_mgr_newest_freed_tsn_s[11]), + .Q(com_tlm_u_tlm_tx_ack_mgr_newest_freed_tsn[11]), + .S(plm_link_up_i) + ); + FDS com_tlm_u_tlm_tx_ack_mgr_mgr_state_0_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_ack_mgr_N_86010_i_3195), + .Q(com_tlm_u_tlm_tx_ack_mgr_mgr_state_0__3185), + .S(plm_link_up_i) + ); + FDR com_tlm_u_tlm_tx_ack_mgr_mgr_state_12_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_ack_mgr_mgr_statec_6_i), + .Q(com_tlm_u_tlm_tx_ack_mgr_mgr_state_12__3184), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_tx_ack_mgr_mgr_state_11_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_ack_mgr_mgr_statec_5_i), + .Q(com_tlm_u_tlm_tx_ack_mgr_mgr_state_11__3192), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_tx_ack_mgr_mgr_state_10_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_ack_mgr_mgr_statec_4_i), + .Q(com_tlm_u_tlm_tx_ack_mgr_mgr_state_10__3194), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_tx_ack_mgr_mgr_state_9_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_ack_mgr_mgr_statec_3_i), + .Q(com_tlm_u_tlm_tx_ack_mgr_mgr_state_9__3190), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_tx_ack_mgr_mgr_state_7_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_ack_mgr_mgr_statec_2_i), + .Q(com_tlm_u_tlm_tx_ack_mgr_mgr_state_7__3187), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_tx_ack_mgr_mgr_state_4_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_ack_mgr_mgr_statec_0_i), + .Q(com_tlm_u_tlm_tx_ack_mgr_mgr_state_4__3193), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_tx_ack_mgr_mgr_state_2_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_ack_mgr_mgr_statec_i), + .Q(com_tlm_u_tlm_tx_ack_mgr_mgr_state_2__3226), + .R(plm_link_up_i) + ); + defparam com_tlm_u_tlm_tx_ack_mgr_mgr_state_4_i_o2_0_o3_7_.INIT = 4'h2; + LUT2 com_tlm_u_tlm_tx_ack_mgr_mgr_state_4_i_o2_0_o3_7_ ( + .I0(com_reg_tx_update_retry_int), + .I1(com_reg_tx_update_retry_q), + .O(com_tlm_u_tlm_tx_ack_mgr_N_55889_i) + ); + defparam com_tlm_u_tlm_tx_ack_mgr_un1_lnk_rupdate_ack_i_0_a2_0_a2.INIT = 4'h2; + LUT2 com_tlm_u_tlm_tx_ack_mgr_un1_lnk_rupdate_ack_i_0_a2_0_a2 ( + .I0(com_reg_tx_update_ack), + .I1(com_tlm_u_tlm_tx_am_retry_lock), + .O(com_tlm_u_tlm_tx_ack_mgr_un1_lnk_rupdate_ack_i_0_a2_0_a2_3183) + ); + defparam com_tlm_u_tlm_tx_ack_mgr_un1_lnk_rupdate_ack_i_1_i_0_0_o2_0.INIT = 4'h4; + LUT2 com_tlm_u_tlm_tx_ack_mgr_un1_lnk_rupdate_ack_i_1_i_0_0_o2_0 ( + .I0(com_tlm_u_tlm_tx_am_retry_dst_rdy), + .I1(com_tlm_u_tlm_tx_am_retry_src_rdy), + .O(com_tlm_u_tlm_tx_ack_mgr_N_56340_i) + ); + defparam com_tlm_u_tlm_tx_ack_mgr_mgr_state_4_iv_i_o3_0_0_.INIT = 4'h1; + LUT2 com_tlm_u_tlm_tx_ack_mgr_mgr_state_4_iv_i_o3_0_0_ ( + .I0(com_tlm_u_tlm_tx_ack_mgr_mgr_state_0__3185), + .I1(com_tlm_u_tlm_tx_ack_mgr_mgr_state_12__3184), + .O(com_tlm_u_tlm_tx_ack_mgr_N_56502_i) + ); + defparam com_tlm_u_tlm_tx_ack_mgr_mgr_state_4_i_0_o3_7_.INIT = 4'h8; + LUT2 com_tlm_u_tlm_tx_ack_mgr_mgr_state_4_i_0_o3_7_ ( + .I0(com_tlm_u_tlm_tx_ack_mgr_nak_req_3225), + .I1(com_tlm_u_tlm_tx_un1_frees_pending), + .O(com_tlm_u_tlm_tx_ack_mgr_N_56351_i) + ); + defparam com_tlm_u_tlm_tx_ack_mgr_mgr_state_4_i_o3_10_.INIT = 4'h1; + LUT2 com_tlm_u_tlm_tx_ack_mgr_mgr_state_4_i_o3_10_ ( + .I0(com_tlm_u_tlm_tx_ack_mgr_mgr_state_8__3242), + .I1(com_tlm_u_tlm_tx_ack_mgr_mgr_state_10__3194), + .O(com_tlm_u_tlm_tx_ack_mgr_N_56325_i) + ); + defparam com_tlm_u_tlm_tx_ack_mgr_mgr_state_4_0_o3_8_.INIT = 4'h4; + LUT2 com_tlm_u_tlm_tx_ack_mgr_mgr_state_4_0_o3_8_ ( + .I0(com_tlm_u_tlm_tx_ack_mgr_fifo_nxt_vld), + .I1(com_tlm_u_tlm_tx_am_retry_dst_rdy), + .O(com_tlm_u_tlm_tx_ack_mgr_N_56066_i) + ); + defparam com_tlm_u_tlm_tx_ack_mgr_mgr_state_4_iv_i_o3_0_.INIT = 4'h1; + LUT2 com_tlm_u_tlm_tx_ack_mgr_mgr_state_4_iv_i_o3_0_ ( + .I0(com_tlm_u_tlm_tx_ack_mgr_mgr_state_2__3226), + .I1(com_tlm_u_tlm_tx_ack_mgr_mgr_state_4__3193), + .O(com_tlm_u_tlm_tx_N_55899_i) + ); + defparam com_tlm_u_tlm_tx_ack_mgr_retry_src_rdy_o_3_i_a2_3_1.INIT = 8'h80; + LUT3 com_tlm_u_tlm_tx_ack_mgr_retry_src_rdy_o_3_i_a2_3_1 ( + .I0(com_tlm_u_tlm_tx_ack_mgr_fifo_vld), + .I1(com_tlm_u_tlm_tx_ack_mgr_mgr_state_7__3187), + .I2(com_tlm_u_tlm_tx_ack_mgr_un1_skips_pending), + .O(com_tlm_u_tlm_tx_ack_mgr_N_58367_1) + ); + defparam com_tlm_u_tlm_tx_ack_mgr_un1_nxt_mgr_state_i_o3.INIT = 8'h40; + LUT3 com_tlm_u_tlm_tx_ack_mgr_un1_nxt_mgr_state_i_o3 ( + .I0(com_tlm_u_tlm_tx_ack_mgr_fifo_vld), + .I1(com_tlm_u_tlm_tx_ack_mgr_mgr_state_7__3187), + .I2(com_tlm_u_tlm_tx_ack_mgr_un1_skips_pending), + .O(com_tlm_u_tlm_tx_ack_mgr_N_56143_i) + ); + defparam com_tlm_u_tlm_tx_ack_mgr_un1_nxt_mgr_state_i_o3_0.INIT = 8'h08; + LUT3 com_tlm_u_tlm_tx_ack_mgr_un1_nxt_mgr_state_i_o3_0 ( + .I0(com_tlm_u_tlm_tx_ack_mgr_N_56066_i), + .I1(com_tlm_u_tlm_tx_ack_mgr_mgr_state_8__3242), + .I2(com_tlm_u_tlm_tx_ds_buf_src_rdy), + .O(com_tlm_u_tlm_tx_ack_mgr_N_57048_i) + ); + defparam com_tlm_u_tlm_tx_ack_mgr_N_87231_i.INIT = 4'hE; + LUT2 com_tlm_u_tlm_tx_ack_mgr_N_87231_i ( + .I0(com_tlm_u_tlm_tx_ack_mgr_N_55979_i), + .I1(com_tlm_u_tlm_tx_ack_mgr_jump_retry_tsn_3244), + .O(com_tlm_u_tlm_tx_ack_mgr_N_87231_i_3186) + ); + defparam com_tlm_u_tlm_tx_ack_mgr_mgr_state_4_i_0_a2_1_0_4_.INIT = 4'h8; + LUT2 com_tlm_u_tlm_tx_ack_mgr_mgr_state_4_i_0_a2_1_0_4_ ( + .I0(com_tlm_u_tlm_tx_ack_mgr_N_10925_i_i), + .I1(com_tlm_u_tlm_tx_un1_frees_pending), + .O(com_tlm_u_tlm_tx_ack_mgr_N_58380_1) + ); + defparam com_tlm_u_tlm_tx_ack_mgr_un1_nxt_mgr_state_i_o2.INIT = 4'h8; + LUT2 com_tlm_u_tlm_tx_ack_mgr_un1_nxt_mgr_state_i_o2 ( + .I0(com_tlm_u_tlm_tx_ack_mgr_N_10925_i_i), + .I1(plm_link_up_1), + .O(com_tlm_u_tlm_tx_ack_mgr_N_56235_i) + ); + defparam com_tlm_u_tlm_tx_ack_mgr_mgr_state_4_iv_i_a2_0_.INIT = 4'h2; + LUT2 com_tlm_u_tlm_tx_ack_mgr_mgr_state_4_iv_i_a2_0_ ( + .I0(com_tlm_u_tlm_tx_ack_mgr_N_10925_i_i), + .I1(com_tlm_u_tlm_tx_ack_mgr_N_56502_i), + .O(com_tlm_u_tlm_tx_ack_mgr_N_58250) + ); + defparam com_tlm_u_tlm_tx_ack_mgr_mgr_state_4_i_a2_11_.INIT = 16'h0203; + LUT4_L com_tlm_u_tlm_tx_ack_mgr_mgr_state_4_i_a2_11_ ( + .I0(com_tlm_u_tlm_tx_ack_mgr_N_56325_i), + .I1(com_tlm_u_tlm_tx_ack_mgr_mgr_state_7__3187), + .I2(com_tlm_u_tlm_tx_ack_mgr_mgr_state_9__3190), + .I3(com_tlm_u_tlm_tx_am_retry_dst_rdy), + .LO(com_tlm_u_tlm_tx_ack_mgr_N_57355) + ); + defparam com_tlm_u_tlm_tx_ack_mgr_N_87602_i.INIT = 4'h7; + LUT2 com_tlm_u_tlm_tx_ack_mgr_N_87602_i ( + .I0(com_tlm_u_tlm_tx_ack_mgr_N_10925_i_i), + .I1(com_tlm_u_tlm_tx_ack_mgr_N_56340_i), + .O(com_tlm_u_tlm_tx_ack_mgr_N_87602_i_3188) + ); + defparam com_tlm_u_tlm_tx_ack_mgr_un1_fifo_ren_iv_i_a2_0_.INIT = 16'h0002; + LUT4_L com_tlm_u_tlm_tx_ack_mgr_un1_fifo_ren_iv_i_a2_0_ ( + .I0(com_tlm_u_tlm_tx_ack_mgr_N_55893_i), + .I1(com_tlm_u_tlm_tx_ack_mgr_N_55921_i), + .I2(com_tlm_u_tlm_tx_ack_mgr_N_55979_i), + .I3(com_tlm_u_tlm_tx_ack_mgr_N_56106_i), + .LO(com_tlm_u_tlm_tx_ack_mgr_N_58283) + ); + defparam com_tlm_u_tlm_tx_ack_mgr_retry_src_rdy_o_3_i_0.INIT = 16'h5F4C; + LUT4_L com_tlm_u_tlm_tx_ack_mgr_retry_src_rdy_o_3_i_0 ( + .I0(com_tlm_u_tlm_tx_ack_mgr_N_10925_i_i), + .I1(com_tlm_u_tlm_tx_ack_mgr_N_56325_i), + .I2(com_tlm_u_tlm_tx_ack_mgr_mgr_state_9__3190), + .I3(com_tlm_u_tlm_tx_am_retry_dst_rdy), + .LO(com_tlm_u_tlm_tx_ack_mgr_retry_src_rdy_o_3_i_0_3191) + ); + defparam com_tlm_u_tlm_tx_ack_mgr_N_87236_i.INIT = 8'hA8; + LUT3 com_tlm_u_tlm_tx_ack_mgr_N_87236_i ( + .I0(com_tlm_u_tlm_tx_ack_mgr_N_10925_i_i), + .I1(com_tlm_u_tlm_tx_ack_mgr_N_56143_i), + .I2(com_tlm_u_tlm_tx_ack_mgr_N_57048_i), + .O(com_tlm_u_tlm_tx_ack_mgr_N_87236_i_3189) + ); + defparam com_tlm_u_tlm_tx_ack_mgr_un1_fifo_ren_iv_i_0_.INIT = 4'h4; + LUT2 com_tlm_u_tlm_tx_ack_mgr_un1_fifo_ren_iv_i_0_ ( + .I0(com_tlm_u_tlm_tx_ack_mgr_N_58283), + .I1(plm_link_up_1), + .O(com_tlm_u_tlm_tx_ack_mgr_N_51909_i) + ); + defparam com_tlm_u_tlm_tx_ack_mgr_mgr_state_4_0_0_8_.INIT = 16'h33BF; + LUT4 com_tlm_u_tlm_tx_ack_mgr_mgr_state_4_0_0_8_ ( + .I0(com_tlm_u_tlm_tx_ack_mgr_N_56066_i), + .I1(com_tlm_u_tlm_tx_ack_mgr_N_56235_i), + .I2(com_tlm_u_tlm_tx_ack_mgr_mgr_state_8__3242), + .I3(com_tlm_u_tlm_tx_ack_mgr_mgr_state_9__3190), + .O(com_tlm_u_tlm_tx_ack_mgr_mgr_state_4_0_0[8]) + ); + defparam com_tlm_u_tlm_tx_ack_mgr_retry_src_rdy_o_3_i_1.INIT = 16'h7F00; + LUT4 com_tlm_u_tlm_tx_ack_mgr_retry_src_rdy_o_3_i_1 ( + .I0(com_tlm_u_tlm_tx_ack_mgr_N_10925_i_i), + .I1(com_tlm_u_tlm_tx_ack_mgr_fifo_nxt_vld), + .I2(com_tlm_u_tlm_tx_ack_mgr_mgr_state_8__3242), + .I3(com_tlm_u_tlm_tx_ack_mgr_retry_src_rdy_o_3_i_0_3191), + .O(com_tlm_u_tlm_tx_ack_mgr_retry_src_rdy_o_3_i_1_3222) + ); + defparam com_tlm_u_tlm_tx_ack_mgr_mgr_statec.INIT = 16'h51F1; + LUT4_L com_tlm_u_tlm_tx_ack_mgr_mgr_statec ( + .I0(com_tlm_u_tlm_tx_ack_mgr_N_10925_i_i), + .I1(com_tlm_u_tlm_tx_ack_mgr_N_56502_i), + .I2(com_tlm_u_tlm_tx_ack_mgr_mgr_state_2__3226), + .I3(com_tlm_u_tlm_tx_un1_frees_pending), + .LO(com_tlm_u_tlm_tx_ack_mgr_mgr_statec_i) + ); + defparam com_tlm_u_tlm_tx_ack_mgr_mgr_statec_0.INIT = 8'hF4; + LUT3_L com_tlm_u_tlm_tx_ack_mgr_mgr_statec_0 ( + .I0(com_tlm_u_tlm_tx_ack_mgr_N_58380_1), + .I1(com_tlm_u_tlm_tx_ack_mgr_mgr_state_4__3193), + .I2(com_tlm_u_tlm_tx_ack_mgr_mgr_state_11__3192), + .LO(com_tlm_u_tlm_tx_ack_mgr_mgr_statec_0_i) + ); + defparam com_tlm_u_tlm_tx_ack_mgr_mgr_statec_2.INIT = 16'hA888; + LUT4_L com_tlm_u_tlm_tx_ack_mgr_mgr_statec_2 ( + .I0(com_tlm_u_tlm_tx_ack_mgr_N_10925_i_i), + .I1(com_tlm_u_tlm_tx_ack_mgr_N_55921_i), + .I2(com_tlm_u_tlm_tx_ack_mgr_N_56351_i), + .I3(com_tlm_u_tlm_tx_ack_mgr_mgr_state_4__3193), + .LO(com_tlm_u_tlm_tx_ack_mgr_mgr_statec_2_i) + ); + defparam com_tlm_u_tlm_tx_ack_mgr_mgr_statec_3.INIT = 16'h8000; + LUT4_L com_tlm_u_tlm_tx_ack_mgr_mgr_statec_3 ( + .I0(com_tlm_u_tlm_tx_ack_mgr_N_10925_i_i), + .I1(com_tlm_u_tlm_tx_ack_mgr_N_56066_i), + .I2(com_tlm_u_tlm_tx_ack_mgr_mgr_state_8__3242), + .I3(com_tlm_u_tlm_tx_ds_buf_src_rdy), + .LO(com_tlm_u_tlm_tx_ack_mgr_mgr_statec_3_i) + ); + defparam com_tlm_u_tlm_tx_ack_mgr_mgr_statec_4.INIT = 16'h00F4; + LUT4_L com_tlm_u_tlm_tx_ack_mgr_mgr_statec_4 ( + .I0(com_tlm_u_tlm_tx_ack_mgr_N_10925_i_i), + .I1(com_tlm_u_tlm_tx_ack_mgr_mgr_state_8__3242), + .I2(com_tlm_u_tlm_tx_ack_mgr_mgr_state_10__3194), + .I3(com_tlm_u_tlm_tx_am_retry_dst_rdy), + .LO(com_tlm_u_tlm_tx_ack_mgr_mgr_statec_4_i) + ); + defparam com_tlm_u_tlm_tx_ack_mgr_mgr_statec_5.INIT = 8'h31; + LUT3_L com_tlm_u_tlm_tx_ack_mgr_mgr_statec_5 ( + .I0(com_tlm_u_tlm_tx_ack_mgr_N_10925_i_i), + .I1(com_tlm_u_tlm_tx_ack_mgr_N_57355), + .I2(com_tlm_u_tlm_tx_ack_mgr_mgr_state_10__3194), + .LO(com_tlm_u_tlm_tx_ack_mgr_mgr_statec_5_i) + ); + defparam com_tlm_u_tlm_tx_ack_mgr_mgr_statec_6.INIT = 8'hA8; + LUT3_L com_tlm_u_tlm_tx_ack_mgr_mgr_statec_6 ( + .I0(com_tlm_u_tlm_tx_ack_mgr_N_10925_i_i), + .I1(com_tlm_u_tlm_tx_ack_mgr_N_56143_i), + .I2(com_tlm_u_tlm_tx_ack_mgr_N_57048_i), + .LO(com_tlm_u_tlm_tx_ack_mgr_mgr_statec_6_i) + ); + defparam com_tlm_u_tlm_tx_ack_mgr_N_86010_i.INIT = 16'hCCDC; + LUT4_L com_tlm_u_tlm_tx_ack_mgr_N_86010_i ( + .I0(com_tlm_u_tlm_tx_N_55899_i), + .I1(com_tlm_u_tlm_tx_ack_mgr_N_58250), + .I2(com_tlm_u_tlm_tx_ack_mgr_N_58380_1), + .I3(com_tlm_u_tlm_tx_ack_mgr_nak_req_3225), + .LO(com_tlm_u_tlm_tx_ack_mgr_N_86010_i_3195) + ); + defparam com_tlm_u_tlm_tx_ack_mgr_un1_oldest_tsn_1_axb_11.INIT = 16'hD800; + LUT4_L com_tlm_u_tlm_tx_ack_mgr_un1_oldest_tsn_1_axb_11 ( + .I0(com_tlm_u_tlm_tx_ack_mgr_N_55893_i), + .I1(com_tlm_u_tlm_tx_ack_mgr_fifo_tsn[11]), + .I2(com_tlm_u_tlm_tx_ack_mgr_newest_freed_tsn[11]), + .I3(plm_link_up_2), + .LO(com_tlm_u_tlm_tx_ack_mgr_un1_oldest_tsn_1_axb_11_3196) + ); + defparam com_tlm_u_tlm_tx_ack_mgr_un1_oldest_tsn_1_axb_10.INIT = 16'hD800; + LUT4_L com_tlm_u_tlm_tx_ack_mgr_un1_oldest_tsn_1_axb_10 ( + .I0(com_tlm_u_tlm_tx_ack_mgr_N_55893_i), + .I1(com_tlm_u_tlm_tx_ack_mgr_fifo_tsn[10]), + .I2(com_tlm_u_tlm_tx_ack_mgr_newest_freed_tsn[10]), + .I3(plm_link_up_2), + .LO(com_tlm_u_tlm_tx_ack_mgr_un1_oldest_tsn_1_axb_10_3197) + ); + defparam com_tlm_u_tlm_tx_ack_mgr_un1_oldest_tsn_1_axb_9.INIT = 16'hD800; + LUT4_L com_tlm_u_tlm_tx_ack_mgr_un1_oldest_tsn_1_axb_9 ( + .I0(com_tlm_u_tlm_tx_ack_mgr_N_55893_i), + .I1(com_tlm_u_tlm_tx_ack_mgr_fifo_tsn[9]), + .I2(com_tlm_u_tlm_tx_ack_mgr_newest_freed_tsn[9]), + .I3(plm_link_up_2), + .LO(com_tlm_u_tlm_tx_ack_mgr_un1_oldest_tsn_1_axb_9_3198) + ); + defparam com_tlm_u_tlm_tx_ack_mgr_un1_oldest_tsn_1_axb_8.INIT = 16'hD800; + LUT4_L com_tlm_u_tlm_tx_ack_mgr_un1_oldest_tsn_1_axb_8 ( + .I0(com_tlm_u_tlm_tx_ack_mgr_N_55893_i), + .I1(com_tlm_u_tlm_tx_ack_mgr_fifo_tsn[8]), + .I2(com_tlm_u_tlm_tx_ack_mgr_newest_freed_tsn[8]), + .I3(plm_link_up_2), + .LO(com_tlm_u_tlm_tx_ack_mgr_un1_oldest_tsn_1_axb_8_3199) + ); + defparam com_tlm_u_tlm_tx_ack_mgr_un1_oldest_tsn_1_axb_7.INIT = 16'hD800; + LUT4_L com_tlm_u_tlm_tx_ack_mgr_un1_oldest_tsn_1_axb_7 ( + .I0(com_tlm_u_tlm_tx_ack_mgr_N_55893_i), + .I1(com_tlm_u_tlm_tx_ack_mgr_fifo_tsn[7]), + .I2(com_tlm_u_tlm_tx_ack_mgr_newest_freed_tsn[7]), + .I3(plm_link_up_2), + .LO(com_tlm_u_tlm_tx_ack_mgr_un1_oldest_tsn_1_axb_7_3200) + ); + defparam com_tlm_u_tlm_tx_ack_mgr_un1_oldest_tsn_1_axb_6.INIT = 16'hD800; + LUT4_L com_tlm_u_tlm_tx_ack_mgr_un1_oldest_tsn_1_axb_6 ( + .I0(com_tlm_u_tlm_tx_ack_mgr_N_55893_i), + .I1(com_tlm_u_tlm_tx_ack_mgr_fifo_tsn[6]), + .I2(com_tlm_u_tlm_tx_ack_mgr_newest_freed_tsn[6]), + .I3(plm_link_up_2), + .LO(com_tlm_u_tlm_tx_ack_mgr_un1_oldest_tsn_1_axb_6_3201) + ); + defparam com_tlm_u_tlm_tx_ack_mgr_un1_oldest_tsn_1_axb_5.INIT = 16'hD800; + LUT4_L com_tlm_u_tlm_tx_ack_mgr_un1_oldest_tsn_1_axb_5 ( + .I0(com_tlm_u_tlm_tx_ack_mgr_N_55893_i), + .I1(com_tlm_u_tlm_tx_ack_mgr_fifo_tsn[5]), + .I2(com_tlm_u_tlm_tx_ack_mgr_newest_freed_tsn[5]), + .I3(plm_link_up_2), + .LO(com_tlm_u_tlm_tx_ack_mgr_un1_oldest_tsn_1_axb_5_3202) + ); + defparam com_tlm_u_tlm_tx_ack_mgr_un1_oldest_tsn_1_axb_4.INIT = 16'hD800; + LUT4_L com_tlm_u_tlm_tx_ack_mgr_un1_oldest_tsn_1_axb_4 ( + .I0(com_tlm_u_tlm_tx_ack_mgr_N_55893_i), + .I1(com_tlm_u_tlm_tx_ack_mgr_fifo_tsn[4]), + .I2(com_tlm_u_tlm_tx_ack_mgr_newest_freed_tsn[4]), + .I3(plm_link_up_2), + .LO(com_tlm_u_tlm_tx_ack_mgr_un1_oldest_tsn_1_axb_4_3203) + ); + defparam com_tlm_u_tlm_tx_ack_mgr_un1_oldest_tsn_1_axb_3.INIT = 16'hD800; + LUT4_L com_tlm_u_tlm_tx_ack_mgr_un1_oldest_tsn_1_axb_3 ( + .I0(com_tlm_u_tlm_tx_ack_mgr_N_55893_i), + .I1(com_tlm_u_tlm_tx_ack_mgr_fifo_tsn[3]), + .I2(com_tlm_u_tlm_tx_ack_mgr_newest_freed_tsn[3]), + .I3(plm_link_up_2), + .LO(com_tlm_u_tlm_tx_ack_mgr_un1_oldest_tsn_1_axb_3_3204) + ); + defparam com_tlm_u_tlm_tx_ack_mgr_un1_oldest_tsn_1_axb_2.INIT = 16'hD800; + LUT4_L com_tlm_u_tlm_tx_ack_mgr_un1_oldest_tsn_1_axb_2 ( + .I0(com_tlm_u_tlm_tx_ack_mgr_N_55893_i), + .I1(com_tlm_u_tlm_tx_ack_mgr_fifo_tsn[2]), + .I2(com_tlm_u_tlm_tx_ack_mgr_newest_freed_tsn[2]), + .I3(plm_link_up_2), + .LO(com_tlm_u_tlm_tx_ack_mgr_un1_oldest_tsn_1_axb_2_3205) + ); + defparam com_tlm_u_tlm_tx_ack_mgr_un1_oldest_tsn_1_axb_1.INIT = 16'hD800; + LUT4_L com_tlm_u_tlm_tx_ack_mgr_un1_oldest_tsn_1_axb_1 ( + .I0(com_tlm_u_tlm_tx_ack_mgr_N_55893_i), + .I1(com_tlm_u_tlm_tx_ack_mgr_fifo_tsn[1]), + .I2(com_tlm_u_tlm_tx_ack_mgr_newest_freed_tsn[1]), + .I3(plm_link_up_2), + .LO(com_tlm_u_tlm_tx_ack_mgr_un1_oldest_tsn_1_axb_1_3206) + ); + defparam com_tlm_u_tlm_tx_ack_mgr_un1_oldest_tsn_1_axb_0.INIT = 16'hD800; + LUT4_L com_tlm_u_tlm_tx_ack_mgr_un1_oldest_tsn_1_axb_0 ( + .I0(com_tlm_u_tlm_tx_ack_mgr_N_55893_i), + .I1(com_tlm_u_tlm_tx_ack_mgr_fifo_tsn[0]), + .I2(com_tlm_u_tlm_tx_ack_mgr_newest_freed_tsn[0]), + .I3(plm_link_up_2), + .LO(com_tlm_u_tlm_tx_ack_mgr_un1_oldest_tsn_1_axb_0_3207) + ); + defparam com_tlm_u_tlm_tx_ack_mgr_N_85576_i.INIT = 16'hA8FF; + LUT4_L com_tlm_u_tlm_tx_ack_mgr_N_85576_i ( + .I0(com_tlm_u_tlm_tx_ack_mgr_N_56235_i), + .I1(com_tlm_u_tlm_tx_ack_mgr_N_58366_1), + .I2(com_tlm_u_tlm_tx_ack_mgr_N_58367_1), + .I3(com_tlm_u_tlm_tx_ack_mgr_mgr_state_4_0_0[8]), + .LO(com_tlm_u_tlm_tx_ack_mgr_N_85576_i_3241) + ); + defparam com_tlm_u_tlm_tx_ack_mgr_N_60497_i.INIT = 4'hE; + LUT2_L com_tlm_u_tlm_tx_ack_mgr_N_60497_i ( + .I0(com_tlm_u_tlm_tx_ack_mgr_fifo_nxt_vld), + .I1(com_tlm_u_tlm_tx_ack_mgr_fifo_vld), + .LO(com_tlm_u_tlm_tx_ack_mgr_N_60497_i_3208) + ); + defparam com_tlm_u_tlm_tx_ack_mgr_nak_in_retry19_0_a2_0_a2_0_a2.INIT = 4'h8; + LUT2_L com_tlm_u_tlm_tx_ack_mgr_nak_in_retry19_0_a2_0_a2_0_a2 ( + .I0(com_tlm_u_tlm_tx_ack_mgr_N_55889_i), + .I1(com_tlm_u_tlm_tx_ack_mgr_N_56340_i), + .LO(com_tlm_u_tlm_tx_ack_mgr_nak_in_retry19) + ); + defparam com_tlm_u_tlm_tx_ack_mgr_un4_retry_tsn_o_axb_11.INIT = 8'hD8; + LUT3_L com_tlm_u_tlm_tx_ack_mgr_un4_retry_tsn_o_axb_11 ( + .I0(com_tlm_u_tlm_tx_ack_mgr_jump_retry_tsn_3244), + .I1(com_tlm_u_tlm_tx_ack_mgr_lnk_rupdate_seq_q[11]), + .I2(com_tlm_u_tlm_tx_am_retry_tsn[11]), + .LO(com_tlm_u_tlm_tx_ack_mgr_un4_retry_tsn_o_axb_11_3209) + ); + defparam com_tlm_u_tlm_tx_ack_mgr_un4_retry_tsn_o_axb_10.INIT = 8'hD8; + LUT3_L com_tlm_u_tlm_tx_ack_mgr_un4_retry_tsn_o_axb_10 ( + .I0(com_tlm_u_tlm_tx_ack_mgr_jump_retry_tsn_3244), + .I1(com_tlm_u_tlm_tx_ack_mgr_lnk_rupdate_seq_q[10]), + .I2(com_tlm_u_tlm_tx_am_retry_tsn[10]), + .LO(com_tlm_u_tlm_tx_ack_mgr_un4_retry_tsn_o_axb_10_3210) + ); + defparam com_tlm_u_tlm_tx_ack_mgr_un4_retry_tsn_o_axb_9.INIT = 8'hD8; + LUT3_L com_tlm_u_tlm_tx_ack_mgr_un4_retry_tsn_o_axb_9 ( + .I0(com_tlm_u_tlm_tx_ack_mgr_jump_retry_tsn_3244), + .I1(com_tlm_u_tlm_tx_ack_mgr_lnk_rupdate_seq_q[9]), + .I2(com_tlm_u_tlm_tx_am_retry_tsn[9]), + .LO(com_tlm_u_tlm_tx_ack_mgr_un4_retry_tsn_o_axb_9_3211) + ); + defparam com_tlm_u_tlm_tx_ack_mgr_un4_retry_tsn_o_axb_8.INIT = 8'hD8; + LUT3_L com_tlm_u_tlm_tx_ack_mgr_un4_retry_tsn_o_axb_8 ( + .I0(com_tlm_u_tlm_tx_ack_mgr_jump_retry_tsn_3244), + .I1(com_tlm_u_tlm_tx_ack_mgr_lnk_rupdate_seq_q[8]), + .I2(com_tlm_u_tlm_tx_am_retry_tsn[8]), + .LO(com_tlm_u_tlm_tx_ack_mgr_un4_retry_tsn_o_axb_8_3212) + ); + defparam com_tlm_u_tlm_tx_ack_mgr_un4_retry_tsn_o_axb_7.INIT = 8'hD8; + LUT3_L com_tlm_u_tlm_tx_ack_mgr_un4_retry_tsn_o_axb_7 ( + .I0(com_tlm_u_tlm_tx_ack_mgr_jump_retry_tsn_3244), + .I1(com_tlm_u_tlm_tx_ack_mgr_lnk_rupdate_seq_q[7]), + .I2(com_tlm_u_tlm_tx_am_retry_tsn[7]), + .LO(com_tlm_u_tlm_tx_ack_mgr_un4_retry_tsn_o_axb_7_3213) + ); + defparam com_tlm_u_tlm_tx_ack_mgr_un4_retry_tsn_o_axb_6.INIT = 8'hD8; + LUT3_L com_tlm_u_tlm_tx_ack_mgr_un4_retry_tsn_o_axb_6 ( + .I0(com_tlm_u_tlm_tx_ack_mgr_jump_retry_tsn_3244), + .I1(com_tlm_u_tlm_tx_ack_mgr_lnk_rupdate_seq_q[6]), + .I2(com_tlm_u_tlm_tx_am_retry_tsn[6]), + .LO(com_tlm_u_tlm_tx_ack_mgr_un4_retry_tsn_o_axb_6_3214) + ); + defparam com_tlm_u_tlm_tx_ack_mgr_un4_retry_tsn_o_axb_5.INIT = 8'hD8; + LUT3_L com_tlm_u_tlm_tx_ack_mgr_un4_retry_tsn_o_axb_5 ( + .I0(com_tlm_u_tlm_tx_ack_mgr_jump_retry_tsn_3244), + .I1(com_tlm_u_tlm_tx_ack_mgr_lnk_rupdate_seq_q[5]), + .I2(com_tlm_u_tlm_tx_am_retry_tsn[5]), + .LO(com_tlm_u_tlm_tx_ack_mgr_un4_retry_tsn_o_axb_5_3215) + ); + defparam com_tlm_u_tlm_tx_ack_mgr_un4_retry_tsn_o_axb_4.INIT = 8'hD8; + LUT3_L com_tlm_u_tlm_tx_ack_mgr_un4_retry_tsn_o_axb_4 ( + .I0(com_tlm_u_tlm_tx_ack_mgr_jump_retry_tsn_3244), + .I1(com_tlm_u_tlm_tx_ack_mgr_lnk_rupdate_seq_q[4]), + .I2(com_tlm_u_tlm_tx_am_retry_tsn[4]), + .LO(com_tlm_u_tlm_tx_ack_mgr_un4_retry_tsn_o_axb_4_3216) + ); + defparam com_tlm_u_tlm_tx_ack_mgr_un4_retry_tsn_o_axb_3.INIT = 8'hD8; + LUT3_L com_tlm_u_tlm_tx_ack_mgr_un4_retry_tsn_o_axb_3 ( + .I0(com_tlm_u_tlm_tx_ack_mgr_jump_retry_tsn_3244), + .I1(com_tlm_u_tlm_tx_ack_mgr_lnk_rupdate_seq_q[3]), + .I2(com_tlm_u_tlm_tx_am_retry_tsn[3]), + .LO(com_tlm_u_tlm_tx_ack_mgr_un4_retry_tsn_o_axb_3_3217) + ); + defparam com_tlm_u_tlm_tx_ack_mgr_un4_retry_tsn_o_axb_2.INIT = 8'hD8; + LUT3_L com_tlm_u_tlm_tx_ack_mgr_un4_retry_tsn_o_axb_2 ( + .I0(com_tlm_u_tlm_tx_ack_mgr_jump_retry_tsn_3244), + .I1(com_tlm_u_tlm_tx_ack_mgr_lnk_rupdate_seq_q[2]), + .I2(com_tlm_u_tlm_tx_am_retry_tsn[2]), + .LO(com_tlm_u_tlm_tx_ack_mgr_un4_retry_tsn_o_axb_2_3218) + ); + defparam com_tlm_u_tlm_tx_ack_mgr_un4_retry_tsn_o_axb_1.INIT = 8'hD8; + LUT3_L com_tlm_u_tlm_tx_ack_mgr_un4_retry_tsn_o_axb_1 ( + .I0(com_tlm_u_tlm_tx_ack_mgr_jump_retry_tsn_3244), + .I1(com_tlm_u_tlm_tx_ack_mgr_lnk_rupdate_seq_q[1]), + .I2(com_tlm_u_tlm_tx_am_retry_tsn[1]), + .LO(com_tlm_u_tlm_tx_ack_mgr_un4_retry_tsn_o_axb_1_3219) + ); + defparam com_tlm_u_tlm_tx_ack_mgr_N_56649_i.INIT = 8'h27; + LUT3_L com_tlm_u_tlm_tx_ack_mgr_N_56649_i ( + .I0(com_tlm_u_tlm_tx_ack_mgr_jump_retry_tsn_3244), + .I1(com_tlm_u_tlm_tx_ack_mgr_lnk_rupdate_seq_q[0]), + .I2(com_tlm_u_tlm_tx_am_retry_tsn[0]), + .LO(com_tlm_u_tlm_tx_ack_mgr_N_56649_i_3220) + ); + defparam com_tlm_u_tlm_tx_ack_mgr_N_85579_i.INIT = 16'hA8FF; + LUT4_L com_tlm_u_tlm_tx_ack_mgr_N_85579_i ( + .I0(com_tlm_u_tlm_tx_ack_mgr_N_10925_i_i), + .I1(com_tlm_u_tlm_tx_ack_mgr_N_58366_1), + .I2(com_tlm_u_tlm_tx_ack_mgr_N_58367_1), + .I3(com_tlm_u_tlm_tx_ack_mgr_retry_src_rdy_o_3_i_1_3222), + .LO(com_tlm_u_tlm_tx_ack_mgr_N_85579_i_3221) + ); + defparam com_tlm_u_tlm_tx_ack_mgr_N_87598_i.INIT = 16'hE0AA; + LUT4_L com_tlm_u_tlm_tx_ack_mgr_N_87598_i ( + .I0(com_tlm_u_tlm_tx_ack_mgr_N_55889_i), + .I1(com_tlm_u_tlm_tx_ack_mgr_nak_in_retry_3224), + .I2(com_tlm_u_tlm_tx_am_retry_dst_rdy), + .I3(com_tlm_u_tlm_tx_am_retry_src_rdy), + .LO(com_tlm_u_tlm_tx_ack_mgr_N_87598_i_3223) + ); + defparam com_tlm_u_tlm_tx_ack_mgr_un1_lnk_rupdate_ack_i_1_i_0_0_o2.INIT = 8'h45; + LUT3 com_tlm_u_tlm_tx_ack_mgr_un1_lnk_rupdate_ack_i_1_i_0_0_o2 ( + .I0(com_reg_tx_update_ack), + .I1(com_reg_tx_update_retry_q), + .I2(com_reg_tx_update_retry_int), + .O(com_tlm_u_tlm_tx_ack_mgr_N_10925_i_i) + ); + defparam com_tlm_u_tlm_tx_ack_mgr_retry_src_rdy_o_3_i_a2_2_1.INIT = 8'h80; + LUT3 com_tlm_u_tlm_tx_ack_mgr_retry_src_rdy_o_3_i_a2_2_1 ( + .I0(com_tlm_u_tlm_tx_ack_mgr_mgr_state_2__3226), + .I1(com_tlm_u_tlm_tx_un1_frees_pending), + .I2(com_tlm_u_tlm_tx_ack_mgr_nak_req_3225), + .O(com_tlm_u_tlm_tx_ack_mgr_N_58366_1) + ); + defparam com_tlm_u_tlm_tx_ack_mgr_N_10925_i_i_i.INIT = 8'hF2; + LUT3 com_tlm_u_tlm_tx_ack_mgr_N_10925_i_i_i ( + .I0(com_reg_tx_update_retry_int), + .I1(com_reg_tx_update_retry_q), + .I2(com_reg_tx_update_ack), + .O(com_tlm_u_tlm_tx_ack_mgr_N_10925_i_i_i_3227) + ); + MUXCY com_tlm_u_tlm_tx_ack_mgr_unreg_skips_pend_un1_skips_pending_0_I_19 ( + .CI(com_tlm_u_tlm_tx_ack_mgr_data_tmp_0[4]), + .DI(com_tlm_u_tlm_tx_ack_mgr_GND_3228), + .O(com_tlm_u_tlm_tx_ack_mgr_un1_skips_pending), + .S(com_tlm_u_tlm_tx_ack_mgr_N_27) + ); + MUXCY com_tlm_u_tlm_tx_ack_mgr_unreg_frees_pend_un1_frees_pending_0_I_19 ( + .CI(com_tlm_u_tlm_tx_ack_mgr_data_tmp[4]), + .DI(com_tlm_u_tlm_tx_ack_mgr_GND_3228), + .O(com_tlm_u_tlm_tx_un1_frees_pending), + .S(com_tlm_u_tlm_tx_ack_mgr_N_27_0) + ); + FD com_tlm_u_tlm_tx_ack_mgr_fifo_tsn_11_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_ack_mgr_un1_oldest_tsn_1_s_11_3229), + .Q(com_tlm_u_tlm_tx_ack_mgr_fifo_tsn[11]) + ); + FD com_tlm_u_tlm_tx_ack_mgr_fifo_tsn_10_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_ack_mgr_un1_oldest_tsn_1_s_10_3230), + .Q(com_tlm_u_tlm_tx_ack_mgr_fifo_tsn[10]) + ); + FD com_tlm_u_tlm_tx_ack_mgr_fifo_tsn_9_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_ack_mgr_un1_oldest_tsn_1_s_9_3231), + .Q(com_tlm_u_tlm_tx_ack_mgr_fifo_tsn[9]) + ); + FD com_tlm_u_tlm_tx_ack_mgr_fifo_tsn_8_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_ack_mgr_un1_oldest_tsn_1_s_8_3232), + .Q(com_tlm_u_tlm_tx_ack_mgr_fifo_tsn[8]) + ); + FD com_tlm_u_tlm_tx_ack_mgr_fifo_tsn_7_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_ack_mgr_un1_oldest_tsn_1_s_7_3233), + .Q(com_tlm_u_tlm_tx_ack_mgr_fifo_tsn[7]) + ); + FD com_tlm_u_tlm_tx_ack_mgr_fifo_tsn_6_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_ack_mgr_un1_oldest_tsn_1_s_6_3234), + .Q(com_tlm_u_tlm_tx_ack_mgr_fifo_tsn[6]) + ); + FD com_tlm_u_tlm_tx_ack_mgr_fifo_tsn_5_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_ack_mgr_un1_oldest_tsn_1_s_5_3235), + .Q(com_tlm_u_tlm_tx_ack_mgr_fifo_tsn[5]) + ); + FD com_tlm_u_tlm_tx_ack_mgr_fifo_tsn_4_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_ack_mgr_un1_oldest_tsn_1_s_4_3236), + .Q(com_tlm_u_tlm_tx_ack_mgr_fifo_tsn[4]) + ); + FD com_tlm_u_tlm_tx_ack_mgr_fifo_tsn_3_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_ack_mgr_un1_oldest_tsn_1_s_3_3237), + .Q(com_tlm_u_tlm_tx_ack_mgr_fifo_tsn[3]) + ); + FD com_tlm_u_tlm_tx_ack_mgr_fifo_tsn_2_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_ack_mgr_un1_oldest_tsn_1_s_2_3238), + .Q(com_tlm_u_tlm_tx_ack_mgr_fifo_tsn[2]) + ); + FD com_tlm_u_tlm_tx_ack_mgr_fifo_tsn_1_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_ack_mgr_un1_oldest_tsn_1_s_1_3239), + .Q(com_tlm_u_tlm_tx_ack_mgr_fifo_tsn[1]) + ); + FD com_tlm_u_tlm_tx_ack_mgr_fifo_tsn_0_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_ack_mgr_un1_oldest_tsn_1_s_0_3240), + .Q(com_tlm_u_tlm_tx_ack_mgr_fifo_tsn[0]) + ); + FD com_tlm_u_tlm_tx_ack_mgr_mgr_state_8_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_ack_mgr_N_85576_i_3241), + .Q(com_tlm_u_tlm_tx_ack_mgr_mgr_state_8__3242) + ); + defparam com_tlm_u_tlm_tx_ack_mgr_newest_freed_tsn_qxu_0_0_.INIT = 4'h2; + LUT1_L com_tlm_u_tlm_tx_ack_mgr_newest_freed_tsn_qxu_0_0_ ( + .I0(com_tlm_u_tlm_tx_ack_mgr_newest_freed_tsn[0]), + .LO(com_tlm_u_tlm_tx_ack_mgr_newest_freed_tsn_qxu[0]) + ); + defparam com_tlm_u_tlm_tx_ack_mgr_newest_freed_tsn_qxu_0_11_.INIT = 4'h2; + LUT1_L com_tlm_u_tlm_tx_ack_mgr_newest_freed_tsn_qxu_0_11_ ( + .I0(com_tlm_u_tlm_tx_ack_mgr_newest_freed_tsn[11]), + .LO(com_tlm_u_tlm_tx_ack_mgr_newest_freed_tsn_qxu[11]) + ); + defparam com_tlm_u_tlm_tx_ack_mgr_newest_freed_tsn_qxu_0_10_.INIT = 4'h2; + LUT1_L com_tlm_u_tlm_tx_ack_mgr_newest_freed_tsn_qxu_0_10_ ( + .I0(com_tlm_u_tlm_tx_ack_mgr_newest_freed_tsn[10]), + .LO(com_tlm_u_tlm_tx_ack_mgr_newest_freed_tsn_qxu[10]) + ); + defparam com_tlm_u_tlm_tx_ack_mgr_newest_freed_tsn_qxu_0_9_.INIT = 4'h2; + LUT1_L com_tlm_u_tlm_tx_ack_mgr_newest_freed_tsn_qxu_0_9_ ( + .I0(com_tlm_u_tlm_tx_ack_mgr_newest_freed_tsn[9]), + .LO(com_tlm_u_tlm_tx_ack_mgr_newest_freed_tsn_qxu[9]) + ); + defparam com_tlm_u_tlm_tx_ack_mgr_newest_freed_tsn_qxu_0_8_.INIT = 4'h2; + LUT1_L com_tlm_u_tlm_tx_ack_mgr_newest_freed_tsn_qxu_0_8_ ( + .I0(com_tlm_u_tlm_tx_ack_mgr_newest_freed_tsn[8]), + .LO(com_tlm_u_tlm_tx_ack_mgr_newest_freed_tsn_qxu[8]) + ); + defparam com_tlm_u_tlm_tx_ack_mgr_newest_freed_tsn_qxu_0_7_.INIT = 4'h2; + LUT1_L com_tlm_u_tlm_tx_ack_mgr_newest_freed_tsn_qxu_0_7_ ( + .I0(com_tlm_u_tlm_tx_ack_mgr_newest_freed_tsn[7]), + .LO(com_tlm_u_tlm_tx_ack_mgr_newest_freed_tsn_qxu[7]) + ); + defparam com_tlm_u_tlm_tx_ack_mgr_newest_freed_tsn_qxu_0_6_.INIT = 4'h2; + LUT1_L com_tlm_u_tlm_tx_ack_mgr_newest_freed_tsn_qxu_0_6_ ( + .I0(com_tlm_u_tlm_tx_ack_mgr_newest_freed_tsn[6]), + .LO(com_tlm_u_tlm_tx_ack_mgr_newest_freed_tsn_qxu[6]) + ); + defparam com_tlm_u_tlm_tx_ack_mgr_newest_freed_tsn_qxu_0_5_.INIT = 4'h2; + LUT1_L com_tlm_u_tlm_tx_ack_mgr_newest_freed_tsn_qxu_0_5_ ( + .I0(com_tlm_u_tlm_tx_ack_mgr_newest_freed_tsn[5]), + .LO(com_tlm_u_tlm_tx_ack_mgr_newest_freed_tsn_qxu[5]) + ); + defparam com_tlm_u_tlm_tx_ack_mgr_newest_freed_tsn_qxu_0_4_.INIT = 4'h2; + LUT1_L com_tlm_u_tlm_tx_ack_mgr_newest_freed_tsn_qxu_0_4_ ( + .I0(com_tlm_u_tlm_tx_ack_mgr_newest_freed_tsn[4]), + .LO(com_tlm_u_tlm_tx_ack_mgr_newest_freed_tsn_qxu[4]) + ); + defparam com_tlm_u_tlm_tx_ack_mgr_newest_freed_tsn_qxu_0_3_.INIT = 4'h2; + LUT1_L com_tlm_u_tlm_tx_ack_mgr_newest_freed_tsn_qxu_0_3_ ( + .I0(com_tlm_u_tlm_tx_ack_mgr_newest_freed_tsn[3]), + .LO(com_tlm_u_tlm_tx_ack_mgr_newest_freed_tsn_qxu[3]) + ); + defparam com_tlm_u_tlm_tx_ack_mgr_newest_freed_tsn_qxu_0_2_.INIT = 4'h2; + LUT1_L com_tlm_u_tlm_tx_ack_mgr_newest_freed_tsn_qxu_0_2_ ( + .I0(com_tlm_u_tlm_tx_ack_mgr_newest_freed_tsn[2]), + .LO(com_tlm_u_tlm_tx_ack_mgr_newest_freed_tsn_qxu[2]) + ); + defparam com_tlm_u_tlm_tx_ack_mgr_newest_freed_tsn_qxu_0_1_.INIT = 4'h2; + LUT1_L com_tlm_u_tlm_tx_ack_mgr_newest_freed_tsn_qxu_0_1_ ( + .I0(com_tlm_u_tlm_tx_ack_mgr_newest_freed_tsn[1]), + .LO(com_tlm_u_tlm_tx_ack_mgr_newest_freed_tsn_qxu[1]) + ); + defparam com_tlm_u_tlm_tx_ack_mgr_newest_freed_tsn_s_0_.INIT = 4'h1; + LUT1_L com_tlm_u_tlm_tx_ack_mgr_newest_freed_tsn_s_0_ ( + .I0(com_tlm_u_tlm_tx_ack_mgr_newest_freed_tsn_qxu[0]), + .LO(com_tlm_u_tlm_tx_ack_mgr_newest_freed_tsn_s[0]) + ); + defparam com_tlm_u_tlm_tx_ack_mgr_unreg_frees_pend_un1_frees_pending_0_I_27.INIT = 16'h8421; + LUT4 com_tlm_u_tlm_tx_ack_mgr_unreg_frees_pend_un1_frees_pending_0_I_27 ( + .I0(com_tlm_u_tlm_tx_ack_mgr_latest_ack_tsn[10]), + .I1(com_tlm_u_tlm_tx_ack_mgr_latest_ack_tsn[11]), + .I2(com_tlm_u_tlm_tx_ack_mgr_newest_freed_tsn[10]), + .I3(com_tlm_u_tlm_tx_ack_mgr_newest_freed_tsn[11]), + .O(com_tlm_u_tlm_tx_ack_mgr_N_27_0) + ); + defparam com_tlm_u_tlm_tx_ack_mgr_unreg_skips_pend_un1_skips_pending_0_I_27.INIT = 16'h8421; + LUT4 com_tlm_u_tlm_tx_ack_mgr_unreg_skips_pend_un1_skips_pending_0_I_27 ( + .I0(com_tlm_u_tlm_tx_ack_mgr_fifo_tsn[10]), + .I1(com_tlm_u_tlm_tx_ack_mgr_fifo_tsn[11]), + .I2(com_tlm_u_tlm_tx_am_retry_tsn[10]), + .I3(com_tlm_u_tlm_tx_am_retry_tsn[11]), + .O(com_tlm_u_tlm_tx_ack_mgr_N_27) + ); + defparam com_tlm_u_tlm_tx_ack_mgr_un4_retry_tsn_o_axb_0.INIT = 8'hD8; + LUT3 com_tlm_u_tlm_tx_ack_mgr_un4_retry_tsn_o_axb_0 ( + .I0(com_tlm_u_tlm_tx_ack_mgr_jump_retry_tsn_3244), + .I1(com_tlm_u_tlm_tx_ack_mgr_lnk_rupdate_seq_q[0]), + .I2(com_tlm_u_tlm_tx_am_retry_tsn[0]), + .O(com_tlm_u_tlm_tx_ack_mgr_un4_retry_tsn_o_axb_0_3243) + ); + defparam com_tlm_u_tlm_tx_ack_mgr_unreg_skips_pend_un1_skips_pending_0_I_54.INIT = 16'h8421; + LUT4 com_tlm_u_tlm_tx_ack_mgr_unreg_skips_pend_un1_skips_pending_0_I_54 ( + .I0(com_tlm_u_tlm_tx_ack_mgr_fifo_tsn[2]), + .I1(com_tlm_u_tlm_tx_ack_mgr_fifo_tsn[3]), + .I2(com_tlm_u_tlm_tx_am_retry_tsn[2]), + .I3(com_tlm_u_tlm_tx_am_retry_tsn[3]), + .O(com_tlm_u_tlm_tx_ack_mgr_N_3_0) + ); + defparam com_tlm_u_tlm_tx_ack_mgr_unreg_skips_pend_un1_skips_pending_0_I_45.INIT = 16'h8421; + LUT4 com_tlm_u_tlm_tx_ack_mgr_unreg_skips_pend_un1_skips_pending_0_I_45 ( + .I0(com_tlm_u_tlm_tx_ack_mgr_fifo_tsn[8]), + .I1(com_tlm_u_tlm_tx_ack_mgr_fifo_tsn[9]), + .I2(com_tlm_u_tlm_tx_am_retry_tsn[8]), + .I3(com_tlm_u_tlm_tx_am_retry_tsn[9]), + .O(com_tlm_u_tlm_tx_ack_mgr_N_11_0) + ); + defparam com_tlm_u_tlm_tx_ack_mgr_unreg_skips_pend_un1_skips_pending_0_I_36.INIT = 16'h8421; + LUT4 com_tlm_u_tlm_tx_ack_mgr_unreg_skips_pend_un1_skips_pending_0_I_36 ( + .I0(com_tlm_u_tlm_tx_ack_mgr_fifo_tsn[6]), + .I1(com_tlm_u_tlm_tx_ack_mgr_fifo_tsn[7]), + .I2(com_tlm_u_tlm_tx_am_retry_tsn[6]), + .I3(com_tlm_u_tlm_tx_am_retry_tsn[7]), + .O(com_tlm_u_tlm_tx_ack_mgr_N_19_0) + ); + defparam com_tlm_u_tlm_tx_ack_mgr_unreg_skips_pend_un1_skips_pending_0_I_18.INIT = 16'h8421; + LUT4 com_tlm_u_tlm_tx_ack_mgr_unreg_skips_pend_un1_skips_pending_0_I_18 ( + .I0(com_tlm_u_tlm_tx_ack_mgr_fifo_tsn[4]), + .I1(com_tlm_u_tlm_tx_ack_mgr_fifo_tsn[5]), + .I2(com_tlm_u_tlm_tx_am_retry_tsn[4]), + .I3(com_tlm_u_tlm_tx_am_retry_tsn[5]), + .O(com_tlm_u_tlm_tx_ack_mgr_N_35_0) + ); + defparam com_tlm_u_tlm_tx_ack_mgr_unreg_skips_pend_un1_skips_pending_0_I_9.INIT = 16'h8421; + LUT4 com_tlm_u_tlm_tx_ack_mgr_unreg_skips_pend_un1_skips_pending_0_I_9 ( + .I0(com_tlm_u_tlm_tx_ack_mgr_fifo_tsn[0]), + .I1(com_tlm_u_tlm_tx_ack_mgr_fifo_tsn[1]), + .I2(com_tlm_u_tlm_tx_am_retry_tsn[0]), + .I3(com_tlm_u_tlm_tx_am_retry_tsn[1]), + .O(com_tlm_u_tlm_tx_ack_mgr_N_43_0) + ); + defparam com_tlm_u_tlm_tx_ack_mgr_unreg_frees_pend_un1_frees_pending_0_I_54.INIT = 16'h8421; + LUT4 com_tlm_u_tlm_tx_ack_mgr_unreg_frees_pend_un1_frees_pending_0_I_54 ( + .I0(com_tlm_u_tlm_tx_ack_mgr_latest_ack_tsn[2]), + .I1(com_tlm_u_tlm_tx_ack_mgr_latest_ack_tsn[3]), + .I2(com_tlm_u_tlm_tx_ack_mgr_newest_freed_tsn[2]), + .I3(com_tlm_u_tlm_tx_ack_mgr_newest_freed_tsn[3]), + .O(com_tlm_u_tlm_tx_ack_mgr_N_3) + ); + defparam com_tlm_u_tlm_tx_ack_mgr_unreg_frees_pend_un1_frees_pending_0_I_45.INIT = 16'h8421; + LUT4 com_tlm_u_tlm_tx_ack_mgr_unreg_frees_pend_un1_frees_pending_0_I_45 ( + .I0(com_tlm_u_tlm_tx_ack_mgr_latest_ack_tsn[8]), + .I1(com_tlm_u_tlm_tx_ack_mgr_latest_ack_tsn[9]), + .I2(com_tlm_u_tlm_tx_ack_mgr_newest_freed_tsn[8]), + .I3(com_tlm_u_tlm_tx_ack_mgr_newest_freed_tsn[9]), + .O(com_tlm_u_tlm_tx_ack_mgr_N_11) + ); + defparam com_tlm_u_tlm_tx_ack_mgr_unreg_frees_pend_un1_frees_pending_0_I_36.INIT = 16'h8421; + LUT4 com_tlm_u_tlm_tx_ack_mgr_unreg_frees_pend_un1_frees_pending_0_I_36 ( + .I0(com_tlm_u_tlm_tx_ack_mgr_latest_ack_tsn[6]), + .I1(com_tlm_u_tlm_tx_ack_mgr_latest_ack_tsn[7]), + .I2(com_tlm_u_tlm_tx_ack_mgr_newest_freed_tsn[6]), + .I3(com_tlm_u_tlm_tx_ack_mgr_newest_freed_tsn[7]), + .O(com_tlm_u_tlm_tx_ack_mgr_N_19) + ); + defparam com_tlm_u_tlm_tx_ack_mgr_unreg_frees_pend_un1_frees_pending_0_I_18.INIT = 16'h8421; + LUT4 com_tlm_u_tlm_tx_ack_mgr_unreg_frees_pend_un1_frees_pending_0_I_18 ( + .I0(com_tlm_u_tlm_tx_ack_mgr_latest_ack_tsn[4]), + .I1(com_tlm_u_tlm_tx_ack_mgr_latest_ack_tsn[5]), + .I2(com_tlm_u_tlm_tx_ack_mgr_newest_freed_tsn[4]), + .I3(com_tlm_u_tlm_tx_ack_mgr_newest_freed_tsn[5]), + .O(com_tlm_u_tlm_tx_ack_mgr_N_35) + ); + defparam com_tlm_u_tlm_tx_ack_mgr_unreg_frees_pend_un1_frees_pending_0_I_9.INIT = 16'h8421; + LUT4 com_tlm_u_tlm_tx_ack_mgr_unreg_frees_pend_un1_frees_pending_0_I_9 ( + .I0(com_tlm_u_tlm_tx_ack_mgr_latest_ack_tsn[0]), + .I1(com_tlm_u_tlm_tx_ack_mgr_latest_ack_tsn[1]), + .I2(com_tlm_u_tlm_tx_ack_mgr_newest_freed_tsn[0]), + .I3(com_tlm_u_tlm_tx_ack_mgr_newest_freed_tsn[1]), + .O(com_tlm_u_tlm_tx_ack_mgr_N_43) + ); + GND com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_GND ( + .G(com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_GND_3245) + ); + SRLC16E com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_srlrow_0__srlcol_0__srlinst ( + .CE(com_tlm_u_tlm_tx_ds_buf_src_rdy), + .D(com_tlm_u_tlm_tx_ds_buf_num[0]), + .Q(com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_shift_tap[0]), + .CLK(NlwRenamedSig_OI_trn_clk), + .Q15(NLW_com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_srlrow_0__srlcol_0__srlinst_Q15_UNCONNECTED), + .A0(com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_raddr_lo[0]), + .A1(com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_raddr_lo[1]), + .A2(com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_raddr_lo[2]), + .A3(com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_raddr_lo[3]) + ); + SRLC16E com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_srlrow_0__srlcol_3__srlinst ( + .CE(com_tlm_u_tlm_tx_ds_buf_src_rdy), + .D(com_tlm_u_tlm_tx_ds_buf_num[3]), + .Q(com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_shift_tap[3]), + .CLK(NlwRenamedSig_OI_trn_clk), + .Q15(NLW_com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_srlrow_0__srlcol_3__srlinst_Q15_UNCONNECTED), + .A0(com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_raddr_lo[0]), + .A1(com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_raddr_lo[1]), + .A2(com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_raddr_lo[2]), + .A3(com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_raddr_lo[3]) + ); + SRLC16E com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_srlrow_0__srlcol_2__srlinst ( + .CE(com_tlm_u_tlm_tx_ds_buf_src_rdy), + .D(com_tlm_u_tlm_tx_ds_buf_num[2]), + .Q(com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_shift_tap[2]), + .CLK(NlwRenamedSig_OI_trn_clk), + .Q15(NLW_com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_srlrow_0__srlcol_2__srlinst_Q15_UNCONNECTED), + .A0(com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_raddr_lo[0]), + .A1(com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_raddr_lo[1]), + .A2(com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_raddr_lo[2]), + .A3(com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_raddr_lo[3]) + ); + SRLC16E com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_srlrow_0__srlcol_1__srlinst ( + .CE(com_tlm_u_tlm_tx_ds_buf_src_rdy), + .D(com_tlm_u_tlm_tx_ds_buf_num[1]), + .Q(com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_shift_tap[1]), + .CLK(NlwRenamedSig_OI_trn_clk), + .Q15(NLW_com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_srlrow_0__srlcol_1__srlinst_Q15_UNCONNECTED), + .A0(com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_raddr_lo[0]), + .A1(com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_raddr_lo[1]), + .A2(com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_raddr_lo[2]), + .A3(com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_raddr_lo[3]) + ); + FDS com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_raddr_lo_0_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_raddr_lo_5_i_m2_i_m3_0[0]), + .Q(com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_raddr_lo[0]), + .S(plm_link_up_i) + ); + FDS com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_raddr_lo_1_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_raddr_lo_5_i_m2_i_m3_0[1]), + .Q(com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_raddr_lo[1]), + .S(plm_link_up_i) + ); + FDS com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_raddr_lo_2_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_raddr_lo_5_i_m2_i_m3_0[2]), + .Q(com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_raddr_lo[2]), + .S(plm_link_up_i) + ); + FDS com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_raddr_lo_3_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_raddr_lo_5_i_m2_i_m3_0[3]), + .Q(com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_raddr_lo[3]), + .S(plm_link_up_i) + ); + FDS com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_bkp_raddr_lo_0_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_N_51180_i), + .Q(com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_bkp_raddr_lo[0]), + .S(plm_link_up_i) + ); + FDS com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_bkp_raddr_lo_1_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_N_51182_i), + .Q(com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_bkp_raddr_lo[1]), + .S(plm_link_up_i) + ); + FDS com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_bkp_raddr_lo_2_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_N_51184_i), + .Q(com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_bkp_raddr_lo[2]), + .S(plm_link_up_i) + ); + FDS com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_bkp_raddr_lo_3_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_N_51186_i), + .Q(com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_bkp_raddr_lo[3]), + .S(plm_link_up_i) + ); + FDRSE com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_bkp_nxt_vld ( + .CE(com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_N_55936_i_i_3266), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_ack_mgr_fifo_nxt_vld), + .Q(com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_bkp_nxt_vld_3258), + .R(plm_link_up_i), + .S(com_tlm_u_tlm_tx_ds_buf_src_rdy) + ); + FDRE com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_nxt_vld_o ( + .CE(com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_N_85539_i_3253), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_nxt_vld_o_8_iv_i_m3_0_3257), + .Q(com_tlm_u_tlm_tx_ack_mgr_fifo_nxt_vld), + .R(plm_link_up_i) + ); + FDRE com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_bkp_vld ( + .CE(com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_N_55936_i_i_3266), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_ack_mgr_fifo_vld), + .Q(com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_bkp_vld_3256), + .R(plm_link_up_i) + ); + FDRE com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_bkp_data_0_ ( + .CE(com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_N_55936_i_i_3266), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_freed_buf[0]), + .Q(com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_bkp_data[0]), + .R(plm_link_up_i) + ); + FDRE com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_bkp_data_1_ ( + .CE(com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_N_55936_i_i_3266), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_freed_buf[1]), + .Q(com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_bkp_data[1]), + .R(plm_link_up_i) + ); + FDRE com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_bkp_data_2_ ( + .CE(com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_N_55936_i_i_3266), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_freed_buf[2]), + .Q(com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_bkp_data[2]), + .R(plm_link_up_i) + ); + FDRE com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_bkp_data_3_ ( + .CE(com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_N_55936_i_i_3266), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_freed_buf[3]), + .Q(com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_bkp_data[3]), + .R(plm_link_up_i) + ); + FDRE com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_vld_o ( + .CE(com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_N_87126_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_vld_o_5_i_m2_i_m3_0_3255), + .Q(com_tlm_u_tlm_tx_ack_mgr_fifo_vld), + .R(plm_link_up_i) + ); + defparam com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_un1_bkp_raddr_lo_1_p4.INIT = 16'h8000; + LUT4_L com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_un1_bkp_raddr_lo_1_p4 ( + .I0(com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_N_51168_i), + .I1(com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_N_51170_i), + .I2(com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_N_51172_i), + .I3(com_tlm_u_tlm_tx_ds_buf_src_rdy), + .LO(com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_un1_bkp_raddr_lo_1_p4_3251) + ); + MUXCY_L com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_un1_raddr_lo_1_cry_0 ( + .CI(com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_GND_3245), + .DI(com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_raddr_lo[0]), + .LO(com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_un1_raddr_lo_1_cry_0_3246), + .S(com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_un1_raddr_lo_1_axb_0_3264) + ); + MUXCY_L com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_un1_raddr_lo_1_cry_1 ( + .CI(com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_un1_raddr_lo_1_cry_0_3246), + .DI(com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_raddr_lo[1]), + .LO(com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_un1_raddr_lo_1_cry_1_3247), + .S(com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_un1_raddr_lo_1_axb_1_3268) + ); + XORCY com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_un1_raddr_lo_1_s_1 ( + .CI(com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_un1_raddr_lo_1_cry_0_3246), + .LI(com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_un1_raddr_lo_1_axb_1_3268), + .O(com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_un1_raddr_lo_1_s_1_3263) + ); + MUXCY_L com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_un1_raddr_lo_1_cry_2 ( + .CI(com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_un1_raddr_lo_1_cry_1_3247), + .DI(com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_raddr_lo[2]), + .LO(com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_un1_raddr_lo_1_cry_2_3248), + .S(com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_un1_raddr_lo_1_axb_2_3267) + ); + XORCY com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_un1_raddr_lo_1_s_2 ( + .CI(com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_un1_raddr_lo_1_cry_1_3247), + .LI(com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_un1_raddr_lo_1_axb_2_3267), + .O(com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_un1_raddr_lo_1_s_2_3262) + ); + XORCY com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_un1_raddr_lo_1_s_3 ( + .CI(com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_un1_raddr_lo_1_cry_2_3248), + .LI(com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_un1_raddr_lo_1_axb_3_3252), + .O(com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_un1_raddr_lo_1_s_3_3261) + ); + defparam com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_raddr_w_backup_ct_o35_0_o3_0.INIT = 4'h8; + LUT2 com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_raddr_w_backup_ct_o35_0_o3_0 ( + .I0(com_tlm_u_tlm_tx_am_retry_dst_rdy), + .I1(com_tlm_u_tlm_tx_am_retry_src_rdy), + .O(com_tlm_u_tlm_tx_ack_mgr_N_55979_i) + ); + defparam com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_raddr_w_backup_ct_o35_0_o3.INIT = 4'h2; + LUT2 com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_raddr_w_backup_ct_o35_0_o3 ( + .I0(com_tlm_u_tlm_tx_ack_mgr_mgr_state_7__3187), + .I1(com_tlm_u_tlm_tx_ack_mgr_un1_skips_pending), + .O(com_tlm_u_tlm_tx_ack_mgr_N_55921_i) + ); + defparam com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_un1_bkp_i_1_i_0_o2.INIT = 4'h1; + LUT2 com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_un1_bkp_i_1_i_0_o2 ( + .I0(com_tlm_u_tlm_tx_ack_mgr_mgr_state_11__3192), + .I1(com_tlm_u_tlm_tx_ack_mgr_mgr_state_12__3184), + .O(com_tlm_u_tlm_tx_ack_mgr_N_55893_i) + ); + defparam com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_raddr_w_backup_ct_o35_0_a2_0_0.INIT = 4'h8; + LUT2 com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_raddr_w_backup_ct_o35_0_a2_0_0 ( + .I0(com_tlm_u_tlm_tx_ack_mgr_fifo_vld), + .I1(com_tlm_u_tlm_tx_ds_buf_src_rdy), + .O(com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_ct_o35_0_a2_0) + ); + defparam com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_raddr_w_backup_ct_o35_0_o3_1.INIT = 4'h1; + LUT2 com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_raddr_w_backup_ct_o35_0_o3_1 ( + .I0(com_tlm_u_tlm_tx_N_55899_i), + .I1(com_tlm_u_tlm_tx_un1_frees_pending), + .O(com_tlm_u_tlm_tx_ack_mgr_N_56106_i) + ); + defparam com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_un1_bkp_i_1_i_0_a2_2.INIT = 16'h0001; + LUT4 com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_un1_bkp_i_1_i_0_a2_2 ( + .I0(com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_raddr_lo[0]), + .I1(com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_raddr_lo[1]), + .I2(com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_raddr_lo[2]), + .I3(com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_raddr_lo[3]), + .O(com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_un1_bkp_i_1_i_0_a2_2_3254) + ); + defparam com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_un1_bkp_raddr_lo_i_a2_1_0_3_.INIT = 4'h4; + LUT2 com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_un1_bkp_raddr_lo_i_a2_1_0_3_ ( + .I0(com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_N_55936_i), + .I1(com_tlm_u_tlm_tx_ds_buf_src_rdy), + .O(com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_N_57365_1) + ); + defparam com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_data_bits_un1_bkp_i_i_0_0_o2.INIT = 16'h0100; + LUT4 com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_data_bits_un1_bkp_i_i_0_0_o2 ( + .I0(com_tlm_u_tlm_tx_ack_mgr_N_55921_i), + .I1(com_tlm_u_tlm_tx_ack_mgr_N_55979_i), + .I2(com_tlm_u_tlm_tx_ack_mgr_N_56106_i), + .I3(com_tlm_u_tlm_tx_ack_mgr_fifo_vld), + .O(com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_un1_bkp_i_i_0_0_o2) + ); + defparam com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_raddr_w_backup_ct_o35_0_a2.INIT = 16'h0100; + LUT4 com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_raddr_w_backup_ct_o35_0_a2 ( + .I0(com_tlm_u_tlm_tx_ack_mgr_N_55921_i), + .I1(com_tlm_u_tlm_tx_ack_mgr_N_55979_i), + .I2(com_tlm_u_tlm_tx_ack_mgr_N_56106_i), + .I3(com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_ct_o35_0_a2_0), + .O(com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_N_57368) + ); + defparam com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_un1_bkp_raddr_lo_i_0_3_.INIT = 8'hDC; + LUT3 com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_un1_bkp_raddr_lo_i_0_3_ ( + .I0(com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_N_55936_i), + .I1(com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_bkp_raddr_lo[3]), + .I2(com_tlm_u_tlm_tx_ds_buf_src_rdy), + .O(com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_un1_bkp_raddr_lo_i_0_3__3250) + ); + defparam com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_un1_bkp_raddr_lo_i_0_0_.INIT = 8'hDC; + LUT3 com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_un1_bkp_raddr_lo_i_0_0_ ( + .I0(com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_N_55936_i), + .I1(com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_bkp_raddr_lo[0]), + .I2(com_tlm_u_tlm_tx_ds_buf_src_rdy), + .O(com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_un1_bkp_raddr_lo_i_0_0__3249) + ); + defparam com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_un1_bkp_raddr_lo_i_0_.INIT = 8'hD0; + LUT3 com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_un1_bkp_raddr_lo_i_0_ ( + .I0(com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_N_57365_1), + .I1(com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_raddr_lo[0]), + .I2(com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_un1_bkp_raddr_lo_i_0_0__3249), + .O(com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_N_51168_i) + ); + defparam com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_un1_bkp_raddr_lo_i_1_.INIT = 16'h3130; + LUT4 com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_un1_bkp_raddr_lo_i_1_ ( + .I0(com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_N_55936_i), + .I1(com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_N_57359), + .I2(com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_bkp_raddr_lo[1]), + .I3(com_tlm_u_tlm_tx_ds_buf_src_rdy), + .O(com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_N_51170_i) + ); + defparam com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_un1_bkp_raddr_lo_i_2_.INIT = 16'h3130; + LUT4 com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_un1_bkp_raddr_lo_i_2_ ( + .I0(com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_N_55936_i), + .I1(com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_N_57362), + .I2(com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_bkp_raddr_lo[2]), + .I3(com_tlm_u_tlm_tx_ds_buf_src_rdy), + .O(com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_N_51172_i) + ); + defparam com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_data_bits_N_87126_i.INIT = 4'h7; + LUT2 com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_data_bits_N_87126_i ( + .I0(com_tlm_u_tlm_tx_ack_mgr_N_55893_i), + .I1(com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_un1_bkp_i_i_0_0_o2), + .O(com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_N_87126_i) + ); + defparam com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_un1_bkp_raddr_lo_1_ac0.INIT = 4'h8; + LUT2_L com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_un1_bkp_raddr_lo_1_ac0 ( + .I0(com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_N_51168_i), + .I1(com_tlm_u_tlm_tx_ds_buf_src_rdy), + .LO(com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_un1_bkp_raddr_lo_1_c1) + ); + defparam com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_un1_bkp_raddr_lo_1_axbxc3.INIT = 16'h2DF0; + LUT4_L com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_un1_bkp_raddr_lo_1_axbxc3 ( + .I0(com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_N_57365_1), + .I1(com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_raddr_lo[3]), + .I2(com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_un1_bkp_raddr_lo_1_p4_3251), + .I3(com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_un1_bkp_raddr_lo_i_0_3__3250), + .LO(com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_un1_bkp_raddr_lo_1_axbxc3_3259) + ); + defparam com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_un1_raddr_lo_1_axb_3.INIT = 16'hCC9C; + LUT4 com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_un1_raddr_lo_1_axb_3 ( + .I0(com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_un1_bkp_i_i_0_0_o2), + .I1(com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_raddr_lo[3]), + .I2(com_tlm_u_tlm_tx_ack_mgr_fifo_nxt_vld), + .I3(com_tlm_u_tlm_tx_ds_buf_src_rdy), + .O(com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_un1_raddr_lo_1_axb_3_3252) + ); + defparam com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_raddr_w_backup_ct_o35_0.INIT = 16'h5045; + LUT4_L com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_raddr_w_backup_ct_o35_0 ( + .I0(com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_N_57368), + .I1(com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_un1_bkp_i_i_0_0_o2), + .I2(com_tlm_u_tlm_tx_ack_mgr_fifo_nxt_vld), + .I3(com_tlm_u_tlm_tx_ds_buf_src_rdy), + .LO(com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_ct_o35_0) + ); + defparam com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_N_85539_i.INIT = 16'hFF75; + LUT4 com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_N_85539_i ( + .I0(com_tlm_u_tlm_tx_ack_mgr_N_55893_i), + .I1(com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_un1_bkp_i_i_0_0_o2), + .I2(com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_un1_bkp_i_1_i_0_a2_2_3254), + .I3(com_tlm_u_tlm_tx_ds_buf_src_rdy), + .O(com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_N_85539_i_3253) + ); + defparam com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_un1_raddr_lo_1_axb_0.INIT = 4'h9; + LUT2 com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_un1_raddr_lo_1_axb_0 ( + .I0(com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_ct_o35_0), + .I1(com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_raddr_lo[0]), + .O(com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_un1_raddr_lo_1_axb_0_3264) + ); + defparam com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_un1_bkp_raddr_lo_1_axbxc2.INIT = 8'h6C; + LUT3_L com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_un1_bkp_raddr_lo_1_axbxc2 ( + .I0(com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_N_51170_i), + .I1(com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_N_51172_i), + .I2(com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_un1_bkp_raddr_lo_1_c1), + .LO(com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_un1_bkp_raddr_lo_1_axbxc2_3260) + ); + defparam com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_data_bits_d_o_4_i_m2_i_m3_0_3_.INIT = 8'hE4; + LUT3_L com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_data_bits_d_o_4_i_m2_i_m3_0_3_ ( + .I0(com_tlm_u_tlm_tx_ack_mgr_N_55893_i), + .I1(com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_bkp_data[3]), + .I2(com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_shift_tap[3]), + .LO(com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_d_o_4_i_m2_i_m3_0[3]) + ); + defparam com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_data_bits_d_o_4_i_m2_i_m3_0_2_.INIT = 8'hE4; + LUT3_L com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_data_bits_d_o_4_i_m2_i_m3_0_2_ ( + .I0(com_tlm_u_tlm_tx_ack_mgr_N_55893_i), + .I1(com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_bkp_data[2]), + .I2(com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_shift_tap[2]), + .LO(com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_d_o_4_i_m2_i_m3_0[2]) + ); + defparam com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_data_bits_d_o_4_i_m2_i_m3_0_1_.INIT = 8'hE4; + LUT3_L com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_data_bits_d_o_4_i_m2_i_m3_0_1_ ( + .I0(com_tlm_u_tlm_tx_ack_mgr_N_55893_i), + .I1(com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_bkp_data[1]), + .I2(com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_shift_tap[1]), + .LO(com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_d_o_4_i_m2_i_m3_0[1]) + ); + defparam com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_data_bits_d_o_4_i_m2_i_m3_0_0_.INIT = 8'hE4; + LUT3_L com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_data_bits_d_o_4_i_m2_i_m3_0_0_ ( + .I0(com_tlm_u_tlm_tx_ack_mgr_N_55893_i), + .I1(com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_bkp_data[0]), + .I2(com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_shift_tap[0]), + .LO(com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_d_o_4_i_m2_i_m3_0[0]) + ); + defparam com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_vld_o_5_i_m2_i_m3_0.INIT = 8'hE4; + LUT3_L com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_vld_o_5_i_m2_i_m3_0 ( + .I0(com_tlm_u_tlm_tx_ack_mgr_N_55893_i), + .I1(com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_bkp_vld_3256), + .I2(com_tlm_u_tlm_tx_ack_mgr_fifo_nxt_vld), + .LO(com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_vld_o_5_i_m2_i_m3_0_3255) + ); + defparam com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_nxt_vld_o_8_iv_i_m3_0.INIT = 8'hE4; + LUT3_L com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_nxt_vld_o_8_iv_i_m3_0 ( + .I0(com_tlm_u_tlm_tx_ack_mgr_N_55893_i), + .I1(com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_bkp_nxt_vld_3258), + .I2(com_tlm_u_tlm_tx_ds_buf_src_rdy), + .LO(com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_nxt_vld_o_8_iv_i_m3_0_3257) + ); + defparam com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_bkp_raddr_lo_7_i_3_.INIT = 16'hCCD8; + LUT4_L com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_bkp_raddr_lo_7_i_3_ ( + .I0(com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_N_55936_i), + .I1(com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_un1_bkp_raddr_lo_1_axbxc3_3259), + .I2(com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_raddr_lo[3]), + .I3(com_tlm_u_tlm_tx_ds_buf_src_rdy), + .LO(com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_N_51186_i) + ); + defparam com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_bkp_raddr_lo_7_i_2_.INIT = 16'hCCD8; + LUT4_L com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_bkp_raddr_lo_7_i_2_ ( + .I0(com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_N_55936_i), + .I1(com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_un1_bkp_raddr_lo_1_axbxc2_3260), + .I2(com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_raddr_lo[2]), + .I3(com_tlm_u_tlm_tx_ds_buf_src_rdy), + .LO(com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_N_51184_i) + ); + defparam com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_bkp_raddr_lo_7_i_1_.INIT = 16'hCCD8; + LUT4_L com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_bkp_raddr_lo_7_i_1_ ( + .I0(com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_N_55936_i), + .I1(com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_un1_bkp_raddr_lo_1_axbxc1_3265), + .I2(com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_raddr_lo[1]), + .I3(com_tlm_u_tlm_tx_ds_buf_src_rdy), + .LO(com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_N_51182_i) + ); + defparam com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_bkp_raddr_lo_7_i_0_.INIT = 16'h55B8; + LUT4_L com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_bkp_raddr_lo_7_i_0_ ( + .I0(com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_N_51168_i), + .I1(com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_N_55936_i), + .I2(com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_raddr_lo[0]), + .I3(com_tlm_u_tlm_tx_ds_buf_src_rdy), + .LO(com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_N_51180_i) + ); + defparam com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_raddr_w_backup_raddr_lo_5_i_m2_i_m3_0_3_.INIT = 8'hE4; + LUT3_L com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_raddr_w_backup_raddr_lo_5_i_m2_i_m3_0_3_ ( + .I0(com_tlm_u_tlm_tx_ack_mgr_N_55893_i), + .I1(com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_bkp_raddr_lo[3]), + .I2(com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_un1_raddr_lo_1_s_3_3261), + .LO(com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_raddr_lo_5_i_m2_i_m3_0[3]) + ); + defparam com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_raddr_w_backup_raddr_lo_5_i_m2_i_m3_0_2_.INIT = 8'hE4; + LUT3_L com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_raddr_w_backup_raddr_lo_5_i_m2_i_m3_0_2_ ( + .I0(com_tlm_u_tlm_tx_ack_mgr_N_55893_i), + .I1(com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_bkp_raddr_lo[2]), + .I2(com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_un1_raddr_lo_1_s_2_3262), + .LO(com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_raddr_lo_5_i_m2_i_m3_0[2]) + ); + defparam com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_raddr_w_backup_raddr_lo_5_i_m2_i_m3_0_1_.INIT = 8'hE4; + LUT3_L com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_raddr_w_backup_raddr_lo_5_i_m2_i_m3_0_1_ ( + .I0(com_tlm_u_tlm_tx_ack_mgr_N_55893_i), + .I1(com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_bkp_raddr_lo[1]), + .I2(com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_un1_raddr_lo_1_s_1_3263), + .LO(com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_raddr_lo_5_i_m2_i_m3_0[1]) + ); + defparam com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_raddr_w_backup_raddr_lo_5_i_m2_i_m3_0_0_.INIT = 8'hE4; + LUT3_L com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_raddr_w_backup_raddr_lo_5_i_m2_i_m3_0_0_ ( + .I0(com_tlm_u_tlm_tx_ack_mgr_N_55893_i), + .I1(com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_bkp_raddr_lo[0]), + .I2(com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_un1_raddr_lo_1_axb_0_3264), + .LO(com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_raddr_lo_5_i_m2_i_m3_0[0]) + ); + defparam com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_un1_bkp_raddr_lo_i_o3_0_.INIT = 8'h01; + LUT3 com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_un1_bkp_raddr_lo_i_o3_0_ ( + .I0(com_tlm_u_tlm_tx_ack_mgr_mgr_state_0__3185), + .I1(com_tlm_u_tlm_tx_ack_mgr_mgr_state_4__3193), + .I2(com_tlm_u_tlm_tx_ack_mgr_mgr_state_2__3226), + .O(com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_N_55936_i) + ); + defparam com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_un1_bkp_raddr_lo_i_a2_1_.INIT = 8'h04; + LUT3_L com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_un1_bkp_raddr_lo_i_a2_1_ ( + .I0(com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_raddr_lo[1]), + .I1(com_tlm_u_tlm_tx_ds_buf_src_rdy), + .I2(com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_N_55936_i), + .LO(com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_N_57359) + ); + defparam com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_un1_bkp_raddr_lo_i_a2_2_.INIT = 8'h04; + LUT3_L com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_un1_bkp_raddr_lo_i_a2_2_ ( + .I0(com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_raddr_lo[2]), + .I1(com_tlm_u_tlm_tx_ds_buf_src_rdy), + .I2(com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_N_55936_i), + .LO(com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_N_57362) + ); + defparam com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_un1_bkp_raddr_lo_1_axbxc1.INIT = 8'h6A; + LUT3_L com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_un1_bkp_raddr_lo_1_axbxc1 ( + .I0(com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_N_51170_i), + .I1(com_tlm_u_tlm_tx_ds_buf_src_rdy), + .I2(com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_N_51168_i), + .LO(com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_un1_bkp_raddr_lo_1_axbxc1_3265) + ); + FDE com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_d_o_3_ ( + .CE(com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_N_87126_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_d_o_4_i_m2_i_m3_0[3]), + .Q(com_tlm_u_tlm_tx_freed_buf[3]) + ); + FDE com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_d_o_2_ ( + .CE(com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_N_87126_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_d_o_4_i_m2_i_m3_0[2]), + .Q(com_tlm_u_tlm_tx_freed_buf[2]) + ); + FDE com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_d_o_1_ ( + .CE(com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_N_87126_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_d_o_4_i_m2_i_m3_0[1]), + .Q(com_tlm_u_tlm_tx_freed_buf[1]) + ); + FDE com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_d_o_0_ ( + .CE(com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_N_87126_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_d_o_4_i_m2_i_m3_0[0]), + .Q(com_tlm_u_tlm_tx_freed_buf[0]) + ); + INV com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_N_55936_i_i ( + .I(com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_N_55936_i), + .O(com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_N_55936_i_i_3266) + ); + defparam com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_un1_raddr_lo_1_axb_2.INIT = 16'hCC9C; + LUT4 com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_un1_raddr_lo_1_axb_2 ( + .I0(com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_un1_bkp_i_i_0_0_o2), + .I1(com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_raddr_lo[2]), + .I2(com_tlm_u_tlm_tx_ack_mgr_fifo_nxt_vld), + .I3(com_tlm_u_tlm_tx_ds_buf_src_rdy), + .O(com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_un1_raddr_lo_1_axb_2_3267) + ); + defparam com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_un1_raddr_lo_1_axb_1.INIT = 16'hCC9C; + LUT4 com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_un1_raddr_lo_1_axb_1 ( + .I0(com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_un1_bkp_i_i_0_0_o2), + .I1(com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_raddr_lo[1]), + .I2(com_tlm_u_tlm_tx_ack_mgr_fifo_nxt_vld), + .I3(com_tlm_u_tlm_tx_ds_buf_src_rdy), + .O(com_tlm_u_tlm_tx_ack_mgr_buf_num_fifo_un1_raddr_lo_1_axb_1_3268) + ); + defparam com_tlm_u_tlm_tx_fc_snk_fc_init_vld_o_0_a2.INIT = 4'h2; + LUT2_L com_tlm_u_tlm_tx_fc_snk_fc_init_vld_o_0_a2 ( + .I0(com_lnk_rfc_type[2]), + .I1(com_lnk_rfc_vc_n[0]), + .LO(com_tlm_u_tlm_tx_fc_init_vld) + ); + defparam com_tlm_u_tlm_tx_fc_snk_fc_update_vld_o_0_a2.INIT = 4'h1; + LUT2_L com_tlm_u_tlm_tx_fc_snk_fc_update_vld_o_0_a2 ( + .I0(com_lnk_rfc_type[2]), + .I1(com_lnk_rfc_vc_n[0]), + .LO(com_tlm_u_tlm_tx_fc_update_vld) + ); + VCC com_tlm_u_tlm_tx_vc0_buf_pool_VCC ( + .P(com_tlm_u_tlm_tx_vc0_buf_pool_VCC_3272) + ); + GND com_tlm_u_tlm_tx_vc0_buf_pool_GND ( + .G(com_tlm_u_tlm_tx_vc0_buf_pool_GND_3279) + ); + FDRSE com_tlm_u_tlm_tx_vc0_buf_pool_buf_avail ( + .CE(com_tlm_u_tlm_tx_vc0_buf_pool_N_20353_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_buf_pool_GND_3279), + .Q(com_tlm_u_tlm_tx_vc0_in_frame), + .R(plm_link_up_i), + .S(com_tlm_u_tlm_tx_vc0_buf_pool_in_frame17_i_i_a2_0_a2_3283) + ); + FDRE com_tlm_u_tlm_tx_vc0_buf_pool_src_rdy_d ( + .CE(com_tlm_u_tlm_tx_vc0_buf_pool_N_55898_i_i_3442), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_buf_pool_rvld_q_any_3302), + .Q(com_tlm_u_tlm_tx_vc0_src_rdy), + .R(plm_link_up_i) + ); + FDRE com_tlm_u_tlm_tx_vc0_buf_pool_rvld_q_any ( + .CE(com_tlm_u_tlm_tx_vc0_buf_pool_N_86909_i_3305), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_buf_pool_rvld_any_3303), + .Q(com_tlm_u_tlm_tx_vc0_buf_pool_rvld_q_any_3302), + .R(plm_link_up_i) + ); + FDRE com_tlm_u_tlm_tx_vc0_buf_pool_rvld_bit_1__rvld_1_ ( + .CE(com_tlm_u_tlm_tx_vc0_buf_pool_N_85563_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_buf_pool_rvld_10[1]), + .Q(com_tlm_u_tlm_tx_vc0_buf_pool_rvld[1]), + .R(plm_link_up_i) + ); + FDRE com_tlm_u_tlm_tx_vc0_buf_pool_rvld_bit_0__rvld_0_ ( + .CE(com_tlm_u_tlm_tx_vc0_buf_pool_N_85563_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_buf_pool_rvld_3[0]), + .Q(com_tlm_u_tlm_tx_vc0_buf_pool_rvld[0]), + .R(plm_link_up_i) + ); + FDRE com_tlm_u_tlm_tx_vc0_buf_pool_rvld_any ( + .CE(com_tlm_u_tlm_tx_vc0_buf_pool_N_85563_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_buf_pool_N_62985_i_3298), + .Q(com_tlm_u_tlm_tx_vc0_buf_pool_rvld_any_3303), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_tx_vc0_buf_pool_rdata_sof_d_hold ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_buf_pool_N_87188_i_3297), + .Q(com_tlm_u_tlm_tx_vc0_buf_pool_rdata_sof_d_hold_3281), + .R(plm_link_up_i) + ); + FDRE com_tlm_u_tlm_tx_vc0_buf_pool_rem_d ( + .CE(com_tlm_u_tlm_tx_vc0_buf_pool_N_55898_i_i_3442), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_buf_pool_rdata_q_i_0_i_a2[68]), + .Q(com_tlm_u_tlm_tx_vc0_rem), + .R(plm_link_up_i) + ); + FDRE com_tlm_u_tlm_tx_vc0_buf_pool_wdata_vld_bit_1__wdata_vld_1_ ( + .CE(com_tlm_u_tlm_tx_vc0_buf_pool_N_59233_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_buf_pool_N_27041_i), + .Q(com_tlm_u_tlm_tx_vc0_buf_pool_wdata_vld[1]), + .R(plm_link_up_i) + ); + FDRE com_tlm_u_tlm_tx_vc0_buf_pool_wdata_vld_bit_0__wdata_vld_0_ ( + .CE(com_tlm_u_tlm_tx_vc0_buf_pool_N_59233_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_buf_pool_N_27045_i), + .Q(com_tlm_u_tlm_tx_vc0_buf_pool_wdata_vld[0]), + .R(plm_link_up_i) + ); + FDRE com_tlm_u_tlm_tx_vc0_buf_pool_wdata_vld_any ( + .CE(com_tlm_u_tlm_tx_vc0_buf_pool_N_59233_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_trn_vld), + .Q(com_tlm_u_tlm_tx_vc0_buf_pool_wdata_vld_any_3282), + .R(plm_link_up_i) + ); + FDRE com_tlm_u_tlm_tx_vc0_buf_pool_sof_d ( + .CE(com_tlm_u_tlm_tx_vc0_buf_pool_N_55898_i_i_3442), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_buf_pool_N_56200_i_i), + .Q(com_tlm_u_tlm_tx_vc0_sof), + .R(plm_link_up_i) + ); + FDRE com_tlm_u_tlm_tx_vc0_buf_pool_eof_d ( + .CE(com_tlm_u_tlm_tx_vc0_buf_pool_N_55898_i_i_3442), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_buf_pool_N_59099_i_3290), + .Q(com_tlm_u_tlm_tx_vc0_eof), + .R(plm_link_up_i) + ); + FDRE com_tlm_u_tlm_tx_vc0_buf_pool_rdata_q_all_136_ ( + .CE(com_tlm_u_tlm_tx_vc0_buf_pool_N_86909_i_3305), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_buf_pool_rdata_q_all_18_136_), + .Q(com_tlm_u_tlm_tx_vc0_buf_pool_rdata_q_all_136__3293), + .R(plm_link_up_i) + ); + FDRE com_tlm_u_tlm_tx_vc0_buf_pool_rdata_q_all_137_ ( + .CE(com_tlm_u_tlm_tx_vc0_buf_pool_N_86909_i_3305), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_buf_pool_rdata_q_all_18_137_), + .Q(com_tlm_u_tlm_tx_vc0_buf_pool_rdata_q_all_137__3291), + .R(plm_link_up_i) + ); + FDRE com_tlm_u_tlm_tx_vc0_buf_pool_rdata_q_all_138_ ( + .CE(com_tlm_u_tlm_tx_vc0_buf_pool_N_86909_i_3305), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_buf_pool_rdata_q_all_18_138_), + .Q(com_tlm_u_tlm_tx_vc0_buf_pool_rdata_q_all_138__3269), + .R(plm_link_up_i) + ); + FDRE com_tlm_u_tlm_tx_vc0_buf_pool_rdata_q_all_139_ ( + .CE(com_tlm_u_tlm_tx_vc0_buf_pool_N_86909_i_3305), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_N_55914_i), + .Q(com_tlm_u_tlm_tx_vc0_buf_pool_rdata_q_all_139__3299), + .R(plm_link_up_i) + ); + FDRE com_tlm_u_tlm_tx_vc0_buf_pool_rdata_q_all_140_ ( + .CE(com_tlm_u_tlm_tx_vc0_buf_pool_N_86909_i_3305), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_buf_pool_rdata_q_all_18_140_), + .Q(com_tlm_u_tlm_tx_vc0_buf_pool_rdata_q_all_140__3295), + .R(plm_link_up_i) + ); + FDRE com_tlm_u_tlm_tx_vc0_buf_pool_rdata_q_all_64_ ( + .CE(com_tlm_u_tlm_tx_vc0_buf_pool_N_86909_i_3305), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_buf_pool_rdata_q_all_5_64_), + .Q(com_tlm_u_tlm_tx_vc0_buf_pool_rdata_q_all_64__3294), + .R(plm_link_up_i) + ); + FDRE com_tlm_u_tlm_tx_vc0_buf_pool_rdata_q_all_65_ ( + .CE(com_tlm_u_tlm_tx_vc0_buf_pool_N_86909_i_3305), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_buf_pool_rdata_q_all_5_65_), + .Q(com_tlm_u_tlm_tx_vc0_buf_pool_rdata_q_all_65__3292), + .R(plm_link_up_i) + ); + FDRE com_tlm_u_tlm_tx_vc0_buf_pool_rdata_q_all_66_ ( + .CE(com_tlm_u_tlm_tx_vc0_buf_pool_N_86909_i_3305), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_buf_pool_rdata_q_all_5_66_), + .Q(com_tlm_u_tlm_tx_vc0_buf_pool_rdata_q_all_66__3270), + .R(plm_link_up_i) + ); + FDRE com_tlm_u_tlm_tx_vc0_buf_pool_rdata_q_all_67_ ( + .CE(com_tlm_u_tlm_tx_vc0_buf_pool_N_86909_i_3305), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_N_55980_i), + .Q(com_tlm_u_tlm_tx_vc0_buf_pool_rdata_q_all_67__3300), + .R(plm_link_up_i) + ); + FDRE com_tlm_u_tlm_tx_vc0_buf_pool_rdata_q_all_68_ ( + .CE(com_tlm_u_tlm_tx_vc0_buf_pool_N_86909_i_3305), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_buf_pool_rdata_q_all_5_68_), + .Q(com_tlm_u_tlm_tx_vc0_buf_pool_rdata_q_all_68__3296), + .R(plm_link_up_i) + ); + FDRE com_tlm_u_tlm_tx_vc0_buf_pool_rvld_q_0_ ( + .CE(com_tlm_u_tlm_tx_vc0_buf_pool_N_86909_i_1_3304), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_buf_pool_rvld[0]), + .Q(com_tlm_u_tlm_tx_vc0_buf_pool_rvld_q[0]), + .R(plm_link_up_i) + ); + FDRE com_tlm_u_tlm_tx_vc0_buf_pool_rvld_q_1_ ( + .CE(com_tlm_u_tlm_tx_vc0_buf_pool_N_86909_i_1_3304), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_buf_pool_rvld[1]), + .Q(com_tlm_u_tlm_tx_vc0_buf_pool_rvld_q[1]), + .R(plm_link_up_i) + ); + FDRSE com_tlm_u_tlm_tx_vc0_buf_pool_errfwd_wen ( + .CE(com_tlm_u_tlm_tx_vc0_trn_vld), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_buf_pool_GND_3279), + .Q(com_tlm_u_tlm_tx_vc0_buf_pool_errfwd_wen_3271), + .R(plm_link_up_i), + .S(com_tlm_u_tlm_tx_vc0_buf_pool_N_27043_i) + ); + RAM16X1D com_tlm_u_tlm_tx_vc0_buf_pool_errfwd_0_I_1 ( + .DPO(com_tlm_u_tlm_tx_vc0_buf_pool_errfwd), + .WCLK(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_buf_pool_wdata_errfwd_3441), + .A0(com_tlm_u_tlm_tx_vc0_buf_pool_waddr_h[0]), + .A1(com_tlm_u_tlm_tx_vc0_buf_pool_waddr_h[1]), + .A2(com_tlm_u_tlm_tx_vc0_buf_pool_waddr_h[2]), + .A3(com_tlm_u_tlm_tx_vc0_buf_pool_waddr_h[3]), + .DPRA0(com_tlm_u_tlm_tx_vc0_buf_pool_raddr_h[0]), + .DPRA1(com_tlm_u_tlm_tx_vc0_buf_pool_raddr_h[1]), + .DPRA2(com_tlm_u_tlm_tx_vc0_buf_pool_raddr_h[2]), + .DPRA3(com_tlm_u_tlm_tx_vc0_buf_pool_raddr_h[3]), + .SPO(NLW_com_tlm_u_tlm_tx_vc0_buf_pool_errfwd_0_I_1_SPO_UNCONNECTED), + .WE(com_tlm_u_tlm_tx_vc0_buf_pool_errfwd_wen_3271) + ); + MUXCY_L com_tlm_u_tlm_tx_vc0_buf_pool_waddr_l_1_cry_0 ( + .CI(com_tlm_u_tlm_tx_vc0_buf_pool_VCC_3272), + .DI(com_tlm_u_tlm_tx_vc0_buf_pool_GND_3279), + .LO(com_tlm_u_tlm_tx_vc0_buf_pool_waddr_l_1_cry_0_3273), + .S(com_tlm_u_tlm_tx_vc0_buf_pool_waddr_l_1_axb_0_3443) + ); + MUXCY_L com_tlm_u_tlm_tx_vc0_buf_pool_waddr_l_1_cry_1 ( + .CI(com_tlm_u_tlm_tx_vc0_buf_pool_waddr_l_1_cry_0_3273), + .DI(com_tlm_u_tlm_tx_vc0_buf_pool_GND_3279), + .LO(com_tlm_u_tlm_tx_vc0_buf_pool_waddr_l_1_cry_1_3274), + .S(com_tlm_u_tlm_tx_vc0_buf_pool_waddr_l_1_axb_1_3289) + ); + XORCY com_tlm_u_tlm_tx_vc0_buf_pool_waddr_l_1_s_1 ( + .CI(com_tlm_u_tlm_tx_vc0_buf_pool_waddr_l_1_cry_0_3273), + .LI(com_tlm_u_tlm_tx_vc0_buf_pool_waddr_l_1_axb_1_3289), + .O(com_tlm_u_tlm_tx_vc0_buf_pool_waddr_l_1[1]) + ); + MUXCY_L com_tlm_u_tlm_tx_vc0_buf_pool_waddr_l_1_cry_2 ( + .CI(com_tlm_u_tlm_tx_vc0_buf_pool_waddr_l_1_cry_1_3274), + .DI(com_tlm_u_tlm_tx_vc0_buf_pool_GND_3279), + .LO(com_tlm_u_tlm_tx_vc0_buf_pool_waddr_l_1_cry_2_3275), + .S(com_tlm_u_tlm_tx_vc0_buf_pool_waddr_l_1_axb_2_3288) + ); + XORCY com_tlm_u_tlm_tx_vc0_buf_pool_waddr_l_1_s_2 ( + .CI(com_tlm_u_tlm_tx_vc0_buf_pool_waddr_l_1_cry_1_3274), + .LI(com_tlm_u_tlm_tx_vc0_buf_pool_waddr_l_1_axb_2_3288), + .O(com_tlm_u_tlm_tx_vc0_buf_pool_waddr_l_1[2]) + ); + MUXCY_L com_tlm_u_tlm_tx_vc0_buf_pool_waddr_l_1_cry_3 ( + .CI(com_tlm_u_tlm_tx_vc0_buf_pool_waddr_l_1_cry_2_3275), + .DI(com_tlm_u_tlm_tx_vc0_buf_pool_GND_3279), + .LO(com_tlm_u_tlm_tx_vc0_buf_pool_waddr_l_1_cry_3_3276), + .S(com_tlm_u_tlm_tx_vc0_buf_pool_waddr_l_1_axb_3_3287) + ); + XORCY com_tlm_u_tlm_tx_vc0_buf_pool_waddr_l_1_s_3 ( + .CI(com_tlm_u_tlm_tx_vc0_buf_pool_waddr_l_1_cry_2_3275), + .LI(com_tlm_u_tlm_tx_vc0_buf_pool_waddr_l_1_axb_3_3287), + .O(com_tlm_u_tlm_tx_vc0_buf_pool_waddr_l_1[3]) + ); + MUXCY_L com_tlm_u_tlm_tx_vc0_buf_pool_waddr_l_1_cry_4 ( + .CI(com_tlm_u_tlm_tx_vc0_buf_pool_waddr_l_1_cry_3_3276), + .DI(com_tlm_u_tlm_tx_vc0_buf_pool_GND_3279), + .LO(com_tlm_u_tlm_tx_vc0_buf_pool_waddr_l_1_cry_4_3277), + .S(com_tlm_u_tlm_tx_vc0_buf_pool_waddr_l_1_axb_4_3286) + ); + XORCY com_tlm_u_tlm_tx_vc0_buf_pool_waddr_l_1_s_4 ( + .CI(com_tlm_u_tlm_tx_vc0_buf_pool_waddr_l_1_cry_3_3276), + .LI(com_tlm_u_tlm_tx_vc0_buf_pool_waddr_l_1_axb_4_3286), + .O(com_tlm_u_tlm_tx_vc0_buf_pool_waddr_l_1[4]) + ); + MUXCY_L com_tlm_u_tlm_tx_vc0_buf_pool_waddr_l_1_cry_5 ( + .CI(com_tlm_u_tlm_tx_vc0_buf_pool_waddr_l_1_cry_4_3277), + .DI(com_tlm_u_tlm_tx_vc0_buf_pool_GND_3279), + .LO(com_tlm_u_tlm_tx_vc0_buf_pool_waddr_l_1_cry_5_3278), + .S(com_tlm_u_tlm_tx_vc0_buf_pool_waddr_l_1_axb_5_3285) + ); + XORCY com_tlm_u_tlm_tx_vc0_buf_pool_waddr_l_1_s_5 ( + .CI(com_tlm_u_tlm_tx_vc0_buf_pool_waddr_l_1_cry_4_3277), + .LI(com_tlm_u_tlm_tx_vc0_buf_pool_waddr_l_1_axb_5_3285), + .O(com_tlm_u_tlm_tx_vc0_buf_pool_waddr_l_1[5]) + ); + XORCY com_tlm_u_tlm_tx_vc0_buf_pool_waddr_l_1_s_6 ( + .CI(com_tlm_u_tlm_tx_vc0_buf_pool_waddr_l_1_cry_5_3278), + .LI(com_tlm_u_tlm_tx_vc0_buf_pool_waddr_l_1_axb_6_3284), + .O(com_tlm_u_tlm_tx_vc0_buf_pool_waddr_l_1[6]) + ); + FDRE com_tlm_u_tlm_tx_vc0_buf_pool_raddr_l_0_ ( + .CE(com_tlm_u_tlm_tx_vc0_buf_pool_en_ram_i_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_buf_pool_raddr_l_s[0]), + .Q(com_tlm_u_tlm_tx_vc0_buf_pool_raddr_l[0]), + .R(com_tlm_u_tlm_tx_vc0_N_55858_i) + ); + MUXCY_L com_tlm_u_tlm_tx_vc0_buf_pool_raddr_l_cry_1_ ( + .CI(com_tlm_u_tlm_tx_vc0_buf_pool_raddr_l[0]), + .DI(com_tlm_u_tlm_tx_vc0_buf_pool_GND_3279), + .LO(com_tlm_u_tlm_tx_vc0_buf_pool_raddr_l_cry[1]), + .S(com_tlm_u_tlm_tx_vc0_buf_pool_raddr_l_qxu[1]) + ); + XORCY com_tlm_u_tlm_tx_vc0_buf_pool_raddr_l_s_1_ ( + .CI(com_tlm_u_tlm_tx_vc0_buf_pool_raddr_l[0]), + .LI(com_tlm_u_tlm_tx_vc0_buf_pool_raddr_l_qxu[1]), + .O(com_tlm_u_tlm_tx_vc0_buf_pool_raddr_l_s[1]) + ); + FDRE com_tlm_u_tlm_tx_vc0_buf_pool_raddr_l_1_ ( + .CE(com_tlm_u_tlm_tx_vc0_buf_pool_en_ram_i_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_buf_pool_raddr_l_s[1]), + .Q(com_tlm_u_tlm_tx_vc0_buf_pool_raddr_l[1]), + .R(com_tlm_u_tlm_tx_vc0_N_55858_i) + ); + MUXCY_L com_tlm_u_tlm_tx_vc0_buf_pool_raddr_l_cry_2_ ( + .CI(com_tlm_u_tlm_tx_vc0_buf_pool_raddr_l_cry[1]), + .DI(com_tlm_u_tlm_tx_vc0_buf_pool_GND_3279), + .LO(com_tlm_u_tlm_tx_vc0_buf_pool_raddr_l_cry[2]), + .S(com_tlm_u_tlm_tx_vc0_buf_pool_raddr_l_qxu[2]) + ); + XORCY com_tlm_u_tlm_tx_vc0_buf_pool_raddr_l_s_2_ ( + .CI(com_tlm_u_tlm_tx_vc0_buf_pool_raddr_l_cry[1]), + .LI(com_tlm_u_tlm_tx_vc0_buf_pool_raddr_l_qxu[2]), + .O(com_tlm_u_tlm_tx_vc0_buf_pool_raddr_l_s[2]) + ); + FDRE com_tlm_u_tlm_tx_vc0_buf_pool_raddr_l_2_ ( + .CE(com_tlm_u_tlm_tx_vc0_buf_pool_en_ram_i_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_buf_pool_raddr_l_s[2]), + .Q(com_tlm_u_tlm_tx_vc0_buf_pool_raddr_l[2]), + .R(com_tlm_u_tlm_tx_vc0_N_55858_i) + ); + MUXCY_L com_tlm_u_tlm_tx_vc0_buf_pool_raddr_l_cry_3_ ( + .CI(com_tlm_u_tlm_tx_vc0_buf_pool_raddr_l_cry[2]), + .DI(com_tlm_u_tlm_tx_vc0_buf_pool_GND_3279), + .LO(com_tlm_u_tlm_tx_vc0_buf_pool_raddr_l_cry[3]), + .S(com_tlm_u_tlm_tx_vc0_buf_pool_raddr_l_qxu[3]) + ); + XORCY com_tlm_u_tlm_tx_vc0_buf_pool_raddr_l_s_3_ ( + .CI(com_tlm_u_tlm_tx_vc0_buf_pool_raddr_l_cry[2]), + .LI(com_tlm_u_tlm_tx_vc0_buf_pool_raddr_l_qxu[3]), + .O(com_tlm_u_tlm_tx_vc0_buf_pool_raddr_l_s[3]) + ); + FDRE com_tlm_u_tlm_tx_vc0_buf_pool_raddr_l_3_ ( + .CE(com_tlm_u_tlm_tx_vc0_buf_pool_en_ram_i_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_buf_pool_raddr_l_s[3]), + .Q(com_tlm_u_tlm_tx_vc0_buf_pool_raddr_l[3]), + .R(com_tlm_u_tlm_tx_vc0_N_55858_i) + ); + MUXCY_L com_tlm_u_tlm_tx_vc0_buf_pool_raddr_l_cry_4_ ( + .CI(com_tlm_u_tlm_tx_vc0_buf_pool_raddr_l_cry[3]), + .DI(com_tlm_u_tlm_tx_vc0_buf_pool_GND_3279), + .LO(com_tlm_u_tlm_tx_vc0_buf_pool_raddr_l_cry[4]), + .S(com_tlm_u_tlm_tx_vc0_buf_pool_raddr_l_qxu[4]) + ); + XORCY com_tlm_u_tlm_tx_vc0_buf_pool_raddr_l_s_4_ ( + .CI(com_tlm_u_tlm_tx_vc0_buf_pool_raddr_l_cry[3]), + .LI(com_tlm_u_tlm_tx_vc0_buf_pool_raddr_l_qxu[4]), + .O(com_tlm_u_tlm_tx_vc0_buf_pool_raddr_l_s[4]) + ); + FDRE com_tlm_u_tlm_tx_vc0_buf_pool_raddr_l_4_ ( + .CE(com_tlm_u_tlm_tx_vc0_buf_pool_en_ram_i_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_buf_pool_raddr_l_s[4]), + .Q(com_tlm_u_tlm_tx_vc0_buf_pool_raddr_l[4]), + .R(com_tlm_u_tlm_tx_vc0_N_55858_i) + ); + MUXCY_L com_tlm_u_tlm_tx_vc0_buf_pool_raddr_l_cry_5_ ( + .CI(com_tlm_u_tlm_tx_vc0_buf_pool_raddr_l_cry[4]), + .DI(com_tlm_u_tlm_tx_vc0_buf_pool_GND_3279), + .LO(com_tlm_u_tlm_tx_vc0_buf_pool_raddr_l_cry[5]), + .S(com_tlm_u_tlm_tx_vc0_buf_pool_raddr_l_qxu[5]) + ); + XORCY com_tlm_u_tlm_tx_vc0_buf_pool_raddr_l_s_5_ ( + .CI(com_tlm_u_tlm_tx_vc0_buf_pool_raddr_l_cry[4]), + .LI(com_tlm_u_tlm_tx_vc0_buf_pool_raddr_l_qxu[5]), + .O(com_tlm_u_tlm_tx_vc0_buf_pool_raddr_l_s[5]) + ); + FDRE com_tlm_u_tlm_tx_vc0_buf_pool_raddr_l_5_ ( + .CE(com_tlm_u_tlm_tx_vc0_buf_pool_en_ram_i_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_buf_pool_raddr_l_s[5]), + .Q(com_tlm_u_tlm_tx_vc0_buf_pool_raddr_l[5]), + .R(com_tlm_u_tlm_tx_vc0_N_55858_i) + ); + XORCY com_tlm_u_tlm_tx_vc0_buf_pool_raddr_l_s_6_ ( + .CI(com_tlm_u_tlm_tx_vc0_buf_pool_raddr_l_cry[5]), + .LI(com_tlm_u_tlm_tx_vc0_buf_pool_raddr_l_qxu[6]), + .O(com_tlm_u_tlm_tx_vc0_buf_pool_raddr_l_s[6]) + ); + FDRE com_tlm_u_tlm_tx_vc0_buf_pool_raddr_l_6_ ( + .CE(com_tlm_u_tlm_tx_vc0_buf_pool_en_ram_i_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_buf_pool_raddr_l_s[6]), + .Q(com_tlm_u_tlm_tx_vc0_buf_pool_raddr_l[6]), + .R(com_tlm_u_tlm_tx_vc0_N_55858_i) + ); + FDR com_tlm_u_tlm_tx_vc0_buf_pool_start_xfer_q ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_N_55858_i), + .Q(com_tlm_u_tlm_tx_vc0_buf_pool_start_xfer_q_3280), + .R(plm_link_up_i) + ); + defparam com_tlm_u_tlm_tx_vc0_buf_pool_un2_start_dst_rdy_o_i_0_0_0_o3.INIT = 4'h8; + LUT2 com_tlm_u_tlm_tx_vc0_buf_pool_un2_start_dst_rdy_o_i_0_0_0_o3 ( + .I0(com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all_139_), + .I1(com_tlm_u_tlm_tx_vc0_buf_pool_rvld[1]), + .O(com_tlm_u_tlm_tx_vc0_N_55914_i) + ); + defparam com_tlm_u_tlm_tx_vc0_buf_pool_un2_start_dst_rdy_o_i_0_0_0_o3_0.INIT = 4'h8; + LUT2 com_tlm_u_tlm_tx_vc0_buf_pool_un2_start_dst_rdy_o_i_0_0_0_o3_0 ( + .I0(com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all_67_), + .I1(com_tlm_u_tlm_tx_vc0_buf_pool_rvld[0]), + .O(com_tlm_u_tlm_tx_vc0_N_55980_i) + ); + defparam com_tlm_u_tlm_tx_vc0_buf_pool_rdata_sof_d_0_a2_0_a2.INIT = 4'h1; + LUT2 com_tlm_u_tlm_tx_vc0_buf_pool_rdata_sof_d_0_a2_0_a2 ( + .I0(com_tlm_u_tlm_tx_vc0_buf_pool_rdata_sof_d_hold_3281), + .I1(com_tlm_u_tlm_tx_vc0_buf_pool_start_xfer_q_3280), + .O(com_tlm_u_tlm_tx_vc0_buf_pool_rdata_sof_d_0_a2_0_a2_3301) + ); + defparam com_tlm_u_tlm_tx_vc0_buf_pool_en_q_i_i_a2_i_o2.INIT = 4'h8; + LUT2 com_tlm_u_tlm_tx_vc0_buf_pool_en_q_i_i_a2_i_o2 ( + .I0(com_lnk_tdst_rdy_n), + .I1(com_tlm_u_tlm_tx_vc0_src_rdy), + .O(com_tlm_u_tlm_tx_vc0_buf_pool_N_55898_i) + ); + defparam com_tlm_u_tlm_tx_vc0_buf_pool_errfwd_wen_0_sqmuxa_i_0_0.INIT = 8'hE0; + LUT3 com_tlm_u_tlm_tx_vc0_buf_pool_errfwd_wen_0_sqmuxa_i_0_0 ( + .I0(com_tlm_u_tlm_tx_vc0_trn_errfwd), + .I1(com_tlm_u_tlm_tx_vc0_trn_sof), + .I2(com_tlm_u_tlm_tx_vc0_trn_vld), + .O(com_tlm_u_tlm_tx_vc0_buf_pool_N_27043_i) + ); + defparam com_tlm_u_tlm_tx_vc0_buf_pool_un8_wen_i_0_0_1_.INIT = 8'hC8; + LUT3 com_tlm_u_tlm_tx_vc0_buf_pool_un8_wen_i_0_0_1_ ( + .I0(com_tlm_u_tlm_tx_vc0_buf_pool_wdata_65__3310), + .I1(com_tlm_u_tlm_tx_vc0_buf_pool_wdata_vld[1]), + .I2(com_tlm_u_tlm_tx_vc0_trn_vld), + .O(com_tlm_u_tlm_tx_vc0_buf_pool_N_27039_i) + ); + defparam com_tlm_u_tlm_tx_vc0_buf_pool_un8_wen_i_0_0_0_.INIT = 8'hC8; + LUT3 com_tlm_u_tlm_tx_vc0_buf_pool_un8_wen_i_0_0_0_ ( + .I0(com_tlm_u_tlm_tx_vc0_buf_pool_wdata_65__3310), + .I1(com_tlm_u_tlm_tx_vc0_buf_pool_wdata_vld[0]), + .I2(com_tlm_u_tlm_tx_vc0_trn_vld), + .O(com_tlm_u_tlm_tx_vc0_buf_pool_N_27037_i) + ); + defparam com_tlm_u_tlm_tx_vc0_buf_pool_un2_start_dst_rdy_o_i_0_0_0_o3_1.INIT = 8'h80; + LUT3 com_tlm_u_tlm_tx_vc0_buf_pool_un2_start_dst_rdy_o_i_0_0_0_o3_1 ( + .I0(com_tlm_u_tlm_tx_vc0_buf_pool_N_55898_i), + .I1(com_tlm_u_tlm_tx_vc0_buf_pool_rvld_any_3303), + .I2(com_tlm_u_tlm_tx_vc0_buf_pool_rvld_q_any_3302), + .O(com_tlm_u_tlm_tx_vc0_N_56167_i) + ); + defparam com_tlm_u_tlm_tx_vc0_buf_pool_wdata_vld_bit_0__N_59233_i.INIT = 8'hFB; + LUT3 com_tlm_u_tlm_tx_vc0_buf_pool_wdata_vld_bit_0__N_59233_i ( + .I0(com_tlm_u_tlm_tx_vc0_buf_pool_wdata_65__3310), + .I1(com_tlm_u_tlm_tx_vc0_buf_pool_wdata_vld_any_3282), + .I2(com_tlm_u_tlm_tx_vc0_trn_vld), + .O(com_tlm_u_tlm_tx_vc0_buf_pool_N_59233_i) + ); + defparam com_tlm_u_tlm_tx_vc0_buf_pool_N_86909_i.INIT = 8'h5D; + LUT3 com_tlm_u_tlm_tx_vc0_buf_pool_N_86909_i ( + .I0(com_tlm_u_tlm_tx_vc0_buf_pool_N_55898_i), + .I1(com_tlm_u_tlm_tx_vc0_buf_pool_rvld_any_3303), + .I2(com_tlm_u_tlm_tx_vc0_buf_pool_rvld_q_any_3302), + .O(com_tlm_u_tlm_tx_vc0_buf_pool_N_86909_i_3305) + ); + defparam com_tlm_u_tlm_tx_vc0_buf_pool_en_ram_i_i_i_0.INIT = 4'h4; + LUT2 com_tlm_u_tlm_tx_vc0_buf_pool_en_ram_i_i_i_0 ( + .I0(com_tlm_u_tlm_tx_vc0_N_56167_i), + .I1(com_tlm_u_tlm_tx_vc0_in_frame), + .O(com_tlm_u_tlm_tx_vc0_buf_pool_en_ram_i_i) + ); + defparam com_tlm_u_tlm_tx_vc0_buf_pool_en_retry_d_0_a2_0_a3_i_o2.INIT = 8'h54; + LUT3 com_tlm_u_tlm_tx_vc0_buf_pool_en_retry_d_0_a2_0_a3_i_o2 ( + .I0(com_tlm_u_tlm_tx_vc0_buf_pool_N_55898_i), + .I1(com_tlm_u_tlm_tx_vc0_buf_pool_N_55935_i), + .I2(com_tlm_u_tlm_tx_vc0_buf_pool_N_55992_i), + .O(com_tlm_u_tlm_tx_vc0_buf_pool_N_56080_i) + ); + defparam com_tlm_u_tlm_tx_vc0_buf_pool_waddr_l14_0_0_0.INIT = 16'hFCF8; + LUT4 com_tlm_u_tlm_tx_vc0_buf_pool_waddr_l14_0_0_0 ( + .I0(com_tlm_u_tlm_tx_vc0_buf_pool_wdata_65__3310), + .I1(com_tlm_u_tlm_tx_vc0_buf_pool_wdata_vld_any_3282), + .I2(com_tlm_u_tlm_tx_vc0_trn_sof), + .I3(com_tlm_u_tlm_tx_vc0_trn_vld), + .O(com_tlm_u_tlm_tx_vc0_buf_pool_N_10835_i) + ); + defparam com_tlm_u_tlm_tx_vc0_buf_pool_un2_start_dst_rdy_o_i_0_0_0.INIT = 8'hE0; + LUT3 com_tlm_u_tlm_tx_vc0_buf_pool_un2_start_dst_rdy_o_i_0_0_0 ( + .I0(com_tlm_u_tlm_tx_vc0_N_55914_i), + .I1(com_tlm_u_tlm_tx_vc0_N_55980_i), + .I2(com_tlm_u_tlm_tx_vc0_buf_pool_en_ram_i_i), + .O(com_tlm_u_tlm_tx_vc0_buf_pool_N_20353_i) + ); + defparam com_tlm_u_tlm_tx_vc0_buf_pool_in_frame17_i_i_a2_0_a2.INIT = 4'h8; + LUT2 com_tlm_u_tlm_tx_vc0_buf_pool_in_frame17_i_i_a2_0_a2 ( + .I0(com_tlm_u_tlm_tx_vc0_N_55858_i), + .I1(plm_link_up_1), + .O(com_tlm_u_tlm_tx_vc0_buf_pool_in_frame17_i_i_a2_0_a2_3283) + ); + defparam com_tlm_u_tlm_tx_vc0_buf_pool_raddr_h_0_0_3_.INIT = 8'hE4; + LUT3_L com_tlm_u_tlm_tx_vc0_buf_pool_raddr_h_0_0_3_ ( + .I0(com_tlm_u_tlm_tx_vc0_N_55858_i), + .I1(com_tlm_u_tlm_tx_vc0_buf_pool_raddr_h[3]), + .I2(com_tlm_u_tlm_tx_vc0_start_buf_num[3]), + .LO(com_tlm_u_tlm_tx_vc0_buf_pool_raddr_h_0_0[3]) + ); + defparam com_tlm_u_tlm_tx_vc0_buf_pool_raddr_h_0_0_2_.INIT = 8'hE4; + LUT3_L com_tlm_u_tlm_tx_vc0_buf_pool_raddr_h_0_0_2_ ( + .I0(com_tlm_u_tlm_tx_vc0_N_55858_i), + .I1(com_tlm_u_tlm_tx_vc0_buf_pool_raddr_h[2]), + .I2(com_tlm_u_tlm_tx_vc0_start_buf_num[2]), + .LO(com_tlm_u_tlm_tx_vc0_buf_pool_raddr_h_0_0[2]) + ); + defparam com_tlm_u_tlm_tx_vc0_buf_pool_raddr_h_0_0_1_.INIT = 8'hE4; + LUT3_L com_tlm_u_tlm_tx_vc0_buf_pool_raddr_h_0_0_1_ ( + .I0(com_tlm_u_tlm_tx_vc0_N_55858_i), + .I1(com_tlm_u_tlm_tx_vc0_buf_pool_raddr_h[1]), + .I2(com_tlm_u_tlm_tx_vc0_start_buf_num[1]), + .LO(com_tlm_u_tlm_tx_vc0_buf_pool_raddr_h_0_0[1]) + ); + defparam com_tlm_u_tlm_tx_vc0_buf_pool_raddr_h_0_0_0_.INIT = 8'hE4; + LUT3_L com_tlm_u_tlm_tx_vc0_buf_pool_raddr_h_0_0_0_ ( + .I0(com_tlm_u_tlm_tx_vc0_N_55858_i), + .I1(com_tlm_u_tlm_tx_vc0_buf_pool_raddr_h[0]), + .I2(com_tlm_u_tlm_tx_vc0_start_buf_num[0]), + .LO(com_tlm_u_tlm_tx_vc0_buf_pool_raddr_h_0_0[0]) + ); + defparam com_tlm_u_tlm_tx_vc0_buf_pool_waddr_l_1_axb_6.INIT = 4'hE; + LUT2_L com_tlm_u_tlm_tx_vc0_buf_pool_waddr_l_1_axb_6 ( + .I0(com_tlm_u_tlm_tx_vc0_buf_pool_waddr_l[6]), + .I1(com_tlm_u_tlm_tx_vc0_trn_sof), + .LO(com_tlm_u_tlm_tx_vc0_buf_pool_waddr_l_1_axb_6_3284) + ); + defparam com_tlm_u_tlm_tx_vc0_buf_pool_waddr_l_1_axb_5.INIT = 4'hE; + LUT2_L com_tlm_u_tlm_tx_vc0_buf_pool_waddr_l_1_axb_5 ( + .I0(com_tlm_u_tlm_tx_vc0_buf_pool_waddr_l[5]), + .I1(com_tlm_u_tlm_tx_vc0_trn_sof), + .LO(com_tlm_u_tlm_tx_vc0_buf_pool_waddr_l_1_axb_5_3285) + ); + defparam com_tlm_u_tlm_tx_vc0_buf_pool_waddr_l_1_axb_4.INIT = 4'hE; + LUT2_L com_tlm_u_tlm_tx_vc0_buf_pool_waddr_l_1_axb_4 ( + .I0(com_tlm_u_tlm_tx_vc0_buf_pool_waddr_l[4]), + .I1(com_tlm_u_tlm_tx_vc0_trn_sof), + .LO(com_tlm_u_tlm_tx_vc0_buf_pool_waddr_l_1_axb_4_3286) + ); + defparam com_tlm_u_tlm_tx_vc0_buf_pool_waddr_l_1_axb_3.INIT = 4'hE; + LUT2_L com_tlm_u_tlm_tx_vc0_buf_pool_waddr_l_1_axb_3 ( + .I0(com_tlm_u_tlm_tx_vc0_buf_pool_waddr_l[3]), + .I1(com_tlm_u_tlm_tx_vc0_trn_sof), + .LO(com_tlm_u_tlm_tx_vc0_buf_pool_waddr_l_1_axb_3_3287) + ); + defparam com_tlm_u_tlm_tx_vc0_buf_pool_waddr_l_1_axb_2.INIT = 4'hE; + LUT2_L com_tlm_u_tlm_tx_vc0_buf_pool_waddr_l_1_axb_2 ( + .I0(com_tlm_u_tlm_tx_vc0_buf_pool_waddr_l[2]), + .I1(com_tlm_u_tlm_tx_vc0_trn_sof), + .LO(com_tlm_u_tlm_tx_vc0_buf_pool_waddr_l_1_axb_2_3288) + ); + defparam com_tlm_u_tlm_tx_vc0_buf_pool_waddr_l_1_axb_1.INIT = 4'hE; + LUT2_L com_tlm_u_tlm_tx_vc0_buf_pool_waddr_l_1_axb_1 ( + .I0(com_tlm_u_tlm_tx_vc0_buf_pool_waddr_l[1]), + .I1(com_tlm_u_tlm_tx_vc0_trn_sof), + .LO(com_tlm_u_tlm_tx_vc0_buf_pool_waddr_l_1_axb_1_3289) + ); + defparam com_tlm_u_tlm_tx_vc0_buf_pool_rdata_q_all_5_0_a2_0_a2_0_a2_68_.INIT = 4'h8; + LUT2_L com_tlm_u_tlm_tx_vc0_buf_pool_rdata_q_all_5_0_a2_0_a2_0_a2_68_ ( + .I0(com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all_68_), + .I1(com_tlm_u_tlm_tx_vc0_buf_pool_rvld[0]), + .LO(com_tlm_u_tlm_tx_vc0_buf_pool_rdata_q_all_5_68_) + ); + defparam com_tlm_u_tlm_tx_vc0_buf_pool_rdata_q_all_5_0_a2_0_a2_0_a2_66_.INIT = 4'h8; + LUT2_L com_tlm_u_tlm_tx_vc0_buf_pool_rdata_q_all_5_0_a2_0_a2_0_a2_66_ ( + .I0(com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all_66_), + .I1(com_tlm_u_tlm_tx_vc0_buf_pool_rvld[0]), + .LO(com_tlm_u_tlm_tx_vc0_buf_pool_rdata_q_all_5_66_) + ); + defparam com_tlm_u_tlm_tx_vc0_buf_pool_rdata_q_all_5_0_a2_0_a2_0_a2_65_.INIT = 4'h8; + LUT2_L com_tlm_u_tlm_tx_vc0_buf_pool_rdata_q_all_5_0_a2_0_a2_0_a2_65_ ( + .I0(com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all_65_), + .I1(com_tlm_u_tlm_tx_vc0_buf_pool_rvld[0]), + .LO(com_tlm_u_tlm_tx_vc0_buf_pool_rdata_q_all_5_65_) + ); + defparam com_tlm_u_tlm_tx_vc0_buf_pool_rdata_q_all_5_0_a2_0_a2_0_a2_64_.INIT = 4'h8; + LUT2_L com_tlm_u_tlm_tx_vc0_buf_pool_rdata_q_all_5_0_a2_0_a2_0_a2_64_ ( + .I0(com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all_64_), + .I1(com_tlm_u_tlm_tx_vc0_buf_pool_rvld[0]), + .LO(com_tlm_u_tlm_tx_vc0_buf_pool_rdata_q_all_5_64_) + ); + defparam com_tlm_u_tlm_tx_vc0_buf_pool_rdata_q_all_18_0_a2_0_a2_0_a2_140_.INIT = 4'h8; + LUT2_L com_tlm_u_tlm_tx_vc0_buf_pool_rdata_q_all_18_0_a2_0_a2_0_a2_140_ ( + .I0(com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all_140_), + .I1(com_tlm_u_tlm_tx_vc0_buf_pool_rvld[1]), + .LO(com_tlm_u_tlm_tx_vc0_buf_pool_rdata_q_all_18_140_) + ); + defparam com_tlm_u_tlm_tx_vc0_buf_pool_rdata_q_all_18_0_a2_0_a2_0_a2_138_.INIT = 4'h8; + LUT2_L com_tlm_u_tlm_tx_vc0_buf_pool_rdata_q_all_18_0_a2_0_a2_0_a2_138_ ( + .I0(com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all_138_), + .I1(com_tlm_u_tlm_tx_vc0_buf_pool_rvld[1]), + .LO(com_tlm_u_tlm_tx_vc0_buf_pool_rdata_q_all_18_138_) + ); + defparam com_tlm_u_tlm_tx_vc0_buf_pool_rdata_q_all_18_0_a2_0_a2_0_a2_137_.INIT = 4'h8; + LUT2_L com_tlm_u_tlm_tx_vc0_buf_pool_rdata_q_all_18_0_a2_0_a2_0_a2_137_ ( + .I0(com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all_137_), + .I1(com_tlm_u_tlm_tx_vc0_buf_pool_rvld[1]), + .LO(com_tlm_u_tlm_tx_vc0_buf_pool_rdata_q_all_18_137_) + ); + defparam com_tlm_u_tlm_tx_vc0_buf_pool_rdata_q_all_18_0_a2_0_a2_0_a2_136_.INIT = 4'h8; + LUT2_L com_tlm_u_tlm_tx_vc0_buf_pool_rdata_q_all_18_0_a2_0_a2_0_a2_136_ ( + .I0(com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all_136_), + .I1(com_tlm_u_tlm_tx_vc0_buf_pool_rvld[1]), + .LO(com_tlm_u_tlm_tx_vc0_buf_pool_rdata_q_all_18_136_) + ); + defparam com_tlm_u_tlm_tx_vc0_buf_pool_N_59099_i.INIT = 16'hECA0; + LUT4_L com_tlm_u_tlm_tx_vc0_buf_pool_N_59099_i ( + .I0(com_tlm_u_tlm_tx_vc0_buf_pool_rdata_q_all_65__3292), + .I1(com_tlm_u_tlm_tx_vc0_buf_pool_rdata_q_all_137__3291), + .I2(com_tlm_u_tlm_tx_vc0_buf_pool_rvld_q[0]), + .I3(com_tlm_u_tlm_tx_vc0_buf_pool_rvld_q[1]), + .LO(com_tlm_u_tlm_tx_vc0_buf_pool_N_59099_i_3290) + ); + defparam com_tlm_u_tlm_tx_vc0_buf_pool_N_59264_i.INIT = 16'hECA0; + LUT4_L com_tlm_u_tlm_tx_vc0_buf_pool_N_59264_i ( + .I0(com_tlm_u_tlm_tx_vc0_buf_pool_rdata_q_all_64__3294), + .I1(com_tlm_u_tlm_tx_vc0_buf_pool_rdata_q_all_136__3293), + .I2(com_tlm_u_tlm_tx_vc0_buf_pool_rvld_q[0]), + .I3(com_tlm_u_tlm_tx_vc0_buf_pool_rvld_q[1]), + .LO(com_tlm_u_tlm_tx_vc0_buf_pool_N_59264_i_3307) + ); + defparam com_tlm_u_tlm_tx_vc0_buf_pool_wdata_vld_bit_0__wdata_vld_3_i_0_0_0_.INIT = 16'h3500; + LUT4_L com_tlm_u_tlm_tx_vc0_buf_pool_wdata_vld_bit_0__wdata_vld_3_i_0_0_0_ ( + .I0(com_tlm_u_tlm_tx_vc0_buf_pool_waddr_h[3]), + .I1(com_tlm_u_tlm_tx_vc0_tkn_buf_num[3]), + .I2(com_tlm_u_tlm_tx_vc0_trn_sof), + .I3(com_tlm_u_tlm_tx_vc0_trn_vld), + .LO(com_tlm_u_tlm_tx_vc0_buf_pool_N_27045_i) + ); + defparam com_tlm_u_tlm_tx_vc0_buf_pool_wdata_vld_bit_1__wdata_vld_10_i_0_0_1_.INIT = 16'hCA00; + LUT4_L com_tlm_u_tlm_tx_vc0_buf_pool_wdata_vld_bit_1__wdata_vld_10_i_0_0_1_ ( + .I0(com_tlm_u_tlm_tx_vc0_buf_pool_waddr_h[3]), + .I1(com_tlm_u_tlm_tx_vc0_tkn_buf_num[3]), + .I2(com_tlm_u_tlm_tx_vc0_trn_sof), + .I3(com_tlm_u_tlm_tx_vc0_trn_vld), + .LO(com_tlm_u_tlm_tx_vc0_buf_pool_N_27041_i) + ); + defparam com_tlm_u_tlm_tx_vc0_buf_pool_rdata_q_i_0_i_a2_68_.INIT = 16'h135F; + LUT4_L com_tlm_u_tlm_tx_vc0_buf_pool_rdata_q_i_0_i_a2_68_ ( + .I0(com_tlm_u_tlm_tx_vc0_buf_pool_rdata_q_all_68__3296), + .I1(com_tlm_u_tlm_tx_vc0_buf_pool_rdata_q_all_140__3295), + .I2(com_tlm_u_tlm_tx_vc0_buf_pool_rvld_q[0]), + .I3(com_tlm_u_tlm_tx_vc0_buf_pool_rvld_q[1]), + .LO(com_tlm_u_tlm_tx_vc0_buf_pool_rdata_q_i_0_i_a2[68]) + ); + defparam com_tlm_u_tlm_tx_vc0_buf_pool_N_59265_i.INIT = 16'hECA0; + LUT4_L com_tlm_u_tlm_tx_vc0_buf_pool_N_59265_i ( + .I0(com_tlm_u_tlm_tx_vc0_buf_pool_rdata_q_all_63_), + .I1(com_tlm_u_tlm_tx_vc0_buf_pool_rdata_q_all_135_), + .I2(com_tlm_u_tlm_tx_vc0_buf_pool_rvld_q[0]), + .I3(com_tlm_u_tlm_tx_vc0_buf_pool_rvld_q[1]), + .LO(com_tlm_u_tlm_tx_vc0_buf_pool_N_59265_i_3376) + ); + defparam com_tlm_u_tlm_tx_vc0_buf_pool_N_59266_i.INIT = 16'hECA0; + LUT4_L com_tlm_u_tlm_tx_vc0_buf_pool_N_59266_i ( + .I0(com_tlm_u_tlm_tx_vc0_buf_pool_rdata_q_all_62_), + .I1(com_tlm_u_tlm_tx_vc0_buf_pool_rdata_q_all_134_), + .I2(com_tlm_u_tlm_tx_vc0_buf_pool_rvld_q[0]), + .I3(com_tlm_u_tlm_tx_vc0_buf_pool_rvld_q[1]), + .LO(com_tlm_u_tlm_tx_vc0_buf_pool_N_59266_i_3377) + ); + defparam com_tlm_u_tlm_tx_vc0_buf_pool_N_59267_i.INIT = 16'hECA0; + LUT4_L com_tlm_u_tlm_tx_vc0_buf_pool_N_59267_i ( + .I0(com_tlm_u_tlm_tx_vc0_buf_pool_rdata_q_all_61_), + .I1(com_tlm_u_tlm_tx_vc0_buf_pool_rdata_q_all_133_), + .I2(com_tlm_u_tlm_tx_vc0_buf_pool_rvld_q[0]), + .I3(com_tlm_u_tlm_tx_vc0_buf_pool_rvld_q[1]), + .LO(com_tlm_u_tlm_tx_vc0_buf_pool_N_59267_i_3378) + ); + defparam com_tlm_u_tlm_tx_vc0_buf_pool_N_59268_i.INIT = 16'hECA0; + LUT4_L com_tlm_u_tlm_tx_vc0_buf_pool_N_59268_i ( + .I0(com_tlm_u_tlm_tx_vc0_buf_pool_rdata_q_all_60_), + .I1(com_tlm_u_tlm_tx_vc0_buf_pool_rdata_q_all_132_), + .I2(com_tlm_u_tlm_tx_vc0_buf_pool_rvld_q[0]), + .I3(com_tlm_u_tlm_tx_vc0_buf_pool_rvld_q[1]), + .LO(com_tlm_u_tlm_tx_vc0_buf_pool_N_59268_i_3379) + ); + defparam com_tlm_u_tlm_tx_vc0_buf_pool_N_59269_i.INIT = 16'hECA0; + LUT4_L com_tlm_u_tlm_tx_vc0_buf_pool_N_59269_i ( + .I0(com_tlm_u_tlm_tx_vc0_buf_pool_rdata_q_all_59_), + .I1(com_tlm_u_tlm_tx_vc0_buf_pool_rdata_q_all_131_), + .I2(com_tlm_u_tlm_tx_vc0_buf_pool_rvld_q[0]), + .I3(com_tlm_u_tlm_tx_vc0_buf_pool_rvld_q[1]), + .LO(com_tlm_u_tlm_tx_vc0_buf_pool_N_59269_i_3380) + ); + defparam com_tlm_u_tlm_tx_vc0_buf_pool_N_59270_i.INIT = 16'hECA0; + LUT4_L com_tlm_u_tlm_tx_vc0_buf_pool_N_59270_i ( + .I0(com_tlm_u_tlm_tx_vc0_buf_pool_rdata_q_all_58_), + .I1(com_tlm_u_tlm_tx_vc0_buf_pool_rdata_q_all_130_), + .I2(com_tlm_u_tlm_tx_vc0_buf_pool_rvld_q[0]), + .I3(com_tlm_u_tlm_tx_vc0_buf_pool_rvld_q[1]), + .LO(com_tlm_u_tlm_tx_vc0_buf_pool_N_59270_i_3381) + ); + defparam com_tlm_u_tlm_tx_vc0_buf_pool_N_59271_i.INIT = 16'hECA0; + LUT4_L com_tlm_u_tlm_tx_vc0_buf_pool_N_59271_i ( + .I0(com_tlm_u_tlm_tx_vc0_buf_pool_rdata_q_all_57_), + .I1(com_tlm_u_tlm_tx_vc0_buf_pool_rdata_q_all_129_), + .I2(com_tlm_u_tlm_tx_vc0_buf_pool_rvld_q[0]), + .I3(com_tlm_u_tlm_tx_vc0_buf_pool_rvld_q[1]), + .LO(com_tlm_u_tlm_tx_vc0_buf_pool_N_59271_i_3382) + ); + defparam com_tlm_u_tlm_tx_vc0_buf_pool_N_59272_i.INIT = 16'hECA0; + LUT4_L com_tlm_u_tlm_tx_vc0_buf_pool_N_59272_i ( + .I0(com_tlm_u_tlm_tx_vc0_buf_pool_rdata_q_all_56_), + .I1(com_tlm_u_tlm_tx_vc0_buf_pool_rdata_q_all_128_), + .I2(com_tlm_u_tlm_tx_vc0_buf_pool_rvld_q[0]), + .I3(com_tlm_u_tlm_tx_vc0_buf_pool_rvld_q[1]), + .LO(com_tlm_u_tlm_tx_vc0_buf_pool_N_59272_i_3383) + ); + defparam com_tlm_u_tlm_tx_vc0_buf_pool_N_59273_i.INIT = 16'hECA0; + LUT4_L com_tlm_u_tlm_tx_vc0_buf_pool_N_59273_i ( + .I0(com_tlm_u_tlm_tx_vc0_buf_pool_rdata_q_all_55_), + .I1(com_tlm_u_tlm_tx_vc0_buf_pool_rdata_q_all_127_), + .I2(com_tlm_u_tlm_tx_vc0_buf_pool_rvld_q[0]), + .I3(com_tlm_u_tlm_tx_vc0_buf_pool_rvld_q[1]), + .LO(com_tlm_u_tlm_tx_vc0_buf_pool_N_59273_i_3384) + ); + defparam com_tlm_u_tlm_tx_vc0_buf_pool_N_59274_i.INIT = 16'hECA0; + LUT4_L com_tlm_u_tlm_tx_vc0_buf_pool_N_59274_i ( + .I0(com_tlm_u_tlm_tx_vc0_buf_pool_rdata_q_all_54_), + .I1(com_tlm_u_tlm_tx_vc0_buf_pool_rdata_q_all_126_), + .I2(com_tlm_u_tlm_tx_vc0_buf_pool_rvld_q[0]), + .I3(com_tlm_u_tlm_tx_vc0_buf_pool_rvld_q[1]), + .LO(com_tlm_u_tlm_tx_vc0_buf_pool_N_59274_i_3385) + ); + defparam com_tlm_u_tlm_tx_vc0_buf_pool_N_59275_i.INIT = 16'hECA0; + LUT4_L com_tlm_u_tlm_tx_vc0_buf_pool_N_59275_i ( + .I0(com_tlm_u_tlm_tx_vc0_buf_pool_rdata_q_all_53_), + .I1(com_tlm_u_tlm_tx_vc0_buf_pool_rdata_q_all_125_), + .I2(com_tlm_u_tlm_tx_vc0_buf_pool_rvld_q[0]), + .I3(com_tlm_u_tlm_tx_vc0_buf_pool_rvld_q[1]), + .LO(com_tlm_u_tlm_tx_vc0_buf_pool_N_59275_i_3386) + ); + defparam com_tlm_u_tlm_tx_vc0_buf_pool_N_59276_i.INIT = 16'hECA0; + LUT4_L com_tlm_u_tlm_tx_vc0_buf_pool_N_59276_i ( + .I0(com_tlm_u_tlm_tx_vc0_buf_pool_rdata_q_all_52_), + .I1(com_tlm_u_tlm_tx_vc0_buf_pool_rdata_q_all_124_), + .I2(com_tlm_u_tlm_tx_vc0_buf_pool_rvld_q[0]), + .I3(com_tlm_u_tlm_tx_vc0_buf_pool_rvld_q[1]), + .LO(com_tlm_u_tlm_tx_vc0_buf_pool_N_59276_i_3387) + ); + defparam com_tlm_u_tlm_tx_vc0_buf_pool_N_59277_i.INIT = 16'hECA0; + LUT4_L com_tlm_u_tlm_tx_vc0_buf_pool_N_59277_i ( + .I0(com_tlm_u_tlm_tx_vc0_buf_pool_rdata_q_all_51_), + .I1(com_tlm_u_tlm_tx_vc0_buf_pool_rdata_q_all_123_), + .I2(com_tlm_u_tlm_tx_vc0_buf_pool_rvld_q[0]), + .I3(com_tlm_u_tlm_tx_vc0_buf_pool_rvld_q[1]), + .LO(com_tlm_u_tlm_tx_vc0_buf_pool_N_59277_i_3388) + ); + defparam com_tlm_u_tlm_tx_vc0_buf_pool_N_59278_i.INIT = 16'hECA0; + LUT4_L com_tlm_u_tlm_tx_vc0_buf_pool_N_59278_i ( + .I0(com_tlm_u_tlm_tx_vc0_buf_pool_rdata_q_all_50_), + .I1(com_tlm_u_tlm_tx_vc0_buf_pool_rdata_q_all_122_), + .I2(com_tlm_u_tlm_tx_vc0_buf_pool_rvld_q[0]), + .I3(com_tlm_u_tlm_tx_vc0_buf_pool_rvld_q[1]), + .LO(com_tlm_u_tlm_tx_vc0_buf_pool_N_59278_i_3389) + ); + defparam com_tlm_u_tlm_tx_vc0_buf_pool_N_59279_i.INIT = 16'hECA0; + LUT4_L com_tlm_u_tlm_tx_vc0_buf_pool_N_59279_i ( + .I0(com_tlm_u_tlm_tx_vc0_buf_pool_rdata_q_all_49_), + .I1(com_tlm_u_tlm_tx_vc0_buf_pool_rdata_q_all_121_), + .I2(com_tlm_u_tlm_tx_vc0_buf_pool_rvld_q[0]), + .I3(com_tlm_u_tlm_tx_vc0_buf_pool_rvld_q[1]), + .LO(com_tlm_u_tlm_tx_vc0_buf_pool_N_59279_i_3390) + ); + defparam com_tlm_u_tlm_tx_vc0_buf_pool_N_59280_i.INIT = 16'hECA0; + LUT4_L com_tlm_u_tlm_tx_vc0_buf_pool_N_59280_i ( + .I0(com_tlm_u_tlm_tx_vc0_buf_pool_rdata_q_all_48_), + .I1(com_tlm_u_tlm_tx_vc0_buf_pool_rdata_q_all_120_), + .I2(com_tlm_u_tlm_tx_vc0_buf_pool_rvld_q[0]), + .I3(com_tlm_u_tlm_tx_vc0_buf_pool_rvld_q[1]), + .LO(com_tlm_u_tlm_tx_vc0_buf_pool_N_59280_i_3391) + ); + defparam com_tlm_u_tlm_tx_vc0_buf_pool_N_59281_i.INIT = 16'hECA0; + LUT4_L com_tlm_u_tlm_tx_vc0_buf_pool_N_59281_i ( + .I0(com_tlm_u_tlm_tx_vc0_buf_pool_rdata_q_all_47_), + .I1(com_tlm_u_tlm_tx_vc0_buf_pool_rdata_q_all_119_), + .I2(com_tlm_u_tlm_tx_vc0_buf_pool_rvld_q[0]), + .I3(com_tlm_u_tlm_tx_vc0_buf_pool_rvld_q[1]), + .LO(com_tlm_u_tlm_tx_vc0_buf_pool_N_59281_i_3392) + ); + defparam com_tlm_u_tlm_tx_vc0_buf_pool_N_59282_i.INIT = 16'hECA0; + LUT4_L com_tlm_u_tlm_tx_vc0_buf_pool_N_59282_i ( + .I0(com_tlm_u_tlm_tx_vc0_buf_pool_rdata_q_all_46_), + .I1(com_tlm_u_tlm_tx_vc0_buf_pool_rdata_q_all_118_), + .I2(com_tlm_u_tlm_tx_vc0_buf_pool_rvld_q[0]), + .I3(com_tlm_u_tlm_tx_vc0_buf_pool_rvld_q[1]), + .LO(com_tlm_u_tlm_tx_vc0_buf_pool_N_59282_i_3393) + ); + defparam com_tlm_u_tlm_tx_vc0_buf_pool_N_59283_i.INIT = 16'hECA0; + LUT4_L com_tlm_u_tlm_tx_vc0_buf_pool_N_59283_i ( + .I0(com_tlm_u_tlm_tx_vc0_buf_pool_rdata_q_all_45_), + .I1(com_tlm_u_tlm_tx_vc0_buf_pool_rdata_q_all_117_), + .I2(com_tlm_u_tlm_tx_vc0_buf_pool_rvld_q[0]), + .I3(com_tlm_u_tlm_tx_vc0_buf_pool_rvld_q[1]), + .LO(com_tlm_u_tlm_tx_vc0_buf_pool_N_59283_i_3394) + ); + defparam com_tlm_u_tlm_tx_vc0_buf_pool_N_59284_i.INIT = 16'hECA0; + LUT4_L com_tlm_u_tlm_tx_vc0_buf_pool_N_59284_i ( + .I0(com_tlm_u_tlm_tx_vc0_buf_pool_rdata_q_all_44_), + .I1(com_tlm_u_tlm_tx_vc0_buf_pool_rdata_q_all_116_), + .I2(com_tlm_u_tlm_tx_vc0_buf_pool_rvld_q[0]), + .I3(com_tlm_u_tlm_tx_vc0_buf_pool_rvld_q[1]), + .LO(com_tlm_u_tlm_tx_vc0_buf_pool_N_59284_i_3395) + ); + defparam com_tlm_u_tlm_tx_vc0_buf_pool_N_59285_i.INIT = 16'hECA0; + LUT4_L com_tlm_u_tlm_tx_vc0_buf_pool_N_59285_i ( + .I0(com_tlm_u_tlm_tx_vc0_buf_pool_rdata_q_all_43_), + .I1(com_tlm_u_tlm_tx_vc0_buf_pool_rdata_q_all_115_), + .I2(com_tlm_u_tlm_tx_vc0_buf_pool_rvld_q[0]), + .I3(com_tlm_u_tlm_tx_vc0_buf_pool_rvld_q[1]), + .LO(com_tlm_u_tlm_tx_vc0_buf_pool_N_59285_i_3396) + ); + defparam com_tlm_u_tlm_tx_vc0_buf_pool_N_59286_i.INIT = 16'hECA0; + LUT4_L com_tlm_u_tlm_tx_vc0_buf_pool_N_59286_i ( + .I0(com_tlm_u_tlm_tx_vc0_buf_pool_rdata_q_all_42_), + .I1(com_tlm_u_tlm_tx_vc0_buf_pool_rdata_q_all_114_), + .I2(com_tlm_u_tlm_tx_vc0_buf_pool_rvld_q[0]), + .I3(com_tlm_u_tlm_tx_vc0_buf_pool_rvld_q[1]), + .LO(com_tlm_u_tlm_tx_vc0_buf_pool_N_59286_i_3397) + ); + defparam com_tlm_u_tlm_tx_vc0_buf_pool_N_59287_i.INIT = 16'hECA0; + LUT4_L com_tlm_u_tlm_tx_vc0_buf_pool_N_59287_i ( + .I0(com_tlm_u_tlm_tx_vc0_buf_pool_rdata_q_all_41_), + .I1(com_tlm_u_tlm_tx_vc0_buf_pool_rdata_q_all_113_), + .I2(com_tlm_u_tlm_tx_vc0_buf_pool_rvld_q[0]), + .I3(com_tlm_u_tlm_tx_vc0_buf_pool_rvld_q[1]), + .LO(com_tlm_u_tlm_tx_vc0_buf_pool_N_59287_i_3398) + ); + defparam com_tlm_u_tlm_tx_vc0_buf_pool_N_59288_i.INIT = 16'hECA0; + LUT4_L com_tlm_u_tlm_tx_vc0_buf_pool_N_59288_i ( + .I0(com_tlm_u_tlm_tx_vc0_buf_pool_rdata_q_all_40_), + .I1(com_tlm_u_tlm_tx_vc0_buf_pool_rdata_q_all_112_), + .I2(com_tlm_u_tlm_tx_vc0_buf_pool_rvld_q[0]), + .I3(com_tlm_u_tlm_tx_vc0_buf_pool_rvld_q[1]), + .LO(com_tlm_u_tlm_tx_vc0_buf_pool_N_59288_i_3399) + ); + defparam com_tlm_u_tlm_tx_vc0_buf_pool_N_59289_i.INIT = 16'hECA0; + LUT4_L com_tlm_u_tlm_tx_vc0_buf_pool_N_59289_i ( + .I0(com_tlm_u_tlm_tx_vc0_buf_pool_rdata_q_all_39_), + .I1(com_tlm_u_tlm_tx_vc0_buf_pool_rdata_q_all_111_), + .I2(com_tlm_u_tlm_tx_vc0_buf_pool_rvld_q[0]), + .I3(com_tlm_u_tlm_tx_vc0_buf_pool_rvld_q[1]), + .LO(com_tlm_u_tlm_tx_vc0_buf_pool_N_59289_i_3400) + ); + defparam com_tlm_u_tlm_tx_vc0_buf_pool_N_59290_i.INIT = 16'hECA0; + LUT4_L com_tlm_u_tlm_tx_vc0_buf_pool_N_59290_i ( + .I0(com_tlm_u_tlm_tx_vc0_buf_pool_rdata_q_all_38_), + .I1(com_tlm_u_tlm_tx_vc0_buf_pool_rdata_q_all_110_), + .I2(com_tlm_u_tlm_tx_vc0_buf_pool_rvld_q[0]), + .I3(com_tlm_u_tlm_tx_vc0_buf_pool_rvld_q[1]), + .LO(com_tlm_u_tlm_tx_vc0_buf_pool_N_59290_i_3401) + ); + defparam com_tlm_u_tlm_tx_vc0_buf_pool_N_59291_i.INIT = 16'hECA0; + LUT4_L com_tlm_u_tlm_tx_vc0_buf_pool_N_59291_i ( + .I0(com_tlm_u_tlm_tx_vc0_buf_pool_rdata_q_all_37_), + .I1(com_tlm_u_tlm_tx_vc0_buf_pool_rdata_q_all_109_), + .I2(com_tlm_u_tlm_tx_vc0_buf_pool_rvld_q[0]), + .I3(com_tlm_u_tlm_tx_vc0_buf_pool_rvld_q[1]), + .LO(com_tlm_u_tlm_tx_vc0_buf_pool_N_59291_i_3402) + ); + defparam com_tlm_u_tlm_tx_vc0_buf_pool_N_59292_i.INIT = 16'hECA0; + LUT4_L com_tlm_u_tlm_tx_vc0_buf_pool_N_59292_i ( + .I0(com_tlm_u_tlm_tx_vc0_buf_pool_rdata_q_all_36_), + .I1(com_tlm_u_tlm_tx_vc0_buf_pool_rdata_q_all_108_), + .I2(com_tlm_u_tlm_tx_vc0_buf_pool_rvld_q[0]), + .I3(com_tlm_u_tlm_tx_vc0_buf_pool_rvld_q[1]), + .LO(com_tlm_u_tlm_tx_vc0_buf_pool_N_59292_i_3403) + ); + defparam com_tlm_u_tlm_tx_vc0_buf_pool_N_59293_i.INIT = 16'hECA0; + LUT4_L com_tlm_u_tlm_tx_vc0_buf_pool_N_59293_i ( + .I0(com_tlm_u_tlm_tx_vc0_buf_pool_rdata_q_all_35_), + .I1(com_tlm_u_tlm_tx_vc0_buf_pool_rdata_q_all_107_), + .I2(com_tlm_u_tlm_tx_vc0_buf_pool_rvld_q[0]), + .I3(com_tlm_u_tlm_tx_vc0_buf_pool_rvld_q[1]), + .LO(com_tlm_u_tlm_tx_vc0_buf_pool_N_59293_i_3404) + ); + defparam com_tlm_u_tlm_tx_vc0_buf_pool_N_59294_i.INIT = 16'hECA0; + LUT4_L com_tlm_u_tlm_tx_vc0_buf_pool_N_59294_i ( + .I0(com_tlm_u_tlm_tx_vc0_buf_pool_rdata_q_all_34_), + .I1(com_tlm_u_tlm_tx_vc0_buf_pool_rdata_q_all_106_), + .I2(com_tlm_u_tlm_tx_vc0_buf_pool_rvld_q[0]), + .I3(com_tlm_u_tlm_tx_vc0_buf_pool_rvld_q[1]), + .LO(com_tlm_u_tlm_tx_vc0_buf_pool_N_59294_i_3405) + ); + defparam com_tlm_u_tlm_tx_vc0_buf_pool_N_59295_i.INIT = 16'hECA0; + LUT4_L com_tlm_u_tlm_tx_vc0_buf_pool_N_59295_i ( + .I0(com_tlm_u_tlm_tx_vc0_buf_pool_rdata_q_all_33_), + .I1(com_tlm_u_tlm_tx_vc0_buf_pool_rdata_q_all_105_), + .I2(com_tlm_u_tlm_tx_vc0_buf_pool_rvld_q[0]), + .I3(com_tlm_u_tlm_tx_vc0_buf_pool_rvld_q[1]), + .LO(com_tlm_u_tlm_tx_vc0_buf_pool_N_59295_i_3406) + ); + defparam com_tlm_u_tlm_tx_vc0_buf_pool_N_59296_i.INIT = 16'hECA0; + LUT4_L com_tlm_u_tlm_tx_vc0_buf_pool_N_59296_i ( + .I0(com_tlm_u_tlm_tx_vc0_buf_pool_rdata_q_all_32_), + .I1(com_tlm_u_tlm_tx_vc0_buf_pool_rdata_q_all_104_), + .I2(com_tlm_u_tlm_tx_vc0_buf_pool_rvld_q[0]), + .I3(com_tlm_u_tlm_tx_vc0_buf_pool_rvld_q[1]), + .LO(com_tlm_u_tlm_tx_vc0_buf_pool_N_59296_i_3407) + ); + defparam com_tlm_u_tlm_tx_vc0_buf_pool_N_59297_i.INIT = 16'hECA0; + LUT4_L com_tlm_u_tlm_tx_vc0_buf_pool_N_59297_i ( + .I0(com_tlm_u_tlm_tx_vc0_buf_pool_rdata_q_all_31_), + .I1(com_tlm_u_tlm_tx_vc0_buf_pool_rdata_q_all_103_), + .I2(com_tlm_u_tlm_tx_vc0_buf_pool_rvld_q[0]), + .I3(com_tlm_u_tlm_tx_vc0_buf_pool_rvld_q[1]), + .LO(com_tlm_u_tlm_tx_vc0_buf_pool_N_59297_i_3408) + ); + defparam com_tlm_u_tlm_tx_vc0_buf_pool_N_59298_i.INIT = 16'hECA0; + LUT4_L com_tlm_u_tlm_tx_vc0_buf_pool_N_59298_i ( + .I0(com_tlm_u_tlm_tx_vc0_buf_pool_rdata_q_all_30_), + .I1(com_tlm_u_tlm_tx_vc0_buf_pool_rdata_q_all_102_), + .I2(com_tlm_u_tlm_tx_vc0_buf_pool_rvld_q[0]), + .I3(com_tlm_u_tlm_tx_vc0_buf_pool_rvld_q[1]), + .LO(com_tlm_u_tlm_tx_vc0_buf_pool_N_59298_i_3409) + ); + defparam com_tlm_u_tlm_tx_vc0_buf_pool_N_59299_i.INIT = 16'hECA0; + LUT4_L com_tlm_u_tlm_tx_vc0_buf_pool_N_59299_i ( + .I0(com_tlm_u_tlm_tx_vc0_buf_pool_rdata_q_all_29_), + .I1(com_tlm_u_tlm_tx_vc0_buf_pool_rdata_q_all_101_), + .I2(com_tlm_u_tlm_tx_vc0_buf_pool_rvld_q[0]), + .I3(com_tlm_u_tlm_tx_vc0_buf_pool_rvld_q[1]), + .LO(com_tlm_u_tlm_tx_vc0_buf_pool_N_59299_i_3410) + ); + defparam com_tlm_u_tlm_tx_vc0_buf_pool_N_59300_i.INIT = 16'hECA0; + LUT4_L com_tlm_u_tlm_tx_vc0_buf_pool_N_59300_i ( + .I0(com_tlm_u_tlm_tx_vc0_buf_pool_rdata_q_all_28_), + .I1(com_tlm_u_tlm_tx_vc0_buf_pool_rdata_q_all_100_), + .I2(com_tlm_u_tlm_tx_vc0_buf_pool_rvld_q[0]), + .I3(com_tlm_u_tlm_tx_vc0_buf_pool_rvld_q[1]), + .LO(com_tlm_u_tlm_tx_vc0_buf_pool_N_59300_i_3411) + ); + defparam com_tlm_u_tlm_tx_vc0_buf_pool_N_59301_i.INIT = 16'hECA0; + LUT4_L com_tlm_u_tlm_tx_vc0_buf_pool_N_59301_i ( + .I0(com_tlm_u_tlm_tx_vc0_buf_pool_rdata_q_all_27_), + .I1(com_tlm_u_tlm_tx_vc0_buf_pool_rdata_q_all_99_), + .I2(com_tlm_u_tlm_tx_vc0_buf_pool_rvld_q[0]), + .I3(com_tlm_u_tlm_tx_vc0_buf_pool_rvld_q[1]), + .LO(com_tlm_u_tlm_tx_vc0_buf_pool_N_59301_i_3412) + ); + defparam com_tlm_u_tlm_tx_vc0_buf_pool_N_59302_i.INIT = 16'hECA0; + LUT4_L com_tlm_u_tlm_tx_vc0_buf_pool_N_59302_i ( + .I0(com_tlm_u_tlm_tx_vc0_buf_pool_rdata_q_all_26_), + .I1(com_tlm_u_tlm_tx_vc0_buf_pool_rdata_q_all_98_), + .I2(com_tlm_u_tlm_tx_vc0_buf_pool_rvld_q[0]), + .I3(com_tlm_u_tlm_tx_vc0_buf_pool_rvld_q[1]), + .LO(com_tlm_u_tlm_tx_vc0_buf_pool_N_59302_i_3413) + ); + defparam com_tlm_u_tlm_tx_vc0_buf_pool_N_59303_i.INIT = 16'hECA0; + LUT4_L com_tlm_u_tlm_tx_vc0_buf_pool_N_59303_i ( + .I0(com_tlm_u_tlm_tx_vc0_buf_pool_rdata_q_all_25_), + .I1(com_tlm_u_tlm_tx_vc0_buf_pool_rdata_q_all_97_), + .I2(com_tlm_u_tlm_tx_vc0_buf_pool_rvld_q[0]), + .I3(com_tlm_u_tlm_tx_vc0_buf_pool_rvld_q[1]), + .LO(com_tlm_u_tlm_tx_vc0_buf_pool_N_59303_i_3414) + ); + defparam com_tlm_u_tlm_tx_vc0_buf_pool_N_59304_i.INIT = 16'hECA0; + LUT4_L com_tlm_u_tlm_tx_vc0_buf_pool_N_59304_i ( + .I0(com_tlm_u_tlm_tx_vc0_buf_pool_rdata_q_all_24_), + .I1(com_tlm_u_tlm_tx_vc0_buf_pool_rdata_q_all_96_), + .I2(com_tlm_u_tlm_tx_vc0_buf_pool_rvld_q[0]), + .I3(com_tlm_u_tlm_tx_vc0_buf_pool_rvld_q[1]), + .LO(com_tlm_u_tlm_tx_vc0_buf_pool_N_59304_i_3415) + ); + defparam com_tlm_u_tlm_tx_vc0_buf_pool_N_59305_i.INIT = 16'hECA0; + LUT4_L com_tlm_u_tlm_tx_vc0_buf_pool_N_59305_i ( + .I0(com_tlm_u_tlm_tx_vc0_buf_pool_rdata_q_all_23_), + .I1(com_tlm_u_tlm_tx_vc0_buf_pool_rdata_q_all_95_), + .I2(com_tlm_u_tlm_tx_vc0_buf_pool_rvld_q[0]), + .I3(com_tlm_u_tlm_tx_vc0_buf_pool_rvld_q[1]), + .LO(com_tlm_u_tlm_tx_vc0_buf_pool_N_59305_i_3416) + ); + defparam com_tlm_u_tlm_tx_vc0_buf_pool_N_59306_i.INIT = 16'hECA0; + LUT4_L com_tlm_u_tlm_tx_vc0_buf_pool_N_59306_i ( + .I0(com_tlm_u_tlm_tx_vc0_buf_pool_rdata_q_all_22_), + .I1(com_tlm_u_tlm_tx_vc0_buf_pool_rdata_q_all_94_), + .I2(com_tlm_u_tlm_tx_vc0_buf_pool_rvld_q[0]), + .I3(com_tlm_u_tlm_tx_vc0_buf_pool_rvld_q[1]), + .LO(com_tlm_u_tlm_tx_vc0_buf_pool_N_59306_i_3417) + ); + defparam com_tlm_u_tlm_tx_vc0_buf_pool_N_59307_i.INIT = 16'hECA0; + LUT4_L com_tlm_u_tlm_tx_vc0_buf_pool_N_59307_i ( + .I0(com_tlm_u_tlm_tx_vc0_buf_pool_rdata_q_all_21_), + .I1(com_tlm_u_tlm_tx_vc0_buf_pool_rdata_q_all_93_), + .I2(com_tlm_u_tlm_tx_vc0_buf_pool_rvld_q[0]), + .I3(com_tlm_u_tlm_tx_vc0_buf_pool_rvld_q[1]), + .LO(com_tlm_u_tlm_tx_vc0_buf_pool_N_59307_i_3418) + ); + defparam com_tlm_u_tlm_tx_vc0_buf_pool_N_59308_i.INIT = 16'hECA0; + LUT4_L com_tlm_u_tlm_tx_vc0_buf_pool_N_59308_i ( + .I0(com_tlm_u_tlm_tx_vc0_buf_pool_rdata_q_all_20_), + .I1(com_tlm_u_tlm_tx_vc0_buf_pool_rdata_q_all_92_), + .I2(com_tlm_u_tlm_tx_vc0_buf_pool_rvld_q[0]), + .I3(com_tlm_u_tlm_tx_vc0_buf_pool_rvld_q[1]), + .LO(com_tlm_u_tlm_tx_vc0_buf_pool_N_59308_i_3419) + ); + defparam com_tlm_u_tlm_tx_vc0_buf_pool_N_59309_i.INIT = 16'hECA0; + LUT4_L com_tlm_u_tlm_tx_vc0_buf_pool_N_59309_i ( + .I0(com_tlm_u_tlm_tx_vc0_buf_pool_rdata_q_all_19_), + .I1(com_tlm_u_tlm_tx_vc0_buf_pool_rdata_q_all_91_), + .I2(com_tlm_u_tlm_tx_vc0_buf_pool_rvld_q[0]), + .I3(com_tlm_u_tlm_tx_vc0_buf_pool_rvld_q[1]), + .LO(com_tlm_u_tlm_tx_vc0_buf_pool_N_59309_i_3420) + ); + defparam com_tlm_u_tlm_tx_vc0_buf_pool_N_59310_i.INIT = 16'hECA0; + LUT4_L com_tlm_u_tlm_tx_vc0_buf_pool_N_59310_i ( + .I0(com_tlm_u_tlm_tx_vc0_buf_pool_rdata_q_all_18_), + .I1(com_tlm_u_tlm_tx_vc0_buf_pool_rdata_q_all_90_), + .I2(com_tlm_u_tlm_tx_vc0_buf_pool_rvld_q[0]), + .I3(com_tlm_u_tlm_tx_vc0_buf_pool_rvld_q[1]), + .LO(com_tlm_u_tlm_tx_vc0_buf_pool_N_59310_i_3421) + ); + defparam com_tlm_u_tlm_tx_vc0_buf_pool_N_59311_i.INIT = 16'hECA0; + LUT4_L com_tlm_u_tlm_tx_vc0_buf_pool_N_59311_i ( + .I0(com_tlm_u_tlm_tx_vc0_buf_pool_rdata_q_all_17_), + .I1(com_tlm_u_tlm_tx_vc0_buf_pool_rdata_q_all_89_), + .I2(com_tlm_u_tlm_tx_vc0_buf_pool_rvld_q[0]), + .I3(com_tlm_u_tlm_tx_vc0_buf_pool_rvld_q[1]), + .LO(com_tlm_u_tlm_tx_vc0_buf_pool_N_59311_i_3422) + ); + defparam com_tlm_u_tlm_tx_vc0_buf_pool_N_59312_i.INIT = 16'hECA0; + LUT4_L com_tlm_u_tlm_tx_vc0_buf_pool_N_59312_i ( + .I0(com_tlm_u_tlm_tx_vc0_buf_pool_rdata_q_all_16_), + .I1(com_tlm_u_tlm_tx_vc0_buf_pool_rdata_q_all_88_), + .I2(com_tlm_u_tlm_tx_vc0_buf_pool_rvld_q[0]), + .I3(com_tlm_u_tlm_tx_vc0_buf_pool_rvld_q[1]), + .LO(com_tlm_u_tlm_tx_vc0_buf_pool_N_59312_i_3423) + ); + defparam com_tlm_u_tlm_tx_vc0_buf_pool_N_59313_i.INIT = 16'hECA0; + LUT4_L com_tlm_u_tlm_tx_vc0_buf_pool_N_59313_i ( + .I0(com_tlm_u_tlm_tx_vc0_buf_pool_rdata_q_all_15_), + .I1(com_tlm_u_tlm_tx_vc0_buf_pool_rdata_q_all_87_), + .I2(com_tlm_u_tlm_tx_vc0_buf_pool_rvld_q[0]), + .I3(com_tlm_u_tlm_tx_vc0_buf_pool_rvld_q[1]), + .LO(com_tlm_u_tlm_tx_vc0_buf_pool_N_59313_i_3424) + ); + defparam com_tlm_u_tlm_tx_vc0_buf_pool_N_59314_i.INIT = 16'hECA0; + LUT4_L com_tlm_u_tlm_tx_vc0_buf_pool_N_59314_i ( + .I0(com_tlm_u_tlm_tx_vc0_buf_pool_rdata_q_all_14_), + .I1(com_tlm_u_tlm_tx_vc0_buf_pool_rdata_q_all_86_), + .I2(com_tlm_u_tlm_tx_vc0_buf_pool_rvld_q[0]), + .I3(com_tlm_u_tlm_tx_vc0_buf_pool_rvld_q[1]), + .LO(com_tlm_u_tlm_tx_vc0_buf_pool_N_59314_i_3425) + ); + defparam com_tlm_u_tlm_tx_vc0_buf_pool_N_59315_i.INIT = 16'hECA0; + LUT4_L com_tlm_u_tlm_tx_vc0_buf_pool_N_59315_i ( + .I0(com_tlm_u_tlm_tx_vc0_buf_pool_rdata_q_all_13_), + .I1(com_tlm_u_tlm_tx_vc0_buf_pool_rdata_q_all_85_), + .I2(com_tlm_u_tlm_tx_vc0_buf_pool_rvld_q[0]), + .I3(com_tlm_u_tlm_tx_vc0_buf_pool_rvld_q[1]), + .LO(com_tlm_u_tlm_tx_vc0_buf_pool_N_59315_i_3426) + ); + defparam com_tlm_u_tlm_tx_vc0_buf_pool_N_59316_i.INIT = 16'hECA0; + LUT4_L com_tlm_u_tlm_tx_vc0_buf_pool_N_59316_i ( + .I0(com_tlm_u_tlm_tx_vc0_buf_pool_rdata_q_all_12_), + .I1(com_tlm_u_tlm_tx_vc0_buf_pool_rdata_q_all_84_), + .I2(com_tlm_u_tlm_tx_vc0_buf_pool_rvld_q[0]), + .I3(com_tlm_u_tlm_tx_vc0_buf_pool_rvld_q[1]), + .LO(com_tlm_u_tlm_tx_vc0_buf_pool_N_59316_i_3427) + ); + defparam com_tlm_u_tlm_tx_vc0_buf_pool_N_59317_i.INIT = 16'hECA0; + LUT4_L com_tlm_u_tlm_tx_vc0_buf_pool_N_59317_i ( + .I0(com_tlm_u_tlm_tx_vc0_buf_pool_rdata_q_all_11_), + .I1(com_tlm_u_tlm_tx_vc0_buf_pool_rdata_q_all_83_), + .I2(com_tlm_u_tlm_tx_vc0_buf_pool_rvld_q[0]), + .I3(com_tlm_u_tlm_tx_vc0_buf_pool_rvld_q[1]), + .LO(com_tlm_u_tlm_tx_vc0_buf_pool_N_59317_i_3428) + ); + defparam com_tlm_u_tlm_tx_vc0_buf_pool_N_59318_i.INIT = 16'hECA0; + LUT4_L com_tlm_u_tlm_tx_vc0_buf_pool_N_59318_i ( + .I0(com_tlm_u_tlm_tx_vc0_buf_pool_rdata_q_all_10_), + .I1(com_tlm_u_tlm_tx_vc0_buf_pool_rdata_q_all_82_), + .I2(com_tlm_u_tlm_tx_vc0_buf_pool_rvld_q[0]), + .I3(com_tlm_u_tlm_tx_vc0_buf_pool_rvld_q[1]), + .LO(com_tlm_u_tlm_tx_vc0_buf_pool_N_59318_i_3429) + ); + defparam com_tlm_u_tlm_tx_vc0_buf_pool_N_59319_i.INIT = 16'hECA0; + LUT4_L com_tlm_u_tlm_tx_vc0_buf_pool_N_59319_i ( + .I0(com_tlm_u_tlm_tx_vc0_buf_pool_rdata_q_all_9_), + .I1(com_tlm_u_tlm_tx_vc0_buf_pool_rdata_q_all_81_), + .I2(com_tlm_u_tlm_tx_vc0_buf_pool_rvld_q[0]), + .I3(com_tlm_u_tlm_tx_vc0_buf_pool_rvld_q[1]), + .LO(com_tlm_u_tlm_tx_vc0_buf_pool_N_59319_i_3430) + ); + defparam com_tlm_u_tlm_tx_vc0_buf_pool_N_59320_i.INIT = 16'hECA0; + LUT4_L com_tlm_u_tlm_tx_vc0_buf_pool_N_59320_i ( + .I0(com_tlm_u_tlm_tx_vc0_buf_pool_rdata_q_all_8_), + .I1(com_tlm_u_tlm_tx_vc0_buf_pool_rdata_q_all_80_), + .I2(com_tlm_u_tlm_tx_vc0_buf_pool_rvld_q[0]), + .I3(com_tlm_u_tlm_tx_vc0_buf_pool_rvld_q[1]), + .LO(com_tlm_u_tlm_tx_vc0_buf_pool_N_59320_i_3431) + ); + defparam com_tlm_u_tlm_tx_vc0_buf_pool_N_59321_i.INIT = 16'hECA0; + LUT4_L com_tlm_u_tlm_tx_vc0_buf_pool_N_59321_i ( + .I0(com_tlm_u_tlm_tx_vc0_buf_pool_rdata_q_all_7_), + .I1(com_tlm_u_tlm_tx_vc0_buf_pool_rdata_q_all_79_), + .I2(com_tlm_u_tlm_tx_vc0_buf_pool_rvld_q[0]), + .I3(com_tlm_u_tlm_tx_vc0_buf_pool_rvld_q[1]), + .LO(com_tlm_u_tlm_tx_vc0_buf_pool_N_59321_i_3432) + ); + defparam com_tlm_u_tlm_tx_vc0_buf_pool_N_59322_i.INIT = 16'hECA0; + LUT4_L com_tlm_u_tlm_tx_vc0_buf_pool_N_59322_i ( + .I0(com_tlm_u_tlm_tx_vc0_buf_pool_rdata_q_all_6_), + .I1(com_tlm_u_tlm_tx_vc0_buf_pool_rdata_q_all_78_), + .I2(com_tlm_u_tlm_tx_vc0_buf_pool_rvld_q[0]), + .I3(com_tlm_u_tlm_tx_vc0_buf_pool_rvld_q[1]), + .LO(com_tlm_u_tlm_tx_vc0_buf_pool_N_59322_i_3433) + ); + defparam com_tlm_u_tlm_tx_vc0_buf_pool_N_59323_i.INIT = 16'hECA0; + LUT4_L com_tlm_u_tlm_tx_vc0_buf_pool_N_59323_i ( + .I0(com_tlm_u_tlm_tx_vc0_buf_pool_rdata_q_all_5_), + .I1(com_tlm_u_tlm_tx_vc0_buf_pool_rdata_q_all_77_), + .I2(com_tlm_u_tlm_tx_vc0_buf_pool_rvld_q[0]), + .I3(com_tlm_u_tlm_tx_vc0_buf_pool_rvld_q[1]), + .LO(com_tlm_u_tlm_tx_vc0_buf_pool_N_59323_i_3434) + ); + defparam com_tlm_u_tlm_tx_vc0_buf_pool_N_59324_i.INIT = 16'hECA0; + LUT4_L com_tlm_u_tlm_tx_vc0_buf_pool_N_59324_i ( + .I0(com_tlm_u_tlm_tx_vc0_buf_pool_rdata_q_all_4_), + .I1(com_tlm_u_tlm_tx_vc0_buf_pool_rdata_q_all_76_), + .I2(com_tlm_u_tlm_tx_vc0_buf_pool_rvld_q[0]), + .I3(com_tlm_u_tlm_tx_vc0_buf_pool_rvld_q[1]), + .LO(com_tlm_u_tlm_tx_vc0_buf_pool_N_59324_i_3435) + ); + defparam com_tlm_u_tlm_tx_vc0_buf_pool_N_59325_i.INIT = 16'hECA0; + LUT4_L com_tlm_u_tlm_tx_vc0_buf_pool_N_59325_i ( + .I0(com_tlm_u_tlm_tx_vc0_buf_pool_rdata_q_all_3_), + .I1(com_tlm_u_tlm_tx_vc0_buf_pool_rdata_q_all_75_), + .I2(com_tlm_u_tlm_tx_vc0_buf_pool_rvld_q[0]), + .I3(com_tlm_u_tlm_tx_vc0_buf_pool_rvld_q[1]), + .LO(com_tlm_u_tlm_tx_vc0_buf_pool_N_59325_i_3436) + ); + defparam com_tlm_u_tlm_tx_vc0_buf_pool_N_59326_i.INIT = 16'hECA0; + LUT4_L com_tlm_u_tlm_tx_vc0_buf_pool_N_59326_i ( + .I0(com_tlm_u_tlm_tx_vc0_buf_pool_rdata_q_all_2_), + .I1(com_tlm_u_tlm_tx_vc0_buf_pool_rdata_q_all_74_), + .I2(com_tlm_u_tlm_tx_vc0_buf_pool_rvld_q[0]), + .I3(com_tlm_u_tlm_tx_vc0_buf_pool_rvld_q[1]), + .LO(com_tlm_u_tlm_tx_vc0_buf_pool_N_59326_i_3437) + ); + defparam com_tlm_u_tlm_tx_vc0_buf_pool_N_59327_i.INIT = 16'hECA0; + LUT4_L com_tlm_u_tlm_tx_vc0_buf_pool_N_59327_i ( + .I0(com_tlm_u_tlm_tx_vc0_buf_pool_rdata_q_all_1_), + .I1(com_tlm_u_tlm_tx_vc0_buf_pool_rdata_q_all_73_), + .I2(com_tlm_u_tlm_tx_vc0_buf_pool_rvld_q[0]), + .I3(com_tlm_u_tlm_tx_vc0_buf_pool_rvld_q[1]), + .LO(com_tlm_u_tlm_tx_vc0_buf_pool_N_59327_i_3438) + ); + defparam com_tlm_u_tlm_tx_vc0_buf_pool_N_59182_i.INIT = 16'hECA0; + LUT4_L com_tlm_u_tlm_tx_vc0_buf_pool_N_59182_i ( + .I0(com_tlm_u_tlm_tx_vc0_buf_pool_rdata_q_all_0_), + .I1(com_tlm_u_tlm_tx_vc0_buf_pool_rdata_q_all_72_), + .I2(com_tlm_u_tlm_tx_vc0_buf_pool_rvld_q[0]), + .I3(com_tlm_u_tlm_tx_vc0_buf_pool_rvld_q[1]), + .LO(com_tlm_u_tlm_tx_vc0_buf_pool_N_59182_i_3439) + ); + defparam com_tlm_u_tlm_tx_vc0_buf_pool_N_86423_i.INIT = 8'hCE; + LUT3_L com_tlm_u_tlm_tx_vc0_buf_pool_N_86423_i ( + .I0(com_tlm_u_tlm_tx_vc0_buf_pool_wdata_errfwd_3441), + .I1(com_tlm_u_tlm_tx_vc0_trn_errfwd), + .I2(com_tlm_u_tlm_tx_vc0_trn_sof), + .LO(com_tlm_u_tlm_tx_vc0_buf_pool_N_86423_i_3440) + ); + defparam com_tlm_u_tlm_tx_vc0_buf_pool_N_87188_i.INIT = 8'h23; + LUT3_L com_tlm_u_tlm_tx_vc0_buf_pool_N_87188_i ( + .I0(com_tlm_u_tlm_tx_vc0_N_56167_i), + .I1(com_tlm_u_tlm_tx_vc0_buf_pool_rdata_sof_d_0_a2_0_a2_3301), + .I2(com_tlm_u_tlm_tx_vc0_in_frame), + .LO(com_tlm_u_tlm_tx_vc0_buf_pool_N_87188_i_3297) + ); + defparam com_tlm_u_tlm_tx_vc0_buf_pool_N_62985_i.INIT = 4'h1; + LUT1_L com_tlm_u_tlm_tx_vc0_buf_pool_N_62985_i ( + .I0(com_tlm_u_tlm_tx_vc0_buf_pool_rdata_sof_d_0_a2_0_a2_3301), + .LO(com_tlm_u_tlm_tx_vc0_buf_pool_N_62985_i_3298) + ); + defparam com_tlm_u_tlm_tx_vc0_buf_pool_rvld_bit_0__rvld_3_0_a2_0_a2_0_.INIT = 4'h1; + LUT2_L com_tlm_u_tlm_tx_vc0_buf_pool_rvld_bit_0__rvld_3_0_a2_0_a2_0_ ( + .I0(com_tlm_u_tlm_tx_vc0_buf_pool_rdata_sof_d_0_a2_0_a2_3301), + .I1(com_tlm_u_tlm_tx_vc0_buf_pool_raddr_h[3]), + .LO(com_tlm_u_tlm_tx_vc0_buf_pool_rvld_3[0]) + ); + defparam com_tlm_u_tlm_tx_vc0_buf_pool_rvld_bit_1__rvld_10_0_a2_0_a2_1_.INIT = 4'h4; + LUT2_L com_tlm_u_tlm_tx_vc0_buf_pool_rvld_bit_1__rvld_10_0_a2_0_a2_1_ ( + .I0(com_tlm_u_tlm_tx_vc0_buf_pool_rdata_sof_d_0_a2_0_a2_3301), + .I1(com_tlm_u_tlm_tx_vc0_buf_pool_raddr_h[3]), + .LO(com_tlm_u_tlm_tx_vc0_buf_pool_rvld_10[1]) + ); + defparam com_tlm_u_tlm_tx_vc0_buf_pool_rvld_bit_0__N_85563_i_1.INIT = 16'h135F; + LUT4 com_tlm_u_tlm_tx_vc0_buf_pool_rvld_bit_0__N_85563_i_1 ( + .I0(com_tlm_u_tlm_tx_vc0_buf_pool_rdata_q_all_67__3300), + .I1(com_tlm_u_tlm_tx_vc0_buf_pool_rdata_q_all_139__3299), + .I2(com_tlm_u_tlm_tx_vc0_buf_pool_rvld_q[0]), + .I3(com_tlm_u_tlm_tx_vc0_buf_pool_rvld_q[1]), + .O(com_tlm_u_tlm_tx_vc0_buf_pool_N_85563_i_1) + ); + defparam com_tlm_u_tlm_tx_vc0_buf_pool_rvld_bit_0__N_85563_i.INIT = 16'h3075; + LUT4 com_tlm_u_tlm_tx_vc0_buf_pool_rvld_bit_0__N_85563_i ( + .I0(com_tlm_u_tlm_tx_vc0_buf_pool_N_55898_i), + .I1(com_tlm_u_tlm_tx_vc0_buf_pool_rdata_sof_d_0_a2_0_a2_3301), + .I2(com_tlm_u_tlm_tx_vc0_buf_pool_en_ram_i_i), + .I3(com_tlm_u_tlm_tx_vc0_buf_pool_N_85563_i_1), + .O(com_tlm_u_tlm_tx_vc0_buf_pool_N_85563_i) + ); + defparam com_tlm_u_tlm_tx_vc0_buf_pool_N_86909_i_1.INIT = 8'h5D; + LUT3 com_tlm_u_tlm_tx_vc0_buf_pool_N_86909_i_1 ( + .I0(com_tlm_u_tlm_tx_vc0_buf_pool_N_55898_i), + .I1(com_tlm_u_tlm_tx_vc0_buf_pool_rvld_any_3303), + .I2(com_tlm_u_tlm_tx_vc0_buf_pool_rvld_q_any_3302), + .O(com_tlm_u_tlm_tx_vc0_buf_pool_N_86909_i_1_3304) + ); + FD com_tlm_u_tlm_tx_vc0_buf_pool_rdata_errfwd ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_buf_pool_errfwd), + .Q(com_tlm_u_tlm_tx_vc0_buf_pool_rdata_errfwd_3306) + ); + FD com_tlm_u_tlm_tx_vc0_buf_pool_raddr_h_3_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_buf_pool_raddr_h_0_0[3]), + .Q(com_tlm_u_tlm_tx_vc0_buf_pool_raddr_h[3]) + ); + FD com_tlm_u_tlm_tx_vc0_buf_pool_raddr_h_2_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_buf_pool_raddr_h_0_0[2]), + .Q(com_tlm_u_tlm_tx_vc0_buf_pool_raddr_h[2]) + ); + FD com_tlm_u_tlm_tx_vc0_buf_pool_raddr_h_1_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_buf_pool_raddr_h_0_0[1]), + .Q(com_tlm_u_tlm_tx_vc0_buf_pool_raddr_h[1]) + ); + FD com_tlm_u_tlm_tx_vc0_buf_pool_raddr_h_0_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_buf_pool_raddr_h_0_0[0]), + .Q(com_tlm_u_tlm_tx_vc0_buf_pool_raddr_h[0]) + ); + FDE com_tlm_u_tlm_tx_vc0_buf_pool_waddr_l_6_ ( + .CE(com_tlm_u_tlm_tx_vc0_buf_pool_N_10835_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_buf_pool_waddr_l_1[6]), + .Q(com_tlm_u_tlm_tx_vc0_buf_pool_waddr_l[6]) + ); + FDE com_tlm_u_tlm_tx_vc0_buf_pool_waddr_l_5_ ( + .CE(com_tlm_u_tlm_tx_vc0_buf_pool_N_10835_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_buf_pool_waddr_l_1[5]), + .Q(com_tlm_u_tlm_tx_vc0_buf_pool_waddr_l[5]) + ); + FDE com_tlm_u_tlm_tx_vc0_buf_pool_waddr_l_4_ ( + .CE(com_tlm_u_tlm_tx_vc0_buf_pool_N_10835_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_buf_pool_waddr_l_1[4]), + .Q(com_tlm_u_tlm_tx_vc0_buf_pool_waddr_l[4]) + ); + FDE com_tlm_u_tlm_tx_vc0_buf_pool_waddr_l_3_ ( + .CE(com_tlm_u_tlm_tx_vc0_buf_pool_N_10835_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_buf_pool_waddr_l_1[3]), + .Q(com_tlm_u_tlm_tx_vc0_buf_pool_waddr_l[3]) + ); + FDE com_tlm_u_tlm_tx_vc0_buf_pool_waddr_l_2_ ( + .CE(com_tlm_u_tlm_tx_vc0_buf_pool_N_10835_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_buf_pool_waddr_l_1[2]), + .Q(com_tlm_u_tlm_tx_vc0_buf_pool_waddr_l[2]) + ); + FDE com_tlm_u_tlm_tx_vc0_buf_pool_waddr_l_1_ ( + .CE(com_tlm_u_tlm_tx_vc0_buf_pool_N_10835_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_buf_pool_waddr_l_1[1]), + .Q(com_tlm_u_tlm_tx_vc0_buf_pool_waddr_l[1]) + ); + FDE com_tlm_u_tlm_tx_vc0_buf_pool_waddr_l_0_ ( + .CE(com_tlm_u_tlm_tx_vc0_buf_pool_N_10835_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_buf_pool_waddr_l_1[0]), + .Q(com_tlm_u_tlm_tx_vc0_buf_pool_waddr_l[0]) + ); + FDE com_tlm_u_tlm_tx_vc0_buf_pool_waddr_h_1_ ( + .CE(com_tlm_u_tlm_tx_vc0_trn_sof), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_tkn_buf_num[1]), + .Q(com_tlm_u_tlm_tx_vc0_buf_pool_waddr_h[1]) + ); + FDE com_tlm_u_tlm_tx_vc0_buf_pool_waddr_h_0_ ( + .CE(com_tlm_u_tlm_tx_vc0_trn_sof), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_tkn_buf_num[0]), + .Q(com_tlm_u_tlm_tx_vc0_buf_pool_waddr_h[0]) + ); + FDE com_tlm_u_tlm_tx_vc0_buf_pool_waddr_h_3_ ( + .CE(com_tlm_u_tlm_tx_vc0_trn_sof), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_tkn_buf_num[3]), + .Q(com_tlm_u_tlm_tx_vc0_buf_pool_waddr_h[3]) + ); + FDE com_tlm_u_tlm_tx_vc0_buf_pool_waddr_h_2_ ( + .CE(com_tlm_u_tlm_tx_vc0_trn_sof), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_tkn_buf_num[2]), + .Q(com_tlm_u_tlm_tx_vc0_buf_pool_waddr_h[2]) + ); + FDE com_tlm_u_tlm_tx_vc0_buf_pool_rdata_reg_0__rdata_q_all_63_ ( + .CE(com_tlm_u_tlm_tx_vc0_buf_pool_N_86909_i_1_3304), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all_63_), + .Q(com_tlm_u_tlm_tx_vc0_buf_pool_rdata_q_all_63_) + ); + FDE com_tlm_u_tlm_tx_vc0_buf_pool_rdata_reg_0__rdata_q_all_62_ ( + .CE(com_tlm_u_tlm_tx_vc0_buf_pool_N_86909_i_1_3304), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all_62_), + .Q(com_tlm_u_tlm_tx_vc0_buf_pool_rdata_q_all_62_) + ); + FDE com_tlm_u_tlm_tx_vc0_buf_pool_rdata_reg_0__rdata_q_all_61_ ( + .CE(com_tlm_u_tlm_tx_vc0_buf_pool_N_86909_i_1_3304), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all_61_), + .Q(com_tlm_u_tlm_tx_vc0_buf_pool_rdata_q_all_61_) + ); + FDE com_tlm_u_tlm_tx_vc0_buf_pool_rdata_reg_0__rdata_q_all_60_ ( + .CE(com_tlm_u_tlm_tx_vc0_buf_pool_N_86909_i_1_3304), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all_60_), + .Q(com_tlm_u_tlm_tx_vc0_buf_pool_rdata_q_all_60_) + ); + FDE com_tlm_u_tlm_tx_vc0_buf_pool_rdata_reg_0__rdata_q_all_59_ ( + .CE(com_tlm_u_tlm_tx_vc0_buf_pool_N_86909_i_1_3304), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all_59_), + .Q(com_tlm_u_tlm_tx_vc0_buf_pool_rdata_q_all_59_) + ); + FDE com_tlm_u_tlm_tx_vc0_buf_pool_rdata_reg_0__rdata_q_all_58_ ( + .CE(com_tlm_u_tlm_tx_vc0_buf_pool_N_86909_i_1_3304), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all_58_), + .Q(com_tlm_u_tlm_tx_vc0_buf_pool_rdata_q_all_58_) + ); + FDE com_tlm_u_tlm_tx_vc0_buf_pool_rdata_reg_0__rdata_q_all_57_ ( + .CE(com_tlm_u_tlm_tx_vc0_buf_pool_N_86909_i_1_3304), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all_57_), + .Q(com_tlm_u_tlm_tx_vc0_buf_pool_rdata_q_all_57_) + ); + FDE com_tlm_u_tlm_tx_vc0_buf_pool_rdata_reg_0__rdata_q_all_56_ ( + .CE(com_tlm_u_tlm_tx_vc0_buf_pool_N_86909_i_1_3304), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all_56_), + .Q(com_tlm_u_tlm_tx_vc0_buf_pool_rdata_q_all_56_) + ); + FDE com_tlm_u_tlm_tx_vc0_buf_pool_rdata_reg_0__rdata_q_all_55_ ( + .CE(com_tlm_u_tlm_tx_vc0_buf_pool_N_86909_i_1_3304), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all_55_), + .Q(com_tlm_u_tlm_tx_vc0_buf_pool_rdata_q_all_55_) + ); + FDE com_tlm_u_tlm_tx_vc0_buf_pool_rdata_reg_0__rdata_q_all_54_ ( + .CE(com_tlm_u_tlm_tx_vc0_buf_pool_N_86909_i_1_3304), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all_54_), + .Q(com_tlm_u_tlm_tx_vc0_buf_pool_rdata_q_all_54_) + ); + FDE com_tlm_u_tlm_tx_vc0_buf_pool_rdata_reg_0__rdata_q_all_53_ ( + .CE(com_tlm_u_tlm_tx_vc0_buf_pool_N_86909_i_1_3304), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all_53_), + .Q(com_tlm_u_tlm_tx_vc0_buf_pool_rdata_q_all_53_) + ); + FDE com_tlm_u_tlm_tx_vc0_buf_pool_rdata_reg_0__rdata_q_all_52_ ( + .CE(com_tlm_u_tlm_tx_vc0_buf_pool_N_86909_i_1_3304), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all_52_), + .Q(com_tlm_u_tlm_tx_vc0_buf_pool_rdata_q_all_52_) + ); + FDE com_tlm_u_tlm_tx_vc0_buf_pool_rdata_reg_0__rdata_q_all_51_ ( + .CE(com_tlm_u_tlm_tx_vc0_buf_pool_N_86909_i_1_3304), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all_51_), + .Q(com_tlm_u_tlm_tx_vc0_buf_pool_rdata_q_all_51_) + ); + FDE com_tlm_u_tlm_tx_vc0_buf_pool_rdata_reg_0__rdata_q_all_50_ ( + .CE(com_tlm_u_tlm_tx_vc0_buf_pool_N_86909_i_1_3304), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all_50_), + .Q(com_tlm_u_tlm_tx_vc0_buf_pool_rdata_q_all_50_) + ); + FDE com_tlm_u_tlm_tx_vc0_buf_pool_rdata_reg_0__rdata_q_all_49_ ( + .CE(com_tlm_u_tlm_tx_vc0_buf_pool_N_86909_i_1_3304), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all_49_), + .Q(com_tlm_u_tlm_tx_vc0_buf_pool_rdata_q_all_49_) + ); + FDE com_tlm_u_tlm_tx_vc0_buf_pool_rdata_reg_0__rdata_q_all_48_ ( + .CE(com_tlm_u_tlm_tx_vc0_buf_pool_N_86909_i_1_3304), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all_48_), + .Q(com_tlm_u_tlm_tx_vc0_buf_pool_rdata_q_all_48_) + ); + FDE com_tlm_u_tlm_tx_vc0_buf_pool_rdata_reg_0__rdata_q_all_47_ ( + .CE(com_tlm_u_tlm_tx_vc0_buf_pool_N_86909_i_1_3304), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all_47_), + .Q(com_tlm_u_tlm_tx_vc0_buf_pool_rdata_q_all_47_) + ); + FDE com_tlm_u_tlm_tx_vc0_buf_pool_rdata_reg_0__rdata_q_all_46_ ( + .CE(com_tlm_u_tlm_tx_vc0_buf_pool_N_86909_i_1_3304), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all_46_), + .Q(com_tlm_u_tlm_tx_vc0_buf_pool_rdata_q_all_46_) + ); + FDE com_tlm_u_tlm_tx_vc0_buf_pool_rdata_reg_0__rdata_q_all_45_ ( + .CE(com_tlm_u_tlm_tx_vc0_buf_pool_N_86909_i_1_3304), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all_45_), + .Q(com_tlm_u_tlm_tx_vc0_buf_pool_rdata_q_all_45_) + ); + FDE com_tlm_u_tlm_tx_vc0_buf_pool_rdata_reg_0__rdata_q_all_44_ ( + .CE(com_tlm_u_tlm_tx_vc0_buf_pool_N_86909_i_1_3304), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all_44_), + .Q(com_tlm_u_tlm_tx_vc0_buf_pool_rdata_q_all_44_) + ); + FDE com_tlm_u_tlm_tx_vc0_buf_pool_rdata_reg_0__rdata_q_all_43_ ( + .CE(com_tlm_u_tlm_tx_vc0_buf_pool_N_86909_i_1_3304), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all_43_), + .Q(com_tlm_u_tlm_tx_vc0_buf_pool_rdata_q_all_43_) + ); + FDE com_tlm_u_tlm_tx_vc0_buf_pool_rdata_reg_0__rdata_q_all_42_ ( + .CE(com_tlm_u_tlm_tx_vc0_buf_pool_N_86909_i_1_3304), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all_42_), + .Q(com_tlm_u_tlm_tx_vc0_buf_pool_rdata_q_all_42_) + ); + FDE com_tlm_u_tlm_tx_vc0_buf_pool_rdata_reg_0__rdata_q_all_41_ ( + .CE(com_tlm_u_tlm_tx_vc0_buf_pool_N_86909_i_1_3304), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all_41_), + .Q(com_tlm_u_tlm_tx_vc0_buf_pool_rdata_q_all_41_) + ); + FDE com_tlm_u_tlm_tx_vc0_buf_pool_rdata_reg_0__rdata_q_all_40_ ( + .CE(com_tlm_u_tlm_tx_vc0_buf_pool_N_86909_i_1_3304), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all_40_), + .Q(com_tlm_u_tlm_tx_vc0_buf_pool_rdata_q_all_40_) + ); + FDE com_tlm_u_tlm_tx_vc0_buf_pool_rdata_reg_0__rdata_q_all_39_ ( + .CE(com_tlm_u_tlm_tx_vc0_buf_pool_N_86909_i_1_3304), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all_39_), + .Q(com_tlm_u_tlm_tx_vc0_buf_pool_rdata_q_all_39_) + ); + FDE com_tlm_u_tlm_tx_vc0_buf_pool_rdata_reg_0__rdata_q_all_38_ ( + .CE(com_tlm_u_tlm_tx_vc0_buf_pool_N_86909_i_1_3304), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all_38_), + .Q(com_tlm_u_tlm_tx_vc0_buf_pool_rdata_q_all_38_) + ); + FDE com_tlm_u_tlm_tx_vc0_buf_pool_rdata_reg_0__rdata_q_all_37_ ( + .CE(com_tlm_u_tlm_tx_vc0_buf_pool_N_86909_i_1_3304), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all_37_), + .Q(com_tlm_u_tlm_tx_vc0_buf_pool_rdata_q_all_37_) + ); + FDE com_tlm_u_tlm_tx_vc0_buf_pool_rdata_reg_0__rdata_q_all_36_ ( + .CE(com_tlm_u_tlm_tx_vc0_buf_pool_N_86909_i_1_3304), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all_36_), + .Q(com_tlm_u_tlm_tx_vc0_buf_pool_rdata_q_all_36_) + ); + FDE com_tlm_u_tlm_tx_vc0_buf_pool_rdata_reg_0__rdata_q_all_35_ ( + .CE(com_tlm_u_tlm_tx_vc0_buf_pool_N_86909_i_1_3304), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all_35_), + .Q(com_tlm_u_tlm_tx_vc0_buf_pool_rdata_q_all_35_) + ); + FDE com_tlm_u_tlm_tx_vc0_buf_pool_rdata_reg_0__rdata_q_all_34_ ( + .CE(com_tlm_u_tlm_tx_vc0_buf_pool_N_86909_i_1_3304), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all_34_), + .Q(com_tlm_u_tlm_tx_vc0_buf_pool_rdata_q_all_34_) + ); + FDE com_tlm_u_tlm_tx_vc0_buf_pool_rdata_reg_0__rdata_q_all_33_ ( + .CE(com_tlm_u_tlm_tx_vc0_buf_pool_N_86909_i_1_3304), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all_33_), + .Q(com_tlm_u_tlm_tx_vc0_buf_pool_rdata_q_all_33_) + ); + FDE com_tlm_u_tlm_tx_vc0_buf_pool_rdata_reg_0__rdata_q_all_32_ ( + .CE(com_tlm_u_tlm_tx_vc0_buf_pool_N_86909_i_1_3304), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all_32_), + .Q(com_tlm_u_tlm_tx_vc0_buf_pool_rdata_q_all_32_) + ); + FDE com_tlm_u_tlm_tx_vc0_buf_pool_rdata_reg_0__rdata_q_all_31_ ( + .CE(com_tlm_u_tlm_tx_vc0_buf_pool_N_86909_i_1_3304), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all_31_), + .Q(com_tlm_u_tlm_tx_vc0_buf_pool_rdata_q_all_31_) + ); + FDE com_tlm_u_tlm_tx_vc0_buf_pool_rdata_reg_0__rdata_q_all_30_ ( + .CE(com_tlm_u_tlm_tx_vc0_buf_pool_N_86909_i_1_3304), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all_30_), + .Q(com_tlm_u_tlm_tx_vc0_buf_pool_rdata_q_all_30_) + ); + FDE com_tlm_u_tlm_tx_vc0_buf_pool_rdata_reg_0__rdata_q_all_29_ ( + .CE(com_tlm_u_tlm_tx_vc0_buf_pool_N_86909_i_1_3304), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all_29_), + .Q(com_tlm_u_tlm_tx_vc0_buf_pool_rdata_q_all_29_) + ); + FDE com_tlm_u_tlm_tx_vc0_buf_pool_rdata_reg_0__rdata_q_all_28_ ( + .CE(com_tlm_u_tlm_tx_vc0_buf_pool_N_86909_i_1_3304), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all_28_), + .Q(com_tlm_u_tlm_tx_vc0_buf_pool_rdata_q_all_28_) + ); + FDE com_tlm_u_tlm_tx_vc0_buf_pool_rdata_reg_0__rdata_q_all_27_ ( + .CE(com_tlm_u_tlm_tx_vc0_buf_pool_N_86909_i_1_3304), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all_27_), + .Q(com_tlm_u_tlm_tx_vc0_buf_pool_rdata_q_all_27_) + ); + FDE com_tlm_u_tlm_tx_vc0_buf_pool_rdata_reg_0__rdata_q_all_26_ ( + .CE(com_tlm_u_tlm_tx_vc0_buf_pool_N_86909_i_1_3304), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all_26_), + .Q(com_tlm_u_tlm_tx_vc0_buf_pool_rdata_q_all_26_) + ); + FDE com_tlm_u_tlm_tx_vc0_buf_pool_rdata_reg_0__rdata_q_all_25_ ( + .CE(com_tlm_u_tlm_tx_vc0_buf_pool_N_86909_i_1_3304), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all_25_), + .Q(com_tlm_u_tlm_tx_vc0_buf_pool_rdata_q_all_25_) + ); + FDE com_tlm_u_tlm_tx_vc0_buf_pool_rdata_reg_0__rdata_q_all_24_ ( + .CE(com_tlm_u_tlm_tx_vc0_buf_pool_N_86909_i_1_3304), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all_24_), + .Q(com_tlm_u_tlm_tx_vc0_buf_pool_rdata_q_all_24_) + ); + FDE com_tlm_u_tlm_tx_vc0_buf_pool_rdata_reg_0__rdata_q_all_23_ ( + .CE(com_tlm_u_tlm_tx_vc0_buf_pool_N_86909_i_1_3304), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all_23_), + .Q(com_tlm_u_tlm_tx_vc0_buf_pool_rdata_q_all_23_) + ); + FDE com_tlm_u_tlm_tx_vc0_buf_pool_rdata_reg_0__rdata_q_all_22_ ( + .CE(com_tlm_u_tlm_tx_vc0_buf_pool_N_86909_i_1_3304), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all_22_), + .Q(com_tlm_u_tlm_tx_vc0_buf_pool_rdata_q_all_22_) + ); + FDE com_tlm_u_tlm_tx_vc0_buf_pool_rdata_reg_0__rdata_q_all_21_ ( + .CE(com_tlm_u_tlm_tx_vc0_buf_pool_N_86909_i_1_3304), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all_21_), + .Q(com_tlm_u_tlm_tx_vc0_buf_pool_rdata_q_all_21_) + ); + FDE com_tlm_u_tlm_tx_vc0_buf_pool_rdata_reg_0__rdata_q_all_20_ ( + .CE(com_tlm_u_tlm_tx_vc0_buf_pool_N_86909_i_1_3304), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all_20_), + .Q(com_tlm_u_tlm_tx_vc0_buf_pool_rdata_q_all_20_) + ); + FDE com_tlm_u_tlm_tx_vc0_buf_pool_rdata_reg_0__rdata_q_all_19_ ( + .CE(com_tlm_u_tlm_tx_vc0_buf_pool_N_86909_i_1_3304), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all_19_), + .Q(com_tlm_u_tlm_tx_vc0_buf_pool_rdata_q_all_19_) + ); + FDE com_tlm_u_tlm_tx_vc0_buf_pool_rdata_reg_0__rdata_q_all_18_ ( + .CE(com_tlm_u_tlm_tx_vc0_buf_pool_N_86909_i_1_3304), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all_18_), + .Q(com_tlm_u_tlm_tx_vc0_buf_pool_rdata_q_all_18_) + ); + FDE com_tlm_u_tlm_tx_vc0_buf_pool_rdata_reg_0__rdata_q_all_17_ ( + .CE(com_tlm_u_tlm_tx_vc0_buf_pool_N_86909_i_1_3304), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all_17_), + .Q(com_tlm_u_tlm_tx_vc0_buf_pool_rdata_q_all_17_) + ); + FDE com_tlm_u_tlm_tx_vc0_buf_pool_rdata_reg_0__rdata_q_all_16_ ( + .CE(com_tlm_u_tlm_tx_vc0_buf_pool_N_86909_i_1_3304), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all_16_), + .Q(com_tlm_u_tlm_tx_vc0_buf_pool_rdata_q_all_16_) + ); + FDE com_tlm_u_tlm_tx_vc0_buf_pool_rdata_reg_0__rdata_q_all_15_ ( + .CE(com_tlm_u_tlm_tx_vc0_buf_pool_N_86909_i_1_3304), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all_15_), + .Q(com_tlm_u_tlm_tx_vc0_buf_pool_rdata_q_all_15_) + ); + FDE com_tlm_u_tlm_tx_vc0_buf_pool_rdata_reg_0__rdata_q_all_14_ ( + .CE(com_tlm_u_tlm_tx_vc0_buf_pool_N_86909_i_1_3304), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all_14_), + .Q(com_tlm_u_tlm_tx_vc0_buf_pool_rdata_q_all_14_) + ); + FDE com_tlm_u_tlm_tx_vc0_buf_pool_rdata_reg_0__rdata_q_all_13_ ( + .CE(com_tlm_u_tlm_tx_vc0_buf_pool_N_86909_i_1_3304), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all_13_), + .Q(com_tlm_u_tlm_tx_vc0_buf_pool_rdata_q_all_13_) + ); + FDE com_tlm_u_tlm_tx_vc0_buf_pool_rdata_reg_0__rdata_q_all_12_ ( + .CE(com_tlm_u_tlm_tx_vc0_buf_pool_N_86909_i_1_3304), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all_12_), + .Q(com_tlm_u_tlm_tx_vc0_buf_pool_rdata_q_all_12_) + ); + FDE com_tlm_u_tlm_tx_vc0_buf_pool_rdata_reg_0__rdata_q_all_11_ ( + .CE(com_tlm_u_tlm_tx_vc0_buf_pool_N_86909_i_1_3304), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all_11_), + .Q(com_tlm_u_tlm_tx_vc0_buf_pool_rdata_q_all_11_) + ); + FDE com_tlm_u_tlm_tx_vc0_buf_pool_rdata_reg_0__rdata_q_all_10_ ( + .CE(com_tlm_u_tlm_tx_vc0_buf_pool_N_86909_i_1_3304), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all_10_), + .Q(com_tlm_u_tlm_tx_vc0_buf_pool_rdata_q_all_10_) + ); + FDE com_tlm_u_tlm_tx_vc0_buf_pool_rdata_reg_0__rdata_q_all_9_ ( + .CE(com_tlm_u_tlm_tx_vc0_buf_pool_N_86909_i_1_3304), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all_9_), + .Q(com_tlm_u_tlm_tx_vc0_buf_pool_rdata_q_all_9_) + ); + FDE com_tlm_u_tlm_tx_vc0_buf_pool_rdata_reg_0__rdata_q_all_8_ ( + .CE(com_tlm_u_tlm_tx_vc0_buf_pool_N_86909_i_1_3304), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all_8_), + .Q(com_tlm_u_tlm_tx_vc0_buf_pool_rdata_q_all_8_) + ); + FDE com_tlm_u_tlm_tx_vc0_buf_pool_rdata_reg_0__rdata_q_all_7_ ( + .CE(com_tlm_u_tlm_tx_vc0_buf_pool_N_86909_i_1_3304), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all_7_), + .Q(com_tlm_u_tlm_tx_vc0_buf_pool_rdata_q_all_7_) + ); + FDE com_tlm_u_tlm_tx_vc0_buf_pool_rdata_reg_0__rdata_q_all_6_ ( + .CE(com_tlm_u_tlm_tx_vc0_buf_pool_N_86909_i_1_3304), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all_6_), + .Q(com_tlm_u_tlm_tx_vc0_buf_pool_rdata_q_all_6_) + ); + FDE com_tlm_u_tlm_tx_vc0_buf_pool_rdata_reg_0__rdata_q_all_5_ ( + .CE(com_tlm_u_tlm_tx_vc0_buf_pool_N_86909_i_1_3304), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all_5_), + .Q(com_tlm_u_tlm_tx_vc0_buf_pool_rdata_q_all_5_) + ); + FDE com_tlm_u_tlm_tx_vc0_buf_pool_rdata_reg_0__rdata_q_all_4_ ( + .CE(com_tlm_u_tlm_tx_vc0_buf_pool_N_86909_i_1_3304), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all_4_), + .Q(com_tlm_u_tlm_tx_vc0_buf_pool_rdata_q_all_4_) + ); + FDE com_tlm_u_tlm_tx_vc0_buf_pool_rdata_reg_0__rdata_q_all_3_ ( + .CE(com_tlm_u_tlm_tx_vc0_buf_pool_N_86909_i_1_3304), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all_3_), + .Q(com_tlm_u_tlm_tx_vc0_buf_pool_rdata_q_all_3_) + ); + FDE com_tlm_u_tlm_tx_vc0_buf_pool_rdata_reg_0__rdata_q_all_2_ ( + .CE(com_tlm_u_tlm_tx_vc0_buf_pool_N_86909_i_1_3304), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all_2_), + .Q(com_tlm_u_tlm_tx_vc0_buf_pool_rdata_q_all_2_) + ); + FDE com_tlm_u_tlm_tx_vc0_buf_pool_rdata_reg_0__rdata_q_all_1_ ( + .CE(com_tlm_u_tlm_tx_vc0_buf_pool_N_86909_i_1_3304), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all_1_), + .Q(com_tlm_u_tlm_tx_vc0_buf_pool_rdata_q_all_1_) + ); + FDE com_tlm_u_tlm_tx_vc0_buf_pool_rdata_reg_0__rdata_q_all_0_ ( + .CE(com_tlm_u_tlm_tx_vc0_buf_pool_N_86909_i_1_3304), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all_0_), + .Q(com_tlm_u_tlm_tx_vc0_buf_pool_rdata_q_all_0_) + ); + FDE com_tlm_u_tlm_tx_vc0_buf_pool_rdata_reg_1__rdata_q_all_135_ ( + .CE(com_tlm_u_tlm_tx_vc0_buf_pool_N_86909_i_1_3304), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all_135_), + .Q(com_tlm_u_tlm_tx_vc0_buf_pool_rdata_q_all_135_) + ); + FDE com_tlm_u_tlm_tx_vc0_buf_pool_rdata_reg_1__rdata_q_all_134_ ( + .CE(com_tlm_u_tlm_tx_vc0_buf_pool_N_86909_i_1_3304), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all_134_), + .Q(com_tlm_u_tlm_tx_vc0_buf_pool_rdata_q_all_134_) + ); + FDE com_tlm_u_tlm_tx_vc0_buf_pool_rdata_reg_1__rdata_q_all_133_ ( + .CE(com_tlm_u_tlm_tx_vc0_buf_pool_N_86909_i_1_3304), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all_133_), + .Q(com_tlm_u_tlm_tx_vc0_buf_pool_rdata_q_all_133_) + ); + FDE com_tlm_u_tlm_tx_vc0_buf_pool_rdata_reg_1__rdata_q_all_132_ ( + .CE(com_tlm_u_tlm_tx_vc0_buf_pool_N_86909_i_1_3304), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all_132_), + .Q(com_tlm_u_tlm_tx_vc0_buf_pool_rdata_q_all_132_) + ); + FDE com_tlm_u_tlm_tx_vc0_buf_pool_rdata_reg_1__rdata_q_all_131_ ( + .CE(com_tlm_u_tlm_tx_vc0_buf_pool_N_86909_i_1_3304), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all_131_), + .Q(com_tlm_u_tlm_tx_vc0_buf_pool_rdata_q_all_131_) + ); + FDE com_tlm_u_tlm_tx_vc0_buf_pool_rdata_reg_1__rdata_q_all_130_ ( + .CE(com_tlm_u_tlm_tx_vc0_buf_pool_N_86909_i_3305), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all_130_), + .Q(com_tlm_u_tlm_tx_vc0_buf_pool_rdata_q_all_130_) + ); + FDE com_tlm_u_tlm_tx_vc0_buf_pool_rdata_reg_1__rdata_q_all_129_ ( + .CE(com_tlm_u_tlm_tx_vc0_buf_pool_N_86909_i_3305), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all_129_), + .Q(com_tlm_u_tlm_tx_vc0_buf_pool_rdata_q_all_129_) + ); + FDE com_tlm_u_tlm_tx_vc0_buf_pool_rdata_reg_1__rdata_q_all_128_ ( + .CE(com_tlm_u_tlm_tx_vc0_buf_pool_N_86909_i_3305), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all_128_), + .Q(com_tlm_u_tlm_tx_vc0_buf_pool_rdata_q_all_128_) + ); + FDE com_tlm_u_tlm_tx_vc0_buf_pool_rdata_reg_1__rdata_q_all_127_ ( + .CE(com_tlm_u_tlm_tx_vc0_buf_pool_N_86909_i_3305), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all_127_), + .Q(com_tlm_u_tlm_tx_vc0_buf_pool_rdata_q_all_127_) + ); + FDE com_tlm_u_tlm_tx_vc0_buf_pool_rdata_reg_1__rdata_q_all_126_ ( + .CE(com_tlm_u_tlm_tx_vc0_buf_pool_N_86909_i_3305), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all_126_), + .Q(com_tlm_u_tlm_tx_vc0_buf_pool_rdata_q_all_126_) + ); + FDE com_tlm_u_tlm_tx_vc0_buf_pool_rdata_reg_1__rdata_q_all_125_ ( + .CE(com_tlm_u_tlm_tx_vc0_buf_pool_N_86909_i_3305), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all_125_), + .Q(com_tlm_u_tlm_tx_vc0_buf_pool_rdata_q_all_125_) + ); + FDE com_tlm_u_tlm_tx_vc0_buf_pool_rdata_reg_1__rdata_q_all_124_ ( + .CE(com_tlm_u_tlm_tx_vc0_buf_pool_N_86909_i_3305), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all_124_), + .Q(com_tlm_u_tlm_tx_vc0_buf_pool_rdata_q_all_124_) + ); + FDE com_tlm_u_tlm_tx_vc0_buf_pool_rdata_reg_1__rdata_q_all_123_ ( + .CE(com_tlm_u_tlm_tx_vc0_buf_pool_N_86909_i_3305), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all_123_), + .Q(com_tlm_u_tlm_tx_vc0_buf_pool_rdata_q_all_123_) + ); + FDE com_tlm_u_tlm_tx_vc0_buf_pool_rdata_reg_1__rdata_q_all_122_ ( + .CE(com_tlm_u_tlm_tx_vc0_buf_pool_N_86909_i_3305), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all_122_), + .Q(com_tlm_u_tlm_tx_vc0_buf_pool_rdata_q_all_122_) + ); + FDE com_tlm_u_tlm_tx_vc0_buf_pool_rdata_reg_1__rdata_q_all_121_ ( + .CE(com_tlm_u_tlm_tx_vc0_buf_pool_N_86909_i_3305), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all_121_), + .Q(com_tlm_u_tlm_tx_vc0_buf_pool_rdata_q_all_121_) + ); + FDE com_tlm_u_tlm_tx_vc0_buf_pool_rdata_reg_1__rdata_q_all_120_ ( + .CE(com_tlm_u_tlm_tx_vc0_buf_pool_N_86909_i_3305), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all_120_), + .Q(com_tlm_u_tlm_tx_vc0_buf_pool_rdata_q_all_120_) + ); + FDE com_tlm_u_tlm_tx_vc0_buf_pool_rdata_reg_1__rdata_q_all_119_ ( + .CE(com_tlm_u_tlm_tx_vc0_buf_pool_N_86909_i_3305), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all_119_), + .Q(com_tlm_u_tlm_tx_vc0_buf_pool_rdata_q_all_119_) + ); + FDE com_tlm_u_tlm_tx_vc0_buf_pool_rdata_reg_1__rdata_q_all_118_ ( + .CE(com_tlm_u_tlm_tx_vc0_buf_pool_N_86909_i_3305), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all_118_), + .Q(com_tlm_u_tlm_tx_vc0_buf_pool_rdata_q_all_118_) + ); + FDE com_tlm_u_tlm_tx_vc0_buf_pool_rdata_reg_1__rdata_q_all_117_ ( + .CE(com_tlm_u_tlm_tx_vc0_buf_pool_N_86909_i_3305), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all_117_), + .Q(com_tlm_u_tlm_tx_vc0_buf_pool_rdata_q_all_117_) + ); + FDE com_tlm_u_tlm_tx_vc0_buf_pool_rdata_reg_1__rdata_q_all_116_ ( + .CE(com_tlm_u_tlm_tx_vc0_buf_pool_N_86909_i_3305), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all_116_), + .Q(com_tlm_u_tlm_tx_vc0_buf_pool_rdata_q_all_116_) + ); + FDE com_tlm_u_tlm_tx_vc0_buf_pool_rdata_reg_1__rdata_q_all_115_ ( + .CE(com_tlm_u_tlm_tx_vc0_buf_pool_N_86909_i_3305), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all_115_), + .Q(com_tlm_u_tlm_tx_vc0_buf_pool_rdata_q_all_115_) + ); + FDE com_tlm_u_tlm_tx_vc0_buf_pool_rdata_reg_1__rdata_q_all_114_ ( + .CE(com_tlm_u_tlm_tx_vc0_buf_pool_N_86909_i_3305), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all_114_), + .Q(com_tlm_u_tlm_tx_vc0_buf_pool_rdata_q_all_114_) + ); + FDE com_tlm_u_tlm_tx_vc0_buf_pool_rdata_reg_1__rdata_q_all_113_ ( + .CE(com_tlm_u_tlm_tx_vc0_buf_pool_N_86909_i_3305), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all_113_), + .Q(com_tlm_u_tlm_tx_vc0_buf_pool_rdata_q_all_113_) + ); + FDE com_tlm_u_tlm_tx_vc0_buf_pool_rdata_reg_1__rdata_q_all_112_ ( + .CE(com_tlm_u_tlm_tx_vc0_buf_pool_N_86909_i_3305), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all_112_), + .Q(com_tlm_u_tlm_tx_vc0_buf_pool_rdata_q_all_112_) + ); + FDE com_tlm_u_tlm_tx_vc0_buf_pool_rdata_reg_1__rdata_q_all_111_ ( + .CE(com_tlm_u_tlm_tx_vc0_buf_pool_N_86909_i_3305), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all_111_), + .Q(com_tlm_u_tlm_tx_vc0_buf_pool_rdata_q_all_111_) + ); + FDE com_tlm_u_tlm_tx_vc0_buf_pool_rdata_reg_1__rdata_q_all_110_ ( + .CE(com_tlm_u_tlm_tx_vc0_buf_pool_N_86909_i_3305), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all_110_), + .Q(com_tlm_u_tlm_tx_vc0_buf_pool_rdata_q_all_110_) + ); + FDE com_tlm_u_tlm_tx_vc0_buf_pool_rdata_reg_1__rdata_q_all_109_ ( + .CE(com_tlm_u_tlm_tx_vc0_buf_pool_N_86909_i_3305), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all_109_), + .Q(com_tlm_u_tlm_tx_vc0_buf_pool_rdata_q_all_109_) + ); + FDE com_tlm_u_tlm_tx_vc0_buf_pool_rdata_reg_1__rdata_q_all_108_ ( + .CE(com_tlm_u_tlm_tx_vc0_buf_pool_N_86909_i_3305), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all_108_), + .Q(com_tlm_u_tlm_tx_vc0_buf_pool_rdata_q_all_108_) + ); + FDE com_tlm_u_tlm_tx_vc0_buf_pool_rdata_reg_1__rdata_q_all_107_ ( + .CE(com_tlm_u_tlm_tx_vc0_buf_pool_N_86909_i_3305), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all_107_), + .Q(com_tlm_u_tlm_tx_vc0_buf_pool_rdata_q_all_107_) + ); + FDE com_tlm_u_tlm_tx_vc0_buf_pool_rdata_reg_1__rdata_q_all_106_ ( + .CE(com_tlm_u_tlm_tx_vc0_buf_pool_N_86909_i_3305), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all_106_), + .Q(com_tlm_u_tlm_tx_vc0_buf_pool_rdata_q_all_106_) + ); + FDE com_tlm_u_tlm_tx_vc0_buf_pool_rdata_reg_1__rdata_q_all_105_ ( + .CE(com_tlm_u_tlm_tx_vc0_buf_pool_N_86909_i_3305), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all_105_), + .Q(com_tlm_u_tlm_tx_vc0_buf_pool_rdata_q_all_105_) + ); + FDE com_tlm_u_tlm_tx_vc0_buf_pool_rdata_reg_1__rdata_q_all_104_ ( + .CE(com_tlm_u_tlm_tx_vc0_buf_pool_N_86909_i_3305), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all_104_), + .Q(com_tlm_u_tlm_tx_vc0_buf_pool_rdata_q_all_104_) + ); + FDE com_tlm_u_tlm_tx_vc0_buf_pool_rdata_reg_1__rdata_q_all_103_ ( + .CE(com_tlm_u_tlm_tx_vc0_buf_pool_N_86909_i_3305), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all_103_), + .Q(com_tlm_u_tlm_tx_vc0_buf_pool_rdata_q_all_103_) + ); + FDE com_tlm_u_tlm_tx_vc0_buf_pool_rdata_reg_1__rdata_q_all_102_ ( + .CE(com_tlm_u_tlm_tx_vc0_buf_pool_N_86909_i_3305), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all_102_), + .Q(com_tlm_u_tlm_tx_vc0_buf_pool_rdata_q_all_102_) + ); + FDE com_tlm_u_tlm_tx_vc0_buf_pool_rdata_reg_1__rdata_q_all_101_ ( + .CE(com_tlm_u_tlm_tx_vc0_buf_pool_N_86909_i_3305), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all_101_), + .Q(com_tlm_u_tlm_tx_vc0_buf_pool_rdata_q_all_101_) + ); + FDE com_tlm_u_tlm_tx_vc0_buf_pool_rdata_reg_1__rdata_q_all_100_ ( + .CE(com_tlm_u_tlm_tx_vc0_buf_pool_N_86909_i_3305), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all_100_), + .Q(com_tlm_u_tlm_tx_vc0_buf_pool_rdata_q_all_100_) + ); + FDE com_tlm_u_tlm_tx_vc0_buf_pool_rdata_reg_1__rdata_q_all_99_ ( + .CE(com_tlm_u_tlm_tx_vc0_buf_pool_N_86909_i_3305), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all_99_), + .Q(com_tlm_u_tlm_tx_vc0_buf_pool_rdata_q_all_99_) + ); + FDE com_tlm_u_tlm_tx_vc0_buf_pool_rdata_reg_1__rdata_q_all_98_ ( + .CE(com_tlm_u_tlm_tx_vc0_buf_pool_N_86909_i_3305), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all_98_), + .Q(com_tlm_u_tlm_tx_vc0_buf_pool_rdata_q_all_98_) + ); + FDE com_tlm_u_tlm_tx_vc0_buf_pool_rdata_reg_1__rdata_q_all_97_ ( + .CE(com_tlm_u_tlm_tx_vc0_buf_pool_N_86909_i_3305), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all_97_), + .Q(com_tlm_u_tlm_tx_vc0_buf_pool_rdata_q_all_97_) + ); + FDE com_tlm_u_tlm_tx_vc0_buf_pool_rdata_reg_1__rdata_q_all_96_ ( + .CE(com_tlm_u_tlm_tx_vc0_buf_pool_N_86909_i_3305), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all_96_), + .Q(com_tlm_u_tlm_tx_vc0_buf_pool_rdata_q_all_96_) + ); + FDE com_tlm_u_tlm_tx_vc0_buf_pool_rdata_reg_1__rdata_q_all_95_ ( + .CE(com_tlm_u_tlm_tx_vc0_buf_pool_N_86909_i_3305), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all_95_), + .Q(com_tlm_u_tlm_tx_vc0_buf_pool_rdata_q_all_95_) + ); + FDE com_tlm_u_tlm_tx_vc0_buf_pool_rdata_reg_1__rdata_q_all_94_ ( + .CE(com_tlm_u_tlm_tx_vc0_buf_pool_N_86909_i_3305), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all_94_), + .Q(com_tlm_u_tlm_tx_vc0_buf_pool_rdata_q_all_94_) + ); + FDE com_tlm_u_tlm_tx_vc0_buf_pool_rdata_reg_1__rdata_q_all_93_ ( + .CE(com_tlm_u_tlm_tx_vc0_buf_pool_N_86909_i_3305), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all_93_), + .Q(com_tlm_u_tlm_tx_vc0_buf_pool_rdata_q_all_93_) + ); + FDE com_tlm_u_tlm_tx_vc0_buf_pool_rdata_reg_1__rdata_q_all_92_ ( + .CE(com_tlm_u_tlm_tx_vc0_buf_pool_N_86909_i_3305), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all_92_), + .Q(com_tlm_u_tlm_tx_vc0_buf_pool_rdata_q_all_92_) + ); + FDE com_tlm_u_tlm_tx_vc0_buf_pool_rdata_reg_1__rdata_q_all_91_ ( + .CE(com_tlm_u_tlm_tx_vc0_buf_pool_N_86909_i_3305), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all_91_), + .Q(com_tlm_u_tlm_tx_vc0_buf_pool_rdata_q_all_91_) + ); + FDE com_tlm_u_tlm_tx_vc0_buf_pool_rdata_reg_1__rdata_q_all_90_ ( + .CE(com_tlm_u_tlm_tx_vc0_buf_pool_N_86909_i_3305), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all_90_), + .Q(com_tlm_u_tlm_tx_vc0_buf_pool_rdata_q_all_90_) + ); + FDE com_tlm_u_tlm_tx_vc0_buf_pool_rdata_reg_1__rdata_q_all_89_ ( + .CE(com_tlm_u_tlm_tx_vc0_buf_pool_N_86909_i_3305), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all_89_), + .Q(com_tlm_u_tlm_tx_vc0_buf_pool_rdata_q_all_89_) + ); + FDE com_tlm_u_tlm_tx_vc0_buf_pool_rdata_reg_1__rdata_q_all_88_ ( + .CE(com_tlm_u_tlm_tx_vc0_buf_pool_N_86909_i_3305), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all_88_), + .Q(com_tlm_u_tlm_tx_vc0_buf_pool_rdata_q_all_88_) + ); + FDE com_tlm_u_tlm_tx_vc0_buf_pool_rdata_reg_1__rdata_q_all_87_ ( + .CE(com_tlm_u_tlm_tx_vc0_buf_pool_N_86909_i_3305), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all_87_), + .Q(com_tlm_u_tlm_tx_vc0_buf_pool_rdata_q_all_87_) + ); + FDE com_tlm_u_tlm_tx_vc0_buf_pool_rdata_reg_1__rdata_q_all_86_ ( + .CE(com_tlm_u_tlm_tx_vc0_buf_pool_N_86909_i_3305), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all_86_), + .Q(com_tlm_u_tlm_tx_vc0_buf_pool_rdata_q_all_86_) + ); + FDE com_tlm_u_tlm_tx_vc0_buf_pool_rdata_reg_1__rdata_q_all_85_ ( + .CE(com_tlm_u_tlm_tx_vc0_buf_pool_N_86909_i_3305), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all_85_), + .Q(com_tlm_u_tlm_tx_vc0_buf_pool_rdata_q_all_85_) + ); + FDE com_tlm_u_tlm_tx_vc0_buf_pool_rdata_reg_1__rdata_q_all_84_ ( + .CE(com_tlm_u_tlm_tx_vc0_buf_pool_N_86909_i_3305), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all_84_), + .Q(com_tlm_u_tlm_tx_vc0_buf_pool_rdata_q_all_84_) + ); + FDE com_tlm_u_tlm_tx_vc0_buf_pool_rdata_reg_1__rdata_q_all_83_ ( + .CE(com_tlm_u_tlm_tx_vc0_buf_pool_N_86909_i_3305), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all_83_), + .Q(com_tlm_u_tlm_tx_vc0_buf_pool_rdata_q_all_83_) + ); + FDE com_tlm_u_tlm_tx_vc0_buf_pool_rdata_reg_1__rdata_q_all_82_ ( + .CE(com_tlm_u_tlm_tx_vc0_buf_pool_N_86909_i_3305), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all_82_), + .Q(com_tlm_u_tlm_tx_vc0_buf_pool_rdata_q_all_82_) + ); + FDE com_tlm_u_tlm_tx_vc0_buf_pool_rdata_reg_1__rdata_q_all_81_ ( + .CE(com_tlm_u_tlm_tx_vc0_buf_pool_N_86909_i_3305), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all_81_), + .Q(com_tlm_u_tlm_tx_vc0_buf_pool_rdata_q_all_81_) + ); + FDE com_tlm_u_tlm_tx_vc0_buf_pool_rdata_reg_1__rdata_q_all_80_ ( + .CE(com_tlm_u_tlm_tx_vc0_buf_pool_N_86909_i_3305), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all_80_), + .Q(com_tlm_u_tlm_tx_vc0_buf_pool_rdata_q_all_80_) + ); + FDE com_tlm_u_tlm_tx_vc0_buf_pool_rdata_reg_1__rdata_q_all_79_ ( + .CE(com_tlm_u_tlm_tx_vc0_buf_pool_N_86909_i_3305), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all_79_), + .Q(com_tlm_u_tlm_tx_vc0_buf_pool_rdata_q_all_79_) + ); + FDE com_tlm_u_tlm_tx_vc0_buf_pool_rdata_reg_1__rdata_q_all_78_ ( + .CE(com_tlm_u_tlm_tx_vc0_buf_pool_N_86909_i_3305), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all_78_), + .Q(com_tlm_u_tlm_tx_vc0_buf_pool_rdata_q_all_78_) + ); + FDE com_tlm_u_tlm_tx_vc0_buf_pool_rdata_reg_1__rdata_q_all_77_ ( + .CE(com_tlm_u_tlm_tx_vc0_buf_pool_N_86909_i_3305), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all_77_), + .Q(com_tlm_u_tlm_tx_vc0_buf_pool_rdata_q_all_77_) + ); + FDE com_tlm_u_tlm_tx_vc0_buf_pool_rdata_reg_1__rdata_q_all_76_ ( + .CE(com_tlm_u_tlm_tx_vc0_buf_pool_N_86909_i_3305), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all_76_), + .Q(com_tlm_u_tlm_tx_vc0_buf_pool_rdata_q_all_76_) + ); + FDE com_tlm_u_tlm_tx_vc0_buf_pool_rdata_reg_1__rdata_q_all_75_ ( + .CE(com_tlm_u_tlm_tx_vc0_buf_pool_N_86909_i_3305), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all_75_), + .Q(com_tlm_u_tlm_tx_vc0_buf_pool_rdata_q_all_75_) + ); + FDE com_tlm_u_tlm_tx_vc0_buf_pool_rdata_reg_1__rdata_q_all_74_ ( + .CE(com_tlm_u_tlm_tx_vc0_buf_pool_N_86909_i_3305), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all_74_), + .Q(com_tlm_u_tlm_tx_vc0_buf_pool_rdata_q_all_74_) + ); + FDE com_tlm_u_tlm_tx_vc0_buf_pool_rdata_reg_1__rdata_q_all_73_ ( + .CE(com_tlm_u_tlm_tx_vc0_buf_pool_N_86909_i_3305), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all_73_), + .Q(com_tlm_u_tlm_tx_vc0_buf_pool_rdata_q_all_73_) + ); + FDE com_tlm_u_tlm_tx_vc0_buf_pool_rdata_reg_1__rdata_q_all_72_ ( + .CE(com_tlm_u_tlm_tx_vc0_buf_pool_N_86909_i_3305), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all_72_), + .Q(com_tlm_u_tlm_tx_vc0_buf_pool_rdata_q_all_72_) + ); + FDE com_tlm_u_tlm_tx_vc0_buf_pool_rdata_q_errfwd ( + .CE(com_tlm_u_tlm_tx_vc0_buf_pool_N_86909_i_3305), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_buf_pool_rdata_errfwd_3306), + .Q(com_tlm_u_tlm_tx_vc0_buf_pool_rdata_q_errfwd_3308) + ); + FDE com_tlm_u_tlm_tx_vc0_buf_pool_cfg_d ( + .CE(com_tlm_u_tlm_tx_vc0_buf_pool_N_55898_i_i_3442), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_buf_pool_N_59264_i_3307), + .Q(com_tlm_u_tlm_tx_vc0_cfg) + ); + FDE com_tlm_u_tlm_tx_vc0_buf_pool_errfwd_d ( + .CE(com_tlm_u_tlm_tx_vc0_buf_pool_N_55898_i_i_3442), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_buf_pool_rdata_q_errfwd_3308), + .Q(com_tlm_u_tlm_tx_vc0_errfwd) + ); + FDE com_tlm_u_tlm_tx_vc0_buf_pool_wdata_66_ ( + .CE(com_tlm_u_tlm_tx_vc0_buf_pool_N_59233_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_trn_sof), + .Q(com_tlm_u_tlm_tx_vc0_buf_pool_wdata_66__3309) + ); + FDE com_tlm_u_tlm_tx_vc0_buf_pool_wdata_65_ ( + .CE(com_tlm_u_tlm_tx_vc0_buf_pool_N_59233_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_trn_eof), + .Q(com_tlm_u_tlm_tx_vc0_buf_pool_wdata_65__3310) + ); + FDE com_tlm_u_tlm_tx_vc0_buf_pool_wdata_64_ ( + .CE(com_tlm_u_tlm_tx_vc0_buf_pool_N_59233_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_trn_cfg), + .Q(com_tlm_u_tlm_tx_vc0_buf_pool_wdata_64__3311) + ); + FDE com_tlm_u_tlm_tx_vc0_buf_pool_wdata_63_ ( + .CE(com_tlm_u_tlm_tx_vc0_buf_pool_N_59233_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_trn_d[63]), + .Q(com_tlm_u_tlm_tx_vc0_buf_pool_wdata_63__3312) + ); + FDE com_tlm_u_tlm_tx_vc0_buf_pool_wdata_62_ ( + .CE(com_tlm_u_tlm_tx_vc0_buf_pool_N_59233_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_trn_d[62]), + .Q(com_tlm_u_tlm_tx_vc0_buf_pool_wdata_62__3313) + ); + FDE com_tlm_u_tlm_tx_vc0_buf_pool_wdata_61_ ( + .CE(com_tlm_u_tlm_tx_vc0_buf_pool_N_59233_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_trn_d[61]), + .Q(com_tlm_u_tlm_tx_vc0_buf_pool_wdata_61__3314) + ); + FDE com_tlm_u_tlm_tx_vc0_buf_pool_wdata_60_ ( + .CE(com_tlm_u_tlm_tx_vc0_buf_pool_N_59233_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_trn_d[60]), + .Q(com_tlm_u_tlm_tx_vc0_buf_pool_wdata_60__3315) + ); + FDE com_tlm_u_tlm_tx_vc0_buf_pool_wdata_59_ ( + .CE(com_tlm_u_tlm_tx_vc0_buf_pool_N_59233_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_trn_d[59]), + .Q(com_tlm_u_tlm_tx_vc0_buf_pool_wdata_59__3316) + ); + FDE com_tlm_u_tlm_tx_vc0_buf_pool_wdata_58_ ( + .CE(com_tlm_u_tlm_tx_vc0_buf_pool_N_59233_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_trn_d[58]), + .Q(com_tlm_u_tlm_tx_vc0_buf_pool_wdata_58__3317) + ); + FDE com_tlm_u_tlm_tx_vc0_buf_pool_wdata_57_ ( + .CE(com_tlm_u_tlm_tx_vc0_buf_pool_N_59233_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_trn_d[57]), + .Q(com_tlm_u_tlm_tx_vc0_buf_pool_wdata_57__3318) + ); + FDE com_tlm_u_tlm_tx_vc0_buf_pool_wdata_56_ ( + .CE(com_tlm_u_tlm_tx_vc0_buf_pool_N_59233_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_trn_d[56]), + .Q(com_tlm_u_tlm_tx_vc0_buf_pool_wdata_56__3319) + ); + FDE com_tlm_u_tlm_tx_vc0_buf_pool_wdata_55_ ( + .CE(com_tlm_u_tlm_tx_vc0_buf_pool_N_59233_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_trn_d[55]), + .Q(com_tlm_u_tlm_tx_vc0_buf_pool_wdata_55__3320) + ); + FDE com_tlm_u_tlm_tx_vc0_buf_pool_wdata_54_ ( + .CE(com_tlm_u_tlm_tx_vc0_buf_pool_N_59233_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_trn_d[54]), + .Q(com_tlm_u_tlm_tx_vc0_buf_pool_wdata_54__3321) + ); + FDE com_tlm_u_tlm_tx_vc0_buf_pool_wdata_53_ ( + .CE(com_tlm_u_tlm_tx_vc0_buf_pool_N_59233_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_trn_d[53]), + .Q(com_tlm_u_tlm_tx_vc0_buf_pool_wdata_53__3322) + ); + FDE com_tlm_u_tlm_tx_vc0_buf_pool_wdata_52_ ( + .CE(com_tlm_u_tlm_tx_vc0_buf_pool_N_59233_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_trn_d[52]), + .Q(com_tlm_u_tlm_tx_vc0_buf_pool_wdata_52__3323) + ); + FDE com_tlm_u_tlm_tx_vc0_buf_pool_wdata_51_ ( + .CE(com_tlm_u_tlm_tx_vc0_buf_pool_N_59233_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_trn_d[51]), + .Q(com_tlm_u_tlm_tx_vc0_buf_pool_wdata_51__3324) + ); + FDE com_tlm_u_tlm_tx_vc0_buf_pool_wdata_50_ ( + .CE(com_tlm_u_tlm_tx_vc0_buf_pool_N_59233_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_trn_d[50]), + .Q(com_tlm_u_tlm_tx_vc0_buf_pool_wdata_50__3325) + ); + FDE com_tlm_u_tlm_tx_vc0_buf_pool_wdata_49_ ( + .CE(com_tlm_u_tlm_tx_vc0_buf_pool_N_59233_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_trn_d[49]), + .Q(com_tlm_u_tlm_tx_vc0_buf_pool_wdata_49__3326) + ); + FDE com_tlm_u_tlm_tx_vc0_buf_pool_wdata_48_ ( + .CE(com_tlm_u_tlm_tx_vc0_buf_pool_N_59233_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_trn_d[48]), + .Q(com_tlm_u_tlm_tx_vc0_buf_pool_wdata_48__3327) + ); + FDE com_tlm_u_tlm_tx_vc0_buf_pool_wdata_47_ ( + .CE(com_tlm_u_tlm_tx_vc0_buf_pool_N_59233_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_trn_d[47]), + .Q(com_tlm_u_tlm_tx_vc0_buf_pool_wdata_47__3328) + ); + FDE com_tlm_u_tlm_tx_vc0_buf_pool_wdata_46_ ( + .CE(com_tlm_u_tlm_tx_vc0_buf_pool_N_59233_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_trn_d[46]), + .Q(com_tlm_u_tlm_tx_vc0_buf_pool_wdata_46__3329) + ); + FDE com_tlm_u_tlm_tx_vc0_buf_pool_wdata_45_ ( + .CE(com_tlm_u_tlm_tx_vc0_buf_pool_N_59233_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_trn_d[45]), + .Q(com_tlm_u_tlm_tx_vc0_buf_pool_wdata_45__3330) + ); + FDE com_tlm_u_tlm_tx_vc0_buf_pool_wdata_44_ ( + .CE(com_tlm_u_tlm_tx_vc0_buf_pool_N_59233_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_trn_d[44]), + .Q(com_tlm_u_tlm_tx_vc0_buf_pool_wdata_44__3331) + ); + FDE com_tlm_u_tlm_tx_vc0_buf_pool_wdata_43_ ( + .CE(com_tlm_u_tlm_tx_vc0_buf_pool_N_59233_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_trn_d[43]), + .Q(com_tlm_u_tlm_tx_vc0_buf_pool_wdata_43__3332) + ); + FDE com_tlm_u_tlm_tx_vc0_buf_pool_wdata_42_ ( + .CE(com_tlm_u_tlm_tx_vc0_buf_pool_N_59233_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_trn_d[42]), + .Q(com_tlm_u_tlm_tx_vc0_buf_pool_wdata_42__3333) + ); + FDE com_tlm_u_tlm_tx_vc0_buf_pool_wdata_41_ ( + .CE(com_tlm_u_tlm_tx_vc0_buf_pool_N_59233_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_trn_d[41]), + .Q(com_tlm_u_tlm_tx_vc0_buf_pool_wdata_41__3334) + ); + FDE com_tlm_u_tlm_tx_vc0_buf_pool_wdata_40_ ( + .CE(com_tlm_u_tlm_tx_vc0_buf_pool_N_59233_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_trn_d[40]), + .Q(com_tlm_u_tlm_tx_vc0_buf_pool_wdata_40__3335) + ); + FDE com_tlm_u_tlm_tx_vc0_buf_pool_wdata_39_ ( + .CE(com_tlm_u_tlm_tx_vc0_buf_pool_N_59233_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_trn_d[39]), + .Q(com_tlm_u_tlm_tx_vc0_buf_pool_wdata_39__3336) + ); + FDE com_tlm_u_tlm_tx_vc0_buf_pool_wdata_38_ ( + .CE(com_tlm_u_tlm_tx_vc0_buf_pool_N_59233_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_trn_d[38]), + .Q(com_tlm_u_tlm_tx_vc0_buf_pool_wdata_38__3337) + ); + FDE com_tlm_u_tlm_tx_vc0_buf_pool_wdata_37_ ( + .CE(com_tlm_u_tlm_tx_vc0_buf_pool_N_59233_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_trn_d[37]), + .Q(com_tlm_u_tlm_tx_vc0_buf_pool_wdata_37__3338) + ); + FDE com_tlm_u_tlm_tx_vc0_buf_pool_wdata_36_ ( + .CE(com_tlm_u_tlm_tx_vc0_buf_pool_N_59233_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_trn_d[36]), + .Q(com_tlm_u_tlm_tx_vc0_buf_pool_wdata_36__3339) + ); + FDE com_tlm_u_tlm_tx_vc0_buf_pool_wdata_35_ ( + .CE(com_tlm_u_tlm_tx_vc0_buf_pool_N_59233_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_trn_d[35]), + .Q(com_tlm_u_tlm_tx_vc0_buf_pool_wdata_35__3340) + ); + FDE com_tlm_u_tlm_tx_vc0_buf_pool_wdata_34_ ( + .CE(com_tlm_u_tlm_tx_vc0_buf_pool_N_59233_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_trn_d[34]), + .Q(com_tlm_u_tlm_tx_vc0_buf_pool_wdata_34__3341) + ); + FDE com_tlm_u_tlm_tx_vc0_buf_pool_wdata_33_ ( + .CE(com_tlm_u_tlm_tx_vc0_buf_pool_N_59233_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_trn_d[33]), + .Q(com_tlm_u_tlm_tx_vc0_buf_pool_wdata_33__3342) + ); + FDE com_tlm_u_tlm_tx_vc0_buf_pool_wdata_32_ ( + .CE(com_tlm_u_tlm_tx_vc0_buf_pool_N_59233_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_trn_d[32]), + .Q(com_tlm_u_tlm_tx_vc0_buf_pool_wdata_32__3343) + ); + FDE com_tlm_u_tlm_tx_vc0_buf_pool_wdata_31_ ( + .CE(com_tlm_u_tlm_tx_vc0_buf_pool_N_59233_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_trn_d[31]), + .Q(com_tlm_u_tlm_tx_vc0_buf_pool_wdata_31__3344) + ); + FDE com_tlm_u_tlm_tx_vc0_buf_pool_wdata_30_ ( + .CE(com_tlm_u_tlm_tx_vc0_buf_pool_N_59233_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_trn_d[30]), + .Q(com_tlm_u_tlm_tx_vc0_buf_pool_wdata_30__3345) + ); + FDE com_tlm_u_tlm_tx_vc0_buf_pool_wdata_29_ ( + .CE(com_tlm_u_tlm_tx_vc0_buf_pool_N_59233_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_trn_d[29]), + .Q(com_tlm_u_tlm_tx_vc0_buf_pool_wdata_29__3346) + ); + FDE com_tlm_u_tlm_tx_vc0_buf_pool_wdata_28_ ( + .CE(com_tlm_u_tlm_tx_vc0_buf_pool_N_59233_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_trn_d[28]), + .Q(com_tlm_u_tlm_tx_vc0_buf_pool_wdata_28__3347) + ); + FDE com_tlm_u_tlm_tx_vc0_buf_pool_wdata_27_ ( + .CE(com_tlm_u_tlm_tx_vc0_buf_pool_N_59233_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_trn_d[27]), + .Q(com_tlm_u_tlm_tx_vc0_buf_pool_wdata_27__3348) + ); + FDE com_tlm_u_tlm_tx_vc0_buf_pool_wdata_26_ ( + .CE(com_tlm_u_tlm_tx_vc0_buf_pool_N_59233_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_trn_d[26]), + .Q(com_tlm_u_tlm_tx_vc0_buf_pool_wdata_26__3349) + ); + FDE com_tlm_u_tlm_tx_vc0_buf_pool_wdata_25_ ( + .CE(com_tlm_u_tlm_tx_vc0_buf_pool_N_59233_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_trn_d[25]), + .Q(com_tlm_u_tlm_tx_vc0_buf_pool_wdata_25__3350) + ); + FDE com_tlm_u_tlm_tx_vc0_buf_pool_wdata_24_ ( + .CE(com_tlm_u_tlm_tx_vc0_buf_pool_N_59233_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_trn_d[24]), + .Q(com_tlm_u_tlm_tx_vc0_buf_pool_wdata_24__3351) + ); + FDE com_tlm_u_tlm_tx_vc0_buf_pool_wdata_23_ ( + .CE(com_tlm_u_tlm_tx_vc0_buf_pool_N_59233_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_trn_d[23]), + .Q(com_tlm_u_tlm_tx_vc0_buf_pool_wdata_23__3352) + ); + FDE com_tlm_u_tlm_tx_vc0_buf_pool_wdata_22_ ( + .CE(com_tlm_u_tlm_tx_vc0_buf_pool_N_59233_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_trn_d[22]), + .Q(com_tlm_u_tlm_tx_vc0_buf_pool_wdata_22__3353) + ); + FDE com_tlm_u_tlm_tx_vc0_buf_pool_wdata_21_ ( + .CE(com_tlm_u_tlm_tx_vc0_buf_pool_N_59233_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_trn_d[21]), + .Q(com_tlm_u_tlm_tx_vc0_buf_pool_wdata_21__3354) + ); + FDE com_tlm_u_tlm_tx_vc0_buf_pool_wdata_20_ ( + .CE(com_tlm_u_tlm_tx_vc0_buf_pool_N_59233_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_trn_d[20]), + .Q(com_tlm_u_tlm_tx_vc0_buf_pool_wdata_20__3355) + ); + FDE com_tlm_u_tlm_tx_vc0_buf_pool_wdata_19_ ( + .CE(com_tlm_u_tlm_tx_vc0_buf_pool_N_59233_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_trn_d[19]), + .Q(com_tlm_u_tlm_tx_vc0_buf_pool_wdata_19__3356) + ); + FDE com_tlm_u_tlm_tx_vc0_buf_pool_wdata_18_ ( + .CE(com_tlm_u_tlm_tx_vc0_buf_pool_N_59233_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_trn_d[18]), + .Q(com_tlm_u_tlm_tx_vc0_buf_pool_wdata_18__3357) + ); + FDE com_tlm_u_tlm_tx_vc0_buf_pool_wdata_17_ ( + .CE(com_tlm_u_tlm_tx_vc0_buf_pool_N_59233_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_trn_d[17]), + .Q(com_tlm_u_tlm_tx_vc0_buf_pool_wdata_17__3358) + ); + FDE com_tlm_u_tlm_tx_vc0_buf_pool_wdata_16_ ( + .CE(com_tlm_u_tlm_tx_vc0_buf_pool_N_59233_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_trn_d[16]), + .Q(com_tlm_u_tlm_tx_vc0_buf_pool_wdata_16__3359) + ); + FDE com_tlm_u_tlm_tx_vc0_buf_pool_wdata_15_ ( + .CE(com_tlm_u_tlm_tx_vc0_buf_pool_N_59233_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_trn_d[15]), + .Q(com_tlm_u_tlm_tx_vc0_buf_pool_wdata_15__3360) + ); + FDE com_tlm_u_tlm_tx_vc0_buf_pool_wdata_14_ ( + .CE(com_tlm_u_tlm_tx_vc0_buf_pool_N_59233_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_trn_d[14]), + .Q(com_tlm_u_tlm_tx_vc0_buf_pool_wdata_14__3361) + ); + FDE com_tlm_u_tlm_tx_vc0_buf_pool_wdata_13_ ( + .CE(com_tlm_u_tlm_tx_vc0_buf_pool_N_59233_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_trn_d[13]), + .Q(com_tlm_u_tlm_tx_vc0_buf_pool_wdata_13__3362) + ); + FDE com_tlm_u_tlm_tx_vc0_buf_pool_wdata_12_ ( + .CE(com_tlm_u_tlm_tx_vc0_buf_pool_N_59233_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_trn_d[12]), + .Q(com_tlm_u_tlm_tx_vc0_buf_pool_wdata_12__3363) + ); + FDE com_tlm_u_tlm_tx_vc0_buf_pool_wdata_11_ ( + .CE(com_tlm_u_tlm_tx_vc0_buf_pool_N_59233_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_trn_d[11]), + .Q(com_tlm_u_tlm_tx_vc0_buf_pool_wdata_11__3364) + ); + FDE com_tlm_u_tlm_tx_vc0_buf_pool_wdata_10_ ( + .CE(com_tlm_u_tlm_tx_vc0_buf_pool_N_59233_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_trn_d[10]), + .Q(com_tlm_u_tlm_tx_vc0_buf_pool_wdata_10__3365) + ); + FDE com_tlm_u_tlm_tx_vc0_buf_pool_wdata_9_ ( + .CE(com_tlm_u_tlm_tx_vc0_buf_pool_N_59233_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_trn_d[9]), + .Q(com_tlm_u_tlm_tx_vc0_buf_pool_wdata_9__3366) + ); + FDE com_tlm_u_tlm_tx_vc0_buf_pool_wdata_8_ ( + .CE(com_tlm_u_tlm_tx_vc0_buf_pool_N_59233_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_trn_d[8]), + .Q(com_tlm_u_tlm_tx_vc0_buf_pool_wdata_8__3367) + ); + FDE com_tlm_u_tlm_tx_vc0_buf_pool_wdata_7_ ( + .CE(com_tlm_u_tlm_tx_vc0_buf_pool_N_59233_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_trn_d[7]), + .Q(com_tlm_u_tlm_tx_vc0_buf_pool_wdata_7__3368) + ); + FDE com_tlm_u_tlm_tx_vc0_buf_pool_wdata_6_ ( + .CE(com_tlm_u_tlm_tx_vc0_buf_pool_N_59233_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_trn_d[6]), + .Q(com_tlm_u_tlm_tx_vc0_buf_pool_wdata_6__3369) + ); + FDE com_tlm_u_tlm_tx_vc0_buf_pool_wdata_5_ ( + .CE(com_tlm_u_tlm_tx_vc0_buf_pool_N_59233_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_trn_d[5]), + .Q(com_tlm_u_tlm_tx_vc0_buf_pool_wdata_5__3370) + ); + FDE com_tlm_u_tlm_tx_vc0_buf_pool_wdata_4_ ( + .CE(com_tlm_u_tlm_tx_vc0_buf_pool_N_59233_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_trn_d[4]), + .Q(com_tlm_u_tlm_tx_vc0_buf_pool_wdata_4__3371) + ); + FDE com_tlm_u_tlm_tx_vc0_buf_pool_wdata_3_ ( + .CE(com_tlm_u_tlm_tx_vc0_buf_pool_N_59233_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_trn_d[3]), + .Q(com_tlm_u_tlm_tx_vc0_buf_pool_wdata_3__3372) + ); + FDE com_tlm_u_tlm_tx_vc0_buf_pool_wdata_2_ ( + .CE(com_tlm_u_tlm_tx_vc0_buf_pool_N_59233_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_trn_d[2]), + .Q(com_tlm_u_tlm_tx_vc0_buf_pool_wdata_2__3373) + ); + FDE com_tlm_u_tlm_tx_vc0_buf_pool_wdata_1_ ( + .CE(com_tlm_u_tlm_tx_vc0_buf_pool_N_59233_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_trn_d[1]), + .Q(com_tlm_u_tlm_tx_vc0_buf_pool_wdata_1__3374) + ); + FDE com_tlm_u_tlm_tx_vc0_buf_pool_wdata_0_ ( + .CE(com_tlm_u_tlm_tx_vc0_buf_pool_N_59233_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_trn_d[0]), + .Q(com_tlm_u_tlm_tx_vc0_buf_pool_wdata_0__3375) + ); + FDE com_tlm_u_tlm_tx_vc0_buf_pool_write_rem_wdata_68_ ( + .CE(com_tlm_u_tlm_tx_vc0_buf_pool_N_59233_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_trn_rem_i), + .Q(com_tlm_u_tlm_tx_vc0_buf_pool_wdata_68_) + ); + FDE com_tlm_u_tlm_tx_vc0_buf_pool_d_d_63_ ( + .CE(com_tlm_u_tlm_tx_vc0_buf_pool_N_55898_i_i_3442), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_buf_pool_N_59265_i_3376), + .Q(com_tlm_u_tlm_tx_vc0_d[63]) + ); + FDE com_tlm_u_tlm_tx_vc0_buf_pool_d_d_62_ ( + .CE(com_tlm_u_tlm_tx_vc0_buf_pool_N_55898_i_i_3442), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_buf_pool_N_59266_i_3377), + .Q(com_tlm_u_tlm_tx_vc0_d[62]) + ); + FDE com_tlm_u_tlm_tx_vc0_buf_pool_d_d_61_ ( + .CE(com_tlm_u_tlm_tx_vc0_buf_pool_N_55898_i_i_3442), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_buf_pool_N_59267_i_3378), + .Q(com_tlm_u_tlm_tx_vc0_d[61]) + ); + FDE com_tlm_u_tlm_tx_vc0_buf_pool_d_d_60_ ( + .CE(com_tlm_u_tlm_tx_vc0_buf_pool_N_55898_i_i_3442), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_buf_pool_N_59268_i_3379), + .Q(com_tlm_u_tlm_tx_vc0_d[60]) + ); + FDE com_tlm_u_tlm_tx_vc0_buf_pool_d_d_59_ ( + .CE(com_tlm_u_tlm_tx_vc0_buf_pool_N_55898_i_i_3442), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_buf_pool_N_59269_i_3380), + .Q(com_tlm_u_tlm_tx_vc0_d[59]) + ); + FDE com_tlm_u_tlm_tx_vc0_buf_pool_d_d_58_ ( + .CE(com_tlm_u_tlm_tx_vc0_buf_pool_N_55898_i_i_3442), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_buf_pool_N_59270_i_3381), + .Q(com_tlm_u_tlm_tx_vc0_d[58]) + ); + FDE com_tlm_u_tlm_tx_vc0_buf_pool_d_d_57_ ( + .CE(com_tlm_u_tlm_tx_vc0_buf_pool_N_55898_i_i_3442), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_buf_pool_N_59271_i_3382), + .Q(com_tlm_u_tlm_tx_vc0_d[57]) + ); + FDE com_tlm_u_tlm_tx_vc0_buf_pool_d_d_56_ ( + .CE(com_tlm_u_tlm_tx_vc0_buf_pool_N_55898_i_i_3442), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_buf_pool_N_59272_i_3383), + .Q(com_tlm_u_tlm_tx_vc0_d[56]) + ); + FDE com_tlm_u_tlm_tx_vc0_buf_pool_d_d_55_ ( + .CE(com_tlm_u_tlm_tx_vc0_buf_pool_N_55898_i_i_3442), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_buf_pool_N_59273_i_3384), + .Q(com_tlm_u_tlm_tx_vc0_d[55]) + ); + FDE com_tlm_u_tlm_tx_vc0_buf_pool_d_d_54_ ( + .CE(com_tlm_u_tlm_tx_vc0_buf_pool_N_55898_i_i_3442), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_buf_pool_N_59274_i_3385), + .Q(com_tlm_u_tlm_tx_vc0_d[54]) + ); + FDE com_tlm_u_tlm_tx_vc0_buf_pool_d_d_53_ ( + .CE(com_tlm_u_tlm_tx_vc0_buf_pool_N_55898_i_i_3442), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_buf_pool_N_59275_i_3386), + .Q(com_tlm_u_tlm_tx_vc0_d[53]) + ); + FDE com_tlm_u_tlm_tx_vc0_buf_pool_d_d_52_ ( + .CE(com_tlm_u_tlm_tx_vc0_buf_pool_N_55898_i_i_3442), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_buf_pool_N_59276_i_3387), + .Q(com_tlm_u_tlm_tx_vc0_d[52]) + ); + FDE com_tlm_u_tlm_tx_vc0_buf_pool_d_d_51_ ( + .CE(com_tlm_u_tlm_tx_vc0_buf_pool_N_55898_i_i_3442), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_buf_pool_N_59277_i_3388), + .Q(com_tlm_u_tlm_tx_vc0_d[51]) + ); + FDE com_tlm_u_tlm_tx_vc0_buf_pool_d_d_50_ ( + .CE(com_tlm_u_tlm_tx_vc0_buf_pool_N_55898_i_i_3442), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_buf_pool_N_59278_i_3389), + .Q(com_tlm_u_tlm_tx_vc0_d[50]) + ); + FDE com_tlm_u_tlm_tx_vc0_buf_pool_d_d_49_ ( + .CE(com_tlm_u_tlm_tx_vc0_buf_pool_N_55898_i_i_3442), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_buf_pool_N_59279_i_3390), + .Q(com_tlm_u_tlm_tx_vc0_d[49]) + ); + FDE com_tlm_u_tlm_tx_vc0_buf_pool_d_d_48_ ( + .CE(com_tlm_u_tlm_tx_vc0_buf_pool_N_55898_i_i_3442), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_buf_pool_N_59280_i_3391), + .Q(com_tlm_u_tlm_tx_vc0_d[48]) + ); + FDE com_tlm_u_tlm_tx_vc0_buf_pool_d_d_47_ ( + .CE(com_tlm_u_tlm_tx_vc0_buf_pool_N_55898_i_i_3442), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_buf_pool_N_59281_i_3392), + .Q(com_tlm_u_tlm_tx_vc0_d[47]) + ); + FDE com_tlm_u_tlm_tx_vc0_buf_pool_d_d_46_ ( + .CE(com_tlm_u_tlm_tx_vc0_buf_pool_N_55898_i_i_3442), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_buf_pool_N_59282_i_3393), + .Q(com_tlm_u_tlm_tx_vc0_d[46]) + ); + FDE com_tlm_u_tlm_tx_vc0_buf_pool_d_d_45_ ( + .CE(com_tlm_u_tlm_tx_vc0_buf_pool_N_55898_i_i_3442), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_buf_pool_N_59283_i_3394), + .Q(com_tlm_u_tlm_tx_vc0_d[45]) + ); + FDE com_tlm_u_tlm_tx_vc0_buf_pool_d_d_44_ ( + .CE(com_tlm_u_tlm_tx_vc0_buf_pool_N_55898_i_i_3442), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_buf_pool_N_59284_i_3395), + .Q(com_tlm_u_tlm_tx_vc0_d[44]) + ); + FDE com_tlm_u_tlm_tx_vc0_buf_pool_d_d_43_ ( + .CE(com_tlm_u_tlm_tx_vc0_buf_pool_N_55898_i_i_3442), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_buf_pool_N_59285_i_3396), + .Q(com_tlm_u_tlm_tx_vc0_d[43]) + ); + FDE com_tlm_u_tlm_tx_vc0_buf_pool_d_d_42_ ( + .CE(com_tlm_u_tlm_tx_vc0_buf_pool_N_55898_i_i_3442), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_buf_pool_N_59286_i_3397), + .Q(com_tlm_u_tlm_tx_vc0_d[42]) + ); + FDE com_tlm_u_tlm_tx_vc0_buf_pool_d_d_41_ ( + .CE(com_tlm_u_tlm_tx_vc0_buf_pool_N_55898_i_i_3442), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_buf_pool_N_59287_i_3398), + .Q(com_tlm_u_tlm_tx_vc0_d[41]) + ); + FDE com_tlm_u_tlm_tx_vc0_buf_pool_d_d_40_ ( + .CE(com_tlm_u_tlm_tx_vc0_buf_pool_N_55898_i_i_3442), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_buf_pool_N_59288_i_3399), + .Q(com_tlm_u_tlm_tx_vc0_d[40]) + ); + FDE com_tlm_u_tlm_tx_vc0_buf_pool_d_d_39_ ( + .CE(com_tlm_u_tlm_tx_vc0_buf_pool_N_55898_i_i_3442), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_buf_pool_N_59289_i_3400), + .Q(com_tlm_u_tlm_tx_vc0_d[39]) + ); + FDE com_tlm_u_tlm_tx_vc0_buf_pool_d_d_38_ ( + .CE(com_tlm_u_tlm_tx_vc0_buf_pool_N_55898_i_i_3442), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_buf_pool_N_59290_i_3401), + .Q(com_tlm_u_tlm_tx_vc0_d[38]) + ); + FDE com_tlm_u_tlm_tx_vc0_buf_pool_d_d_37_ ( + .CE(com_tlm_u_tlm_tx_vc0_buf_pool_N_55898_i_i_3442), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_buf_pool_N_59291_i_3402), + .Q(com_tlm_u_tlm_tx_vc0_d[37]) + ); + FDE com_tlm_u_tlm_tx_vc0_buf_pool_d_d_36_ ( + .CE(com_tlm_u_tlm_tx_vc0_buf_pool_N_55898_i_i_3442), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_buf_pool_N_59292_i_3403), + .Q(com_tlm_u_tlm_tx_vc0_d[36]) + ); + FDE com_tlm_u_tlm_tx_vc0_buf_pool_d_d_35_ ( + .CE(com_tlm_u_tlm_tx_vc0_buf_pool_N_55898_i_i_3442), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_buf_pool_N_59293_i_3404), + .Q(com_tlm_u_tlm_tx_vc0_d[35]) + ); + FDE com_tlm_u_tlm_tx_vc0_buf_pool_d_d_34_ ( + .CE(com_tlm_u_tlm_tx_vc0_buf_pool_N_55898_i_i_3442), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_buf_pool_N_59294_i_3405), + .Q(com_tlm_u_tlm_tx_vc0_d[34]) + ); + FDE com_tlm_u_tlm_tx_vc0_buf_pool_d_d_33_ ( + .CE(com_tlm_u_tlm_tx_vc0_buf_pool_N_55898_i_i_3442), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_buf_pool_N_59295_i_3406), + .Q(com_tlm_u_tlm_tx_vc0_d[33]) + ); + FDE com_tlm_u_tlm_tx_vc0_buf_pool_d_d_32_ ( + .CE(com_tlm_u_tlm_tx_vc0_buf_pool_N_55898_i_i_3442), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_buf_pool_N_59296_i_3407), + .Q(com_tlm_u_tlm_tx_vc0_d[32]) + ); + FDE com_tlm_u_tlm_tx_vc0_buf_pool_d_d_31_ ( + .CE(com_tlm_u_tlm_tx_vc0_buf_pool_N_55898_i_i_3442), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_buf_pool_N_59297_i_3408), + .Q(com_tlm_u_tlm_tx_vc0_d[31]) + ); + FDE com_tlm_u_tlm_tx_vc0_buf_pool_d_d_30_ ( + .CE(com_tlm_u_tlm_tx_vc0_buf_pool_N_55898_i_i_3442), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_buf_pool_N_59298_i_3409), + .Q(com_tlm_u_tlm_tx_vc0_d[30]) + ); + FDE com_tlm_u_tlm_tx_vc0_buf_pool_d_d_29_ ( + .CE(com_tlm_u_tlm_tx_vc0_buf_pool_N_55898_i_i_3442), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_buf_pool_N_59299_i_3410), + .Q(com_tlm_u_tlm_tx_vc0_d[29]) + ); + FDE com_tlm_u_tlm_tx_vc0_buf_pool_d_d_28_ ( + .CE(com_tlm_u_tlm_tx_vc0_buf_pool_N_55898_i_i_3442), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_buf_pool_N_59300_i_3411), + .Q(com_tlm_u_tlm_tx_vc0_d[28]) + ); + FDE com_tlm_u_tlm_tx_vc0_buf_pool_d_d_27_ ( + .CE(com_tlm_u_tlm_tx_vc0_buf_pool_N_55898_i_i_3442), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_buf_pool_N_59301_i_3412), + .Q(com_tlm_u_tlm_tx_vc0_d[27]) + ); + FDE com_tlm_u_tlm_tx_vc0_buf_pool_d_d_26_ ( + .CE(com_tlm_u_tlm_tx_vc0_buf_pool_N_55898_i_i_3442), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_buf_pool_N_59302_i_3413), + .Q(com_tlm_u_tlm_tx_vc0_d[26]) + ); + FDE com_tlm_u_tlm_tx_vc0_buf_pool_d_d_25_ ( + .CE(com_tlm_u_tlm_tx_vc0_buf_pool_N_55898_i_i_3442), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_buf_pool_N_59303_i_3414), + .Q(com_tlm_u_tlm_tx_vc0_d[25]) + ); + FDE com_tlm_u_tlm_tx_vc0_buf_pool_d_d_24_ ( + .CE(com_tlm_u_tlm_tx_vc0_buf_pool_N_55898_i_i_3442), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_buf_pool_N_59304_i_3415), + .Q(com_tlm_u_tlm_tx_vc0_d[24]) + ); + FDE com_tlm_u_tlm_tx_vc0_buf_pool_d_d_23_ ( + .CE(com_tlm_u_tlm_tx_vc0_buf_pool_N_55898_i_i_3442), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_buf_pool_N_59305_i_3416), + .Q(com_tlm_u_tlm_tx_vc0_d[23]) + ); + FDE com_tlm_u_tlm_tx_vc0_buf_pool_d_d_22_ ( + .CE(com_tlm_u_tlm_tx_vc0_buf_pool_N_55898_i_i_3442), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_buf_pool_N_59306_i_3417), + .Q(com_tlm_u_tlm_tx_vc0_d[22]) + ); + FDE com_tlm_u_tlm_tx_vc0_buf_pool_d_d_21_ ( + .CE(com_tlm_u_tlm_tx_vc0_buf_pool_N_55898_i_i_3442), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_buf_pool_N_59307_i_3418), + .Q(com_tlm_u_tlm_tx_vc0_d[21]) + ); + FDE com_tlm_u_tlm_tx_vc0_buf_pool_d_d_20_ ( + .CE(com_tlm_u_tlm_tx_vc0_buf_pool_N_55898_i_i_3442), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_buf_pool_N_59308_i_3419), + .Q(com_tlm_u_tlm_tx_vc0_d[20]) + ); + FDE com_tlm_u_tlm_tx_vc0_buf_pool_d_d_19_ ( + .CE(com_tlm_u_tlm_tx_vc0_buf_pool_N_55898_i_i_3442), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_buf_pool_N_59309_i_3420), + .Q(com_tlm_u_tlm_tx_vc0_d[19]) + ); + FDE com_tlm_u_tlm_tx_vc0_buf_pool_d_d_18_ ( + .CE(com_tlm_u_tlm_tx_vc0_buf_pool_N_55898_i_i_3442), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_buf_pool_N_59310_i_3421), + .Q(com_tlm_u_tlm_tx_vc0_d[18]) + ); + FDE com_tlm_u_tlm_tx_vc0_buf_pool_d_d_17_ ( + .CE(com_tlm_u_tlm_tx_vc0_buf_pool_N_55898_i_i_3442), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_buf_pool_N_59311_i_3422), + .Q(com_tlm_u_tlm_tx_vc0_d[17]) + ); + FDE com_tlm_u_tlm_tx_vc0_buf_pool_d_d_16_ ( + .CE(com_tlm_u_tlm_tx_vc0_buf_pool_N_55898_i_i_3442), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_buf_pool_N_59312_i_3423), + .Q(com_tlm_u_tlm_tx_vc0_d[16]) + ); + FDE com_tlm_u_tlm_tx_vc0_buf_pool_d_d_15_ ( + .CE(com_tlm_u_tlm_tx_vc0_buf_pool_N_55898_i_i_3442), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_buf_pool_N_59313_i_3424), + .Q(com_tlm_u_tlm_tx_vc0_d[15]) + ); + FDE com_tlm_u_tlm_tx_vc0_buf_pool_d_d_14_ ( + .CE(com_tlm_u_tlm_tx_vc0_buf_pool_N_55898_i_i_3442), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_buf_pool_N_59314_i_3425), + .Q(com_tlm_u_tlm_tx_vc0_d[14]) + ); + FDE com_tlm_u_tlm_tx_vc0_buf_pool_d_d_13_ ( + .CE(com_tlm_u_tlm_tx_vc0_buf_pool_N_55898_i_i_3442), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_buf_pool_N_59315_i_3426), + .Q(com_tlm_u_tlm_tx_vc0_d[13]) + ); + FDE com_tlm_u_tlm_tx_vc0_buf_pool_d_d_12_ ( + .CE(com_tlm_u_tlm_tx_vc0_buf_pool_N_55898_i_i_3442), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_buf_pool_N_59316_i_3427), + .Q(com_tlm_u_tlm_tx_vc0_d[12]) + ); + FDE com_tlm_u_tlm_tx_vc0_buf_pool_d_d_11_ ( + .CE(com_tlm_u_tlm_tx_vc0_buf_pool_N_55898_i_i_3442), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_buf_pool_N_59317_i_3428), + .Q(com_tlm_u_tlm_tx_vc0_d[11]) + ); + FDE com_tlm_u_tlm_tx_vc0_buf_pool_d_d_10_ ( + .CE(com_tlm_u_tlm_tx_vc0_buf_pool_N_55898_i_i_3442), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_buf_pool_N_59318_i_3429), + .Q(com_tlm_u_tlm_tx_vc0_d[10]) + ); + FDE com_tlm_u_tlm_tx_vc0_buf_pool_d_d_9_ ( + .CE(com_tlm_u_tlm_tx_vc0_buf_pool_N_55898_i_i_3442), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_buf_pool_N_59319_i_3430), + .Q(com_tlm_u_tlm_tx_vc0_d[9]) + ); + FDE com_tlm_u_tlm_tx_vc0_buf_pool_d_d_8_ ( + .CE(com_tlm_u_tlm_tx_vc0_buf_pool_N_55898_i_i_3442), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_buf_pool_N_59320_i_3431), + .Q(com_tlm_u_tlm_tx_vc0_d[8]) + ); + FDE com_tlm_u_tlm_tx_vc0_buf_pool_d_d_7_ ( + .CE(com_tlm_u_tlm_tx_vc0_buf_pool_N_55898_i_i_3442), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_buf_pool_N_59321_i_3432), + .Q(com_tlm_u_tlm_tx_vc0_d[7]) + ); + FDE com_tlm_u_tlm_tx_vc0_buf_pool_d_d_6_ ( + .CE(com_tlm_u_tlm_tx_vc0_buf_pool_N_55898_i_i_3442), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_buf_pool_N_59322_i_3433), + .Q(com_tlm_u_tlm_tx_vc0_d[6]) + ); + FDE com_tlm_u_tlm_tx_vc0_buf_pool_d_d_5_ ( + .CE(com_tlm_u_tlm_tx_vc0_buf_pool_N_55898_i_i_3442), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_buf_pool_N_59323_i_3434), + .Q(com_tlm_u_tlm_tx_vc0_d[5]) + ); + FDE com_tlm_u_tlm_tx_vc0_buf_pool_d_d_4_ ( + .CE(com_tlm_u_tlm_tx_vc0_buf_pool_N_55898_i_i_3442), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_buf_pool_N_59324_i_3435), + .Q(com_tlm_u_tlm_tx_vc0_d[4]) + ); + FDE com_tlm_u_tlm_tx_vc0_buf_pool_d_d_3_ ( + .CE(com_tlm_u_tlm_tx_vc0_buf_pool_N_55898_i_i_3442), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_buf_pool_N_59325_i_3436), + .Q(com_tlm_u_tlm_tx_vc0_d[3]) + ); + FDE com_tlm_u_tlm_tx_vc0_buf_pool_d_d_2_ ( + .CE(com_tlm_u_tlm_tx_vc0_buf_pool_N_55898_i_i_3442), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_buf_pool_N_59326_i_3437), + .Q(com_tlm_u_tlm_tx_vc0_d[2]) + ); + FDE com_tlm_u_tlm_tx_vc0_buf_pool_d_d_1_ ( + .CE(com_tlm_u_tlm_tx_vc0_buf_pool_N_55898_i_i_3442), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_buf_pool_N_59327_i_3438), + .Q(com_tlm_u_tlm_tx_vc0_d[1]) + ); + FDE com_tlm_u_tlm_tx_vc0_buf_pool_d_d_0_ ( + .CE(com_tlm_u_tlm_tx_vc0_buf_pool_N_55898_i_i_3442), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_buf_pool_N_59182_i_3439), + .Q(com_tlm_u_tlm_tx_vc0_d[0]) + ); + FDE com_tlm_u_tlm_tx_vc0_buf_pool_wdata_errfwd ( + .CE(com_tlm_u_tlm_tx_vc0_trn_vld), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_buf_pool_N_86423_i_3440), + .Q(com_tlm_u_tlm_tx_vc0_buf_pool_wdata_errfwd_3441) + ); + FDE com_tlm_u_tlm_tx_vc0_buf_pool_buf_num_d_3_ ( + .CE(com_tlm_u_tlm_tx_vc0_buf_pool_N_56080_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_buf_pool_raddr_h_q[3]), + .Q(com_tlm_u_tlm_tx_vc0_buf_num[3]) + ); + FDE com_tlm_u_tlm_tx_vc0_buf_pool_buf_num_d_2_ ( + .CE(com_tlm_u_tlm_tx_vc0_buf_pool_N_56080_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_buf_pool_raddr_h_q[2]), + .Q(com_tlm_u_tlm_tx_vc0_buf_num[2]) + ); + FDE com_tlm_u_tlm_tx_vc0_buf_pool_buf_num_d_1_ ( + .CE(com_tlm_u_tlm_tx_vc0_buf_pool_N_56080_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_buf_pool_raddr_h_q[1]), + .Q(com_tlm_u_tlm_tx_vc0_buf_num[1]) + ); + FDE com_tlm_u_tlm_tx_vc0_buf_pool_buf_num_d_0_ ( + .CE(com_tlm_u_tlm_tx_vc0_buf_pool_N_56080_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_buf_pool_raddr_h_q[0]), + .Q(com_tlm_u_tlm_tx_vc0_buf_num[0]) + ); + FDE com_tlm_u_tlm_tx_vc0_buf_pool_raddr_h_q_3_ ( + .CE(com_tlm_u_tlm_tx_vc0_buf_pool_en_ram_i_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_buf_pool_raddr_h[3]), + .Q(com_tlm_u_tlm_tx_vc0_buf_pool_raddr_h_q[3]) + ); + FDE com_tlm_u_tlm_tx_vc0_buf_pool_raddr_h_q_2_ ( + .CE(com_tlm_u_tlm_tx_vc0_buf_pool_en_ram_i_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_buf_pool_raddr_h[2]), + .Q(com_tlm_u_tlm_tx_vc0_buf_pool_raddr_h_q[2]) + ); + FDE com_tlm_u_tlm_tx_vc0_buf_pool_raddr_h_q_1_ ( + .CE(com_tlm_u_tlm_tx_vc0_buf_pool_en_ram_i_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_buf_pool_raddr_h[1]), + .Q(com_tlm_u_tlm_tx_vc0_buf_pool_raddr_h_q[1]) + ); + FDE com_tlm_u_tlm_tx_vc0_buf_pool_raddr_h_q_0_ ( + .CE(com_tlm_u_tlm_tx_vc0_buf_pool_en_ram_i_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_buf_pool_raddr_h[0]), + .Q(com_tlm_u_tlm_tx_vc0_buf_pool_raddr_h_q[0]) + ); + INV com_tlm_u_tlm_tx_vc0_buf_pool_N_55898_i_i ( + .I(com_tlm_u_tlm_tx_vc0_buf_pool_N_55898_i), + .O(com_tlm_u_tlm_tx_vc0_buf_pool_N_55898_i_i_3442) + ); + defparam com_tlm_u_tlm_tx_vc0_buf_pool_raddr_l_qxu_0_0_.INIT = 4'h2; + LUT1_L com_tlm_u_tlm_tx_vc0_buf_pool_raddr_l_qxu_0_0_ ( + .I0(com_tlm_u_tlm_tx_vc0_buf_pool_raddr_l[0]), + .LO(com_tlm_u_tlm_tx_vc0_buf_pool_raddr_l_qxu[0]) + ); + defparam com_tlm_u_tlm_tx_vc0_buf_pool_un5_waddr_l_0_a2_0_a2_0_a2_0_.INIT = 4'h1; + LUT2_L com_tlm_u_tlm_tx_vc0_buf_pool_un5_waddr_l_0_a2_0_a2_0_a2_0_ ( + .I0(com_tlm_u_tlm_tx_vc0_buf_pool_waddr_l[0]), + .I1(com_tlm_u_tlm_tx_vc0_trn_sof), + .LO(com_tlm_u_tlm_tx_vc0_buf_pool_waddr_l_1[0]) + ); + defparam com_tlm_u_tlm_tx_vc0_buf_pool_raddr_l_qxu_0_6_.INIT = 4'h2; + LUT1_L com_tlm_u_tlm_tx_vc0_buf_pool_raddr_l_qxu_0_6_ ( + .I0(com_tlm_u_tlm_tx_vc0_buf_pool_raddr_l[6]), + .LO(com_tlm_u_tlm_tx_vc0_buf_pool_raddr_l_qxu[6]) + ); + defparam com_tlm_u_tlm_tx_vc0_buf_pool_raddr_l_qxu_0_5_.INIT = 4'h2; + LUT1_L com_tlm_u_tlm_tx_vc0_buf_pool_raddr_l_qxu_0_5_ ( + .I0(com_tlm_u_tlm_tx_vc0_buf_pool_raddr_l[5]), + .LO(com_tlm_u_tlm_tx_vc0_buf_pool_raddr_l_qxu[5]) + ); + defparam com_tlm_u_tlm_tx_vc0_buf_pool_raddr_l_qxu_0_4_.INIT = 4'h2; + LUT1_L com_tlm_u_tlm_tx_vc0_buf_pool_raddr_l_qxu_0_4_ ( + .I0(com_tlm_u_tlm_tx_vc0_buf_pool_raddr_l[4]), + .LO(com_tlm_u_tlm_tx_vc0_buf_pool_raddr_l_qxu[4]) + ); + defparam com_tlm_u_tlm_tx_vc0_buf_pool_raddr_l_qxu_0_3_.INIT = 4'h2; + LUT1_L com_tlm_u_tlm_tx_vc0_buf_pool_raddr_l_qxu_0_3_ ( + .I0(com_tlm_u_tlm_tx_vc0_buf_pool_raddr_l[3]), + .LO(com_tlm_u_tlm_tx_vc0_buf_pool_raddr_l_qxu[3]) + ); + defparam com_tlm_u_tlm_tx_vc0_buf_pool_raddr_l_qxu_0_2_.INIT = 4'h2; + LUT1_L com_tlm_u_tlm_tx_vc0_buf_pool_raddr_l_qxu_0_2_ ( + .I0(com_tlm_u_tlm_tx_vc0_buf_pool_raddr_l[2]), + .LO(com_tlm_u_tlm_tx_vc0_buf_pool_raddr_l_qxu[2]) + ); + defparam com_tlm_u_tlm_tx_vc0_buf_pool_raddr_l_qxu_0_1_.INIT = 4'h2; + LUT1_L com_tlm_u_tlm_tx_vc0_buf_pool_raddr_l_qxu_0_1_ ( + .I0(com_tlm_u_tlm_tx_vc0_buf_pool_raddr_l[1]), + .LO(com_tlm_u_tlm_tx_vc0_buf_pool_raddr_l_qxu[1]) + ); + defparam com_tlm_u_tlm_tx_vc0_buf_pool_raddr_l_s_0_.INIT = 4'h1; + LUT1_L com_tlm_u_tlm_tx_vc0_buf_pool_raddr_l_s_0_ ( + .I0(com_tlm_u_tlm_tx_vc0_buf_pool_raddr_l_qxu[0]), + .LO(com_tlm_u_tlm_tx_vc0_buf_pool_raddr_l_s[0]) + ); + defparam com_tlm_u_tlm_tx_vc0_buf_pool_waddr_l_1_axb_0.INIT = 4'hE; + LUT2 com_tlm_u_tlm_tx_vc0_buf_pool_waddr_l_1_axb_0 ( + .I0(com_tlm_u_tlm_tx_vc0_buf_pool_waddr_l[0]), + .I1(com_tlm_u_tlm_tx_vc0_trn_sof), + .O(com_tlm_u_tlm_tx_vc0_buf_pool_waddr_l_1_axb_0_3443) + ); + GND com_tlm_u_tlm_tx_vc0_buf_pool_srl_retry_retry_fifo_GND ( + .G(com_tlm_u_tlm_tx_vc0_buf_pool_srl_retry_retry_fifo_GND_3444) + ); + SRLC16E com_tlm_u_tlm_tx_vc0_buf_pool_srl_retry_retry_fifo_srlrow_0__srlcol_0__srlinst ( + .CE(com_tlm_u_tlm_tx_vc0_N_55858_i), + .D(com_tlm_u_tlm_tx_vc0_start_retry_tsn[0]), + .Q(com_tlm_u_tlm_tx_vc0_buf_pool_srl_retry_retry_fifo_shift_tap[0]), + .CLK(NlwRenamedSig_OI_trn_clk), + .Q15(NLW_com_tlm_u_tlm_tx_vc0_buf_pool_srl_retry_retry_fifo_srlrow_0__srlcol_0__srlinst_Q15_UNCONNECTED), + .A0(com_tlm_u_tlm_tx_vc0_buf_pool_srl_retry_retry_fifo_raddr_lo[0]), + .A1(com_tlm_u_tlm_tx_vc0_buf_pool_srl_retry_retry_fifo_GND_3444), + .A2(com_tlm_u_tlm_tx_vc0_buf_pool_srl_retry_retry_fifo_GND_3444), + .A3(com_tlm_u_tlm_tx_vc0_buf_pool_srl_retry_retry_fifo_GND_3444) + ); + SRLC16E com_tlm_u_tlm_tx_vc0_buf_pool_srl_retry_retry_fifo_srlrow_0__srlcol_9__srlinst ( + .CE(com_tlm_u_tlm_tx_vc0_N_55858_i), + .D(com_tlm_u_tlm_tx_vc0_start_retry_tsn[9]), + .Q(com_tlm_u_tlm_tx_vc0_buf_pool_srl_retry_retry_fifo_shift_tap[9]), + .CLK(NlwRenamedSig_OI_trn_clk), + .Q15(NLW_com_tlm_u_tlm_tx_vc0_buf_pool_srl_retry_retry_fifo_srlrow_0__srlcol_9__srlinst_Q15_UNCONNECTED), + .A0(com_tlm_u_tlm_tx_vc0_buf_pool_srl_retry_retry_fifo_raddr_lo[0]), + .A1(com_tlm_u_tlm_tx_vc0_buf_pool_srl_retry_retry_fifo_GND_3444), + .A2(com_tlm_u_tlm_tx_vc0_buf_pool_srl_retry_retry_fifo_GND_3444), + .A3(com_tlm_u_tlm_tx_vc0_buf_pool_srl_retry_retry_fifo_GND_3444) + ); + SRLC16E com_tlm_u_tlm_tx_vc0_buf_pool_srl_retry_retry_fifo_srlrow_0__srlcol_5__srlinst ( + .CE(com_tlm_u_tlm_tx_vc0_N_55858_i), + .D(com_tlm_u_tlm_tx_vc0_start_retry_tsn[5]), + .Q(com_tlm_u_tlm_tx_vc0_buf_pool_srl_retry_retry_fifo_shift_tap[5]), + .CLK(NlwRenamedSig_OI_trn_clk), + .Q15(NLW_com_tlm_u_tlm_tx_vc0_buf_pool_srl_retry_retry_fifo_srlrow_0__srlcol_5__srlinst_Q15_UNCONNECTED), + .A0(com_tlm_u_tlm_tx_vc0_buf_pool_srl_retry_retry_fifo_raddr_lo[0]), + .A1(com_tlm_u_tlm_tx_vc0_buf_pool_srl_retry_retry_fifo_GND_3444), + .A2(com_tlm_u_tlm_tx_vc0_buf_pool_srl_retry_retry_fifo_GND_3444), + .A3(com_tlm_u_tlm_tx_vc0_buf_pool_srl_retry_retry_fifo_GND_3444) + ); + SRLC16E com_tlm_u_tlm_tx_vc0_buf_pool_srl_retry_retry_fifo_srlrow_0__srlcol_1__srlinst ( + .CE(com_tlm_u_tlm_tx_vc0_N_55858_i), + .D(com_tlm_u_tlm_tx_vc0_start_retry_tsn[1]), + .Q(com_tlm_u_tlm_tx_vc0_buf_pool_srl_retry_retry_fifo_shift_tap[1]), + .CLK(NlwRenamedSig_OI_trn_clk), + .Q15(NLW_com_tlm_u_tlm_tx_vc0_buf_pool_srl_retry_retry_fifo_srlrow_0__srlcol_1__srlinst_Q15_UNCONNECTED), + .A0(com_tlm_u_tlm_tx_vc0_buf_pool_srl_retry_retry_fifo_raddr_lo[0]), + .A1(com_tlm_u_tlm_tx_vc0_buf_pool_srl_retry_retry_fifo_GND_3444), + .A2(com_tlm_u_tlm_tx_vc0_buf_pool_srl_retry_retry_fifo_GND_3444), + .A3(com_tlm_u_tlm_tx_vc0_buf_pool_srl_retry_retry_fifo_GND_3444) + ); + SRLC16E com_tlm_u_tlm_tx_vc0_buf_pool_srl_retry_retry_fifo_srlrow_0__srlcol_10__srlinst ( + .CE(com_tlm_u_tlm_tx_vc0_N_55858_i), + .D(com_tlm_u_tlm_tx_vc0_start_retry_tsn[10]), + .Q(com_tlm_u_tlm_tx_vc0_buf_pool_srl_retry_retry_fifo_shift_tap[10]), + .CLK(NlwRenamedSig_OI_trn_clk), + .Q15(NLW_com_tlm_u_tlm_tx_vc0_buf_pool_srl_retry_retry_fifo_srlrow_0__srlcol_10__srlinst_Q15_UNCONNECTED), + .A0(com_tlm_u_tlm_tx_vc0_buf_pool_srl_retry_retry_fifo_raddr_lo[0]), + .A1(com_tlm_u_tlm_tx_vc0_buf_pool_srl_retry_retry_fifo_GND_3444), + .A2(com_tlm_u_tlm_tx_vc0_buf_pool_srl_retry_retry_fifo_GND_3444), + .A3(com_tlm_u_tlm_tx_vc0_buf_pool_srl_retry_retry_fifo_GND_3444) + ); + SRLC16E com_tlm_u_tlm_tx_vc0_buf_pool_srl_retry_retry_fifo_srlrow_0__srlcol_6__srlinst ( + .CE(com_tlm_u_tlm_tx_vc0_N_55858_i), + .D(com_tlm_u_tlm_tx_vc0_start_retry_tsn[6]), + .Q(com_tlm_u_tlm_tx_vc0_buf_pool_srl_retry_retry_fifo_shift_tap[6]), + .CLK(NlwRenamedSig_OI_trn_clk), + .Q15(NLW_com_tlm_u_tlm_tx_vc0_buf_pool_srl_retry_retry_fifo_srlrow_0__srlcol_6__srlinst_Q15_UNCONNECTED), + .A0(com_tlm_u_tlm_tx_vc0_buf_pool_srl_retry_retry_fifo_raddr_lo[0]), + .A1(com_tlm_u_tlm_tx_vc0_buf_pool_srl_retry_retry_fifo_GND_3444), + .A2(com_tlm_u_tlm_tx_vc0_buf_pool_srl_retry_retry_fifo_GND_3444), + .A3(com_tlm_u_tlm_tx_vc0_buf_pool_srl_retry_retry_fifo_GND_3444) + ); + SRLC16E com_tlm_u_tlm_tx_vc0_buf_pool_srl_retry_retry_fifo_srlrow_0__srlcol_2__srlinst ( + .CE(com_tlm_u_tlm_tx_vc0_N_55858_i), + .D(com_tlm_u_tlm_tx_vc0_start_retry_tsn[2]), + .Q(com_tlm_u_tlm_tx_vc0_buf_pool_srl_retry_retry_fifo_shift_tap[2]), + .CLK(NlwRenamedSig_OI_trn_clk), + .Q15(NLW_com_tlm_u_tlm_tx_vc0_buf_pool_srl_retry_retry_fifo_srlrow_0__srlcol_2__srlinst_Q15_UNCONNECTED), + .A0(com_tlm_u_tlm_tx_vc0_buf_pool_srl_retry_retry_fifo_raddr_lo[0]), + .A1(com_tlm_u_tlm_tx_vc0_buf_pool_srl_retry_retry_fifo_GND_3444), + .A2(com_tlm_u_tlm_tx_vc0_buf_pool_srl_retry_retry_fifo_GND_3444), + .A3(com_tlm_u_tlm_tx_vc0_buf_pool_srl_retry_retry_fifo_GND_3444) + ); + SRLC16E com_tlm_u_tlm_tx_vc0_buf_pool_srl_retry_retry_fifo_srlrow_0__srlcol_11__srlinst ( + .CE(com_tlm_u_tlm_tx_vc0_N_55858_i), + .D(com_tlm_u_tlm_tx_vc0_start_retry_tsn[11]), + .Q(com_tlm_u_tlm_tx_vc0_buf_pool_srl_retry_retry_fifo_shift_tap[11]), + .CLK(NlwRenamedSig_OI_trn_clk), + .Q15(NLW_com_tlm_u_tlm_tx_vc0_buf_pool_srl_retry_retry_fifo_srlrow_0__srlcol_11__srlinst_Q15_UNCONNECTED), + .A0(com_tlm_u_tlm_tx_vc0_buf_pool_srl_retry_retry_fifo_raddr_lo[0]), + .A1(com_tlm_u_tlm_tx_vc0_buf_pool_srl_retry_retry_fifo_GND_3444), + .A2(com_tlm_u_tlm_tx_vc0_buf_pool_srl_retry_retry_fifo_GND_3444), + .A3(com_tlm_u_tlm_tx_vc0_buf_pool_srl_retry_retry_fifo_GND_3444) + ); + SRLC16E com_tlm_u_tlm_tx_vc0_buf_pool_srl_retry_retry_fifo_srlrow_0__srlcol_7__srlinst ( + .CE(com_tlm_u_tlm_tx_vc0_N_55858_i), + .D(com_tlm_u_tlm_tx_vc0_start_retry_tsn[7]), + .Q(com_tlm_u_tlm_tx_vc0_buf_pool_srl_retry_retry_fifo_shift_tap[7]), + .CLK(NlwRenamedSig_OI_trn_clk), + .Q15(NLW_com_tlm_u_tlm_tx_vc0_buf_pool_srl_retry_retry_fifo_srlrow_0__srlcol_7__srlinst_Q15_UNCONNECTED), + .A0(com_tlm_u_tlm_tx_vc0_buf_pool_srl_retry_retry_fifo_raddr_lo[0]), + .A1(com_tlm_u_tlm_tx_vc0_buf_pool_srl_retry_retry_fifo_GND_3444), + .A2(com_tlm_u_tlm_tx_vc0_buf_pool_srl_retry_retry_fifo_GND_3444), + .A3(com_tlm_u_tlm_tx_vc0_buf_pool_srl_retry_retry_fifo_GND_3444) + ); + SRLC16E com_tlm_u_tlm_tx_vc0_buf_pool_srl_retry_retry_fifo_srlrow_0__srlcol_3__srlinst ( + .CE(com_tlm_u_tlm_tx_vc0_N_55858_i), + .D(com_tlm_u_tlm_tx_vc0_start_retry_tsn[3]), + .Q(com_tlm_u_tlm_tx_vc0_buf_pool_srl_retry_retry_fifo_shift_tap[3]), + .CLK(NlwRenamedSig_OI_trn_clk), + .Q15(NLW_com_tlm_u_tlm_tx_vc0_buf_pool_srl_retry_retry_fifo_srlrow_0__srlcol_3__srlinst_Q15_UNCONNECTED), + .A0(com_tlm_u_tlm_tx_vc0_buf_pool_srl_retry_retry_fifo_raddr_lo[0]), + .A1(com_tlm_u_tlm_tx_vc0_buf_pool_srl_retry_retry_fifo_GND_3444), + .A2(com_tlm_u_tlm_tx_vc0_buf_pool_srl_retry_retry_fifo_GND_3444), + .A3(com_tlm_u_tlm_tx_vc0_buf_pool_srl_retry_retry_fifo_GND_3444) + ); + SRLC16E com_tlm_u_tlm_tx_vc0_buf_pool_srl_retry_retry_fifo_srlrow_0__srlcol_12__srlinst ( + .CE(com_tlm_u_tlm_tx_vc0_N_55858_i), + .D(com_tlm_u_tlm_tx_vc0_start_retry), + .Q(com_tlm_u_tlm_tx_vc0_buf_pool_srl_retry_retry_fifo_shift_tap[12]), + .CLK(NlwRenamedSig_OI_trn_clk), + .Q15(NLW_com_tlm_u_tlm_tx_vc0_buf_pool_srl_retry_retry_fifo_srlrow_0__srlcol_12__srlinst_Q15_UNCONNECTED), + .A0(com_tlm_u_tlm_tx_vc0_buf_pool_srl_retry_retry_fifo_raddr_lo[0]), + .A1(com_tlm_u_tlm_tx_vc0_buf_pool_srl_retry_retry_fifo_GND_3444), + .A2(com_tlm_u_tlm_tx_vc0_buf_pool_srl_retry_retry_fifo_GND_3444), + .A3(com_tlm_u_tlm_tx_vc0_buf_pool_srl_retry_retry_fifo_GND_3444) + ); + SRLC16E com_tlm_u_tlm_tx_vc0_buf_pool_srl_retry_retry_fifo_srlrow_0__srlcol_8__srlinst ( + .CE(com_tlm_u_tlm_tx_vc0_N_55858_i), + .D(com_tlm_u_tlm_tx_vc0_start_retry_tsn[8]), + .Q(com_tlm_u_tlm_tx_vc0_buf_pool_srl_retry_retry_fifo_shift_tap[8]), + .CLK(NlwRenamedSig_OI_trn_clk), + .Q15(NLW_com_tlm_u_tlm_tx_vc0_buf_pool_srl_retry_retry_fifo_srlrow_0__srlcol_8__srlinst_Q15_UNCONNECTED), + .A0(com_tlm_u_tlm_tx_vc0_buf_pool_srl_retry_retry_fifo_raddr_lo[0]), + .A1(com_tlm_u_tlm_tx_vc0_buf_pool_srl_retry_retry_fifo_GND_3444), + .A2(com_tlm_u_tlm_tx_vc0_buf_pool_srl_retry_retry_fifo_GND_3444), + .A3(com_tlm_u_tlm_tx_vc0_buf_pool_srl_retry_retry_fifo_GND_3444) + ); + SRLC16E com_tlm_u_tlm_tx_vc0_buf_pool_srl_retry_retry_fifo_srlrow_0__srlcol_4__srlinst ( + .CE(com_tlm_u_tlm_tx_vc0_N_55858_i), + .D(com_tlm_u_tlm_tx_vc0_start_retry_tsn[4]), + .Q(com_tlm_u_tlm_tx_vc0_buf_pool_srl_retry_retry_fifo_shift_tap[4]), + .CLK(NlwRenamedSig_OI_trn_clk), + .Q15(NLW_com_tlm_u_tlm_tx_vc0_buf_pool_srl_retry_retry_fifo_srlrow_0__srlcol_4__srlinst_Q15_UNCONNECTED), + .A0(com_tlm_u_tlm_tx_vc0_buf_pool_srl_retry_retry_fifo_raddr_lo[0]), + .A1(com_tlm_u_tlm_tx_vc0_buf_pool_srl_retry_retry_fifo_GND_3444), + .A2(com_tlm_u_tlm_tx_vc0_buf_pool_srl_retry_retry_fifo_GND_3444), + .A3(com_tlm_u_tlm_tx_vc0_buf_pool_srl_retry_retry_fifo_GND_3444) + ); + FDS com_tlm_u_tlm_tx_vc0_buf_pool_srl_retry_retry_fifo_raddr_lo_0_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_buf_pool_srl_retry_retry_fifo_un1_raddr_lo_1_axb_0_3453), + .Q(com_tlm_u_tlm_tx_vc0_buf_pool_srl_retry_retry_fifo_raddr_lo[0]), + .S(plm_link_up_i) + ); + FDS com_tlm_u_tlm_tx_vc0_buf_pool_srl_retry_retry_fifo_raddr_lo_1_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_buf_pool_srl_retry_retry_fifo_un1_raddr_lo_1_s_1_0), + .Q(com_tlm_u_tlm_tx_vc0_buf_pool_srl_retry_retry_fifo_raddr_lo[1]), + .S(plm_link_up_i) + ); + FDS com_tlm_u_tlm_tx_vc0_buf_pool_srl_retry_retry_fifo_raddr_lo_2_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_buf_pool_srl_retry_retry_fifo_un1_raddr_lo_1_s_2_0), + .Q(com_tlm_u_tlm_tx_vc0_buf_pool_srl_retry_retry_fifo_raddr_lo[2]), + .S(plm_link_up_i) + ); + FDS com_tlm_u_tlm_tx_vc0_buf_pool_srl_retry_retry_fifo_raddr_lo_3_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_buf_pool_srl_retry_retry_fifo_un1_raddr_lo_1_s_3_0), + .Q(com_tlm_u_tlm_tx_vc0_buf_pool_srl_retry_retry_fifo_raddr_lo[3]), + .S(plm_link_up_i) + ); + FDRE com_tlm_u_tlm_tx_vc0_buf_pool_srl_retry_retry_fifo_control_bits_d_o_12_ ( + .CE(com_tlm_u_tlm_tx_vc0_buf_pool_N_56080_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_buf_pool_srl_retry_retry_fifo_N_53087_i), + .Q(com_tlm_u_tlm_tx_vc0_retry), + .R(plm_link_up_i) + ); + FDRE com_tlm_u_tlm_tx_vc0_buf_pool_srl_retry_retry_fifo_nxt_vld_o ( + .CE(com_tlm_u_tlm_tx_vc0_buf_pool_srl_retry_retry_fifo_N_85559_i_3450), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_N_55858_i), + .Q(com_tlm_u_tlm_tx_vc0_buf_pool_srl_retry_retry_fifo_un1_retry_fifo_1), + .R(plm_link_up_i) + ); + MUXCY_L com_tlm_u_tlm_tx_vc0_buf_pool_srl_retry_retry_fifo_un1_raddr_lo_1_cry_0 ( + .CI(com_tlm_u_tlm_tx_vc0_buf_pool_srl_retry_retry_fifo_GND_3444), + .DI(com_tlm_u_tlm_tx_vc0_buf_pool_srl_retry_retry_fifo_raddr_lo[0]), + .LO(com_tlm_u_tlm_tx_vc0_buf_pool_srl_retry_retry_fifo_un1_raddr_lo_1_cry_0_3445), + .S(com_tlm_u_tlm_tx_vc0_buf_pool_srl_retry_retry_fifo_un1_raddr_lo_1_axb_0_3453) + ); + MUXCY_L com_tlm_u_tlm_tx_vc0_buf_pool_srl_retry_retry_fifo_un1_raddr_lo_1_cry_1 ( + .CI(com_tlm_u_tlm_tx_vc0_buf_pool_srl_retry_retry_fifo_un1_raddr_lo_1_cry_0_3445), + .DI(com_tlm_u_tlm_tx_vc0_buf_pool_srl_retry_retry_fifo_raddr_lo[1]), + .LO(com_tlm_u_tlm_tx_vc0_buf_pool_srl_retry_retry_fifo_un1_raddr_lo_1_cry_1_3446), + .S(com_tlm_u_tlm_tx_vc0_buf_pool_srl_retry_retry_fifo_un1_raddr_lo_1_axb_1_3459) + ); + XORCY com_tlm_u_tlm_tx_vc0_buf_pool_srl_retry_retry_fifo_un1_raddr_lo_1_s_1 ( + .CI(com_tlm_u_tlm_tx_vc0_buf_pool_srl_retry_retry_fifo_un1_raddr_lo_1_cry_0_3445), + .LI(com_tlm_u_tlm_tx_vc0_buf_pool_srl_retry_retry_fifo_un1_raddr_lo_1_axb_1_3459), + .O(com_tlm_u_tlm_tx_vc0_buf_pool_srl_retry_retry_fifo_un1_raddr_lo_1_s_1_0) + ); + MUXCY_L com_tlm_u_tlm_tx_vc0_buf_pool_srl_retry_retry_fifo_un1_raddr_lo_1_cry_2 ( + .CI(com_tlm_u_tlm_tx_vc0_buf_pool_srl_retry_retry_fifo_un1_raddr_lo_1_cry_1_3446), + .DI(com_tlm_u_tlm_tx_vc0_buf_pool_srl_retry_retry_fifo_raddr_lo[2]), + .LO(com_tlm_u_tlm_tx_vc0_buf_pool_srl_retry_retry_fifo_un1_raddr_lo_1_cry_2_3447), + .S(com_tlm_u_tlm_tx_vc0_buf_pool_srl_retry_retry_fifo_un1_raddr_lo_1_axb_2_3458) + ); + XORCY com_tlm_u_tlm_tx_vc0_buf_pool_srl_retry_retry_fifo_un1_raddr_lo_1_s_2 ( + .CI(com_tlm_u_tlm_tx_vc0_buf_pool_srl_retry_retry_fifo_un1_raddr_lo_1_cry_1_3446), + .LI(com_tlm_u_tlm_tx_vc0_buf_pool_srl_retry_retry_fifo_un1_raddr_lo_1_axb_2_3458), + .O(com_tlm_u_tlm_tx_vc0_buf_pool_srl_retry_retry_fifo_un1_raddr_lo_1_s_2_0) + ); + XORCY com_tlm_u_tlm_tx_vc0_buf_pool_srl_retry_retry_fifo_un1_raddr_lo_1_s_3 ( + .CI(com_tlm_u_tlm_tx_vc0_buf_pool_srl_retry_retry_fifo_un1_raddr_lo_1_cry_2_3447), + .LI(com_tlm_u_tlm_tx_vc0_buf_pool_srl_retry_retry_fifo_un1_raddr_lo_1_axb_3_3457), + .O(com_tlm_u_tlm_tx_vc0_buf_pool_srl_retry_retry_fifo_un1_raddr_lo_1_s_3_0) + ); + defparam com_tlm_u_tlm_tx_vc0_buf_pool_srl_retry_retry_fifo_un1_nxt_vld_o_en_1_i_0_0_0_o3.INIT = 4'h8; + LUT2 com_tlm_u_tlm_tx_vc0_buf_pool_srl_retry_retry_fifo_un1_nxt_vld_o_en_1_i_0_0_0_o3 ( + .I0(com_tlm_u_tlm_tx_vc0_buf_pool_rdata_q_all_138__3269), + .I1(com_tlm_u_tlm_tx_vc0_buf_pool_rvld_q[1]), + .O(com_tlm_u_tlm_tx_vc0_buf_pool_N_55935_i) + ); + defparam com_tlm_u_tlm_tx_vc0_buf_pool_srl_retry_retry_fifo_un1_nxt_vld_o_en_1_i_0_0_0_o3_0.INIT = 4'h8; + LUT2 com_tlm_u_tlm_tx_vc0_buf_pool_srl_retry_retry_fifo_un1_nxt_vld_o_en_1_i_0_0_0_o3_0 ( + .I0(com_tlm_u_tlm_tx_vc0_buf_pool_rdata_q_all_66__3270), + .I1(com_tlm_u_tlm_tx_vc0_buf_pool_rvld_q[0]), + .O(com_tlm_u_tlm_tx_vc0_buf_pool_N_55992_i) + ); + defparam com_tlm_u_tlm_tx_vc0_buf_pool_srl_retry_retry_fifo_un1_nxt_vld_o_en_1_i_0_0_0_a2_0_1_1.INIT = 4'h1; + LUT2 com_tlm_u_tlm_tx_vc0_buf_pool_srl_retry_retry_fifo_un1_nxt_vld_o_en_1_i_0_0_0_a2_0_1_1 ( + .I0(com_tlm_u_tlm_tx_vc0_buf_pool_srl_retry_retry_fifo_raddr_lo[0]), + .I1(com_tlm_u_tlm_tx_vc0_buf_pool_srl_retry_retry_fifo_raddr_lo[2]), + .O(com_tlm_u_tlm_tx_vc0_buf_pool_srl_retry_retry_fifo_un1_nxt_vld_o_en_1_i_0_0_0_a2_0_1_1_3448) + ); + defparam com_tlm_u_tlm_tx_vc0_buf_pool_srl_retry_retry_fifo_raddr_en_0_0_i_a3_1_1.INIT = 4'h4; + LUT2 com_tlm_u_tlm_tx_vc0_buf_pool_srl_retry_retry_fifo_raddr_en_0_0_i_a3_1_1 ( + .I0(com_tlm_u_tlm_tx_vc0_buf_pool_N_55898_i), + .I1(com_tlm_u_tlm_tx_vc0_buf_pool_srl_retry_retry_fifo_un1_retry_fifo_1), + .O(com_tlm_u_tlm_tx_vc0_buf_pool_srl_retry_retry_fifo_N_61280_1) + ); + defparam com_tlm_u_tlm_tx_vc0_buf_pool_srl_retry_retry_fifo_un1_nxt_vld_o_en_1_i_0_0_0_a2_0_1.INIT = 16'h0100; + LUT4 com_tlm_u_tlm_tx_vc0_buf_pool_srl_retry_retry_fifo_un1_nxt_vld_o_en_1_i_0_0_0_a2_0_1 ( + .I0(com_tlm_u_tlm_tx_vc0_buf_pool_N_55898_i), + .I1(com_tlm_u_tlm_tx_vc0_buf_pool_srl_retry_retry_fifo_raddr_lo[1]), + .I2(com_tlm_u_tlm_tx_vc0_buf_pool_srl_retry_retry_fifo_raddr_lo[3]), + .I3(com_tlm_u_tlm_tx_vc0_buf_pool_srl_retry_retry_fifo_un1_nxt_vld_o_en_1_i_0_0_0_a2_0_1_1_3448), + .O(com_tlm_u_tlm_tx_vc0_buf_pool_srl_retry_retry_fifo_N_58747_1) + ); + defparam com_tlm_u_tlm_tx_vc0_buf_pool_srl_retry_retry_fifo_raddr_en_0_0_i_a2_1_0.INIT = 8'h40; + LUT3 com_tlm_u_tlm_tx_vc0_buf_pool_srl_retry_retry_fifo_raddr_en_0_0_i_a2_1_0 ( + .I0(com_tlm_u_tlm_tx_vc0_N_55980_i), + .I1(com_tlm_u_tlm_tx_vc0_in_frame), + .I2(com_tlm_u_tlm_tx_vc0_start_src_rdy), + .O(com_tlm_u_tlm_tx_vc0_buf_pool_srl_retry_retry_fifo_raddr_en_0_0_i_a2_1_0_3454) + ); + defparam com_tlm_u_tlm_tx_vc0_buf_pool_srl_retry_retry_fifo_raddr_en_0_0_a2_1_i_o2.INIT = 4'h8; + LUT2 com_tlm_u_tlm_tx_vc0_buf_pool_srl_retry_retry_fifo_raddr_en_0_0_a2_1_i_o2 ( + .I0(com_tlm_u_tlm_tx_vc0_buf_pool_N_56080_i), + .I1(com_tlm_u_tlm_tx_vc0_buf_pool_srl_retry_retry_fifo_un1_retry_fifo_1), + .O(com_tlm_u_tlm_tx_vc0_buf_pool_srl_retry_retry_fifo_N_56203_i) + ); + defparam com_tlm_u_tlm_tx_vc0_buf_pool_srl_retry_retry_fifo_raddr_en_0_0_i_a2_0_1.INIT = 16'hE000; + LUT4 com_tlm_u_tlm_tx_vc0_buf_pool_srl_retry_retry_fifo_raddr_en_0_0_i_a2_0_1 ( + .I0(com_tlm_u_tlm_tx_vc0_buf_pool_N_55935_i), + .I1(com_tlm_u_tlm_tx_vc0_buf_pool_N_55992_i), + .I2(com_tlm_u_tlm_tx_vc0_buf_pool_srl_retry_retry_fifo_N_61280_1), + .I3(com_tlm_u_tlm_tx_vc0_start_src_rdy), + .O(com_tlm_u_tlm_tx_vc0_buf_pool_srl_retry_retry_fifo_raddr_en_0_0_i_a2_0_1_3451) + ); + defparam com_tlm_u_tlm_tx_vc0_buf_pool_srl_retry_retry_fifo_raddr_en_0_0_a2_1_i_0.INIT = 8'h8A; + LUT3_L com_tlm_u_tlm_tx_vc0_buf_pool_srl_retry_retry_fifo_raddr_en_0_0_a2_1_i_0 ( + .I0(com_tlm_u_tlm_tx_vc0_buf_pool_srl_retry_retry_fifo_N_56203_i), + .I1(com_tlm_u_tlm_tx_vc0_in_frame), + .I2(com_tlm_u_tlm_tx_vc0_start_src_rdy), + .LO(com_tlm_u_tlm_tx_vc0_buf_pool_srl_retry_retry_fifo_raddr_en_0_0_a2_1_i_0_3449) + ); + defparam com_tlm_u_tlm_tx_vc0_buf_pool_srl_retry_retry_fifo_raddr_en_0_0_a2_1_i.INIT = 16'h10F0; + LUT4 com_tlm_u_tlm_tx_vc0_buf_pool_srl_retry_retry_fifo_raddr_en_0_0_a2_1_i ( + .I0(com_tlm_u_tlm_tx_vc0_N_55914_i), + .I1(com_tlm_u_tlm_tx_vc0_N_55980_i), + .I2(com_tlm_u_tlm_tx_vc0_buf_pool_srl_retry_retry_fifo_raddr_en_0_0_a2_1_i_0_3449), + .I3(com_tlm_u_tlm_tx_vc0_start_src_rdy), + .O(com_tlm_u_tlm_tx_vc0_buf_pool_srl_retry_retry_fifo_N_53076_i) + ); + defparam com_tlm_u_tlm_tx_vc0_buf_pool_srl_retry_retry_fifo_raddr_en_0_0_i_o3_0_0.INIT = 16'h72FA; + LUT4_L com_tlm_u_tlm_tx_vc0_buf_pool_srl_retry_retry_fifo_raddr_en_0_0_i_o3_0_0 ( + .I0(com_tlm_u_tlm_tx_vc0_N_55914_i), + .I1(com_tlm_u_tlm_tx_vc0_buf_pool_N_55935_i), + .I2(com_tlm_u_tlm_tx_vc0_buf_pool_srl_retry_retry_fifo_N_56203_i), + .I3(com_tlm_u_tlm_tx_vc0_buf_pool_srl_retry_retry_fifo_N_61280_1), + .LO(com_tlm_u_tlm_tx_vc0_buf_pool_srl_retry_retry_fifo_raddr_en_0_0_i_o3_0) + ); + defparam com_tlm_u_tlm_tx_vc0_buf_pool_srl_retry_retry_fifo_raddr_en_0_0_i_0.INIT = 16'h5F4C; + LUT4_L com_tlm_u_tlm_tx_vc0_buf_pool_srl_retry_retry_fifo_raddr_en_0_0_i_0 ( + .I0(com_tlm_u_tlm_tx_vc0_N_56167_i), + .I1(com_tlm_u_tlm_tx_vc0_buf_pool_srl_retry_retry_fifo_N_56203_i), + .I2(com_tlm_u_tlm_tx_vc0_in_frame), + .I3(com_tlm_u_tlm_tx_vc0_start_src_rdy), + .LO(com_tlm_u_tlm_tx_vc0_buf_pool_srl_retry_retry_fifo_raddr_en_0_0_i_0_3452) + ); + defparam com_tlm_u_tlm_tx_vc0_buf_pool_srl_retry_retry_fifo_N_85559_i.INIT = 16'hFEAA; + LUT4 com_tlm_u_tlm_tx_vc0_buf_pool_srl_retry_retry_fifo_N_85559_i ( + .I0(com_tlm_u_tlm_tx_vc0_N_55858_i), + .I1(com_tlm_u_tlm_tx_vc0_buf_pool_N_55935_i), + .I2(com_tlm_u_tlm_tx_vc0_buf_pool_N_55992_i), + .I3(com_tlm_u_tlm_tx_vc0_buf_pool_srl_retry_retry_fifo_N_58747_1), + .O(com_tlm_u_tlm_tx_vc0_buf_pool_srl_retry_retry_fifo_N_85559_i_3450) + ); + defparam com_tlm_u_tlm_tx_vc0_buf_pool_srl_retry_retry_fifo_raddr_en_0_0_i_o3.INIT = 16'h7F00; + LUT4 com_tlm_u_tlm_tx_vc0_buf_pool_srl_retry_retry_fifo_raddr_en_0_0_i_o3 ( + .I0(com_tlm_u_tlm_tx_vc0_N_55914_i), + .I1(com_tlm_u_tlm_tx_vc0_buf_pool_N_55992_i), + .I2(com_tlm_u_tlm_tx_vc0_buf_pool_srl_retry_retry_fifo_N_61280_1), + .I3(com_tlm_u_tlm_tx_vc0_buf_pool_srl_retry_retry_fifo_raddr_en_0_0_i_o3_0), + .O(com_tlm_u_tlm_tx_vc0_buf_pool_srl_retry_retry_fifo_raddr_en_0_0_i_o3_3456) + ); + defparam com_tlm_u_tlm_tx_vc0_buf_pool_srl_retry_retry_fifo_raddr_en_0_0_i_1.INIT = 16'h40F0; + LUT4 com_tlm_u_tlm_tx_vc0_buf_pool_srl_retry_retry_fifo_raddr_en_0_0_i_1 ( + .I0(com_tlm_u_tlm_tx_vc0_N_55980_i), + .I1(com_tlm_u_tlm_tx_vc0_in_frame), + .I2(com_tlm_u_tlm_tx_vc0_buf_pool_srl_retry_retry_fifo_raddr_en_0_0_i_0_3452), + .I3(com_tlm_u_tlm_tx_vc0_buf_pool_srl_retry_retry_fifo_raddr_en_0_0_i_a2_0_1_3451), + .O(com_tlm_u_tlm_tx_vc0_buf_pool_srl_retry_retry_fifo_raddr_en_0_0_i_1_3455) + ); + defparam com_tlm_u_tlm_tx_vc0_buf_pool_srl_retry_retry_fifo_un1_raddr_lo_1_axb_0.INIT = 16'h738C; + LUT4 com_tlm_u_tlm_tx_vc0_buf_pool_srl_retry_retry_fifo_un1_raddr_lo_1_axb_0 ( + .I0(com_tlm_u_tlm_tx_vc0_buf_pool_srl_retry_retry_fifo_raddr_en_0_0_i_o3_3456), + .I1(com_tlm_u_tlm_tx_vc0_buf_pool_srl_retry_retry_fifo_raddr_en_0_0_i_1_3455), + .I2(com_tlm_u_tlm_tx_vc0_buf_pool_srl_retry_retry_fifo_raddr_en_0_0_i_a2_1_0_3454), + .I3(com_tlm_u_tlm_tx_vc0_buf_pool_srl_retry_retry_fifo_raddr_lo[0]), + .O(com_tlm_u_tlm_tx_vc0_buf_pool_srl_retry_retry_fifo_un1_raddr_lo_1_axb_0_3453) + ); + defparam com_tlm_u_tlm_tx_vc0_buf_pool_srl_retry_retry_fifo_shift_tap_m_0_a2_0_a2_i_12_.INIT = 4'h8; + LUT2_L com_tlm_u_tlm_tx_vc0_buf_pool_srl_retry_retry_fifo_shift_tap_m_0_a2_0_a2_i_12_ ( + .I0(com_tlm_u_tlm_tx_vc0_buf_pool_srl_retry_retry_fifo_N_56203_i), + .I1(com_tlm_u_tlm_tx_vc0_buf_pool_srl_retry_retry_fifo_shift_tap[12]), + .LO(com_tlm_u_tlm_tx_vc0_buf_pool_srl_retry_retry_fifo_N_53087_i) + ); + defparam com_tlm_u_tlm_tx_vc0_buf_pool_srl_retry_retry_fifo_un1_raddr_lo_1_axb_3.INIT = 4'h6; + LUT2_L com_tlm_u_tlm_tx_vc0_buf_pool_srl_retry_retry_fifo_un1_raddr_lo_1_axb_3 ( + .I0(com_tlm_u_tlm_tx_vc0_buf_pool_srl_retry_retry_fifo_N_53076_i), + .I1(com_tlm_u_tlm_tx_vc0_buf_pool_srl_retry_retry_fifo_raddr_lo[3]), + .LO(com_tlm_u_tlm_tx_vc0_buf_pool_srl_retry_retry_fifo_un1_raddr_lo_1_axb_3_3457) + ); + defparam com_tlm_u_tlm_tx_vc0_buf_pool_srl_retry_retry_fifo_un1_raddr_lo_1_axb_2.INIT = 4'h6; + LUT2_L com_tlm_u_tlm_tx_vc0_buf_pool_srl_retry_retry_fifo_un1_raddr_lo_1_axb_2 ( + .I0(com_tlm_u_tlm_tx_vc0_buf_pool_srl_retry_retry_fifo_N_53076_i), + .I1(com_tlm_u_tlm_tx_vc0_buf_pool_srl_retry_retry_fifo_raddr_lo[2]), + .LO(com_tlm_u_tlm_tx_vc0_buf_pool_srl_retry_retry_fifo_un1_raddr_lo_1_axb_2_3458) + ); + defparam com_tlm_u_tlm_tx_vc0_buf_pool_srl_retry_retry_fifo_un1_raddr_lo_1_axb_1.INIT = 4'h6; + LUT2_L com_tlm_u_tlm_tx_vc0_buf_pool_srl_retry_retry_fifo_un1_raddr_lo_1_axb_1 ( + .I0(com_tlm_u_tlm_tx_vc0_buf_pool_srl_retry_retry_fifo_N_53076_i), + .I1(com_tlm_u_tlm_tx_vc0_buf_pool_srl_retry_retry_fifo_raddr_lo[1]), + .LO(com_tlm_u_tlm_tx_vc0_buf_pool_srl_retry_retry_fifo_un1_raddr_lo_1_axb_1_3459) + ); + defparam com_tlm_u_tlm_tx_vc0_buf_pool_srl_retry_retry_fifo_N_56200_i_i.INIT = 4'hE; + LUT2_L com_tlm_u_tlm_tx_vc0_buf_pool_srl_retry_retry_fifo_N_56200_i_i ( + .I0(com_tlm_u_tlm_tx_vc0_buf_pool_N_55935_i), + .I1(com_tlm_u_tlm_tx_vc0_buf_pool_N_55992_i), + .LO(com_tlm_u_tlm_tx_vc0_buf_pool_N_56200_i_i) + ); + FDE com_tlm_u_tlm_tx_vc0_buf_pool_srl_retry_retry_fifo_data_bits_d_o_11_ ( + .CE(com_tlm_u_tlm_tx_vc0_buf_pool_N_56080_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_buf_pool_srl_retry_retry_fifo_shift_tap[11]), + .Q(com_tlm_u_tlm_tx_vc0_retry_tsn[11]) + ); + FDE com_tlm_u_tlm_tx_vc0_buf_pool_srl_retry_retry_fifo_data_bits_d_o_10_ ( + .CE(com_tlm_u_tlm_tx_vc0_buf_pool_N_56080_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_buf_pool_srl_retry_retry_fifo_shift_tap[10]), + .Q(com_tlm_u_tlm_tx_vc0_retry_tsn[10]) + ); + FDE com_tlm_u_tlm_tx_vc0_buf_pool_srl_retry_retry_fifo_data_bits_d_o_9_ ( + .CE(com_tlm_u_tlm_tx_vc0_buf_pool_N_56080_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_buf_pool_srl_retry_retry_fifo_shift_tap[9]), + .Q(com_tlm_u_tlm_tx_vc0_retry_tsn[9]) + ); + FDE com_tlm_u_tlm_tx_vc0_buf_pool_srl_retry_retry_fifo_data_bits_d_o_8_ ( + .CE(com_tlm_u_tlm_tx_vc0_buf_pool_N_56080_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_buf_pool_srl_retry_retry_fifo_shift_tap[8]), + .Q(com_tlm_u_tlm_tx_vc0_retry_tsn[8]) + ); + FDE com_tlm_u_tlm_tx_vc0_buf_pool_srl_retry_retry_fifo_data_bits_d_o_7_ ( + .CE(com_tlm_u_tlm_tx_vc0_buf_pool_N_56080_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_buf_pool_srl_retry_retry_fifo_shift_tap[7]), + .Q(com_tlm_u_tlm_tx_vc0_retry_tsn[7]) + ); + FDE com_tlm_u_tlm_tx_vc0_buf_pool_srl_retry_retry_fifo_data_bits_d_o_6_ ( + .CE(com_tlm_u_tlm_tx_vc0_buf_pool_N_56080_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_buf_pool_srl_retry_retry_fifo_shift_tap[6]), + .Q(com_tlm_u_tlm_tx_vc0_retry_tsn[6]) + ); + FDE com_tlm_u_tlm_tx_vc0_buf_pool_srl_retry_retry_fifo_data_bits_d_o_5_ ( + .CE(com_tlm_u_tlm_tx_vc0_buf_pool_N_56080_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_buf_pool_srl_retry_retry_fifo_shift_tap[5]), + .Q(com_tlm_u_tlm_tx_vc0_retry_tsn[5]) + ); + FDE com_tlm_u_tlm_tx_vc0_buf_pool_srl_retry_retry_fifo_data_bits_d_o_4_ ( + .CE(com_tlm_u_tlm_tx_vc0_buf_pool_N_56080_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_buf_pool_srl_retry_retry_fifo_shift_tap[4]), + .Q(com_tlm_u_tlm_tx_vc0_retry_tsn[4]) + ); + FDE com_tlm_u_tlm_tx_vc0_buf_pool_srl_retry_retry_fifo_data_bits_d_o_3_ ( + .CE(com_tlm_u_tlm_tx_vc0_buf_pool_N_56080_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_buf_pool_srl_retry_retry_fifo_shift_tap[3]), + .Q(com_tlm_u_tlm_tx_vc0_retry_tsn[3]) + ); + FDE com_tlm_u_tlm_tx_vc0_buf_pool_srl_retry_retry_fifo_data_bits_d_o_2_ ( + .CE(com_tlm_u_tlm_tx_vc0_buf_pool_N_56080_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_buf_pool_srl_retry_retry_fifo_shift_tap[2]), + .Q(com_tlm_u_tlm_tx_vc0_retry_tsn[2]) + ); + FDE com_tlm_u_tlm_tx_vc0_buf_pool_srl_retry_retry_fifo_data_bits_d_o_1_ ( + .CE(com_tlm_u_tlm_tx_vc0_buf_pool_N_56080_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_buf_pool_srl_retry_retry_fifo_shift_tap[1]), + .Q(com_tlm_u_tlm_tx_vc0_retry_tsn[1]) + ); + FDE com_tlm_u_tlm_tx_vc0_buf_pool_srl_retry_retry_fifo_data_bits_d_o_0_ ( + .CE(com_tlm_u_tlm_tx_vc0_buf_pool_N_56080_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_buf_pool_srl_retry_retry_fifo_shift_tap[0]), + .Q(com_tlm_u_tlm_tx_vc0_retry_tsn[0]) + ); + INV com_tlm_u_tlm_tx_vc0_buf_pool_srl_retry_retry_fifo_control_bits_vc0_retry_i ( + .I(com_tlm_u_tlm_tx_vc0_retry), + .O(com_tlm_u_tlm_tx_vc0_retry_i) + ); + VCC com_tlm_u_tlm_tx_vc0_buf_pool_bram_0__size4_bram_array_VCC ( + .P(com_tlm_u_tlm_tx_vc0_buf_pool_bram_0__size4_bram_array_VCC_3460) + ); + GND com_tlm_u_tlm_tx_vc0_buf_pool_bram_0__size4_bram_array_GND ( + .G(com_tlm_u_tlm_tx_vc0_buf_pool_bram_0__size4_bram_array_GND_3461) + ); + defparam com_tlm_u_tlm_tx_vc0_buf_pool_bram_0__size4_bram_array_ram_row_0__block_ram_0__ram1024x18_bram.WRITE_MODE_A = "NO_CHANGE"; + RAMB16_S18_S18 com_tlm_u_tlm_tx_vc0_buf_pool_bram_0__size4_bram_array_ram_row_0__block_ram_0__ram1024x18_bram ( + .ENA(com_tlm_u_tlm_tx_vc0_buf_pool_bram_0__size4_bram_array_VCC_3460), + .ENB(com_tlm_u_tlm_tx_vc0_buf_pool_N_10911_i), + .SSRA(com_reset_i_q), + .SSRB(com_reset_i_q), + .WEA(com_tlm_u_tlm_tx_vc0_buf_pool_N_27037_i), + .WEB(com_tlm_u_tlm_tx_vc0_buf_pool_bram_0__size4_bram_array_GND_3461), + .CLKA(NlwRenamedSig_OI_trn_clk), + .CLKB(NlwRenamedSig_OI_trn_clk), + .ADDRA({com_tlm_u_tlm_tx_vc0_buf_pool_waddr_h[2], com_tlm_u_tlm_tx_vc0_buf_pool_waddr_h[1], com_tlm_u_tlm_tx_vc0_buf_pool_waddr_h[0], +com_tlm_u_tlm_tx_vc0_buf_pool_waddr_l[6], com_tlm_u_tlm_tx_vc0_buf_pool_waddr_l[5], com_tlm_u_tlm_tx_vc0_buf_pool_waddr_l[4], +com_tlm_u_tlm_tx_vc0_buf_pool_waddr_l[3], com_tlm_u_tlm_tx_vc0_buf_pool_waddr_l[2], com_tlm_u_tlm_tx_vc0_buf_pool_waddr_l[1], +com_tlm_u_tlm_tx_vc0_buf_pool_waddr_l[0]}), + .DOPA({NLW_com_tlm_u_tlm_tx_vc0_buf_pool_bram_0__size4_bram_array_ram_row_0__block_ram_0__ram1024x18_bram_DOPA_1__UNCONNECTED, +NLW_com_tlm_u_tlm_tx_vc0_buf_pool_bram_0__size4_bram_array_ram_row_0__block_ram_0__ram1024x18_bram_DOPA_0__UNCONNECTED}), + .ADDRB({com_tlm_u_tlm_tx_vc0_buf_pool_raddr_h[2], com_tlm_u_tlm_tx_vc0_buf_pool_raddr_h[1], com_tlm_u_tlm_tx_vc0_buf_pool_raddr_h[0], +com_tlm_u_tlm_tx_vc0_buf_pool_raddr_l[6], com_tlm_u_tlm_tx_vc0_buf_pool_raddr_l[5], com_tlm_u_tlm_tx_vc0_buf_pool_raddr_l[4], +com_tlm_u_tlm_tx_vc0_buf_pool_raddr_l[3], com_tlm_u_tlm_tx_vc0_buf_pool_raddr_l[2], com_tlm_u_tlm_tx_vc0_buf_pool_raddr_l[1], +com_tlm_u_tlm_tx_vc0_buf_pool_raddr_l[0]}), + .DOPB({com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all_17_, com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all_16_}), + .DIA({com_tlm_u_tlm_tx_vc0_buf_pool_wdata_15__3360, com_tlm_u_tlm_tx_vc0_buf_pool_wdata_14__3361, com_tlm_u_tlm_tx_vc0_buf_pool_wdata_13__3362, +com_tlm_u_tlm_tx_vc0_buf_pool_wdata_12__3363, com_tlm_u_tlm_tx_vc0_buf_pool_wdata_11__3364, com_tlm_u_tlm_tx_vc0_buf_pool_wdata_10__3365, +com_tlm_u_tlm_tx_vc0_buf_pool_wdata_9__3366, com_tlm_u_tlm_tx_vc0_buf_pool_wdata_8__3367, com_tlm_u_tlm_tx_vc0_buf_pool_wdata_7__3368, +com_tlm_u_tlm_tx_vc0_buf_pool_wdata_6__3369, com_tlm_u_tlm_tx_vc0_buf_pool_wdata_5__3370, com_tlm_u_tlm_tx_vc0_buf_pool_wdata_4__3371, +com_tlm_u_tlm_tx_vc0_buf_pool_wdata_3__3372, com_tlm_u_tlm_tx_vc0_buf_pool_wdata_2__3373, com_tlm_u_tlm_tx_vc0_buf_pool_wdata_1__3374, +com_tlm_u_tlm_tx_vc0_buf_pool_wdata_0__3375}), + .DIB({com_tlm_u_tlm_tx_vc0_buf_pool_bram_0__size4_bram_array_GND_3461, com_tlm_u_tlm_tx_vc0_buf_pool_bram_0__size4_bram_array_GND_3461, +com_tlm_u_tlm_tx_vc0_buf_pool_bram_0__size4_bram_array_GND_3461, com_tlm_u_tlm_tx_vc0_buf_pool_bram_0__size4_bram_array_GND_3461, +com_tlm_u_tlm_tx_vc0_buf_pool_bram_0__size4_bram_array_GND_3461, com_tlm_u_tlm_tx_vc0_buf_pool_bram_0__size4_bram_array_GND_3461, +com_tlm_u_tlm_tx_vc0_buf_pool_bram_0__size4_bram_array_GND_3461, com_tlm_u_tlm_tx_vc0_buf_pool_bram_0__size4_bram_array_GND_3461, +com_tlm_u_tlm_tx_vc0_buf_pool_bram_0__size4_bram_array_GND_3461, com_tlm_u_tlm_tx_vc0_buf_pool_bram_0__size4_bram_array_GND_3461, +com_tlm_u_tlm_tx_vc0_buf_pool_bram_0__size4_bram_array_GND_3461, com_tlm_u_tlm_tx_vc0_buf_pool_bram_0__size4_bram_array_GND_3461, +com_tlm_u_tlm_tx_vc0_buf_pool_bram_0__size4_bram_array_GND_3461, com_tlm_u_tlm_tx_vc0_buf_pool_bram_0__size4_bram_array_GND_3461, +com_tlm_u_tlm_tx_vc0_buf_pool_bram_0__size4_bram_array_GND_3461, com_tlm_u_tlm_tx_vc0_buf_pool_bram_0__size4_bram_array_GND_3461}), + .DOA({NLW_com_tlm_u_tlm_tx_vc0_buf_pool_bram_0__size4_bram_array_ram_row_0__block_ram_0__ram1024x18_bram_DOA_15__UNCONNECTED, +NLW_com_tlm_u_tlm_tx_vc0_buf_pool_bram_0__size4_bram_array_ram_row_0__block_ram_0__ram1024x18_bram_DOA_14__UNCONNECTED, +NLW_com_tlm_u_tlm_tx_vc0_buf_pool_bram_0__size4_bram_array_ram_row_0__block_ram_0__ram1024x18_bram_DOA_13__UNCONNECTED, +NLW_com_tlm_u_tlm_tx_vc0_buf_pool_bram_0__size4_bram_array_ram_row_0__block_ram_0__ram1024x18_bram_DOA_12__UNCONNECTED, +NLW_com_tlm_u_tlm_tx_vc0_buf_pool_bram_0__size4_bram_array_ram_row_0__block_ram_0__ram1024x18_bram_DOA_11__UNCONNECTED, +NLW_com_tlm_u_tlm_tx_vc0_buf_pool_bram_0__size4_bram_array_ram_row_0__block_ram_0__ram1024x18_bram_DOA_10__UNCONNECTED, +NLW_com_tlm_u_tlm_tx_vc0_buf_pool_bram_0__size4_bram_array_ram_row_0__block_ram_0__ram1024x18_bram_DOA_9__UNCONNECTED, +NLW_com_tlm_u_tlm_tx_vc0_buf_pool_bram_0__size4_bram_array_ram_row_0__block_ram_0__ram1024x18_bram_DOA_8__UNCONNECTED, +NLW_com_tlm_u_tlm_tx_vc0_buf_pool_bram_0__size4_bram_array_ram_row_0__block_ram_0__ram1024x18_bram_DOA_7__UNCONNECTED, +NLW_com_tlm_u_tlm_tx_vc0_buf_pool_bram_0__size4_bram_array_ram_row_0__block_ram_0__ram1024x18_bram_DOA_6__UNCONNECTED, +NLW_com_tlm_u_tlm_tx_vc0_buf_pool_bram_0__size4_bram_array_ram_row_0__block_ram_0__ram1024x18_bram_DOA_5__UNCONNECTED, +NLW_com_tlm_u_tlm_tx_vc0_buf_pool_bram_0__size4_bram_array_ram_row_0__block_ram_0__ram1024x18_bram_DOA_4__UNCONNECTED, +NLW_com_tlm_u_tlm_tx_vc0_buf_pool_bram_0__size4_bram_array_ram_row_0__block_ram_0__ram1024x18_bram_DOA_3__UNCONNECTED, +NLW_com_tlm_u_tlm_tx_vc0_buf_pool_bram_0__size4_bram_array_ram_row_0__block_ram_0__ram1024x18_bram_DOA_2__UNCONNECTED, +NLW_com_tlm_u_tlm_tx_vc0_buf_pool_bram_0__size4_bram_array_ram_row_0__block_ram_0__ram1024x18_bram_DOA_1__UNCONNECTED, +NLW_com_tlm_u_tlm_tx_vc0_buf_pool_bram_0__size4_bram_array_ram_row_0__block_ram_0__ram1024x18_bram_DOA_0__UNCONNECTED}), + .DOB({com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all_15_, com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all_14_, com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all_13_, +com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all_12_, com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all_11_, com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all_10_, +com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all_9_, com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all_8_, com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all_7_, +com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all_6_, com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all_5_, com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all_4_, +com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all_3_, com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all_2_, com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all_1_, +com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all_0_}), + .DIPA({com_tlm_u_tlm_tx_vc0_buf_pool_wdata_17__3358, com_tlm_u_tlm_tx_vc0_buf_pool_wdata_16__3359}), + .DIPB({com_tlm_u_tlm_tx_vc0_buf_pool_bram_0__size4_bram_array_GND_3461, com_tlm_u_tlm_tx_vc0_buf_pool_bram_0__size4_bram_array_GND_3461}) + ); + defparam com_tlm_u_tlm_tx_vc0_buf_pool_bram_0__size4_bram_array_ram_row_0__block_ram_1__ram1024x18_bram.WRITE_MODE_A = "NO_CHANGE"; + RAMB16_S18_S18 com_tlm_u_tlm_tx_vc0_buf_pool_bram_0__size4_bram_array_ram_row_0__block_ram_1__ram1024x18_bram ( + .ENA(com_tlm_u_tlm_tx_vc0_buf_pool_bram_0__size4_bram_array_VCC_3460), + .ENB(com_tlm_u_tlm_tx_vc0_buf_pool_N_10911_i), + .SSRA(com_reset_i_q), + .SSRB(com_reset_i_q), + .WEA(com_tlm_u_tlm_tx_vc0_buf_pool_N_27037_i), + .WEB(com_tlm_u_tlm_tx_vc0_buf_pool_bram_0__size4_bram_array_GND_3461), + .CLKA(NlwRenamedSig_OI_trn_clk), + .CLKB(NlwRenamedSig_OI_trn_clk), + .ADDRA({com_tlm_u_tlm_tx_vc0_buf_pool_waddr_h[2], com_tlm_u_tlm_tx_vc0_buf_pool_waddr_h[1], com_tlm_u_tlm_tx_vc0_buf_pool_waddr_h[0], +com_tlm_u_tlm_tx_vc0_buf_pool_waddr_l[6], com_tlm_u_tlm_tx_vc0_buf_pool_waddr_l[5], com_tlm_u_tlm_tx_vc0_buf_pool_waddr_l[4], +com_tlm_u_tlm_tx_vc0_buf_pool_waddr_l[3], com_tlm_u_tlm_tx_vc0_buf_pool_waddr_l[2], com_tlm_u_tlm_tx_vc0_buf_pool_waddr_l[1], +com_tlm_u_tlm_tx_vc0_buf_pool_waddr_l[0]}), + .DOPA({NLW_com_tlm_u_tlm_tx_vc0_buf_pool_bram_0__size4_bram_array_ram_row_0__block_ram_1__ram1024x18_bram_DOPA_1__UNCONNECTED, +NLW_com_tlm_u_tlm_tx_vc0_buf_pool_bram_0__size4_bram_array_ram_row_0__block_ram_1__ram1024x18_bram_DOPA_0__UNCONNECTED}), + .ADDRB({com_tlm_u_tlm_tx_vc0_buf_pool_raddr_h[2], com_tlm_u_tlm_tx_vc0_buf_pool_raddr_h[1], com_tlm_u_tlm_tx_vc0_buf_pool_raddr_h[0], +com_tlm_u_tlm_tx_vc0_buf_pool_raddr_l[6], com_tlm_u_tlm_tx_vc0_buf_pool_raddr_l[5], com_tlm_u_tlm_tx_vc0_buf_pool_raddr_l[4], +com_tlm_u_tlm_tx_vc0_buf_pool_raddr_l[3], com_tlm_u_tlm_tx_vc0_buf_pool_raddr_l[2], com_tlm_u_tlm_tx_vc0_buf_pool_raddr_l[1], +com_tlm_u_tlm_tx_vc0_buf_pool_raddr_l[0]}), + .DOPB({com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all_35_, com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all_34_}), + .DIA({com_tlm_u_tlm_tx_vc0_buf_pool_wdata_33__3342, com_tlm_u_tlm_tx_vc0_buf_pool_wdata_32__3343, com_tlm_u_tlm_tx_vc0_buf_pool_wdata_31__3344, +com_tlm_u_tlm_tx_vc0_buf_pool_wdata_30__3345, com_tlm_u_tlm_tx_vc0_buf_pool_wdata_29__3346, com_tlm_u_tlm_tx_vc0_buf_pool_wdata_28__3347, +com_tlm_u_tlm_tx_vc0_buf_pool_wdata_27__3348, com_tlm_u_tlm_tx_vc0_buf_pool_wdata_26__3349, com_tlm_u_tlm_tx_vc0_buf_pool_wdata_25__3350, +com_tlm_u_tlm_tx_vc0_buf_pool_wdata_24__3351, com_tlm_u_tlm_tx_vc0_buf_pool_wdata_23__3352, com_tlm_u_tlm_tx_vc0_buf_pool_wdata_22__3353, +com_tlm_u_tlm_tx_vc0_buf_pool_wdata_21__3354, com_tlm_u_tlm_tx_vc0_buf_pool_wdata_20__3355, com_tlm_u_tlm_tx_vc0_buf_pool_wdata_19__3356, +com_tlm_u_tlm_tx_vc0_buf_pool_wdata_18__3357}), + .DIB({com_tlm_u_tlm_tx_vc0_buf_pool_bram_0__size4_bram_array_GND_3461, com_tlm_u_tlm_tx_vc0_buf_pool_bram_0__size4_bram_array_GND_3461, +com_tlm_u_tlm_tx_vc0_buf_pool_bram_0__size4_bram_array_GND_3461, com_tlm_u_tlm_tx_vc0_buf_pool_bram_0__size4_bram_array_GND_3461, +com_tlm_u_tlm_tx_vc0_buf_pool_bram_0__size4_bram_array_GND_3461, com_tlm_u_tlm_tx_vc0_buf_pool_bram_0__size4_bram_array_GND_3461, +com_tlm_u_tlm_tx_vc0_buf_pool_bram_0__size4_bram_array_GND_3461, com_tlm_u_tlm_tx_vc0_buf_pool_bram_0__size4_bram_array_GND_3461, +com_tlm_u_tlm_tx_vc0_buf_pool_bram_0__size4_bram_array_GND_3461, com_tlm_u_tlm_tx_vc0_buf_pool_bram_0__size4_bram_array_GND_3461, +com_tlm_u_tlm_tx_vc0_buf_pool_bram_0__size4_bram_array_GND_3461, com_tlm_u_tlm_tx_vc0_buf_pool_bram_0__size4_bram_array_GND_3461, +com_tlm_u_tlm_tx_vc0_buf_pool_bram_0__size4_bram_array_GND_3461, com_tlm_u_tlm_tx_vc0_buf_pool_bram_0__size4_bram_array_GND_3461, +com_tlm_u_tlm_tx_vc0_buf_pool_bram_0__size4_bram_array_GND_3461, com_tlm_u_tlm_tx_vc0_buf_pool_bram_0__size4_bram_array_GND_3461}), + .DOA({NLW_com_tlm_u_tlm_tx_vc0_buf_pool_bram_0__size4_bram_array_ram_row_0__block_ram_1__ram1024x18_bram_DOA_15__UNCONNECTED, +NLW_com_tlm_u_tlm_tx_vc0_buf_pool_bram_0__size4_bram_array_ram_row_0__block_ram_1__ram1024x18_bram_DOA_14__UNCONNECTED, +NLW_com_tlm_u_tlm_tx_vc0_buf_pool_bram_0__size4_bram_array_ram_row_0__block_ram_1__ram1024x18_bram_DOA_13__UNCONNECTED, +NLW_com_tlm_u_tlm_tx_vc0_buf_pool_bram_0__size4_bram_array_ram_row_0__block_ram_1__ram1024x18_bram_DOA_12__UNCONNECTED, +NLW_com_tlm_u_tlm_tx_vc0_buf_pool_bram_0__size4_bram_array_ram_row_0__block_ram_1__ram1024x18_bram_DOA_11__UNCONNECTED, +NLW_com_tlm_u_tlm_tx_vc0_buf_pool_bram_0__size4_bram_array_ram_row_0__block_ram_1__ram1024x18_bram_DOA_10__UNCONNECTED, +NLW_com_tlm_u_tlm_tx_vc0_buf_pool_bram_0__size4_bram_array_ram_row_0__block_ram_1__ram1024x18_bram_DOA_9__UNCONNECTED, +NLW_com_tlm_u_tlm_tx_vc0_buf_pool_bram_0__size4_bram_array_ram_row_0__block_ram_1__ram1024x18_bram_DOA_8__UNCONNECTED, +NLW_com_tlm_u_tlm_tx_vc0_buf_pool_bram_0__size4_bram_array_ram_row_0__block_ram_1__ram1024x18_bram_DOA_7__UNCONNECTED, +NLW_com_tlm_u_tlm_tx_vc0_buf_pool_bram_0__size4_bram_array_ram_row_0__block_ram_1__ram1024x18_bram_DOA_6__UNCONNECTED, +NLW_com_tlm_u_tlm_tx_vc0_buf_pool_bram_0__size4_bram_array_ram_row_0__block_ram_1__ram1024x18_bram_DOA_5__UNCONNECTED, +NLW_com_tlm_u_tlm_tx_vc0_buf_pool_bram_0__size4_bram_array_ram_row_0__block_ram_1__ram1024x18_bram_DOA_4__UNCONNECTED, +NLW_com_tlm_u_tlm_tx_vc0_buf_pool_bram_0__size4_bram_array_ram_row_0__block_ram_1__ram1024x18_bram_DOA_3__UNCONNECTED, +NLW_com_tlm_u_tlm_tx_vc0_buf_pool_bram_0__size4_bram_array_ram_row_0__block_ram_1__ram1024x18_bram_DOA_2__UNCONNECTED, +NLW_com_tlm_u_tlm_tx_vc0_buf_pool_bram_0__size4_bram_array_ram_row_0__block_ram_1__ram1024x18_bram_DOA_1__UNCONNECTED, +NLW_com_tlm_u_tlm_tx_vc0_buf_pool_bram_0__size4_bram_array_ram_row_0__block_ram_1__ram1024x18_bram_DOA_0__UNCONNECTED}), + .DOB({com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all_33_, com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all_32_, com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all_31_, +com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all_30_, com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all_29_, com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all_28_, +com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all_27_, com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all_26_, com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all_25_, +com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all_24_, com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all_23_, com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all_22_, +com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all_21_, com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all_20_, com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all_19_, +com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all_18_}), + .DIPA({com_tlm_u_tlm_tx_vc0_buf_pool_wdata_35__3340, com_tlm_u_tlm_tx_vc0_buf_pool_wdata_34__3341}), + .DIPB({com_tlm_u_tlm_tx_vc0_buf_pool_bram_0__size4_bram_array_GND_3461, com_tlm_u_tlm_tx_vc0_buf_pool_bram_0__size4_bram_array_GND_3461}) + ); + defparam com_tlm_u_tlm_tx_vc0_buf_pool_bram_0__size4_bram_array_ram_row_0__block_ram_2__ram1024x18_bram.WRITE_MODE_A = "NO_CHANGE"; + RAMB16_S18_S18 com_tlm_u_tlm_tx_vc0_buf_pool_bram_0__size4_bram_array_ram_row_0__block_ram_2__ram1024x18_bram ( + .ENA(com_tlm_u_tlm_tx_vc0_buf_pool_bram_0__size4_bram_array_VCC_3460), + .ENB(com_tlm_u_tlm_tx_vc0_buf_pool_N_10911_i), + .SSRA(com_reset_i_q), + .SSRB(com_reset_i_q), + .WEA(com_tlm_u_tlm_tx_vc0_buf_pool_N_27037_i), + .WEB(com_tlm_u_tlm_tx_vc0_buf_pool_bram_0__size4_bram_array_GND_3461), + .CLKA(NlwRenamedSig_OI_trn_clk), + .CLKB(NlwRenamedSig_OI_trn_clk), + .ADDRA({com_tlm_u_tlm_tx_vc0_buf_pool_waddr_h[2], com_tlm_u_tlm_tx_vc0_buf_pool_waddr_h[1], com_tlm_u_tlm_tx_vc0_buf_pool_waddr_h[0], +com_tlm_u_tlm_tx_vc0_buf_pool_waddr_l[6], com_tlm_u_tlm_tx_vc0_buf_pool_waddr_l[5], com_tlm_u_tlm_tx_vc0_buf_pool_waddr_l[4], +com_tlm_u_tlm_tx_vc0_buf_pool_waddr_l[3], com_tlm_u_tlm_tx_vc0_buf_pool_waddr_l[2], com_tlm_u_tlm_tx_vc0_buf_pool_waddr_l[1], +com_tlm_u_tlm_tx_vc0_buf_pool_waddr_l[0]}), + .DOPA({NLW_com_tlm_u_tlm_tx_vc0_buf_pool_bram_0__size4_bram_array_ram_row_0__block_ram_2__ram1024x18_bram_DOPA_1__UNCONNECTED, +NLW_com_tlm_u_tlm_tx_vc0_buf_pool_bram_0__size4_bram_array_ram_row_0__block_ram_2__ram1024x18_bram_DOPA_0__UNCONNECTED}), + .ADDRB({com_tlm_u_tlm_tx_vc0_buf_pool_raddr_h[2], com_tlm_u_tlm_tx_vc0_buf_pool_raddr_h[1], com_tlm_u_tlm_tx_vc0_buf_pool_raddr_h[0], +com_tlm_u_tlm_tx_vc0_buf_pool_raddr_l[6], com_tlm_u_tlm_tx_vc0_buf_pool_raddr_l[5], com_tlm_u_tlm_tx_vc0_buf_pool_raddr_l[4], +com_tlm_u_tlm_tx_vc0_buf_pool_raddr_l[3], com_tlm_u_tlm_tx_vc0_buf_pool_raddr_l[2], com_tlm_u_tlm_tx_vc0_buf_pool_raddr_l[1], +com_tlm_u_tlm_tx_vc0_buf_pool_raddr_l[0]}), + .DOPB({com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all_53_, com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all_52_}), + .DIA({com_tlm_u_tlm_tx_vc0_buf_pool_wdata_51__3324, com_tlm_u_tlm_tx_vc0_buf_pool_wdata_50__3325, com_tlm_u_tlm_tx_vc0_buf_pool_wdata_49__3326, +com_tlm_u_tlm_tx_vc0_buf_pool_wdata_48__3327, com_tlm_u_tlm_tx_vc0_buf_pool_wdata_47__3328, com_tlm_u_tlm_tx_vc0_buf_pool_wdata_46__3329, +com_tlm_u_tlm_tx_vc0_buf_pool_wdata_45__3330, com_tlm_u_tlm_tx_vc0_buf_pool_wdata_44__3331, com_tlm_u_tlm_tx_vc0_buf_pool_wdata_43__3332, +com_tlm_u_tlm_tx_vc0_buf_pool_wdata_42__3333, com_tlm_u_tlm_tx_vc0_buf_pool_wdata_41__3334, com_tlm_u_tlm_tx_vc0_buf_pool_wdata_40__3335, +com_tlm_u_tlm_tx_vc0_buf_pool_wdata_39__3336, com_tlm_u_tlm_tx_vc0_buf_pool_wdata_38__3337, com_tlm_u_tlm_tx_vc0_buf_pool_wdata_37__3338, +com_tlm_u_tlm_tx_vc0_buf_pool_wdata_36__3339}), + .DIB({com_tlm_u_tlm_tx_vc0_buf_pool_bram_0__size4_bram_array_GND_3461, com_tlm_u_tlm_tx_vc0_buf_pool_bram_0__size4_bram_array_GND_3461, +com_tlm_u_tlm_tx_vc0_buf_pool_bram_0__size4_bram_array_GND_3461, com_tlm_u_tlm_tx_vc0_buf_pool_bram_0__size4_bram_array_GND_3461, +com_tlm_u_tlm_tx_vc0_buf_pool_bram_0__size4_bram_array_GND_3461, com_tlm_u_tlm_tx_vc0_buf_pool_bram_0__size4_bram_array_GND_3461, +com_tlm_u_tlm_tx_vc0_buf_pool_bram_0__size4_bram_array_GND_3461, com_tlm_u_tlm_tx_vc0_buf_pool_bram_0__size4_bram_array_GND_3461, +com_tlm_u_tlm_tx_vc0_buf_pool_bram_0__size4_bram_array_GND_3461, com_tlm_u_tlm_tx_vc0_buf_pool_bram_0__size4_bram_array_GND_3461, +com_tlm_u_tlm_tx_vc0_buf_pool_bram_0__size4_bram_array_GND_3461, com_tlm_u_tlm_tx_vc0_buf_pool_bram_0__size4_bram_array_GND_3461, +com_tlm_u_tlm_tx_vc0_buf_pool_bram_0__size4_bram_array_GND_3461, com_tlm_u_tlm_tx_vc0_buf_pool_bram_0__size4_bram_array_GND_3461, +com_tlm_u_tlm_tx_vc0_buf_pool_bram_0__size4_bram_array_GND_3461, com_tlm_u_tlm_tx_vc0_buf_pool_bram_0__size4_bram_array_GND_3461}), + .DOA({NLW_com_tlm_u_tlm_tx_vc0_buf_pool_bram_0__size4_bram_array_ram_row_0__block_ram_2__ram1024x18_bram_DOA_15__UNCONNECTED, +NLW_com_tlm_u_tlm_tx_vc0_buf_pool_bram_0__size4_bram_array_ram_row_0__block_ram_2__ram1024x18_bram_DOA_14__UNCONNECTED, +NLW_com_tlm_u_tlm_tx_vc0_buf_pool_bram_0__size4_bram_array_ram_row_0__block_ram_2__ram1024x18_bram_DOA_13__UNCONNECTED, +NLW_com_tlm_u_tlm_tx_vc0_buf_pool_bram_0__size4_bram_array_ram_row_0__block_ram_2__ram1024x18_bram_DOA_12__UNCONNECTED, +NLW_com_tlm_u_tlm_tx_vc0_buf_pool_bram_0__size4_bram_array_ram_row_0__block_ram_2__ram1024x18_bram_DOA_11__UNCONNECTED, +NLW_com_tlm_u_tlm_tx_vc0_buf_pool_bram_0__size4_bram_array_ram_row_0__block_ram_2__ram1024x18_bram_DOA_10__UNCONNECTED, +NLW_com_tlm_u_tlm_tx_vc0_buf_pool_bram_0__size4_bram_array_ram_row_0__block_ram_2__ram1024x18_bram_DOA_9__UNCONNECTED, +NLW_com_tlm_u_tlm_tx_vc0_buf_pool_bram_0__size4_bram_array_ram_row_0__block_ram_2__ram1024x18_bram_DOA_8__UNCONNECTED, +NLW_com_tlm_u_tlm_tx_vc0_buf_pool_bram_0__size4_bram_array_ram_row_0__block_ram_2__ram1024x18_bram_DOA_7__UNCONNECTED, +NLW_com_tlm_u_tlm_tx_vc0_buf_pool_bram_0__size4_bram_array_ram_row_0__block_ram_2__ram1024x18_bram_DOA_6__UNCONNECTED, +NLW_com_tlm_u_tlm_tx_vc0_buf_pool_bram_0__size4_bram_array_ram_row_0__block_ram_2__ram1024x18_bram_DOA_5__UNCONNECTED, +NLW_com_tlm_u_tlm_tx_vc0_buf_pool_bram_0__size4_bram_array_ram_row_0__block_ram_2__ram1024x18_bram_DOA_4__UNCONNECTED, +NLW_com_tlm_u_tlm_tx_vc0_buf_pool_bram_0__size4_bram_array_ram_row_0__block_ram_2__ram1024x18_bram_DOA_3__UNCONNECTED, +NLW_com_tlm_u_tlm_tx_vc0_buf_pool_bram_0__size4_bram_array_ram_row_0__block_ram_2__ram1024x18_bram_DOA_2__UNCONNECTED, +NLW_com_tlm_u_tlm_tx_vc0_buf_pool_bram_0__size4_bram_array_ram_row_0__block_ram_2__ram1024x18_bram_DOA_1__UNCONNECTED, +NLW_com_tlm_u_tlm_tx_vc0_buf_pool_bram_0__size4_bram_array_ram_row_0__block_ram_2__ram1024x18_bram_DOA_0__UNCONNECTED}), + .DOB({com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all_51_, com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all_50_, com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all_49_, +com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all_48_, com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all_47_, com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all_46_, +com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all_45_, com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all_44_, com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all_43_, +com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all_42_, com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all_41_, com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all_40_, +com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all_39_, com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all_38_, com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all_37_, +com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all_36_}), + .DIPA({com_tlm_u_tlm_tx_vc0_buf_pool_wdata_53__3322, com_tlm_u_tlm_tx_vc0_buf_pool_wdata_52__3323}), + .DIPB({com_tlm_u_tlm_tx_vc0_buf_pool_bram_0__size4_bram_array_GND_3461, com_tlm_u_tlm_tx_vc0_buf_pool_bram_0__size4_bram_array_GND_3461}) + ); + defparam com_tlm_u_tlm_tx_vc0_buf_pool_bram_0__size4_bram_array_ram_row_0__block_ram_3__ram1024x18_bram.WRITE_MODE_A = "NO_CHANGE"; + RAMB16_S18_S18 com_tlm_u_tlm_tx_vc0_buf_pool_bram_0__size4_bram_array_ram_row_0__block_ram_3__ram1024x18_bram ( + .ENA(com_tlm_u_tlm_tx_vc0_buf_pool_bram_0__size4_bram_array_VCC_3460), + .ENB(com_tlm_u_tlm_tx_vc0_buf_pool_N_10911_i), + .SSRA(com_reset_i_q), + .SSRB(com_reset_i_q), + .WEA(com_tlm_u_tlm_tx_vc0_buf_pool_N_27037_i), + .WEB(com_tlm_u_tlm_tx_vc0_buf_pool_bram_0__size4_bram_array_GND_3461), + .CLKA(NlwRenamedSig_OI_trn_clk), + .CLKB(NlwRenamedSig_OI_trn_clk), + .ADDRA({com_tlm_u_tlm_tx_vc0_buf_pool_waddr_h[2], com_tlm_u_tlm_tx_vc0_buf_pool_waddr_h[1], com_tlm_u_tlm_tx_vc0_buf_pool_waddr_h[0], +com_tlm_u_tlm_tx_vc0_buf_pool_waddr_l[6], com_tlm_u_tlm_tx_vc0_buf_pool_waddr_l[5], com_tlm_u_tlm_tx_vc0_buf_pool_waddr_l[4], +com_tlm_u_tlm_tx_vc0_buf_pool_waddr_l[3], com_tlm_u_tlm_tx_vc0_buf_pool_waddr_l[2], com_tlm_u_tlm_tx_vc0_buf_pool_waddr_l[1], +com_tlm_u_tlm_tx_vc0_buf_pool_waddr_l[0]}), + .DOPA({NLW_com_tlm_u_tlm_tx_vc0_buf_pool_bram_0__size4_bram_array_ram_row_0__block_ram_3__ram1024x18_bram_DOPA_1__UNCONNECTED, +NLW_com_tlm_u_tlm_tx_vc0_buf_pool_bram_0__size4_bram_array_ram_row_0__block_ram_3__ram1024x18_bram_DOPA_0__UNCONNECTED}), + .ADDRB({com_tlm_u_tlm_tx_vc0_buf_pool_raddr_h[2], com_tlm_u_tlm_tx_vc0_buf_pool_raddr_h[1], com_tlm_u_tlm_tx_vc0_buf_pool_raddr_h[0], +com_tlm_u_tlm_tx_vc0_buf_pool_raddr_l[6], com_tlm_u_tlm_tx_vc0_buf_pool_raddr_l[5], com_tlm_u_tlm_tx_vc0_buf_pool_raddr_l[4], +com_tlm_u_tlm_tx_vc0_buf_pool_raddr_l[3], com_tlm_u_tlm_tx_vc0_buf_pool_raddr_l[2], com_tlm_u_tlm_tx_vc0_buf_pool_raddr_l[1], +com_tlm_u_tlm_tx_vc0_buf_pool_raddr_l[0]}), + .DOPB({NLW_com_tlm_u_tlm_tx_vc0_buf_pool_bram_0__size4_bram_array_ram_row_0__block_ram_3__ram1024x18_bram_DOPB_1__UNCONNECTED, +NLW_com_tlm_u_tlm_tx_vc0_buf_pool_bram_0__size4_bram_array_ram_row_0__block_ram_3__ram1024x18_bram_DOPB_0__UNCONNECTED}), + .DIA({com_tlm_u_tlm_tx_vc0_buf_pool_bram_0__size4_bram_array_GND_3461, com_tlm_u_tlm_tx_vc0_buf_pool_wdata_68_, com_tlm_u_tlm_tx_vc0_trn_eof, +com_tlm_u_tlm_tx_vc0_buf_pool_wdata_66__3309, com_tlm_u_tlm_tx_vc0_buf_pool_wdata_65__3310, com_tlm_u_tlm_tx_vc0_buf_pool_wdata_64__3311, +com_tlm_u_tlm_tx_vc0_buf_pool_wdata_63__3312, com_tlm_u_tlm_tx_vc0_buf_pool_wdata_62__3313, com_tlm_u_tlm_tx_vc0_buf_pool_wdata_61__3314, +com_tlm_u_tlm_tx_vc0_buf_pool_wdata_60__3315, com_tlm_u_tlm_tx_vc0_buf_pool_wdata_59__3316, com_tlm_u_tlm_tx_vc0_buf_pool_wdata_58__3317, +com_tlm_u_tlm_tx_vc0_buf_pool_wdata_57__3318, com_tlm_u_tlm_tx_vc0_buf_pool_wdata_56__3319, com_tlm_u_tlm_tx_vc0_buf_pool_wdata_55__3320, +com_tlm_u_tlm_tx_vc0_buf_pool_wdata_54__3321}), + .DIB({com_tlm_u_tlm_tx_vc0_buf_pool_bram_0__size4_bram_array_GND_3461, com_tlm_u_tlm_tx_vc0_buf_pool_bram_0__size4_bram_array_GND_3461, +com_tlm_u_tlm_tx_vc0_buf_pool_bram_0__size4_bram_array_GND_3461, com_tlm_u_tlm_tx_vc0_buf_pool_bram_0__size4_bram_array_GND_3461, +com_tlm_u_tlm_tx_vc0_buf_pool_bram_0__size4_bram_array_GND_3461, com_tlm_u_tlm_tx_vc0_buf_pool_bram_0__size4_bram_array_GND_3461, +com_tlm_u_tlm_tx_vc0_buf_pool_bram_0__size4_bram_array_GND_3461, com_tlm_u_tlm_tx_vc0_buf_pool_bram_0__size4_bram_array_GND_3461, +com_tlm_u_tlm_tx_vc0_buf_pool_bram_0__size4_bram_array_GND_3461, com_tlm_u_tlm_tx_vc0_buf_pool_bram_0__size4_bram_array_GND_3461, +com_tlm_u_tlm_tx_vc0_buf_pool_bram_0__size4_bram_array_GND_3461, com_tlm_u_tlm_tx_vc0_buf_pool_bram_0__size4_bram_array_GND_3461, +com_tlm_u_tlm_tx_vc0_buf_pool_bram_0__size4_bram_array_GND_3461, com_tlm_u_tlm_tx_vc0_buf_pool_bram_0__size4_bram_array_GND_3461, +com_tlm_u_tlm_tx_vc0_buf_pool_bram_0__size4_bram_array_GND_3461, com_tlm_u_tlm_tx_vc0_buf_pool_bram_0__size4_bram_array_GND_3461}), + .DOA({NLW_com_tlm_u_tlm_tx_vc0_buf_pool_bram_0__size4_bram_array_ram_row_0__block_ram_3__ram1024x18_bram_DOA_15__UNCONNECTED, +NLW_com_tlm_u_tlm_tx_vc0_buf_pool_bram_0__size4_bram_array_ram_row_0__block_ram_3__ram1024x18_bram_DOA_14__UNCONNECTED, +NLW_com_tlm_u_tlm_tx_vc0_buf_pool_bram_0__size4_bram_array_ram_row_0__block_ram_3__ram1024x18_bram_DOA_13__UNCONNECTED, +NLW_com_tlm_u_tlm_tx_vc0_buf_pool_bram_0__size4_bram_array_ram_row_0__block_ram_3__ram1024x18_bram_DOA_12__UNCONNECTED, +NLW_com_tlm_u_tlm_tx_vc0_buf_pool_bram_0__size4_bram_array_ram_row_0__block_ram_3__ram1024x18_bram_DOA_11__UNCONNECTED, +NLW_com_tlm_u_tlm_tx_vc0_buf_pool_bram_0__size4_bram_array_ram_row_0__block_ram_3__ram1024x18_bram_DOA_10__UNCONNECTED, +NLW_com_tlm_u_tlm_tx_vc0_buf_pool_bram_0__size4_bram_array_ram_row_0__block_ram_3__ram1024x18_bram_DOA_9__UNCONNECTED, +NLW_com_tlm_u_tlm_tx_vc0_buf_pool_bram_0__size4_bram_array_ram_row_0__block_ram_3__ram1024x18_bram_DOA_8__UNCONNECTED, +NLW_com_tlm_u_tlm_tx_vc0_buf_pool_bram_0__size4_bram_array_ram_row_0__block_ram_3__ram1024x18_bram_DOA_7__UNCONNECTED, +NLW_com_tlm_u_tlm_tx_vc0_buf_pool_bram_0__size4_bram_array_ram_row_0__block_ram_3__ram1024x18_bram_DOA_6__UNCONNECTED, +NLW_com_tlm_u_tlm_tx_vc0_buf_pool_bram_0__size4_bram_array_ram_row_0__block_ram_3__ram1024x18_bram_DOA_5__UNCONNECTED, +NLW_com_tlm_u_tlm_tx_vc0_buf_pool_bram_0__size4_bram_array_ram_row_0__block_ram_3__ram1024x18_bram_DOA_4__UNCONNECTED, +NLW_com_tlm_u_tlm_tx_vc0_buf_pool_bram_0__size4_bram_array_ram_row_0__block_ram_3__ram1024x18_bram_DOA_3__UNCONNECTED, +NLW_com_tlm_u_tlm_tx_vc0_buf_pool_bram_0__size4_bram_array_ram_row_0__block_ram_3__ram1024x18_bram_DOA_2__UNCONNECTED, +NLW_com_tlm_u_tlm_tx_vc0_buf_pool_bram_0__size4_bram_array_ram_row_0__block_ram_3__ram1024x18_bram_DOA_1__UNCONNECTED, +NLW_com_tlm_u_tlm_tx_vc0_buf_pool_bram_0__size4_bram_array_ram_row_0__block_ram_3__ram1024x18_bram_DOA_0__UNCONNECTED}), + .DOB({NLW_com_tlm_u_tlm_tx_vc0_buf_pool_bram_0__size4_bram_array_ram_row_0__block_ram_3__ram1024x18_bram_DOB_15__UNCONNECTED, +com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all_68_, com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all_67_, com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all_66_, +com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all_65_, com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all_64_, com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all_63_, +com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all_62_, com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all_61_, com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all_60_, +com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all_59_, com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all_58_, com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all_57_, +com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all_56_, com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all_55_, com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all_54_}), + .DIPA({com_tlm_u_tlm_tx_vc0_buf_pool_bram_0__size4_bram_array_GND_3461, com_tlm_u_tlm_tx_vc0_buf_pool_bram_0__size4_bram_array_GND_3461}), + .DIPB({com_tlm_u_tlm_tx_vc0_buf_pool_bram_0__size4_bram_array_GND_3461, com_tlm_u_tlm_tx_vc0_buf_pool_bram_0__size4_bram_array_GND_3461}) + ); + defparam com_tlm_u_tlm_tx_vc0_buf_pool_bram_0__size4_bram_array_ren_all_0.INIT = 8'hDC; + LUT3 com_tlm_u_tlm_tx_vc0_buf_pool_bram_0__size4_bram_array_ren_all_0 ( + .I0(com_tlm_u_tlm_tx_vc0_N_56167_i), + .I1(com_reset_i_q), + .I2(com_tlm_u_tlm_tx_vc0_in_frame), + .O(com_tlm_u_tlm_tx_vc0_buf_pool_N_10911_i) + ); + VCC com_tlm_u_tlm_tx_vc0_buf_pool_bram_1__size4_bram_array_VCC ( + .P(com_tlm_u_tlm_tx_vc0_buf_pool_bram_1__size4_bram_array_VCC_3462) + ); + GND com_tlm_u_tlm_tx_vc0_buf_pool_bram_1__size4_bram_array_GND ( + .G(com_tlm_u_tlm_tx_vc0_buf_pool_bram_1__size4_bram_array_GND_3463) + ); + defparam com_tlm_u_tlm_tx_vc0_buf_pool_bram_1__size4_bram_array_ram_row_0__block_ram_0__ram1024x18_bram.WRITE_MODE_A = "NO_CHANGE"; + RAMB16_S18_S18 com_tlm_u_tlm_tx_vc0_buf_pool_bram_1__size4_bram_array_ram_row_0__block_ram_0__ram1024x18_bram ( + .ENA(com_tlm_u_tlm_tx_vc0_buf_pool_bram_1__size4_bram_array_VCC_3462), + .ENB(com_tlm_u_tlm_tx_vc0_buf_pool_N_10911_i), + .SSRA(com_reset_i_q), + .SSRB(com_reset_i_q), + .WEA(com_tlm_u_tlm_tx_vc0_buf_pool_N_27039_i), + .WEB(com_tlm_u_tlm_tx_vc0_buf_pool_bram_1__size4_bram_array_GND_3463), + .CLKA(NlwRenamedSig_OI_trn_clk), + .CLKB(NlwRenamedSig_OI_trn_clk), + .ADDRA({com_tlm_u_tlm_tx_vc0_buf_pool_waddr_h[2], com_tlm_u_tlm_tx_vc0_buf_pool_waddr_h[1], com_tlm_u_tlm_tx_vc0_buf_pool_waddr_h[0], +com_tlm_u_tlm_tx_vc0_buf_pool_waddr_l[6], com_tlm_u_tlm_tx_vc0_buf_pool_waddr_l[5], com_tlm_u_tlm_tx_vc0_buf_pool_waddr_l[4], +com_tlm_u_tlm_tx_vc0_buf_pool_waddr_l[3], com_tlm_u_tlm_tx_vc0_buf_pool_waddr_l[2], com_tlm_u_tlm_tx_vc0_buf_pool_waddr_l[1], +com_tlm_u_tlm_tx_vc0_buf_pool_waddr_l[0]}), + .DOPA({NLW_com_tlm_u_tlm_tx_vc0_buf_pool_bram_1__size4_bram_array_ram_row_0__block_ram_0__ram1024x18_bram_DOPA_1__UNCONNECTED, +NLW_com_tlm_u_tlm_tx_vc0_buf_pool_bram_1__size4_bram_array_ram_row_0__block_ram_0__ram1024x18_bram_DOPA_0__UNCONNECTED}), + .ADDRB({com_tlm_u_tlm_tx_vc0_buf_pool_raddr_h[2], com_tlm_u_tlm_tx_vc0_buf_pool_raddr_h[1], com_tlm_u_tlm_tx_vc0_buf_pool_raddr_h[0], +com_tlm_u_tlm_tx_vc0_buf_pool_raddr_l[6], com_tlm_u_tlm_tx_vc0_buf_pool_raddr_l[5], com_tlm_u_tlm_tx_vc0_buf_pool_raddr_l[4], +com_tlm_u_tlm_tx_vc0_buf_pool_raddr_l[3], com_tlm_u_tlm_tx_vc0_buf_pool_raddr_l[2], com_tlm_u_tlm_tx_vc0_buf_pool_raddr_l[1], +com_tlm_u_tlm_tx_vc0_buf_pool_raddr_l[0]}), + .DOPB({com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all_89_, com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all_88_}), + .DIA({com_tlm_u_tlm_tx_vc0_buf_pool_wdata_15__3360, com_tlm_u_tlm_tx_vc0_buf_pool_wdata_14__3361, com_tlm_u_tlm_tx_vc0_buf_pool_wdata_13__3362, +com_tlm_u_tlm_tx_vc0_buf_pool_wdata_12__3363, com_tlm_u_tlm_tx_vc0_buf_pool_wdata_11__3364, com_tlm_u_tlm_tx_vc0_buf_pool_wdata_10__3365, +com_tlm_u_tlm_tx_vc0_buf_pool_wdata_9__3366, com_tlm_u_tlm_tx_vc0_buf_pool_wdata_8__3367, com_tlm_u_tlm_tx_vc0_buf_pool_wdata_7__3368, +com_tlm_u_tlm_tx_vc0_buf_pool_wdata_6__3369, com_tlm_u_tlm_tx_vc0_buf_pool_wdata_5__3370, com_tlm_u_tlm_tx_vc0_buf_pool_wdata_4__3371, +com_tlm_u_tlm_tx_vc0_buf_pool_wdata_3__3372, com_tlm_u_tlm_tx_vc0_buf_pool_wdata_2__3373, com_tlm_u_tlm_tx_vc0_buf_pool_wdata_1__3374, +com_tlm_u_tlm_tx_vc0_buf_pool_wdata_0__3375}), + .DIB({com_tlm_u_tlm_tx_vc0_buf_pool_bram_1__size4_bram_array_GND_3463, com_tlm_u_tlm_tx_vc0_buf_pool_bram_1__size4_bram_array_GND_3463, +com_tlm_u_tlm_tx_vc0_buf_pool_bram_1__size4_bram_array_GND_3463, com_tlm_u_tlm_tx_vc0_buf_pool_bram_1__size4_bram_array_GND_3463, +com_tlm_u_tlm_tx_vc0_buf_pool_bram_1__size4_bram_array_GND_3463, com_tlm_u_tlm_tx_vc0_buf_pool_bram_1__size4_bram_array_GND_3463, +com_tlm_u_tlm_tx_vc0_buf_pool_bram_1__size4_bram_array_GND_3463, com_tlm_u_tlm_tx_vc0_buf_pool_bram_1__size4_bram_array_GND_3463, +com_tlm_u_tlm_tx_vc0_buf_pool_bram_1__size4_bram_array_GND_3463, com_tlm_u_tlm_tx_vc0_buf_pool_bram_1__size4_bram_array_GND_3463, +com_tlm_u_tlm_tx_vc0_buf_pool_bram_1__size4_bram_array_GND_3463, com_tlm_u_tlm_tx_vc0_buf_pool_bram_1__size4_bram_array_GND_3463, +com_tlm_u_tlm_tx_vc0_buf_pool_bram_1__size4_bram_array_GND_3463, com_tlm_u_tlm_tx_vc0_buf_pool_bram_1__size4_bram_array_GND_3463, +com_tlm_u_tlm_tx_vc0_buf_pool_bram_1__size4_bram_array_GND_3463, com_tlm_u_tlm_tx_vc0_buf_pool_bram_1__size4_bram_array_GND_3463}), + .DOA({NLW_com_tlm_u_tlm_tx_vc0_buf_pool_bram_1__size4_bram_array_ram_row_0__block_ram_0__ram1024x18_bram_DOA_15__UNCONNECTED, +NLW_com_tlm_u_tlm_tx_vc0_buf_pool_bram_1__size4_bram_array_ram_row_0__block_ram_0__ram1024x18_bram_DOA_14__UNCONNECTED, +NLW_com_tlm_u_tlm_tx_vc0_buf_pool_bram_1__size4_bram_array_ram_row_0__block_ram_0__ram1024x18_bram_DOA_13__UNCONNECTED, +NLW_com_tlm_u_tlm_tx_vc0_buf_pool_bram_1__size4_bram_array_ram_row_0__block_ram_0__ram1024x18_bram_DOA_12__UNCONNECTED, +NLW_com_tlm_u_tlm_tx_vc0_buf_pool_bram_1__size4_bram_array_ram_row_0__block_ram_0__ram1024x18_bram_DOA_11__UNCONNECTED, +NLW_com_tlm_u_tlm_tx_vc0_buf_pool_bram_1__size4_bram_array_ram_row_0__block_ram_0__ram1024x18_bram_DOA_10__UNCONNECTED, +NLW_com_tlm_u_tlm_tx_vc0_buf_pool_bram_1__size4_bram_array_ram_row_0__block_ram_0__ram1024x18_bram_DOA_9__UNCONNECTED, +NLW_com_tlm_u_tlm_tx_vc0_buf_pool_bram_1__size4_bram_array_ram_row_0__block_ram_0__ram1024x18_bram_DOA_8__UNCONNECTED, +NLW_com_tlm_u_tlm_tx_vc0_buf_pool_bram_1__size4_bram_array_ram_row_0__block_ram_0__ram1024x18_bram_DOA_7__UNCONNECTED, +NLW_com_tlm_u_tlm_tx_vc0_buf_pool_bram_1__size4_bram_array_ram_row_0__block_ram_0__ram1024x18_bram_DOA_6__UNCONNECTED, +NLW_com_tlm_u_tlm_tx_vc0_buf_pool_bram_1__size4_bram_array_ram_row_0__block_ram_0__ram1024x18_bram_DOA_5__UNCONNECTED, +NLW_com_tlm_u_tlm_tx_vc0_buf_pool_bram_1__size4_bram_array_ram_row_0__block_ram_0__ram1024x18_bram_DOA_4__UNCONNECTED, +NLW_com_tlm_u_tlm_tx_vc0_buf_pool_bram_1__size4_bram_array_ram_row_0__block_ram_0__ram1024x18_bram_DOA_3__UNCONNECTED, +NLW_com_tlm_u_tlm_tx_vc0_buf_pool_bram_1__size4_bram_array_ram_row_0__block_ram_0__ram1024x18_bram_DOA_2__UNCONNECTED, +NLW_com_tlm_u_tlm_tx_vc0_buf_pool_bram_1__size4_bram_array_ram_row_0__block_ram_0__ram1024x18_bram_DOA_1__UNCONNECTED, +NLW_com_tlm_u_tlm_tx_vc0_buf_pool_bram_1__size4_bram_array_ram_row_0__block_ram_0__ram1024x18_bram_DOA_0__UNCONNECTED}), + .DOB({com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all_87_, com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all_86_, com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all_85_, +com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all_84_, com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all_83_, com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all_82_, +com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all_81_, com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all_80_, com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all_79_, +com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all_78_, com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all_77_, com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all_76_, +com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all_75_, com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all_74_, com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all_73_, +com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all_72_}), + .DIPA({com_tlm_u_tlm_tx_vc0_buf_pool_wdata_17__3358, com_tlm_u_tlm_tx_vc0_buf_pool_wdata_16__3359}), + .DIPB({com_tlm_u_tlm_tx_vc0_buf_pool_bram_1__size4_bram_array_GND_3463, com_tlm_u_tlm_tx_vc0_buf_pool_bram_1__size4_bram_array_GND_3463}) + ); + defparam com_tlm_u_tlm_tx_vc0_buf_pool_bram_1__size4_bram_array_ram_row_0__block_ram_1__ram1024x18_bram.WRITE_MODE_A = "NO_CHANGE"; + RAMB16_S18_S18 com_tlm_u_tlm_tx_vc0_buf_pool_bram_1__size4_bram_array_ram_row_0__block_ram_1__ram1024x18_bram ( + .ENA(com_tlm_u_tlm_tx_vc0_buf_pool_bram_1__size4_bram_array_VCC_3462), + .ENB(com_tlm_u_tlm_tx_vc0_buf_pool_N_10911_i), + .SSRA(com_reset_i_q), + .SSRB(com_reset_i_q), + .WEA(com_tlm_u_tlm_tx_vc0_buf_pool_N_27039_i), + .WEB(com_tlm_u_tlm_tx_vc0_buf_pool_bram_1__size4_bram_array_GND_3463), + .CLKA(NlwRenamedSig_OI_trn_clk), + .CLKB(NlwRenamedSig_OI_trn_clk), + .ADDRA({com_tlm_u_tlm_tx_vc0_buf_pool_waddr_h[2], com_tlm_u_tlm_tx_vc0_buf_pool_waddr_h[1], com_tlm_u_tlm_tx_vc0_buf_pool_waddr_h[0], +com_tlm_u_tlm_tx_vc0_buf_pool_waddr_l[6], com_tlm_u_tlm_tx_vc0_buf_pool_waddr_l[5], com_tlm_u_tlm_tx_vc0_buf_pool_waddr_l[4], +com_tlm_u_tlm_tx_vc0_buf_pool_waddr_l[3], com_tlm_u_tlm_tx_vc0_buf_pool_waddr_l[2], com_tlm_u_tlm_tx_vc0_buf_pool_waddr_l[1], +com_tlm_u_tlm_tx_vc0_buf_pool_waddr_l[0]}), + .DOPA({NLW_com_tlm_u_tlm_tx_vc0_buf_pool_bram_1__size4_bram_array_ram_row_0__block_ram_1__ram1024x18_bram_DOPA_1__UNCONNECTED, +NLW_com_tlm_u_tlm_tx_vc0_buf_pool_bram_1__size4_bram_array_ram_row_0__block_ram_1__ram1024x18_bram_DOPA_0__UNCONNECTED}), + .ADDRB({com_tlm_u_tlm_tx_vc0_buf_pool_raddr_h[2], com_tlm_u_tlm_tx_vc0_buf_pool_raddr_h[1], com_tlm_u_tlm_tx_vc0_buf_pool_raddr_h[0], +com_tlm_u_tlm_tx_vc0_buf_pool_raddr_l[6], com_tlm_u_tlm_tx_vc0_buf_pool_raddr_l[5], com_tlm_u_tlm_tx_vc0_buf_pool_raddr_l[4], +com_tlm_u_tlm_tx_vc0_buf_pool_raddr_l[3], com_tlm_u_tlm_tx_vc0_buf_pool_raddr_l[2], com_tlm_u_tlm_tx_vc0_buf_pool_raddr_l[1], +com_tlm_u_tlm_tx_vc0_buf_pool_raddr_l[0]}), + .DOPB({com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all_107_, com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all_106_}), + .DIA({com_tlm_u_tlm_tx_vc0_buf_pool_wdata_33__3342, com_tlm_u_tlm_tx_vc0_buf_pool_wdata_32__3343, com_tlm_u_tlm_tx_vc0_buf_pool_wdata_31__3344, +com_tlm_u_tlm_tx_vc0_buf_pool_wdata_30__3345, com_tlm_u_tlm_tx_vc0_buf_pool_wdata_29__3346, com_tlm_u_tlm_tx_vc0_buf_pool_wdata_28__3347, +com_tlm_u_tlm_tx_vc0_buf_pool_wdata_27__3348, com_tlm_u_tlm_tx_vc0_buf_pool_wdata_26__3349, com_tlm_u_tlm_tx_vc0_buf_pool_wdata_25__3350, +com_tlm_u_tlm_tx_vc0_buf_pool_wdata_24__3351, com_tlm_u_tlm_tx_vc0_buf_pool_wdata_23__3352, com_tlm_u_tlm_tx_vc0_buf_pool_wdata_22__3353, +com_tlm_u_tlm_tx_vc0_buf_pool_wdata_21__3354, com_tlm_u_tlm_tx_vc0_buf_pool_wdata_20__3355, com_tlm_u_tlm_tx_vc0_buf_pool_wdata_19__3356, +com_tlm_u_tlm_tx_vc0_buf_pool_wdata_18__3357}), + .DIB({com_tlm_u_tlm_tx_vc0_buf_pool_bram_1__size4_bram_array_GND_3463, com_tlm_u_tlm_tx_vc0_buf_pool_bram_1__size4_bram_array_GND_3463, +com_tlm_u_tlm_tx_vc0_buf_pool_bram_1__size4_bram_array_GND_3463, com_tlm_u_tlm_tx_vc0_buf_pool_bram_1__size4_bram_array_GND_3463, +com_tlm_u_tlm_tx_vc0_buf_pool_bram_1__size4_bram_array_GND_3463, com_tlm_u_tlm_tx_vc0_buf_pool_bram_1__size4_bram_array_GND_3463, +com_tlm_u_tlm_tx_vc0_buf_pool_bram_1__size4_bram_array_GND_3463, com_tlm_u_tlm_tx_vc0_buf_pool_bram_1__size4_bram_array_GND_3463, +com_tlm_u_tlm_tx_vc0_buf_pool_bram_1__size4_bram_array_GND_3463, com_tlm_u_tlm_tx_vc0_buf_pool_bram_1__size4_bram_array_GND_3463, +com_tlm_u_tlm_tx_vc0_buf_pool_bram_1__size4_bram_array_GND_3463, com_tlm_u_tlm_tx_vc0_buf_pool_bram_1__size4_bram_array_GND_3463, +com_tlm_u_tlm_tx_vc0_buf_pool_bram_1__size4_bram_array_GND_3463, com_tlm_u_tlm_tx_vc0_buf_pool_bram_1__size4_bram_array_GND_3463, +com_tlm_u_tlm_tx_vc0_buf_pool_bram_1__size4_bram_array_GND_3463, com_tlm_u_tlm_tx_vc0_buf_pool_bram_1__size4_bram_array_GND_3463}), + .DOA({NLW_com_tlm_u_tlm_tx_vc0_buf_pool_bram_1__size4_bram_array_ram_row_0__block_ram_1__ram1024x18_bram_DOA_15__UNCONNECTED, +NLW_com_tlm_u_tlm_tx_vc0_buf_pool_bram_1__size4_bram_array_ram_row_0__block_ram_1__ram1024x18_bram_DOA_14__UNCONNECTED, +NLW_com_tlm_u_tlm_tx_vc0_buf_pool_bram_1__size4_bram_array_ram_row_0__block_ram_1__ram1024x18_bram_DOA_13__UNCONNECTED, +NLW_com_tlm_u_tlm_tx_vc0_buf_pool_bram_1__size4_bram_array_ram_row_0__block_ram_1__ram1024x18_bram_DOA_12__UNCONNECTED, +NLW_com_tlm_u_tlm_tx_vc0_buf_pool_bram_1__size4_bram_array_ram_row_0__block_ram_1__ram1024x18_bram_DOA_11__UNCONNECTED, +NLW_com_tlm_u_tlm_tx_vc0_buf_pool_bram_1__size4_bram_array_ram_row_0__block_ram_1__ram1024x18_bram_DOA_10__UNCONNECTED, +NLW_com_tlm_u_tlm_tx_vc0_buf_pool_bram_1__size4_bram_array_ram_row_0__block_ram_1__ram1024x18_bram_DOA_9__UNCONNECTED, +NLW_com_tlm_u_tlm_tx_vc0_buf_pool_bram_1__size4_bram_array_ram_row_0__block_ram_1__ram1024x18_bram_DOA_8__UNCONNECTED, +NLW_com_tlm_u_tlm_tx_vc0_buf_pool_bram_1__size4_bram_array_ram_row_0__block_ram_1__ram1024x18_bram_DOA_7__UNCONNECTED, +NLW_com_tlm_u_tlm_tx_vc0_buf_pool_bram_1__size4_bram_array_ram_row_0__block_ram_1__ram1024x18_bram_DOA_6__UNCONNECTED, +NLW_com_tlm_u_tlm_tx_vc0_buf_pool_bram_1__size4_bram_array_ram_row_0__block_ram_1__ram1024x18_bram_DOA_5__UNCONNECTED, +NLW_com_tlm_u_tlm_tx_vc0_buf_pool_bram_1__size4_bram_array_ram_row_0__block_ram_1__ram1024x18_bram_DOA_4__UNCONNECTED, +NLW_com_tlm_u_tlm_tx_vc0_buf_pool_bram_1__size4_bram_array_ram_row_0__block_ram_1__ram1024x18_bram_DOA_3__UNCONNECTED, +NLW_com_tlm_u_tlm_tx_vc0_buf_pool_bram_1__size4_bram_array_ram_row_0__block_ram_1__ram1024x18_bram_DOA_2__UNCONNECTED, +NLW_com_tlm_u_tlm_tx_vc0_buf_pool_bram_1__size4_bram_array_ram_row_0__block_ram_1__ram1024x18_bram_DOA_1__UNCONNECTED, +NLW_com_tlm_u_tlm_tx_vc0_buf_pool_bram_1__size4_bram_array_ram_row_0__block_ram_1__ram1024x18_bram_DOA_0__UNCONNECTED}), + .DOB({com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all_105_, com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all_104_, com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all_103_, +com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all_102_, com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all_101_, com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all_100_, +com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all_99_, com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all_98_, com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all_97_, +com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all_96_, com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all_95_, com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all_94_, +com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all_93_, com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all_92_, com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all_91_, +com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all_90_}), + .DIPA({com_tlm_u_tlm_tx_vc0_buf_pool_wdata_35__3340, com_tlm_u_tlm_tx_vc0_buf_pool_wdata_34__3341}), + .DIPB({com_tlm_u_tlm_tx_vc0_buf_pool_bram_1__size4_bram_array_GND_3463, com_tlm_u_tlm_tx_vc0_buf_pool_bram_1__size4_bram_array_GND_3463}) + ); + defparam com_tlm_u_tlm_tx_vc0_buf_pool_bram_1__size4_bram_array_ram_row_0__block_ram_2__ram1024x18_bram.WRITE_MODE_A = "NO_CHANGE"; + RAMB16_S18_S18 com_tlm_u_tlm_tx_vc0_buf_pool_bram_1__size4_bram_array_ram_row_0__block_ram_2__ram1024x18_bram ( + .ENA(com_tlm_u_tlm_tx_vc0_buf_pool_bram_1__size4_bram_array_VCC_3462), + .ENB(com_tlm_u_tlm_tx_vc0_buf_pool_N_10911_i), + .SSRA(com_reset_i_q), + .SSRB(com_reset_i_q), + .WEA(com_tlm_u_tlm_tx_vc0_buf_pool_N_27039_i), + .WEB(com_tlm_u_tlm_tx_vc0_buf_pool_bram_1__size4_bram_array_GND_3463), + .CLKA(NlwRenamedSig_OI_trn_clk), + .CLKB(NlwRenamedSig_OI_trn_clk), + .ADDRA({com_tlm_u_tlm_tx_vc0_buf_pool_waddr_h[2], com_tlm_u_tlm_tx_vc0_buf_pool_waddr_h[1], com_tlm_u_tlm_tx_vc0_buf_pool_waddr_h[0], +com_tlm_u_tlm_tx_vc0_buf_pool_waddr_l[6], com_tlm_u_tlm_tx_vc0_buf_pool_waddr_l[5], com_tlm_u_tlm_tx_vc0_buf_pool_waddr_l[4], +com_tlm_u_tlm_tx_vc0_buf_pool_waddr_l[3], com_tlm_u_tlm_tx_vc0_buf_pool_waddr_l[2], com_tlm_u_tlm_tx_vc0_buf_pool_waddr_l[1], +com_tlm_u_tlm_tx_vc0_buf_pool_waddr_l[0]}), + .DOPA({NLW_com_tlm_u_tlm_tx_vc0_buf_pool_bram_1__size4_bram_array_ram_row_0__block_ram_2__ram1024x18_bram_DOPA_1__UNCONNECTED, +NLW_com_tlm_u_tlm_tx_vc0_buf_pool_bram_1__size4_bram_array_ram_row_0__block_ram_2__ram1024x18_bram_DOPA_0__UNCONNECTED}), + .ADDRB({com_tlm_u_tlm_tx_vc0_buf_pool_raddr_h[2], com_tlm_u_tlm_tx_vc0_buf_pool_raddr_h[1], com_tlm_u_tlm_tx_vc0_buf_pool_raddr_h[0], +com_tlm_u_tlm_tx_vc0_buf_pool_raddr_l[6], com_tlm_u_tlm_tx_vc0_buf_pool_raddr_l[5], com_tlm_u_tlm_tx_vc0_buf_pool_raddr_l[4], +com_tlm_u_tlm_tx_vc0_buf_pool_raddr_l[3], com_tlm_u_tlm_tx_vc0_buf_pool_raddr_l[2], com_tlm_u_tlm_tx_vc0_buf_pool_raddr_l[1], +com_tlm_u_tlm_tx_vc0_buf_pool_raddr_l[0]}), + .DOPB({com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all_125_, com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all_124_}), + .DIA({com_tlm_u_tlm_tx_vc0_buf_pool_wdata_51__3324, com_tlm_u_tlm_tx_vc0_buf_pool_wdata_50__3325, com_tlm_u_tlm_tx_vc0_buf_pool_wdata_49__3326, +com_tlm_u_tlm_tx_vc0_buf_pool_wdata_48__3327, com_tlm_u_tlm_tx_vc0_buf_pool_wdata_47__3328, com_tlm_u_tlm_tx_vc0_buf_pool_wdata_46__3329, +com_tlm_u_tlm_tx_vc0_buf_pool_wdata_45__3330, com_tlm_u_tlm_tx_vc0_buf_pool_wdata_44__3331, com_tlm_u_tlm_tx_vc0_buf_pool_wdata_43__3332, +com_tlm_u_tlm_tx_vc0_buf_pool_wdata_42__3333, com_tlm_u_tlm_tx_vc0_buf_pool_wdata_41__3334, com_tlm_u_tlm_tx_vc0_buf_pool_wdata_40__3335, +com_tlm_u_tlm_tx_vc0_buf_pool_wdata_39__3336, com_tlm_u_tlm_tx_vc0_buf_pool_wdata_38__3337, com_tlm_u_tlm_tx_vc0_buf_pool_wdata_37__3338, +com_tlm_u_tlm_tx_vc0_buf_pool_wdata_36__3339}), + .DIB({com_tlm_u_tlm_tx_vc0_buf_pool_bram_1__size4_bram_array_GND_3463, com_tlm_u_tlm_tx_vc0_buf_pool_bram_1__size4_bram_array_GND_3463, +com_tlm_u_tlm_tx_vc0_buf_pool_bram_1__size4_bram_array_GND_3463, com_tlm_u_tlm_tx_vc0_buf_pool_bram_1__size4_bram_array_GND_3463, +com_tlm_u_tlm_tx_vc0_buf_pool_bram_1__size4_bram_array_GND_3463, com_tlm_u_tlm_tx_vc0_buf_pool_bram_1__size4_bram_array_GND_3463, +com_tlm_u_tlm_tx_vc0_buf_pool_bram_1__size4_bram_array_GND_3463, com_tlm_u_tlm_tx_vc0_buf_pool_bram_1__size4_bram_array_GND_3463, +com_tlm_u_tlm_tx_vc0_buf_pool_bram_1__size4_bram_array_GND_3463, com_tlm_u_tlm_tx_vc0_buf_pool_bram_1__size4_bram_array_GND_3463, +com_tlm_u_tlm_tx_vc0_buf_pool_bram_1__size4_bram_array_GND_3463, com_tlm_u_tlm_tx_vc0_buf_pool_bram_1__size4_bram_array_GND_3463, +com_tlm_u_tlm_tx_vc0_buf_pool_bram_1__size4_bram_array_GND_3463, com_tlm_u_tlm_tx_vc0_buf_pool_bram_1__size4_bram_array_GND_3463, +com_tlm_u_tlm_tx_vc0_buf_pool_bram_1__size4_bram_array_GND_3463, com_tlm_u_tlm_tx_vc0_buf_pool_bram_1__size4_bram_array_GND_3463}), + .DOA({NLW_com_tlm_u_tlm_tx_vc0_buf_pool_bram_1__size4_bram_array_ram_row_0__block_ram_2__ram1024x18_bram_DOA_15__UNCONNECTED, +NLW_com_tlm_u_tlm_tx_vc0_buf_pool_bram_1__size4_bram_array_ram_row_0__block_ram_2__ram1024x18_bram_DOA_14__UNCONNECTED, +NLW_com_tlm_u_tlm_tx_vc0_buf_pool_bram_1__size4_bram_array_ram_row_0__block_ram_2__ram1024x18_bram_DOA_13__UNCONNECTED, +NLW_com_tlm_u_tlm_tx_vc0_buf_pool_bram_1__size4_bram_array_ram_row_0__block_ram_2__ram1024x18_bram_DOA_12__UNCONNECTED, +NLW_com_tlm_u_tlm_tx_vc0_buf_pool_bram_1__size4_bram_array_ram_row_0__block_ram_2__ram1024x18_bram_DOA_11__UNCONNECTED, +NLW_com_tlm_u_tlm_tx_vc0_buf_pool_bram_1__size4_bram_array_ram_row_0__block_ram_2__ram1024x18_bram_DOA_10__UNCONNECTED, +NLW_com_tlm_u_tlm_tx_vc0_buf_pool_bram_1__size4_bram_array_ram_row_0__block_ram_2__ram1024x18_bram_DOA_9__UNCONNECTED, +NLW_com_tlm_u_tlm_tx_vc0_buf_pool_bram_1__size4_bram_array_ram_row_0__block_ram_2__ram1024x18_bram_DOA_8__UNCONNECTED, +NLW_com_tlm_u_tlm_tx_vc0_buf_pool_bram_1__size4_bram_array_ram_row_0__block_ram_2__ram1024x18_bram_DOA_7__UNCONNECTED, +NLW_com_tlm_u_tlm_tx_vc0_buf_pool_bram_1__size4_bram_array_ram_row_0__block_ram_2__ram1024x18_bram_DOA_6__UNCONNECTED, +NLW_com_tlm_u_tlm_tx_vc0_buf_pool_bram_1__size4_bram_array_ram_row_0__block_ram_2__ram1024x18_bram_DOA_5__UNCONNECTED, +NLW_com_tlm_u_tlm_tx_vc0_buf_pool_bram_1__size4_bram_array_ram_row_0__block_ram_2__ram1024x18_bram_DOA_4__UNCONNECTED, +NLW_com_tlm_u_tlm_tx_vc0_buf_pool_bram_1__size4_bram_array_ram_row_0__block_ram_2__ram1024x18_bram_DOA_3__UNCONNECTED, +NLW_com_tlm_u_tlm_tx_vc0_buf_pool_bram_1__size4_bram_array_ram_row_0__block_ram_2__ram1024x18_bram_DOA_2__UNCONNECTED, +NLW_com_tlm_u_tlm_tx_vc0_buf_pool_bram_1__size4_bram_array_ram_row_0__block_ram_2__ram1024x18_bram_DOA_1__UNCONNECTED, +NLW_com_tlm_u_tlm_tx_vc0_buf_pool_bram_1__size4_bram_array_ram_row_0__block_ram_2__ram1024x18_bram_DOA_0__UNCONNECTED}), + .DOB({com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all_123_, com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all_122_, com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all_121_, +com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all_120_, com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all_119_, com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all_118_, +com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all_117_, com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all_116_, com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all_115_, +com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all_114_, com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all_113_, com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all_112_, +com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all_111_, com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all_110_, com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all_109_, +com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all_108_}), + .DIPA({com_tlm_u_tlm_tx_vc0_buf_pool_wdata_53__3322, com_tlm_u_tlm_tx_vc0_buf_pool_wdata_52__3323}), + .DIPB({com_tlm_u_tlm_tx_vc0_buf_pool_bram_1__size4_bram_array_GND_3463, com_tlm_u_tlm_tx_vc0_buf_pool_bram_1__size4_bram_array_GND_3463}) + ); + defparam com_tlm_u_tlm_tx_vc0_buf_pool_bram_1__size4_bram_array_ram_row_0__block_ram_3__ram1024x18_bram.WRITE_MODE_A = "NO_CHANGE"; + RAMB16_S18_S18 com_tlm_u_tlm_tx_vc0_buf_pool_bram_1__size4_bram_array_ram_row_0__block_ram_3__ram1024x18_bram ( + .ENA(com_tlm_u_tlm_tx_vc0_buf_pool_bram_1__size4_bram_array_VCC_3462), + .ENB(com_tlm_u_tlm_tx_vc0_buf_pool_N_10911_i), + .SSRA(com_reset_i_q), + .SSRB(com_reset_i_q), + .WEA(com_tlm_u_tlm_tx_vc0_buf_pool_N_27039_i), + .WEB(com_tlm_u_tlm_tx_vc0_buf_pool_bram_1__size4_bram_array_GND_3463), + .CLKA(NlwRenamedSig_OI_trn_clk), + .CLKB(NlwRenamedSig_OI_trn_clk), + .ADDRA({com_tlm_u_tlm_tx_vc0_buf_pool_waddr_h[2], com_tlm_u_tlm_tx_vc0_buf_pool_waddr_h[1], com_tlm_u_tlm_tx_vc0_buf_pool_waddr_h[0], +com_tlm_u_tlm_tx_vc0_buf_pool_waddr_l[6], com_tlm_u_tlm_tx_vc0_buf_pool_waddr_l[5], com_tlm_u_tlm_tx_vc0_buf_pool_waddr_l[4], +com_tlm_u_tlm_tx_vc0_buf_pool_waddr_l[3], com_tlm_u_tlm_tx_vc0_buf_pool_waddr_l[2], com_tlm_u_tlm_tx_vc0_buf_pool_waddr_l[1], +com_tlm_u_tlm_tx_vc0_buf_pool_waddr_l[0]}), + .DOPA({NLW_com_tlm_u_tlm_tx_vc0_buf_pool_bram_1__size4_bram_array_ram_row_0__block_ram_3__ram1024x18_bram_DOPA_1__UNCONNECTED, +NLW_com_tlm_u_tlm_tx_vc0_buf_pool_bram_1__size4_bram_array_ram_row_0__block_ram_3__ram1024x18_bram_DOPA_0__UNCONNECTED}), + .ADDRB({com_tlm_u_tlm_tx_vc0_buf_pool_raddr_h[2], com_tlm_u_tlm_tx_vc0_buf_pool_raddr_h[1], com_tlm_u_tlm_tx_vc0_buf_pool_raddr_h[0], +com_tlm_u_tlm_tx_vc0_buf_pool_raddr_l[6], com_tlm_u_tlm_tx_vc0_buf_pool_raddr_l[5], com_tlm_u_tlm_tx_vc0_buf_pool_raddr_l[4], +com_tlm_u_tlm_tx_vc0_buf_pool_raddr_l[3], com_tlm_u_tlm_tx_vc0_buf_pool_raddr_l[2], com_tlm_u_tlm_tx_vc0_buf_pool_raddr_l[1], +com_tlm_u_tlm_tx_vc0_buf_pool_raddr_l[0]}), + .DOPB({NLW_com_tlm_u_tlm_tx_vc0_buf_pool_bram_1__size4_bram_array_ram_row_0__block_ram_3__ram1024x18_bram_DOPB_1__UNCONNECTED, +NLW_com_tlm_u_tlm_tx_vc0_buf_pool_bram_1__size4_bram_array_ram_row_0__block_ram_3__ram1024x18_bram_DOPB_0__UNCONNECTED}), + .DIA({com_tlm_u_tlm_tx_vc0_buf_pool_bram_1__size4_bram_array_GND_3463, com_tlm_u_tlm_tx_vc0_buf_pool_wdata_68_, com_tlm_u_tlm_tx_vc0_trn_eof, +com_tlm_u_tlm_tx_vc0_buf_pool_wdata_66__3309, com_tlm_u_tlm_tx_vc0_buf_pool_wdata_65__3310, com_tlm_u_tlm_tx_vc0_buf_pool_wdata_64__3311, +com_tlm_u_tlm_tx_vc0_buf_pool_wdata_63__3312, com_tlm_u_tlm_tx_vc0_buf_pool_wdata_62__3313, com_tlm_u_tlm_tx_vc0_buf_pool_wdata_61__3314, +com_tlm_u_tlm_tx_vc0_buf_pool_wdata_60__3315, com_tlm_u_tlm_tx_vc0_buf_pool_wdata_59__3316, com_tlm_u_tlm_tx_vc0_buf_pool_wdata_58__3317, +com_tlm_u_tlm_tx_vc0_buf_pool_wdata_57__3318, com_tlm_u_tlm_tx_vc0_buf_pool_wdata_56__3319, com_tlm_u_tlm_tx_vc0_buf_pool_wdata_55__3320, +com_tlm_u_tlm_tx_vc0_buf_pool_wdata_54__3321}), + .DIB({com_tlm_u_tlm_tx_vc0_buf_pool_bram_1__size4_bram_array_GND_3463, com_tlm_u_tlm_tx_vc0_buf_pool_bram_1__size4_bram_array_GND_3463, +com_tlm_u_tlm_tx_vc0_buf_pool_bram_1__size4_bram_array_GND_3463, com_tlm_u_tlm_tx_vc0_buf_pool_bram_1__size4_bram_array_GND_3463, +com_tlm_u_tlm_tx_vc0_buf_pool_bram_1__size4_bram_array_GND_3463, com_tlm_u_tlm_tx_vc0_buf_pool_bram_1__size4_bram_array_GND_3463, +com_tlm_u_tlm_tx_vc0_buf_pool_bram_1__size4_bram_array_GND_3463, com_tlm_u_tlm_tx_vc0_buf_pool_bram_1__size4_bram_array_GND_3463, +com_tlm_u_tlm_tx_vc0_buf_pool_bram_1__size4_bram_array_GND_3463, com_tlm_u_tlm_tx_vc0_buf_pool_bram_1__size4_bram_array_GND_3463, +com_tlm_u_tlm_tx_vc0_buf_pool_bram_1__size4_bram_array_GND_3463, com_tlm_u_tlm_tx_vc0_buf_pool_bram_1__size4_bram_array_GND_3463, +com_tlm_u_tlm_tx_vc0_buf_pool_bram_1__size4_bram_array_GND_3463, com_tlm_u_tlm_tx_vc0_buf_pool_bram_1__size4_bram_array_GND_3463, +com_tlm_u_tlm_tx_vc0_buf_pool_bram_1__size4_bram_array_GND_3463, com_tlm_u_tlm_tx_vc0_buf_pool_bram_1__size4_bram_array_GND_3463}), + .DOA({NLW_com_tlm_u_tlm_tx_vc0_buf_pool_bram_1__size4_bram_array_ram_row_0__block_ram_3__ram1024x18_bram_DOA_15__UNCONNECTED, +NLW_com_tlm_u_tlm_tx_vc0_buf_pool_bram_1__size4_bram_array_ram_row_0__block_ram_3__ram1024x18_bram_DOA_14__UNCONNECTED, +NLW_com_tlm_u_tlm_tx_vc0_buf_pool_bram_1__size4_bram_array_ram_row_0__block_ram_3__ram1024x18_bram_DOA_13__UNCONNECTED, +NLW_com_tlm_u_tlm_tx_vc0_buf_pool_bram_1__size4_bram_array_ram_row_0__block_ram_3__ram1024x18_bram_DOA_12__UNCONNECTED, +NLW_com_tlm_u_tlm_tx_vc0_buf_pool_bram_1__size4_bram_array_ram_row_0__block_ram_3__ram1024x18_bram_DOA_11__UNCONNECTED, +NLW_com_tlm_u_tlm_tx_vc0_buf_pool_bram_1__size4_bram_array_ram_row_0__block_ram_3__ram1024x18_bram_DOA_10__UNCONNECTED, +NLW_com_tlm_u_tlm_tx_vc0_buf_pool_bram_1__size4_bram_array_ram_row_0__block_ram_3__ram1024x18_bram_DOA_9__UNCONNECTED, +NLW_com_tlm_u_tlm_tx_vc0_buf_pool_bram_1__size4_bram_array_ram_row_0__block_ram_3__ram1024x18_bram_DOA_8__UNCONNECTED, +NLW_com_tlm_u_tlm_tx_vc0_buf_pool_bram_1__size4_bram_array_ram_row_0__block_ram_3__ram1024x18_bram_DOA_7__UNCONNECTED, +NLW_com_tlm_u_tlm_tx_vc0_buf_pool_bram_1__size4_bram_array_ram_row_0__block_ram_3__ram1024x18_bram_DOA_6__UNCONNECTED, +NLW_com_tlm_u_tlm_tx_vc0_buf_pool_bram_1__size4_bram_array_ram_row_0__block_ram_3__ram1024x18_bram_DOA_5__UNCONNECTED, +NLW_com_tlm_u_tlm_tx_vc0_buf_pool_bram_1__size4_bram_array_ram_row_0__block_ram_3__ram1024x18_bram_DOA_4__UNCONNECTED, +NLW_com_tlm_u_tlm_tx_vc0_buf_pool_bram_1__size4_bram_array_ram_row_0__block_ram_3__ram1024x18_bram_DOA_3__UNCONNECTED, +NLW_com_tlm_u_tlm_tx_vc0_buf_pool_bram_1__size4_bram_array_ram_row_0__block_ram_3__ram1024x18_bram_DOA_2__UNCONNECTED, +NLW_com_tlm_u_tlm_tx_vc0_buf_pool_bram_1__size4_bram_array_ram_row_0__block_ram_3__ram1024x18_bram_DOA_1__UNCONNECTED, +NLW_com_tlm_u_tlm_tx_vc0_buf_pool_bram_1__size4_bram_array_ram_row_0__block_ram_3__ram1024x18_bram_DOA_0__UNCONNECTED}), + .DOB({NLW_com_tlm_u_tlm_tx_vc0_buf_pool_bram_1__size4_bram_array_ram_row_0__block_ram_3__ram1024x18_bram_DOB_15__UNCONNECTED, +com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all_140_, com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all_139_, com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all_138_, +com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all_137_, com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all_136_, com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all_135_, +com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all_134_, com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all_133_, com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all_132_, +com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all_131_, com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all_130_, com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all_129_, +com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all_128_, com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all_127_, com_tlm_u_tlm_tx_vc0_buf_pool_rdata_all_126_}), + .DIPA({com_tlm_u_tlm_tx_vc0_buf_pool_bram_1__size4_bram_array_GND_3463, com_tlm_u_tlm_tx_vc0_buf_pool_bram_1__size4_bram_array_GND_3463}), + .DIPB({com_tlm_u_tlm_tx_vc0_buf_pool_bram_1__size4_bram_array_GND_3463, com_tlm_u_tlm_tx_vc0_buf_pool_bram_1__size4_bram_array_GND_3463}) + ); + VCC com_tlm_u_tlm_tx_vc0_trn_VCC ( + .P(com_tlm_u_tlm_tx_vc0_trn_VCC_3557) + ); + GND com_tlm_u_tlm_tx_vc0_trn_GND ( + .G(com_tlm_u_tlm_tx_vc0_trn_GND_3555) + ); + FDR com_tlm_u_tlm_tx_vc0_trn_pkts_in_trn_0_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_trn_un1_pkts_in_trn_1_axb0_3519), + .Q(com_tlm_u_tlm_tx_vc0_trn_pkts_in_trn[0]), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_tx_vc0_trn_pkts_in_trn_1_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_trn_un1_pkts_in_trn_1_axbxc1_3516), + .Q(com_tlm_u_tlm_tx_vc0_trn_pkts_in_trn[1]), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_tx_vc0_trn_trn_tbuf_av_o_0_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_trn_un1_trn_tbuf_av_o_1_axb_0_3484), + .Q(NlwRenamedSig_OI_trn_tbuf_av[0]), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_tx_vc0_trn_trn_tbuf_av_o_1_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_trn_un1_trn_tbuf_av_o_1_s_1_3465), + .Q(NlwRenamedSig_OI_trn_tbuf_av[1]), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_tx_vc0_trn_trn_tbuf_av_o_2_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_trn_un1_trn_tbuf_av_o_1_s_2_3468), + .Q(NlwRenamedSig_OI_trn_tbuf_av[2]), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_tx_vc0_trn_trn_tbuf_av_o_3_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_trn_un1_trn_tbuf_av_o_1_s_3_3471), + .Q(NlwRenamedSig_OI_trn_tbuf_av[3]), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_tx_vc0_trn_trn_tbuf_av_o_4_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_trn_un1_trn_tbuf_av_o_1_s_4_3473), + .Q(NlwRenamedSig_OI_trn_tbuf_av[4]), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_tx_vc0_trn_buffer_rdy ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_trn_N_42911_i), + .Q(com_tlm_u_tlm_tx_vc0_trn_buffer_rdy_3480), + .R(plm_link_up_i) + ); + FDSE com_tlm_u_tlm_tx_vc0_trn_buf_av_one ( + .CE(com_tlm_u_tlm_tx_vc0_trn_N_85887_i_3523), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_trn_N_44071_i), + .Q(com_tlm_u_tlm_tx_vc0_trn_buf_av_one_3511), + .S(plm_link_up_i) + ); + FDSE com_tlm_u_tlm_tx_vc0_trn_buf_av_zero ( + .CE(com_tlm_u_tlm_tx_vc0_trn_N_86362_i_3488), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_trn_N_44071_i), + .Q(com_tlm_u_tlm_tx_vc0_trn_buf_av_zero_3479), + .S(plm_link_up_i) + ); + FDR com_tlm_u_tlm_tx_vc0_trn_trn_tdst_rdy_o ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_trn_N_86293_i_3508), + .Q(com_tlm_u_tlm_tx_vc0_trn_trn_tdst_rdy), + .R(plm_link_up_i) + ); + FDRSE com_tlm_u_tlm_tx_vc0_trn_usr_calc_eof ( + .CE(com_tlm_u_tlm_tx_vc0_trn_N_55997_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_trn_GND_3555), + .Q(com_tlm_u_tlm_tx_vc0_trn_usr_calc_eof_3489), + .R(plm_link_up_i), + .S(com_tlm_u_tlm_tx_vc0_trn_N_42906_i) + ); + FDR com_tlm_u_tlm_tx_vc0_trn_cmm_tdst_rdy_o ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_trn_N_86737_i_3506), + .Q(com_cmmt_tdst_rdy), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_tx_vc0_trn_dsc_in_q ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_trn_N_42903_i), + .Q(com_tlm_u_tlm_tx_vc0_trn_dsc_in_q_3478), + .R(plm_link_up_i) + ); + FDRS com_tlm_u_tlm_tx_vc0_trn_vld_o ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_trn_N_86547_i_3505), + .Q(com_tlm_u_tlm_tx_vc0_trn_vld), + .R(plm_link_up_i), + .S(com_tlm_u_tlm_tx_vc0_trn_vld_o_5_i_0_a2_3564) + ); + FDS com_tlm_u_tlm_tx_vc0_trn_rem_o ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_trn_N_85836_i_3561), + .Q(com_tlm_u_tlm_tx_vc0_trn_trn_rem), + .S(plm_link_up_i) + ); + FDR com_tlm_u_tlm_tx_vc0_trn_sof_o ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_trn_N_86736_i_3502), + .Q(com_tlm_u_tlm_tx_vc0_trn_sof), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_tx_vc0_trn_errfwd_o ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_trn_N_16678_i), + .Q(com_tlm_u_tlm_tx_vc0_trn_errfwd), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_tx_vc0_trn_eof_o ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_trn_N_16676_i), + .Q(com_tlm_u_tlm_tx_vc0_trn_eof), + .R(plm_link_up_i) + ); + FDRSE com_tlm_u_tlm_tx_vc0_trn_usr_frame ( + .CE(com_tlm_u_tlm_tx_vc0_trn_N_86735_i_3481), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_trn_GND_3555), + .Q(com_tlm_u_tlm_tx_vc0_trn_usr_frame_3504), + .R(plm_link_up_i), + .S(com_tlm_u_tlm_tx_vc0_trn_un1_usr_vld_0_a2_0_a2_0_a2_3475) + ); + FDRE com_tlm_u_tlm_tx_vc0_trn_usr_frame_in ( + .CE(com_tlm_u_tlm_tx_vc0_trn_N_85889_i_3483), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_trn_usr_frame_in17), + .Q(com_tlm_u_tlm_tx_vc0_trn_usr_frame_in_3509), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_tx_vc0_trn_start_frame_q ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_trn_N_86698_i_3499), + .Q(com_tlm_u_tlm_tx_vc0_trn_start_frame_q_3526), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_tx_vc0_trn_load_counter_q ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_trn_load_counter_3560), + .Q(com_tlm_u_tlm_tx_vc0_trn_load_counter_q_3476), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_tx_vc0_trn_usr_abort ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_trn_N_16671_i), + .Q(com_tlm_u_tlm_tx_vc0_trn_usr_abort_3553), + .R(plm_link_up_i) + ); + FDRE com_tlm_u_tlm_tx_vc0_trn_cfg_frame_in ( + .CE(com_tlm_u_tlm_tx_vc0_trn_N_16669_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmmt_trem_n_0_sqmuxa), + .Q(com_tlm_u_tlm_tx_vc0_trn_cfg_frame_in_3507), + .R(plm_link_up_i) + ); + FDRE com_tlm_u_tlm_tx_vc0_trn_load_counter ( + .CE(com_tlm_u_tlm_tx_vc0_trn_N_55997_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_trn_usr_start), + .Q(com_tlm_u_tlm_tx_vc0_trn_load_counter_3560), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_tx_vc0_trn_pkt_incoming_o ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_trn_un13_pkt_incoming_o_i_3498), + .Q(com_tlm_u_tlm_tx_pkt_incoming), + .R(plm_link_up_i) + ); + FDS com_tlm_u_tlm_tx_vc0_trn_usr_rem ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_trn_N_60512_i_3497), + .Q(com_tlm_u_tlm_tx_vc0_trn_usr_rem_3562), + .S(plm_link_up_i) + ); + FDR com_tlm_u_tlm_tx_vc0_trn_usr_eof_filt_q_1_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_trn_usr_eof_filt), + .Q(com_tlm_u_tlm_tx_vc0_trn_usr_eof_filt_q_1__3554), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_tx_vc0_trn_cfg_accepted_o ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_trn_cfg_o_2), + .Q(com_tlm_u_tlm_tx_cfg_accepted), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_tx_vc0_trn_usr_eof ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_trn_N_60513_i_3495), + .Q(com_tlm_u_tlm_tx_vc0_trn_usr_eof_3496), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_tx_vc0_trn_usr_dsc ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_trn_N_56499_i_i_3494), + .Q(com_tlm_u_tlm_tx_vc0_trn_usr_dsc_3482), + .R(plm_link_up_i) + ); + FDRSE com_tlm_u_tlm_tx_vc0_trn_released_buf_x ( + .CE(com_tlm_u_tlm_tx_vc0_trn_usr_abort_i_3552), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_trn_GND_3555), + .Q(com_tlm_u_tlm_tx_vc0_trn_released_buf_x_3525), + .R(plm_link_up_i), + .S(com_tlm_u_tlm_tx_vc0_released_buf) + ); + FDR com_tlm_u_tlm_tx_vc0_trn_usr_sof ( + .C(NlwRenamedSig_OI_trn_clk), + .D(trn_tsof_n_i), + .Q(com_tlm_u_tlm_tx_vc0_trn_usr_sof_3477), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_tx_vc0_trn_usr_errfwd ( + .C(NlwRenamedSig_OI_trn_clk), + .D(trn_terrfwd_n_i), + .Q(com_tlm_u_tlm_tx_vc0_trn_usr_errfwd_3501), + .R(plm_link_up_i) + ); + MUXCY_L com_tlm_u_tlm_tx_vc0_trn_un1_trn_tbuf_av_o_1_cry_0 ( + .CI(com_tlm_u_tlm_tx_vc0_trn_GND_3555), + .DI(com_tlm_u_tlm_tx_vc0_trn_un1_trn_tbuf_av_o_1_cry_0_ma_3556), + .LO(com_tlm_u_tlm_tx_vc0_trn_un1_trn_tbuf_av_o_1_cry_0_3466), + .S(com_tlm_u_tlm_tx_vc0_trn_un1_trn_tbuf_av_o_1_axb_0_3484) + ); + MULT_AND com_tlm_u_tlm_tx_vc0_trn_un1_trn_tbuf_av_o_1_cry_1 ( + .I0(com_tlm_u_tlm_tx_vc0_trn_N_44071_i), + .I1(com_tlm_u_tlm_tx_vc0_trn_start_frame_q_3526), + .LO(com_tlm_u_tlm_tx_vc0_trn_un1_trn_tbuf_av_o_1_cry_1_0_3464) + ); + MUXCY_L com_tlm_u_tlm_tx_vc0_trn_un1_trn_tbuf_av_o_1_cry_1_0 ( + .CI(com_tlm_u_tlm_tx_vc0_trn_un1_trn_tbuf_av_o_1_cry_0_3466), + .DI(com_tlm_u_tlm_tx_vc0_trn_un1_trn_tbuf_av_o_1_cry_1_0_3464), + .LO(com_tlm_u_tlm_tx_vc0_trn_un1_trn_tbuf_av_o_1_cry_1_3469), + .S(com_tlm_u_tlm_tx_vc0_trn_un1_trn_tbuf_av_o_1_axb_1_3515) + ); + XORCY com_tlm_u_tlm_tx_vc0_trn_un1_trn_tbuf_av_o_1_s_1 ( + .CI(com_tlm_u_tlm_tx_vc0_trn_un1_trn_tbuf_av_o_1_cry_0_3466), + .LI(com_tlm_u_tlm_tx_vc0_trn_un1_trn_tbuf_av_o_1_axb_1_3515), + .O(com_tlm_u_tlm_tx_vc0_trn_un1_trn_tbuf_av_o_1_s_1_3465) + ); + MULT_AND com_tlm_u_tlm_tx_vc0_trn_un1_trn_tbuf_av_o_1_cry_2 ( + .I0(com_tlm_u_tlm_tx_vc0_trn_N_44071_i), + .I1(com_tlm_u_tlm_tx_vc0_trn_start_frame_q_3526), + .LO(com_tlm_u_tlm_tx_vc0_trn_un1_trn_tbuf_av_o_1_cry_2_0_3467) + ); + MUXCY_L com_tlm_u_tlm_tx_vc0_trn_un1_trn_tbuf_av_o_1_cry_2_0 ( + .CI(com_tlm_u_tlm_tx_vc0_trn_un1_trn_tbuf_av_o_1_cry_1_3469), + .DI(com_tlm_u_tlm_tx_vc0_trn_un1_trn_tbuf_av_o_1_cry_2_0_3467), + .LO(com_tlm_u_tlm_tx_vc0_trn_un1_trn_tbuf_av_o_1_cry_2_3472), + .S(com_tlm_u_tlm_tx_vc0_trn_un1_trn_tbuf_av_o_1_axb_2_3514) + ); + XORCY com_tlm_u_tlm_tx_vc0_trn_un1_trn_tbuf_av_o_1_s_2 ( + .CI(com_tlm_u_tlm_tx_vc0_trn_un1_trn_tbuf_av_o_1_cry_1_3469), + .LI(com_tlm_u_tlm_tx_vc0_trn_un1_trn_tbuf_av_o_1_axb_2_3514), + .O(com_tlm_u_tlm_tx_vc0_trn_un1_trn_tbuf_av_o_1_s_2_3468) + ); + MULT_AND com_tlm_u_tlm_tx_vc0_trn_un1_trn_tbuf_av_o_1_cry_3 ( + .I0(com_tlm_u_tlm_tx_vc0_trn_N_44071_i), + .I1(com_tlm_u_tlm_tx_vc0_trn_start_frame_q_3526), + .LO(com_tlm_u_tlm_tx_vc0_trn_un1_trn_tbuf_av_o_1_cry_3_0_3470) + ); + MUXCY_L com_tlm_u_tlm_tx_vc0_trn_un1_trn_tbuf_av_o_1_cry_3_0 ( + .CI(com_tlm_u_tlm_tx_vc0_trn_un1_trn_tbuf_av_o_1_cry_2_3472), + .DI(com_tlm_u_tlm_tx_vc0_trn_un1_trn_tbuf_av_o_1_cry_3_0_3470), + .LO(com_tlm_u_tlm_tx_vc0_trn_un1_trn_tbuf_av_o_1_cry_3_3474), + .S(com_tlm_u_tlm_tx_vc0_trn_un1_trn_tbuf_av_o_1_axb_3_3513) + ); + XORCY com_tlm_u_tlm_tx_vc0_trn_un1_trn_tbuf_av_o_1_s_3 ( + .CI(com_tlm_u_tlm_tx_vc0_trn_un1_trn_tbuf_av_o_1_cry_2_3472), + .LI(com_tlm_u_tlm_tx_vc0_trn_un1_trn_tbuf_av_o_1_axb_3_3513), + .O(com_tlm_u_tlm_tx_vc0_trn_un1_trn_tbuf_av_o_1_s_3_3471) + ); + XORCY com_tlm_u_tlm_tx_vc0_trn_un1_trn_tbuf_av_o_1_s_4 ( + .CI(com_tlm_u_tlm_tx_vc0_trn_un1_trn_tbuf_av_o_1_cry_3_3474), + .LI(com_tlm_u_tlm_tx_vc0_trn_un1_trn_tbuf_av_o_1_axb_4_3512), + .O(com_tlm_u_tlm_tx_vc0_trn_un1_trn_tbuf_av_o_1_s_4_3473) + ); + MUXCY_L com_tlm_u_tlm_tx_vc0_trn_len_counter_cry_0_ ( + .CI(com_tlm_u_tlm_tx_vc0_trn_load_counter_3560), + .DI(com_tlm_u_tlm_tx_vc0_trn_VCC_3557), + .LO(com_tlm_u_tlm_tx_vc0_trn_len_counter_cry[0]), + .S(com_tlm_u_tlm_tx_vc0_trn_len_counter_qxu[0]) + ); + XORCY com_tlm_u_tlm_tx_vc0_trn_len_counter_s_0_ ( + .CI(com_tlm_u_tlm_tx_vc0_trn_load_counter_3560), + .LI(com_tlm_u_tlm_tx_vc0_trn_len_counter_qxu[0]), + .O(com_tlm_u_tlm_tx_vc0_trn_len_counter_s[0]) + ); + FDRE com_tlm_u_tlm_tx_vc0_trn_len_counter_0_ ( + .CE(com_tlm_u_tlm_tx_vc0_trn_N_55997_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_trn_len_counter_s[0]), + .Q(com_tlm_u_tlm_tx_vc0_trn_len_counter[0]), + .R(plm_link_up_i) + ); + MUXCY_L com_tlm_u_tlm_tx_vc0_trn_len_counter_cry_1_ ( + .CI(com_tlm_u_tlm_tx_vc0_trn_len_counter_cry[0]), + .DI(com_tlm_u_tlm_tx_vc0_trn_VCC_3557), + .LO(com_tlm_u_tlm_tx_vc0_trn_len_counter_cry[1]), + .S(com_tlm_u_tlm_tx_vc0_trn_len_counter_qxu[1]) + ); + XORCY com_tlm_u_tlm_tx_vc0_trn_len_counter_s_1_ ( + .CI(com_tlm_u_tlm_tx_vc0_trn_len_counter_cry[0]), + .LI(com_tlm_u_tlm_tx_vc0_trn_len_counter_qxu[1]), + .O(com_tlm_u_tlm_tx_vc0_trn_len_counter_s[1]) + ); + FDRE com_tlm_u_tlm_tx_vc0_trn_len_counter_1_ ( + .CE(com_tlm_u_tlm_tx_vc0_trn_N_55997_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_trn_len_counter_s[1]), + .Q(com_tlm_u_tlm_tx_vc0_trn_len_counter[1]), + .R(plm_link_up_i) + ); + MUXCY_L com_tlm_u_tlm_tx_vc0_trn_len_counter_cry_2_ ( + .CI(com_tlm_u_tlm_tx_vc0_trn_len_counter_cry[1]), + .DI(com_tlm_u_tlm_tx_vc0_trn_VCC_3557), + .LO(com_tlm_u_tlm_tx_vc0_trn_len_counter_cry[2]), + .S(com_tlm_u_tlm_tx_vc0_trn_len_counter_qxu[2]) + ); + XORCY com_tlm_u_tlm_tx_vc0_trn_len_counter_s_2_ ( + .CI(com_tlm_u_tlm_tx_vc0_trn_len_counter_cry[1]), + .LI(com_tlm_u_tlm_tx_vc0_trn_len_counter_qxu[2]), + .O(com_tlm_u_tlm_tx_vc0_trn_len_counter_s[2]) + ); + FDRE com_tlm_u_tlm_tx_vc0_trn_len_counter_2_ ( + .CE(com_tlm_u_tlm_tx_vc0_trn_N_55997_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_trn_len_counter_s[2]), + .Q(com_tlm_u_tlm_tx_vc0_trn_len_counter[2]), + .R(plm_link_up_i) + ); + MUXCY_L com_tlm_u_tlm_tx_vc0_trn_len_counter_cry_3_ ( + .CI(com_tlm_u_tlm_tx_vc0_trn_len_counter_cry[2]), + .DI(com_tlm_u_tlm_tx_vc0_trn_VCC_3557), + .LO(com_tlm_u_tlm_tx_vc0_trn_len_counter_cry[3]), + .S(com_tlm_u_tlm_tx_vc0_trn_len_counter_qxu[3]) + ); + XORCY com_tlm_u_tlm_tx_vc0_trn_len_counter_s_3_ ( + .CI(com_tlm_u_tlm_tx_vc0_trn_len_counter_cry[2]), + .LI(com_tlm_u_tlm_tx_vc0_trn_len_counter_qxu[3]), + .O(com_tlm_u_tlm_tx_vc0_trn_len_counter_s[3]) + ); + FDRE com_tlm_u_tlm_tx_vc0_trn_len_counter_3_ ( + .CE(com_tlm_u_tlm_tx_vc0_trn_N_55997_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_trn_len_counter_s[3]), + .Q(com_tlm_u_tlm_tx_vc0_trn_len_counter[3]), + .R(plm_link_up_i) + ); + MUXCY_L com_tlm_u_tlm_tx_vc0_trn_len_counter_cry_4_ ( + .CI(com_tlm_u_tlm_tx_vc0_trn_len_counter_cry[3]), + .DI(com_tlm_u_tlm_tx_vc0_trn_VCC_3557), + .LO(com_tlm_u_tlm_tx_vc0_trn_len_counter_cry[4]), + .S(com_tlm_u_tlm_tx_vc0_trn_len_counter_qxu[4]) + ); + XORCY com_tlm_u_tlm_tx_vc0_trn_len_counter_s_4_ ( + .CI(com_tlm_u_tlm_tx_vc0_trn_len_counter_cry[3]), + .LI(com_tlm_u_tlm_tx_vc0_trn_len_counter_qxu[4]), + .O(com_tlm_u_tlm_tx_vc0_trn_len_counter_s[4]) + ); + FDRE com_tlm_u_tlm_tx_vc0_trn_len_counter_4_ ( + .CE(com_tlm_u_tlm_tx_vc0_trn_N_55997_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_trn_len_counter_s[4]), + .Q(com_tlm_u_tlm_tx_vc0_trn_len_counter[4]), + .R(plm_link_up_i) + ); + MUXCY_L com_tlm_u_tlm_tx_vc0_trn_len_counter_cry_5_ ( + .CI(com_tlm_u_tlm_tx_vc0_trn_len_counter_cry[4]), + .DI(com_tlm_u_tlm_tx_vc0_trn_VCC_3557), + .LO(com_tlm_u_tlm_tx_vc0_trn_len_counter_cry[5]), + .S(com_tlm_u_tlm_tx_vc0_trn_len_counter_qxu[5]) + ); + XORCY com_tlm_u_tlm_tx_vc0_trn_len_counter_s_5_ ( + .CI(com_tlm_u_tlm_tx_vc0_trn_len_counter_cry[4]), + .LI(com_tlm_u_tlm_tx_vc0_trn_len_counter_qxu[5]), + .O(com_tlm_u_tlm_tx_vc0_trn_len_counter_s[5]) + ); + FDRE com_tlm_u_tlm_tx_vc0_trn_len_counter_5_ ( + .CE(com_tlm_u_tlm_tx_vc0_trn_N_55997_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_trn_len_counter_s[5]), + .Q(com_tlm_u_tlm_tx_vc0_trn_len_counter[5]), + .R(plm_link_up_i) + ); + XORCY com_tlm_u_tlm_tx_vc0_trn_len_counter_s_6_ ( + .CI(com_tlm_u_tlm_tx_vc0_trn_len_counter_cry[5]), + .LI(com_tlm_u_tlm_tx_vc0_trn_len_counter_qxu[6]), + .O(com_tlm_u_tlm_tx_vc0_trn_len_counter_s[6]) + ); + FDRE com_tlm_u_tlm_tx_vc0_trn_len_counter_6_ ( + .CE(com_tlm_u_tlm_tx_vc0_trn_N_55997_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_trn_len_counter_s[6]), + .Q(com_tlm_u_tlm_tx_vc0_trn_len_counter[6]), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_tx_vc0_trn_usr_vld ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_trn_N_55997_i), + .Q(com_tlm_u_tlm_tx_vc0_trn_usr_vld_3503), + .R(plm_link_up_i) + ); + defparam com_tlm_u_tlm_tx_vc0_trn_load_val_64_load_value10.INIT = 4'h8; + LUT2 com_tlm_u_tlm_tx_vc0_trn_load_val_64_load_value10 ( + .I0(trn_td_6087[47]), + .I1(trn_td_6087[61]), + .O(com_tlm_u_tlm_tx_vc0_trn_load_value10) + ); + defparam com_tlm_u_tlm_tx_vc0_trn_un1_usr_vld_0_a2_0_a2_0_a2.INIT = 4'h8; + LUT2 com_tlm_u_tlm_tx_vc0_trn_un1_usr_vld_0_a2_0_a2_0_a2 ( + .I0(com_tlm_u_tlm_tx_vc0_trn_usr_sof_3477), + .I1(com_tlm_u_tlm_tx_vc0_trn_usr_vld_3503), + .O(com_tlm_u_tlm_tx_vc0_trn_un1_usr_vld_0_a2_0_a2_0_a2_3475) + ); + defparam com_tlm_u_tlm_tx_vc0_trn_usr_sof_filt_0_a2_0_a2_0_a2.INIT = 4'h4; + LUT2 com_tlm_u_tlm_tx_vc0_trn_usr_sof_filt_0_a2_0_a2_0_a2 ( + .I0(com_tlm_u_tlm_tx_vc0_trn_usr_frame_3504), + .I1(com_tlm_u_tlm_tx_vc0_trn_usr_sof_3477), + .O(com_tlm_u_tlm_tx_vc0_trn_usr_sof_filt) + ); + defparam com_tlm_u_tlm_tx_vc0_trn_un1_trn_tsrc_dsc_i_i_0_0_o2.INIT = 4'h4; + LUT2 com_tlm_u_tlm_tx_vc0_trn_un1_trn_tsrc_dsc_i_i_0_0_o2 ( + .I0(com_tlm_u_tlm_tx_vc0_trn_trn_tdst_dsc), + .I1(trn_tsrc_dsc_n), + .O(com_tlm_u_tlm_tx_vc0_trn_N_56499_i) + ); + defparam com_tlm_u_tlm_tx_vc0_trn_usr_calc_eof_0_sqmuxa_i_0_a2.INIT = 4'h1; + LUT2_L com_tlm_u_tlm_tx_vc0_trn_usr_calc_eof_0_sqmuxa_i_0_a2 ( + .I0(com_tlm_u_tlm_tx_vc0_trn_usr_frame_in_3509), + .I1(trn_tsof_n), + .LO(com_tlm_u_tlm_tx_vc0_trn_N_60417) + ); + defparam com_tlm_u_tlm_tx_vc0_trn_un1_usr_abort_1_0_o3.INIT = 4'h1; + LUT2 com_tlm_u_tlm_tx_vc0_trn_un1_usr_abort_1_0_o3 ( + .I0(com_tlm_u_tlm_tx_vc0_trn_released_buf_x_3525), + .I1(com_tlm_u_tlm_tx_vc0_trn_usr_abort_3553), + .O(com_tlm_u_tlm_tx_vc0_trn_N_44071_i) + ); + defparam com_tlm_u_tlm_tx_vc0_trn_usr_vldc.INIT = 4'h2; + LUT2 com_tlm_u_tlm_tx_vc0_trn_usr_vldc ( + .I0(com_tlm_u_tlm_tx_vc0_trn_trn_tdst_rdy), + .I1(trn_tsrc_rdy_n), + .O(com_tlm_u_tlm_tx_vc0_trn_N_55997_i) + ); + defparam com_tlm_u_tlm_tx_vc0_trn_trn_tdst_rdy_o_3_0_0_0_0_a2_0_0_0.INIT = 4'h1; + LUT2 com_tlm_u_tlm_tx_vc0_trn_trn_tdst_rdy_o_3_0_0_0_0_a2_0_0_0 ( + .I0(com_tlm_u_tlm_tx_vc0_trn_trn_tdst_dsc), + .I1(com_tlm_u_tlm_tx_vc0_trn_cfg_frame_in_3507), + .O(com_tlm_u_tlm_tx_vc0_trn_trn_tdst_rdy_o_3_0_0_0_0_a2_0_0) + ); + defparam com_tlm_u_tlm_tx_vc0_trn_usr_calc_eof_0_sqmuxa_i_0_0.INIT = 4'h2; + LUT2 com_tlm_u_tlm_tx_vc0_trn_usr_calc_eof_0_sqmuxa_i_0_0 ( + .I0(com_tlm_u_tlm_tx_vc0_trn_len_counter[0]), + .I1(com_tlm_u_tlm_tx_vc0_trn_load_counter_q_3476), + .O(com_tlm_u_tlm_tx_vc0_trn_usr_calc_eof_0_sqmuxa_i_0_0_3487) + ); + defparam com_tlm_u_tlm_tx_vc0_trn_vld_o_5_i_0_a2.INIT = 8'hE0; + LUT3 com_tlm_u_tlm_tx_vc0_trn_vld_o_5_i_0_a2 ( + .I0(com_tlm_u_tlm_tx_vc0_trn_usr_frame_3504), + .I1(com_tlm_u_tlm_tx_vc0_trn_usr_sof_3477), + .I2(com_tlm_u_tlm_tx_vc0_trn_usr_vld_3503), + .O(com_tlm_u_tlm_tx_vc0_trn_vld_o_5_i_0_a2_3564) + ); + defparam com_tlm_u_tlm_tx_vc0_trn_un1_usr_dsc_1_i_0_0_o3.INIT = 8'h80; + LUT3 com_tlm_u_tlm_tx_vc0_trn_un1_usr_dsc_1_i_0_0_o3 ( + .I0(com_tlm_u_tlm_tx_vc0_trn_usr_eof_3496), + .I1(com_tlm_u_tlm_tx_vc0_trn_usr_frame_3504), + .I2(com_tlm_u_tlm_tx_vc0_trn_usr_vld_3503), + .O(com_tlm_u_tlm_tx_vc0_trn_N_56472_i) + ); + defparam com_tlm_u_tlm_tx_vc0_trn_usr_calc_eof_0_sqmuxa_i_0_o2.INIT = 4'h8; + LUT2 com_tlm_u_tlm_tx_vc0_trn_usr_calc_eof_0_sqmuxa_i_0_o2 ( + .I0(com_tlm_u_tlm_tx_vc0_trn_N_55997_i), + .I1(plm_link_up_1), + .O(com_tlm_u_tlm_tx_vc0_trn_N_56947_i) + ); + defparam com_tlm_u_tlm_tx_vc0_trn_trn_tdst_rdy_o_3_0_0_0_0_o3_0.INIT = 4'h2; + LUT2 com_tlm_u_tlm_tx_vc0_trn_trn_tdst_rdy_o_3_0_0_0_0_o3_0 ( + .I0(com_N_55871_i), + .I1(com_N_55880_i), + .O(com_tlm_u_tlm_tx_vc0_trn_N_56477_i) + ); + defparam com_tlm_u_tlm_tx_vc0_trn_trn_tdst_rdy_o_3_0_0_0_0_o3.INIT = 4'h2; + LUT2 com_tlm_u_tlm_tx_vc0_trn_trn_tdst_rdy_o_3_0_0_0_0_o3 ( + .I0(com_tlm_u_tlm_tx_vc0_trn_N_55997_i), + .I1(trn_teof_n), + .O(com_tlm_u_tlm_tx_vc0_trn_N_56234_i) + ); + defparam com_tlm_u_tlm_tx_vc0_trn_un1_trn_tsrc_dsc_i_i_0_0_o3.INIT = 4'h2; + LUT2 com_tlm_u_tlm_tx_vc0_trn_un1_trn_tsrc_dsc_i_i_0_0_o3 ( + .I0(com_tlm_u_tlm_tx_vc0_trn_N_55997_i), + .I1(trn_tsof_n), + .O(com_tlm_u_tlm_tx_vc0_trn_N_56107_i) + ); + defparam com_tlm_u_tlm_tx_vc0_trn_un1_usr_abort_6_0_0_a2.INIT = 4'h1; + LUT2 com_tlm_u_tlm_tx_vc0_trn_un1_usr_abort_6_0_0_a2 ( + .I0(com_tlm_u_tlm_tx_vc0_trn_N_44071_i), + .I1(com_tlm_u_tlm_tx_vc0_trn_start_frame_q_3526), + .O(com_tlm_u_tlm_tx_vc0_trn_N_58355) + ); + defparam com_tlm_u_tlm_tx_vc0_trn_pkts_in_trn28_i_0_o3.INIT = 8'h01; + LUT3 com_tlm_u_tlm_tx_vc0_trn_pkts_in_trn28_i_0_o3 ( + .I0(com_tlm_u_tlm_tx_vc0_trn_trn_tdst_dsc), + .I1(com_tlm_u_tlm_tx_vc0_trn_dsc_in_q_3478), + .I2(com_tlm_u_tlm_tx_vc0_trn_usr_eof_filt_q_4_), + .O(com_tlm_u_tlm_tx_vc0_trn_N_56231_i) + ); + defparam com_tlm_u_tlm_tx_vc0_trn_un1_usr_abort_8_0_0_a2_0_0.INIT = 8'h01; + LUT3 com_tlm_u_tlm_tx_vc0_trn_un1_usr_abort_8_0_0_a2_0_0 ( + .I0(NlwRenamedSig_OI_trn_tbuf_av[2]), + .I1(NlwRenamedSig_OI_trn_tbuf_av[3]), + .I2(NlwRenamedSig_OI_trn_tbuf_av[4]), + .O(com_tlm_u_tlm_tx_vc0_trn_un1_usr_abort_8_0_0_a2_0_0_3522) + ); + defparam com_tlm_u_tlm_tx_vc0_trn_usr_calc_eof_0_sqmuxa_i_0_5.INIT = 16'h0001; + LUT4 com_tlm_u_tlm_tx_vc0_trn_usr_calc_eof_0_sqmuxa_i_0_5 ( + .I0(com_tlm_u_tlm_tx_vc0_trn_len_counter[1]), + .I1(com_tlm_u_tlm_tx_vc0_trn_len_counter[2]), + .I2(com_tlm_u_tlm_tx_vc0_trn_len_counter[4]), + .I3(com_tlm_u_tlm_tx_vc0_trn_len_counter[6]), + .O(com_tlm_u_tlm_tx_vc0_trn_usr_calc_eof_0_sqmuxa_i_0_5_3486) + ); + defparam com_tlm_u_tlm_tx_vc0_trn_buffer_rdy_3_i_0_0.INIT = 8'h13; + LUT3 com_tlm_u_tlm_tx_vc0_trn_buffer_rdy_3_i_0_0 ( + .I0(com_tlm_u_tlm_tx_vc0_trn_buf_av_one_3511), + .I1(com_tlm_u_tlm_tx_vc0_trn_buf_av_zero_3479), + .I2(com_tlm_u_tlm_tx_vc0_trn_start_frame_q_3526), + .O(com_tlm_u_tlm_tx_vc0_trn_buffer_rdy_3_i_0_0_3510) + ); + defparam com_tlm_u_tlm_tx_vc0_trn_vld_o_5_i_0_a3.INIT = 8'h20; + LUT3 com_tlm_u_tlm_tx_vc0_trn_vld_o_5_i_0_a3 ( + .I0(com_N_55871_i), + .I1(com_N_55880_i), + .I2(com_cmmt_tdst_rdy), + .O(com_tlm_u_tlm_tx_vc0_trn_N_61322) + ); + defparam com_tlm_u_tlm_tx_vc0_trn_d_o_4_0_0_a3_12_.INIT = 8'h20; + LUT3 com_tlm_u_tlm_tx_vc0_trn_d_o_4_0_0_a3_12_ ( + .I0(com_N_55871_i), + .I1(com_state[0]), + .I2(com_cmmt_tdst_rdy), + .O(com_tlm_u_tlm_tx_vc0_trn_N_61337) + ); + defparam com_tlm_u_tlm_tx_vc0_trn_rem_o_5_0_0_0_o3_1.INIT = 16'h0F01; + LUT4_L com_tlm_u_tlm_tx_vc0_trn_rem_o_5_0_0_0_o3_1 ( + .I0(com_tlp_data_0_), + .I1(com_tlp_data_29_), + .I2(com_cmmt_trem_n_0_sqmuxa), + .I3(com_state[0]), + .LO(com_tlm_u_tlm_tx_vc0_trn_rem_o_5_0_0_0_o3_1_3521) + ); + defparam com_tlm_u_tlm_tx_vc0_trn_start_frame_i_0_a2.INIT = 4'h2; + LUT2 com_tlm_u_tlm_tx_vc0_trn_start_frame_i_0_a2 ( + .I0(com_tlm_u_tlm_tx_vc0_trn_N_56107_i), + .I1(com_tlm_u_tlm_tx_vc0_trn_usr_frame_in_3509), + .O(com_tlm_u_tlm_tx_vc0_trn_usr_start) + ); + defparam com_tlm_u_tlm_tx_vc0_trn_un1_usr_abort_6_0_0_a2_0_1_0.INIT = 4'h8; + LUT2 com_tlm_u_tlm_tx_vc0_trn_un1_usr_abort_6_0_0_a2_0_1_0 ( + .I0(com_tlm_u_tlm_tx_vc0_trn_un1_buf_av_one_1_i_0_a2[0]), + .I1(com_tlm_u_tlm_tx_vc0_trn_un1_usr_abort_8_0_0_a2_0_0_3522), + .O(com_tlm_u_tlm_tx_vc0_trn_N_58356_1_0) + ); + defparam com_tlm_u_tlm_tx_vc0_trn_trn_tdst_rdy_o_3_0_0_0_0_a2.INIT = 16'h0040; + LUT4_L com_tlm_u_tlm_tx_vc0_trn_trn_tdst_rdy_o_3_0_0_0_0_a2 ( + .I0(com_tlm_u_tlm_tx_vc0_trn_N_56477_i), + .I1(com_cmmt_ppm_suspend_req_n), + .I2(com_tlm_u_tlm_tx_vc0_trn_buffer_rdy_3480), + .I3(com_tlm_u_tlm_tx_vc0_trn_cfg_frame_in_3507), + .LO(com_tlm_u_tlm_tx_vc0_trn_N_57343) + ); + defparam com_tlm_u_tlm_tx_vc0_trn_cmm_tdst_rdy_o_3_0_0_a2_0.INIT = 16'h0020; + LUT4_L com_tlm_u_tlm_tx_vc0_trn_cmm_tdst_rdy_o_3_0_0_a2_0 ( + .I0(com_tlm_u_tlm_tx_vc0_trn_N_56477_i), + .I1(com_tlm_u_tlm_tx_vc0_trn_trn_tdst_rdy), + .I2(com_tlm_u_tlm_tx_vc0_trn_buffer_rdy_3480), + .I3(com_tlm_u_tlm_tx_vc0_trn_usr_frame_in_3509), + .LO(com_tlm_u_tlm_tx_vc0_trn_N_57342) + ); + defparam com_tlm_u_tlm_tx_vc0_trn_usr_calc_eof_0_sqmuxa_i_0_7.INIT = 16'h0001; + LUT4 com_tlm_u_tlm_tx_vc0_trn_usr_calc_eof_0_sqmuxa_i_0_7 ( + .I0(com_tlm_u_tlm_tx_vc0_trn_N_60417), + .I1(com_tlm_u_tlm_tx_vc0_trn_len_counter[3]), + .I2(com_tlm_u_tlm_tx_vc0_trn_len_counter[5]), + .I3(com_tlm_u_tlm_tx_vc0_trn_load_counter_3560), + .O(com_tlm_u_tlm_tx_vc0_trn_usr_calc_eof_0_sqmuxa_i_0_7_3485) + ); + defparam com_tlm_u_tlm_tx_vc0_trn_eof_o_5_i_0_0_0.INIT = 16'h0BFF; + LUT4 com_tlm_u_tlm_tx_vc0_trn_eof_o_5_i_0_0_0 ( + .I0(com_tlm_u_tlm_tx_vc0_trn_usr_eof_3496), + .I1(com_tlm_u_tlm_tx_vc0_trn_usr_frame_3504), + .I2(com_tlm_u_tlm_tx_vc0_trn_usr_sof_filt), + .I3(com_tlm_u_tlm_tx_vc0_trn_usr_vld_3503), + .O(com_tlm_u_tlm_tx_vc0_trn_eof_o_5_i_0_0_0_3500) + ); + defparam com_tlm_u_tlm_tx_vc0_trn_N_86735_i.INIT = 4'hE; + LUT2 com_tlm_u_tlm_tx_vc0_trn_N_86735_i ( + .I0(com_tlm_u_tlm_tx_vc0_trn_N_56472_i), + .I1(com_tlm_u_tlm_tx_vc0_trn_usr_dsc_3482), + .O(com_tlm_u_tlm_tx_vc0_trn_N_86735_i_3481) + ); + defparam com_tlm_u_tlm_tx_vc0_trn_pkts_in_trn_1_sqmuxa_5917_i_0_0.INIT = 16'h50D0; + LUT4 com_tlm_u_tlm_tx_vc0_trn_pkts_in_trn_1_sqmuxa_5917_i_0_0 ( + .I0(com_tlm_u_tlm_tx_vc0_trn_N_56231_i), + .I1(com_tlm_u_tlm_tx_vc0_trn_usr_frame_in_3509), + .I2(plm_link_up_1), + .I3(trn_tsrc_dsc_n), + .O(com_tlm_u_tlm_tx_vc0_trn_pkts_in_trn_1_sqmuxa_5917_i_0_0_3518) + ); + defparam com_tlm_u_tlm_tx_vc0_trn_N_85889_i.INIT = 8'hEF; + LUT3 com_tlm_u_tlm_tx_vc0_trn_N_85889_i ( + .I0(com_tlm_u_tlm_tx_vc0_trn_N_56107_i), + .I1(com_tlm_u_tlm_tx_vc0_trn_N_56234_i), + .I2(com_tlm_u_tlm_tx_vc0_trn_N_56499_i), + .O(com_tlm_u_tlm_tx_vc0_trn_N_85889_i_3483) + ); + defparam com_tlm_u_tlm_tx_vc0_trn_cfg_frame_in_en_i_0_0.INIT = 8'hC4; + LUT3 com_tlm_u_tlm_tx_vc0_trn_cfg_frame_in_en_i_0_0 ( + .I0(com_N_58286), + .I1(com_tlm_u_tlm_tx_vc0_trn_N_61322), + .I2(com_state[0]), + .O(com_tlm_u_tlm_tx_vc0_trn_N_16669_i) + ); + defparam com_tlm_u_tlm_tx_vc0_trn_un1_trn_tbuf_av_o_1_axb_0.INIT = 16'h13EC; + LUT4 com_tlm_u_tlm_tx_vc0_trn_un1_trn_tbuf_av_o_1_axb_0 ( + .I0(com_tlm_u_tlm_tx_vc0_trn_N_58355), + .I1(com_tlm_u_tlm_tx_vc0_trn_un1_buf_av_one_1_i_0_a2[0]), + .I2(plm_link_up_1), + .I3(NlwRenamedSig_OI_trn_tbuf_av[0]), + .O(com_tlm_u_tlm_tx_vc0_trn_un1_trn_tbuf_av_o_1_axb_0_3484) + ); + defparam com_tlm_u_tlm_tx_vc0_trn_usr_calc_eof_0_sqmuxa_i_0.INIT = 16'h8000; + LUT4 com_tlm_u_tlm_tx_vc0_trn_usr_calc_eof_0_sqmuxa_i_0 ( + .I0(com_tlm_u_tlm_tx_vc0_trn_N_56947_i), + .I1(com_tlm_u_tlm_tx_vc0_trn_usr_calc_eof_0_sqmuxa_i_0_0_3487), + .I2(com_tlm_u_tlm_tx_vc0_trn_usr_calc_eof_0_sqmuxa_i_0_5_3486), + .I3(com_tlm_u_tlm_tx_vc0_trn_usr_calc_eof_0_sqmuxa_i_0_7_3485), + .O(com_tlm_u_tlm_tx_vc0_trn_N_42906_i) + ); + defparam com_tlm_u_tlm_tx_vc0_trn_pkts_in_trn28_i_0_39418.INIT = 16'h39F9; + LUT4 com_tlm_u_tlm_tx_vc0_trn_pkts_in_trn28_i_0_39418 ( + .I0(com_tlm_u_tlm_tx_vc0_trn_N_56107_i), + .I1(com_tlm_u_tlm_tx_vc0_trn_N_56231_i), + .I2(com_tlm_u_tlm_tx_vc0_trn_usr_frame_in_3509), + .I3(trn_tsrc_dsc_n), + .O(com_tlm_u_tlm_tx_vc0_trn_pkts_in_trn28_i_0_39418_3520) + ); + defparam com_tlm_u_tlm_tx_vc0_trn_d_o_4_i_0_0_61_.INIT = 16'hC4F5; + LUT4_L com_tlm_u_tlm_tx_vc0_trn_d_o_4_i_0_0_61_ ( + .I0(com_tlm_u_tlm_tx_vc0_trn_N_61337), + .I1(com_tlp_data_29_), + .I2(com_TLP_data_reg_29_), + .I3(com_tlm_u_tlm_tx_vc0_trn_cfg_o_2), + .LO(com_tlm_u_tlm_tx_vc0_trn_d_o_4_i_0_0_61__3491) + ); + defparam com_tlm_u_tlm_tx_vc0_trn_d_o_4_i_0_0_62_.INIT = 16'hC4F5; + LUT4_L com_tlm_u_tlm_tx_vc0_trn_d_o_4_i_0_0_62_ ( + .I0(com_tlm_u_tlm_tx_vc0_trn_N_61337), + .I1(com_tlp_data_0_), + .I2(com_TLP_data_reg_30_), + .I3(com_tlm_u_tlm_tx_vc0_trn_cfg_o_2), + .LO(com_tlm_u_tlm_tx_vc0_trn_d_o_4_i_0_0_62__3490) + ); + defparam com_tlm_u_tlm_tx_vc0_trn_d_o_4_i_i_0_32_.INIT = 16'h135F; + LUT4_L com_tlm_u_tlm_tx_vc0_trn_d_o_4_i_i_0_32_ ( + .I0(com_tlm_u_tlm_tx_vc0_trn_N_61337), + .I1(com_tlp_data_0_), + .I2(com_TLP_data_reg_0_), + .I3(com_tlm_u_tlm_tx_vc0_trn_cfg_o_2), + .LO(com_tlm_u_tlm_tx_vc0_trn_d_o_4_i_i_0[32]) + ); + defparam com_tlm_u_tlm_tx_vc0_trn_d_o_4_i_0_0_57_.INIT = 16'hF3A2; + LUT4_L com_tlm_u_tlm_tx_vc0_trn_d_o_4_i_0_0_57_ ( + .I0(com_tlm_u_tlm_tx_vc0_trn_N_61322), + .I1(com_tlm_u_tlm_tx_vc0_trn_N_61337), + .I2(com_TLP_data_reg_25_), + .I3(com_tlm_u_tlm_tx_vc0_trn_usr_d[57]), + .LO(com_tlm_u_tlm_tx_vc0_trn_d_o_4_i_0_0_57__3493) + ); + defparam com_tlm_u_tlm_tx_vc0_trn_d_o_4_i_0_0_59_.INIT = 16'hF3A2; + LUT4_L com_tlm_u_tlm_tx_vc0_trn_d_o_4_i_0_0_59_ ( + .I0(com_tlm_u_tlm_tx_vc0_trn_N_61322), + .I1(com_tlm_u_tlm_tx_vc0_trn_N_61337), + .I2(com_TLP_data_reg_27_), + .I3(com_tlm_u_tlm_tx_vc0_trn_usr_d[59]), + .LO(com_tlm_u_tlm_tx_vc0_trn_d_o_4_i_0_0_59__3492) + ); + defparam com_tlm_u_tlm_tx_vc0_trn_N_86362_i.INIT = 16'hAAEA; + LUT4 com_tlm_u_tlm_tx_vc0_trn_N_86362_i ( + .I0(com_tlm_u_tlm_tx_vc0_trn_N_58355), + .I1(com_tlm_u_tlm_tx_vc0_trn_N_58356_1_0), + .I2(NlwRenamedSig_OI_trn_tbuf_av[0]), + .I3(NlwRenamedSig_OI_trn_tbuf_av[1]), + .O(com_tlm_u_tlm_tx_vc0_trn_N_86362_i_3488) + ); + defparam com_tlm_u_tlm_tx_vc0_trn_un1_pkts_in_trn_1_ac0_0.INIT = 8'h80; + LUT3_L com_tlm_u_tlm_tx_vc0_trn_un1_pkts_in_trn_1_ac0_0 ( + .I0(com_tlm_u_tlm_tx_vc0_trn_pkts_in_trn28_i_0_39418_3520), + .I1(com_tlm_u_tlm_tx_vc0_trn_pkts_in_trn[0]), + .I2(plm_link_up_1), + .LO(com_tlm_u_tlm_tx_vc0_trn_un1_pkts_in_trn_1_ac0_0_3517) + ); + defparam com_tlm_u_tlm_tx_vc0_trn_usr_no_eof_err14_0_a2_0_a2_0_a2.INIT = 16'h8000; + LUT4_L com_tlm_u_tlm_tx_vc0_trn_usr_no_eof_err14_0_a2_0_a2_0_a2 ( + .I0(com_tlm_u_tlm_tx_vc0_trn_N_56947_i), + .I1(com_tlm_u_tlm_tx_vc0_trn_usr_calc_eof_3489), + .I2(com_tlm_u_tlm_tx_vc0_trn_usr_frame_in_3509), + .I3(trn_teof_n), + .LO(com_tlm_u_tlm_tx_vc0_trn_usr_no_eof_err14) + ); + defparam com_tlm_u_tlm_tx_vc0_trn_d_o_4_i_0_10_.INIT = 8'hD8; + LUT3_L com_tlm_u_tlm_tx_vc0_trn_d_o_4_i_0_10_ ( + .I0(com_tlm_u_tlm_tx_vc0_trn_N_61322), + .I1(com_N_63654), + .I2(com_tlm_u_tlm_tx_vc0_trn_usr_d[10]), + .LO(com_tlm_u_tlm_tx_vc0_trn_N_42816_i) + ); + defparam com_tlm_u_tlm_tx_vc0_trn_d_o_4_i_0_9_.INIT = 8'hD8; + LUT3_L com_tlm_u_tlm_tx_vc0_trn_d_o_4_i_0_9_ ( + .I0(com_tlm_u_tlm_tx_vc0_trn_N_61322), + .I1(com_N_63653), + .I2(com_tlm_u_tlm_tx_vc0_trn_usr_d[9]), + .LO(com_tlm_u_tlm_tx_vc0_trn_N_42814_i) + ); + defparam com_tlm_u_tlm_tx_vc0_trn_d_o_4_i_0_8_.INIT = 8'hD8; + LUT3_L com_tlm_u_tlm_tx_vc0_trn_d_o_4_i_0_8_ ( + .I0(com_tlm_u_tlm_tx_vc0_trn_N_61322), + .I1(com_N_63652), + .I2(com_tlm_u_tlm_tx_vc0_trn_usr_d[8]), + .LO(com_tlm_u_tlm_tx_vc0_trn_N_42812_i) + ); + defparam com_tlm_u_tlm_tx_vc0_trn_d_o_4_i_0_7_.INIT = 8'hD8; + LUT3_L com_tlm_u_tlm_tx_vc0_trn_d_o_4_i_0_7_ ( + .I0(com_tlm_u_tlm_tx_vc0_trn_N_61322), + .I1(com_N_63651), + .I2(com_tlm_u_tlm_tx_vc0_trn_usr_d[7]), + .LO(com_tlm_u_tlm_tx_vc0_trn_N_42810_i) + ); + defparam com_tlm_u_tlm_tx_vc0_trn_d_o_4_i_0_6_.INIT = 8'hD8; + LUT3_L com_tlm_u_tlm_tx_vc0_trn_d_o_4_i_0_6_ ( + .I0(com_tlm_u_tlm_tx_vc0_trn_N_61322), + .I1(com_N_63650), + .I2(com_tlm_u_tlm_tx_vc0_trn_usr_d[6]), + .LO(com_tlm_u_tlm_tx_vc0_trn_N_42808_i) + ); + defparam com_tlm_u_tlm_tx_vc0_trn_d_o_4_i_0_5_.INIT = 8'hD8; + LUT3_L com_tlm_u_tlm_tx_vc0_trn_d_o_4_i_0_5_ ( + .I0(com_tlm_u_tlm_tx_vc0_trn_N_61322), + .I1(com_N_63659), + .I2(com_tlm_u_tlm_tx_vc0_trn_usr_d[5]), + .LO(com_tlm_u_tlm_tx_vc0_trn_N_42806_i) + ); + defparam com_tlm_u_tlm_tx_vc0_trn_d_o_4_i_0_4_.INIT = 8'hD8; + LUT3_L com_tlm_u_tlm_tx_vc0_trn_d_o_4_i_0_4_ ( + .I0(com_tlm_u_tlm_tx_vc0_trn_N_61322), + .I1(com_N_63658), + .I2(com_tlm_u_tlm_tx_vc0_trn_usr_d[4]), + .LO(com_tlm_u_tlm_tx_vc0_trn_N_42804_i) + ); + defparam com_tlm_u_tlm_tx_vc0_trn_d_o_4_i_0_3_.INIT = 8'hD8; + LUT3_L com_tlm_u_tlm_tx_vc0_trn_d_o_4_i_0_3_ ( + .I0(com_tlm_u_tlm_tx_vc0_trn_N_61322), + .I1(com_N_63657), + .I2(com_tlm_u_tlm_tx_vc0_trn_usr_d[3]), + .LO(com_tlm_u_tlm_tx_vc0_trn_N_42802_i) + ); + defparam com_tlm_u_tlm_tx_vc0_trn_d_o_4_i_0_2_.INIT = 8'hD8; + LUT3_L com_tlm_u_tlm_tx_vc0_trn_d_o_4_i_0_2_ ( + .I0(com_tlm_u_tlm_tx_vc0_trn_N_61322), + .I1(com_N_63656), + .I2(com_tlm_u_tlm_tx_vc0_trn_usr_d[2]), + .LO(com_tlm_u_tlm_tx_vc0_trn_N_42800_i) + ); + defparam com_tlm_u_tlm_tx_vc0_trn_d_o_4_i_0_1_.INIT = 8'hD8; + LUT3_L com_tlm_u_tlm_tx_vc0_trn_d_o_4_i_0_1_ ( + .I0(com_tlm_u_tlm_tx_vc0_trn_N_61322), + .I1(com_N_63655), + .I2(com_tlm_u_tlm_tx_vc0_trn_usr_d[1]), + .LO(com_tlm_u_tlm_tx_vc0_trn_N_42798_i) + ); + defparam com_tlm_u_tlm_tx_vc0_trn_d_o_4_i_0_0_.INIT = 8'hD8; + LUT3_L com_tlm_u_tlm_tx_vc0_trn_d_o_4_i_0_0_ ( + .I0(com_tlm_u_tlm_tx_vc0_trn_N_61322), + .I1(com_N_63660), + .I2(com_tlm_u_tlm_tx_vc0_trn_usr_d[0]), + .LO(com_tlm_u_tlm_tx_vc0_trn_N_42796_i) + ); + defparam com_tlm_u_tlm_tx_vc0_trn_d_o_4_i_0_25_.INIT = 8'hD8; + LUT3_L com_tlm_u_tlm_tx_vc0_trn_d_o_4_i_0_25_ ( + .I0(com_tlm_u_tlm_tx_vc0_trn_N_61322), + .I1(com_N_63644), + .I2(com_tlm_u_tlm_tx_vc0_trn_usr_d[25]), + .LO(com_tlm_u_tlm_tx_vc0_trn_N_42841_i) + ); + defparam com_tlm_u_tlm_tx_vc0_trn_d_o_4_i_0_24_.INIT = 8'hD8; + LUT3_L com_tlm_u_tlm_tx_vc0_trn_d_o_4_i_0_24_ ( + .I0(com_tlm_u_tlm_tx_vc0_trn_N_61322), + .I1(com_N_63643), + .I2(com_tlm_u_tlm_tx_vc0_trn_usr_d[24]), + .LO(com_tlm_u_tlm_tx_vc0_trn_N_42839_i) + ); + defparam com_tlm_u_tlm_tx_vc0_trn_d_o_4_i_0_23_.INIT = 8'hD8; + LUT3_L com_tlm_u_tlm_tx_vc0_trn_d_o_4_i_0_23_ ( + .I0(com_tlm_u_tlm_tx_vc0_trn_N_61322), + .I1(com_N_63642), + .I2(com_tlm_u_tlm_tx_vc0_trn_usr_d[23]), + .LO(com_tlm_u_tlm_tx_vc0_trn_N_42837_i) + ); + defparam com_tlm_u_tlm_tx_vc0_trn_d_o_4_i_0_22_.INIT = 8'hD8; + LUT3_L com_tlm_u_tlm_tx_vc0_trn_d_o_4_i_0_22_ ( + .I0(com_tlm_u_tlm_tx_vc0_trn_N_61322), + .I1(com_N_63641), + .I2(com_tlm_u_tlm_tx_vc0_trn_usr_d[22]), + .LO(com_tlm_u_tlm_tx_vc0_trn_N_42835_i) + ); + defparam com_tlm_u_tlm_tx_vc0_trn_d_o_4_i_0_21_.INIT = 8'hD8; + LUT3_L com_tlm_u_tlm_tx_vc0_trn_d_o_4_i_0_21_ ( + .I0(com_tlm_u_tlm_tx_vc0_trn_N_61322), + .I1(com_N_63640), + .I2(com_tlm_u_tlm_tx_vc0_trn_usr_d[21]), + .LO(com_tlm_u_tlm_tx_vc0_trn_N_42833_i) + ); + defparam com_tlm_u_tlm_tx_vc0_trn_d_o_4_i_0_20_.INIT = 8'hD8; + LUT3_L com_tlm_u_tlm_tx_vc0_trn_d_o_4_i_0_20_ ( + .I0(com_tlm_u_tlm_tx_vc0_trn_N_61322), + .I1(com_N_63649), + .I2(com_tlm_u_tlm_tx_vc0_trn_usr_d[20]), + .LO(com_tlm_u_tlm_tx_vc0_trn_N_42831_i) + ); + defparam com_tlm_u_tlm_tx_vc0_trn_d_o_4_i_0_19_.INIT = 8'hD8; + LUT3_L com_tlm_u_tlm_tx_vc0_trn_d_o_4_i_0_19_ ( + .I0(com_tlm_u_tlm_tx_vc0_trn_N_61322), + .I1(com_N_63648), + .I2(com_tlm_u_tlm_tx_vc0_trn_usr_d[19]), + .LO(com_tlm_u_tlm_tx_vc0_trn_N_42829_i) + ); + defparam com_tlm_u_tlm_tx_vc0_trn_N_86273_i.INIT = 16'hD5C0; + LUT4_L com_tlm_u_tlm_tx_vc0_trn_N_86273_i ( + .I0(com_tlm_u_tlm_tx_vc0_trn_N_61322), + .I1(com_tlm_u_tlm_tx_vc0_trn_N_61337), + .I2(com_TLP_data_reg_50_), + .I3(com_tlm_u_tlm_tx_vc0_trn_usr_d[18]), + .LO(com_tlm_u_tlm_tx_vc0_trn_N_86273_i_3527) + ); + defparam com_tlm_u_tlm_tx_vc0_trn_N_86272_i.INIT = 16'hD5C0; + LUT4_L com_tlm_u_tlm_tx_vc0_trn_N_86272_i ( + .I0(com_tlm_u_tlm_tx_vc0_trn_N_61322), + .I1(com_tlm_u_tlm_tx_vc0_trn_N_61337), + .I2(com_TLP_data_reg_49_), + .I3(com_tlm_u_tlm_tx_vc0_trn_usr_d[17]), + .LO(com_tlm_u_tlm_tx_vc0_trn_N_86272_i_3528) + ); + defparam com_tlm_u_tlm_tx_vc0_trn_N_86271_i.INIT = 16'hD5C0; + LUT4_L com_tlm_u_tlm_tx_vc0_trn_N_86271_i ( + .I0(com_tlm_u_tlm_tx_vc0_trn_N_61322), + .I1(com_tlm_u_tlm_tx_vc0_trn_N_61337), + .I2(com_TLP_data_reg_48_), + .I3(com_tlm_u_tlm_tx_vc0_trn_usr_d[16]), + .LO(com_tlm_u_tlm_tx_vc0_trn_N_86271_i_3529) + ); + defparam com_tlm_u_tlm_tx_vc0_trn_d_o_4_i_0_15_.INIT = 8'hD8; + LUT3_L com_tlm_u_tlm_tx_vc0_trn_d_o_4_i_0_15_ ( + .I0(com_tlm_u_tlm_tx_vc0_trn_N_61322), + .I1(com_N_63647), + .I2(com_tlm_u_tlm_tx_vc0_trn_usr_d[15]), + .LO(com_tlm_u_tlm_tx_vc0_trn_N_42824_i) + ); + defparam com_tlm_u_tlm_tx_vc0_trn_N_86270_i.INIT = 16'hD5C0; + LUT4_L com_tlm_u_tlm_tx_vc0_trn_N_86270_i ( + .I0(com_tlm_u_tlm_tx_vc0_trn_N_61322), + .I1(com_tlm_u_tlm_tx_vc0_trn_N_61337), + .I2(com_TLP_data_reg_46_), + .I3(com_tlm_u_tlm_tx_vc0_trn_usr_d[14]), + .LO(com_tlm_u_tlm_tx_vc0_trn_N_86270_i_3530) + ); + defparam com_tlm_u_tlm_tx_vc0_trn_d_o_4_i_0_13_.INIT = 8'hD8; + LUT3_L com_tlm_u_tlm_tx_vc0_trn_d_o_4_i_0_13_ ( + .I0(com_tlm_u_tlm_tx_vc0_trn_N_61322), + .I1(com_N_63646), + .I2(com_tlm_u_tlm_tx_vc0_trn_usr_d[13]), + .LO(com_tlm_u_tlm_tx_vc0_trn_N_42821_i) + ); + defparam com_tlm_u_tlm_tx_vc0_trn_N_86269_i.INIT = 16'hD5C0; + LUT4_L com_tlm_u_tlm_tx_vc0_trn_N_86269_i ( + .I0(com_tlm_u_tlm_tx_vc0_trn_N_61322), + .I1(com_tlm_u_tlm_tx_vc0_trn_N_61337), + .I2(com_TLP_data_reg_44_), + .I3(com_tlm_u_tlm_tx_vc0_trn_usr_d[12]), + .LO(com_tlm_u_tlm_tx_vc0_trn_N_86269_i_3531) + ); + defparam com_tlm_u_tlm_tx_vc0_trn_d_o_4_i_0_11_.INIT = 8'hD8; + LUT3_L com_tlm_u_tlm_tx_vc0_trn_d_o_4_i_0_11_ ( + .I0(com_tlm_u_tlm_tx_vc0_trn_N_61322), + .I1(com_N_63645), + .I2(com_tlm_u_tlm_tx_vc0_trn_usr_d[11]), + .LO(com_tlm_u_tlm_tx_vc0_trn_N_42818_i) + ); + defparam com_tlm_u_tlm_tx_vc0_trn_N_86281_i.INIT = 16'hD5C0; + LUT4_L com_tlm_u_tlm_tx_vc0_trn_N_86281_i ( + .I0(com_tlm_u_tlm_tx_vc0_trn_N_61322), + .I1(com_tlm_u_tlm_tx_vc0_trn_N_61337), + .I2(com_TLP_data_reg_8_), + .I3(com_tlm_u_tlm_tx_vc0_trn_usr_d[40]), + .LO(com_tlm_u_tlm_tx_vc0_trn_N_86281_i_3532) + ); + defparam com_tlm_u_tlm_tx_vc0_trn_N_86280_i.INIT = 16'hD5C0; + LUT4_L com_tlm_u_tlm_tx_vc0_trn_N_86280_i ( + .I0(com_tlm_u_tlm_tx_vc0_trn_N_61322), + .I1(com_tlm_u_tlm_tx_vc0_trn_N_61337), + .I2(com_TLP_data_reg_7_), + .I3(com_tlm_u_tlm_tx_vc0_trn_usr_d[39]), + .LO(com_tlm_u_tlm_tx_vc0_trn_N_86280_i_3533) + ); + defparam com_tlm_u_tlm_tx_vc0_trn_N_86279_i.INIT = 16'hD5C0; + LUT4_L com_tlm_u_tlm_tx_vc0_trn_N_86279_i ( + .I0(com_tlm_u_tlm_tx_vc0_trn_N_61322), + .I1(com_tlm_u_tlm_tx_vc0_trn_N_61337), + .I2(com_TLP_data_reg_6_), + .I3(com_tlm_u_tlm_tx_vc0_trn_usr_d[38]), + .LO(com_tlm_u_tlm_tx_vc0_trn_N_86279_i_3534) + ); + defparam com_tlm_u_tlm_tx_vc0_trn_N_86278_i.INIT = 16'hD5C0; + LUT4_L com_tlm_u_tlm_tx_vc0_trn_N_86278_i ( + .I0(com_tlm_u_tlm_tx_vc0_trn_N_61322), + .I1(com_tlm_u_tlm_tx_vc0_trn_N_61337), + .I2(com_TLP_data_reg_5_), + .I3(com_tlm_u_tlm_tx_vc0_trn_usr_d[37]), + .LO(com_tlm_u_tlm_tx_vc0_trn_N_86278_i_3535) + ); + defparam com_tlm_u_tlm_tx_vc0_trn_N_86277_i.INIT = 16'hD5C0; + LUT4_L com_tlm_u_tlm_tx_vc0_trn_N_86277_i ( + .I0(com_tlm_u_tlm_tx_vc0_trn_N_61322), + .I1(com_tlm_u_tlm_tx_vc0_trn_N_61337), + .I2(com_TLP_data_reg_4_), + .I3(com_tlm_u_tlm_tx_vc0_trn_usr_d[36]), + .LO(com_tlm_u_tlm_tx_vc0_trn_N_86277_i_3536) + ); + defparam com_tlm_u_tlm_tx_vc0_trn_N_86276_i.INIT = 16'hD5C0; + LUT4_L com_tlm_u_tlm_tx_vc0_trn_N_86276_i ( + .I0(com_tlm_u_tlm_tx_vc0_trn_N_61322), + .I1(com_tlm_u_tlm_tx_vc0_trn_N_61337), + .I2(com_TLP_data_reg_3_), + .I3(com_tlm_u_tlm_tx_vc0_trn_usr_d[35]), + .LO(com_tlm_u_tlm_tx_vc0_trn_N_86276_i_3537) + ); + defparam com_tlm_u_tlm_tx_vc0_trn_N_86275_i.INIT = 16'hD5C0; + LUT4_L com_tlm_u_tlm_tx_vc0_trn_N_86275_i ( + .I0(com_tlm_u_tlm_tx_vc0_trn_N_61322), + .I1(com_tlm_u_tlm_tx_vc0_trn_N_61337), + .I2(com_TLP_data_reg_2_), + .I3(com_tlm_u_tlm_tx_vc0_trn_usr_d[34]), + .LO(com_tlm_u_tlm_tx_vc0_trn_N_86275_i_3538) + ); + defparam com_tlm_u_tlm_tx_vc0_trn_N_86274_i.INIT = 16'hD5C0; + LUT4_L com_tlm_u_tlm_tx_vc0_trn_N_86274_i ( + .I0(com_tlm_u_tlm_tx_vc0_trn_N_61322), + .I1(com_tlm_u_tlm_tx_vc0_trn_N_61337), + .I2(com_TLP_data_reg_1_), + .I3(com_tlm_u_tlm_tx_vc0_trn_usr_d[33]), + .LO(com_tlm_u_tlm_tx_vc0_trn_N_86274_i_3539) + ); + defparam com_tlm_u_tlm_tx_vc0_trn_N_85835_i.INIT = 8'h73; + LUT3_L com_tlm_u_tlm_tx_vc0_trn_N_85835_i ( + .I0(com_tlm_u_tlm_tx_vc0_trn_N_61322), + .I1(com_tlm_u_tlm_tx_vc0_trn_d_o_4_i_i_0[32]), + .I2(com_tlm_u_tlm_tx_vc0_trn_usr_d[32]), + .LO(com_tlm_u_tlm_tx_vc0_trn_N_85835_i_3540) + ); + defparam com_tlm_u_tlm_tx_vc0_trn_d_o_4_i_0_31_.INIT = 8'hD8; + LUT3_L com_tlm_u_tlm_tx_vc0_trn_d_o_4_i_0_31_ ( + .I0(com_tlm_u_tlm_tx_vc0_trn_N_61322), + .I1(com_N_63630), + .I2(com_tlm_u_tlm_tx_vc0_trn_usr_d[31]), + .LO(com_tlm_u_tlm_tx_vc0_trn_N_42853_i) + ); + defparam com_tlm_u_tlm_tx_vc0_trn_d_o_4_i_0_30_.INIT = 8'hD8; + LUT3_L com_tlm_u_tlm_tx_vc0_trn_d_o_4_i_0_30_ ( + .I0(com_tlm_u_tlm_tx_vc0_trn_N_61322), + .I1(com_N_63639), + .I2(com_tlm_u_tlm_tx_vc0_trn_usr_d[30]), + .LO(com_tlm_u_tlm_tx_vc0_trn_N_42851_i) + ); + defparam com_tlm_u_tlm_tx_vc0_trn_d_o_4_i_0_29_.INIT = 8'hD8; + LUT3_L com_tlm_u_tlm_tx_vc0_trn_d_o_4_i_0_29_ ( + .I0(com_tlm_u_tlm_tx_vc0_trn_N_61322), + .I1(com_N_63638), + .I2(com_tlm_u_tlm_tx_vc0_trn_usr_d[29]), + .LO(com_tlm_u_tlm_tx_vc0_trn_N_42849_i) + ); + defparam com_tlm_u_tlm_tx_vc0_trn_d_o_4_i_0_28_.INIT = 8'hD8; + LUT3_L com_tlm_u_tlm_tx_vc0_trn_d_o_4_i_0_28_ ( + .I0(com_tlm_u_tlm_tx_vc0_trn_N_61322), + .I1(com_N_63637), + .I2(com_tlm_u_tlm_tx_vc0_trn_usr_d[28]), + .LO(com_tlm_u_tlm_tx_vc0_trn_N_42847_i) + ); + defparam com_tlm_u_tlm_tx_vc0_trn_d_o_4_i_0_27_.INIT = 8'hD8; + LUT3_L com_tlm_u_tlm_tx_vc0_trn_d_o_4_i_0_27_ ( + .I0(com_tlm_u_tlm_tx_vc0_trn_N_61322), + .I1(com_N_63636), + .I2(com_tlm_u_tlm_tx_vc0_trn_usr_d[27]), + .LO(com_tlm_u_tlm_tx_vc0_trn_N_42845_i) + ); + defparam com_tlm_u_tlm_tx_vc0_trn_d_o_4_i_0_26_.INIT = 8'hD8; + LUT3_L com_tlm_u_tlm_tx_vc0_trn_d_o_4_i_0_26_ ( + .I0(com_tlm_u_tlm_tx_vc0_trn_N_61322), + .I1(com_N_63635), + .I2(com_tlm_u_tlm_tx_vc0_trn_usr_d[26]), + .LO(com_tlm_u_tlm_tx_vc0_trn_N_42843_i) + ); + defparam com_tlm_u_tlm_tx_vc0_trn_N_86291_i.INIT = 16'hD5C0; + LUT4_L com_tlm_u_tlm_tx_vc0_trn_N_86291_i ( + .I0(com_tlm_u_tlm_tx_vc0_trn_N_61322), + .I1(com_tlm_u_tlm_tx_vc0_trn_N_61337), + .I2(com_TLP_data_reg_23_), + .I3(com_tlm_u_tlm_tx_vc0_trn_usr_d[55]), + .LO(com_tlm_u_tlm_tx_vc0_trn_N_86291_i_3541) + ); + defparam com_tlm_u_tlm_tx_vc0_trn_d_o_4_i_0_54_.INIT = 8'hD8; + LUT3_L com_tlm_u_tlm_tx_vc0_trn_d_o_4_i_0_54_ ( + .I0(com_tlm_u_tlm_tx_vc0_trn_N_61322), + .I1(com_N_63661), + .I2(com_tlm_u_tlm_tx_vc0_trn_usr_d[54]), + .LO(com_tlm_u_tlm_tx_vc0_trn_N_42882_i) + ); + defparam com_tlm_u_tlm_tx_vc0_trn_d_o_4_i_0_53_.INIT = 8'hD8; + LUT3_L com_tlm_u_tlm_tx_vc0_trn_d_o_4_i_0_53_ ( + .I0(com_tlm_u_tlm_tx_vc0_trn_N_61322), + .I1(com_N_63634), + .I2(com_tlm_u_tlm_tx_vc0_trn_usr_d[53]), + .LO(com_tlm_u_tlm_tx_vc0_trn_N_42880_i) + ); + defparam com_tlm_u_tlm_tx_vc0_trn_d_o_4_i_0_52_.INIT = 8'hD8; + LUT3_L com_tlm_u_tlm_tx_vc0_trn_d_o_4_i_0_52_ ( + .I0(com_tlm_u_tlm_tx_vc0_trn_N_61322), + .I1(com_N_63633), + .I2(com_tlm_u_tlm_tx_vc0_trn_usr_d[52]), + .LO(com_tlm_u_tlm_tx_vc0_trn_N_42878_i) + ); + defparam com_tlm_u_tlm_tx_vc0_trn_N_86290_i.INIT = 16'hD5C0; + LUT4_L com_tlm_u_tlm_tx_vc0_trn_N_86290_i ( + .I0(com_tlm_u_tlm_tx_vc0_trn_N_61322), + .I1(com_tlm_u_tlm_tx_vc0_trn_N_61337), + .I2(com_TLP_data_reg_19_), + .I3(com_tlm_u_tlm_tx_vc0_trn_usr_d[51]), + .LO(com_tlm_u_tlm_tx_vc0_trn_N_86290_i_3542) + ); + defparam com_tlm_u_tlm_tx_vc0_trn_N_86289_i.INIT = 16'hD5C0; + LUT4_L com_tlm_u_tlm_tx_vc0_trn_N_86289_i ( + .I0(com_tlm_u_tlm_tx_vc0_trn_N_61322), + .I1(com_tlm_u_tlm_tx_vc0_trn_N_61337), + .I2(com_TLP_data_reg_18_), + .I3(com_tlm_u_tlm_tx_vc0_trn_usr_d[50]), + .LO(com_tlm_u_tlm_tx_vc0_trn_N_86289_i_3543) + ); + defparam com_tlm_u_tlm_tx_vc0_trn_N_86288_i.INIT = 16'hD5C0; + LUT4_L com_tlm_u_tlm_tx_vc0_trn_N_86288_i ( + .I0(com_tlm_u_tlm_tx_vc0_trn_N_61322), + .I1(com_tlm_u_tlm_tx_vc0_trn_N_61337), + .I2(com_TLP_data_reg_17_), + .I3(com_tlm_u_tlm_tx_vc0_trn_usr_d[49]), + .LO(com_tlm_u_tlm_tx_vc0_trn_N_86288_i_3544) + ); + defparam com_tlm_u_tlm_tx_vc0_trn_N_86287_i.INIT = 16'hD5C0; + LUT4_L com_tlm_u_tlm_tx_vc0_trn_N_86287_i ( + .I0(com_tlm_u_tlm_tx_vc0_trn_N_61322), + .I1(com_tlm_u_tlm_tx_vc0_trn_N_61337), + .I2(com_TLP_data_reg_16_), + .I3(com_tlm_u_tlm_tx_vc0_trn_usr_d[48]), + .LO(com_tlm_u_tlm_tx_vc0_trn_N_86287_i_3545) + ); + defparam com_tlm_u_tlm_tx_vc0_trn_N_86286_i.INIT = 16'hD5C0; + LUT4_L com_tlm_u_tlm_tx_vc0_trn_N_86286_i ( + .I0(com_tlm_u_tlm_tx_vc0_trn_N_61322), + .I1(com_tlm_u_tlm_tx_vc0_trn_N_61337), + .I2(com_TLP_data_reg_15_), + .I3(com_tlm_u_tlm_tx_vc0_trn_usr_d[47]), + .LO(com_tlm_u_tlm_tx_vc0_trn_N_86286_i_3546) + ); + defparam com_tlm_u_tlm_tx_vc0_trn_N_86285_i.INIT = 16'hD5C0; + LUT4_L com_tlm_u_tlm_tx_vc0_trn_N_86285_i ( + .I0(com_tlm_u_tlm_tx_vc0_trn_N_61322), + .I1(com_tlm_u_tlm_tx_vc0_trn_N_61337), + .I2(com_TLP_data_reg_14_), + .I3(com_tlm_u_tlm_tx_vc0_trn_usr_d[46]), + .LO(com_tlm_u_tlm_tx_vc0_trn_N_86285_i_3547) + ); + defparam com_tlm_u_tlm_tx_vc0_trn_d_o_4_i_0_45_.INIT = 8'hD8; + LUT3_L com_tlm_u_tlm_tx_vc0_trn_d_o_4_i_0_45_ ( + .I0(com_tlm_u_tlm_tx_vc0_trn_N_61322), + .I1(com_N_63632), + .I2(com_tlm_u_tlm_tx_vc0_trn_usr_d[45]), + .LO(com_tlm_u_tlm_tx_vc0_trn_N_42870_i) + ); + defparam com_tlm_u_tlm_tx_vc0_trn_d_o_4_i_0_44_.INIT = 8'hD8; + LUT3_L com_tlm_u_tlm_tx_vc0_trn_d_o_4_i_0_44_ ( + .I0(com_tlm_u_tlm_tx_vc0_trn_N_61322), + .I1(com_N_63631), + .I2(com_tlm_u_tlm_tx_vc0_trn_usr_d[44]), + .LO(com_tlm_u_tlm_tx_vc0_trn_N_42868_i) + ); + defparam com_tlm_u_tlm_tx_vc0_trn_N_86284_i.INIT = 16'hD5C0; + LUT4_L com_tlm_u_tlm_tx_vc0_trn_N_86284_i ( + .I0(com_tlm_u_tlm_tx_vc0_trn_N_61322), + .I1(com_tlm_u_tlm_tx_vc0_trn_N_61337), + .I2(com_TLP_data_reg_11_), + .I3(com_tlm_u_tlm_tx_vc0_trn_usr_d[43]), + .LO(com_tlm_u_tlm_tx_vc0_trn_N_86284_i_3548) + ); + defparam com_tlm_u_tlm_tx_vc0_trn_N_86283_i.INIT = 16'hD5C0; + LUT4_L com_tlm_u_tlm_tx_vc0_trn_N_86283_i ( + .I0(com_tlm_u_tlm_tx_vc0_trn_N_61322), + .I1(com_tlm_u_tlm_tx_vc0_trn_N_61337), + .I2(com_TLP_data_reg_10_), + .I3(com_tlm_u_tlm_tx_vc0_trn_usr_d[42]), + .LO(com_tlm_u_tlm_tx_vc0_trn_N_86283_i_3549) + ); + defparam com_tlm_u_tlm_tx_vc0_trn_N_86282_i.INIT = 16'hD5C0; + LUT4_L com_tlm_u_tlm_tx_vc0_trn_N_86282_i ( + .I0(com_tlm_u_tlm_tx_vc0_trn_N_61322), + .I1(com_tlm_u_tlm_tx_vc0_trn_N_61337), + .I2(com_TLP_data_reg_9_), + .I3(com_tlm_u_tlm_tx_vc0_trn_usr_d[41]), + .LO(com_tlm_u_tlm_tx_vc0_trn_N_86282_i_3550) + ); + defparam com_tlm_u_tlm_tx_vc0_trn_N_86292_i.INIT = 16'hD5C0; + LUT4_L com_tlm_u_tlm_tx_vc0_trn_N_86292_i ( + .I0(com_tlm_u_tlm_tx_vc0_trn_N_61322), + .I1(com_tlm_u_tlm_tx_vc0_trn_N_61337), + .I2(com_TLP_data_reg_31_), + .I3(com_tlm_u_tlm_tx_vc0_trn_usr_d[63]), + .LO(com_tlm_u_tlm_tx_vc0_trn_N_86292_i_3551) + ); + defparam com_tlm_u_tlm_tx_vc0_trn_d_o_4_i_0_62_.INIT = 8'hC8; + LUT3_L com_tlm_u_tlm_tx_vc0_trn_d_o_4_i_0_62_ ( + .I0(com_tlm_u_tlm_tx_vc0_trn_N_61322), + .I1(com_tlm_u_tlm_tx_vc0_trn_d_o_4_i_0_0_62__3490), + .I2(com_tlm_u_tlm_tx_vc0_trn_usr_d[62]), + .LO(com_tlm_u_tlm_tx_vc0_trn_N_42897_i) + ); + defparam com_tlm_u_tlm_tx_vc0_trn_d_o_4_i_0_61_.INIT = 8'hC8; + LUT3_L com_tlm_u_tlm_tx_vc0_trn_d_o_4_i_0_61_ ( + .I0(com_tlm_u_tlm_tx_vc0_trn_N_61322), + .I1(com_tlm_u_tlm_tx_vc0_trn_d_o_4_i_0_0_61__3491), + .I2(com_tlm_u_tlm_tx_vc0_trn_usr_d[61]), + .LO(com_tlm_u_tlm_tx_vc0_trn_N_42895_i) + ); + defparam com_tlm_u_tlm_tx_vc0_trn_d_o_4_i_0_60_.INIT = 8'hD8; + LUT3_L com_tlm_u_tlm_tx_vc0_trn_d_o_4_i_0_60_ ( + .I0(com_tlm_u_tlm_tx_vc0_trn_N_61322), + .I1(com_N_63664), + .I2(com_tlm_u_tlm_tx_vc0_trn_usr_d[60]), + .LO(com_tlm_u_tlm_tx_vc0_trn_N_42893_i) + ); + defparam com_tlm_u_tlm_tx_vc0_trn_d_o_4_i_0_59_.INIT = 8'h8C; + LUT3_L com_tlm_u_tlm_tx_vc0_trn_d_o_4_i_0_59_ ( + .I0(com_tlp_data_27_), + .I1(com_tlm_u_tlm_tx_vc0_trn_d_o_4_i_0_0_59__3492), + .I2(com_tlm_u_tlm_tx_vc0_trn_cfg_o_2), + .LO(com_tlm_u_tlm_tx_vc0_trn_N_42891_i) + ); + defparam com_tlm_u_tlm_tx_vc0_trn_d_o_4_i_0_58_.INIT = 8'hD8; + LUT3_L com_tlm_u_tlm_tx_vc0_trn_d_o_4_i_0_58_ ( + .I0(com_tlm_u_tlm_tx_vc0_trn_N_61322), + .I1(com_N_63663), + .I2(com_tlm_u_tlm_tx_vc0_trn_usr_d[58]), + .LO(com_tlm_u_tlm_tx_vc0_trn_N_42889_i) + ); + defparam com_tlm_u_tlm_tx_vc0_trn_d_o_4_i_0_57_.INIT = 8'h8C; + LUT3_L com_tlm_u_tlm_tx_vc0_trn_d_o_4_i_0_57_ ( + .I0(com_tlp_data_27_), + .I1(com_tlm_u_tlm_tx_vc0_trn_d_o_4_i_0_0_57__3493), + .I2(com_tlm_u_tlm_tx_vc0_trn_cfg_o_2), + .LO(com_tlm_u_tlm_tx_vc0_trn_N_42887_i) + ); + defparam com_tlm_u_tlm_tx_vc0_trn_d_o_4_i_0_56_.INIT = 8'hD8; + LUT3_L com_tlm_u_tlm_tx_vc0_trn_d_o_4_i_0_56_ ( + .I0(com_tlm_u_tlm_tx_vc0_trn_N_61322), + .I1(com_N_63662), + .I2(com_tlm_u_tlm_tx_vc0_trn_usr_d[56]), + .LO(com_tlm_u_tlm_tx_vc0_trn_N_42885_i) + ); + defparam com_tlm_u_tlm_tx_vc0_trn_trn_rem_i.INIT = 4'h1; + LUT1_L com_tlm_u_tlm_tx_vc0_trn_trn_rem_i ( + .I0(com_tlm_u_tlm_tx_vc0_trn_trn_rem), + .LO(com_tlm_u_tlm_tx_vc0_trn_rem_i) + ); + defparam com_tlm_u_tlm_tx_vc0_trn_usr_d_i_62_.INIT = 4'h1; + LUT1_L com_tlm_u_tlm_tx_vc0_trn_usr_d_i_62_ ( + .I0(com_tlm_u_tlm_tx_vc0_trn_usr_d[62]), + .LO(com_tlm_u_tlm_tx_vc0_trn_usr_d_i[62]) + ); + defparam com_tlm_u_tlm_tx_vc0_trn_N_56499_i_i.INIT = 4'h1; + LUT1_L com_tlm_u_tlm_tx_vc0_trn_N_56499_i_i ( + .I0(com_tlm_u_tlm_tx_vc0_trn_N_56499_i), + .LO(com_tlm_u_tlm_tx_vc0_trn_N_56499_i_i_3494) + ); + defparam com_tlm_u_tlm_tx_vc0_trn_N_60513_i.INIT = 4'hB; + LUT2_L com_tlm_u_tlm_tx_vc0_trn_N_60513_i ( + .I0(com_tlm_u_tlm_tx_vc0_trn_trn_tdst_dsc), + .I1(trn_teof_n), + .LO(com_tlm_u_tlm_tx_vc0_trn_N_60513_i_3495) + ); + defparam com_tlm_u_tlm_tx_vc0_trn_usr_eof_filt_0_a2_0_a2_0_a2.INIT = 4'h8; + LUT2_L com_tlm_u_tlm_tx_vc0_trn_usr_eof_filt_0_a2_0_a2_0_a2 ( + .I0(com_tlm_u_tlm_tx_vc0_trn_usr_eof_3496), + .I1(com_tlm_u_tlm_tx_vc0_trn_usr_frame_3504), + .LO(com_tlm_u_tlm_tx_vc0_trn_usr_eof_filt) + ); + defparam com_tlm_u_tlm_tx_vc0_trn_N_60512_i.INIT = 4'hB; + LUT2_L com_tlm_u_tlm_tx_vc0_trn_N_60512_i ( + .I0(trn_teof_n), + .I1(trn_trem_n_6088[0]), + .LO(com_tlm_u_tlm_tx_vc0_trn_N_60512_i_3497) + ); + defparam com_tlm_u_tlm_tx_vc0_trn_un13_pkt_incoming_o_i.INIT = 4'hE; + LUT2_L com_tlm_u_tlm_tx_vc0_trn_un13_pkt_incoming_o_i ( + .I0(com_tlm_u_tlm_tx_vc0_trn_pkts_in_trn[0]), + .I1(com_tlm_u_tlm_tx_vc0_trn_pkts_in_trn[1]), + .LO(com_tlm_u_tlm_tx_vc0_trn_un13_pkt_incoming_o_i_3498) + ); + defparam com_tlm_u_tlm_tx_vc0_trn_usr_abort_3_i_0_0.INIT = 4'h4; + LUT2_L com_tlm_u_tlm_tx_vc0_trn_usr_abort_3_i_0_0 ( + .I0(com_tlm_u_tlm_tx_vc0_trn_N_56499_i), + .I1(com_tlm_u_tlm_tx_vc0_trn_usr_frame_in_3509), + .LO(com_tlm_u_tlm_tx_vc0_trn_N_16671_i) + ); + defparam com_tlm_u_tlm_tx_vc0_trn_load_val_64_load_value10_i.INIT = 4'h1; + LUT1_L com_tlm_u_tlm_tx_vc0_trn_load_val_64_load_value10_i ( + .I0(com_tlm_u_tlm_tx_vc0_trn_load_value10), + .LO(com_tlm_u_tlm_tx_vc0_trn_load_value10_i) + ); + defparam com_tlm_u_tlm_tx_vc0_trn_N_86698_i.INIT = 4'hE; + LUT2_L com_tlm_u_tlm_tx_vc0_trn_N_86698_i ( + .I0(com_tlm_u_tlm_tx_vc0_trn_usr_start), + .I1(com_tlm_u_tlm_tx_vc0_trn_cfg_o_2), + .LO(com_tlm_u_tlm_tx_vc0_trn_N_86698_i_3499) + ); + defparam com_tlm_u_tlm_tx_vc0_trn_usr_frame_in17_0_a2_0_a2_0_a2.INIT = 4'h2; + LUT2_L com_tlm_u_tlm_tx_vc0_trn_usr_frame_in17_0_a2_0_a2_0_a2 ( + .I0(com_tlm_u_tlm_tx_vc0_trn_N_56499_i), + .I1(trn_tsof_n), + .LO(com_tlm_u_tlm_tx_vc0_trn_usr_frame_in17) + ); + defparam com_tlm_u_tlm_tx_vc0_trn_eof_o_5_i_0_0.INIT = 16'hC444; + LUT4_L com_tlm_u_tlm_tx_vc0_trn_eof_o_5_i_0_0 ( + .I0(com_N_58286), + .I1(com_tlm_u_tlm_tx_vc0_trn_eof_o_5_i_0_0_0_3500), + .I2(com_tlm_u_tlm_tx_vc0_trn_usr_frame_3504), + .I3(com_tlm_u_tlm_tx_vc0_trn_usr_vld_3503), + .LO(com_tlm_u_tlm_tx_vc0_trn_N_16676_i) + ); + defparam com_tlm_u_tlm_tx_vc0_trn_errfwd_o_5_i_0_0.INIT = 4'h8; + LUT2_L com_tlm_u_tlm_tx_vc0_trn_errfwd_o_5_i_0_0 ( + .I0(com_tlm_u_tlm_tx_vc0_trn_vld_o_5_i_0_a2_3564), + .I1(com_tlm_u_tlm_tx_vc0_trn_usr_errfwd_3501), + .LO(com_tlm_u_tlm_tx_vc0_trn_N_16678_i) + ); + defparam com_tlm_u_tlm_tx_vc0_trn_N_86736_i.INIT = 16'hDFC0; + LUT4_L com_tlm_u_tlm_tx_vc0_trn_N_86736_i ( + .I0(com_tlm_u_tlm_tx_vc0_trn_usr_frame_3504), + .I1(com_tlm_u_tlm_tx_vc0_trn_usr_sof_filt), + .I2(com_tlm_u_tlm_tx_vc0_trn_usr_vld_3503), + .I3(com_tlm_u_tlm_tx_vc0_trn_cfg_o_2), + .LO(com_tlm_u_tlm_tx_vc0_trn_N_86736_i_3502) + ); + defparam com_tlm_u_tlm_tx_vc0_trn_N_86547_i.INIT = 4'hE; + LUT2_L com_tlm_u_tlm_tx_vc0_trn_N_86547_i ( + .I0(com_tlm_u_tlm_tx_vc0_trn_vld_o_5_i_0_a2_3564), + .I1(com_tlm_u_tlm_tx_vc0_trn_N_61322), + .LO(com_tlm_u_tlm_tx_vc0_trn_N_86547_i_3505) + ); + defparam com_tlm_u_tlm_tx_vc0_trn_dsc_in_q_3_i_0.INIT = 16'h88C8; + LUT4_L com_tlm_u_tlm_tx_vc0_trn_dsc_in_q_3_i_0 ( + .I0(com_tlm_u_tlm_tx_vc0_trn_trn_tdst_dsc), + .I1(com_tlm_u_tlm_tx_vc0_trn_usr_eof_filt_q_4_), + .I2(com_tlm_u_tlm_tx_vc0_trn_usr_frame_in_3509), + .I3(trn_tsrc_dsc_n), + .LO(com_tlm_u_tlm_tx_vc0_trn_N_42903_i) + ); + defparam com_tlm_u_tlm_tx_vc0_trn_N_86737_i.INIT = 16'hAEAA; + LUT4_L com_tlm_u_tlm_tx_vc0_trn_N_86737_i ( + .I0(com_tlm_u_tlm_tx_vc0_trn_N_57342), + .I1(com_N_58286), + .I2(com_tlm_u_tlm_tx_vc0_trn_trn_tdst_rdy), + .I3(com_tlm_u_tlm_tx_vc0_trn_cfg_frame_in_3507), + .LO(com_tlm_u_tlm_tx_vc0_trn_N_86737_i_3506) + ); + defparam com_tlm_u_tlm_tx_vc0_trn_N_86293_i.INIT = 16'hDCCC; + LUT4_L com_tlm_u_tlm_tx_vc0_trn_N_86293_i ( + .I0(com_tlm_u_tlm_tx_vc0_trn_N_56234_i), + .I1(com_tlm_u_tlm_tx_vc0_trn_N_57343), + .I2(com_tlm_u_tlm_tx_vc0_trn_trn_tdst_rdy_o_3_0_0_0_0_a2_0_0), + .I3(com_tlm_u_tlm_tx_vc0_trn_usr_frame_in_3509), + .LO(com_tlm_u_tlm_tx_vc0_trn_N_86293_i_3508) + ); + defparam com_tlm_u_tlm_tx_vc0_trn_buffer_rdy_3_i_0.INIT = 16'h444C; + LUT4_L com_tlm_u_tlm_tx_vc0_trn_buffer_rdy_3_i_0 ( + .I0(com_tlm_u_tlm_tx_vc0_trn_buf_av_one_3511), + .I1(com_tlm_u_tlm_tx_vc0_trn_buffer_rdy_3_i_0_0_3510), + .I2(com_tlm_u_tlm_tx_vc0_trn_usr_start), + .I3(com_tlm_u_tlm_tx_vc0_trn_cfg_o_2), + .LO(com_tlm_u_tlm_tx_vc0_trn_N_42911_i) + ); + defparam com_tlm_u_tlm_tx_vc0_trn_un1_trn_tbuf_av_o_1_axb_4.INIT = 8'h78; + LUT3_L com_tlm_u_tlm_tx_vc0_trn_un1_trn_tbuf_av_o_1_axb_4 ( + .I0(com_tlm_u_tlm_tx_vc0_trn_N_44071_i), + .I1(com_tlm_u_tlm_tx_vc0_trn_start_frame_q_3526), + .I2(NlwRenamedSig_OI_trn_tbuf_av[4]), + .LO(com_tlm_u_tlm_tx_vc0_trn_un1_trn_tbuf_av_o_1_axb_4_3512) + ); + defparam com_tlm_u_tlm_tx_vc0_trn_un1_trn_tbuf_av_o_1_axb_3.INIT = 8'h78; + LUT3_L com_tlm_u_tlm_tx_vc0_trn_un1_trn_tbuf_av_o_1_axb_3 ( + .I0(com_tlm_u_tlm_tx_vc0_trn_N_44071_i), + .I1(com_tlm_u_tlm_tx_vc0_trn_start_frame_q_3526), + .I2(NlwRenamedSig_OI_trn_tbuf_av[3]), + .LO(com_tlm_u_tlm_tx_vc0_trn_un1_trn_tbuf_av_o_1_axb_3_3513) + ); + defparam com_tlm_u_tlm_tx_vc0_trn_un1_trn_tbuf_av_o_1_axb_2.INIT = 8'h78; + LUT3_L com_tlm_u_tlm_tx_vc0_trn_un1_trn_tbuf_av_o_1_axb_2 ( + .I0(com_tlm_u_tlm_tx_vc0_trn_N_44071_i), + .I1(com_tlm_u_tlm_tx_vc0_trn_start_frame_q_3526), + .I2(NlwRenamedSig_OI_trn_tbuf_av[2]), + .LO(com_tlm_u_tlm_tx_vc0_trn_un1_trn_tbuf_av_o_1_axb_2_3514) + ); + defparam com_tlm_u_tlm_tx_vc0_trn_un1_trn_tbuf_av_o_1_axb_1.INIT = 8'h78; + LUT3_L com_tlm_u_tlm_tx_vc0_trn_un1_trn_tbuf_av_o_1_axb_1 ( + .I0(com_tlm_u_tlm_tx_vc0_trn_N_44071_i), + .I1(com_tlm_u_tlm_tx_vc0_trn_start_frame_q_3526), + .I2(NlwRenamedSig_OI_trn_tbuf_av[1]), + .LO(com_tlm_u_tlm_tx_vc0_trn_un1_trn_tbuf_av_o_1_axb_1_3515) + ); + defparam com_tlm_u_tlm_tx_vc0_trn_un1_pkts_in_trn_1_axbxc1.INIT = 16'h5A96; + LUT4_L com_tlm_u_tlm_tx_vc0_trn_un1_pkts_in_trn_1_axbxc1 ( + .I0(com_tlm_u_tlm_tx_vc0_trn_pkts_in_trn[1]), + .I1(com_tlm_u_tlm_tx_vc0_trn_pkts_in_trn_1_sqmuxa_5917_i_0_0_3518), + .I2(com_tlm_u_tlm_tx_vc0_trn_un1_pkts_in_trn_1_ac0_0_3517), + .I3(com_tlm_u_tlm_tx_vc0_trn_usr_start), + .LO(com_tlm_u_tlm_tx_vc0_trn_un1_pkts_in_trn_1_axbxc1_3516) + ); + defparam com_tlm_u_tlm_tx_vc0_trn_un1_pkts_in_trn_1_axb0.INIT = 8'h6C; + LUT3_L com_tlm_u_tlm_tx_vc0_trn_un1_pkts_in_trn_1_axb0 ( + .I0(com_tlm_u_tlm_tx_vc0_trn_pkts_in_trn28_i_0_39418_3520), + .I1(com_tlm_u_tlm_tx_vc0_trn_pkts_in_trn[0]), + .I2(plm_link_up_2), + .LO(com_tlm_u_tlm_tx_vc0_trn_un1_pkts_in_trn_1_axb0_3519) + ); + defparam com_tlm_u_tlm_tx_vc0_trn_N_85836_i_1.INIT = 16'h3100; + LUT4_L com_tlm_u_tlm_tx_vc0_trn_N_85836_i_1 ( + .I0(com_N_55871_i), + .I1(com_N_56344_i), + .I2(com_tlm_u_tlm_tx_vc0_trn_rem_o_5_0_0_0_o3_1_3521), + .I3(com_state[1]), + .LO(com_tlm_u_tlm_tx_vc0_trn_N_85836_i_1_3563) + ); + defparam com_tlm_u_tlm_tx_vc0_trn_N_85887_i_1.INIT = 16'h0A3F; + LUT4_L com_tlm_u_tlm_tx_vc0_trn_N_85887_i_1 ( + .I0(com_tlm_u_tlm_tx_vc0_trn_N_58356_1_0), + .I1(com_tlm_u_tlm_tx_vc0_trn_un1_usr_abort_8_0_0_a2_0_0_3522), + .I2(NlwRenamedSig_OI_trn_tbuf_av[0]), + .I3(NlwRenamedSig_OI_trn_tbuf_av[1]), + .LO(com_tlm_u_tlm_tx_vc0_trn_N_85887_i_1_3524) + ); + defparam com_tlm_u_tlm_tx_vc0_trn_N_85887_i.INIT = 16'hCE2A; + LUT4 com_tlm_u_tlm_tx_vc0_trn_N_85887_i ( + .I0(com_tlm_u_tlm_tx_vc0_trn_N_58355), + .I1(com_tlm_u_tlm_tx_vc0_trn_N_85887_i_1_3524), + .I2(plm_link_up_2), + .I3(NlwRenamedSig_OI_trn_tbuf_av[1]), + .O(com_tlm_u_tlm_tx_vc0_trn_N_85887_i_3523) + ); + defparam com_tlm_u_tlm_tx_vc0_trn_un1_buf_av_one_1_i_0_a2_0_.INIT = 8'h02; + LUT3 com_tlm_u_tlm_tx_vc0_trn_un1_buf_av_one_1_i_0_a2_0_ ( + .I0(com_tlm_u_tlm_tx_vc0_trn_start_frame_q_3526), + .I1(com_tlm_u_tlm_tx_vc0_trn_usr_abort_3553), + .I2(com_tlm_u_tlm_tx_vc0_trn_released_buf_x_3525), + .O(com_tlm_u_tlm_tx_vc0_trn_un1_buf_av_one_1_i_0_a2[0]) + ); + FD com_tlm_u_tlm_tx_vc0_trn_usr_eof_filt_q_DOUT_0_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_trn_usr_eof_filt_q_N_6), + .Q(com_tlm_u_tlm_tx_vc0_trn_usr_eof_filt_q_4_) + ); + FD com_tlm_u_tlm_tx_vc0_trn_usr_no_eof_err ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_trn_usr_no_eof_err14), + .Q(com_tlm_u_tlm_tx_vc0_trn_trn_tdst_dsc) + ); + FD com_tlm_u_tlm_tx_vc0_trn_d_o_10_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_trn_N_42816_i), + .Q(com_tlm_u_tlm_tx_vc0_trn_d[10]) + ); + FD com_tlm_u_tlm_tx_vc0_trn_d_o_9_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_trn_N_42814_i), + .Q(com_tlm_u_tlm_tx_vc0_trn_d[9]) + ); + FD com_tlm_u_tlm_tx_vc0_trn_d_o_8_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_trn_N_42812_i), + .Q(com_tlm_u_tlm_tx_vc0_trn_d[8]) + ); + FD com_tlm_u_tlm_tx_vc0_trn_d_o_7_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_trn_N_42810_i), + .Q(com_tlm_u_tlm_tx_vc0_trn_d[7]) + ); + FD com_tlm_u_tlm_tx_vc0_trn_d_o_6_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_trn_N_42808_i), + .Q(com_tlm_u_tlm_tx_vc0_trn_d[6]) + ); + FD com_tlm_u_tlm_tx_vc0_trn_d_o_5_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_trn_N_42806_i), + .Q(com_tlm_u_tlm_tx_vc0_trn_d[5]) + ); + FD com_tlm_u_tlm_tx_vc0_trn_d_o_4_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_trn_N_42804_i), + .Q(com_tlm_u_tlm_tx_vc0_trn_d[4]) + ); + FD com_tlm_u_tlm_tx_vc0_trn_d_o_3_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_trn_N_42802_i), + .Q(com_tlm_u_tlm_tx_vc0_trn_d[3]) + ); + FD com_tlm_u_tlm_tx_vc0_trn_d_o_2_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_trn_N_42800_i), + .Q(com_tlm_u_tlm_tx_vc0_trn_d[2]) + ); + FD com_tlm_u_tlm_tx_vc0_trn_d_o_1_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_trn_N_42798_i), + .Q(com_tlm_u_tlm_tx_vc0_trn_d[1]) + ); + FD com_tlm_u_tlm_tx_vc0_trn_d_o_0_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_trn_N_42796_i), + .Q(com_tlm_u_tlm_tx_vc0_trn_d[0]) + ); + FD com_tlm_u_tlm_tx_vc0_trn_d_o_25_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_trn_N_42841_i), + .Q(com_tlm_u_tlm_tx_vc0_trn_d[25]) + ); + FD com_tlm_u_tlm_tx_vc0_trn_d_o_24_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_trn_N_42839_i), + .Q(com_tlm_u_tlm_tx_vc0_trn_d[24]) + ); + FD com_tlm_u_tlm_tx_vc0_trn_d_o_23_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_trn_N_42837_i), + .Q(com_tlm_u_tlm_tx_vc0_trn_d[23]) + ); + FD com_tlm_u_tlm_tx_vc0_trn_d_o_22_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_trn_N_42835_i), + .Q(com_tlm_u_tlm_tx_vc0_trn_d[22]) + ); + FD com_tlm_u_tlm_tx_vc0_trn_d_o_21_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_trn_N_42833_i), + .Q(com_tlm_u_tlm_tx_vc0_trn_d[21]) + ); + FD com_tlm_u_tlm_tx_vc0_trn_d_o_20_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_trn_N_42831_i), + .Q(com_tlm_u_tlm_tx_vc0_trn_d[20]) + ); + FD com_tlm_u_tlm_tx_vc0_trn_d_o_19_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_trn_N_42829_i), + .Q(com_tlm_u_tlm_tx_vc0_trn_d[19]) + ); + FD com_tlm_u_tlm_tx_vc0_trn_d_o_18_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_trn_N_86273_i_3527), + .Q(com_tlm_u_tlm_tx_vc0_trn_d[18]) + ); + FD com_tlm_u_tlm_tx_vc0_trn_d_o_17_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_trn_N_86272_i_3528), + .Q(com_tlm_u_tlm_tx_vc0_trn_d[17]) + ); + FD com_tlm_u_tlm_tx_vc0_trn_d_o_16_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_trn_N_86271_i_3529), + .Q(com_tlm_u_tlm_tx_vc0_trn_d[16]) + ); + FD com_tlm_u_tlm_tx_vc0_trn_d_o_15_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_trn_N_42824_i), + .Q(com_tlm_u_tlm_tx_vc0_trn_d[15]) + ); + FD com_tlm_u_tlm_tx_vc0_trn_d_o_14_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_trn_N_86270_i_3530), + .Q(com_tlm_u_tlm_tx_vc0_trn_d[14]) + ); + FD com_tlm_u_tlm_tx_vc0_trn_d_o_13_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_trn_N_42821_i), + .Q(com_tlm_u_tlm_tx_vc0_trn_d[13]) + ); + FD com_tlm_u_tlm_tx_vc0_trn_d_o_12_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_trn_N_86269_i_3531), + .Q(com_tlm_u_tlm_tx_vc0_trn_d[12]) + ); + FD com_tlm_u_tlm_tx_vc0_trn_d_o_11_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_trn_N_42818_i), + .Q(com_tlm_u_tlm_tx_vc0_trn_d[11]) + ); + FD com_tlm_u_tlm_tx_vc0_trn_d_o_40_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_trn_N_86281_i_3532), + .Q(com_tlm_u_tlm_tx_vc0_trn_d[40]) + ); + FD com_tlm_u_tlm_tx_vc0_trn_d_o_39_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_trn_N_86280_i_3533), + .Q(com_tlm_u_tlm_tx_vc0_trn_d[39]) + ); + FD com_tlm_u_tlm_tx_vc0_trn_d_o_38_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_trn_N_86279_i_3534), + .Q(com_tlm_u_tlm_tx_vc0_trn_d[38]) + ); + FD com_tlm_u_tlm_tx_vc0_trn_d_o_37_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_trn_N_86278_i_3535), + .Q(com_tlm_u_tlm_tx_vc0_trn_d[37]) + ); + FD com_tlm_u_tlm_tx_vc0_trn_d_o_36_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_trn_N_86277_i_3536), + .Q(com_tlm_u_tlm_tx_vc0_trn_d[36]) + ); + FD com_tlm_u_tlm_tx_vc0_trn_d_o_35_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_trn_N_86276_i_3537), + .Q(com_tlm_u_tlm_tx_vc0_trn_d[35]) + ); + FD com_tlm_u_tlm_tx_vc0_trn_d_o_34_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_trn_N_86275_i_3538), + .Q(com_tlm_u_tlm_tx_vc0_trn_d[34]) + ); + FD com_tlm_u_tlm_tx_vc0_trn_d_o_33_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_trn_N_86274_i_3539), + .Q(com_tlm_u_tlm_tx_vc0_trn_d[33]) + ); + FD com_tlm_u_tlm_tx_vc0_trn_d_o_32_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_trn_N_85835_i_3540), + .Q(com_tlm_u_tlm_tx_vc0_trn_d[32]) + ); + FD com_tlm_u_tlm_tx_vc0_trn_d_o_31_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_trn_N_42853_i), + .Q(com_tlm_u_tlm_tx_vc0_trn_d[31]) + ); + FD com_tlm_u_tlm_tx_vc0_trn_d_o_30_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_trn_N_42851_i), + .Q(com_tlm_u_tlm_tx_vc0_trn_d[30]) + ); + FD com_tlm_u_tlm_tx_vc0_trn_d_o_29_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_trn_N_42849_i), + .Q(com_tlm_u_tlm_tx_vc0_trn_d[29]) + ); + FD com_tlm_u_tlm_tx_vc0_trn_d_o_28_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_trn_N_42847_i), + .Q(com_tlm_u_tlm_tx_vc0_trn_d[28]) + ); + FD com_tlm_u_tlm_tx_vc0_trn_d_o_27_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_trn_N_42845_i), + .Q(com_tlm_u_tlm_tx_vc0_trn_d[27]) + ); + FD com_tlm_u_tlm_tx_vc0_trn_d_o_26_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_trn_N_42843_i), + .Q(com_tlm_u_tlm_tx_vc0_trn_d[26]) + ); + FD com_tlm_u_tlm_tx_vc0_trn_d_o_55_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_trn_N_86291_i_3541), + .Q(com_tlm_u_tlm_tx_vc0_trn_d[55]) + ); + FD com_tlm_u_tlm_tx_vc0_trn_d_o_54_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_trn_N_42882_i), + .Q(com_tlm_u_tlm_tx_vc0_trn_d[54]) + ); + FD com_tlm_u_tlm_tx_vc0_trn_d_o_53_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_trn_N_42880_i), + .Q(com_tlm_u_tlm_tx_vc0_trn_d[53]) + ); + FD com_tlm_u_tlm_tx_vc0_trn_d_o_52_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_trn_N_42878_i), + .Q(com_tlm_u_tlm_tx_vc0_trn_d[52]) + ); + FD com_tlm_u_tlm_tx_vc0_trn_d_o_51_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_trn_N_86290_i_3542), + .Q(com_tlm_u_tlm_tx_vc0_trn_d[51]) + ); + FD com_tlm_u_tlm_tx_vc0_trn_d_o_50_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_trn_N_86289_i_3543), + .Q(com_tlm_u_tlm_tx_vc0_trn_d[50]) + ); + FD com_tlm_u_tlm_tx_vc0_trn_d_o_49_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_trn_N_86288_i_3544), + .Q(com_tlm_u_tlm_tx_vc0_trn_d[49]) + ); + FD com_tlm_u_tlm_tx_vc0_trn_d_o_48_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_trn_N_86287_i_3545), + .Q(com_tlm_u_tlm_tx_vc0_trn_d[48]) + ); + FD com_tlm_u_tlm_tx_vc0_trn_d_o_47_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_trn_N_86286_i_3546), + .Q(com_tlm_u_tlm_tx_vc0_trn_d[47]) + ); + FD com_tlm_u_tlm_tx_vc0_trn_d_o_46_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_trn_N_86285_i_3547), + .Q(com_tlm_u_tlm_tx_vc0_trn_d[46]) + ); + FD com_tlm_u_tlm_tx_vc0_trn_d_o_45_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_trn_N_42870_i), + .Q(com_tlm_u_tlm_tx_vc0_trn_d[45]) + ); + FD com_tlm_u_tlm_tx_vc0_trn_d_o_44_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_trn_N_42868_i), + .Q(com_tlm_u_tlm_tx_vc0_trn_d[44]) + ); + FD com_tlm_u_tlm_tx_vc0_trn_d_o_43_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_trn_N_86284_i_3548), + .Q(com_tlm_u_tlm_tx_vc0_trn_d[43]) + ); + FD com_tlm_u_tlm_tx_vc0_trn_d_o_42_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_trn_N_86283_i_3549), + .Q(com_tlm_u_tlm_tx_vc0_trn_d[42]) + ); + FD com_tlm_u_tlm_tx_vc0_trn_d_o_41_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_trn_N_86282_i_3550), + .Q(com_tlm_u_tlm_tx_vc0_trn_d[41]) + ); + FD com_tlm_u_tlm_tx_vc0_trn_d_o_63_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_trn_N_86292_i_3551), + .Q(com_tlm_u_tlm_tx_vc0_trn_d[63]) + ); + FD com_tlm_u_tlm_tx_vc0_trn_d_o_62_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_trn_N_42897_i), + .Q(com_tlm_u_tlm_tx_vc0_trn_d[62]) + ); + FD com_tlm_u_tlm_tx_vc0_trn_d_o_61_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_trn_N_42895_i), + .Q(com_tlm_u_tlm_tx_vc0_trn_d[61]) + ); + FD com_tlm_u_tlm_tx_vc0_trn_d_o_60_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_trn_N_42893_i), + .Q(com_tlm_u_tlm_tx_vc0_trn_d[60]) + ); + FD com_tlm_u_tlm_tx_vc0_trn_d_o_59_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_trn_N_42891_i), + .Q(com_tlm_u_tlm_tx_vc0_trn_d[59]) + ); + FD com_tlm_u_tlm_tx_vc0_trn_d_o_58_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_trn_N_42889_i), + .Q(com_tlm_u_tlm_tx_vc0_trn_d[58]) + ); + FD com_tlm_u_tlm_tx_vc0_trn_d_o_57_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_trn_N_42887_i), + .Q(com_tlm_u_tlm_tx_vc0_trn_d[57]) + ); + FD com_tlm_u_tlm_tx_vc0_trn_d_o_56_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_trn_N_42885_i), + .Q(com_tlm_u_tlm_tx_vc0_trn_d[56]) + ); + FD com_tlm_u_tlm_tx_vc0_trn_usr_d_14_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(trn_td_6087[14]), + .Q(com_tlm_u_tlm_tx_vc0_trn_usr_d[14]) + ); + FD com_tlm_u_tlm_tx_vc0_trn_usr_d_13_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(trn_td_6087[13]), + .Q(com_tlm_u_tlm_tx_vc0_trn_usr_d[13]) + ); + FD com_tlm_u_tlm_tx_vc0_trn_usr_d_12_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(trn_td_6087[12]), + .Q(com_tlm_u_tlm_tx_vc0_trn_usr_d[12]) + ); + FD com_tlm_u_tlm_tx_vc0_trn_usr_d_11_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(trn_td_6087[11]), + .Q(com_tlm_u_tlm_tx_vc0_trn_usr_d[11]) + ); + FD com_tlm_u_tlm_tx_vc0_trn_usr_d_10_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(trn_td_6087[10]), + .Q(com_tlm_u_tlm_tx_vc0_trn_usr_d[10]) + ); + FD com_tlm_u_tlm_tx_vc0_trn_usr_d_9_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(trn_td_6087[9]), + .Q(com_tlm_u_tlm_tx_vc0_trn_usr_d[9]) + ); + FD com_tlm_u_tlm_tx_vc0_trn_usr_d_8_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(trn_td_6087[8]), + .Q(com_tlm_u_tlm_tx_vc0_trn_usr_d[8]) + ); + FD com_tlm_u_tlm_tx_vc0_trn_usr_d_7_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(trn_td_6087[7]), + .Q(com_tlm_u_tlm_tx_vc0_trn_usr_d[7]) + ); + FD com_tlm_u_tlm_tx_vc0_trn_usr_d_6_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(trn_td_6087[6]), + .Q(com_tlm_u_tlm_tx_vc0_trn_usr_d[6]) + ); + FD com_tlm_u_tlm_tx_vc0_trn_usr_d_5_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(trn_td_6087[5]), + .Q(com_tlm_u_tlm_tx_vc0_trn_usr_d[5]) + ); + FD com_tlm_u_tlm_tx_vc0_trn_usr_d_4_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(trn_td_6087[4]), + .Q(com_tlm_u_tlm_tx_vc0_trn_usr_d[4]) + ); + FD com_tlm_u_tlm_tx_vc0_trn_usr_d_3_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(trn_td_6087[3]), + .Q(com_tlm_u_tlm_tx_vc0_trn_usr_d[3]) + ); + FD com_tlm_u_tlm_tx_vc0_trn_usr_d_2_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(trn_td_6087[2]), + .Q(com_tlm_u_tlm_tx_vc0_trn_usr_d[2]) + ); + FD com_tlm_u_tlm_tx_vc0_trn_usr_d_1_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(trn_td_6087[1]), + .Q(com_tlm_u_tlm_tx_vc0_trn_usr_d[1]) + ); + FD com_tlm_u_tlm_tx_vc0_trn_usr_d_0_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(trn_td_6087[0]), + .Q(com_tlm_u_tlm_tx_vc0_trn_usr_d[0]) + ); + FD com_tlm_u_tlm_tx_vc0_trn_usr_d_29_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(trn_td_6087[29]), + .Q(com_tlm_u_tlm_tx_vc0_trn_usr_d[29]) + ); + FD com_tlm_u_tlm_tx_vc0_trn_usr_d_28_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(trn_td_6087[28]), + .Q(com_tlm_u_tlm_tx_vc0_trn_usr_d[28]) + ); + FD com_tlm_u_tlm_tx_vc0_trn_usr_d_27_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(trn_td_6087[27]), + .Q(com_tlm_u_tlm_tx_vc0_trn_usr_d[27]) + ); + FD com_tlm_u_tlm_tx_vc0_trn_usr_d_26_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(trn_td_6087[26]), + .Q(com_tlm_u_tlm_tx_vc0_trn_usr_d[26]) + ); + FD com_tlm_u_tlm_tx_vc0_trn_usr_d_25_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(trn_td_6087[25]), + .Q(com_tlm_u_tlm_tx_vc0_trn_usr_d[25]) + ); + FD com_tlm_u_tlm_tx_vc0_trn_usr_d_24_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(trn_td_6087[24]), + .Q(com_tlm_u_tlm_tx_vc0_trn_usr_d[24]) + ); + FD com_tlm_u_tlm_tx_vc0_trn_usr_d_23_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(trn_td_6087[23]), + .Q(com_tlm_u_tlm_tx_vc0_trn_usr_d[23]) + ); + FD com_tlm_u_tlm_tx_vc0_trn_usr_d_22_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(trn_td_6087[22]), + .Q(com_tlm_u_tlm_tx_vc0_trn_usr_d[22]) + ); + FD com_tlm_u_tlm_tx_vc0_trn_usr_d_21_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(trn_td_6087[21]), + .Q(com_tlm_u_tlm_tx_vc0_trn_usr_d[21]) + ); + FD com_tlm_u_tlm_tx_vc0_trn_usr_d_20_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(trn_td_6087[20]), + .Q(com_tlm_u_tlm_tx_vc0_trn_usr_d[20]) + ); + FD com_tlm_u_tlm_tx_vc0_trn_usr_d_19_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(trn_td_6087[19]), + .Q(com_tlm_u_tlm_tx_vc0_trn_usr_d[19]) + ); + FD com_tlm_u_tlm_tx_vc0_trn_usr_d_18_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(trn_td_6087[18]), + .Q(com_tlm_u_tlm_tx_vc0_trn_usr_d[18]) + ); + FD com_tlm_u_tlm_tx_vc0_trn_usr_d_17_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(trn_td_6087[17]), + .Q(com_tlm_u_tlm_tx_vc0_trn_usr_d[17]) + ); + FD com_tlm_u_tlm_tx_vc0_trn_usr_d_16_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(trn_td_6087[16]), + .Q(com_tlm_u_tlm_tx_vc0_trn_usr_d[16]) + ); + FD com_tlm_u_tlm_tx_vc0_trn_usr_d_15_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(trn_td_6087[15]), + .Q(com_tlm_u_tlm_tx_vc0_trn_usr_d[15]) + ); + FD com_tlm_u_tlm_tx_vc0_trn_usr_d_44_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(trn_td_6087[44]), + .Q(com_tlm_u_tlm_tx_vc0_trn_usr_d[44]) + ); + FD com_tlm_u_tlm_tx_vc0_trn_usr_d_43_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(trn_td_6087[43]), + .Q(com_tlm_u_tlm_tx_vc0_trn_usr_d[43]) + ); + FD com_tlm_u_tlm_tx_vc0_trn_usr_d_42_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(trn_td_6087[42]), + .Q(com_tlm_u_tlm_tx_vc0_trn_usr_d[42]) + ); + FD com_tlm_u_tlm_tx_vc0_trn_usr_d_41_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(trn_td_6087[41]), + .Q(com_tlm_u_tlm_tx_vc0_trn_usr_d[41]) + ); + FD com_tlm_u_tlm_tx_vc0_trn_usr_d_40_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(trn_td_6087[40]), + .Q(com_tlm_u_tlm_tx_vc0_trn_usr_d[40]) + ); + FD com_tlm_u_tlm_tx_vc0_trn_usr_d_39_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(trn_td_6087[39]), + .Q(com_tlm_u_tlm_tx_vc0_trn_usr_d[39]) + ); + FD com_tlm_u_tlm_tx_vc0_trn_usr_d_38_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(trn_td_6087[38]), + .Q(com_tlm_u_tlm_tx_vc0_trn_usr_d[38]) + ); + FD com_tlm_u_tlm_tx_vc0_trn_usr_d_37_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(trn_td_6087[37]), + .Q(com_tlm_u_tlm_tx_vc0_trn_usr_d[37]) + ); + FD com_tlm_u_tlm_tx_vc0_trn_usr_d_36_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(trn_td_6087[36]), + .Q(com_tlm_u_tlm_tx_vc0_trn_usr_d[36]) + ); + FD com_tlm_u_tlm_tx_vc0_trn_usr_d_35_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(trn_td_6087[35]), + .Q(com_tlm_u_tlm_tx_vc0_trn_usr_d[35]) + ); + FD com_tlm_u_tlm_tx_vc0_trn_usr_d_34_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(trn_td_6087[34]), + .Q(com_tlm_u_tlm_tx_vc0_trn_usr_d[34]) + ); + FD com_tlm_u_tlm_tx_vc0_trn_usr_d_33_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(trn_td_6087[33]), + .Q(com_tlm_u_tlm_tx_vc0_trn_usr_d[33]) + ); + FD com_tlm_u_tlm_tx_vc0_trn_usr_d_32_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(trn_td_6087[32]), + .Q(com_tlm_u_tlm_tx_vc0_trn_usr_d[32]) + ); + FD com_tlm_u_tlm_tx_vc0_trn_usr_d_31_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(trn_td_6087[31]), + .Q(com_tlm_u_tlm_tx_vc0_trn_usr_d[31]) + ); + FD com_tlm_u_tlm_tx_vc0_trn_usr_d_30_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(trn_td_6087[30]), + .Q(com_tlm_u_tlm_tx_vc0_trn_usr_d[30]) + ); + FD com_tlm_u_tlm_tx_vc0_trn_usr_d_59_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(trn_td_6087[59]), + .Q(com_tlm_u_tlm_tx_vc0_trn_usr_d[59]) + ); + FD com_tlm_u_tlm_tx_vc0_trn_usr_d_58_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(trn_td_6087[58]), + .Q(com_tlm_u_tlm_tx_vc0_trn_usr_d[58]) + ); + FD com_tlm_u_tlm_tx_vc0_trn_usr_d_57_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(trn_td_6087[57]), + .Q(com_tlm_u_tlm_tx_vc0_trn_usr_d[57]) + ); + FD com_tlm_u_tlm_tx_vc0_trn_usr_d_56_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(trn_td_6087[56]), + .Q(com_tlm_u_tlm_tx_vc0_trn_usr_d[56]) + ); + FD com_tlm_u_tlm_tx_vc0_trn_usr_d_55_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(trn_td_6087[55]), + .Q(com_tlm_u_tlm_tx_vc0_trn_usr_d[55]) + ); + FD com_tlm_u_tlm_tx_vc0_trn_usr_d_54_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(trn_td_6087[54]), + .Q(com_tlm_u_tlm_tx_vc0_trn_usr_d[54]) + ); + FD com_tlm_u_tlm_tx_vc0_trn_usr_d_53_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(trn_td_6087[53]), + .Q(com_tlm_u_tlm_tx_vc0_trn_usr_d[53]) + ); + FD com_tlm_u_tlm_tx_vc0_trn_usr_d_52_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(trn_td_6087[52]), + .Q(com_tlm_u_tlm_tx_vc0_trn_usr_d[52]) + ); + FD com_tlm_u_tlm_tx_vc0_trn_usr_d_51_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(trn_td_6087[51]), + .Q(com_tlm_u_tlm_tx_vc0_trn_usr_d[51]) + ); + FD com_tlm_u_tlm_tx_vc0_trn_usr_d_50_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(trn_td_6087[50]), + .Q(com_tlm_u_tlm_tx_vc0_trn_usr_d[50]) + ); + FD com_tlm_u_tlm_tx_vc0_trn_usr_d_49_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(trn_td_6087[49]), + .Q(com_tlm_u_tlm_tx_vc0_trn_usr_d[49]) + ); + FD com_tlm_u_tlm_tx_vc0_trn_usr_d_48_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(trn_td_6087[48]), + .Q(com_tlm_u_tlm_tx_vc0_trn_usr_d[48]) + ); + FD com_tlm_u_tlm_tx_vc0_trn_usr_d_47_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(trn_td_6087[47]), + .Q(com_tlm_u_tlm_tx_vc0_trn_usr_d[47]) + ); + FD com_tlm_u_tlm_tx_vc0_trn_usr_d_46_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(trn_td_6087[46]), + .Q(com_tlm_u_tlm_tx_vc0_trn_usr_d[46]) + ); + FD com_tlm_u_tlm_tx_vc0_trn_usr_d_45_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(trn_td_6087[45]), + .Q(com_tlm_u_tlm_tx_vc0_trn_usr_d[45]) + ); + FD com_tlm_u_tlm_tx_vc0_trn_usr_d_63_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(trn_td_6087[63]), + .Q(com_tlm_u_tlm_tx_vc0_trn_usr_d[63]) + ); + FD com_tlm_u_tlm_tx_vc0_trn_usr_d_62_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(trn_td_6087[62]), + .Q(com_tlm_u_tlm_tx_vc0_trn_usr_d[62]) + ); + FD com_tlm_u_tlm_tx_vc0_trn_usr_d_61_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(trn_td_6087[61]), + .Q(com_tlm_u_tlm_tx_vc0_trn_usr_d[61]) + ); + FD com_tlm_u_tlm_tx_vc0_trn_usr_d_60_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(trn_td_6087[60]), + .Q(com_tlm_u_tlm_tx_vc0_trn_usr_d[60]) + ); + FDE com_tlm_u_tlm_tx_vc0_trn_load_value_6_ ( + .CE(com_tlm_u_tlm_tx_vc0_trn_N_55997_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_trn_load_value10), + .Q(com_tlm_u_tlm_tx_vc0_trn_load_value_6__3558) + ); + FDE com_tlm_u_tlm_tx_vc0_trn_load_value_0_ ( + .CE(com_tlm_u_tlm_tx_vc0_trn_N_55997_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_trn_load_value10_i), + .Q(com_tlm_u_tlm_tx_vc0_trn_load_value_0__3559) + ); + INV com_tlm_u_tlm_tx_vc0_trn_usr_abort_i ( + .I(com_tlm_u_tlm_tx_vc0_trn_usr_abort_3553), + .O(com_tlm_u_tlm_tx_vc0_trn_usr_abort_i_3552) + ); + INV com_tlm_u_tlm_tx_vc0_trn_trn_tdst_dsc_i ( + .I(com_tlm_u_tlm_tx_vc0_trn_trn_tdst_dsc), + .O(trn_tdst_dsc_n) + ); + INV com_tlm_u_tlm_tx_vc0_trn_trn_tdst_rdy_i ( + .I(com_tlm_u_tlm_tx_vc0_trn_trn_tdst_rdy), + .O(trn_tdst_rdy_n) + ); + SRL16 com_tlm_u_tlm_tx_vc0_trn_usr_eof_filt_q_I_1 ( + .D(com_tlm_u_tlm_tx_vc0_trn_usr_eof_filt_q_1__3554), + .Q(com_tlm_u_tlm_tx_vc0_trn_usr_eof_filt_q_N_6), + .CLK(NlwRenamedSig_OI_trn_clk), + .A0(com_tlm_u_tlm_tx_vc0_trn_VCC_3557), + .A1(com_tlm_u_tlm_tx_vc0_trn_GND_3555), + .A2(com_tlm_u_tlm_tx_vc0_trn_GND_3555), + .A3(com_tlm_u_tlm_tx_vc0_trn_GND_3555) + ); + MULT_AND com_tlm_u_tlm_tx_vc0_trn_un1_trn_tbuf_av_o_1_cry_0_ma ( + .I0(NlwRenamedSig_OI_trn_tbuf_av[0]), + .I1(com_tlm_u_tlm_tx_vc0_trn_VCC_3557), + .LO(com_tlm_u_tlm_tx_vc0_trn_un1_trn_tbuf_av_o_1_cry_0_ma_3556) + ); + defparam com_tlm_u_tlm_tx_vc0_trn_len_counter_qxu_0_6_.INIT = 8'h1D; + LUT3_L com_tlm_u_tlm_tx_vc0_trn_len_counter_qxu_0_6_ ( + .I0(com_tlm_u_tlm_tx_vc0_trn_len_counter[6]), + .I1(com_tlm_u_tlm_tx_vc0_trn_load_counter_3560), + .I2(com_tlm_u_tlm_tx_vc0_trn_load_value_6__3558), + .LO(com_tlm_u_tlm_tx_vc0_trn_len_counter_qxu[6]) + ); + defparam com_tlm_u_tlm_tx_vc0_trn_len_counter_qxu_0_5_.INIT = 8'h1D; + LUT3_L com_tlm_u_tlm_tx_vc0_trn_len_counter_qxu_0_5_ ( + .I0(com_tlm_u_tlm_tx_vc0_trn_len_counter[5]), + .I1(com_tlm_u_tlm_tx_vc0_trn_load_counter_3560), + .I2(com_tlm_u_tlm_tx_vc0_trn_load_value_0__3559), + .LO(com_tlm_u_tlm_tx_vc0_trn_len_counter_qxu[5]) + ); + defparam com_tlm_u_tlm_tx_vc0_trn_len_counter_qxu_0_4_.INIT = 8'h1D; + LUT3_L com_tlm_u_tlm_tx_vc0_trn_len_counter_qxu_0_4_ ( + .I0(com_tlm_u_tlm_tx_vc0_trn_len_counter[4]), + .I1(com_tlm_u_tlm_tx_vc0_trn_load_counter_3560), + .I2(com_tlm_u_tlm_tx_vc0_trn_load_value_0__3559), + .LO(com_tlm_u_tlm_tx_vc0_trn_len_counter_qxu[4]) + ); + defparam com_tlm_u_tlm_tx_vc0_trn_len_counter_qxu_0_3_.INIT = 8'h1D; + LUT3_L com_tlm_u_tlm_tx_vc0_trn_len_counter_qxu_0_3_ ( + .I0(com_tlm_u_tlm_tx_vc0_trn_len_counter[3]), + .I1(com_tlm_u_tlm_tx_vc0_trn_load_counter_3560), + .I2(com_tlm_u_tlm_tx_vc0_trn_load_value_0__3559), + .LO(com_tlm_u_tlm_tx_vc0_trn_len_counter_qxu[3]) + ); + defparam com_tlm_u_tlm_tx_vc0_trn_len_counter_qxu_0_2_.INIT = 8'h1D; + LUT3_L com_tlm_u_tlm_tx_vc0_trn_len_counter_qxu_0_2_ ( + .I0(com_tlm_u_tlm_tx_vc0_trn_len_counter[2]), + .I1(com_tlm_u_tlm_tx_vc0_trn_load_counter_3560), + .I2(com_tlm_u_tlm_tx_vc0_trn_load_value_0__3559), + .LO(com_tlm_u_tlm_tx_vc0_trn_len_counter_qxu[2]) + ); + defparam com_tlm_u_tlm_tx_vc0_trn_len_counter_qxu_0_1_.INIT = 8'h1D; + LUT3_L com_tlm_u_tlm_tx_vc0_trn_len_counter_qxu_0_1_ ( + .I0(com_tlm_u_tlm_tx_vc0_trn_len_counter[1]), + .I1(com_tlm_u_tlm_tx_vc0_trn_load_counter_3560), + .I2(com_tlm_u_tlm_tx_vc0_trn_load_value_0__3559), + .LO(com_tlm_u_tlm_tx_vc0_trn_len_counter_qxu[1]) + ); + defparam com_tlm_u_tlm_tx_vc0_trn_len_counter_qxu_0_0_.INIT = 8'h1D; + LUT3_L com_tlm_u_tlm_tx_vc0_trn_len_counter_qxu_0_0_ ( + .I0(com_tlm_u_tlm_tx_vc0_trn_len_counter[0]), + .I1(com_tlm_u_tlm_tx_vc0_trn_load_counter_3560), + .I2(com_tlm_u_tlm_tx_vc0_trn_load_value_0__3559), + .LO(com_tlm_u_tlm_tx_vc0_trn_len_counter_qxu[0]) + ); + defparam com_tlm_u_tlm_tx_vc0_trn_N_85836_i.INIT = 16'hAB01; + LUT4_L com_tlm_u_tlm_tx_vc0_trn_N_85836_i ( + .I0(com_tlm_u_tlm_tx_vc0_trn_vld_o_5_i_0_a2_3564), + .I1(com_state[2]), + .I2(com_tlm_u_tlm_tx_vc0_trn_N_85836_i_1_3563), + .I3(com_tlm_u_tlm_tx_vc0_trn_usr_rem_3562), + .LO(com_tlm_u_tlm_tx_vc0_trn_N_85836_i_3561) + ); + GND com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_GND ( + .G(com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_GND_3568) + ); + FDRE com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_sof_q ( + .CE(com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_N_86733_i_3575), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_N_86700_i_3589), + .Q(com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_sof_q_3590), + .R(plm_link_up_i) + ); + FDRE com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_usr_dsc_q ( + .CE(com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_N_86734_i_3574), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_N_56181_i_3584), + .Q(com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_usr_dsc_q_3576), + .R(plm_link_up_i) + ); + MUXCY_L com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_un1_usr_d_i_3_cry_0 ( + .CI(com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_usr_credits14_i_3572), + .DI(com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_GND_3568), + .LO(com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_un1_usr_d_i_3_cry_0_3565), + .S(com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_un1_usr_d_i_3_axb_0_3596) + ); + XORCY com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_un1_usr_d_i_3_s_0 ( + .CI(com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_usr_credits14_i_3572), + .LI(com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_un1_usr_d_i_3_axb_0_3596), + .O(com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_un1_usr_d_i_3_s_0_3583) + ); + MUXCY_L com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_un1_usr_d_i_3_cry_1 ( + .CI(com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_un1_usr_d_i_3_cry_0_3565), + .DI(com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_GND_3568), + .LO(com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_un1_usr_d_i_3_cry_1_3566), + .S(com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_un1_usr_d_i_3_axb_1_3595) + ); + XORCY com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_un1_usr_d_i_3_s_1 ( + .CI(com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_un1_usr_d_i_3_cry_0_3565), + .LI(com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_un1_usr_d_i_3_axb_1_3595), + .O(com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_un1_usr_d_i_3_s_1_3582) + ); + MUXCY_L com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_un1_usr_d_i_3_cry_2 ( + .CI(com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_un1_usr_d_i_3_cry_1_3566), + .DI(com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_GND_3568), + .LO(com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_un1_usr_d_i_3_cry_2_3567), + .S(com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_un1_usr_d_i_3_axb_2_3594) + ); + XORCY com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_un1_usr_d_i_3_s_2 ( + .CI(com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_un1_usr_d_i_3_cry_1_3566), + .LI(com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_un1_usr_d_i_3_axb_2_3594), + .O(com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_un1_usr_d_i_3_s_2_3581) + ); + MUXCY_L com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_un1_usr_d_i_3_cry_3 ( + .CI(com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_un1_usr_d_i_3_cry_2_3567), + .DI(com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_GND_3568), + .LO(com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_un1_usr_d_i_3_cry_3_3569), + .S(com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_un1_usr_d_i_3_axb_3_3593) + ); + XORCY com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_un1_usr_d_i_3_s_3 ( + .CI(com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_un1_usr_d_i_3_cry_2_3567), + .LI(com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_un1_usr_d_i_3_axb_3_3593), + .O(com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_un1_usr_d_i_3_s_3_3580) + ); + MUXCY_L com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_un1_usr_d_i_3_cry_4 ( + .CI(com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_un1_usr_d_i_3_cry_3_3569), + .DI(com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_GND_3568), + .LO(com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_un1_usr_d_i_3_cry_4_3570), + .S(com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_un1_usr_d_i_3_axb_4_3592) + ); + XORCY com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_un1_usr_d_i_3_s_4 ( + .CI(com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_un1_usr_d_i_3_cry_3_3569), + .LI(com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_un1_usr_d_i_3_axb_4_3592), + .O(com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_un1_usr_d_i_3_s_4_3579) + ); + XORCY com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_un1_usr_d_i_3_s_5 ( + .CI(com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_un1_usr_d_i_3_cry_4_3570), + .LI(com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_un1_usr_d_i_3_axb_5_3571), + .O(com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_un1_usr_d_i_3_s_5_3578) + ); + FDR com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_frame_vld_o_1 ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_frame_vld_o_1c_i), + .Q(com_tlm_u_tlm_tx_vc0_frame_vld), + .R(plm_link_up_i) + ); + defparam com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_un1_usr_d_i_3_axb_5.INIT = 4'h2; + LUT1 com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_un1_usr_d_i_3_axb_5 ( + .I0(com_tlm_u_tlm_tx_vc0_trn_usr_d[39]), + .O(com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_un1_usr_d_i_3_axb_5_3571) + ); + defparam com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_usr_cat20_0_a2_0_a2_1_0_.INIT = 4'h1; + LUT2_L com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_usr_cat20_0_a2_0_a2_1_0_ ( + .I0(com_tlm_u_tlm_tx_vc0_trn_usr_d[58]), + .I1(com_tlm_u_tlm_tx_vc0_trn_usr_d[61]), + .LO(com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_usr_cat20_0_a2_0_a2_1[0]) + ); + defparam com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_usr_credits14_i.INIT = 4'hE; + LUT2 com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_usr_credits14_i ( + .I0(com_tlm_u_tlm_tx_vc0_trn_usr_d[32]), + .I1(com_tlm_u_tlm_tx_vc0_trn_usr_d[33]), + .O(com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_usr_credits14_i_3572) + ); + defparam com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_usr_cat19_0_0_1.INIT = 16'h0103; + LUT4_L com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_usr_cat19_0_0_1 ( + .I0(com_tlm_u_tlm_tx_vc0_trn_usr_d[58]), + .I1(com_tlm_u_tlm_tx_vc0_trn_usr_d[59]), + .I2(com_tlm_u_tlm_tx_vc0_trn_usr_d[60]), + .I3(com_tlm_u_tlm_tx_vc0_trn_usr_d[61]), + .LO(com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_usr_cat19_0_0_1_3573) + ); + defparam com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_sof_q_3_i_0_0_a3.INIT = 8'h80; + LUT3 com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_sof_q_3_i_0_0_a3 ( + .I0(com_N_55871_i), + .I1(com_cmmt_trem_n_0_sqmuxa), + .I2(com_cmmt_tdst_rdy), + .O(com_tlm_u_tlm_tx_vc0_trn_cfg_o_2) + ); + defparam com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_usr_cat19_0_0_3.INIT = 16'h3700; + LUT4_L com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_usr_cat19_0_0_3 ( + .I0(com_tlm_u_tlm_tx_vc0_trn_usr_d[56]), + .I1(com_tlm_u_tlm_tx_vc0_trn_usr_d[57]), + .I2(com_tlm_u_tlm_tx_vc0_trn_usr_d[61]), + .I3(com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_usr_cat19_0_0_1_3573), + .LO(com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_usr_cat19_0_0_3_3585) + ); + defparam com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_N_86734_i.INIT = 16'hEFEA; + LUT4 com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_N_86734_i ( + .I0(com_tlm_u_tlm_tx_vc0_trn_usr_dsc_3482), + .I1(com_tlm_u_tlm_tx_vc0_trn_usr_eof_3496), + .I2(com_tlm_u_tlm_tx_vc0_trn_usr_frame_3504), + .I3(com_tlm_u_tlm_tx_vc0_trn_usr_sof_3477), + .O(com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_N_86734_i_3574) + ); + defparam com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_frame_vld_o14_0_i_0_o3_0_1.INIT = 4'h4; + LUT2_L com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_frame_vld_o14_0_i_0_o3_0_1 ( + .I0(com_N_58286), + .I1(com_tlm_u_tlm_tx_vc0_trn_N_61322), + .LO(com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_frame_vld_o14_0_i_0_o3_0_1_3577) + ); + defparam com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_N_86733_i.INIT = 4'hE; + LUT2 com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_N_86733_i ( + .I0(com_tlm_u_tlm_tx_vc0_trn_N_61322), + .I1(com_tlm_u_tlm_tx_vc0_trn_usr_vld_3503), + .O(com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_N_86733_i_3575) + ); + defparam com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_N_86700_i.INIT = 8'hF8; + LUT3 com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_N_86700_i ( + .I0(com_tlm_u_tlm_tx_vc0_trn_usr_sof_filt), + .I1(com_tlm_u_tlm_tx_vc0_trn_usr_vld_3503), + .I2(com_tlm_u_tlm_tx_vc0_trn_cfg_o_2), + .O(com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_N_86700_i_3589) + ); + defparam com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_frame_vld_o_1c.INIT = 16'hCCCE; + LUT4_L com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_frame_vld_o_1c ( + .I0(com_tlm_u_tlm_tx_vc0_trn_N_56472_i), + .I1(com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_frame_vld_o14_0_i_0_o3_0_1_3577), + .I2(com_tlm_u_tlm_tx_vc0_trn_usr_dsc_3482), + .I3(com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_usr_dsc_q_3576), + .LO(com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_frame_vld_o_1c_i) + ); + defparam com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_usr_credits_6_1_a2_0_a2_5_.INIT = 4'h8; + LUT2_L com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_usr_credits_6_1_a2_0_a2_5_ ( + .I0(com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_un1_usr_d_i_3_s_5_3578), + .I1(com_tlm_u_tlm_tx_vc0_trn_usr_d[62]), + .LO(com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_usr_credits_6[5]) + ); + defparam com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_usr_credits_6_1_a2_0_a2_4_.INIT = 4'h8; + LUT2_L com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_usr_credits_6_1_a2_0_a2_4_ ( + .I0(com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_un1_usr_d_i_3_s_4_3579), + .I1(com_tlm_u_tlm_tx_vc0_trn_usr_d[62]), + .LO(com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_usr_credits_6[4]) + ); + defparam com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_usr_credits_6_1_a2_0_a2_3_.INIT = 4'h8; + LUT2_L com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_usr_credits_6_1_a2_0_a2_3_ ( + .I0(com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_un1_usr_d_i_3_s_3_3580), + .I1(com_tlm_u_tlm_tx_vc0_trn_usr_d[62]), + .LO(com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_usr_credits_6[3]) + ); + defparam com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_usr_credits_6_1_a2_0_a2_2_.INIT = 4'h8; + LUT2_L com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_usr_credits_6_1_a2_0_a2_2_ ( + .I0(com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_un1_usr_d_i_3_s_2_3581), + .I1(com_tlm_u_tlm_tx_vc0_trn_usr_d[62]), + .LO(com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_usr_credits_6[2]) + ); + defparam com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_usr_credits_6_1_a2_0_a2_1_.INIT = 4'h8; + LUT2_L com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_usr_credits_6_1_a2_0_a2_1_ ( + .I0(com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_un1_usr_d_i_3_s_1_3582), + .I1(com_tlm_u_tlm_tx_vc0_trn_usr_d[62]), + .LO(com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_usr_credits_6[1]) + ); + defparam com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_usr_credits_6_1_a2_0_a2_0_.INIT = 4'h8; + LUT2_L com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_usr_credits_6_1_a2_0_a2_0_ ( + .I0(com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_un1_usr_d_i_3_s_0_3583), + .I1(com_tlm_u_tlm_tx_vc0_trn_usr_d[62]), + .LO(com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_usr_credits_6[0]) + ); + defparam com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_cat_o_2_0_1_.INIT = 8'hAC; + LUT3_L com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_cat_o_2_0_1_ ( + .I0(com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_cfg_cat[1]), + .I1(com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_usr_cat[1]), + .I2(com_tlm_u_tlm_tx_vc0_trn_cfg), + .LO(com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_cat_o_2[1]) + ); + defparam com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_cat_o_2_0_.INIT = 4'h2; + LUT2_L com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_cat_o_2_0_ ( + .I0(com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_usr_cat[0]), + .I1(com_tlm_u_tlm_tx_vc0_trn_cfg), + .LO(com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_cat_o_2[0]) + ); + defparam com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_N_56181_i.INIT = 8'h47; + LUT3_L com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_N_56181_i ( + .I0(com_tlm_u_tlm_tx_vc0_trn_usr_eof_3496), + .I1(com_tlm_u_tlm_tx_vc0_trn_usr_frame_3504), + .I2(com_tlm_u_tlm_tx_vc0_trn_usr_sof_3477), + .LO(com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_N_56181_i_3584) + ); + defparam com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_credits_o_2_0_a2_0_a2_0_a2_5_.INIT = 4'h8; + LUT2_L com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_credits_o_2_0_a2_0_a2_0_a2_5_ ( + .I0(com_tlm_u_tlm_tx_vc0_trn_usr_vld_3503), + .I1(com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_usr_credits[5]), + .LO(com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_credits_o_2[5]) + ); + defparam com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_credits_o_2_0_a2_0_a2_0_a2_4_.INIT = 4'h8; + LUT2_L com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_credits_o_2_0_a2_0_a2_0_a2_4_ ( + .I0(com_tlm_u_tlm_tx_vc0_trn_usr_vld_3503), + .I1(com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_usr_credits[4]), + .LO(com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_credits_o_2[4]) + ); + defparam com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_credits_o_2_0_a2_0_a2_0_a2_3_.INIT = 4'h8; + LUT2_L com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_credits_o_2_0_a2_0_a2_0_a2_3_ ( + .I0(com_tlm_u_tlm_tx_vc0_trn_usr_vld_3503), + .I1(com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_usr_credits[3]), + .LO(com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_credits_o_2[3]) + ); + defparam com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_credits_o_2_0_a2_0_a2_0_a2_2_.INIT = 4'h8; + LUT2_L com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_credits_o_2_0_a2_0_a2_0_a2_2_ ( + .I0(com_tlm_u_tlm_tx_vc0_trn_usr_vld_3503), + .I1(com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_usr_credits[2]), + .LO(com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_credits_o_2[2]) + ); + defparam com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_credits_o_2_0_a2_0_a2_0_a2_1_.INIT = 4'h8; + LUT2_L com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_credits_o_2_0_a2_0_a2_0_a2_1_ ( + .I0(com_tlm_u_tlm_tx_vc0_trn_usr_vld_3503), + .I1(com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_usr_credits[1]), + .LO(com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_credits_o_2[1]) + ); + defparam com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_credits_o_2_i_m2_i_m3_i_m3_0_0_.INIT = 8'hE4; + LUT3_L com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_credits_o_2_i_m2_i_m3_i_m3_0_0_ ( + .I0(com_tlm_u_tlm_tx_vc0_trn_usr_vld_3503), + .I1(com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_cfg_credits_3586), + .I2(com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_usr_credits[0]), + .LO(com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_credits_o_2_i_m2_i_m3_i_m3_0[0]) + ); + defparam com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_no_payload_o_2_i_m2_i_m3_i_m3_0.INIT = 8'hE4; + LUT3_L com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_no_payload_o_2_i_m2_i_m3_i_m3_0 ( + .I0(com_tlm_u_tlm_tx_vc0_trn_usr_vld_3503), + .I1(com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_cfg_no_payload_3588), + .I2(com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_usr_no_payload_3587), + .LO(com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_no_payload_o_2_i_m2_i_m3_i_m3_0_3591) + ); + defparam com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_usr_cat20_0_a2_0_a2_0_.INIT = 16'h0800; + LUT4_L com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_usr_cat20_0_a2_0_a2_0_ ( + .I0(com_tlm_u_tlm_tx_vc0_trn_usr_d[57]), + .I1(com_tlm_u_tlm_tx_vc0_trn_usr_d[59]), + .I2(com_tlm_u_tlm_tx_vc0_trn_usr_d[60]), + .I3(com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_usr_cat20_0_a2_0_a2_1[0]), + .LO(com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_usr_cat20[0]) + ); + defparam com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_usr_cat19_0_0.INIT = 16'h6700; + LUT4_L com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_usr_cat19_0_0 ( + .I0(com_tlm_u_tlm_tx_vc0_trn_usr_d[57]), + .I1(com_tlm_u_tlm_tx_vc0_trn_usr_d[58]), + .I2(com_tlm_u_tlm_tx_vc0_trn_usr_d[62]), + .I3(com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_usr_cat19_0_0_3_3585), + .LO(com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_N_10827_i) + ); + FDE com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_usr_credits_5_ ( + .CE(com_tlm_u_tlm_tx_vc0_trn_usr_sof_filt), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_usr_credits_6[5]), + .Q(com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_usr_credits[5]) + ); + FDE com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_usr_credits_4_ ( + .CE(com_tlm_u_tlm_tx_vc0_trn_usr_sof_filt), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_usr_credits_6[4]), + .Q(com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_usr_credits[4]) + ); + FDE com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_usr_credits_3_ ( + .CE(com_tlm_u_tlm_tx_vc0_trn_usr_sof_filt), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_usr_credits_6[3]), + .Q(com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_usr_credits[3]) + ); + FDE com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_usr_credits_2_ ( + .CE(com_tlm_u_tlm_tx_vc0_trn_usr_sof_filt), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_usr_credits_6[2]), + .Q(com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_usr_credits[2]) + ); + FDE com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_usr_credits_1_ ( + .CE(com_tlm_u_tlm_tx_vc0_trn_usr_sof_filt), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_usr_credits_6[1]), + .Q(com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_usr_credits[1]) + ); + FDE com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_usr_credits_0_ ( + .CE(com_tlm_u_tlm_tx_vc0_trn_usr_sof_filt), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_usr_credits_6[0]), + .Q(com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_usr_credits[0]) + ); + FD com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_cat_o_1_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_cat_o_2[1]), + .Q(com_tlm_u_tlm_tx_vc0_cat[1]) + ); + FD com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_cat_o_0_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_cat_o_2[0]), + .Q(com_tlm_u_tlm_tx_vc0_cat[0]) + ); + FDE com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_cfg_credits ( + .CE(com_cmmt_trem_n_0_sqmuxa), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_N_43005_i), + .Q(com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_cfg_credits_3586) + ); + FDE com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_usr_no_payload ( + .CE(com_tlm_u_tlm_tx_vc0_trn_usr_sof_filt), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_trn_usr_d_i[62]), + .Q(com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_usr_no_payload_3587) + ); + FDE com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_cfg_no_payload ( + .CE(com_cmmt_trem_n_0_sqmuxa), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_N_43005_i_i), + .Q(com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_cfg_no_payload_3588) + ); + FDE com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_cfg_cat_1_ ( + .CE(com_cmmt_trem_n_0_sqmuxa), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_N_86529_i), + .Q(com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_cfg_cat[1]) + ); + FDE com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_cfg_o ( + .CE(com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_N_86700_i_3589), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_trn_cfg_o_2), + .Q(com_tlm_u_tlm_tx_vc0_trn_cfg) + ); + FDE com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_credits_o_5_ ( + .CE(com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_sof_q_3590), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_credits_o_2[5]), + .Q(com_tlm_u_tlm_tx_vc0_credits[5]) + ); + FDE com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_credits_o_4_ ( + .CE(com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_sof_q_3590), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_credits_o_2[4]), + .Q(com_tlm_u_tlm_tx_vc0_credits[4]) + ); + FDE com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_credits_o_3_ ( + .CE(com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_sof_q_3590), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_credits_o_2[3]), + .Q(com_tlm_u_tlm_tx_vc0_credits[3]) + ); + FDE com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_credits_o_2_ ( + .CE(com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_sof_q_3590), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_credits_o_2[2]), + .Q(com_tlm_u_tlm_tx_vc0_credits[2]) + ); + FDE com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_credits_o_1_ ( + .CE(com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_sof_q_3590), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_credits_o_2[1]), + .Q(com_tlm_u_tlm_tx_vc0_credits[1]) + ); + FDE com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_credits_o_0_ ( + .CE(com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_sof_q_3590), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_credits_o_2_i_m2_i_m3_i_m3_0[0]), + .Q(com_tlm_u_tlm_tx_vc0_credits[0]) + ); + FDE com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_no_payload_o ( + .CE(com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_sof_q_3590), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_no_payload_o_2_i_m2_i_m3_i_m3_0_3591), + .Q(com_tlm_u_tlm_tx_vc0_no_payload) + ); + FDE com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_usr_cat_1_ ( + .CE(com_tlm_u_tlm_tx_vc0_trn_usr_sof_filt), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_usr_cat20[0]), + .Q(com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_usr_cat[1]) + ); + FDE com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_usr_cat_0_ ( + .CE(com_tlm_u_tlm_tx_vc0_trn_usr_sof_filt), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_N_10827_i), + .Q(com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_usr_cat[0]) + ); + defparam com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_un1_usr_d_i_3_axb_4.INIT = 4'h2; + LUT1 com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_un1_usr_d_i_3_axb_4 ( + .I0(com_tlm_u_tlm_tx_vc0_trn_usr_d[38]), + .O(com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_un1_usr_d_i_3_axb_4_3592) + ); + defparam com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_un1_usr_d_i_3_axb_3.INIT = 4'h2; + LUT1 com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_un1_usr_d_i_3_axb_3 ( + .I0(com_tlm_u_tlm_tx_vc0_trn_usr_d[37]), + .O(com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_un1_usr_d_i_3_axb_3_3593) + ); + defparam com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_un1_usr_d_i_3_axb_2.INIT = 4'h2; + LUT1 com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_un1_usr_d_i_3_axb_2 ( + .I0(com_tlm_u_tlm_tx_vc0_trn_usr_d[36]), + .O(com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_un1_usr_d_i_3_axb_2_3594) + ); + defparam com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_un1_usr_d_i_3_axb_1.INIT = 4'h2; + LUT1 com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_un1_usr_d_i_3_axb_1 ( + .I0(com_tlm_u_tlm_tx_vc0_trn_usr_d[35]), + .O(com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_un1_usr_d_i_3_axb_1_3595) + ); + defparam com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_un1_usr_d_i_3_axb_0.INIT = 4'h2; + LUT1 com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_un1_usr_d_i_3_axb_0 ( + .I0(com_tlm_u_tlm_tx_vc0_trn_usr_d[34]), + .O(com_tlm_u_tlm_tx_vc0_trn_wr_ctrl_un1_usr_d_i_3_axb_0_3596) + ); + VCC com_tlm_u_tlm_tx_vc0_token_fifo_VCC ( + .P(com_tlm_u_tlm_tx_vc0_token_fifo_VCC_3597) + ); + FDR com_tlm_u_tlm_tx_vc0_token_fifo_token_index_0_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_token_fifo_un1_token_index_axbxc0_3603), + .Q(com_tlm_u_tlm_tx_vc0_token_fifo_token_index[0]), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_tx_vc0_token_fifo_token_index_1_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_token_fifo_un1_token_index_axbxc1_3602), + .Q(com_tlm_u_tlm_tx_vc0_token_fifo_token_index[1]), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_tx_vc0_token_fifo_token_index_2_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_token_fifo_un1_token_index_axbxc2_3601), + .Q(com_tlm_u_tlm_tx_vc0_token_fifo_token_index[2]), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_tx_vc0_token_fifo_token_index_3_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_token_fifo_un1_token_index_axbxc3_3599), + .Q(com_tlm_u_tlm_tx_vc0_token_fifo_token_index[3]), + .R(plm_link_up_i) + ); + FDRE com_tlm_u_tlm_tx_vc0_token_fifo_tokens_loaded ( + .CE(com_tlm_u_tlm_tx_vc0_token_fifo_tokens_loaded_0_sqmuxa), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_token_fifo_VCC_3597), + .Q(com_tlm_u_tlm_tx_vc0_token_fifo_tokens_loaded_3604), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_tx_vc0_token_fifo_fifo_wen ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_token_fifo_N_52001_i), + .Q(com_tlm_u_tlm_tx_vc0_released_buf), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_tx_vc0_token_fifo_fifo_d_0_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_token_fifo_fifo_d_6_i_m2_i_m3_0[0]), + .Q(com_tlm_u_tlm_tx_vc0_token_fifo_fifo_d[0]), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_tx_vc0_token_fifo_fifo_d_1_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_token_fifo_fifo_d_6_i_m2_i_m3_0[1]), + .Q(com_tlm_u_tlm_tx_vc0_token_fifo_fifo_d[1]), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_tx_vc0_token_fifo_fifo_d_2_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_token_fifo_fifo_d_6_i_m2_i_m3_0[2]), + .Q(com_tlm_u_tlm_tx_vc0_token_fifo_fifo_d[2]), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_tx_vc0_token_fifo_fifo_d_3_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_token_fifo_fifo_d_6_i_o2_i_m3_0[3]), + .Q(com_tlm_u_tlm_tx_vc0_token_fifo_fifo_d[3]), + .R(plm_link_up_i) + ); + defparam com_tlm_u_tlm_tx_vc0_token_fifo_un1_token_index_p4.INIT = 16'h0080; + LUT4_L com_tlm_u_tlm_tx_vc0_token_fifo_un1_token_index_p4 ( + .I0(com_tlm_u_tlm_tx_vc0_token_fifo_token_index[0]), + .I1(com_tlm_u_tlm_tx_vc0_token_fifo_token_index[1]), + .I2(com_tlm_u_tlm_tx_vc0_token_fifo_token_index[2]), + .I3(com_tlm_u_tlm_tx_vc0_token_fifo_tokens_loaded_3604), + .LO(com_tlm_u_tlm_tx_vc0_token_fifo_un1_token_index_p4_3600) + ); + defparam com_tlm_u_tlm_tx_vc0_token_fifo_tokens_loaded_0_sqmuxa_0_a2_3_a2_1.INIT = 4'h8; + LUT2_L com_tlm_u_tlm_tx_vc0_token_fifo_tokens_loaded_0_sqmuxa_0_a2_3_a2_1 ( + .I0(com_tlm_u_tlm_tx_vc0_token_fifo_token_index[0]), + .I1(com_tlm_u_tlm_tx_vc0_token_fifo_token_index[1]), + .LO(com_tlm_u_tlm_tx_vc0_token_fifo_tokens_loaded_0_sqmuxa_0_a2_3_a2_1_3598) + ); + defparam com_tlm_u_tlm_tx_vc0_token_fifo_tokens_loaded_0_sqmuxa_0_a2_3_a2.INIT = 16'h0800; + LUT4 com_tlm_u_tlm_tx_vc0_token_fifo_tokens_loaded_0_sqmuxa_0_a2_3_a2 ( + .I0(com_tlm_u_tlm_tx_vc0_token_fifo_token_index[2]), + .I1(com_tlm_u_tlm_tx_vc0_token_fifo_token_index[3]), + .I2(com_tlm_u_tlm_tx_vc0_token_fifo_tokens_loaded_3604), + .I3(com_tlm_u_tlm_tx_vc0_token_fifo_tokens_loaded_0_sqmuxa_0_a2_3_a2_1_3598), + .O(com_tlm_u_tlm_tx_vc0_token_fifo_tokens_loaded_0_sqmuxa) + ); + defparam com_tlm_u_tlm_tx_vc0_token_fifo_fifo_d_6_i_o2_i_m3_0_3_.INIT = 8'hAC; + LUT3_L com_tlm_u_tlm_tx_vc0_token_fifo_fifo_d_6_i_o2_i_m3_0_3_ ( + .I0(com_tlm_u_tlm_tx_freed_buf[3]), + .I1(com_tlm_u_tlm_tx_vc0_token_fifo_token_index[3]), + .I2(com_tlm_u_tlm_tx_vc0_token_fifo_tokens_loaded_3604), + .LO(com_tlm_u_tlm_tx_vc0_token_fifo_fifo_d_6_i_o2_i_m3_0[3]) + ); + defparam com_tlm_u_tlm_tx_vc0_token_fifo_fifo_d_6_i_m2_i_m3_0_2_.INIT = 8'hAC; + LUT3_L com_tlm_u_tlm_tx_vc0_token_fifo_fifo_d_6_i_m2_i_m3_0_2_ ( + .I0(com_tlm_u_tlm_tx_freed_buf[2]), + .I1(com_tlm_u_tlm_tx_vc0_token_fifo_token_index[2]), + .I2(com_tlm_u_tlm_tx_vc0_token_fifo_tokens_loaded_3604), + .LO(com_tlm_u_tlm_tx_vc0_token_fifo_fifo_d_6_i_m2_i_m3_0[2]) + ); + defparam com_tlm_u_tlm_tx_vc0_token_fifo_fifo_d_6_i_m2_i_m3_0_1_.INIT = 8'hAC; + LUT3_L com_tlm_u_tlm_tx_vc0_token_fifo_fifo_d_6_i_m2_i_m3_0_1_ ( + .I0(com_tlm_u_tlm_tx_freed_buf[1]), + .I1(com_tlm_u_tlm_tx_vc0_token_fifo_token_index[1]), + .I2(com_tlm_u_tlm_tx_vc0_token_fifo_tokens_loaded_3604), + .LO(com_tlm_u_tlm_tx_vc0_token_fifo_fifo_d_6_i_m2_i_m3_0[1]) + ); + defparam com_tlm_u_tlm_tx_vc0_token_fifo_fifo_d_6_i_m2_i_m3_0_0_.INIT = 8'hAC; + LUT3_L com_tlm_u_tlm_tx_vc0_token_fifo_fifo_d_6_i_m2_i_m3_0_0_ ( + .I0(com_tlm_u_tlm_tx_freed_buf[0]), + .I1(com_tlm_u_tlm_tx_vc0_token_fifo_token_index[0]), + .I2(com_tlm_u_tlm_tx_vc0_token_fifo_tokens_loaded_3604), + .LO(com_tlm_u_tlm_tx_vc0_token_fifo_fifo_d_6_i_m2_i_m3_0[0]) + ); + defparam com_tlm_u_tlm_tx_vc0_token_fifo_fifo_wen_6_i_i.INIT = 8'h1F; + LUT3_L com_tlm_u_tlm_tx_vc0_token_fifo_fifo_wen_6_i_i ( + .I0(com_tlm_u_tlm_tx_N_55899_i), + .I1(com_tlm_u_tlm_tx_un1_frees_pending), + .I2(com_tlm_u_tlm_tx_vc0_token_fifo_tokens_loaded_3604), + .LO(com_tlm_u_tlm_tx_vc0_token_fifo_N_52001_i) + ); + defparam com_tlm_u_tlm_tx_vc0_token_fifo_un1_token_index_axbxc3.INIT = 4'h6; + LUT2_L com_tlm_u_tlm_tx_vc0_token_fifo_un1_token_index_axbxc3 ( + .I0(com_tlm_u_tlm_tx_vc0_token_fifo_token_index[3]), + .I1(com_tlm_u_tlm_tx_vc0_token_fifo_un1_token_index_p4_3600), + .LO(com_tlm_u_tlm_tx_vc0_token_fifo_un1_token_index_axbxc3_3599) + ); + defparam com_tlm_u_tlm_tx_vc0_token_fifo_un1_token_index_axbxc2.INIT = 16'hF078; + LUT4_L com_tlm_u_tlm_tx_vc0_token_fifo_un1_token_index_axbxc2 ( + .I0(com_tlm_u_tlm_tx_vc0_token_fifo_token_index[0]), + .I1(com_tlm_u_tlm_tx_vc0_token_fifo_token_index[1]), + .I2(com_tlm_u_tlm_tx_vc0_token_fifo_token_index[2]), + .I3(com_tlm_u_tlm_tx_vc0_token_fifo_tokens_loaded_3604), + .LO(com_tlm_u_tlm_tx_vc0_token_fifo_un1_token_index_axbxc2_3601) + ); + defparam com_tlm_u_tlm_tx_vc0_token_fifo_un1_token_index_axbxc1.INIT = 8'hC6; + LUT3_L com_tlm_u_tlm_tx_vc0_token_fifo_un1_token_index_axbxc1 ( + .I0(com_tlm_u_tlm_tx_vc0_token_fifo_token_index[0]), + .I1(com_tlm_u_tlm_tx_vc0_token_fifo_token_index[1]), + .I2(com_tlm_u_tlm_tx_vc0_token_fifo_tokens_loaded_3604), + .LO(com_tlm_u_tlm_tx_vc0_token_fifo_un1_token_index_axbxc1_3602) + ); + defparam com_tlm_u_tlm_tx_vc0_token_fifo_un1_token_index_axbxc0.INIT = 4'h9; + LUT2_L com_tlm_u_tlm_tx_vc0_token_fifo_un1_token_index_axbxc0 ( + .I0(com_tlm_u_tlm_tx_vc0_token_fifo_token_index[0]), + .I1(com_tlm_u_tlm_tx_vc0_token_fifo_tokens_loaded_3604), + .LO(com_tlm_u_tlm_tx_vc0_token_fifo_un1_token_index_axbxc0_3603) + ); + GND com_tlm_u_tlm_tx_vc0_token_fifo_t_fifo_GND ( + .G(com_tlm_u_tlm_tx_vc0_token_fifo_t_fifo_GND_3605) + ); + SRLC16E com_tlm_u_tlm_tx_vc0_token_fifo_t_fifo_srlrow_0__srlcol_0__srlinst ( + .CE(com_tlm_u_tlm_tx_vc0_released_buf), + .D(com_tlm_u_tlm_tx_vc0_token_fifo_fifo_d[0]), + .Q(com_tlm_u_tlm_tx_vc0_token_fifo_t_fifo_shift_tap[0]), + .CLK(NlwRenamedSig_OI_trn_clk), + .Q15(NLW_com_tlm_u_tlm_tx_vc0_token_fifo_t_fifo_srlrow_0__srlcol_0__srlinst_Q15_UNCONNECTED), + .A0(com_tlm_u_tlm_tx_vc0_token_fifo_t_fifo_raddr_lo[0]), + .A1(com_tlm_u_tlm_tx_vc0_token_fifo_t_fifo_raddr_lo[1]), + .A2(com_tlm_u_tlm_tx_vc0_token_fifo_t_fifo_raddr_lo[2]), + .A3(com_tlm_u_tlm_tx_vc0_token_fifo_t_fifo_raddr_lo[3]) + ); + SRLC16E com_tlm_u_tlm_tx_vc0_token_fifo_t_fifo_srlrow_0__srlcol_3__srlinst ( + .CE(com_tlm_u_tlm_tx_vc0_released_buf), + .D(com_tlm_u_tlm_tx_vc0_token_fifo_fifo_d[3]), + .Q(com_tlm_u_tlm_tx_vc0_token_fifo_t_fifo_shift_tap[3]), + .CLK(NlwRenamedSig_OI_trn_clk), + .Q15(NLW_com_tlm_u_tlm_tx_vc0_token_fifo_t_fifo_srlrow_0__srlcol_3__srlinst_Q15_UNCONNECTED), + .A0(com_tlm_u_tlm_tx_vc0_token_fifo_t_fifo_raddr_lo[0]), + .A1(com_tlm_u_tlm_tx_vc0_token_fifo_t_fifo_raddr_lo[1]), + .A2(com_tlm_u_tlm_tx_vc0_token_fifo_t_fifo_raddr_lo[2]), + .A3(com_tlm_u_tlm_tx_vc0_token_fifo_t_fifo_raddr_lo[3]) + ); + SRLC16E com_tlm_u_tlm_tx_vc0_token_fifo_t_fifo_srlrow_0__srlcol_2__srlinst ( + .CE(com_tlm_u_tlm_tx_vc0_released_buf), + .D(com_tlm_u_tlm_tx_vc0_token_fifo_fifo_d[2]), + .Q(com_tlm_u_tlm_tx_vc0_token_fifo_t_fifo_shift_tap[2]), + .CLK(NlwRenamedSig_OI_trn_clk), + .Q15(NLW_com_tlm_u_tlm_tx_vc0_token_fifo_t_fifo_srlrow_0__srlcol_2__srlinst_Q15_UNCONNECTED), + .A0(com_tlm_u_tlm_tx_vc0_token_fifo_t_fifo_raddr_lo[0]), + .A1(com_tlm_u_tlm_tx_vc0_token_fifo_t_fifo_raddr_lo[1]), + .A2(com_tlm_u_tlm_tx_vc0_token_fifo_t_fifo_raddr_lo[2]), + .A3(com_tlm_u_tlm_tx_vc0_token_fifo_t_fifo_raddr_lo[3]) + ); + SRLC16E com_tlm_u_tlm_tx_vc0_token_fifo_t_fifo_srlrow_0__srlcol_1__srlinst ( + .CE(com_tlm_u_tlm_tx_vc0_released_buf), + .D(com_tlm_u_tlm_tx_vc0_token_fifo_fifo_d[1]), + .Q(com_tlm_u_tlm_tx_vc0_token_fifo_t_fifo_shift_tap[1]), + .CLK(NlwRenamedSig_OI_trn_clk), + .Q15(NLW_com_tlm_u_tlm_tx_vc0_token_fifo_t_fifo_srlrow_0__srlcol_1__srlinst_Q15_UNCONNECTED), + .A0(com_tlm_u_tlm_tx_vc0_token_fifo_t_fifo_raddr_lo[0]), + .A1(com_tlm_u_tlm_tx_vc0_token_fifo_t_fifo_raddr_lo[1]), + .A2(com_tlm_u_tlm_tx_vc0_token_fifo_t_fifo_raddr_lo[2]), + .A3(com_tlm_u_tlm_tx_vc0_token_fifo_t_fifo_raddr_lo[3]) + ); + FDS com_tlm_u_tlm_tx_vc0_token_fifo_t_fifo_raddr_lo_0_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_token_fifo_t_fifo_un1_raddr_lo_1_axb_0_3611), + .Q(com_tlm_u_tlm_tx_vc0_token_fifo_t_fifo_raddr_lo[0]), + .S(plm_link_up_i) + ); + FDS com_tlm_u_tlm_tx_vc0_token_fifo_t_fifo_raddr_lo_1_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_token_fifo_t_fifo_un1_raddr_lo_1_s_1_1), + .Q(com_tlm_u_tlm_tx_vc0_token_fifo_t_fifo_raddr_lo[1]), + .S(plm_link_up_i) + ); + FDS com_tlm_u_tlm_tx_vc0_token_fifo_t_fifo_raddr_lo_2_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_token_fifo_t_fifo_un1_raddr_lo_1_s_2_1), + .Q(com_tlm_u_tlm_tx_vc0_token_fifo_t_fifo_raddr_lo[2]), + .S(plm_link_up_i) + ); + FDS com_tlm_u_tlm_tx_vc0_token_fifo_t_fifo_raddr_lo_3_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_token_fifo_t_fifo_un1_raddr_lo_1_s_3_1), + .Q(com_tlm_u_tlm_tx_vc0_token_fifo_t_fifo_raddr_lo[3]), + .S(plm_link_up_i) + ); + FDRE com_tlm_u_tlm_tx_vc0_token_fifo_t_fifo_nxt_vld_o ( + .CE(com_tlm_u_tlm_tx_vc0_token_fifo_t_fifo_N_86417_i_3609), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_released_buf), + .Q(com_tlm_u_tlm_tx_vc0_token_fifo_t_fifo_nxt_vld_o_3615), + .R(plm_link_up_i) + ); + FDRE com_tlm_u_tlm_tx_vc0_token_fifo_t_fifo_vld_o ( + .CE(com_tlm_u_tlm_tx_vc0_token_fifo_t_fifo_N_56062_i_i_3617), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_token_fifo_t_fifo_nxt_vld_o_3615), + .Q(com_tlm_u_tlm_tx_vc0_token_fifo_t_fifo_vld_o_3616), + .R(plm_link_up_i) + ); + MUXCY_L com_tlm_u_tlm_tx_vc0_token_fifo_t_fifo_un1_raddr_lo_1_cry_0 ( + .CI(com_tlm_u_tlm_tx_vc0_token_fifo_t_fifo_GND_3605), + .DI(com_tlm_u_tlm_tx_vc0_token_fifo_t_fifo_raddr_lo[0]), + .LO(com_tlm_u_tlm_tx_vc0_token_fifo_t_fifo_un1_raddr_lo_1_cry_0_3606), + .S(com_tlm_u_tlm_tx_vc0_token_fifo_t_fifo_un1_raddr_lo_1_axb_0_3611) + ); + MUXCY_L com_tlm_u_tlm_tx_vc0_token_fifo_t_fifo_un1_raddr_lo_1_cry_1 ( + .CI(com_tlm_u_tlm_tx_vc0_token_fifo_t_fifo_un1_raddr_lo_1_cry_0_3606), + .DI(com_tlm_u_tlm_tx_vc0_token_fifo_t_fifo_raddr_lo[1]), + .LO(com_tlm_u_tlm_tx_vc0_token_fifo_t_fifo_un1_raddr_lo_1_cry_1_3607), + .S(com_tlm_u_tlm_tx_vc0_token_fifo_t_fifo_un1_raddr_lo_1_axb_1_3614) + ); + XORCY com_tlm_u_tlm_tx_vc0_token_fifo_t_fifo_un1_raddr_lo_1_s_1 ( + .CI(com_tlm_u_tlm_tx_vc0_token_fifo_t_fifo_un1_raddr_lo_1_cry_0_3606), + .LI(com_tlm_u_tlm_tx_vc0_token_fifo_t_fifo_un1_raddr_lo_1_axb_1_3614), + .O(com_tlm_u_tlm_tx_vc0_token_fifo_t_fifo_un1_raddr_lo_1_s_1_1) + ); + MUXCY_L com_tlm_u_tlm_tx_vc0_token_fifo_t_fifo_un1_raddr_lo_1_cry_2 ( + .CI(com_tlm_u_tlm_tx_vc0_token_fifo_t_fifo_un1_raddr_lo_1_cry_1_3607), + .DI(com_tlm_u_tlm_tx_vc0_token_fifo_t_fifo_raddr_lo[2]), + .LO(com_tlm_u_tlm_tx_vc0_token_fifo_t_fifo_un1_raddr_lo_1_cry_2_3608), + .S(com_tlm_u_tlm_tx_vc0_token_fifo_t_fifo_un1_raddr_lo_1_axb_2_3613) + ); + XORCY com_tlm_u_tlm_tx_vc0_token_fifo_t_fifo_un1_raddr_lo_1_s_2 ( + .CI(com_tlm_u_tlm_tx_vc0_token_fifo_t_fifo_un1_raddr_lo_1_cry_1_3607), + .LI(com_tlm_u_tlm_tx_vc0_token_fifo_t_fifo_un1_raddr_lo_1_axb_2_3613), + .O(com_tlm_u_tlm_tx_vc0_token_fifo_t_fifo_un1_raddr_lo_1_s_2_1) + ); + XORCY com_tlm_u_tlm_tx_vc0_token_fifo_t_fifo_un1_raddr_lo_1_s_3 ( + .CI(com_tlm_u_tlm_tx_vc0_token_fifo_t_fifo_un1_raddr_lo_1_cry_2_3608), + .LI(com_tlm_u_tlm_tx_vc0_token_fifo_t_fifo_un1_raddr_lo_1_axb_3_3612), + .O(com_tlm_u_tlm_tx_vc0_token_fifo_t_fifo_un1_raddr_lo_1_s_3_1) + ); + defparam com_tlm_u_tlm_tx_vc0_token_fifo_t_fifo_raddr_en_0_0_0_o3.INIT = 4'h4; + LUT2 com_tlm_u_tlm_tx_vc0_token_fifo_t_fifo_raddr_en_0_0_0_o3 ( + .I0(com_tlm_u_tlm_tx_vc0_frame_vld), + .I1(com_tlm_u_tlm_tx_vc0_token_fifo_t_fifo_vld_o_3616), + .O(com_tlm_u_tlm_tx_vc0_token_fifo_t_fifo_N_56062_i) + ); + defparam com_tlm_u_tlm_tx_vc0_token_fifo_t_fifo_un1_bkp_i_1_i_0_0_0_a2_2.INIT = 16'h0001; + LUT4 com_tlm_u_tlm_tx_vc0_token_fifo_t_fifo_un1_bkp_i_1_i_0_0_0_a2_2 ( + .I0(com_tlm_u_tlm_tx_vc0_token_fifo_t_fifo_raddr_lo[0]), + .I1(com_tlm_u_tlm_tx_vc0_token_fifo_t_fifo_raddr_lo[1]), + .I2(com_tlm_u_tlm_tx_vc0_token_fifo_t_fifo_raddr_lo[2]), + .I3(com_tlm_u_tlm_tx_vc0_token_fifo_t_fifo_raddr_lo[3]), + .O(com_tlm_u_tlm_tx_vc0_token_fifo_t_fifo_un1_bkp_i_1_i_0_0_0_a2_2_3610) + ); + defparam com_tlm_u_tlm_tx_vc0_token_fifo_t_fifo_N_86417_i.INIT = 8'hDC; + LUT3 com_tlm_u_tlm_tx_vc0_token_fifo_t_fifo_N_86417_i ( + .I0(com_tlm_u_tlm_tx_vc0_token_fifo_t_fifo_N_56062_i), + .I1(com_tlm_u_tlm_tx_vc0_released_buf), + .I2(com_tlm_u_tlm_tx_vc0_token_fifo_t_fifo_un1_bkp_i_1_i_0_0_0_a2_2_3610), + .O(com_tlm_u_tlm_tx_vc0_token_fifo_t_fifo_N_86417_i_3609) + ); + defparam com_tlm_u_tlm_tx_vc0_token_fifo_t_fifo_un1_raddr_lo_1_axb_0.INIT = 16'h693C; + LUT4 com_tlm_u_tlm_tx_vc0_token_fifo_t_fifo_un1_raddr_lo_1_axb_0 ( + .I0(com_tlm_u_tlm_tx_vc0_token_fifo_t_fifo_N_56062_i), + .I1(com_tlm_u_tlm_tx_vc0_released_buf), + .I2(com_tlm_u_tlm_tx_vc0_token_fifo_t_fifo_raddr_lo[0]), + .I3(com_tlm_u_tlm_tx_vc0_token_fifo_t_fifo_nxt_vld_o_3615), + .O(com_tlm_u_tlm_tx_vc0_token_fifo_t_fifo_un1_raddr_lo_1_axb_0_3611) + ); + defparam com_tlm_u_tlm_tx_vc0_token_fifo_t_fifo_un1_raddr_lo_1_axb_3.INIT = 16'hE1F0; + LUT4_L com_tlm_u_tlm_tx_vc0_token_fifo_t_fifo_un1_raddr_lo_1_axb_3 ( + .I0(com_tlm_u_tlm_tx_vc0_token_fifo_t_fifo_N_56062_i), + .I1(com_tlm_u_tlm_tx_vc0_released_buf), + .I2(com_tlm_u_tlm_tx_vc0_token_fifo_t_fifo_raddr_lo[3]), + .I3(com_tlm_u_tlm_tx_vc0_token_fifo_t_fifo_nxt_vld_o_3615), + .LO(com_tlm_u_tlm_tx_vc0_token_fifo_t_fifo_un1_raddr_lo_1_axb_3_3612) + ); + defparam com_tlm_u_tlm_tx_vc0_token_fifo_t_fifo_un1_raddr_lo_1_axb_2.INIT = 16'hE1F0; + LUT4_L com_tlm_u_tlm_tx_vc0_token_fifo_t_fifo_un1_raddr_lo_1_axb_2 ( + .I0(com_tlm_u_tlm_tx_vc0_token_fifo_t_fifo_N_56062_i), + .I1(com_tlm_u_tlm_tx_vc0_released_buf), + .I2(com_tlm_u_tlm_tx_vc0_token_fifo_t_fifo_raddr_lo[2]), + .I3(com_tlm_u_tlm_tx_vc0_token_fifo_t_fifo_nxt_vld_o_3615), + .LO(com_tlm_u_tlm_tx_vc0_token_fifo_t_fifo_un1_raddr_lo_1_axb_2_3613) + ); + defparam com_tlm_u_tlm_tx_vc0_token_fifo_t_fifo_un1_raddr_lo_1_axb_1.INIT = 16'hE1F0; + LUT4_L com_tlm_u_tlm_tx_vc0_token_fifo_t_fifo_un1_raddr_lo_1_axb_1 ( + .I0(com_tlm_u_tlm_tx_vc0_token_fifo_t_fifo_N_56062_i), + .I1(com_tlm_u_tlm_tx_vc0_released_buf), + .I2(com_tlm_u_tlm_tx_vc0_token_fifo_t_fifo_raddr_lo[1]), + .I3(com_tlm_u_tlm_tx_vc0_token_fifo_t_fifo_nxt_vld_o_3615), + .LO(com_tlm_u_tlm_tx_vc0_token_fifo_t_fifo_un1_raddr_lo_1_axb_1_3614) + ); + defparam com_tlm_u_tlm_tx_vc0_token_fifo_t_fifo_N_56062_i_i.INIT = 4'hD; + LUT2 com_tlm_u_tlm_tx_vc0_token_fifo_t_fifo_N_56062_i_i ( + .I0(com_tlm_u_tlm_tx_vc0_token_fifo_t_fifo_vld_o_3616), + .I1(com_tlm_u_tlm_tx_vc0_frame_vld), + .O(com_tlm_u_tlm_tx_vc0_token_fifo_t_fifo_N_56062_i_i_3617) + ); + FDE com_tlm_u_tlm_tx_vc0_token_fifo_t_fifo_d_o_3_ ( + .CE(com_tlm_u_tlm_tx_vc0_token_fifo_t_fifo_N_56062_i_i_3617), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_token_fifo_t_fifo_shift_tap[3]), + .Q(com_tlm_u_tlm_tx_vc0_tkn_buf_num[3]) + ); + FDE com_tlm_u_tlm_tx_vc0_token_fifo_t_fifo_d_o_2_ ( + .CE(com_tlm_u_tlm_tx_vc0_token_fifo_t_fifo_N_56062_i_i_3617), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_token_fifo_t_fifo_shift_tap[2]), + .Q(com_tlm_u_tlm_tx_vc0_tkn_buf_num[2]) + ); + FDE com_tlm_u_tlm_tx_vc0_token_fifo_t_fifo_d_o_1_ ( + .CE(com_tlm_u_tlm_tx_vc0_token_fifo_t_fifo_N_56062_i_i_3617), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_token_fifo_t_fifo_shift_tap[1]), + .Q(com_tlm_u_tlm_tx_vc0_tkn_buf_num[1]) + ); + FDE com_tlm_u_tlm_tx_vc0_token_fifo_t_fifo_d_o_0_ ( + .CE(com_tlm_u_tlm_tx_vc0_token_fifo_t_fifo_N_56062_i_i_3617), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_token_fifo_t_fifo_shift_tap[0]), + .Q(com_tlm_u_tlm_tx_vc0_tkn_buf_num[0]) + ); + VCC com_tlm_u_tlm_tx_vc0_frm_seq_VCC ( + .P(com_tlm_u_tlm_tx_vc0_frm_seq_VCC_3669) + ); + GND com_tlm_u_tlm_tx_vc0_frm_seq_GND ( + .G(com_tlm_u_tlm_tx_vc0_frm_seq_GND_3622) + ); + FDR com_tlm_u_tlm_tx_vc0_frm_seq_oq_ren ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_N_9928_i), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_oq_ren_3618), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_tx_vc0_frm_seq_consumed_nph ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_N_9929_i), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_consumed_nph_3619), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_tx_vc0_frm_seq_bq_wen ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_N_16924_i), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_bq_wen_3676), + .R(plm_link_up_i) + ); + FDS com_tlm_u_tlm_tx_vc0_frm_seq_queue_state_0_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_N_52360_i), + .Q(com_tlm_u_tlm_tx_queue_state[0]), + .S(plm_link_up_i) + ); + FDR com_tlm_u_tlm_tx_vc0_frm_seq_queue_state_1_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_N_86359_i_3688), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_queue_state[1]), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_tx_vc0_frm_seq_queue_state_2_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_N_85898_i_3687), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_queue_state[2]), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_tx_vc0_frm_seq_queue_state_3_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_nxt_queue_state_1_sqmuxa_1), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_queue_state[3]), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_tx_vc0_frm_seq_consumed_ph ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_N_16890_i), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_consumed_ph_3620), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_tx_vc0_frm_seq_consumed_cplh ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_N_16888_i), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_consumed_cplh_3621), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_tx_vc0_frm_seq_sq_wen ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_N_57072_i), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_sq_wen_3693), + .R(plm_link_up_i) + ); + FDS com_tlm_u_tlm_tx_vc0_frm_seq_seq_state_0_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_N_20410_i), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_seq_state[0]), + .S(plm_link_up_i) + ); + FDR com_tlm_u_tlm_tx_vc0_frm_seq_seq_state_1_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_nxt_seq_state_0_sqmuxa_2), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_seq_state[1]), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_tx_vc0_frm_seq_seq_state_2_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_nxt_seq_state_0_sqmuxa_1), + .Q(com_tlm_u_tlm_tx_am_retry_dst_rdy), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_tx_vc0_frm_seq_seq_state_3_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_N_85820_i_3686), + .Q(com_tlm_u_tlm_tx_vc0_start_src_rdy), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_tx_vc0_frm_seq_header_vld_oq ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_N_16926_i), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_header_vld_oq_3678), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_tx_vc0_frm_seq_bnpd_diff_11_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_un4_bnpd_diff_s_11_3657), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_bnpd_diff[11]), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_tx_vc0_frm_seq_pd_diff_11_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_un4_pd_diff_s_11_3670), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_pd_diff[11]), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_tx_vc0_frm_seq_npd_diff_11_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_un4_npd_diff_s_11_3633), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_npd_diff[11]), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_tx_vc0_frm_seq_cpld_diff_11_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_un4_cpld_diff_s_11_3645), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_cpld_diff[11]), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_tx_vc0_frm_seq_nonposted_vld_oq ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_nonposted_vld_oq_3), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_nonposted_vld_oq_3691), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_tx_vc0_frm_seq_header_vld_bq ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_header_vld_bq_3), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_header_vld_bq_3672), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_tx_vc0_frm_seq_last_buf_num_match ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_last_buf_num_match_3), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_last_buf_num_match_3689), + .R(plm_link_up_i) + ); + FDRSE com_tlm_u_tlm_tx_vc0_frm_seq_bq_holdoff ( + .CE(com_tlm_u_tlm_tx_vc0_frm_seq_bq_vld), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_GND_3622), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_bq_holdoff_3674), + .R(plm_link_up_i), + .S(com_tlm_u_tlm_tx_vc0_frm_seq_bq_holdoff13) + ); + FDRE com_tlm_u_tlm_tx_vc0_frm_seq_start_retry_o ( + .CE(com_tlm_u_tlm_tx_vc0_frm_seq_N_56491_i_i_3692), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_am_retry_dst_rdy), + .Q(com_tlm_u_tlm_tx_vc0_start_retry), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_tx_vc0_frm_seq_bq_no_payload_qq ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_bq_q[10]), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_bq_no_payload_qq_3673), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_tx_vc0_frm_seq_oq_no_payload_qq ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_bq_d[10]), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_oq_no_payload_qq_3677), + .R(plm_link_up_i) + ); + FDRE com_tlm_u_tlm_tx_vc0_frm_seq_last_buf_num_0_ ( + .CE(com_tlm_u_tlm_tx_vc0_frm_seq_seq_state[1]), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_sq_q[0]), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_last_buf_num[0]), + .R(plm_link_up_i) + ); + FDRE com_tlm_u_tlm_tx_vc0_frm_seq_last_buf_num_1_ ( + .CE(com_tlm_u_tlm_tx_vc0_frm_seq_seq_state[1]), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_sq_q[1]), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_last_buf_num[1]), + .R(plm_link_up_i) + ); + FDRE com_tlm_u_tlm_tx_vc0_frm_seq_last_buf_num_2_ ( + .CE(com_tlm_u_tlm_tx_vc0_frm_seq_seq_state[1]), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_sq_q[2]), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_last_buf_num[2]), + .R(plm_link_up_i) + ); + FDRE com_tlm_u_tlm_tx_vc0_frm_seq_last_buf_num_3_ ( + .CE(com_tlm_u_tlm_tx_vc0_frm_seq_seq_state[1]), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_sq_q[3]), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_last_buf_num[3]), + .R(plm_link_up_i) + ); + MUXCY_L com_tlm_u_tlm_tx_vc0_frm_seq_un4_npd_diff_cry_0 ( + .CI(com_tlm_u_tlm_tx_vc0_frm_seq_VCC_3669), + .DI(com_tlm_u_tlm_tx_vc0_frm_seq_npd_av[0]), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_un4_npd_diff_cry_0_3623), + .S(com_tlm_u_tlm_tx_vc0_frm_seq_un4_npd_diff_axb_0_3722) + ); + MUXCY_L com_tlm_u_tlm_tx_vc0_frm_seq_un4_npd_diff_cry_1 ( + .CI(com_tlm_u_tlm_tx_vc0_frm_seq_un4_npd_diff_cry_0_3623), + .DI(com_tlm_u_tlm_tx_vc0_frm_seq_npd_av[1]), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_un4_npd_diff_cry_1_3624), + .S(com_tlm_u_tlm_tx_vc0_frm_seq_un4_npd_diff_axb_1_3721) + ); + MUXCY_L com_tlm_u_tlm_tx_vc0_frm_seq_un4_npd_diff_cry_2 ( + .CI(com_tlm_u_tlm_tx_vc0_frm_seq_un4_npd_diff_cry_1_3624), + .DI(com_tlm_u_tlm_tx_vc0_frm_seq_npd_av[2]), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_un4_npd_diff_cry_2_3625), + .S(com_tlm_u_tlm_tx_vc0_frm_seq_un4_npd_diff_axb_2_3720) + ); + MUXCY_L com_tlm_u_tlm_tx_vc0_frm_seq_un4_npd_diff_cry_3 ( + .CI(com_tlm_u_tlm_tx_vc0_frm_seq_un4_npd_diff_cry_2_3625), + .DI(com_tlm_u_tlm_tx_vc0_frm_seq_npd_av[3]), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_un4_npd_diff_cry_3_3626), + .S(com_tlm_u_tlm_tx_vc0_frm_seq_un4_npd_diff_axb_3_3719) + ); + MUXCY_L com_tlm_u_tlm_tx_vc0_frm_seq_un4_npd_diff_cry_4 ( + .CI(com_tlm_u_tlm_tx_vc0_frm_seq_un4_npd_diff_cry_3_3626), + .DI(com_tlm_u_tlm_tx_vc0_frm_seq_npd_av[4]), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_un4_npd_diff_cry_4_3627), + .S(com_tlm_u_tlm_tx_vc0_frm_seq_un4_npd_diff_axb_4_3718) + ); + MUXCY_L com_tlm_u_tlm_tx_vc0_frm_seq_un4_npd_diff_cry_5 ( + .CI(com_tlm_u_tlm_tx_vc0_frm_seq_un4_npd_diff_cry_4_3627), + .DI(com_tlm_u_tlm_tx_vc0_frm_seq_npd_av[5]), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_un4_npd_diff_cry_5_3628), + .S(com_tlm_u_tlm_tx_vc0_frm_seq_un4_npd_diff_axb_5_3717) + ); + MUXCY_L com_tlm_u_tlm_tx_vc0_frm_seq_un4_npd_diff_cry_6 ( + .CI(com_tlm_u_tlm_tx_vc0_frm_seq_un4_npd_diff_cry_5_3628), + .DI(com_tlm_u_tlm_tx_vc0_frm_seq_VCC_3669), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_un4_npd_diff_cry_6_3629), + .S(com_tlm_u_tlm_tx_vc0_frm_seq_npd_av_i[6]) + ); + MUXCY_L com_tlm_u_tlm_tx_vc0_frm_seq_un4_npd_diff_cry_7 ( + .CI(com_tlm_u_tlm_tx_vc0_frm_seq_un4_npd_diff_cry_6_3629), + .DI(com_tlm_u_tlm_tx_vc0_frm_seq_VCC_3669), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_un4_npd_diff_cry_7_3630), + .S(com_tlm_u_tlm_tx_vc0_frm_seq_npd_av_i[7]) + ); + MUXCY_L com_tlm_u_tlm_tx_vc0_frm_seq_un4_npd_diff_cry_8 ( + .CI(com_tlm_u_tlm_tx_vc0_frm_seq_un4_npd_diff_cry_7_3630), + .DI(com_tlm_u_tlm_tx_vc0_frm_seq_VCC_3669), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_un4_npd_diff_cry_8_3631), + .S(com_tlm_u_tlm_tx_vc0_frm_seq_npd_av_i[8]) + ); + MUXCY_L com_tlm_u_tlm_tx_vc0_frm_seq_un4_npd_diff_cry_9 ( + .CI(com_tlm_u_tlm_tx_vc0_frm_seq_un4_npd_diff_cry_8_3631), + .DI(com_tlm_u_tlm_tx_vc0_frm_seq_VCC_3669), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_un4_npd_diff_cry_9_3632), + .S(com_tlm_u_tlm_tx_vc0_frm_seq_npd_av_i[9]) + ); + MUXCY_L com_tlm_u_tlm_tx_vc0_frm_seq_un4_npd_diff_cry_10 ( + .CI(com_tlm_u_tlm_tx_vc0_frm_seq_un4_npd_diff_cry_9_3632), + .DI(com_tlm_u_tlm_tx_vc0_frm_seq_VCC_3669), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_un4_npd_diff_cry_10_3634), + .S(com_tlm_u_tlm_tx_vc0_frm_seq_npd_av_i[10]) + ); + XORCY com_tlm_u_tlm_tx_vc0_frm_seq_un4_npd_diff_s_11 ( + .CI(com_tlm_u_tlm_tx_vc0_frm_seq_un4_npd_diff_cry_10_3634), + .LI(com_tlm_u_tlm_tx_vc0_frm_seq_un4_npd_diff_s_11_sf_3682), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_un4_npd_diff_s_11_3633) + ); + MUXCY_L com_tlm_u_tlm_tx_vc0_frm_seq_un4_cpld_diff_cry_0 ( + .CI(com_tlm_u_tlm_tx_vc0_frm_seq_VCC_3669), + .DI(com_tlm_u_tlm_tx_vc0_frm_seq_cpld_av_0_), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_un4_cpld_diff_cry_0_3635), + .S(com_tlm_u_tlm_tx_vc0_frm_seq_un4_cpld_diff_axb_0_3716) + ); + MUXCY_L com_tlm_u_tlm_tx_vc0_frm_seq_un4_cpld_diff_cry_1 ( + .CI(com_tlm_u_tlm_tx_vc0_frm_seq_un4_cpld_diff_cry_0_3635), + .DI(com_tlm_u_tlm_tx_vc0_frm_seq_cpld_av_1_), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_un4_cpld_diff_cry_1_3636), + .S(com_tlm_u_tlm_tx_vc0_frm_seq_un4_cpld_diff_axb_1_3715) + ); + MUXCY_L com_tlm_u_tlm_tx_vc0_frm_seq_un4_cpld_diff_cry_2 ( + .CI(com_tlm_u_tlm_tx_vc0_frm_seq_un4_cpld_diff_cry_1_3636), + .DI(com_tlm_u_tlm_tx_vc0_frm_seq_cpld_av_2_), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_un4_cpld_diff_cry_2_3637), + .S(com_tlm_u_tlm_tx_vc0_frm_seq_un4_cpld_diff_axb_2_3714) + ); + MUXCY_L com_tlm_u_tlm_tx_vc0_frm_seq_un4_cpld_diff_cry_3 ( + .CI(com_tlm_u_tlm_tx_vc0_frm_seq_un4_cpld_diff_cry_2_3637), + .DI(com_tlm_u_tlm_tx_vc0_frm_seq_cpld_av_3_), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_un4_cpld_diff_cry_3_3638), + .S(com_tlm_u_tlm_tx_vc0_frm_seq_un4_cpld_diff_axb_3_3713) + ); + MUXCY_L com_tlm_u_tlm_tx_vc0_frm_seq_un4_cpld_diff_cry_4 ( + .CI(com_tlm_u_tlm_tx_vc0_frm_seq_un4_cpld_diff_cry_3_3638), + .DI(com_tlm_u_tlm_tx_vc0_frm_seq_cpld_av_4_), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_un4_cpld_diff_cry_4_3639), + .S(com_tlm_u_tlm_tx_vc0_frm_seq_un4_cpld_diff_axb_4_3712) + ); + MUXCY_L com_tlm_u_tlm_tx_vc0_frm_seq_un4_cpld_diff_cry_5 ( + .CI(com_tlm_u_tlm_tx_vc0_frm_seq_un4_cpld_diff_cry_4_3639), + .DI(com_tlm_u_tlm_tx_vc0_frm_seq_cpld_av_5_), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_un4_cpld_diff_cry_5_3640), + .S(com_tlm_u_tlm_tx_vc0_frm_seq_un4_cpld_diff_axb_5_3711) + ); + MUXCY_L com_tlm_u_tlm_tx_vc0_frm_seq_un4_cpld_diff_cry_6 ( + .CI(com_tlm_u_tlm_tx_vc0_frm_seq_un4_cpld_diff_cry_5_3640), + .DI(com_tlm_u_tlm_tx_vc0_frm_seq_VCC_3669), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_un4_cpld_diff_cry_6_3641), + .S(com_tlm_u_tlm_tx_vc0_frm_seq_cpld_av_i[6]) + ); + MUXCY_L com_tlm_u_tlm_tx_vc0_frm_seq_un4_cpld_diff_cry_7 ( + .CI(com_tlm_u_tlm_tx_vc0_frm_seq_un4_cpld_diff_cry_6_3641), + .DI(com_tlm_u_tlm_tx_vc0_frm_seq_VCC_3669), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_un4_cpld_diff_cry_7_3642), + .S(com_tlm_u_tlm_tx_vc0_frm_seq_cpld_av_i[7]) + ); + MUXCY_L com_tlm_u_tlm_tx_vc0_frm_seq_un4_cpld_diff_cry_8 ( + .CI(com_tlm_u_tlm_tx_vc0_frm_seq_un4_cpld_diff_cry_7_3642), + .DI(com_tlm_u_tlm_tx_vc0_frm_seq_VCC_3669), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_un4_cpld_diff_cry_8_3643), + .S(com_tlm_u_tlm_tx_vc0_frm_seq_cpld_av_i[8]) + ); + MUXCY_L com_tlm_u_tlm_tx_vc0_frm_seq_un4_cpld_diff_cry_9 ( + .CI(com_tlm_u_tlm_tx_vc0_frm_seq_un4_cpld_diff_cry_8_3643), + .DI(com_tlm_u_tlm_tx_vc0_frm_seq_VCC_3669), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_un4_cpld_diff_cry_9_3644), + .S(com_tlm_u_tlm_tx_vc0_frm_seq_cpld_av_i[9]) + ); + MUXCY_L com_tlm_u_tlm_tx_vc0_frm_seq_un4_cpld_diff_cry_10 ( + .CI(com_tlm_u_tlm_tx_vc0_frm_seq_un4_cpld_diff_cry_9_3644), + .DI(com_tlm_u_tlm_tx_vc0_frm_seq_VCC_3669), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_un4_cpld_diff_cry_10_3646), + .S(com_tlm_u_tlm_tx_vc0_frm_seq_cpld_av_i[10]) + ); + XORCY com_tlm_u_tlm_tx_vc0_frm_seq_un4_cpld_diff_s_11 ( + .CI(com_tlm_u_tlm_tx_vc0_frm_seq_un4_cpld_diff_cry_10_3646), + .LI(com_tlm_u_tlm_tx_vc0_frm_seq_un4_cpld_diff_s_11_sf_3681), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_un4_cpld_diff_s_11_3645) + ); + MUXCY_L com_tlm_u_tlm_tx_vc0_frm_seq_un4_bnpd_diff_cry_0 ( + .CI(com_tlm_u_tlm_tx_vc0_frm_seq_VCC_3669), + .DI(com_tlm_u_tlm_tx_vc0_frm_seq_npd_av[0]), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_un4_bnpd_diff_cry_0_3647), + .S(com_tlm_u_tlm_tx_vc0_frm_seq_un4_bnpd_diff_axb_0_3710) + ); + MUXCY_L com_tlm_u_tlm_tx_vc0_frm_seq_un4_bnpd_diff_cry_1 ( + .CI(com_tlm_u_tlm_tx_vc0_frm_seq_un4_bnpd_diff_cry_0_3647), + .DI(com_tlm_u_tlm_tx_vc0_frm_seq_npd_av[1]), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_un4_bnpd_diff_cry_1_3648), + .S(com_tlm_u_tlm_tx_vc0_frm_seq_un4_bnpd_diff_axb_1_3709) + ); + MUXCY_L com_tlm_u_tlm_tx_vc0_frm_seq_un4_bnpd_diff_cry_2 ( + .CI(com_tlm_u_tlm_tx_vc0_frm_seq_un4_bnpd_diff_cry_1_3648), + .DI(com_tlm_u_tlm_tx_vc0_frm_seq_npd_av[2]), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_un4_bnpd_diff_cry_2_3649), + .S(com_tlm_u_tlm_tx_vc0_frm_seq_un4_bnpd_diff_axb_2_3708) + ); + MUXCY_L com_tlm_u_tlm_tx_vc0_frm_seq_un4_bnpd_diff_cry_3 ( + .CI(com_tlm_u_tlm_tx_vc0_frm_seq_un4_bnpd_diff_cry_2_3649), + .DI(com_tlm_u_tlm_tx_vc0_frm_seq_npd_av[3]), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_un4_bnpd_diff_cry_3_3650), + .S(com_tlm_u_tlm_tx_vc0_frm_seq_un4_bnpd_diff_axb_3_3707) + ); + MUXCY_L com_tlm_u_tlm_tx_vc0_frm_seq_un4_bnpd_diff_cry_4 ( + .CI(com_tlm_u_tlm_tx_vc0_frm_seq_un4_bnpd_diff_cry_3_3650), + .DI(com_tlm_u_tlm_tx_vc0_frm_seq_npd_av[4]), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_un4_bnpd_diff_cry_4_3651), + .S(com_tlm_u_tlm_tx_vc0_frm_seq_un4_bnpd_diff_axb_4_3706) + ); + MUXCY_L com_tlm_u_tlm_tx_vc0_frm_seq_un4_bnpd_diff_cry_5 ( + .CI(com_tlm_u_tlm_tx_vc0_frm_seq_un4_bnpd_diff_cry_4_3651), + .DI(com_tlm_u_tlm_tx_vc0_frm_seq_npd_av[5]), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_un4_bnpd_diff_cry_5_3652), + .S(com_tlm_u_tlm_tx_vc0_frm_seq_un4_bnpd_diff_axb_5_3705) + ); + MUXCY_L com_tlm_u_tlm_tx_vc0_frm_seq_un4_bnpd_diff_cry_6 ( + .CI(com_tlm_u_tlm_tx_vc0_frm_seq_un4_bnpd_diff_cry_5_3652), + .DI(com_tlm_u_tlm_tx_vc0_frm_seq_VCC_3669), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_un4_bnpd_diff_cry_6_3653), + .S(com_tlm_u_tlm_tx_vc0_frm_seq_un4_bnpd_diff_cry_6_sf_3704) + ); + MUXCY_L com_tlm_u_tlm_tx_vc0_frm_seq_un4_bnpd_diff_cry_7 ( + .CI(com_tlm_u_tlm_tx_vc0_frm_seq_un4_bnpd_diff_cry_6_3653), + .DI(com_tlm_u_tlm_tx_vc0_frm_seq_VCC_3669), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_un4_bnpd_diff_cry_7_3654), + .S(com_tlm_u_tlm_tx_vc0_frm_seq_un4_bnpd_diff_cry_7_sf_3703) + ); + MUXCY_L com_tlm_u_tlm_tx_vc0_frm_seq_un4_bnpd_diff_cry_8 ( + .CI(com_tlm_u_tlm_tx_vc0_frm_seq_un4_bnpd_diff_cry_7_3654), + .DI(com_tlm_u_tlm_tx_vc0_frm_seq_VCC_3669), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_un4_bnpd_diff_cry_8_3655), + .S(com_tlm_u_tlm_tx_vc0_frm_seq_un4_bnpd_diff_cry_8_sf_3702) + ); + MUXCY_L com_tlm_u_tlm_tx_vc0_frm_seq_un4_bnpd_diff_cry_9 ( + .CI(com_tlm_u_tlm_tx_vc0_frm_seq_un4_bnpd_diff_cry_8_3655), + .DI(com_tlm_u_tlm_tx_vc0_frm_seq_VCC_3669), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_un4_bnpd_diff_cry_9_3656), + .S(com_tlm_u_tlm_tx_vc0_frm_seq_un4_bnpd_diff_cry_9_sf_3701) + ); + MUXCY_L com_tlm_u_tlm_tx_vc0_frm_seq_un4_bnpd_diff_cry_10 ( + .CI(com_tlm_u_tlm_tx_vc0_frm_seq_un4_bnpd_diff_cry_9_3656), + .DI(com_tlm_u_tlm_tx_vc0_frm_seq_VCC_3669), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_un4_bnpd_diff_cry_10_3658), + .S(com_tlm_u_tlm_tx_vc0_frm_seq_un4_bnpd_diff_cry_10_sf_3700) + ); + XORCY com_tlm_u_tlm_tx_vc0_frm_seq_un4_bnpd_diff_s_11 ( + .CI(com_tlm_u_tlm_tx_vc0_frm_seq_un4_bnpd_diff_cry_10_3658), + .LI(com_tlm_u_tlm_tx_vc0_frm_seq_un4_bnpd_diff_s_11_sf_3684), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_un4_bnpd_diff_s_11_3657) + ); + MUXCY_L com_tlm_u_tlm_tx_vc0_frm_seq_un4_pd_diff_cry_0 ( + .CI(com_tlm_u_tlm_tx_vc0_frm_seq_VCC_3669), + .DI(com_tlm_u_tlm_tx_vc0_frm_seq_pd_av_0_), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_un4_pd_diff_cry_0_3659), + .S(com_tlm_u_tlm_tx_vc0_frm_seq_un4_pd_diff_axb_0_3699) + ); + MUXCY_L com_tlm_u_tlm_tx_vc0_frm_seq_un4_pd_diff_cry_1 ( + .CI(com_tlm_u_tlm_tx_vc0_frm_seq_un4_pd_diff_cry_0_3659), + .DI(com_tlm_u_tlm_tx_vc0_frm_seq_pd_av_1_), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_un4_pd_diff_cry_1_3660), + .S(com_tlm_u_tlm_tx_vc0_frm_seq_un4_pd_diff_axb_1_3698) + ); + MUXCY_L com_tlm_u_tlm_tx_vc0_frm_seq_un4_pd_diff_cry_2 ( + .CI(com_tlm_u_tlm_tx_vc0_frm_seq_un4_pd_diff_cry_1_3660), + .DI(com_tlm_u_tlm_tx_vc0_frm_seq_pd_av_2_), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_un4_pd_diff_cry_2_3661), + .S(com_tlm_u_tlm_tx_vc0_frm_seq_un4_pd_diff_axb_2_3697) + ); + MUXCY_L com_tlm_u_tlm_tx_vc0_frm_seq_un4_pd_diff_cry_3 ( + .CI(com_tlm_u_tlm_tx_vc0_frm_seq_un4_pd_diff_cry_2_3661), + .DI(com_tlm_u_tlm_tx_vc0_frm_seq_pd_av_3_), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_un4_pd_diff_cry_3_3662), + .S(com_tlm_u_tlm_tx_vc0_frm_seq_un4_pd_diff_axb_3_3696) + ); + MUXCY_L com_tlm_u_tlm_tx_vc0_frm_seq_un4_pd_diff_cry_4 ( + .CI(com_tlm_u_tlm_tx_vc0_frm_seq_un4_pd_diff_cry_3_3662), + .DI(com_tlm_u_tlm_tx_vc0_frm_seq_pd_av_4_), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_un4_pd_diff_cry_4_3663), + .S(com_tlm_u_tlm_tx_vc0_frm_seq_un4_pd_diff_axb_4_3695) + ); + MUXCY_L com_tlm_u_tlm_tx_vc0_frm_seq_un4_pd_diff_cry_5 ( + .CI(com_tlm_u_tlm_tx_vc0_frm_seq_un4_pd_diff_cry_4_3663), + .DI(com_tlm_u_tlm_tx_vc0_frm_seq_pd_av_5_), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_un4_pd_diff_cry_5_3664), + .S(com_tlm_u_tlm_tx_vc0_frm_seq_un4_pd_diff_axb_5_3694) + ); + MUXCY_L com_tlm_u_tlm_tx_vc0_frm_seq_un4_pd_diff_cry_6 ( + .CI(com_tlm_u_tlm_tx_vc0_frm_seq_un4_pd_diff_cry_5_3664), + .DI(com_tlm_u_tlm_tx_vc0_frm_seq_VCC_3669), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_un4_pd_diff_cry_6_3665), + .S(com_tlm_u_tlm_tx_vc0_frm_seq_pd_av_i[6]) + ); + MUXCY_L com_tlm_u_tlm_tx_vc0_frm_seq_un4_pd_diff_cry_7 ( + .CI(com_tlm_u_tlm_tx_vc0_frm_seq_un4_pd_diff_cry_6_3665), + .DI(com_tlm_u_tlm_tx_vc0_frm_seq_VCC_3669), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_un4_pd_diff_cry_7_3666), + .S(com_tlm_u_tlm_tx_vc0_frm_seq_pd_av_i[7]) + ); + MUXCY_L com_tlm_u_tlm_tx_vc0_frm_seq_un4_pd_diff_cry_8 ( + .CI(com_tlm_u_tlm_tx_vc0_frm_seq_un4_pd_diff_cry_7_3666), + .DI(com_tlm_u_tlm_tx_vc0_frm_seq_VCC_3669), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_un4_pd_diff_cry_8_3667), + .S(com_tlm_u_tlm_tx_vc0_frm_seq_pd_av_i[8]) + ); + MUXCY_L com_tlm_u_tlm_tx_vc0_frm_seq_un4_pd_diff_cry_9 ( + .CI(com_tlm_u_tlm_tx_vc0_frm_seq_un4_pd_diff_cry_8_3667), + .DI(com_tlm_u_tlm_tx_vc0_frm_seq_VCC_3669), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_un4_pd_diff_cry_9_3668), + .S(com_tlm_u_tlm_tx_vc0_frm_seq_pd_av_i[9]) + ); + MUXCY_L com_tlm_u_tlm_tx_vc0_frm_seq_un4_pd_diff_cry_10 ( + .CI(com_tlm_u_tlm_tx_vc0_frm_seq_un4_pd_diff_cry_9_3668), + .DI(com_tlm_u_tlm_tx_vc0_frm_seq_VCC_3669), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_un4_pd_diff_cry_10_3671), + .S(com_tlm_u_tlm_tx_vc0_frm_seq_pd_av_i[10]) + ); + XORCY com_tlm_u_tlm_tx_vc0_frm_seq_un4_pd_diff_s_11 ( + .CI(com_tlm_u_tlm_tx_vc0_frm_seq_un4_pd_diff_cry_10_3671), + .LI(com_tlm_u_tlm_tx_vc0_frm_seq_un4_pd_diff_s_11_sf_3683), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_un4_pd_diff_s_11_3670) + ); + FDR com_tlm_u_tlm_tx_vc0_frm_seq_oq_cat_qq_1_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_oq_q[12]), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_oq_cat_qq[1]), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_tx_vc0_frm_seq_oq_cat_qq_0_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_oq_q[11]), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_oq_cat_qq[0]), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_tx_vc0_frm_seq_bq_ren ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_bq_renc_i), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_bq_ren_3675), + .R(plm_link_up_i) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_last_buf_num_match_3_0.INIT = 4'h6; + LUT2 com_tlm_u_tlm_tx_vc0_frm_seq_last_buf_num_match_3_0 ( + .I0(com_tlm_u_tlm_tx_ds_buf_num[0]), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_last_buf_num[0]), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_last_buf_num_match_3_0_3680) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_header_vld_oq_7_u_i_0_0_0_a2.INIT = 4'h4; + LUT2 com_tlm_u_tlm_tx_vc0_frm_seq_header_vld_oq_7_u_i_0_0_0_a2 ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_cplh_av), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_oq_q[12]), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_N_58460) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_nxt_queue_state_0_i_0_0_a2_0_1_2_.INIT = 4'h2; + LUT2 com_tlm_u_tlm_tx_vc0_frm_seq_nxt_queue_state_0_i_0_0_a2_0_1_2_ ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_queue_state[2]), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_sq_wen_3693), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_N_58767_1) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_bq_holdoff13_0_a2_0_a2_0_a2_0_a2.INIT = 4'h4; + LUT2 com_tlm_u_tlm_tx_vc0_frm_seq_bq_holdoff13_0_a2_0_a2_0_a2_0_a2 ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_bq_vld), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_bq_wen_3676), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_bq_holdoff13) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_oq_rdy_u_i_m4_0.INIT = 8'hB8; + LUT3_L com_tlm_u_tlm_tx_vc0_frm_seq_oq_rdy_u_i_m4_0 ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_npd_diff[11]), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_oq_cat_qq[0]), + .I2(com_tlm_u_tlm_tx_vc0_frm_seq_pd_diff[11]), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_N_62975) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_N_56491_i_i.INIT = 4'hE; + LUT2 com_tlm_u_tlm_tx_vc0_frm_seq_N_56491_i_i ( + .I0(com_tlm_u_tlm_tx_am_retry_dst_rdy), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_seq_state[1]), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_N_56491_i_i_3692) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_bq_rdy.INIT = 8'hD0; + LUT3 com_tlm_u_tlm_tx_vc0_frm_seq_bq_rdy ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_bnpd_diff[11]), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_bq_no_payload_qq_3673), + .I2(com_tlm_u_tlm_tx_vc0_frm_seq_header_vld_bq_3672), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_bq_rdy_3690) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_reg_ren_bq_wen_14_u_i_0_0_o3.INIT = 8'h10; + LUT3 com_tlm_u_tlm_tx_vc0_frm_seq_reg_ren_bq_wen_14_u_i_0_0_o3 ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_sq_cnt[0]), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_sq_cnt[1]), + .I2(com_tlm_u_tlm_tx_vc0_frm_seq_sq_cnt[2]), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_N_56190_i) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_nxt_queue_state_0_i_0_0_a2_2_.INIT = 8'h04; + LUT3 com_tlm_u_tlm_tx_vc0_frm_seq_nxt_queue_state_0_i_0_0_a2_2_ ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_last_buf_num_match_3689), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_queue_state[3]), + .I2(com_tlm_u_tlm_tx_vc0_frm_seq_sq_wen_3693), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_N_58766) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_nxt_queue_state_0_i_0_0_a2_1_2_.INIT = 16'h0008; + LUT4 com_tlm_u_tlm_tx_vc0_frm_seq_nxt_queue_state_0_i_0_0_a2_1_2_ ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_queue_state[1]), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_seq_state[1]), + .I2(com_tlm_u_tlm_tx_vc0_frm_seq_sq_nxt_vld), + .I3(com_tlm_u_tlm_tx_vc0_frm_seq_sq_wen_3693), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_N_58768) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_header_vld_oq_7_u_i_0_0_0_a2_2.INIT = 16'h0020; + LUT4 com_tlm_u_tlm_tx_vc0_frm_seq_header_vld_oq_7_u_i_0_0_0_a2_2 ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_bq_holdoff_3674), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_bq_vld), + .I2(com_tlm_u_tlm_tx_vc0_frm_seq_oq_q[11]), + .I3(com_tlm_u_tlm_tx_vc0_frm_seq_oq_q[12]), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_N_58463) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_header_vld_oq_7_u_i_0_0_0_1_0.INIT = 8'h08; + LUT3 com_tlm_u_tlm_tx_vc0_frm_seq_header_vld_oq_7_u_i_0_0_0_1_0 ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_N_62984_i), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_av_valid), + .I2(com_tlm_u_tlm_tx_vc0_frm_seq_bq_ren_3675), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_N_16926_i_1) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_bq_renc_2.INIT = 16'h0001; + LUT4 com_tlm_u_tlm_tx_vc0_frm_seq_bq_renc_2 ( + .I0(com_link_status[1]), + .I1(com_link_status[2]), + .I2(com_tlm_u_tlm_tx_vc0_frm_seq_bq_wen_3676), + .I3(com_tlm_u_tlm_tx_vc0_frm_seq_sq_wen_3693), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_N_56218_i) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_last_buf_num_match_3_NE_0.INIT = 16'h8421; + LUT4 com_tlm_u_tlm_tx_vc0_frm_seq_last_buf_num_match_3_NE_0 ( + .I0(com_tlm_u_tlm_tx_ds_buf_num[2]), + .I1(com_tlm_u_tlm_tx_ds_buf_num[3]), + .I2(com_tlm_u_tlm_tx_vc0_frm_seq_last_buf_num[2]), + .I3(com_tlm_u_tlm_tx_vc0_frm_seq_last_buf_num[3]), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_last_buf_num_match_3_NE_0_3679) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_un1_seq_state_2_i_0_0_0_a2.INIT = 16'hD080; + LUT4 com_tlm_u_tlm_tx_vc0_frm_seq_un1_seq_state_2_i_0_0_0_a2 ( + .I0(com_tlm_u_tlm_tx_am_retry_lock), + .I1(com_tlm_u_tlm_tx_am_retry_src_rdy), + .I2(com_tlm_u_tlm_tx_vc0_frm_seq_seq_state[0]), + .I3(com_tlm_u_tlm_tx_vc0_frm_seq_sq_vld), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_N_58771) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_N_35287_i_i_a3.INIT = 8'h10; + LUT3 com_tlm_u_tlm_tx_vc0_frm_seq_N_35287_i_i_a3 ( + .I0(com_tlm_u_tlm_tx_vc0_N_55914_i), + .I1(com_tlm_u_tlm_tx_vc0_N_55980_i), + .I2(com_tlm_u_tlm_tx_vc0_in_frame), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_N_61285) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_oq_rdy_u_i_m3_0.INIT = 8'hCA; + LUT3_L com_tlm_u_tlm_tx_vc0_frm_seq_oq_rdy_u_i_m3_0 ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_N_62975), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_cpld_diff[11]), + .I2(com_tlm_u_tlm_tx_vc0_frm_seq_oq_cat_qq[1]), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_N_62976) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_header_vld_oq_7_u_i_0_0_0_39305.INIT = 16'hFBF8; + LUT4 com_tlm_u_tlm_tx_vc0_frm_seq_header_vld_oq_7_u_i_0_0_0_39305 ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_nph_av), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_oq_q[11]), + .I2(com_tlm_u_tlm_tx_vc0_frm_seq_oq_q[12]), + .I3(com_tlm_u_tlm_tx_vc0_frm_seq_ph_av), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_header_vld_oq_7_u_i_0_0_0_39305_3685) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_reg_ren_bq_wen_14_u_i_0_0_0.INIT = 4'h8; + LUT2 com_tlm_u_tlm_tx_vc0_frm_seq_reg_ren_bq_wen_14_u_i_0_0_0 ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_N_56218_i), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_nonposted_vld_oq_3691), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_bq_wen_14_u_i_0_0_0) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_reg_ren_consumed_cplh_10_i_0_0_1_1.INIT = 16'h0004; + LUT4 com_tlm_u_tlm_tx_vc0_frm_seq_reg_ren_consumed_cplh_10_i_0_0_1_1 ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_N_56190_i), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_N_56218_i), + .I2(com_tlm_u_tlm_tx_vc0_frm_seq_bq_rdy_3690), + .I3(com_tlm_u_tlm_tx_vc0_frm_seq_oq_q[11]), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_consumed_cplh_10_i_0_0_1_1) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_oq_rdy_u_i_i_a2_0_a3.INIT = 8'hC4; + LUT3 com_tlm_u_tlm_tx_vc0_frm_seq_oq_rdy_u_i_i_a2_0_a3 ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_N_62976), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_header_vld_oq_3678), + .I2(com_tlm_u_tlm_tx_vc0_frm_seq_oq_no_payload_qq_3677), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_N_63484) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_un1_seq_state_2_i_0_0_0_1.INIT = 16'h13FF; + LUT4 com_tlm_u_tlm_tx_vc0_frm_seq_un1_seq_state_2_i_0_0_0_1 ( + .I0(com_tlm_u_tlm_tx_vc0_N_56167_i), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_N_61285), + .I2(com_tlm_u_tlm_tx_vc0_in_frame), + .I3(com_tlm_u_tlm_tx_vc0_start_src_rdy), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_N_20410_i_1) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_N_35287_i_i_o2.INIT = 16'h1300; + LUT4 com_tlm_u_tlm_tx_vc0_frm_seq_N_35287_i_i_o2 ( + .I0(com_tlm_u_tlm_tx_vc0_N_56167_i), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_N_61285), + .I2(com_tlm_u_tlm_tx_vc0_in_frame), + .I3(com_tlm_u_tlm_tx_vc0_start_src_rdy), + .O(com_tlm_u_tlm_tx_vc0_N_55858_i) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_reg_ren_oq_ren_12_iv_0_0_0_m2_0.INIT = 8'hD8; + LUT3_L com_tlm_u_tlm_tx_vc0_frm_seq_reg_ren_oq_ren_12_iv_0_0_0_m2_0 ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_N_56190_i), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_N_63484), + .I2(com_tlm_u_tlm_tx_vc0_frm_seq_bq_rdy_3690), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_N_57053) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_reg_ren_consumed_nph_10_iv_0_0_0_0_o2.INIT = 16'h4440; + LUT4 com_tlm_u_tlm_tx_vc0_frm_seq_reg_ren_consumed_nph_10_iv_0_0_0_0_o2 ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_N_56190_i), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_N_56218_i), + .I2(com_tlm_u_tlm_tx_vc0_frm_seq_N_63484), + .I3(com_tlm_u_tlm_tx_vc0_frm_seq_bq_rdy_3690), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_N_57072_i) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_bq_renc.INIT = 8'h40; + LUT3_L com_tlm_u_tlm_tx_vc0_frm_seq_bq_renc ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_N_56190_i), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_N_56218_i), + .I2(com_tlm_u_tlm_tx_vc0_frm_seq_bq_rdy_3690), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_bq_renc_i) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_reg_ren_consumed_credits_4_i_m3_i_m3_i_m3_i_m3_0_5_.INIT = 8'hCA; + LUT3_L com_tlm_u_tlm_tx_vc0_frm_seq_reg_ren_consumed_credits_4_i_m3_i_m3_i_m3_i_m3_0_5_ ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_bq_d[9]), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_bq_q[9]), + .I2(com_tlm_u_tlm_tx_vc0_frm_seq_bq_rdy_3690), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_consumed_credits_4_i_m3_i_m3_i_m3_i_m3_0[5]) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_reg_ren_consumed_credits_4_i_m3_i_m3_i_m3_i_m3_0_4_.INIT = 8'hCA; + LUT3_L com_tlm_u_tlm_tx_vc0_frm_seq_reg_ren_consumed_credits_4_i_m3_i_m3_i_m3_i_m3_0_4_ ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_bq_d[8]), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_bq_q[8]), + .I2(com_tlm_u_tlm_tx_vc0_frm_seq_bq_rdy_3690), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_consumed_credits_4_i_m3_i_m3_i_m3_i_m3_0[4]) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_reg_ren_consumed_credits_4_i_m3_i_m3_i_m3_i_m3_0_3_.INIT = 8'hCA; + LUT3_L com_tlm_u_tlm_tx_vc0_frm_seq_reg_ren_consumed_credits_4_i_m3_i_m3_i_m3_i_m3_0_3_ ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_bq_d[7]), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_bq_q[7]), + .I2(com_tlm_u_tlm_tx_vc0_frm_seq_bq_rdy_3690), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_consumed_credits_4_i_m3_i_m3_i_m3_i_m3_0[3]) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_reg_ren_consumed_credits_4_i_m3_i_m3_i_m3_i_m3_0_2_.INIT = 8'hCA; + LUT3_L com_tlm_u_tlm_tx_vc0_frm_seq_reg_ren_consumed_credits_4_i_m3_i_m3_i_m3_i_m3_0_2_ ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_bq_d[6]), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_bq_q[6]), + .I2(com_tlm_u_tlm_tx_vc0_frm_seq_bq_rdy_3690), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_consumed_credits_4_i_m3_i_m3_i_m3_i_m3_0[2]) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_reg_ren_consumed_credits_4_i_m3_i_m3_i_m3_i_m3_0_1_.INIT = 8'hCA; + LUT3_L com_tlm_u_tlm_tx_vc0_frm_seq_reg_ren_consumed_credits_4_i_m3_i_m3_i_m3_i_m3_0_1_ ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_bq_d[5]), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_bq_q[5]), + .I2(com_tlm_u_tlm_tx_vc0_frm_seq_bq_rdy_3690), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_consumed_credits_4_i_m3_i_m3_i_m3_i_m3_0[1]) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_reg_ren_consumed_credits_4_i_m3_i_m3_i_m3_i_m3_0_0_.INIT = 8'hCA; + LUT3_L com_tlm_u_tlm_tx_vc0_frm_seq_reg_ren_consumed_credits_4_i_m3_i_m3_i_m3_i_m3_0_0_ ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_bq_d[4]), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_bq_q[4]), + .I2(com_tlm_u_tlm_tx_vc0_frm_seq_bq_rdy_3690), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_consumed_credits_4_i_m3_i_m3_i_m3_i_m3_0[0]) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_reg_ren_sq_d_4_i_m3_i_m3_i_m3_i_m3_0_3_.INIT = 8'hCA; + LUT3_L com_tlm_u_tlm_tx_vc0_frm_seq_reg_ren_sq_d_4_i_m3_i_m3_i_m3_i_m3_0_3_ ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_bq_d[3]), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_bq_q[3]), + .I2(com_tlm_u_tlm_tx_vc0_frm_seq_bq_rdy_3690), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_sq_d_4_i_m3_i_m3_i_m3_i_m3_0[3]) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_reg_ren_sq_d_4_i_m3_i_m3_i_m3_i_m3_0_2_.INIT = 8'hCA; + LUT3_L com_tlm_u_tlm_tx_vc0_frm_seq_reg_ren_sq_d_4_i_m3_i_m3_i_m3_i_m3_0_2_ ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_bq_d[2]), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_bq_q[2]), + .I2(com_tlm_u_tlm_tx_vc0_frm_seq_bq_rdy_3690), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_sq_d_4_i_m3_i_m3_i_m3_i_m3_0[2]) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_reg_ren_sq_d_4_i_m3_i_m3_i_m3_i_m3_0_1_.INIT = 8'hCA; + LUT3_L com_tlm_u_tlm_tx_vc0_frm_seq_reg_ren_sq_d_4_i_m3_i_m3_i_m3_i_m3_0_1_ ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_bq_d[1]), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_bq_q[1]), + .I2(com_tlm_u_tlm_tx_vc0_frm_seq_bq_rdy_3690), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_sq_d_4_i_m3_i_m3_i_m3_i_m3_0[1]) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_reg_ren_sq_d_4_i_m3_i_m3_i_m3_i_m3_0_0_.INIT = 8'hCA; + LUT3_L com_tlm_u_tlm_tx_vc0_frm_seq_reg_ren_sq_d_4_i_m3_i_m3_i_m3_i_m3_0_0_ ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_bq_d[0]), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_bq_q[0]), + .I2(com_tlm_u_tlm_tx_vc0_frm_seq_bq_rdy_3690), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_sq_d_4_i_m3_i_m3_i_m3_i_m3_0[0]) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_start_buf_o_2_i_m2_i_m3_i_m3_0_3_.INIT = 8'hD8; + LUT3_L com_tlm_u_tlm_tx_vc0_frm_seq_start_buf_o_2_i_m2_i_m3_i_m3_0_3_ ( + .I0(com_tlm_u_tlm_tx_am_retry_dst_rdy), + .I1(com_tlm_u_tlm_tx_freed_buf[3]), + .I2(com_tlm_u_tlm_tx_vc0_frm_seq_sq_q[3]), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_start_buf_o_2_i_m2_i_m3_i_m3_0[3]) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_start_buf_o_2_i_m2_i_m3_i_m3_0_2_.INIT = 8'hD8; + LUT3_L com_tlm_u_tlm_tx_vc0_frm_seq_start_buf_o_2_i_m2_i_m3_i_m3_0_2_ ( + .I0(com_tlm_u_tlm_tx_am_retry_dst_rdy), + .I1(com_tlm_u_tlm_tx_freed_buf[2]), + .I2(com_tlm_u_tlm_tx_vc0_frm_seq_sq_q[2]), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_start_buf_o_2_i_m2_i_m3_i_m3_0[2]) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_start_buf_o_2_i_m2_i_m3_i_m3_0_1_.INIT = 8'hD8; + LUT3_L com_tlm_u_tlm_tx_vc0_frm_seq_start_buf_o_2_i_m2_i_m3_i_m3_0_1_ ( + .I0(com_tlm_u_tlm_tx_am_retry_dst_rdy), + .I1(com_tlm_u_tlm_tx_freed_buf[1]), + .I2(com_tlm_u_tlm_tx_vc0_frm_seq_sq_q[1]), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_start_buf_o_2_i_m2_i_m3_i_m3_0[1]) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_start_buf_o_2_i_m2_i_m3_i_m3_0_0_.INIT = 8'hD8; + LUT3_L com_tlm_u_tlm_tx_vc0_frm_seq_start_buf_o_2_i_m2_i_m3_i_m3_0_0_ ( + .I0(com_tlm_u_tlm_tx_am_retry_dst_rdy), + .I1(com_tlm_u_tlm_tx_freed_buf[0]), + .I2(com_tlm_u_tlm_tx_vc0_frm_seq_sq_q[0]), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_start_buf_o_2_i_m2_i_m3_i_m3_0[0]) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_last_buf_num_match_3_NE.INIT = 16'h0900; + LUT4_L com_tlm_u_tlm_tx_vc0_frm_seq_last_buf_num_match_3_NE ( + .I0(com_tlm_u_tlm_tx_ds_buf_num[1]), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_last_buf_num[1]), + .I2(com_tlm_u_tlm_tx_vc0_frm_seq_last_buf_num_match_3_0_3680), + .I3(com_tlm_u_tlm_tx_vc0_frm_seq_last_buf_num_match_3_NE_0_3679), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_last_buf_num_match_3) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_header_vld_bq_3_0_a2_0_a2_0_a2.INIT = 16'h0080; + LUT4_L com_tlm_u_tlm_tx_vc0_frm_seq_header_vld_bq_3_0_a2_0_a2_0_a2 ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_av_valid), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_bq_vld), + .I2(com_tlm_u_tlm_tx_vc0_frm_seq_nph_av), + .I3(com_tlm_u_tlm_tx_vc0_frm_seq_sq_wen_3693), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_header_vld_bq_3) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_nonposted_vld_oq_3_0_a2_0_a2_0_a2.INIT = 8'h08; + LUT3_L com_tlm_u_tlm_tx_vc0_frm_seq_nonposted_vld_oq_3_0_a2_0_a2_0_a2 ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_N_16926_i_1), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_oq_q[11]), + .I2(com_tlm_u_tlm_tx_vc0_frm_seq_oq_q[12]), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_nonposted_vld_oq_3) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_un4_cpld_diff_s_11_sf.INIT = 4'h1; + LUT1_L com_tlm_u_tlm_tx_vc0_frm_seq_un4_cpld_diff_s_11_sf ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_cpld_av_11_), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_un4_cpld_diff_s_11_sf_3681) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_un4_npd_diff_s_11_sf.INIT = 4'h1; + LUT1_L com_tlm_u_tlm_tx_vc0_frm_seq_un4_npd_diff_s_11_sf ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_npd_av[11]), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_un4_npd_diff_s_11_sf_3682) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_un4_pd_diff_s_11_sf.INIT = 4'h1; + LUT1_L com_tlm_u_tlm_tx_vc0_frm_seq_un4_pd_diff_s_11_sf ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_pd_av_11_), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_un4_pd_diff_s_11_sf_3683) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_un4_bnpd_diff_s_11_sf.INIT = 4'h1; + LUT1_L com_tlm_u_tlm_tx_vc0_frm_seq_un4_bnpd_diff_s_11_sf ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_npd_av[11]), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_un4_bnpd_diff_s_11_sf_3684) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_header_vld_oq_7_u_i_0_0_0.INIT = 16'h0200; + LUT4_L com_tlm_u_tlm_tx_vc0_frm_seq_header_vld_oq_7_u_i_0_0_0 ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_N_16926_i_1), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_N_58460), + .I2(com_tlm_u_tlm_tx_vc0_frm_seq_N_58463), + .I3(com_tlm_u_tlm_tx_vc0_frm_seq_header_vld_oq_7_u_i_0_0_0_39305_3685), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_N_16926_i) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_N_85820_i.INIT = 8'hFD; + LUT3_L com_tlm_u_tlm_tx_vc0_frm_seq_N_85820_i ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_N_20410_i_1), + .I1(com_tlm_u_tlm_tx_am_retry_dst_rdy), + .I2(com_tlm_u_tlm_tx_vc0_frm_seq_seq_state[1]), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_N_85820_i_3686) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_nxt_seq_state_0_sqmuxa_1_0_a2_0_a2_1_a2_0_a2_0_a2.INIT = 8'h80; + LUT3_L com_tlm_u_tlm_tx_vc0_frm_seq_nxt_seq_state_0_sqmuxa_1_0_a2_0_a2_1_a2_0_a2_0_a2 ( + .I0(com_tlm_u_tlm_tx_am_retry_lock), + .I1(com_tlm_u_tlm_tx_am_retry_src_rdy), + .I2(com_tlm_u_tlm_tx_vc0_frm_seq_seq_state[0]), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_nxt_seq_state_0_sqmuxa_1) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_nxt_seq_state_0_sqmuxa_2_0_a2_1_a2_0_a2_0_a2.INIT = 8'h40; + LUT3_L com_tlm_u_tlm_tx_vc0_frm_seq_nxt_seq_state_0_sqmuxa_2_0_a2_1_a2_0_a2_0_a2 ( + .I0(com_tlm_u_tlm_tx_am_retry_lock), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_seq_state[0]), + .I2(com_tlm_u_tlm_tx_vc0_frm_seq_sq_vld), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_nxt_seq_state_0_sqmuxa_2) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_un1_seq_state_2_i_0_0_0.INIT = 16'h0002; + LUT4_L com_tlm_u_tlm_tx_vc0_frm_seq_un1_seq_state_2_i_0_0_0 ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_N_20410_i_1), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_N_58771), + .I2(com_tlm_u_tlm_tx_am_retry_dst_rdy), + .I3(com_tlm_u_tlm_tx_vc0_frm_seq_seq_state[1]), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_N_20410_i) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_reg_ren_consumed_cplh_10_i_0_0.INIT = 8'h80; + LUT3_L com_tlm_u_tlm_tx_vc0_frm_seq_reg_ren_consumed_cplh_10_i_0_0 ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_N_63484), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_oq_q[12]), + .I2(com_tlm_u_tlm_tx_vc0_frm_seq_consumed_cplh_10_i_0_0_1_1), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_N_16888_i) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_reg_ren_consumed_ph_10_i_0_0.INIT = 8'h20; + LUT3_L com_tlm_u_tlm_tx_vc0_frm_seq_reg_ren_consumed_ph_10_i_0_0 ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_N_63484), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_oq_q[12]), + .I2(com_tlm_u_tlm_tx_vc0_frm_seq_consumed_cplh_10_i_0_0_1_1), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_N_16890_i) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_N_85898_i.INIT = 16'hFAFE; + LUT4_L com_tlm_u_tlm_tx_vc0_frm_seq_N_85898_i ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_N_58766), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_N_58767_1), + .I2(com_tlm_u_tlm_tx_vc0_frm_seq_N_58768), + .I3(com_tlm_u_tlm_tx_ds_buf_src_rdy), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_N_85898_i_3687) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_N_86359_i.INIT = 16'hFFA2; + LUT4_L com_tlm_u_tlm_tx_vc0_frm_seq_N_86359_i ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_queue_state[1]), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_seq_state[1]), + .I2(com_tlm_u_tlm_tx_vc0_frm_seq_sq_nxt_vld), + .I3(com_tlm_u_tlm_tx_vc0_frm_seq_sq_wen_3693), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_N_86359_i_3688) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_nxt_queue_state_0_i_0_0_i_0_.INIT = 16'h00EC; + LUT4_L com_tlm_u_tlm_tx_vc0_frm_seq_nxt_queue_state_0_i_0_0_i_0_ ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_last_buf_num_match_3689), + .I1(com_tlm_u_tlm_tx_queue_state[0]), + .I2(com_tlm_u_tlm_tx_vc0_frm_seq_queue_state[3]), + .I3(com_tlm_u_tlm_tx_vc0_frm_seq_sq_wen_3693), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_N_52360_i) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_reg_ren_bq_wen_14_u_i_0_0.INIT = 16'h2300; + LUT4_L com_tlm_u_tlm_tx_vc0_frm_seq_reg_ren_bq_wen_14_u_i_0_0 ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_N_56190_i), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_N_63484), + .I2(com_tlm_u_tlm_tx_vc0_frm_seq_bq_rdy_3690), + .I3(com_tlm_u_tlm_tx_vc0_frm_seq_bq_wen_14_u_i_0_0_0), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_N_16924_i) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_reg_ren_consumed_nph_10_iv_0_0_0_0.INIT = 16'h88A8; + LUT4_L com_tlm_u_tlm_tx_vc0_frm_seq_reg_ren_consumed_nph_10_iv_0_0_0_0 ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_N_57072_i), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_bq_rdy_3690), + .I2(com_tlm_u_tlm_tx_vc0_frm_seq_oq_q[11]), + .I3(com_tlm_u_tlm_tx_vc0_frm_seq_oq_q[12]), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_N_9929_i) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_reg_ren_oq_ren_12_iv_0_0_0.INIT = 16'h2220; + LUT4_L com_tlm_u_tlm_tx_vc0_frm_seq_reg_ren_oq_ren_12_iv_0_0_0 ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_N_56218_i), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_N_57053), + .I2(com_tlm_u_tlm_tx_vc0_frm_seq_N_63484), + .I3(com_tlm_u_tlm_tx_vc0_frm_seq_nonposted_vld_oq_3691), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_N_9928_i) + ); + FD com_tlm_u_tlm_tx_vc0_frm_seq_consumed_credits_5_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_consumed_credits_4_i_m3_i_m3_i_m3_i_m3_0[5]), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_consumed_credits[5]) + ); + FD com_tlm_u_tlm_tx_vc0_frm_seq_consumed_credits_4_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_consumed_credits_4_i_m3_i_m3_i_m3_i_m3_0[4]), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_consumed_credits[4]) + ); + FD com_tlm_u_tlm_tx_vc0_frm_seq_consumed_credits_3_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_consumed_credits_4_i_m3_i_m3_i_m3_i_m3_0[3]), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_consumed_credits[3]) + ); + FD com_tlm_u_tlm_tx_vc0_frm_seq_consumed_credits_2_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_consumed_credits_4_i_m3_i_m3_i_m3_i_m3_0[2]), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_consumed_credits[2]) + ); + FD com_tlm_u_tlm_tx_vc0_frm_seq_consumed_credits_1_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_consumed_credits_4_i_m3_i_m3_i_m3_i_m3_0[1]), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_consumed_credits[1]) + ); + FD com_tlm_u_tlm_tx_vc0_frm_seq_consumed_credits_0_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_consumed_credits_4_i_m3_i_m3_i_m3_i_m3_0[0]), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_consumed_credits[0]) + ); + FD com_tlm_u_tlm_tx_vc0_frm_seq_sq_d_3_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_sq_d_4_i_m3_i_m3_i_m3_i_m3_0[3]), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_sq_d[3]) + ); + FD com_tlm_u_tlm_tx_vc0_frm_seq_sq_d_2_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_sq_d_4_i_m3_i_m3_i_m3_i_m3_0[2]), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_sq_d[2]) + ); + FD com_tlm_u_tlm_tx_vc0_frm_seq_sq_d_1_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_sq_d_4_i_m3_i_m3_i_m3_i_m3_0[1]), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_sq_d[1]) + ); + FD com_tlm_u_tlm_tx_vc0_frm_seq_sq_d_0_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_sq_d_4_i_m3_i_m3_i_m3_i_m3_0[0]), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_sq_d[0]) + ); + FDE com_tlm_u_tlm_tx_vc0_frm_seq_start_retry_tsn_o_11_ ( + .CE(com_tlm_u_tlm_tx_am_retry_dst_rdy), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_am_retry_tsn[11]), + .Q(com_tlm_u_tlm_tx_vc0_start_retry_tsn[11]) + ); + FDE com_tlm_u_tlm_tx_vc0_frm_seq_start_retry_tsn_o_10_ ( + .CE(com_tlm_u_tlm_tx_am_retry_dst_rdy), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_am_retry_tsn[10]), + .Q(com_tlm_u_tlm_tx_vc0_start_retry_tsn[10]) + ); + FDE com_tlm_u_tlm_tx_vc0_frm_seq_start_retry_tsn_o_9_ ( + .CE(com_tlm_u_tlm_tx_am_retry_dst_rdy), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_am_retry_tsn[9]), + .Q(com_tlm_u_tlm_tx_vc0_start_retry_tsn[9]) + ); + FDE com_tlm_u_tlm_tx_vc0_frm_seq_start_retry_tsn_o_8_ ( + .CE(com_tlm_u_tlm_tx_am_retry_dst_rdy), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_am_retry_tsn[8]), + .Q(com_tlm_u_tlm_tx_vc0_start_retry_tsn[8]) + ); + FDE com_tlm_u_tlm_tx_vc0_frm_seq_start_retry_tsn_o_7_ ( + .CE(com_tlm_u_tlm_tx_am_retry_dst_rdy), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_am_retry_tsn[7]), + .Q(com_tlm_u_tlm_tx_vc0_start_retry_tsn[7]) + ); + FDE com_tlm_u_tlm_tx_vc0_frm_seq_start_retry_tsn_o_6_ ( + .CE(com_tlm_u_tlm_tx_am_retry_dst_rdy), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_am_retry_tsn[6]), + .Q(com_tlm_u_tlm_tx_vc0_start_retry_tsn[6]) + ); + FDE com_tlm_u_tlm_tx_vc0_frm_seq_start_retry_tsn_o_5_ ( + .CE(com_tlm_u_tlm_tx_am_retry_dst_rdy), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_am_retry_tsn[5]), + .Q(com_tlm_u_tlm_tx_vc0_start_retry_tsn[5]) + ); + FDE com_tlm_u_tlm_tx_vc0_frm_seq_start_retry_tsn_o_4_ ( + .CE(com_tlm_u_tlm_tx_am_retry_dst_rdy), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_am_retry_tsn[4]), + .Q(com_tlm_u_tlm_tx_vc0_start_retry_tsn[4]) + ); + FDE com_tlm_u_tlm_tx_vc0_frm_seq_start_retry_tsn_o_3_ ( + .CE(com_tlm_u_tlm_tx_am_retry_dst_rdy), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_am_retry_tsn[3]), + .Q(com_tlm_u_tlm_tx_vc0_start_retry_tsn[3]) + ); + FDE com_tlm_u_tlm_tx_vc0_frm_seq_start_retry_tsn_o_2_ ( + .CE(com_tlm_u_tlm_tx_am_retry_dst_rdy), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_am_retry_tsn[2]), + .Q(com_tlm_u_tlm_tx_vc0_start_retry_tsn[2]) + ); + FDE com_tlm_u_tlm_tx_vc0_frm_seq_start_retry_tsn_o_1_ ( + .CE(com_tlm_u_tlm_tx_am_retry_dst_rdy), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_am_retry_tsn[1]), + .Q(com_tlm_u_tlm_tx_vc0_start_retry_tsn[1]) + ); + FDE com_tlm_u_tlm_tx_vc0_frm_seq_start_retry_tsn_o_0_ ( + .CE(com_tlm_u_tlm_tx_am_retry_dst_rdy), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_am_retry_tsn[0]), + .Q(com_tlm_u_tlm_tx_vc0_start_retry_tsn[0]) + ); + FDE com_tlm_u_tlm_tx_vc0_frm_seq_start_buf_o_3_ ( + .CE(com_tlm_u_tlm_tx_vc0_frm_seq_N_56491_i_i_3692), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_start_buf_o_2_i_m2_i_m3_i_m3_0[3]), + .Q(com_tlm_u_tlm_tx_vc0_start_buf_num[3]) + ); + FDE com_tlm_u_tlm_tx_vc0_frm_seq_start_buf_o_2_ ( + .CE(com_tlm_u_tlm_tx_vc0_frm_seq_N_56491_i_i_3692), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_start_buf_o_2_i_m2_i_m3_i_m3_0[2]), + .Q(com_tlm_u_tlm_tx_vc0_start_buf_num[2]) + ); + FDE com_tlm_u_tlm_tx_vc0_frm_seq_start_buf_o_1_ ( + .CE(com_tlm_u_tlm_tx_vc0_frm_seq_N_56491_i_i_3692), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_start_buf_o_2_i_m2_i_m3_i_m3_0[1]), + .Q(com_tlm_u_tlm_tx_vc0_start_buf_num[1]) + ); + FDE com_tlm_u_tlm_tx_vc0_frm_seq_start_buf_o_0_ ( + .CE(com_tlm_u_tlm_tx_vc0_frm_seq_N_56491_i_i_3692), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_start_buf_o_2_i_m2_i_m3_i_m3_0[0]), + .Q(com_tlm_u_tlm_tx_vc0_start_buf_num[0]) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_nxt_queue_state_1_sqmuxa_1_0_a2.INIT = 8'h20; + LUT3_L com_tlm_u_tlm_tx_vc0_frm_seq_nxt_queue_state_1_sqmuxa_1_0_a2 ( + .I0(com_tlm_u_tlm_tx_ds_buf_src_rdy), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_sq_wen_3693), + .I2(com_tlm_u_tlm_tx_vc0_frm_seq_queue_state[2]), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_nxt_queue_state_1_sqmuxa_1) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_un4_pd_diff_axb_5.INIT = 4'h9; + LUT2 com_tlm_u_tlm_tx_vc0_frm_seq_un4_pd_diff_axb_5 ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_bq_d[9]), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_pd_av_5_), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_un4_pd_diff_axb_5_3694) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_un4_pd_diff_axb_4.INIT = 4'h9; + LUT2 com_tlm_u_tlm_tx_vc0_frm_seq_un4_pd_diff_axb_4 ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_bq_d[8]), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_pd_av_4_), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_un4_pd_diff_axb_4_3695) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_un4_pd_diff_axb_3.INIT = 4'h9; + LUT2 com_tlm_u_tlm_tx_vc0_frm_seq_un4_pd_diff_axb_3 ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_bq_d[7]), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_pd_av_3_), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_un4_pd_diff_axb_3_3696) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_un4_pd_diff_axb_2.INIT = 4'h9; + LUT2 com_tlm_u_tlm_tx_vc0_frm_seq_un4_pd_diff_axb_2 ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_bq_d[6]), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_pd_av_2_), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_un4_pd_diff_axb_2_3697) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_un4_pd_diff_axb_1.INIT = 4'h9; + LUT2 com_tlm_u_tlm_tx_vc0_frm_seq_un4_pd_diff_axb_1 ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_bq_d[5]), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_pd_av_1_), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_un4_pd_diff_axb_1_3698) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_un4_pd_diff_axb_0.INIT = 4'h9; + LUT2 com_tlm_u_tlm_tx_vc0_frm_seq_un4_pd_diff_axb_0 ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_bq_d[4]), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_pd_av_0_), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_un4_pd_diff_axb_0_3699) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_un4_bnpd_diff_cry_10_sf.INIT = 4'h1; + LUT1 com_tlm_u_tlm_tx_vc0_frm_seq_un4_bnpd_diff_cry_10_sf ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_npd_av[10]), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_un4_bnpd_diff_cry_10_sf_3700) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_un4_bnpd_diff_cry_9_sf.INIT = 4'h1; + LUT1 com_tlm_u_tlm_tx_vc0_frm_seq_un4_bnpd_diff_cry_9_sf ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_npd_av[9]), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_un4_bnpd_diff_cry_9_sf_3701) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_un4_bnpd_diff_cry_8_sf.INIT = 4'h1; + LUT1 com_tlm_u_tlm_tx_vc0_frm_seq_un4_bnpd_diff_cry_8_sf ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_npd_av[8]), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_un4_bnpd_diff_cry_8_sf_3702) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_un4_bnpd_diff_cry_7_sf.INIT = 4'h1; + LUT1 com_tlm_u_tlm_tx_vc0_frm_seq_un4_bnpd_diff_cry_7_sf ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_npd_av[7]), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_un4_bnpd_diff_cry_7_sf_3703) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_un4_bnpd_diff_cry_6_sf.INIT = 4'h1; + LUT1 com_tlm_u_tlm_tx_vc0_frm_seq_un4_bnpd_diff_cry_6_sf ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_npd_av[6]), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_un4_bnpd_diff_cry_6_sf_3704) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_un4_bnpd_diff_axb_5.INIT = 4'h9; + LUT2 com_tlm_u_tlm_tx_vc0_frm_seq_un4_bnpd_diff_axb_5 ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_bq_q[9]), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_npd_av[5]), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_un4_bnpd_diff_axb_5_3705) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_un4_bnpd_diff_axb_4.INIT = 4'h9; + LUT2 com_tlm_u_tlm_tx_vc0_frm_seq_un4_bnpd_diff_axb_4 ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_bq_q[8]), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_npd_av[4]), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_un4_bnpd_diff_axb_4_3706) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_un4_bnpd_diff_axb_3.INIT = 4'h9; + LUT2 com_tlm_u_tlm_tx_vc0_frm_seq_un4_bnpd_diff_axb_3 ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_bq_q[7]), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_npd_av[3]), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_un4_bnpd_diff_axb_3_3707) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_un4_bnpd_diff_axb_2.INIT = 4'h9; + LUT2 com_tlm_u_tlm_tx_vc0_frm_seq_un4_bnpd_diff_axb_2 ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_bq_q[6]), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_npd_av[2]), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_un4_bnpd_diff_axb_2_3708) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_un4_bnpd_diff_axb_1.INIT = 4'h9; + LUT2 com_tlm_u_tlm_tx_vc0_frm_seq_un4_bnpd_diff_axb_1 ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_bq_q[5]), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_npd_av[1]), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_un4_bnpd_diff_axb_1_3709) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_un4_bnpd_diff_axb_0.INIT = 4'h9; + LUT2 com_tlm_u_tlm_tx_vc0_frm_seq_un4_bnpd_diff_axb_0 ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_bq_q[4]), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_npd_av[0]), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_un4_bnpd_diff_axb_0_3710) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_un4_cpld_diff_axb_5.INIT = 4'h9; + LUT2 com_tlm_u_tlm_tx_vc0_frm_seq_un4_cpld_diff_axb_5 ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_bq_d[9]), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_cpld_av_5_), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_un4_cpld_diff_axb_5_3711) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_un4_cpld_diff_axb_4.INIT = 4'h9; + LUT2 com_tlm_u_tlm_tx_vc0_frm_seq_un4_cpld_diff_axb_4 ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_bq_d[8]), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_cpld_av_4_), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_un4_cpld_diff_axb_4_3712) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_un4_cpld_diff_axb_3.INIT = 4'h9; + LUT2 com_tlm_u_tlm_tx_vc0_frm_seq_un4_cpld_diff_axb_3 ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_bq_d[7]), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_cpld_av_3_), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_un4_cpld_diff_axb_3_3713) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_un4_cpld_diff_axb_2.INIT = 4'h9; + LUT2 com_tlm_u_tlm_tx_vc0_frm_seq_un4_cpld_diff_axb_2 ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_bq_d[6]), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_cpld_av_2_), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_un4_cpld_diff_axb_2_3714) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_un4_cpld_diff_axb_1.INIT = 4'h9; + LUT2 com_tlm_u_tlm_tx_vc0_frm_seq_un4_cpld_diff_axb_1 ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_bq_d[5]), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_cpld_av_1_), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_un4_cpld_diff_axb_1_3715) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_un4_cpld_diff_axb_0.INIT = 4'h9; + LUT2 com_tlm_u_tlm_tx_vc0_frm_seq_un4_cpld_diff_axb_0 ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_bq_d[4]), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_cpld_av_0_), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_un4_cpld_diff_axb_0_3716) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_un4_npd_diff_axb_5.INIT = 4'h9; + LUT2 com_tlm_u_tlm_tx_vc0_frm_seq_un4_npd_diff_axb_5 ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_bq_d[9]), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_npd_av[5]), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_un4_npd_diff_axb_5_3717) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_un4_npd_diff_axb_4.INIT = 4'h9; + LUT2 com_tlm_u_tlm_tx_vc0_frm_seq_un4_npd_diff_axb_4 ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_bq_d[8]), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_npd_av[4]), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_un4_npd_diff_axb_4_3718) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_un4_npd_diff_axb_3.INIT = 4'h9; + LUT2 com_tlm_u_tlm_tx_vc0_frm_seq_un4_npd_diff_axb_3 ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_bq_d[7]), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_npd_av[3]), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_un4_npd_diff_axb_3_3719) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_un4_npd_diff_axb_2.INIT = 4'h9; + LUT2 com_tlm_u_tlm_tx_vc0_frm_seq_un4_npd_diff_axb_2 ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_bq_d[6]), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_npd_av[2]), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_un4_npd_diff_axb_2_3720) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_un4_npd_diff_axb_1.INIT = 4'h9; + LUT2 com_tlm_u_tlm_tx_vc0_frm_seq_un4_npd_diff_axb_1 ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_bq_d[5]), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_npd_av[1]), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_un4_npd_diff_axb_1_3721) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_un4_npd_diff_axb_0.INIT = 4'h9; + LUT2 com_tlm_u_tlm_tx_vc0_frm_seq_un4_npd_diff_axb_0 ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_bq_d[4]), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_npd_av[0]), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_un4_npd_diff_axb_0_3722) + ); + GND com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_GND ( + .G(com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_GND_3723) + ); + SRLC16E com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_srlrow_0__srlcol_0__srlinst ( + .CE(com_tlm_u_tlm_tx_vc0_frame_vld), + .D(com_tlm_u_tlm_tx_vc0_tkn_buf_num[0]), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_shift_tap[0]), + .CLK(NlwRenamedSig_OI_trn_clk), + .Q15(NLW_com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_srlrow_0__srlcol_0__srlinst_Q15_UNCONNECTED), + .A0(com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_raddr_lo[0]), + .A1(com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_raddr_lo[1]), + .A2(com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_raddr_lo[2]), + .A3(com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_raddr_lo[3]) + ); + SRLC16E com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_srlrow_0__srlcol_9__srlinst ( + .CE(com_tlm_u_tlm_tx_vc0_frame_vld), + .D(com_tlm_u_tlm_tx_vc0_credits[5]), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_shift_tap[9]), + .CLK(NlwRenamedSig_OI_trn_clk), + .Q15(NLW_com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_srlrow_0__srlcol_9__srlinst_Q15_UNCONNECTED), + .A0(com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_raddr_lo[0]), + .A1(com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_raddr_lo[1]), + .A2(com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_raddr_lo[2]), + .A3(com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_raddr_lo[3]) + ); + SRLC16E com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_srlrow_0__srlcol_5__srlinst ( + .CE(com_tlm_u_tlm_tx_vc0_frame_vld), + .D(com_tlm_u_tlm_tx_vc0_credits[1]), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_shift_tap[5]), + .CLK(NlwRenamedSig_OI_trn_clk), + .Q15(NLW_com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_srlrow_0__srlcol_5__srlinst_Q15_UNCONNECTED), + .A0(com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_raddr_lo[0]), + .A1(com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_raddr_lo[1]), + .A2(com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_raddr_lo[2]), + .A3(com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_raddr_lo[3]) + ); + SRLC16E com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_srlrow_0__srlcol_1__srlinst ( + .CE(com_tlm_u_tlm_tx_vc0_frame_vld), + .D(com_tlm_u_tlm_tx_vc0_tkn_buf_num[1]), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_shift_tap[1]), + .CLK(NlwRenamedSig_OI_trn_clk), + .Q15(NLW_com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_srlrow_0__srlcol_1__srlinst_Q15_UNCONNECTED), + .A0(com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_raddr_lo[0]), + .A1(com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_raddr_lo[1]), + .A2(com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_raddr_lo[2]), + .A3(com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_raddr_lo[3]) + ); + SRLC16E com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_srlrow_0__srlcol_10__srlinst ( + .CE(com_tlm_u_tlm_tx_vc0_frame_vld), + .D(com_tlm_u_tlm_tx_vc0_no_payload), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_shift_tap[10]), + .CLK(NlwRenamedSig_OI_trn_clk), + .Q15(NLW_com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_srlrow_0__srlcol_10__srlinst_Q15_UNCONNECTED), + .A0(com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_raddr_lo[0]), + .A1(com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_raddr_lo[1]), + .A2(com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_raddr_lo[2]), + .A3(com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_raddr_lo[3]) + ); + SRLC16E com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_srlrow_0__srlcol_6__srlinst ( + .CE(com_tlm_u_tlm_tx_vc0_frame_vld), + .D(com_tlm_u_tlm_tx_vc0_credits[2]), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_shift_tap[6]), + .CLK(NlwRenamedSig_OI_trn_clk), + .Q15(NLW_com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_srlrow_0__srlcol_6__srlinst_Q15_UNCONNECTED), + .A0(com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_raddr_lo[0]), + .A1(com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_raddr_lo[1]), + .A2(com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_raddr_lo[2]), + .A3(com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_raddr_lo[3]) + ); + SRLC16E com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_srlrow_0__srlcol_2__srlinst ( + .CE(com_tlm_u_tlm_tx_vc0_frame_vld), + .D(com_tlm_u_tlm_tx_vc0_tkn_buf_num[2]), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_shift_tap[2]), + .CLK(NlwRenamedSig_OI_trn_clk), + .Q15(NLW_com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_srlrow_0__srlcol_2__srlinst_Q15_UNCONNECTED), + .A0(com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_raddr_lo[0]), + .A1(com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_raddr_lo[1]), + .A2(com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_raddr_lo[2]), + .A3(com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_raddr_lo[3]) + ); + SRLC16E com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_srlrow_0__srlcol_11__srlinst ( + .CE(com_tlm_u_tlm_tx_vc0_frame_vld), + .D(com_tlm_u_tlm_tx_vc0_cat[0]), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_shift_tap[11]), + .CLK(NlwRenamedSig_OI_trn_clk), + .Q15(NLW_com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_srlrow_0__srlcol_11__srlinst_Q15_UNCONNECTED), + .A0(com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_raddr_lo[0]), + .A1(com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_raddr_lo[1]), + .A2(com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_raddr_lo[2]), + .A3(com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_raddr_lo[3]) + ); + SRLC16E com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_srlrow_0__srlcol_7__srlinst ( + .CE(com_tlm_u_tlm_tx_vc0_frame_vld), + .D(com_tlm_u_tlm_tx_vc0_credits[3]), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_shift_tap[7]), + .CLK(NlwRenamedSig_OI_trn_clk), + .Q15(NLW_com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_srlrow_0__srlcol_7__srlinst_Q15_UNCONNECTED), + .A0(com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_raddr_lo[0]), + .A1(com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_raddr_lo[1]), + .A2(com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_raddr_lo[2]), + .A3(com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_raddr_lo[3]) + ); + SRLC16E com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_srlrow_0__srlcol_3__srlinst ( + .CE(com_tlm_u_tlm_tx_vc0_frame_vld), + .D(com_tlm_u_tlm_tx_vc0_tkn_buf_num[3]), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_shift_tap[3]), + .CLK(NlwRenamedSig_OI_trn_clk), + .Q15(NLW_com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_srlrow_0__srlcol_3__srlinst_Q15_UNCONNECTED), + .A0(com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_raddr_lo[0]), + .A1(com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_raddr_lo[1]), + .A2(com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_raddr_lo[2]), + .A3(com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_raddr_lo[3]) + ); + SRLC16E com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_srlrow_0__srlcol_12__srlinst ( + .CE(com_tlm_u_tlm_tx_vc0_frame_vld), + .D(com_tlm_u_tlm_tx_vc0_cat[1]), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_shift_tap[12]), + .CLK(NlwRenamedSig_OI_trn_clk), + .Q15(NLW_com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_srlrow_0__srlcol_12__srlinst_Q15_UNCONNECTED), + .A0(com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_raddr_lo[0]), + .A1(com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_raddr_lo[1]), + .A2(com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_raddr_lo[2]), + .A3(com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_raddr_lo[3]) + ); + SRLC16E com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_srlrow_0__srlcol_8__srlinst ( + .CE(com_tlm_u_tlm_tx_vc0_frame_vld), + .D(com_tlm_u_tlm_tx_vc0_credits[4]), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_shift_tap[8]), + .CLK(NlwRenamedSig_OI_trn_clk), + .Q15(NLW_com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_srlrow_0__srlcol_8__srlinst_Q15_UNCONNECTED), + .A0(com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_raddr_lo[0]), + .A1(com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_raddr_lo[1]), + .A2(com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_raddr_lo[2]), + .A3(com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_raddr_lo[3]) + ); + SRLC16E com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_srlrow_0__srlcol_4__srlinst ( + .CE(com_tlm_u_tlm_tx_vc0_frame_vld), + .D(com_tlm_u_tlm_tx_vc0_credits[0]), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_shift_tap[4]), + .CLK(NlwRenamedSig_OI_trn_clk), + .Q15(NLW_com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_srlrow_0__srlcol_4__srlinst_Q15_UNCONNECTED), + .A0(com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_raddr_lo[0]), + .A1(com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_raddr_lo[1]), + .A2(com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_raddr_lo[2]), + .A3(com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_raddr_lo[3]) + ); + FDS com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_raddr_lo_0_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_un1_raddr_lo_1_axb_0_3727), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_raddr_lo[0]), + .S(plm_link_up_i) + ); + FDS com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_raddr_lo_1_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_un1_raddr_lo_1_s_1_2), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_raddr_lo[1]), + .S(plm_link_up_i) + ); + FDS com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_raddr_lo_2_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_un1_raddr_lo_1_s_2_2), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_raddr_lo[2]), + .S(plm_link_up_i) + ); + FDS com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_raddr_lo_3_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_un1_raddr_lo_1_s_3_2), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_raddr_lo[3]), + .S(plm_link_up_i) + ); + FDRE com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_nxt_vld_o ( + .CE(com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_N_86416_i_3728), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_srl_wen), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_nxt_vld_o_1), + .R(plm_link_up_i) + ); + FDRE com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_vld_o ( + .CE(com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_N_62984_i_i_3734), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_N_59232_i_3730), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_oq_vld), + .R(plm_link_up_i) + ); + MUXCY_L com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_un1_raddr_lo_1_cry_0 ( + .CI(com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_GND_3723), + .DI(com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_raddr_lo[0]), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_un1_raddr_lo_1_cry_0_3724), + .S(com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_un1_raddr_lo_1_axb_0_3727) + ); + MUXCY_L com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_un1_raddr_lo_1_cry_1 ( + .CI(com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_un1_raddr_lo_1_cry_0_3724), + .DI(com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_raddr_lo[1]), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_un1_raddr_lo_1_cry_1_3725), + .S(com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_un1_raddr_lo_1_axb_1_3733) + ); + XORCY com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_un1_raddr_lo_1_s_1 ( + .CI(com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_un1_raddr_lo_1_cry_0_3724), + .LI(com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_un1_raddr_lo_1_axb_1_3733), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_un1_raddr_lo_1_s_1_2) + ); + MUXCY_L com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_un1_raddr_lo_1_cry_2 ( + .CI(com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_un1_raddr_lo_1_cry_1_3725), + .DI(com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_raddr_lo[2]), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_un1_raddr_lo_1_cry_2_3726), + .S(com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_un1_raddr_lo_1_axb_2_3732) + ); + XORCY com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_un1_raddr_lo_1_s_2 ( + .CI(com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_un1_raddr_lo_1_cry_1_3725), + .LI(com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_un1_raddr_lo_1_axb_2_3732), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_un1_raddr_lo_1_s_2_2) + ); + XORCY com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_un1_raddr_lo_1_s_3 ( + .CI(com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_un1_raddr_lo_1_cry_2_3726), + .LI(com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_un1_raddr_lo_1_axb_3_3731), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_un1_raddr_lo_1_s_3_2) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_raddr_en_0_o2.INIT = 4'h4; + LUT2 com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_raddr_en_0_o2 ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_oq_ren_3618), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_oq_vld), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_N_62984_i) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_un1_bkp_i_1_i_0_0_0_a2_0_2.INIT = 16'h0001; + LUT4 com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_un1_bkp_i_1_i_0_0_0_a2_0_2 ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_raddr_lo[0]), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_raddr_lo[1]), + .I2(com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_raddr_lo[2]), + .I3(com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_raddr_lo[3]), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_un1_bkp_i_1_i_0_0_0_a2_0_2_3729) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_un1_bkp_i_1_i_0_0_0_a2.INIT = 8'hC8; + LUT3 com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_un1_bkp_i_1_i_0_0_0_a2 ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_N_62984_i), + .I1(com_tlm_u_tlm_tx_vc0_frame_vld), + .I2(com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_nxt_vld_o_1), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_srl_wen) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_un1_raddr_lo_1_axb_0.INIT = 16'h6978; + LUT4 com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_un1_raddr_lo_1_axb_0 ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_N_62984_i), + .I1(com_tlm_u_tlm_tx_vc0_frame_vld), + .I2(com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_raddr_lo[0]), + .I3(com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_nxt_vld_o_1), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_un1_raddr_lo_1_axb_0_3727) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_N_86416_i.INIT = 8'hDC; + LUT3 com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_N_86416_i ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_N_62984_i), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_srl_wen), + .I2(com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_un1_bkp_i_1_i_0_0_0_a2_0_2_3729), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_N_86416_i_3728) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_N_59232_i.INIT = 4'hE; + LUT2_L com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_N_59232_i ( + .I0(com_tlm_u_tlm_tx_vc0_frame_vld), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_nxt_vld_o_1), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_N_59232_i_3730) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_data_bits_d_o_36_0_i_m2_i_m3_i_m3_0_12_.INIT = 8'hCA; + LUT3_L com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_data_bits_d_o_36_0_i_m2_i_m3_i_m3_0_12_ ( + .I0(com_tlm_u_tlm_tx_vc0_cat[1]), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_shift_tap[12]), + .I2(com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_nxt_vld_o_1), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_d_o_36_0_i_m2_i_m3_i_m3_0[12]) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_data_bits_d_o_36_0_i_m2_i_m3_i_m3_0_11_.INIT = 8'hCA; + LUT3_L com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_data_bits_d_o_36_0_i_m2_i_m3_i_m3_0_11_ ( + .I0(com_tlm_u_tlm_tx_vc0_cat[0]), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_shift_tap[11]), + .I2(com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_nxt_vld_o_1), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_d_o_36_0_i_m2_i_m3_i_m3_0[11]) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_data_bits_d_o_36_0_i_m2_i_m3_i_m3_0_10_.INIT = 8'hB8; + LUT3_L com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_data_bits_d_o_36_0_i_m2_i_m3_i_m3_0_10_ ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_shift_tap[10]), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_nxt_vld_o_1), + .I2(com_tlm_u_tlm_tx_vc0_no_payload), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_d_o_36_0_i_m2_i_m3_i_m3_0[10]) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_data_bits_d_o_36_0_i_m2_i_m3_i_m3_0_9_.INIT = 8'hCA; + LUT3_L com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_data_bits_d_o_36_0_i_m2_i_m3_i_m3_0_9_ ( + .I0(com_tlm_u_tlm_tx_vc0_credits[5]), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_shift_tap[9]), + .I2(com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_nxt_vld_o_1), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_d_o_36_0_i_m2_i_m3_i_m3_0[9]) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_data_bits_d_o_36_0_i_m2_i_m3_i_m3_0_8_.INIT = 8'hCA; + LUT3_L com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_data_bits_d_o_36_0_i_m2_i_m3_i_m3_0_8_ ( + .I0(com_tlm_u_tlm_tx_vc0_credits[4]), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_shift_tap[8]), + .I2(com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_nxt_vld_o_1), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_d_o_36_0_i_m2_i_m3_i_m3_0[8]) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_data_bits_d_o_36_0_i_m2_i_m3_i_m3_0_7_.INIT = 8'hCA; + LUT3_L com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_data_bits_d_o_36_0_i_m2_i_m3_i_m3_0_7_ ( + .I0(com_tlm_u_tlm_tx_vc0_credits[3]), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_shift_tap[7]), + .I2(com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_nxt_vld_o_1), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_d_o_36_0_i_m2_i_m3_i_m3_0[7]) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_data_bits_d_o_36_0_i_m2_i_m3_i_m3_0_6_.INIT = 8'hCA; + LUT3_L com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_data_bits_d_o_36_0_i_m2_i_m3_i_m3_0_6_ ( + .I0(com_tlm_u_tlm_tx_vc0_credits[2]), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_shift_tap[6]), + .I2(com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_nxt_vld_o_1), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_d_o_36_0_i_m2_i_m3_i_m3_0[6]) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_data_bits_d_o_36_0_i_m2_i_m3_i_m3_0_5_.INIT = 8'hCA; + LUT3_L com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_data_bits_d_o_36_0_i_m2_i_m3_i_m3_0_5_ ( + .I0(com_tlm_u_tlm_tx_vc0_credits[1]), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_shift_tap[5]), + .I2(com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_nxt_vld_o_1), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_d_o_36_0_i_m2_i_m3_i_m3_0[5]) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_data_bits_d_o_36_0_i_m2_i_m3_i_m3_0_4_.INIT = 8'hCA; + LUT3_L com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_data_bits_d_o_36_0_i_m2_i_m3_i_m3_0_4_ ( + .I0(com_tlm_u_tlm_tx_vc0_credits[0]), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_shift_tap[4]), + .I2(com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_nxt_vld_o_1), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_d_o_36_0_i_m2_i_m3_i_m3_0[4]) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_data_bits_d_o_36_0_i_m2_i_m3_i_m3_0_3_.INIT = 8'hB8; + LUT3_L com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_data_bits_d_o_36_0_i_m2_i_m3_i_m3_0_3_ ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_shift_tap[3]), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_nxt_vld_o_1), + .I2(com_tlm_u_tlm_tx_vc0_tkn_buf_num[3]), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_d_o_36_0_i_m2_i_m3_i_m3_0[3]) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_data_bits_d_o_36_0_i_m2_i_m3_i_m3_0_2_.INIT = 8'hB8; + LUT3_L com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_data_bits_d_o_36_0_i_m2_i_m3_i_m3_0_2_ ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_shift_tap[2]), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_nxt_vld_o_1), + .I2(com_tlm_u_tlm_tx_vc0_tkn_buf_num[2]), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_d_o_36_0_i_m2_i_m3_i_m3_0[2]) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_data_bits_d_o_36_0_i_m2_i_m3_i_m3_0_1_.INIT = 8'hB8; + LUT3_L com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_data_bits_d_o_36_0_i_m2_i_m3_i_m3_0_1_ ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_shift_tap[1]), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_nxt_vld_o_1), + .I2(com_tlm_u_tlm_tx_vc0_tkn_buf_num[1]), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_d_o_36_0_i_m2_i_m3_i_m3_0[1]) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_data_bits_d_o_36_0_i_m2_i_m3_i_m3_0_0_.INIT = 8'hB8; + LUT3_L com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_data_bits_d_o_36_0_i_m2_i_m3_i_m3_0_0_ ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_shift_tap[0]), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_nxt_vld_o_1), + .I2(com_tlm_u_tlm_tx_vc0_tkn_buf_num[0]), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_d_o_36_0_i_m2_i_m3_i_m3_0[0]) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_un1_raddr_lo_1_axb_3.INIT = 16'hE1F0; + LUT4_L com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_un1_raddr_lo_1_axb_3 ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_N_62984_i), + .I1(com_tlm_u_tlm_tx_vc0_frame_vld), + .I2(com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_raddr_lo[3]), + .I3(com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_nxt_vld_o_1), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_un1_raddr_lo_1_axb_3_3731) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_un1_raddr_lo_1_axb_2.INIT = 16'hE1F0; + LUT4_L com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_un1_raddr_lo_1_axb_2 ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_N_62984_i), + .I1(com_tlm_u_tlm_tx_vc0_frame_vld), + .I2(com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_raddr_lo[2]), + .I3(com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_nxt_vld_o_1), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_un1_raddr_lo_1_axb_2_3732) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_un1_raddr_lo_1_axb_1.INIT = 16'hE1F0; + LUT4_L com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_un1_raddr_lo_1_axb_1 ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_N_62984_i), + .I1(com_tlm_u_tlm_tx_vc0_frame_vld), + .I2(com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_raddr_lo[1]), + .I3(com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_nxt_vld_o_1), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_un1_raddr_lo_1_axb_1_3733) + ); + FDE com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_d_o_12_ ( + .CE(com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_N_62984_i_i_3734), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_d_o_36_0_i_m2_i_m3_i_m3_0[12]), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_oq_q[12]) + ); + FDE com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_d_o_11_ ( + .CE(com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_N_62984_i_i_3734), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_d_o_36_0_i_m2_i_m3_i_m3_0[11]), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_oq_q[11]) + ); + FDE com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_d_o_10_ ( + .CE(com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_N_62984_i_i_3734), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_d_o_36_0_i_m2_i_m3_i_m3_0[10]), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_bq_d[10]) + ); + FDE com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_d_o_9_ ( + .CE(com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_N_62984_i_i_3734), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_d_o_36_0_i_m2_i_m3_i_m3_0[9]), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_bq_d[9]) + ); + FDE com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_d_o_8_ ( + .CE(com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_N_62984_i_i_3734), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_d_o_36_0_i_m2_i_m3_i_m3_0[8]), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_bq_d[8]) + ); + FDE com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_d_o_7_ ( + .CE(com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_N_62984_i_i_3734), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_d_o_36_0_i_m2_i_m3_i_m3_0[7]), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_bq_d[7]) + ); + FDE com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_d_o_6_ ( + .CE(com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_N_62984_i_i_3734), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_d_o_36_0_i_m2_i_m3_i_m3_0[6]), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_bq_d[6]) + ); + FDE com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_d_o_5_ ( + .CE(com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_N_62984_i_i_3734), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_d_o_36_0_i_m2_i_m3_i_m3_0[5]), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_bq_d[5]) + ); + FDE com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_d_o_4_ ( + .CE(com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_N_62984_i_i_3734), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_d_o_36_0_i_m2_i_m3_i_m3_0[4]), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_bq_d[4]) + ); + FDE com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_d_o_3_ ( + .CE(com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_N_62984_i_i_3734), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_d_o_36_0_i_m2_i_m3_i_m3_0[3]), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_bq_d[3]) + ); + FDE com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_d_o_2_ ( + .CE(com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_N_62984_i_i_3734), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_d_o_36_0_i_m2_i_m3_i_m3_0[2]), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_bq_d[2]) + ); + FDE com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_d_o_1_ ( + .CE(com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_N_62984_i_i_3734), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_d_o_36_0_i_m2_i_m3_i_m3_0[1]), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_bq_d[1]) + ); + FDE com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_d_o_0_ ( + .CE(com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_N_62984_i_i_3734), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_d_o_36_0_i_m2_i_m3_i_m3_0[0]), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_bq_d[0]) + ); + INV com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_N_62984_i_i ( + .I(com_tlm_u_tlm_tx_vc0_frm_seq_N_62984_i), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_oq_fifo_N_62984_i_i_3734) + ); + GND com_tlm_u_tlm_tx_vc0_frm_seq_bq_fifo_GND ( + .G(com_tlm_u_tlm_tx_vc0_frm_seq_bq_fifo_GND_3735) + ); + SRLC16E com_tlm_u_tlm_tx_vc0_frm_seq_bq_fifo_srlrow_0__srlcol_0__srlinst ( + .CE(com_tlm_u_tlm_tx_vc0_frm_seq_bq_wen_3676), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_bq_d[0]), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_bq_fifo_shift_tap[0]), + .CLK(NlwRenamedSig_OI_trn_clk), + .Q15(NLW_com_tlm_u_tlm_tx_vc0_frm_seq_bq_fifo_srlrow_0__srlcol_0__srlinst_Q15_UNCONNECTED), + .A0(com_tlm_u_tlm_tx_vc0_frm_seq_bq_fifo_raddr_lo[0]), + .A1(com_tlm_u_tlm_tx_vc0_frm_seq_bq_fifo_raddr_lo[1]), + .A2(com_tlm_u_tlm_tx_vc0_frm_seq_bq_fifo_raddr_lo[2]), + .A3(com_tlm_u_tlm_tx_vc0_frm_seq_bq_fifo_raddr_lo[3]) + ); + SRLC16E com_tlm_u_tlm_tx_vc0_frm_seq_bq_fifo_srlrow_0__srlcol_5__srlinst ( + .CE(com_tlm_u_tlm_tx_vc0_frm_seq_bq_wen_3676), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_bq_d[5]), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_bq_fifo_shift_tap[5]), + .CLK(NlwRenamedSig_OI_trn_clk), + .Q15(NLW_com_tlm_u_tlm_tx_vc0_frm_seq_bq_fifo_srlrow_0__srlcol_5__srlinst_Q15_UNCONNECTED), + .A0(com_tlm_u_tlm_tx_vc0_frm_seq_bq_fifo_raddr_lo[0]), + .A1(com_tlm_u_tlm_tx_vc0_frm_seq_bq_fifo_raddr_lo[1]), + .A2(com_tlm_u_tlm_tx_vc0_frm_seq_bq_fifo_raddr_lo[2]), + .A3(com_tlm_u_tlm_tx_vc0_frm_seq_bq_fifo_raddr_lo[3]) + ); + SRLC16E com_tlm_u_tlm_tx_vc0_frm_seq_bq_fifo_srlrow_0__srlcol_9__srlinst ( + .CE(com_tlm_u_tlm_tx_vc0_frm_seq_bq_wen_3676), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_bq_d[9]), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_bq_fifo_shift_tap[9]), + .CLK(NlwRenamedSig_OI_trn_clk), + .Q15(NLW_com_tlm_u_tlm_tx_vc0_frm_seq_bq_fifo_srlrow_0__srlcol_9__srlinst_Q15_UNCONNECTED), + .A0(com_tlm_u_tlm_tx_vc0_frm_seq_bq_fifo_raddr_lo[0]), + .A1(com_tlm_u_tlm_tx_vc0_frm_seq_bq_fifo_raddr_lo[1]), + .A2(com_tlm_u_tlm_tx_vc0_frm_seq_bq_fifo_raddr_lo[2]), + .A3(com_tlm_u_tlm_tx_vc0_frm_seq_bq_fifo_raddr_lo[3]) + ); + SRLC16E com_tlm_u_tlm_tx_vc0_frm_seq_bq_fifo_srlrow_0__srlcol_10__srlinst ( + .CE(com_tlm_u_tlm_tx_vc0_frm_seq_bq_wen_3676), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_bq_d[10]), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_bq_fifo_shift_tap[10]), + .CLK(NlwRenamedSig_OI_trn_clk), + .Q15(NLW_com_tlm_u_tlm_tx_vc0_frm_seq_bq_fifo_srlrow_0__srlcol_10__srlinst_Q15_UNCONNECTED), + .A0(com_tlm_u_tlm_tx_vc0_frm_seq_bq_fifo_raddr_lo[0]), + .A1(com_tlm_u_tlm_tx_vc0_frm_seq_bq_fifo_raddr_lo[1]), + .A2(com_tlm_u_tlm_tx_vc0_frm_seq_bq_fifo_raddr_lo[2]), + .A3(com_tlm_u_tlm_tx_vc0_frm_seq_bq_fifo_raddr_lo[3]) + ); + SRLC16E com_tlm_u_tlm_tx_vc0_frm_seq_bq_fifo_srlrow_0__srlcol_6__srlinst ( + .CE(com_tlm_u_tlm_tx_vc0_frm_seq_bq_wen_3676), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_bq_d[6]), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_bq_fifo_shift_tap[6]), + .CLK(NlwRenamedSig_OI_trn_clk), + .Q15(NLW_com_tlm_u_tlm_tx_vc0_frm_seq_bq_fifo_srlrow_0__srlcol_6__srlinst_Q15_UNCONNECTED), + .A0(com_tlm_u_tlm_tx_vc0_frm_seq_bq_fifo_raddr_lo[0]), + .A1(com_tlm_u_tlm_tx_vc0_frm_seq_bq_fifo_raddr_lo[1]), + .A2(com_tlm_u_tlm_tx_vc0_frm_seq_bq_fifo_raddr_lo[2]), + .A3(com_tlm_u_tlm_tx_vc0_frm_seq_bq_fifo_raddr_lo[3]) + ); + SRLC16E com_tlm_u_tlm_tx_vc0_frm_seq_bq_fifo_srlrow_0__srlcol_7__srlinst ( + .CE(com_tlm_u_tlm_tx_vc0_frm_seq_bq_wen_3676), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_bq_d[7]), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_bq_fifo_shift_tap[7]), + .CLK(NlwRenamedSig_OI_trn_clk), + .Q15(NLW_com_tlm_u_tlm_tx_vc0_frm_seq_bq_fifo_srlrow_0__srlcol_7__srlinst_Q15_UNCONNECTED), + .A0(com_tlm_u_tlm_tx_vc0_frm_seq_bq_fifo_raddr_lo[0]), + .A1(com_tlm_u_tlm_tx_vc0_frm_seq_bq_fifo_raddr_lo[1]), + .A2(com_tlm_u_tlm_tx_vc0_frm_seq_bq_fifo_raddr_lo[2]), + .A3(com_tlm_u_tlm_tx_vc0_frm_seq_bq_fifo_raddr_lo[3]) + ); + SRLC16E com_tlm_u_tlm_tx_vc0_frm_seq_bq_fifo_srlrow_0__srlcol_4__srlinst ( + .CE(com_tlm_u_tlm_tx_vc0_frm_seq_bq_wen_3676), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_bq_d[4]), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_bq_fifo_shift_tap[4]), + .CLK(NlwRenamedSig_OI_trn_clk), + .Q15(NLW_com_tlm_u_tlm_tx_vc0_frm_seq_bq_fifo_srlrow_0__srlcol_4__srlinst_Q15_UNCONNECTED), + .A0(com_tlm_u_tlm_tx_vc0_frm_seq_bq_fifo_raddr_lo[0]), + .A1(com_tlm_u_tlm_tx_vc0_frm_seq_bq_fifo_raddr_lo[1]), + .A2(com_tlm_u_tlm_tx_vc0_frm_seq_bq_fifo_raddr_lo[2]), + .A3(com_tlm_u_tlm_tx_vc0_frm_seq_bq_fifo_raddr_lo[3]) + ); + SRLC16E com_tlm_u_tlm_tx_vc0_frm_seq_bq_fifo_srlrow_0__srlcol_3__srlinst ( + .CE(com_tlm_u_tlm_tx_vc0_frm_seq_bq_wen_3676), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_bq_d[3]), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_bq_fifo_shift_tap[3]), + .CLK(NlwRenamedSig_OI_trn_clk), + .Q15(NLW_com_tlm_u_tlm_tx_vc0_frm_seq_bq_fifo_srlrow_0__srlcol_3__srlinst_Q15_UNCONNECTED), + .A0(com_tlm_u_tlm_tx_vc0_frm_seq_bq_fifo_raddr_lo[0]), + .A1(com_tlm_u_tlm_tx_vc0_frm_seq_bq_fifo_raddr_lo[1]), + .A2(com_tlm_u_tlm_tx_vc0_frm_seq_bq_fifo_raddr_lo[2]), + .A3(com_tlm_u_tlm_tx_vc0_frm_seq_bq_fifo_raddr_lo[3]) + ); + SRLC16E com_tlm_u_tlm_tx_vc0_frm_seq_bq_fifo_srlrow_0__srlcol_8__srlinst ( + .CE(com_tlm_u_tlm_tx_vc0_frm_seq_bq_wen_3676), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_bq_d[8]), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_bq_fifo_shift_tap[8]), + .CLK(NlwRenamedSig_OI_trn_clk), + .Q15(NLW_com_tlm_u_tlm_tx_vc0_frm_seq_bq_fifo_srlrow_0__srlcol_8__srlinst_Q15_UNCONNECTED), + .A0(com_tlm_u_tlm_tx_vc0_frm_seq_bq_fifo_raddr_lo[0]), + .A1(com_tlm_u_tlm_tx_vc0_frm_seq_bq_fifo_raddr_lo[1]), + .A2(com_tlm_u_tlm_tx_vc0_frm_seq_bq_fifo_raddr_lo[2]), + .A3(com_tlm_u_tlm_tx_vc0_frm_seq_bq_fifo_raddr_lo[3]) + ); + SRLC16E com_tlm_u_tlm_tx_vc0_frm_seq_bq_fifo_srlrow_0__srlcol_1__srlinst ( + .CE(com_tlm_u_tlm_tx_vc0_frm_seq_bq_wen_3676), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_bq_d[1]), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_bq_fifo_shift_tap[1]), + .CLK(NlwRenamedSig_OI_trn_clk), + .Q15(NLW_com_tlm_u_tlm_tx_vc0_frm_seq_bq_fifo_srlrow_0__srlcol_1__srlinst_Q15_UNCONNECTED), + .A0(com_tlm_u_tlm_tx_vc0_frm_seq_bq_fifo_raddr_lo[0]), + .A1(com_tlm_u_tlm_tx_vc0_frm_seq_bq_fifo_raddr_lo[1]), + .A2(com_tlm_u_tlm_tx_vc0_frm_seq_bq_fifo_raddr_lo[2]), + .A3(com_tlm_u_tlm_tx_vc0_frm_seq_bq_fifo_raddr_lo[3]) + ); + SRLC16E com_tlm_u_tlm_tx_vc0_frm_seq_bq_fifo_srlrow_0__srlcol_2__srlinst ( + .CE(com_tlm_u_tlm_tx_vc0_frm_seq_bq_wen_3676), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_bq_d[2]), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_bq_fifo_shift_tap[2]), + .CLK(NlwRenamedSig_OI_trn_clk), + .Q15(NLW_com_tlm_u_tlm_tx_vc0_frm_seq_bq_fifo_srlrow_0__srlcol_2__srlinst_Q15_UNCONNECTED), + .A0(com_tlm_u_tlm_tx_vc0_frm_seq_bq_fifo_raddr_lo[0]), + .A1(com_tlm_u_tlm_tx_vc0_frm_seq_bq_fifo_raddr_lo[1]), + .A2(com_tlm_u_tlm_tx_vc0_frm_seq_bq_fifo_raddr_lo[2]), + .A3(com_tlm_u_tlm_tx_vc0_frm_seq_bq_fifo_raddr_lo[3]) + ); + FDS com_tlm_u_tlm_tx_vc0_frm_seq_bq_fifo_raddr_lo_0_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_bq_fifo_un1_raddr_lo_1_axb_0_3741), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_bq_fifo_raddr_lo[0]), + .S(plm_link_up_i) + ); + FDS com_tlm_u_tlm_tx_vc0_frm_seq_bq_fifo_raddr_lo_1_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_bq_fifo_un1_raddr_lo_1_s_1_3), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_bq_fifo_raddr_lo[1]), + .S(plm_link_up_i) + ); + FDS com_tlm_u_tlm_tx_vc0_frm_seq_bq_fifo_raddr_lo_2_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_bq_fifo_un1_raddr_lo_1_s_2_3), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_bq_fifo_raddr_lo[2]), + .S(plm_link_up_i) + ); + FDS com_tlm_u_tlm_tx_vc0_frm_seq_bq_fifo_raddr_lo_3_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_bq_fifo_un1_raddr_lo_1_s_3_3), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_bq_fifo_raddr_lo[3]), + .S(plm_link_up_i) + ); + FDRE com_tlm_u_tlm_tx_vc0_frm_seq_bq_fifo_nxt_vld_o ( + .CE(com_tlm_u_tlm_tx_vc0_frm_seq_bq_fifo_N_86367_i_3739), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_bq_wen_3676), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_bq_fifo_nxt_vld_o_0), + .R(plm_link_up_i) + ); + FDRE com_tlm_u_tlm_tx_vc0_frm_seq_bq_fifo_vld_o ( + .CE(com_tlm_u_tlm_tx_vc0_frm_seq_bq_fifo_N_56063_i_i_3745), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_bq_fifo_nxt_vld_o_0), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_bq_vld), + .R(plm_link_up_i) + ); + MUXCY_L com_tlm_u_tlm_tx_vc0_frm_seq_bq_fifo_un1_raddr_lo_1_cry_0 ( + .CI(com_tlm_u_tlm_tx_vc0_frm_seq_bq_fifo_GND_3735), + .DI(com_tlm_u_tlm_tx_vc0_frm_seq_bq_fifo_raddr_lo[0]), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_bq_fifo_un1_raddr_lo_1_cry_0_3736), + .S(com_tlm_u_tlm_tx_vc0_frm_seq_bq_fifo_un1_raddr_lo_1_axb_0_3741) + ); + MUXCY_L com_tlm_u_tlm_tx_vc0_frm_seq_bq_fifo_un1_raddr_lo_1_cry_1 ( + .CI(com_tlm_u_tlm_tx_vc0_frm_seq_bq_fifo_un1_raddr_lo_1_cry_0_3736), + .DI(com_tlm_u_tlm_tx_vc0_frm_seq_bq_fifo_raddr_lo[1]), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_bq_fifo_un1_raddr_lo_1_cry_1_3737), + .S(com_tlm_u_tlm_tx_vc0_frm_seq_bq_fifo_un1_raddr_lo_1_axb_1_3744) + ); + XORCY com_tlm_u_tlm_tx_vc0_frm_seq_bq_fifo_un1_raddr_lo_1_s_1 ( + .CI(com_tlm_u_tlm_tx_vc0_frm_seq_bq_fifo_un1_raddr_lo_1_cry_0_3736), + .LI(com_tlm_u_tlm_tx_vc0_frm_seq_bq_fifo_un1_raddr_lo_1_axb_1_3744), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_bq_fifo_un1_raddr_lo_1_s_1_3) + ); + MUXCY_L com_tlm_u_tlm_tx_vc0_frm_seq_bq_fifo_un1_raddr_lo_1_cry_2 ( + .CI(com_tlm_u_tlm_tx_vc0_frm_seq_bq_fifo_un1_raddr_lo_1_cry_1_3737), + .DI(com_tlm_u_tlm_tx_vc0_frm_seq_bq_fifo_raddr_lo[2]), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_bq_fifo_un1_raddr_lo_1_cry_2_3738), + .S(com_tlm_u_tlm_tx_vc0_frm_seq_bq_fifo_un1_raddr_lo_1_axb_2_3743) + ); + XORCY com_tlm_u_tlm_tx_vc0_frm_seq_bq_fifo_un1_raddr_lo_1_s_2 ( + .CI(com_tlm_u_tlm_tx_vc0_frm_seq_bq_fifo_un1_raddr_lo_1_cry_1_3737), + .LI(com_tlm_u_tlm_tx_vc0_frm_seq_bq_fifo_un1_raddr_lo_1_axb_2_3743), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_bq_fifo_un1_raddr_lo_1_s_2_3) + ); + XORCY com_tlm_u_tlm_tx_vc0_frm_seq_bq_fifo_un1_raddr_lo_1_s_3 ( + .CI(com_tlm_u_tlm_tx_vc0_frm_seq_bq_fifo_un1_raddr_lo_1_cry_2_3738), + .LI(com_tlm_u_tlm_tx_vc0_frm_seq_bq_fifo_un1_raddr_lo_1_axb_3_3742), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_bq_fifo_un1_raddr_lo_1_s_3_3) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_bq_fifo_un1_bkp_i_1_i_0_0_0_0_o3.INIT = 4'h4; + LUT2 com_tlm_u_tlm_tx_vc0_frm_seq_bq_fifo_un1_bkp_i_1_i_0_0_0_0_o3 ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_bq_ren_3675), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_bq_vld), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_bq_fifo_N_56063_i) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_bq_fifo_un1_bkp_i_1_i_0_0_0_0_a2_2.INIT = 16'h0001; + LUT4 com_tlm_u_tlm_tx_vc0_frm_seq_bq_fifo_un1_bkp_i_1_i_0_0_0_0_a2_2 ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_bq_fifo_raddr_lo[0]), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_bq_fifo_raddr_lo[1]), + .I2(com_tlm_u_tlm_tx_vc0_frm_seq_bq_fifo_raddr_lo[2]), + .I3(com_tlm_u_tlm_tx_vc0_frm_seq_bq_fifo_raddr_lo[3]), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_bq_fifo_un1_bkp_i_1_i_0_0_0_0_a2_2_3740) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_bq_fifo_N_86367_i.INIT = 8'hF4; + LUT3 com_tlm_u_tlm_tx_vc0_frm_seq_bq_fifo_N_86367_i ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_bq_fifo_N_56063_i), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_bq_fifo_un1_bkp_i_1_i_0_0_0_0_a2_2_3740), + .I2(com_tlm_u_tlm_tx_vc0_frm_seq_bq_wen_3676), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_bq_fifo_N_86367_i_3739) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_bq_fifo_un1_raddr_lo_1_axb_0.INIT = 16'h693C; + LUT4 com_tlm_u_tlm_tx_vc0_frm_seq_bq_fifo_un1_raddr_lo_1_axb_0 ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_bq_fifo_N_56063_i), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_bq_fifo_raddr_lo[0]), + .I2(com_tlm_u_tlm_tx_vc0_frm_seq_bq_wen_3676), + .I3(com_tlm_u_tlm_tx_vc0_frm_seq_bq_fifo_nxt_vld_o_0), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_bq_fifo_un1_raddr_lo_1_axb_0_3741) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_bq_fifo_un1_raddr_lo_1_axb_3.INIT = 16'hC9CC; + LUT4_L com_tlm_u_tlm_tx_vc0_frm_seq_bq_fifo_un1_raddr_lo_1_axb_3 ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_bq_fifo_N_56063_i), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_bq_fifo_raddr_lo[3]), + .I2(com_tlm_u_tlm_tx_vc0_frm_seq_bq_wen_3676), + .I3(com_tlm_u_tlm_tx_vc0_frm_seq_bq_fifo_nxt_vld_o_0), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_bq_fifo_un1_raddr_lo_1_axb_3_3742) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_bq_fifo_un1_raddr_lo_1_axb_2.INIT = 16'hC9CC; + LUT4_L com_tlm_u_tlm_tx_vc0_frm_seq_bq_fifo_un1_raddr_lo_1_axb_2 ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_bq_fifo_N_56063_i), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_bq_fifo_raddr_lo[2]), + .I2(com_tlm_u_tlm_tx_vc0_frm_seq_bq_wen_3676), + .I3(com_tlm_u_tlm_tx_vc0_frm_seq_bq_fifo_nxt_vld_o_0), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_bq_fifo_un1_raddr_lo_1_axb_2_3743) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_bq_fifo_un1_raddr_lo_1_axb_1.INIT = 16'hC9CC; + LUT4_L com_tlm_u_tlm_tx_vc0_frm_seq_bq_fifo_un1_raddr_lo_1_axb_1 ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_bq_fifo_N_56063_i), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_bq_fifo_raddr_lo[1]), + .I2(com_tlm_u_tlm_tx_vc0_frm_seq_bq_wen_3676), + .I3(com_tlm_u_tlm_tx_vc0_frm_seq_bq_fifo_nxt_vld_o_0), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_bq_fifo_un1_raddr_lo_1_axb_1_3744) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_bq_fifo_N_56063_i_i.INIT = 4'hD; + LUT2 com_tlm_u_tlm_tx_vc0_frm_seq_bq_fifo_N_56063_i_i ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_bq_vld), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_bq_ren_3675), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_bq_fifo_N_56063_i_i_3745) + ); + FDE com_tlm_u_tlm_tx_vc0_frm_seq_bq_fifo_d_o_10_ ( + .CE(com_tlm_u_tlm_tx_vc0_frm_seq_bq_fifo_N_56063_i_i_3745), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_bq_fifo_shift_tap[10]), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_bq_q[10]) + ); + FDE com_tlm_u_tlm_tx_vc0_frm_seq_bq_fifo_d_o_9_ ( + .CE(com_tlm_u_tlm_tx_vc0_frm_seq_bq_fifo_N_56063_i_i_3745), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_bq_fifo_shift_tap[9]), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_bq_q[9]) + ); + FDE com_tlm_u_tlm_tx_vc0_frm_seq_bq_fifo_d_o_8_ ( + .CE(com_tlm_u_tlm_tx_vc0_frm_seq_bq_fifo_N_56063_i_i_3745), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_bq_fifo_shift_tap[8]), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_bq_q[8]) + ); + FDE com_tlm_u_tlm_tx_vc0_frm_seq_bq_fifo_d_o_7_ ( + .CE(com_tlm_u_tlm_tx_vc0_frm_seq_bq_fifo_N_56063_i_i_3745), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_bq_fifo_shift_tap[7]), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_bq_q[7]) + ); + FDE com_tlm_u_tlm_tx_vc0_frm_seq_bq_fifo_d_o_6_ ( + .CE(com_tlm_u_tlm_tx_vc0_frm_seq_bq_fifo_N_56063_i_i_3745), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_bq_fifo_shift_tap[6]), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_bq_q[6]) + ); + FDE com_tlm_u_tlm_tx_vc0_frm_seq_bq_fifo_d_o_5_ ( + .CE(com_tlm_u_tlm_tx_vc0_frm_seq_bq_fifo_N_56063_i_i_3745), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_bq_fifo_shift_tap[5]), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_bq_q[5]) + ); + FDE com_tlm_u_tlm_tx_vc0_frm_seq_bq_fifo_d_o_4_ ( + .CE(com_tlm_u_tlm_tx_vc0_frm_seq_bq_fifo_N_56063_i_i_3745), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_bq_fifo_shift_tap[4]), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_bq_q[4]) + ); + FDE com_tlm_u_tlm_tx_vc0_frm_seq_bq_fifo_d_o_3_ ( + .CE(com_tlm_u_tlm_tx_vc0_frm_seq_bq_fifo_N_56063_i_i_3745), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_bq_fifo_shift_tap[3]), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_bq_q[3]) + ); + FDE com_tlm_u_tlm_tx_vc0_frm_seq_bq_fifo_d_o_2_ ( + .CE(com_tlm_u_tlm_tx_vc0_frm_seq_bq_fifo_N_56063_i_i_3745), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_bq_fifo_shift_tap[2]), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_bq_q[2]) + ); + FDE com_tlm_u_tlm_tx_vc0_frm_seq_bq_fifo_d_o_1_ ( + .CE(com_tlm_u_tlm_tx_vc0_frm_seq_bq_fifo_N_56063_i_i_3745), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_bq_fifo_shift_tap[1]), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_bq_q[1]) + ); + FDE com_tlm_u_tlm_tx_vc0_frm_seq_bq_fifo_d_o_0_ ( + .CE(com_tlm_u_tlm_tx_vc0_frm_seq_bq_fifo_N_56063_i_i_3745), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_bq_fifo_shift_tap[0]), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_bq_q[0]) + ); + GND com_tlm_u_tlm_tx_vc0_frm_seq_sq_fifo_GND ( + .G(com_tlm_u_tlm_tx_vc0_frm_seq_sq_fifo_GND_3746) + ); + SRLC16E com_tlm_u_tlm_tx_vc0_frm_seq_sq_fifo_srlrow_0__srlcol_0__srlinst ( + .CE(com_tlm_u_tlm_tx_vc0_frm_seq_sq_wen_3693), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_sq_d[0]), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_sq_fifo_shift_tap[0]), + .CLK(NlwRenamedSig_OI_trn_clk), + .Q15(NLW_com_tlm_u_tlm_tx_vc0_frm_seq_sq_fifo_srlrow_0__srlcol_0__srlinst_Q15_UNCONNECTED), + .A0(com_tlm_u_tlm_tx_vc0_frm_seq_sq_fifo_raddr_lo[0]), + .A1(com_tlm_u_tlm_tx_vc0_frm_seq_sq_fifo_raddr_lo[1]), + .A2(com_tlm_u_tlm_tx_vc0_frm_seq_sq_fifo_GND_3746), + .A3(com_tlm_u_tlm_tx_vc0_frm_seq_sq_fifo_GND_3746) + ); + SRLC16E com_tlm_u_tlm_tx_vc0_frm_seq_sq_fifo_srlrow_0__srlcol_3__srlinst ( + .CE(com_tlm_u_tlm_tx_vc0_frm_seq_sq_wen_3693), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_sq_d[3]), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_sq_fifo_shift_tap[3]), + .CLK(NlwRenamedSig_OI_trn_clk), + .Q15(NLW_com_tlm_u_tlm_tx_vc0_frm_seq_sq_fifo_srlrow_0__srlcol_3__srlinst_Q15_UNCONNECTED), + .A0(com_tlm_u_tlm_tx_vc0_frm_seq_sq_fifo_raddr_lo[0]), + .A1(com_tlm_u_tlm_tx_vc0_frm_seq_sq_fifo_raddr_lo[1]), + .A2(com_tlm_u_tlm_tx_vc0_frm_seq_sq_fifo_GND_3746), + .A3(com_tlm_u_tlm_tx_vc0_frm_seq_sq_fifo_GND_3746) + ); + SRLC16E com_tlm_u_tlm_tx_vc0_frm_seq_sq_fifo_srlrow_0__srlcol_2__srlinst ( + .CE(com_tlm_u_tlm_tx_vc0_frm_seq_sq_wen_3693), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_sq_d[2]), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_sq_fifo_shift_tap[2]), + .CLK(NlwRenamedSig_OI_trn_clk), + .Q15(NLW_com_tlm_u_tlm_tx_vc0_frm_seq_sq_fifo_srlrow_0__srlcol_2__srlinst_Q15_UNCONNECTED), + .A0(com_tlm_u_tlm_tx_vc0_frm_seq_sq_fifo_raddr_lo[0]), + .A1(com_tlm_u_tlm_tx_vc0_frm_seq_sq_fifo_raddr_lo[1]), + .A2(com_tlm_u_tlm_tx_vc0_frm_seq_sq_fifo_GND_3746), + .A3(com_tlm_u_tlm_tx_vc0_frm_seq_sq_fifo_GND_3746) + ); + SRLC16E com_tlm_u_tlm_tx_vc0_frm_seq_sq_fifo_srlrow_0__srlcol_1__srlinst ( + .CE(com_tlm_u_tlm_tx_vc0_frm_seq_sq_wen_3693), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_sq_d[1]), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_sq_fifo_shift_tap[1]), + .CLK(NlwRenamedSig_OI_trn_clk), + .Q15(NLW_com_tlm_u_tlm_tx_vc0_frm_seq_sq_fifo_srlrow_0__srlcol_1__srlinst_Q15_UNCONNECTED), + .A0(com_tlm_u_tlm_tx_vc0_frm_seq_sq_fifo_raddr_lo[0]), + .A1(com_tlm_u_tlm_tx_vc0_frm_seq_sq_fifo_raddr_lo[1]), + .A2(com_tlm_u_tlm_tx_vc0_frm_seq_sq_fifo_GND_3746), + .A3(com_tlm_u_tlm_tx_vc0_frm_seq_sq_fifo_GND_3746) + ); + FDS com_tlm_u_tlm_tx_vc0_frm_seq_sq_fifo_raddr_lo_0_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_sq_fifo_un1_raddr_lo_1_axb_0_3750), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_sq_fifo_raddr_lo[0]), + .S(plm_link_up_i) + ); + FDS com_tlm_u_tlm_tx_vc0_frm_seq_sq_fifo_raddr_lo_1_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_sq_fifo_un1_raddr_lo_1_s_1_4), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_sq_fifo_raddr_lo[1]), + .S(plm_link_up_i) + ); + FDS com_tlm_u_tlm_tx_vc0_frm_seq_sq_fifo_raddr_lo_2_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_sq_fifo_un1_raddr_lo_1_s_2_4), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_sq_fifo_raddr_lo[2]), + .S(plm_link_up_i) + ); + FDS com_tlm_u_tlm_tx_vc0_frm_seq_sq_fifo_raddr_lo_3_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_sq_fifo_un1_raddr_lo_1_s_3_4), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_sq_fifo_raddr_lo[3]), + .S(plm_link_up_i) + ); + FDRE com_tlm_u_tlm_tx_vc0_frm_seq_sq_fifo_nxt_vld_o ( + .CE(com_tlm_u_tlm_tx_vc0_frm_seq_sq_fifo_N_87187_i_3751), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_sq_fifo_srl_wen), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_sq_nxt_vld), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_tx_vc0_frm_seq_sq_fifo_ct_o_0_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_sq_fifo_un1_ct_o_axb0_3757), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_sq_cnt[0]), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_tx_vc0_frm_seq_sq_fifo_ct_o_1_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_sq_fifo_un1_ct_o_axbxc1_3756), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_sq_cnt[1]), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_tx_vc0_frm_seq_sq_fifo_ct_o_2_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_sq_fifo_un1_ct_o_axbxc2_3754), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_sq_cnt[2]), + .R(plm_link_up_i) + ); + FDRE com_tlm_u_tlm_tx_vc0_frm_seq_sq_fifo_vld_o ( + .CE(com_tlm_u_tlm_tx_vc0_frm_seq_sq_fifo_N_56061_i_i_3761), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_sq_fifo_N_59263_i_3753), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_sq_vld), + .R(plm_link_up_i) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_sq_fifo_un1_ct_o_p4.INIT = 16'hEC80; + LUT4_L com_tlm_u_tlm_tx_vc0_frm_seq_sq_fifo_un1_ct_o_p4 ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_sq_fifo_N_56520_i_i), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_sq_fifo_un1_ct_o217_0_a2_0_a2_0_a2_0_a2[1]), + .I2(com_tlm_u_tlm_tx_vc0_frm_seq_sq_cnt[0]), + .I3(com_tlm_u_tlm_tx_vc0_frm_seq_sq_cnt[1]), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_sq_fifo_un1_ct_o_p4_3755) + ); + MUXCY_L com_tlm_u_tlm_tx_vc0_frm_seq_sq_fifo_un1_raddr_lo_1_cry_0 ( + .CI(com_tlm_u_tlm_tx_vc0_frm_seq_sq_fifo_GND_3746), + .DI(com_tlm_u_tlm_tx_vc0_frm_seq_sq_fifo_raddr_lo[0]), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_sq_fifo_un1_raddr_lo_1_cry_0_3747), + .S(com_tlm_u_tlm_tx_vc0_frm_seq_sq_fifo_un1_raddr_lo_1_axb_0_3750) + ); + MUXCY_L com_tlm_u_tlm_tx_vc0_frm_seq_sq_fifo_un1_raddr_lo_1_cry_1 ( + .CI(com_tlm_u_tlm_tx_vc0_frm_seq_sq_fifo_un1_raddr_lo_1_cry_0_3747), + .DI(com_tlm_u_tlm_tx_vc0_frm_seq_sq_fifo_raddr_lo[1]), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_sq_fifo_un1_raddr_lo_1_cry_1_3748), + .S(com_tlm_u_tlm_tx_vc0_frm_seq_sq_fifo_un1_raddr_lo_1_axb_1_3760) + ); + XORCY com_tlm_u_tlm_tx_vc0_frm_seq_sq_fifo_un1_raddr_lo_1_s_1 ( + .CI(com_tlm_u_tlm_tx_vc0_frm_seq_sq_fifo_un1_raddr_lo_1_cry_0_3747), + .LI(com_tlm_u_tlm_tx_vc0_frm_seq_sq_fifo_un1_raddr_lo_1_axb_1_3760), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_sq_fifo_un1_raddr_lo_1_s_1_4) + ); + MUXCY_L com_tlm_u_tlm_tx_vc0_frm_seq_sq_fifo_un1_raddr_lo_1_cry_2 ( + .CI(com_tlm_u_tlm_tx_vc0_frm_seq_sq_fifo_un1_raddr_lo_1_cry_1_3748), + .DI(com_tlm_u_tlm_tx_vc0_frm_seq_sq_fifo_raddr_lo[2]), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_sq_fifo_un1_raddr_lo_1_cry_2_3749), + .S(com_tlm_u_tlm_tx_vc0_frm_seq_sq_fifo_un1_raddr_lo_1_axb_2_3759) + ); + XORCY com_tlm_u_tlm_tx_vc0_frm_seq_sq_fifo_un1_raddr_lo_1_s_2 ( + .CI(com_tlm_u_tlm_tx_vc0_frm_seq_sq_fifo_un1_raddr_lo_1_cry_1_3748), + .LI(com_tlm_u_tlm_tx_vc0_frm_seq_sq_fifo_un1_raddr_lo_1_axb_2_3759), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_sq_fifo_un1_raddr_lo_1_s_2_4) + ); + XORCY com_tlm_u_tlm_tx_vc0_frm_seq_sq_fifo_un1_raddr_lo_1_s_3 ( + .CI(com_tlm_u_tlm_tx_vc0_frm_seq_sq_fifo_un1_raddr_lo_1_cry_2_3749), + .LI(com_tlm_u_tlm_tx_vc0_frm_seq_sq_fifo_un1_raddr_lo_1_axb_3_3758), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_sq_fifo_un1_raddr_lo_1_s_3_4) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_sq_fifo_raddr_en_0_0_0_0_o3.INIT = 4'h4; + LUT2 com_tlm_u_tlm_tx_vc0_frm_seq_sq_fifo_raddr_en_0_0_0_0_o3 ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_seq_state[1]), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_sq_vld), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_sq_fifo_N_56061_i) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_sq_fifo_un1_ct_o217_0_a2_0_a2_0_a2_0_o3_1_.INIT = 4'h8; + LUT2 com_tlm_u_tlm_tx_vc0_frm_seq_sq_fifo_un1_ct_o217_0_a2_0_a2_0_a2_0_o3_1_ ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_seq_state[1]), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_sq_vld), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_sq_fifo_N_56519_i) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_sq_fifo_un1_ct_o217_0_a2_0_a2_0_a2_0_a2_1_.INIT = 4'h2; + LUT2 com_tlm_u_tlm_tx_vc0_frm_seq_sq_fifo_un1_ct_o217_0_a2_0_a2_0_a2_0_a2_1_ ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_sq_fifo_N_56519_i), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_sq_wen_3693), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_sq_fifo_un1_ct_o217_0_a2_0_a2_0_a2_0_a2[1]) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_sq_fifo_un1_bkp_i_1_i_0_0_0_0_a2_0_2.INIT = 16'h0001; + LUT4 com_tlm_u_tlm_tx_vc0_frm_seq_sq_fifo_un1_bkp_i_1_i_0_0_0_0_a2_0_2 ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_sq_fifo_raddr_lo[0]), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_sq_fifo_raddr_lo[1]), + .I2(com_tlm_u_tlm_tx_vc0_frm_seq_sq_fifo_raddr_lo[2]), + .I3(com_tlm_u_tlm_tx_vc0_frm_seq_sq_fifo_raddr_lo[3]), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_sq_fifo_un1_bkp_i_1_i_0_0_0_0_a2_0_2_3752) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_sq_fifo_un1_bkp_i_1_i_0_0_0_0_a2.INIT = 8'hE0; + LUT3 com_tlm_u_tlm_tx_vc0_frm_seq_sq_fifo_un1_bkp_i_1_i_0_0_0_0_a2 ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_sq_fifo_N_56061_i), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_sq_nxt_vld), + .I2(com_tlm_u_tlm_tx_vc0_frm_seq_sq_wen_3693), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_sq_fifo_srl_wen) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_sq_fifo_std_ct_N_56520_i_i.INIT = 4'h6; + LUT2 com_tlm_u_tlm_tx_vc0_frm_seq_sq_fifo_std_ct_N_56520_i_i ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_sq_fifo_N_56519_i), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_sq_wen_3693), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_sq_fifo_N_56520_i_i) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_sq_fifo_un1_raddr_lo_1_axb_0.INIT = 16'h669C; + LUT4 com_tlm_u_tlm_tx_vc0_frm_seq_sq_fifo_un1_raddr_lo_1_axb_0 ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_sq_fifo_N_56061_i), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_sq_fifo_raddr_lo[0]), + .I2(com_tlm_u_tlm_tx_vc0_frm_seq_sq_nxt_vld), + .I3(com_tlm_u_tlm_tx_vc0_frm_seq_sq_wen_3693), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_sq_fifo_un1_raddr_lo_1_axb_0_3750) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_sq_fifo_N_87187_i.INIT = 8'hDC; + LUT3 com_tlm_u_tlm_tx_vc0_frm_seq_sq_fifo_N_87187_i ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_sq_fifo_N_56061_i), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_sq_fifo_srl_wen), + .I2(com_tlm_u_tlm_tx_vc0_frm_seq_sq_fifo_un1_bkp_i_1_i_0_0_0_0_a2_0_2_3752), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_sq_fifo_N_87187_i_3751) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_sq_fifo_N_59263_i.INIT = 4'hE; + LUT2_L com_tlm_u_tlm_tx_vc0_frm_seq_sq_fifo_N_59263_i ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_sq_nxt_vld), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_sq_wen_3693), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_sq_fifo_N_59263_i_3753) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_sq_fifo_data_bits_d_o_46_0_i_m2_i_m3_i_m3_i_m3_0_3_.INIT = 8'hCA; + LUT3_L com_tlm_u_tlm_tx_vc0_frm_seq_sq_fifo_data_bits_d_o_46_0_i_m2_i_m3_i_m3_i_m3_0_3_ ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_sq_d[3]), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_sq_fifo_shift_tap[3]), + .I2(com_tlm_u_tlm_tx_vc0_frm_seq_sq_nxt_vld), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_sq_fifo_d_o_46_0_i_m2_i_m3_i_m3_i_m3_0[3]) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_sq_fifo_data_bits_d_o_46_0_i_m2_i_m3_i_m3_i_m3_0_2_.INIT = 8'hCA; + LUT3_L com_tlm_u_tlm_tx_vc0_frm_seq_sq_fifo_data_bits_d_o_46_0_i_m2_i_m3_i_m3_i_m3_0_2_ ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_sq_d[2]), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_sq_fifo_shift_tap[2]), + .I2(com_tlm_u_tlm_tx_vc0_frm_seq_sq_nxt_vld), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_sq_fifo_d_o_46_0_i_m2_i_m3_i_m3_i_m3_0[2]) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_sq_fifo_data_bits_d_o_46_0_i_m2_i_m3_i_m3_i_m3_0_1_.INIT = 8'hCA; + LUT3_L com_tlm_u_tlm_tx_vc0_frm_seq_sq_fifo_data_bits_d_o_46_0_i_m2_i_m3_i_m3_i_m3_0_1_ ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_sq_d[1]), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_sq_fifo_shift_tap[1]), + .I2(com_tlm_u_tlm_tx_vc0_frm_seq_sq_nxt_vld), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_sq_fifo_d_o_46_0_i_m2_i_m3_i_m3_i_m3_0[1]) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_sq_fifo_data_bits_d_o_46_0_i_m2_i_m3_i_m3_i_m3_0_0_.INIT = 8'hCA; + LUT3_L com_tlm_u_tlm_tx_vc0_frm_seq_sq_fifo_data_bits_d_o_46_0_i_m2_i_m3_i_m3_i_m3_0_0_ ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_sq_d[0]), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_sq_fifo_shift_tap[0]), + .I2(com_tlm_u_tlm_tx_vc0_frm_seq_sq_nxt_vld), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_sq_fifo_d_o_46_0_i_m2_i_m3_i_m3_i_m3_0[0]) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_sq_fifo_un1_ct_o_axbxc2.INIT = 8'h96; + LUT3_L com_tlm_u_tlm_tx_vc0_frm_seq_sq_fifo_un1_ct_o_axbxc2 ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_sq_fifo_un1_ct_o217_0_a2_0_a2_0_a2_0_a2[1]), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_sq_cnt[2]), + .I2(com_tlm_u_tlm_tx_vc0_frm_seq_sq_fifo_un1_ct_o_p4_3755), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_sq_fifo_un1_ct_o_axbxc2_3754) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_sq_fifo_un1_ct_o_axbxc1.INIT = 16'hB4D2; + LUT4_L com_tlm_u_tlm_tx_vc0_frm_seq_sq_fifo_un1_ct_o_axbxc1 ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_sq_fifo_N_56519_i), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_sq_cnt[0]), + .I2(com_tlm_u_tlm_tx_vc0_frm_seq_sq_cnt[1]), + .I3(com_tlm_u_tlm_tx_vc0_frm_seq_sq_wen_3693), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_sq_fifo_un1_ct_o_axbxc1_3756) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_sq_fifo_un1_ct_o_axb0.INIT = 8'h96; + LUT3_L com_tlm_u_tlm_tx_vc0_frm_seq_sq_fifo_un1_ct_o_axb0 ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_sq_fifo_N_56519_i), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_sq_cnt[0]), + .I2(com_tlm_u_tlm_tx_vc0_frm_seq_sq_wen_3693), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_sq_fifo_un1_ct_o_axb0_3757) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_sq_fifo_un1_raddr_lo_1_axb_3.INIT = 16'hCC9C; + LUT4_L com_tlm_u_tlm_tx_vc0_frm_seq_sq_fifo_un1_raddr_lo_1_axb_3 ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_sq_fifo_N_56061_i), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_sq_fifo_raddr_lo[3]), + .I2(com_tlm_u_tlm_tx_vc0_frm_seq_sq_nxt_vld), + .I3(com_tlm_u_tlm_tx_vc0_frm_seq_sq_wen_3693), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_sq_fifo_un1_raddr_lo_1_axb_3_3758) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_sq_fifo_un1_raddr_lo_1_axb_2.INIT = 16'hCC9C; + LUT4_L com_tlm_u_tlm_tx_vc0_frm_seq_sq_fifo_un1_raddr_lo_1_axb_2 ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_sq_fifo_N_56061_i), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_sq_fifo_raddr_lo[2]), + .I2(com_tlm_u_tlm_tx_vc0_frm_seq_sq_nxt_vld), + .I3(com_tlm_u_tlm_tx_vc0_frm_seq_sq_wen_3693), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_sq_fifo_un1_raddr_lo_1_axb_2_3759) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_sq_fifo_un1_raddr_lo_1_axb_1.INIT = 16'hCC9C; + LUT4_L com_tlm_u_tlm_tx_vc0_frm_seq_sq_fifo_un1_raddr_lo_1_axb_1 ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_sq_fifo_N_56061_i), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_sq_fifo_raddr_lo[1]), + .I2(com_tlm_u_tlm_tx_vc0_frm_seq_sq_nxt_vld), + .I3(com_tlm_u_tlm_tx_vc0_frm_seq_sq_wen_3693), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_sq_fifo_un1_raddr_lo_1_axb_1_3760) + ); + FDE com_tlm_u_tlm_tx_vc0_frm_seq_sq_fifo_d_o_3_ ( + .CE(com_tlm_u_tlm_tx_vc0_frm_seq_sq_fifo_N_56061_i_i_3761), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_sq_fifo_d_o_46_0_i_m2_i_m3_i_m3_i_m3_0[3]), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_sq_q[3]) + ); + FDE com_tlm_u_tlm_tx_vc0_frm_seq_sq_fifo_d_o_2_ ( + .CE(com_tlm_u_tlm_tx_vc0_frm_seq_sq_fifo_N_56061_i_i_3761), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_sq_fifo_d_o_46_0_i_m2_i_m3_i_m3_i_m3_0[2]), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_sq_q[2]) + ); + FDE com_tlm_u_tlm_tx_vc0_frm_seq_sq_fifo_d_o_1_ ( + .CE(com_tlm_u_tlm_tx_vc0_frm_seq_sq_fifo_N_56061_i_i_3761), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_sq_fifo_d_o_46_0_i_m2_i_m3_i_m3_i_m3_0[1]), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_sq_q[1]) + ); + FDE com_tlm_u_tlm_tx_vc0_frm_seq_sq_fifo_d_o_0_ ( + .CE(com_tlm_u_tlm_tx_vc0_frm_seq_sq_fifo_N_56061_i_i_3761), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_sq_fifo_d_o_46_0_i_m2_i_m3_i_m3_i_m3_0[0]), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_sq_q[0]) + ); + INV com_tlm_u_tlm_tx_vc0_frm_seq_sq_fifo_N_56061_i_i ( + .I(com_tlm_u_tlm_tx_vc0_frm_seq_sq_fifo_N_56061_i), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_sq_fifo_N_56061_i_i_3761) + ); + VCC com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_VCC ( + .P(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_VCC_3864) + ); + GND com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_GND ( + .G(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_GND_3876) + ); + FDS com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_min_data_cred_3_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_min_data_cred_7[3]), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_min_data_cred[3]), + .S(plm_link_up_i) + ); + FDR com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_min_data_cred_4_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_min_data_cred_7[4]), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_min_data_cred[4]), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_min_data_cred_5_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_N_32423_i), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_min_data_cred[5]), + .R(plm_link_up_i) + ); + FDS com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_pd_av_o_0_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_pd_av_o_6[0]), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_pd_av_0_), + .S(plm_link_up_i) + ); + FDS com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_pd_av_o_1_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_pd_av_o_6[1]), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_pd_av_1_), + .S(plm_link_up_i) + ); + FDS com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_pd_av_o_2_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_pd_av_o_6[2]), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_pd_av_2_), + .S(plm_link_up_i) + ); + FDS com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_pd_av_o_3_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_pd_av_o_6[3]), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_pd_av_3_), + .S(plm_link_up_i) + ); + FDS com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_pd_av_o_4_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_pd_av_o_6[4]), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_pd_av_4_), + .S(plm_link_up_i) + ); + FDS com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_pd_av_o_5_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_pd_av_o_6[5]), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_pd_av_5_), + .S(plm_link_up_i) + ); + FDS com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_pd_av_o_6_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_pd_av_o_6[6]), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_pd_av[6]), + .S(plm_link_up_i) + ); + FDS com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_pd_av_o_7_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_pd_av_o_6[7]), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_pd_av[7]), + .S(plm_link_up_i) + ); + FDS com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_pd_av_o_8_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_pd_av_o_6[8]), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_pd_av[8]), + .S(plm_link_up_i) + ); + FDS com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_pd_av_o_9_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_pd_av_o_6[9]), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_pd_av[9]), + .S(plm_link_up_i) + ); + FDS com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_pd_av_o_10_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_pd_av_o_6[10]), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_pd_av[10]), + .S(plm_link_up_i) + ); + FDR com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_pd_av_o_11_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_pd_av_o_6[11]), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_pd_av_11_), + .R(plm_link_up_i) + ); + FDS com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_npd_av_o_0_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_npd_av_o_6[0]), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_npd_av[0]), + .S(plm_link_up_i) + ); + FDS com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_npd_av_o_1_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_npd_av_o_6[1]), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_npd_av[1]), + .S(plm_link_up_i) + ); + FDS com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_npd_av_o_2_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_npd_av_o_6[2]), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_npd_av[2]), + .S(plm_link_up_i) + ); + FDS com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_npd_av_o_3_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_npd_av_o_6[3]), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_npd_av[3]), + .S(plm_link_up_i) + ); + FDS com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_npd_av_o_4_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_npd_av_o_6[4]), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_npd_av[4]), + .S(plm_link_up_i) + ); + FDS com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_npd_av_o_5_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_npd_av_o_6[5]), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_npd_av[5]), + .S(plm_link_up_i) + ); + FDS com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_npd_av_o_6_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_npd_av_o_6[6]), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_npd_av[6]), + .S(plm_link_up_i) + ); + FDS com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_npd_av_o_7_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_npd_av_o_6[7]), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_npd_av[7]), + .S(plm_link_up_i) + ); + FDS com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_npd_av_o_8_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_npd_av_o_6[8]), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_npd_av[8]), + .S(plm_link_up_i) + ); + FDS com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_npd_av_o_9_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_npd_av_o_6[9]), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_npd_av[9]), + .S(plm_link_up_i) + ); + FDS com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_npd_av_o_10_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_npd_av_o_6[10]), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_npd_av[10]), + .S(plm_link_up_i) + ); + FDR com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_npd_av_o_11_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_npd_av_o_6[11]), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_npd_av[11]), + .R(plm_link_up_i) + ); + FDS com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_cpld_av_o_0_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_cpld_av_o_6[0]), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_cpld_av_0_), + .S(plm_link_up_i) + ); + FDS com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_cpld_av_o_1_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_cpld_av_o_6[1]), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_cpld_av_1_), + .S(plm_link_up_i) + ); + FDS com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_cpld_av_o_2_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_cpld_av_o_6[2]), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_cpld_av_2_), + .S(plm_link_up_i) + ); + FDS com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_cpld_av_o_3_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_cpld_av_o_6[3]), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_cpld_av_3_), + .S(plm_link_up_i) + ); + FDS com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_cpld_av_o_4_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_cpld_av_o_6[4]), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_cpld_av_4_), + .S(plm_link_up_i) + ); + FDS com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_cpld_av_o_5_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_cpld_av_o_6[5]), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_cpld_av_5_), + .S(plm_link_up_i) + ); + FDS com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_cpld_av_o_6_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_cpld_av_o_6[6]), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_cpld_av[6]), + .S(plm_link_up_i) + ); + FDS com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_cpld_av_o_7_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_cpld_av_o_6[7]), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_cpld_av[7]), + .S(plm_link_up_i) + ); + FDS com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_cpld_av_o_8_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_cpld_av_o_6[8]), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_cpld_av[8]), + .S(plm_link_up_i) + ); + FDS com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_cpld_av_o_9_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_cpld_av_o_6[9]), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_cpld_av[9]), + .S(plm_link_up_i) + ); + FDS com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_cpld_av_o_10_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_cpld_av_o_6[10]), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_cpld_av[10]), + .S(plm_link_up_i) + ); + FDR com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_cpld_av_o_11_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_cpld_av_o_6[11]), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_cpld_av_11_), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_PD_0_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_PD_1_axb_0_3943), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_PD[0]), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_PD_1_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_PD_1_s_1_3782), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_PD[1]), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_PD_2_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_PD_1_s_2_3785), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_PD[2]), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_PD_3_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_PD_1_s_3_3788), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_PD[3]), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_PD_4_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_PD_1_s_4_3791), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_PD[4]), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_PD_5_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_PD_1_s_5_3794), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_PD[5]), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_PD_6_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_PD_1_s_6_3796), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_PD[6]), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_PD_7_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_PD_1_s_7_3798), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_PD[7]), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_PD_8_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_PD_1_s_8_3800), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_PD[8]), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_PD_9_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_PD_1_s_9_3802), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_PD[9]), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_PD_10_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_PD_1_s_10_3804), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_PD[10]), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_PD_11_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_PD_1_s_11_3806), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_PD[11]), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_NPD_0_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_NPD_1_axb_0_3944), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_NPD[0]), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_NPD_1_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_NPD_1_s_1_3810), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_NPD[1]), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_NPD_2_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_NPD_1_s_2_3813), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_NPD[2]), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_NPD_3_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_NPD_1_s_3_3816), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_NPD[3]), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_NPD_4_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_NPD_1_s_4_3819), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_NPD[4]), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_NPD_5_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_NPD_1_s_5_3822), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_NPD[5]), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_NPD_6_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_NPD_1_s_6_3824), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_NPD[6]), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_NPD_7_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_NPD_1_s_7_3826), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_NPD[7]), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_NPD_8_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_NPD_1_s_8_3828), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_NPD[8]), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_NPD_9_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_NPD_1_s_9_3830), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_NPD[9]), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_NPD_10_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_NPD_1_s_10_3832), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_NPD[10]), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_NPD_11_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_NPD_1_s_11_3834), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_NPD[11]), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_CPLD_0_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_CPLD_1_axb_0_3945), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_CPLD[0]), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_CPLD_1_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_CPLD_1_s_1_3838), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_CPLD[1]), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_CPLD_2_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_CPLD_1_s_2_3841), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_CPLD[2]), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_CPLD_3_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_CPLD_1_s_3_3844), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_CPLD[3]), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_CPLD_4_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_CPLD_1_s_4_3847), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_CPLD[4]), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_CPLD_5_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_CPLD_1_s_5_3850), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_CPLD[5]), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_CPLD_6_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_CPLD_1_s_6_3852), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_CPLD[6]), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_CPLD_7_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_CPLD_1_s_7_3854), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_CPLD[7]), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_CPLD_8_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_CPLD_1_s_8_3856), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_CPLD[8]), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_CPLD_9_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_CPLD_1_s_9_3858), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_CPLD[9]), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_CPLD_10_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_CPLD_1_s_10_3860), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_CPLD[10]), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_CPLD_11_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_CPLD_1_s_11_3862), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_CPLD[11]), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_credits_ok_0_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_credits_ok_3[0]), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_credits_ok[0]), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_credits_ok_1_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_credits_ok[0]), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_credits_ok[1]), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_credits_ok_2_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_credits_ok[1]), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_credits_ok[2]), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_av_hdr_cred ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_N_85833_i_3997), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_av_hdr_cred_4001), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_av_data_cred_0_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_N_32433_i), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_av_data_cred[0]), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_av_data_cred_1_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_N_32435_i), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_av_data_cred[1]), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_av_data_cred_2_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_N_32437_i), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_av_data_cred[2]), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_av_data_cred_3_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_N_32439_i), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_av_data_cred[3]), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_av_data_cred_4_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_N_32441_i), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_av_data_cred[4]), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_av_data_cred_5_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_N_32443_i), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_av_data_cred[5]), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_av_data_cred_6_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_N_32445_i), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_av_data_cred[6]), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_av_data_cred_7_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_N_32447_i), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_av_data_cred[7]), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_av_data_cred_8_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_N_32449_i), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_av_data_cred[8]), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_av_data_cred_9_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_N_32451_i), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_av_data_cred[9]), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_av_data_cred_10_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_N_32453_i), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_av_data_cred[10]), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_av_data_cred_11_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_N_32455_i), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_av_data_cred[11]), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_ph_av_o ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_N_9378_i_3992), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_ph_av), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_nph_av_o ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_N_9379_i_3987), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_nph_av), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_cplh_av_o ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_N_9377_i_3982), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_cplh_av), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_err_fc_o ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_err_fc_o13), + .Q(com_tlm_cmmt_err_flow_control), + .R(plm_link_up_i) + ); + FDRE com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_limit_PH_0_ ( + .CE(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_N_87844_i_3955), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_header_qq[0]), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_limit_PH[0]), + .R(plm_link_up_i) + ); + FDRE com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_limit_PH_1_ ( + .CE(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_N_87844_i_3955), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_header_qq[1]), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_limit_PH[1]), + .R(plm_link_up_i) + ); + FDRE com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_limit_PH_2_ ( + .CE(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_N_87844_i_3955), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_header_qq[2]), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_limit_PH[2]), + .R(plm_link_up_i) + ); + FDRE com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_limit_PH_3_ ( + .CE(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_N_87844_i_3955), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_header_qq[3]), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_limit_PH[3]), + .R(plm_link_up_i) + ); + FDRE com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_limit_PH_4_ ( + .CE(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_N_87844_i_3955), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_header_qq[4]), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_limit_PH[4]), + .R(plm_link_up_i) + ); + FDRE com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_limit_PH_5_ ( + .CE(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_N_87844_i_3955), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_header_qq[5]), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_limit_PH[5]), + .R(plm_link_up_i) + ); + FDRE com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_limit_PH_6_ ( + .CE(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_N_87844_i_3955), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_header_qq[6]), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_limit_PH[6]), + .R(plm_link_up_i) + ); + FDRE com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_limit_PH_7_ ( + .CE(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_N_87844_i_3955), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_header_qq[7]), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_limit_PH[7]), + .R(plm_link_up_i) + ); + FDRE com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_limit_PD_0_ ( + .CE(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_N_87844_i_3955), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_data_qq[0]), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_limit_PD[0]), + .R(plm_link_up_i) + ); + FDRE com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_limit_PD_1_ ( + .CE(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_N_87844_i_3955), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_data_qq[1]), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_limit_PD[1]), + .R(plm_link_up_i) + ); + FDRE com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_limit_PD_2_ ( + .CE(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_N_87844_i_3955), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_data_qq[2]), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_limit_PD[2]), + .R(plm_link_up_i) + ); + FDRE com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_limit_PD_3_ ( + .CE(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_N_87844_i_3955), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_data_qq[3]), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_limit_PD[3]), + .R(plm_link_up_i) + ); + FDRE com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_limit_PD_4_ ( + .CE(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_N_87844_i_3955), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_data_qq[4]), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_limit_PD[4]), + .R(plm_link_up_i) + ); + FDRE com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_limit_PD_5_ ( + .CE(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_N_87844_i_3955), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_data_qq[5]), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_limit_PD[5]), + .R(plm_link_up_i) + ); + FDRE com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_limit_PD_6_ ( + .CE(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_N_87844_i_3955), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_data_qq[6]), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_limit_PD[6]), + .R(plm_link_up_i) + ); + FDRE com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_limit_PD_7_ ( + .CE(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_N_87844_i_3955), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_data_qq[7]), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_limit_PD[7]), + .R(plm_link_up_i) + ); + FDRE com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_limit_PD_8_ ( + .CE(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_N_87844_i_3955), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_data_qq[8]), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_limit_PD[8]), + .R(plm_link_up_i) + ); + FDRE com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_limit_PD_9_ ( + .CE(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_N_87844_i_3955), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_data_qq[9]), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_limit_PD[9]), + .R(plm_link_up_i) + ); + FDRE com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_limit_PD_10_ ( + .CE(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_N_87844_i_3955), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_data_qq[10]), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_limit_PD[10]), + .R(plm_link_up_i) + ); + FDRE com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_limit_PD_11_ ( + .CE(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_N_87844_i_3955), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_data_qq[11]), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_limit_PD[11]), + .R(plm_link_up_i) + ); + FDRE com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_limit_NPH_0_ ( + .CE(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_N_87845_i_3958), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_header_qq[0]), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_limit_NPH[0]), + .R(plm_link_up_i) + ); + FDRE com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_limit_NPH_1_ ( + .CE(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_N_87845_i_3958), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_header_qq[1]), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_limit_NPH[1]), + .R(plm_link_up_i) + ); + FDRE com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_limit_NPH_2_ ( + .CE(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_N_87845_i_3958), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_header_qq[2]), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_limit_NPH[2]), + .R(plm_link_up_i) + ); + FDRE com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_limit_NPH_3_ ( + .CE(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_N_87845_i_3958), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_header_qq[3]), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_limit_NPH[3]), + .R(plm_link_up_i) + ); + FDRE com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_limit_NPH_4_ ( + .CE(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_N_87845_i_3958), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_header_qq[4]), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_limit_NPH[4]), + .R(plm_link_up_i) + ); + FDRE com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_limit_NPH_5_ ( + .CE(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_N_87845_i_3958), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_header_qq[5]), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_limit_NPH[5]), + .R(plm_link_up_i) + ); + FDRE com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_limit_NPH_6_ ( + .CE(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_N_87845_i_3958), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_header_qq[6]), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_limit_NPH[6]), + .R(plm_link_up_i) + ); + FDRE com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_limit_NPH_7_ ( + .CE(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_N_87845_i_3958), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_header_qq[7]), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_limit_NPH[7]), + .R(plm_link_up_i) + ); + FDRE com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_limit_NPD_0_ ( + .CE(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_N_87845_i_3958), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_data_qq[0]), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_limit_NPD[0]), + .R(plm_link_up_i) + ); + FDRE com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_limit_NPD_1_ ( + .CE(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_N_87845_i_3958), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_data_qq[1]), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_limit_NPD[1]), + .R(plm_link_up_i) + ); + FDRE com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_limit_NPD_2_ ( + .CE(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_N_87845_i_3958), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_data_qq[2]), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_limit_NPD[2]), + .R(plm_link_up_i) + ); + FDRE com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_limit_NPD_3_ ( + .CE(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_N_87845_i_3958), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_data_qq[3]), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_limit_NPD[3]), + .R(plm_link_up_i) + ); + FDRE com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_limit_NPD_4_ ( + .CE(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_N_87845_i_3958), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_data_qq[4]), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_limit_NPD[4]), + .R(plm_link_up_i) + ); + FDRE com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_limit_NPD_5_ ( + .CE(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_N_87845_i_3958), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_data_qq[5]), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_limit_NPD[5]), + .R(plm_link_up_i) + ); + FDRE com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_limit_NPD_6_ ( + .CE(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_N_87845_i_3958), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_data_qq[6]), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_limit_NPD[6]), + .R(plm_link_up_i) + ); + FDRE com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_limit_NPD_7_ ( + .CE(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_N_87845_i_3958), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_data_qq[7]), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_limit_NPD[7]), + .R(plm_link_up_i) + ); + FDRE com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_limit_NPD_8_ ( + .CE(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_N_87845_i_3958), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_data_qq[8]), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_limit_NPD[8]), + .R(plm_link_up_i) + ); + FDRE com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_limit_NPD_9_ ( + .CE(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_N_87845_i_3958), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_data_qq[9]), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_limit_NPD[9]), + .R(plm_link_up_i) + ); + FDRE com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_limit_NPD_10_ ( + .CE(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_N_87845_i_3958), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_data_qq[10]), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_limit_NPD[10]), + .R(plm_link_up_i) + ); + FDRE com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_limit_NPD_11_ ( + .CE(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_N_87845_i_3958), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_data_qq[11]), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_limit_NPD[11]), + .R(plm_link_up_i) + ); + FDRE com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_limit_CPLH_0_ ( + .CE(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_N_87846_i_3961), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_header_qq[0]), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_limit_CPLH[0]), + .R(plm_link_up_i) + ); + FDRE com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_limit_CPLH_1_ ( + .CE(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_N_87846_i_3961), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_header_qq[1]), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_limit_CPLH[1]), + .R(plm_link_up_i) + ); + FDRE com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_limit_CPLH_2_ ( + .CE(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_N_87846_i_3961), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_header_qq[2]), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_limit_CPLH[2]), + .R(plm_link_up_i) + ); + FDRE com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_limit_CPLH_3_ ( + .CE(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_N_87846_i_3961), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_header_qq[3]), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_limit_CPLH[3]), + .R(plm_link_up_i) + ); + FDRE com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_limit_CPLH_4_ ( + .CE(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_N_87846_i_3961), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_header_qq[4]), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_limit_CPLH[4]), + .R(plm_link_up_i) + ); + FDRE com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_limit_CPLH_5_ ( + .CE(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_N_87846_i_3961), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_header_qq[5]), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_limit_CPLH[5]), + .R(plm_link_up_i) + ); + FDRE com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_limit_CPLH_6_ ( + .CE(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_N_87846_i_3961), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_header_qq[6]), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_limit_CPLH[6]), + .R(plm_link_up_i) + ); + FDRE com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_limit_CPLH_7_ ( + .CE(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_N_87846_i_3961), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_header_qq[7]), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_limit_CPLH[7]), + .R(plm_link_up_i) + ); + FDRE com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_limit_CPLD_0_ ( + .CE(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_N_87846_i_3961), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_data_qq[0]), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_limit_CPLD[0]), + .R(plm_link_up_i) + ); + FDRE com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_limit_CPLD_1_ ( + .CE(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_N_87846_i_3961), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_data_qq[1]), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_limit_CPLD[1]), + .R(plm_link_up_i) + ); + FDRE com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_limit_CPLD_2_ ( + .CE(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_N_87846_i_3961), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_data_qq[2]), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_limit_CPLD[2]), + .R(plm_link_up_i) + ); + FDRE com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_limit_CPLD_3_ ( + .CE(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_N_87846_i_3961), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_data_qq[3]), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_limit_CPLD[3]), + .R(plm_link_up_i) + ); + FDRE com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_limit_CPLD_4_ ( + .CE(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_N_87846_i_3961), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_data_qq[4]), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_limit_CPLD[4]), + .R(plm_link_up_i) + ); + FDRE com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_limit_CPLD_5_ ( + .CE(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_N_87846_i_3961), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_data_qq[5]), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_limit_CPLD[5]), + .R(plm_link_up_i) + ); + FDRE com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_limit_CPLD_6_ ( + .CE(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_N_87846_i_3961), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_data_qq[6]), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_limit_CPLD[6]), + .R(plm_link_up_i) + ); + FDRE com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_limit_CPLD_7_ ( + .CE(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_N_87846_i_3961), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_data_qq[7]), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_limit_CPLD[7]), + .R(plm_link_up_i) + ); + FDRE com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_limit_CPLD_8_ ( + .CE(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_N_87846_i_3961), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_data_qq[8]), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_limit_CPLD[8]), + .R(plm_link_up_i) + ); + FDRE com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_limit_CPLD_9_ ( + .CE(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_N_87846_i_3961), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_data_qq[9]), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_limit_CPLD[9]), + .R(plm_link_up_i) + ); + FDRE com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_limit_CPLD_10_ ( + .CE(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_N_87846_i_3961), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_data_qq[10]), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_limit_CPLD[10]), + .R(plm_link_up_i) + ); + FDRE com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_limit_CPLD_11_ ( + .CE(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_N_87846_i_3961), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_data_qq[11]), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_limit_CPLD[11]), + .R(plm_link_up_i) + ); + FDRE com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_infinite_PH ( + .CE(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_init_pc_3948), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_infinite_header_q_4070), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_infinite_PH_3950), + .R(plm_link_up_i) + ); + FDRE com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_infinite_PD ( + .CE(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_init_pc_3948), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_infinite_data_q_4071), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_infinite_PD_4084), + .R(plm_link_up_i) + ); + FDRE com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_infinite_NPH ( + .CE(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_init_npc_3947), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_infinite_header_q_4070), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_infinite_NPH_3951), + .R(plm_link_up_i) + ); + FDRE com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_infinite_NPD ( + .CE(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_init_npc_3947), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_infinite_data_q_4071), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_infinite_NPD_4082), + .R(plm_link_up_i) + ); + FDRE com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_infinite_CPLH ( + .CE(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_init_cplc_3946), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_infinite_header_q_4070), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_infinite_CPLH_3972), + .R(plm_link_up_i) + ); + FDRE com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_infinite_CPLD ( + .CE(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_init_cplc_3946), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_infinite_data_q_4071), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_infinite_CPLD_4080), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_av_valid_o ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_av_valid_o_4), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_av_valid), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_update_p ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_update_p_3), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_update_p_3956), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_update_np ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_update_np_3), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_update_np_3959), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_update_cpl ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_update_cpl_3), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_update_cpl_3962), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_suspend_rdy_o ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_suspend_rdy_o_3_3976), + .Q(com_tlm_u_tlm_tx_suspend_credit_rdy), + .R(plm_link_up_i) + ); + FDS com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_q ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_N_16839_i_3975), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_q_3978), + .S(plm_link_up_i) + ); + FDR com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_update_vld_qq ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_update_vld_q_3977), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_update_vld_qq_3979), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_update_vld_q ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_fc_update_vld), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_update_vld_q_3977), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_init_vld_q ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_fc_init_vld), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_init_vld_q_3949), + .R(plm_link_up_i) + ); + MUXCY_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un7_credits_ok_cry_0 ( + .CI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_GND_3876), + .DI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_suspend_cat[1]), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un7_credits_ok_cry_0_3762), + .S(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un7_credits_ok_axb_0_i_4114) + ); + MUXCY_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un7_credits_ok_cry_1 ( + .CI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un7_credits_ok_cry_0_3762), + .DI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_GND_3876), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un7_credits_ok_cry_1_3763), + .S(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_av_data_cred_i_1__4113) + ); + MUXCY_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un7_credits_ok_cry_2 ( + .CI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un7_credits_ok_cry_1_3763), + .DI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_GND_3876), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un7_credits_ok_cry_2_3764), + .S(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_av_data_cred_i_2__4112) + ); + MUXCY_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un7_credits_ok_cry_3 ( + .CI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un7_credits_ok_cry_2_3764), + .DI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_min_data_cred[3]), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un7_credits_ok_cry_3_3765), + .S(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un7_credits_ok_axb_3_i_4111) + ); + MUXCY_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un7_credits_ok_cry_4 ( + .CI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un7_credits_ok_cry_3_3765), + .DI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_min_data_cred[4]), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un7_credits_ok_cry_4_3766), + .S(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un7_credits_ok_axb_4_i_4110) + ); + MUXCY_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un7_credits_ok_cry_5 ( + .CI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un7_credits_ok_cry_4_3766), + .DI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_min_data_cred[5]), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un7_credits_ok_cry_5_3767), + .S(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un7_credits_ok_axb_5_i_4109) + ); + MUXCY_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un7_credits_ok_cry_6 ( + .CI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un7_credits_ok_cry_5_3767), + .DI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_GND_3876), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un7_credits_ok_cry_6_3768), + .S(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_av_data_cred_i_6__4108) + ); + MUXCY_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un7_credits_ok_cry_7 ( + .CI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un7_credits_ok_cry_6_3768), + .DI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_GND_3876), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un7_credits_ok_cry_7_3769), + .S(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_av_data_cred_i_7__4107) + ); + MUXCY_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un7_credits_ok_cry_8 ( + .CI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un7_credits_ok_cry_7_3769), + .DI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_GND_3876), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un7_credits_ok_cry_8_3770), + .S(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_av_data_cred_i_8__4106) + ); + MUXCY_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un7_credits_ok_cry_9 ( + .CI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un7_credits_ok_cry_8_3770), + .DI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_GND_3876), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un7_credits_ok_cry_9_3771), + .S(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_av_data_cred_i_9__4105) + ); + MUXCY_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un7_credits_ok_cry_10 ( + .CI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un7_credits_ok_cry_9_3771), + .DI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_GND_3876), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un7_credits_ok_cry_10_3772), + .S(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_av_data_cred_i_10__4104) + ); + MUXCY com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un7_credits_ok_cry_11 ( + .CI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un7_credits_ok_cry_10_3772), + .DI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_GND_3876), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un7_credits_ok_cry_11_4000), + .S(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_av_data_cred_i_11__4103) + ); + MUXCY_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_fc_diff_header_cry_0 ( + .CI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_VCC_3864), + .DI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_header_q[0]), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_fc_diff_header_cry_0_3773), + .S(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_fc_diff_header_axb_0_4102) + ); + MUXCY_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_fc_diff_header_cry_1 ( + .CI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_fc_diff_header_cry_0_3773), + .DI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_header_q[1]), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_fc_diff_header_cry_1_3774), + .S(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_fc_diff_header_axb_1_4101) + ); + MUXCY_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_fc_diff_header_cry_2 ( + .CI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_fc_diff_header_cry_1_3774), + .DI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_header_q[2]), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_fc_diff_header_cry_2_3775), + .S(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_fc_diff_header_axb_2_4100) + ); + MUXCY_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_fc_diff_header_cry_3 ( + .CI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_fc_diff_header_cry_2_3775), + .DI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_header_q[3]), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_fc_diff_header_cry_3_3776), + .S(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_fc_diff_header_axb_3_4099) + ); + MUXCY_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_fc_diff_header_cry_4 ( + .CI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_fc_diff_header_cry_3_3776), + .DI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_header_q[4]), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_fc_diff_header_cry_4_3777), + .S(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_fc_diff_header_axb_4_4098) + ); + MUXCY_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_fc_diff_header_cry_5 ( + .CI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_fc_diff_header_cry_4_3777), + .DI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_header_q[5]), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_fc_diff_header_cry_5_3778), + .S(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_fc_diff_header_axb_5_4097) + ); + MUXCY_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_fc_diff_header_cry_6 ( + .CI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_fc_diff_header_cry_5_3778), + .DI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_header_q[6]), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_fc_diff_header_cry_6_3779), + .S(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_fc_diff_header_axb_6_4096) + ); + XORCY com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_fc_diff_header_s_7 ( + .CI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_fc_diff_header_cry_6_3779), + .LI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_fc_diff_header_axb_7_3971), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_fc_diff_header[7]) + ); + MULT_AND com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_PD_1_cry_0 ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_consumed_credits[0]), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_consumed_ph_3620), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_PD_1_cry_0_0_3780) + ); + MUXCY_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_PD_1_cry_0_0 ( + .CI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_GND_3876), + .DI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_PD_1_cry_0_0_3780), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_PD_1_cry_0_3783), + .S(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_PD_1_axb_0_3943) + ); + MULT_AND com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_PD_1_cry_1 ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_consumed_credits[1]), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_consumed_ph_3620), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_PD_1_cry_1_0_3781) + ); + MUXCY_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_PD_1_cry_1_0 ( + .CI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_PD_1_cry_0_3783), + .DI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_PD_1_cry_1_0_3781), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_PD_1_cry_1_3786), + .S(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_PD_1_axb_1_4034) + ); + XORCY com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_PD_1_s_1 ( + .CI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_PD_1_cry_0_3783), + .LI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_PD_1_axb_1_4034), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_PD_1_s_1_3782) + ); + MULT_AND com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_PD_1_cry_2 ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_consumed_credits[2]), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_consumed_ph_3620), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_PD_1_cry_2_0_3784) + ); + MUXCY_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_PD_1_cry_2_0 ( + .CI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_PD_1_cry_1_3786), + .DI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_PD_1_cry_2_0_3784), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_PD_1_cry_2_3789), + .S(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_PD_1_axb_2_4033) + ); + XORCY com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_PD_1_s_2 ( + .CI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_PD_1_cry_1_3786), + .LI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_PD_1_axb_2_4033), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_PD_1_s_2_3785) + ); + MULT_AND com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_PD_1_cry_3 ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_consumed_credits[3]), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_consumed_ph_3620), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_PD_1_cry_3_0_3787) + ); + MUXCY_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_PD_1_cry_3_0 ( + .CI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_PD_1_cry_2_3789), + .DI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_PD_1_cry_3_0_3787), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_PD_1_cry_3_3792), + .S(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_PD_1_axb_3_4032) + ); + XORCY com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_PD_1_s_3 ( + .CI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_PD_1_cry_2_3789), + .LI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_PD_1_axb_3_4032), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_PD_1_s_3_3788) + ); + MULT_AND com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_PD_1_cry_4 ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_consumed_credits[4]), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_consumed_ph_3620), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_PD_1_cry_4_0_3790) + ); + MUXCY_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_PD_1_cry_4_0 ( + .CI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_PD_1_cry_3_3792), + .DI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_PD_1_cry_4_0_3790), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_PD_1_cry_4_3795), + .S(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_PD_1_axb_4_4031) + ); + XORCY com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_PD_1_s_4 ( + .CI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_PD_1_cry_3_3792), + .LI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_PD_1_axb_4_4031), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_PD_1_s_4_3791) + ); + MULT_AND com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_PD_1_cry_5 ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_consumed_credits[5]), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_consumed_ph_3620), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_PD_1_cry_5_0_3793) + ); + MUXCY_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_PD_1_cry_5_0 ( + .CI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_PD_1_cry_4_3795), + .DI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_PD_1_cry_5_0_3793), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_PD_1_cry_5_3797), + .S(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_PD_1_axb_5_4030) + ); + XORCY com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_PD_1_s_5 ( + .CI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_PD_1_cry_4_3795), + .LI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_PD_1_axb_5_4030), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_PD_1_s_5_3794) + ); + MUXCY_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_PD_1_cry_6 ( + .CI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_PD_1_cry_5_3797), + .DI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_GND_3876), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_PD_1_cry_6_3799), + .S(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_PD_1_axb_6_4029) + ); + XORCY com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_PD_1_s_6 ( + .CI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_PD_1_cry_5_3797), + .LI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_PD_1_axb_6_4029), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_PD_1_s_6_3796) + ); + MUXCY_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_PD_1_cry_7 ( + .CI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_PD_1_cry_6_3799), + .DI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_GND_3876), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_PD_1_cry_7_3801), + .S(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_PD_1_axb_7_4028) + ); + XORCY com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_PD_1_s_7 ( + .CI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_PD_1_cry_6_3799), + .LI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_PD_1_axb_7_4028), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_PD_1_s_7_3798) + ); + MUXCY_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_PD_1_cry_8 ( + .CI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_PD_1_cry_7_3801), + .DI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_GND_3876), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_PD_1_cry_8_3803), + .S(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_PD_1_axb_8_4027) + ); + XORCY com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_PD_1_s_8 ( + .CI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_PD_1_cry_7_3801), + .LI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_PD_1_axb_8_4027), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_PD_1_s_8_3800) + ); + MUXCY_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_PD_1_cry_9 ( + .CI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_PD_1_cry_8_3803), + .DI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_GND_3876), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_PD_1_cry_9_3805), + .S(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_PD_1_axb_9_4026) + ); + XORCY com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_PD_1_s_9 ( + .CI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_PD_1_cry_8_3803), + .LI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_PD_1_axb_9_4026), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_PD_1_s_9_3802) + ); + MUXCY_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_PD_1_cry_10 ( + .CI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_PD_1_cry_9_3805), + .DI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_GND_3876), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_PD_1_cry_10_3807), + .S(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_PD_1_axb_10_4025) + ); + XORCY com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_PD_1_s_10 ( + .CI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_PD_1_cry_9_3805), + .LI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_PD_1_axb_10_4025), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_PD_1_s_10_3804) + ); + XORCY com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_PD_1_s_11 ( + .CI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_PD_1_cry_10_3807), + .LI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_PD_1_axb_11_4024), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_PD_1_s_11_3806) + ); + MULT_AND com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_NPD_1_cry_0 ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_consumed_credits[0]), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_consumed_nph_3619), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_NPD_1_cry_0_0_3808) + ); + MUXCY_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_NPD_1_cry_0_0 ( + .CI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_GND_3876), + .DI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_NPD_1_cry_0_0_3808), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_NPD_1_cry_0_3811), + .S(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_NPD_1_axb_0_3944) + ); + MULT_AND com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_NPD_1_cry_1 ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_consumed_credits[1]), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_consumed_nph_3619), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_NPD_1_cry_1_0_3809) + ); + MUXCY_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_NPD_1_cry_1_0 ( + .CI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_NPD_1_cry_0_3811), + .DI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_NPD_1_cry_1_0_3809), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_NPD_1_cry_1_3814), + .S(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_NPD_1_axb_1_4023) + ); + XORCY com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_NPD_1_s_1 ( + .CI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_NPD_1_cry_0_3811), + .LI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_NPD_1_axb_1_4023), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_NPD_1_s_1_3810) + ); + MULT_AND com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_NPD_1_cry_2 ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_consumed_credits[2]), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_consumed_nph_3619), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_NPD_1_cry_2_0_3812) + ); + MUXCY_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_NPD_1_cry_2_0 ( + .CI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_NPD_1_cry_1_3814), + .DI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_NPD_1_cry_2_0_3812), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_NPD_1_cry_2_3817), + .S(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_NPD_1_axb_2_4022) + ); + XORCY com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_NPD_1_s_2 ( + .CI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_NPD_1_cry_1_3814), + .LI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_NPD_1_axb_2_4022), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_NPD_1_s_2_3813) + ); + MULT_AND com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_NPD_1_cry_3 ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_consumed_credits[3]), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_consumed_nph_3619), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_NPD_1_cry_3_0_3815) + ); + MUXCY_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_NPD_1_cry_3_0 ( + .CI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_NPD_1_cry_2_3817), + .DI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_NPD_1_cry_3_0_3815), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_NPD_1_cry_3_3820), + .S(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_NPD_1_axb_3_4021) + ); + XORCY com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_NPD_1_s_3 ( + .CI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_NPD_1_cry_2_3817), + .LI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_NPD_1_axb_3_4021), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_NPD_1_s_3_3816) + ); + MULT_AND com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_NPD_1_cry_4 ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_consumed_credits[4]), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_consumed_nph_3619), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_NPD_1_cry_4_0_3818) + ); + MUXCY_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_NPD_1_cry_4_0 ( + .CI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_NPD_1_cry_3_3820), + .DI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_NPD_1_cry_4_0_3818), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_NPD_1_cry_4_3823), + .S(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_NPD_1_axb_4_4020) + ); + XORCY com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_NPD_1_s_4 ( + .CI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_NPD_1_cry_3_3820), + .LI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_NPD_1_axb_4_4020), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_NPD_1_s_4_3819) + ); + MULT_AND com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_NPD_1_cry_5 ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_consumed_credits[5]), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_consumed_nph_3619), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_NPD_1_cry_5_0_3821) + ); + MUXCY_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_NPD_1_cry_5_0 ( + .CI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_NPD_1_cry_4_3823), + .DI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_NPD_1_cry_5_0_3821), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_NPD_1_cry_5_3825), + .S(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_NPD_1_axb_5_4019) + ); + XORCY com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_NPD_1_s_5 ( + .CI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_NPD_1_cry_4_3823), + .LI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_NPD_1_axb_5_4019), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_NPD_1_s_5_3822) + ); + MUXCY_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_NPD_1_cry_6 ( + .CI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_NPD_1_cry_5_3825), + .DI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_GND_3876), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_NPD_1_cry_6_3827), + .S(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_NPD_1_axb_6_4018) + ); + XORCY com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_NPD_1_s_6 ( + .CI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_NPD_1_cry_5_3825), + .LI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_NPD_1_axb_6_4018), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_NPD_1_s_6_3824) + ); + MUXCY_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_NPD_1_cry_7 ( + .CI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_NPD_1_cry_6_3827), + .DI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_GND_3876), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_NPD_1_cry_7_3829), + .S(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_NPD_1_axb_7_4017) + ); + XORCY com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_NPD_1_s_7 ( + .CI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_NPD_1_cry_6_3827), + .LI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_NPD_1_axb_7_4017), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_NPD_1_s_7_3826) + ); + MUXCY_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_NPD_1_cry_8 ( + .CI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_NPD_1_cry_7_3829), + .DI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_GND_3876), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_NPD_1_cry_8_3831), + .S(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_NPD_1_axb_8_4016) + ); + XORCY com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_NPD_1_s_8 ( + .CI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_NPD_1_cry_7_3829), + .LI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_NPD_1_axb_8_4016), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_NPD_1_s_8_3828) + ); + MUXCY_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_NPD_1_cry_9 ( + .CI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_NPD_1_cry_8_3831), + .DI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_GND_3876), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_NPD_1_cry_9_3833), + .S(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_NPD_1_axb_9_4015) + ); + XORCY com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_NPD_1_s_9 ( + .CI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_NPD_1_cry_8_3831), + .LI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_NPD_1_axb_9_4015), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_NPD_1_s_9_3830) + ); + MUXCY_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_NPD_1_cry_10 ( + .CI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_NPD_1_cry_9_3833), + .DI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_GND_3876), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_NPD_1_cry_10_3835), + .S(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_NPD_1_axb_10_4014) + ); + XORCY com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_NPD_1_s_10 ( + .CI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_NPD_1_cry_9_3833), + .LI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_NPD_1_axb_10_4014), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_NPD_1_s_10_3832) + ); + XORCY com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_NPD_1_s_11 ( + .CI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_NPD_1_cry_10_3835), + .LI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_NPD_1_axb_11_4013), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_NPD_1_s_11_3834) + ); + MULT_AND com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_CPLD_1_cry_0 ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_consumed_cplh_3621), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_consumed_credits[0]), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_CPLD_1_cry_0_0_3836) + ); + MUXCY_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_CPLD_1_cry_0_0 ( + .CI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_GND_3876), + .DI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_CPLD_1_cry_0_0_3836), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_CPLD_1_cry_0_3839), + .S(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_CPLD_1_axb_0_3945) + ); + MULT_AND com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_CPLD_1_cry_1 ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_consumed_cplh_3621), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_consumed_credits[1]), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_CPLD_1_cry_1_0_3837) + ); + MUXCY_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_CPLD_1_cry_1_0 ( + .CI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_CPLD_1_cry_0_3839), + .DI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_CPLD_1_cry_1_0_3837), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_CPLD_1_cry_1_3842), + .S(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_CPLD_1_axb_1_4012) + ); + XORCY com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_CPLD_1_s_1 ( + .CI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_CPLD_1_cry_0_3839), + .LI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_CPLD_1_axb_1_4012), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_CPLD_1_s_1_3838) + ); + MULT_AND com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_CPLD_1_cry_2 ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_consumed_cplh_3621), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_consumed_credits[2]), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_CPLD_1_cry_2_0_3840) + ); + MUXCY_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_CPLD_1_cry_2_0 ( + .CI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_CPLD_1_cry_1_3842), + .DI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_CPLD_1_cry_2_0_3840), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_CPLD_1_cry_2_3845), + .S(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_CPLD_1_axb_2_4011) + ); + XORCY com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_CPLD_1_s_2 ( + .CI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_CPLD_1_cry_1_3842), + .LI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_CPLD_1_axb_2_4011), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_CPLD_1_s_2_3841) + ); + MULT_AND com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_CPLD_1_cry_3 ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_consumed_cplh_3621), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_consumed_credits[3]), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_CPLD_1_cry_3_0_3843) + ); + MUXCY_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_CPLD_1_cry_3_0 ( + .CI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_CPLD_1_cry_2_3845), + .DI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_CPLD_1_cry_3_0_3843), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_CPLD_1_cry_3_3848), + .S(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_CPLD_1_axb_3_4010) + ); + XORCY com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_CPLD_1_s_3 ( + .CI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_CPLD_1_cry_2_3845), + .LI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_CPLD_1_axb_3_4010), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_CPLD_1_s_3_3844) + ); + MULT_AND com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_CPLD_1_cry_4 ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_consumed_cplh_3621), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_consumed_credits[4]), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_CPLD_1_cry_4_0_3846) + ); + MUXCY_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_CPLD_1_cry_4_0 ( + .CI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_CPLD_1_cry_3_3848), + .DI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_CPLD_1_cry_4_0_3846), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_CPLD_1_cry_4_3851), + .S(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_CPLD_1_axb_4_4009) + ); + XORCY com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_CPLD_1_s_4 ( + .CI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_CPLD_1_cry_3_3848), + .LI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_CPLD_1_axb_4_4009), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_CPLD_1_s_4_3847) + ); + MULT_AND com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_CPLD_1_cry_5 ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_consumed_cplh_3621), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_consumed_credits[5]), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_CPLD_1_cry_5_0_3849) + ); + MUXCY_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_CPLD_1_cry_5_0 ( + .CI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_CPLD_1_cry_4_3851), + .DI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_CPLD_1_cry_5_0_3849), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_CPLD_1_cry_5_3853), + .S(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_CPLD_1_axb_5_4008) + ); + XORCY com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_CPLD_1_s_5 ( + .CI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_CPLD_1_cry_4_3851), + .LI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_CPLD_1_axb_5_4008), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_CPLD_1_s_5_3850) + ); + MUXCY_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_CPLD_1_cry_6 ( + .CI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_CPLD_1_cry_5_3853), + .DI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_GND_3876), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_CPLD_1_cry_6_3855), + .S(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_CPLD_1_axb_6_4007) + ); + XORCY com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_CPLD_1_s_6 ( + .CI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_CPLD_1_cry_5_3853), + .LI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_CPLD_1_axb_6_4007), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_CPLD_1_s_6_3852) + ); + MUXCY_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_CPLD_1_cry_7 ( + .CI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_CPLD_1_cry_6_3855), + .DI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_GND_3876), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_CPLD_1_cry_7_3857), + .S(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_CPLD_1_axb_7_4006) + ); + XORCY com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_CPLD_1_s_7 ( + .CI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_CPLD_1_cry_6_3855), + .LI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_CPLD_1_axb_7_4006), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_CPLD_1_s_7_3854) + ); + MUXCY_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_CPLD_1_cry_8 ( + .CI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_CPLD_1_cry_7_3857), + .DI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_GND_3876), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_CPLD_1_cry_8_3859), + .S(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_CPLD_1_axb_8_4005) + ); + XORCY com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_CPLD_1_s_8 ( + .CI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_CPLD_1_cry_7_3857), + .LI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_CPLD_1_axb_8_4005), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_CPLD_1_s_8_3856) + ); + MUXCY_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_CPLD_1_cry_9 ( + .CI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_CPLD_1_cry_8_3859), + .DI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_GND_3876), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_CPLD_1_cry_9_3861), + .S(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_CPLD_1_axb_9_4004) + ); + XORCY com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_CPLD_1_s_9 ( + .CI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_CPLD_1_cry_8_3859), + .LI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_CPLD_1_axb_9_4004), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_CPLD_1_s_9_3858) + ); + MUXCY_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_CPLD_1_cry_10 ( + .CI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_CPLD_1_cry_9_3861), + .DI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_GND_3876), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_CPLD_1_cry_10_3863), + .S(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_CPLD_1_axb_10_4003) + ); + XORCY com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_CPLD_1_s_10 ( + .CI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_CPLD_1_cry_9_3861), + .LI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_CPLD_1_axb_10_4003), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_CPLD_1_s_10_3860) + ); + XORCY com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_CPLD_1_s_11 ( + .CI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_CPLD_1_cry_10_3863), + .LI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_CPLD_1_axb_11_4002), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_CPLD_1_s_11_3862) + ); + MUXCY_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_fc_diff_data_cry_0 ( + .CI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_VCC_3864), + .DI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_data_q[0]), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_fc_diff_data_cry_0_3865), + .S(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_fc_diff_data_axb_0_4095) + ); + MUXCY_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_fc_diff_data_cry_1 ( + .CI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_fc_diff_data_cry_0_3865), + .DI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_data_q[1]), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_fc_diff_data_cry_1_3866), + .S(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_fc_diff_data_axb_1_4094) + ); + MUXCY_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_fc_diff_data_cry_2 ( + .CI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_fc_diff_data_cry_1_3866), + .DI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_data_q[2]), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_fc_diff_data_cry_2_3867), + .S(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_fc_diff_data_axb_2_4093) + ); + MUXCY_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_fc_diff_data_cry_3 ( + .CI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_fc_diff_data_cry_2_3867), + .DI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_data_q[3]), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_fc_diff_data_cry_3_3868), + .S(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_fc_diff_data_axb_3_4092) + ); + MUXCY_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_fc_diff_data_cry_4 ( + .CI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_fc_diff_data_cry_3_3868), + .DI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_data_q[4]), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_fc_diff_data_cry_4_3869), + .S(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_fc_diff_data_axb_4_4091) + ); + MUXCY_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_fc_diff_data_cry_5 ( + .CI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_fc_diff_data_cry_4_3869), + .DI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_data_q[5]), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_fc_diff_data_cry_5_3870), + .S(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_fc_diff_data_axb_5_4090) + ); + MUXCY_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_fc_diff_data_cry_6 ( + .CI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_fc_diff_data_cry_5_3870), + .DI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_data_q[6]), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_fc_diff_data_cry_6_3871), + .S(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_fc_diff_data_axb_6_4089) + ); + MUXCY_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_fc_diff_data_cry_7 ( + .CI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_fc_diff_data_cry_6_3871), + .DI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_data_q[7]), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_fc_diff_data_cry_7_3872), + .S(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_fc_diff_data_axb_7_4088) + ); + MUXCY_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_fc_diff_data_cry_8 ( + .CI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_fc_diff_data_cry_7_3872), + .DI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_data_q[8]), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_fc_diff_data_cry_8_3873), + .S(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_fc_diff_data_axb_8_4087) + ); + MUXCY_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_fc_diff_data_cry_9 ( + .CI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_fc_diff_data_cry_8_3873), + .DI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_data_q[9]), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_fc_diff_data_cry_9_3874), + .S(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_fc_diff_data_axb_9_4086) + ); + MUXCY_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_fc_diff_data_cry_10 ( + .CI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_fc_diff_data_cry_9_3874), + .DI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_data_q[10]), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_fc_diff_data_cry_10_3875), + .S(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_fc_diff_data_axb_10_4085) + ); + XORCY com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_fc_diff_data_s_11 ( + .CI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_fc_diff_data_cry_10_3875), + .LI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_fc_diff_data_axb_11_3970), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_fc_diff_data[11]) + ); + FDRE com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_PH_0_ ( + .CE(com_tlm_u_tlm_tx_vc0_frm_seq_consumed_ph_3620), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_PH_s[0]), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_PH[0]), + .R(plm_link_up_i) + ); + MUXCY_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_PH_cry_1_ ( + .CI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_PH[0]), + .DI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_GND_3876), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_PH_cry[1]), + .S(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_PH_qxu[1]) + ); + XORCY com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_PH_s_1_ ( + .CI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_PH[0]), + .LI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_PH_qxu[1]), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_PH_s[1]) + ); + FDRE com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_PH_1_ ( + .CE(com_tlm_u_tlm_tx_vc0_frm_seq_consumed_ph_3620), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_PH_s[1]), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_PH[1]), + .R(plm_link_up_i) + ); + MUXCY_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_PH_cry_2_ ( + .CI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_PH_cry[1]), + .DI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_GND_3876), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_PH_cry[2]), + .S(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_PH_qxu[2]) + ); + XORCY com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_PH_s_2_ ( + .CI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_PH_cry[1]), + .LI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_PH_qxu[2]), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_PH_s[2]) + ); + FDRE com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_PH_2_ ( + .CE(com_tlm_u_tlm_tx_vc0_frm_seq_consumed_ph_3620), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_PH_s[2]), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_PH[2]), + .R(plm_link_up_i) + ); + MUXCY_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_PH_cry_3_ ( + .CI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_PH_cry[2]), + .DI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_GND_3876), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_PH_cry[3]), + .S(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_PH_qxu[3]) + ); + XORCY com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_PH_s_3_ ( + .CI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_PH_cry[2]), + .LI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_PH_qxu[3]), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_PH_s[3]) + ); + FDRE com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_PH_3_ ( + .CE(com_tlm_u_tlm_tx_vc0_frm_seq_consumed_ph_3620), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_PH_s[3]), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_PH[3]), + .R(plm_link_up_i) + ); + MUXCY_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_PH_cry_4_ ( + .CI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_PH_cry[3]), + .DI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_GND_3876), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_PH_cry[4]), + .S(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_PH_qxu[4]) + ); + XORCY com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_PH_s_4_ ( + .CI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_PH_cry[3]), + .LI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_PH_qxu[4]), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_PH_s[4]) + ); + FDRE com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_PH_4_ ( + .CE(com_tlm_u_tlm_tx_vc0_frm_seq_consumed_ph_3620), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_PH_s[4]), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_PH[4]), + .R(plm_link_up_i) + ); + MUXCY_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_PH_cry_5_ ( + .CI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_PH_cry[4]), + .DI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_GND_3876), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_PH_cry[5]), + .S(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_PH_qxu[5]) + ); + XORCY com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_PH_s_5_ ( + .CI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_PH_cry[4]), + .LI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_PH_qxu[5]), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_PH_s[5]) + ); + FDRE com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_PH_5_ ( + .CE(com_tlm_u_tlm_tx_vc0_frm_seq_consumed_ph_3620), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_PH_s[5]), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_PH[5]), + .R(plm_link_up_i) + ); + MUXCY_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_PH_cry_6_ ( + .CI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_PH_cry[5]), + .DI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_GND_3876), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_PH_cry[6]), + .S(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_PH_qxu[6]) + ); + XORCY com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_PH_s_6_ ( + .CI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_PH_cry[5]), + .LI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_PH_qxu[6]), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_PH_s[6]) + ); + FDRE com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_PH_6_ ( + .CE(com_tlm_u_tlm_tx_vc0_frm_seq_consumed_ph_3620), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_PH_s[6]), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_PH[6]), + .R(plm_link_up_i) + ); + XORCY com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_PH_s_7_ ( + .CI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_PH_cry[6]), + .LI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_PH_qxu[7]), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_PH_s[7]) + ); + FDRE com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_PH_7_ ( + .CE(com_tlm_u_tlm_tx_vc0_frm_seq_consumed_ph_3620), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_PH_s[7]), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_PH[7]), + .R(plm_link_up_i) + ); + FDRE com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_NPH_0_ ( + .CE(com_tlm_u_tlm_tx_vc0_frm_seq_consumed_nph_3619), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_NPH_s[0]), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_NPH[0]), + .R(plm_link_up_i) + ); + MUXCY_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_NPH_cry_1_ ( + .CI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_NPH[0]), + .DI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_GND_3876), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_NPH_cry[1]), + .S(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_NPH_qxu[1]) + ); + XORCY com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_NPH_s_1_ ( + .CI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_NPH[0]), + .LI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_NPH_qxu[1]), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_NPH_s[1]) + ); + FDRE com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_NPH_1_ ( + .CE(com_tlm_u_tlm_tx_vc0_frm_seq_consumed_nph_3619), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_NPH_s[1]), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_NPH[1]), + .R(plm_link_up_i) + ); + MUXCY_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_NPH_cry_2_ ( + .CI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_NPH_cry[1]), + .DI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_GND_3876), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_NPH_cry[2]), + .S(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_NPH_qxu[2]) + ); + XORCY com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_NPH_s_2_ ( + .CI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_NPH_cry[1]), + .LI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_NPH_qxu[2]), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_NPH_s[2]) + ); + FDRE com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_NPH_2_ ( + .CE(com_tlm_u_tlm_tx_vc0_frm_seq_consumed_nph_3619), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_NPH_s[2]), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_NPH[2]), + .R(plm_link_up_i) + ); + MUXCY_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_NPH_cry_3_ ( + .CI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_NPH_cry[2]), + .DI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_GND_3876), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_NPH_cry[3]), + .S(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_NPH_qxu[3]) + ); + XORCY com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_NPH_s_3_ ( + .CI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_NPH_cry[2]), + .LI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_NPH_qxu[3]), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_NPH_s[3]) + ); + FDRE com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_NPH_3_ ( + .CE(com_tlm_u_tlm_tx_vc0_frm_seq_consumed_nph_3619), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_NPH_s[3]), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_NPH[3]), + .R(plm_link_up_i) + ); + MUXCY_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_NPH_cry_4_ ( + .CI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_NPH_cry[3]), + .DI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_GND_3876), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_NPH_cry[4]), + .S(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_NPH_qxu[4]) + ); + XORCY com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_NPH_s_4_ ( + .CI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_NPH_cry[3]), + .LI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_NPH_qxu[4]), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_NPH_s[4]) + ); + FDRE com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_NPH_4_ ( + .CE(com_tlm_u_tlm_tx_vc0_frm_seq_consumed_nph_3619), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_NPH_s[4]), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_NPH[4]), + .R(plm_link_up_i) + ); + MUXCY_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_NPH_cry_5_ ( + .CI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_NPH_cry[4]), + .DI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_GND_3876), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_NPH_cry[5]), + .S(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_NPH_qxu[5]) + ); + XORCY com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_NPH_s_5_ ( + .CI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_NPH_cry[4]), + .LI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_NPH_qxu[5]), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_NPH_s[5]) + ); + FDRE com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_NPH_5_ ( + .CE(com_tlm_u_tlm_tx_vc0_frm_seq_consumed_nph_3619), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_NPH_s[5]), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_NPH[5]), + .R(plm_link_up_i) + ); + MUXCY_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_NPH_cry_6_ ( + .CI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_NPH_cry[5]), + .DI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_GND_3876), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_NPH_cry[6]), + .S(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_NPH_qxu[6]) + ); + XORCY com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_NPH_s_6_ ( + .CI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_NPH_cry[5]), + .LI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_NPH_qxu[6]), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_NPH_s[6]) + ); + FDRE com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_NPH_6_ ( + .CE(com_tlm_u_tlm_tx_vc0_frm_seq_consumed_nph_3619), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_NPH_s[6]), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_NPH[6]), + .R(plm_link_up_i) + ); + XORCY com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_NPH_s_7_ ( + .CI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_NPH_cry[6]), + .LI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_NPH_qxu[7]), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_NPH_s[7]) + ); + FDRE com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_NPH_7_ ( + .CE(com_tlm_u_tlm_tx_vc0_frm_seq_consumed_nph_3619), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_NPH_s[7]), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_NPH[7]), + .R(plm_link_up_i) + ); + FDRE com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_CPLH_0_ ( + .CE(com_tlm_u_tlm_tx_vc0_frm_seq_consumed_cplh_3621), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_CPLH_s[0]), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_CPLH[0]), + .R(plm_link_up_i) + ); + MUXCY_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_CPLH_cry_1_ ( + .CI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_CPLH[0]), + .DI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_GND_3876), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_CPLH_cry[1]), + .S(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_CPLH_qxu[1]) + ); + XORCY com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_CPLH_s_1_ ( + .CI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_CPLH[0]), + .LI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_CPLH_qxu[1]), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_CPLH_s[1]) + ); + FDRE com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_CPLH_1_ ( + .CE(com_tlm_u_tlm_tx_vc0_frm_seq_consumed_cplh_3621), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_CPLH_s[1]), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_CPLH[1]), + .R(plm_link_up_i) + ); + MUXCY_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_CPLH_cry_2_ ( + .CI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_CPLH_cry[1]), + .DI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_GND_3876), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_CPLH_cry[2]), + .S(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_CPLH_qxu[2]) + ); + XORCY com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_CPLH_s_2_ ( + .CI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_CPLH_cry[1]), + .LI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_CPLH_qxu[2]), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_CPLH_s[2]) + ); + FDRE com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_CPLH_2_ ( + .CE(com_tlm_u_tlm_tx_vc0_frm_seq_consumed_cplh_3621), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_CPLH_s[2]), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_CPLH[2]), + .R(plm_link_up_i) + ); + MUXCY_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_CPLH_cry_3_ ( + .CI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_CPLH_cry[2]), + .DI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_GND_3876), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_CPLH_cry[3]), + .S(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_CPLH_qxu[3]) + ); + XORCY com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_CPLH_s_3_ ( + .CI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_CPLH_cry[2]), + .LI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_CPLH_qxu[3]), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_CPLH_s[3]) + ); + FDRE com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_CPLH_3_ ( + .CE(com_tlm_u_tlm_tx_vc0_frm_seq_consumed_cplh_3621), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_CPLH_s[3]), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_CPLH[3]), + .R(plm_link_up_i) + ); + MUXCY_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_CPLH_cry_4_ ( + .CI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_CPLH_cry[3]), + .DI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_GND_3876), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_CPLH_cry[4]), + .S(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_CPLH_qxu[4]) + ); + XORCY com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_CPLH_s_4_ ( + .CI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_CPLH_cry[3]), + .LI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_CPLH_qxu[4]), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_CPLH_s[4]) + ); + FDRE com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_CPLH_4_ ( + .CE(com_tlm_u_tlm_tx_vc0_frm_seq_consumed_cplh_3621), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_CPLH_s[4]), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_CPLH[4]), + .R(plm_link_up_i) + ); + MUXCY_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_CPLH_cry_5_ ( + .CI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_CPLH_cry[4]), + .DI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_GND_3876), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_CPLH_cry[5]), + .S(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_CPLH_qxu[5]) + ); + XORCY com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_CPLH_s_5_ ( + .CI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_CPLH_cry[4]), + .LI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_CPLH_qxu[5]), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_CPLH_s[5]) + ); + FDRE com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_CPLH_5_ ( + .CE(com_tlm_u_tlm_tx_vc0_frm_seq_consumed_cplh_3621), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_CPLH_s[5]), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_CPLH[5]), + .R(plm_link_up_i) + ); + MUXCY_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_CPLH_cry_6_ ( + .CI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_CPLH_cry[5]), + .DI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_GND_3876), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_CPLH_cry[6]), + .S(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_CPLH_qxu[6]) + ); + XORCY com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_CPLH_s_6_ ( + .CI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_CPLH_cry[5]), + .LI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_CPLH_qxu[6]), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_CPLH_s[6]) + ); + FDRE com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_CPLH_6_ ( + .CE(com_tlm_u_tlm_tx_vc0_frm_seq_consumed_cplh_3621), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_CPLH_s[6]), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_CPLH[6]), + .R(plm_link_up_i) + ); + XORCY com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_CPLH_s_7_ ( + .CI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_CPLH_cry[6]), + .LI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_CPLH_qxu[7]), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_CPLH_s[7]) + ); + FDRE com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_CPLH_7_ ( + .CE(com_tlm_u_tlm_tx_vc0_frm_seq_consumed_cplh_3621), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_CPLH_s[7]), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_CPLH[7]), + .R(plm_link_up_i) + ); + MULT_AND com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_cpld_av_o_6_cry_0 ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_CPLD_i[0]), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_infinite_CPLD_i_4076), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_cpld_av_o_6_cry_0_0_3877) + ); + MUXCY_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_cpld_av_o_6_cry_0_0 ( + .CI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_infinite_CPLD_i_4076), + .DI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_cpld_av_o_6_cry_0_0_3877), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_cpld_av_o_6_cry_0_3879), + .S(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_cpld_av_o_6_axb_0_4045) + ); + XORCY com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_cpld_av_o_6_s_0 ( + .CI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_infinite_CPLD_i_4076), + .LI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_cpld_av_o_6_axb_0_4045), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_cpld_av_o_6[0]) + ); + MULT_AND com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_cpld_av_o_6_cry_1 ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_CPLD_i[1]), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_infinite_CPLD_i_4076), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_cpld_av_o_6_cry_1_0_3878) + ); + MUXCY_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_cpld_av_o_6_cry_1_0 ( + .CI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_cpld_av_o_6_cry_0_3879), + .DI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_cpld_av_o_6_cry_1_0_3878), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_cpld_av_o_6_cry_1_3881), + .S(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_cpld_av_o_6_axb_1_4044) + ); + XORCY com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_cpld_av_o_6_s_1 ( + .CI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_cpld_av_o_6_cry_0_3879), + .LI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_cpld_av_o_6_axb_1_4044), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_cpld_av_o_6[1]) + ); + MULT_AND com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_cpld_av_o_6_cry_2 ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_CPLD_i[2]), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_infinite_CPLD_i_4076), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_cpld_av_o_6_cry_2_0_3880) + ); + MUXCY_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_cpld_av_o_6_cry_2_0 ( + .CI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_cpld_av_o_6_cry_1_3881), + .DI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_cpld_av_o_6_cry_2_0_3880), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_cpld_av_o_6_cry_2_3883), + .S(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_cpld_av_o_6_axb_2_4043) + ); + XORCY com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_cpld_av_o_6_s_2 ( + .CI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_cpld_av_o_6_cry_1_3881), + .LI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_cpld_av_o_6_axb_2_4043), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_cpld_av_o_6[2]) + ); + MULT_AND com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_cpld_av_o_6_cry_3 ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_CPLD_i[3]), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_infinite_CPLD_i_4076), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_cpld_av_o_6_cry_3_0_3882) + ); + MUXCY_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_cpld_av_o_6_cry_3_0 ( + .CI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_cpld_av_o_6_cry_2_3883), + .DI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_cpld_av_o_6_cry_3_0_3882), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_cpld_av_o_6_cry_3_3885), + .S(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_cpld_av_o_6_axb_3_4042) + ); + XORCY com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_cpld_av_o_6_s_3 ( + .CI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_cpld_av_o_6_cry_2_3883), + .LI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_cpld_av_o_6_axb_3_4042), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_cpld_av_o_6[3]) + ); + MULT_AND com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_cpld_av_o_6_cry_4 ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_CPLD_i[4]), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_infinite_CPLD_i_4076), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_cpld_av_o_6_cry_4_0_3884) + ); + MUXCY_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_cpld_av_o_6_cry_4_0 ( + .CI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_cpld_av_o_6_cry_3_3885), + .DI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_cpld_av_o_6_cry_4_0_3884), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_cpld_av_o_6_cry_4_3887), + .S(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_cpld_av_o_6_axb_4_4041) + ); + XORCY com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_cpld_av_o_6_s_4 ( + .CI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_cpld_av_o_6_cry_3_3885), + .LI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_cpld_av_o_6_axb_4_4041), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_cpld_av_o_6[4]) + ); + MULT_AND com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_cpld_av_o_6_cry_5 ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_CPLD_i[5]), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_infinite_CPLD_i_4076), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_cpld_av_o_6_cry_5_0_3886) + ); + MUXCY_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_cpld_av_o_6_cry_5_0 ( + .CI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_cpld_av_o_6_cry_4_3887), + .DI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_cpld_av_o_6_cry_5_0_3886), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_cpld_av_o_6_cry_5_3889), + .S(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_cpld_av_o_6_axb_5_4040) + ); + XORCY com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_cpld_av_o_6_s_5 ( + .CI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_cpld_av_o_6_cry_4_3887), + .LI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_cpld_av_o_6_axb_5_4040), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_cpld_av_o_6[5]) + ); + MULT_AND com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_cpld_av_o_6_cry_6 ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_CPLD_i[6]), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_infinite_CPLD_i_4076), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_cpld_av_o_6_cry_6_0_3888) + ); + MUXCY_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_cpld_av_o_6_cry_6_0 ( + .CI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_cpld_av_o_6_cry_5_3889), + .DI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_cpld_av_o_6_cry_6_0_3888), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_cpld_av_o_6_cry_6_3891), + .S(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_cpld_av_o_6_axb_6_4039) + ); + XORCY com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_cpld_av_o_6_s_6 ( + .CI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_cpld_av_o_6_cry_5_3889), + .LI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_cpld_av_o_6_axb_6_4039), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_cpld_av_o_6[6]) + ); + MULT_AND com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_cpld_av_o_6_cry_7 ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_CPLD_i[7]), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_infinite_CPLD_i_4076), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_cpld_av_o_6_cry_7_0_3890) + ); + MUXCY_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_cpld_av_o_6_cry_7_0 ( + .CI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_cpld_av_o_6_cry_6_3891), + .DI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_cpld_av_o_6_cry_7_0_3890), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_cpld_av_o_6_cry_7_3893), + .S(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_cpld_av_o_6_axb_7_4038) + ); + XORCY com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_cpld_av_o_6_s_7 ( + .CI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_cpld_av_o_6_cry_6_3891), + .LI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_cpld_av_o_6_axb_7_4038), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_cpld_av_o_6[7]) + ); + MULT_AND com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_cpld_av_o_6_cry_8 ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_CPLD_i[8]), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_infinite_CPLD_i_4076), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_cpld_av_o_6_cry_8_0_3892) + ); + MUXCY_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_cpld_av_o_6_cry_8_0 ( + .CI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_cpld_av_o_6_cry_7_3893), + .DI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_cpld_av_o_6_cry_8_0_3892), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_cpld_av_o_6_cry_8_3895), + .S(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_cpld_av_o_6_axb_8_4037) + ); + XORCY com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_cpld_av_o_6_s_8 ( + .CI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_cpld_av_o_6_cry_7_3893), + .LI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_cpld_av_o_6_axb_8_4037), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_cpld_av_o_6[8]) + ); + MULT_AND com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_cpld_av_o_6_cry_9 ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_CPLD_i[9]), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_infinite_CPLD_i_4076), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_cpld_av_o_6_cry_9_0_3894) + ); + MUXCY_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_cpld_av_o_6_cry_9_0 ( + .CI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_cpld_av_o_6_cry_8_3895), + .DI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_cpld_av_o_6_cry_9_0_3894), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_cpld_av_o_6_cry_9_3897), + .S(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_cpld_av_o_6_axb_9_4036) + ); + XORCY com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_cpld_av_o_6_s_9 ( + .CI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_cpld_av_o_6_cry_8_3895), + .LI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_cpld_av_o_6_axb_9_4036), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_cpld_av_o_6[9]) + ); + MULT_AND com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_cpld_av_o_6_cry_10 ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_CPLD_i[10]), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_infinite_CPLD_i_4076), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_cpld_av_o_6_cry_10_0_3896) + ); + MUXCY_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_cpld_av_o_6_cry_10_0 ( + .CI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_cpld_av_o_6_cry_9_3897), + .DI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_cpld_av_o_6_cry_10_0_3896), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_cpld_av_o_6_cry_10_3898), + .S(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_cpld_av_o_6_axb_10_4035) + ); + XORCY com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_cpld_av_o_6_s_10 ( + .CI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_cpld_av_o_6_cry_9_3897), + .LI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_cpld_av_o_6_axb_10_4035), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_cpld_av_o_6[10]) + ); + XORCY com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_cpld_av_o_6_s_11 ( + .CI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_cpld_av_o_6_cry_10_3898), + .LI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_cpld_av_o_6_axb_11_4079), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_cpld_av_o_6[11]) + ); + MULT_AND com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_npd_av_o_6_cry_0 ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_NPD_i[0]), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_infinite_NPD_i_4077), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_npd_av_o_6_cry_0_0_3899) + ); + MUXCY_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_npd_av_o_6_cry_0_0 ( + .CI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_infinite_NPD_i_4077), + .DI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_npd_av_o_6_cry_0_0_3899), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_npd_av_o_6_cry_0_3901), + .S(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_npd_av_o_6_axb_0_4056) + ); + XORCY com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_npd_av_o_6_s_0 ( + .CI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_infinite_NPD_i_4077), + .LI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_npd_av_o_6_axb_0_4056), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_npd_av_o_6[0]) + ); + MULT_AND com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_npd_av_o_6_cry_1 ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_NPD_i[1]), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_infinite_NPD_i_4077), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_npd_av_o_6_cry_1_0_3900) + ); + MUXCY_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_npd_av_o_6_cry_1_0 ( + .CI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_npd_av_o_6_cry_0_3901), + .DI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_npd_av_o_6_cry_1_0_3900), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_npd_av_o_6_cry_1_3903), + .S(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_npd_av_o_6_axb_1_4055) + ); + XORCY com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_npd_av_o_6_s_1 ( + .CI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_npd_av_o_6_cry_0_3901), + .LI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_npd_av_o_6_axb_1_4055), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_npd_av_o_6[1]) + ); + MULT_AND com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_npd_av_o_6_cry_2 ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_NPD_i[2]), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_infinite_NPD_i_4077), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_npd_av_o_6_cry_2_0_3902) + ); + MUXCY_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_npd_av_o_6_cry_2_0 ( + .CI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_npd_av_o_6_cry_1_3903), + .DI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_npd_av_o_6_cry_2_0_3902), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_npd_av_o_6_cry_2_3905), + .S(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_npd_av_o_6_axb_2_4054) + ); + XORCY com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_npd_av_o_6_s_2 ( + .CI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_npd_av_o_6_cry_1_3903), + .LI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_npd_av_o_6_axb_2_4054), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_npd_av_o_6[2]) + ); + MULT_AND com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_npd_av_o_6_cry_3 ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_NPD_i[3]), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_infinite_NPD_i_4077), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_npd_av_o_6_cry_3_0_3904) + ); + MUXCY_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_npd_av_o_6_cry_3_0 ( + .CI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_npd_av_o_6_cry_2_3905), + .DI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_npd_av_o_6_cry_3_0_3904), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_npd_av_o_6_cry_3_3907), + .S(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_npd_av_o_6_axb_3_4053) + ); + XORCY com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_npd_av_o_6_s_3 ( + .CI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_npd_av_o_6_cry_2_3905), + .LI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_npd_av_o_6_axb_3_4053), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_npd_av_o_6[3]) + ); + MULT_AND com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_npd_av_o_6_cry_4 ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_NPD_i[4]), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_infinite_NPD_i_4077), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_npd_av_o_6_cry_4_0_3906) + ); + MUXCY_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_npd_av_o_6_cry_4_0 ( + .CI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_npd_av_o_6_cry_3_3907), + .DI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_npd_av_o_6_cry_4_0_3906), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_npd_av_o_6_cry_4_3909), + .S(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_npd_av_o_6_axb_4_4052) + ); + XORCY com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_npd_av_o_6_s_4 ( + .CI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_npd_av_o_6_cry_3_3907), + .LI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_npd_av_o_6_axb_4_4052), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_npd_av_o_6[4]) + ); + MULT_AND com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_npd_av_o_6_cry_5 ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_NPD_i[5]), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_infinite_NPD_i_4077), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_npd_av_o_6_cry_5_0_3908) + ); + MUXCY_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_npd_av_o_6_cry_5_0 ( + .CI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_npd_av_o_6_cry_4_3909), + .DI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_npd_av_o_6_cry_5_0_3908), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_npd_av_o_6_cry_5_3911), + .S(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_npd_av_o_6_axb_5_4051) + ); + XORCY com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_npd_av_o_6_s_5 ( + .CI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_npd_av_o_6_cry_4_3909), + .LI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_npd_av_o_6_axb_5_4051), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_npd_av_o_6[5]) + ); + MULT_AND com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_npd_av_o_6_cry_6 ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_NPD_i[6]), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_infinite_NPD_i_4077), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_npd_av_o_6_cry_6_0_3910) + ); + MUXCY_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_npd_av_o_6_cry_6_0 ( + .CI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_npd_av_o_6_cry_5_3911), + .DI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_npd_av_o_6_cry_6_0_3910), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_npd_av_o_6_cry_6_3913), + .S(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_npd_av_o_6_axb_6_4050) + ); + XORCY com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_npd_av_o_6_s_6 ( + .CI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_npd_av_o_6_cry_5_3911), + .LI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_npd_av_o_6_axb_6_4050), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_npd_av_o_6[6]) + ); + MULT_AND com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_npd_av_o_6_cry_7 ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_NPD_i[7]), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_infinite_NPD_i_4077), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_npd_av_o_6_cry_7_0_3912) + ); + MUXCY_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_npd_av_o_6_cry_7_0 ( + .CI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_npd_av_o_6_cry_6_3913), + .DI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_npd_av_o_6_cry_7_0_3912), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_npd_av_o_6_cry_7_3915), + .S(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_npd_av_o_6_axb_7_4049) + ); + XORCY com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_npd_av_o_6_s_7 ( + .CI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_npd_av_o_6_cry_6_3913), + .LI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_npd_av_o_6_axb_7_4049), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_npd_av_o_6[7]) + ); + MULT_AND com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_npd_av_o_6_cry_8 ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_NPD_i[8]), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_infinite_NPD_i_4077), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_npd_av_o_6_cry_8_0_3914) + ); + MUXCY_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_npd_av_o_6_cry_8_0 ( + .CI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_npd_av_o_6_cry_7_3915), + .DI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_npd_av_o_6_cry_8_0_3914), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_npd_av_o_6_cry_8_3917), + .S(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_npd_av_o_6_axb_8_4048) + ); + XORCY com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_npd_av_o_6_s_8 ( + .CI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_npd_av_o_6_cry_7_3915), + .LI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_npd_av_o_6_axb_8_4048), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_npd_av_o_6[8]) + ); + MULT_AND com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_npd_av_o_6_cry_9 ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_NPD_i[9]), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_infinite_NPD_i_4077), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_npd_av_o_6_cry_9_0_3916) + ); + MUXCY_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_npd_av_o_6_cry_9_0 ( + .CI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_npd_av_o_6_cry_8_3917), + .DI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_npd_av_o_6_cry_9_0_3916), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_npd_av_o_6_cry_9_3919), + .S(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_npd_av_o_6_axb_9_4047) + ); + XORCY com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_npd_av_o_6_s_9 ( + .CI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_npd_av_o_6_cry_8_3917), + .LI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_npd_av_o_6_axb_9_4047), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_npd_av_o_6[9]) + ); + MULT_AND com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_npd_av_o_6_cry_10 ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_NPD_i[10]), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_infinite_NPD_i_4077), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_npd_av_o_6_cry_10_0_3918) + ); + MUXCY_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_npd_av_o_6_cry_10_0 ( + .CI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_npd_av_o_6_cry_9_3919), + .DI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_npd_av_o_6_cry_10_0_3918), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_npd_av_o_6_cry_10_3920), + .S(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_npd_av_o_6_axb_10_4046) + ); + XORCY com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_npd_av_o_6_s_10 ( + .CI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_npd_av_o_6_cry_9_3919), + .LI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_npd_av_o_6_axb_10_4046), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_npd_av_o_6[10]) + ); + XORCY com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_npd_av_o_6_s_11 ( + .CI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_npd_av_o_6_cry_10_3920), + .LI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_npd_av_o_6_axb_11_4081), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_npd_av_o_6[11]) + ); + MULT_AND com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_pd_av_o_6_cry_0 ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_PD_i[0]), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_infinite_PD_i_4078), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_pd_av_o_6_cry_0_0_3921) + ); + MUXCY_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_pd_av_o_6_cry_0_0 ( + .CI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_infinite_PD_i_4078), + .DI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_pd_av_o_6_cry_0_0_3921), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_pd_av_o_6_cry_0_3923), + .S(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_pd_av_o_6_axb_0_4067) + ); + XORCY com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_pd_av_o_6_s_0 ( + .CI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_infinite_PD_i_4078), + .LI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_pd_av_o_6_axb_0_4067), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_pd_av_o_6[0]) + ); + MULT_AND com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_pd_av_o_6_cry_1 ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_PD_i[1]), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_infinite_PD_i_4078), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_pd_av_o_6_cry_1_0_3922) + ); + MUXCY_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_pd_av_o_6_cry_1_0 ( + .CI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_pd_av_o_6_cry_0_3923), + .DI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_pd_av_o_6_cry_1_0_3922), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_pd_av_o_6_cry_1_3925), + .S(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_pd_av_o_6_axb_1_4066) + ); + XORCY com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_pd_av_o_6_s_1 ( + .CI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_pd_av_o_6_cry_0_3923), + .LI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_pd_av_o_6_axb_1_4066), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_pd_av_o_6[1]) + ); + MULT_AND com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_pd_av_o_6_cry_2 ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_PD_i[2]), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_infinite_PD_i_4078), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_pd_av_o_6_cry_2_0_3924) + ); + MUXCY_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_pd_av_o_6_cry_2_0 ( + .CI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_pd_av_o_6_cry_1_3925), + .DI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_pd_av_o_6_cry_2_0_3924), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_pd_av_o_6_cry_2_3927), + .S(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_pd_av_o_6_axb_2_4065) + ); + XORCY com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_pd_av_o_6_s_2 ( + .CI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_pd_av_o_6_cry_1_3925), + .LI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_pd_av_o_6_axb_2_4065), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_pd_av_o_6[2]) + ); + MULT_AND com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_pd_av_o_6_cry_3 ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_PD_i[3]), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_infinite_PD_i_4078), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_pd_av_o_6_cry_3_0_3926) + ); + MUXCY_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_pd_av_o_6_cry_3_0 ( + .CI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_pd_av_o_6_cry_2_3927), + .DI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_pd_av_o_6_cry_3_0_3926), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_pd_av_o_6_cry_3_3929), + .S(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_pd_av_o_6_axb_3_4064) + ); + XORCY com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_pd_av_o_6_s_3 ( + .CI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_pd_av_o_6_cry_2_3927), + .LI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_pd_av_o_6_axb_3_4064), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_pd_av_o_6[3]) + ); + MULT_AND com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_pd_av_o_6_cry_4 ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_PD_i[4]), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_infinite_PD_i_4078), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_pd_av_o_6_cry_4_0_3928) + ); + MUXCY_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_pd_av_o_6_cry_4_0 ( + .CI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_pd_av_o_6_cry_3_3929), + .DI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_pd_av_o_6_cry_4_0_3928), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_pd_av_o_6_cry_4_3931), + .S(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_pd_av_o_6_axb_4_4063) + ); + XORCY com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_pd_av_o_6_s_4 ( + .CI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_pd_av_o_6_cry_3_3929), + .LI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_pd_av_o_6_axb_4_4063), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_pd_av_o_6[4]) + ); + MULT_AND com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_pd_av_o_6_cry_5 ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_PD_i[5]), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_infinite_PD_i_4078), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_pd_av_o_6_cry_5_0_3930) + ); + MUXCY_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_pd_av_o_6_cry_5_0 ( + .CI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_pd_av_o_6_cry_4_3931), + .DI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_pd_av_o_6_cry_5_0_3930), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_pd_av_o_6_cry_5_3933), + .S(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_pd_av_o_6_axb_5_4062) + ); + XORCY com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_pd_av_o_6_s_5 ( + .CI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_pd_av_o_6_cry_4_3931), + .LI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_pd_av_o_6_axb_5_4062), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_pd_av_o_6[5]) + ); + MULT_AND com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_pd_av_o_6_cry_6 ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_PD_i[6]), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_infinite_PD_i_4078), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_pd_av_o_6_cry_6_0_3932) + ); + MUXCY_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_pd_av_o_6_cry_6_0 ( + .CI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_pd_av_o_6_cry_5_3933), + .DI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_pd_av_o_6_cry_6_0_3932), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_pd_av_o_6_cry_6_3935), + .S(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_pd_av_o_6_axb_6_4061) + ); + XORCY com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_pd_av_o_6_s_6 ( + .CI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_pd_av_o_6_cry_5_3933), + .LI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_pd_av_o_6_axb_6_4061), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_pd_av_o_6[6]) + ); + MULT_AND com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_pd_av_o_6_cry_7 ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_PD_i[7]), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_infinite_PD_i_4078), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_pd_av_o_6_cry_7_0_3934) + ); + MUXCY_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_pd_av_o_6_cry_7_0 ( + .CI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_pd_av_o_6_cry_6_3935), + .DI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_pd_av_o_6_cry_7_0_3934), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_pd_av_o_6_cry_7_3937), + .S(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_pd_av_o_6_axb_7_4060) + ); + XORCY com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_pd_av_o_6_s_7 ( + .CI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_pd_av_o_6_cry_6_3935), + .LI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_pd_av_o_6_axb_7_4060), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_pd_av_o_6[7]) + ); + MULT_AND com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_pd_av_o_6_cry_8 ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_PD_i[8]), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_infinite_PD_i_4078), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_pd_av_o_6_cry_8_0_3936) + ); + MUXCY_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_pd_av_o_6_cry_8_0 ( + .CI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_pd_av_o_6_cry_7_3937), + .DI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_pd_av_o_6_cry_8_0_3936), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_pd_av_o_6_cry_8_3939), + .S(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_pd_av_o_6_axb_8_4059) + ); + XORCY com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_pd_av_o_6_s_8 ( + .CI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_pd_av_o_6_cry_7_3937), + .LI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_pd_av_o_6_axb_8_4059), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_pd_av_o_6[8]) + ); + MULT_AND com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_pd_av_o_6_cry_9 ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_PD_i[9]), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_infinite_PD_i_4078), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_pd_av_o_6_cry_9_0_3938) + ); + MUXCY_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_pd_av_o_6_cry_9_0 ( + .CI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_pd_av_o_6_cry_8_3939), + .DI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_pd_av_o_6_cry_9_0_3938), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_pd_av_o_6_cry_9_3941), + .S(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_pd_av_o_6_axb_9_4058) + ); + XORCY com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_pd_av_o_6_s_9 ( + .CI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_pd_av_o_6_cry_8_3939), + .LI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_pd_av_o_6_axb_9_4058), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_pd_av_o_6[9]) + ); + MULT_AND com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_pd_av_o_6_cry_10 ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_PD_i[10]), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_infinite_PD_i_4078), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_pd_av_o_6_cry_10_0_3940) + ); + MUXCY_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_pd_av_o_6_cry_10_0 ( + .CI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_pd_av_o_6_cry_9_3941), + .DI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_pd_av_o_6_cry_10_0_3940), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_pd_av_o_6_cry_10_3942), + .S(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_pd_av_o_6_axb_10_4057) + ); + XORCY com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_pd_av_o_6_s_10 ( + .CI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_pd_av_o_6_cry_9_3941), + .LI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_pd_av_o_6_axb_10_4057), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_pd_av_o_6[10]) + ); + XORCY com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_pd_av_o_6_s_11 ( + .CI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_pd_av_o_6_cry_10_3942), + .LI(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_pd_av_o_6_axb_11_4083), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_pd_av_o_6[11]) + ); + FDR com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_suspend_cat_1_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_suspend_cat[0]), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_suspend_cat[1]), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_suspend_cat_0_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_N_70880_i_3964), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_suspend_cat[0]), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_init_cpl ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_init_cplc_3946), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_init_cpl_3963), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_init_np ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_init_npc_3947), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_init_np_3960), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_init_p ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_init_pc_3948), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_init_p_3957), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_init_vld_qq ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_init_vld_q_3949), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_init_vld_qq_3980), + .R(plm_link_up_i) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un8_suspend_cat_axbxc1.INIT = 4'h6; + LUT2 com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un8_suspend_cat_axbxc1 ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_suspend_cat[0]), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_suspend_cat[1]), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un8_suspend_cat_axbxc1_3999) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_infinite_header_q_2_0_a2_0.INIT = 4'h1; + LUT2 com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_infinite_header_q_2_0_a2_0 ( + .I0(com_lnk_rfc_header[0]), + .I1(com_lnk_rfc_header[1]), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_infinite_header_q_2_0_a2_0_3966) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_prev_limit_header_q_5_0_0_7_.INIT = 8'hD8; + LUT3_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_prev_limit_header_q_5_0_0_7_ ( + .I0(com_lnk_rfc_type[0]), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_limit_NPH[7]), + .I2(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_limit_PH[7]), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_prev_limit_header_q_5_0_0[7]) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_prev_limit_header_q_5_0_0_6_.INIT = 8'hD8; + LUT3_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_prev_limit_header_q_5_0_0_6_ ( + .I0(com_lnk_rfc_type[0]), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_limit_NPH[6]), + .I2(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_limit_PH[6]), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_prev_limit_header_q_5_0_0[6]) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_prev_limit_header_q_5_0_0_5_.INIT = 8'hD8; + LUT3_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_prev_limit_header_q_5_0_0_5_ ( + .I0(com_lnk_rfc_type[0]), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_limit_NPH[5]), + .I2(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_limit_PH[5]), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_prev_limit_header_q_5_0_0[5]) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_prev_limit_header_q_5_0_0_4_.INIT = 8'hD8; + LUT3_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_prev_limit_header_q_5_0_0_4_ ( + .I0(com_lnk_rfc_type[0]), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_limit_NPH[4]), + .I2(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_limit_PH[4]), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_prev_limit_header_q_5_0_0[4]) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_prev_limit_header_q_5_0_0_3_.INIT = 8'hD8; + LUT3_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_prev_limit_header_q_5_0_0_3_ ( + .I0(com_lnk_rfc_type[0]), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_limit_NPH[3]), + .I2(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_limit_PH[3]), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_prev_limit_header_q_5_0_0[3]) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_prev_limit_header_q_5_0_0_2_.INIT = 8'hD8; + LUT3_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_prev_limit_header_q_5_0_0_2_ ( + .I0(com_lnk_rfc_type[0]), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_limit_NPH[2]), + .I2(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_limit_PH[2]), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_prev_limit_header_q_5_0_0[2]) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_prev_limit_header_q_5_0_0_1_.INIT = 8'hD8; + LUT3_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_prev_limit_header_q_5_0_0_1_ ( + .I0(com_lnk_rfc_type[0]), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_limit_NPH[1]), + .I2(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_limit_PH[1]), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_prev_limit_header_q_5_0_0[1]) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_prev_limit_header_q_5_0_0_0_.INIT = 8'hD8; + LUT3_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_prev_limit_header_q_5_0_0_0_ ( + .I0(com_lnk_rfc_type[0]), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_limit_NPH[0]), + .I2(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_limit_PH[0]), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_prev_limit_header_q_5_0_0[0]) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_prev_limit_data_q_5_0_0_11_.INIT = 8'hD8; + LUT3_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_prev_limit_data_q_5_0_0_11_ ( + .I0(com_lnk_rfc_type[0]), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_limit_NPD[11]), + .I2(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_limit_PD[11]), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_prev_limit_data_q_5_0_0[11]) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_prev_limit_data_q_5_0_0_10_.INIT = 8'hD8; + LUT3_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_prev_limit_data_q_5_0_0_10_ ( + .I0(com_lnk_rfc_type[0]), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_limit_NPD[10]), + .I2(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_limit_PD[10]), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_prev_limit_data_q_5_0_0[10]) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_prev_limit_data_q_5_0_0_9_.INIT = 8'hD8; + LUT3_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_prev_limit_data_q_5_0_0_9_ ( + .I0(com_lnk_rfc_type[0]), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_limit_NPD[9]), + .I2(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_limit_PD[9]), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_prev_limit_data_q_5_0_0[9]) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_prev_limit_data_q_5_0_0_8_.INIT = 8'hD8; + LUT3_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_prev_limit_data_q_5_0_0_8_ ( + .I0(com_lnk_rfc_type[0]), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_limit_NPD[8]), + .I2(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_limit_PD[8]), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_prev_limit_data_q_5_0_0[8]) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_prev_limit_data_q_5_0_0_7_.INIT = 8'hD8; + LUT3_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_prev_limit_data_q_5_0_0_7_ ( + .I0(com_lnk_rfc_type[0]), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_limit_NPD[7]), + .I2(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_limit_PD[7]), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_prev_limit_data_q_5_0_0[7]) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_prev_limit_data_q_5_0_0_6_.INIT = 8'hD8; + LUT3_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_prev_limit_data_q_5_0_0_6_ ( + .I0(com_lnk_rfc_type[0]), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_limit_NPD[6]), + .I2(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_limit_PD[6]), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_prev_limit_data_q_5_0_0[6]) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_prev_limit_data_q_5_0_0_5_.INIT = 8'hD8; + LUT3_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_prev_limit_data_q_5_0_0_5_ ( + .I0(com_lnk_rfc_type[0]), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_limit_NPD[5]), + .I2(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_limit_PD[5]), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_prev_limit_data_q_5_0_0[5]) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_prev_limit_data_q_5_0_0_4_.INIT = 8'hD8; + LUT3_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_prev_limit_data_q_5_0_0_4_ ( + .I0(com_lnk_rfc_type[0]), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_limit_NPD[4]), + .I2(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_limit_PD[4]), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_prev_limit_data_q_5_0_0[4]) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_prev_limit_data_q_5_0_0_3_.INIT = 8'hD8; + LUT3_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_prev_limit_data_q_5_0_0_3_ ( + .I0(com_lnk_rfc_type[0]), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_limit_NPD[3]), + .I2(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_limit_PD[3]), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_prev_limit_data_q_5_0_0[3]) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_prev_limit_data_q_5_0_0_2_.INIT = 8'hD8; + LUT3_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_prev_limit_data_q_5_0_0_2_ ( + .I0(com_lnk_rfc_type[0]), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_limit_NPD[2]), + .I2(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_limit_PD[2]), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_prev_limit_data_q_5_0_0[2]) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_prev_limit_data_q_5_0_0_1_.INIT = 8'hD8; + LUT3_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_prev_limit_data_q_5_0_0_1_ ( + .I0(com_lnk_rfc_type[0]), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_limit_NPD[1]), + .I2(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_limit_PD[1]), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_prev_limit_data_q_5_0_0[1]) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_prev_limit_data_q_5_0_0_0_.INIT = 8'hD8; + LUT3_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_prev_limit_data_q_5_0_0_0_ ( + .I0(com_lnk_rfc_type[0]), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_limit_NPD[0]), + .I2(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_limit_PD[0]), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_prev_limit_data_q_5_0_0[0]) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_infinite_header_q_5_0_0.INIT = 8'hD8; + LUT3_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_infinite_header_q_5_0_0 ( + .I0(com_lnk_rfc_type[0]), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_infinite_NPH_3951), + .I2(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_infinite_PH_3950), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_infinite_header_q_5_0_0_3973) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_infinite_data_q_5_0_0.INIT = 8'hD8; + LUT3_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_infinite_data_q_5_0_0 ( + .I0(com_lnk_rfc_type[0]), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_infinite_NPD_4082), + .I2(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_infinite_PD_4084), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_infinite_data_q_5_0_0_3974) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_new_limit_data_ok_0.INIT = 8'hD1; + LUT3_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_new_limit_data_ok_0 ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_fc_diff_data_q[11]), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_infinite_data_qq_4073), + .I2(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_infinite_data_qq_4069), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_new_limit_data_ok) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_av_data_cred_7_i_0_a3_0_0_.INIT = 4'h4; + LUT2 com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_av_data_cred_7_i_0_a3_0_0_ ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_suspend_cat[0]), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_suspend_cat[1]), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_N_61373) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_PD_1_axb_0.INIT = 8'h78; + LUT3 com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_PD_1_axb_0 ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_consumed_credits[0]), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_consumed_ph_3620), + .I2(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_PD[0]), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_PD_1_axb_0_3943) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_NPD_1_axb_0.INIT = 8'h78; + LUT3 com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_NPD_1_axb_0 ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_consumed_credits[0]), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_consumed_nph_3619), + .I2(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_NPD[0]), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_NPD_1_axb_0_3944) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_CPLD_1_axb_0.INIT = 8'h78; + LUT3 com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_CPLD_1_axb_0 ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_consumed_cplh_3621), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_consumed_credits[0]), + .I2(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_CPLD[0]), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_CPLD_1_axb_0_3945) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_init_cplc.INIT = 8'h40; + LUT3 com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_init_cplc ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_cat_q[0]), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_cat_q[1]), + .I2(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_init_vld_q_3949), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_init_cplc_3946) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_init_npc.INIT = 8'h20; + LUT3 com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_init_npc ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_cat_q[0]), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_cat_q[1]), + .I2(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_init_vld_q_3949), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_init_npc_3947) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_init_pc.INIT = 8'h10; + LUT3 com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_init_pc ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_cat_q[0]), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_cat_q[1]), + .I2(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_init_vld_q_3949), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_init_pc_3948) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_infinite_header_q_2_0_a2_4.INIT = 16'h0001; + LUT4 com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_infinite_header_q_2_0_a2_4 ( + .I0(com_lnk_rfc_header[4]), + .I1(com_lnk_rfc_header[5]), + .I2(com_lnk_rfc_header[6]), + .I3(com_lnk_rfc_header[7]), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_infinite_header_q_2_0_a2_4_3965) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_infinite_data_q_2_0_a2_6.INIT = 16'h0001; + LUT4 com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_infinite_data_q_2_0_a2_6 ( + .I0(com_lnk_rfc_data[0]), + .I1(com_lnk_rfc_data[1]), + .I2(com_lnk_rfc_data[2]), + .I3(com_lnk_rfc_data[3]), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_infinite_data_q_2_0_a2_6_3969) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_infinite_data_q_2_0_a2_7.INIT = 16'h0001; + LUT4 com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_infinite_data_q_2_0_a2_7 ( + .I0(com_lnk_rfc_data[8]), + .I1(com_lnk_rfc_data[9]), + .I2(com_lnk_rfc_data[10]), + .I3(com_lnk_rfc_data[11]), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_infinite_data_q_2_0_a2_7_3968) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_infinite_data_q_2_0_a2_8.INIT = 16'h0001; + LUT4 com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_infinite_data_q_2_0_a2_8 ( + .I0(com_lnk_rfc_data[4]), + .I1(com_lnk_rfc_data[5]), + .I2(com_lnk_rfc_data[6]), + .I3(com_lnk_rfc_data[7]), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_infinite_data_q_2_0_a2_8_3967) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_ph_av_o_6_0.INIT = 8'h21; + LUT3 com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_ph_av_o_6_0 ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_PH[6]), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_infinite_PH_3950), + .I2(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_limit_PH[6]), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_ph_av_o_6_0_3996) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_ph_av_o_6_1.INIT = 16'h8421; + LUT4 com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_ph_av_o_6_1 ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_PH[4]), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_PH[5]), + .I2(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_limit_PH[4]), + .I3(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_limit_PH[5]), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_ph_av_o_6_1_3995) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_ph_av_o_6_2.INIT = 16'h8421; + LUT4 com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_ph_av_o_6_2 ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_PH[3]), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_PH[7]), + .I2(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_limit_PH[3]), + .I3(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_limit_PH[7]), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_ph_av_o_6_2_3994) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_ph_av_o_6_3.INIT = 16'h8421; + LUT4_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_ph_av_o_6_3 ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_PH[1]), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_PH[2]), + .I2(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_limit_PH[1]), + .I3(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_limit_PH[2]), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_ph_av_o_6_3_3952) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_nph_av_o_6_0.INIT = 8'h21; + LUT3 com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_nph_av_o_6_0 ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_NPH[6]), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_infinite_NPH_3951), + .I2(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_limit_NPH[6]), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_nph_av_o_6_0_3991) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_nph_av_o_6_1.INIT = 16'h8421; + LUT4 com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_nph_av_o_6_1 ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_NPH[4]), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_NPH[5]), + .I2(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_limit_NPH[4]), + .I3(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_limit_NPH[5]), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_nph_av_o_6_1_3990) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_nph_av_o_6_2.INIT = 16'h8421; + LUT4 com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_nph_av_o_6_2 ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_NPH[3]), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_NPH[7]), + .I2(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_limit_NPH[3]), + .I3(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_limit_NPH[7]), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_nph_av_o_6_2_3989) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_nph_av_o_6_3.INIT = 16'h8421; + LUT4_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_nph_av_o_6_3 ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_NPH[1]), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_NPH[2]), + .I2(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_limit_NPH[1]), + .I3(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_limit_NPH[2]), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_nph_av_o_6_3_3953) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_infinite_CPLH_0.INIT = 8'h21; + LUT3 com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_infinite_CPLH_0 ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_CPLH[6]), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_infinite_CPLH_3972), + .I2(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_limit_CPLH[6]), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_infinite_CPLH_0_3986) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_infinite_CPLH_1.INIT = 16'h8421; + LUT4 com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_infinite_CPLH_1 ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_CPLH[4]), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_CPLH[5]), + .I2(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_limit_CPLH[4]), + .I3(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_limit_CPLH[5]), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_infinite_CPLH_1_3985) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_infinite_CPLH_2.INIT = 16'h8421; + LUT4 com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_infinite_CPLH_2 ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_CPLH[3]), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_CPLH[7]), + .I2(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_limit_CPLH[3]), + .I3(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_limit_CPLH[7]), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_infinite_CPLH_2_3984) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_infinite_CPLH_3.INIT = 16'h8421; + LUT4_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_infinite_CPLH_3 ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_CPLH[1]), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_CPLH[2]), + .I2(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_limit_CPLH[1]), + .I3(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_limit_CPLH[2]), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_infinite_CPLH_3_3954) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_av_hdr_cred_7_iv_i_0_0_0.INIT = 16'h135F; + LUT4 com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_av_hdr_cred_7_iv_i_0_0_0 ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_cplh_av), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_suspend_cat[0]), + .I2(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_suspend_cat[1]), + .I3(com_tlm_u_tlm_tx_vc0_frm_seq_nph_av), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_av_hdr_cred_7_iv_i_0_0_0_3998) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_new_limit_header_ok_3_0_a2.INIT = 16'hD010; + LUT4 com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_new_limit_header_ok_3_0_a2 ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_fc_diff_header_q[7]), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_infinite_header_qq_4072), + .I2(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_new_limit_data_ok), + .I3(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_infinite_header_qq_4068), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_new_limit_header_ok_3_0_a2_3981) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_ph_av_o_6_4.INIT = 8'h90; + LUT3_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_ph_av_o_6_4 ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_PH[0]), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_limit_PH[0]), + .I2(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_ph_av_o_6_3_3952), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_ph_av_o_6_4_3993) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_nph_av_o_6_4.INIT = 8'h90; + LUT3_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_nph_av_o_6_4 ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_NPH[0]), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_limit_NPH[0]), + .I2(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_nph_av_o_6_3_3953), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_nph_av_o_6_4_3988) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_infinite_CPLH_4.INIT = 8'h90; + LUT3_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_infinite_CPLH_4 ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_CPLH[0]), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_limit_CPLH[0]), + .I2(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_infinite_CPLH_3_3954), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_infinite_CPLH_4_3983) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_av_data_cred_7_i_0_0_1_.INIT = 16'hFD64; + LUT4 com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_av_data_cred_7_i_0_0_1_ ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_suspend_cat[0]), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_suspend_cat[1]), + .I2(com_tlm_u_tlm_tx_vc0_frm_seq_npd_av[1]), + .I3(com_tlm_u_tlm_tx_vc0_frm_seq_pd_av_1_), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_av_data_cred_7_i_0_0[1]) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_av_data_cred_7_i_0_0_4_.INIT = 16'hFD64; + LUT4 com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_av_data_cred_7_i_0_0_4_ ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_suspend_cat[0]), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_suspend_cat[1]), + .I2(com_tlm_u_tlm_tx_vc0_frm_seq_npd_av[4]), + .I3(com_tlm_u_tlm_tx_vc0_frm_seq_pd_av_4_), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_av_data_cred_7_i_0_0[4]) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_av_data_cred_7_i_0_0_7_.INIT = 16'hFD64; + LUT4 com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_av_data_cred_7_i_0_0_7_ ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_suspend_cat[0]), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_suspend_cat[1]), + .I2(com_tlm_u_tlm_tx_vc0_frm_seq_npd_av[7]), + .I3(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_pd_av[7]), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_av_data_cred_7_i_0_0[7]) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_av_data_cred_7_i_0_0_5_.INIT = 16'hFD64; + LUT4 com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_av_data_cred_7_i_0_0_5_ ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_suspend_cat[0]), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_suspend_cat[1]), + .I2(com_tlm_u_tlm_tx_vc0_frm_seq_npd_av[5]), + .I3(com_tlm_u_tlm_tx_vc0_frm_seq_pd_av_5_), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_av_data_cred_7_i_0_0[5]) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_av_data_cred_7_i_0_0_11_.INIT = 16'hFD64; + LUT4 com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_av_data_cred_7_i_0_0_11_ ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_suspend_cat[0]), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_suspend_cat[1]), + .I2(com_tlm_u_tlm_tx_vc0_frm_seq_npd_av[11]), + .I3(com_tlm_u_tlm_tx_vc0_frm_seq_pd_av_11_), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_av_data_cred_7_i_0_0[11]) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_av_data_cred_7_i_0_0_9_.INIT = 16'hFD64; + LUT4 com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_av_data_cred_7_i_0_0_9_ ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_suspend_cat[0]), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_suspend_cat[1]), + .I2(com_tlm_u_tlm_tx_vc0_frm_seq_npd_av[9]), + .I3(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_pd_av[9]), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_av_data_cred_7_i_0_0[9]) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_av_data_cred_7_i_0_0_0_.INIT = 16'hFD64; + LUT4 com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_av_data_cred_7_i_0_0_0_ ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_suspend_cat[0]), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_suspend_cat[1]), + .I2(com_tlm_u_tlm_tx_vc0_frm_seq_npd_av[0]), + .I3(com_tlm_u_tlm_tx_vc0_frm_seq_pd_av_0_), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_av_data_cred_7_i_0_0[0]) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_av_data_cred_7_i_0_0_6_.INIT = 16'hFD64; + LUT4 com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_av_data_cred_7_i_0_0_6_ ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_suspend_cat[0]), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_suspend_cat[1]), + .I2(com_tlm_u_tlm_tx_vc0_frm_seq_npd_av[6]), + .I3(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_pd_av[6]), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_av_data_cred_7_i_0_0[6]) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_av_data_cred_7_i_0_0_10_.INIT = 16'hFD64; + LUT4 com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_av_data_cred_7_i_0_0_10_ ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_suspend_cat[0]), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_suspend_cat[1]), + .I2(com_tlm_u_tlm_tx_vc0_frm_seq_npd_av[10]), + .I3(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_pd_av[10]), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_av_data_cred_7_i_0_0[10]) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_av_data_cred_7_i_0_0_2_.INIT = 16'hFD64; + LUT4 com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_av_data_cred_7_i_0_0_2_ ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_suspend_cat[0]), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_suspend_cat[1]), + .I2(com_tlm_u_tlm_tx_vc0_frm_seq_npd_av[2]), + .I3(com_tlm_u_tlm_tx_vc0_frm_seq_pd_av_2_), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_av_data_cred_7_i_0_0[2]) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_av_data_cred_7_i_0_0_3_.INIT = 16'hFD64; + LUT4 com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_av_data_cred_7_i_0_0_3_ ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_suspend_cat[0]), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_suspend_cat[1]), + .I2(com_tlm_u_tlm_tx_vc0_frm_seq_npd_av[3]), + .I3(com_tlm_u_tlm_tx_vc0_frm_seq_pd_av_3_), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_av_data_cred_7_i_0_0[3]) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_av_data_cred_7_i_0_0_8_.INIT = 16'hFD64; + LUT4 com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_av_data_cred_7_i_0_0_8_ ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_suspend_cat[0]), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_suspend_cat[1]), + .I2(com_tlm_u_tlm_tx_vc0_frm_seq_npd_av[8]), + .I3(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_pd_av[8]), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_av_data_cred_7_i_0_0[8]) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_N_87844_i.INIT = 8'hEC; + LUT3 com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_N_87844_i ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_new_limit_header_ok_3_0_a2_3981), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_init_p_3957), + .I2(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_update_p_3956), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_N_87844_i_3955) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_N_87845_i.INIT = 8'hEC; + LUT3 com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_N_87845_i ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_new_limit_header_ok_3_0_a2_3981), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_init_np_3960), + .I2(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_update_np_3959), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_N_87845_i_3958) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_N_87846_i.INIT = 8'hEC; + LUT3 com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_N_87846_i ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_new_limit_header_ok_3_0_a2_3981), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_init_cpl_3963), + .I2(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_update_cpl_3962), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_N_87846_i_3961) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_N_70880_i.INIT = 4'h1; + LUT1_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_N_70880_i ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un8_suspend_cat_axbxc1_3999), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_N_70880_i_3964) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_infinite_header_q_2_0_a2.INIT = 16'h1000; + LUT4_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_infinite_header_q_2_0_a2 ( + .I0(com_lnk_rfc_header[2]), + .I1(com_lnk_rfc_header[3]), + .I2(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_infinite_header_q_2_0_a2_0_3966), + .I3(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_infinite_header_q_2_0_a2_4_3965), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_infinite_header_q_2) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_infinite_data_q_2_0_a2.INIT = 8'h80; + LUT3_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_infinite_data_q_2_0_a2 ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_infinite_data_q_2_0_a2_6_3969), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_infinite_data_q_2_0_a2_7_3968), + .I2(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_infinite_data_q_2_0_a2_8_3967), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_infinite_data_q_2) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_fc_diff_data_axb_11.INIT = 4'h9; + LUT2_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_fc_diff_data_axb_11 ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_prev_limit_data_q[11]), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_data_q[11]), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_fc_diff_data_axb_11_3970) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_fc_diff_header_axb_7.INIT = 4'h9; + LUT2_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_fc_diff_header_axb_7 ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_prev_limit_header_q[7]), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_header_q[7]), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_fc_diff_header_axb_7_3971) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_infinite_header_q_5_u_0.INIT = 8'hE2; + LUT3_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_infinite_header_q_5_u_0 ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_infinite_header_q_5_0_0_3973), + .I1(com_lnk_rfc_type[1]), + .I2(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_infinite_CPLH_3972), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_infinite_header_q_5) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_infinite_data_q_5_u_0.INIT = 8'hE2; + LUT3_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_infinite_data_q_5_u_0 ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_infinite_data_q_5_0_0_3974), + .I1(com_lnk_rfc_type[1]), + .I2(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_infinite_CPLD_4080), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_infinite_data_q_5) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_prev_limit_data_q_5_1_1_.INIT = 8'hE2; + LUT3_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_prev_limit_data_q_5_1_1_ ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_prev_limit_data_q_5_0_0[1]), + .I1(com_lnk_rfc_type[1]), + .I2(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_limit_CPLD[1]), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_prev_limit_data_q_5[1]) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_prev_limit_data_q_5_1_0_.INIT = 8'hE2; + LUT3_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_prev_limit_data_q_5_1_0_ ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_prev_limit_data_q_5_0_0[0]), + .I1(com_lnk_rfc_type[1]), + .I2(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_limit_CPLD[0]), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_prev_limit_data_q_5[0]) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_prev_limit_header_q_5_1_4_.INIT = 8'hE2; + LUT3_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_prev_limit_header_q_5_1_4_ ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_prev_limit_header_q_5_0_0[4]), + .I1(com_lnk_rfc_type[1]), + .I2(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_limit_CPLH[4]), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_prev_limit_header_q_5[4]) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_prev_limit_header_q_5_1_3_.INIT = 8'hE2; + LUT3_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_prev_limit_header_q_5_1_3_ ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_prev_limit_header_q_5_0_0[3]), + .I1(com_lnk_rfc_type[1]), + .I2(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_limit_CPLH[3]), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_prev_limit_header_q_5[3]) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_prev_limit_header_q_5_1_2_.INIT = 8'hE2; + LUT3_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_prev_limit_header_q_5_1_2_ ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_prev_limit_header_q_5_0_0[2]), + .I1(com_lnk_rfc_type[1]), + .I2(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_limit_CPLH[2]), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_prev_limit_header_q_5[2]) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_prev_limit_header_q_5_1_1_.INIT = 8'hE2; + LUT3_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_prev_limit_header_q_5_1_1_ ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_prev_limit_header_q_5_0_0[1]), + .I1(com_lnk_rfc_type[1]), + .I2(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_limit_CPLH[1]), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_prev_limit_header_q_5[1]) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_prev_limit_header_q_5_1_0_.INIT = 8'hE2; + LUT3_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_prev_limit_header_q_5_1_0_ ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_prev_limit_header_q_5_0_0[0]), + .I1(com_lnk_rfc_type[1]), + .I2(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_limit_CPLH[0]), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_prev_limit_header_q_5[0]) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_prev_limit_data_q_5_1_11_.INIT = 8'hE2; + LUT3_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_prev_limit_data_q_5_1_11_ ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_prev_limit_data_q_5_0_0[11]), + .I1(com_lnk_rfc_type[1]), + .I2(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_limit_CPLD[11]), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_prev_limit_data_q_5[11]) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_prev_limit_data_q_5_1_10_.INIT = 8'hE2; + LUT3_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_prev_limit_data_q_5_1_10_ ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_prev_limit_data_q_5_0_0[10]), + .I1(com_lnk_rfc_type[1]), + .I2(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_limit_CPLD[10]), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_prev_limit_data_q_5[10]) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_prev_limit_data_q_5_1_9_.INIT = 8'hE2; + LUT3_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_prev_limit_data_q_5_1_9_ ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_prev_limit_data_q_5_0_0[9]), + .I1(com_lnk_rfc_type[1]), + .I2(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_limit_CPLD[9]), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_prev_limit_data_q_5[9]) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_prev_limit_data_q_5_1_8_.INIT = 8'hE2; + LUT3_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_prev_limit_data_q_5_1_8_ ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_prev_limit_data_q_5_0_0[8]), + .I1(com_lnk_rfc_type[1]), + .I2(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_limit_CPLD[8]), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_prev_limit_data_q_5[8]) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_prev_limit_data_q_5_1_7_.INIT = 8'hE2; + LUT3_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_prev_limit_data_q_5_1_7_ ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_prev_limit_data_q_5_0_0[7]), + .I1(com_lnk_rfc_type[1]), + .I2(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_limit_CPLD[7]), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_prev_limit_data_q_5[7]) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_prev_limit_data_q_5_1_6_.INIT = 8'hE2; + LUT3_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_prev_limit_data_q_5_1_6_ ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_prev_limit_data_q_5_0_0[6]), + .I1(com_lnk_rfc_type[1]), + .I2(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_limit_CPLD[6]), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_prev_limit_data_q_5[6]) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_prev_limit_data_q_5_1_5_.INIT = 8'hE2; + LUT3_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_prev_limit_data_q_5_1_5_ ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_prev_limit_data_q_5_0_0[5]), + .I1(com_lnk_rfc_type[1]), + .I2(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_limit_CPLD[5]), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_prev_limit_data_q_5[5]) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_prev_limit_data_q_5_1_4_.INIT = 8'hE2; + LUT3_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_prev_limit_data_q_5_1_4_ ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_prev_limit_data_q_5_0_0[4]), + .I1(com_lnk_rfc_type[1]), + .I2(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_limit_CPLD[4]), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_prev_limit_data_q_5[4]) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_prev_limit_data_q_5_1_3_.INIT = 8'hE2; + LUT3_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_prev_limit_data_q_5_1_3_ ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_prev_limit_data_q_5_0_0[3]), + .I1(com_lnk_rfc_type[1]), + .I2(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_limit_CPLD[3]), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_prev_limit_data_q_5[3]) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_prev_limit_data_q_5_1_2_.INIT = 8'hE2; + LUT3_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_prev_limit_data_q_5_1_2_ ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_prev_limit_data_q_5_0_0[2]), + .I1(com_lnk_rfc_type[1]), + .I2(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_limit_CPLD[2]), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_prev_limit_data_q_5[2]) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_prev_limit_header_q_5_1_7_.INIT = 8'hE2; + LUT3_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_prev_limit_header_q_5_1_7_ ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_prev_limit_header_q_5_0_0[7]), + .I1(com_lnk_rfc_type[1]), + .I2(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_limit_CPLH[7]), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_prev_limit_header_q_5[7]) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_prev_limit_header_q_5_1_6_.INIT = 8'hE2; + LUT3_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_prev_limit_header_q_5_1_6_ ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_prev_limit_header_q_5_0_0[6]), + .I1(com_lnk_rfc_type[1]), + .I2(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_limit_CPLH[6]), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_prev_limit_header_q_5[6]) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_prev_limit_header_q_5_1_5_.INIT = 8'hE2; + LUT3_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_prev_limit_header_q_5_1_5_ ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_prev_limit_header_q_5_0_0[5]), + .I1(com_lnk_rfc_type[1]), + .I2(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_limit_CPLH[5]), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_prev_limit_header_q_5[5]) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_N_16839_i.INIT = 8'hFE; + LUT3_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_N_16839_i ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_consumed_cplh_3621), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_consumed_nph_3619), + .I2(com_tlm_u_tlm_tx_vc0_frm_seq_consumed_ph_3620), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_N_16839_i_3975) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_suspend_rdy_o_3.INIT = 8'h80; + LUT3_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_suspend_rdy_o_3 ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_credits_ok[0]), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_credits_ok[1]), + .I2(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_credits_ok[2]), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_suspend_rdy_o_3_3976) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_update_cpl_3_0_a2.INIT = 8'h40; + LUT3_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_update_cpl_3_0_a2 ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_cat_q[0]), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_cat_q[1]), + .I2(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_update_vld_q_3977), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_update_cpl_3) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_update_np_3_0_a2.INIT = 8'h20; + LUT3_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_update_np_3_0_a2 ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_cat_q[0]), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_cat_q[1]), + .I2(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_update_vld_q_3977), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_update_np_3) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_update_p_3_0_a2.INIT = 8'h10; + LUT3_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_update_p_3_0_a2 ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_cat_q[0]), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_cat_q[1]), + .I2(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_update_vld_q_3977), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_update_p_3) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_av_valid_o_4_0_a2.INIT = 16'h0001; + LUT4_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_av_valid_o_4_0_a2 ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_consumed_cplh_3621), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_consumed_nph_3619), + .I2(com_tlm_u_tlm_tx_vc0_frm_seq_consumed_ph_3620), + .I3(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_q_3978), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_av_valid_o_4) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_err_fc_o13_0_a2.INIT = 8'h54; + LUT3_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_err_fc_o13_0_a2 ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_new_limit_header_ok_3_0_a2_3981), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_init_vld_qq_3980), + .I2(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_update_vld_qq_3979), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_err_fc_o13) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_N_9377_i.INIT = 16'h7FFF; + LUT4_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_N_9377_i ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_infinite_CPLH_0_3986), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_infinite_CPLH_1_3985), + .I2(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_infinite_CPLH_2_3984), + .I3(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_infinite_CPLH_4_3983), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_N_9377_i_3982) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_N_9379_i.INIT = 16'h7FFF; + LUT4_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_N_9379_i ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_nph_av_o_6_0_3991), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_nph_av_o_6_1_3990), + .I2(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_nph_av_o_6_2_3989), + .I3(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_nph_av_o_6_4_3988), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_N_9379_i_3987) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_N_9378_i.INIT = 16'h7FFF; + LUT4_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_N_9378_i ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_ph_av_o_6_0_3996), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_ph_av_o_6_1_3995), + .I2(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_ph_av_o_6_2_3994), + .I3(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_ph_av_o_6_4_3993), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_N_9378_i_3992) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_av_data_cred_7_i_0_11_.INIT = 8'hD0; + LUT3_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_av_data_cred_7_i_0_11_ ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_N_61373), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_cpld_av_11_), + .I2(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_av_data_cred_7_i_0_0[11]), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_N_32455_i) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_av_data_cred_7_i_0_10_.INIT = 8'hD0; + LUT3_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_av_data_cred_7_i_0_10_ ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_N_61373), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_cpld_av[10]), + .I2(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_av_data_cred_7_i_0_0[10]), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_N_32453_i) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_av_data_cred_7_i_0_9_.INIT = 8'hD0; + LUT3_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_av_data_cred_7_i_0_9_ ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_N_61373), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_cpld_av[9]), + .I2(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_av_data_cred_7_i_0_0[9]), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_N_32451_i) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_av_data_cred_7_i_0_8_.INIT = 8'hD0; + LUT3_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_av_data_cred_7_i_0_8_ ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_N_61373), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_cpld_av[8]), + .I2(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_av_data_cred_7_i_0_0[8]), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_N_32449_i) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_av_data_cred_7_i_0_7_.INIT = 8'hD0; + LUT3_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_av_data_cred_7_i_0_7_ ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_N_61373), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_cpld_av[7]), + .I2(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_av_data_cred_7_i_0_0[7]), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_N_32447_i) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_av_data_cred_7_i_0_6_.INIT = 8'hD0; + LUT3_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_av_data_cred_7_i_0_6_ ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_N_61373), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_cpld_av[6]), + .I2(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_av_data_cred_7_i_0_0[6]), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_N_32445_i) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_av_data_cred_7_i_0_5_.INIT = 8'hD0; + LUT3_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_av_data_cred_7_i_0_5_ ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_N_61373), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_cpld_av_5_), + .I2(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_av_data_cred_7_i_0_0[5]), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_N_32443_i) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_av_data_cred_7_i_0_4_.INIT = 8'hD0; + LUT3_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_av_data_cred_7_i_0_4_ ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_N_61373), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_cpld_av_4_), + .I2(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_av_data_cred_7_i_0_0[4]), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_N_32441_i) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_av_data_cred_7_i_0_3_.INIT = 8'hD0; + LUT3_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_av_data_cred_7_i_0_3_ ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_N_61373), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_cpld_av_3_), + .I2(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_av_data_cred_7_i_0_0[3]), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_N_32439_i) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_av_data_cred_7_i_0_2_.INIT = 8'hD0; + LUT3_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_av_data_cred_7_i_0_2_ ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_N_61373), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_cpld_av_2_), + .I2(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_av_data_cred_7_i_0_0[2]), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_N_32437_i) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_av_data_cred_7_i_0_1_.INIT = 8'hD0; + LUT3_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_av_data_cred_7_i_0_1_ ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_N_61373), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_cpld_av_1_), + .I2(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_av_data_cred_7_i_0_0[1]), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_N_32435_i) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_av_data_cred_7_i_0_0_.INIT = 8'hD0; + LUT3_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_av_data_cred_7_i_0_0_ ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_N_61373), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_cpld_av_0_), + .I2(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_av_data_cred_7_i_0_0[0]), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_N_32433_i) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_N_85833_i.INIT = 8'h73; + LUT3_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_N_85833_i ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un8_suspend_cat_axbxc1_3999), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_av_hdr_cred_7_iv_i_0_0_0_3998), + .I2(com_tlm_u_tlm_tx_vc0_frm_seq_ph_av), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_N_85833_i_3997) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_credits_ok_3_0_.INIT = 4'h2; + LUT2_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_credits_ok_3_0_ ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_av_hdr_cred_4001), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un7_credits_ok_cry_11_4000), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_credits_ok_3[0]) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_CPLD_1_axb_11.INIT = 4'h2; + LUT1_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_CPLD_1_axb_11 ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_CPLD[11]), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_CPLD_1_axb_11_4002) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_CPLD_1_axb_10.INIT = 4'h2; + LUT1_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_CPLD_1_axb_10 ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_CPLD[10]), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_CPLD_1_axb_10_4003) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_CPLD_1_axb_9.INIT = 4'h2; + LUT1_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_CPLD_1_axb_9 ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_CPLD[9]), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_CPLD_1_axb_9_4004) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_CPLD_1_axb_8.INIT = 4'h2; + LUT1_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_CPLD_1_axb_8 ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_CPLD[8]), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_CPLD_1_axb_8_4005) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_CPLD_1_axb_7.INIT = 4'h2; + LUT1_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_CPLD_1_axb_7 ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_CPLD[7]), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_CPLD_1_axb_7_4006) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_CPLD_1_axb_6.INIT = 4'h2; + LUT1_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_CPLD_1_axb_6 ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_CPLD[6]), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_CPLD_1_axb_6_4007) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_CPLD_1_axb_5.INIT = 8'h78; + LUT3_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_CPLD_1_axb_5 ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_consumed_cplh_3621), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_consumed_credits[5]), + .I2(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_CPLD[5]), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_CPLD_1_axb_5_4008) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_CPLD_1_axb_4.INIT = 8'h78; + LUT3_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_CPLD_1_axb_4 ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_consumed_cplh_3621), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_consumed_credits[4]), + .I2(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_CPLD[4]), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_CPLD_1_axb_4_4009) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_CPLD_1_axb_3.INIT = 8'h78; + LUT3_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_CPLD_1_axb_3 ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_consumed_cplh_3621), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_consumed_credits[3]), + .I2(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_CPLD[3]), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_CPLD_1_axb_3_4010) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_CPLD_1_axb_2.INIT = 8'h78; + LUT3_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_CPLD_1_axb_2 ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_consumed_cplh_3621), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_consumed_credits[2]), + .I2(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_CPLD[2]), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_CPLD_1_axb_2_4011) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_CPLD_1_axb_1.INIT = 8'h78; + LUT3_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_CPLD_1_axb_1 ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_consumed_cplh_3621), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_consumed_credits[1]), + .I2(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_CPLD[1]), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_CPLD_1_axb_1_4012) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_NPD_1_axb_11.INIT = 4'h2; + LUT1_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_NPD_1_axb_11 ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_NPD[11]), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_NPD_1_axb_11_4013) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_NPD_1_axb_10.INIT = 4'h2; + LUT1_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_NPD_1_axb_10 ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_NPD[10]), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_NPD_1_axb_10_4014) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_NPD_1_axb_9.INIT = 4'h2; + LUT1_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_NPD_1_axb_9 ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_NPD[9]), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_NPD_1_axb_9_4015) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_NPD_1_axb_8.INIT = 4'h2; + LUT1_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_NPD_1_axb_8 ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_NPD[8]), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_NPD_1_axb_8_4016) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_NPD_1_axb_7.INIT = 4'h2; + LUT1_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_NPD_1_axb_7 ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_NPD[7]), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_NPD_1_axb_7_4017) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_NPD_1_axb_6.INIT = 4'h2; + LUT1_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_NPD_1_axb_6 ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_NPD[6]), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_NPD_1_axb_6_4018) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_NPD_1_axb_5.INIT = 8'h78; + LUT3_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_NPD_1_axb_5 ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_consumed_credits[5]), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_consumed_nph_3619), + .I2(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_NPD[5]), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_NPD_1_axb_5_4019) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_NPD_1_axb_4.INIT = 8'h78; + LUT3_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_NPD_1_axb_4 ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_consumed_credits[4]), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_consumed_nph_3619), + .I2(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_NPD[4]), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_NPD_1_axb_4_4020) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_NPD_1_axb_3.INIT = 8'h78; + LUT3_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_NPD_1_axb_3 ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_consumed_credits[3]), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_consumed_nph_3619), + .I2(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_NPD[3]), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_NPD_1_axb_3_4021) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_NPD_1_axb_2.INIT = 8'h78; + LUT3_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_NPD_1_axb_2 ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_consumed_credits[2]), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_consumed_nph_3619), + .I2(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_NPD[2]), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_NPD_1_axb_2_4022) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_NPD_1_axb_1.INIT = 8'h78; + LUT3_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_NPD_1_axb_1 ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_consumed_credits[1]), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_consumed_nph_3619), + .I2(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_NPD[1]), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_NPD_1_axb_1_4023) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_PD_1_axb_11.INIT = 4'h2; + LUT1_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_PD_1_axb_11 ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_PD[11]), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_PD_1_axb_11_4024) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_PD_1_axb_10.INIT = 4'h2; + LUT1_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_PD_1_axb_10 ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_PD[10]), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_PD_1_axb_10_4025) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_PD_1_axb_9.INIT = 4'h2; + LUT1_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_PD_1_axb_9 ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_PD[9]), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_PD_1_axb_9_4026) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_PD_1_axb_8.INIT = 4'h2; + LUT1_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_PD_1_axb_8 ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_PD[8]), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_PD_1_axb_8_4027) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_PD_1_axb_7.INIT = 4'h2; + LUT1_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_PD_1_axb_7 ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_PD[7]), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_PD_1_axb_7_4028) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_PD_1_axb_6.INIT = 4'h2; + LUT1_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_PD_1_axb_6 ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_PD[6]), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_PD_1_axb_6_4029) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_PD_1_axb_5.INIT = 8'h78; + LUT3_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_PD_1_axb_5 ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_consumed_credits[5]), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_consumed_ph_3620), + .I2(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_PD[5]), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_PD_1_axb_5_4030) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_PD_1_axb_4.INIT = 8'h78; + LUT3_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_PD_1_axb_4 ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_consumed_credits[4]), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_consumed_ph_3620), + .I2(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_PD[4]), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_PD_1_axb_4_4031) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_PD_1_axb_3.INIT = 8'h78; + LUT3_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_PD_1_axb_3 ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_consumed_credits[3]), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_consumed_ph_3620), + .I2(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_PD[3]), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_PD_1_axb_3_4032) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_PD_1_axb_2.INIT = 8'h78; + LUT3_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_PD_1_axb_2 ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_consumed_credits[2]), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_consumed_ph_3620), + .I2(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_PD[2]), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_PD_1_axb_2_4033) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_PD_1_axb_1.INIT = 8'h78; + LUT3_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_PD_1_axb_1 ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_consumed_credits[1]), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_consumed_ph_3620), + .I2(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_PD[1]), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un1_consumed_PD_1_axb_1_4034) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_cpld_av_o_6_axb_10.INIT = 8'h7B; + LUT3_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_cpld_av_o_6_axb_10 ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_CPLD_i[10]), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_infinite_CPLD_i_4076), + .I2(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_limit_CPLD[10]), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_cpld_av_o_6_axb_10_4035) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_cpld_av_o_6_axb_9.INIT = 8'h7B; + LUT3_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_cpld_av_o_6_axb_9 ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_CPLD_i[9]), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_infinite_CPLD_i_4076), + .I2(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_limit_CPLD[9]), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_cpld_av_o_6_axb_9_4036) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_cpld_av_o_6_axb_8.INIT = 8'h7B; + LUT3_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_cpld_av_o_6_axb_8 ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_CPLD_i[8]), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_infinite_CPLD_i_4076), + .I2(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_limit_CPLD[8]), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_cpld_av_o_6_axb_8_4037) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_cpld_av_o_6_axb_7.INIT = 8'h7B; + LUT3_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_cpld_av_o_6_axb_7 ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_CPLD_i[7]), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_infinite_CPLD_i_4076), + .I2(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_limit_CPLD[7]), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_cpld_av_o_6_axb_7_4038) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_cpld_av_o_6_axb_6.INIT = 8'h7B; + LUT3_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_cpld_av_o_6_axb_6 ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_CPLD_i[6]), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_infinite_CPLD_i_4076), + .I2(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_limit_CPLD[6]), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_cpld_av_o_6_axb_6_4039) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_cpld_av_o_6_axb_5.INIT = 8'h7B; + LUT3_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_cpld_av_o_6_axb_5 ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_CPLD_i[5]), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_infinite_CPLD_i_4076), + .I2(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_limit_CPLD[5]), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_cpld_av_o_6_axb_5_4040) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_cpld_av_o_6_axb_4.INIT = 8'h7B; + LUT3_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_cpld_av_o_6_axb_4 ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_CPLD_i[4]), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_infinite_CPLD_i_4076), + .I2(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_limit_CPLD[4]), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_cpld_av_o_6_axb_4_4041) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_cpld_av_o_6_axb_3.INIT = 8'h7B; + LUT3_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_cpld_av_o_6_axb_3 ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_CPLD_i[3]), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_infinite_CPLD_i_4076), + .I2(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_limit_CPLD[3]), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_cpld_av_o_6_axb_3_4042) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_cpld_av_o_6_axb_2.INIT = 8'h7B; + LUT3_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_cpld_av_o_6_axb_2 ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_CPLD_i[2]), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_infinite_CPLD_i_4076), + .I2(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_limit_CPLD[2]), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_cpld_av_o_6_axb_2_4043) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_cpld_av_o_6_axb_1.INIT = 8'h7B; + LUT3_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_cpld_av_o_6_axb_1 ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_CPLD_i[1]), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_infinite_CPLD_i_4076), + .I2(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_limit_CPLD[1]), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_cpld_av_o_6_axb_1_4044) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_cpld_av_o_6_axb_0.INIT = 8'h7B; + LUT3_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_cpld_av_o_6_axb_0 ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_CPLD_i[0]), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_infinite_CPLD_i_4076), + .I2(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_limit_CPLD[0]), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_cpld_av_o_6_axb_0_4045) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_npd_av_o_6_axb_10.INIT = 8'h7B; + LUT3_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_npd_av_o_6_axb_10 ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_NPD_i[10]), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_infinite_NPD_i_4077), + .I2(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_limit_NPD[10]), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_npd_av_o_6_axb_10_4046) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_npd_av_o_6_axb_9.INIT = 8'h7B; + LUT3_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_npd_av_o_6_axb_9 ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_NPD_i[9]), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_infinite_NPD_i_4077), + .I2(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_limit_NPD[9]), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_npd_av_o_6_axb_9_4047) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_npd_av_o_6_axb_8.INIT = 8'h7B; + LUT3_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_npd_av_o_6_axb_8 ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_NPD_i[8]), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_infinite_NPD_i_4077), + .I2(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_limit_NPD[8]), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_npd_av_o_6_axb_8_4048) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_npd_av_o_6_axb_7.INIT = 8'h7B; + LUT3_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_npd_av_o_6_axb_7 ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_NPD_i[7]), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_infinite_NPD_i_4077), + .I2(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_limit_NPD[7]), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_npd_av_o_6_axb_7_4049) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_npd_av_o_6_axb_6.INIT = 8'h7B; + LUT3_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_npd_av_o_6_axb_6 ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_NPD_i[6]), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_infinite_NPD_i_4077), + .I2(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_limit_NPD[6]), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_npd_av_o_6_axb_6_4050) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_npd_av_o_6_axb_5.INIT = 8'h7B; + LUT3_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_npd_av_o_6_axb_5 ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_NPD_i[5]), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_infinite_NPD_i_4077), + .I2(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_limit_NPD[5]), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_npd_av_o_6_axb_5_4051) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_npd_av_o_6_axb_4.INIT = 8'h7B; + LUT3_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_npd_av_o_6_axb_4 ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_NPD_i[4]), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_infinite_NPD_i_4077), + .I2(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_limit_NPD[4]), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_npd_av_o_6_axb_4_4052) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_npd_av_o_6_axb_3.INIT = 8'h7B; + LUT3_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_npd_av_o_6_axb_3 ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_NPD_i[3]), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_infinite_NPD_i_4077), + .I2(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_limit_NPD[3]), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_npd_av_o_6_axb_3_4053) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_npd_av_o_6_axb_2.INIT = 8'h7B; + LUT3_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_npd_av_o_6_axb_2 ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_NPD_i[2]), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_infinite_NPD_i_4077), + .I2(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_limit_NPD[2]), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_npd_av_o_6_axb_2_4054) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_npd_av_o_6_axb_1.INIT = 8'h7B; + LUT3_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_npd_av_o_6_axb_1 ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_NPD_i[1]), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_infinite_NPD_i_4077), + .I2(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_limit_NPD[1]), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_npd_av_o_6_axb_1_4055) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_npd_av_o_6_axb_0.INIT = 8'h7B; + LUT3_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_npd_av_o_6_axb_0 ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_NPD_i[0]), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_infinite_NPD_i_4077), + .I2(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_limit_NPD[0]), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_npd_av_o_6_axb_0_4056) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_pd_av_o_6_axb_10.INIT = 8'h7B; + LUT3_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_pd_av_o_6_axb_10 ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_PD_i[10]), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_infinite_PD_i_4078), + .I2(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_limit_PD[10]), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_pd_av_o_6_axb_10_4057) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_pd_av_o_6_axb_9.INIT = 8'h7B; + LUT3_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_pd_av_o_6_axb_9 ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_PD_i[9]), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_infinite_PD_i_4078), + .I2(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_limit_PD[9]), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_pd_av_o_6_axb_9_4058) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_pd_av_o_6_axb_8.INIT = 8'h7B; + LUT3_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_pd_av_o_6_axb_8 ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_PD_i[8]), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_infinite_PD_i_4078), + .I2(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_limit_PD[8]), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_pd_av_o_6_axb_8_4059) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_pd_av_o_6_axb_7.INIT = 8'h7B; + LUT3_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_pd_av_o_6_axb_7 ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_PD_i[7]), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_infinite_PD_i_4078), + .I2(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_limit_PD[7]), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_pd_av_o_6_axb_7_4060) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_pd_av_o_6_axb_6.INIT = 8'h7B; + LUT3_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_pd_av_o_6_axb_6 ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_PD_i[6]), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_infinite_PD_i_4078), + .I2(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_limit_PD[6]), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_pd_av_o_6_axb_6_4061) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_pd_av_o_6_axb_5.INIT = 8'h7B; + LUT3_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_pd_av_o_6_axb_5 ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_PD_i[5]), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_infinite_PD_i_4078), + .I2(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_limit_PD[5]), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_pd_av_o_6_axb_5_4062) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_pd_av_o_6_axb_4.INIT = 8'h7B; + LUT3_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_pd_av_o_6_axb_4 ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_PD_i[4]), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_infinite_PD_i_4078), + .I2(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_limit_PD[4]), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_pd_av_o_6_axb_4_4063) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_pd_av_o_6_axb_3.INIT = 8'h7B; + LUT3_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_pd_av_o_6_axb_3 ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_PD_i[3]), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_infinite_PD_i_4078), + .I2(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_limit_PD[3]), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_pd_av_o_6_axb_3_4064) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_pd_av_o_6_axb_2.INIT = 8'h7B; + LUT3_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_pd_av_o_6_axb_2 ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_PD_i[2]), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_infinite_PD_i_4078), + .I2(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_limit_PD[2]), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_pd_av_o_6_axb_2_4065) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_pd_av_o_6_axb_1.INIT = 8'h7B; + LUT3_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_pd_av_o_6_axb_1 ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_PD_i[1]), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_infinite_PD_i_4078), + .I2(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_limit_PD[1]), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_pd_av_o_6_axb_1_4066) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_pd_av_o_6_axb_0.INIT = 8'h7B; + LUT3_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_pd_av_o_6_axb_0 ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_PD_i[0]), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_infinite_PD_i_4078), + .I2(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_limit_PD[0]), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_pd_av_o_6_axb_0_4067) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_min_data_cred_7_i_0_0_5_.INIT = 4'h1; + LUT2_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_min_data_cred_7_i_0_0_5_ ( + .I0(com_N_56034_i), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_suspend_cat[0]), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_N_32423_i) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_min_data_cred_7_0_a2_0_a2_0_a2_4_.INIT = 4'h2; + LUT2_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_min_data_cred_7_0_a2_0_a2_0_a2_4_ ( + .I0(com_N_56202_i), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_suspend_cat[0]), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_min_data_cred_7[4]) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_min_data_cred_7_0_a2_0_a2_0_a2_3_.INIT = 4'h2; + LUT2_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_min_data_cred_7_0_a2_0_a2_0_a2_3_ ( + .I0(com_N_56233_i), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_suspend_cat[0]), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_min_data_cred_7[3]) + ); + FD com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_infinite_header_qq ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_infinite_header_q_4070), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_infinite_header_qq_4068) + ); + FD com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_infinite_data_qq ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_infinite_data_q_4071), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_infinite_data_qq_4069) + ); + FD com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_infinite_header_q ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_infinite_header_q_2), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_infinite_header_q_4070) + ); + FD com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_infinite_data_q ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_infinite_data_q_2), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_infinite_data_q_4071) + ); + FD com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_fc_diff_data_q_11_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_fc_diff_data[11]), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_fc_diff_data_q[11]) + ); + FD com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_fc_diff_header_q_7_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_fc_diff_header[7]), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_fc_diff_header_q[7]) + ); + FD com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_infinite_header_qq ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_infinite_header_q_4074), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_infinite_header_qq_4072) + ); + FD com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_infinite_data_qq ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_infinite_data_q_4075), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_infinite_data_qq_4073) + ); + FD com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_infinite_header_q ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_infinite_header_q_5), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_infinite_header_q_4074) + ); + FD com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_infinite_data_q ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_infinite_data_q_5), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_infinite_data_q_4075) + ); + FD com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_prev_limit_data_q_1_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_prev_limit_data_q_5[1]), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_prev_limit_data_q[1]) + ); + FD com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_prev_limit_data_q_0_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_prev_limit_data_q_5[0]), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_prev_limit_data_q[0]) + ); + FD com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_prev_limit_header_q_4_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_prev_limit_header_q_5[4]), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_prev_limit_header_q[4]) + ); + FD com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_prev_limit_header_q_3_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_prev_limit_header_q_5[3]), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_prev_limit_header_q[3]) + ); + FD com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_prev_limit_header_q_2_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_prev_limit_header_q_5[2]), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_prev_limit_header_q[2]) + ); + FD com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_prev_limit_header_q_1_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_prev_limit_header_q_5[1]), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_prev_limit_header_q[1]) + ); + FD com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_prev_limit_header_q_0_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_prev_limit_header_q_5[0]), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_prev_limit_header_q[0]) + ); + FD com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_prev_limit_data_q_11_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_prev_limit_data_q_5[11]), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_prev_limit_data_q[11]) + ); + FD com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_prev_limit_data_q_10_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_prev_limit_data_q_5[10]), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_prev_limit_data_q[10]) + ); + FD com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_prev_limit_data_q_9_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_prev_limit_data_q_5[9]), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_prev_limit_data_q[9]) + ); + FD com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_prev_limit_data_q_8_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_prev_limit_data_q_5[8]), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_prev_limit_data_q[8]) + ); + FD com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_prev_limit_data_q_7_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_prev_limit_data_q_5[7]), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_prev_limit_data_q[7]) + ); + FD com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_prev_limit_data_q_6_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_prev_limit_data_q_5[6]), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_prev_limit_data_q[6]) + ); + FD com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_prev_limit_data_q_5_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_prev_limit_data_q_5[5]), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_prev_limit_data_q[5]) + ); + FD com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_prev_limit_data_q_4_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_prev_limit_data_q_5[4]), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_prev_limit_data_q[4]) + ); + FD com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_prev_limit_data_q_3_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_prev_limit_data_q_5[3]), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_prev_limit_data_q[3]) + ); + FD com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_prev_limit_data_q_2_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_prev_limit_data_q_5[2]), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_prev_limit_data_q[2]) + ); + FD com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_data_q_9_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_lnk_rfc_data[9]), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_data_q[9]) + ); + FD com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_data_q_8_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_lnk_rfc_data[8]), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_data_q[8]) + ); + FD com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_data_q_7_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_lnk_rfc_data[7]), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_data_q[7]) + ); + FD com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_data_q_6_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_lnk_rfc_data[6]), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_data_q[6]) + ); + FD com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_data_q_5_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_lnk_rfc_data[5]), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_data_q[5]) + ); + FD com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_data_q_4_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_lnk_rfc_data[4]), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_data_q[4]) + ); + FD com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_data_q_3_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_lnk_rfc_data[3]), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_data_q[3]) + ); + FD com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_data_q_2_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_lnk_rfc_data[2]), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_data_q[2]) + ); + FD com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_data_q_1_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_lnk_rfc_data[1]), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_data_q[1]) + ); + FD com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_data_q_0_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_lnk_rfc_data[0]), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_data_q[0]) + ); + FD com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_cat_q_1_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_lnk_rfc_type[1]), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_cat_q[1]) + ); + FD com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_cat_q_0_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_lnk_rfc_type[0]), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_cat_q[0]) + ); + FD com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_prev_limit_header_q_7_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_prev_limit_header_q_5[7]), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_prev_limit_header_q[7]) + ); + FD com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_prev_limit_header_q_6_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_prev_limit_header_q_5[6]), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_prev_limit_header_q[6]) + ); + FD com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_prev_limit_header_q_5_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_prev_limit_header_q_5[5]), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_prev_limit_header_q[5]) + ); + FD com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_data_qq_4_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_data_q[4]), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_data_qq[4]) + ); + FD com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_data_qq_3_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_data_q[3]), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_data_qq[3]) + ); + FD com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_data_qq_2_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_data_q[2]), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_data_qq[2]) + ); + FD com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_data_qq_1_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_data_q[1]), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_data_qq[1]) + ); + FD com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_data_qq_0_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_data_q[0]), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_data_qq[0]) + ); + FD com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_header_q_7_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_lnk_rfc_header[7]), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_header_q[7]) + ); + FD com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_header_q_6_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_lnk_rfc_header[6]), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_header_q[6]) + ); + FD com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_header_q_5_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_lnk_rfc_header[5]), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_header_q[5]) + ); + FD com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_header_q_4_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_lnk_rfc_header[4]), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_header_q[4]) + ); + FD com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_header_q_3_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_lnk_rfc_header[3]), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_header_q[3]) + ); + FD com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_header_q_2_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_lnk_rfc_header[2]), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_header_q[2]) + ); + FD com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_header_q_1_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_lnk_rfc_header[1]), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_header_q[1]) + ); + FD com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_header_q_0_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_lnk_rfc_header[0]), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_header_q[0]) + ); + FD com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_data_q_11_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_lnk_rfc_data[11]), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_data_q[11]) + ); + FD com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_data_q_10_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_lnk_rfc_data[10]), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_data_q[10]) + ); + FD com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_header_qq_7_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_header_q[7]), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_header_qq[7]) + ); + FD com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_header_qq_6_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_header_q[6]), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_header_qq[6]) + ); + FD com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_header_qq_5_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_header_q[5]), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_header_qq[5]) + ); + FD com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_header_qq_4_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_header_q[4]), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_header_qq[4]) + ); + FD com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_header_qq_3_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_header_q[3]), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_header_qq[3]) + ); + FD com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_header_qq_2_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_header_q[2]), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_header_qq[2]) + ); + FD com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_header_qq_1_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_header_q[1]), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_header_qq[1]) + ); + FD com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_header_qq_0_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_header_q[0]), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_header_qq[0]) + ); + FD com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_data_qq_11_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_data_q[11]), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_data_qq[11]) + ); + FD com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_data_qq_10_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_data_q[10]), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_data_qq[10]) + ); + FD com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_data_qq_9_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_data_q[9]), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_data_qq[9]) + ); + FD com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_data_qq_8_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_data_q[8]), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_data_qq[8]) + ); + FD com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_data_qq_7_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_data_q[7]), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_data_qq[7]) + ); + FD com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_data_qq_6_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_data_q[6]), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_data_qq[6]) + ); + FD com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_data_qq_5_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_data_q[5]), + .Q(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_data_qq[5]) + ); + INV com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_infinite_CPLD_i ( + .I(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_infinite_CPLD_4080), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_infinite_CPLD_i_4076) + ); + INV com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_CPLD_i_0_ ( + .I(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_CPLD[0]), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_CPLD_i[0]) + ); + INV com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_CPLD_i_1_ ( + .I(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_CPLD[1]), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_CPLD_i[1]) + ); + INV com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_CPLD_i_2_ ( + .I(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_CPLD[2]), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_CPLD_i[2]) + ); + INV com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_CPLD_i_3_ ( + .I(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_CPLD[3]), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_CPLD_i[3]) + ); + INV com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_CPLD_i_4_ ( + .I(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_CPLD[4]), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_CPLD_i[4]) + ); + INV com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_CPLD_i_5_ ( + .I(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_CPLD[5]), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_CPLD_i[5]) + ); + INV com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_CPLD_i_6_ ( + .I(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_CPLD[6]), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_CPLD_i[6]) + ); + INV com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_CPLD_i_7_ ( + .I(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_CPLD[7]), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_CPLD_i[7]) + ); + INV com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_CPLD_i_8_ ( + .I(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_CPLD[8]), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_CPLD_i[8]) + ); + INV com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_CPLD_i_9_ ( + .I(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_CPLD[9]), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_CPLD_i[9]) + ); + INV com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_CPLD_i_10_ ( + .I(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_CPLD[10]), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_CPLD_i[10]) + ); + INV com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_infinite_NPD_i ( + .I(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_infinite_NPD_4082), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_infinite_NPD_i_4077) + ); + INV com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_NPD_i_0_ ( + .I(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_NPD[0]), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_NPD_i[0]) + ); + INV com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_NPD_i_1_ ( + .I(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_NPD[1]), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_NPD_i[1]) + ); + INV com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_NPD_i_2_ ( + .I(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_NPD[2]), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_NPD_i[2]) + ); + INV com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_NPD_i_3_ ( + .I(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_NPD[3]), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_NPD_i[3]) + ); + INV com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_NPD_i_4_ ( + .I(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_NPD[4]), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_NPD_i[4]) + ); + INV com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_NPD_i_5_ ( + .I(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_NPD[5]), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_NPD_i[5]) + ); + INV com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_NPD_i_6_ ( + .I(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_NPD[6]), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_NPD_i[6]) + ); + INV com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_NPD_i_7_ ( + .I(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_NPD[7]), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_NPD_i[7]) + ); + INV com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_NPD_i_8_ ( + .I(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_NPD[8]), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_NPD_i[8]) + ); + INV com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_NPD_i_9_ ( + .I(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_NPD[9]), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_NPD_i[9]) + ); + INV com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_NPD_i_10_ ( + .I(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_NPD[10]), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_NPD_i[10]) + ); + INV com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_infinite_PD_i ( + .I(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_infinite_PD_4084), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_infinite_PD_i_4078) + ); + INV com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_PD_i_0_ ( + .I(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_PD[0]), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_PD_i[0]) + ); + INV com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_PD_i_1_ ( + .I(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_PD[1]), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_PD_i[1]) + ); + INV com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_PD_i_2_ ( + .I(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_PD[2]), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_PD_i[2]) + ); + INV com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_PD_i_3_ ( + .I(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_PD[3]), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_PD_i[3]) + ); + INV com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_PD_i_4_ ( + .I(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_PD[4]), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_PD_i[4]) + ); + INV com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_PD_i_5_ ( + .I(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_PD[5]), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_PD_i[5]) + ); + INV com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_PD_i_6_ ( + .I(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_PD[6]), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_PD_i[6]) + ); + INV com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_PD_i_7_ ( + .I(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_PD[7]), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_PD_i[7]) + ); + INV com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_PD_i_8_ ( + .I(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_PD[8]), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_PD_i[8]) + ); + INV com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_PD_i_9_ ( + .I(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_PD[9]), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_PD_i[9]) + ); + INV com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_PD_i_10_ ( + .I(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_PD[10]), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_PD_i[10]) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_PH_qxu_0_0_.INIT = 4'h2; + LUT1_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_PH_qxu_0_0_ ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_PH[0]), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_PH_qxu[0]) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_NPH_qxu_0_0_.INIT = 4'h2; + LUT1_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_NPH_qxu_0_0_ ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_NPH[0]), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_NPH_qxu[0]) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_CPLH_qxu_0_0_.INIT = 4'h2; + LUT1_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_CPLH_qxu_0_0_ ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_CPLH[0]), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_CPLH_qxu[0]) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_CPLH_qxu_0_7_.INIT = 4'h2; + LUT1_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_CPLH_qxu_0_7_ ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_CPLH[7]), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_CPLH_qxu[7]) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_CPLH_qxu_0_6_.INIT = 4'h2; + LUT1_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_CPLH_qxu_0_6_ ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_CPLH[6]), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_CPLH_qxu[6]) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_CPLH_qxu_0_5_.INIT = 4'h2; + LUT1_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_CPLH_qxu_0_5_ ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_CPLH[5]), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_CPLH_qxu[5]) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_CPLH_qxu_0_4_.INIT = 4'h2; + LUT1_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_CPLH_qxu_0_4_ ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_CPLH[4]), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_CPLH_qxu[4]) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_CPLH_qxu_0_3_.INIT = 4'h2; + LUT1_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_CPLH_qxu_0_3_ ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_CPLH[3]), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_CPLH_qxu[3]) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_CPLH_qxu_0_2_.INIT = 4'h2; + LUT1_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_CPLH_qxu_0_2_ ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_CPLH[2]), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_CPLH_qxu[2]) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_CPLH_qxu_0_1_.INIT = 4'h2; + LUT1_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_CPLH_qxu_0_1_ ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_CPLH[1]), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_CPLH_qxu[1]) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_CPLH_s_0_.INIT = 4'h1; + LUT1_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_CPLH_s_0_ ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_CPLH_qxu[0]), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_CPLH_s[0]) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_NPH_qxu_0_7_.INIT = 4'h2; + LUT1_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_NPH_qxu_0_7_ ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_NPH[7]), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_NPH_qxu[7]) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_NPH_qxu_0_6_.INIT = 4'h2; + LUT1_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_NPH_qxu_0_6_ ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_NPH[6]), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_NPH_qxu[6]) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_NPH_qxu_0_5_.INIT = 4'h2; + LUT1_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_NPH_qxu_0_5_ ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_NPH[5]), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_NPH_qxu[5]) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_NPH_qxu_0_4_.INIT = 4'h2; + LUT1_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_NPH_qxu_0_4_ ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_NPH[4]), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_NPH_qxu[4]) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_NPH_qxu_0_3_.INIT = 4'h2; + LUT1_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_NPH_qxu_0_3_ ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_NPH[3]), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_NPH_qxu[3]) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_NPH_qxu_0_2_.INIT = 4'h2; + LUT1_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_NPH_qxu_0_2_ ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_NPH[2]), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_NPH_qxu[2]) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_NPH_qxu_0_1_.INIT = 4'h2; + LUT1_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_NPH_qxu_0_1_ ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_NPH[1]), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_NPH_qxu[1]) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_NPH_s_0_.INIT = 4'h1; + LUT1_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_NPH_s_0_ ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_NPH_qxu[0]), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_NPH_s[0]) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_PH_qxu_0_7_.INIT = 4'h2; + LUT1_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_PH_qxu_0_7_ ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_PH[7]), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_PH_qxu[7]) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_PH_qxu_0_6_.INIT = 4'h2; + LUT1_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_PH_qxu_0_6_ ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_PH[6]), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_PH_qxu[6]) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_PH_qxu_0_5_.INIT = 4'h2; + LUT1_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_PH_qxu_0_5_ ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_PH[5]), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_PH_qxu[5]) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_PH_qxu_0_4_.INIT = 4'h2; + LUT1_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_PH_qxu_0_4_ ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_PH[4]), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_PH_qxu[4]) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_PH_qxu_0_3_.INIT = 4'h2; + LUT1_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_PH_qxu_0_3_ ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_PH[3]), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_PH_qxu[3]) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_PH_qxu_0_2_.INIT = 4'h2; + LUT1_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_PH_qxu_0_2_ ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_PH[2]), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_PH_qxu[2]) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_PH_qxu_0_1_.INIT = 4'h2; + LUT1_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_PH_qxu_0_1_ ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_PH[1]), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_PH_qxu[1]) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_PH_s_0_.INIT = 4'h1; + LUT1_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_PH_s_0_ ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_PH_qxu[0]), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_PH_s[0]) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_cpld_av_o_6_axb_11.INIT = 8'h09; + LUT3_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_cpld_av_o_6_axb_11 ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_limit_CPLD[11]), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_CPLD[11]), + .I2(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_infinite_CPLD_4080), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_cpld_av_o_6_axb_11_4079) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_npd_av_o_6_axb_11.INIT = 8'h09; + LUT3_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_npd_av_o_6_axb_11 ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_limit_NPD[11]), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_NPD[11]), + .I2(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_infinite_NPD_4082), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_npd_av_o_6_axb_11_4081) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_pd_av_o_6_axb_11.INIT = 8'h09; + LUT3_L com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_pd_av_o_6_axb_11 ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_limit_PD[11]), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_consumed_PD[11]), + .I2(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_infinite_PD_4084), + .LO(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_pd_av_o_6_axb_11_4083) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_fc_diff_data_axb_10.INIT = 4'h9; + LUT2 com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_fc_diff_data_axb_10 ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_prev_limit_data_q[10]), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_data_q[10]), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_fc_diff_data_axb_10_4085) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_fc_diff_data_axb_9.INIT = 4'h9; + LUT2 com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_fc_diff_data_axb_9 ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_prev_limit_data_q[9]), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_data_q[9]), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_fc_diff_data_axb_9_4086) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_fc_diff_data_axb_8.INIT = 4'h9; + LUT2 com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_fc_diff_data_axb_8 ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_prev_limit_data_q[8]), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_data_q[8]), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_fc_diff_data_axb_8_4087) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_fc_diff_data_axb_7.INIT = 4'h9; + LUT2 com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_fc_diff_data_axb_7 ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_prev_limit_data_q[7]), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_data_q[7]), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_fc_diff_data_axb_7_4088) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_fc_diff_data_axb_6.INIT = 4'h9; + LUT2 com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_fc_diff_data_axb_6 ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_prev_limit_data_q[6]), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_data_q[6]), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_fc_diff_data_axb_6_4089) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_fc_diff_data_axb_5.INIT = 4'h9; + LUT2 com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_fc_diff_data_axb_5 ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_prev_limit_data_q[5]), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_data_q[5]), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_fc_diff_data_axb_5_4090) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_fc_diff_data_axb_4.INIT = 4'h9; + LUT2 com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_fc_diff_data_axb_4 ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_prev_limit_data_q[4]), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_data_q[4]), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_fc_diff_data_axb_4_4091) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_fc_diff_data_axb_3.INIT = 4'h9; + LUT2 com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_fc_diff_data_axb_3 ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_prev_limit_data_q[3]), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_data_q[3]), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_fc_diff_data_axb_3_4092) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_fc_diff_data_axb_2.INIT = 4'h9; + LUT2 com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_fc_diff_data_axb_2 ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_prev_limit_data_q[2]), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_data_q[2]), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_fc_diff_data_axb_2_4093) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_fc_diff_data_axb_1.INIT = 4'h9; + LUT2 com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_fc_diff_data_axb_1 ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_prev_limit_data_q[1]), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_data_q[1]), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_fc_diff_data_axb_1_4094) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_fc_diff_data_axb_0.INIT = 4'h9; + LUT2 com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_fc_diff_data_axb_0 ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_prev_limit_data_q[0]), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_data_q[0]), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_fc_diff_data_axb_0_4095) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_pd_av_i_10_.INIT = 4'h1; + LUT1 com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_pd_av_i_10_ ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_pd_av[10]), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_pd_av_i[10]) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_pd_av_i_9_.INIT = 4'h1; + LUT1 com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_pd_av_i_9_ ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_pd_av[9]), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_pd_av_i[9]) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_pd_av_i_8_.INIT = 4'h1; + LUT1 com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_pd_av_i_8_ ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_pd_av[8]), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_pd_av_i[8]) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_pd_av_i_7_.INIT = 4'h1; + LUT1 com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_pd_av_i_7_ ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_pd_av[7]), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_pd_av_i[7]) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_pd_av_i_6_.INIT = 4'h1; + LUT1 com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_pd_av_i_6_ ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_pd_av[6]), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_pd_av_i[6]) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_fc_diff_header_axb_6.INIT = 4'h9; + LUT2 com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_fc_diff_header_axb_6 ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_prev_limit_header_q[6]), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_header_q[6]), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_fc_diff_header_axb_6_4096) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_fc_diff_header_axb_5.INIT = 4'h9; + LUT2 com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_fc_diff_header_axb_5 ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_prev_limit_header_q[5]), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_header_q[5]), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_fc_diff_header_axb_5_4097) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_fc_diff_header_axb_4.INIT = 4'h9; + LUT2 com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_fc_diff_header_axb_4 ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_prev_limit_header_q[4]), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_header_q[4]), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_fc_diff_header_axb_4_4098) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_fc_diff_header_axb_3.INIT = 4'h9; + LUT2 com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_fc_diff_header_axb_3 ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_prev_limit_header_q[3]), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_header_q[3]), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_fc_diff_header_axb_3_4099) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_fc_diff_header_axb_2.INIT = 4'h9; + LUT2 com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_fc_diff_header_axb_2 ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_prev_limit_header_q[2]), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_header_q[2]), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_fc_diff_header_axb_2_4100) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_fc_diff_header_axb_1.INIT = 4'h9; + LUT2 com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_fc_diff_header_axb_1 ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_prev_limit_header_q[1]), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_header_q[1]), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_fc_diff_header_axb_1_4101) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_fc_diff_header_axb_0.INIT = 4'h9; + LUT2 com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_fc_diff_header_axb_0 ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_prev_limit_header_q[0]), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_rx_fc_header_q[0]), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_fc_diff_header_axb_0_4102) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_cpld_av_i_10_.INIT = 4'h1; + LUT1 com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_cpld_av_i_10_ ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_cpld_av[10]), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_cpld_av_i[10]) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_cpld_av_i_9_.INIT = 4'h1; + LUT1 com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_cpld_av_i_9_ ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_cpld_av[9]), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_cpld_av_i[9]) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_cpld_av_i_8_.INIT = 4'h1; + LUT1 com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_cpld_av_i_8_ ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_cpld_av[8]), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_cpld_av_i[8]) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_cpld_av_i_7_.INIT = 4'h1; + LUT1 com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_cpld_av_i_7_ ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_cpld_av[7]), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_cpld_av_i[7]) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_cpld_av_i_6_.INIT = 4'h1; + LUT1 com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_cpld_av_i_6_ ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_cpld_av[6]), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_cpld_av_i[6]) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_npd_av_i_10_.INIT = 4'h1; + LUT1 com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_npd_av_i_10_ ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_npd_av[10]), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_npd_av_i[10]) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_npd_av_i_9_.INIT = 4'h1; + LUT1 com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_npd_av_i_9_ ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_npd_av[9]), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_npd_av_i[9]) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_npd_av_i_8_.INIT = 4'h1; + LUT1 com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_npd_av_i_8_ ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_npd_av[8]), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_npd_av_i[8]) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_npd_av_i_7_.INIT = 4'h1; + LUT1 com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_npd_av_i_7_ ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_npd_av[7]), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_npd_av_i[7]) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_npd_av_i_6_.INIT = 4'h1; + LUT1 com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_npd_av_i_6_ ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_npd_av[6]), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_npd_av_i[6]) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_av_data_cred_i_11_.INIT = 4'h1; + LUT1 com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_av_data_cred_i_11_ ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_av_data_cred[11]), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_av_data_cred_i_11__4103) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_av_data_cred_i_10_.INIT = 4'h1; + LUT1 com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_av_data_cred_i_10_ ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_av_data_cred[10]), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_av_data_cred_i_10__4104) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_av_data_cred_i_9_.INIT = 4'h1; + LUT1 com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_av_data_cred_i_9_ ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_av_data_cred[9]), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_av_data_cred_i_9__4105) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_av_data_cred_i_8_.INIT = 4'h1; + LUT1 com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_av_data_cred_i_8_ ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_av_data_cred[8]), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_av_data_cred_i_8__4106) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_av_data_cred_i_7_.INIT = 4'h1; + LUT1 com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_av_data_cred_i_7_ ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_av_data_cred[7]), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_av_data_cred_i_7__4107) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_av_data_cred_i_6_.INIT = 4'h1; + LUT1 com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_av_data_cred_i_6_ ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_av_data_cred[6]), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_av_data_cred_i_6__4108) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un7_credits_ok_axb_5_i.INIT = 4'h9; + LUT2 com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un7_credits_ok_axb_5_i ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_av_data_cred[5]), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_min_data_cred[5]), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un7_credits_ok_axb_5_i_4109) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un7_credits_ok_axb_4_i.INIT = 4'h9; + LUT2 com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un7_credits_ok_axb_4_i ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_av_data_cred[4]), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_min_data_cred[4]), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un7_credits_ok_axb_4_i_4110) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un7_credits_ok_axb_3_i.INIT = 4'h9; + LUT2 com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un7_credits_ok_axb_3_i ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_av_data_cred[3]), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_min_data_cred[3]), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un7_credits_ok_axb_3_i_4111) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_av_data_cred_i_2_.INIT = 4'h1; + LUT1 com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_av_data_cred_i_2_ ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_av_data_cred[2]), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_av_data_cred_i_2__4112) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_av_data_cred_i_1_.INIT = 4'h1; + LUT1 com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_av_data_cred_i_1_ ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_av_data_cred[1]), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_av_data_cred_i_1__4113) + ); + defparam com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un7_credits_ok_axb_0_i.INIT = 4'h9; + LUT2 com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un7_credits_ok_axb_0_i ( + .I0(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_av_data_cred[0]), + .I1(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_suspend_cat[1]), + .O(com_tlm_u_tlm_tx_vc0_frm_seq_credit_store_un7_credits_ok_axb_0_i_4114) + ); + GND com_tlm_u_tlm_tx_pm_ctrl_GND ( + .G(com_tlm_u_tlm_tx_pm_ctrl_GND_4115) + ); + FDR com_tlm_u_tlm_tx_pm_ctrl_cfg_ct_0_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_pm_ctrl_un1_cfg_ct_axb_0_4124), + .Q(com_tlm_u_tlm_tx_pm_ctrl_cfg_ct[0]), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_tx_pm_ctrl_cfg_ct_1_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_pm_ctrl_un1_cfg_ct_s_1_4116), + .Q(com_tlm_u_tlm_tx_pm_ctrl_cfg_ct[1]), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_tx_pm_ctrl_cfg_ct_2_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_pm_ctrl_un1_cfg_ct_s_2_4118), + .Q(com_tlm_u_tlm_tx_pm_ctrl_cfg_ct[2]), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_tx_pm_ctrl_cfg_ct_3_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_pm_ctrl_un1_cfg_ct_s_3_4120), + .Q(com_tlm_u_tlm_tx_pm_ctrl_cfg_ct[3]), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_tx_pm_ctrl_cfg_ct_4_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_pm_ctrl_un1_cfg_ct_s_4_4122), + .Q(com_tlm_u_tlm_tx_pm_ctrl_cfg_ct[4]), + .R(plm_link_up_i) + ); + FDRSE com_tlm_u_tlm_tx_pm_ctrl_cfg_pending ( + .CE(com_tlm_u_tlm_tx_pm_ctrl_cfg_ct23), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_pm_ctrl_N_21863_i_4126), + .Q(com_tlm_u_tlm_tx_pm_ctrl_cfg_pending_4125), + .R(plm_link_up_i), + .S(com_tlm_u_tlm_tx_cfg_accepted) + ); + FDR com_tlm_u_tlm_tx_pm_ctrl_aspm_suspend_req_o ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_pm_ctrl_N_58770), + .Q(com_cmmt_aspm_suspend_req), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_tx_pm_ctrl_ppm_suspend_ok_o ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_tx_pm_ctrl_ppm_suspend_ok_o_3), + .Q(com_cmmt_ppm_suspend_ok), + .R(plm_link_up_i) + ); + MUXCY_L com_tlm_u_tlm_tx_pm_ctrl_un1_cfg_ct_cry_0 ( + .CI(com_tlm_u_tlm_tx_pm_ctrl_GND_4115), + .DI(com_tlm_u_tlm_tx_pm_ctrl_cfg_ct[0]), + .LO(com_tlm_u_tlm_tx_pm_ctrl_un1_cfg_ct_cry_0_4117), + .S(com_tlm_u_tlm_tx_pm_ctrl_un1_cfg_ct_axb_0_4124) + ); + MUXCY_L com_tlm_u_tlm_tx_pm_ctrl_un1_cfg_ct_cry_1 ( + .CI(com_tlm_u_tlm_tx_pm_ctrl_un1_cfg_ct_cry_0_4117), + .DI(com_tlm_u_tlm_tx_pm_ctrl_cfg_ct[1]), + .LO(com_tlm_u_tlm_tx_pm_ctrl_un1_cfg_ct_cry_1_4119), + .S(com_tlm_u_tlm_tx_pm_ctrl_un1_cfg_ct_axb_1_4130) + ); + XORCY com_tlm_u_tlm_tx_pm_ctrl_un1_cfg_ct_s_1 ( + .CI(com_tlm_u_tlm_tx_pm_ctrl_un1_cfg_ct_cry_0_4117), + .LI(com_tlm_u_tlm_tx_pm_ctrl_un1_cfg_ct_axb_1_4130), + .O(com_tlm_u_tlm_tx_pm_ctrl_un1_cfg_ct_s_1_4116) + ); + MUXCY_L com_tlm_u_tlm_tx_pm_ctrl_un1_cfg_ct_cry_2 ( + .CI(com_tlm_u_tlm_tx_pm_ctrl_un1_cfg_ct_cry_1_4119), + .DI(com_tlm_u_tlm_tx_pm_ctrl_cfg_ct[2]), + .LO(com_tlm_u_tlm_tx_pm_ctrl_un1_cfg_ct_cry_2_4121), + .S(com_tlm_u_tlm_tx_pm_ctrl_un1_cfg_ct_axb_2_4129) + ); + XORCY com_tlm_u_tlm_tx_pm_ctrl_un1_cfg_ct_s_2 ( + .CI(com_tlm_u_tlm_tx_pm_ctrl_un1_cfg_ct_cry_1_4119), + .LI(com_tlm_u_tlm_tx_pm_ctrl_un1_cfg_ct_axb_2_4129), + .O(com_tlm_u_tlm_tx_pm_ctrl_un1_cfg_ct_s_2_4118) + ); + MUXCY_L com_tlm_u_tlm_tx_pm_ctrl_un1_cfg_ct_cry_3 ( + .CI(com_tlm_u_tlm_tx_pm_ctrl_un1_cfg_ct_cry_2_4121), + .DI(com_tlm_u_tlm_tx_pm_ctrl_cfg_ct[3]), + .LO(com_tlm_u_tlm_tx_pm_ctrl_un1_cfg_ct_cry_3_4123), + .S(com_tlm_u_tlm_tx_pm_ctrl_un1_cfg_ct_axb_3_4128) + ); + XORCY com_tlm_u_tlm_tx_pm_ctrl_un1_cfg_ct_s_3 ( + .CI(com_tlm_u_tlm_tx_pm_ctrl_un1_cfg_ct_cry_2_4121), + .LI(com_tlm_u_tlm_tx_pm_ctrl_un1_cfg_ct_axb_3_4128), + .O(com_tlm_u_tlm_tx_pm_ctrl_un1_cfg_ct_s_3_4120) + ); + XORCY com_tlm_u_tlm_tx_pm_ctrl_un1_cfg_ct_s_4 ( + .CI(com_tlm_u_tlm_tx_pm_ctrl_un1_cfg_ct_cry_3_4123), + .LI(com_tlm_u_tlm_tx_pm_ctrl_un1_cfg_ct_axb_4_4127), + .O(com_tlm_u_tlm_tx_pm_ctrl_un1_cfg_ct_s_4_4122) + ); + defparam com_tlm_u_tlm_tx_pm_ctrl_cfg_ct23_0_a2.INIT = 4'h4; + LUT2 com_tlm_u_tlm_tx_pm_ctrl_cfg_ct23_0_a2 ( + .I0(com_tlm_u_tlm_tx_cfg_accepted), + .I1(com_tlm_u_tlm_tx_cfg_sent), + .O(com_tlm_u_tlm_tx_pm_ctrl_cfg_ct23) + ); + defparam com_tlm_u_tlm_tx_pm_ctrl_un1_cfg_ct_axb_0.INIT = 8'h96; + LUT3 com_tlm_u_tlm_tx_pm_ctrl_un1_cfg_ct_axb_0 ( + .I0(com_tlm_u_tlm_tx_cfg_accepted), + .I1(com_tlm_u_tlm_tx_cfg_sent), + .I2(com_tlm_u_tlm_tx_pm_ctrl_cfg_ct[0]), + .O(com_tlm_u_tlm_tx_pm_ctrl_un1_cfg_ct_axb_0_4124) + ); + defparam com_tlm_u_tlm_tx_pm_ctrl_ppm_suspend_ok_o_3_0_a2_0_a2_0_a2_0_a2.INIT = 16'h0100; + LUT4_L com_tlm_u_tlm_tx_pm_ctrl_ppm_suspend_ok_o_3_0_a2_0_a2_0_a2_0_a2 ( + .I0(com_cmmt_ppm_suspend_req_n), + .I1(com_tlm_u_tlm_tx_ack_pending), + .I2(com_tlm_u_tlm_tx_pm_ctrl_cfg_pending_4125), + .I3(com_tlm_u_tlm_tx_suspend_credit_rdy), + .LO(com_tlm_u_tlm_tx_pm_ctrl_ppm_suspend_ok_o_3) + ); + defparam com_tlm_u_tlm_tx_pm_ctrl_aspm_suspend_req_o_3_i_0_0_0_a2.INIT = 16'h0200; + LUT4_L com_tlm_u_tlm_tx_pm_ctrl_aspm_suspend_req_o_3_i_0_0_0_a2 ( + .I0(com_tlm_aspm_ok), + .I1(com_tlm_u_tlm_tx_ack_pending), + .I2(com_tlm_u_tlm_tx_pkt_incoming), + .I3(com_tlm_u_tlm_tx_queue_state[0]), + .LO(com_tlm_u_tlm_tx_pm_ctrl_N_58770) + ); + defparam com_tlm_u_tlm_tx_pm_ctrl_N_21863_i.INIT = 16'hFFFE; + LUT4_L com_tlm_u_tlm_tx_pm_ctrl_N_21863_i ( + .I0(com_tlm_u_tlm_tx_pm_ctrl_cfg_ct[1]), + .I1(com_tlm_u_tlm_tx_pm_ctrl_cfg_ct[2]), + .I2(com_tlm_u_tlm_tx_pm_ctrl_cfg_ct[3]), + .I3(com_tlm_u_tlm_tx_pm_ctrl_cfg_ct[4]), + .LO(com_tlm_u_tlm_tx_pm_ctrl_N_21863_i_4126) + ); + defparam com_tlm_u_tlm_tx_pm_ctrl_un1_cfg_ct_axb_4.INIT = 4'h6; + LUT2_L com_tlm_u_tlm_tx_pm_ctrl_un1_cfg_ct_axb_4 ( + .I0(com_tlm_u_tlm_tx_pm_ctrl_cfg_ct23), + .I1(com_tlm_u_tlm_tx_pm_ctrl_cfg_ct[4]), + .LO(com_tlm_u_tlm_tx_pm_ctrl_un1_cfg_ct_axb_4_4127) + ); + defparam com_tlm_u_tlm_tx_pm_ctrl_un1_cfg_ct_axb_3.INIT = 4'h6; + LUT2_L com_tlm_u_tlm_tx_pm_ctrl_un1_cfg_ct_axb_3 ( + .I0(com_tlm_u_tlm_tx_pm_ctrl_cfg_ct23), + .I1(com_tlm_u_tlm_tx_pm_ctrl_cfg_ct[3]), + .LO(com_tlm_u_tlm_tx_pm_ctrl_un1_cfg_ct_axb_3_4128) + ); + defparam com_tlm_u_tlm_tx_pm_ctrl_un1_cfg_ct_axb_2.INIT = 4'h6; + LUT2_L com_tlm_u_tlm_tx_pm_ctrl_un1_cfg_ct_axb_2 ( + .I0(com_tlm_u_tlm_tx_pm_ctrl_cfg_ct23), + .I1(com_tlm_u_tlm_tx_pm_ctrl_cfg_ct[2]), + .LO(com_tlm_u_tlm_tx_pm_ctrl_un1_cfg_ct_axb_2_4129) + ); + defparam com_tlm_u_tlm_tx_pm_ctrl_un1_cfg_ct_axb_1.INIT = 8'hA6; + LUT3_L com_tlm_u_tlm_tx_pm_ctrl_un1_cfg_ct_axb_1 ( + .I0(com_tlm_u_tlm_tx_pm_ctrl_cfg_ct[1]), + .I1(com_tlm_u_tlm_tx_cfg_sent), + .I2(com_tlm_u_tlm_tx_cfg_accepted), + .LO(com_tlm_u_tlm_tx_pm_ctrl_un1_cfg_ct_axb_1_4130) + ); + GND com_tlm_u_tlm_rx_vc0_rd_mon_GND ( + .G(com_tlm_u_tlm_rx_vc0_rd_mon_GND_4131) + ); + FDS com_tlm_u_tlm_rx_vc0_rd_mon_word_ct_0_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_rd_mon_N_16449_i), + .Q(com_tlm_u_tlm_rx_vc0_rd_mon_word_ct[0]), + .S(plm_link_up_i) + ); + FDRS com_tlm_u_tlm_rx_vc0_rd_mon_fc_free_1data_o ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_rd_mon_N_86267_i_4143), + .Q(com_tlm_u_tlm_rx_vc0_fc_free_1data), + .R(plm_link_up_i), + .S(com_tlm_u_tlm_rx_vc0_rd_mon_fc_free_1data_d_4142) + ); + FDR com_tlm_u_tlm_rx_vc0_rd_mon_fc_free_1header_o ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_rd_mon_N_86549_i_4140), + .Q(com_tlm_u_tlm_rx_vc0_fc_free_1header), + .R(plm_link_up_i) + ); + FDRE com_tlm_u_tlm_rx_vc0_rd_mon_unaligned_header_q ( + .CE(com_tlm_u_tlm_rx_vc0_rd_mon_N_86433_i_4133), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_rd_mon_N_56476_i_0_i_4139), + .Q(com_tlm_u_tlm_rx_vc0_rd_mon_unaligned_header_q_4132), + .R(plm_link_up_i) + ); + FDRSE com_tlm_u_tlm_rx_vc0_rd_mon_in_header ( + .CE(com_tlm_u_tlm_rx_vc0_rd_mon_N_86550_i_4134), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_rd_mon_GND_4131), + .Q(com_tlm_u_tlm_rx_vc0_rd_mon_in_header_4144), + .R(plm_link_up_i), + .S(com_tlm_u_tlm_rx_vc0_rd_mon_N_86433_i_4133) + ); + FDR com_tlm_u_tlm_rx_vc0_rd_mon_fc_free_p_o ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_rd_mon_fc_free_p_o_3_4136), + .Q(com_tlm_u_tlm_rx_vc0_fc_free_p), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_rx_vc0_rd_mon_fc_free_np_o ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_rd_mon_np_q_4137), + .Q(com_tlm_u_tlm_rx_vc0_fc_free_np), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_rx_vc0_rd_mon_fc_free_cpl_o ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_rd_mon_cpl_q_4138), + .Q(com_tlm_u_tlm_rx_vc0_fc_free_cpl), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_rx_vc0_rd_mon_np_q ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_np), + .Q(com_tlm_u_tlm_rx_vc0_rd_mon_np_q_4137), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_rx_vc0_rd_mon_cpl_q ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_cpl), + .Q(com_tlm_u_tlm_rx_vc0_rd_mon_cpl_q_4138), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_rx_vc0_rd_mon_fc_free_eof_o ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_rd_mon_N_60499_i_4135), + .Q(com_tlm_u_tlm_rx_vc0_fc_free_eof), + .R(plm_link_up_i) + ); + defparam com_tlm_u_tlm_rx_vc0_rd_mon_word_ct_8_iv_i_0_0_o3_1_0_.INIT = 4'h4; + LUT2 com_tlm_u_tlm_rx_vc0_rd_mon_word_ct_8_iv_i_0_0_o3_1_0_ ( + .I0(cfg_cfg_6102[508]), + .I1(NlwRenamedSig_OI_trn_rd[47]), + .O(com_tlm_u_tlm_rx_vc0_rd_mon_N_56116_i) + ); + defparam com_tlm_u_tlm_rx_vc0_rd_mon_un1_trn_active_word_0_a2_i_o2_0_o3_0.INIT = 4'h4; + LUT2 com_tlm_u_tlm_rx_vc0_rd_mon_un1_trn_active_word_0_a2_i_o2_0_o3_0 ( + .I0(com_cmmt_rdst_rdy_n), + .I1(com_cmmt_rsrc_rdy), + .O(com_tlm_u_tlm_rx_vc0_N_55978_i) + ); + defparam com_tlm_u_tlm_rx_vc0_rd_mon_word_ct_8_iv_i_0_0_a3_0_.INIT = 4'h1; + LUT2 com_tlm_u_tlm_rx_vc0_rd_mon_word_ct_8_iv_i_0_0_a3_0_ ( + .I0(com_tlm_u_tlm_rx_vc0_trn_reof), + .I1(com_tlm_u_tlm_rx_vc0_trn_rsof), + .O(com_tlm_u_tlm_rx_vc0_rd_mon_N_61417) + ); + defparam com_tlm_u_tlm_rx_vc0_rd_mon_un1_trn_active_word_0_a2_i_o2_0_o3.INIT = 4'h2; + LUT2 com_tlm_u_tlm_rx_vc0_rd_mon_un1_trn_active_word_0_a2_i_o2_0_o3 ( + .I0(com_tlm_u_tlm_rx_vc0_trn_rsrc_rdy), + .I1(trn_rdst_rdy_n), + .O(com_tlm_u_tlm_rx_vc0_N_55948_i) + ); + defparam com_tlm_u_tlm_rx_vc0_rd_mon_fc_free_1data_d_1_sqmuxa_0_a2_0_a2_0_a2_1.INIT = 16'h0800; + LUT4 com_tlm_u_tlm_rx_vc0_rd_mon_fc_free_1data_d_1_sqmuxa_0_a2_0_a2_0_a2_1 ( + .I0(com_tlm_u_tlm_rx_vc0_trn_rrem), + .I1(com_tlm_u_tlm_rx_vc0_rd_mon_unaligned_header_q_4132), + .I2(com_tlm_u_tlm_rx_vc0_rd_mon_word_ct[0]), + .I3(plm_link_up_1), + .O(com_tlm_u_tlm_rx_vc0_rd_mon_N_60501_3) + ); + defparam com_tlm_u_tlm_rx_vc0_rd_mon_fc_free_eof_o17_0_a2_0_a2_i_a2.INIT = 8'h13; + LUT3 com_tlm_u_tlm_rx_vc0_rd_mon_fc_free_eof_o17_0_a2_0_a2_i_a2 ( + .I0(com_tlm_u_tlm_rx_vc0_N_55948_i), + .I1(com_tlm_u_tlm_rx_vc0_N_56232_i), + .I2(com_tlm_u_tlm_rx_vc0_trn_reof), + .O(com_tlm_u_tlm_rx_vc0_N_60499) + ); + defparam com_tlm_u_tlm_rx_vc0_rd_mon_word_ct_8_iv_i_0_0_a2_0_.INIT = 16'h20A0; + LUT4 com_tlm_u_tlm_rx_vc0_rd_mon_word_ct_8_iv_i_0_0_a2_0_ ( + .I0(com_tlm_u_tlm_rx_vc0_N_55948_i), + .I1(com_tlm_u_tlm_rx_vc0_rd_mon_N_56116_i), + .I2(com_tlm_u_tlm_rx_vc0_trn_rsof), + .I3(NlwRenamedSig_OI_trn_rd[61]), + .O(com_tlm_u_tlm_rx_vc0_rd_mon_N_58442) + ); + defparam com_tlm_u_tlm_rx_vc0_rd_mon_word_ct_8_iv_i_0_0_a2_0_0_.INIT = 16'h20A0; + LUT4 com_tlm_u_tlm_rx_vc0_rd_mon_word_ct_8_iv_i_0_0_a2_0_0_ ( + .I0(com_tlm_u_tlm_rx_vc0_N_55978_i), + .I1(com_tlm_u_tlm_rx_vc0_rd_mon_N_56116_i), + .I2(com_tlm_u_tlm_rx_vc0_cmmt_rsof), + .I3(NlwRenamedSig_OI_trn_rd[61]), + .O(com_tlm_u_tlm_rx_vc0_rd_mon_N_58443) + ); + defparam com_tlm_u_tlm_rx_vc0_rd_mon_N_86433_i.INIT = 16'hEAC0; + LUT4 com_tlm_u_tlm_rx_vc0_rd_mon_N_86433_i ( + .I0(com_tlm_u_tlm_rx_vc0_N_55948_i), + .I1(com_tlm_u_tlm_rx_vc0_N_55978_i), + .I2(com_tlm_u_tlm_rx_vc0_cmmt_rsof), + .I3(com_tlm_u_tlm_rx_vc0_trn_rsof), + .O(com_tlm_u_tlm_rx_vc0_rd_mon_N_86433_i_4133) + ); + defparam com_tlm_u_tlm_rx_vc0_rd_mon_N_86550_i.INIT = 8'h0E; + LUT3 com_tlm_u_tlm_rx_vc0_rd_mon_N_86550_i ( + .I0(com_tlm_u_tlm_rx_vc0_N_55948_i), + .I1(com_tlm_u_tlm_rx_vc0_N_55978_i), + .I2(com_tlm_u_tlm_rx_vc0_rd_mon_word_ct[0]), + .O(com_tlm_u_tlm_rx_vc0_rd_mon_N_86550_i_4134) + ); + defparam com_tlm_u_tlm_rx_vc0_rd_mon_word_ct_8_iv_i_0_0_a2_1_1_0_.INIT = 16'hE411; + LUT4 com_tlm_u_tlm_rx_vc0_rd_mon_word_ct_8_iv_i_0_0_a2_1_1_0_ ( + .I0(com_tlm_u_tlm_rx_vc0_N_55948_i), + .I1(com_tlm_u_tlm_rx_vc0_N_55978_i), + .I2(com_tlm_u_tlm_rx_vc0_rd_mon_N_61417), + .I3(com_tlm_u_tlm_rx_vc0_rd_mon_word_ct[0]), + .O(com_tlm_u_tlm_rx_vc0_rd_mon_N_58444_1) + ); + defparam com_tlm_u_tlm_rx_vc0_rd_mon_word_ct_8_iv_i_0_0_1_0_.INIT = 16'h0203; + LUT4_L com_tlm_u_tlm_rx_vc0_rd_mon_word_ct_8_iv_i_0_0_1_0_ ( + .I0(com_tlm_u_tlm_rx_vc0_N_55978_i), + .I1(com_tlm_u_tlm_rx_vc0_rd_mon_N_58442), + .I2(com_tlm_u_tlm_rx_vc0_rd_mon_N_58443), + .I3(com_tlm_u_tlm_rx_vc0_rd_mon_N_58444_1), + .LO(com_tlm_u_tlm_rx_vc0_rd_mon_word_ct_8_iv_i_0_0_1[0]) + ); + defparam com_tlm_u_tlm_rx_vc0_rd_mon_N_60499_i.INIT = 4'h1; + LUT1_L com_tlm_u_tlm_rx_vc0_rd_mon_N_60499_i ( + .I0(com_tlm_u_tlm_rx_vc0_N_60499), + .LO(com_tlm_u_tlm_rx_vc0_rd_mon_N_60499_i_4135) + ); + defparam com_tlm_u_tlm_rx_vc0_rd_mon_N_86706_i.INIT = 16'hE0C0; + LUT4_L com_tlm_u_tlm_rx_vc0_rd_mon_N_86706_i ( + .I0(com_tlm_u_tlm_rx_vc0_N_55948_i), + .I1(com_tlm_u_tlm_rx_vc0_N_56232_i), + .I2(com_tlm_u_tlm_rx_vc0_rd_mon_N_60501_3), + .I3(com_tlm_u_tlm_rx_vc0_trn_reof), + .LO(com_tlm_u_tlm_rx_vc0_rd_mon_N_86706_i_4141) + ); + defparam com_tlm_u_tlm_rx_vc0_rd_mon_fc_free_p_o_3.INIT = 4'h1; + LUT2_L com_tlm_u_tlm_rx_vc0_rd_mon_fc_free_p_o_3 ( + .I0(com_tlm_u_tlm_rx_vc0_rd_mon_cpl_q_4138), + .I1(com_tlm_u_tlm_rx_vc0_rd_mon_np_q_4137), + .LO(com_tlm_u_tlm_rx_vc0_rd_mon_fc_free_p_o_3_4136) + ); + defparam com_tlm_u_tlm_rx_vc0_rd_mon_N_56476_i_0_i.INIT = 4'h9; + LUT2_L com_tlm_u_tlm_rx_vc0_rd_mon_N_56476_i_0_i ( + .I0(com_tlm_u_tlm_rx_vc0_rd_mon_N_56116_i), + .I1(NlwRenamedSig_OI_trn_rd[61]), + .LO(com_tlm_u_tlm_rx_vc0_rd_mon_N_56476_i_0_i_4139) + ); + defparam com_tlm_u_tlm_rx_vc0_rd_mon_N_86549_i.INIT = 16'h00E0; + LUT4_L com_tlm_u_tlm_rx_vc0_rd_mon_N_86549_i ( + .I0(com_tlm_u_tlm_rx_vc0_N_55948_i), + .I1(com_tlm_u_tlm_rx_vc0_N_55978_i), + .I2(com_tlm_u_tlm_rx_vc0_rd_mon_in_header_4144), + .I3(com_tlm_u_tlm_rx_vc0_rd_mon_word_ct[0]), + .LO(com_tlm_u_tlm_rx_vc0_rd_mon_N_86549_i_4140) + ); + defparam com_tlm_u_tlm_rx_vc0_rd_mon_word_ct_8_iv_i_0_0_0_.INIT = 16'hFD00; + LUT4_L com_tlm_u_tlm_rx_vc0_rd_mon_word_ct_8_iv_i_0_0_0_ ( + .I0(com_tlm_u_tlm_rx_vc0_rd_mon_N_58444_1), + .I1(com_tlm_u_tlm_rx_vc0_cmmt_reof), + .I2(com_tlm_u_tlm_rx_vc0_cmmt_rsof), + .I3(com_tlm_u_tlm_rx_vc0_rd_mon_word_ct_8_iv_i_0_0_1[0]), + .LO(com_tlm_u_tlm_rx_vc0_rd_mon_N_16449_i) + ); + defparam com_tlm_u_tlm_rx_vc0_rd_mon_N_86267_i_1.INIT = 16'h5F11; + LUT4_L com_tlm_u_tlm_rx_vc0_rd_mon_N_86267_i_1 ( + .I0(com_tlm_u_tlm_rx_vc0_N_55948_i), + .I1(com_tlm_u_tlm_rx_vc0_N_55978_i), + .I2(com_tlm_u_tlm_rx_vc0_trn_reof), + .I3(com_tlm_u_tlm_rx_vc0_rd_mon_word_ct[0]), + .LO(com_tlm_u_tlm_rx_vc0_rd_mon_N_86267_i_1_4145) + ); + defparam com_tlm_u_tlm_rx_vc0_rd_mon_un1_trn_active_word_0_a2_i_o2_0.INIT = 8'h51; + LUT3 com_tlm_u_tlm_rx_vc0_rd_mon_un1_trn_active_word_0_a2_i_o2_0 ( + .I0(com_tlm_u_tlm_rx_vc0_N_55948_i), + .I1(com_cmmt_rsrc_rdy), + .I2(com_cmmt_rdst_rdy_n), + .O(com_tlm_u_tlm_rx_vc0_un1_trn_active_word_0_a2_i_o2_0) + ); + FD com_tlm_u_tlm_rx_vc0_rd_mon_fc_free_1data_d ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_rd_mon_N_86706_i_4141), + .Q(com_tlm_u_tlm_rx_vc0_rd_mon_fc_free_1data_d_4142) + ); + defparam com_tlm_u_tlm_rx_vc0_rd_mon_N_86267_i.INIT = 16'h008F; + LUT4_L com_tlm_u_tlm_rx_vc0_rd_mon_N_86267_i ( + .I0(com_tlm_u_tlm_rx_vc0_N_55978_i), + .I1(com_tlm_u_tlm_rx_vc0_cmmt_reof), + .I2(com_tlm_u_tlm_rx_vc0_rd_mon_N_86267_i_1_4145), + .I3(com_tlm_u_tlm_rx_vc0_rd_mon_in_header_4144), + .LO(com_tlm_u_tlm_rx_vc0_rd_mon_N_86267_i_4143) + ); + GND com_tlm_u_tlm_rx_vc0_fifo_GND ( + .G(com_tlm_u_tlm_rx_vc0_fifo_GND_4146) + ); + FDRSE com_tlm_u_tlm_rx_vc0_fifo_select_bq ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_N_85839_i_4240), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_GND_4146), + .Q(com_tlm_u_tlm_rx_vc0_fifo_select_bq_4161), + .R(plm_link_up_i), + .S(com_tlm_u_tlm_rx_vc0_fifo_select_bq_0_sqmuxa_4152) + ); + FDRE com_tlm_u_tlm_rx_vc0_fifo_select_usr ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_N_85839_i_4240), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_select_usr_7), + .Q(com_tlm_u_tlm_rx_vc0_fifo_select_usr_4157), + .R(plm_link_up_i) + ); + FDRE com_tlm_u_tlm_rx_vc0_fifo_select_cfg ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_N_85839_i_4240), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_select_cfg_7), + .Q(com_tlm_u_tlm_rx_vc0_fifo_select_cfg_4159), + .R(plm_link_up_i) + ); + FDRE com_tlm_u_tlm_rx_vc0_fifo_select_oq ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_N_85839_i_4240), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_select_bq17_4164), + .Q(com_tlm_u_tlm_rx_vc0_fifo_select_oq_4160), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_rx_vc0_fifo_select_oq2bq_d ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_select_oq2bq_d_5_4162), + .Q(com_tlm_u_tlm_rx_vc0_fifo_select_oq2bq_d_4163), + .R(plm_link_up_i) + ); + FDRE com_tlm_u_tlm_rx_vc0_fifo_cfg_src_rdy_d ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_N_10675_i_i_i_4239), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_cfg_src_rdy_d_3_4158), + .Q(com_cmmt_rsrc_rdy), + .R(plm_link_up_i) + ); + FDRE com_tlm_u_tlm_rx_vc0_fifo_usr_src_rdy_d ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_N_10675_i_i_i_4239), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_usr_src_rdy_d_3_4156), + .Q(com_tlm_u_tlm_rx_vc0_trn_rsrc_rdy), + .R(plm_link_up_i) + ); + FDRE com_tlm_u_tlm_rx_vc0_fifo_usr_sof_d ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_N_10675_i_i_i_4239), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_N_10669_i_4155), + .Q(com_tlm_u_tlm_rx_vc0_trn_rsof), + .R(plm_link_up_i) + ); + FDRE com_tlm_u_tlm_rx_vc0_fifo_select_oq2bq ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_un1_select_oq2bq_d_1_i_4237), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_select_oq2bq_5), + .Q(com_tlm_u_tlm_rx_vc0_fifo_select_oq2bq_4169), + .R(plm_link_up_i) + ); + FDRE com_tlm_u_tlm_rx_vc0_fifo_cfg_eof_d ( + .CE(com_tlm_u_tlm_rx_vc0_N_55978_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_N_10672_i_4148), + .Q(com_tlm_u_tlm_rx_vc0_cmmt_reof), + .R(plm_link_up_i) + ); + FDRE com_tlm_u_tlm_rx_vc0_fifo_cfg_sof_d ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_N_10675_i_i_i_4239), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_N_86093_i_4154), + .Q(com_tlm_u_tlm_rx_vc0_cmmt_rsof), + .R(plm_link_up_i) + ); + FDRE com_tlm_u_tlm_rx_vc0_fifo_usr_eof_d ( + .CE(com_tlm_u_tlm_rx_vc0_N_55948_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_N_10672_i_4148), + .Q(com_tlm_u_tlm_rx_vc0_trn_reof), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_rx_vc0_fifo_wen_aux_oq ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_wen_aux_oq_3), + .Q(com_tlm_u_tlm_rx_vc0_fifo_wen_aux_oq_4147), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_rx_vc0_fifo_usr_src_dsc_o ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_reset_i_q_i_4153), + .Q(com_tlm_u_tlm_rx_vc0_fifo_trn_rsrc_dsc), + .R(plm_link_up) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_adv_pkt_out_i_0_0_a2.INIT = 4'h1; + LUT2 com_tlm_u_tlm_rx_vc0_fifo_adv_pkt_out_i_0_0_a2 ( + .I0(com_cmmt_rsrc_rdy), + .I1(com_tlm_u_tlm_rx_vc0_trn_rsrc_rdy), + .O(com_tlm_u_tlm_rx_vc0_fifo_N_58449) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_cfg_nxt_rdy_0_a2_0_a2_0_a2.INIT = 4'h1; + LUT2 com_tlm_u_tlm_rx_vc0_fifo_cfg_nxt_rdy_0_a2_0_a2_0_a2 ( + .I0(com_cmmt_rdst_rdy_n), + .I1(com_cmmt_rsrc_rdy), + .O(com_tlm_u_tlm_rx_vc0_fifo_cfg_nxt_rdy) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_rem_out_rem_out_rem_d_2_0_o3.INIT = 4'h8; + LUT2 com_tlm_u_tlm_rx_vc0_fifo_rem_out_rem_out_rem_d_2_0_o3 ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_data_vld_oqr), + .I1(com_tlm_u_tlm_rx_vc0_fifo_select_oq_4160), + .O(com_tlm_u_tlm_rx_vc0_fifo_N_44082_i) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_un4_usr_sof_d_1_0_a2.INIT = 4'h8; + LUT2 com_tlm_u_tlm_rx_vc0_fifo_un4_usr_sof_d_1_0_a2 ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_data_bqr_64_), + .I1(com_tlm_u_tlm_rx_vc0_fifo_select_bq_4161), + .O(com_tlm_u_tlm_rx_vc0_fifo_un4_usr_sof_d_1) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_un1_select_oq2bq_d_1.INIT = 4'h1; + LUT2 com_tlm_u_tlm_rx_vc0_fifo_un1_select_oq2bq_d_1 ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_select_oq2bq_4169), + .I1(com_tlm_u_tlm_rx_vc0_fifo_select_oq2bq_d_4163), + .O(com_tlm_u_tlm_rx_vc0_fifo_un1_select_oq2bq_d_1_4238) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_bar_d_1_0_m3_0_0_.INIT = 8'hCA; + LUT3_L com_tlm_u_tlm_rx_vc0_fifo_bar_d_1_0_m3_0_0_ ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_aux[0]), + .I1(com_tlm_u_tlm_rx_vc0_fifo_aux_q[0]), + .I2(com_tlm_u_tlm_rx_vc0_fifo_sof_hold), + .LO(com_tlm_u_tlm_rx_vc0_fifo_N_44256) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_bar_d_1_0_m3_0_1_.INIT = 8'hCA; + LUT3_L com_tlm_u_tlm_rx_vc0_fifo_bar_d_1_0_m3_0_1_ ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_aux[1]), + .I1(com_tlm_u_tlm_rx_vc0_fifo_aux_q[1]), + .I2(com_tlm_u_tlm_rx_vc0_fifo_sof_hold), + .LO(com_tlm_u_tlm_rx_vc0_fifo_N_44257) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_bar_d_1_0_m3_0_2_.INIT = 8'hCA; + LUT3_L com_tlm_u_tlm_rx_vc0_fifo_bar_d_1_0_m3_0_2_ ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_aux[2]), + .I1(com_tlm_u_tlm_rx_vc0_fifo_aux_q[2]), + .I2(com_tlm_u_tlm_rx_vc0_fifo_sof_hold), + .LO(com_tlm_u_tlm_rx_vc0_fifo_N_44258) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_bar_d_1_0_m3_0_3_.INIT = 8'hCA; + LUT3_L com_tlm_u_tlm_rx_vc0_fifo_bar_d_1_0_m3_0_3_ ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_aux[3]), + .I1(com_tlm_u_tlm_rx_vc0_fifo_aux_q[3]), + .I2(com_tlm_u_tlm_rx_vc0_fifo_sof_hold), + .LO(com_tlm_u_tlm_rx_vc0_fifo_N_44259) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_bar_d_1_0_m3_0_4_.INIT = 8'hCA; + LUT3_L com_tlm_u_tlm_rx_vc0_fifo_bar_d_1_0_m3_0_4_ ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_aux[4]), + .I1(com_tlm_u_tlm_rx_vc0_fifo_aux_q[4]), + .I2(com_tlm_u_tlm_rx_vc0_fifo_sof_hold), + .LO(com_tlm_u_tlm_rx_vc0_fifo_N_44260) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_bar_d_1_0_m3_0_5_.INIT = 8'hCA; + LUT3_L com_tlm_u_tlm_rx_vc0_fifo_bar_d_1_0_m3_0_5_ ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_aux[5]), + .I1(com_tlm_u_tlm_rx_vc0_fifo_aux_q[5]), + .I2(com_tlm_u_tlm_rx_vc0_fifo_sof_hold), + .LO(com_tlm_u_tlm_rx_vc0_fifo_N_44261) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_bar_d_1_0_m3_0_6_.INIT = 8'hCA; + LUT3_L com_tlm_u_tlm_rx_vc0_fifo_bar_d_1_0_m3_0_6_ ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_aux[6]), + .I1(com_tlm_u_tlm_rx_vc0_fifo_aux_q[6]), + .I2(com_tlm_u_tlm_rx_vc0_fifo_sof_hold), + .LO(com_tlm_u_tlm_rx_vc0_fifo_N_44262) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_adv_pkt_out_i_0_0_o3_0.INIT = 4'h8; + LUT2 com_tlm_u_tlm_rx_vc0_fifo_adv_pkt_out_i_0_0_o3_0 ( + .I0(com_tlm_u_tlm_rx_vc0_N_55978_i), + .I1(com_tlm_u_tlm_rx_vc0_cmmt_reof), + .O(com_tlm_u_tlm_rx_vc0_N_56232_i) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_un6_usr_sof_d_1_0_a2.INIT = 4'h8; + LUT2 com_tlm_u_tlm_rx_vc0_fifo_un6_usr_sof_d_1_0_a2 ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_N_44082_i), + .I1(com_tlm_u_tlm_rx_vc0_fifo_ram_dout[64]), + .O(com_tlm_u_tlm_rx_vc0_fifo_un6_usr_sof_d_1) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_un4_adv_pkt_oq_0.INIT = 16'h8BBB; + LUT4_L com_tlm_u_tlm_rx_vc0_fifo_un4_adv_pkt_oq_0 ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_cfg_nxt_rdy), + .I1(com_tlm_u_tlm_rx_vc0_fifo_cfg_oqr), + .I2(com_tlm_u_tlm_rx_vc0_fifo_np_oqr), + .I3(trn_rnp_ok_n), + .LO(com_tlm_u_tlm_rx_vc0_fifo_un4_adv_pkt_oq) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_adv_pkt_bq_0.INIT = 16'hCA00; + LUT4 com_tlm_u_tlm_rx_vc0_fifo_adv_pkt_bq_0 ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_aux_vld), + .I1(com_tlm_u_tlm_rx_vc0_fifo_aux_vld_q), + .I2(com_tlm_u_tlm_rx_vc0_fifo_sof_hold), + .I3(com_tlm_u_tlm_rx_vc0_fifo_data_vld_bqr), + .O(com_tlm_u_tlm_rx_vc0_fifo_adv_pkt_bq_0_4149) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_adv_pkt_in_i_0.INIT = 16'h8CA0; + LUT4 com_tlm_u_tlm_rx_vc0_fifo_adv_pkt_in_i_0 ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_data_vld_bqr), + .I1(com_tlm_u_tlm_rx_vc0_fifo_data_vld_oqr), + .I2(com_tlm_u_tlm_rx_vc0_fifo_select_bq_4161), + .I3(com_tlm_u_tlm_rx_vc0_fifo_select_oq_4160), + .O(com_tlm_u_tlm_rx_vc0_fifo_adv_pkt_in_i_0_4151) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_N_44895_i.INIT = 16'hECA0; + LUT4 com_tlm_u_tlm_rx_vc0_fifo_N_44895_i ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_data_bqr_46_), + .I1(com_tlm_u_tlm_rx_vc0_fifo_ep_oqr), + .I2(com_tlm_u_tlm_rx_vc0_fifo_select_bq_4161), + .I3(com_tlm_u_tlm_rx_vc0_fifo_select_oq_4160), + .O(com_tlm_u_tlm_rx_vc0_fifo_N_44895_i_4190) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_N_10675_i_0_o2_0.INIT = 4'h4; + LUT2 com_tlm_u_tlm_rx_vc0_fifo_N_10675_i_0_o2_0 ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_N_58449), + .I1(com_tlm_u_tlm_rx_vc0_un1_trn_active_word_0_a2_i_o2_0), + .O(com_tlm_u_tlm_rx_vc0_fifo_N_10675_i_i) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_N_10672_i.INIT = 16'hECA0; + LUT4 com_tlm_u_tlm_rx_vc0_fifo_N_10672_i ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_data_bqr_65_), + .I1(com_tlm_u_tlm_rx_vc0_fifo_eof_oqr), + .I2(com_tlm_u_tlm_rx_vc0_fifo_select_bq_4161), + .I3(com_tlm_u_tlm_rx_vc0_fifo_select_oq_4160), + .O(com_tlm_u_tlm_rx_vc0_fifo_N_10672_i_4148) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_adv_pkt_bq.INIT = 16'h80C4; + LUT4 com_tlm_u_tlm_rx_vc0_fifo_adv_pkt_bq ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_N_44111), + .I1(com_tlm_u_tlm_rx_vc0_fifo_adv_pkt_bq_0_4149), + .I2(com_tlm_u_tlm_rx_vc0_fifo_cfg_nxt_rdy), + .I3(trn_rnp_ok_n), + .O(com_tlm_u_tlm_rx_vc0_fifo_adv_pkt_bq_4165) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_ren_oq_i_a3_0.INIT = 16'h004F; + LUT4 com_tlm_u_tlm_rx_vc0_fifo_ren_oq_i_a3_0 ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_N_58449), + .I1(com_tlm_u_tlm_rx_vc0_un1_trn_active_word_0_a2_i_o2_0), + .I2(com_tlm_u_tlm_rx_vc0_fifo_select_oq_4160), + .I3(com_tlm_u_tlm_rx_vc0_fifo_select_oq2bq_4169), + .O(com_tlm_u_tlm_rx_vc0_fifo_ren_oq_i_a3_0_4150) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_N_86703_i.INIT = 4'hB; + LUT2 com_tlm_u_tlm_rx_vc0_fifo_N_86703_i ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_N_58449), + .I1(com_tlm_u_tlm_rx_vc0_N_60499), + .O(com_tlm_u_tlm_rx_vc0_fifo_N_86703_i_4171) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_adv_pkt_in_i_a2_0.INIT = 8'h40; + LUT3 com_tlm_u_tlm_rx_vc0_fifo_adv_pkt_in_i_a2_0 ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_N_10675_i_i), + .I1(com_tlm_u_tlm_rx_vc0_fifo_data_bqr_65_), + .I2(com_tlm_u_tlm_rx_vc0_fifo_select_bq_4161), + .O(com_tlm_u_tlm_rx_vc0_fifo_N_44893) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_adv_pkt_in_i_a2.INIT = 16'hC040; + LUT4 com_tlm_u_tlm_rx_vc0_fifo_adv_pkt_in_i_a2 ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_N_10675_i_i), + .I1(com_tlm_u_tlm_rx_vc0_fifo_ram_dout[65]), + .I2(com_tlm_u_tlm_rx_vc0_fifo_select_oq_4160), + .I3(com_tlm_u_tlm_rx_vc0_fifo_select_oq2bq_4169), + .O(com_tlm_u_tlm_rx_vc0_fifo_N_44892) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_un1_data_oqr_0_0_.INIT = 8'hB8; + LUT3_L com_tlm_u_tlm_rx_vc0_fifo_un1_data_oqr_0_0_ ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_N_44135_i), + .I1(com_tlm_u_tlm_rx_vc0_fifo_ren_oq_i_a3_0_4150), + .I2(com_tlm_u_tlm_rx_vc0_fifo_eof_oqr), + .LO(com_tlm_u_tlm_rx_vc0_fifo_un1_data_oqr[0]) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_adv_pkt_in_i.INIT = 8'h10; + LUT3 com_tlm_u_tlm_rx_vc0_fifo_adv_pkt_in_i ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_N_44892), + .I1(com_tlm_u_tlm_rx_vc0_fifo_N_44893), + .I2(com_tlm_u_tlm_rx_vc0_fifo_adv_pkt_in_i_0_4151), + .O(com_tlm_u_tlm_rx_vc0_fifo_adv_pkt_in_i_4241) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_select_bq_0_sqmuxa.INIT = 4'h4; + LUT2 com_tlm_u_tlm_rx_vc0_fifo_select_bq_0_sqmuxa ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_adv_pkt_in_i_4241), + .I1(com_tlm_u_tlm_rx_vc0_fifo_adv_pkt_bq_4165), + .O(com_tlm_u_tlm_rx_vc0_fifo_select_bq_0_sqmuxa_4152) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_reset_i_q_i.INIT = 4'h1; + LUT1_L com_tlm_u_tlm_rx_vc0_fifo_reset_i_q_i ( + .I0(com_reset_i_q), + .LO(com_tlm_u_tlm_rx_vc0_fifo_reset_i_q_i_4153) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_rem_out_rem_out_rem_d_2_0.INIT = 16'hECA0; + LUT4_L com_tlm_u_tlm_rx_vc0_fifo_rem_out_rem_out_rem_d_2_0 ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_N_44082_i), + .I1(com_tlm_u_tlm_rx_vc0_fifo_data_bqr_67_), + .I2(com_tlm_u_tlm_rx_vc0_fifo_ram_dout[67]), + .I3(com_tlm_u_tlm_rx_vc0_fifo_select_bq_4161), + .LO(com_tlm_u_tlm_rx_vc0_fifo_N_10673_i) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_N_86093_i.INIT = 16'hECA0; + LUT4_L com_tlm_u_tlm_rx_vc0_fifo_N_86093_i ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_N_44111), + .I1(com_tlm_u_tlm_rx_vc0_fifo_cfg_oqr), + .I2(com_tlm_u_tlm_rx_vc0_fifo_un4_usr_sof_d_1), + .I3(com_tlm_u_tlm_rx_vc0_fifo_un6_usr_sof_d_1), + .LO(com_tlm_u_tlm_rx_vc0_fifo_N_86093_i_4154) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_select_oq2bq_5_0.INIT = 16'h0A33; + LUT4_L com_tlm_u_tlm_rx_vc0_fifo_select_oq2bq_5_0 ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_data_vld_oqr), + .I1(com_tlm_u_tlm_rx_vc0_fifo_eof_oqr), + .I2(com_tlm_u_tlm_rx_vc0_fifo_select_oq_4160), + .I3(com_tlm_u_tlm_rx_vc0_fifo_select_oq2bq_d_4163), + .LO(com_tlm_u_tlm_rx_vc0_fifo_select_oq2bq_5) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_N_10669_i.INIT = 16'h7350; + LUT4_L com_tlm_u_tlm_rx_vc0_fifo_N_10669_i ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_N_44111), + .I1(com_tlm_u_tlm_rx_vc0_fifo_cfg_oqr), + .I2(com_tlm_u_tlm_rx_vc0_fifo_un4_usr_sof_d_1), + .I3(com_tlm_u_tlm_rx_vc0_fifo_un6_usr_sof_d_1), + .LO(com_tlm_u_tlm_rx_vc0_fifo_N_10669_i_4155) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_bar_d_1_0_6_.INIT = 16'hECA0; + LUT4_L com_tlm_u_tlm_rx_vc0_fifo_bar_d_1_0_6_ ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_N_44262), + .I1(com_tlm_u_tlm_rx_vc0_fifo_aux_oqr[6]), + .I2(com_tlm_u_tlm_rx_vc0_fifo_select_bq_4161), + .I3(com_tlm_u_tlm_rx_vc0_fifo_select_oq_4160), + .LO(com_tlm_u_tlm_rx_vc0_fifo_N_10460_i) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_bar_d_1_0_5_.INIT = 16'hECA0; + LUT4_L com_tlm_u_tlm_rx_vc0_fifo_bar_d_1_0_5_ ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_N_44261), + .I1(com_tlm_u_tlm_rx_vc0_fifo_aux_oqr[5]), + .I2(com_tlm_u_tlm_rx_vc0_fifo_select_bq_4161), + .I3(com_tlm_u_tlm_rx_vc0_fifo_select_oq_4160), + .LO(com_tlm_u_tlm_rx_vc0_fifo_N_10461_i) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_bar_d_1_0_4_.INIT = 16'hECA0; + LUT4_L com_tlm_u_tlm_rx_vc0_fifo_bar_d_1_0_4_ ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_N_44260), + .I1(com_tlm_u_tlm_rx_vc0_fifo_aux_oqr[4]), + .I2(com_tlm_u_tlm_rx_vc0_fifo_select_bq_4161), + .I3(com_tlm_u_tlm_rx_vc0_fifo_select_oq_4160), + .LO(com_tlm_u_tlm_rx_vc0_fifo_N_10462_i) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_bar_d_1_0_3_.INIT = 16'hECA0; + LUT4_L com_tlm_u_tlm_rx_vc0_fifo_bar_d_1_0_3_ ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_N_44259), + .I1(com_tlm_u_tlm_rx_vc0_fifo_aux_oqr[3]), + .I2(com_tlm_u_tlm_rx_vc0_fifo_select_bq_4161), + .I3(com_tlm_u_tlm_rx_vc0_fifo_select_oq_4160), + .LO(com_tlm_u_tlm_rx_vc0_fifo_N_10463_i) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_bar_d_1_0_2_.INIT = 16'hECA0; + LUT4_L com_tlm_u_tlm_rx_vc0_fifo_bar_d_1_0_2_ ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_N_44258), + .I1(com_tlm_u_tlm_rx_vc0_fifo_aux_oqr[2]), + .I2(com_tlm_u_tlm_rx_vc0_fifo_select_bq_4161), + .I3(com_tlm_u_tlm_rx_vc0_fifo_select_oq_4160), + .LO(com_tlm_u_tlm_rx_vc0_fifo_N_10464_i) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_bar_d_1_0_1_.INIT = 16'hECA0; + LUT4_L com_tlm_u_tlm_rx_vc0_fifo_bar_d_1_0_1_ ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_N_44257), + .I1(com_tlm_u_tlm_rx_vc0_fifo_aux_oqr[1]), + .I2(com_tlm_u_tlm_rx_vc0_fifo_select_bq_4161), + .I3(com_tlm_u_tlm_rx_vc0_fifo_select_oq_4160), + .LO(com_tlm_u_tlm_rx_vc0_fifo_N_10465_i) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_bar_d_1_0_0_.INIT = 16'hECA0; + LUT4_L com_tlm_u_tlm_rx_vc0_fifo_bar_d_1_0_0_ ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_N_44256), + .I1(com_tlm_u_tlm_rx_vc0_fifo_aux_oqr[0]), + .I2(com_tlm_u_tlm_rx_vc0_fifo_select_bq_4161), + .I3(com_tlm_u_tlm_rx_vc0_fifo_select_oq_4160), + .LO(com_tlm_u_tlm_rx_vc0_fifo_N_10466_i) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_un8_cpl_d_0_a2.INIT = 4'h8; + LUT2_L com_tlm_u_tlm_rx_vc0_fifo_un8_cpl_d_0_a2 ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_N_44082_i), + .I1(com_tlm_u_tlm_rx_vc0_fifo_ram_dout[66]), + .LO(com_tlm_u_tlm_rx_vc0_fifo_un8_cpl_d_0_a2_4170) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_N_44896_i.INIT = 8'hEC; + LUT3_L com_tlm_u_tlm_rx_vc0_fifo_N_44896_i ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_np_oqr), + .I1(com_tlm_u_tlm_rx_vc0_fifo_select_bq_4161), + .I2(com_tlm_u_tlm_rx_vc0_fifo_select_oq_4160), + .LO(com_tlm_u_tlm_rx_vc0_fifo_N_44896_i_4172) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_usr_src_rdy_d_3.INIT = 16'hEA00; + LUT4_L com_tlm_u_tlm_rx_vc0_fifo_usr_src_rdy_d_3 ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_N_44082_i), + .I1(com_tlm_u_tlm_rx_vc0_fifo_data_vld_bqr), + .I2(com_tlm_u_tlm_rx_vc0_fifo_select_bq_4161), + .I3(com_tlm_u_tlm_rx_vc0_fifo_select_usr_4157), + .LO(com_tlm_u_tlm_rx_vc0_fifo_usr_src_rdy_d_3_4156) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_cfg_src_rdy_d_3.INIT = 16'hEA00; + LUT4_L com_tlm_u_tlm_rx_vc0_fifo_cfg_src_rdy_d_3 ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_N_44082_i), + .I1(com_tlm_u_tlm_rx_vc0_fifo_data_vld_bqr), + .I2(com_tlm_u_tlm_rx_vc0_fifo_select_bq_4161), + .I3(com_tlm_u_tlm_rx_vc0_fifo_select_cfg_4159), + .LO(com_tlm_u_tlm_rx_vc0_fifo_cfg_src_rdy_d_3_4158) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_N_44815_i.INIT = 16'hECA0; + LUT4_L com_tlm_u_tlm_rx_vc0_fifo_N_44815_i ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_data_bqr_63_), + .I1(com_tlm_u_tlm_rx_vc0_fifo_data_oqr_63_), + .I2(com_tlm_u_tlm_rx_vc0_fifo_select_bq_4161), + .I3(com_tlm_u_tlm_rx_vc0_fifo_select_oq_4160), + .LO(com_tlm_u_tlm_rx_vc0_fifo_N_44815_i_4173) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_N_44816_i.INIT = 16'hECA0; + LUT4_L com_tlm_u_tlm_rx_vc0_fifo_N_44816_i ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_data_bqr_62_), + .I1(com_tlm_u_tlm_rx_vc0_fifo_data_oqr_62_), + .I2(com_tlm_u_tlm_rx_vc0_fifo_select_bq_4161), + .I3(com_tlm_u_tlm_rx_vc0_fifo_select_oq_4160), + .LO(com_tlm_u_tlm_rx_vc0_fifo_N_44816_i_4174) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_N_44817_i.INIT = 16'hECA0; + LUT4_L com_tlm_u_tlm_rx_vc0_fifo_N_44817_i ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_data_bqr_61_), + .I1(com_tlm_u_tlm_rx_vc0_fifo_data_oqr_61_), + .I2(com_tlm_u_tlm_rx_vc0_fifo_select_bq_4161), + .I3(com_tlm_u_tlm_rx_vc0_fifo_select_oq_4160), + .LO(com_tlm_u_tlm_rx_vc0_fifo_N_44817_i_4175) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_N_44818_i.INIT = 16'hECA0; + LUT4_L com_tlm_u_tlm_rx_vc0_fifo_N_44818_i ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_data_bqr_60_), + .I1(com_tlm_u_tlm_rx_vc0_fifo_data_oqr_60_), + .I2(com_tlm_u_tlm_rx_vc0_fifo_select_bq_4161), + .I3(com_tlm_u_tlm_rx_vc0_fifo_select_oq_4160), + .LO(com_tlm_u_tlm_rx_vc0_fifo_N_44818_i_4176) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_N_44819_i.INIT = 16'hECA0; + LUT4_L com_tlm_u_tlm_rx_vc0_fifo_N_44819_i ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_data_bqr_59_), + .I1(com_tlm_u_tlm_rx_vc0_fifo_data_oqr_59_), + .I2(com_tlm_u_tlm_rx_vc0_fifo_select_bq_4161), + .I3(com_tlm_u_tlm_rx_vc0_fifo_select_oq_4160), + .LO(com_tlm_u_tlm_rx_vc0_fifo_N_44819_i_4177) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_N_44820_i.INIT = 16'hECA0; + LUT4_L com_tlm_u_tlm_rx_vc0_fifo_N_44820_i ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_data_bqr_58_), + .I1(com_tlm_u_tlm_rx_vc0_fifo_data_oqr_58_), + .I2(com_tlm_u_tlm_rx_vc0_fifo_select_bq_4161), + .I3(com_tlm_u_tlm_rx_vc0_fifo_select_oq_4160), + .LO(com_tlm_u_tlm_rx_vc0_fifo_N_44820_i_4178) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_N_44821_i.INIT = 16'hECA0; + LUT4_L com_tlm_u_tlm_rx_vc0_fifo_N_44821_i ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_data_bqr_57_), + .I1(com_tlm_u_tlm_rx_vc0_fifo_data_oqr_57_), + .I2(com_tlm_u_tlm_rx_vc0_fifo_select_bq_4161), + .I3(com_tlm_u_tlm_rx_vc0_fifo_select_oq_4160), + .LO(com_tlm_u_tlm_rx_vc0_fifo_N_44821_i_4179) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_N_44822_i.INIT = 16'hECA0; + LUT4_L com_tlm_u_tlm_rx_vc0_fifo_N_44822_i ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_data_bqr_56_), + .I1(com_tlm_u_tlm_rx_vc0_fifo_data_oqr_56_), + .I2(com_tlm_u_tlm_rx_vc0_fifo_select_bq_4161), + .I3(com_tlm_u_tlm_rx_vc0_fifo_select_oq_4160), + .LO(com_tlm_u_tlm_rx_vc0_fifo_N_44822_i_4180) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_N_44823_i.INIT = 16'hECA0; + LUT4_L com_tlm_u_tlm_rx_vc0_fifo_N_44823_i ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_data_bqr_55_), + .I1(com_tlm_u_tlm_rx_vc0_fifo_data_oqr_55_), + .I2(com_tlm_u_tlm_rx_vc0_fifo_select_bq_4161), + .I3(com_tlm_u_tlm_rx_vc0_fifo_select_oq_4160), + .LO(com_tlm_u_tlm_rx_vc0_fifo_N_44823_i_4181) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_N_44824_i.INIT = 16'hECA0; + LUT4_L com_tlm_u_tlm_rx_vc0_fifo_N_44824_i ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_data_bqr_54_), + .I1(com_tlm_u_tlm_rx_vc0_fifo_data_oqr_54_), + .I2(com_tlm_u_tlm_rx_vc0_fifo_select_bq_4161), + .I3(com_tlm_u_tlm_rx_vc0_fifo_select_oq_4160), + .LO(com_tlm_u_tlm_rx_vc0_fifo_N_44824_i_4182) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_N_44825_i.INIT = 16'hECA0; + LUT4_L com_tlm_u_tlm_rx_vc0_fifo_N_44825_i ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_data_bqr_53_), + .I1(com_tlm_u_tlm_rx_vc0_fifo_data_oqr_53_), + .I2(com_tlm_u_tlm_rx_vc0_fifo_select_bq_4161), + .I3(com_tlm_u_tlm_rx_vc0_fifo_select_oq_4160), + .LO(com_tlm_u_tlm_rx_vc0_fifo_N_44825_i_4183) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_N_44826_i.INIT = 16'hECA0; + LUT4_L com_tlm_u_tlm_rx_vc0_fifo_N_44826_i ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_data_bqr_52_), + .I1(com_tlm_u_tlm_rx_vc0_fifo_data_oqr_52_), + .I2(com_tlm_u_tlm_rx_vc0_fifo_select_bq_4161), + .I3(com_tlm_u_tlm_rx_vc0_fifo_select_oq_4160), + .LO(com_tlm_u_tlm_rx_vc0_fifo_N_44826_i_4184) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_N_44827_i.INIT = 16'hECA0; + LUT4_L com_tlm_u_tlm_rx_vc0_fifo_N_44827_i ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_data_bqr_51_), + .I1(com_tlm_u_tlm_rx_vc0_fifo_data_oqr_51_), + .I2(com_tlm_u_tlm_rx_vc0_fifo_select_bq_4161), + .I3(com_tlm_u_tlm_rx_vc0_fifo_select_oq_4160), + .LO(com_tlm_u_tlm_rx_vc0_fifo_N_44827_i_4185) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_N_44828_i.INIT = 16'hECA0; + LUT4_L com_tlm_u_tlm_rx_vc0_fifo_N_44828_i ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_data_bqr_50_), + .I1(com_tlm_u_tlm_rx_vc0_fifo_data_oqr_50_), + .I2(com_tlm_u_tlm_rx_vc0_fifo_select_bq_4161), + .I3(com_tlm_u_tlm_rx_vc0_fifo_select_oq_4160), + .LO(com_tlm_u_tlm_rx_vc0_fifo_N_44828_i_4186) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_N_44829_i.INIT = 16'hECA0; + LUT4_L com_tlm_u_tlm_rx_vc0_fifo_N_44829_i ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_data_bqr_49_), + .I1(com_tlm_u_tlm_rx_vc0_fifo_data_oqr_49_), + .I2(com_tlm_u_tlm_rx_vc0_fifo_select_bq_4161), + .I3(com_tlm_u_tlm_rx_vc0_fifo_select_oq_4160), + .LO(com_tlm_u_tlm_rx_vc0_fifo_N_44829_i_4187) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_N_44830_i.INIT = 16'hECA0; + LUT4_L com_tlm_u_tlm_rx_vc0_fifo_N_44830_i ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_data_bqr_48_), + .I1(com_tlm_u_tlm_rx_vc0_fifo_data_oqr_48_), + .I2(com_tlm_u_tlm_rx_vc0_fifo_select_bq_4161), + .I3(com_tlm_u_tlm_rx_vc0_fifo_select_oq_4160), + .LO(com_tlm_u_tlm_rx_vc0_fifo_N_44830_i_4188) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_N_44901_i.INIT = 16'hECA0; + LUT4_L com_tlm_u_tlm_rx_vc0_fifo_N_44901_i ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_data_bqr_47_), + .I1(com_tlm_u_tlm_rx_vc0_fifo_data_oqr_47_), + .I2(com_tlm_u_tlm_rx_vc0_fifo_select_bq_4161), + .I3(com_tlm_u_tlm_rx_vc0_fifo_select_oq_4160), + .LO(com_tlm_u_tlm_rx_vc0_fifo_N_44901_i_4189) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_N_44831_i.INIT = 16'hECA0; + LUT4_L com_tlm_u_tlm_rx_vc0_fifo_N_44831_i ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_data_bqr_45_), + .I1(com_tlm_u_tlm_rx_vc0_fifo_data_oqr_45_), + .I2(com_tlm_u_tlm_rx_vc0_fifo_select_bq_4161), + .I3(com_tlm_u_tlm_rx_vc0_fifo_select_oq_4160), + .LO(com_tlm_u_tlm_rx_vc0_fifo_N_44831_i_4191) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_N_44832_i.INIT = 16'hECA0; + LUT4_L com_tlm_u_tlm_rx_vc0_fifo_N_44832_i ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_data_bqr_44_), + .I1(com_tlm_u_tlm_rx_vc0_fifo_data_oqr_44_), + .I2(com_tlm_u_tlm_rx_vc0_fifo_select_bq_4161), + .I3(com_tlm_u_tlm_rx_vc0_fifo_select_oq_4160), + .LO(com_tlm_u_tlm_rx_vc0_fifo_N_44832_i_4192) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_N_44833_i.INIT = 16'hECA0; + LUT4_L com_tlm_u_tlm_rx_vc0_fifo_N_44833_i ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_data_bqr_43_), + .I1(com_tlm_u_tlm_rx_vc0_fifo_data_oqr_43_), + .I2(com_tlm_u_tlm_rx_vc0_fifo_select_bq_4161), + .I3(com_tlm_u_tlm_rx_vc0_fifo_select_oq_4160), + .LO(com_tlm_u_tlm_rx_vc0_fifo_N_44833_i_4193) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_N_44834_i.INIT = 16'hECA0; + LUT4_L com_tlm_u_tlm_rx_vc0_fifo_N_44834_i ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_data_bqr_42_), + .I1(com_tlm_u_tlm_rx_vc0_fifo_data_oqr_42_), + .I2(com_tlm_u_tlm_rx_vc0_fifo_select_bq_4161), + .I3(com_tlm_u_tlm_rx_vc0_fifo_select_oq_4160), + .LO(com_tlm_u_tlm_rx_vc0_fifo_N_44834_i_4194) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_N_44835_i.INIT = 16'hECA0; + LUT4_L com_tlm_u_tlm_rx_vc0_fifo_N_44835_i ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_data_bqr_41_), + .I1(com_tlm_u_tlm_rx_vc0_fifo_data_oqr_41_), + .I2(com_tlm_u_tlm_rx_vc0_fifo_select_bq_4161), + .I3(com_tlm_u_tlm_rx_vc0_fifo_select_oq_4160), + .LO(com_tlm_u_tlm_rx_vc0_fifo_N_44835_i_4195) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_N_44836_i.INIT = 16'hECA0; + LUT4_L com_tlm_u_tlm_rx_vc0_fifo_N_44836_i ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_data_bqr_40_), + .I1(com_tlm_u_tlm_rx_vc0_fifo_data_oqr_40_), + .I2(com_tlm_u_tlm_rx_vc0_fifo_select_bq_4161), + .I3(com_tlm_u_tlm_rx_vc0_fifo_select_oq_4160), + .LO(com_tlm_u_tlm_rx_vc0_fifo_N_44836_i_4196) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_N_44837_i.INIT = 16'hECA0; + LUT4_L com_tlm_u_tlm_rx_vc0_fifo_N_44837_i ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_data_bqr_39_), + .I1(com_tlm_u_tlm_rx_vc0_fifo_data_oqr_39_), + .I2(com_tlm_u_tlm_rx_vc0_fifo_select_bq_4161), + .I3(com_tlm_u_tlm_rx_vc0_fifo_select_oq_4160), + .LO(com_tlm_u_tlm_rx_vc0_fifo_N_44837_i_4197) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_N_44838_i.INIT = 16'hECA0; + LUT4_L com_tlm_u_tlm_rx_vc0_fifo_N_44838_i ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_data_bqr_38_), + .I1(com_tlm_u_tlm_rx_vc0_fifo_data_oqr_38_), + .I2(com_tlm_u_tlm_rx_vc0_fifo_select_bq_4161), + .I3(com_tlm_u_tlm_rx_vc0_fifo_select_oq_4160), + .LO(com_tlm_u_tlm_rx_vc0_fifo_N_44838_i_4198) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_N_44839_i.INIT = 16'hECA0; + LUT4_L com_tlm_u_tlm_rx_vc0_fifo_N_44839_i ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_data_bqr_37_), + .I1(com_tlm_u_tlm_rx_vc0_fifo_data_oqr_37_), + .I2(com_tlm_u_tlm_rx_vc0_fifo_select_bq_4161), + .I3(com_tlm_u_tlm_rx_vc0_fifo_select_oq_4160), + .LO(com_tlm_u_tlm_rx_vc0_fifo_N_44839_i_4199) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_N_44840_i.INIT = 16'hECA0; + LUT4_L com_tlm_u_tlm_rx_vc0_fifo_N_44840_i ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_data_bqr_36_), + .I1(com_tlm_u_tlm_rx_vc0_fifo_data_oqr_36_), + .I2(com_tlm_u_tlm_rx_vc0_fifo_select_bq_4161), + .I3(com_tlm_u_tlm_rx_vc0_fifo_select_oq_4160), + .LO(com_tlm_u_tlm_rx_vc0_fifo_N_44840_i_4200) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_N_44841_i.INIT = 16'hECA0; + LUT4_L com_tlm_u_tlm_rx_vc0_fifo_N_44841_i ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_data_bqr_35_), + .I1(com_tlm_u_tlm_rx_vc0_fifo_data_oqr_35_), + .I2(com_tlm_u_tlm_rx_vc0_fifo_select_bq_4161), + .I3(com_tlm_u_tlm_rx_vc0_fifo_select_oq_4160), + .LO(com_tlm_u_tlm_rx_vc0_fifo_N_44841_i_4201) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_N_44842_i.INIT = 16'hECA0; + LUT4_L com_tlm_u_tlm_rx_vc0_fifo_N_44842_i ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_data_bqr_34_), + .I1(com_tlm_u_tlm_rx_vc0_fifo_data_oqr_34_), + .I2(com_tlm_u_tlm_rx_vc0_fifo_select_bq_4161), + .I3(com_tlm_u_tlm_rx_vc0_fifo_select_oq_4160), + .LO(com_tlm_u_tlm_rx_vc0_fifo_N_44842_i_4202) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_N_44843_i.INIT = 16'hECA0; + LUT4_L com_tlm_u_tlm_rx_vc0_fifo_N_44843_i ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_data_bqr_33_), + .I1(com_tlm_u_tlm_rx_vc0_fifo_data_oqr_33_), + .I2(com_tlm_u_tlm_rx_vc0_fifo_select_bq_4161), + .I3(com_tlm_u_tlm_rx_vc0_fifo_select_oq_4160), + .LO(com_tlm_u_tlm_rx_vc0_fifo_N_44843_i_4203) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_N_44844_i.INIT = 16'hECA0; + LUT4_L com_tlm_u_tlm_rx_vc0_fifo_N_44844_i ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_data_bqr_32_), + .I1(com_tlm_u_tlm_rx_vc0_fifo_data_oqr_32_), + .I2(com_tlm_u_tlm_rx_vc0_fifo_select_bq_4161), + .I3(com_tlm_u_tlm_rx_vc0_fifo_select_oq_4160), + .LO(com_tlm_u_tlm_rx_vc0_fifo_N_44844_i_4204) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_N_44845_i.INIT = 16'hECA0; + LUT4_L com_tlm_u_tlm_rx_vc0_fifo_N_44845_i ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_data_bqr_31_), + .I1(com_tlm_u_tlm_rx_vc0_fifo_data_oqr_31_), + .I2(com_tlm_u_tlm_rx_vc0_fifo_select_bq_4161), + .I3(com_tlm_u_tlm_rx_vc0_fifo_select_oq_4160), + .LO(com_tlm_u_tlm_rx_vc0_fifo_N_44845_i_4205) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_N_44846_i.INIT = 16'hECA0; + LUT4_L com_tlm_u_tlm_rx_vc0_fifo_N_44846_i ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_data_bqr_30_), + .I1(com_tlm_u_tlm_rx_vc0_fifo_data_oqr_30_), + .I2(com_tlm_u_tlm_rx_vc0_fifo_select_bq_4161), + .I3(com_tlm_u_tlm_rx_vc0_fifo_select_oq_4160), + .LO(com_tlm_u_tlm_rx_vc0_fifo_N_44846_i_4206) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_N_44847_i.INIT = 16'hECA0; + LUT4_L com_tlm_u_tlm_rx_vc0_fifo_N_44847_i ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_data_bqr_29_), + .I1(com_tlm_u_tlm_rx_vc0_fifo_data_oqr_29_), + .I2(com_tlm_u_tlm_rx_vc0_fifo_select_bq_4161), + .I3(com_tlm_u_tlm_rx_vc0_fifo_select_oq_4160), + .LO(com_tlm_u_tlm_rx_vc0_fifo_N_44847_i_4207) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_N_44848_i.INIT = 16'hECA0; + LUT4_L com_tlm_u_tlm_rx_vc0_fifo_N_44848_i ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_data_bqr_28_), + .I1(com_tlm_u_tlm_rx_vc0_fifo_data_oqr_28_), + .I2(com_tlm_u_tlm_rx_vc0_fifo_select_bq_4161), + .I3(com_tlm_u_tlm_rx_vc0_fifo_select_oq_4160), + .LO(com_tlm_u_tlm_rx_vc0_fifo_N_44848_i_4208) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_N_44849_i.INIT = 16'hECA0; + LUT4_L com_tlm_u_tlm_rx_vc0_fifo_N_44849_i ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_data_bqr_27_), + .I1(com_tlm_u_tlm_rx_vc0_fifo_data_oqr_27_), + .I2(com_tlm_u_tlm_rx_vc0_fifo_select_bq_4161), + .I3(com_tlm_u_tlm_rx_vc0_fifo_select_oq_4160), + .LO(com_tlm_u_tlm_rx_vc0_fifo_N_44849_i_4209) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_N_44850_i.INIT = 16'hECA0; + LUT4_L com_tlm_u_tlm_rx_vc0_fifo_N_44850_i ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_data_bqr_26_), + .I1(com_tlm_u_tlm_rx_vc0_fifo_data_oqr_26_), + .I2(com_tlm_u_tlm_rx_vc0_fifo_select_bq_4161), + .I3(com_tlm_u_tlm_rx_vc0_fifo_select_oq_4160), + .LO(com_tlm_u_tlm_rx_vc0_fifo_N_44850_i_4210) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_N_44851_i.INIT = 16'hECA0; + LUT4_L com_tlm_u_tlm_rx_vc0_fifo_N_44851_i ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_data_bqr_25_), + .I1(com_tlm_u_tlm_rx_vc0_fifo_data_oqr_25_), + .I2(com_tlm_u_tlm_rx_vc0_fifo_select_bq_4161), + .I3(com_tlm_u_tlm_rx_vc0_fifo_select_oq_4160), + .LO(com_tlm_u_tlm_rx_vc0_fifo_N_44851_i_4211) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_N_44852_i.INIT = 16'hECA0; + LUT4_L com_tlm_u_tlm_rx_vc0_fifo_N_44852_i ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_data_bqr_24_), + .I1(com_tlm_u_tlm_rx_vc0_fifo_data_oqr_24_), + .I2(com_tlm_u_tlm_rx_vc0_fifo_select_bq_4161), + .I3(com_tlm_u_tlm_rx_vc0_fifo_select_oq_4160), + .LO(com_tlm_u_tlm_rx_vc0_fifo_N_44852_i_4212) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_N_44853_i.INIT = 16'hECA0; + LUT4_L com_tlm_u_tlm_rx_vc0_fifo_N_44853_i ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_data_bqr_23_), + .I1(com_tlm_u_tlm_rx_vc0_fifo_data_oqr_23_), + .I2(com_tlm_u_tlm_rx_vc0_fifo_select_bq_4161), + .I3(com_tlm_u_tlm_rx_vc0_fifo_select_oq_4160), + .LO(com_tlm_u_tlm_rx_vc0_fifo_N_44853_i_4213) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_N_44854_i.INIT = 16'hECA0; + LUT4_L com_tlm_u_tlm_rx_vc0_fifo_N_44854_i ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_data_bqr_22_), + .I1(com_tlm_u_tlm_rx_vc0_fifo_data_oqr_22_), + .I2(com_tlm_u_tlm_rx_vc0_fifo_select_bq_4161), + .I3(com_tlm_u_tlm_rx_vc0_fifo_select_oq_4160), + .LO(com_tlm_u_tlm_rx_vc0_fifo_N_44854_i_4214) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_N_44855_i.INIT = 16'hECA0; + LUT4_L com_tlm_u_tlm_rx_vc0_fifo_N_44855_i ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_data_bqr_21_), + .I1(com_tlm_u_tlm_rx_vc0_fifo_data_oqr_21_), + .I2(com_tlm_u_tlm_rx_vc0_fifo_select_bq_4161), + .I3(com_tlm_u_tlm_rx_vc0_fifo_select_oq_4160), + .LO(com_tlm_u_tlm_rx_vc0_fifo_N_44855_i_4215) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_N_44856_i.INIT = 16'hECA0; + LUT4_L com_tlm_u_tlm_rx_vc0_fifo_N_44856_i ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_data_bqr_20_), + .I1(com_tlm_u_tlm_rx_vc0_fifo_data_oqr_20_), + .I2(com_tlm_u_tlm_rx_vc0_fifo_select_bq_4161), + .I3(com_tlm_u_tlm_rx_vc0_fifo_select_oq_4160), + .LO(com_tlm_u_tlm_rx_vc0_fifo_N_44856_i_4216) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_N_44857_i.INIT = 16'hECA0; + LUT4_L com_tlm_u_tlm_rx_vc0_fifo_N_44857_i ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_data_bqr_19_), + .I1(com_tlm_u_tlm_rx_vc0_fifo_data_oqr_19_), + .I2(com_tlm_u_tlm_rx_vc0_fifo_select_bq_4161), + .I3(com_tlm_u_tlm_rx_vc0_fifo_select_oq_4160), + .LO(com_tlm_u_tlm_rx_vc0_fifo_N_44857_i_4217) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_N_44858_i.INIT = 16'hECA0; + LUT4_L com_tlm_u_tlm_rx_vc0_fifo_N_44858_i ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_data_bqr_18_), + .I1(com_tlm_u_tlm_rx_vc0_fifo_data_oqr_18_), + .I2(com_tlm_u_tlm_rx_vc0_fifo_select_bq_4161), + .I3(com_tlm_u_tlm_rx_vc0_fifo_select_oq_4160), + .LO(com_tlm_u_tlm_rx_vc0_fifo_N_44858_i_4218) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_N_44859_i.INIT = 16'hECA0; + LUT4_L com_tlm_u_tlm_rx_vc0_fifo_N_44859_i ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_data_bqr_17_), + .I1(com_tlm_u_tlm_rx_vc0_fifo_data_oqr_17_), + .I2(com_tlm_u_tlm_rx_vc0_fifo_select_bq_4161), + .I3(com_tlm_u_tlm_rx_vc0_fifo_select_oq_4160), + .LO(com_tlm_u_tlm_rx_vc0_fifo_N_44859_i_4219) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_N_44860_i.INIT = 16'hECA0; + LUT4_L com_tlm_u_tlm_rx_vc0_fifo_N_44860_i ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_data_bqr_16_), + .I1(com_tlm_u_tlm_rx_vc0_fifo_data_oqr_16_), + .I2(com_tlm_u_tlm_rx_vc0_fifo_select_bq_4161), + .I3(com_tlm_u_tlm_rx_vc0_fifo_select_oq_4160), + .LO(com_tlm_u_tlm_rx_vc0_fifo_N_44860_i_4220) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_N_44861_i.INIT = 16'hECA0; + LUT4_L com_tlm_u_tlm_rx_vc0_fifo_N_44861_i ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_data_bqr_15_), + .I1(com_tlm_u_tlm_rx_vc0_fifo_data_oqr_15_), + .I2(com_tlm_u_tlm_rx_vc0_fifo_select_bq_4161), + .I3(com_tlm_u_tlm_rx_vc0_fifo_select_oq_4160), + .LO(com_tlm_u_tlm_rx_vc0_fifo_N_44861_i_4221) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_N_44862_i.INIT = 16'hECA0; + LUT4_L com_tlm_u_tlm_rx_vc0_fifo_N_44862_i ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_data_bqr_14_), + .I1(com_tlm_u_tlm_rx_vc0_fifo_data_oqr_14_), + .I2(com_tlm_u_tlm_rx_vc0_fifo_select_bq_4161), + .I3(com_tlm_u_tlm_rx_vc0_fifo_select_oq_4160), + .LO(com_tlm_u_tlm_rx_vc0_fifo_N_44862_i_4222) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_N_44863_i.INIT = 16'hECA0; + LUT4_L com_tlm_u_tlm_rx_vc0_fifo_N_44863_i ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_data_bqr_13_), + .I1(com_tlm_u_tlm_rx_vc0_fifo_data_oqr_13_), + .I2(com_tlm_u_tlm_rx_vc0_fifo_select_bq_4161), + .I3(com_tlm_u_tlm_rx_vc0_fifo_select_oq_4160), + .LO(com_tlm_u_tlm_rx_vc0_fifo_N_44863_i_4223) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_N_44864_i.INIT = 16'hECA0; + LUT4_L com_tlm_u_tlm_rx_vc0_fifo_N_44864_i ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_data_bqr_12_), + .I1(com_tlm_u_tlm_rx_vc0_fifo_data_oqr_12_), + .I2(com_tlm_u_tlm_rx_vc0_fifo_select_bq_4161), + .I3(com_tlm_u_tlm_rx_vc0_fifo_select_oq_4160), + .LO(com_tlm_u_tlm_rx_vc0_fifo_N_44864_i_4224) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_N_44865_i.INIT = 16'hECA0; + LUT4_L com_tlm_u_tlm_rx_vc0_fifo_N_44865_i ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_data_bqr_11_), + .I1(com_tlm_u_tlm_rx_vc0_fifo_data_oqr_11_), + .I2(com_tlm_u_tlm_rx_vc0_fifo_select_bq_4161), + .I3(com_tlm_u_tlm_rx_vc0_fifo_select_oq_4160), + .LO(com_tlm_u_tlm_rx_vc0_fifo_N_44865_i_4225) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_N_44866_i.INIT = 16'hECA0; + LUT4_L com_tlm_u_tlm_rx_vc0_fifo_N_44866_i ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_data_bqr_10_), + .I1(com_tlm_u_tlm_rx_vc0_fifo_data_oqr_10_), + .I2(com_tlm_u_tlm_rx_vc0_fifo_select_bq_4161), + .I3(com_tlm_u_tlm_rx_vc0_fifo_select_oq_4160), + .LO(com_tlm_u_tlm_rx_vc0_fifo_N_44866_i_4226) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_N_44867_i.INIT = 16'hECA0; + LUT4_L com_tlm_u_tlm_rx_vc0_fifo_N_44867_i ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_data_bqr_9_), + .I1(com_tlm_u_tlm_rx_vc0_fifo_data_oqr_9_), + .I2(com_tlm_u_tlm_rx_vc0_fifo_select_bq_4161), + .I3(com_tlm_u_tlm_rx_vc0_fifo_select_oq_4160), + .LO(com_tlm_u_tlm_rx_vc0_fifo_N_44867_i_4227) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_N_44868_i.INIT = 16'hECA0; + LUT4_L com_tlm_u_tlm_rx_vc0_fifo_N_44868_i ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_data_bqr_8_), + .I1(com_tlm_u_tlm_rx_vc0_fifo_data_oqr_8_), + .I2(com_tlm_u_tlm_rx_vc0_fifo_select_bq_4161), + .I3(com_tlm_u_tlm_rx_vc0_fifo_select_oq_4160), + .LO(com_tlm_u_tlm_rx_vc0_fifo_N_44868_i_4228) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_N_44869_i.INIT = 16'hECA0; + LUT4_L com_tlm_u_tlm_rx_vc0_fifo_N_44869_i ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_data_bqr_7_), + .I1(com_tlm_u_tlm_rx_vc0_fifo_data_oqr_7_), + .I2(com_tlm_u_tlm_rx_vc0_fifo_select_bq_4161), + .I3(com_tlm_u_tlm_rx_vc0_fifo_select_oq_4160), + .LO(com_tlm_u_tlm_rx_vc0_fifo_N_44869_i_4229) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_N_44870_i.INIT = 16'hECA0; + LUT4_L com_tlm_u_tlm_rx_vc0_fifo_N_44870_i ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_data_bqr_6_), + .I1(com_tlm_u_tlm_rx_vc0_fifo_data_oqr_6_), + .I2(com_tlm_u_tlm_rx_vc0_fifo_select_bq_4161), + .I3(com_tlm_u_tlm_rx_vc0_fifo_select_oq_4160), + .LO(com_tlm_u_tlm_rx_vc0_fifo_N_44870_i_4230) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_N_44871_i.INIT = 16'hECA0; + LUT4_L com_tlm_u_tlm_rx_vc0_fifo_N_44871_i ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_data_bqr_5_), + .I1(com_tlm_u_tlm_rx_vc0_fifo_data_oqr_5_), + .I2(com_tlm_u_tlm_rx_vc0_fifo_select_bq_4161), + .I3(com_tlm_u_tlm_rx_vc0_fifo_select_oq_4160), + .LO(com_tlm_u_tlm_rx_vc0_fifo_N_44871_i_4231) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_N_44872_i.INIT = 16'hECA0; + LUT4_L com_tlm_u_tlm_rx_vc0_fifo_N_44872_i ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_data_bqr_4_), + .I1(com_tlm_u_tlm_rx_vc0_fifo_data_oqr_4_), + .I2(com_tlm_u_tlm_rx_vc0_fifo_select_bq_4161), + .I3(com_tlm_u_tlm_rx_vc0_fifo_select_oq_4160), + .LO(com_tlm_u_tlm_rx_vc0_fifo_N_44872_i_4232) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_N_44873_i.INIT = 16'hECA0; + LUT4_L com_tlm_u_tlm_rx_vc0_fifo_N_44873_i ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_data_bqr_3_), + .I1(com_tlm_u_tlm_rx_vc0_fifo_data_oqr_3_), + .I2(com_tlm_u_tlm_rx_vc0_fifo_select_bq_4161), + .I3(com_tlm_u_tlm_rx_vc0_fifo_select_oq_4160), + .LO(com_tlm_u_tlm_rx_vc0_fifo_N_44873_i_4233) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_N_44874_i.INIT = 16'hECA0; + LUT4_L com_tlm_u_tlm_rx_vc0_fifo_N_44874_i ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_data_bqr_2_), + .I1(com_tlm_u_tlm_rx_vc0_fifo_data_oqr_2_), + .I2(com_tlm_u_tlm_rx_vc0_fifo_select_bq_4161), + .I3(com_tlm_u_tlm_rx_vc0_fifo_select_oq_4160), + .LO(com_tlm_u_tlm_rx_vc0_fifo_N_44874_i_4234) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_N_44875_i.INIT = 16'hECA0; + LUT4_L com_tlm_u_tlm_rx_vc0_fifo_N_44875_i ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_data_bqr_1_), + .I1(com_tlm_u_tlm_rx_vc0_fifo_data_oqr_1_), + .I2(com_tlm_u_tlm_rx_vc0_fifo_select_bq_4161), + .I3(com_tlm_u_tlm_rx_vc0_fifo_select_oq_4160), + .LO(com_tlm_u_tlm_rx_vc0_fifo_N_44875_i_4235) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_N_44876_i.INIT = 16'hECA0; + LUT4_L com_tlm_u_tlm_rx_vc0_fifo_N_44876_i ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_data_bqr_0_), + .I1(com_tlm_u_tlm_rx_vc0_fifo_data_oqr_0_), + .I2(com_tlm_u_tlm_rx_vc0_fifo_select_bq_4161), + .I3(com_tlm_u_tlm_rx_vc0_fifo_select_oq_4160), + .LO(com_tlm_u_tlm_rx_vc0_fifo_N_44876_i_4236) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_select_oq2bq_d_5.INIT = 8'h20; + LUT3_L com_tlm_u_tlm_rx_vc0_fifo_select_oq2bq_d_5 ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_np_oqr), + .I1(com_tlm_u_tlm_rx_vc0_fifo_select_oq2bq_d_4163), + .I2(com_tlm_u_tlm_rx_vc0_fifo_un1_data_oqr[0]), + .LO(com_tlm_u_tlm_rx_vc0_fifo_select_oq2bq_d_5_4162) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_select_bq17.INIT = 4'h4; + LUT2_L com_tlm_u_tlm_rx_vc0_fifo_select_bq17 ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_adv_pkt_bq_4165), + .I1(com_tlm_u_tlm_rx_vc0_fifo_un1_adv_pkt_oq_4166), + .LO(com_tlm_u_tlm_rx_vc0_fifo_select_bq17_4164) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_select_cfg_7_u_0.INIT = 16'hB888; + LUT4_L com_tlm_u_tlm_rx_vc0_fifo_select_cfg_7_u_0 ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_N_44111), + .I1(com_tlm_u_tlm_rx_vc0_fifo_adv_pkt_bq_4165), + .I2(com_tlm_u_tlm_rx_vc0_fifo_cfg_oqr), + .I3(com_tlm_u_tlm_rx_vc0_fifo_un1_adv_pkt_oq_4166), + .LO(com_tlm_u_tlm_rx_vc0_fifo_select_cfg_7) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_select_usr_7_u_0.INIT = 16'h4744; + LUT4_L com_tlm_u_tlm_rx_vc0_fifo_select_usr_7_u_0 ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_N_44111), + .I1(com_tlm_u_tlm_rx_vc0_fifo_adv_pkt_bq_4165), + .I2(com_tlm_u_tlm_rx_vc0_fifo_cfg_oqr), + .I3(com_tlm_u_tlm_rx_vc0_fifo_un1_adv_pkt_oq_4166), + .LO(com_tlm_u_tlm_rx_vc0_fifo_select_usr_7) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_un1_adv_pkt_oq_1_0.INIT = 16'h0A2A; + LUT4 com_tlm_u_tlm_rx_vc0_fifo_un1_adv_pkt_oq_1_0 ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_aux_vld_oqr), + .I1(com_tlm_u_tlm_rx_vc0_fifo_data_vld_bqr), + .I2(com_tlm_u_tlm_rx_vc0_fifo_np_oqr), + .I3(com_tlm_u_tlm_rx_vc0_fifo_nxt_vld_bqr), + .O(com_tlm_u_tlm_rx_vc0_fifo_un1_adv_pkt_oq_1_0_4167) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_un1_adv_pkt_oq.INIT = 16'h8000; + LUT4 com_tlm_u_tlm_rx_vc0_fifo_un1_adv_pkt_oq ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_data_vld_oqr), + .I1(com_tlm_u_tlm_rx_vc0_fifo_un1_adv_pkt_oq_1_0_4167), + .I2(com_tlm_u_tlm_rx_vc0_fifo_un1_select_oq2bq_d_1_4238), + .I3(com_tlm_u_tlm_rx_vc0_fifo_un4_adv_pkt_oq), + .O(com_tlm_u_tlm_rx_vc0_fifo_un1_adv_pkt_oq_4166) + ); + FDRE com_tlm_u_tlm_rx_vc0_fifo_select_oq2bq_1 ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_un1_select_oq2bq_d_1_i_4237), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_select_oq2bq_5), + .Q(com_tlm_u_tlm_rx_vc0_fifo_select_oq2bq_1_4168), + .R(plm_link_up_i) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_wen_aux_bq_0_o3.INIT = 8'h80; + LUT3 com_tlm_u_tlm_rx_vc0_fifo_wen_aux_bq_0_o3 ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_select_oq2bq_4169), + .I1(com_tlm_u_tlm_rx_vc0_fifo_ram_dout[64]), + .I2(com_tlm_u_tlm_rx_vc0_fifo_data_vld_oqr), + .O(com_tlm_u_tlm_rx_vc0_fifo_N_44215_i) + ); + FD com_tlm_u_tlm_rx_vc0_fifo_reset_i_q ( + .C(NlwRenamedSig_OI_trn_clk), + .D(plm_link_up_0), + .Q(com_reset_i_q) + ); + FD com_tlm_u_tlm_rx_vc0_fifo_aux_in_8_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_aux_i_d[8]), + .Q(com_tlm_u_tlm_rx_vc0_fifo_aux_in[8]) + ); + FD com_tlm_u_tlm_rx_vc0_fifo_aux_in_7_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_aux_i_d[7]), + .Q(com_tlm_u_tlm_rx_vc0_fifo_aux_in[7]) + ); + FD com_tlm_u_tlm_rx_vc0_fifo_aux_in_6_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_aux_i_d[6]), + .Q(com_tlm_u_tlm_rx_vc0_fifo_aux_in[6]) + ); + FD com_tlm_u_tlm_rx_vc0_fifo_aux_in_5_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_aux_i_d[5]), + .Q(com_tlm_u_tlm_rx_vc0_fifo_aux_in[5]) + ); + FD com_tlm_u_tlm_rx_vc0_fifo_aux_in_4_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_aux_i_d[4]), + .Q(com_tlm_u_tlm_rx_vc0_fifo_aux_in[4]) + ); + FD com_tlm_u_tlm_rx_vc0_fifo_aux_in_3_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_aux_i_d[3]), + .Q(com_tlm_u_tlm_rx_vc0_fifo_aux_in[3]) + ); + FD com_tlm_u_tlm_rx_vc0_fifo_aux_in_2_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_aux_i_d[2]), + .Q(com_tlm_u_tlm_rx_vc0_fifo_aux_in[2]) + ); + FD com_tlm_u_tlm_rx_vc0_fifo_aux_in_1_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_aux_i_d[1]), + .Q(com_tlm_u_tlm_rx_vc0_fifo_aux_in[1]) + ); + FD com_tlm_u_tlm_rx_vc0_fifo_aux_in_0_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_aux_i_d[0]), + .Q(com_tlm_u_tlm_rx_vc0_fifo_aux_in[0]) + ); + FDE com_tlm_u_tlm_rx_vc0_fifo_aux_i_d_6_ ( + .CE(com_tlm_u_tlm_rx_ds_bar_src_rdy), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_ds_bar[6]), + .Q(com_tlm_u_tlm_rx_vc0_fifo_aux_i_d[6]) + ); + FDE com_tlm_u_tlm_rx_vc0_fifo_aux_i_d_5_ ( + .CE(com_tlm_u_tlm_rx_ds_bar_src_rdy), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_ds_bar[5]), + .Q(com_tlm_u_tlm_rx_vc0_fifo_aux_i_d[5]) + ); + FDE com_tlm_u_tlm_rx_vc0_fifo_aux_i_d_4_ ( + .CE(com_tlm_u_tlm_rx_ds_bar_src_rdy), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_ds_bar[4]), + .Q(com_tlm_u_tlm_rx_vc0_fifo_aux_i_d[4]) + ); + FDE com_tlm_u_tlm_rx_vc0_fifo_aux_i_d_3_ ( + .CE(com_tlm_u_tlm_rx_ds_bar_src_rdy), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_ds_bar[3]), + .Q(com_tlm_u_tlm_rx_vc0_fifo_aux_i_d[3]) + ); + FDE com_tlm_u_tlm_rx_vc0_fifo_aux_i_d_2_ ( + .CE(com_tlm_u_tlm_rx_ds_bar_src_rdy), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_ds_bar[2]), + .Q(com_tlm_u_tlm_rx_vc0_fifo_aux_i_d[2]) + ); + FDE com_tlm_u_tlm_rx_vc0_fifo_aux_i_d_1_ ( + .CE(com_tlm_u_tlm_rx_ds_bar_src_rdy), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_ds_bar[1]), + .Q(com_tlm_u_tlm_rx_vc0_fifo_aux_i_d[1]) + ); + FDE com_tlm_u_tlm_rx_vc0_fifo_aux_i_d_0_ ( + .CE(com_tlm_u_tlm_rx_ds_bar_src_rdy), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_ds_bar[0]), + .Q(com_tlm_u_tlm_rx_vc0_fifo_aux_i_d[0]) + ); + FDE com_tlm_u_tlm_rx_vc0_fifo_aux_i_d_8_ ( + .CE(com_tlm_u_tlm_rx_ds_sof), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_ds_np), + .Q(com_tlm_u_tlm_rx_vc0_fifo_aux_i_d[8]) + ); + FDE com_tlm_u_tlm_rx_vc0_fifo_aux_i_d_7_ ( + .CE(com_tlm_u_tlm_rx_ds_sof), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_ds_cfg), + .Q(com_tlm_u_tlm_rx_vc0_fifo_aux_i_d[7]) + ); + FDE com_tlm_u_tlm_rx_vc0_fifo_rem_d ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_N_10675_i_i_i_4239), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_N_10673_i), + .Q(com_tlm_u_tlm_rx_vc0_trn_rrem) + ); + FDE com_tlm_u_tlm_rx_vc0_fifo_bar_d_6_ ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_N_86703_i_4171), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_N_10460_i), + .Q(com_tlm_u_tlm_rx_vc0_fifo_trn_rbar_hit[6]) + ); + FDE com_tlm_u_tlm_rx_vc0_fifo_bar_d_5_ ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_N_86703_i_4171), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_N_10461_i), + .Q(com_tlm_u_tlm_rx_vc0_fifo_trn_rbar_hit[5]) + ); + FDE com_tlm_u_tlm_rx_vc0_fifo_bar_d_4_ ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_N_86703_i_4171), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_N_10462_i), + .Q(com_tlm_u_tlm_rx_vc0_fifo_trn_rbar_hit[4]) + ); + FDE com_tlm_u_tlm_rx_vc0_fifo_bar_d_3_ ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_N_86703_i_4171), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_N_10463_i), + .Q(com_tlm_u_tlm_rx_vc0_fifo_trn_rbar_hit[3]) + ); + FDE com_tlm_u_tlm_rx_vc0_fifo_bar_d_2_ ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_N_86703_i_4171), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_N_10464_i), + .Q(com_tlm_u_tlm_rx_vc0_fifo_trn_rbar_hit[2]) + ); + FDE com_tlm_u_tlm_rx_vc0_fifo_bar_d_1_ ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_N_86703_i_4171), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_N_10465_i), + .Q(com_tlm_u_tlm_rx_vc0_fifo_trn_rbar_hit[1]) + ); + FDE com_tlm_u_tlm_rx_vc0_fifo_bar_d_0_ ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_N_86703_i_4171), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_N_10466_i), + .Q(com_tlm_u_tlm_rx_vc0_fifo_trn_rbar_hit[0]) + ); + FDE com_tlm_u_tlm_rx_vc0_fifo_cpl_d ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_N_86703_i_4171), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_un8_cpl_d_0_a2_4170), + .Q(com_tlm_u_tlm_rx_vc0_fifo_cpl) + ); + FDE com_tlm_u_tlm_rx_vc0_fifo_ep_d ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_N_86703_i_4171), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_N_44895_i_4190), + .Q(com_tlm_u_tlm_rx_vc0_fifo_trn_rerrfwd) + ); + FDE com_tlm_u_tlm_rx_vc0_fifo_np_d ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_N_86703_i_4171), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_N_44896_i_4172), + .Q(com_tlm_u_tlm_rx_vc0_fifo_np) + ); + FDE com_tlm_u_tlm_rx_vc0_fifo_d_d_63_ ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_N_10675_i_i_i_4239), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_N_44815_i_4173), + .Q(NlwRenamedSig_OI_trn_rd[63]) + ); + FDE com_tlm_u_tlm_rx_vc0_fifo_d_d_62_ ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_N_10675_i_i_i_4239), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_N_44816_i_4174), + .Q(NlwRenamedSig_OI_trn_rd[62]) + ); + FDE com_tlm_u_tlm_rx_vc0_fifo_d_d_61_ ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_N_10675_i_i_i_4239), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_N_44817_i_4175), + .Q(NlwRenamedSig_OI_trn_rd[61]) + ); + FDE com_tlm_u_tlm_rx_vc0_fifo_d_d_60_ ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_N_10675_i_i_i_4239), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_N_44818_i_4176), + .Q(NlwRenamedSig_OI_trn_rd[60]) + ); + FDE com_tlm_u_tlm_rx_vc0_fifo_d_d_59_ ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_N_10675_i_i_i_4239), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_N_44819_i_4177), + .Q(NlwRenamedSig_OI_trn_rd[59]) + ); + FDE com_tlm_u_tlm_rx_vc0_fifo_d_d_58_ ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_N_10675_i_i_i_4239), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_N_44820_i_4178), + .Q(NlwRenamedSig_OI_trn_rd[58]) + ); + FDE com_tlm_u_tlm_rx_vc0_fifo_d_d_57_ ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_N_10675_i_i_i_4239), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_N_44821_i_4179), + .Q(NlwRenamedSig_OI_trn_rd[57]) + ); + FDE com_tlm_u_tlm_rx_vc0_fifo_d_d_56_ ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_N_10675_i_i_i_4239), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_N_44822_i_4180), + .Q(NlwRenamedSig_OI_trn_rd[56]) + ); + FDE com_tlm_u_tlm_rx_vc0_fifo_d_d_55_ ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_N_10675_i_i_i_4239), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_N_44823_i_4181), + .Q(NlwRenamedSig_OI_trn_rd[55]) + ); + FDE com_tlm_u_tlm_rx_vc0_fifo_d_d_54_ ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_N_10675_i_i_i_4239), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_N_44824_i_4182), + .Q(NlwRenamedSig_OI_trn_rd[54]) + ); + FDE com_tlm_u_tlm_rx_vc0_fifo_d_d_53_ ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_N_10675_i_i_i_4239), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_N_44825_i_4183), + .Q(NlwRenamedSig_OI_trn_rd[53]) + ); + FDE com_tlm_u_tlm_rx_vc0_fifo_d_d_52_ ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_N_10675_i_i_i_4239), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_N_44826_i_4184), + .Q(NlwRenamedSig_OI_trn_rd[52]) + ); + FDE com_tlm_u_tlm_rx_vc0_fifo_d_d_51_ ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_N_10675_i_i_i_4239), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_N_44827_i_4185), + .Q(NlwRenamedSig_OI_trn_rd[51]) + ); + FDE com_tlm_u_tlm_rx_vc0_fifo_d_d_50_ ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_N_10675_i_i_i_4239), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_N_44828_i_4186), + .Q(NlwRenamedSig_OI_trn_rd[50]) + ); + FDE com_tlm_u_tlm_rx_vc0_fifo_d_d_49_ ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_N_10675_i_i_i_4239), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_N_44829_i_4187), + .Q(NlwRenamedSig_OI_trn_rd[49]) + ); + FDE com_tlm_u_tlm_rx_vc0_fifo_d_d_48_ ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_N_10675_i_i_i_4239), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_N_44830_i_4188), + .Q(NlwRenamedSig_OI_trn_rd[48]) + ); + FDE com_tlm_u_tlm_rx_vc0_fifo_d_d_47_ ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_N_10675_i_i_i_4239), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_N_44901_i_4189), + .Q(NlwRenamedSig_OI_trn_rd[47]) + ); + FDE com_tlm_u_tlm_rx_vc0_fifo_d_d_46_ ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_N_10675_i_i_i_4239), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_N_44895_i_4190), + .Q(NlwRenamedSig_OI_trn_rd[46]) + ); + FDE com_tlm_u_tlm_rx_vc0_fifo_d_d_45_ ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_N_10675_i_i_i_4239), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_N_44831_i_4191), + .Q(NlwRenamedSig_OI_trn_rd[45]) + ); + FDE com_tlm_u_tlm_rx_vc0_fifo_d_d_44_ ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_N_10675_i_i_i_4239), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_N_44832_i_4192), + .Q(NlwRenamedSig_OI_trn_rd[44]) + ); + FDE com_tlm_u_tlm_rx_vc0_fifo_d_d_43_ ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_N_10675_i_i_i_4239), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_N_44833_i_4193), + .Q(NlwRenamedSig_OI_trn_rd[43]) + ); + FDE com_tlm_u_tlm_rx_vc0_fifo_d_d_42_ ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_N_10675_i_i_i_4239), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_N_44834_i_4194), + .Q(NlwRenamedSig_OI_trn_rd[42]) + ); + FDE com_tlm_u_tlm_rx_vc0_fifo_d_d_41_ ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_N_10675_i_i_i_4239), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_N_44835_i_4195), + .Q(NlwRenamedSig_OI_trn_rd[41]) + ); + FDE com_tlm_u_tlm_rx_vc0_fifo_d_d_40_ ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_N_10675_i_i_i_4239), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_N_44836_i_4196), + .Q(NlwRenamedSig_OI_trn_rd[40]) + ); + FDE com_tlm_u_tlm_rx_vc0_fifo_d_d_39_ ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_N_10675_i_i_i_4239), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_N_44837_i_4197), + .Q(NlwRenamedSig_OI_trn_rd[39]) + ); + FDE com_tlm_u_tlm_rx_vc0_fifo_d_d_38_ ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_N_10675_i_i_i_4239), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_N_44838_i_4198), + .Q(NlwRenamedSig_OI_trn_rd[38]) + ); + FDE com_tlm_u_tlm_rx_vc0_fifo_d_d_37_ ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_N_10675_i_i_i_4239), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_N_44839_i_4199), + .Q(NlwRenamedSig_OI_trn_rd[37]) + ); + FDE com_tlm_u_tlm_rx_vc0_fifo_d_d_36_ ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_N_10675_i_i_i_4239), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_N_44840_i_4200), + .Q(NlwRenamedSig_OI_trn_rd[36]) + ); + FDE com_tlm_u_tlm_rx_vc0_fifo_d_d_35_ ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_N_10675_i_i_i_4239), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_N_44841_i_4201), + .Q(NlwRenamedSig_OI_trn_rd[35]) + ); + FDE com_tlm_u_tlm_rx_vc0_fifo_d_d_34_ ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_N_10675_i_i_i_4239), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_N_44842_i_4202), + .Q(NlwRenamedSig_OI_trn_rd[34]) + ); + FDE com_tlm_u_tlm_rx_vc0_fifo_d_d_33_ ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_N_10675_i_i_i_4239), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_N_44843_i_4203), + .Q(NlwRenamedSig_OI_trn_rd[33]) + ); + FDE com_tlm_u_tlm_rx_vc0_fifo_d_d_32_ ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_N_10675_i_i_i_4239), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_N_44844_i_4204), + .Q(NlwRenamedSig_OI_trn_rd[32]) + ); + FDE com_tlm_u_tlm_rx_vc0_fifo_d_d_31_ ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_N_10675_i_i_i_4239), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_N_44845_i_4205), + .Q(NlwRenamedSig_OI_trn_rd[31]) + ); + FDE com_tlm_u_tlm_rx_vc0_fifo_d_d_30_ ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_N_10675_i_i_i_4239), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_N_44846_i_4206), + .Q(NlwRenamedSig_OI_trn_rd[30]) + ); + FDE com_tlm_u_tlm_rx_vc0_fifo_d_d_29_ ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_N_10675_i_i_i_4239), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_N_44847_i_4207), + .Q(NlwRenamedSig_OI_trn_rd[29]) + ); + FDE com_tlm_u_tlm_rx_vc0_fifo_d_d_28_ ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_N_10675_i_i_i_4239), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_N_44848_i_4208), + .Q(NlwRenamedSig_OI_trn_rd[28]) + ); + FDE com_tlm_u_tlm_rx_vc0_fifo_d_d_27_ ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_N_10675_i_i_i_4239), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_N_44849_i_4209), + .Q(NlwRenamedSig_OI_trn_rd[27]) + ); + FDE com_tlm_u_tlm_rx_vc0_fifo_d_d_26_ ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_N_10675_i_i_i_4239), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_N_44850_i_4210), + .Q(NlwRenamedSig_OI_trn_rd[26]) + ); + FDE com_tlm_u_tlm_rx_vc0_fifo_d_d_25_ ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_N_10675_i_i_i_4239), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_N_44851_i_4211), + .Q(NlwRenamedSig_OI_trn_rd[25]) + ); + FDE com_tlm_u_tlm_rx_vc0_fifo_d_d_24_ ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_N_10675_i_i_i_4239), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_N_44852_i_4212), + .Q(NlwRenamedSig_OI_trn_rd[24]) + ); + FDE com_tlm_u_tlm_rx_vc0_fifo_d_d_23_ ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_N_10675_i_i_i_4239), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_N_44853_i_4213), + .Q(NlwRenamedSig_OI_trn_rd[23]) + ); + FDE com_tlm_u_tlm_rx_vc0_fifo_d_d_22_ ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_N_10675_i_i_i_4239), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_N_44854_i_4214), + .Q(NlwRenamedSig_OI_trn_rd[22]) + ); + FDE com_tlm_u_tlm_rx_vc0_fifo_d_d_21_ ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_N_10675_i_i_i_4239), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_N_44855_i_4215), + .Q(NlwRenamedSig_OI_trn_rd[21]) + ); + FDE com_tlm_u_tlm_rx_vc0_fifo_d_d_20_ ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_N_10675_i_i_i_4239), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_N_44856_i_4216), + .Q(NlwRenamedSig_OI_trn_rd[20]) + ); + FDE com_tlm_u_tlm_rx_vc0_fifo_d_d_19_ ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_N_10675_i_i_i_4239), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_N_44857_i_4217), + .Q(NlwRenamedSig_OI_trn_rd[19]) + ); + FDE com_tlm_u_tlm_rx_vc0_fifo_d_d_18_ ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_N_10675_i_i_i_4239), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_N_44858_i_4218), + .Q(NlwRenamedSig_OI_trn_rd[18]) + ); + FDE com_tlm_u_tlm_rx_vc0_fifo_d_d_17_ ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_N_10675_i_i_i_4239), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_N_44859_i_4219), + .Q(NlwRenamedSig_OI_trn_rd[17]) + ); + FDE com_tlm_u_tlm_rx_vc0_fifo_d_d_16_ ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_N_10675_i_i_i_4239), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_N_44860_i_4220), + .Q(NlwRenamedSig_OI_trn_rd[16]) + ); + FDE com_tlm_u_tlm_rx_vc0_fifo_d_d_15_ ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_N_10675_i_i_i_4239), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_N_44861_i_4221), + .Q(NlwRenamedSig_OI_trn_rd[15]) + ); + FDE com_tlm_u_tlm_rx_vc0_fifo_d_d_14_ ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_N_10675_i_i_i_4239), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_N_44862_i_4222), + .Q(NlwRenamedSig_OI_trn_rd[14]) + ); + FDE com_tlm_u_tlm_rx_vc0_fifo_d_d_13_ ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_N_10675_i_i_i_4239), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_N_44863_i_4223), + .Q(NlwRenamedSig_OI_trn_rd[13]) + ); + FDE com_tlm_u_tlm_rx_vc0_fifo_d_d_12_ ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_N_10675_i_i_i_4239), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_N_44864_i_4224), + .Q(NlwRenamedSig_OI_trn_rd[12]) + ); + FDE com_tlm_u_tlm_rx_vc0_fifo_d_d_11_ ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_N_10675_i_i_i_4239), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_N_44865_i_4225), + .Q(NlwRenamedSig_OI_trn_rd[11]) + ); + FDE com_tlm_u_tlm_rx_vc0_fifo_d_d_10_ ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_N_10675_i_i_i_4239), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_N_44866_i_4226), + .Q(NlwRenamedSig_OI_trn_rd[10]) + ); + FDE com_tlm_u_tlm_rx_vc0_fifo_d_d_9_ ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_N_10675_i_i_i_4239), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_N_44867_i_4227), + .Q(NlwRenamedSig_OI_trn_rd[9]) + ); + FDE com_tlm_u_tlm_rx_vc0_fifo_d_d_8_ ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_N_10675_i_i_i_4239), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_N_44868_i_4228), + .Q(NlwRenamedSig_OI_trn_rd[8]) + ); + FDE com_tlm_u_tlm_rx_vc0_fifo_d_d_7_ ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_N_10675_i_i_i_4239), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_N_44869_i_4229), + .Q(NlwRenamedSig_OI_trn_rd[7]) + ); + FDE com_tlm_u_tlm_rx_vc0_fifo_d_d_6_ ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_N_10675_i_i_i_4239), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_N_44870_i_4230), + .Q(NlwRenamedSig_OI_trn_rd[6]) + ); + FDE com_tlm_u_tlm_rx_vc0_fifo_d_d_5_ ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_N_10675_i_i_i_4239), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_N_44871_i_4231), + .Q(NlwRenamedSig_OI_trn_rd[5]) + ); + FDE com_tlm_u_tlm_rx_vc0_fifo_d_d_4_ ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_N_10675_i_i_i_4239), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_N_44872_i_4232), + .Q(NlwRenamedSig_OI_trn_rd[4]) + ); + FDE com_tlm_u_tlm_rx_vc0_fifo_d_d_3_ ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_N_10675_i_i_i_4239), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_N_44873_i_4233), + .Q(NlwRenamedSig_OI_trn_rd[3]) + ); + FDE com_tlm_u_tlm_rx_vc0_fifo_d_d_2_ ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_N_10675_i_i_i_4239), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_N_44874_i_4234), + .Q(NlwRenamedSig_OI_trn_rd[2]) + ); + FDE com_tlm_u_tlm_rx_vc0_fifo_d_d_1_ ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_N_10675_i_i_i_4239), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_N_44875_i_4235), + .Q(NlwRenamedSig_OI_trn_rd[1]) + ); + FDE com_tlm_u_tlm_rx_vc0_fifo_d_d_0_ ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_N_10675_i_i_i_4239), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_N_44876_i_4236), + .Q(NlwRenamedSig_OI_trn_rd[0]) + ); + INV com_tlm_u_tlm_rx_vc0_fifo_trn_rbar_hit_i_0_ ( + .I(com_tlm_u_tlm_rx_vc0_fifo_trn_rbar_hit[0]), + .O(trn_rbar_hit_n_6089[0]) + ); + INV com_tlm_u_tlm_rx_vc0_fifo_trn_rbar_hit_i_1_ ( + .I(com_tlm_u_tlm_rx_vc0_fifo_trn_rbar_hit[1]), + .O(trn_rbar_hit_n_6089[1]) + ); + INV com_tlm_u_tlm_rx_vc0_fifo_trn_rbar_hit_i_2_ ( + .I(com_tlm_u_tlm_rx_vc0_fifo_trn_rbar_hit[2]), + .O(trn_rbar_hit_n_6089[2]) + ); + INV com_tlm_u_tlm_rx_vc0_fifo_trn_rbar_hit_i_3_ ( + .I(com_tlm_u_tlm_rx_vc0_fifo_trn_rbar_hit[3]), + .O(trn_rbar_hit_n_6089[3]) + ); + INV com_tlm_u_tlm_rx_vc0_fifo_trn_rbar_hit_i_4_ ( + .I(com_tlm_u_tlm_rx_vc0_fifo_trn_rbar_hit[4]), + .O(trn_rbar_hit_n_6089[4]) + ); + INV com_tlm_u_tlm_rx_vc0_fifo_trn_rbar_hit_i_5_ ( + .I(com_tlm_u_tlm_rx_vc0_fifo_trn_rbar_hit[5]), + .O(trn_rbar_hit_n_6089[5]) + ); + INV com_tlm_u_tlm_rx_vc0_fifo_trn_rbar_hit_i_6_ ( + .I(com_tlm_u_tlm_rx_vc0_fifo_trn_rbar_hit[6]), + .O(trn_rbar_hit_n_6089[6]) + ); + INV com_tlm_u_tlm_rx_vc0_fifo_trn_rerrfwd_i ( + .I(com_tlm_u_tlm_rx_vc0_fifo_trn_rerrfwd), + .O(trn_rerrfwd_n) + ); + INV com_tlm_u_tlm_rx_vc0_fifo_trn_rsrc_dsc_i ( + .I(com_tlm_u_tlm_rx_vc0_fifo_trn_rsrc_dsc), + .O(trn_rsrc_dsc_n) + ); + INV com_tlm_u_tlm_rx_vc0_fifo_trn_rsrc_rdy_i ( + .I(com_tlm_u_tlm_rx_vc0_trn_rsrc_rdy), + .O(trn_rsrc_rdy_n) + ); + INV com_tlm_u_tlm_rx_vc0_fifo_trn_reof_i ( + .I(com_tlm_u_tlm_rx_vc0_trn_reof), + .O(trn_reof_n) + ); + INV com_tlm_u_tlm_rx_vc0_fifo_trn_rsof_i ( + .I(com_tlm_u_tlm_rx_vc0_trn_rsof), + .O(trn_rsof_n) + ); + INV com_tlm_u_tlm_rx_vc0_fifo_trn_rrem_i ( + .I(com_tlm_u_tlm_rx_vc0_trn_rrem), + .O(NlwRenamedSignal_trn_rrem_n[3]) + ); + INV com_tlm_u_tlm_rx_vc0_fifo_un1_select_oq2bq_d_1_i ( + .I(com_tlm_u_tlm_rx_vc0_fifo_un1_select_oq2bq_d_1_4238), + .O(com_tlm_u_tlm_rx_vc0_fifo_un1_select_oq2bq_d_1_i_4237) + ); + INV com_tlm_u_tlm_rx_vc0_fifo_N_10675_i_i_i ( + .I(com_tlm_u_tlm_rx_vc0_fifo_N_10675_i_i), + .O(com_tlm_u_tlm_rx_vc0_fifo_N_10675_i_i_i_4239) + ); + INV com_tlm_u_tlm_rx_vc0_fifo_N_85839_i ( + .I(com_tlm_u_tlm_rx_vc0_fifo_adv_pkt_in_i_4241), + .O(com_tlm_u_tlm_rx_vc0_fifo_N_85839_i_4240) + ); + VCC com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_VCC ( + .P(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_VCC_4350) + ); + GND com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_GND ( + .G(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_GND_4305) + ); + FDRE com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr_bkp_0_ ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_frm_vld), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr_p1[0]), + .Q(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr_bkp[0]), + .R(plm_link_up_i) + ); + FDRE com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr_bkp_1_ ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_frm_vld), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr_p1[1]), + .Q(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr_bkp[1]), + .R(plm_link_up_i) + ); + FDRE com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr_bkp_2_ ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_frm_vld), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr_p1[2]), + .Q(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr_bkp[2]), + .R(plm_link_up_i) + ); + FDRE com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr_bkp_3_ ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_frm_vld), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr_p1[3]), + .Q(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr_bkp[3]), + .R(plm_link_up_i) + ); + FDRE com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr_bkp_4_ ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_frm_vld), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr_p1[4]), + .Q(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr_bkp[4]), + .R(plm_link_up_i) + ); + FDRE com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr_bkp_5_ ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_frm_vld), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr_p1[5]), + .Q(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr_bkp[5]), + .R(plm_link_up_i) + ); + FDRE com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr_bkp_6_ ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_frm_vld), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr_p1[6]), + .Q(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr_bkp[6]), + .R(plm_link_up_i) + ); + FDRE com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr_bkp_7_ ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_frm_vld), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr_p1[7]), + .Q(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr_bkp[7]), + .R(plm_link_up_i) + ); + FDRE com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr_bkp_8_ ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_frm_vld), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr_p1[8]), + .Q(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr_bkp[8]), + .R(plm_link_up_i) + ); + FDRE com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr_bkp_9_ ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_frm_vld), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr_p1[9]), + .Q(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr_bkp[9]), + .R(plm_link_up_i) + ); + FDS com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr_p1_0_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_waddr_p1_1_s_0_4242), + .Q(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr_p1[0]), + .S(plm_link_up_i) + ); + FDR com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr_p1_1_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_waddr_p1_1_s_1_4243), + .Q(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr_p1[1]), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr_p1_2_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_waddr_p1_1_s_2_4245), + .Q(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr_p1[2]), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr_p1_3_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_waddr_p1_1_s_3_4247), + .Q(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr_p1[3]), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr_p1_4_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_waddr_p1_1_s_4_4249), + .Q(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr_p1[4]), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr_p1_5_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_waddr_p1_1_s_5_4251), + .Q(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr_p1[5]), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr_p1_6_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_waddr_p1_1_s_6_4253), + .Q(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr_p1[6]), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr_p1_7_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_waddr_p1_1_s_7_4255), + .Q(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr_p1[7]), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr_p1_8_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_waddr_p1_1_s_8_4257), + .Q(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr_p1[8]), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr_p1_9_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_waddr_p1_1_s_9_4259), + .Q(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr_p1[9]), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_vld_ct_0_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_vld_ct_1_axb_0_4315), + .Q(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_vld_ct[0]), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_vld_ct_1_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_vld_ct_1_s_1_4285), + .Q(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_vld_ct[1]), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_vld_ct_2_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_vld_ct_1_s_2_4287), + .Q(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_vld_ct[2]), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_vld_ct_3_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_vld_ct_1_s_3_4289), + .Q(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_vld_ct[3]), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_vld_ct_4_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_vld_ct_1_s_4_4291), + .Q(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_vld_ct[4]), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_vld_ct_5_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_vld_ct_1_s_5_4293), + .Q(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_vld_ct[5]), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_vld_ct_6_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_vld_ct_1_s_6_4295), + .Q(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_vld_ct[6]), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_vld_ct_7_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_vld_ct_1_s_7_4298), + .Q(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_vld_ct[7]), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_vld_ct_8_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_vld_ct_1_s_8_4301), + .Q(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_vld_ct[8]), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_vld_ct_9_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_vld_ct_1_s_9_4303), + .Q(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_vld_ct[9]), + .R(plm_link_up_i) + ); + FDSE com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_pkt_ct_m1_0_ ( + .CE(com_tlm_u_tlm_rx_ds_src_rdy), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un8_pkt_ct_m1_i[0]), + .Q(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_pkt_ct_m1[0]), + .S(plm_link_up_i) + ); + FDRE com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_pkt_ct_m1_1_ ( + .CE(com_tlm_u_tlm_rx_ds_src_rdy), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un3_pkt_ct_m1_s_1_4273), + .Q(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_pkt_ct_m1[1]), + .R(plm_link_up_i) + ); + FDRE com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_pkt_ct_m1_2_ ( + .CE(com_tlm_u_tlm_rx_ds_src_rdy), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un3_pkt_ct_m1_s_2_4275), + .Q(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_pkt_ct_m1[2]), + .R(plm_link_up_i) + ); + FDRE com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_pkt_ct_m1_3_ ( + .CE(com_tlm_u_tlm_rx_ds_src_rdy), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un3_pkt_ct_m1_s_3_4277), + .Q(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_pkt_ct_m1[3]), + .R(plm_link_up_i) + ); + FDRE com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_pkt_ct_m1_4_ ( + .CE(com_tlm_u_tlm_rx_ds_src_rdy), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un3_pkt_ct_m1_s_4_4279), + .Q(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_pkt_ct_m1[4]), + .R(plm_link_up_i) + ); + FDRE com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_pkt_ct_m1_5_ ( + .CE(com_tlm_u_tlm_rx_ds_src_rdy), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un3_pkt_ct_m1_s_5_4281), + .Q(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_pkt_ct_m1[5]), + .R(plm_link_up_i) + ); + FDRE com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_pkt_ct_m1_6_ ( + .CE(com_tlm_u_tlm_rx_ds_src_rdy), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un3_pkt_ct_m1_s_6_4283), + .Q(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_pkt_ct_m1[6]), + .R(plm_link_up_i) + ); + FDRE com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_pkt_ct_0_ ( + .CE(com_tlm_u_tlm_rx_ds_src_rdy), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un8_pkt_ct[0]), + .Q(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_pkt_ct[0]), + .R(plm_link_up_i) + ); + FDSE com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_pkt_ct_1_ ( + .CE(com_tlm_u_tlm_rx_ds_src_rdy), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un3_pkt_ct_s_1_4261), + .Q(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_pkt_ct[1]), + .S(plm_link_up_i) + ); + FDRE com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_pkt_ct_2_ ( + .CE(com_tlm_u_tlm_rx_ds_src_rdy), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un3_pkt_ct_s_2_4263), + .Q(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_pkt_ct[2]), + .R(plm_link_up_i) + ); + FDRE com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_pkt_ct_3_ ( + .CE(com_tlm_u_tlm_rx_ds_src_rdy), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un3_pkt_ct_s_3_4265), + .Q(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_pkt_ct[3]), + .R(plm_link_up_i) + ); + FDRE com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_pkt_ct_4_ ( + .CE(com_tlm_u_tlm_rx_ds_src_rdy), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un3_pkt_ct_s_4_4267), + .Q(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_pkt_ct[4]), + .R(plm_link_up_i) + ); + FDRE com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_pkt_ct_5_ ( + .CE(com_tlm_u_tlm_rx_ds_src_rdy), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un3_pkt_ct_s_5_4269), + .Q(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_pkt_ct[5]), + .R(plm_link_up_i) + ); + FDRE com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_pkt_ct_6_ ( + .CE(com_tlm_u_tlm_rx_ds_src_rdy), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un3_pkt_ct_s_6_4271), + .Q(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_pkt_ct[6]), + .R(plm_link_up_i) + ); + FDRE com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_all_full ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_N_10763_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_N_10763_1), + .Q(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_all_full_4307), + .R(plm_link_up_i) + ); + FDRE com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_vld_o ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_N_43142_i_i_4311), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_nxt_vld_4309), + .Q(com_tlm_u_tlm_rx_vc0_fifo_data_vld_oqr), + .R(plm_link_up_i) + ); + FDRSE com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_nxt_vld ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_vld_ct_eq_1_4312), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_GND_4305), + .Q(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_nxt_vld_4309), + .R(plm_link_up_i), + .S(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_vld_ct25) + ); + FDRE com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_lockout ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_N_16460_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_ds_eof_i), + .Q(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_lockout_4306), + .R(plm_link_up_i) + ); + MUXCY_L com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_waddr_p1_1_cry_0 ( + .CI(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_N_10762_i_4348), + .DI(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_GND_4305), + .LO(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_waddr_p1_1_cry_0_4244), + .S(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_waddr_p1_1_axb_0_4346) + ); + XORCY com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_waddr_p1_1_s_0 ( + .CI(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_N_10762_i_4348), + .LI(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_waddr_p1_1_axb_0_4346), + .O(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_waddr_p1_1_s_0_4242) + ); + MUXCY_L com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_waddr_p1_1_cry_1 ( + .CI(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_waddr_p1_1_cry_0_4244), + .DI(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_GND_4305), + .LO(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_waddr_p1_1_cry_1_4246), + .S(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_waddr_p1_1_axb_1_4345) + ); + XORCY com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_waddr_p1_1_s_1 ( + .CI(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_waddr_p1_1_cry_0_4244), + .LI(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_waddr_p1_1_axb_1_4345), + .O(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_waddr_p1_1_s_1_4243) + ); + MUXCY_L com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_waddr_p1_1_cry_2 ( + .CI(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_waddr_p1_1_cry_1_4246), + .DI(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_GND_4305), + .LO(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_waddr_p1_1_cry_2_4248), + .S(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_waddr_p1_1_axb_2_4344) + ); + XORCY com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_waddr_p1_1_s_2 ( + .CI(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_waddr_p1_1_cry_1_4246), + .LI(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_waddr_p1_1_axb_2_4344), + .O(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_waddr_p1_1_s_2_4245) + ); + MUXCY_L com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_waddr_p1_1_cry_3 ( + .CI(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_waddr_p1_1_cry_2_4248), + .DI(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_GND_4305), + .LO(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_waddr_p1_1_cry_3_4250), + .S(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_waddr_p1_1_axb_3_4343) + ); + XORCY com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_waddr_p1_1_s_3 ( + .CI(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_waddr_p1_1_cry_2_4248), + .LI(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_waddr_p1_1_axb_3_4343), + .O(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_waddr_p1_1_s_3_4247) + ); + MUXCY_L com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_waddr_p1_1_cry_4 ( + .CI(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_waddr_p1_1_cry_3_4250), + .DI(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_GND_4305), + .LO(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_waddr_p1_1_cry_4_4252), + .S(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_waddr_p1_1_axb_4_4342) + ); + XORCY com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_waddr_p1_1_s_4 ( + .CI(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_waddr_p1_1_cry_3_4250), + .LI(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_waddr_p1_1_axb_4_4342), + .O(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_waddr_p1_1_s_4_4249) + ); + MUXCY_L com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_waddr_p1_1_cry_5 ( + .CI(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_waddr_p1_1_cry_4_4252), + .DI(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_GND_4305), + .LO(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_waddr_p1_1_cry_5_4254), + .S(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_waddr_p1_1_axb_5_4341) + ); + XORCY com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_waddr_p1_1_s_5 ( + .CI(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_waddr_p1_1_cry_4_4252), + .LI(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_waddr_p1_1_axb_5_4341), + .O(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_waddr_p1_1_s_5_4251) + ); + MUXCY_L com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_waddr_p1_1_cry_6 ( + .CI(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_waddr_p1_1_cry_5_4254), + .DI(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_GND_4305), + .LO(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_waddr_p1_1_cry_6_4256), + .S(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_waddr_p1_1_axb_6_4340) + ); + XORCY com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_waddr_p1_1_s_6 ( + .CI(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_waddr_p1_1_cry_5_4254), + .LI(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_waddr_p1_1_axb_6_4340), + .O(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_waddr_p1_1_s_6_4253) + ); + MUXCY_L com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_waddr_p1_1_cry_7 ( + .CI(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_waddr_p1_1_cry_6_4256), + .DI(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_GND_4305), + .LO(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_waddr_p1_1_cry_7_4258), + .S(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_waddr_p1_1_axb_7_4339) + ); + XORCY com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_waddr_p1_1_s_7 ( + .CI(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_waddr_p1_1_cry_6_4256), + .LI(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_waddr_p1_1_axb_7_4339), + .O(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_waddr_p1_1_s_7_4255) + ); + MUXCY_L com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_waddr_p1_1_cry_8 ( + .CI(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_waddr_p1_1_cry_7_4258), + .DI(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_GND_4305), + .LO(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_waddr_p1_1_cry_8_4260), + .S(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_waddr_p1_1_axb_8_4338) + ); + XORCY com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_waddr_p1_1_s_8 ( + .CI(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_waddr_p1_1_cry_7_4258), + .LI(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_waddr_p1_1_axb_8_4338), + .O(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_waddr_p1_1_s_8_4257) + ); + XORCY com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_waddr_p1_1_s_9 ( + .CI(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_waddr_p1_1_cry_8_4260), + .LI(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_waddr_p1_1_axb_9_4337), + .O(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_waddr_p1_1_s_9_4259) + ); + MUXCY_L com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un3_pkt_ct_cry_0 ( + .CI(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_VCC_4350), + .DI(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_GND_4305), + .LO(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un3_pkt_ct_cry_0_4262), + .S(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un3_pkt_ct_axb_0_4354) + ); + MUXCY_L com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un3_pkt_ct_cry_1 ( + .CI(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un3_pkt_ct_cry_0_4262), + .DI(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_GND_4305), + .LO(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un3_pkt_ct_cry_1_4264), + .S(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un3_pkt_ct_axb_1_4322) + ); + XORCY com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un3_pkt_ct_s_1 ( + .CI(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un3_pkt_ct_cry_0_4262), + .LI(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un3_pkt_ct_axb_1_4322), + .O(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un3_pkt_ct_s_1_4261) + ); + MUXCY_L com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un3_pkt_ct_cry_2 ( + .CI(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un3_pkt_ct_cry_1_4264), + .DI(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_GND_4305), + .LO(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un3_pkt_ct_cry_2_4266), + .S(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un3_pkt_ct_axb_2_4321) + ); + XORCY com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un3_pkt_ct_s_2 ( + .CI(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un3_pkt_ct_cry_1_4264), + .LI(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un3_pkt_ct_axb_2_4321), + .O(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un3_pkt_ct_s_2_4263) + ); + MUXCY_L com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un3_pkt_ct_cry_3 ( + .CI(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un3_pkt_ct_cry_2_4266), + .DI(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_GND_4305), + .LO(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un3_pkt_ct_cry_3_4268), + .S(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un3_pkt_ct_axb_3_4320) + ); + XORCY com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un3_pkt_ct_s_3 ( + .CI(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un3_pkt_ct_cry_2_4266), + .LI(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un3_pkt_ct_axb_3_4320), + .O(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un3_pkt_ct_s_3_4265) + ); + MUXCY_L com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un3_pkt_ct_cry_4 ( + .CI(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un3_pkt_ct_cry_3_4268), + .DI(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_GND_4305), + .LO(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un3_pkt_ct_cry_4_4270), + .S(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un3_pkt_ct_axb_4_4319) + ); + XORCY com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un3_pkt_ct_s_4 ( + .CI(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un3_pkt_ct_cry_3_4268), + .LI(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un3_pkt_ct_axb_4_4319), + .O(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un3_pkt_ct_s_4_4267) + ); + MUXCY_L com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un3_pkt_ct_cry_5 ( + .CI(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un3_pkt_ct_cry_4_4270), + .DI(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_GND_4305), + .LO(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un3_pkt_ct_cry_5_4272), + .S(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un3_pkt_ct_axb_5_4318) + ); + XORCY com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un3_pkt_ct_s_5 ( + .CI(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un3_pkt_ct_cry_4_4270), + .LI(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un3_pkt_ct_axb_5_4318), + .O(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un3_pkt_ct_s_5_4269) + ); + XORCY com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un3_pkt_ct_s_6 ( + .CI(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un3_pkt_ct_cry_5_4272), + .LI(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un3_pkt_ct_axb_6_4317), + .O(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un3_pkt_ct_s_6_4271) + ); + MUXCY_L com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un3_pkt_ct_m1_cry_0 ( + .CI(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_VCC_4350), + .DI(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_GND_4305), + .LO(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un3_pkt_ct_m1_cry_0_4274), + .S(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un3_pkt_ct_m1_axb_0_4353) + ); + MUXCY_L com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un3_pkt_ct_m1_cry_1 ( + .CI(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un3_pkt_ct_m1_cry_0_4274), + .DI(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_GND_4305), + .LO(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un3_pkt_ct_m1_cry_1_4276), + .S(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un3_pkt_ct_m1_axb_1_4328) + ); + XORCY com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un3_pkt_ct_m1_s_1 ( + .CI(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un3_pkt_ct_m1_cry_0_4274), + .LI(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un3_pkt_ct_m1_axb_1_4328), + .O(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un3_pkt_ct_m1_s_1_4273) + ); + MUXCY_L com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un3_pkt_ct_m1_cry_2 ( + .CI(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un3_pkt_ct_m1_cry_1_4276), + .DI(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_GND_4305), + .LO(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un3_pkt_ct_m1_cry_2_4278), + .S(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un3_pkt_ct_m1_axb_2_4327) + ); + XORCY com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un3_pkt_ct_m1_s_2 ( + .CI(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un3_pkt_ct_m1_cry_1_4276), + .LI(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un3_pkt_ct_m1_axb_2_4327), + .O(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un3_pkt_ct_m1_s_2_4275) + ); + MUXCY_L com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un3_pkt_ct_m1_cry_3 ( + .CI(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un3_pkt_ct_m1_cry_2_4278), + .DI(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_GND_4305), + .LO(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un3_pkt_ct_m1_cry_3_4280), + .S(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un3_pkt_ct_m1_axb_3_4326) + ); + XORCY com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un3_pkt_ct_m1_s_3 ( + .CI(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un3_pkt_ct_m1_cry_2_4278), + .LI(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un3_pkt_ct_m1_axb_3_4326), + .O(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un3_pkt_ct_m1_s_3_4277) + ); + MUXCY_L com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un3_pkt_ct_m1_cry_4 ( + .CI(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un3_pkt_ct_m1_cry_3_4280), + .DI(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_GND_4305), + .LO(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un3_pkt_ct_m1_cry_4_4282), + .S(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un3_pkt_ct_m1_axb_4_4325) + ); + XORCY com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un3_pkt_ct_m1_s_4 ( + .CI(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un3_pkt_ct_m1_cry_3_4280), + .LI(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un3_pkt_ct_m1_axb_4_4325), + .O(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un3_pkt_ct_m1_s_4_4279) + ); + MUXCY_L com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un3_pkt_ct_m1_cry_5 ( + .CI(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un3_pkt_ct_m1_cry_4_4282), + .DI(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_GND_4305), + .LO(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un3_pkt_ct_m1_cry_5_4284), + .S(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un3_pkt_ct_m1_axb_5_4324) + ); + XORCY com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un3_pkt_ct_m1_s_5 ( + .CI(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un3_pkt_ct_m1_cry_4_4282), + .LI(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un3_pkt_ct_m1_axb_5_4324), + .O(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un3_pkt_ct_m1_s_5_4281) + ); + XORCY com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un3_pkt_ct_m1_s_6 ( + .CI(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un3_pkt_ct_m1_cry_5_4284), + .LI(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un3_pkt_ct_m1_axb_6_4323), + .O(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un3_pkt_ct_m1_s_6_4283) + ); + MUXCY_L com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_vld_ct_1_cry_0 ( + .CI(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_GND_4305), + .DI(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_vld_ct[0]), + .LO(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_vld_ct_1_cry_0_4286), + .S(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_vld_ct_1_axb_0_4315) + ); + MUXCY_L com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_vld_ct_1_cry_1 ( + .CI(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_vld_ct_1_cry_0_4286), + .DI(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_vld_ct[1]), + .LO(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_vld_ct_1_cry_1_4288), + .S(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_vld_ct_1_axb_1_4336) + ); + XORCY com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_vld_ct_1_s_1 ( + .CI(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_vld_ct_1_cry_0_4286), + .LI(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_vld_ct_1_axb_1_4336), + .O(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_vld_ct_1_s_1_4285) + ); + MUXCY_L com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_vld_ct_1_cry_2 ( + .CI(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_vld_ct_1_cry_1_4288), + .DI(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_vld_ct[2]), + .LO(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_vld_ct_1_cry_2_4290), + .S(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_vld_ct_1_axb_2_4335) + ); + XORCY com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_vld_ct_1_s_2 ( + .CI(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_vld_ct_1_cry_1_4288), + .LI(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_vld_ct_1_axb_2_4335), + .O(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_vld_ct_1_s_2_4287) + ); + MUXCY_L com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_vld_ct_1_cry_3 ( + .CI(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_vld_ct_1_cry_2_4290), + .DI(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_vld_ct[3]), + .LO(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_vld_ct_1_cry_3_4292), + .S(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_vld_ct_1_axb_3_4334) + ); + XORCY com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_vld_ct_1_s_3 ( + .CI(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_vld_ct_1_cry_2_4290), + .LI(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_vld_ct_1_axb_3_4334), + .O(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_vld_ct_1_s_3_4289) + ); + MUXCY_L com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_vld_ct_1_cry_4 ( + .CI(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_vld_ct_1_cry_3_4292), + .DI(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_vld_ct[4]), + .LO(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_vld_ct_1_cry_4_4294), + .S(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_vld_ct_1_axb_4_4333) + ); + XORCY com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_vld_ct_1_s_4 ( + .CI(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_vld_ct_1_cry_3_4292), + .LI(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_vld_ct_1_axb_4_4333), + .O(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_vld_ct_1_s_4_4291) + ); + MUXCY_L com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_vld_ct_1_cry_5 ( + .CI(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_vld_ct_1_cry_4_4294), + .DI(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_vld_ct[5]), + .LO(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_vld_ct_1_cry_5_4296), + .S(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_vld_ct_1_axb_5_4332) + ); + XORCY com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_vld_ct_1_s_5 ( + .CI(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_vld_ct_1_cry_4_4294), + .LI(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_vld_ct_1_axb_5_4332), + .O(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_vld_ct_1_s_5_4293) + ); + MUXCY_L com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_vld_ct_1_cry_6 ( + .CI(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_vld_ct_1_cry_5_4296), + .DI(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_vld_ct_1_cry_6_ma_4349), + .LO(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_vld_ct_1_cry_6_4299), + .S(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_vld_ct_1_axb_6_4331) + ); + XORCY com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_vld_ct_1_s_6 ( + .CI(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_vld_ct_1_cry_5_4296), + .LI(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_vld_ct_1_axb_6_4331), + .O(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_vld_ct_1_s_6_4295) + ); + MULT_AND com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_vld_ct_1_cry_7 ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_pop_4352), + .I1(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_vld_ct25_i), + .LO(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_vld_ct_1_cry_7_0_4297) + ); + MUXCY_L com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_vld_ct_1_cry_7_0 ( + .CI(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_vld_ct_1_cry_6_4299), + .DI(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_vld_ct_1_cry_7_0_4297), + .LO(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_vld_ct_1_cry_7_4302), + .S(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_vld_ct_1_axb_7_4330) + ); + XORCY com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_vld_ct_1_s_7 ( + .CI(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_vld_ct_1_cry_6_4299), + .LI(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_vld_ct_1_axb_7_4330), + .O(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_vld_ct_1_s_7_4298) + ); + MULT_AND com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_vld_ct_1_cry_8 ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_pop_4352), + .I1(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_vld_ct25_i), + .LO(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_vld_ct_1_cry_8_0_4300) + ); + MUXCY_L com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_vld_ct_1_cry_8_0 ( + .CI(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_vld_ct_1_cry_7_4302), + .DI(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_vld_ct_1_cry_8_0_4300), + .LO(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_vld_ct_1_cry_8_4304), + .S(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_vld_ct_1_axb_8_4329) + ); + XORCY com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_vld_ct_1_s_8 ( + .CI(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_vld_ct_1_cry_7_4302), + .LI(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_vld_ct_1_axb_8_4329), + .O(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_vld_ct_1_s_8_4301) + ); + XORCY com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_vld_ct_1_s_9 ( + .CI(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_vld_ct_1_cry_8_4304), + .LI(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_vld_ct_1_axb_9_4351), + .O(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_vld_ct_1_s_9_4303) + ); + FDRE com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_raddr_0_ ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_pop_4352), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_raddr_s[0]), + .Q(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_raddr[0]), + .R(plm_link_up_i) + ); + MUXCY_L com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_raddr_cry_1_ ( + .CI(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_raddr[0]), + .DI(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_GND_4305), + .LO(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_raddr_cry[1]), + .S(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_raddr_qxu[1]) + ); + XORCY com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_raddr_s_1_ ( + .CI(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_raddr[0]), + .LI(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_raddr_qxu[1]), + .O(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_raddr_s[1]) + ); + FDRE com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_raddr_1_ ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_pop_4352), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_raddr_s[1]), + .Q(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_raddr[1]), + .R(plm_link_up_i) + ); + MUXCY_L com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_raddr_cry_2_ ( + .CI(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_raddr_cry[1]), + .DI(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_GND_4305), + .LO(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_raddr_cry[2]), + .S(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_raddr_qxu[2]) + ); + XORCY com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_raddr_s_2_ ( + .CI(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_raddr_cry[1]), + .LI(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_raddr_qxu[2]), + .O(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_raddr_s[2]) + ); + FDRE com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_raddr_2_ ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_pop_4352), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_raddr_s[2]), + .Q(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_raddr[2]), + .R(plm_link_up_i) + ); + MUXCY_L com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_raddr_cry_3_ ( + .CI(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_raddr_cry[2]), + .DI(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_GND_4305), + .LO(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_raddr_cry[3]), + .S(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_raddr_qxu[3]) + ); + XORCY com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_raddr_s_3_ ( + .CI(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_raddr_cry[2]), + .LI(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_raddr_qxu[3]), + .O(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_raddr_s[3]) + ); + FDRE com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_raddr_3_ ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_pop_4352), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_raddr_s[3]), + .Q(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_raddr[3]), + .R(plm_link_up_i) + ); + MUXCY_L com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_raddr_cry_4_ ( + .CI(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_raddr_cry[3]), + .DI(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_GND_4305), + .LO(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_raddr_cry[4]), + .S(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_raddr_qxu[4]) + ); + XORCY com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_raddr_s_4_ ( + .CI(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_raddr_cry[3]), + .LI(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_raddr_qxu[4]), + .O(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_raddr_s[4]) + ); + FDRE com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_raddr_4_ ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_pop_4352), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_raddr_s[4]), + .Q(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_raddr[4]), + .R(plm_link_up_i) + ); + MUXCY_L com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_raddr_cry_5_ ( + .CI(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_raddr_cry[4]), + .DI(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_GND_4305), + .LO(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_raddr_cry[5]), + .S(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_raddr_qxu[5]) + ); + XORCY com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_raddr_s_5_ ( + .CI(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_raddr_cry[4]), + .LI(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_raddr_qxu[5]), + .O(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_raddr_s[5]) + ); + FDRE com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_raddr_5_ ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_pop_4352), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_raddr_s[5]), + .Q(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_raddr[5]), + .R(plm_link_up_i) + ); + MUXCY_L com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_raddr_cry_6_ ( + .CI(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_raddr_cry[5]), + .DI(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_GND_4305), + .LO(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_raddr_cry[6]), + .S(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_raddr_qxu[6]) + ); + XORCY com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_raddr_s_6_ ( + .CI(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_raddr_cry[5]), + .LI(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_raddr_qxu[6]), + .O(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_raddr_s[6]) + ); + FDRE com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_raddr_6_ ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_pop_4352), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_raddr_s[6]), + .Q(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_raddr[6]), + .R(plm_link_up_i) + ); + MUXCY_L com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_raddr_cry_7_ ( + .CI(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_raddr_cry[6]), + .DI(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_GND_4305), + .LO(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_raddr_cry[7]), + .S(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_raddr_qxu[7]) + ); + XORCY com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_raddr_s_7_ ( + .CI(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_raddr_cry[6]), + .LI(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_raddr_qxu[7]), + .O(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_raddr_s[7]) + ); + FDRE com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_raddr_7_ ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_pop_4352), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_raddr_s[7]), + .Q(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_raddr[7]), + .R(plm_link_up_i) + ); + MUXCY_L com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_raddr_cry_8_ ( + .CI(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_raddr_cry[7]), + .DI(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_GND_4305), + .LO(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_raddr_cry[8]), + .S(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_raddr_qxu[8]) + ); + XORCY com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_raddr_s_8_ ( + .CI(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_raddr_cry[7]), + .LI(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_raddr_qxu[8]), + .O(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_raddr_s[8]) + ); + FDRE com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_raddr_8_ ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_pop_4352), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_raddr_s[8]), + .Q(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_raddr[8]), + .R(plm_link_up_i) + ); + XORCY com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_raddr_s_9_ ( + .CI(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_raddr_cry[8]), + .LI(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_raddr_qxu[9]), + .O(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_raddr_s[9]) + ); + FDRE com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_raddr_9_ ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_pop_4352), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_raddr_s[9]), + .Q(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_raddr[9]), + .R(plm_link_up_i) + ); + MUXCY_L com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr_cry_0_ ( + .CI(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_overflow_1_i), + .DI(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_GND_4305), + .LO(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr_cry[0]), + .S(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr_qxu[0]) + ); + XORCY com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr_s_0_ ( + .CI(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_overflow_1_i), + .LI(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr_qxu[0]), + .O(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr_s[0]) + ); + FDRE com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr_0_ ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_N_10350_i_4316), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr_s[0]), + .Q(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr[0]), + .R(plm_link_up_i) + ); + MUXCY_L com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr_cry_1_ ( + .CI(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr_cry[0]), + .DI(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_GND_4305), + .LO(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr_cry[1]), + .S(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr_qxu[1]) + ); + XORCY com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr_s_1_ ( + .CI(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr_cry[0]), + .LI(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr_qxu[1]), + .O(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr_s[1]) + ); + FDRE com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr_1_ ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_N_10350_i_4316), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr_s[1]), + .Q(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr[1]), + .R(plm_link_up_i) + ); + MUXCY_L com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr_cry_2_ ( + .CI(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr_cry[1]), + .DI(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_GND_4305), + .LO(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr_cry[2]), + .S(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr_qxu[2]) + ); + XORCY com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr_s_2_ ( + .CI(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr_cry[1]), + .LI(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr_qxu[2]), + .O(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr_s[2]) + ); + FDRE com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr_2_ ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_N_10350_i_4316), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr_s[2]), + .Q(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr[2]), + .R(plm_link_up_i) + ); + MUXCY_L com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr_cry_3_ ( + .CI(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr_cry[2]), + .DI(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_GND_4305), + .LO(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr_cry[3]), + .S(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr_qxu[3]) + ); + XORCY com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr_s_3_ ( + .CI(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr_cry[2]), + .LI(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr_qxu[3]), + .O(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr_s[3]) + ); + FDRE com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr_3_ ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_N_10350_i_4316), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr_s[3]), + .Q(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr[3]), + .R(plm_link_up_i) + ); + MUXCY_L com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr_cry_4_ ( + .CI(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr_cry[3]), + .DI(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_GND_4305), + .LO(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr_cry[4]), + .S(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr_qxu[4]) + ); + XORCY com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr_s_4_ ( + .CI(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr_cry[3]), + .LI(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr_qxu[4]), + .O(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr_s[4]) + ); + FDRE com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr_4_ ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_N_10350_i_4316), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr_s[4]), + .Q(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr[4]), + .R(plm_link_up_i) + ); + MUXCY_L com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr_cry_5_ ( + .CI(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr_cry[4]), + .DI(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_GND_4305), + .LO(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr_cry[5]), + .S(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr_qxu[5]) + ); + XORCY com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr_s_5_ ( + .CI(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr_cry[4]), + .LI(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr_qxu[5]), + .O(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr_s[5]) + ); + FDRE com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr_5_ ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_N_10350_i_4316), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr_s[5]), + .Q(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr[5]), + .R(plm_link_up_i) + ); + MUXCY_L com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr_cry_6_ ( + .CI(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr_cry[5]), + .DI(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_GND_4305), + .LO(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr_cry[6]), + .S(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr_qxu[6]) + ); + XORCY com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr_s_6_ ( + .CI(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr_cry[5]), + .LI(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr_qxu[6]), + .O(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr_s[6]) + ); + FDRE com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr_6_ ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_N_10350_i_4316), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr_s[6]), + .Q(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr[6]), + .R(plm_link_up_i) + ); + MUXCY_L com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr_cry_7_ ( + .CI(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr_cry[6]), + .DI(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_GND_4305), + .LO(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr_cry[7]), + .S(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr_qxu[7]) + ); + XORCY com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr_s_7_ ( + .CI(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr_cry[6]), + .LI(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr_qxu[7]), + .O(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr_s[7]) + ); + FDRE com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr_7_ ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_N_10350_i_4316), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr_s[7]), + .Q(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr[7]), + .R(plm_link_up_i) + ); + MUXCY_L com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr_cry_8_ ( + .CI(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr_cry[7]), + .DI(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_GND_4305), + .LO(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr_cry[8]), + .S(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr_qxu[8]) + ); + XORCY com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr_s_8_ ( + .CI(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr_cry[7]), + .LI(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr_qxu[8]), + .O(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr_s[8]) + ); + FDRE com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr_8_ ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_N_10350_i_4316), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr_s[8]), + .Q(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr[8]), + .R(plm_link_up_i) + ); + XORCY com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr_s_9_ ( + .CI(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr_cry[8]), + .LI(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr_qxu[9]), + .O(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr_s[9]) + ); + FDRE com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr_9_ ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_N_10350_i_4316), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr_s[9]), + .Q(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr[9]), + .R(plm_link_up_i) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_overflow.INIT = 4'h8; + LUT2 com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_overflow ( + .I0(com_tlm_u_tlm_rx_ds_src_rdy), + .I1(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_all_full_4307), + .O(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_overflow_4310) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un6_d_o_0_o3_0_.INIT = 4'h8; + LUT2 com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un6_d_o_0_o3_0_ ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_data_vld_oqr), + .I1(com_tlm_u_tlm_rx_vc0_fifo_ram_dout[64]), + .O(com_tlm_u_tlm_rx_vc0_fifo_N_44135_i) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un6_d_o_0_a2_3_.INIT = 4'h8; + LUT2 com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un6_d_o_0_a2_3_ ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_data_vld_oqr), + .I1(com_tlm_u_tlm_rx_vc0_fifo_ram_dout[67]), + .O(com_tlm_u_tlm_rx_vc0_fifo_rem_oqr) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un6_d_o_0_a2_1_.INIT = 4'h8; + LUT2 com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un6_d_o_0_a2_1_ ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_data_vld_oqr), + .I1(com_tlm_u_tlm_rx_vc0_fifo_ram_dout[65]), + .O(com_tlm_u_tlm_rx_vc0_fifo_eof_oqr) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_standard_all_full_un1_waddr_p1_3.INIT = 4'h6; + LUT2 com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_standard_all_full_un1_waddr_p1_3 ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_raddr[3]), + .I1(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr_p1[3]), + .O(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_waddr_p1_3) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un10_vld_ct_0_0_.INIT = 8'hCA; + LUT3_L com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un10_vld_ct_0_0_ ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_pkt_ct[0]), + .I1(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_pkt_ct_m1[0]), + .I2(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_pop_4352), + .LO(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un10_vld_ct[0]) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un10_vld_ct_0_1_.INIT = 8'hCA; + LUT3_L com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un10_vld_ct_0_1_ ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_pkt_ct[1]), + .I1(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_pkt_ct_m1[1]), + .I2(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_pop_4352), + .LO(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un10_vld_ct[1]) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un10_vld_ct_0_2_.INIT = 8'hCA; + LUT3_L com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un10_vld_ct_0_2_ ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_pkt_ct[2]), + .I1(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_pkt_ct_m1[2]), + .I2(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_pop_4352), + .LO(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un10_vld_ct[2]) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un10_vld_ct_0_3_.INIT = 8'hCA; + LUT3_L com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un10_vld_ct_0_3_ ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_pkt_ct[3]), + .I1(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_pkt_ct_m1[3]), + .I2(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_pop_4352), + .LO(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un10_vld_ct[3]) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un10_vld_ct_0_4_.INIT = 8'hCA; + LUT3_L com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un10_vld_ct_0_4_ ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_pkt_ct[4]), + .I1(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_pkt_ct_m1[4]), + .I2(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_pop_4352), + .LO(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un10_vld_ct[4]) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un10_vld_ct_0_5_.INIT = 8'hCA; + LUT3_L com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un10_vld_ct_0_5_ ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_pkt_ct[5]), + .I1(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_pkt_ct_m1[5]), + .I2(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_pop_4352), + .LO(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un10_vld_ct[5]) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un10_vld_ct_0_6_.INIT = 8'hCA; + LUT3_L com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un10_vld_ct_0_6_ ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_pkt_ct[6]), + .I1(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_pkt_ct_m1[6]), + .I2(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_pop_4352), + .LO(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un10_vld_ct[6]) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_wen_i_1_i.INIT = 8'hC8; + LUT3 com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_wen_i_1_i ( + .I0(com_tlm_u_tlm_rx_ds_eof), + .I1(com_tlm_u_tlm_rx_ds_src_rdy), + .I2(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_all_full_4307), + .O(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_N_16460_i) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_push_0_a2.INIT = 8'h02; + LUT3 com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_push_0_a2 ( + .I0(com_tlm_u_tlm_rx_ds_src_rdy), + .I1(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_all_full_4307), + .I2(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_lockout_4306), + .O(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_push) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_standard_all_full_un1_wen_i_1.INIT = 16'h8421; + LUT4_L com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_standard_all_full_un1_wen_i_1 ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_raddr[7]), + .I1(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_raddr[8]), + .I2(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr_p1[7]), + .I3(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr_p1[8]), + .LO(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_wen_i_1) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_standard_all_full_un1_wen_i_2.INIT = 16'h8421; + LUT4 com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_standard_all_full_un1_wen_i_2 ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_raddr[5]), + .I1(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_raddr[6]), + .I2(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr_p1[5]), + .I3(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr_p1[6]), + .O(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_wen_i_2) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_standard_all_full_un1_wen_i_4.INIT = 16'h8421; + LUT4_L com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_standard_all_full_un1_wen_i_4 ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_raddr[0]), + .I1(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_raddr[2]), + .I2(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr_p1[0]), + .I3(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr_p1[2]), + .LO(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_wen_i_4) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_vld_ct_eq_1_5.INIT = 16'h0002; + LUT4_L com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_vld_ct_eq_1_5 ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_vld_ct[0]), + .I1(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_vld_ct[7]), + .I2(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_vld_ct[8]), + .I3(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_vld_ct[9]), + .LO(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_vld_ct_eq_1_5_4308) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_vld_ct_eq_1_6.INIT = 16'h0001; + LUT4 com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_vld_ct_eq_1_6 ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_vld_ct[3]), + .I1(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_vld_ct[4]), + .I2(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_vld_ct[5]), + .I3(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_vld_ct[6]), + .O(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_vld_ct_eq_1_6_4314) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_frm_vld_0_a2.INIT = 8'h10; + LUT3 com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_frm_vld_0_a2 ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_all_full_4307), + .I1(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_lockout_4306), + .I2(com_tlm_u_tlm_rx_wen_aux_oq_3), + .O(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_frm_vld) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_standard_all_full_un1_wen_i_5.INIT = 8'h84; + LUT3 com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_standard_all_full_un1_wen_i_5 ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_raddr[1]), + .I1(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_wen_i_4), + .I2(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr_p1[1]), + .O(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_wen_i_5) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_standard_all_full_un1_wen_i_6.INIT = 16'h2010; + LUT4 com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_standard_all_full_un1_wen_i_6 ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_raddr[4]), + .I1(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_waddr_p1_3), + .I2(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_wen_i_2), + .I3(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr_p1[4]), + .O(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_wen_i_6) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_standard_all_full_un1_wen_i_7.INIT = 16'h8020; + LUT4 com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_standard_all_full_un1_wen_i_7 ( + .I0(com_tlm_u_tlm_rx_ds_src_rdy), + .I1(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_raddr[9]), + .I2(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_wen_i_1), + .I3(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr_p1[9]), + .O(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_wen_i_7) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_vld_ct_eq_1_7.INIT = 8'h02; + LUT3 com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_vld_ct_eq_1_7 ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_vld_ct_eq_1_5_4308), + .I1(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_vld_ct[1]), + .I2(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_vld_ct[2]), + .O(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_vld_ct_eq_1_7_4313) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_standard_vld_ct_vld_ct25.INIT = 4'h8; + LUT2 com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_standard_vld_ct_vld_ct25 ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_frm_vld), + .I1(plm_link_up_1), + .O(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_vld_ct25) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_overflow_1.INIT = 8'h0D; + LUT3 com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_overflow_1 ( + .I0(com_tlm_u_tlm_rx_ds_eof), + .I1(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_frm_vld), + .I2(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_overflow_4310), + .O(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_overflow_1_i) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr16.INIT = 4'h4; + LUT2 com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr16 ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_overflow_1_i), + .I1(plm_link_up_1), + .O(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr16_4347) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_pop.INIT = 8'h70; + LUT3 com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_pop ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_ren_oq_i_a3_0_4150), + .I1(com_tlm_u_tlm_rx_vc0_fifo_data_vld_oqr), + .I2(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_nxt_vld_4309), + .O(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_pop_4352) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_standard_all_full_un1_ren_i_1.INIT = 16'h0020; + LUT4 com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_standard_all_full_un1_ren_i_1 ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_ren_oq_i_a3_0_4150), + .I1(com_tlm_u_tlm_rx_ds_dsc), + .I2(com_tlm_u_tlm_rx_vc0_fifo_data_vld_oqr), + .I3(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_overflow_4310), + .O(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_N_10763_1) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_N_43142_i_i.INIT = 4'h7; + LUT2 com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_N_43142_i_i ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_ren_oq_i_a3_0_4150), + .I1(com_tlm_u_tlm_rx_vc0_fifo_data_vld_oqr), + .O(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_N_43142_i_i_4311) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_vld_ct_eq_1.INIT = 16'h7000; + LUT4 com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_vld_ct_eq_1 ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_ren_oq_i_a3_0_4150), + .I1(com_tlm_u_tlm_rx_vc0_fifo_data_vld_oqr), + .I2(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_vld_ct_eq_1_6_4314), + .I3(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_vld_ct_eq_1_7_4313), + .O(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_vld_ct_eq_1_4312) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_vld_ct_1_axb_0.INIT = 16'h1DE2; + LUT4 com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_vld_ct_1_axb_0 ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_pop_4352), + .I1(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_vld_ct25), + .I2(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un10_vld_ct[0]), + .I3(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_vld_ct[0]), + .O(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_vld_ct_1_axb_0_4315) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_N_10350_i.INIT = 4'hB; + LUT2 com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_N_10350_i ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_push), + .I1(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_overflow_1_i), + .O(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_N_10350_i_4316) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_standard_all_full_N_10763_i.INIT = 16'hD555; + LUT4 com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_standard_all_full_N_10763_i ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_N_10763_1), + .I1(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_wen_i_5), + .I2(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_wen_i_6), + .I3(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_wen_i_7), + .O(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_N_10763_i) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr_qxu_9_.INIT = 8'hD8; + LUT3_L com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr_qxu_9_ ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_overflow_1_i), + .I1(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr[9]), + .I2(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr_bkp[9]), + .LO(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr_qxu[9]) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr_qxu_8_.INIT = 8'hD8; + LUT3_L com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr_qxu_8_ ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_overflow_1_i), + .I1(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr[8]), + .I2(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr_bkp[8]), + .LO(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr_qxu[8]) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr_qxu_7_.INIT = 8'hD8; + LUT3_L com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr_qxu_7_ ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_overflow_1_i), + .I1(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr[7]), + .I2(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr_bkp[7]), + .LO(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr_qxu[7]) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr_qxu_6_.INIT = 8'hD8; + LUT3_L com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr_qxu_6_ ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_overflow_1_i), + .I1(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr[6]), + .I2(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr_bkp[6]), + .LO(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr_qxu[6]) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr_qxu_5_.INIT = 8'hD8; + LUT3_L com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr_qxu_5_ ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_overflow_1_i), + .I1(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr[5]), + .I2(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr_bkp[5]), + .LO(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr_qxu[5]) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr_qxu_4_.INIT = 8'hD8; + LUT3_L com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr_qxu_4_ ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_overflow_1_i), + .I1(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr[4]), + .I2(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr_bkp[4]), + .LO(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr_qxu[4]) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr_qxu_3_.INIT = 8'hD8; + LUT3_L com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr_qxu_3_ ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_overflow_1_i), + .I1(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr[3]), + .I2(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr_bkp[3]), + .LO(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr_qxu[3]) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr_qxu_2_.INIT = 8'hD8; + LUT3_L com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr_qxu_2_ ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_overflow_1_i), + .I1(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr[2]), + .I2(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr_bkp[2]), + .LO(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr_qxu[2]) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr_qxu_1_.INIT = 8'hD8; + LUT3_L com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr_qxu_1_ ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_overflow_1_i), + .I1(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr[1]), + .I2(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr_bkp[1]), + .LO(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr_qxu[1]) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr_qxu_0_.INIT = 8'hD8; + LUT3_L com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr_qxu_0_ ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_overflow_1_i), + .I1(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr[0]), + .I2(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr_bkp[0]), + .LO(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr_qxu[0]) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un3_pkt_ct_axb_6.INIT = 4'h4; + LUT2_L com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un3_pkt_ct_axb_6 ( + .I0(com_tlm_u_tlm_rx_ds_sof), + .I1(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_pkt_ct[6]), + .LO(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un3_pkt_ct_axb_6_4317) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un3_pkt_ct_axb_5.INIT = 4'h4; + LUT2_L com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un3_pkt_ct_axb_5 ( + .I0(com_tlm_u_tlm_rx_ds_sof), + .I1(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_pkt_ct[5]), + .LO(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un3_pkt_ct_axb_5_4318) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un3_pkt_ct_axb_4.INIT = 4'h4; + LUT2_L com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un3_pkt_ct_axb_4 ( + .I0(com_tlm_u_tlm_rx_ds_sof), + .I1(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_pkt_ct[4]), + .LO(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un3_pkt_ct_axb_4_4319) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un3_pkt_ct_axb_3.INIT = 4'h4; + LUT2_L com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un3_pkt_ct_axb_3 ( + .I0(com_tlm_u_tlm_rx_ds_sof), + .I1(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_pkt_ct[3]), + .LO(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un3_pkt_ct_axb_3_4320) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un3_pkt_ct_axb_2.INIT = 4'h4; + LUT2_L com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un3_pkt_ct_axb_2 ( + .I0(com_tlm_u_tlm_rx_ds_sof), + .I1(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_pkt_ct[2]), + .LO(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un3_pkt_ct_axb_2_4321) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un3_pkt_ct_axb_1.INIT = 4'h4; + LUT2_L com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un3_pkt_ct_axb_1 ( + .I0(com_tlm_u_tlm_rx_ds_sof), + .I1(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_pkt_ct[1]), + .LO(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un3_pkt_ct_axb_1_4322) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un3_pkt_ct_m1_axb_6.INIT = 4'h4; + LUT2_L com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un3_pkt_ct_m1_axb_6 ( + .I0(com_tlm_u_tlm_rx_ds_sof), + .I1(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_pkt_ct_m1[6]), + .LO(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un3_pkt_ct_m1_axb_6_4323) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un3_pkt_ct_m1_axb_5.INIT = 4'h4; + LUT2_L com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un3_pkt_ct_m1_axb_5 ( + .I0(com_tlm_u_tlm_rx_ds_sof), + .I1(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_pkt_ct_m1[5]), + .LO(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un3_pkt_ct_m1_axb_5_4324) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un3_pkt_ct_m1_axb_4.INIT = 4'h4; + LUT2_L com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un3_pkt_ct_m1_axb_4 ( + .I0(com_tlm_u_tlm_rx_ds_sof), + .I1(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_pkt_ct_m1[4]), + .LO(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un3_pkt_ct_m1_axb_4_4325) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un3_pkt_ct_m1_axb_3.INIT = 4'h4; + LUT2_L com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un3_pkt_ct_m1_axb_3 ( + .I0(com_tlm_u_tlm_rx_ds_sof), + .I1(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_pkt_ct_m1[3]), + .LO(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un3_pkt_ct_m1_axb_3_4326) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un3_pkt_ct_m1_axb_2.INIT = 4'h4; + LUT2_L com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un3_pkt_ct_m1_axb_2 ( + .I0(com_tlm_u_tlm_rx_ds_sof), + .I1(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_pkt_ct_m1[2]), + .LO(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un3_pkt_ct_m1_axb_2_4327) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un3_pkt_ct_m1_axb_1.INIT = 4'h4; + LUT2_L com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un3_pkt_ct_m1_axb_1 ( + .I0(com_tlm_u_tlm_rx_ds_sof), + .I1(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_pkt_ct_m1[1]), + .LO(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un3_pkt_ct_m1_axb_1_4328) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un8_pkt_ct_m1_i_0_.INIT = 4'hB; + LUT2_L com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un8_pkt_ct_m1_i_0_ ( + .I0(com_tlm_u_tlm_rx_ds_sof), + .I1(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_pkt_ct_m1[0]), + .LO(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un8_pkt_ct_m1_i[0]) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_vld_ct_1_axb_8.INIT = 8'h78; + LUT3_L com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_vld_ct_1_axb_8 ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_pop_4352), + .I1(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_vld_ct25_i), + .I2(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_vld_ct[8]), + .LO(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_vld_ct_1_axb_8_4329) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_vld_ct_1_axb_7.INIT = 8'h78; + LUT3_L com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_vld_ct_1_axb_7 ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_pop_4352), + .I1(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_vld_ct25_i), + .I2(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_vld_ct[7]), + .LO(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_vld_ct_1_axb_7_4330) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_vld_ct_1_axb_6.INIT = 16'h1DE2; + LUT4_L com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_vld_ct_1_axb_6 ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_pop_4352), + .I1(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_vld_ct25), + .I2(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un10_vld_ct[6]), + .I3(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_vld_ct[6]), + .LO(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_vld_ct_1_axb_6_4331) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_vld_ct_1_axb_5.INIT = 16'h1DE2; + LUT4_L com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_vld_ct_1_axb_5 ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_pop_4352), + .I1(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_vld_ct25), + .I2(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un10_vld_ct[5]), + .I3(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_vld_ct[5]), + .LO(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_vld_ct_1_axb_5_4332) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_vld_ct_1_axb_4.INIT = 16'h1DE2; + LUT4_L com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_vld_ct_1_axb_4 ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_pop_4352), + .I1(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_vld_ct25), + .I2(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un10_vld_ct[4]), + .I3(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_vld_ct[4]), + .LO(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_vld_ct_1_axb_4_4333) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_vld_ct_1_axb_3.INIT = 16'h1DE2; + LUT4_L com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_vld_ct_1_axb_3 ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_pop_4352), + .I1(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_vld_ct25), + .I2(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un10_vld_ct[3]), + .I3(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_vld_ct[3]), + .LO(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_vld_ct_1_axb_3_4334) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_vld_ct_1_axb_2.INIT = 16'h1DE2; + LUT4_L com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_vld_ct_1_axb_2 ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_pop_4352), + .I1(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_vld_ct25), + .I2(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un10_vld_ct[2]), + .I3(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_vld_ct[2]), + .LO(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_vld_ct_1_axb_2_4335) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_vld_ct_1_axb_1.INIT = 16'h1DE2; + LUT4_L com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_vld_ct_1_axb_1 ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_pop_4352), + .I1(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_vld_ct25), + .I2(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un10_vld_ct[1]), + .I3(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_vld_ct[1]), + .LO(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_vld_ct_1_axb_1_4336) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_waddr_p1_1_axb_9.INIT = 8'hD8; + LUT3_L com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_waddr_p1_1_axb_9 ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr16_4347), + .I1(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr_bkp[9]), + .I2(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr_p1[9]), + .LO(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_waddr_p1_1_axb_9_4337) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_waddr_p1_1_axb_8.INIT = 8'hD8; + LUT3_L com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_waddr_p1_1_axb_8 ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr16_4347), + .I1(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr_bkp[8]), + .I2(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr_p1[8]), + .LO(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_waddr_p1_1_axb_8_4338) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_waddr_p1_1_axb_7.INIT = 8'hD8; + LUT3_L com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_waddr_p1_1_axb_7 ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr16_4347), + .I1(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr_bkp[7]), + .I2(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr_p1[7]), + .LO(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_waddr_p1_1_axb_7_4339) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_waddr_p1_1_axb_6.INIT = 8'hD8; + LUT3_L com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_waddr_p1_1_axb_6 ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr16_4347), + .I1(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr_bkp[6]), + .I2(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr_p1[6]), + .LO(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_waddr_p1_1_axb_6_4340) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_waddr_p1_1_axb_5.INIT = 8'hD8; + LUT3_L com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_waddr_p1_1_axb_5 ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr16_4347), + .I1(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr_bkp[5]), + .I2(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr_p1[5]), + .LO(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_waddr_p1_1_axb_5_4341) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_waddr_p1_1_axb_4.INIT = 8'hD8; + LUT3_L com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_waddr_p1_1_axb_4 ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr16_4347), + .I1(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr_bkp[4]), + .I2(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr_p1[4]), + .LO(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_waddr_p1_1_axb_4_4342) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_waddr_p1_1_axb_3.INIT = 8'hD8; + LUT3_L com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_waddr_p1_1_axb_3 ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr16_4347), + .I1(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr_bkp[3]), + .I2(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr_p1[3]), + .LO(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_waddr_p1_1_axb_3_4343) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_waddr_p1_1_axb_2.INIT = 8'hD8; + LUT3_L com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_waddr_p1_1_axb_2 ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr16_4347), + .I1(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr_bkp[2]), + .I2(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr_p1[2]), + .LO(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_waddr_p1_1_axb_2_4344) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_waddr_p1_1_axb_1.INIT = 8'hD8; + LUT3_L com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_waddr_p1_1_axb_1 ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr16_4347), + .I1(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr_bkp[1]), + .I2(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr_p1[1]), + .LO(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_waddr_p1_1_axb_1_4345) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_waddr_p1_1_axb_0.INIT = 8'hD8; + LUT3_L com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_waddr_p1_1_axb_0 ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr16_4347), + .I1(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr_bkp[0]), + .I2(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr_p1[0]), + .LO(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_waddr_p1_1_axb_0_4346) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_N_10762_i.INIT = 8'hAE; + LUT3 com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_N_10762_i ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_push), + .I1(plm_link_up_1), + .I2(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_overflow_1_i), + .O(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_N_10762_i_4348) + ); + INV com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_standard_vld_ct_vld_ct25_i ( + .I(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_vld_ct25), + .O(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_vld_ct25_i) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_raddr_qxu_0_0_.INIT = 4'h2; + LUT1_L com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_raddr_qxu_0_0_ ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_raddr[0]), + .LO(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_raddr_qxu[0]) + ); + MULT_AND com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_vld_ct_1_cry_6_ma ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_vld_ct[6]), + .I1(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_VCC_4350), + .LO(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_vld_ct_1_cry_6_ma_4349) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_raddr_qxu_0_9_.INIT = 4'h2; + LUT1_L com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_raddr_qxu_0_9_ ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_raddr[9]), + .LO(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_raddr_qxu[9]) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_raddr_qxu_0_8_.INIT = 4'h2; + LUT1_L com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_raddr_qxu_0_8_ ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_raddr[8]), + .LO(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_raddr_qxu[8]) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_raddr_qxu_0_7_.INIT = 4'h2; + LUT1_L com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_raddr_qxu_0_7_ ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_raddr[7]), + .LO(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_raddr_qxu[7]) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_raddr_qxu_0_6_.INIT = 4'h2; + LUT1_L com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_raddr_qxu_0_6_ ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_raddr[6]), + .LO(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_raddr_qxu[6]) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_raddr_qxu_0_5_.INIT = 4'h2; + LUT1_L com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_raddr_qxu_0_5_ ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_raddr[5]), + .LO(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_raddr_qxu[5]) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_raddr_qxu_0_4_.INIT = 4'h2; + LUT1_L com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_raddr_qxu_0_4_ ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_raddr[4]), + .LO(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_raddr_qxu[4]) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_raddr_qxu_0_3_.INIT = 4'h2; + LUT1_L com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_raddr_qxu_0_3_ ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_raddr[3]), + .LO(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_raddr_qxu[3]) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_raddr_qxu_0_2_.INIT = 4'h2; + LUT1_L com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_raddr_qxu_0_2_ ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_raddr[2]), + .LO(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_raddr_qxu[2]) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_raddr_qxu_0_1_.INIT = 4'h2; + LUT1_L com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_raddr_qxu_0_1_ ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_raddr[1]), + .LO(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_raddr_qxu[1]) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_raddr_s_0_.INIT = 4'h1; + LUT1_L com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_raddr_s_0_ ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_raddr_qxu[0]), + .LO(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_raddr_s[0]) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un8_pkt_ct_0_.INIT = 4'h1; + LUT2_L com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un8_pkt_ct_0_ ( + .I0(com_tlm_u_tlm_rx_ds_sof), + .I1(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_pkt_ct[0]), + .LO(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un8_pkt_ct[0]) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_vld_ct_1_axb_9.INIT = 8'hA6; + LUT3_L com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_vld_ct_1_axb_9 ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_vld_ct[9]), + .I1(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_pop_4352), + .I2(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_vld_ct25), + .LO(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un1_vld_ct_1_axb_9_4351) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un3_pkt_ct_m1_axb_0.INIT = 4'h4; + LUT2 com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un3_pkt_ct_m1_axb_0 ( + .I0(com_tlm_u_tlm_rx_ds_sof), + .I1(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_pkt_ct_m1[0]), + .O(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un3_pkt_ct_m1_axb_0_4353) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un3_pkt_ct_axb_0.INIT = 4'hE; + LUT2 com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un3_pkt_ct_axb_0 ( + .I0(com_tlm_u_tlm_rx_ds_sof), + .I1(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_pkt_ct[0]), + .O(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_un3_pkt_ct_axb_0_4354) + ); + VCC com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_queue_ram_VCC ( + .P(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_queue_ram_VCC_4355) + ); + GND com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_queue_ram_GND ( + .G(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_queue_ram_GND_4356) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_queue_ram_ram_row_0__block_ram_0__ram1024x18_bram.WRITE_MODE_A = "NO_CHANGE"; + RAMB16_S18_S18 com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_queue_ram_ram_row_0__block_ram_0__ram1024x18_bram ( + .ENA(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_queue_ram_VCC_4355), + .ENB(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_queue_ram_N_58351_i_4357), + .SSRA(com_reset_i_q), + .SSRB(com_reset_i_q), + .WEA(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_push), + .WEB(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_queue_ram_GND_4356), + .CLKA(NlwRenamedSig_OI_trn_clk), + .CLKB(NlwRenamedSig_OI_trn_clk), + .ADDRA({com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr[9], com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr[8], +com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr[7], com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr[6], +com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr[5], com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr[4], +com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr[3], com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr[2], +com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr[1], com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr[0]}), + .DOPA({NLW_com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_queue_ram_ram_row_0__block_ram_0__ram1024x18_bram_DOPA_1__UNCONNECTED, +NLW_com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_queue_ram_ram_row_0__block_ram_0__ram1024x18_bram_DOPA_0__UNCONNECTED}), + .ADDRB({com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_raddr[9], com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_raddr[8], +com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_raddr[7], com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_raddr[6], +com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_raddr[5], com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_raddr[4], +com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_raddr[3], com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_raddr[2], +com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_raddr[1], com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_raddr[0]}), + .DOPB({com_tlm_u_tlm_rx_vc0_fifo_data_oqr_17_, com_tlm_u_tlm_rx_vc0_fifo_data_oqr_16_}), + .DIA({com_tlm_u_tlm_rx_ds_d[15], com_tlm_u_tlm_rx_ds_d[14], com_tlm_u_tlm_rx_ds_d[13], com_tlm_u_tlm_rx_ds_d[12], com_tlm_u_tlm_rx_ds_d[11], +com_tlm_u_tlm_rx_ds_d[10], com_tlm_u_tlm_rx_ds_d[9], com_tlm_u_tlm_rx_ds_d[8], com_tlm_u_tlm_rx_ds_d[7], com_tlm_u_tlm_rx_ds_d[6], +com_tlm_u_tlm_rx_ds_d[5], com_tlm_u_tlm_rx_ds_d[4], com_tlm_u_tlm_rx_ds_d[3], com_tlm_u_tlm_rx_ds_d[2], com_tlm_u_tlm_rx_ds_d[1], +com_tlm_u_tlm_rx_ds_d[0]}), + .DIB({com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_queue_ram_GND_4356, com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_queue_ram_GND_4356, +com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_queue_ram_GND_4356, com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_queue_ram_GND_4356, +com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_queue_ram_GND_4356, com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_queue_ram_GND_4356, +com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_queue_ram_GND_4356, com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_queue_ram_GND_4356, +com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_queue_ram_GND_4356, com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_queue_ram_GND_4356, +com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_queue_ram_GND_4356, com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_queue_ram_GND_4356, +com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_queue_ram_GND_4356, com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_queue_ram_GND_4356, +com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_queue_ram_GND_4356, com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_queue_ram_GND_4356}), + .DOA({NLW_com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_queue_ram_ram_row_0__block_ram_0__ram1024x18_bram_DOA_15__UNCONNECTED, +NLW_com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_queue_ram_ram_row_0__block_ram_0__ram1024x18_bram_DOA_14__UNCONNECTED, +NLW_com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_queue_ram_ram_row_0__block_ram_0__ram1024x18_bram_DOA_13__UNCONNECTED, +NLW_com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_queue_ram_ram_row_0__block_ram_0__ram1024x18_bram_DOA_12__UNCONNECTED, +NLW_com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_queue_ram_ram_row_0__block_ram_0__ram1024x18_bram_DOA_11__UNCONNECTED, +NLW_com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_queue_ram_ram_row_0__block_ram_0__ram1024x18_bram_DOA_10__UNCONNECTED, +NLW_com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_queue_ram_ram_row_0__block_ram_0__ram1024x18_bram_DOA_9__UNCONNECTED, +NLW_com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_queue_ram_ram_row_0__block_ram_0__ram1024x18_bram_DOA_8__UNCONNECTED, +NLW_com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_queue_ram_ram_row_0__block_ram_0__ram1024x18_bram_DOA_7__UNCONNECTED, +NLW_com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_queue_ram_ram_row_0__block_ram_0__ram1024x18_bram_DOA_6__UNCONNECTED, +NLW_com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_queue_ram_ram_row_0__block_ram_0__ram1024x18_bram_DOA_5__UNCONNECTED, +NLW_com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_queue_ram_ram_row_0__block_ram_0__ram1024x18_bram_DOA_4__UNCONNECTED, +NLW_com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_queue_ram_ram_row_0__block_ram_0__ram1024x18_bram_DOA_3__UNCONNECTED, +NLW_com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_queue_ram_ram_row_0__block_ram_0__ram1024x18_bram_DOA_2__UNCONNECTED, +NLW_com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_queue_ram_ram_row_0__block_ram_0__ram1024x18_bram_DOA_1__UNCONNECTED, +NLW_com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_queue_ram_ram_row_0__block_ram_0__ram1024x18_bram_DOA_0__UNCONNECTED}), + .DOB({com_tlm_u_tlm_rx_vc0_fifo_data_oqr_15_, com_tlm_u_tlm_rx_vc0_fifo_data_oqr_14_, com_tlm_u_tlm_rx_vc0_fifo_data_oqr_13_, +com_tlm_u_tlm_rx_vc0_fifo_data_oqr_12_, com_tlm_u_tlm_rx_vc0_fifo_data_oqr_11_, com_tlm_u_tlm_rx_vc0_fifo_data_oqr_10_, +com_tlm_u_tlm_rx_vc0_fifo_data_oqr_9_, com_tlm_u_tlm_rx_vc0_fifo_data_oqr_8_, com_tlm_u_tlm_rx_vc0_fifo_data_oqr_7_, +com_tlm_u_tlm_rx_vc0_fifo_data_oqr_6_, com_tlm_u_tlm_rx_vc0_fifo_data_oqr_5_, com_tlm_u_tlm_rx_vc0_fifo_data_oqr_4_, +com_tlm_u_tlm_rx_vc0_fifo_data_oqr_3_, com_tlm_u_tlm_rx_vc0_fifo_data_oqr_2_, com_tlm_u_tlm_rx_vc0_fifo_data_oqr_1_, +com_tlm_u_tlm_rx_vc0_fifo_data_oqr_0_}), + .DIPA({com_tlm_u_tlm_rx_ds_d[17], com_tlm_u_tlm_rx_ds_d[16]}), + .DIPB({com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_queue_ram_GND_4356, com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_queue_ram_GND_4356}) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_queue_ram_ram_row_0__block_ram_1__ram1024x18_bram.WRITE_MODE_A = "NO_CHANGE"; + RAMB16_S18_S18 com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_queue_ram_ram_row_0__block_ram_1__ram1024x18_bram ( + .ENA(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_queue_ram_VCC_4355), + .ENB(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_queue_ram_N_58351_i_4357), + .SSRA(com_reset_i_q), + .SSRB(com_reset_i_q), + .WEA(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_push), + .WEB(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_queue_ram_GND_4356), + .CLKA(NlwRenamedSig_OI_trn_clk), + .CLKB(NlwRenamedSig_OI_trn_clk), + .ADDRA({com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr[9], com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr[8], +com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr[7], com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr[6], +com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr[5], com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr[4], +com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr[3], com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr[2], +com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr[1], com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr[0]}), + .DOPA({NLW_com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_queue_ram_ram_row_0__block_ram_1__ram1024x18_bram_DOPA_1__UNCONNECTED, +NLW_com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_queue_ram_ram_row_0__block_ram_1__ram1024x18_bram_DOPA_0__UNCONNECTED}), + .ADDRB({com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_raddr[9], com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_raddr[8], +com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_raddr[7], com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_raddr[6], +com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_raddr[5], com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_raddr[4], +com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_raddr[3], com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_raddr[2], +com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_raddr[1], com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_raddr[0]}), + .DOPB({com_tlm_u_tlm_rx_vc0_fifo_data_oqr_35_, com_tlm_u_tlm_rx_vc0_fifo_data_oqr_34_}), + .DIA({com_tlm_u_tlm_rx_ds_d[33], com_tlm_u_tlm_rx_ds_d[32], com_tlm_u_tlm_rx_ds_d[31], com_tlm_u_tlm_rx_ds_d[30], com_tlm_u_tlm_rx_ds_d[29], +com_tlm_u_tlm_rx_ds_d[28], com_tlm_u_tlm_rx_ds_d[27], com_tlm_u_tlm_rx_ds_d[26], com_tlm_u_tlm_rx_ds_d[25], com_tlm_u_tlm_rx_ds_d[24], +com_tlm_u_tlm_rx_ds_d[23], com_tlm_u_tlm_rx_ds_d[22], com_tlm_u_tlm_rx_ds_d[21], com_tlm_u_tlm_rx_ds_d[20], com_tlm_u_tlm_rx_ds_d[19], +com_tlm_u_tlm_rx_ds_d[18]}), + .DIB({com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_queue_ram_GND_4356, com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_queue_ram_GND_4356, +com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_queue_ram_GND_4356, com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_queue_ram_GND_4356, +com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_queue_ram_GND_4356, com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_queue_ram_GND_4356, +com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_queue_ram_GND_4356, com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_queue_ram_GND_4356, +com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_queue_ram_GND_4356, com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_queue_ram_GND_4356, +com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_queue_ram_GND_4356, com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_queue_ram_GND_4356, +com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_queue_ram_GND_4356, com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_queue_ram_GND_4356, +com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_queue_ram_GND_4356, com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_queue_ram_GND_4356}), + .DOA({NLW_com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_queue_ram_ram_row_0__block_ram_1__ram1024x18_bram_DOA_15__UNCONNECTED, +NLW_com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_queue_ram_ram_row_0__block_ram_1__ram1024x18_bram_DOA_14__UNCONNECTED, +NLW_com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_queue_ram_ram_row_0__block_ram_1__ram1024x18_bram_DOA_13__UNCONNECTED, +NLW_com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_queue_ram_ram_row_0__block_ram_1__ram1024x18_bram_DOA_12__UNCONNECTED, +NLW_com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_queue_ram_ram_row_0__block_ram_1__ram1024x18_bram_DOA_11__UNCONNECTED, +NLW_com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_queue_ram_ram_row_0__block_ram_1__ram1024x18_bram_DOA_10__UNCONNECTED, +NLW_com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_queue_ram_ram_row_0__block_ram_1__ram1024x18_bram_DOA_9__UNCONNECTED, +NLW_com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_queue_ram_ram_row_0__block_ram_1__ram1024x18_bram_DOA_8__UNCONNECTED, +NLW_com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_queue_ram_ram_row_0__block_ram_1__ram1024x18_bram_DOA_7__UNCONNECTED, +NLW_com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_queue_ram_ram_row_0__block_ram_1__ram1024x18_bram_DOA_6__UNCONNECTED, +NLW_com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_queue_ram_ram_row_0__block_ram_1__ram1024x18_bram_DOA_5__UNCONNECTED, +NLW_com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_queue_ram_ram_row_0__block_ram_1__ram1024x18_bram_DOA_4__UNCONNECTED, +NLW_com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_queue_ram_ram_row_0__block_ram_1__ram1024x18_bram_DOA_3__UNCONNECTED, +NLW_com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_queue_ram_ram_row_0__block_ram_1__ram1024x18_bram_DOA_2__UNCONNECTED, +NLW_com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_queue_ram_ram_row_0__block_ram_1__ram1024x18_bram_DOA_1__UNCONNECTED, +NLW_com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_queue_ram_ram_row_0__block_ram_1__ram1024x18_bram_DOA_0__UNCONNECTED}), + .DOB({com_tlm_u_tlm_rx_vc0_fifo_data_oqr_33_, com_tlm_u_tlm_rx_vc0_fifo_data_oqr_32_, com_tlm_u_tlm_rx_vc0_fifo_data_oqr_31_, +com_tlm_u_tlm_rx_vc0_fifo_data_oqr_30_, com_tlm_u_tlm_rx_vc0_fifo_data_oqr_29_, com_tlm_u_tlm_rx_vc0_fifo_data_oqr_28_, +com_tlm_u_tlm_rx_vc0_fifo_data_oqr_27_, com_tlm_u_tlm_rx_vc0_fifo_data_oqr_26_, com_tlm_u_tlm_rx_vc0_fifo_data_oqr_25_, +com_tlm_u_tlm_rx_vc0_fifo_data_oqr_24_, com_tlm_u_tlm_rx_vc0_fifo_data_oqr_23_, com_tlm_u_tlm_rx_vc0_fifo_data_oqr_22_, +com_tlm_u_tlm_rx_vc0_fifo_data_oqr_21_, com_tlm_u_tlm_rx_vc0_fifo_data_oqr_20_, com_tlm_u_tlm_rx_vc0_fifo_data_oqr_19_, +com_tlm_u_tlm_rx_vc0_fifo_data_oqr_18_}), + .DIPA({com_tlm_u_tlm_rx_ds_d[35], com_tlm_u_tlm_rx_ds_d[34]}), + .DIPB({com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_queue_ram_GND_4356, com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_queue_ram_GND_4356}) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_queue_ram_ram_row_0__block_ram_2__ram1024x18_bram.WRITE_MODE_A = "NO_CHANGE"; + RAMB16_S18_S18 com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_queue_ram_ram_row_0__block_ram_2__ram1024x18_bram ( + .ENA(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_queue_ram_VCC_4355), + .ENB(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_queue_ram_N_58351_i_4357), + .SSRA(com_reset_i_q), + .SSRB(com_reset_i_q), + .WEA(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_push), + .WEB(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_queue_ram_GND_4356), + .CLKA(NlwRenamedSig_OI_trn_clk), + .CLKB(NlwRenamedSig_OI_trn_clk), + .ADDRA({com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr[9], com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr[8], +com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr[7], com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr[6], +com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr[5], com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr[4], +com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr[3], com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr[2], +com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr[1], com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr[0]}), + .DOPA({NLW_com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_queue_ram_ram_row_0__block_ram_2__ram1024x18_bram_DOPA_1__UNCONNECTED, +NLW_com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_queue_ram_ram_row_0__block_ram_2__ram1024x18_bram_DOPA_0__UNCONNECTED}), + .ADDRB({com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_raddr[9], com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_raddr[8], +com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_raddr[7], com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_raddr[6], +com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_raddr[5], com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_raddr[4], +com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_raddr[3], com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_raddr[2], +com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_raddr[1], com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_raddr[0]}), + .DOPB({com_tlm_u_tlm_rx_vc0_fifo_data_oqr_53_, com_tlm_u_tlm_rx_vc0_fifo_data_oqr_52_}), + .DIA({com_tlm_u_tlm_rx_ds_d[51], com_tlm_u_tlm_rx_ds_d[50], com_tlm_u_tlm_rx_ds_d[49], com_tlm_u_tlm_rx_ds_d[48], com_tlm_u_tlm_rx_ds_d[47], +com_tlm_u_tlm_rx_ds_d[46], com_tlm_u_tlm_rx_ds_d[45], com_tlm_u_tlm_rx_ds_d[44], com_tlm_u_tlm_rx_ds_d[43], com_tlm_u_tlm_rx_ds_d[42], +com_tlm_u_tlm_rx_ds_d[41], com_tlm_u_tlm_rx_ds_d[40], com_tlm_u_tlm_rx_ds_d[39], com_tlm_u_tlm_rx_ds_d[38], com_tlm_u_tlm_rx_ds_d[37], +com_tlm_u_tlm_rx_ds_d[36]}), + .DIB({com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_queue_ram_GND_4356, com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_queue_ram_GND_4356, +com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_queue_ram_GND_4356, com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_queue_ram_GND_4356, +com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_queue_ram_GND_4356, com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_queue_ram_GND_4356, +com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_queue_ram_GND_4356, com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_queue_ram_GND_4356, +com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_queue_ram_GND_4356, com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_queue_ram_GND_4356, +com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_queue_ram_GND_4356, com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_queue_ram_GND_4356, +com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_queue_ram_GND_4356, com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_queue_ram_GND_4356, +com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_queue_ram_GND_4356, com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_queue_ram_GND_4356}), + .DOA({NLW_com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_queue_ram_ram_row_0__block_ram_2__ram1024x18_bram_DOA_15__UNCONNECTED, +NLW_com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_queue_ram_ram_row_0__block_ram_2__ram1024x18_bram_DOA_14__UNCONNECTED, +NLW_com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_queue_ram_ram_row_0__block_ram_2__ram1024x18_bram_DOA_13__UNCONNECTED, +NLW_com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_queue_ram_ram_row_0__block_ram_2__ram1024x18_bram_DOA_12__UNCONNECTED, +NLW_com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_queue_ram_ram_row_0__block_ram_2__ram1024x18_bram_DOA_11__UNCONNECTED, +NLW_com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_queue_ram_ram_row_0__block_ram_2__ram1024x18_bram_DOA_10__UNCONNECTED, +NLW_com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_queue_ram_ram_row_0__block_ram_2__ram1024x18_bram_DOA_9__UNCONNECTED, +NLW_com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_queue_ram_ram_row_0__block_ram_2__ram1024x18_bram_DOA_8__UNCONNECTED, +NLW_com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_queue_ram_ram_row_0__block_ram_2__ram1024x18_bram_DOA_7__UNCONNECTED, +NLW_com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_queue_ram_ram_row_0__block_ram_2__ram1024x18_bram_DOA_6__UNCONNECTED, +NLW_com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_queue_ram_ram_row_0__block_ram_2__ram1024x18_bram_DOA_5__UNCONNECTED, +NLW_com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_queue_ram_ram_row_0__block_ram_2__ram1024x18_bram_DOA_4__UNCONNECTED, +NLW_com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_queue_ram_ram_row_0__block_ram_2__ram1024x18_bram_DOA_3__UNCONNECTED, +NLW_com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_queue_ram_ram_row_0__block_ram_2__ram1024x18_bram_DOA_2__UNCONNECTED, +NLW_com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_queue_ram_ram_row_0__block_ram_2__ram1024x18_bram_DOA_1__UNCONNECTED, +NLW_com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_queue_ram_ram_row_0__block_ram_2__ram1024x18_bram_DOA_0__UNCONNECTED}), + .DOB({com_tlm_u_tlm_rx_vc0_fifo_data_oqr_51_, com_tlm_u_tlm_rx_vc0_fifo_data_oqr_50_, com_tlm_u_tlm_rx_vc0_fifo_data_oqr_49_, +com_tlm_u_tlm_rx_vc0_fifo_data_oqr_48_, com_tlm_u_tlm_rx_vc0_fifo_data_oqr_47_, com_tlm_u_tlm_rx_vc0_fifo_ep_oqr, +com_tlm_u_tlm_rx_vc0_fifo_data_oqr_45_, com_tlm_u_tlm_rx_vc0_fifo_data_oqr_44_, com_tlm_u_tlm_rx_vc0_fifo_data_oqr_43_, +com_tlm_u_tlm_rx_vc0_fifo_data_oqr_42_, com_tlm_u_tlm_rx_vc0_fifo_data_oqr_41_, com_tlm_u_tlm_rx_vc0_fifo_data_oqr_40_, +com_tlm_u_tlm_rx_vc0_fifo_data_oqr_39_, com_tlm_u_tlm_rx_vc0_fifo_data_oqr_38_, com_tlm_u_tlm_rx_vc0_fifo_data_oqr_37_, +com_tlm_u_tlm_rx_vc0_fifo_data_oqr_36_}), + .DIPA({com_tlm_u_tlm_rx_ds_d[53], com_tlm_u_tlm_rx_ds_d[52]}), + .DIPB({com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_queue_ram_GND_4356, com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_queue_ram_GND_4356}) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_queue_ram_ram_row_0__block_ram_3__ram1024x18_bram.WRITE_MODE_A = "NO_CHANGE"; + RAMB16_S18_S18 com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_queue_ram_ram_row_0__block_ram_3__ram1024x18_bram ( + .ENA(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_queue_ram_VCC_4355), + .ENB(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_queue_ram_N_58351_i_4357), + .SSRA(com_reset_i_q), + .SSRB(com_reset_i_q), + .WEA(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_push), + .WEB(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_queue_ram_GND_4356), + .CLKA(NlwRenamedSig_OI_trn_clk), + .CLKB(NlwRenamedSig_OI_trn_clk), + .ADDRA({com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr[9], com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr[8], +com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr[7], com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr[6], +com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr[5], com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr[4], +com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr[3], com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr[2], +com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr[1], com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_waddr[0]}), + .DOPA({NLW_com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_queue_ram_ram_row_0__block_ram_3__ram1024x18_bram_DOPA_1__UNCONNECTED, +NLW_com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_queue_ram_ram_row_0__block_ram_3__ram1024x18_bram_DOPA_0__UNCONNECTED}), + .ADDRB({com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_raddr[9], com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_raddr[8], +com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_raddr[7], com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_raddr[6], +com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_raddr[5], com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_raddr[4], +com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_raddr[3], com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_raddr[2], +com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_raddr[1], com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_raddr[0]}), + .DOPB({NLW_com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_queue_ram_ram_row_0__block_ram_3__ram1024x18_bram_DOPB_1__UNCONNECTED, +NLW_com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_queue_ram_ram_row_0__block_ram_3__ram1024x18_bram_DOPB_0__UNCONNECTED}), + .DIA({com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_queue_ram_GND_4356, com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_queue_ram_GND_4356, +com_tlm_u_tlm_rx_ds_rem, com_tlm_u_tlm_rx_ds_cpl, com_tlm_u_tlm_rx_ds_eof, com_tlm_u_tlm_rx_ds_sof, com_tlm_u_tlm_rx_ds_d[63], +com_tlm_u_tlm_rx_ds_d[62], com_tlm_u_tlm_rx_ds_d[61], com_tlm_u_tlm_rx_ds_d[60], com_tlm_u_tlm_rx_ds_d[59], com_tlm_u_tlm_rx_ds_d[58], +com_tlm_u_tlm_rx_ds_d[57], com_tlm_u_tlm_rx_ds_d[56], com_tlm_u_tlm_rx_ds_d[55], com_tlm_u_tlm_rx_ds_d[54]}), + .DIB({com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_queue_ram_GND_4356, com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_queue_ram_GND_4356, +com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_queue_ram_GND_4356, com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_queue_ram_GND_4356, +com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_queue_ram_GND_4356, com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_queue_ram_GND_4356, +com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_queue_ram_GND_4356, com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_queue_ram_GND_4356, +com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_queue_ram_GND_4356, com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_queue_ram_GND_4356, +com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_queue_ram_GND_4356, com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_queue_ram_GND_4356, +com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_queue_ram_GND_4356, com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_queue_ram_GND_4356, +com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_queue_ram_GND_4356, com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_queue_ram_GND_4356}), + .DOA({NLW_com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_queue_ram_ram_row_0__block_ram_3__ram1024x18_bram_DOA_15__UNCONNECTED, +NLW_com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_queue_ram_ram_row_0__block_ram_3__ram1024x18_bram_DOA_14__UNCONNECTED, +NLW_com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_queue_ram_ram_row_0__block_ram_3__ram1024x18_bram_DOA_13__UNCONNECTED, +NLW_com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_queue_ram_ram_row_0__block_ram_3__ram1024x18_bram_DOA_12__UNCONNECTED, +NLW_com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_queue_ram_ram_row_0__block_ram_3__ram1024x18_bram_DOA_11__UNCONNECTED, +NLW_com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_queue_ram_ram_row_0__block_ram_3__ram1024x18_bram_DOA_10__UNCONNECTED, +NLW_com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_queue_ram_ram_row_0__block_ram_3__ram1024x18_bram_DOA_9__UNCONNECTED, +NLW_com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_queue_ram_ram_row_0__block_ram_3__ram1024x18_bram_DOA_8__UNCONNECTED, +NLW_com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_queue_ram_ram_row_0__block_ram_3__ram1024x18_bram_DOA_7__UNCONNECTED, +NLW_com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_queue_ram_ram_row_0__block_ram_3__ram1024x18_bram_DOA_6__UNCONNECTED, +NLW_com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_queue_ram_ram_row_0__block_ram_3__ram1024x18_bram_DOA_5__UNCONNECTED, +NLW_com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_queue_ram_ram_row_0__block_ram_3__ram1024x18_bram_DOA_4__UNCONNECTED, +NLW_com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_queue_ram_ram_row_0__block_ram_3__ram1024x18_bram_DOA_3__UNCONNECTED, +NLW_com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_queue_ram_ram_row_0__block_ram_3__ram1024x18_bram_DOA_2__UNCONNECTED, +NLW_com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_queue_ram_ram_row_0__block_ram_3__ram1024x18_bram_DOA_1__UNCONNECTED, +NLW_com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_queue_ram_ram_row_0__block_ram_3__ram1024x18_bram_DOA_0__UNCONNECTED}), + .DOB({NLW_com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_queue_ram_ram_row_0__block_ram_3__ram1024x18_bram_DOB_15__UNCONNECTED, +NLW_com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_queue_ram_ram_row_0__block_ram_3__ram1024x18_bram_DOB_14__UNCONNECTED, +com_tlm_u_tlm_rx_vc0_fifo_ram_dout[67], com_tlm_u_tlm_rx_vc0_fifo_ram_dout[66], com_tlm_u_tlm_rx_vc0_fifo_ram_dout[65], +com_tlm_u_tlm_rx_vc0_fifo_ram_dout[64], com_tlm_u_tlm_rx_vc0_fifo_data_oqr_63_, com_tlm_u_tlm_rx_vc0_fifo_data_oqr_62_, +com_tlm_u_tlm_rx_vc0_fifo_data_oqr_61_, com_tlm_u_tlm_rx_vc0_fifo_data_oqr_60_, com_tlm_u_tlm_rx_vc0_fifo_data_oqr_59_, +com_tlm_u_tlm_rx_vc0_fifo_data_oqr_58_, com_tlm_u_tlm_rx_vc0_fifo_data_oqr_57_, com_tlm_u_tlm_rx_vc0_fifo_data_oqr_56_, +com_tlm_u_tlm_rx_vc0_fifo_data_oqr_55_, com_tlm_u_tlm_rx_vc0_fifo_data_oqr_54_}), + .DIPA({com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_queue_ram_GND_4356, com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_queue_ram_GND_4356}), + .DIPB({com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_queue_ram_GND_4356, com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_queue_ram_GND_4356}) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_queue_ram_N_58351_i.INIT = 4'hE; + LUT2 com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_queue_ram_N_58351_i ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_pop_4352), + .I1(com_reset_i_q), + .O(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_main_fifo_queue_ram_N_58351_i_4357) + ); + SRLC16E com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_srlrow_3__srlcol_4__srlinst ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_wen_aux_oq_4147), + .D(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_shift_in[31]), + .Q(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_shift_tap[31]), + .CLK(NlwRenamedSig_OI_trn_clk), + .Q15(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_shift_in[40]), + .A0(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_lo[0]), + .A1(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_lo[1]), + .A2(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_lo[2]), + .A3(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_lo[3]) + ); + SRLC16E com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_srlrow_2__srlcol_0__srlinst ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_wen_aux_oq_4147), + .D(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_shift_in[18]), + .Q(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_shift_tap[18]), + .CLK(NlwRenamedSig_OI_trn_clk), + .Q15(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_shift_in[27]), + .A0(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_lo[0]), + .A1(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_lo[1]), + .A2(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_lo[2]), + .A3(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_lo[3]) + ); + SRLC16E com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_srlrow_1__srlcol_6__srlinst ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_wen_aux_oq_4147), + .D(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_shift_in[15]), + .Q(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_shift_tap[15]), + .CLK(NlwRenamedSig_OI_trn_clk), + .Q15(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_shift_in[24]), + .A0(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_lo[0]), + .A1(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_lo[1]), + .A2(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_lo[2]), + .A3(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_lo[3]) + ); + SRLC16E com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_srlrow_4__srlcol_8__srlinst ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_wen_aux_oq_4147), + .D(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_shift_in[44]), + .Q(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_shift_tap[44]), + .CLK(NlwRenamedSig_OI_trn_clk), + .Q15(NLW_com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_srlrow_4__srlcol_8__srlinst_Q15_UNCONNECTED), + .A0(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_lo[0]), + .A1(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_lo[1]), + .A2(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_lo[2]), + .A3(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_lo[3]) + ); + SRLC16E com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_srlrow_4__srlcol_5__srlinst ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_wen_aux_oq_4147), + .D(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_shift_in[41]), + .Q(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_shift_tap[41]), + .CLK(NlwRenamedSig_OI_trn_clk), + .Q15(NLW_com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_srlrow_4__srlcol_5__srlinst_Q15_UNCONNECTED), + .A0(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_lo[0]), + .A1(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_lo[1]), + .A2(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_lo[2]), + .A3(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_lo[3]) + ); + SRLC16E com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_srlrow_4__srlcol_6__srlinst ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_wen_aux_oq_4147), + .D(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_shift_in[42]), + .Q(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_shift_tap[42]), + .CLK(NlwRenamedSig_OI_trn_clk), + .Q15(NLW_com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_srlrow_4__srlcol_6__srlinst_Q15_UNCONNECTED), + .A0(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_lo[0]), + .A1(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_lo[1]), + .A2(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_lo[2]), + .A3(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_lo[3]) + ); + SRLC16E com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_srlrow_4__srlcol_7__srlinst ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_wen_aux_oq_4147), + .D(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_shift_in[43]), + .Q(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_shift_tap[43]), + .CLK(NlwRenamedSig_OI_trn_clk), + .Q15(NLW_com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_srlrow_4__srlcol_7__srlinst_Q15_UNCONNECTED), + .A0(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_lo[0]), + .A1(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_lo[1]), + .A2(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_lo[2]), + .A3(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_lo[3]) + ); + SRLC16E com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_srlrow_4__srlcol_4__srlinst ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_wen_aux_oq_4147), + .D(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_shift_in[40]), + .Q(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_shift_tap[40]), + .CLK(NlwRenamedSig_OI_trn_clk), + .Q15(NLW_com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_srlrow_4__srlcol_4__srlinst_Q15_UNCONNECTED), + .A0(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_lo[0]), + .A1(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_lo[1]), + .A2(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_lo[2]), + .A3(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_lo[3]) + ); + SRLC16E com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_srlrow_1__srlcol_7__srlinst ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_wen_aux_oq_4147), + .D(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_shift_in[16]), + .Q(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_shift_tap[16]), + .CLK(NlwRenamedSig_OI_trn_clk), + .Q15(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_shift_in[25]), + .A0(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_lo[0]), + .A1(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_lo[1]), + .A2(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_lo[2]), + .A3(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_lo[3]) + ); + SRLC16E com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_srlrow_0__srlcol_3__srlinst ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_wen_aux_oq_4147), + .D(com_tlm_u_tlm_rx_vc0_fifo_aux_in[3]), + .Q(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_shift_tap[3]), + .CLK(NlwRenamedSig_OI_trn_clk), + .Q15(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_shift_in[12]), + .A0(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_lo[0]), + .A1(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_lo[1]), + .A2(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_lo[2]), + .A3(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_lo[3]) + ); + SRLC16E com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_srlrow_3__srlcol_3__srlinst ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_wen_aux_oq_4147), + .D(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_shift_in[30]), + .Q(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_shift_tap[30]), + .CLK(NlwRenamedSig_OI_trn_clk), + .Q15(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_shift_in[39]), + .A0(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_lo[0]), + .A1(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_lo[1]), + .A2(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_lo[2]), + .A3(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_lo[3]) + ); + SRLC16E com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_srlrow_1__srlcol_8__srlinst ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_wen_aux_oq_4147), + .D(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_shift_in[17]), + .Q(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_shift_tap[17]), + .CLK(NlwRenamedSig_OI_trn_clk), + .Q15(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_shift_in[26]), + .A0(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_lo[0]), + .A1(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_lo[1]), + .A2(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_lo[2]), + .A3(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_lo[3]) + ); + SRLC16E com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_srlrow_0__srlcol_4__srlinst ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_wen_aux_oq_4147), + .D(com_tlm_u_tlm_rx_vc0_fifo_aux_in[4]), + .Q(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_shift_tap[4]), + .CLK(NlwRenamedSig_OI_trn_clk), + .Q15(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_shift_in[13]), + .A0(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_lo[0]), + .A1(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_lo[1]), + .A2(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_lo[2]), + .A3(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_lo[3]) + ); + SRLC16E com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_srlrow_3__srlcol_2__srlinst ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_wen_aux_oq_4147), + .D(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_shift_in[29]), + .Q(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_shift_tap[29]), + .CLK(NlwRenamedSig_OI_trn_clk), + .Q15(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_shift_in[38]), + .A0(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_lo[0]), + .A1(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_lo[1]), + .A2(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_lo[2]), + .A3(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_lo[3]) + ); + SRLC16E com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_srlrow_0__srlcol_2__srlinst ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_wen_aux_oq_4147), + .D(com_tlm_u_tlm_rx_vc0_fifo_aux_in[2]), + .Q(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_shift_tap[2]), + .CLK(NlwRenamedSig_OI_trn_clk), + .Q15(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_shift_in[11]), + .A0(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_lo[0]), + .A1(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_lo[1]), + .A2(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_lo[2]), + .A3(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_lo[3]) + ); + SRLC16E com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_srlrow_0__srlcol_5__srlinst ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_wen_aux_oq_4147), + .D(com_tlm_u_tlm_rx_vc0_fifo_aux_in[5]), + .Q(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_shift_tap[5]), + .CLK(NlwRenamedSig_OI_trn_clk), + .Q15(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_shift_in[14]), + .A0(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_lo[0]), + .A1(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_lo[1]), + .A2(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_lo[2]), + .A3(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_lo[3]) + ); + SRLC16E com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_srlrow_3__srlcol_5__srlinst ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_wen_aux_oq_4147), + .D(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_shift_in[32]), + .Q(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_shift_tap[32]), + .CLK(NlwRenamedSig_OI_trn_clk), + .Q15(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_shift_in[41]), + .A0(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_lo[0]), + .A1(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_lo[1]), + .A2(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_lo[2]), + .A3(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_lo[3]) + ); + SRLC16E com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_srlrow_2__srlcol_1__srlinst ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_wen_aux_oq_4147), + .D(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_shift_in[19]), + .Q(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_shift_tap[19]), + .CLK(NlwRenamedSig_OI_trn_clk), + .Q15(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_shift_in[28]), + .A0(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_lo[0]), + .A1(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_lo[1]), + .A2(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_lo[2]), + .A3(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_lo[3]) + ); + SRLC16E com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_srlrow_0__srlcol_6__srlinst ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_wen_aux_oq_4147), + .D(com_tlm_u_tlm_rx_vc0_fifo_aux_in[6]), + .Q(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_shift_tap[6]), + .CLK(NlwRenamedSig_OI_trn_clk), + .Q15(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_shift_in[15]), + .A0(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_lo[0]), + .A1(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_lo[1]), + .A2(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_lo[2]), + .A3(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_lo[3]) + ); + SRLC16E com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_srlrow_3__srlcol_6__srlinst ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_wen_aux_oq_4147), + .D(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_shift_in[33]), + .Q(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_shift_tap[33]), + .CLK(NlwRenamedSig_OI_trn_clk), + .Q15(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_shift_in[42]), + .A0(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_lo[0]), + .A1(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_lo[1]), + .A2(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_lo[2]), + .A3(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_lo[3]) + ); + SRLC16E com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_srlrow_2__srlcol_2__srlinst ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_wen_aux_oq_4147), + .D(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_shift_in[20]), + .Q(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_shift_tap[20]), + .CLK(NlwRenamedSig_OI_trn_clk), + .Q15(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_shift_in[29]), + .A0(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_lo[0]), + .A1(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_lo[1]), + .A2(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_lo[2]), + .A3(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_lo[3]) + ); + SRLC16E com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_srlrow_0__srlcol_7__srlinst ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_wen_aux_oq_4147), + .D(com_tlm_u_tlm_rx_vc0_fifo_aux_in[7]), + .Q(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_shift_tap[7]), + .CLK(NlwRenamedSig_OI_trn_clk), + .Q15(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_shift_in[16]), + .A0(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_lo[0]), + .A1(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_lo[1]), + .A2(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_lo[2]), + .A3(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_lo[3]) + ); + SRLC16E com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_srlrow_3__srlcol_7__srlinst ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_wen_aux_oq_4147), + .D(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_shift_in[34]), + .Q(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_shift_tap[34]), + .CLK(NlwRenamedSig_OI_trn_clk), + .Q15(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_shift_in[43]), + .A0(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_lo[0]), + .A1(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_lo[1]), + .A2(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_lo[2]), + .A3(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_lo[3]) + ); + SRLC16E com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_srlrow_2__srlcol_3__srlinst ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_wen_aux_oq_4147), + .D(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_shift_in[21]), + .Q(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_shift_tap[21]), + .CLK(NlwRenamedSig_OI_trn_clk), + .Q15(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_shift_in[30]), + .A0(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_lo[0]), + .A1(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_lo[1]), + .A2(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_lo[2]), + .A3(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_lo[3]) + ); + SRLC16E com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_srlrow_0__srlcol_8__srlinst ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_wen_aux_oq_4147), + .D(com_tlm_u_tlm_rx_vc0_fifo_aux_in[8]), + .Q(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_shift_tap[8]), + .CLK(NlwRenamedSig_OI_trn_clk), + .Q15(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_shift_in[17]), + .A0(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_lo[0]), + .A1(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_lo[1]), + .A2(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_lo[2]), + .A3(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_lo[3]) + ); + SRLC16E com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_srlrow_3__srlcol_8__srlinst ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_wen_aux_oq_4147), + .D(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_shift_in[35]), + .Q(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_shift_tap[35]), + .CLK(NlwRenamedSig_OI_trn_clk), + .Q15(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_shift_in[44]), + .A0(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_lo[0]), + .A1(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_lo[1]), + .A2(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_lo[2]), + .A3(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_lo[3]) + ); + SRLC16E com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_srlrow_2__srlcol_4__srlinst ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_wen_aux_oq_4147), + .D(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_shift_in[22]), + .Q(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_shift_tap[22]), + .CLK(NlwRenamedSig_OI_trn_clk), + .Q15(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_shift_in[31]), + .A0(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_lo[0]), + .A1(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_lo[1]), + .A2(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_lo[2]), + .A3(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_lo[3]) + ); + SRLC16E com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_srlrow_1__srlcol_0__srlinst ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_wen_aux_oq_4147), + .D(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_shift_in[9]), + .Q(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_shift_tap[9]), + .CLK(NlwRenamedSig_OI_trn_clk), + .Q15(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_shift_in[18]), + .A0(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_lo[0]), + .A1(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_lo[1]), + .A2(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_lo[2]), + .A3(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_lo[3]) + ); + SRLC16E com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_srlrow_4__srlcol_0__srlinst ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_wen_aux_oq_4147), + .D(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_shift_in[36]), + .Q(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_shift_tap[36]), + .CLK(NlwRenamedSig_OI_trn_clk), + .Q15(NLW_com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_srlrow_4__srlcol_0__srlinst_Q15_UNCONNECTED), + .A0(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_lo[0]), + .A1(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_lo[1]), + .A2(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_lo[2]), + .A3(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_lo[3]) + ); + SRLC16E com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_srlrow_2__srlcol_5__srlinst ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_wen_aux_oq_4147), + .D(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_shift_in[23]), + .Q(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_shift_tap[23]), + .CLK(NlwRenamedSig_OI_trn_clk), + .Q15(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_shift_in[32]), + .A0(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_lo[0]), + .A1(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_lo[1]), + .A2(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_lo[2]), + .A3(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_lo[3]) + ); + SRLC16E com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_srlrow_1__srlcol_1__srlinst ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_wen_aux_oq_4147), + .D(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_shift_in[10]), + .Q(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_shift_tap[10]), + .CLK(NlwRenamedSig_OI_trn_clk), + .Q15(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_shift_in[19]), + .A0(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_lo[0]), + .A1(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_lo[1]), + .A2(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_lo[2]), + .A3(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_lo[3]) + ); + SRLC16E com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_srlrow_4__srlcol_1__srlinst ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_wen_aux_oq_4147), + .D(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_shift_in[37]), + .Q(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_shift_tap[37]), + .CLK(NlwRenamedSig_OI_trn_clk), + .Q15(NLW_com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_srlrow_4__srlcol_1__srlinst_Q15_UNCONNECTED), + .A0(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_lo[0]), + .A1(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_lo[1]), + .A2(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_lo[2]), + .A3(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_lo[3]) + ); + SRLC16E com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_srlrow_2__srlcol_6__srlinst ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_wen_aux_oq_4147), + .D(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_shift_in[24]), + .Q(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_shift_tap[24]), + .CLK(NlwRenamedSig_OI_trn_clk), + .Q15(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_shift_in[33]), + .A0(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_lo[0]), + .A1(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_lo[1]), + .A2(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_lo[2]), + .A3(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_lo[3]) + ); + SRLC16E com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_srlrow_3__srlcol_0__srlinst ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_wen_aux_oq_4147), + .D(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_shift_in[27]), + .Q(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_shift_tap[27]), + .CLK(NlwRenamedSig_OI_trn_clk), + .Q15(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_shift_in[36]), + .A0(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_lo[0]), + .A1(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_lo[1]), + .A2(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_lo[2]), + .A3(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_lo[3]) + ); + SRLC16E com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_srlrow_0__srlcol_0__srlinst ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_wen_aux_oq_4147), + .D(com_tlm_u_tlm_rx_vc0_fifo_aux_in[0]), + .Q(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_shift_tap[0]), + .CLK(NlwRenamedSig_OI_trn_clk), + .Q15(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_shift_in[9]), + .A0(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_lo[0]), + .A1(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_lo[1]), + .A2(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_lo[2]), + .A3(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_lo[3]) + ); + SRLC16E com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_srlrow_2__srlcol_7__srlinst ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_wen_aux_oq_4147), + .D(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_shift_in[25]), + .Q(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_shift_tap[25]), + .CLK(NlwRenamedSig_OI_trn_clk), + .Q15(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_shift_in[34]), + .A0(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_lo[0]), + .A1(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_lo[1]), + .A2(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_lo[2]), + .A3(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_lo[3]) + ); + SRLC16E com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_srlrow_1__srlcol_3__srlinst ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_wen_aux_oq_4147), + .D(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_shift_in[12]), + .Q(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_shift_tap[12]), + .CLK(NlwRenamedSig_OI_trn_clk), + .Q15(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_shift_in[21]), + .A0(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_lo[0]), + .A1(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_lo[1]), + .A2(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_lo[2]), + .A3(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_lo[3]) + ); + SRLC16E com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_srlrow_4__srlcol_3__srlinst ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_wen_aux_oq_4147), + .D(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_shift_in[39]), + .Q(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_shift_tap[39]), + .CLK(NlwRenamedSig_OI_trn_clk), + .Q15(NLW_com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_srlrow_4__srlcol_3__srlinst_Q15_UNCONNECTED), + .A0(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_lo[0]), + .A1(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_lo[1]), + .A2(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_lo[2]), + .A3(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_lo[3]) + ); + SRLC16E com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_srlrow_2__srlcol_8__srlinst ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_wen_aux_oq_4147), + .D(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_shift_in[26]), + .Q(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_shift_tap[26]), + .CLK(NlwRenamedSig_OI_trn_clk), + .Q15(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_shift_in[35]), + .A0(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_lo[0]), + .A1(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_lo[1]), + .A2(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_lo[2]), + .A3(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_lo[3]) + ); + SRLC16E com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_srlrow_1__srlcol_4__srlinst ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_wen_aux_oq_4147), + .D(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_shift_in[13]), + .Q(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_shift_tap[13]), + .CLK(NlwRenamedSig_OI_trn_clk), + .Q15(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_shift_in[22]), + .A0(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_lo[0]), + .A1(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_lo[1]), + .A2(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_lo[2]), + .A3(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_lo[3]) + ); + SRLC16E com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_srlrow_4__srlcol_2__srlinst ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_wen_aux_oq_4147), + .D(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_shift_in[38]), + .Q(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_shift_tap[38]), + .CLK(NlwRenamedSig_OI_trn_clk), + .Q15(NLW_com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_srlrow_4__srlcol_2__srlinst_Q15_UNCONNECTED), + .A0(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_lo[0]), + .A1(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_lo[1]), + .A2(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_lo[2]), + .A3(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_lo[3]) + ); + SRLC16E com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_srlrow_1__srlcol_2__srlinst ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_wen_aux_oq_4147), + .D(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_shift_in[11]), + .Q(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_shift_tap[11]), + .CLK(NlwRenamedSig_OI_trn_clk), + .Q15(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_shift_in[20]), + .A0(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_lo[0]), + .A1(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_lo[1]), + .A2(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_lo[2]), + .A3(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_lo[3]) + ); + SRLC16E com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_srlrow_3__srlcol_1__srlinst ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_wen_aux_oq_4147), + .D(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_shift_in[28]), + .Q(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_shift_tap[28]), + .CLK(NlwRenamedSig_OI_trn_clk), + .Q15(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_shift_in[37]), + .A0(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_lo[0]), + .A1(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_lo[1]), + .A2(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_lo[2]), + .A3(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_lo[3]) + ); + SRLC16E com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_srlrow_0__srlcol_1__srlinst ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_wen_aux_oq_4147), + .D(com_tlm_u_tlm_rx_vc0_fifo_aux_in[1]), + .Q(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_shift_tap[1]), + .CLK(NlwRenamedSig_OI_trn_clk), + .Q15(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_shift_in[10]), + .A0(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_lo[0]), + .A1(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_lo[1]), + .A2(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_lo[2]), + .A3(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_lo[3]) + ); + SRLC16E com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_srlrow_1__srlcol_5__srlinst ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_wen_aux_oq_4147), + .D(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_shift_in[14]), + .Q(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_shift_tap[14]), + .CLK(NlwRenamedSig_OI_trn_clk), + .Q15(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_shift_in[23]), + .A0(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_lo[0]), + .A1(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_lo[1]), + .A2(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_lo[2]), + .A3(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_lo[3]) + ); + FDS com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_lo_0_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_un1_raddr_lo_1_axb0_4369), + .Q(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_lo[0]), + .S(plm_link_up_i) + ); + FDS com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_lo_1_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_un1_raddr_lo_1_axbxc1_4368), + .Q(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_lo[1]), + .S(plm_link_up_i) + ); + FDS com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_lo_2_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_un1_raddr_lo_1_axbxc2_4366), + .Q(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_lo[2]), + .S(plm_link_up_i) + ); + FDS com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_lo_3_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_un1_raddr_lo_1_axbxc3_4364), + .Q(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_lo[3]), + .S(plm_link_up_i) + ); + FDRE com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_hi_0_ ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_un1_bkp_i_3_i_4359), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_hi_62[0]), + .Q(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_hi[0]), + .R(plm_link_up_i) + ); + FDRE com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_hi_1_ ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_un1_bkp_i_3_i_4359), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_hi_62[1]), + .Q(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_hi[1]), + .R(plm_link_up_i) + ); + FDRE com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_hi_2_ ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_un1_bkp_i_3_i_4359), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_hi_62[2]), + .Q(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_hi[2]), + .R(plm_link_up_i) + ); + FDRE com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_hi_3_ ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_un1_bkp_i_3_i_4359), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_hi_62[3]), + .Q(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_hi[3]), + .R(plm_link_up_i) + ); + FDRE com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_hi_4_ ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_un1_bkp_i_3_i_4359), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_hi_62[4]), + .Q(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_hi[4]), + .R(plm_link_up_i) + ); + FDRE com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_nxt_vld_o ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_un1_bkp_i_1_i_4358), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_hi_eq_1_m_i_4362), + .Q(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_nxt_vld_o_2), + .R(plm_link_up_i) + ); + FDRE com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_d_o_0_ ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_N_43140_i_i_4371), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_d_o_56[0]), + .Q(com_tlm_u_tlm_rx_vc0_fifo_aux_oqr[0]), + .R(plm_link_up_i) + ); + FDRE com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_d_o_1_ ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_N_43140_i_i_4371), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_d_o_56[1]), + .Q(com_tlm_u_tlm_rx_vc0_fifo_aux_oqr[1]), + .R(plm_link_up_i) + ); + FDRE com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_d_o_2_ ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_N_43140_i_i_4371), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_d_o_56[2]), + .Q(com_tlm_u_tlm_rx_vc0_fifo_aux_oqr[2]), + .R(plm_link_up_i) + ); + FDRE com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_d_o_3_ ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_N_43140_i_i_4371), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_d_o_56[3]), + .Q(com_tlm_u_tlm_rx_vc0_fifo_aux_oqr[3]), + .R(plm_link_up_i) + ); + FDRE com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_d_o_4_ ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_N_43140_i_i_4371), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_d_o_56[4]), + .Q(com_tlm_u_tlm_rx_vc0_fifo_aux_oqr[4]), + .R(plm_link_up_i) + ); + FDRE com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_d_o_5_ ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_N_43140_i_i_4371), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_d_o_56[5]), + .Q(com_tlm_u_tlm_rx_vc0_fifo_aux_oqr[5]), + .R(plm_link_up_i) + ); + FDRE com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_d_o_6_ ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_N_43140_i_i_4371), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_d_o_56[6]), + .Q(com_tlm_u_tlm_rx_vc0_fifo_aux_oqr[6]), + .R(plm_link_up_i) + ); + FDRE com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_d_o_7_ ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_N_43140_i_i_4371), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_d_o_56[7]), + .Q(com_tlm_u_tlm_rx_vc0_fifo_cfg_oqr), + .R(plm_link_up_i) + ); + FDRE com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_d_o_8_ ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_N_43140_i_i_4371), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_d_o_56[8]), + .Q(com_tlm_u_tlm_rx_vc0_fifo_np_oqr), + .R(plm_link_up_i) + ); + FDRE com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_vld_o ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_N_43140_i_i_4371), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_N_10761_i), + .Q(com_tlm_u_tlm_rx_vc0_fifo_aux_vld_oqr), + .R(plm_link_up_i) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_un1_raddr_lo_1_p4.INIT = 16'hF880; + LUT4 com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_un1_raddr_lo_1_p4 ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_en_4370), + .I1(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_lo[0]), + .I2(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_lo[1]), + .I3(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_un1_raddr_en_1[1]), + .O(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_un1_raddr_lo_1_p4_4367) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_un1_raddr_lo_1_p4_0.INIT = 8'hE8; + LUT3_L com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_un1_raddr_lo_1_p4_0 ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_lo[2]), + .I1(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_un1_raddr_en_1[1]), + .I2(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_un1_raddr_lo_1_p4_4367), + .LO(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_un1_raddr_lo_1_p4_0_4365) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddrshift_un8_raddr_shiftup_1.INIT = 16'h0001; + LUT4 com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddrshift_un8_raddr_shiftup_1 ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_hi[1]), + .I1(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_hi[2]), + .I2(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_hi[3]), + .I3(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_hi[4]), + .O(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_N_10759_1) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_d_o_d_0_3_.INIT = 16'h135F; + LUT4 com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_d_o_d_0_3_ ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_hi[3]), + .I1(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_hi[4]), + .I2(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_shift_tap[30]), + .I3(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_shift_tap[39]), + .O(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_d_o_d_0[3]) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_d_o_d_1_3_.INIT = 16'h135F; + LUT4 com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_d_o_d_1_3_ ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_hi[1]), + .I1(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_hi[2]), + .I2(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_shift_tap[12]), + .I3(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_shift_tap[21]), + .O(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_d_o_d_1[3]) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_d_o_d_0_5_.INIT = 16'h135F; + LUT4 com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_d_o_d_0_5_ ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_hi[1]), + .I1(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_hi[4]), + .I2(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_shift_tap[14]), + .I3(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_shift_tap[41]), + .O(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_d_o_d_0[5]) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_d_o_d_1_5_.INIT = 16'h135F; + LUT4 com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_d_o_d_1_5_ ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_hi[2]), + .I1(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_hi[3]), + .I2(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_shift_tap[23]), + .I3(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_shift_tap[32]), + .O(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_d_o_d_1[5]) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_d_o_d_0_1_.INIT = 16'h135F; + LUT4 com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_d_o_d_0_1_ ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_hi[3]), + .I1(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_hi[4]), + .I2(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_shift_tap[28]), + .I3(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_shift_tap[37]), + .O(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_d_o_d_0[1]) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_d_o_d_1_1_.INIT = 16'h135F; + LUT4 com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_d_o_d_1_1_ ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_hi[1]), + .I1(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_hi[2]), + .I2(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_shift_tap[10]), + .I3(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_shift_tap[19]), + .O(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_d_o_d_1[1]) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_d_o_d_0_4_.INIT = 16'h135F; + LUT4 com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_d_o_d_0_4_ ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_hi[3]), + .I1(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_hi[4]), + .I2(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_shift_tap[31]), + .I3(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_shift_tap[40]), + .O(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_d_o_d_0[4]) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_d_o_d_1_4_.INIT = 16'h135F; + LUT4 com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_d_o_d_1_4_ ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_hi[1]), + .I1(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_hi[2]), + .I2(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_shift_tap[13]), + .I3(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_shift_tap[22]), + .O(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_d_o_d_1[4]) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_d_o_d_0_2_.INIT = 16'h135F; + LUT4 com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_d_o_d_0_2_ ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_hi[3]), + .I1(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_hi[4]), + .I2(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_shift_tap[29]), + .I3(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_shift_tap[38]), + .O(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_d_o_d_0[2]) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_d_o_d_1_2_.INIT = 16'h135F; + LUT4 com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_d_o_d_1_2_ ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_hi[1]), + .I1(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_hi[2]), + .I2(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_shift_tap[11]), + .I3(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_shift_tap[20]), + .O(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_d_o_d_1[2]) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_d_o_d_0_6_.INIT = 16'h135F; + LUT4 com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_d_o_d_0_6_ ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_hi[3]), + .I1(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_hi[4]), + .I2(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_shift_tap[33]), + .I3(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_shift_tap[42]), + .O(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_d_o_d_0[6]) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_d_o_d_1_6_.INIT = 16'h135F; + LUT4 com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_d_o_d_1_6_ ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_hi[1]), + .I1(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_hi[2]), + .I2(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_shift_tap[15]), + .I3(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_shift_tap[24]), + .O(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_d_o_d_1[6]) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_d_o_d_0_0_.INIT = 16'h135F; + LUT4 com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_d_o_d_0_0_ ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_hi[3]), + .I1(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_hi[4]), + .I2(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_shift_tap[27]), + .I3(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_shift_tap[36]), + .O(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_d_o_d_0[0]) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_d_o_d_1_0_.INIT = 16'h135F; + LUT4 com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_d_o_d_1_0_ ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_hi[1]), + .I1(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_hi[2]), + .I2(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_shift_tap[9]), + .I3(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_shift_tap[18]), + .O(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_d_o_d_1[0]) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_d_o_d_0_8_.INIT = 16'h135F; + LUT4 com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_d_o_d_0_8_ ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_hi[3]), + .I1(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_hi[4]), + .I2(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_shift_tap[35]), + .I3(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_shift_tap[44]), + .O(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_d_o_d_0[8]) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_d_o_d_1_8_.INIT = 16'h135F; + LUT4 com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_d_o_d_1_8_ ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_hi[1]), + .I1(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_hi[2]), + .I2(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_shift_tap[17]), + .I3(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_shift_tap[26]), + .O(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_d_o_d_1[8]) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_d_o_d_0_7_.INIT = 16'h135F; + LUT4 com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_d_o_d_0_7_ ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_hi[3]), + .I1(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_hi[4]), + .I2(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_shift_tap[34]), + .I3(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_shift_tap[43]), + .O(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_d_o_d_0[7]) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_d_o_d_1_7_.INIT = 16'h135F; + LUT4 com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_d_o_d_1_7_ ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_hi[1]), + .I1(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_hi[2]), + .I2(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_shift_tap[16]), + .I3(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_shift_tap[25]), + .O(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_d_o_d_1[7]) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_un13_nxt_vld_o_en_2.INIT = 16'h0001; + LUT4 com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_un13_nxt_vld_o_en_2 ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_lo[0]), + .I1(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_lo[1]), + .I2(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_lo[2]), + .I3(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_lo[3]), + .O(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_un13_nxt_vld_o_en_2_4360) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_overwrap_2.INIT = 16'h8000; + LUT4 com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_overwrap_2 ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_lo[0]), + .I1(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_lo[1]), + .I2(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_lo[2]), + .I3(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_lo[3]), + .O(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_overwrap_2_4361) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_d_o_d_5_.INIT = 16'h0888; + LUT4 com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_d_o_d_5_ ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_d_o_d_0[5]), + .I1(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_d_o_d_1[5]), + .I2(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_hi[0]), + .I3(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_shift_tap[5]), + .O(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_N_10752) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_d_o_d_6_.INIT = 16'h0888; + LUT4 com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_d_o_d_6_ ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_d_o_d_0[6]), + .I1(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_d_o_d_1[6]), + .I2(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_hi[0]), + .I3(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_shift_tap[6]), + .O(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_N_10751) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_d_o_d_7_.INIT = 16'h0888; + LUT4 com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_d_o_d_7_ ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_d_o_d_0[7]), + .I1(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_d_o_d_1[7]), + .I2(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_hi[0]), + .I3(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_shift_tap[7]), + .O(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_N_10750) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_d_o_d_8_.INIT = 16'h0888; + LUT4 com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_d_o_d_8_ ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_d_o_d_0[8]), + .I1(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_d_o_d_1[8]), + .I2(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_hi[0]), + .I3(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_shift_tap[8]), + .O(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_N_10749) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_d_o_d_0_.INIT = 16'h0888; + LUT4 com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_d_o_d_0_ ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_d_o_d_0[0]), + .I1(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_d_o_d_1[0]), + .I2(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_hi[0]), + .I3(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_shift_tap[0]), + .O(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_N_10757) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_d_o_d_1_.INIT = 16'h0888; + LUT4 com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_d_o_d_1_ ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_d_o_d_0[1]), + .I1(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_d_o_d_1[1]), + .I2(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_hi[0]), + .I3(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_shift_tap[1]), + .O(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_N_10756) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_d_o_d_2_.INIT = 16'h0888; + LUT4 com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_d_o_d_2_ ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_d_o_d_0[2]), + .I1(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_d_o_d_1[2]), + .I2(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_hi[0]), + .I3(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_shift_tap[2]), + .O(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_N_10755) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_d_o_d_3_.INIT = 16'h0888; + LUT4 com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_d_o_d_3_ ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_d_o_d_0[3]), + .I1(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_d_o_d_1[3]), + .I2(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_hi[0]), + .I3(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_shift_tap[3]), + .O(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_N_10754) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_d_o_d_4_.INIT = 16'h0888; + LUT4 com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_d_o_d_4_ ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_d_o_d_0[4]), + .I1(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_d_o_d_1[4]), + .I2(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_hi[0]), + .I3(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_shift_tap[4]), + .O(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_N_10753) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_srl_ren_i.INIT = 8'hD0; + LUT3 com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_srl_ren_i ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_N_44135_i), + .I1(com_tlm_u_tlm_rx_vc0_fifo_ren_oq_i_a3_0_4150), + .I2(com_tlm_u_tlm_rx_vc0_fifo_aux_vld_oqr), + .O(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_N_43140_i) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_srl_wen.INIT = 8'hE0; + LUT3 com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_srl_wen ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_N_43140_i), + .I1(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_nxt_vld_o_2), + .I2(com_tlm_u_tlm_rx_vc0_fifo_wen_aux_oq_4147), + .O(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_srl_wen_4363) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_en.INIT = 8'hA4; + LUT3 com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_en ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_N_43140_i), + .I1(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_nxt_vld_o_2), + .I2(com_tlm_u_tlm_rx_vc0_fifo_wen_aux_oq_4147), + .O(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_en_4370) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_un1_raddr_en_1_1_.INIT = 8'h04; + LUT3 com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_un1_raddr_en_1_1_ ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_N_43140_i), + .I1(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_nxt_vld_o_2), + .I2(com_tlm_u_tlm_rx_vc0_fifo_wen_aux_oq_4147), + .O(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_un1_raddr_en_1[1]) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_un1_bkp_i_1_i.INIT = 8'hDC; + LUT3 com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_un1_bkp_i_1_i ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_N_43140_i), + .I1(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_srl_wen_4363), + .I2(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_un13_nxt_vld_o_en_2_4360), + .O(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_un1_bkp_i_1_i_4358) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_un1_bkp_i_3_i.INIT = 16'h8580; + LUT4 com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_un1_bkp_i_3_i ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_N_43140_i), + .I1(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_overwrap_2_4361), + .I2(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_srl_wen_4363), + .I3(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_un13_nxt_vld_o_en_2_4360), + .O(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_un1_bkp_i_3_i_4359) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_control_bits_N_10761_i.INIT = 4'hE; + LUT2_L com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_control_bits_N_10761_i ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_nxt_vld_o_2), + .I1(com_tlm_u_tlm_rx_vc0_fifo_wen_aux_oq_4147), + .LO(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_N_10761_i) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_control_bits_d_o_56_0_8_.INIT = 16'h5C50; + LUT4_L com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_control_bits_d_o_56_0_8_ ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_N_10749), + .I1(com_tlm_u_tlm_rx_vc0_fifo_aux_in[8]), + .I2(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_nxt_vld_o_2), + .I3(com_tlm_u_tlm_rx_vc0_fifo_wen_aux_oq_4147), + .LO(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_d_o_56[8]) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_control_bits_d_o_56_0_7_.INIT = 16'h5C50; + LUT4_L com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_control_bits_d_o_56_0_7_ ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_N_10750), + .I1(com_tlm_u_tlm_rx_vc0_fifo_aux_in[7]), + .I2(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_nxt_vld_o_2), + .I3(com_tlm_u_tlm_rx_vc0_fifo_wen_aux_oq_4147), + .LO(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_d_o_56[7]) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_control_bits_d_o_56_0_6_.INIT = 16'h5C50; + LUT4_L com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_control_bits_d_o_56_0_6_ ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_N_10751), + .I1(com_tlm_u_tlm_rx_vc0_fifo_aux_in[6]), + .I2(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_nxt_vld_o_2), + .I3(com_tlm_u_tlm_rx_vc0_fifo_wen_aux_oq_4147), + .LO(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_d_o_56[6]) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_control_bits_d_o_56_0_5_.INIT = 16'h5C50; + LUT4_L com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_control_bits_d_o_56_0_5_ ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_N_10752), + .I1(com_tlm_u_tlm_rx_vc0_fifo_aux_in[5]), + .I2(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_nxt_vld_o_2), + .I3(com_tlm_u_tlm_rx_vc0_fifo_wen_aux_oq_4147), + .LO(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_d_o_56[5]) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_control_bits_d_o_56_0_4_.INIT = 16'h5C50; + LUT4_L com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_control_bits_d_o_56_0_4_ ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_N_10753), + .I1(com_tlm_u_tlm_rx_vc0_fifo_aux_in[4]), + .I2(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_nxt_vld_o_2), + .I3(com_tlm_u_tlm_rx_vc0_fifo_wen_aux_oq_4147), + .LO(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_d_o_56[4]) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_control_bits_d_o_56_0_3_.INIT = 16'h5C50; + LUT4_L com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_control_bits_d_o_56_0_3_ ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_N_10754), + .I1(com_tlm_u_tlm_rx_vc0_fifo_aux_in[3]), + .I2(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_nxt_vld_o_2), + .I3(com_tlm_u_tlm_rx_vc0_fifo_wen_aux_oq_4147), + .LO(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_d_o_56[3]) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_control_bits_d_o_56_0_2_.INIT = 16'h5C50; + LUT4_L com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_control_bits_d_o_56_0_2_ ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_N_10755), + .I1(com_tlm_u_tlm_rx_vc0_fifo_aux_in[2]), + .I2(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_nxt_vld_o_2), + .I3(com_tlm_u_tlm_rx_vc0_fifo_wen_aux_oq_4147), + .LO(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_d_o_56[2]) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_control_bits_d_o_56_0_1_.INIT = 16'h5C50; + LUT4_L com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_control_bits_d_o_56_0_1_ ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_N_10756), + .I1(com_tlm_u_tlm_rx_vc0_fifo_aux_in[1]), + .I2(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_nxt_vld_o_2), + .I3(com_tlm_u_tlm_rx_vc0_fifo_wen_aux_oq_4147), + .LO(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_d_o_56[1]) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_control_bits_d_o_56_0_0_.INIT = 16'h5C50; + LUT4_L com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_control_bits_d_o_56_0_0_ ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_N_10757), + .I1(com_tlm_u_tlm_rx_vc0_fifo_aux_in[0]), + .I2(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_nxt_vld_o_2), + .I3(com_tlm_u_tlm_rx_vc0_fifo_wen_aux_oq_4147), + .LO(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_d_o_56[0]) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_hi_eq_1_m_i.INIT = 8'hF7; + LUT3_L com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_hi_eq_1_m_i ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_N_10759_1), + .I1(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_hi[0]), + .I2(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_srl_wen_4363), + .LO(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_hi_eq_1_m_i_4362) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_hi_62_0_4_.INIT = 4'h8; + LUT2_L com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_hi_62_0_4_ ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_hi[3]), + .I1(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_srl_wen_4363), + .LO(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_hi_62[4]) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_hi_62_0_0_3_.INIT = 8'hAC; + LUT3_L com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_hi_62_0_0_3_ ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_hi[2]), + .I1(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_hi[4]), + .I2(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_srl_wen_4363), + .LO(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_hi_62[3]) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_hi_62_0_0_2_.INIT = 8'hAC; + LUT3_L com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_hi_62_0_0_2_ ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_hi[1]), + .I1(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_hi[3]), + .I2(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_srl_wen_4363), + .LO(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_hi_62[2]) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_hi_62_0_0_1_.INIT = 8'hAC; + LUT3_L com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_hi_62_0_0_1_ ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_hi[0]), + .I1(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_hi[2]), + .I2(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_srl_wen_4363), + .LO(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_hi_62[1]) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_hi_62_0_0_0_.INIT = 16'h22F0; + LUT4_L com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_hi_62_0_0_0_ ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_N_10759_1), + .I1(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_hi[0]), + .I2(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_hi[1]), + .I3(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_srl_wen_4363), + .LO(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_hi_62[0]) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_un1_raddr_lo_1_axbxc3.INIT = 8'h96; + LUT3_L com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_un1_raddr_lo_1_axbxc3 ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_lo[3]), + .I1(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_un1_raddr_en_1[1]), + .I2(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_un1_raddr_lo_1_p4_0_4365), + .LO(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_un1_raddr_lo_1_axbxc3_4364) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_un1_raddr_lo_1_axbxc2.INIT = 8'h96; + LUT3_L com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_un1_raddr_lo_1_axbxc2 ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_lo[2]), + .I1(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_un1_raddr_en_1[1]), + .I2(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_un1_raddr_lo_1_p4_4367), + .LO(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_un1_raddr_lo_1_axbxc2_4366) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_un1_raddr_lo_1_axbxc1.INIT = 16'h8778; + LUT4_L com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_un1_raddr_lo_1_axbxc1 ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_en_4370), + .I1(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_lo[0]), + .I2(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_lo[1]), + .I3(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_un1_raddr_en_1[1]), + .LO(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_un1_raddr_lo_1_axbxc1_4368) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_un1_raddr_lo_1_axb0.INIT = 4'h6; + LUT2_L com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_un1_raddr_lo_1_axb0 ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_en_4370), + .I1(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_raddr_lo[0]), + .LO(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_un1_raddr_lo_1_axb0_4369) + ); + INV com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_N_43140_i_i ( + .I(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_N_43140_i), + .O(com_tlm_u_tlm_rx_vc0_fifo_ord_queue_aux_fifo_N_43140_i_i_4371) + ); + FDR com_tlm_u_tlm_rx_vc0_fifo_byp_queue_sof_hold ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_sof_hold_3), + .Q(com_tlm_u_tlm_rx_vc0_fifo_sof_hold), + .R(plm_link_up_i) + ); + FDRE com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_vld_q ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_ren_4372), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_aux_vld), + .Q(com_tlm_u_tlm_rx_vc0_fifo_aux_vld_q), + .R(plm_link_up_i) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_ren.INIT = 4'h4; + LUT2 com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_ren ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_sof_hold), + .I1(com_tlm_u_tlm_rx_vc0_fifo_data_bqr_64_), + .O(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_ren_4372) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_o_i_m3_0_7_.INIT = 8'hCA; + LUT3 com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_o_i_m3_0_7_ ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux[7]), + .I1(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_q[7]), + .I2(com_tlm_u_tlm_rx_vc0_fifo_sof_hold), + .O(com_tlm_u_tlm_rx_vc0_fifo_N_44111) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_ren_64_sof_hold_3.INIT = 8'h8C; + LUT3_L com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_ren_64_sof_hold_3 ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_N_10675_i_i), + .I1(com_tlm_u_tlm_rx_vc0_fifo_data_bqr_64_), + .I2(com_tlm_u_tlm_rx_vc0_fifo_select_bq_4161), + .LO(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_sof_hold_3) + ); + FDE com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_q_7_ ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_ren_4372), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux[7]), + .Q(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_q[7]) + ); + FDE com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_q_6_ ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_ren_4372), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_aux[6]), + .Q(com_tlm_u_tlm_rx_vc0_fifo_aux_q[6]) + ); + FDE com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_q_5_ ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_ren_4372), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_aux[5]), + .Q(com_tlm_u_tlm_rx_vc0_fifo_aux_q[5]) + ); + FDE com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_q_4_ ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_ren_4372), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_aux[4]), + .Q(com_tlm_u_tlm_rx_vc0_fifo_aux_q[4]) + ); + FDE com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_q_3_ ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_ren_4372), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_aux[3]), + .Q(com_tlm_u_tlm_rx_vc0_fifo_aux_q[3]) + ); + FDE com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_q_2_ ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_ren_4372), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_aux[2]), + .Q(com_tlm_u_tlm_rx_vc0_fifo_aux_q[2]) + ); + FDE com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_q_1_ ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_ren_4372), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_aux[1]), + .Q(com_tlm_u_tlm_rx_vc0_fifo_aux_q[1]) + ); + FDE com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_q_0_ ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_ren_4372), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_aux[0]), + .Q(com_tlm_u_tlm_rx_vc0_fifo_aux_q[0]) + ); + GND com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_GND ( + .G(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_GND_4373) + ); + SRLC16E com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_srlrow_0__srlcol_0__srlinst ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_select_oq2bq_4169), + .D(com_tlm_u_tlm_rx_vc0_fifo_data_oqr_0_), + .Q(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_0_), + .CLK(NlwRenamedSig_OI_trn_clk), + .Q15(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_in_72_), + .A0(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[0]), + .A1(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[1]), + .A2(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[2]), + .A3(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[3]) + ); + SRLC16E com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_srlrow_1__srlcol_9__srlinst ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_select_oq2bq_4169), + .D(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_in_81_), + .Q(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_81_), + .CLK(NlwRenamedSig_OI_trn_clk), + .Q15(NLW_com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_srlrow_1__srlcol_9__srlinst_Q15_UNCONNECTED), + .A0(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[0]), + .A1(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[1]), + .A2(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[2]), + .A3(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[3]) + ); + SRLC16E com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_srlrow_0__srlcol_41__srlinst ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_select_oq2bq_1_4168), + .D(com_tlm_u_tlm_rx_vc0_fifo_data_oqr_41_), + .Q(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_41_), + .CLK(NlwRenamedSig_OI_trn_clk), + .Q15(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_in_113_), + .A0(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[0]), + .A1(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[1]), + .A2(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[2]), + .A3(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[3]) + ); + SRLC16E com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_srlrow_0__srlcol_1__srlinst ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_select_oq2bq_4169), + .D(com_tlm_u_tlm_rx_vc0_fifo_data_oqr_1_), + .Q(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_1_), + .CLK(NlwRenamedSig_OI_trn_clk), + .Q15(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_in_73_), + .A0(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[0]), + .A1(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[1]), + .A2(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[2]), + .A3(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[3]) + ); + SRLC16E com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_srlrow_1__srlcol_10__srlinst ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_select_oq2bq_4169), + .D(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_in_82_), + .Q(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_82_), + .CLK(NlwRenamedSig_OI_trn_clk), + .Q15(NLW_com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_srlrow_1__srlcol_10__srlinst_Q15_UNCONNECTED), + .A0(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[0]), + .A1(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[1]), + .A2(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[2]), + .A3(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[3]) + ); + SRLC16E com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_srlrow_0__srlcol_42__srlinst ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_select_oq2bq_1_4168), + .D(com_tlm_u_tlm_rx_vc0_fifo_data_oqr_42_), + .Q(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_42_), + .CLK(NlwRenamedSig_OI_trn_clk), + .Q15(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_in_114_), + .A0(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[0]), + .A1(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[1]), + .A2(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[2]), + .A3(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[3]) + ); + SRLC16E com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_srlrow_0__srlcol_2__srlinst ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_select_oq2bq_4169), + .D(com_tlm_u_tlm_rx_vc0_fifo_data_oqr_2_), + .Q(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_2_), + .CLK(NlwRenamedSig_OI_trn_clk), + .Q15(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_in_74_), + .A0(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[0]), + .A1(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[1]), + .A2(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[2]), + .A3(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[3]) + ); + SRLC16E com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_srlrow_1__srlcol_11__srlinst ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_select_oq2bq_4169), + .D(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_in_83_), + .Q(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_83_), + .CLK(NlwRenamedSig_OI_trn_clk), + .Q15(NLW_com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_srlrow_1__srlcol_11__srlinst_Q15_UNCONNECTED), + .A0(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[0]), + .A1(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[1]), + .A2(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[2]), + .A3(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[3]) + ); + SRLC16E com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_srlrow_0__srlcol_43__srlinst ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_select_oq2bq_1_4168), + .D(com_tlm_u_tlm_rx_vc0_fifo_data_oqr_43_), + .Q(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_43_), + .CLK(NlwRenamedSig_OI_trn_clk), + .Q15(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_in_115_), + .A0(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[0]), + .A1(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[1]), + .A2(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[2]), + .A3(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[3]) + ); + SRLC16E com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_srlrow_0__srlcol_3__srlinst ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_select_oq2bq_4169), + .D(com_tlm_u_tlm_rx_vc0_fifo_data_oqr_3_), + .Q(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_3_), + .CLK(NlwRenamedSig_OI_trn_clk), + .Q15(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_in_75_), + .A0(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[0]), + .A1(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[1]), + .A2(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[2]), + .A3(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[3]) + ); + SRLC16E com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_srlrow_0__srlcol_21__srlinst ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_select_oq2bq_4169), + .D(com_tlm_u_tlm_rx_vc0_fifo_data_oqr_21_), + .Q(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_21_), + .CLK(NlwRenamedSig_OI_trn_clk), + .Q15(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_in_93_), + .A0(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[0]), + .A1(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[1]), + .A2(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[2]), + .A3(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[3]) + ); + SRLC16E com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_srlrow_1__srlcol_30__srlinst ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_select_oq2bq_1_4168), + .D(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_in_102_), + .Q(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_102_), + .CLK(NlwRenamedSig_OI_trn_clk), + .Q15(NLW_com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_srlrow_1__srlcol_30__srlinst_Q15_UNCONNECTED), + .A0(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[0]), + .A1(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[1]), + .A2(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[2]), + .A3(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[3]) + ); + SRLC16E com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_srlrow_0__srlcol_4__srlinst ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_select_oq2bq_4169), + .D(com_tlm_u_tlm_rx_vc0_fifo_data_oqr_4_), + .Q(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_4_), + .CLK(NlwRenamedSig_OI_trn_clk), + .Q15(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_in_76_), + .A0(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[0]), + .A1(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[1]), + .A2(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[2]), + .A3(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[3]) + ); + SRLC16E com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_srlrow_1__srlcol_13__srlinst ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_select_oq2bq_4169), + .D(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_in_85_), + .Q(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_85_), + .CLK(NlwRenamedSig_OI_trn_clk), + .Q15(NLW_com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_srlrow_1__srlcol_13__srlinst_Q15_UNCONNECTED), + .A0(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[0]), + .A1(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[1]), + .A2(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[2]), + .A3(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[3]) + ); + SRLC16E com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_srlrow_0__srlcol_60__srlinst ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_select_oq2bq_1_4168), + .D(com_tlm_u_tlm_rx_vc0_fifo_data_oqr_60_), + .Q(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_60_), + .CLK(NlwRenamedSig_OI_trn_clk), + .Q15(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_in_132_), + .A0(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[0]), + .A1(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[1]), + .A2(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[2]), + .A3(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[3]) + ); + SRLC16E com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_srlrow_0__srlcol_20__srlinst ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_select_oq2bq_4169), + .D(com_tlm_u_tlm_rx_vc0_fifo_data_oqr_20_), + .Q(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_20_), + .CLK(NlwRenamedSig_OI_trn_clk), + .Q15(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_in_92_), + .A0(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[0]), + .A1(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[1]), + .A2(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[2]), + .A3(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[3]) + ); + SRLC16E com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_srlrow_1__srlcol_14__srlinst ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_select_oq2bq_4169), + .D(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_in_86_), + .Q(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_86_), + .CLK(NlwRenamedSig_OI_trn_clk), + .Q15(NLW_com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_srlrow_1__srlcol_14__srlinst_Q15_UNCONNECTED), + .A0(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[0]), + .A1(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[1]), + .A2(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[2]), + .A3(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[3]) + ); + SRLC16E com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_srlrow_0__srlcol_46__srlinst ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_select_oq2bq_1_4168), + .D(com_tlm_u_tlm_rx_vc0_fifo_ep_oqr), + .Q(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_46_), + .CLK(NlwRenamedSig_OI_trn_clk), + .Q15(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_in_118_), + .A0(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[0]), + .A1(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[1]), + .A2(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[2]), + .A3(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[3]) + ); + SRLC16E com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_srlrow_0__srlcol_6__srlinst ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_select_oq2bq_4169), + .D(com_tlm_u_tlm_rx_vc0_fifo_data_oqr_6_), + .Q(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_6_), + .CLK(NlwRenamedSig_OI_trn_clk), + .Q15(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_in_78_), + .A0(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[0]), + .A1(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[1]), + .A2(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[2]), + .A3(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[3]) + ); + SRLC16E com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_srlrow_0__srlcol_54__srlinst ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_select_oq2bq_1_4168), + .D(com_tlm_u_tlm_rx_vc0_fifo_data_oqr_54_), + .Q(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_54_), + .CLK(NlwRenamedSig_OI_trn_clk), + .Q15(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_in_126_), + .A0(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[0]), + .A1(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[1]), + .A2(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[2]), + .A3(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[3]) + ); + SRLC16E com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_srlrow_0__srlcol_14__srlinst ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_select_oq2bq_4169), + .D(com_tlm_u_tlm_rx_vc0_fifo_data_oqr_14_), + .Q(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_14_), + .CLK(NlwRenamedSig_OI_trn_clk), + .Q15(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_in_86_), + .A0(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[0]), + .A1(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[1]), + .A2(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[2]), + .A3(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[3]) + ); + SRLC16E com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_srlrow_0__srlcol_7__srlinst ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_select_oq2bq_4169), + .D(com_tlm_u_tlm_rx_vc0_fifo_data_oqr_7_), + .Q(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_7_), + .CLK(NlwRenamedSig_OI_trn_clk), + .Q15(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_in_79_), + .A0(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[0]), + .A1(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[1]), + .A2(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[2]), + .A3(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[3]) + ); + SRLC16E com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_srlrow_1__srlcol_16__srlinst ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_select_oq2bq_4169), + .D(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_in_88_), + .Q(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_88_), + .CLK(NlwRenamedSig_OI_trn_clk), + .Q15(NLW_com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_srlrow_1__srlcol_16__srlinst_Q15_UNCONNECTED), + .A0(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[0]), + .A1(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[1]), + .A2(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[2]), + .A3(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[3]) + ); + SRLC16E com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_srlrow_0__srlcol_57__srlinst ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_select_oq2bq_1_4168), + .D(com_tlm_u_tlm_rx_vc0_fifo_data_oqr_57_), + .Q(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_57_), + .CLK(NlwRenamedSig_OI_trn_clk), + .Q15(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_in_129_), + .A0(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[0]), + .A1(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[1]), + .A2(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[2]), + .A3(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[3]) + ); + SRLC16E com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_srlrow_0__srlcol_17__srlinst ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_select_oq2bq_4169), + .D(com_tlm_u_tlm_rx_vc0_fifo_data_oqr_17_), + .Q(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_17_), + .CLK(NlwRenamedSig_OI_trn_clk), + .Q15(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_in_89_), + .A0(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[0]), + .A1(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[1]), + .A2(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[2]), + .A3(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[3]) + ); + SRLC16E com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_srlrow_1__srlcol_17__srlinst ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_select_oq2bq_4169), + .D(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_in_89_), + .Q(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_89_), + .CLK(NlwRenamedSig_OI_trn_clk), + .Q15(NLW_com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_srlrow_1__srlcol_17__srlinst_Q15_UNCONNECTED), + .A0(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[0]), + .A1(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[1]), + .A2(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[2]), + .A3(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[3]) + ); + SRLC16E com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_srlrow_0__srlcol_49__srlinst ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_select_oq2bq_1_4168), + .D(com_tlm_u_tlm_rx_vc0_fifo_data_oqr_49_), + .Q(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_49_), + .CLK(NlwRenamedSig_OI_trn_clk), + .Q15(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_in_121_), + .A0(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[0]), + .A1(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[1]), + .A2(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[2]), + .A3(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[3]) + ); + SRLC16E com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_srlrow_0__srlcol_9__srlinst ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_select_oq2bq_4169), + .D(com_tlm_u_tlm_rx_vc0_fifo_data_oqr_9_), + .Q(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_9_), + .CLK(NlwRenamedSig_OI_trn_clk), + .Q15(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_in_81_), + .A0(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[0]), + .A1(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[1]), + .A2(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[2]), + .A3(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[3]) + ); + SRLC16E com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_srlrow_1__srlcol_18__srlinst ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_select_oq2bq_4169), + .D(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_in_90_), + .Q(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_90_), + .CLK(NlwRenamedSig_OI_trn_clk), + .Q15(NLW_com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_srlrow_1__srlcol_18__srlinst_Q15_UNCONNECTED), + .A0(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[0]), + .A1(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[1]), + .A2(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[2]), + .A3(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[3]) + ); + SRLC16E com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_srlrow_0__srlcol_50__srlinst ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_select_oq2bq_1_4168), + .D(com_tlm_u_tlm_rx_vc0_fifo_data_oqr_50_), + .Q(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_50_), + .CLK(NlwRenamedSig_OI_trn_clk), + .Q15(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_in_122_), + .A0(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[0]), + .A1(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[1]), + .A2(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[2]), + .A3(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[3]) + ); + SRLC16E com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_srlrow_0__srlcol_10__srlinst ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_select_oq2bq_4169), + .D(com_tlm_u_tlm_rx_vc0_fifo_data_oqr_10_), + .Q(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_10_), + .CLK(NlwRenamedSig_OI_trn_clk), + .Q15(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_in_82_), + .A0(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[0]), + .A1(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[1]), + .A2(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[2]), + .A3(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[3]) + ); + SRLC16E com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_srlrow_1__srlcol_19__srlinst ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_select_oq2bq_4169), + .D(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_in_91_), + .Q(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_91_), + .CLK(NlwRenamedSig_OI_trn_clk), + .Q15(NLW_com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_srlrow_1__srlcol_19__srlinst_Q15_UNCONNECTED), + .A0(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[0]), + .A1(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[1]), + .A2(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[2]), + .A3(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[3]) + ); + SRLC16E com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_srlrow_0__srlcol_51__srlinst ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_select_oq2bq_1_4168), + .D(com_tlm_u_tlm_rx_vc0_fifo_data_oqr_51_), + .Q(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_51_), + .CLK(NlwRenamedSig_OI_trn_clk), + .Q15(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_in_123_), + .A0(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[0]), + .A1(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[1]), + .A2(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[2]), + .A3(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[3]) + ); + SRLC16E com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_srlrow_0__srlcol_11__srlinst ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_select_oq2bq_4169), + .D(com_tlm_u_tlm_rx_vc0_fifo_data_oqr_11_), + .Q(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_11_), + .CLK(NlwRenamedSig_OI_trn_clk), + .Q15(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_in_83_), + .A0(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[0]), + .A1(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[1]), + .A2(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[2]), + .A3(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[3]) + ); + SRLC16E com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_srlrow_1__srlcol_20__srlinst ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_select_oq2bq_4169), + .D(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_in_92_), + .Q(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_92_), + .CLK(NlwRenamedSig_OI_trn_clk), + .Q15(NLW_com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_srlrow_1__srlcol_20__srlinst_Q15_UNCONNECTED), + .A0(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[0]), + .A1(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[1]), + .A2(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[2]), + .A3(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[3]) + ); + SRLC16E com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_srlrow_0__srlcol_52__srlinst ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_select_oq2bq_1_4168), + .D(com_tlm_u_tlm_rx_vc0_fifo_data_oqr_52_), + .Q(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_52_), + .CLK(NlwRenamedSig_OI_trn_clk), + .Q15(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_in_124_), + .A0(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[0]), + .A1(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[1]), + .A2(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[2]), + .A3(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[3]) + ); + SRLC16E com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_srlrow_0__srlcol_12__srlinst ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_select_oq2bq_4169), + .D(com_tlm_u_tlm_rx_vc0_fifo_data_oqr_12_), + .Q(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_12_), + .CLK(NlwRenamedSig_OI_trn_clk), + .Q15(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_in_84_), + .A0(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[0]), + .A1(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[1]), + .A2(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[2]), + .A3(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[3]) + ); + SRLC16E com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_srlrow_0__srlcol_48__srlinst ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_select_oq2bq_1_4168), + .D(com_tlm_u_tlm_rx_vc0_fifo_data_oqr_48_), + .Q(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_48_), + .CLK(NlwRenamedSig_OI_trn_clk), + .Q15(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_in_120_), + .A0(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[0]), + .A1(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[1]), + .A2(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[2]), + .A3(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[3]) + ); + SRLC16E com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_srlrow_0__srlcol_8__srlinst ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_select_oq2bq_4169), + .D(com_tlm_u_tlm_rx_vc0_fifo_data_oqr_8_), + .Q(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_8_), + .CLK(NlwRenamedSig_OI_trn_clk), + .Q15(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_in_80_), + .A0(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[0]), + .A1(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[1]), + .A2(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[2]), + .A3(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[3]) + ); + SRLC16E com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_srlrow_0__srlcol_13__srlinst ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_select_oq2bq_4169), + .D(com_tlm_u_tlm_rx_vc0_fifo_data_oqr_13_), + .Q(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_13_), + .CLK(NlwRenamedSig_OI_trn_clk), + .Q15(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_in_85_), + .A0(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[0]), + .A1(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[1]), + .A2(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[2]), + .A3(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[3]) + ); + SRLC16E com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_srlrow_1__srlcol_22__srlinst ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_select_oq2bq_4169), + .D(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_in_94_), + .Q(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_94_), + .CLK(NlwRenamedSig_OI_trn_clk), + .Q15(NLW_com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_srlrow_1__srlcol_22__srlinst_Q15_UNCONNECTED), + .A0(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[0]), + .A1(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[1]), + .A2(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[2]), + .A3(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[3]) + ); + SRLC16E com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_srlrow_1__srlcol_61__srlinst ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_select_oq2bq_1_4168), + .D(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_in_133_), + .Q(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_133_), + .CLK(NlwRenamedSig_OI_trn_clk), + .Q15(NLW_com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_srlrow_1__srlcol_61__srlinst_Q15_UNCONNECTED), + .A0(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[0]), + .A1(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[1]), + .A2(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[2]), + .A3(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[3]) + ); + SRLC16E com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_srlrow_1__srlcol_57__srlinst ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_select_oq2bq_1_4168), + .D(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_in_129_), + .Q(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_129_), + .CLK(NlwRenamedSig_OI_trn_clk), + .Q15(NLW_com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_srlrow_1__srlcol_57__srlinst_Q15_UNCONNECTED), + .A0(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[0]), + .A1(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[1]), + .A2(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[2]), + .A3(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[3]) + ); + SRLC16E com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_srlrow_1__srlcol_23__srlinst ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_select_oq2bq_4169), + .D(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_in_95_), + .Q(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_95_), + .CLK(NlwRenamedSig_OI_trn_clk), + .Q15(NLW_com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_srlrow_1__srlcol_23__srlinst_Q15_UNCONNECTED), + .A0(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[0]), + .A1(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[1]), + .A2(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[2]), + .A3(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[3]) + ); + SRLC16E com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_srlrow_0__srlcol_55__srlinst ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_select_oq2bq_1_4168), + .D(com_tlm_u_tlm_rx_vc0_fifo_data_oqr_55_), + .Q(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_55_), + .CLK(NlwRenamedSig_OI_trn_clk), + .Q15(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_in_127_), + .A0(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[0]), + .A1(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[1]), + .A2(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[2]), + .A3(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[3]) + ); + SRLC16E com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_srlrow_0__srlcol_15__srlinst ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_select_oq2bq_4169), + .D(com_tlm_u_tlm_rx_vc0_fifo_data_oqr_15_), + .Q(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_15_), + .CLK(NlwRenamedSig_OI_trn_clk), + .Q15(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_in_87_), + .A0(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[0]), + .A1(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[1]), + .A2(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[2]), + .A3(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[3]) + ); + SRLC16E com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_srlrow_1__srlcol_24__srlinst ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_select_oq2bq_4169), + .D(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_in_96_), + .Q(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_96_), + .CLK(NlwRenamedSig_OI_trn_clk), + .Q15(NLW_com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_srlrow_1__srlcol_24__srlinst_Q15_UNCONNECTED), + .A0(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[0]), + .A1(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[1]), + .A2(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[2]), + .A3(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[3]) + ); + SRLC16E com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_srlrow_0__srlcol_56__srlinst ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_select_oq2bq_1_4168), + .D(com_tlm_u_tlm_rx_vc0_fifo_data_oqr_56_), + .Q(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_56_), + .CLK(NlwRenamedSig_OI_trn_clk), + .Q15(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_in_128_), + .A0(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[0]), + .A1(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[1]), + .A2(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[2]), + .A3(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[3]) + ); + SRLC16E com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_srlrow_0__srlcol_16__srlinst ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_select_oq2bq_4169), + .D(com_tlm_u_tlm_rx_vc0_fifo_data_oqr_16_), + .Q(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_16_), + .CLK(NlwRenamedSig_OI_trn_clk), + .Q15(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_in_88_), + .A0(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[0]), + .A1(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[1]), + .A2(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[2]), + .A3(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[3]) + ); + SRLC16E com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_srlrow_1__srlcol_25__srlinst ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_select_oq2bq_4169), + .D(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_in_97_), + .Q(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_97_), + .CLK(NlwRenamedSig_OI_trn_clk), + .Q15(NLW_com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_srlrow_1__srlcol_25__srlinst_Q15_UNCONNECTED), + .A0(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[0]), + .A1(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[1]), + .A2(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[2]), + .A3(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[3]) + ); + SRLC16E com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_srlrow_1__srlcol_26__srlinst ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_select_oq2bq_4169), + .D(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_in_98_), + .Q(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_98_), + .CLK(NlwRenamedSig_OI_trn_clk), + .Q15(NLW_com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_srlrow_1__srlcol_26__srlinst_Q15_UNCONNECTED), + .A0(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[0]), + .A1(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[1]), + .A2(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[2]), + .A3(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[3]) + ); + SRLC16E com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_srlrow_0__srlcol_58__srlinst ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_select_oq2bq_1_4168), + .D(com_tlm_u_tlm_rx_vc0_fifo_data_oqr_58_), + .Q(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_58_), + .CLK(NlwRenamedSig_OI_trn_clk), + .Q15(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_in_130_), + .A0(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[0]), + .A1(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[1]), + .A2(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[2]), + .A3(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[3]) + ); + SRLC16E com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_srlrow_0__srlcol_18__srlinst ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_select_oq2bq_4169), + .D(com_tlm_u_tlm_rx_vc0_fifo_data_oqr_18_), + .Q(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_18_), + .CLK(NlwRenamedSig_OI_trn_clk), + .Q15(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_in_90_), + .A0(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[0]), + .A1(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[1]), + .A2(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[2]), + .A3(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[3]) + ); + SRLC16E com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_srlrow_1__srlcol_27__srlinst ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_select_oq2bq_4169), + .D(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_in_99_), + .Q(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_99_), + .CLK(NlwRenamedSig_OI_trn_clk), + .Q15(NLW_com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_srlrow_1__srlcol_27__srlinst_Q15_UNCONNECTED), + .A0(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[0]), + .A1(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[1]), + .A2(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[2]), + .A3(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[3]) + ); + SRLC16E com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_srlrow_0__srlcol_59__srlinst ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_select_oq2bq_1_4168), + .D(com_tlm_u_tlm_rx_vc0_fifo_data_oqr_59_), + .Q(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_59_), + .CLK(NlwRenamedSig_OI_trn_clk), + .Q15(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_in_131_), + .A0(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[0]), + .A1(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[1]), + .A2(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[2]), + .A3(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[3]) + ); + SRLC16E com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_srlrow_0__srlcol_19__srlinst ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_select_oq2bq_4169), + .D(com_tlm_u_tlm_rx_vc0_fifo_data_oqr_19_), + .Q(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_19_), + .CLK(NlwRenamedSig_OI_trn_clk), + .Q15(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_in_91_), + .A0(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[0]), + .A1(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[1]), + .A2(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[2]), + .A3(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[3]) + ); + SRLC16E com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_srlrow_1__srlcol_28__srlinst ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_select_oq2bq_4169), + .D(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_in_100_), + .Q(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_100_), + .CLK(NlwRenamedSig_OI_trn_clk), + .Q15(NLW_com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_srlrow_1__srlcol_28__srlinst_Q15_UNCONNECTED), + .A0(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[0]), + .A1(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[1]), + .A2(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[2]), + .A3(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[3]) + ); + SRLC16E com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_srlrow_1__srlcol_67__srlinst ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_select_oq2bq_1_4168), + .D(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_in_139_), + .Q(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_139_), + .CLK(NlwRenamedSig_OI_trn_clk), + .Q15(NLW_com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_srlrow_1__srlcol_67__srlinst_Q15_UNCONNECTED), + .A0(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[0]), + .A1(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[1]), + .A2(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[2]), + .A3(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[3]) + ); + SRLC16E com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_srlrow_1__srlcol_63__srlinst ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_select_oq2bq_1_4168), + .D(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_in_135_), + .Q(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_135_), + .CLK(NlwRenamedSig_OI_trn_clk), + .Q15(NLW_com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_srlrow_1__srlcol_63__srlinst_Q15_UNCONNECTED), + .A0(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[0]), + .A1(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[1]), + .A2(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[2]), + .A3(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[3]) + ); + SRLC16E com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_srlrow_1__srlcol_29__srlinst ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_select_oq2bq_4169), + .D(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_in_101_), + .Q(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_101_), + .CLK(NlwRenamedSig_OI_trn_clk), + .Q15(NLW_com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_srlrow_1__srlcol_29__srlinst_Q15_UNCONNECTED), + .A0(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[0]), + .A1(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[1]), + .A2(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[2]), + .A3(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[3]) + ); + SRLC16E com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_srlrow_0__srlcol_61__srlinst ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_select_oq2bq_1_4168), + .D(com_tlm_u_tlm_rx_vc0_fifo_data_oqr_61_), + .Q(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_61_), + .CLK(NlwRenamedSig_OI_trn_clk), + .Q15(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_in_133_), + .A0(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[0]), + .A1(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[1]), + .A2(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[2]), + .A3(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[3]) + ); + SRLC16E com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_srlrow_1__srlcol_21__srlinst ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_select_oq2bq_4169), + .D(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_in_93_), + .Q(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_93_), + .CLK(NlwRenamedSig_OI_trn_clk), + .Q15(NLW_com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_srlrow_1__srlcol_21__srlinst_Q15_UNCONNECTED), + .A0(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[0]), + .A1(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[1]), + .A2(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[2]), + .A3(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[3]) + ); + SRLC16E com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_srlrow_0__srlcol_53__srlinst ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_select_oq2bq_1_4168), + .D(com_tlm_u_tlm_rx_vc0_fifo_data_oqr_53_), + .Q(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_53_), + .CLK(NlwRenamedSig_OI_trn_clk), + .Q15(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_in_125_), + .A0(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[0]), + .A1(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[1]), + .A2(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[2]), + .A3(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[3]) + ); + SRLC16E com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_srlrow_0__srlcol_62__srlinst ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_select_oq2bq_1_4168), + .D(com_tlm_u_tlm_rx_vc0_fifo_data_oqr_62_), + .Q(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_62_), + .CLK(NlwRenamedSig_OI_trn_clk), + .Q15(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_in_134_), + .A0(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[0]), + .A1(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[1]), + .A2(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[2]), + .A3(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[3]) + ); + SRLC16E com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_srlrow_0__srlcol_22__srlinst ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_select_oq2bq_4169), + .D(com_tlm_u_tlm_rx_vc0_fifo_data_oqr_22_), + .Q(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_22_), + .CLK(NlwRenamedSig_OI_trn_clk), + .Q15(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_in_94_), + .A0(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[0]), + .A1(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[1]), + .A2(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[2]), + .A3(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[3]) + ); + SRLC16E com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_srlrow_1__srlcol_31__srlinst ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_select_oq2bq_1_4168), + .D(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_in_103_), + .Q(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_103_), + .CLK(NlwRenamedSig_OI_trn_clk), + .Q15(NLW_com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_srlrow_1__srlcol_31__srlinst_Q15_UNCONNECTED), + .A0(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[0]), + .A1(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[1]), + .A2(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[2]), + .A3(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[3]) + ); + SRLC16E com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_srlrow_0__srlcol_63__srlinst ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_select_oq2bq_1_4168), + .D(com_tlm_u_tlm_rx_vc0_fifo_data_oqr_63_), + .Q(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_63_), + .CLK(NlwRenamedSig_OI_trn_clk), + .Q15(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_in_135_), + .A0(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[0]), + .A1(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[1]), + .A2(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[2]), + .A3(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[3]) + ); + SRLC16E com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_srlrow_0__srlcol_23__srlinst ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_select_oq2bq_4169), + .D(com_tlm_u_tlm_rx_vc0_fifo_data_oqr_23_), + .Q(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_23_), + .CLK(NlwRenamedSig_OI_trn_clk), + .Q15(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_in_95_), + .A0(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[0]), + .A1(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[1]), + .A2(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[2]), + .A3(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[3]) + ); + SRLC16E com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_srlrow_1__srlcol_32__srlinst ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_select_oq2bq_1_4168), + .D(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_in_104_), + .Q(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_104_), + .CLK(NlwRenamedSig_OI_trn_clk), + .Q15(NLW_com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_srlrow_1__srlcol_32__srlinst_Q15_UNCONNECTED), + .A0(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[0]), + .A1(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[1]), + .A2(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[2]), + .A3(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[3]) + ); + SRLC16E com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_srlrow_0__srlcol_64__srlinst ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_select_oq2bq_1_4168), + .D(com_tlm_u_tlm_rx_vc0_fifo_N_44135_i), + .Q(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_64_), + .CLK(NlwRenamedSig_OI_trn_clk), + .Q15(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_in_136_), + .A0(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[0]), + .A1(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[1]), + .A2(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[2]), + .A3(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[3]) + ); + SRLC16E com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_srlrow_0__srlcol_24__srlinst ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_select_oq2bq_4169), + .D(com_tlm_u_tlm_rx_vc0_fifo_data_oqr_24_), + .Q(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_24_), + .CLK(NlwRenamedSig_OI_trn_clk), + .Q15(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_in_96_), + .A0(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[0]), + .A1(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[1]), + .A2(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[2]), + .A3(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[3]) + ); + SRLC16E com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_srlrow_1__srlcol_33__srlinst ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_select_oq2bq_1_4168), + .D(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_in_105_), + .Q(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_105_), + .CLK(NlwRenamedSig_OI_trn_clk), + .Q15(NLW_com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_srlrow_1__srlcol_33__srlinst_Q15_UNCONNECTED), + .A0(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[0]), + .A1(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[1]), + .A2(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[2]), + .A3(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[3]) + ); + SRLC16E com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_srlrow_0__srlcol_65__srlinst ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_select_oq2bq_1_4168), + .D(com_tlm_u_tlm_rx_vc0_fifo_eof_oqr), + .Q(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_65_), + .CLK(NlwRenamedSig_OI_trn_clk), + .Q15(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_in_137_), + .A0(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[0]), + .A1(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[1]), + .A2(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[2]), + .A3(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[3]) + ); + SRLC16E com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_srlrow_0__srlcol_25__srlinst ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_select_oq2bq_4169), + .D(com_tlm_u_tlm_rx_vc0_fifo_data_oqr_25_), + .Q(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_25_), + .CLK(NlwRenamedSig_OI_trn_clk), + .Q15(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_in_97_), + .A0(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[0]), + .A1(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[1]), + .A2(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[2]), + .A3(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[3]) + ); + SRLC16E com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_srlrow_1__srlcol_34__srlinst ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_select_oq2bq_1_4168), + .D(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_in_106_), + .Q(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_106_), + .CLK(NlwRenamedSig_OI_trn_clk), + .Q15(NLW_com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_srlrow_1__srlcol_34__srlinst_Q15_UNCONNECTED), + .A0(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[0]), + .A1(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[1]), + .A2(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[2]), + .A3(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[3]) + ); + SRLC16E com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_srlrow_0__srlcol_26__srlinst ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_select_oq2bq_4169), + .D(com_tlm_u_tlm_rx_vc0_fifo_data_oqr_26_), + .Q(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_26_), + .CLK(NlwRenamedSig_OI_trn_clk), + .Q15(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_in_98_), + .A0(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[0]), + .A1(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[1]), + .A2(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[2]), + .A3(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[3]) + ); + SRLC16E com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_srlrow_1__srlcol_35__srlinst ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_select_oq2bq_1_4168), + .D(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_in_107_), + .Q(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_107_), + .CLK(NlwRenamedSig_OI_trn_clk), + .Q15(NLW_com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_srlrow_1__srlcol_35__srlinst_Q15_UNCONNECTED), + .A0(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[0]), + .A1(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[1]), + .A2(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[2]), + .A3(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[3]) + ); + SRLC16E com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_srlrow_0__srlcol_67__srlinst ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_select_oq2bq_1_4168), + .D(com_tlm_u_tlm_rx_vc0_fifo_rem_oqr), + .Q(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_67_), + .CLK(NlwRenamedSig_OI_trn_clk), + .Q15(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_in_139_), + .A0(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[0]), + .A1(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[1]), + .A2(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[2]), + .A3(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[3]) + ); + SRLC16E com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_srlrow_0__srlcol_27__srlinst ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_select_oq2bq_4169), + .D(com_tlm_u_tlm_rx_vc0_fifo_data_oqr_27_), + .Q(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_27_), + .CLK(NlwRenamedSig_OI_trn_clk), + .Q15(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_in_99_), + .A0(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[0]), + .A1(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[1]), + .A2(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[2]), + .A3(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[3]) + ); + SRLC16E com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_srlrow_1__srlcol_36__srlinst ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_select_oq2bq_1_4168), + .D(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_in_108_), + .Q(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_108_), + .CLK(NlwRenamedSig_OI_trn_clk), + .Q15(NLW_com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_srlrow_1__srlcol_36__srlinst_Q15_UNCONNECTED), + .A0(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[0]), + .A1(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[1]), + .A2(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[2]), + .A3(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[3]) + ); + SRLC16E com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_srlrow_0__srlcol_28__srlinst ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_select_oq2bq_4169), + .D(com_tlm_u_tlm_rx_vc0_fifo_data_oqr_28_), + .Q(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_28_), + .CLK(NlwRenamedSig_OI_trn_clk), + .Q15(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_in_100_), + .A0(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[0]), + .A1(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[1]), + .A2(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[2]), + .A3(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[3]) + ); + SRLC16E com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_srlrow_1__srlcol_37__srlinst ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_select_oq2bq_1_4168), + .D(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_in_109_), + .Q(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_109_), + .CLK(NlwRenamedSig_OI_trn_clk), + .Q15(NLW_com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_srlrow_1__srlcol_37__srlinst_Q15_UNCONNECTED), + .A0(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[0]), + .A1(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[1]), + .A2(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[2]), + .A3(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[3]) + ); + SRLC16E com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_srlrow_0__srlcol_29__srlinst ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_select_oq2bq_4169), + .D(com_tlm_u_tlm_rx_vc0_fifo_data_oqr_29_), + .Q(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_29_), + .CLK(NlwRenamedSig_OI_trn_clk), + .Q15(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_in_101_), + .A0(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[0]), + .A1(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[1]), + .A2(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[2]), + .A3(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[3]) + ); + SRLC16E com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_srlrow_1__srlcol_38__srlinst ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_select_oq2bq_1_4168), + .D(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_in_110_), + .Q(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_110_), + .CLK(NlwRenamedSig_OI_trn_clk), + .Q15(NLW_com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_srlrow_1__srlcol_38__srlinst_Q15_UNCONNECTED), + .A0(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[0]), + .A1(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[1]), + .A2(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[2]), + .A3(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[3]) + ); + SRLC16E com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_srlrow_0__srlcol_30__srlinst ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_select_oq2bq_1_4168), + .D(com_tlm_u_tlm_rx_vc0_fifo_data_oqr_30_), + .Q(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_30_), + .CLK(NlwRenamedSig_OI_trn_clk), + .Q15(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_in_102_), + .A0(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[0]), + .A1(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[1]), + .A2(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[2]), + .A3(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[3]) + ); + SRLC16E com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_srlrow_1__srlcol_39__srlinst ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_select_oq2bq_1_4168), + .D(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_in_111_), + .Q(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_111_), + .CLK(NlwRenamedSig_OI_trn_clk), + .Q15(NLW_com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_srlrow_1__srlcol_39__srlinst_Q15_UNCONNECTED), + .A0(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[0]), + .A1(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[1]), + .A2(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[2]), + .A3(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[3]) + ); + SRLC16E com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_srlrow_0__srlcol_31__srlinst ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_select_oq2bq_1_4168), + .D(com_tlm_u_tlm_rx_vc0_fifo_data_oqr_31_), + .Q(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_31_), + .CLK(NlwRenamedSig_OI_trn_clk), + .Q15(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_in_103_), + .A0(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[0]), + .A1(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[1]), + .A2(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[2]), + .A3(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[3]) + ); + SRLC16E com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_srlrow_1__srlcol_40__srlinst ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_select_oq2bq_1_4168), + .D(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_in_112_), + .Q(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_112_), + .CLK(NlwRenamedSig_OI_trn_clk), + .Q15(NLW_com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_srlrow_1__srlcol_40__srlinst_Q15_UNCONNECTED), + .A0(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[0]), + .A1(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[1]), + .A2(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[2]), + .A3(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[3]) + ); + SRLC16E com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_srlrow_1__srlcol_0__srlinst ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_select_oq2bq_4169), + .D(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_in_72_), + .Q(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_72_), + .CLK(NlwRenamedSig_OI_trn_clk), + .Q15(NLW_com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_srlrow_1__srlcol_0__srlinst_Q15_UNCONNECTED), + .A0(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[0]), + .A1(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[1]), + .A2(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[2]), + .A3(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[3]) + ); + SRLC16E com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_srlrow_0__srlcol_32__srlinst ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_select_oq2bq_1_4168), + .D(com_tlm_u_tlm_rx_vc0_fifo_data_oqr_32_), + .Q(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_32_), + .CLK(NlwRenamedSig_OI_trn_clk), + .Q15(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_in_104_), + .A0(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[0]), + .A1(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[1]), + .A2(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[2]), + .A3(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[3]) + ); + SRLC16E com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_srlrow_1__srlcol_41__srlinst ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_select_oq2bq_1_4168), + .D(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_in_113_), + .Q(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_113_), + .CLK(NlwRenamedSig_OI_trn_clk), + .Q15(NLW_com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_srlrow_1__srlcol_41__srlinst_Q15_UNCONNECTED), + .A0(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[0]), + .A1(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[1]), + .A2(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[2]), + .A3(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[3]) + ); + SRLC16E com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_srlrow_1__srlcol_1__srlinst ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_select_oq2bq_4169), + .D(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_in_73_), + .Q(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_73_), + .CLK(NlwRenamedSig_OI_trn_clk), + .Q15(NLW_com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_srlrow_1__srlcol_1__srlinst_Q15_UNCONNECTED), + .A0(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[0]), + .A1(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[1]), + .A2(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[2]), + .A3(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[3]) + ); + SRLC16E com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_srlrow_0__srlcol_33__srlinst ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_select_oq2bq_1_4168), + .D(com_tlm_u_tlm_rx_vc0_fifo_data_oqr_33_), + .Q(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_33_), + .CLK(NlwRenamedSig_OI_trn_clk), + .Q15(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_in_105_), + .A0(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[0]), + .A1(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[1]), + .A2(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[2]), + .A3(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[3]) + ); + SRLC16E com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_srlrow_1__srlcol_42__srlinst ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_select_oq2bq_1_4168), + .D(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_in_114_), + .Q(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_114_), + .CLK(NlwRenamedSig_OI_trn_clk), + .Q15(NLW_com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_srlrow_1__srlcol_42__srlinst_Q15_UNCONNECTED), + .A0(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[0]), + .A1(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[1]), + .A2(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[2]), + .A3(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[3]) + ); + SRLC16E com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_srlrow_1__srlcol_2__srlinst ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_select_oq2bq_4169), + .D(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_in_74_), + .Q(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_74_), + .CLK(NlwRenamedSig_OI_trn_clk), + .Q15(NLW_com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_srlrow_1__srlcol_2__srlinst_Q15_UNCONNECTED), + .A0(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[0]), + .A1(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[1]), + .A2(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[2]), + .A3(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[3]) + ); + SRLC16E com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_srlrow_0__srlcol_34__srlinst ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_select_oq2bq_1_4168), + .D(com_tlm_u_tlm_rx_vc0_fifo_data_oqr_34_), + .Q(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_34_), + .CLK(NlwRenamedSig_OI_trn_clk), + .Q15(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_in_106_), + .A0(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[0]), + .A1(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[1]), + .A2(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[2]), + .A3(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[3]) + ); + SRLC16E com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_srlrow_1__srlcol_43__srlinst ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_select_oq2bq_1_4168), + .D(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_in_115_), + .Q(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_115_), + .CLK(NlwRenamedSig_OI_trn_clk), + .Q15(NLW_com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_srlrow_1__srlcol_43__srlinst_Q15_UNCONNECTED), + .A0(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[0]), + .A1(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[1]), + .A2(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[2]), + .A3(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[3]) + ); + SRLC16E com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_srlrow_1__srlcol_3__srlinst ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_select_oq2bq_4169), + .D(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_in_75_), + .Q(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_75_), + .CLK(NlwRenamedSig_OI_trn_clk), + .Q15(NLW_com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_srlrow_1__srlcol_3__srlinst_Q15_UNCONNECTED), + .A0(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[0]), + .A1(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[1]), + .A2(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[2]), + .A3(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[3]) + ); + SRLC16E com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_srlrow_0__srlcol_35__srlinst ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_select_oq2bq_1_4168), + .D(com_tlm_u_tlm_rx_vc0_fifo_data_oqr_35_), + .Q(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_35_), + .CLK(NlwRenamedSig_OI_trn_clk), + .Q15(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_in_107_), + .A0(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[0]), + .A1(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[1]), + .A2(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[2]), + .A3(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[3]) + ); + SRLC16E com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_srlrow_1__srlcol_44__srlinst ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_select_oq2bq_1_4168), + .D(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_in_116_), + .Q(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_116_), + .CLK(NlwRenamedSig_OI_trn_clk), + .Q15(NLW_com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_srlrow_1__srlcol_44__srlinst_Q15_UNCONNECTED), + .A0(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[0]), + .A1(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[1]), + .A2(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[2]), + .A3(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[3]) + ); + SRLC16E com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_srlrow_1__srlcol_4__srlinst ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_select_oq2bq_4169), + .D(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_in_76_), + .Q(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_76_), + .CLK(NlwRenamedSig_OI_trn_clk), + .Q15(NLW_com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_srlrow_1__srlcol_4__srlinst_Q15_UNCONNECTED), + .A0(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[0]), + .A1(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[1]), + .A2(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[2]), + .A3(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[3]) + ); + SRLC16E com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_srlrow_0__srlcol_36__srlinst ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_select_oq2bq_1_4168), + .D(com_tlm_u_tlm_rx_vc0_fifo_data_oqr_36_), + .Q(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_36_), + .CLK(NlwRenamedSig_OI_trn_clk), + .Q15(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_in_108_), + .A0(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[0]), + .A1(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[1]), + .A2(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[2]), + .A3(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[3]) + ); + SRLC16E com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_srlrow_1__srlcol_45__srlinst ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_select_oq2bq_1_4168), + .D(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_in_117_), + .Q(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_117_), + .CLK(NlwRenamedSig_OI_trn_clk), + .Q15(NLW_com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_srlrow_1__srlcol_45__srlinst_Q15_UNCONNECTED), + .A0(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[0]), + .A1(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[1]), + .A2(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[2]), + .A3(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[3]) + ); + SRLC16E com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_srlrow_1__srlcol_5__srlinst ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_select_oq2bq_4169), + .D(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_in_77_), + .Q(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_77_), + .CLK(NlwRenamedSig_OI_trn_clk), + .Q15(NLW_com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_srlrow_1__srlcol_5__srlinst_Q15_UNCONNECTED), + .A0(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[0]), + .A1(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[1]), + .A2(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[2]), + .A3(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[3]) + ); + SRLC16E com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_srlrow_0__srlcol_37__srlinst ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_select_oq2bq_1_4168), + .D(com_tlm_u_tlm_rx_vc0_fifo_data_oqr_37_), + .Q(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_37_), + .CLK(NlwRenamedSig_OI_trn_clk), + .Q15(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_in_109_), + .A0(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[0]), + .A1(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[1]), + .A2(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[2]), + .A3(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[3]) + ); + SRLC16E com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_srlrow_1__srlcol_46__srlinst ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_select_oq2bq_1_4168), + .D(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_in_118_), + .Q(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_118_), + .CLK(NlwRenamedSig_OI_trn_clk), + .Q15(NLW_com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_srlrow_1__srlcol_46__srlinst_Q15_UNCONNECTED), + .A0(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[0]), + .A1(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[1]), + .A2(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[2]), + .A3(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[3]) + ); + SRLC16E com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_srlrow_1__srlcol_6__srlinst ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_select_oq2bq_4169), + .D(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_in_78_), + .Q(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_78_), + .CLK(NlwRenamedSig_OI_trn_clk), + .Q15(NLW_com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_srlrow_1__srlcol_6__srlinst_Q15_UNCONNECTED), + .A0(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[0]), + .A1(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[1]), + .A2(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[2]), + .A3(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[3]) + ); + SRLC16E com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_srlrow_0__srlcol_45__srlinst ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_select_oq2bq_1_4168), + .D(com_tlm_u_tlm_rx_vc0_fifo_data_oqr_45_), + .Q(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_45_), + .CLK(NlwRenamedSig_OI_trn_clk), + .Q15(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_in_117_), + .A0(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[0]), + .A1(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[1]), + .A2(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[2]), + .A3(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[3]) + ); + SRLC16E com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_srlrow_0__srlcol_5__srlinst ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_select_oq2bq_4169), + .D(com_tlm_u_tlm_rx_vc0_fifo_data_oqr_5_), + .Q(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_5_), + .CLK(NlwRenamedSig_OI_trn_clk), + .Q15(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_in_77_), + .A0(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[0]), + .A1(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[1]), + .A2(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[2]), + .A3(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[3]) + ); + SRLC16E com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_srlrow_1__srlcol_7__srlinst ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_select_oq2bq_4169), + .D(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_in_79_), + .Q(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_79_), + .CLK(NlwRenamedSig_OI_trn_clk), + .Q15(NLW_com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_srlrow_1__srlcol_7__srlinst_Q15_UNCONNECTED), + .A0(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[0]), + .A1(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[1]), + .A2(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[2]), + .A3(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[3]) + ); + SRLC16E com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_srlrow_0__srlcol_39__srlinst ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_select_oq2bq_1_4168), + .D(com_tlm_u_tlm_rx_vc0_fifo_data_oqr_39_), + .Q(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_39_), + .CLK(NlwRenamedSig_OI_trn_clk), + .Q15(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_in_111_), + .A0(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[0]), + .A1(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[1]), + .A2(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[2]), + .A3(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[3]) + ); + SRLC16E com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_srlrow_1__srlcol_12__srlinst ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_select_oq2bq_4169), + .D(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_in_84_), + .Q(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_84_), + .CLK(NlwRenamedSig_OI_trn_clk), + .Q15(NLW_com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_srlrow_1__srlcol_12__srlinst_Q15_UNCONNECTED), + .A0(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[0]), + .A1(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[1]), + .A2(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[2]), + .A3(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[3]) + ); + SRLC16E com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_srlrow_0__srlcol_44__srlinst ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_select_oq2bq_1_4168), + .D(com_tlm_u_tlm_rx_vc0_fifo_data_oqr_44_), + .Q(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_44_), + .CLK(NlwRenamedSig_OI_trn_clk), + .Q15(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_in_116_), + .A0(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[0]), + .A1(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[1]), + .A2(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[2]), + .A3(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[3]) + ); + SRLC16E com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_srlrow_0__srlcol_40__srlinst ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_select_oq2bq_1_4168), + .D(com_tlm_u_tlm_rx_vc0_fifo_data_oqr_40_), + .Q(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_40_), + .CLK(NlwRenamedSig_OI_trn_clk), + .Q15(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_in_112_), + .A0(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[0]), + .A1(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[1]), + .A2(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[2]), + .A3(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[3]) + ); + SRLC16E com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_srlrow_1__srlcol_49__srlinst ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_select_oq2bq_1_4168), + .D(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_in_121_), + .Q(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_121_), + .CLK(NlwRenamedSig_OI_trn_clk), + .Q15(NLW_com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_srlrow_1__srlcol_49__srlinst_Q15_UNCONNECTED), + .A0(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[0]), + .A1(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[1]), + .A2(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[2]), + .A3(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[3]) + ); + SRLC16E com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_srlrow_1__srlcol_15__srlinst ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_select_oq2bq_4169), + .D(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_in_87_), + .Q(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_87_), + .CLK(NlwRenamedSig_OI_trn_clk), + .Q15(NLW_com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_srlrow_1__srlcol_15__srlinst_Q15_UNCONNECTED), + .A0(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[0]), + .A1(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[1]), + .A2(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[2]), + .A3(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[3]) + ); + SRLC16E com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_srlrow_0__srlcol_47__srlinst ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_select_oq2bq_1_4168), + .D(com_tlm_u_tlm_rx_vc0_fifo_data_oqr_47_), + .Q(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_47_), + .CLK(NlwRenamedSig_OI_trn_clk), + .Q15(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_in_119_), + .A0(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[0]), + .A1(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[1]), + .A2(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[2]), + .A3(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[3]) + ); + SRLC16E com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_srlrow_1__srlcol_50__srlinst ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_select_oq2bq_1_4168), + .D(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_in_122_), + .Q(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_122_), + .CLK(NlwRenamedSig_OI_trn_clk), + .Q15(NLW_com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_srlrow_1__srlcol_50__srlinst_Q15_UNCONNECTED), + .A0(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[0]), + .A1(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[1]), + .A2(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[2]), + .A3(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[3]) + ); + SRLC16E com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_srlrow_1__srlcol_64__srlinst ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_select_oq2bq_1_4168), + .D(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_in_136_), + .Q(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_136_), + .CLK(NlwRenamedSig_OI_trn_clk), + .Q15(NLW_com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_srlrow_1__srlcol_64__srlinst_Q15_UNCONNECTED), + .A0(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[0]), + .A1(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[1]), + .A2(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[2]), + .A3(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[3]) + ); + SRLC16E com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_srlrow_1__srlcol_51__srlinst ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_select_oq2bq_1_4168), + .D(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_in_123_), + .Q(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_123_), + .CLK(NlwRenamedSig_OI_trn_clk), + .Q15(NLW_com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_srlrow_1__srlcol_51__srlinst_Q15_UNCONNECTED), + .A0(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[0]), + .A1(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[1]), + .A2(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[2]), + .A3(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[3]) + ); + SRLC16E com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_srlrow_1__srlcol_65__srlinst ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_select_oq2bq_1_4168), + .D(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_in_137_), + .Q(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_137_), + .CLK(NlwRenamedSig_OI_trn_clk), + .Q15(NLW_com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_srlrow_1__srlcol_65__srlinst_Q15_UNCONNECTED), + .A0(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[0]), + .A1(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[1]), + .A2(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[2]), + .A3(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[3]) + ); + SRLC16E com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_srlrow_1__srlcol_52__srlinst ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_select_oq2bq_1_4168), + .D(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_in_124_), + .Q(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_124_), + .CLK(NlwRenamedSig_OI_trn_clk), + .Q15(NLW_com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_srlrow_1__srlcol_52__srlinst_Q15_UNCONNECTED), + .A0(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[0]), + .A1(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[1]), + .A2(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[2]), + .A3(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[3]) + ); + SRLC16E com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_srlrow_1__srlcol_48__srlinst ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_select_oq2bq_1_4168), + .D(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_in_120_), + .Q(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_120_), + .CLK(NlwRenamedSig_OI_trn_clk), + .Q15(NLW_com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_srlrow_1__srlcol_48__srlinst_Q15_UNCONNECTED), + .A0(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[0]), + .A1(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[1]), + .A2(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[2]), + .A3(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[3]) + ); + SRLC16E com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_srlrow_1__srlcol_8__srlinst ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_select_oq2bq_4169), + .D(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_in_80_), + .Q(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_80_), + .CLK(NlwRenamedSig_OI_trn_clk), + .Q15(NLW_com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_srlrow_1__srlcol_8__srlinst_Q15_UNCONNECTED), + .A0(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[0]), + .A1(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[1]), + .A2(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[2]), + .A3(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[3]) + ); + SRLC16E com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_srlrow_1__srlcol_53__srlinst ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_select_oq2bq_1_4168), + .D(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_in_125_), + .Q(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_125_), + .CLK(NlwRenamedSig_OI_trn_clk), + .Q15(NLW_com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_srlrow_1__srlcol_53__srlinst_Q15_UNCONNECTED), + .A0(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[0]), + .A1(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[1]), + .A2(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[2]), + .A3(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[3]) + ); + SRLC16E com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_srlrow_1__srlcol_58__srlinst ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_select_oq2bq_1_4168), + .D(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_in_130_), + .Q(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_130_), + .CLK(NlwRenamedSig_OI_trn_clk), + .Q15(NLW_com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_srlrow_1__srlcol_58__srlinst_Q15_UNCONNECTED), + .A0(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[0]), + .A1(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[1]), + .A2(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[2]), + .A3(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[3]) + ); + SRLC16E com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_srlrow_1__srlcol_54__srlinst ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_select_oq2bq_1_4168), + .D(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_in_126_), + .Q(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_126_), + .CLK(NlwRenamedSig_OI_trn_clk), + .Q15(NLW_com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_srlrow_1__srlcol_54__srlinst_Q15_UNCONNECTED), + .A0(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[0]), + .A1(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[1]), + .A2(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[2]), + .A3(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[3]) + ); + SRLC16E com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_srlrow_1__srlcol_60__srlinst ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_select_oq2bq_1_4168), + .D(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_in_132_), + .Q(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_132_), + .CLK(NlwRenamedSig_OI_trn_clk), + .Q15(NLW_com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_srlrow_1__srlcol_60__srlinst_Q15_UNCONNECTED), + .A0(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[0]), + .A1(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[1]), + .A2(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[2]), + .A3(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[3]) + ); + SRLC16E com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_srlrow_1__srlcol_59__srlinst ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_select_oq2bq_1_4168), + .D(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_in_131_), + .Q(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_131_), + .CLK(NlwRenamedSig_OI_trn_clk), + .Q15(NLW_com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_srlrow_1__srlcol_59__srlinst_Q15_UNCONNECTED), + .A0(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[0]), + .A1(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[1]), + .A2(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[2]), + .A3(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[3]) + ); + SRLC16E com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_srlrow_1__srlcol_55__srlinst ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_select_oq2bq_1_4168), + .D(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_in_127_), + .Q(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_127_), + .CLK(NlwRenamedSig_OI_trn_clk), + .Q15(NLW_com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_srlrow_1__srlcol_55__srlinst_Q15_UNCONNECTED), + .A0(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[0]), + .A1(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[1]), + .A2(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[2]), + .A3(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[3]) + ); + SRLC16E com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_srlrow_0__srlcol_38__srlinst ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_select_oq2bq_1_4168), + .D(com_tlm_u_tlm_rx_vc0_fifo_data_oqr_38_), + .Q(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_38_), + .CLK(NlwRenamedSig_OI_trn_clk), + .Q15(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_in_110_), + .A0(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[0]), + .A1(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[1]), + .A2(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[2]), + .A3(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[3]) + ); + SRLC16E com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_srlrow_1__srlcol_47__srlinst ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_select_oq2bq_1_4168), + .D(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_in_119_), + .Q(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_119_), + .CLK(NlwRenamedSig_OI_trn_clk), + .Q15(NLW_com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_srlrow_1__srlcol_47__srlinst_Q15_UNCONNECTED), + .A0(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[0]), + .A1(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[1]), + .A2(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[2]), + .A3(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[3]) + ); + SRLC16E com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_srlrow_1__srlcol_56__srlinst ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_select_oq2bq_1_4168), + .D(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_in_128_), + .Q(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_128_), + .CLK(NlwRenamedSig_OI_trn_clk), + .Q15(NLW_com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_srlrow_1__srlcol_56__srlinst_Q15_UNCONNECTED), + .A0(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[0]), + .A1(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[1]), + .A2(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[2]), + .A3(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[3]) + ); + SRLC16E com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_srlrow_1__srlcol_62__srlinst ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_select_oq2bq_1_4168), + .D(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_in_134_), + .Q(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_134_), + .CLK(NlwRenamedSig_OI_trn_clk), + .Q15(NLW_com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_srlrow_1__srlcol_62__srlinst_Q15_UNCONNECTED), + .A0(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[0]), + .A1(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[1]), + .A2(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[2]), + .A3(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[3]) + ); + FDS com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_0_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_un1_raddr_lo_1_axb_0_4391), + .Q(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[0]), + .S(plm_link_up_i) + ); + FDS com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_un1_raddr_lo_1_s_1_5), + .Q(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[1]), + .S(plm_link_up_i) + ); + FDS com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_2_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_un1_raddr_lo_1_s_2_5), + .Q(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[2]), + .S(plm_link_up_i) + ); + FDS com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_3_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_un1_raddr_lo_1_s_3_5), + .Q(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[3]), + .S(plm_link_up_i) + ); + FDRE com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_hi_0_ ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_un1_bkp_i_3_i_4380), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_hi_71[0]), + .Q(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_hi[0]), + .R(plm_link_up_i) + ); + FDRE com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_hi_1_ ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_un1_bkp_i_3_i_4380), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_hi_71[1]), + .Q(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_hi[1]), + .R(plm_link_up_i) + ); + FDRE com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_control_bits_d_o_64_ ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_86095_i_4455), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_d_o_d_m_64__4386), + .Q(com_tlm_u_tlm_rx_vc0_fifo_data_bqr_64_), + .R(plm_link_up_i) + ); + FDRE com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_control_bits_d_o_65_ ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_86095_i_4455), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_d_o_d_m_65__4385), + .Q(com_tlm_u_tlm_rx_vc0_fifo_data_bqr_65_), + .R(plm_link_up_i) + ); + FDRE com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_control_bits_d_o_67_ ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_86095_i_4455), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_d_o_d_m_67__4384), + .Q(com_tlm_u_tlm_rx_vc0_fifo_data_bqr_67_), + .R(plm_link_up_i) + ); + FDRE com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_nxt_vld_o ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_un1_bkp_i_1_i_4379), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_hi_eq_1_m_i_4383), + .Q(com_tlm_u_tlm_rx_vc0_fifo_nxt_vld_bqr), + .R(plm_link_up_i) + ); + FDRE com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_vld_o ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_86095_i_4455), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_nxt_vld_bqr), + .Q(com_tlm_u_tlm_rx_vc0_fifo_data_vld_bqr), + .R(plm_link_up_i) + ); + MUXCY_L com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_un1_raddr_lo_1_cry_0 ( + .CI(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_GND_4373), + .DI(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[0]), + .LO(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_un1_raddr_lo_1_cry_0_4374), + .S(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_un1_raddr_lo_1_axb_0_4391) + ); + MUXCY_L com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_un1_raddr_lo_1_cry_1 ( + .CI(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_un1_raddr_lo_1_cry_0_4374), + .DI(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[1]), + .LO(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_un1_raddr_lo_1_cry_1_4375), + .S(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_un1_raddr_lo_1_axb_1_4389) + ); + XORCY com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_un1_raddr_lo_1_s_1 ( + .CI(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_un1_raddr_lo_1_cry_0_4374), + .LI(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_un1_raddr_lo_1_axb_1_4389), + .O(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_un1_raddr_lo_1_s_1_5) + ); + MUXCY_L com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_un1_raddr_lo_1_cry_2 ( + .CI(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_un1_raddr_lo_1_cry_1_4375), + .DI(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[2]), + .LO(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_un1_raddr_lo_1_cry_2_4376), + .S(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_un1_raddr_lo_1_axb_2_4388) + ); + XORCY com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_un1_raddr_lo_1_s_2 ( + .CI(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_un1_raddr_lo_1_cry_1_4375), + .LI(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_un1_raddr_lo_1_axb_2_4388), + .O(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_un1_raddr_lo_1_s_2_5) + ); + XORCY com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_un1_raddr_lo_1_s_3 ( + .CI(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_un1_raddr_lo_1_cry_2_4376), + .LI(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_un1_raddr_lo_1_axb_3_4387), + .O(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_un1_raddr_lo_1_s_3_5) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_outcol_multi_outcol_64__un591_d_o_d_0_.INIT = 4'h8; + LUT2 com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_outcol_multi_outcol_64__un591_d_o_d_0_ ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_hi[0]), + .I1(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_64_), + .O(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_un591_d_o_d[0]) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_outcol_multi_outcol_65__un599_d_o_d_0_.INIT = 4'h8; + LUT2 com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_outcol_multi_outcol_65__un599_d_o_d_0_ ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_hi[0]), + .I1(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_65_), + .O(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_un599_d_o_d[0]) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_outcol_multi_outcol_67__un615_d_o_d_0_.INIT = 4'h8; + LUT2 com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_outcol_multi_outcol_67__un615_d_o_d_0_ ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_hi[0]), + .I1(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_67_), + .O(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_un615_d_o_d[0]) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_overwrap_0.INIT = 4'h8; + LUT2_L com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_overwrap_0 ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[0]), + .I1(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[3]), + .LO(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_overwrap_0_4377) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_un15_nxt_vld_o_en_2.INIT = 16'h0001; + LUT4 com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_un15_nxt_vld_o_en_2 ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[0]), + .I1(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[1]), + .I2(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[2]), + .I3(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[3]), + .O(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_un15_nxt_vld_o_en_2_4378) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_overwrap_3.INIT = 16'h8000; + LUT4 com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_overwrap_3 ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[1]), + .I1(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[2]), + .I2(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_overwrap_0_4377), + .I3(com_tlm_u_tlm_rx_vc0_fifo_select_oq2bq_4169), + .O(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_overwrap_3_4382) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_d_o_0_sqmuxa.INIT = 16'h7030; + LUT4 com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_d_o_0_sqmuxa ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_N_10675_i_i), + .I1(com_tlm_u_tlm_rx_vc0_fifo_data_vld_bqr), + .I2(com_tlm_u_tlm_rx_vc0_fifo_nxt_vld_bqr), + .I3(com_tlm_u_tlm_rx_vc0_fifo_select_bq_4161), + .O(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_d_o_0_sqmuxa_4390) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_86095_i.INIT = 8'h73; + LUT3 com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_86095_i ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_N_10675_i_i), + .I1(com_tlm_u_tlm_rx_vc0_fifo_data_vld_bqr), + .I2(com_tlm_u_tlm_rx_vc0_fifo_select_bq_4161), + .O(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_86095_i_4455) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_un15_nxt_vld_o_en.INIT = 16'h4C0C; + LUT4 com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_un15_nxt_vld_o_en ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_N_10675_i_i), + .I1(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_un15_nxt_vld_o_en_2_4378), + .I2(com_tlm_u_tlm_rx_vc0_fifo_data_vld_bqr), + .I3(com_tlm_u_tlm_rx_vc0_fifo_select_bq_4161), + .O(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_un15_nxt_vld_o_en_4381) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_un1_bkp_i_1_i.INIT = 4'hE; + LUT2 com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_un1_bkp_i_1_i ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_un15_nxt_vld_o_en_4381), + .I1(com_tlm_u_tlm_rx_vc0_fifo_select_oq2bq_4169), + .O(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_un1_bkp_i_1_i_4379) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_un1_raddr_lo_1_axb_0.INIT = 8'h96; + LUT3 com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_un1_raddr_lo_1_axb_0 ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_d_o_0_sqmuxa_4390), + .I1(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[0]), + .I2(com_tlm_u_tlm_rx_vc0_fifo_select_oq2bq_4169), + .O(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_un1_raddr_lo_1_axb_0_4391) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_un1_bkp_i_3_i.INIT = 16'h44F4; + LUT4 com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_un1_bkp_i_3_i ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_d_o_0_sqmuxa_4390), + .I1(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_overwrap_3_4382), + .I2(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_un15_nxt_vld_o_en_4381), + .I3(com_tlm_u_tlm_rx_vc0_fifo_select_oq2bq_4169), + .O(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_un1_bkp_i_3_i_4380) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_10683_i.INIT = 16'hECA0; + LUT4_L com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_10683_i ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_hi[0]), + .I1(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_hi[1]), + .I2(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_63_), + .I3(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_135_), + .LO(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_10683_i_4392) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_10684_i.INIT = 16'hECA0; + LUT4_L com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_10684_i ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_hi[0]), + .I1(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_hi[1]), + .I2(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_62_), + .I3(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_134_), + .LO(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_10684_i_4393) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_10685_i.INIT = 16'hECA0; + LUT4_L com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_10685_i ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_hi[0]), + .I1(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_hi[1]), + .I2(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_61_), + .I3(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_133_), + .LO(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_10685_i_4394) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_10686_i.INIT = 16'hECA0; + LUT4_L com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_10686_i ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_hi[0]), + .I1(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_hi[1]), + .I2(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_60_), + .I3(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_132_), + .LO(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_10686_i_4395) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_10687_i.INIT = 16'hECA0; + LUT4_L com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_10687_i ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_hi[0]), + .I1(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_hi[1]), + .I2(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_59_), + .I3(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_131_), + .LO(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_10687_i_4396) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_10688_i.INIT = 16'hECA0; + LUT4_L com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_10688_i ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_hi[0]), + .I1(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_hi[1]), + .I2(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_58_), + .I3(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_130_), + .LO(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_10688_i_4397) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_10689_i.INIT = 16'hECA0; + LUT4_L com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_10689_i ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_hi[0]), + .I1(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_hi[1]), + .I2(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_57_), + .I3(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_129_), + .LO(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_10689_i_4398) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_10690_i.INIT = 16'hECA0; + LUT4_L com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_10690_i ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_hi[0]), + .I1(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_hi[1]), + .I2(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_56_), + .I3(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_128_), + .LO(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_10690_i_4399) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_10691_i.INIT = 16'hECA0; + LUT4_L com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_10691_i ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_hi[0]), + .I1(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_hi[1]), + .I2(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_55_), + .I3(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_127_), + .LO(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_10691_i_4400) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_10692_i.INIT = 16'hECA0; + LUT4_L com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_10692_i ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_hi[0]), + .I1(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_hi[1]), + .I2(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_54_), + .I3(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_126_), + .LO(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_10692_i_4401) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_10693_i.INIT = 16'hECA0; + LUT4_L com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_10693_i ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_hi[0]), + .I1(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_hi[1]), + .I2(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_53_), + .I3(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_125_), + .LO(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_10693_i_4402) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_10694_i.INIT = 16'hECA0; + LUT4_L com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_10694_i ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_hi[0]), + .I1(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_hi[1]), + .I2(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_52_), + .I3(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_124_), + .LO(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_10694_i_4403) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_10695_i.INIT = 16'hECA0; + LUT4_L com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_10695_i ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_hi[0]), + .I1(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_hi[1]), + .I2(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_51_), + .I3(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_123_), + .LO(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_10695_i_4404) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_10696_i.INIT = 16'hECA0; + LUT4_L com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_10696_i ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_hi[0]), + .I1(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_hi[1]), + .I2(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_50_), + .I3(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_122_), + .LO(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_10696_i_4405) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_10697_i.INIT = 16'hECA0; + LUT4_L com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_10697_i ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_hi[0]), + .I1(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_hi[1]), + .I2(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_49_), + .I3(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_121_), + .LO(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_10697_i_4406) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_10698_i.INIT = 16'hECA0; + LUT4_L com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_10698_i ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_hi[0]), + .I1(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_hi[1]), + .I2(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_48_), + .I3(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_120_), + .LO(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_10698_i_4407) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_10699_i.INIT = 16'hECA0; + LUT4_L com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_10699_i ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_hi[0]), + .I1(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_hi[1]), + .I2(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_47_), + .I3(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_119_), + .LO(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_10699_i_4408) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_10700_i.INIT = 16'hECA0; + LUT4_L com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_10700_i ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_hi[0]), + .I1(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_hi[1]), + .I2(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_46_), + .I3(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_118_), + .LO(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_10700_i_4409) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_10701_i.INIT = 16'hECA0; + LUT4_L com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_10701_i ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_hi[0]), + .I1(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_hi[1]), + .I2(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_45_), + .I3(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_117_), + .LO(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_10701_i_4410) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_10702_i.INIT = 16'hECA0; + LUT4_L com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_10702_i ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_hi[0]), + .I1(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_hi[1]), + .I2(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_44_), + .I3(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_116_), + .LO(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_10702_i_4411) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_10703_i.INIT = 16'hECA0; + LUT4_L com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_10703_i ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_hi[0]), + .I1(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_hi[1]), + .I2(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_43_), + .I3(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_115_), + .LO(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_10703_i_4412) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_10704_i.INIT = 16'hECA0; + LUT4_L com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_10704_i ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_hi[0]), + .I1(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_hi[1]), + .I2(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_42_), + .I3(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_114_), + .LO(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_10704_i_4413) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_10705_i.INIT = 16'hECA0; + LUT4_L com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_10705_i ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_hi[0]), + .I1(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_hi[1]), + .I2(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_41_), + .I3(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_113_), + .LO(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_10705_i_4414) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_10706_i.INIT = 16'hECA0; + LUT4_L com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_10706_i ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_hi[0]), + .I1(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_hi[1]), + .I2(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_40_), + .I3(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_112_), + .LO(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_10706_i_4415) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_10707_i.INIT = 16'hECA0; + LUT4_L com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_10707_i ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_hi[0]), + .I1(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_hi[1]), + .I2(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_39_), + .I3(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_111_), + .LO(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_10707_i_4416) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_10708_i.INIT = 16'hECA0; + LUT4_L com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_10708_i ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_hi[0]), + .I1(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_hi[1]), + .I2(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_38_), + .I3(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_110_), + .LO(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_10708_i_4417) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_10709_i.INIT = 16'hECA0; + LUT4_L com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_10709_i ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_hi[0]), + .I1(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_hi[1]), + .I2(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_37_), + .I3(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_109_), + .LO(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_10709_i_4418) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_10710_i.INIT = 16'hECA0; + LUT4_L com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_10710_i ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_hi[0]), + .I1(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_hi[1]), + .I2(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_36_), + .I3(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_108_), + .LO(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_10710_i_4419) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_10711_i.INIT = 16'hECA0; + LUT4_L com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_10711_i ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_hi[0]), + .I1(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_hi[1]), + .I2(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_35_), + .I3(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_107_), + .LO(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_10711_i_4420) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_10712_i.INIT = 16'hECA0; + LUT4_L com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_10712_i ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_hi[0]), + .I1(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_hi[1]), + .I2(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_34_), + .I3(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_106_), + .LO(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_10712_i_4421) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_10713_i.INIT = 16'hECA0; + LUT4_L com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_10713_i ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_hi[0]), + .I1(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_hi[1]), + .I2(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_33_), + .I3(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_105_), + .LO(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_10713_i_4422) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_10714_i.INIT = 16'hECA0; + LUT4_L com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_10714_i ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_hi[0]), + .I1(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_hi[1]), + .I2(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_32_), + .I3(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_104_), + .LO(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_10714_i_4423) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_10715_i.INIT = 16'hECA0; + LUT4_L com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_10715_i ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_hi[0]), + .I1(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_hi[1]), + .I2(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_31_), + .I3(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_103_), + .LO(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_10715_i_4424) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_10716_i.INIT = 16'hECA0; + LUT4_L com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_10716_i ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_hi[0]), + .I1(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_hi[1]), + .I2(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_30_), + .I3(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_102_), + .LO(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_10716_i_4425) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_10717_i.INIT = 16'hECA0; + LUT4_L com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_10717_i ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_hi[0]), + .I1(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_hi[1]), + .I2(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_29_), + .I3(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_101_), + .LO(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_10717_i_4426) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_10718_i.INIT = 16'hECA0; + LUT4_L com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_10718_i ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_hi[0]), + .I1(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_hi[1]), + .I2(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_28_), + .I3(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_100_), + .LO(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_10718_i_4427) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_10719_i.INIT = 16'hECA0; + LUT4_L com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_10719_i ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_hi[0]), + .I1(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_hi[1]), + .I2(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_27_), + .I3(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_99_), + .LO(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_10719_i_4428) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_10720_i.INIT = 16'hECA0; + LUT4_L com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_10720_i ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_hi[0]), + .I1(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_hi[1]), + .I2(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_26_), + .I3(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_98_), + .LO(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_10720_i_4429) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_10721_i.INIT = 16'hECA0; + LUT4_L com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_10721_i ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_hi[0]), + .I1(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_hi[1]), + .I2(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_25_), + .I3(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_97_), + .LO(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_10721_i_4430) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_10722_i.INIT = 16'hECA0; + LUT4_L com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_10722_i ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_hi[0]), + .I1(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_hi[1]), + .I2(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_24_), + .I3(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_96_), + .LO(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_10722_i_4431) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_10723_i.INIT = 16'hECA0; + LUT4_L com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_10723_i ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_hi[0]), + .I1(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_hi[1]), + .I2(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_23_), + .I3(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_95_), + .LO(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_10723_i_4432) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_10724_i.INIT = 16'hECA0; + LUT4_L com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_10724_i ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_hi[0]), + .I1(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_hi[1]), + .I2(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_22_), + .I3(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_94_), + .LO(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_10724_i_4433) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_10725_i.INIT = 16'hECA0; + LUT4_L com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_10725_i ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_hi[0]), + .I1(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_hi[1]), + .I2(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_21_), + .I3(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_93_), + .LO(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_10725_i_4434) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_10726_i.INIT = 16'hECA0; + LUT4_L com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_10726_i ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_hi[0]), + .I1(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_hi[1]), + .I2(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_20_), + .I3(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_92_), + .LO(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_10726_i_4435) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_10727_i.INIT = 16'hECA0; + LUT4_L com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_10727_i ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_hi[0]), + .I1(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_hi[1]), + .I2(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_19_), + .I3(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_91_), + .LO(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_10727_i_4436) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_10728_i.INIT = 16'hECA0; + LUT4_L com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_10728_i ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_hi[0]), + .I1(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_hi[1]), + .I2(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_18_), + .I3(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_90_), + .LO(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_10728_i_4437) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_10729_i.INIT = 16'hECA0; + LUT4_L com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_10729_i ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_hi[0]), + .I1(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_hi[1]), + .I2(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_17_), + .I3(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_89_), + .LO(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_10729_i_4438) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_10730_i.INIT = 16'hECA0; + LUT4_L com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_10730_i ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_hi[0]), + .I1(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_hi[1]), + .I2(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_16_), + .I3(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_88_), + .LO(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_10730_i_4439) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_10731_i.INIT = 16'hECA0; + LUT4_L com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_10731_i ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_hi[0]), + .I1(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_hi[1]), + .I2(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_15_), + .I3(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_87_), + .LO(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_10731_i_4440) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_10732_i.INIT = 16'hECA0; + LUT4_L com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_10732_i ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_hi[0]), + .I1(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_hi[1]), + .I2(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_14_), + .I3(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_86_), + .LO(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_10732_i_4441) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_10733_i.INIT = 16'hECA0; + LUT4_L com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_10733_i ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_hi[0]), + .I1(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_hi[1]), + .I2(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_13_), + .I3(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_85_), + .LO(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_10733_i_4442) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_10734_i.INIT = 16'hECA0; + LUT4_L com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_10734_i ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_hi[0]), + .I1(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_hi[1]), + .I2(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_12_), + .I3(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_84_), + .LO(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_10734_i_4443) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_10735_i.INIT = 16'hECA0; + LUT4_L com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_10735_i ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_hi[0]), + .I1(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_hi[1]), + .I2(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_11_), + .I3(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_83_), + .LO(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_10735_i_4444) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_10736_i.INIT = 16'hECA0; + LUT4_L com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_10736_i ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_hi[0]), + .I1(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_hi[1]), + .I2(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_10_), + .I3(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_82_), + .LO(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_10736_i_4445) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_10737_i.INIT = 16'hECA0; + LUT4_L com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_10737_i ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_hi[0]), + .I1(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_hi[1]), + .I2(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_9_), + .I3(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_81_), + .LO(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_10737_i_4446) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_10738_i.INIT = 16'hECA0; + LUT4_L com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_10738_i ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_hi[0]), + .I1(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_hi[1]), + .I2(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_8_), + .I3(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_80_), + .LO(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_10738_i_4447) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_10739_i.INIT = 16'hECA0; + LUT4_L com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_10739_i ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_hi[0]), + .I1(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_hi[1]), + .I2(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_7_), + .I3(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_79_), + .LO(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_10739_i_4448) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_10740_i.INIT = 16'hECA0; + LUT4_L com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_10740_i ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_hi[0]), + .I1(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_hi[1]), + .I2(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_6_), + .I3(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_78_), + .LO(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_10740_i_4449) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_10741_i.INIT = 16'hECA0; + LUT4_L com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_10741_i ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_hi[0]), + .I1(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_hi[1]), + .I2(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_5_), + .I3(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_77_), + .LO(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_10741_i_4450) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_10742_i.INIT = 16'hECA0; + LUT4_L com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_10742_i ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_hi[0]), + .I1(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_hi[1]), + .I2(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_4_), + .I3(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_76_), + .LO(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_10742_i_4451) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_10743_i.INIT = 16'hECA0; + LUT4_L com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_10743_i ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_hi[0]), + .I1(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_hi[1]), + .I2(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_3_), + .I3(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_75_), + .LO(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_10743_i_4452) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_10744_i.INIT = 16'hECA0; + LUT4_L com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_10744_i ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_hi[0]), + .I1(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_hi[1]), + .I2(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_2_), + .I3(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_74_), + .LO(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_10744_i_4453) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_10745_i.INIT = 16'hECA0; + LUT4_L com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_10745_i ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_hi[0]), + .I1(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_hi[1]), + .I2(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_1_), + .I3(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_73_), + .LO(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_10745_i_4454) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_10746_i.INIT = 16'hECA0; + LUT4_L com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_10746_i ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_hi[0]), + .I1(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_hi[1]), + .I2(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_0_), + .I3(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_72_), + .LO(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_10746_i_4456) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_hi_eq_1_m_i.INIT = 8'hFD; + LUT3_L com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_hi_eq_1_m_i ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_hi[0]), + .I1(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_hi[1]), + .I2(com_tlm_u_tlm_rx_vc0_fifo_select_oq2bq_4169), + .LO(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_hi_eq_1_m_i_4383) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_d_o_d_m_67_.INIT = 16'hA888; + LUT4_L com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_d_o_d_m_67_ ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_d_o_0_sqmuxa_4390), + .I1(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_un615_d_o_d[0]), + .I2(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_hi[1]), + .I3(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_139_), + .LO(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_d_o_d_m_67__4384) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_d_o_d_m_65_.INIT = 16'hA888; + LUT4_L com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_d_o_d_m_65_ ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_d_o_0_sqmuxa_4390), + .I1(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_un599_d_o_d[0]), + .I2(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_hi[1]), + .I3(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_137_), + .LO(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_d_o_d_m_65__4385) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_d_o_d_m_64_.INIT = 16'hA888; + LUT4_L com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_d_o_d_m_64_ ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_d_o_0_sqmuxa_4390), + .I1(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_un591_d_o_d[0]), + .I2(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_hi[1]), + .I3(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_shift_tap_136_), + .LO(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_d_o_d_m_64__4386) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_hi_71_0_1_.INIT = 4'h8; + LUT2_L com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_hi_71_0_1_ ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_hi[0]), + .I1(com_tlm_u_tlm_rx_vc0_fifo_select_oq2bq_4169), + .LO(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_hi_71[1]) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_hi_71_0_0_0_.INIT = 8'h1C; + LUT3_L com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_hi_71_0_0_0_ ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_hi[0]), + .I1(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_hi[1]), + .I2(com_tlm_u_tlm_rx_vc0_fifo_select_oq2bq_4169), + .LO(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_hi_71[0]) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_un1_raddr_lo_1_axb_3.INIT = 8'hC6; + LUT3_L com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_un1_raddr_lo_1_axb_3 ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_d_o_0_sqmuxa_4390), + .I1(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[3]), + .I2(com_tlm_u_tlm_rx_vc0_fifo_select_oq2bq_4169), + .LO(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_un1_raddr_lo_1_axb_3_4387) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_un1_raddr_lo_1_axb_2.INIT = 8'hC6; + LUT3_L com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_un1_raddr_lo_1_axb_2 ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_d_o_0_sqmuxa_4390), + .I1(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[2]), + .I2(com_tlm_u_tlm_rx_vc0_fifo_select_oq2bq_4169), + .LO(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_un1_raddr_lo_1_axb_2_4388) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_un1_raddr_lo_1_axb_1.INIT = 8'hC6; + LUT3_L com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_un1_raddr_lo_1_axb_1 ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_d_o_0_sqmuxa_4390), + .I1(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo[1]), + .I2(com_tlm_u_tlm_rx_vc0_fifo_select_oq2bq_4169), + .LO(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_un1_raddr_lo_1_axb_1_4389) + ); + FDS com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1_0_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_un1_raddr_lo_1_axb_0_4391), + .Q(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[0]), + .S(plm_link_up_i) + ); + FDS com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1_2_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_un1_raddr_lo_1_s_2_5), + .Q(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[2]), + .S(plm_link_up_i) + ); + FDS com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1_1_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_un1_raddr_lo_1_s_1_5), + .Q(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[1]), + .S(plm_link_up_i) + ); + FDS com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1_3_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_un1_raddr_lo_1_s_3_5), + .Q(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_raddr_lo_1[3]), + .S(plm_link_up_i) + ); + FDE com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_data_bits_d_o_63_ ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_86095_i_4455), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_10683_i_4392), + .Q(com_tlm_u_tlm_rx_vc0_fifo_data_bqr_63_) + ); + FDE com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_data_bits_d_o_62_ ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_86095_i_4455), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_10684_i_4393), + .Q(com_tlm_u_tlm_rx_vc0_fifo_data_bqr_62_) + ); + FDE com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_data_bits_d_o_61_ ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_86095_i_4455), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_10685_i_4394), + .Q(com_tlm_u_tlm_rx_vc0_fifo_data_bqr_61_) + ); + FDE com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_data_bits_d_o_60_ ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_86095_i_4455), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_10686_i_4395), + .Q(com_tlm_u_tlm_rx_vc0_fifo_data_bqr_60_) + ); + FDE com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_data_bits_d_o_59_ ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_86095_i_4455), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_10687_i_4396), + .Q(com_tlm_u_tlm_rx_vc0_fifo_data_bqr_59_) + ); + FDE com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_data_bits_d_o_58_ ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_86095_i_4455), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_10688_i_4397), + .Q(com_tlm_u_tlm_rx_vc0_fifo_data_bqr_58_) + ); + FDE com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_data_bits_d_o_57_ ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_86095_i_4455), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_10689_i_4398), + .Q(com_tlm_u_tlm_rx_vc0_fifo_data_bqr_57_) + ); + FDE com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_data_bits_d_o_56_ ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_86095_i_4455), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_10690_i_4399), + .Q(com_tlm_u_tlm_rx_vc0_fifo_data_bqr_56_) + ); + FDE com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_data_bits_d_o_55_ ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_86095_i_4455), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_10691_i_4400), + .Q(com_tlm_u_tlm_rx_vc0_fifo_data_bqr_55_) + ); + FDE com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_data_bits_d_o_54_ ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_86095_i_4455), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_10692_i_4401), + .Q(com_tlm_u_tlm_rx_vc0_fifo_data_bqr_54_) + ); + FDE com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_data_bits_d_o_53_ ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_86095_i_4455), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_10693_i_4402), + .Q(com_tlm_u_tlm_rx_vc0_fifo_data_bqr_53_) + ); + FDE com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_data_bits_d_o_52_ ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_86095_i_4455), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_10694_i_4403), + .Q(com_tlm_u_tlm_rx_vc0_fifo_data_bqr_52_) + ); + FDE com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_data_bits_d_o_51_ ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_86095_i_4455), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_10695_i_4404), + .Q(com_tlm_u_tlm_rx_vc0_fifo_data_bqr_51_) + ); + FDE com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_data_bits_d_o_50_ ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_86095_i_4455), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_10696_i_4405), + .Q(com_tlm_u_tlm_rx_vc0_fifo_data_bqr_50_) + ); + FDE com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_data_bits_d_o_49_ ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_86095_i_4455), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_10697_i_4406), + .Q(com_tlm_u_tlm_rx_vc0_fifo_data_bqr_49_) + ); + FDE com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_data_bits_d_o_48_ ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_86095_i_4455), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_10698_i_4407), + .Q(com_tlm_u_tlm_rx_vc0_fifo_data_bqr_48_) + ); + FDE com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_data_bits_d_o_47_ ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_86095_i_4455), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_10699_i_4408), + .Q(com_tlm_u_tlm_rx_vc0_fifo_data_bqr_47_) + ); + FDE com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_data_bits_d_o_46_ ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_86095_i_4455), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_10700_i_4409), + .Q(com_tlm_u_tlm_rx_vc0_fifo_data_bqr_46_) + ); + FDE com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_data_bits_d_o_45_ ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_86095_i_4455), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_10701_i_4410), + .Q(com_tlm_u_tlm_rx_vc0_fifo_data_bqr_45_) + ); + FDE com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_data_bits_d_o_44_ ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_86095_i_4455), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_10702_i_4411), + .Q(com_tlm_u_tlm_rx_vc0_fifo_data_bqr_44_) + ); + FDE com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_data_bits_d_o_43_ ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_86095_i_4455), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_10703_i_4412), + .Q(com_tlm_u_tlm_rx_vc0_fifo_data_bqr_43_) + ); + FDE com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_data_bits_d_o_42_ ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_86095_i_4455), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_10704_i_4413), + .Q(com_tlm_u_tlm_rx_vc0_fifo_data_bqr_42_) + ); + FDE com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_data_bits_d_o_41_ ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_86095_i_4455), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_10705_i_4414), + .Q(com_tlm_u_tlm_rx_vc0_fifo_data_bqr_41_) + ); + FDE com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_data_bits_d_o_40_ ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_86095_i_4455), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_10706_i_4415), + .Q(com_tlm_u_tlm_rx_vc0_fifo_data_bqr_40_) + ); + FDE com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_data_bits_d_o_39_ ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_86095_i_4455), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_10707_i_4416), + .Q(com_tlm_u_tlm_rx_vc0_fifo_data_bqr_39_) + ); + FDE com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_data_bits_d_o_38_ ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_86095_i_4455), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_10708_i_4417), + .Q(com_tlm_u_tlm_rx_vc0_fifo_data_bqr_38_) + ); + FDE com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_data_bits_d_o_37_ ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_86095_i_4455), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_10709_i_4418), + .Q(com_tlm_u_tlm_rx_vc0_fifo_data_bqr_37_) + ); + FDE com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_data_bits_d_o_36_ ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_86095_i_4455), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_10710_i_4419), + .Q(com_tlm_u_tlm_rx_vc0_fifo_data_bqr_36_) + ); + FDE com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_data_bits_d_o_35_ ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_86095_i_4455), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_10711_i_4420), + .Q(com_tlm_u_tlm_rx_vc0_fifo_data_bqr_35_) + ); + FDE com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_data_bits_d_o_34_ ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_86095_i_4455), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_10712_i_4421), + .Q(com_tlm_u_tlm_rx_vc0_fifo_data_bqr_34_) + ); + FDE com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_data_bits_d_o_33_ ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_86095_i_4455), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_10713_i_4422), + .Q(com_tlm_u_tlm_rx_vc0_fifo_data_bqr_33_) + ); + FDE com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_data_bits_d_o_32_ ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_86095_i_4455), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_10714_i_4423), + .Q(com_tlm_u_tlm_rx_vc0_fifo_data_bqr_32_) + ); + FDE com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_data_bits_d_o_31_ ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_86095_i_4455), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_10715_i_4424), + .Q(com_tlm_u_tlm_rx_vc0_fifo_data_bqr_31_) + ); + FDE com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_data_bits_d_o_30_ ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_86095_i_4455), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_10716_i_4425), + .Q(com_tlm_u_tlm_rx_vc0_fifo_data_bqr_30_) + ); + FDE com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_data_bits_d_o_29_ ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_86095_i_4455), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_10717_i_4426), + .Q(com_tlm_u_tlm_rx_vc0_fifo_data_bqr_29_) + ); + FDE com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_data_bits_d_o_28_ ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_86095_i_4455), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_10718_i_4427), + .Q(com_tlm_u_tlm_rx_vc0_fifo_data_bqr_28_) + ); + FDE com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_data_bits_d_o_27_ ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_86095_i_4455), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_10719_i_4428), + .Q(com_tlm_u_tlm_rx_vc0_fifo_data_bqr_27_) + ); + FDE com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_data_bits_d_o_26_ ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_86095_i_4455), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_10720_i_4429), + .Q(com_tlm_u_tlm_rx_vc0_fifo_data_bqr_26_) + ); + FDE com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_data_bits_d_o_25_ ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_86095_i_4455), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_10721_i_4430), + .Q(com_tlm_u_tlm_rx_vc0_fifo_data_bqr_25_) + ); + FDE com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_data_bits_d_o_24_ ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_86095_i_4455), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_10722_i_4431), + .Q(com_tlm_u_tlm_rx_vc0_fifo_data_bqr_24_) + ); + FDE com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_data_bits_d_o_23_ ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_86095_i_4455), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_10723_i_4432), + .Q(com_tlm_u_tlm_rx_vc0_fifo_data_bqr_23_) + ); + FDE com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_data_bits_d_o_22_ ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_86095_i_4455), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_10724_i_4433), + .Q(com_tlm_u_tlm_rx_vc0_fifo_data_bqr_22_) + ); + FDE com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_data_bits_d_o_21_ ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_86095_i_4455), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_10725_i_4434), + .Q(com_tlm_u_tlm_rx_vc0_fifo_data_bqr_21_) + ); + FDE com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_data_bits_d_o_20_ ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_86095_i_4455), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_10726_i_4435), + .Q(com_tlm_u_tlm_rx_vc0_fifo_data_bqr_20_) + ); + FDE com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_data_bits_d_o_19_ ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_86095_i_4455), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_10727_i_4436), + .Q(com_tlm_u_tlm_rx_vc0_fifo_data_bqr_19_) + ); + FDE com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_data_bits_d_o_18_ ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_86095_i_4455), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_10728_i_4437), + .Q(com_tlm_u_tlm_rx_vc0_fifo_data_bqr_18_) + ); + FDE com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_data_bits_d_o_17_ ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_86095_i_4455), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_10729_i_4438), + .Q(com_tlm_u_tlm_rx_vc0_fifo_data_bqr_17_) + ); + FDE com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_data_bits_d_o_16_ ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_86095_i_4455), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_10730_i_4439), + .Q(com_tlm_u_tlm_rx_vc0_fifo_data_bqr_16_) + ); + FDE com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_data_bits_d_o_15_ ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_86095_i_4455), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_10731_i_4440), + .Q(com_tlm_u_tlm_rx_vc0_fifo_data_bqr_15_) + ); + FDE com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_data_bits_d_o_14_ ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_86095_i_4455), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_10732_i_4441), + .Q(com_tlm_u_tlm_rx_vc0_fifo_data_bqr_14_) + ); + FDE com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_data_bits_d_o_13_ ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_86095_i_4455), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_10733_i_4442), + .Q(com_tlm_u_tlm_rx_vc0_fifo_data_bqr_13_) + ); + FDE com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_data_bits_d_o_12_ ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_86095_i_4455), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_10734_i_4443), + .Q(com_tlm_u_tlm_rx_vc0_fifo_data_bqr_12_) + ); + FDE com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_data_bits_d_o_11_ ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_86095_i_4455), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_10735_i_4444), + .Q(com_tlm_u_tlm_rx_vc0_fifo_data_bqr_11_) + ); + FDE com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_data_bits_d_o_10_ ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_86095_i_4455), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_10736_i_4445), + .Q(com_tlm_u_tlm_rx_vc0_fifo_data_bqr_10_) + ); + FDE com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_data_bits_d_o_9_ ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_86095_i_4455), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_10737_i_4446), + .Q(com_tlm_u_tlm_rx_vc0_fifo_data_bqr_9_) + ); + FDE com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_data_bits_d_o_8_ ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_86095_i_4455), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_10738_i_4447), + .Q(com_tlm_u_tlm_rx_vc0_fifo_data_bqr_8_) + ); + FDE com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_data_bits_d_o_7_ ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_86095_i_4455), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_10739_i_4448), + .Q(com_tlm_u_tlm_rx_vc0_fifo_data_bqr_7_) + ); + FDE com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_data_bits_d_o_6_ ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_86095_i_4455), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_10740_i_4449), + .Q(com_tlm_u_tlm_rx_vc0_fifo_data_bqr_6_) + ); + FDE com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_data_bits_d_o_5_ ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_86095_i_4455), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_10741_i_4450), + .Q(com_tlm_u_tlm_rx_vc0_fifo_data_bqr_5_) + ); + FDE com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_data_bits_d_o_4_ ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_86095_i_4455), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_10742_i_4451), + .Q(com_tlm_u_tlm_rx_vc0_fifo_data_bqr_4_) + ); + FDE com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_data_bits_d_o_3_ ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_86095_i_4455), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_10743_i_4452), + .Q(com_tlm_u_tlm_rx_vc0_fifo_data_bqr_3_) + ); + FDE com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_data_bits_d_o_2_ ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_86095_i_4455), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_10744_i_4453), + .Q(com_tlm_u_tlm_rx_vc0_fifo_data_bqr_2_) + ); + FDE com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_data_bits_d_o_1_ ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_86095_i_4455), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_10745_i_4454), + .Q(com_tlm_u_tlm_rx_vc0_fifo_data_bqr_1_) + ); + FDE com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_data_bits_d_o_0_ ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_86095_i_4455), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_main_queue_main_queue_N_10746_i_4456), + .Q(com_tlm_u_tlm_rx_vc0_fifo_data_bqr_0_) + ); + GND com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_queue_aux_queue_GND ( + .G(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_queue_aux_queue_GND_4457) + ); + SRLC16E com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_queue_aux_queue_srlrow_0__srlcol_0__srlinst ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_N_44215_i), + .D(com_tlm_u_tlm_rx_vc0_fifo_aux_oqr[0]), + .Q(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_queue_aux_queue_shift_tap[0]), + .CLK(NlwRenamedSig_OI_trn_clk), + .Q15(NLW_com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_queue_aux_queue_srlrow_0__srlcol_0__srlinst_Q15_UNCONNECTED), + .A0(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_queue_aux_queue_raddr_lo[0]), + .A1(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_queue_aux_queue_raddr_lo[1]), + .A2(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_queue_aux_queue_raddr_lo[2]), + .A3(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_queue_aux_queue_raddr_lo[3]) + ); + SRLC16E com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_queue_aux_queue_srlrow_0__srlcol_3__srlinst ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_N_44215_i), + .D(com_tlm_u_tlm_rx_vc0_fifo_aux_oqr[3]), + .Q(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_queue_aux_queue_shift_tap[3]), + .CLK(NlwRenamedSig_OI_trn_clk), + .Q15(NLW_com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_queue_aux_queue_srlrow_0__srlcol_3__srlinst_Q15_UNCONNECTED), + .A0(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_queue_aux_queue_raddr_lo[0]), + .A1(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_queue_aux_queue_raddr_lo[1]), + .A2(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_queue_aux_queue_raddr_lo[2]), + .A3(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_queue_aux_queue_raddr_lo[3]) + ); + SRLC16E com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_queue_aux_queue_srlrow_0__srlcol_2__srlinst ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_N_44215_i), + .D(com_tlm_u_tlm_rx_vc0_fifo_aux_oqr[2]), + .Q(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_queue_aux_queue_shift_tap[2]), + .CLK(NlwRenamedSig_OI_trn_clk), + .Q15(NLW_com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_queue_aux_queue_srlrow_0__srlcol_2__srlinst_Q15_UNCONNECTED), + .A0(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_queue_aux_queue_raddr_lo[0]), + .A1(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_queue_aux_queue_raddr_lo[1]), + .A2(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_queue_aux_queue_raddr_lo[2]), + .A3(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_queue_aux_queue_raddr_lo[3]) + ); + SRLC16E com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_queue_aux_queue_srlrow_0__srlcol_1__srlinst ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_N_44215_i), + .D(com_tlm_u_tlm_rx_vc0_fifo_aux_oqr[1]), + .Q(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_queue_aux_queue_shift_tap[1]), + .CLK(NlwRenamedSig_OI_trn_clk), + .Q15(NLW_com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_queue_aux_queue_srlrow_0__srlcol_1__srlinst_Q15_UNCONNECTED), + .A0(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_queue_aux_queue_raddr_lo[0]), + .A1(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_queue_aux_queue_raddr_lo[1]), + .A2(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_queue_aux_queue_raddr_lo[2]), + .A3(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_queue_aux_queue_raddr_lo[3]) + ); + SRLC16E com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_queue_aux_queue_srlrow_0__srlcol_4__srlinst ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_N_44215_i), + .D(com_tlm_u_tlm_rx_vc0_fifo_aux_oqr[4]), + .Q(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_queue_aux_queue_shift_tap[4]), + .CLK(NlwRenamedSig_OI_trn_clk), + .Q15(NLW_com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_queue_aux_queue_srlrow_0__srlcol_4__srlinst_Q15_UNCONNECTED), + .A0(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_queue_aux_queue_raddr_lo[0]), + .A1(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_queue_aux_queue_raddr_lo[1]), + .A2(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_queue_aux_queue_raddr_lo[2]), + .A3(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_queue_aux_queue_raddr_lo[3]) + ); + SRLC16E com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_queue_aux_queue_srlrow_0__srlcol_7__srlinst ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_N_44215_i), + .D(com_tlm_u_tlm_rx_vc0_fifo_cfg_oqr), + .Q(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_queue_aux_queue_shift_tap[7]), + .CLK(NlwRenamedSig_OI_trn_clk), + .Q15(NLW_com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_queue_aux_queue_srlrow_0__srlcol_7__srlinst_Q15_UNCONNECTED), + .A0(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_queue_aux_queue_raddr_lo[0]), + .A1(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_queue_aux_queue_raddr_lo[1]), + .A2(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_queue_aux_queue_raddr_lo[2]), + .A3(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_queue_aux_queue_raddr_lo[3]) + ); + SRLC16E com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_queue_aux_queue_srlrow_0__srlcol_6__srlinst ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_N_44215_i), + .D(com_tlm_u_tlm_rx_vc0_fifo_aux_oqr[6]), + .Q(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_queue_aux_queue_shift_tap[6]), + .CLK(NlwRenamedSig_OI_trn_clk), + .Q15(NLW_com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_queue_aux_queue_srlrow_0__srlcol_6__srlinst_Q15_UNCONNECTED), + .A0(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_queue_aux_queue_raddr_lo[0]), + .A1(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_queue_aux_queue_raddr_lo[1]), + .A2(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_queue_aux_queue_raddr_lo[2]), + .A3(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_queue_aux_queue_raddr_lo[3]) + ); + SRLC16E com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_queue_aux_queue_srlrow_0__srlcol_5__srlinst ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_N_44215_i), + .D(com_tlm_u_tlm_rx_vc0_fifo_aux_oqr[5]), + .Q(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_queue_aux_queue_shift_tap[5]), + .CLK(NlwRenamedSig_OI_trn_clk), + .Q15(NLW_com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_queue_aux_queue_srlrow_0__srlcol_5__srlinst_Q15_UNCONNECTED), + .A0(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_queue_aux_queue_raddr_lo[0]), + .A1(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_queue_aux_queue_raddr_lo[1]), + .A2(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_queue_aux_queue_raddr_lo[2]), + .A3(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_queue_aux_queue_raddr_lo[3]) + ); + FDS com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_queue_aux_queue_raddr_lo_0_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_queue_aux_queue_un1_raddr_lo_1_axb_0_4464), + .Q(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_queue_aux_queue_raddr_lo[0]), + .S(plm_link_up_i) + ); + FDS com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_queue_aux_queue_raddr_lo_1_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_queue_aux_queue_un1_raddr_lo_1_s_1_6), + .Q(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_queue_aux_queue_raddr_lo[1]), + .S(plm_link_up_i) + ); + FDS com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_queue_aux_queue_raddr_lo_2_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_queue_aux_queue_un1_raddr_lo_1_s_2_6), + .Q(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_queue_aux_queue_raddr_lo[2]), + .S(plm_link_up_i) + ); + FDS com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_queue_aux_queue_raddr_lo_3_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_queue_aux_queue_un1_raddr_lo_1_s_3_6), + .Q(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_queue_aux_queue_raddr_lo[3]), + .S(plm_link_up_i) + ); + FDRE com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_queue_aux_queue_d_o_0_ ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_queue_aux_queue_N_44080_i_i_4461), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_queue_aux_queue_shift_tap_m[0]), + .Q(com_tlm_u_tlm_rx_vc0_fifo_aux[0]), + .R(plm_link_up_i) + ); + FDRE com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_queue_aux_queue_d_o_1_ ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_queue_aux_queue_N_44080_i_i_4461), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_queue_aux_queue_shift_tap_m[1]), + .Q(com_tlm_u_tlm_rx_vc0_fifo_aux[1]), + .R(plm_link_up_i) + ); + FDRE com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_queue_aux_queue_d_o_2_ ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_queue_aux_queue_N_44080_i_i_4461), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_queue_aux_queue_shift_tap_m[2]), + .Q(com_tlm_u_tlm_rx_vc0_fifo_aux[2]), + .R(plm_link_up_i) + ); + FDRE com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_queue_aux_queue_d_o_3_ ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_queue_aux_queue_N_44080_i_i_4461), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_queue_aux_queue_shift_tap_m[3]), + .Q(com_tlm_u_tlm_rx_vc0_fifo_aux[3]), + .R(plm_link_up_i) + ); + FDRE com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_queue_aux_queue_d_o_4_ ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_queue_aux_queue_N_44080_i_i_4461), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_queue_aux_queue_shift_tap_m[4]), + .Q(com_tlm_u_tlm_rx_vc0_fifo_aux[4]), + .R(plm_link_up_i) + ); + FDRE com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_queue_aux_queue_d_o_5_ ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_queue_aux_queue_N_44080_i_i_4461), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_queue_aux_queue_shift_tap_m[5]), + .Q(com_tlm_u_tlm_rx_vc0_fifo_aux[5]), + .R(plm_link_up_i) + ); + FDRE com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_queue_aux_queue_d_o_6_ ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_queue_aux_queue_N_44080_i_i_4461), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_queue_aux_queue_shift_tap_m[6]), + .Q(com_tlm_u_tlm_rx_vc0_fifo_aux[6]), + .R(plm_link_up_i) + ); + FDRE com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_queue_aux_queue_d_o_7_ ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_queue_aux_queue_N_44080_i_i_4461), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_queue_aux_queue_shift_tap_m[7]), + .Q(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux[7]), + .R(plm_link_up_i) + ); + FDRE com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_queue_aux_queue_nxt_vld_o ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_queue_aux_queue_N_86084_i_4462), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_N_44215_i), + .Q(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_queue_aux_queue_un1_aux_queue), + .R(plm_link_up_i) + ); + FDRE com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_queue_aux_queue_vld_o ( + .CE(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_queue_aux_queue_N_44080_i_i_4461), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_queue_aux_queue_un1_aux_queue), + .Q(com_tlm_u_tlm_rx_vc0_fifo_aux_vld), + .R(plm_link_up_i) + ); + MUXCY_L com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_queue_aux_queue_un1_raddr_lo_1_cry_0 ( + .CI(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_queue_aux_queue_GND_4457), + .DI(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_queue_aux_queue_raddr_lo[0]), + .LO(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_queue_aux_queue_un1_raddr_lo_1_cry_0_4458), + .S(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_queue_aux_queue_un1_raddr_lo_1_axb_0_4464) + ); + MUXCY_L com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_queue_aux_queue_un1_raddr_lo_1_cry_1 ( + .CI(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_queue_aux_queue_un1_raddr_lo_1_cry_0_4458), + .DI(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_queue_aux_queue_raddr_lo[1]), + .LO(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_queue_aux_queue_un1_raddr_lo_1_cry_1_4459), + .S(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_queue_aux_queue_un1_raddr_lo_1_axb_1_4467) + ); + XORCY com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_queue_aux_queue_un1_raddr_lo_1_s_1 ( + .CI(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_queue_aux_queue_un1_raddr_lo_1_cry_0_4458), + .LI(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_queue_aux_queue_un1_raddr_lo_1_axb_1_4467), + .O(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_queue_aux_queue_un1_raddr_lo_1_s_1_6) + ); + MUXCY_L com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_queue_aux_queue_un1_raddr_lo_1_cry_2 ( + .CI(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_queue_aux_queue_un1_raddr_lo_1_cry_1_4459), + .DI(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_queue_aux_queue_raddr_lo[2]), + .LO(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_queue_aux_queue_un1_raddr_lo_1_cry_2_4460), + .S(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_queue_aux_queue_un1_raddr_lo_1_axb_2_4466) + ); + XORCY com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_queue_aux_queue_un1_raddr_lo_1_s_2 ( + .CI(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_queue_aux_queue_un1_raddr_lo_1_cry_1_4459), + .LI(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_queue_aux_queue_un1_raddr_lo_1_axb_2_4466), + .O(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_queue_aux_queue_un1_raddr_lo_1_s_2_6) + ); + XORCY com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_queue_aux_queue_un1_raddr_lo_1_s_3 ( + .CI(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_queue_aux_queue_un1_raddr_lo_1_cry_2_4460), + .LI(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_queue_aux_queue_un1_raddr_lo_1_axb_3_4465), + .O(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_queue_aux_queue_un1_raddr_lo_1_s_3_6) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_queue_aux_queue_un1_bkp_i_1_i_0_a2_2.INIT = 16'h0001; + LUT4 com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_queue_aux_queue_un1_bkp_i_1_i_0_a2_2 ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_queue_aux_queue_raddr_lo[0]), + .I1(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_queue_aux_queue_raddr_lo[1]), + .I2(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_queue_aux_queue_raddr_lo[2]), + .I3(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_queue_aux_queue_raddr_lo[3]), + .O(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_queue_aux_queue_un1_bkp_i_1_i_0_a2_2_4463) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_queue_aux_queue_d_o_0_sqmuxa_i_o2.INIT = 8'h8A; + LUT3 com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_queue_aux_queue_d_o_0_sqmuxa_i_o2 ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_queue_aux_queue_un1_aux_queue), + .I1(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_ren_4372), + .I2(com_tlm_u_tlm_rx_vc0_fifo_aux_vld), + .O(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_queue_aux_queue_N_44106_i) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_queue_aux_queue_N_44080_i_i.INIT = 4'hB; + LUT2 com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_queue_aux_queue_N_44080_i_i ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_ren_4372), + .I1(com_tlm_u_tlm_rx_vc0_fifo_aux_vld), + .O(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_queue_aux_queue_N_44080_i_i_4461) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_queue_aux_queue_N_86084_i.INIT = 16'hEAEE; + LUT4 com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_queue_aux_queue_N_86084_i ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_N_44215_i), + .I1(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_queue_aux_queue_un1_bkp_i_1_i_0_a2_2_4463), + .I2(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_ren_4372), + .I3(com_tlm_u_tlm_rx_vc0_fifo_aux_vld), + .O(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_queue_aux_queue_N_86084_i_4462) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_queue_aux_queue_un1_raddr_lo_1_axb_0.INIT = 8'h96; + LUT3 com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_queue_aux_queue_un1_raddr_lo_1_axb_0 ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_queue_aux_queue_N_44106_i), + .I1(com_tlm_u_tlm_rx_vc0_fifo_N_44215_i), + .I2(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_queue_aux_queue_raddr_lo[0]), + .O(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_queue_aux_queue_un1_raddr_lo_1_axb_0_4464) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_queue_aux_queue_shift_tap_m_7_.INIT = 4'h8; + LUT2_L com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_queue_aux_queue_shift_tap_m_7_ ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_queue_aux_queue_N_44106_i), + .I1(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_queue_aux_queue_shift_tap[7]), + .LO(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_queue_aux_queue_shift_tap_m[7]) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_queue_aux_queue_shift_tap_m_6_.INIT = 4'h8; + LUT2_L com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_queue_aux_queue_shift_tap_m_6_ ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_queue_aux_queue_N_44106_i), + .I1(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_queue_aux_queue_shift_tap[6]), + .LO(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_queue_aux_queue_shift_tap_m[6]) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_queue_aux_queue_shift_tap_m_5_.INIT = 4'h8; + LUT2_L com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_queue_aux_queue_shift_tap_m_5_ ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_queue_aux_queue_N_44106_i), + .I1(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_queue_aux_queue_shift_tap[5]), + .LO(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_queue_aux_queue_shift_tap_m[5]) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_queue_aux_queue_shift_tap_m_4_.INIT = 4'h8; + LUT2_L com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_queue_aux_queue_shift_tap_m_4_ ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_queue_aux_queue_N_44106_i), + .I1(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_queue_aux_queue_shift_tap[4]), + .LO(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_queue_aux_queue_shift_tap_m[4]) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_queue_aux_queue_shift_tap_m_3_.INIT = 4'h8; + LUT2_L com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_queue_aux_queue_shift_tap_m_3_ ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_queue_aux_queue_N_44106_i), + .I1(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_queue_aux_queue_shift_tap[3]), + .LO(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_queue_aux_queue_shift_tap_m[3]) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_queue_aux_queue_shift_tap_m_2_.INIT = 4'h8; + LUT2_L com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_queue_aux_queue_shift_tap_m_2_ ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_queue_aux_queue_N_44106_i), + .I1(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_queue_aux_queue_shift_tap[2]), + .LO(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_queue_aux_queue_shift_tap_m[2]) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_queue_aux_queue_shift_tap_m_1_.INIT = 4'h8; + LUT2_L com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_queue_aux_queue_shift_tap_m_1_ ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_queue_aux_queue_N_44106_i), + .I1(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_queue_aux_queue_shift_tap[1]), + .LO(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_queue_aux_queue_shift_tap_m[1]) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_queue_aux_queue_shift_tap_m_0_.INIT = 4'h8; + LUT2_L com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_queue_aux_queue_shift_tap_m_0_ ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_queue_aux_queue_N_44106_i), + .I1(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_queue_aux_queue_shift_tap[0]), + .LO(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_queue_aux_queue_shift_tap_m[0]) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_queue_aux_queue_un1_raddr_lo_1_axb_3.INIT = 8'hD2; + LUT3_L com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_queue_aux_queue_un1_raddr_lo_1_axb_3 ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_queue_aux_queue_N_44106_i), + .I1(com_tlm_u_tlm_rx_vc0_fifo_N_44215_i), + .I2(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_queue_aux_queue_raddr_lo[3]), + .LO(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_queue_aux_queue_un1_raddr_lo_1_axb_3_4465) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_queue_aux_queue_un1_raddr_lo_1_axb_2.INIT = 8'hD2; + LUT3_L com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_queue_aux_queue_un1_raddr_lo_1_axb_2 ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_queue_aux_queue_N_44106_i), + .I1(com_tlm_u_tlm_rx_vc0_fifo_N_44215_i), + .I2(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_queue_aux_queue_raddr_lo[2]), + .LO(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_queue_aux_queue_un1_raddr_lo_1_axb_2_4466) + ); + defparam com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_queue_aux_queue_un1_raddr_lo_1_axb_1.INIT = 8'hD2; + LUT3_L com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_queue_aux_queue_un1_raddr_lo_1_axb_1 ( + .I0(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_queue_aux_queue_N_44106_i), + .I1(com_tlm_u_tlm_rx_vc0_fifo_N_44215_i), + .I2(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_queue_aux_queue_raddr_lo[1]), + .LO(com_tlm_u_tlm_rx_vc0_fifo_byp_queue_aux_queue_aux_queue_un1_raddr_lo_1_axb_1_4467) + ); + GND com_tlm_u_tlm_rx_vc0_flow_ctrl_GND ( + .G(com_tlm_u_tlm_rx_vc0_flow_ctrl_GND_4468) + ); + FDS com_tlm_u_tlm_rx_vc0_flow_ctrl_freeze_timer ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_aspm_ok_i), + .Q(com_tlm_u_tlm_rx_vc0_flow_ctrl_freeze_timer_4476), + .S(plm_link_up_i) + ); + FDR com_tlm_u_tlm_rx_vc0_flow_ctrl_err_overflow_o ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_flow_ctrl_N_19688_i_4470), + .Q(com_tlm_cmmt_err_rbuf_overflow), + .R(plm_link_up_i) + ); + MUXCY_L com_tlm_u_tlm_rx_vc0_flow_ctrl_lat_timer_cry_0_ ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_un1_lat_timer_i), + .DI(com_tlm_u_tlm_rx_vc0_flow_ctrl_GND_4468), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_lat_timer_cry[0]), + .S(com_tlm_u_tlm_rx_vc0_flow_ctrl_lat_timer_qxu[0]) + ); + XORCY com_tlm_u_tlm_rx_vc0_flow_ctrl_lat_timer_s_0_ ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_un1_lat_timer_i), + .LI(com_tlm_u_tlm_rx_vc0_flow_ctrl_lat_timer_qxu[0]), + .O(com_tlm_u_tlm_rx_vc0_flow_ctrl_lat_timer_s[0]) + ); + FDRE com_tlm_u_tlm_rx_vc0_flow_ctrl_lat_timer_0_ ( + .CE(com_tlm_u_tlm_rx_vc0_flow_ctrl_N_60552_i_4472), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_flow_ctrl_lat_timer_s[0]), + .Q(com_tlm_u_tlm_rx_vc0_flow_ctrl_lat_timer[0]), + .R(plm_link_up_i) + ); + MUXCY_L com_tlm_u_tlm_rx_vc0_flow_ctrl_lat_timer_cry_1_ ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_lat_timer_cry[0]), + .DI(com_tlm_u_tlm_rx_vc0_flow_ctrl_GND_4468), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_lat_timer_cry[1]), + .S(com_tlm_u_tlm_rx_vc0_flow_ctrl_lat_timer_qxu[1]) + ); + XORCY com_tlm_u_tlm_rx_vc0_flow_ctrl_lat_timer_s_1_ ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_lat_timer_cry[0]), + .LI(com_tlm_u_tlm_rx_vc0_flow_ctrl_lat_timer_qxu[1]), + .O(com_tlm_u_tlm_rx_vc0_flow_ctrl_lat_timer_s[1]) + ); + FDRE com_tlm_u_tlm_rx_vc0_flow_ctrl_lat_timer_1_ ( + .CE(com_tlm_u_tlm_rx_vc0_flow_ctrl_N_60552_i_4472), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_flow_ctrl_lat_timer_s[1]), + .Q(com_tlm_u_tlm_rx_vc0_flow_ctrl_lat_timer[1]), + .R(plm_link_up_i) + ); + MUXCY_L com_tlm_u_tlm_rx_vc0_flow_ctrl_lat_timer_cry_2_ ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_lat_timer_cry[1]), + .DI(com_tlm_u_tlm_rx_vc0_flow_ctrl_GND_4468), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_lat_timer_cry[2]), + .S(com_tlm_u_tlm_rx_vc0_flow_ctrl_lat_timer_qxu[2]) + ); + XORCY com_tlm_u_tlm_rx_vc0_flow_ctrl_lat_timer_s_2_ ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_lat_timer_cry[1]), + .LI(com_tlm_u_tlm_rx_vc0_flow_ctrl_lat_timer_qxu[2]), + .O(com_tlm_u_tlm_rx_vc0_flow_ctrl_lat_timer_s[2]) + ); + FDRE com_tlm_u_tlm_rx_vc0_flow_ctrl_lat_timer_2_ ( + .CE(com_tlm_u_tlm_rx_vc0_flow_ctrl_N_60552_i_4472), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_flow_ctrl_lat_timer_s[2]), + .Q(com_tlm_u_tlm_rx_vc0_flow_ctrl_lat_timer[2]), + .R(plm_link_up_i) + ); + MUXCY_L com_tlm_u_tlm_rx_vc0_flow_ctrl_lat_timer_cry_3_ ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_lat_timer_cry[2]), + .DI(com_tlm_u_tlm_rx_vc0_flow_ctrl_GND_4468), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_lat_timer_cry[3]), + .S(com_tlm_u_tlm_rx_vc0_flow_ctrl_lat_timer_qxu[3]) + ); + XORCY com_tlm_u_tlm_rx_vc0_flow_ctrl_lat_timer_s_3_ ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_lat_timer_cry[2]), + .LI(com_tlm_u_tlm_rx_vc0_flow_ctrl_lat_timer_qxu[3]), + .O(com_tlm_u_tlm_rx_vc0_flow_ctrl_lat_timer_s[3]) + ); + FDRE com_tlm_u_tlm_rx_vc0_flow_ctrl_lat_timer_3_ ( + .CE(com_tlm_u_tlm_rx_vc0_flow_ctrl_N_60552_i_4472), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_flow_ctrl_lat_timer_s[3]), + .Q(com_tlm_u_tlm_rx_vc0_flow_ctrl_lat_timer[3]), + .R(plm_link_up_i) + ); + MUXCY_L com_tlm_u_tlm_rx_vc0_flow_ctrl_lat_timer_cry_4_ ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_lat_timer_cry[3]), + .DI(com_tlm_u_tlm_rx_vc0_flow_ctrl_GND_4468), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_lat_timer_cry[4]), + .S(com_tlm_u_tlm_rx_vc0_flow_ctrl_lat_timer_qxu[4]) + ); + XORCY com_tlm_u_tlm_rx_vc0_flow_ctrl_lat_timer_s_4_ ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_lat_timer_cry[3]), + .LI(com_tlm_u_tlm_rx_vc0_flow_ctrl_lat_timer_qxu[4]), + .O(com_tlm_u_tlm_rx_vc0_flow_ctrl_lat_timer_s[4]) + ); + FDRE com_tlm_u_tlm_rx_vc0_flow_ctrl_lat_timer_4_ ( + .CE(com_tlm_u_tlm_rx_vc0_flow_ctrl_N_60552_i_4472), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_flow_ctrl_lat_timer_s[4]), + .Q(com_tlm_u_tlm_rx_vc0_flow_ctrl_lat_timer[4]), + .R(plm_link_up_i) + ); + MUXCY_L com_tlm_u_tlm_rx_vc0_flow_ctrl_lat_timer_cry_5_ ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_lat_timer_cry[4]), + .DI(com_tlm_u_tlm_rx_vc0_flow_ctrl_GND_4468), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_lat_timer_cry[5]), + .S(com_tlm_u_tlm_rx_vc0_flow_ctrl_lat_timer_qxu[5]) + ); + XORCY com_tlm_u_tlm_rx_vc0_flow_ctrl_lat_timer_s_5_ ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_lat_timer_cry[4]), + .LI(com_tlm_u_tlm_rx_vc0_flow_ctrl_lat_timer_qxu[5]), + .O(com_tlm_u_tlm_rx_vc0_flow_ctrl_lat_timer_s[5]) + ); + FDSE com_tlm_u_tlm_rx_vc0_flow_ctrl_lat_timer_5_ ( + .CE(com_tlm_u_tlm_rx_vc0_flow_ctrl_N_60552_i_4472), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_flow_ctrl_lat_timer_s[5]), + .Q(com_tlm_u_tlm_rx_vc0_flow_ctrl_lat_timer[5]), + .S(plm_link_up_i) + ); + MUXCY_L com_tlm_u_tlm_rx_vc0_flow_ctrl_lat_timer_cry_6_ ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_lat_timer_cry[5]), + .DI(com_tlm_u_tlm_rx_vc0_flow_ctrl_GND_4468), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_lat_timer_cry[6]), + .S(com_tlm_u_tlm_rx_vc0_flow_ctrl_lat_timer_qxu[6]) + ); + XORCY com_tlm_u_tlm_rx_vc0_flow_ctrl_lat_timer_s_6_ ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_lat_timer_cry[5]), + .LI(com_tlm_u_tlm_rx_vc0_flow_ctrl_lat_timer_qxu[6]), + .O(com_tlm_u_tlm_rx_vc0_flow_ctrl_lat_timer_s[6]) + ); + FDSE com_tlm_u_tlm_rx_vc0_flow_ctrl_lat_timer_6_ ( + .CE(com_tlm_u_tlm_rx_vc0_flow_ctrl_N_60552_i_4472), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_flow_ctrl_lat_timer_s[6]), + .Q(com_tlm_u_tlm_rx_vc0_flow_ctrl_lat_timer[6]), + .S(plm_link_up_i) + ); + MUXCY_L com_tlm_u_tlm_rx_vc0_flow_ctrl_lat_timer_cry_7_ ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_lat_timer_cry[6]), + .DI(com_tlm_u_tlm_rx_vc0_flow_ctrl_GND_4468), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_lat_timer_cry[7]), + .S(com_tlm_u_tlm_rx_vc0_flow_ctrl_lat_timer_qxu[7]) + ); + XORCY com_tlm_u_tlm_rx_vc0_flow_ctrl_lat_timer_s_7_ ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_lat_timer_cry[6]), + .LI(com_tlm_u_tlm_rx_vc0_flow_ctrl_lat_timer_qxu[7]), + .O(com_tlm_u_tlm_rx_vc0_flow_ctrl_lat_timer_s[7]) + ); + FDSE com_tlm_u_tlm_rx_vc0_flow_ctrl_lat_timer_7_ ( + .CE(com_tlm_u_tlm_rx_vc0_flow_ctrl_N_60552_i_4472), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_flow_ctrl_lat_timer_s[7]), + .Q(com_tlm_u_tlm_rx_vc0_flow_ctrl_lat_timer[7]), + .S(plm_link_up_i) + ); + MUXCY_L com_tlm_u_tlm_rx_vc0_flow_ctrl_lat_timer_cry_8_ ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_lat_timer_cry[7]), + .DI(com_tlm_u_tlm_rx_vc0_flow_ctrl_GND_4468), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_lat_timer_cry[8]), + .S(com_tlm_u_tlm_rx_vc0_flow_ctrl_lat_timer_qxu[8]) + ); + XORCY com_tlm_u_tlm_rx_vc0_flow_ctrl_lat_timer_s_8_ ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_lat_timer_cry[7]), + .LI(com_tlm_u_tlm_rx_vc0_flow_ctrl_lat_timer_qxu[8]), + .O(com_tlm_u_tlm_rx_vc0_flow_ctrl_lat_timer_s[8]) + ); + FDSE com_tlm_u_tlm_rx_vc0_flow_ctrl_lat_timer_8_ ( + .CE(com_tlm_u_tlm_rx_vc0_flow_ctrl_N_60552_i_4472), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_flow_ctrl_lat_timer_s[8]), + .Q(com_tlm_u_tlm_rx_vc0_flow_ctrl_lat_timer[8]), + .S(plm_link_up_i) + ); + XORCY com_tlm_u_tlm_rx_vc0_flow_ctrl_lat_timer_s_9_ ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_lat_timer_cry[8]), + .LI(com_tlm_u_tlm_rx_vc0_flow_ctrl_lat_timer_qxu[9]), + .O(com_tlm_u_tlm_rx_vc0_flow_ctrl_lat_timer_s[9]) + ); + FDRE com_tlm_u_tlm_rx_vc0_flow_ctrl_lat_timer_9_ ( + .CE(com_tlm_u_tlm_rx_vc0_flow_ctrl_N_60552_i_4472), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_flow_ctrl_lat_timer_s[9]), + .Q(com_tlm_u_tlm_rx_vc0_flow_ctrl_lat_timer[9]), + .R(plm_link_up_i) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_un1_lat_timer_1_a2_0_a2_0_a2.INIT = 4'h1; + LUT2 com_tlm_u_tlm_rx_vc0_flow_ctrl_un1_lat_timer_1_a2_0_a2_0_a2 ( + .I0(com_tlm_u_tlm_rx_vc0_flow_ctrl_freeze_timer_4476), + .I1(com_tlm_u_tlm_rx_vc0_flow_ctrl_lat_timer[9]), + .O(com_tlm_u_tlm_rx_vc0_flow_ctrl_un1_lat_timer_i) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_lat_prescale_4_i_0_o3_2_.INIT = 16'h0002; + LUT4 com_tlm_u_tlm_rx_vc0_flow_ctrl_lat_prescale_4_i_0_o3_2_ ( + .I0(com_tlm_u_tlm_rx_vc0_flow_ctrl_lat_prescale[0]), + .I1(com_tlm_u_tlm_rx_vc0_flow_ctrl_lat_prescale[1]), + .I2(com_tlm_u_tlm_rx_vc0_flow_ctrl_lat_prescale[2]), + .I3(com_tlm_u_tlm_rx_vc0_flow_ctrl_lat_prescale[3]), + .O(com_tlm_u_tlm_rx_vc0_flow_ctrl_N_56162_i) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_err_overflow_o_3_0_a2_3.INIT = 16'h0001; + LUT4_L com_tlm_u_tlm_rx_vc0_flow_ctrl_err_overflow_o_3_0_a2_3 ( + .I0(com_tlm_u_tlm_rx_vc0_flow_ctrl_fc_d_advert[11]), + .I1(com_tlm_u_tlm_rx_vc0_flow_ctrl_fc_h_advert[7]), + .I2(com_tlm_u_tlm_rx_vc0_flow_ctrl_fc_d_advert_0[11]), + .I3(com_tlm_u_tlm_rx_vc0_flow_ctrl_fc_h_advert_0[7]), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_err_overflow_o_3_0_a2_3_4471) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_un7_lat_prescale_c3.INIT = 8'h01; + LUT3 com_tlm_u_tlm_rx_vc0_flow_ctrl_un7_lat_prescale_c3 ( + .I0(com_tlm_u_tlm_rx_vc0_flow_ctrl_lat_prescale[0]), + .I1(com_tlm_u_tlm_rx_vc0_flow_ctrl_lat_prescale[1]), + .I2(com_tlm_u_tlm_rx_vc0_flow_ctrl_lat_prescale[2]), + .O(com_tlm_u_tlm_rx_vc0_flow_ctrl_un7_lat_prescale_c3_4469) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_lat_timer_qxu_8_.INIT = 8'hCA; + LUT3_L com_tlm_u_tlm_rx_vc0_flow_ctrl_lat_timer_qxu_8_ ( + .I0(com_tlm_u_tlm_rx_vc0_flow_ctrl_freeze_timer_4476), + .I1(com_tlm_u_tlm_rx_vc0_flow_ctrl_lat_timer[8]), + .I2(com_tlm_u_tlm_rx_vc0_flow_ctrl_un1_lat_timer_i), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_lat_timer_qxu[8]) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_lat_timer_qxu_7_.INIT = 8'hCA; + LUT3_L com_tlm_u_tlm_rx_vc0_flow_ctrl_lat_timer_qxu_7_ ( + .I0(com_tlm_u_tlm_rx_vc0_flow_ctrl_freeze_timer_4476), + .I1(com_tlm_u_tlm_rx_vc0_flow_ctrl_lat_timer[7]), + .I2(com_tlm_u_tlm_rx_vc0_flow_ctrl_un1_lat_timer_i), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_lat_timer_qxu[7]) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_lat_timer_qxu_6_.INIT = 8'hCA; + LUT3_L com_tlm_u_tlm_rx_vc0_flow_ctrl_lat_timer_qxu_6_ ( + .I0(com_tlm_u_tlm_rx_vc0_flow_ctrl_freeze_timer_4476), + .I1(com_tlm_u_tlm_rx_vc0_flow_ctrl_lat_timer[6]), + .I2(com_tlm_u_tlm_rx_vc0_flow_ctrl_un1_lat_timer_i), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_lat_timer_qxu[6]) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_lat_timer_qxu_5_.INIT = 8'hCA; + LUT3_L com_tlm_u_tlm_rx_vc0_flow_ctrl_lat_timer_qxu_5_ ( + .I0(com_tlm_u_tlm_rx_vc0_flow_ctrl_freeze_timer_4476), + .I1(com_tlm_u_tlm_rx_vc0_flow_ctrl_lat_timer[5]), + .I2(com_tlm_u_tlm_rx_vc0_flow_ctrl_un1_lat_timer_i), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_lat_timer_qxu[5]) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_lat_prescale_4_i_m3_i_m3_0_3_.INIT = 16'h1B4E; + LUT4_L com_tlm_u_tlm_rx_vc0_flow_ctrl_lat_prescale_4_i_m3_i_m3_0_3_ ( + .I0(com_tlm_u_tlm_rx_vc0_flow_ctrl_N_56162_i), + .I1(com_tlm_u_tlm_rx_vc0_flow_ctrl_un7_lat_prescale_c3_4469), + .I2(cmmp_negotiated_width[0]), + .I3(com_tlm_u_tlm_rx_vc0_flow_ctrl_lat_prescale[3]), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_lat_prescale_4_i_m3_i_m3_0_3__4474) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_lat_prescale_4_i_0_2_.INIT = 16'h5401; + LUT4_L com_tlm_u_tlm_rx_vc0_flow_ctrl_lat_prescale_4_i_0_2_ ( + .I0(com_tlm_u_tlm_rx_vc0_flow_ctrl_N_56162_i), + .I1(com_tlm_u_tlm_rx_vc0_flow_ctrl_lat_prescale[0]), + .I2(com_tlm_u_tlm_rx_vc0_flow_ctrl_lat_prescale[1]), + .I3(com_tlm_u_tlm_rx_vc0_flow_ctrl_lat_prescale[2]), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_N_46166_i) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_lat_prescale_4_i_m3_i_m3_0_1_.INIT = 16'hD88D; + LUT4_L com_tlm_u_tlm_rx_vc0_flow_ctrl_lat_prescale_4_i_m3_i_m3_0_1_ ( + .I0(com_tlm_u_tlm_rx_vc0_flow_ctrl_N_56162_i), + .I1(cmmp_negotiated_width[0]), + .I2(com_tlm_u_tlm_rx_vc0_flow_ctrl_lat_prescale[0]), + .I3(com_tlm_u_tlm_rx_vc0_flow_ctrl_lat_prescale[1]), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_lat_prescale_4_i_m3_i_m3_0_1__4475) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_lat_prescale_i_0_.INIT = 4'h1; + LUT1_L com_tlm_u_tlm_rx_vc0_flow_ctrl_lat_prescale_i_0_ ( + .I0(com_tlm_u_tlm_rx_vc0_flow_ctrl_lat_prescale[0]), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_lat_prescale_i[0]) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_N_19688_i.INIT = 8'hFD; + LUT3_L com_tlm_u_tlm_rx_vc0_flow_ctrl_N_19688_i ( + .I0(com_tlm_u_tlm_rx_vc0_flow_ctrl_err_overflow_o_3_0_a2_3_4471), + .I1(NlwRenamedSig_OI_trn_rfc_cpld_av[11]), + .I2(NlwRenamedSig_OI_trn_rfc_cplh_av[7]), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_N_19688_i_4470) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_N_60552_i.INIT = 8'hFE; + LUT3 com_tlm_u_tlm_rx_vc0_flow_ctrl_N_60552_i ( + .I0(com_tlm_u_tlm_rx_vc0_flow_ctrl_lat_prescale_term_4473), + .I1(com_tlm_u_tlm_rx_vc0_flow_ctrl_lat_timer[9]), + .I2(com_tlm_u_tlm_rx_vc0_flow_ctrl_freeze_timer_4476), + .O(com_tlm_u_tlm_rx_vc0_flow_ctrl_N_60552_i_4472) + ); + FD com_tlm_u_tlm_rx_vc0_flow_ctrl_lat_prescale_term ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_flow_ctrl_N_56162_i), + .Q(com_tlm_u_tlm_rx_vc0_flow_ctrl_lat_prescale_term_4473) + ); + FD com_tlm_u_tlm_rx_vc0_flow_ctrl_lat_prescale_3_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_flow_ctrl_lat_prescale_4_i_m3_i_m3_0_3__4474), + .Q(com_tlm_u_tlm_rx_vc0_flow_ctrl_lat_prescale[3]) + ); + FD com_tlm_u_tlm_rx_vc0_flow_ctrl_lat_prescale_2_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_flow_ctrl_N_46166_i), + .Q(com_tlm_u_tlm_rx_vc0_flow_ctrl_lat_prescale[2]) + ); + FD com_tlm_u_tlm_rx_vc0_flow_ctrl_lat_prescale_1_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_flow_ctrl_lat_prescale_4_i_m3_i_m3_0_1__4475), + .Q(com_tlm_u_tlm_rx_vc0_flow_ctrl_lat_prescale[1]) + ); + FD com_tlm_u_tlm_rx_vc0_flow_ctrl_lat_prescale_0_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_flow_ctrl_lat_prescale_i[0]), + .Q(com_tlm_u_tlm_rx_vc0_flow_ctrl_lat_prescale[0]) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_lat_timer_qxu_0_9_.INIT = 4'h8; + LUT2_L com_tlm_u_tlm_rx_vc0_flow_ctrl_lat_timer_qxu_0_9_ ( + .I0(com_tlm_u_tlm_rx_vc0_flow_ctrl_lat_timer[9]), + .I1(com_tlm_u_tlm_rx_vc0_flow_ctrl_un1_lat_timer_i), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_lat_timer_qxu[9]) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_lat_timer_qxu_0_4_.INIT = 4'h8; + LUT2_L com_tlm_u_tlm_rx_vc0_flow_ctrl_lat_timer_qxu_0_4_ ( + .I0(com_tlm_u_tlm_rx_vc0_flow_ctrl_lat_timer[4]), + .I1(com_tlm_u_tlm_rx_vc0_flow_ctrl_un1_lat_timer_i), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_lat_timer_qxu[4]) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_lat_timer_qxu_0_3_.INIT = 4'h8; + LUT2_L com_tlm_u_tlm_rx_vc0_flow_ctrl_lat_timer_qxu_0_3_ ( + .I0(com_tlm_u_tlm_rx_vc0_flow_ctrl_lat_timer[3]), + .I1(com_tlm_u_tlm_rx_vc0_flow_ctrl_un1_lat_timer_i), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_lat_timer_qxu[3]) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_lat_timer_qxu_0_2_.INIT = 4'h8; + LUT2_L com_tlm_u_tlm_rx_vc0_flow_ctrl_lat_timer_qxu_0_2_ ( + .I0(com_tlm_u_tlm_rx_vc0_flow_ctrl_lat_timer[2]), + .I1(com_tlm_u_tlm_rx_vc0_flow_ctrl_un1_lat_timer_i), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_lat_timer_qxu[2]) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_lat_timer_qxu_0_1_.INIT = 4'h8; + LUT2_L com_tlm_u_tlm_rx_vc0_flow_ctrl_lat_timer_qxu_0_1_ ( + .I0(com_tlm_u_tlm_rx_vc0_flow_ctrl_lat_timer[1]), + .I1(com_tlm_u_tlm_rx_vc0_flow_ctrl_un1_lat_timer_i), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_lat_timer_qxu[1]) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_lat_timer_qxu_0_0_.INIT = 4'h8; + LUT2_L com_tlm_u_tlm_rx_vc0_flow_ctrl_lat_timer_qxu_0_0_ ( + .I0(com_tlm_u_tlm_rx_vc0_flow_ctrl_lat_timer[0]), + .I1(com_tlm_u_tlm_rx_vc0_flow_ctrl_un1_lat_timer_i), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_lat_timer_qxu[0]) + ); + VCC com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_VCC ( + .P(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_VCC_4575) + ); + GND com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_GND ( + .G(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_GND_4587) + ); + FDS com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_send_state_0_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_N_87151_i_4648), + .Q(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_send_state_0__4650), + .S(plm_link_up_i) + ); + FDR com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_send_state_1_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_N_87150_i_4647), + .Q(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_req_p_src_rdy), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_send_state_2_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_N_87149_i_4646), + .Q(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_send_state_2__4649), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_d_con_0_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un1_fc_d_con_1_axb_0_4588), + .Q(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_d_con[0]), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_d_con_1_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un1_fc_d_con_1_s_1_4528), + .Q(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_d_con[1]), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_d_con_2_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un1_fc_d_con_1_s_2_4531), + .Q(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_d_con[2]), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_d_con_3_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un1_fc_d_con_1_s_3_4534), + .Q(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_d_con[3]), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_d_con_4_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un1_fc_d_con_1_s_4_4537), + .Q(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_d_con[4]), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_d_con_5_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un1_fc_d_con_1_s_5_4540), + .Q(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_d_con[5]), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_d_con_6_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un1_fc_d_con_1_s_6_4542), + .Q(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_d_con[6]), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_d_con_7_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un1_fc_d_con_1_s_7_4544), + .Q(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_d_con[7]), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_d_con_8_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un1_fc_d_con_1_s_8_4546), + .Q(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_d_con[8]), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_d_con_9_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un1_fc_d_con_1_s_9_4548), + .Q(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_d_con[9]), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_d_con_10_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un1_fc_d_con_1_s_10_4550), + .Q(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_d_con[10]), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_d_con_11_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un1_fc_d_con_1_s_11_4552), + .Q(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_d_con[11]), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_req_d_o_0_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_d_o_0[0]), + .Q(com_tlm_u_tlm_rx_fc_req_pd[0]), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_req_d_o_1_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_d_o_0[1]), + .Q(com_tlm_u_tlm_rx_fc_req_pd[1]), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_req_d_o_2_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_d_o_0[2]), + .Q(com_tlm_u_tlm_rx_fc_req_pd[2]), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_req_d_o_3_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_d_o_0[3]), + .Q(com_tlm_u_tlm_rx_fc_req_pd[3]), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_req_d_o_4_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_d_o_0[4]), + .Q(com_tlm_u_tlm_rx_fc_req_pd[4]), + .R(plm_link_up_i) + ); + FDS com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_req_d_o_5_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_d_o_0[5]), + .Q(com_tlm_u_tlm_rx_fc_req_pd[5]), + .S(plm_link_up_i) + ); + FDR com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_req_d_o_6_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_d_o_0[6]), + .Q(com_tlm_u_tlm_rx_fc_req_pd[6]), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_req_d_o_7_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_d_o_0[7]), + .Q(com_tlm_u_tlm_rx_fc_req_pd[7]), + .R(plm_link_up_i) + ); + FDS com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_req_d_o_8_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_d_o_0[8]), + .Q(com_tlm_u_tlm_rx_fc_req_pd[8]), + .S(plm_link_up_i) + ); + FDR com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_req_d_o_9_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_d_o_0[9]), + .Q(com_tlm_u_tlm_rx_fc_req_pd[9]), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_req_d_o_10_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_d_o_0[10]), + .Q(com_tlm_u_tlm_rx_fc_req_pd[10]), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_req_d_o_11_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_d_o_0[11]), + .Q(com_tlm_u_tlm_rx_fc_req_pd[11]), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_h_av_o_0_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_h_av_o_axb_0_i_4621), + .Q(trn_rfc_ph_av_6092[0]), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_h_av_o_1_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_h_av_o_s_1_4554), + .Q(trn_rfc_ph_av_6092[1]), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_h_av_o_2_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_h_av_o_s_2_4556), + .Q(trn_rfc_ph_av_6092[2]), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_h_av_o_3_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_h_av_o_s_3_4558), + .Q(trn_rfc_ph_av_6092[3]), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_h_av_o_4_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_h_av_o_s_4_4560), + .Q(trn_rfc_ph_av_6092[4]), + .R(plm_link_up_i) + ); + FDS com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_h_av_o_5_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_h_av_o_s_5_4562), + .Q(trn_rfc_ph_av_6092[5]), + .S(plm_link_up_i) + ); + FDR com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_h_av_o_6_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_h_av_o_s_6_4564), + .Q(trn_rfc_ph_av_6092[6]), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_h_av_o_7_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_h_av_o_s_7_4566), + .Q(trn_rfc_ph_av_6092[7]), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_d_av_o_0_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_d_av_o_axb_0_i_4612), + .Q(trn_rfc_pd_av_6093[0]), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_d_av_o_1_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_d_av_o_s_1_4504), + .Q(trn_rfc_pd_av_6093[1]), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_d_av_o_2_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_d_av_o_s_2_4506), + .Q(trn_rfc_pd_av_6093[2]), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_d_av_o_3_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_d_av_o_s_3_4508), + .Q(trn_rfc_pd_av_6093[3]), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_d_av_o_4_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_d_av_o_s_4_4510), + .Q(trn_rfc_pd_av_6093[4]), + .R(plm_link_up_i) + ); + FDS com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_d_av_o_5_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_d_av_o_s_5_4512), + .Q(trn_rfc_pd_av_6093[5]), + .S(plm_link_up_i) + ); + FDR com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_d_av_o_6_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_d_av_o_s_6_4514), + .Q(trn_rfc_pd_av_6093[6]), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_d_av_o_7_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_d_av_o_s_7_4516), + .Q(trn_rfc_pd_av_6093[7]), + .R(plm_link_up_i) + ); + FDS com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_d_av_o_8_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_d_av_o_s_8_4518), + .Q(trn_rfc_pd_av_6093[8]), + .S(plm_link_up_i) + ); + FDR com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_d_av_o_9_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_d_av_o_s_9_4520), + .Q(trn_rfc_pd_av_6093[9]), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_d_av_o_10_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_d_av_o_s_10_4522), + .Q(trn_rfc_pd_av_6093[10]), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_d_av_o_11_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_d_av_o_s_11_4524), + .Q(trn_rfc_pd_av_6093[11]), + .R(plm_link_up_i) + ); + FDRE com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_h_alo_0_ ( + .CE(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_gnt), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_lnk_tfc_header[0]), + .Q(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_h_alo[0]), + .R(plm_link_up_i) + ); + FDRE com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_h_alo_1_ ( + .CE(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_gnt), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_lnk_tfc_header[1]), + .Q(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_h_alo[1]), + .R(plm_link_up_i) + ); + FDRE com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_h_alo_2_ ( + .CE(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_gnt), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_lnk_tfc_header[2]), + .Q(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_h_alo[2]), + .R(plm_link_up_i) + ); + FDRE com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_h_alo_3_ ( + .CE(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_gnt), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_lnk_tfc_header[3]), + .Q(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_h_alo[3]), + .R(plm_link_up_i) + ); + FDRE com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_h_alo_4_ ( + .CE(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_gnt), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_lnk_tfc_header[4]), + .Q(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_h_alo[4]), + .R(plm_link_up_i) + ); + FDSE com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_h_alo_5_ ( + .CE(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_gnt), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_lnk_tfc_header[5]), + .Q(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_h_alo[5]), + .S(plm_link_up_i) + ); + FDRE com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_h_alo_6_ ( + .CE(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_gnt), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_lnk_tfc_header[6]), + .Q(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_h_alo[6]), + .R(plm_link_up_i) + ); + FDRE com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_h_alo_7_ ( + .CE(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_gnt), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_lnk_tfc_header[7]), + .Q(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_h_alo[7]), + .R(plm_link_up_i) + ); + FDRE com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_d_alo_0_ ( + .CE(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_gnt), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_lnk_tfc_data[0]), + .Q(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_d_alo[0]), + .R(plm_link_up_i) + ); + FDRE com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_d_alo_1_ ( + .CE(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_gnt), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_lnk_tfc_data[1]), + .Q(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_d_alo[1]), + .R(plm_link_up_i) + ); + FDRE com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_d_alo_2_ ( + .CE(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_gnt), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_lnk_tfc_data[2]), + .Q(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_d_alo[2]), + .R(plm_link_up_i) + ); + FDRE com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_d_alo_3_ ( + .CE(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_gnt), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_lnk_tfc_data[3]), + .Q(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_d_alo[3]), + .R(plm_link_up_i) + ); + FDRE com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_d_alo_4_ ( + .CE(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_gnt), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_lnk_tfc_data[4]), + .Q(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_d_alo[4]), + .R(plm_link_up_i) + ); + FDSE com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_d_alo_5_ ( + .CE(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_gnt), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_lnk_tfc_data[5]), + .Q(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_d_alo[5]), + .S(plm_link_up_i) + ); + FDRE com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_d_alo_6_ ( + .CE(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_gnt), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_lnk_tfc_data[6]), + .Q(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_d_alo[6]), + .R(plm_link_up_i) + ); + FDRE com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_d_alo_7_ ( + .CE(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_gnt), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_lnk_tfc_data[7]), + .Q(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_d_alo[7]), + .R(plm_link_up_i) + ); + FDSE com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_d_alo_8_ ( + .CE(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_gnt), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_lnk_tfc_data[8]), + .Q(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_d_alo[8]), + .S(plm_link_up_i) + ); + FDRE com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_d_alo_9_ ( + .CE(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_gnt), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_lnk_tfc_data[9]), + .Q(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_d_alo[9]), + .R(plm_link_up_i) + ); + FDRE com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_d_alo_10_ ( + .CE(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_gnt), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_lnk_tfc_data[10]), + .Q(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_d_alo[10]), + .R(plm_link_up_i) + ); + FDRE com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_d_alo_11_ ( + .CE(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_gnt), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_lnk_tfc_data[11]), + .Q(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_d_alo[11]), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_free_q2 ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_free_q_4477), + .Q(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_free_q2_4589), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_req_h_o_0_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_h_o_0[0]), + .Q(com_tlm_u_tlm_rx_fc_req_ph[0]), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_req_h_o_1_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_h_o_0[1]), + .Q(com_tlm_u_tlm_rx_fc_req_ph[1]), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_req_h_o_2_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_h_o_0[2]), + .Q(com_tlm_u_tlm_rx_fc_req_ph[2]), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_req_h_o_3_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_h_o_0[3]), + .Q(com_tlm_u_tlm_rx_fc_req_ph[3]), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_req_h_o_4_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_h_o_0[4]), + .Q(com_tlm_u_tlm_rx_fc_req_ph[4]), + .R(plm_link_up_i) + ); + FDS com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_req_h_o_5_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_h_o_0[5]), + .Q(com_tlm_u_tlm_rx_fc_req_ph[5]), + .S(plm_link_up_i) + ); + FDR com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_req_h_o_6_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_h_o_0[6]), + .Q(com_tlm_u_tlm_rx_fc_req_ph[6]), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_req_h_o_7_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_h_o_0[7]), + .Q(com_tlm_u_tlm_rx_fc_req_ph[7]), + .R(plm_link_up_i) + ); + FDRSE com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_free_hold ( + .CE(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_send_state_0__4650), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_GND_4587), + .Q(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_free_hold_4590), + .R(plm_link_up_i), + .S(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_free_hold13) + ); + FDR com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_free_q ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_free_q_3), + .Q(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_free_q_4477), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_free_h ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_free_h_3), + .Q(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_free_h_4478), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_free_d ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_free_d_3), + .Q(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_free_d_4487), + .R(plm_link_up_i) + ); + MUXCY_L com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_h_o_cry_0 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_free_h_4478), + .DI(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_N_56076_i), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_h_o_cry_0_4479), + .S(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_h_o_axb_0_4600) + ); + XORCY com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_h_o_s_0 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_free_h_4478), + .LI(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_h_o_axb_0_4600), + .O(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_h_o_0[0]) + ); + MUXCY_L com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_h_o_cry_1 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_h_o_cry_0_4479), + .DI(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_GND_4587), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_h_o_cry_1_4480), + .S(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_h_o_axb_1_4599) + ); + XORCY com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_h_o_s_1 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_h_o_cry_0_4479), + .LI(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_h_o_axb_1_4599), + .O(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_h_o_0[1]) + ); + MUXCY_L com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_h_o_cry_2 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_h_o_cry_1_4480), + .DI(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_GND_4587), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_h_o_cry_2_4481), + .S(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_h_o_axb_2_4598) + ); + XORCY com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_h_o_s_2 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_h_o_cry_1_4480), + .LI(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_h_o_axb_2_4598), + .O(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_h_o_0[2]) + ); + MUXCY_L com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_h_o_cry_3 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_h_o_cry_2_4481), + .DI(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_GND_4587), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_h_o_cry_3_4482), + .S(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_h_o_axb_3_4597) + ); + XORCY com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_h_o_s_3 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_h_o_cry_2_4481), + .LI(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_h_o_axb_3_4597), + .O(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_h_o_0[3]) + ); + MUXCY_L com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_h_o_cry_4 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_h_o_cry_3_4482), + .DI(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_GND_4587), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_h_o_cry_4_4483), + .S(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_h_o_axb_4_4596) + ); + XORCY com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_h_o_s_4 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_h_o_cry_3_4482), + .LI(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_h_o_axb_4_4596), + .O(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_h_o_0[4]) + ); + MUXCY_L com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_h_o_cry_5 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_h_o_cry_4_4483), + .DI(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_GND_4587), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_h_o_cry_5_4484), + .S(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_h_o_axb_5_4595) + ); + XORCY com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_h_o_s_5 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_h_o_cry_4_4483), + .LI(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_h_o_axb_5_4595), + .O(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_h_o_0[5]) + ); + MUXCY_L com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_h_o_cry_6 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_h_o_cry_5_4484), + .DI(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_GND_4587), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_h_o_cry_6_4485), + .S(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_h_o_axb_6_4594) + ); + XORCY com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_h_o_s_6 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_h_o_cry_5_4484), + .LI(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_h_o_axb_6_4594), + .O(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_h_o_0[6]) + ); + XORCY com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_h_o_s_7 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_h_o_cry_6_4485), + .LI(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_h_o_axb_7_4593), + .O(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_h_o_0[7]) + ); + MULT_AND com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_d_o_cry_0 ( + .I0(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_N_56076_i), + .I1(com_tlm_u_tlm_rx_fc_use_data[0]), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_d_o_cry_0_0_4486) + ); + MUXCY_L com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_d_o_cry_0_0 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_free_d_4487), + .DI(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_d_o_cry_0_0_4486), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_d_o_cry_0_4489), + .S(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_d_o_axb_0_4634) + ); + XORCY com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_d_o_s_0 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_free_d_4487), + .LI(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_d_o_axb_0_4634), + .O(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_d_o_0[0]) + ); + MULT_AND com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_d_o_cry_1 ( + .I0(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_N_56076_i), + .I1(com_tlm_u_tlm_rx_fc_use_data[1]), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_d_o_cry_1_0_4488) + ); + MUXCY_L com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_d_o_cry_1_0 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_d_o_cry_0_4489), + .DI(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_d_o_cry_1_0_4488), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_d_o_cry_1_4491), + .S(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_d_o_axb_1_4633) + ); + XORCY com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_d_o_s_1 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_d_o_cry_0_4489), + .LI(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_d_o_axb_1_4633), + .O(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_d_o_0[1]) + ); + MULT_AND com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_d_o_cry_2 ( + .I0(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_N_56076_i), + .I1(com_tlm_u_tlm_rx_fc_use_data[2]), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_d_o_cry_2_0_4490) + ); + MUXCY_L com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_d_o_cry_2_0 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_d_o_cry_1_4491), + .DI(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_d_o_cry_2_0_4490), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_d_o_cry_2_4493), + .S(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_d_o_axb_2_4632) + ); + XORCY com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_d_o_s_2 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_d_o_cry_1_4491), + .LI(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_d_o_axb_2_4632), + .O(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_d_o_0[2]) + ); + MULT_AND com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_d_o_cry_3 ( + .I0(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_N_56076_i), + .I1(com_tlm_u_tlm_rx_fc_use_data[3]), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_d_o_cry_3_0_4492) + ); + MUXCY_L com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_d_o_cry_3_0 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_d_o_cry_2_4493), + .DI(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_d_o_cry_3_0_4492), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_d_o_cry_3_4495), + .S(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_d_o_axb_3_4631) + ); + XORCY com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_d_o_s_3 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_d_o_cry_2_4493), + .LI(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_d_o_axb_3_4631), + .O(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_d_o_0[3]) + ); + MULT_AND com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_d_o_cry_4 ( + .I0(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_N_56076_i), + .I1(com_tlm_u_tlm_rx_fc_use_data[4]), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_d_o_cry_4_0_4494) + ); + MUXCY_L com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_d_o_cry_4_0 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_d_o_cry_3_4495), + .DI(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_d_o_cry_4_0_4494), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_d_o_cry_4_4497), + .S(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_d_o_axb_4_4630) + ); + XORCY com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_d_o_s_4 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_d_o_cry_3_4495), + .LI(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_d_o_axb_4_4630), + .O(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_d_o_0[4]) + ); + MULT_AND com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_d_o_cry_5 ( + .I0(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_N_56076_i), + .I1(com_tlm_u_tlm_rx_fc_use_data[5]), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_d_o_cry_5_0_4496) + ); + MUXCY_L com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_d_o_cry_5_0 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_d_o_cry_4_4497), + .DI(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_d_o_cry_5_0_4496), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_d_o_cry_5_4498), + .S(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_d_o_axb_5_4629) + ); + XORCY com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_d_o_s_5 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_d_o_cry_4_4497), + .LI(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_d_o_axb_5_4629), + .O(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_d_o_0[5]) + ); + MUXCY_L com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_d_o_cry_6 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_d_o_cry_5_4498), + .DI(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_GND_4587), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_d_o_cry_6_4499), + .S(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_d_o_axb_6_4628) + ); + XORCY com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_d_o_s_6 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_d_o_cry_5_4498), + .LI(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_d_o_axb_6_4628), + .O(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_d_o_0[6]) + ); + MUXCY_L com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_d_o_cry_7 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_d_o_cry_6_4499), + .DI(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_GND_4587), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_d_o_cry_7_4500), + .S(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_d_o_axb_7_4627) + ); + XORCY com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_d_o_s_7 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_d_o_cry_6_4499), + .LI(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_d_o_axb_7_4627), + .O(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_d_o_0[7]) + ); + MUXCY_L com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_d_o_cry_8 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_d_o_cry_7_4500), + .DI(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_GND_4587), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_d_o_cry_8_4501), + .S(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_d_o_axb_8_4626) + ); + XORCY com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_d_o_s_8 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_d_o_cry_7_4500), + .LI(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_d_o_axb_8_4626), + .O(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_d_o_0[8]) + ); + MUXCY_L com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_d_o_cry_9 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_d_o_cry_8_4501), + .DI(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_GND_4587), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_d_o_cry_9_4502), + .S(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_d_o_axb_9_4625) + ); + XORCY com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_d_o_s_9 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_d_o_cry_8_4501), + .LI(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_d_o_axb_9_4625), + .O(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_d_o_0[9]) + ); + MUXCY_L com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_d_o_cry_10 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_d_o_cry_9_4502), + .DI(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_GND_4587), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_d_o_cry_10_4503), + .S(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_d_o_axb_10_4624) + ); + XORCY com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_d_o_s_10 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_d_o_cry_9_4502), + .LI(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_d_o_axb_10_4624), + .O(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_d_o_0[10]) + ); + XORCY com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_d_o_s_11 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_d_o_cry_10_4503), + .LI(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_d_o_axb_11_4623), + .O(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_d_o_0[11]) + ); + MUXCY_L com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_d_av_o_cry_0 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_VCC_4575), + .DI(com_tlm_u_tlm_rx_fc_req_pd[0]), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_d_av_o_cry_0_4505), + .S(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_d_av_o_axb_0_4613) + ); + MUXCY_L com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_d_av_o_cry_1 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_d_av_o_cry_0_4505), + .DI(com_tlm_u_tlm_rx_fc_req_pd[1]), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_d_av_o_cry_1_4507), + .S(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_d_av_o_axb_1_4611) + ); + XORCY com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_d_av_o_s_1 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_d_av_o_cry_0_4505), + .LI(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_d_av_o_axb_1_4611), + .O(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_d_av_o_s_1_4504) + ); + MUXCY_L com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_d_av_o_cry_2 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_d_av_o_cry_1_4507), + .DI(com_tlm_u_tlm_rx_fc_req_pd[2]), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_d_av_o_cry_2_4509), + .S(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_d_av_o_axb_2_4610) + ); + XORCY com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_d_av_o_s_2 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_d_av_o_cry_1_4507), + .LI(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_d_av_o_axb_2_4610), + .O(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_d_av_o_s_2_4506) + ); + MUXCY_L com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_d_av_o_cry_3 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_d_av_o_cry_2_4509), + .DI(com_tlm_u_tlm_rx_fc_req_pd[3]), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_d_av_o_cry_3_4511), + .S(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_d_av_o_axb_3_4609) + ); + XORCY com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_d_av_o_s_3 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_d_av_o_cry_2_4509), + .LI(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_d_av_o_axb_3_4609), + .O(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_d_av_o_s_3_4508) + ); + MUXCY_L com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_d_av_o_cry_4 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_d_av_o_cry_3_4511), + .DI(com_tlm_u_tlm_rx_fc_req_pd[4]), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_d_av_o_cry_4_4513), + .S(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_d_av_o_axb_4_4608) + ); + XORCY com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_d_av_o_s_4 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_d_av_o_cry_3_4511), + .LI(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_d_av_o_axb_4_4608), + .O(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_d_av_o_s_4_4510) + ); + MUXCY_L com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_d_av_o_cry_5 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_d_av_o_cry_4_4513), + .DI(com_tlm_u_tlm_rx_fc_req_pd[5]), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_d_av_o_cry_5_4515), + .S(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_d_av_o_axb_5_4607) + ); + XORCY com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_d_av_o_s_5 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_d_av_o_cry_4_4513), + .LI(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_d_av_o_axb_5_4607), + .O(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_d_av_o_s_5_4512) + ); + MUXCY_L com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_d_av_o_cry_6 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_d_av_o_cry_5_4515), + .DI(com_tlm_u_tlm_rx_fc_req_pd[6]), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_d_av_o_cry_6_4517), + .S(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_d_av_o_axb_6_4606) + ); + XORCY com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_d_av_o_s_6 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_d_av_o_cry_5_4515), + .LI(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_d_av_o_axb_6_4606), + .O(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_d_av_o_s_6_4514) + ); + MUXCY_L com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_d_av_o_cry_7 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_d_av_o_cry_6_4517), + .DI(com_tlm_u_tlm_rx_fc_req_pd[7]), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_d_av_o_cry_7_4519), + .S(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_d_av_o_axb_7_4605) + ); + XORCY com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_d_av_o_s_7 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_d_av_o_cry_6_4517), + .LI(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_d_av_o_axb_7_4605), + .O(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_d_av_o_s_7_4516) + ); + MUXCY_L com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_d_av_o_cry_8 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_d_av_o_cry_7_4519), + .DI(com_tlm_u_tlm_rx_fc_req_pd[8]), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_d_av_o_cry_8_4521), + .S(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_d_av_o_axb_8_4604) + ); + XORCY com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_d_av_o_s_8 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_d_av_o_cry_7_4519), + .LI(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_d_av_o_axb_8_4604), + .O(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_d_av_o_s_8_4518) + ); + MUXCY_L com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_d_av_o_cry_9 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_d_av_o_cry_8_4521), + .DI(com_tlm_u_tlm_rx_fc_req_pd[9]), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_d_av_o_cry_9_4523), + .S(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_d_av_o_axb_9_4603) + ); + XORCY com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_d_av_o_s_9 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_d_av_o_cry_8_4521), + .LI(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_d_av_o_axb_9_4603), + .O(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_d_av_o_s_9_4520) + ); + MUXCY_L com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_d_av_o_cry_10 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_d_av_o_cry_9_4523), + .DI(com_tlm_u_tlm_rx_fc_req_pd[10]), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_d_av_o_cry_10_4525), + .S(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_d_av_o_axb_10_4602) + ); + XORCY com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_d_av_o_s_10 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_d_av_o_cry_9_4523), + .LI(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_d_av_o_axb_10_4602), + .O(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_d_av_o_s_10_4522) + ); + XORCY com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_d_av_o_s_11 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_d_av_o_cry_10_4525), + .LI(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_d_av_o_axb_11_4601), + .O(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_d_av_o_s_11_4524) + ); + MULT_AND com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un1_fc_d_con_1_cry_0 ( + .I0(com_tlm_u_tlm_rx_fc_use_p), + .I1(com_tlm_u_tlm_rx_fc_use_data[0]), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un1_fc_d_con_1_cry_0_0_4526) + ); + MUXCY_L com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un1_fc_d_con_1_cry_0_0 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_GND_4587), + .DI(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un1_fc_d_con_1_cry_0_0_4526), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un1_fc_d_con_1_cry_0_4529), + .S(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un1_fc_d_con_1_axb_0_4588) + ); + MULT_AND com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un1_fc_d_con_1_cry_1 ( + .I0(com_tlm_u_tlm_rx_fc_use_p), + .I1(com_tlm_u_tlm_rx_fc_use_data[1]), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un1_fc_d_con_1_cry_1_0_4527) + ); + MUXCY_L com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un1_fc_d_con_1_cry_1_0 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un1_fc_d_con_1_cry_0_4529), + .DI(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un1_fc_d_con_1_cry_1_0_4527), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un1_fc_d_con_1_cry_1_4532), + .S(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un1_fc_d_con_1_axb_1_4645) + ); + XORCY com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un1_fc_d_con_1_s_1 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un1_fc_d_con_1_cry_0_4529), + .LI(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un1_fc_d_con_1_axb_1_4645), + .O(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un1_fc_d_con_1_s_1_4528) + ); + MULT_AND com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un1_fc_d_con_1_cry_2 ( + .I0(com_tlm_u_tlm_rx_fc_use_p), + .I1(com_tlm_u_tlm_rx_fc_use_data[2]), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un1_fc_d_con_1_cry_2_0_4530) + ); + MUXCY_L com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un1_fc_d_con_1_cry_2_0 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un1_fc_d_con_1_cry_1_4532), + .DI(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un1_fc_d_con_1_cry_2_0_4530), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un1_fc_d_con_1_cry_2_4535), + .S(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un1_fc_d_con_1_axb_2_4644) + ); + XORCY com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un1_fc_d_con_1_s_2 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un1_fc_d_con_1_cry_1_4532), + .LI(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un1_fc_d_con_1_axb_2_4644), + .O(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un1_fc_d_con_1_s_2_4531) + ); + MULT_AND com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un1_fc_d_con_1_cry_3 ( + .I0(com_tlm_u_tlm_rx_fc_use_p), + .I1(com_tlm_u_tlm_rx_fc_use_data[3]), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un1_fc_d_con_1_cry_3_0_4533) + ); + MUXCY_L com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un1_fc_d_con_1_cry_3_0 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un1_fc_d_con_1_cry_2_4535), + .DI(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un1_fc_d_con_1_cry_3_0_4533), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un1_fc_d_con_1_cry_3_4538), + .S(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un1_fc_d_con_1_axb_3_4643) + ); + XORCY com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un1_fc_d_con_1_s_3 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un1_fc_d_con_1_cry_2_4535), + .LI(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un1_fc_d_con_1_axb_3_4643), + .O(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un1_fc_d_con_1_s_3_4534) + ); + MULT_AND com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un1_fc_d_con_1_cry_4 ( + .I0(com_tlm_u_tlm_rx_fc_use_p), + .I1(com_tlm_u_tlm_rx_fc_use_data[4]), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un1_fc_d_con_1_cry_4_0_4536) + ); + MUXCY_L com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un1_fc_d_con_1_cry_4_0 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un1_fc_d_con_1_cry_3_4538), + .DI(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un1_fc_d_con_1_cry_4_0_4536), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un1_fc_d_con_1_cry_4_4541), + .S(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un1_fc_d_con_1_axb_4_4642) + ); + XORCY com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un1_fc_d_con_1_s_4 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un1_fc_d_con_1_cry_3_4538), + .LI(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un1_fc_d_con_1_axb_4_4642), + .O(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un1_fc_d_con_1_s_4_4537) + ); + MULT_AND com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un1_fc_d_con_1_cry_5 ( + .I0(com_tlm_u_tlm_rx_fc_use_p), + .I1(com_tlm_u_tlm_rx_fc_use_data[5]), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un1_fc_d_con_1_cry_5_0_4539) + ); + MUXCY_L com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un1_fc_d_con_1_cry_5_0 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un1_fc_d_con_1_cry_4_4541), + .DI(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un1_fc_d_con_1_cry_5_0_4539), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un1_fc_d_con_1_cry_5_4543), + .S(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un1_fc_d_con_1_axb_5_4641) + ); + XORCY com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un1_fc_d_con_1_s_5 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un1_fc_d_con_1_cry_4_4541), + .LI(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un1_fc_d_con_1_axb_5_4641), + .O(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un1_fc_d_con_1_s_5_4540) + ); + MUXCY_L com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un1_fc_d_con_1_cry_6 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un1_fc_d_con_1_cry_5_4543), + .DI(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_GND_4587), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un1_fc_d_con_1_cry_6_4545), + .S(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un1_fc_d_con_1_axb_6_4640) + ); + XORCY com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un1_fc_d_con_1_s_6 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un1_fc_d_con_1_cry_5_4543), + .LI(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un1_fc_d_con_1_axb_6_4640), + .O(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un1_fc_d_con_1_s_6_4542) + ); + MUXCY_L com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un1_fc_d_con_1_cry_7 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un1_fc_d_con_1_cry_6_4545), + .DI(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_GND_4587), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un1_fc_d_con_1_cry_7_4547), + .S(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un1_fc_d_con_1_axb_7_4639) + ); + XORCY com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un1_fc_d_con_1_s_7 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un1_fc_d_con_1_cry_6_4545), + .LI(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un1_fc_d_con_1_axb_7_4639), + .O(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un1_fc_d_con_1_s_7_4544) + ); + MUXCY_L com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un1_fc_d_con_1_cry_8 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un1_fc_d_con_1_cry_7_4547), + .DI(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_GND_4587), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un1_fc_d_con_1_cry_8_4549), + .S(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un1_fc_d_con_1_axb_8_4638) + ); + XORCY com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un1_fc_d_con_1_s_8 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un1_fc_d_con_1_cry_7_4547), + .LI(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un1_fc_d_con_1_axb_8_4638), + .O(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un1_fc_d_con_1_s_8_4546) + ); + MUXCY_L com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un1_fc_d_con_1_cry_9 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un1_fc_d_con_1_cry_8_4549), + .DI(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_GND_4587), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un1_fc_d_con_1_cry_9_4551), + .S(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un1_fc_d_con_1_axb_9_4637) + ); + XORCY com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un1_fc_d_con_1_s_9 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un1_fc_d_con_1_cry_8_4549), + .LI(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un1_fc_d_con_1_axb_9_4637), + .O(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un1_fc_d_con_1_s_9_4548) + ); + MUXCY_L com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un1_fc_d_con_1_cry_10 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un1_fc_d_con_1_cry_9_4551), + .DI(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_GND_4587), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un1_fc_d_con_1_cry_10_4553), + .S(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un1_fc_d_con_1_axb_10_4636) + ); + XORCY com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un1_fc_d_con_1_s_10 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un1_fc_d_con_1_cry_9_4551), + .LI(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un1_fc_d_con_1_axb_10_4636), + .O(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un1_fc_d_con_1_s_10_4550) + ); + XORCY com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un1_fc_d_con_1_s_11 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un1_fc_d_con_1_cry_10_4553), + .LI(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un1_fc_d_con_1_axb_11_4635), + .O(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un1_fc_d_con_1_s_11_4552) + ); + MUXCY_L com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_h_av_o_cry_0 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_VCC_4575), + .DI(com_tlm_u_tlm_rx_fc_req_ph[0]), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_h_av_o_cry_0_4555), + .S(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_h_av_o_axb_0_4622) + ); + MUXCY_L com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_h_av_o_cry_1 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_h_av_o_cry_0_4555), + .DI(com_tlm_u_tlm_rx_fc_req_ph[1]), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_h_av_o_cry_1_4557), + .S(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_h_av_o_axb_1_4620) + ); + XORCY com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_h_av_o_s_1 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_h_av_o_cry_0_4555), + .LI(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_h_av_o_axb_1_4620), + .O(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_h_av_o_s_1_4554) + ); + MUXCY_L com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_h_av_o_cry_2 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_h_av_o_cry_1_4557), + .DI(com_tlm_u_tlm_rx_fc_req_ph[2]), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_h_av_o_cry_2_4559), + .S(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_h_av_o_axb_2_4619) + ); + XORCY com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_h_av_o_s_2 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_h_av_o_cry_1_4557), + .LI(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_h_av_o_axb_2_4619), + .O(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_h_av_o_s_2_4556) + ); + MUXCY_L com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_h_av_o_cry_3 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_h_av_o_cry_2_4559), + .DI(com_tlm_u_tlm_rx_fc_req_ph[3]), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_h_av_o_cry_3_4561), + .S(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_h_av_o_axb_3_4618) + ); + XORCY com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_h_av_o_s_3 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_h_av_o_cry_2_4559), + .LI(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_h_av_o_axb_3_4618), + .O(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_h_av_o_s_3_4558) + ); + MUXCY_L com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_h_av_o_cry_4 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_h_av_o_cry_3_4561), + .DI(com_tlm_u_tlm_rx_fc_req_ph[4]), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_h_av_o_cry_4_4563), + .S(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_h_av_o_axb_4_4617) + ); + XORCY com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_h_av_o_s_4 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_h_av_o_cry_3_4561), + .LI(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_h_av_o_axb_4_4617), + .O(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_h_av_o_s_4_4560) + ); + MUXCY_L com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_h_av_o_cry_5 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_h_av_o_cry_4_4563), + .DI(com_tlm_u_tlm_rx_fc_req_ph[5]), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_h_av_o_cry_5_4565), + .S(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_h_av_o_axb_5_4616) + ); + XORCY com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_h_av_o_s_5 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_h_av_o_cry_4_4563), + .LI(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_h_av_o_axb_5_4616), + .O(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_h_av_o_s_5_4562) + ); + MUXCY_L com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_h_av_o_cry_6 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_h_av_o_cry_5_4565), + .DI(com_tlm_u_tlm_rx_fc_req_ph[6]), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_h_av_o_cry_6_4567), + .S(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_h_av_o_axb_6_4615) + ); + XORCY com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_h_av_o_s_6 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_h_av_o_cry_5_4565), + .LI(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_h_av_o_axb_6_4615), + .O(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_h_av_o_s_6_4564) + ); + XORCY com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_h_av_o_s_7 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_h_av_o_cry_6_4567), + .LI(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_h_av_o_axb_7_4614), + .O(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_h_av_o_s_7_4566) + ); + MUXCY_L com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_h_advert_1_cry_0 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_VCC_4575), + .DI(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_h_alo[0]), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_h_advert_1_cry_0_4568), + .S(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_h_advert_1_axb_0_4668) + ); + MUXCY_L com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_h_advert_1_cry_1 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_h_advert_1_cry_0_4568), + .DI(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_h_alo[1]), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_h_advert_1_cry_1_4569), + .S(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_h_advert_1_axb_1_4667) + ); + MUXCY_L com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_h_advert_1_cry_2 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_h_advert_1_cry_1_4569), + .DI(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_h_alo[2]), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_h_advert_1_cry_2_4570), + .S(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_h_advert_1_axb_2_4666) + ); + MUXCY_L com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_h_advert_1_cry_3 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_h_advert_1_cry_2_4570), + .DI(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_h_alo[3]), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_h_advert_1_cry_3_4571), + .S(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_h_advert_1_axb_3_4665) + ); + MUXCY_L com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_h_advert_1_cry_4 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_h_advert_1_cry_3_4571), + .DI(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_h_alo[4]), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_h_advert_1_cry_4_4572), + .S(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_h_advert_1_axb_4_4664) + ); + MUXCY_L com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_h_advert_1_cry_5 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_h_advert_1_cry_4_4572), + .DI(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_h_alo[5]), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_h_advert_1_cry_5_4573), + .S(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_h_advert_1_axb_5_4663) + ); + MUXCY_L com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_h_advert_1_cry_6 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_h_advert_1_cry_5_4573), + .DI(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_h_alo[6]), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_h_advert_1_cry_6_4574), + .S(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_h_advert_1_axb_6_4662) + ); + XORCY com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_h_advert_1_s_7 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_h_advert_1_cry_6_4574), + .LI(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_h_advert_1_axb_7_4592), + .O(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_h_advert_1[7]) + ); + MUXCY_L com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_d_advert_1_cry_0 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_VCC_4575), + .DI(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_d_alo[0]), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_d_advert_1_cry_0_4576), + .S(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_d_advert_1_axb_0_4661) + ); + MUXCY_L com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_d_advert_1_cry_1 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_d_advert_1_cry_0_4576), + .DI(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_d_alo[1]), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_d_advert_1_cry_1_4577), + .S(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_d_advert_1_axb_1_4660) + ); + MUXCY_L com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_d_advert_1_cry_2 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_d_advert_1_cry_1_4577), + .DI(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_d_alo[2]), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_d_advert_1_cry_2_4578), + .S(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_d_advert_1_axb_2_4659) + ); + MUXCY_L com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_d_advert_1_cry_3 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_d_advert_1_cry_2_4578), + .DI(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_d_alo[3]), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_d_advert_1_cry_3_4579), + .S(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_d_advert_1_axb_3_4658) + ); + MUXCY_L com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_d_advert_1_cry_4 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_d_advert_1_cry_3_4579), + .DI(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_d_alo[4]), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_d_advert_1_cry_4_4580), + .S(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_d_advert_1_axb_4_4657) + ); + MUXCY_L com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_d_advert_1_cry_5 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_d_advert_1_cry_4_4580), + .DI(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_d_alo[5]), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_d_advert_1_cry_5_4581), + .S(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_d_advert_1_axb_5_4656) + ); + MUXCY_L com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_d_advert_1_cry_6 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_d_advert_1_cry_5_4581), + .DI(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_d_alo[6]), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_d_advert_1_cry_6_4582), + .S(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_d_advert_1_axb_6_4655) + ); + MUXCY_L com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_d_advert_1_cry_7 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_d_advert_1_cry_6_4582), + .DI(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_d_alo[7]), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_d_advert_1_cry_7_4583), + .S(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_d_advert_1_axb_7_4654) + ); + MUXCY_L com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_d_advert_1_cry_8 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_d_advert_1_cry_7_4583), + .DI(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_d_alo[8]), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_d_advert_1_cry_8_4584), + .S(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_d_advert_1_axb_8_4653) + ); + MUXCY_L com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_d_advert_1_cry_9 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_d_advert_1_cry_8_4584), + .DI(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_d_alo[9]), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_d_advert_1_cry_9_4585), + .S(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_d_advert_1_axb_9_4652) + ); + MUXCY_L com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_d_advert_1_cry_10 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_d_advert_1_cry_9_4585), + .DI(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_d_alo[10]), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_d_advert_1_cry_10_4586), + .S(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_d_advert_1_axb_10_4651) + ); + XORCY com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_d_advert_1_s_11 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_d_advert_1_cry_10_4586), + .LI(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_d_advert_1_axb_11_4591), + .O(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_d_advert_1[11]) + ); + FDRE com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_h_con_0_ ( + .CE(com_tlm_u_tlm_rx_fc_use_p), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_h_con_s[0]), + .Q(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_h_con[0]), + .R(plm_link_up_i) + ); + MUXCY_L com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_h_con_cry_1_ ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_h_con[0]), + .DI(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_GND_4587), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_h_con_cry[1]), + .S(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_h_con_qxu[1]) + ); + XORCY com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_h_con_s_1_ ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_h_con[0]), + .LI(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_h_con_qxu[1]), + .O(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_h_con_s[1]) + ); + FDRE com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_h_con_1_ ( + .CE(com_tlm_u_tlm_rx_fc_use_p), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_h_con_s[1]), + .Q(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_h_con[1]), + .R(plm_link_up_i) + ); + MUXCY_L com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_h_con_cry_2_ ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_h_con_cry[1]), + .DI(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_GND_4587), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_h_con_cry[2]), + .S(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_h_con_qxu[2]) + ); + XORCY com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_h_con_s_2_ ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_h_con_cry[1]), + .LI(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_h_con_qxu[2]), + .O(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_h_con_s[2]) + ); + FDRE com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_h_con_2_ ( + .CE(com_tlm_u_tlm_rx_fc_use_p), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_h_con_s[2]), + .Q(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_h_con[2]), + .R(plm_link_up_i) + ); + MUXCY_L com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_h_con_cry_3_ ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_h_con_cry[2]), + .DI(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_GND_4587), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_h_con_cry[3]), + .S(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_h_con_qxu[3]) + ); + XORCY com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_h_con_s_3_ ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_h_con_cry[2]), + .LI(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_h_con_qxu[3]), + .O(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_h_con_s[3]) + ); + FDRE com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_h_con_3_ ( + .CE(com_tlm_u_tlm_rx_fc_use_p), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_h_con_s[3]), + .Q(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_h_con[3]), + .R(plm_link_up_i) + ); + MUXCY_L com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_h_con_cry_4_ ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_h_con_cry[3]), + .DI(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_GND_4587), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_h_con_cry[4]), + .S(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_h_con_qxu[4]) + ); + XORCY com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_h_con_s_4_ ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_h_con_cry[3]), + .LI(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_h_con_qxu[4]), + .O(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_h_con_s[4]) + ); + FDRE com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_h_con_4_ ( + .CE(com_tlm_u_tlm_rx_fc_use_p), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_h_con_s[4]), + .Q(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_h_con[4]), + .R(plm_link_up_i) + ); + MUXCY_L com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_h_con_cry_5_ ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_h_con_cry[4]), + .DI(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_GND_4587), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_h_con_cry[5]), + .S(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_h_con_qxu[5]) + ); + XORCY com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_h_con_s_5_ ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_h_con_cry[4]), + .LI(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_h_con_qxu[5]), + .O(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_h_con_s[5]) + ); + FDRE com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_h_con_5_ ( + .CE(com_tlm_u_tlm_rx_fc_use_p), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_h_con_s[5]), + .Q(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_h_con[5]), + .R(plm_link_up_i) + ); + MUXCY_L com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_h_con_cry_6_ ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_h_con_cry[5]), + .DI(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_GND_4587), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_h_con_cry[6]), + .S(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_h_con_qxu[6]) + ); + XORCY com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_h_con_s_6_ ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_h_con_cry[5]), + .LI(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_h_con_qxu[6]), + .O(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_h_con_s[6]) + ); + FDRE com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_h_con_6_ ( + .CE(com_tlm_u_tlm_rx_fc_use_p), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_h_con_s[6]), + .Q(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_h_con[6]), + .R(plm_link_up_i) + ); + XORCY com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_h_con_s_7_ ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_h_con_cry[6]), + .LI(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_h_con_qxu[7]), + .O(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_h_con_s[7]) + ); + FDRE com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_h_con_7_ ( + .CE(com_tlm_u_tlm_rx_fc_use_p), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_h_con_s[7]), + .Q(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_h_con[7]), + .R(plm_link_up_i) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_unuse_direct_N_44083_i_0_o3.INIT = 4'h8; + LUT2 com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_unuse_direct_N_44083_i_0_o3 ( + .I0(com_tlm_u_tlm_rx_fc_unuse), + .I1(com_tlm_u_tlm_rx_fc_use_p), + .O(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_N_56076_i) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_free_hold13_0_a2_0_a2_0_a2.INIT = 4'h2; + LUT2 com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_free_hold13_0_a2_0_a2_0_a2 ( + .I0(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_free_q2_4589), + .I1(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_send_state_0__4650), + .O(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_free_hold13) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_send_state_13_0_i_0_0_a2_2_.INIT = 4'h8; + LUT2 com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_send_state_13_0_i_0_0_a2_2_ ( + .I0(com_tlm_u_tlm_rx_fc_req_p_dst_rdy), + .I1(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_req_p_src_rdy), + .O(com_tlm_u_tlm_rx_fc_send_state_0_sqmuxa) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_d_av_o_axb_0.INIT = 4'h9; + LUT2 com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_d_av_o_axb_0 ( + .I0(com_tlm_u_tlm_rx_fc_req_pd[0]), + .I1(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_d_con[0]), + .O(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_d_av_o_axb_0_4613) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_h_av_o_axb_0.INIT = 4'h9; + LUT2 com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_h_av_o_axb_0 ( + .I0(com_tlm_u_tlm_rx_fc_req_ph[0]), + .I1(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_h_con[0]), + .O(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_h_av_o_axb_0_4622) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un1_fc_d_con_1_axb_0.INIT = 8'h78; + LUT3 com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un1_fc_d_con_1_axb_0 ( + .I0(com_tlm_u_tlm_rx_fc_use_data[0]), + .I1(com_tlm_u_tlm_rx_fc_use_p), + .I2(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_d_con[0]), + .O(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un1_fc_d_con_1_axb_0_4588) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_send_state_13_0_i_0_0_o3_1_.INIT = 16'h0001; + LUT4 com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_send_state_13_0_i_0_0_o3_1_ ( + .I0(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_N_56076_i), + .I1(com_tlm_u_tlm_rx_vc0_flow_ctrl_lat_timer[9]), + .I2(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_free_hold_4590), + .I3(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_free_q2_4589), + .O(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_N_57046_i) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_gnt_0_a2_0_a2_0_a2_0_a2.INIT = 4'h4; + LUT2 com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_gnt_0_a2_0_a2_0_a2_0_a2 ( + .I0(com_lnk_tfc_type[0]), + .I1(com_tlm_u_tlm_rx_vc0_flow_ctrl_fc_gnt_3), + .O(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_gnt) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_d_advert_1_axb_11.INIT = 4'h9; + LUT2_L com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_d_advert_1_axb_11 ( + .I0(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_d_alo[11]), + .I1(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_d_con[11]), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_d_advert_1_axb_11_4591) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_h_advert_1_axb_7.INIT = 4'h9; + LUT2_L com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_h_advert_1_axb_7 ( + .I0(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_h_alo[7]), + .I1(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_h_con[7]), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_h_advert_1_axb_7_4592) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_free_d_3_0_a2.INIT = 4'h8; + LUT2_L com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_free_d_3_0_a2 ( + .I0(com_tlm_u_tlm_rx_vc0_fc_free_1data), + .I1(com_tlm_u_tlm_rx_vc0_fc_free_p), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_free_d_3) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_free_h_3_0_a2.INIT = 4'h8; + LUT2_L com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_free_h_3_0_a2 ( + .I0(com_tlm_u_tlm_rx_vc0_fc_free_1header), + .I1(com_tlm_u_tlm_rx_vc0_fc_free_p), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_free_h_3) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_free_q_3_0_a2.INIT = 4'h8; + LUT2_L com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_free_q_3_0_a2 ( + .I0(com_tlm_u_tlm_rx_vc0_fc_free_eof), + .I1(com_tlm_u_tlm_rx_vc0_fc_free_p), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_free_q_3) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_h_o_axb_7.INIT = 4'h2; + LUT1_L com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_h_o_axb_7 ( + .I0(com_tlm_u_tlm_rx_fc_req_ph[7]), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_h_o_axb_7_4593) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_h_o_axb_6.INIT = 4'h2; + LUT1_L com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_h_o_axb_6 ( + .I0(com_tlm_u_tlm_rx_fc_req_ph[6]), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_h_o_axb_6_4594) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_h_o_axb_5.INIT = 4'h2; + LUT1_L com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_h_o_axb_5 ( + .I0(com_tlm_u_tlm_rx_fc_req_ph[5]), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_h_o_axb_5_4595) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_h_o_axb_4.INIT = 4'h2; + LUT1_L com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_h_o_axb_4 ( + .I0(com_tlm_u_tlm_rx_fc_req_ph[4]), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_h_o_axb_4_4596) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_h_o_axb_3.INIT = 4'h2; + LUT1_L com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_h_o_axb_3 ( + .I0(com_tlm_u_tlm_rx_fc_req_ph[3]), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_h_o_axb_3_4597) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_h_o_axb_2.INIT = 4'h2; + LUT1_L com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_h_o_axb_2 ( + .I0(com_tlm_u_tlm_rx_fc_req_ph[2]), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_h_o_axb_2_4598) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_h_o_axb_1.INIT = 4'h2; + LUT1_L com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_h_o_axb_1 ( + .I0(com_tlm_u_tlm_rx_fc_req_ph[1]), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_h_o_axb_1_4599) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_h_o_axb_0.INIT = 4'h6; + LUT2_L com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_h_o_axb_0 ( + .I0(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_N_56076_i), + .I1(com_tlm_u_tlm_rx_fc_req_ph[0]), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_h_o_axb_0_4600) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_d_av_o_axb_11.INIT = 4'h9; + LUT2_L com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_d_av_o_axb_11 ( + .I0(com_tlm_u_tlm_rx_fc_req_pd[11]), + .I1(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_d_con[11]), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_d_av_o_axb_11_4601) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_d_av_o_axb_10.INIT = 4'h9; + LUT2_L com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_d_av_o_axb_10 ( + .I0(com_tlm_u_tlm_rx_fc_req_pd[10]), + .I1(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_d_con[10]), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_d_av_o_axb_10_4602) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_d_av_o_axb_9.INIT = 4'h9; + LUT2_L com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_d_av_o_axb_9 ( + .I0(com_tlm_u_tlm_rx_fc_req_pd[9]), + .I1(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_d_con[9]), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_d_av_o_axb_9_4603) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_d_av_o_axb_8.INIT = 4'h9; + LUT2_L com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_d_av_o_axb_8 ( + .I0(com_tlm_u_tlm_rx_fc_req_pd[8]), + .I1(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_d_con[8]), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_d_av_o_axb_8_4604) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_d_av_o_axb_7.INIT = 4'h9; + LUT2_L com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_d_av_o_axb_7 ( + .I0(com_tlm_u_tlm_rx_fc_req_pd[7]), + .I1(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_d_con[7]), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_d_av_o_axb_7_4605) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_d_av_o_axb_6.INIT = 4'h9; + LUT2_L com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_d_av_o_axb_6 ( + .I0(com_tlm_u_tlm_rx_fc_req_pd[6]), + .I1(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_d_con[6]), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_d_av_o_axb_6_4606) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_d_av_o_axb_5.INIT = 4'h9; + LUT2_L com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_d_av_o_axb_5 ( + .I0(com_tlm_u_tlm_rx_fc_req_pd[5]), + .I1(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_d_con[5]), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_d_av_o_axb_5_4607) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_d_av_o_axb_4.INIT = 4'h9; + LUT2_L com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_d_av_o_axb_4 ( + .I0(com_tlm_u_tlm_rx_fc_req_pd[4]), + .I1(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_d_con[4]), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_d_av_o_axb_4_4608) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_d_av_o_axb_3.INIT = 4'h9; + LUT2_L com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_d_av_o_axb_3 ( + .I0(com_tlm_u_tlm_rx_fc_req_pd[3]), + .I1(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_d_con[3]), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_d_av_o_axb_3_4609) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_d_av_o_axb_2.INIT = 4'h9; + LUT2_L com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_d_av_o_axb_2 ( + .I0(com_tlm_u_tlm_rx_fc_req_pd[2]), + .I1(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_d_con[2]), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_d_av_o_axb_2_4610) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_d_av_o_axb_1.INIT = 4'h9; + LUT2_L com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_d_av_o_axb_1 ( + .I0(com_tlm_u_tlm_rx_fc_req_pd[1]), + .I1(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_d_con[1]), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_d_av_o_axb_1_4611) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_d_av_o_axb_0_i.INIT = 4'h1; + LUT1_L com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_d_av_o_axb_0_i ( + .I0(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_d_av_o_axb_0_4613), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_d_av_o_axb_0_i_4612) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_h_av_o_axb_7.INIT = 4'h9; + LUT2_L com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_h_av_o_axb_7 ( + .I0(com_tlm_u_tlm_rx_fc_req_ph[7]), + .I1(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_h_con[7]), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_h_av_o_axb_7_4614) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_h_av_o_axb_6.INIT = 4'h9; + LUT2_L com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_h_av_o_axb_6 ( + .I0(com_tlm_u_tlm_rx_fc_req_ph[6]), + .I1(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_h_con[6]), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_h_av_o_axb_6_4615) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_h_av_o_axb_5.INIT = 4'h9; + LUT2_L com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_h_av_o_axb_5 ( + .I0(com_tlm_u_tlm_rx_fc_req_ph[5]), + .I1(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_h_con[5]), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_h_av_o_axb_5_4616) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_h_av_o_axb_4.INIT = 4'h9; + LUT2_L com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_h_av_o_axb_4 ( + .I0(com_tlm_u_tlm_rx_fc_req_ph[4]), + .I1(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_h_con[4]), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_h_av_o_axb_4_4617) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_h_av_o_axb_3.INIT = 4'h9; + LUT2_L com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_h_av_o_axb_3 ( + .I0(com_tlm_u_tlm_rx_fc_req_ph[3]), + .I1(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_h_con[3]), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_h_av_o_axb_3_4618) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_h_av_o_axb_2.INIT = 4'h9; + LUT2_L com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_h_av_o_axb_2 ( + .I0(com_tlm_u_tlm_rx_fc_req_ph[2]), + .I1(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_h_con[2]), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_h_av_o_axb_2_4619) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_h_av_o_axb_1.INIT = 4'h9; + LUT2_L com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_h_av_o_axb_1 ( + .I0(com_tlm_u_tlm_rx_fc_req_ph[1]), + .I1(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_h_con[1]), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_h_av_o_axb_1_4620) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_h_av_o_axb_0_i.INIT = 4'h1; + LUT1_L com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_h_av_o_axb_0_i ( + .I0(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_h_av_o_axb_0_4622), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_h_av_o_axb_0_i_4621) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_d_o_axb_11.INIT = 4'h2; + LUT1_L com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_d_o_axb_11 ( + .I0(com_tlm_u_tlm_rx_fc_req_pd[11]), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_d_o_axb_11_4623) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_d_o_axb_10.INIT = 4'h2; + LUT1_L com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_d_o_axb_10 ( + .I0(com_tlm_u_tlm_rx_fc_req_pd[10]), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_d_o_axb_10_4624) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_d_o_axb_9.INIT = 4'h2; + LUT1_L com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_d_o_axb_9 ( + .I0(com_tlm_u_tlm_rx_fc_req_pd[9]), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_d_o_axb_9_4625) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_d_o_axb_8.INIT = 4'h2; + LUT1_L com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_d_o_axb_8 ( + .I0(com_tlm_u_tlm_rx_fc_req_pd[8]), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_d_o_axb_8_4626) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_d_o_axb_7.INIT = 4'h2; + LUT1_L com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_d_o_axb_7 ( + .I0(com_tlm_u_tlm_rx_fc_req_pd[7]), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_d_o_axb_7_4627) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_d_o_axb_6.INIT = 4'h2; + LUT1_L com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_d_o_axb_6 ( + .I0(com_tlm_u_tlm_rx_fc_req_pd[6]), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_d_o_axb_6_4628) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_d_o_axb_5.INIT = 8'h6C; + LUT3_L com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_d_o_axb_5 ( + .I0(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_N_56076_i), + .I1(com_tlm_u_tlm_rx_fc_req_pd[5]), + .I2(com_tlm_u_tlm_rx_fc_use_data[5]), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_d_o_axb_5_4629) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_d_o_axb_4.INIT = 8'h6C; + LUT3_L com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_d_o_axb_4 ( + .I0(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_N_56076_i), + .I1(com_tlm_u_tlm_rx_fc_req_pd[4]), + .I2(com_tlm_u_tlm_rx_fc_use_data[4]), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_d_o_axb_4_4630) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_d_o_axb_3.INIT = 8'h6C; + LUT3_L com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_d_o_axb_3 ( + .I0(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_N_56076_i), + .I1(com_tlm_u_tlm_rx_fc_req_pd[3]), + .I2(com_tlm_u_tlm_rx_fc_use_data[3]), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_d_o_axb_3_4631) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_d_o_axb_2.INIT = 8'h6C; + LUT3_L com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_d_o_axb_2 ( + .I0(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_N_56076_i), + .I1(com_tlm_u_tlm_rx_fc_req_pd[2]), + .I2(com_tlm_u_tlm_rx_fc_use_data[2]), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_d_o_axb_2_4632) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_d_o_axb_1.INIT = 8'h6C; + LUT3_L com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_d_o_axb_1 ( + .I0(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_N_56076_i), + .I1(com_tlm_u_tlm_rx_fc_req_pd[1]), + .I2(com_tlm_u_tlm_rx_fc_use_data[1]), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_d_o_axb_1_4633) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_d_o_axb_0.INIT = 8'h6C; + LUT3_L com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_d_o_axb_0 ( + .I0(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_N_56076_i), + .I1(com_tlm_u_tlm_rx_fc_req_pd[0]), + .I2(com_tlm_u_tlm_rx_fc_use_data[0]), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un13_fc_req_d_o_axb_0_4634) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un1_fc_d_con_1_axb_11.INIT = 4'h2; + LUT1_L com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un1_fc_d_con_1_axb_11 ( + .I0(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_d_con[11]), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un1_fc_d_con_1_axb_11_4635) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un1_fc_d_con_1_axb_10.INIT = 4'h2; + LUT1_L com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un1_fc_d_con_1_axb_10 ( + .I0(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_d_con[10]), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un1_fc_d_con_1_axb_10_4636) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un1_fc_d_con_1_axb_9.INIT = 4'h2; + LUT1_L com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un1_fc_d_con_1_axb_9 ( + .I0(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_d_con[9]), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un1_fc_d_con_1_axb_9_4637) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un1_fc_d_con_1_axb_8.INIT = 4'h2; + LUT1_L com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un1_fc_d_con_1_axb_8 ( + .I0(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_d_con[8]), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un1_fc_d_con_1_axb_8_4638) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un1_fc_d_con_1_axb_7.INIT = 4'h2; + LUT1_L com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un1_fc_d_con_1_axb_7 ( + .I0(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_d_con[7]), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un1_fc_d_con_1_axb_7_4639) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un1_fc_d_con_1_axb_6.INIT = 4'h2; + LUT1_L com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un1_fc_d_con_1_axb_6 ( + .I0(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_d_con[6]), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un1_fc_d_con_1_axb_6_4640) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un1_fc_d_con_1_axb_5.INIT = 8'h78; + LUT3_L com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un1_fc_d_con_1_axb_5 ( + .I0(com_tlm_u_tlm_rx_fc_use_data[5]), + .I1(com_tlm_u_tlm_rx_fc_use_p), + .I2(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_d_con[5]), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un1_fc_d_con_1_axb_5_4641) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un1_fc_d_con_1_axb_4.INIT = 8'h78; + LUT3_L com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un1_fc_d_con_1_axb_4 ( + .I0(com_tlm_u_tlm_rx_fc_use_data[4]), + .I1(com_tlm_u_tlm_rx_fc_use_p), + .I2(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_d_con[4]), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un1_fc_d_con_1_axb_4_4642) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un1_fc_d_con_1_axb_3.INIT = 8'h78; + LUT3_L com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un1_fc_d_con_1_axb_3 ( + .I0(com_tlm_u_tlm_rx_fc_use_data[3]), + .I1(com_tlm_u_tlm_rx_fc_use_p), + .I2(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_d_con[3]), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un1_fc_d_con_1_axb_3_4643) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un1_fc_d_con_1_axb_2.INIT = 8'h78; + LUT3_L com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un1_fc_d_con_1_axb_2 ( + .I0(com_tlm_u_tlm_rx_fc_use_data[2]), + .I1(com_tlm_u_tlm_rx_fc_use_p), + .I2(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_d_con[2]), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un1_fc_d_con_1_axb_2_4644) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un1_fc_d_con_1_axb_1.INIT = 8'h78; + LUT3_L com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un1_fc_d_con_1_axb_1 ( + .I0(com_tlm_u_tlm_rx_fc_use_data[1]), + .I1(com_tlm_u_tlm_rx_fc_use_p), + .I2(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_d_con[1]), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_un1_fc_d_con_1_axb_1_4645) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_N_87149_i.INIT = 8'hF4; + LUT3_L com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_N_87149_i ( + .I0(com_tlm_u_tlm_rx_fc_sched_p), + .I1(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_send_state_2__4649), + .I2(com_tlm_u_tlm_rx_fc_send_state_0_sqmuxa), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_N_87149_i_4646) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_N_87150_i.INIT = 16'h7530; + LUT4_L com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_N_87150_i ( + .I0(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_N_57046_i), + .I1(com_tlm_u_tlm_rx_fc_req_p_dst_rdy), + .I2(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_req_p_src_rdy), + .I3(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_send_state_0__4650), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_N_87150_i_4647) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_N_87151_i.INIT = 16'hECA0; + LUT4_L com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_N_87151_i ( + .I0(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_N_57046_i), + .I1(com_tlm_u_tlm_rx_fc_sched_p), + .I2(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_send_state_0__4650), + .I3(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_send_state_2__4649), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_N_87151_i_4648) + ); + FD com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_d_advert_11_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_d_advert_1[11]), + .Q(com_tlm_u_tlm_rx_vc0_flow_ctrl_fc_d_advert_0[11]) + ); + FD com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_h_advert_7_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_h_advert_1[7]), + .Q(com_tlm_u_tlm_rx_vc0_flow_ctrl_fc_h_advert_0[7]) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_h_con_qxu_0_0_.INIT = 4'h2; + LUT1_L com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_h_con_qxu_0_0_ ( + .I0(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_h_con[0]), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_h_con_qxu[0]) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_h_con_qxu_0_7_.INIT = 4'h2; + LUT1_L com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_h_con_qxu_0_7_ ( + .I0(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_h_con[7]), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_h_con_qxu[7]) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_h_con_qxu_0_6_.INIT = 4'h2; + LUT1_L com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_h_con_qxu_0_6_ ( + .I0(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_h_con[6]), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_h_con_qxu[6]) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_h_con_qxu_0_5_.INIT = 4'h2; + LUT1_L com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_h_con_qxu_0_5_ ( + .I0(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_h_con[5]), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_h_con_qxu[5]) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_h_con_qxu_0_4_.INIT = 4'h2; + LUT1_L com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_h_con_qxu_0_4_ ( + .I0(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_h_con[4]), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_h_con_qxu[4]) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_h_con_qxu_0_3_.INIT = 4'h2; + LUT1_L com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_h_con_qxu_0_3_ ( + .I0(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_h_con[3]), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_h_con_qxu[3]) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_h_con_qxu_0_2_.INIT = 4'h2; + LUT1_L com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_h_con_qxu_0_2_ ( + .I0(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_h_con[2]), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_h_con_qxu[2]) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_h_con_qxu_0_1_.INIT = 4'h2; + LUT1_L com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_h_con_qxu_0_1_ ( + .I0(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_h_con[1]), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_h_con_qxu[1]) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_h_con_s_0_.INIT = 4'h1; + LUT1_L com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_h_con_s_0_ ( + .I0(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_h_con_qxu[0]), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_h_con_s[0]) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_d_advert_1_axb_10.INIT = 4'h9; + LUT2 com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_d_advert_1_axb_10 ( + .I0(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_d_alo[10]), + .I1(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_d_con[10]), + .O(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_d_advert_1_axb_10_4651) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_d_advert_1_axb_9.INIT = 4'h9; + LUT2 com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_d_advert_1_axb_9 ( + .I0(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_d_alo[9]), + .I1(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_d_con[9]), + .O(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_d_advert_1_axb_9_4652) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_d_advert_1_axb_8.INIT = 4'h9; + LUT2 com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_d_advert_1_axb_8 ( + .I0(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_d_alo[8]), + .I1(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_d_con[8]), + .O(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_d_advert_1_axb_8_4653) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_d_advert_1_axb_7.INIT = 4'h9; + LUT2 com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_d_advert_1_axb_7 ( + .I0(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_d_alo[7]), + .I1(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_d_con[7]), + .O(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_d_advert_1_axb_7_4654) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_d_advert_1_axb_6.INIT = 4'h9; + LUT2 com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_d_advert_1_axb_6 ( + .I0(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_d_alo[6]), + .I1(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_d_con[6]), + .O(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_d_advert_1_axb_6_4655) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_d_advert_1_axb_5.INIT = 4'h9; + LUT2 com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_d_advert_1_axb_5 ( + .I0(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_d_alo[5]), + .I1(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_d_con[5]), + .O(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_d_advert_1_axb_5_4656) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_d_advert_1_axb_4.INIT = 4'h9; + LUT2 com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_d_advert_1_axb_4 ( + .I0(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_d_alo[4]), + .I1(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_d_con[4]), + .O(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_d_advert_1_axb_4_4657) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_d_advert_1_axb_3.INIT = 4'h9; + LUT2 com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_d_advert_1_axb_3 ( + .I0(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_d_alo[3]), + .I1(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_d_con[3]), + .O(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_d_advert_1_axb_3_4658) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_d_advert_1_axb_2.INIT = 4'h9; + LUT2 com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_d_advert_1_axb_2 ( + .I0(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_d_alo[2]), + .I1(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_d_con[2]), + .O(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_d_advert_1_axb_2_4659) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_d_advert_1_axb_1.INIT = 4'h9; + LUT2 com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_d_advert_1_axb_1 ( + .I0(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_d_alo[1]), + .I1(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_d_con[1]), + .O(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_d_advert_1_axb_1_4660) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_d_advert_1_axb_0.INIT = 4'h9; + LUT2 com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_d_advert_1_axb_0 ( + .I0(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_d_alo[0]), + .I1(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_d_con[0]), + .O(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_d_advert_1_axb_0_4661) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_h_advert_1_axb_6.INIT = 4'h9; + LUT2 com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_h_advert_1_axb_6 ( + .I0(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_h_alo[6]), + .I1(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_h_con[6]), + .O(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_h_advert_1_axb_6_4662) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_h_advert_1_axb_5.INIT = 4'h9; + LUT2 com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_h_advert_1_axb_5 ( + .I0(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_h_alo[5]), + .I1(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_h_con[5]), + .O(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_h_advert_1_axb_5_4663) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_h_advert_1_axb_4.INIT = 4'h9; + LUT2 com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_h_advert_1_axb_4 ( + .I0(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_h_alo[4]), + .I1(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_h_con[4]), + .O(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_h_advert_1_axb_4_4664) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_h_advert_1_axb_3.INIT = 4'h9; + LUT2 com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_h_advert_1_axb_3 ( + .I0(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_h_alo[3]), + .I1(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_h_con[3]), + .O(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_h_advert_1_axb_3_4665) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_h_advert_1_axb_2.INIT = 4'h9; + LUT2 com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_h_advert_1_axb_2 ( + .I0(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_h_alo[2]), + .I1(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_h_con[2]), + .O(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_h_advert_1_axb_2_4666) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_h_advert_1_axb_1.INIT = 4'h9; + LUT2 com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_h_advert_1_axb_1 ( + .I0(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_h_alo[1]), + .I1(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_h_con[1]), + .O(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_h_advert_1_axb_1_4667) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_h_advert_1_axb_0.INIT = 4'h9; + LUT2 com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_h_advert_1_axb_0 ( + .I0(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_h_alo[0]), + .I1(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_h_con[0]), + .O(com_tlm_u_tlm_rx_vc0_flow_ctrl_posted_fc_h_advert_1_axb_0_4668) + ); + VCC com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_VCC ( + .P(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_VCC_4756) + ); + GND com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_GND ( + .G(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_GND_4768) + ); + FDS com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_send_state_0_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_N_87154_i_4829), + .Q(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_send_state_0__4831), + .S(plm_link_up_i) + ); + FDR com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_send_state_1_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_N_87153_i_4828), + .Q(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_req_np_src_rdy), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_send_state_2_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_N_87152_i_4827), + .Q(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_send_state_2__4830), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_d_con_0_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un1_fc_d_con_1_axb_0_4769), + .Q(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_d_con[0]), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_d_con_1_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un1_fc_d_con_1_s_1_0), + .Q(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_d_con[1]), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_d_con_2_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un1_fc_d_con_1_s_2_0), + .Q(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_d_con[2]), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_d_con_3_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un1_fc_d_con_1_s_3_0), + .Q(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_d_con[3]), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_d_con_4_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un1_fc_d_con_1_s_4_0), + .Q(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_d_con[4]), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_d_con_5_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un1_fc_d_con_1_s_5_0), + .Q(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_d_con[5]), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_d_con_6_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un1_fc_d_con_1_s_6_0), + .Q(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_d_con[6]), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_d_con_7_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un1_fc_d_con_1_s_7_0), + .Q(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_d_con[7]), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_d_con_8_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un1_fc_d_con_1_s_8_0), + .Q(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_d_con[8]), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_d_con_9_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un1_fc_d_con_1_s_9_0), + .Q(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_d_con[9]), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_d_con_10_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un1_fc_d_con_1_s_10_0), + .Q(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_d_con[10]), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_d_con_11_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un1_fc_d_con_1_s_11_0), + .Q(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_d_con[11]), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_req_d_o_0_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_d_o_0[0]), + .Q(com_tlm_u_tlm_rx_fc_req_npd[0]), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_req_d_o_1_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_d_o_0[1]), + .Q(com_tlm_u_tlm_rx_fc_req_npd[1]), + .R(plm_link_up_i) + ); + FDS com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_req_d_o_2_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_d_o_0[2]), + .Q(com_tlm_u_tlm_rx_fc_req_npd[2]), + .S(plm_link_up_i) + ); + FDS com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_req_d_o_3_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_d_o_0[3]), + .Q(com_tlm_u_tlm_rx_fc_req_npd[3]), + .S(plm_link_up_i) + ); + FDR com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_req_d_o_4_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_d_o_0[4]), + .Q(com_tlm_u_tlm_rx_fc_req_npd[4]), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_req_d_o_5_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_d_o_0[5]), + .Q(com_tlm_u_tlm_rx_fc_req_npd[5]), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_req_d_o_6_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_d_o_0[6]), + .Q(com_tlm_u_tlm_rx_fc_req_npd[6]), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_req_d_o_7_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_d_o_0[7]), + .Q(com_tlm_u_tlm_rx_fc_req_npd[7]), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_req_d_o_8_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_d_o_0[8]), + .Q(com_tlm_u_tlm_rx_fc_req_npd[8]), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_req_d_o_9_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_d_o_0[9]), + .Q(com_tlm_u_tlm_rx_fc_req_npd[9]), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_req_d_o_10_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_d_o_0[10]), + .Q(com_tlm_u_tlm_rx_fc_req_npd[10]), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_req_d_o_11_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_d_o_0[11]), + .Q(com_tlm_u_tlm_rx_fc_req_npd[11]), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_h_av_o_0_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un35_fc_h_av_o_axb_0_i_4802), + .Q(trn_rfc_nph_av_6090[0]), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_h_av_o_1_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un35_fc_h_av_o_s_1_4735), + .Q(trn_rfc_nph_av_6090[1]), + .R(plm_link_up_i) + ); + FDS com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_h_av_o_2_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un35_fc_h_av_o_s_2_4737), + .Q(trn_rfc_nph_av_6090[2]), + .S(plm_link_up_i) + ); + FDS com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_h_av_o_3_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un35_fc_h_av_o_s_3_4739), + .Q(trn_rfc_nph_av_6090[3]), + .S(plm_link_up_i) + ); + FDR com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_h_av_o_4_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un35_fc_h_av_o_s_4_4741), + .Q(trn_rfc_nph_av_6090[4]), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_h_av_o_5_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un35_fc_h_av_o_s_5_4743), + .Q(trn_rfc_nph_av_6090[5]), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_h_av_o_6_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un35_fc_h_av_o_s_6_4745), + .Q(trn_rfc_nph_av_6090[6]), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_h_av_o_7_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un35_fc_h_av_o_s_7_4747), + .Q(trn_rfc_nph_av_6090[7]), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_d_av_o_0_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un36_fc_d_av_o_axb_0_i_4793), + .Q(trn_rfc_npd_av_6091[0]), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_d_av_o_1_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un36_fc_d_av_o_s_1_4696), + .Q(trn_rfc_npd_av_6091[1]), + .R(plm_link_up_i) + ); + FDS com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_d_av_o_2_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un36_fc_d_av_o_s_2_4698), + .Q(trn_rfc_npd_av_6091[2]), + .S(plm_link_up_i) + ); + FDS com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_d_av_o_3_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un36_fc_d_av_o_s_3_4700), + .Q(trn_rfc_npd_av_6091[3]), + .S(plm_link_up_i) + ); + FDR com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_d_av_o_4_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un36_fc_d_av_o_s_4_4702), + .Q(trn_rfc_npd_av_6091[4]), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_d_av_o_5_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un36_fc_d_av_o_s_5_4704), + .Q(trn_rfc_npd_av_6091[5]), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_d_av_o_6_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un36_fc_d_av_o_s_6_4706), + .Q(trn_rfc_npd_av_6091[6]), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_d_av_o_7_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un36_fc_d_av_o_s_7_4708), + .Q(trn_rfc_npd_av_6091[7]), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_d_av_o_8_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un36_fc_d_av_o_s_8_4710), + .Q(trn_rfc_npd_av_6091[8]), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_d_av_o_9_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un36_fc_d_av_o_s_9_4712), + .Q(trn_rfc_npd_av_6091[9]), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_d_av_o_10_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un36_fc_d_av_o_s_10_4714), + .Q(trn_rfc_npd_av_6091[10]), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_d_av_o_11_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un36_fc_d_av_o_s_11_4716), + .Q(trn_rfc_npd_av_6091[11]), + .R(plm_link_up_i) + ); + FDRE com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_h_alo_0_ ( + .CE(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_gnt), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_lnk_tfc_header[0]), + .Q(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_h_alo[0]), + .R(plm_link_up_i) + ); + FDRE com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_h_alo_1_ ( + .CE(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_gnt), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_lnk_tfc_header[1]), + .Q(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_h_alo[1]), + .R(plm_link_up_i) + ); + FDSE com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_h_alo_2_ ( + .CE(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_gnt), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_lnk_tfc_header[2]), + .Q(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_h_alo[2]), + .S(plm_link_up_i) + ); + FDSE com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_h_alo_3_ ( + .CE(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_gnt), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_lnk_tfc_header[3]), + .Q(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_h_alo[3]), + .S(plm_link_up_i) + ); + FDRE com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_h_alo_4_ ( + .CE(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_gnt), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_lnk_tfc_header[4]), + .Q(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_h_alo[4]), + .R(plm_link_up_i) + ); + FDRE com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_h_alo_5_ ( + .CE(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_gnt), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_lnk_tfc_header[5]), + .Q(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_h_alo[5]), + .R(plm_link_up_i) + ); + FDRE com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_h_alo_6_ ( + .CE(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_gnt), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_lnk_tfc_header[6]), + .Q(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_h_alo[6]), + .R(plm_link_up_i) + ); + FDRE com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_h_alo_7_ ( + .CE(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_gnt), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_lnk_tfc_header[7]), + .Q(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_h_alo[7]), + .R(plm_link_up_i) + ); + FDRE com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_d_alo_0_ ( + .CE(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_gnt), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_lnk_tfc_data[0]), + .Q(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_d_alo[0]), + .R(plm_link_up_i) + ); + FDRE com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_d_alo_1_ ( + .CE(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_gnt), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_lnk_tfc_data[1]), + .Q(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_d_alo[1]), + .R(plm_link_up_i) + ); + FDSE com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_d_alo_2_ ( + .CE(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_gnt), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_lnk_tfc_data[2]), + .Q(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_d_alo[2]), + .S(plm_link_up_i) + ); + FDSE com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_d_alo_3_ ( + .CE(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_gnt), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_lnk_tfc_data[3]), + .Q(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_d_alo[3]), + .S(plm_link_up_i) + ); + FDRE com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_d_alo_4_ ( + .CE(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_gnt), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_lnk_tfc_data[4]), + .Q(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_d_alo[4]), + .R(plm_link_up_i) + ); + FDRE com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_d_alo_5_ ( + .CE(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_gnt), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_lnk_tfc_data[5]), + .Q(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_d_alo[5]), + .R(plm_link_up_i) + ); + FDRE com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_d_alo_6_ ( + .CE(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_gnt), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_lnk_tfc_data[6]), + .Q(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_d_alo[6]), + .R(plm_link_up_i) + ); + FDRE com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_d_alo_7_ ( + .CE(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_gnt), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_lnk_tfc_data[7]), + .Q(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_d_alo[7]), + .R(plm_link_up_i) + ); + FDRE com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_d_alo_8_ ( + .CE(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_gnt), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_lnk_tfc_data[8]), + .Q(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_d_alo[8]), + .R(plm_link_up_i) + ); + FDRE com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_d_alo_9_ ( + .CE(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_gnt), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_lnk_tfc_data[9]), + .Q(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_d_alo[9]), + .R(plm_link_up_i) + ); + FDRE com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_d_alo_10_ ( + .CE(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_gnt), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_lnk_tfc_data[10]), + .Q(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_d_alo[10]), + .R(plm_link_up_i) + ); + FDRE com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_d_alo_11_ ( + .CE(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_gnt), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_lnk_tfc_data[11]), + .Q(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_d_alo[11]), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_free_q2 ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_free_q_4669), + .Q(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_free_q2_4770), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_req_h_o_0_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_h_o_0[0]), + .Q(com_tlm_u_tlm_rx_fc_req_nph[0]), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_req_h_o_1_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_h_o_0[1]), + .Q(com_tlm_u_tlm_rx_fc_req_nph[1]), + .R(plm_link_up_i) + ); + FDS com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_req_h_o_2_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_h_o_0[2]), + .Q(com_tlm_u_tlm_rx_fc_req_nph[2]), + .S(plm_link_up_i) + ); + FDS com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_req_h_o_3_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_h_o_0[3]), + .Q(com_tlm_u_tlm_rx_fc_req_nph[3]), + .S(plm_link_up_i) + ); + FDR com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_req_h_o_4_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_h_o_0[4]), + .Q(com_tlm_u_tlm_rx_fc_req_nph[4]), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_req_h_o_5_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_h_o_0[5]), + .Q(com_tlm_u_tlm_rx_fc_req_nph[5]), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_req_h_o_6_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_h_o_0[6]), + .Q(com_tlm_u_tlm_rx_fc_req_nph[6]), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_req_h_o_7_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_h_o_0[7]), + .Q(com_tlm_u_tlm_rx_fc_req_nph[7]), + .R(plm_link_up_i) + ); + FDRSE com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_free_hold ( + .CE(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_send_state_0__4831), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_GND_4768), + .Q(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_free_hold_4771), + .R(plm_link_up_i), + .S(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_free_hold34) + ); + FDR com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_free_q ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_free_q_8), + .Q(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_free_q_4669), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_free_h ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_free_h_8), + .Q(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_free_h_4670), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_free_d ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_free_d_8), + .Q(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_free_d_4679), + .R(plm_link_up_i) + ); + MUXCY_L com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_h_o_cry_0 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_free_h_4670), + .DI(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_N_56077_i), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_h_o_cry_0_4671), + .S(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_h_o_axb_0_4781) + ); + XORCY com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_h_o_s_0 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_free_h_4670), + .LI(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_h_o_axb_0_4781), + .O(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_h_o_0[0]) + ); + MUXCY_L com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_h_o_cry_1 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_h_o_cry_0_4671), + .DI(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_GND_4768), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_h_o_cry_1_4672), + .S(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_h_o_axb_1_4780) + ); + XORCY com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_h_o_s_1 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_h_o_cry_0_4671), + .LI(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_h_o_axb_1_4780), + .O(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_h_o_0[1]) + ); + MUXCY_L com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_h_o_cry_2 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_h_o_cry_1_4672), + .DI(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_GND_4768), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_h_o_cry_2_4673), + .S(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_h_o_axb_2_4779) + ); + XORCY com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_h_o_s_2 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_h_o_cry_1_4672), + .LI(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_h_o_axb_2_4779), + .O(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_h_o_0[2]) + ); + MUXCY_L com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_h_o_cry_3 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_h_o_cry_2_4673), + .DI(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_GND_4768), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_h_o_cry_3_4674), + .S(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_h_o_axb_3_4778) + ); + XORCY com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_h_o_s_3 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_h_o_cry_2_4673), + .LI(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_h_o_axb_3_4778), + .O(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_h_o_0[3]) + ); + MUXCY_L com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_h_o_cry_4 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_h_o_cry_3_4674), + .DI(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_GND_4768), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_h_o_cry_4_4675), + .S(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_h_o_axb_4_4777) + ); + XORCY com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_h_o_s_4 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_h_o_cry_3_4674), + .LI(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_h_o_axb_4_4777), + .O(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_h_o_0[4]) + ); + MUXCY_L com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_h_o_cry_5 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_h_o_cry_4_4675), + .DI(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_GND_4768), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_h_o_cry_5_4676), + .S(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_h_o_axb_5_4776) + ); + XORCY com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_h_o_s_5 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_h_o_cry_4_4675), + .LI(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_h_o_axb_5_4776), + .O(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_h_o_0[5]) + ); + MUXCY_L com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_h_o_cry_6 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_h_o_cry_5_4676), + .DI(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_GND_4768), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_h_o_cry_6_4677), + .S(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_h_o_axb_6_4775) + ); + XORCY com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_h_o_s_6 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_h_o_cry_5_4676), + .LI(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_h_o_axb_6_4775), + .O(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_h_o_0[6]) + ); + XORCY com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_h_o_s_7 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_h_o_cry_6_4677), + .LI(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_h_o_axb_7_4774), + .O(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_h_o_0[7]) + ); + MULT_AND com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_d_o_cry_0 ( + .I0(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_N_56077_i), + .I1(com_tlm_u_tlm_rx_fc_use_data[0]), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_d_o_cry_0_0_4678) + ); + MUXCY_L com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_d_o_cry_0_0 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_free_d_4679), + .DI(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_d_o_cry_0_0_4678), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_d_o_cry_0_4681), + .S(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_d_o_axb_0_4815) + ); + XORCY com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_d_o_s_0 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_free_d_4679), + .LI(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_d_o_axb_0_4815), + .O(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_d_o_0[0]) + ); + MULT_AND com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_d_o_cry_1 ( + .I0(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_N_56077_i), + .I1(com_tlm_u_tlm_rx_fc_use_data[1]), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_d_o_cry_1_0_4680) + ); + MUXCY_L com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_d_o_cry_1_0 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_d_o_cry_0_4681), + .DI(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_d_o_cry_1_0_4680), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_d_o_cry_1_4683), + .S(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_d_o_axb_1_4814) + ); + XORCY com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_d_o_s_1 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_d_o_cry_0_4681), + .LI(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_d_o_axb_1_4814), + .O(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_d_o_0[1]) + ); + MULT_AND com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_d_o_cry_2 ( + .I0(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_N_56077_i), + .I1(com_tlm_u_tlm_rx_fc_use_data[2]), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_d_o_cry_2_0_4682) + ); + MUXCY_L com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_d_o_cry_2_0 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_d_o_cry_1_4683), + .DI(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_d_o_cry_2_0_4682), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_d_o_cry_2_4685), + .S(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_d_o_axb_2_4813) + ); + XORCY com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_d_o_s_2 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_d_o_cry_1_4683), + .LI(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_d_o_axb_2_4813), + .O(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_d_o_0[2]) + ); + MULT_AND com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_d_o_cry_3 ( + .I0(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_N_56077_i), + .I1(com_tlm_u_tlm_rx_fc_use_data[3]), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_d_o_cry_3_0_4684) + ); + MUXCY_L com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_d_o_cry_3_0 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_d_o_cry_2_4685), + .DI(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_d_o_cry_3_0_4684), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_d_o_cry_3_4687), + .S(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_d_o_axb_3_4812) + ); + XORCY com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_d_o_s_3 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_d_o_cry_2_4685), + .LI(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_d_o_axb_3_4812), + .O(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_d_o_0[3]) + ); + MULT_AND com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_d_o_cry_4 ( + .I0(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_N_56077_i), + .I1(com_tlm_u_tlm_rx_fc_use_data[4]), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_d_o_cry_4_0_4686) + ); + MUXCY_L com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_d_o_cry_4_0 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_d_o_cry_3_4687), + .DI(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_d_o_cry_4_0_4686), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_d_o_cry_4_4689), + .S(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_d_o_axb_4_4811) + ); + XORCY com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_d_o_s_4 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_d_o_cry_3_4687), + .LI(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_d_o_axb_4_4811), + .O(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_d_o_0[4]) + ); + MULT_AND com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_d_o_cry_5 ( + .I0(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_N_56077_i), + .I1(com_tlm_u_tlm_rx_fc_use_data[5]), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_d_o_cry_5_0_4688) + ); + MUXCY_L com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_d_o_cry_5_0 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_d_o_cry_4_4689), + .DI(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_d_o_cry_5_0_4688), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_d_o_cry_5_4690), + .S(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_d_o_axb_5_4810) + ); + XORCY com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_d_o_s_5 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_d_o_cry_4_4689), + .LI(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_d_o_axb_5_4810), + .O(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_d_o_0[5]) + ); + MUXCY_L com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_d_o_cry_6 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_d_o_cry_5_4690), + .DI(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_GND_4768), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_d_o_cry_6_4691), + .S(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_d_o_axb_6_4809) + ); + XORCY com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_d_o_s_6 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_d_o_cry_5_4690), + .LI(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_d_o_axb_6_4809), + .O(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_d_o_0[6]) + ); + MUXCY_L com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_d_o_cry_7 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_d_o_cry_6_4691), + .DI(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_GND_4768), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_d_o_cry_7_4692), + .S(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_d_o_axb_7_4808) + ); + XORCY com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_d_o_s_7 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_d_o_cry_6_4691), + .LI(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_d_o_axb_7_4808), + .O(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_d_o_0[7]) + ); + MUXCY_L com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_d_o_cry_8 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_d_o_cry_7_4692), + .DI(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_GND_4768), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_d_o_cry_8_4693), + .S(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_d_o_axb_8_4807) + ); + XORCY com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_d_o_s_8 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_d_o_cry_7_4692), + .LI(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_d_o_axb_8_4807), + .O(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_d_o_0[8]) + ); + MUXCY_L com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_d_o_cry_9 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_d_o_cry_8_4693), + .DI(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_GND_4768), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_d_o_cry_9_4694), + .S(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_d_o_axb_9_4806) + ); + XORCY com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_d_o_s_9 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_d_o_cry_8_4693), + .LI(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_d_o_axb_9_4806), + .O(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_d_o_0[9]) + ); + MUXCY_L com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_d_o_cry_10 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_d_o_cry_9_4694), + .DI(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_GND_4768), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_d_o_cry_10_4695), + .S(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_d_o_axb_10_4805) + ); + XORCY com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_d_o_s_10 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_d_o_cry_9_4694), + .LI(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_d_o_axb_10_4805), + .O(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_d_o_0[10]) + ); + XORCY com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_d_o_s_11 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_d_o_cry_10_4695), + .LI(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_d_o_axb_11_4804), + .O(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_d_o_0[11]) + ); + MUXCY_L com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un36_fc_d_av_o_cry_0 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_VCC_4756), + .DI(com_tlm_u_tlm_rx_fc_req_npd[0]), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un36_fc_d_av_o_cry_0_4697), + .S(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un36_fc_d_av_o_axb_0_4794) + ); + MUXCY_L com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un36_fc_d_av_o_cry_1 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un36_fc_d_av_o_cry_0_4697), + .DI(com_tlm_u_tlm_rx_fc_req_npd[1]), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un36_fc_d_av_o_cry_1_4699), + .S(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un36_fc_d_av_o_axb_1_4792) + ); + XORCY com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un36_fc_d_av_o_s_1 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un36_fc_d_av_o_cry_0_4697), + .LI(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un36_fc_d_av_o_axb_1_4792), + .O(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un36_fc_d_av_o_s_1_4696) + ); + MUXCY_L com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un36_fc_d_av_o_cry_2 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un36_fc_d_av_o_cry_1_4699), + .DI(com_tlm_u_tlm_rx_fc_req_npd[2]), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un36_fc_d_av_o_cry_2_4701), + .S(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un36_fc_d_av_o_axb_2_4791) + ); + XORCY com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un36_fc_d_av_o_s_2 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un36_fc_d_av_o_cry_1_4699), + .LI(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un36_fc_d_av_o_axb_2_4791), + .O(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un36_fc_d_av_o_s_2_4698) + ); + MUXCY_L com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un36_fc_d_av_o_cry_3 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un36_fc_d_av_o_cry_2_4701), + .DI(com_tlm_u_tlm_rx_fc_req_npd[3]), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un36_fc_d_av_o_cry_3_4703), + .S(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un36_fc_d_av_o_axb_3_4790) + ); + XORCY com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un36_fc_d_av_o_s_3 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un36_fc_d_av_o_cry_2_4701), + .LI(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un36_fc_d_av_o_axb_3_4790), + .O(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un36_fc_d_av_o_s_3_4700) + ); + MUXCY_L com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un36_fc_d_av_o_cry_4 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un36_fc_d_av_o_cry_3_4703), + .DI(com_tlm_u_tlm_rx_fc_req_npd[4]), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un36_fc_d_av_o_cry_4_4705), + .S(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un36_fc_d_av_o_axb_4_4789) + ); + XORCY com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un36_fc_d_av_o_s_4 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un36_fc_d_av_o_cry_3_4703), + .LI(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un36_fc_d_av_o_axb_4_4789), + .O(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un36_fc_d_av_o_s_4_4702) + ); + MUXCY_L com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un36_fc_d_av_o_cry_5 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un36_fc_d_av_o_cry_4_4705), + .DI(com_tlm_u_tlm_rx_fc_req_npd[5]), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un36_fc_d_av_o_cry_5_4707), + .S(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un36_fc_d_av_o_axb_5_4788) + ); + XORCY com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un36_fc_d_av_o_s_5 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un36_fc_d_av_o_cry_4_4705), + .LI(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un36_fc_d_av_o_axb_5_4788), + .O(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un36_fc_d_av_o_s_5_4704) + ); + MUXCY_L com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un36_fc_d_av_o_cry_6 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un36_fc_d_av_o_cry_5_4707), + .DI(com_tlm_u_tlm_rx_fc_req_npd[6]), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un36_fc_d_av_o_cry_6_4709), + .S(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un36_fc_d_av_o_axb_6_4787) + ); + XORCY com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un36_fc_d_av_o_s_6 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un36_fc_d_av_o_cry_5_4707), + .LI(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un36_fc_d_av_o_axb_6_4787), + .O(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un36_fc_d_av_o_s_6_4706) + ); + MUXCY_L com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un36_fc_d_av_o_cry_7 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un36_fc_d_av_o_cry_6_4709), + .DI(com_tlm_u_tlm_rx_fc_req_npd[7]), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un36_fc_d_av_o_cry_7_4711), + .S(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un36_fc_d_av_o_axb_7_4786) + ); + XORCY com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un36_fc_d_av_o_s_7 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un36_fc_d_av_o_cry_6_4709), + .LI(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un36_fc_d_av_o_axb_7_4786), + .O(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un36_fc_d_av_o_s_7_4708) + ); + MUXCY_L com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un36_fc_d_av_o_cry_8 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un36_fc_d_av_o_cry_7_4711), + .DI(com_tlm_u_tlm_rx_fc_req_npd[8]), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un36_fc_d_av_o_cry_8_4713), + .S(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un36_fc_d_av_o_axb_8_4785) + ); + XORCY com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un36_fc_d_av_o_s_8 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un36_fc_d_av_o_cry_7_4711), + .LI(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un36_fc_d_av_o_axb_8_4785), + .O(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un36_fc_d_av_o_s_8_4710) + ); + MUXCY_L com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un36_fc_d_av_o_cry_9 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un36_fc_d_av_o_cry_8_4713), + .DI(com_tlm_u_tlm_rx_fc_req_npd[9]), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un36_fc_d_av_o_cry_9_4715), + .S(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un36_fc_d_av_o_axb_9_4784) + ); + XORCY com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un36_fc_d_av_o_s_9 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un36_fc_d_av_o_cry_8_4713), + .LI(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un36_fc_d_av_o_axb_9_4784), + .O(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un36_fc_d_av_o_s_9_4712) + ); + MUXCY_L com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un36_fc_d_av_o_cry_10 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un36_fc_d_av_o_cry_9_4715), + .DI(com_tlm_u_tlm_rx_fc_req_npd[10]), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un36_fc_d_av_o_cry_10_4717), + .S(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un36_fc_d_av_o_axb_10_4783) + ); + XORCY com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un36_fc_d_av_o_s_10 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un36_fc_d_av_o_cry_9_4715), + .LI(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un36_fc_d_av_o_axb_10_4783), + .O(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un36_fc_d_av_o_s_10_4714) + ); + XORCY com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un36_fc_d_av_o_s_11 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un36_fc_d_av_o_cry_10_4717), + .LI(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un36_fc_d_av_o_axb_11_4782), + .O(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un36_fc_d_av_o_s_11_4716) + ); + MULT_AND com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un1_fc_d_con_1_cry_0 ( + .I0(com_tlm_u_tlm_rx_fc_use_np), + .I1(com_tlm_u_tlm_rx_fc_use_data[0]), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un1_fc_d_con_1_cry_0_0_4718) + ); + MUXCY_L com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un1_fc_d_con_1_cry_0_0 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_GND_4768), + .DI(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un1_fc_d_con_1_cry_0_0_4718), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un1_fc_d_con_1_cry_0_4720), + .S(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un1_fc_d_con_1_axb_0_4769) + ); + MULT_AND com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un1_fc_d_con_1_cry_1 ( + .I0(com_tlm_u_tlm_rx_fc_use_np), + .I1(com_tlm_u_tlm_rx_fc_use_data[1]), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un1_fc_d_con_1_cry_1_0_4719) + ); + MUXCY_L com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un1_fc_d_con_1_cry_1_0 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un1_fc_d_con_1_cry_0_4720), + .DI(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un1_fc_d_con_1_cry_1_0_4719), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un1_fc_d_con_1_cry_1_4722), + .S(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un1_fc_d_con_1_axb_1_4826) + ); + XORCY com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un1_fc_d_con_1_s_1 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un1_fc_d_con_1_cry_0_4720), + .LI(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un1_fc_d_con_1_axb_1_4826), + .O(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un1_fc_d_con_1_s_1_0) + ); + MULT_AND com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un1_fc_d_con_1_cry_2 ( + .I0(com_tlm_u_tlm_rx_fc_use_np), + .I1(com_tlm_u_tlm_rx_fc_use_data[2]), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un1_fc_d_con_1_cry_2_0_4721) + ); + MUXCY_L com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un1_fc_d_con_1_cry_2_0 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un1_fc_d_con_1_cry_1_4722), + .DI(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un1_fc_d_con_1_cry_2_0_4721), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un1_fc_d_con_1_cry_2_4724), + .S(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un1_fc_d_con_1_axb_2_4825) + ); + XORCY com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un1_fc_d_con_1_s_2 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un1_fc_d_con_1_cry_1_4722), + .LI(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un1_fc_d_con_1_axb_2_4825), + .O(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un1_fc_d_con_1_s_2_0) + ); + MULT_AND com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un1_fc_d_con_1_cry_3 ( + .I0(com_tlm_u_tlm_rx_fc_use_np), + .I1(com_tlm_u_tlm_rx_fc_use_data[3]), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un1_fc_d_con_1_cry_3_0_4723) + ); + MUXCY_L com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un1_fc_d_con_1_cry_3_0 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un1_fc_d_con_1_cry_2_4724), + .DI(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un1_fc_d_con_1_cry_3_0_4723), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un1_fc_d_con_1_cry_3_4726), + .S(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un1_fc_d_con_1_axb_3_4824) + ); + XORCY com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un1_fc_d_con_1_s_3 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un1_fc_d_con_1_cry_2_4724), + .LI(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un1_fc_d_con_1_axb_3_4824), + .O(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un1_fc_d_con_1_s_3_0) + ); + MULT_AND com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un1_fc_d_con_1_cry_4 ( + .I0(com_tlm_u_tlm_rx_fc_use_np), + .I1(com_tlm_u_tlm_rx_fc_use_data[4]), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un1_fc_d_con_1_cry_4_0_4725) + ); + MUXCY_L com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un1_fc_d_con_1_cry_4_0 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un1_fc_d_con_1_cry_3_4726), + .DI(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un1_fc_d_con_1_cry_4_0_4725), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un1_fc_d_con_1_cry_4_4728), + .S(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un1_fc_d_con_1_axb_4_4823) + ); + XORCY com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un1_fc_d_con_1_s_4 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un1_fc_d_con_1_cry_3_4726), + .LI(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un1_fc_d_con_1_axb_4_4823), + .O(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un1_fc_d_con_1_s_4_0) + ); + MULT_AND com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un1_fc_d_con_1_cry_5 ( + .I0(com_tlm_u_tlm_rx_fc_use_np), + .I1(com_tlm_u_tlm_rx_fc_use_data[5]), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un1_fc_d_con_1_cry_5_0_4727) + ); + MUXCY_L com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un1_fc_d_con_1_cry_5_0 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un1_fc_d_con_1_cry_4_4728), + .DI(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un1_fc_d_con_1_cry_5_0_4727), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un1_fc_d_con_1_cry_5_4729), + .S(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un1_fc_d_con_1_axb_5_4822) + ); + XORCY com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un1_fc_d_con_1_s_5 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un1_fc_d_con_1_cry_4_4728), + .LI(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un1_fc_d_con_1_axb_5_4822), + .O(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un1_fc_d_con_1_s_5_0) + ); + MUXCY_L com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un1_fc_d_con_1_cry_6 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un1_fc_d_con_1_cry_5_4729), + .DI(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_GND_4768), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un1_fc_d_con_1_cry_6_4730), + .S(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un1_fc_d_con_1_axb_6_4821) + ); + XORCY com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un1_fc_d_con_1_s_6 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un1_fc_d_con_1_cry_5_4729), + .LI(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un1_fc_d_con_1_axb_6_4821), + .O(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un1_fc_d_con_1_s_6_0) + ); + MUXCY_L com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un1_fc_d_con_1_cry_7 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un1_fc_d_con_1_cry_6_4730), + .DI(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_GND_4768), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un1_fc_d_con_1_cry_7_4731), + .S(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un1_fc_d_con_1_axb_7_4820) + ); + XORCY com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un1_fc_d_con_1_s_7 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un1_fc_d_con_1_cry_6_4730), + .LI(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un1_fc_d_con_1_axb_7_4820), + .O(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un1_fc_d_con_1_s_7_0) + ); + MUXCY_L com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un1_fc_d_con_1_cry_8 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un1_fc_d_con_1_cry_7_4731), + .DI(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_GND_4768), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un1_fc_d_con_1_cry_8_4732), + .S(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un1_fc_d_con_1_axb_8_4819) + ); + XORCY com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un1_fc_d_con_1_s_8 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un1_fc_d_con_1_cry_7_4731), + .LI(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un1_fc_d_con_1_axb_8_4819), + .O(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un1_fc_d_con_1_s_8_0) + ); + MUXCY_L com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un1_fc_d_con_1_cry_9 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un1_fc_d_con_1_cry_8_4732), + .DI(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_GND_4768), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un1_fc_d_con_1_cry_9_4733), + .S(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un1_fc_d_con_1_axb_9_4818) + ); + XORCY com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un1_fc_d_con_1_s_9 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un1_fc_d_con_1_cry_8_4732), + .LI(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un1_fc_d_con_1_axb_9_4818), + .O(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un1_fc_d_con_1_s_9_0) + ); + MUXCY_L com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un1_fc_d_con_1_cry_10 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un1_fc_d_con_1_cry_9_4733), + .DI(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_GND_4768), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un1_fc_d_con_1_cry_10_4734), + .S(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un1_fc_d_con_1_axb_10_4817) + ); + XORCY com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un1_fc_d_con_1_s_10 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un1_fc_d_con_1_cry_9_4733), + .LI(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un1_fc_d_con_1_axb_10_4817), + .O(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un1_fc_d_con_1_s_10_0) + ); + XORCY com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un1_fc_d_con_1_s_11 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un1_fc_d_con_1_cry_10_4734), + .LI(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un1_fc_d_con_1_axb_11_4816), + .O(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un1_fc_d_con_1_s_11_0) + ); + MUXCY_L com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un35_fc_h_av_o_cry_0 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_VCC_4756), + .DI(com_tlm_u_tlm_rx_fc_req_nph[0]), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un35_fc_h_av_o_cry_0_4736), + .S(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un35_fc_h_av_o_axb_0_4803) + ); + MUXCY_L com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un35_fc_h_av_o_cry_1 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un35_fc_h_av_o_cry_0_4736), + .DI(com_tlm_u_tlm_rx_fc_req_nph[1]), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un35_fc_h_av_o_cry_1_4738), + .S(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un35_fc_h_av_o_axb_1_4801) + ); + XORCY com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un35_fc_h_av_o_s_1 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un35_fc_h_av_o_cry_0_4736), + .LI(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un35_fc_h_av_o_axb_1_4801), + .O(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un35_fc_h_av_o_s_1_4735) + ); + MUXCY_L com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un35_fc_h_av_o_cry_2 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un35_fc_h_av_o_cry_1_4738), + .DI(com_tlm_u_tlm_rx_fc_req_nph[2]), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un35_fc_h_av_o_cry_2_4740), + .S(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un35_fc_h_av_o_axb_2_4800) + ); + XORCY com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un35_fc_h_av_o_s_2 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un35_fc_h_av_o_cry_1_4738), + .LI(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un35_fc_h_av_o_axb_2_4800), + .O(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un35_fc_h_av_o_s_2_4737) + ); + MUXCY_L com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un35_fc_h_av_o_cry_3 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un35_fc_h_av_o_cry_2_4740), + .DI(com_tlm_u_tlm_rx_fc_req_nph[3]), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un35_fc_h_av_o_cry_3_4742), + .S(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un35_fc_h_av_o_axb_3_4799) + ); + XORCY com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un35_fc_h_av_o_s_3 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un35_fc_h_av_o_cry_2_4740), + .LI(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un35_fc_h_av_o_axb_3_4799), + .O(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un35_fc_h_av_o_s_3_4739) + ); + MUXCY_L com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un35_fc_h_av_o_cry_4 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un35_fc_h_av_o_cry_3_4742), + .DI(com_tlm_u_tlm_rx_fc_req_nph[4]), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un35_fc_h_av_o_cry_4_4744), + .S(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un35_fc_h_av_o_axb_4_4798) + ); + XORCY com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un35_fc_h_av_o_s_4 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un35_fc_h_av_o_cry_3_4742), + .LI(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un35_fc_h_av_o_axb_4_4798), + .O(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un35_fc_h_av_o_s_4_4741) + ); + MUXCY_L com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un35_fc_h_av_o_cry_5 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un35_fc_h_av_o_cry_4_4744), + .DI(com_tlm_u_tlm_rx_fc_req_nph[5]), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un35_fc_h_av_o_cry_5_4746), + .S(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un35_fc_h_av_o_axb_5_4797) + ); + XORCY com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un35_fc_h_av_o_s_5 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un35_fc_h_av_o_cry_4_4744), + .LI(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un35_fc_h_av_o_axb_5_4797), + .O(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un35_fc_h_av_o_s_5_4743) + ); + MUXCY_L com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un35_fc_h_av_o_cry_6 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un35_fc_h_av_o_cry_5_4746), + .DI(com_tlm_u_tlm_rx_fc_req_nph[6]), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un35_fc_h_av_o_cry_6_4748), + .S(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un35_fc_h_av_o_axb_6_4796) + ); + XORCY com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un35_fc_h_av_o_s_6 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un35_fc_h_av_o_cry_5_4746), + .LI(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un35_fc_h_av_o_axb_6_4796), + .O(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un35_fc_h_av_o_s_6_4745) + ); + XORCY com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un35_fc_h_av_o_s_7 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un35_fc_h_av_o_cry_6_4748), + .LI(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un35_fc_h_av_o_axb_7_4795), + .O(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un35_fc_h_av_o_s_7_4747) + ); + MUXCY_L com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un5_fc_h_advert_cry_0 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_VCC_4756), + .DI(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_h_alo[0]), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un5_fc_h_advert_cry_0_4749), + .S(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un5_fc_h_advert_axb_0_4851) + ); + MUXCY_L com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un5_fc_h_advert_cry_1 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un5_fc_h_advert_cry_0_4749), + .DI(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_h_alo[1]), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un5_fc_h_advert_cry_1_4750), + .S(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un5_fc_h_advert_axb_1_4850) + ); + MUXCY_L com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un5_fc_h_advert_cry_2 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un5_fc_h_advert_cry_1_4750), + .DI(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_h_alo[2]), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un5_fc_h_advert_cry_2_4751), + .S(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un5_fc_h_advert_axb_2_4849) + ); + MUXCY_L com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un5_fc_h_advert_cry_3 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un5_fc_h_advert_cry_2_4751), + .DI(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_h_alo[3]), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un5_fc_h_advert_cry_3_4752), + .S(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un5_fc_h_advert_axb_3_4848) + ); + MUXCY_L com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un5_fc_h_advert_cry_4 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un5_fc_h_advert_cry_3_4752), + .DI(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_h_alo[4]), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un5_fc_h_advert_cry_4_4753), + .S(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un5_fc_h_advert_axb_4_4847) + ); + MUXCY_L com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un5_fc_h_advert_cry_5 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un5_fc_h_advert_cry_4_4753), + .DI(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_h_alo[5]), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un5_fc_h_advert_cry_5_4754), + .S(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un5_fc_h_advert_axb_5_4846) + ); + MUXCY_L com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un5_fc_h_advert_cry_6 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un5_fc_h_advert_cry_5_4754), + .DI(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_h_alo[6]), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un5_fc_h_advert_cry_6_4755), + .S(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un5_fc_h_advert_axb_6_4845) + ); + XORCY com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un5_fc_h_advert_s_7 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un5_fc_h_advert_cry_6_4755), + .LI(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un5_fc_h_advert_axb_7_4773), + .O(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un5_fc_h_advert_s_7_4833) + ); + MUXCY_L com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un5_fc_d_advert_cry_0 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_VCC_4756), + .DI(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_d_alo[0]), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un5_fc_d_advert_cry_0_4757), + .S(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un5_fc_d_advert_axb_0_4844) + ); + MUXCY_L com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un5_fc_d_advert_cry_1 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un5_fc_d_advert_cry_0_4757), + .DI(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_d_alo[1]), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un5_fc_d_advert_cry_1_4758), + .S(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un5_fc_d_advert_axb_1_4843) + ); + MUXCY_L com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un5_fc_d_advert_cry_2 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un5_fc_d_advert_cry_1_4758), + .DI(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_d_alo[2]), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un5_fc_d_advert_cry_2_4759), + .S(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un5_fc_d_advert_axb_2_4842) + ); + MUXCY_L com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un5_fc_d_advert_cry_3 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un5_fc_d_advert_cry_2_4759), + .DI(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_d_alo[3]), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un5_fc_d_advert_cry_3_4760), + .S(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un5_fc_d_advert_axb_3_4841) + ); + MUXCY_L com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un5_fc_d_advert_cry_4 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un5_fc_d_advert_cry_3_4760), + .DI(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_d_alo[4]), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un5_fc_d_advert_cry_4_4761), + .S(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un5_fc_d_advert_axb_4_4840) + ); + MUXCY_L com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un5_fc_d_advert_cry_5 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un5_fc_d_advert_cry_4_4761), + .DI(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_d_alo[5]), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un5_fc_d_advert_cry_5_4762), + .S(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un5_fc_d_advert_axb_5_4839) + ); + MUXCY_L com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un5_fc_d_advert_cry_6 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un5_fc_d_advert_cry_5_4762), + .DI(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_d_alo[6]), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un5_fc_d_advert_cry_6_4763), + .S(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un5_fc_d_advert_axb_6_4838) + ); + MUXCY_L com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un5_fc_d_advert_cry_7 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un5_fc_d_advert_cry_6_4763), + .DI(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_d_alo[7]), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un5_fc_d_advert_cry_7_4764), + .S(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un5_fc_d_advert_axb_7_4837) + ); + MUXCY_L com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un5_fc_d_advert_cry_8 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un5_fc_d_advert_cry_7_4764), + .DI(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_d_alo[8]), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un5_fc_d_advert_cry_8_4765), + .S(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un5_fc_d_advert_axb_8_4836) + ); + MUXCY_L com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un5_fc_d_advert_cry_9 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un5_fc_d_advert_cry_8_4765), + .DI(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_d_alo[9]), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un5_fc_d_advert_cry_9_4766), + .S(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un5_fc_d_advert_axb_9_4835) + ); + MUXCY_L com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un5_fc_d_advert_cry_10 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un5_fc_d_advert_cry_9_4766), + .DI(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_d_alo[10]), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un5_fc_d_advert_cry_10_4767), + .S(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un5_fc_d_advert_axb_10_4834) + ); + XORCY com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un5_fc_d_advert_s_11 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un5_fc_d_advert_cry_10_4767), + .LI(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un5_fc_d_advert_axb_11_4772), + .O(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un5_fc_d_advert_s_11_4832) + ); + FDRE com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_h_con_0_ ( + .CE(com_tlm_u_tlm_rx_fc_use_np), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_h_con_s[0]), + .Q(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_h_con[0]), + .R(plm_link_up_i) + ); + MUXCY_L com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_h_con_cry_1_ ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_h_con[0]), + .DI(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_GND_4768), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_h_con_cry[1]), + .S(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_h_con_qxu[1]) + ); + XORCY com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_h_con_s_1_ ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_h_con[0]), + .LI(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_h_con_qxu[1]), + .O(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_h_con_s[1]) + ); + FDRE com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_h_con_1_ ( + .CE(com_tlm_u_tlm_rx_fc_use_np), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_h_con_s[1]), + .Q(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_h_con[1]), + .R(plm_link_up_i) + ); + MUXCY_L com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_h_con_cry_2_ ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_h_con_cry[1]), + .DI(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_GND_4768), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_h_con_cry[2]), + .S(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_h_con_qxu[2]) + ); + XORCY com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_h_con_s_2_ ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_h_con_cry[1]), + .LI(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_h_con_qxu[2]), + .O(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_h_con_s[2]) + ); + FDRE com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_h_con_2_ ( + .CE(com_tlm_u_tlm_rx_fc_use_np), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_h_con_s[2]), + .Q(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_h_con[2]), + .R(plm_link_up_i) + ); + MUXCY_L com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_h_con_cry_3_ ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_h_con_cry[2]), + .DI(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_GND_4768), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_h_con_cry[3]), + .S(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_h_con_qxu[3]) + ); + XORCY com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_h_con_s_3_ ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_h_con_cry[2]), + .LI(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_h_con_qxu[3]), + .O(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_h_con_s[3]) + ); + FDRE com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_h_con_3_ ( + .CE(com_tlm_u_tlm_rx_fc_use_np), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_h_con_s[3]), + .Q(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_h_con[3]), + .R(plm_link_up_i) + ); + MUXCY_L com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_h_con_cry_4_ ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_h_con_cry[3]), + .DI(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_GND_4768), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_h_con_cry[4]), + .S(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_h_con_qxu[4]) + ); + XORCY com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_h_con_s_4_ ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_h_con_cry[3]), + .LI(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_h_con_qxu[4]), + .O(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_h_con_s[4]) + ); + FDRE com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_h_con_4_ ( + .CE(com_tlm_u_tlm_rx_fc_use_np), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_h_con_s[4]), + .Q(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_h_con[4]), + .R(plm_link_up_i) + ); + MUXCY_L com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_h_con_cry_5_ ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_h_con_cry[4]), + .DI(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_GND_4768), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_h_con_cry[5]), + .S(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_h_con_qxu[5]) + ); + XORCY com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_h_con_s_5_ ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_h_con_cry[4]), + .LI(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_h_con_qxu[5]), + .O(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_h_con_s[5]) + ); + FDRE com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_h_con_5_ ( + .CE(com_tlm_u_tlm_rx_fc_use_np), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_h_con_s[5]), + .Q(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_h_con[5]), + .R(plm_link_up_i) + ); + MUXCY_L com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_h_con_cry_6_ ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_h_con_cry[5]), + .DI(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_GND_4768), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_h_con_cry[6]), + .S(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_h_con_qxu[6]) + ); + XORCY com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_h_con_s_6_ ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_h_con_cry[5]), + .LI(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_h_con_qxu[6]), + .O(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_h_con_s[6]) + ); + FDRE com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_h_con_6_ ( + .CE(com_tlm_u_tlm_rx_fc_use_np), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_h_con_s[6]), + .Q(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_h_con[6]), + .R(plm_link_up_i) + ); + XORCY com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_h_con_s_7_ ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_h_con_cry[6]), + .LI(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_h_con_qxu[7]), + .O(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_h_con_s[7]) + ); + FDRE com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_h_con_7_ ( + .CE(com_tlm_u_tlm_rx_fc_use_np), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_h_con_s[7]), + .Q(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_h_con[7]), + .R(plm_link_up_i) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_unuse_direct_N_44084_i_0_o3.INIT = 4'h8; + LUT2 com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_unuse_direct_N_44084_i_0_o3 ( + .I0(com_tlm_u_tlm_rx_fc_unuse), + .I1(com_tlm_u_tlm_rx_fc_use_np), + .O(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_N_56077_i) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_free_hold34_0_a2_0_a2_0_a2.INIT = 4'h2; + LUT2 com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_free_hold34_0_a2_0_a2_0_a2 ( + .I0(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_free_q2_4770), + .I1(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_send_state_0__4831), + .O(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_free_hold34) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_send_state_28_0_i_0_0_a2_2_.INIT = 4'h8; + LUT2 com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_send_state_28_0_i_0_0_a2_2_ ( + .I0(com_tlm_u_tlm_rx_fc_req_np_dst_rdy), + .I1(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_req_np_src_rdy), + .O(com_tlm_u_tlm_rx_fc_send_state_0_sqmuxa_0) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un36_fc_d_av_o_axb_0.INIT = 4'h9; + LUT2 com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un36_fc_d_av_o_axb_0 ( + .I0(com_tlm_u_tlm_rx_fc_req_npd[0]), + .I1(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_d_con[0]), + .O(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un36_fc_d_av_o_axb_0_4794) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un35_fc_h_av_o_axb_0.INIT = 4'h9; + LUT2 com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un35_fc_h_av_o_axb_0 ( + .I0(com_tlm_u_tlm_rx_fc_req_nph[0]), + .I1(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_h_con[0]), + .O(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un35_fc_h_av_o_axb_0_4803) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un1_fc_d_con_1_axb_0.INIT = 8'h78; + LUT3 com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un1_fc_d_con_1_axb_0 ( + .I0(com_tlm_u_tlm_rx_fc_use_data[0]), + .I1(com_tlm_u_tlm_rx_fc_use_np), + .I2(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_d_con[0]), + .O(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un1_fc_d_con_1_axb_0_4769) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_send_state_28_0_i_0_0_o3_1_.INIT = 16'h0001; + LUT4 com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_send_state_28_0_i_0_0_o3_1_ ( + .I0(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_N_56077_i), + .I1(com_tlm_u_tlm_rx_vc0_flow_ctrl_lat_timer[9]), + .I2(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_free_hold_4771), + .I3(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_free_q2_4770), + .O(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_N_57045_i) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_gnt_0_a2_0_a2_0_a2_0_a2_1.INIT = 16'h0200; + LUT4 com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_gnt_0_a2_0_a2_0_a2_0_a2_1 ( + .I0(com_un1_lnk_tfc_dst_rdy_i_0_o2_i_a2), + .I1(com_lnk_tfc_type[1]), + .I2(com_lnk_tfc_type[2]), + .I3(com_lnk_tfc_type[3]), + .O(com_tlm_u_tlm_rx_vc0_flow_ctrl_fc_gnt_3) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_gnt_0_a2_0_a2_0_a2_0_a2.INIT = 4'h8; + LUT2 com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_gnt_0_a2_0_a2_0_a2_0_a2 ( + .I0(com_lnk_tfc_type[0]), + .I1(com_tlm_u_tlm_rx_vc0_flow_ctrl_fc_gnt_3), + .O(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_gnt) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un5_fc_d_advert_axb_11.INIT = 4'h9; + LUT2_L com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un5_fc_d_advert_axb_11 ( + .I0(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_d_alo[11]), + .I1(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_d_con[11]), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un5_fc_d_advert_axb_11_4772) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un5_fc_h_advert_axb_7.INIT = 4'h9; + LUT2_L com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un5_fc_h_advert_axb_7 ( + .I0(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_h_alo[7]), + .I1(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_h_con[7]), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un5_fc_h_advert_axb_7_4773) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_free_d_8_0_a2.INIT = 4'h8; + LUT2_L com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_free_d_8_0_a2 ( + .I0(com_tlm_u_tlm_rx_vc0_fc_free_1data), + .I1(com_tlm_u_tlm_rx_vc0_fc_free_np), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_free_d_8) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_free_h_8_0_a2.INIT = 4'h8; + LUT2_L com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_free_h_8_0_a2 ( + .I0(com_tlm_u_tlm_rx_vc0_fc_free_1header), + .I1(com_tlm_u_tlm_rx_vc0_fc_free_np), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_free_h_8) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_free_q_8_0_a2.INIT = 4'h8; + LUT2_L com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_free_q_8_0_a2 ( + .I0(com_tlm_u_tlm_rx_vc0_fc_free_eof), + .I1(com_tlm_u_tlm_rx_vc0_fc_free_np), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_free_q_8) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_h_o_axb_7.INIT = 4'h2; + LUT1_L com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_h_o_axb_7 ( + .I0(com_tlm_u_tlm_rx_fc_req_nph[7]), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_h_o_axb_7_4774) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_h_o_axb_6.INIT = 4'h2; + LUT1_L com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_h_o_axb_6 ( + .I0(com_tlm_u_tlm_rx_fc_req_nph[6]), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_h_o_axb_6_4775) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_h_o_axb_5.INIT = 4'h2; + LUT1_L com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_h_o_axb_5 ( + .I0(com_tlm_u_tlm_rx_fc_req_nph[5]), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_h_o_axb_5_4776) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_h_o_axb_4.INIT = 4'h2; + LUT1_L com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_h_o_axb_4 ( + .I0(com_tlm_u_tlm_rx_fc_req_nph[4]), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_h_o_axb_4_4777) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_h_o_axb_3.INIT = 4'h2; + LUT1_L com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_h_o_axb_3 ( + .I0(com_tlm_u_tlm_rx_fc_req_nph[3]), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_h_o_axb_3_4778) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_h_o_axb_2.INIT = 4'h2; + LUT1_L com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_h_o_axb_2 ( + .I0(com_tlm_u_tlm_rx_fc_req_nph[2]), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_h_o_axb_2_4779) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_h_o_axb_1.INIT = 4'h2; + LUT1_L com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_h_o_axb_1 ( + .I0(com_tlm_u_tlm_rx_fc_req_nph[1]), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_h_o_axb_1_4780) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_h_o_axb_0.INIT = 4'h6; + LUT2_L com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_h_o_axb_0 ( + .I0(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_N_56077_i), + .I1(com_tlm_u_tlm_rx_fc_req_nph[0]), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_h_o_axb_0_4781) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un36_fc_d_av_o_axb_11.INIT = 4'h9; + LUT2_L com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un36_fc_d_av_o_axb_11 ( + .I0(com_tlm_u_tlm_rx_fc_req_npd[11]), + .I1(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_d_con[11]), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un36_fc_d_av_o_axb_11_4782) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un36_fc_d_av_o_axb_10.INIT = 4'h9; + LUT2_L com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un36_fc_d_av_o_axb_10 ( + .I0(com_tlm_u_tlm_rx_fc_req_npd[10]), + .I1(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_d_con[10]), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un36_fc_d_av_o_axb_10_4783) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un36_fc_d_av_o_axb_9.INIT = 4'h9; + LUT2_L com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un36_fc_d_av_o_axb_9 ( + .I0(com_tlm_u_tlm_rx_fc_req_npd[9]), + .I1(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_d_con[9]), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un36_fc_d_av_o_axb_9_4784) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un36_fc_d_av_o_axb_8.INIT = 4'h9; + LUT2_L com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un36_fc_d_av_o_axb_8 ( + .I0(com_tlm_u_tlm_rx_fc_req_npd[8]), + .I1(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_d_con[8]), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un36_fc_d_av_o_axb_8_4785) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un36_fc_d_av_o_axb_7.INIT = 4'h9; + LUT2_L com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un36_fc_d_av_o_axb_7 ( + .I0(com_tlm_u_tlm_rx_fc_req_npd[7]), + .I1(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_d_con[7]), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un36_fc_d_av_o_axb_7_4786) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un36_fc_d_av_o_axb_6.INIT = 4'h9; + LUT2_L com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un36_fc_d_av_o_axb_6 ( + .I0(com_tlm_u_tlm_rx_fc_req_npd[6]), + .I1(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_d_con[6]), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un36_fc_d_av_o_axb_6_4787) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un36_fc_d_av_o_axb_5.INIT = 4'h9; + LUT2_L com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un36_fc_d_av_o_axb_5 ( + .I0(com_tlm_u_tlm_rx_fc_req_npd[5]), + .I1(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_d_con[5]), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un36_fc_d_av_o_axb_5_4788) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un36_fc_d_av_o_axb_4.INIT = 4'h9; + LUT2_L com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un36_fc_d_av_o_axb_4 ( + .I0(com_tlm_u_tlm_rx_fc_req_npd[4]), + .I1(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_d_con[4]), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un36_fc_d_av_o_axb_4_4789) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un36_fc_d_av_o_axb_3.INIT = 4'h9; + LUT2_L com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un36_fc_d_av_o_axb_3 ( + .I0(com_tlm_u_tlm_rx_fc_req_npd[3]), + .I1(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_d_con[3]), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un36_fc_d_av_o_axb_3_4790) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un36_fc_d_av_o_axb_2.INIT = 4'h9; + LUT2_L com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un36_fc_d_av_o_axb_2 ( + .I0(com_tlm_u_tlm_rx_fc_req_npd[2]), + .I1(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_d_con[2]), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un36_fc_d_av_o_axb_2_4791) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un36_fc_d_av_o_axb_1.INIT = 4'h9; + LUT2_L com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un36_fc_d_av_o_axb_1 ( + .I0(com_tlm_u_tlm_rx_fc_req_npd[1]), + .I1(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_d_con[1]), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un36_fc_d_av_o_axb_1_4792) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un36_fc_d_av_o_axb_0_i.INIT = 4'h1; + LUT1_L com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un36_fc_d_av_o_axb_0_i ( + .I0(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un36_fc_d_av_o_axb_0_4794), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un36_fc_d_av_o_axb_0_i_4793) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un35_fc_h_av_o_axb_7.INIT = 4'h9; + LUT2_L com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un35_fc_h_av_o_axb_7 ( + .I0(com_tlm_u_tlm_rx_fc_req_nph[7]), + .I1(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_h_con[7]), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un35_fc_h_av_o_axb_7_4795) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un35_fc_h_av_o_axb_6.INIT = 4'h9; + LUT2_L com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un35_fc_h_av_o_axb_6 ( + .I0(com_tlm_u_tlm_rx_fc_req_nph[6]), + .I1(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_h_con[6]), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un35_fc_h_av_o_axb_6_4796) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un35_fc_h_av_o_axb_5.INIT = 4'h9; + LUT2_L com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un35_fc_h_av_o_axb_5 ( + .I0(com_tlm_u_tlm_rx_fc_req_nph[5]), + .I1(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_h_con[5]), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un35_fc_h_av_o_axb_5_4797) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un35_fc_h_av_o_axb_4.INIT = 4'h9; + LUT2_L com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un35_fc_h_av_o_axb_4 ( + .I0(com_tlm_u_tlm_rx_fc_req_nph[4]), + .I1(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_h_con[4]), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un35_fc_h_av_o_axb_4_4798) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un35_fc_h_av_o_axb_3.INIT = 4'h9; + LUT2_L com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un35_fc_h_av_o_axb_3 ( + .I0(com_tlm_u_tlm_rx_fc_req_nph[3]), + .I1(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_h_con[3]), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un35_fc_h_av_o_axb_3_4799) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un35_fc_h_av_o_axb_2.INIT = 4'h9; + LUT2_L com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un35_fc_h_av_o_axb_2 ( + .I0(com_tlm_u_tlm_rx_fc_req_nph[2]), + .I1(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_h_con[2]), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un35_fc_h_av_o_axb_2_4800) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un35_fc_h_av_o_axb_1.INIT = 4'h9; + LUT2_L com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un35_fc_h_av_o_axb_1 ( + .I0(com_tlm_u_tlm_rx_fc_req_nph[1]), + .I1(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_h_con[1]), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un35_fc_h_av_o_axb_1_4801) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un35_fc_h_av_o_axb_0_i.INIT = 4'h1; + LUT1_L com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un35_fc_h_av_o_axb_0_i ( + .I0(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un35_fc_h_av_o_axb_0_4803), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un35_fc_h_av_o_axb_0_i_4802) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_d_o_axb_11.INIT = 4'h2; + LUT1_L com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_d_o_axb_11 ( + .I0(com_tlm_u_tlm_rx_fc_req_npd[11]), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_d_o_axb_11_4804) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_d_o_axb_10.INIT = 4'h2; + LUT1_L com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_d_o_axb_10 ( + .I0(com_tlm_u_tlm_rx_fc_req_npd[10]), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_d_o_axb_10_4805) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_d_o_axb_9.INIT = 4'h2; + LUT1_L com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_d_o_axb_9 ( + .I0(com_tlm_u_tlm_rx_fc_req_npd[9]), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_d_o_axb_9_4806) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_d_o_axb_8.INIT = 4'h2; + LUT1_L com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_d_o_axb_8 ( + .I0(com_tlm_u_tlm_rx_fc_req_npd[8]), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_d_o_axb_8_4807) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_d_o_axb_7.INIT = 4'h2; + LUT1_L com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_d_o_axb_7 ( + .I0(com_tlm_u_tlm_rx_fc_req_npd[7]), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_d_o_axb_7_4808) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_d_o_axb_6.INIT = 4'h2; + LUT1_L com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_d_o_axb_6 ( + .I0(com_tlm_u_tlm_rx_fc_req_npd[6]), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_d_o_axb_6_4809) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_d_o_axb_5.INIT = 8'h6C; + LUT3_L com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_d_o_axb_5 ( + .I0(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_N_56077_i), + .I1(com_tlm_u_tlm_rx_fc_req_npd[5]), + .I2(com_tlm_u_tlm_rx_fc_use_data[5]), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_d_o_axb_5_4810) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_d_o_axb_4.INIT = 8'h6C; + LUT3_L com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_d_o_axb_4 ( + .I0(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_N_56077_i), + .I1(com_tlm_u_tlm_rx_fc_req_npd[4]), + .I2(com_tlm_u_tlm_rx_fc_use_data[4]), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_d_o_axb_4_4811) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_d_o_axb_3.INIT = 8'h6C; + LUT3_L com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_d_o_axb_3 ( + .I0(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_N_56077_i), + .I1(com_tlm_u_tlm_rx_fc_req_npd[3]), + .I2(com_tlm_u_tlm_rx_fc_use_data[3]), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_d_o_axb_3_4812) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_d_o_axb_2.INIT = 8'h6C; + LUT3_L com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_d_o_axb_2 ( + .I0(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_N_56077_i), + .I1(com_tlm_u_tlm_rx_fc_req_npd[2]), + .I2(com_tlm_u_tlm_rx_fc_use_data[2]), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_d_o_axb_2_4813) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_d_o_axb_1.INIT = 8'h6C; + LUT3_L com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_d_o_axb_1 ( + .I0(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_N_56077_i), + .I1(com_tlm_u_tlm_rx_fc_req_npd[1]), + .I2(com_tlm_u_tlm_rx_fc_use_data[1]), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_d_o_axb_1_4814) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_d_o_axb_0.INIT = 8'h6C; + LUT3_L com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_d_o_axb_0 ( + .I0(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_N_56077_i), + .I1(com_tlm_u_tlm_rx_fc_req_npd[0]), + .I2(com_tlm_u_tlm_rx_fc_use_data[0]), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un37_fc_req_d_o_axb_0_4815) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un1_fc_d_con_1_axb_11.INIT = 4'h2; + LUT1_L com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un1_fc_d_con_1_axb_11 ( + .I0(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_d_con[11]), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un1_fc_d_con_1_axb_11_4816) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un1_fc_d_con_1_axb_10.INIT = 4'h2; + LUT1_L com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un1_fc_d_con_1_axb_10 ( + .I0(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_d_con[10]), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un1_fc_d_con_1_axb_10_4817) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un1_fc_d_con_1_axb_9.INIT = 4'h2; + LUT1_L com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un1_fc_d_con_1_axb_9 ( + .I0(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_d_con[9]), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un1_fc_d_con_1_axb_9_4818) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un1_fc_d_con_1_axb_8.INIT = 4'h2; + LUT1_L com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un1_fc_d_con_1_axb_8 ( + .I0(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_d_con[8]), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un1_fc_d_con_1_axb_8_4819) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un1_fc_d_con_1_axb_7.INIT = 4'h2; + LUT1_L com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un1_fc_d_con_1_axb_7 ( + .I0(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_d_con[7]), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un1_fc_d_con_1_axb_7_4820) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un1_fc_d_con_1_axb_6.INIT = 4'h2; + LUT1_L com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un1_fc_d_con_1_axb_6 ( + .I0(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_d_con[6]), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un1_fc_d_con_1_axb_6_4821) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un1_fc_d_con_1_axb_5.INIT = 8'h78; + LUT3_L com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un1_fc_d_con_1_axb_5 ( + .I0(com_tlm_u_tlm_rx_fc_use_data[5]), + .I1(com_tlm_u_tlm_rx_fc_use_np), + .I2(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_d_con[5]), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un1_fc_d_con_1_axb_5_4822) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un1_fc_d_con_1_axb_4.INIT = 8'h78; + LUT3_L com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un1_fc_d_con_1_axb_4 ( + .I0(com_tlm_u_tlm_rx_fc_use_data[4]), + .I1(com_tlm_u_tlm_rx_fc_use_np), + .I2(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_d_con[4]), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un1_fc_d_con_1_axb_4_4823) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un1_fc_d_con_1_axb_3.INIT = 8'h78; + LUT3_L com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un1_fc_d_con_1_axb_3 ( + .I0(com_tlm_u_tlm_rx_fc_use_data[3]), + .I1(com_tlm_u_tlm_rx_fc_use_np), + .I2(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_d_con[3]), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un1_fc_d_con_1_axb_3_4824) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un1_fc_d_con_1_axb_2.INIT = 8'h78; + LUT3_L com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un1_fc_d_con_1_axb_2 ( + .I0(com_tlm_u_tlm_rx_fc_use_data[2]), + .I1(com_tlm_u_tlm_rx_fc_use_np), + .I2(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_d_con[2]), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un1_fc_d_con_1_axb_2_4825) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un1_fc_d_con_1_axb_1.INIT = 8'h78; + LUT3_L com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un1_fc_d_con_1_axb_1 ( + .I0(com_tlm_u_tlm_rx_fc_use_data[1]), + .I1(com_tlm_u_tlm_rx_fc_use_np), + .I2(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_d_con[1]), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un1_fc_d_con_1_axb_1_4826) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_N_87152_i.INIT = 8'hF4; + LUT3_L com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_N_87152_i ( + .I0(com_tlm_u_tlm_rx_fc_sched_np), + .I1(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_send_state_2__4830), + .I2(com_tlm_u_tlm_rx_fc_send_state_0_sqmuxa_0), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_N_87152_i_4827) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_N_87153_i.INIT = 16'h7530; + LUT4_L com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_N_87153_i ( + .I0(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_N_57045_i), + .I1(com_tlm_u_tlm_rx_fc_req_np_dst_rdy), + .I2(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_req_np_src_rdy), + .I3(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_send_state_0__4831), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_N_87153_i_4828) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_N_87154_i.INIT = 16'hECA0; + LUT4_L com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_N_87154_i ( + .I0(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_N_57045_i), + .I1(com_tlm_u_tlm_rx_fc_sched_np), + .I2(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_send_state_0__4831), + .I3(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_send_state_2__4830), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_N_87154_i_4829) + ); + FD com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_d_advert_11_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un5_fc_d_advert_s_11_4832), + .Q(com_tlm_u_tlm_rx_vc0_flow_ctrl_fc_d_advert[11]) + ); + FD com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_h_advert_7_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un5_fc_h_advert_s_7_4833), + .Q(com_tlm_u_tlm_rx_vc0_flow_ctrl_fc_h_advert[7]) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_h_con_qxu_0_0_.INIT = 4'h2; + LUT1_L com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_h_con_qxu_0_0_ ( + .I0(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_h_con[0]), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_h_con_qxu[0]) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_h_con_qxu_0_7_.INIT = 4'h2; + LUT1_L com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_h_con_qxu_0_7_ ( + .I0(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_h_con[7]), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_h_con_qxu[7]) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_h_con_qxu_0_6_.INIT = 4'h2; + LUT1_L com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_h_con_qxu_0_6_ ( + .I0(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_h_con[6]), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_h_con_qxu[6]) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_h_con_qxu_0_5_.INIT = 4'h2; + LUT1_L com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_h_con_qxu_0_5_ ( + .I0(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_h_con[5]), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_h_con_qxu[5]) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_h_con_qxu_0_4_.INIT = 4'h2; + LUT1_L com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_h_con_qxu_0_4_ ( + .I0(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_h_con[4]), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_h_con_qxu[4]) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_h_con_qxu_0_3_.INIT = 4'h2; + LUT1_L com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_h_con_qxu_0_3_ ( + .I0(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_h_con[3]), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_h_con_qxu[3]) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_h_con_qxu_0_2_.INIT = 4'h2; + LUT1_L com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_h_con_qxu_0_2_ ( + .I0(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_h_con[2]), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_h_con_qxu[2]) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_h_con_qxu_0_1_.INIT = 4'h2; + LUT1_L com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_h_con_qxu_0_1_ ( + .I0(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_h_con[1]), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_h_con_qxu[1]) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_h_con_s_0_.INIT = 4'h1; + LUT1_L com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_h_con_s_0_ ( + .I0(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_h_con_qxu[0]), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_h_con_s[0]) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un5_fc_d_advert_axb_10.INIT = 4'h9; + LUT2 com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un5_fc_d_advert_axb_10 ( + .I0(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_d_alo[10]), + .I1(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_d_con[10]), + .O(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un5_fc_d_advert_axb_10_4834) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un5_fc_d_advert_axb_9.INIT = 4'h9; + LUT2 com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un5_fc_d_advert_axb_9 ( + .I0(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_d_alo[9]), + .I1(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_d_con[9]), + .O(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un5_fc_d_advert_axb_9_4835) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un5_fc_d_advert_axb_8.INIT = 4'h9; + LUT2 com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un5_fc_d_advert_axb_8 ( + .I0(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_d_alo[8]), + .I1(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_d_con[8]), + .O(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un5_fc_d_advert_axb_8_4836) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un5_fc_d_advert_axb_7.INIT = 4'h9; + LUT2 com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un5_fc_d_advert_axb_7 ( + .I0(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_d_alo[7]), + .I1(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_d_con[7]), + .O(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un5_fc_d_advert_axb_7_4837) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un5_fc_d_advert_axb_6.INIT = 4'h9; + LUT2 com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un5_fc_d_advert_axb_6 ( + .I0(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_d_alo[6]), + .I1(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_d_con[6]), + .O(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un5_fc_d_advert_axb_6_4838) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un5_fc_d_advert_axb_5.INIT = 4'h9; + LUT2 com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un5_fc_d_advert_axb_5 ( + .I0(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_d_alo[5]), + .I1(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_d_con[5]), + .O(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un5_fc_d_advert_axb_5_4839) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un5_fc_d_advert_axb_4.INIT = 4'h9; + LUT2 com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un5_fc_d_advert_axb_4 ( + .I0(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_d_alo[4]), + .I1(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_d_con[4]), + .O(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un5_fc_d_advert_axb_4_4840) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un5_fc_d_advert_axb_3.INIT = 4'h9; + LUT2 com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un5_fc_d_advert_axb_3 ( + .I0(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_d_alo[3]), + .I1(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_d_con[3]), + .O(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un5_fc_d_advert_axb_3_4841) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un5_fc_d_advert_axb_2.INIT = 4'h9; + LUT2 com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un5_fc_d_advert_axb_2 ( + .I0(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_d_alo[2]), + .I1(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_d_con[2]), + .O(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un5_fc_d_advert_axb_2_4842) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un5_fc_d_advert_axb_1.INIT = 4'h9; + LUT2 com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un5_fc_d_advert_axb_1 ( + .I0(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_d_alo[1]), + .I1(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_d_con[1]), + .O(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un5_fc_d_advert_axb_1_4843) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un5_fc_d_advert_axb_0.INIT = 4'h9; + LUT2 com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un5_fc_d_advert_axb_0 ( + .I0(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_d_alo[0]), + .I1(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_d_con[0]), + .O(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un5_fc_d_advert_axb_0_4844) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un5_fc_h_advert_axb_6.INIT = 4'h9; + LUT2 com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un5_fc_h_advert_axb_6 ( + .I0(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_h_alo[6]), + .I1(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_h_con[6]), + .O(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un5_fc_h_advert_axb_6_4845) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un5_fc_h_advert_axb_5.INIT = 4'h9; + LUT2 com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un5_fc_h_advert_axb_5 ( + .I0(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_h_alo[5]), + .I1(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_h_con[5]), + .O(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un5_fc_h_advert_axb_5_4846) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un5_fc_h_advert_axb_4.INIT = 4'h9; + LUT2 com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un5_fc_h_advert_axb_4 ( + .I0(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_h_alo[4]), + .I1(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_h_con[4]), + .O(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un5_fc_h_advert_axb_4_4847) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un5_fc_h_advert_axb_3.INIT = 4'h9; + LUT2 com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un5_fc_h_advert_axb_3 ( + .I0(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_h_alo[3]), + .I1(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_h_con[3]), + .O(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un5_fc_h_advert_axb_3_4848) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un5_fc_h_advert_axb_2.INIT = 4'h9; + LUT2 com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un5_fc_h_advert_axb_2 ( + .I0(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_h_alo[2]), + .I1(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_h_con[2]), + .O(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un5_fc_h_advert_axb_2_4849) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un5_fc_h_advert_axb_1.INIT = 4'h9; + LUT2 com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un5_fc_h_advert_axb_1 ( + .I0(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_h_alo[1]), + .I1(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_h_con[1]), + .O(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un5_fc_h_advert_axb_1_4850) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un5_fc_h_advert_axb_0.INIT = 4'h9; + LUT2 com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un5_fc_h_advert_axb_0 ( + .I0(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_h_alo[0]), + .I1(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_fc_h_con[0]), + .O(com_tlm_u_tlm_rx_vc0_flow_ctrl_nonposted_un5_fc_h_advert_axb_0_4851) + ); + VCC com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_VCC ( + .P(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_VCC_5052) + ); + GND com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_GND ( + .G(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_GND_4932) + ); + FDR com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_d_con_0_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_d_con_2_axb_0_4935), + .Q(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_d_con[0]), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_d_con_1_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_d_con_2_s_1_4876), + .Q(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_d_con[1]), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_d_con_2_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_d_con_2_s_2_4879), + .Q(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_d_con[2]), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_d_con_3_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_d_con_2_s_3_4882), + .Q(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_d_con[3]), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_d_con_4_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_d_con_2_s_4_4885), + .Q(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_d_con[4]), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_d_con_5_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_d_con_2_s_5_4888), + .Q(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_d_con[5]), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_d_con_6_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_d_con_2_s_6_4890), + .Q(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_d_con[6]), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_d_con_7_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_d_con_2_s_7_4892), + .Q(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_d_con[7]), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_d_con_8_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_d_con_2_s_8_4894), + .Q(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_d_con[8]), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_d_con_9_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_d_con_2_s_9_4896), + .Q(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_d_con[9]), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_d_con_10_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_d_con_2_s_10_4898), + .Q(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_d_con[10]), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_d_con_11_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_d_con_2_s_11_4900), + .Q(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_d_con[11]), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_free_h ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_free_h_13), + .Q(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_free_h_4933), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_free_d ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_free_d_13), + .Q(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_free_d_4934), + .R(plm_link_up_i) + ); + MUXCY_L com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_h_o_2_cry_0 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_free_h[0]), + .DI(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_h_o_i_m3_i_m4_i_m3_i_m3_0_0__5044), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_h_o_2_cry_0_4852), + .S(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_h_o_2_axb_0_4950) + ); + XORCY com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_h_o_2_s_0 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_free_h[0]), + .LI(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_h_o_2_axb_0_4950), + .O(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_h_o_2_s_0_5001) + ); + MUXCY_L com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_h_o_2_cry_1 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_h_o_2_cry_0_4852), + .DI(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_GND_4932), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_h_o_2_cry_1_4853), + .S(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_h_o_2_axb_1_4949) + ); + XORCY com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_h_o_2_s_1 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_h_o_2_cry_0_4852), + .LI(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_h_o_2_axb_1_4949), + .O(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_h_o_2_s_1_5000) + ); + MUXCY_L com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_h_o_2_cry_2 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_h_o_2_cry_1_4853), + .DI(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_h_o_i_m3_i_m4_i_m3_i_m3_0_2__5046), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_h_o_2_cry_2_4854), + .S(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_h_o_2_axb_2_4948) + ); + XORCY com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_h_o_2_s_2 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_h_o_2_cry_1_4853), + .LI(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_h_o_2_axb_2_4948), + .O(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_h_o_2_s_2_4999) + ); + MUXCY_L com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_h_o_2_cry_3 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_h_o_2_cry_2_4854), + .DI(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_GND_4932), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_h_o_2_cry_3_4855), + .S(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_h_o_2_axb_3_4947) + ); + XORCY com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_h_o_2_s_3 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_h_o_2_cry_2_4854), + .LI(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_h_o_2_axb_3_4947), + .O(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_h_o_2_s_3_4998) + ); + MUXCY_L com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_h_o_2_cry_4 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_h_o_2_cry_3_4855), + .DI(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_GND_4932), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_h_o_2_cry_4_4856), + .S(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_h_o_2_axb_4_4946) + ); + XORCY com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_h_o_2_s_4 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_h_o_2_cry_3_4855), + .LI(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_h_o_2_axb_4_4946), + .O(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_h_o_2_s_4_4997) + ); + MUXCY_L com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_h_o_2_cry_5 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_h_o_2_cry_4_4856), + .DI(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_N_10115_i_5048), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_h_o_2_cry_5_4857), + .S(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_h_o_2_axb_5_4975) + ); + XORCY com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_h_o_2_s_5 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_h_o_2_cry_4_4856), + .LI(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_h_o_2_axb_5_4975), + .O(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_h_o_2_s_5_5026) + ); + MUXCY_L com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_h_o_2_cry_6 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_h_o_2_cry_5_4857), + .DI(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_GND_4932), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_h_o_2_cry_6_4858), + .S(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_h_o_2_axb_6_4974) + ); + XORCY com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_h_o_2_s_6 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_h_o_2_cry_5_4857), + .LI(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_h_o_2_axb_6_4974), + .O(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_h_o_2_s_6_5025) + ); + XORCY com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_h_o_2_s_7 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_h_o_2_cry_6_4858), + .LI(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_h_o_2_axb_7_4973), + .O(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_h_o_2_s_7_5024) + ); + MUXCY_L com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_2_cry_0 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_free_d[0]), + .DI(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_2_cry_0_ma_5049), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_2_cry_0_4860), + .S(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_2_axb_0_4972) + ); + XORCY com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_2_s_0 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_free_d[0]), + .LI(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_2_axb_0_4972), + .O(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_2_s_0_5023) + ); + MULT_AND com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_2_cry_1 ( + .I0(com_tlm_u_tlm_rx_fc_use_data[1]), + .I1(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_N_60525_1), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_2_cry_1_0_4859) + ); + MUXCY_L com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_2_cry_1_0 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_2_cry_0_4860), + .DI(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_2_cry_1_0_4859), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_2_cry_1_4862), + .S(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_2_axb_1_4971) + ); + XORCY com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_2_s_1 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_2_cry_0_4860), + .LI(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_2_axb_1_4971), + .O(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_2_s_1_5022) + ); + MULT_AND com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_2_cry_2 ( + .I0(com_tlm_u_tlm_rx_fc_use_data[2]), + .I1(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_N_60525_1), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_2_cry_2_0_4861) + ); + MUXCY_L com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_2_cry_2_0 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_2_cry_1_4862), + .DI(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_2_cry_2_0_4861), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_2_cry_2_4864), + .S(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_2_axb_2_4970) + ); + XORCY com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_2_s_2 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_2_cry_1_4862), + .LI(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_2_axb_2_4970), + .O(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_2_s_2_5021) + ); + MULT_AND com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_2_cry_3 ( + .I0(com_tlm_u_tlm_rx_fc_use_data[3]), + .I1(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_N_60525_1), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_2_cry_3_0_4863) + ); + MUXCY_L com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_2_cry_3_0 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_2_cry_2_4864), + .DI(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_2_cry_3_0_4863), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_2_cry_3_4865), + .S(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_2_axb_3_4969) + ); + XORCY com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_2_s_3 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_2_cry_2_4864), + .LI(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_2_axb_3_4969), + .O(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_2_s_3_5020) + ); + MUXCY_L com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_2_cry_4 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_2_cry_3_4865), + .DI(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_2_cry_4_ma_5051), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_2_cry_4_4867), + .S(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_2_axb_4_4968) + ); + XORCY com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_2_s_4 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_2_cry_3_4865), + .LI(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_2_axb_4_4968), + .O(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_2_s_4_5019) + ); + MULT_AND com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_2_cry_5 ( + .I0(com_tlm_u_tlm_rx_fc_use_data[5]), + .I1(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_N_60525_1), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_2_cry_5_0_4866) + ); + MUXCY_L com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_2_cry_5_0 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_2_cry_4_4867), + .DI(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_2_cry_5_0_4866), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_2_cry_5_4868), + .S(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_2_axb_5_4967) + ); + XORCY com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_2_s_5 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_2_cry_4_4867), + .LI(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_2_axb_5_4967), + .O(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_2_s_5_5018) + ); + MUXCY_L com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_2_cry_6 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_2_cry_5_4868), + .DI(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_GND_4932), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_2_cry_6_4869), + .S(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_2_axb_6_4966) + ); + XORCY com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_2_s_6 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_2_cry_5_4868), + .LI(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_2_axb_6_4966), + .O(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_2_s_6_5017) + ); + MUXCY_L com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_2_cry_7 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_2_cry_6_4869), + .DI(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_N_10126_i_5042), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_2_cry_7_4870), + .S(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_2_axb_7_4965) + ); + XORCY com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_2_s_7 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_2_cry_6_4869), + .LI(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_2_axb_7_4965), + .O(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_2_s_7_5016) + ); + MUXCY_L com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_2_cry_8 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_2_cry_7_4870), + .DI(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_GND_4932), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_2_cry_8_4871), + .S(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_2_axb_8_4964) + ); + XORCY com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_2_s_8 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_2_cry_7_4870), + .LI(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_2_axb_8_4964), + .O(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_2_s_8_5015) + ); + MUXCY_L com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_2_cry_9 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_2_cry_8_4871), + .DI(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_GND_4932), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_2_cry_9_4872), + .S(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_2_axb_9_4963) + ); + XORCY com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_2_s_9 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_2_cry_8_4871), + .LI(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_2_axb_9_4963), + .O(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_2_s_9_5014) + ); + MUXCY_L com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_2_cry_10 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_2_cry_9_4872), + .DI(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_GND_4932), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_2_cry_10_4873), + .S(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_2_axb_10_4962) + ); + XORCY com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_2_s_10 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_2_cry_9_4872), + .LI(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_2_axb_10_4962), + .O(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_2_s_10_5013) + ); + XORCY com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_2_s_11 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_2_cry_10_4873), + .LI(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_2_axb_11_4961), + .O(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_2_s_11_5012) + ); + MULT_AND com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_d_con_2_cry_0 ( + .I0(com_tlm_u_tlm_rx_fc_use_cpl), + .I1(com_tlm_u_tlm_rx_fc_use_data[0]), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_d_con_2_cry_0_0_4874) + ); + MUXCY_L com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_d_con_2_cry_0_0 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_GND_4932), + .DI(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_d_con_2_cry_0_0_4874), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_d_con_2_cry_0_4877), + .S(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_d_con_2_axb_0_4935) + ); + MULT_AND com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_d_con_2_cry_1 ( + .I0(com_tlm_u_tlm_rx_fc_use_cpl), + .I1(com_tlm_u_tlm_rx_fc_use_data[1]), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_d_con_2_cry_1_0_4875) + ); + MUXCY_L com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_d_con_2_cry_1_0 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_d_con_2_cry_0_4877), + .DI(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_d_con_2_cry_1_0_4875), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_d_con_2_cry_1_4880), + .S(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_d_con_2_axb_1_4986) + ); + XORCY com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_d_con_2_s_1 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_d_con_2_cry_0_4877), + .LI(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_d_con_2_axb_1_4986), + .O(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_d_con_2_s_1_4876) + ); + MULT_AND com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_d_con_2_cry_2 ( + .I0(com_tlm_u_tlm_rx_fc_use_cpl), + .I1(com_tlm_u_tlm_rx_fc_use_data[2]), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_d_con_2_cry_2_0_4878) + ); + MUXCY_L com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_d_con_2_cry_2_0 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_d_con_2_cry_1_4880), + .DI(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_d_con_2_cry_2_0_4878), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_d_con_2_cry_2_4883), + .S(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_d_con_2_axb_2_4985) + ); + XORCY com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_d_con_2_s_2 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_d_con_2_cry_1_4880), + .LI(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_d_con_2_axb_2_4985), + .O(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_d_con_2_s_2_4879) + ); + MULT_AND com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_d_con_2_cry_3 ( + .I0(com_tlm_u_tlm_rx_fc_use_cpl), + .I1(com_tlm_u_tlm_rx_fc_use_data[3]), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_d_con_2_cry_3_0_4881) + ); + MUXCY_L com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_d_con_2_cry_3_0 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_d_con_2_cry_2_4883), + .DI(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_d_con_2_cry_3_0_4881), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_d_con_2_cry_3_4886), + .S(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_d_con_2_axb_3_4984) + ); + XORCY com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_d_con_2_s_3 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_d_con_2_cry_2_4883), + .LI(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_d_con_2_axb_3_4984), + .O(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_d_con_2_s_3_4882) + ); + MULT_AND com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_d_con_2_cry_4 ( + .I0(com_tlm_u_tlm_rx_fc_use_cpl), + .I1(com_tlm_u_tlm_rx_fc_use_data[4]), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_d_con_2_cry_4_0_4884) + ); + MUXCY_L com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_d_con_2_cry_4_0 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_d_con_2_cry_3_4886), + .DI(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_d_con_2_cry_4_0_4884), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_d_con_2_cry_4_4889), + .S(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_d_con_2_axb_4_4983) + ); + XORCY com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_d_con_2_s_4 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_d_con_2_cry_3_4886), + .LI(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_d_con_2_axb_4_4983), + .O(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_d_con_2_s_4_4885) + ); + MULT_AND com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_d_con_2_cry_5 ( + .I0(com_tlm_u_tlm_rx_fc_use_cpl), + .I1(com_tlm_u_tlm_rx_fc_use_data[5]), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_d_con_2_cry_5_0_4887) + ); + MUXCY_L com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_d_con_2_cry_5_0 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_d_con_2_cry_4_4889), + .DI(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_d_con_2_cry_5_0_4887), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_d_con_2_cry_5_4891), + .S(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_d_con_2_axb_5_4982) + ); + XORCY com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_d_con_2_s_5 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_d_con_2_cry_4_4889), + .LI(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_d_con_2_axb_5_4982), + .O(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_d_con_2_s_5_4888) + ); + MUXCY_L com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_d_con_2_cry_6 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_d_con_2_cry_5_4891), + .DI(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_GND_4932), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_d_con_2_cry_6_4893), + .S(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_d_con_2_axb_6_4981) + ); + XORCY com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_d_con_2_s_6 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_d_con_2_cry_5_4891), + .LI(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_d_con_2_axb_6_4981), + .O(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_d_con_2_s_6_4890) + ); + MUXCY_L com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_d_con_2_cry_7 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_d_con_2_cry_6_4893), + .DI(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_GND_4932), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_d_con_2_cry_7_4895), + .S(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_d_con_2_axb_7_4980) + ); + XORCY com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_d_con_2_s_7 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_d_con_2_cry_6_4893), + .LI(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_d_con_2_axb_7_4980), + .O(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_d_con_2_s_7_4892) + ); + MUXCY_L com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_d_con_2_cry_8 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_d_con_2_cry_7_4895), + .DI(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_GND_4932), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_d_con_2_cry_8_4897), + .S(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_d_con_2_axb_8_4979) + ); + XORCY com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_d_con_2_s_8 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_d_con_2_cry_7_4895), + .LI(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_d_con_2_axb_8_4979), + .O(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_d_con_2_s_8_4894) + ); + MUXCY_L com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_d_con_2_cry_9 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_d_con_2_cry_8_4897), + .DI(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_GND_4932), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_d_con_2_cry_9_4899), + .S(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_d_con_2_axb_9_4978) + ); + XORCY com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_d_con_2_s_9 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_d_con_2_cry_8_4897), + .LI(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_d_con_2_axb_9_4978), + .O(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_d_con_2_s_9_4896) + ); + MUXCY_L com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_d_con_2_cry_10 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_d_con_2_cry_9_4899), + .DI(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_GND_4932), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_d_con_2_cry_10_4901), + .S(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_d_con_2_axb_10_4977) + ); + XORCY com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_d_con_2_s_10 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_d_con_2_cry_9_4899), + .LI(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_d_con_2_axb_10_4977), + .O(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_d_con_2_s_10_4898) + ); + XORCY com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_d_con_2_s_11 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_d_con_2_cry_10_4901), + .LI(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_d_con_2_axb_11_4976), + .O(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_d_con_2_s_11_4900) + ); + MUXCY_L com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_h_o_1_cry_0 ( + .CI(plm_link_up_2), + .DI(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_h_o_1_cry_0_ma_5043), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_h_o_1_cry_0_4903), + .S(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_h_o_1_axb_0_4958) + ); + XORCY com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_h_o_1_s_0 ( + .CI(plm_link_up_2), + .LI(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_h_o_1_axb_0_4958), + .O(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_h_o_1_s_0_5009) + ); + MULT_AND com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_h_o_1_cry_1 ( + .I0(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_h_con_i_1__5027), + .I1(plm_link_up_2), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_h_o_1_cry_1_0_4902) + ); + MUXCY_L com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_h_o_1_cry_1_0 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_h_o_1_cry_0_4903), + .DI(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_h_o_1_cry_1_0_4902), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_h_o_1_cry_1_4904), + .S(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_h_o_1_axb_1_4957) + ); + XORCY com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_h_o_1_s_1 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_h_o_1_cry_0_4903), + .LI(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_h_o_1_axb_1_4957), + .O(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_h_o_1_s_1_5008) + ); + MUXCY_L com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_h_o_1_cry_2 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_h_o_1_cry_1_4904), + .DI(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_h_o_1_cry_2_ma_5045), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_h_o_1_cry_2_4906), + .S(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_h_o_1_axb_2_4956) + ); + XORCY com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_h_o_1_s_2 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_h_o_1_cry_1_4904), + .LI(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_h_o_1_axb_2_4956), + .O(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_h_o_1_s_2_5007) + ); + MULT_AND com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_h_o_1_cry_3 ( + .I0(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_h_con_i_3__5028), + .I1(plm_link_up_1), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_h_o_1_cry_3_0_4905) + ); + MUXCY_L com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_h_o_1_cry_3_0 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_h_o_1_cry_2_4906), + .DI(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_h_o_1_cry_3_0_4905), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_h_o_1_cry_3_4908), + .S(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_h_o_1_axb_3_4955) + ); + XORCY com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_h_o_1_s_3 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_h_o_1_cry_2_4906), + .LI(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_h_o_1_axb_3_4955), + .O(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_h_o_1_s_3_5006) + ); + MULT_AND com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_h_o_1_cry_4 ( + .I0(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_h_con_i_4__5029), + .I1(plm_link_up_1), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_h_o_1_cry_4_0_4907) + ); + MUXCY_L com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_h_o_1_cry_4_0 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_h_o_1_cry_3_4908), + .DI(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_h_o_1_cry_4_0_4907), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_h_o_1_cry_4_4909), + .S(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_h_o_1_axb_4_4954) + ); + XORCY com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_h_o_1_s_4 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_h_o_1_cry_3_4908), + .LI(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_h_o_1_axb_4_4954), + .O(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_h_o_1_s_4_5005) + ); + MUXCY_L com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_h_o_1_cry_5 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_h_o_1_cry_4_4909), + .DI(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_h_o_1_cry_5_ma_5047), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_h_o_1_cry_5_4911), + .S(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_h_o_1_axb_5_4953) + ); + XORCY com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_h_o_1_s_5 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_h_o_1_cry_4_4909), + .LI(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_h_o_1_axb_5_4953), + .O(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_h_o_1_s_5_5004) + ); + MULT_AND com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_h_o_1_cry_6 ( + .I0(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_h_con_i_6__5030), + .I1(plm_link_up_1), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_h_o_1_cry_6_0_4910) + ); + MUXCY_L com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_h_o_1_cry_6_0 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_h_o_1_cry_5_4911), + .DI(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_h_o_1_cry_6_0_4910), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_h_o_1_cry_6_4912), + .S(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_h_o_1_axb_6_4952) + ); + XORCY com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_h_o_1_s_6 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_h_o_1_cry_5_4911), + .LI(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_h_o_1_axb_6_4952), + .O(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_h_o_1_s_6_5003) + ); + XORCY com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_h_o_1_s_7 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_h_o_1_cry_6_4912), + .LI(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_h_o_1_axb_7_4951), + .O(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_h_o_1_s_7_5002) + ); + MUXCY_L com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_1_cry_0 ( + .CI(plm_link_up_1), + .DI(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_1_cry_0_ma_5039), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_1_cry_0_4914), + .S(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_1_axb_0_4945) + ); + XORCY com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_1_s_0 ( + .CI(plm_link_up_1), + .LI(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_1_axb_0_4945), + .O(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_1_s_0_4996) + ); + MULT_AND com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_1_cry_1 ( + .I0(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_d_con_i_1__5031), + .I1(plm_link_up_1), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_1_cry_1_0_4913) + ); + MUXCY_L com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_1_cry_1_0 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_1_cry_0_4914), + .DI(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_1_cry_1_0_4913), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_1_cry_1_4916), + .S(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_1_axb_1_4944) + ); + XORCY com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_1_s_1 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_1_cry_0_4914), + .LI(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_1_axb_1_4944), + .O(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_1_s_1_4995) + ); + MULT_AND com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_1_cry_2 ( + .I0(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_d_con_i_2__5032), + .I1(plm_link_up_1), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_1_cry_2_0_4915) + ); + MUXCY_L com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_1_cry_2_0 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_1_cry_1_4916), + .DI(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_1_cry_2_0_4915), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_1_cry_2_4918), + .S(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_1_axb_2_4943) + ); + XORCY com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_1_s_2 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_1_cry_1_4916), + .LI(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_1_axb_2_4943), + .O(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_1_s_2_4994) + ); + MULT_AND com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_1_cry_3 ( + .I0(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_d_con_i_3__5033), + .I1(plm_link_up_1), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_1_cry_3_0_4917) + ); + MUXCY_L com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_1_cry_3_0 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_1_cry_2_4918), + .DI(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_1_cry_3_0_4917), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_1_cry_3_4919), + .S(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_1_axb_3_4942) + ); + XORCY com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_1_s_3 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_1_cry_2_4918), + .LI(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_1_axb_3_4942), + .O(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_1_s_3_4993) + ); + MUXCY_L com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_1_cry_4 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_1_cry_3_4919), + .DI(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_1_cry_4_ma_5040), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_1_cry_4_4921), + .S(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_1_axb_4_4941) + ); + XORCY com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_1_s_4 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_1_cry_3_4919), + .LI(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_1_axb_4_4941), + .O(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_1_s_4_4992) + ); + MULT_AND com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_1_cry_5 ( + .I0(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_d_con_i_5__5034), + .I1(plm_link_up_1), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_1_cry_5_0_4920) + ); + MUXCY_L com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_1_cry_5_0 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_1_cry_4_4921), + .DI(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_1_cry_5_0_4920), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_1_cry_5_4923), + .S(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_1_axb_5_4940) + ); + XORCY com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_1_s_5 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_1_cry_4_4921), + .LI(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_1_axb_5_4940), + .O(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_1_s_5_4991) + ); + MULT_AND com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_1_cry_6 ( + .I0(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_d_con_i_6__5035), + .I1(plm_link_up_1), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_1_cry_6_0_4922) + ); + MUXCY_L com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_1_cry_6_0 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_1_cry_5_4923), + .DI(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_1_cry_6_0_4922), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_1_cry_6_4924), + .S(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_1_axb_6_4939) + ); + XORCY com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_1_s_6 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_1_cry_5_4923), + .LI(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_1_axb_6_4939), + .O(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_1_s_6_4990) + ); + MUXCY_L com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_1_cry_7 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_1_cry_6_4924), + .DI(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_1_cry_7_ma_5041), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_1_cry_7_4926), + .S(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_1_axb_7_4938) + ); + XORCY com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_1_s_7 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_1_cry_6_4924), + .LI(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_1_axb_7_4938), + .O(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_1_s_7_4989) + ); + MULT_AND com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_1_cry_8 ( + .I0(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_d_con_i_8__5036), + .I1(plm_link_up_1), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_1_cry_8_0_4925) + ); + MUXCY_L com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_1_cry_8_0 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_1_cry_7_4926), + .DI(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_1_cry_8_0_4925), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_1_cry_8_4928), + .S(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_1_axb_8_4937) + ); + XORCY com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_1_s_8 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_1_cry_7_4926), + .LI(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_1_axb_8_4937), + .O(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_1_s_8_4988) + ); + MULT_AND com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_1_cry_9 ( + .I0(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_d_con_i_9__5037), + .I1(plm_link_up_1), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_1_cry_9_0_4927) + ); + MUXCY_L com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_1_cry_9_0 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_1_cry_8_4928), + .DI(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_1_cry_9_0_4927), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_1_cry_9_4930), + .S(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_1_axb_9_4936) + ); + XORCY com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_1_s_9 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_1_cry_8_4928), + .LI(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_1_axb_9_4936), + .O(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_1_s_9_4987) + ); + MULT_AND com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_1_cry_10 ( + .I0(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_d_con_i_10__5038), + .I1(plm_link_up_2), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_1_cry_10_0_4929) + ); + MUXCY_L com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_1_cry_10_0 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_1_cry_9_4930), + .DI(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_1_cry_10_0_4929), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_1_cry_10_4931), + .S(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_1_axb_10_4960) + ); + XORCY com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_1_s_10 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_1_cry_9_4930), + .LI(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_1_axb_10_4960), + .O(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_1_s_10_5011) + ); + XORCY com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_1_s_11 ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_1_cry_10_4931), + .LI(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_1_axb_11_4959), + .O(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_1_s_11_5010) + ); + FDRE com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_h_con_0_ ( + .CE(com_tlm_u_tlm_rx_fc_use_cpl), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_h_con_s[0]), + .Q(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_h_con[0]), + .R(plm_link_up_i) + ); + MUXCY_L com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_h_con_cry_1_ ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_h_con[0]), + .DI(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_GND_4932), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_h_con_cry[1]), + .S(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_h_con_qxu[1]) + ); + XORCY com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_h_con_s_1_ ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_h_con[0]), + .LI(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_h_con_qxu[1]), + .O(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_h_con_s[1]) + ); + FDRE com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_h_con_1_ ( + .CE(com_tlm_u_tlm_rx_fc_use_cpl), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_h_con_s[1]), + .Q(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_h_con[1]), + .R(plm_link_up_i) + ); + MUXCY_L com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_h_con_cry_2_ ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_h_con_cry[1]), + .DI(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_GND_4932), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_h_con_cry[2]), + .S(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_h_con_qxu[2]) + ); + XORCY com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_h_con_s_2_ ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_h_con_cry[1]), + .LI(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_h_con_qxu[2]), + .O(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_h_con_s[2]) + ); + FDRE com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_h_con_2_ ( + .CE(com_tlm_u_tlm_rx_fc_use_cpl), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_h_con_s[2]), + .Q(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_h_con[2]), + .R(plm_link_up_i) + ); + MUXCY_L com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_h_con_cry_3_ ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_h_con_cry[2]), + .DI(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_GND_4932), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_h_con_cry[3]), + .S(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_h_con_qxu[3]) + ); + XORCY com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_h_con_s_3_ ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_h_con_cry[2]), + .LI(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_h_con_qxu[3]), + .O(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_h_con_s[3]) + ); + FDRE com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_h_con_3_ ( + .CE(com_tlm_u_tlm_rx_fc_use_cpl), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_h_con_s[3]), + .Q(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_h_con[3]), + .R(plm_link_up_i) + ); + MUXCY_L com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_h_con_cry_4_ ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_h_con_cry[3]), + .DI(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_GND_4932), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_h_con_cry[4]), + .S(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_h_con_qxu[4]) + ); + XORCY com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_h_con_s_4_ ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_h_con_cry[3]), + .LI(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_h_con_qxu[4]), + .O(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_h_con_s[4]) + ); + FDRE com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_h_con_4_ ( + .CE(com_tlm_u_tlm_rx_fc_use_cpl), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_h_con_s[4]), + .Q(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_h_con[4]), + .R(plm_link_up_i) + ); + MUXCY_L com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_h_con_cry_5_ ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_h_con_cry[4]), + .DI(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_GND_4932), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_h_con_cry[5]), + .S(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_h_con_qxu[5]) + ); + XORCY com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_h_con_s_5_ ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_h_con_cry[4]), + .LI(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_h_con_qxu[5]), + .O(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_h_con_s[5]) + ); + FDRE com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_h_con_5_ ( + .CE(com_tlm_u_tlm_rx_fc_use_cpl), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_h_con_s[5]), + .Q(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_h_con[5]), + .R(plm_link_up_i) + ); + MUXCY_L com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_h_con_cry_6_ ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_h_con_cry[5]), + .DI(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_GND_4932), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_h_con_cry[6]), + .S(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_h_con_qxu[6]) + ); + XORCY com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_h_con_s_6_ ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_h_con_cry[5]), + .LI(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_h_con_qxu[6]), + .O(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_h_con_s[6]) + ); + FDRE com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_h_con_6_ ( + .CE(com_tlm_u_tlm_rx_fc_use_cpl), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_h_con_s[6]), + .Q(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_h_con[6]), + .R(plm_link_up_i) + ); + XORCY com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_h_con_s_7_ ( + .CI(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_h_con_cry[6]), + .LI(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_h_con_qxu[7]), + .O(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_h_con_s[7]) + ); + FDRE com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_h_con_7_ ( + .CE(com_tlm_u_tlm_rx_fc_use_cpl), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_h_con_s[7]), + .Q(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_h_con[7]), + .R(plm_link_up_i) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_free_h_0_.INIT = 4'h8; + LUT2 com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_free_h_0_ ( + .I0(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_free_h_4933), + .I1(plm_link_up_1), + .O(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_free_h[0]) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_free_d_0_.INIT = 4'h8; + LUT2 com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_free_d_0_ ( + .I0(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_free_d_4934), + .I1(plm_link_up_1), + .O(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_free_d[0]) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_h_o_5_.INIT = 4'h4; + LUT2_L com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_h_o_5_ ( + .I0(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_req_h_o[5]), + .I1(plm_link_up_1), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_h_o[5]) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_unuse_d28_1_i_0_0_a3_0_.INIT = 4'h8; + LUT2 com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_unuse_d28_1_i_0_0_a3_0_ ( + .I0(com_tlm_u_tlm_rx_fc_unuse), + .I1(com_tlm_u_tlm_rx_fc_use_cpl), + .O(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_N_61398) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_i_m3_i_m4_i_m3_i_m3_0_0_.INIT = 8'hCA; + LUT3 com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_i_m3_i_m4_i_m3_i_m3_0_0_ ( + .I0(cfg_cfg_6102[508]), + .I1(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_req_d_o[0]), + .I2(plm_link_up_1), + .O(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_i_m3_i_m4_i_m3_i_m3_0_0__5050) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_i_m3_i_m4_i_m3_i_m3_0_4_.INIT = 8'hCA; + LUT3 com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_i_m3_i_m4_i_m3_i_m3_0_4_ ( + .I0(cfg_cfg_6102[508]), + .I1(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_req_d_o[4]), + .I2(plm_link_up_1), + .O(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_i_m3_i_m4_i_m3_i_m3_0_4__5053) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_h_o_i_m3_i_m4_i_m3_i_m3_0_0_.INIT = 8'hCA; + LUT3 com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_h_o_i_m3_i_m4_i_m3_i_m3_0_0_ ( + .I0(cfg_cfg_6102[508]), + .I1(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_req_h_o[0]), + .I2(plm_link_up_1), + .O(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_h_o_i_m3_i_m4_i_m3_i_m3_0_0__5044) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_h_o_i_m3_i_m4_i_m3_i_m3_0_2_.INIT = 8'hCA; + LUT3 com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_h_o_i_m3_i_m4_i_m3_i_m3_0_2_ ( + .I0(cfg_cfg_6102[508]), + .I1(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_req_h_o[2]), + .I2(plm_link_up_1), + .O(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_h_o_i_m3_i_m4_i_m3_i_m3_0_2__5046) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_d_con_2_axb_0.INIT = 8'h78; + LUT3 com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_d_con_2_axb_0 ( + .I0(com_tlm_u_tlm_rx_fc_use_cpl), + .I1(com_tlm_u_tlm_rx_fc_use_data[0]), + .I2(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_d_con[0]), + .O(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_d_con_2_axb_0_4935) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_N_10126_i.INIT = 4'hB; + LUT2 com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_N_10126_i ( + .I0(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_req_d_o[7]), + .I1(plm_link_up_1), + .O(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_N_10126_i_5042) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_1_axb_9.INIT = 8'h6F; + LUT3_L com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_1_axb_9 ( + .I0(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_d_con_i_9__5037), + .I1(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_req_d_o[9]), + .I2(plm_link_up_1), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_1_axb_9_4936) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_1_axb_8.INIT = 8'h6F; + LUT3_L com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_1_axb_8 ( + .I0(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_d_con_i_8__5036), + .I1(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_req_d_o[8]), + .I2(plm_link_up_1), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_1_axb_8_4937) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_1_axb_7.INIT = 8'h90; + LUT3_L com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_1_axb_7 ( + .I0(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_d_con[7]), + .I1(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_req_d_o[7]), + .I2(plm_link_up_1), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_1_axb_7_4938) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_1_axb_6.INIT = 8'h6F; + LUT3_L com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_1_axb_6 ( + .I0(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_d_con_i_6__5035), + .I1(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_req_d_o[6]), + .I2(plm_link_up_1), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_1_axb_6_4939) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_1_axb_5.INIT = 8'h6F; + LUT3_L com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_1_axb_5 ( + .I0(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_d_con_i_5__5034), + .I1(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_req_d_o[5]), + .I2(plm_link_up_1), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_1_axb_5_4940) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_1_axb_4.INIT = 8'h95; + LUT3_L com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_1_axb_4 ( + .I0(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_i_m3_i_m4_i_m3_i_m3_0_4__5053), + .I1(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_d_con[4]), + .I2(plm_link_up_1), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_1_axb_4_4941) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_1_axb_3.INIT = 8'h6F; + LUT3_L com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_1_axb_3 ( + .I0(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_d_con_i_3__5033), + .I1(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_req_d_o[3]), + .I2(plm_link_up_1), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_1_axb_3_4942) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_1_axb_2.INIT = 8'h6F; + LUT3_L com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_1_axb_2 ( + .I0(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_d_con_i_2__5032), + .I1(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_req_d_o[2]), + .I2(plm_link_up_1), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_1_axb_2_4943) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_1_axb_1.INIT = 8'h6F; + LUT3_L com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_1_axb_1 ( + .I0(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_d_con_i_1__5031), + .I1(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_req_d_o[1]), + .I2(plm_link_up_1), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_1_axb_1_4944) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_1_axb_0.INIT = 8'h95; + LUT3_L com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_1_axb_0 ( + .I0(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_i_m3_i_m4_i_m3_i_m3_0_0__5050), + .I1(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_d_con[0]), + .I2(plm_link_up_1), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_1_axb_0_4945) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_h_o_2_axb_4.INIT = 4'hB; + LUT2_L com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_h_o_2_axb_4 ( + .I0(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_req_h_o[4]), + .I1(plm_link_up_1), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_h_o_2_axb_4_4946) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_h_o_2_axb_3.INIT = 4'hB; + LUT2_L com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_h_o_2_axb_3 ( + .I0(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_req_h_o[3]), + .I1(plm_link_up_1), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_h_o_2_axb_3_4947) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_h_o_2_axb_2.INIT = 4'h9; + LUT2_L com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_h_o_2_axb_2 ( + .I0(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_h_o_i_m3_i_m4_i_m3_i_m3_0_2__5046), + .I1(plm_link_up_1), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_h_o_2_axb_2_4948) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_h_o_2_axb_1.INIT = 4'hB; + LUT2_L com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_h_o_2_axb_1 ( + .I0(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_req_h_o[1]), + .I1(plm_link_up_1), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_h_o_2_axb_1_4949) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_h_o_2_axb_0.INIT = 8'h65; + LUT3_L com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_h_o_2_axb_0 ( + .I0(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_h_o_i_m3_i_m4_i_m3_i_m3_0_0__5044), + .I1(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_N_61398), + .I2(plm_link_up_1), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_h_o_2_axb_0_4950) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_h_o_1_axb_7.INIT = 8'h9F; + LUT3_L com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_h_o_1_axb_7 ( + .I0(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_h_con[7]), + .I1(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_req_h_o[7]), + .I2(plm_link_up_1), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_h_o_1_axb_7_4951) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_h_o_1_axb_6.INIT = 8'h6F; + LUT3_L com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_h_o_1_axb_6 ( + .I0(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_h_con_i_6__5030), + .I1(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_req_h_o[6]), + .I2(plm_link_up_1), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_h_o_1_axb_6_4952) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_h_o_1_axb_5.INIT = 8'h6A; + LUT3_L com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_h_o_1_axb_5 ( + .I0(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_h_o[5]), + .I1(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_h_con[5]), + .I2(plm_link_up_1), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_h_o_1_axb_5_4953) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_h_o_1_axb_4.INIT = 8'h6F; + LUT3_L com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_h_o_1_axb_4 ( + .I0(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_h_con_i_4__5029), + .I1(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_req_h_o[4]), + .I2(plm_link_up_1), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_h_o_1_axb_4_4954) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_h_o_1_axb_3.INIT = 8'h6F; + LUT3_L com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_h_o_1_axb_3 ( + .I0(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_h_con_i_3__5028), + .I1(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_req_h_o[3]), + .I2(plm_link_up_1), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_h_o_1_axb_3_4955) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_h_o_1_axb_2.INIT = 8'h95; + LUT3_L com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_h_o_1_axb_2 ( + .I0(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_h_o_i_m3_i_m4_i_m3_i_m3_0_2__5046), + .I1(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_h_con[2]), + .I2(plm_link_up_1), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_h_o_1_axb_2_4956) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_h_o_1_axb_1.INIT = 8'h6F; + LUT3_L com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_h_o_1_axb_1 ( + .I0(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_h_con_i_1__5027), + .I1(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_req_h_o[1]), + .I2(plm_link_up_2), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_h_o_1_axb_1_4957) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_h_o_1_axb_0.INIT = 8'h95; + LUT3_L com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_h_o_1_axb_0 ( + .I0(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_h_o_i_m3_i_m4_i_m3_i_m3_0_0__5044), + .I1(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_h_con[0]), + .I2(plm_link_up_2), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_h_o_1_axb_0_4958) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_1_axb_11.INIT = 8'h9F; + LUT3_L com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_1_axb_11 ( + .I0(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_d_con[11]), + .I1(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_req_d_o[11]), + .I2(plm_link_up_2), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_1_axb_11_4959) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_1_axb_10.INIT = 8'h6F; + LUT3_L com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_1_axb_10 ( + .I0(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_d_con_i_10__5038), + .I1(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_req_d_o[10]), + .I2(plm_link_up_2), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_1_axb_10_4960) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_2_axb_11.INIT = 4'hB; + LUT2_L com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_2_axb_11 ( + .I0(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_req_d_o[11]), + .I1(plm_link_up_2), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_2_axb_11_4961) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_2_axb_10.INIT = 4'hB; + LUT2_L com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_2_axb_10 ( + .I0(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_req_d_o[10]), + .I1(plm_link_up_2), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_2_axb_10_4962) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_2_axb_9.INIT = 4'hB; + LUT2_L com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_2_axb_9 ( + .I0(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_req_d_o[9]), + .I1(plm_link_up_2), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_2_axb_9_4963) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_2_axb_8.INIT = 4'hB; + LUT2_L com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_2_axb_8 ( + .I0(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_req_d_o[8]), + .I1(plm_link_up_2), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_2_axb_8_4964) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_2_axb_7.INIT = 4'h8; + LUT2_L com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_2_axb_7 ( + .I0(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_req_d_o[7]), + .I1(plm_link_up_2), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_2_axb_7_4965) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_2_axb_6.INIT = 4'hB; + LUT2_L com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_2_axb_6 ( + .I0(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_req_d_o[6]), + .I1(plm_link_up_2), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_2_axb_6_4966) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_2_axb_5.INIT = 16'h7877; + LUT4_L com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_2_axb_5 ( + .I0(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_N_60525_1), + .I1(com_tlm_u_tlm_rx_fc_use_data[5]), + .I2(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_req_d_o[5]), + .I3(plm_link_up_2), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_2_axb_5_4967) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_2_axb_4.INIT = 16'h6A55; + LUT4_L com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_2_axb_4 ( + .I0(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_i_m3_i_m4_i_m3_i_m3_0_4__5053), + .I1(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_N_61398), + .I2(com_tlm_u_tlm_rx_fc_use_data[4]), + .I3(plm_link_up_2), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_2_axb_4_4968) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_2_axb_3.INIT = 16'h7877; + LUT4_L com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_2_axb_3 ( + .I0(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_N_60525_1), + .I1(com_tlm_u_tlm_rx_fc_use_data[3]), + .I2(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_req_d_o[3]), + .I3(plm_link_up_2), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_2_axb_3_4969) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_2_axb_2.INIT = 16'h7877; + LUT4_L com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_2_axb_2 ( + .I0(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_N_60525_1), + .I1(com_tlm_u_tlm_rx_fc_use_data[2]), + .I2(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_req_d_o[2]), + .I3(plm_link_up_2), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_2_axb_2_4970) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_2_axb_1.INIT = 16'h7877; + LUT4_L com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_2_axb_1 ( + .I0(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_N_60525_1), + .I1(com_tlm_u_tlm_rx_fc_use_data[1]), + .I2(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_req_d_o[1]), + .I3(plm_link_up_2), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_2_axb_1_4971) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_2_axb_0.INIT = 16'h6A55; + LUT4_L com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_2_axb_0 ( + .I0(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_i_m3_i_m4_i_m3_i_m3_0_0__5050), + .I1(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_N_61398), + .I2(com_tlm_u_tlm_rx_fc_use_data[0]), + .I3(plm_link_up_2), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_2_axb_0_4972) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_h_o_2_axb_7.INIT = 4'hB; + LUT2_L com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_h_o_2_axb_7 ( + .I0(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_req_h_o[7]), + .I1(plm_link_up_2), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_h_o_2_axb_7_4973) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_h_o_2_axb_6.INIT = 4'hB; + LUT2_L com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_h_o_2_axb_6 ( + .I0(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_req_h_o[6]), + .I1(plm_link_up_2), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_h_o_2_axb_6_4974) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_h_o_2_axb_5.INIT = 4'h8; + LUT2_L com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_h_o_2_axb_5 ( + .I0(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_req_h_o[5]), + .I1(plm_link_up_2), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_h_o_2_axb_5_4975) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_free_d_13_0_a2.INIT = 4'h8; + LUT2_L com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_free_d_13_0_a2 ( + .I0(com_tlm_u_tlm_rx_vc0_fc_free_1data), + .I1(com_tlm_u_tlm_rx_vc0_fc_free_cpl), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_free_d_13) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_free_h_13_0_a2.INIT = 4'h8; + LUT2_L com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_free_h_13_0_a2 ( + .I0(com_tlm_u_tlm_rx_vc0_fc_free_1header), + .I1(com_tlm_u_tlm_rx_vc0_fc_free_cpl), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_free_h_13) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_d_con_2_axb_11.INIT = 4'h2; + LUT1_L com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_d_con_2_axb_11 ( + .I0(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_d_con[11]), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_d_con_2_axb_11_4976) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_d_con_2_axb_10.INIT = 4'h2; + LUT1_L com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_d_con_2_axb_10 ( + .I0(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_d_con[10]), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_d_con_2_axb_10_4977) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_d_con_2_axb_9.INIT = 4'h2; + LUT1_L com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_d_con_2_axb_9 ( + .I0(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_d_con[9]), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_d_con_2_axb_9_4978) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_d_con_2_axb_8.INIT = 4'h2; + LUT1_L com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_d_con_2_axb_8 ( + .I0(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_d_con[8]), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_d_con_2_axb_8_4979) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_d_con_2_axb_7.INIT = 4'h2; + LUT1_L com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_d_con_2_axb_7 ( + .I0(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_d_con[7]), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_d_con_2_axb_7_4980) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_d_con_2_axb_6.INIT = 4'h2; + LUT1_L com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_d_con_2_axb_6 ( + .I0(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_d_con[6]), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_d_con_2_axb_6_4981) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_d_con_2_axb_5.INIT = 8'h78; + LUT3_L com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_d_con_2_axb_5 ( + .I0(com_tlm_u_tlm_rx_fc_use_cpl), + .I1(com_tlm_u_tlm_rx_fc_use_data[5]), + .I2(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_d_con[5]), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_d_con_2_axb_5_4982) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_d_con_2_axb_4.INIT = 8'h78; + LUT3_L com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_d_con_2_axb_4 ( + .I0(com_tlm_u_tlm_rx_fc_use_cpl), + .I1(com_tlm_u_tlm_rx_fc_use_data[4]), + .I2(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_d_con[4]), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_d_con_2_axb_4_4983) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_d_con_2_axb_3.INIT = 8'h78; + LUT3_L com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_d_con_2_axb_3 ( + .I0(com_tlm_u_tlm_rx_fc_use_cpl), + .I1(com_tlm_u_tlm_rx_fc_use_data[3]), + .I2(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_d_con[3]), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_d_con_2_axb_3_4984) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_d_con_2_axb_2.INIT = 8'h78; + LUT3_L com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_d_con_2_axb_2 ( + .I0(com_tlm_u_tlm_rx_fc_use_cpl), + .I1(com_tlm_u_tlm_rx_fc_use_data[2]), + .I2(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_d_con[2]), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_d_con_2_axb_2_4985) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_d_con_2_axb_1.INIT = 8'h78; + LUT3_L com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_d_con_2_axb_1 ( + .I0(com_tlm_u_tlm_rx_fc_use_cpl), + .I1(com_tlm_u_tlm_rx_fc_use_data[1]), + .I2(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_d_con[1]), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_d_con_2_axb_1_4986) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_N_10115_i.INIT = 4'hD; + LUT2 com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_N_10115_i ( + .I0(plm_link_up_1), + .I1(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_req_h_o[5]), + .O(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_N_10115_i_5048) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_unuse_d_0_a2_0_a2_0_a2_1_5_.INIT = 8'h80; + LUT3 com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_unuse_d_0_a2_0_a2_0_a2_1_5_ ( + .I0(plm_link_up_1), + .I1(com_tlm_u_tlm_rx_fc_use_cpl), + .I2(com_tlm_u_tlm_rx_fc_unuse), + .O(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_N_60525_1) + ); + FD com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_d_av_o_9_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_1_s_9_4987), + .Q(trn_rfc_cpld_av_6095[9]) + ); + FD com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_d_av_o_8_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_1_s_8_4988), + .Q(trn_rfc_cpld_av_6095[8]) + ); + FD com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_d_av_o_7_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_1_s_7_4989), + .Q(trn_rfc_cpld_av_6095[7]) + ); + FD com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_d_av_o_6_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_1_s_6_4990), + .Q(trn_rfc_cpld_av_6095[6]) + ); + FD com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_d_av_o_5_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_1_s_5_4991), + .Q(trn_rfc_cpld_av_6095[5]) + ); + FD com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_d_av_o_4_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_1_s_4_4992), + .Q(trn_rfc_cpld_av_6095[4]) + ); + FD com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_d_av_o_3_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_1_s_3_4993), + .Q(trn_rfc_cpld_av_6095[3]) + ); + FD com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_d_av_o_2_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_1_s_2_4994), + .Q(trn_rfc_cpld_av_6095[2]) + ); + FD com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_d_av_o_1_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_1_s_1_4995), + .Q(trn_rfc_cpld_av_6095[1]) + ); + FD com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_d_av_o_0_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_1_s_0_4996), + .Q(trn_rfc_cpld_av_6095[0]) + ); + FD com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_req_h_o_4_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_h_o_2_s_4_4997), + .Q(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_req_h_o[4]) + ); + FD com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_req_h_o_3_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_h_o_2_s_3_4998), + .Q(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_req_h_o[3]) + ); + FD com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_req_h_o_2_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_h_o_2_s_2_4999), + .Q(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_req_h_o[2]) + ); + FD com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_req_h_o_1_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_h_o_2_s_1_5000), + .Q(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_req_h_o[1]) + ); + FD com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_req_h_o_0_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_h_o_2_s_0_5001), + .Q(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_req_h_o[0]) + ); + FD com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_h_av_o_7_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_h_o_1_s_7_5002), + .Q(NlwRenamedSig_OI_trn_rfc_cplh_av[7]) + ); + FD com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_h_av_o_6_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_h_o_1_s_6_5003), + .Q(trn_rfc_cplh_av_6094[6]) + ); + FD com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_h_av_o_5_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_h_o_1_s_5_5004), + .Q(trn_rfc_cplh_av_6094[5]) + ); + FD com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_h_av_o_4_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_h_o_1_s_4_5005), + .Q(trn_rfc_cplh_av_6094[4]) + ); + FD com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_h_av_o_3_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_h_o_1_s_3_5006), + .Q(trn_rfc_cplh_av_6094[3]) + ); + FD com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_h_av_o_2_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_h_o_1_s_2_5007), + .Q(trn_rfc_cplh_av_6094[2]) + ); + FD com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_h_av_o_1_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_h_o_1_s_1_5008), + .Q(trn_rfc_cplh_av_6094[1]) + ); + FD com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_h_av_o_0_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_h_o_1_s_0_5009), + .Q(trn_rfc_cplh_av_6094[0]) + ); + FD com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_d_av_o_11_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_1_s_11_5010), + .Q(NlwRenamedSig_OI_trn_rfc_cpld_av[11]) + ); + FD com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_d_av_o_10_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_1_s_10_5011), + .Q(trn_rfc_cpld_av_6095[10]) + ); + FD com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_req_d_o_11_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_2_s_11_5012), + .Q(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_req_d_o[11]) + ); + FD com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_req_d_o_10_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_2_s_10_5013), + .Q(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_req_d_o[10]) + ); + FD com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_req_d_o_9_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_2_s_9_5014), + .Q(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_req_d_o[9]) + ); + FD com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_req_d_o_8_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_2_s_8_5015), + .Q(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_req_d_o[8]) + ); + FD com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_req_d_o_7_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_2_s_7_5016), + .Q(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_req_d_o[7]) + ); + FD com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_req_d_o_6_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_2_s_6_5017), + .Q(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_req_d_o[6]) + ); + FD com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_req_d_o_5_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_2_s_5_5018), + .Q(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_req_d_o[5]) + ); + FD com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_req_d_o_4_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_2_s_4_5019), + .Q(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_req_d_o[4]) + ); + FD com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_req_d_o_3_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_2_s_3_5020), + .Q(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_req_d_o[3]) + ); + FD com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_req_d_o_2_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_2_s_2_5021), + .Q(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_req_d_o[2]) + ); + FD com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_req_d_o_1_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_2_s_1_5022), + .Q(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_req_d_o[1]) + ); + FD com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_req_d_o_0_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_2_s_0_5023), + .Q(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_req_d_o[0]) + ); + FD com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_req_h_o_7_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_h_o_2_s_7_5024), + .Q(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_req_h_o[7]) + ); + FD com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_req_h_o_6_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_h_o_2_s_6_5025), + .Q(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_req_h_o[6]) + ); + FD com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_req_h_o_5_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_h_o_2_s_5_5026), + .Q(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_req_h_o[5]) + ); + INV com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_h_con_i_1_ ( + .I(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_h_con[1]), + .O(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_h_con_i_1__5027) + ); + INV com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_h_con_i_3_ ( + .I(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_h_con[3]), + .O(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_h_con_i_3__5028) + ); + INV com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_h_con_i_4_ ( + .I(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_h_con[4]), + .O(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_h_con_i_4__5029) + ); + INV com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_h_con_i_6_ ( + .I(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_h_con[6]), + .O(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_h_con_i_6__5030) + ); + INV com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_d_con_i_1_ ( + .I(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_d_con[1]), + .O(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_d_con_i_1__5031) + ); + INV com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_d_con_i_2_ ( + .I(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_d_con[2]), + .O(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_d_con_i_2__5032) + ); + INV com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_d_con_i_3_ ( + .I(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_d_con[3]), + .O(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_d_con_i_3__5033) + ); + INV com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_d_con_i_5_ ( + .I(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_d_con[5]), + .O(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_d_con_i_5__5034) + ); + INV com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_d_con_i_6_ ( + .I(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_d_con[6]), + .O(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_d_con_i_6__5035) + ); + INV com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_d_con_i_8_ ( + .I(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_d_con[8]), + .O(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_d_con_i_8__5036) + ); + INV com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_d_con_i_9_ ( + .I(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_d_con[9]), + .O(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_d_con_i_9__5037) + ); + INV com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_d_con_i_10_ ( + .I(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_d_con[10]), + .O(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_d_con_i_10__5038) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_h_con_qxu_0_0_.INIT = 4'h2; + LUT1_L com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_h_con_qxu_0_0_ ( + .I0(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_h_con[0]), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_h_con_qxu[0]) + ); + MULT_AND com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_1_cry_0_ma ( + .I0(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_i_m3_i_m4_i_m3_i_m3_0_0__5050), + .I1(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_VCC_5052), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_1_cry_0_ma_5039) + ); + MULT_AND com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_1_cry_4_ma ( + .I0(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_i_m3_i_m4_i_m3_i_m3_0_4__5053), + .I1(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_VCC_5052), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_1_cry_4_ma_5040) + ); + MULT_AND com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_1_cry_7_ma ( + .I0(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_N_10126_i_5042), + .I1(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_VCC_5052), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_1_cry_7_ma_5041) + ); + MULT_AND com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_h_o_1_cry_0_ma ( + .I0(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_h_o_i_m3_i_m4_i_m3_i_m3_0_0__5044), + .I1(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_VCC_5052), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_h_o_1_cry_0_ma_5043) + ); + MULT_AND com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_h_o_1_cry_2_ma ( + .I0(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_h_o_i_m3_i_m4_i_m3_i_m3_0_2__5046), + .I1(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_VCC_5052), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_h_o_1_cry_2_ma_5045) + ); + MULT_AND com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_h_o_1_cry_5_ma ( + .I0(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_N_10115_i_5048), + .I1(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_VCC_5052), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_h_o_1_cry_5_ma_5047) + ); + MULT_AND com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_2_cry_0_ma ( + .I0(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_i_m3_i_m4_i_m3_i_m3_0_0__5050), + .I1(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_VCC_5052), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_2_cry_0_ma_5049) + ); + MULT_AND com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_2_cry_4_ma ( + .I0(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_i_m3_i_m4_i_m3_i_m3_0_4__5053), + .I1(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_VCC_5052), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_un1_fc_req_d_o_2_cry_4_ma_5051) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_h_con_qxu_0_7_.INIT = 4'h2; + LUT1_L com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_h_con_qxu_0_7_ ( + .I0(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_h_con[7]), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_h_con_qxu[7]) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_h_con_qxu_0_6_.INIT = 4'h2; + LUT1_L com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_h_con_qxu_0_6_ ( + .I0(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_h_con[6]), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_h_con_qxu[6]) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_h_con_qxu_0_5_.INIT = 4'h2; + LUT1_L com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_h_con_qxu_0_5_ ( + .I0(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_h_con[5]), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_h_con_qxu[5]) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_h_con_qxu_0_4_.INIT = 4'h2; + LUT1_L com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_h_con_qxu_0_4_ ( + .I0(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_h_con[4]), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_h_con_qxu[4]) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_h_con_qxu_0_3_.INIT = 4'h2; + LUT1_L com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_h_con_qxu_0_3_ ( + .I0(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_h_con[3]), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_h_con_qxu[3]) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_h_con_qxu_0_2_.INIT = 4'h2; + LUT1_L com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_h_con_qxu_0_2_ ( + .I0(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_h_con[2]), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_h_con_qxu[2]) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_h_con_qxu_0_1_.INIT = 4'h2; + LUT1_L com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_h_con_qxu_0_1_ ( + .I0(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_h_con[1]), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_h_con_qxu[1]) + ); + defparam com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_h_con_s_0_.INIT = 4'h1; + LUT1_L com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_h_con_s_0_ ( + .I0(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_h_con_qxu[0]), + .LO(com_tlm_u_tlm_rx_vc0_flow_ctrl_completion_fc_h_con_s[0]) + ); + VCC com_tlm_u_tlm_rx_data_snk_VCC ( + .P(com_tlm_u_tlm_rx_data_snk_VCC_5140) + ); + GND com_tlm_u_tlm_rx_data_snk_GND ( + .G(com_tlm_u_tlm_rx_data_snk_GND_5139) + ); + FDR com_tlm_u_tlm_rx_data_snk_src_rdy_o ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_src_rdy_o_8), + .Q(com_tlm_u_tlm_rx_ds_src_rdy), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_rx_data_snk_stat_tlp_ep_o ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_stat_tlp_ep_o_5_5105), + .Q(com_cmmt_stat_tlp_rx_ep), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_rx_data_snk_stat_tlp_cpl_ur_o ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_stat_tlp_cpl_ur_o_5_5103), + .Q(com_cmmt_stat_tlp_rx_cpl_ur), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_rx_data_snk_stat_tlp_cpl_ep_o ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_stat_tlp_cpl_ep_o_5_5101), + .Q(com_cmmt_stat_tlp_rx_cpl_ep), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_rx_data_snk_stat_tlp_cpl_abort_o ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_stat_tlp_cpl_abort_o_5_5099), + .Q(com_cmmt_stat_tlp_rx_cpl_abort), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_rx_data_snk_dsc_o ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_dsc_o_5), + .Q(com_tlm_u_tlm_rx_ds_dsc), + .R(plm_link_up_i) + ); + FDRE com_tlm_u_tlm_rx_data_snk_cur_byte_ct_1dw_0_ ( + .CE(com_tlm_u_tlm_rx_data_snk_latch_2nd_dword), + .C(NlwRenamedSig_OI_trn_clk), + .D(N_85925_i_112), + .Q(com_tlm_u_tlm_rx_data_snk_cur_byte_ct_1dw[0]), + .R(plm_link_up_i) + ); + FDRE com_tlm_u_tlm_rx_data_snk_cur_byte_ct_1dw_1_ ( + .CE(com_tlm_u_tlm_rx_data_snk_latch_2nd_dword), + .C(NlwRenamedSig_OI_trn_clk), + .D(N_86751_i_113), + .Q(com_tlm_u_tlm_rx_data_snk_cur_byte_ct_1dw[1]), + .R(plm_link_up_i) + ); + FDRE com_tlm_u_tlm_rx_data_snk_cur_byte_ct_1dw_2_ ( + .CE(com_tlm_u_tlm_rx_data_snk_latch_2nd_dword), + .C(NlwRenamedSig_OI_trn_clk), + .D(N_56103_i), + .Q(com_tlm_u_tlm_rx_data_snk_cur_byte_ct_1dw[2]), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_rx_data_snk_fc_unuse_o ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_fc_unuse_o_5_5098), + .Q(com_tlm_u_tlm_rx_fc_unuse), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_rx_data_snk_cur_drop ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_next_cur_drop_5141), + .Q(com_tlm_u_tlm_rx_data_snk_cur_drop_5073), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_rx_data_snk_fc_use_p_o ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_fc_use_p_o_5_5097), + .Q(com_tlm_u_tlm_rx_fc_use_p), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_rx_data_snk_fc_use_np_o ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_fc_use_np_o_5_5096), + .Q(com_tlm_u_tlm_rx_fc_use_np), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_rx_data_snk_fc_use_cpl_o ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_fc_use_cpl_o_5_5095), + .Q(com_tlm_u_tlm_rx_fc_use_cpl), + .R(plm_link_up_i) + ); + FDRSE com_tlm_u_tlm_rx_data_snk_vc_hit_o ( + .CE(com_tlm_u_tlm_rx_data_snk_GND_5139), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_GND_5139), + .Q(com_lnk_tfc_vc_hit), + .R(plm_link_up_i), + .S(com_tlm_u_tlm_rx_wen_aux_oq_3) + ); + FDS com_tlm_u_tlm_rx_data_snk_rem_q_1_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_N_87127_i_5094), + .Q(com_tlm_u_tlm_rx_data_snk_rem_q_1__5136), + .S(plm_link_up_i) + ); + FDRE com_tlm_u_tlm_rx_data_snk_cur_first_be_adj_0_ ( + .CE(com_tlm_u_tlm_rx_data_snk_latch_2nd_dword), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_N_86752_i_5093), + .Q(com_tlm_u_tlm_rx_data_snk_cur_first_be_adj[0]), + .R(plm_link_up_i) + ); + FDRE com_tlm_u_tlm_rx_data_snk_cur_first_be_adj_1_ ( + .CE(com_tlm_u_tlm_rx_data_snk_latch_2nd_dword), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_N_17463_i), + .Q(com_tlm_u_tlm_rx_data_snk_cur_first_be_adj[1]), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_rx_data_snk_err_tlp_ur_o ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_err_tlp_ur_o_3_5092), + .Q(com_cmmt_err_tlp_ur), + .R(plm_link_up_i) + ); + FDRE com_tlm_u_tlm_rx_data_snk_remove_lastword ( + .CE(com_tlm_u_tlm_rx_data_snk_N_16531_i_5069), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_remove_lastword_6), + .Q(com_tlm_u_tlm_rx_data_snk_remove_lastword_5089), + .R(plm_link_up_i) + ); + FDRE com_tlm_u_tlm_rx_data_snk_cur_cpl_ur ( + .CE(com_tlm_u_tlm_rx_data_snk_latch_1st_dword_q2), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_cur_cpl_ur_6), + .Q(com_tlm_u_tlm_rx_data_snk_cur_cpl_ur_5104), + .R(plm_link_up_i) + ); + FDRE com_tlm_u_tlm_rx_data_snk_cur_cpl_abort ( + .CE(com_tlm_u_tlm_rx_data_snk_latch_1st_dword_q2), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_cur_cpl_abort_6), + .Q(com_tlm_u_tlm_rx_data_snk_cur_cpl_abort_5100), + .R(plm_link_up_i) + ); + FDS com_tlm_u_tlm_rx_data_snk_rem_o ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_rem_o_5), + .Q(com_tlm_u_tlm_rx_ds_rem), + .S(plm_link_up_i) + ); + FDR com_tlm_u_tlm_rx_data_snk_eof_o ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_eof_o_5), + .Q(com_tlm_u_tlm_rx_ds_eof), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_rx_data_snk_src_rdy_q_1_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_N_16426_i), + .Q(com_tlm_u_tlm_rx_data_snk_src_rdy_q_1__5138), + .R(plm_link_up_i) + ); + FDRE com_tlm_u_tlm_rx_data_snk_packet_ip ( + .CE(com_lnk_rsrc_rdy_n_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_N_16424_i), + .Q(com_tlm_u_tlm_rx_data_snk_packet_ip_5087), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_rx_data_snk_err_tlp_malformed_o ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_err_tlp_malformed_o_3_5088), + .Q(com_tlm_cmmt_err_tlp_malformed), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_rx_data_snk_eof_nd_q_1_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_eof_nd_q_3[1]), + .Q(com_tlm_u_tlm_rx_data_snk_eof_nd_q_1__5134), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_rx_data_snk_dsc_q_1_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_dsc_q_3[1]), + .Q(com_tlm_u_tlm_rx_data_snk_dsc_q_1__5137), + .R(plm_link_up_i) + ); + FDRE com_tlm_u_tlm_rx_data_snk_cur_cpl_ep ( + .CE(com_tlm_u_tlm_rx_data_snk_latch_1st_dword_q2), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_cur_cpl_ep_6), + .Q(com_tlm_u_tlm_rx_data_snk_cur_cpl_ep_5102), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_rx_data_snk_sof_q_1_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_sof_q_3[1]), + .Q(com_tlm_u_tlm_rx_data_snk_sof_q_1__5135), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_rx_data_snk_eof_q_1_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_N_56509_i), + .Q(com_tlm_u_tlm_rx_data_snk_eof_q_1__5112), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_rx_data_snk_sof_o ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_sof_q_5__5109), + .Q(com_tlm_u_tlm_rx_ds_sof), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_rx_data_snk_latch_1st_dword_q3 ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_latch_1st_dword_q2), + .Q(com_tlm_u_tlm_rx_data_snk_latch_1st_dword_q3_5054), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_rx_data_snk_err_tlp_p_o ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_ds_np_i_5086), + .Q(com_cmmt_err_tlp_p_cpl), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_rx_data_snk_latch_1st_dword_q4 ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_latch_1st_dword_q3_5054), + .Q(com_tlm_u_tlm_rx_data_snk_latch_1st_dword_q4_5124), + .R(plm_link_up_i) + ); + FDRE com_tlm_u_tlm_rx_data_snk_pwr_mgmt_mode_on ( + .CE(com_lnk_rsof_n_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmmt_ppm_suspend_req_n_i), + .Q(com_tlm_u_tlm_rx_data_snk_pwr_mgmt_mode_on_5055), + .R(plm_link_up_i) + ); + MUXCY_L com_tlm_u_tlm_rx_data_snk_un4_cur_byte_ct_cry_0 ( + .CI(com_tlm_u_tlm_rx_data_snk_GND_5139), + .DI(com_tlm_u_tlm_rx_data_snk_VCC_5140), + .LO(com_tlm_u_tlm_rx_data_snk_un4_cur_byte_ct_cry_0_5056), + .S(com_tlm_u_tlm_rx_data_snk_un4_cur_byte_ct_cry_0_sf_5152) + ); + MUXCY_L com_tlm_u_tlm_rx_data_snk_un4_cur_byte_ct_cry_1 ( + .CI(com_tlm_u_tlm_rx_data_snk_un4_cur_byte_ct_cry_0_5056), + .DI(com_tlm_u_tlm_rx_data_snk_GND_5139), + .LO(com_tlm_u_tlm_rx_data_snk_un4_cur_byte_ct_cry_1_5057), + .S(com_tlm_u_tlm_rx_data_snk_un4_cur_byte_ct_axb_1_5151) + ); + XORCY com_tlm_u_tlm_rx_data_snk_un4_cur_byte_ct_s_1 ( + .CI(com_tlm_u_tlm_rx_data_snk_un4_cur_byte_ct_cry_0_5056), + .LI(com_tlm_u_tlm_rx_data_snk_un4_cur_byte_ct_axb_1_5151), + .O(com_tlm_u_tlm_rx_data_snk_un4_cur_byte_ct_s_1_5075) + ); + MUXCY_L com_tlm_u_tlm_rx_data_snk_un4_cur_byte_ct_cry_2 ( + .CI(com_tlm_u_tlm_rx_data_snk_un4_cur_byte_ct_cry_1_5057), + .DI(com_tlm_u_tlm_rx_data_snk_cur_length_0__2), + .LO(com_tlm_u_tlm_rx_data_snk_un4_cur_byte_ct_cry_2_5058), + .S(com_tlm_u_tlm_rx_data_snk_un4_cur_byte_ct_axb_2_5150) + ); + XORCY com_tlm_u_tlm_rx_data_snk_un4_cur_byte_ct_s_2 ( + .CI(com_tlm_u_tlm_rx_data_snk_un4_cur_byte_ct_cry_1_5057), + .LI(com_tlm_u_tlm_rx_data_snk_un4_cur_byte_ct_axb_2_5150), + .O(com_tlm_u_tlm_rx_data_snk_un4_cur_byte_ct_s_2_5085) + ); + MUXCY_L com_tlm_u_tlm_rx_data_snk_un4_cur_byte_ct_cry_3 ( + .CI(com_tlm_u_tlm_rx_data_snk_un4_cur_byte_ct_cry_2_5058), + .DI(com_tlm_u_tlm_rx_data_snk_VCC_5140), + .LO(com_tlm_u_tlm_rx_data_snk_un4_cur_byte_ct_cry_3_5059), + .S(com_tlm_u_tlm_rx_data_snk_un4_cur_byte_ct_s_3_sf_5149) + ); + XORCY com_tlm_u_tlm_rx_data_snk_un4_cur_byte_ct_s_3 ( + .CI(com_tlm_u_tlm_rx_data_snk_un4_cur_byte_ct_cry_2_5058), + .LI(com_tlm_u_tlm_rx_data_snk_un4_cur_byte_ct_s_3_sf_5149), + .O(com_tlm_u_tlm_rx_data_snk_un4_cur_byte_ct_s_3_5084) + ); + MUXCY_L com_tlm_u_tlm_rx_data_snk_un4_cur_byte_ct_cry_4 ( + .CI(com_tlm_u_tlm_rx_data_snk_un4_cur_byte_ct_cry_3_5059), + .DI(com_tlm_u_tlm_rx_data_snk_VCC_5140), + .LO(com_tlm_u_tlm_rx_data_snk_un4_cur_byte_ct_cry_4_5060), + .S(com_tlm_u_tlm_rx_data_snk_un4_cur_byte_ct_s_4_sf_5148) + ); + XORCY com_tlm_u_tlm_rx_data_snk_un4_cur_byte_ct_s_4 ( + .CI(com_tlm_u_tlm_rx_data_snk_un4_cur_byte_ct_cry_3_5059), + .LI(com_tlm_u_tlm_rx_data_snk_un4_cur_byte_ct_s_4_sf_5148), + .O(com_tlm_u_tlm_rx_data_snk_un4_cur_byte_ct_s_4_5083) + ); + MUXCY_L com_tlm_u_tlm_rx_data_snk_un4_cur_byte_ct_cry_5 ( + .CI(com_tlm_u_tlm_rx_data_snk_un4_cur_byte_ct_cry_4_5060), + .DI(com_tlm_u_tlm_rx_data_snk_VCC_5140), + .LO(com_tlm_u_tlm_rx_data_snk_un4_cur_byte_ct_cry_5_5061), + .S(com_tlm_u_tlm_rx_data_snk_un4_cur_byte_ct_s_5_sf_5147) + ); + XORCY com_tlm_u_tlm_rx_data_snk_un4_cur_byte_ct_s_5 ( + .CI(com_tlm_u_tlm_rx_data_snk_un4_cur_byte_ct_cry_4_5060), + .LI(com_tlm_u_tlm_rx_data_snk_un4_cur_byte_ct_s_5_sf_5147), + .O(com_tlm_u_tlm_rx_data_snk_un4_cur_byte_ct_s_5_5082) + ); + MUXCY_L com_tlm_u_tlm_rx_data_snk_un4_cur_byte_ct_cry_6 ( + .CI(com_tlm_u_tlm_rx_data_snk_un4_cur_byte_ct_cry_5_5061), + .DI(com_tlm_u_tlm_rx_data_snk_VCC_5140), + .LO(com_tlm_u_tlm_rx_data_snk_un4_cur_byte_ct_cry_6_5062), + .S(com_tlm_u_tlm_rx_data_snk_un4_cur_byte_ct_s_6_sf_5146) + ); + XORCY com_tlm_u_tlm_rx_data_snk_un4_cur_byte_ct_s_6 ( + .CI(com_tlm_u_tlm_rx_data_snk_un4_cur_byte_ct_cry_5_5061), + .LI(com_tlm_u_tlm_rx_data_snk_un4_cur_byte_ct_s_6_sf_5146), + .O(com_tlm_u_tlm_rx_data_snk_un4_cur_byte_ct_s_6_5081) + ); + MUXCY_L com_tlm_u_tlm_rx_data_snk_un4_cur_byte_ct_cry_7 ( + .CI(com_tlm_u_tlm_rx_data_snk_un4_cur_byte_ct_cry_6_5062), + .DI(com_tlm_u_tlm_rx_data_snk_VCC_5140), + .LO(com_tlm_u_tlm_rx_data_snk_un4_cur_byte_ct_cry_7_5063), + .S(com_tlm_u_tlm_rx_data_snk_un4_cur_byte_ct_s_7_sf_5145) + ); + XORCY com_tlm_u_tlm_rx_data_snk_un4_cur_byte_ct_s_7 ( + .CI(com_tlm_u_tlm_rx_data_snk_un4_cur_byte_ct_cry_6_5062), + .LI(com_tlm_u_tlm_rx_data_snk_un4_cur_byte_ct_s_7_sf_5145), + .O(com_tlm_u_tlm_rx_data_snk_un4_cur_byte_ct_s_7_5080) + ); + MUXCY_L com_tlm_u_tlm_rx_data_snk_un4_cur_byte_ct_cry_8 ( + .CI(com_tlm_u_tlm_rx_data_snk_un4_cur_byte_ct_cry_7_5063), + .DI(com_tlm_u_tlm_rx_data_snk_VCC_5140), + .LO(com_tlm_u_tlm_rx_data_snk_un4_cur_byte_ct_cry_8_5064), + .S(com_tlm_u_tlm_rx_data_snk_un4_cur_byte_ct_s_8_sf_5144) + ); + XORCY com_tlm_u_tlm_rx_data_snk_un4_cur_byte_ct_s_8 ( + .CI(com_tlm_u_tlm_rx_data_snk_un4_cur_byte_ct_cry_7_5063), + .LI(com_tlm_u_tlm_rx_data_snk_un4_cur_byte_ct_s_8_sf_5144), + .O(com_tlm_u_tlm_rx_data_snk_un4_cur_byte_ct_s_8_5079) + ); + MUXCY_L com_tlm_u_tlm_rx_data_snk_un4_cur_byte_ct_cry_9 ( + .CI(com_tlm_u_tlm_rx_data_snk_un4_cur_byte_ct_cry_8_5064), + .DI(com_tlm_u_tlm_rx_data_snk_VCC_5140), + .LO(com_tlm_u_tlm_rx_data_snk_un4_cur_byte_ct_cry_9_5065), + .S(com_tlm_u_tlm_rx_data_snk_un4_cur_byte_ct_s_9_sf_5143) + ); + XORCY com_tlm_u_tlm_rx_data_snk_un4_cur_byte_ct_s_9 ( + .CI(com_tlm_u_tlm_rx_data_snk_un4_cur_byte_ct_cry_8_5064), + .LI(com_tlm_u_tlm_rx_data_snk_un4_cur_byte_ct_s_9_sf_5143), + .O(com_tlm_u_tlm_rx_data_snk_un4_cur_byte_ct_s_9_5078) + ); + MUXCY_L com_tlm_u_tlm_rx_data_snk_un4_cur_byte_ct_cry_10 ( + .CI(com_tlm_u_tlm_rx_data_snk_un4_cur_byte_ct_cry_9_5065), + .DI(com_tlm_u_tlm_rx_data_snk_VCC_5140), + .LO(com_tlm_u_tlm_rx_data_snk_un4_cur_byte_ct_cry_10_5066), + .S(com_tlm_u_tlm_rx_data_snk_un4_cur_byte_ct_s_10_sf_5142) + ); + XORCY com_tlm_u_tlm_rx_data_snk_un4_cur_byte_ct_s_10 ( + .CI(com_tlm_u_tlm_rx_data_snk_un4_cur_byte_ct_cry_9_5065), + .LI(com_tlm_u_tlm_rx_data_snk_un4_cur_byte_ct_s_10_sf_5142), + .O(com_tlm_u_tlm_rx_data_snk_un4_cur_byte_ct_s_10_5077) + ); + XORCY com_tlm_u_tlm_rx_data_snk_un4_cur_byte_ct_s_11 ( + .CI(com_tlm_u_tlm_rx_data_snk_un4_cur_byte_ct_cry_10_5066), + .LI(com_tlm_u_tlm_rx_data_snk_un4_cur_byte_ct_s_11_sf_5068), + .O(com_tlm_u_tlm_rx_data_snk_un4_cur_byte_ct_s_11_5076) + ); + FDR com_tlm_u_tlm_rx_data_snk_latch_1st_dword_q1 ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_latch_2nd_dword), + .Q(com_tlm_u_tlm_rx_data_snk_latch_1st_dword_q1_5067), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_rx_data_snk_bar_src_rdy_o ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_sof_q_4_), + .Q(com_tlm_u_tlm_rx_ds_bar_src_rdy), + .R(plm_link_up_i) + ); + defparam com_tlm_u_tlm_rx_data_snk_un1_eof_q_2_1.INIT = 4'h1; + LUT2 com_tlm_u_tlm_rx_data_snk_un1_eof_q_2_1 ( + .I0(com_tlm_u_tlm_rx_data_snk_malformed), + .I1(com_tlm_u_tlm_rx_data_snk_tlp_ur), + .O(com_tlm_u_tlm_rx_data_snk_un1_eof_q_2_1_5070) + ); + defparam com_tlm_u_tlm_rx_data_snk_un1_cur_fulltype_oh37_0_0_0_o3_0.INIT = 4'h1; + LUT2 com_tlm_u_tlm_rx_data_snk_un1_cur_fulltype_oh37_0_0_0_o3_0 ( + .I0(com_lnk_rd_6113[56]), + .I1(com_lnk_rd_6113[61]), + .O(com_tlm_u_tlm_rx_data_snk_N_56507_i) + ); + defparam com_tlm_u_tlm_rx_data_snk_cur_fulltype_mem12_0_0_0_o2.INIT = 4'h1; + LUT2 com_tlm_u_tlm_rx_data_snk_cur_fulltype_mem12_0_0_0_o2 ( + .I0(com_lnk_rd_6113[57]), + .I1(com_lnk_rd_6113[59]), + .O(com_tlm_u_tlm_rx_data_snk_N_56498_i) + ); + defparam com_tlm_u_tlm_rx_data_snk_un1_cur_fulltype_oh37_0_0_0_o3.INIT = 4'h1; + LUT2 com_tlm_u_tlm_rx_data_snk_un1_cur_fulltype_oh37_0_0_0_o3 ( + .I0(com_lnk_rd_6113[58]), + .I1(com_lnk_rd_6113[60]), + .O(com_tlm_u_tlm_rx_data_snk_N_56191_i) + ); + defparam com_tlm_u_tlm_rx_data_snk_cur_rem_0_sqmuxa_0_a2_0_a2_0_a2.INIT = 4'h4; + LUT2 com_tlm_u_tlm_rx_data_snk_cur_rem_0_sqmuxa_0_a2_0_a2_0_a2 ( + .I0(com_lnk_reof_n), + .I1(plm_link_up_1), + .O(com_tlm_u_tlm_rx_data_snk_cur_rem_0_sqmuxa) + ); + defparam com_tlm_u_tlm_rx_data_snk_packet_ip_3_i_0_0_a2.INIT = 4'h2; + LUT2 com_tlm_u_tlm_rx_data_snk_packet_ip_3_i_0_0_a2 ( + .I0(com_lnk_rsof_n), + .I1(com_tlm_u_tlm_rx_data_snk_packet_ip_5087), + .O(com_tlm_u_tlm_rx_data_snk_N_58441) + ); + defparam com_tlm_u_tlm_rx_data_snk_first_be_missing_0_0_0_a2_0_.INIT = 4'h4; + LUT2 com_tlm_u_tlm_rx_data_snk_first_be_missing_0_0_0_a2_0_ ( + .I0(com_lnk_rd[0]), + .I1(com_lnk_rd[1]), + .O(N_57268) + ); + defparam com_tlm_u_tlm_rx_data_snk_N_39425_i_0_o3.INIT = 4'h8; + LUT2 com_tlm_u_tlm_rx_data_snk_N_39425_i_0_o3 ( + .I0(com_lnk_rd[0]), + .I1(com_lnk_rd[3]), + .O(N_56103_i) + ); + defparam com_tlm_u_tlm_rx_data_snk_latch_1st_dword_q1c.INIT = 4'h1; + LUT2 com_tlm_u_tlm_rx_data_snk_latch_1st_dword_q1c ( + .I0(com_lnk_rsof_n), + .I1(com_lnk_rsrc_rdy_n), + .O(com_tlm_u_tlm_rx_data_snk_latch_2nd_dword) + ); + defparam com_tlm_u_tlm_rx_data_snk_un4_cur_byte_ct_s_11_sf.INIT = 4'h1; + LUT1 com_tlm_u_tlm_rx_data_snk_un4_cur_byte_ct_s_11_sf ( + .I0(com_tlm_u_tlm_rx_data_snk_cur_length_9__14), + .O(com_tlm_u_tlm_rx_data_snk_un4_cur_byte_ct_s_11_sf_5068) + ); + defparam com_tlm_u_tlm_rx_data_snk_N_16531_i.INIT = 4'hE; + LUT2 com_tlm_u_tlm_rx_data_snk_N_16531_i ( + .I0(com_tlm_u_tlm_rx_data_snk_eof_q_2__5113), + .I1(com_tlm_u_tlm_rx_ds_eof), + .O(com_tlm_u_tlm_rx_data_snk_N_16531_i_5069) + ); + defparam com_tlm_u_tlm_rx_data_snk_un1_cur_fulltype_oh37_0_0_0_o2.INIT = 8'h2A; + LUT3 com_tlm_u_tlm_rx_data_snk_un1_cur_fulltype_oh37_0_0_0_o2 ( + .I0(com_tlm_u_tlm_rx_data_snk_N_56191_i), + .I1(com_lnk_rd_6113[56]), + .I2(com_lnk_rd_6113[62]), + .O(com_tlm_u_tlm_rx_data_snk_N_56236_i) + ); + defparam com_tlm_u_tlm_rx_data_snk_last_be_missing_i_0_0_1_.INIT = 8'hA8; + LUT3 com_tlm_u_tlm_rx_data_snk_last_be_missing_i_0_0_1_ ( + .I0(com_tlm_u_tlm_rx_data_snk_N_56488_i), + .I1(com_lnk_rd[4]), + .I2(com_lnk_rd[5]), + .O(com_tlm_u_tlm_rx_data_snk_N_17291_i) + ); + defparam com_tlm_u_tlm_rx_data_snk_first_be_missing_i_0_0_1_.INIT = 16'h1110; + LUT4 com_tlm_u_tlm_rx_data_snk_first_be_missing_i_0_0_1_ ( + .I0(com_lnk_rd[0]), + .I1(com_lnk_rd[1]), + .I2(com_lnk_rd[2]), + .I3(com_lnk_rd[3]), + .O(com_tlm_u_tlm_rx_data_snk_N_17463_i) + ); + defparam com_tlm_u_tlm_rx_data_snk_un1_src_rdy_o_0_a2.INIT = 8'h40; + LUT3 com_tlm_u_tlm_rx_data_snk_un1_src_rdy_o_0_a2 ( + .I0(com_tlm_u_tlm_rx_ds_dsc), + .I1(com_tlm_u_tlm_rx_ds_eof), + .I2(com_tlm_u_tlm_rx_ds_src_rdy), + .O(com_tlm_u_tlm_rx_wen_aux_oq_3) + ); + defparam com_tlm_u_tlm_rx_data_snk_cur_length1_2_0_a2_0_a2_0_a2_0_a2_4.INIT = 16'h0001; + LUT4 com_tlm_u_tlm_rx_data_snk_cur_length1_2_0_a2_0_a2_0_a2_0_a2_4 ( + .I0(com_lnk_rd_6113[34]), + .I1(com_lnk_rd_6113[35]), + .I2(com_lnk_rd_6113[36]), + .I3(com_lnk_rd_6113[37]), + .O(com_tlm_u_tlm_rx_data_snk_cur_length1_2_0_a2_0_a2_0_a2_0_a2_4_5091) + ); + defparam com_tlm_u_tlm_rx_data_snk_cur_length1_2_0_a2_0_a2_0_a2_0_a2_5.INIT = 16'h0002; + LUT4_L com_tlm_u_tlm_rx_data_snk_cur_length1_2_0_a2_0_a2_0_a2_0_a2_5 ( + .I0(com_lnk_rd_6113[32]), + .I1(com_lnk_rd_6113[33]), + .I2(com_lnk_rd_6113[38]), + .I3(com_lnk_rd_6113[39]), + .LO(com_tlm_u_tlm_rx_data_snk_cur_length1_2_0_a2_0_a2_0_a2_0_a2_5_5090) + ); + defparam com_tlm_u_tlm_rx_data_snk_first_be_missing_0_0_0_0_.INIT = 16'h5455; + LUT4 com_tlm_u_tlm_rx_data_snk_first_be_missing_0_0_0_0_ ( + .I0(N_57268), + .I1(com_lnk_rd[0]), + .I2(com_lnk_rd[2]), + .I3(com_lnk_rd[3]), + .O(com_tlm_u_tlm_rx_data_snk_first_be_missing_0_0_0[0]) + ); + defparam com_tlm_u_tlm_rx_data_snk_last_be_missing_i_0_0_0_.INIT = 8'h0E; + LUT3 com_tlm_u_tlm_rx_data_snk_last_be_missing_i_0_0_0_ ( + .I0(com_tlm_u_tlm_rx_data_snk_N_56132_i), + .I1(com_lnk_rd[6]), + .I2(com_lnk_rd[7]), + .O(com_tlm_u_tlm_rx_data_snk_N_17289_i) + ); + defparam com_tlm_u_tlm_rx_data_snk_cur_fulltype_oh40_0_a2_0_a2_0_a2_1.INIT = 8'h08; + LUT3 com_tlm_u_tlm_rx_data_snk_cur_fulltype_oh40_0_a2_0_a2_0_a2_1 ( + .I0(com_tlm_u_tlm_rx_data_snk_N_56191_i), + .I1(com_lnk_rd_6113[57]), + .I2(com_lnk_rd_6113[61]), + .O(com_tlm_u_tlm_rx_data_snk_cur_fulltype_oh40_1) + ); + defparam com_tlm_u_tlm_rx_data_snk_next_cur_drop_2.INIT = 16'h0100; + LUT4 com_tlm_u_tlm_rx_data_snk_next_cur_drop_2 ( + .I0(com_tlm_u_tlm_rx_data_snk_cur_hp_msg_detect), + .I1(com_tlm_u_tlm_rx_data_snk_cur_pm_msg_detect), + .I2(com_tlm_u_tlm_rx_data_snk_tlp_uc), + .I3(com_tlm_u_tlm_rx_data_snk_un1_eof_q_2_1_5070), + .O(com_tlm_u_tlm_rx_data_snk_N_10631) + ); + defparam com_tlm_u_tlm_rx_data_snk_cur_byte_ct_6_1_a2_0_a2_0_a2_0_a3_1_3_.INIT = 8'h08; + LUT3 com_tlm_u_tlm_rx_data_snk_cur_byte_ct_6_1_a2_0_a2_0_a2_0_a3_1_3_ ( + .I0(com_tlm_u_tlm_rx_data_snk_N_56003_i), + .I1(com_tlm_u_tlm_rx_data_snk_N_56246_i), + .I2(com_tlm_u_tlm_rx_data_snk_cur_fulltype[6]), + .O(com_tlm_u_tlm_rx_data_snk_N_61370_1) + ); + defparam com_tlm_u_tlm_rx_data_snk_src_rdy_o_8_u_0_am.INIT = 8'h8C; + LUT3 com_tlm_u_tlm_rx_data_snk_src_rdy_o_8_u_0_am ( + .I0(com_tlm_u_tlm_rx_data_snk_sof_q_5__5109), + .I1(com_tlm_u_tlm_rx_data_snk_src_rdy_q_5__5115), + .I2(com_tlm_u_tlm_rx_ds_eof), + .O(com_tlm_u_tlm_rx_data_snk_src_rdy_o_8_u_0_am_5072) + ); + defparam com_tlm_u_tlm_rx_data_snk_src_rdy_o_8_u_0_bm.INIT = 8'h4C; + LUT3 com_tlm_u_tlm_rx_data_snk_src_rdy_o_8_u_0_bm ( + .I0(com_tlm_u_tlm_rx_data_snk_rem_q_4_), + .I1(com_tlm_u_tlm_rx_data_snk_src_rdy_q_4_), + .I2(com_tlm_u_tlm_rx_ds_eof), + .O(com_tlm_u_tlm_rx_data_snk_src_rdy_o_8_u_0_bm_5071) + ); + MUXF5 com_tlm_u_tlm_rx_data_snk_src_rdy_o_8_u_0 ( + .I0(com_tlm_u_tlm_rx_data_snk_src_rdy_o_8_u_0_am_5072), + .I1(com_tlm_u_tlm_rx_data_snk_src_rdy_o_8_u_0_bm_5071), + .O(com_tlm_u_tlm_rx_data_snk_src_rdy_o_8), + .S(com_tlm_u_tlm_rx_data_snk_remove_lastword_5089) + ); + defparam com_tlm_u_tlm_rx_data_snk_dsc_o_5_0_am.INIT = 8'hEC; + LUT3 com_tlm_u_tlm_rx_data_snk_dsc_o_5_0_am ( + .I0(com_tlm_u_tlm_rx_data_snk_cur_drop_5073), + .I1(com_tlm_u_tlm_rx_data_snk_dsc_q_5__5114), + .I2(com_tlm_u_tlm_rx_data_snk_eof_q_5__5111), + .O(com_tlm_u_tlm_rx_data_snk_dsc_o_5_0_am_5074) + ); + MUXF5 com_tlm_u_tlm_rx_data_snk_dsc_o_5_0 ( + .I0(com_tlm_u_tlm_rx_data_snk_dsc_o_5_0_am_5074), + .I1(com_tlm_u_tlm_rx_data_snk_dsc_o_5_0_bm_5106), + .O(com_tlm_u_tlm_rx_data_snk_dsc_o_5), + .S(com_tlm_u_tlm_rx_data_snk_remove_lastword_5089) + ); + defparam com_tlm_u_tlm_rx_data_snk_cur_byte_ct_6_2_a2_0_a2_0_a2_0_a2_1_.INIT = 16'h8A80; + LUT4_L com_tlm_u_tlm_rx_data_snk_cur_byte_ct_6_2_a2_0_a2_0_a2_0_a2_1_ ( + .I0(com_tlm_u_tlm_rx_data_snk_N_61370_1), + .I1(com_tlm_u_tlm_rx_data_snk_cur_byte_ct_1dw[1]), + .I2(com_tlm_u_tlm_rx_data_snk_cur_length1_5126), + .I3(com_tlm_u_tlm_rx_data_snk_un4_cur_byte_ct_s_1_5075), + .LO(com_tlm_u_tlm_rx_data_snk_cur_byte_ct_6_1_) + ); + defparam com_tlm_u_tlm_rx_data_snk_cur_byte_ct_6_2_a2_0_a2_0_a2_0_a2_0_.INIT = 16'h88A0; + LUT4_L com_tlm_u_tlm_rx_data_snk_cur_byte_ct_6_2_a2_0_a2_0_a2_0_a2_0_ ( + .I0(com_tlm_u_tlm_rx_data_snk_N_61370_1), + .I1(com_tlm_u_tlm_rx_data_snk_cur_byte_ct_1dw[0]), + .I2(com_tlm_u_tlm_rx_data_snk_cur_bytes_missing[0]), + .I3(com_tlm_u_tlm_rx_data_snk_cur_length1_5126), + .LO(com_tlm_u_tlm_rx_data_snk_cur_byte_ct_6_0_) + ); + defparam com_tlm_u_tlm_rx_data_snk_cur_bytes_missing_1_p4.INIT = 16'hC0E8; + LUT4_L com_tlm_u_tlm_rx_data_snk_cur_bytes_missing_1_p4 ( + .I0(com_tlm_u_tlm_rx_data_snk_N_17289_i), + .I1(com_tlm_u_tlm_rx_data_snk_N_17291_i), + .I2(com_tlm_u_tlm_rx_data_snk_N_17463_i), + .I3(com_tlm_u_tlm_rx_data_snk_first_be_missing_0_0_0[0]), + .LO(com_tlm_u_tlm_rx_data_snk_cur_bytes_missing_1[2]) + ); + defparam com_tlm_u_tlm_rx_data_snk_cur_bytes_missing_1_axbxc1.INIT = 16'h3C96; + LUT4_L com_tlm_u_tlm_rx_data_snk_cur_bytes_missing_1_axbxc1 ( + .I0(com_tlm_u_tlm_rx_data_snk_N_17289_i), + .I1(com_tlm_u_tlm_rx_data_snk_N_17291_i), + .I2(com_tlm_u_tlm_rx_data_snk_N_17463_i), + .I3(com_tlm_u_tlm_rx_data_snk_first_be_missing_0_0_0[0]), + .LO(com_tlm_u_tlm_rx_data_snk_cur_bytes_missing_1[1]) + ); + defparam com_tlm_u_tlm_rx_data_snk_cur_bytes_missing_1_axb0.INIT = 4'h9; + LUT2_L com_tlm_u_tlm_rx_data_snk_cur_bytes_missing_1_axb0 ( + .I0(com_tlm_u_tlm_rx_data_snk_N_17289_i), + .I1(com_tlm_u_tlm_rx_data_snk_first_be_missing_0_0_0[0]), + .LO(com_tlm_u_tlm_rx_data_snk_cur_bytes_missing_1_axb0_5107) + ); + defparam com_tlm_u_tlm_rx_data_snk_cur_byte_ct_6_1_a2_0_a2_0_a2_0_a2_11_.INIT = 8'h20; + LUT3_L com_tlm_u_tlm_rx_data_snk_cur_byte_ct_6_1_a2_0_a2_0_a2_0_a2_11_ ( + .I0(com_tlm_u_tlm_rx_data_snk_N_61370_1), + .I1(com_tlm_u_tlm_rx_data_snk_cur_length1_5126), + .I2(com_tlm_u_tlm_rx_data_snk_un4_cur_byte_ct_s_11_5076), + .LO(com_tlm_u_tlm_rx_data_snk_cur_byte_ct_6_11_) + ); + defparam com_tlm_u_tlm_rx_data_snk_cur_byte_ct_6_1_a2_0_a2_0_a2_0_a2_10_.INIT = 8'h20; + LUT3_L com_tlm_u_tlm_rx_data_snk_cur_byte_ct_6_1_a2_0_a2_0_a2_0_a2_10_ ( + .I0(com_tlm_u_tlm_rx_data_snk_N_61370_1), + .I1(com_tlm_u_tlm_rx_data_snk_cur_length1_5126), + .I2(com_tlm_u_tlm_rx_data_snk_un4_cur_byte_ct_s_10_5077), + .LO(com_tlm_u_tlm_rx_data_snk_cur_byte_ct_6_10_) + ); + defparam com_tlm_u_tlm_rx_data_snk_cur_byte_ct_6_1_a2_0_a2_0_a2_0_a2_9_.INIT = 8'h20; + LUT3_L com_tlm_u_tlm_rx_data_snk_cur_byte_ct_6_1_a2_0_a2_0_a2_0_a2_9_ ( + .I0(com_tlm_u_tlm_rx_data_snk_N_61370_1), + .I1(com_tlm_u_tlm_rx_data_snk_cur_length1_5126), + .I2(com_tlm_u_tlm_rx_data_snk_un4_cur_byte_ct_s_9_5078), + .LO(com_tlm_u_tlm_rx_data_snk_cur_byte_ct_6_9_) + ); + defparam com_tlm_u_tlm_rx_data_snk_cur_byte_ct_6_1_a2_0_a2_0_a2_0_a2_8_.INIT = 8'h20; + LUT3_L com_tlm_u_tlm_rx_data_snk_cur_byte_ct_6_1_a2_0_a2_0_a2_0_a2_8_ ( + .I0(com_tlm_u_tlm_rx_data_snk_N_61370_1), + .I1(com_tlm_u_tlm_rx_data_snk_cur_length1_5126), + .I2(com_tlm_u_tlm_rx_data_snk_un4_cur_byte_ct_s_8_5079), + .LO(com_tlm_u_tlm_rx_data_snk_cur_byte_ct_6_8_) + ); + defparam com_tlm_u_tlm_rx_data_snk_cur_byte_ct_6_1_a2_0_a2_0_a2_0_a2_7_.INIT = 8'h20; + LUT3_L com_tlm_u_tlm_rx_data_snk_cur_byte_ct_6_1_a2_0_a2_0_a2_0_a2_7_ ( + .I0(com_tlm_u_tlm_rx_data_snk_N_61370_1), + .I1(com_tlm_u_tlm_rx_data_snk_cur_length1_5126), + .I2(com_tlm_u_tlm_rx_data_snk_un4_cur_byte_ct_s_7_5080), + .LO(com_tlm_u_tlm_rx_data_snk_cur_byte_ct_6_7_) + ); + defparam com_tlm_u_tlm_rx_data_snk_cur_byte_ct_6_1_a2_0_a2_0_a2_0_a2_6_.INIT = 8'h20; + LUT3_L com_tlm_u_tlm_rx_data_snk_cur_byte_ct_6_1_a2_0_a2_0_a2_0_a2_6_ ( + .I0(com_tlm_u_tlm_rx_data_snk_N_61370_1), + .I1(com_tlm_u_tlm_rx_data_snk_cur_length1_5126), + .I2(com_tlm_u_tlm_rx_data_snk_un4_cur_byte_ct_s_6_5081), + .LO(com_tlm_u_tlm_rx_data_snk_cur_byte_ct_6_6_) + ); + defparam com_tlm_u_tlm_rx_data_snk_cur_byte_ct_6_1_a2_0_a2_0_a2_0_a2_5_.INIT = 8'h20; + LUT3_L com_tlm_u_tlm_rx_data_snk_cur_byte_ct_6_1_a2_0_a2_0_a2_0_a2_5_ ( + .I0(com_tlm_u_tlm_rx_data_snk_N_61370_1), + .I1(com_tlm_u_tlm_rx_data_snk_cur_length1_5126), + .I2(com_tlm_u_tlm_rx_data_snk_un4_cur_byte_ct_s_5_5082), + .LO(com_tlm_u_tlm_rx_data_snk_cur_byte_ct_6_5_) + ); + defparam com_tlm_u_tlm_rx_data_snk_cur_byte_ct_6_1_a2_0_a2_0_a2_0_a2_4_.INIT = 8'h20; + LUT3_L com_tlm_u_tlm_rx_data_snk_cur_byte_ct_6_1_a2_0_a2_0_a2_0_a2_4_ ( + .I0(com_tlm_u_tlm_rx_data_snk_N_61370_1), + .I1(com_tlm_u_tlm_rx_data_snk_cur_length1_5126), + .I2(com_tlm_u_tlm_rx_data_snk_un4_cur_byte_ct_s_4_5083), + .LO(com_tlm_u_tlm_rx_data_snk_cur_byte_ct_6_4_) + ); + defparam com_tlm_u_tlm_rx_data_snk_cur_byte_ct_6_1_a2_0_a2_0_a2_0_a2_3_.INIT = 8'h20; + LUT3_L com_tlm_u_tlm_rx_data_snk_cur_byte_ct_6_1_a2_0_a2_0_a2_0_a2_3_ ( + .I0(com_tlm_u_tlm_rx_data_snk_N_61370_1), + .I1(com_tlm_u_tlm_rx_data_snk_cur_length1_5126), + .I2(com_tlm_u_tlm_rx_data_snk_un4_cur_byte_ct_s_3_5084), + .LO(com_tlm_u_tlm_rx_data_snk_cur_byte_ct_6_3_) + ); + defparam com_tlm_u_tlm_rx_data_snk_N_59469_i.INIT = 16'hDFD5; + LUT4_L com_tlm_u_tlm_rx_data_snk_N_59469_i ( + .I0(com_tlm_u_tlm_rx_data_snk_N_61370_1), + .I1(com_tlm_u_tlm_rx_data_snk_cur_byte_ct_1dw[2]), + .I2(com_tlm_u_tlm_rx_data_snk_cur_length1_5126), + .I3(com_tlm_u_tlm_rx_data_snk_un4_cur_byte_ct_s_2_5085), + .LO(com_tlm_u_tlm_rx_data_snk_N_59469_i_5108) + ); + defparam com_tlm_u_tlm_rx_data_snk_ds_eof_i.INIT = 4'h1; + LUT1_L com_tlm_u_tlm_rx_data_snk_ds_eof_i ( + .I0(com_tlm_u_tlm_rx_ds_eof), + .LO(com_tlm_u_tlm_rx_ds_eof_i) + ); + defparam com_tlm_u_tlm_rx_data_snk_ds_np_i.INIT = 4'h1; + LUT1_L com_tlm_u_tlm_rx_data_snk_ds_np_i ( + .I0(com_tlm_u_tlm_rx_ds_np), + .LO(com_tlm_u_tlm_rx_data_snk_ds_np_i_5086) + ); + defparam com_tlm_u_tlm_rx_data_snk_sof_q_3_0_a2_0_a2_0_a2_1_.INIT = 4'h2; + LUT2_L com_tlm_u_tlm_rx_data_snk_sof_q_3_0_a2_0_a2_0_a2_1_ ( + .I0(com_tlm_u_tlm_rx_data_snk_latch_2nd_dword), + .I1(com_tlm_u_tlm_rx_data_snk_packet_ip_5087), + .LO(com_tlm_u_tlm_rx_data_snk_sof_q_3[1]) + ); + defparam com_tlm_u_tlm_rx_data_snk_cur_np_2_0_a2_0_a2_0_a2_0_a2.INIT = 8'h01; + LUT3_L com_tlm_u_tlm_rx_data_snk_cur_np_2_0_a2_0_a2_0_a2_0_a2 ( + .I0(com_tlm_u_tlm_rx_data_snk_cur_fulltype_oh_0__5133), + .I1(com_tlm_u_tlm_rx_data_snk_cur_fulltype_oh_1_), + .I2(com_tlm_u_tlm_rx_data_snk_cur_fulltype_oh_5__5131), + .LO(com_tlm_u_tlm_rx_data_snk_cur_np_2) + ); + defparam com_tlm_u_tlm_rx_data_snk_cur_tc0_2_0_a2_0_a2_0_a2.INIT = 8'h01; + LUT3_L com_tlm_u_tlm_rx_data_snk_cur_tc0_2_0_a2_0_a2_0_a2 ( + .I0(com_lnk_rd_6113[52]), + .I1(com_lnk_rd_6113[53]), + .I2(com_lnk_rd_6113[54]), + .LO(com_tlm_u_tlm_rx_data_snk_cur_tc0_2) + ); + defparam com_tlm_u_tlm_rx_data_snk_cur_cpl_ep_6_0_a2_0_a2_0_a2_0_a2.INIT = 4'h8; + LUT2_L com_tlm_u_tlm_rx_data_snk_cur_cpl_ep_6_0_a2_0_a2_0_a2_0_a2 ( + .I0(com_tlm_u_tlm_rx_data_snk_cur_ep_5118), + .I1(com_tlm_u_tlm_rx_data_snk_cur_fulltype_oh_0__5133), + .LO(com_tlm_u_tlm_rx_data_snk_cur_cpl_ep_6) + ); + defparam com_tlm_u_tlm_rx_data_snk_dsc_q_3_0_a2_0_a2_0_a2_0_a2_1_.INIT = 4'h2; + LUT2_L com_tlm_u_tlm_rx_data_snk_dsc_q_3_0_a2_0_a2_0_a2_0_a2_1_ ( + .I0(com_tlm_u_tlm_rx_data_snk_N_56509_i), + .I1(com_lnk_rsrc_dsc_n), + .LO(com_tlm_u_tlm_rx_data_snk_dsc_q_3[1]) + ); + defparam com_tlm_u_tlm_rx_data_snk_eof_nd_q_3_0_a2_0_a2_0_a2_0_a2_1_.INIT = 4'h8; + LUT2_L com_tlm_u_tlm_rx_data_snk_eof_nd_q_3_0_a2_0_a2_0_a2_0_a2_1_ ( + .I0(com_tlm_u_tlm_rx_data_snk_N_56509_i), + .I1(com_lnk_rsrc_dsc_n), + .LO(com_tlm_u_tlm_rx_data_snk_eof_nd_q_3[1]) + ); + defparam com_tlm_u_tlm_rx_data_snk_err_tlp_malformed_o_3.INIT = 4'h8; + LUT2_L com_tlm_u_tlm_rx_data_snk_err_tlp_malformed_o_3 ( + .I0(com_tlm_u_tlm_rx_data_snk_eof_nd_q_4_), + .I1(com_tlm_u_tlm_rx_data_snk_malformed), + .LO(com_tlm_u_tlm_rx_data_snk_err_tlp_malformed_o_3_5088) + ); + defparam com_tlm_u_tlm_rx_data_snk_cur_lower_addr_22_0_a3_0_a2_0_a2_1_.INIT = 4'h8; + LUT2_L com_tlm_u_tlm_rx_data_snk_cur_lower_addr_22_0_a3_0_a2_0_a2_1_ ( + .I0(com_tlm_u_tlm_rx_data_snk_cur_first_be_adj[1]), + .I1(com_tlm_u_tlm_rx_data_snk_cur_fulltype_mem_5128), + .LO(com_tlm_u_tlm_rx_data_snk_cur_lower_addr_22[1]) + ); + defparam com_tlm_u_tlm_rx_data_snk_cur_lower_addr_22_0_a3_0_a2_0_a2_0_.INIT = 4'h8; + LUT2_L com_tlm_u_tlm_rx_data_snk_cur_lower_addr_22_0_a3_0_a2_0_a2_0_ ( + .I0(com_tlm_u_tlm_rx_data_snk_cur_first_be_adj[0]), + .I1(com_tlm_u_tlm_rx_data_snk_cur_fulltype_mem_5128), + .LO(com_tlm_u_tlm_rx_data_snk_cur_lower_addr_22[0]) + ); + defparam com_tlm_u_tlm_rx_data_snk_packet_ip_3_i_0_0.INIT = 4'h4; + LUT2_L com_tlm_u_tlm_rx_data_snk_packet_ip_3_i_0_0 ( + .I0(com_tlm_u_tlm_rx_data_snk_N_58441), + .I1(com_lnk_reof_n), + .LO(com_tlm_u_tlm_rx_data_snk_N_16424_i) + ); + defparam com_tlm_u_tlm_rx_data_snk_src_rdy_q_3_i_0_0_1_.INIT = 4'h1; + LUT2_L com_tlm_u_tlm_rx_data_snk_src_rdy_q_3_i_0_0_1_ ( + .I0(com_tlm_u_tlm_rx_data_snk_N_58441), + .I1(com_lnk_rsrc_rdy_n), + .LO(com_tlm_u_tlm_rx_data_snk_N_16426_i) + ); + defparam com_tlm_u_tlm_rx_data_snk_eof_o_5_0.INIT = 8'hAC; + LUT3_L com_tlm_u_tlm_rx_data_snk_eof_o_5_0 ( + .I0(com_tlm_u_tlm_rx_data_snk_eof_o_3), + .I1(com_tlm_u_tlm_rx_data_snk_eof_q_5__5111), + .I2(com_tlm_u_tlm_rx_data_snk_remove_lastword_5089), + .LO(com_tlm_u_tlm_rx_data_snk_eof_o_5) + ); + defparam com_tlm_u_tlm_rx_data_snk_rem_o_5_0.INIT = 8'hAC; + LUT3_L com_tlm_u_tlm_rx_data_snk_rem_o_5_0 ( + .I0(com_tlm_u_tlm_rx_data_snk_rem_q_4_), + .I1(com_tlm_u_tlm_rx_data_snk_rem_q_5__5110), + .I2(com_tlm_u_tlm_rx_data_snk_remove_lastword_5089), + .LO(com_tlm_u_tlm_rx_data_snk_rem_o_5) + ); + defparam com_tlm_u_tlm_rx_data_snk_cur_cpl_abort_6_0_a2_0_a2_0_a2.INIT = 16'h0200; + LUT4_L com_tlm_u_tlm_rx_data_snk_cur_cpl_abort_6_0_a2_0_a2_0_a2 ( + .I0(com_tlm_u_tlm_rx_data_snk_cur_fulltype_oh_0__5133), + .I1(com_tlm_u_tlm_rx_data_snk_cur_tag[5]), + .I2(com_tlm_u_tlm_rx_data_snk_cur_tag[6]), + .I3(com_tlm_u_tlm_rx_data_snk_cur_tag[7]), + .LO(com_tlm_u_tlm_rx_data_snk_cur_cpl_abort_6) + ); + defparam com_tlm_u_tlm_rx_data_snk_cur_cpl_ur_6_0_a2_0_a2_0_a2.INIT = 16'h0008; + LUT4_L com_tlm_u_tlm_rx_data_snk_cur_cpl_ur_6_0_a2_0_a2_0_a2 ( + .I0(com_tlm_u_tlm_rx_data_snk_cur_fulltype_oh_0__5133), + .I1(com_tlm_u_tlm_rx_data_snk_cur_tag[5]), + .I2(com_tlm_u_tlm_rx_data_snk_cur_tag[6]), + .I3(com_tlm_u_tlm_rx_data_snk_cur_tag[7]), + .LO(com_tlm_u_tlm_rx_data_snk_cur_cpl_ur_6) + ); + defparam com_tlm_u_tlm_rx_data_snk_remove_lastword_6_0_a2_0_a2_0_a2_0_a2.INIT = 16'h2000; + LUT4_L com_tlm_u_tlm_rx_data_snk_remove_lastword_6_0_a2_0_a2_0_a2_0_a2 ( + .I0(cfg_cfg_6102[508]), + .I1(com_tlm_u_tlm_rx_data_snk_cur_rem_5120), + .I2(com_tlm_u_tlm_rx_data_snk_cur_td_q_5117), + .I3(com_tlm_u_tlm_rx_data_snk_eof_q_2__5113), + .LO(com_tlm_u_tlm_rx_data_snk_remove_lastword_6) + ); + defparam com_tlm_u_tlm_rx_data_snk_cur_length1_2_0_a2_0_a2_0_a2_0_a2.INIT = 16'h1000; + LUT4_L com_tlm_u_tlm_rx_data_snk_cur_length1_2_0_a2_0_a2_0_a2_0_a2 ( + .I0(com_lnk_rd_6113[40]), + .I1(com_lnk_rd_6113[41]), + .I2(com_tlm_u_tlm_rx_data_snk_cur_length1_2_0_a2_0_a2_0_a2_0_a2_4_5091), + .I3(com_tlm_u_tlm_rx_data_snk_cur_length1_2_0_a2_0_a2_0_a2_0_a2_5_5090), + .LO(com_tlm_u_tlm_rx_data_snk_cur_length1_2) + ); + defparam com_tlm_u_tlm_rx_data_snk_cur_fulltype_6412_0_0_0.INIT = 16'h0200; + LUT4_L com_tlm_u_tlm_rx_data_snk_cur_fulltype_6412_0_0_0 ( + .I0(com_tlm_u_tlm_rx_data_snk_N_56236_i), + .I1(com_lnk_rd_6113[57]), + .I2(com_lnk_rd_6113[59]), + .I3(com_lnk_rd_6113[61]), + .LO(com_tlm_u_tlm_rx_data_snk_N_10630_i) + ); + defparam com_tlm_u_tlm_rx_data_snk_err_tlp_ur_o_3.INIT = 8'h20; + LUT3_L com_tlm_u_tlm_rx_data_snk_err_tlp_ur_o_3 ( + .I0(com_tlm_u_tlm_rx_data_snk_eof_nd_q_4_), + .I1(com_tlm_u_tlm_rx_data_snk_malformed), + .I2(com_tlm_u_tlm_rx_data_snk_tlp_ur), + .LO(com_tlm_u_tlm_rx_data_snk_err_tlp_ur_o_3_5092) + ); + defparam com_tlm_u_tlm_rx_data_snk_N_86752_i.INIT = 4'h1; + LUT1_L com_tlm_u_tlm_rx_data_snk_N_86752_i ( + .I0(com_tlm_u_tlm_rx_data_snk_first_be_missing_0_0_0[0]), + .LO(com_tlm_u_tlm_rx_data_snk_N_86752_i_5093) + ); + defparam com_tlm_u_tlm_rx_data_snk_N_87127_i.INIT = 16'hDEFC; + LUT4_L com_tlm_u_tlm_rx_data_snk_N_87127_i ( + .I0(cfg_cfg_6102[508]), + .I1(com_lnk_reof_n), + .I2(com_lnk_rrem[0]), + .I3(com_tlm_u_tlm_rx_data_snk_cur_td_5119), + .LO(com_tlm_u_tlm_rx_data_snk_N_87127_i_5094) + ); + defparam com_tlm_u_tlm_rx_data_snk_fc_use_cpl_o_5.INIT = 8'h40; + LUT3_L com_tlm_u_tlm_rx_data_snk_fc_use_cpl_o_5 ( + .I0(com_tlm_u_tlm_rx_data_snk_dsc_q_4_), + .I1(com_tlm_u_tlm_rx_data_snk_eof_o_3), + .I2(com_tlm_u_tlm_rx_ds_cpl), + .LO(com_tlm_u_tlm_rx_data_snk_fc_use_cpl_o_5_5095) + ); + defparam com_tlm_u_tlm_rx_data_snk_fc_use_np_o_5.INIT = 8'h40; + LUT3_L com_tlm_u_tlm_rx_data_snk_fc_use_np_o_5 ( + .I0(com_tlm_u_tlm_rx_data_snk_dsc_q_4_), + .I1(com_tlm_u_tlm_rx_data_snk_eof_o_3), + .I2(com_tlm_u_tlm_rx_ds_np), + .LO(com_tlm_u_tlm_rx_data_snk_fc_use_np_o_5_5096) + ); + defparam com_tlm_u_tlm_rx_data_snk_fc_use_p_o_5.INIT = 16'h0004; + LUT4_L com_tlm_u_tlm_rx_data_snk_fc_use_p_o_5 ( + .I0(com_tlm_u_tlm_rx_data_snk_dsc_q_4_), + .I1(com_tlm_u_tlm_rx_data_snk_eof_o_3), + .I2(com_tlm_u_tlm_rx_ds_cpl), + .I3(com_tlm_u_tlm_rx_ds_np), + .LO(com_tlm_u_tlm_rx_data_snk_fc_use_p_o_5_5097) + ); + defparam com_tlm_u_tlm_rx_data_snk_cur_fulltype_mem12_0_0_0.INIT = 4'h8; + LUT2_L com_tlm_u_tlm_rx_data_snk_cur_fulltype_mem12_0_0_0 ( + .I0(com_tlm_u_tlm_rx_data_snk_N_56236_i), + .I1(com_tlm_u_tlm_rx_data_snk_N_56498_i), + .LO(com_tlm_u_tlm_rx_data_snk_cur_fulltype_mem12_i_i) + ); + defparam com_tlm_u_tlm_rx_data_snk_cur_lower_addr_15_i_0_0_6_.INIT = 16'hC840; + LUT4_L com_tlm_u_tlm_rx_data_snk_cur_lower_addr_15_i_0_0_6_ ( + .I0(com_tlm_u_tlm_rx_data_snk_cur_fulltype_64_5127), + .I1(com_tlm_u_tlm_rx_data_snk_cur_fulltype_mem_5128), + .I2(com_tlm_u_tlm_rx_data_snk_lower_addr32_in_q[6]), + .I3(com_tlm_u_tlm_rx_data_snk_lower_addr64_in_q[6]), + .LO(com_tlm_u_tlm_rx_data_snk_N_25253_i) + ); + defparam com_tlm_u_tlm_rx_data_snk_cur_lower_addr_15_i_0_0_5_.INIT = 16'hC840; + LUT4_L com_tlm_u_tlm_rx_data_snk_cur_lower_addr_15_i_0_0_5_ ( + .I0(com_tlm_u_tlm_rx_data_snk_cur_fulltype_64_5127), + .I1(com_tlm_u_tlm_rx_data_snk_cur_fulltype_mem_5128), + .I2(com_tlm_u_tlm_rx_data_snk_lower_addr32_in_q[5]), + .I3(com_tlm_u_tlm_rx_data_snk_lower_addr64_in_q[5]), + .LO(com_tlm_u_tlm_rx_data_snk_N_25251_i) + ); + defparam com_tlm_u_tlm_rx_data_snk_cur_lower_addr_15_i_0_0_4_.INIT = 16'hC840; + LUT4_L com_tlm_u_tlm_rx_data_snk_cur_lower_addr_15_i_0_0_4_ ( + .I0(com_tlm_u_tlm_rx_data_snk_cur_fulltype_64_5127), + .I1(com_tlm_u_tlm_rx_data_snk_cur_fulltype_mem_5128), + .I2(com_tlm_u_tlm_rx_data_snk_lower_addr32_in_q[4]), + .I3(com_tlm_u_tlm_rx_data_snk_lower_addr64_in_q[4]), + .LO(com_tlm_u_tlm_rx_data_snk_N_25249_i) + ); + defparam com_tlm_u_tlm_rx_data_snk_cur_lower_addr_15_i_0_0_3_.INIT = 16'hC840; + LUT4_L com_tlm_u_tlm_rx_data_snk_cur_lower_addr_15_i_0_0_3_ ( + .I0(com_tlm_u_tlm_rx_data_snk_cur_fulltype_64_5127), + .I1(com_tlm_u_tlm_rx_data_snk_cur_fulltype_mem_5128), + .I2(com_tlm_u_tlm_rx_data_snk_lower_addr32_in_q[3]), + .I3(com_tlm_u_tlm_rx_data_snk_lower_addr64_in_q[3]), + .LO(com_tlm_u_tlm_rx_data_snk_N_25247_i) + ); + defparam com_tlm_u_tlm_rx_data_snk_cur_lower_addr_15_i_0_0_2_.INIT = 16'hC840; + LUT4_L com_tlm_u_tlm_rx_data_snk_cur_lower_addr_15_i_0_0_2_ ( + .I0(com_tlm_u_tlm_rx_data_snk_cur_fulltype_64_5127), + .I1(com_tlm_u_tlm_rx_data_snk_cur_fulltype_mem_5128), + .I2(com_tlm_u_tlm_rx_data_snk_lower_addr32_in_q[2]), + .I3(com_tlm_u_tlm_rx_data_snk_lower_addr64_in_q[2]), + .LO(com_tlm_u_tlm_rx_data_snk_N_25245_i) + ); + defparam com_tlm_u_tlm_rx_data_snk_fc_unuse_o_5.INIT = 8'h10; + LUT3_L com_tlm_u_tlm_rx_data_snk_fc_unuse_o_5 ( + .I0(com_tlm_u_tlm_rx_data_snk_N_10631), + .I1(com_tlm_u_tlm_rx_data_snk_dsc_q_4_), + .I2(com_tlm_u_tlm_rx_data_snk_eof_o_3), + .LO(com_tlm_u_tlm_rx_data_snk_fc_unuse_o_5_5098) + ); + defparam com_tlm_u_tlm_rx_data_snk_un1_cur_fulltype_oh37_0_0_0.INIT = 16'h008A; + LUT4_L com_tlm_u_tlm_rx_data_snk_un1_cur_fulltype_oh37_0_0_0 ( + .I0(com_tlm_u_tlm_rx_data_snk_N_56236_i), + .I1(com_tlm_u_tlm_rx_data_snk_N_56507_i), + .I2(com_lnk_rd_6113[57]), + .I3(com_lnk_rd_6113[59]), + .LO(com_tlm_u_tlm_rx_data_snk_N_10626_i) + ); + defparam com_tlm_u_tlm_rx_data_snk_cur_fulltype_oh35_i_a2_0_a2_0_a2.INIT = 8'h20; + LUT3_L com_tlm_u_tlm_rx_data_snk_cur_fulltype_oh35_i_a2_0_a2_0_a2 ( + .I0(com_tlm_u_tlm_rx_data_snk_N_59435_1), + .I1(com_lnk_rd_6113[56]), + .I2(com_lnk_rd_6113[62]), + .LO(com_tlm_u_tlm_rx_data_snk_cur_fulltype_oh35_i_a2_0_a2_0_a2_5130) + ); + defparam com_tlm_u_tlm_rx_data_snk_cur_fulltype_oh40_0_a2_0_a2_0_a2.INIT = 4'h8; + LUT2_L com_tlm_u_tlm_rx_data_snk_cur_fulltype_oh40_0_a2_0_a2_0_a2 ( + .I0(com_lnk_rd_6113[59]), + .I1(com_tlm_u_tlm_rx_data_snk_cur_fulltype_oh40_1), + .LO(com_tlm_u_tlm_rx_data_snk_cur_fulltype_oh40) + ); + defparam com_tlm_u_tlm_rx_data_snk_stat_tlp_cpl_abort_o_5.INIT = 16'h0800; + LUT4_L com_tlm_u_tlm_rx_data_snk_stat_tlp_cpl_abort_o_5 ( + .I0(com_tlm_u_tlm_rx_data_snk_N_10631), + .I1(com_tlm_u_tlm_rx_data_snk_cur_cpl_abort_5100), + .I2(com_tlm_u_tlm_rx_data_snk_dsc_q_4_), + .I3(com_tlm_u_tlm_rx_data_snk_eof_o_3), + .LO(com_tlm_u_tlm_rx_data_snk_stat_tlp_cpl_abort_o_5_5099) + ); + defparam com_tlm_u_tlm_rx_data_snk_stat_tlp_cpl_ep_o_5.INIT = 16'h0800; + LUT4_L com_tlm_u_tlm_rx_data_snk_stat_tlp_cpl_ep_o_5 ( + .I0(com_tlm_u_tlm_rx_data_snk_N_10631), + .I1(com_tlm_u_tlm_rx_data_snk_cur_cpl_ep_5102), + .I2(com_tlm_u_tlm_rx_data_snk_dsc_q_4_), + .I3(com_tlm_u_tlm_rx_data_snk_eof_o_3), + .LO(com_tlm_u_tlm_rx_data_snk_stat_tlp_cpl_ep_o_5_5101) + ); + defparam com_tlm_u_tlm_rx_data_snk_stat_tlp_cpl_ur_o_5.INIT = 16'h0800; + LUT4_L com_tlm_u_tlm_rx_data_snk_stat_tlp_cpl_ur_o_5 ( + .I0(com_tlm_u_tlm_rx_data_snk_N_10631), + .I1(com_tlm_u_tlm_rx_data_snk_cur_cpl_ur_5104), + .I2(com_tlm_u_tlm_rx_data_snk_dsc_q_4_), + .I3(com_tlm_u_tlm_rx_data_snk_eof_o_3), + .LO(com_tlm_u_tlm_rx_data_snk_stat_tlp_cpl_ur_o_5_5103) + ); + defparam com_tlm_u_tlm_rx_data_snk_stat_tlp_ep_o_5.INIT = 16'h0800; + LUT4_L com_tlm_u_tlm_rx_data_snk_stat_tlp_ep_o_5 ( + .I0(com_tlm_u_tlm_rx_data_snk_N_10631), + .I1(com_tlm_u_tlm_rx_data_snk_cur_ep_q_5116), + .I2(com_tlm_u_tlm_rx_data_snk_dsc_q_4_), + .I3(com_tlm_u_tlm_rx_data_snk_eof_o_3), + .LO(com_tlm_u_tlm_rx_data_snk_stat_tlp_ep_o_5_5105) + ); + defparam com_tlm_u_tlm_rx_data_snk_d_mux_1_i_0_0_47_.INIT = 8'hC4; + LUT3_L com_tlm_u_tlm_rx_data_snk_d_mux_1_i_0_0_47_ ( + .I0(cfg_cfg_6102[508]), + .I1(com_lnk_rd_6113[47]), + .I2(com_lnk_rsof_n), + .LO(com_tlm_u_tlm_rx_data_snk_N_17287_i) + ); + defparam com_tlm_u_tlm_rx_data_snk_cur_fulltype_oh35_i_a2_0_a2_0_a2_1.INIT = 8'h02; + LUT3 com_tlm_u_tlm_rx_data_snk_cur_fulltype_oh35_i_a2_0_a2_0_a2_1 ( + .I0(com_tlm_u_tlm_rx_data_snk_N_56191_i), + .I1(com_lnk_rd_6113[59]), + .I2(com_lnk_rd_6113[57]), + .O(com_tlm_u_tlm_rx_data_snk_N_59435_1) + ); + defparam com_tlm_u_tlm_rx_data_snk_dsc_o_5_0_bm.INIT = 8'hAE; + LUT3 com_tlm_u_tlm_rx_data_snk_dsc_o_5_0_bm ( + .I0(com_tlm_u_tlm_rx_data_snk_dsc_q_4_), + .I1(com_tlm_u_tlm_rx_data_snk_eof_o_3), + .I2(com_tlm_u_tlm_rx_data_snk_N_10631), + .O(com_tlm_u_tlm_rx_data_snk_dsc_o_5_0_bm_5106) + ); + FD com_tlm_u_tlm_rx_data_snk_d_o_62_DOUT_0_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_d_o_62_N_6), + .Q(com_tlm_u_tlm_rx_ds_d[7]) + ); + FD com_tlm_u_tlm_rx_data_snk_d_o_61_DOUT_0_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_d_o_61_N_6), + .Q(com_tlm_u_tlm_rx_ds_d[6]) + ); + FD com_tlm_u_tlm_rx_data_snk_d_o_60_DOUT_0_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_d_o_60_N_6), + .Q(com_tlm_u_tlm_rx_ds_d[5]) + ); + FD com_tlm_u_tlm_rx_data_snk_d_o_59_DOUT_0_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_d_o_59_N_6), + .Q(com_tlm_u_tlm_rx_ds_d[4]) + ); + FD com_tlm_u_tlm_rx_data_snk_d_o_58_DOUT_0_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_d_o_58_N_6), + .Q(com_tlm_u_tlm_rx_ds_d[3]) + ); + FD com_tlm_u_tlm_rx_data_snk_d_o_57_DOUT_0_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_d_o_57_N_6), + .Q(com_tlm_u_tlm_rx_ds_d[2]) + ); + FD com_tlm_u_tlm_rx_data_snk_d_o_56_DOUT_0_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_d_o_56_N_6), + .Q(com_tlm_u_tlm_rx_ds_d[1]) + ); + FD com_tlm_u_tlm_rx_data_snk_d_o_55_DOUT_0_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_d_o_55_N_6), + .Q(com_tlm_u_tlm_rx_ds_d[0]) + ); + FD com_tlm_u_tlm_rx_data_snk_d_o_54_DOUT_0_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_d_o_54_N_6), + .Q(com_tlm_u_tlm_rx_ds_d[22]) + ); + FD com_tlm_u_tlm_rx_data_snk_d_o_53_DOUT_0_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_d_o_53_N_6), + .Q(com_tlm_u_tlm_rx_ds_d[21]) + ); + FD com_tlm_u_tlm_rx_data_snk_d_o_52_DOUT_0_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_d_o_52_N_6), + .Q(com_tlm_u_tlm_rx_ds_d[20]) + ); + FD com_tlm_u_tlm_rx_data_snk_d_o_51_DOUT_0_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_d_o_51_N_6), + .Q(com_tlm_u_tlm_rx_ds_d[19]) + ); + FD com_tlm_u_tlm_rx_data_snk_d_o_50_DOUT_0_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_d_o_50_N_6), + .Q(com_tlm_u_tlm_rx_ds_d[18]) + ); + FD com_tlm_u_tlm_rx_data_snk_d_o_49_DOUT_0_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_d_o_49_N_6), + .Q(com_tlm_u_tlm_rx_ds_d[17]) + ); + FD com_tlm_u_tlm_rx_data_snk_d_o_48_DOUT_0_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_d_o_48_N_6), + .Q(com_tlm_u_tlm_rx_ds_d[16]) + ); + FD com_tlm_u_tlm_rx_data_snk_d_o_47_DOUT_0_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_d_o_47_N_6), + .Q(com_tlm_u_tlm_rx_ds_d[15]) + ); + FD com_tlm_u_tlm_rx_data_snk_d_o_46_DOUT_0_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_d_o_46_N_6), + .Q(com_tlm_u_tlm_rx_ds_d[14]) + ); + FD com_tlm_u_tlm_rx_data_snk_d_o_45_DOUT_0_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_d_o_45_N_6), + .Q(com_tlm_u_tlm_rx_ds_d[13]) + ); + FD com_tlm_u_tlm_rx_data_snk_d_o_44_DOUT_0_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_d_o_44_N_6), + .Q(com_tlm_u_tlm_rx_ds_d[12]) + ); + FD com_tlm_u_tlm_rx_data_snk_d_o_43_DOUT_0_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_d_o_43_N_6), + .Q(com_tlm_u_tlm_rx_ds_d[11]) + ); + FD com_tlm_u_tlm_rx_data_snk_d_o_42_DOUT_0_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_d_o_42_N_6), + .Q(com_tlm_u_tlm_rx_ds_d[10]) + ); + FD com_tlm_u_tlm_rx_data_snk_d_o_41_DOUT_0_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_d_o_41_N_6), + .Q(com_tlm_u_tlm_rx_ds_d[9]) + ); + FD com_tlm_u_tlm_rx_data_snk_d_o_40_DOUT_0_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_d_o_40_N_6), + .Q(com_tlm_u_tlm_rx_ds_d[8]) + ); + FD com_tlm_u_tlm_rx_data_snk_d_o_39_DOUT_0_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_d_o_39_N_6), + .Q(com_tlm_u_tlm_rx_ds_d[37]) + ); + FD com_tlm_u_tlm_rx_data_snk_d_o_38_DOUT_0_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_d_o_38_N_6), + .Q(com_tlm_u_tlm_rx_ds_d[36]) + ); + FD com_tlm_u_tlm_rx_data_snk_d_o_37_DOUT_0_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_d_o_37_N_6), + .Q(com_tlm_u_tlm_rx_ds_d[35]) + ); + FD com_tlm_u_tlm_rx_data_snk_d_o_36_DOUT_0_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_d_o_36_N_6), + .Q(com_tlm_u_tlm_rx_ds_d[34]) + ); + FD com_tlm_u_tlm_rx_data_snk_d_o_35_DOUT_0_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_d_o_35_N_6), + .Q(com_tlm_u_tlm_rx_ds_d[33]) + ); + FD com_tlm_u_tlm_rx_data_snk_d_o_34_DOUT_0_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_d_o_34_N_6), + .Q(com_tlm_u_tlm_rx_ds_d[32]) + ); + FD com_tlm_u_tlm_rx_data_snk_d_o_33_DOUT_0_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_d_o_33_N_6), + .Q(com_tlm_u_tlm_rx_ds_d[31]) + ); + FD com_tlm_u_tlm_rx_data_snk_d_o_32_DOUT_0_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_d_o_32_N_6), + .Q(com_tlm_u_tlm_rx_ds_d[30]) + ); + FD com_tlm_u_tlm_rx_data_snk_d_o_31_DOUT_0_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_d_o_31_N_6), + .Q(com_tlm_u_tlm_rx_ds_d[29]) + ); + FD com_tlm_u_tlm_rx_data_snk_d_o_30_DOUT_0_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_d_o_30_N_6), + .Q(com_tlm_u_tlm_rx_ds_d[28]) + ); + FD com_tlm_u_tlm_rx_data_snk_d_o_29_DOUT_0_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_d_o_29_N_6), + .Q(com_tlm_u_tlm_rx_ds_d[27]) + ); + FD com_tlm_u_tlm_rx_data_snk_d_o_28_DOUT_0_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_d_o_28_N_6), + .Q(com_tlm_u_tlm_rx_ds_d[26]) + ); + FD com_tlm_u_tlm_rx_data_snk_d_o_27_DOUT_0_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_d_o_27_N_6), + .Q(com_tlm_u_tlm_rx_ds_d[25]) + ); + FD com_tlm_u_tlm_rx_data_snk_d_o_26_DOUT_0_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_d_o_26_N_6), + .Q(com_tlm_u_tlm_rx_ds_d[24]) + ); + FD com_tlm_u_tlm_rx_data_snk_d_o_25_DOUT_0_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_d_o_25_N_6), + .Q(com_tlm_u_tlm_rx_ds_d[23]) + ); + FD com_tlm_u_tlm_rx_data_snk_d_o_24_DOUT_0_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_d_o_24_N_6), + .Q(com_tlm_u_tlm_rx_ds_d[52]) + ); + FD com_tlm_u_tlm_rx_data_snk_d_o_23_DOUT_0_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_d_o_23_N_6), + .Q(com_tlm_u_tlm_rx_ds_d[51]) + ); + FD com_tlm_u_tlm_rx_data_snk_d_o_22_DOUT_0_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_d_o_22_N_6), + .Q(com_tlm_u_tlm_rx_ds_d[50]) + ); + FD com_tlm_u_tlm_rx_data_snk_d_o_21_DOUT_0_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_d_o_21_N_6), + .Q(com_tlm_u_tlm_rx_ds_d[49]) + ); + FD com_tlm_u_tlm_rx_data_snk_d_o_20_DOUT_0_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_d_o_20_N_6), + .Q(com_tlm_u_tlm_rx_ds_d[48]) + ); + FD com_tlm_u_tlm_rx_data_snk_d_o_19_DOUT_0_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_d_o_19_N_6), + .Q(com_tlm_u_tlm_rx_ds_d[47]) + ); + FD com_tlm_u_tlm_rx_data_snk_d_o_18_DOUT_0_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_d_o_18_N_6), + .Q(com_tlm_u_tlm_rx_ds_d[46]) + ); + FD com_tlm_u_tlm_rx_data_snk_d_o_17_DOUT_0_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_d_o_17_N_6), + .Q(com_tlm_u_tlm_rx_ds_d[45]) + ); + FD com_tlm_u_tlm_rx_data_snk_d_o_16_DOUT_0_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_d_o_16_N_6), + .Q(com_tlm_u_tlm_rx_ds_d[44]) + ); + FD com_tlm_u_tlm_rx_data_snk_d_o_15_DOUT_0_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_d_o_15_N_6), + .Q(com_tlm_u_tlm_rx_ds_d[43]) + ); + FD com_tlm_u_tlm_rx_data_snk_d_o_14_DOUT_0_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_d_o_14_N_6), + .Q(com_tlm_u_tlm_rx_ds_d[42]) + ); + FD com_tlm_u_tlm_rx_data_snk_d_o_13_DOUT_0_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_d_o_13_N_6), + .Q(com_tlm_u_tlm_rx_ds_d[41]) + ); + FD com_tlm_u_tlm_rx_data_snk_d_o_12_DOUT_0_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_d_o_12_N_6), + .Q(com_tlm_u_tlm_rx_ds_d[40]) + ); + FD com_tlm_u_tlm_rx_data_snk_d_o_11_DOUT_0_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_d_o_11_N_6), + .Q(com_tlm_u_tlm_rx_ds_d[39]) + ); + FD com_tlm_u_tlm_rx_data_snk_d_o_10_DOUT_0_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_d_o_10_N_6), + .Q(com_tlm_u_tlm_rx_ds_d[38]) + ); + FD com_tlm_u_tlm_rx_data_snk_eof_nd_q_DOUT_0_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_eof_nd_q_N_6), + .Q(com_tlm_u_tlm_rx_data_snk_eof_nd_q_4_) + ); + FD com_tlm_u_tlm_rx_data_snk_d_o_9_DOUT_0_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_d_o_9_N_6), + .Q(com_tlm_u_tlm_rx_ds_d[63]) + ); + FD com_tlm_u_tlm_rx_data_snk_d_o_8_DOUT_0_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_d_o_8_N_6), + .Q(com_tlm_u_tlm_rx_ds_d[62]) + ); + FD com_tlm_u_tlm_rx_data_snk_d_o_7_DOUT_0_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_d_o_7_N_6), + .Q(com_tlm_u_tlm_rx_ds_d[61]) + ); + FD com_tlm_u_tlm_rx_data_snk_d_o_6_DOUT_0_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_d_o_6_N_6), + .Q(com_tlm_u_tlm_rx_ds_d[60]) + ); + FD com_tlm_u_tlm_rx_data_snk_d_o_5_DOUT_0_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_d_o_5_N_6), + .Q(com_tlm_u_tlm_rx_ds_d[59]) + ); + FD com_tlm_u_tlm_rx_data_snk_d_o_4_DOUT_0_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_d_o_4_N_6), + .Q(com_tlm_u_tlm_rx_ds_d[58]) + ); + FD com_tlm_u_tlm_rx_data_snk_d_o_3_DOUT_0_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_d_o_3_N_6), + .Q(com_tlm_u_tlm_rx_ds_d[57]) + ); + FD com_tlm_u_tlm_rx_data_snk_d_o_2_DOUT_0_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_d_o_2_N_6), + .Q(com_tlm_u_tlm_rx_ds_d[56]) + ); + FD com_tlm_u_tlm_rx_data_snk_d_o_1_DOUT_0_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_d_o_1_N_6), + .Q(com_tlm_u_tlm_rx_ds_d[55]) + ); + FD com_tlm_u_tlm_rx_data_snk_d_o_0_DOUT_0_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_d_o_0_N_6), + .Q(com_tlm_u_tlm_rx_ds_d[54]) + ); + FD com_tlm_u_tlm_rx_data_snk_d_o_DOUT_0_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_d_o_N_6), + .Q(com_tlm_u_tlm_rx_ds_d[53]) + ); + FD com_tlm_u_tlm_rx_data_snk_sof_q_DOUT_0_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_sof_q_N_6), + .Q(com_tlm_u_tlm_rx_data_snk_sof_q_4_) + ); + FD com_tlm_u_tlm_rx_data_snk_rem_q_DOUT_0_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_rem_q_N_6), + .Q(com_tlm_u_tlm_rx_data_snk_rem_q_4_) + ); + FD com_tlm_u_tlm_rx_data_snk_dsc_q_DOUT_0_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_dsc_q_N_6), + .Q(com_tlm_u_tlm_rx_data_snk_dsc_q_4_) + ); + FD com_tlm_u_tlm_rx_data_snk_src_rdy_q_DOUT_0_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_src_rdy_q_N_6), + .Q(com_tlm_u_tlm_rx_data_snk_src_rdy_q_4_) + ); + FDE com_tlm_u_tlm_rx_data_snk_cur_byte_ct_1_ ( + .CE(com_tlm_u_tlm_rx_data_snk_latch_1st_dword_q2), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_cur_byte_ct_6_1_), + .Q(com_tlm_u_tlm_rx_data_snk_cur_byte_ct[1]) + ); + FDE com_tlm_u_tlm_rx_data_snk_cur_byte_ct_0_ ( + .CE(com_tlm_u_tlm_rx_data_snk_latch_1st_dword_q2), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_cur_byte_ct_6_0_), + .Q(com_tlm_u_tlm_rx_data_snk_cur_byte_ct[0]) + ); + FDE com_tlm_u_tlm_rx_data_snk_cur_bytes_missing_2_ ( + .CE(com_tlm_u_tlm_rx_data_snk_latch_2nd_dword), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_cur_bytes_missing_1[2]), + .Q(com_tlm_u_tlm_rx_data_snk_cur_bytes_missing[2]) + ); + FDE com_tlm_u_tlm_rx_data_snk_cur_bytes_missing_1_ ( + .CE(com_tlm_u_tlm_rx_data_snk_latch_2nd_dword), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_cur_bytes_missing_1[1]), + .Q(com_tlm_u_tlm_rx_data_snk_cur_bytes_missing[1]) + ); + FDE com_tlm_u_tlm_rx_data_snk_cur_bytes_missing_0_ ( + .CE(com_tlm_u_tlm_rx_data_snk_latch_2nd_dword), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_cur_bytes_missing_1_axb0_5107), + .Q(com_tlm_u_tlm_rx_data_snk_cur_bytes_missing[0]) + ); + FDE com_tlm_u_tlm_rx_data_snk_cur_byte_ct_11_ ( + .CE(com_tlm_u_tlm_rx_data_snk_latch_1st_dword_q2), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_cur_byte_ct_6_11_), + .Q(com_tlm_u_tlm_rx_data_snk_cur_byte_ct[11]) + ); + FDE com_tlm_u_tlm_rx_data_snk_cur_byte_ct_10_ ( + .CE(com_tlm_u_tlm_rx_data_snk_latch_1st_dword_q2), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_cur_byte_ct_6_10_), + .Q(com_tlm_u_tlm_rx_data_snk_cur_byte_ct[10]) + ); + FDE com_tlm_u_tlm_rx_data_snk_cur_byte_ct_9_ ( + .CE(com_tlm_u_tlm_rx_data_snk_latch_1st_dword_q2), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_cur_byte_ct_6_9_), + .Q(com_tlm_u_tlm_rx_data_snk_cur_byte_ct[9]) + ); + FDE com_tlm_u_tlm_rx_data_snk_cur_byte_ct_8_ ( + .CE(com_tlm_u_tlm_rx_data_snk_latch_1st_dword_q2), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_cur_byte_ct_6_8_), + .Q(com_tlm_u_tlm_rx_data_snk_cur_byte_ct[8]) + ); + FDE com_tlm_u_tlm_rx_data_snk_cur_byte_ct_7_ ( + .CE(com_tlm_u_tlm_rx_data_snk_latch_1st_dword_q2), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_cur_byte_ct_6_7_), + .Q(com_tlm_u_tlm_rx_data_snk_cur_byte_ct[7]) + ); + FDE com_tlm_u_tlm_rx_data_snk_cur_byte_ct_6_ ( + .CE(com_tlm_u_tlm_rx_data_snk_latch_1st_dword_q2), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_cur_byte_ct_6_6_), + .Q(com_tlm_u_tlm_rx_data_snk_cur_byte_ct[6]) + ); + FDE com_tlm_u_tlm_rx_data_snk_cur_byte_ct_5_ ( + .CE(com_tlm_u_tlm_rx_data_snk_latch_1st_dword_q2), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_cur_byte_ct_6_5_), + .Q(com_tlm_u_tlm_rx_data_snk_cur_byte_ct[5]) + ); + FDE com_tlm_u_tlm_rx_data_snk_cur_byte_ct_4_ ( + .CE(com_tlm_u_tlm_rx_data_snk_latch_1st_dword_q2), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_cur_byte_ct_6_4_), + .Q(com_tlm_u_tlm_rx_data_snk_cur_byte_ct[4]) + ); + FDE com_tlm_u_tlm_rx_data_snk_cur_byte_ct_3_ ( + .CE(com_tlm_u_tlm_rx_data_snk_latch_1st_dword_q2), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_cur_byte_ct_6_3_), + .Q(com_tlm_u_tlm_rx_data_snk_cur_byte_ct[3]) + ); + FDE com_tlm_u_tlm_rx_data_snk_cur_byte_ct_2_ ( + .CE(com_tlm_u_tlm_rx_data_snk_latch_1st_dword_q2), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_N_59469_i_5108), + .Q(com_tlm_u_tlm_rx_data_snk_cur_byte_ct[2]) + ); + FD com_tlm_u_tlm_rx_data_snk_sof_q_5_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_sof_q_4_), + .Q(com_tlm_u_tlm_rx_data_snk_sof_q_5__5109) + ); + FD com_tlm_u_tlm_rx_data_snk_rem_q_5_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_rem_q_4_), + .Q(com_tlm_u_tlm_rx_data_snk_rem_q_5__5110) + ); + FD com_tlm_u_tlm_rx_data_snk_eof_q_5_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_eof_o_3), + .Q(com_tlm_u_tlm_rx_data_snk_eof_q_5__5111) + ); + FD com_tlm_u_tlm_rx_data_snk_eof_q_4_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_eof_q_3__5122), + .Q(com_tlm_u_tlm_rx_data_snk_eof_o_3) + ); + FD com_tlm_u_tlm_rx_data_snk_eof_q_3_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_eof_q_2__5113), + .Q(com_tlm_u_tlm_rx_data_snk_eof_q_3__5122) + ); + FD com_tlm_u_tlm_rx_data_snk_eof_q_2_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_eof_q_1__5112), + .Q(com_tlm_u_tlm_rx_data_snk_eof_q_2__5113) + ); + FD com_tlm_u_tlm_rx_data_snk_dsc_q_5_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_dsc_q_4_), + .Q(com_tlm_u_tlm_rx_data_snk_dsc_q_5__5114) + ); + FD com_tlm_u_tlm_rx_data_snk_lower_addr64_in_q_6_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_lnk_rd[6]), + .Q(com_tlm_u_tlm_rx_data_snk_lower_addr64_in_q[6]) + ); + FD com_tlm_u_tlm_rx_data_snk_lower_addr64_in_q_5_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_lnk_rd[5]), + .Q(com_tlm_u_tlm_rx_data_snk_lower_addr64_in_q[5]) + ); + FD com_tlm_u_tlm_rx_data_snk_lower_addr64_in_q_4_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_lnk_rd[4]), + .Q(com_tlm_u_tlm_rx_data_snk_lower_addr64_in_q[4]) + ); + FD com_tlm_u_tlm_rx_data_snk_lower_addr64_in_q_3_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_lnk_rd[3]), + .Q(com_tlm_u_tlm_rx_data_snk_lower_addr64_in_q[3]) + ); + FD com_tlm_u_tlm_rx_data_snk_lower_addr64_in_q_2_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_lnk_rd[2]), + .Q(com_tlm_u_tlm_rx_data_snk_lower_addr64_in_q[2]) + ); + FD com_tlm_u_tlm_rx_data_snk_lower_addr32_in_q_6_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_lnk_rd_6113[38]), + .Q(com_tlm_u_tlm_rx_data_snk_lower_addr32_in_q[6]) + ); + FD com_tlm_u_tlm_rx_data_snk_lower_addr32_in_q_5_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_lnk_rd_6113[37]), + .Q(com_tlm_u_tlm_rx_data_snk_lower_addr32_in_q[5]) + ); + FD com_tlm_u_tlm_rx_data_snk_lower_addr32_in_q_4_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_lnk_rd_6113[36]), + .Q(com_tlm_u_tlm_rx_data_snk_lower_addr32_in_q[4]) + ); + FD com_tlm_u_tlm_rx_data_snk_lower_addr32_in_q_3_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_lnk_rd_6113[35]), + .Q(com_tlm_u_tlm_rx_data_snk_lower_addr32_in_q[3]) + ); + FD com_tlm_u_tlm_rx_data_snk_lower_addr32_in_q_2_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_lnk_rd_6113[34]), + .Q(com_tlm_u_tlm_rx_data_snk_lower_addr32_in_q[2]) + ); + FD com_tlm_u_tlm_rx_data_snk_src_rdy_q_5_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_src_rdy_q_4_), + .Q(com_tlm_u_tlm_rx_data_snk_src_rdy_q_5__5115) + ); + FDE com_tlm_u_tlm_rx_data_snk_cur_cpl ( + .CE(com_tlm_u_tlm_rx_data_snk_latch_1st_dword_q2), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_cur_fulltype_oh_0__5133), + .Q(com_tlm_u_tlm_rx_data_snk_cur_cpl_5123) + ); + FDE com_tlm_u_tlm_rx_data_snk_bar_o_6_ ( + .CE(com_tlm_u_tlm_rx_data_snk_sof_q_4_), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmmt_rbar_hit[6]), + .Q(com_tlm_u_tlm_rx_ds_bar[6]) + ); + FDE com_tlm_u_tlm_rx_data_snk_bar_o_5_ ( + .CE(com_tlm_u_tlm_rx_data_snk_sof_q_4_), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmmt_rbar_hit[5]), + .Q(com_tlm_u_tlm_rx_ds_bar[5]) + ); + FDE com_tlm_u_tlm_rx_data_snk_bar_o_4_ ( + .CE(com_tlm_u_tlm_rx_data_snk_sof_q_4_), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmmt_rbar_hit[4]), + .Q(com_tlm_u_tlm_rx_ds_bar[4]) + ); + FDE com_tlm_u_tlm_rx_data_snk_bar_o_3_ ( + .CE(com_tlm_u_tlm_rx_data_snk_sof_q_4_), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmmt_rbar_hit[3]), + .Q(com_tlm_u_tlm_rx_ds_bar[3]) + ); + FDE com_tlm_u_tlm_rx_data_snk_bar_o_2_ ( + .CE(com_tlm_u_tlm_rx_data_snk_sof_q_4_), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmmt_rbar_hit[2]), + .Q(com_tlm_u_tlm_rx_ds_bar[2]) + ); + FDE com_tlm_u_tlm_rx_data_snk_bar_o_1_ ( + .CE(com_tlm_u_tlm_rx_data_snk_sof_q_4_), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmmt_rbar_hit[1]), + .Q(com_tlm_u_tlm_rx_ds_bar[1]) + ); + FDE com_tlm_u_tlm_rx_data_snk_bar_o_0_ ( + .CE(com_tlm_u_tlm_rx_data_snk_sof_q_4_), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmmt_rbar_hit[0]), + .Q(com_tlm_u_tlm_rx_ds_bar[0]) + ); + FDE com_tlm_u_tlm_rx_data_snk_cur_cpl_header_fmt_28_ ( + .CE(com_tlm_u_tlm_rx_data_snk_latch_1st_dword_q2), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_cur_tc[2]), + .Q(com_tlm_u_tlm_rx_data_snk_cur_cpl_header_fmt[28]) + ); + FDE com_tlm_u_tlm_rx_data_snk_cur_cpl_header_fmt_27_ ( + .CE(com_tlm_u_tlm_rx_data_snk_latch_1st_dword_q2), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_cur_tc[1]), + .Q(com_tlm_u_tlm_rx_data_snk_cur_cpl_header_fmt[27]) + ); + FDE com_tlm_u_tlm_rx_data_snk_cur_cpl_header_fmt_26_ ( + .CE(com_tlm_u_tlm_rx_data_snk_latch_1st_dword_q2), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_cur_tc[0]), + .Q(com_tlm_u_tlm_rx_data_snk_cur_cpl_header_fmt[26]) + ); + FDE com_tlm_u_tlm_rx_data_snk_cur_cpl_header_fmt_25_ ( + .CE(com_tlm_u_tlm_rx_data_snk_latch_1st_dword_q2), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_cur_attr[1]), + .Q(com_tlm_u_tlm_rx_data_snk_cur_cpl_header_fmt[25]) + ); + FDE com_tlm_u_tlm_rx_data_snk_cur_cpl_header_fmt_24_ ( + .CE(com_tlm_u_tlm_rx_data_snk_latch_1st_dword_q2), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_cur_attr[0]), + .Q(com_tlm_u_tlm_rx_data_snk_cur_cpl_header_fmt[24]) + ); + FDE com_tlm_u_tlm_rx_data_snk_cur_cpl_header_fmt_23_ ( + .CE(com_tlm_u_tlm_rx_data_snk_latch_1st_dword_q2), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_cur_req_id[15]), + .Q(com_tlm_u_tlm_rx_data_snk_cur_cpl_header_fmt[23]) + ); + FDE com_tlm_u_tlm_rx_data_snk_cur_cpl_header_fmt_22_ ( + .CE(com_tlm_u_tlm_rx_data_snk_latch_1st_dword_q2), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_cur_req_id[14]), + .Q(com_tlm_u_tlm_rx_data_snk_cur_cpl_header_fmt[22]) + ); + FDE com_tlm_u_tlm_rx_data_snk_cur_cpl_header_fmt_21_ ( + .CE(com_tlm_u_tlm_rx_data_snk_latch_1st_dword_q2), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_cur_req_id[13]), + .Q(com_tlm_u_tlm_rx_data_snk_cur_cpl_header_fmt[21]) + ); + FDE com_tlm_u_tlm_rx_data_snk_cur_cpl_header_fmt_20_ ( + .CE(com_tlm_u_tlm_rx_data_snk_latch_1st_dword_q2), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_cur_req_id[12]), + .Q(com_tlm_u_tlm_rx_data_snk_cur_cpl_header_fmt[20]) + ); + FDE com_tlm_u_tlm_rx_data_snk_cur_cpl_header_fmt_19_ ( + .CE(com_tlm_u_tlm_rx_data_snk_latch_1st_dword_q2), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_cur_req_id[11]), + .Q(com_tlm_u_tlm_rx_data_snk_cur_cpl_header_fmt[19]) + ); + FDE com_tlm_u_tlm_rx_data_snk_cur_cpl_header_fmt_18_ ( + .CE(com_tlm_u_tlm_rx_data_snk_latch_1st_dword_q2), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_cur_req_id[10]), + .Q(com_tlm_u_tlm_rx_data_snk_cur_cpl_header_fmt[18]) + ); + FDE com_tlm_u_tlm_rx_data_snk_cur_cpl_header_fmt_17_ ( + .CE(com_tlm_u_tlm_rx_data_snk_latch_1st_dword_q2), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_cur_req_id[9]), + .Q(com_tlm_u_tlm_rx_data_snk_cur_cpl_header_fmt[17]) + ); + FDE com_tlm_u_tlm_rx_data_snk_cur_cpl_header_fmt_16_ ( + .CE(com_tlm_u_tlm_rx_data_snk_latch_1st_dword_q2), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_cur_req_id[8]), + .Q(com_tlm_u_tlm_rx_data_snk_cur_cpl_header_fmt[16]) + ); + FDE com_tlm_u_tlm_rx_data_snk_cur_cpl_header_fmt_15_ ( + .CE(com_tlm_u_tlm_rx_data_snk_latch_1st_dword_q2), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_cur_req_id[7]), + .Q(com_tlm_u_tlm_rx_data_snk_cur_cpl_header_fmt[15]) + ); + FDE com_tlm_u_tlm_rx_data_snk_cur_cpl_header_fmt_14_ ( + .CE(com_tlm_u_tlm_rx_data_snk_latch_1st_dword_q2), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_cur_req_id[6]), + .Q(com_tlm_u_tlm_rx_data_snk_cur_cpl_header_fmt[14]) + ); + FDE com_tlm_u_tlm_rx_data_snk_cur_cpl_header_fmt_13_ ( + .CE(com_tlm_u_tlm_rx_data_snk_latch_1st_dword_q2), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_cur_req_id[5]), + .Q(com_tlm_u_tlm_rx_data_snk_cur_cpl_header_fmt[13]) + ); + FDE com_tlm_u_tlm_rx_data_snk_cur_cpl_header_fmt_12_ ( + .CE(com_tlm_u_tlm_rx_data_snk_latch_1st_dword_q2), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_cur_req_id[4]), + .Q(com_tlm_u_tlm_rx_data_snk_cur_cpl_header_fmt[12]) + ); + FDE com_tlm_u_tlm_rx_data_snk_cur_cpl_header_fmt_11_ ( + .CE(com_tlm_u_tlm_rx_data_snk_latch_1st_dword_q2), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_cur_req_id[3]), + .Q(com_tlm_u_tlm_rx_data_snk_cur_cpl_header_fmt[11]) + ); + FDE com_tlm_u_tlm_rx_data_snk_cur_cpl_header_fmt_10_ ( + .CE(com_tlm_u_tlm_rx_data_snk_latch_1st_dword_q2), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_cur_req_id[2]), + .Q(com_tlm_u_tlm_rx_data_snk_cur_cpl_header_fmt[10]) + ); + FDE com_tlm_u_tlm_rx_data_snk_cur_cpl_header_fmt_9_ ( + .CE(com_tlm_u_tlm_rx_data_snk_latch_1st_dword_q2), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_cur_req_id[1]), + .Q(com_tlm_u_tlm_rx_data_snk_cur_cpl_header_fmt[9]) + ); + FDE com_tlm_u_tlm_rx_data_snk_cur_cpl_header_fmt_8_ ( + .CE(com_tlm_u_tlm_rx_data_snk_latch_1st_dword_q2), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_cur_req_id[0]), + .Q(com_tlm_u_tlm_rx_data_snk_cur_cpl_header_fmt[8]) + ); + FDE com_tlm_u_tlm_rx_data_snk_cur_cpl_header_fmt_7_ ( + .CE(com_tlm_u_tlm_rx_data_snk_latch_1st_dword_q2), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_cur_tag[7]), + .Q(com_tlm_u_tlm_rx_data_snk_cur_cpl_header_fmt[7]) + ); + FDE com_tlm_u_tlm_rx_data_snk_cur_cpl_header_fmt_6_ ( + .CE(com_tlm_u_tlm_rx_data_snk_latch_1st_dword_q2), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_cur_tag[6]), + .Q(com_tlm_u_tlm_rx_data_snk_cur_cpl_header_fmt[6]) + ); + FDE com_tlm_u_tlm_rx_data_snk_cur_cpl_header_fmt_5_ ( + .CE(com_tlm_u_tlm_rx_data_snk_latch_1st_dword_q2), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_cur_tag[5]), + .Q(com_tlm_u_tlm_rx_data_snk_cur_cpl_header_fmt[5]) + ); + FDE com_tlm_u_tlm_rx_data_snk_cur_cpl_header_fmt_4_ ( + .CE(com_tlm_u_tlm_rx_data_snk_latch_1st_dword_q2), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_cur_tag[4]), + .Q(com_tlm_u_tlm_rx_data_snk_cur_cpl_header_fmt[4]) + ); + FDE com_tlm_u_tlm_rx_data_snk_cur_cpl_header_fmt_3_ ( + .CE(com_tlm_u_tlm_rx_data_snk_latch_1st_dword_q2), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_cur_tag[3]), + .Q(com_tlm_u_tlm_rx_data_snk_cur_cpl_header_fmt[3]) + ); + FDE com_tlm_u_tlm_rx_data_snk_cur_cpl_header_fmt_2_ ( + .CE(com_tlm_u_tlm_rx_data_snk_latch_1st_dword_q2), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_cur_tag[2]), + .Q(com_tlm_u_tlm_rx_data_snk_cur_cpl_header_fmt[2]) + ); + FDE com_tlm_u_tlm_rx_data_snk_cur_cpl_header_fmt_1_ ( + .CE(com_tlm_u_tlm_rx_data_snk_latch_1st_dword_q2), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_cur_tag[1]), + .Q(com_tlm_u_tlm_rx_data_snk_cur_cpl_header_fmt[1]) + ); + FDE com_tlm_u_tlm_rx_data_snk_cur_cpl_header_fmt_0_ ( + .CE(com_tlm_u_tlm_rx_data_snk_latch_1st_dword_q2), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_cur_tag[0]), + .Q(com_tlm_u_tlm_rx_data_snk_cur_cpl_header_fmt[0]) + ); + FDE com_tlm_u_tlm_rx_data_snk_cur_ep_q ( + .CE(com_tlm_u_tlm_rx_data_snk_latch_1st_dword_q2), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_cur_ep_5118), + .Q(com_tlm_u_tlm_rx_data_snk_cur_ep_q_5116) + ); + FDE com_tlm_u_tlm_rx_data_snk_cur_td_q ( + .CE(com_tlm_u_tlm_rx_data_snk_latch_1st_dword_q2), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_cur_td_5119), + .Q(com_tlm_u_tlm_rx_data_snk_cur_td_q_5117) + ); + FDE com_tlm_u_tlm_rx_data_snk_cur_attr_1_ ( + .CE(com_tlm_u_tlm_rx_data_snk_latch_2nd_dword), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_lnk_rd_6113[45]), + .Q(com_tlm_u_tlm_rx_data_snk_cur_attr[1]) + ); + FDE com_tlm_u_tlm_rx_data_snk_cur_attr_0_ ( + .CE(com_tlm_u_tlm_rx_data_snk_latch_2nd_dword), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_lnk_rd_6113[44]), + .Q(com_tlm_u_tlm_rx_data_snk_cur_attr[0]) + ); + FDE com_tlm_u_tlm_rx_data_snk_cur_ep ( + .CE(com_tlm_u_tlm_rx_data_snk_latch_2nd_dword), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_lnk_rd_6113[46]), + .Q(com_tlm_u_tlm_rx_data_snk_cur_ep_5118) + ); + FDE com_tlm_u_tlm_rx_data_snk_cur_length_9_ ( + .CE(com_tlm_u_tlm_rx_data_snk_latch_2nd_dword), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_lnk_rd_6113[41]), + .Q(com_tlm_u_tlm_rx_data_snk_cur_length_9__14) + ); + FDE com_tlm_u_tlm_rx_data_snk_cur_length_8_ ( + .CE(com_tlm_u_tlm_rx_data_snk_latch_2nd_dword), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_lnk_rd_6113[40]), + .Q(com_tlm_u_tlm_rx_data_snk_cur_length_8__12) + ); + FDE com_tlm_u_tlm_rx_data_snk_cur_length_7_ ( + .CE(com_tlm_u_tlm_rx_data_snk_latch_2nd_dword), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_lnk_rd_6113[39]), + .Q(com_tlm_u_tlm_rx_data_snk_cur_length[7]) + ); + FDE com_tlm_u_tlm_rx_data_snk_cur_length_6_ ( + .CE(com_tlm_u_tlm_rx_data_snk_latch_2nd_dword), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_lnk_rd_6113[38]), + .Q(com_tlm_u_tlm_rx_data_snk_cur_length[6]) + ); + FDE com_tlm_u_tlm_rx_data_snk_cur_length_5_ ( + .CE(com_tlm_u_tlm_rx_data_snk_latch_2nd_dword), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_lnk_rd_6113[37]), + .Q(com_tlm_u_tlm_rx_data_snk_cur_length[5]) + ); + FDE com_tlm_u_tlm_rx_data_snk_cur_length_4_ ( + .CE(com_tlm_u_tlm_rx_data_snk_latch_2nd_dword), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_lnk_rd_6113[36]), + .Q(com_tlm_u_tlm_rx_data_snk_cur_length_4__10) + ); + FDE com_tlm_u_tlm_rx_data_snk_cur_length_3_ ( + .CE(com_tlm_u_tlm_rx_data_snk_latch_2nd_dword), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_lnk_rd_6113[35]), + .Q(com_tlm_u_tlm_rx_data_snk_cur_length_3__8) + ); + FDE com_tlm_u_tlm_rx_data_snk_cur_length_2_ ( + .CE(com_tlm_u_tlm_rx_data_snk_latch_2nd_dword), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_lnk_rd_6113[34]), + .Q(com_tlm_u_tlm_rx_data_snk_cur_length_2__6) + ); + FDE com_tlm_u_tlm_rx_data_snk_cur_length_1_ ( + .CE(com_tlm_u_tlm_rx_data_snk_latch_2nd_dword), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_lnk_rd_6113[33]), + .Q(com_tlm_u_tlm_rx_data_snk_cur_length_1__4) + ); + FDE com_tlm_u_tlm_rx_data_snk_cur_length_0_ ( + .CE(com_tlm_u_tlm_rx_data_snk_latch_2nd_dword), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_lnk_rd_6113[32]), + .Q(com_tlm_u_tlm_rx_data_snk_cur_length_0__2) + ); + FDE com_tlm_u_tlm_rx_data_snk_cur_tc_2_ ( + .CE(com_tlm_u_tlm_rx_data_snk_latch_2nd_dword), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_lnk_rd_6113[54]), + .Q(com_tlm_u_tlm_rx_data_snk_cur_tc[2]) + ); + FDE com_tlm_u_tlm_rx_data_snk_cur_tc_1_ ( + .CE(com_tlm_u_tlm_rx_data_snk_latch_2nd_dword), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_lnk_rd_6113[53]), + .Q(com_tlm_u_tlm_rx_data_snk_cur_tc[1]) + ); + FDE com_tlm_u_tlm_rx_data_snk_cur_tc_0_ ( + .CE(com_tlm_u_tlm_rx_data_snk_latch_2nd_dword), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_lnk_rd_6113[52]), + .Q(com_tlm_u_tlm_rx_data_snk_cur_tc[0]) + ); + FDE com_tlm_u_tlm_rx_data_snk_cur_td ( + .CE(com_tlm_u_tlm_rx_data_snk_latch_2nd_dword), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_lnk_rd_6113[47]), + .Q(com_tlm_u_tlm_rx_data_snk_cur_td_5119) + ); + FDE com_tlm_u_tlm_rx_data_snk_cur_cpl_stat_2_ ( + .CE(com_tlm_u_tlm_rx_data_snk_latch_2nd_dword), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_lnk_rd_6113[15]), + .Q(com_tlm_u_tlm_rx_data_snk_cur_tag[7]) + ); + FDE com_tlm_u_tlm_rx_data_snk_cur_cpl_stat_1_ ( + .CE(com_tlm_u_tlm_rx_data_snk_latch_2nd_dword), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_lnk_rd_6113[14]), + .Q(com_tlm_u_tlm_rx_data_snk_cur_tag[6]) + ); + FDE com_tlm_u_tlm_rx_data_snk_cur_cpl_stat_0_ ( + .CE(com_tlm_u_tlm_rx_data_snk_latch_2nd_dword), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_lnk_rd_6113[13]), + .Q(com_tlm_u_tlm_rx_data_snk_cur_tag[5]) + ); + FDE com_tlm_u_tlm_rx_data_snk_cur_msgcode_7_ ( + .CE(com_tlm_u_tlm_rx_data_snk_latch_2nd_dword), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_lnk_rd[7]), + .Q(com_tlm_u_tlm_rx_data_snk_cur_msgcode[7]) + ); + FDE com_tlm_u_tlm_rx_data_snk_cur_msgcode_6_ ( + .CE(com_tlm_u_tlm_rx_data_snk_latch_2nd_dword), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_lnk_rd[6]), + .Q(com_tlm_u_tlm_rx_data_snk_cur_msgcode[6]) + ); + FDE com_tlm_u_tlm_rx_data_snk_cur_msgcode_5_ ( + .CE(com_tlm_u_tlm_rx_data_snk_latch_2nd_dword), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_lnk_rd[5]), + .Q(com_tlm_u_tlm_rx_data_snk_cur_msgcode[5]) + ); + FDE com_tlm_u_tlm_rx_data_snk_cur_msgcode_4_ ( + .CE(com_tlm_u_tlm_rx_data_snk_latch_2nd_dword), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_lnk_rd[4]), + .Q(com_tlm_u_tlm_rx_data_snk_cur_msgcode[4]) + ); + FDE com_tlm_u_tlm_rx_data_snk_cur_msgcode_3_ ( + .CE(com_tlm_u_tlm_rx_data_snk_latch_2nd_dword), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_lnk_rd[3]), + .Q(com_tlm_u_tlm_rx_data_snk_cur_msgcode[3]) + ); + FDE com_tlm_u_tlm_rx_data_snk_cur_msgcode_2_ ( + .CE(com_tlm_u_tlm_rx_data_snk_latch_2nd_dword), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_lnk_rd[2]), + .Q(com_tlm_u_tlm_rx_data_snk_cur_msgcode[2]) + ); + FDE com_tlm_u_tlm_rx_data_snk_cur_msgcode_1_ ( + .CE(com_tlm_u_tlm_rx_data_snk_latch_2nd_dword), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_lnk_rd[1]), + .Q(com_tlm_u_tlm_rx_data_snk_cur_msgcode[1]) + ); + FDE com_tlm_u_tlm_rx_data_snk_cur_msgcode_0_ ( + .CE(com_tlm_u_tlm_rx_data_snk_latch_2nd_dword), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_lnk_rd[0]), + .Q(com_tlm_u_tlm_rx_data_snk_cur_msgcode[0]) + ); + FDE com_tlm_u_tlm_rx_data_snk_cur_req_id_15_ ( + .CE(com_tlm_u_tlm_rx_data_snk_latch_2nd_dword), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_lnk_rd_6113[31]), + .Q(com_tlm_u_tlm_rx_data_snk_cur_req_id[15]) + ); + FDE com_tlm_u_tlm_rx_data_snk_cur_req_id_14_ ( + .CE(com_tlm_u_tlm_rx_data_snk_latch_2nd_dword), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_lnk_rd_6113[30]), + .Q(com_tlm_u_tlm_rx_data_snk_cur_req_id[14]) + ); + FDE com_tlm_u_tlm_rx_data_snk_cur_req_id_13_ ( + .CE(com_tlm_u_tlm_rx_data_snk_latch_2nd_dword), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_lnk_rd_6113[29]), + .Q(com_tlm_u_tlm_rx_data_snk_cur_req_id[13]) + ); + FDE com_tlm_u_tlm_rx_data_snk_cur_req_id_12_ ( + .CE(com_tlm_u_tlm_rx_data_snk_latch_2nd_dword), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_lnk_rd_6113[28]), + .Q(com_tlm_u_tlm_rx_data_snk_cur_req_id[12]) + ); + FDE com_tlm_u_tlm_rx_data_snk_cur_req_id_11_ ( + .CE(com_tlm_u_tlm_rx_data_snk_latch_2nd_dword), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_lnk_rd_6113[27]), + .Q(com_tlm_u_tlm_rx_data_snk_cur_req_id[11]) + ); + FDE com_tlm_u_tlm_rx_data_snk_cur_req_id_10_ ( + .CE(com_tlm_u_tlm_rx_data_snk_latch_2nd_dword), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_lnk_rd_6113[26]), + .Q(com_tlm_u_tlm_rx_data_snk_cur_req_id[10]) + ); + FDE com_tlm_u_tlm_rx_data_snk_cur_req_id_9_ ( + .CE(com_tlm_u_tlm_rx_data_snk_latch_2nd_dword), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_lnk_rd_6113[25]), + .Q(com_tlm_u_tlm_rx_data_snk_cur_req_id[9]) + ); + FDE com_tlm_u_tlm_rx_data_snk_cur_req_id_8_ ( + .CE(com_tlm_u_tlm_rx_data_snk_latch_2nd_dword), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_lnk_rd_6113[24]), + .Q(com_tlm_u_tlm_rx_data_snk_cur_req_id[8]) + ); + FDE com_tlm_u_tlm_rx_data_snk_cur_req_id_7_ ( + .CE(com_tlm_u_tlm_rx_data_snk_latch_2nd_dword), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_lnk_rd_6113[23]), + .Q(com_tlm_u_tlm_rx_data_snk_cur_req_id[7]) + ); + FDE com_tlm_u_tlm_rx_data_snk_cur_req_id_6_ ( + .CE(com_tlm_u_tlm_rx_data_snk_latch_2nd_dword), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_lnk_rd_6113[22]), + .Q(com_tlm_u_tlm_rx_data_snk_cur_req_id[6]) + ); + FDE com_tlm_u_tlm_rx_data_snk_cur_req_id_5_ ( + .CE(com_tlm_u_tlm_rx_data_snk_latch_2nd_dword), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_lnk_rd_6113[21]), + .Q(com_tlm_u_tlm_rx_data_snk_cur_req_id[5]) + ); + FDE com_tlm_u_tlm_rx_data_snk_cur_req_id_4_ ( + .CE(com_tlm_u_tlm_rx_data_snk_latch_2nd_dword), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_lnk_rd_6113[20]), + .Q(com_tlm_u_tlm_rx_data_snk_cur_req_id[4]) + ); + FDE com_tlm_u_tlm_rx_data_snk_cur_req_id_3_ ( + .CE(com_tlm_u_tlm_rx_data_snk_latch_2nd_dword), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_lnk_rd_6113[19]), + .Q(com_tlm_u_tlm_rx_data_snk_cur_req_id[3]) + ); + FDE com_tlm_u_tlm_rx_data_snk_cur_req_id_2_ ( + .CE(com_tlm_u_tlm_rx_data_snk_latch_2nd_dword), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_lnk_rd_6113[18]), + .Q(com_tlm_u_tlm_rx_data_snk_cur_req_id[2]) + ); + FDE com_tlm_u_tlm_rx_data_snk_cur_req_id_1_ ( + .CE(com_tlm_u_tlm_rx_data_snk_latch_2nd_dword), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_lnk_rd_6113[17]), + .Q(com_tlm_u_tlm_rx_data_snk_cur_req_id[1]) + ); + FDE com_tlm_u_tlm_rx_data_snk_cur_req_id_0_ ( + .CE(com_tlm_u_tlm_rx_data_snk_latch_2nd_dword), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_lnk_rd_6113[16]), + .Q(com_tlm_u_tlm_rx_data_snk_cur_req_id[0]) + ); + FDE com_tlm_u_tlm_rx_data_snk_cur_tag_4_ ( + .CE(com_tlm_u_tlm_rx_data_snk_latch_2nd_dword), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_lnk_rd_6113[12]), + .Q(com_tlm_u_tlm_rx_data_snk_cur_tag[4]) + ); + FDE com_tlm_u_tlm_rx_data_snk_cur_tag_3_ ( + .CE(com_tlm_u_tlm_rx_data_snk_latch_2nd_dword), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_lnk_rd_6113[11]), + .Q(com_tlm_u_tlm_rx_data_snk_cur_tag[3]) + ); + FDE com_tlm_u_tlm_rx_data_snk_cur_tag_2_ ( + .CE(com_tlm_u_tlm_rx_data_snk_latch_2nd_dword), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_lnk_rd_6113[10]), + .Q(com_tlm_u_tlm_rx_data_snk_cur_tag[2]) + ); + FDE com_tlm_u_tlm_rx_data_snk_cur_tag_1_ ( + .CE(com_tlm_u_tlm_rx_data_snk_latch_2nd_dword), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_lnk_rd_6113[9]), + .Q(com_tlm_u_tlm_rx_data_snk_cur_tag[1]) + ); + FDE com_tlm_u_tlm_rx_data_snk_cur_tag_0_ ( + .CE(com_tlm_u_tlm_rx_data_snk_latch_2nd_dword), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_lnk_rd_6113[8]), + .Q(com_tlm_u_tlm_rx_data_snk_cur_tag[0]) + ); + FDE com_tlm_u_tlm_rx_data_snk_cur_rem ( + .CE(com_tlm_u_tlm_rx_data_snk_cur_rem_0_sqmuxa), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_lnk_rrem[0]), + .Q(com_tlm_u_tlm_rx_data_snk_cur_rem_5120) + ); + FDE com_tlm_u_tlm_rx_data_snk_cur_np ( + .CE(com_tlm_u_tlm_rx_data_snk_latch_1st_dword_q2), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_cur_np_2), + .Q(com_tlm_u_tlm_rx_data_snk_cur_np_5125) + ); + FDE com_tlm_u_tlm_rx_data_snk_cur_tc0 ( + .CE(com_tlm_u_tlm_rx_data_snk_latch_2nd_dword), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_cur_tc0_2), + .Q(com_tlm_u_tlm_rx_data_snk_cur_tc0_5121) + ); + FDE com_tlm_u_tlm_rx_data_snk_fc_use_data_o_5_ ( + .CE(com_tlm_u_tlm_rx_data_snk_cur_data_credits_vld), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_cur_data_credits[5]), + .Q(com_tlm_u_tlm_rx_fc_use_data[5]) + ); + FDE com_tlm_u_tlm_rx_data_snk_fc_use_data_o_4_ ( + .CE(com_tlm_u_tlm_rx_data_snk_cur_data_credits_vld), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_cur_data_credits[4]), + .Q(com_tlm_u_tlm_rx_fc_use_data[4]) + ); + FDE com_tlm_u_tlm_rx_data_snk_fc_use_data_o_3_ ( + .CE(com_tlm_u_tlm_rx_data_snk_cur_data_credits_vld), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_cur_data_credits[3]), + .Q(com_tlm_u_tlm_rx_fc_use_data[3]) + ); + FDE com_tlm_u_tlm_rx_data_snk_fc_use_data_o_2_ ( + .CE(com_tlm_u_tlm_rx_data_snk_cur_data_credits_vld), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_cur_data_credits[2]), + .Q(com_tlm_u_tlm_rx_fc_use_data[2]) + ); + FDE com_tlm_u_tlm_rx_data_snk_fc_use_data_o_1_ ( + .CE(com_tlm_u_tlm_rx_data_snk_cur_data_credits_vld), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_cur_data_credits[1]), + .Q(com_tlm_u_tlm_rx_fc_use_data[1]) + ); + FDE com_tlm_u_tlm_rx_data_snk_fc_use_data_o_0_ ( + .CE(com_tlm_u_tlm_rx_data_snk_cur_data_credits_vld), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_cur_data_credits[0]), + .Q(com_tlm_u_tlm_rx_fc_use_data[0]) + ); + FDE com_tlm_u_tlm_rx_data_snk_err_tlp_cpl_header_o_47_ ( + .CE(com_tlm_u_tlm_rx_data_snk_eof_q_3__5122), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_cur_lower_addr[6]), + .Q(com_cmmt_err_tlp_hdr[47]) + ); + FDE com_tlm_u_tlm_rx_data_snk_err_tlp_cpl_header_o_46_ ( + .CE(com_tlm_u_tlm_rx_data_snk_eof_q_3__5122), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_cur_lower_addr[5]), + .Q(com_cmmt_err_tlp_hdr[46]) + ); + FDE com_tlm_u_tlm_rx_data_snk_err_tlp_cpl_header_o_45_ ( + .CE(com_tlm_u_tlm_rx_data_snk_eof_q_3__5122), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_cur_lower_addr[4]), + .Q(com_cmmt_err_tlp_hdr[45]) + ); + FDE com_tlm_u_tlm_rx_data_snk_err_tlp_cpl_header_o_44_ ( + .CE(com_tlm_u_tlm_rx_data_snk_eof_q_3__5122), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_cur_lower_addr[3]), + .Q(com_cmmt_err_tlp_hdr[44]) + ); + FDE com_tlm_u_tlm_rx_data_snk_err_tlp_cpl_header_o_43_ ( + .CE(com_tlm_u_tlm_rx_data_snk_eof_q_3__5122), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_cur_lower_addr[2]), + .Q(com_cmmt_err_tlp_hdr[43]) + ); + FDE com_tlm_u_tlm_rx_data_snk_err_tlp_cpl_header_o_42_ ( + .CE(com_tlm_u_tlm_rx_data_snk_eof_q_3__5122), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_cur_lower_addr[1]), + .Q(com_cmmt_err_tlp_hdr[42]) + ); + FDE com_tlm_u_tlm_rx_data_snk_err_tlp_cpl_header_o_41_ ( + .CE(com_tlm_u_tlm_rx_data_snk_eof_q_3__5122), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_cur_lower_addr[0]), + .Q(com_cmmt_err_tlp_hdr[41]) + ); + FDE com_tlm_u_tlm_rx_data_snk_err_tlp_cpl_header_o_40_ ( + .CE(com_tlm_u_tlm_rx_data_snk_eof_q_3__5122), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_cur_byte_ct[11]), + .Q(com_cmmt_err_tlp_hdr[40]) + ); + FDE com_tlm_u_tlm_rx_data_snk_err_tlp_cpl_header_o_39_ ( + .CE(com_tlm_u_tlm_rx_data_snk_eof_q_3__5122), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_cur_byte_ct[10]), + .Q(com_cmmt_err_tlp_hdr[39]) + ); + FDE com_tlm_u_tlm_rx_data_snk_err_tlp_cpl_header_o_38_ ( + .CE(com_tlm_u_tlm_rx_data_snk_eof_q_3__5122), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_cur_byte_ct[9]), + .Q(com_cmmt_err_tlp_hdr[38]) + ); + FDE com_tlm_u_tlm_rx_data_snk_err_tlp_cpl_header_o_37_ ( + .CE(com_tlm_u_tlm_rx_data_snk_eof_q_3__5122), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_cur_byte_ct[8]), + .Q(com_cmmt_err_tlp_hdr[37]) + ); + FDE com_tlm_u_tlm_rx_data_snk_err_tlp_cpl_header_o_36_ ( + .CE(com_tlm_u_tlm_rx_data_snk_eof_q_3__5122), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_cur_byte_ct[7]), + .Q(com_cmmt_err_tlp_hdr[36]) + ); + FDE com_tlm_u_tlm_rx_data_snk_err_tlp_cpl_header_o_35_ ( + .CE(com_tlm_u_tlm_rx_data_snk_eof_q_3__5122), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_cur_byte_ct[6]), + .Q(com_cmmt_err_tlp_hdr[35]) + ); + FDE com_tlm_u_tlm_rx_data_snk_err_tlp_cpl_header_o_34_ ( + .CE(com_tlm_u_tlm_rx_data_snk_eof_q_3__5122), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_cur_byte_ct[5]), + .Q(com_cmmt_err_tlp_hdr[34]) + ); + FDE com_tlm_u_tlm_rx_data_snk_err_tlp_cpl_header_o_33_ ( + .CE(com_tlm_u_tlm_rx_data_snk_eof_q_3__5122), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_cur_byte_ct[4]), + .Q(com_cmmt_err_tlp_hdr[33]) + ); + FDE com_tlm_u_tlm_rx_data_snk_err_tlp_cpl_header_o_32_ ( + .CE(com_tlm_u_tlm_rx_data_snk_eof_q_3__5122), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_cur_byte_ct[3]), + .Q(com_cmmt_err_tlp_hdr[32]) + ); + FDE com_tlm_u_tlm_rx_data_snk_err_tlp_cpl_header_o_31_ ( + .CE(com_tlm_u_tlm_rx_data_snk_eof_q_3__5122), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_cur_byte_ct[2]), + .Q(com_cmmt_err_tlp_hdr[31]) + ); + FDE com_tlm_u_tlm_rx_data_snk_err_tlp_cpl_header_o_30_ ( + .CE(com_tlm_u_tlm_rx_data_snk_eof_q_3__5122), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_cur_byte_ct[1]), + .Q(com_cmmt_err_tlp_hdr[30]) + ); + FDE com_tlm_u_tlm_rx_data_snk_err_tlp_cpl_header_o_29_ ( + .CE(com_tlm_u_tlm_rx_data_snk_eof_q_3__5122), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_cur_byte_ct[0]), + .Q(com_cmmt_err_tlp_hdr[29]) + ); + FDE com_tlm_u_tlm_rx_data_snk_err_tlp_cpl_header_o_28_ ( + .CE(com_tlm_u_tlm_rx_data_snk_eof_q_3__5122), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_cur_cpl_header_fmt[28]), + .Q(com_cmmt_err_tlp_hdr[28]) + ); + FDE com_tlm_u_tlm_rx_data_snk_err_tlp_cpl_header_o_27_ ( + .CE(com_tlm_u_tlm_rx_data_snk_eof_q_3__5122), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_cur_cpl_header_fmt[27]), + .Q(com_cmmt_err_tlp_hdr[27]) + ); + FDE com_tlm_u_tlm_rx_data_snk_err_tlp_cpl_header_o_26_ ( + .CE(com_tlm_u_tlm_rx_data_snk_eof_q_3__5122), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_cur_cpl_header_fmt[26]), + .Q(com_cmmt_err_tlp_hdr[26]) + ); + FDE com_tlm_u_tlm_rx_data_snk_err_tlp_cpl_header_o_25_ ( + .CE(com_tlm_u_tlm_rx_data_snk_eof_q_3__5122), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_cur_cpl_header_fmt[25]), + .Q(com_cmmt_err_tlp_hdr[25]) + ); + FDE com_tlm_u_tlm_rx_data_snk_err_tlp_cpl_header_o_24_ ( + .CE(com_tlm_u_tlm_rx_data_snk_eof_q_3__5122), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_cur_cpl_header_fmt[24]), + .Q(com_cmmt_err_tlp_hdr[24]) + ); + FDE com_tlm_u_tlm_rx_data_snk_err_tlp_cpl_header_o_23_ ( + .CE(com_tlm_u_tlm_rx_data_snk_eof_q_3__5122), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_cur_cpl_header_fmt[23]), + .Q(com_cmmt_err_tlp_hdr[23]) + ); + FDE com_tlm_u_tlm_rx_data_snk_err_tlp_cpl_header_o_22_ ( + .CE(com_tlm_u_tlm_rx_data_snk_eof_q_3__5122), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_cur_cpl_header_fmt[22]), + .Q(com_cmmt_err_tlp_hdr[22]) + ); + FDE com_tlm_u_tlm_rx_data_snk_err_tlp_cpl_header_o_21_ ( + .CE(com_tlm_u_tlm_rx_data_snk_eof_q_3__5122), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_cur_cpl_header_fmt[21]), + .Q(com_cmmt_err_tlp_hdr[21]) + ); + FDE com_tlm_u_tlm_rx_data_snk_err_tlp_cpl_header_o_20_ ( + .CE(com_tlm_u_tlm_rx_data_snk_eof_q_3__5122), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_cur_cpl_header_fmt[20]), + .Q(com_cmmt_err_tlp_hdr[20]) + ); + FDE com_tlm_u_tlm_rx_data_snk_err_tlp_cpl_header_o_19_ ( + .CE(com_tlm_u_tlm_rx_data_snk_eof_q_3__5122), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_cur_cpl_header_fmt[19]), + .Q(com_cmmt_err_tlp_hdr[19]) + ); + FDE com_tlm_u_tlm_rx_data_snk_err_tlp_cpl_header_o_18_ ( + .CE(com_tlm_u_tlm_rx_data_snk_eof_q_3__5122), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_cur_cpl_header_fmt[18]), + .Q(com_cmmt_err_tlp_hdr[18]) + ); + FDE com_tlm_u_tlm_rx_data_snk_err_tlp_cpl_header_o_17_ ( + .CE(com_tlm_u_tlm_rx_data_snk_eof_q_3__5122), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_cur_cpl_header_fmt[17]), + .Q(com_cmmt_err_tlp_hdr[17]) + ); + FDE com_tlm_u_tlm_rx_data_snk_err_tlp_cpl_header_o_16_ ( + .CE(com_tlm_u_tlm_rx_data_snk_eof_q_3__5122), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_cur_cpl_header_fmt[16]), + .Q(com_cmmt_err_tlp_hdr[16]) + ); + FDE com_tlm_u_tlm_rx_data_snk_err_tlp_cpl_header_o_15_ ( + .CE(com_tlm_u_tlm_rx_data_snk_eof_q_3__5122), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_cur_cpl_header_fmt[15]), + .Q(com_cmmt_err_tlp_hdr[15]) + ); + FDE com_tlm_u_tlm_rx_data_snk_err_tlp_cpl_header_o_14_ ( + .CE(com_tlm_u_tlm_rx_data_snk_eof_q_3__5122), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_cur_cpl_header_fmt[14]), + .Q(com_cmmt_err_tlp_hdr[14]) + ); + FDE com_tlm_u_tlm_rx_data_snk_err_tlp_cpl_header_o_13_ ( + .CE(com_tlm_u_tlm_rx_data_snk_eof_q_3__5122), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_cur_cpl_header_fmt[13]), + .Q(com_cmmt_err_tlp_hdr[13]) + ); + FDE com_tlm_u_tlm_rx_data_snk_err_tlp_cpl_header_o_12_ ( + .CE(com_tlm_u_tlm_rx_data_snk_eof_q_3__5122), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_cur_cpl_header_fmt[12]), + .Q(com_cmmt_err_tlp_hdr[12]) + ); + FDE com_tlm_u_tlm_rx_data_snk_err_tlp_cpl_header_o_11_ ( + .CE(com_tlm_u_tlm_rx_data_snk_eof_q_3__5122), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_cur_cpl_header_fmt[11]), + .Q(com_cmmt_err_tlp_hdr[11]) + ); + FDE com_tlm_u_tlm_rx_data_snk_err_tlp_cpl_header_o_10_ ( + .CE(com_tlm_u_tlm_rx_data_snk_eof_q_3__5122), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_cur_cpl_header_fmt[10]), + .Q(com_cmmt_err_tlp_hdr[10]) + ); + FDE com_tlm_u_tlm_rx_data_snk_err_tlp_cpl_header_o_9_ ( + .CE(com_tlm_u_tlm_rx_data_snk_eof_q_3__5122), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_cur_cpl_header_fmt[9]), + .Q(com_cmmt_err_tlp_hdr[9]) + ); + FDE com_tlm_u_tlm_rx_data_snk_err_tlp_cpl_header_o_8_ ( + .CE(com_tlm_u_tlm_rx_data_snk_eof_q_3__5122), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_cur_cpl_header_fmt[8]), + .Q(com_cmmt_err_tlp_hdr[8]) + ); + FDE com_tlm_u_tlm_rx_data_snk_err_tlp_cpl_header_o_7_ ( + .CE(com_tlm_u_tlm_rx_data_snk_eof_q_3__5122), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_cur_cpl_header_fmt[7]), + .Q(com_cmmt_err_tlp_hdr[7]) + ); + FDE com_tlm_u_tlm_rx_data_snk_err_tlp_cpl_header_o_6_ ( + .CE(com_tlm_u_tlm_rx_data_snk_eof_q_3__5122), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_cur_cpl_header_fmt[6]), + .Q(com_cmmt_err_tlp_hdr[6]) + ); + FDE com_tlm_u_tlm_rx_data_snk_err_tlp_cpl_header_o_5_ ( + .CE(com_tlm_u_tlm_rx_data_snk_eof_q_3__5122), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_cur_cpl_header_fmt[5]), + .Q(com_cmmt_err_tlp_hdr[5]) + ); + FDE com_tlm_u_tlm_rx_data_snk_err_tlp_cpl_header_o_4_ ( + .CE(com_tlm_u_tlm_rx_data_snk_eof_q_3__5122), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_cur_cpl_header_fmt[4]), + .Q(com_cmmt_err_tlp_hdr[4]) + ); + FDE com_tlm_u_tlm_rx_data_snk_err_tlp_cpl_header_o_3_ ( + .CE(com_tlm_u_tlm_rx_data_snk_eof_q_3__5122), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_cur_cpl_header_fmt[3]), + .Q(com_cmmt_err_tlp_hdr[3]) + ); + FDE com_tlm_u_tlm_rx_data_snk_err_tlp_cpl_header_o_2_ ( + .CE(com_tlm_u_tlm_rx_data_snk_eof_q_3__5122), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_cur_cpl_header_fmt[2]), + .Q(com_cmmt_err_tlp_hdr[2]) + ); + FDE com_tlm_u_tlm_rx_data_snk_err_tlp_cpl_header_o_1_ ( + .CE(com_tlm_u_tlm_rx_data_snk_eof_q_3__5122), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_cur_cpl_header_fmt[1]), + .Q(com_cmmt_err_tlp_hdr[1]) + ); + FDE com_tlm_u_tlm_rx_data_snk_err_tlp_cpl_header_o_0_ ( + .CE(com_tlm_u_tlm_rx_data_snk_eof_q_3__5122), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_cur_cpl_header_fmt[0]), + .Q(com_cmmt_err_tlp_hdr[0]) + ); + FDE com_tlm_u_tlm_rx_data_snk_cfg_o ( + .CE(com_tlm_u_tlm_rx_data_snk_latch_1st_dword_q4_5124), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_cur_cfg), + .Q(com_tlm_u_tlm_rx_ds_cfg) + ); + FDE com_tlm_u_tlm_rx_data_snk_cpl_o ( + .CE(com_tlm_u_tlm_rx_data_snk_latch_1st_dword_q4_5124), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_cur_cpl_5123), + .Q(com_tlm_u_tlm_rx_ds_cpl) + ); + FDE com_tlm_u_tlm_rx_data_snk_np_o ( + .CE(com_tlm_u_tlm_rx_data_snk_latch_1st_dword_q4_5124), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_cur_np_5125), + .Q(com_tlm_u_tlm_rx_ds_np) + ); + FDE com_tlm_u_tlm_rx_data_snk_cur_lower_addr_1_ ( + .CE(com_tlm_u_tlm_rx_data_snk_latch_3rd_dword_q1), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_cur_lower_addr_22[1]), + .Q(com_tlm_u_tlm_rx_data_snk_cur_lower_addr[1]) + ); + FDE com_tlm_u_tlm_rx_data_snk_cur_lower_addr_0_ ( + .CE(com_tlm_u_tlm_rx_data_snk_latch_3rd_dword_q1), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_cur_lower_addr_22[0]), + .Q(com_tlm_u_tlm_rx_data_snk_cur_lower_addr[0]) + ); + FDE com_tlm_u_tlm_rx_data_snk_cur_length1 ( + .CE(com_tlm_u_tlm_rx_data_snk_latch_2nd_dword), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_cur_length1_2), + .Q(com_tlm_u_tlm_rx_data_snk_cur_length1_5126) + ); + FDE com_tlm_u_tlm_rx_data_snk_cur_fulltype_64 ( + .CE(com_tlm_u_tlm_rx_data_snk_latch_2nd_dword), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_N_10630_i), + .Q(com_tlm_u_tlm_rx_data_snk_cur_fulltype_64_5127) + ); + FDE com_tlm_u_tlm_rx_data_snk_cur_fulltype_mem ( + .CE(com_tlm_u_tlm_rx_data_snk_latch_2nd_dword), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_cur_fulltype_mem12_i_i), + .Q(com_tlm_u_tlm_rx_data_snk_cur_fulltype_mem_5128) + ); + FDE com_tlm_u_tlm_rx_data_snk_cur_lower_addr_6_ ( + .CE(com_tlm_u_tlm_rx_data_snk_latch_3rd_dword_q1), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_N_25253_i), + .Q(com_tlm_u_tlm_rx_data_snk_cur_lower_addr[6]) + ); + FDE com_tlm_u_tlm_rx_data_snk_cur_lower_addr_5_ ( + .CE(com_tlm_u_tlm_rx_data_snk_latch_3rd_dword_q1), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_N_25251_i), + .Q(com_tlm_u_tlm_rx_data_snk_cur_lower_addr[5]) + ); + FDE com_tlm_u_tlm_rx_data_snk_cur_lower_addr_4_ ( + .CE(com_tlm_u_tlm_rx_data_snk_latch_3rd_dword_q1), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_N_25249_i), + .Q(com_tlm_u_tlm_rx_data_snk_cur_lower_addr[4]) + ); + FDE com_tlm_u_tlm_rx_data_snk_cur_lower_addr_3_ ( + .CE(com_tlm_u_tlm_rx_data_snk_latch_3rd_dword_q1), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_N_25247_i), + .Q(com_tlm_u_tlm_rx_data_snk_cur_lower_addr[3]) + ); + FDE com_tlm_u_tlm_rx_data_snk_cur_lower_addr_2_ ( + .CE(com_tlm_u_tlm_rx_data_snk_latch_3rd_dword_q1), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_N_25245_i), + .Q(com_tlm_u_tlm_rx_data_snk_cur_lower_addr[2]) + ); + FDE com_tlm_u_tlm_rx_data_snk_cur_fulltype_oh_7_ ( + .CE(com_tlm_u_tlm_rx_data_snk_latch_2nd_dword), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_N_10626_i), + .Q(com_tlm_u_tlm_rx_data_snk_cur_fulltype_oh_7__5129) + ); + FDE com_tlm_u_tlm_rx_data_snk_cur_fulltype_oh_5_ ( + .CE(com_tlm_u_tlm_rx_data_snk_latch_2nd_dword), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_cur_fulltype_oh35_i_a2_0_a2_0_a2_5130), + .Q(com_tlm_u_tlm_rx_data_snk_cur_fulltype_oh_5__5131) + ); + FDE com_tlm_u_tlm_rx_data_snk_cur_fulltype_oh_3_ ( + .CE(com_tlm_u_tlm_rx_data_snk_latch_2nd_dword), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_cur_fulltype_oh37), + .Q(com_tlm_u_tlm_rx_data_snk_cur_fulltype_oh_3__5132) + ); + FDE com_tlm_u_tlm_rx_data_snk_cur_fulltype_oh_0_ ( + .CE(com_tlm_u_tlm_rx_data_snk_latch_2nd_dword), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_cur_fulltype_oh40), + .Q(com_tlm_u_tlm_rx_data_snk_cur_fulltype_oh_0__5133) + ); + SRL16 com_tlm_u_tlm_rx_data_snk_d_o_62_I_1 ( + .D(com_lnk_rd[7]), + .Q(com_tlm_u_tlm_rx_data_snk_d_o_62_N_6), + .CLK(NlwRenamedSig_OI_trn_clk), + .A0(com_tlm_u_tlm_rx_data_snk_GND_5139), + .A1(com_tlm_u_tlm_rx_data_snk_GND_5139), + .A2(com_tlm_u_tlm_rx_data_snk_VCC_5140), + .A3(com_tlm_u_tlm_rx_data_snk_GND_5139) + ); + SRL16 com_tlm_u_tlm_rx_data_snk_d_o_61_I_1 ( + .D(com_tlm_u_tlm_rx_data_snk_lower_addr64_in_q[6]), + .Q(com_tlm_u_tlm_rx_data_snk_d_o_61_N_6), + .CLK(NlwRenamedSig_OI_trn_clk), + .A0(com_tlm_u_tlm_rx_data_snk_VCC_5140), + .A1(com_tlm_u_tlm_rx_data_snk_VCC_5140), + .A2(com_tlm_u_tlm_rx_data_snk_GND_5139), + .A3(com_tlm_u_tlm_rx_data_snk_GND_5139) + ); + SRL16 com_tlm_u_tlm_rx_data_snk_d_o_60_I_1 ( + .D(com_tlm_u_tlm_rx_data_snk_lower_addr64_in_q[5]), + .Q(com_tlm_u_tlm_rx_data_snk_d_o_60_N_6), + .CLK(NlwRenamedSig_OI_trn_clk), + .A0(com_tlm_u_tlm_rx_data_snk_VCC_5140), + .A1(com_tlm_u_tlm_rx_data_snk_VCC_5140), + .A2(com_tlm_u_tlm_rx_data_snk_GND_5139), + .A3(com_tlm_u_tlm_rx_data_snk_GND_5139) + ); + SRL16 com_tlm_u_tlm_rx_data_snk_d_o_59_I_1 ( + .D(com_tlm_u_tlm_rx_data_snk_lower_addr64_in_q[4]), + .Q(com_tlm_u_tlm_rx_data_snk_d_o_59_N_6), + .CLK(NlwRenamedSig_OI_trn_clk), + .A0(com_tlm_u_tlm_rx_data_snk_VCC_5140), + .A1(com_tlm_u_tlm_rx_data_snk_VCC_5140), + .A2(com_tlm_u_tlm_rx_data_snk_GND_5139), + .A3(com_tlm_u_tlm_rx_data_snk_GND_5139) + ); + SRL16 com_tlm_u_tlm_rx_data_snk_d_o_58_I_1 ( + .D(com_tlm_u_tlm_rx_data_snk_lower_addr64_in_q[3]), + .Q(com_tlm_u_tlm_rx_data_snk_d_o_58_N_6), + .CLK(NlwRenamedSig_OI_trn_clk), + .A0(com_tlm_u_tlm_rx_data_snk_VCC_5140), + .A1(com_tlm_u_tlm_rx_data_snk_VCC_5140), + .A2(com_tlm_u_tlm_rx_data_snk_GND_5139), + .A3(com_tlm_u_tlm_rx_data_snk_GND_5139) + ); + SRL16 com_tlm_u_tlm_rx_data_snk_d_o_57_I_1 ( + .D(com_tlm_u_tlm_rx_data_snk_lower_addr64_in_q[2]), + .Q(com_tlm_u_tlm_rx_data_snk_d_o_57_N_6), + .CLK(NlwRenamedSig_OI_trn_clk), + .A0(com_tlm_u_tlm_rx_data_snk_VCC_5140), + .A1(com_tlm_u_tlm_rx_data_snk_VCC_5140), + .A2(com_tlm_u_tlm_rx_data_snk_GND_5139), + .A3(com_tlm_u_tlm_rx_data_snk_GND_5139) + ); + SRL16 com_tlm_u_tlm_rx_data_snk_d_o_56_I_1 ( + .D(com_lnk_rd[1]), + .Q(com_tlm_u_tlm_rx_data_snk_d_o_56_N_6), + .CLK(NlwRenamedSig_OI_trn_clk), + .A0(com_tlm_u_tlm_rx_data_snk_GND_5139), + .A1(com_tlm_u_tlm_rx_data_snk_GND_5139), + .A2(com_tlm_u_tlm_rx_data_snk_VCC_5140), + .A3(com_tlm_u_tlm_rx_data_snk_GND_5139) + ); + SRL16 com_tlm_u_tlm_rx_data_snk_d_o_55_I_1 ( + .D(com_lnk_rd[0]), + .Q(com_tlm_u_tlm_rx_data_snk_d_o_55_N_6), + .CLK(NlwRenamedSig_OI_trn_clk), + .A0(com_tlm_u_tlm_rx_data_snk_GND_5139), + .A1(com_tlm_u_tlm_rx_data_snk_GND_5139), + .A2(com_tlm_u_tlm_rx_data_snk_VCC_5140), + .A3(com_tlm_u_tlm_rx_data_snk_GND_5139) + ); + SRL16 com_tlm_u_tlm_rx_data_snk_d_o_54_I_1 ( + .D(com_lnk_rd_6113[22]), + .Q(com_tlm_u_tlm_rx_data_snk_d_o_54_N_6), + .CLK(NlwRenamedSig_OI_trn_clk), + .A0(com_tlm_u_tlm_rx_data_snk_GND_5139), + .A1(com_tlm_u_tlm_rx_data_snk_GND_5139), + .A2(com_tlm_u_tlm_rx_data_snk_VCC_5140), + .A3(com_tlm_u_tlm_rx_data_snk_GND_5139) + ); + SRL16 com_tlm_u_tlm_rx_data_snk_d_o_53_I_1 ( + .D(com_lnk_rd_6113[21]), + .Q(com_tlm_u_tlm_rx_data_snk_d_o_53_N_6), + .CLK(NlwRenamedSig_OI_trn_clk), + .A0(com_tlm_u_tlm_rx_data_snk_GND_5139), + .A1(com_tlm_u_tlm_rx_data_snk_GND_5139), + .A2(com_tlm_u_tlm_rx_data_snk_VCC_5140), + .A3(com_tlm_u_tlm_rx_data_snk_GND_5139) + ); + SRL16 com_tlm_u_tlm_rx_data_snk_d_o_52_I_1 ( + .D(com_lnk_rd_6113[20]), + .Q(com_tlm_u_tlm_rx_data_snk_d_o_52_N_6), + .CLK(NlwRenamedSig_OI_trn_clk), + .A0(com_tlm_u_tlm_rx_data_snk_GND_5139), + .A1(com_tlm_u_tlm_rx_data_snk_GND_5139), + .A2(com_tlm_u_tlm_rx_data_snk_VCC_5140), + .A3(com_tlm_u_tlm_rx_data_snk_GND_5139) + ); + SRL16 com_tlm_u_tlm_rx_data_snk_d_o_51_I_1 ( + .D(com_lnk_rd_6113[19]), + .Q(com_tlm_u_tlm_rx_data_snk_d_o_51_N_6), + .CLK(NlwRenamedSig_OI_trn_clk), + .A0(com_tlm_u_tlm_rx_data_snk_GND_5139), + .A1(com_tlm_u_tlm_rx_data_snk_GND_5139), + .A2(com_tlm_u_tlm_rx_data_snk_VCC_5140), + .A3(com_tlm_u_tlm_rx_data_snk_GND_5139) + ); + SRL16 com_tlm_u_tlm_rx_data_snk_d_o_50_I_1 ( + .D(com_lnk_rd_6113[18]), + .Q(com_tlm_u_tlm_rx_data_snk_d_o_50_N_6), + .CLK(NlwRenamedSig_OI_trn_clk), + .A0(com_tlm_u_tlm_rx_data_snk_GND_5139), + .A1(com_tlm_u_tlm_rx_data_snk_GND_5139), + .A2(com_tlm_u_tlm_rx_data_snk_VCC_5140), + .A3(com_tlm_u_tlm_rx_data_snk_GND_5139) + ); + SRL16 com_tlm_u_tlm_rx_data_snk_d_o_49_I_1 ( + .D(com_lnk_rd_6113[17]), + .Q(com_tlm_u_tlm_rx_data_snk_d_o_49_N_6), + .CLK(NlwRenamedSig_OI_trn_clk), + .A0(com_tlm_u_tlm_rx_data_snk_GND_5139), + .A1(com_tlm_u_tlm_rx_data_snk_GND_5139), + .A2(com_tlm_u_tlm_rx_data_snk_VCC_5140), + .A3(com_tlm_u_tlm_rx_data_snk_GND_5139) + ); + SRL16 com_tlm_u_tlm_rx_data_snk_d_o_48_I_1 ( + .D(com_lnk_rd_6113[16]), + .Q(com_tlm_u_tlm_rx_data_snk_d_o_48_N_6), + .CLK(NlwRenamedSig_OI_trn_clk), + .A0(com_tlm_u_tlm_rx_data_snk_GND_5139), + .A1(com_tlm_u_tlm_rx_data_snk_GND_5139), + .A2(com_tlm_u_tlm_rx_data_snk_VCC_5140), + .A3(com_tlm_u_tlm_rx_data_snk_GND_5139) + ); + SRL16 com_tlm_u_tlm_rx_data_snk_d_o_47_I_1 ( + .D(com_lnk_rd_6113[15]), + .Q(com_tlm_u_tlm_rx_data_snk_d_o_47_N_6), + .CLK(NlwRenamedSig_OI_trn_clk), + .A0(com_tlm_u_tlm_rx_data_snk_GND_5139), + .A1(com_tlm_u_tlm_rx_data_snk_GND_5139), + .A2(com_tlm_u_tlm_rx_data_snk_VCC_5140), + .A3(com_tlm_u_tlm_rx_data_snk_GND_5139) + ); + SRL16 com_tlm_u_tlm_rx_data_snk_d_o_46_I_1 ( + .D(com_lnk_rd_6113[14]), + .Q(com_tlm_u_tlm_rx_data_snk_d_o_46_N_6), + .CLK(NlwRenamedSig_OI_trn_clk), + .A0(com_tlm_u_tlm_rx_data_snk_GND_5139), + .A1(com_tlm_u_tlm_rx_data_snk_GND_5139), + .A2(com_tlm_u_tlm_rx_data_snk_VCC_5140), + .A3(com_tlm_u_tlm_rx_data_snk_GND_5139) + ); + SRL16 com_tlm_u_tlm_rx_data_snk_d_o_45_I_1 ( + .D(com_lnk_rd_6113[13]), + .Q(com_tlm_u_tlm_rx_data_snk_d_o_45_N_6), + .CLK(NlwRenamedSig_OI_trn_clk), + .A0(com_tlm_u_tlm_rx_data_snk_GND_5139), + .A1(com_tlm_u_tlm_rx_data_snk_GND_5139), + .A2(com_tlm_u_tlm_rx_data_snk_VCC_5140), + .A3(com_tlm_u_tlm_rx_data_snk_GND_5139) + ); + SRL16 com_tlm_u_tlm_rx_data_snk_d_o_44_I_1 ( + .D(com_lnk_rd_6113[12]), + .Q(com_tlm_u_tlm_rx_data_snk_d_o_44_N_6), + .CLK(NlwRenamedSig_OI_trn_clk), + .A0(com_tlm_u_tlm_rx_data_snk_GND_5139), + .A1(com_tlm_u_tlm_rx_data_snk_GND_5139), + .A2(com_tlm_u_tlm_rx_data_snk_VCC_5140), + .A3(com_tlm_u_tlm_rx_data_snk_GND_5139) + ); + SRL16 com_tlm_u_tlm_rx_data_snk_d_o_43_I_1 ( + .D(com_lnk_rd_6113[11]), + .Q(com_tlm_u_tlm_rx_data_snk_d_o_43_N_6), + .CLK(NlwRenamedSig_OI_trn_clk), + .A0(com_tlm_u_tlm_rx_data_snk_GND_5139), + .A1(com_tlm_u_tlm_rx_data_snk_GND_5139), + .A2(com_tlm_u_tlm_rx_data_snk_VCC_5140), + .A3(com_tlm_u_tlm_rx_data_snk_GND_5139) + ); + SRL16 com_tlm_u_tlm_rx_data_snk_d_o_42_I_1 ( + .D(com_lnk_rd_6113[10]), + .Q(com_tlm_u_tlm_rx_data_snk_d_o_42_N_6), + .CLK(NlwRenamedSig_OI_trn_clk), + .A0(com_tlm_u_tlm_rx_data_snk_GND_5139), + .A1(com_tlm_u_tlm_rx_data_snk_GND_5139), + .A2(com_tlm_u_tlm_rx_data_snk_VCC_5140), + .A3(com_tlm_u_tlm_rx_data_snk_GND_5139) + ); + SRL16 com_tlm_u_tlm_rx_data_snk_d_o_41_I_1 ( + .D(com_lnk_rd_6113[9]), + .Q(com_tlm_u_tlm_rx_data_snk_d_o_41_N_6), + .CLK(NlwRenamedSig_OI_trn_clk), + .A0(com_tlm_u_tlm_rx_data_snk_GND_5139), + .A1(com_tlm_u_tlm_rx_data_snk_GND_5139), + .A2(com_tlm_u_tlm_rx_data_snk_VCC_5140), + .A3(com_tlm_u_tlm_rx_data_snk_GND_5139) + ); + SRL16 com_tlm_u_tlm_rx_data_snk_d_o_40_I_1 ( + .D(com_lnk_rd_6113[8]), + .Q(com_tlm_u_tlm_rx_data_snk_d_o_40_N_6), + .CLK(NlwRenamedSig_OI_trn_clk), + .A0(com_tlm_u_tlm_rx_data_snk_GND_5139), + .A1(com_tlm_u_tlm_rx_data_snk_GND_5139), + .A2(com_tlm_u_tlm_rx_data_snk_VCC_5140), + .A3(com_tlm_u_tlm_rx_data_snk_GND_5139) + ); + SRL16 com_tlm_u_tlm_rx_data_snk_d_o_39_I_1 ( + .D(com_tlm_u_tlm_rx_data_snk_lower_addr32_in_q[5]), + .Q(com_tlm_u_tlm_rx_data_snk_d_o_39_N_6), + .CLK(NlwRenamedSig_OI_trn_clk), + .A0(com_tlm_u_tlm_rx_data_snk_VCC_5140), + .A1(com_tlm_u_tlm_rx_data_snk_VCC_5140), + .A2(com_tlm_u_tlm_rx_data_snk_GND_5139), + .A3(com_tlm_u_tlm_rx_data_snk_GND_5139) + ); + SRL16 com_tlm_u_tlm_rx_data_snk_d_o_38_I_1 ( + .D(com_tlm_u_tlm_rx_data_snk_lower_addr32_in_q[4]), + .Q(com_tlm_u_tlm_rx_data_snk_d_o_38_N_6), + .CLK(NlwRenamedSig_OI_trn_clk), + .A0(com_tlm_u_tlm_rx_data_snk_VCC_5140), + .A1(com_tlm_u_tlm_rx_data_snk_VCC_5140), + .A2(com_tlm_u_tlm_rx_data_snk_GND_5139), + .A3(com_tlm_u_tlm_rx_data_snk_GND_5139) + ); + SRL16 com_tlm_u_tlm_rx_data_snk_d_o_37_I_1 ( + .D(com_tlm_u_tlm_rx_data_snk_lower_addr32_in_q[3]), + .Q(com_tlm_u_tlm_rx_data_snk_d_o_37_N_6), + .CLK(NlwRenamedSig_OI_trn_clk), + .A0(com_tlm_u_tlm_rx_data_snk_VCC_5140), + .A1(com_tlm_u_tlm_rx_data_snk_VCC_5140), + .A2(com_tlm_u_tlm_rx_data_snk_GND_5139), + .A3(com_tlm_u_tlm_rx_data_snk_GND_5139) + ); + SRL16 com_tlm_u_tlm_rx_data_snk_d_o_36_I_1 ( + .D(com_tlm_u_tlm_rx_data_snk_lower_addr32_in_q[2]), + .Q(com_tlm_u_tlm_rx_data_snk_d_o_36_N_6), + .CLK(NlwRenamedSig_OI_trn_clk), + .A0(com_tlm_u_tlm_rx_data_snk_VCC_5140), + .A1(com_tlm_u_tlm_rx_data_snk_VCC_5140), + .A2(com_tlm_u_tlm_rx_data_snk_GND_5139), + .A3(com_tlm_u_tlm_rx_data_snk_GND_5139) + ); + SRL16 com_tlm_u_tlm_rx_data_snk_d_o_35_I_1 ( + .D(com_lnk_rd_6113[33]), + .Q(com_tlm_u_tlm_rx_data_snk_d_o_35_N_6), + .CLK(NlwRenamedSig_OI_trn_clk), + .A0(com_tlm_u_tlm_rx_data_snk_GND_5139), + .A1(com_tlm_u_tlm_rx_data_snk_GND_5139), + .A2(com_tlm_u_tlm_rx_data_snk_VCC_5140), + .A3(com_tlm_u_tlm_rx_data_snk_GND_5139) + ); + SRL16 com_tlm_u_tlm_rx_data_snk_d_o_34_I_1 ( + .D(com_lnk_rd_6113[32]), + .Q(com_tlm_u_tlm_rx_data_snk_d_o_34_N_6), + .CLK(NlwRenamedSig_OI_trn_clk), + .A0(com_tlm_u_tlm_rx_data_snk_GND_5139), + .A1(com_tlm_u_tlm_rx_data_snk_GND_5139), + .A2(com_tlm_u_tlm_rx_data_snk_VCC_5140), + .A3(com_tlm_u_tlm_rx_data_snk_GND_5139) + ); + SRL16 com_tlm_u_tlm_rx_data_snk_d_o_33_I_1 ( + .D(com_lnk_rd_6113[31]), + .Q(com_tlm_u_tlm_rx_data_snk_d_o_33_N_6), + .CLK(NlwRenamedSig_OI_trn_clk), + .A0(com_tlm_u_tlm_rx_data_snk_GND_5139), + .A1(com_tlm_u_tlm_rx_data_snk_GND_5139), + .A2(com_tlm_u_tlm_rx_data_snk_VCC_5140), + .A3(com_tlm_u_tlm_rx_data_snk_GND_5139) + ); + SRL16 com_tlm_u_tlm_rx_data_snk_d_o_32_I_1 ( + .D(com_lnk_rd_6113[30]), + .Q(com_tlm_u_tlm_rx_data_snk_d_o_32_N_6), + .CLK(NlwRenamedSig_OI_trn_clk), + .A0(com_tlm_u_tlm_rx_data_snk_GND_5139), + .A1(com_tlm_u_tlm_rx_data_snk_GND_5139), + .A2(com_tlm_u_tlm_rx_data_snk_VCC_5140), + .A3(com_tlm_u_tlm_rx_data_snk_GND_5139) + ); + SRL16 com_tlm_u_tlm_rx_data_snk_d_o_31_I_1 ( + .D(com_lnk_rd_6113[29]), + .Q(com_tlm_u_tlm_rx_data_snk_d_o_31_N_6), + .CLK(NlwRenamedSig_OI_trn_clk), + .A0(com_tlm_u_tlm_rx_data_snk_GND_5139), + .A1(com_tlm_u_tlm_rx_data_snk_GND_5139), + .A2(com_tlm_u_tlm_rx_data_snk_VCC_5140), + .A3(com_tlm_u_tlm_rx_data_snk_GND_5139) + ); + SRL16 com_tlm_u_tlm_rx_data_snk_d_o_30_I_1 ( + .D(com_lnk_rd_6113[28]), + .Q(com_tlm_u_tlm_rx_data_snk_d_o_30_N_6), + .CLK(NlwRenamedSig_OI_trn_clk), + .A0(com_tlm_u_tlm_rx_data_snk_GND_5139), + .A1(com_tlm_u_tlm_rx_data_snk_GND_5139), + .A2(com_tlm_u_tlm_rx_data_snk_VCC_5140), + .A3(com_tlm_u_tlm_rx_data_snk_GND_5139) + ); + SRL16 com_tlm_u_tlm_rx_data_snk_d_o_29_I_1 ( + .D(com_lnk_rd_6113[27]), + .Q(com_tlm_u_tlm_rx_data_snk_d_o_29_N_6), + .CLK(NlwRenamedSig_OI_trn_clk), + .A0(com_tlm_u_tlm_rx_data_snk_GND_5139), + .A1(com_tlm_u_tlm_rx_data_snk_GND_5139), + .A2(com_tlm_u_tlm_rx_data_snk_VCC_5140), + .A3(com_tlm_u_tlm_rx_data_snk_GND_5139) + ); + SRL16 com_tlm_u_tlm_rx_data_snk_d_o_28_I_1 ( + .D(com_lnk_rd_6113[26]), + .Q(com_tlm_u_tlm_rx_data_snk_d_o_28_N_6), + .CLK(NlwRenamedSig_OI_trn_clk), + .A0(com_tlm_u_tlm_rx_data_snk_GND_5139), + .A1(com_tlm_u_tlm_rx_data_snk_GND_5139), + .A2(com_tlm_u_tlm_rx_data_snk_VCC_5140), + .A3(com_tlm_u_tlm_rx_data_snk_GND_5139) + ); + SRL16 com_tlm_u_tlm_rx_data_snk_d_o_27_I_1 ( + .D(com_lnk_rd_6113[25]), + .Q(com_tlm_u_tlm_rx_data_snk_d_o_27_N_6), + .CLK(NlwRenamedSig_OI_trn_clk), + .A0(com_tlm_u_tlm_rx_data_snk_GND_5139), + .A1(com_tlm_u_tlm_rx_data_snk_GND_5139), + .A2(com_tlm_u_tlm_rx_data_snk_VCC_5140), + .A3(com_tlm_u_tlm_rx_data_snk_GND_5139) + ); + SRL16 com_tlm_u_tlm_rx_data_snk_d_o_26_I_1 ( + .D(com_lnk_rd_6113[24]), + .Q(com_tlm_u_tlm_rx_data_snk_d_o_26_N_6), + .CLK(NlwRenamedSig_OI_trn_clk), + .A0(com_tlm_u_tlm_rx_data_snk_GND_5139), + .A1(com_tlm_u_tlm_rx_data_snk_GND_5139), + .A2(com_tlm_u_tlm_rx_data_snk_VCC_5140), + .A3(com_tlm_u_tlm_rx_data_snk_GND_5139) + ); + SRL16 com_tlm_u_tlm_rx_data_snk_d_o_25_I_1 ( + .D(com_lnk_rd_6113[23]), + .Q(com_tlm_u_tlm_rx_data_snk_d_o_25_N_6), + .CLK(NlwRenamedSig_OI_trn_clk), + .A0(com_tlm_u_tlm_rx_data_snk_GND_5139), + .A1(com_tlm_u_tlm_rx_data_snk_GND_5139), + .A2(com_tlm_u_tlm_rx_data_snk_VCC_5140), + .A3(com_tlm_u_tlm_rx_data_snk_GND_5139) + ); + SRL16 com_tlm_u_tlm_rx_data_snk_d_o_24_I_1 ( + .D(com_lnk_rd_6113[52]), + .Q(com_tlm_u_tlm_rx_data_snk_d_o_24_N_6), + .CLK(NlwRenamedSig_OI_trn_clk), + .A0(com_tlm_u_tlm_rx_data_snk_GND_5139), + .A1(com_tlm_u_tlm_rx_data_snk_GND_5139), + .A2(com_tlm_u_tlm_rx_data_snk_VCC_5140), + .A3(com_tlm_u_tlm_rx_data_snk_GND_5139) + ); + SRL16 com_tlm_u_tlm_rx_data_snk_d_o_23_I_1 ( + .D(com_lnk_rd_6113[51]), + .Q(com_tlm_u_tlm_rx_data_snk_d_o_23_N_6), + .CLK(NlwRenamedSig_OI_trn_clk), + .A0(com_tlm_u_tlm_rx_data_snk_GND_5139), + .A1(com_tlm_u_tlm_rx_data_snk_GND_5139), + .A2(com_tlm_u_tlm_rx_data_snk_VCC_5140), + .A3(com_tlm_u_tlm_rx_data_snk_GND_5139) + ); + SRL16 com_tlm_u_tlm_rx_data_snk_d_o_22_I_1 ( + .D(com_lnk_rd_6113[50]), + .Q(com_tlm_u_tlm_rx_data_snk_d_o_22_N_6), + .CLK(NlwRenamedSig_OI_trn_clk), + .A0(com_tlm_u_tlm_rx_data_snk_GND_5139), + .A1(com_tlm_u_tlm_rx_data_snk_GND_5139), + .A2(com_tlm_u_tlm_rx_data_snk_VCC_5140), + .A3(com_tlm_u_tlm_rx_data_snk_GND_5139) + ); + SRL16 com_tlm_u_tlm_rx_data_snk_d_o_21_I_1 ( + .D(com_lnk_rd_6113[49]), + .Q(com_tlm_u_tlm_rx_data_snk_d_o_21_N_6), + .CLK(NlwRenamedSig_OI_trn_clk), + .A0(com_tlm_u_tlm_rx_data_snk_GND_5139), + .A1(com_tlm_u_tlm_rx_data_snk_GND_5139), + .A2(com_tlm_u_tlm_rx_data_snk_VCC_5140), + .A3(com_tlm_u_tlm_rx_data_snk_GND_5139) + ); + SRL16 com_tlm_u_tlm_rx_data_snk_d_o_20_I_1 ( + .D(com_lnk_rd_6113[48]), + .Q(com_tlm_u_tlm_rx_data_snk_d_o_20_N_6), + .CLK(NlwRenamedSig_OI_trn_clk), + .A0(com_tlm_u_tlm_rx_data_snk_GND_5139), + .A1(com_tlm_u_tlm_rx_data_snk_GND_5139), + .A2(com_tlm_u_tlm_rx_data_snk_VCC_5140), + .A3(com_tlm_u_tlm_rx_data_snk_GND_5139) + ); + SRL16 com_tlm_u_tlm_rx_data_snk_d_o_19_I_1 ( + .D(com_tlm_u_tlm_rx_data_snk_N_17287_i), + .Q(com_tlm_u_tlm_rx_data_snk_d_o_19_N_6), + .CLK(NlwRenamedSig_OI_trn_clk), + .A0(com_tlm_u_tlm_rx_data_snk_GND_5139), + .A1(com_tlm_u_tlm_rx_data_snk_GND_5139), + .A2(com_tlm_u_tlm_rx_data_snk_VCC_5140), + .A3(com_tlm_u_tlm_rx_data_snk_GND_5139) + ); + SRL16 com_tlm_u_tlm_rx_data_snk_d_o_18_I_1 ( + .D(com_lnk_rd_6113[46]), + .Q(com_tlm_u_tlm_rx_data_snk_d_o_18_N_6), + .CLK(NlwRenamedSig_OI_trn_clk), + .A0(com_tlm_u_tlm_rx_data_snk_GND_5139), + .A1(com_tlm_u_tlm_rx_data_snk_GND_5139), + .A2(com_tlm_u_tlm_rx_data_snk_VCC_5140), + .A3(com_tlm_u_tlm_rx_data_snk_GND_5139) + ); + SRL16 com_tlm_u_tlm_rx_data_snk_d_o_17_I_1 ( + .D(com_lnk_rd_6113[45]), + .Q(com_tlm_u_tlm_rx_data_snk_d_o_17_N_6), + .CLK(NlwRenamedSig_OI_trn_clk), + .A0(com_tlm_u_tlm_rx_data_snk_GND_5139), + .A1(com_tlm_u_tlm_rx_data_snk_GND_5139), + .A2(com_tlm_u_tlm_rx_data_snk_VCC_5140), + .A3(com_tlm_u_tlm_rx_data_snk_GND_5139) + ); + SRL16 com_tlm_u_tlm_rx_data_snk_d_o_16_I_1 ( + .D(com_lnk_rd_6113[44]), + .Q(com_tlm_u_tlm_rx_data_snk_d_o_16_N_6), + .CLK(NlwRenamedSig_OI_trn_clk), + .A0(com_tlm_u_tlm_rx_data_snk_GND_5139), + .A1(com_tlm_u_tlm_rx_data_snk_GND_5139), + .A2(com_tlm_u_tlm_rx_data_snk_VCC_5140), + .A3(com_tlm_u_tlm_rx_data_snk_GND_5139) + ); + SRL16 com_tlm_u_tlm_rx_data_snk_d_o_15_I_1 ( + .D(com_lnk_rd_6113[43]), + .Q(com_tlm_u_tlm_rx_data_snk_d_o_15_N_6), + .CLK(NlwRenamedSig_OI_trn_clk), + .A0(com_tlm_u_tlm_rx_data_snk_GND_5139), + .A1(com_tlm_u_tlm_rx_data_snk_GND_5139), + .A2(com_tlm_u_tlm_rx_data_snk_VCC_5140), + .A3(com_tlm_u_tlm_rx_data_snk_GND_5139) + ); + SRL16 com_tlm_u_tlm_rx_data_snk_d_o_14_I_1 ( + .D(com_lnk_rd_6113[42]), + .Q(com_tlm_u_tlm_rx_data_snk_d_o_14_N_6), + .CLK(NlwRenamedSig_OI_trn_clk), + .A0(com_tlm_u_tlm_rx_data_snk_GND_5139), + .A1(com_tlm_u_tlm_rx_data_snk_GND_5139), + .A2(com_tlm_u_tlm_rx_data_snk_VCC_5140), + .A3(com_tlm_u_tlm_rx_data_snk_GND_5139) + ); + SRL16 com_tlm_u_tlm_rx_data_snk_d_o_13_I_1 ( + .D(com_lnk_rd_6113[41]), + .Q(com_tlm_u_tlm_rx_data_snk_d_o_13_N_6), + .CLK(NlwRenamedSig_OI_trn_clk), + .A0(com_tlm_u_tlm_rx_data_snk_GND_5139), + .A1(com_tlm_u_tlm_rx_data_snk_GND_5139), + .A2(com_tlm_u_tlm_rx_data_snk_VCC_5140), + .A3(com_tlm_u_tlm_rx_data_snk_GND_5139) + ); + SRL16 com_tlm_u_tlm_rx_data_snk_d_o_12_I_1 ( + .D(com_lnk_rd_6113[40]), + .Q(com_tlm_u_tlm_rx_data_snk_d_o_12_N_6), + .CLK(NlwRenamedSig_OI_trn_clk), + .A0(com_tlm_u_tlm_rx_data_snk_GND_5139), + .A1(com_tlm_u_tlm_rx_data_snk_GND_5139), + .A2(com_tlm_u_tlm_rx_data_snk_VCC_5140), + .A3(com_tlm_u_tlm_rx_data_snk_GND_5139) + ); + SRL16 com_tlm_u_tlm_rx_data_snk_d_o_11_I_1 ( + .D(com_lnk_rd_6113[39]), + .Q(com_tlm_u_tlm_rx_data_snk_d_o_11_N_6), + .CLK(NlwRenamedSig_OI_trn_clk), + .A0(com_tlm_u_tlm_rx_data_snk_GND_5139), + .A1(com_tlm_u_tlm_rx_data_snk_GND_5139), + .A2(com_tlm_u_tlm_rx_data_snk_VCC_5140), + .A3(com_tlm_u_tlm_rx_data_snk_GND_5139) + ); + SRL16 com_tlm_u_tlm_rx_data_snk_d_o_10_I_1 ( + .D(com_tlm_u_tlm_rx_data_snk_lower_addr32_in_q[6]), + .Q(com_tlm_u_tlm_rx_data_snk_d_o_10_N_6), + .CLK(NlwRenamedSig_OI_trn_clk), + .A0(com_tlm_u_tlm_rx_data_snk_VCC_5140), + .A1(com_tlm_u_tlm_rx_data_snk_VCC_5140), + .A2(com_tlm_u_tlm_rx_data_snk_GND_5139), + .A3(com_tlm_u_tlm_rx_data_snk_GND_5139) + ); + SRL16 com_tlm_u_tlm_rx_data_snk_eof_nd_q_I_1 ( + .D(com_tlm_u_tlm_rx_data_snk_eof_nd_q_1__5134), + .Q(com_tlm_u_tlm_rx_data_snk_eof_nd_q_N_6), + .CLK(NlwRenamedSig_OI_trn_clk), + .A0(com_tlm_u_tlm_rx_data_snk_VCC_5140), + .A1(com_tlm_u_tlm_rx_data_snk_GND_5139), + .A2(com_tlm_u_tlm_rx_data_snk_GND_5139), + .A3(com_tlm_u_tlm_rx_data_snk_GND_5139) + ); + SRL16 com_tlm_u_tlm_rx_data_snk_d_o_9_I_1 ( + .D(com_lnk_rd_6113[63]), + .Q(com_tlm_u_tlm_rx_data_snk_d_o_9_N_6), + .CLK(NlwRenamedSig_OI_trn_clk), + .A0(com_tlm_u_tlm_rx_data_snk_GND_5139), + .A1(com_tlm_u_tlm_rx_data_snk_GND_5139), + .A2(com_tlm_u_tlm_rx_data_snk_VCC_5140), + .A3(com_tlm_u_tlm_rx_data_snk_GND_5139) + ); + SRL16 com_tlm_u_tlm_rx_data_snk_d_o_8_I_1 ( + .D(com_lnk_rd_6113[62]), + .Q(com_tlm_u_tlm_rx_data_snk_d_o_8_N_6), + .CLK(NlwRenamedSig_OI_trn_clk), + .A0(com_tlm_u_tlm_rx_data_snk_GND_5139), + .A1(com_tlm_u_tlm_rx_data_snk_GND_5139), + .A2(com_tlm_u_tlm_rx_data_snk_VCC_5140), + .A3(com_tlm_u_tlm_rx_data_snk_GND_5139) + ); + SRL16 com_tlm_u_tlm_rx_data_snk_d_o_7_I_1 ( + .D(com_lnk_rd_6113[61]), + .Q(com_tlm_u_tlm_rx_data_snk_d_o_7_N_6), + .CLK(NlwRenamedSig_OI_trn_clk), + .A0(com_tlm_u_tlm_rx_data_snk_GND_5139), + .A1(com_tlm_u_tlm_rx_data_snk_GND_5139), + .A2(com_tlm_u_tlm_rx_data_snk_VCC_5140), + .A3(com_tlm_u_tlm_rx_data_snk_GND_5139) + ); + SRL16 com_tlm_u_tlm_rx_data_snk_d_o_6_I_1 ( + .D(com_lnk_rd_6113[60]), + .Q(com_tlm_u_tlm_rx_data_snk_d_o_6_N_6), + .CLK(NlwRenamedSig_OI_trn_clk), + .A0(com_tlm_u_tlm_rx_data_snk_GND_5139), + .A1(com_tlm_u_tlm_rx_data_snk_GND_5139), + .A2(com_tlm_u_tlm_rx_data_snk_VCC_5140), + .A3(com_tlm_u_tlm_rx_data_snk_GND_5139) + ); + SRL16 com_tlm_u_tlm_rx_data_snk_d_o_5_I_1 ( + .D(com_lnk_rd_6113[59]), + .Q(com_tlm_u_tlm_rx_data_snk_d_o_5_N_6), + .CLK(NlwRenamedSig_OI_trn_clk), + .A0(com_tlm_u_tlm_rx_data_snk_GND_5139), + .A1(com_tlm_u_tlm_rx_data_snk_GND_5139), + .A2(com_tlm_u_tlm_rx_data_snk_VCC_5140), + .A3(com_tlm_u_tlm_rx_data_snk_GND_5139) + ); + SRL16 com_tlm_u_tlm_rx_data_snk_d_o_4_I_1 ( + .D(com_lnk_rd_6113[58]), + .Q(com_tlm_u_tlm_rx_data_snk_d_o_4_N_6), + .CLK(NlwRenamedSig_OI_trn_clk), + .A0(com_tlm_u_tlm_rx_data_snk_GND_5139), + .A1(com_tlm_u_tlm_rx_data_snk_GND_5139), + .A2(com_tlm_u_tlm_rx_data_snk_VCC_5140), + .A3(com_tlm_u_tlm_rx_data_snk_GND_5139) + ); + SRL16 com_tlm_u_tlm_rx_data_snk_d_o_3_I_1 ( + .D(com_lnk_rd_6113[57]), + .Q(com_tlm_u_tlm_rx_data_snk_d_o_3_N_6), + .CLK(NlwRenamedSig_OI_trn_clk), + .A0(com_tlm_u_tlm_rx_data_snk_GND_5139), + .A1(com_tlm_u_tlm_rx_data_snk_GND_5139), + .A2(com_tlm_u_tlm_rx_data_snk_VCC_5140), + .A3(com_tlm_u_tlm_rx_data_snk_GND_5139) + ); + SRL16 com_tlm_u_tlm_rx_data_snk_d_o_2_I_1 ( + .D(com_lnk_rd_6113[56]), + .Q(com_tlm_u_tlm_rx_data_snk_d_o_2_N_6), + .CLK(NlwRenamedSig_OI_trn_clk), + .A0(com_tlm_u_tlm_rx_data_snk_GND_5139), + .A1(com_tlm_u_tlm_rx_data_snk_GND_5139), + .A2(com_tlm_u_tlm_rx_data_snk_VCC_5140), + .A3(com_tlm_u_tlm_rx_data_snk_GND_5139) + ); + SRL16 com_tlm_u_tlm_rx_data_snk_d_o_1_I_1 ( + .D(com_lnk_rd_6113[55]), + .Q(com_tlm_u_tlm_rx_data_snk_d_o_1_N_6), + .CLK(NlwRenamedSig_OI_trn_clk), + .A0(com_tlm_u_tlm_rx_data_snk_GND_5139), + .A1(com_tlm_u_tlm_rx_data_snk_GND_5139), + .A2(com_tlm_u_tlm_rx_data_snk_VCC_5140), + .A3(com_tlm_u_tlm_rx_data_snk_GND_5139) + ); + SRL16 com_tlm_u_tlm_rx_data_snk_d_o_0_I_1 ( + .D(com_lnk_rd_6113[54]), + .Q(com_tlm_u_tlm_rx_data_snk_d_o_0_N_6), + .CLK(NlwRenamedSig_OI_trn_clk), + .A0(com_tlm_u_tlm_rx_data_snk_GND_5139), + .A1(com_tlm_u_tlm_rx_data_snk_GND_5139), + .A2(com_tlm_u_tlm_rx_data_snk_VCC_5140), + .A3(com_tlm_u_tlm_rx_data_snk_GND_5139) + ); + SRL16 com_tlm_u_tlm_rx_data_snk_d_o_I_1 ( + .D(com_lnk_rd_6113[53]), + .Q(com_tlm_u_tlm_rx_data_snk_d_o_N_6), + .CLK(NlwRenamedSig_OI_trn_clk), + .A0(com_tlm_u_tlm_rx_data_snk_GND_5139), + .A1(com_tlm_u_tlm_rx_data_snk_GND_5139), + .A2(com_tlm_u_tlm_rx_data_snk_VCC_5140), + .A3(com_tlm_u_tlm_rx_data_snk_GND_5139) + ); + SRL16 com_tlm_u_tlm_rx_data_snk_sof_q_I_1 ( + .D(com_tlm_u_tlm_rx_data_snk_sof_q_1__5135), + .Q(com_tlm_u_tlm_rx_data_snk_sof_q_N_6), + .CLK(NlwRenamedSig_OI_trn_clk), + .A0(com_tlm_u_tlm_rx_data_snk_VCC_5140), + .A1(com_tlm_u_tlm_rx_data_snk_GND_5139), + .A2(com_tlm_u_tlm_rx_data_snk_GND_5139), + .A3(com_tlm_u_tlm_rx_data_snk_GND_5139) + ); + SRL16 com_tlm_u_tlm_rx_data_snk_rem_q_I_1 ( + .D(com_tlm_u_tlm_rx_data_snk_rem_q_1__5136), + .Q(com_tlm_u_tlm_rx_data_snk_rem_q_N_6), + .CLK(NlwRenamedSig_OI_trn_clk), + .A0(com_tlm_u_tlm_rx_data_snk_VCC_5140), + .A1(com_tlm_u_tlm_rx_data_snk_GND_5139), + .A2(com_tlm_u_tlm_rx_data_snk_GND_5139), + .A3(com_tlm_u_tlm_rx_data_snk_GND_5139) + ); + SRL16 com_tlm_u_tlm_rx_data_snk_dsc_q_I_1 ( + .D(com_tlm_u_tlm_rx_data_snk_dsc_q_1__5137), + .Q(com_tlm_u_tlm_rx_data_snk_dsc_q_N_6), + .CLK(NlwRenamedSig_OI_trn_clk), + .A0(com_tlm_u_tlm_rx_data_snk_VCC_5140), + .A1(com_tlm_u_tlm_rx_data_snk_GND_5139), + .A2(com_tlm_u_tlm_rx_data_snk_GND_5139), + .A3(com_tlm_u_tlm_rx_data_snk_GND_5139) + ); + SRL16 com_tlm_u_tlm_rx_data_snk_src_rdy_q_I_1 ( + .D(com_tlm_u_tlm_rx_data_snk_src_rdy_q_1__5138), + .Q(com_tlm_u_tlm_rx_data_snk_src_rdy_q_N_6), + .CLK(NlwRenamedSig_OI_trn_clk), + .A0(com_tlm_u_tlm_rx_data_snk_VCC_5140), + .A1(com_tlm_u_tlm_rx_data_snk_GND_5139), + .A2(com_tlm_u_tlm_rx_data_snk_GND_5139), + .A3(com_tlm_u_tlm_rx_data_snk_GND_5139) + ); + defparam com_tlm_u_tlm_rx_data_snk_next_cur_drop.INIT = 4'h4; + LUT2_L com_tlm_u_tlm_rx_data_snk_next_cur_drop ( + .I0(com_tlm_u_tlm_rx_data_snk_N_10631), + .I1(com_tlm_u_tlm_rx_data_snk_eof_o_3), + .LO(com_tlm_u_tlm_rx_data_snk_next_cur_drop_5141) + ); + defparam com_tlm_u_tlm_rx_data_snk_un4_cur_byte_ct_s_10_sf.INIT = 4'h1; + LUT1 com_tlm_u_tlm_rx_data_snk_un4_cur_byte_ct_s_10_sf ( + .I0(com_tlm_u_tlm_rx_data_snk_cur_length_8__12), + .O(com_tlm_u_tlm_rx_data_snk_un4_cur_byte_ct_s_10_sf_5142) + ); + defparam com_tlm_u_tlm_rx_data_snk_un4_cur_byte_ct_s_9_sf.INIT = 4'h1; + LUT1 com_tlm_u_tlm_rx_data_snk_un4_cur_byte_ct_s_9_sf ( + .I0(com_tlm_u_tlm_rx_data_snk_cur_length[7]), + .O(com_tlm_u_tlm_rx_data_snk_un4_cur_byte_ct_s_9_sf_5143) + ); + defparam com_tlm_u_tlm_rx_data_snk_un4_cur_byte_ct_s_8_sf.INIT = 4'h1; + LUT1 com_tlm_u_tlm_rx_data_snk_un4_cur_byte_ct_s_8_sf ( + .I0(com_tlm_u_tlm_rx_data_snk_cur_length[6]), + .O(com_tlm_u_tlm_rx_data_snk_un4_cur_byte_ct_s_8_sf_5144) + ); + defparam com_tlm_u_tlm_rx_data_snk_un4_cur_byte_ct_s_7_sf.INIT = 4'h1; + LUT1 com_tlm_u_tlm_rx_data_snk_un4_cur_byte_ct_s_7_sf ( + .I0(com_tlm_u_tlm_rx_data_snk_cur_length[5]), + .O(com_tlm_u_tlm_rx_data_snk_un4_cur_byte_ct_s_7_sf_5145) + ); + defparam com_tlm_u_tlm_rx_data_snk_un4_cur_byte_ct_s_6_sf.INIT = 4'h1; + LUT1 com_tlm_u_tlm_rx_data_snk_un4_cur_byte_ct_s_6_sf ( + .I0(com_tlm_u_tlm_rx_data_snk_cur_length_4__10), + .O(com_tlm_u_tlm_rx_data_snk_un4_cur_byte_ct_s_6_sf_5146) + ); + defparam com_tlm_u_tlm_rx_data_snk_un4_cur_byte_ct_s_5_sf.INIT = 4'h1; + LUT1 com_tlm_u_tlm_rx_data_snk_un4_cur_byte_ct_s_5_sf ( + .I0(com_tlm_u_tlm_rx_data_snk_cur_length_3__8), + .O(com_tlm_u_tlm_rx_data_snk_un4_cur_byte_ct_s_5_sf_5147) + ); + defparam com_tlm_u_tlm_rx_data_snk_un4_cur_byte_ct_s_4_sf.INIT = 4'h1; + LUT1 com_tlm_u_tlm_rx_data_snk_un4_cur_byte_ct_s_4_sf ( + .I0(com_tlm_u_tlm_rx_data_snk_cur_length_2__6), + .O(com_tlm_u_tlm_rx_data_snk_un4_cur_byte_ct_s_4_sf_5148) + ); + defparam com_tlm_u_tlm_rx_data_snk_un4_cur_byte_ct_s_3_sf.INIT = 4'h1; + LUT1 com_tlm_u_tlm_rx_data_snk_un4_cur_byte_ct_s_3_sf ( + .I0(com_tlm_u_tlm_rx_data_snk_cur_length_1__4), + .O(com_tlm_u_tlm_rx_data_snk_un4_cur_byte_ct_s_3_sf_5149) + ); + defparam com_tlm_u_tlm_rx_data_snk_un4_cur_byte_ct_axb_2.INIT = 4'h9; + LUT2 com_tlm_u_tlm_rx_data_snk_un4_cur_byte_ct_axb_2 ( + .I0(com_tlm_u_tlm_rx_data_snk_cur_bytes_missing[2]), + .I1(com_tlm_u_tlm_rx_data_snk_cur_length_0__2), + .O(com_tlm_u_tlm_rx_data_snk_un4_cur_byte_ct_axb_2_5150) + ); + defparam com_tlm_u_tlm_rx_data_snk_un4_cur_byte_ct_axb_1.INIT = 4'h1; + LUT1 com_tlm_u_tlm_rx_data_snk_un4_cur_byte_ct_axb_1 ( + .I0(com_tlm_u_tlm_rx_data_snk_cur_bytes_missing[1]), + .O(com_tlm_u_tlm_rx_data_snk_un4_cur_byte_ct_axb_1_5151) + ); + defparam com_tlm_u_tlm_rx_data_snk_un4_cur_byte_ct_cry_0_sf.INIT = 4'h2; + LUT1 com_tlm_u_tlm_rx_data_snk_un4_cur_byte_ct_cry_0_sf ( + .I0(com_tlm_u_tlm_rx_data_snk_cur_bytes_missing[0]), + .O(com_tlm_u_tlm_rx_data_snk_un4_cur_byte_ct_cry_0_sf_5152) + ); + VCC com_tlm_u_tlm_rx_data_snk_malformed_checks_VCC ( + .P(com_tlm_u_tlm_rx_data_snk_malformed_checks_VCC_5179) + ); + GND com_tlm_u_tlm_rx_data_snk_malformed_checks_GND ( + .G(com_tlm_u_tlm_rx_data_snk_malformed_checks_GND_5170) + ); + FDRE com_tlm_u_tlm_rx_data_snk_malformed_checks_word_ct_0_ ( + .CE(com_tlm_u_tlm_rx_data_snk_malformed_checks_delay_ct_i_5241), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_malformed_checks_word_ct_d_i[0]), + .Q(com_tlm_u_tlm_rx_data_snk_malformed_checks_word_ct[0]), + .R(plm_link_up_i) + ); + FDRE com_tlm_u_tlm_rx_data_snk_malformed_checks_word_ct_1_ ( + .CE(com_tlm_u_tlm_rx_data_snk_malformed_checks_delay_ct_i_5241), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_malformed_checks_un4_word_ct_s_1_5171), + .Q(com_tlm_u_tlm_rx_data_snk_malformed_checks_word_ct[1]), + .R(plm_link_up_i) + ); + FDRE com_tlm_u_tlm_rx_data_snk_malformed_checks_word_ct_2_ ( + .CE(com_tlm_u_tlm_rx_data_snk_malformed_checks_delay_ct_i_5241), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_malformed_checks_un4_word_ct_s_2_5173), + .Q(com_tlm_u_tlm_rx_data_snk_malformed_checks_word_ct[2]), + .R(plm_link_up_i) + ); + FDRE com_tlm_u_tlm_rx_data_snk_malformed_checks_word_ct_3_ ( + .CE(com_tlm_u_tlm_rx_data_snk_malformed_checks_delay_ct_i_5241), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_malformed_checks_un4_word_ct_s_3_5175), + .Q(com_tlm_u_tlm_rx_data_snk_malformed_checks_word_ct[3]), + .R(plm_link_up_i) + ); + FDRE com_tlm_u_tlm_rx_data_snk_malformed_checks_word_ct_4_ ( + .CE(com_tlm_u_tlm_rx_data_snk_malformed_checks_delay_ct_i_5241), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_malformed_checks_un4_word_ct_s_4_5177), + .Q(com_tlm_u_tlm_rx_data_snk_malformed_checks_word_ct[4]), + .R(plm_link_up_i) + ); + FDRE com_tlm_u_tlm_rx_data_snk_malformed_checks_word_ct_5_ ( + .CE(com_tlm_u_tlm_rx_data_snk_malformed_checks_delay_ct_i_5241), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_malformed_checks_un4_word_ct_s_5_5180), + .Q(com_tlm_u_tlm_rx_data_snk_malformed_checks_word_ct[5]), + .R(plm_link_up_i) + ); + FDRE com_tlm_u_tlm_rx_data_snk_malformed_checks_word_ct_6_ ( + .CE(com_tlm_u_tlm_rx_data_snk_malformed_checks_delay_ct_i_5241), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_malformed_checks_un4_word_ct_s_6_5182), + .Q(com_tlm_u_tlm_rx_data_snk_malformed_checks_word_ct[6]), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_rx_data_snk_malformed_checks_malformed_min ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_malformed_checks_N_10359_i_i), + .Q(com_tlm_u_tlm_rx_data_snk_malformed_checks_malformed_min_5208), + .R(plm_link_up_i) + ); + FDRE com_tlm_u_tlm_rx_data_snk_malformed_checks_malformed_maxsize ( + .CE(com_tlm_u_tlm_rx_data_snk_latch_1st_dword_q1_5067), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_malformed_checks_N_87098_i_5228), + .Q(com_tlm_u_tlm_rx_data_snk_malformed_checks_malformed_maxsize_5217), + .R(plm_link_up_i) + ); + FDS com_tlm_u_tlm_rx_data_snk_malformed_checks_max_length_5_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_N_56233_i), + .Q(com_tlm_u_tlm_rx_data_snk_malformed_checks_max_length[5]), + .S(plm_link_up_i) + ); + FDR com_tlm_u_tlm_rx_data_snk_malformed_checks_max_length_6_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_N_56202_i), + .Q(com_tlm_u_tlm_rx_data_snk_malformed_checks_max_length[6]), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_rx_data_snk_malformed_checks_max_length_7_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_N_56034_i_i), + .Q(com_tlm_u_tlm_rx_data_snk_malformed_checks_max_length[7]), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_rx_data_snk_malformed_checks_malformed_over ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_malformed_checks_N_28370_i), + .Q(com_tlm_u_tlm_rx_data_snk_malformed_checks_malformed_over_5227), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_rx_data_snk_malformed_checks_malformed_eof ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_malformed_checks_N_28368_i), + .Q(com_tlm_u_tlm_rx_data_snk_malformed_checks_malformed_eof_5209), + .R(plm_link_up_i) + ); + FDRE com_tlm_u_tlm_rx_data_snk_malformed_checks_ur_pwr_mgmt ( + .CE(com_tlm_u_tlm_rx_data_snk_latch_1st_dword_q1_5067), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_malformed_checks_N_13914_i), + .Q(com_tlm_u_tlm_rx_data_snk_malformed_checks_ur_pwr_mgmt_5154), + .R(plm_link_up_i) + ); + FDRSE com_tlm_u_tlm_rx_data_snk_malformed_checks_type_1dw ( + .CE(com_tlm_u_tlm_rx_data_snk_latch_1st_dword_q1_5067), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_malformed_checks_GND_5170), + .Q(com_tlm_u_tlm_rx_data_snk_malformed_checks_type_1dw_5189), + .R(plm_link_up_i), + .S(com_tlm_u_tlm_rx_data_snk_malformed_checks_N_13912_i) + ); + FDRE com_tlm_u_tlm_rx_data_snk_malformed_checks_malformed_message ( + .CE(com_tlm_u_tlm_rx_data_snk_latch_1st_dword_q1_5067), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_malformed_checks_N_85575_i_5242), + .Q(com_tlm_u_tlm_rx_data_snk_malformed_checks_malformed_message_5190), + .R(plm_link_up_i) + ); + FDRE com_tlm_u_tlm_rx_data_snk_malformed_checks_malformed_fulltype ( + .CE(com_tlm_u_tlm_rx_data_snk_latch_1st_dword_q1_5067), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_malformed_checks_N_85578_i_5223), + .Q(com_tlm_u_tlm_rx_data_snk_malformed_checks_malformed_fulltype_5218), + .R(plm_link_up_i) + ); + FDRE com_tlm_u_tlm_rx_data_snk_malformed_checks_malformed_tc ( + .CE(com_tlm_u_tlm_rx_data_snk_latch_1st_dword_q1_5067), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_malformed_checks_N_53153_i), + .Q(com_tlm_u_tlm_rx_data_snk_malformed_checks_malformed_tc_5216), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_rx_data_snk_malformed_checks_malformed_rem ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_malformed_checks_malformed_rem_3_5220), + .Q(com_tlm_u_tlm_rx_data_snk_malformed_checks_malformed_rem_5207), + .R(plm_link_up_i) + ); + FDRSE com_tlm_u_tlm_rx_data_snk_malformed_checks_cfg1_ip ( + .CE(com_tlm_u_tlm_rx_data_snk_latch_1st_dword_q1_5067), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_malformed_checks_GND_5170), + .Q(com_tlm_u_tlm_rx_data_snk_malformed_checks_cfg1_ip_5213), + .R(plm_link_up_i), + .S(com_tlm_u_tlm_rx_data_snk_malformed_checks_cfg1_ip_0_sqmuxa) + ); + FDRSE com_tlm_u_tlm_rx_data_snk_malformed_checks_cfg0_ip ( + .CE(com_tlm_u_tlm_rx_data_snk_latch_1st_dword_q1_5067), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_malformed_checks_GND_5170), + .Q(com_tlm_u_tlm_rx_data_snk_malformed_checks_cfg0_ip_5214), + .R(plm_link_up_i), + .S(com_tlm_u_tlm_rx_data_snk_malformed_checks_cfg0_ip_0_sqmuxa) + ); + FDRE com_tlm_u_tlm_rx_data_snk_malformed_checks_uc_pwr_mgmt ( + .CE(com_tlm_u_tlm_rx_data_snk_latch_1st_dword_q1_5067), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_malformed_checks_uc_pwr_mgmt_7), + .Q(com_tlm_u_tlm_rx_data_snk_malformed_checks_uc_pwr_mgmt_5155), + .R(plm_link_up_i) + ); + FDRE com_tlm_u_tlm_rx_data_snk_malformed_checks_malformed_fmt ( + .CE(com_tlm_u_tlm_rx_data_snk_latch_1st_dword_q2), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_malformed_checks_N_85660_i_5215), + .Q(com_tlm_u_tlm_rx_data_snk_malformed_checks_malformed_fmt_5205), + .R(plm_link_up_i) + ); + FDRE com_tlm_u_tlm_rx_data_snk_malformed_checks_cfg_o ( + .CE(com_tlm_u_tlm_rx_data_snk_latch_3rd_dword_q1), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_malformed_checks_N_62723_i_5210), + .Q(com_tlm_u_tlm_rx_data_snk_cur_cfg), + .R(plm_link_up_i) + ); + FDRE com_tlm_u_tlm_rx_data_snk_malformed_checks_is_usr_ext_ap ( + .CE(com_tlm_u_tlm_rx_data_snk_sof_q_1__5135), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_malformed_checks_N_25301_i), + .Q(com_tlm_u_tlm_rx_data_snk_malformed_checks_is_usr_ext_ap_5212), + .R(plm_link_up_i) + ); + FDRE com_tlm_u_tlm_rx_data_snk_malformed_checks_length_1dw ( + .CE(com_tlm_u_tlm_rx_data_snk_latch_1st_dword_q1_5067), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_malformed_checks_length_1dw_3), + .Q(com_tlm_u_tlm_rx_data_snk_malformed_checks_length_1dw_5191), + .R(plm_link_up_i) + ); + FDRE com_tlm_u_tlm_rx_data_snk_malformed_checks_is_usr_leg_ap ( + .CE(com_tlm_u_tlm_rx_data_snk_sof_q_1__5135), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_malformed_checks_is_usr_leg_ap_3), + .Q(com_tlm_u_tlm_rx_data_snk_malformed_checks_is_usr_leg_ap_5211), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_rx_data_snk_malformed_checks_sof_q4 ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_malformed_checks_sof_q3_5153), + .Q(com_tlm_u_tlm_rx_data_snk_cur_data_credits_vld), + .R(plm_link_up_i) + ); + FDRE com_tlm_u_tlm_rx_data_snk_malformed_checks_malformed_len ( + .CE(com_tlm_u_tlm_rx_data_snk_eof_q_1__5112), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_malformed_checks_N_59447_i_5206), + .Q(com_tlm_u_tlm_rx_data_snk_malformed_checks_malformed_len_5204), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_rx_data_snk_malformed_checks_sof_q3 ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_latch_3rd_dword_q1), + .Q(com_tlm_u_tlm_rx_data_snk_malformed_checks_sof_q3_5153), + .R(plm_link_up_i) + ); + FDRSE com_tlm_u_tlm_rx_data_snk_malformed_checks_tlp_ur_o ( + .CE(com_tlm_u_tlm_rx_data_snk_sof_q_4_), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_malformed_checks_GND_5170), + .Q(com_tlm_u_tlm_rx_data_snk_tlp_ur), + .R(plm_link_up_i), + .S(com_tlm_u_tlm_rx_data_snk_malformed_checks_tlp_ur_o_0_sqmuxa) + ); + FDRSE com_tlm_u_tlm_rx_data_snk_malformed_checks_tlp_uc_o ( + .CE(com_tlm_u_tlm_rx_data_snk_sof_q_4_), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_malformed_checks_GND_5170), + .Q(com_tlm_u_tlm_rx_data_snk_tlp_uc), + .R(plm_link_up_i), + .S(com_tlm_u_tlm_rx_data_snk_malformed_checks_tlp_uc_o_0_sqmuxa) + ); + FDRE com_tlm_u_tlm_rx_data_snk_malformed_checks_ur_format ( + .CE(com_tlm_u_tlm_rx_data_snk_latch_1st_dword_q2), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_malformed_checks_ur_pwr_mgmt_5154), + .Q(com_tlm_u_tlm_rx_data_snk_malformed_checks_ur_format_5186), + .R(plm_link_up_i) + ); + FDRE com_tlm_u_tlm_rx_data_snk_malformed_checks_uc_format ( + .CE(com_tlm_u_tlm_rx_data_snk_latch_1st_dword_q2), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_malformed_checks_uc_pwr_mgmt_5155), + .Q(com_tlm_u_tlm_rx_data_snk_malformed_checks_uc_format_5185), + .R(plm_link_up_i) + ); + FDRE com_tlm_u_tlm_rx_data_snk_malformed_checks_malformed_o ( + .CE(com_tlm_u_tlm_rx_data_snk_malformed_checks_eof_q2_5184), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_malformed_checks_N_62722_i_5203), + .Q(com_tlm_u_tlm_rx_data_snk_malformed), + .R(plm_link_up_i) + ); + FDRE com_tlm_u_tlm_rx_data_snk_malformed_checks_hp_msg_detect_o ( + .CE(com_tlm_u_tlm_rx_data_snk_latch_1st_dword_q2), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_malformed_checks_msgcode_hotplug_5238), + .Q(com_tlm_u_tlm_rx_data_snk_cur_hp_msg_detect), + .R(plm_link_up_i) + ); + MUXCY_L com_tlm_u_tlm_rx_data_snk_malformed_checks_un6_malformed_maxsize_cry_0 ( + .CI(com_tlm_u_tlm_rx_data_snk_malformed_checks_GND_5170), + .DI(com_tlm_u_tlm_rx_data_snk_malformed_checks_VCC_5179), + .LO(com_tlm_u_tlm_rx_data_snk_malformed_checks_un6_malformed_maxsize_cry_0_5156), + .S(N_6610_i_3) + ); + MUXCY_L com_tlm_u_tlm_rx_data_snk_malformed_checks_un6_malformed_maxsize_cry_1 ( + .CI(com_tlm_u_tlm_rx_data_snk_malformed_checks_un6_malformed_maxsize_cry_0_5156), + .DI(com_tlm_u_tlm_rx_data_snk_malformed_checks_VCC_5179), + .LO(com_tlm_u_tlm_rx_data_snk_malformed_checks_un6_malformed_maxsize_cry_1_5157), + .S(N_6611_i_5) + ); + MUXCY_L com_tlm_u_tlm_rx_data_snk_malformed_checks_un6_malformed_maxsize_cry_2 ( + .CI(com_tlm_u_tlm_rx_data_snk_malformed_checks_un6_malformed_maxsize_cry_1_5157), + .DI(com_tlm_u_tlm_rx_data_snk_malformed_checks_VCC_5179), + .LO(com_tlm_u_tlm_rx_data_snk_malformed_checks_un6_malformed_maxsize_cry_2_5158), + .S(N_6612_i_7) + ); + MUXCY_L com_tlm_u_tlm_rx_data_snk_malformed_checks_un6_malformed_maxsize_cry_3 ( + .CI(com_tlm_u_tlm_rx_data_snk_malformed_checks_un6_malformed_maxsize_cry_2_5158), + .DI(com_tlm_u_tlm_rx_data_snk_malformed_checks_VCC_5179), + .LO(com_tlm_u_tlm_rx_data_snk_malformed_checks_un6_malformed_maxsize_cry_3_5159), + .S(N_6613_i_9) + ); + MUXCY_L com_tlm_u_tlm_rx_data_snk_malformed_checks_un6_malformed_maxsize_cry_4 ( + .CI(com_tlm_u_tlm_rx_data_snk_malformed_checks_un6_malformed_maxsize_cry_3_5159), + .DI(com_tlm_u_tlm_rx_data_snk_malformed_checks_VCC_5179), + .LO(com_tlm_u_tlm_rx_data_snk_malformed_checks_un6_malformed_maxsize_cry_4_5160), + .S(N_6614_i_11) + ); + MUXCY_L com_tlm_u_tlm_rx_data_snk_malformed_checks_un6_malformed_maxsize_cry_5 ( + .CI(com_tlm_u_tlm_rx_data_snk_malformed_checks_un6_malformed_maxsize_cry_4_5160), + .DI(com_tlm_u_tlm_rx_data_snk_cur_length[5]), + .LO(com_tlm_u_tlm_rx_data_snk_malformed_checks_un6_malformed_maxsize_cry_5_5161), + .S(com_tlm_u_tlm_rx_data_snk_malformed_checks_un6_malformed_maxsize_axb_5_i_5255) + ); + MUXCY_L com_tlm_u_tlm_rx_data_snk_malformed_checks_un6_malformed_maxsize_cry_6 ( + .CI(com_tlm_u_tlm_rx_data_snk_malformed_checks_un6_malformed_maxsize_cry_5_5161), + .DI(com_tlm_u_tlm_rx_data_snk_cur_length[6]), + .LO(com_tlm_u_tlm_rx_data_snk_malformed_checks_un6_malformed_maxsize_cry_6_5162), + .S(com_tlm_u_tlm_rx_data_snk_malformed_checks_un6_malformed_maxsize_axb_6_i_5254) + ); + MUXCY_L com_tlm_u_tlm_rx_data_snk_malformed_checks_un6_malformed_maxsize_cry_7 ( + .CI(com_tlm_u_tlm_rx_data_snk_malformed_checks_un6_malformed_maxsize_cry_6_5162), + .DI(com_tlm_u_tlm_rx_data_snk_cur_length[7]), + .LO(com_tlm_u_tlm_rx_data_snk_malformed_checks_un6_malformed_maxsize_cry_7_5163), + .S(com_tlm_u_tlm_rx_data_snk_malformed_checks_un6_malformed_maxsize_axb_7_i_5253) + ); + MUXCY_L com_tlm_u_tlm_rx_data_snk_malformed_checks_un6_malformed_maxsize_cry_8 ( + .CI(com_tlm_u_tlm_rx_data_snk_malformed_checks_un6_malformed_maxsize_cry_7_5163), + .DI(com_tlm_u_tlm_rx_data_snk_malformed_checks_VCC_5179), + .LO(com_tlm_u_tlm_rx_data_snk_malformed_checks_un6_malformed_maxsize_cry_8_5164), + .S(N_6618_i_13) + ); + MUXCY com_tlm_u_tlm_rx_data_snk_malformed_checks_un6_malformed_maxsize_cry_9 ( + .CI(com_tlm_u_tlm_rx_data_snk_malformed_checks_un6_malformed_maxsize_cry_8_5164), + .DI(com_tlm_u_tlm_rx_data_snk_malformed_checks_VCC_5179), + .O(com_tlm_u_tlm_rx_data_snk_malformed_checks_un6_malformed_maxsize_cry_9_5229), + .S(N_6619_i_15) + ); + MUXCY_L com_tlm_u_tlm_rx_data_snk_malformed_checks_un1_data_credits_o_cry_0 ( + .CI(com_tlm_u_tlm_rx_data_snk_malformed_checks_N_59470_i_5188), + .DI(com_tlm_u_tlm_rx_data_snk_malformed_checks_GND_5170), + .LO(com_tlm_u_tlm_rx_data_snk_malformed_checks_un1_data_credits_o_cry_0_5165), + .S(com_tlm_u_tlm_rx_data_snk_malformed_checks_un1_data_credits_o_axb_0_5252) + ); + XORCY com_tlm_u_tlm_rx_data_snk_malformed_checks_un1_data_credits_o_s_0 ( + .CI(com_tlm_u_tlm_rx_data_snk_malformed_checks_N_59470_i_5188), + .LI(com_tlm_u_tlm_rx_data_snk_malformed_checks_un1_data_credits_o_axb_0_5252), + .O(com_tlm_u_tlm_rx_data_snk_malformed_checks_un1_data_credits_o_s_0_5198) + ); + MUXCY_L com_tlm_u_tlm_rx_data_snk_malformed_checks_un1_data_credits_o_cry_1 ( + .CI(com_tlm_u_tlm_rx_data_snk_malformed_checks_un1_data_credits_o_cry_0_5165), + .DI(com_tlm_u_tlm_rx_data_snk_malformed_checks_GND_5170), + .LO(com_tlm_u_tlm_rx_data_snk_malformed_checks_un1_data_credits_o_cry_1_5166), + .S(com_tlm_u_tlm_rx_data_snk_malformed_checks_un1_data_credits_o_axb_1_5251) + ); + XORCY com_tlm_u_tlm_rx_data_snk_malformed_checks_un1_data_credits_o_s_1 ( + .CI(com_tlm_u_tlm_rx_data_snk_malformed_checks_un1_data_credits_o_cry_0_5165), + .LI(com_tlm_u_tlm_rx_data_snk_malformed_checks_un1_data_credits_o_axb_1_5251), + .O(com_tlm_u_tlm_rx_data_snk_malformed_checks_un1_data_credits_o_s_1_5197) + ); + MUXCY_L com_tlm_u_tlm_rx_data_snk_malformed_checks_un1_data_credits_o_cry_2 ( + .CI(com_tlm_u_tlm_rx_data_snk_malformed_checks_un1_data_credits_o_cry_1_5166), + .DI(com_tlm_u_tlm_rx_data_snk_malformed_checks_GND_5170), + .LO(com_tlm_u_tlm_rx_data_snk_malformed_checks_un1_data_credits_o_cry_2_5167), + .S(com_tlm_u_tlm_rx_data_snk_malformed_checks_un1_data_credits_o_axb_2_5250) + ); + XORCY com_tlm_u_tlm_rx_data_snk_malformed_checks_un1_data_credits_o_s_2 ( + .CI(com_tlm_u_tlm_rx_data_snk_malformed_checks_un1_data_credits_o_cry_1_5166), + .LI(com_tlm_u_tlm_rx_data_snk_malformed_checks_un1_data_credits_o_axb_2_5250), + .O(com_tlm_u_tlm_rx_data_snk_malformed_checks_un1_data_credits_o_s_2_5202) + ); + MUXCY_L com_tlm_u_tlm_rx_data_snk_malformed_checks_un1_data_credits_o_cry_3 ( + .CI(com_tlm_u_tlm_rx_data_snk_malformed_checks_un1_data_credits_o_cry_2_5167), + .DI(com_tlm_u_tlm_rx_data_snk_malformed_checks_GND_5170), + .LO(com_tlm_u_tlm_rx_data_snk_malformed_checks_un1_data_credits_o_cry_3_5168), + .S(com_tlm_u_tlm_rx_data_snk_malformed_checks_un1_data_credits_o_axb_3_5249) + ); + XORCY com_tlm_u_tlm_rx_data_snk_malformed_checks_un1_data_credits_o_s_3 ( + .CI(com_tlm_u_tlm_rx_data_snk_malformed_checks_un1_data_credits_o_cry_2_5167), + .LI(com_tlm_u_tlm_rx_data_snk_malformed_checks_un1_data_credits_o_axb_3_5249), + .O(com_tlm_u_tlm_rx_data_snk_malformed_checks_un1_data_credits_o_s_3_5201) + ); + MUXCY_L com_tlm_u_tlm_rx_data_snk_malformed_checks_un1_data_credits_o_cry_4 ( + .CI(com_tlm_u_tlm_rx_data_snk_malformed_checks_un1_data_credits_o_cry_3_5168), + .DI(com_tlm_u_tlm_rx_data_snk_malformed_checks_GND_5170), + .LO(com_tlm_u_tlm_rx_data_snk_malformed_checks_un1_data_credits_o_cry_4_5169), + .S(com_tlm_u_tlm_rx_data_snk_malformed_checks_un1_data_credits_o_axb_4_5248) + ); + XORCY com_tlm_u_tlm_rx_data_snk_malformed_checks_un1_data_credits_o_s_4 ( + .CI(com_tlm_u_tlm_rx_data_snk_malformed_checks_un1_data_credits_o_cry_3_5168), + .LI(com_tlm_u_tlm_rx_data_snk_malformed_checks_un1_data_credits_o_axb_4_5248), + .O(com_tlm_u_tlm_rx_data_snk_malformed_checks_un1_data_credits_o_s_4_5200) + ); + XORCY com_tlm_u_tlm_rx_data_snk_malformed_checks_un1_data_credits_o_s_5 ( + .CI(com_tlm_u_tlm_rx_data_snk_malformed_checks_un1_data_credits_o_cry_4_5169), + .LI(com_tlm_u_tlm_rx_data_snk_malformed_checks_un1_data_credits_o_axb_5_5187), + .O(com_tlm_u_tlm_rx_data_snk_malformed_checks_un1_data_credits_o_s_5_5199) + ); + MUXCY_L com_tlm_u_tlm_rx_data_snk_malformed_checks_un4_word_ct_cry_0 ( + .CI(com_tlm_u_tlm_rx_data_snk_malformed_checks_GND_5170), + .DI(com_tlm_u_tlm_rx_data_snk_malformed_checks_VCC_5179), + .LO(com_tlm_u_tlm_rx_data_snk_malformed_checks_un4_word_ct_cry_0_5172), + .S(com_tlm_u_tlm_rx_data_snk_malformed_checks_word_ct_d_i[0]) + ); + MUXCY_L com_tlm_u_tlm_rx_data_snk_malformed_checks_un4_word_ct_cry_1 ( + .CI(com_tlm_u_tlm_rx_data_snk_malformed_checks_un4_word_ct_cry_0_5172), + .DI(com_tlm_u_tlm_rx_data_snk_malformed_checks_VCC_5179), + .LO(com_tlm_u_tlm_rx_data_snk_malformed_checks_un4_word_ct_cry_1_5174), + .S(com_tlm_u_tlm_rx_data_snk_malformed_checks_word_ct_d_i[1]) + ); + XORCY com_tlm_u_tlm_rx_data_snk_malformed_checks_un4_word_ct_s_1 ( + .CI(com_tlm_u_tlm_rx_data_snk_malformed_checks_un4_word_ct_cry_0_5172), + .LI(com_tlm_u_tlm_rx_data_snk_malformed_checks_word_ct_d_i[1]), + .O(com_tlm_u_tlm_rx_data_snk_malformed_checks_un4_word_ct_s_1_5171) + ); + MUXCY_L com_tlm_u_tlm_rx_data_snk_malformed_checks_un4_word_ct_cry_2 ( + .CI(com_tlm_u_tlm_rx_data_snk_malformed_checks_un4_word_ct_cry_1_5174), + .DI(com_tlm_u_tlm_rx_data_snk_malformed_checks_VCC_5179), + .LO(com_tlm_u_tlm_rx_data_snk_malformed_checks_un4_word_ct_cry_2_5176), + .S(com_tlm_u_tlm_rx_data_snk_malformed_checks_word_ct_d_i[2]) + ); + XORCY com_tlm_u_tlm_rx_data_snk_malformed_checks_un4_word_ct_s_2 ( + .CI(com_tlm_u_tlm_rx_data_snk_malformed_checks_un4_word_ct_cry_1_5174), + .LI(com_tlm_u_tlm_rx_data_snk_malformed_checks_word_ct_d_i[2]), + .O(com_tlm_u_tlm_rx_data_snk_malformed_checks_un4_word_ct_s_2_5173) + ); + MUXCY_L com_tlm_u_tlm_rx_data_snk_malformed_checks_un4_word_ct_cry_3 ( + .CI(com_tlm_u_tlm_rx_data_snk_malformed_checks_un4_word_ct_cry_2_5176), + .DI(com_tlm_u_tlm_rx_data_snk_malformed_checks_VCC_5179), + .LO(com_tlm_u_tlm_rx_data_snk_malformed_checks_un4_word_ct_cry_3_5178), + .S(com_tlm_u_tlm_rx_data_snk_malformed_checks_word_ct_d_i[3]) + ); + XORCY com_tlm_u_tlm_rx_data_snk_malformed_checks_un4_word_ct_s_3 ( + .CI(com_tlm_u_tlm_rx_data_snk_malformed_checks_un4_word_ct_cry_2_5176), + .LI(com_tlm_u_tlm_rx_data_snk_malformed_checks_word_ct_d_i[3]), + .O(com_tlm_u_tlm_rx_data_snk_malformed_checks_un4_word_ct_s_3_5175) + ); + MUXCY_L com_tlm_u_tlm_rx_data_snk_malformed_checks_un4_word_ct_cry_4 ( + .CI(com_tlm_u_tlm_rx_data_snk_malformed_checks_un4_word_ct_cry_3_5178), + .DI(com_tlm_u_tlm_rx_data_snk_malformed_checks_VCC_5179), + .LO(com_tlm_u_tlm_rx_data_snk_malformed_checks_un4_word_ct_cry_4_5181), + .S(com_tlm_u_tlm_rx_data_snk_malformed_checks_word_ct_d_i[4]) + ); + XORCY com_tlm_u_tlm_rx_data_snk_malformed_checks_un4_word_ct_s_4 ( + .CI(com_tlm_u_tlm_rx_data_snk_malformed_checks_un4_word_ct_cry_3_5178), + .LI(com_tlm_u_tlm_rx_data_snk_malformed_checks_word_ct_d_i[4]), + .O(com_tlm_u_tlm_rx_data_snk_malformed_checks_un4_word_ct_s_4_5177) + ); + MUXCY_L com_tlm_u_tlm_rx_data_snk_malformed_checks_un4_word_ct_cry_5 ( + .CI(com_tlm_u_tlm_rx_data_snk_malformed_checks_un4_word_ct_cry_4_5181), + .DI(com_tlm_u_tlm_rx_data_snk_malformed_checks_VCC_5179), + .LO(com_tlm_u_tlm_rx_data_snk_malformed_checks_un4_word_ct_cry_5_5183), + .S(com_tlm_u_tlm_rx_data_snk_malformed_checks_word_ct_d_i[5]) + ); + XORCY com_tlm_u_tlm_rx_data_snk_malformed_checks_un4_word_ct_s_5 ( + .CI(com_tlm_u_tlm_rx_data_snk_malformed_checks_un4_word_ct_cry_4_5181), + .LI(com_tlm_u_tlm_rx_data_snk_malformed_checks_word_ct_d_i[5]), + .O(com_tlm_u_tlm_rx_data_snk_malformed_checks_un4_word_ct_s_5_5180) + ); + XORCY com_tlm_u_tlm_rx_data_snk_malformed_checks_un4_word_ct_s_6 ( + .CI(com_tlm_u_tlm_rx_data_snk_malformed_checks_un4_word_ct_cry_5_5183), + .LI(com_tlm_u_tlm_rx_data_snk_malformed_checks_word_ct_d_i[6]), + .O(com_tlm_u_tlm_rx_data_snk_malformed_checks_un4_word_ct_s_6_5182) + ); + FDR com_tlm_u_tlm_rx_data_snk_malformed_checks_delay_ct ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_malformed_checks_delay_ctc_i), + .Q(com_tlm_u_tlm_rx_data_snk_malformed_checks_delay_ct_5247), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_rx_data_snk_malformed_checks_load_aperture_q ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_sof_q_1__5135), + .Q(com_tlm_u_tlm_rx_data_snk_latch_3rd_dword_q1), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_rx_data_snk_malformed_checks_eof_q2 ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_eof_q_1__5112), + .Q(com_tlm_u_tlm_rx_data_snk_malformed_checks_eof_q2_5184), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_rx_data_snk_malformed_checks_eval_formats_q ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_latch_1st_dword_q1_5067), + .Q(com_tlm_u_tlm_rx_data_snk_latch_1st_dword_q2), + .R(plm_link_up_i) + ); + defparam com_tlm_u_tlm_rx_data_snk_malformed_checks_tlp_uc_o_0_sqmuxa_0_a2.INIT = 4'h8; + LUT2 com_tlm_u_tlm_rx_data_snk_malformed_checks_tlp_uc_o_0_sqmuxa_0_a2 ( + .I0(com_tlm_u_tlm_rx_data_snk_malformed_checks_uc_format_5185), + .I1(com_tlm_u_tlm_rx_data_snk_sof_q_4_), + .O(com_tlm_u_tlm_rx_data_snk_malformed_checks_tlp_uc_o_0_sqmuxa) + ); + defparam com_tlm_u_tlm_rx_data_snk_malformed_checks_tlp_ur_o_0_sqmuxa_0_a2.INIT = 4'h8; + LUT2 com_tlm_u_tlm_rx_data_snk_malformed_checks_tlp_ur_o_0_sqmuxa_0_a2 ( + .I0(com_tlm_u_tlm_rx_data_snk_malformed_checks_ur_format_5186), + .I1(com_tlm_u_tlm_rx_data_snk_sof_q_4_), + .O(com_tlm_u_tlm_rx_data_snk_malformed_checks_tlp_ur_o_0_sqmuxa) + ); + defparam com_tlm_u_tlm_rx_data_snk_malformed_checks_type_1dw_0_sqmuxa_i_0_0_0_o2.INIT = 4'h1; + LUT2 com_tlm_u_tlm_rx_data_snk_malformed_checks_type_1dw_0_sqmuxa_i_0_0_0_o2 ( + .I0(com_tlm_u_tlm_rx_data_snk_malformed_checks_cur_fulltype[3]), + .I1(com_tlm_u_tlm_rx_data_snk_malformed_checks_cur_fulltype[4]), + .O(com_tlm_u_tlm_rx_data_snk_N_56246_i) + ); + defparam com_tlm_u_tlm_rx_data_snk_malformed_checks_malformed_fulltype16_0_0_0_0_o3_0.INIT = 4'h2; + LUT2 com_tlm_u_tlm_rx_data_snk_malformed_checks_malformed_fulltype16_0_0_0_0_o3_0 ( + .I0(com_tlm_u_tlm_rx_data_snk_malformed_checks_cur_fulltype[1]), + .I1(com_tlm_u_tlm_rx_data_snk_malformed_checks_cur_fulltype[4]), + .O(com_tlm_u_tlm_rx_data_snk_malformed_checks_N_56501_i) + ); + defparam com_tlm_u_tlm_rx_data_snk_malformed_checks_malformed_message_6_0_0_0_0_x3.INIT = 4'h6; + LUT2_L com_tlm_u_tlm_rx_data_snk_malformed_checks_malformed_message_6_0_0_0_0_x3 ( + .I0(com_tlm_u_tlm_rx_data_snk_malformed_checks_cur_fulltype[1]), + .I1(com_tlm_u_tlm_rx_data_snk_malformed_checks_msgcode_routing[1]), + .LO(com_tlm_u_tlm_rx_data_snk_malformed_checks_N_56362_i_0) + ); + defparam com_tlm_u_tlm_rx_data_snk_malformed_checks_un1_reset_i_1_i_0_0_0_o3.INIT = 4'h8; + LUT2 com_tlm_u_tlm_rx_data_snk_malformed_checks_un1_reset_i_1_i_0_0_0_o3 ( + .I0(com_tlm_u_tlm_rx_data_snk_cur_fulltype[6]), + .I1(com_tlm_u_tlm_rx_data_snk_cur_length_0__2), + .O(com_tlm_u_tlm_rx_data_snk_malformed_checks_N_56346_i) + ); + defparam com_tlm_u_tlm_rx_data_snk_malformed_checks_malformed_fulltype16_0_0_0_0_o3.INIT = 4'h1; + LUT2 com_tlm_u_tlm_rx_data_snk_malformed_checks_malformed_fulltype16_0_0_0_0_o3 ( + .I0(com_tlm_u_tlm_rx_data_snk_malformed_checks_cur_fulltype[1]), + .I1(com_tlm_u_tlm_rx_data_snk_malformed_checks_cur_fulltype[2]), + .O(com_tlm_u_tlm_rx_data_snk_N_56003_i) + ); + defparam com_tlm_u_tlm_rx_data_snk_malformed_checks_msgcode_sigdef16_0_0_0_a2_2.INIT = 4'h8; + LUT2 com_tlm_u_tlm_rx_data_snk_malformed_checks_msgcode_sigdef16_0_0_0_a2_2 ( + .I0(com_lnk_rd[2]), + .I1(com_lnk_rd[4]), + .O(com_tlm_u_tlm_rx_data_snk_malformed_checks_N_58343) + ); + defparam com_tlm_u_tlm_rx_data_snk_malformed_checks_check_int_msgcode_routing18_0_0_0_o2.INIT = 4'h1; + LUT2 com_tlm_u_tlm_rx_data_snk_malformed_checks_check_int_msgcode_routing18_0_0_0_o2 ( + .I0(com_lnk_rd[1]), + .I1(com_lnk_rd[2]), + .O(N_56031_i) + ); + defparam com_tlm_u_tlm_rx_data_snk_malformed_checks_msgcode_sigdef16_0_0_0_o3.INIT = 4'h2; + LUT2 com_tlm_u_tlm_rx_data_snk_malformed_checks_msgcode_sigdef16_0_0_0_o3 ( + .I0(com_lnk_rd[4]), + .I1(com_lnk_rd[5]), + .O(com_tlm_u_tlm_rx_data_snk_N_56132_i) + ); + defparam com_tlm_u_tlm_rx_data_snk_malformed_checks_check_int_un1_msgcode_routing19_0_0_0_o3.INIT = 4'h1; + LUT2 com_tlm_u_tlm_rx_data_snk_malformed_checks_check_int_un1_msgcode_routing19_0_0_0_o3 ( + .I0(com_lnk_rd[0]), + .I1(com_lnk_rd[3]), + .O(com_tlm_u_tlm_rx_data_snk_malformed_checks_N_56133_i) + ); + defparam com_tlm_u_tlm_rx_data_snk_malformed_checks_msgcode_hotplug12_0_0_0_o2.INIT = 4'h2; + LUT2 com_tlm_u_tlm_rx_data_snk_malformed_checks_msgcode_hotplug12_0_0_0_o2 ( + .I0(com_lnk_rd[6]), + .I1(com_lnk_rd[7]), + .O(com_tlm_u_tlm_rx_data_snk_malformed_checks_N_56244_i) + ); + defparam com_tlm_u_tlm_rx_data_snk_malformed_checks_msgcode_sigdef16_0_0_0_o3_0.INIT = 4'h8; + LUT2 com_tlm_u_tlm_rx_data_snk_malformed_checks_msgcode_sigdef16_0_0_0_o3_0 ( + .I0(com_lnk_rd[1]), + .I1(com_lnk_rd[3]), + .O(com_tlm_u_tlm_rx_data_snk_malformed_checks_N_56353_i) + ); + defparam com_tlm_u_tlm_rx_data_snk_malformed_checks_check_int_un1_msgcode_routing19_0_0_0_o2.INIT = 4'h1; + LUT2 com_tlm_u_tlm_rx_data_snk_malformed_checks_check_int_un1_msgcode_routing19_0_0_0_o2 ( + .I0(com_lnk_rd[6]), + .I1(com_lnk_rd[7]), + .O(com_tlm_u_tlm_rx_data_snk_N_56488_i) + ); + defparam com_tlm_u_tlm_rx_data_snk_malformed_checks_is_usr_ext_ap_3_i_0_0_0_a2.INIT = 4'h1; + LUT2 com_tlm_u_tlm_rx_data_snk_malformed_checks_is_usr_ext_ap_3_i_0_0_0_a2 ( + .I0(com_lnk_rd_6113[42]), + .I1(com_lnk_rd_6113[43]), + .O(com_tlm_u_tlm_rx_data_snk_malformed_checks_N_59001) + ); + defparam com_tlm_u_tlm_rx_data_snk_malformed_checks_un1_data_credits_o_axb_5.INIT = 4'h2; + LUT1 com_tlm_u_tlm_rx_data_snk_malformed_checks_un1_data_credits_o_axb_5 ( + .I0(com_tlm_u_tlm_rx_data_snk_cur_length[7]), + .O(com_tlm_u_tlm_rx_data_snk_malformed_checks_un1_data_credits_o_axb_5_5187) + ); + defparam com_tlm_u_tlm_rx_data_snk_malformed_checks_uc_pwr_mgmt_7_0_a2_0_a2_0_a2_0_a2_1.INIT = 4'h4; + LUT2 com_tlm_u_tlm_rx_data_snk_malformed_checks_uc_pwr_mgmt_7_0_a2_0_a2_0_a2_0_a2_1 ( + .I0(com_tlm_u_tlm_rx_data_snk_malformed_checks_cur_fulltype[2]), + .I1(com_tlm_u_tlm_rx_data_snk_pwr_mgmt_mode_on_5055), + .O(com_tlm_u_tlm_rx_data_snk_malformed_checks_uc_pwr_mgmt_7_1) + ); + defparam com_tlm_u_tlm_rx_data_snk_malformed_checks_ismsgany17_0_o3_i_o3_i_o3_0_.INIT = 8'h40; + LUT3 com_tlm_u_tlm_rx_data_snk_malformed_checks_ismsgany17_0_o3_i_o3_i_o3_0_ ( + .I0(com_lnk_rd_6113[59]), + .I1(com_lnk_rd_6113[60]), + .I2(com_lnk_rd_6113[61]), + .O(com_tlm_u_tlm_rx_data_snk_malformed_checks_N_56050_i) + ); + defparam com_tlm_u_tlm_rx_data_snk_malformed_checks_msgcode_sigdef16_0_0_0_a2_1.INIT = 4'h8; + LUT2_L com_tlm_u_tlm_rx_data_snk_malformed_checks_msgcode_sigdef16_0_0_0_a2_1 ( + .I0(N_57268), + .I1(com_lnk_rd[4]), + .LO(com_tlm_u_tlm_rx_data_snk_malformed_checks_N_58342) + ); + defparam com_tlm_u_tlm_rx_data_snk_malformed_checks_N_59470_i.INIT = 4'hE; + LUT2 com_tlm_u_tlm_rx_data_snk_malformed_checks_N_59470_i ( + .I0(com_tlm_u_tlm_rx_data_snk_cur_length_0__2), + .I1(com_tlm_u_tlm_rx_data_snk_cur_length_1__4), + .O(com_tlm_u_tlm_rx_data_snk_malformed_checks_N_59470_i_5188) + ); + defparam com_tlm_u_tlm_rx_data_snk_malformed_checks_N_10359_i_0_0_0_0_o2.INIT = 8'h10; + LUT3 com_tlm_u_tlm_rx_data_snk_malformed_checks_N_10359_i_0_0_0_0_o2 ( + .I0(com_lnk_reof_n), + .I1(com_lnk_rsrc_rdy_n), + .I2(com_tlm_u_tlm_rx_data_snk_packet_ip_5087), + .O(com_tlm_u_tlm_rx_data_snk_N_56509_i) + ); + defparam com_tlm_u_tlm_rx_data_snk_malformed_checks_cfg1_ip_0_sqmuxa_0_a2_0_a2_0_a2_0_a2_1_0.INIT = 16'h4000; + LUT4 com_tlm_u_tlm_rx_data_snk_malformed_checks_cfg1_ip_0_sqmuxa_0_a2_0_a2_0_a2_0_a2_1_0 ( + .I0(com_tlm_u_tlm_rx_data_snk_malformed_checks_cur_fulltype[1]), + .I1(com_tlm_u_tlm_rx_data_snk_malformed_checks_cur_fulltype[2]), + .I2(com_tlm_u_tlm_rx_data_snk_latch_1st_dword_q1_5067), + .I3(plm_link_up_1), + .O(com_tlm_u_tlm_rx_data_snk_malformed_checks_cfg1_ip_0_sqmuxa_1_0) + ); + defparam com_tlm_u_tlm_rx_data_snk_malformed_checks_malformed_eof_3_i_0_0_a2_0_4.INIT = 16'h0001; + LUT4_L com_tlm_u_tlm_rx_data_snk_malformed_checks_malformed_eof_3_i_0_0_a2_0_4 ( + .I0(com_tlm_u_tlm_rx_data_snk_malformed_checks_word_ct[1]), + .I1(com_tlm_u_tlm_rx_data_snk_malformed_checks_word_ct[2]), + .I2(com_tlm_u_tlm_rx_data_snk_malformed_checks_word_ct[3]), + .I3(com_tlm_u_tlm_rx_data_snk_malformed_checks_word_ct[5]), + .LO(com_tlm_u_tlm_rx_data_snk_malformed_checks_malformed_eof_3_i_0_0_a2_0_4_5231) + ); + defparam com_tlm_u_tlm_rx_data_snk_malformed_checks_malformed_over_3_i_0_0_o3_4.INIT = 16'h8000; + LUT4_L com_tlm_u_tlm_rx_data_snk_malformed_checks_malformed_over_3_i_0_0_o3_4 ( + .I0(com_tlm_u_tlm_rx_data_snk_malformed_checks_word_ct[0]), + .I1(com_tlm_u_tlm_rx_data_snk_malformed_checks_word_ct[1]), + .I2(com_tlm_u_tlm_rx_data_snk_malformed_checks_word_ct[2]), + .I3(com_tlm_u_tlm_rx_data_snk_malformed_checks_word_ct[6]), + .LO(com_tlm_u_tlm_rx_data_snk_malformed_checks_malformed_over_3_i_0_0_o3_4_5192) + ); + defparam com_tlm_u_tlm_rx_data_snk_malformed_checks_malformed_maxsize_3_0_0_0_0_a2_0_1_4.INIT = 8'h01; + LUT3 com_tlm_u_tlm_rx_data_snk_malformed_checks_malformed_maxsize_3_0_0_0_0_a2_0_1_4 ( + .I0(com_tlm_u_tlm_rx_data_snk_cur_length_4__10), + .I1(com_tlm_u_tlm_rx_data_snk_cur_length_8__12), + .I2(com_tlm_u_tlm_rx_data_snk_cur_length_9__14), + .O(com_tlm_u_tlm_rx_data_snk_malformed_checks_malformed_maxsize_3_0_0_0_0_a2_0_1_4_5194) + ); + defparam com_tlm_u_tlm_rx_data_snk_malformed_checks_malformed_maxsize_3_0_0_0_0_a2_0_1_5.INIT = 16'h0001; + LUT4_L com_tlm_u_tlm_rx_data_snk_malformed_checks_malformed_maxsize_3_0_0_0_0_a2_0_1_5 ( + .I0(com_tlm_u_tlm_rx_data_snk_cur_length_1__4), + .I1(com_tlm_u_tlm_rx_data_snk_cur_length_3__8), + .I2(com_tlm_u_tlm_rx_data_snk_cur_length[5]), + .I3(com_tlm_u_tlm_rx_data_snk_cur_length[6]), + .LO(com_tlm_u_tlm_rx_data_snk_malformed_checks_malformed_maxsize_3_0_0_0_0_a2_0_1_5_5193) + ); + defparam com_tlm_u_tlm_rx_data_snk_malformed_checks_malformed_fmt_3_i_0_0_2.INIT = 16'h4C5F; + LUT4_L com_tlm_u_tlm_rx_data_snk_malformed_checks_malformed_fmt_3_i_0_0_2 ( + .I0(com_tlm_u_tlm_rx_data_snk_cur_fulltype_oh_1_), + .I1(com_tlm_u_tlm_rx_data_snk_malformed_checks_length_1dw_5191), + .I2(com_tlm_u_tlm_rx_data_snk_malformed_checks_malformed_message_5190), + .I3(com_tlm_u_tlm_rx_data_snk_malformed_checks_type_1dw_5189), + .LO(com_tlm_u_tlm_rx_data_snk_malformed_checks_malformed_fmt_3_i_0_0_2_5219) + ); + defparam com_tlm_u_tlm_rx_data_snk_malformed_checks_is_usr_leg_ap_3_0_a2_0_a2_0_a2_0_a2_1_0.INIT = 8'h80; + LUT3_L com_tlm_u_tlm_rx_data_snk_malformed_checks_is_usr_leg_ap_3_0_a2_0_a2_0_a2_0_a2_1_0 ( + .I0(cfg_cfg_6102[502]), + .I1(com_lnk_rd_6113[38]), + .I2(com_lnk_rd_6113[39]), + .LO(com_tlm_u_tlm_rx_data_snk_malformed_checks_is_usr_leg_ap_3_0_a2_0_a2_0_a2_0_a2_1) + ); + defparam com_tlm_u_tlm_rx_data_snk_malformed_checks_msgcode_hotplug12_0_0_0_0.INIT = 16'h0007; + LUT4 com_tlm_u_tlm_rx_data_snk_malformed_checks_msgcode_hotplug12_0_0_0_0 ( + .I0(com_lnk_rd[2]), + .I1(com_lnk_rd[3]), + .I2(com_lnk_rd[4]), + .I3(com_lnk_rd[5]), + .O(com_tlm_u_tlm_rx_data_snk_malformed_checks_msgcode_hotplug12_0_0_0_0_5222) + ); + defparam com_tlm_u_tlm_rx_data_snk_malformed_checks_check_int_un1_msgcode_routing19_0_0_0_m2_0.INIT = 8'h7E; + LUT3 com_tlm_u_tlm_rx_data_snk_malformed_checks_check_int_un1_msgcode_routing19_0_0_0_m2_0 ( + .I0(com_lnk_rd[0]), + .I1(com_lnk_rd[3]), + .I2(com_lnk_rd[4]), + .O(com_tlm_u_tlm_rx_data_snk_malformed_checks_N_56185) + ); + defparam com_tlm_u_tlm_rx_data_snk_malformed_checks_word_ct_d_1_0_0_0_.INIT = 16'h707F; + LUT4 com_tlm_u_tlm_rx_data_snk_malformed_checks_word_ct_d_1_0_0_0_ ( + .I0(com_tlm_u_tlm_rx_data_snk_cur_fulltype[6]), + .I1(com_tlm_u_tlm_rx_data_snk_cur_length_1__4), + .I2(com_tlm_u_tlm_rx_data_snk_latch_1st_dword_q1_5067), + .I3(com_tlm_u_tlm_rx_data_snk_malformed_checks_word_ct[0]), + .O(com_tlm_u_tlm_rx_data_snk_malformed_checks_word_ct_d_i[0]) + ); + defparam com_tlm_u_tlm_rx_data_snk_malformed_checks_msgd_check_64_msgcode_dmatch_4_0_x3_0_x3_0_o3_0.INIT = 16'h8000; + LUT4_L com_tlm_u_tlm_rx_data_snk_malformed_checks_msgd_check_64_msgcode_dmatch_4_0_x3_0_x3_0_o3_0 ( + .I0(N_56031_i), + .I1(com_tlm_u_tlm_rx_data_snk_N_56132_i), + .I2(com_tlm_u_tlm_rx_data_snk_malformed_checks_N_56133_i), + .I3(com_tlm_u_tlm_rx_data_snk_malformed_checks_N_56244_i), + .LO(com_tlm_u_tlm_rx_data_snk_malformed_checks_msgcode_dmatch_4_0_x3_0_x3_0_o3_0) + ); + defparam com_tlm_u_tlm_rx_data_snk_malformed_checks_malformed_over_3_i_0_0_o3.INIT = 16'h8000; + LUT4 com_tlm_u_tlm_rx_data_snk_malformed_checks_malformed_over_3_i_0_0_o3 ( + .I0(com_tlm_u_tlm_rx_data_snk_malformed_checks_malformed_over_3_i_0_0_o3_4_5192), + .I1(com_tlm_u_tlm_rx_data_snk_malformed_checks_word_ct[3]), + .I2(com_tlm_u_tlm_rx_data_snk_malformed_checks_word_ct[4]), + .I3(com_tlm_u_tlm_rx_data_snk_malformed_checks_word_ct[5]), + .O(com_tlm_u_tlm_rx_data_snk_malformed_checks_N_57047_i) + ); + defparam com_tlm_u_tlm_rx_data_snk_malformed_checks_cfg0_ip_0_sqmuxa_0_a2_0_a2_0_a2_0_a2.INIT = 16'h0008; + LUT4 com_tlm_u_tlm_rx_data_snk_malformed_checks_cfg0_ip_0_sqmuxa_0_a2_0_a2_0_a2_0_a2 ( + .I0(com_tlm_u_tlm_rx_data_snk_N_56246_i), + .I1(com_tlm_u_tlm_rx_data_snk_malformed_checks_cfg1_ip_0_sqmuxa_1_0), + .I2(com_tlm_u_tlm_rx_data_snk_malformed_checks_fulltype_in_0__5233), + .I3(com_tlm_u_tlm_rx_data_snk_malformed_checks_fulltype_in_5__5232), + .O(com_tlm_u_tlm_rx_data_snk_malformed_checks_cfg0_ip_0_sqmuxa) + ); + defparam com_tlm_u_tlm_rx_data_snk_malformed_checks_malformed_fulltype16_0_0_0_0_a2_4.INIT = 16'h2000; + LUT4 com_tlm_u_tlm_rx_data_snk_malformed_checks_malformed_fulltype16_0_0_0_0_a2_4 ( + .I0(com_tlm_u_tlm_rx_data_snk_N_56246_i), + .I1(com_tlm_u_tlm_rx_data_snk_malformed_checks_cur_fulltype[2]), + .I2(com_tlm_u_tlm_rx_data_snk_cur_fulltype[6]), + .I3(com_tlm_u_tlm_rx_data_snk_malformed_checks_fulltype_in_0__5233), + .O(com_tlm_u_tlm_rx_data_snk_malformed_checks_N_58350) + ); + defparam com_tlm_u_tlm_rx_data_snk_malformed_checks_fulltype_tc012_i_0_0_a2_0.INIT = 16'h0008; + LUT4 com_tlm_u_tlm_rx_data_snk_malformed_checks_fulltype_tc012_i_0_0_a2_0 ( + .I0(com_tlm_u_tlm_rx_data_snk_N_56498_i), + .I1(com_lnk_rd_6113[58]), + .I2(com_lnk_rd_6113[60]), + .I3(com_lnk_rd_6113[61]), + .O(com_tlm_u_tlm_rx_data_snk_malformed_checks_N_58513) + ); + defparam com_tlm_u_tlm_rx_data_snk_malformed_checks_malformed_message_6_0_0_0_0_a2_0.INIT = 16'h00D0; + LUT4_L com_tlm_u_tlm_rx_data_snk_malformed_checks_malformed_message_6_0_0_0_0_a2_0 ( + .I0(com_tlm_u_tlm_rx_data_snk_N_56003_i), + .I1(com_tlm_u_tlm_rx_data_snk_malformed_checks_fulltype_in_0__5233), + .I2(com_tlm_u_tlm_rx_data_snk_malformed_checks_msgcode_vendef_5243), + .I3(com_tlm_u_tlm_rx_data_snk_malformed_checks_routing_vendef_5235), + .LO(com_tlm_u_tlm_rx_data_snk_malformed_checks_N_57271) + ); + defparam com_tlm_u_tlm_rx_data_snk_malformed_checks_N_10359_i_0_0_0_0_39304.INIT = 8'hD4; + LUT3 com_tlm_u_tlm_rx_data_snk_malformed_checks_N_10359_i_0_0_0_0_39304 ( + .I0(com_lnk_rrem[0]), + .I1(com_tlm_u_tlm_rx_data_snk_cur_td_5119), + .I2(com_tlm_u_tlm_rx_data_snk_malformed_checks_fulltype_in_5__5232), + .O(com_tlm_u_tlm_rx_data_snk_malformed_checks_N_10359_i_0_0_0_0_39304_5230) + ); + defparam com_tlm_u_tlm_rx_data_snk_malformed_checks_msgcode_sigdef16_0_0_0_39393.INIT = 16'h33A2; + LUT4 com_tlm_u_tlm_rx_data_snk_malformed_checks_msgcode_sigdef16_0_0_0_39393 ( + .I0(com_tlm_u_tlm_rx_data_snk_malformed_checks_N_56353_i), + .I1(com_lnk_rd[3]), + .I2(com_lnk_rd[4]), + .I3(com_lnk_rd[5]), + .O(com_tlm_u_tlm_rx_data_snk_malformed_checks_msgcode_sigdef16_0_0_0_39393_5225) + ); + defparam com_tlm_u_tlm_rx_data_snk_malformed_checks_ur_pwr_mgmt_7_i_0_0_0_1.INIT = 16'h2A00; + LUT4_L com_tlm_u_tlm_rx_data_snk_malformed_checks_ur_pwr_mgmt_7_i_0_0_0_1 ( + .I0(com_tlm_u_tlm_rx_data_snk_N_56246_i), + .I1(com_tlm_u_tlm_rx_data_snk_cur_fulltype[6]), + .I2(com_tlm_u_tlm_rx_data_snk_malformed_checks_fulltype_in_0__5233), + .I3(com_tlm_u_tlm_rx_data_snk_malformed_checks_uc_pwr_mgmt_7_1), + .LO(com_tlm_u_tlm_rx_data_snk_malformed_checks_ur_pwr_mgmt_7_i_0_0_0_1_5226) + ); + defparam com_tlm_u_tlm_rx_data_snk_malformed_checks_type_1dw_0_sqmuxa_i_0_0_0_1.INIT = 16'h0800; + LUT4_L com_tlm_u_tlm_rx_data_snk_malformed_checks_type_1dw_0_sqmuxa_i_0_0_0_1 ( + .I0(com_tlm_u_tlm_rx_data_snk_N_56246_i), + .I1(com_tlm_u_tlm_rx_data_snk_latch_1st_dword_q1_5067), + .I2(com_tlm_u_tlm_rx_data_snk_malformed_checks_fulltype_in_5__5232), + .I3(plm_link_up_1), + .LO(com_tlm_u_tlm_rx_data_snk_malformed_checks_type_1dw_0_sqmuxa_i_0_0_0_1_5195) + ); + defparam com_tlm_u_tlm_rx_data_snk_malformed_checks_malformed_message_6_0_0_0_0_1.INIT = 16'hFF41; + LUT4 com_tlm_u_tlm_rx_data_snk_malformed_checks_malformed_message_6_0_0_0_0_1 ( + .I0(com_tlm_u_tlm_rx_data_snk_malformed_checks_N_56362_i_0), + .I1(com_tlm_u_tlm_rx_data_snk_malformed_checks_cur_fulltype[2]), + .I2(com_tlm_u_tlm_rx_data_snk_malformed_checks_msgcode_routing[2]), + .I3(com_tlm_u_tlm_rx_data_snk_malformed_checks_msgcode_vendef_5243), + .O(com_tlm_u_tlm_rx_data_snk_malformed_checks_malformed_message_6_0_0_0_0_1_5244) + ); + defparam com_tlm_u_tlm_rx_data_snk_malformed_checks_check_int_un1_msgcode_routing19_0_0_0_1.INIT = 8'h04; + LUT3 com_tlm_u_tlm_rx_data_snk_malformed_checks_check_int_un1_msgcode_routing19_0_0_0_1 ( + .I0(com_tlm_u_tlm_rx_data_snk_malformed_checks_N_56185), + .I1(com_tlm_u_tlm_rx_data_snk_N_56488_i), + .I2(com_lnk_rd[5]), + .O(com_tlm_u_tlm_rx_data_snk_malformed_checks_N_10637_i_1) + ); + defparam com_tlm_u_tlm_rx_data_snk_malformed_checks_cfg1_ip_0_sqmuxa_0_a2_0_a2_0_a2_0_a2.INIT = 16'h0080; + LUT4 com_tlm_u_tlm_rx_data_snk_malformed_checks_cfg1_ip_0_sqmuxa_0_a2_0_a2_0_a2_0_a2 ( + .I0(com_tlm_u_tlm_rx_data_snk_N_56246_i), + .I1(com_tlm_u_tlm_rx_data_snk_malformed_checks_cfg1_ip_0_sqmuxa_1_0), + .I2(com_tlm_u_tlm_rx_data_snk_malformed_checks_fulltype_in_0__5233), + .I3(com_tlm_u_tlm_rx_data_snk_malformed_checks_fulltype_in_5__5232), + .O(com_tlm_u_tlm_rx_data_snk_malformed_checks_cfg1_ip_0_sqmuxa) + ); + defparam com_tlm_u_tlm_rx_data_snk_malformed_checks_malformed_maxsize_3_0_0_0_0_a2_0_1.INIT = 16'h1000; + LUT4 com_tlm_u_tlm_rx_data_snk_malformed_checks_malformed_maxsize_3_0_0_0_0_a2_0_1 ( + .I0(com_tlm_u_tlm_rx_data_snk_cur_length_2__6), + .I1(com_tlm_u_tlm_rx_data_snk_cur_length[7]), + .I2(com_tlm_u_tlm_rx_data_snk_malformed_checks_malformed_maxsize_3_0_0_0_0_a2_0_1_4_5194), + .I3(com_tlm_u_tlm_rx_data_snk_malformed_checks_malformed_maxsize_3_0_0_0_0_a2_0_1_5_5193), + .O(com_tlm_u_tlm_rx_data_snk_malformed_checks_N_57276_1) + ); + defparam com_tlm_u_tlm_rx_data_snk_malformed_checks_type_1dw_0_sqmuxa_i_0_0_0.INIT = 16'h4600; + LUT4 com_tlm_u_tlm_rx_data_snk_malformed_checks_type_1dw_0_sqmuxa_i_0_0_0 ( + .I0(com_tlm_u_tlm_rx_data_snk_malformed_checks_cur_fulltype[1]), + .I1(com_tlm_u_tlm_rx_data_snk_malformed_checks_cur_fulltype[2]), + .I2(com_tlm_u_tlm_rx_data_snk_malformed_checks_fulltype_in_0__5233), + .I3(com_tlm_u_tlm_rx_data_snk_malformed_checks_type_1dw_0_sqmuxa_i_0_0_0_1_5195), + .O(com_tlm_u_tlm_rx_data_snk_malformed_checks_N_13912_i) + ); + defparam com_tlm_u_tlm_rx_data_snk_malformed_checks_malformed_fulltype16_0_0_0_0_39380.INIT = 16'hF107; + LUT4 com_tlm_u_tlm_rx_data_snk_malformed_checks_malformed_fulltype16_0_0_0_0_39380 ( + .I0(com_tlm_u_tlm_rx_data_snk_malformed_checks_cur_fulltype[1]), + .I1(com_tlm_u_tlm_rx_data_snk_malformed_checks_cur_fulltype[2]), + .I2(com_tlm_u_tlm_rx_data_snk_malformed_checks_cur_fulltype[4]), + .I3(com_tlm_u_tlm_rx_data_snk_malformed_checks_fulltype_in_5__5232), + .O(com_tlm_u_tlm_rx_data_snk_malformed_checks_malformed_fulltype16_0_0_0_0_39380_5196) + ); + defparam com_tlm_u_tlm_rx_data_snk_malformed_checks_fulltype_tc012_i_0_0_0.INIT = 16'h5515; + LUT4_L com_tlm_u_tlm_rx_data_snk_malformed_checks_fulltype_tc012_i_0_0_0 ( + .I0(com_tlm_u_tlm_rx_data_snk_malformed_checks_N_58513), + .I1(com_tlm_u_tlm_rx_data_snk_N_59435_1), + .I2(com_lnk_rd_6113[56]), + .I3(com_lnk_rd_6113[62]), + .LO(com_tlm_u_tlm_rx_data_snk_malformed_checks_fulltype_tc012_i_0_0_0_5221) + ); + defparam com_tlm_u_tlm_rx_data_snk_malformed_checks_malformed_fulltype16_0_0_0_0_1.INIT = 16'h4CCC; + LUT4 com_tlm_u_tlm_rx_data_snk_malformed_checks_malformed_fulltype16_0_0_0_0_1 ( + .I0(com_tlm_u_tlm_rx_data_snk_N_56246_i), + .I1(com_tlm_u_tlm_rx_data_snk_malformed_checks_malformed_fulltype16_0_0_0_0_39380_5196), + .I2(com_tlm_u_tlm_rx_data_snk_malformed_checks_cur_fulltype[1]), + .I3(com_tlm_u_tlm_rx_data_snk_malformed_checks_fulltype_in_0__5233), + .O(com_tlm_u_tlm_rx_data_snk_malformed_checks_malformed_fulltype16_0_0_0_0_1_5224) + ); + defparam com_tlm_u_tlm_rx_data_snk_malformed_checks_delay_ctc.INIT = 16'hE080; + LUT4_L com_tlm_u_tlm_rx_data_snk_malformed_checks_delay_ctc ( + .I0(com_tlm_u_tlm_rx_data_snk_malformed_checks_N_56346_i), + .I1(com_tlm_u_tlm_rx_data_snk_cur_td_5119), + .I2(com_tlm_u_tlm_rx_data_snk_latch_1st_dword_q1_5067), + .I3(com_tlm_u_tlm_rx_data_snk_malformed_checks_fulltype_in_5__5232), + .LO(com_tlm_u_tlm_rx_data_snk_malformed_checks_delay_ctc_i) + ); + defparam com_tlm_u_tlm_rx_data_snk_malformed_checks_un11_data_credits_o_1_a2_0_a2_0_a2_0_a2_1_.INIT = 4'h8; + LUT2_L com_tlm_u_tlm_rx_data_snk_malformed_checks_un11_data_credits_o_1_a2_0_a2_0_a2_0_a2_1_ ( + .I0(com_tlm_u_tlm_rx_data_snk_malformed_checks_un1_data_credits_o_s_1_5197), + .I1(com_tlm_u_tlm_rx_data_snk_cur_fulltype[6]), + .LO(com_tlm_u_tlm_rx_data_snk_malformed_checks_un11_data_credits_o_1_a2_0_a2_0_a2_0_a2[1]) + ); + defparam com_tlm_u_tlm_rx_data_snk_malformed_checks_un11_data_credits_o_1_a2_0_a2_0_a2_0_a2_0_.INIT = 4'h8; + LUT2_L com_tlm_u_tlm_rx_data_snk_malformed_checks_un11_data_credits_o_1_a2_0_a2_0_a2_0_a2_0_ ( + .I0(com_tlm_u_tlm_rx_data_snk_malformed_checks_un1_data_credits_o_s_0_5198), + .I1(com_tlm_u_tlm_rx_data_snk_cur_fulltype[6]), + .LO(com_tlm_u_tlm_rx_data_snk_malformed_checks_un11_data_credits_o_1_a2_0_a2_0_a2_0_a2[0]) + ); + defparam com_tlm_u_tlm_rx_data_snk_malformed_checks_un11_data_credits_o_1_a2_0_a2_0_a2_0_a2_5_.INIT = 4'h8; + LUT2_L com_tlm_u_tlm_rx_data_snk_malformed_checks_un11_data_credits_o_1_a2_0_a2_0_a2_0_a2_5_ ( + .I0(com_tlm_u_tlm_rx_data_snk_malformed_checks_un1_data_credits_o_s_5_5199), + .I1(com_tlm_u_tlm_rx_data_snk_cur_fulltype[6]), + .LO(com_tlm_u_tlm_rx_data_snk_malformed_checks_un11_data_credits_o_1_a2_0_a2_0_a2_0_a2[5]) + ); + defparam com_tlm_u_tlm_rx_data_snk_malformed_checks_un11_data_credits_o_1_a2_0_a2_0_a2_0_a2_4_.INIT = 4'h8; + LUT2_L com_tlm_u_tlm_rx_data_snk_malformed_checks_un11_data_credits_o_1_a2_0_a2_0_a2_0_a2_4_ ( + .I0(com_tlm_u_tlm_rx_data_snk_malformed_checks_un1_data_credits_o_s_4_5200), + .I1(com_tlm_u_tlm_rx_data_snk_cur_fulltype[6]), + .LO(com_tlm_u_tlm_rx_data_snk_malformed_checks_un11_data_credits_o_1_a2_0_a2_0_a2_0_a2[4]) + ); + defparam com_tlm_u_tlm_rx_data_snk_malformed_checks_un11_data_credits_o_1_a2_0_a2_0_a2_0_a2_3_.INIT = 4'h8; + LUT2_L com_tlm_u_tlm_rx_data_snk_malformed_checks_un11_data_credits_o_1_a2_0_a2_0_a2_0_a2_3_ ( + .I0(com_tlm_u_tlm_rx_data_snk_malformed_checks_un1_data_credits_o_s_3_5201), + .I1(com_tlm_u_tlm_rx_data_snk_cur_fulltype[6]), + .LO(com_tlm_u_tlm_rx_data_snk_malformed_checks_un11_data_credits_o_1_a2_0_a2_0_a2_0_a2[3]) + ); + defparam com_tlm_u_tlm_rx_data_snk_malformed_checks_un11_data_credits_o_1_a2_0_a2_0_a2_0_a2_2_.INIT = 4'h8; + LUT2_L com_tlm_u_tlm_rx_data_snk_malformed_checks_un11_data_credits_o_1_a2_0_a2_0_a2_0_a2_2_ ( + .I0(com_tlm_u_tlm_rx_data_snk_malformed_checks_un1_data_credits_o_s_2_5202), + .I1(com_tlm_u_tlm_rx_data_snk_cur_fulltype[6]), + .LO(com_tlm_u_tlm_rx_data_snk_malformed_checks_un11_data_credits_o_1_a2_0_a2_0_a2_0_a2[2]) + ); + defparam com_tlm_u_tlm_rx_data_snk_malformed_checks_N_62722_i.INIT = 4'hE; + LUT2_L com_tlm_u_tlm_rx_data_snk_malformed_checks_N_62722_i ( + .I0(com_tlm_u_tlm_rx_data_snk_malformed_checks_malformed_fmt_5205), + .I1(com_tlm_u_tlm_rx_data_snk_malformed_checks_malformed_len_5204), + .LO(com_tlm_u_tlm_rx_data_snk_malformed_checks_N_62722_i_5203) + ); + defparam com_tlm_u_tlm_rx_data_snk_malformed_checks_N_59447_i.INIT = 16'hFFFE; + LUT4_L com_tlm_u_tlm_rx_data_snk_malformed_checks_N_59447_i ( + .I0(com_tlm_u_tlm_rx_data_snk_malformed_checks_malformed_eof_5209), + .I1(com_tlm_u_tlm_rx_data_snk_malformed_checks_malformed_min_5208), + .I2(com_tlm_u_tlm_rx_data_snk_malformed_checks_malformed_over_5227), + .I3(com_tlm_u_tlm_rx_data_snk_malformed_checks_malformed_rem_5207), + .LO(com_tlm_u_tlm_rx_data_snk_malformed_checks_N_59447_i_5206) + ); + defparam com_tlm_u_tlm_rx_data_snk_malformed_checks_msgcode_vendef12_0_a2_0_a2_0_a2.INIT = 16'h8000; + LUT4_L com_tlm_u_tlm_rx_data_snk_malformed_checks_msgcode_vendef12_0_a2_0_a2_0_a2 ( + .I0(com_tlm_u_tlm_rx_data_snk_malformed_checks_N_56244_i), + .I1(com_tlm_u_tlm_rx_data_snk_malformed_checks_N_56353_i), + .I2(com_tlm_u_tlm_rx_data_snk_malformed_checks_N_58343), + .I3(com_lnk_rd[5]), + .LO(com_tlm_u_tlm_rx_data_snk_malformed_checks_msgcode_vendef12) + ); + defparam com_tlm_u_tlm_rx_data_snk_malformed_checks_is_usr_leg_ap_3_0_a2_0_a2_0_a2_0_a2.INIT = 16'h0200; + LUT4_L com_tlm_u_tlm_rx_data_snk_malformed_checks_is_usr_leg_ap_3_0_a2_0_a2_0_a2_0_a2 ( + .I0(com_tlm_u_tlm_rx_data_snk_malformed_checks_N_59001), + .I1(com_lnk_rd_6113[40]), + .I2(com_lnk_rd_6113[41]), + .I3(com_tlm_u_tlm_rx_data_snk_malformed_checks_is_usr_leg_ap_3_0_a2_0_a2_0_a2_0_a2_1), + .LO(com_tlm_u_tlm_rx_data_snk_malformed_checks_is_usr_leg_ap_3) + ); + defparam com_tlm_u_tlm_rx_data_snk_malformed_checks_length_1dw_3_0_a2_0_a2_0_a2.INIT = 4'h8; + LUT2_L com_tlm_u_tlm_rx_data_snk_malformed_checks_length_1dw_3_0_a2_0_a2_0_a2 ( + .I0(com_tlm_u_tlm_rx_data_snk_malformed_checks_N_57276_1), + .I1(com_tlm_u_tlm_rx_data_snk_cur_length_0__2), + .LO(com_tlm_u_tlm_rx_data_snk_malformed_checks_length_1dw_3) + ); + defparam com_tlm_u_tlm_rx_data_snk_malformed_checks_N_87170_i.INIT = 8'h1C; + LUT3_L com_tlm_u_tlm_rx_data_snk_malformed_checks_N_87170_i ( + .I0(com_lnk_rd_6113[56]), + .I1(com_lnk_rd_6113[57]), + .I2(com_lnk_rd_6113[58]), + .LO(com_tlm_u_tlm_rx_data_snk_malformed_checks_N_87170_i_5234) + ); + defparam com_tlm_u_tlm_rx_data_snk_malformed_checks_N_62723_i.INIT = 16'hCCCE; + LUT4_L com_tlm_u_tlm_rx_data_snk_malformed_checks_N_62723_i ( + .I0(com_tlm_u_tlm_rx_data_snk_malformed_checks_cfg0_ip_5214), + .I1(com_tlm_u_tlm_rx_data_snk_malformed_checks_cfg1_ip_5213), + .I2(com_tlm_u_tlm_rx_data_snk_malformed_checks_is_usr_ext_ap_5212), + .I3(com_tlm_u_tlm_rx_data_snk_malformed_checks_is_usr_leg_ap_5211), + .LO(com_tlm_u_tlm_rx_data_snk_malformed_checks_N_62723_i_5210) + ); + defparam com_tlm_u_tlm_rx_data_snk_malformed_checks_N_85660_i.INIT = 16'hFFFD; + LUT4_L com_tlm_u_tlm_rx_data_snk_malformed_checks_N_85660_i ( + .I0(com_tlm_u_tlm_rx_data_snk_malformed_checks_malformed_fmt_3_i_0_0_2_5219), + .I1(com_tlm_u_tlm_rx_data_snk_malformed_checks_malformed_fulltype_5218), + .I2(com_tlm_u_tlm_rx_data_snk_malformed_checks_malformed_maxsize_5217), + .I3(com_tlm_u_tlm_rx_data_snk_malformed_checks_malformed_tc_5216), + .LO(com_tlm_u_tlm_rx_data_snk_malformed_checks_N_85660_i_5215) + ); + defparam com_tlm_u_tlm_rx_data_snk_malformed_checks_uc_pwr_mgmt_7_0_a2_0_a2_0_a2_0_a2.INIT = 16'h0800; + LUT4_L com_tlm_u_tlm_rx_data_snk_malformed_checks_uc_pwr_mgmt_7_0_a2_0_a2_0_a2_0_a2 ( + .I0(com_tlm_u_tlm_rx_data_snk_malformed_checks_N_56501_i), + .I1(com_tlm_u_tlm_rx_data_snk_malformed_checks_cur_fulltype[3]), + .I2(com_tlm_u_tlm_rx_data_snk_malformed_checks_fulltype_in_5__5232), + .I3(com_tlm_u_tlm_rx_data_snk_malformed_checks_uc_pwr_mgmt_7_1), + .LO(com_tlm_u_tlm_rx_data_snk_malformed_checks_uc_pwr_mgmt_7) + ); + defparam com_tlm_u_tlm_rx_data_snk_malformed_checks_malformed_rem_3.INIT = 16'h6996; + LUT4_L com_tlm_u_tlm_rx_data_snk_malformed_checks_malformed_rem_3 ( + .I0(com_tlm_u_tlm_rx_data_snk_malformed_checks_N_56346_i), + .I1(com_lnk_rrem[0]), + .I2(com_tlm_u_tlm_rx_data_snk_cur_td_5119), + .I3(com_tlm_u_tlm_rx_data_snk_malformed_checks_fulltype_in_5__5232), + .LO(com_tlm_u_tlm_rx_data_snk_malformed_checks_malformed_rem_3_5220) + ); + defparam com_tlm_u_tlm_rx_data_snk_malformed_checks_malformed_tc_6_0_i_i_i.INIT = 16'h3230; + LUT4_L com_tlm_u_tlm_rx_data_snk_malformed_checks_malformed_tc_6_0_i_i_i ( + .I0(com_tlm_u_tlm_rx_data_snk_cur_fulltype_oh_1_), + .I1(com_tlm_u_tlm_rx_data_snk_cur_tc0_5121), + .I2(com_tlm_u_tlm_rx_data_snk_malformed_checks_fulltype_tc0_5237), + .I3(com_tlm_u_tlm_rx_data_snk_malformed_checks_msgcode_sigdef_5240), + .LO(com_tlm_u_tlm_rx_data_snk_malformed_checks_N_53153_i) + ); + defparam com_tlm_u_tlm_rx_data_snk_malformed_checks_N_85558_i.INIT = 16'h90FF; + LUT4_L com_tlm_u_tlm_rx_data_snk_malformed_checks_N_85558_i ( + .I0(com_lnk_rd_6113[56]), + .I1(com_lnk_rd_6113[59]), + .I2(com_tlm_u_tlm_rx_data_snk_cur_fulltype_oh40_1), + .I3(com_tlm_u_tlm_rx_data_snk_malformed_checks_fulltype_tc012_i_0_0_0_5221), + .LO(com_tlm_u_tlm_rx_data_snk_malformed_checks_N_85558_i_5236) + ); + defparam com_tlm_u_tlm_rx_data_snk_malformed_checks_msgcode_hotplug12_0_0_0.INIT = 16'h0400; + LUT4_L com_tlm_u_tlm_rx_data_snk_malformed_checks_msgcode_hotplug12_0_0_0 ( + .I0(N_56103_i), + .I1(com_tlm_u_tlm_rx_data_snk_malformed_checks_N_56244_i), + .I2(N_57268), + .I3(com_tlm_u_tlm_rx_data_snk_malformed_checks_msgcode_hotplug12_0_0_0_0_5222), + .LO(com_tlm_u_tlm_rx_data_snk_malformed_checks_N_10641_i) + ); + defparam com_tlm_u_tlm_rx_data_snk_malformed_checks_N_85578_i.INIT = 16'hDCFF; + LUT4_L com_tlm_u_tlm_rx_data_snk_malformed_checks_N_85578_i ( + .I0(com_tlm_u_tlm_rx_data_snk_malformed_checks_N_56501_i), + .I1(com_tlm_u_tlm_rx_data_snk_malformed_checks_N_58350), + .I2(com_tlm_u_tlm_rx_data_snk_malformed_checks_cur_fulltype[3]), + .I3(com_tlm_u_tlm_rx_data_snk_malformed_checks_malformed_fulltype16_0_0_0_0_1_5224), + .LO(com_tlm_u_tlm_rx_data_snk_malformed_checks_N_85578_i_5223) + ); + defparam com_tlm_u_tlm_rx_data_snk_malformed_checks_msgd_check_64_msgcode_dmatch_4_0_x3_0_x3_0_x3.INIT = 8'hC6; + LUT3_L com_tlm_u_tlm_rx_data_snk_malformed_checks_msgd_check_64_msgcode_dmatch_4_0_x3_0_x3_0_x3 ( + .I0(com_tlm_u_tlm_rx_data_snk_malformed_checks_N_56050_i), + .I1(com_tlm_u_tlm_rx_data_snk_malformed_checks_msgcode_dmatch_4_0_x3_0_x3_0_o3_0), + .I2(com_lnk_rd_6113[62]), + .LO(com_tlm_u_tlm_rx_data_snk_malformed_checks_N_57044_i_0) + ); + defparam com_tlm_u_tlm_rx_data_snk_malformed_checks_msgcode_sigdef16_0_0_0.INIT = 16'h0200; + LUT4_L com_tlm_u_tlm_rx_data_snk_malformed_checks_msgcode_sigdef16_0_0_0 ( + .I0(com_tlm_u_tlm_rx_data_snk_N_56488_i), + .I1(com_tlm_u_tlm_rx_data_snk_malformed_checks_N_58342), + .I2(com_tlm_u_tlm_rx_data_snk_malformed_checks_N_58343), + .I3(com_tlm_u_tlm_rx_data_snk_malformed_checks_msgcode_sigdef16_0_0_0_39393_5225), + .LO(com_tlm_u_tlm_rx_data_snk_malformed_checks_N_10638_i) + ); + defparam com_tlm_u_tlm_rx_data_snk_malformed_checks_ur_pwr_mgmt_7_i_0_0_0.INIT = 16'h5700; + LUT4_L com_tlm_u_tlm_rx_data_snk_malformed_checks_ur_pwr_mgmt_7_i_0_0_0 ( + .I0(com_tlm_u_tlm_rx_data_snk_malformed_checks_cur_fulltype[1]), + .I1(com_tlm_u_tlm_rx_data_snk_malformed_checks_fulltype_in_0__5233), + .I2(com_tlm_u_tlm_rx_data_snk_malformed_checks_fulltype_in_5__5232), + .I3(com_tlm_u_tlm_rx_data_snk_malformed_checks_ur_pwr_mgmt_7_i_0_0_0_1_5226), + .LO(com_tlm_u_tlm_rx_data_snk_malformed_checks_N_13914_i) + ); + defparam com_tlm_u_tlm_rx_data_snk_malformed_checks_malformed_over_3_i_0_0.INIT = 16'h3302; + LUT4_L com_tlm_u_tlm_rx_data_snk_malformed_checks_malformed_over_3_i_0_0 ( + .I0(com_tlm_u_tlm_rx_data_snk_malformed_checks_N_57047_i), + .I1(com_tlm_u_tlm_rx_data_snk_latch_1st_dword_q1_5067), + .I2(com_tlm_u_tlm_rx_data_snk_malformed_checks_delay_ct_5247), + .I3(com_tlm_u_tlm_rx_data_snk_malformed_checks_malformed_over_5227), + .LO(com_tlm_u_tlm_rx_data_snk_malformed_checks_N_28370_i) + ); + defparam com_tlm_u_tlm_rx_data_snk_malformed_checks_N_87098_i.INIT = 16'hCC08; + LUT4_L com_tlm_u_tlm_rx_data_snk_malformed_checks_N_87098_i ( + .I0(com_tlm_u_tlm_rx_data_snk_malformed_checks_N_57276_1), + .I1(com_tlm_u_tlm_rx_data_snk_cur_fulltype[6]), + .I2(com_tlm_u_tlm_rx_data_snk_cur_length_0__2), + .I3(com_tlm_u_tlm_rx_data_snk_malformed_checks_un6_malformed_maxsize_cry_9_5229), + .LO(com_tlm_u_tlm_rx_data_snk_malformed_checks_N_87098_i_5228) + ); + defparam com_tlm_u_tlm_rx_data_snk_malformed_checks_N_10359_i_0_0_0_0.INIT = 8'h80; + LUT3_L com_tlm_u_tlm_rx_data_snk_malformed_checks_N_10359_i_0_0_0_0 ( + .I0(com_tlm_u_tlm_rx_data_snk_N_56509_i), + .I1(com_tlm_u_tlm_rx_data_snk_malformed_checks_N_10359_i_0_0_0_0_39304_5230), + .I2(com_tlm_u_tlm_rx_data_snk_sof_q_1__5135), + .LO(com_tlm_u_tlm_rx_data_snk_malformed_checks_N_10359_i_i) + ); + defparam com_tlm_u_tlm_rx_data_snk_malformed_checks_word_ct_d_1_0_0_6_.INIT = 16'h707F; + LUT4_L com_tlm_u_tlm_rx_data_snk_malformed_checks_word_ct_d_1_0_0_6_ ( + .I0(com_tlm_u_tlm_rx_data_snk_cur_fulltype[6]), + .I1(com_tlm_u_tlm_rx_data_snk_cur_length[7]), + .I2(com_tlm_u_tlm_rx_data_snk_latch_1st_dword_q1_5067), + .I3(com_tlm_u_tlm_rx_data_snk_malformed_checks_word_ct[6]), + .LO(com_tlm_u_tlm_rx_data_snk_malformed_checks_word_ct_d_i[6]) + ); + defparam com_tlm_u_tlm_rx_data_snk_malformed_checks_word_ct_d_1_0_0_5_.INIT = 16'h707F; + LUT4_L com_tlm_u_tlm_rx_data_snk_malformed_checks_word_ct_d_1_0_0_5_ ( + .I0(com_tlm_u_tlm_rx_data_snk_cur_fulltype[6]), + .I1(com_tlm_u_tlm_rx_data_snk_cur_length[6]), + .I2(com_tlm_u_tlm_rx_data_snk_latch_1st_dword_q1_5067), + .I3(com_tlm_u_tlm_rx_data_snk_malformed_checks_word_ct[5]), + .LO(com_tlm_u_tlm_rx_data_snk_malformed_checks_word_ct_d_i[5]) + ); + defparam com_tlm_u_tlm_rx_data_snk_malformed_checks_word_ct_d_1_0_0_4_.INIT = 16'h707F; + LUT4_L com_tlm_u_tlm_rx_data_snk_malformed_checks_word_ct_d_1_0_0_4_ ( + .I0(com_tlm_u_tlm_rx_data_snk_cur_fulltype[6]), + .I1(com_tlm_u_tlm_rx_data_snk_cur_length[5]), + .I2(com_tlm_u_tlm_rx_data_snk_latch_1st_dword_q1_5067), + .I3(com_tlm_u_tlm_rx_data_snk_malformed_checks_word_ct[4]), + .LO(com_tlm_u_tlm_rx_data_snk_malformed_checks_word_ct_d_i[4]) + ); + defparam com_tlm_u_tlm_rx_data_snk_malformed_checks_word_ct_d_1_0_0_3_.INIT = 16'h707F; + LUT4_L com_tlm_u_tlm_rx_data_snk_malformed_checks_word_ct_d_1_0_0_3_ ( + .I0(com_tlm_u_tlm_rx_data_snk_cur_fulltype[6]), + .I1(com_tlm_u_tlm_rx_data_snk_cur_length_4__10), + .I2(com_tlm_u_tlm_rx_data_snk_latch_1st_dword_q1_5067), + .I3(com_tlm_u_tlm_rx_data_snk_malformed_checks_word_ct[3]), + .LO(com_tlm_u_tlm_rx_data_snk_malformed_checks_word_ct_d_i[3]) + ); + defparam com_tlm_u_tlm_rx_data_snk_malformed_checks_word_ct_d_1_0_0_2_.INIT = 16'h707F; + LUT4_L com_tlm_u_tlm_rx_data_snk_malformed_checks_word_ct_d_1_0_0_2_ ( + .I0(com_tlm_u_tlm_rx_data_snk_cur_fulltype[6]), + .I1(com_tlm_u_tlm_rx_data_snk_cur_length_3__8), + .I2(com_tlm_u_tlm_rx_data_snk_latch_1st_dword_q1_5067), + .I3(com_tlm_u_tlm_rx_data_snk_malformed_checks_word_ct[2]), + .LO(com_tlm_u_tlm_rx_data_snk_malformed_checks_word_ct_d_i[2]) + ); + defparam com_tlm_u_tlm_rx_data_snk_malformed_checks_word_ct_d_1_0_0_1_.INIT = 16'h707F; + LUT4_L com_tlm_u_tlm_rx_data_snk_malformed_checks_word_ct_d_1_0_0_1_ ( + .I0(com_tlm_u_tlm_rx_data_snk_cur_fulltype[6]), + .I1(com_tlm_u_tlm_rx_data_snk_cur_length_2__6), + .I2(com_tlm_u_tlm_rx_data_snk_latch_1st_dword_q1_5067), + .I3(com_tlm_u_tlm_rx_data_snk_malformed_checks_word_ct[1]), + .LO(com_tlm_u_tlm_rx_data_snk_malformed_checks_word_ct_d_i[1]) + ); + defparam com_tlm_u_tlm_rx_data_snk_malformed_checks_check_int_msgcode_routing18_0_0_0.INIT = 4'h8; + LUT2_L com_tlm_u_tlm_rx_data_snk_malformed_checks_check_int_msgcode_routing18_0_0_0 ( + .I0(com_tlm_u_tlm_rx_data_snk_malformed_checks_N_10637_i_1), + .I1(N_56031_i), + .LO(com_tlm_u_tlm_rx_data_snk_malformed_checks_msgcode_routing18_i_i) + ); + defparam com_tlm_u_tlm_rx_data_snk_malformed_checks_check_int_un1_msgcode_routing19_0_0_0.INIT = 16'h0A02; + LUT4_L com_tlm_u_tlm_rx_data_snk_malformed_checks_check_int_un1_msgcode_routing19_0_0_0 ( + .I0(com_tlm_u_tlm_rx_data_snk_malformed_checks_N_10637_i_1), + .I1(com_lnk_rd[1]), + .I2(com_lnk_rd[2]), + .I3(com_lnk_rd[4]), + .LO(com_tlm_u_tlm_rx_data_snk_malformed_checks_N_10637_i) + ); + defparam com_tlm_u_tlm_rx_data_snk_malformed_checks_un1_fulltype_i_3_0_a2_0_a2_0_a2.INIT = 16'h0080; + LUT4_L com_tlm_u_tlm_rx_data_snk_malformed_checks_un1_fulltype_i_3_0_a2_0_a2_0_a2 ( + .I0(com_tlm_u_tlm_rx_data_snk_N_56191_i), + .I1(com_tlm_u_tlm_rx_data_snk_N_56507_i), + .I2(com_lnk_rd_6113[57]), + .I3(com_lnk_rd_6113[59]), + .LO(com_tlm_u_tlm_rx_data_snk_cur_fulltype_oh37) + ); + defparam com_tlm_u_tlm_rx_data_snk_malformed_checks_malformed_eof_3_i_0_0_1.INIT = 16'h0002; + LUT4 com_tlm_u_tlm_rx_data_snk_malformed_checks_malformed_eof_3_i_0_0_1 ( + .I0(com_tlm_u_tlm_rx_data_snk_malformed_checks_malformed_eof_3_i_0_0_a2_0_4_5231), + .I1(com_tlm_u_tlm_rx_data_snk_malformed_checks_word_ct[0]), + .I2(com_tlm_u_tlm_rx_data_snk_malformed_checks_word_ct[4]), + .I3(com_tlm_u_tlm_rx_data_snk_malformed_checks_word_ct[6]), + .O(com_tlm_u_tlm_rx_data_snk_malformed_checks_malformed_eof_3_i_0_0_1_5246) + ); + defparam com_tlm_u_tlm_rx_data_snk_malformed_checks_N_85575_i_1.INIT = 16'h7BFF; + LUT4 com_tlm_u_tlm_rx_data_snk_malformed_checks_N_85575_i_1 ( + .I0(com_tlm_u_tlm_rx_data_snk_malformed_checks_fulltype_in_0__5233), + .I1(com_tlm_u_tlm_rx_data_snk_malformed_checks_msgcode_dmatch_5239), + .I2(com_tlm_u_tlm_rx_data_snk_malformed_checks_msgcode_routing[0]), + .I3(com_tlm_u_tlm_rx_data_snk_malformed_checks_msgcode_sigdef_5240), + .O(com_tlm_u_tlm_rx_data_snk_malformed_checks_N_85575_i_1_5245) + ); + FDE com_tlm_u_tlm_rx_data_snk_malformed_checks_data_credits_o_1_ ( + .CE(com_tlm_u_tlm_rx_data_snk_latch_3rd_dword_q1), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_malformed_checks_un11_data_credits_o_1_a2_0_a2_0_a2_0_a2[1]), + .Q(com_tlm_u_tlm_rx_data_snk_cur_data_credits[1]) + ); + FDE com_tlm_u_tlm_rx_data_snk_malformed_checks_data_credits_o_0_ ( + .CE(com_tlm_u_tlm_rx_data_snk_latch_3rd_dword_q1), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_malformed_checks_un11_data_credits_o_1_a2_0_a2_0_a2_0_a2[0]), + .Q(com_tlm_u_tlm_rx_data_snk_cur_data_credits[0]) + ); + FDE com_tlm_u_tlm_rx_data_snk_malformed_checks_data_credits_o_5_ ( + .CE(com_tlm_u_tlm_rx_data_snk_latch_3rd_dword_q1), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_malformed_checks_un11_data_credits_o_1_a2_0_a2_0_a2_0_a2[5]), + .Q(com_tlm_u_tlm_rx_data_snk_cur_data_credits[5]) + ); + FDE com_tlm_u_tlm_rx_data_snk_malformed_checks_data_credits_o_4_ ( + .CE(com_tlm_u_tlm_rx_data_snk_latch_3rd_dword_q1), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_malformed_checks_un11_data_credits_o_1_a2_0_a2_0_a2_0_a2[4]), + .Q(com_tlm_u_tlm_rx_data_snk_cur_data_credits[4]) + ); + FDE com_tlm_u_tlm_rx_data_snk_malformed_checks_data_credits_o_3_ ( + .CE(com_tlm_u_tlm_rx_data_snk_latch_3rd_dword_q1), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_malformed_checks_un11_data_credits_o_1_a2_0_a2_0_a2_0_a2[3]), + .Q(com_tlm_u_tlm_rx_data_snk_cur_data_credits[3]) + ); + FDE com_tlm_u_tlm_rx_data_snk_malformed_checks_data_credits_o_2_ ( + .CE(com_tlm_u_tlm_rx_data_snk_latch_3rd_dword_q1), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_malformed_checks_un11_data_credits_o_1_a2_0_a2_0_a2_0_a2[2]), + .Q(com_tlm_u_tlm_rx_data_snk_cur_data_credits[2]) + ); + FDE com_tlm_u_tlm_rx_data_snk_malformed_checks_fulltype_in_6_ ( + .CE(com_tlm_u_tlm_rx_data_snk_latch_2nd_dword), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_lnk_rd_6113[62]), + .Q(com_tlm_u_tlm_rx_data_snk_cur_fulltype[6]) + ); + FDE com_tlm_u_tlm_rx_data_snk_malformed_checks_fulltype_in_5_ ( + .CE(com_tlm_u_tlm_rx_data_snk_latch_2nd_dword), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_lnk_rd_6113[61]), + .Q(com_tlm_u_tlm_rx_data_snk_malformed_checks_fulltype_in_5__5232) + ); + FDE com_tlm_u_tlm_rx_data_snk_malformed_checks_fulltype_in_4_ ( + .CE(com_tlm_u_tlm_rx_data_snk_latch_2nd_dword), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_lnk_rd_6113[60]), + .Q(com_tlm_u_tlm_rx_data_snk_malformed_checks_cur_fulltype[4]) + ); + FDE com_tlm_u_tlm_rx_data_snk_malformed_checks_fulltype_in_3_ ( + .CE(com_tlm_u_tlm_rx_data_snk_latch_2nd_dword), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_lnk_rd_6113[59]), + .Q(com_tlm_u_tlm_rx_data_snk_malformed_checks_cur_fulltype[3]) + ); + FDE com_tlm_u_tlm_rx_data_snk_malformed_checks_fulltype_in_2_ ( + .CE(com_tlm_u_tlm_rx_data_snk_latch_2nd_dword), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_lnk_rd_6113[58]), + .Q(com_tlm_u_tlm_rx_data_snk_malformed_checks_cur_fulltype[2]) + ); + FDE com_tlm_u_tlm_rx_data_snk_malformed_checks_fulltype_in_1_ ( + .CE(com_tlm_u_tlm_rx_data_snk_latch_2nd_dword), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_lnk_rd_6113[57]), + .Q(com_tlm_u_tlm_rx_data_snk_malformed_checks_cur_fulltype[1]) + ); + FDE com_tlm_u_tlm_rx_data_snk_malformed_checks_fulltype_in_0_ ( + .CE(com_tlm_u_tlm_rx_data_snk_latch_2nd_dword), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_lnk_rd_6113[56]), + .Q(com_tlm_u_tlm_rx_data_snk_malformed_checks_fulltype_in_0__5233) + ); + FDE com_tlm_u_tlm_rx_data_snk_malformed_checks_ismsgany ( + .CE(com_tlm_u_tlm_rx_data_snk_latch_2nd_dword), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_malformed_checks_N_56050_i), + .Q(com_tlm_u_tlm_rx_data_snk_cur_fulltype_oh_1_) + ); + FDE com_tlm_u_tlm_rx_data_snk_malformed_checks_msgcode_vendef ( + .CE(com_tlm_u_tlm_rx_data_snk_latch_2nd_dword), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_malformed_checks_msgcode_vendef12), + .Q(com_tlm_u_tlm_rx_data_snk_malformed_checks_msgcode_vendef_5243) + ); + FDE com_tlm_u_tlm_rx_data_snk_malformed_checks_routing_vendef ( + .CE(com_tlm_u_tlm_rx_data_snk_latch_2nd_dword), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_malformed_checks_N_87170_i_5234), + .Q(com_tlm_u_tlm_rx_data_snk_malformed_checks_routing_vendef_5235) + ); + FDE com_tlm_u_tlm_rx_data_snk_malformed_checks_fulltype_tc0 ( + .CE(com_tlm_u_tlm_rx_data_snk_latch_2nd_dword), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_malformed_checks_N_85558_i_5236), + .Q(com_tlm_u_tlm_rx_data_snk_malformed_checks_fulltype_tc0_5237) + ); + FDE com_tlm_u_tlm_rx_data_snk_malformed_checks_msgcode_hotplug ( + .CE(com_tlm_u_tlm_rx_data_snk_latch_2nd_dword), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_malformed_checks_N_10641_i), + .Q(com_tlm_u_tlm_rx_data_snk_malformed_checks_msgcode_hotplug_5238) + ); + FDE com_tlm_u_tlm_rx_data_snk_malformed_checks_msgcode_dmatch ( + .CE(com_tlm_u_tlm_rx_data_snk_latch_2nd_dword), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_malformed_checks_N_57044_i_0), + .Q(com_tlm_u_tlm_rx_data_snk_malformed_checks_msgcode_dmatch_5239) + ); + FDE com_tlm_u_tlm_rx_data_snk_malformed_checks_msgcode_sigdef ( + .CE(com_tlm_u_tlm_rx_data_snk_latch_2nd_dword), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_malformed_checks_N_10638_i), + .Q(com_tlm_u_tlm_rx_data_snk_malformed_checks_msgcode_sigdef_5240) + ); + FDE com_tlm_u_tlm_rx_data_snk_malformed_checks_msgcode_routing_2_ ( + .CE(com_tlm_u_tlm_rx_data_snk_latch_2nd_dword), + .C(NlwRenamedSig_OI_trn_clk), + .D(N_17347_i), + .Q(com_tlm_u_tlm_rx_data_snk_malformed_checks_msgcode_routing[2]) + ); + FDE com_tlm_u_tlm_rx_data_snk_malformed_checks_msgcode_routing_1_ ( + .CE(com_tlm_u_tlm_rx_data_snk_latch_2nd_dword), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_malformed_checks_msgcode_routing18_i_i), + .Q(com_tlm_u_tlm_rx_data_snk_malformed_checks_msgcode_routing[1]) + ); + FDE com_tlm_u_tlm_rx_data_snk_malformed_checks_msgcode_routing_0_ ( + .CE(com_tlm_u_tlm_rx_data_snk_latch_2nd_dword), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_malformed_checks_N_10637_i), + .Q(com_tlm_u_tlm_rx_data_snk_malformed_checks_msgcode_routing[0]) + ); + INV com_tlm_u_tlm_rx_data_snk_malformed_checks_delay_ct_i ( + .I(com_tlm_u_tlm_rx_data_snk_malformed_checks_delay_ct_5247), + .O(com_tlm_u_tlm_rx_data_snk_malformed_checks_delay_ct_i_5241) + ); + defparam com_tlm_u_tlm_rx_data_snk_malformed_checks_is_usr_ext_ap_3_i_0_0_0.INIT = 8'hA8; + LUT3_L com_tlm_u_tlm_rx_data_snk_malformed_checks_is_usr_ext_ap_3_i_0_0_0 ( + .I0(cfg_cfg_6102[503]), + .I1(com_lnk_rd_6113[43]), + .I2(com_lnk_rd_6113[42]), + .LO(com_tlm_u_tlm_rx_data_snk_malformed_checks_N_25301_i) + ); + defparam com_tlm_u_tlm_rx_data_snk_malformed_checks_N_85575_i.INIT = 16'hAFEF; + LUT4_L com_tlm_u_tlm_rx_data_snk_malformed_checks_N_85575_i ( + .I0(com_tlm_u_tlm_rx_data_snk_malformed_checks_N_57271), + .I1(com_tlm_u_tlm_rx_data_snk_malformed_checks_N_85575_i_1_5245), + .I2(com_tlm_u_tlm_rx_data_snk_malformed_checks_malformed_message_6_0_0_0_0_1_5244), + .I3(com_tlm_u_tlm_rx_data_snk_malformed_checks_msgcode_vendef_5243), + .LO(com_tlm_u_tlm_rx_data_snk_malformed_checks_N_85575_i_5242) + ); + defparam com_tlm_u_tlm_rx_data_snk_malformed_checks_malformed_eof_3_i_0_0.INIT = 16'h1013; + LUT4_L com_tlm_u_tlm_rx_data_snk_malformed_checks_malformed_eof_3_i_0_0 ( + .I0(com_tlm_u_tlm_rx_data_snk_malformed_checks_N_57047_i), + .I1(com_tlm_u_tlm_rx_data_snk_latch_1st_dword_q1_5067), + .I2(com_tlm_u_tlm_rx_data_snk_malformed_checks_delay_ct_5247), + .I3(com_tlm_u_tlm_rx_data_snk_malformed_checks_malformed_eof_3_i_0_0_1_5246), + .LO(com_tlm_u_tlm_rx_data_snk_malformed_checks_N_28368_i) + ); + defparam com_tlm_u_tlm_rx_data_snk_malformed_checks_un1_data_credits_o_axb_4.INIT = 4'h2; + LUT1 com_tlm_u_tlm_rx_data_snk_malformed_checks_un1_data_credits_o_axb_4 ( + .I0(com_tlm_u_tlm_rx_data_snk_cur_length[6]), + .O(com_tlm_u_tlm_rx_data_snk_malformed_checks_un1_data_credits_o_axb_4_5248) + ); + defparam com_tlm_u_tlm_rx_data_snk_malformed_checks_un1_data_credits_o_axb_3.INIT = 4'h2; + LUT1 com_tlm_u_tlm_rx_data_snk_malformed_checks_un1_data_credits_o_axb_3 ( + .I0(com_tlm_u_tlm_rx_data_snk_cur_length[5]), + .O(com_tlm_u_tlm_rx_data_snk_malformed_checks_un1_data_credits_o_axb_3_5249) + ); + defparam com_tlm_u_tlm_rx_data_snk_malformed_checks_un1_data_credits_o_axb_2.INIT = 4'h2; + LUT1 com_tlm_u_tlm_rx_data_snk_malformed_checks_un1_data_credits_o_axb_2 ( + .I0(com_tlm_u_tlm_rx_data_snk_cur_length_4__10), + .O(com_tlm_u_tlm_rx_data_snk_malformed_checks_un1_data_credits_o_axb_2_5250) + ); + defparam com_tlm_u_tlm_rx_data_snk_malformed_checks_un1_data_credits_o_axb_1.INIT = 4'h2; + LUT1 com_tlm_u_tlm_rx_data_snk_malformed_checks_un1_data_credits_o_axb_1 ( + .I0(com_tlm_u_tlm_rx_data_snk_cur_length_3__8), + .O(com_tlm_u_tlm_rx_data_snk_malformed_checks_un1_data_credits_o_axb_1_5251) + ); + defparam com_tlm_u_tlm_rx_data_snk_malformed_checks_un1_data_credits_o_axb_0.INIT = 4'h2; + LUT1 com_tlm_u_tlm_rx_data_snk_malformed_checks_un1_data_credits_o_axb_0 ( + .I0(com_tlm_u_tlm_rx_data_snk_cur_length_2__6), + .O(com_tlm_u_tlm_rx_data_snk_malformed_checks_un1_data_credits_o_axb_0_5252) + ); + defparam com_tlm_u_tlm_rx_data_snk_malformed_checks_un6_malformed_maxsize_axb_7_i.INIT = 4'h9; + LUT2 com_tlm_u_tlm_rx_data_snk_malformed_checks_un6_malformed_maxsize_axb_7_i ( + .I0(com_tlm_u_tlm_rx_data_snk_cur_length[7]), + .I1(com_tlm_u_tlm_rx_data_snk_malformed_checks_max_length[7]), + .O(com_tlm_u_tlm_rx_data_snk_malformed_checks_un6_malformed_maxsize_axb_7_i_5253) + ); + defparam com_tlm_u_tlm_rx_data_snk_malformed_checks_un6_malformed_maxsize_axb_6_i.INIT = 4'h9; + LUT2 com_tlm_u_tlm_rx_data_snk_malformed_checks_un6_malformed_maxsize_axb_6_i ( + .I0(com_tlm_u_tlm_rx_data_snk_cur_length[6]), + .I1(com_tlm_u_tlm_rx_data_snk_malformed_checks_max_length[6]), + .O(com_tlm_u_tlm_rx_data_snk_malformed_checks_un6_malformed_maxsize_axb_6_i_5254) + ); + defparam com_tlm_u_tlm_rx_data_snk_malformed_checks_un6_malformed_maxsize_axb_5_i.INIT = 4'h9; + LUT2 com_tlm_u_tlm_rx_data_snk_malformed_checks_un6_malformed_maxsize_axb_5_i ( + .I0(com_tlm_u_tlm_rx_data_snk_cur_length[5]), + .I1(com_tlm_u_tlm_rx_data_snk_malformed_checks_max_length[5]), + .O(com_tlm_u_tlm_rx_data_snk_malformed_checks_un6_malformed_maxsize_axb_5_i_5255) + ); + FDRE com_tlm_u_tlm_rx_data_snk_pwr_mgmt_cur_pm_turn_off ( + .CE(com_tlm_u_tlm_rx_data_snk_latch_1st_dword_q1_5067), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_pwr_mgmt_cur_pm_turn_off_6), + .Q(com_tlm_u_tlm_rx_data_snk_pwr_mgmt_cur_pm_turn_off_5263), + .R(plm_link_up_i) + ); + FDRE com_tlm_u_tlm_rx_data_snk_pwr_mgmt_cur_pm_set_slot_pwr ( + .CE(com_tlm_u_tlm_rx_data_snk_latch_1st_dword_q1_5067), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_pwr_mgmt_cur_pm_set_slot_pwr_6), + .Q(com_tlm_u_tlm_rx_data_snk_pwr_mgmt_cur_pm_set_slot_pwr_5261), + .R(plm_link_up_i) + ); + FDRE com_tlm_u_tlm_rx_data_snk_pwr_mgmt_cur_pm_as_nak_l1 ( + .CE(com_tlm_u_tlm_rx_data_snk_latch_1st_dword_q1_5067), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_pwr_mgmt_cur_pm_as_nak_l1_6), + .Q(com_tlm_u_tlm_rx_data_snk_pwr_mgmt_cur_pm_as_nak_l1_5259), + .R(plm_link_up_i) + ); + FDRE com_tlm_u_tlm_rx_data_snk_pwr_mgmt_pm_turn_off_o ( + .CE(com_tlm_u_tlm_rx_data_snk_pwr_mgmt_un1_act_pwr_mgmt_i_1_i_5266), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_pwr_mgmt_pm_turn_off_o_5_5262), + .Q(com_cmmt_rpm_turn_off), + .R(plm_link_up_i) + ); + FDRE com_tlm_u_tlm_rx_data_snk_pwr_mgmt_pm_set_slot_pwr_o ( + .CE(com_tlm_u_tlm_rx_data_snk_pwr_mgmt_un1_act_pwr_mgmt_i_1_i_5266), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_pwr_mgmt_pm_set_slot_pwr_o_5_5260), + .Q(com_cmmt_rpm_set_slot_pwr), + .R(plm_link_up_i) + ); + FDRE com_tlm_u_tlm_rx_data_snk_pwr_mgmt_pm_as_nak_l1_o ( + .CE(com_tlm_u_tlm_rx_data_snk_pwr_mgmt_un1_act_pwr_mgmt_i_1_i_5266), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_pwr_mgmt_pm_as_nak_l1_o_5_5258), + .Q(com_cmmt_rpm_as_nak_l1), + .R(plm_link_up_i) + ); + FDRE com_tlm_u_tlm_rx_data_snk_pwr_mgmt_pm_msg_detect_o ( + .CE(com_tlm_u_tlm_rx_data_snk_latch_1st_dword_q2), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_pwr_mgmt_N_10635_i_5257), + .Q(com_tlm_u_tlm_rx_data_snk_cur_pm_msg_detect), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_rx_data_snk_pwr_mgmt_act_pwr_mgmt_q1 ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_pwr_mgmt_act_pwr_mgmt_q1c_5264), + .Q(com_tlm_u_tlm_rx_data_snk_pwr_mgmt_act_pwr_mgmt_q1_5267), + .R(plm_link_up_i) + ); + defparam com_tlm_u_tlm_rx_data_snk_pwr_mgmt_cur_pm_turn_off_6_0_a2_0_a2_0_a2_1_0_0.INIT = 4'h1; + LUT2_L com_tlm_u_tlm_rx_data_snk_pwr_mgmt_cur_pm_turn_off_6_0_a2_0_a2_0_a2_1_0_0 ( + .I0(com_tlm_u_tlm_rx_data_snk_cur_msgcode[1]), + .I1(com_tlm_u_tlm_rx_data_snk_cur_msgcode[5]), + .LO(com_tlm_u_tlm_rx_data_snk_pwr_mgmt_cur_pm_turn_off_6_0_a2_0_a2_0_a2_1_0_0_5256) + ); + defparam com_tlm_u_tlm_rx_data_snk_pwr_mgmt_cur_pm_turn_off_6_0_a2_0_a2_0_a2_1.INIT = 4'h1; + LUT2 com_tlm_u_tlm_rx_data_snk_pwr_mgmt_cur_pm_turn_off_6_0_a2_0_a2_0_a2_1 ( + .I0(com_tlm_u_tlm_rx_data_snk_cur_msgcode[2]), + .I1(com_tlm_u_tlm_rx_data_snk_cur_msgcode[6]), + .O(com_tlm_u_tlm_rx_data_snk_pwr_mgmt_cur_pm_turn_off_6_0_a2_0_a2_0_a2_1_5265) + ); + defparam com_tlm_u_tlm_rx_data_snk_pwr_mgmt_act_pwr_mgmt_q1c.INIT = 4'h8; + LUT2 com_tlm_u_tlm_rx_data_snk_pwr_mgmt_act_pwr_mgmt_q1c ( + .I0(com_tlm_u_tlm_rx_data_snk_eof_q_3__5122), + .I1(com_tlm_u_tlm_rx_data_snk_un1_eof_q_2_1_5070), + .O(com_tlm_u_tlm_rx_data_snk_pwr_mgmt_act_pwr_mgmt_q1c_5264) + ); + defparam com_tlm_u_tlm_rx_data_snk_pwr_mgmt_cur_pm_turn_off_6_0_a2_0_a2_0_a2_1_0.INIT = 16'h0800; + LUT4 com_tlm_u_tlm_rx_data_snk_pwr_mgmt_cur_pm_turn_off_6_0_a2_0_a2_0_a2_1_0 ( + .I0(com_tlm_u_tlm_rx_data_snk_cur_fulltype_oh_1_), + .I1(com_tlm_u_tlm_rx_data_snk_cur_msgcode[4]), + .I2(com_tlm_u_tlm_rx_data_snk_cur_msgcode[7]), + .I3(com_tlm_u_tlm_rx_data_snk_pwr_mgmt_cur_pm_turn_off_6_0_a2_0_a2_0_a2_1_0_0_5256), + .O(com_tlm_u_tlm_rx_data_snk_pwr_mgmt_cur_pm_turn_off_6_1_0) + ); + defparam com_tlm_u_tlm_rx_data_snk_pwr_mgmt_cur_pm_set_slot_pwr_6_0_a2_0_a2_0_a2_1.INIT = 8'h10; + LUT3 com_tlm_u_tlm_rx_data_snk_pwr_mgmt_cur_pm_set_slot_pwr_6_0_a2_0_a2_0_a2_1 ( + .I0(com_tlm_u_tlm_rx_data_snk_cur_msgcode[0]), + .I1(com_tlm_u_tlm_rx_data_snk_cur_msgcode[3]), + .I2(com_tlm_u_tlm_rx_data_snk_pwr_mgmt_cur_pm_turn_off_6_1_0), + .O(com_tlm_u_tlm_rx_data_snk_pwr_mgmt_cur_pm_set_slot_pwr_6_1) + ); + defparam com_tlm_u_tlm_rx_data_snk_pwr_mgmt_N_10635_i.INIT = 8'hFE; + LUT3_L com_tlm_u_tlm_rx_data_snk_pwr_mgmt_N_10635_i ( + .I0(com_tlm_u_tlm_rx_data_snk_pwr_mgmt_cur_pm_as_nak_l1_5259), + .I1(com_tlm_u_tlm_rx_data_snk_pwr_mgmt_cur_pm_set_slot_pwr_5261), + .I2(com_tlm_u_tlm_rx_data_snk_pwr_mgmt_cur_pm_turn_off_5263), + .LO(com_tlm_u_tlm_rx_data_snk_pwr_mgmt_N_10635_i_5257) + ); + defparam com_tlm_u_tlm_rx_data_snk_pwr_mgmt_pm_as_nak_l1_o_5.INIT = 4'h8; + LUT2_L com_tlm_u_tlm_rx_data_snk_pwr_mgmt_pm_as_nak_l1_o_5 ( + .I0(com_tlm_u_tlm_rx_data_snk_pwr_mgmt_act_pwr_mgmt_q1c_5264), + .I1(com_tlm_u_tlm_rx_data_snk_pwr_mgmt_cur_pm_as_nak_l1_5259), + .LO(com_tlm_u_tlm_rx_data_snk_pwr_mgmt_pm_as_nak_l1_o_5_5258) + ); + defparam com_tlm_u_tlm_rx_data_snk_pwr_mgmt_pm_set_slot_pwr_o_5.INIT = 4'h8; + LUT2_L com_tlm_u_tlm_rx_data_snk_pwr_mgmt_pm_set_slot_pwr_o_5 ( + .I0(com_tlm_u_tlm_rx_data_snk_pwr_mgmt_act_pwr_mgmt_q1c_5264), + .I1(com_tlm_u_tlm_rx_data_snk_pwr_mgmt_cur_pm_set_slot_pwr_5261), + .LO(com_tlm_u_tlm_rx_data_snk_pwr_mgmt_pm_set_slot_pwr_o_5_5260) + ); + defparam com_tlm_u_tlm_rx_data_snk_pwr_mgmt_pm_turn_off_o_5.INIT = 4'h8; + LUT2_L com_tlm_u_tlm_rx_data_snk_pwr_mgmt_pm_turn_off_o_5 ( + .I0(com_tlm_u_tlm_rx_data_snk_pwr_mgmt_act_pwr_mgmt_q1c_5264), + .I1(com_tlm_u_tlm_rx_data_snk_pwr_mgmt_cur_pm_turn_off_5263), + .LO(com_tlm_u_tlm_rx_data_snk_pwr_mgmt_pm_turn_off_o_5_5262) + ); + defparam com_tlm_u_tlm_rx_data_snk_pwr_mgmt_cur_pm_as_nak_l1_6_0_a2_0_a2_0_a2.INIT = 8'h20; + LUT3_L com_tlm_u_tlm_rx_data_snk_pwr_mgmt_cur_pm_as_nak_l1_6_0_a2_0_a2_0_a2 ( + .I0(com_tlm_u_tlm_rx_data_snk_cur_msgcode[2]), + .I1(com_tlm_u_tlm_rx_data_snk_cur_msgcode[6]), + .I2(com_tlm_u_tlm_rx_data_snk_pwr_mgmt_cur_pm_set_slot_pwr_6_1), + .LO(com_tlm_u_tlm_rx_data_snk_pwr_mgmt_cur_pm_as_nak_l1_6) + ); + defparam com_tlm_u_tlm_rx_data_snk_pwr_mgmt_cur_pm_set_slot_pwr_6_0_a2_0_a2_0_a2.INIT = 8'h40; + LUT3_L com_tlm_u_tlm_rx_data_snk_pwr_mgmt_cur_pm_set_slot_pwr_6_0_a2_0_a2_0_a2 ( + .I0(com_tlm_u_tlm_rx_data_snk_cur_msgcode[2]), + .I1(com_tlm_u_tlm_rx_data_snk_cur_msgcode[6]), + .I2(com_tlm_u_tlm_rx_data_snk_pwr_mgmt_cur_pm_set_slot_pwr_6_1), + .LO(com_tlm_u_tlm_rx_data_snk_pwr_mgmt_cur_pm_set_slot_pwr_6) + ); + defparam com_tlm_u_tlm_rx_data_snk_pwr_mgmt_cur_pm_turn_off_6_0_a2_0_a2_0_a2.INIT = 16'h8000; + LUT4_L com_tlm_u_tlm_rx_data_snk_pwr_mgmt_cur_pm_turn_off_6_0_a2_0_a2_0_a2 ( + .I0(com_tlm_u_tlm_rx_data_snk_cur_msgcode[0]), + .I1(com_tlm_u_tlm_rx_data_snk_cur_msgcode[3]), + .I2(com_tlm_u_tlm_rx_data_snk_pwr_mgmt_cur_pm_turn_off_6_0_a2_0_a2_0_a2_1_5265), + .I3(com_tlm_u_tlm_rx_data_snk_pwr_mgmt_cur_pm_turn_off_6_1_0), + .LO(com_tlm_u_tlm_rx_data_snk_pwr_mgmt_cur_pm_turn_off_6) + ); + defparam com_tlm_u_tlm_rx_data_snk_pwr_mgmt_un1_act_pwr_mgmt_i_1_i.INIT = 8'hEA; + LUT3 com_tlm_u_tlm_rx_data_snk_pwr_mgmt_un1_act_pwr_mgmt_i_1_i ( + .I0(com_tlm_u_tlm_rx_data_snk_pwr_mgmt_act_pwr_mgmt_q1_5267), + .I1(com_tlm_u_tlm_rx_data_snk_un1_eof_q_2_1_5070), + .I2(com_tlm_u_tlm_rx_data_snk_eof_q_3__5122), + .O(com_tlm_u_tlm_rx_data_snk_pwr_mgmt_un1_act_pwr_mgmt_i_1_i_5266) + ); + FDE com_tlm_u_tlm_rx_data_snk_pwr_mgmt_pm_set_slot_pwr_data_o_9_ ( + .CE(com_tlm_u_tlm_rx_data_snk_latch_3rd_dword_q1), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_lnk_rd_6113[41]), + .Q(com_cmmt_rpm_set_slot_pwr_data[9]) + ); + FDE com_tlm_u_tlm_rx_data_snk_pwr_mgmt_pm_set_slot_pwr_data_o_8_ ( + .CE(com_tlm_u_tlm_rx_data_snk_latch_3rd_dword_q1), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_lnk_rd_6113[40]), + .Q(com_cmmt_rpm_set_slot_pwr_data[8]) + ); + FDE com_tlm_u_tlm_rx_data_snk_pwr_mgmt_pm_set_slot_pwr_data_o_7_ ( + .CE(com_tlm_u_tlm_rx_data_snk_latch_3rd_dword_q1), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_lnk_rd_6113[39]), + .Q(com_cmmt_rpm_set_slot_pwr_data[7]) + ); + FDE com_tlm_u_tlm_rx_data_snk_pwr_mgmt_pm_set_slot_pwr_data_o_6_ ( + .CE(com_tlm_u_tlm_rx_data_snk_latch_3rd_dword_q1), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_lnk_rd_6113[38]), + .Q(com_cmmt_rpm_set_slot_pwr_data[6]) + ); + FDE com_tlm_u_tlm_rx_data_snk_pwr_mgmt_pm_set_slot_pwr_data_o_5_ ( + .CE(com_tlm_u_tlm_rx_data_snk_latch_3rd_dword_q1), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_lnk_rd_6113[37]), + .Q(com_cmmt_rpm_set_slot_pwr_data[5]) + ); + FDE com_tlm_u_tlm_rx_data_snk_pwr_mgmt_pm_set_slot_pwr_data_o_4_ ( + .CE(com_tlm_u_tlm_rx_data_snk_latch_3rd_dword_q1), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_lnk_rd_6113[36]), + .Q(com_cmmt_rpm_set_slot_pwr_data[4]) + ); + FDE com_tlm_u_tlm_rx_data_snk_pwr_mgmt_pm_set_slot_pwr_data_o_3_ ( + .CE(com_tlm_u_tlm_rx_data_snk_latch_3rd_dword_q1), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_lnk_rd_6113[35]), + .Q(com_cmmt_rpm_set_slot_pwr_data[3]) + ); + FDE com_tlm_u_tlm_rx_data_snk_pwr_mgmt_pm_set_slot_pwr_data_o_2_ ( + .CE(com_tlm_u_tlm_rx_data_snk_latch_3rd_dword_q1), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_lnk_rd_6113[34]), + .Q(com_cmmt_rpm_set_slot_pwr_data[2]) + ); + FDE com_tlm_u_tlm_rx_data_snk_pwr_mgmt_pm_set_slot_pwr_data_o_1_ ( + .CE(com_tlm_u_tlm_rx_data_snk_latch_3rd_dword_q1), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_lnk_rd_6113[33]), + .Q(com_cmmt_rpm_set_slot_pwr_data[1]) + ); + FDE com_tlm_u_tlm_rx_data_snk_pwr_mgmt_pm_set_slot_pwr_data_o_0_ ( + .CE(com_tlm_u_tlm_rx_data_snk_latch_3rd_dword_q1), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_lnk_rd_6113[32]), + .Q(com_cmmt_rpm_set_slot_pwr_data[0]) + ); + FDR com_tlm_u_tlm_rx_data_snk_bar_hit_check_rmem32_o ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_bar_hit_check_rmem32_o_5), + .Q(com_cmmt_mem32), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_rx_data_snk_bar_hit_check_rmem64_o ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_bar_hit_check_rmem64_o_5), + .Q(com_cmmt_mem64), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_rx_data_snk_bar_hit_check_rio_o ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_bar_hit_check_rio_o_5), + .Q(com_cmmt_rio), + .R(plm_link_up_i) + ); + defparam com_tlm_u_tlm_rx_data_snk_bar_hit_check_raddr_d_i_0_0_o3_63_.INIT = 4'h1; + LUT2 com_tlm_u_tlm_rx_data_snk_bar_hit_check_raddr_d_i_0_0_o3_63_ ( + .I0(com_tlm_u_tlm_rx_data_snk_cur_fulltype_oh_0__5133), + .I1(com_tlm_u_tlm_rx_data_snk_cur_fulltype_oh_7__5129), + .O(com_tlm_u_tlm_rx_data_snk_bar_hit_check_raddr_d_i_0_0_o3[63]) + ); + defparam com_tlm_u_tlm_rx_data_snk_bar_hit_check_rio_o_5_0_a2_0_a2_0_a2.INIT = 4'h8; + LUT2_L com_tlm_u_tlm_rx_data_snk_bar_hit_check_rio_o_5_0_a2_0_a2_0_a2 ( + .I0(com_tlm_u_tlm_rx_data_snk_cur_fulltype_oh_3__5132), + .I1(com_tlm_u_tlm_rx_data_snk_sof_q_1__5135), + .LO(com_tlm_u_tlm_rx_data_snk_bar_hit_check_rio_o_5) + ); + defparam com_tlm_u_tlm_rx_data_snk_bar_hit_check_rmem64_o_5_0_a3_0_a2_0_a2.INIT = 8'h80; + LUT3_L com_tlm_u_tlm_rx_data_snk_bar_hit_check_rmem64_o_5_0_a3_0_a2_0_a2 ( + .I0(com_tlm_u_tlm_rx_data_snk_cur_fulltype_64_5127), + .I1(com_tlm_u_tlm_rx_data_snk_cur_fulltype_mem_5128), + .I2(com_tlm_u_tlm_rx_data_snk_sof_q_1__5135), + .LO(com_tlm_u_tlm_rx_data_snk_bar_hit_check_rmem64_o_5) + ); + defparam com_tlm_u_tlm_rx_data_snk_bar_hit_check_rmem32_o_5_0_a3_0_a2_0_a2.INIT = 8'h40; + LUT3_L com_tlm_u_tlm_rx_data_snk_bar_hit_check_rmem32_o_5_0_a3_0_a2_0_a2 ( + .I0(com_tlm_u_tlm_rx_data_snk_cur_fulltype_64_5127), + .I1(com_tlm_u_tlm_rx_data_snk_cur_fulltype_mem_5128), + .I2(com_tlm_u_tlm_rx_data_snk_sof_q_1__5135), + .LO(com_tlm_u_tlm_rx_data_snk_bar_hit_check_rmem32_o_5) + ); + defparam com_tlm_u_tlm_rx_data_snk_bar_hit_N_87156_i.INIT = 16'hF444; + LUT4_L com_tlm_u_tlm_rx_data_snk_bar_hit_N_87156_i ( + .I0(com_tlm_u_tlm_rx_data_snk_bar_hit_check_raddr_d_i_0_0_o3[63]), + .I1(com_lnk_rd_6113[63]), + .I2(com_tlm_u_tlm_rx_data_snk_cur_fulltype_oh_1_), + .I3(com_tlm_u_tlm_rx_data_snk_cur_req_id[15]), + .LO(com_tlm_u_tlm_rx_data_snk_bar_hit_N_87156_i_5268) + ); + defparam com_tlm_u_tlm_rx_data_snk_bar_hit_N_87157_i.INIT = 16'hF444; + LUT4_L com_tlm_u_tlm_rx_data_snk_bar_hit_N_87157_i ( + .I0(com_tlm_u_tlm_rx_data_snk_bar_hit_check_raddr_d_i_0_0_o3[63]), + .I1(com_lnk_rd_6113[62]), + .I2(com_tlm_u_tlm_rx_data_snk_cur_fulltype_oh_1_), + .I3(com_tlm_u_tlm_rx_data_snk_cur_req_id[14]), + .LO(com_tlm_u_tlm_rx_data_snk_bar_hit_N_87157_i_5269) + ); + defparam com_tlm_u_tlm_rx_data_snk_bar_hit_N_87158_i.INIT = 16'hF444; + LUT4_L com_tlm_u_tlm_rx_data_snk_bar_hit_N_87158_i ( + .I0(com_tlm_u_tlm_rx_data_snk_bar_hit_check_raddr_d_i_0_0_o3[63]), + .I1(com_lnk_rd_6113[61]), + .I2(com_tlm_u_tlm_rx_data_snk_cur_fulltype_oh_1_), + .I3(com_tlm_u_tlm_rx_data_snk_cur_req_id[13]), + .LO(com_tlm_u_tlm_rx_data_snk_bar_hit_N_87158_i_5270) + ); + defparam com_tlm_u_tlm_rx_data_snk_bar_hit_N_87172_i.INIT = 16'hF444; + LUT4_L com_tlm_u_tlm_rx_data_snk_bar_hit_N_87172_i ( + .I0(com_tlm_u_tlm_rx_data_snk_bar_hit_check_raddr_d_i_0_0_o3[63]), + .I1(com_lnk_rd_6113[60]), + .I2(com_tlm_u_tlm_rx_data_snk_cur_fulltype_oh_1_), + .I3(com_tlm_u_tlm_rx_data_snk_cur_req_id[12]), + .LO(com_tlm_u_tlm_rx_data_snk_bar_hit_N_87172_i_5271) + ); + defparam com_tlm_u_tlm_rx_data_snk_bar_hit_N_87173_i.INIT = 16'hF444; + LUT4_L com_tlm_u_tlm_rx_data_snk_bar_hit_N_87173_i ( + .I0(com_tlm_u_tlm_rx_data_snk_bar_hit_check_raddr_d_i_0_0_o3[63]), + .I1(com_lnk_rd_6113[59]), + .I2(com_tlm_u_tlm_rx_data_snk_cur_fulltype_oh_1_), + .I3(com_tlm_u_tlm_rx_data_snk_cur_req_id[11]), + .LO(com_tlm_u_tlm_rx_data_snk_bar_hit_N_87173_i_5272) + ); + defparam com_tlm_u_tlm_rx_data_snk_bar_hit_N_87159_i.INIT = 16'hF444; + LUT4_L com_tlm_u_tlm_rx_data_snk_bar_hit_N_87159_i ( + .I0(com_tlm_u_tlm_rx_data_snk_bar_hit_check_raddr_d_i_0_0_o3[63]), + .I1(com_lnk_rd_6113[58]), + .I2(com_tlm_u_tlm_rx_data_snk_cur_fulltype_oh_1_), + .I3(com_tlm_u_tlm_rx_data_snk_cur_req_id[10]), + .LO(com_tlm_u_tlm_rx_data_snk_bar_hit_N_87159_i_5273) + ); + defparam com_tlm_u_tlm_rx_data_snk_bar_hit_N_87160_i.INIT = 16'hF444; + LUT4_L com_tlm_u_tlm_rx_data_snk_bar_hit_N_87160_i ( + .I0(com_tlm_u_tlm_rx_data_snk_bar_hit_check_raddr_d_i_0_0_o3[63]), + .I1(com_lnk_rd_6113[57]), + .I2(com_tlm_u_tlm_rx_data_snk_cur_fulltype_oh_1_), + .I3(com_tlm_u_tlm_rx_data_snk_cur_req_id[9]), + .LO(com_tlm_u_tlm_rx_data_snk_bar_hit_N_87160_i_5274) + ); + defparam com_tlm_u_tlm_rx_data_snk_bar_hit_N_87161_i.INIT = 16'hF444; + LUT4_L com_tlm_u_tlm_rx_data_snk_bar_hit_N_87161_i ( + .I0(com_tlm_u_tlm_rx_data_snk_bar_hit_check_raddr_d_i_0_0_o3[63]), + .I1(com_lnk_rd_6113[56]), + .I2(com_tlm_u_tlm_rx_data_snk_cur_fulltype_oh_1_), + .I3(com_tlm_u_tlm_rx_data_snk_cur_req_id[8]), + .LO(com_tlm_u_tlm_rx_data_snk_bar_hit_N_87161_i_5275) + ); + defparam com_tlm_u_tlm_rx_data_snk_bar_hit_N_87162_i.INIT = 16'hF444; + LUT4_L com_tlm_u_tlm_rx_data_snk_bar_hit_N_87162_i ( + .I0(com_tlm_u_tlm_rx_data_snk_bar_hit_check_raddr_d_i_0_0_o3[63]), + .I1(com_lnk_rd_6113[55]), + .I2(com_tlm_u_tlm_rx_data_snk_cur_fulltype_oh_1_), + .I3(com_tlm_u_tlm_rx_data_snk_cur_req_id[7]), + .LO(com_tlm_u_tlm_rx_data_snk_bar_hit_N_87162_i_5276) + ); + defparam com_tlm_u_tlm_rx_data_snk_bar_hit_N_87163_i.INIT = 16'hF444; + LUT4_L com_tlm_u_tlm_rx_data_snk_bar_hit_N_87163_i ( + .I0(com_tlm_u_tlm_rx_data_snk_bar_hit_check_raddr_d_i_0_0_o3[63]), + .I1(com_lnk_rd_6113[54]), + .I2(com_tlm_u_tlm_rx_data_snk_cur_fulltype_oh_1_), + .I3(com_tlm_u_tlm_rx_data_snk_cur_req_id[6]), + .LO(com_tlm_u_tlm_rx_data_snk_bar_hit_N_87163_i_5277) + ); + defparam com_tlm_u_tlm_rx_data_snk_bar_hit_N_87164_i.INIT = 16'hF444; + LUT4_L com_tlm_u_tlm_rx_data_snk_bar_hit_N_87164_i ( + .I0(com_tlm_u_tlm_rx_data_snk_bar_hit_check_raddr_d_i_0_0_o3[63]), + .I1(com_lnk_rd_6113[53]), + .I2(com_tlm_u_tlm_rx_data_snk_cur_fulltype_oh_1_), + .I3(com_tlm_u_tlm_rx_data_snk_cur_req_id[5]), + .LO(com_tlm_u_tlm_rx_data_snk_bar_hit_N_87164_i_5278) + ); + defparam com_tlm_u_tlm_rx_data_snk_bar_hit_N_87165_i.INIT = 16'hF444; + LUT4_L com_tlm_u_tlm_rx_data_snk_bar_hit_N_87165_i ( + .I0(com_tlm_u_tlm_rx_data_snk_bar_hit_check_raddr_d_i_0_0_o3[63]), + .I1(com_lnk_rd_6113[52]), + .I2(com_tlm_u_tlm_rx_data_snk_cur_fulltype_oh_1_), + .I3(com_tlm_u_tlm_rx_data_snk_cur_req_id[4]), + .LO(com_tlm_u_tlm_rx_data_snk_bar_hit_N_87165_i_5279) + ); + defparam com_tlm_u_tlm_rx_data_snk_bar_hit_N_87166_i.INIT = 16'hF444; + LUT4_L com_tlm_u_tlm_rx_data_snk_bar_hit_N_87166_i ( + .I0(com_tlm_u_tlm_rx_data_snk_bar_hit_check_raddr_d_i_0_0_o3[63]), + .I1(com_lnk_rd_6113[51]), + .I2(com_tlm_u_tlm_rx_data_snk_cur_fulltype_oh_1_), + .I3(com_tlm_u_tlm_rx_data_snk_cur_req_id[3]), + .LO(com_tlm_u_tlm_rx_data_snk_bar_hit_N_87166_i_5280) + ); + defparam com_tlm_u_tlm_rx_data_snk_bar_hit_N_87167_i.INIT = 16'hF444; + LUT4_L com_tlm_u_tlm_rx_data_snk_bar_hit_N_87167_i ( + .I0(com_tlm_u_tlm_rx_data_snk_bar_hit_check_raddr_d_i_0_0_o3[63]), + .I1(com_lnk_rd_6113[50]), + .I2(com_tlm_u_tlm_rx_data_snk_cur_fulltype_oh_1_), + .I3(com_tlm_u_tlm_rx_data_snk_cur_req_id[2]), + .LO(com_tlm_u_tlm_rx_data_snk_bar_hit_N_87167_i_5281) + ); + defparam com_tlm_u_tlm_rx_data_snk_bar_hit_N_87168_i.INIT = 16'hF444; + LUT4_L com_tlm_u_tlm_rx_data_snk_bar_hit_N_87168_i ( + .I0(com_tlm_u_tlm_rx_data_snk_bar_hit_check_raddr_d_i_0_0_o3[63]), + .I1(com_lnk_rd_6113[49]), + .I2(com_tlm_u_tlm_rx_data_snk_cur_fulltype_oh_1_), + .I3(com_tlm_u_tlm_rx_data_snk_cur_req_id[1]), + .LO(com_tlm_u_tlm_rx_data_snk_bar_hit_N_87168_i_5282) + ); + defparam com_tlm_u_tlm_rx_data_snk_bar_hit_N_87169_i.INIT = 16'hF444; + LUT4_L com_tlm_u_tlm_rx_data_snk_bar_hit_N_87169_i ( + .I0(com_tlm_u_tlm_rx_data_snk_bar_hit_check_raddr_d_i_0_0_o3[63]), + .I1(com_lnk_rd_6113[48]), + .I2(com_tlm_u_tlm_rx_data_snk_cur_fulltype_oh_1_), + .I3(com_tlm_u_tlm_rx_data_snk_cur_req_id[0]), + .LO(com_tlm_u_tlm_rx_data_snk_bar_hit_N_87169_i_5283) + ); + defparam com_tlm_u_tlm_rx_data_snk_bar_hit_un18_check_raddr_d_0_a2_0_a2_0_a2_0_a2_47_.INIT = 4'h8; + LUT2_L com_tlm_u_tlm_rx_data_snk_bar_hit_un18_check_raddr_d_0_a2_0_a2_0_a2_0_a2_47_ ( + .I0(com_lnk_rd_6113[47]), + .I1(com_tlm_u_tlm_rx_data_snk_cur_fulltype_oh_7__5129), + .LO(com_tlm_u_tlm_rx_data_snk_bar_hit_un18_check_raddr_d_0_a2_0_a2_0_a2_0_a2[47]) + ); + defparam com_tlm_u_tlm_rx_data_snk_bar_hit_un18_check_raddr_d_0_a2_0_a2_0_a2_0_a2_46_.INIT = 4'h8; + LUT2_L com_tlm_u_tlm_rx_data_snk_bar_hit_un18_check_raddr_d_0_a2_0_a2_0_a2_0_a2_46_ ( + .I0(com_lnk_rd_6113[46]), + .I1(com_tlm_u_tlm_rx_data_snk_cur_fulltype_oh_7__5129), + .LO(com_tlm_u_tlm_rx_data_snk_bar_hit_un18_check_raddr_d_0_a2_0_a2_0_a2_0_a2[46]) + ); + defparam com_tlm_u_tlm_rx_data_snk_bar_hit_un18_check_raddr_d_0_a2_0_a2_0_a2_0_a2_45_.INIT = 4'h8; + LUT2_L com_tlm_u_tlm_rx_data_snk_bar_hit_un18_check_raddr_d_0_a2_0_a2_0_a2_0_a2_45_ ( + .I0(com_lnk_rd_6113[45]), + .I1(com_tlm_u_tlm_rx_data_snk_cur_fulltype_oh_7__5129), + .LO(com_tlm_u_tlm_rx_data_snk_bar_hit_un18_check_raddr_d_0_a2_0_a2_0_a2_0_a2[45]) + ); + defparam com_tlm_u_tlm_rx_data_snk_bar_hit_un18_check_raddr_d_0_a2_0_a2_0_a2_0_a2_44_.INIT = 4'h8; + LUT2_L com_tlm_u_tlm_rx_data_snk_bar_hit_un18_check_raddr_d_0_a2_0_a2_0_a2_0_a2_44_ ( + .I0(com_lnk_rd_6113[44]), + .I1(com_tlm_u_tlm_rx_data_snk_cur_fulltype_oh_7__5129), + .LO(com_tlm_u_tlm_rx_data_snk_bar_hit_un18_check_raddr_d_0_a2_0_a2_0_a2_0_a2[44]) + ); + defparam com_tlm_u_tlm_rx_data_snk_bar_hit_un18_check_raddr_d_0_a2_0_a2_0_a2_0_a2_43_.INIT = 4'h8; + LUT2_L com_tlm_u_tlm_rx_data_snk_bar_hit_un18_check_raddr_d_0_a2_0_a2_0_a2_0_a2_43_ ( + .I0(com_lnk_rd_6113[43]), + .I1(com_tlm_u_tlm_rx_data_snk_cur_fulltype_oh_7__5129), + .LO(com_tlm_u_tlm_rx_data_snk_bar_hit_un18_check_raddr_d_0_a2_0_a2_0_a2_0_a2[43]) + ); + defparam com_tlm_u_tlm_rx_data_snk_bar_hit_un18_check_raddr_d_0_a2_0_a2_0_a2_0_a2_42_.INIT = 4'h8; + LUT2_L com_tlm_u_tlm_rx_data_snk_bar_hit_un18_check_raddr_d_0_a2_0_a2_0_a2_0_a2_42_ ( + .I0(com_lnk_rd_6113[42]), + .I1(com_tlm_u_tlm_rx_data_snk_cur_fulltype_oh_7__5129), + .LO(com_tlm_u_tlm_rx_data_snk_bar_hit_un18_check_raddr_d_0_a2_0_a2_0_a2_0_a2[42]) + ); + defparam com_tlm_u_tlm_rx_data_snk_bar_hit_un18_check_raddr_d_0_a2_0_a2_0_a2_0_a2_41_.INIT = 4'h8; + LUT2_L com_tlm_u_tlm_rx_data_snk_bar_hit_un18_check_raddr_d_0_a2_0_a2_0_a2_0_a2_41_ ( + .I0(com_lnk_rd_6113[41]), + .I1(com_tlm_u_tlm_rx_data_snk_cur_fulltype_oh_7__5129), + .LO(com_tlm_u_tlm_rx_data_snk_bar_hit_un18_check_raddr_d_0_a2_0_a2_0_a2_0_a2[41]) + ); + defparam com_tlm_u_tlm_rx_data_snk_bar_hit_un18_check_raddr_d_0_a2_0_a2_0_a2_0_a2_40_.INIT = 4'h8; + LUT2_L com_tlm_u_tlm_rx_data_snk_bar_hit_un18_check_raddr_d_0_a2_0_a2_0_a2_0_a2_40_ ( + .I0(com_lnk_rd_6113[40]), + .I1(com_tlm_u_tlm_rx_data_snk_cur_fulltype_oh_7__5129), + .LO(com_tlm_u_tlm_rx_data_snk_bar_hit_un18_check_raddr_d_0_a2_0_a2_0_a2_0_a2[40]) + ); + defparam com_tlm_u_tlm_rx_data_snk_bar_hit_un18_check_raddr_d_0_a2_0_a2_0_a2_0_a2_39_.INIT = 4'h8; + LUT2_L com_tlm_u_tlm_rx_data_snk_bar_hit_un18_check_raddr_d_0_a2_0_a2_0_a2_0_a2_39_ ( + .I0(com_lnk_rd_6113[39]), + .I1(com_tlm_u_tlm_rx_data_snk_cur_fulltype_oh_7__5129), + .LO(com_tlm_u_tlm_rx_data_snk_bar_hit_un18_check_raddr_d_0_a2_0_a2_0_a2_0_a2[39]) + ); + defparam com_tlm_u_tlm_rx_data_snk_bar_hit_un18_check_raddr_d_0_a2_0_a2_0_a2_0_a2_38_.INIT = 4'h8; + LUT2_L com_tlm_u_tlm_rx_data_snk_bar_hit_un18_check_raddr_d_0_a2_0_a2_0_a2_0_a2_38_ ( + .I0(com_lnk_rd_6113[38]), + .I1(com_tlm_u_tlm_rx_data_snk_cur_fulltype_oh_7__5129), + .LO(com_tlm_u_tlm_rx_data_snk_bar_hit_un18_check_raddr_d_0_a2_0_a2_0_a2_0_a2[38]) + ); + defparam com_tlm_u_tlm_rx_data_snk_bar_hit_un18_check_raddr_d_0_a2_0_a2_0_a2_0_a2_37_.INIT = 4'h8; + LUT2_L com_tlm_u_tlm_rx_data_snk_bar_hit_un18_check_raddr_d_0_a2_0_a2_0_a2_0_a2_37_ ( + .I0(com_lnk_rd_6113[37]), + .I1(com_tlm_u_tlm_rx_data_snk_cur_fulltype_oh_7__5129), + .LO(com_tlm_u_tlm_rx_data_snk_bar_hit_un18_check_raddr_d_0_a2_0_a2_0_a2_0_a2[37]) + ); + defparam com_tlm_u_tlm_rx_data_snk_bar_hit_un18_check_raddr_d_0_a2_0_a2_0_a2_0_a2_36_.INIT = 4'h8; + LUT2_L com_tlm_u_tlm_rx_data_snk_bar_hit_un18_check_raddr_d_0_a2_0_a2_0_a2_0_a2_36_ ( + .I0(com_lnk_rd_6113[36]), + .I1(com_tlm_u_tlm_rx_data_snk_cur_fulltype_oh_7__5129), + .LO(com_tlm_u_tlm_rx_data_snk_bar_hit_un18_check_raddr_d_0_a2_0_a2_0_a2_0_a2[36]) + ); + defparam com_tlm_u_tlm_rx_data_snk_bar_hit_un18_check_raddr_d_0_a2_0_a2_0_a2_0_a2_35_.INIT = 4'h8; + LUT2_L com_tlm_u_tlm_rx_data_snk_bar_hit_un18_check_raddr_d_0_a2_0_a2_0_a2_0_a2_35_ ( + .I0(com_lnk_rd_6113[35]), + .I1(com_tlm_u_tlm_rx_data_snk_cur_fulltype_oh_7__5129), + .LO(com_tlm_u_tlm_rx_data_snk_bar_hit_un18_check_raddr_d_0_a2_0_a2_0_a2_0_a2[35]) + ); + defparam com_tlm_u_tlm_rx_data_snk_bar_hit_un18_check_raddr_d_0_a2_0_a2_0_a2_0_a2_34_.INIT = 4'h8; + LUT2_L com_tlm_u_tlm_rx_data_snk_bar_hit_un18_check_raddr_d_0_a2_0_a2_0_a2_0_a2_34_ ( + .I0(com_lnk_rd_6113[34]), + .I1(com_tlm_u_tlm_rx_data_snk_cur_fulltype_oh_7__5129), + .LO(com_tlm_u_tlm_rx_data_snk_bar_hit_un18_check_raddr_d_0_a2_0_a2_0_a2_0_a2[34]) + ); + defparam com_tlm_u_tlm_rx_data_snk_bar_hit_un18_check_raddr_d_0_a2_0_a2_0_a2_0_a2_33_.INIT = 4'h8; + LUT2_L com_tlm_u_tlm_rx_data_snk_bar_hit_un18_check_raddr_d_0_a2_0_a2_0_a2_0_a2_33_ ( + .I0(com_lnk_rd_6113[33]), + .I1(com_tlm_u_tlm_rx_data_snk_cur_fulltype_oh_7__5129), + .LO(com_tlm_u_tlm_rx_data_snk_bar_hit_un18_check_raddr_d_0_a2_0_a2_0_a2_0_a2[33]) + ); + defparam com_tlm_u_tlm_rx_data_snk_bar_hit_un18_check_raddr_d_0_a2_0_a2_0_a2_0_a2_32_.INIT = 4'h8; + LUT2_L com_tlm_u_tlm_rx_data_snk_bar_hit_un18_check_raddr_d_0_a2_0_a2_0_a2_0_a2_32_ ( + .I0(com_lnk_rd_6113[32]), + .I1(com_tlm_u_tlm_rx_data_snk_cur_fulltype_oh_7__5129), + .LO(com_tlm_u_tlm_rx_data_snk_bar_hit_un18_check_raddr_d_0_a2_0_a2_0_a2_0_a2[32]) + ); + defparam com_tlm_u_tlm_rx_data_snk_bar_hit_un18_check_raddr_d_0_a2_0_a2_0_a2_0_a2_31_.INIT = 4'h8; + LUT2_L com_tlm_u_tlm_rx_data_snk_bar_hit_un18_check_raddr_d_0_a2_0_a2_0_a2_0_a2_31_ ( + .I0(com_lnk_rd_6113[31]), + .I1(com_tlm_u_tlm_rx_data_snk_cur_fulltype_oh_7__5129), + .LO(com_tlm_u_tlm_rx_data_snk_bar_hit_un18_check_raddr_d_0_a2_0_a2_0_a2_0_a2[31]) + ); + defparam com_tlm_u_tlm_rx_data_snk_bar_hit_un18_check_raddr_d_0_a2_0_a2_0_a2_0_a2_30_.INIT = 4'h8; + LUT2_L com_tlm_u_tlm_rx_data_snk_bar_hit_un18_check_raddr_d_0_a2_0_a2_0_a2_0_a2_30_ ( + .I0(com_lnk_rd_6113[30]), + .I1(com_tlm_u_tlm_rx_data_snk_cur_fulltype_oh_7__5129), + .LO(com_tlm_u_tlm_rx_data_snk_bar_hit_un18_check_raddr_d_0_a2_0_a2_0_a2_0_a2[30]) + ); + defparam com_tlm_u_tlm_rx_data_snk_bar_hit_un18_check_raddr_d_0_a2_0_a2_0_a2_0_a2_29_.INIT = 4'h8; + LUT2_L com_tlm_u_tlm_rx_data_snk_bar_hit_un18_check_raddr_d_0_a2_0_a2_0_a2_0_a2_29_ ( + .I0(com_lnk_rd_6113[29]), + .I1(com_tlm_u_tlm_rx_data_snk_cur_fulltype_oh_7__5129), + .LO(com_tlm_u_tlm_rx_data_snk_bar_hit_un18_check_raddr_d_0_a2_0_a2_0_a2_0_a2[29]) + ); + defparam com_tlm_u_tlm_rx_data_snk_bar_hit_un18_check_raddr_d_0_a2_0_a2_0_a2_0_a2_28_.INIT = 4'h8; + LUT2_L com_tlm_u_tlm_rx_data_snk_bar_hit_un18_check_raddr_d_0_a2_0_a2_0_a2_0_a2_28_ ( + .I0(com_lnk_rd_6113[28]), + .I1(com_tlm_u_tlm_rx_data_snk_cur_fulltype_oh_7__5129), + .LO(com_tlm_u_tlm_rx_data_snk_bar_hit_un18_check_raddr_d_0_a2_0_a2_0_a2_0_a2[28]) + ); + defparam com_tlm_u_tlm_rx_data_snk_bar_hit_un18_check_raddr_d_0_a2_0_a2_0_a2_0_a2_27_.INIT = 4'h8; + LUT2_L com_tlm_u_tlm_rx_data_snk_bar_hit_un18_check_raddr_d_0_a2_0_a2_0_a2_0_a2_27_ ( + .I0(com_lnk_rd_6113[27]), + .I1(com_tlm_u_tlm_rx_data_snk_cur_fulltype_oh_7__5129), + .LO(com_tlm_u_tlm_rx_data_snk_bar_hit_un18_check_raddr_d_0_a2_0_a2_0_a2_0_a2[27]) + ); + defparam com_tlm_u_tlm_rx_data_snk_bar_hit_un18_check_raddr_d_0_a2_0_a2_0_a2_0_a2_26_.INIT = 4'h8; + LUT2_L com_tlm_u_tlm_rx_data_snk_bar_hit_un18_check_raddr_d_0_a2_0_a2_0_a2_0_a2_26_ ( + .I0(com_lnk_rd_6113[26]), + .I1(com_tlm_u_tlm_rx_data_snk_cur_fulltype_oh_7__5129), + .LO(com_tlm_u_tlm_rx_data_snk_bar_hit_un18_check_raddr_d_0_a2_0_a2_0_a2_0_a2[26]) + ); + defparam com_tlm_u_tlm_rx_data_snk_bar_hit_un18_check_raddr_d_0_a2_0_a2_0_a2_0_a2_25_.INIT = 4'h8; + LUT2_L com_tlm_u_tlm_rx_data_snk_bar_hit_un18_check_raddr_d_0_a2_0_a2_0_a2_0_a2_25_ ( + .I0(com_lnk_rd_6113[25]), + .I1(com_tlm_u_tlm_rx_data_snk_cur_fulltype_oh_7__5129), + .LO(com_tlm_u_tlm_rx_data_snk_bar_hit_un18_check_raddr_d_0_a2_0_a2_0_a2_0_a2[25]) + ); + defparam com_tlm_u_tlm_rx_data_snk_bar_hit_un18_check_raddr_d_0_a2_0_a2_0_a2_0_a2_24_.INIT = 4'h8; + LUT2_L com_tlm_u_tlm_rx_data_snk_bar_hit_un18_check_raddr_d_0_a2_0_a2_0_a2_0_a2_24_ ( + .I0(com_lnk_rd_6113[24]), + .I1(com_tlm_u_tlm_rx_data_snk_cur_fulltype_oh_7__5129), + .LO(com_tlm_u_tlm_rx_data_snk_bar_hit_un18_check_raddr_d_0_a2_0_a2_0_a2_0_a2[24]) + ); + defparam com_tlm_u_tlm_rx_data_snk_bar_hit_un18_check_raddr_d_0_a2_0_a2_0_a2_0_a2_23_.INIT = 4'h8; + LUT2_L com_tlm_u_tlm_rx_data_snk_bar_hit_un18_check_raddr_d_0_a2_0_a2_0_a2_0_a2_23_ ( + .I0(com_lnk_rd_6113[23]), + .I1(com_tlm_u_tlm_rx_data_snk_cur_fulltype_oh_7__5129), + .LO(com_tlm_u_tlm_rx_data_snk_bar_hit_un18_check_raddr_d_0_a2_0_a2_0_a2_0_a2[23]) + ); + defparam com_tlm_u_tlm_rx_data_snk_bar_hit_un18_check_raddr_d_0_a2_0_a2_0_a2_0_a2_22_.INIT = 4'h8; + LUT2_L com_tlm_u_tlm_rx_data_snk_bar_hit_un18_check_raddr_d_0_a2_0_a2_0_a2_0_a2_22_ ( + .I0(com_lnk_rd_6113[22]), + .I1(com_tlm_u_tlm_rx_data_snk_cur_fulltype_oh_7__5129), + .LO(com_tlm_u_tlm_rx_data_snk_bar_hit_un18_check_raddr_d_0_a2_0_a2_0_a2_0_a2[22]) + ); + defparam com_tlm_u_tlm_rx_data_snk_bar_hit_un18_check_raddr_d_0_a2_0_a2_0_a2_0_a2_21_.INIT = 4'h8; + LUT2_L com_tlm_u_tlm_rx_data_snk_bar_hit_un18_check_raddr_d_0_a2_0_a2_0_a2_0_a2_21_ ( + .I0(com_lnk_rd_6113[21]), + .I1(com_tlm_u_tlm_rx_data_snk_cur_fulltype_oh_7__5129), + .LO(com_tlm_u_tlm_rx_data_snk_bar_hit_un18_check_raddr_d_0_a2_0_a2_0_a2_0_a2[21]) + ); + defparam com_tlm_u_tlm_rx_data_snk_bar_hit_un18_check_raddr_d_0_a2_0_a2_0_a2_0_a2_20_.INIT = 4'h8; + LUT2_L com_tlm_u_tlm_rx_data_snk_bar_hit_un18_check_raddr_d_0_a2_0_a2_0_a2_0_a2_20_ ( + .I0(com_lnk_rd_6113[20]), + .I1(com_tlm_u_tlm_rx_data_snk_cur_fulltype_oh_7__5129), + .LO(com_tlm_u_tlm_rx_data_snk_bar_hit_un18_check_raddr_d_0_a2_0_a2_0_a2_0_a2[20]) + ); + defparam com_tlm_u_tlm_rx_data_snk_bar_hit_un18_check_raddr_d_0_a2_0_a2_0_a2_0_a2_19_.INIT = 4'h8; + LUT2_L com_tlm_u_tlm_rx_data_snk_bar_hit_un18_check_raddr_d_0_a2_0_a2_0_a2_0_a2_19_ ( + .I0(com_lnk_rd_6113[19]), + .I1(com_tlm_u_tlm_rx_data_snk_cur_fulltype_oh_7__5129), + .LO(com_tlm_u_tlm_rx_data_snk_bar_hit_un18_check_raddr_d_0_a2_0_a2_0_a2_0_a2[19]) + ); + defparam com_tlm_u_tlm_rx_data_snk_bar_hit_un18_check_raddr_d_0_a2_0_a2_0_a2_0_a2_18_.INIT = 4'h8; + LUT2_L com_tlm_u_tlm_rx_data_snk_bar_hit_un18_check_raddr_d_0_a2_0_a2_0_a2_0_a2_18_ ( + .I0(com_lnk_rd_6113[18]), + .I1(com_tlm_u_tlm_rx_data_snk_cur_fulltype_oh_7__5129), + .LO(com_tlm_u_tlm_rx_data_snk_bar_hit_un18_check_raddr_d_0_a2_0_a2_0_a2_0_a2[18]) + ); + defparam com_tlm_u_tlm_rx_data_snk_bar_hit_un18_check_raddr_d_0_a2_0_a2_0_a2_0_a2_17_.INIT = 4'h8; + LUT2_L com_tlm_u_tlm_rx_data_snk_bar_hit_un18_check_raddr_d_0_a2_0_a2_0_a2_0_a2_17_ ( + .I0(com_lnk_rd_6113[17]), + .I1(com_tlm_u_tlm_rx_data_snk_cur_fulltype_oh_7__5129), + .LO(com_tlm_u_tlm_rx_data_snk_bar_hit_un18_check_raddr_d_0_a2_0_a2_0_a2_0_a2[17]) + ); + defparam com_tlm_u_tlm_rx_data_snk_bar_hit_un18_check_raddr_d_0_a2_0_a2_0_a2_0_a2_16_.INIT = 4'h8; + LUT2_L com_tlm_u_tlm_rx_data_snk_bar_hit_un18_check_raddr_d_0_a2_0_a2_0_a2_0_a2_16_ ( + .I0(com_lnk_rd_6113[16]), + .I1(com_tlm_u_tlm_rx_data_snk_cur_fulltype_oh_7__5129), + .LO(com_tlm_u_tlm_rx_data_snk_bar_hit_un18_check_raddr_d_0_a2_0_a2_0_a2_0_a2[16]) + ); + defparam com_tlm_u_tlm_rx_data_snk_bar_hit_un18_check_raddr_d_0_a2_0_a2_0_a2_0_a2_15_.INIT = 4'h8; + LUT2_L com_tlm_u_tlm_rx_data_snk_bar_hit_un18_check_raddr_d_0_a2_0_a2_0_a2_0_a2_15_ ( + .I0(com_lnk_rd_6113[15]), + .I1(com_tlm_u_tlm_rx_data_snk_cur_fulltype_oh_7__5129), + .LO(com_tlm_u_tlm_rx_data_snk_bar_hit_un18_check_raddr_d_0_a2_0_a2_0_a2_0_a2[15]) + ); + defparam com_tlm_u_tlm_rx_data_snk_bar_hit_un18_check_raddr_d_0_a2_0_a2_0_a2_0_a2_14_.INIT = 4'h8; + LUT2_L com_tlm_u_tlm_rx_data_snk_bar_hit_un18_check_raddr_d_0_a2_0_a2_0_a2_0_a2_14_ ( + .I0(com_lnk_rd_6113[14]), + .I1(com_tlm_u_tlm_rx_data_snk_cur_fulltype_oh_7__5129), + .LO(com_tlm_u_tlm_rx_data_snk_bar_hit_un18_check_raddr_d_0_a2_0_a2_0_a2_0_a2[14]) + ); + defparam com_tlm_u_tlm_rx_data_snk_bar_hit_un18_check_raddr_d_0_a2_0_a2_0_a2_0_a2_13_.INIT = 4'h8; + LUT2_L com_tlm_u_tlm_rx_data_snk_bar_hit_un18_check_raddr_d_0_a2_0_a2_0_a2_0_a2_13_ ( + .I0(com_lnk_rd_6113[13]), + .I1(com_tlm_u_tlm_rx_data_snk_cur_fulltype_oh_7__5129), + .LO(com_tlm_u_tlm_rx_data_snk_bar_hit_un18_check_raddr_d_0_a2_0_a2_0_a2_0_a2[13]) + ); + defparam com_tlm_u_tlm_rx_data_snk_bar_hit_un18_check_raddr_d_0_a2_0_a2_0_a2_0_a2_12_.INIT = 4'h8; + LUT2_L com_tlm_u_tlm_rx_data_snk_bar_hit_un18_check_raddr_d_0_a2_0_a2_0_a2_0_a2_12_ ( + .I0(com_lnk_rd_6113[12]), + .I1(com_tlm_u_tlm_rx_data_snk_cur_fulltype_oh_7__5129), + .LO(com_tlm_u_tlm_rx_data_snk_bar_hit_un18_check_raddr_d_0_a2_0_a2_0_a2_0_a2[12]) + ); + defparam com_tlm_u_tlm_rx_data_snk_bar_hit_un18_check_raddr_d_0_a2_0_a2_0_a2_0_a2_11_.INIT = 4'h8; + LUT2_L com_tlm_u_tlm_rx_data_snk_bar_hit_un18_check_raddr_d_0_a2_0_a2_0_a2_0_a2_11_ ( + .I0(com_lnk_rd_6113[11]), + .I1(com_tlm_u_tlm_rx_data_snk_cur_fulltype_oh_7__5129), + .LO(com_tlm_u_tlm_rx_data_snk_bar_hit_un18_check_raddr_d_0_a2_0_a2_0_a2_0_a2[11]) + ); + defparam com_tlm_u_tlm_rx_data_snk_bar_hit_un18_check_raddr_d_0_a2_0_a2_0_a2_0_a2_10_.INIT = 4'h8; + LUT2_L com_tlm_u_tlm_rx_data_snk_bar_hit_un18_check_raddr_d_0_a2_0_a2_0_a2_0_a2_10_ ( + .I0(com_lnk_rd_6113[10]), + .I1(com_tlm_u_tlm_rx_data_snk_cur_fulltype_oh_7__5129), + .LO(com_tlm_u_tlm_rx_data_snk_bar_hit_un18_check_raddr_d_0_a2_0_a2_0_a2_0_a2[10]) + ); + defparam com_tlm_u_tlm_rx_data_snk_bar_hit_un18_check_raddr_d_0_a2_0_a2_0_a2_0_a2_9_.INIT = 4'h8; + LUT2_L com_tlm_u_tlm_rx_data_snk_bar_hit_un18_check_raddr_d_0_a2_0_a2_0_a2_0_a2_9_ ( + .I0(com_lnk_rd_6113[9]), + .I1(com_tlm_u_tlm_rx_data_snk_cur_fulltype_oh_7__5129), + .LO(com_tlm_u_tlm_rx_data_snk_bar_hit_un18_check_raddr_d_0_a2_0_a2_0_a2_0_a2[9]) + ); + defparam com_tlm_u_tlm_rx_data_snk_bar_hit_un18_check_raddr_d_0_a2_0_a2_0_a2_0_a2_8_.INIT = 4'h8; + LUT2_L com_tlm_u_tlm_rx_data_snk_bar_hit_un18_check_raddr_d_0_a2_0_a2_0_a2_0_a2_8_ ( + .I0(com_lnk_rd_6113[8]), + .I1(com_tlm_u_tlm_rx_data_snk_cur_fulltype_oh_7__5129), + .LO(com_tlm_u_tlm_rx_data_snk_bar_hit_un18_check_raddr_d_0_a2_0_a2_0_a2_0_a2[8]) + ); + defparam com_tlm_u_tlm_rx_data_snk_bar_hit_un18_check_raddr_d_0_a2_0_a2_0_a2_0_a2_7_.INIT = 4'h8; + LUT2_L com_tlm_u_tlm_rx_data_snk_bar_hit_un18_check_raddr_d_0_a2_0_a2_0_a2_0_a2_7_ ( + .I0(com_lnk_rd[7]), + .I1(com_tlm_u_tlm_rx_data_snk_cur_fulltype_oh_7__5129), + .LO(com_tlm_u_tlm_rx_data_snk_bar_hit_un18_check_raddr_d_0_a2_0_a2_0_a2_0_a2[7]) + ); + defparam com_tlm_u_tlm_rx_data_snk_bar_hit_un18_check_raddr_d_0_a2_0_a2_0_a2_0_a2_6_.INIT = 4'h8; + LUT2_L com_tlm_u_tlm_rx_data_snk_bar_hit_un18_check_raddr_d_0_a2_0_a2_0_a2_0_a2_6_ ( + .I0(com_lnk_rd[6]), + .I1(com_tlm_u_tlm_rx_data_snk_cur_fulltype_oh_7__5129), + .LO(com_tlm_u_tlm_rx_data_snk_bar_hit_un18_check_raddr_d_0_a2_0_a2_0_a2_0_a2[6]) + ); + defparam com_tlm_u_tlm_rx_data_snk_bar_hit_un18_check_raddr_d_0_a2_0_a2_0_a2_5_.INIT = 4'h8; + LUT2_L com_tlm_u_tlm_rx_data_snk_bar_hit_un18_check_raddr_d_0_a2_0_a2_0_a2_5_ ( + .I0(com_lnk_rd[5]), + .I1(com_tlm_u_tlm_rx_data_snk_cur_fulltype_oh_7__5129), + .LO(com_tlm_u_tlm_rx_data_snk_bar_hit_un18_check_raddr_d_0_a2_0_a2_0_a2[5]) + ); + defparam com_tlm_u_tlm_rx_data_snk_bar_hit_un18_check_raddr_d_0_a2_0_a2_0_a2_4_.INIT = 4'h8; + LUT2_L com_tlm_u_tlm_rx_data_snk_bar_hit_un18_check_raddr_d_0_a2_0_a2_0_a2_4_ ( + .I0(com_lnk_rd[4]), + .I1(com_tlm_u_tlm_rx_data_snk_cur_fulltype_oh_7__5129), + .LO(com_tlm_u_tlm_rx_data_snk_bar_hit_un18_check_raddr_d_0_a2_0_a2_0_a2[4]) + ); + FDE com_tlm_u_tlm_rx_data_snk_bar_hit_check_raddr_o_63_ ( + .CE(com_tlm_u_tlm_rx_data_snk_sof_q_1__5135), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_bar_hit_N_87156_i_5268), + .Q(com_cmmt_raddr[63]) + ); + FDE com_tlm_u_tlm_rx_data_snk_bar_hit_check_raddr_o_62_ ( + .CE(com_tlm_u_tlm_rx_data_snk_sof_q_1__5135), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_bar_hit_N_87157_i_5269), + .Q(com_cmmt_raddr[62]) + ); + FDE com_tlm_u_tlm_rx_data_snk_bar_hit_check_raddr_o_61_ ( + .CE(com_tlm_u_tlm_rx_data_snk_sof_q_1__5135), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_bar_hit_N_87158_i_5270), + .Q(com_cmmt_raddr[61]) + ); + FDE com_tlm_u_tlm_rx_data_snk_bar_hit_check_raddr_o_60_ ( + .CE(com_tlm_u_tlm_rx_data_snk_sof_q_1__5135), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_bar_hit_N_87172_i_5271), + .Q(com_cmmt_raddr[60]) + ); + FDE com_tlm_u_tlm_rx_data_snk_bar_hit_check_raddr_o_59_ ( + .CE(com_tlm_u_tlm_rx_data_snk_sof_q_1__5135), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_bar_hit_N_87173_i_5272), + .Q(com_cmmt_raddr[59]) + ); + FDE com_tlm_u_tlm_rx_data_snk_bar_hit_check_raddr_o_58_ ( + .CE(com_tlm_u_tlm_rx_data_snk_sof_q_1__5135), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_bar_hit_N_87159_i_5273), + .Q(com_cmmt_raddr[58]) + ); + FDE com_tlm_u_tlm_rx_data_snk_bar_hit_check_raddr_o_57_ ( + .CE(com_tlm_u_tlm_rx_data_snk_sof_q_1__5135), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_bar_hit_N_87160_i_5274), + .Q(com_cmmt_raddr[57]) + ); + FDE com_tlm_u_tlm_rx_data_snk_bar_hit_check_raddr_o_56_ ( + .CE(com_tlm_u_tlm_rx_data_snk_sof_q_1__5135), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_bar_hit_N_87161_i_5275), + .Q(com_cmmt_raddr[56]) + ); + FDE com_tlm_u_tlm_rx_data_snk_bar_hit_check_raddr_o_55_ ( + .CE(com_tlm_u_tlm_rx_data_snk_sof_q_1__5135), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_bar_hit_N_87162_i_5276), + .Q(com_cmmt_raddr[55]) + ); + FDE com_tlm_u_tlm_rx_data_snk_bar_hit_check_raddr_o_54_ ( + .CE(com_tlm_u_tlm_rx_data_snk_sof_q_1__5135), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_bar_hit_N_87163_i_5277), + .Q(com_cmmt_raddr[54]) + ); + FDE com_tlm_u_tlm_rx_data_snk_bar_hit_check_raddr_o_53_ ( + .CE(com_tlm_u_tlm_rx_data_snk_sof_q_1__5135), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_bar_hit_N_87164_i_5278), + .Q(com_cmmt_raddr[53]) + ); + FDE com_tlm_u_tlm_rx_data_snk_bar_hit_check_raddr_o_52_ ( + .CE(com_tlm_u_tlm_rx_data_snk_sof_q_1__5135), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_bar_hit_N_87165_i_5279), + .Q(com_cmmt_raddr[52]) + ); + FDE com_tlm_u_tlm_rx_data_snk_bar_hit_check_raddr_o_51_ ( + .CE(com_tlm_u_tlm_rx_data_snk_sof_q_1__5135), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_bar_hit_N_87166_i_5280), + .Q(com_cmmt_raddr[51]) + ); + FDE com_tlm_u_tlm_rx_data_snk_bar_hit_check_raddr_o_50_ ( + .CE(com_tlm_u_tlm_rx_data_snk_sof_q_1__5135), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_bar_hit_N_87167_i_5281), + .Q(com_cmmt_raddr[50]) + ); + FDE com_tlm_u_tlm_rx_data_snk_bar_hit_check_raddr_o_49_ ( + .CE(com_tlm_u_tlm_rx_data_snk_sof_q_1__5135), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_bar_hit_N_87168_i_5282), + .Q(com_cmmt_raddr[49]) + ); + FDE com_tlm_u_tlm_rx_data_snk_bar_hit_check_raddr_o_48_ ( + .CE(com_tlm_u_tlm_rx_data_snk_sof_q_1__5135), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_bar_hit_N_87169_i_5283), + .Q(com_cmmt_raddr[48]) + ); + FDE com_tlm_u_tlm_rx_data_snk_bar_hit_check_raddr_o_47_ ( + .CE(com_tlm_u_tlm_rx_data_snk_sof_q_1__5135), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_bar_hit_un18_check_raddr_d_0_a2_0_a2_0_a2_0_a2[47]), + .Q(com_cmmt_raddr[47]) + ); + FDE com_tlm_u_tlm_rx_data_snk_bar_hit_check_raddr_o_46_ ( + .CE(com_tlm_u_tlm_rx_data_snk_sof_q_1__5135), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_bar_hit_un18_check_raddr_d_0_a2_0_a2_0_a2_0_a2[46]), + .Q(com_cmmt_raddr[46]) + ); + FDE com_tlm_u_tlm_rx_data_snk_bar_hit_check_raddr_o_45_ ( + .CE(com_tlm_u_tlm_rx_data_snk_sof_q_1__5135), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_bar_hit_un18_check_raddr_d_0_a2_0_a2_0_a2_0_a2[45]), + .Q(com_cmmt_raddr[45]) + ); + FDE com_tlm_u_tlm_rx_data_snk_bar_hit_check_raddr_o_44_ ( + .CE(com_tlm_u_tlm_rx_data_snk_sof_q_1__5135), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_bar_hit_un18_check_raddr_d_0_a2_0_a2_0_a2_0_a2[44]), + .Q(com_cmmt_raddr[44]) + ); + FDE com_tlm_u_tlm_rx_data_snk_bar_hit_check_raddr_o_43_ ( + .CE(com_tlm_u_tlm_rx_data_snk_sof_q_1__5135), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_bar_hit_un18_check_raddr_d_0_a2_0_a2_0_a2_0_a2[43]), + .Q(com_cmmt_raddr[43]) + ); + FDE com_tlm_u_tlm_rx_data_snk_bar_hit_check_raddr_o_42_ ( + .CE(com_tlm_u_tlm_rx_data_snk_sof_q_1__5135), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_bar_hit_un18_check_raddr_d_0_a2_0_a2_0_a2_0_a2[42]), + .Q(com_cmmt_raddr[42]) + ); + FDE com_tlm_u_tlm_rx_data_snk_bar_hit_check_raddr_o_41_ ( + .CE(com_tlm_u_tlm_rx_data_snk_sof_q_1__5135), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_bar_hit_un18_check_raddr_d_0_a2_0_a2_0_a2_0_a2[41]), + .Q(com_cmmt_raddr[41]) + ); + FDE com_tlm_u_tlm_rx_data_snk_bar_hit_check_raddr_o_40_ ( + .CE(com_tlm_u_tlm_rx_data_snk_sof_q_1__5135), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_bar_hit_un18_check_raddr_d_0_a2_0_a2_0_a2_0_a2[40]), + .Q(com_cmmt_raddr[40]) + ); + FDE com_tlm_u_tlm_rx_data_snk_bar_hit_check_raddr_o_39_ ( + .CE(com_tlm_u_tlm_rx_data_snk_sof_q_1__5135), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_bar_hit_un18_check_raddr_d_0_a2_0_a2_0_a2_0_a2[39]), + .Q(com_cmmt_raddr[39]) + ); + FDE com_tlm_u_tlm_rx_data_snk_bar_hit_check_raddr_o_38_ ( + .CE(com_tlm_u_tlm_rx_data_snk_sof_q_1__5135), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_bar_hit_un18_check_raddr_d_0_a2_0_a2_0_a2_0_a2[38]), + .Q(com_cmmt_raddr[38]) + ); + FDE com_tlm_u_tlm_rx_data_snk_bar_hit_check_raddr_o_37_ ( + .CE(com_tlm_u_tlm_rx_data_snk_sof_q_1__5135), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_bar_hit_un18_check_raddr_d_0_a2_0_a2_0_a2_0_a2[37]), + .Q(com_cmmt_raddr[37]) + ); + FDE com_tlm_u_tlm_rx_data_snk_bar_hit_check_raddr_o_36_ ( + .CE(com_tlm_u_tlm_rx_data_snk_sof_q_1__5135), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_bar_hit_un18_check_raddr_d_0_a2_0_a2_0_a2_0_a2[36]), + .Q(com_cmmt_raddr[36]) + ); + FDE com_tlm_u_tlm_rx_data_snk_bar_hit_check_raddr_o_35_ ( + .CE(com_tlm_u_tlm_rx_data_snk_sof_q_1__5135), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_bar_hit_un18_check_raddr_d_0_a2_0_a2_0_a2_0_a2[35]), + .Q(com_cmmt_raddr[35]) + ); + FDE com_tlm_u_tlm_rx_data_snk_bar_hit_check_raddr_o_34_ ( + .CE(com_tlm_u_tlm_rx_data_snk_sof_q_1__5135), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_bar_hit_un18_check_raddr_d_0_a2_0_a2_0_a2_0_a2[34]), + .Q(com_cmmt_raddr[34]) + ); + FDE com_tlm_u_tlm_rx_data_snk_bar_hit_check_raddr_o_33_ ( + .CE(com_tlm_u_tlm_rx_data_snk_sof_q_1__5135), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_bar_hit_un18_check_raddr_d_0_a2_0_a2_0_a2_0_a2[33]), + .Q(com_cmmt_raddr[33]) + ); + FDE com_tlm_u_tlm_rx_data_snk_bar_hit_check_raddr_o_32_ ( + .CE(com_tlm_u_tlm_rx_data_snk_sof_q_1__5135), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_bar_hit_un18_check_raddr_d_0_a2_0_a2_0_a2_0_a2[32]), + .Q(com_cmmt_raddr[32]) + ); + FDE com_tlm_u_tlm_rx_data_snk_bar_hit_check_raddr_o_31_ ( + .CE(com_tlm_u_tlm_rx_data_snk_sof_q_1__5135), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_bar_hit_un18_check_raddr_d_0_a2_0_a2_0_a2_0_a2[31]), + .Q(com_cmmt_raddr[31]) + ); + FDE com_tlm_u_tlm_rx_data_snk_bar_hit_check_raddr_o_30_ ( + .CE(com_tlm_u_tlm_rx_data_snk_sof_q_1__5135), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_bar_hit_un18_check_raddr_d_0_a2_0_a2_0_a2_0_a2[30]), + .Q(com_cmmt_raddr[30]) + ); + FDE com_tlm_u_tlm_rx_data_snk_bar_hit_check_raddr_o_29_ ( + .CE(com_tlm_u_tlm_rx_data_snk_sof_q_1__5135), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_bar_hit_un18_check_raddr_d_0_a2_0_a2_0_a2_0_a2[29]), + .Q(com_cmmt_raddr[29]) + ); + FDE com_tlm_u_tlm_rx_data_snk_bar_hit_check_raddr_o_28_ ( + .CE(com_tlm_u_tlm_rx_data_snk_sof_q_1__5135), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_bar_hit_un18_check_raddr_d_0_a2_0_a2_0_a2_0_a2[28]), + .Q(com_cmmt_raddr[28]) + ); + FDE com_tlm_u_tlm_rx_data_snk_bar_hit_check_raddr_o_27_ ( + .CE(com_tlm_u_tlm_rx_data_snk_sof_q_1__5135), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_bar_hit_un18_check_raddr_d_0_a2_0_a2_0_a2_0_a2[27]), + .Q(com_cmmt_raddr[27]) + ); + FDE com_tlm_u_tlm_rx_data_snk_bar_hit_check_raddr_o_26_ ( + .CE(com_tlm_u_tlm_rx_data_snk_sof_q_1__5135), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_bar_hit_un18_check_raddr_d_0_a2_0_a2_0_a2_0_a2[26]), + .Q(com_cmmt_raddr[26]) + ); + FDE com_tlm_u_tlm_rx_data_snk_bar_hit_check_raddr_o_25_ ( + .CE(com_tlm_u_tlm_rx_data_snk_sof_q_1__5135), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_bar_hit_un18_check_raddr_d_0_a2_0_a2_0_a2_0_a2[25]), + .Q(com_cmmt_raddr[25]) + ); + FDE com_tlm_u_tlm_rx_data_snk_bar_hit_check_raddr_o_24_ ( + .CE(com_tlm_u_tlm_rx_data_snk_sof_q_1__5135), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_bar_hit_un18_check_raddr_d_0_a2_0_a2_0_a2_0_a2[24]), + .Q(com_cmmt_raddr[24]) + ); + FDE com_tlm_u_tlm_rx_data_snk_bar_hit_check_raddr_o_23_ ( + .CE(com_tlm_u_tlm_rx_data_snk_sof_q_1__5135), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_bar_hit_un18_check_raddr_d_0_a2_0_a2_0_a2_0_a2[23]), + .Q(com_cmmt_raddr[23]) + ); + FDE com_tlm_u_tlm_rx_data_snk_bar_hit_check_raddr_o_22_ ( + .CE(com_tlm_u_tlm_rx_data_snk_sof_q_1__5135), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_bar_hit_un18_check_raddr_d_0_a2_0_a2_0_a2_0_a2[22]), + .Q(com_cmmt_raddr[22]) + ); + FDE com_tlm_u_tlm_rx_data_snk_bar_hit_check_raddr_o_21_ ( + .CE(com_tlm_u_tlm_rx_data_snk_sof_q_1__5135), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_bar_hit_un18_check_raddr_d_0_a2_0_a2_0_a2_0_a2[21]), + .Q(com_cmmt_raddr[21]) + ); + FDE com_tlm_u_tlm_rx_data_snk_bar_hit_check_raddr_o_20_ ( + .CE(com_tlm_u_tlm_rx_data_snk_sof_q_1__5135), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_bar_hit_un18_check_raddr_d_0_a2_0_a2_0_a2_0_a2[20]), + .Q(com_cmmt_raddr[20]) + ); + FDE com_tlm_u_tlm_rx_data_snk_bar_hit_check_raddr_o_19_ ( + .CE(com_tlm_u_tlm_rx_data_snk_sof_q_1__5135), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_bar_hit_un18_check_raddr_d_0_a2_0_a2_0_a2_0_a2[19]), + .Q(com_cmmt_raddr[19]) + ); + FDE com_tlm_u_tlm_rx_data_snk_bar_hit_check_raddr_o_18_ ( + .CE(com_tlm_u_tlm_rx_data_snk_sof_q_1__5135), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_bar_hit_un18_check_raddr_d_0_a2_0_a2_0_a2_0_a2[18]), + .Q(com_cmmt_raddr[18]) + ); + FDE com_tlm_u_tlm_rx_data_snk_bar_hit_check_raddr_o_17_ ( + .CE(com_tlm_u_tlm_rx_data_snk_sof_q_1__5135), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_bar_hit_un18_check_raddr_d_0_a2_0_a2_0_a2_0_a2[17]), + .Q(com_cmmt_raddr[17]) + ); + FDE com_tlm_u_tlm_rx_data_snk_bar_hit_check_raddr_o_16_ ( + .CE(com_tlm_u_tlm_rx_data_snk_sof_q_1__5135), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_bar_hit_un18_check_raddr_d_0_a2_0_a2_0_a2_0_a2[16]), + .Q(com_cmmt_raddr[16]) + ); + FDE com_tlm_u_tlm_rx_data_snk_bar_hit_check_raddr_o_15_ ( + .CE(com_tlm_u_tlm_rx_data_snk_sof_q_1__5135), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_bar_hit_un18_check_raddr_d_0_a2_0_a2_0_a2_0_a2[15]), + .Q(com_cmmt_raddr[15]) + ); + FDE com_tlm_u_tlm_rx_data_snk_bar_hit_check_raddr_o_14_ ( + .CE(com_tlm_u_tlm_rx_data_snk_sof_q_1__5135), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_bar_hit_un18_check_raddr_d_0_a2_0_a2_0_a2_0_a2[14]), + .Q(com_cmmt_raddr[14]) + ); + FDE com_tlm_u_tlm_rx_data_snk_bar_hit_check_raddr_o_13_ ( + .CE(com_tlm_u_tlm_rx_data_snk_sof_q_1__5135), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_bar_hit_un18_check_raddr_d_0_a2_0_a2_0_a2_0_a2[13]), + .Q(com_cmmt_raddr[13]) + ); + FDE com_tlm_u_tlm_rx_data_snk_bar_hit_check_raddr_o_12_ ( + .CE(com_tlm_u_tlm_rx_data_snk_sof_q_1__5135), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_bar_hit_un18_check_raddr_d_0_a2_0_a2_0_a2_0_a2[12]), + .Q(com_cmmt_raddr[12]) + ); + FDE com_tlm_u_tlm_rx_data_snk_bar_hit_check_raddr_o_11_ ( + .CE(com_tlm_u_tlm_rx_data_snk_sof_q_1__5135), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_bar_hit_un18_check_raddr_d_0_a2_0_a2_0_a2_0_a2[11]), + .Q(com_cmmt_raddr[11]) + ); + FDE com_tlm_u_tlm_rx_data_snk_bar_hit_check_raddr_o_10_ ( + .CE(com_tlm_u_tlm_rx_data_snk_sof_q_1__5135), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_bar_hit_un18_check_raddr_d_0_a2_0_a2_0_a2_0_a2[10]), + .Q(com_cmmt_raddr[10]) + ); + FDE com_tlm_u_tlm_rx_data_snk_bar_hit_check_raddr_o_9_ ( + .CE(com_tlm_u_tlm_rx_data_snk_sof_q_1__5135), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_bar_hit_un18_check_raddr_d_0_a2_0_a2_0_a2_0_a2[9]), + .Q(com_cmmt_raddr[9]) + ); + FDE com_tlm_u_tlm_rx_data_snk_bar_hit_check_raddr_o_8_ ( + .CE(com_tlm_u_tlm_rx_data_snk_sof_q_1__5135), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_bar_hit_un18_check_raddr_d_0_a2_0_a2_0_a2_0_a2[8]), + .Q(com_cmmt_raddr[8]) + ); + FDE com_tlm_u_tlm_rx_data_snk_bar_hit_check_raddr_o_7_ ( + .CE(com_tlm_u_tlm_rx_data_snk_sof_q_1__5135), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_bar_hit_un18_check_raddr_d_0_a2_0_a2_0_a2_0_a2[7]), + .Q(com_cmmt_raddr[7]) + ); + FDE com_tlm_u_tlm_rx_data_snk_bar_hit_check_raddr_o_6_ ( + .CE(com_tlm_u_tlm_rx_data_snk_sof_q_1__5135), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_bar_hit_un18_check_raddr_d_0_a2_0_a2_0_a2_0_a2[6]), + .Q(com_cmmt_raddr[6]) + ); + FDE com_tlm_u_tlm_rx_data_snk_bar_hit_check_raddr_o_5_ ( + .CE(com_tlm_u_tlm_rx_data_snk_sof_q_1__5135), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_bar_hit_un18_check_raddr_d_0_a2_0_a2_0_a2[5]), + .Q(com_cmmt_raddr[5]) + ); + FDE com_tlm_u_tlm_rx_data_snk_bar_hit_check_raddr_o_4_ ( + .CE(com_tlm_u_tlm_rx_data_snk_sof_q_1__5135), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_data_snk_bar_hit_un18_check_raddr_d_0_a2_0_a2_0_a2[4]), + .Q(com_cmmt_raddr[4]) + ); + GND com_tlm_u_tlm_rx_fc_src_GND ( + .G(com_tlm_u_tlm_rx_fc_src_GND_5284) + ); + FDRE com_tlm_u_tlm_rx_fc_src_lnk_tfc_src_rdy_o_1 ( + .CE(com_tlm_u_tlm_rx_fc_src_N_87522_i_5286), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_fc_src_N_21949_i), + .Q(com_tlm_u_tlm_rx_fc_src_lnk_tfc_src_rdy), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_rx_fc_src_fc_update_en_o ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_fc_src_N_16034_i), + .Q(com_tlm_aspm_ok), + .R(plm_link_up_i) + ); + FDRSE com_tlm_u_tlm_rx_fc_src_np_vld ( + .CE(com_tlm_u_tlm_rx_fc_src_N_87525_i_5287), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_fc_src_GND_5284), + .Q(com_tlm_u_tlm_rx_fc_src_np_vld_5314), + .R(plm_link_up_i), + .S(com_tlm_u_tlm_rx_fc_send_state_0_sqmuxa_0) + ); + FDRSE com_tlm_u_tlm_rx_fc_src_p_vld ( + .CE(com_tlm_u_tlm_rx_fc_src_N_87232_i_5288), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_fc_src_GND_5284), + .Q(com_tlm_u_tlm_rx_fc_src_p_vld_5292), + .R(plm_link_up_i), + .S(com_tlm_u_tlm_rx_fc_send_state_0_sqmuxa) + ); + FDRE com_tlm_u_tlm_rx_fc_src_p_pending ( + .CE(com_tlm_u_tlm_rx_fc_src_N_58788_i_5317), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_fc_src_lnk_tfc_data_o_0_sqmuxa), + .Q(com_tlm_u_tlm_rx_fc_src_p_pending_5291), + .R(plm_link_up_i) + ); + FDRE com_tlm_u_tlm_rx_fc_src_np_pending ( + .CE(com_tlm_u_tlm_rx_fc_src_N_58788_i_5317), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_fc_src_np_pending_6), + .Q(com_tlm_u_tlm_rx_fc_src_np_pending_5290), + .R(plm_link_up_i) + ); + FDRE com_tlm_u_tlm_rx_fc_src_init_pending ( + .CE(com_tlm_u_tlm_rx_fc_src_N_58788_i_5317), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_fc_src_initFC_st_i[0]), + .Q(com_tlm_u_tlm_rx_fc_src_init_pending_5285), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_rx_fc_src_fc_req_p_dst_rdy_o ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_fc_src_N_43440_i), + .Q(com_tlm_u_tlm_rx_fc_req_p_dst_rdy), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_rx_fc_src_fc_req_np_dst_rdy_o ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_fc_src_N_43438_i), + .Q(com_tlm_u_tlm_rx_fc_req_np_dst_rdy), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_rx_fc_src_fc_sched_p_o ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_fc_src_fc_sched_p_o_5), + .Q(com_tlm_u_tlm_rx_fc_sched_p), + .R(plm_link_up_i) + ); + FDR com_tlm_u_tlm_rx_fc_src_fc_sched_np_o ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_fc_src_fc_sched_np_o_5), + .Q(com_tlm_u_tlm_rx_fc_sched_np), + .R(plm_link_up_i) + ); + FDRSE com_tlm_u_tlm_rx_fc_src_init2_seq_det ( + .CE(com_tlm_u_tlm_rx_fc_src_initFC_st[4]), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_fc_src_GND_5284), + .Q(com_tlm_u_tlm_rx_fc_src_init2_seq_det_5293), + .R(plm_link_up_i), + .S(com_link_status[2]) + ); + FDRE com_tlm_u_tlm_rx_fc_src_initFC_st_6_ ( + .CE(com_tlm_u_tlm_rx_fc_src_N_85516_i_5289), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_fc_src_initFC_st[5]), + .Q(com_tlm_u_tlm_rx_fc_src_initFC_st[6]), + .R(plm_link_up_i) + ); + FDRE com_tlm_u_tlm_rx_fc_src_initFC_st_5_ ( + .CE(com_tlm_u_tlm_rx_fc_src_N_85516_i_5289), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_fc_src_initFC_st[4]), + .Q(com_tlm_u_tlm_rx_fc_src_initFC_st[5]), + .R(plm_link_up_i) + ); + FDRE com_tlm_u_tlm_rx_fc_src_initFC_st_4_ ( + .CE(com_tlm_u_tlm_rx_fc_src_N_85516_i_5289), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_fc_src_initFC_stc_0_i), + .Q(com_tlm_u_tlm_rx_fc_src_initFC_st[4]), + .R(plm_link_up_i) + ); + FDRE com_tlm_u_tlm_rx_fc_src_initFC_st_3_ ( + .CE(com_tlm_u_tlm_rx_fc_src_N_85516_i_5289), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_fc_src_initFC_st[2]), + .Q(com_tlm_u_tlm_rx_fc_src_initFC_st[3]), + .R(plm_link_up_i) + ); + FDRE com_tlm_u_tlm_rx_fc_src_initFC_st_2_ ( + .CE(com_tlm_u_tlm_rx_fc_src_N_85516_i_5289), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_fc_src_initFC_st[1]), + .Q(com_tlm_u_tlm_rx_fc_src_initFC_st[2]), + .R(plm_link_up_i) + ); + FDRE com_tlm_u_tlm_rx_fc_src_initFC_st_1_ ( + .CE(com_tlm_u_tlm_rx_fc_src_N_85516_i_5289), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_fc_src_initFC_stc_i), + .Q(com_tlm_u_tlm_rx_fc_src_initFC_st[1]), + .R(plm_link_up_i) + ); + FDSE com_tlm_u_tlm_rx_fc_src_initFC_st_0_ ( + .CE(com_tlm_u_tlm_rx_fc_src_N_85516_i_5289), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_fc_src_N_58440), + .Q(com_tlm_u_tlm_rx_fc_src_initFC_st[0]), + .S(plm_link_up_i) + ); + defparam com_tlm_u_tlm_rx_fc_src_un1_lnk_tfc_dst_rdy_i_0_o2_i_a2.INIT = 4'h4; + LUT2 com_tlm_u_tlm_rx_fc_src_un1_lnk_tfc_dst_rdy_i_0_o2_i_a2 ( + .I0(com_lnk_tfc_dst_rdy_n), + .I1(com_tlm_u_tlm_rx_fc_src_lnk_tfc_src_rdy), + .O(com_un1_lnk_tfc_dst_rdy_i_0_o2_i_a2) + ); + defparam com_tlm_u_tlm_rx_fc_src_lnk_tfc_type_o_11_0_i_0_0_o2_0_.INIT = 4'h1; + LUT2 com_tlm_u_tlm_rx_fc_src_lnk_tfc_type_o_11_0_i_0_0_o2_0_ ( + .I0(com_tlm_u_tlm_rx_fc_src_initFC_st[2]), + .I1(com_tlm_u_tlm_rx_fc_src_initFC_st[5]), + .O(com_tlm_u_tlm_rx_fc_src_N_55891_i) + ); + defparam com_tlm_u_tlm_rx_fc_src_fc_req_p_dst_rdy_o_7_0_a2_i_0_o2.INIT = 4'h2; + LUT2 com_tlm_u_tlm_rx_fc_src_fc_req_p_dst_rdy_o_7_0_a2_i_0_o2 ( + .I0(com_tlm_u_tlm_rx_fc_src_initFC_st[0]), + .I1(com_tlm_u_tlm_rx_fc_src_p_vld_5292), + .O(com_tlm_u_tlm_rx_fc_src_N_56217_i) + ); + defparam com_tlm_u_tlm_rx_fc_src_initFC_nst_0_sqmuxa_i_0_0_0_o3.INIT = 8'h01; + LUT3 com_tlm_u_tlm_rx_fc_src_initFC_nst_0_sqmuxa_i_0_0_0_o3 ( + .I0(com_tlm_u_tlm_rx_fc_src_initFC_st[0]), + .I1(com_tlm_u_tlm_rx_fc_src_initFC_st[3]), + .I2(com_tlm_u_tlm_rx_fc_src_initFC_st[6]), + .O(com_tlm_u_tlm_rx_fc_src_N_56332_i) + ); + defparam com_tlm_u_tlm_rx_fc_src_un1_load_output_1_i_0_0_0_0_o3.INIT = 8'h01; + LUT3 com_tlm_u_tlm_rx_fc_src_un1_load_output_1_i_0_0_0_0_o3 ( + .I0(com_tlm_u_tlm_rx_fc_src_init_pending_5285), + .I1(com_tlm_u_tlm_rx_fc_src_np_pending_5290), + .I2(com_tlm_u_tlm_rx_fc_src_p_pending_5291), + .O(com_tlm_u_tlm_rx_fc_src_N_56329_i) + ); + defparam com_tlm_u_tlm_rx_fc_src_lnk_tfc_header_o_11_3_a2_i_0_0_a2_0_6_.INIT = 16'h02A2; + LUT4 com_tlm_u_tlm_rx_fc_src_lnk_tfc_header_o_11_3_a2_i_0_0_a2_0_6_ ( + .I0(com_tlm_u_tlm_rx_fc_src_initFC_st[0]), + .I1(com_tlm_u_tlm_rx_fc_src_nph[6]), + .I2(com_tlm_u_tlm_rx_fc_src_p_vld_5292), + .I3(com_tlm_u_tlm_rx_fc_src_ph[6]), + .O(com_tlm_u_tlm_rx_fc_src_N_59167) + ); + defparam com_tlm_u_tlm_rx_fc_src_lnk_tfc_header_o_11_3_a2_i_0_0_a2_0_5_.INIT = 16'h02A2; + LUT4 com_tlm_u_tlm_rx_fc_src_lnk_tfc_header_o_11_3_a2_i_0_0_a2_0_5_ ( + .I0(com_tlm_u_tlm_rx_fc_src_initFC_st[0]), + .I1(com_tlm_u_tlm_rx_fc_src_nph[5]), + .I2(com_tlm_u_tlm_rx_fc_src_p_vld_5292), + .I3(com_tlm_u_tlm_rx_fc_src_ph[5]), + .O(com_tlm_u_tlm_rx_fc_src_N_59164) + ); + defparam com_tlm_u_tlm_rx_fc_src_lnk_tfc_header_o_11_3_a2_i_0_0_a2_0_4_.INIT = 16'h02A2; + LUT4 com_tlm_u_tlm_rx_fc_src_lnk_tfc_header_o_11_3_a2_i_0_0_a2_0_4_ ( + .I0(com_tlm_u_tlm_rx_fc_src_initFC_st[0]), + .I1(com_tlm_u_tlm_rx_fc_src_nph[4]), + .I2(com_tlm_u_tlm_rx_fc_src_p_vld_5292), + .I3(com_tlm_u_tlm_rx_fc_src_ph[4]), + .O(com_tlm_u_tlm_rx_fc_src_N_59161) + ); + defparam com_tlm_u_tlm_rx_fc_src_lnk_tfc_header_o_11_3_a2_i_0_0_a2_0_3_.INIT = 16'h02A2; + LUT4 com_tlm_u_tlm_rx_fc_src_lnk_tfc_header_o_11_3_a2_i_0_0_a2_0_3_ ( + .I0(com_tlm_u_tlm_rx_fc_src_initFC_st[0]), + .I1(com_tlm_u_tlm_rx_fc_src_nph[3]), + .I2(com_tlm_u_tlm_rx_fc_src_p_vld_5292), + .I3(com_tlm_u_tlm_rx_fc_src_ph[3]), + .O(com_tlm_u_tlm_rx_fc_src_N_59158) + ); + defparam com_tlm_u_tlm_rx_fc_src_lnk_tfc_header_o_11_3_a2_i_0_0_a2_0_2_.INIT = 16'h02A2; + LUT4 com_tlm_u_tlm_rx_fc_src_lnk_tfc_header_o_11_3_a2_i_0_0_a2_0_2_ ( + .I0(com_tlm_u_tlm_rx_fc_src_initFC_st[0]), + .I1(com_tlm_u_tlm_rx_fc_src_nph[2]), + .I2(com_tlm_u_tlm_rx_fc_src_p_vld_5292), + .I3(com_tlm_u_tlm_rx_fc_src_ph[2]), + .O(com_tlm_u_tlm_rx_fc_src_N_59155) + ); + defparam com_tlm_u_tlm_rx_fc_src_lnk_tfc_header_o_11_3_a2_i_0_0_a2_0_1_.INIT = 16'h02A2; + LUT4 com_tlm_u_tlm_rx_fc_src_lnk_tfc_header_o_11_3_a2_i_0_0_a2_0_1_ ( + .I0(com_tlm_u_tlm_rx_fc_src_initFC_st[0]), + .I1(com_tlm_u_tlm_rx_fc_src_nph[1]), + .I2(com_tlm_u_tlm_rx_fc_src_p_vld_5292), + .I3(com_tlm_u_tlm_rx_fc_src_ph[1]), + .O(com_tlm_u_tlm_rx_fc_src_N_59152) + ); + defparam com_tlm_u_tlm_rx_fc_src_lnk_tfc_header_o_11_3_a2_i_0_0_a2_0_0_.INIT = 16'h02A2; + LUT4 com_tlm_u_tlm_rx_fc_src_lnk_tfc_header_o_11_3_a2_i_0_0_a2_0_0_ ( + .I0(com_tlm_u_tlm_rx_fc_src_initFC_st[0]), + .I1(com_tlm_u_tlm_rx_fc_src_nph[0]), + .I2(com_tlm_u_tlm_rx_fc_src_p_vld_5292), + .I3(com_tlm_u_tlm_rx_fc_src_ph[0]), + .O(com_tlm_u_tlm_rx_fc_src_N_59149) + ); + defparam com_tlm_u_tlm_rx_fc_src_lnk_tfc_data_o_11_3_a2_i_0_0_a2_0_11_.INIT = 16'h02A2; + LUT4 com_tlm_u_tlm_rx_fc_src_lnk_tfc_data_o_11_3_a2_i_0_0_a2_0_11_ ( + .I0(com_tlm_u_tlm_rx_fc_src_initFC_st[0]), + .I1(com_tlm_u_tlm_rx_fc_src_npd[11]), + .I2(com_tlm_u_tlm_rx_fc_src_p_vld_5292), + .I3(com_tlm_u_tlm_rx_fc_src_pd[11]), + .O(com_tlm_u_tlm_rx_fc_src_N_59146) + ); + defparam com_tlm_u_tlm_rx_fc_src_lnk_tfc_data_o_11_3_a2_i_0_0_a2_0_10_.INIT = 16'h02A2; + LUT4 com_tlm_u_tlm_rx_fc_src_lnk_tfc_data_o_11_3_a2_i_0_0_a2_0_10_ ( + .I0(com_tlm_u_tlm_rx_fc_src_initFC_st[0]), + .I1(com_tlm_u_tlm_rx_fc_src_npd[10]), + .I2(com_tlm_u_tlm_rx_fc_src_p_vld_5292), + .I3(com_tlm_u_tlm_rx_fc_src_pd[10]), + .O(com_tlm_u_tlm_rx_fc_src_N_59143) + ); + defparam com_tlm_u_tlm_rx_fc_src_lnk_tfc_data_o_11_3_a2_i_0_0_a2_0_4_.INIT = 16'h02A2; + LUT4 com_tlm_u_tlm_rx_fc_src_lnk_tfc_data_o_11_3_a2_i_0_0_a2_0_4_ ( + .I0(com_tlm_u_tlm_rx_fc_src_initFC_st[0]), + .I1(com_tlm_u_tlm_rx_fc_src_npd[4]), + .I2(com_tlm_u_tlm_rx_fc_src_p_vld_5292), + .I3(com_tlm_u_tlm_rx_fc_src_pd[4]), + .O(com_tlm_u_tlm_rx_fc_src_N_59140) + ); + defparam com_tlm_u_tlm_rx_fc_src_lnk_tfc_data_o_11_3_a2_i_0_0_a2_0_3_.INIT = 16'h02A2; + LUT4 com_tlm_u_tlm_rx_fc_src_lnk_tfc_data_o_11_3_a2_i_0_0_a2_0_3_ ( + .I0(com_tlm_u_tlm_rx_fc_src_initFC_st[0]), + .I1(com_tlm_u_tlm_rx_fc_src_npd[3]), + .I2(com_tlm_u_tlm_rx_fc_src_p_vld_5292), + .I3(com_tlm_u_tlm_rx_fc_src_pd[3]), + .O(com_tlm_u_tlm_rx_fc_src_N_59137) + ); + defparam com_tlm_u_tlm_rx_fc_src_lnk_tfc_data_o_11_3_a2_i_0_0_a2_0_2_.INIT = 16'h02A2; + LUT4 com_tlm_u_tlm_rx_fc_src_lnk_tfc_data_o_11_3_a2_i_0_0_a2_0_2_ ( + .I0(com_tlm_u_tlm_rx_fc_src_initFC_st[0]), + .I1(com_tlm_u_tlm_rx_fc_src_npd[2]), + .I2(com_tlm_u_tlm_rx_fc_src_p_vld_5292), + .I3(com_tlm_u_tlm_rx_fc_src_pd[2]), + .O(com_tlm_u_tlm_rx_fc_src_N_59134) + ); + defparam com_tlm_u_tlm_rx_fc_src_lnk_tfc_data_o_11_3_a2_i_0_0_a2_0_1_.INIT = 16'h02A2; + LUT4 com_tlm_u_tlm_rx_fc_src_lnk_tfc_data_o_11_3_a2_i_0_0_a2_0_1_ ( + .I0(com_tlm_u_tlm_rx_fc_src_initFC_st[0]), + .I1(com_tlm_u_tlm_rx_fc_src_npd[1]), + .I2(com_tlm_u_tlm_rx_fc_src_p_vld_5292), + .I3(com_tlm_u_tlm_rx_fc_src_pd[1]), + .O(com_tlm_u_tlm_rx_fc_src_N_59131) + ); + defparam com_tlm_u_tlm_rx_fc_src_lnk_tfc_data_o_11_3_a2_i_0_0_a2_0_0_.INIT = 16'h02A2; + LUT4 com_tlm_u_tlm_rx_fc_src_lnk_tfc_data_o_11_3_a2_i_0_0_a2_0_0_ ( + .I0(com_tlm_u_tlm_rx_fc_src_initFC_st[0]), + .I1(com_tlm_u_tlm_rx_fc_src_npd[0]), + .I2(com_tlm_u_tlm_rx_fc_src_p_vld_5292), + .I3(com_tlm_u_tlm_rx_fc_src_pd[0]), + .O(com_tlm_u_tlm_rx_fc_src_N_59128) + ); + defparam com_tlm_u_tlm_rx_fc_src_lnk_tfc_header_o_11_i_0_0_0_a2_0_7_.INIT = 16'h02A2; + LUT4 com_tlm_u_tlm_rx_fc_src_lnk_tfc_header_o_11_i_0_0_0_a2_0_7_ ( + .I0(com_tlm_u_tlm_rx_fc_src_initFC_st[0]), + .I1(com_tlm_u_tlm_rx_fc_src_nph[7]), + .I2(com_tlm_u_tlm_rx_fc_src_p_vld_5292), + .I3(com_tlm_u_tlm_rx_fc_src_ph[7]), + .O(com_tlm_u_tlm_rx_fc_src_N_58764) + ); + defparam com_tlm_u_tlm_rx_fc_src_lnk_tfc_data_o_11_i_0_0_0_a2_0_9_.INIT = 16'h02A2; + LUT4 com_tlm_u_tlm_rx_fc_src_lnk_tfc_data_o_11_i_0_0_0_a2_0_9_ ( + .I0(com_tlm_u_tlm_rx_fc_src_initFC_st[0]), + .I1(com_tlm_u_tlm_rx_fc_src_npd[9]), + .I2(com_tlm_u_tlm_rx_fc_src_p_vld_5292), + .I3(com_tlm_u_tlm_rx_fc_src_pd[9]), + .O(com_tlm_u_tlm_rx_fc_src_N_58761) + ); + defparam com_tlm_u_tlm_rx_fc_src_lnk_tfc_data_o_11_i_0_0_0_a2_0_8_.INIT = 16'h02A2; + LUT4 com_tlm_u_tlm_rx_fc_src_lnk_tfc_data_o_11_i_0_0_0_a2_0_8_ ( + .I0(com_tlm_u_tlm_rx_fc_src_initFC_st[0]), + .I1(com_tlm_u_tlm_rx_fc_src_npd[8]), + .I2(com_tlm_u_tlm_rx_fc_src_p_vld_5292), + .I3(com_tlm_u_tlm_rx_fc_src_pd[8]), + .O(com_tlm_u_tlm_rx_fc_src_N_58758) + ); + defparam com_tlm_u_tlm_rx_fc_src_lnk_tfc_data_o_11_i_0_0_0_a2_0_7_.INIT = 16'h02A2; + LUT4 com_tlm_u_tlm_rx_fc_src_lnk_tfc_data_o_11_i_0_0_0_a2_0_7_ ( + .I0(com_tlm_u_tlm_rx_fc_src_initFC_st[0]), + .I1(com_tlm_u_tlm_rx_fc_src_npd[7]), + .I2(com_tlm_u_tlm_rx_fc_src_p_vld_5292), + .I3(com_tlm_u_tlm_rx_fc_src_pd[7]), + .O(com_tlm_u_tlm_rx_fc_src_N_58755) + ); + defparam com_tlm_u_tlm_rx_fc_src_lnk_tfc_data_o_11_i_0_0_0_a2_0_6_.INIT = 16'h02A2; + LUT4 com_tlm_u_tlm_rx_fc_src_lnk_tfc_data_o_11_i_0_0_0_a2_0_6_ ( + .I0(com_tlm_u_tlm_rx_fc_src_initFC_st[0]), + .I1(com_tlm_u_tlm_rx_fc_src_npd[6]), + .I2(com_tlm_u_tlm_rx_fc_src_p_vld_5292), + .I3(com_tlm_u_tlm_rx_fc_src_pd[6]), + .O(com_tlm_u_tlm_rx_fc_src_N_58752) + ); + defparam com_tlm_u_tlm_rx_fc_src_lnk_tfc_data_o_11_i_0_0_0_a2_0_5_.INIT = 16'h02A2; + LUT4 com_tlm_u_tlm_rx_fc_src_lnk_tfc_data_o_11_i_0_0_0_a2_0_5_ ( + .I0(com_tlm_u_tlm_rx_fc_src_initFC_st[0]), + .I1(com_tlm_u_tlm_rx_fc_src_npd[5]), + .I2(com_tlm_u_tlm_rx_fc_src_p_vld_5292), + .I3(com_tlm_u_tlm_rx_fc_src_pd[5]), + .O(com_tlm_u_tlm_rx_fc_src_N_58749) + ); + defparam com_tlm_u_tlm_rx_fc_src_N_58788_i.INIT = 4'hB; + LUT2 com_tlm_u_tlm_rx_fc_src_N_58788_i ( + .I0(com_tlm_u_tlm_rx_fc_src_N_56329_i), + .I1(com_lnk_tfc_sent_n), + .O(com_tlm_u_tlm_rx_fc_src_N_58788_i_5317) + ); + defparam com_tlm_u_tlm_rx_fc_src_lnk_tfc_header_o_11_i_0_0_0_7_39397.INIT = 16'hFFE4; + LUT4_L com_tlm_u_tlm_rx_fc_src_lnk_tfc_header_o_11_i_0_0_0_7_39397 ( + .I0(com_tlm_u_tlm_rx_fc_src_N_55891_i), + .I1(com_tlm_u_tlm_rx_fc_req_nph[7]), + .I2(com_tlm_u_tlm_rx_fc_req_ph[7]), + .I3(com_tlm_u_tlm_rx_fc_src_initFC_st[0]), + .LO(com_tlm_u_tlm_rx_fc_src_lnk_tfc_header_o_11_i_0_0_0_7_39397_5306) + ); + defparam com_tlm_u_tlm_rx_fc_src_lnk_tfc_data_o_11_i_0_0_0_9_39398.INIT = 16'hFFE4; + LUT4_L com_tlm_u_tlm_rx_fc_src_lnk_tfc_data_o_11_i_0_0_0_9_39398 ( + .I0(com_tlm_u_tlm_rx_fc_src_N_55891_i), + .I1(com_tlm_u_tlm_rx_fc_req_npd[9]), + .I2(com_tlm_u_tlm_rx_fc_req_pd[9]), + .I3(com_tlm_u_tlm_rx_fc_src_initFC_st[0]), + .LO(com_tlm_u_tlm_rx_fc_src_lnk_tfc_data_o_11_i_0_0_0_9_39398_5296) + ); + defparam com_tlm_u_tlm_rx_fc_src_lnk_tfc_data_o_11_i_0_0_0_8_39399.INIT = 16'hFFE4; + LUT4_L com_tlm_u_tlm_rx_fc_src_lnk_tfc_data_o_11_i_0_0_0_8_39399 ( + .I0(com_tlm_u_tlm_rx_fc_src_N_55891_i), + .I1(com_tlm_u_tlm_rx_fc_req_npd[8]), + .I2(com_tlm_u_tlm_rx_fc_req_pd[8]), + .I3(com_tlm_u_tlm_rx_fc_src_initFC_st[0]), + .LO(com_tlm_u_tlm_rx_fc_src_lnk_tfc_data_o_11_i_0_0_0_8_39399_5297) + ); + defparam com_tlm_u_tlm_rx_fc_src_lnk_tfc_data_o_11_i_0_0_0_7_39400.INIT = 16'hFFE4; + LUT4_L com_tlm_u_tlm_rx_fc_src_lnk_tfc_data_o_11_i_0_0_0_7_39400 ( + .I0(com_tlm_u_tlm_rx_fc_src_N_55891_i), + .I1(com_tlm_u_tlm_rx_fc_req_npd[7]), + .I2(com_tlm_u_tlm_rx_fc_req_pd[7]), + .I3(com_tlm_u_tlm_rx_fc_src_initFC_st[0]), + .LO(com_tlm_u_tlm_rx_fc_src_lnk_tfc_data_o_11_i_0_0_0_7_39400_5298) + ); + defparam com_tlm_u_tlm_rx_fc_src_lnk_tfc_data_o_11_i_0_0_0_6_39401.INIT = 16'hFFE4; + LUT4_L com_tlm_u_tlm_rx_fc_src_lnk_tfc_data_o_11_i_0_0_0_6_39401 ( + .I0(com_tlm_u_tlm_rx_fc_src_N_55891_i), + .I1(com_tlm_u_tlm_rx_fc_req_npd[6]), + .I2(com_tlm_u_tlm_rx_fc_req_pd[6]), + .I3(com_tlm_u_tlm_rx_fc_src_initFC_st[0]), + .LO(com_tlm_u_tlm_rx_fc_src_lnk_tfc_data_o_11_i_0_0_0_6_39401_5299) + ); + defparam com_tlm_u_tlm_rx_fc_src_lnk_tfc_data_o_11_i_0_0_0_5_39402.INIT = 16'hFFE4; + LUT4_L com_tlm_u_tlm_rx_fc_src_lnk_tfc_data_o_11_i_0_0_0_5_39402 ( + .I0(com_tlm_u_tlm_rx_fc_src_N_55891_i), + .I1(com_tlm_u_tlm_rx_fc_req_npd[5]), + .I2(com_tlm_u_tlm_rx_fc_req_pd[5]), + .I3(com_tlm_u_tlm_rx_fc_src_initFC_st[0]), + .LO(com_tlm_u_tlm_rx_fc_src_lnk_tfc_data_o_11_i_0_0_0_5_39402_5300) + ); + defparam com_tlm_u_tlm_rx_fc_src_lnk_tfc_data_o_11_3_a2_i_0_0_10_39403.INIT = 16'hFFE4; + LUT4_L com_tlm_u_tlm_rx_fc_src_lnk_tfc_data_o_11_3_a2_i_0_0_10_39403 ( + .I0(com_tlm_u_tlm_rx_fc_src_N_55891_i), + .I1(com_tlm_u_tlm_rx_fc_req_npd[10]), + .I2(com_tlm_u_tlm_rx_fc_req_pd[10]), + .I3(com_tlm_u_tlm_rx_fc_src_initFC_st[0]), + .LO(com_tlm_u_tlm_rx_fc_src_lnk_tfc_data_o_11_3_a2_i_0_0_10_39403_5295) + ); + defparam com_tlm_u_tlm_rx_fc_src_lnk_tfc_data_o_11_3_a2_i_0_0_4_39404.INIT = 16'hFFE4; + LUT4_L com_tlm_u_tlm_rx_fc_src_lnk_tfc_data_o_11_3_a2_i_0_0_4_39404 ( + .I0(com_tlm_u_tlm_rx_fc_src_N_55891_i), + .I1(com_tlm_u_tlm_rx_fc_req_npd[4]), + .I2(com_tlm_u_tlm_rx_fc_req_pd[4]), + .I3(com_tlm_u_tlm_rx_fc_src_initFC_st[0]), + .LO(com_tlm_u_tlm_rx_fc_src_lnk_tfc_data_o_11_3_a2_i_0_0_4_39404_5301) + ); + defparam com_tlm_u_tlm_rx_fc_src_lnk_tfc_data_o_11_3_a2_i_0_0_3_39405.INIT = 16'hFFE4; + LUT4_L com_tlm_u_tlm_rx_fc_src_lnk_tfc_data_o_11_3_a2_i_0_0_3_39405 ( + .I0(com_tlm_u_tlm_rx_fc_src_N_55891_i), + .I1(com_tlm_u_tlm_rx_fc_req_npd[3]), + .I2(com_tlm_u_tlm_rx_fc_req_pd[3]), + .I3(com_tlm_u_tlm_rx_fc_src_initFC_st[0]), + .LO(com_tlm_u_tlm_rx_fc_src_lnk_tfc_data_o_11_3_a2_i_0_0_3_39405_5302) + ); + defparam com_tlm_u_tlm_rx_fc_src_lnk_tfc_data_o_11_3_a2_i_0_0_2_39406.INIT = 16'hFFE4; + LUT4_L com_tlm_u_tlm_rx_fc_src_lnk_tfc_data_o_11_3_a2_i_0_0_2_39406 ( + .I0(com_tlm_u_tlm_rx_fc_src_N_55891_i), + .I1(com_tlm_u_tlm_rx_fc_req_npd[2]), + .I2(com_tlm_u_tlm_rx_fc_req_pd[2]), + .I3(com_tlm_u_tlm_rx_fc_src_initFC_st[0]), + .LO(com_tlm_u_tlm_rx_fc_src_lnk_tfc_data_o_11_3_a2_i_0_0_2_39406_5303) + ); + defparam com_tlm_u_tlm_rx_fc_src_lnk_tfc_data_o_11_3_a2_i_0_0_1_39407.INIT = 16'hFFE4; + LUT4_L com_tlm_u_tlm_rx_fc_src_lnk_tfc_data_o_11_3_a2_i_0_0_1_39407 ( + .I0(com_tlm_u_tlm_rx_fc_src_N_55891_i), + .I1(com_tlm_u_tlm_rx_fc_req_npd[1]), + .I2(com_tlm_u_tlm_rx_fc_req_pd[1]), + .I3(com_tlm_u_tlm_rx_fc_src_initFC_st[0]), + .LO(com_tlm_u_tlm_rx_fc_src_lnk_tfc_data_o_11_3_a2_i_0_0_1_39407_5304) + ); + defparam com_tlm_u_tlm_rx_fc_src_lnk_tfc_data_o_11_3_a2_i_0_0_0_39408.INIT = 16'hFFE4; + LUT4_L com_tlm_u_tlm_rx_fc_src_lnk_tfc_data_o_11_3_a2_i_0_0_0_39408 ( + .I0(com_tlm_u_tlm_rx_fc_src_N_55891_i), + .I1(com_tlm_u_tlm_rx_fc_req_npd[0]), + .I2(com_tlm_u_tlm_rx_fc_req_pd[0]), + .I3(com_tlm_u_tlm_rx_fc_src_initFC_st[0]), + .LO(com_tlm_u_tlm_rx_fc_src_lnk_tfc_data_o_11_3_a2_i_0_0_0_39408_5305) + ); + defparam com_tlm_u_tlm_rx_fc_src_lnk_tfc_header_o_11_3_a2_i_0_0_6_39409.INIT = 16'hFFE4; + LUT4_L com_tlm_u_tlm_rx_fc_src_lnk_tfc_header_o_11_3_a2_i_0_0_6_39409 ( + .I0(com_tlm_u_tlm_rx_fc_src_N_55891_i), + .I1(com_tlm_u_tlm_rx_fc_req_nph[6]), + .I2(com_tlm_u_tlm_rx_fc_req_ph[6]), + .I3(com_tlm_u_tlm_rx_fc_src_initFC_st[0]), + .LO(com_tlm_u_tlm_rx_fc_src_lnk_tfc_header_o_11_3_a2_i_0_0_6_39409_5307) + ); + defparam com_tlm_u_tlm_rx_fc_src_lnk_tfc_header_o_11_3_a2_i_0_0_5_39410.INIT = 16'hFFE4; + LUT4_L com_tlm_u_tlm_rx_fc_src_lnk_tfc_header_o_11_3_a2_i_0_0_5_39410 ( + .I0(com_tlm_u_tlm_rx_fc_src_N_55891_i), + .I1(com_tlm_u_tlm_rx_fc_req_nph[5]), + .I2(com_tlm_u_tlm_rx_fc_req_ph[5]), + .I3(com_tlm_u_tlm_rx_fc_src_initFC_st[0]), + .LO(com_tlm_u_tlm_rx_fc_src_lnk_tfc_header_o_11_3_a2_i_0_0_5_39410_5308) + ); + defparam com_tlm_u_tlm_rx_fc_src_lnk_tfc_header_o_11_3_a2_i_0_0_4_39411.INIT = 16'hFFE4; + LUT4_L com_tlm_u_tlm_rx_fc_src_lnk_tfc_header_o_11_3_a2_i_0_0_4_39411 ( + .I0(com_tlm_u_tlm_rx_fc_src_N_55891_i), + .I1(com_tlm_u_tlm_rx_fc_req_nph[4]), + .I2(com_tlm_u_tlm_rx_fc_req_ph[4]), + .I3(com_tlm_u_tlm_rx_fc_src_initFC_st[0]), + .LO(com_tlm_u_tlm_rx_fc_src_lnk_tfc_header_o_11_3_a2_i_0_0_4_39411_5309) + ); + defparam com_tlm_u_tlm_rx_fc_src_lnk_tfc_header_o_11_3_a2_i_0_0_3_39412.INIT = 16'hFFE4; + LUT4_L com_tlm_u_tlm_rx_fc_src_lnk_tfc_header_o_11_3_a2_i_0_0_3_39412 ( + .I0(com_tlm_u_tlm_rx_fc_src_N_55891_i), + .I1(com_tlm_u_tlm_rx_fc_req_nph[3]), + .I2(com_tlm_u_tlm_rx_fc_req_ph[3]), + .I3(com_tlm_u_tlm_rx_fc_src_initFC_st[0]), + .LO(com_tlm_u_tlm_rx_fc_src_lnk_tfc_header_o_11_3_a2_i_0_0_3_39412_5310) + ); + defparam com_tlm_u_tlm_rx_fc_src_lnk_tfc_header_o_11_3_a2_i_0_0_2_39413.INIT = 16'hFFE4; + LUT4_L com_tlm_u_tlm_rx_fc_src_lnk_tfc_header_o_11_3_a2_i_0_0_2_39413 ( + .I0(com_tlm_u_tlm_rx_fc_src_N_55891_i), + .I1(com_tlm_u_tlm_rx_fc_req_nph[2]), + .I2(com_tlm_u_tlm_rx_fc_req_ph[2]), + .I3(com_tlm_u_tlm_rx_fc_src_initFC_st[0]), + .LO(com_tlm_u_tlm_rx_fc_src_lnk_tfc_header_o_11_3_a2_i_0_0_2_39413_5311) + ); + defparam com_tlm_u_tlm_rx_fc_src_lnk_tfc_header_o_11_3_a2_i_0_0_1_39414.INIT = 16'hFFE4; + LUT4_L com_tlm_u_tlm_rx_fc_src_lnk_tfc_header_o_11_3_a2_i_0_0_1_39414 ( + .I0(com_tlm_u_tlm_rx_fc_src_N_55891_i), + .I1(com_tlm_u_tlm_rx_fc_req_nph[1]), + .I2(com_tlm_u_tlm_rx_fc_req_ph[1]), + .I3(com_tlm_u_tlm_rx_fc_src_initFC_st[0]), + .LO(com_tlm_u_tlm_rx_fc_src_lnk_tfc_header_o_11_3_a2_i_0_0_1_39414_5312) + ); + defparam com_tlm_u_tlm_rx_fc_src_lnk_tfc_header_o_11_3_a2_i_0_0_0_39415.INIT = 16'hFFE4; + LUT4_L com_tlm_u_tlm_rx_fc_src_lnk_tfc_header_o_11_3_a2_i_0_0_0_39415 ( + .I0(com_tlm_u_tlm_rx_fc_src_N_55891_i), + .I1(com_tlm_u_tlm_rx_fc_req_nph[0]), + .I2(com_tlm_u_tlm_rx_fc_req_ph[0]), + .I3(com_tlm_u_tlm_rx_fc_src_initFC_st[0]), + .LO(com_tlm_u_tlm_rx_fc_src_lnk_tfc_header_o_11_3_a2_i_0_0_0_39415_5313) + ); + defparam com_tlm_u_tlm_rx_fc_src_lnk_tfc_data_o_11_3_a2_i_0_0_11_39416.INIT = 16'hFFE4; + LUT4_L com_tlm_u_tlm_rx_fc_src_lnk_tfc_data_o_11_3_a2_i_0_0_11_39416 ( + .I0(com_tlm_u_tlm_rx_fc_src_N_55891_i), + .I1(com_tlm_u_tlm_rx_fc_req_npd[11]), + .I2(com_tlm_u_tlm_rx_fc_req_pd[11]), + .I3(com_tlm_u_tlm_rx_fc_src_initFC_st[0]), + .LO(com_tlm_u_tlm_rx_fc_src_lnk_tfc_data_o_11_3_a2_i_0_0_11_39416_5294) + ); + defparam com_tlm_u_tlm_rx_fc_src_N_87522_i.INIT = 8'hEF; + LUT3 com_tlm_u_tlm_rx_fc_src_N_87522_i ( + .I0(com_tlm_u_tlm_rx_fc_src_N_56329_i), + .I1(com_un1_lnk_tfc_dst_rdy_i_0_o2_i_a2), + .I2(com_lnk_tfc_sent_n), + .O(com_tlm_u_tlm_rx_fc_src_N_87522_i_5286) + ); + defparam com_tlm_u_tlm_rx_fc_src_N_87525_i.INIT = 8'h8A; + LUT3 com_tlm_u_tlm_rx_fc_src_N_87525_i ( + .I0(com_tlm_u_tlm_rx_fc_src_N_56217_i), + .I1(com_tlm_u_tlm_rx_fc_src_N_56329_i), + .I2(com_lnk_tfc_sent_n), + .O(com_tlm_u_tlm_rx_fc_src_N_87525_i_5287) + ); + defparam com_tlm_u_tlm_rx_fc_src_N_87232_i.INIT = 8'hB0; + LUT3 com_tlm_u_tlm_rx_fc_src_N_87232_i ( + .I0(com_tlm_u_tlm_rx_fc_src_N_56329_i), + .I1(com_lnk_tfc_sent_n), + .I2(com_tlm_u_tlm_rx_fc_src_initFC_st[0]), + .O(com_tlm_u_tlm_rx_fc_src_N_87232_i_5288) + ); + defparam com_tlm_u_tlm_rx_fc_src_N_85516_i.INIT = 16'hFBFF; + LUT4 com_tlm_u_tlm_rx_fc_src_N_85516_i ( + .I0(com_tlm_u_tlm_rx_fc_src_N_56329_i), + .I1(com_lnk_tfc_sent_n), + .I2(com_tlm_u_tlm_rx_fc_src_initFC_st[0]), + .I3(plm_link_up_1), + .O(com_tlm_u_tlm_rx_fc_src_N_85516_i_5289) + ); + defparam com_tlm_u_tlm_rx_fc_src_initFC_st_4_0_i_0_0_a2_0_.INIT = 16'h0001; + LUT4_L com_tlm_u_tlm_rx_fc_src_initFC_st_4_0_i_0_0_a2_0_ ( + .I0(com_tlm_u_tlm_rx_fc_src_N_56332_i), + .I1(com_link_status[1]), + .I2(com_link_status[2]), + .I3(com_tlm_u_tlm_rx_fc_src_init2_seq_det_5293), + .LO(com_tlm_u_tlm_rx_fc_src_N_58440) + ); + defparam com_tlm_u_tlm_rx_fc_src_initFC_stc.INIT = 4'h4; + LUT2_L com_tlm_u_tlm_rx_fc_src_initFC_stc ( + .I0(com_tlm_u_tlm_rx_fc_src_N_56332_i), + .I1(com_link_status[1]), + .LO(com_tlm_u_tlm_rx_fc_src_initFC_stc_i) + ); + defparam com_tlm_u_tlm_rx_fc_src_initFC_stc_0.INIT = 16'h1110; + LUT4_L com_tlm_u_tlm_rx_fc_src_initFC_stc_0 ( + .I0(com_tlm_u_tlm_rx_fc_src_N_56332_i), + .I1(com_link_status[1]), + .I2(com_link_status[2]), + .I3(com_tlm_u_tlm_rx_fc_src_init2_seq_det_5293), + .LO(com_tlm_u_tlm_rx_fc_src_initFC_stc_0_i) + ); + defparam com_tlm_u_tlm_rx_fc_src_N_63252_i.INIT = 4'h1; + LUT1_L com_tlm_u_tlm_rx_fc_src_N_63252_i ( + .I0(com_un1_lnk_tfc_dst_rdy_i_0_o2_i_a2), + .LO(com_N_63252_i) + ); + defparam com_tlm_u_tlm_rx_fc_src_aspm_ok_i.INIT = 4'h1; + LUT1_L com_tlm_u_tlm_rx_fc_src_aspm_ok_i ( + .I0(com_tlm_aspm_ok), + .LO(com_tlm_u_tlm_rx_aspm_ok_i) + ); + defparam com_tlm_u_tlm_rx_fc_src_fc_sched_np_o_5_0_a2_0_a2_0_a2_0_a2.INIT = 4'h4; + LUT2_L com_tlm_u_tlm_rx_fc_src_fc_sched_np_o_5_0_a2_0_a2_0_a2_0_a2 ( + .I0(com_lnk_tfc_sent_n), + .I1(com_tlm_u_tlm_rx_fc_src_np_pending_5290), + .LO(com_tlm_u_tlm_rx_fc_src_fc_sched_np_o_5) + ); + defparam com_tlm_u_tlm_rx_fc_src_fc_sched_p_o_5_0_a2_0_a2_0_a2_0_a2.INIT = 4'h4; + LUT2_L com_tlm_u_tlm_rx_fc_src_fc_sched_p_o_5_0_a2_0_a2_0_a2_0_a2 ( + .I0(com_lnk_tfc_sent_n), + .I1(com_tlm_u_tlm_rx_fc_src_p_pending_5291), + .LO(com_tlm_u_tlm_rx_fc_src_fc_sched_p_o_5) + ); + defparam com_tlm_u_tlm_rx_fc_src_fc_req_np_dst_rdy_o_7_0_a2_i_0.INIT = 8'h02; + LUT3_L com_tlm_u_tlm_rx_fc_src_fc_req_np_dst_rdy_o_7_0_a2_i_0 ( + .I0(com_tlm_u_tlm_rx_fc_src_initFC_st[0]), + .I1(com_tlm_u_tlm_rx_fc_src_np_vld_5314), + .I2(com_tlm_u_tlm_rx_fc_send_state_0_sqmuxa_0), + .LO(com_tlm_u_tlm_rx_fc_src_N_43438_i) + ); + defparam com_tlm_u_tlm_rx_fc_src_fc_req_p_dst_rdy_o_7_0_a2_i_0.INIT = 4'h2; + LUT2_L com_tlm_u_tlm_rx_fc_src_fc_req_p_dst_rdy_o_7_0_a2_i_0 ( + .I0(com_tlm_u_tlm_rx_fc_src_N_56217_i), + .I1(com_tlm_u_tlm_rx_fc_send_state_0_sqmuxa), + .LO(com_tlm_u_tlm_rx_fc_src_N_43440_i) + ); + defparam com_tlm_u_tlm_rx_fc_src_np_pending_6_0_a2_0_a2_0_a2.INIT = 4'h8; + LUT2_L com_tlm_u_tlm_rx_fc_src_np_pending_6_0_a2_0_a2_0_a2 ( + .I0(com_tlm_u_tlm_rx_fc_src_N_56217_i), + .I1(com_tlm_u_tlm_rx_fc_src_np_vld_5314), + .LO(com_tlm_u_tlm_rx_fc_src_np_pending_6) + ); + defparam com_tlm_u_tlm_rx_fc_src_lnk_tfc_data_o_0_sqmuxa_0_a2_0_a2_0_a2_0_a2.INIT = 4'h8; + LUT2_L com_tlm_u_tlm_rx_fc_src_lnk_tfc_data_o_0_sqmuxa_0_a2_0_a2_0_a2_0_a2 ( + .I0(com_tlm_u_tlm_rx_fc_src_initFC_st[0]), + .I1(com_tlm_u_tlm_rx_fc_src_p_vld_5292), + .LO(com_tlm_u_tlm_rx_fc_src_lnk_tfc_data_o_0_sqmuxa) + ); + defparam com_tlm_u_tlm_rx_fc_src_fc_update_en_o_3_i_0_0_0.INIT = 16'h5150; + LUT4_L com_tlm_u_tlm_rx_fc_src_fc_update_en_o_3_i_0_0_0 ( + .I0(com_link_status[1]), + .I1(com_link_status[2]), + .I2(com_tlm_aspm_ok), + .I3(com_tlm_u_tlm_rx_fc_src_init2_seq_det_5293), + .LO(com_tlm_u_tlm_rx_fc_src_N_16034_i) + ); + defparam com_tlm_u_tlm_rx_fc_src_lnk_tfc_data_o_11_3_a2_i_0_0_11_.INIT = 16'h0004; + LUT4_L com_tlm_u_tlm_rx_fc_src_lnk_tfc_data_o_11_3_a2_i_0_0_11_ ( + .I0(com_tlm_u_tlm_rx_fc_src_N_59146), + .I1(com_tlm_u_tlm_rx_fc_src_lnk_tfc_data_o_11_3_a2_i_0_0_11_39416_5294), + .I2(com_tlm_u_tlm_rx_fc_src_initFC_st[3]), + .I3(com_tlm_u_tlm_rx_fc_src_initFC_st[6]), + .LO(com_tlm_u_tlm_rx_fc_src_N_30262_i) + ); + defparam com_tlm_u_tlm_rx_fc_src_lnk_tfc_data_o_11_3_a2_i_0_0_10_.INIT = 16'h0004; + LUT4_L com_tlm_u_tlm_rx_fc_src_lnk_tfc_data_o_11_3_a2_i_0_0_10_ ( + .I0(com_tlm_u_tlm_rx_fc_src_N_59143), + .I1(com_tlm_u_tlm_rx_fc_src_lnk_tfc_data_o_11_3_a2_i_0_0_10_39403_5295), + .I2(com_tlm_u_tlm_rx_fc_src_initFC_st[3]), + .I3(com_tlm_u_tlm_rx_fc_src_initFC_st[6]), + .LO(com_tlm_u_tlm_rx_fc_src_N_30260_i) + ); + defparam com_tlm_u_tlm_rx_fc_src_lnk_tfc_data_o_11_i_0_0_0_9_.INIT = 16'h0004; + LUT4_L com_tlm_u_tlm_rx_fc_src_lnk_tfc_data_o_11_i_0_0_0_9_ ( + .I0(com_tlm_u_tlm_rx_fc_src_N_58761), + .I1(com_tlm_u_tlm_rx_fc_src_lnk_tfc_data_o_11_i_0_0_0_9_39398_5296), + .I2(com_tlm_u_tlm_rx_fc_src_initFC_st[3]), + .I3(com_tlm_u_tlm_rx_fc_src_initFC_st[6]), + .LO(com_tlm_u_tlm_rx_fc_src_N_20375_i) + ); + defparam com_tlm_u_tlm_rx_fc_src_lnk_tfc_data_o_11_i_0_0_0_8_.INIT = 16'h0004; + LUT4_L com_tlm_u_tlm_rx_fc_src_lnk_tfc_data_o_11_i_0_0_0_8_ ( + .I0(com_tlm_u_tlm_rx_fc_src_N_58758), + .I1(com_tlm_u_tlm_rx_fc_src_lnk_tfc_data_o_11_i_0_0_0_8_39399_5297), + .I2(com_tlm_u_tlm_rx_fc_src_initFC_st[3]), + .I3(com_tlm_u_tlm_rx_fc_src_initFC_st[6]), + .LO(com_tlm_u_tlm_rx_fc_src_N_20373_i) + ); + defparam com_tlm_u_tlm_rx_fc_src_lnk_tfc_data_o_11_i_0_0_0_7_.INIT = 16'h0004; + LUT4_L com_tlm_u_tlm_rx_fc_src_lnk_tfc_data_o_11_i_0_0_0_7_ ( + .I0(com_tlm_u_tlm_rx_fc_src_N_58755), + .I1(com_tlm_u_tlm_rx_fc_src_lnk_tfc_data_o_11_i_0_0_0_7_39400_5298), + .I2(com_tlm_u_tlm_rx_fc_src_initFC_st[3]), + .I3(com_tlm_u_tlm_rx_fc_src_initFC_st[6]), + .LO(com_tlm_u_tlm_rx_fc_src_N_20371_i) + ); + defparam com_tlm_u_tlm_rx_fc_src_lnk_tfc_data_o_11_i_0_0_0_6_.INIT = 16'h0004; + LUT4_L com_tlm_u_tlm_rx_fc_src_lnk_tfc_data_o_11_i_0_0_0_6_ ( + .I0(com_tlm_u_tlm_rx_fc_src_N_58752), + .I1(com_tlm_u_tlm_rx_fc_src_lnk_tfc_data_o_11_i_0_0_0_6_39401_5299), + .I2(com_tlm_u_tlm_rx_fc_src_initFC_st[3]), + .I3(com_tlm_u_tlm_rx_fc_src_initFC_st[6]), + .LO(com_tlm_u_tlm_rx_fc_src_N_20369_i) + ); + defparam com_tlm_u_tlm_rx_fc_src_lnk_tfc_data_o_11_i_0_0_0_5_.INIT = 16'h0004; + LUT4_L com_tlm_u_tlm_rx_fc_src_lnk_tfc_data_o_11_i_0_0_0_5_ ( + .I0(com_tlm_u_tlm_rx_fc_src_N_58749), + .I1(com_tlm_u_tlm_rx_fc_src_lnk_tfc_data_o_11_i_0_0_0_5_39402_5300), + .I2(com_tlm_u_tlm_rx_fc_src_initFC_st[3]), + .I3(com_tlm_u_tlm_rx_fc_src_initFC_st[6]), + .LO(com_tlm_u_tlm_rx_fc_src_N_20367_i) + ); + defparam com_tlm_u_tlm_rx_fc_src_lnk_tfc_data_o_11_3_a2_i_0_0_4_.INIT = 16'h0004; + LUT4_L com_tlm_u_tlm_rx_fc_src_lnk_tfc_data_o_11_3_a2_i_0_0_4_ ( + .I0(com_tlm_u_tlm_rx_fc_src_N_59140), + .I1(com_tlm_u_tlm_rx_fc_src_lnk_tfc_data_o_11_3_a2_i_0_0_4_39404_5301), + .I2(com_tlm_u_tlm_rx_fc_src_initFC_st[3]), + .I3(com_tlm_u_tlm_rx_fc_src_initFC_st[6]), + .LO(com_tlm_u_tlm_rx_fc_src_N_30258_i) + ); + defparam com_tlm_u_tlm_rx_fc_src_lnk_tfc_data_o_11_3_a2_i_0_0_3_.INIT = 16'h0004; + LUT4_L com_tlm_u_tlm_rx_fc_src_lnk_tfc_data_o_11_3_a2_i_0_0_3_ ( + .I0(com_tlm_u_tlm_rx_fc_src_N_59137), + .I1(com_tlm_u_tlm_rx_fc_src_lnk_tfc_data_o_11_3_a2_i_0_0_3_39405_5302), + .I2(com_tlm_u_tlm_rx_fc_src_initFC_st[3]), + .I3(com_tlm_u_tlm_rx_fc_src_initFC_st[6]), + .LO(com_tlm_u_tlm_rx_fc_src_N_30256_i) + ); + defparam com_tlm_u_tlm_rx_fc_src_lnk_tfc_data_o_11_3_a2_i_0_0_2_.INIT = 16'h0004; + LUT4_L com_tlm_u_tlm_rx_fc_src_lnk_tfc_data_o_11_3_a2_i_0_0_2_ ( + .I0(com_tlm_u_tlm_rx_fc_src_N_59134), + .I1(com_tlm_u_tlm_rx_fc_src_lnk_tfc_data_o_11_3_a2_i_0_0_2_39406_5303), + .I2(com_tlm_u_tlm_rx_fc_src_initFC_st[3]), + .I3(com_tlm_u_tlm_rx_fc_src_initFC_st[6]), + .LO(com_tlm_u_tlm_rx_fc_src_N_30254_i) + ); + defparam com_tlm_u_tlm_rx_fc_src_lnk_tfc_data_o_11_3_a2_i_0_0_1_.INIT = 16'h0004; + LUT4_L com_tlm_u_tlm_rx_fc_src_lnk_tfc_data_o_11_3_a2_i_0_0_1_ ( + .I0(com_tlm_u_tlm_rx_fc_src_N_59131), + .I1(com_tlm_u_tlm_rx_fc_src_lnk_tfc_data_o_11_3_a2_i_0_0_1_39407_5304), + .I2(com_tlm_u_tlm_rx_fc_src_initFC_st[3]), + .I3(com_tlm_u_tlm_rx_fc_src_initFC_st[6]), + .LO(com_tlm_u_tlm_rx_fc_src_N_30252_i) + ); + defparam com_tlm_u_tlm_rx_fc_src_lnk_tfc_data_o_11_3_a2_i_0_0_0_.INIT = 16'h0004; + LUT4_L com_tlm_u_tlm_rx_fc_src_lnk_tfc_data_o_11_3_a2_i_0_0_0_ ( + .I0(com_tlm_u_tlm_rx_fc_src_N_59128), + .I1(com_tlm_u_tlm_rx_fc_src_lnk_tfc_data_o_11_3_a2_i_0_0_0_39408_5305), + .I2(com_tlm_u_tlm_rx_fc_src_initFC_st[3]), + .I3(com_tlm_u_tlm_rx_fc_src_initFC_st[6]), + .LO(com_tlm_u_tlm_rx_fc_src_N_30250_i) + ); + defparam com_tlm_u_tlm_rx_fc_src_lnk_tfc_header_o_11_i_0_0_0_7_.INIT = 16'h0004; + LUT4_L com_tlm_u_tlm_rx_fc_src_lnk_tfc_header_o_11_i_0_0_0_7_ ( + .I0(com_tlm_u_tlm_rx_fc_src_N_58764), + .I1(com_tlm_u_tlm_rx_fc_src_lnk_tfc_header_o_11_i_0_0_0_7_39397_5306), + .I2(com_tlm_u_tlm_rx_fc_src_initFC_st[3]), + .I3(com_tlm_u_tlm_rx_fc_src_initFC_st[6]), + .LO(com_tlm_u_tlm_rx_fc_src_N_20386_i) + ); + defparam com_tlm_u_tlm_rx_fc_src_lnk_tfc_header_o_11_3_a2_i_0_0_6_.INIT = 16'h0004; + LUT4_L com_tlm_u_tlm_rx_fc_src_lnk_tfc_header_o_11_3_a2_i_0_0_6_ ( + .I0(com_tlm_u_tlm_rx_fc_src_N_59167), + .I1(com_tlm_u_tlm_rx_fc_src_lnk_tfc_header_o_11_3_a2_i_0_0_6_39409_5307), + .I2(com_tlm_u_tlm_rx_fc_src_initFC_st[3]), + .I3(com_tlm_u_tlm_rx_fc_src_initFC_st[6]), + .LO(com_tlm_u_tlm_rx_fc_src_N_30276_i) + ); + defparam com_tlm_u_tlm_rx_fc_src_lnk_tfc_header_o_11_3_a2_i_0_0_5_.INIT = 16'h0004; + LUT4_L com_tlm_u_tlm_rx_fc_src_lnk_tfc_header_o_11_3_a2_i_0_0_5_ ( + .I0(com_tlm_u_tlm_rx_fc_src_N_59164), + .I1(com_tlm_u_tlm_rx_fc_src_lnk_tfc_header_o_11_3_a2_i_0_0_5_39410_5308), + .I2(com_tlm_u_tlm_rx_fc_src_initFC_st[3]), + .I3(com_tlm_u_tlm_rx_fc_src_initFC_st[6]), + .LO(com_tlm_u_tlm_rx_fc_src_N_30274_i) + ); + defparam com_tlm_u_tlm_rx_fc_src_lnk_tfc_header_o_11_3_a2_i_0_0_4_.INIT = 16'h0004; + LUT4_L com_tlm_u_tlm_rx_fc_src_lnk_tfc_header_o_11_3_a2_i_0_0_4_ ( + .I0(com_tlm_u_tlm_rx_fc_src_N_59161), + .I1(com_tlm_u_tlm_rx_fc_src_lnk_tfc_header_o_11_3_a2_i_0_0_4_39411_5309), + .I2(com_tlm_u_tlm_rx_fc_src_initFC_st[3]), + .I3(com_tlm_u_tlm_rx_fc_src_initFC_st[6]), + .LO(com_tlm_u_tlm_rx_fc_src_N_30272_i) + ); + defparam com_tlm_u_tlm_rx_fc_src_lnk_tfc_header_o_11_3_a2_i_0_0_3_.INIT = 16'h0004; + LUT4_L com_tlm_u_tlm_rx_fc_src_lnk_tfc_header_o_11_3_a2_i_0_0_3_ ( + .I0(com_tlm_u_tlm_rx_fc_src_N_59158), + .I1(com_tlm_u_tlm_rx_fc_src_lnk_tfc_header_o_11_3_a2_i_0_0_3_39412_5310), + .I2(com_tlm_u_tlm_rx_fc_src_initFC_st[3]), + .I3(com_tlm_u_tlm_rx_fc_src_initFC_st[6]), + .LO(com_tlm_u_tlm_rx_fc_src_N_30270_i) + ); + defparam com_tlm_u_tlm_rx_fc_src_lnk_tfc_header_o_11_3_a2_i_0_0_2_.INIT = 16'h0004; + LUT4_L com_tlm_u_tlm_rx_fc_src_lnk_tfc_header_o_11_3_a2_i_0_0_2_ ( + .I0(com_tlm_u_tlm_rx_fc_src_N_59155), + .I1(com_tlm_u_tlm_rx_fc_src_lnk_tfc_header_o_11_3_a2_i_0_0_2_39413_5311), + .I2(com_tlm_u_tlm_rx_fc_src_initFC_st[3]), + .I3(com_tlm_u_tlm_rx_fc_src_initFC_st[6]), + .LO(com_tlm_u_tlm_rx_fc_src_N_30268_i) + ); + defparam com_tlm_u_tlm_rx_fc_src_lnk_tfc_header_o_11_3_a2_i_0_0_1_.INIT = 16'h0004; + LUT4_L com_tlm_u_tlm_rx_fc_src_lnk_tfc_header_o_11_3_a2_i_0_0_1_ ( + .I0(com_tlm_u_tlm_rx_fc_src_N_59152), + .I1(com_tlm_u_tlm_rx_fc_src_lnk_tfc_header_o_11_3_a2_i_0_0_1_39414_5312), + .I2(com_tlm_u_tlm_rx_fc_src_initFC_st[3]), + .I3(com_tlm_u_tlm_rx_fc_src_initFC_st[6]), + .LO(com_tlm_u_tlm_rx_fc_src_N_30266_i) + ); + defparam com_tlm_u_tlm_rx_fc_src_lnk_tfc_header_o_11_3_a2_i_0_0_0_.INIT = 16'h0004; + LUT4_L com_tlm_u_tlm_rx_fc_src_lnk_tfc_header_o_11_3_a2_i_0_0_0_ ( + .I0(com_tlm_u_tlm_rx_fc_src_N_59149), + .I1(com_tlm_u_tlm_rx_fc_src_lnk_tfc_header_o_11_3_a2_i_0_0_0_39415_5313), + .I2(com_tlm_u_tlm_rx_fc_src_initFC_st[3]), + .I3(com_tlm_u_tlm_rx_fc_src_initFC_st[6]), + .LO(com_tlm_u_tlm_rx_fc_src_N_30264_i) + ); + defparam com_tlm_u_tlm_rx_fc_src_un1_initFC_st_2_0_a2_0_a2_0_a2.INIT = 8'h01; + LUT3_L com_tlm_u_tlm_rx_fc_src_un1_initFC_st_2_0_a2_0_a2_0_a2 ( + .I0(com_tlm_u_tlm_rx_fc_src_initFC_st[1]), + .I1(com_tlm_u_tlm_rx_fc_src_initFC_st[2]), + .I2(com_tlm_u_tlm_rx_fc_src_initFC_st[3]), + .LO(com_tlm_u_tlm_rx_fc_src_un1_initFC_st_2_0_a2_0_a2_0_a2_5315) + ); + defparam com_tlm_u_tlm_rx_fc_src_N_55975_i_i.INIT = 4'hE; + LUT2_L com_tlm_u_tlm_rx_fc_src_N_55975_i_i ( + .I0(com_tlm_u_tlm_rx_fc_src_initFC_st[3]), + .I1(com_tlm_u_tlm_rx_fc_src_initFC_st[6]), + .LO(com_tlm_u_tlm_rx_fc_src_N_55975_i_i_5316) + ); + defparam com_tlm_u_tlm_rx_fc_src_N_87527_i.INIT = 4'hD; + LUT2_L com_tlm_u_tlm_rx_fc_src_N_87527_i ( + .I0(com_tlm_u_tlm_rx_fc_src_N_55891_i), + .I1(com_tlm_u_tlm_rx_fc_src_N_56217_i), + .LO(com_tlm_u_tlm_rx_fc_src_N_87527_i_5318) + ); + defparam com_tlm_u_tlm_rx_fc_src_lnk_tfc_src_rdy_o_7_f0_i_0_0_0.INIT = 16'hCF45; + LUT4_L com_tlm_u_tlm_rx_fc_src_lnk_tfc_src_rdy_o_7_f0_i_0_0_0 ( + .I0(com_tlm_u_tlm_rx_fc_src_N_56217_i), + .I1(com_tlm_u_tlm_rx_fc_src_N_56329_i), + .I2(com_lnk_tfc_sent_n), + .I3(com_tlm_u_tlm_rx_fc_src_np_vld_5314), + .LO(com_tlm_u_tlm_rx_fc_src_N_21949_i) + ); + FDE com_tlm_u_tlm_rx_fc_src_pd_11_ ( + .CE(com_tlm_u_tlm_rx_fc_send_state_0_sqmuxa), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_fc_req_pd[11]), + .Q(com_tlm_u_tlm_rx_fc_src_pd[11]) + ); + FDE com_tlm_u_tlm_rx_fc_src_pd_10_ ( + .CE(com_tlm_u_tlm_rx_fc_send_state_0_sqmuxa), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_fc_req_pd[10]), + .Q(com_tlm_u_tlm_rx_fc_src_pd[10]) + ); + FDE com_tlm_u_tlm_rx_fc_src_pd_9_ ( + .CE(com_tlm_u_tlm_rx_fc_send_state_0_sqmuxa), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_fc_req_pd[9]), + .Q(com_tlm_u_tlm_rx_fc_src_pd[9]) + ); + FDE com_tlm_u_tlm_rx_fc_src_pd_8_ ( + .CE(com_tlm_u_tlm_rx_fc_send_state_0_sqmuxa), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_fc_req_pd[8]), + .Q(com_tlm_u_tlm_rx_fc_src_pd[8]) + ); + FDE com_tlm_u_tlm_rx_fc_src_pd_7_ ( + .CE(com_tlm_u_tlm_rx_fc_send_state_0_sqmuxa), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_fc_req_pd[7]), + .Q(com_tlm_u_tlm_rx_fc_src_pd[7]) + ); + FDE com_tlm_u_tlm_rx_fc_src_pd_6_ ( + .CE(com_tlm_u_tlm_rx_fc_send_state_0_sqmuxa), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_fc_req_pd[6]), + .Q(com_tlm_u_tlm_rx_fc_src_pd[6]) + ); + FDE com_tlm_u_tlm_rx_fc_src_pd_5_ ( + .CE(com_tlm_u_tlm_rx_fc_send_state_0_sqmuxa), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_fc_req_pd[5]), + .Q(com_tlm_u_tlm_rx_fc_src_pd[5]) + ); + FDE com_tlm_u_tlm_rx_fc_src_pd_4_ ( + .CE(com_tlm_u_tlm_rx_fc_send_state_0_sqmuxa), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_fc_req_pd[4]), + .Q(com_tlm_u_tlm_rx_fc_src_pd[4]) + ); + FDE com_tlm_u_tlm_rx_fc_src_pd_3_ ( + .CE(com_tlm_u_tlm_rx_fc_send_state_0_sqmuxa), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_fc_req_pd[3]), + .Q(com_tlm_u_tlm_rx_fc_src_pd[3]) + ); + FDE com_tlm_u_tlm_rx_fc_src_pd_2_ ( + .CE(com_tlm_u_tlm_rx_fc_send_state_0_sqmuxa), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_fc_req_pd[2]), + .Q(com_tlm_u_tlm_rx_fc_src_pd[2]) + ); + FDE com_tlm_u_tlm_rx_fc_src_pd_1_ ( + .CE(com_tlm_u_tlm_rx_fc_send_state_0_sqmuxa), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_fc_req_pd[1]), + .Q(com_tlm_u_tlm_rx_fc_src_pd[1]) + ); + FDE com_tlm_u_tlm_rx_fc_src_pd_0_ ( + .CE(com_tlm_u_tlm_rx_fc_send_state_0_sqmuxa), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_fc_req_pd[0]), + .Q(com_tlm_u_tlm_rx_fc_src_pd[0]) + ); + FDE com_tlm_u_tlm_rx_fc_src_ph_7_ ( + .CE(com_tlm_u_tlm_rx_fc_send_state_0_sqmuxa), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_fc_req_ph[7]), + .Q(com_tlm_u_tlm_rx_fc_src_ph[7]) + ); + FDE com_tlm_u_tlm_rx_fc_src_ph_6_ ( + .CE(com_tlm_u_tlm_rx_fc_send_state_0_sqmuxa), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_fc_req_ph[6]), + .Q(com_tlm_u_tlm_rx_fc_src_ph[6]) + ); + FDE com_tlm_u_tlm_rx_fc_src_ph_5_ ( + .CE(com_tlm_u_tlm_rx_fc_send_state_0_sqmuxa), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_fc_req_ph[5]), + .Q(com_tlm_u_tlm_rx_fc_src_ph[5]) + ); + FDE com_tlm_u_tlm_rx_fc_src_ph_4_ ( + .CE(com_tlm_u_tlm_rx_fc_send_state_0_sqmuxa), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_fc_req_ph[4]), + .Q(com_tlm_u_tlm_rx_fc_src_ph[4]) + ); + FDE com_tlm_u_tlm_rx_fc_src_ph_3_ ( + .CE(com_tlm_u_tlm_rx_fc_send_state_0_sqmuxa), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_fc_req_ph[3]), + .Q(com_tlm_u_tlm_rx_fc_src_ph[3]) + ); + FDE com_tlm_u_tlm_rx_fc_src_ph_2_ ( + .CE(com_tlm_u_tlm_rx_fc_send_state_0_sqmuxa), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_fc_req_ph[2]), + .Q(com_tlm_u_tlm_rx_fc_src_ph[2]) + ); + FDE com_tlm_u_tlm_rx_fc_src_ph_1_ ( + .CE(com_tlm_u_tlm_rx_fc_send_state_0_sqmuxa), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_fc_req_ph[1]), + .Q(com_tlm_u_tlm_rx_fc_src_ph[1]) + ); + FDE com_tlm_u_tlm_rx_fc_src_ph_0_ ( + .CE(com_tlm_u_tlm_rx_fc_send_state_0_sqmuxa), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_fc_req_ph[0]), + .Q(com_tlm_u_tlm_rx_fc_src_ph[0]) + ); + FDE com_tlm_u_tlm_rx_fc_src_npd_11_ ( + .CE(com_tlm_u_tlm_rx_fc_send_state_0_sqmuxa_0), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_fc_req_npd[11]), + .Q(com_tlm_u_tlm_rx_fc_src_npd[11]) + ); + FDE com_tlm_u_tlm_rx_fc_src_npd_10_ ( + .CE(com_tlm_u_tlm_rx_fc_send_state_0_sqmuxa_0), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_fc_req_npd[10]), + .Q(com_tlm_u_tlm_rx_fc_src_npd[10]) + ); + FDE com_tlm_u_tlm_rx_fc_src_npd_9_ ( + .CE(com_tlm_u_tlm_rx_fc_send_state_0_sqmuxa_0), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_fc_req_npd[9]), + .Q(com_tlm_u_tlm_rx_fc_src_npd[9]) + ); + FDE com_tlm_u_tlm_rx_fc_src_npd_8_ ( + .CE(com_tlm_u_tlm_rx_fc_send_state_0_sqmuxa_0), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_fc_req_npd[8]), + .Q(com_tlm_u_tlm_rx_fc_src_npd[8]) + ); + FDE com_tlm_u_tlm_rx_fc_src_npd_7_ ( + .CE(com_tlm_u_tlm_rx_fc_send_state_0_sqmuxa_0), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_fc_req_npd[7]), + .Q(com_tlm_u_tlm_rx_fc_src_npd[7]) + ); + FDE com_tlm_u_tlm_rx_fc_src_npd_6_ ( + .CE(com_tlm_u_tlm_rx_fc_send_state_0_sqmuxa_0), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_fc_req_npd[6]), + .Q(com_tlm_u_tlm_rx_fc_src_npd[6]) + ); + FDE com_tlm_u_tlm_rx_fc_src_npd_5_ ( + .CE(com_tlm_u_tlm_rx_fc_send_state_0_sqmuxa_0), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_fc_req_npd[5]), + .Q(com_tlm_u_tlm_rx_fc_src_npd[5]) + ); + FDE com_tlm_u_tlm_rx_fc_src_npd_4_ ( + .CE(com_tlm_u_tlm_rx_fc_send_state_0_sqmuxa_0), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_fc_req_npd[4]), + .Q(com_tlm_u_tlm_rx_fc_src_npd[4]) + ); + FDE com_tlm_u_tlm_rx_fc_src_npd_3_ ( + .CE(com_tlm_u_tlm_rx_fc_send_state_0_sqmuxa_0), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_fc_req_npd[3]), + .Q(com_tlm_u_tlm_rx_fc_src_npd[3]) + ); + FDE com_tlm_u_tlm_rx_fc_src_npd_2_ ( + .CE(com_tlm_u_tlm_rx_fc_send_state_0_sqmuxa_0), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_fc_req_npd[2]), + .Q(com_tlm_u_tlm_rx_fc_src_npd[2]) + ); + FDE com_tlm_u_tlm_rx_fc_src_npd_1_ ( + .CE(com_tlm_u_tlm_rx_fc_send_state_0_sqmuxa_0), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_fc_req_npd[1]), + .Q(com_tlm_u_tlm_rx_fc_src_npd[1]) + ); + FDE com_tlm_u_tlm_rx_fc_src_npd_0_ ( + .CE(com_tlm_u_tlm_rx_fc_send_state_0_sqmuxa_0), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_fc_req_npd[0]), + .Q(com_tlm_u_tlm_rx_fc_src_npd[0]) + ); + FDE com_tlm_u_tlm_rx_fc_src_nph_7_ ( + .CE(com_tlm_u_tlm_rx_fc_send_state_0_sqmuxa_0), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_fc_req_nph[7]), + .Q(com_tlm_u_tlm_rx_fc_src_nph[7]) + ); + FDE com_tlm_u_tlm_rx_fc_src_nph_6_ ( + .CE(com_tlm_u_tlm_rx_fc_send_state_0_sqmuxa_0), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_fc_req_nph[6]), + .Q(com_tlm_u_tlm_rx_fc_src_nph[6]) + ); + FDE com_tlm_u_tlm_rx_fc_src_nph_5_ ( + .CE(com_tlm_u_tlm_rx_fc_send_state_0_sqmuxa_0), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_fc_req_nph[5]), + .Q(com_tlm_u_tlm_rx_fc_src_nph[5]) + ); + FDE com_tlm_u_tlm_rx_fc_src_nph_4_ ( + .CE(com_tlm_u_tlm_rx_fc_send_state_0_sqmuxa_0), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_fc_req_nph[4]), + .Q(com_tlm_u_tlm_rx_fc_src_nph[4]) + ); + FDE com_tlm_u_tlm_rx_fc_src_nph_3_ ( + .CE(com_tlm_u_tlm_rx_fc_send_state_0_sqmuxa_0), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_fc_req_nph[3]), + .Q(com_tlm_u_tlm_rx_fc_src_nph[3]) + ); + FDE com_tlm_u_tlm_rx_fc_src_nph_2_ ( + .CE(com_tlm_u_tlm_rx_fc_send_state_0_sqmuxa_0), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_fc_req_nph[2]), + .Q(com_tlm_u_tlm_rx_fc_src_nph[2]) + ); + FDE com_tlm_u_tlm_rx_fc_src_nph_1_ ( + .CE(com_tlm_u_tlm_rx_fc_send_state_0_sqmuxa_0), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_fc_req_nph[1]), + .Q(com_tlm_u_tlm_rx_fc_src_nph[1]) + ); + FDE com_tlm_u_tlm_rx_fc_src_nph_0_ ( + .CE(com_tlm_u_tlm_rx_fc_send_state_0_sqmuxa_0), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_fc_req_nph[0]), + .Q(com_tlm_u_tlm_rx_fc_src_nph[0]) + ); + FDE com_tlm_u_tlm_rx_fc_src_lnk_tfc_data_o_1_11_ ( + .CE(com_tlm_u_tlm_rx_fc_src_N_58788_i_5317), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_fc_src_N_30262_i), + .Q(com_lnk_tfc_data[11]) + ); + FDE com_tlm_u_tlm_rx_fc_src_lnk_tfc_data_o_1_10_ ( + .CE(com_tlm_u_tlm_rx_fc_src_N_58788_i_5317), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_fc_src_N_30260_i), + .Q(com_lnk_tfc_data[10]) + ); + FDE com_tlm_u_tlm_rx_fc_src_lnk_tfc_data_o_1_9_ ( + .CE(com_tlm_u_tlm_rx_fc_src_N_58788_i_5317), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_fc_src_N_20375_i), + .Q(com_lnk_tfc_data[9]) + ); + FDE com_tlm_u_tlm_rx_fc_src_lnk_tfc_data_o_1_8_ ( + .CE(com_tlm_u_tlm_rx_fc_src_N_58788_i_5317), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_fc_src_N_20373_i), + .Q(com_lnk_tfc_data[8]) + ); + FDE com_tlm_u_tlm_rx_fc_src_lnk_tfc_data_o_1_7_ ( + .CE(com_tlm_u_tlm_rx_fc_src_N_58788_i_5317), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_fc_src_N_20371_i), + .Q(com_lnk_tfc_data[7]) + ); + FDE com_tlm_u_tlm_rx_fc_src_lnk_tfc_data_o_1_6_ ( + .CE(com_tlm_u_tlm_rx_fc_src_N_58788_i_5317), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_fc_src_N_20369_i), + .Q(com_lnk_tfc_data[6]) + ); + FDE com_tlm_u_tlm_rx_fc_src_lnk_tfc_data_o_1_5_ ( + .CE(com_tlm_u_tlm_rx_fc_src_N_58788_i_5317), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_fc_src_N_20367_i), + .Q(com_lnk_tfc_data[5]) + ); + FDE com_tlm_u_tlm_rx_fc_src_lnk_tfc_data_o_1_4_ ( + .CE(com_tlm_u_tlm_rx_fc_src_N_58788_i_5317), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_fc_src_N_30258_i), + .Q(com_lnk_tfc_data[4]) + ); + FDE com_tlm_u_tlm_rx_fc_src_lnk_tfc_data_o_1_3_ ( + .CE(com_tlm_u_tlm_rx_fc_src_N_58788_i_5317), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_fc_src_N_30256_i), + .Q(com_lnk_tfc_data[3]) + ); + FDE com_tlm_u_tlm_rx_fc_src_lnk_tfc_data_o_1_2_ ( + .CE(com_tlm_u_tlm_rx_fc_src_N_58788_i_5317), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_fc_src_N_30254_i), + .Q(com_lnk_tfc_data[2]) + ); + FDE com_tlm_u_tlm_rx_fc_src_lnk_tfc_data_o_1_1_ ( + .CE(com_tlm_u_tlm_rx_fc_src_N_58788_i_5317), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_fc_src_N_30252_i), + .Q(com_lnk_tfc_data[1]) + ); + FDE com_tlm_u_tlm_rx_fc_src_lnk_tfc_data_o_1_0_ ( + .CE(com_tlm_u_tlm_rx_fc_src_N_58788_i_5317), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_fc_src_N_30250_i), + .Q(com_lnk_tfc_data[0]) + ); + FDE com_tlm_u_tlm_rx_fc_src_lnk_tfc_header_o_1_7_ ( + .CE(com_tlm_u_tlm_rx_fc_src_N_58788_i_5317), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_fc_src_N_20386_i), + .Q(com_lnk_tfc_header[7]) + ); + FDE com_tlm_u_tlm_rx_fc_src_lnk_tfc_header_o_1_6_ ( + .CE(com_tlm_u_tlm_rx_fc_src_N_58788_i_5317), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_fc_src_N_30276_i), + .Q(com_lnk_tfc_header[6]) + ); + FDE com_tlm_u_tlm_rx_fc_src_lnk_tfc_header_o_1_5_ ( + .CE(com_tlm_u_tlm_rx_fc_src_N_58788_i_5317), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_fc_src_N_30274_i), + .Q(com_lnk_tfc_header[5]) + ); + FDE com_tlm_u_tlm_rx_fc_src_lnk_tfc_header_o_1_4_ ( + .CE(com_tlm_u_tlm_rx_fc_src_N_58788_i_5317), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_fc_src_N_30272_i), + .Q(com_lnk_tfc_header[4]) + ); + FDE com_tlm_u_tlm_rx_fc_src_lnk_tfc_header_o_1_3_ ( + .CE(com_tlm_u_tlm_rx_fc_src_N_58788_i_5317), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_fc_src_N_30270_i), + .Q(com_lnk_tfc_header[3]) + ); + FDE com_tlm_u_tlm_rx_fc_src_lnk_tfc_header_o_1_2_ ( + .CE(com_tlm_u_tlm_rx_fc_src_N_58788_i_5317), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_fc_src_N_30268_i), + .Q(com_lnk_tfc_header[2]) + ); + FDE com_tlm_u_tlm_rx_fc_src_lnk_tfc_header_o_1_1_ ( + .CE(com_tlm_u_tlm_rx_fc_src_N_58788_i_5317), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_fc_src_N_30266_i), + .Q(com_lnk_tfc_header[1]) + ); + FDE com_tlm_u_tlm_rx_fc_src_lnk_tfc_header_o_1_0_ ( + .CE(com_tlm_u_tlm_rx_fc_src_N_58788_i_5317), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_fc_src_N_30264_i), + .Q(com_lnk_tfc_header[0]) + ); + FDE com_tlm_u_tlm_rx_fc_src_lnk_tfc_type_o_1_3_ ( + .CE(com_tlm_u_tlm_rx_fc_src_N_58788_i_5317), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_fc_src_un1_initFC_st_2_0_a2_0_a2_0_a2_5315), + .Q(com_lnk_tfc_type[3]) + ); + FDE com_tlm_u_tlm_rx_fc_src_lnk_tfc_type_o_1_2_ ( + .CE(com_tlm_u_tlm_rx_fc_src_N_58788_i_5317), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_fc_src_initFC_st_i[0]), + .Q(com_lnk_tfc_type[2]) + ); + FDE com_tlm_u_tlm_rx_fc_src_lnk_tfc_type_o_1_1_ ( + .CE(com_tlm_u_tlm_rx_fc_src_N_58788_i_5317), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_fc_src_N_55975_i_i_5316), + .Q(com_lnk_tfc_type[1]) + ); + FDE com_tlm_u_tlm_rx_fc_src_lnk_tfc_type_o_1_0_ ( + .CE(com_tlm_u_tlm_rx_fc_src_N_58788_i_5317), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_tlm_u_tlm_rx_fc_src_N_87527_i_5318), + .Q(com_lnk_tfc_type[0]) + ); + INV com_tlm_u_tlm_rx_fc_src_initFC_st_i_0_ ( + .I(com_tlm_u_tlm_rx_fc_src_initFC_st[0]), + .O(com_tlm_u_tlm_rx_fc_src_initFC_st_i[0]) + ); + VCC com_cmm_VCC ( + .P(com_cmm_VCC_5319) + ); + GND com_cmm_GND ( + .G(com_cmm_GND_5320) + ); + FDS com_cmm_rst ( + .C(NlwRenamedSig_OI_trn_clk), + .D(trn_reset_n_i), + .Q(com_cmm_rst_351), + .S(plm_link_up_i) + ); + INV com_cmm_rst_i ( + .I(com_cmm_rst_351), + .O(com_cmm_rst_i_5321) + ); + INV com_cmm_cfg_intr_rdy_i ( + .I(com_cmm_cfg_intr_rdy), + .O(cfg_interrupt_rdy_n) + ); + VCC com_cmm_u_cmm_intr_VCC ( + .P(com_cmm_u_cmm_intr_VCC_5345) + ); + GND com_cmm_u_cmm_intr_GND ( + .G(com_cmm_u_cmm_intr_GND_5344) + ); + MUXCY_L com_cmm_u_cmm_intr_un5_msi_64_0 ( + .CI(com_cmm_u_cmm_intr_VCC_5345), + .DI(com_cmm_u_cmm_intr_GND_5344), + .LO(com_cmm_u_cmm_intr_un5_msi_64_0_5322), + .S(com_cmm_u_cmm_intr_un5_msi_64_0_and_5343) + ); + MUXCY_L com_cmm_u_cmm_intr_un5_msi_64_1 ( + .CI(com_cmm_u_cmm_intr_un5_msi_64_0_5322), + .DI(com_cmm_u_cmm_intr_GND_5344), + .LO(com_cmm_u_cmm_intr_un5_msi_64_1_5323), + .S(com_cmm_u_cmm_intr_un5_msi_64_1_and_5342) + ); + MUXCY_L com_cmm_u_cmm_intr_un5_msi_64_2 ( + .CI(com_cmm_u_cmm_intr_un5_msi_64_1_5323), + .DI(com_cmm_u_cmm_intr_GND_5344), + .LO(com_cmm_u_cmm_intr_un5_msi_64_2_5324), + .S(com_cmm_u_cmm_intr_un5_msi_64_2_and_5341) + ); + MUXCY_L com_cmm_u_cmm_intr_un5_msi_64_3 ( + .CI(com_cmm_u_cmm_intr_un5_msi_64_2_5324), + .DI(com_cmm_u_cmm_intr_GND_5344), + .LO(com_cmm_u_cmm_intr_un5_msi_64_3_5325), + .S(com_cmm_u_cmm_intr_un5_msi_64_3_and_5340) + ); + MUXCY_L com_cmm_u_cmm_intr_un5_msi_64_4 ( + .CI(com_cmm_u_cmm_intr_un5_msi_64_3_5325), + .DI(com_cmm_u_cmm_intr_GND_5344), + .LO(com_cmm_u_cmm_intr_un5_msi_64_4_5326), + .S(com_cmm_u_cmm_intr_un5_msi_64_4_and_5339) + ); + MUXCY_L com_cmm_u_cmm_intr_un5_msi_64_5 ( + .CI(com_cmm_u_cmm_intr_un5_msi_64_4_5326), + .DI(com_cmm_u_cmm_intr_GND_5344), + .LO(com_cmm_u_cmm_intr_un5_msi_64_5_5327), + .S(com_cmm_u_cmm_intr_un5_msi_64_5_and_5338) + ); + MUXCY_L com_cmm_u_cmm_intr_un5_msi_64_6 ( + .CI(com_cmm_u_cmm_intr_un5_msi_64_5_5327), + .DI(com_cmm_u_cmm_intr_GND_5344), + .LO(com_cmm_u_cmm_intr_un5_msi_64_6_5328), + .S(com_cmm_u_cmm_intr_un5_msi_64_6_and_5337) + ); + MUXCY com_cmm_u_cmm_intr_un5_msi_64_7 ( + .CI(com_cmm_u_cmm_intr_un5_msi_64_6_5328), + .DI(com_cmm_u_cmm_intr_GND_5344), + .O(com_cmm_u_cmm_intr_un5_msi_64_7_5329), + .S(com_cmm_u_cmm_intr_un5_msi_64_7_and_5336) + ); + defparam com_cmm_u_cmm_intr_signaledint_0_a2.INIT = 4'h8; + LUT2 com_cmm_u_cmm_intr_signaledint_0_a2 ( + .I0(com_cmm_gnt_intr), + .I1(com_cmm_u_cmm_intr_state[2]), + .O(com_cmm_signaledint) + ); + defparam com_cmm_u_cmm_intr_un1_intr_rdy_0_a2.INIT = 4'h4; + LUT2 com_cmm_u_cmm_intr_un1_intr_rdy_0_a2 ( + .I0(com_cmm_req_intr), + .I1(com_cmm_u_cmm_intr_state[0]), + .O(com_cmm_cfg_intr_rdy) + ); + defparam com_cmm_u_cmm_intr_next_state_0_i_a2_0_1_3_.INIT = 4'h8; + LUT2 com_cmm_u_cmm_intr_next_state_0_i_a2_0_1_3_ ( + .I0(com_cmm_u_cmm_intr_intr_req_q_5335), + .I1(com_cmm_u_cmm_intr_state[0]), + .O(com_cmm_u_cmm_intr_N_124_1) + ); + defparam com_cmm_u_cmm_intr_next_state_0_i_a2_0_0_2_.INIT = 4'h4; + LUT2 com_cmm_u_cmm_intr_next_state_0_i_a2_0_0_2_ ( + .I0(com_cmm_u_cmm_intr_intr_req_q_5335), + .I1(com_cmm_u_cmm_intr_state[0]), + .O(com_cmm_u_cmm_intr_next_state_0_i_a2_0_0[2]) + ); + defparam com_cmm_u_cmm_intr_next_state_i_m3_i_o2_0_.INIT = 8'h01; + LUT3 com_cmm_u_cmm_intr_next_state_i_m3_i_o2_0_ ( + .I0(com_cmm_u_cmm_intr_state[1]), + .I1(com_cmm_u_cmm_intr_state[2]), + .I2(com_cmm_u_cmm_intr_state[3]), + .O(com_cmm_u_cmm_intr_next_state_i_m3_i_o2[0]) + ); + defparam com_cmm_u_cmm_intr_next_state_0_i_a2_0_0_3_.INIT = 4'h2; + LUT2 com_cmm_u_cmm_intr_next_state_0_i_a2_0_0_3_ ( + .I0(com_cmm_u_cmm_intr_N_124_1), + .I1(com_cmm_msi_control_1[0]), + .O(com_cmm_u_cmm_intr_next_state_0_i_a2_0_0[3]) + ); + defparam com_cmm_u_cmm_intr_intr_req.INIT = 16'h4405; + LUT4 com_cmm_u_cmm_intr_intr_req ( + .I0(cfg_interrupt_n), + .I1(NlwRenamedSig_OI_cfg_command_2_), + .I2(NlwRenamedSig_OI_cfg_command_10_), + .I3(com_cmm_msi_control_1[0]), + .O(com_cmm_u_cmm_intr_intr_req_5334) + ); + defparam com_cmm_u_cmm_intr_next_state_i_m3_i_o2_0_0_.INIT = 4'h2; + LUT2 com_cmm_u_cmm_intr_next_state_i_m3_i_o2_0_0_ ( + .I0(com_cmm_u_cmm_intr_intr_req_5334), + .I1(com_cmm_msi_control_1[0]), + .O(com_cmm_u_cmm_intr_N_114_i) + ); + defparam com_cmm_u_cmm_intr_state_i_0_.INIT = 4'h1; + LUT1_L com_cmm_u_cmm_intr_state_i_0_ ( + .I0(com_cmm_u_cmm_intr_state[0]), + .LO(com_cmm_u_cmm_intr_state_i[0]) + ); + defparam com_cmm_u_cmm_intr_N_239_i.INIT = 16'h7530; + LUT4_L com_cmm_u_cmm_intr_N_239_i ( + .I0(com_cmm_gnt_intr), + .I1(com_cmm_u_cmm_intr_intr_req_5334), + .I2(com_cmm_u_cmm_intr_next_state_0_i_a2_0_0[3]), + .I3(com_cmm_u_cmm_intr_state[3]), + .LO(com_cmm_u_cmm_intr_N_239_i_5330) + ); + defparam com_cmm_u_cmm_intr_N_238_i.INIT = 16'hB3A0; + LUT4_L com_cmm_u_cmm_intr_N_238_i ( + .I0(com_cmm_u_cmm_intr_N_114_i), + .I1(com_cmm_gnt_intr), + .I2(com_cmm_u_cmm_intr_next_state_0_i_a2_0_0[2]), + .I3(com_cmm_u_cmm_intr_state[2]), + .LO(com_cmm_u_cmm_intr_N_238_i_5331) + ); + defparam com_cmm_u_cmm_intr_N_237_i.INIT = 16'hB3A0; + LUT4_L com_cmm_u_cmm_intr_N_237_i ( + .I0(com_cmm_u_cmm_intr_N_124_1), + .I1(com_cmm_gnt_intr), + .I2(com_cmm_msi_control_1[0]), + .I3(com_cmm_u_cmm_intr_state[1]), + .LO(com_cmm_u_cmm_intr_N_237_i_5332) + ); + defparam com_cmm_u_cmm_intr_next_state_i_m3_i_m2_0_.INIT = 16'hB874; + LUT4_L com_cmm_u_cmm_intr_next_state_i_m3_i_m2_0_ ( + .I0(com_cmm_u_cmm_intr_N_114_i), + .I1(com_cmm_u_cmm_intr_next_state_i_m3_i_o2[0]), + .I2(com_cmm_gnt_intr), + .I3(com_cmm_u_cmm_intr_intr_req_q_5335), + .LO(com_cmm_u_cmm_intr_next_state_i_m3_i_m2[0]) + ); + defparam com_cmm_u_cmm_intr_N_240_i.INIT = 16'hF0F8; + LUT4_L com_cmm_u_cmm_intr_N_240_i ( + .I0(com_cmm_VCC_5319), + .I1(com_cmm_u_cmm_intr_state[1]), + .I2(com_cmm_u_cmm_intr_state[3]), + .I3(com_cmm_u_cmm_intr_un5_msi_64_7_5329), + .LO(com_cmm_u_cmm_intr_N_240_i_5333) + ); + FDC com_cmm_u_cmm_intr_intr_req_valid ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_intr_state_i[0]), + .Q(com_cmm_req_intr), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_intr_state_3_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_intr_N_239_i_5330), + .Q(com_cmm_u_cmm_intr_state[3]), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_intr_state_2_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_intr_N_238_i_5331), + .Q(com_cmm_u_cmm_intr_state[2]), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_intr_state_1_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_intr_N_237_i_5332), + .Q(com_cmm_u_cmm_intr_state[1]), + .CLR(com_cmm_rst_351) + ); + FDP com_cmm_u_cmm_intr_state_0_ ( + .PRE(com_cmm_rst_351), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_intr_next_state_i_m3_i_m2[0]), + .Q(com_cmm_u_cmm_intr_state[0]) + ); + FDC com_cmm_u_cmm_intr_intr_req_type_1_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_intr_state[1]), + .Q(com_cmm_intr_req_type[1]), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_intr_intr_req_type_0_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_intr_N_240_i_5333), + .Q(com_cmm_intr_req_type[0]), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_intr_intr_req_q ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_intr_intr_req_5334), + .Q(com_cmm_u_cmm_intr_intr_req_q_5335), + .CLR(com_cmm_rst_351) + ); + defparam com_cmm_u_cmm_intr_un5_msi_64_7_and.INIT = 16'h0001; + LUT4 com_cmm_u_cmm_intr_un5_msi_64_7_and ( + .I0(com_cmm_msi_haddr[28]), + .I1(com_cmm_msi_haddr[29]), + .I2(com_cmm_msi_haddr[30]), + .I3(com_cmm_msi_haddr[31]), + .O(com_cmm_u_cmm_intr_un5_msi_64_7_and_5336) + ); + defparam com_cmm_u_cmm_intr_un5_msi_64_6_and.INIT = 16'h0001; + LUT4 com_cmm_u_cmm_intr_un5_msi_64_6_and ( + .I0(com_cmm_msi_haddr[24]), + .I1(com_cmm_msi_haddr[25]), + .I2(com_cmm_msi_haddr[26]), + .I3(com_cmm_msi_haddr[27]), + .O(com_cmm_u_cmm_intr_un5_msi_64_6_and_5337) + ); + defparam com_cmm_u_cmm_intr_un5_msi_64_5_and.INIT = 16'h0001; + LUT4 com_cmm_u_cmm_intr_un5_msi_64_5_and ( + .I0(com_cmm_msi_haddr[20]), + .I1(com_cmm_msi_haddr[21]), + .I2(com_cmm_msi_haddr[22]), + .I3(com_cmm_msi_haddr[23]), + .O(com_cmm_u_cmm_intr_un5_msi_64_5_and_5338) + ); + defparam com_cmm_u_cmm_intr_un5_msi_64_4_and.INIT = 16'h0001; + LUT4 com_cmm_u_cmm_intr_un5_msi_64_4_and ( + .I0(com_cmm_msi_haddr[16]), + .I1(com_cmm_msi_haddr[17]), + .I2(com_cmm_msi_haddr[18]), + .I3(com_cmm_msi_haddr[19]), + .O(com_cmm_u_cmm_intr_un5_msi_64_4_and_5339) + ); + defparam com_cmm_u_cmm_intr_un5_msi_64_3_and.INIT = 16'h0001; + LUT4 com_cmm_u_cmm_intr_un5_msi_64_3_and ( + .I0(com_cmm_msi_haddr[12]), + .I1(com_cmm_msi_haddr[13]), + .I2(com_cmm_msi_haddr[14]), + .I3(com_cmm_msi_haddr[15]), + .O(com_cmm_u_cmm_intr_un5_msi_64_3_and_5340) + ); + defparam com_cmm_u_cmm_intr_un5_msi_64_2_and.INIT = 16'h0001; + LUT4 com_cmm_u_cmm_intr_un5_msi_64_2_and ( + .I0(com_cmm_msi_haddr[8]), + .I1(com_cmm_msi_haddr[9]), + .I2(com_cmm_msi_haddr[10]), + .I3(com_cmm_msi_haddr[11]), + .O(com_cmm_u_cmm_intr_un5_msi_64_2_and_5341) + ); + defparam com_cmm_u_cmm_intr_un5_msi_64_1_and.INIT = 16'h0001; + LUT4 com_cmm_u_cmm_intr_un5_msi_64_1_and ( + .I0(com_cmm_msi_haddr[4]), + .I1(com_cmm_msi_haddr[5]), + .I2(com_cmm_msi_haddr[6]), + .I3(com_cmm_msi_haddr[7]), + .O(com_cmm_u_cmm_intr_un5_msi_64_1_and_5342) + ); + defparam com_cmm_u_cmm_intr_un5_msi_64_0_and.INIT = 16'h0001; + LUT4 com_cmm_u_cmm_intr_un5_msi_64_0_and ( + .I0(com_cmm_msi_haddr[0]), + .I1(com_cmm_msi_haddr[1]), + .I2(com_cmm_msi_haddr[2]), + .I3(com_cmm_msi_haddr[3]), + .O(com_cmm_u_cmm_intr_un5_msi_64_0_and_5343) + ); + FDRE com_cmm_u_rx_pkt_proc_bdf_err_rd_pack ( + .CE(com_cmm_u_rx_pkt_proc_dw1_enable), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_rx_pkt_proc_N_85975_i_5353), + .Q(com_cmm_bdf_err_rd_pack), + .R(com_cmm_rst_351) + ); + FDRE com_cmm_u_rx_pkt_proc_posnd_wr_pack ( + .CE(com_cmm_u_rx_pkt_proc_N_19513_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_rx_pkt_proc_N_85914_i_5351), + .Q(com_cmm_posnd_wr_pack), + .R(com_cmm_rst_351) + ); + FDRE com_cmm_u_rx_pkt_proc_device_0_ ( + .CE(com_cmm_u_rx_pkt_proc_un1_dw1_enable_2_0_a2_0_a2_0_a2_5347), + .C(NlwRenamedSig_OI_trn_clk), + .D(NlwRenamedSig_OI_trn_rd[51]), + .Q(NlwRenamedSig_OI_cfg_device_number[0]), + .R(com_cmm_rst_351) + ); + FDRE com_cmm_u_rx_pkt_proc_device_1_ ( + .CE(com_cmm_u_rx_pkt_proc_un1_dw1_enable_2_0_a2_0_a2_0_a2_5347), + .C(NlwRenamedSig_OI_trn_clk), + .D(NlwRenamedSig_OI_trn_rd[52]), + .Q(NlwRenamedSig_OI_cfg_device_number[1]), + .R(com_cmm_rst_351) + ); + FDRE com_cmm_u_rx_pkt_proc_device_2_ ( + .CE(com_cmm_u_rx_pkt_proc_un1_dw1_enable_2_0_a2_0_a2_0_a2_5347), + .C(NlwRenamedSig_OI_trn_clk), + .D(NlwRenamedSig_OI_trn_rd[53]), + .Q(NlwRenamedSig_OI_cfg_device_number[2]), + .R(com_cmm_rst_351) + ); + FDRE com_cmm_u_rx_pkt_proc_device_3_ ( + .CE(com_cmm_u_rx_pkt_proc_un1_dw1_enable_2_0_a2_0_a2_0_a2_5347), + .C(NlwRenamedSig_OI_trn_clk), + .D(NlwRenamedSig_OI_trn_rd[54]), + .Q(NlwRenamedSig_OI_cfg_device_number[3]), + .R(com_cmm_rst_351) + ); + FDRE com_cmm_u_rx_pkt_proc_device_4_ ( + .CE(com_cmm_u_rx_pkt_proc_un1_dw1_enable_2_0_a2_0_a2_0_a2_5347), + .C(NlwRenamedSig_OI_trn_clk), + .D(NlwRenamedSig_OI_trn_rd[55]), + .Q(NlwRenamedSig_OI_cfg_device_number[4]), + .R(com_cmm_rst_351) + ); + FDRE com_cmm_u_rx_pkt_proc_bus_0_ ( + .CE(com_cmm_u_rx_pkt_proc_un1_dw1_enable_2_0_a2_0_a2_0_a2_5347), + .C(NlwRenamedSig_OI_trn_clk), + .D(NlwRenamedSig_OI_trn_rd[56]), + .Q(NlwRenamedSig_OI_cfg_bus_number[0]), + .R(com_cmm_rst_351) + ); + FDRE com_cmm_u_rx_pkt_proc_bus_1_ ( + .CE(com_cmm_u_rx_pkt_proc_un1_dw1_enable_2_0_a2_0_a2_0_a2_5347), + .C(NlwRenamedSig_OI_trn_clk), + .D(NlwRenamedSig_OI_trn_rd[57]), + .Q(NlwRenamedSig_OI_cfg_bus_number[1]), + .R(com_cmm_rst_351) + ); + FDRE com_cmm_u_rx_pkt_proc_bus_2_ ( + .CE(com_cmm_u_rx_pkt_proc_un1_dw1_enable_2_0_a2_0_a2_0_a2_5347), + .C(NlwRenamedSig_OI_trn_clk), + .D(NlwRenamedSig_OI_trn_rd[58]), + .Q(NlwRenamedSig_OI_cfg_bus_number[2]), + .R(com_cmm_rst_351) + ); + FDRE com_cmm_u_rx_pkt_proc_bus_3_ ( + .CE(com_cmm_u_rx_pkt_proc_un1_dw1_enable_2_0_a2_0_a2_0_a2_5347), + .C(NlwRenamedSig_OI_trn_clk), + .D(NlwRenamedSig_OI_trn_rd[59]), + .Q(NlwRenamedSig_OI_cfg_bus_number[3]), + .R(com_cmm_rst_351) + ); + FDRE com_cmm_u_rx_pkt_proc_bus_4_ ( + .CE(com_cmm_u_rx_pkt_proc_un1_dw1_enable_2_0_a2_0_a2_0_a2_5347), + .C(NlwRenamedSig_OI_trn_clk), + .D(NlwRenamedSig_OI_trn_rd[60]), + .Q(NlwRenamedSig_OI_cfg_bus_number[4]), + .R(com_cmm_rst_351) + ); + FDRE com_cmm_u_rx_pkt_proc_bus_5_ ( + .CE(com_cmm_u_rx_pkt_proc_un1_dw1_enable_2_0_a2_0_a2_0_a2_5347), + .C(NlwRenamedSig_OI_trn_clk), + .D(NlwRenamedSig_OI_trn_rd[61]), + .Q(NlwRenamedSig_OI_cfg_bus_number[5]), + .R(com_cmm_rst_351) + ); + FDRE com_cmm_u_rx_pkt_proc_bus_6_ ( + .CE(com_cmm_u_rx_pkt_proc_un1_dw1_enable_2_0_a2_0_a2_0_a2_5347), + .C(NlwRenamedSig_OI_trn_clk), + .D(NlwRenamedSig_OI_trn_rd[62]), + .Q(NlwRenamedSig_OI_cfg_bus_number[6]), + .R(com_cmm_rst_351) + ); + FDRE com_cmm_u_rx_pkt_proc_bus_7_ ( + .CE(com_cmm_u_rx_pkt_proc_un1_dw1_enable_2_0_a2_0_a2_0_a2_5347), + .C(NlwRenamedSig_OI_trn_clk), + .D(NlwRenamedSig_OI_trn_rd[63]), + .Q(NlwRenamedSig_OI_cfg_bus_number[7]), + .R(com_cmm_rst_351) + ); + FDRE com_cmm_u_rx_pkt_proc_type1_type0_bar ( + .CE(com_cmm_u_rx_pkt_proc_idle_enable), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_rx_pkt_proc_type1_type0_bar_3), + .Q(com_cmm_type1_type0_bar), + .R(com_cmm_rst_351) + ); + FDRE com_cmm_u_rx_pkt_proc_cfg_wr ( + .CE(com_cmm_u_rx_pkt_proc_idle_enable), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_rx_pkt_proc_cfg_wr_3), + .Q(com_cmm_cfg_wr), + .R(com_cmm_rst_351) + ); + FDRE com_cmm_u_rx_pkt_proc_cfg_rd ( + .CE(com_cmm_u_rx_pkt_proc_idle_enable), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_rx_pkt_proc_cfg_rd_3), + .Q(com_cmm_cfg_rd), + .R(com_cmm_rst_351) + ); + FDRE com_cmm_u_rx_pkt_proc_tag_0_ ( + .CE(com_cmm_u_rx_pkt_proc_idle_enable), + .C(NlwRenamedSig_OI_trn_clk), + .D(NlwRenamedSig_OI_trn_rd[8]), + .Q(com_cmm_tag[0]), + .R(com_cmm_rst_351) + ); + FDRE com_cmm_u_rx_pkt_proc_tag_1_ ( + .CE(com_cmm_u_rx_pkt_proc_idle_enable), + .C(NlwRenamedSig_OI_trn_clk), + .D(NlwRenamedSig_OI_trn_rd[9]), + .Q(com_cmm_tag[1]), + .R(com_cmm_rst_351) + ); + FDRE com_cmm_u_rx_pkt_proc_tag_2_ ( + .CE(com_cmm_u_rx_pkt_proc_idle_enable), + .C(NlwRenamedSig_OI_trn_clk), + .D(NlwRenamedSig_OI_trn_rd[10]), + .Q(com_cmm_tag[2]), + .R(com_cmm_rst_351) + ); + FDRE com_cmm_u_rx_pkt_proc_tag_3_ ( + .CE(com_cmm_u_rx_pkt_proc_idle_enable), + .C(NlwRenamedSig_OI_trn_clk), + .D(NlwRenamedSig_OI_trn_rd[11]), + .Q(com_cmm_tag[3]), + .R(com_cmm_rst_351) + ); + FDRE com_cmm_u_rx_pkt_proc_tag_4_ ( + .CE(com_cmm_u_rx_pkt_proc_idle_enable), + .C(NlwRenamedSig_OI_trn_clk), + .D(NlwRenamedSig_OI_trn_rd[12]), + .Q(com_cmm_tag[4]), + .R(com_cmm_rst_351) + ); + FDRE com_cmm_u_rx_pkt_proc_tag_5_ ( + .CE(com_cmm_u_rx_pkt_proc_idle_enable), + .C(NlwRenamedSig_OI_trn_clk), + .D(NlwRenamedSig_OI_trn_rd[13]), + .Q(com_cmm_tag[5]), + .R(com_cmm_rst_351) + ); + FDRE com_cmm_u_rx_pkt_proc_tag_6_ ( + .CE(com_cmm_u_rx_pkt_proc_idle_enable), + .C(NlwRenamedSig_OI_trn_clk), + .D(NlwRenamedSig_OI_trn_rd[14]), + .Q(com_cmm_tag[6]), + .R(com_cmm_rst_351) + ); + FDRE com_cmm_u_rx_pkt_proc_tag_7_ ( + .CE(com_cmm_u_rx_pkt_proc_idle_enable), + .C(NlwRenamedSig_OI_trn_clk), + .D(NlwRenamedSig_OI_trn_rd[15]), + .Q(com_cmm_tag[7]), + .R(com_cmm_rst_351) + ); + FDRE com_cmm_u_rx_pkt_proc_req_id_0_ ( + .CE(com_cmm_u_rx_pkt_proc_idle_enable), + .C(NlwRenamedSig_OI_trn_clk), + .D(NlwRenamedSig_OI_trn_rd[16]), + .Q(com_cmm_req_id[0]), + .R(com_cmm_rst_351) + ); + FDRE com_cmm_u_rx_pkt_proc_req_id_1_ ( + .CE(com_cmm_u_rx_pkt_proc_idle_enable), + .C(NlwRenamedSig_OI_trn_clk), + .D(NlwRenamedSig_OI_trn_rd[17]), + .Q(com_cmm_req_id[1]), + .R(com_cmm_rst_351) + ); + FDRE com_cmm_u_rx_pkt_proc_req_id_2_ ( + .CE(com_cmm_u_rx_pkt_proc_idle_enable), + .C(NlwRenamedSig_OI_trn_clk), + .D(NlwRenamedSig_OI_trn_rd[18]), + .Q(com_cmm_req_id[2]), + .R(com_cmm_rst_351) + ); + FDRE com_cmm_u_rx_pkt_proc_req_id_3_ ( + .CE(com_cmm_u_rx_pkt_proc_idle_enable), + .C(NlwRenamedSig_OI_trn_clk), + .D(NlwRenamedSig_OI_trn_rd[19]), + .Q(com_cmm_req_id[3]), + .R(com_cmm_rst_351) + ); + FDRE com_cmm_u_rx_pkt_proc_req_id_4_ ( + .CE(com_cmm_u_rx_pkt_proc_idle_enable), + .C(NlwRenamedSig_OI_trn_clk), + .D(NlwRenamedSig_OI_trn_rd[20]), + .Q(com_cmm_req_id[4]), + .R(com_cmm_rst_351) + ); + FDRE com_cmm_u_rx_pkt_proc_req_id_5_ ( + .CE(com_cmm_u_rx_pkt_proc_idle_enable), + .C(NlwRenamedSig_OI_trn_clk), + .D(NlwRenamedSig_OI_trn_rd[21]), + .Q(com_cmm_req_id[5]), + .R(com_cmm_rst_351) + ); + FDRE com_cmm_u_rx_pkt_proc_req_id_6_ ( + .CE(com_cmm_u_rx_pkt_proc_idle_enable), + .C(NlwRenamedSig_OI_trn_clk), + .D(NlwRenamedSig_OI_trn_rd[22]), + .Q(com_cmm_req_id[6]), + .R(com_cmm_rst_351) + ); + FDRE com_cmm_u_rx_pkt_proc_req_id_7_ ( + .CE(com_cmm_u_rx_pkt_proc_idle_enable), + .C(NlwRenamedSig_OI_trn_clk), + .D(NlwRenamedSig_OI_trn_rd[23]), + .Q(com_cmm_req_id[7]), + .R(com_cmm_rst_351) + ); + FDRE com_cmm_u_rx_pkt_proc_req_id_8_ ( + .CE(com_cmm_u_rx_pkt_proc_idle_enable), + .C(NlwRenamedSig_OI_trn_clk), + .D(NlwRenamedSig_OI_trn_rd[24]), + .Q(com_cmm_req_id[8]), + .R(com_cmm_rst_351) + ); + FDRE com_cmm_u_rx_pkt_proc_req_id_9_ ( + .CE(com_cmm_u_rx_pkt_proc_idle_enable), + .C(NlwRenamedSig_OI_trn_clk), + .D(NlwRenamedSig_OI_trn_rd[25]), + .Q(com_cmm_req_id[9]), + .R(com_cmm_rst_351) + ); + FDRE com_cmm_u_rx_pkt_proc_req_id_10_ ( + .CE(com_cmm_u_rx_pkt_proc_idle_enable), + .C(NlwRenamedSig_OI_trn_clk), + .D(NlwRenamedSig_OI_trn_rd[26]), + .Q(com_cmm_req_id[10]), + .R(com_cmm_rst_351) + ); + FDRE com_cmm_u_rx_pkt_proc_req_id_11_ ( + .CE(com_cmm_u_rx_pkt_proc_idle_enable), + .C(NlwRenamedSig_OI_trn_clk), + .D(NlwRenamedSig_OI_trn_rd[27]), + .Q(com_cmm_req_id[11]), + .R(com_cmm_rst_351) + ); + FDRE com_cmm_u_rx_pkt_proc_req_id_12_ ( + .CE(com_cmm_u_rx_pkt_proc_idle_enable), + .C(NlwRenamedSig_OI_trn_clk), + .D(NlwRenamedSig_OI_trn_rd[28]), + .Q(com_cmm_req_id[12]), + .R(com_cmm_rst_351) + ); + FDRE com_cmm_u_rx_pkt_proc_req_id_13_ ( + .CE(com_cmm_u_rx_pkt_proc_idle_enable), + .C(NlwRenamedSig_OI_trn_clk), + .D(NlwRenamedSig_OI_trn_rd[29]), + .Q(com_cmm_req_id[13]), + .R(com_cmm_rst_351) + ); + FDRE com_cmm_u_rx_pkt_proc_req_id_14_ ( + .CE(com_cmm_u_rx_pkt_proc_idle_enable), + .C(NlwRenamedSig_OI_trn_clk), + .D(NlwRenamedSig_OI_trn_rd[30]), + .Q(com_cmm_req_id[14]), + .R(com_cmm_rst_351) + ); + FDRE com_cmm_u_rx_pkt_proc_req_id_15_ ( + .CE(com_cmm_u_rx_pkt_proc_idle_enable), + .C(NlwRenamedSig_OI_trn_clk), + .D(NlwRenamedSig_OI_trn_rd[31]), + .Q(com_cmm_req_id[15]), + .R(com_cmm_rst_351) + ); + FDRE com_cmm_u_rx_pkt_proc_cfg_be_0_ ( + .CE(com_cmm_u_rx_pkt_proc_idle_enable), + .C(NlwRenamedSig_OI_trn_clk), + .D(NlwRenamedSig_OI_trn_rd[0]), + .Q(com_cmm_cfg_be[0]), + .R(com_cmm_rst_351) + ); + FDRE com_cmm_u_rx_pkt_proc_cfg_be_1_ ( + .CE(com_cmm_u_rx_pkt_proc_idle_enable), + .C(NlwRenamedSig_OI_trn_clk), + .D(NlwRenamedSig_OI_trn_rd[1]), + .Q(com_cmm_cfg_be[1]), + .R(com_cmm_rst_351) + ); + FDRE com_cmm_u_rx_pkt_proc_cfg_be_2_ ( + .CE(com_cmm_u_rx_pkt_proc_idle_enable), + .C(NlwRenamedSig_OI_trn_clk), + .D(NlwRenamedSig_OI_trn_rd[2]), + .Q(com_cmm_cfg_be[2]), + .R(com_cmm_rst_351) + ); + FDRE com_cmm_u_rx_pkt_proc_cfg_be_3_ ( + .CE(com_cmm_u_rx_pkt_proc_idle_enable), + .C(NlwRenamedSig_OI_trn_clk), + .D(NlwRenamedSig_OI_trn_rd[3]), + .Q(com_cmm_cfg_be[3]), + .R(com_cmm_rst_351) + ); + FDRE com_cmm_u_rx_pkt_proc_attr_0_ ( + .CE(com_cmm_u_rx_pkt_proc_idle_enable), + .C(NlwRenamedSig_OI_trn_clk), + .D(NlwRenamedSig_OI_trn_rd[44]), + .Q(com_cmm_attr[0]), + .R(com_cmm_rst_351) + ); + FDRE com_cmm_u_rx_pkt_proc_attr_1_ ( + .CE(com_cmm_u_rx_pkt_proc_idle_enable), + .C(NlwRenamedSig_OI_trn_clk), + .D(NlwRenamedSig_OI_trn_rd[45]), + .Q(com_cmm_attr[1]), + .R(com_cmm_rst_351) + ); + FDRE com_cmm_u_rx_pkt_proc_ecrc ( + .CE(com_cmmt_rsrc_rdy), + .C(NlwRenamedSig_OI_trn_clk), + .D(NlwRenamedSig_OI_trn_rd[47]), + .Q(com_cmm_u_rx_pkt_proc_ecrc_5350), + .R(com_cmm_rst_351) + ); + defparam com_cmm_u_rx_pkt_proc_idle_enable_0_a2_0_a2_0_a2.INIT = 4'h8; + LUT2 com_cmm_u_rx_pkt_proc_idle_enable_0_a2_0_a2_0_a2 ( + .I0(com_cmm_u_rx_pkt_proc_state[0]), + .I1(com_cmmt_rsrc_rdy), + .O(com_cmm_u_rx_pkt_proc_idle_enable) + ); + defparam com_cmm_u_rx_pkt_proc_dw1_enable_0_a2_0_a2_0_a2.INIT = 4'h8; + LUT2 com_cmm_u_rx_pkt_proc_dw1_enable_0_a2_0_a2_0_a2 ( + .I0(com_cmm_u_rx_pkt_proc_state[1]), + .I1(com_cmmt_rsrc_rdy), + .O(com_cmm_u_rx_pkt_proc_dw1_enable) + ); + defparam com_cmm_u_rx_pkt_proc_nxt_req_valid_iv_i_0_0_o3.INIT = 4'h8; + LUT2 com_cmm_u_rx_pkt_proc_nxt_req_valid_iv_i_0_0_o3 ( + .I0(com_cmm_gnt_cfgctrl), + .I1(com_cmm_req_cfgctrl), + .O(com_cmm_N_56090_i) + ); + defparam com_cmm_u_rx_pkt_proc_bdf_err_rd_pack_3_i_0_o3_0_0.INIT = 4'h1; + LUT2_L com_cmm_u_rx_pkt_proc_bdf_err_rd_pack_3_i_0_o3_0_0 ( + .I0(NlwRenamedSig_OI_trn_rd[38]), + .I1(NlwRenamedSig_OI_trn_rd[39]), + .LO(com_cmm_u_rx_pkt_proc_bdf_err_rd_pack_3_i_0_o3_0_0_5346) + ); + defparam com_cmm_u_rx_pkt_proc_nxt_req_valid_iv_i_0_0_a2.INIT = 8'h70; + LUT3 com_cmm_u_rx_pkt_proc_nxt_req_valid_iv_i_0_0_a2 ( + .I0(com_cmm_cfg_wr), + .I1(com_cmm_u_rx_pkt_proc_ecrc_5350), + .I2(com_cmm_u_rx_pkt_proc_state[1]), + .O(com_cmm_u_rx_pkt_proc_N_58687) + ); + defparam com_cmm_u_rx_pkt_proc_un1_cmmt_rsrc_rdy_n_1_i_0_0.INIT = 8'hE0; + LUT3 com_cmm_u_rx_pkt_proc_un1_cmmt_rsrc_rdy_n_1_i_0_0 ( + .I0(com_cmm_u_rx_pkt_proc_state[0]), + .I1(com_cmm_u_rx_pkt_proc_state[1]), + .I2(com_cmmt_rsrc_rdy), + .O(com_cmm_u_rx_pkt_proc_N_19513_i) + ); + defparam com_cmm_u_rx_pkt_proc_bdf_err_rd_pack_3_i_o4.INIT = 8'h01; + LUT3 com_cmm_u_rx_pkt_proc_bdf_err_rd_pack_3_i_o4 ( + .I0(NlwRenamedSig_OI_trn_rd[32]), + .I1(NlwRenamedSig_OI_trn_rd[33]), + .I2(NlwRenamedSig_OI_trn_rd[34]), + .O(com_cmm_u_rx_pkt_proc_bdf_err_rd_pack_3_i_o4_5349) + ); + defparam com_cmm_u_rx_pkt_proc_bdf_err_rd_pack_3_i_0_o3.INIT = 8'h01; + LUT3 com_cmm_u_rx_pkt_proc_bdf_err_rd_pack_3_i_0_o3 ( + .I0(NlwRenamedSig_OI_trn_rd[48]), + .I1(NlwRenamedSig_OI_trn_rd[49]), + .I2(NlwRenamedSig_OI_trn_rd[50]), + .O(com_cmm_u_rx_pkt_proc_N_56198_i) + ); + defparam com_cmm_u_rx_pkt_proc_cfg_rd_3_0_a2_0_a2_0_a2_2.INIT = 16'h0001; + LUT4 com_cmm_u_rx_pkt_proc_cfg_rd_3_0_a2_0_a2_0_a2_2 ( + .I0(NlwRenamedSig_OI_trn_rd[57]), + .I1(NlwRenamedSig_OI_trn_rd[59]), + .I2(NlwRenamedSig_OI_trn_rd[60]), + .I3(NlwRenamedSig_OI_trn_rd[61]), + .O(com_cmm_u_rx_pkt_proc_N_60331_5) + ); + defparam com_cmm_u_rx_pkt_proc_un1_state_1_i_0_0.INIT = 16'h0501; + LUT4 com_cmm_u_rx_pkt_proc_un1_state_1_i_0_0 ( + .I0(com_cmm_u_rx_pkt_proc_state[0]), + .I1(com_cmm_u_rx_pkt_proc_state[1]), + .I2(com_cmm_u_rx_pkt_proc_state[2]), + .I3(com_cmmt_rsrc_rdy), + .O(com_cmm_u_rx_pkt_proc_N_19515_i) + ); + defparam com_cmm_u_rx_pkt_proc_bdf_err_rd_pack_3_i_0_2.INIT = 16'h0001; + LUT4 com_cmm_u_rx_pkt_proc_bdf_err_rd_pack_3_i_0_2 ( + .I0(NlwRenamedSig_OI_trn_rd[41]), + .I1(NlwRenamedSig_OI_trn_rd[42]), + .I2(NlwRenamedSig_OI_trn_rd[43]), + .I3(NlwRenamedSig_OI_trn_rd[44]), + .O(com_cmm_u_rx_pkt_proc_bdf_err_rd_pack_3_i_0_2_5348) + ); + defparam com_cmm_u_rx_pkt_proc_bdf_err_rd_pack_3_i_0_a2.INIT = 16'hFD00; + LUT4 com_cmm_u_rx_pkt_proc_bdf_err_rd_pack_3_i_0_a2 ( + .I0(com_cmm_u_rx_pkt_proc_bdf_err_rd_pack_3_i_0_o3_0_0_5346), + .I1(NlwRenamedSig_OI_trn_rd[36]), + .I2(NlwRenamedSig_OI_trn_rd[37]), + .I3(NlwRenamedSig_OI_trn_rd[40]), + .O(com_cmm_u_rx_pkt_proc_N_59558) + ); + defparam com_cmm_u_rx_pkt_proc_un1_dw1_enable_2_0_a2_0_a2_0_a2.INIT = 8'h80; + LUT3 com_cmm_u_rx_pkt_proc_un1_dw1_enable_2_0_a2_0_a2_0_a2 ( + .I0(com_cmm_N_55868_i), + .I1(com_cmm_u_rx_pkt_proc_N_56198_i), + .I2(com_cmm_u_rx_pkt_proc_dw1_enable), + .O(com_cmm_u_rx_pkt_proc_un1_dw1_enable_2_0_a2_0_a2_0_a2_5347) + ); + defparam com_cmm_u_rx_pkt_proc_cfg_wr_3_0_a2_0_a2_0_a2.INIT = 8'h80; + LUT3 com_cmm_u_rx_pkt_proc_cfg_wr_3_0_a2_0_a2_0_a2 ( + .I0(com_cmm_u_rx_pkt_proc_N_60331_5), + .I1(NlwRenamedSig_OI_trn_rd[58]), + .I2(NlwRenamedSig_OI_trn_rd[62]), + .O(com_cmm_u_rx_pkt_proc_cfg_wr_3) + ); + defparam com_cmm_u_rx_pkt_proc_bdf_err_rd_pack_3_i_0_3.INIT = 16'h8CCC; + LUT4 com_cmm_u_rx_pkt_proc_bdf_err_rd_pack_3_i_0_3 ( + .I0(com_cmm_u_rx_pkt_proc_bdf_err_rd_pack_3_i_o4_5349), + .I1(com_cmm_u_rx_pkt_proc_bdf_err_rd_pack_3_i_0_2_5348), + .I2(NlwRenamedSig_OI_trn_rd[35]), + .I3(NlwRenamedSig_OI_trn_rd[40]), + .O(com_cmm_u_rx_pkt_proc_bdf_err_rd_pack_3_i_0_3_5354) + ); + defparam com_cmm_u_rx_pkt_proc_posnd_wr_pack_6_0_i_i_0.INIT = 16'hFF0B; + LUT4 com_cmm_u_rx_pkt_proc_posnd_wr_pack_6_0_i_i_0 ( + .I0(com_cmm_u_rx_pkt_proc_N_56198_i), + .I1(com_cmm_cfg_wr), + .I2(com_cmm_posnd_wr_pack), + .I3(com_cmm_u_rx_pkt_proc_state[0]), + .O(com_cmm_u_rx_pkt_proc_posnd_wr_pack_6_0_i_i_0_5352) + ); + defparam com_cmm_u_rx_pkt_proc_N_85817_i.INIT = 16'hFEFC; + LUT4_L com_cmm_u_rx_pkt_proc_N_85817_i ( + .I0(com_cmm_u_rx_pkt_proc_N_58687), + .I1(com_cmm_u_rx_pkt_proc_N_58688), + .I2(com_cmm_u_rx_pkt_proc_state[2]), + .I3(com_cmmt_rsrc_rdy), + .LO(com_cmm_u_rx_pkt_proc_N_85817_i_5355) + ); + defparam com_cmm_u_rx_pkt_proc_next_state_0_sqmuxa_3_0_a2_0_a2_0_a2.INIT = 8'h80; + LUT3_L com_cmm_u_rx_pkt_proc_next_state_0_sqmuxa_3_0_a2_0_a2_0_a2 ( + .I0(com_cmm_cfg_wr), + .I1(com_cmm_u_rx_pkt_proc_dw1_enable), + .I2(com_cmm_u_rx_pkt_proc_ecrc_5350), + .LO(com_cmm_u_rx_pkt_proc_next_state_0_sqmuxa_3) + ); + defparam com_cmm_u_rx_pkt_proc_state_idle_3_i_i_0.INIT = 16'hA0EC; + LUT4_L com_cmm_u_rx_pkt_proc_state_idle_3_i_i_0 ( + .I0(com_cmm_N_56090_i), + .I1(com_cmm_u_rx_pkt_proc_state[0]), + .I2(com_cmmt_rdst_rdy_n), + .I3(com_cmmt_rsrc_rdy), + .LO(com_cmm_u_rx_pkt_proc_N_43405_i) + ); + defparam com_cmm_u_rx_pkt_proc_cfg_rd_3_0_a2_0_a2_0_a2.INIT = 8'h08; + LUT3_L com_cmm_u_rx_pkt_proc_cfg_rd_3_0_a2_0_a2_0_a2 ( + .I0(com_cmm_u_rx_pkt_proc_N_60331_5), + .I1(NlwRenamedSig_OI_trn_rd[58]), + .I2(NlwRenamedSig_OI_trn_rd[62]), + .LO(com_cmm_u_rx_pkt_proc_cfg_rd_3) + ); + defparam com_cmm_u_rx_pkt_proc_type1_type0_bar_3_0_a2_0_a2_0_a2.INIT = 8'h80; + LUT3_L com_cmm_u_rx_pkt_proc_type1_type0_bar_3_0_a2_0_a2_0_a2 ( + .I0(com_cmm_u_rx_pkt_proc_N_60331_5), + .I1(NlwRenamedSig_OI_trn_rd[56]), + .I2(NlwRenamedSig_OI_trn_rd[58]), + .LO(com_cmm_u_rx_pkt_proc_type1_type0_bar_3) + ); + defparam com_cmm_u_rx_pkt_proc_nxt_cfg_wr_data_0_a2_0_a2_0_a2_31_.INIT = 4'h8; + LUT2_L com_cmm_u_rx_pkt_proc_nxt_cfg_wr_data_0_a2_0_a2_0_a2_31_ ( + .I0(com_cmm_cfg_wr), + .I1(NlwRenamedSig_OI_trn_rd[31]), + .LO(com_cmm_u_rx_pkt_proc_nxt_cfg_wr_data[31]) + ); + defparam com_cmm_u_rx_pkt_proc_nxt_cfg_wr_data_0_a2_0_a2_0_a2_30_.INIT = 4'h8; + LUT2_L com_cmm_u_rx_pkt_proc_nxt_cfg_wr_data_0_a2_0_a2_0_a2_30_ ( + .I0(com_cmm_cfg_wr), + .I1(NlwRenamedSig_OI_trn_rd[30]), + .LO(com_cmm_u_rx_pkt_proc_nxt_cfg_wr_data[30]) + ); + defparam com_cmm_u_rx_pkt_proc_nxt_cfg_wr_data_0_a2_0_a2_0_a2_29_.INIT = 4'h8; + LUT2_L com_cmm_u_rx_pkt_proc_nxt_cfg_wr_data_0_a2_0_a2_0_a2_29_ ( + .I0(com_cmm_cfg_wr), + .I1(NlwRenamedSig_OI_trn_rd[29]), + .LO(com_cmm_u_rx_pkt_proc_nxt_cfg_wr_data[29]) + ); + defparam com_cmm_u_rx_pkt_proc_nxt_cfg_wr_data_0_a2_0_a2_0_a2_28_.INIT = 4'h8; + LUT2_L com_cmm_u_rx_pkt_proc_nxt_cfg_wr_data_0_a2_0_a2_0_a2_28_ ( + .I0(com_cmm_cfg_wr), + .I1(NlwRenamedSig_OI_trn_rd[28]), + .LO(com_cmm_u_rx_pkt_proc_nxt_cfg_wr_data[28]) + ); + defparam com_cmm_u_rx_pkt_proc_nxt_cfg_wr_data_0_a2_0_a2_0_a2_27_.INIT = 4'h8; + LUT2_L com_cmm_u_rx_pkt_proc_nxt_cfg_wr_data_0_a2_0_a2_0_a2_27_ ( + .I0(com_cmm_cfg_wr), + .I1(NlwRenamedSig_OI_trn_rd[27]), + .LO(com_cmm_u_rx_pkt_proc_nxt_cfg_wr_data[27]) + ); + defparam com_cmm_u_rx_pkt_proc_nxt_cfg_wr_data_0_a2_0_a2_0_a2_26_.INIT = 4'h8; + LUT2_L com_cmm_u_rx_pkt_proc_nxt_cfg_wr_data_0_a2_0_a2_0_a2_26_ ( + .I0(com_cmm_cfg_wr), + .I1(NlwRenamedSig_OI_trn_rd[26]), + .LO(com_cmm_u_rx_pkt_proc_nxt_cfg_wr_data[26]) + ); + defparam com_cmm_u_rx_pkt_proc_nxt_cfg_wr_data_0_a2_0_a2_0_a2_25_.INIT = 4'h8; + LUT2_L com_cmm_u_rx_pkt_proc_nxt_cfg_wr_data_0_a2_0_a2_0_a2_25_ ( + .I0(com_cmm_cfg_wr), + .I1(NlwRenamedSig_OI_trn_rd[25]), + .LO(com_cmm_u_rx_pkt_proc_nxt_cfg_wr_data[25]) + ); + defparam com_cmm_u_rx_pkt_proc_nxt_cfg_wr_data_0_a2_0_a2_0_a2_24_.INIT = 4'h8; + LUT2_L com_cmm_u_rx_pkt_proc_nxt_cfg_wr_data_0_a2_0_a2_0_a2_24_ ( + .I0(com_cmm_cfg_wr), + .I1(NlwRenamedSig_OI_trn_rd[24]), + .LO(com_cmm_u_rx_pkt_proc_nxt_cfg_wr_data[24]) + ); + defparam com_cmm_u_rx_pkt_proc_nxt_cfg_wr_data_0_a2_0_a2_0_a2_23_.INIT = 4'h8; + LUT2_L com_cmm_u_rx_pkt_proc_nxt_cfg_wr_data_0_a2_0_a2_0_a2_23_ ( + .I0(com_cmm_cfg_wr), + .I1(NlwRenamedSig_OI_trn_rd[23]), + .LO(com_cmm_u_rx_pkt_proc_nxt_cfg_wr_data[23]) + ); + defparam com_cmm_u_rx_pkt_proc_nxt_cfg_wr_data_0_a2_0_a2_0_a2_22_.INIT = 4'h8; + LUT2_L com_cmm_u_rx_pkt_proc_nxt_cfg_wr_data_0_a2_0_a2_0_a2_22_ ( + .I0(com_cmm_cfg_wr), + .I1(NlwRenamedSig_OI_trn_rd[22]), + .LO(com_cmm_u_rx_pkt_proc_nxt_cfg_wr_data[22]) + ); + defparam com_cmm_u_rx_pkt_proc_nxt_cfg_wr_data_0_a2_0_a2_0_a2_21_.INIT = 4'h8; + LUT2_L com_cmm_u_rx_pkt_proc_nxt_cfg_wr_data_0_a2_0_a2_0_a2_21_ ( + .I0(com_cmm_cfg_wr), + .I1(NlwRenamedSig_OI_trn_rd[21]), + .LO(com_cmm_u_rx_pkt_proc_nxt_cfg_wr_data[21]) + ); + defparam com_cmm_u_rx_pkt_proc_nxt_cfg_wr_data_0_a2_0_a2_0_a2_20_.INIT = 4'h8; + LUT2_L com_cmm_u_rx_pkt_proc_nxt_cfg_wr_data_0_a2_0_a2_0_a2_20_ ( + .I0(com_cmm_cfg_wr), + .I1(NlwRenamedSig_OI_trn_rd[20]), + .LO(com_cmm_u_rx_pkt_proc_nxt_cfg_wr_data[20]) + ); + defparam com_cmm_u_rx_pkt_proc_nxt_cfg_wr_data_0_a2_0_a2_0_a2_19_.INIT = 4'h8; + LUT2_L com_cmm_u_rx_pkt_proc_nxt_cfg_wr_data_0_a2_0_a2_0_a2_19_ ( + .I0(com_cmm_cfg_wr), + .I1(NlwRenamedSig_OI_trn_rd[19]), + .LO(com_cmm_u_rx_pkt_proc_nxt_cfg_wr_data[19]) + ); + defparam com_cmm_u_rx_pkt_proc_nxt_cfg_wr_data_0_a2_0_a2_0_a2_18_.INIT = 4'h8; + LUT2_L com_cmm_u_rx_pkt_proc_nxt_cfg_wr_data_0_a2_0_a2_0_a2_18_ ( + .I0(com_cmm_cfg_wr), + .I1(NlwRenamedSig_OI_trn_rd[18]), + .LO(com_cmm_u_rx_pkt_proc_nxt_cfg_wr_data[18]) + ); + defparam com_cmm_u_rx_pkt_proc_nxt_cfg_wr_data_0_a2_0_a2_0_a2_17_.INIT = 4'h8; + LUT2_L com_cmm_u_rx_pkt_proc_nxt_cfg_wr_data_0_a2_0_a2_0_a2_17_ ( + .I0(com_cmm_cfg_wr), + .I1(NlwRenamedSig_OI_trn_rd[17]), + .LO(com_cmm_u_rx_pkt_proc_nxt_cfg_wr_data[17]) + ); + defparam com_cmm_u_rx_pkt_proc_nxt_cfg_wr_data_0_a2_0_a2_0_a2_16_.INIT = 4'h8; + LUT2_L com_cmm_u_rx_pkt_proc_nxt_cfg_wr_data_0_a2_0_a2_0_a2_16_ ( + .I0(com_cmm_cfg_wr), + .I1(NlwRenamedSig_OI_trn_rd[16]), + .LO(com_cmm_u_rx_pkt_proc_nxt_cfg_wr_data[16]) + ); + defparam com_cmm_u_rx_pkt_proc_nxt_cfg_wr_data_0_a2_0_a2_0_a2_15_.INIT = 4'h8; + LUT2_L com_cmm_u_rx_pkt_proc_nxt_cfg_wr_data_0_a2_0_a2_0_a2_15_ ( + .I0(com_cmm_cfg_wr), + .I1(NlwRenamedSig_OI_trn_rd[15]), + .LO(com_cmm_u_rx_pkt_proc_nxt_cfg_wr_data[15]) + ); + defparam com_cmm_u_rx_pkt_proc_nxt_cfg_wr_data_0_a2_0_a2_0_a2_14_.INIT = 4'h8; + LUT2_L com_cmm_u_rx_pkt_proc_nxt_cfg_wr_data_0_a2_0_a2_0_a2_14_ ( + .I0(com_cmm_cfg_wr), + .I1(NlwRenamedSig_OI_trn_rd[14]), + .LO(com_cmm_u_rx_pkt_proc_nxt_cfg_wr_data[14]) + ); + defparam com_cmm_u_rx_pkt_proc_nxt_cfg_wr_data_0_a2_0_a2_0_a2_13_.INIT = 4'h8; + LUT2_L com_cmm_u_rx_pkt_proc_nxt_cfg_wr_data_0_a2_0_a2_0_a2_13_ ( + .I0(com_cmm_cfg_wr), + .I1(NlwRenamedSig_OI_trn_rd[13]), + .LO(com_cmm_u_rx_pkt_proc_nxt_cfg_wr_data[13]) + ); + defparam com_cmm_u_rx_pkt_proc_nxt_cfg_wr_data_0_a2_0_a2_0_a2_12_.INIT = 4'h8; + LUT2_L com_cmm_u_rx_pkt_proc_nxt_cfg_wr_data_0_a2_0_a2_0_a2_12_ ( + .I0(com_cmm_cfg_wr), + .I1(NlwRenamedSig_OI_trn_rd[12]), + .LO(com_cmm_u_rx_pkt_proc_nxt_cfg_wr_data[12]) + ); + defparam com_cmm_u_rx_pkt_proc_nxt_cfg_wr_data_0_a2_0_a2_0_a2_11_.INIT = 4'h8; + LUT2_L com_cmm_u_rx_pkt_proc_nxt_cfg_wr_data_0_a2_0_a2_0_a2_11_ ( + .I0(com_cmm_cfg_wr), + .I1(NlwRenamedSig_OI_trn_rd[11]), + .LO(com_cmm_u_rx_pkt_proc_nxt_cfg_wr_data[11]) + ); + defparam com_cmm_u_rx_pkt_proc_nxt_cfg_wr_data_0_a2_0_a2_0_a2_10_.INIT = 4'h8; + LUT2_L com_cmm_u_rx_pkt_proc_nxt_cfg_wr_data_0_a2_0_a2_0_a2_10_ ( + .I0(com_cmm_cfg_wr), + .I1(NlwRenamedSig_OI_trn_rd[10]), + .LO(com_cmm_u_rx_pkt_proc_nxt_cfg_wr_data[10]) + ); + defparam com_cmm_u_rx_pkt_proc_nxt_cfg_wr_data_0_a2_0_a2_0_a2_9_.INIT = 4'h8; + LUT2_L com_cmm_u_rx_pkt_proc_nxt_cfg_wr_data_0_a2_0_a2_0_a2_9_ ( + .I0(com_cmm_cfg_wr), + .I1(NlwRenamedSig_OI_trn_rd[9]), + .LO(com_cmm_u_rx_pkt_proc_nxt_cfg_wr_data[9]) + ); + defparam com_cmm_u_rx_pkt_proc_nxt_cfg_wr_data_0_a2_0_a2_0_a2_8_.INIT = 4'h8; + LUT2_L com_cmm_u_rx_pkt_proc_nxt_cfg_wr_data_0_a2_0_a2_0_a2_8_ ( + .I0(com_cmm_cfg_wr), + .I1(NlwRenamedSig_OI_trn_rd[8]), + .LO(com_cmm_u_rx_pkt_proc_nxt_cfg_wr_data[8]) + ); + defparam com_cmm_u_rx_pkt_proc_nxt_cfg_wr_data_0_a2_0_a2_0_a2_7_.INIT = 4'h8; + LUT2_L com_cmm_u_rx_pkt_proc_nxt_cfg_wr_data_0_a2_0_a2_0_a2_7_ ( + .I0(com_cmm_cfg_wr), + .I1(NlwRenamedSig_OI_trn_rd[7]), + .LO(com_cmm_u_rx_pkt_proc_nxt_cfg_wr_data[7]) + ); + defparam com_cmm_u_rx_pkt_proc_nxt_cfg_wr_data_0_a2_0_a2_0_a2_6_.INIT = 4'h8; + LUT2_L com_cmm_u_rx_pkt_proc_nxt_cfg_wr_data_0_a2_0_a2_0_a2_6_ ( + .I0(com_cmm_cfg_wr), + .I1(NlwRenamedSig_OI_trn_rd[6]), + .LO(com_cmm_u_rx_pkt_proc_nxt_cfg_wr_data[6]) + ); + defparam com_cmm_u_rx_pkt_proc_nxt_cfg_wr_data_0_a2_0_a2_0_a2_5_.INIT = 4'h8; + LUT2_L com_cmm_u_rx_pkt_proc_nxt_cfg_wr_data_0_a2_0_a2_0_a2_5_ ( + .I0(com_cmm_cfg_wr), + .I1(NlwRenamedSig_OI_trn_rd[5]), + .LO(com_cmm_u_rx_pkt_proc_nxt_cfg_wr_data[5]) + ); + defparam com_cmm_u_rx_pkt_proc_nxt_cfg_wr_data_0_a2_0_a2_0_a2_4_.INIT = 4'h8; + LUT2_L com_cmm_u_rx_pkt_proc_nxt_cfg_wr_data_0_a2_0_a2_0_a2_4_ ( + .I0(com_cmm_cfg_wr), + .I1(NlwRenamedSig_OI_trn_rd[4]), + .LO(com_cmm_u_rx_pkt_proc_nxt_cfg_wr_data[4]) + ); + defparam com_cmm_u_rx_pkt_proc_nxt_cfg_wr_data_0_a2_0_a2_0_a2_3_.INIT = 4'h8; + LUT2_L com_cmm_u_rx_pkt_proc_nxt_cfg_wr_data_0_a2_0_a2_0_a2_3_ ( + .I0(com_cmm_cfg_wr), + .I1(NlwRenamedSig_OI_trn_rd[3]), + .LO(com_cmm_u_rx_pkt_proc_nxt_cfg_wr_data[3]) + ); + defparam com_cmm_u_rx_pkt_proc_nxt_cfg_wr_data_0_a2_0_a2_0_a2_2_.INIT = 4'h8; + LUT2_L com_cmm_u_rx_pkt_proc_nxt_cfg_wr_data_0_a2_0_a2_0_a2_2_ ( + .I0(com_cmm_cfg_wr), + .I1(NlwRenamedSig_OI_trn_rd[2]), + .LO(com_cmm_u_rx_pkt_proc_nxt_cfg_wr_data[2]) + ); + defparam com_cmm_u_rx_pkt_proc_nxt_cfg_wr_data_0_a2_0_a2_0_a2_1_.INIT = 4'h8; + LUT2_L com_cmm_u_rx_pkt_proc_nxt_cfg_wr_data_0_a2_0_a2_0_a2_1_ ( + .I0(com_cmm_cfg_wr), + .I1(NlwRenamedSig_OI_trn_rd[1]), + .LO(com_cmm_u_rx_pkt_proc_nxt_cfg_wr_data[1]) + ); + defparam com_cmm_u_rx_pkt_proc_nxt_cfg_wr_data_0_a2_0_a2_0_a2_0_.INIT = 4'h8; + LUT2_L com_cmm_u_rx_pkt_proc_nxt_cfg_wr_data_0_a2_0_a2_0_a2_0_ ( + .I0(com_cmm_cfg_wr), + .I1(NlwRenamedSig_OI_trn_rd[0]), + .LO(com_cmm_u_rx_pkt_proc_nxt_cfg_wr_data[0]) + ); + defparam com_cmm_u_rx_pkt_proc_N_86814_i.INIT = 4'hE; + LUT2_L com_cmm_u_rx_pkt_proc_N_86814_i ( + .I0(com_cmm_u_rx_pkt_proc_N_58687), + .I1(com_cmm_u_rx_pkt_proc_N_58688), + .LO(com_cmm_u_rx_pkt_proc_N_86814_i_5356) + ); + defparam com_cmm_u_rx_pkt_proc_N_85914_i.INIT = 16'hB333; + LUT4_L com_cmm_u_rx_pkt_proc_N_85914_i ( + .I0(com_cmm_u_rx_pkt_proc_cfg_wr_3), + .I1(com_cmm_u_rx_pkt_proc_posnd_wr_pack_6_0_i_i_0_5352), + .I2(com_cmm_u_rx_pkt_proc_state[0]), + .I3(NlwRenamedSig_OI_trn_rd[46]), + .LO(com_cmm_u_rx_pkt_proc_N_85914_i_5351) + ); + defparam com_cmm_u_rx_pkt_proc_N_85975_i.INIT = 16'hDCFF; + LUT4_L com_cmm_u_rx_pkt_proc_N_85975_i ( + .I0(com_cmm_u_rx_pkt_proc_N_56198_i), + .I1(com_cmm_u_rx_pkt_proc_N_59558), + .I2(com_cmm_cfg_rd), + .I3(com_cmm_u_rx_pkt_proc_bdf_err_rd_pack_3_i_0_3_5354), + .LO(com_cmm_u_rx_pkt_proc_N_85975_i_5353) + ); + defparam com_cmm_u_rx_pkt_proc_nxt_req_valid_iv_i_0_0_a2_0.INIT = 8'h2A; + LUT3 com_cmm_u_rx_pkt_proc_nxt_req_valid_iv_i_0_0_a2_0 ( + .I0(com_cmmt_rdst_rdy_n), + .I1(com_cmm_req_cfgctrl), + .I2(com_cmm_gnt_cfgctrl), + .O(com_cmm_u_rx_pkt_proc_N_58688) + ); + FDC com_cmm_u_rx_pkt_proc_state_3_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_rx_pkt_proc_N_85817_i_5355), + .Q(com_cmmt_rdst_rdy_n), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_rx_pkt_proc_state_2_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_rx_pkt_proc_next_state_0_sqmuxa_3), + .Q(com_cmm_u_rx_pkt_proc_state[2]), + .CLR(com_cmm_rst_351) + ); + FDCE com_cmm_u_rx_pkt_proc_state_1_ ( + .CE(com_cmmt_rsrc_rdy), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_rx_pkt_proc_state[0]), + .Q(com_cmm_u_rx_pkt_proc_state[1]), + .CLR(com_cmm_rst_351) + ); + FDP com_cmm_u_rx_pkt_proc_state_0_ ( + .PRE(com_cmm_rst_351), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_rx_pkt_proc_N_43405_i), + .Q(com_cmm_u_rx_pkt_proc_state[0]) + ); + FDCE com_cmm_u_rx_pkt_proc_cfg_addr_9_ ( + .CE(com_cmm_u_rx_pkt_proc_dw1_enable), + .C(NlwRenamedSig_OI_trn_clk), + .D(NlwRenamedSig_OI_trn_rd[43]), + .Q(com_cmm_cfg_addr[9]), + .CLR(com_cmm_rst_351) + ); + FDCE com_cmm_u_rx_pkt_proc_cfg_addr_8_ ( + .CE(com_cmm_u_rx_pkt_proc_dw1_enable), + .C(NlwRenamedSig_OI_trn_clk), + .D(NlwRenamedSig_OI_trn_rd[42]), + .Q(com_cmm_cfg_addr[8]), + .CLR(com_cmm_rst_351) + ); + FDCE com_cmm_u_rx_pkt_proc_cfg_addr_7_ ( + .CE(com_cmm_u_rx_pkt_proc_dw1_enable), + .C(NlwRenamedSig_OI_trn_clk), + .D(NlwRenamedSig_OI_trn_rd[41]), + .Q(com_cmm_cfg_addr[7]), + .CLR(com_cmm_rst_351) + ); + FDCE com_cmm_u_rx_pkt_proc_cfg_addr_6_ ( + .CE(com_cmm_u_rx_pkt_proc_dw1_enable), + .C(NlwRenamedSig_OI_trn_clk), + .D(NlwRenamedSig_OI_trn_rd[40]), + .Q(com_cmm_cfg_addr[6]), + .CLR(com_cmm_rst_351) + ); + FDCE com_cmm_u_rx_pkt_proc_cfg_addr_5_ ( + .CE(com_cmm_u_rx_pkt_proc_dw1_enable), + .C(NlwRenamedSig_OI_trn_clk), + .D(NlwRenamedSig_OI_trn_rd[39]), + .Q(com_cmm_cfg_addr[5]), + .CLR(com_cmm_rst_351) + ); + FDCE com_cmm_u_rx_pkt_proc_cfg_addr_4_ ( + .CE(com_cmm_u_rx_pkt_proc_dw1_enable), + .C(NlwRenamedSig_OI_trn_clk), + .D(NlwRenamedSig_OI_trn_rd[38]), + .Q(com_cmm_cfg_addr[4]), + .CLR(com_cmm_rst_351) + ); + FDCE com_cmm_u_rx_pkt_proc_cfg_addr_3_ ( + .CE(com_cmm_u_rx_pkt_proc_dw1_enable), + .C(NlwRenamedSig_OI_trn_clk), + .D(NlwRenamedSig_OI_trn_rd[37]), + .Q(com_cmm_cfg_addr[3]), + .CLR(com_cmm_rst_351) + ); + FDCE com_cmm_u_rx_pkt_proc_cfg_addr_2_ ( + .CE(com_cmm_u_rx_pkt_proc_dw1_enable), + .C(NlwRenamedSig_OI_trn_clk), + .D(NlwRenamedSig_OI_trn_rd[36]), + .Q(com_cmm_cfg_addr[2]), + .CLR(com_cmm_rst_351) + ); + FDCE com_cmm_u_rx_pkt_proc_cfg_addr_1_ ( + .CE(com_cmm_u_rx_pkt_proc_dw1_enable), + .C(NlwRenamedSig_OI_trn_clk), + .D(NlwRenamedSig_OI_trn_rd[35]), + .Q(com_cmm_cfg_addr[1]), + .CLR(com_cmm_rst_351) + ); + FDCE com_cmm_u_rx_pkt_proc_cfg_addr_0_ ( + .CE(com_cmm_u_rx_pkt_proc_dw1_enable), + .C(NlwRenamedSig_OI_trn_clk), + .D(NlwRenamedSig_OI_trn_rd[34]), + .Q(com_cmm_cfg_addr[0]), + .CLR(com_cmm_rst_351) + ); + FDCE com_cmm_u_rx_pkt_proc_cfg_wr_data_31_ ( + .CE(com_cmm_u_rx_pkt_proc_dw1_enable), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_rx_pkt_proc_nxt_cfg_wr_data[31]), + .Q(com_cmm_cfg_wr_data_31_), + .CLR(com_cmm_rst_351) + ); + FDCE com_cmm_u_rx_pkt_proc_cfg_wr_data_30_ ( + .CE(com_cmm_u_rx_pkt_proc_dw1_enable), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_rx_pkt_proc_nxt_cfg_wr_data[30]), + .Q(com_cmm_cfg_wr_data_30_), + .CLR(com_cmm_rst_351) + ); + FDCE com_cmm_u_rx_pkt_proc_cfg_wr_data_29_ ( + .CE(com_cmm_u_rx_pkt_proc_dw1_enable), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_rx_pkt_proc_nxt_cfg_wr_data[29]), + .Q(com_cmm_cfg_wr_data_29_), + .CLR(com_cmm_rst_351) + ); + FDCE com_cmm_u_rx_pkt_proc_cfg_wr_data_28_ ( + .CE(com_cmm_u_rx_pkt_proc_dw1_enable), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_rx_pkt_proc_nxt_cfg_wr_data[28]), + .Q(com_cmm_cfg_wr_data_28_), + .CLR(com_cmm_rst_351) + ); + FDCE com_cmm_u_rx_pkt_proc_cfg_wr_data_27_ ( + .CE(com_cmm_u_rx_pkt_proc_dw1_enable), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_rx_pkt_proc_nxt_cfg_wr_data[27]), + .Q(com_cmm_cfg_wr_data[27]), + .CLR(com_cmm_rst_351) + ); + FDCE com_cmm_u_rx_pkt_proc_cfg_wr_data_26_ ( + .CE(com_cmm_u_rx_pkt_proc_dw1_enable), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_rx_pkt_proc_nxt_cfg_wr_data[26]), + .Q(com_cmm_cfg_wr_data[26]), + .CLR(com_cmm_rst_351) + ); + FDCE com_cmm_u_rx_pkt_proc_cfg_wr_data_25_ ( + .CE(com_cmm_u_rx_pkt_proc_dw1_enable), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_rx_pkt_proc_nxt_cfg_wr_data[25]), + .Q(com_cmm_cfg_wr_data[25]), + .CLR(com_cmm_rst_351) + ); + FDCE com_cmm_u_rx_pkt_proc_cfg_wr_data_24_ ( + .CE(com_cmm_u_rx_pkt_proc_dw1_enable), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_rx_pkt_proc_nxt_cfg_wr_data[24]), + .Q(com_cmm_cfg_wr_data[24]), + .CLR(com_cmm_rst_351) + ); + FDCE com_cmm_u_rx_pkt_proc_cfg_wr_data_23_ ( + .CE(com_cmm_u_rx_pkt_proc_dw1_enable), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_rx_pkt_proc_nxt_cfg_wr_data[23]), + .Q(com_cmm_cfg_wr_data_23_), + .CLR(com_cmm_rst_351) + ); + FDCE com_cmm_u_rx_pkt_proc_cfg_wr_data_22_ ( + .CE(com_cmm_u_rx_pkt_proc_dw1_enable), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_rx_pkt_proc_nxt_cfg_wr_data[22]), + .Q(com_cmm_cfg_wr_data_22_), + .CLR(com_cmm_rst_351) + ); + FDCE com_cmm_u_rx_pkt_proc_cfg_wr_data_21_ ( + .CE(com_cmm_u_rx_pkt_proc_dw1_enable), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_rx_pkt_proc_nxt_cfg_wr_data[21]), + .Q(com_cmm_cfg_wr_data_21_), + .CLR(com_cmm_rst_351) + ); + FDCE com_cmm_u_rx_pkt_proc_cfg_wr_data_20_ ( + .CE(com_cmm_u_rx_pkt_proc_dw1_enable), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_rx_pkt_proc_nxt_cfg_wr_data[20]), + .Q(com_cmm_cfg_wr_data_20_), + .CLR(com_cmm_rst_351) + ); + FDCE com_cmm_u_rx_pkt_proc_cfg_wr_data_19_ ( + .CE(com_cmm_u_rx_pkt_proc_dw1_enable), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_rx_pkt_proc_nxt_cfg_wr_data[19]), + .Q(com_cmm_cfg_wr_data_19_), + .CLR(com_cmm_rst_351) + ); + FDCE com_cmm_u_rx_pkt_proc_cfg_wr_data_18_ ( + .CE(com_cmm_u_rx_pkt_proc_dw1_enable), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_rx_pkt_proc_nxt_cfg_wr_data[18]), + .Q(com_cmm_cfg_wr_data_18_), + .CLR(com_cmm_rst_351) + ); + FDCE com_cmm_u_rx_pkt_proc_cfg_wr_data_17_ ( + .CE(com_cmm_u_rx_pkt_proc_dw1_enable), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_rx_pkt_proc_nxt_cfg_wr_data[17]), + .Q(com_cmm_cfg_wr_data_17_), + .CLR(com_cmm_rst_351) + ); + FDCE com_cmm_u_rx_pkt_proc_cfg_wr_data_16_ ( + .CE(com_cmm_u_rx_pkt_proc_dw1_enable), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_rx_pkt_proc_nxt_cfg_wr_data[16]), + .Q(com_cmm_cfg_wr_data_16_), + .CLR(com_cmm_rst_351) + ); + FDCE com_cmm_u_rx_pkt_proc_cfg_wr_data_15_ ( + .CE(com_cmm_u_rx_pkt_proc_dw1_enable), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_rx_pkt_proc_nxt_cfg_wr_data[15]), + .Q(com_cmm_cfg_wr_data_15_), + .CLR(com_cmm_rst_351) + ); + FDCE com_cmm_u_rx_pkt_proc_cfg_wr_data_14_ ( + .CE(com_cmm_u_rx_pkt_proc_dw1_enable), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_rx_pkt_proc_nxt_cfg_wr_data[14]), + .Q(com_cmm_cfg_wr_data_14_), + .CLR(com_cmm_rst_351) + ); + FDCE com_cmm_u_rx_pkt_proc_cfg_wr_data_13_ ( + .CE(com_cmm_u_rx_pkt_proc_dw1_enable), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_rx_pkt_proc_nxt_cfg_wr_data[13]), + .Q(com_cmm_cfg_wr_data_13_), + .CLR(com_cmm_rst_351) + ); + FDCE com_cmm_u_rx_pkt_proc_cfg_wr_data_12_ ( + .CE(com_cmm_u_rx_pkt_proc_dw1_enable), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_rx_pkt_proc_nxt_cfg_wr_data[12]), + .Q(com_cmm_cfg_wr_data_12_), + .CLR(com_cmm_rst_351) + ); + FDCE com_cmm_u_rx_pkt_proc_cfg_wr_data_11_ ( + .CE(com_cmm_u_rx_pkt_proc_dw1_enable), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_rx_pkt_proc_nxt_cfg_wr_data[11]), + .Q(com_cmm_cfg_wr_data_11_), + .CLR(com_cmm_rst_351) + ); + FDCE com_cmm_u_rx_pkt_proc_cfg_wr_data_10_ ( + .CE(com_cmm_u_rx_pkt_proc_dw1_enable), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_rx_pkt_proc_nxt_cfg_wr_data[10]), + .Q(com_cmm_cfg_wr_data_10_), + .CLR(com_cmm_rst_351) + ); + FDCE com_cmm_u_rx_pkt_proc_cfg_wr_data_9_ ( + .CE(com_cmm_u_rx_pkt_proc_dw1_enable), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_rx_pkt_proc_nxt_cfg_wr_data[9]), + .Q(com_cmm_cfg_wr_data_9_), + .CLR(com_cmm_rst_351) + ); + FDCE com_cmm_u_rx_pkt_proc_cfg_wr_data_8_ ( + .CE(com_cmm_u_rx_pkt_proc_dw1_enable), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_rx_pkt_proc_nxt_cfg_wr_data[8]), + .Q(com_cmm_cfg_wr_data_8_), + .CLR(com_cmm_rst_351) + ); + FDCE com_cmm_u_rx_pkt_proc_cfg_wr_data_7_ ( + .CE(com_cmm_u_rx_pkt_proc_dw1_enable), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_rx_pkt_proc_nxt_cfg_wr_data[7]), + .Q(com_cmm_cfg_wr_data_7_), + .CLR(com_cmm_rst_351) + ); + FDCE com_cmm_u_rx_pkt_proc_cfg_wr_data_6_ ( + .CE(com_cmm_u_rx_pkt_proc_dw1_enable), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_rx_pkt_proc_nxt_cfg_wr_data[6]), + .Q(com_cmm_cfg_wr_data_6_), + .CLR(com_cmm_rst_351) + ); + FDCE com_cmm_u_rx_pkt_proc_cfg_wr_data_5_ ( + .CE(com_cmm_u_rx_pkt_proc_dw1_enable), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_rx_pkt_proc_nxt_cfg_wr_data[5]), + .Q(com_cmm_cfg_wr_data_5_), + .CLR(com_cmm_rst_351) + ); + FDCE com_cmm_u_rx_pkt_proc_cfg_wr_data_4_ ( + .CE(com_cmm_u_rx_pkt_proc_dw1_enable), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_rx_pkt_proc_nxt_cfg_wr_data[4]), + .Q(com_cmm_cfg_wr_data_4_), + .CLR(com_cmm_rst_351) + ); + FDCE com_cmm_u_rx_pkt_proc_cfg_wr_data_3_ ( + .CE(com_cmm_u_rx_pkt_proc_dw1_enable), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_rx_pkt_proc_nxt_cfg_wr_data[3]), + .Q(com_cmm_cfg_wr_data_3_), + .CLR(com_cmm_rst_351) + ); + FDCE com_cmm_u_rx_pkt_proc_cfg_wr_data_2_ ( + .CE(com_cmm_u_rx_pkt_proc_dw1_enable), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_rx_pkt_proc_nxt_cfg_wr_data[2]), + .Q(com_cmm_cfg_wr_data_2_), + .CLR(com_cmm_rst_351) + ); + FDCE com_cmm_u_rx_pkt_proc_cfg_wr_data_1_ ( + .CE(com_cmm_u_rx_pkt_proc_dw1_enable), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_rx_pkt_proc_nxt_cfg_wr_data[1]), + .Q(com_cmm_cfg_wr_data_1_), + .CLR(com_cmm_rst_351) + ); + FDCE com_cmm_u_rx_pkt_proc_cfg_wr_data_0_ ( + .CE(com_cmm_u_rx_pkt_proc_dw1_enable), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_rx_pkt_proc_nxt_cfg_wr_data[0]), + .Q(com_cmm_cfg_wr_data_0_), + .CLR(com_cmm_rst_351) + ); + FDCE com_cmm_u_rx_pkt_proc_req_valid ( + .CE(com_cmm_u_rx_pkt_proc_N_19515_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_rx_pkt_proc_N_86814_i_5356), + .Q(com_cmm_req_valid), + .CLR(com_cmm_rst_351) + ); + FDRE com_cmm_u_tx_pkt_proc_TLP_data_reg_0_ ( + .CE(com_cmm_u_tx_pkt_proc_N_60502_i_5392), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_tx_pkt_proc_TLP_data_reg_10_0_), + .Q(com_TLP_data_reg_0_), + .R(com_cmm_rst_351) + ); + FDRE com_cmm_u_tx_pkt_proc_TLP_data_reg_1_ ( + .CE(com_cmm_u_tx_pkt_proc_N_60502_i_5392), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_tx_pkt_proc_TLP_data_reg_10_1_), + .Q(com_TLP_data_reg_1_), + .R(com_cmm_rst_351) + ); + FDRE com_cmm_u_tx_pkt_proc_TLP_data_reg_2_ ( + .CE(com_cmm_u_tx_pkt_proc_N_60502_i_5392), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_tx_pkt_proc_TLP_data_reg_10_2_), + .Q(com_TLP_data_reg_2_), + .R(com_cmm_rst_351) + ); + FDRE com_cmm_u_tx_pkt_proc_TLP_data_reg_3_ ( + .CE(com_cmm_u_tx_pkt_proc_N_60502_i_5392), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_tx_pkt_proc_TLP_data_reg_10_3_), + .Q(com_TLP_data_reg_3_), + .R(com_cmm_rst_351) + ); + FDRE com_cmm_u_tx_pkt_proc_TLP_data_reg_4_ ( + .CE(com_cmm_u_tx_pkt_proc_N_60502_i_5392), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_tx_pkt_proc_TLP_data_reg_10_4_), + .Q(com_TLP_data_reg_4_), + .R(com_cmm_rst_351) + ); + FDRE com_cmm_u_tx_pkt_proc_TLP_data_reg_5_ ( + .CE(com_cmm_u_tx_pkt_proc_N_60502_i_5392), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_tx_pkt_proc_TLP_data_reg_10_5_), + .Q(com_TLP_data_reg_5_), + .R(com_cmm_rst_351) + ); + FDRE com_cmm_u_tx_pkt_proc_TLP_data_reg_6_ ( + .CE(com_cmm_u_tx_pkt_proc_N_60502_i_5392), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_tx_pkt_proc_TLP_data_reg_10_6_), + .Q(com_TLP_data_reg_6_), + .R(com_cmm_rst_351) + ); + FDRE com_cmm_u_tx_pkt_proc_TLP_data_reg_7_ ( + .CE(com_cmm_u_tx_pkt_proc_N_60502_i_5392), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_tx_pkt_proc_TLP_data_reg_10_7_), + .Q(com_TLP_data_reg_7_), + .R(com_cmm_rst_351) + ); + FDRE com_cmm_u_tx_pkt_proc_TLP_data_reg_8_ ( + .CE(com_cmm_u_tx_pkt_proc_N_60502_i_5392), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_tx_pkt_proc_TLP_data_reg_10_8_), + .Q(com_TLP_data_reg_8_), + .R(com_cmm_rst_351) + ); + FDRE com_cmm_u_tx_pkt_proc_TLP_data_reg_9_ ( + .CE(com_cmm_u_tx_pkt_proc_N_60502_i_5392), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_tx_pkt_proc_TLP_data_reg_10_9_), + .Q(com_TLP_data_reg_9_), + .R(com_cmm_rst_351) + ); + FDRE com_cmm_u_tx_pkt_proc_TLP_data_reg_10_ ( + .CE(com_cmm_u_tx_pkt_proc_N_60502_i_5392), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_tx_pkt_proc_TLP_data_reg_10_10_), + .Q(com_TLP_data_reg_10_), + .R(com_cmm_rst_351) + ); + FDRE com_cmm_u_tx_pkt_proc_TLP_data_reg_11_ ( + .CE(com_cmm_u_tx_pkt_proc_N_60502_i_5392), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_tx_pkt_proc_TLP_data_reg_10_11_), + .Q(com_TLP_data_reg_11_), + .R(com_cmm_rst_351) + ); + FDRE com_cmm_u_tx_pkt_proc_TLP_data_reg_12_ ( + .CE(com_cmm_u_tx_pkt_proc_N_60502_i_5392), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_tx_pkt_proc_TLP_data_reg_10_12_), + .Q(com_cmm_u_tx_pkt_proc_TLP_data_reg_12__5358), + .R(com_cmm_rst_351) + ); + FDRE com_cmm_u_tx_pkt_proc_TLP_data_reg_13_ ( + .CE(com_cmm_u_tx_pkt_proc_N_60502_i_5392), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_tx_pkt_proc_TLP_data_reg_10_13_), + .Q(com_cmm_u_tx_pkt_proc_TLP_data_reg_13__5359), + .R(com_cmm_rst_351) + ); + FDRE com_cmm_u_tx_pkt_proc_TLP_data_reg_14_ ( + .CE(com_cmm_u_tx_pkt_proc_N_60502_i_5392), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_tx_pkt_proc_TLP_data_reg_10_14_), + .Q(com_TLP_data_reg_14_), + .R(com_cmm_rst_351) + ); + FDRE com_cmm_u_tx_pkt_proc_TLP_data_reg_15_ ( + .CE(com_cmm_u_tx_pkt_proc_N_60502_i_5392), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_tx_pkt_proc_TLP_data_reg_10_15_), + .Q(com_TLP_data_reg_15_), + .R(com_cmm_rst_351) + ); + FDRE com_cmm_u_tx_pkt_proc_TLP_data_reg_16_ ( + .CE(com_cmm_u_tx_pkt_proc_N_60502_i_5392), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_tx_pkt_proc_N_43007_i), + .Q(com_TLP_data_reg_16_), + .R(com_cmm_rst_351) + ); + FDRE com_cmm_u_tx_pkt_proc_TLP_data_reg_17_ ( + .CE(com_cmm_u_tx_pkt_proc_N_60502_i_5392), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_tx_pkt_proc_N_43009_i), + .Q(com_TLP_data_reg_17_), + .R(com_cmm_rst_351) + ); + FDRE com_cmm_u_tx_pkt_proc_TLP_data_reg_18_ ( + .CE(com_cmm_u_tx_pkt_proc_N_60502_i_5392), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_tx_pkt_proc_N_43011_i), + .Q(com_TLP_data_reg_18_), + .R(com_cmm_rst_351) + ); + FDRE com_cmm_u_tx_pkt_proc_TLP_data_reg_19_ ( + .CE(com_cmm_u_tx_pkt_proc_N_60502_i_5392), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_tx_pkt_proc_N_43013_i), + .Q(com_TLP_data_reg_19_), + .R(com_cmm_rst_351) + ); + FDRE com_cmm_u_tx_pkt_proc_TLP_data_reg_20_ ( + .CE(com_cmm_u_tx_pkt_proc_N_60502_i_5392), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_tx_pkt_proc_N_43015_i), + .Q(com_cmm_u_tx_pkt_proc_TLP_data_reg_20__5360), + .R(com_cmm_rst_351) + ); + FDRE com_cmm_u_tx_pkt_proc_TLP_data_reg_21_ ( + .CE(com_cmm_u_tx_pkt_proc_N_60502_i_5392), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_tx_pkt_proc_N_43017_i), + .Q(com_cmm_u_tx_pkt_proc_TLP_data_reg_21__5361), + .R(com_cmm_rst_351) + ); + FDRE com_cmm_u_tx_pkt_proc_TLP_data_reg_22_ ( + .CE(com_cmm_u_tx_pkt_proc_N_60502_i_5392), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_tx_pkt_proc_N_43019_i), + .Q(com_cmm_u_tx_pkt_proc_TLP_data_reg_22__5388), + .R(com_cmm_rst_351) + ); + FDRE com_cmm_u_tx_pkt_proc_TLP_data_reg_23_ ( + .CE(com_cmm_u_tx_pkt_proc_N_60502_i_5392), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_tx_pkt_proc_N_43021_i), + .Q(com_TLP_data_reg_23_), + .R(com_cmm_rst_351) + ); + FDRE com_cmm_u_tx_pkt_proc_TLP_data_reg_24_ ( + .CE(com_cmm_u_tx_pkt_proc_N_60502_i_5392), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_tx_pkt_proc_N_43023_i), + .Q(com_cmm_u_tx_pkt_proc_TLP_data_reg_24__5389), + .R(com_cmm_rst_351) + ); + FDRE com_cmm_u_tx_pkt_proc_TLP_data_reg_25_ ( + .CE(com_cmm_u_tx_pkt_proc_N_60502_i_5392), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_tx_pkt_proc_N_43025_i), + .Q(com_TLP_data_reg_25_), + .R(com_cmm_rst_351) + ); + FDRE com_cmm_u_tx_pkt_proc_TLP_data_reg_26_ ( + .CE(com_cmm_u_tx_pkt_proc_N_60502_i_5392), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_tx_pkt_proc_N_43027_i), + .Q(com_cmm_u_tx_pkt_proc_TLP_data_reg_26__5390), + .R(com_cmm_rst_351) + ); + FDRE com_cmm_u_tx_pkt_proc_TLP_data_reg_27_ ( + .CE(com_cmm_u_tx_pkt_proc_N_60502_i_5392), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_tx_pkt_proc_N_43029_i), + .Q(com_TLP_data_reg_27_), + .R(com_cmm_rst_351) + ); + FDRE com_cmm_u_tx_pkt_proc_TLP_data_reg_28_ ( + .CE(com_cmm_u_tx_pkt_proc_N_60502_i_5392), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_tx_pkt_proc_N_43031_i), + .Q(com_cmm_u_tx_pkt_proc_TLP_data_reg_28__5391), + .R(com_cmm_rst_351) + ); + FDRE com_cmm_u_tx_pkt_proc_TLP_data_reg_29_ ( + .CE(com_cmm_u_tx_pkt_proc_N_60502_i_5392), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_tx_pkt_proc_N_43033_i), + .Q(com_TLP_data_reg_29_), + .R(com_cmm_rst_351) + ); + FDRE com_cmm_u_tx_pkt_proc_TLP_data_reg_30_ ( + .CE(com_cmm_u_tx_pkt_proc_N_60502_i_5392), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_tx_pkt_proc_N_43035_i), + .Q(com_TLP_data_reg_30_), + .R(com_cmm_rst_351) + ); + FDRE com_cmm_u_tx_pkt_proc_TLP_data_reg_31_ ( + .CE(com_cmm_u_tx_pkt_proc_N_60502_i_5392), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_tx_pkt_proc_N_43037_i), + .Q(com_TLP_data_reg_31_), + .R(com_cmm_rst_351) + ); + FDRE com_cmm_u_tx_pkt_proc_TLP_data_reg_32_ ( + .CE(com_cmm_u_tx_pkt_proc_N_60502_i_5392), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_tx_pkt_proc_TLP_data_reg_10_32_), + .Q(com_cmm_u_tx_pkt_proc_TLP_data_reg_32__5387), + .R(com_cmm_rst_351) + ); + FDRE com_cmm_u_tx_pkt_proc_TLP_data_reg_33_ ( + .CE(com_cmm_u_tx_pkt_proc_N_60502_i_5392), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_tx_pkt_proc_TLP_data_reg_10_33_), + .Q(com_cmm_u_tx_pkt_proc_TLP_data_reg_33__5382), + .R(com_cmm_rst_351) + ); + FDRE com_cmm_u_tx_pkt_proc_TLP_data_reg_34_ ( + .CE(com_cmm_u_tx_pkt_proc_N_60502_i_5392), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_tx_pkt_proc_TLP_data_reg_10_34_), + .Q(com_cmm_u_tx_pkt_proc_TLP_data_reg_34__5383), + .R(com_cmm_rst_351) + ); + FDRE com_cmm_u_tx_pkt_proc_TLP_data_reg_35_ ( + .CE(com_cmm_u_tx_pkt_proc_N_60502_i_5392), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_tx_pkt_proc_TLP_data_reg_10_35_), + .Q(com_cmm_u_tx_pkt_proc_TLP_data_reg_35__5384), + .R(com_cmm_rst_351) + ); + FDRE com_cmm_u_tx_pkt_proc_TLP_data_reg_36_ ( + .CE(com_cmm_u_tx_pkt_proc_N_60502_i_5392), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_tx_pkt_proc_TLP_data_reg_10_36_), + .Q(com_cmm_u_tx_pkt_proc_TLP_data_reg_36__5385), + .R(com_cmm_rst_351) + ); + FDRE com_cmm_u_tx_pkt_proc_TLP_data_reg_37_ ( + .CE(com_cmm_u_tx_pkt_proc_N_60502_i_5392), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_tx_pkt_proc_TLP_data_reg_10_37_), + .Q(com_cmm_u_tx_pkt_proc_TLP_data_reg_37__5386), + .R(com_cmm_rst_351) + ); + FDRE com_cmm_u_tx_pkt_proc_TLP_data_reg_38_ ( + .CE(com_cmm_u_tx_pkt_proc_N_60502_i_5392), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_tx_pkt_proc_TLP_data_reg_10_38_), + .Q(com_cmm_u_tx_pkt_proc_TLP_data_reg_38__5377), + .R(com_cmm_rst_351) + ); + FDRE com_cmm_u_tx_pkt_proc_TLP_data_reg_39_ ( + .CE(com_cmm_u_tx_pkt_proc_N_60502_i_5392), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_tx_pkt_proc_TLP_data_reg_10_39_), + .Q(com_cmm_u_tx_pkt_proc_TLP_data_reg_39__5378), + .R(com_cmm_rst_351) + ); + FDRE com_cmm_u_tx_pkt_proc_TLP_data_reg_40_ ( + .CE(com_cmm_u_tx_pkt_proc_N_60502_i_5392), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_tx_pkt_proc_TLP_data_reg_10_40_), + .Q(com_cmm_u_tx_pkt_proc_TLP_data_reg_40__5379), + .R(com_cmm_rst_351) + ); + FDRE com_cmm_u_tx_pkt_proc_TLP_data_reg_41_ ( + .CE(com_cmm_u_tx_pkt_proc_N_60502_i_5392), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_tx_pkt_proc_TLP_data_reg_10_41_), + .Q(com_cmm_u_tx_pkt_proc_TLP_data_reg_41__5380), + .R(com_cmm_rst_351) + ); + FDRE com_cmm_u_tx_pkt_proc_TLP_data_reg_42_ ( + .CE(com_cmm_u_tx_pkt_proc_N_60502_i_5392), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_tx_pkt_proc_TLP_data_reg_10_42_), + .Q(com_cmm_u_tx_pkt_proc_TLP_data_reg_42__5381), + .R(com_cmm_rst_351) + ); + FDRE com_cmm_u_tx_pkt_proc_TLP_data_reg_43_ ( + .CE(com_cmm_u_tx_pkt_proc_N_60502_i_5392), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_tx_pkt_proc_TLP_data_reg_10_43_), + .Q(com_cmm_u_tx_pkt_proc_TLP_data_reg_43__5372), + .R(com_cmm_rst_351) + ); + FDRE com_cmm_u_tx_pkt_proc_TLP_data_reg_44_ ( + .CE(com_cmm_u_tx_pkt_proc_N_60502_i_5392), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_tx_pkt_proc_TLP_data_reg_10_44_), + .Q(com_TLP_data_reg_44_), + .R(com_cmm_rst_351) + ); + FDRE com_cmm_u_tx_pkt_proc_TLP_data_reg_45_ ( + .CE(com_cmm_u_tx_pkt_proc_N_60502_i_5392), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_tx_pkt_proc_TLP_data_reg_10_45_), + .Q(com_cmm_u_tx_pkt_proc_TLP_data_reg_45__5373), + .R(com_cmm_rst_351) + ); + FDRE com_cmm_u_tx_pkt_proc_TLP_data_reg_46_ ( + .CE(com_cmm_u_tx_pkt_proc_N_60502_i_5392), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_tx_pkt_proc_TLP_data_reg_10_46_), + .Q(com_TLP_data_reg_46_), + .R(com_cmm_rst_351) + ); + FDRE com_cmm_u_tx_pkt_proc_TLP_data_reg_47_ ( + .CE(com_cmm_u_tx_pkt_proc_N_60502_i_5392), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_tx_pkt_proc_TLP_data_reg_10_47_), + .Q(com_cmm_u_tx_pkt_proc_TLP_data_reg_47__5374), + .R(com_cmm_rst_351) + ); + FDRE com_cmm_u_tx_pkt_proc_TLP_data_reg_48_ ( + .CE(com_cmm_u_tx_pkt_proc_N_60502_i_5392), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_tx_pkt_proc_TLP_data_reg_10_48_), + .Q(com_TLP_data_reg_48_), + .R(com_cmm_rst_351) + ); + FDRE com_cmm_u_tx_pkt_proc_TLP_data_reg_49_ ( + .CE(com_cmm_u_tx_pkt_proc_N_60502_i_5392), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_tx_pkt_proc_TLP_data_reg_10_49_), + .Q(com_TLP_data_reg_49_), + .R(com_cmm_rst_351) + ); + FDRE com_cmm_u_tx_pkt_proc_TLP_data_reg_50_ ( + .CE(com_cmm_u_tx_pkt_proc_N_60502_i_5392), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_tx_pkt_proc_TLP_data_reg_10_50_), + .Q(com_TLP_data_reg_50_), + .R(com_cmm_rst_351) + ); + FDRE com_cmm_u_tx_pkt_proc_TLP_data_reg_51_ ( + .CE(com_cmm_u_tx_pkt_proc_N_60502_i_5392), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_tx_pkt_proc_TLP_data_reg_10_51_), + .Q(com_cmm_u_tx_pkt_proc_TLP_data_reg_51__5375), + .R(com_cmm_rst_351) + ); + FDRE com_cmm_u_tx_pkt_proc_TLP_data_reg_52_ ( + .CE(com_cmm_u_tx_pkt_proc_N_60502_i_5392), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_tx_pkt_proc_TLP_data_reg_10_52_), + .Q(com_cmm_u_tx_pkt_proc_TLP_data_reg_52__5376), + .R(com_cmm_rst_351) + ); + FDRE com_cmm_u_tx_pkt_proc_TLP_data_reg_53_ ( + .CE(com_cmm_u_tx_pkt_proc_N_60502_i_5392), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_tx_pkt_proc_TLP_data_reg_10_53_), + .Q(com_cmm_u_tx_pkt_proc_TLP_data_reg_53__5367), + .R(com_cmm_rst_351) + ); + FDRE com_cmm_u_tx_pkt_proc_TLP_data_reg_54_ ( + .CE(com_cmm_u_tx_pkt_proc_N_60502_i_5392), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_tx_pkt_proc_TLP_data_reg_10_54_), + .Q(com_cmm_u_tx_pkt_proc_TLP_data_reg_54__5368), + .R(com_cmm_rst_351) + ); + FDRE com_cmm_u_tx_pkt_proc_TLP_data_reg_55_ ( + .CE(com_cmm_u_tx_pkt_proc_N_60502_i_5392), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_tx_pkt_proc_TLP_data_reg_10_55_), + .Q(com_cmm_u_tx_pkt_proc_TLP_data_reg_55__5369), + .R(com_cmm_rst_351) + ); + FDRE com_cmm_u_tx_pkt_proc_TLP_data_reg_56_ ( + .CE(com_cmm_u_tx_pkt_proc_N_60502_i_5392), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_tx_pkt_proc_TLP_data_reg_10_56_), + .Q(com_cmm_u_tx_pkt_proc_TLP_data_reg_56__5370), + .R(com_cmm_rst_351) + ); + FDRE com_cmm_u_tx_pkt_proc_TLP_data_reg_57_ ( + .CE(com_cmm_u_tx_pkt_proc_N_60502_i_5392), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_tx_pkt_proc_TLP_data_reg_10_57_), + .Q(com_cmm_u_tx_pkt_proc_TLP_data_reg_57__5371), + .R(com_cmm_rst_351) + ); + FDRE com_cmm_u_tx_pkt_proc_TLP_data_reg_58_ ( + .CE(com_cmm_u_tx_pkt_proc_N_60502_i_5392), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_tx_pkt_proc_TLP_data_reg_10_58_), + .Q(com_cmm_u_tx_pkt_proc_TLP_data_reg_58__5362), + .R(com_cmm_rst_351) + ); + FDRE com_cmm_u_tx_pkt_proc_TLP_data_reg_59_ ( + .CE(com_cmm_u_tx_pkt_proc_N_60502_i_5392), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_tx_pkt_proc_TLP_data_reg_10_59_), + .Q(com_cmm_u_tx_pkt_proc_TLP_data_reg_59__5363), + .R(com_cmm_rst_351) + ); + FDRE com_cmm_u_tx_pkt_proc_TLP_data_reg_60_ ( + .CE(com_cmm_u_tx_pkt_proc_N_60502_i_5392), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_tx_pkt_proc_TLP_data_reg_10_60_), + .Q(com_cmm_u_tx_pkt_proc_TLP_data_reg_60__5364), + .R(com_cmm_rst_351) + ); + FDRE com_cmm_u_tx_pkt_proc_TLP_data_reg_61_ ( + .CE(com_cmm_u_tx_pkt_proc_N_60502_i_5392), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_tx_pkt_proc_TLP_data_reg_10_61_), + .Q(com_cmm_u_tx_pkt_proc_TLP_data_reg_61__5365), + .R(com_cmm_rst_351) + ); + FDRE com_cmm_u_tx_pkt_proc_TLP_data_reg_62_ ( + .CE(com_cmm_u_tx_pkt_proc_N_60502_i_5392), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_tx_pkt_proc_TLP_data_reg_10_62_), + .Q(com_cmm_u_tx_pkt_proc_TLP_data_reg_62__5366), + .R(com_cmm_rst_351) + ); + FDRE com_cmm_u_tx_pkt_proc_TLP_data_reg_63_ ( + .CE(com_cmm_u_tx_pkt_proc_N_60502_i_5392), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_tx_pkt_proc_TLP_data_reg_10_63_), + .Q(com_cmm_u_tx_pkt_proc_TLP_data_reg_63__5357), + .R(com_cmm_rst_351) + ); + defparam com_cmm_u_tx_pkt_proc_cmmt_trem_n_0_sqmuxa_0_a2_0_a3_0_a3.INIT = 4'h8; + LUT2 com_cmm_u_tx_pkt_proc_cmmt_trem_n_0_sqmuxa_0_a2_0_a3_0_a3 ( + .I0(com_cmm_req_pkt_tx), + .I1(com_state[0]), + .O(com_cmmt_trem_n_0_sqmuxa) + ); + defparam com_cmm_u_tx_pkt_proc_cmmt_td_i_0_0_o3_60_.INIT = 4'h4; + LUT2 com_cmm_u_tx_pkt_proc_cmmt_td_i_0_0_o3_60_ ( + .I0(com_cmm_req_pkt_tx), + .I1(com_state[0]), + .O(com_N_55880_i) + ); + defparam com_cmm_u_tx_pkt_proc_next_state_0_i_0_o3_0_2_.INIT = 4'h8; + LUT2 com_cmm_u_tx_pkt_proc_next_state_0_i_0_o3_0_2_ ( + .I0(com_tlp_data_0_), + .I1(com_tlp_data_29_), + .O(com_N_56344_i) + ); + defparam com_cmm_u_tx_pkt_proc_next_state_0_i_0_o3_2_.INIT = 4'h1; + LUT2 com_cmm_u_tx_pkt_proc_next_state_0_i_0_o3_2_ ( + .I0(com_cmm_gnt_pkt_tx), + .I1(com_cmm_u_tx_pkt_proc_state[4]), + .O(com_N_55871_i) + ); + defparam com_cmm_u_tx_pkt_proc_cmmt_td_0_i_m2_i_m3_i_m3_0_31_.INIT = 8'hAC; + LUT3 com_cmm_u_tx_pkt_proc_cmmt_td_0_i_m2_i_m3_i_m3_0_31_ ( + .I0(com_cmm_tlp_data_63_), + .I1(com_cmm_u_tx_pkt_proc_TLP_data_reg_63__5357), + .I2(com_state[0]), + .O(com_N_63630) + ); + defparam com_cmm_u_tx_pkt_proc_cmmt_td_0_i_m2_i_m3_i_m3_0_44_.INIT = 8'hAC; + LUT3 com_cmm_u_tx_pkt_proc_cmmt_td_0_i_m2_i_m3_i_m3_0_44_ ( + .I0(com_cmm_tlp_data_12_), + .I1(com_cmm_u_tx_pkt_proc_TLP_data_reg_12__5358), + .I2(com_state[0]), + .O(com_N_63631) + ); + defparam com_cmm_u_tx_pkt_proc_cmmt_td_0_i_m2_i_m3_i_m3_0_45_.INIT = 8'hAC; + LUT3 com_cmm_u_tx_pkt_proc_cmmt_td_0_i_m2_i_m3_i_m3_0_45_ ( + .I0(com_cmm_tlp_data_13_), + .I1(com_cmm_u_tx_pkt_proc_TLP_data_reg_13__5359), + .I2(com_state[0]), + .O(com_N_63632) + ); + defparam com_cmm_u_tx_pkt_proc_cmmt_td_0_i_m2_i_m3_i_m3_0_52_.INIT = 8'hAC; + LUT3 com_cmm_u_tx_pkt_proc_cmmt_td_0_i_m2_i_m3_i_m3_0_52_ ( + .I0(com_cmm_tlp_data_20_), + .I1(com_cmm_u_tx_pkt_proc_TLP_data_reg_20__5360), + .I2(com_state[0]), + .O(com_N_63633) + ); + defparam com_cmm_u_tx_pkt_proc_cmmt_td_0_i_m2_i_m3_i_m3_0_53_.INIT = 8'hAC; + LUT3 com_cmm_u_tx_pkt_proc_cmmt_td_0_i_m2_i_m3_i_m3_0_53_ ( + .I0(com_cmm_tlp_data_21_), + .I1(com_cmm_u_tx_pkt_proc_TLP_data_reg_21__5361), + .I2(com_state[0]), + .O(com_N_63634) + ); + defparam com_cmm_u_tx_pkt_proc_cmmt_td_0_i_m2_i_m3_i_m3_0_26_.INIT = 8'hAC; + LUT3 com_cmm_u_tx_pkt_proc_cmmt_td_0_i_m2_i_m3_i_m3_0_26_ ( + .I0(com_cmm_tlp_data_58_), + .I1(com_cmm_u_tx_pkt_proc_TLP_data_reg_58__5362), + .I2(com_state[0]), + .O(com_N_63635) + ); + defparam com_cmm_u_tx_pkt_proc_cmmt_td_0_i_m2_i_m3_i_m3_0_27_.INIT = 8'hAC; + LUT3 com_cmm_u_tx_pkt_proc_cmmt_td_0_i_m2_i_m3_i_m3_0_27_ ( + .I0(com_cmm_tlp_data_59_), + .I1(com_cmm_u_tx_pkt_proc_TLP_data_reg_59__5363), + .I2(com_state[0]), + .O(com_N_63636) + ); + defparam com_cmm_u_tx_pkt_proc_cmmt_td_0_i_m2_i_m3_i_m3_0_28_.INIT = 8'hAC; + LUT3 com_cmm_u_tx_pkt_proc_cmmt_td_0_i_m2_i_m3_i_m3_0_28_ ( + .I0(com_cmm_tlp_data_60_), + .I1(com_cmm_u_tx_pkt_proc_TLP_data_reg_60__5364), + .I2(com_state[0]), + .O(com_N_63637) + ); + defparam com_cmm_u_tx_pkt_proc_cmmt_td_0_i_m2_i_m3_i_m3_0_29_.INIT = 8'hAC; + LUT3 com_cmm_u_tx_pkt_proc_cmmt_td_0_i_m2_i_m3_i_m3_0_29_ ( + .I0(com_cmm_tlp_data_61_), + .I1(com_cmm_u_tx_pkt_proc_TLP_data_reg_61__5365), + .I2(com_state[0]), + .O(com_N_63638) + ); + defparam com_cmm_u_tx_pkt_proc_cmmt_td_0_i_m2_i_m3_i_m3_0_30_.INIT = 8'hAC; + LUT3 com_cmm_u_tx_pkt_proc_cmmt_td_0_i_m2_i_m3_i_m3_0_30_ ( + .I0(com_cmm_tlp_data_62_), + .I1(com_cmm_u_tx_pkt_proc_TLP_data_reg_62__5366), + .I2(com_state[0]), + .O(com_N_63639) + ); + defparam com_cmm_u_tx_pkt_proc_cmmt_td_0_i_m2_i_m3_i_m3_0_21_.INIT = 8'hAC; + LUT3 com_cmm_u_tx_pkt_proc_cmmt_td_0_i_m2_i_m3_i_m3_0_21_ ( + .I0(com_cmm_tlp_data_53_), + .I1(com_cmm_u_tx_pkt_proc_TLP_data_reg_53__5367), + .I2(com_state[0]), + .O(com_N_63640) + ); + defparam com_cmm_u_tx_pkt_proc_cmmt_td_0_i_m2_i_m3_i_m3_0_22_.INIT = 8'hAC; + LUT3 com_cmm_u_tx_pkt_proc_cmmt_td_0_i_m2_i_m3_i_m3_0_22_ ( + .I0(com_cmm_tlp_data_54_), + .I1(com_cmm_u_tx_pkt_proc_TLP_data_reg_54__5368), + .I2(com_state[0]), + .O(com_N_63641) + ); + defparam com_cmm_u_tx_pkt_proc_cmmt_td_0_i_m2_i_m3_i_m3_0_23_.INIT = 8'hAC; + LUT3 com_cmm_u_tx_pkt_proc_cmmt_td_0_i_m2_i_m3_i_m3_0_23_ ( + .I0(com_cmm_tlp_data_55_), + .I1(com_cmm_u_tx_pkt_proc_TLP_data_reg_55__5369), + .I2(com_state[0]), + .O(com_N_63642) + ); + defparam com_cmm_u_tx_pkt_proc_cmmt_td_0_i_m2_i_m3_i_m3_0_24_.INIT = 8'hAC; + LUT3 com_cmm_u_tx_pkt_proc_cmmt_td_0_i_m2_i_m3_i_m3_0_24_ ( + .I0(com_cmm_tlp_data_56_), + .I1(com_cmm_u_tx_pkt_proc_TLP_data_reg_56__5370), + .I2(com_state[0]), + .O(com_N_63643) + ); + defparam com_cmm_u_tx_pkt_proc_cmmt_td_0_i_m2_i_m3_i_m3_0_25_.INIT = 8'hAC; + LUT3 com_cmm_u_tx_pkt_proc_cmmt_td_0_i_m2_i_m3_i_m3_0_25_ ( + .I0(com_cmm_tlp_data_57_), + .I1(com_cmm_u_tx_pkt_proc_TLP_data_reg_57__5371), + .I2(com_state[0]), + .O(com_N_63644) + ); + defparam com_cmm_u_tx_pkt_proc_cmmt_td_0_i_m2_i_m3_i_m3_0_11_.INIT = 8'hAC; + LUT3 com_cmm_u_tx_pkt_proc_cmmt_td_0_i_m2_i_m3_i_m3_0_11_ ( + .I0(com_cmm_tlp_data_43_), + .I1(com_cmm_u_tx_pkt_proc_TLP_data_reg_43__5372), + .I2(com_state[0]), + .O(com_N_63645) + ); + defparam com_cmm_u_tx_pkt_proc_cmmt_td_0_i_m2_i_m3_i_m3_0_13_.INIT = 8'hAC; + LUT3 com_cmm_u_tx_pkt_proc_cmmt_td_0_i_m2_i_m3_i_m3_0_13_ ( + .I0(com_cmm_tlp_data_45_), + .I1(com_cmm_u_tx_pkt_proc_TLP_data_reg_45__5373), + .I2(com_state[0]), + .O(com_N_63646) + ); + defparam com_cmm_u_tx_pkt_proc_cmmt_td_0_i_m2_i_m3_i_m3_0_15_.INIT = 8'hAC; + LUT3 com_cmm_u_tx_pkt_proc_cmmt_td_0_i_m2_i_m3_i_m3_0_15_ ( + .I0(com_cmm_tlp_data_47_), + .I1(com_cmm_u_tx_pkt_proc_TLP_data_reg_47__5374), + .I2(com_state[0]), + .O(com_N_63647) + ); + defparam com_cmm_u_tx_pkt_proc_cmmt_td_0_i_m2_i_m3_i_m3_0_19_.INIT = 8'hAC; + LUT3 com_cmm_u_tx_pkt_proc_cmmt_td_0_i_m2_i_m3_i_m3_0_19_ ( + .I0(com_cmm_tlp_data_51_), + .I1(com_cmm_u_tx_pkt_proc_TLP_data_reg_51__5375), + .I2(com_state[0]), + .O(com_N_63648) + ); + defparam com_cmm_u_tx_pkt_proc_cmmt_td_0_i_m2_i_m3_i_m3_0_20_.INIT = 8'hAC; + LUT3 com_cmm_u_tx_pkt_proc_cmmt_td_0_i_m2_i_m3_i_m3_0_20_ ( + .I0(com_cmm_tlp_data_52_), + .I1(com_cmm_u_tx_pkt_proc_TLP_data_reg_52__5376), + .I2(com_state[0]), + .O(com_N_63649) + ); + defparam com_cmm_u_tx_pkt_proc_cmmt_td_0_i_m2_i_m3_i_m3_0_6_.INIT = 8'hAC; + LUT3 com_cmm_u_tx_pkt_proc_cmmt_td_0_i_m2_i_m3_i_m3_0_6_ ( + .I0(com_cmm_tlp_data_38_), + .I1(com_cmm_u_tx_pkt_proc_TLP_data_reg_38__5377), + .I2(com_state[0]), + .O(com_N_63650) + ); + defparam com_cmm_u_tx_pkt_proc_cmmt_td_0_i_m2_i_m3_i_m3_0_7_.INIT = 8'hAC; + LUT3 com_cmm_u_tx_pkt_proc_cmmt_td_0_i_m2_i_m3_i_m3_0_7_ ( + .I0(com_cmm_tlp_data_39_), + .I1(com_cmm_u_tx_pkt_proc_TLP_data_reg_39__5378), + .I2(com_state[0]), + .O(com_N_63651) + ); + defparam com_cmm_u_tx_pkt_proc_cmmt_td_0_i_m2_i_m3_i_m3_0_8_.INIT = 8'hAC; + LUT3 com_cmm_u_tx_pkt_proc_cmmt_td_0_i_m2_i_m3_i_m3_0_8_ ( + .I0(com_cmm_tlp_data_40_), + .I1(com_cmm_u_tx_pkt_proc_TLP_data_reg_40__5379), + .I2(com_state[0]), + .O(com_N_63652) + ); + defparam com_cmm_u_tx_pkt_proc_cmmt_td_0_i_m2_i_m3_i_m3_0_9_.INIT = 8'hAC; + LUT3 com_cmm_u_tx_pkt_proc_cmmt_td_0_i_m2_i_m3_i_m3_0_9_ ( + .I0(com_cmm_tlp_data_41_), + .I1(com_cmm_u_tx_pkt_proc_TLP_data_reg_41__5380), + .I2(com_state[0]), + .O(com_N_63653) + ); + defparam com_cmm_u_tx_pkt_proc_cmmt_td_0_i_m2_i_m3_i_m3_0_10_.INIT = 8'hAC; + LUT3 com_cmm_u_tx_pkt_proc_cmmt_td_0_i_m2_i_m3_i_m3_0_10_ ( + .I0(com_cmm_tlp_data_42_), + .I1(com_cmm_u_tx_pkt_proc_TLP_data_reg_42__5381), + .I2(com_state[0]), + .O(com_N_63654) + ); + defparam com_cmm_u_tx_pkt_proc_cmmt_td_0_i_m2_i_m3_i_m3_0_1_.INIT = 8'hAC; + LUT3 com_cmm_u_tx_pkt_proc_cmmt_td_0_i_m2_i_m3_i_m3_0_1_ ( + .I0(com_cmm_tlp_data_33_), + .I1(com_cmm_u_tx_pkt_proc_TLP_data_reg_33__5382), + .I2(com_state[0]), + .O(com_N_63655) + ); + defparam com_cmm_u_tx_pkt_proc_cmmt_td_0_i_m2_i_m3_i_m3_0_2_.INIT = 8'hAC; + LUT3 com_cmm_u_tx_pkt_proc_cmmt_td_0_i_m2_i_m3_i_m3_0_2_ ( + .I0(com_cmm_tlp_data_34_), + .I1(com_cmm_u_tx_pkt_proc_TLP_data_reg_34__5383), + .I2(com_state[0]), + .O(com_N_63656) + ); + defparam com_cmm_u_tx_pkt_proc_cmmt_td_0_i_m2_i_m3_i_m3_0_3_.INIT = 8'hAC; + LUT3 com_cmm_u_tx_pkt_proc_cmmt_td_0_i_m2_i_m3_i_m3_0_3_ ( + .I0(com_cmm_tlp_data_35_), + .I1(com_cmm_u_tx_pkt_proc_TLP_data_reg_35__5384), + .I2(com_state[0]), + .O(com_N_63657) + ); + defparam com_cmm_u_tx_pkt_proc_cmmt_td_0_i_m2_i_m3_i_m3_0_4_.INIT = 8'hAC; + LUT3 com_cmm_u_tx_pkt_proc_cmmt_td_0_i_m2_i_m3_i_m3_0_4_ ( + .I0(com_cmm_tlp_data_36_), + .I1(com_cmm_u_tx_pkt_proc_TLP_data_reg_36__5385), + .I2(com_state[0]), + .O(com_N_63658) + ); + defparam com_cmm_u_tx_pkt_proc_cmmt_td_0_i_m2_i_m3_i_m3_0_5_.INIT = 8'hAC; + LUT3 com_cmm_u_tx_pkt_proc_cmmt_td_0_i_m2_i_m3_i_m3_0_5_ ( + .I0(com_cmm_tlp_data_37_), + .I1(com_cmm_u_tx_pkt_proc_TLP_data_reg_37__5386), + .I2(com_state[0]), + .O(com_N_63659) + ); + defparam com_cmm_u_tx_pkt_proc_cmmt_td_0_i_m2_i_m3_i_m3_0_0_.INIT = 8'hAC; + LUT3 com_cmm_u_tx_pkt_proc_cmmt_td_0_i_m2_i_m3_i_m3_0_0_ ( + .I0(com_cmm_tlp_data_32_), + .I1(com_cmm_u_tx_pkt_proc_TLP_data_reg_32__5387), + .I2(com_state[0]), + .O(com_N_63660) + ); + defparam com_cmm_u_tx_pkt_proc_cmmt_td_0_i_m2_i_m3_i_m3_0_54_.INIT = 8'hAC; + LUT3 com_cmm_u_tx_pkt_proc_cmmt_td_0_i_m2_i_m3_i_m3_0_54_ ( + .I0(com_cmm_tlp_data_22_), + .I1(com_cmm_u_tx_pkt_proc_TLP_data_reg_22__5388), + .I2(com_state[0]), + .O(com_N_63661) + ); + defparam com_cmm_u_tx_pkt_proc_cmmt_td_0_i_m2_i_m3_i_m3_0_56_.INIT = 8'hAC; + LUT3 com_cmm_u_tx_pkt_proc_cmmt_td_0_i_m2_i_m3_i_m3_0_56_ ( + .I0(com_cmm_tlp_data_24_), + .I1(com_cmm_u_tx_pkt_proc_TLP_data_reg_24__5389), + .I2(com_state[0]), + .O(com_N_63662) + ); + defparam com_cmm_u_tx_pkt_proc_cmmt_td_0_i_m2_i_m3_i_m3_0_58_.INIT = 8'hAC; + LUT3 com_cmm_u_tx_pkt_proc_cmmt_td_0_i_m2_i_m3_i_m3_0_58_ ( + .I0(com_cmm_tlp_data_26_), + .I1(com_cmm_u_tx_pkt_proc_TLP_data_reg_26__5390), + .I2(com_state[0]), + .O(com_N_63663) + ); + defparam com_cmm_u_tx_pkt_proc_cmmt_td_0_i_m2_i_m3_i_m3_0_60_.INIT = 8'hAC; + LUT3 com_cmm_u_tx_pkt_proc_cmmt_td_0_i_m2_i_m3_i_m3_0_60_ ( + .I0(com_cmm_tlp_data_28_), + .I1(com_cmm_u_tx_pkt_proc_TLP_data_reg_28__5391), + .I2(com_state[0]), + .O(com_N_63664) + ); + defparam com_cmm_u_tx_pkt_proc_next_state_0_i_0_o2_2_.INIT = 8'h2A; + LUT3 com_cmm_u_tx_pkt_proc_next_state_0_i_0_o2_2_ ( + .I0(com_N_55871_i), + .I1(com_state[2]), + .I2(com_cmmt_tdst_rdy), + .O(com_cmm_u_tx_pkt_proc_N_55927_i) + ); + defparam com_cmm_u_tx_pkt_proc_next_state_0_i_0_a2_0_.INIT = 16'h0004; + LUT4 com_cmm_u_tx_pkt_proc_next_state_0_i_0_a2_0_ ( + .I0(com_cmm_gnt_pkt_tx), + .I1(com_state[0]), + .I2(com_state[1]), + .I3(com_cmmt_tdst_rdy), + .O(com_cmm_u_tx_pkt_proc_N_60436) + ); + defparam com_cmm_u_tx_pkt_proc_next_state_0_i_0_a2_0_1_0_.INIT = 8'h10; + LUT3 com_cmm_u_tx_pkt_proc_next_state_0_i_0_a2_0_1_0_ ( + .I0(com_cmm_gnt_pkt_tx), + .I1(com_state[2]), + .I2(com_cmmt_tdst_rdy), + .O(com_cmm_u_tx_pkt_proc_next_state_0_i_0_a2_0_1[0]) + ); + defparam com_cmm_u_tx_pkt_proc_next_state_0_i_0_0_2_.INIT = 8'h51; + LUT3 com_cmm_u_tx_pkt_proc_next_state_0_i_0_0_2_ ( + .I0(com_state[0]), + .I1(com_state[1]), + .I2(com_cmmt_tdst_rdy), + .O(com_cmm_u_tx_pkt_proc_next_state_0_i_0_0[2]) + ); + defparam com_cmm_u_tx_pkt_proc_cmmt_td_i_0_0_62_.INIT = 16'h4450; + LUT4 com_cmm_u_tx_pkt_proc_cmmt_td_i_0_0_62_ ( + .I0(com_N_55880_i), + .I1(com_tlp_data_0_), + .I2(com_TLP_data_reg_30_), + .I3(com_state[0]), + .O(com_N_43005_i) + ); + defparam com_cmm_u_tx_pkt_proc_N_60502_i.INIT = 8'hF1; + LUT3 com_cmm_u_tx_pkt_proc_N_60502_i ( + .I0(com_state[1]), + .I1(com_state[2]), + .I2(com_cmmt_tdst_rdy), + .O(com_cmm_u_tx_pkt_proc_N_60502_i_5392) + ); + defparam com_cmm_u_tx_pkt_proc_grant_reg_iv_0_0_a2.INIT = 8'h0B; + LUT3 com_cmm_u_tx_pkt_proc_grant_reg_iv_0_0_a2 ( + .I0(com_N_56344_i), + .I1(com_state[1]), + .I2(com_state[2]), + .O(com_N_58286) + ); + defparam com_cmm_u_tx_pkt_proc_N_86366_i.INIT = 8'hAC; + LUT3_L com_cmm_u_tx_pkt_proc_N_86366_i ( + .I0(com_cmmt_trem_n_0_sqmuxa), + .I1(com_state[1]), + .I2(com_cmmt_tdst_rdy), + .LO(com_cmm_u_tx_pkt_proc_N_86366_i_5393) + ); + defparam com_cmm_u_tx_pkt_proc_N_85919_i.INIT = 16'hFFEC; + LUT4_L com_cmm_u_tx_pkt_proc_N_85919_i ( + .I0(com_N_55880_i), + .I1(com_cmm_u_tx_pkt_proc_N_60436), + .I2(com_cmm_u_tx_pkt_proc_next_state_0_i_0_a2_0_1[0]), + .I3(com_cmm_u_tx_pkt_proc_state[4]), + .LO(com_cmm_u_tx_pkt_proc_N_85919_i_5394) + ); + defparam com_cmm_u_tx_pkt_proc_grant_reg_iv_0_0.INIT = 4'h4; + LUT2_L com_cmm_u_tx_pkt_proc_grant_reg_iv_0_0 ( + .I0(com_N_58286), + .I1(com_cmmt_tdst_rdy), + .LO(com_cmm_u_tx_pkt_proc_N_9934_i) + ); + defparam com_cmm_u_tx_pkt_proc_next_state_0_i_0_2_.INIT = 16'hA080; + LUT4_L com_cmm_u_tx_pkt_proc_next_state_0_i_0_2_ ( + .I0(com_cmm_u_tx_pkt_proc_N_55927_i), + .I1(com_N_56344_i), + .I2(com_cmm_u_tx_pkt_proc_next_state_0_i_0_0[2]), + .I3(com_state[2]), + .LO(com_cmm_u_tx_pkt_proc_N_42769_i) + ); + defparam com_cmm_u_tx_pkt_proc_N_43005_i_i.INIT = 4'h1; + LUT1_L com_cmm_u_tx_pkt_proc_N_43005_i_i ( + .I0(com_N_43005_i), + .LO(com_N_43005_i_i) + ); + defparam com_cmm_u_tx_pkt_proc_N_86529_i.INIT = 4'hB; + LUT2_L com_cmm_u_tx_pkt_proc_N_86529_i ( + .I0(com_N_55880_i), + .I1(com_N_63664), + .LO(com_N_86529_i) + ); + defparam com_cmm_u_tx_pkt_proc_TLP_data_reg_10_0_a2_0_a2_0_a2_63_.INIT = 4'h8; + LUT2_L com_cmm_u_tx_pkt_proc_TLP_data_reg_10_0_a2_0_a2_0_a2_63_ ( + .I0(com_cmm_tlp_data_127_), + .I1(com_state[0]), + .LO(com_cmm_u_tx_pkt_proc_TLP_data_reg_10_63_) + ); + defparam com_cmm_u_tx_pkt_proc_TLP_data_reg_10_0_a2_0_a2_0_a2_62_.INIT = 4'h8; + LUT2_L com_cmm_u_tx_pkt_proc_TLP_data_reg_10_0_a2_0_a2_0_a2_62_ ( + .I0(com_cmm_tlp_data_126_), + .I1(com_state[0]), + .LO(com_cmm_u_tx_pkt_proc_TLP_data_reg_10_62_) + ); + defparam com_cmm_u_tx_pkt_proc_TLP_data_reg_10_0_a2_0_a2_0_a2_61_.INIT = 4'h8; + LUT2_L com_cmm_u_tx_pkt_proc_TLP_data_reg_10_0_a2_0_a2_0_a2_61_ ( + .I0(com_cmm_tlp_data_125_), + .I1(com_state[0]), + .LO(com_cmm_u_tx_pkt_proc_TLP_data_reg_10_61_) + ); + defparam com_cmm_u_tx_pkt_proc_TLP_data_reg_10_0_a2_0_a2_0_a2_60_.INIT = 4'h8; + LUT2_L com_cmm_u_tx_pkt_proc_TLP_data_reg_10_0_a2_0_a2_0_a2_60_ ( + .I0(com_cmm_tlp_data_124_), + .I1(com_state[0]), + .LO(com_cmm_u_tx_pkt_proc_TLP_data_reg_10_60_) + ); + defparam com_cmm_u_tx_pkt_proc_TLP_data_reg_10_0_a2_0_a2_0_a2_59_.INIT = 4'h8; + LUT2_L com_cmm_u_tx_pkt_proc_TLP_data_reg_10_0_a2_0_a2_0_a2_59_ ( + .I0(com_cmm_tlp_data_123_), + .I1(com_state[0]), + .LO(com_cmm_u_tx_pkt_proc_TLP_data_reg_10_59_) + ); + defparam com_cmm_u_tx_pkt_proc_TLP_data_reg_10_0_a2_0_a2_0_a2_58_.INIT = 4'h8; + LUT2_L com_cmm_u_tx_pkt_proc_TLP_data_reg_10_0_a2_0_a2_0_a2_58_ ( + .I0(com_cmm_tlp_data_122_), + .I1(com_state[0]), + .LO(com_cmm_u_tx_pkt_proc_TLP_data_reg_10_58_) + ); + defparam com_cmm_u_tx_pkt_proc_TLP_data_reg_10_0_a2_0_a2_0_a2_57_.INIT = 4'h8; + LUT2_L com_cmm_u_tx_pkt_proc_TLP_data_reg_10_0_a2_0_a2_0_a2_57_ ( + .I0(com_cmm_tlp_data_121_), + .I1(com_state[0]), + .LO(com_cmm_u_tx_pkt_proc_TLP_data_reg_10_57_) + ); + defparam com_cmm_u_tx_pkt_proc_TLP_data_reg_10_0_a2_0_a2_0_a2_56_.INIT = 4'h8; + LUT2_L com_cmm_u_tx_pkt_proc_TLP_data_reg_10_0_a2_0_a2_0_a2_56_ ( + .I0(com_cmm_tlp_data_120_), + .I1(com_state[0]), + .LO(com_cmm_u_tx_pkt_proc_TLP_data_reg_10_56_) + ); + defparam com_cmm_u_tx_pkt_proc_TLP_data_reg_10_0_a2_0_a2_0_a2_55_.INIT = 4'h8; + LUT2_L com_cmm_u_tx_pkt_proc_TLP_data_reg_10_0_a2_0_a2_0_a2_55_ ( + .I0(com_cmm_tlp_data_119_), + .I1(com_state[0]), + .LO(com_cmm_u_tx_pkt_proc_TLP_data_reg_10_55_) + ); + defparam com_cmm_u_tx_pkt_proc_TLP_data_reg_10_0_a2_0_a2_0_a2_54_.INIT = 4'h8; + LUT2_L com_cmm_u_tx_pkt_proc_TLP_data_reg_10_0_a2_0_a2_0_a2_54_ ( + .I0(com_cmm_tlp_data_118_), + .I1(com_state[0]), + .LO(com_cmm_u_tx_pkt_proc_TLP_data_reg_10_54_) + ); + defparam com_cmm_u_tx_pkt_proc_TLP_data_reg_10_0_a2_0_a2_0_a2_53_.INIT = 4'h8; + LUT2_L com_cmm_u_tx_pkt_proc_TLP_data_reg_10_0_a2_0_a2_0_a2_53_ ( + .I0(com_cmm_tlp_data_117_), + .I1(com_state[0]), + .LO(com_cmm_u_tx_pkt_proc_TLP_data_reg_10_53_) + ); + defparam com_cmm_u_tx_pkt_proc_TLP_data_reg_10_0_a2_0_a2_0_a2_52_.INIT = 4'h8; + LUT2_L com_cmm_u_tx_pkt_proc_TLP_data_reg_10_0_a2_0_a2_0_a2_52_ ( + .I0(com_cmm_tlp_data_116_), + .I1(com_state[0]), + .LO(com_cmm_u_tx_pkt_proc_TLP_data_reg_10_52_) + ); + defparam com_cmm_u_tx_pkt_proc_TLP_data_reg_10_0_a2_0_a2_0_a2_51_.INIT = 4'h8; + LUT2_L com_cmm_u_tx_pkt_proc_TLP_data_reg_10_0_a2_0_a2_0_a2_51_ ( + .I0(com_cmm_tlp_data_115_), + .I1(com_state[0]), + .LO(com_cmm_u_tx_pkt_proc_TLP_data_reg_10_51_) + ); + defparam com_cmm_u_tx_pkt_proc_TLP_data_reg_10_0_a2_0_a2_0_a2_50_.INIT = 4'h8; + LUT2_L com_cmm_u_tx_pkt_proc_TLP_data_reg_10_0_a2_0_a2_0_a2_50_ ( + .I0(com_cmm_tlp_data_114_), + .I1(com_state[0]), + .LO(com_cmm_u_tx_pkt_proc_TLP_data_reg_10_50_) + ); + defparam com_cmm_u_tx_pkt_proc_TLP_data_reg_10_0_a2_0_a2_0_a2_49_.INIT = 4'h8; + LUT2_L com_cmm_u_tx_pkt_proc_TLP_data_reg_10_0_a2_0_a2_0_a2_49_ ( + .I0(com_cmm_tlp_data_113_), + .I1(com_state[0]), + .LO(com_cmm_u_tx_pkt_proc_TLP_data_reg_10_49_) + ); + defparam com_cmm_u_tx_pkt_proc_TLP_data_reg_10_0_a2_0_a2_0_a2_48_.INIT = 4'h8; + LUT2_L com_cmm_u_tx_pkt_proc_TLP_data_reg_10_0_a2_0_a2_0_a2_48_ ( + .I0(com_cmm_tlp_data_112_), + .I1(com_state[0]), + .LO(com_cmm_u_tx_pkt_proc_TLP_data_reg_10_48_) + ); + defparam com_cmm_u_tx_pkt_proc_TLP_data_reg_10_0_a2_0_a2_0_a2_47_.INIT = 4'h8; + LUT2_L com_cmm_u_tx_pkt_proc_TLP_data_reg_10_0_a2_0_a2_0_a2_47_ ( + .I0(com_cmm_tlp_data_111_), + .I1(com_state[0]), + .LO(com_cmm_u_tx_pkt_proc_TLP_data_reg_10_47_) + ); + defparam com_cmm_u_tx_pkt_proc_TLP_data_reg_10_0_a2_0_a2_0_a2_46_.INIT = 4'h8; + LUT2_L com_cmm_u_tx_pkt_proc_TLP_data_reg_10_0_a2_0_a2_0_a2_46_ ( + .I0(com_cmm_tlp_data_110_), + .I1(com_state[0]), + .LO(com_cmm_u_tx_pkt_proc_TLP_data_reg_10_46_) + ); + defparam com_cmm_u_tx_pkt_proc_TLP_data_reg_10_0_a2_0_a2_0_a2_45_.INIT = 4'h8; + LUT2_L com_cmm_u_tx_pkt_proc_TLP_data_reg_10_0_a2_0_a2_0_a2_45_ ( + .I0(com_cmm_tlp_data_109_), + .I1(com_state[0]), + .LO(com_cmm_u_tx_pkt_proc_TLP_data_reg_10_45_) + ); + defparam com_cmm_u_tx_pkt_proc_TLP_data_reg_10_0_a2_0_a2_0_a2_44_.INIT = 4'h8; + LUT2_L com_cmm_u_tx_pkt_proc_TLP_data_reg_10_0_a2_0_a2_0_a2_44_ ( + .I0(com_cmm_tlp_data_108_), + .I1(com_state[0]), + .LO(com_cmm_u_tx_pkt_proc_TLP_data_reg_10_44_) + ); + defparam com_cmm_u_tx_pkt_proc_TLP_data_reg_10_0_a2_0_a2_0_a2_43_.INIT = 4'h8; + LUT2_L com_cmm_u_tx_pkt_proc_TLP_data_reg_10_0_a2_0_a2_0_a2_43_ ( + .I0(com_cmm_tlp_data_107_), + .I1(com_state[0]), + .LO(com_cmm_u_tx_pkt_proc_TLP_data_reg_10_43_) + ); + defparam com_cmm_u_tx_pkt_proc_TLP_data_reg_10_0_a2_0_a2_0_a2_42_.INIT = 4'h8; + LUT2_L com_cmm_u_tx_pkt_proc_TLP_data_reg_10_0_a2_0_a2_0_a2_42_ ( + .I0(com_cmm_tlp_data_106_), + .I1(com_state[0]), + .LO(com_cmm_u_tx_pkt_proc_TLP_data_reg_10_42_) + ); + defparam com_cmm_u_tx_pkt_proc_TLP_data_reg_10_0_a2_0_a2_0_a2_41_.INIT = 4'h8; + LUT2_L com_cmm_u_tx_pkt_proc_TLP_data_reg_10_0_a2_0_a2_0_a2_41_ ( + .I0(com_cmm_tlp_data_105_), + .I1(com_state[0]), + .LO(com_cmm_u_tx_pkt_proc_TLP_data_reg_10_41_) + ); + defparam com_cmm_u_tx_pkt_proc_TLP_data_reg_10_0_a2_0_a2_0_a2_40_.INIT = 4'h8; + LUT2_L com_cmm_u_tx_pkt_proc_TLP_data_reg_10_0_a2_0_a2_0_a2_40_ ( + .I0(com_cmm_tlp_data_104_), + .I1(com_state[0]), + .LO(com_cmm_u_tx_pkt_proc_TLP_data_reg_10_40_) + ); + defparam com_cmm_u_tx_pkt_proc_TLP_data_reg_10_0_a2_0_a2_0_a2_39_.INIT = 4'h8; + LUT2_L com_cmm_u_tx_pkt_proc_TLP_data_reg_10_0_a2_0_a2_0_a2_39_ ( + .I0(com_cmm_tlp_data_103_), + .I1(com_state[0]), + .LO(com_cmm_u_tx_pkt_proc_TLP_data_reg_10_39_) + ); + defparam com_cmm_u_tx_pkt_proc_TLP_data_reg_10_0_a2_0_a2_0_a2_38_.INIT = 4'h8; + LUT2_L com_cmm_u_tx_pkt_proc_TLP_data_reg_10_0_a2_0_a2_0_a2_38_ ( + .I0(com_cmm_tlp_data_102_), + .I1(com_state[0]), + .LO(com_cmm_u_tx_pkt_proc_TLP_data_reg_10_38_) + ); + defparam com_cmm_u_tx_pkt_proc_TLP_data_reg_10_0_a2_0_a2_0_a2_37_.INIT = 4'h8; + LUT2_L com_cmm_u_tx_pkt_proc_TLP_data_reg_10_0_a2_0_a2_0_a2_37_ ( + .I0(com_cmm_tlp_data_101_), + .I1(com_state[0]), + .LO(com_cmm_u_tx_pkt_proc_TLP_data_reg_10_37_) + ); + defparam com_cmm_u_tx_pkt_proc_TLP_data_reg_10_0_a2_0_a2_0_a2_36_.INIT = 4'h8; + LUT2_L com_cmm_u_tx_pkt_proc_TLP_data_reg_10_0_a2_0_a2_0_a2_36_ ( + .I0(com_cmm_tlp_data_100_), + .I1(com_state[0]), + .LO(com_cmm_u_tx_pkt_proc_TLP_data_reg_10_36_) + ); + defparam com_cmm_u_tx_pkt_proc_TLP_data_reg_10_0_a2_0_a2_0_a2_35_.INIT = 4'h8; + LUT2_L com_cmm_u_tx_pkt_proc_TLP_data_reg_10_0_a2_0_a2_0_a2_35_ ( + .I0(com_cmm_tlp_data_99_), + .I1(com_state[0]), + .LO(com_cmm_u_tx_pkt_proc_TLP_data_reg_10_35_) + ); + defparam com_cmm_u_tx_pkt_proc_TLP_data_reg_10_0_a2_0_a2_0_a2_34_.INIT = 4'h8; + LUT2_L com_cmm_u_tx_pkt_proc_TLP_data_reg_10_0_a2_0_a2_0_a2_34_ ( + .I0(com_cmm_tlp_data_98_), + .I1(com_state[0]), + .LO(com_cmm_u_tx_pkt_proc_TLP_data_reg_10_34_) + ); + defparam com_cmm_u_tx_pkt_proc_TLP_data_reg_10_0_a2_0_a2_0_a2_33_.INIT = 4'h8; + LUT2_L com_cmm_u_tx_pkt_proc_TLP_data_reg_10_0_a2_0_a2_0_a2_33_ ( + .I0(com_cmm_tlp_data_97_), + .I1(com_state[0]), + .LO(com_cmm_u_tx_pkt_proc_TLP_data_reg_10_33_) + ); + defparam com_cmm_u_tx_pkt_proc_TLP_data_reg_10_0_a2_0_a2_0_a2_32_.INIT = 4'h8; + LUT2_L com_cmm_u_tx_pkt_proc_TLP_data_reg_10_0_a2_0_a2_0_a2_32_ ( + .I0(com_cmm_tlp_data_96_), + .I1(com_state[0]), + .LO(com_cmm_u_tx_pkt_proc_TLP_data_reg_10_32_) + ); + defparam com_cmm_u_tx_pkt_proc_TLP_data_reg_10_i_0_31_.INIT = 16'h88A0; + LUT4_L com_cmm_u_tx_pkt_proc_TLP_data_reg_10_i_0_31_ ( + .I0(com_cmm_u_tx_pkt_proc_N_55927_i), + .I1(com_cmm_msi_data[7]), + .I2(com_cmm_tlp_data_95_), + .I3(com_state[1]), + .LO(com_cmm_u_tx_pkt_proc_N_43037_i) + ); + defparam com_cmm_u_tx_pkt_proc_TLP_data_reg_10_i_0_30_.INIT = 16'h88A0; + LUT4_L com_cmm_u_tx_pkt_proc_TLP_data_reg_10_i_0_30_ ( + .I0(com_cmm_u_tx_pkt_proc_N_55927_i), + .I1(com_cmm_msi_data[6]), + .I2(com_cmm_tlp_data_94_), + .I3(com_state[1]), + .LO(com_cmm_u_tx_pkt_proc_N_43035_i) + ); + defparam com_cmm_u_tx_pkt_proc_TLP_data_reg_10_i_0_29_.INIT = 16'h88A0; + LUT4_L com_cmm_u_tx_pkt_proc_TLP_data_reg_10_i_0_29_ ( + .I0(com_cmm_u_tx_pkt_proc_N_55927_i), + .I1(com_cmm_msi_data[5]), + .I2(com_cmm_tlp_data_93_), + .I3(com_state[1]), + .LO(com_cmm_u_tx_pkt_proc_N_43033_i) + ); + defparam com_cmm_u_tx_pkt_proc_TLP_data_reg_10_i_0_28_.INIT = 16'h88A0; + LUT4_L com_cmm_u_tx_pkt_proc_TLP_data_reg_10_i_0_28_ ( + .I0(com_cmm_u_tx_pkt_proc_N_55927_i), + .I1(com_cmm_msi_data[4]), + .I2(com_cmm_tlp_data_92_), + .I3(com_state[1]), + .LO(com_cmm_u_tx_pkt_proc_N_43031_i) + ); + defparam com_cmm_u_tx_pkt_proc_TLP_data_reg_10_i_0_27_.INIT = 16'h88A0; + LUT4_L com_cmm_u_tx_pkt_proc_TLP_data_reg_10_i_0_27_ ( + .I0(com_cmm_u_tx_pkt_proc_N_55927_i), + .I1(com_cmm_msi_data[3]), + .I2(com_cmm_tlp_data_91_), + .I3(com_state[1]), + .LO(com_cmm_u_tx_pkt_proc_N_43029_i) + ); + defparam com_cmm_u_tx_pkt_proc_TLP_data_reg_10_i_0_26_.INIT = 16'h88A0; + LUT4_L com_cmm_u_tx_pkt_proc_TLP_data_reg_10_i_0_26_ ( + .I0(com_cmm_u_tx_pkt_proc_N_55927_i), + .I1(com_cmm_msi_data[2]), + .I2(com_cmm_tlp_data_90_), + .I3(com_state[1]), + .LO(com_cmm_u_tx_pkt_proc_N_43027_i) + ); + defparam com_cmm_u_tx_pkt_proc_TLP_data_reg_10_i_0_25_.INIT = 16'h88A0; + LUT4_L com_cmm_u_tx_pkt_proc_TLP_data_reg_10_i_0_25_ ( + .I0(com_cmm_u_tx_pkt_proc_N_55927_i), + .I1(com_cmm_msi_data[1]), + .I2(com_cmm_tlp_data_89_), + .I3(com_state[1]), + .LO(com_cmm_u_tx_pkt_proc_N_43025_i) + ); + defparam com_cmm_u_tx_pkt_proc_TLP_data_reg_10_i_0_24_.INIT = 16'h88A0; + LUT4_L com_cmm_u_tx_pkt_proc_TLP_data_reg_10_i_0_24_ ( + .I0(com_cmm_u_tx_pkt_proc_N_55927_i), + .I1(com_cmm_msi_data[0]), + .I2(com_cmm_tlp_data_88_), + .I3(com_state[1]), + .LO(com_cmm_u_tx_pkt_proc_N_43023_i) + ); + defparam com_cmm_u_tx_pkt_proc_TLP_data_reg_10_i_0_23_.INIT = 16'h88A0; + LUT4_L com_cmm_u_tx_pkt_proc_TLP_data_reg_10_i_0_23_ ( + .I0(com_cmm_u_tx_pkt_proc_N_55927_i), + .I1(com_cmm_msi_data[15]), + .I2(com_cmm_tlp_data_87_), + .I3(com_state[1]), + .LO(com_cmm_u_tx_pkt_proc_N_43021_i) + ); + defparam com_cmm_u_tx_pkt_proc_TLP_data_reg_10_i_0_22_.INIT = 16'h88A0; + LUT4_L com_cmm_u_tx_pkt_proc_TLP_data_reg_10_i_0_22_ ( + .I0(com_cmm_u_tx_pkt_proc_N_55927_i), + .I1(com_cmm_msi_data[14]), + .I2(com_cmm_tlp_data_86_), + .I3(com_state[1]), + .LO(com_cmm_u_tx_pkt_proc_N_43019_i) + ); + defparam com_cmm_u_tx_pkt_proc_TLP_data_reg_10_i_0_21_.INIT = 16'h88A0; + LUT4_L com_cmm_u_tx_pkt_proc_TLP_data_reg_10_i_0_21_ ( + .I0(com_cmm_u_tx_pkt_proc_N_55927_i), + .I1(com_cmm_msi_data[13]), + .I2(com_cmm_tlp_data_85_), + .I3(com_state[1]), + .LO(com_cmm_u_tx_pkt_proc_N_43017_i) + ); + defparam com_cmm_u_tx_pkt_proc_TLP_data_reg_10_i_0_20_.INIT = 16'h88A0; + LUT4_L com_cmm_u_tx_pkt_proc_TLP_data_reg_10_i_0_20_ ( + .I0(com_cmm_u_tx_pkt_proc_N_55927_i), + .I1(com_cmm_msi_data[12]), + .I2(com_cmm_tlp_data_84_), + .I3(com_state[1]), + .LO(com_cmm_u_tx_pkt_proc_N_43015_i) + ); + defparam com_cmm_u_tx_pkt_proc_TLP_data_reg_10_i_0_19_.INIT = 16'h88A0; + LUT4_L com_cmm_u_tx_pkt_proc_TLP_data_reg_10_i_0_19_ ( + .I0(com_cmm_u_tx_pkt_proc_N_55927_i), + .I1(com_cmm_msi_data[11]), + .I2(com_cmm_tlp_data_83_), + .I3(com_state[1]), + .LO(com_cmm_u_tx_pkt_proc_N_43013_i) + ); + defparam com_cmm_u_tx_pkt_proc_TLP_data_reg_10_i_0_18_.INIT = 16'h88A0; + LUT4_L com_cmm_u_tx_pkt_proc_TLP_data_reg_10_i_0_18_ ( + .I0(com_cmm_u_tx_pkt_proc_N_55927_i), + .I1(com_cmm_msi_data[10]), + .I2(com_cmm_tlp_data_82_), + .I3(com_state[1]), + .LO(com_cmm_u_tx_pkt_proc_N_43011_i) + ); + defparam com_cmm_u_tx_pkt_proc_TLP_data_reg_10_i_0_17_.INIT = 16'h88A0; + LUT4_L com_cmm_u_tx_pkt_proc_TLP_data_reg_10_i_0_17_ ( + .I0(com_cmm_u_tx_pkt_proc_N_55927_i), + .I1(com_cmm_msi_data[9]), + .I2(com_cmm_tlp_data_81_), + .I3(com_state[1]), + .LO(com_cmm_u_tx_pkt_proc_N_43009_i) + ); + defparam com_cmm_u_tx_pkt_proc_TLP_data_reg_10_i_0_16_.INIT = 16'h88A0; + LUT4_L com_cmm_u_tx_pkt_proc_TLP_data_reg_10_i_0_16_ ( + .I0(com_cmm_u_tx_pkt_proc_N_55927_i), + .I1(com_cmm_msi_data[8]), + .I2(com_cmm_tlp_data_80_), + .I3(com_state[1]), + .LO(com_cmm_u_tx_pkt_proc_N_43007_i) + ); + defparam com_cmm_u_tx_pkt_proc_TLP_data_reg_10_0_a2_0_a2_0_a2_15_.INIT = 4'h8; + LUT2_L com_cmm_u_tx_pkt_proc_TLP_data_reg_10_0_a2_0_a2_0_a2_15_ ( + .I0(com_cmm_tlp_data_79_), + .I1(com_state[0]), + .LO(com_cmm_u_tx_pkt_proc_TLP_data_reg_10_15_) + ); + defparam com_cmm_u_tx_pkt_proc_TLP_data_reg_10_0_a2_0_a2_0_a2_14_.INIT = 4'h8; + LUT2_L com_cmm_u_tx_pkt_proc_TLP_data_reg_10_0_a2_0_a2_0_a2_14_ ( + .I0(com_cmm_tlp_data_78_), + .I1(com_state[0]), + .LO(com_cmm_u_tx_pkt_proc_TLP_data_reg_10_14_) + ); + defparam com_cmm_u_tx_pkt_proc_TLP_data_reg_10_0_a2_0_a2_0_a2_13_.INIT = 4'h8; + LUT2_L com_cmm_u_tx_pkt_proc_TLP_data_reg_10_0_a2_0_a2_0_a2_13_ ( + .I0(com_cmm_tlp_data_77_), + .I1(com_state[0]), + .LO(com_cmm_u_tx_pkt_proc_TLP_data_reg_10_13_) + ); + defparam com_cmm_u_tx_pkt_proc_TLP_data_reg_10_0_a2_0_a2_0_a2_12_.INIT = 4'h8; + LUT2_L com_cmm_u_tx_pkt_proc_TLP_data_reg_10_0_a2_0_a2_0_a2_12_ ( + .I0(com_cmm_tlp_data_76_), + .I1(com_state[0]), + .LO(com_cmm_u_tx_pkt_proc_TLP_data_reg_10_12_) + ); + defparam com_cmm_u_tx_pkt_proc_TLP_data_reg_10_0_a2_0_a2_0_a2_11_.INIT = 4'h8; + LUT2_L com_cmm_u_tx_pkt_proc_TLP_data_reg_10_0_a2_0_a2_0_a2_11_ ( + .I0(com_cmm_tlp_data_75_), + .I1(com_state[0]), + .LO(com_cmm_u_tx_pkt_proc_TLP_data_reg_10_11_) + ); + defparam com_cmm_u_tx_pkt_proc_TLP_data_reg_10_0_a2_0_a2_0_a2_10_.INIT = 4'h8; + LUT2_L com_cmm_u_tx_pkt_proc_TLP_data_reg_10_0_a2_0_a2_0_a2_10_ ( + .I0(com_cmm_tlp_data_74_), + .I1(com_state[0]), + .LO(com_cmm_u_tx_pkt_proc_TLP_data_reg_10_10_) + ); + defparam com_cmm_u_tx_pkt_proc_TLP_data_reg_10_0_a2_0_a2_0_a2_9_.INIT = 4'h8; + LUT2_L com_cmm_u_tx_pkt_proc_TLP_data_reg_10_0_a2_0_a2_0_a2_9_ ( + .I0(com_cmm_tlp_data_73_), + .I1(com_state[0]), + .LO(com_cmm_u_tx_pkt_proc_TLP_data_reg_10_9_) + ); + defparam com_cmm_u_tx_pkt_proc_TLP_data_reg_10_0_a2_0_a2_8_.INIT = 4'h8; + LUT2_L com_cmm_u_tx_pkt_proc_TLP_data_reg_10_0_a2_0_a2_8_ ( + .I0(com_cmm_tlp_data_72_), + .I1(com_state[0]), + .LO(com_cmm_u_tx_pkt_proc_TLP_data_reg_10_8_) + ); + defparam com_cmm_u_tx_pkt_proc_TLP_data_reg_10_0_a2_0_a2_7_.INIT = 4'h8; + LUT2_L com_cmm_u_tx_pkt_proc_TLP_data_reg_10_0_a2_0_a2_7_ ( + .I0(com_cmm_tlp_data_71_), + .I1(com_state[0]), + .LO(com_cmm_u_tx_pkt_proc_TLP_data_reg_10_7_) + ); + defparam com_cmm_u_tx_pkt_proc_TLP_data_reg_10_0_a2_0_a2_6_.INIT = 4'h8; + LUT2_L com_cmm_u_tx_pkt_proc_TLP_data_reg_10_0_a2_0_a2_6_ ( + .I0(com_cmm_tlp_data_70_), + .I1(com_state[0]), + .LO(com_cmm_u_tx_pkt_proc_TLP_data_reg_10_6_) + ); + defparam com_cmm_u_tx_pkt_proc_TLP_data_reg_10_0_a2_0_a2_5_.INIT = 4'h8; + LUT2_L com_cmm_u_tx_pkt_proc_TLP_data_reg_10_0_a2_0_a2_5_ ( + .I0(com_cmm_tlp_data_69_), + .I1(com_state[0]), + .LO(com_cmm_u_tx_pkt_proc_TLP_data_reg_10_5_) + ); + defparam com_cmm_u_tx_pkt_proc_TLP_data_reg_10_0_a2_0_a2_4_.INIT = 4'h8; + LUT2_L com_cmm_u_tx_pkt_proc_TLP_data_reg_10_0_a2_0_a2_4_ ( + .I0(com_cmm_tlp_data_68_), + .I1(com_state[0]), + .LO(com_cmm_u_tx_pkt_proc_TLP_data_reg_10_4_) + ); + defparam com_cmm_u_tx_pkt_proc_TLP_data_reg_10_0_a2_0_a2_3_.INIT = 4'h8; + LUT2_L com_cmm_u_tx_pkt_proc_TLP_data_reg_10_0_a2_0_a2_3_ ( + .I0(com_cmm_tlp_data_67_), + .I1(com_state[0]), + .LO(com_cmm_u_tx_pkt_proc_TLP_data_reg_10_3_) + ); + defparam com_cmm_u_tx_pkt_proc_TLP_data_reg_10_0_a2_0_a2_2_.INIT = 4'h8; + LUT2_L com_cmm_u_tx_pkt_proc_TLP_data_reg_10_0_a2_0_a2_2_ ( + .I0(com_cmm_tlp_data_66_), + .I1(com_state[0]), + .LO(com_cmm_u_tx_pkt_proc_TLP_data_reg_10_2_) + ); + defparam com_cmm_u_tx_pkt_proc_TLP_data_reg_10_0_a2_0_a2_1_.INIT = 4'h8; + LUT2_L com_cmm_u_tx_pkt_proc_TLP_data_reg_10_0_a2_0_a2_1_ ( + .I0(com_cmm_tlp_data_65_), + .I1(com_state[0]), + .LO(com_cmm_u_tx_pkt_proc_TLP_data_reg_10_1_) + ); + defparam com_cmm_u_tx_pkt_proc_TLP_data_reg_10_0_a2_0_a2_0_.INIT = 4'h8; + LUT2_L com_cmm_u_tx_pkt_proc_TLP_data_reg_10_0_a2_0_a2_0_ ( + .I0(com_cmm_tlp_data_64_), + .I1(com_state[0]), + .LO(com_cmm_u_tx_pkt_proc_TLP_data_reg_10_0_) + ); + FDC com_cmm_u_tx_pkt_proc_state_1_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_tx_pkt_proc_N_86366_i_5393), + .Q(com_state[1]), + .CLR(com_cmm_rst_351) + ); + FDP com_cmm_u_tx_pkt_proc_state_0_ ( + .PRE(com_cmm_rst_351), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_tx_pkt_proc_N_85919_i_5394), + .Q(com_state[0]) + ); + FDC com_cmm_u_tx_pkt_proc_state_4_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_gnt_pkt_tx), + .Q(com_cmm_u_tx_pkt_proc_state[4]), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_tx_pkt_proc_state_3_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_tx_pkt_proc_N_9934_i), + .Q(com_cmm_gnt_pkt_tx), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_tx_pkt_proc_state_2_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_tx_pkt_proc_N_42769_i), + .Q(com_state[2]), + .CLR(com_cmm_rst_351) + ); + defparam com_cmm_u_cfg_ctrl_wrdata_0_a2_0_a2_0_a2_0_a2_0_a2_5_.INIT = 4'h8; + LUT2 com_cmm_u_cfg_ctrl_wrdata_0_a2_0_a2_0_a2_0_a2_0_a2_5_ ( + .I0(com_cmm_cfg_wr_data_29_), + .I1(com_cmm_state_0[1]), + .O(com_cmm_tlm2cfg_wrdata_5_) + ); + defparam com_cmm_u_cfg_ctrl_wrdata_0_a2_0_a2_0_a2_0_a2_0_a2_6_.INIT = 4'h8; + LUT2 com_cmm_u_cfg_ctrl_wrdata_0_a2_0_a2_0_a2_0_a2_0_a2_6_ ( + .I0(com_cmm_cfg_wr_data_30_), + .I1(com_cmm_state_0[1]), + .O(com_cmm_tlm2cfg_wrdata_6_) + ); + defparam com_cmm_u_cfg_ctrl_wrdata_0_a2_0_a2_0_a2_0_a2_0_a2_7_.INIT = 4'h8; + LUT2 com_cmm_u_cfg_ctrl_wrdata_0_a2_0_a2_0_a2_0_a2_0_a2_7_ ( + .I0(com_cmm_cfg_wr_data_31_), + .I1(com_cmm_state_0[1]), + .O(com_cmm_tlm2cfg_wrdata_7_) + ); + defparam com_cmm_u_cfg_ctrl_wrdata_0_a2_0_a2_0_a2_0_a2_0_a2_2_.INIT = 4'h8; + LUT2 com_cmm_u_cfg_ctrl_wrdata_0_a2_0_a2_0_a2_0_a2_0_a2_2_ ( + .I0(com_cmm_cfg_wr_data[26]), + .I1(com_cmm_state_0[1]), + .O(com_cmm_tlm2cfg_wrdata_2_) + ); + defparam com_cmm_u_cfg_ctrl_wrdata_0_a2_0_a2_0_a2_0_a2_0_a2_3_.INIT = 4'h8; + LUT2 com_cmm_u_cfg_ctrl_wrdata_0_a2_0_a2_0_a2_0_a2_0_a2_3_ ( + .I0(com_cmm_cfg_wr_data[27]), + .I1(com_cmm_state_0[1]), + .O(com_cmm_tlm2cfg_wrdata_3_) + ); + defparam com_cmm_u_cfg_ctrl_wrdata_0_a2_0_a2_0_a2_0_a2_0_a2_4_.INIT = 4'h8; + LUT2 com_cmm_u_cfg_ctrl_wrdata_0_a2_0_a2_0_a2_0_a2_0_a2_4_ ( + .I0(com_cmm_cfg_wr_data_28_), + .I1(com_cmm_state_0[1]), + .O(com_cmm_tlm2cfg_wrdata_4_) + ); + defparam com_cmm_u_cfg_ctrl_N_33408_i_0_a2_0_a2.INIT = 4'h8; + LUT2 com_cmm_u_cfg_ctrl_N_33408_i_0_a2_0_a2 ( + .I0(com_cmm_cfg_wr_data[24]), + .I1(com_cmm_state_0[1]), + .O(com_cmm_N_33408_i_0) + ); + defparam com_cmm_u_cfg_ctrl_N_33410_i_0_a2_0_a2.INIT = 4'h8; + LUT2 com_cmm_u_cfg_ctrl_N_33410_i_0_a2_0_a2 ( + .I0(com_cmm_cfg_wr_data[25]), + .I1(com_cmm_state_0[1]), + .O(com_cmm_N_33410_i_0) + ); + defparam com_cmm_u_cfg_ctrl_next_state_0_i_0_0_o3_2_.INIT = 4'h1; + LUT2_L com_cmm_u_cfg_ctrl_next_state_0_i_0_0_o3_2_ ( + .I0(com_cmm_cfg_rd), + .I1(com_cmm_cfg_wr), + .LO(com_cmm_u_cfg_ctrl_next_state_0_i_0_0_o3[2]) + ); + defparam com_cmm_u_cfg_ctrl_next_state_0_i_0_0_a2_0_1_.INIT = 16'h0400; + LUT4 com_cmm_u_cfg_ctrl_next_state_0_i_0_0_a2_0_1_ ( + .I0(com_cmm_bdf_err_rd_pack), + .I1(com_cmm_req_valid), + .I2(com_cmm_type1_type0_bar), + .I3(com_cmm_u_cfg_ctrl_state[0]), + .O(com_cmm_u_cfg_ctrl_N_58695) + ); + defparam com_cmm_u_cfg_ctrl_next_state_0_i_0_0_a2_2_2_.INIT = 16'hC800; + LUT4 com_cmm_u_cfg_ctrl_next_state_0_i_0_0_a2_2_2_ ( + .I0(com_cmm_bdf_err_rd_pack), + .I1(com_cmm_req_valid), + .I2(com_cmm_type1_type0_bar), + .I3(com_cmm_u_cfg_ctrl_state[0]), + .O(com_cmm_u_cfg_ctrl_N_58693) + ); + defparam com_cmm_u_cfg_ctrl_next_state_0_i_0_a2_2_2_.INIT = 16'h2F3F; + LUT4 com_cmm_u_cfg_ctrl_next_state_0_i_0_a2_2_2_ ( + .I0(com_cmm_u_cfg_ctrl_next_state_0_i_0_0_o3[2]), + .I1(com_cmm_posnd_wr_pack), + .I2(com_cmm_state_0[1]), + .I3(com_cmm_state[6]), + .O(com_cmm_u_cfg_ctrl_next_state_0_sqmuxa_i) + ); + defparam com_cmm_u_cfg_ctrl_N_85814_i.INIT = 16'hBAFF; + LUT4_L com_cmm_u_cfg_ctrl_N_85814_i ( + .I0(com_cmm_u_cfg_ctrl_N_58693), + .I1(com_cmm_gnt_cfgctrl), + .I2(com_cmm_req_cfgctrl), + .I3(com_cmm_u_cfg_ctrl_next_state_0_sqmuxa_i), + .LO(com_cmm_u_cfg_ctrl_N_85814_i_5395) + ); + defparam com_cmm_u_cfg_ctrl_N_86813_i.INIT = 8'hEA; + LUT3_L com_cmm_u_cfg_ctrl_N_86813_i ( + .I0(com_cmm_u_cfg_ctrl_N_58695), + .I1(com_cmm_u_cfg_ctrl_next_state_0_sqmuxa_i), + .I2(com_cmm_state_0[1]), + .LO(com_cmm_u_cfg_ctrl_N_86813_i_5396) + ); + defparam com_cmm_u_cfg_ctrl_N_86780_i.INIT = 8'hBA; + LUT3_L com_cmm_u_cfg_ctrl_N_86780_i ( + .I0(com_cmm_N_56090_i), + .I1(com_cmm_req_valid), + .I2(com_cmm_u_cfg_ctrl_state[0]), + .LO(com_cmm_u_cfg_ctrl_N_86780_i_5397) + ); + defparam com_cmm_u_cfg_ctrl_wrdata_0_a2_0_a2_0_a2_0_a2_16_.INIT = 4'h8; + LUT2_L com_cmm_u_cfg_ctrl_wrdata_0_a2_0_a2_0_a2_0_a2_16_ ( + .I0(com_cmm_cfg_wr_data_8_), + .I1(com_cmm_state_0[1]), + .LO(com_cmm_tlm2cfg_wrdata_16_) + ); + FDC com_cmm_u_cfg_ctrl_state_2_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cfg_ctrl_N_85814_i_5395), + .Q(com_cmm_req_cfgctrl), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cfg_ctrl_state_1_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cfg_ctrl_N_86813_i_5396), + .Q(com_cmm_state_0[1]), + .CLR(com_cmm_rst_351) + ); + FDP com_cmm_u_cfg_ctrl_state_0_ ( + .PRE(com_cmm_rst_351), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cfg_ctrl_N_86780_i_5397), + .Q(com_cmm_u_cfg_ctrl_state[0]) + ); + FDCE com_cmm_u_cfg_ctrl_cfg_rd_data_31_ ( + .CE(com_cmm_u_cfg_ctrl_next_state_0_sqmuxa_i_i_5398), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_cfg2tlm_rddata[31]), + .Q(com_cmm_cfg_rd_data[31]), + .CLR(com_cmm_rst_351) + ); + FDCE com_cmm_u_cfg_ctrl_cfg_rd_data_30_ ( + .CE(com_cmm_u_cfg_ctrl_next_state_0_sqmuxa_i_i_5398), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_cfg2tlm_rddata[30]), + .Q(com_cmm_cfg_rd_data[30]), + .CLR(com_cmm_rst_351) + ); + FDCE com_cmm_u_cfg_ctrl_cfg_rd_data_29_ ( + .CE(com_cmm_u_cfg_ctrl_next_state_0_sqmuxa_i_i_5398), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_cfg2tlm_rddata[29]), + .Q(com_cmm_cfg_rd_data[29]), + .CLR(com_cmm_rst_351) + ); + FDCE com_cmm_u_cfg_ctrl_cfg_rd_data_28_ ( + .CE(com_cmm_u_cfg_ctrl_next_state_0_sqmuxa_i_i_5398), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_cfg2tlm_rddata[28]), + .Q(com_cmm_cfg_rd_data[28]), + .CLR(com_cmm_rst_351) + ); + FDCE com_cmm_u_cfg_ctrl_cfg_rd_data_27_ ( + .CE(com_cmm_u_cfg_ctrl_next_state_0_sqmuxa_i_i_5398), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_cfg2tlm_rddata[27]), + .Q(com_cmm_cfg_rd_data[27]), + .CLR(com_cmm_rst_351) + ); + FDCE com_cmm_u_cfg_ctrl_cfg_rd_data_26_ ( + .CE(com_cmm_u_cfg_ctrl_next_state_0_sqmuxa_i_i_5398), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_cfg2tlm_rddata[26]), + .Q(com_cmm_cfg_rd_data[26]), + .CLR(com_cmm_rst_351) + ); + FDCE com_cmm_u_cfg_ctrl_cfg_rd_data_25_ ( + .CE(com_cmm_u_cfg_ctrl_next_state_0_sqmuxa_i_i_5398), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_cfg2tlm_rddata[25]), + .Q(com_cmm_cfg_rd_data[25]), + .CLR(com_cmm_rst_351) + ); + FDCE com_cmm_u_cfg_ctrl_cfg_rd_data_24_ ( + .CE(com_cmm_u_cfg_ctrl_next_state_0_sqmuxa_i_i_5398), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_cfg2tlm_rddata[24]), + .Q(com_cmm_cfg_rd_data[24]), + .CLR(com_cmm_rst_351) + ); + FDCE com_cmm_u_cfg_ctrl_cfg_rd_data_23_ ( + .CE(com_cmm_u_cfg_ctrl_next_state_0_sqmuxa_i_i_5398), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_cfg2tlm_rddata[23]), + .Q(com_cmm_cfg_rd_data[23]), + .CLR(com_cmm_rst_351) + ); + FDCE com_cmm_u_cfg_ctrl_cfg_rd_data_22_ ( + .CE(com_cmm_u_cfg_ctrl_next_state_0_sqmuxa_i_i_5398), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_cfg2tlm_rddata[22]), + .Q(com_cmm_cfg_rd_data[22]), + .CLR(com_cmm_rst_351) + ); + FDCE com_cmm_u_cfg_ctrl_cfg_rd_data_21_ ( + .CE(com_cmm_u_cfg_ctrl_next_state_0_sqmuxa_i_i_5398), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_cfg2tlm_rddata[21]), + .Q(com_cmm_cfg_rd_data[21]), + .CLR(com_cmm_rst_351) + ); + FDCE com_cmm_u_cfg_ctrl_cfg_rd_data_20_ ( + .CE(com_cmm_u_cfg_ctrl_next_state_0_sqmuxa_i_i_5398), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_cfg2tlm_rddata[20]), + .Q(com_cmm_cfg_rd_data[20]), + .CLR(com_cmm_rst_351) + ); + FDCE com_cmm_u_cfg_ctrl_cfg_rd_data_19_ ( + .CE(com_cmm_u_cfg_ctrl_next_state_0_sqmuxa_i_i_5398), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_cfg2tlm_rddata[19]), + .Q(com_cmm_cfg_rd_data[19]), + .CLR(com_cmm_rst_351) + ); + FDCE com_cmm_u_cfg_ctrl_cfg_rd_data_18_ ( + .CE(com_cmm_u_cfg_ctrl_next_state_0_sqmuxa_i_i_5398), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_cfg2tlm_rddata[18]), + .Q(com_cmm_cfg_rd_data[18]), + .CLR(com_cmm_rst_351) + ); + FDCE com_cmm_u_cfg_ctrl_cfg_rd_data_17_ ( + .CE(com_cmm_u_cfg_ctrl_next_state_0_sqmuxa_i_i_5398), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_cfg2tlm_rddata[17]), + .Q(com_cmm_cfg_rd_data[17]), + .CLR(com_cmm_rst_351) + ); + FDCE com_cmm_u_cfg_ctrl_cfg_rd_data_16_ ( + .CE(com_cmm_u_cfg_ctrl_next_state_0_sqmuxa_i_i_5398), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_cfg2tlm_rddata[16]), + .Q(com_cmm_cfg_rd_data[16]), + .CLR(com_cmm_rst_351) + ); + FDCE com_cmm_u_cfg_ctrl_cfg_rd_data_15_ ( + .CE(com_cmm_u_cfg_ctrl_next_state_0_sqmuxa_i_i_5398), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_cfg2tlm_rddata[15]), + .Q(com_cmm_cfg_rd_data[15]), + .CLR(com_cmm_rst_351) + ); + FDCE com_cmm_u_cfg_ctrl_cfg_rd_data_14_ ( + .CE(com_cmm_u_cfg_ctrl_next_state_0_sqmuxa_i_i_5398), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_cfg2tlm_rddata[14]), + .Q(com_cmm_cfg_rd_data[14]), + .CLR(com_cmm_rst_351) + ); + FDCE com_cmm_u_cfg_ctrl_cfg_rd_data_13_ ( + .CE(com_cmm_u_cfg_ctrl_next_state_0_sqmuxa_i_i_5398), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_cfg2tlm_rddata[13]), + .Q(com_cmm_cfg_rd_data[13]), + .CLR(com_cmm_rst_351) + ); + FDCE com_cmm_u_cfg_ctrl_cfg_rd_data_12_ ( + .CE(com_cmm_u_cfg_ctrl_next_state_0_sqmuxa_i_i_5398), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_cfg2tlm_rddata[12]), + .Q(com_cmm_cfg_rd_data[12]), + .CLR(com_cmm_rst_351) + ); + FDCE com_cmm_u_cfg_ctrl_cfg_rd_data_11_ ( + .CE(com_cmm_u_cfg_ctrl_next_state_0_sqmuxa_i_i_5398), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_cfg2tlm_rddata[11]), + .Q(com_cmm_cfg_rd_data[11]), + .CLR(com_cmm_rst_351) + ); + FDCE com_cmm_u_cfg_ctrl_cfg_rd_data_10_ ( + .CE(com_cmm_u_cfg_ctrl_next_state_0_sqmuxa_i_i_5398), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_cfg2tlm_rddata[10]), + .Q(com_cmm_cfg_rd_data[10]), + .CLR(com_cmm_rst_351) + ); + FDCE com_cmm_u_cfg_ctrl_cfg_rd_data_9_ ( + .CE(com_cmm_u_cfg_ctrl_next_state_0_sqmuxa_i_i_5398), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_cfg2tlm_rddata[9]), + .Q(com_cmm_cfg_rd_data[9]), + .CLR(com_cmm_rst_351) + ); + FDCE com_cmm_u_cfg_ctrl_cfg_rd_data_8_ ( + .CE(com_cmm_u_cfg_ctrl_next_state_0_sqmuxa_i_i_5398), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_cfg2tlm_rddata[8]), + .Q(com_cmm_cfg_rd_data[8]), + .CLR(com_cmm_rst_351) + ); + FDCE com_cmm_u_cfg_ctrl_cfg_rd_data_7_ ( + .CE(com_cmm_u_cfg_ctrl_next_state_0_sqmuxa_i_i_5398), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_cfg2tlm_rddata[7]), + .Q(com_cmm_cfg_rd_data[7]), + .CLR(com_cmm_rst_351) + ); + FDCE com_cmm_u_cfg_ctrl_cfg_rd_data_6_ ( + .CE(com_cmm_u_cfg_ctrl_next_state_0_sqmuxa_i_i_5398), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_cfg2tlm_rddata[6]), + .Q(com_cmm_cfg_rd_data[6]), + .CLR(com_cmm_rst_351) + ); + FDCE com_cmm_u_cfg_ctrl_cfg_rd_data_5_ ( + .CE(com_cmm_u_cfg_ctrl_next_state_0_sqmuxa_i_i_5398), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_cfg2tlm_rddata[5]), + .Q(com_cmm_cfg_rd_data[5]), + .CLR(com_cmm_rst_351) + ); + FDCE com_cmm_u_cfg_ctrl_cfg_rd_data_4_ ( + .CE(com_cmm_u_cfg_ctrl_next_state_0_sqmuxa_i_i_5398), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_cfg2tlm_rddata[4]), + .Q(com_cmm_cfg_rd_data[4]), + .CLR(com_cmm_rst_351) + ); + FDCE com_cmm_u_cfg_ctrl_cfg_rd_data_3_ ( + .CE(com_cmm_u_cfg_ctrl_next_state_0_sqmuxa_i_i_5398), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_cfg2tlm_rddata[3]), + .Q(com_cmm_cfg_rd_data[3]), + .CLR(com_cmm_rst_351) + ); + FDCE com_cmm_u_cfg_ctrl_cfg_rd_data_2_ ( + .CE(com_cmm_u_cfg_ctrl_next_state_0_sqmuxa_i_i_5398), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_cfg2tlm_rddata[2]), + .Q(com_cmm_cfg_rd_data[2]), + .CLR(com_cmm_rst_351) + ); + FDCE com_cmm_u_cfg_ctrl_cfg_rd_data_1_ ( + .CE(com_cmm_u_cfg_ctrl_next_state_0_sqmuxa_i_i_5398), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_cfg2tlm_rddata[1]), + .Q(com_cmm_cfg_rd_data[1]), + .CLR(com_cmm_rst_351) + ); + FDCE com_cmm_u_cfg_ctrl_cfg_rd_data_0_ ( + .CE(com_cmm_u_cfg_ctrl_next_state_0_sqmuxa_i_i_5398), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_cfg2tlm_rddata[0]), + .Q(com_cmm_cfg_rd_data[0]), + .CLR(com_cmm_rst_351) + ); + INV com_cmm_u_cfg_ctrl_next_state_0_sqmuxa_i_i ( + .I(com_cmm_u_cfg_ctrl_next_state_0_sqmuxa_i), + .O(com_cmm_u_cfg_ctrl_next_state_0_sqmuxa_i_i_5398) + ); + VCC com_cmm_u_cmm_decoder_VCC ( + .P(com_cmm_u_cmm_decoder_VCC_5484) + ); + GND com_cmm_u_cmm_decoder_GND ( + .G(com_cmm_u_cmm_decoder_GND_5513) + ); + MUXCY_L com_cmm_u_cmm_decoder_un10_bar45_64_hit_low_0_I_1 ( + .CI(com_cmm_u_cmm_decoder_VCC_5484), + .DI(com_cmm_u_cmm_decoder_GND_5513), + .LO(com_cmm_u_cmm_decoder_data_tmp_14[0]), + .S(com_cmm_u_cmm_decoder_N_107_13) + ); + MUXCY_L com_cmm_u_cmm_decoder_un10_bar45_64_hit_low_0_I_10 ( + .CI(com_cmm_u_cmm_decoder_data_tmp_14[0]), + .DI(com_cmm_u_cmm_decoder_GND_5513), + .LO(com_cmm_u_cmm_decoder_data_tmp_15[1]), + .S(com_cmm_u_cmm_decoder_N_27_3) + ); + MUXCY_L com_cmm_u_cmm_decoder_un10_bar45_64_hit_low_0_I_19 ( + .CI(com_cmm_u_cmm_decoder_data_tmp_15[1]), + .DI(com_cmm_u_cmm_decoder_GND_5513), + .LO(com_cmm_u_cmm_decoder_data_tmp_15[2]), + .S(com_cmm_u_cmm_decoder_N_3_3) + ); + MUXCY_L com_cmm_u_cmm_decoder_un10_bar45_64_hit_low_0_I_37 ( + .CI(com_cmm_u_cmm_decoder_data_tmp_14[10]), + .DI(com_cmm_u_cmm_decoder_GND_5513), + .LO(com_cmm_u_cmm_decoder_data_tmp_14[11]), + .S(com_cmm_u_cmm_decoder_N_19_3) + ); + MUXCY_L com_cmm_u_cmm_decoder_un10_bar45_64_hit_low_0_I_46 ( + .CI(com_cmm_u_cmm_decoder_data_tmp_15[4]), + .DI(com_cmm_u_cmm_decoder_GND_5513), + .LO(com_cmm_u_cmm_decoder_data_tmp_15[5]), + .S(com_cmm_u_cmm_decoder_N_59_3) + ); + MUXCY_L com_cmm_u_cmm_decoder_un10_bar45_64_hit_low_0_I_55 ( + .CI(com_cmm_u_cmm_decoder_data_tmp_15[5]), + .DI(com_cmm_u_cmm_decoder_GND_5513), + .LO(com_cmm_u_cmm_decoder_data_tmp_15[6]), + .S(com_cmm_u_cmm_decoder_N_35_3) + ); + MUXCY_L com_cmm_u_cmm_decoder_un10_bar45_64_hit_low_0_I_64 ( + .CI(com_cmm_u_cmm_decoder_data_tmp_14[11]), + .DI(com_cmm_u_cmm_decoder_GND_5513), + .LO(com_cmm_u_cmm_decoder_data_tmp_14[12]), + .S(com_cmm_u_cmm_decoder_N_11_4) + ); + MUXCY_L com_cmm_u_cmm_decoder_un10_bar45_64_hit_low_0_I_73 ( + .CI(com_cmm_u_cmm_decoder_data_tmp_15[6]), + .DI(com_cmm_u_cmm_decoder_GND_5513), + .LO(com_cmm_u_cmm_decoder_data_tmp_15[7]), + .S(com_cmm_u_cmm_decoder_N_51_3) + ); + MUXCY_L com_cmm_u_cmm_decoder_un10_bar45_64_hit_low_0_I_82 ( + .CI(com_cmm_u_cmm_decoder_data_tmp_15[8]), + .DI(com_cmm_u_cmm_decoder_GND_5513), + .LO(com_cmm_u_cmm_decoder_data_tmp_15[9]), + .S(com_cmm_u_cmm_decoder_N_91_3) + ); + MUXCY_L com_cmm_u_cmm_decoder_un10_bar45_64_hit_low_0_I_91 ( + .CI(com_cmm_u_cmm_decoder_data_tmp_15[9]), + .DI(com_cmm_u_cmm_decoder_GND_5513), + .LO(com_cmm_u_cmm_decoder_data_tmp_14[10]), + .S(com_cmm_u_cmm_decoder_N_67_3) + ); + MUXCY_L com_cmm_u_cmm_decoder_un10_bar45_64_hit_low_0_I_100 ( + .CI(com_cmm_u_cmm_decoder_data_tmp_15[7]), + .DI(com_cmm_u_cmm_decoder_GND_5513), + .LO(com_cmm_u_cmm_decoder_data_tmp_15[8]), + .S(com_cmm_u_cmm_decoder_N_43_3) + ); + MUXCY_L com_cmm_u_cmm_decoder_un10_bar45_64_hit_low_0_I_109 ( + .CI(com_cmm_u_cmm_decoder_data_tmp_15[2]), + .DI(com_cmm_u_cmm_decoder_GND_5513), + .LO(com_cmm_u_cmm_decoder_data_tmp_15[3]), + .S(com_cmm_u_cmm_decoder_N_83_3) + ); + MUXCY_L com_cmm_u_cmm_decoder_un10_bar45_64_hit_low_0_I_118 ( + .CI(com_cmm_u_cmm_decoder_data_tmp_14[12]), + .DI(com_cmm_u_cmm_decoder_GND_5513), + .LO(com_cmm_u_cmm_decoder_data_tmp_3[13]), + .S(com_cmm_u_cmm_decoder_N_99_9) + ); + MUXCY_L com_cmm_u_cmm_decoder_un10_bar45_64_hit_low_0_I_127 ( + .CI(com_cmm_u_cmm_decoder_data_tmp_3[13]), + .DI(com_cmm_u_cmm_decoder_GND_5513), + .LO(com_cmm_u_cmm_decoder_data_tmp[14]), + .S(com_cmm_u_cmm_decoder_N_11) + ); + MUXCY_L com_cmm_u_cmm_decoder_un10_bar45_64_hit_low_0_I_136 ( + .CI(com_cmm_u_cmm_decoder_data_tmp_15[3]), + .DI(com_cmm_u_cmm_decoder_GND_5513), + .LO(com_cmm_u_cmm_decoder_data_tmp_15[4]), + .S(com_cmm_u_cmm_decoder_N_75_3) + ); + MUXCY_L com_cmm_u_cmm_decoder_un10_bar34_64_hit_low_0_I_1 ( + .CI(com_cmm_u_cmm_decoder_VCC_5484), + .DI(com_cmm_u_cmm_decoder_GND_5513), + .LO(com_cmm_u_cmm_decoder_data_tmp_13[0]), + .S(com_cmm_u_cmm_decoder_N_123) + ); + MUXCY_L com_cmm_u_cmm_decoder_un10_bar34_64_hit_low_0_I_10 ( + .CI(com_cmm_u_cmm_decoder_data_tmp_13[0]), + .DI(com_cmm_u_cmm_decoder_GND_5513), + .LO(com_cmm_u_cmm_decoder_data_tmp_14[1]), + .S(com_cmm_u_cmm_decoder_N_115) + ); + MUXCY_L com_cmm_u_cmm_decoder_un10_bar34_64_hit_low_0_I_19 ( + .CI(com_cmm_u_cmm_decoder_data_tmp_14[1]), + .DI(com_cmm_u_cmm_decoder_GND_5513), + .LO(com_cmm_u_cmm_decoder_data_tmp_14[2]), + .S(com_cmm_u_cmm_decoder_N_107) + ); + MUXCY_L com_cmm_u_cmm_decoder_un10_bar34_64_hit_low_0_I_37 ( + .CI(com_cmm_u_cmm_decoder_data_tmp_13[10]), + .DI(com_cmm_u_cmm_decoder_GND_5513), + .LO(com_cmm_u_cmm_decoder_data_tmp_13[11]), + .S(com_cmm_u_cmm_decoder_N_91) + ); + MUXCY_L com_cmm_u_cmm_decoder_un10_bar34_64_hit_low_0_I_46 ( + .CI(com_cmm_u_cmm_decoder_data_tmp_14[4]), + .DI(com_cmm_u_cmm_decoder_GND_5513), + .LO(com_cmm_u_cmm_decoder_data_tmp_14[5]), + .S(com_cmm_u_cmm_decoder_N_83) + ); + MUXCY_L com_cmm_u_cmm_decoder_un10_bar34_64_hit_low_0_I_55 ( + .CI(com_cmm_u_cmm_decoder_data_tmp_14[5]), + .DI(com_cmm_u_cmm_decoder_GND_5513), + .LO(com_cmm_u_cmm_decoder_data_tmp_14[6]), + .S(com_cmm_u_cmm_decoder_N_75) + ); + MUXCY_L com_cmm_u_cmm_decoder_un10_bar34_64_hit_low_0_I_64 ( + .CI(com_cmm_u_cmm_decoder_data_tmp_13[11]), + .DI(com_cmm_u_cmm_decoder_GND_5513), + .LO(com_cmm_u_cmm_decoder_data_tmp_13[12]), + .S(com_cmm_u_cmm_decoder_N_67) + ); + MUXCY_L com_cmm_u_cmm_decoder_un10_bar34_64_hit_low_0_I_73 ( + .CI(com_cmm_u_cmm_decoder_data_tmp_14[6]), + .DI(com_cmm_u_cmm_decoder_GND_5513), + .LO(com_cmm_u_cmm_decoder_data_tmp_14[7]), + .S(com_cmm_u_cmm_decoder_N_59) + ); + MUXCY_L com_cmm_u_cmm_decoder_un10_bar34_64_hit_low_0_I_82 ( + .CI(com_cmm_u_cmm_decoder_data_tmp_14[8]), + .DI(com_cmm_u_cmm_decoder_GND_5513), + .LO(com_cmm_u_cmm_decoder_data_tmp_14[9]), + .S(com_cmm_u_cmm_decoder_N_51) + ); + MUXCY_L com_cmm_u_cmm_decoder_un10_bar34_64_hit_low_0_I_91 ( + .CI(com_cmm_u_cmm_decoder_data_tmp_14[9]), + .DI(com_cmm_u_cmm_decoder_GND_5513), + .LO(com_cmm_u_cmm_decoder_data_tmp_13[10]), + .S(com_cmm_u_cmm_decoder_N_43) + ); + MUXCY_L com_cmm_u_cmm_decoder_un10_bar34_64_hit_low_0_I_100 ( + .CI(com_cmm_u_cmm_decoder_data_tmp_14[7]), + .DI(com_cmm_u_cmm_decoder_GND_5513), + .LO(com_cmm_u_cmm_decoder_data_tmp_14[8]), + .S(com_cmm_u_cmm_decoder_N_35) + ); + MUXCY_L com_cmm_u_cmm_decoder_un10_bar34_64_hit_low_0_I_109 ( + .CI(com_cmm_u_cmm_decoder_data_tmp_14[2]), + .DI(com_cmm_u_cmm_decoder_GND_5513), + .LO(com_cmm_u_cmm_decoder_data_tmp_14[3]), + .S(com_cmm_u_cmm_decoder_N_27) + ); + MUXCY_L com_cmm_u_cmm_decoder_un10_bar34_64_hit_low_0_I_118 ( + .CI(com_cmm_u_cmm_decoder_data_tmp_13[12]), + .DI(com_cmm_u_cmm_decoder_GND_5513), + .LO(com_cmm_u_cmm_decoder_data_tmp_2[13]), + .S(com_cmm_u_cmm_decoder_N_19) + ); + MUXCY_L com_cmm_u_cmm_decoder_un10_bar34_64_hit_low_0_I_127 ( + .CI(com_cmm_u_cmm_decoder_data_tmp_2[13]), + .DI(com_cmm_u_cmm_decoder_GND_5513), + .LO(com_cmm_u_cmm_decoder_data_tmp_0[14]), + .S(com_cmm_u_cmm_decoder_N_11_0) + ); + MUXCY_L com_cmm_u_cmm_decoder_un10_bar34_64_hit_low_0_I_136 ( + .CI(com_cmm_u_cmm_decoder_data_tmp_14[3]), + .DI(com_cmm_u_cmm_decoder_GND_5513), + .LO(com_cmm_u_cmm_decoder_data_tmp_14[4]), + .S(com_cmm_u_cmm_decoder_N_3) + ); + MUXCY_L com_cmm_u_cmm_decoder_un10_bar23_64_hit_low_0_I_1 ( + .CI(com_cmm_u_cmm_decoder_VCC_5484), + .DI(com_cmm_u_cmm_decoder_GND_5513), + .LO(com_cmm_u_cmm_decoder_data_tmp_12[0]), + .S(com_cmm_u_cmm_decoder_N_123_0) + ); + MUXCY_L com_cmm_u_cmm_decoder_un10_bar23_64_hit_low_0_I_10 ( + .CI(com_cmm_u_cmm_decoder_data_tmp_12[0]), + .DI(com_cmm_u_cmm_decoder_GND_5513), + .LO(com_cmm_u_cmm_decoder_data_tmp_13[1]), + .S(com_cmm_u_cmm_decoder_N_115_0) + ); + MUXCY_L com_cmm_u_cmm_decoder_un10_bar23_64_hit_low_0_I_19 ( + .CI(com_cmm_u_cmm_decoder_data_tmp_13[1]), + .DI(com_cmm_u_cmm_decoder_GND_5513), + .LO(com_cmm_u_cmm_decoder_data_tmp_13[2]), + .S(com_cmm_u_cmm_decoder_N_107_0) + ); + MUXCY_L com_cmm_u_cmm_decoder_un10_bar23_64_hit_low_0_I_37 ( + .CI(com_cmm_u_cmm_decoder_data_tmp_12[10]), + .DI(com_cmm_u_cmm_decoder_GND_5513), + .LO(com_cmm_u_cmm_decoder_data_tmp_12[11]), + .S(com_cmm_u_cmm_decoder_N_91_0) + ); + MUXCY_L com_cmm_u_cmm_decoder_un10_bar23_64_hit_low_0_I_46 ( + .CI(com_cmm_u_cmm_decoder_data_tmp_13[4]), + .DI(com_cmm_u_cmm_decoder_GND_5513), + .LO(com_cmm_u_cmm_decoder_data_tmp_13[5]), + .S(com_cmm_u_cmm_decoder_N_83_0) + ); + MUXCY_L com_cmm_u_cmm_decoder_un10_bar23_64_hit_low_0_I_55 ( + .CI(com_cmm_u_cmm_decoder_data_tmp_13[5]), + .DI(com_cmm_u_cmm_decoder_GND_5513), + .LO(com_cmm_u_cmm_decoder_data_tmp_13[6]), + .S(com_cmm_u_cmm_decoder_N_75_0) + ); + MUXCY_L com_cmm_u_cmm_decoder_un10_bar23_64_hit_low_0_I_64 ( + .CI(com_cmm_u_cmm_decoder_data_tmp_12[11]), + .DI(com_cmm_u_cmm_decoder_GND_5513), + .LO(com_cmm_u_cmm_decoder_data_tmp_12[12]), + .S(com_cmm_u_cmm_decoder_N_67_0) + ); + MUXCY_L com_cmm_u_cmm_decoder_un10_bar23_64_hit_low_0_I_73 ( + .CI(com_cmm_u_cmm_decoder_data_tmp_13[6]), + .DI(com_cmm_u_cmm_decoder_GND_5513), + .LO(com_cmm_u_cmm_decoder_data_tmp_13[7]), + .S(com_cmm_u_cmm_decoder_N_59_0) + ); + MUXCY_L com_cmm_u_cmm_decoder_un10_bar23_64_hit_low_0_I_82 ( + .CI(com_cmm_u_cmm_decoder_data_tmp_13[8]), + .DI(com_cmm_u_cmm_decoder_GND_5513), + .LO(com_cmm_u_cmm_decoder_data_tmp_13[9]), + .S(com_cmm_u_cmm_decoder_N_51_0) + ); + MUXCY_L com_cmm_u_cmm_decoder_un10_bar23_64_hit_low_0_I_91 ( + .CI(com_cmm_u_cmm_decoder_data_tmp_13[9]), + .DI(com_cmm_u_cmm_decoder_GND_5513), + .LO(com_cmm_u_cmm_decoder_data_tmp_12[10]), + .S(com_cmm_u_cmm_decoder_N_43_0) + ); + MUXCY_L com_cmm_u_cmm_decoder_un10_bar23_64_hit_low_0_I_100 ( + .CI(com_cmm_u_cmm_decoder_data_tmp_13[7]), + .DI(com_cmm_u_cmm_decoder_GND_5513), + .LO(com_cmm_u_cmm_decoder_data_tmp_13[8]), + .S(com_cmm_u_cmm_decoder_N_35_0) + ); + MUXCY_L com_cmm_u_cmm_decoder_un10_bar23_64_hit_low_0_I_109 ( + .CI(com_cmm_u_cmm_decoder_data_tmp_13[2]), + .DI(com_cmm_u_cmm_decoder_GND_5513), + .LO(com_cmm_u_cmm_decoder_data_tmp_13[3]), + .S(com_cmm_u_cmm_decoder_N_27_0) + ); + MUXCY_L com_cmm_u_cmm_decoder_un10_bar23_64_hit_low_0_I_118 ( + .CI(com_cmm_u_cmm_decoder_data_tmp_12[12]), + .DI(com_cmm_u_cmm_decoder_GND_5513), + .LO(com_cmm_u_cmm_decoder_data_tmp_1[13]), + .S(com_cmm_u_cmm_decoder_N_19_0) + ); + MUXCY_L com_cmm_u_cmm_decoder_un10_bar23_64_hit_low_0_I_127 ( + .CI(com_cmm_u_cmm_decoder_data_tmp_1[13]), + .DI(com_cmm_u_cmm_decoder_GND_5513), + .LO(com_cmm_u_cmm_decoder_data_tmp_1[14]), + .S(com_cmm_u_cmm_decoder_N_11_1) + ); + MUXCY_L com_cmm_u_cmm_decoder_un10_bar23_64_hit_low_0_I_136 ( + .CI(com_cmm_u_cmm_decoder_data_tmp_13[3]), + .DI(com_cmm_u_cmm_decoder_GND_5513), + .LO(com_cmm_u_cmm_decoder_data_tmp_13[4]), + .S(com_cmm_u_cmm_decoder_N_3_0) + ); + MUXCY_L com_cmm_u_cmm_decoder_un10_bar12_64_hit_low_0_I_1 ( + .CI(com_cmm_u_cmm_decoder_VCC_5484), + .DI(com_cmm_u_cmm_decoder_GND_5513), + .LO(com_cmm_u_cmm_decoder_data_tmp_11[0]), + .S(com_cmm_u_cmm_decoder_N_123_1) + ); + MUXCY_L com_cmm_u_cmm_decoder_un10_bar12_64_hit_low_0_I_10 ( + .CI(com_cmm_u_cmm_decoder_data_tmp_11[0]), + .DI(com_cmm_u_cmm_decoder_GND_5513), + .LO(com_cmm_u_cmm_decoder_data_tmp_12[1]), + .S(com_cmm_u_cmm_decoder_N_115_1) + ); + MUXCY_L com_cmm_u_cmm_decoder_un10_bar12_64_hit_low_0_I_19 ( + .CI(com_cmm_u_cmm_decoder_data_tmp_12[1]), + .DI(com_cmm_u_cmm_decoder_GND_5513), + .LO(com_cmm_u_cmm_decoder_data_tmp_12[2]), + .S(com_cmm_u_cmm_decoder_N_107_1) + ); + MUXCY_L com_cmm_u_cmm_decoder_un10_bar12_64_hit_low_0_I_37 ( + .CI(com_cmm_u_cmm_decoder_data_tmp_11[10]), + .DI(com_cmm_u_cmm_decoder_GND_5513), + .LO(com_cmm_u_cmm_decoder_data_tmp_11[11]), + .S(com_cmm_u_cmm_decoder_N_91_1) + ); + MUXCY_L com_cmm_u_cmm_decoder_un10_bar12_64_hit_low_0_I_46 ( + .CI(com_cmm_u_cmm_decoder_data_tmp_12[4]), + .DI(com_cmm_u_cmm_decoder_GND_5513), + .LO(com_cmm_u_cmm_decoder_data_tmp_12[5]), + .S(com_cmm_u_cmm_decoder_N_83_1) + ); + MUXCY_L com_cmm_u_cmm_decoder_un10_bar12_64_hit_low_0_I_55 ( + .CI(com_cmm_u_cmm_decoder_data_tmp_12[5]), + .DI(com_cmm_u_cmm_decoder_GND_5513), + .LO(com_cmm_u_cmm_decoder_data_tmp_12[6]), + .S(com_cmm_u_cmm_decoder_N_75_1) + ); + MUXCY_L com_cmm_u_cmm_decoder_un10_bar12_64_hit_low_0_I_64 ( + .CI(com_cmm_u_cmm_decoder_data_tmp_11[11]), + .DI(com_cmm_u_cmm_decoder_GND_5513), + .LO(com_cmm_u_cmm_decoder_data_tmp_11[12]), + .S(com_cmm_u_cmm_decoder_N_67_1) + ); + MUXCY_L com_cmm_u_cmm_decoder_un10_bar12_64_hit_low_0_I_73 ( + .CI(com_cmm_u_cmm_decoder_data_tmp_12[6]), + .DI(com_cmm_u_cmm_decoder_GND_5513), + .LO(com_cmm_u_cmm_decoder_data_tmp_12[7]), + .S(com_cmm_u_cmm_decoder_N_59_1) + ); + MUXCY_L com_cmm_u_cmm_decoder_un10_bar12_64_hit_low_0_I_82 ( + .CI(com_cmm_u_cmm_decoder_data_tmp_12[8]), + .DI(com_cmm_u_cmm_decoder_GND_5513), + .LO(com_cmm_u_cmm_decoder_data_tmp_12[9]), + .S(com_cmm_u_cmm_decoder_N_51_1) + ); + MUXCY_L com_cmm_u_cmm_decoder_un10_bar12_64_hit_low_0_I_91 ( + .CI(com_cmm_u_cmm_decoder_data_tmp_12[9]), + .DI(com_cmm_u_cmm_decoder_GND_5513), + .LO(com_cmm_u_cmm_decoder_data_tmp_11[10]), + .S(com_cmm_u_cmm_decoder_N_43_1) + ); + MUXCY_L com_cmm_u_cmm_decoder_un10_bar12_64_hit_low_0_I_100 ( + .CI(com_cmm_u_cmm_decoder_data_tmp_12[7]), + .DI(com_cmm_u_cmm_decoder_GND_5513), + .LO(com_cmm_u_cmm_decoder_data_tmp_12[8]), + .S(com_cmm_u_cmm_decoder_N_35_1) + ); + MUXCY_L com_cmm_u_cmm_decoder_un10_bar12_64_hit_low_0_I_109 ( + .CI(com_cmm_u_cmm_decoder_data_tmp_12[2]), + .DI(com_cmm_u_cmm_decoder_GND_5513), + .LO(com_cmm_u_cmm_decoder_data_tmp_12[3]), + .S(com_cmm_u_cmm_decoder_N_27_1) + ); + MUXCY_L com_cmm_u_cmm_decoder_un10_bar12_64_hit_low_0_I_118 ( + .CI(com_cmm_u_cmm_decoder_data_tmp_11[12]), + .DI(com_cmm_u_cmm_decoder_GND_5513), + .LO(com_cmm_u_cmm_decoder_data_tmp_0[13]), + .S(com_cmm_u_cmm_decoder_N_19_1) + ); + MUXCY_L com_cmm_u_cmm_decoder_un10_bar12_64_hit_low_0_I_127 ( + .CI(com_cmm_u_cmm_decoder_data_tmp_0[13]), + .DI(com_cmm_u_cmm_decoder_GND_5513), + .LO(com_cmm_u_cmm_decoder_data_tmp_2[14]), + .S(com_cmm_u_cmm_decoder_N_11_2) + ); + MUXCY_L com_cmm_u_cmm_decoder_un10_bar12_64_hit_low_0_I_136 ( + .CI(com_cmm_u_cmm_decoder_data_tmp_12[3]), + .DI(com_cmm_u_cmm_decoder_GND_5513), + .LO(com_cmm_u_cmm_decoder_data_tmp_12[4]), + .S(com_cmm_u_cmm_decoder_N_3_1) + ); + MUXCY_L com_cmm_u_cmm_decoder_un10_bar01_64_hit_low_0_I_1 ( + .CI(com_cmm_u_cmm_decoder_VCC_5484), + .DI(com_cmm_u_cmm_decoder_GND_5513), + .LO(com_cmm_u_cmm_decoder_data_tmp_10[0]), + .S(com_cmm_u_cmm_decoder_N_123_2) + ); + MUXCY_L com_cmm_u_cmm_decoder_un10_bar01_64_hit_low_0_I_10 ( + .CI(com_cmm_u_cmm_decoder_data_tmp_10[0]), + .DI(com_cmm_u_cmm_decoder_GND_5513), + .LO(com_cmm_u_cmm_decoder_data_tmp_11[1]), + .S(com_cmm_u_cmm_decoder_N_115_2) + ); + MUXCY_L com_cmm_u_cmm_decoder_un10_bar01_64_hit_low_0_I_19 ( + .CI(com_cmm_u_cmm_decoder_data_tmp_11[1]), + .DI(com_cmm_u_cmm_decoder_GND_5513), + .LO(com_cmm_u_cmm_decoder_data_tmp_11[2]), + .S(com_cmm_u_cmm_decoder_N_107_2) + ); + MUXCY_L com_cmm_u_cmm_decoder_un10_bar01_64_hit_low_0_I_37 ( + .CI(com_cmm_u_cmm_decoder_data_tmp_10[10]), + .DI(com_cmm_u_cmm_decoder_GND_5513), + .LO(com_cmm_u_cmm_decoder_data_tmp_10[11]), + .S(com_cmm_u_cmm_decoder_N_91_2) + ); + MUXCY_L com_cmm_u_cmm_decoder_un10_bar01_64_hit_low_0_I_46 ( + .CI(com_cmm_u_cmm_decoder_data_tmp_11[4]), + .DI(com_cmm_u_cmm_decoder_GND_5513), + .LO(com_cmm_u_cmm_decoder_data_tmp_11[5]), + .S(com_cmm_u_cmm_decoder_N_83_2) + ); + MUXCY_L com_cmm_u_cmm_decoder_un10_bar01_64_hit_low_0_I_55 ( + .CI(com_cmm_u_cmm_decoder_data_tmp_11[5]), + .DI(com_cmm_u_cmm_decoder_GND_5513), + .LO(com_cmm_u_cmm_decoder_data_tmp_11[6]), + .S(com_cmm_u_cmm_decoder_N_75_2) + ); + MUXCY_L com_cmm_u_cmm_decoder_un10_bar01_64_hit_low_0_I_64 ( + .CI(com_cmm_u_cmm_decoder_data_tmp_10[11]), + .DI(com_cmm_u_cmm_decoder_GND_5513), + .LO(com_cmm_u_cmm_decoder_data_tmp_10[12]), + .S(com_cmm_u_cmm_decoder_N_67_2) + ); + MUXCY_L com_cmm_u_cmm_decoder_un10_bar01_64_hit_low_0_I_73 ( + .CI(com_cmm_u_cmm_decoder_data_tmp_11[6]), + .DI(com_cmm_u_cmm_decoder_GND_5513), + .LO(com_cmm_u_cmm_decoder_data_tmp_11[7]), + .S(com_cmm_u_cmm_decoder_N_59_2) + ); + MUXCY_L com_cmm_u_cmm_decoder_un10_bar01_64_hit_low_0_I_82 ( + .CI(com_cmm_u_cmm_decoder_data_tmp_11[8]), + .DI(com_cmm_u_cmm_decoder_GND_5513), + .LO(com_cmm_u_cmm_decoder_data_tmp_11[9]), + .S(com_cmm_u_cmm_decoder_N_51_2) + ); + MUXCY_L com_cmm_u_cmm_decoder_un10_bar01_64_hit_low_0_I_91 ( + .CI(com_cmm_u_cmm_decoder_data_tmp_11[9]), + .DI(com_cmm_u_cmm_decoder_GND_5513), + .LO(com_cmm_u_cmm_decoder_data_tmp_10[10]), + .S(com_cmm_u_cmm_decoder_N_43_2) + ); + MUXCY_L com_cmm_u_cmm_decoder_un10_bar01_64_hit_low_0_I_100 ( + .CI(com_cmm_u_cmm_decoder_data_tmp_11[7]), + .DI(com_cmm_u_cmm_decoder_GND_5513), + .LO(com_cmm_u_cmm_decoder_data_tmp_11[8]), + .S(com_cmm_u_cmm_decoder_N_35_2) + ); + MUXCY_L com_cmm_u_cmm_decoder_un10_bar01_64_hit_low_0_I_109 ( + .CI(com_cmm_u_cmm_decoder_data_tmp_11[2]), + .DI(com_cmm_u_cmm_decoder_GND_5513), + .LO(com_cmm_u_cmm_decoder_data_tmp_11[3]), + .S(com_cmm_u_cmm_decoder_N_27_2) + ); + MUXCY_L com_cmm_u_cmm_decoder_un10_bar01_64_hit_low_0_I_118 ( + .CI(com_cmm_u_cmm_decoder_data_tmp_10[12]), + .DI(com_cmm_u_cmm_decoder_GND_5513), + .LO(com_cmm_u_cmm_decoder_data_tmp[13]), + .S(com_cmm_u_cmm_decoder_N_19_2) + ); + MUXCY_L com_cmm_u_cmm_decoder_un10_bar01_64_hit_low_0_I_127 ( + .CI(com_cmm_u_cmm_decoder_data_tmp[13]), + .DI(com_cmm_u_cmm_decoder_GND_5513), + .LO(com_cmm_u_cmm_decoder_data_tmp_3[14]), + .S(com_cmm_u_cmm_decoder_N_11_3) + ); + MUXCY_L com_cmm_u_cmm_decoder_un10_bar01_64_hit_low_0_I_136 ( + .CI(com_cmm_u_cmm_decoder_data_tmp_11[3]), + .DI(com_cmm_u_cmm_decoder_GND_5513), + .LO(com_cmm_u_cmm_decoder_data_tmp_11[4]), + .S(com_cmm_u_cmm_decoder_N_3_2) + ); + MUXCY_L com_cmm_u_cmm_decoder_bar5_eq_raddr_3_0_I_19 ( + .CI(com_cmm_u_cmm_decoder_data_tmp_10[8]), + .DI(com_cmm_u_cmm_decoder_GND_5513), + .LO(com_cmm_u_cmm_decoder_data_tmp_10[9]), + .S(com_cmm_u_cmm_decoder_I_19_sf) + ); + MUXCY_L com_cmm_u_cmm_decoder_bar5_eq_raddr_3_0_I_28 ( + .CI(com_cmm_u_cmm_decoder_data_tmp_10[2]), + .DI(com_cmm_u_cmm_decoder_GND_5513), + .LO(com_cmm_u_cmm_decoder_data_tmp_10[3]), + .S(com_cmm_u_cmm_decoder_I_28_sf) + ); + MUXCY_L com_cmm_u_cmm_decoder_bar5_eq_raddr_3_0_I_37 ( + .CI(com_cmm_u_cmm_decoder_data_tmp_10[3]), + .DI(com_cmm_u_cmm_decoder_GND_5513), + .LO(com_cmm_u_cmm_decoder_data_tmp_10[4]), + .S(com_cmm_u_cmm_decoder_I_37_sf) + ); + MUXCY_L com_cmm_u_cmm_decoder_bar5_eq_raddr_3_0_I_46 ( + .CI(com_cmm_u_cmm_decoder_data_tmp_10[9]), + .DI(com_cmm_u_cmm_decoder_GND_5513), + .LO(com_cmm_u_cmm_decoder_data_tmp_9[10]), + .S(com_cmm_u_cmm_decoder_I_46_sf) + ); + MUXCY_L com_cmm_u_cmm_decoder_bar5_eq_raddr_3_0_I_55 ( + .CI(com_cmm_u_cmm_decoder_data_tmp_10[4]), + .DI(com_cmm_u_cmm_decoder_GND_5513), + .LO(com_cmm_u_cmm_decoder_data_tmp_10[5]), + .S(com_cmm_u_cmm_decoder_I_55_sf) + ); + MUXCY_L com_cmm_u_cmm_decoder_bar5_eq_raddr_3_0_I_64 ( + .CI(com_cmm_u_cmm_decoder_data_tmp_10[6]), + .DI(com_cmm_u_cmm_decoder_GND_5513), + .LO(com_cmm_u_cmm_decoder_data_tmp_10[7]), + .S(com_cmm_u_cmm_decoder_I_64_sf) + ); + MUXCY_L com_cmm_u_cmm_decoder_bar5_eq_raddr_3_0_I_73 ( + .CI(com_cmm_u_cmm_decoder_data_tmp_10[7]), + .DI(com_cmm_u_cmm_decoder_GND_5513), + .LO(com_cmm_u_cmm_decoder_data_tmp_10[8]), + .S(com_cmm_u_cmm_decoder_I_73_sf) + ); + MUXCY_L com_cmm_u_cmm_decoder_bar5_eq_raddr_3_0_I_82 ( + .CI(com_cmm_u_cmm_decoder_data_tmp_10[5]), + .DI(com_cmm_u_cmm_decoder_GND_5513), + .LO(com_cmm_u_cmm_decoder_data_tmp_10[6]), + .S(com_cmm_u_cmm_decoder_I_82_sf) + ); + MUXCY_L com_cmm_u_cmm_decoder_bar5_eq_raddr_3_0_I_91 ( + .CI(com_cmm_u_cmm_decoder_N_107_13), + .DI(com_cmm_u_cmm_decoder_GND_5513), + .LO(com_cmm_u_cmm_decoder_data_tmp_10[1]), + .S(com_cmm_u_cmm_decoder_I_91_sf) + ); + MUXCY_L com_cmm_u_cmm_decoder_bar5_eq_raddr_3_0_I_100 ( + .CI(com_cmm_u_cmm_decoder_data_tmp_9[10]), + .DI(com_cmm_u_cmm_decoder_GND_5513), + .LO(com_cmm_u_cmm_decoder_data_tmp_9[11]), + .S(com_cmm_u_cmm_decoder_I_100_sf) + ); + MUXCY_L com_cmm_u_cmm_decoder_bar5_eq_raddr_3_0_I_109 ( + .CI(com_cmm_u_cmm_decoder_data_tmp_9[11]), + .DI(com_cmm_u_cmm_decoder_GND_5513), + .LO(com_cmm_u_cmm_decoder_data_tmp[12]), + .S(com_cmm_u_cmm_decoder_I_109_sf) + ); + MUXCY_L com_cmm_u_cmm_decoder_bar5_eq_raddr_3_0_I_118 ( + .CI(com_cmm_u_cmm_decoder_data_tmp_10[1]), + .DI(com_cmm_u_cmm_decoder_GND_5513), + .LO(com_cmm_u_cmm_decoder_data_tmp_10[2]), + .S(com_cmm_u_cmm_decoder_I_118_sf) + ); + MUXCY_L com_cmm_u_cmm_decoder_bar6_eq_raddr_3_0_I_1 ( + .CI(com_cmm_u_cmm_decoder_VCC_5484), + .DI(com_cmm_u_cmm_decoder_GND_5513), + .LO(com_cmm_u_cmm_decoder_data_tmp_9[0]), + .S(com_cmm_u_cmm_decoder_N_81) + ); + MUXCY_L com_cmm_u_cmm_decoder_bar6_eq_raddr_3_0_I_10 ( + .CI(com_cmm_u_cmm_decoder_data_tmp_9[8]), + .DI(com_cmm_u_cmm_decoder_GND_5513), + .LO(com_cmm_u_cmm_decoder_data_tmp[9]), + .S(com_cmm_u_cmm_decoder_N_73) + ); + MUXCY_L com_cmm_u_cmm_decoder_bar6_eq_raddr_3_0_I_19 ( + .CI(com_cmm_u_cmm_decoder_data_tmp_9[1]), + .DI(com_cmm_u_cmm_decoder_GND_5513), + .LO(com_cmm_u_cmm_decoder_data_tmp_9[2]), + .S(com_cmm_u_cmm_decoder_N_65) + ); + MUXCY_L com_cmm_u_cmm_decoder_bar6_eq_raddr_3_0_I_28 ( + .CI(com_cmm_u_cmm_decoder_data_tmp_9[2]), + .DI(com_cmm_u_cmm_decoder_GND_5513), + .LO(com_cmm_u_cmm_decoder_data_tmp_9[3]), + .S(com_cmm_u_cmm_decoder_N_57) + ); + MUXCY_L com_cmm_u_cmm_decoder_bar6_eq_raddr_3_0_I_37 ( + .CI(com_cmm_u_cmm_decoder_data_tmp_9[4]), + .DI(com_cmm_u_cmm_decoder_GND_5513), + .LO(com_cmm_u_cmm_decoder_data_tmp_9[5]), + .S(com_cmm_u_cmm_decoder_N_49) + ); + MUXCY_L com_cmm_u_cmm_decoder_bar6_eq_raddr_3_0_I_46 ( + .CI(com_cmm_u_cmm_decoder_data_tmp_9[7]), + .DI(com_cmm_u_cmm_decoder_GND_5513), + .LO(com_cmm_u_cmm_decoder_data_tmp_9[8]), + .S(com_cmm_u_cmm_decoder_N_41) + ); + MUXCY_L com_cmm_u_cmm_decoder_bar6_eq_raddr_3_0_I_55 ( + .CI(com_cmm_u_cmm_decoder_data_tmp_9[5]), + .DI(com_cmm_u_cmm_decoder_GND_5513), + .LO(com_cmm_u_cmm_decoder_data_tmp_9[6]), + .S(com_cmm_u_cmm_decoder_N_33) + ); + MUXCY_L com_cmm_u_cmm_decoder_bar6_eq_raddr_3_0_I_64 ( + .CI(com_cmm_u_cmm_decoder_data_tmp_9[6]), + .DI(com_cmm_u_cmm_decoder_GND_5513), + .LO(com_cmm_u_cmm_decoder_data_tmp_9[7]), + .S(com_cmm_u_cmm_decoder_N_25) + ); + MUXCY_L com_cmm_u_cmm_decoder_bar6_eq_raddr_3_0_I_73 ( + .CI(com_cmm_u_cmm_decoder_data_tmp_9[0]), + .DI(com_cmm_u_cmm_decoder_GND_5513), + .LO(com_cmm_u_cmm_decoder_data_tmp_9[1]), + .S(com_cmm_u_cmm_decoder_N_17) + ); + MUXCY_L com_cmm_u_cmm_decoder_bar6_eq_raddr_3_0_I_82 ( + .CI(com_cmm_u_cmm_decoder_data_tmp_9[3]), + .DI(com_cmm_u_cmm_decoder_GND_5513), + .LO(com_cmm_u_cmm_decoder_data_tmp_9[4]), + .S(com_cmm_u_cmm_decoder_N_9) + ); + MUXCY_L com_cmm_u_cmm_decoder_un9_bar01_64_hit_high_0_I_1 ( + .CI(com_cmm_u_cmm_decoder_VCC_5484), + .DI(com_cmm_u_cmm_decoder_GND_5513), + .LO(com_cmm_u_cmm_decoder_data_tmp_8[0]), + .S(com_cmm_u_cmm_decoder_N_107_3) + ); + MUXCY_L com_cmm_u_cmm_decoder_un9_bar01_64_hit_high_0_I_19 ( + .CI(com_cmm_u_cmm_decoder_data_tmp_8[8]), + .DI(com_cmm_u_cmm_decoder_GND_5513), + .LO(com_cmm_u_cmm_decoder_data_tmp_9[9]), + .S(com_cmm_u_cmm_decoder_N_91_4) + ); + MUXCY_L com_cmm_u_cmm_decoder_un9_bar01_64_hit_high_0_I_28 ( + .CI(com_cmm_u_cmm_decoder_data_tmp_8[2]), + .DI(com_cmm_u_cmm_decoder_GND_5513), + .LO(com_cmm_u_cmm_decoder_data_tmp_8[3]), + .S(com_cmm_u_cmm_decoder_N_83_4) + ); + MUXCY_L com_cmm_u_cmm_decoder_un9_bar01_64_hit_high_0_I_37 ( + .CI(com_cmm_u_cmm_decoder_data_tmp_8[3]), + .DI(com_cmm_u_cmm_decoder_GND_5513), + .LO(com_cmm_u_cmm_decoder_data_tmp_8[4]), + .S(com_cmm_u_cmm_decoder_N_75_4) + ); + MUXCY_L com_cmm_u_cmm_decoder_un9_bar01_64_hit_high_0_I_46 ( + .CI(com_cmm_u_cmm_decoder_data_tmp_9[9]), + .DI(com_cmm_u_cmm_decoder_GND_5513), + .LO(com_cmm_u_cmm_decoder_data_tmp_8[10]), + .S(com_cmm_u_cmm_decoder_N_67_4) + ); + MUXCY_L com_cmm_u_cmm_decoder_un9_bar01_64_hit_high_0_I_55 ( + .CI(com_cmm_u_cmm_decoder_data_tmp_8[4]), + .DI(com_cmm_u_cmm_decoder_GND_5513), + .LO(com_cmm_u_cmm_decoder_data_tmp_8[5]), + .S(com_cmm_u_cmm_decoder_N_59_4) + ); + MUXCY_L com_cmm_u_cmm_decoder_un9_bar01_64_hit_high_0_I_64 ( + .CI(com_cmm_u_cmm_decoder_data_tmp_8[6]), + .DI(com_cmm_u_cmm_decoder_GND_5513), + .LO(com_cmm_u_cmm_decoder_data_tmp_8[7]), + .S(com_cmm_u_cmm_decoder_N_51_4) + ); + MUXCY_L com_cmm_u_cmm_decoder_un9_bar01_64_hit_high_0_I_73 ( + .CI(com_cmm_u_cmm_decoder_data_tmp_8[7]), + .DI(com_cmm_u_cmm_decoder_GND_5513), + .LO(com_cmm_u_cmm_decoder_data_tmp_8[8]), + .S(com_cmm_u_cmm_decoder_N_43_4) + ); + MUXCY_L com_cmm_u_cmm_decoder_un9_bar01_64_hit_high_0_I_82 ( + .CI(com_cmm_u_cmm_decoder_data_tmp_8[5]), + .DI(com_cmm_u_cmm_decoder_GND_5513), + .LO(com_cmm_u_cmm_decoder_data_tmp_8[6]), + .S(com_cmm_u_cmm_decoder_N_35_4) + ); + MUXCY_L com_cmm_u_cmm_decoder_un9_bar01_64_hit_high_0_I_91 ( + .CI(com_cmm_u_cmm_decoder_data_tmp_8[0]), + .DI(com_cmm_u_cmm_decoder_GND_5513), + .LO(com_cmm_u_cmm_decoder_data_tmp_8[1]), + .S(com_cmm_u_cmm_decoder_N_27_4) + ); + MUXCY_L com_cmm_u_cmm_decoder_un9_bar01_64_hit_high_0_I_100 ( + .CI(com_cmm_u_cmm_decoder_data_tmp_8[10]), + .DI(com_cmm_u_cmm_decoder_GND_5513), + .LO(com_cmm_u_cmm_decoder_data_tmp_8[11]), + .S(com_cmm_u_cmm_decoder_N_19_4) + ); + MUXCY_L com_cmm_u_cmm_decoder_un9_bar01_64_hit_high_0_I_109 ( + .CI(com_cmm_u_cmm_decoder_data_tmp_8[11]), + .DI(com_cmm_u_cmm_decoder_GND_5513), + .LO(com_cmm_u_cmm_decoder_data_tmp_0[12]), + .S(com_cmm_u_cmm_decoder_N_11_5) + ); + MUXCY_L com_cmm_u_cmm_decoder_un9_bar01_64_hit_high_0_I_118 ( + .CI(com_cmm_u_cmm_decoder_data_tmp_8[1]), + .DI(com_cmm_u_cmm_decoder_GND_5513), + .LO(com_cmm_u_cmm_decoder_data_tmp_8[2]), + .S(com_cmm_u_cmm_decoder_N_3_4) + ); + MUXCY_L com_cmm_u_cmm_decoder_un9_bar12_64_hit_high_0_I_1 ( + .CI(com_cmm_u_cmm_decoder_VCC_5484), + .DI(com_cmm_u_cmm_decoder_GND_5513), + .LO(com_cmm_u_cmm_decoder_data_tmp_7[0]), + .S(com_cmm_u_cmm_decoder_N_107_4) + ); + MUXCY_L com_cmm_u_cmm_decoder_un9_bar12_64_hit_high_0_I_19 ( + .CI(com_cmm_u_cmm_decoder_data_tmp_7[8]), + .DI(com_cmm_u_cmm_decoder_GND_5513), + .LO(com_cmm_u_cmm_decoder_data_tmp_8[9]), + .S(com_cmm_u_cmm_decoder_N_91_5) + ); + MUXCY_L com_cmm_u_cmm_decoder_un9_bar12_64_hit_high_0_I_28 ( + .CI(com_cmm_u_cmm_decoder_data_tmp_7[2]), + .DI(com_cmm_u_cmm_decoder_GND_5513), + .LO(com_cmm_u_cmm_decoder_data_tmp_7[3]), + .S(com_cmm_u_cmm_decoder_N_83_5) + ); + MUXCY_L com_cmm_u_cmm_decoder_un9_bar12_64_hit_high_0_I_37 ( + .CI(com_cmm_u_cmm_decoder_data_tmp_7[3]), + .DI(com_cmm_u_cmm_decoder_GND_5513), + .LO(com_cmm_u_cmm_decoder_data_tmp_7[4]), + .S(com_cmm_u_cmm_decoder_N_75_5) + ); + MUXCY_L com_cmm_u_cmm_decoder_un9_bar12_64_hit_high_0_I_46 ( + .CI(com_cmm_u_cmm_decoder_data_tmp_8[9]), + .DI(com_cmm_u_cmm_decoder_GND_5513), + .LO(com_cmm_u_cmm_decoder_data_tmp_7[10]), + .S(com_cmm_u_cmm_decoder_N_67_5) + ); + MUXCY_L com_cmm_u_cmm_decoder_un9_bar12_64_hit_high_0_I_55 ( + .CI(com_cmm_u_cmm_decoder_data_tmp_7[4]), + .DI(com_cmm_u_cmm_decoder_GND_5513), + .LO(com_cmm_u_cmm_decoder_data_tmp_7[5]), + .S(com_cmm_u_cmm_decoder_N_59_5) + ); + MUXCY_L com_cmm_u_cmm_decoder_un9_bar12_64_hit_high_0_I_64 ( + .CI(com_cmm_u_cmm_decoder_data_tmp_7[6]), + .DI(com_cmm_u_cmm_decoder_GND_5513), + .LO(com_cmm_u_cmm_decoder_data_tmp_7[7]), + .S(com_cmm_u_cmm_decoder_N_51_5) + ); + MUXCY_L com_cmm_u_cmm_decoder_un9_bar12_64_hit_high_0_I_73 ( + .CI(com_cmm_u_cmm_decoder_data_tmp_7[7]), + .DI(com_cmm_u_cmm_decoder_GND_5513), + .LO(com_cmm_u_cmm_decoder_data_tmp_7[8]), + .S(com_cmm_u_cmm_decoder_N_43_5) + ); + MUXCY_L com_cmm_u_cmm_decoder_un9_bar12_64_hit_high_0_I_82 ( + .CI(com_cmm_u_cmm_decoder_data_tmp_7[5]), + .DI(com_cmm_u_cmm_decoder_GND_5513), + .LO(com_cmm_u_cmm_decoder_data_tmp_7[6]), + .S(com_cmm_u_cmm_decoder_N_35_5) + ); + MUXCY_L com_cmm_u_cmm_decoder_un9_bar12_64_hit_high_0_I_91 ( + .CI(com_cmm_u_cmm_decoder_data_tmp_7[0]), + .DI(com_cmm_u_cmm_decoder_GND_5513), + .LO(com_cmm_u_cmm_decoder_data_tmp_7[1]), + .S(com_cmm_u_cmm_decoder_N_27_5) + ); + MUXCY_L com_cmm_u_cmm_decoder_un9_bar12_64_hit_high_0_I_100 ( + .CI(com_cmm_u_cmm_decoder_data_tmp_7[10]), + .DI(com_cmm_u_cmm_decoder_GND_5513), + .LO(com_cmm_u_cmm_decoder_data_tmp_7[11]), + .S(com_cmm_u_cmm_decoder_N_19_5) + ); + MUXCY_L com_cmm_u_cmm_decoder_un9_bar12_64_hit_high_0_I_109 ( + .CI(com_cmm_u_cmm_decoder_data_tmp_7[11]), + .DI(com_cmm_u_cmm_decoder_GND_5513), + .LO(com_cmm_u_cmm_decoder_data_tmp_1[12]), + .S(com_cmm_u_cmm_decoder_N_11_6) + ); + MUXCY_L com_cmm_u_cmm_decoder_un9_bar12_64_hit_high_0_I_118 ( + .CI(com_cmm_u_cmm_decoder_data_tmp_7[1]), + .DI(com_cmm_u_cmm_decoder_GND_5513), + .LO(com_cmm_u_cmm_decoder_data_tmp_7[2]), + .S(com_cmm_u_cmm_decoder_N_3_5) + ); + MUXCY_L com_cmm_u_cmm_decoder_un9_bar23_64_hit_high_0_I_1 ( + .CI(com_cmm_u_cmm_decoder_VCC_5484), + .DI(com_cmm_u_cmm_decoder_GND_5513), + .LO(com_cmm_u_cmm_decoder_data_tmp_6[0]), + .S(com_cmm_u_cmm_decoder_N_107_5) + ); + MUXCY_L com_cmm_u_cmm_decoder_un9_bar23_64_hit_high_0_I_19 ( + .CI(com_cmm_u_cmm_decoder_data_tmp_6[8]), + .DI(com_cmm_u_cmm_decoder_GND_5513), + .LO(com_cmm_u_cmm_decoder_data_tmp_7[9]), + .S(com_cmm_u_cmm_decoder_N_91_6) + ); + MUXCY_L com_cmm_u_cmm_decoder_un9_bar23_64_hit_high_0_I_28 ( + .CI(com_cmm_u_cmm_decoder_data_tmp_6[2]), + .DI(com_cmm_u_cmm_decoder_GND_5513), + .LO(com_cmm_u_cmm_decoder_data_tmp_6[3]), + .S(com_cmm_u_cmm_decoder_N_83_6) + ); + MUXCY_L com_cmm_u_cmm_decoder_un9_bar23_64_hit_high_0_I_37 ( + .CI(com_cmm_u_cmm_decoder_data_tmp_6[3]), + .DI(com_cmm_u_cmm_decoder_GND_5513), + .LO(com_cmm_u_cmm_decoder_data_tmp_6[4]), + .S(com_cmm_u_cmm_decoder_N_75_6) + ); + MUXCY_L com_cmm_u_cmm_decoder_un9_bar23_64_hit_high_0_I_46 ( + .CI(com_cmm_u_cmm_decoder_data_tmp_7[9]), + .DI(com_cmm_u_cmm_decoder_GND_5513), + .LO(com_cmm_u_cmm_decoder_data_tmp_6[10]), + .S(com_cmm_u_cmm_decoder_N_67_6) + ); + MUXCY_L com_cmm_u_cmm_decoder_un9_bar23_64_hit_high_0_I_55 ( + .CI(com_cmm_u_cmm_decoder_data_tmp_6[4]), + .DI(com_cmm_u_cmm_decoder_GND_5513), + .LO(com_cmm_u_cmm_decoder_data_tmp_6[5]), + .S(com_cmm_u_cmm_decoder_N_59_6) + ); + MUXCY_L com_cmm_u_cmm_decoder_un9_bar23_64_hit_high_0_I_64 ( + .CI(com_cmm_u_cmm_decoder_data_tmp_6[6]), + .DI(com_cmm_u_cmm_decoder_GND_5513), + .LO(com_cmm_u_cmm_decoder_data_tmp_6[7]), + .S(com_cmm_u_cmm_decoder_N_51_6) + ); + MUXCY_L com_cmm_u_cmm_decoder_un9_bar23_64_hit_high_0_I_73 ( + .CI(com_cmm_u_cmm_decoder_data_tmp_6[7]), + .DI(com_cmm_u_cmm_decoder_GND_5513), + .LO(com_cmm_u_cmm_decoder_data_tmp_6[8]), + .S(com_cmm_u_cmm_decoder_N_43_6) + ); + MUXCY_L com_cmm_u_cmm_decoder_un9_bar23_64_hit_high_0_I_82 ( + .CI(com_cmm_u_cmm_decoder_data_tmp_6[5]), + .DI(com_cmm_u_cmm_decoder_GND_5513), + .LO(com_cmm_u_cmm_decoder_data_tmp_6[6]), + .S(com_cmm_u_cmm_decoder_N_35_6) + ); + MUXCY_L com_cmm_u_cmm_decoder_un9_bar23_64_hit_high_0_I_91 ( + .CI(com_cmm_u_cmm_decoder_data_tmp_6[0]), + .DI(com_cmm_u_cmm_decoder_GND_5513), + .LO(com_cmm_u_cmm_decoder_data_tmp_6[1]), + .S(com_cmm_u_cmm_decoder_N_27_6) + ); + MUXCY_L com_cmm_u_cmm_decoder_un9_bar23_64_hit_high_0_I_100 ( + .CI(com_cmm_u_cmm_decoder_data_tmp_6[10]), + .DI(com_cmm_u_cmm_decoder_GND_5513), + .LO(com_cmm_u_cmm_decoder_data_tmp_6[11]), + .S(com_cmm_u_cmm_decoder_N_19_6) + ); + MUXCY_L com_cmm_u_cmm_decoder_un9_bar23_64_hit_high_0_I_109 ( + .CI(com_cmm_u_cmm_decoder_data_tmp_6[11]), + .DI(com_cmm_u_cmm_decoder_GND_5513), + .LO(com_cmm_u_cmm_decoder_data_tmp_2[12]), + .S(com_cmm_u_cmm_decoder_N_11_7) + ); + MUXCY_L com_cmm_u_cmm_decoder_un9_bar23_64_hit_high_0_I_118 ( + .CI(com_cmm_u_cmm_decoder_data_tmp_6[1]), + .DI(com_cmm_u_cmm_decoder_GND_5513), + .LO(com_cmm_u_cmm_decoder_data_tmp_6[2]), + .S(com_cmm_u_cmm_decoder_N_3_6) + ); + MUXCY_L com_cmm_u_cmm_decoder_un9_bar34_64_hit_high_0_I_1 ( + .CI(com_cmm_u_cmm_decoder_VCC_5484), + .DI(com_cmm_u_cmm_decoder_GND_5513), + .LO(com_cmm_u_cmm_decoder_data_tmp_5[0]), + .S(com_cmm_u_cmm_decoder_N_107_6) + ); + MUXCY_L com_cmm_u_cmm_decoder_un9_bar34_64_hit_high_0_I_19 ( + .CI(com_cmm_u_cmm_decoder_data_tmp_5[8]), + .DI(com_cmm_u_cmm_decoder_GND_5513), + .LO(com_cmm_u_cmm_decoder_data_tmp_6[9]), + .S(com_cmm_u_cmm_decoder_N_91_7) + ); + MUXCY_L com_cmm_u_cmm_decoder_un9_bar34_64_hit_high_0_I_28 ( + .CI(com_cmm_u_cmm_decoder_data_tmp_5[2]), + .DI(com_cmm_u_cmm_decoder_GND_5513), + .LO(com_cmm_u_cmm_decoder_data_tmp_5[3]), + .S(com_cmm_u_cmm_decoder_N_83_7) + ); + MUXCY_L com_cmm_u_cmm_decoder_un9_bar34_64_hit_high_0_I_37 ( + .CI(com_cmm_u_cmm_decoder_data_tmp_5[3]), + .DI(com_cmm_u_cmm_decoder_GND_5513), + .LO(com_cmm_u_cmm_decoder_data_tmp_5[4]), + .S(com_cmm_u_cmm_decoder_N_75_7) + ); + MUXCY_L com_cmm_u_cmm_decoder_un9_bar34_64_hit_high_0_I_46 ( + .CI(com_cmm_u_cmm_decoder_data_tmp_6[9]), + .DI(com_cmm_u_cmm_decoder_GND_5513), + .LO(com_cmm_u_cmm_decoder_data_tmp_5[10]), + .S(com_cmm_u_cmm_decoder_N_67_7) + ); + MUXCY_L com_cmm_u_cmm_decoder_un9_bar34_64_hit_high_0_I_55 ( + .CI(com_cmm_u_cmm_decoder_data_tmp_5[4]), + .DI(com_cmm_u_cmm_decoder_GND_5513), + .LO(com_cmm_u_cmm_decoder_data_tmp_5[5]), + .S(com_cmm_u_cmm_decoder_N_59_7) + ); + MUXCY_L com_cmm_u_cmm_decoder_un9_bar34_64_hit_high_0_I_64 ( + .CI(com_cmm_u_cmm_decoder_data_tmp_5[6]), + .DI(com_cmm_u_cmm_decoder_GND_5513), + .LO(com_cmm_u_cmm_decoder_data_tmp_5[7]), + .S(com_cmm_u_cmm_decoder_N_51_7) + ); + MUXCY_L com_cmm_u_cmm_decoder_un9_bar34_64_hit_high_0_I_73 ( + .CI(com_cmm_u_cmm_decoder_data_tmp_5[7]), + .DI(com_cmm_u_cmm_decoder_GND_5513), + .LO(com_cmm_u_cmm_decoder_data_tmp_5[8]), + .S(com_cmm_u_cmm_decoder_N_43_7) + ); + MUXCY_L com_cmm_u_cmm_decoder_un9_bar34_64_hit_high_0_I_82 ( + .CI(com_cmm_u_cmm_decoder_data_tmp_5[5]), + .DI(com_cmm_u_cmm_decoder_GND_5513), + .LO(com_cmm_u_cmm_decoder_data_tmp_5[6]), + .S(com_cmm_u_cmm_decoder_N_35_7) + ); + MUXCY_L com_cmm_u_cmm_decoder_un9_bar34_64_hit_high_0_I_91 ( + .CI(com_cmm_u_cmm_decoder_data_tmp_5[0]), + .DI(com_cmm_u_cmm_decoder_GND_5513), + .LO(com_cmm_u_cmm_decoder_data_tmp_5[1]), + .S(com_cmm_u_cmm_decoder_N_27_7) + ); + MUXCY_L com_cmm_u_cmm_decoder_un9_bar34_64_hit_high_0_I_100 ( + .CI(com_cmm_u_cmm_decoder_data_tmp_5[10]), + .DI(com_cmm_u_cmm_decoder_GND_5513), + .LO(com_cmm_u_cmm_decoder_data_tmp_5[11]), + .S(com_cmm_u_cmm_decoder_N_19_7) + ); + MUXCY_L com_cmm_u_cmm_decoder_un9_bar34_64_hit_high_0_I_109 ( + .CI(com_cmm_u_cmm_decoder_data_tmp_5[11]), + .DI(com_cmm_u_cmm_decoder_GND_5513), + .LO(com_cmm_u_cmm_decoder_data_tmp_3[12]), + .S(com_cmm_u_cmm_decoder_N_11_8) + ); + MUXCY_L com_cmm_u_cmm_decoder_un9_bar34_64_hit_high_0_I_118 ( + .CI(com_cmm_u_cmm_decoder_data_tmp_5[1]), + .DI(com_cmm_u_cmm_decoder_GND_5513), + .LO(com_cmm_u_cmm_decoder_data_tmp_5[2]), + .S(com_cmm_u_cmm_decoder_N_3_7) + ); + MUXCY_L com_cmm_u_cmm_decoder_un9_bar45_64_hit_high_0_I_1 ( + .CI(com_cmm_u_cmm_decoder_VCC_5484), + .DI(com_cmm_u_cmm_decoder_GND_5513), + .LO(com_cmm_u_cmm_decoder_data_tmp_4[0]), + .S(com_cmm_u_cmm_decoder_N_107_7) + ); + MUXCY_L com_cmm_u_cmm_decoder_un9_bar45_64_hit_high_0_I_19 ( + .CI(com_cmm_u_cmm_decoder_data_tmp_4[8]), + .DI(com_cmm_u_cmm_decoder_GND_5513), + .LO(com_cmm_u_cmm_decoder_data_tmp_5[9]), + .S(com_cmm_u_cmm_decoder_N_91_8) + ); + MUXCY_L com_cmm_u_cmm_decoder_un9_bar45_64_hit_high_0_I_28 ( + .CI(com_cmm_u_cmm_decoder_data_tmp_4[2]), + .DI(com_cmm_u_cmm_decoder_GND_5513), + .LO(com_cmm_u_cmm_decoder_data_tmp_4[3]), + .S(com_cmm_u_cmm_decoder_N_83_8) + ); + MUXCY_L com_cmm_u_cmm_decoder_un9_bar45_64_hit_high_0_I_37 ( + .CI(com_cmm_u_cmm_decoder_data_tmp_4[3]), + .DI(com_cmm_u_cmm_decoder_GND_5513), + .LO(com_cmm_u_cmm_decoder_data_tmp_4[4]), + .S(com_cmm_u_cmm_decoder_N_75_8) + ); + MUXCY_L com_cmm_u_cmm_decoder_un9_bar45_64_hit_high_0_I_46 ( + .CI(com_cmm_u_cmm_decoder_data_tmp_5[9]), + .DI(com_cmm_u_cmm_decoder_GND_5513), + .LO(com_cmm_u_cmm_decoder_data_tmp_4[10]), + .S(com_cmm_u_cmm_decoder_N_67_8) + ); + MUXCY_L com_cmm_u_cmm_decoder_un9_bar45_64_hit_high_0_I_55 ( + .CI(com_cmm_u_cmm_decoder_data_tmp_4[4]), + .DI(com_cmm_u_cmm_decoder_GND_5513), + .LO(com_cmm_u_cmm_decoder_data_tmp_4[5]), + .S(com_cmm_u_cmm_decoder_N_59_8) + ); + MUXCY_L com_cmm_u_cmm_decoder_un9_bar45_64_hit_high_0_I_64 ( + .CI(com_cmm_u_cmm_decoder_data_tmp_4[6]), + .DI(com_cmm_u_cmm_decoder_GND_5513), + .LO(com_cmm_u_cmm_decoder_data_tmp_4[7]), + .S(com_cmm_u_cmm_decoder_N_51_8) + ); + MUXCY_L com_cmm_u_cmm_decoder_un9_bar45_64_hit_high_0_I_73 ( + .CI(com_cmm_u_cmm_decoder_data_tmp_4[7]), + .DI(com_cmm_u_cmm_decoder_GND_5513), + .LO(com_cmm_u_cmm_decoder_data_tmp_4[8]), + .S(com_cmm_u_cmm_decoder_N_43_8) + ); + MUXCY_L com_cmm_u_cmm_decoder_un9_bar45_64_hit_high_0_I_82 ( + .CI(com_cmm_u_cmm_decoder_data_tmp_4[5]), + .DI(com_cmm_u_cmm_decoder_GND_5513), + .LO(com_cmm_u_cmm_decoder_data_tmp_4[6]), + .S(com_cmm_u_cmm_decoder_N_35_8) + ); + MUXCY_L com_cmm_u_cmm_decoder_un9_bar45_64_hit_high_0_I_91 ( + .CI(com_cmm_u_cmm_decoder_data_tmp_4[0]), + .DI(com_cmm_u_cmm_decoder_GND_5513), + .LO(com_cmm_u_cmm_decoder_data_tmp_4[1]), + .S(com_cmm_u_cmm_decoder_N_27_8) + ); + MUXCY_L com_cmm_u_cmm_decoder_un9_bar45_64_hit_high_0_I_100 ( + .CI(com_cmm_u_cmm_decoder_data_tmp_4[10]), + .DI(com_cmm_u_cmm_decoder_GND_5513), + .LO(com_cmm_u_cmm_decoder_data_tmp_4[11]), + .S(com_cmm_u_cmm_decoder_N_19_8) + ); + MUXCY_L com_cmm_u_cmm_decoder_un9_bar45_64_hit_high_0_I_109 ( + .CI(com_cmm_u_cmm_decoder_data_tmp_4[11]), + .DI(com_cmm_u_cmm_decoder_GND_5513), + .LO(com_cmm_u_cmm_decoder_data_tmp_4[12]), + .S(com_cmm_u_cmm_decoder_N_11_9) + ); + MUXCY_L com_cmm_u_cmm_decoder_un9_bar45_64_hit_high_0_I_118 ( + .CI(com_cmm_u_cmm_decoder_data_tmp_4[1]), + .DI(com_cmm_u_cmm_decoder_GND_5513), + .LO(com_cmm_u_cmm_decoder_data_tmp_4[2]), + .S(com_cmm_u_cmm_decoder_N_3_8) + ); + MUXCY_L com_cmm_u_cmm_decoder_bar0_eq_raddr_3_0_I_1 ( + .CI(com_cmm_u_cmm_decoder_VCC_5484), + .DI(com_cmm_u_cmm_decoder_GND_5513), + .LO(com_cmm_u_cmm_decoder_data_tmp_3[0]), + .S(com_cmm_u_cmm_decoder_N_107_8) + ); + MUXCY_L com_cmm_u_cmm_decoder_bar0_eq_raddr_3_0_I_19 ( + .CI(com_cmm_u_cmm_decoder_data_tmp_3[8]), + .DI(com_cmm_u_cmm_decoder_GND_5513), + .LO(com_cmm_u_cmm_decoder_data_tmp_4[9]), + .S(com_cmm_u_cmm_decoder_N_91_9) + ); + MUXCY_L com_cmm_u_cmm_decoder_bar0_eq_raddr_3_0_I_28 ( + .CI(com_cmm_u_cmm_decoder_data_tmp_3[2]), + .DI(com_cmm_u_cmm_decoder_GND_5513), + .LO(com_cmm_u_cmm_decoder_data_tmp_3[3]), + .S(com_cmm_u_cmm_decoder_N_83_9) + ); + MUXCY_L com_cmm_u_cmm_decoder_bar0_eq_raddr_3_0_I_37 ( + .CI(com_cmm_u_cmm_decoder_data_tmp_3[3]), + .DI(com_cmm_u_cmm_decoder_GND_5513), + .LO(com_cmm_u_cmm_decoder_data_tmp_3[4]), + .S(com_cmm_u_cmm_decoder_N_75_9) + ); + MUXCY_L com_cmm_u_cmm_decoder_bar0_eq_raddr_3_0_I_46 ( + .CI(com_cmm_u_cmm_decoder_data_tmp_4[9]), + .DI(com_cmm_u_cmm_decoder_GND_5513), + .LO(com_cmm_u_cmm_decoder_data_tmp_3[10]), + .S(com_cmm_u_cmm_decoder_N_67_9) + ); + MUXCY_L com_cmm_u_cmm_decoder_bar0_eq_raddr_3_0_I_55 ( + .CI(com_cmm_u_cmm_decoder_data_tmp_3[4]), + .DI(com_cmm_u_cmm_decoder_GND_5513), + .LO(com_cmm_u_cmm_decoder_data_tmp_3[5]), + .S(com_cmm_u_cmm_decoder_N_59_9) + ); + MUXCY_L com_cmm_u_cmm_decoder_bar0_eq_raddr_3_0_I_64 ( + .CI(com_cmm_u_cmm_decoder_data_tmp_3[6]), + .DI(com_cmm_u_cmm_decoder_GND_5513), + .LO(com_cmm_u_cmm_decoder_data_tmp_3[7]), + .S(com_cmm_u_cmm_decoder_N_51_9) + ); + MUXCY_L com_cmm_u_cmm_decoder_bar0_eq_raddr_3_0_I_73 ( + .CI(com_cmm_u_cmm_decoder_data_tmp_3[7]), + .DI(com_cmm_u_cmm_decoder_GND_5513), + .LO(com_cmm_u_cmm_decoder_data_tmp_3[8]), + .S(com_cmm_u_cmm_decoder_N_43_9) + ); + MUXCY_L com_cmm_u_cmm_decoder_bar0_eq_raddr_3_0_I_82 ( + .CI(com_cmm_u_cmm_decoder_data_tmp_3[5]), + .DI(com_cmm_u_cmm_decoder_GND_5513), + .LO(com_cmm_u_cmm_decoder_data_tmp_3[6]), + .S(com_cmm_u_cmm_decoder_N_35_9) + ); + MUXCY_L com_cmm_u_cmm_decoder_bar0_eq_raddr_3_0_I_91 ( + .CI(com_cmm_u_cmm_decoder_data_tmp_3[0]), + .DI(com_cmm_u_cmm_decoder_GND_5513), + .LO(com_cmm_u_cmm_decoder_data_tmp_3[1]), + .S(com_cmm_u_cmm_decoder_N_27_9) + ); + MUXCY_L com_cmm_u_cmm_decoder_bar0_eq_raddr_3_0_I_100 ( + .CI(com_cmm_u_cmm_decoder_data_tmp_3[10]), + .DI(com_cmm_u_cmm_decoder_GND_5513), + .LO(com_cmm_u_cmm_decoder_data_tmp_3[11]), + .S(com_cmm_u_cmm_decoder_N_19_9) + ); + MUXCY_L com_cmm_u_cmm_decoder_bar0_eq_raddr_3_0_I_109 ( + .CI(com_cmm_u_cmm_decoder_data_tmp_3[11]), + .DI(com_cmm_u_cmm_decoder_GND_5513), + .LO(com_cmm_u_cmm_decoder_data_tmp_5[12]), + .S(com_cmm_u_cmm_decoder_N_11_10) + ); + MUXCY_L com_cmm_u_cmm_decoder_bar0_eq_raddr_3_0_I_118 ( + .CI(com_cmm_u_cmm_decoder_data_tmp_3[1]), + .DI(com_cmm_u_cmm_decoder_GND_5513), + .LO(com_cmm_u_cmm_decoder_data_tmp_3[2]), + .S(com_cmm_u_cmm_decoder_N_3_9) + ); + MUXCY_L com_cmm_u_cmm_decoder_bar1_eq_raddr_3_0_I_1 ( + .CI(com_cmm_u_cmm_decoder_VCC_5484), + .DI(com_cmm_u_cmm_decoder_GND_5513), + .LO(com_cmm_u_cmm_decoder_data_tmp_2[0]), + .S(com_cmm_u_cmm_decoder_N_107_9) + ); + MUXCY_L com_cmm_u_cmm_decoder_bar1_eq_raddr_3_0_I_19 ( + .CI(com_cmm_u_cmm_decoder_data_tmp_2[8]), + .DI(com_cmm_u_cmm_decoder_GND_5513), + .LO(com_cmm_u_cmm_decoder_data_tmp_3[9]), + .S(com_cmm_u_cmm_decoder_N_91_10) + ); + MUXCY_L com_cmm_u_cmm_decoder_bar1_eq_raddr_3_0_I_28 ( + .CI(com_cmm_u_cmm_decoder_data_tmp_2[2]), + .DI(com_cmm_u_cmm_decoder_GND_5513), + .LO(com_cmm_u_cmm_decoder_data_tmp_2[3]), + .S(com_cmm_u_cmm_decoder_N_83_10) + ); + MUXCY_L com_cmm_u_cmm_decoder_bar1_eq_raddr_3_0_I_37 ( + .CI(com_cmm_u_cmm_decoder_data_tmp_2[3]), + .DI(com_cmm_u_cmm_decoder_GND_5513), + .LO(com_cmm_u_cmm_decoder_data_tmp_2[4]), + .S(com_cmm_u_cmm_decoder_N_75_10) + ); + MUXCY_L com_cmm_u_cmm_decoder_bar1_eq_raddr_3_0_I_46 ( + .CI(com_cmm_u_cmm_decoder_data_tmp_3[9]), + .DI(com_cmm_u_cmm_decoder_GND_5513), + .LO(com_cmm_u_cmm_decoder_data_tmp_2[10]), + .S(com_cmm_u_cmm_decoder_N_67_10) + ); + MUXCY_L com_cmm_u_cmm_decoder_bar1_eq_raddr_3_0_I_55 ( + .CI(com_cmm_u_cmm_decoder_data_tmp_2[4]), + .DI(com_cmm_u_cmm_decoder_GND_5513), + .LO(com_cmm_u_cmm_decoder_data_tmp_2[5]), + .S(com_cmm_u_cmm_decoder_N_59_10) + ); + MUXCY_L com_cmm_u_cmm_decoder_bar1_eq_raddr_3_0_I_64 ( + .CI(com_cmm_u_cmm_decoder_data_tmp_2[6]), + .DI(com_cmm_u_cmm_decoder_GND_5513), + .LO(com_cmm_u_cmm_decoder_data_tmp_2[7]), + .S(com_cmm_u_cmm_decoder_N_51_10) + ); + MUXCY_L com_cmm_u_cmm_decoder_bar1_eq_raddr_3_0_I_73 ( + .CI(com_cmm_u_cmm_decoder_data_tmp_2[7]), + .DI(com_cmm_u_cmm_decoder_GND_5513), + .LO(com_cmm_u_cmm_decoder_data_tmp_2[8]), + .S(com_cmm_u_cmm_decoder_N_43_10) + ); + MUXCY_L com_cmm_u_cmm_decoder_bar1_eq_raddr_3_0_I_82 ( + .CI(com_cmm_u_cmm_decoder_data_tmp_2[5]), + .DI(com_cmm_u_cmm_decoder_GND_5513), + .LO(com_cmm_u_cmm_decoder_data_tmp_2[6]), + .S(com_cmm_u_cmm_decoder_N_35_10) + ); + MUXCY_L com_cmm_u_cmm_decoder_bar1_eq_raddr_3_0_I_91 ( + .CI(com_cmm_u_cmm_decoder_data_tmp_2[0]), + .DI(com_cmm_u_cmm_decoder_GND_5513), + .LO(com_cmm_u_cmm_decoder_data_tmp_2[1]), + .S(com_cmm_u_cmm_decoder_N_27_10) + ); + MUXCY_L com_cmm_u_cmm_decoder_bar1_eq_raddr_3_0_I_100 ( + .CI(com_cmm_u_cmm_decoder_data_tmp_2[10]), + .DI(com_cmm_u_cmm_decoder_GND_5513), + .LO(com_cmm_u_cmm_decoder_data_tmp_2[11]), + .S(com_cmm_u_cmm_decoder_N_19_10) + ); + MUXCY_L com_cmm_u_cmm_decoder_bar1_eq_raddr_3_0_I_109 ( + .CI(com_cmm_u_cmm_decoder_data_tmp_2[11]), + .DI(com_cmm_u_cmm_decoder_GND_5513), + .LO(com_cmm_u_cmm_decoder_data_tmp_6[12]), + .S(com_cmm_u_cmm_decoder_N_11_11) + ); + MUXCY_L com_cmm_u_cmm_decoder_bar1_eq_raddr_3_0_I_118 ( + .CI(com_cmm_u_cmm_decoder_data_tmp_2[1]), + .DI(com_cmm_u_cmm_decoder_GND_5513), + .LO(com_cmm_u_cmm_decoder_data_tmp_2[2]), + .S(com_cmm_u_cmm_decoder_N_3_10) + ); + MUXCY_L com_cmm_u_cmm_decoder_bar2_eq_raddr_3_0_I_1 ( + .CI(com_cmm_u_cmm_decoder_VCC_5484), + .DI(com_cmm_u_cmm_decoder_GND_5513), + .LO(com_cmm_u_cmm_decoder_data_tmp_1[0]), + .S(com_cmm_u_cmm_decoder_N_107_10) + ); + MUXCY_L com_cmm_u_cmm_decoder_bar2_eq_raddr_3_0_I_19 ( + .CI(com_cmm_u_cmm_decoder_data_tmp_1[8]), + .DI(com_cmm_u_cmm_decoder_GND_5513), + .LO(com_cmm_u_cmm_decoder_data_tmp_2[9]), + .S(com_cmm_u_cmm_decoder_N_91_11) + ); + MUXCY_L com_cmm_u_cmm_decoder_bar2_eq_raddr_3_0_I_28 ( + .CI(com_cmm_u_cmm_decoder_data_tmp_1[2]), + .DI(com_cmm_u_cmm_decoder_GND_5513), + .LO(com_cmm_u_cmm_decoder_data_tmp_1[3]), + .S(com_cmm_u_cmm_decoder_N_83_11) + ); + MUXCY_L com_cmm_u_cmm_decoder_bar2_eq_raddr_3_0_I_37 ( + .CI(com_cmm_u_cmm_decoder_data_tmp_1[3]), + .DI(com_cmm_u_cmm_decoder_GND_5513), + .LO(com_cmm_u_cmm_decoder_data_tmp_1[4]), + .S(com_cmm_u_cmm_decoder_N_75_11) + ); + MUXCY_L com_cmm_u_cmm_decoder_bar2_eq_raddr_3_0_I_46 ( + .CI(com_cmm_u_cmm_decoder_data_tmp_2[9]), + .DI(com_cmm_u_cmm_decoder_GND_5513), + .LO(com_cmm_u_cmm_decoder_data_tmp_1[10]), + .S(com_cmm_u_cmm_decoder_N_67_11) + ); + MUXCY_L com_cmm_u_cmm_decoder_bar2_eq_raddr_3_0_I_55 ( + .CI(com_cmm_u_cmm_decoder_data_tmp_1[4]), + .DI(com_cmm_u_cmm_decoder_GND_5513), + .LO(com_cmm_u_cmm_decoder_data_tmp_1[5]), + .S(com_cmm_u_cmm_decoder_N_59_11) + ); + MUXCY_L com_cmm_u_cmm_decoder_bar2_eq_raddr_3_0_I_64 ( + .CI(com_cmm_u_cmm_decoder_data_tmp_1[6]), + .DI(com_cmm_u_cmm_decoder_GND_5513), + .LO(com_cmm_u_cmm_decoder_data_tmp_1[7]), + .S(com_cmm_u_cmm_decoder_N_51_11) + ); + MUXCY_L com_cmm_u_cmm_decoder_bar2_eq_raddr_3_0_I_73 ( + .CI(com_cmm_u_cmm_decoder_data_tmp_1[7]), + .DI(com_cmm_u_cmm_decoder_GND_5513), + .LO(com_cmm_u_cmm_decoder_data_tmp_1[8]), + .S(com_cmm_u_cmm_decoder_N_43_11) + ); + MUXCY_L com_cmm_u_cmm_decoder_bar2_eq_raddr_3_0_I_82 ( + .CI(com_cmm_u_cmm_decoder_data_tmp_1[5]), + .DI(com_cmm_u_cmm_decoder_GND_5513), + .LO(com_cmm_u_cmm_decoder_data_tmp_1[6]), + .S(com_cmm_u_cmm_decoder_N_35_11) + ); + MUXCY_L com_cmm_u_cmm_decoder_bar2_eq_raddr_3_0_I_91 ( + .CI(com_cmm_u_cmm_decoder_data_tmp_1[0]), + .DI(com_cmm_u_cmm_decoder_GND_5513), + .LO(com_cmm_u_cmm_decoder_data_tmp_1[1]), + .S(com_cmm_u_cmm_decoder_N_27_11) + ); + MUXCY_L com_cmm_u_cmm_decoder_bar2_eq_raddr_3_0_I_100 ( + .CI(com_cmm_u_cmm_decoder_data_tmp_1[10]), + .DI(com_cmm_u_cmm_decoder_GND_5513), + .LO(com_cmm_u_cmm_decoder_data_tmp_1[11]), + .S(com_cmm_u_cmm_decoder_N_19_11) + ); + MUXCY_L com_cmm_u_cmm_decoder_bar2_eq_raddr_3_0_I_109 ( + .CI(com_cmm_u_cmm_decoder_data_tmp_1[11]), + .DI(com_cmm_u_cmm_decoder_GND_5513), + .LO(com_cmm_u_cmm_decoder_data_tmp_7[12]), + .S(com_cmm_u_cmm_decoder_N_11_12) + ); + MUXCY_L com_cmm_u_cmm_decoder_bar2_eq_raddr_3_0_I_118 ( + .CI(com_cmm_u_cmm_decoder_data_tmp_1[1]), + .DI(com_cmm_u_cmm_decoder_GND_5513), + .LO(com_cmm_u_cmm_decoder_data_tmp_1[2]), + .S(com_cmm_u_cmm_decoder_N_3_11) + ); + MUXCY_L com_cmm_u_cmm_decoder_bar3_eq_raddr_3_0_I_1 ( + .CI(com_cmm_u_cmm_decoder_VCC_5484), + .DI(com_cmm_u_cmm_decoder_GND_5513), + .LO(com_cmm_u_cmm_decoder_data_tmp_0[0]), + .S(com_cmm_u_cmm_decoder_N_107_11) + ); + MUXCY_L com_cmm_u_cmm_decoder_bar3_eq_raddr_3_0_I_19 ( + .CI(com_cmm_u_cmm_decoder_data_tmp_0[8]), + .DI(com_cmm_u_cmm_decoder_GND_5513), + .LO(com_cmm_u_cmm_decoder_data_tmp_1[9]), + .S(com_cmm_u_cmm_decoder_N_91_12) + ); + MUXCY_L com_cmm_u_cmm_decoder_bar3_eq_raddr_3_0_I_28 ( + .CI(com_cmm_u_cmm_decoder_data_tmp_0[2]), + .DI(com_cmm_u_cmm_decoder_GND_5513), + .LO(com_cmm_u_cmm_decoder_data_tmp_0[3]), + .S(com_cmm_u_cmm_decoder_N_83_12) + ); + MUXCY_L com_cmm_u_cmm_decoder_bar3_eq_raddr_3_0_I_37 ( + .CI(com_cmm_u_cmm_decoder_data_tmp_0[3]), + .DI(com_cmm_u_cmm_decoder_GND_5513), + .LO(com_cmm_u_cmm_decoder_data_tmp_0[4]), + .S(com_cmm_u_cmm_decoder_N_75_12) + ); + MUXCY_L com_cmm_u_cmm_decoder_bar3_eq_raddr_3_0_I_46 ( + .CI(com_cmm_u_cmm_decoder_data_tmp_1[9]), + .DI(com_cmm_u_cmm_decoder_GND_5513), + .LO(com_cmm_u_cmm_decoder_data_tmp_0[10]), + .S(com_cmm_u_cmm_decoder_N_67_12) + ); + MUXCY_L com_cmm_u_cmm_decoder_bar3_eq_raddr_3_0_I_55 ( + .CI(com_cmm_u_cmm_decoder_data_tmp_0[4]), + .DI(com_cmm_u_cmm_decoder_GND_5513), + .LO(com_cmm_u_cmm_decoder_data_tmp_0[5]), + .S(com_cmm_u_cmm_decoder_N_59_12) + ); + MUXCY_L com_cmm_u_cmm_decoder_bar3_eq_raddr_3_0_I_64 ( + .CI(com_cmm_u_cmm_decoder_data_tmp_0[6]), + .DI(com_cmm_u_cmm_decoder_GND_5513), + .LO(com_cmm_u_cmm_decoder_data_tmp_0[7]), + .S(com_cmm_u_cmm_decoder_N_51_12) + ); + MUXCY_L com_cmm_u_cmm_decoder_bar3_eq_raddr_3_0_I_73 ( + .CI(com_cmm_u_cmm_decoder_data_tmp_0[7]), + .DI(com_cmm_u_cmm_decoder_GND_5513), + .LO(com_cmm_u_cmm_decoder_data_tmp_0[8]), + .S(com_cmm_u_cmm_decoder_N_43_12) + ); + MUXCY_L com_cmm_u_cmm_decoder_bar3_eq_raddr_3_0_I_82 ( + .CI(com_cmm_u_cmm_decoder_data_tmp_0[5]), + .DI(com_cmm_u_cmm_decoder_GND_5513), + .LO(com_cmm_u_cmm_decoder_data_tmp_0[6]), + .S(com_cmm_u_cmm_decoder_N_35_12) + ); + MUXCY_L com_cmm_u_cmm_decoder_bar3_eq_raddr_3_0_I_91 ( + .CI(com_cmm_u_cmm_decoder_data_tmp_0[0]), + .DI(com_cmm_u_cmm_decoder_GND_5513), + .LO(com_cmm_u_cmm_decoder_data_tmp_0[1]), + .S(com_cmm_u_cmm_decoder_N_27_12) + ); + MUXCY_L com_cmm_u_cmm_decoder_bar3_eq_raddr_3_0_I_100 ( + .CI(com_cmm_u_cmm_decoder_data_tmp_0[10]), + .DI(com_cmm_u_cmm_decoder_GND_5513), + .LO(com_cmm_u_cmm_decoder_data_tmp_0[11]), + .S(com_cmm_u_cmm_decoder_N_19_12) + ); + MUXCY_L com_cmm_u_cmm_decoder_bar3_eq_raddr_3_0_I_109 ( + .CI(com_cmm_u_cmm_decoder_data_tmp_0[11]), + .DI(com_cmm_u_cmm_decoder_GND_5513), + .LO(com_cmm_u_cmm_decoder_data_tmp_8[12]), + .S(com_cmm_u_cmm_decoder_N_11_13) + ); + MUXCY_L com_cmm_u_cmm_decoder_bar3_eq_raddr_3_0_I_118 ( + .CI(com_cmm_u_cmm_decoder_data_tmp_0[1]), + .DI(com_cmm_u_cmm_decoder_GND_5513), + .LO(com_cmm_u_cmm_decoder_data_tmp_0[2]), + .S(com_cmm_u_cmm_decoder_N_3_12) + ); + MUXCY_L com_cmm_u_cmm_decoder_bar4_eq_raddr_3_0_I_1 ( + .CI(com_cmm_u_cmm_decoder_VCC_5484), + .DI(com_cmm_u_cmm_decoder_GND_5513), + .LO(com_cmm_u_cmm_decoder_data_tmp[0]), + .S(com_cmm_u_cmm_decoder_N_107_12) + ); + MUXCY_L com_cmm_u_cmm_decoder_bar4_eq_raddr_3_0_I_19 ( + .CI(com_cmm_u_cmm_decoder_data_tmp[8]), + .DI(com_cmm_u_cmm_decoder_GND_5513), + .LO(com_cmm_u_cmm_decoder_data_tmp_0[9]), + .S(com_cmm_u_cmm_decoder_N_91_13) + ); + MUXCY_L com_cmm_u_cmm_decoder_bar4_eq_raddr_3_0_I_28 ( + .CI(com_cmm_u_cmm_decoder_data_tmp[2]), + .DI(com_cmm_u_cmm_decoder_GND_5513), + .LO(com_cmm_u_cmm_decoder_data_tmp[3]), + .S(com_cmm_u_cmm_decoder_N_83_13) + ); + MUXCY_L com_cmm_u_cmm_decoder_bar4_eq_raddr_3_0_I_37 ( + .CI(com_cmm_u_cmm_decoder_data_tmp[3]), + .DI(com_cmm_u_cmm_decoder_GND_5513), + .LO(com_cmm_u_cmm_decoder_data_tmp[4]), + .S(com_cmm_u_cmm_decoder_N_75_13) + ); + MUXCY_L com_cmm_u_cmm_decoder_bar4_eq_raddr_3_0_I_46 ( + .CI(com_cmm_u_cmm_decoder_data_tmp_0[9]), + .DI(com_cmm_u_cmm_decoder_GND_5513), + .LO(com_cmm_u_cmm_decoder_data_tmp[10]), + .S(com_cmm_u_cmm_decoder_N_67_13) + ); + MUXCY_L com_cmm_u_cmm_decoder_bar4_eq_raddr_3_0_I_55 ( + .CI(com_cmm_u_cmm_decoder_data_tmp[4]), + .DI(com_cmm_u_cmm_decoder_GND_5513), + .LO(com_cmm_u_cmm_decoder_data_tmp[5]), + .S(com_cmm_u_cmm_decoder_N_59_13) + ); + MUXCY_L com_cmm_u_cmm_decoder_bar4_eq_raddr_3_0_I_64 ( + .CI(com_cmm_u_cmm_decoder_data_tmp[6]), + .DI(com_cmm_u_cmm_decoder_GND_5513), + .LO(com_cmm_u_cmm_decoder_data_tmp[7]), + .S(com_cmm_u_cmm_decoder_N_51_13) + ); + MUXCY_L com_cmm_u_cmm_decoder_bar4_eq_raddr_3_0_I_73 ( + .CI(com_cmm_u_cmm_decoder_data_tmp[7]), + .DI(com_cmm_u_cmm_decoder_GND_5513), + .LO(com_cmm_u_cmm_decoder_data_tmp[8]), + .S(com_cmm_u_cmm_decoder_N_43_13) + ); + MUXCY_L com_cmm_u_cmm_decoder_bar4_eq_raddr_3_0_I_82 ( + .CI(com_cmm_u_cmm_decoder_data_tmp[5]), + .DI(com_cmm_u_cmm_decoder_GND_5513), + .LO(com_cmm_u_cmm_decoder_data_tmp[6]), + .S(com_cmm_u_cmm_decoder_N_35_13) + ); + MUXCY_L com_cmm_u_cmm_decoder_bar4_eq_raddr_3_0_I_91 ( + .CI(com_cmm_u_cmm_decoder_data_tmp[0]), + .DI(com_cmm_u_cmm_decoder_GND_5513), + .LO(com_cmm_u_cmm_decoder_data_tmp[1]), + .S(com_cmm_u_cmm_decoder_N_27_13) + ); + MUXCY_L com_cmm_u_cmm_decoder_bar4_eq_raddr_3_0_I_100 ( + .CI(com_cmm_u_cmm_decoder_data_tmp[10]), + .DI(com_cmm_u_cmm_decoder_GND_5513), + .LO(com_cmm_u_cmm_decoder_data_tmp[11]), + .S(com_cmm_u_cmm_decoder_N_19_13) + ); + MUXCY_L com_cmm_u_cmm_decoder_bar4_eq_raddr_3_0_I_109 ( + .CI(com_cmm_u_cmm_decoder_data_tmp[11]), + .DI(com_cmm_u_cmm_decoder_GND_5513), + .LO(com_cmm_u_cmm_decoder_data_tmp_9[12]), + .S(com_cmm_u_cmm_decoder_N_11_14) + ); + MUXCY_L com_cmm_u_cmm_decoder_bar4_eq_raddr_3_0_I_118 ( + .CI(com_cmm_u_cmm_decoder_data_tmp[1]), + .DI(com_cmm_u_cmm_decoder_GND_5513), + .LO(com_cmm_u_cmm_decoder_data_tmp[2]), + .S(com_cmm_u_cmm_decoder_N_3_13) + ); + MUXCY_L com_cmm_u_cmm_decoder_un11_bar34_64_hit_low_0 ( + .CI(com_cmm_u_cmm_decoder_VCC_5484), + .DI(com_cmm_u_cmm_decoder_GND_5513), + .LO(com_cmm_u_cmm_decoder_un11_bar34_64_hit_low_0_5399), + .S(com_cmm_u_cmm_decoder_un11_bar4_32_hit_nc_0_and) + ); + MUXCY_L com_cmm_u_cmm_decoder_un11_bar34_64_hit_low_1 ( + .CI(com_cmm_u_cmm_decoder_un11_bar34_64_hit_low_0_5399), + .DI(com_cmm_u_cmm_decoder_GND_5513), + .LO(com_cmm_u_cmm_decoder_un11_bar34_64_hit_low_1_5400), + .S(com_cmm_u_cmm_decoder_un11_bar4_32_hit_nc_1_and) + ); + MUXCY_L com_cmm_u_cmm_decoder_un11_bar34_64_hit_low_2 ( + .CI(com_cmm_u_cmm_decoder_un11_bar34_64_hit_low_1_5400), + .DI(com_cmm_u_cmm_decoder_GND_5513), + .LO(com_cmm_u_cmm_decoder_un11_bar34_64_hit_low_2_5401), + .S(com_cmm_u_cmm_decoder_un11_bar4_32_hit_nc_2_and) + ); + MUXCY_L com_cmm_u_cmm_decoder_un11_bar34_64_hit_low_3 ( + .CI(com_cmm_u_cmm_decoder_un11_bar34_64_hit_low_2_5401), + .DI(com_cmm_u_cmm_decoder_GND_5513), + .LO(com_cmm_u_cmm_decoder_un11_bar34_64_hit_low_3_5402), + .S(com_cmm_u_cmm_decoder_un11_bar4_32_hit_nc_3_and) + ); + MUXCY_L com_cmm_u_cmm_decoder_un11_bar34_64_hit_low_4 ( + .CI(com_cmm_u_cmm_decoder_un11_bar34_64_hit_low_3_5402), + .DI(com_cmm_u_cmm_decoder_GND_5513), + .LO(com_cmm_u_cmm_decoder_un11_bar34_64_hit_low_4_5403), + .S(com_cmm_u_cmm_decoder_un11_bar4_32_hit_nc_4_and) + ); + MUXCY_L com_cmm_u_cmm_decoder_un11_bar34_64_hit_low_5 ( + .CI(com_cmm_u_cmm_decoder_un11_bar34_64_hit_low_4_5403), + .DI(com_cmm_u_cmm_decoder_GND_5513), + .LO(com_cmm_u_cmm_decoder_un11_bar34_64_hit_low_5_5404), + .S(com_cmm_u_cmm_decoder_un11_bar4_32_hit_nc_5_and) + ); + MUXCY_L com_cmm_u_cmm_decoder_un11_bar34_64_hit_low_6 ( + .CI(com_cmm_u_cmm_decoder_un11_bar34_64_hit_low_5_5404), + .DI(com_cmm_u_cmm_decoder_GND_5513), + .LO(com_cmm_u_cmm_decoder_un11_bar34_64_hit_low_6_5405), + .S(com_cmm_u_cmm_decoder_un11_bar4_32_hit_nc_6_and) + ); + MUXCY com_cmm_u_cmm_decoder_un11_bar34_64_hit_low_7 ( + .CI(com_cmm_u_cmm_decoder_un11_bar34_64_hit_low_6_5405), + .DI(com_cmm_u_cmm_decoder_GND_5513), + .O(com_cmm_u_cmm_decoder_un11_bar34_64_hit_low_7_5499), + .S(com_cmm_u_cmm_decoder_un11_bar4_32_hit_nc_7_and) + ); + MUXCY_L com_cmm_u_cmm_decoder_un11_bar5_32_hit_nc_0 ( + .CI(com_cmm_u_cmm_decoder_VCC_5484), + .DI(com_cmm_u_cmm_decoder_GND_5513), + .LO(com_cmm_u_cmm_decoder_un11_bar5_32_hit_nc_0_5406), + .S(com_cmm_u_cmm_decoder_un11_bar5_32_hit_nc_0_and) + ); + MUXCY_L com_cmm_u_cmm_decoder_un11_bar5_32_hit_nc_1 ( + .CI(com_cmm_u_cmm_decoder_un11_bar5_32_hit_nc_0_5406), + .DI(com_cmm_u_cmm_decoder_GND_5513), + .LO(com_cmm_u_cmm_decoder_un11_bar5_32_hit_nc_1_5407), + .S(com_cmm_u_cmm_decoder_un11_bar5_32_hit_nc_1_and) + ); + MUXCY_L com_cmm_u_cmm_decoder_un11_bar5_32_hit_nc_2 ( + .CI(com_cmm_u_cmm_decoder_un11_bar5_32_hit_nc_1_5407), + .DI(com_cmm_u_cmm_decoder_GND_5513), + .LO(com_cmm_u_cmm_decoder_un11_bar5_32_hit_nc_2_5408), + .S(com_cmm_u_cmm_decoder_un11_bar5_32_hit_nc_2_and) + ); + MUXCY_L com_cmm_u_cmm_decoder_un11_bar5_32_hit_nc_3 ( + .CI(com_cmm_u_cmm_decoder_un11_bar5_32_hit_nc_2_5408), + .DI(com_cmm_u_cmm_decoder_GND_5513), + .LO(com_cmm_u_cmm_decoder_un11_bar5_32_hit_nc_3_5409), + .S(com_cmm_u_cmm_decoder_un11_bar5_32_hit_nc_3_and) + ); + MUXCY_L com_cmm_u_cmm_decoder_un11_bar5_32_hit_nc_4 ( + .CI(com_cmm_u_cmm_decoder_un11_bar5_32_hit_nc_3_5409), + .DI(com_cmm_u_cmm_decoder_GND_5513), + .LO(com_cmm_u_cmm_decoder_un11_bar5_32_hit_nc_4_5410), + .S(com_cmm_u_cmm_decoder_un11_bar5_32_hit_nc_4_and) + ); + MUXCY_L com_cmm_u_cmm_decoder_un11_bar5_32_hit_nc_5 ( + .CI(com_cmm_u_cmm_decoder_un11_bar5_32_hit_nc_4_5410), + .DI(com_cmm_u_cmm_decoder_GND_5513), + .LO(com_cmm_u_cmm_decoder_un11_bar5_32_hit_nc_5_5411), + .S(com_cmm_u_cmm_decoder_un11_bar5_32_hit_nc_5_and) + ); + MUXCY_L com_cmm_u_cmm_decoder_un11_bar5_32_hit_nc_6 ( + .CI(com_cmm_u_cmm_decoder_un11_bar5_32_hit_nc_5_5411), + .DI(com_cmm_u_cmm_decoder_GND_5513), + .LO(com_cmm_u_cmm_decoder_un11_bar5_32_hit_nc_6_5412), + .S(com_cmm_u_cmm_decoder_un11_bar5_32_hit_nc_6_and) + ); + MUXCY com_cmm_u_cmm_decoder_un11_bar5_32_hit_nc_7 ( + .CI(com_cmm_u_cmm_decoder_un11_bar5_32_hit_nc_6_5412), + .DI(com_cmm_u_cmm_decoder_GND_5513), + .O(com_cmm_u_cmm_decoder_un11_bar5_32_hit_nc_7_5498), + .S(com_cmm_u_cmm_decoder_un11_bar5_32_hit_nc_7_and) + ); + MUXCY_L com_cmm_u_cmm_decoder_un11_bar4_32_hit_nc_0 ( + .CI(com_cmm_u_cmm_decoder_VCC_5484), + .DI(com_cmm_u_cmm_decoder_GND_5513), + .LO(com_cmm_u_cmm_decoder_un11_bar4_32_hit_nc_0_5413), + .S(com_cmm_u_cmm_decoder_un11_bar4_32_hit_nc_0_sf_5553) + ); + MUXCY_L com_cmm_u_cmm_decoder_un11_bar4_32_hit_nc_1 ( + .CI(com_cmm_u_cmm_decoder_un11_bar4_32_hit_nc_0_5413), + .DI(com_cmm_u_cmm_decoder_GND_5513), + .LO(com_cmm_u_cmm_decoder_un11_bar4_32_hit_nc_1_5414), + .S(com_cmm_u_cmm_decoder_un11_bar4_32_hit_nc_1_sf_5552) + ); + MUXCY_L com_cmm_u_cmm_decoder_un11_bar4_32_hit_nc_2 ( + .CI(com_cmm_u_cmm_decoder_un11_bar4_32_hit_nc_1_5414), + .DI(com_cmm_u_cmm_decoder_GND_5513), + .LO(com_cmm_u_cmm_decoder_un11_bar4_32_hit_nc_2_5415), + .S(com_cmm_u_cmm_decoder_un11_bar4_32_hit_nc_2_sf_5551) + ); + MUXCY_L com_cmm_u_cmm_decoder_un11_bar4_32_hit_nc_3 ( + .CI(com_cmm_u_cmm_decoder_un11_bar4_32_hit_nc_2_5415), + .DI(com_cmm_u_cmm_decoder_GND_5513), + .LO(com_cmm_u_cmm_decoder_un11_bar4_32_hit_nc_3_5416), + .S(com_cmm_u_cmm_decoder_un11_bar4_32_hit_nc_3_sf_5550) + ); + MUXCY_L com_cmm_u_cmm_decoder_un11_bar4_32_hit_nc_4 ( + .CI(com_cmm_u_cmm_decoder_un11_bar4_32_hit_nc_3_5416), + .DI(com_cmm_u_cmm_decoder_GND_5513), + .LO(com_cmm_u_cmm_decoder_un11_bar4_32_hit_nc_4_5417), + .S(com_cmm_u_cmm_decoder_un11_bar4_32_hit_nc_4_sf_5549) + ); + MUXCY_L com_cmm_u_cmm_decoder_un11_bar4_32_hit_nc_5 ( + .CI(com_cmm_u_cmm_decoder_un11_bar4_32_hit_nc_4_5417), + .DI(com_cmm_u_cmm_decoder_GND_5513), + .LO(com_cmm_u_cmm_decoder_un11_bar4_32_hit_nc_5_5418), + .S(com_cmm_u_cmm_decoder_un11_bar4_32_hit_nc_5_sf_5548) + ); + MUXCY_L com_cmm_u_cmm_decoder_un11_bar4_32_hit_nc_6 ( + .CI(com_cmm_u_cmm_decoder_un11_bar4_32_hit_nc_5_5418), + .DI(com_cmm_u_cmm_decoder_GND_5513), + .LO(com_cmm_u_cmm_decoder_un11_bar4_32_hit_nc_6_5419), + .S(com_cmm_u_cmm_decoder_un11_bar4_32_hit_nc_6_sf_5547) + ); + MUXCY_L com_cmm_u_cmm_decoder_un11_bar4_32_hit_nc_7 ( + .CI(com_cmm_u_cmm_decoder_un11_bar4_32_hit_nc_6_5419), + .DI(com_cmm_u_cmm_decoder_GND_5513), + .LO(com_cmm_u_cmm_decoder_un11_bar4_32_hit_nc_7_5420), + .S(com_cmm_u_cmm_decoder_un11_bar4_32_hit_nc_7_sf_5546) + ); + MUXCY com_cmm_u_cmm_decoder_un11_bar4_32_hit_nc_8 ( + .CI(com_cmm_u_cmm_decoder_un11_bar4_32_hit_nc_7_5420), + .DI(com_cmm_u_cmm_decoder_GND_5513), + .O(com_cmm_u_cmm_decoder_un11_bar4_32_hit_nc_8_5507), + .S(cfg_cfg_i_224_) + ); + MUXCY_L com_cmm_u_cmm_decoder_un11_bar3_32_hit_nc_0 ( + .CI(com_cmm_u_cmm_decoder_VCC_5484), + .DI(com_cmm_u_cmm_decoder_GND_5513), + .LO(com_cmm_u_cmm_decoder_un11_bar3_32_hit_nc_0_5421), + .S(com_cmm_u_cmm_decoder_un11_bar3_32_hit_nc_0_and) + ); + MUXCY_L com_cmm_u_cmm_decoder_un11_bar3_32_hit_nc_1 ( + .CI(com_cmm_u_cmm_decoder_un11_bar3_32_hit_nc_0_5421), + .DI(com_cmm_u_cmm_decoder_GND_5513), + .LO(com_cmm_u_cmm_decoder_un11_bar3_32_hit_nc_1_5422), + .S(com_cmm_u_cmm_decoder_un11_bar3_32_hit_nc_1_and) + ); + MUXCY_L com_cmm_u_cmm_decoder_un11_bar3_32_hit_nc_2 ( + .CI(com_cmm_u_cmm_decoder_un11_bar3_32_hit_nc_1_5422), + .DI(com_cmm_u_cmm_decoder_GND_5513), + .LO(com_cmm_u_cmm_decoder_un11_bar3_32_hit_nc_2_5423), + .S(com_cmm_u_cmm_decoder_un11_bar3_32_hit_nc_2_and) + ); + MUXCY_L com_cmm_u_cmm_decoder_un11_bar3_32_hit_nc_3 ( + .CI(com_cmm_u_cmm_decoder_un11_bar3_32_hit_nc_2_5423), + .DI(com_cmm_u_cmm_decoder_GND_5513), + .LO(com_cmm_u_cmm_decoder_un11_bar3_32_hit_nc_3_5424), + .S(com_cmm_u_cmm_decoder_un11_bar3_32_hit_nc_3_and) + ); + MUXCY_L com_cmm_u_cmm_decoder_un11_bar3_32_hit_nc_4 ( + .CI(com_cmm_u_cmm_decoder_un11_bar3_32_hit_nc_3_5424), + .DI(com_cmm_u_cmm_decoder_GND_5513), + .LO(com_cmm_u_cmm_decoder_un11_bar3_32_hit_nc_4_5425), + .S(com_cmm_u_cmm_decoder_un11_bar3_32_hit_nc_4_and) + ); + MUXCY_L com_cmm_u_cmm_decoder_un11_bar3_32_hit_nc_5 ( + .CI(com_cmm_u_cmm_decoder_un11_bar3_32_hit_nc_4_5425), + .DI(com_cmm_u_cmm_decoder_GND_5513), + .LO(com_cmm_u_cmm_decoder_un11_bar3_32_hit_nc_5_5426), + .S(com_cmm_u_cmm_decoder_un11_bar3_32_hit_nc_5_and) + ); + MUXCY_L com_cmm_u_cmm_decoder_un11_bar3_32_hit_nc_6 ( + .CI(com_cmm_u_cmm_decoder_un11_bar3_32_hit_nc_5_5426), + .DI(com_cmm_u_cmm_decoder_GND_5513), + .LO(com_cmm_u_cmm_decoder_un11_bar3_32_hit_nc_6_5427), + .S(com_cmm_u_cmm_decoder_un11_bar3_32_hit_nc_6_and) + ); + MUXCY com_cmm_u_cmm_decoder_un11_bar3_32_hit_nc_7 ( + .CI(com_cmm_u_cmm_decoder_un11_bar3_32_hit_nc_6_5427), + .DI(com_cmm_u_cmm_decoder_GND_5513), + .O(com_cmm_u_cmm_decoder_un11_bar3_32_hit_nc_7_5500), + .S(com_cmm_u_cmm_decoder_un11_bar3_32_hit_nc_7_and) + ); + MUXCY_L com_cmm_u_cmm_decoder_un11_bar2_32_hit_nc_0 ( + .CI(com_cmm_u_cmm_decoder_VCC_5484), + .DI(com_cmm_u_cmm_decoder_GND_5513), + .LO(com_cmm_u_cmm_decoder_un11_bar2_32_hit_nc_0_5428), + .S(com_cmm_u_cmm_decoder_un11_bar2_32_hit_nc_0_and) + ); + MUXCY_L com_cmm_u_cmm_decoder_un11_bar2_32_hit_nc_1 ( + .CI(com_cmm_u_cmm_decoder_un11_bar2_32_hit_nc_0_5428), + .DI(com_cmm_u_cmm_decoder_GND_5513), + .LO(com_cmm_u_cmm_decoder_un11_bar2_32_hit_nc_1_5429), + .S(com_cmm_u_cmm_decoder_un11_bar2_32_hit_nc_1_and) + ); + MUXCY_L com_cmm_u_cmm_decoder_un11_bar2_32_hit_nc_2 ( + .CI(com_cmm_u_cmm_decoder_un11_bar2_32_hit_nc_1_5429), + .DI(com_cmm_u_cmm_decoder_GND_5513), + .LO(com_cmm_u_cmm_decoder_un11_bar2_32_hit_nc_2_5430), + .S(com_cmm_u_cmm_decoder_un11_bar2_32_hit_nc_2_and) + ); + MUXCY_L com_cmm_u_cmm_decoder_un11_bar2_32_hit_nc_3 ( + .CI(com_cmm_u_cmm_decoder_un11_bar2_32_hit_nc_2_5430), + .DI(com_cmm_u_cmm_decoder_GND_5513), + .LO(com_cmm_u_cmm_decoder_un11_bar2_32_hit_nc_3_5431), + .S(com_cmm_u_cmm_decoder_un11_bar2_32_hit_nc_3_and) + ); + MUXCY_L com_cmm_u_cmm_decoder_un11_bar2_32_hit_nc_4 ( + .CI(com_cmm_u_cmm_decoder_un11_bar2_32_hit_nc_3_5431), + .DI(com_cmm_u_cmm_decoder_GND_5513), + .LO(com_cmm_u_cmm_decoder_un11_bar2_32_hit_nc_4_5432), + .S(com_cmm_u_cmm_decoder_un11_bar2_32_hit_nc_4_and) + ); + MUXCY_L com_cmm_u_cmm_decoder_un11_bar2_32_hit_nc_5 ( + .CI(com_cmm_u_cmm_decoder_un11_bar2_32_hit_nc_4_5432), + .DI(com_cmm_u_cmm_decoder_GND_5513), + .LO(com_cmm_u_cmm_decoder_un11_bar2_32_hit_nc_5_5433), + .S(com_cmm_u_cmm_decoder_un11_bar2_32_hit_nc_5_and) + ); + MUXCY_L com_cmm_u_cmm_decoder_un11_bar2_32_hit_nc_6 ( + .CI(com_cmm_u_cmm_decoder_un11_bar2_32_hit_nc_5_5433), + .DI(com_cmm_u_cmm_decoder_GND_5513), + .LO(com_cmm_u_cmm_decoder_un11_bar2_32_hit_nc_6_5434), + .S(com_cmm_u_cmm_decoder_un11_bar2_32_hit_nc_6_and) + ); + MUXCY com_cmm_u_cmm_decoder_un11_bar2_32_hit_nc_7 ( + .CI(com_cmm_u_cmm_decoder_un11_bar2_32_hit_nc_6_5434), + .DI(com_cmm_u_cmm_decoder_GND_5513), + .O(com_cmm_u_cmm_decoder_un11_bar2_32_hit_nc_7_5501), + .S(com_cmm_u_cmm_decoder_un11_bar2_32_hit_nc_7_and) + ); + MUXCY_L com_cmm_u_cmm_decoder_un11_bar1_32_hit_nc_0 ( + .CI(com_cmm_u_cmm_decoder_VCC_5484), + .DI(com_cmm_u_cmm_decoder_GND_5513), + .LO(com_cmm_u_cmm_decoder_un11_bar1_32_hit_nc_0_5435), + .S(com_cmm_u_cmm_decoder_un11_bar1_32_hit_nc_0_and) + ); + MUXCY_L com_cmm_u_cmm_decoder_un11_bar1_32_hit_nc_1 ( + .CI(com_cmm_u_cmm_decoder_un11_bar1_32_hit_nc_0_5435), + .DI(com_cmm_u_cmm_decoder_GND_5513), + .LO(com_cmm_u_cmm_decoder_un11_bar1_32_hit_nc_1_5436), + .S(com_cmm_u_cmm_decoder_un11_bar1_32_hit_nc_1_and) + ); + MUXCY_L com_cmm_u_cmm_decoder_un11_bar1_32_hit_nc_2 ( + .CI(com_cmm_u_cmm_decoder_un11_bar1_32_hit_nc_1_5436), + .DI(com_cmm_u_cmm_decoder_GND_5513), + .LO(com_cmm_u_cmm_decoder_un11_bar1_32_hit_nc_2_5437), + .S(com_cmm_u_cmm_decoder_un11_bar1_32_hit_nc_2_and) + ); + MUXCY_L com_cmm_u_cmm_decoder_un11_bar1_32_hit_nc_3 ( + .CI(com_cmm_u_cmm_decoder_un11_bar1_32_hit_nc_2_5437), + .DI(com_cmm_u_cmm_decoder_GND_5513), + .LO(com_cmm_u_cmm_decoder_un11_bar1_32_hit_nc_3_5438), + .S(com_cmm_u_cmm_decoder_un11_bar1_32_hit_nc_3_and) + ); + MUXCY_L com_cmm_u_cmm_decoder_un11_bar1_32_hit_nc_4 ( + .CI(com_cmm_u_cmm_decoder_un11_bar1_32_hit_nc_3_5438), + .DI(com_cmm_u_cmm_decoder_GND_5513), + .LO(com_cmm_u_cmm_decoder_un11_bar1_32_hit_nc_4_5439), + .S(com_cmm_u_cmm_decoder_un11_bar1_32_hit_nc_4_and) + ); + MUXCY_L com_cmm_u_cmm_decoder_un11_bar1_32_hit_nc_5 ( + .CI(com_cmm_u_cmm_decoder_un11_bar1_32_hit_nc_4_5439), + .DI(com_cmm_u_cmm_decoder_GND_5513), + .LO(com_cmm_u_cmm_decoder_un11_bar1_32_hit_nc_5_5440), + .S(com_cmm_u_cmm_decoder_un11_bar1_32_hit_nc_5_and) + ); + MUXCY_L com_cmm_u_cmm_decoder_un11_bar1_32_hit_nc_6 ( + .CI(com_cmm_u_cmm_decoder_un11_bar1_32_hit_nc_5_5440), + .DI(com_cmm_u_cmm_decoder_GND_5513), + .LO(com_cmm_u_cmm_decoder_un11_bar1_32_hit_nc_6_5441), + .S(com_cmm_u_cmm_decoder_un11_bar1_32_hit_nc_6_and) + ); + MUXCY com_cmm_u_cmm_decoder_un11_bar1_32_hit_nc_7 ( + .CI(com_cmm_u_cmm_decoder_un11_bar1_32_hit_nc_6_5441), + .DI(com_cmm_u_cmm_decoder_GND_5513), + .O(com_cmm_u_cmm_decoder_un11_bar1_32_hit_nc_7_5502), + .S(com_cmm_u_cmm_decoder_un11_bar1_32_hit_nc_7_and) + ); + MUXCY_L com_cmm_u_cmm_decoder_un18_bar4_32_hit_nc_0 ( + .CI(com_cmm_u_cmm_decoder_VCC_5484), + .DI(com_cmm_u_cmm_decoder_GND_5513), + .LO(com_cmm_u_cmm_decoder_un18_bar4_32_hit_nc_0_5442), + .S(com_cmm_u_cmm_decoder_un18_bar4_32_hit_nc_0_and) + ); + MUXCY_L com_cmm_u_cmm_decoder_un18_bar4_32_hit_nc_1 ( + .CI(com_cmm_u_cmm_decoder_un18_bar4_32_hit_nc_0_5442), + .DI(com_cmm_u_cmm_decoder_GND_5513), + .LO(com_cmm_u_cmm_decoder_un18_bar4_32_hit_nc_1_5443), + .S(com_cmm_u_cmm_decoder_un18_bar4_32_hit_nc_1_and) + ); + MUXCY_L com_cmm_u_cmm_decoder_un18_bar4_32_hit_nc_2 ( + .CI(com_cmm_u_cmm_decoder_un18_bar4_32_hit_nc_1_5443), + .DI(com_cmm_u_cmm_decoder_GND_5513), + .LO(com_cmm_u_cmm_decoder_un18_bar4_32_hit_nc_2_5444), + .S(com_cmm_u_cmm_decoder_un18_bar4_32_hit_nc_2_and) + ); + MUXCY_L com_cmm_u_cmm_decoder_un18_bar4_32_hit_nc_3 ( + .CI(com_cmm_u_cmm_decoder_un18_bar4_32_hit_nc_2_5444), + .DI(com_cmm_u_cmm_decoder_GND_5513), + .LO(com_cmm_u_cmm_decoder_un18_bar4_32_hit_nc_3_5445), + .S(com_cmm_u_cmm_decoder_un18_bar4_32_hit_nc_3_and) + ); + MUXCY_L com_cmm_u_cmm_decoder_un18_bar4_32_hit_nc_4 ( + .CI(com_cmm_u_cmm_decoder_un18_bar4_32_hit_nc_3_5445), + .DI(com_cmm_u_cmm_decoder_GND_5513), + .LO(com_cmm_u_cmm_decoder_un18_bar4_32_hit_nc_4_5446), + .S(com_cmm_u_cmm_decoder_un18_bar4_32_hit_nc_4_and) + ); + MUXCY_L com_cmm_u_cmm_decoder_un18_bar4_32_hit_nc_5 ( + .CI(com_cmm_u_cmm_decoder_un18_bar4_32_hit_nc_4_5446), + .DI(com_cmm_u_cmm_decoder_GND_5513), + .LO(com_cmm_u_cmm_decoder_un18_bar4_32_hit_nc_5_5447), + .S(com_cmm_u_cmm_decoder_un18_bar4_32_hit_nc_5_and) + ); + MUXCY_L com_cmm_u_cmm_decoder_un18_bar4_32_hit_nc_6 ( + .CI(com_cmm_u_cmm_decoder_un18_bar4_32_hit_nc_5_5447), + .DI(com_cmm_u_cmm_decoder_GND_5513), + .LO(com_cmm_u_cmm_decoder_un18_bar4_32_hit_nc_6_5448), + .S(com_cmm_u_cmm_decoder_un18_bar4_32_hit_nc_6_and) + ); + MUXCY com_cmm_u_cmm_decoder_un18_bar4_32_hit_nc_7 ( + .CI(com_cmm_u_cmm_decoder_un18_bar4_32_hit_nc_6_5448), + .DI(com_cmm_u_cmm_decoder_GND_5513), + .O(com_cmm_u_cmm_decoder_un18_bar4_32_hit_nc_7_5506), + .S(com_cmm_u_cmm_decoder_un18_bar4_32_hit_nc_7_and) + ); + MUXCY_L com_cmm_u_cmm_decoder_un18_bar3_32_hit_nc_0 ( + .CI(com_cmm_u_cmm_decoder_VCC_5484), + .DI(com_cmm_u_cmm_decoder_GND_5513), + .LO(com_cmm_u_cmm_decoder_un18_bar3_32_hit_nc_0_5449), + .S(com_cmm_u_cmm_decoder_un18_bar3_32_hit_nc_0_and) + ); + MUXCY_L com_cmm_u_cmm_decoder_un18_bar3_32_hit_nc_1 ( + .CI(com_cmm_u_cmm_decoder_un18_bar3_32_hit_nc_0_5449), + .DI(com_cmm_u_cmm_decoder_GND_5513), + .LO(com_cmm_u_cmm_decoder_un18_bar3_32_hit_nc_1_5450), + .S(com_cmm_u_cmm_decoder_un18_bar3_32_hit_nc_1_and) + ); + MUXCY_L com_cmm_u_cmm_decoder_un18_bar3_32_hit_nc_2 ( + .CI(com_cmm_u_cmm_decoder_un18_bar3_32_hit_nc_1_5450), + .DI(com_cmm_u_cmm_decoder_GND_5513), + .LO(com_cmm_u_cmm_decoder_un18_bar3_32_hit_nc_2_5451), + .S(com_cmm_u_cmm_decoder_un18_bar3_32_hit_nc_2_and) + ); + MUXCY_L com_cmm_u_cmm_decoder_un18_bar3_32_hit_nc_3 ( + .CI(com_cmm_u_cmm_decoder_un18_bar3_32_hit_nc_2_5451), + .DI(com_cmm_u_cmm_decoder_GND_5513), + .LO(com_cmm_u_cmm_decoder_un18_bar3_32_hit_nc_3_5452), + .S(com_cmm_u_cmm_decoder_un18_bar3_32_hit_nc_3_and) + ); + MUXCY_L com_cmm_u_cmm_decoder_un18_bar3_32_hit_nc_4 ( + .CI(com_cmm_u_cmm_decoder_un18_bar3_32_hit_nc_3_5452), + .DI(com_cmm_u_cmm_decoder_GND_5513), + .LO(com_cmm_u_cmm_decoder_un18_bar3_32_hit_nc_4_5453), + .S(com_cmm_u_cmm_decoder_un18_bar3_32_hit_nc_4_and) + ); + MUXCY_L com_cmm_u_cmm_decoder_un18_bar3_32_hit_nc_5 ( + .CI(com_cmm_u_cmm_decoder_un18_bar3_32_hit_nc_4_5453), + .DI(com_cmm_u_cmm_decoder_GND_5513), + .LO(com_cmm_u_cmm_decoder_un18_bar3_32_hit_nc_5_5454), + .S(com_cmm_u_cmm_decoder_un18_bar3_32_hit_nc_5_and) + ); + MUXCY_L com_cmm_u_cmm_decoder_un18_bar3_32_hit_nc_6 ( + .CI(com_cmm_u_cmm_decoder_un18_bar3_32_hit_nc_5_5454), + .DI(com_cmm_u_cmm_decoder_GND_5513), + .LO(com_cmm_u_cmm_decoder_un18_bar3_32_hit_nc_6_5455), + .S(com_cmm_u_cmm_decoder_un18_bar3_32_hit_nc_6_and) + ); + MUXCY com_cmm_u_cmm_decoder_un18_bar3_32_hit_nc_7 ( + .CI(com_cmm_u_cmm_decoder_un18_bar3_32_hit_nc_6_5455), + .DI(com_cmm_u_cmm_decoder_GND_5513), + .O(com_cmm_u_cmm_decoder_un18_bar3_32_hit_nc_7_5509), + .S(com_cmm_u_cmm_decoder_un18_bar3_32_hit_nc_7_and) + ); + MUXCY_L com_cmm_u_cmm_decoder_un18_bar2_32_hit_nc_0 ( + .CI(com_cmm_u_cmm_decoder_VCC_5484), + .DI(com_cmm_u_cmm_decoder_GND_5513), + .LO(com_cmm_u_cmm_decoder_un18_bar2_32_hit_nc_0_5456), + .S(com_cmm_u_cmm_decoder_un18_bar2_32_hit_nc_0_and) + ); + MUXCY_L com_cmm_u_cmm_decoder_un18_bar2_32_hit_nc_1 ( + .CI(com_cmm_u_cmm_decoder_un18_bar2_32_hit_nc_0_5456), + .DI(com_cmm_u_cmm_decoder_GND_5513), + .LO(com_cmm_u_cmm_decoder_un18_bar2_32_hit_nc_1_5457), + .S(com_cmm_u_cmm_decoder_un18_bar2_32_hit_nc_1_and) + ); + MUXCY_L com_cmm_u_cmm_decoder_un18_bar2_32_hit_nc_2 ( + .CI(com_cmm_u_cmm_decoder_un18_bar2_32_hit_nc_1_5457), + .DI(com_cmm_u_cmm_decoder_GND_5513), + .LO(com_cmm_u_cmm_decoder_un18_bar2_32_hit_nc_2_5458), + .S(com_cmm_u_cmm_decoder_un18_bar2_32_hit_nc_2_and) + ); + MUXCY_L com_cmm_u_cmm_decoder_un18_bar2_32_hit_nc_3 ( + .CI(com_cmm_u_cmm_decoder_un18_bar2_32_hit_nc_2_5458), + .DI(com_cmm_u_cmm_decoder_GND_5513), + .LO(com_cmm_u_cmm_decoder_un18_bar2_32_hit_nc_3_5459), + .S(com_cmm_u_cmm_decoder_un18_bar2_32_hit_nc_3_and) + ); + MUXCY_L com_cmm_u_cmm_decoder_un18_bar2_32_hit_nc_4 ( + .CI(com_cmm_u_cmm_decoder_un18_bar2_32_hit_nc_3_5459), + .DI(com_cmm_u_cmm_decoder_GND_5513), + .LO(com_cmm_u_cmm_decoder_un18_bar2_32_hit_nc_4_5460), + .S(com_cmm_u_cmm_decoder_un18_bar2_32_hit_nc_4_and) + ); + MUXCY_L com_cmm_u_cmm_decoder_un18_bar2_32_hit_nc_5 ( + .CI(com_cmm_u_cmm_decoder_un18_bar2_32_hit_nc_4_5460), + .DI(com_cmm_u_cmm_decoder_GND_5513), + .LO(com_cmm_u_cmm_decoder_un18_bar2_32_hit_nc_5_5461), + .S(com_cmm_u_cmm_decoder_un18_bar2_32_hit_nc_5_and) + ); + MUXCY_L com_cmm_u_cmm_decoder_un18_bar2_32_hit_nc_6 ( + .CI(com_cmm_u_cmm_decoder_un18_bar2_32_hit_nc_5_5461), + .DI(com_cmm_u_cmm_decoder_GND_5513), + .LO(com_cmm_u_cmm_decoder_un18_bar2_32_hit_nc_6_5462), + .S(com_cmm_u_cmm_decoder_un18_bar2_32_hit_nc_6_and) + ); + MUXCY com_cmm_u_cmm_decoder_un18_bar2_32_hit_nc_7 ( + .CI(com_cmm_u_cmm_decoder_un18_bar2_32_hit_nc_6_5462), + .DI(com_cmm_u_cmm_decoder_GND_5513), + .O(com_cmm_u_cmm_decoder_un18_bar2_32_hit_nc_7_5494), + .S(com_cmm_u_cmm_decoder_un18_bar2_32_hit_nc_7_and) + ); + MUXCY_L com_cmm_u_cmm_decoder_un18_bar1_32_hit_nc_0 ( + .CI(com_cmm_u_cmm_decoder_VCC_5484), + .DI(com_cmm_u_cmm_decoder_GND_5513), + .LO(com_cmm_u_cmm_decoder_un18_bar1_32_hit_nc_0_5463), + .S(com_cmm_u_cmm_decoder_un18_bar1_32_hit_nc_0_and) + ); + MUXCY_L com_cmm_u_cmm_decoder_un18_bar1_32_hit_nc_1 ( + .CI(com_cmm_u_cmm_decoder_un18_bar1_32_hit_nc_0_5463), + .DI(com_cmm_u_cmm_decoder_GND_5513), + .LO(com_cmm_u_cmm_decoder_un18_bar1_32_hit_nc_1_5464), + .S(com_cmm_u_cmm_decoder_un18_bar1_32_hit_nc_1_and) + ); + MUXCY_L com_cmm_u_cmm_decoder_un18_bar1_32_hit_nc_2 ( + .CI(com_cmm_u_cmm_decoder_un18_bar1_32_hit_nc_1_5464), + .DI(com_cmm_u_cmm_decoder_GND_5513), + .LO(com_cmm_u_cmm_decoder_un18_bar1_32_hit_nc_2_5465), + .S(com_cmm_u_cmm_decoder_un18_bar1_32_hit_nc_2_and) + ); + MUXCY_L com_cmm_u_cmm_decoder_un18_bar1_32_hit_nc_3 ( + .CI(com_cmm_u_cmm_decoder_un18_bar1_32_hit_nc_2_5465), + .DI(com_cmm_u_cmm_decoder_GND_5513), + .LO(com_cmm_u_cmm_decoder_un18_bar1_32_hit_nc_3_5466), + .S(com_cmm_u_cmm_decoder_un18_bar1_32_hit_nc_3_and) + ); + MUXCY_L com_cmm_u_cmm_decoder_un18_bar1_32_hit_nc_4 ( + .CI(com_cmm_u_cmm_decoder_un18_bar1_32_hit_nc_3_5466), + .DI(com_cmm_u_cmm_decoder_GND_5513), + .LO(com_cmm_u_cmm_decoder_un18_bar1_32_hit_nc_4_5467), + .S(com_cmm_u_cmm_decoder_un18_bar1_32_hit_nc_4_and) + ); + MUXCY_L com_cmm_u_cmm_decoder_un18_bar1_32_hit_nc_5 ( + .CI(com_cmm_u_cmm_decoder_un18_bar1_32_hit_nc_4_5467), + .DI(com_cmm_u_cmm_decoder_GND_5513), + .LO(com_cmm_u_cmm_decoder_un18_bar1_32_hit_nc_5_5468), + .S(com_cmm_u_cmm_decoder_un18_bar1_32_hit_nc_5_and) + ); + MUXCY_L com_cmm_u_cmm_decoder_un18_bar1_32_hit_nc_6 ( + .CI(com_cmm_u_cmm_decoder_un18_bar1_32_hit_nc_5_5468), + .DI(com_cmm_u_cmm_decoder_GND_5513), + .LO(com_cmm_u_cmm_decoder_un18_bar1_32_hit_nc_6_5469), + .S(com_cmm_u_cmm_decoder_un18_bar1_32_hit_nc_6_and) + ); + MUXCY com_cmm_u_cmm_decoder_un18_bar1_32_hit_nc_7 ( + .CI(com_cmm_u_cmm_decoder_un18_bar1_32_hit_nc_6_5469), + .DI(com_cmm_u_cmm_decoder_GND_5513), + .O(com_cmm_u_cmm_decoder_un18_bar1_32_hit_nc_7_5496), + .S(com_cmm_u_cmm_decoder_un18_bar1_32_hit_nc_7_and) + ); + MUXCY_L com_cmm_u_cmm_decoder_un18_bar0_32_hit_nc_0 ( + .CI(com_cmm_u_cmm_decoder_VCC_5484), + .DI(com_cmm_u_cmm_decoder_GND_5513), + .LO(com_cmm_u_cmm_decoder_un18_bar0_32_hit_nc_0_5470), + .S(com_cmm_u_cmm_decoder_un18_bar0_32_hit_nc_0_and) + ); + MUXCY_L com_cmm_u_cmm_decoder_un18_bar0_32_hit_nc_1 ( + .CI(com_cmm_u_cmm_decoder_un18_bar0_32_hit_nc_0_5470), + .DI(com_cmm_u_cmm_decoder_GND_5513), + .LO(com_cmm_u_cmm_decoder_un18_bar0_32_hit_nc_1_5471), + .S(com_cmm_u_cmm_decoder_un18_bar0_32_hit_nc_1_and) + ); + MUXCY_L com_cmm_u_cmm_decoder_un18_bar0_32_hit_nc_2 ( + .CI(com_cmm_u_cmm_decoder_un18_bar0_32_hit_nc_1_5471), + .DI(com_cmm_u_cmm_decoder_GND_5513), + .LO(com_cmm_u_cmm_decoder_un18_bar0_32_hit_nc_2_5472), + .S(com_cmm_u_cmm_decoder_un18_bar0_32_hit_nc_2_and) + ); + MUXCY_L com_cmm_u_cmm_decoder_un18_bar0_32_hit_nc_3 ( + .CI(com_cmm_u_cmm_decoder_un18_bar0_32_hit_nc_2_5472), + .DI(com_cmm_u_cmm_decoder_GND_5513), + .LO(com_cmm_u_cmm_decoder_un18_bar0_32_hit_nc_3_5473), + .S(com_cmm_u_cmm_decoder_un18_bar0_32_hit_nc_3_and) + ); + MUXCY_L com_cmm_u_cmm_decoder_un18_bar0_32_hit_nc_4 ( + .CI(com_cmm_u_cmm_decoder_un18_bar0_32_hit_nc_3_5473), + .DI(com_cmm_u_cmm_decoder_GND_5513), + .LO(com_cmm_u_cmm_decoder_un18_bar0_32_hit_nc_4_5474), + .S(com_cmm_u_cmm_decoder_un18_bar0_32_hit_nc_4_and) + ); + MUXCY_L com_cmm_u_cmm_decoder_un18_bar0_32_hit_nc_5 ( + .CI(com_cmm_u_cmm_decoder_un18_bar0_32_hit_nc_4_5474), + .DI(com_cmm_u_cmm_decoder_GND_5513), + .LO(com_cmm_u_cmm_decoder_un18_bar0_32_hit_nc_5_5475), + .S(com_cmm_u_cmm_decoder_un18_bar0_32_hit_nc_5_and) + ); + MUXCY_L com_cmm_u_cmm_decoder_un18_bar0_32_hit_nc_6 ( + .CI(com_cmm_u_cmm_decoder_un18_bar0_32_hit_nc_5_5475), + .DI(com_cmm_u_cmm_decoder_GND_5513), + .LO(com_cmm_u_cmm_decoder_un18_bar0_32_hit_nc_6_5476), + .S(com_cmm_u_cmm_decoder_un18_bar0_32_hit_nc_6_and) + ); + MUXCY com_cmm_u_cmm_decoder_un18_bar0_32_hit_nc_7 ( + .CI(com_cmm_u_cmm_decoder_un18_bar0_32_hit_nc_6_5476), + .DI(com_cmm_u_cmm_decoder_GND_5513), + .O(com_cmm_u_cmm_decoder_un18_bar0_32_hit_nc_7_5503), + .S(com_cmm_u_cmm_decoder_un18_bar0_32_hit_nc_7_and) + ); + MUXCY_L com_cmm_u_cmm_decoder_un11_bar0_32_hit_nc_0 ( + .CI(com_cmm_u_cmm_decoder_VCC_5484), + .DI(com_cmm_u_cmm_decoder_GND_5513), + .LO(com_cmm_u_cmm_decoder_un11_bar0_32_hit_nc_0_5477), + .S(com_cmm_u_cmm_decoder_un11_bar0_32_hit_nc_0_and) + ); + MUXCY_L com_cmm_u_cmm_decoder_un11_bar0_32_hit_nc_1 ( + .CI(com_cmm_u_cmm_decoder_un11_bar0_32_hit_nc_0_5477), + .DI(com_cmm_u_cmm_decoder_GND_5513), + .LO(com_cmm_u_cmm_decoder_un11_bar0_32_hit_nc_1_5478), + .S(com_cmm_u_cmm_decoder_un11_bar0_32_hit_nc_1_and) + ); + MUXCY_L com_cmm_u_cmm_decoder_un11_bar0_32_hit_nc_2 ( + .CI(com_cmm_u_cmm_decoder_un11_bar0_32_hit_nc_1_5478), + .DI(com_cmm_u_cmm_decoder_GND_5513), + .LO(com_cmm_u_cmm_decoder_un11_bar0_32_hit_nc_2_5479), + .S(com_cmm_u_cmm_decoder_un11_bar0_32_hit_nc_2_and) + ); + MUXCY_L com_cmm_u_cmm_decoder_un11_bar0_32_hit_nc_3 ( + .CI(com_cmm_u_cmm_decoder_un11_bar0_32_hit_nc_2_5479), + .DI(com_cmm_u_cmm_decoder_GND_5513), + .LO(com_cmm_u_cmm_decoder_un11_bar0_32_hit_nc_3_5480), + .S(com_cmm_u_cmm_decoder_un11_bar0_32_hit_nc_3_and) + ); + MUXCY_L com_cmm_u_cmm_decoder_un11_bar0_32_hit_nc_4 ( + .CI(com_cmm_u_cmm_decoder_un11_bar0_32_hit_nc_3_5480), + .DI(com_cmm_u_cmm_decoder_GND_5513), + .LO(com_cmm_u_cmm_decoder_un11_bar0_32_hit_nc_4_5481), + .S(com_cmm_u_cmm_decoder_un11_bar0_32_hit_nc_4_and) + ); + MUXCY_L com_cmm_u_cmm_decoder_un11_bar0_32_hit_nc_5 ( + .CI(com_cmm_u_cmm_decoder_un11_bar0_32_hit_nc_4_5481), + .DI(com_cmm_u_cmm_decoder_GND_5513), + .LO(com_cmm_u_cmm_decoder_un11_bar0_32_hit_nc_5_5482), + .S(com_cmm_u_cmm_decoder_un11_bar0_32_hit_nc_5_and) + ); + MUXCY_L com_cmm_u_cmm_decoder_un11_bar0_32_hit_nc_6 ( + .CI(com_cmm_u_cmm_decoder_un11_bar0_32_hit_nc_5_5482), + .DI(com_cmm_u_cmm_decoder_GND_5513), + .LO(com_cmm_u_cmm_decoder_un11_bar0_32_hit_nc_6_5483), + .S(com_cmm_u_cmm_decoder_un11_bar0_32_hit_nc_6_and) + ); + MUXCY com_cmm_u_cmm_decoder_un11_bar0_32_hit_nc_7 ( + .CI(com_cmm_u_cmm_decoder_un11_bar0_32_hit_nc_6_5483), + .DI(com_cmm_u_cmm_decoder_GND_5513), + .O(com_cmm_u_cmm_decoder_un11_bar0_32_hit_nc_7_5504), + .S(com_cmm_u_cmm_decoder_un11_bar0_32_hit_nc_7_and) + ); + MUXCY_L com_cmm_u_cmm_decoder_un7_bar6_32_hit_nc_0 ( + .CI(com_cmm_u_cmm_decoder_VCC_5484), + .DI(com_cmm_u_cmm_decoder_GND_5513), + .LO(com_cmm_u_cmm_decoder_un7_bar6_32_hit_nc_0_5485), + .S(com_cmm_u_cmm_decoder_un7_bar6_32_hit_nc_0_and_5545) + ); + MUXCY_L com_cmm_u_cmm_decoder_un7_bar6_32_hit_nc_1 ( + .CI(com_cmm_u_cmm_decoder_un7_bar6_32_hit_nc_0_5485), + .DI(com_cmm_u_cmm_decoder_GND_5513), + .LO(com_cmm_u_cmm_decoder_un7_bar6_32_hit_nc_1_5486), + .S(com_cmm_u_cmm_decoder_un7_bar6_32_hit_nc_1_and) + ); + MUXCY_L com_cmm_u_cmm_decoder_un7_bar6_32_hit_nc_2 ( + .CI(com_cmm_u_cmm_decoder_un7_bar6_32_hit_nc_1_5486), + .DI(com_cmm_u_cmm_decoder_GND_5513), + .LO(com_cmm_u_cmm_decoder_un7_bar6_32_hit_nc_2_5487), + .S(com_cmm_u_cmm_decoder_un7_bar6_32_hit_nc_2_and) + ); + MUXCY_L com_cmm_u_cmm_decoder_un7_bar6_32_hit_nc_3 ( + .CI(com_cmm_u_cmm_decoder_un7_bar6_32_hit_nc_2_5487), + .DI(com_cmm_u_cmm_decoder_GND_5513), + .LO(com_cmm_u_cmm_decoder_un7_bar6_32_hit_nc_3_5488), + .S(com_cmm_u_cmm_decoder_un7_bar6_32_hit_nc_3_and) + ); + MUXCY_L com_cmm_u_cmm_decoder_un7_bar6_32_hit_nc_4 ( + .CI(com_cmm_u_cmm_decoder_un7_bar6_32_hit_nc_3_5488), + .DI(com_cmm_u_cmm_decoder_GND_5513), + .LO(com_cmm_u_cmm_decoder_un7_bar6_32_hit_nc_4_5489), + .S(com_cmm_u_cmm_decoder_un7_bar6_32_hit_nc_4_and) + ); + MUXCY_L com_cmm_u_cmm_decoder_un7_bar6_32_hit_nc_5 ( + .CI(com_cmm_u_cmm_decoder_un7_bar6_32_hit_nc_4_5489), + .DI(com_cmm_u_cmm_decoder_GND_5513), + .LO(com_cmm_u_cmm_decoder_un7_bar6_32_hit_nc_5_5490), + .S(com_cmm_u_cmm_decoder_un7_bar6_32_hit_nc_5_and) + ); + MUXCY com_cmm_u_cmm_decoder_un7_bar6_32_hit_nc_6 ( + .CI(com_cmm_u_cmm_decoder_un7_bar6_32_hit_nc_5_5490), + .DI(com_cmm_u_cmm_decoder_GND_5513), + .O(com_cmm_u_cmm_decoder_un7_bar6_32_hit_nc_6_5493), + .S(cfg_cfg_i_351_) + ); + defparam com_cmm_u_cmm_decoder_un11_bar34_64_hit_low_0_and_0_a2_0_a2_0_a2_0_o3.INIT = 4'h1; + LUT2 com_cmm_u_cmm_decoder_un11_bar34_64_hit_low_0_and_0_a2_0_a2_0_a2_0_o3 ( + .I0(cfg_cfg_6102[192]), + .I1(cfg_cfg_6102[193]), + .O(com_cmm_N_56058_i) + ); + defparam com_cmm_u_cmm_decoder_un18_bar3_32_hit_nc_0_and_0_a2_0_a2_0_a2_0_a2_1.INIT = 4'h1; + LUT2 com_cmm_u_cmm_decoder_un18_bar3_32_hit_nc_0_and_0_a2_0_a2_0_a2_0_a2_1 ( + .I0(com_cmm_bar4_reg[0]), + .I1(com_cmm_bar4_reg[1]), + .O(com_cmm_u_cmm_decoder_un18_bar3_32_hit_nc_0_and_1) + ); + defparam com_cmm_u_cmm_decoder_bar34_64_hit_high_3_0_a2_0_a2_0_a2_0_a2_1.INIT = 4'h1; + LUT2 com_cmm_u_cmm_decoder_bar34_64_hit_high_3_0_a2_0_a2_0_a2_0_a2_1 ( + .I0(com_cmm_bar3_reg[0]), + .I1(com_cmm_bar3_reg[1]), + .O(com_cmm_u_cmm_decoder_bar34_64_hit_high_3_1) + ); + defparam com_cmm_u_cmm_decoder_un18_bar1_32_hit_nc_0_and_0_a2_0_a2_0_a2_0_a2_1.INIT = 4'h1; + LUT2 com_cmm_u_cmm_decoder_un18_bar1_32_hit_nc_0_and_0_a2_0_a2_0_a2_0_a2_1 ( + .I0(com_cmm_bar2_reg[0]), + .I1(com_cmm_bar2_reg[1]), + .O(com_cmm_u_cmm_decoder_un18_bar1_32_hit_nc_0_and_1) + ); + defparam com_cmm_u_cmm_decoder_un18_bar0_32_hit_nc_0_and_0_a2_0_a2_0_a2_0_a2_1.INIT = 4'h1; + LUT2_L com_cmm_u_cmm_decoder_un18_bar0_32_hit_nc_0_and_0_a2_0_a2_0_a2_0_a2_1 ( + .I0(com_cmm_bar1_reg[0]), + .I1(com_cmm_bar1_reg[1]), + .LO(com_cmm_u_cmm_decoder_un18_bar0_32_hit_nc_0_and_1) + ); + defparam com_cmm_u_cmm_decoder_bar5_32_hit_nc_3_i_0_0_0_o2.INIT = 4'h1; + LUT2 com_cmm_u_cmm_decoder_bar5_32_hit_nc_3_i_0_0_0_o2 ( + .I0(com_cmm_pme_pmcsr[0]), + .I1(com_cmm_pme_pmcsr[1]), + .O(com_cmm_u_cmm_decoder_N_56113_i) + ); + defparam com_cmm_u_cmm_decoder_un11_bar3_32_hit_nc_0_and_0_a2_0_a2_0_a2_0_o3.INIT = 4'h1; + LUT2 com_cmm_u_cmm_decoder_un11_bar3_32_hit_nc_0_and_0_a2_0_a2_0_a2_0_o3 ( + .I0(cfg_cfg_6102[160]), + .I1(cfg_cfg_6102[161]), + .O(com_cmm_N_56057_i) + ); + defparam com_cmm_u_cmm_decoder_un11_bar2_32_hit_nc_0_and_0_a2_0_a2_0_a2_0_o3.INIT = 4'h1; + LUT2 com_cmm_u_cmm_decoder_un11_bar2_32_hit_nc_0_and_0_a2_0_a2_0_a2_0_o3 ( + .I0(cfg_cfg_6102[128]), + .I1(cfg_cfg_6102[129]), + .O(com_cmm_N_56056_i) + ); + defparam com_cmm_u_cmm_decoder_bar5_32_hit_nc_3_i_0_0_0_o3_0.INIT = 4'h8; + LUT2 com_cmm_u_cmm_decoder_bar5_32_hit_nc_3_i_0_0_0_o3_0 ( + .I0(NlwRenamedSig_OI_cfg_command_0_), + .I1(com_cmmt_rio), + .O(com_cmm_u_cmm_decoder_bar5_32_hit_nc_3_i_0_0_0_o3_0_5492) + ); + defparam com_cmm_u_cmm_decoder_bar5_32_hit_nc_3_i_0_0_0_o3.INIT = 4'h8; + LUT2 com_cmm_u_cmm_decoder_bar5_32_hit_nc_3_i_0_0_0_o3 ( + .I0(NlwRenamedSig_OI_cfg_command_1_), + .I1(com_cmmt_mem32), + .O(com_cmm_u_cmm_decoder_N_56035_i) + ); + defparam com_cmm_u_cmm_decoder_bar5_eq_raddr_3_0_I_68.INIT = 8'h6C; + LUT3_L com_cmm_u_cmm_decoder_bar5_eq_raddr_3_0_I_68 ( + .I0(cfg_cfg_6102[243]), + .I1(com_cmm_bar5_reg[19]), + .I2(com_cmmt_raddr[51]), + .LO(com_cmm_u_cmm_decoder_N_54_9) + ); + defparam com_cmm_u_cmm_decoder_bar5_eq_raddr_3_0_I_86.INIT = 8'h6C; + LUT3_L com_cmm_u_cmm_decoder_bar5_eq_raddr_3_0_I_86 ( + .I0(cfg_cfg_6102[241]), + .I1(com_cmm_bar5_reg[17]), + .I2(com_cmmt_raddr[49]), + .LO(com_cmm_u_cmm_decoder_N_38_9) + ); + defparam com_cmm_u_cmm_decoder_un9_bar12_64_hit_high_0_I_86.INIT = 8'h6C; + LUT3_L com_cmm_u_cmm_decoder_un9_bar12_64_hit_high_0_I_86 ( + .I0(cfg_cfg_6102[113]), + .I1(com_cmm_bar1_reg[17]), + .I2(com_cmmt_raddr[17]), + .LO(com_cmm_u_cmm_decoder_N_38_4) + ); + defparam com_cmm_u_cmm_decoder_un9_bar45_64_hit_high_0_I_86.INIT = 8'h6C; + LUT3_L com_cmm_u_cmm_decoder_un9_bar45_64_hit_high_0_I_86 ( + .I0(cfg_cfg_6102[209]), + .I1(com_cmm_bar4_reg[17]), + .I2(com_cmmt_raddr[17]), + .LO(com_cmm_u_cmm_decoder_N_38_7) + ); + defparam com_cmm_u_cmm_decoder_bar1_eq_raddr_3_0_I_86.INIT = 8'h6C; + LUT3 com_cmm_u_cmm_decoder_bar1_eq_raddr_3_0_I_86 ( + .I0(cfg_cfg_6102[113]), + .I1(com_cmm_bar1_reg[17]), + .I2(com_cmmt_raddr[49]), + .O(com_cmm_u_cmm_decoder_N_38_2) + ); + defparam com_cmm_u_cmm_decoder_bar2_eq_raddr_3_0_I_86.INIT = 8'h6C; + LUT3 com_cmm_u_cmm_decoder_bar2_eq_raddr_3_0_I_86 ( + .I0(cfg_cfg_6102[145]), + .I1(com_cmm_bar2_reg[17]), + .I2(com_cmmt_raddr[49]), + .O(com_cmm_u_cmm_decoder_N_38_1) + ); + defparam com_cmm_u_cmm_decoder_bar3_eq_raddr_3_0_I_86.INIT = 8'h6C; + LUT3 com_cmm_u_cmm_decoder_bar3_eq_raddr_3_0_I_86 ( + .I0(cfg_cfg_6102[177]), + .I1(com_cmm_bar3_reg[17]), + .I2(com_cmmt_raddr[49]), + .O(com_cmm_u_cmm_decoder_N_38_0) + ); + defparam com_cmm_u_cmm_decoder_bar4_eq_raddr_3_0_I_86.INIT = 8'h6C; + LUT3 com_cmm_u_cmm_decoder_bar4_eq_raddr_3_0_I_86 ( + .I0(cfg_cfg_6102[209]), + .I1(com_cmm_bar4_reg[17]), + .I2(com_cmmt_raddr[49]), + .O(com_cmm_u_cmm_decoder_N_38) + ); + defparam com_cmm_u_cmm_decoder_un9_bar23_64_hit_high_0_I_95.INIT = 8'h6C; + LUT3_L com_cmm_u_cmm_decoder_un9_bar23_64_hit_high_0_I_95 ( + .I0(cfg_cfg_6102[135]), + .I1(com_cmm_bar2_reg[7]), + .I2(com_cmmt_raddr[7]), + .LO(com_cmm_u_cmm_decoder_N_30_5) + ); + defparam com_cmm_u_cmm_decoder_bar4_eq_raddr_3_0_I_123.INIT = 8'h6C; + LUT3 com_cmm_u_cmm_decoder_bar4_eq_raddr_3_0_I_123 ( + .I0(cfg_cfg_6102[200]), + .I1(com_cmm_bar4_reg[8]), + .I2(com_cmmt_raddr[40]), + .O(com_cmm_u_cmm_decoder_N_7) + ); + defparam com_cmm_u_cmm_decoder_bar4_eq_raddr_3_0_I_122.INIT = 8'h6C; + LUT3 com_cmm_u_cmm_decoder_bar4_eq_raddr_3_0_I_122 ( + .I0(cfg_cfg_6102[201]), + .I1(com_cmm_bar4_reg[9]), + .I2(com_cmmt_raddr[41]), + .O(com_cmm_u_cmm_decoder_N_6) + ); + defparam com_cmm_u_cmm_decoder_bar4_eq_raddr_3_0_I_114.INIT = 8'h6C; + LUT3 com_cmm_u_cmm_decoder_bar4_eq_raddr_3_0_I_114 ( + .I0(cfg_cfg_6102[220]), + .I1(com_cmm_bar4_reg[28]), + .I2(com_cmmt_raddr[60]), + .O(com_cmm_u_cmm_decoder_N_15) + ); + defparam com_cmm_u_cmm_decoder_bar4_eq_raddr_3_0_I_113.INIT = 8'h6C; + LUT3 com_cmm_u_cmm_decoder_bar4_eq_raddr_3_0_I_113 ( + .I0(cfg_cfg_6102[221]), + .I1(com_cmm_bar4_reg[29]), + .I2(com_cmmt_raddr[61]), + .O(com_cmm_u_cmm_decoder_N_14_0) + ); + defparam com_cmm_u_cmm_decoder_bar4_eq_raddr_3_0_I_105.INIT = 8'h6C; + LUT3 com_cmm_u_cmm_decoder_bar4_eq_raddr_3_0_I_105 ( + .I0(cfg_cfg_6102[218]), + .I1(com_cmm_bar4_reg[26]), + .I2(com_cmmt_raddr[58]), + .O(com_cmm_u_cmm_decoder_N_23) + ); + defparam com_cmm_u_cmm_decoder_bar4_eq_raddr_3_0_I_104.INIT = 8'h6C; + LUT3 com_cmm_u_cmm_decoder_bar4_eq_raddr_3_0_I_104 ( + .I0(cfg_cfg_6102[219]), + .I1(com_cmm_bar4_reg[27]), + .I2(com_cmmt_raddr[59]), + .O(com_cmm_u_cmm_decoder_N_22) + ); + defparam com_cmm_u_cmm_decoder_bar4_eq_raddr_3_0_I_96.INIT = 8'h6C; + LUT3 com_cmm_u_cmm_decoder_bar4_eq_raddr_3_0_I_96 ( + .I0(cfg_cfg_6102[198]), + .I1(com_cmm_bar4_reg[6]), + .I2(com_cmmt_raddr[38]), + .O(com_cmm_u_cmm_decoder_N_31) + ); + defparam com_cmm_u_cmm_decoder_bar4_eq_raddr_3_0_I_95.INIT = 8'h6C; + LUT3 com_cmm_u_cmm_decoder_bar4_eq_raddr_3_0_I_95 ( + .I0(cfg_cfg_6102[199]), + .I1(com_cmm_bar4_reg[7]), + .I2(com_cmmt_raddr[39]), + .O(com_cmm_u_cmm_decoder_N_30) + ); + defparam com_cmm_u_cmm_decoder_bar4_eq_raddr_3_0_I_87.INIT = 8'h6C; + LUT3 com_cmm_u_cmm_decoder_bar4_eq_raddr_3_0_I_87 ( + .I0(cfg_cfg_6102[208]), + .I1(com_cmm_bar4_reg[16]), + .I2(com_cmmt_raddr[48]), + .O(com_cmm_u_cmm_decoder_N_39) + ); + defparam com_cmm_u_cmm_decoder_bar4_eq_raddr_3_0_I_78.INIT = 8'h6C; + LUT3 com_cmm_u_cmm_decoder_bar4_eq_raddr_3_0_I_78 ( + .I0(cfg_cfg_6102[212]), + .I1(com_cmm_bar4_reg[20]), + .I2(com_cmmt_raddr[52]), + .O(com_cmm_u_cmm_decoder_N_47) + ); + defparam com_cmm_u_cmm_decoder_bar4_eq_raddr_3_0_I_77.INIT = 8'h6C; + LUT3 com_cmm_u_cmm_decoder_bar4_eq_raddr_3_0_I_77 ( + .I0(cfg_cfg_6102[213]), + .I1(com_cmm_bar4_reg[21]), + .I2(com_cmmt_raddr[53]), + .O(com_cmm_u_cmm_decoder_N_46) + ); + defparam com_cmm_u_cmm_decoder_bar4_eq_raddr_3_0_I_68.INIT = 8'h6C; + LUT3 com_cmm_u_cmm_decoder_bar4_eq_raddr_3_0_I_68 ( + .I0(cfg_cfg_6102[211]), + .I1(com_cmm_bar4_reg[19]), + .I2(com_cmmt_raddr[51]), + .O(com_cmm_u_cmm_decoder_N_54) + ); + defparam com_cmm_u_cmm_decoder_bar4_eq_raddr_3_0_I_60.INIT = 8'h6C; + LUT3 com_cmm_u_cmm_decoder_bar4_eq_raddr_3_0_I_60 ( + .I0(cfg_cfg_6102[206]), + .I1(com_cmm_bar4_reg[14]), + .I2(com_cmmt_raddr[46]), + .O(com_cmm_u_cmm_decoder_N_63) + ); + defparam com_cmm_u_cmm_decoder_bar4_eq_raddr_3_0_I_59.INIT = 8'h6C; + LUT3 com_cmm_u_cmm_decoder_bar4_eq_raddr_3_0_I_59 ( + .I0(cfg_cfg_6102[207]), + .I1(com_cmm_bar4_reg[15]), + .I2(com_cmmt_raddr[47]), + .O(com_cmm_u_cmm_decoder_N_62) + ); + defparam com_cmm_u_cmm_decoder_bar4_eq_raddr_3_0_I_50.INIT = 8'h6C; + LUT3 com_cmm_u_cmm_decoder_bar4_eq_raddr_3_0_I_50 ( + .I0(cfg_cfg_6102[217]), + .I1(com_cmm_bar4_reg[25]), + .I2(com_cmmt_raddr[57]), + .O(com_cmm_u_cmm_decoder_N_70) + ); + defparam com_cmm_u_cmm_decoder_bar4_eq_raddr_3_0_I_42.INIT = 8'h6C; + LUT3 com_cmm_u_cmm_decoder_bar4_eq_raddr_3_0_I_42 ( + .I0(cfg_cfg_6102[204]), + .I1(com_cmm_bar4_reg[12]), + .I2(com_cmmt_raddr[44]), + .O(com_cmm_u_cmm_decoder_N_79) + ); + defparam com_cmm_u_cmm_decoder_bar4_eq_raddr_3_0_I_33.INIT = 8'h6C; + LUT3 com_cmm_u_cmm_decoder_bar4_eq_raddr_3_0_I_33 ( + .I0(cfg_cfg_6102[202]), + .I1(com_cmm_bar4_reg[10]), + .I2(com_cmmt_raddr[42]), + .O(com_cmm_u_cmm_decoder_N_87) + ); + defparam com_cmm_u_cmm_decoder_bar4_eq_raddr_3_0_I_23.INIT = 8'h6C; + LUT3 com_cmm_u_cmm_decoder_bar4_eq_raddr_3_0_I_23 ( + .I0(cfg_cfg_6102[215]), + .I1(com_cmm_bar4_reg[23]), + .I2(com_cmmt_raddr[55]), + .O(com_cmm_u_cmm_decoder_N_94) + ); + defparam com_cmm_u_cmm_decoder_bar4_eq_raddr_3_0_I_14.INIT = 8'h6C; + LUT3 com_cmm_u_cmm_decoder_bar4_eq_raddr_3_0_I_14 ( + .I0(cfg_cfg_6102[223]), + .I1(com_cmm_bar4_reg[31]), + .I2(com_cmmt_raddr[63]), + .O(com_cmm_u_cmm_decoder_N_102) + ); + defparam com_cmm_u_cmm_decoder_bar4_eq_raddr_3_0_I_6.INIT = 8'h6C; + LUT3 com_cmm_u_cmm_decoder_bar4_eq_raddr_3_0_I_6 ( + .I0(cfg_cfg_6102[196]), + .I1(com_cmm_bar4_reg[4]), + .I2(com_cmmt_raddr[36]), + .O(com_cmm_u_cmm_decoder_N_111) + ); + defparam com_cmm_u_cmm_decoder_bar4_eq_raddr_3_0_I_5.INIT = 8'h6C; + LUT3 com_cmm_u_cmm_decoder_bar4_eq_raddr_3_0_I_5 ( + .I0(cfg_cfg_6102[197]), + .I1(com_cmm_bar4_reg[5]), + .I2(com_cmmt_raddr[37]), + .O(com_cmm_u_cmm_decoder_N_110) + ); + defparam com_cmm_u_cmm_decoder_bar3_eq_raddr_3_0_I_123.INIT = 8'h6C; + LUT3 com_cmm_u_cmm_decoder_bar3_eq_raddr_3_0_I_123 ( + .I0(cfg_cfg_6102[168]), + .I1(com_cmm_bar3_reg[8]), + .I2(com_cmmt_raddr[40]), + .O(com_cmm_u_cmm_decoder_N_7_0) + ); + defparam com_cmm_u_cmm_decoder_bar3_eq_raddr_3_0_I_122.INIT = 8'h6C; + LUT3 com_cmm_u_cmm_decoder_bar3_eq_raddr_3_0_I_122 ( + .I0(cfg_cfg_6102[169]), + .I1(com_cmm_bar3_reg[9]), + .I2(com_cmmt_raddr[41]), + .O(com_cmm_u_cmm_decoder_N_6_0) + ); + defparam com_cmm_u_cmm_decoder_bar3_eq_raddr_3_0_I_114.INIT = 8'h6C; + LUT3 com_cmm_u_cmm_decoder_bar3_eq_raddr_3_0_I_114 ( + .I0(cfg_cfg_6102[188]), + .I1(com_cmm_bar3_reg[28]), + .I2(com_cmmt_raddr[60]), + .O(com_cmm_u_cmm_decoder_N_15_0) + ); + defparam com_cmm_u_cmm_decoder_bar3_eq_raddr_3_0_I_113.INIT = 8'h6C; + LUT3 com_cmm_u_cmm_decoder_bar3_eq_raddr_3_0_I_113 ( + .I0(cfg_cfg_6102[189]), + .I1(com_cmm_bar3_reg[29]), + .I2(com_cmmt_raddr[61]), + .O(com_cmm_u_cmm_decoder_N_14_1) + ); + defparam com_cmm_u_cmm_decoder_bar3_eq_raddr_3_0_I_105.INIT = 8'h6C; + LUT3 com_cmm_u_cmm_decoder_bar3_eq_raddr_3_0_I_105 ( + .I0(cfg_cfg_6102[186]), + .I1(com_cmm_bar3_reg[26]), + .I2(com_cmmt_raddr[58]), + .O(com_cmm_u_cmm_decoder_N_23_0) + ); + defparam com_cmm_u_cmm_decoder_bar3_eq_raddr_3_0_I_104.INIT = 8'h6C; + LUT3 com_cmm_u_cmm_decoder_bar3_eq_raddr_3_0_I_104 ( + .I0(cfg_cfg_6102[187]), + .I1(com_cmm_bar3_reg[27]), + .I2(com_cmmt_raddr[59]), + .O(com_cmm_u_cmm_decoder_N_22_0) + ); + defparam com_cmm_u_cmm_decoder_bar3_eq_raddr_3_0_I_96.INIT = 8'h6C; + LUT3 com_cmm_u_cmm_decoder_bar3_eq_raddr_3_0_I_96 ( + .I0(cfg_cfg_6102[166]), + .I1(com_cmm_bar3_reg[6]), + .I2(com_cmmt_raddr[38]), + .O(com_cmm_u_cmm_decoder_N_31_0) + ); + defparam com_cmm_u_cmm_decoder_bar3_eq_raddr_3_0_I_95.INIT = 8'h6C; + LUT3 com_cmm_u_cmm_decoder_bar3_eq_raddr_3_0_I_95 ( + .I0(cfg_cfg_6102[167]), + .I1(com_cmm_bar3_reg[7]), + .I2(com_cmmt_raddr[39]), + .O(com_cmm_u_cmm_decoder_N_30_0) + ); + defparam com_cmm_u_cmm_decoder_bar3_eq_raddr_3_0_I_87.INIT = 8'h6C; + LUT3 com_cmm_u_cmm_decoder_bar3_eq_raddr_3_0_I_87 ( + .I0(cfg_cfg_6102[176]), + .I1(com_cmm_bar3_reg[16]), + .I2(com_cmmt_raddr[48]), + .O(com_cmm_u_cmm_decoder_N_39_0) + ); + defparam com_cmm_u_cmm_decoder_bar3_eq_raddr_3_0_I_78.INIT = 8'h6C; + LUT3 com_cmm_u_cmm_decoder_bar3_eq_raddr_3_0_I_78 ( + .I0(cfg_cfg_6102[180]), + .I1(com_cmm_bar3_reg[20]), + .I2(com_cmmt_raddr[52]), + .O(com_cmm_u_cmm_decoder_N_47_0) + ); + defparam com_cmm_u_cmm_decoder_bar3_eq_raddr_3_0_I_77.INIT = 8'h6C; + LUT3 com_cmm_u_cmm_decoder_bar3_eq_raddr_3_0_I_77 ( + .I0(cfg_cfg_6102[181]), + .I1(com_cmm_bar3_reg[21]), + .I2(com_cmmt_raddr[53]), + .O(com_cmm_u_cmm_decoder_N_46_0) + ); + defparam com_cmm_u_cmm_decoder_bar3_eq_raddr_3_0_I_68.INIT = 8'h6C; + LUT3 com_cmm_u_cmm_decoder_bar3_eq_raddr_3_0_I_68 ( + .I0(cfg_cfg_6102[179]), + .I1(com_cmm_bar3_reg[19]), + .I2(com_cmmt_raddr[51]), + .O(com_cmm_u_cmm_decoder_N_54_0) + ); + defparam com_cmm_u_cmm_decoder_bar3_eq_raddr_3_0_I_60.INIT = 8'h6C; + LUT3 com_cmm_u_cmm_decoder_bar3_eq_raddr_3_0_I_60 ( + .I0(cfg_cfg_6102[174]), + .I1(com_cmm_bar3_reg[14]), + .I2(com_cmmt_raddr[46]), + .O(com_cmm_u_cmm_decoder_N_63_0) + ); + defparam com_cmm_u_cmm_decoder_bar3_eq_raddr_3_0_I_59.INIT = 8'h6C; + LUT3 com_cmm_u_cmm_decoder_bar3_eq_raddr_3_0_I_59 ( + .I0(cfg_cfg_6102[175]), + .I1(com_cmm_bar3_reg[15]), + .I2(com_cmmt_raddr[47]), + .O(com_cmm_u_cmm_decoder_N_62_0) + ); + defparam com_cmm_u_cmm_decoder_bar3_eq_raddr_3_0_I_50.INIT = 8'h6C; + LUT3 com_cmm_u_cmm_decoder_bar3_eq_raddr_3_0_I_50 ( + .I0(cfg_cfg_6102[185]), + .I1(com_cmm_bar3_reg[25]), + .I2(com_cmmt_raddr[57]), + .O(com_cmm_u_cmm_decoder_N_70_0) + ); + defparam com_cmm_u_cmm_decoder_bar3_eq_raddr_3_0_I_41.INIT = 8'h6C; + LUT3 com_cmm_u_cmm_decoder_bar3_eq_raddr_3_0_I_41 ( + .I0(cfg_cfg_6102[173]), + .I1(com_cmm_bar3_reg[13]), + .I2(com_cmmt_raddr[45]), + .O(com_cmm_u_cmm_decoder_N_78) + ); + defparam com_cmm_u_cmm_decoder_bar3_eq_raddr_3_0_I_32.INIT = 8'h6C; + LUT3 com_cmm_u_cmm_decoder_bar3_eq_raddr_3_0_I_32 ( + .I0(cfg_cfg_6102[171]), + .I1(com_cmm_bar3_reg[11]), + .I2(com_cmmt_raddr[43]), + .O(com_cmm_u_cmm_decoder_N_86) + ); + defparam com_cmm_u_cmm_decoder_bar3_eq_raddr_3_0_I_23.INIT = 8'h6C; + LUT3 com_cmm_u_cmm_decoder_bar3_eq_raddr_3_0_I_23 ( + .I0(cfg_cfg_6102[183]), + .I1(com_cmm_bar3_reg[23]), + .I2(com_cmmt_raddr[55]), + .O(com_cmm_u_cmm_decoder_N_94_0) + ); + defparam com_cmm_u_cmm_decoder_bar3_eq_raddr_3_0_I_14.INIT = 8'h6C; + LUT3 com_cmm_u_cmm_decoder_bar3_eq_raddr_3_0_I_14 ( + .I0(cfg_cfg_6102[191]), + .I1(com_cmm_bar3_reg[31]), + .I2(com_cmmt_raddr[63]), + .O(com_cmm_u_cmm_decoder_N_102_0) + ); + defparam com_cmm_u_cmm_decoder_bar3_eq_raddr_3_0_I_6.INIT = 8'h6C; + LUT3 com_cmm_u_cmm_decoder_bar3_eq_raddr_3_0_I_6 ( + .I0(cfg_cfg_6102[164]), + .I1(com_cmm_bar3_reg[4]), + .I2(com_cmmt_raddr[36]), + .O(com_cmm_u_cmm_decoder_N_111_0) + ); + defparam com_cmm_u_cmm_decoder_bar2_eq_raddr_3_0_I_123.INIT = 8'h6C; + LUT3 com_cmm_u_cmm_decoder_bar2_eq_raddr_3_0_I_123 ( + .I0(cfg_cfg_6102[136]), + .I1(com_cmm_bar2_reg[8]), + .I2(com_cmmt_raddr[40]), + .O(com_cmm_u_cmm_decoder_N_7_1) + ); + defparam com_cmm_u_cmm_decoder_bar2_eq_raddr_3_0_I_122.INIT = 8'h6C; + LUT3 com_cmm_u_cmm_decoder_bar2_eq_raddr_3_0_I_122 ( + .I0(cfg_cfg_6102[137]), + .I1(com_cmm_bar2_reg[9]), + .I2(com_cmmt_raddr[41]), + .O(com_cmm_u_cmm_decoder_N_6_1) + ); + defparam com_cmm_u_cmm_decoder_bar2_eq_raddr_3_0_I_114.INIT = 8'h6C; + LUT3 com_cmm_u_cmm_decoder_bar2_eq_raddr_3_0_I_114 ( + .I0(cfg_cfg_6102[156]), + .I1(com_cmm_bar2_reg[28]), + .I2(com_cmmt_raddr[60]), + .O(com_cmm_u_cmm_decoder_N_15_1) + ); + defparam com_cmm_u_cmm_decoder_bar2_eq_raddr_3_0_I_113.INIT = 8'h6C; + LUT3 com_cmm_u_cmm_decoder_bar2_eq_raddr_3_0_I_113 ( + .I0(cfg_cfg_6102[157]), + .I1(com_cmm_bar2_reg[29]), + .I2(com_cmmt_raddr[61]), + .O(com_cmm_u_cmm_decoder_N_14_2) + ); + defparam com_cmm_u_cmm_decoder_bar2_eq_raddr_3_0_I_105.INIT = 8'h6C; + LUT3 com_cmm_u_cmm_decoder_bar2_eq_raddr_3_0_I_105 ( + .I0(cfg_cfg_6102[154]), + .I1(com_cmm_bar2_reg[26]), + .I2(com_cmmt_raddr[58]), + .O(com_cmm_u_cmm_decoder_N_23_1) + ); + defparam com_cmm_u_cmm_decoder_bar2_eq_raddr_3_0_I_104.INIT = 8'h6C; + LUT3 com_cmm_u_cmm_decoder_bar2_eq_raddr_3_0_I_104 ( + .I0(cfg_cfg_6102[155]), + .I1(com_cmm_bar2_reg[27]), + .I2(com_cmmt_raddr[59]), + .O(com_cmm_u_cmm_decoder_N_22_1) + ); + defparam com_cmm_u_cmm_decoder_bar2_eq_raddr_3_0_I_96.INIT = 8'h6C; + LUT3 com_cmm_u_cmm_decoder_bar2_eq_raddr_3_0_I_96 ( + .I0(cfg_cfg_6102[134]), + .I1(com_cmm_bar2_reg[6]), + .I2(com_cmmt_raddr[38]), + .O(com_cmm_u_cmm_decoder_N_31_1) + ); + defparam com_cmm_u_cmm_decoder_bar2_eq_raddr_3_0_I_95.INIT = 8'h6C; + LUT3 com_cmm_u_cmm_decoder_bar2_eq_raddr_3_0_I_95 ( + .I0(cfg_cfg_6102[135]), + .I1(com_cmm_bar2_reg[7]), + .I2(com_cmmt_raddr[39]), + .O(com_cmm_u_cmm_decoder_N_30_1) + ); + defparam com_cmm_u_cmm_decoder_bar2_eq_raddr_3_0_I_87.INIT = 8'h6C; + LUT3 com_cmm_u_cmm_decoder_bar2_eq_raddr_3_0_I_87 ( + .I0(cfg_cfg_6102[144]), + .I1(com_cmm_bar2_reg[16]), + .I2(com_cmmt_raddr[48]), + .O(com_cmm_u_cmm_decoder_N_39_1) + ); + defparam com_cmm_u_cmm_decoder_bar2_eq_raddr_3_0_I_78.INIT = 8'h6C; + LUT3 com_cmm_u_cmm_decoder_bar2_eq_raddr_3_0_I_78 ( + .I0(cfg_cfg_6102[148]), + .I1(com_cmm_bar2_reg[20]), + .I2(com_cmmt_raddr[52]), + .O(com_cmm_u_cmm_decoder_N_47_1) + ); + defparam com_cmm_u_cmm_decoder_bar2_eq_raddr_3_0_I_77.INIT = 8'h6C; + LUT3 com_cmm_u_cmm_decoder_bar2_eq_raddr_3_0_I_77 ( + .I0(cfg_cfg_6102[149]), + .I1(com_cmm_bar2_reg[21]), + .I2(com_cmmt_raddr[53]), + .O(com_cmm_u_cmm_decoder_N_46_1) + ); + defparam com_cmm_u_cmm_decoder_bar2_eq_raddr_3_0_I_68.INIT = 8'h6C; + LUT3 com_cmm_u_cmm_decoder_bar2_eq_raddr_3_0_I_68 ( + .I0(cfg_cfg_6102[147]), + .I1(com_cmm_bar2_reg[19]), + .I2(com_cmmt_raddr[51]), + .O(com_cmm_u_cmm_decoder_N_54_1) + ); + defparam com_cmm_u_cmm_decoder_bar2_eq_raddr_3_0_I_60.INIT = 8'h6C; + LUT3 com_cmm_u_cmm_decoder_bar2_eq_raddr_3_0_I_60 ( + .I0(cfg_cfg_6102[142]), + .I1(com_cmm_bar2_reg[14]), + .I2(com_cmmt_raddr[46]), + .O(com_cmm_u_cmm_decoder_N_63_1) + ); + defparam com_cmm_u_cmm_decoder_bar2_eq_raddr_3_0_I_59.INIT = 8'h6C; + LUT3 com_cmm_u_cmm_decoder_bar2_eq_raddr_3_0_I_59 ( + .I0(cfg_cfg_6102[143]), + .I1(com_cmm_bar2_reg[15]), + .I2(com_cmmt_raddr[47]), + .O(com_cmm_u_cmm_decoder_N_62_1) + ); + defparam com_cmm_u_cmm_decoder_bar2_eq_raddr_3_0_I_50.INIT = 8'h6C; + LUT3 com_cmm_u_cmm_decoder_bar2_eq_raddr_3_0_I_50 ( + .I0(cfg_cfg_6102[153]), + .I1(com_cmm_bar2_reg[25]), + .I2(com_cmmt_raddr[57]), + .O(com_cmm_u_cmm_decoder_N_70_1) + ); + defparam com_cmm_u_cmm_decoder_bar2_eq_raddr_3_0_I_41.INIT = 8'h6C; + LUT3 com_cmm_u_cmm_decoder_bar2_eq_raddr_3_0_I_41 ( + .I0(cfg_cfg_6102[141]), + .I1(com_cmm_bar2_reg[13]), + .I2(com_cmmt_raddr[45]), + .O(com_cmm_u_cmm_decoder_N_78_0) + ); + defparam com_cmm_u_cmm_decoder_bar2_eq_raddr_3_0_I_32.INIT = 8'h6C; + LUT3 com_cmm_u_cmm_decoder_bar2_eq_raddr_3_0_I_32 ( + .I0(cfg_cfg_6102[139]), + .I1(com_cmm_bar2_reg[11]), + .I2(com_cmmt_raddr[43]), + .O(com_cmm_u_cmm_decoder_N_86_0) + ); + defparam com_cmm_u_cmm_decoder_bar2_eq_raddr_3_0_I_23.INIT = 8'h6C; + LUT3 com_cmm_u_cmm_decoder_bar2_eq_raddr_3_0_I_23 ( + .I0(cfg_cfg_6102[151]), + .I1(com_cmm_bar2_reg[23]), + .I2(com_cmmt_raddr[55]), + .O(com_cmm_u_cmm_decoder_N_94_1) + ); + defparam com_cmm_u_cmm_decoder_bar2_eq_raddr_3_0_I_14.INIT = 8'h6C; + LUT3 com_cmm_u_cmm_decoder_bar2_eq_raddr_3_0_I_14 ( + .I0(cfg_cfg_6102[159]), + .I1(com_cmm_bar2_reg[31]), + .I2(com_cmmt_raddr[63]), + .O(com_cmm_u_cmm_decoder_N_102_1) + ); + defparam com_cmm_u_cmm_decoder_bar2_eq_raddr_3_0_I_6.INIT = 8'h6C; + LUT3 com_cmm_u_cmm_decoder_bar2_eq_raddr_3_0_I_6 ( + .I0(cfg_cfg_6102[132]), + .I1(com_cmm_bar2_reg[4]), + .I2(com_cmmt_raddr[36]), + .O(com_cmm_u_cmm_decoder_N_111_1) + ); + defparam com_cmm_u_cmm_decoder_bar1_eq_raddr_3_0_I_123.INIT = 8'h6C; + LUT3 com_cmm_u_cmm_decoder_bar1_eq_raddr_3_0_I_123 ( + .I0(cfg_cfg_6102[104]), + .I1(com_cmm_bar1_reg[8]), + .I2(com_cmmt_raddr[40]), + .O(com_cmm_u_cmm_decoder_N_7_2) + ); + defparam com_cmm_u_cmm_decoder_bar1_eq_raddr_3_0_I_122.INIT = 8'h6C; + LUT3 com_cmm_u_cmm_decoder_bar1_eq_raddr_3_0_I_122 ( + .I0(cfg_cfg_6102[105]), + .I1(com_cmm_bar1_reg[9]), + .I2(com_cmmt_raddr[41]), + .O(com_cmm_u_cmm_decoder_N_6_2) + ); + defparam com_cmm_u_cmm_decoder_bar1_eq_raddr_3_0_I_113.INIT = 8'h6C; + LUT3 com_cmm_u_cmm_decoder_bar1_eq_raddr_3_0_I_113 ( + .I0(cfg_cfg_6102[125]), + .I1(com_cmm_bar1_reg[29]), + .I2(com_cmmt_raddr[61]), + .O(com_cmm_u_cmm_decoder_N_14_3) + ); + defparam com_cmm_u_cmm_decoder_bar1_eq_raddr_3_0_I_105.INIT = 8'h6C; + LUT3 com_cmm_u_cmm_decoder_bar1_eq_raddr_3_0_I_105 ( + .I0(cfg_cfg_6102[122]), + .I1(com_cmm_bar1_reg[26]), + .I2(com_cmmt_raddr[58]), + .O(com_cmm_u_cmm_decoder_N_23_2) + ); + defparam com_cmm_u_cmm_decoder_bar1_eq_raddr_3_0_I_104.INIT = 8'h6C; + LUT3 com_cmm_u_cmm_decoder_bar1_eq_raddr_3_0_I_104 ( + .I0(cfg_cfg_6102[123]), + .I1(com_cmm_bar1_reg[27]), + .I2(com_cmmt_raddr[59]), + .O(com_cmm_u_cmm_decoder_N_22_2) + ); + defparam com_cmm_u_cmm_decoder_bar1_eq_raddr_3_0_I_95.INIT = 8'h6C; + LUT3 com_cmm_u_cmm_decoder_bar1_eq_raddr_3_0_I_95 ( + .I0(cfg_cfg_6102[103]), + .I1(com_cmm_bar1_reg[7]), + .I2(com_cmmt_raddr[39]), + .O(com_cmm_u_cmm_decoder_N_30_2) + ); + defparam com_cmm_u_cmm_decoder_bar1_eq_raddr_3_0_I_87.INIT = 8'h6C; + LUT3 com_cmm_u_cmm_decoder_bar1_eq_raddr_3_0_I_87 ( + .I0(cfg_cfg_6102[112]), + .I1(com_cmm_bar1_reg[16]), + .I2(com_cmmt_raddr[48]), + .O(com_cmm_u_cmm_decoder_N_39_2) + ); + defparam com_cmm_u_cmm_decoder_bar1_eq_raddr_3_0_I_77.INIT = 8'h6C; + LUT3 com_cmm_u_cmm_decoder_bar1_eq_raddr_3_0_I_77 ( + .I0(cfg_cfg_6102[117]), + .I1(com_cmm_bar1_reg[21]), + .I2(com_cmmt_raddr[53]), + .O(com_cmm_u_cmm_decoder_N_46_2) + ); + defparam com_cmm_u_cmm_decoder_bar1_eq_raddr_3_0_I_68.INIT = 8'h6C; + LUT3 com_cmm_u_cmm_decoder_bar1_eq_raddr_3_0_I_68 ( + .I0(cfg_cfg_6102[115]), + .I1(com_cmm_bar1_reg[19]), + .I2(com_cmmt_raddr[51]), + .O(com_cmm_u_cmm_decoder_N_54_2) + ); + defparam com_cmm_u_cmm_decoder_bar1_eq_raddr_3_0_I_60.INIT = 8'h6C; + LUT3 com_cmm_u_cmm_decoder_bar1_eq_raddr_3_0_I_60 ( + .I0(cfg_cfg_6102[110]), + .I1(com_cmm_bar1_reg[14]), + .I2(com_cmmt_raddr[46]), + .O(com_cmm_u_cmm_decoder_N_63_2) + ); + defparam com_cmm_u_cmm_decoder_bar1_eq_raddr_3_0_I_59.INIT = 8'h6C; + LUT3 com_cmm_u_cmm_decoder_bar1_eq_raddr_3_0_I_59 ( + .I0(cfg_cfg_6102[111]), + .I1(com_cmm_bar1_reg[15]), + .I2(com_cmmt_raddr[47]), + .O(com_cmm_u_cmm_decoder_N_62_2) + ); + defparam com_cmm_u_cmm_decoder_bar1_eq_raddr_3_0_I_50.INIT = 8'h6C; + LUT3 com_cmm_u_cmm_decoder_bar1_eq_raddr_3_0_I_50 ( + .I0(cfg_cfg_6102[121]), + .I1(com_cmm_bar1_reg[25]), + .I2(com_cmmt_raddr[57]), + .O(com_cmm_u_cmm_decoder_N_70_2) + ); + defparam com_cmm_u_cmm_decoder_bar1_eq_raddr_3_0_I_41.INIT = 8'h6C; + LUT3 com_cmm_u_cmm_decoder_bar1_eq_raddr_3_0_I_41 ( + .I0(cfg_cfg_6102[109]), + .I1(com_cmm_bar1_reg[13]), + .I2(com_cmmt_raddr[45]), + .O(com_cmm_u_cmm_decoder_N_78_1) + ); + defparam com_cmm_u_cmm_decoder_bar1_eq_raddr_3_0_I_32.INIT = 8'h6C; + LUT3 com_cmm_u_cmm_decoder_bar1_eq_raddr_3_0_I_32 ( + .I0(cfg_cfg_6102[107]), + .I1(com_cmm_bar1_reg[11]), + .I2(com_cmmt_raddr[43]), + .O(com_cmm_u_cmm_decoder_N_86_1) + ); + defparam com_cmm_u_cmm_decoder_bar1_eq_raddr_3_0_I_23.INIT = 8'h6C; + LUT3 com_cmm_u_cmm_decoder_bar1_eq_raddr_3_0_I_23 ( + .I0(cfg_cfg_6102[119]), + .I1(com_cmm_bar1_reg[23]), + .I2(com_cmmt_raddr[55]), + .O(com_cmm_u_cmm_decoder_N_94_2) + ); + defparam com_cmm_u_cmm_decoder_bar1_eq_raddr_3_0_I_14.INIT = 8'h6C; + LUT3 com_cmm_u_cmm_decoder_bar1_eq_raddr_3_0_I_14 ( + .I0(cfg_cfg_6102[127]), + .I1(com_cmm_bar1_reg[31]), + .I2(com_cmmt_raddr[63]), + .O(com_cmm_u_cmm_decoder_N_102_2) + ); + defparam com_cmm_u_cmm_decoder_bar1_eq_raddr_3_0_I_6.INIT = 8'h6C; + LUT3 com_cmm_u_cmm_decoder_bar1_eq_raddr_3_0_I_6 ( + .I0(cfg_cfg_6102[100]), + .I1(com_cmm_bar1_reg[4]), + .I2(com_cmmt_raddr[36]), + .O(com_cmm_u_cmm_decoder_N_111_2) + ); + defparam com_cmm_u_cmm_decoder_bar1_eq_raddr_3_0_I_5.INIT = 8'h6C; + LUT3 com_cmm_u_cmm_decoder_bar1_eq_raddr_3_0_I_5 ( + .I0(cfg_cfg_6102[101]), + .I1(com_cmm_bar1_reg[5]), + .I2(com_cmmt_raddr[37]), + .O(com_cmm_u_cmm_decoder_N_110_0) + ); + defparam com_cmm_u_cmm_decoder_bar0_eq_raddr_3_0_I_122.INIT = 8'h6C; + LUT3_L com_cmm_u_cmm_decoder_bar0_eq_raddr_3_0_I_122 ( + .I0(cfg_cfg_6102[73]), + .I1(com_cmm_bar0_reg_9_), + .I2(com_cmmt_raddr[41]), + .LO(com_cmm_u_cmm_decoder_N_6_8) + ); + defparam com_cmm_u_cmm_decoder_bar0_eq_raddr_3_0_I_113.INIT = 8'h6C; + LUT3_L com_cmm_u_cmm_decoder_bar0_eq_raddr_3_0_I_113 ( + .I0(cfg_cfg_6102[93]), + .I1(com_cmm_bar0_reg_29_), + .I2(com_cmmt_raddr[61]), + .LO(com_cmm_u_cmm_decoder_N_14_9) + ); + defparam com_cmm_u_cmm_decoder_bar0_eq_raddr_3_0_I_104.INIT = 8'h6C; + LUT3_L com_cmm_u_cmm_decoder_bar0_eq_raddr_3_0_I_104 ( + .I0(cfg_cfg_6102[91]), + .I1(com_cmm_bar0_reg_27_), + .I2(com_cmmt_raddr[59]), + .LO(com_cmm_u_cmm_decoder_N_22_8) + ); + defparam com_cmm_u_cmm_decoder_bar0_eq_raddr_3_0_I_95.INIT = 8'h6C; + LUT3_L com_cmm_u_cmm_decoder_bar0_eq_raddr_3_0_I_95 ( + .I0(cfg_cfg_6102[71]), + .I1(com_cmm_bar0_reg_7_), + .I2(com_cmmt_raddr[39]), + .LO(com_cmm_u_cmm_decoder_N_30_8) + ); + defparam com_cmm_u_cmm_decoder_bar0_eq_raddr_3_0_I_86.INIT = 8'h6C; + LUT3_L com_cmm_u_cmm_decoder_bar0_eq_raddr_3_0_I_86 ( + .I0(cfg_cfg_6102[81]), + .I1(com_cmm_bar0_reg_17_), + .I2(com_cmmt_raddr[49]), + .LO(com_cmm_u_cmm_decoder_N_38_8) + ); + defparam com_cmm_u_cmm_decoder_bar0_eq_raddr_3_0_I_77.INIT = 8'h6C; + LUT3_L com_cmm_u_cmm_decoder_bar0_eq_raddr_3_0_I_77 ( + .I0(cfg_cfg_6102[85]), + .I1(com_cmm_bar0_reg_21_), + .I2(com_cmmt_raddr[53]), + .LO(com_cmm_u_cmm_decoder_N_46_8) + ); + defparam com_cmm_u_cmm_decoder_bar0_eq_raddr_3_0_I_68.INIT = 8'h6C; + LUT3_L com_cmm_u_cmm_decoder_bar0_eq_raddr_3_0_I_68 ( + .I0(cfg_cfg_6102[83]), + .I1(com_cmm_bar0_reg_19_), + .I2(com_cmmt_raddr[51]), + .LO(com_cmm_u_cmm_decoder_N_54_8) + ); + defparam com_cmm_u_cmm_decoder_bar0_eq_raddr_3_0_I_59.INIT = 8'h6C; + LUT3_L com_cmm_u_cmm_decoder_bar0_eq_raddr_3_0_I_59 ( + .I0(cfg_cfg_6102[79]), + .I1(com_cmm_bar0_reg_15_), + .I2(com_cmmt_raddr[47]), + .LO(com_cmm_u_cmm_decoder_N_62_8) + ); + defparam com_cmm_u_cmm_decoder_bar0_eq_raddr_3_0_I_50.INIT = 8'h6C; + LUT3_L com_cmm_u_cmm_decoder_bar0_eq_raddr_3_0_I_50 ( + .I0(cfg_cfg_6102[89]), + .I1(com_cmm_bar0_reg_25_), + .I2(com_cmmt_raddr[57]), + .LO(com_cmm_u_cmm_decoder_N_70_8) + ); + defparam com_cmm_u_cmm_decoder_bar0_eq_raddr_3_0_I_41.INIT = 8'h6C; + LUT3_L com_cmm_u_cmm_decoder_bar0_eq_raddr_3_0_I_41 ( + .I0(cfg_cfg_6102[77]), + .I1(com_cmm_bar0_reg_13_), + .I2(com_cmmt_raddr[45]), + .LO(com_cmm_u_cmm_decoder_N_78_7) + ); + defparam com_cmm_u_cmm_decoder_bar0_eq_raddr_3_0_I_32.INIT = 8'h6C; + LUT3_L com_cmm_u_cmm_decoder_bar0_eq_raddr_3_0_I_32 ( + .I0(cfg_cfg_6102[75]), + .I1(com_cmm_bar0_reg_11_), + .I2(com_cmmt_raddr[43]), + .LO(com_cmm_u_cmm_decoder_N_86_7) + ); + defparam com_cmm_u_cmm_decoder_bar0_eq_raddr_3_0_I_23.INIT = 8'h6C; + LUT3_L com_cmm_u_cmm_decoder_bar0_eq_raddr_3_0_I_23 ( + .I0(cfg_cfg_6102[87]), + .I1(com_cmm_bar0_reg_23_), + .I2(com_cmmt_raddr[55]), + .LO(com_cmm_u_cmm_decoder_N_94_8) + ); + defparam com_cmm_u_cmm_decoder_bar0_eq_raddr_3_0_I_14.INIT = 8'h6C; + LUT3_L com_cmm_u_cmm_decoder_bar0_eq_raddr_3_0_I_14 ( + .I0(cfg_cfg_6102[95]), + .I1(com_cmm_bar0_reg_31_), + .I2(com_cmmt_raddr[63]), + .LO(com_cmm_u_cmm_decoder_N_102_3) + ); + defparam com_cmm_u_cmm_decoder_bar0_eq_raddr_3_0_I_5.INIT = 8'h6C; + LUT3_L com_cmm_u_cmm_decoder_bar0_eq_raddr_3_0_I_5 ( + .I0(cfg_cfg_6102[69]), + .I1(com_cmm_bar0_reg_5_), + .I2(com_cmmt_raddr[37]), + .LO(com_cmm_u_cmm_decoder_N_110_6) + ); + defparam com_cmm_u_cmm_decoder_un9_bar45_64_hit_high_0_I_122.INIT = 8'h6C; + LUT3_L com_cmm_u_cmm_decoder_un9_bar45_64_hit_high_0_I_122 ( + .I0(cfg_cfg_6102[201]), + .I1(com_cmm_bar4_reg[9]), + .I2(com_cmmt_raddr[9]), + .LO(com_cmm_u_cmm_decoder_N_6_7) + ); + defparam com_cmm_u_cmm_decoder_un9_bar45_64_hit_high_0_I_113.INIT = 8'h6C; + LUT3_L com_cmm_u_cmm_decoder_un9_bar45_64_hit_high_0_I_113 ( + .I0(cfg_cfg_6102[221]), + .I1(com_cmm_bar4_reg[29]), + .I2(com_cmmt_raddr[29]), + .LO(com_cmm_u_cmm_decoder_N_14_8) + ); + defparam com_cmm_u_cmm_decoder_un9_bar45_64_hit_high_0_I_104.INIT = 8'h6C; + LUT3_L com_cmm_u_cmm_decoder_un9_bar45_64_hit_high_0_I_104 ( + .I0(cfg_cfg_6102[219]), + .I1(com_cmm_bar4_reg[27]), + .I2(com_cmmt_raddr[27]), + .LO(com_cmm_u_cmm_decoder_N_22_7) + ); + defparam com_cmm_u_cmm_decoder_un9_bar45_64_hit_high_0_I_95.INIT = 8'h6C; + LUT3_L com_cmm_u_cmm_decoder_un9_bar45_64_hit_high_0_I_95 ( + .I0(cfg_cfg_6102[199]), + .I1(com_cmm_bar4_reg[7]), + .I2(com_cmmt_raddr[7]), + .LO(com_cmm_u_cmm_decoder_N_30_7) + ); + defparam com_cmm_u_cmm_decoder_un9_bar45_64_hit_high_0_I_77.INIT = 8'h6C; + LUT3_L com_cmm_u_cmm_decoder_un9_bar45_64_hit_high_0_I_77 ( + .I0(cfg_cfg_6102[213]), + .I1(com_cmm_bar4_reg[21]), + .I2(com_cmmt_raddr[21]), + .LO(com_cmm_u_cmm_decoder_N_46_7) + ); + defparam com_cmm_u_cmm_decoder_un9_bar45_64_hit_high_0_I_68.INIT = 8'h6C; + LUT3_L com_cmm_u_cmm_decoder_un9_bar45_64_hit_high_0_I_68 ( + .I0(cfg_cfg_6102[211]), + .I1(com_cmm_bar4_reg[19]), + .I2(com_cmmt_raddr[19]), + .LO(com_cmm_u_cmm_decoder_N_54_7) + ); + defparam com_cmm_u_cmm_decoder_un9_bar45_64_hit_high_0_I_59.INIT = 8'h6C; + LUT3_L com_cmm_u_cmm_decoder_un9_bar45_64_hit_high_0_I_59 ( + .I0(cfg_cfg_6102[207]), + .I1(com_cmm_bar4_reg[15]), + .I2(com_cmmt_raddr[15]), + .LO(com_cmm_u_cmm_decoder_N_62_7) + ); + defparam com_cmm_u_cmm_decoder_un9_bar45_64_hit_high_0_I_50.INIT = 8'h6C; + LUT3_L com_cmm_u_cmm_decoder_un9_bar45_64_hit_high_0_I_50 ( + .I0(cfg_cfg_6102[217]), + .I1(com_cmm_bar4_reg[25]), + .I2(com_cmmt_raddr[25]), + .LO(com_cmm_u_cmm_decoder_N_70_7) + ); + defparam com_cmm_u_cmm_decoder_un9_bar45_64_hit_high_0_I_41.INIT = 8'h6C; + LUT3_L com_cmm_u_cmm_decoder_un9_bar45_64_hit_high_0_I_41 ( + .I0(cfg_cfg_6102[205]), + .I1(com_cmm_bar4_reg[13]), + .I2(com_cmmt_raddr[13]), + .LO(com_cmm_u_cmm_decoder_N_78_6) + ); + defparam com_cmm_u_cmm_decoder_un9_bar45_64_hit_high_0_I_32.INIT = 8'h6C; + LUT3_L com_cmm_u_cmm_decoder_un9_bar45_64_hit_high_0_I_32 ( + .I0(cfg_cfg_6102[203]), + .I1(com_cmm_bar4_reg[11]), + .I2(com_cmmt_raddr[11]), + .LO(com_cmm_u_cmm_decoder_N_86_6) + ); + defparam com_cmm_u_cmm_decoder_un9_bar45_64_hit_high_0_I_23.INIT = 8'h6C; + LUT3_L com_cmm_u_cmm_decoder_un9_bar45_64_hit_high_0_I_23 ( + .I0(cfg_cfg_6102[215]), + .I1(com_cmm_bar4_reg[23]), + .I2(com_cmmt_raddr[23]), + .LO(com_cmm_u_cmm_decoder_N_94_7) + ); + defparam com_cmm_u_cmm_decoder_un9_bar45_64_hit_high_0_I_14.INIT = 8'h6C; + LUT3_L com_cmm_u_cmm_decoder_un9_bar45_64_hit_high_0_I_14 ( + .I0(cfg_cfg_6102[223]), + .I1(com_cmm_bar4_reg[31]), + .I2(com_cmmt_raddr[31]), + .LO(com_cmm_u_cmm_decoder_N_102_4) + ); + defparam com_cmm_u_cmm_decoder_un9_bar45_64_hit_high_0_I_5.INIT = 8'h6C; + LUT3_L com_cmm_u_cmm_decoder_un9_bar45_64_hit_high_0_I_5 ( + .I0(cfg_cfg_6102[197]), + .I1(com_cmm_bar4_reg[5]), + .I2(com_cmmt_raddr[5]), + .LO(com_cmm_u_cmm_decoder_N_110_5) + ); + defparam com_cmm_u_cmm_decoder_un9_bar34_64_hit_high_0_I_122.INIT = 8'h6C; + LUT3_L com_cmm_u_cmm_decoder_un9_bar34_64_hit_high_0_I_122 ( + .I0(cfg_cfg_6102[169]), + .I1(com_cmm_bar3_reg[9]), + .I2(com_cmmt_raddr[9]), + .LO(com_cmm_u_cmm_decoder_N_6_6) + ); + defparam com_cmm_u_cmm_decoder_un9_bar34_64_hit_high_0_I_113.INIT = 8'h6C; + LUT3_L com_cmm_u_cmm_decoder_un9_bar34_64_hit_high_0_I_113 ( + .I0(cfg_cfg_6102[189]), + .I1(com_cmm_bar3_reg[29]), + .I2(com_cmmt_raddr[29]), + .LO(com_cmm_u_cmm_decoder_N_14_7) + ); + defparam com_cmm_u_cmm_decoder_un9_bar34_64_hit_high_0_I_104.INIT = 8'h6C; + LUT3_L com_cmm_u_cmm_decoder_un9_bar34_64_hit_high_0_I_104 ( + .I0(cfg_cfg_6102[187]), + .I1(com_cmm_bar3_reg[27]), + .I2(com_cmmt_raddr[27]), + .LO(com_cmm_u_cmm_decoder_N_22_6) + ); + defparam com_cmm_u_cmm_decoder_un9_bar34_64_hit_high_0_I_95.INIT = 8'h6C; + LUT3_L com_cmm_u_cmm_decoder_un9_bar34_64_hit_high_0_I_95 ( + .I0(cfg_cfg_6102[167]), + .I1(com_cmm_bar3_reg[7]), + .I2(com_cmmt_raddr[7]), + .LO(com_cmm_u_cmm_decoder_N_30_6) + ); + defparam com_cmm_u_cmm_decoder_un9_bar34_64_hit_high_0_I_86.INIT = 8'h6C; + LUT3_L com_cmm_u_cmm_decoder_un9_bar34_64_hit_high_0_I_86 ( + .I0(cfg_cfg_6102[177]), + .I1(com_cmm_bar3_reg[17]), + .I2(com_cmmt_raddr[17]), + .LO(com_cmm_u_cmm_decoder_N_38_6) + ); + defparam com_cmm_u_cmm_decoder_un9_bar34_64_hit_high_0_I_77.INIT = 8'h6C; + LUT3_L com_cmm_u_cmm_decoder_un9_bar34_64_hit_high_0_I_77 ( + .I0(cfg_cfg_6102[181]), + .I1(com_cmm_bar3_reg[21]), + .I2(com_cmmt_raddr[21]), + .LO(com_cmm_u_cmm_decoder_N_46_6) + ); + defparam com_cmm_u_cmm_decoder_un9_bar34_64_hit_high_0_I_68.INIT = 8'h6C; + LUT3_L com_cmm_u_cmm_decoder_un9_bar34_64_hit_high_0_I_68 ( + .I0(cfg_cfg_6102[179]), + .I1(com_cmm_bar3_reg[19]), + .I2(com_cmmt_raddr[19]), + .LO(com_cmm_u_cmm_decoder_N_54_6) + ); + defparam com_cmm_u_cmm_decoder_un9_bar34_64_hit_high_0_I_59.INIT = 8'h6C; + LUT3_L com_cmm_u_cmm_decoder_un9_bar34_64_hit_high_0_I_59 ( + .I0(cfg_cfg_6102[175]), + .I1(com_cmm_bar3_reg[15]), + .I2(com_cmmt_raddr[15]), + .LO(com_cmm_u_cmm_decoder_N_62_6) + ); + defparam com_cmm_u_cmm_decoder_un9_bar34_64_hit_high_0_I_50.INIT = 8'h6C; + LUT3_L com_cmm_u_cmm_decoder_un9_bar34_64_hit_high_0_I_50 ( + .I0(cfg_cfg_6102[185]), + .I1(com_cmm_bar3_reg[25]), + .I2(com_cmmt_raddr[25]), + .LO(com_cmm_u_cmm_decoder_N_70_6) + ); + defparam com_cmm_u_cmm_decoder_un9_bar34_64_hit_high_0_I_41.INIT = 8'h6C; + LUT3_L com_cmm_u_cmm_decoder_un9_bar34_64_hit_high_0_I_41 ( + .I0(cfg_cfg_6102[173]), + .I1(com_cmm_bar3_reg[13]), + .I2(com_cmmt_raddr[13]), + .LO(com_cmm_u_cmm_decoder_N_78_5) + ); + defparam com_cmm_u_cmm_decoder_un9_bar34_64_hit_high_0_I_32.INIT = 8'h6C; + LUT3_L com_cmm_u_cmm_decoder_un9_bar34_64_hit_high_0_I_32 ( + .I0(cfg_cfg_6102[171]), + .I1(com_cmm_bar3_reg[11]), + .I2(com_cmmt_raddr[11]), + .LO(com_cmm_u_cmm_decoder_N_86_5) + ); + defparam com_cmm_u_cmm_decoder_un9_bar34_64_hit_high_0_I_23.INIT = 8'h6C; + LUT3_L com_cmm_u_cmm_decoder_un9_bar34_64_hit_high_0_I_23 ( + .I0(cfg_cfg_6102[183]), + .I1(com_cmm_bar3_reg[23]), + .I2(com_cmmt_raddr[23]), + .LO(com_cmm_u_cmm_decoder_N_94_6) + ); + defparam com_cmm_u_cmm_decoder_un9_bar34_64_hit_high_0_I_14.INIT = 8'h6C; + LUT3_L com_cmm_u_cmm_decoder_un9_bar34_64_hit_high_0_I_14 ( + .I0(cfg_cfg_6102[191]), + .I1(com_cmm_bar3_reg[31]), + .I2(com_cmmt_raddr[31]), + .LO(com_cmm_u_cmm_decoder_N_102_5) + ); + defparam com_cmm_u_cmm_decoder_un9_bar34_64_hit_high_0_I_5.INIT = 8'h6C; + LUT3_L com_cmm_u_cmm_decoder_un9_bar34_64_hit_high_0_I_5 ( + .I0(cfg_cfg_6102[165]), + .I1(com_cmm_bar3_reg[5]), + .I2(com_cmmt_raddr[5]), + .LO(com_cmm_u_cmm_decoder_N_110_4) + ); + defparam com_cmm_u_cmm_decoder_un9_bar23_64_hit_high_0_I_122.INIT = 8'h6C; + LUT3_L com_cmm_u_cmm_decoder_un9_bar23_64_hit_high_0_I_122 ( + .I0(cfg_cfg_6102[137]), + .I1(com_cmm_bar2_reg[9]), + .I2(com_cmmt_raddr[9]), + .LO(com_cmm_u_cmm_decoder_N_6_5) + ); + defparam com_cmm_u_cmm_decoder_un9_bar23_64_hit_high_0_I_113.INIT = 8'h6C; + LUT3_L com_cmm_u_cmm_decoder_un9_bar23_64_hit_high_0_I_113 ( + .I0(cfg_cfg_6102[157]), + .I1(com_cmm_bar2_reg[29]), + .I2(com_cmmt_raddr[29]), + .LO(com_cmm_u_cmm_decoder_N_14_6) + ); + defparam com_cmm_u_cmm_decoder_un9_bar23_64_hit_high_0_I_104.INIT = 8'h6C; + LUT3_L com_cmm_u_cmm_decoder_un9_bar23_64_hit_high_0_I_104 ( + .I0(cfg_cfg_6102[155]), + .I1(com_cmm_bar2_reg[27]), + .I2(com_cmmt_raddr[27]), + .LO(com_cmm_u_cmm_decoder_N_22_5) + ); + defparam com_cmm_u_cmm_decoder_un9_bar23_64_hit_high_0_I_86.INIT = 8'h6C; + LUT3_L com_cmm_u_cmm_decoder_un9_bar23_64_hit_high_0_I_86 ( + .I0(cfg_cfg_6102[145]), + .I1(com_cmm_bar2_reg[17]), + .I2(com_cmmt_raddr[17]), + .LO(com_cmm_u_cmm_decoder_N_38_5) + ); + defparam com_cmm_u_cmm_decoder_un9_bar23_64_hit_high_0_I_77.INIT = 8'h6C; + LUT3_L com_cmm_u_cmm_decoder_un9_bar23_64_hit_high_0_I_77 ( + .I0(cfg_cfg_6102[149]), + .I1(com_cmm_bar2_reg[21]), + .I2(com_cmmt_raddr[21]), + .LO(com_cmm_u_cmm_decoder_N_46_5) + ); + defparam com_cmm_u_cmm_decoder_un9_bar23_64_hit_high_0_I_68.INIT = 8'h6C; + LUT3_L com_cmm_u_cmm_decoder_un9_bar23_64_hit_high_0_I_68 ( + .I0(cfg_cfg_6102[147]), + .I1(com_cmm_bar2_reg[19]), + .I2(com_cmmt_raddr[19]), + .LO(com_cmm_u_cmm_decoder_N_54_5) + ); + defparam com_cmm_u_cmm_decoder_un9_bar23_64_hit_high_0_I_59.INIT = 8'h6C; + LUT3_L com_cmm_u_cmm_decoder_un9_bar23_64_hit_high_0_I_59 ( + .I0(cfg_cfg_6102[143]), + .I1(com_cmm_bar2_reg[15]), + .I2(com_cmmt_raddr[15]), + .LO(com_cmm_u_cmm_decoder_N_62_5) + ); + defparam com_cmm_u_cmm_decoder_un9_bar23_64_hit_high_0_I_50.INIT = 8'h6C; + LUT3_L com_cmm_u_cmm_decoder_un9_bar23_64_hit_high_0_I_50 ( + .I0(cfg_cfg_6102[153]), + .I1(com_cmm_bar2_reg[25]), + .I2(com_cmmt_raddr[25]), + .LO(com_cmm_u_cmm_decoder_N_70_5) + ); + defparam com_cmm_u_cmm_decoder_un9_bar23_64_hit_high_0_I_41.INIT = 8'h6C; + LUT3_L com_cmm_u_cmm_decoder_un9_bar23_64_hit_high_0_I_41 ( + .I0(cfg_cfg_6102[141]), + .I1(com_cmm_bar2_reg[13]), + .I2(com_cmmt_raddr[13]), + .LO(com_cmm_u_cmm_decoder_N_78_4) + ); + defparam com_cmm_u_cmm_decoder_un9_bar23_64_hit_high_0_I_32.INIT = 8'h6C; + LUT3_L com_cmm_u_cmm_decoder_un9_bar23_64_hit_high_0_I_32 ( + .I0(cfg_cfg_6102[139]), + .I1(com_cmm_bar2_reg[11]), + .I2(com_cmmt_raddr[11]), + .LO(com_cmm_u_cmm_decoder_N_86_4) + ); + defparam com_cmm_u_cmm_decoder_un9_bar23_64_hit_high_0_I_23.INIT = 8'h6C; + LUT3_L com_cmm_u_cmm_decoder_un9_bar23_64_hit_high_0_I_23 ( + .I0(cfg_cfg_6102[151]), + .I1(com_cmm_bar2_reg[23]), + .I2(com_cmmt_raddr[23]), + .LO(com_cmm_u_cmm_decoder_N_94_5) + ); + defparam com_cmm_u_cmm_decoder_un9_bar23_64_hit_high_0_I_14.INIT = 8'h6C; + LUT3_L com_cmm_u_cmm_decoder_un9_bar23_64_hit_high_0_I_14 ( + .I0(cfg_cfg_6102[159]), + .I1(com_cmm_bar2_reg[31]), + .I2(com_cmmt_raddr[31]), + .LO(com_cmm_u_cmm_decoder_N_102_6) + ); + defparam com_cmm_u_cmm_decoder_un9_bar23_64_hit_high_0_I_5.INIT = 8'h6C; + LUT3_L com_cmm_u_cmm_decoder_un9_bar23_64_hit_high_0_I_5 ( + .I0(cfg_cfg_6102[133]), + .I1(com_cmm_bar2_reg[5]), + .I2(com_cmmt_raddr[5]), + .LO(com_cmm_u_cmm_decoder_N_110_3) + ); + defparam com_cmm_u_cmm_decoder_un9_bar12_64_hit_high_0_I_122.INIT = 8'h6C; + LUT3_L com_cmm_u_cmm_decoder_un9_bar12_64_hit_high_0_I_122 ( + .I0(cfg_cfg_6102[105]), + .I1(com_cmm_bar1_reg[9]), + .I2(com_cmmt_raddr[9]), + .LO(com_cmm_u_cmm_decoder_N_6_4) + ); + defparam com_cmm_u_cmm_decoder_un9_bar12_64_hit_high_0_I_113.INIT = 8'h6C; + LUT3_L com_cmm_u_cmm_decoder_un9_bar12_64_hit_high_0_I_113 ( + .I0(cfg_cfg_6102[125]), + .I1(com_cmm_bar1_reg[29]), + .I2(com_cmmt_raddr[29]), + .LO(com_cmm_u_cmm_decoder_N_14_5) + ); + defparam com_cmm_u_cmm_decoder_un9_bar12_64_hit_high_0_I_104.INIT = 8'h6C; + LUT3_L com_cmm_u_cmm_decoder_un9_bar12_64_hit_high_0_I_104 ( + .I0(cfg_cfg_6102[123]), + .I1(com_cmm_bar1_reg[27]), + .I2(com_cmmt_raddr[27]), + .LO(com_cmm_u_cmm_decoder_N_22_4) + ); + defparam com_cmm_u_cmm_decoder_un9_bar12_64_hit_high_0_I_95.INIT = 8'h6C; + LUT3_L com_cmm_u_cmm_decoder_un9_bar12_64_hit_high_0_I_95 ( + .I0(cfg_cfg_6102[103]), + .I1(com_cmm_bar1_reg[7]), + .I2(com_cmmt_raddr[7]), + .LO(com_cmm_u_cmm_decoder_N_30_4) + ); + defparam com_cmm_u_cmm_decoder_un9_bar12_64_hit_high_0_I_77.INIT = 8'h6C; + LUT3_L com_cmm_u_cmm_decoder_un9_bar12_64_hit_high_0_I_77 ( + .I0(cfg_cfg_6102[117]), + .I1(com_cmm_bar1_reg[21]), + .I2(com_cmmt_raddr[21]), + .LO(com_cmm_u_cmm_decoder_N_46_4) + ); + defparam com_cmm_u_cmm_decoder_un9_bar12_64_hit_high_0_I_68.INIT = 8'h6C; + LUT3_L com_cmm_u_cmm_decoder_un9_bar12_64_hit_high_0_I_68 ( + .I0(cfg_cfg_6102[115]), + .I1(com_cmm_bar1_reg[19]), + .I2(com_cmmt_raddr[19]), + .LO(com_cmm_u_cmm_decoder_N_54_4) + ); + defparam com_cmm_u_cmm_decoder_un9_bar12_64_hit_high_0_I_59.INIT = 8'h6C; + LUT3_L com_cmm_u_cmm_decoder_un9_bar12_64_hit_high_0_I_59 ( + .I0(cfg_cfg_6102[111]), + .I1(com_cmm_bar1_reg[15]), + .I2(com_cmmt_raddr[15]), + .LO(com_cmm_u_cmm_decoder_N_62_4) + ); + defparam com_cmm_u_cmm_decoder_un9_bar12_64_hit_high_0_I_50.INIT = 8'h6C; + LUT3_L com_cmm_u_cmm_decoder_un9_bar12_64_hit_high_0_I_50 ( + .I0(cfg_cfg_6102[121]), + .I1(com_cmm_bar1_reg[25]), + .I2(com_cmmt_raddr[25]), + .LO(com_cmm_u_cmm_decoder_N_70_4) + ); + defparam com_cmm_u_cmm_decoder_un9_bar12_64_hit_high_0_I_41.INIT = 8'h6C; + LUT3_L com_cmm_u_cmm_decoder_un9_bar12_64_hit_high_0_I_41 ( + .I0(cfg_cfg_6102[109]), + .I1(com_cmm_bar1_reg[13]), + .I2(com_cmmt_raddr[13]), + .LO(com_cmm_u_cmm_decoder_N_78_3) + ); + defparam com_cmm_u_cmm_decoder_un9_bar12_64_hit_high_0_I_32.INIT = 8'h6C; + LUT3_L com_cmm_u_cmm_decoder_un9_bar12_64_hit_high_0_I_32 ( + .I0(cfg_cfg_6102[107]), + .I1(com_cmm_bar1_reg[11]), + .I2(com_cmmt_raddr[11]), + .LO(com_cmm_u_cmm_decoder_N_86_3) + ); + defparam com_cmm_u_cmm_decoder_un9_bar12_64_hit_high_0_I_23.INIT = 8'h6C; + LUT3_L com_cmm_u_cmm_decoder_un9_bar12_64_hit_high_0_I_23 ( + .I0(cfg_cfg_6102[119]), + .I1(com_cmm_bar1_reg[23]), + .I2(com_cmmt_raddr[23]), + .LO(com_cmm_u_cmm_decoder_N_94_4) + ); + defparam com_cmm_u_cmm_decoder_un9_bar12_64_hit_high_0_I_14.INIT = 8'h6C; + LUT3_L com_cmm_u_cmm_decoder_un9_bar12_64_hit_high_0_I_14 ( + .I0(cfg_cfg_6102[127]), + .I1(com_cmm_bar1_reg[31]), + .I2(com_cmmt_raddr[31]), + .LO(com_cmm_u_cmm_decoder_N_102_7) + ); + defparam com_cmm_u_cmm_decoder_un9_bar12_64_hit_high_0_I_5.INIT = 8'h6C; + LUT3_L com_cmm_u_cmm_decoder_un9_bar12_64_hit_high_0_I_5 ( + .I0(cfg_cfg_6102[101]), + .I1(com_cmm_bar1_reg[5]), + .I2(com_cmmt_raddr[5]), + .LO(com_cmm_u_cmm_decoder_N_110_2) + ); + defparam com_cmm_u_cmm_decoder_un9_bar01_64_hit_high_0_I_122.INIT = 8'h6C; + LUT3_L com_cmm_u_cmm_decoder_un9_bar01_64_hit_high_0_I_122 ( + .I0(cfg_cfg_6102[73]), + .I1(com_cmm_bar0_reg_9_), + .I2(com_cmmt_raddr[9]), + .LO(com_cmm_u_cmm_decoder_N_6_3) + ); + defparam com_cmm_u_cmm_decoder_un9_bar01_64_hit_high_0_I_113.INIT = 8'h6C; + LUT3_L com_cmm_u_cmm_decoder_un9_bar01_64_hit_high_0_I_113 ( + .I0(cfg_cfg_6102[93]), + .I1(com_cmm_bar0_reg_29_), + .I2(com_cmmt_raddr[29]), + .LO(com_cmm_u_cmm_decoder_N_14_4) + ); + defparam com_cmm_u_cmm_decoder_un9_bar01_64_hit_high_0_I_104.INIT = 8'h6C; + LUT3_L com_cmm_u_cmm_decoder_un9_bar01_64_hit_high_0_I_104 ( + .I0(cfg_cfg_6102[91]), + .I1(com_cmm_bar0_reg_27_), + .I2(com_cmmt_raddr[27]), + .LO(com_cmm_u_cmm_decoder_N_22_3) + ); + defparam com_cmm_u_cmm_decoder_un9_bar01_64_hit_high_0_I_95.INIT = 8'h6C; + LUT3_L com_cmm_u_cmm_decoder_un9_bar01_64_hit_high_0_I_95 ( + .I0(cfg_cfg_6102[71]), + .I1(com_cmm_bar0_reg_7_), + .I2(com_cmmt_raddr[7]), + .LO(com_cmm_u_cmm_decoder_N_30_3) + ); + defparam com_cmm_u_cmm_decoder_un9_bar01_64_hit_high_0_I_86.INIT = 8'h6C; + LUT3_L com_cmm_u_cmm_decoder_un9_bar01_64_hit_high_0_I_86 ( + .I0(cfg_cfg_6102[81]), + .I1(com_cmm_bar0_reg_17_), + .I2(com_cmmt_raddr[17]), + .LO(com_cmm_u_cmm_decoder_N_38_3) + ); + defparam com_cmm_u_cmm_decoder_un9_bar01_64_hit_high_0_I_77.INIT = 8'h6C; + LUT3_L com_cmm_u_cmm_decoder_un9_bar01_64_hit_high_0_I_77 ( + .I0(cfg_cfg_6102[85]), + .I1(com_cmm_bar0_reg_21_), + .I2(com_cmmt_raddr[21]), + .LO(com_cmm_u_cmm_decoder_N_46_3) + ); + defparam com_cmm_u_cmm_decoder_un9_bar01_64_hit_high_0_I_68.INIT = 8'h6C; + LUT3_L com_cmm_u_cmm_decoder_un9_bar01_64_hit_high_0_I_68 ( + .I0(cfg_cfg_6102[83]), + .I1(com_cmm_bar0_reg_19_), + .I2(com_cmmt_raddr[19]), + .LO(com_cmm_u_cmm_decoder_N_54_3) + ); + defparam com_cmm_u_cmm_decoder_un9_bar01_64_hit_high_0_I_59.INIT = 8'h6C; + LUT3_L com_cmm_u_cmm_decoder_un9_bar01_64_hit_high_0_I_59 ( + .I0(cfg_cfg_6102[79]), + .I1(com_cmm_bar0_reg_15_), + .I2(com_cmmt_raddr[15]), + .LO(com_cmm_u_cmm_decoder_N_62_3) + ); + defparam com_cmm_u_cmm_decoder_un9_bar01_64_hit_high_0_I_50.INIT = 8'h6C; + LUT3_L com_cmm_u_cmm_decoder_un9_bar01_64_hit_high_0_I_50 ( + .I0(cfg_cfg_6102[89]), + .I1(com_cmm_bar0_reg_25_), + .I2(com_cmmt_raddr[25]), + .LO(com_cmm_u_cmm_decoder_N_70_3) + ); + defparam com_cmm_u_cmm_decoder_un9_bar01_64_hit_high_0_I_41.INIT = 8'h6C; + LUT3_L com_cmm_u_cmm_decoder_un9_bar01_64_hit_high_0_I_41 ( + .I0(cfg_cfg_6102[77]), + .I1(com_cmm_bar0_reg_13_), + .I2(com_cmmt_raddr[13]), + .LO(com_cmm_u_cmm_decoder_N_78_2) + ); + defparam com_cmm_u_cmm_decoder_un9_bar01_64_hit_high_0_I_32.INIT = 8'h6C; + LUT3_L com_cmm_u_cmm_decoder_un9_bar01_64_hit_high_0_I_32 ( + .I0(cfg_cfg_6102[75]), + .I1(com_cmm_bar0_reg_11_), + .I2(com_cmmt_raddr[11]), + .LO(com_cmm_u_cmm_decoder_N_86_2) + ); + defparam com_cmm_u_cmm_decoder_un9_bar01_64_hit_high_0_I_23.INIT = 8'h6C; + LUT3_L com_cmm_u_cmm_decoder_un9_bar01_64_hit_high_0_I_23 ( + .I0(cfg_cfg_6102[87]), + .I1(com_cmm_bar0_reg_23_), + .I2(com_cmmt_raddr[23]), + .LO(com_cmm_u_cmm_decoder_N_94_3) + ); + defparam com_cmm_u_cmm_decoder_un9_bar01_64_hit_high_0_I_14.INIT = 8'h6C; + LUT3_L com_cmm_u_cmm_decoder_un9_bar01_64_hit_high_0_I_14 ( + .I0(cfg_cfg_6102[95]), + .I1(com_cmm_bar0_reg_31_), + .I2(com_cmmt_raddr[31]), + .LO(com_cmm_u_cmm_decoder_N_102_8) + ); + defparam com_cmm_u_cmm_decoder_un9_bar01_64_hit_high_0_I_5.INIT = 8'h6C; + LUT3_L com_cmm_u_cmm_decoder_un9_bar01_64_hit_high_0_I_5 ( + .I0(cfg_cfg_6102[69]), + .I1(com_cmm_bar0_reg_5_), + .I2(com_cmmt_raddr[5]), + .LO(com_cmm_u_cmm_decoder_N_110_1) + ); + defparam com_cmm_u_cmm_decoder_bar6_eq_raddr_3_0_I_86.INIT = 8'h6C; + LUT3_L com_cmm_u_cmm_decoder_bar6_eq_raddr_3_0_I_86 ( + .I0(cfg_cfg_6102[340]), + .I1(com_cmm_xrom_reg_20_), + .I2(com_cmmt_raddr[52]), + .LO(com_cmm_u_cmm_decoder_N_12) + ); + defparam com_cmm_u_cmm_decoder_bar6_eq_raddr_3_0_I_77.INIT = 8'h6C; + LUT3_L com_cmm_u_cmm_decoder_bar6_eq_raddr_3_0_I_77 ( + .I0(cfg_cfg_6102[334]), + .I1(com_cmm_xrom_reg_14_), + .I2(com_cmmt_raddr[46]), + .LO(com_cmm_u_cmm_decoder_N_20) + ); + defparam com_cmm_u_cmm_decoder_bar6_eq_raddr_3_0_I_68.INIT = 8'h6C; + LUT3_L com_cmm_u_cmm_decoder_bar6_eq_raddr_3_0_I_68 ( + .I0(cfg_cfg_6102[346]), + .I1(com_cmm_xrom_reg_26_), + .I2(com_cmmt_raddr[58]), + .LO(com_cmm_u_cmm_decoder_N_28) + ); + defparam com_cmm_u_cmm_decoder_bar6_eq_raddr_3_0_I_59.INIT = 8'h6C; + LUT3_L com_cmm_u_cmm_decoder_bar6_eq_raddr_3_0_I_59 ( + .I0(cfg_cfg_6102[344]), + .I1(com_cmm_xrom_reg_24_), + .I2(com_cmmt_raddr[56]), + .LO(com_cmm_u_cmm_decoder_N_36) + ); + defparam com_cmm_u_cmm_decoder_bar6_eq_raddr_3_0_I_50.INIT = 8'h6C; + LUT3_L com_cmm_u_cmm_decoder_bar6_eq_raddr_3_0_I_50 ( + .I0(cfg_cfg_6102[348]), + .I1(com_cmm_xrom_reg_28_), + .I2(com_cmmt_raddr[60]), + .LO(com_cmm_u_cmm_decoder_N_44) + ); + defparam com_cmm_u_cmm_decoder_bar6_eq_raddr_3_0_I_41.INIT = 8'h6C; + LUT3_L com_cmm_u_cmm_decoder_bar6_eq_raddr_3_0_I_41 ( + .I0(cfg_cfg_6102[342]), + .I1(com_cmm_xrom_reg_22_), + .I2(com_cmmt_raddr[54]), + .LO(com_cmm_u_cmm_decoder_N_52) + ); + defparam com_cmm_u_cmm_decoder_bar6_eq_raddr_3_0_I_32.INIT = 8'h6C; + LUT3_L com_cmm_u_cmm_decoder_bar6_eq_raddr_3_0_I_32 ( + .I0(cfg_cfg_6102[338]), + .I1(com_cmm_xrom_reg_18_), + .I2(com_cmmt_raddr[50]), + .LO(com_cmm_u_cmm_decoder_N_60) + ); + defparam com_cmm_u_cmm_decoder_bar6_eq_raddr_3_0_I_23.INIT = 8'h6C; + LUT3_L com_cmm_u_cmm_decoder_bar6_eq_raddr_3_0_I_23 ( + .I0(cfg_cfg_6102[336]), + .I1(com_cmm_xrom_reg_16_), + .I2(com_cmmt_raddr[48]), + .LO(com_cmm_u_cmm_decoder_N_68) + ); + defparam com_cmm_u_cmm_decoder_bar6_eq_raddr_3_0_I_14.INIT = 8'h6C; + LUT3_L com_cmm_u_cmm_decoder_bar6_eq_raddr_3_0_I_14 ( + .I0(cfg_cfg_6102[350]), + .I1(com_cmm_xrom_reg_30_), + .I2(com_cmmt_raddr[62]), + .LO(com_cmm_u_cmm_decoder_N_76) + ); + defparam com_cmm_u_cmm_decoder_bar6_eq_raddr_3_0_I_5.INIT = 8'h6C; + LUT3_L com_cmm_u_cmm_decoder_bar6_eq_raddr_3_0_I_5 ( + .I0(cfg_cfg_6102[332]), + .I1(com_cmm_xrom_reg_12_), + .I2(com_cmmt_raddr[44]), + .LO(com_cmm_u_cmm_decoder_N_84) + ); + defparam com_cmm_u_cmm_decoder_bar5_eq_raddr_3_0_I_122.INIT = 8'h6C; + LUT3_L com_cmm_u_cmm_decoder_bar5_eq_raddr_3_0_I_122 ( + .I0(cfg_cfg_6102[233]), + .I1(com_cmm_bar5_reg[9]), + .I2(com_cmmt_raddr[41]), + .LO(com_cmm_u_cmm_decoder_N_6_9) + ); + defparam com_cmm_u_cmm_decoder_bar5_eq_raddr_3_0_I_113.INIT = 8'h6C; + LUT3_L com_cmm_u_cmm_decoder_bar5_eq_raddr_3_0_I_113 ( + .I0(cfg_cfg_6102[253]), + .I1(com_cmm_bar5_reg[29]), + .I2(com_cmmt_raddr[61]), + .LO(com_cmm_u_cmm_decoder_N_14_10) + ); + defparam com_cmm_u_cmm_decoder_bar5_eq_raddr_3_0_I_104.INIT = 8'h6C; + LUT3_L com_cmm_u_cmm_decoder_bar5_eq_raddr_3_0_I_104 ( + .I0(cfg_cfg_6102[251]), + .I1(com_cmm_bar5_reg[27]), + .I2(com_cmmt_raddr[59]), + .LO(com_cmm_u_cmm_decoder_N_22_9) + ); + defparam com_cmm_u_cmm_decoder_bar5_eq_raddr_3_0_I_95.INIT = 8'h6C; + LUT3_L com_cmm_u_cmm_decoder_bar5_eq_raddr_3_0_I_95 ( + .I0(cfg_cfg_6102[231]), + .I1(com_cmm_bar5_reg[7]), + .I2(com_cmmt_raddr[39]), + .LO(com_cmm_u_cmm_decoder_N_30_9) + ); + defparam com_cmm_u_cmm_decoder_bar5_eq_raddr_3_0_I_77.INIT = 8'h6C; + LUT3_L com_cmm_u_cmm_decoder_bar5_eq_raddr_3_0_I_77 ( + .I0(cfg_cfg_6102[245]), + .I1(com_cmm_bar5_reg[21]), + .I2(com_cmmt_raddr[53]), + .LO(com_cmm_u_cmm_decoder_N_46_9) + ); + defparam com_cmm_u_cmm_decoder_bar5_eq_raddr_3_0_I_59.INIT = 8'h6C; + LUT3_L com_cmm_u_cmm_decoder_bar5_eq_raddr_3_0_I_59 ( + .I0(cfg_cfg_6102[239]), + .I1(com_cmm_bar5_reg[15]), + .I2(com_cmmt_raddr[47]), + .LO(com_cmm_u_cmm_decoder_N_62_9) + ); + defparam com_cmm_u_cmm_decoder_bar5_eq_raddr_3_0_I_50.INIT = 8'h6C; + LUT3_L com_cmm_u_cmm_decoder_bar5_eq_raddr_3_0_I_50 ( + .I0(cfg_cfg_6102[249]), + .I1(com_cmm_bar5_reg[25]), + .I2(com_cmmt_raddr[57]), + .LO(com_cmm_u_cmm_decoder_N_70_9) + ); + defparam com_cmm_u_cmm_decoder_bar5_eq_raddr_3_0_I_41.INIT = 8'h6C; + LUT3_L com_cmm_u_cmm_decoder_bar5_eq_raddr_3_0_I_41 ( + .I0(cfg_cfg_6102[237]), + .I1(com_cmm_bar5_reg[13]), + .I2(com_cmmt_raddr[45]), + .LO(com_cmm_u_cmm_decoder_N_78_8) + ); + defparam com_cmm_u_cmm_decoder_bar5_eq_raddr_3_0_I_32.INIT = 8'h6C; + LUT3_L com_cmm_u_cmm_decoder_bar5_eq_raddr_3_0_I_32 ( + .I0(cfg_cfg_6102[235]), + .I1(com_cmm_bar5_reg[11]), + .I2(com_cmmt_raddr[43]), + .LO(com_cmm_u_cmm_decoder_N_86_8) + ); + defparam com_cmm_u_cmm_decoder_bar5_eq_raddr_3_0_I_23.INIT = 8'h6C; + LUT3_L com_cmm_u_cmm_decoder_bar5_eq_raddr_3_0_I_23 ( + .I0(cfg_cfg_6102[247]), + .I1(com_cmm_bar5_reg[23]), + .I2(com_cmmt_raddr[55]), + .LO(com_cmm_u_cmm_decoder_N_94_9) + ); + defparam com_cmm_u_cmm_decoder_bar5_eq_raddr_3_0_I_14.INIT = 8'h6C; + LUT3_L com_cmm_u_cmm_decoder_bar5_eq_raddr_3_0_I_14 ( + .I0(cfg_cfg_6102[255]), + .I1(com_cmm_bar5_reg[31]), + .I2(com_cmmt_raddr[63]), + .LO(com_cmm_u_cmm_decoder_N_102_14) + ); + defparam com_cmm_u_cmm_decoder_bar5_eq_raddr_3_0_I_5.INIT = 8'h6C; + LUT3_L com_cmm_u_cmm_decoder_bar5_eq_raddr_3_0_I_5 ( + .I0(cfg_cfg_6102[229]), + .I1(com_cmm_bar5_reg[5]), + .I2(com_cmmt_raddr[37]), + .LO(com_cmm_u_cmm_decoder_N_110_7) + ); + defparam com_cmm_u_cmm_decoder_un10_bar01_64_hit_low_0_I_32.INIT = 8'h6C; + LUT3_L com_cmm_u_cmm_decoder_un10_bar01_64_hit_low_0_I_32 ( + .I0(cfg_cfg_6102[96]), + .I1(com_cmm_bar1_reg[0]), + .I2(com_cmmt_raddr[32]), + .LO(com_cmm_u_cmm_decoder_N_102_9) + ); + defparam com_cmm_u_cmm_decoder_un10_bar12_64_hit_low_0_I_32.INIT = 8'h6C; + LUT3_L com_cmm_u_cmm_decoder_un10_bar12_64_hit_low_0_I_32 ( + .I0(cfg_cfg_6102[128]), + .I1(com_cmm_bar2_reg[0]), + .I2(com_cmmt_raddr[32]), + .LO(com_cmm_u_cmm_decoder_N_102_10) + ); + defparam com_cmm_u_cmm_decoder_un10_bar23_64_hit_low_0_I_32.INIT = 8'h6C; + LUT3_L com_cmm_u_cmm_decoder_un10_bar23_64_hit_low_0_I_32 ( + .I0(cfg_cfg_6102[160]), + .I1(com_cmm_bar3_reg[0]), + .I2(com_cmmt_raddr[32]), + .LO(com_cmm_u_cmm_decoder_N_102_11) + ); + defparam com_cmm_u_cmm_decoder_un10_bar34_64_hit_low_0_I_32.INIT = 8'h6C; + LUT3_L com_cmm_u_cmm_decoder_un10_bar34_64_hit_low_0_I_32 ( + .I0(cfg_cfg_6102[192]), + .I1(com_cmm_bar4_reg[0]), + .I2(com_cmmt_raddr[32]), + .LO(com_cmm_u_cmm_decoder_N_102_12) + ); + defparam com_cmm_u_cmm_decoder_un10_bar45_64_hit_low_0_I_131.INIT = 8'h6C; + LUT3_L com_cmm_u_cmm_decoder_un10_bar45_64_hit_low_0_I_131 ( + .I0(cfg_cfg_6102[226]), + .I1(com_cmm_bar5_reg[2]), + .I2(com_cmmt_raddr[34]), + .LO(com_cmm_u_cmm_decoder_N_14) + ); + defparam com_cmm_u_cmm_decoder_un10_bar45_64_hit_low_0_I_32.INIT = 8'h6C; + LUT3_L com_cmm_u_cmm_decoder_un10_bar45_64_hit_low_0_I_32 ( + .I0(cfg_cfg_6102[224]), + .I1(com_cmm_bar5_reg[0]), + .I2(com_cmmt_raddr[32]), + .LO(com_cmm_u_cmm_decoder_N_102_13) + ); + defparam com_cmm_u_cmm_decoder_bar45_64_hit_high_3_0_a2_0_a2_0_a2_0_a2_0.INIT = 4'h8; + LUT2 com_cmm_u_cmm_decoder_bar45_64_hit_high_3_0_a2_0_a2_0_a2_0_a2_0 ( + .I0(com_cmm_bar4_reg[2]), + .I1(com_cmm_u_cmm_decoder_un18_bar3_32_hit_nc_0_and_1), + .O(com_cmm_u_cmm_decoder_N_58543) + ); + defparam com_cmm_u_cmm_decoder_bar23_64_hit_high_3_0_a2_0_a2_0_a2_0_a2_0.INIT = 4'h8; + LUT2 com_cmm_u_cmm_decoder_bar23_64_hit_high_3_0_a2_0_a2_0_a2_0_a2_0 ( + .I0(com_cmm_bar2_reg[2]), + .I1(com_cmm_u_cmm_decoder_un18_bar1_32_hit_nc_0_and_1), + .O(com_cmm_u_cmm_decoder_N_58557) + ); + defparam com_cmm_u_cmm_decoder_un11_bar34_64_hit_low_3_and_0_a2_0_a2_0_a2_0_a2.INIT = 16'h0001; + LUT4 com_cmm_u_cmm_decoder_un11_bar34_64_hit_low_3_and_0_a2_0_a2_0_a2_0_a2 ( + .I0(cfg_cfg_6102[204]), + .I1(cfg_cfg_6102[205]), + .I2(cfg_cfg_6102[206]), + .I3(cfg_cfg_6102[207]), + .O(com_cmm_u_cmm_decoder_un11_bar4_32_hit_nc_3_and) + ); + defparam com_cmm_u_cmm_decoder_un11_bar34_64_hit_low_1_and_0_a2_0_a2_0_a2_0_a2.INIT = 16'h0001; + LUT4 com_cmm_u_cmm_decoder_un11_bar34_64_hit_low_1_and_0_a2_0_a2_0_a2_0_a2 ( + .I0(cfg_cfg_6102[196]), + .I1(cfg_cfg_6102[197]), + .I2(cfg_cfg_6102[198]), + .I3(cfg_cfg_6102[199]), + .O(com_cmm_u_cmm_decoder_un11_bar4_32_hit_nc_1_and) + ); + defparam com_cmm_u_cmm_decoder_un11_bar34_64_hit_low_4_and_0_a2_0_a2_0_a2_0_a2.INIT = 16'h0001; + LUT4 com_cmm_u_cmm_decoder_un11_bar34_64_hit_low_4_and_0_a2_0_a2_0_a2_0_a2 ( + .I0(cfg_cfg_6102[208]), + .I1(cfg_cfg_6102[209]), + .I2(cfg_cfg_6102[210]), + .I3(cfg_cfg_6102[211]), + .O(com_cmm_u_cmm_decoder_un11_bar4_32_hit_nc_4_and) + ); + defparam com_cmm_u_cmm_decoder_un11_bar34_64_hit_low_5_and_0_a2_0_a2_0_a2.INIT = 16'h0001; + LUT4 com_cmm_u_cmm_decoder_un11_bar34_64_hit_low_5_and_0_a2_0_a2_0_a2 ( + .I0(cfg_cfg_6102[212]), + .I1(cfg_cfg_6102[213]), + .I2(cfg_cfg_6102[214]), + .I3(cfg_cfg_6102[215]), + .O(com_cmm_u_cmm_decoder_un11_bar4_32_hit_nc_5_and) + ); + defparam com_cmm_u_cmm_decoder_un11_bar34_64_hit_low_2_and_0_a2_0_a2_0_a2.INIT = 16'h0001; + LUT4 com_cmm_u_cmm_decoder_un11_bar34_64_hit_low_2_and_0_a2_0_a2_0_a2 ( + .I0(cfg_cfg_6102[200]), + .I1(cfg_cfg_6102[201]), + .I2(cfg_cfg_6102[202]), + .I3(cfg_cfg_6102[203]), + .O(com_cmm_u_cmm_decoder_un11_bar4_32_hit_nc_2_and) + ); + defparam com_cmm_u_cmm_decoder_un11_bar34_64_hit_low_7_and_0_a2_0_a2_0_a2.INIT = 16'h0001; + LUT4 com_cmm_u_cmm_decoder_un11_bar34_64_hit_low_7_and_0_a2_0_a2_0_a2 ( + .I0(cfg_cfg_6102[220]), + .I1(cfg_cfg_6102[221]), + .I2(cfg_cfg_6102[222]), + .I3(cfg_cfg_6102[223]), + .O(com_cmm_u_cmm_decoder_un11_bar4_32_hit_nc_7_and) + ); + defparam com_cmm_u_cmm_decoder_un11_bar34_64_hit_low_6_and_0_a2_0_a2_0_a2.INIT = 16'h0001; + LUT4 com_cmm_u_cmm_decoder_un11_bar34_64_hit_low_6_and_0_a2_0_a2_0_a2 ( + .I0(cfg_cfg_6102[216]), + .I1(cfg_cfg_6102[217]), + .I2(cfg_cfg_6102[218]), + .I3(cfg_cfg_6102[219]), + .O(com_cmm_u_cmm_decoder_un11_bar4_32_hit_nc_6_and) + ); + defparam com_cmm_u_cmm_decoder_bar23_64_hit_low_3_0_a2_0_a2_0_a2_0_a2_0.INIT = 8'h80; + LUT3 com_cmm_u_cmm_decoder_bar23_64_hit_low_3_0_a2_0_a2_0_a2_0_a2_0 ( + .I0(com_cmm_u_cmm_decoder_N_56113_i), + .I1(NlwRenamedSig_OI_cfg_command_1_), + .I2(com_cmmt_mem64), + .O(com_cmm_u_cmm_decoder_bar45_64_hit_low_3_0_a2_0_a2_0_a2_0_a2_0) + ); + defparam com_cmm_u_cmm_decoder_bar01_64_hit_high_3_0_a2_0_a2_0_a2_0_a2_0.INIT = 8'h10; + LUT3 com_cmm_u_cmm_decoder_bar01_64_hit_high_3_0_a2_0_a2_0_a2_0_a2_0 ( + .I0(com_cmm_bar0_reg_0_), + .I1(com_cmm_bar0_reg_1_), + .I2(com_cmm_bar0_reg_2_), + .O(com_cmm_u_cmm_decoder_N_58582) + ); + defparam com_cmm_u_cmm_decoder_bar_hit_4_0_a2_0_1_.INIT = 16'h0777; + LUT4_L com_cmm_u_cmm_decoder_bar_hit_4_0_a2_0_1_ ( + .I0(com_cmm_u_cmm_decoder_bar1_32_hit_nc_5529), + .I1(com_cmm_u_cmm_decoder_bar1_eq_raddr_5519), + .I2(com_cmm_u_cmm_decoder_bar12_64_hit_high_5524), + .I3(com_cmm_u_cmm_decoder_bar12_64_hit_low_5533), + .LO(com_cmm_u_cmm_decoder_bar_hit_4_0_a2_0[1]) + ); + defparam com_cmm_u_cmm_decoder_bar_hit_5_0_a2_0_2_.INIT = 16'h0777; + LUT4_L com_cmm_u_cmm_decoder_bar_hit_5_0_a2_0_2_ ( + .I0(com_cmm_u_cmm_decoder_bar2_32_hit_nc_5528), + .I1(com_cmm_u_cmm_decoder_bar2_eq_raddr_5518), + .I2(com_cmm_u_cmm_decoder_bar23_64_hit_high_5523), + .I3(com_cmm_u_cmm_decoder_bar23_64_hit_low_5532), + .LO(com_cmm_u_cmm_decoder_bar_hit_5_0_a2_0[2]) + ); + defparam com_cmm_u_cmm_decoder_bar_hit_7_0_a2_0_4_.INIT = 16'h0777; + LUT4_L com_cmm_u_cmm_decoder_bar_hit_7_0_a2_0_4_ ( + .I0(com_cmm_u_cmm_decoder_bar4_32_hit_nc_5536), + .I1(com_cmm_u_cmm_decoder_bar4_eq_raddr_5516), + .I2(com_cmm_u_cmm_decoder_bar45_64_hit_high_5521), + .I3(com_cmm_u_cmm_decoder_bar45_64_hit_low_5530), + .LO(com_cmm_u_cmm_decoder_bar_hit_7_0_a2_0[4]) + ); + defparam com_cmm_u_cmm_decoder_bar_hit_6_0_a2_0_3_.INIT = 16'h0777; + LUT4_L com_cmm_u_cmm_decoder_bar_hit_6_0_a2_0_3_ ( + .I0(com_cmm_u_cmm_decoder_bar3_32_hit_nc_5537), + .I1(com_cmm_u_cmm_decoder_bar3_eq_raddr_5517), + .I2(com_cmm_u_cmm_decoder_bar34_64_hit_high_5522), + .I3(com_cmm_u_cmm_decoder_bar34_64_hit_low_5531), + .LO(com_cmm_u_cmm_decoder_bar_hit_6_0_a2_0[3]) + ); + defparam com_cmm_u_cmm_decoder_bar5_32_hit_nc_3_i_0_0_0_m2_0.INIT = 8'h35; + LUT3 com_cmm_u_cmm_decoder_bar5_32_hit_nc_3_i_0_0_0_m2_0 ( + .I0(com_cmm_u_cmm_decoder_N_56035_i), + .I1(com_cmm_u_cmm_decoder_bar5_32_hit_nc_3_i_0_0_0_o3_0_5492), + .I2(cfg_cfg_6102[224]), + .O(com_cmm_u_cmm_decoder_N_56986) + ); + defparam com_cmm_u_cmm_decoder_bar3_32_hit_nc_3_i_0_0_0_m2_0.INIT = 8'h35; + LUT3 com_cmm_u_cmm_decoder_bar3_32_hit_nc_3_i_0_0_0_m2_0 ( + .I0(com_cmm_u_cmm_decoder_N_56035_i), + .I1(com_cmm_u_cmm_decoder_bar5_32_hit_nc_3_i_0_0_0_o3_0_5492), + .I2(cfg_cfg_6102[160]), + .O(com_cmm_u_cmm_decoder_N_56989) + ); + defparam com_cmm_u_cmm_decoder_bar5_eq_raddr_3_0_I_72.INIT = 16'h0903; + LUT4 com_cmm_u_cmm_decoder_bar5_eq_raddr_3_0_I_72 ( + .I0(cfg_cfg_6102[242]), + .I1(com_cmm_bar5_reg[18]), + .I2(com_cmm_u_cmm_decoder_N_54_9), + .I3(com_cmmt_raddr[50]), + .O(com_cmm_u_cmm_decoder_N_51_3) + ); + defparam com_cmm_u_cmm_decoder_bar5_eq_raddr_3_0_I_90.INIT = 16'h0903; + LUT4 com_cmm_u_cmm_decoder_bar5_eq_raddr_3_0_I_90 ( + .I0(cfg_cfg_6102[240]), + .I1(com_cmm_bar5_reg[16]), + .I2(com_cmm_u_cmm_decoder_N_38_9), + .I3(com_cmmt_raddr[48]), + .O(com_cmm_u_cmm_decoder_N_35_3) + ); + defparam com_cmm_u_cmm_decoder_bar5_eq_raddr_3_0_I_126.INIT = 16'h0903; + LUT4 com_cmm_u_cmm_decoder_bar5_eq_raddr_3_0_I_126 ( + .I0(cfg_cfg_6102[232]), + .I1(com_cmm_bar5_reg[8]), + .I2(com_cmm_u_cmm_decoder_N_6_9), + .I3(com_cmmt_raddr[40]), + .O(com_cmm_u_cmm_decoder_N_3_3) + ); + defparam com_cmm_u_cmm_decoder_bar5_eq_raddr_3_0_I_117.INIT = 16'h0903; + LUT4 com_cmm_u_cmm_decoder_bar5_eq_raddr_3_0_I_117 ( + .I0(cfg_cfg_6102[252]), + .I1(com_cmm_bar5_reg[28]), + .I2(com_cmm_u_cmm_decoder_N_14_10), + .I3(com_cmmt_raddr[60]), + .O(com_cmm_u_cmm_decoder_N_11_4) + ); + defparam com_cmm_u_cmm_decoder_bar5_eq_raddr_3_0_I_108.INIT = 16'h0903; + LUT4 com_cmm_u_cmm_decoder_bar5_eq_raddr_3_0_I_108 ( + .I0(cfg_cfg_6102[250]), + .I1(com_cmm_bar5_reg[26]), + .I2(com_cmm_u_cmm_decoder_N_22_9), + .I3(com_cmmt_raddr[58]), + .O(com_cmm_u_cmm_decoder_N_19_3) + ); + defparam com_cmm_u_cmm_decoder_bar5_eq_raddr_3_0_I_99.INIT = 16'h0903; + LUT4 com_cmm_u_cmm_decoder_bar5_eq_raddr_3_0_I_99 ( + .I0(cfg_cfg_6102[230]), + .I1(com_cmm_bar5_reg[6]), + .I2(com_cmm_u_cmm_decoder_N_30_9), + .I3(com_cmmt_raddr[38]), + .O(com_cmm_u_cmm_decoder_N_27_3) + ); + defparam com_cmm_u_cmm_decoder_bar5_eq_raddr_3_0_I_81.INIT = 16'h0903; + LUT4 com_cmm_u_cmm_decoder_bar5_eq_raddr_3_0_I_81 ( + .I0(cfg_cfg_6102[244]), + .I1(com_cmm_bar5_reg[20]), + .I2(com_cmm_u_cmm_decoder_N_46_9), + .I3(com_cmmt_raddr[52]), + .O(com_cmm_u_cmm_decoder_N_43_3) + ); + defparam com_cmm_u_cmm_decoder_bar5_eq_raddr_3_0_I_63.INIT = 16'h0903; + LUT4 com_cmm_u_cmm_decoder_bar5_eq_raddr_3_0_I_63 ( + .I0(cfg_cfg_6102[238]), + .I1(com_cmm_bar5_reg[14]), + .I2(com_cmm_u_cmm_decoder_N_62_9), + .I3(com_cmmt_raddr[46]), + .O(com_cmm_u_cmm_decoder_N_59_3) + ); + defparam com_cmm_u_cmm_decoder_bar5_eq_raddr_3_0_I_54.INIT = 16'h0903; + LUT4 com_cmm_u_cmm_decoder_bar5_eq_raddr_3_0_I_54 ( + .I0(cfg_cfg_6102[248]), + .I1(com_cmm_bar5_reg[24]), + .I2(com_cmm_u_cmm_decoder_N_70_9), + .I3(com_cmmt_raddr[56]), + .O(com_cmm_u_cmm_decoder_N_67_3) + ); + defparam com_cmm_u_cmm_decoder_bar5_eq_raddr_3_0_I_45.INIT = 16'h0903; + LUT4 com_cmm_u_cmm_decoder_bar5_eq_raddr_3_0_I_45 ( + .I0(cfg_cfg_6102[236]), + .I1(com_cmm_bar5_reg[12]), + .I2(com_cmm_u_cmm_decoder_N_78_8), + .I3(com_cmmt_raddr[44]), + .O(com_cmm_u_cmm_decoder_N_75_3) + ); + defparam com_cmm_u_cmm_decoder_bar5_eq_raddr_3_0_I_36.INIT = 16'h0903; + LUT4 com_cmm_u_cmm_decoder_bar5_eq_raddr_3_0_I_36 ( + .I0(cfg_cfg_6102[234]), + .I1(com_cmm_bar5_reg[10]), + .I2(com_cmm_u_cmm_decoder_N_86_8), + .I3(com_cmmt_raddr[42]), + .O(com_cmm_u_cmm_decoder_N_83_3) + ); + defparam com_cmm_u_cmm_decoder_bar5_eq_raddr_3_0_I_27.INIT = 16'h0903; + LUT4 com_cmm_u_cmm_decoder_bar5_eq_raddr_3_0_I_27 ( + .I0(cfg_cfg_6102[246]), + .I1(com_cmm_bar5_reg[22]), + .I2(com_cmm_u_cmm_decoder_N_94_9), + .I3(com_cmmt_raddr[54]), + .O(com_cmm_u_cmm_decoder_N_91_3) + ); + defparam com_cmm_u_cmm_decoder_bar5_eq_raddr_3_0_I_18.INIT = 16'h0903; + LUT4 com_cmm_u_cmm_decoder_bar5_eq_raddr_3_0_I_18 ( + .I0(cfg_cfg_6102[254]), + .I1(com_cmm_bar5_reg[30]), + .I2(com_cmm_u_cmm_decoder_N_102_14), + .I3(com_cmmt_raddr[62]), + .O(com_cmm_u_cmm_decoder_N_99_9) + ); + defparam com_cmm_u_cmm_decoder_bar5_eq_raddr_3_0_I_9.INIT = 16'h0903; + LUT4 com_cmm_u_cmm_decoder_bar5_eq_raddr_3_0_I_9 ( + .I0(cfg_cfg_6102[228]), + .I1(com_cmm_bar5_reg[4]), + .I2(com_cmm_u_cmm_decoder_N_110_7), + .I3(com_cmmt_raddr[36]), + .O(com_cmm_u_cmm_decoder_N_107_13) + ); + defparam com_cmm_u_cmm_decoder_bar4_32_hit_nc_3_i_0_0_0_0.INIT = 8'h2A; + LUT3_L com_cmm_u_cmm_decoder_bar4_32_hit_nc_3_i_0_0_0_0 ( + .I0(com_cmm_u_cmm_decoder_N_56113_i), + .I1(com_cmm_bar3_reg[2]), + .I2(com_cmm_u_cmm_decoder_bar34_64_hit_high_3_1), + .LO(com_cmm_u_cmm_decoder_bar4_32_hit_nc_3_i_0_0_0_0_5491) + ); + defparam com_cmm_u_cmm_decoder_bar0_32_hit_nc_3_i_0_0_0_0.INIT = 16'hC088; + LUT4 com_cmm_u_cmm_decoder_bar0_32_hit_nc_3_i_0_0_0_0 ( + .I0(com_cmm_u_cmm_decoder_N_56035_i), + .I1(com_cmm_u_cmm_decoder_N_56113_i), + .I2(com_cmm_u_cmm_decoder_bar5_32_hit_nc_3_i_0_0_0_o3_0_5492), + .I3(cfg_cfg_6102[64]), + .O(com_cmm_u_cmm_decoder_bar0_32_hit_nc_3_i_0_0_0_0_5505) + ); + defparam com_cmm_u_cmm_decoder_bar4_32_hit_nc_3_i_0_0_0_1.INIT = 16'hCA00; + LUT4 com_cmm_u_cmm_decoder_bar4_32_hit_nc_3_i_0_0_0_1 ( + .I0(com_cmm_u_cmm_decoder_N_56035_i), + .I1(com_cmm_u_cmm_decoder_bar5_32_hit_nc_3_i_0_0_0_o3_0_5492), + .I2(cfg_cfg_6102[192]), + .I3(com_cmm_u_cmm_decoder_bar4_32_hit_nc_3_i_0_0_0_0_5491), + .O(com_cmm_u_cmm_decoder_bar4_32_hit_nc_3_i_0_0_0_1_5508) + ); + defparam com_cmm_u_cmm_decoder_bar2_32_hit_nc_3_i_0_0_0_1.INIT = 16'hCA00; + LUT4 com_cmm_u_cmm_decoder_bar2_32_hit_nc_3_i_0_0_0_1 ( + .I0(com_cmm_u_cmm_decoder_N_56035_i), + .I1(com_cmm_u_cmm_decoder_bar5_32_hit_nc_3_i_0_0_0_o3_0_5492), + .I2(cfg_cfg_6102[128]), + .I3(com_cmm_u_cmm_decoder_bar2_32_hit_nc_3_i_0_0_0_0_5511), + .O(com_cmm_u_cmm_decoder_bar2_32_hit_nc_3_i_0_0_0_1_5495) + ); + defparam com_cmm_u_cmm_decoder_bar1_32_hit_nc_3_i_0_0_0_1.INIT = 16'hCA00; + LUT4 com_cmm_u_cmm_decoder_bar1_32_hit_nc_3_i_0_0_0_1 ( + .I0(com_cmm_u_cmm_decoder_N_56035_i), + .I1(com_cmm_u_cmm_decoder_bar5_32_hit_nc_3_i_0_0_0_o3_0_5492), + .I2(cfg_cfg_6102[96]), + .I3(com_cmm_u_cmm_decoder_bar1_32_hit_nc_3_i_0_0_0_0_5512), + .O(com_cmm_u_cmm_decoder_bar1_32_hit_nc_3_i_0_0_0_1_5497) + ); + defparam com_cmm_u_cmm_decoder_bar3_32_hit_nc_3_i_0_0_0_2.INIT = 16'h0002; + LUT4_L com_cmm_u_cmm_decoder_bar3_32_hit_nc_3_i_0_0_0_2 ( + .I0(com_cmm_u_cmm_decoder_N_56113_i), + .I1(com_cmm_u_cmm_decoder_N_56989), + .I2(com_cmm_u_cmm_decoder_N_58557), + .I3(com_cmm_u_cmm_decoder_un11_bar3_32_hit_nc_7_5500), + .LO(com_cmm_u_cmm_decoder_bar3_32_hit_nc_3_i_0_0_0_2_5510) + ); + defparam com_cmm_u_cmm_decoder_bar45_64_hit_high_3_0_a2_0_a2_0_a2_0_a2.INIT = 8'h08; + LUT3_L com_cmm_u_cmm_decoder_bar45_64_hit_high_3_0_a2_0_a2_0_a2_0_a2 ( + .I0(com_cmm_u_cmm_decoder_N_58543), + .I1(com_cmm_u_cmm_decoder_I_10), + .I2(com_cmm_u_cmm_decoder_un11_bar34_64_hit_low_7_5499), + .LO(com_cmm_u_cmm_decoder_bar45_64_hit_high_3) + ); + defparam com_cmm_u_cmm_decoder_bar34_64_hit_high_3_0_a2_0_a2_0_a2_0_a2.INIT = 16'h0080; + LUT4_L com_cmm_u_cmm_decoder_bar34_64_hit_high_3_0_a2_0_a2_0_a2_0_a2 ( + .I0(com_cmm_bar3_reg[2]), + .I1(com_cmm_u_cmm_decoder_bar34_64_hit_high_3_1), + .I2(com_cmm_u_cmm_decoder_I_10_0), + .I3(com_cmm_u_cmm_decoder_un11_bar3_32_hit_nc_7_5500), + .LO(com_cmm_u_cmm_decoder_bar34_64_hit_high_3) + ); + defparam com_cmm_u_cmm_decoder_bar23_64_hit_high_3_0_a2_0_a2_0_a2_0_a2.INIT = 8'h08; + LUT3_L com_cmm_u_cmm_decoder_bar23_64_hit_high_3_0_a2_0_a2_0_a2_0_a2 ( + .I0(com_cmm_u_cmm_decoder_N_58557), + .I1(com_cmm_u_cmm_decoder_I_10_1), + .I2(com_cmm_u_cmm_decoder_un11_bar2_32_hit_nc_7_5501), + .LO(com_cmm_u_cmm_decoder_bar23_64_hit_high_3) + ); + defparam com_cmm_u_cmm_decoder_bar12_64_hit_high_3_0_a2_0_a2_0_a2_0_a2.INIT = 8'h08; + LUT3_L com_cmm_u_cmm_decoder_bar12_64_hit_high_3_0_a2_0_a2_0_a2_0_a2 ( + .I0(com_cmm_u_cmm_decoder_N_58555), + .I1(com_cmm_u_cmm_decoder_I_10_2), + .I2(com_cmm_u_cmm_decoder_un11_bar1_32_hit_nc_7_5502), + .LO(com_cmm_u_cmm_decoder_bar12_64_hit_high_3) + ); + defparam com_cmm_u_cmm_decoder_bar01_64_hit_high_3_0_a2_0_a2_0_a2_0_a2.INIT = 8'h08; + LUT3_L com_cmm_u_cmm_decoder_bar01_64_hit_high_3_0_a2_0_a2_0_a2_0_a2 ( + .I0(com_cmm_u_cmm_decoder_N_58582), + .I1(com_cmm_u_cmm_decoder_I_10_3), + .I2(com_cmm_u_cmm_decoder_un11_bar0_32_hit_nc_7_5504), + .LO(com_cmm_u_cmm_decoder_bar01_64_hit_high_3) + ); + defparam com_cmm_u_cmm_decoder_bar6_32_hit_nc_3_0_a2_0_a2_0_a2_0_a2.INIT = 16'h0800; + LUT4_L com_cmm_u_cmm_decoder_bar6_32_hit_nc_3_0_a2_0_a2_0_a2_0_a2 ( + .I0(com_cmm_u_cmm_decoder_N_56035_i), + .I1(com_cmm_u_cmm_decoder_N_56113_i), + .I2(com_cmm_u_cmm_decoder_un7_bar6_32_hit_nc_6_5493), + .I3(com_cmm_xrom_reg_0_), + .LO(com_cmm_u_cmm_decoder_bar6_32_hit_nc_3) + ); + defparam com_cmm_u_cmm_decoder_bar5_32_hit_nc_3_i_0_0_0.INIT = 16'h0002; + LUT4_L com_cmm_u_cmm_decoder_bar5_32_hit_nc_3_i_0_0_0 ( + .I0(com_cmm_u_cmm_decoder_N_56113_i), + .I1(com_cmm_u_cmm_decoder_N_56986), + .I2(com_cmm_u_cmm_decoder_N_58543), + .I3(com_cmm_u_cmm_decoder_un11_bar5_32_hit_nc_7_5498), + .LO(com_cmm_u_cmm_decoder_N_17867_i) + ); + defparam com_cmm_u_cmm_decoder_bar2_32_hit_nc_3_i_0_0_0.INIT = 16'h0C04; + LUT4_L com_cmm_u_cmm_decoder_bar2_32_hit_nc_3_i_0_0_0 ( + .I0(com_cmm_u_cmm_decoder_N_58557), + .I1(com_cmm_u_cmm_decoder_bar2_32_hit_nc_3_i_0_0_0_1_5495), + .I2(com_cmm_u_cmm_decoder_un11_bar2_32_hit_nc_7_5501), + .I3(com_cmm_u_cmm_decoder_un18_bar2_32_hit_nc_7_5494), + .LO(com_cmm_u_cmm_decoder_N_18225_i) + ); + defparam com_cmm_u_cmm_decoder_bar1_32_hit_nc_3_i_0_0_0.INIT = 16'h0C04; + LUT4_L com_cmm_u_cmm_decoder_bar1_32_hit_nc_3_i_0_0_0 ( + .I0(com_cmm_u_cmm_decoder_N_58555), + .I1(com_cmm_u_cmm_decoder_bar1_32_hit_nc_3_i_0_0_0_1_5497), + .I2(com_cmm_u_cmm_decoder_un11_bar1_32_hit_nc_7_5502), + .I3(com_cmm_u_cmm_decoder_un18_bar1_32_hit_nc_7_5496), + .LO(com_cmm_u_cmm_decoder_N_18403_i) + ); + defparam com_cmm_u_cmm_decoder_bar45_64_hit_low_3_0_a2_0_a2_0_a2_0_a2.INIT = 8'h08; + LUT3_L com_cmm_u_cmm_decoder_bar45_64_hit_low_3_0_a2_0_a2_0_a2_0_a2 ( + .I0(com_cmm_u_cmm_decoder_bar45_64_hit_low_3_0_a2_0_a2_0_a2_0_a2_0), + .I1(com_cmm_u_cmm_decoder_I_28_1), + .I2(com_cmm_u_cmm_decoder_un11_bar5_32_hit_nc_7_5498), + .LO(com_cmm_u_cmm_decoder_bar45_64_hit_low_3) + ); + defparam com_cmm_u_cmm_decoder_bar34_64_hit_low_3_0_a2_0_a2_0_a2_0_a2.INIT = 8'h08; + LUT3_L com_cmm_u_cmm_decoder_bar34_64_hit_low_3_0_a2_0_a2_0_a2_0_a2 ( + .I0(com_cmm_u_cmm_decoder_bar45_64_hit_low_3_0_a2_0_a2_0_a2_0_a2_0), + .I1(com_cmm_u_cmm_decoder_I_28_2), + .I2(com_cmm_u_cmm_decoder_un11_bar34_64_hit_low_7_5499), + .LO(com_cmm_u_cmm_decoder_bar34_64_hit_low_3) + ); + defparam com_cmm_u_cmm_decoder_bar23_64_hit_low_3_0_a2_0_a2_0_a2_0_a2.INIT = 8'h08; + LUT3_L com_cmm_u_cmm_decoder_bar23_64_hit_low_3_0_a2_0_a2_0_a2_0_a2 ( + .I0(com_cmm_u_cmm_decoder_bar45_64_hit_low_3_0_a2_0_a2_0_a2_0_a2_0), + .I1(com_cmm_u_cmm_decoder_I_28_3), + .I2(com_cmm_u_cmm_decoder_un11_bar3_32_hit_nc_7_5500), + .LO(com_cmm_u_cmm_decoder_bar23_64_hit_low_3) + ); + defparam com_cmm_u_cmm_decoder_bar12_64_hit_low_3_0_a2_0_a2_0_a2_0_a2.INIT = 8'h08; + LUT3_L com_cmm_u_cmm_decoder_bar12_64_hit_low_3_0_a2_0_a2_0_a2_0_a2 ( + .I0(com_cmm_u_cmm_decoder_bar45_64_hit_low_3_0_a2_0_a2_0_a2_0_a2_0), + .I1(com_cmm_u_cmm_decoder_I_28_4), + .I2(com_cmm_u_cmm_decoder_un11_bar2_32_hit_nc_7_5501), + .LO(com_cmm_u_cmm_decoder_bar12_64_hit_low_3) + ); + defparam com_cmm_u_cmm_decoder_bar01_64_hit_low_3_0_a2_0_a2_0_a2_0_a2.INIT = 8'h08; + LUT3_L com_cmm_u_cmm_decoder_bar01_64_hit_low_3_0_a2_0_a2_0_a2_0_a2 ( + .I0(com_cmm_u_cmm_decoder_bar45_64_hit_low_3_0_a2_0_a2_0_a2_0_a2_0), + .I1(com_cmm_u_cmm_decoder_I_28_5), + .I2(com_cmm_u_cmm_decoder_un11_bar1_32_hit_nc_7_5502), + .LO(com_cmm_u_cmm_decoder_bar01_64_hit_low_3) + ); + defparam com_cmm_u_cmm_decoder_bar0_32_hit_nc_3_i_0_0_0.INIT = 16'h0C04; + LUT4_L com_cmm_u_cmm_decoder_bar0_32_hit_nc_3_i_0_0_0 ( + .I0(com_cmm_u_cmm_decoder_N_58582), + .I1(com_cmm_u_cmm_decoder_bar0_32_hit_nc_3_i_0_0_0_0_5505), + .I2(com_cmm_u_cmm_decoder_un11_bar0_32_hit_nc_7_5504), + .I3(com_cmm_u_cmm_decoder_un18_bar0_32_hit_nc_7_5503), + .LO(com_cmm_u_cmm_decoder_N_18400_i) + ); + defparam com_cmm_u_cmm_decoder_bar4_32_hit_nc_3_i_0_0_0.INIT = 16'h0C04; + LUT4_L com_cmm_u_cmm_decoder_bar4_32_hit_nc_3_i_0_0_0 ( + .I0(com_cmm_u_cmm_decoder_N_58543), + .I1(com_cmm_u_cmm_decoder_bar4_32_hit_nc_3_i_0_0_0_1_5508), + .I2(com_cmm_u_cmm_decoder_un11_bar4_32_hit_nc_8_5507), + .I3(com_cmm_u_cmm_decoder_un18_bar4_32_hit_nc_7_5506), + .LO(com_cmm_u_cmm_decoder_N_18054_i) + ); + defparam com_cmm_u_cmm_decoder_bar3_32_hit_nc_3_i_0_0_0.INIT = 16'hCC4C; + LUT4_L com_cmm_u_cmm_decoder_bar3_32_hit_nc_3_i_0_0_0 ( + .I0(com_cmm_bar3_reg[2]), + .I1(com_cmm_u_cmm_decoder_bar3_32_hit_nc_3_i_0_0_0_2_5510), + .I2(com_cmm_u_cmm_decoder_bar34_64_hit_high_3_1), + .I3(com_cmm_u_cmm_decoder_un18_bar3_32_hit_nc_7_5509), + .LO(com_cmm_u_cmm_decoder_N_18227_i) + ); + defparam com_cmm_u_cmm_decoder_bar6_32_hit.INIT = 4'h8; + LUT2_L com_cmm_u_cmm_decoder_bar6_32_hit ( + .I0(com_cmm_u_cmm_decoder_bar6_32_hit_nc_5526), + .I1(com_cmm_u_cmm_decoder_bar6_eq_raddr_5514), + .LO(com_cmm_u_cmm_decoder_bar6_32_hit_5538) + ); + defparam com_cmm_u_cmm_decoder_N_18563_i.INIT = 16'hF888; + LUT4_L com_cmm_u_cmm_decoder_N_18563_i ( + .I0(com_cmm_u_cmm_decoder_bar5_32_hit_nc_5527), + .I1(com_cmm_u_cmm_decoder_bar5_eq_raddr_5515), + .I2(com_cmm_u_cmm_decoder_bar45_64_hit_high_5521), + .I3(com_cmm_u_cmm_decoder_bar45_64_hit_low_5530), + .LO(com_cmm_u_cmm_decoder_N_18563_i_5539) + ); + defparam com_cmm_u_cmm_decoder_N_18564_i.INIT = 8'h8F; + LUT3_L com_cmm_u_cmm_decoder_N_18564_i ( + .I0(com_cmm_u_cmm_decoder_bar34_64_hit_high_5522), + .I1(com_cmm_u_cmm_decoder_bar34_64_hit_low_5531), + .I2(com_cmm_u_cmm_decoder_bar_hit_7_0_a2_0[4]), + .LO(com_cmm_u_cmm_decoder_N_18564_i_5540) + ); + defparam com_cmm_u_cmm_decoder_N_18565_i.INIT = 8'h8F; + LUT3_L com_cmm_u_cmm_decoder_N_18565_i ( + .I0(com_cmm_u_cmm_decoder_bar23_64_hit_high_5523), + .I1(com_cmm_u_cmm_decoder_bar23_64_hit_low_5532), + .I2(com_cmm_u_cmm_decoder_bar_hit_6_0_a2_0[3]), + .LO(com_cmm_u_cmm_decoder_N_18565_i_5541) + ); + defparam com_cmm_u_cmm_decoder_N_18566_i.INIT = 8'h8F; + LUT3_L com_cmm_u_cmm_decoder_N_18566_i ( + .I0(com_cmm_u_cmm_decoder_bar12_64_hit_high_5524), + .I1(com_cmm_u_cmm_decoder_bar12_64_hit_low_5533), + .I2(com_cmm_u_cmm_decoder_bar_hit_5_0_a2_0[2]), + .LO(com_cmm_u_cmm_decoder_N_18566_i_5542) + ); + defparam com_cmm_u_cmm_decoder_N_18567_i.INIT = 8'h8F; + LUT3_L com_cmm_u_cmm_decoder_N_18567_i ( + .I0(com_cmm_u_cmm_decoder_bar01_64_hit_high_5525), + .I1(com_cmm_u_cmm_decoder_bar01_64_hit_low_5534), + .I2(com_cmm_u_cmm_decoder_bar_hit_4_0_a2_0[1]), + .LO(com_cmm_u_cmm_decoder_N_18567_i_5543) + ); + defparam com_cmm_u_cmm_decoder_N_18568_i.INIT = 16'hF888; + LUT4_L com_cmm_u_cmm_decoder_N_18568_i ( + .I0(com_cmm_u_cmm_decoder_bar01_64_hit_high_5525), + .I1(com_cmm_u_cmm_decoder_bar01_64_hit_low_5534), + .I2(com_cmm_u_cmm_decoder_bar0_32_hit_nc_5535), + .I3(com_cmm_u_cmm_decoder_bar0_eq_raddr_5520), + .LO(com_cmm_u_cmm_decoder_N_18568_i_5544) + ); + defparam com_cmm_u_cmm_decoder_bar12_64_hit_high_3_0_a2_0_a2_0_a2_0_a2_0.INIT = 8'h02; + LUT3 com_cmm_u_cmm_decoder_bar12_64_hit_high_3_0_a2_0_a2_0_a2_0_a2_0 ( + .I0(com_cmm_bar1_reg[2]), + .I1(com_cmm_bar1_reg[1]), + .I2(com_cmm_bar1_reg[0]), + .O(com_cmm_u_cmm_decoder_N_58555) + ); + defparam com_cmm_u_cmm_decoder_bar2_32_hit_nc_3_i_0_0_0_0.INIT = 8'h01; + LUT3_L com_cmm_u_cmm_decoder_bar2_32_hit_nc_3_i_0_0_0_0 ( + .I0(com_cmm_u_cmm_decoder_N_58555), + .I1(com_cmm_pme_pmcsr[1]), + .I2(com_cmm_pme_pmcsr[0]), + .LO(com_cmm_u_cmm_decoder_bar2_32_hit_nc_3_i_0_0_0_0_5511) + ); + defparam com_cmm_u_cmm_decoder_bar1_32_hit_nc_3_i_0_0_0_0.INIT = 8'h01; + LUT3_L com_cmm_u_cmm_decoder_bar1_32_hit_nc_3_i_0_0_0_0 ( + .I0(com_cmm_u_cmm_decoder_N_58582), + .I1(com_cmm_pme_pmcsr[1]), + .I2(com_cmm_pme_pmcsr[0]), + .LO(com_cmm_u_cmm_decoder_bar1_32_hit_nc_3_i_0_0_0_0_5512) + ); + MUXCY com_cmm_u_cmm_decoder_bar4_eq_raddr_3_0_I_10 ( + .CI(com_cmm_u_cmm_decoder_data_tmp_9[12]), + .DI(com_cmm_u_cmm_decoder_GND_5513), + .O(com_cmm_u_cmm_decoder_bar4_eq_raddr_3), + .S(com_cmm_u_cmm_decoder_N_99) + ); + MUXCY com_cmm_u_cmm_decoder_bar3_eq_raddr_3_0_I_10 ( + .CI(com_cmm_u_cmm_decoder_data_tmp_8[12]), + .DI(com_cmm_u_cmm_decoder_GND_5513), + .O(com_cmm_u_cmm_decoder_bar3_eq_raddr_3), + .S(com_cmm_u_cmm_decoder_N_99_0) + ); + MUXCY com_cmm_u_cmm_decoder_bar2_eq_raddr_3_0_I_10 ( + .CI(com_cmm_u_cmm_decoder_data_tmp_7[12]), + .DI(com_cmm_u_cmm_decoder_GND_5513), + .O(com_cmm_u_cmm_decoder_bar2_eq_raddr_3), + .S(com_cmm_u_cmm_decoder_N_99_1) + ); + MUXCY com_cmm_u_cmm_decoder_bar1_eq_raddr_3_0_I_10 ( + .CI(com_cmm_u_cmm_decoder_data_tmp_6[12]), + .DI(com_cmm_u_cmm_decoder_GND_5513), + .O(com_cmm_u_cmm_decoder_bar1_eq_raddr_3), + .S(com_cmm_u_cmm_decoder_N_99_2) + ); + MUXCY com_cmm_u_cmm_decoder_bar0_eq_raddr_3_0_I_10 ( + .CI(com_cmm_u_cmm_decoder_data_tmp_5[12]), + .DI(com_cmm_u_cmm_decoder_GND_5513), + .O(com_cmm_u_cmm_decoder_bar0_eq_raddr_3), + .S(com_cmm_u_cmm_decoder_N_99_3) + ); + MUXCY com_cmm_u_cmm_decoder_un9_bar45_64_hit_high_0_I_10 ( + .CI(com_cmm_u_cmm_decoder_data_tmp_4[12]), + .DI(com_cmm_u_cmm_decoder_GND_5513), + .O(com_cmm_u_cmm_decoder_I_10), + .S(com_cmm_u_cmm_decoder_N_99_4) + ); + MUXCY com_cmm_u_cmm_decoder_un9_bar34_64_hit_high_0_I_10 ( + .CI(com_cmm_u_cmm_decoder_data_tmp_3[12]), + .DI(com_cmm_u_cmm_decoder_GND_5513), + .O(com_cmm_u_cmm_decoder_I_10_0), + .S(com_cmm_u_cmm_decoder_N_99_5) + ); + MUXCY com_cmm_u_cmm_decoder_un9_bar23_64_hit_high_0_I_10 ( + .CI(com_cmm_u_cmm_decoder_data_tmp_2[12]), + .DI(com_cmm_u_cmm_decoder_GND_5513), + .O(com_cmm_u_cmm_decoder_I_10_1), + .S(com_cmm_u_cmm_decoder_N_99_6) + ); + MUXCY com_cmm_u_cmm_decoder_un9_bar12_64_hit_high_0_I_10 ( + .CI(com_cmm_u_cmm_decoder_data_tmp_1[12]), + .DI(com_cmm_u_cmm_decoder_GND_5513), + .O(com_cmm_u_cmm_decoder_I_10_2), + .S(com_cmm_u_cmm_decoder_N_99_7) + ); + MUXCY com_cmm_u_cmm_decoder_un9_bar01_64_hit_high_0_I_10 ( + .CI(com_cmm_u_cmm_decoder_data_tmp_0[12]), + .DI(com_cmm_u_cmm_decoder_GND_5513), + .O(com_cmm_u_cmm_decoder_I_10_3), + .S(com_cmm_u_cmm_decoder_N_99_8) + ); + MUXCY com_cmm_u_cmm_decoder_bar6_eq_raddr_3_0_I_91 ( + .CI(com_cmm_u_cmm_decoder_data_tmp[9]), + .DI(com_cmm_u_cmm_decoder_GND_5513), + .O(com_cmm_u_cmm_decoder_bar6_eq_raddr_3), + .S(com_cmm_u_cmm_decoder_N_7_i) + ); + MUXCY com_cmm_u_cmm_decoder_bar5_eq_raddr_3_0_I_10 ( + .CI(com_cmm_u_cmm_decoder_data_tmp[12]), + .DI(com_cmm_u_cmm_decoder_GND_5513), + .O(com_cmm_u_cmm_decoder_bar5_eq_raddr_3), + .S(com_cmm_u_cmm_decoder_I_10_sf) + ); + MUXCY com_cmm_u_cmm_decoder_un10_bar01_64_hit_low_0_I_28 ( + .CI(com_cmm_u_cmm_decoder_data_tmp_3[14]), + .DI(com_cmm_u_cmm_decoder_GND_5513), + .O(com_cmm_u_cmm_decoder_I_28_5), + .S(com_cmm_u_cmm_decoder_N_99_10) + ); + MUXCY com_cmm_u_cmm_decoder_un10_bar12_64_hit_low_0_I_28 ( + .CI(com_cmm_u_cmm_decoder_data_tmp_2[14]), + .DI(com_cmm_u_cmm_decoder_GND_5513), + .O(com_cmm_u_cmm_decoder_I_28_4), + .S(com_cmm_u_cmm_decoder_N_99_11) + ); + MUXCY com_cmm_u_cmm_decoder_un10_bar23_64_hit_low_0_I_28 ( + .CI(com_cmm_u_cmm_decoder_data_tmp_1[14]), + .DI(com_cmm_u_cmm_decoder_GND_5513), + .O(com_cmm_u_cmm_decoder_I_28_3), + .S(com_cmm_u_cmm_decoder_N_99_12) + ); + MUXCY com_cmm_u_cmm_decoder_un10_bar34_64_hit_low_0_I_28 ( + .CI(com_cmm_u_cmm_decoder_data_tmp_0[14]), + .DI(com_cmm_u_cmm_decoder_GND_5513), + .O(com_cmm_u_cmm_decoder_I_28_2), + .S(com_cmm_u_cmm_decoder_N_99_13) + ); + MUXCY com_cmm_u_cmm_decoder_un10_bar45_64_hit_low_0_I_28 ( + .CI(com_cmm_u_cmm_decoder_data_tmp[14]), + .DI(com_cmm_u_cmm_decoder_GND_5513), + .O(com_cmm_u_cmm_decoder_I_28_1), + .S(com_cmm_u_cmm_decoder_N_99_14) + ); + FDC com_cmm_u_cmm_decoder_bar6_eq_raddr ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_decoder_bar6_eq_raddr_3), + .Q(com_cmm_u_cmm_decoder_bar6_eq_raddr_5514), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_decoder_bar5_eq_raddr ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_decoder_bar5_eq_raddr_3), + .Q(com_cmm_u_cmm_decoder_bar5_eq_raddr_5515), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_decoder_bar4_eq_raddr ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_decoder_bar4_eq_raddr_3), + .Q(com_cmm_u_cmm_decoder_bar4_eq_raddr_5516), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_decoder_bar3_eq_raddr ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_decoder_bar3_eq_raddr_3), + .Q(com_cmm_u_cmm_decoder_bar3_eq_raddr_5517), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_decoder_bar2_eq_raddr ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_decoder_bar2_eq_raddr_3), + .Q(com_cmm_u_cmm_decoder_bar2_eq_raddr_5518), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_decoder_bar1_eq_raddr ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_decoder_bar1_eq_raddr_3), + .Q(com_cmm_u_cmm_decoder_bar1_eq_raddr_5519), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_decoder_bar0_eq_raddr ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_decoder_bar0_eq_raddr_3), + .Q(com_cmm_u_cmm_decoder_bar0_eq_raddr_5520), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_decoder_bar45_64_hit_high ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_decoder_bar45_64_hit_high_3), + .Q(com_cmm_u_cmm_decoder_bar45_64_hit_high_5521), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_decoder_bar34_64_hit_high ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_decoder_bar34_64_hit_high_3), + .Q(com_cmm_u_cmm_decoder_bar34_64_hit_high_5522), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_decoder_bar23_64_hit_high ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_decoder_bar23_64_hit_high_3), + .Q(com_cmm_u_cmm_decoder_bar23_64_hit_high_5523), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_decoder_bar12_64_hit_high ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_decoder_bar12_64_hit_high_3), + .Q(com_cmm_u_cmm_decoder_bar12_64_hit_high_5524), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_decoder_bar01_64_hit_high ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_decoder_bar01_64_hit_high_3), + .Q(com_cmm_u_cmm_decoder_bar01_64_hit_high_5525), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_decoder_bar6_32_hit_nc ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_decoder_bar6_32_hit_nc_3), + .Q(com_cmm_u_cmm_decoder_bar6_32_hit_nc_5526), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_decoder_bar5_32_hit_nc ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_decoder_N_17867_i), + .Q(com_cmm_u_cmm_decoder_bar5_32_hit_nc_5527), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_decoder_bar2_32_hit_nc ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_decoder_N_18225_i), + .Q(com_cmm_u_cmm_decoder_bar2_32_hit_nc_5528), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_decoder_bar1_32_hit_nc ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_decoder_N_18403_i), + .Q(com_cmm_u_cmm_decoder_bar1_32_hit_nc_5529), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_decoder_bar45_64_hit_low ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_decoder_bar45_64_hit_low_3), + .Q(com_cmm_u_cmm_decoder_bar45_64_hit_low_5530), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_decoder_bar34_64_hit_low ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_decoder_bar34_64_hit_low_3), + .Q(com_cmm_u_cmm_decoder_bar34_64_hit_low_5531), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_decoder_bar23_64_hit_low ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_decoder_bar23_64_hit_low_3), + .Q(com_cmm_u_cmm_decoder_bar23_64_hit_low_5532), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_decoder_bar12_64_hit_low ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_decoder_bar12_64_hit_low_3), + .Q(com_cmm_u_cmm_decoder_bar12_64_hit_low_5533), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_decoder_bar01_64_hit_low ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_decoder_bar01_64_hit_low_3), + .Q(com_cmm_u_cmm_decoder_bar01_64_hit_low_5534), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_decoder_bar0_32_hit_nc ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_decoder_N_18400_i), + .Q(com_cmm_u_cmm_decoder_bar0_32_hit_nc_5535), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_decoder_bar4_32_hit_nc ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_decoder_N_18054_i), + .Q(com_cmm_u_cmm_decoder_bar4_32_hit_nc_5536), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_decoder_bar3_32_hit_nc ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_decoder_N_18227_i), + .Q(com_cmm_u_cmm_decoder_bar3_32_hit_nc_5537), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_decoder_bar_hit_6_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_decoder_bar6_32_hit_5538), + .Q(com_cmmt_rbar_hit[6]), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_decoder_bar_hit_5_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_decoder_N_18563_i_5539), + .Q(com_cmmt_rbar_hit[5]), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_decoder_bar_hit_4_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_decoder_N_18564_i_5540), + .Q(com_cmmt_rbar_hit[4]), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_decoder_bar_hit_3_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_decoder_N_18565_i_5541), + .Q(com_cmmt_rbar_hit[3]), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_decoder_bar_hit_2_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_decoder_N_18566_i_5542), + .Q(com_cmmt_rbar_hit[2]), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_decoder_bar_hit_1_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_decoder_N_18567_i_5543), + .Q(com_cmmt_rbar_hit[1]), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_decoder_bar_hit_0_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_decoder_N_18568_i_5544), + .Q(com_cmmt_rbar_hit[0]), + .CLR(com_cmm_rst_351) + ); + defparam com_cmm_u_cmm_decoder_un10_bar45_64_hit_low_0_I_36.INIT = 16'h0903; + LUT4 com_cmm_u_cmm_decoder_un10_bar45_64_hit_low_0_I_36 ( + .I0(cfg_cfg_6102[227]), + .I1(com_cmm_bar5_reg[3]), + .I2(com_cmm_u_cmm_decoder_N_102_13), + .I3(com_cmmt_raddr[35]), + .O(com_cmm_u_cmm_decoder_N_99_14) + ); + defparam com_cmm_u_cmm_decoder_un10_bar34_64_hit_low_0_I_36.INIT = 16'h0903; + LUT4 com_cmm_u_cmm_decoder_un10_bar34_64_hit_low_0_I_36 ( + .I0(cfg_cfg_6102[194]), + .I1(com_cmm_bar4_reg[2]), + .I2(com_cmm_u_cmm_decoder_N_102_12), + .I3(com_cmmt_raddr[34]), + .O(com_cmm_u_cmm_decoder_N_99_13) + ); + defparam com_cmm_u_cmm_decoder_un10_bar23_64_hit_low_0_I_36.INIT = 16'h0903; + LUT4 com_cmm_u_cmm_decoder_un10_bar23_64_hit_low_0_I_36 ( + .I0(cfg_cfg_6102[162]), + .I1(com_cmm_bar3_reg[2]), + .I2(com_cmm_u_cmm_decoder_N_102_11), + .I3(com_cmmt_raddr[34]), + .O(com_cmm_u_cmm_decoder_N_99_12) + ); + defparam com_cmm_u_cmm_decoder_un10_bar12_64_hit_low_0_I_36.INIT = 16'h0903; + LUT4 com_cmm_u_cmm_decoder_un10_bar12_64_hit_low_0_I_36 ( + .I0(cfg_cfg_6102[130]), + .I1(com_cmm_bar2_reg[2]), + .I2(com_cmm_u_cmm_decoder_N_102_10), + .I3(com_cmmt_raddr[34]), + .O(com_cmm_u_cmm_decoder_N_99_11) + ); + defparam com_cmm_u_cmm_decoder_un10_bar01_64_hit_low_0_I_36.INIT = 16'h0903; + LUT4 com_cmm_u_cmm_decoder_un10_bar01_64_hit_low_0_I_36 ( + .I0(cfg_cfg_6102[98]), + .I1(com_cmm_bar1_reg[2]), + .I2(com_cmm_u_cmm_decoder_N_102_9), + .I3(com_cmmt_raddr[34]), + .O(com_cmm_u_cmm_decoder_N_99_10) + ); + defparam com_cmm_u_cmm_decoder_bar5_eq_raddr_3_0_I_10_sf.INIT = 4'h2; + LUT1 com_cmm_u_cmm_decoder_bar5_eq_raddr_3_0_I_10_sf ( + .I0(com_cmm_u_cmm_decoder_N_99_9), + .O(com_cmm_u_cmm_decoder_I_10_sf) + ); + defparam com_cmm_u_cmm_decoder_bar6_eq_raddr_3_0_N_7_i.INIT = 8'h93; + LUT3 com_cmm_u_cmm_decoder_bar6_eq_raddr_3_0_N_7_i ( + .I0(cfg_cfg_6102[351]), + .I1(com_cmm_xrom_reg_31_), + .I2(com_cmmt_raddr[63]), + .O(com_cmm_u_cmm_decoder_N_7_i) + ); + defparam com_cmm_u_cmm_decoder_un9_bar01_64_hit_high_0_I_18.INIT = 16'h0903; + LUT4 com_cmm_u_cmm_decoder_un9_bar01_64_hit_high_0_I_18 ( + .I0(cfg_cfg_6102[94]), + .I1(com_cmm_bar0_reg_30_), + .I2(com_cmm_u_cmm_decoder_N_102_8), + .I3(com_cmmt_raddr[30]), + .O(com_cmm_u_cmm_decoder_N_99_8) + ); + defparam com_cmm_u_cmm_decoder_un9_bar12_64_hit_high_0_I_18.INIT = 16'h0903; + LUT4 com_cmm_u_cmm_decoder_un9_bar12_64_hit_high_0_I_18 ( + .I0(cfg_cfg_6102[126]), + .I1(com_cmm_bar1_reg[30]), + .I2(com_cmm_u_cmm_decoder_N_102_7), + .I3(com_cmmt_raddr[30]), + .O(com_cmm_u_cmm_decoder_N_99_7) + ); + defparam com_cmm_u_cmm_decoder_un9_bar23_64_hit_high_0_I_18.INIT = 16'h0903; + LUT4 com_cmm_u_cmm_decoder_un9_bar23_64_hit_high_0_I_18 ( + .I0(cfg_cfg_6102[158]), + .I1(com_cmm_bar2_reg[30]), + .I2(com_cmm_u_cmm_decoder_N_102_6), + .I3(com_cmmt_raddr[30]), + .O(com_cmm_u_cmm_decoder_N_99_6) + ); + defparam com_cmm_u_cmm_decoder_un9_bar34_64_hit_high_0_I_18.INIT = 16'h0903; + LUT4 com_cmm_u_cmm_decoder_un9_bar34_64_hit_high_0_I_18 ( + .I0(cfg_cfg_6102[190]), + .I1(com_cmm_bar3_reg[30]), + .I2(com_cmm_u_cmm_decoder_N_102_5), + .I3(com_cmmt_raddr[30]), + .O(com_cmm_u_cmm_decoder_N_99_5) + ); + defparam com_cmm_u_cmm_decoder_un9_bar45_64_hit_high_0_I_18.INIT = 16'h0903; + LUT4 com_cmm_u_cmm_decoder_un9_bar45_64_hit_high_0_I_18 ( + .I0(cfg_cfg_6102[222]), + .I1(com_cmm_bar4_reg[30]), + .I2(com_cmm_u_cmm_decoder_N_102_4), + .I3(com_cmmt_raddr[30]), + .O(com_cmm_u_cmm_decoder_N_99_4) + ); + defparam com_cmm_u_cmm_decoder_bar0_eq_raddr_3_0_I_18.INIT = 16'h0903; + LUT4 com_cmm_u_cmm_decoder_bar0_eq_raddr_3_0_I_18 ( + .I0(cfg_cfg_6102[94]), + .I1(com_cmm_bar0_reg_30_), + .I2(com_cmm_u_cmm_decoder_N_102_3), + .I3(com_cmmt_raddr[62]), + .O(com_cmm_u_cmm_decoder_N_99_3) + ); + defparam com_cmm_u_cmm_decoder_bar1_eq_raddr_3_0_I_18.INIT = 16'h0903; + LUT4 com_cmm_u_cmm_decoder_bar1_eq_raddr_3_0_I_18 ( + .I0(cfg_cfg_6102[126]), + .I1(com_cmm_bar1_reg[30]), + .I2(com_cmm_u_cmm_decoder_N_102_2), + .I3(com_cmmt_raddr[62]), + .O(com_cmm_u_cmm_decoder_N_99_2) + ); + defparam com_cmm_u_cmm_decoder_bar2_eq_raddr_3_0_I_18.INIT = 16'h0903; + LUT4 com_cmm_u_cmm_decoder_bar2_eq_raddr_3_0_I_18 ( + .I0(cfg_cfg_6102[158]), + .I1(com_cmm_bar2_reg[30]), + .I2(com_cmm_u_cmm_decoder_N_102_1), + .I3(com_cmmt_raddr[62]), + .O(com_cmm_u_cmm_decoder_N_99_1) + ); + defparam com_cmm_u_cmm_decoder_bar3_eq_raddr_3_0_I_18.INIT = 16'h0903; + LUT4 com_cmm_u_cmm_decoder_bar3_eq_raddr_3_0_I_18 ( + .I0(cfg_cfg_6102[190]), + .I1(com_cmm_bar3_reg[30]), + .I2(com_cmm_u_cmm_decoder_N_102_0), + .I3(com_cmmt_raddr[62]), + .O(com_cmm_u_cmm_decoder_N_99_0) + ); + defparam com_cmm_u_cmm_decoder_bar4_eq_raddr_3_0_I_18.INIT = 16'h0903; + LUT4 com_cmm_u_cmm_decoder_bar4_eq_raddr_3_0_I_18 ( + .I0(cfg_cfg_6102[222]), + .I1(com_cmm_bar4_reg[30]), + .I2(com_cmm_u_cmm_decoder_N_102), + .I3(com_cmmt_raddr[62]), + .O(com_cmm_u_cmm_decoder_N_99) + ); + defparam com_cmm_u_cmm_decoder_un7_bar6_32_hit_nc_5_and_0_a2_0_a2_0_a2_0_a2.INIT = 16'h0001; + LUT4 com_cmm_u_cmm_decoder_un7_bar6_32_hit_nc_5_and_0_a2_0_a2_0_a2_0_a2 ( + .I0(cfg_cfg_6102[347]), + .I1(cfg_cfg_6102[348]), + .I2(cfg_cfg_6102[349]), + .I3(cfg_cfg_6102[350]), + .O(com_cmm_u_cmm_decoder_un7_bar6_32_hit_nc_5_and) + ); + defparam com_cmm_u_cmm_decoder_un7_bar6_32_hit_nc_4_and_0_a2_0_a2_0_a2.INIT = 16'h0001; + LUT4 com_cmm_u_cmm_decoder_un7_bar6_32_hit_nc_4_and_0_a2_0_a2_0_a2 ( + .I0(cfg_cfg_6102[343]), + .I1(cfg_cfg_6102[344]), + .I2(cfg_cfg_6102[345]), + .I3(cfg_cfg_6102[346]), + .O(com_cmm_u_cmm_decoder_un7_bar6_32_hit_nc_4_and) + ); + defparam com_cmm_u_cmm_decoder_un7_bar6_32_hit_nc_3_and_0_a2_0_a2.INIT = 16'h0001; + LUT4 com_cmm_u_cmm_decoder_un7_bar6_32_hit_nc_3_and_0_a2_0_a2 ( + .I0(cfg_cfg_6102[339]), + .I1(cfg_cfg_6102[340]), + .I2(cfg_cfg_6102[341]), + .I3(cfg_cfg_6102[342]), + .O(com_cmm_u_cmm_decoder_un7_bar6_32_hit_nc_3_and) + ); + defparam com_cmm_u_cmm_decoder_un7_bar6_32_hit_nc_2_and_0_a2_0_a2_0_a2_0_a2.INIT = 16'h0001; + LUT4 com_cmm_u_cmm_decoder_un7_bar6_32_hit_nc_2_and_0_a2_0_a2_0_a2_0_a2 ( + .I0(cfg_cfg_6102[335]), + .I1(cfg_cfg_6102[336]), + .I2(cfg_cfg_6102[337]), + .I3(cfg_cfg_6102[338]), + .O(com_cmm_u_cmm_decoder_un7_bar6_32_hit_nc_2_and) + ); + defparam com_cmm_u_cmm_decoder_un7_bar6_32_hit_nc_1_and_0_a2_0_a2_0_a2_0_a2.INIT = 16'h0001; + LUT4 com_cmm_u_cmm_decoder_un7_bar6_32_hit_nc_1_and_0_a2_0_a2_0_a2_0_a2 ( + .I0(cfg_cfg_6102[331]), + .I1(cfg_cfg_6102[332]), + .I2(cfg_cfg_6102[333]), + .I3(cfg_cfg_6102[334]), + .O(com_cmm_u_cmm_decoder_un7_bar6_32_hit_nc_1_and) + ); + defparam com_cmm_u_cmm_decoder_un7_bar6_32_hit_nc_0_and.INIT = 16'h0001; + LUT4 com_cmm_u_cmm_decoder_un7_bar6_32_hit_nc_0_and ( + .I0(cfg_cfg_6102[327]), + .I1(cfg_cfg_6102[328]), + .I2(cfg_cfg_6102[329]), + .I3(cfg_cfg_6102[330]), + .O(com_cmm_u_cmm_decoder_un7_bar6_32_hit_nc_0_and_5545) + ); + defparam com_cmm_u_cmm_decoder_un11_bar0_32_hit_nc_7_and_0_a2_0_a2_0_a2.INIT = 16'h0001; + LUT4 com_cmm_u_cmm_decoder_un11_bar0_32_hit_nc_7_and_0_a2_0_a2_0_a2 ( + .I0(cfg_cfg_6102[92]), + .I1(cfg_cfg_6102[93]), + .I2(cfg_cfg_6102[94]), + .I3(cfg_cfg_6102[95]), + .O(com_cmm_u_cmm_decoder_un11_bar0_32_hit_nc_7_and) + ); + defparam com_cmm_u_cmm_decoder_un11_bar0_32_hit_nc_6_and_0_a2_0_a2_0_a2.INIT = 16'h0001; + LUT4 com_cmm_u_cmm_decoder_un11_bar0_32_hit_nc_6_and_0_a2_0_a2_0_a2 ( + .I0(cfg_cfg_6102[88]), + .I1(cfg_cfg_6102[89]), + .I2(cfg_cfg_6102[90]), + .I3(cfg_cfg_6102[91]), + .O(com_cmm_u_cmm_decoder_un11_bar0_32_hit_nc_6_and) + ); + defparam com_cmm_u_cmm_decoder_un11_bar0_32_hit_nc_5_and_0_a2_0_a2_0_a2.INIT = 16'h0001; + LUT4 com_cmm_u_cmm_decoder_un11_bar0_32_hit_nc_5_and_0_a2_0_a2_0_a2 ( + .I0(cfg_cfg_6102[84]), + .I1(cfg_cfg_6102[85]), + .I2(cfg_cfg_6102[86]), + .I3(cfg_cfg_6102[87]), + .O(com_cmm_u_cmm_decoder_un11_bar0_32_hit_nc_5_and) + ); + defparam com_cmm_u_cmm_decoder_un11_bar0_32_hit_nc_4_and_0_a2_0_a2_0_a2_0_a2.INIT = 16'h0001; + LUT4 com_cmm_u_cmm_decoder_un11_bar0_32_hit_nc_4_and_0_a2_0_a2_0_a2_0_a2 ( + .I0(cfg_cfg_6102[80]), + .I1(cfg_cfg_6102[81]), + .I2(cfg_cfg_6102[82]), + .I3(cfg_cfg_6102[83]), + .O(com_cmm_u_cmm_decoder_un11_bar0_32_hit_nc_4_and) + ); + defparam com_cmm_u_cmm_decoder_un11_bar0_32_hit_nc_3_and_0_a2_0_a2_0_a2_0_a2.INIT = 16'h0001; + LUT4 com_cmm_u_cmm_decoder_un11_bar0_32_hit_nc_3_and_0_a2_0_a2_0_a2_0_a2 ( + .I0(cfg_cfg_6102[76]), + .I1(cfg_cfg_6102[77]), + .I2(cfg_cfg_6102[78]), + .I3(cfg_cfg_6102[79]), + .O(com_cmm_u_cmm_decoder_un11_bar0_32_hit_nc_3_and) + ); + defparam com_cmm_u_cmm_decoder_un11_bar0_32_hit_nc_2_and_0_a2_0_a2_0_a2.INIT = 16'h0001; + LUT4 com_cmm_u_cmm_decoder_un11_bar0_32_hit_nc_2_and_0_a2_0_a2_0_a2 ( + .I0(cfg_cfg_6102[72]), + .I1(cfg_cfg_6102[73]), + .I2(cfg_cfg_6102[74]), + .I3(cfg_cfg_6102[75]), + .O(com_cmm_u_cmm_decoder_un11_bar0_32_hit_nc_2_and) + ); + defparam com_cmm_u_cmm_decoder_un11_bar0_32_hit_nc_1_and_0_a2_0_a2_0_a2_0_a2.INIT = 16'h0001; + LUT4 com_cmm_u_cmm_decoder_un11_bar0_32_hit_nc_1_and_0_a2_0_a2_0_a2_0_a2 ( + .I0(cfg_cfg_6102[68]), + .I1(cfg_cfg_6102[69]), + .I2(cfg_cfg_6102[70]), + .I3(cfg_cfg_6102[71]), + .O(com_cmm_u_cmm_decoder_un11_bar0_32_hit_nc_1_and) + ); + defparam com_cmm_u_cmm_decoder_un11_bar0_32_hit_nc_0_and_0_a2_0_a2_0_a2_0_a2.INIT = 16'h0001; + LUT4 com_cmm_u_cmm_decoder_un11_bar0_32_hit_nc_0_and_0_a2_0_a2_0_a2_0_a2 ( + .I0(cfg_cfg_6102[64]), + .I1(cfg_cfg_6102[65]), + .I2(cfg_cfg_6102[66]), + .I3(cfg_cfg_6102[67]), + .O(com_cmm_u_cmm_decoder_un11_bar0_32_hit_nc_0_and) + ); + defparam com_cmm_u_cmm_decoder_un18_bar0_32_hit_nc_7_and_0_a2_0_a2.INIT = 16'h0001; + LUT4 com_cmm_u_cmm_decoder_un18_bar0_32_hit_nc_7_and_0_a2_0_a2 ( + .I0(com_cmm_bar1_reg[28]), + .I1(com_cmm_bar1_reg[29]), + .I2(com_cmm_bar1_reg[30]), + .I3(com_cmm_bar1_reg[31]), + .O(com_cmm_u_cmm_decoder_un18_bar0_32_hit_nc_7_and) + ); + defparam com_cmm_u_cmm_decoder_un18_bar0_32_hit_nc_6_and_0_a2_0_a2.INIT = 16'h0001; + LUT4 com_cmm_u_cmm_decoder_un18_bar0_32_hit_nc_6_and_0_a2_0_a2 ( + .I0(com_cmm_bar1_reg[24]), + .I1(com_cmm_bar1_reg[25]), + .I2(com_cmm_bar1_reg[26]), + .I3(com_cmm_bar1_reg[27]), + .O(com_cmm_u_cmm_decoder_un18_bar0_32_hit_nc_6_and) + ); + defparam com_cmm_u_cmm_decoder_un18_bar0_32_hit_nc_5_and_0_a2_0_a2.INIT = 16'h0001; + LUT4 com_cmm_u_cmm_decoder_un18_bar0_32_hit_nc_5_and_0_a2_0_a2 ( + .I0(com_cmm_bar1_reg[20]), + .I1(com_cmm_bar1_reg[21]), + .I2(com_cmm_bar1_reg[22]), + .I3(com_cmm_bar1_reg[23]), + .O(com_cmm_u_cmm_decoder_un18_bar0_32_hit_nc_5_and) + ); + defparam com_cmm_u_cmm_decoder_un18_bar0_32_hit_nc_4_and_0_a2_0_a2.INIT = 16'h0001; + LUT4 com_cmm_u_cmm_decoder_un18_bar0_32_hit_nc_4_and_0_a2_0_a2 ( + .I0(com_cmm_bar1_reg[16]), + .I1(com_cmm_bar1_reg[17]), + .I2(com_cmm_bar1_reg[18]), + .I3(com_cmm_bar1_reg[19]), + .O(com_cmm_u_cmm_decoder_un18_bar0_32_hit_nc_4_and) + ); + defparam com_cmm_u_cmm_decoder_un18_bar0_32_hit_nc_3_and_0_a2_0_a2.INIT = 16'h0001; + LUT4 com_cmm_u_cmm_decoder_un18_bar0_32_hit_nc_3_and_0_a2_0_a2 ( + .I0(com_cmm_bar1_reg[12]), + .I1(com_cmm_bar1_reg[13]), + .I2(com_cmm_bar1_reg[14]), + .I3(com_cmm_bar1_reg[15]), + .O(com_cmm_u_cmm_decoder_un18_bar0_32_hit_nc_3_and) + ); + defparam com_cmm_u_cmm_decoder_un18_bar0_32_hit_nc_2_and_0_a2_0_a2.INIT = 16'h0001; + LUT4 com_cmm_u_cmm_decoder_un18_bar0_32_hit_nc_2_and_0_a2_0_a2 ( + .I0(com_cmm_bar1_reg[8]), + .I1(com_cmm_bar1_reg[9]), + .I2(com_cmm_bar1_reg[10]), + .I3(com_cmm_bar1_reg[11]), + .O(com_cmm_u_cmm_decoder_un18_bar0_32_hit_nc_2_and) + ); + defparam com_cmm_u_cmm_decoder_un18_bar0_32_hit_nc_1_and_0_a2_0_a2.INIT = 16'h0001; + LUT4 com_cmm_u_cmm_decoder_un18_bar0_32_hit_nc_1_and_0_a2_0_a2 ( + .I0(com_cmm_bar1_reg[4]), + .I1(com_cmm_bar1_reg[5]), + .I2(com_cmm_bar1_reg[6]), + .I3(com_cmm_bar1_reg[7]), + .O(com_cmm_u_cmm_decoder_un18_bar0_32_hit_nc_1_and) + ); + defparam com_cmm_u_cmm_decoder_un18_bar0_32_hit_nc_0_and_0_a2_0_a2_0_a2_0_a2.INIT = 8'h10; + LUT3 com_cmm_u_cmm_decoder_un18_bar0_32_hit_nc_0_and_0_a2_0_a2_0_a2_0_a2 ( + .I0(com_cmm_bar1_reg[2]), + .I1(com_cmm_bar1_reg[3]), + .I2(com_cmm_u_cmm_decoder_un18_bar0_32_hit_nc_0_and_1), + .O(com_cmm_u_cmm_decoder_un18_bar0_32_hit_nc_0_and) + ); + defparam com_cmm_u_cmm_decoder_un18_bar1_32_hit_nc_7_and_0_a2_0_a2.INIT = 16'h0001; + LUT4 com_cmm_u_cmm_decoder_un18_bar1_32_hit_nc_7_and_0_a2_0_a2 ( + .I0(com_cmm_bar2_reg[28]), + .I1(com_cmm_bar2_reg[29]), + .I2(com_cmm_bar2_reg[30]), + .I3(com_cmm_bar2_reg[31]), + .O(com_cmm_u_cmm_decoder_un18_bar1_32_hit_nc_7_and) + ); + defparam com_cmm_u_cmm_decoder_un18_bar1_32_hit_nc_6_and_0_a2_0_a2.INIT = 16'h0001; + LUT4 com_cmm_u_cmm_decoder_un18_bar1_32_hit_nc_6_and_0_a2_0_a2 ( + .I0(com_cmm_bar2_reg[24]), + .I1(com_cmm_bar2_reg[25]), + .I2(com_cmm_bar2_reg[26]), + .I3(com_cmm_bar2_reg[27]), + .O(com_cmm_u_cmm_decoder_un18_bar1_32_hit_nc_6_and) + ); + defparam com_cmm_u_cmm_decoder_un18_bar1_32_hit_nc_5_and_0_a2_0_a2.INIT = 16'h0001; + LUT4 com_cmm_u_cmm_decoder_un18_bar1_32_hit_nc_5_and_0_a2_0_a2 ( + .I0(com_cmm_bar2_reg[20]), + .I1(com_cmm_bar2_reg[21]), + .I2(com_cmm_bar2_reg[22]), + .I3(com_cmm_bar2_reg[23]), + .O(com_cmm_u_cmm_decoder_un18_bar1_32_hit_nc_5_and) + ); + defparam com_cmm_u_cmm_decoder_un18_bar1_32_hit_nc_4_and_0_a2_0_a2.INIT = 16'h0001; + LUT4 com_cmm_u_cmm_decoder_un18_bar1_32_hit_nc_4_and_0_a2_0_a2 ( + .I0(com_cmm_bar2_reg[16]), + .I1(com_cmm_bar2_reg[17]), + .I2(com_cmm_bar2_reg[18]), + .I3(com_cmm_bar2_reg[19]), + .O(com_cmm_u_cmm_decoder_un18_bar1_32_hit_nc_4_and) + ); + defparam com_cmm_u_cmm_decoder_un18_bar1_32_hit_nc_3_and_0_a2_0_a2.INIT = 16'h0001; + LUT4 com_cmm_u_cmm_decoder_un18_bar1_32_hit_nc_3_and_0_a2_0_a2 ( + .I0(com_cmm_bar2_reg[12]), + .I1(com_cmm_bar2_reg[13]), + .I2(com_cmm_bar2_reg[14]), + .I3(com_cmm_bar2_reg[15]), + .O(com_cmm_u_cmm_decoder_un18_bar1_32_hit_nc_3_and) + ); + defparam com_cmm_u_cmm_decoder_un18_bar1_32_hit_nc_2_and_0_a2_0_a2.INIT = 16'h0001; + LUT4 com_cmm_u_cmm_decoder_un18_bar1_32_hit_nc_2_and_0_a2_0_a2 ( + .I0(com_cmm_bar2_reg[8]), + .I1(com_cmm_bar2_reg[9]), + .I2(com_cmm_bar2_reg[10]), + .I3(com_cmm_bar2_reg[11]), + .O(com_cmm_u_cmm_decoder_un18_bar1_32_hit_nc_2_and) + ); + defparam com_cmm_u_cmm_decoder_un18_bar1_32_hit_nc_1_and_0_a2_0_a2.INIT = 16'h0001; + LUT4 com_cmm_u_cmm_decoder_un18_bar1_32_hit_nc_1_and_0_a2_0_a2 ( + .I0(com_cmm_bar2_reg[4]), + .I1(com_cmm_bar2_reg[5]), + .I2(com_cmm_bar2_reg[6]), + .I3(com_cmm_bar2_reg[7]), + .O(com_cmm_u_cmm_decoder_un18_bar1_32_hit_nc_1_and) + ); + defparam com_cmm_u_cmm_decoder_un18_bar1_32_hit_nc_0_and_0_a2_0_a2_0_a2_0_a2.INIT = 8'h10; + LUT3 com_cmm_u_cmm_decoder_un18_bar1_32_hit_nc_0_and_0_a2_0_a2_0_a2_0_a2 ( + .I0(com_cmm_bar2_reg[2]), + .I1(com_cmm_bar2_reg[3]), + .I2(com_cmm_u_cmm_decoder_un18_bar1_32_hit_nc_0_and_1), + .O(com_cmm_u_cmm_decoder_un18_bar1_32_hit_nc_0_and) + ); + defparam com_cmm_u_cmm_decoder_un18_bar2_32_hit_nc_7_and_0_a2_0_a2.INIT = 16'h0001; + LUT4 com_cmm_u_cmm_decoder_un18_bar2_32_hit_nc_7_and_0_a2_0_a2 ( + .I0(com_cmm_bar3_reg[28]), + .I1(com_cmm_bar3_reg[29]), + .I2(com_cmm_bar3_reg[30]), + .I3(com_cmm_bar3_reg[31]), + .O(com_cmm_u_cmm_decoder_un18_bar2_32_hit_nc_7_and) + ); + defparam com_cmm_u_cmm_decoder_un18_bar2_32_hit_nc_6_and_0_a2_0_a2.INIT = 16'h0001; + LUT4 com_cmm_u_cmm_decoder_un18_bar2_32_hit_nc_6_and_0_a2_0_a2 ( + .I0(com_cmm_bar3_reg[24]), + .I1(com_cmm_bar3_reg[25]), + .I2(com_cmm_bar3_reg[26]), + .I3(com_cmm_bar3_reg[27]), + .O(com_cmm_u_cmm_decoder_un18_bar2_32_hit_nc_6_and) + ); + defparam com_cmm_u_cmm_decoder_un18_bar2_32_hit_nc_5_and_0_a2_0_a2.INIT = 16'h0001; + LUT4 com_cmm_u_cmm_decoder_un18_bar2_32_hit_nc_5_and_0_a2_0_a2 ( + .I0(com_cmm_bar3_reg[20]), + .I1(com_cmm_bar3_reg[21]), + .I2(com_cmm_bar3_reg[22]), + .I3(com_cmm_bar3_reg[23]), + .O(com_cmm_u_cmm_decoder_un18_bar2_32_hit_nc_5_and) + ); + defparam com_cmm_u_cmm_decoder_un18_bar2_32_hit_nc_4_and_0_a2_0_a2.INIT = 16'h0001; + LUT4 com_cmm_u_cmm_decoder_un18_bar2_32_hit_nc_4_and_0_a2_0_a2 ( + .I0(com_cmm_bar3_reg[16]), + .I1(com_cmm_bar3_reg[17]), + .I2(com_cmm_bar3_reg[18]), + .I3(com_cmm_bar3_reg[19]), + .O(com_cmm_u_cmm_decoder_un18_bar2_32_hit_nc_4_and) + ); + defparam com_cmm_u_cmm_decoder_un18_bar2_32_hit_nc_3_and_0_a2_0_a2.INIT = 16'h0001; + LUT4 com_cmm_u_cmm_decoder_un18_bar2_32_hit_nc_3_and_0_a2_0_a2 ( + .I0(com_cmm_bar3_reg[12]), + .I1(com_cmm_bar3_reg[13]), + .I2(com_cmm_bar3_reg[14]), + .I3(com_cmm_bar3_reg[15]), + .O(com_cmm_u_cmm_decoder_un18_bar2_32_hit_nc_3_and) + ); + defparam com_cmm_u_cmm_decoder_un18_bar2_32_hit_nc_2_and_0_a2_0_a2.INIT = 16'h0001; + LUT4 com_cmm_u_cmm_decoder_un18_bar2_32_hit_nc_2_and_0_a2_0_a2 ( + .I0(com_cmm_bar3_reg[8]), + .I1(com_cmm_bar3_reg[9]), + .I2(com_cmm_bar3_reg[10]), + .I3(com_cmm_bar3_reg[11]), + .O(com_cmm_u_cmm_decoder_un18_bar2_32_hit_nc_2_and) + ); + defparam com_cmm_u_cmm_decoder_un18_bar2_32_hit_nc_1_and_0_a2.INIT = 16'h0001; + LUT4 com_cmm_u_cmm_decoder_un18_bar2_32_hit_nc_1_and_0_a2 ( + .I0(com_cmm_bar3_reg[4]), + .I1(com_cmm_bar3_reg[5]), + .I2(com_cmm_bar3_reg[6]), + .I3(com_cmm_bar3_reg[7]), + .O(com_cmm_u_cmm_decoder_un18_bar2_32_hit_nc_1_and) + ); + defparam com_cmm_u_cmm_decoder_un18_bar2_32_hit_nc_0_and_0_a2_0_a2_0_a2_0_a2.INIT = 8'h10; + LUT3 com_cmm_u_cmm_decoder_un18_bar2_32_hit_nc_0_and_0_a2_0_a2_0_a2_0_a2 ( + .I0(com_cmm_bar3_reg[2]), + .I1(com_cmm_bar3_reg[3]), + .I2(com_cmm_u_cmm_decoder_bar34_64_hit_high_3_1), + .O(com_cmm_u_cmm_decoder_un18_bar2_32_hit_nc_0_and) + ); + defparam com_cmm_u_cmm_decoder_un18_bar3_32_hit_nc_7_and_0_a2_0_a2_0_a2_0_a2.INIT = 16'h0001; + LUT4 com_cmm_u_cmm_decoder_un18_bar3_32_hit_nc_7_and_0_a2_0_a2_0_a2_0_a2 ( + .I0(com_cmm_bar4_reg[28]), + .I1(com_cmm_bar4_reg[29]), + .I2(com_cmm_bar4_reg[30]), + .I3(com_cmm_bar4_reg[31]), + .O(com_cmm_u_cmm_decoder_un18_bar3_32_hit_nc_7_and) + ); + defparam com_cmm_u_cmm_decoder_un18_bar3_32_hit_nc_6_and_0_a2_0_a2_0_a2_0_a2.INIT = 16'h0001; + LUT4 com_cmm_u_cmm_decoder_un18_bar3_32_hit_nc_6_and_0_a2_0_a2_0_a2_0_a2 ( + .I0(com_cmm_bar4_reg[24]), + .I1(com_cmm_bar4_reg[25]), + .I2(com_cmm_bar4_reg[26]), + .I3(com_cmm_bar4_reg[27]), + .O(com_cmm_u_cmm_decoder_un18_bar3_32_hit_nc_6_and) + ); + defparam com_cmm_u_cmm_decoder_un18_bar3_32_hit_nc_5_and_0_a2_0_a2_0_a2_0_a2.INIT = 16'h0001; + LUT4 com_cmm_u_cmm_decoder_un18_bar3_32_hit_nc_5_and_0_a2_0_a2_0_a2_0_a2 ( + .I0(com_cmm_bar4_reg[20]), + .I1(com_cmm_bar4_reg[21]), + .I2(com_cmm_bar4_reg[22]), + .I3(com_cmm_bar4_reg[23]), + .O(com_cmm_u_cmm_decoder_un18_bar3_32_hit_nc_5_and) + ); + defparam com_cmm_u_cmm_decoder_un18_bar3_32_hit_nc_4_and_0_a2_0_a2_0_a2.INIT = 16'h0001; + LUT4 com_cmm_u_cmm_decoder_un18_bar3_32_hit_nc_4_and_0_a2_0_a2_0_a2 ( + .I0(com_cmm_bar4_reg[16]), + .I1(com_cmm_bar4_reg[17]), + .I2(com_cmm_bar4_reg[18]), + .I3(com_cmm_bar4_reg[19]), + .O(com_cmm_u_cmm_decoder_un18_bar3_32_hit_nc_4_and) + ); + defparam com_cmm_u_cmm_decoder_un18_bar3_32_hit_nc_3_and_0_a2_0_a2_0_a2_0_a2.INIT = 16'h0001; + LUT4 com_cmm_u_cmm_decoder_un18_bar3_32_hit_nc_3_and_0_a2_0_a2_0_a2_0_a2 ( + .I0(com_cmm_bar4_reg[12]), + .I1(com_cmm_bar4_reg[13]), + .I2(com_cmm_bar4_reg[14]), + .I3(com_cmm_bar4_reg[15]), + .O(com_cmm_u_cmm_decoder_un18_bar3_32_hit_nc_3_and) + ); + defparam com_cmm_u_cmm_decoder_un18_bar3_32_hit_nc_2_and_0_a2_0_a2_0_a2.INIT = 16'h0001; + LUT4 com_cmm_u_cmm_decoder_un18_bar3_32_hit_nc_2_and_0_a2_0_a2_0_a2 ( + .I0(com_cmm_bar4_reg[8]), + .I1(com_cmm_bar4_reg[9]), + .I2(com_cmm_bar4_reg[10]), + .I3(com_cmm_bar4_reg[11]), + .O(com_cmm_u_cmm_decoder_un18_bar3_32_hit_nc_2_and) + ); + defparam com_cmm_u_cmm_decoder_un18_bar3_32_hit_nc_1_and_0_a2_0_a2_0_a2.INIT = 16'h0001; + LUT4 com_cmm_u_cmm_decoder_un18_bar3_32_hit_nc_1_and_0_a2_0_a2_0_a2 ( + .I0(com_cmm_bar4_reg[4]), + .I1(com_cmm_bar4_reg[5]), + .I2(com_cmm_bar4_reg[6]), + .I3(com_cmm_bar4_reg[7]), + .O(com_cmm_u_cmm_decoder_un18_bar3_32_hit_nc_1_and) + ); + defparam com_cmm_u_cmm_decoder_un18_bar3_32_hit_nc_0_and_0_a2_0_a2_0_a2_0_a2.INIT = 8'h10; + LUT3 com_cmm_u_cmm_decoder_un18_bar3_32_hit_nc_0_and_0_a2_0_a2_0_a2_0_a2 ( + .I0(com_cmm_bar4_reg[2]), + .I1(com_cmm_bar4_reg[3]), + .I2(com_cmm_u_cmm_decoder_un18_bar3_32_hit_nc_0_and_1), + .O(com_cmm_u_cmm_decoder_un18_bar3_32_hit_nc_0_and) + ); + defparam com_cmm_u_cmm_decoder_un18_bar4_32_hit_nc_7_and_0_a2.INIT = 16'h0001; + LUT4 com_cmm_u_cmm_decoder_un18_bar4_32_hit_nc_7_and_0_a2 ( + .I0(com_cmm_bar5_reg[28]), + .I1(com_cmm_bar5_reg[29]), + .I2(com_cmm_bar5_reg[30]), + .I3(com_cmm_bar5_reg[31]), + .O(com_cmm_u_cmm_decoder_un18_bar4_32_hit_nc_7_and) + ); + defparam com_cmm_u_cmm_decoder_un18_bar4_32_hit_nc_6_and_0_a2_0_a2.INIT = 16'h0001; + LUT4 com_cmm_u_cmm_decoder_un18_bar4_32_hit_nc_6_and_0_a2_0_a2 ( + .I0(com_cmm_bar5_reg[24]), + .I1(com_cmm_bar5_reg[25]), + .I2(com_cmm_bar5_reg[26]), + .I3(com_cmm_bar5_reg[27]), + .O(com_cmm_u_cmm_decoder_un18_bar4_32_hit_nc_6_and) + ); + defparam com_cmm_u_cmm_decoder_un18_bar4_32_hit_nc_5_and_0_a2_0_a2.INIT = 16'h0001; + LUT4 com_cmm_u_cmm_decoder_un18_bar4_32_hit_nc_5_and_0_a2_0_a2 ( + .I0(com_cmm_bar5_reg[20]), + .I1(com_cmm_bar5_reg[21]), + .I2(com_cmm_bar5_reg[22]), + .I3(com_cmm_bar5_reg[23]), + .O(com_cmm_u_cmm_decoder_un18_bar4_32_hit_nc_5_and) + ); + defparam com_cmm_u_cmm_decoder_un18_bar4_32_hit_nc_4_and_0_a2_0_a2.INIT = 16'h0001; + LUT4 com_cmm_u_cmm_decoder_un18_bar4_32_hit_nc_4_and_0_a2_0_a2 ( + .I0(com_cmm_bar5_reg[16]), + .I1(com_cmm_bar5_reg[17]), + .I2(com_cmm_bar5_reg[18]), + .I3(com_cmm_bar5_reg[19]), + .O(com_cmm_u_cmm_decoder_un18_bar4_32_hit_nc_4_and) + ); + defparam com_cmm_u_cmm_decoder_un18_bar4_32_hit_nc_3_and_0_a2_0_a2.INIT = 16'h0001; + LUT4 com_cmm_u_cmm_decoder_un18_bar4_32_hit_nc_3_and_0_a2_0_a2 ( + .I0(com_cmm_bar5_reg[12]), + .I1(com_cmm_bar5_reg[13]), + .I2(com_cmm_bar5_reg[14]), + .I3(com_cmm_bar5_reg[15]), + .O(com_cmm_u_cmm_decoder_un18_bar4_32_hit_nc_3_and) + ); + defparam com_cmm_u_cmm_decoder_un18_bar4_32_hit_nc_2_and_0_a2_0_a2.INIT = 16'h0001; + LUT4 com_cmm_u_cmm_decoder_un18_bar4_32_hit_nc_2_and_0_a2_0_a2 ( + .I0(com_cmm_bar5_reg[8]), + .I1(com_cmm_bar5_reg[9]), + .I2(com_cmm_bar5_reg[10]), + .I3(com_cmm_bar5_reg[11]), + .O(com_cmm_u_cmm_decoder_un18_bar4_32_hit_nc_2_and) + ); + defparam com_cmm_u_cmm_decoder_un18_bar4_32_hit_nc_1_and_0_a2_0_a2.INIT = 16'h0001; + LUT4 com_cmm_u_cmm_decoder_un18_bar4_32_hit_nc_1_and_0_a2_0_a2 ( + .I0(com_cmm_bar5_reg[4]), + .I1(com_cmm_bar5_reg[5]), + .I2(com_cmm_bar5_reg[6]), + .I3(com_cmm_bar5_reg[7]), + .O(com_cmm_u_cmm_decoder_un18_bar4_32_hit_nc_1_and) + ); + defparam com_cmm_u_cmm_decoder_un18_bar4_32_hit_nc_0_and_0_a2_0_a2_0_a2_0_a2.INIT = 16'h0001; + LUT4 com_cmm_u_cmm_decoder_un18_bar4_32_hit_nc_0_and_0_a2_0_a2_0_a2_0_a2 ( + .I0(com_cmm_bar5_reg[0]), + .I1(com_cmm_bar5_reg[1]), + .I2(com_cmm_bar5_reg[2]), + .I3(com_cmm_bar5_reg[3]), + .O(com_cmm_u_cmm_decoder_un18_bar4_32_hit_nc_0_and) + ); + defparam com_cmm_u_cmm_decoder_un11_bar1_32_hit_nc_7_and_0_a2_0_a2_0_a2.INIT = 16'h0001; + LUT4 com_cmm_u_cmm_decoder_un11_bar1_32_hit_nc_7_and_0_a2_0_a2_0_a2 ( + .I0(cfg_cfg_6102[124]), + .I1(cfg_cfg_6102[125]), + .I2(cfg_cfg_6102[126]), + .I3(cfg_cfg_6102[127]), + .O(com_cmm_u_cmm_decoder_un11_bar1_32_hit_nc_7_and) + ); + defparam com_cmm_u_cmm_decoder_un11_bar1_32_hit_nc_6_and_0_a2_0_a2_0_a2.INIT = 16'h0001; + LUT4 com_cmm_u_cmm_decoder_un11_bar1_32_hit_nc_6_and_0_a2_0_a2_0_a2 ( + .I0(cfg_cfg_6102[120]), + .I1(cfg_cfg_6102[121]), + .I2(cfg_cfg_6102[122]), + .I3(cfg_cfg_6102[123]), + .O(com_cmm_u_cmm_decoder_un11_bar1_32_hit_nc_6_and) + ); + defparam com_cmm_u_cmm_decoder_un11_bar1_32_hit_nc_5_and_0_a2_0_a2.INIT = 16'h0001; + LUT4 com_cmm_u_cmm_decoder_un11_bar1_32_hit_nc_5_and_0_a2_0_a2 ( + .I0(cfg_cfg_6102[116]), + .I1(cfg_cfg_6102[117]), + .I2(cfg_cfg_6102[118]), + .I3(cfg_cfg_6102[119]), + .O(com_cmm_u_cmm_decoder_un11_bar1_32_hit_nc_5_and) + ); + defparam com_cmm_u_cmm_decoder_un11_bar1_32_hit_nc_4_and_0_a2_0_a2_0_a2_0_a2.INIT = 16'h0001; + LUT4 com_cmm_u_cmm_decoder_un11_bar1_32_hit_nc_4_and_0_a2_0_a2_0_a2_0_a2 ( + .I0(cfg_cfg_6102[112]), + .I1(cfg_cfg_6102[113]), + .I2(cfg_cfg_6102[114]), + .I3(cfg_cfg_6102[115]), + .O(com_cmm_u_cmm_decoder_un11_bar1_32_hit_nc_4_and) + ); + defparam com_cmm_u_cmm_decoder_un11_bar1_32_hit_nc_3_and_0_a2_0_a2_0_a2.INIT = 16'h0001; + LUT4 com_cmm_u_cmm_decoder_un11_bar1_32_hit_nc_3_and_0_a2_0_a2_0_a2 ( + .I0(cfg_cfg_6102[108]), + .I1(cfg_cfg_6102[109]), + .I2(cfg_cfg_6102[110]), + .I3(cfg_cfg_6102[111]), + .O(com_cmm_u_cmm_decoder_un11_bar1_32_hit_nc_3_and) + ); + defparam com_cmm_u_cmm_decoder_un11_bar1_32_hit_nc_2_and_0_a2_0_a2_0_a2.INIT = 16'h0001; + LUT4 com_cmm_u_cmm_decoder_un11_bar1_32_hit_nc_2_and_0_a2_0_a2_0_a2 ( + .I0(cfg_cfg_6102[104]), + .I1(cfg_cfg_6102[105]), + .I2(cfg_cfg_6102[106]), + .I3(cfg_cfg_6102[107]), + .O(com_cmm_u_cmm_decoder_un11_bar1_32_hit_nc_2_and) + ); + defparam com_cmm_u_cmm_decoder_un11_bar1_32_hit_nc_1_and_0_a2_0_a2_0_a2_0_a2.INIT = 16'h0001; + LUT4 com_cmm_u_cmm_decoder_un11_bar1_32_hit_nc_1_and_0_a2_0_a2_0_a2_0_a2 ( + .I0(cfg_cfg_6102[100]), + .I1(cfg_cfg_6102[101]), + .I2(cfg_cfg_6102[102]), + .I3(cfg_cfg_6102[103]), + .O(com_cmm_u_cmm_decoder_un11_bar1_32_hit_nc_1_and) + ); + defparam com_cmm_u_cmm_decoder_un11_bar1_32_hit_nc_0_and_0_a2_0_a2_0_a2_0_a2.INIT = 16'h0001; + LUT4 com_cmm_u_cmm_decoder_un11_bar1_32_hit_nc_0_and_0_a2_0_a2_0_a2_0_a2 ( + .I0(cfg_cfg_6102[96]), + .I1(cfg_cfg_6102[97]), + .I2(cfg_cfg_6102[98]), + .I3(cfg_cfg_6102[99]), + .O(com_cmm_u_cmm_decoder_un11_bar1_32_hit_nc_0_and) + ); + defparam com_cmm_u_cmm_decoder_un11_bar2_32_hit_nc_7_and_0_a2_0_a2_0_a2.INIT = 16'h0001; + LUT4 com_cmm_u_cmm_decoder_un11_bar2_32_hit_nc_7_and_0_a2_0_a2_0_a2 ( + .I0(cfg_cfg_6102[156]), + .I1(cfg_cfg_6102[157]), + .I2(cfg_cfg_6102[158]), + .I3(cfg_cfg_6102[159]), + .O(com_cmm_u_cmm_decoder_un11_bar2_32_hit_nc_7_and) + ); + defparam com_cmm_u_cmm_decoder_un11_bar2_32_hit_nc_6_and_0_a2_0_a2_0_a2.INIT = 16'h0001; + LUT4 com_cmm_u_cmm_decoder_un11_bar2_32_hit_nc_6_and_0_a2_0_a2_0_a2 ( + .I0(cfg_cfg_6102[152]), + .I1(cfg_cfg_6102[153]), + .I2(cfg_cfg_6102[154]), + .I3(cfg_cfg_6102[155]), + .O(com_cmm_u_cmm_decoder_un11_bar2_32_hit_nc_6_and) + ); + defparam com_cmm_u_cmm_decoder_un11_bar2_32_hit_nc_5_and_0_a2_0_a2.INIT = 16'h0001; + LUT4 com_cmm_u_cmm_decoder_un11_bar2_32_hit_nc_5_and_0_a2_0_a2 ( + .I0(cfg_cfg_6102[148]), + .I1(cfg_cfg_6102[149]), + .I2(cfg_cfg_6102[150]), + .I3(cfg_cfg_6102[151]), + .O(com_cmm_u_cmm_decoder_un11_bar2_32_hit_nc_5_and) + ); + defparam com_cmm_u_cmm_decoder_un11_bar2_32_hit_nc_4_and_0_a2_0_a2_0_a2_0_a2.INIT = 16'h0001; + LUT4 com_cmm_u_cmm_decoder_un11_bar2_32_hit_nc_4_and_0_a2_0_a2_0_a2_0_a2 ( + .I0(cfg_cfg_6102[144]), + .I1(cfg_cfg_6102[145]), + .I2(cfg_cfg_6102[146]), + .I3(cfg_cfg_6102[147]), + .O(com_cmm_u_cmm_decoder_un11_bar2_32_hit_nc_4_and) + ); + defparam com_cmm_u_cmm_decoder_un11_bar2_32_hit_nc_3_and_0_a2_0_a2_0_a2.INIT = 16'h0001; + LUT4 com_cmm_u_cmm_decoder_un11_bar2_32_hit_nc_3_and_0_a2_0_a2_0_a2 ( + .I0(cfg_cfg_6102[140]), + .I1(cfg_cfg_6102[141]), + .I2(cfg_cfg_6102[142]), + .I3(cfg_cfg_6102[143]), + .O(com_cmm_u_cmm_decoder_un11_bar2_32_hit_nc_3_and) + ); + defparam com_cmm_u_cmm_decoder_un11_bar2_32_hit_nc_2_and_0_a2_0_a2_0_a2.INIT = 16'h0001; + LUT4 com_cmm_u_cmm_decoder_un11_bar2_32_hit_nc_2_and_0_a2_0_a2_0_a2 ( + .I0(cfg_cfg_6102[136]), + .I1(cfg_cfg_6102[137]), + .I2(cfg_cfg_6102[138]), + .I3(cfg_cfg_6102[139]), + .O(com_cmm_u_cmm_decoder_un11_bar2_32_hit_nc_2_and) + ); + defparam com_cmm_u_cmm_decoder_un11_bar2_32_hit_nc_1_and_0_a2_0_a2_0_a2_0_a2.INIT = 16'h0001; + LUT4 com_cmm_u_cmm_decoder_un11_bar2_32_hit_nc_1_and_0_a2_0_a2_0_a2_0_a2 ( + .I0(cfg_cfg_6102[132]), + .I1(cfg_cfg_6102[133]), + .I2(cfg_cfg_6102[134]), + .I3(cfg_cfg_6102[135]), + .O(com_cmm_u_cmm_decoder_un11_bar2_32_hit_nc_1_and) + ); + defparam com_cmm_u_cmm_decoder_un11_bar2_32_hit_nc_0_and_0_a2_0_a2_0_a2_0_a2.INIT = 8'h02; + LUT3 com_cmm_u_cmm_decoder_un11_bar2_32_hit_nc_0_and_0_a2_0_a2_0_a2_0_a2 ( + .I0(com_cmm_N_56056_i), + .I1(cfg_cfg_6102[130]), + .I2(cfg_cfg_6102[131]), + .O(com_cmm_u_cmm_decoder_un11_bar2_32_hit_nc_0_and) + ); + defparam com_cmm_u_cmm_decoder_un11_bar3_32_hit_nc_7_and_0_a2_0_a2_0_a2.INIT = 16'h0001; + LUT4 com_cmm_u_cmm_decoder_un11_bar3_32_hit_nc_7_and_0_a2_0_a2_0_a2 ( + .I0(cfg_cfg_6102[188]), + .I1(cfg_cfg_6102[189]), + .I2(cfg_cfg_6102[190]), + .I3(cfg_cfg_6102[191]), + .O(com_cmm_u_cmm_decoder_un11_bar3_32_hit_nc_7_and) + ); + defparam com_cmm_u_cmm_decoder_un11_bar3_32_hit_nc_6_and_0_a2_0_a2_0_a2.INIT = 16'h0001; + LUT4 com_cmm_u_cmm_decoder_un11_bar3_32_hit_nc_6_and_0_a2_0_a2_0_a2 ( + .I0(cfg_cfg_6102[184]), + .I1(cfg_cfg_6102[185]), + .I2(cfg_cfg_6102[186]), + .I3(cfg_cfg_6102[187]), + .O(com_cmm_u_cmm_decoder_un11_bar3_32_hit_nc_6_and) + ); + defparam com_cmm_u_cmm_decoder_un11_bar3_32_hit_nc_5_and_0_a2_0_a2.INIT = 16'h0001; + LUT4 com_cmm_u_cmm_decoder_un11_bar3_32_hit_nc_5_and_0_a2_0_a2 ( + .I0(cfg_cfg_6102[180]), + .I1(cfg_cfg_6102[181]), + .I2(cfg_cfg_6102[182]), + .I3(cfg_cfg_6102[183]), + .O(com_cmm_u_cmm_decoder_un11_bar3_32_hit_nc_5_and) + ); + defparam com_cmm_u_cmm_decoder_un11_bar3_32_hit_nc_4_and_0_a2_0_a2_0_a2_0_a2.INIT = 16'h0001; + LUT4 com_cmm_u_cmm_decoder_un11_bar3_32_hit_nc_4_and_0_a2_0_a2_0_a2_0_a2 ( + .I0(cfg_cfg_6102[176]), + .I1(cfg_cfg_6102[177]), + .I2(cfg_cfg_6102[178]), + .I3(cfg_cfg_6102[179]), + .O(com_cmm_u_cmm_decoder_un11_bar3_32_hit_nc_4_and) + ); + defparam com_cmm_u_cmm_decoder_un11_bar3_32_hit_nc_3_and_0_a2_0_a2_0_a2.INIT = 16'h0001; + LUT4 com_cmm_u_cmm_decoder_un11_bar3_32_hit_nc_3_and_0_a2_0_a2_0_a2 ( + .I0(cfg_cfg_6102[172]), + .I1(cfg_cfg_6102[173]), + .I2(cfg_cfg_6102[174]), + .I3(cfg_cfg_6102[175]), + .O(com_cmm_u_cmm_decoder_un11_bar3_32_hit_nc_3_and) + ); + defparam com_cmm_u_cmm_decoder_un11_bar3_32_hit_nc_2_and_0_a2_0_a2_0_a2.INIT = 16'h0001; + LUT4 com_cmm_u_cmm_decoder_un11_bar3_32_hit_nc_2_and_0_a2_0_a2_0_a2 ( + .I0(cfg_cfg_6102[168]), + .I1(cfg_cfg_6102[169]), + .I2(cfg_cfg_6102[170]), + .I3(cfg_cfg_6102[171]), + .O(com_cmm_u_cmm_decoder_un11_bar3_32_hit_nc_2_and) + ); + defparam com_cmm_u_cmm_decoder_un11_bar3_32_hit_nc_1_and_0_a2_0_a2_0_a2_0_a2.INIT = 16'h0001; + LUT4 com_cmm_u_cmm_decoder_un11_bar3_32_hit_nc_1_and_0_a2_0_a2_0_a2_0_a2 ( + .I0(cfg_cfg_6102[164]), + .I1(cfg_cfg_6102[165]), + .I2(cfg_cfg_6102[166]), + .I3(cfg_cfg_6102[167]), + .O(com_cmm_u_cmm_decoder_un11_bar3_32_hit_nc_1_and) + ); + defparam com_cmm_u_cmm_decoder_un11_bar3_32_hit_nc_0_and_0_a2_0_a2_0_a2_0_a2.INIT = 8'h02; + LUT3 com_cmm_u_cmm_decoder_un11_bar3_32_hit_nc_0_and_0_a2_0_a2_0_a2_0_a2 ( + .I0(com_cmm_N_56057_i), + .I1(cfg_cfg_6102[162]), + .I2(cfg_cfg_6102[163]), + .O(com_cmm_u_cmm_decoder_un11_bar3_32_hit_nc_0_and) + ); + defparam com_cmm_u_cmm_decoder_un11_bar4_32_hit_nc_7_sf.INIT = 4'h2; + LUT1 com_cmm_u_cmm_decoder_un11_bar4_32_hit_nc_7_sf ( + .I0(com_cmm_u_cmm_decoder_un11_bar4_32_hit_nc_7_and), + .O(com_cmm_u_cmm_decoder_un11_bar4_32_hit_nc_7_sf_5546) + ); + defparam com_cmm_u_cmm_decoder_un11_bar4_32_hit_nc_6_sf.INIT = 4'h2; + LUT1 com_cmm_u_cmm_decoder_un11_bar4_32_hit_nc_6_sf ( + .I0(com_cmm_u_cmm_decoder_un11_bar4_32_hit_nc_6_and), + .O(com_cmm_u_cmm_decoder_un11_bar4_32_hit_nc_6_sf_5547) + ); + defparam com_cmm_u_cmm_decoder_un11_bar4_32_hit_nc_5_sf.INIT = 4'h2; + LUT1 com_cmm_u_cmm_decoder_un11_bar4_32_hit_nc_5_sf ( + .I0(com_cmm_u_cmm_decoder_un11_bar4_32_hit_nc_5_and), + .O(com_cmm_u_cmm_decoder_un11_bar4_32_hit_nc_5_sf_5548) + ); + defparam com_cmm_u_cmm_decoder_un11_bar4_32_hit_nc_4_sf.INIT = 4'h2; + LUT1 com_cmm_u_cmm_decoder_un11_bar4_32_hit_nc_4_sf ( + .I0(com_cmm_u_cmm_decoder_un11_bar4_32_hit_nc_4_and), + .O(com_cmm_u_cmm_decoder_un11_bar4_32_hit_nc_4_sf_5549) + ); + defparam com_cmm_u_cmm_decoder_un11_bar4_32_hit_nc_3_sf.INIT = 4'h2; + LUT1 com_cmm_u_cmm_decoder_un11_bar4_32_hit_nc_3_sf ( + .I0(com_cmm_u_cmm_decoder_un11_bar4_32_hit_nc_3_and), + .O(com_cmm_u_cmm_decoder_un11_bar4_32_hit_nc_3_sf_5550) + ); + defparam com_cmm_u_cmm_decoder_un11_bar4_32_hit_nc_2_sf.INIT = 4'h2; + LUT1 com_cmm_u_cmm_decoder_un11_bar4_32_hit_nc_2_sf ( + .I0(com_cmm_u_cmm_decoder_un11_bar4_32_hit_nc_2_and), + .O(com_cmm_u_cmm_decoder_un11_bar4_32_hit_nc_2_sf_5551) + ); + defparam com_cmm_u_cmm_decoder_un11_bar4_32_hit_nc_1_sf.INIT = 4'h2; + LUT1 com_cmm_u_cmm_decoder_un11_bar4_32_hit_nc_1_sf ( + .I0(com_cmm_u_cmm_decoder_un11_bar4_32_hit_nc_1_and), + .O(com_cmm_u_cmm_decoder_un11_bar4_32_hit_nc_1_sf_5552) + ); + defparam com_cmm_u_cmm_decoder_un11_bar4_32_hit_nc_0_sf.INIT = 8'h02; + LUT3 com_cmm_u_cmm_decoder_un11_bar4_32_hit_nc_0_sf ( + .I0(com_cmm_N_56058_i), + .I1(cfg_cfg_6102[194]), + .I2(cfg_cfg_6102[195]), + .O(com_cmm_u_cmm_decoder_un11_bar4_32_hit_nc_0_sf_5553) + ); + defparam com_cmm_u_cmm_decoder_un11_bar5_32_hit_nc_7_and_0_a2_0_a2_0_a2.INIT = 16'h0001; + LUT4 com_cmm_u_cmm_decoder_un11_bar5_32_hit_nc_7_and_0_a2_0_a2_0_a2 ( + .I0(cfg_cfg_6102[252]), + .I1(cfg_cfg_6102[253]), + .I2(cfg_cfg_6102[254]), + .I3(cfg_cfg_6102[255]), + .O(com_cmm_u_cmm_decoder_un11_bar5_32_hit_nc_7_and) + ); + defparam com_cmm_u_cmm_decoder_un11_bar5_32_hit_nc_6_and_0_a2_0_a2_0_a2.INIT = 16'h0001; + LUT4 com_cmm_u_cmm_decoder_un11_bar5_32_hit_nc_6_and_0_a2_0_a2_0_a2 ( + .I0(cfg_cfg_6102[248]), + .I1(cfg_cfg_6102[249]), + .I2(cfg_cfg_6102[250]), + .I3(cfg_cfg_6102[251]), + .O(com_cmm_u_cmm_decoder_un11_bar5_32_hit_nc_6_and) + ); + defparam com_cmm_u_cmm_decoder_un11_bar5_32_hit_nc_5_and_0_a2_0_a2_0_a2.INIT = 16'h0001; + LUT4 com_cmm_u_cmm_decoder_un11_bar5_32_hit_nc_5_and_0_a2_0_a2_0_a2 ( + .I0(cfg_cfg_6102[244]), + .I1(cfg_cfg_6102[245]), + .I2(cfg_cfg_6102[246]), + .I3(cfg_cfg_6102[247]), + .O(com_cmm_u_cmm_decoder_un11_bar5_32_hit_nc_5_and) + ); + defparam com_cmm_u_cmm_decoder_un11_bar5_32_hit_nc_4_and_0_a2_0_a2_0_a2_0_a2.INIT = 16'h0001; + LUT4 com_cmm_u_cmm_decoder_un11_bar5_32_hit_nc_4_and_0_a2_0_a2_0_a2_0_a2 ( + .I0(cfg_cfg_6102[240]), + .I1(cfg_cfg_6102[241]), + .I2(cfg_cfg_6102[242]), + .I3(cfg_cfg_6102[243]), + .O(com_cmm_u_cmm_decoder_un11_bar5_32_hit_nc_4_and) + ); + defparam com_cmm_u_cmm_decoder_un11_bar5_32_hit_nc_3_and_0_a2_0_a2_0_a2.INIT = 16'h0001; + LUT4 com_cmm_u_cmm_decoder_un11_bar5_32_hit_nc_3_and_0_a2_0_a2_0_a2 ( + .I0(cfg_cfg_6102[236]), + .I1(cfg_cfg_6102[237]), + .I2(cfg_cfg_6102[238]), + .I3(cfg_cfg_6102[239]), + .O(com_cmm_u_cmm_decoder_un11_bar5_32_hit_nc_3_and) + ); + defparam com_cmm_u_cmm_decoder_un11_bar5_32_hit_nc_2_and_0_a2_0_a2_0_a2.INIT = 16'h0001; + LUT4 com_cmm_u_cmm_decoder_un11_bar5_32_hit_nc_2_and_0_a2_0_a2_0_a2 ( + .I0(cfg_cfg_6102[232]), + .I1(cfg_cfg_6102[233]), + .I2(cfg_cfg_6102[234]), + .I3(cfg_cfg_6102[235]), + .O(com_cmm_u_cmm_decoder_un11_bar5_32_hit_nc_2_and) + ); + defparam com_cmm_u_cmm_decoder_un11_bar5_32_hit_nc_1_and_0_a2_0_a2_0_a2_0_a2.INIT = 16'h0001; + LUT4 com_cmm_u_cmm_decoder_un11_bar5_32_hit_nc_1_and_0_a2_0_a2_0_a2_0_a2 ( + .I0(cfg_cfg_6102[228]), + .I1(cfg_cfg_6102[229]), + .I2(cfg_cfg_6102[230]), + .I3(cfg_cfg_6102[231]), + .O(com_cmm_u_cmm_decoder_un11_bar5_32_hit_nc_1_and) + ); + defparam com_cmm_u_cmm_decoder_un11_bar5_32_hit_nc_0_and_0_a2_0_a2_0_a2_0_a2.INIT = 16'h0001; + LUT4 com_cmm_u_cmm_decoder_un11_bar5_32_hit_nc_0_and_0_a2_0_a2_0_a2_0_a2 ( + .I0(cfg_cfg_6102[224]), + .I1(cfg_cfg_6102[225]), + .I2(cfg_cfg_6102[226]), + .I3(cfg_cfg_6102[227]), + .O(com_cmm_u_cmm_decoder_un11_bar5_32_hit_nc_0_and) + ); + defparam com_cmm_u_cmm_decoder_un11_bar34_64_hit_low_0_and_0_a2_0_a2_0_a2_0_a2.INIT = 8'h02; + LUT3 com_cmm_u_cmm_decoder_un11_bar34_64_hit_low_0_and_0_a2_0_a2_0_a2_0_a2 ( + .I0(com_cmm_N_56058_i), + .I1(cfg_cfg_6102[194]), + .I2(cfg_cfg_6102[195]), + .O(com_cmm_u_cmm_decoder_un11_bar4_32_hit_nc_0_and) + ); + defparam com_cmm_u_cmm_decoder_bar4_eq_raddr_3_0_I_126.INIT = 4'h1; + LUT2 com_cmm_u_cmm_decoder_bar4_eq_raddr_3_0_I_126 ( + .I0(com_cmm_u_cmm_decoder_N_6), + .I1(com_cmm_u_cmm_decoder_N_7), + .O(com_cmm_u_cmm_decoder_N_3_13) + ); + defparam com_cmm_u_cmm_decoder_bar4_eq_raddr_3_0_I_117.INIT = 4'h1; + LUT2 com_cmm_u_cmm_decoder_bar4_eq_raddr_3_0_I_117 ( + .I0(com_cmm_u_cmm_decoder_N_14_0), + .I1(com_cmm_u_cmm_decoder_N_15), + .O(com_cmm_u_cmm_decoder_N_11_14) + ); + defparam com_cmm_u_cmm_decoder_bar4_eq_raddr_3_0_I_108.INIT = 4'h1; + LUT2 com_cmm_u_cmm_decoder_bar4_eq_raddr_3_0_I_108 ( + .I0(com_cmm_u_cmm_decoder_N_22), + .I1(com_cmm_u_cmm_decoder_N_23), + .O(com_cmm_u_cmm_decoder_N_19_13) + ); + defparam com_cmm_u_cmm_decoder_bar4_eq_raddr_3_0_I_99.INIT = 4'h1; + LUT2 com_cmm_u_cmm_decoder_bar4_eq_raddr_3_0_I_99 ( + .I0(com_cmm_u_cmm_decoder_N_30), + .I1(com_cmm_u_cmm_decoder_N_31), + .O(com_cmm_u_cmm_decoder_N_27_13) + ); + defparam com_cmm_u_cmm_decoder_bar4_eq_raddr_3_0_I_90.INIT = 4'h1; + LUT2 com_cmm_u_cmm_decoder_bar4_eq_raddr_3_0_I_90 ( + .I0(com_cmm_u_cmm_decoder_N_38), + .I1(com_cmm_u_cmm_decoder_N_39), + .O(com_cmm_u_cmm_decoder_N_35_13) + ); + defparam com_cmm_u_cmm_decoder_bar4_eq_raddr_3_0_I_81.INIT = 4'h1; + LUT2 com_cmm_u_cmm_decoder_bar4_eq_raddr_3_0_I_81 ( + .I0(com_cmm_u_cmm_decoder_N_46), + .I1(com_cmm_u_cmm_decoder_N_47), + .O(com_cmm_u_cmm_decoder_N_43_13) + ); + defparam com_cmm_u_cmm_decoder_bar4_eq_raddr_3_0_I_72.INIT = 16'h0903; + LUT4 com_cmm_u_cmm_decoder_bar4_eq_raddr_3_0_I_72 ( + .I0(cfg_cfg_6102[210]), + .I1(com_cmm_bar4_reg[18]), + .I2(com_cmm_u_cmm_decoder_N_54), + .I3(com_cmmt_raddr[50]), + .O(com_cmm_u_cmm_decoder_N_51_13) + ); + defparam com_cmm_u_cmm_decoder_bar4_eq_raddr_3_0_I_63.INIT = 4'h1; + LUT2 com_cmm_u_cmm_decoder_bar4_eq_raddr_3_0_I_63 ( + .I0(com_cmm_u_cmm_decoder_N_62), + .I1(com_cmm_u_cmm_decoder_N_63), + .O(com_cmm_u_cmm_decoder_N_59_13) + ); + defparam com_cmm_u_cmm_decoder_bar4_eq_raddr_3_0_I_54.INIT = 16'h0903; + LUT4 com_cmm_u_cmm_decoder_bar4_eq_raddr_3_0_I_54 ( + .I0(cfg_cfg_6102[216]), + .I1(com_cmm_bar4_reg[24]), + .I2(com_cmm_u_cmm_decoder_N_70), + .I3(com_cmmt_raddr[56]), + .O(com_cmm_u_cmm_decoder_N_67_13) + ); + defparam com_cmm_u_cmm_decoder_bar4_eq_raddr_3_0_I_45.INIT = 16'h0903; + LUT4 com_cmm_u_cmm_decoder_bar4_eq_raddr_3_0_I_45 ( + .I0(cfg_cfg_6102[205]), + .I1(com_cmm_bar4_reg[13]), + .I2(com_cmm_u_cmm_decoder_N_79), + .I3(com_cmmt_raddr[45]), + .O(com_cmm_u_cmm_decoder_N_75_13) + ); + defparam com_cmm_u_cmm_decoder_bar4_eq_raddr_3_0_I_36.INIT = 16'h0903; + LUT4 com_cmm_u_cmm_decoder_bar4_eq_raddr_3_0_I_36 ( + .I0(cfg_cfg_6102[203]), + .I1(com_cmm_bar4_reg[11]), + .I2(com_cmm_u_cmm_decoder_N_87), + .I3(com_cmmt_raddr[43]), + .O(com_cmm_u_cmm_decoder_N_83_13) + ); + defparam com_cmm_u_cmm_decoder_bar4_eq_raddr_3_0_I_27.INIT = 16'h0903; + LUT4 com_cmm_u_cmm_decoder_bar4_eq_raddr_3_0_I_27 ( + .I0(cfg_cfg_6102[214]), + .I1(com_cmm_bar4_reg[22]), + .I2(com_cmm_u_cmm_decoder_N_94), + .I3(com_cmmt_raddr[54]), + .O(com_cmm_u_cmm_decoder_N_91_13) + ); + defparam com_cmm_u_cmm_decoder_bar4_eq_raddr_3_0_I_9.INIT = 4'h1; + LUT2 com_cmm_u_cmm_decoder_bar4_eq_raddr_3_0_I_9 ( + .I0(com_cmm_u_cmm_decoder_N_110), + .I1(com_cmm_u_cmm_decoder_N_111), + .O(com_cmm_u_cmm_decoder_N_107_12) + ); + defparam com_cmm_u_cmm_decoder_bar3_eq_raddr_3_0_I_126.INIT = 4'h1; + LUT2 com_cmm_u_cmm_decoder_bar3_eq_raddr_3_0_I_126 ( + .I0(com_cmm_u_cmm_decoder_N_6_0), + .I1(com_cmm_u_cmm_decoder_N_7_0), + .O(com_cmm_u_cmm_decoder_N_3_12) + ); + defparam com_cmm_u_cmm_decoder_bar3_eq_raddr_3_0_I_117.INIT = 4'h1; + LUT2 com_cmm_u_cmm_decoder_bar3_eq_raddr_3_0_I_117 ( + .I0(com_cmm_u_cmm_decoder_N_14_1), + .I1(com_cmm_u_cmm_decoder_N_15_0), + .O(com_cmm_u_cmm_decoder_N_11_13) + ); + defparam com_cmm_u_cmm_decoder_bar3_eq_raddr_3_0_I_108.INIT = 4'h1; + LUT2 com_cmm_u_cmm_decoder_bar3_eq_raddr_3_0_I_108 ( + .I0(com_cmm_u_cmm_decoder_N_22_0), + .I1(com_cmm_u_cmm_decoder_N_23_0), + .O(com_cmm_u_cmm_decoder_N_19_12) + ); + defparam com_cmm_u_cmm_decoder_bar3_eq_raddr_3_0_I_99.INIT = 4'h1; + LUT2 com_cmm_u_cmm_decoder_bar3_eq_raddr_3_0_I_99 ( + .I0(com_cmm_u_cmm_decoder_N_30_0), + .I1(com_cmm_u_cmm_decoder_N_31_0), + .O(com_cmm_u_cmm_decoder_N_27_12) + ); + defparam com_cmm_u_cmm_decoder_bar3_eq_raddr_3_0_I_90.INIT = 4'h1; + LUT2 com_cmm_u_cmm_decoder_bar3_eq_raddr_3_0_I_90 ( + .I0(com_cmm_u_cmm_decoder_N_38_0), + .I1(com_cmm_u_cmm_decoder_N_39_0), + .O(com_cmm_u_cmm_decoder_N_35_12) + ); + defparam com_cmm_u_cmm_decoder_bar3_eq_raddr_3_0_I_81.INIT = 4'h1; + LUT2 com_cmm_u_cmm_decoder_bar3_eq_raddr_3_0_I_81 ( + .I0(com_cmm_u_cmm_decoder_N_46_0), + .I1(com_cmm_u_cmm_decoder_N_47_0), + .O(com_cmm_u_cmm_decoder_N_43_12) + ); + defparam com_cmm_u_cmm_decoder_bar3_eq_raddr_3_0_I_72.INIT = 16'h0903; + LUT4 com_cmm_u_cmm_decoder_bar3_eq_raddr_3_0_I_72 ( + .I0(cfg_cfg_6102[178]), + .I1(com_cmm_bar3_reg[18]), + .I2(com_cmm_u_cmm_decoder_N_54_0), + .I3(com_cmmt_raddr[50]), + .O(com_cmm_u_cmm_decoder_N_51_12) + ); + defparam com_cmm_u_cmm_decoder_bar3_eq_raddr_3_0_I_63.INIT = 4'h1; + LUT2 com_cmm_u_cmm_decoder_bar3_eq_raddr_3_0_I_63 ( + .I0(com_cmm_u_cmm_decoder_N_62_0), + .I1(com_cmm_u_cmm_decoder_N_63_0), + .O(com_cmm_u_cmm_decoder_N_59_12) + ); + defparam com_cmm_u_cmm_decoder_bar3_eq_raddr_3_0_I_54.INIT = 16'h0903; + LUT4 com_cmm_u_cmm_decoder_bar3_eq_raddr_3_0_I_54 ( + .I0(cfg_cfg_6102[184]), + .I1(com_cmm_bar3_reg[24]), + .I2(com_cmm_u_cmm_decoder_N_70_0), + .I3(com_cmmt_raddr[56]), + .O(com_cmm_u_cmm_decoder_N_67_12) + ); + defparam com_cmm_u_cmm_decoder_bar3_eq_raddr_3_0_I_45.INIT = 16'h0903; + LUT4 com_cmm_u_cmm_decoder_bar3_eq_raddr_3_0_I_45 ( + .I0(cfg_cfg_6102[172]), + .I1(com_cmm_bar3_reg[12]), + .I2(com_cmm_u_cmm_decoder_N_78), + .I3(com_cmmt_raddr[44]), + .O(com_cmm_u_cmm_decoder_N_75_12) + ); + defparam com_cmm_u_cmm_decoder_bar3_eq_raddr_3_0_I_36.INIT = 16'h0903; + LUT4 com_cmm_u_cmm_decoder_bar3_eq_raddr_3_0_I_36 ( + .I0(cfg_cfg_6102[170]), + .I1(com_cmm_bar3_reg[10]), + .I2(com_cmm_u_cmm_decoder_N_86), + .I3(com_cmmt_raddr[42]), + .O(com_cmm_u_cmm_decoder_N_83_12) + ); + defparam com_cmm_u_cmm_decoder_bar3_eq_raddr_3_0_I_27.INIT = 16'h0903; + LUT4 com_cmm_u_cmm_decoder_bar3_eq_raddr_3_0_I_27 ( + .I0(cfg_cfg_6102[182]), + .I1(com_cmm_bar3_reg[22]), + .I2(com_cmm_u_cmm_decoder_N_94_0), + .I3(com_cmmt_raddr[54]), + .O(com_cmm_u_cmm_decoder_N_91_12) + ); + defparam com_cmm_u_cmm_decoder_bar3_eq_raddr_3_0_I_9.INIT = 16'h0903; + LUT4 com_cmm_u_cmm_decoder_bar3_eq_raddr_3_0_I_9 ( + .I0(cfg_cfg_6102[165]), + .I1(com_cmm_bar3_reg[5]), + .I2(com_cmm_u_cmm_decoder_N_111_0), + .I3(com_cmmt_raddr[37]), + .O(com_cmm_u_cmm_decoder_N_107_11) + ); + defparam com_cmm_u_cmm_decoder_bar2_eq_raddr_3_0_I_126.INIT = 4'h1; + LUT2 com_cmm_u_cmm_decoder_bar2_eq_raddr_3_0_I_126 ( + .I0(com_cmm_u_cmm_decoder_N_6_1), + .I1(com_cmm_u_cmm_decoder_N_7_1), + .O(com_cmm_u_cmm_decoder_N_3_11) + ); + defparam com_cmm_u_cmm_decoder_bar2_eq_raddr_3_0_I_117.INIT = 4'h1; + LUT2 com_cmm_u_cmm_decoder_bar2_eq_raddr_3_0_I_117 ( + .I0(com_cmm_u_cmm_decoder_N_14_2), + .I1(com_cmm_u_cmm_decoder_N_15_1), + .O(com_cmm_u_cmm_decoder_N_11_12) + ); + defparam com_cmm_u_cmm_decoder_bar2_eq_raddr_3_0_I_108.INIT = 4'h1; + LUT2 com_cmm_u_cmm_decoder_bar2_eq_raddr_3_0_I_108 ( + .I0(com_cmm_u_cmm_decoder_N_22_1), + .I1(com_cmm_u_cmm_decoder_N_23_1), + .O(com_cmm_u_cmm_decoder_N_19_11) + ); + defparam com_cmm_u_cmm_decoder_bar2_eq_raddr_3_0_I_99.INIT = 4'h1; + LUT2 com_cmm_u_cmm_decoder_bar2_eq_raddr_3_0_I_99 ( + .I0(com_cmm_u_cmm_decoder_N_30_1), + .I1(com_cmm_u_cmm_decoder_N_31_1), + .O(com_cmm_u_cmm_decoder_N_27_11) + ); + defparam com_cmm_u_cmm_decoder_bar2_eq_raddr_3_0_I_90.INIT = 4'h1; + LUT2 com_cmm_u_cmm_decoder_bar2_eq_raddr_3_0_I_90 ( + .I0(com_cmm_u_cmm_decoder_N_38_1), + .I1(com_cmm_u_cmm_decoder_N_39_1), + .O(com_cmm_u_cmm_decoder_N_35_11) + ); + defparam com_cmm_u_cmm_decoder_bar2_eq_raddr_3_0_I_81.INIT = 4'h1; + LUT2 com_cmm_u_cmm_decoder_bar2_eq_raddr_3_0_I_81 ( + .I0(com_cmm_u_cmm_decoder_N_46_1), + .I1(com_cmm_u_cmm_decoder_N_47_1), + .O(com_cmm_u_cmm_decoder_N_43_11) + ); + defparam com_cmm_u_cmm_decoder_bar2_eq_raddr_3_0_I_72.INIT = 16'h0903; + LUT4 com_cmm_u_cmm_decoder_bar2_eq_raddr_3_0_I_72 ( + .I0(cfg_cfg_6102[146]), + .I1(com_cmm_bar2_reg[18]), + .I2(com_cmm_u_cmm_decoder_N_54_1), + .I3(com_cmmt_raddr[50]), + .O(com_cmm_u_cmm_decoder_N_51_11) + ); + defparam com_cmm_u_cmm_decoder_bar2_eq_raddr_3_0_I_63.INIT = 4'h1; + LUT2 com_cmm_u_cmm_decoder_bar2_eq_raddr_3_0_I_63 ( + .I0(com_cmm_u_cmm_decoder_N_62_1), + .I1(com_cmm_u_cmm_decoder_N_63_1), + .O(com_cmm_u_cmm_decoder_N_59_11) + ); + defparam com_cmm_u_cmm_decoder_bar2_eq_raddr_3_0_I_54.INIT = 16'h0903; + LUT4 com_cmm_u_cmm_decoder_bar2_eq_raddr_3_0_I_54 ( + .I0(cfg_cfg_6102[152]), + .I1(com_cmm_bar2_reg[24]), + .I2(com_cmm_u_cmm_decoder_N_70_1), + .I3(com_cmmt_raddr[56]), + .O(com_cmm_u_cmm_decoder_N_67_11) + ); + defparam com_cmm_u_cmm_decoder_bar2_eq_raddr_3_0_I_45.INIT = 16'h0903; + LUT4 com_cmm_u_cmm_decoder_bar2_eq_raddr_3_0_I_45 ( + .I0(cfg_cfg_6102[140]), + .I1(com_cmm_bar2_reg[12]), + .I2(com_cmm_u_cmm_decoder_N_78_0), + .I3(com_cmmt_raddr[44]), + .O(com_cmm_u_cmm_decoder_N_75_11) + ); + defparam com_cmm_u_cmm_decoder_bar2_eq_raddr_3_0_I_36.INIT = 16'h0903; + LUT4 com_cmm_u_cmm_decoder_bar2_eq_raddr_3_0_I_36 ( + .I0(cfg_cfg_6102[138]), + .I1(com_cmm_bar2_reg[10]), + .I2(com_cmm_u_cmm_decoder_N_86_0), + .I3(com_cmmt_raddr[42]), + .O(com_cmm_u_cmm_decoder_N_83_11) + ); + defparam com_cmm_u_cmm_decoder_bar2_eq_raddr_3_0_I_27.INIT = 16'h0903; + LUT4 com_cmm_u_cmm_decoder_bar2_eq_raddr_3_0_I_27 ( + .I0(cfg_cfg_6102[150]), + .I1(com_cmm_bar2_reg[22]), + .I2(com_cmm_u_cmm_decoder_N_94_1), + .I3(com_cmmt_raddr[54]), + .O(com_cmm_u_cmm_decoder_N_91_11) + ); + defparam com_cmm_u_cmm_decoder_bar2_eq_raddr_3_0_I_9.INIT = 16'h0903; + LUT4 com_cmm_u_cmm_decoder_bar2_eq_raddr_3_0_I_9 ( + .I0(cfg_cfg_6102[133]), + .I1(com_cmm_bar2_reg[5]), + .I2(com_cmm_u_cmm_decoder_N_111_1), + .I3(com_cmmt_raddr[37]), + .O(com_cmm_u_cmm_decoder_N_107_10) + ); + defparam com_cmm_u_cmm_decoder_bar1_eq_raddr_3_0_I_126.INIT = 4'h1; + LUT2 com_cmm_u_cmm_decoder_bar1_eq_raddr_3_0_I_126 ( + .I0(com_cmm_u_cmm_decoder_N_6_2), + .I1(com_cmm_u_cmm_decoder_N_7_2), + .O(com_cmm_u_cmm_decoder_N_3_10) + ); + defparam com_cmm_u_cmm_decoder_bar1_eq_raddr_3_0_I_117.INIT = 16'h0903; + LUT4 com_cmm_u_cmm_decoder_bar1_eq_raddr_3_0_I_117 ( + .I0(cfg_cfg_6102[124]), + .I1(com_cmm_bar1_reg[28]), + .I2(com_cmm_u_cmm_decoder_N_14_3), + .I3(com_cmmt_raddr[60]), + .O(com_cmm_u_cmm_decoder_N_11_11) + ); + defparam com_cmm_u_cmm_decoder_bar1_eq_raddr_3_0_I_108.INIT = 4'h1; + LUT2 com_cmm_u_cmm_decoder_bar1_eq_raddr_3_0_I_108 ( + .I0(com_cmm_u_cmm_decoder_N_22_2), + .I1(com_cmm_u_cmm_decoder_N_23_2), + .O(com_cmm_u_cmm_decoder_N_19_10) + ); + defparam com_cmm_u_cmm_decoder_bar1_eq_raddr_3_0_I_99.INIT = 16'h0903; + LUT4 com_cmm_u_cmm_decoder_bar1_eq_raddr_3_0_I_99 ( + .I0(cfg_cfg_6102[102]), + .I1(com_cmm_bar1_reg[6]), + .I2(com_cmm_u_cmm_decoder_N_30_2), + .I3(com_cmmt_raddr[38]), + .O(com_cmm_u_cmm_decoder_N_27_10) + ); + defparam com_cmm_u_cmm_decoder_bar1_eq_raddr_3_0_I_90.INIT = 4'h1; + LUT2 com_cmm_u_cmm_decoder_bar1_eq_raddr_3_0_I_90 ( + .I0(com_cmm_u_cmm_decoder_N_38_2), + .I1(com_cmm_u_cmm_decoder_N_39_2), + .O(com_cmm_u_cmm_decoder_N_35_10) + ); + defparam com_cmm_u_cmm_decoder_bar1_eq_raddr_3_0_I_81.INIT = 16'h0903; + LUT4 com_cmm_u_cmm_decoder_bar1_eq_raddr_3_0_I_81 ( + .I0(cfg_cfg_6102[116]), + .I1(com_cmm_bar1_reg[20]), + .I2(com_cmm_u_cmm_decoder_N_46_2), + .I3(com_cmmt_raddr[52]), + .O(com_cmm_u_cmm_decoder_N_43_10) + ); + defparam com_cmm_u_cmm_decoder_bar1_eq_raddr_3_0_I_72.INIT = 16'h0903; + LUT4 com_cmm_u_cmm_decoder_bar1_eq_raddr_3_0_I_72 ( + .I0(cfg_cfg_6102[114]), + .I1(com_cmm_bar1_reg[18]), + .I2(com_cmm_u_cmm_decoder_N_54_2), + .I3(com_cmmt_raddr[50]), + .O(com_cmm_u_cmm_decoder_N_51_10) + ); + defparam com_cmm_u_cmm_decoder_bar1_eq_raddr_3_0_I_63.INIT = 4'h1; + LUT2 com_cmm_u_cmm_decoder_bar1_eq_raddr_3_0_I_63 ( + .I0(com_cmm_u_cmm_decoder_N_62_2), + .I1(com_cmm_u_cmm_decoder_N_63_2), + .O(com_cmm_u_cmm_decoder_N_59_10) + ); + defparam com_cmm_u_cmm_decoder_bar1_eq_raddr_3_0_I_54.INIT = 16'h0903; + LUT4 com_cmm_u_cmm_decoder_bar1_eq_raddr_3_0_I_54 ( + .I0(cfg_cfg_6102[120]), + .I1(com_cmm_bar1_reg[24]), + .I2(com_cmm_u_cmm_decoder_N_70_2), + .I3(com_cmmt_raddr[56]), + .O(com_cmm_u_cmm_decoder_N_67_10) + ); + defparam com_cmm_u_cmm_decoder_bar1_eq_raddr_3_0_I_45.INIT = 16'h0903; + LUT4 com_cmm_u_cmm_decoder_bar1_eq_raddr_3_0_I_45 ( + .I0(cfg_cfg_6102[108]), + .I1(com_cmm_bar1_reg[12]), + .I2(com_cmm_u_cmm_decoder_N_78_1), + .I3(com_cmmt_raddr[44]), + .O(com_cmm_u_cmm_decoder_N_75_10) + ); + defparam com_cmm_u_cmm_decoder_bar1_eq_raddr_3_0_I_36.INIT = 16'h0903; + LUT4 com_cmm_u_cmm_decoder_bar1_eq_raddr_3_0_I_36 ( + .I0(cfg_cfg_6102[106]), + .I1(com_cmm_bar1_reg[10]), + .I2(com_cmm_u_cmm_decoder_N_86_1), + .I3(com_cmmt_raddr[42]), + .O(com_cmm_u_cmm_decoder_N_83_10) + ); + defparam com_cmm_u_cmm_decoder_bar1_eq_raddr_3_0_I_27.INIT = 16'h0903; + LUT4 com_cmm_u_cmm_decoder_bar1_eq_raddr_3_0_I_27 ( + .I0(cfg_cfg_6102[118]), + .I1(com_cmm_bar1_reg[22]), + .I2(com_cmm_u_cmm_decoder_N_94_2), + .I3(com_cmmt_raddr[54]), + .O(com_cmm_u_cmm_decoder_N_91_10) + ); + defparam com_cmm_u_cmm_decoder_bar1_eq_raddr_3_0_I_9.INIT = 4'h1; + LUT2 com_cmm_u_cmm_decoder_bar1_eq_raddr_3_0_I_9 ( + .I0(com_cmm_u_cmm_decoder_N_110_0), + .I1(com_cmm_u_cmm_decoder_N_111_2), + .O(com_cmm_u_cmm_decoder_N_107_9) + ); + defparam com_cmm_u_cmm_decoder_bar0_eq_raddr_3_0_I_126.INIT = 16'h0903; + LUT4 com_cmm_u_cmm_decoder_bar0_eq_raddr_3_0_I_126 ( + .I0(cfg_cfg_6102[72]), + .I1(com_cmm_bar0_reg_8_), + .I2(com_cmm_u_cmm_decoder_N_6_8), + .I3(com_cmmt_raddr[40]), + .O(com_cmm_u_cmm_decoder_N_3_9) + ); + defparam com_cmm_u_cmm_decoder_bar0_eq_raddr_3_0_I_117.INIT = 16'h0903; + LUT4 com_cmm_u_cmm_decoder_bar0_eq_raddr_3_0_I_117 ( + .I0(cfg_cfg_6102[92]), + .I1(com_cmm_bar0_reg_28_), + .I2(com_cmm_u_cmm_decoder_N_14_9), + .I3(com_cmmt_raddr[60]), + .O(com_cmm_u_cmm_decoder_N_11_10) + ); + defparam com_cmm_u_cmm_decoder_bar0_eq_raddr_3_0_I_108.INIT = 16'h0903; + LUT4 com_cmm_u_cmm_decoder_bar0_eq_raddr_3_0_I_108 ( + .I0(cfg_cfg_6102[90]), + .I1(com_cmm_bar0_reg_26_), + .I2(com_cmm_u_cmm_decoder_N_22_8), + .I3(com_cmmt_raddr[58]), + .O(com_cmm_u_cmm_decoder_N_19_9) + ); + defparam com_cmm_u_cmm_decoder_bar0_eq_raddr_3_0_I_99.INIT = 16'h0903; + LUT4 com_cmm_u_cmm_decoder_bar0_eq_raddr_3_0_I_99 ( + .I0(cfg_cfg_6102[70]), + .I1(com_cmm_bar0_reg_6_), + .I2(com_cmm_u_cmm_decoder_N_30_8), + .I3(com_cmmt_raddr[38]), + .O(com_cmm_u_cmm_decoder_N_27_9) + ); + defparam com_cmm_u_cmm_decoder_bar0_eq_raddr_3_0_I_90.INIT = 16'h0903; + LUT4 com_cmm_u_cmm_decoder_bar0_eq_raddr_3_0_I_90 ( + .I0(cfg_cfg_6102[80]), + .I1(com_cmm_bar0_reg_16_), + .I2(com_cmm_u_cmm_decoder_N_38_8), + .I3(com_cmmt_raddr[48]), + .O(com_cmm_u_cmm_decoder_N_35_9) + ); + defparam com_cmm_u_cmm_decoder_bar0_eq_raddr_3_0_I_81.INIT = 16'h0903; + LUT4 com_cmm_u_cmm_decoder_bar0_eq_raddr_3_0_I_81 ( + .I0(cfg_cfg_6102[84]), + .I1(com_cmm_bar0_reg_20_), + .I2(com_cmm_u_cmm_decoder_N_46_8), + .I3(com_cmmt_raddr[52]), + .O(com_cmm_u_cmm_decoder_N_43_9) + ); + defparam com_cmm_u_cmm_decoder_bar0_eq_raddr_3_0_I_72.INIT = 16'h0903; + LUT4 com_cmm_u_cmm_decoder_bar0_eq_raddr_3_0_I_72 ( + .I0(cfg_cfg_6102[82]), + .I1(com_cmm_bar0_reg_18_), + .I2(com_cmm_u_cmm_decoder_N_54_8), + .I3(com_cmmt_raddr[50]), + .O(com_cmm_u_cmm_decoder_N_51_9) + ); + defparam com_cmm_u_cmm_decoder_bar0_eq_raddr_3_0_I_63.INIT = 16'h0903; + LUT4 com_cmm_u_cmm_decoder_bar0_eq_raddr_3_0_I_63 ( + .I0(cfg_cfg_6102[78]), + .I1(com_cmm_bar0_reg_14_), + .I2(com_cmm_u_cmm_decoder_N_62_8), + .I3(com_cmmt_raddr[46]), + .O(com_cmm_u_cmm_decoder_N_59_9) + ); + defparam com_cmm_u_cmm_decoder_bar0_eq_raddr_3_0_I_54.INIT = 16'h0903; + LUT4 com_cmm_u_cmm_decoder_bar0_eq_raddr_3_0_I_54 ( + .I0(cfg_cfg_6102[88]), + .I1(com_cmm_bar0_reg_24_), + .I2(com_cmm_u_cmm_decoder_N_70_8), + .I3(com_cmmt_raddr[56]), + .O(com_cmm_u_cmm_decoder_N_67_9) + ); + defparam com_cmm_u_cmm_decoder_bar0_eq_raddr_3_0_I_45.INIT = 16'h0903; + LUT4 com_cmm_u_cmm_decoder_bar0_eq_raddr_3_0_I_45 ( + .I0(cfg_cfg_6102[76]), + .I1(com_cmm_bar0_reg_12_), + .I2(com_cmm_u_cmm_decoder_N_78_7), + .I3(com_cmmt_raddr[44]), + .O(com_cmm_u_cmm_decoder_N_75_9) + ); + defparam com_cmm_u_cmm_decoder_bar0_eq_raddr_3_0_I_36.INIT = 16'h0903; + LUT4 com_cmm_u_cmm_decoder_bar0_eq_raddr_3_0_I_36 ( + .I0(cfg_cfg_6102[74]), + .I1(com_cmm_bar0_reg_10_), + .I2(com_cmm_u_cmm_decoder_N_86_7), + .I3(com_cmmt_raddr[42]), + .O(com_cmm_u_cmm_decoder_N_83_9) + ); + defparam com_cmm_u_cmm_decoder_bar0_eq_raddr_3_0_I_27.INIT = 16'h0903; + LUT4 com_cmm_u_cmm_decoder_bar0_eq_raddr_3_0_I_27 ( + .I0(cfg_cfg_6102[86]), + .I1(com_cmm_bar0_reg_22_), + .I2(com_cmm_u_cmm_decoder_N_94_8), + .I3(com_cmmt_raddr[54]), + .O(com_cmm_u_cmm_decoder_N_91_9) + ); + defparam com_cmm_u_cmm_decoder_bar0_eq_raddr_3_0_I_9.INIT = 16'h0903; + LUT4 com_cmm_u_cmm_decoder_bar0_eq_raddr_3_0_I_9 ( + .I0(cfg_cfg_6102[68]), + .I1(com_cmm_bar0_reg_4_), + .I2(com_cmm_u_cmm_decoder_N_110_6), + .I3(com_cmmt_raddr[36]), + .O(com_cmm_u_cmm_decoder_N_107_8) + ); + defparam com_cmm_u_cmm_decoder_un9_bar45_64_hit_high_0_I_126.INIT = 16'h0903; + LUT4 com_cmm_u_cmm_decoder_un9_bar45_64_hit_high_0_I_126 ( + .I0(cfg_cfg_6102[200]), + .I1(com_cmm_bar4_reg[8]), + .I2(com_cmm_u_cmm_decoder_N_6_7), + .I3(com_cmmt_raddr[8]), + .O(com_cmm_u_cmm_decoder_N_3_8) + ); + defparam com_cmm_u_cmm_decoder_un9_bar45_64_hit_high_0_I_117.INIT = 16'h0903; + LUT4 com_cmm_u_cmm_decoder_un9_bar45_64_hit_high_0_I_117 ( + .I0(cfg_cfg_6102[220]), + .I1(com_cmm_bar4_reg[28]), + .I2(com_cmm_u_cmm_decoder_N_14_8), + .I3(com_cmmt_raddr[28]), + .O(com_cmm_u_cmm_decoder_N_11_9) + ); + defparam com_cmm_u_cmm_decoder_un9_bar45_64_hit_high_0_I_108.INIT = 16'h0903; + LUT4 com_cmm_u_cmm_decoder_un9_bar45_64_hit_high_0_I_108 ( + .I0(cfg_cfg_6102[218]), + .I1(com_cmm_bar4_reg[26]), + .I2(com_cmm_u_cmm_decoder_N_22_7), + .I3(com_cmmt_raddr[26]), + .O(com_cmm_u_cmm_decoder_N_19_8) + ); + defparam com_cmm_u_cmm_decoder_un9_bar45_64_hit_high_0_I_99.INIT = 16'h0903; + LUT4 com_cmm_u_cmm_decoder_un9_bar45_64_hit_high_0_I_99 ( + .I0(cfg_cfg_6102[198]), + .I1(com_cmm_bar4_reg[6]), + .I2(com_cmm_u_cmm_decoder_N_30_7), + .I3(com_cmmt_raddr[6]), + .O(com_cmm_u_cmm_decoder_N_27_8) + ); + defparam com_cmm_u_cmm_decoder_un9_bar45_64_hit_high_0_I_90.INIT = 16'h0903; + LUT4 com_cmm_u_cmm_decoder_un9_bar45_64_hit_high_0_I_90 ( + .I0(cfg_cfg_6102[208]), + .I1(com_cmm_bar4_reg[16]), + .I2(com_cmm_u_cmm_decoder_N_38_7), + .I3(com_cmmt_raddr[16]), + .O(com_cmm_u_cmm_decoder_N_35_8) + ); + defparam com_cmm_u_cmm_decoder_un9_bar45_64_hit_high_0_I_81.INIT = 16'h0903; + LUT4 com_cmm_u_cmm_decoder_un9_bar45_64_hit_high_0_I_81 ( + .I0(cfg_cfg_6102[212]), + .I1(com_cmm_bar4_reg[20]), + .I2(com_cmm_u_cmm_decoder_N_46_7), + .I3(com_cmmt_raddr[20]), + .O(com_cmm_u_cmm_decoder_N_43_8) + ); + defparam com_cmm_u_cmm_decoder_un9_bar45_64_hit_high_0_I_72.INIT = 16'h0903; + LUT4 com_cmm_u_cmm_decoder_un9_bar45_64_hit_high_0_I_72 ( + .I0(cfg_cfg_6102[210]), + .I1(com_cmm_bar4_reg[18]), + .I2(com_cmm_u_cmm_decoder_N_54_7), + .I3(com_cmmt_raddr[18]), + .O(com_cmm_u_cmm_decoder_N_51_8) + ); + defparam com_cmm_u_cmm_decoder_un9_bar45_64_hit_high_0_I_63.INIT = 16'h0903; + LUT4 com_cmm_u_cmm_decoder_un9_bar45_64_hit_high_0_I_63 ( + .I0(cfg_cfg_6102[206]), + .I1(com_cmm_bar4_reg[14]), + .I2(com_cmm_u_cmm_decoder_N_62_7), + .I3(com_cmmt_raddr[14]), + .O(com_cmm_u_cmm_decoder_N_59_8) + ); + defparam com_cmm_u_cmm_decoder_un9_bar45_64_hit_high_0_I_54.INIT = 16'h0903; + LUT4 com_cmm_u_cmm_decoder_un9_bar45_64_hit_high_0_I_54 ( + .I0(cfg_cfg_6102[216]), + .I1(com_cmm_bar4_reg[24]), + .I2(com_cmm_u_cmm_decoder_N_70_7), + .I3(com_cmmt_raddr[24]), + .O(com_cmm_u_cmm_decoder_N_67_8) + ); + defparam com_cmm_u_cmm_decoder_un9_bar45_64_hit_high_0_I_45.INIT = 16'h0903; + LUT4 com_cmm_u_cmm_decoder_un9_bar45_64_hit_high_0_I_45 ( + .I0(cfg_cfg_6102[204]), + .I1(com_cmm_bar4_reg[12]), + .I2(com_cmm_u_cmm_decoder_N_78_6), + .I3(com_cmmt_raddr[12]), + .O(com_cmm_u_cmm_decoder_N_75_8) + ); + defparam com_cmm_u_cmm_decoder_un9_bar45_64_hit_high_0_I_36.INIT = 16'h0903; + LUT4 com_cmm_u_cmm_decoder_un9_bar45_64_hit_high_0_I_36 ( + .I0(cfg_cfg_6102[202]), + .I1(com_cmm_bar4_reg[10]), + .I2(com_cmm_u_cmm_decoder_N_86_6), + .I3(com_cmmt_raddr[10]), + .O(com_cmm_u_cmm_decoder_N_83_8) + ); + defparam com_cmm_u_cmm_decoder_un9_bar45_64_hit_high_0_I_27.INIT = 16'h0903; + LUT4 com_cmm_u_cmm_decoder_un9_bar45_64_hit_high_0_I_27 ( + .I0(cfg_cfg_6102[214]), + .I1(com_cmm_bar4_reg[22]), + .I2(com_cmm_u_cmm_decoder_N_94_7), + .I3(com_cmmt_raddr[22]), + .O(com_cmm_u_cmm_decoder_N_91_8) + ); + defparam com_cmm_u_cmm_decoder_un9_bar45_64_hit_high_0_I_9.INIT = 16'h0903; + LUT4 com_cmm_u_cmm_decoder_un9_bar45_64_hit_high_0_I_9 ( + .I0(cfg_cfg_6102[196]), + .I1(com_cmm_bar4_reg[4]), + .I2(com_cmm_u_cmm_decoder_N_110_5), + .I3(com_cmmt_raddr[4]), + .O(com_cmm_u_cmm_decoder_N_107_7) + ); + defparam com_cmm_u_cmm_decoder_un9_bar34_64_hit_high_0_I_126.INIT = 16'h0903; + LUT4 com_cmm_u_cmm_decoder_un9_bar34_64_hit_high_0_I_126 ( + .I0(cfg_cfg_6102[168]), + .I1(com_cmm_bar3_reg[8]), + .I2(com_cmm_u_cmm_decoder_N_6_6), + .I3(com_cmmt_raddr[8]), + .O(com_cmm_u_cmm_decoder_N_3_7) + ); + defparam com_cmm_u_cmm_decoder_un9_bar34_64_hit_high_0_I_117.INIT = 16'h0903; + LUT4 com_cmm_u_cmm_decoder_un9_bar34_64_hit_high_0_I_117 ( + .I0(cfg_cfg_6102[188]), + .I1(com_cmm_bar3_reg[28]), + .I2(com_cmm_u_cmm_decoder_N_14_7), + .I3(com_cmmt_raddr[28]), + .O(com_cmm_u_cmm_decoder_N_11_8) + ); + defparam com_cmm_u_cmm_decoder_un9_bar34_64_hit_high_0_I_108.INIT = 16'h0903; + LUT4 com_cmm_u_cmm_decoder_un9_bar34_64_hit_high_0_I_108 ( + .I0(cfg_cfg_6102[186]), + .I1(com_cmm_bar3_reg[26]), + .I2(com_cmm_u_cmm_decoder_N_22_6), + .I3(com_cmmt_raddr[26]), + .O(com_cmm_u_cmm_decoder_N_19_7) + ); + defparam com_cmm_u_cmm_decoder_un9_bar34_64_hit_high_0_I_99.INIT = 16'h0903; + LUT4 com_cmm_u_cmm_decoder_un9_bar34_64_hit_high_0_I_99 ( + .I0(cfg_cfg_6102[166]), + .I1(com_cmm_bar3_reg[6]), + .I2(com_cmm_u_cmm_decoder_N_30_6), + .I3(com_cmmt_raddr[6]), + .O(com_cmm_u_cmm_decoder_N_27_7) + ); + defparam com_cmm_u_cmm_decoder_un9_bar34_64_hit_high_0_I_90.INIT = 16'h0903; + LUT4 com_cmm_u_cmm_decoder_un9_bar34_64_hit_high_0_I_90 ( + .I0(cfg_cfg_6102[176]), + .I1(com_cmm_bar3_reg[16]), + .I2(com_cmm_u_cmm_decoder_N_38_6), + .I3(com_cmmt_raddr[16]), + .O(com_cmm_u_cmm_decoder_N_35_7) + ); + defparam com_cmm_u_cmm_decoder_un9_bar34_64_hit_high_0_I_81.INIT = 16'h0903; + LUT4 com_cmm_u_cmm_decoder_un9_bar34_64_hit_high_0_I_81 ( + .I0(cfg_cfg_6102[180]), + .I1(com_cmm_bar3_reg[20]), + .I2(com_cmm_u_cmm_decoder_N_46_6), + .I3(com_cmmt_raddr[20]), + .O(com_cmm_u_cmm_decoder_N_43_7) + ); + defparam com_cmm_u_cmm_decoder_un9_bar34_64_hit_high_0_I_72.INIT = 16'h0903; + LUT4 com_cmm_u_cmm_decoder_un9_bar34_64_hit_high_0_I_72 ( + .I0(cfg_cfg_6102[178]), + .I1(com_cmm_bar3_reg[18]), + .I2(com_cmm_u_cmm_decoder_N_54_6), + .I3(com_cmmt_raddr[18]), + .O(com_cmm_u_cmm_decoder_N_51_7) + ); + defparam com_cmm_u_cmm_decoder_un9_bar34_64_hit_high_0_I_63.INIT = 16'h0903; + LUT4 com_cmm_u_cmm_decoder_un9_bar34_64_hit_high_0_I_63 ( + .I0(cfg_cfg_6102[174]), + .I1(com_cmm_bar3_reg[14]), + .I2(com_cmm_u_cmm_decoder_N_62_6), + .I3(com_cmmt_raddr[14]), + .O(com_cmm_u_cmm_decoder_N_59_7) + ); + defparam com_cmm_u_cmm_decoder_un9_bar34_64_hit_high_0_I_54.INIT = 16'h0903; + LUT4 com_cmm_u_cmm_decoder_un9_bar34_64_hit_high_0_I_54 ( + .I0(cfg_cfg_6102[184]), + .I1(com_cmm_bar3_reg[24]), + .I2(com_cmm_u_cmm_decoder_N_70_6), + .I3(com_cmmt_raddr[24]), + .O(com_cmm_u_cmm_decoder_N_67_7) + ); + defparam com_cmm_u_cmm_decoder_un9_bar34_64_hit_high_0_I_45.INIT = 16'h0903; + LUT4 com_cmm_u_cmm_decoder_un9_bar34_64_hit_high_0_I_45 ( + .I0(cfg_cfg_6102[172]), + .I1(com_cmm_bar3_reg[12]), + .I2(com_cmm_u_cmm_decoder_N_78_5), + .I3(com_cmmt_raddr[12]), + .O(com_cmm_u_cmm_decoder_N_75_7) + ); + defparam com_cmm_u_cmm_decoder_un9_bar34_64_hit_high_0_I_36.INIT = 16'h0903; + LUT4 com_cmm_u_cmm_decoder_un9_bar34_64_hit_high_0_I_36 ( + .I0(cfg_cfg_6102[170]), + .I1(com_cmm_bar3_reg[10]), + .I2(com_cmm_u_cmm_decoder_N_86_5), + .I3(com_cmmt_raddr[10]), + .O(com_cmm_u_cmm_decoder_N_83_7) + ); + defparam com_cmm_u_cmm_decoder_un9_bar34_64_hit_high_0_I_27.INIT = 16'h0903; + LUT4 com_cmm_u_cmm_decoder_un9_bar34_64_hit_high_0_I_27 ( + .I0(cfg_cfg_6102[182]), + .I1(com_cmm_bar3_reg[22]), + .I2(com_cmm_u_cmm_decoder_N_94_6), + .I3(com_cmmt_raddr[22]), + .O(com_cmm_u_cmm_decoder_N_91_7) + ); + defparam com_cmm_u_cmm_decoder_un9_bar34_64_hit_high_0_I_9.INIT = 16'h0903; + LUT4 com_cmm_u_cmm_decoder_un9_bar34_64_hit_high_0_I_9 ( + .I0(cfg_cfg_6102[164]), + .I1(com_cmm_bar3_reg[4]), + .I2(com_cmm_u_cmm_decoder_N_110_4), + .I3(com_cmmt_raddr[4]), + .O(com_cmm_u_cmm_decoder_N_107_6) + ); + defparam com_cmm_u_cmm_decoder_un9_bar23_64_hit_high_0_I_126.INIT = 16'h0903; + LUT4 com_cmm_u_cmm_decoder_un9_bar23_64_hit_high_0_I_126 ( + .I0(cfg_cfg_6102[136]), + .I1(com_cmm_bar2_reg[8]), + .I2(com_cmm_u_cmm_decoder_N_6_5), + .I3(com_cmmt_raddr[8]), + .O(com_cmm_u_cmm_decoder_N_3_6) + ); + defparam com_cmm_u_cmm_decoder_un9_bar23_64_hit_high_0_I_117.INIT = 16'h0903; + LUT4 com_cmm_u_cmm_decoder_un9_bar23_64_hit_high_0_I_117 ( + .I0(cfg_cfg_6102[156]), + .I1(com_cmm_bar2_reg[28]), + .I2(com_cmm_u_cmm_decoder_N_14_6), + .I3(com_cmmt_raddr[28]), + .O(com_cmm_u_cmm_decoder_N_11_7) + ); + defparam com_cmm_u_cmm_decoder_un9_bar23_64_hit_high_0_I_108.INIT = 16'h0903; + LUT4 com_cmm_u_cmm_decoder_un9_bar23_64_hit_high_0_I_108 ( + .I0(cfg_cfg_6102[154]), + .I1(com_cmm_bar2_reg[26]), + .I2(com_cmm_u_cmm_decoder_N_22_5), + .I3(com_cmmt_raddr[26]), + .O(com_cmm_u_cmm_decoder_N_19_6) + ); + defparam com_cmm_u_cmm_decoder_un9_bar23_64_hit_high_0_I_99.INIT = 16'h0903; + LUT4 com_cmm_u_cmm_decoder_un9_bar23_64_hit_high_0_I_99 ( + .I0(cfg_cfg_6102[134]), + .I1(com_cmm_bar2_reg[6]), + .I2(com_cmm_u_cmm_decoder_N_30_5), + .I3(com_cmmt_raddr[6]), + .O(com_cmm_u_cmm_decoder_N_27_6) + ); + defparam com_cmm_u_cmm_decoder_un9_bar23_64_hit_high_0_I_90.INIT = 16'h0903; + LUT4 com_cmm_u_cmm_decoder_un9_bar23_64_hit_high_0_I_90 ( + .I0(cfg_cfg_6102[144]), + .I1(com_cmm_bar2_reg[16]), + .I2(com_cmm_u_cmm_decoder_N_38_5), + .I3(com_cmmt_raddr[16]), + .O(com_cmm_u_cmm_decoder_N_35_6) + ); + defparam com_cmm_u_cmm_decoder_un9_bar23_64_hit_high_0_I_81.INIT = 16'h0903; + LUT4 com_cmm_u_cmm_decoder_un9_bar23_64_hit_high_0_I_81 ( + .I0(cfg_cfg_6102[148]), + .I1(com_cmm_bar2_reg[20]), + .I2(com_cmm_u_cmm_decoder_N_46_5), + .I3(com_cmmt_raddr[20]), + .O(com_cmm_u_cmm_decoder_N_43_6) + ); + defparam com_cmm_u_cmm_decoder_un9_bar23_64_hit_high_0_I_72.INIT = 16'h0903; + LUT4 com_cmm_u_cmm_decoder_un9_bar23_64_hit_high_0_I_72 ( + .I0(cfg_cfg_6102[146]), + .I1(com_cmm_bar2_reg[18]), + .I2(com_cmm_u_cmm_decoder_N_54_5), + .I3(com_cmmt_raddr[18]), + .O(com_cmm_u_cmm_decoder_N_51_6) + ); + defparam com_cmm_u_cmm_decoder_un9_bar23_64_hit_high_0_I_63.INIT = 16'h0903; + LUT4 com_cmm_u_cmm_decoder_un9_bar23_64_hit_high_0_I_63 ( + .I0(cfg_cfg_6102[142]), + .I1(com_cmm_bar2_reg[14]), + .I2(com_cmm_u_cmm_decoder_N_62_5), + .I3(com_cmmt_raddr[14]), + .O(com_cmm_u_cmm_decoder_N_59_6) + ); + defparam com_cmm_u_cmm_decoder_un9_bar23_64_hit_high_0_I_54.INIT = 16'h0903; + LUT4 com_cmm_u_cmm_decoder_un9_bar23_64_hit_high_0_I_54 ( + .I0(cfg_cfg_6102[152]), + .I1(com_cmm_bar2_reg[24]), + .I2(com_cmm_u_cmm_decoder_N_70_5), + .I3(com_cmmt_raddr[24]), + .O(com_cmm_u_cmm_decoder_N_67_6) + ); + defparam com_cmm_u_cmm_decoder_un9_bar23_64_hit_high_0_I_45.INIT = 16'h0903; + LUT4 com_cmm_u_cmm_decoder_un9_bar23_64_hit_high_0_I_45 ( + .I0(cfg_cfg_6102[140]), + .I1(com_cmm_bar2_reg[12]), + .I2(com_cmm_u_cmm_decoder_N_78_4), + .I3(com_cmmt_raddr[12]), + .O(com_cmm_u_cmm_decoder_N_75_6) + ); + defparam com_cmm_u_cmm_decoder_un9_bar23_64_hit_high_0_I_36.INIT = 16'h0903; + LUT4 com_cmm_u_cmm_decoder_un9_bar23_64_hit_high_0_I_36 ( + .I0(cfg_cfg_6102[138]), + .I1(com_cmm_bar2_reg[10]), + .I2(com_cmm_u_cmm_decoder_N_86_4), + .I3(com_cmmt_raddr[10]), + .O(com_cmm_u_cmm_decoder_N_83_6) + ); + defparam com_cmm_u_cmm_decoder_un9_bar23_64_hit_high_0_I_27.INIT = 16'h0903; + LUT4 com_cmm_u_cmm_decoder_un9_bar23_64_hit_high_0_I_27 ( + .I0(cfg_cfg_6102[150]), + .I1(com_cmm_bar2_reg[22]), + .I2(com_cmm_u_cmm_decoder_N_94_5), + .I3(com_cmmt_raddr[22]), + .O(com_cmm_u_cmm_decoder_N_91_6) + ); + defparam com_cmm_u_cmm_decoder_un9_bar23_64_hit_high_0_I_9.INIT = 16'h0903; + LUT4 com_cmm_u_cmm_decoder_un9_bar23_64_hit_high_0_I_9 ( + .I0(cfg_cfg_6102[132]), + .I1(com_cmm_bar2_reg[4]), + .I2(com_cmm_u_cmm_decoder_N_110_3), + .I3(com_cmmt_raddr[4]), + .O(com_cmm_u_cmm_decoder_N_107_5) + ); + defparam com_cmm_u_cmm_decoder_un9_bar12_64_hit_high_0_I_126.INIT = 16'h0903; + LUT4 com_cmm_u_cmm_decoder_un9_bar12_64_hit_high_0_I_126 ( + .I0(cfg_cfg_6102[104]), + .I1(com_cmm_bar1_reg[8]), + .I2(com_cmm_u_cmm_decoder_N_6_4), + .I3(com_cmmt_raddr[8]), + .O(com_cmm_u_cmm_decoder_N_3_5) + ); + defparam com_cmm_u_cmm_decoder_un9_bar12_64_hit_high_0_I_117.INIT = 16'h0903; + LUT4 com_cmm_u_cmm_decoder_un9_bar12_64_hit_high_0_I_117 ( + .I0(cfg_cfg_6102[124]), + .I1(com_cmm_bar1_reg[28]), + .I2(com_cmm_u_cmm_decoder_N_14_5), + .I3(com_cmmt_raddr[28]), + .O(com_cmm_u_cmm_decoder_N_11_6) + ); + defparam com_cmm_u_cmm_decoder_un9_bar12_64_hit_high_0_I_108.INIT = 16'h0903; + LUT4 com_cmm_u_cmm_decoder_un9_bar12_64_hit_high_0_I_108 ( + .I0(cfg_cfg_6102[122]), + .I1(com_cmm_bar1_reg[26]), + .I2(com_cmm_u_cmm_decoder_N_22_4), + .I3(com_cmmt_raddr[26]), + .O(com_cmm_u_cmm_decoder_N_19_5) + ); + defparam com_cmm_u_cmm_decoder_un9_bar12_64_hit_high_0_I_99.INIT = 16'h0903; + LUT4 com_cmm_u_cmm_decoder_un9_bar12_64_hit_high_0_I_99 ( + .I0(cfg_cfg_6102[102]), + .I1(com_cmm_bar1_reg[6]), + .I2(com_cmm_u_cmm_decoder_N_30_4), + .I3(com_cmmt_raddr[6]), + .O(com_cmm_u_cmm_decoder_N_27_5) + ); + defparam com_cmm_u_cmm_decoder_un9_bar12_64_hit_high_0_I_90.INIT = 16'h0903; + LUT4 com_cmm_u_cmm_decoder_un9_bar12_64_hit_high_0_I_90 ( + .I0(cfg_cfg_6102[112]), + .I1(com_cmm_bar1_reg[16]), + .I2(com_cmm_u_cmm_decoder_N_38_4), + .I3(com_cmmt_raddr[16]), + .O(com_cmm_u_cmm_decoder_N_35_5) + ); + defparam com_cmm_u_cmm_decoder_un9_bar12_64_hit_high_0_I_81.INIT = 16'h0903; + LUT4 com_cmm_u_cmm_decoder_un9_bar12_64_hit_high_0_I_81 ( + .I0(cfg_cfg_6102[116]), + .I1(com_cmm_bar1_reg[20]), + .I2(com_cmm_u_cmm_decoder_N_46_4), + .I3(com_cmmt_raddr[20]), + .O(com_cmm_u_cmm_decoder_N_43_5) + ); + defparam com_cmm_u_cmm_decoder_un9_bar12_64_hit_high_0_I_72.INIT = 16'h0903; + LUT4 com_cmm_u_cmm_decoder_un9_bar12_64_hit_high_0_I_72 ( + .I0(cfg_cfg_6102[114]), + .I1(com_cmm_bar1_reg[18]), + .I2(com_cmm_u_cmm_decoder_N_54_4), + .I3(com_cmmt_raddr[18]), + .O(com_cmm_u_cmm_decoder_N_51_5) + ); + defparam com_cmm_u_cmm_decoder_un9_bar12_64_hit_high_0_I_63.INIT = 16'h0903; + LUT4 com_cmm_u_cmm_decoder_un9_bar12_64_hit_high_0_I_63 ( + .I0(cfg_cfg_6102[110]), + .I1(com_cmm_bar1_reg[14]), + .I2(com_cmm_u_cmm_decoder_N_62_4), + .I3(com_cmmt_raddr[14]), + .O(com_cmm_u_cmm_decoder_N_59_5) + ); + defparam com_cmm_u_cmm_decoder_un9_bar12_64_hit_high_0_I_54.INIT = 16'h0903; + LUT4 com_cmm_u_cmm_decoder_un9_bar12_64_hit_high_0_I_54 ( + .I0(cfg_cfg_6102[120]), + .I1(com_cmm_bar1_reg[24]), + .I2(com_cmm_u_cmm_decoder_N_70_4), + .I3(com_cmmt_raddr[24]), + .O(com_cmm_u_cmm_decoder_N_67_5) + ); + defparam com_cmm_u_cmm_decoder_un9_bar12_64_hit_high_0_I_45.INIT = 16'h0903; + LUT4 com_cmm_u_cmm_decoder_un9_bar12_64_hit_high_0_I_45 ( + .I0(cfg_cfg_6102[108]), + .I1(com_cmm_bar1_reg[12]), + .I2(com_cmm_u_cmm_decoder_N_78_3), + .I3(com_cmmt_raddr[12]), + .O(com_cmm_u_cmm_decoder_N_75_5) + ); + defparam com_cmm_u_cmm_decoder_un9_bar12_64_hit_high_0_I_36.INIT = 16'h0903; + LUT4 com_cmm_u_cmm_decoder_un9_bar12_64_hit_high_0_I_36 ( + .I0(cfg_cfg_6102[106]), + .I1(com_cmm_bar1_reg[10]), + .I2(com_cmm_u_cmm_decoder_N_86_3), + .I3(com_cmmt_raddr[10]), + .O(com_cmm_u_cmm_decoder_N_83_5) + ); + defparam com_cmm_u_cmm_decoder_un9_bar12_64_hit_high_0_I_27.INIT = 16'h0903; + LUT4 com_cmm_u_cmm_decoder_un9_bar12_64_hit_high_0_I_27 ( + .I0(cfg_cfg_6102[118]), + .I1(com_cmm_bar1_reg[22]), + .I2(com_cmm_u_cmm_decoder_N_94_4), + .I3(com_cmmt_raddr[22]), + .O(com_cmm_u_cmm_decoder_N_91_5) + ); + defparam com_cmm_u_cmm_decoder_un9_bar12_64_hit_high_0_I_9.INIT = 16'h0903; + LUT4 com_cmm_u_cmm_decoder_un9_bar12_64_hit_high_0_I_9 ( + .I0(cfg_cfg_6102[100]), + .I1(com_cmm_bar1_reg[4]), + .I2(com_cmm_u_cmm_decoder_N_110_2), + .I3(com_cmmt_raddr[4]), + .O(com_cmm_u_cmm_decoder_N_107_4) + ); + defparam com_cmm_u_cmm_decoder_un9_bar01_64_hit_high_0_I_126.INIT = 16'h0903; + LUT4 com_cmm_u_cmm_decoder_un9_bar01_64_hit_high_0_I_126 ( + .I0(cfg_cfg_6102[72]), + .I1(com_cmm_bar0_reg_8_), + .I2(com_cmm_u_cmm_decoder_N_6_3), + .I3(com_cmmt_raddr[8]), + .O(com_cmm_u_cmm_decoder_N_3_4) + ); + defparam com_cmm_u_cmm_decoder_un9_bar01_64_hit_high_0_I_117.INIT = 16'h0903; + LUT4 com_cmm_u_cmm_decoder_un9_bar01_64_hit_high_0_I_117 ( + .I0(cfg_cfg_6102[92]), + .I1(com_cmm_bar0_reg_28_), + .I2(com_cmm_u_cmm_decoder_N_14_4), + .I3(com_cmmt_raddr[28]), + .O(com_cmm_u_cmm_decoder_N_11_5) + ); + defparam com_cmm_u_cmm_decoder_un9_bar01_64_hit_high_0_I_108.INIT = 16'h0903; + LUT4 com_cmm_u_cmm_decoder_un9_bar01_64_hit_high_0_I_108 ( + .I0(cfg_cfg_6102[90]), + .I1(com_cmm_bar0_reg_26_), + .I2(com_cmm_u_cmm_decoder_N_22_3), + .I3(com_cmmt_raddr[26]), + .O(com_cmm_u_cmm_decoder_N_19_4) + ); + defparam com_cmm_u_cmm_decoder_un9_bar01_64_hit_high_0_I_99.INIT = 16'h0903; + LUT4 com_cmm_u_cmm_decoder_un9_bar01_64_hit_high_0_I_99 ( + .I0(cfg_cfg_6102[70]), + .I1(com_cmm_bar0_reg_6_), + .I2(com_cmm_u_cmm_decoder_N_30_3), + .I3(com_cmmt_raddr[6]), + .O(com_cmm_u_cmm_decoder_N_27_4) + ); + defparam com_cmm_u_cmm_decoder_un9_bar01_64_hit_high_0_I_90.INIT = 16'h0903; + LUT4 com_cmm_u_cmm_decoder_un9_bar01_64_hit_high_0_I_90 ( + .I0(cfg_cfg_6102[80]), + .I1(com_cmm_bar0_reg_16_), + .I2(com_cmm_u_cmm_decoder_N_38_3), + .I3(com_cmmt_raddr[16]), + .O(com_cmm_u_cmm_decoder_N_35_4) + ); + defparam com_cmm_u_cmm_decoder_un9_bar01_64_hit_high_0_I_81.INIT = 16'h0903; + LUT4 com_cmm_u_cmm_decoder_un9_bar01_64_hit_high_0_I_81 ( + .I0(cfg_cfg_6102[84]), + .I1(com_cmm_bar0_reg_20_), + .I2(com_cmm_u_cmm_decoder_N_46_3), + .I3(com_cmmt_raddr[20]), + .O(com_cmm_u_cmm_decoder_N_43_4) + ); + defparam com_cmm_u_cmm_decoder_un9_bar01_64_hit_high_0_I_72.INIT = 16'h0903; + LUT4 com_cmm_u_cmm_decoder_un9_bar01_64_hit_high_0_I_72 ( + .I0(cfg_cfg_6102[82]), + .I1(com_cmm_bar0_reg_18_), + .I2(com_cmm_u_cmm_decoder_N_54_3), + .I3(com_cmmt_raddr[18]), + .O(com_cmm_u_cmm_decoder_N_51_4) + ); + defparam com_cmm_u_cmm_decoder_un9_bar01_64_hit_high_0_I_63.INIT = 16'h0903; + LUT4 com_cmm_u_cmm_decoder_un9_bar01_64_hit_high_0_I_63 ( + .I0(cfg_cfg_6102[78]), + .I1(com_cmm_bar0_reg_14_), + .I2(com_cmm_u_cmm_decoder_N_62_3), + .I3(com_cmmt_raddr[14]), + .O(com_cmm_u_cmm_decoder_N_59_4) + ); + defparam com_cmm_u_cmm_decoder_un9_bar01_64_hit_high_0_I_54.INIT = 16'h0903; + LUT4 com_cmm_u_cmm_decoder_un9_bar01_64_hit_high_0_I_54 ( + .I0(cfg_cfg_6102[88]), + .I1(com_cmm_bar0_reg_24_), + .I2(com_cmm_u_cmm_decoder_N_70_3), + .I3(com_cmmt_raddr[24]), + .O(com_cmm_u_cmm_decoder_N_67_4) + ); + defparam com_cmm_u_cmm_decoder_un9_bar01_64_hit_high_0_I_45.INIT = 16'h0903; + LUT4 com_cmm_u_cmm_decoder_un9_bar01_64_hit_high_0_I_45 ( + .I0(cfg_cfg_6102[76]), + .I1(com_cmm_bar0_reg_12_), + .I2(com_cmm_u_cmm_decoder_N_78_2), + .I3(com_cmmt_raddr[12]), + .O(com_cmm_u_cmm_decoder_N_75_4) + ); + defparam com_cmm_u_cmm_decoder_un9_bar01_64_hit_high_0_I_36.INIT = 16'h0903; + LUT4 com_cmm_u_cmm_decoder_un9_bar01_64_hit_high_0_I_36 ( + .I0(cfg_cfg_6102[74]), + .I1(com_cmm_bar0_reg_10_), + .I2(com_cmm_u_cmm_decoder_N_86_2), + .I3(com_cmmt_raddr[10]), + .O(com_cmm_u_cmm_decoder_N_83_4) + ); + defparam com_cmm_u_cmm_decoder_un9_bar01_64_hit_high_0_I_27.INIT = 16'h0903; + LUT4 com_cmm_u_cmm_decoder_un9_bar01_64_hit_high_0_I_27 ( + .I0(cfg_cfg_6102[86]), + .I1(com_cmm_bar0_reg_22_), + .I2(com_cmm_u_cmm_decoder_N_94_3), + .I3(com_cmmt_raddr[22]), + .O(com_cmm_u_cmm_decoder_N_91_4) + ); + defparam com_cmm_u_cmm_decoder_un9_bar01_64_hit_high_0_I_9.INIT = 16'h0903; + LUT4 com_cmm_u_cmm_decoder_un9_bar01_64_hit_high_0_I_9 ( + .I0(cfg_cfg_6102[68]), + .I1(com_cmm_bar0_reg_4_), + .I2(com_cmm_u_cmm_decoder_N_110_1), + .I3(com_cmmt_raddr[4]), + .O(com_cmm_u_cmm_decoder_N_107_3) + ); + defparam com_cmm_u_cmm_decoder_bar6_eq_raddr_3_0_I_90.INIT = 16'h2103; + LUT4 com_cmm_u_cmm_decoder_bar6_eq_raddr_3_0_I_90 ( + .I0(cfg_cfg_6102[339]), + .I1(com_cmm_u_cmm_decoder_N_12), + .I2(com_cmm_xrom_reg_19_), + .I3(com_cmmt_raddr[51]), + .O(com_cmm_u_cmm_decoder_N_9) + ); + defparam com_cmm_u_cmm_decoder_bar6_eq_raddr_3_0_I_81.INIT = 16'h2103; + LUT4 com_cmm_u_cmm_decoder_bar6_eq_raddr_3_0_I_81 ( + .I0(cfg_cfg_6102[333]), + .I1(com_cmm_u_cmm_decoder_N_20), + .I2(com_cmm_xrom_reg_13_), + .I3(com_cmmt_raddr[45]), + .O(com_cmm_u_cmm_decoder_N_17) + ); + defparam com_cmm_u_cmm_decoder_bar6_eq_raddr_3_0_I_72.INIT = 16'h2103; + LUT4 com_cmm_u_cmm_decoder_bar6_eq_raddr_3_0_I_72 ( + .I0(cfg_cfg_6102[345]), + .I1(com_cmm_u_cmm_decoder_N_28), + .I2(com_cmm_xrom_reg_25_), + .I3(com_cmmt_raddr[57]), + .O(com_cmm_u_cmm_decoder_N_25) + ); + defparam com_cmm_u_cmm_decoder_bar6_eq_raddr_3_0_I_63.INIT = 16'h2103; + LUT4 com_cmm_u_cmm_decoder_bar6_eq_raddr_3_0_I_63 ( + .I0(cfg_cfg_6102[343]), + .I1(com_cmm_u_cmm_decoder_N_36), + .I2(com_cmm_xrom_reg_23_), + .I3(com_cmmt_raddr[55]), + .O(com_cmm_u_cmm_decoder_N_33) + ); + defparam com_cmm_u_cmm_decoder_bar6_eq_raddr_3_0_I_54.INIT = 16'h2103; + LUT4 com_cmm_u_cmm_decoder_bar6_eq_raddr_3_0_I_54 ( + .I0(cfg_cfg_6102[347]), + .I1(com_cmm_u_cmm_decoder_N_44), + .I2(com_cmm_xrom_reg_27_), + .I3(com_cmmt_raddr[59]), + .O(com_cmm_u_cmm_decoder_N_41) + ); + defparam com_cmm_u_cmm_decoder_bar6_eq_raddr_3_0_I_45.INIT = 16'h2103; + LUT4 com_cmm_u_cmm_decoder_bar6_eq_raddr_3_0_I_45 ( + .I0(cfg_cfg_6102[341]), + .I1(com_cmm_u_cmm_decoder_N_52), + .I2(com_cmm_xrom_reg_21_), + .I3(com_cmmt_raddr[53]), + .O(com_cmm_u_cmm_decoder_N_49) + ); + defparam com_cmm_u_cmm_decoder_bar6_eq_raddr_3_0_I_36.INIT = 16'h2103; + LUT4 com_cmm_u_cmm_decoder_bar6_eq_raddr_3_0_I_36 ( + .I0(cfg_cfg_6102[337]), + .I1(com_cmm_u_cmm_decoder_N_60), + .I2(com_cmm_xrom_reg_17_), + .I3(com_cmmt_raddr[49]), + .O(com_cmm_u_cmm_decoder_N_57) + ); + defparam com_cmm_u_cmm_decoder_bar6_eq_raddr_3_0_I_27.INIT = 16'h2103; + LUT4 com_cmm_u_cmm_decoder_bar6_eq_raddr_3_0_I_27 ( + .I0(cfg_cfg_6102[335]), + .I1(com_cmm_u_cmm_decoder_N_68), + .I2(com_cmm_xrom_reg_15_), + .I3(com_cmmt_raddr[47]), + .O(com_cmm_u_cmm_decoder_N_65) + ); + defparam com_cmm_u_cmm_decoder_bar6_eq_raddr_3_0_I_18.INIT = 16'h2103; + LUT4 com_cmm_u_cmm_decoder_bar6_eq_raddr_3_0_I_18 ( + .I0(cfg_cfg_6102[349]), + .I1(com_cmm_u_cmm_decoder_N_76), + .I2(com_cmm_xrom_reg_29_), + .I3(com_cmmt_raddr[61]), + .O(com_cmm_u_cmm_decoder_N_73) + ); + defparam com_cmm_u_cmm_decoder_bar6_eq_raddr_3_0_I_9.INIT = 16'h2103; + LUT4 com_cmm_u_cmm_decoder_bar6_eq_raddr_3_0_I_9 ( + .I0(cfg_cfg_6102[331]), + .I1(com_cmm_u_cmm_decoder_N_84), + .I2(com_cmm_xrom_reg_11_), + .I3(com_cmmt_raddr[43]), + .O(com_cmm_u_cmm_decoder_N_81) + ); + defparam com_cmm_u_cmm_decoder_bar5_eq_raddr_3_0_I_118_sf.INIT = 4'h2; + LUT1 com_cmm_u_cmm_decoder_bar5_eq_raddr_3_0_I_118_sf ( + .I0(com_cmm_u_cmm_decoder_N_3_3), + .O(com_cmm_u_cmm_decoder_I_118_sf) + ); + defparam com_cmm_u_cmm_decoder_bar5_eq_raddr_3_0_I_109_sf.INIT = 4'h2; + LUT1 com_cmm_u_cmm_decoder_bar5_eq_raddr_3_0_I_109_sf ( + .I0(com_cmm_u_cmm_decoder_N_11_4), + .O(com_cmm_u_cmm_decoder_I_109_sf) + ); + defparam com_cmm_u_cmm_decoder_bar5_eq_raddr_3_0_I_100_sf.INIT = 4'h2; + LUT1 com_cmm_u_cmm_decoder_bar5_eq_raddr_3_0_I_100_sf ( + .I0(com_cmm_u_cmm_decoder_N_19_3), + .O(com_cmm_u_cmm_decoder_I_100_sf) + ); + defparam com_cmm_u_cmm_decoder_bar5_eq_raddr_3_0_I_91_sf.INIT = 4'h2; + LUT1 com_cmm_u_cmm_decoder_bar5_eq_raddr_3_0_I_91_sf ( + .I0(com_cmm_u_cmm_decoder_N_27_3), + .O(com_cmm_u_cmm_decoder_I_91_sf) + ); + defparam com_cmm_u_cmm_decoder_bar5_eq_raddr_3_0_I_82_sf.INIT = 4'h2; + LUT1 com_cmm_u_cmm_decoder_bar5_eq_raddr_3_0_I_82_sf ( + .I0(com_cmm_u_cmm_decoder_N_35_3), + .O(com_cmm_u_cmm_decoder_I_82_sf) + ); + defparam com_cmm_u_cmm_decoder_bar5_eq_raddr_3_0_I_73_sf.INIT = 4'h2; + LUT1 com_cmm_u_cmm_decoder_bar5_eq_raddr_3_0_I_73_sf ( + .I0(com_cmm_u_cmm_decoder_N_43_3), + .O(com_cmm_u_cmm_decoder_I_73_sf) + ); + defparam com_cmm_u_cmm_decoder_bar5_eq_raddr_3_0_I_64_sf.INIT = 4'h2; + LUT1 com_cmm_u_cmm_decoder_bar5_eq_raddr_3_0_I_64_sf ( + .I0(com_cmm_u_cmm_decoder_N_51_3), + .O(com_cmm_u_cmm_decoder_I_64_sf) + ); + defparam com_cmm_u_cmm_decoder_bar5_eq_raddr_3_0_I_55_sf.INIT = 4'h2; + LUT1 com_cmm_u_cmm_decoder_bar5_eq_raddr_3_0_I_55_sf ( + .I0(com_cmm_u_cmm_decoder_N_59_3), + .O(com_cmm_u_cmm_decoder_I_55_sf) + ); + defparam com_cmm_u_cmm_decoder_bar5_eq_raddr_3_0_I_46_sf.INIT = 4'h2; + LUT1 com_cmm_u_cmm_decoder_bar5_eq_raddr_3_0_I_46_sf ( + .I0(com_cmm_u_cmm_decoder_N_67_3), + .O(com_cmm_u_cmm_decoder_I_46_sf) + ); + defparam com_cmm_u_cmm_decoder_bar5_eq_raddr_3_0_I_37_sf.INIT = 4'h2; + LUT1 com_cmm_u_cmm_decoder_bar5_eq_raddr_3_0_I_37_sf ( + .I0(com_cmm_u_cmm_decoder_N_75_3), + .O(com_cmm_u_cmm_decoder_I_37_sf) + ); + defparam com_cmm_u_cmm_decoder_bar5_eq_raddr_3_0_I_28_sf.INIT = 4'h2; + LUT1 com_cmm_u_cmm_decoder_bar5_eq_raddr_3_0_I_28_sf ( + .I0(com_cmm_u_cmm_decoder_N_83_3), + .O(com_cmm_u_cmm_decoder_I_28_sf) + ); + defparam com_cmm_u_cmm_decoder_bar5_eq_raddr_3_0_I_19_sf.INIT = 4'h2; + LUT1 com_cmm_u_cmm_decoder_bar5_eq_raddr_3_0_I_19_sf ( + .I0(com_cmm_u_cmm_decoder_N_91_3), + .O(com_cmm_u_cmm_decoder_I_19_sf) + ); + defparam com_cmm_u_cmm_decoder_un10_bar01_64_hit_low_0_I_144.INIT = 16'h0903; + LUT4 com_cmm_u_cmm_decoder_un10_bar01_64_hit_low_0_I_144 ( + .I0(cfg_cfg_6102[108]), + .I1(com_cmm_bar1_reg[12]), + .I2(com_cmm_u_cmm_decoder_N_86_1), + .I3(com_cmmt_raddr[44]), + .O(com_cmm_u_cmm_decoder_N_3_2) + ); + defparam com_cmm_u_cmm_decoder_un10_bar01_64_hit_low_0_I_135.INIT = 16'h0903; + LUT4 com_cmm_u_cmm_decoder_un10_bar01_64_hit_low_0_I_135 ( + .I0(cfg_cfg_6102[97]), + .I1(com_cmm_bar1_reg[1]), + .I2(com_cmm_u_cmm_decoder_N_102_2), + .I3(com_cmmt_raddr[33]), + .O(com_cmm_u_cmm_decoder_N_11_3) + ); + defparam com_cmm_u_cmm_decoder_un10_bar01_64_hit_low_0_I_126.INIT = 16'h0903; + LUT4 com_cmm_u_cmm_decoder_un10_bar01_64_hit_low_0_I_126 ( + .I0(cfg_cfg_6102[126]), + .I1(com_cmm_bar1_reg[30]), + .I2(com_cmm_u_cmm_decoder_N_14_3), + .I3(com_cmmt_raddr[62]), + .O(com_cmm_u_cmm_decoder_N_19_2) + ); + defparam com_cmm_u_cmm_decoder_un10_bar01_64_hit_low_0_I_117.INIT = 16'h0903; + LUT4 com_cmm_u_cmm_decoder_un10_bar01_64_hit_low_0_I_117 ( + .I0(cfg_cfg_6102[106]), + .I1(com_cmm_bar1_reg[10]), + .I2(com_cmm_u_cmm_decoder_N_6_2), + .I3(com_cmmt_raddr[42]), + .O(com_cmm_u_cmm_decoder_N_27_2) + ); + defparam com_cmm_u_cmm_decoder_un10_bar01_64_hit_low_0_I_108.INIT = 16'h0903; + LUT4 com_cmm_u_cmm_decoder_un10_bar01_64_hit_low_0_I_108 ( + .I0(cfg_cfg_6102[116]), + .I1(com_cmm_bar1_reg[20]), + .I2(com_cmm_u_cmm_decoder_N_54_2), + .I3(com_cmmt_raddr[52]), + .O(com_cmm_u_cmm_decoder_N_35_2) + ); + defparam com_cmm_u_cmm_decoder_un10_bar01_64_hit_low_0_I_99.INIT = 16'h0903; + LUT4 com_cmm_u_cmm_decoder_un10_bar01_64_hit_low_0_I_99 ( + .I0(cfg_cfg_6102[120]), + .I1(com_cmm_bar1_reg[24]), + .I2(com_cmm_u_cmm_decoder_N_94_2), + .I3(com_cmmt_raddr[56]), + .O(com_cmm_u_cmm_decoder_N_43_2) + ); + defparam com_cmm_u_cmm_decoder_un10_bar01_64_hit_low_0_I_90.INIT = 16'h0903; + LUT4 com_cmm_u_cmm_decoder_un10_bar01_64_hit_low_0_I_90 ( + .I0(cfg_cfg_6102[118]), + .I1(com_cmm_bar1_reg[22]), + .I2(com_cmm_u_cmm_decoder_N_46_2), + .I3(com_cmmt_raddr[54]), + .O(com_cmm_u_cmm_decoder_N_51_2) + ); + defparam com_cmm_u_cmm_decoder_un10_bar01_64_hit_low_0_I_81.INIT = 16'h0903; + LUT4 com_cmm_u_cmm_decoder_un10_bar01_64_hit_low_0_I_81 ( + .I0(cfg_cfg_6102[114]), + .I1(com_cmm_bar1_reg[18]), + .I2(com_cmm_u_cmm_decoder_N_38_2), + .I3(com_cmmt_raddr[50]), + .O(com_cmm_u_cmm_decoder_N_59_2) + ); + defparam com_cmm_u_cmm_decoder_un10_bar01_64_hit_low_0_I_72.INIT = 16'h0903; + LUT4 com_cmm_u_cmm_decoder_un10_bar01_64_hit_low_0_I_72 ( + .I0(cfg_cfg_6102[124]), + .I1(com_cmm_bar1_reg[28]), + .I2(com_cmm_u_cmm_decoder_N_22_2), + .I3(com_cmmt_raddr[60]), + .O(com_cmm_u_cmm_decoder_N_67_2) + ); + defparam com_cmm_u_cmm_decoder_un10_bar01_64_hit_low_0_I_63.INIT = 4'h1; + LUT2 com_cmm_u_cmm_decoder_un10_bar01_64_hit_low_0_I_63 ( + .I0(com_cmm_u_cmm_decoder_N_39_2), + .I1(com_cmm_u_cmm_decoder_N_62_2), + .O(com_cmm_u_cmm_decoder_N_75_2) + ); + defparam com_cmm_u_cmm_decoder_un10_bar01_64_hit_low_0_I_54.INIT = 4'h1; + LUT2 com_cmm_u_cmm_decoder_un10_bar01_64_hit_low_0_I_54 ( + .I0(com_cmm_u_cmm_decoder_N_63_2), + .I1(com_cmm_u_cmm_decoder_N_78_1), + .O(com_cmm_u_cmm_decoder_N_83_2) + ); + defparam com_cmm_u_cmm_decoder_un10_bar01_64_hit_low_0_I_45.INIT = 4'h1; + LUT2 com_cmm_u_cmm_decoder_un10_bar01_64_hit_low_0_I_45 ( + .I0(com_cmm_u_cmm_decoder_N_23_2), + .I1(com_cmm_u_cmm_decoder_N_70_2), + .O(com_cmm_u_cmm_decoder_N_91_2) + ); + defparam com_cmm_u_cmm_decoder_un10_bar01_64_hit_low_0_I_27.INIT = 4'h1; + LUT2 com_cmm_u_cmm_decoder_un10_bar01_64_hit_low_0_I_27 ( + .I0(com_cmm_u_cmm_decoder_N_7_2), + .I1(com_cmm_u_cmm_decoder_N_30_2), + .O(com_cmm_u_cmm_decoder_N_107_2) + ); + defparam com_cmm_u_cmm_decoder_un10_bar01_64_hit_low_0_I_18.INIT = 16'h0903; + LUT4 com_cmm_u_cmm_decoder_un10_bar01_64_hit_low_0_I_18 ( + .I0(cfg_cfg_6102[102]), + .I1(com_cmm_bar1_reg[6]), + .I2(com_cmm_u_cmm_decoder_N_110_0), + .I3(com_cmmt_raddr[38]), + .O(com_cmm_u_cmm_decoder_N_115_2) + ); + defparam com_cmm_u_cmm_decoder_un10_bar01_64_hit_low_0_I_9.INIT = 16'h0903; + LUT4 com_cmm_u_cmm_decoder_un10_bar01_64_hit_low_0_I_9 ( + .I0(cfg_cfg_6102[99]), + .I1(com_cmm_bar1_reg[3]), + .I2(com_cmm_u_cmm_decoder_N_111_2), + .I3(com_cmmt_raddr[35]), + .O(com_cmm_u_cmm_decoder_N_123_2) + ); + defparam com_cmm_u_cmm_decoder_un10_bar12_64_hit_low_0_I_144.INIT = 16'h0903; + LUT4 com_cmm_u_cmm_decoder_un10_bar12_64_hit_low_0_I_144 ( + .I0(cfg_cfg_6102[140]), + .I1(com_cmm_bar2_reg[12]), + .I2(com_cmm_u_cmm_decoder_N_86_0), + .I3(com_cmmt_raddr[44]), + .O(com_cmm_u_cmm_decoder_N_3_1) + ); + defparam com_cmm_u_cmm_decoder_un10_bar12_64_hit_low_0_I_135.INIT = 16'h0903; + LUT4 com_cmm_u_cmm_decoder_un10_bar12_64_hit_low_0_I_135 ( + .I0(cfg_cfg_6102[129]), + .I1(com_cmm_bar2_reg[1]), + .I2(com_cmm_u_cmm_decoder_N_102_1), + .I3(com_cmmt_raddr[33]), + .O(com_cmm_u_cmm_decoder_N_11_2) + ); + defparam com_cmm_u_cmm_decoder_un10_bar12_64_hit_low_0_I_126.INIT = 16'h0903; + LUT4 com_cmm_u_cmm_decoder_un10_bar12_64_hit_low_0_I_126 ( + .I0(cfg_cfg_6102[158]), + .I1(com_cmm_bar2_reg[30]), + .I2(com_cmm_u_cmm_decoder_N_14_2), + .I3(com_cmmt_raddr[62]), + .O(com_cmm_u_cmm_decoder_N_19_1) + ); + defparam com_cmm_u_cmm_decoder_un10_bar12_64_hit_low_0_I_117.INIT = 16'h0903; + LUT4 com_cmm_u_cmm_decoder_un10_bar12_64_hit_low_0_I_117 ( + .I0(cfg_cfg_6102[138]), + .I1(com_cmm_bar2_reg[10]), + .I2(com_cmm_u_cmm_decoder_N_6_1), + .I3(com_cmmt_raddr[42]), + .O(com_cmm_u_cmm_decoder_N_27_1) + ); + defparam com_cmm_u_cmm_decoder_un10_bar12_64_hit_low_0_I_108.INIT = 4'h1; + LUT2 com_cmm_u_cmm_decoder_un10_bar12_64_hit_low_0_I_108 ( + .I0(com_cmm_u_cmm_decoder_N_47_1), + .I1(com_cmm_u_cmm_decoder_N_54_1), + .O(com_cmm_u_cmm_decoder_N_35_1) + ); + defparam com_cmm_u_cmm_decoder_un10_bar12_64_hit_low_0_I_99.INIT = 16'h0903; + LUT4 com_cmm_u_cmm_decoder_un10_bar12_64_hit_low_0_I_99 ( + .I0(cfg_cfg_6102[152]), + .I1(com_cmm_bar2_reg[24]), + .I2(com_cmm_u_cmm_decoder_N_94_1), + .I3(com_cmmt_raddr[56]), + .O(com_cmm_u_cmm_decoder_N_43_1) + ); + defparam com_cmm_u_cmm_decoder_un10_bar12_64_hit_low_0_I_90.INIT = 16'h0903; + LUT4 com_cmm_u_cmm_decoder_un10_bar12_64_hit_low_0_I_90 ( + .I0(cfg_cfg_6102[150]), + .I1(com_cmm_bar2_reg[22]), + .I2(com_cmm_u_cmm_decoder_N_46_1), + .I3(com_cmmt_raddr[54]), + .O(com_cmm_u_cmm_decoder_N_51_1) + ); + defparam com_cmm_u_cmm_decoder_un10_bar12_64_hit_low_0_I_81.INIT = 16'h0903; + LUT4 com_cmm_u_cmm_decoder_un10_bar12_64_hit_low_0_I_81 ( + .I0(cfg_cfg_6102[146]), + .I1(com_cmm_bar2_reg[18]), + .I2(com_cmm_u_cmm_decoder_N_38_1), + .I3(com_cmmt_raddr[50]), + .O(com_cmm_u_cmm_decoder_N_59_1) + ); + defparam com_cmm_u_cmm_decoder_un10_bar12_64_hit_low_0_I_72.INIT = 4'h1; + LUT2 com_cmm_u_cmm_decoder_un10_bar12_64_hit_low_0_I_72 ( + .I0(com_cmm_u_cmm_decoder_N_15_1), + .I1(com_cmm_u_cmm_decoder_N_22_1), + .O(com_cmm_u_cmm_decoder_N_67_1) + ); + defparam com_cmm_u_cmm_decoder_un10_bar12_64_hit_low_0_I_63.INIT = 4'h1; + LUT2 com_cmm_u_cmm_decoder_un10_bar12_64_hit_low_0_I_63 ( + .I0(com_cmm_u_cmm_decoder_N_39_1), + .I1(com_cmm_u_cmm_decoder_N_62_1), + .O(com_cmm_u_cmm_decoder_N_75_1) + ); + defparam com_cmm_u_cmm_decoder_un10_bar12_64_hit_low_0_I_54.INIT = 4'h1; + LUT2 com_cmm_u_cmm_decoder_un10_bar12_64_hit_low_0_I_54 ( + .I0(com_cmm_u_cmm_decoder_N_63_1), + .I1(com_cmm_u_cmm_decoder_N_78_0), + .O(com_cmm_u_cmm_decoder_N_83_1) + ); + defparam com_cmm_u_cmm_decoder_un10_bar12_64_hit_low_0_I_45.INIT = 4'h1; + LUT2 com_cmm_u_cmm_decoder_un10_bar12_64_hit_low_0_I_45 ( + .I0(com_cmm_u_cmm_decoder_N_23_1), + .I1(com_cmm_u_cmm_decoder_N_70_1), + .O(com_cmm_u_cmm_decoder_N_91_1) + ); + defparam com_cmm_u_cmm_decoder_un10_bar12_64_hit_low_0_I_27.INIT = 4'h1; + LUT2 com_cmm_u_cmm_decoder_un10_bar12_64_hit_low_0_I_27 ( + .I0(com_cmm_u_cmm_decoder_N_7_1), + .I1(com_cmm_u_cmm_decoder_N_30_1), + .O(com_cmm_u_cmm_decoder_N_107_1) + ); + defparam com_cmm_u_cmm_decoder_un10_bar12_64_hit_low_0_I_18.INIT = 16'h0903; + LUT4 com_cmm_u_cmm_decoder_un10_bar12_64_hit_low_0_I_18 ( + .I0(cfg_cfg_6102[133]), + .I1(com_cmm_bar2_reg[5]), + .I2(com_cmm_u_cmm_decoder_N_31_1), + .I3(com_cmmt_raddr[37]), + .O(com_cmm_u_cmm_decoder_N_115_1) + ); + defparam com_cmm_u_cmm_decoder_un10_bar12_64_hit_low_0_I_9.INIT = 16'h0903; + LUT4 com_cmm_u_cmm_decoder_un10_bar12_64_hit_low_0_I_9 ( + .I0(cfg_cfg_6102[131]), + .I1(com_cmm_bar2_reg[3]), + .I2(com_cmm_u_cmm_decoder_N_111_1), + .I3(com_cmmt_raddr[35]), + .O(com_cmm_u_cmm_decoder_N_123_1) + ); + defparam com_cmm_u_cmm_decoder_un10_bar23_64_hit_low_0_I_144.INIT = 16'h0903; + LUT4 com_cmm_u_cmm_decoder_un10_bar23_64_hit_low_0_I_144 ( + .I0(cfg_cfg_6102[172]), + .I1(com_cmm_bar3_reg[12]), + .I2(com_cmm_u_cmm_decoder_N_86), + .I3(com_cmmt_raddr[44]), + .O(com_cmm_u_cmm_decoder_N_3_0) + ); + defparam com_cmm_u_cmm_decoder_un10_bar23_64_hit_low_0_I_135.INIT = 16'h0903; + LUT4 com_cmm_u_cmm_decoder_un10_bar23_64_hit_low_0_I_135 ( + .I0(cfg_cfg_6102[161]), + .I1(com_cmm_bar3_reg[1]), + .I2(com_cmm_u_cmm_decoder_N_102_0), + .I3(com_cmmt_raddr[33]), + .O(com_cmm_u_cmm_decoder_N_11_1) + ); + defparam com_cmm_u_cmm_decoder_un10_bar23_64_hit_low_0_I_126.INIT = 16'h0903; + LUT4 com_cmm_u_cmm_decoder_un10_bar23_64_hit_low_0_I_126 ( + .I0(cfg_cfg_6102[190]), + .I1(com_cmm_bar3_reg[30]), + .I2(com_cmm_u_cmm_decoder_N_14_1), + .I3(com_cmmt_raddr[62]), + .O(com_cmm_u_cmm_decoder_N_19_0) + ); + defparam com_cmm_u_cmm_decoder_un10_bar23_64_hit_low_0_I_117.INIT = 16'h0903; + LUT4 com_cmm_u_cmm_decoder_un10_bar23_64_hit_low_0_I_117 ( + .I0(cfg_cfg_6102[170]), + .I1(com_cmm_bar3_reg[10]), + .I2(com_cmm_u_cmm_decoder_N_6_0), + .I3(com_cmmt_raddr[42]), + .O(com_cmm_u_cmm_decoder_N_27_0) + ); + defparam com_cmm_u_cmm_decoder_un10_bar23_64_hit_low_0_I_108.INIT = 4'h1; + LUT2 com_cmm_u_cmm_decoder_un10_bar23_64_hit_low_0_I_108 ( + .I0(com_cmm_u_cmm_decoder_N_47_0), + .I1(com_cmm_u_cmm_decoder_N_54_0), + .O(com_cmm_u_cmm_decoder_N_35_0) + ); + defparam com_cmm_u_cmm_decoder_un10_bar23_64_hit_low_0_I_99.INIT = 16'h0903; + LUT4 com_cmm_u_cmm_decoder_un10_bar23_64_hit_low_0_I_99 ( + .I0(cfg_cfg_6102[184]), + .I1(com_cmm_bar3_reg[24]), + .I2(com_cmm_u_cmm_decoder_N_94_0), + .I3(com_cmmt_raddr[56]), + .O(com_cmm_u_cmm_decoder_N_43_0) + ); + defparam com_cmm_u_cmm_decoder_un10_bar23_64_hit_low_0_I_90.INIT = 16'h0903; + LUT4 com_cmm_u_cmm_decoder_un10_bar23_64_hit_low_0_I_90 ( + .I0(cfg_cfg_6102[182]), + .I1(com_cmm_bar3_reg[22]), + .I2(com_cmm_u_cmm_decoder_N_46_0), + .I3(com_cmmt_raddr[54]), + .O(com_cmm_u_cmm_decoder_N_51_0) + ); + defparam com_cmm_u_cmm_decoder_un10_bar23_64_hit_low_0_I_81.INIT = 16'h0903; + LUT4 com_cmm_u_cmm_decoder_un10_bar23_64_hit_low_0_I_81 ( + .I0(cfg_cfg_6102[178]), + .I1(com_cmm_bar3_reg[18]), + .I2(com_cmm_u_cmm_decoder_N_38_0), + .I3(com_cmmt_raddr[50]), + .O(com_cmm_u_cmm_decoder_N_59_0) + ); + defparam com_cmm_u_cmm_decoder_un10_bar23_64_hit_low_0_I_72.INIT = 4'h1; + LUT2 com_cmm_u_cmm_decoder_un10_bar23_64_hit_low_0_I_72 ( + .I0(com_cmm_u_cmm_decoder_N_15_0), + .I1(com_cmm_u_cmm_decoder_N_22_0), + .O(com_cmm_u_cmm_decoder_N_67_0) + ); + defparam com_cmm_u_cmm_decoder_un10_bar23_64_hit_low_0_I_63.INIT = 4'h1; + LUT2 com_cmm_u_cmm_decoder_un10_bar23_64_hit_low_0_I_63 ( + .I0(com_cmm_u_cmm_decoder_N_39_0), + .I1(com_cmm_u_cmm_decoder_N_62_0), + .O(com_cmm_u_cmm_decoder_N_75_0) + ); + defparam com_cmm_u_cmm_decoder_un10_bar23_64_hit_low_0_I_54.INIT = 4'h1; + LUT2 com_cmm_u_cmm_decoder_un10_bar23_64_hit_low_0_I_54 ( + .I0(com_cmm_u_cmm_decoder_N_63_0), + .I1(com_cmm_u_cmm_decoder_N_78), + .O(com_cmm_u_cmm_decoder_N_83_0) + ); + defparam com_cmm_u_cmm_decoder_un10_bar23_64_hit_low_0_I_45.INIT = 4'h1; + LUT2 com_cmm_u_cmm_decoder_un10_bar23_64_hit_low_0_I_45 ( + .I0(com_cmm_u_cmm_decoder_N_23_0), + .I1(com_cmm_u_cmm_decoder_N_70_0), + .O(com_cmm_u_cmm_decoder_N_91_0) + ); + defparam com_cmm_u_cmm_decoder_un10_bar23_64_hit_low_0_I_27.INIT = 4'h1; + LUT2 com_cmm_u_cmm_decoder_un10_bar23_64_hit_low_0_I_27 ( + .I0(com_cmm_u_cmm_decoder_N_7_0), + .I1(com_cmm_u_cmm_decoder_N_30_0), + .O(com_cmm_u_cmm_decoder_N_107_0) + ); + defparam com_cmm_u_cmm_decoder_un10_bar23_64_hit_low_0_I_18.INIT = 16'h0903; + LUT4 com_cmm_u_cmm_decoder_un10_bar23_64_hit_low_0_I_18 ( + .I0(cfg_cfg_6102[165]), + .I1(com_cmm_bar3_reg[5]), + .I2(com_cmm_u_cmm_decoder_N_31_0), + .I3(com_cmmt_raddr[37]), + .O(com_cmm_u_cmm_decoder_N_115_0) + ); + defparam com_cmm_u_cmm_decoder_un10_bar23_64_hit_low_0_I_9.INIT = 16'h0903; + LUT4 com_cmm_u_cmm_decoder_un10_bar23_64_hit_low_0_I_9 ( + .I0(cfg_cfg_6102[163]), + .I1(com_cmm_bar3_reg[3]), + .I2(com_cmm_u_cmm_decoder_N_111_0), + .I3(com_cmmt_raddr[35]), + .O(com_cmm_u_cmm_decoder_N_123_0) + ); + defparam com_cmm_u_cmm_decoder_un10_bar34_64_hit_low_0_I_144.INIT = 16'h0903; + LUT4 com_cmm_u_cmm_decoder_un10_bar34_64_hit_low_0_I_144 ( + .I0(cfg_cfg_6102[203]), + .I1(com_cmm_bar4_reg[11]), + .I2(com_cmm_u_cmm_decoder_N_79), + .I3(com_cmmt_raddr[43]), + .O(com_cmm_u_cmm_decoder_N_3) + ); + defparam com_cmm_u_cmm_decoder_un10_bar34_64_hit_low_0_I_135.INIT = 16'h0903; + LUT4 com_cmm_u_cmm_decoder_un10_bar34_64_hit_low_0_I_135 ( + .I0(cfg_cfg_6102[193]), + .I1(com_cmm_bar4_reg[1]), + .I2(com_cmm_u_cmm_decoder_N_102), + .I3(com_cmmt_raddr[33]), + .O(com_cmm_u_cmm_decoder_N_11_0) + ); + defparam com_cmm_u_cmm_decoder_un10_bar34_64_hit_low_0_I_126.INIT = 16'h0903; + LUT4 com_cmm_u_cmm_decoder_un10_bar34_64_hit_low_0_I_126 ( + .I0(cfg_cfg_6102[222]), + .I1(com_cmm_bar4_reg[30]), + .I2(com_cmm_u_cmm_decoder_N_14_0), + .I3(com_cmmt_raddr[62]), + .O(com_cmm_u_cmm_decoder_N_19) + ); + defparam com_cmm_u_cmm_decoder_un10_bar34_64_hit_low_0_I_117.INIT = 4'h1; + LUT2 com_cmm_u_cmm_decoder_un10_bar34_64_hit_low_0_I_117 ( + .I0(com_cmm_u_cmm_decoder_N_6), + .I1(com_cmm_u_cmm_decoder_N_87), + .O(com_cmm_u_cmm_decoder_N_27) + ); + defparam com_cmm_u_cmm_decoder_un10_bar34_64_hit_low_0_I_108.INIT = 4'h1; + LUT2 com_cmm_u_cmm_decoder_un10_bar34_64_hit_low_0_I_108 ( + .I0(com_cmm_u_cmm_decoder_N_47), + .I1(com_cmm_u_cmm_decoder_N_54), + .O(com_cmm_u_cmm_decoder_N_35) + ); + defparam com_cmm_u_cmm_decoder_un10_bar34_64_hit_low_0_I_99.INIT = 16'h0903; + LUT4 com_cmm_u_cmm_decoder_un10_bar34_64_hit_low_0_I_99 ( + .I0(cfg_cfg_6102[216]), + .I1(com_cmm_bar4_reg[24]), + .I2(com_cmm_u_cmm_decoder_N_94), + .I3(com_cmmt_raddr[56]), + .O(com_cmm_u_cmm_decoder_N_43) + ); + defparam com_cmm_u_cmm_decoder_un10_bar34_64_hit_low_0_I_90.INIT = 16'h0903; + LUT4 com_cmm_u_cmm_decoder_un10_bar34_64_hit_low_0_I_90 ( + .I0(cfg_cfg_6102[214]), + .I1(com_cmm_bar4_reg[22]), + .I2(com_cmm_u_cmm_decoder_N_46), + .I3(com_cmmt_raddr[54]), + .O(com_cmm_u_cmm_decoder_N_51) + ); + defparam com_cmm_u_cmm_decoder_un10_bar34_64_hit_low_0_I_81.INIT = 16'h0903; + LUT4 com_cmm_u_cmm_decoder_un10_bar34_64_hit_low_0_I_81 ( + .I0(cfg_cfg_6102[210]), + .I1(com_cmm_bar4_reg[18]), + .I2(com_cmm_u_cmm_decoder_N_38), + .I3(com_cmmt_raddr[50]), + .O(com_cmm_u_cmm_decoder_N_59) + ); + defparam com_cmm_u_cmm_decoder_un10_bar34_64_hit_low_0_I_72.INIT = 4'h1; + LUT2 com_cmm_u_cmm_decoder_un10_bar34_64_hit_low_0_I_72 ( + .I0(com_cmm_u_cmm_decoder_N_15), + .I1(com_cmm_u_cmm_decoder_N_22), + .O(com_cmm_u_cmm_decoder_N_67) + ); + defparam com_cmm_u_cmm_decoder_un10_bar34_64_hit_low_0_I_63.INIT = 4'h1; + LUT2 com_cmm_u_cmm_decoder_un10_bar34_64_hit_low_0_I_63 ( + .I0(com_cmm_u_cmm_decoder_N_39), + .I1(com_cmm_u_cmm_decoder_N_62), + .O(com_cmm_u_cmm_decoder_N_75) + ); + defparam com_cmm_u_cmm_decoder_un10_bar34_64_hit_low_0_I_54.INIT = 16'h0903; + LUT4 com_cmm_u_cmm_decoder_un10_bar34_64_hit_low_0_I_54 ( + .I0(cfg_cfg_6102[205]), + .I1(com_cmm_bar4_reg[13]), + .I2(com_cmm_u_cmm_decoder_N_63), + .I3(com_cmmt_raddr[45]), + .O(com_cmm_u_cmm_decoder_N_83) + ); + defparam com_cmm_u_cmm_decoder_un10_bar34_64_hit_low_0_I_45.INIT = 4'h1; + LUT2 com_cmm_u_cmm_decoder_un10_bar34_64_hit_low_0_I_45 ( + .I0(com_cmm_u_cmm_decoder_N_23), + .I1(com_cmm_u_cmm_decoder_N_70), + .O(com_cmm_u_cmm_decoder_N_91) + ); + defparam com_cmm_u_cmm_decoder_un10_bar34_64_hit_low_0_I_27.INIT = 4'h1; + LUT2 com_cmm_u_cmm_decoder_un10_bar34_64_hit_low_0_I_27 ( + .I0(com_cmm_u_cmm_decoder_N_7), + .I1(com_cmm_u_cmm_decoder_N_30), + .O(com_cmm_u_cmm_decoder_N_107) + ); + defparam com_cmm_u_cmm_decoder_un10_bar34_64_hit_low_0_I_18.INIT = 4'h1; + LUT2 com_cmm_u_cmm_decoder_un10_bar34_64_hit_low_0_I_18 ( + .I0(com_cmm_u_cmm_decoder_N_31), + .I1(com_cmm_u_cmm_decoder_N_110), + .O(com_cmm_u_cmm_decoder_N_115) + ); + defparam com_cmm_u_cmm_decoder_un10_bar34_64_hit_low_0_I_9.INIT = 16'h0903; + LUT4 com_cmm_u_cmm_decoder_un10_bar34_64_hit_low_0_I_9 ( + .I0(cfg_cfg_6102[195]), + .I1(com_cmm_bar4_reg[3]), + .I2(com_cmm_u_cmm_decoder_N_111), + .I3(com_cmmt_raddr[35]), + .O(com_cmm_u_cmm_decoder_N_123) + ); + defparam com_cmm_u_cmm_decoder_un10_bar45_64_hit_low_0_I_135.INIT = 16'h0903; + LUT4 com_cmm_u_cmm_decoder_un10_bar45_64_hit_low_0_I_135 ( + .I0(cfg_cfg_6102[225]), + .I1(com_cmm_bar5_reg[1]), + .I2(com_cmm_u_cmm_decoder_N_14), + .I3(com_cmmt_raddr[33]), + .O(com_cmm_u_cmm_decoder_N_11) + ); + VCC com_cmm_u_cmm_cfgspace_VCC ( + .P(com_cmm_u_cmm_cfgspace_VCC_5805) + ); + FDR com_cmm_u_cmm_cfgspace_low_addr_01_q_0_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_cfgspace_low_addr_01[0]), + .Q(com_cmm_u_cmm_cfgspace_low_addr_01_q[0]), + .R(com_cmm_u_cmm_cfgspace_N_10576_i_5554) + ); + FDR com_cmm_u_cmm_cfgspace_low_addr_01_q_1_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_cfgspace_low_addr_01[1]), + .Q(com_cmm_u_cmm_cfgspace_low_addr_01_q[1]), + .R(com_cmm_u_cmm_cfgspace_N_10576_i_5554) + ); + FDR com_cmm_u_cmm_cfgspace_low_addr_01_q_2_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_cfgspace_low_addr_01[2]), + .Q(com_cmm_u_cmm_cfgspace_low_addr_01_q[2]), + .R(com_cmm_u_cmm_cfgspace_N_10576_i_5554) + ); + FDR com_cmm_u_cmm_cfgspace_low_addr_01_q_3_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_cfgspace_low_addr_01[3]), + .Q(com_cmm_u_cmm_cfgspace_low_addr_01_q[3]), + .R(com_cmm_u_cmm_cfgspace_N_10576_i_5554) + ); + FDR com_cmm_u_cmm_cfgspace_low_addr_01_q_4_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_cfgspace_low_addr_01[4]), + .Q(com_cmm_u_cmm_cfgspace_low_addr_01_q[4]), + .R(com_cmm_u_cmm_cfgspace_N_10576_i_5554) + ); + FDR com_cmm_u_cmm_cfgspace_low_addr_01_q_5_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_cfgspace_low_addr_01[5]), + .Q(com_cmm_u_cmm_cfgspace_low_addr_01_q[5]), + .R(com_cmm_u_cmm_cfgspace_N_10576_i_5554) + ); + FDR com_cmm_u_cmm_cfgspace_low_addr_01_q_6_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_cfgspace_low_addr_01[6]), + .Q(com_cmm_u_cmm_cfgspace_low_addr_01_q[6]), + .R(com_cmm_u_cmm_cfgspace_N_10576_i_5554) + ); + FDR com_cmm_u_cmm_cfgspace_low_addr_01_q_7_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_cfgspace_low_addr_01[7]), + .Q(com_cmm_u_cmm_cfgspace_low_addr_01_q[7]), + .R(com_cmm_u_cmm_cfgspace_N_10576_i_5554) + ); + FDR com_cmm_u_cmm_cfgspace_low_addr_01_q_8_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_cfgspace_low_addr_01[8]), + .Q(com_cmm_u_cmm_cfgspace_low_addr_01_q[8]), + .R(com_cmm_u_cmm_cfgspace_N_10576_i_5554) + ); + FDR com_cmm_u_cmm_cfgspace_low_addr_01_q_9_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_cfgspace_low_addr_01[9]), + .Q(com_cmm_u_cmm_cfgspace_low_addr_01_q[9]), + .R(com_cmm_u_cmm_cfgspace_N_10576_i_5554) + ); + FDR com_cmm_u_cmm_cfgspace_low_addr_01_q_10_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_cfgspace_low_addr_01[10]), + .Q(com_cmm_u_cmm_cfgspace_low_addr_01_q[10]), + .R(com_cmm_u_cmm_cfgspace_N_10576_i_5554) + ); + FDR com_cmm_u_cmm_cfgspace_low_addr_01_q_11_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_cfgspace_low_addr_01[11]), + .Q(com_cmm_u_cmm_cfgspace_low_addr_01_q[11]), + .R(com_cmm_u_cmm_cfgspace_N_10576_i_5554) + ); + FDR com_cmm_u_cmm_cfgspace_low_addr_01_q_12_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_cfgspace_low_addr_01[12]), + .Q(com_cmm_u_cmm_cfgspace_low_addr_01_q[12]), + .R(com_cmm_u_cmm_cfgspace_N_10576_i_5554) + ); + FDR com_cmm_u_cmm_cfgspace_low_addr_01_q_13_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_cfgspace_low_addr_01[13]), + .Q(com_cmm_u_cmm_cfgspace_low_addr_01_q[13]), + .R(com_cmm_u_cmm_cfgspace_N_10576_i_5554) + ); + FDR com_cmm_u_cmm_cfgspace_low_addr_01_q_14_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_cfgspace_low_addr_01[14]), + .Q(com_cmm_u_cmm_cfgspace_low_addr_01_q[14]), + .R(com_cmm_u_cmm_cfgspace_N_10576_i_5554) + ); + FDR com_cmm_u_cmm_cfgspace_low_addr_01_q_15_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_cfgspace_low_addr_01[15]), + .Q(com_cmm_u_cmm_cfgspace_low_addr_01_q[15]), + .R(com_cmm_u_cmm_cfgspace_N_10576_i_5554) + ); + FDR com_cmm_u_cmm_cfgspace_low_addr_01_q_16_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_cfgspace_low_addr_01[16]), + .Q(com_cmm_u_cmm_cfgspace_low_addr_01_q[16]), + .R(com_cmm_u_cmm_cfgspace_N_10576_i_5554) + ); + FDR com_cmm_u_cmm_cfgspace_low_addr_01_q_17_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_cfgspace_low_addr_01[17]), + .Q(com_cmm_u_cmm_cfgspace_low_addr_01_q[17]), + .R(com_cmm_u_cmm_cfgspace_N_10576_i_5554) + ); + FDR com_cmm_u_cmm_cfgspace_low_addr_01_q_18_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_cfgspace_low_addr_01[18]), + .Q(com_cmm_u_cmm_cfgspace_low_addr_01_q[18]), + .R(com_cmm_u_cmm_cfgspace_N_10576_i_5554) + ); + FDR com_cmm_u_cmm_cfgspace_low_addr_01_q_19_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_cfgspace_low_addr_01[19]), + .Q(com_cmm_u_cmm_cfgspace_low_addr_01_q[19]), + .R(com_cmm_u_cmm_cfgspace_N_10576_i_5554) + ); + FDR com_cmm_u_cmm_cfgspace_low_addr_01_q_20_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_cfgspace_low_addr_01[20]), + .Q(com_cmm_u_cmm_cfgspace_low_addr_01_q[20]), + .R(com_cmm_u_cmm_cfgspace_N_10576_i_5554) + ); + FDR com_cmm_u_cmm_cfgspace_low_addr_01_q_21_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_cfgspace_low_addr_01[21]), + .Q(com_cmm_u_cmm_cfgspace_low_addr_01_q[21]), + .R(com_cmm_u_cmm_cfgspace_N_10576_i_5554) + ); + FDR com_cmm_u_cmm_cfgspace_low_addr_01_q_22_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_cfgspace_low_addr_01[22]), + .Q(com_cmm_u_cmm_cfgspace_low_addr_01_q[22]), + .R(com_cmm_u_cmm_cfgspace_N_10576_i_5554) + ); + FDR com_cmm_u_cmm_cfgspace_low_addr_01_q_23_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_cfgspace_low_addr_01[23]), + .Q(com_cmm_u_cmm_cfgspace_low_addr_01_q[23]), + .R(com_cmm_u_cmm_cfgspace_N_10576_i_5554) + ); + FDR com_cmm_u_cmm_cfgspace_low_addr_01_q_24_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_cfgspace_low_addr_01[24]), + .Q(com_cmm_u_cmm_cfgspace_low_addr_01_q[24]), + .R(com_cmm_u_cmm_cfgspace_N_10576_i_5554) + ); + FDR com_cmm_u_cmm_cfgspace_low_addr_01_q_25_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_cfgspace_low_addr_01[25]), + .Q(com_cmm_u_cmm_cfgspace_low_addr_01_q[25]), + .R(com_cmm_u_cmm_cfgspace_N_10576_i_5554) + ); + FDR com_cmm_u_cmm_cfgspace_low_addr_01_q_26_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_cfgspace_low_addr_01[26]), + .Q(com_cmm_u_cmm_cfgspace_low_addr_01_q[26]), + .R(com_cmm_u_cmm_cfgspace_N_10576_i_5554) + ); + FDR com_cmm_u_cmm_cfgspace_low_addr_01_q_27_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_cfgspace_low_addr_01[27]), + .Q(com_cmm_u_cmm_cfgspace_low_addr_01_q[27]), + .R(com_cmm_u_cmm_cfgspace_N_10576_i_5554) + ); + FDR com_cmm_u_cmm_cfgspace_low_addr_01_q_28_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_cfgspace_low_addr_01[28]), + .Q(com_cmm_u_cmm_cfgspace_low_addr_01_q[28]), + .R(com_cmm_u_cmm_cfgspace_N_10576_i_5554) + ); + FDR com_cmm_u_cmm_cfgspace_low_addr_01_q_29_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_cfgspace_low_addr_01[29]), + .Q(com_cmm_u_cmm_cfgspace_low_addr_01_q[29]), + .R(com_cmm_u_cmm_cfgspace_N_10576_i_5554) + ); + FDR com_cmm_u_cmm_cfgspace_low_addr_01_q_30_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_cfgspace_low_addr_01[30]), + .Q(com_cmm_u_cmm_cfgspace_low_addr_01_q[30]), + .R(com_cmm_u_cmm_cfgspace_N_10576_i_5554) + ); + FDR com_cmm_u_cmm_cfgspace_low_addr_01_q_31_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_cfgspace_low_addr_01[31]), + .Q(com_cmm_u_cmm_cfgspace_low_addr_01_q[31]), + .R(com_cmm_u_cmm_cfgspace_N_10576_i_5554) + ); + FDR com_cmm_u_cmm_cfgspace_sel_encodex_en ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_cfgspace_N_85958_i_5746), + .Q(com_cmm_u_cmm_cfgspace_sel_encodex_en_5555), + .R(com_cmm_rst_351) + ); + FDR com_cmm_u_cmm_cfgspace_low_addr_03_q_0_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_cfgspace_low_addr_03_q_4[0]), + .Q(com_cmm_u_cmm_cfgspace_low_addr_03_q[0]), + .R(com_cmm_u_cmm_cfgspace_N_10576_i_5554) + ); + FDR com_cmm_u_cmm_cfgspace_low_addr_03_q_1_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_cfgspace_low_addr_03_q_4[1]), + .Q(com_cmm_u_cmm_cfgspace_low_addr_03_q[1]), + .R(com_cmm_u_cmm_cfgspace_N_10576_i_5554) + ); + FDR com_cmm_u_cmm_cfgspace_low_addr_03_q_2_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_cfgspace_low_addr_03_q_4[2]), + .Q(com_cmm_u_cmm_cfgspace_low_addr_03_q[2]), + .R(com_cmm_u_cmm_cfgspace_N_10576_i_5554) + ); + FDR com_cmm_u_cmm_cfgspace_low_addr_03_q_3_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_cfgspace_low_addr_03_q_4[3]), + .Q(com_cmm_u_cmm_cfgspace_low_addr_03_q[3]), + .R(com_cmm_u_cmm_cfgspace_N_10576_i_5554) + ); + FDR com_cmm_u_cmm_cfgspace_low_addr_03_q_4_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_cfgspace_low_addr_03_q_4[4]), + .Q(com_cmm_u_cmm_cfgspace_low_addr_03_q[4]), + .R(com_cmm_u_cmm_cfgspace_N_10576_i_5554) + ); + FDR com_cmm_u_cmm_cfgspace_low_addr_03_q_5_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_cfgspace_low_addr_03_q_4[5]), + .Q(com_cmm_u_cmm_cfgspace_low_addr_03_q[5]), + .R(com_cmm_u_cmm_cfgspace_N_10576_i_5554) + ); + FDR com_cmm_u_cmm_cfgspace_low_addr_03_q_6_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_cfgspace_low_addr_03_q_4[6]), + .Q(com_cmm_u_cmm_cfgspace_low_addr_03_q[6]), + .R(com_cmm_u_cmm_cfgspace_N_10576_i_5554) + ); + FDR com_cmm_u_cmm_cfgspace_low_addr_03_q_7_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_cfgspace_low_addr_03_q_4[7]), + .Q(com_cmm_u_cmm_cfgspace_low_addr_03_q[7]), + .R(com_cmm_u_cmm_cfgspace_N_10576_i_5554) + ); + FDR com_cmm_u_cmm_cfgspace_low_addr_03_q_8_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_cfgspace_low_addr_03_q_4[8]), + .Q(com_cmm_u_cmm_cfgspace_low_addr_03_q[8]), + .R(com_cmm_u_cmm_cfgspace_N_10576_i_5554) + ); + FDR com_cmm_u_cmm_cfgspace_low_addr_03_q_9_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_cfgspace_low_addr_03_q_4[9]), + .Q(com_cmm_u_cmm_cfgspace_low_addr_03_q[9]), + .R(com_cmm_u_cmm_cfgspace_N_10576_i_5554) + ); + FDR com_cmm_u_cmm_cfgspace_low_addr_03_q_10_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_cfgspace_low_addr_03_q_4[10]), + .Q(com_cmm_u_cmm_cfgspace_low_addr_03_q[10]), + .R(com_cmm_u_cmm_cfgspace_N_10576_i_5554) + ); + FDR com_cmm_u_cmm_cfgspace_low_addr_03_q_11_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_cfgspace_low_addr_03_q_4[11]), + .Q(com_cmm_u_cmm_cfgspace_low_addr_03_q[11]), + .R(com_cmm_u_cmm_cfgspace_N_10576_i_5554) + ); + FDR com_cmm_u_cmm_cfgspace_low_addr_03_q_12_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_cfgspace_low_addr_03_q_4[12]), + .Q(com_cmm_u_cmm_cfgspace_low_addr_03_q[12]), + .R(com_cmm_u_cmm_cfgspace_N_10576_i_5554) + ); + FDR com_cmm_u_cmm_cfgspace_low_addr_03_q_13_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_cfgspace_low_addr_03_q_4[13]), + .Q(com_cmm_u_cmm_cfgspace_low_addr_03_q[13]), + .R(com_cmm_u_cmm_cfgspace_N_10576_i_5554) + ); + FDR com_cmm_u_cmm_cfgspace_low_addr_03_q_14_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_cfgspace_low_addr_03_q_4[14]), + .Q(com_cmm_u_cmm_cfgspace_low_addr_03_q[14]), + .R(com_cmm_u_cmm_cfgspace_N_10576_i_5554) + ); + FDR com_cmm_u_cmm_cfgspace_low_addr_03_q_15_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_cfgspace_low_addr_03_q_4[15]), + .Q(com_cmm_u_cmm_cfgspace_low_addr_03_q[15]), + .R(com_cmm_u_cmm_cfgspace_N_10576_i_5554) + ); + FDR com_cmm_u_cmm_cfgspace_low_addr_03_q_16_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_cfgspace_low_addr_03_q_4[16]), + .Q(com_cmm_u_cmm_cfgspace_low_addr_03_q[16]), + .R(com_cmm_u_cmm_cfgspace_N_10576_i_5554) + ); + FDR com_cmm_u_cmm_cfgspace_low_addr_03_q_17_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_cfgspace_low_addr_03_q_4[17]), + .Q(com_cmm_u_cmm_cfgspace_low_addr_03_q[17]), + .R(com_cmm_u_cmm_cfgspace_N_10576_i_5554) + ); + FDR com_cmm_u_cmm_cfgspace_low_addr_03_q_18_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_cfgspace_low_addr_03_q_4[18]), + .Q(com_cmm_u_cmm_cfgspace_low_addr_03_q[18]), + .R(com_cmm_u_cmm_cfgspace_N_10576_i_5554) + ); + FDR com_cmm_u_cmm_cfgspace_low_addr_03_q_19_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_cfgspace_low_addr_03_q_4[19]), + .Q(com_cmm_u_cmm_cfgspace_low_addr_03_q[19]), + .R(com_cmm_u_cmm_cfgspace_N_10576_i_5554) + ); + FDR com_cmm_u_cmm_cfgspace_low_addr_03_q_20_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_cfgspace_low_addr_03_q_4[20]), + .Q(com_cmm_u_cmm_cfgspace_low_addr_03_q[20]), + .R(com_cmm_u_cmm_cfgspace_N_10576_i_5554) + ); + FDR com_cmm_u_cmm_cfgspace_low_addr_03_q_21_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_cfgspace_low_addr_03_q_4[21]), + .Q(com_cmm_u_cmm_cfgspace_low_addr_03_q[21]), + .R(com_cmm_u_cmm_cfgspace_N_10576_i_5554) + ); + FDR com_cmm_u_cmm_cfgspace_low_addr_03_q_22_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_cfgspace_low_addr_03_q_4[22]), + .Q(com_cmm_u_cmm_cfgspace_low_addr_03_q[22]), + .R(com_cmm_u_cmm_cfgspace_N_10576_i_5554) + ); + FDR com_cmm_u_cmm_cfgspace_low_addr_03_q_23_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_cfgspace_low_addr_03_q_4[23]), + .Q(com_cmm_u_cmm_cfgspace_low_addr_03_q[23]), + .R(com_cmm_u_cmm_cfgspace_N_10576_i_5554) + ); + FDR com_cmm_u_cmm_cfgspace_low_addr_03_q_24_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_cfgspace_low_addr_03_q_4[24]), + .Q(com_cmm_u_cmm_cfgspace_low_addr_03_q[24]), + .R(com_cmm_u_cmm_cfgspace_N_10576_i_5554) + ); + FDR com_cmm_u_cmm_cfgspace_low_addr_03_q_25_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_cfgspace_low_addr_03_q_4[25]), + .Q(com_cmm_u_cmm_cfgspace_low_addr_03_q[25]), + .R(com_cmm_u_cmm_cfgspace_N_10576_i_5554) + ); + FDR com_cmm_u_cmm_cfgspace_low_addr_03_q_26_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_cfgspace_low_addr_03_q_4[26]), + .Q(com_cmm_u_cmm_cfgspace_low_addr_03_q[26]), + .R(com_cmm_u_cmm_cfgspace_N_10576_i_5554) + ); + FDR com_cmm_u_cmm_cfgspace_low_addr_03_q_27_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_cfgspace_low_addr_03_q_4[27]), + .Q(com_cmm_u_cmm_cfgspace_low_addr_03_q[27]), + .R(com_cmm_u_cmm_cfgspace_N_10576_i_5554) + ); + FDR com_cmm_u_cmm_cfgspace_low_addr_03_q_28_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_cfgspace_low_addr_03_q_4[28]), + .Q(com_cmm_u_cmm_cfgspace_low_addr_03_q[28]), + .R(com_cmm_u_cmm_cfgspace_N_10576_i_5554) + ); + FDR com_cmm_u_cmm_cfgspace_low_addr_03_q_29_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_cfgspace_low_addr_03_q_4[29]), + .Q(com_cmm_u_cmm_cfgspace_low_addr_03_q[29]), + .R(com_cmm_u_cmm_cfgspace_N_10576_i_5554) + ); + FDR com_cmm_u_cmm_cfgspace_low_addr_03_q_30_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_cfgspace_low_addr_03_q_4[30]), + .Q(com_cmm_u_cmm_cfgspace_low_addr_03_q[30]), + .R(com_cmm_u_cmm_cfgspace_N_10576_i_5554) + ); + FDR com_cmm_u_cmm_cfgspace_low_addr_03_q_31_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_cfgspace_low_addr_03_q_4[31]), + .Q(com_cmm_u_cmm_cfgspace_low_addr_03_q[31]), + .R(com_cmm_u_cmm_cfgspace_N_10576_i_5554) + ); + FDR com_cmm_u_cmm_cfgspace_low_addr_02_q_0_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_cfgspace_low_addr_02[0]), + .Q(com_cmm_u_cmm_cfgspace_low_addr_02_q[0]), + .R(com_cmm_u_cmm_cfgspace_N_10576_i_5554) + ); + FDR com_cmm_u_cmm_cfgspace_low_addr_02_q_1_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_cfgspace_low_addr_02[1]), + .Q(com_cmm_u_cmm_cfgspace_low_addr_02_q[1]), + .R(com_cmm_u_cmm_cfgspace_N_10576_i_5554) + ); + FDR com_cmm_u_cmm_cfgspace_low_addr_02_q_2_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_cfgspace_low_addr_02[2]), + .Q(com_cmm_u_cmm_cfgspace_low_addr_02_q[2]), + .R(com_cmm_u_cmm_cfgspace_N_10576_i_5554) + ); + FDR com_cmm_u_cmm_cfgspace_low_addr_02_q_3_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_cfgspace_low_addr_02[3]), + .Q(com_cmm_u_cmm_cfgspace_low_addr_02_q[3]), + .R(com_cmm_u_cmm_cfgspace_N_10576_i_5554) + ); + FDR com_cmm_u_cmm_cfgspace_low_addr_02_q_4_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_cfgspace_low_addr_02[4]), + .Q(com_cmm_u_cmm_cfgspace_low_addr_02_q[4]), + .R(com_cmm_u_cmm_cfgspace_N_10576_i_5554) + ); + FDR com_cmm_u_cmm_cfgspace_low_addr_02_q_5_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_cfgspace_low_addr_02[5]), + .Q(com_cmm_u_cmm_cfgspace_low_addr_02_q[5]), + .R(com_cmm_u_cmm_cfgspace_N_10576_i_5554) + ); + FDR com_cmm_u_cmm_cfgspace_low_addr_02_q_6_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_cfgspace_low_addr_02[6]), + .Q(com_cmm_u_cmm_cfgspace_low_addr_02_q[6]), + .R(com_cmm_u_cmm_cfgspace_N_10576_i_5554) + ); + FDR com_cmm_u_cmm_cfgspace_low_addr_02_q_7_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_cfgspace_low_addr_02[7]), + .Q(com_cmm_u_cmm_cfgspace_low_addr_02_q[7]), + .R(com_cmm_u_cmm_cfgspace_N_10576_i_5554) + ); + FDR com_cmm_u_cmm_cfgspace_low_addr_02_q_8_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_cfgspace_low_addr_02[8]), + .Q(com_cmm_u_cmm_cfgspace_low_addr_02_q[8]), + .R(com_cmm_u_cmm_cfgspace_N_10576_i_5554) + ); + FDR com_cmm_u_cmm_cfgspace_low_addr_02_q_9_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_cfgspace_low_addr_02[9]), + .Q(com_cmm_u_cmm_cfgspace_low_addr_02_q[9]), + .R(com_cmm_u_cmm_cfgspace_N_10576_i_5554) + ); + FDR com_cmm_u_cmm_cfgspace_low_addr_02_q_10_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_cfgspace_low_addr_02[10]), + .Q(com_cmm_u_cmm_cfgspace_low_addr_02_q[10]), + .R(com_cmm_u_cmm_cfgspace_N_10576_i_5554) + ); + FDR com_cmm_u_cmm_cfgspace_low_addr_02_q_11_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_cfgspace_low_addr_02[11]), + .Q(com_cmm_u_cmm_cfgspace_low_addr_02_q[11]), + .R(com_cmm_u_cmm_cfgspace_N_10576_i_5554) + ); + FDR com_cmm_u_cmm_cfgspace_low_addr_02_q_12_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_cfgspace_low_addr_02[12]), + .Q(com_cmm_u_cmm_cfgspace_low_addr_02_q[12]), + .R(com_cmm_u_cmm_cfgspace_N_10576_i_5554) + ); + FDR com_cmm_u_cmm_cfgspace_low_addr_02_q_13_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_cfgspace_low_addr_02[13]), + .Q(com_cmm_u_cmm_cfgspace_low_addr_02_q[13]), + .R(com_cmm_u_cmm_cfgspace_N_10576_i_5554) + ); + FDR com_cmm_u_cmm_cfgspace_low_addr_02_q_14_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_cfgspace_low_addr_02[14]), + .Q(com_cmm_u_cmm_cfgspace_low_addr_02_q[14]), + .R(com_cmm_u_cmm_cfgspace_N_10576_i_5554) + ); + FDR com_cmm_u_cmm_cfgspace_low_addr_02_q_15_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_cfgspace_low_addr_02[15]), + .Q(com_cmm_u_cmm_cfgspace_low_addr_02_q[15]), + .R(com_cmm_u_cmm_cfgspace_N_10576_i_5554) + ); + FDR com_cmm_u_cmm_cfgspace_low_addr_02_q_16_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_cfgspace_low_addr_02[16]), + .Q(com_cmm_u_cmm_cfgspace_low_addr_02_q[16]), + .R(com_cmm_u_cmm_cfgspace_N_10576_i_5554) + ); + FDR com_cmm_u_cmm_cfgspace_low_addr_02_q_17_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_cfgspace_low_addr_02[17]), + .Q(com_cmm_u_cmm_cfgspace_low_addr_02_q[17]), + .R(com_cmm_u_cmm_cfgspace_N_10576_i_5554) + ); + FDR com_cmm_u_cmm_cfgspace_low_addr_02_q_18_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_cfgspace_low_addr_02[18]), + .Q(com_cmm_u_cmm_cfgspace_low_addr_02_q[18]), + .R(com_cmm_u_cmm_cfgspace_N_10576_i_5554) + ); + FDR com_cmm_u_cmm_cfgspace_low_addr_02_q_19_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_cfgspace_low_addr_02[19]), + .Q(com_cmm_u_cmm_cfgspace_low_addr_02_q[19]), + .R(com_cmm_u_cmm_cfgspace_N_10576_i_5554) + ); + FDR com_cmm_u_cmm_cfgspace_low_addr_02_q_20_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_cfgspace_low_addr_02[20]), + .Q(com_cmm_u_cmm_cfgspace_low_addr_02_q[20]), + .R(com_cmm_u_cmm_cfgspace_N_10576_i_5554) + ); + FDR com_cmm_u_cmm_cfgspace_low_addr_02_q_21_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_cfgspace_low_addr_02[21]), + .Q(com_cmm_u_cmm_cfgspace_low_addr_02_q[21]), + .R(com_cmm_u_cmm_cfgspace_N_10576_i_5554) + ); + FDR com_cmm_u_cmm_cfgspace_low_addr_02_q_22_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_cfgspace_low_addr_02[22]), + .Q(com_cmm_u_cmm_cfgspace_low_addr_02_q[22]), + .R(com_cmm_u_cmm_cfgspace_N_10576_i_5554) + ); + FDR com_cmm_u_cmm_cfgspace_low_addr_02_q_23_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_cfgspace_low_addr_02[23]), + .Q(com_cmm_u_cmm_cfgspace_low_addr_02_q[23]), + .R(com_cmm_u_cmm_cfgspace_N_10576_i_5554) + ); + FDR com_cmm_u_cmm_cfgspace_low_addr_02_q_24_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_cfgspace_low_addr_02[24]), + .Q(com_cmm_u_cmm_cfgspace_low_addr_02_q[24]), + .R(com_cmm_u_cmm_cfgspace_N_10576_i_5554) + ); + FDR com_cmm_u_cmm_cfgspace_low_addr_02_q_25_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_cfgspace_low_addr_02[25]), + .Q(com_cmm_u_cmm_cfgspace_low_addr_02_q[25]), + .R(com_cmm_u_cmm_cfgspace_N_10576_i_5554) + ); + FDR com_cmm_u_cmm_cfgspace_low_addr_02_q_26_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_cfgspace_low_addr_02[26]), + .Q(com_cmm_u_cmm_cfgspace_low_addr_02_q[26]), + .R(com_cmm_u_cmm_cfgspace_N_10576_i_5554) + ); + FDR com_cmm_u_cmm_cfgspace_low_addr_02_q_27_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_cfgspace_low_addr_02[27]), + .Q(com_cmm_u_cmm_cfgspace_low_addr_02_q[27]), + .R(com_cmm_u_cmm_cfgspace_N_10576_i_5554) + ); + FDR com_cmm_u_cmm_cfgspace_low_addr_02_q_28_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_cfgspace_low_addr_02[28]), + .Q(com_cmm_u_cmm_cfgspace_low_addr_02_q[28]), + .R(com_cmm_u_cmm_cfgspace_N_10576_i_5554) + ); + FDR com_cmm_u_cmm_cfgspace_low_addr_02_q_29_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_cfgspace_low_addr_02[29]), + .Q(com_cmm_u_cmm_cfgspace_low_addr_02_q[29]), + .R(com_cmm_u_cmm_cfgspace_N_10576_i_5554) + ); + FDR com_cmm_u_cmm_cfgspace_low_addr_02_q_30_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_cfgspace_low_addr_02[30]), + .Q(com_cmm_u_cmm_cfgspace_low_addr_02_q[30]), + .R(com_cmm_u_cmm_cfgspace_N_10576_i_5554) + ); + FDR com_cmm_u_cmm_cfgspace_low_addr_02_q_31_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_cfgspace_low_addr_02[31]), + .Q(com_cmm_u_cmm_cfgspace_low_addr_02_q[31]), + .R(com_cmm_u_cmm_cfgspace_N_10576_i_5554) + ); + FDR com_cmm_u_cmm_cfgspace_low_addr_00_q_0_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_cfgspace_N_25682_i), + .Q(com_cmm_u_cmm_cfgspace_low_addr_00_q[0]), + .R(com_cmm_u_cmm_cfgspace_N_10576_i_5554) + ); + FDR com_cmm_u_cmm_cfgspace_low_addr_00_q_1_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_cfgspace_N_40005_i), + .Q(com_cmm_u_cmm_cfgspace_low_addr_00_q[1]), + .R(com_cmm_u_cmm_cfgspace_N_10576_i_5554) + ); + FDR com_cmm_u_cmm_cfgspace_low_addr_00_q_2_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_cfgspace_N_85926_i_5739), + .Q(com_cmm_u_cmm_cfgspace_low_addr_00_q[2]), + .R(com_cmm_u_cmm_cfgspace_N_10576_i_5554) + ); + FDR com_cmm_u_cmm_cfgspace_low_addr_00_q_3_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_cfgspace_N_85927_i_5736), + .Q(com_cmm_u_cmm_cfgspace_low_addr_00_q[3]), + .R(com_cmm_u_cmm_cfgspace_N_10576_i_5554) + ); + FDR com_cmm_u_cmm_cfgspace_low_addr_00_q_4_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_cfgspace_N_85928_i_5733), + .Q(com_cmm_u_cmm_cfgspace_low_addr_00_q[4]), + .R(com_cmm_u_cmm_cfgspace_N_10576_i_5554) + ); + FDR com_cmm_u_cmm_cfgspace_low_addr_00_q_5_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_cfgspace_N_85929_i_5730), + .Q(com_cmm_u_cmm_cfgspace_low_addr_00_q[5]), + .R(com_cmm_u_cmm_cfgspace_N_10576_i_5554) + ); + FDR com_cmm_u_cmm_cfgspace_low_addr_00_q_6_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_cfgspace_N_85930_i_5727), + .Q(com_cmm_u_cmm_cfgspace_low_addr_00_q[6]), + .R(com_cmm_u_cmm_cfgspace_N_10576_i_5554) + ); + FDR com_cmm_u_cmm_cfgspace_low_addr_00_q_7_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_cfgspace_N_85931_i_5724), + .Q(com_cmm_u_cmm_cfgspace_low_addr_00_q[7]), + .R(com_cmm_u_cmm_cfgspace_N_10576_i_5554) + ); + FDR com_cmm_u_cmm_cfgspace_low_addr_00_q_8_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_cfgspace_N_85932_i_5721), + .Q(com_cmm_u_cmm_cfgspace_low_addr_00_q[8]), + .R(com_cmm_u_cmm_cfgspace_N_10576_i_5554) + ); + FDR com_cmm_u_cmm_cfgspace_low_addr_00_q_9_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_cfgspace_N_85933_i_5718), + .Q(com_cmm_u_cmm_cfgspace_low_addr_00_q[9]), + .R(com_cmm_u_cmm_cfgspace_N_10576_i_5554) + ); + FDR com_cmm_u_cmm_cfgspace_low_addr_00_q_10_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_cfgspace_N_85934_i_5715), + .Q(com_cmm_u_cmm_cfgspace_low_addr_00_q[10]), + .R(com_cmm_u_cmm_cfgspace_N_10576_i_5554) + ); + FDR com_cmm_u_cmm_cfgspace_low_addr_00_q_11_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_cfgspace_N_85935_i_5714), + .Q(com_cmm_u_cmm_cfgspace_low_addr_00_q[11]), + .R(com_cmm_u_cmm_cfgspace_N_10576_i_5554) + ); + FDR com_cmm_u_cmm_cfgspace_low_addr_00_q_12_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_cfgspace_N_85936_i_5713), + .Q(com_cmm_u_cmm_cfgspace_low_addr_00_q[12]), + .R(com_cmm_u_cmm_cfgspace_N_10576_i_5554) + ); + FDR com_cmm_u_cmm_cfgspace_low_addr_00_q_13_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_cfgspace_N_85937_i_5710), + .Q(com_cmm_u_cmm_cfgspace_low_addr_00_q[13]), + .R(com_cmm_u_cmm_cfgspace_N_10576_i_5554) + ); + FDR com_cmm_u_cmm_cfgspace_low_addr_00_q_14_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_cfgspace_N_85938_i_5708), + .Q(com_cmm_u_cmm_cfgspace_low_addr_00_q[14]), + .R(com_cmm_u_cmm_cfgspace_N_10576_i_5554) + ); + FDR com_cmm_u_cmm_cfgspace_low_addr_00_q_15_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_cfgspace_N_40020_i), + .Q(com_cmm_u_cmm_cfgspace_low_addr_00_q[15]), + .R(com_cmm_u_cmm_cfgspace_N_10576_i_5554) + ); + FDR com_cmm_u_cmm_cfgspace_low_addr_00_q_16_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_cfgspace_N_17891_i), + .Q(com_cmm_u_cmm_cfgspace_low_addr_00_q[16]), + .R(com_cmm_u_cmm_cfgspace_N_10576_i_5554) + ); + FDR com_cmm_u_cmm_cfgspace_low_addr_00_q_17_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_cfgspace_N_85976_i_5703), + .Q(com_cmm_u_cmm_cfgspace_low_addr_00_q[17]), + .R(com_cmm_u_cmm_cfgspace_N_10576_i_5554) + ); + FDR com_cmm_u_cmm_cfgspace_low_addr_00_q_18_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_cfgspace_N_85977_i_5702), + .Q(com_cmm_u_cmm_cfgspace_low_addr_00_q[18]), + .R(com_cmm_u_cmm_cfgspace_N_10576_i_5554) + ); + FDR com_cmm_u_cmm_cfgspace_low_addr_00_q_19_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_cfgspace_N_85978_i_5701), + .Q(com_cmm_u_cmm_cfgspace_low_addr_00_q[19]), + .R(com_cmm_u_cmm_cfgspace_N_10576_i_5554) + ); + FDR com_cmm_u_cmm_cfgspace_low_addr_00_q_20_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_cfgspace_N_40022_i), + .Q(com_cmm_u_cmm_cfgspace_low_addr_00_q[20]), + .R(com_cmm_u_cmm_cfgspace_N_10576_i_5554) + ); + FDR com_cmm_u_cmm_cfgspace_low_addr_00_q_21_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_cfgspace_N_85939_i_5698), + .Q(com_cmm_u_cmm_cfgspace_low_addr_00_q[21]), + .R(com_cmm_u_cmm_cfgspace_N_10576_i_5554) + ); + FDR com_cmm_u_cmm_cfgspace_low_addr_00_q_22_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_cfgspace_N_40025_i), + .Q(com_cmm_u_cmm_cfgspace_low_addr_00_q[22]), + .R(com_cmm_u_cmm_cfgspace_N_10576_i_5554) + ); + FDR com_cmm_u_cmm_cfgspace_low_addr_00_q_23_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_cfgspace_N_35668_i), + .Q(com_cmm_u_cmm_cfgspace_low_addr_00_q[23]), + .R(com_cmm_u_cmm_cfgspace_N_10576_i_5554) + ); + FDR com_cmm_u_cmm_cfgspace_low_addr_00_q_24_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_cfgspace_N_40027_i), + .Q(com_cmm_u_cmm_cfgspace_low_addr_00_q[24]), + .R(com_cmm_u_cmm_cfgspace_N_10576_i_5554) + ); + FDR com_cmm_u_cmm_cfgspace_low_addr_00_q_25_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_cfgspace_N_35670_i), + .Q(com_cmm_u_cmm_cfgspace_low_addr_00_q[25]), + .R(com_cmm_u_cmm_cfgspace_N_10576_i_5554) + ); + FDR com_cmm_u_cmm_cfgspace_low_addr_00_q_26_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_cfgspace_N_35672_i), + .Q(com_cmm_u_cmm_cfgspace_low_addr_00_q[26]), + .R(com_cmm_u_cmm_cfgspace_N_10576_i_5554) + ); + FDR com_cmm_u_cmm_cfgspace_low_addr_00_q_27_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_cfgspace_N_19325_i), + .Q(com_cmm_u_cmm_cfgspace_low_addr_00_q[27]), + .R(com_cmm_u_cmm_cfgspace_N_10576_i_5554) + ); + FDR com_cmm_u_cmm_cfgspace_low_addr_00_q_28_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_cfgspace_N_25327_i), + .Q(com_cmm_u_cmm_cfgspace_low_addr_00_q[28]), + .R(com_cmm_u_cmm_cfgspace_N_10576_i_5554) + ); + FDR com_cmm_u_cmm_cfgspace_low_addr_00_q_29_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_cfgspace_N_85969_i_5695), + .Q(com_cmm_u_cmm_cfgspace_low_addr_00_q[29]), + .R(com_cmm_u_cmm_cfgspace_N_10576_i_5554) + ); + FDR com_cmm_u_cmm_cfgspace_low_addr_00_q_30_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_cfgspace_N_33956_i), + .Q(com_cmm_u_cmm_cfgspace_low_addr_00_q[30]), + .R(com_cmm_u_cmm_cfgspace_N_10576_i_5554) + ); + FDR com_cmm_u_cmm_cfgspace_low_addr_00_q_31_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_cfgspace_N_25331_i), + .Q(com_cmm_u_cmm_cfgspace_low_addr_00_q[31]), + .R(com_cmm_u_cmm_cfgspace_N_10576_i_5554) + ); + FDR com_cmm_u_cmm_cfgspace_sel_xencode_0_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_cfgspace_N_86827_i_5693), + .Q(com_cmm_u_cmm_cfgspace_sel_xencode[0]), + .R(com_cmm_rst_351) + ); + FDR com_cmm_u_cmm_cfgspace_sel_xencode_1_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_cfgspace_N_86826_i_5692), + .Q(com_cmm_u_cmm_cfgspace_sel_xencode[1]), + .R(com_cmm_rst_351) + ); + FDRS com_cmm_u_cmm_cfgspace_sel_encodex_0_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_cfgspace_N_86825_i_5758), + .Q(com_cmm_u_cmm_cfgspace_sel_encodex[0]), + .R(com_cmm_rst_351), + .S(com_cmm_u_cmm_cfgspace_N_86244_i_5757) + ); + FDRS com_cmm_u_cmm_cfgspace_sel_encodex_1_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_cfgspace_N_86243_i_5755), + .Q(com_cmm_u_cmm_cfgspace_sel_encodex[1]), + .R(com_cmm_rst_351), + .S(com_cmm_u_cmm_cfgspace_N_86244_i_5757) + ); + FDRS com_cmm_u_cmm_cfgspace_sel_encodex_2_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_cfgspace_N_86824_i_5756), + .Q(com_cmm_u_cmm_cfgspace_sel_encodex[2]), + .R(com_cmm_rst_351), + .S(com_cmm_u_cmm_cfgspace_N_86244_i_5757) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_01_2_0_a2_0_a2_0_a3_24_.INIT = 4'h1; + LUT2 com_cmm_u_cmm_cfgspace_low_addr_01_2_0_a2_0_a2_0_a3_24_ ( + .I0(com_cmm_u_cmm_cfgspace_pme_pmcsr[12]), + .I1(com_cmm_u_cmm_cfgspace_sel_encodex[1]), + .O(com_cmm_u_cmm_cfgspace_N_61397) + ); + defparam com_cmm_u_cmm_cfgspace_x3gio_pmcsr_pme_pmcsr_21_0_a2_0_a2_0_a2_1_14_.INIT = 4'h1; + LUT2 com_cmm_u_cmm_cfgspace_x3gio_pmcsr_pme_pmcsr_21_0_a2_0_a2_0_a2_1_14_ ( + .I0(com_cmm_u_cmm_cfgspace_pme_pmcsr[12]), + .I1(com_cmm_rst_351), + .O(com_cmm_u_cmm_cfgspace_pme_pmcsr_21_1[14]) + ); + defparam com_cmm_u_cmm_cfgspace_x3gio_decodepipe_h_sel_6x_3_0_0_0_0_o3_0.INIT = 4'h8; + LUT2 com_cmm_u_cmm_cfgspace_x3gio_decodepipe_h_sel_6x_3_0_0_0_0_o3_0 ( + .I0(com_cmm_cfg_addr[3]), + .I1(com_cmm_cfg_addr[4]), + .O(com_cmm_u_cmm_cfgspace_N_56350_i) + ); + defparam com_cmm_u_cmm_cfgspace_x3gio_decodepipe_h_sel_0x_3_0_0_0_0_a3_2.INIT = 4'h1; + LUT2 com_cmm_u_cmm_cfgspace_x3gio_decodepipe_h_sel_0x_3_0_0_0_0_a3_2 ( + .I0(com_cmm_cfg_addr[3]), + .I1(com_cmm_cfg_addr[4]), + .O(com_cmm_u_cmm_cfgspace_N_61290_2) + ); + defparam com_cmm_u_cmm_cfgspace_sel_encodex_en_3_i_0_0_0_a2_1_2.INIT = 4'h1; + LUT2 com_cmm_u_cmm_cfgspace_sel_encodex_en_3_i_0_0_0_a2_1_2 ( + .I0(cfg_dwaddr_6099[3]), + .I1(cfg_dwaddr_6099[4]), + .O(com_cmm_u_cmm_cfgspace_N_58589_2) + ); + defparam com_cmm_u_cmm_cfgspace_un1_state_2_1_0_o2.INIT = 4'h1; + LUT2 com_cmm_u_cmm_cfgspace_un1_state_2_1_0_o2 ( + .I0(com_cmm_u_cmm_cfgspace_state_1__5798), + .I1(com_cmm_u_cmm_cfgspace_state_2__5797), + .O(com_cmm_u_cmm_cfgspace_N_18687_i) + ); + defparam com_cmm_u_cmm_cfgspace_next_state_1_sqmuxa_i_0_0_0_o3.INIT = 4'h2; + LUT2 com_cmm_u_cmm_cfgspace_next_state_1_sqmuxa_i_0_0_0_o3 ( + .I0(com_cmm_cfg_wr), + .I1(com_cmm_posnd_wr_pack), + .O(com_cmm_N_55868_i) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_02_2_0_a2_0_a2_1_15_.INIT = 4'h2; + LUT2 com_cmm_u_cmm_cfgspace_low_addr_02_2_0_a2_0_a2_1_15_ ( + .I0(cfg_cfg_6102[482]), + .I1(com_cmm_u_cmm_cfgspace_sel_encodex[1]), + .O(com_cmm_u_cmm_cfgspace_N_59052_1) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_00_i_0_a2_1_1_1_.INIT = 4'h4; + LUT2 com_cmm_u_cmm_cfgspace_low_addr_00_i_0_a2_1_1_1_ ( + .I0(com_cmm_u_cmm_cfgspace_sel_encodex[1]), + .I1(com_cmm_u_cmm_cfgspace_sel_encodex[2]), + .O(com_cmm_u_cmm_cfgspace_N_59532_1) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_00_i_0_a2_2_1_15_.INIT = 4'h1; + LUT2 com_cmm_u_cmm_cfgspace_low_addr_00_i_0_a2_2_1_15_ ( + .I0(com_cmm_u_cmm_cfgspace_sel_encodex[0]), + .I1(com_cmm_u_cmm_cfgspace_sel_encodex[1]), + .O(com_cmm_u_cmm_cfgspace_N_59538_1) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_00_i_0_a3_15_.INIT = 4'h4; + LUT2 com_cmm_u_cmm_cfgspace_low_addr_00_i_0_a3_15_ ( + .I0(com_cmm_u_cmm_cfgspace_sel_encodex[0]), + .I1(com_cmm_u_cmm_cfgspace_sel_encodex[2]), + .O(com_cmm_u_cmm_cfgspace_N_61347) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_00_i_0_0_0_a3_0_27_.INIT = 4'h8; + LUT2 com_cmm_u_cmm_cfgspace_low_addr_00_i_0_0_0_a3_0_27_ ( + .I0(com_cmm_u_cmm_cfgspace_sel_encodex[0]), + .I1(com_cmm_u_cmm_cfgspace_sel_encodex[2]), + .O(com_cmm_u_cmm_cfgspace_N_61336) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_00_i_0_0_0_a3_27_.INIT = 4'h4; + LUT2 com_cmm_u_cmm_cfgspace_low_addr_00_i_0_0_0_a3_27_ ( + .I0(com_cmm_u_cmm_cfgspace_sel_encodex[0]), + .I1(com_cmm_u_cmm_cfgspace_sel_encodex[1]), + .O(com_cmm_u_cmm_cfgspace_N_61316) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_00_i_0_0_0_a2_27_.INIT = 4'h8; + LUT2 com_cmm_u_cmm_cfgspace_low_addr_00_i_0_0_0_a2_27_ ( + .I0(com_cmm_u_cmm_cfgspace_sel_encodex[1]), + .I1(com_cmm_u_cmm_cfgspace_sel_encodex[2]), + .O(com_cmm_u_cmm_cfgspace_N_58663) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_01_1_0_1_.INIT = 8'hCA; + LUT3_L com_cmm_u_cmm_cfgspace_low_addr_01_1_0_1_ ( + .I0(NlwRenamedSig_OI_cfg_command_1_), + .I1(com_cmm_bar5_reg[1]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex[1]), + .LO(com_cmm_u_cmm_cfgspace_N_3731) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_01_1_0_8_.INIT = 8'hCA; + LUT3_L com_cmm_u_cmm_cfgspace_low_addr_01_1_0_8_ ( + .I0(NlwRenamedSig_OI_cfg_command_8_), + .I1(com_cmm_bar5_reg[8]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex[1]), + .LO(com_cmm_u_cmm_cfgspace_N_3738) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_01_1_0_19_.INIT = 8'hCA; + LUT3_L com_cmm_u_cmm_cfgspace_low_addr_01_1_0_19_ ( + .I0(NlwRenamedSig_OI_cfg_status_3_), + .I1(com_cmm_bar5_reg[19]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex[1]), + .LO(com_cmm_u_cmm_cfgspace_N_3749) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_01_1_0_24_.INIT = 8'hCA; + LUT3 com_cmm_u_cmm_cfgspace_low_addr_01_1_0_24_ ( + .I0(NlwRenamedSig_OI_cfg_status_8_), + .I1(com_cmm_bar5_reg[24]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex[1]), + .O(com_cmm_u_cmm_cfgspace_N_3754) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_01_1_0_27_.INIT = 8'hCA; + LUT3 com_cmm_u_cmm_cfgspace_low_addr_01_1_0_27_ ( + .I0(NlwRenamedSig_OI_cfg_status_11_), + .I1(com_cmm_bar5_reg[27]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex[1]), + .O(com_cmm_u_cmm_cfgspace_N_3757) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_01_1_0_28_.INIT = 8'hCA; + LUT3 com_cmm_u_cmm_cfgspace_low_addr_01_1_0_28_ ( + .I0(NlwRenamedSig_OI_cfg_status_12_), + .I1(com_cmm_bar5_reg[28]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex[1]), + .O(com_cmm_u_cmm_cfgspace_N_3758) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_01_1_0_29_.INIT = 8'hCA; + LUT3 com_cmm_u_cmm_cfgspace_low_addr_01_1_0_29_ ( + .I0(NlwRenamedSig_OI_cfg_status_13_), + .I1(com_cmm_bar5_reg[29]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex[1]), + .O(com_cmm_u_cmm_cfgspace_N_3759) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_01_1_0_30_.INIT = 8'hCA; + LUT3 com_cmm_u_cmm_cfgspace_low_addr_01_1_0_30_ ( + .I0(NlwRenamedSig_OI_cfg_status_14_), + .I1(com_cmm_bar5_reg[30]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex[1]), + .O(com_cmm_u_cmm_cfgspace_N_3760) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_01_1_0_31_.INIT = 8'hCA; + LUT3 com_cmm_u_cmm_cfgspace_low_addr_01_1_0_31_ ( + .I0(NlwRenamedSig_OI_cfg_status_15_), + .I1(com_cmm_bar5_reg[31]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex[1]), + .O(com_cmm_u_cmm_cfgspace_N_3761) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_01_2_0_11_.INIT = 8'hAC; + LUT3_L com_cmm_u_cmm_cfgspace_low_addr_01_2_0_11_ ( + .I0(cfg_cfg_6102[411]), + .I1(com_cmm_u_cmm_cfgspace_pme_pmcsr[11]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex[1]), + .LO(com_cmm_u_cmm_cfgspace_N_3773) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_01_2_0_13_.INIT = 8'hE2; + LUT3_L com_cmm_u_cmm_cfgspace_low_addr_01_2_0_13_ ( + .I0(com_cmm_u_cmm_cfgspace_pme_pmcsr[13]), + .I1(com_cmm_u_cmm_cfgspace_sel_encodex[1]), + .I2(com_cmm_u_cmm_cfgspace_x_lcap[0]), + .LO(com_cmm_u_cmm_cfgspace_N_3775) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_01_2_0_15_.INIT = 8'hE2; + LUT3_L com_cmm_u_cmm_cfgspace_low_addr_01_2_0_15_ ( + .I0(com_cmm_u_cmm_cfgspace_pme_pmcsr[15]), + .I1(com_cmm_u_cmm_cfgspace_sel_encodex[1]), + .I2(com_cmm_u_cmm_cfgspace_x_lcap[0]), + .LO(com_cmm_u_cmm_cfgspace_N_3777) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_01_5_0_0_.INIT = 8'hAC; + LUT3_L com_cmm_u_cmm_cfgspace_low_addr_01_5_0_0_ ( + .I0(cfg_cfg_6102[656]), + .I1(com_cmm_msi_data[0]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex[1]), + .LO(com_cmm_u_cmm_cfgspace_N_3858) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_01_5_0_1_.INIT = 8'hAC; + LUT3_L com_cmm_u_cmm_cfgspace_low_addr_01_5_0_1_ ( + .I0(cfg_cfg_6102[657]), + .I1(com_cmm_msi_data[1]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex[1]), + .LO(com_cmm_u_cmm_cfgspace_N_3859) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_01_5_0_2_.INIT = 8'hAC; + LUT3_L com_cmm_u_cmm_cfgspace_low_addr_01_5_0_2_ ( + .I0(cfg_cfg_6102[658]), + .I1(com_cmm_msi_data[2]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex[1]), + .LO(com_cmm_u_cmm_cfgspace_N_3860) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_01_5_0_3_.INIT = 8'hAC; + LUT3_L com_cmm_u_cmm_cfgspace_low_addr_01_5_0_3_ ( + .I0(cfg_cfg_6102[659]), + .I1(com_cmm_msi_data[3]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex[1]), + .LO(com_cmm_u_cmm_cfgspace_N_3861) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_01_5_0_4_.INIT = 8'hAC; + LUT3_L com_cmm_u_cmm_cfgspace_low_addr_01_5_0_4_ ( + .I0(cfg_cfg_6102[660]), + .I1(com_cmm_msi_data[4]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex[1]), + .LO(com_cmm_u_cmm_cfgspace_N_3862) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_01_5_0_5_.INIT = 8'hAC; + LUT3_L com_cmm_u_cmm_cfgspace_low_addr_01_5_0_5_ ( + .I0(cfg_cfg_6102[661]), + .I1(com_cmm_msi_data[5]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex[1]), + .LO(com_cmm_u_cmm_cfgspace_N_3863) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_01_5_0_7_.INIT = 8'hAC; + LUT3_L com_cmm_u_cmm_cfgspace_low_addr_01_5_0_7_ ( + .I0(cfg_cfg_6102[663]), + .I1(com_cmm_msi_data[7]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex[1]), + .LO(com_cmm_u_cmm_cfgspace_N_3865) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_01_5_0_8_.INIT = 8'hAC; + LUT3_L com_cmm_u_cmm_cfgspace_low_addr_01_5_0_8_ ( + .I0(cfg_cfg_6102[664]), + .I1(com_cmm_msi_data[8]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex[1]), + .LO(com_cmm_u_cmm_cfgspace_N_3866) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_01_5_0_9_.INIT = 8'hAC; + LUT3_L com_cmm_u_cmm_cfgspace_low_addr_01_5_0_9_ ( + .I0(cfg_cfg_6102[665]), + .I1(com_cmm_msi_data[9]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex[1]), + .LO(com_cmm_u_cmm_cfgspace_N_3867) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_01_5_0_10_.INIT = 8'hAC; + LUT3_L com_cmm_u_cmm_cfgspace_low_addr_01_5_0_10_ ( + .I0(cfg_cfg_6102[666]), + .I1(com_cmm_msi_data[10]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex[1]), + .LO(com_cmm_u_cmm_cfgspace_N_3868) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_01_5_0_11_.INIT = 8'hAC; + LUT3_L com_cmm_u_cmm_cfgspace_low_addr_01_5_0_11_ ( + .I0(cfg_cfg_6102[667]), + .I1(com_cmm_msi_data[11]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex[1]), + .LO(com_cmm_u_cmm_cfgspace_N_3869) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_01_5_0_13_.INIT = 8'hAC; + LUT3_L com_cmm_u_cmm_cfgspace_low_addr_01_5_0_13_ ( + .I0(cfg_cfg_6102[669]), + .I1(com_cmm_msi_data[13]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex[1]), + .LO(com_cmm_u_cmm_cfgspace_N_3871) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_01_5_0_15_.INIT = 8'hAC; + LUT3_L com_cmm_u_cmm_cfgspace_low_addr_01_5_0_15_ ( + .I0(cfg_cfg_6102[671]), + .I1(com_cmm_msi_data[15]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex[1]), + .LO(com_cmm_u_cmm_cfgspace_N_3873) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_03_q_4_1_0_2_.INIT = 8'hAC; + LUT3_L com_cmm_u_cmm_cfgspace_low_addr_03_q_4_1_0_2_ ( + .I0(cfg_cfg_6102[290]), + .I1(com_cmm_u_cmm_cfgspace_cache_line[2]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex[1]), + .LO(com_cmm_u_cmm_cfgspace_N_3956) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_03_q_4_1_0_3_.INIT = 8'hAC; + LUT3_L com_cmm_u_cmm_cfgspace_low_addr_03_q_4_1_0_3_ ( + .I0(cfg_cfg_6102[291]), + .I1(com_cmm_u_cmm_cfgspace_cache_line[3]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex[1]), + .LO(com_cmm_u_cmm_cfgspace_N_3957) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_03_q_4_1_0_4_.INIT = 8'hAC; + LUT3_L com_cmm_u_cmm_cfgspace_low_addr_03_q_4_1_0_4_ ( + .I0(cfg_cfg_6102[292]), + .I1(com_cmm_u_cmm_cfgspace_cache_line[4]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex[1]), + .LO(com_cmm_u_cmm_cfgspace_N_3958) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_03_q_4_1_0_5_.INIT = 8'hAC; + LUT3_L com_cmm_u_cmm_cfgspace_low_addr_03_q_4_1_0_5_ ( + .I0(cfg_cfg_6102[293]), + .I1(com_cmm_u_cmm_cfgspace_cache_line[5]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex[1]), + .LO(com_cmm_u_cmm_cfgspace_N_3959) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_03_q_4_1_0_6_.INIT = 8'hAC; + LUT3_L com_cmm_u_cmm_cfgspace_low_addr_03_q_4_1_0_6_ ( + .I0(cfg_cfg_6102[294]), + .I1(com_cmm_u_cmm_cfgspace_cache_line[6]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex[1]), + .LO(com_cmm_u_cmm_cfgspace_N_3960) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_03_q_4_1_0_7_.INIT = 8'hAC; + LUT3_L com_cmm_u_cmm_cfgspace_low_addr_03_q_4_1_0_7_ ( + .I0(cfg_cfg_6102[295]), + .I1(com_cmm_u_cmm_cfgspace_cache_line[7]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex[1]), + .LO(com_cmm_u_cmm_cfgspace_N_3961) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_03_q_4_4_0_0_.INIT = 8'hCA; + LUT3_L com_cmm_u_cmm_cfgspace_low_addr_03_q_4_4_0_0_ ( + .I0(com_cmm_bar3_reg[0]), + .I1(com_cmm_u_cmm_cfgspace_int_line[0]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex[1]), + .LO(com_cmm_u_cmm_cfgspace_N_4050) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_03_q_4_4_0_1_.INIT = 8'hCA; + LUT3_L com_cmm_u_cmm_cfgspace_low_addr_03_q_4_4_0_1_ ( + .I0(com_cmm_bar3_reg[1]), + .I1(com_cmm_u_cmm_cfgspace_int_line[1]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex[1]), + .LO(com_cmm_u_cmm_cfgspace_N_4051) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_03_q_4_4_0_2_.INIT = 8'hCA; + LUT3_L com_cmm_u_cmm_cfgspace_low_addr_03_q_4_4_0_2_ ( + .I0(com_cmm_bar3_reg[2]), + .I1(com_cmm_u_cmm_cfgspace_int_line[2]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex[1]), + .LO(com_cmm_u_cmm_cfgspace_N_4052) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_03_q_4_4_0_3_.INIT = 8'hCA; + LUT3_L com_cmm_u_cmm_cfgspace_low_addr_03_q_4_4_0_3_ ( + .I0(com_cmm_bar3_reg[3]), + .I1(com_cmm_u_cmm_cfgspace_int_line[3]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex[1]), + .LO(com_cmm_u_cmm_cfgspace_N_4053) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_03_q_4_4_0_4_.INIT = 8'hCA; + LUT3_L com_cmm_u_cmm_cfgspace_low_addr_03_q_4_4_0_4_ ( + .I0(com_cmm_bar3_reg[4]), + .I1(com_cmm_u_cmm_cfgspace_int_line[4]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex[1]), + .LO(com_cmm_u_cmm_cfgspace_N_4054) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_03_q_4_4_0_5_.INIT = 8'hCA; + LUT3_L com_cmm_u_cmm_cfgspace_low_addr_03_q_4_4_0_5_ ( + .I0(com_cmm_bar3_reg[5]), + .I1(com_cmm_u_cmm_cfgspace_int_line[5]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex[1]), + .LO(com_cmm_u_cmm_cfgspace_N_4055) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_03_q_4_4_0_6_.INIT = 8'hCA; + LUT3_L com_cmm_u_cmm_cfgspace_low_addr_03_q_4_4_0_6_ ( + .I0(com_cmm_bar3_reg[6]), + .I1(com_cmm_u_cmm_cfgspace_int_line[6]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex[1]), + .LO(com_cmm_u_cmm_cfgspace_N_4056) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_03_q_4_4_0_7_.INIT = 8'hCA; + LUT3_L com_cmm_u_cmm_cfgspace_low_addr_03_q_4_4_0_7_ ( + .I0(com_cmm_bar3_reg[7]), + .I1(com_cmm_u_cmm_cfgspace_int_line[7]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex[1]), + .LO(com_cmm_u_cmm_cfgspace_N_4057) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_02_1_0_0_.INIT = 8'hCA; + LUT3_L com_cmm_u_cmm_cfgspace_low_addr_02_1_0_0_ ( + .I0(cfg_cfg_6102[32]), + .I1(cfg_cfg_6102[256]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex[1]), + .LO(com_cmm_u_cmm_cfgspace_N_4578) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_02_1_0_1_.INIT = 8'hCA; + LUT3_L com_cmm_u_cmm_cfgspace_low_addr_02_1_0_1_ ( + .I0(cfg_cfg_6102[33]), + .I1(cfg_cfg_6102[257]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex[1]), + .LO(com_cmm_u_cmm_cfgspace_N_4579) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_02_1_0_3_.INIT = 8'hCA; + LUT3_L com_cmm_u_cmm_cfgspace_low_addr_02_1_0_3_ ( + .I0(cfg_cfg_6102[35]), + .I1(cfg_cfg_6102[259]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex[1]), + .LO(com_cmm_u_cmm_cfgspace_N_4581) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_02_1_0_8_.INIT = 8'hCA; + LUT3 com_cmm_u_cmm_cfgspace_low_addr_02_1_0_8_ ( + .I0(cfg_cfg_6102[40]), + .I1(cfg_cfg_6102[264]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex[1]), + .O(com_cmm_u_cmm_cfgspace_N_4586) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_02_1_0_9_.INIT = 8'hCA; + LUT3 com_cmm_u_cmm_cfgspace_low_addr_02_1_0_9_ ( + .I0(cfg_cfg_6102[41]), + .I1(cfg_cfg_6102[265]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex[1]), + .O(com_cmm_u_cmm_cfgspace_N_4587) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_02_1_0_10_.INIT = 8'hCA; + LUT3 com_cmm_u_cmm_cfgspace_low_addr_02_1_0_10_ ( + .I0(cfg_cfg_6102[42]), + .I1(cfg_cfg_6102[266]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex[1]), + .O(com_cmm_u_cmm_cfgspace_N_4588) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_02_1_0_13_.INIT = 8'hCA; + LUT3 com_cmm_u_cmm_cfgspace_low_addr_02_1_0_13_ ( + .I0(cfg_cfg_6102[45]), + .I1(cfg_cfg_6102[269]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex[1]), + .O(com_cmm_u_cmm_cfgspace_N_4591) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_02_1_0_15_.INIT = 8'hCA; + LUT3 com_cmm_u_cmm_cfgspace_low_addr_02_1_0_15_ ( + .I0(cfg_cfg_6102[47]), + .I1(cfg_cfg_6102[271]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex[1]), + .O(com_cmm_u_cmm_cfgspace_N_4593) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_02_1_0_20_.INIT = 8'hCA; + LUT3_L com_cmm_u_cmm_cfgspace_low_addr_02_1_0_20_ ( + .I0(cfg_cfg_6102[52]), + .I1(cfg_cfg_6102[276]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex[1]), + .LO(com_cmm_u_cmm_cfgspace_N_4598) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_02_1_0_22_.INIT = 8'hCA; + LUT3_L com_cmm_u_cmm_cfgspace_low_addr_02_1_0_22_ ( + .I0(cfg_cfg_6102[54]), + .I1(cfg_cfg_6102[278]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex[1]), + .LO(com_cmm_u_cmm_cfgspace_N_4600) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_02_1_0_28_.INIT = 8'hCA; + LUT3_L com_cmm_u_cmm_cfgspace_low_addr_02_1_0_28_ ( + .I0(cfg_cfg_6102[60]), + .I1(cfg_cfg_6102[284]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex[1]), + .LO(com_cmm_u_cmm_cfgspace_N_4606) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_02_5_0_0_.INIT = 8'hCA; + LUT3_L com_cmm_u_cmm_cfgspace_low_addr_02_5_0_0_ ( + .I0(cfg_cfg_6102[424]), + .I1(cfg_cfg_6102[688]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex[1]), + .LO(com_cmm_u_cmm_cfgspace_N_4706) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_02_5_0_1_.INIT = 8'hCA; + LUT3_L com_cmm_u_cmm_cfgspace_low_addr_02_5_0_1_ ( + .I0(cfg_cfg_6102[425]), + .I1(cfg_cfg_6102[689]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex[1]), + .LO(com_cmm_u_cmm_cfgspace_N_4707) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_02_5_0_2_.INIT = 8'hCA; + LUT3_L com_cmm_u_cmm_cfgspace_low_addr_02_5_0_2_ ( + .I0(cfg_cfg_6102[426]), + .I1(cfg_cfg_6102[690]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex[1]), + .LO(com_cmm_u_cmm_cfgspace_N_4708) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_02_5_0_3_.INIT = 8'hCA; + LUT3_L com_cmm_u_cmm_cfgspace_low_addr_02_5_0_3_ ( + .I0(cfg_cfg_6102[427]), + .I1(cfg_cfg_6102[691]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex[1]), + .LO(com_cmm_u_cmm_cfgspace_N_4709) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_02_5_0_4_.INIT = 8'hCA; + LUT3_L com_cmm_u_cmm_cfgspace_low_addr_02_5_0_4_ ( + .I0(cfg_cfg_6102[428]), + .I1(cfg_cfg_6102[692]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex[1]), + .LO(com_cmm_u_cmm_cfgspace_N_4710) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_02_5_0_5_.INIT = 8'hCA; + LUT3_L com_cmm_u_cmm_cfgspace_low_addr_02_5_0_5_ ( + .I0(cfg_cfg_6102[429]), + .I1(cfg_cfg_6102[693]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex[1]), + .LO(com_cmm_u_cmm_cfgspace_N_4711) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_02_5_0_14_.INIT = 8'hCA; + LUT3_L com_cmm_u_cmm_cfgspace_low_addr_02_5_0_14_ ( + .I0(cfg_cfg_6102[502]), + .I1(cfg_cfg_6102[702]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex[1]), + .LO(com_cmm_u_cmm_cfgspace_N_4720) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_02_5_0_15_.INIT = 8'hCA; + LUT3_L com_cmm_u_cmm_cfgspace_low_addr_02_5_0_15_ ( + .I0(cfg_cfg_6102[502]), + .I1(cfg_cfg_6102[703]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex[1]), + .LO(com_cmm_u_cmm_cfgspace_N_4721) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_02_5_0_16_.INIT = 8'hCA; + LUT3_L com_cmm_u_cmm_cfgspace_low_addr_02_5_0_16_ ( + .I0(cfg_cfg_6102[352]), + .I1(cfg_cfg_6102[704]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex[1]), + .LO(com_cmm_u_cmm_cfgspace_N_4722) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_02_5_0_17_.INIT = 8'hCA; + LUT3_L com_cmm_u_cmm_cfgspace_low_addr_02_5_0_17_ ( + .I0(cfg_cfg_6102[353]), + .I1(cfg_cfg_6102[705]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex[1]), + .LO(com_cmm_u_cmm_cfgspace_N_4723) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_02_5_0_18_.INIT = 8'hCA; + LUT3_L com_cmm_u_cmm_cfgspace_low_addr_02_5_0_18_ ( + .I0(cfg_cfg_6102[354]), + .I1(cfg_cfg_6102[706]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex[1]), + .LO(com_cmm_u_cmm_cfgspace_N_4724) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_02_5_0_19_.INIT = 8'hCA; + LUT3_L com_cmm_u_cmm_cfgspace_low_addr_02_5_0_19_ ( + .I0(cfg_cfg_6102[355]), + .I1(cfg_cfg_6102[707]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex[1]), + .LO(com_cmm_u_cmm_cfgspace_N_4725) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_02_5_0_20_.INIT = 8'hCA; + LUT3_L com_cmm_u_cmm_cfgspace_low_addr_02_5_0_20_ ( + .I0(cfg_cfg_6102[356]), + .I1(cfg_cfg_6102[708]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex[1]), + .LO(com_cmm_u_cmm_cfgspace_N_4726) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_02_5_0_21_.INIT = 8'hCA; + LUT3_L com_cmm_u_cmm_cfgspace_low_addr_02_5_0_21_ ( + .I0(cfg_cfg_6102[357]), + .I1(cfg_cfg_6102[709]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex[1]), + .LO(com_cmm_u_cmm_cfgspace_N_4727) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_02_5_0_22_.INIT = 8'hCA; + LUT3_L com_cmm_u_cmm_cfgspace_low_addr_02_5_0_22_ ( + .I0(cfg_cfg_6102[358]), + .I1(cfg_cfg_6102[710]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex[1]), + .LO(com_cmm_u_cmm_cfgspace_N_4728) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_02_5_0_23_.INIT = 8'hCA; + LUT3_L com_cmm_u_cmm_cfgspace_low_addr_02_5_0_23_ ( + .I0(cfg_cfg_6102[359]), + .I1(cfg_cfg_6102[711]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex[1]), + .LO(com_cmm_u_cmm_cfgspace_N_4729) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_02_5_0_24_.INIT = 8'hCA; + LUT3_L com_cmm_u_cmm_cfgspace_low_addr_02_5_0_24_ ( + .I0(cfg_cfg_6102[360]), + .I1(cfg_cfg_6102[712]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex[1]), + .LO(com_cmm_u_cmm_cfgspace_N_4730) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_02_5_0_25_.INIT = 8'hCA; + LUT3_L com_cmm_u_cmm_cfgspace_low_addr_02_5_0_25_ ( + .I0(cfg_cfg_6102[361]), + .I1(cfg_cfg_6102[713]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex[1]), + .LO(com_cmm_u_cmm_cfgspace_N_4731) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_02_5_0_26_.INIT = 8'hCA; + LUT3_L com_cmm_u_cmm_cfgspace_low_addr_02_5_0_26_ ( + .I0(cfg_cfg_6102[362]), + .I1(cfg_cfg_6102[714]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex[1]), + .LO(com_cmm_u_cmm_cfgspace_N_4732) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_02_5_0_27_.INIT = 8'hCA; + LUT3_L com_cmm_u_cmm_cfgspace_low_addr_02_5_0_27_ ( + .I0(cfg_cfg_6102[363]), + .I1(cfg_cfg_6102[715]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex[1]), + .LO(com_cmm_u_cmm_cfgspace_N_4733) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_02_5_0_28_.INIT = 8'hCA; + LUT3_L com_cmm_u_cmm_cfgspace_low_addr_02_5_0_28_ ( + .I0(cfg_cfg_6102[364]), + .I1(cfg_cfg_6102[716]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex[1]), + .LO(com_cmm_u_cmm_cfgspace_N_4734) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_02_5_0_29_.INIT = 8'hCA; + LUT3_L com_cmm_u_cmm_cfgspace_low_addr_02_5_0_29_ ( + .I0(cfg_cfg_6102[365]), + .I1(cfg_cfg_6102[717]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex[1]), + .LO(com_cmm_u_cmm_cfgspace_N_4735) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_02_5_0_30_.INIT = 8'hCA; + LUT3_L com_cmm_u_cmm_cfgspace_low_addr_02_5_0_30_ ( + .I0(cfg_cfg_6102[366]), + .I1(cfg_cfg_6102[718]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex[1]), + .LO(com_cmm_u_cmm_cfgspace_N_4736) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_02_5_0_31_.INIT = 8'hCA; + LUT3_L com_cmm_u_cmm_cfgspace_low_addr_02_5_0_31_ ( + .I0(cfg_cfg_6102[367]), + .I1(cfg_cfg_6102[719]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex[1]), + .LO(com_cmm_u_cmm_cfgspace_N_4737) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_02_5_0_7_.INIT = 8'hCA; + LUT3_L com_cmm_u_cmm_cfgspace_low_addr_02_5_0_7_ ( + .I0(cfg_cfg_6102[431]), + .I1(cfg_cfg_6102[695]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex[1]), + .LO(com_cmm_u_cmm_cfgspace_N_4713) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_02_5_0_6_.INIT = 8'hCA; + LUT3_L com_cmm_u_cmm_cfgspace_low_addr_02_5_0_6_ ( + .I0(cfg_cfg_6102[430]), + .I1(cfg_cfg_6102[694]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex[1]), + .LO(com_cmm_u_cmm_cfgspace_N_4712) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_02_1_0_7_.INIT = 8'hCA; + LUT3_L com_cmm_u_cmm_cfgspace_low_addr_02_1_0_7_ ( + .I0(cfg_cfg_6102[39]), + .I1(cfg_cfg_6102[263]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex[1]), + .LO(com_cmm_u_cmm_cfgspace_N_4585) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_02_1_0_6_.INIT = 8'hCA; + LUT3_L com_cmm_u_cmm_cfgspace_low_addr_02_1_0_6_ ( + .I0(cfg_cfg_6102[38]), + .I1(cfg_cfg_6102[262]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex[1]), + .LO(com_cmm_u_cmm_cfgspace_N_4584) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_01_5_0_14_.INIT = 8'hAC; + LUT3_L com_cmm_u_cmm_cfgspace_low_addr_01_5_0_14_ ( + .I0(cfg_cfg_6102[670]), + .I1(com_cmm_msi_data[14]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex[1]), + .LO(com_cmm_u_cmm_cfgspace_N_3872) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_01_5_0_12_.INIT = 8'hAC; + LUT3_L com_cmm_u_cmm_cfgspace_low_addr_01_5_0_12_ ( + .I0(cfg_cfg_6102[668]), + .I1(com_cmm_msi_data[12]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex[1]), + .LO(com_cmm_u_cmm_cfgspace_N_3870) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_01_5_0_6_.INIT = 8'hAC; + LUT3_L com_cmm_u_cmm_cfgspace_low_addr_01_5_0_6_ ( + .I0(cfg_cfg_6102[662]), + .I1(com_cmm_msi_data[6]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex[1]), + .LO(com_cmm_u_cmm_cfgspace_N_3864) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_01_2_0_14_.INIT = 8'hE2; + LUT3_L com_cmm_u_cmm_cfgspace_low_addr_01_2_0_14_ ( + .I0(com_cmm_u_cmm_cfgspace_pme_pmcsr[14]), + .I1(com_cmm_u_cmm_cfgspace_sel_encodex[1]), + .I2(com_cmm_u_cmm_cfgspace_x_lcap[0]), + .LO(com_cmm_u_cmm_cfgspace_N_3776) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_01_2_0_12_.INIT = 8'hE2; + LUT3_L com_cmm_u_cmm_cfgspace_low_addr_01_2_0_12_ ( + .I0(com_cmm_u_cmm_cfgspace_pme_pmcsr[12]), + .I1(com_cmm_u_cmm_cfgspace_sel_encodex[1]), + .I2(com_cmm_u_cmm_cfgspace_x_lcap[0]), + .LO(com_cmm_u_cmm_cfgspace_N_3774) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_01_1_0_6_.INIT = 8'hCA; + LUT3_L com_cmm_u_cmm_cfgspace_low_addr_01_1_0_6_ ( + .I0(NlwRenamedSig_OI_cfg_command_6_), + .I1(com_cmm_bar5_reg[6]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex[1]), + .LO(com_cmm_u_cmm_cfgspace_N_3736) + ); + defparam com_cmm_u_cmm_cfgspace_N_10576_i.INIT = 4'hB; + LUT2 com_cmm_u_cmm_cfgspace_N_10576_i ( + .I0(com_cmm_rst_351), + .I1(com_cmm_u_cmm_cfgspace_sel_encodex_en_5555), + .O(com_cmm_u_cmm_cfgspace_N_10576_i_5554) + ); + defparam com_cmm_u_cmm_cfgspace_x3gio_msihaddr_msi_haddr12_0_a2_0_a2_0_a2_0_o3.INIT = 8'h80; + LUT3 com_cmm_u_cmm_cfgspace_x3gio_msihaddr_msi_haddr12_0_a2_0_a2_0_a2_0_o3 ( + .I0(com_cmm_N_55868_i), + .I1(com_cmm_state_0[1]), + .I2(com_cmm_state[6]), + .O(com_cmm_u_cmm_cfgspace_N_55870_i) + ); + defparam com_cmm_u_cmm_cfgspace_x3gio_decodepipe_l_sel_x3_3_i_0_0_a2_1.INIT = 4'h2; + LUT2 com_cmm_u_cmm_cfgspace_x3gio_decodepipe_l_sel_x3_3_i_0_0_a2_1 ( + .I0(com_cmm_u_cmm_cfgspace_N_18687_i), + .I1(com_cmm_cfg_rd), + .O(com_cmm_u_cmm_cfgspace_N_59237_1) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_00_i_i_0_a2_2_1_19_.INIT = 4'h2; + LUT2 com_cmm_u_cmm_cfgspace_low_addr_00_i_i_0_a2_2_1_19_ ( + .I0(com_cmm_u_cmm_cfgspace_N_61347), + .I1(com_cmm_u_cmm_cfgspace_sel_encodex[1]), + .O(com_cmm_u_cmm_cfgspace_N_59578_1) + ); + defparam com_cmm_u_cmm_cfgspace_x3gio_bar1_bar1_reg_8_1_0_0_0_o3_0_0_.INIT = 8'h10; + LUT3 com_cmm_u_cmm_cfgspace_x3gio_bar1_bar1_reg_8_1_0_0_0_o3_0_0_ ( + .I0(cfg_cfg_6102[64]), + .I1(cfg_cfg_6102[65]), + .I2(cfg_cfg_6102[66]), + .O(com_cmm_u_cmm_cfgspace_N_56071_i) + ); + defparam com_cmm_u_cmm_cfgspace_x3gio_bar2_bar2_reg_8_1_0_0_0_o3_0_0_.INIT = 8'h10; + LUT3 com_cmm_u_cmm_cfgspace_x3gio_bar2_bar2_reg_8_1_0_0_0_o3_0_0_ ( + .I0(cfg_cfg_6102[96]), + .I1(cfg_cfg_6102[97]), + .I2(cfg_cfg_6102[98]), + .O(com_cmm_u_cmm_cfgspace_N_56070_i) + ); + defparam com_cmm_u_cmm_cfgspace_x3gio_bar3_bar3_reg_8_1_0_0_0_o3_0_0_.INIT = 4'h8; + LUT2 com_cmm_u_cmm_cfgspace_x3gio_bar3_bar3_reg_8_1_0_0_0_o3_0_0_ ( + .I0(com_cmm_N_56056_i), + .I1(cfg_cfg_6102[130]), + .O(com_cmm_u_cmm_cfgspace_N_56069_i) + ); + defparam com_cmm_u_cmm_cfgspace_x3gio_bar4_bar4_reg_8_1_0_0_0_o3_0_0_.INIT = 4'h8; + LUT2 com_cmm_u_cmm_cfgspace_x3gio_bar4_bar4_reg_8_1_0_0_0_o3_0_0_ ( + .I0(com_cmm_N_56057_i), + .I1(cfg_cfg_6102[162]), + .O(com_cmm_u_cmm_cfgspace_N_56068_i) + ); + defparam com_cmm_u_cmm_cfgspace_x3gio_bar5_bar5_reg_8_1_0_0_0_o3_0_0_.INIT = 4'h8; + LUT2 com_cmm_u_cmm_cfgspace_x3gio_bar5_bar5_reg_8_1_0_0_0_o3_0_0_ ( + .I0(com_cmm_N_56058_i), + .I1(cfg_cfg_6102[194]), + .O(com_cmm_u_cmm_cfgspace_N_56067_i) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_00_0_0_0_a3_0_2_.INIT = 8'h01; + LUT3 com_cmm_u_cmm_cfgspace_low_addr_00_0_0_0_a3_0_2_ ( + .I0(com_cmm_u_cmm_cfgspace_sel_encodex[0]), + .I1(com_cmm_u_cmm_cfgspace_sel_encodex[1]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex[2]), + .O(com_cmm_u_cmm_cfgspace_N_61340) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_00_0_0_0_a3_2_.INIT = 8'h02; + LUT3 com_cmm_u_cmm_cfgspace_low_addr_00_0_0_0_a3_2_ ( + .I0(com_cmm_u_cmm_cfgspace_sel_encodex[0]), + .I1(com_cmm_u_cmm_cfgspace_sel_encodex[1]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex[2]), + .O(com_cmm_u_cmm_cfgspace_N_61330) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_00_i_0_0_0_a2_1_31_.INIT = 4'h2; + LUT2 com_cmm_u_cmm_cfgspace_low_addr_00_i_0_0_0_a2_1_31_ ( + .I0(com_cmm_u_cmm_cfgspace_N_61347), + .I1(cfg_cfg_6102[527]), + .O(com_cmm_u_cmm_cfgspace_N_59010) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_00_i_0_0_0_a2_1_28_.INIT = 4'h2; + LUT2 com_cmm_u_cmm_cfgspace_low_addr_00_i_0_0_0_a2_1_28_ ( + .I0(com_cmm_u_cmm_cfgspace_N_61347), + .I1(cfg_cfg_6102[524]), + .O(com_cmm_u_cmm_cfgspace_N_59004) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_00_i_0_0_0_a2_2_27_.INIT = 4'h2; + LUT2 com_cmm_u_cmm_cfgspace_low_addr_00_i_0_0_0_a2_2_27_ ( + .I0(com_cmm_u_cmm_cfgspace_N_61347), + .I1(cfg_cfg_6102[523]), + .O(com_cmm_u_cmm_cfgspace_N_58666) + ); + defparam com_cmm_u_cmm_cfgspace_sel_encodex_en_3_i_0_0_0_a2_3_1.INIT = 16'h0001; + LUT4 com_cmm_u_cmm_cfgspace_sel_encodex_en_3_i_0_0_0_a2_3_1 ( + .I0(com_cmm_cfg_addr[5]), + .I1(com_cmm_cfg_addr[7]), + .I2(com_cmm_cfg_addr[8]), + .I3(com_cmm_cfg_addr[9]), + .O(com_cmm_u_cmm_cfgspace_N_58591_1) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_00_i_i_0_0_a2_29_.INIT = 8'h80; + LUT3 com_cmm_u_cmm_cfgspace_low_addr_00_i_i_0_0_a2_29_ ( + .I0(com_cmm_u_cmm_cfgspace_N_61336), + .I1(cfg_cfg_6102[503]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex[1]), + .O(com_cmm_u_cmm_cfgspace_N_59358) + ); + defparam com_cmm_u_cmm_cfgspace_decoder_sel_addr_0_0_0_0_o3_0_.INIT = 8'h02; + LUT3 com_cmm_u_cmm_cfgspace_decoder_sel_addr_0_0_0_0_o3_0_ ( + .I0(com_cmm_u_cmm_cfgspace_N_18687_i), + .I1(com_cmm_u_cmm_cfgspace_cfg2ulm_valid), + .I2(com_cmm_u_cmm_cfgspace_state_0__5800), + .O(com_cmm_u_cmm_cfgspace_N_55879_i) + ); + defparam com_cmm_u_cmm_cfgspace_x3gio_decodepipe_h_sel_1x_3_0_0_0_0_o3_2.INIT = 16'h0001; + LUT4 com_cmm_u_cmm_cfgspace_x3gio_decodepipe_h_sel_1x_3_0_0_0_0_o3_2 ( + .I0(cfg_dwaddr_6099[5]), + .I1(cfg_dwaddr_6099[7]), + .I2(cfg_dwaddr_6099[8]), + .I3(cfg_dwaddr_6099[9]), + .O(com_cmm_u_cmm_cfgspace_sel_1x_3_0_0_0_0_o3_2) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_00_i_0_0_0_a2_16_.INIT = 16'h0A22; + LUT4 com_cmm_u_cmm_cfgspace_low_addr_00_i_0_0_0_a2_16_ ( + .I0(com_cmm_u_cmm_cfgspace_N_59538_1), + .I1(cfg_cfg_6102[16]), + .I2(cfg_cfg_6102[512]), + .I3(com_cmm_u_cmm_cfgspace_sel_encodex[2]), + .O(com_cmm_u_cmm_cfgspace_N_58545) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_02_6_0_11_.INIT = 16'hA00C; + LUT4 com_cmm_u_cmm_cfgspace_low_addr_02_6_0_11_ ( + .I0(cfg_cfg_6102[699]), + .I1(com_cmm_bar2_reg[11]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex[1]), + .I3(com_cmm_u_cmm_cfgspace_sel_encodex[2]), + .O(com_cmm_u_cmm_cfgspace_N_4749) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_02_6_0_12_.INIT = 16'hA00C; + LUT4 com_cmm_u_cmm_cfgspace_low_addr_02_6_0_12_ ( + .I0(cfg_cfg_6102[700]), + .I1(com_cmm_bar2_reg[12]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex[1]), + .I3(com_cmm_u_cmm_cfgspace_sel_encodex[2]), + .O(com_cmm_u_cmm_cfgspace_N_4750) + ); + defparam com_cmm_u_cmm_cfgspace_decoder_sel_addr_0_0_0_0_a3_0_.INIT = 4'h8; + LUT2 com_cmm_u_cmm_cfgspace_decoder_sel_addr_0_0_0_0_a3_0_ ( + .I0(com_cmm_u_cmm_cfgspace_N_55879_i), + .I1(com_cmm_state_0[1]), + .O(com_cmm_u_cmm_cfgspace_N_61378) + ); + defparam com_cmm_u_cmm_cfgspace_x3gio_decodepipe_l_sel_x0_3_i_0_0_a3.INIT = 16'h222A; + LUT4 com_cmm_u_cmm_cfgspace_x3gio_decodepipe_l_sel_x0_3_i_0_0_a3 ( + .I0(com_cmm_u_cmm_cfgspace_N_18687_i), + .I1(com_cmm_state_0[1]), + .I2(com_cmm_u_cmm_cfgspace_state_4__5796), + .I3(com_cmm_u_cmm_cfgspace_state_5__5795), + .O(com_cmm_u_cmm_cfgspace_N_61355) + ); + defparam com_cmm_u_cmm_cfgspace_x3gio_decodepipe_h_sel_1x_3_0_0_0_0_a3.INIT = 4'h2; + LUT2 com_cmm_u_cmm_cfgspace_x3gio_decodepipe_h_sel_1x_3_0_0_0_0_a3 ( + .I0(com_cmm_u_cmm_cfgspace_N_58591_1), + .I1(com_cmm_cfg_addr[6]), + .O(com_cmm_u_cmm_cfgspace_N_61379) + ); + defparam com_cmm_u_cmm_cfgspace_x3gio_msictrl_msi_control27_0_a2_0_a2_0_a2_0_o3.INIT = 4'h8; + LUT2 com_cmm_u_cmm_cfgspace_x3gio_msictrl_msi_control27_0_a2_0_a2_0_a2_0_o3 ( + .I0(com_cmm_u_cmm_cfgspace_N_55870_i), + .I1(com_cmm_u_cmm_cfgspace_sel_4x_5772), + .O(com_cmm_u_cmm_cfgspace_N_55964_i) + ); + defparam com_cmm_u_cmm_cfgspace_x3gio_dsts_x_dsts_21_iv_0_0_0_0_o3_0_.INIT = 4'h8; + LUT2 com_cmm_u_cmm_cfgspace_x3gio_dsts_x_dsts_21_iv_0_0_0_0_o3_0_ ( + .I0(com_cmm_u_cmm_cfgspace_N_55870_i), + .I1(com_cmm_u_cmm_cfgspace_sel_6x_5777), + .O(com_cmm_u_cmm_cfgspace_N_55912_i) + ); + defparam com_cmm_u_cmm_cfgspace_x3gio_bar4_bar4_reg58_0_a2_0_a2_0_a2_0_o3.INIT = 4'h8; + LUT2 com_cmm_u_cmm_cfgspace_x3gio_bar4_bar4_reg58_0_a2_0_a2_0_a2_0_o3 ( + .I0(com_cmm_u_cmm_cfgspace_N_55870_i), + .I1(com_cmm_u_cmm_cfgspace_sel_2x_5774), + .O(com_cmm_u_cmm_cfgspace_N_55910_i) + ); + defparam com_cmm_u_cmm_cfgspace_x3gio_bar0_bar0_reg18_0_a2_0_a2_0_a2_0_o3.INIT = 4'h8; + LUT2 com_cmm_u_cmm_cfgspace_x3gio_bar0_bar0_reg18_0_a2_0_a2_0_a2_0_o3 ( + .I0(com_cmm_u_cmm_cfgspace_N_55870_i), + .I1(com_cmm_u_cmm_cfgspace_sel_1x_5775), + .O(com_cmm_u_cmm_cfgspace_N_55892_i) + ); + defparam com_cmm_u_cmm_cfgspace_x3gio_status_status_22_iv_0_0_0_0_a3_11_.INIT = 4'h8; + LUT2 com_cmm_u_cmm_cfgspace_x3gio_status_status_22_iv_0_0_0_0_a3_11_ ( + .I0(com_cmm_u_cmm_cfgspace_N_55870_i), + .I1(com_cmm_u_cmm_cfgspace_sel_0x_5776), + .O(com_cmm_u_cmm_cfgspace_N_61391) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_00_i_i_0_a2_5_19_.INIT = 4'h8; + LUT2 com_cmm_u_cmm_cfgspace_low_addr_00_i_i_0_a2_5_19_ ( + .I0(com_cmm_u_cmm_cfgspace_N_61350), + .I1(com_cmm_bar4_reg[19]), + .O(com_cmm_u_cmm_cfgspace_N_59581) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_00_i_i_0_a2_5_18_.INIT = 4'h8; + LUT2 com_cmm_u_cmm_cfgspace_low_addr_00_i_i_0_a2_5_18_ ( + .I0(com_cmm_u_cmm_cfgspace_N_61350), + .I1(com_cmm_bar4_reg[18]), + .O(com_cmm_u_cmm_cfgspace_N_59574) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_00_i_i_0_a2_5_17_.INIT = 4'h8; + LUT2 com_cmm_u_cmm_cfgspace_low_addr_00_i_i_0_a2_5_17_ ( + .I0(com_cmm_u_cmm_cfgspace_N_61350), + .I1(com_cmm_bar4_reg[17]), + .O(com_cmm_u_cmm_cfgspace_N_59567) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_00_i_0_0_0_a2_2_16_.INIT = 4'h2; + LUT2_L com_cmm_u_cmm_cfgspace_low_addr_00_i_0_0_0_a2_2_16_ ( + .I0(com_cmm_u_cmm_cfgspace_N_61330), + .I1(com_cmm_bar0_reg_16_), + .LO(com_cmm_u_cmm_cfgspace_N_58548) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_00_0_0_a2_5_21_.INIT = 4'h8; + LUT2 com_cmm_u_cmm_cfgspace_low_addr_00_0_0_a2_5_21_ ( + .I0(com_cmm_u_cmm_cfgspace_N_61350), + .I1(com_cmm_bar4_reg[21]), + .O(com_cmm_u_cmm_cfgspace_N_58005) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_01_3_0_am_0_.INIT = 8'hCA; + LUT3 com_cmm_u_cmm_cfgspace_low_addr_01_3_0_am_0_ ( + .I0(NlwRenamedSig_OI_cfg_command_0_), + .I1(com_cmm_bar5_reg[0]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex[1]), + .O(com_cmm_u_cmm_cfgspace_low_addr_01_3_0_am_0__5557) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_01_3_0_bm_0_.INIT = 8'hE2; + LUT3 com_cmm_u_cmm_cfgspace_low_addr_01_3_0_bm_0_ ( + .I0(com_cmm_pme_pmcsr[0]), + .I1(com_cmm_u_cmm_cfgspace_sel_encodex[1]), + .I2(com_cmm_u_cmm_cfgspace_x_lcap[0]), + .O(com_cmm_u_cmm_cfgspace_low_addr_01_3_0_bm_0__5556) + ); + MUXF5 com_cmm_u_cmm_cfgspace_low_addr_01_3_0_0_ ( + .I0(com_cmm_u_cmm_cfgspace_low_addr_01_3_0_am_0__5557), + .I1(com_cmm_u_cmm_cfgspace_low_addr_01_3_0_bm_0__5556), + .O(com_cmm_u_cmm_cfgspace_N_3794), + .S(com_cmm_u_cmm_cfgspace_sel_encodex_2[2]) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_01_3_0_am_10_.INIT = 8'hCA; + LUT3 com_cmm_u_cmm_cfgspace_low_addr_01_3_0_am_10_ ( + .I0(NlwRenamedSig_OI_cfg_command_10_), + .I1(com_cmm_bar5_reg[10]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex[1]), + .O(com_cmm_u_cmm_cfgspace_low_addr_01_3_0_am_10__5559) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_01_3_0_bm_10_.INIT = 8'hAC; + LUT3 com_cmm_u_cmm_cfgspace_low_addr_01_3_0_bm_10_ ( + .I0(cfg_cfg_6102[410]), + .I1(com_cmm_u_cmm_cfgspace_pme_pmcsr[10]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex_1[1]), + .O(com_cmm_u_cmm_cfgspace_low_addr_01_3_0_bm_10__5558) + ); + MUXF5 com_cmm_u_cmm_cfgspace_low_addr_01_3_0_10_ ( + .I0(com_cmm_u_cmm_cfgspace_low_addr_01_3_0_am_10__5559), + .I1(com_cmm_u_cmm_cfgspace_low_addr_01_3_0_bm_10__5558), + .O(com_cmm_u_cmm_cfgspace_N_3804), + .S(com_cmm_u_cmm_cfgspace_sel_encodex_2[2]) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_01_6_0_0_.INIT = 16'hAA0C; + LUT4_L com_cmm_u_cmm_cfgspace_low_addr_01_6_0_0_ ( + .I0(com_cmm_u_cmm_cfgspace_N_3858), + .I1(com_cmm_bar1_reg[0]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex_1[1]), + .I3(com_cmm_u_cmm_cfgspace_sel_encodex[2]), + .LO(com_cmm_u_cmm_cfgspace_N_3890) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_01_6_0_10_.INIT = 16'hAA0C; + LUT4 com_cmm_u_cmm_cfgspace_low_addr_01_6_0_10_ ( + .I0(com_cmm_u_cmm_cfgspace_N_3868), + .I1(com_cmm_bar1_reg[10]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex_1[1]), + .I3(com_cmm_u_cmm_cfgspace_sel_encodex[2]), + .O(com_cmm_u_cmm_cfgspace_N_3900) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_02_3_0_am_16_.INIT = 8'hCA; + LUT3 com_cmm_u_cmm_cfgspace_low_addr_02_3_0_am_16_ ( + .I0(cfg_cfg_6102[48]), + .I1(cfg_cfg_6102[272]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex_1[1]), + .O(com_cmm_u_cmm_cfgspace_low_addr_02_3_0_am_16__5561) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_02_3_0_bm_16_.INIT = 8'hB8; + LUT3 com_cmm_u_cmm_cfgspace_low_addr_02_3_0_bm_16_ ( + .I0(NlwRenamedSig_OI_cfg_lstatus_0_), + .I1(com_cmm_u_cmm_cfgspace_sel_encodex_1[1]), + .I2(com_cmm_msi_control_1[0]), + .O(com_cmm_u_cmm_cfgspace_low_addr_02_3_0_bm_16__5560) + ); + MUXF5 com_cmm_u_cmm_cfgspace_low_addr_02_3_0_16_ ( + .I0(com_cmm_u_cmm_cfgspace_low_addr_02_3_0_am_16__5561), + .I1(com_cmm_u_cmm_cfgspace_low_addr_02_3_0_bm_16__5560), + .O(com_cmm_u_cmm_cfgspace_N_4658), + .S(com_cmm_u_cmm_cfgspace_sel_encodex_2[2]) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_02_6_0_14_.INIT = 16'hAA0C; + LUT4 com_cmm_u_cmm_cfgspace_low_addr_02_6_0_14_ ( + .I0(com_cmm_u_cmm_cfgspace_N_4720), + .I1(com_cmm_bar2_reg[14]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex_1[1]), + .I3(com_cmm_u_cmm_cfgspace_sel_encodex[2]), + .O(com_cmm_u_cmm_cfgspace_N_4752) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_02_6_0_16_.INIT = 16'hAA0C; + LUT4 com_cmm_u_cmm_cfgspace_low_addr_02_6_0_16_ ( + .I0(com_cmm_u_cmm_cfgspace_N_4722), + .I1(com_cmm_bar2_reg[16]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex_1[1]), + .I3(com_cmm_u_cmm_cfgspace_sel_encodex[2]), + .O(com_cmm_u_cmm_cfgspace_N_4754) + ); + defparam com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_am_0_.INIT = 8'hCA; + LUT3 com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_am_0_ ( + .I0(com_cmm_u_cmm_cfgspace_low_addr_00_q[0]), + .I1(com_cmm_u_cmm_cfgspace_low_addr_02_q[0]), + .I2(com_cmm_u_cmm_cfgspace_sel_xencode[1]), + .O(com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_am[0]) + ); + defparam com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_bm_0_.INIT = 8'hCA; + LUT3 com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_bm_0_ ( + .I0(com_cmm_u_cmm_cfgspace_low_addr_01_q[0]), + .I1(com_cmm_u_cmm_cfgspace_low_addr_03_q[0]), + .I2(com_cmm_u_cmm_cfgspace_sel_xencode[1]), + .O(com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_bm[0]) + ); + MUXF5 com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_0_ ( + .I0(com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_am[0]), + .I1(com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_bm[0]), + .O(com_cmm_u_cmm_cfgspace_decoder_read_data[0]), + .S(com_cmm_u_cmm_cfgspace_sel_xencode[0]) + ); + defparam com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_am_1_.INIT = 8'hCA; + LUT3 com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_am_1_ ( + .I0(com_cmm_u_cmm_cfgspace_low_addr_00_q[1]), + .I1(com_cmm_u_cmm_cfgspace_low_addr_02_q[1]), + .I2(com_cmm_u_cmm_cfgspace_sel_xencode[1]), + .O(com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_am[1]) + ); + defparam com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_bm_1_.INIT = 8'hCA; + LUT3 com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_bm_1_ ( + .I0(com_cmm_u_cmm_cfgspace_low_addr_01_q[1]), + .I1(com_cmm_u_cmm_cfgspace_low_addr_03_q[1]), + .I2(com_cmm_u_cmm_cfgspace_sel_xencode[1]), + .O(com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_bm[1]) + ); + MUXF5 com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_1_ ( + .I0(com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_am[1]), + .I1(com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_bm[1]), + .O(com_cmm_u_cmm_cfgspace_decoder_read_data[1]), + .S(com_cmm_u_cmm_cfgspace_sel_xencode[0]) + ); + defparam com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_am_2_.INIT = 8'hCA; + LUT3 com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_am_2_ ( + .I0(com_cmm_u_cmm_cfgspace_low_addr_00_q[2]), + .I1(com_cmm_u_cmm_cfgspace_low_addr_02_q[2]), + .I2(com_cmm_u_cmm_cfgspace_sel_xencode[1]), + .O(com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_am[2]) + ); + defparam com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_bm_2_.INIT = 8'hCA; + LUT3 com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_bm_2_ ( + .I0(com_cmm_u_cmm_cfgspace_low_addr_01_q[2]), + .I1(com_cmm_u_cmm_cfgspace_low_addr_03_q[2]), + .I2(com_cmm_u_cmm_cfgspace_sel_xencode[1]), + .O(com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_bm[2]) + ); + MUXF5 com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_2_ ( + .I0(com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_am[2]), + .I1(com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_bm[2]), + .O(com_cmm_u_cmm_cfgspace_decoder_read_data[2]), + .S(com_cmm_u_cmm_cfgspace_sel_xencode[0]) + ); + defparam com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_am_3_.INIT = 8'hCA; + LUT3 com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_am_3_ ( + .I0(com_cmm_u_cmm_cfgspace_low_addr_00_q[3]), + .I1(com_cmm_u_cmm_cfgspace_low_addr_02_q[3]), + .I2(com_cmm_u_cmm_cfgspace_sel_xencode[1]), + .O(com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_am[3]) + ); + defparam com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_bm_3_.INIT = 8'hCA; + LUT3 com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_bm_3_ ( + .I0(com_cmm_u_cmm_cfgspace_low_addr_01_q[3]), + .I1(com_cmm_u_cmm_cfgspace_low_addr_03_q[3]), + .I2(com_cmm_u_cmm_cfgspace_sel_xencode[1]), + .O(com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_bm[3]) + ); + MUXF5 com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_3_ ( + .I0(com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_am[3]), + .I1(com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_bm[3]), + .O(com_cmm_u_cmm_cfgspace_decoder_read_data[3]), + .S(com_cmm_u_cmm_cfgspace_sel_xencode[0]) + ); + defparam com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_am_4_.INIT = 8'hCA; + LUT3 com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_am_4_ ( + .I0(com_cmm_u_cmm_cfgspace_low_addr_00_q[4]), + .I1(com_cmm_u_cmm_cfgspace_low_addr_02_q[4]), + .I2(com_cmm_u_cmm_cfgspace_sel_xencode[1]), + .O(com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_am[4]) + ); + defparam com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_bm_4_.INIT = 8'hCA; + LUT3 com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_bm_4_ ( + .I0(com_cmm_u_cmm_cfgspace_low_addr_01_q[4]), + .I1(com_cmm_u_cmm_cfgspace_low_addr_03_q[4]), + .I2(com_cmm_u_cmm_cfgspace_sel_xencode[1]), + .O(com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_bm[4]) + ); + MUXF5 com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_4_ ( + .I0(com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_am[4]), + .I1(com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_bm[4]), + .O(com_cmm_u_cmm_cfgspace_decoder_read_data[4]), + .S(com_cmm_u_cmm_cfgspace_sel_xencode[0]) + ); + defparam com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_am_5_.INIT = 8'hCA; + LUT3 com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_am_5_ ( + .I0(com_cmm_u_cmm_cfgspace_low_addr_00_q[5]), + .I1(com_cmm_u_cmm_cfgspace_low_addr_02_q[5]), + .I2(com_cmm_u_cmm_cfgspace_sel_xencode[1]), + .O(com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_am[5]) + ); + defparam com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_bm_5_.INIT = 8'hCA; + LUT3 com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_bm_5_ ( + .I0(com_cmm_u_cmm_cfgspace_low_addr_01_q[5]), + .I1(com_cmm_u_cmm_cfgspace_low_addr_03_q[5]), + .I2(com_cmm_u_cmm_cfgspace_sel_xencode[1]), + .O(com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_bm[5]) + ); + MUXF5 com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_5_ ( + .I0(com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_am[5]), + .I1(com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_bm[5]), + .O(com_cmm_u_cmm_cfgspace_decoder_read_data[5]), + .S(com_cmm_u_cmm_cfgspace_sel_xencode[0]) + ); + defparam com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_am_6_.INIT = 8'hCA; + LUT3 com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_am_6_ ( + .I0(com_cmm_u_cmm_cfgspace_low_addr_00_q[6]), + .I1(com_cmm_u_cmm_cfgspace_low_addr_02_q[6]), + .I2(com_cmm_u_cmm_cfgspace_sel_xencode[1]), + .O(com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_am[6]) + ); + defparam com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_bm_6_.INIT = 8'hCA; + LUT3 com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_bm_6_ ( + .I0(com_cmm_u_cmm_cfgspace_low_addr_01_q[6]), + .I1(com_cmm_u_cmm_cfgspace_low_addr_03_q[6]), + .I2(com_cmm_u_cmm_cfgspace_sel_xencode[1]), + .O(com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_bm[6]) + ); + MUXF5 com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_6_ ( + .I0(com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_am[6]), + .I1(com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_bm[6]), + .O(com_cmm_u_cmm_cfgspace_decoder_read_data[6]), + .S(com_cmm_u_cmm_cfgspace_sel_xencode[0]) + ); + defparam com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_am_7_.INIT = 8'hCA; + LUT3 com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_am_7_ ( + .I0(com_cmm_u_cmm_cfgspace_low_addr_00_q[7]), + .I1(com_cmm_u_cmm_cfgspace_low_addr_02_q[7]), + .I2(com_cmm_u_cmm_cfgspace_sel_xencode[1]), + .O(com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_am[7]) + ); + defparam com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_bm_7_.INIT = 8'hCA; + LUT3 com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_bm_7_ ( + .I0(com_cmm_u_cmm_cfgspace_low_addr_01_q[7]), + .I1(com_cmm_u_cmm_cfgspace_low_addr_03_q[7]), + .I2(com_cmm_u_cmm_cfgspace_sel_xencode[1]), + .O(com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_bm[7]) + ); + MUXF5 com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_7_ ( + .I0(com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_am[7]), + .I1(com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_bm[7]), + .O(com_cmm_u_cmm_cfgspace_decoder_read_data[7]), + .S(com_cmm_u_cmm_cfgspace_sel_xencode[0]) + ); + defparam com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_am_8_.INIT = 8'hCA; + LUT3 com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_am_8_ ( + .I0(com_cmm_u_cmm_cfgspace_low_addr_00_q[8]), + .I1(com_cmm_u_cmm_cfgspace_low_addr_02_q[8]), + .I2(com_cmm_u_cmm_cfgspace_sel_xencode[1]), + .O(com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_am[8]) + ); + defparam com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_bm_8_.INIT = 8'hCA; + LUT3 com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_bm_8_ ( + .I0(com_cmm_u_cmm_cfgspace_low_addr_01_q[8]), + .I1(com_cmm_u_cmm_cfgspace_low_addr_03_q[8]), + .I2(com_cmm_u_cmm_cfgspace_sel_xencode[1]), + .O(com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_bm[8]) + ); + MUXF5 com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_8_ ( + .I0(com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_am[8]), + .I1(com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_bm[8]), + .O(com_cmm_u_cmm_cfgspace_decoder_read_data[8]), + .S(com_cmm_u_cmm_cfgspace_sel_xencode[0]) + ); + defparam com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_am_9_.INIT = 8'hCA; + LUT3 com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_am_9_ ( + .I0(com_cmm_u_cmm_cfgspace_low_addr_00_q[9]), + .I1(com_cmm_u_cmm_cfgspace_low_addr_02_q[9]), + .I2(com_cmm_u_cmm_cfgspace_sel_xencode[1]), + .O(com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_am[9]) + ); + defparam com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_bm_9_.INIT = 8'hCA; + LUT3 com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_bm_9_ ( + .I0(com_cmm_u_cmm_cfgspace_low_addr_01_q[9]), + .I1(com_cmm_u_cmm_cfgspace_low_addr_03_q[9]), + .I2(com_cmm_u_cmm_cfgspace_sel_xencode[1]), + .O(com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_bm[9]) + ); + MUXF5 com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_9_ ( + .I0(com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_am[9]), + .I1(com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_bm[9]), + .O(com_cmm_u_cmm_cfgspace_decoder_read_data[9]), + .S(com_cmm_u_cmm_cfgspace_sel_xencode[0]) + ); + defparam com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_am_10_.INIT = 8'hCA; + LUT3 com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_am_10_ ( + .I0(com_cmm_u_cmm_cfgspace_low_addr_00_q[10]), + .I1(com_cmm_u_cmm_cfgspace_low_addr_02_q[10]), + .I2(com_cmm_u_cmm_cfgspace_sel_xencode[1]), + .O(com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_am[10]) + ); + defparam com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_bm_10_.INIT = 8'hCA; + LUT3 com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_bm_10_ ( + .I0(com_cmm_u_cmm_cfgspace_low_addr_01_q[10]), + .I1(com_cmm_u_cmm_cfgspace_low_addr_03_q[10]), + .I2(com_cmm_u_cmm_cfgspace_sel_xencode[1]), + .O(com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_bm[10]) + ); + MUXF5 com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_10_ ( + .I0(com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_am[10]), + .I1(com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_bm[10]), + .O(com_cmm_u_cmm_cfgspace_decoder_read_data[10]), + .S(com_cmm_u_cmm_cfgspace_sel_xencode[0]) + ); + defparam com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_am_11_.INIT = 8'hCA; + LUT3 com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_am_11_ ( + .I0(com_cmm_u_cmm_cfgspace_low_addr_00_q[11]), + .I1(com_cmm_u_cmm_cfgspace_low_addr_02_q[11]), + .I2(com_cmm_u_cmm_cfgspace_sel_xencode[1]), + .O(com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_am[11]) + ); + defparam com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_bm_11_.INIT = 8'hCA; + LUT3 com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_bm_11_ ( + .I0(com_cmm_u_cmm_cfgspace_low_addr_01_q[11]), + .I1(com_cmm_u_cmm_cfgspace_low_addr_03_q[11]), + .I2(com_cmm_u_cmm_cfgspace_sel_xencode[1]), + .O(com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_bm[11]) + ); + MUXF5 com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_11_ ( + .I0(com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_am[11]), + .I1(com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_bm[11]), + .O(com_cmm_u_cmm_cfgspace_decoder_read_data[11]), + .S(com_cmm_u_cmm_cfgspace_sel_xencode[0]) + ); + defparam com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_am_12_.INIT = 8'hCA; + LUT3 com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_am_12_ ( + .I0(com_cmm_u_cmm_cfgspace_low_addr_00_q[12]), + .I1(com_cmm_u_cmm_cfgspace_low_addr_02_q[12]), + .I2(com_cmm_u_cmm_cfgspace_sel_xencode[1]), + .O(com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_am[12]) + ); + defparam com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_bm_12_.INIT = 8'hCA; + LUT3 com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_bm_12_ ( + .I0(com_cmm_u_cmm_cfgspace_low_addr_01_q[12]), + .I1(com_cmm_u_cmm_cfgspace_low_addr_03_q[12]), + .I2(com_cmm_u_cmm_cfgspace_sel_xencode[1]), + .O(com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_bm[12]) + ); + MUXF5 com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_12_ ( + .I0(com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_am[12]), + .I1(com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_bm[12]), + .O(com_cmm_u_cmm_cfgspace_decoder_read_data[12]), + .S(com_cmm_u_cmm_cfgspace_sel_xencode[0]) + ); + defparam com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_am_13_.INIT = 8'hCA; + LUT3 com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_am_13_ ( + .I0(com_cmm_u_cmm_cfgspace_low_addr_00_q[13]), + .I1(com_cmm_u_cmm_cfgspace_low_addr_02_q[13]), + .I2(com_cmm_u_cmm_cfgspace_sel_xencode[1]), + .O(com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_am[13]) + ); + defparam com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_bm_13_.INIT = 8'hCA; + LUT3 com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_bm_13_ ( + .I0(com_cmm_u_cmm_cfgspace_low_addr_01_q[13]), + .I1(com_cmm_u_cmm_cfgspace_low_addr_03_q[13]), + .I2(com_cmm_u_cmm_cfgspace_sel_xencode[1]), + .O(com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_bm[13]) + ); + MUXF5 com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_13_ ( + .I0(com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_am[13]), + .I1(com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_bm[13]), + .O(com_cmm_u_cmm_cfgspace_decoder_read_data[13]), + .S(com_cmm_u_cmm_cfgspace_sel_xencode[0]) + ); + defparam com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_am_14_.INIT = 8'hCA; + LUT3 com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_am_14_ ( + .I0(com_cmm_u_cmm_cfgspace_low_addr_00_q[14]), + .I1(com_cmm_u_cmm_cfgspace_low_addr_02_q[14]), + .I2(com_cmm_u_cmm_cfgspace_sel_xencode[1]), + .O(com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_am[14]) + ); + defparam com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_bm_14_.INIT = 8'hCA; + LUT3 com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_bm_14_ ( + .I0(com_cmm_u_cmm_cfgspace_low_addr_01_q[14]), + .I1(com_cmm_u_cmm_cfgspace_low_addr_03_q[14]), + .I2(com_cmm_u_cmm_cfgspace_sel_xencode[1]), + .O(com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_bm[14]) + ); + MUXF5 com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_14_ ( + .I0(com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_am[14]), + .I1(com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_bm[14]), + .O(com_cmm_u_cmm_cfgspace_decoder_read_data[14]), + .S(com_cmm_u_cmm_cfgspace_sel_xencode[0]) + ); + defparam com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_am_15_.INIT = 8'hCA; + LUT3 com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_am_15_ ( + .I0(com_cmm_u_cmm_cfgspace_low_addr_00_q[15]), + .I1(com_cmm_u_cmm_cfgspace_low_addr_02_q[15]), + .I2(com_cmm_u_cmm_cfgspace_sel_xencode[1]), + .O(com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_am[15]) + ); + defparam com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_bm_15_.INIT = 8'hCA; + LUT3 com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_bm_15_ ( + .I0(com_cmm_u_cmm_cfgspace_low_addr_01_q[15]), + .I1(com_cmm_u_cmm_cfgspace_low_addr_03_q[15]), + .I2(com_cmm_u_cmm_cfgspace_sel_xencode[1]), + .O(com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_bm[15]) + ); + MUXF5 com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_15_ ( + .I0(com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_am[15]), + .I1(com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_bm[15]), + .O(com_cmm_u_cmm_cfgspace_decoder_read_data[15]), + .S(com_cmm_u_cmm_cfgspace_sel_xencode[0]) + ); + defparam com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_am_16_.INIT = 8'hCA; + LUT3 com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_am_16_ ( + .I0(com_cmm_u_cmm_cfgspace_low_addr_00_q[16]), + .I1(com_cmm_u_cmm_cfgspace_low_addr_02_q[16]), + .I2(com_cmm_u_cmm_cfgspace_sel_xencode[1]), + .O(com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_am[16]) + ); + defparam com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_bm_16_.INIT = 8'hCA; + LUT3 com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_bm_16_ ( + .I0(com_cmm_u_cmm_cfgspace_low_addr_01_q[16]), + .I1(com_cmm_u_cmm_cfgspace_low_addr_03_q[16]), + .I2(com_cmm_u_cmm_cfgspace_sel_xencode[1]), + .O(com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_bm[16]) + ); + MUXF5 com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_16_ ( + .I0(com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_am[16]), + .I1(com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_bm[16]), + .O(com_cmm_u_cmm_cfgspace_decoder_read_data[16]), + .S(com_cmm_u_cmm_cfgspace_sel_xencode[0]) + ); + defparam com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_am_17_.INIT = 8'hCA; + LUT3 com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_am_17_ ( + .I0(com_cmm_u_cmm_cfgspace_low_addr_00_q[17]), + .I1(com_cmm_u_cmm_cfgspace_low_addr_02_q[17]), + .I2(com_cmm_u_cmm_cfgspace_sel_xencode[1]), + .O(com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_am[17]) + ); + defparam com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_bm_17_.INIT = 8'hCA; + LUT3 com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_bm_17_ ( + .I0(com_cmm_u_cmm_cfgspace_low_addr_01_q[17]), + .I1(com_cmm_u_cmm_cfgspace_low_addr_03_q[17]), + .I2(com_cmm_u_cmm_cfgspace_sel_xencode[1]), + .O(com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_bm[17]) + ); + MUXF5 com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_17_ ( + .I0(com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_am[17]), + .I1(com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_bm[17]), + .O(com_cmm_u_cmm_cfgspace_decoder_read_data[17]), + .S(com_cmm_u_cmm_cfgspace_sel_xencode[0]) + ); + defparam com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_am_18_.INIT = 8'hCA; + LUT3 com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_am_18_ ( + .I0(com_cmm_u_cmm_cfgspace_low_addr_00_q[18]), + .I1(com_cmm_u_cmm_cfgspace_low_addr_02_q[18]), + .I2(com_cmm_u_cmm_cfgspace_sel_xencode[1]), + .O(com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_am[18]) + ); + defparam com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_bm_18_.INIT = 8'hCA; + LUT3 com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_bm_18_ ( + .I0(com_cmm_u_cmm_cfgspace_low_addr_01_q[18]), + .I1(com_cmm_u_cmm_cfgspace_low_addr_03_q[18]), + .I2(com_cmm_u_cmm_cfgspace_sel_xencode[1]), + .O(com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_bm[18]) + ); + MUXF5 com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_18_ ( + .I0(com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_am[18]), + .I1(com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_bm[18]), + .O(com_cmm_u_cmm_cfgspace_decoder_read_data[18]), + .S(com_cmm_u_cmm_cfgspace_sel_xencode[0]) + ); + defparam com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_am_19_.INIT = 8'hCA; + LUT3 com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_am_19_ ( + .I0(com_cmm_u_cmm_cfgspace_low_addr_00_q[19]), + .I1(com_cmm_u_cmm_cfgspace_low_addr_02_q[19]), + .I2(com_cmm_u_cmm_cfgspace_sel_xencode[1]), + .O(com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_am[19]) + ); + defparam com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_bm_19_.INIT = 8'hCA; + LUT3 com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_bm_19_ ( + .I0(com_cmm_u_cmm_cfgspace_low_addr_01_q[19]), + .I1(com_cmm_u_cmm_cfgspace_low_addr_03_q[19]), + .I2(com_cmm_u_cmm_cfgspace_sel_xencode[1]), + .O(com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_bm[19]) + ); + MUXF5 com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_19_ ( + .I0(com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_am[19]), + .I1(com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_bm[19]), + .O(com_cmm_u_cmm_cfgspace_decoder_read_data[19]), + .S(com_cmm_u_cmm_cfgspace_sel_xencode[0]) + ); + defparam com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_am_20_.INIT = 8'hCA; + LUT3 com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_am_20_ ( + .I0(com_cmm_u_cmm_cfgspace_low_addr_00_q[20]), + .I1(com_cmm_u_cmm_cfgspace_low_addr_02_q[20]), + .I2(com_cmm_u_cmm_cfgspace_sel_xencode[1]), + .O(com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_am[20]) + ); + defparam com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_bm_20_.INIT = 8'hCA; + LUT3 com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_bm_20_ ( + .I0(com_cmm_u_cmm_cfgspace_low_addr_01_q[20]), + .I1(com_cmm_u_cmm_cfgspace_low_addr_03_q[20]), + .I2(com_cmm_u_cmm_cfgspace_sel_xencode[1]), + .O(com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_bm[20]) + ); + MUXF5 com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_20_ ( + .I0(com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_am[20]), + .I1(com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_bm[20]), + .O(com_cmm_u_cmm_cfgspace_decoder_read_data[20]), + .S(com_cmm_u_cmm_cfgspace_sel_xencode[0]) + ); + defparam com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_am_21_.INIT = 8'hCA; + LUT3 com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_am_21_ ( + .I0(com_cmm_u_cmm_cfgspace_low_addr_00_q[21]), + .I1(com_cmm_u_cmm_cfgspace_low_addr_02_q[21]), + .I2(com_cmm_u_cmm_cfgspace_sel_xencode[1]), + .O(com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_am[21]) + ); + defparam com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_bm_21_.INIT = 8'hCA; + LUT3 com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_bm_21_ ( + .I0(com_cmm_u_cmm_cfgspace_low_addr_01_q[21]), + .I1(com_cmm_u_cmm_cfgspace_low_addr_03_q[21]), + .I2(com_cmm_u_cmm_cfgspace_sel_xencode[1]), + .O(com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_bm[21]) + ); + MUXF5 com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_21_ ( + .I0(com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_am[21]), + .I1(com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_bm[21]), + .O(com_cmm_u_cmm_cfgspace_decoder_read_data[21]), + .S(com_cmm_u_cmm_cfgspace_sel_xencode[0]) + ); + defparam com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_am_22_.INIT = 8'hCA; + LUT3 com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_am_22_ ( + .I0(com_cmm_u_cmm_cfgspace_low_addr_00_q[22]), + .I1(com_cmm_u_cmm_cfgspace_low_addr_02_q[22]), + .I2(com_cmm_u_cmm_cfgspace_sel_xencode[1]), + .O(com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_am[22]) + ); + defparam com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_bm_22_.INIT = 8'hCA; + LUT3 com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_bm_22_ ( + .I0(com_cmm_u_cmm_cfgspace_low_addr_01_q[22]), + .I1(com_cmm_u_cmm_cfgspace_low_addr_03_q[22]), + .I2(com_cmm_u_cmm_cfgspace_sel_xencode[1]), + .O(com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_bm[22]) + ); + MUXF5 com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_22_ ( + .I0(com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_am[22]), + .I1(com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_bm[22]), + .O(com_cmm_u_cmm_cfgspace_decoder_read_data[22]), + .S(com_cmm_u_cmm_cfgspace_sel_xencode[0]) + ); + defparam com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_am_23_.INIT = 8'hCA; + LUT3 com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_am_23_ ( + .I0(com_cmm_u_cmm_cfgspace_low_addr_00_q[23]), + .I1(com_cmm_u_cmm_cfgspace_low_addr_02_q[23]), + .I2(com_cmm_u_cmm_cfgspace_sel_xencode[1]), + .O(com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_am[23]) + ); + defparam com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_bm_23_.INIT = 8'hCA; + LUT3 com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_bm_23_ ( + .I0(com_cmm_u_cmm_cfgspace_low_addr_01_q[23]), + .I1(com_cmm_u_cmm_cfgspace_low_addr_03_q[23]), + .I2(com_cmm_u_cmm_cfgspace_sel_xencode[1]), + .O(com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_bm[23]) + ); + MUXF5 com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_23_ ( + .I0(com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_am[23]), + .I1(com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_bm[23]), + .O(com_cmm_u_cmm_cfgspace_decoder_read_data[23]), + .S(com_cmm_u_cmm_cfgspace_sel_xencode[0]) + ); + defparam com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_am_24_.INIT = 8'hCA; + LUT3 com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_am_24_ ( + .I0(com_cmm_u_cmm_cfgspace_low_addr_00_q[24]), + .I1(com_cmm_u_cmm_cfgspace_low_addr_02_q[24]), + .I2(com_cmm_u_cmm_cfgspace_sel_xencode[1]), + .O(com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_am[24]) + ); + defparam com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_bm_24_.INIT = 8'hCA; + LUT3 com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_bm_24_ ( + .I0(com_cmm_u_cmm_cfgspace_low_addr_01_q[24]), + .I1(com_cmm_u_cmm_cfgspace_low_addr_03_q[24]), + .I2(com_cmm_u_cmm_cfgspace_sel_xencode[1]), + .O(com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_bm[24]) + ); + MUXF5 com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_24_ ( + .I0(com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_am[24]), + .I1(com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_bm[24]), + .O(com_cmm_u_cmm_cfgspace_decoder_read_data[24]), + .S(com_cmm_u_cmm_cfgspace_sel_xencode[0]) + ); + defparam com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_am_26_.INIT = 8'hCA; + LUT3 com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_am_26_ ( + .I0(com_cmm_u_cmm_cfgspace_low_addr_00_q[26]), + .I1(com_cmm_u_cmm_cfgspace_low_addr_02_q[26]), + .I2(com_cmm_u_cmm_cfgspace_sel_xencode[1]), + .O(com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_am[26]) + ); + defparam com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_bm_26_.INIT = 8'hCA; + LUT3 com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_bm_26_ ( + .I0(com_cmm_u_cmm_cfgspace_low_addr_01_q[26]), + .I1(com_cmm_u_cmm_cfgspace_low_addr_03_q[26]), + .I2(com_cmm_u_cmm_cfgspace_sel_xencode[1]), + .O(com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_bm[26]) + ); + MUXF5 com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_26_ ( + .I0(com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_am[26]), + .I1(com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_bm[26]), + .O(com_cmm_u_cmm_cfgspace_decoder_read_data[26]), + .S(com_cmm_u_cmm_cfgspace_sel_xencode[0]) + ); + defparam com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_am_27_.INIT = 8'hCA; + LUT3 com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_am_27_ ( + .I0(com_cmm_u_cmm_cfgspace_low_addr_00_q[27]), + .I1(com_cmm_u_cmm_cfgspace_low_addr_02_q[27]), + .I2(com_cmm_u_cmm_cfgspace_sel_xencode[1]), + .O(com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_am[27]) + ); + defparam com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_bm_27_.INIT = 8'hCA; + LUT3 com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_bm_27_ ( + .I0(com_cmm_u_cmm_cfgspace_low_addr_01_q[27]), + .I1(com_cmm_u_cmm_cfgspace_low_addr_03_q[27]), + .I2(com_cmm_u_cmm_cfgspace_sel_xencode[1]), + .O(com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_bm[27]) + ); + MUXF5 com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_27_ ( + .I0(com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_am[27]), + .I1(com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_bm[27]), + .O(com_cmm_u_cmm_cfgspace_decoder_read_data[27]), + .S(com_cmm_u_cmm_cfgspace_sel_xencode[0]) + ); + defparam com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_am_28_.INIT = 8'hCA; + LUT3 com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_am_28_ ( + .I0(com_cmm_u_cmm_cfgspace_low_addr_00_q[28]), + .I1(com_cmm_u_cmm_cfgspace_low_addr_02_q[28]), + .I2(com_cmm_u_cmm_cfgspace_sel_xencode[1]), + .O(com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_am[28]) + ); + defparam com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_bm_28_.INIT = 8'hCA; + LUT3 com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_bm_28_ ( + .I0(com_cmm_u_cmm_cfgspace_low_addr_01_q[28]), + .I1(com_cmm_u_cmm_cfgspace_low_addr_03_q[28]), + .I2(com_cmm_u_cmm_cfgspace_sel_xencode[1]), + .O(com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_bm[28]) + ); + MUXF5 com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_28_ ( + .I0(com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_am[28]), + .I1(com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_bm[28]), + .O(com_cmm_u_cmm_cfgspace_decoder_read_data[28]), + .S(com_cmm_u_cmm_cfgspace_sel_xencode[0]) + ); + defparam com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_am_29_.INIT = 8'hCA; + LUT3 com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_am_29_ ( + .I0(com_cmm_u_cmm_cfgspace_low_addr_00_q[29]), + .I1(com_cmm_u_cmm_cfgspace_low_addr_02_q[29]), + .I2(com_cmm_u_cmm_cfgspace_sel_xencode[1]), + .O(com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_am[29]) + ); + defparam com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_bm_29_.INIT = 8'hCA; + LUT3 com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_bm_29_ ( + .I0(com_cmm_u_cmm_cfgspace_low_addr_01_q[29]), + .I1(com_cmm_u_cmm_cfgspace_low_addr_03_q[29]), + .I2(com_cmm_u_cmm_cfgspace_sel_xencode[1]), + .O(com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_bm[29]) + ); + MUXF5 com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_29_ ( + .I0(com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_am[29]), + .I1(com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_bm[29]), + .O(com_cmm_u_cmm_cfgspace_decoder_read_data[29]), + .S(com_cmm_u_cmm_cfgspace_sel_xencode[0]) + ); + defparam com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_am_30_.INIT = 8'hCA; + LUT3 com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_am_30_ ( + .I0(com_cmm_u_cmm_cfgspace_low_addr_00_q[30]), + .I1(com_cmm_u_cmm_cfgspace_low_addr_02_q[30]), + .I2(com_cmm_u_cmm_cfgspace_sel_xencode[1]), + .O(com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_am[30]) + ); + defparam com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_bm_30_.INIT = 8'hCA; + LUT3 com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_bm_30_ ( + .I0(com_cmm_u_cmm_cfgspace_low_addr_01_q[30]), + .I1(com_cmm_u_cmm_cfgspace_low_addr_03_q[30]), + .I2(com_cmm_u_cmm_cfgspace_sel_xencode[1]), + .O(com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_bm[30]) + ); + MUXF5 com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_30_ ( + .I0(com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_am[30]), + .I1(com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_bm[30]), + .O(com_cmm_u_cmm_cfgspace_decoder_read_data[30]), + .S(com_cmm_u_cmm_cfgspace_sel_xencode[0]) + ); + defparam com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_am_31_.INIT = 8'hCA; + LUT3 com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_am_31_ ( + .I0(com_cmm_u_cmm_cfgspace_low_addr_00_q[31]), + .I1(com_cmm_u_cmm_cfgspace_low_addr_02_q[31]), + .I2(com_cmm_u_cmm_cfgspace_sel_xencode[1]), + .O(com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_am[31]) + ); + defparam com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_bm_31_.INIT = 8'hCA; + LUT3 com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_bm_31_ ( + .I0(com_cmm_u_cmm_cfgspace_low_addr_01_q[31]), + .I1(com_cmm_u_cmm_cfgspace_low_addr_03_q[31]), + .I2(com_cmm_u_cmm_cfgspace_sel_xencode[1]), + .O(com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_bm[31]) + ); + MUXF5 com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_31_ ( + .I0(com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_am[31]), + .I1(com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_bm[31]), + .O(com_cmm_u_cmm_cfgspace_decoder_read_data[31]), + .S(com_cmm_u_cmm_cfgspace_sel_xencode[0]) + ); + defparam com_cmm_u_cmm_cfgspace_data_scale_5_i_m4_i_m3_0_am_0_.INIT = 8'hCA; + LUT3 com_cmm_u_cmm_cfgspace_data_scale_5_i_m4_i_m3_0_am_0_ ( + .I0(cfg_cfg_6102[568]), + .I1(cfg_cfg_6102[632]), + .I2(com_cmm_u_cmm_cfgspace_pme_pmcsr[11]), + .O(com_cmm_u_cmm_cfgspace_data_scale_5_i_m4_i_m3_0_am[0]) + ); + defparam com_cmm_u_cmm_cfgspace_data_scale_5_i_m4_i_m3_0_bm_0_.INIT = 8'hCA; + LUT3 com_cmm_u_cmm_cfgspace_data_scale_5_i_m4_i_m3_0_bm_0_ ( + .I0(cfg_cfg_6102[584]), + .I1(cfg_cfg_6102[648]), + .I2(com_cmm_u_cmm_cfgspace_pme_pmcsr[11]), + .O(com_cmm_u_cmm_cfgspace_data_scale_5_i_m4_i_m3_0_bm[0]) + ); + MUXF5 com_cmm_u_cmm_cfgspace_data_scale_5_i_m4_i_m3_0_0_ ( + .I0(com_cmm_u_cmm_cfgspace_data_scale_5_i_m4_i_m3_0_am[0]), + .I1(com_cmm_u_cmm_cfgspace_data_scale_5_i_m4_i_m3_0_bm[0]), + .O(com_cmm_u_cmm_cfgspace_N_63538), + .S(com_cmm_u_cmm_cfgspace_pme_pmcsr[9]) + ); + defparam com_cmm_u_cmm_cfgspace_data_scale_5_i_m4_i_m3_0_am_1_.INIT = 8'hCA; + LUT3 com_cmm_u_cmm_cfgspace_data_scale_5_i_m4_i_m3_0_am_1_ ( + .I0(cfg_cfg_6102[569]), + .I1(cfg_cfg_6102[633]), + .I2(com_cmm_u_cmm_cfgspace_pme_pmcsr[11]), + .O(com_cmm_u_cmm_cfgspace_data_scale_5_i_m4_i_m3_0_am[1]) + ); + defparam com_cmm_u_cmm_cfgspace_data_scale_5_i_m4_i_m3_0_bm_1_.INIT = 8'hCA; + LUT3 com_cmm_u_cmm_cfgspace_data_scale_5_i_m4_i_m3_0_bm_1_ ( + .I0(cfg_cfg_6102[585]), + .I1(cfg_cfg_6102[649]), + .I2(com_cmm_u_cmm_cfgspace_pme_pmcsr[11]), + .O(com_cmm_u_cmm_cfgspace_data_scale_5_i_m4_i_m3_0_bm[1]) + ); + MUXF5 com_cmm_u_cmm_cfgspace_data_scale_5_i_m4_i_m3_0_1_ ( + .I0(com_cmm_u_cmm_cfgspace_data_scale_5_i_m4_i_m3_0_am[1]), + .I1(com_cmm_u_cmm_cfgspace_data_scale_5_i_m4_i_m3_0_bm[1]), + .O(com_cmm_u_cmm_cfgspace_N_63539), + .S(com_cmm_u_cmm_cfgspace_pme_pmcsr[9]) + ); + defparam com_cmm_u_cmm_cfgspace_pme_data_5_i_m4_i_m3_0_am_0_.INIT = 8'hCA; + LUT3 com_cmm_u_cmm_cfgspace_pme_data_5_i_m4_i_m3_0_am_0_ ( + .I0(cfg_cfg_6102[560]), + .I1(cfg_cfg_6102[624]), + .I2(com_cmm_u_cmm_cfgspace_pme_pmcsr[11]), + .O(com_cmm_u_cmm_cfgspace_pme_data_5_i_m4_i_m3_0_am[0]) + ); + defparam com_cmm_u_cmm_cfgspace_pme_data_5_i_m4_i_m3_0_bm_0_.INIT = 8'hCA; + LUT3 com_cmm_u_cmm_cfgspace_pme_data_5_i_m4_i_m3_0_bm_0_ ( + .I0(cfg_cfg_6102[576]), + .I1(cfg_cfg_6102[640]), + .I2(com_cmm_u_cmm_cfgspace_pme_pmcsr[11]), + .O(com_cmm_u_cmm_cfgspace_pme_data_5_i_m4_i_m3_0_bm[0]) + ); + MUXF5 com_cmm_u_cmm_cfgspace_pme_data_5_i_m4_i_m3_0_0_ ( + .I0(com_cmm_u_cmm_cfgspace_pme_data_5_i_m4_i_m3_0_am[0]), + .I1(com_cmm_u_cmm_cfgspace_pme_data_5_i_m4_i_m3_0_bm[0]), + .O(com_cmm_u_cmm_cfgspace_N_63556), + .S(com_cmm_u_cmm_cfgspace_pme_pmcsr[9]) + ); + defparam com_cmm_u_cmm_cfgspace_pme_data_5_i_m4_i_m3_0_am_1_.INIT = 8'hCA; + LUT3 com_cmm_u_cmm_cfgspace_pme_data_5_i_m4_i_m3_0_am_1_ ( + .I0(cfg_cfg_6102[561]), + .I1(cfg_cfg_6102[625]), + .I2(com_cmm_u_cmm_cfgspace_pme_pmcsr[11]), + .O(com_cmm_u_cmm_cfgspace_pme_data_5_i_m4_i_m3_0_am[1]) + ); + defparam com_cmm_u_cmm_cfgspace_pme_data_5_i_m4_i_m3_0_bm_1_.INIT = 8'hCA; + LUT3 com_cmm_u_cmm_cfgspace_pme_data_5_i_m4_i_m3_0_bm_1_ ( + .I0(cfg_cfg_6102[577]), + .I1(cfg_cfg_6102[641]), + .I2(com_cmm_u_cmm_cfgspace_pme_pmcsr[11]), + .O(com_cmm_u_cmm_cfgspace_pme_data_5_i_m4_i_m3_0_bm[1]) + ); + MUXF5 com_cmm_u_cmm_cfgspace_pme_data_5_i_m4_i_m3_0_1_ ( + .I0(com_cmm_u_cmm_cfgspace_pme_data_5_i_m4_i_m3_0_am[1]), + .I1(com_cmm_u_cmm_cfgspace_pme_data_5_i_m4_i_m3_0_bm[1]), + .O(com_cmm_u_cmm_cfgspace_N_63557), + .S(com_cmm_u_cmm_cfgspace_pme_pmcsr[9]) + ); + defparam com_cmm_u_cmm_cfgspace_pme_data_5_i_m4_i_m3_0_am_2_.INIT = 8'hCA; + LUT3 com_cmm_u_cmm_cfgspace_pme_data_5_i_m4_i_m3_0_am_2_ ( + .I0(cfg_cfg_6102[562]), + .I1(cfg_cfg_6102[626]), + .I2(com_cmm_u_cmm_cfgspace_pme_pmcsr[11]), + .O(com_cmm_u_cmm_cfgspace_pme_data_5_i_m4_i_m3_0_am[2]) + ); + defparam com_cmm_u_cmm_cfgspace_pme_data_5_i_m4_i_m3_0_bm_2_.INIT = 8'hCA; + LUT3 com_cmm_u_cmm_cfgspace_pme_data_5_i_m4_i_m3_0_bm_2_ ( + .I0(cfg_cfg_6102[578]), + .I1(cfg_cfg_6102[642]), + .I2(com_cmm_u_cmm_cfgspace_pme_pmcsr[11]), + .O(com_cmm_u_cmm_cfgspace_pme_data_5_i_m4_i_m3_0_bm[2]) + ); + MUXF5 com_cmm_u_cmm_cfgspace_pme_data_5_i_m4_i_m3_0_2_ ( + .I0(com_cmm_u_cmm_cfgspace_pme_data_5_i_m4_i_m3_0_am[2]), + .I1(com_cmm_u_cmm_cfgspace_pme_data_5_i_m4_i_m3_0_bm[2]), + .O(com_cmm_u_cmm_cfgspace_N_63558), + .S(com_cmm_u_cmm_cfgspace_pme_pmcsr[9]) + ); + defparam com_cmm_u_cmm_cfgspace_pme_data_5_i_m4_i_m3_0_am_3_.INIT = 8'hCA; + LUT3 com_cmm_u_cmm_cfgspace_pme_data_5_i_m4_i_m3_0_am_3_ ( + .I0(cfg_cfg_6102[563]), + .I1(cfg_cfg_6102[627]), + .I2(com_cmm_u_cmm_cfgspace_pme_pmcsr[11]), + .O(com_cmm_u_cmm_cfgspace_pme_data_5_i_m4_i_m3_0_am[3]) + ); + defparam com_cmm_u_cmm_cfgspace_pme_data_5_i_m4_i_m3_0_bm_3_.INIT = 8'hCA; + LUT3 com_cmm_u_cmm_cfgspace_pme_data_5_i_m4_i_m3_0_bm_3_ ( + .I0(cfg_cfg_6102[579]), + .I1(cfg_cfg_6102[643]), + .I2(com_cmm_u_cmm_cfgspace_pme_pmcsr[11]), + .O(com_cmm_u_cmm_cfgspace_pme_data_5_i_m4_i_m3_0_bm[3]) + ); + MUXF5 com_cmm_u_cmm_cfgspace_pme_data_5_i_m4_i_m3_0_3_ ( + .I0(com_cmm_u_cmm_cfgspace_pme_data_5_i_m4_i_m3_0_am[3]), + .I1(com_cmm_u_cmm_cfgspace_pme_data_5_i_m4_i_m3_0_bm[3]), + .O(com_cmm_u_cmm_cfgspace_N_63559), + .S(com_cmm_u_cmm_cfgspace_pme_pmcsr[9]) + ); + defparam com_cmm_u_cmm_cfgspace_pme_data_5_i_m4_i_m3_0_am_4_.INIT = 8'hCA; + LUT3 com_cmm_u_cmm_cfgspace_pme_data_5_i_m4_i_m3_0_am_4_ ( + .I0(cfg_cfg_6102[564]), + .I1(cfg_cfg_6102[628]), + .I2(com_cmm_u_cmm_cfgspace_pme_pmcsr[11]), + .O(com_cmm_u_cmm_cfgspace_pme_data_5_i_m4_i_m3_0_am[4]) + ); + defparam com_cmm_u_cmm_cfgspace_pme_data_5_i_m4_i_m3_0_bm_4_.INIT = 8'hCA; + LUT3 com_cmm_u_cmm_cfgspace_pme_data_5_i_m4_i_m3_0_bm_4_ ( + .I0(cfg_cfg_6102[580]), + .I1(cfg_cfg_6102[644]), + .I2(com_cmm_u_cmm_cfgspace_pme_pmcsr[11]), + .O(com_cmm_u_cmm_cfgspace_pme_data_5_i_m4_i_m3_0_bm[4]) + ); + MUXF5 com_cmm_u_cmm_cfgspace_pme_data_5_i_m4_i_m3_0_4_ ( + .I0(com_cmm_u_cmm_cfgspace_pme_data_5_i_m4_i_m3_0_am[4]), + .I1(com_cmm_u_cmm_cfgspace_pme_data_5_i_m4_i_m3_0_bm[4]), + .O(com_cmm_u_cmm_cfgspace_N_63560), + .S(com_cmm_u_cmm_cfgspace_pme_pmcsr[9]) + ); + defparam com_cmm_u_cmm_cfgspace_pme_data_5_i_m4_i_m3_0_am_5_.INIT = 8'hCA; + LUT3 com_cmm_u_cmm_cfgspace_pme_data_5_i_m4_i_m3_0_am_5_ ( + .I0(cfg_cfg_6102[565]), + .I1(cfg_cfg_6102[629]), + .I2(com_cmm_u_cmm_cfgspace_pme_pmcsr[11]), + .O(com_cmm_u_cmm_cfgspace_pme_data_5_i_m4_i_m3_0_am[5]) + ); + defparam com_cmm_u_cmm_cfgspace_pme_data_5_i_m4_i_m3_0_bm_5_.INIT = 8'hCA; + LUT3 com_cmm_u_cmm_cfgspace_pme_data_5_i_m4_i_m3_0_bm_5_ ( + .I0(cfg_cfg_6102[581]), + .I1(cfg_cfg_6102[645]), + .I2(com_cmm_u_cmm_cfgspace_pme_pmcsr[11]), + .O(com_cmm_u_cmm_cfgspace_pme_data_5_i_m4_i_m3_0_bm[5]) + ); + MUXF5 com_cmm_u_cmm_cfgspace_pme_data_5_i_m4_i_m3_0_5_ ( + .I0(com_cmm_u_cmm_cfgspace_pme_data_5_i_m4_i_m3_0_am[5]), + .I1(com_cmm_u_cmm_cfgspace_pme_data_5_i_m4_i_m3_0_bm[5]), + .O(com_cmm_u_cmm_cfgspace_N_63561), + .S(com_cmm_u_cmm_cfgspace_pme_pmcsr[9]) + ); + defparam com_cmm_u_cmm_cfgspace_pme_data_5_i_m4_i_m3_0_am_6_.INIT = 8'hCA; + LUT3 com_cmm_u_cmm_cfgspace_pme_data_5_i_m4_i_m3_0_am_6_ ( + .I0(cfg_cfg_6102[566]), + .I1(cfg_cfg_6102[630]), + .I2(com_cmm_u_cmm_cfgspace_pme_pmcsr[11]), + .O(com_cmm_u_cmm_cfgspace_pme_data_5_i_m4_i_m3_0_am[6]) + ); + defparam com_cmm_u_cmm_cfgspace_pme_data_5_i_m4_i_m3_0_bm_6_.INIT = 8'hCA; + LUT3 com_cmm_u_cmm_cfgspace_pme_data_5_i_m4_i_m3_0_bm_6_ ( + .I0(cfg_cfg_6102[582]), + .I1(cfg_cfg_6102[646]), + .I2(com_cmm_u_cmm_cfgspace_pme_pmcsr[11]), + .O(com_cmm_u_cmm_cfgspace_pme_data_5_i_m4_i_m3_0_bm[6]) + ); + MUXF5 com_cmm_u_cmm_cfgspace_pme_data_5_i_m4_i_m3_0_6_ ( + .I0(com_cmm_u_cmm_cfgspace_pme_data_5_i_m4_i_m3_0_am[6]), + .I1(com_cmm_u_cmm_cfgspace_pme_data_5_i_m4_i_m3_0_bm[6]), + .O(com_cmm_u_cmm_cfgspace_N_63562), + .S(com_cmm_u_cmm_cfgspace_pme_pmcsr[9]) + ); + defparam com_cmm_u_cmm_cfgspace_pme_data_5_i_m4_i_m3_0_am_7_.INIT = 8'hCA; + LUT3 com_cmm_u_cmm_cfgspace_pme_data_5_i_m4_i_m3_0_am_7_ ( + .I0(cfg_cfg_6102[567]), + .I1(cfg_cfg_6102[631]), + .I2(com_cmm_u_cmm_cfgspace_pme_pmcsr[11]), + .O(com_cmm_u_cmm_cfgspace_pme_data_5_i_m4_i_m3_0_am[7]) + ); + defparam com_cmm_u_cmm_cfgspace_pme_data_5_i_m4_i_m3_0_bm_7_.INIT = 8'hCA; + LUT3 com_cmm_u_cmm_cfgspace_pme_data_5_i_m4_i_m3_0_bm_7_ ( + .I0(cfg_cfg_6102[583]), + .I1(cfg_cfg_6102[647]), + .I2(com_cmm_u_cmm_cfgspace_pme_pmcsr[11]), + .O(com_cmm_u_cmm_cfgspace_pme_data_5_i_m4_i_m3_0_bm[7]) + ); + MUXF5 com_cmm_u_cmm_cfgspace_pme_data_5_i_m4_i_m3_0_7_ ( + .I0(com_cmm_u_cmm_cfgspace_pme_data_5_i_m4_i_m3_0_am[7]), + .I1(com_cmm_u_cmm_cfgspace_pme_data_5_i_m4_i_m3_0_bm[7]), + .O(com_cmm_u_cmm_cfgspace_N_63563), + .S(com_cmm_u_cmm_cfgspace_pme_pmcsr[9]) + ); + defparam com_cmm_u_cmm_cfgspace_data_scale_4_i_m4_i_m4_i_m3_0_am_0_.INIT = 8'hCA; + LUT3 com_cmm_u_cmm_cfgspace_data_scale_4_i_m4_i_m4_i_m3_0_am_0_ ( + .I0(cfg_cfg_6102[536]), + .I1(cfg_cfg_6102[552]), + .I2(com_cmm_u_cmm_cfgspace_pme_pmcsr[9]), + .O(com_cmm_u_cmm_cfgspace_data_scale_4_i_m4_i_m4_i_m3_0_am[0]) + ); + defparam com_cmm_u_cmm_cfgspace_data_scale_4_i_m4_i_m4_i_m3_0_bm_0_.INIT = 8'hCA; + LUT3 com_cmm_u_cmm_cfgspace_data_scale_4_i_m4_i_m4_i_m3_0_bm_0_ ( + .I0(cfg_cfg_6102[600]), + .I1(cfg_cfg_6102[616]), + .I2(com_cmm_u_cmm_cfgspace_pme_pmcsr[9]), + .O(com_cmm_u_cmm_cfgspace_data_scale_4_i_m4_i_m4_i_m3_0_bm[0]) + ); + MUXF5 com_cmm_u_cmm_cfgspace_data_scale_4_i_m4_i_m4_i_m3_0_0_ ( + .I0(com_cmm_u_cmm_cfgspace_data_scale_4_i_m4_i_m4_i_m3_0_am[0]), + .I1(com_cmm_u_cmm_cfgspace_data_scale_4_i_m4_i_m4_i_m3_0_bm[0]), + .O(com_cmm_u_cmm_cfgspace_N_63568), + .S(com_cmm_u_cmm_cfgspace_pme_pmcsr[11]) + ); + defparam com_cmm_u_cmm_cfgspace_data_scale_4_i_m4_i_m4_i_m3_0_am_1_.INIT = 8'hCA; + LUT3 com_cmm_u_cmm_cfgspace_data_scale_4_i_m4_i_m4_i_m3_0_am_1_ ( + .I0(cfg_cfg_6102[537]), + .I1(cfg_cfg_6102[553]), + .I2(com_cmm_u_cmm_cfgspace_pme_pmcsr[9]), + .O(com_cmm_u_cmm_cfgspace_data_scale_4_i_m4_i_m4_i_m3_0_am[1]) + ); + defparam com_cmm_u_cmm_cfgspace_data_scale_4_i_m4_i_m4_i_m3_0_bm_1_.INIT = 8'hCA; + LUT3 com_cmm_u_cmm_cfgspace_data_scale_4_i_m4_i_m4_i_m3_0_bm_1_ ( + .I0(cfg_cfg_6102[601]), + .I1(cfg_cfg_6102[617]), + .I2(com_cmm_u_cmm_cfgspace_pme_pmcsr[9]), + .O(com_cmm_u_cmm_cfgspace_data_scale_4_i_m4_i_m4_i_m3_0_bm[1]) + ); + MUXF5 com_cmm_u_cmm_cfgspace_data_scale_4_i_m4_i_m4_i_m3_0_1_ ( + .I0(com_cmm_u_cmm_cfgspace_data_scale_4_i_m4_i_m4_i_m3_0_am[1]), + .I1(com_cmm_u_cmm_cfgspace_data_scale_4_i_m4_i_m4_i_m3_0_bm[1]), + .O(com_cmm_u_cmm_cfgspace_N_63569), + .S(com_cmm_u_cmm_cfgspace_pme_pmcsr[11]) + ); + defparam com_cmm_u_cmm_cfgspace_pme_data_4_i_m4_i_m4_i_m3_0_am_0_.INIT = 8'hCA; + LUT3 com_cmm_u_cmm_cfgspace_pme_data_4_i_m4_i_m4_i_m3_0_am_0_ ( + .I0(cfg_cfg_6102[528]), + .I1(cfg_cfg_6102[544]), + .I2(com_cmm_u_cmm_cfgspace_pme_pmcsr[9]), + .O(com_cmm_u_cmm_cfgspace_pme_data_4_i_m4_i_m4_i_m3_0_am[0]) + ); + defparam com_cmm_u_cmm_cfgspace_pme_data_4_i_m4_i_m4_i_m3_0_bm_0_.INIT = 8'hCA; + LUT3 com_cmm_u_cmm_cfgspace_pme_data_4_i_m4_i_m4_i_m3_0_bm_0_ ( + .I0(cfg_cfg_6102[592]), + .I1(cfg_cfg_6102[608]), + .I2(com_cmm_u_cmm_cfgspace_pme_pmcsr[9]), + .O(com_cmm_u_cmm_cfgspace_pme_data_4_i_m4_i_m4_i_m3_0_bm[0]) + ); + MUXF5 com_cmm_u_cmm_cfgspace_pme_data_4_i_m4_i_m4_i_m3_0_0_ ( + .I0(com_cmm_u_cmm_cfgspace_pme_data_4_i_m4_i_m4_i_m3_0_am[0]), + .I1(com_cmm_u_cmm_cfgspace_pme_data_4_i_m4_i_m4_i_m3_0_bm[0]), + .O(com_cmm_u_cmm_cfgspace_N_63586), + .S(com_cmm_u_cmm_cfgspace_pme_pmcsr[11]) + ); + defparam com_cmm_u_cmm_cfgspace_pme_data_4_i_m4_i_m4_i_m3_0_am_1_.INIT = 8'hCA; + LUT3 com_cmm_u_cmm_cfgspace_pme_data_4_i_m4_i_m4_i_m3_0_am_1_ ( + .I0(cfg_cfg_6102[529]), + .I1(cfg_cfg_6102[545]), + .I2(com_cmm_u_cmm_cfgspace_pme_pmcsr[9]), + .O(com_cmm_u_cmm_cfgspace_pme_data_4_i_m4_i_m4_i_m3_0_am[1]) + ); + defparam com_cmm_u_cmm_cfgspace_pme_data_4_i_m4_i_m4_i_m3_0_bm_1_.INIT = 8'hCA; + LUT3 com_cmm_u_cmm_cfgspace_pme_data_4_i_m4_i_m4_i_m3_0_bm_1_ ( + .I0(cfg_cfg_6102[593]), + .I1(cfg_cfg_6102[609]), + .I2(com_cmm_u_cmm_cfgspace_pme_pmcsr[9]), + .O(com_cmm_u_cmm_cfgspace_pme_data_4_i_m4_i_m4_i_m3_0_bm[1]) + ); + MUXF5 com_cmm_u_cmm_cfgspace_pme_data_4_i_m4_i_m4_i_m3_0_1_ ( + .I0(com_cmm_u_cmm_cfgspace_pme_data_4_i_m4_i_m4_i_m3_0_am[1]), + .I1(com_cmm_u_cmm_cfgspace_pme_data_4_i_m4_i_m4_i_m3_0_bm[1]), + .O(com_cmm_u_cmm_cfgspace_N_63587), + .S(com_cmm_u_cmm_cfgspace_pme_pmcsr[11]) + ); + defparam com_cmm_u_cmm_cfgspace_pme_data_4_i_m4_i_m4_i_m3_0_am_2_.INIT = 8'hCA; + LUT3 com_cmm_u_cmm_cfgspace_pme_data_4_i_m4_i_m4_i_m3_0_am_2_ ( + .I0(cfg_cfg_6102[530]), + .I1(cfg_cfg_6102[546]), + .I2(com_cmm_u_cmm_cfgspace_pme_pmcsr[9]), + .O(com_cmm_u_cmm_cfgspace_pme_data_4_i_m4_i_m4_i_m3_0_am[2]) + ); + defparam com_cmm_u_cmm_cfgspace_pme_data_4_i_m4_i_m4_i_m3_0_bm_2_.INIT = 8'hCA; + LUT3 com_cmm_u_cmm_cfgspace_pme_data_4_i_m4_i_m4_i_m3_0_bm_2_ ( + .I0(cfg_cfg_6102[594]), + .I1(cfg_cfg_6102[610]), + .I2(com_cmm_u_cmm_cfgspace_pme_pmcsr[9]), + .O(com_cmm_u_cmm_cfgspace_pme_data_4_i_m4_i_m4_i_m3_0_bm[2]) + ); + MUXF5 com_cmm_u_cmm_cfgspace_pme_data_4_i_m4_i_m4_i_m3_0_2_ ( + .I0(com_cmm_u_cmm_cfgspace_pme_data_4_i_m4_i_m4_i_m3_0_am[2]), + .I1(com_cmm_u_cmm_cfgspace_pme_data_4_i_m4_i_m4_i_m3_0_bm[2]), + .O(com_cmm_u_cmm_cfgspace_N_63588), + .S(com_cmm_u_cmm_cfgspace_pme_pmcsr[11]) + ); + defparam com_cmm_u_cmm_cfgspace_pme_data_4_i_m4_i_m4_i_m3_0_am_3_.INIT = 8'hCA; + LUT3 com_cmm_u_cmm_cfgspace_pme_data_4_i_m4_i_m4_i_m3_0_am_3_ ( + .I0(cfg_cfg_6102[531]), + .I1(cfg_cfg_6102[547]), + .I2(com_cmm_u_cmm_cfgspace_pme_pmcsr[9]), + .O(com_cmm_u_cmm_cfgspace_pme_data_4_i_m4_i_m4_i_m3_0_am[3]) + ); + defparam com_cmm_u_cmm_cfgspace_pme_data_4_i_m4_i_m4_i_m3_0_bm_3_.INIT = 8'hCA; + LUT3 com_cmm_u_cmm_cfgspace_pme_data_4_i_m4_i_m4_i_m3_0_bm_3_ ( + .I0(cfg_cfg_6102[595]), + .I1(cfg_cfg_6102[611]), + .I2(com_cmm_u_cmm_cfgspace_pme_pmcsr[9]), + .O(com_cmm_u_cmm_cfgspace_pme_data_4_i_m4_i_m4_i_m3_0_bm[3]) + ); + MUXF5 com_cmm_u_cmm_cfgspace_pme_data_4_i_m4_i_m4_i_m3_0_3_ ( + .I0(com_cmm_u_cmm_cfgspace_pme_data_4_i_m4_i_m4_i_m3_0_am[3]), + .I1(com_cmm_u_cmm_cfgspace_pme_data_4_i_m4_i_m4_i_m3_0_bm[3]), + .O(com_cmm_u_cmm_cfgspace_N_63589), + .S(com_cmm_u_cmm_cfgspace_pme_pmcsr[11]) + ); + defparam com_cmm_u_cmm_cfgspace_pme_data_4_i_m4_i_m4_i_m3_0_am_4_.INIT = 8'hCA; + LUT3 com_cmm_u_cmm_cfgspace_pme_data_4_i_m4_i_m4_i_m3_0_am_4_ ( + .I0(cfg_cfg_6102[532]), + .I1(cfg_cfg_6102[548]), + .I2(com_cmm_u_cmm_cfgspace_pme_pmcsr[9]), + .O(com_cmm_u_cmm_cfgspace_pme_data_4_i_m4_i_m4_i_m3_0_am[4]) + ); + defparam com_cmm_u_cmm_cfgspace_pme_data_4_i_m4_i_m4_i_m3_0_bm_4_.INIT = 8'hCA; + LUT3 com_cmm_u_cmm_cfgspace_pme_data_4_i_m4_i_m4_i_m3_0_bm_4_ ( + .I0(cfg_cfg_6102[596]), + .I1(cfg_cfg_6102[612]), + .I2(com_cmm_u_cmm_cfgspace_pme_pmcsr[9]), + .O(com_cmm_u_cmm_cfgspace_pme_data_4_i_m4_i_m4_i_m3_0_bm[4]) + ); + MUXF5 com_cmm_u_cmm_cfgspace_pme_data_4_i_m4_i_m4_i_m3_0_4_ ( + .I0(com_cmm_u_cmm_cfgspace_pme_data_4_i_m4_i_m4_i_m3_0_am[4]), + .I1(com_cmm_u_cmm_cfgspace_pme_data_4_i_m4_i_m4_i_m3_0_bm[4]), + .O(com_cmm_u_cmm_cfgspace_N_63590), + .S(com_cmm_u_cmm_cfgspace_pme_pmcsr[11]) + ); + defparam com_cmm_u_cmm_cfgspace_pme_data_4_i_m4_i_m4_i_m3_0_am_5_.INIT = 8'hCA; + LUT3 com_cmm_u_cmm_cfgspace_pme_data_4_i_m4_i_m4_i_m3_0_am_5_ ( + .I0(cfg_cfg_6102[533]), + .I1(cfg_cfg_6102[549]), + .I2(com_cmm_u_cmm_cfgspace_pme_pmcsr[9]), + .O(com_cmm_u_cmm_cfgspace_pme_data_4_i_m4_i_m4_i_m3_0_am[5]) + ); + defparam com_cmm_u_cmm_cfgspace_pme_data_4_i_m4_i_m4_i_m3_0_bm_5_.INIT = 8'hCA; + LUT3 com_cmm_u_cmm_cfgspace_pme_data_4_i_m4_i_m4_i_m3_0_bm_5_ ( + .I0(cfg_cfg_6102[597]), + .I1(cfg_cfg_6102[613]), + .I2(com_cmm_u_cmm_cfgspace_pme_pmcsr[9]), + .O(com_cmm_u_cmm_cfgspace_pme_data_4_i_m4_i_m4_i_m3_0_bm[5]) + ); + MUXF5 com_cmm_u_cmm_cfgspace_pme_data_4_i_m4_i_m4_i_m3_0_5_ ( + .I0(com_cmm_u_cmm_cfgspace_pme_data_4_i_m4_i_m4_i_m3_0_am[5]), + .I1(com_cmm_u_cmm_cfgspace_pme_data_4_i_m4_i_m4_i_m3_0_bm[5]), + .O(com_cmm_u_cmm_cfgspace_N_63591), + .S(com_cmm_u_cmm_cfgspace_pme_pmcsr[11]) + ); + defparam com_cmm_u_cmm_cfgspace_pme_data_4_i_m4_i_m4_i_m3_0_am_6_.INIT = 8'hCA; + LUT3 com_cmm_u_cmm_cfgspace_pme_data_4_i_m4_i_m4_i_m3_0_am_6_ ( + .I0(cfg_cfg_6102[534]), + .I1(cfg_cfg_6102[550]), + .I2(com_cmm_u_cmm_cfgspace_pme_pmcsr[9]), + .O(com_cmm_u_cmm_cfgspace_pme_data_4_i_m4_i_m4_i_m3_0_am[6]) + ); + defparam com_cmm_u_cmm_cfgspace_pme_data_4_i_m4_i_m4_i_m3_0_bm_6_.INIT = 8'hCA; + LUT3 com_cmm_u_cmm_cfgspace_pme_data_4_i_m4_i_m4_i_m3_0_bm_6_ ( + .I0(cfg_cfg_6102[598]), + .I1(cfg_cfg_6102[614]), + .I2(com_cmm_u_cmm_cfgspace_pme_pmcsr[9]), + .O(com_cmm_u_cmm_cfgspace_pme_data_4_i_m4_i_m4_i_m3_0_bm[6]) + ); + MUXF5 com_cmm_u_cmm_cfgspace_pme_data_4_i_m4_i_m4_i_m3_0_6_ ( + .I0(com_cmm_u_cmm_cfgspace_pme_data_4_i_m4_i_m4_i_m3_0_am[6]), + .I1(com_cmm_u_cmm_cfgspace_pme_data_4_i_m4_i_m4_i_m3_0_bm[6]), + .O(com_cmm_u_cmm_cfgspace_N_63592), + .S(com_cmm_u_cmm_cfgspace_pme_pmcsr[11]) + ); + defparam com_cmm_u_cmm_cfgspace_pme_data_4_i_m4_i_m4_i_m3_0_am_7_.INIT = 8'hCA; + LUT3 com_cmm_u_cmm_cfgspace_pme_data_4_i_m4_i_m4_i_m3_0_am_7_ ( + .I0(cfg_cfg_6102[535]), + .I1(cfg_cfg_6102[551]), + .I2(com_cmm_u_cmm_cfgspace_pme_pmcsr[9]), + .O(com_cmm_u_cmm_cfgspace_pme_data_4_i_m4_i_m4_i_m3_0_am[7]) + ); + defparam com_cmm_u_cmm_cfgspace_pme_data_4_i_m4_i_m4_i_m3_0_bm_7_.INIT = 8'hCA; + LUT3 com_cmm_u_cmm_cfgspace_pme_data_4_i_m4_i_m4_i_m3_0_bm_7_ ( + .I0(cfg_cfg_6102[599]), + .I1(cfg_cfg_6102[615]), + .I2(com_cmm_u_cmm_cfgspace_pme_pmcsr[9]), + .O(com_cmm_u_cmm_cfgspace_pme_data_4_i_m4_i_m4_i_m3_0_bm[7]) + ); + MUXF5 com_cmm_u_cmm_cfgspace_pme_data_4_i_m4_i_m4_i_m3_0_7_ ( + .I0(com_cmm_u_cmm_cfgspace_pme_data_4_i_m4_i_m4_i_m3_0_am[7]), + .I1(com_cmm_u_cmm_cfgspace_pme_data_4_i_m4_i_m4_i_m3_0_bm[7]), + .O(com_cmm_u_cmm_cfgspace_N_63593), + .S(com_cmm_u_cmm_cfgspace_pme_pmcsr[11]) + ); + defparam com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_am_25_.INIT = 8'hCA; + LUT3 com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_am_25_ ( + .I0(com_cmm_u_cmm_cfgspace_low_addr_00_q[25]), + .I1(com_cmm_u_cmm_cfgspace_low_addr_02_q[25]), + .I2(com_cmm_u_cmm_cfgspace_sel_xencode[1]), + .O(com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_am[25]) + ); + defparam com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_bm_25_.INIT = 8'hCA; + LUT3 com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_bm_25_ ( + .I0(com_cmm_u_cmm_cfgspace_low_addr_01_q[25]), + .I1(com_cmm_u_cmm_cfgspace_low_addr_03_q[25]), + .I2(com_cmm_u_cmm_cfgspace_sel_xencode[1]), + .O(com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_bm[25]) + ); + MUXF5 com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_25_ ( + .I0(com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_am[25]), + .I1(com_cmm_u_cmm_cfgspace_decoder_read_data_3_0_bm[25]), + .O(com_cmm_u_cmm_cfgspace_decoder_read_data[25]), + .S(com_cmm_u_cmm_cfgspace_sel_xencode[0]) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_00_i_0_1_39297.INIT = 16'h3111; + LUT4_L com_cmm_u_cmm_cfgspace_low_addr_00_i_0_1_39297 ( + .I0(com_cmm_u_cmm_cfgspace_N_61347), + .I1(com_cmm_u_cmm_cfgspace_N_61371), + .I2(NlwRenamedSig_OI_cfg_dcommand[1]), + .I3(com_cmm_u_cmm_cfgspace_sel_encodex_1[1]), + .LO(com_cmm_u_cmm_cfgspace_low_addr_00_i_0_1_39297_5582) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_00_i_0_1_39298.INIT = 16'hFCAF; + LUT4 com_cmm_u_cmm_cfgspace_low_addr_00_i_0_1_39298 ( + .I0(com_cmm_bar4_reg[1]), + .I1(com_cmm_msi_haddr[1]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex_1[1]), + .I3(com_cmm_u_cmm_cfgspace_sel_encodex[2]), + .O(com_cmm_u_cmm_cfgspace_low_addr_00_i_0_1_39298_5743) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_00_i_0_24_39313.INIT = 16'hEF2F; + LUT4 com_cmm_u_cmm_cfgspace_low_addr_00_i_0_24_39313 ( + .I0(com_cmm_bar4_reg[24]), + .I1(com_cmm_u_cmm_cfgspace_sel_encodex[0]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex_1[1]), + .I3(com_cmm_xrom_reg_24_), + .O(com_cmm_u_cmm_cfgspace_low_addr_00_i_0_24_39313_5751) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_00_i_0_24_39314.INIT = 16'hCAFF; + LUT4 com_cmm_u_cmm_cfgspace_low_addr_00_i_0_24_39314 ( + .I0(cfg_cfg_6102[520]), + .I1(com_cmm_msi_haddr[24]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex[0]), + .I3(com_cmm_u_cmm_cfgspace_sel_encodex[2]), + .O(com_cmm_u_cmm_cfgspace_low_addr_00_i_0_24_39314_5815) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_00_i_0_22_39318.INIT = 16'hEF2F; + LUT4 com_cmm_u_cmm_cfgspace_low_addr_00_i_0_22_39318 ( + .I0(com_cmm_bar4_reg[22]), + .I1(com_cmm_u_cmm_cfgspace_sel_encodex[0]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex_1[1]), + .I3(com_cmm_xrom_reg_22_), + .O(com_cmm_u_cmm_cfgspace_low_addr_00_i_0_22_39318_5749) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_00_i_0_22_39319.INIT = 16'hCAFF; + LUT4 com_cmm_u_cmm_cfgspace_low_addr_00_i_0_22_39319 ( + .I0(cfg_cfg_6102[518]), + .I1(com_cmm_msi_haddr[22]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex[0]), + .I3(com_cmm_u_cmm_cfgspace_sel_encodex[2]), + .O(com_cmm_u_cmm_cfgspace_low_addr_00_i_0_22_39319_5819) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_00_i_0_20_39323.INIT = 16'hEF2F; + LUT4 com_cmm_u_cmm_cfgspace_low_addr_00_i_0_20_39323 ( + .I0(com_cmm_bar4_reg[20]), + .I1(com_cmm_u_cmm_cfgspace_sel_encodex[0]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex_1[1]), + .I3(com_cmm_xrom_reg_20_), + .O(com_cmm_u_cmm_cfgspace_low_addr_00_i_0_20_39323_5748) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_00_i_0_20_39324.INIT = 16'hCAFF; + LUT4 com_cmm_u_cmm_cfgspace_low_addr_00_i_0_20_39324 ( + .I0(cfg_cfg_6102[516]), + .I1(com_cmm_msi_haddr[20]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex[0]), + .I3(com_cmm_u_cmm_cfgspace_sel_encodex[2]), + .O(com_cmm_u_cmm_cfgspace_low_addr_00_i_0_20_39324_5821) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_00_i_0_15_39328.INIT = 16'hEF2F; + LUT4 com_cmm_u_cmm_cfgspace_low_addr_00_i_0_15_39328 ( + .I0(com_cmm_bar4_reg[15]), + .I1(com_cmm_u_cmm_cfgspace_sel_encodex[0]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex_1[1]), + .I3(com_cmm_xrom_reg_15_), + .O(com_cmm_u_cmm_cfgspace_low_addr_00_i_0_15_39328_5707) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_00_i_0_0_26_39332.INIT = 16'hEF2F; + LUT4 com_cmm_u_cmm_cfgspace_low_addr_00_i_0_0_26_39332 ( + .I0(com_cmm_bar4_reg[26]), + .I1(com_cmm_u_cmm_cfgspace_sel_encodex[0]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex_1[1]), + .I3(com_cmm_xrom_reg_26_), + .O(com_cmm_u_cmm_cfgspace_low_addr_00_i_0_0_26_39332_5753) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_00_i_0_0_26_39333.INIT = 16'hCAFF; + LUT4 com_cmm_u_cmm_cfgspace_low_addr_00_i_0_0_26_39333 ( + .I0(cfg_cfg_6102[522]), + .I1(com_cmm_msi_haddr[26]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex[0]), + .I3(com_cmm_u_cmm_cfgspace_sel_encodex[2]), + .O(com_cmm_u_cmm_cfgspace_low_addr_00_i_0_0_26_39333_5811) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_00_i_0_0_25_39337.INIT = 16'hEF2F; + LUT4 com_cmm_u_cmm_cfgspace_low_addr_00_i_0_0_25_39337 ( + .I0(com_cmm_bar4_reg[25]), + .I1(com_cmm_u_cmm_cfgspace_sel_encodex[0]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex_1[1]), + .I3(com_cmm_xrom_reg_25_), + .O(com_cmm_u_cmm_cfgspace_low_addr_00_i_0_0_25_39337_5752) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_00_i_0_0_25_39338.INIT = 16'hCAFF; + LUT4 com_cmm_u_cmm_cfgspace_low_addr_00_i_0_0_25_39338 ( + .I0(cfg_cfg_6102[521]), + .I1(com_cmm_msi_haddr[25]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex[0]), + .I3(com_cmm_u_cmm_cfgspace_sel_encodex[2]), + .O(com_cmm_u_cmm_cfgspace_low_addr_00_i_0_0_25_39338_5813) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_00_i_0_0_23_39342.INIT = 16'hEF2F; + LUT4 com_cmm_u_cmm_cfgspace_low_addr_00_i_0_0_23_39342 ( + .I0(com_cmm_bar4_reg[23]), + .I1(com_cmm_u_cmm_cfgspace_sel_encodex[0]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex_1[1]), + .I3(com_cmm_xrom_reg_23_), + .O(com_cmm_u_cmm_cfgspace_low_addr_00_i_0_0_23_39342_5750) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_00_i_0_0_23_39343.INIT = 16'hCAFF; + LUT4 com_cmm_u_cmm_cfgspace_low_addr_00_i_0_0_23_39343 ( + .I0(cfg_cfg_6102[519]), + .I1(com_cmm_msi_haddr[23]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex[0]), + .I3(com_cmm_u_cmm_cfgspace_sel_encodex[2]), + .O(com_cmm_u_cmm_cfgspace_low_addr_00_i_0_0_23_39343_5817) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_00_i_0_0_30_39347.INIT = 16'hEF2F; + LUT4 com_cmm_u_cmm_cfgspace_low_addr_00_i_0_0_30_39347 ( + .I0(com_cmm_bar4_reg[30]), + .I1(com_cmm_u_cmm_cfgspace_sel_encodex[0]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex_1[1]), + .I3(com_cmm_xrom_reg_30_), + .O(com_cmm_u_cmm_cfgspace_low_addr_00_i_0_0_30_39347_5754) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_00_i_0_0_30_39348.INIT = 16'hCAFF; + LUT4 com_cmm_u_cmm_cfgspace_low_addr_00_i_0_0_30_39348 ( + .I0(cfg_cfg_6102[526]), + .I1(com_cmm_msi_haddr[30]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex[0]), + .I3(com_cmm_u_cmm_cfgspace_sel_encodex[2]), + .O(com_cmm_u_cmm_cfgspace_low_addr_00_i_0_0_30_39348_5809) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_00_i_0_0_0_31_39352.INIT = 16'hEF2F; + LUT4 com_cmm_u_cmm_cfgspace_low_addr_00_i_0_0_0_31_39352 ( + .I0(com_cmm_bar4_reg[31]), + .I1(com_cmm_u_cmm_cfgspace_sel_encodex[0]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex_1[1]), + .I3(com_cmm_xrom_reg_31_), + .O(com_cmm_u_cmm_cfgspace_low_addr_00_i_0_0_0_31_39352_5670) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_00_i_0_0_0_28_39357.INIT = 16'hEF2F; + LUT4 com_cmm_u_cmm_cfgspace_low_addr_00_i_0_0_0_28_39357 ( + .I0(com_cmm_bar4_reg[28]), + .I1(com_cmm_u_cmm_cfgspace_sel_encodex[0]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex_1[1]), + .I3(com_cmm_xrom_reg_28_), + .O(com_cmm_u_cmm_cfgspace_low_addr_00_i_0_0_0_28_39357_5672) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_00_i_0_0_0_27_39362.INIT = 16'hEF2F; + LUT4 com_cmm_u_cmm_cfgspace_low_addr_00_i_0_0_0_27_39362 ( + .I0(com_cmm_bar4_reg[27]), + .I1(com_cmm_u_cmm_cfgspace_sel_encodex[0]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex_1[1]), + .I3(com_cmm_xrom_reg_27_), + .O(com_cmm_u_cmm_cfgspace_low_addr_00_i_0_0_0_27_39362_5674) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_00_0_0_0_0_14_.INIT = 16'h153F; + LUT4_L com_cmm_u_cmm_cfgspace_low_addr_00_0_0_0_0_14_ ( + .I0(com_cmm_u_cmm_cfgspace_N_59532_1), + .I1(com_cmm_u_cmm_cfgspace_N_59538_1), + .I2(cfg_cfg_6102[14]), + .I3(com_cmm_msi_haddr[14]), + .LO(com_cmm_u_cmm_cfgspace_low_addr_00_0_0_0_0_14__5583) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_00_0_0_0_0_0_11_.INIT = 16'h153F; + LUT4_L com_cmm_u_cmm_cfgspace_low_addr_00_0_0_0_0_0_11_ ( + .I0(com_cmm_u_cmm_cfgspace_N_59532_1), + .I1(com_cmm_u_cmm_cfgspace_N_59538_1), + .I2(cfg_cfg_6102[11]), + .I3(com_cmm_msi_haddr[11]), + .LO(com_cmm_u_cmm_cfgspace_low_addr_00_0_0_0_0_0[11]) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_02_3_0_am_11_.INIT = 8'hCA; + LUT3 com_cmm_u_cmm_cfgspace_low_addr_02_3_0_am_11_ ( + .I0(cfg_cfg_6102[43]), + .I1(cfg_cfg_6102[267]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex_1[1]), + .O(com_cmm_u_cmm_cfgspace_low_addr_02_3_0_am_11__5563) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_02_3_0_bm_11_.INIT = 8'h0D; + LUT3 com_cmm_u_cmm_cfgspace_low_addr_02_3_0_bm_11_ ( + .I0(cfg_cfg_6102[482]), + .I1(cfg_cfg_6102[486]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex_1[1]), + .O(com_cmm_u_cmm_cfgspace_low_addr_02_3_0_bm_11__5562) + ); + MUXF5 com_cmm_u_cmm_cfgspace_low_addr_02_3_0_11_ ( + .I0(com_cmm_u_cmm_cfgspace_low_addr_02_3_0_am_11__5563), + .I1(com_cmm_u_cmm_cfgspace_low_addr_02_3_0_bm_11__5562), + .O(com_cmm_u_cmm_cfgspace_N_4653), + .S(com_cmm_u_cmm_cfgspace_sel_encodex_2[2]) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_02_3_0_am_12_.INIT = 8'hCA; + LUT3 com_cmm_u_cmm_cfgspace_low_addr_02_3_0_am_12_ ( + .I0(cfg_cfg_6102[44]), + .I1(cfg_cfg_6102[268]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex_1[1]), + .O(com_cmm_u_cmm_cfgspace_low_addr_02_3_0_am_12__5565) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_02_3_0_bm_12_.INIT = 8'h0D; + LUT3 com_cmm_u_cmm_cfgspace_low_addr_02_3_0_bm_12_ ( + .I0(cfg_cfg_6102[482]), + .I1(cfg_cfg_6102[487]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex_1[1]), + .O(com_cmm_u_cmm_cfgspace_low_addr_02_3_0_bm_12__5564) + ); + MUXF5 com_cmm_u_cmm_cfgspace_low_addr_02_3_0_12_ ( + .I0(com_cmm_u_cmm_cfgspace_low_addr_02_3_0_am_12__5565), + .I1(com_cmm_u_cmm_cfgspace_low_addr_02_3_0_bm_12__5564), + .O(com_cmm_u_cmm_cfgspace_N_4654), + .S(com_cmm_u_cmm_cfgspace_sel_encodex_2[2]) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_02_3_0_am_14_.INIT = 8'hCA; + LUT3 com_cmm_u_cmm_cfgspace_low_addr_02_3_0_am_14_ ( + .I0(cfg_cfg_6102[46]), + .I1(cfg_cfg_6102[270]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex_1[1]), + .O(com_cmm_u_cmm_cfgspace_low_addr_02_3_0_am_14__5567) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_02_3_0_bm_14_.INIT = 8'h0D; + LUT3 com_cmm_u_cmm_cfgspace_low_addr_02_3_0_bm_14_ ( + .I0(cfg_cfg_6102[482]), + .I1(cfg_cfg_6102[489]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex_1[1]), + .O(com_cmm_u_cmm_cfgspace_low_addr_02_3_0_bm_14__5566) + ); + MUXF5 com_cmm_u_cmm_cfgspace_low_addr_02_3_0_14_ ( + .I0(com_cmm_u_cmm_cfgspace_low_addr_02_3_0_am_14__5567), + .I1(com_cmm_u_cmm_cfgspace_low_addr_02_3_0_bm_14__5566), + .O(com_cmm_u_cmm_cfgspace_N_4656), + .S(com_cmm_u_cmm_cfgspace_sel_encodex_2[2]) + ); + defparam com_cmm_u_cmm_cfgspace_x3gio_decodepipe_l_sel_x4_3_i_0_0_m3_0.INIT = 8'hE4; + LUT3 com_cmm_u_cmm_cfgspace_x3gio_decodepipe_l_sel_x4_3_i_0_0_m3_0 ( + .I0(com_cmm_u_cmm_cfgspace_N_55879_i), + .I1(cfg_dwaddr_6099[1]), + .I2(com_cmm_cfg_addr[1]), + .O(com_cmm_u_cmm_cfgspace_N_55900) + ); + defparam com_cmm_u_cmm_cfgspace_x3gio_decodepipe_h_sel_6x_3_0_0_0_0_a2_1.INIT = 8'h10; + LUT3 com_cmm_u_cmm_cfgspace_x3gio_decodepipe_h_sel_6x_3_0_0_0_0_a2_1 ( + .I0(com_cmm_u_cmm_cfgspace_N_55879_i), + .I1(cfg_dwaddr_6099[6]), + .I2(com_cmm_u_cmm_cfgspace_sel_1x_3_0_0_0_0_o3_2), + .O(com_cmm_u_cmm_cfgspace_N_57266_1) + ); + defparam com_cmm_u_cmm_cfgspace_x3gio_decodepipe_h_sel_3x_3_0_0_0_0_a2_0_1.INIT = 4'h2; + LUT2 com_cmm_u_cmm_cfgspace_x3gio_decodepipe_h_sel_3x_3_0_0_0_0_a2_0_1 ( + .I0(com_cmm_u_cmm_cfgspace_N_61379), + .I1(com_cmm_cfg_addr[4]), + .O(com_cmm_u_cmm_cfgspace_N_57261_1) + ); + defparam com_cmm_u_cmm_cfgspace_cfg2ulm_rddata_0_a2_0_a2_0_a2_0_a2_25_.INIT = 4'h8; + LUT2 com_cmm_u_cmm_cfgspace_cfg2ulm_rddata_0_a2_0_a2_0_a2_0_a2_25_ ( + .I0(com_cmm_u_cmm_cfgspace_cfg2ulm_valid), + .I1(com_cmm_u_cmm_cfgspace_decoder_read_data[25]), + .O(cfg_do_6096[25]) + ); + defparam com_cmm_u_cmm_cfgspace_x3gio_msihaddr_msi_haddr12_0_a2_0_a2_0_a2_0_a2.INIT = 8'h80; + LUT3 com_cmm_u_cmm_cfgspace_x3gio_msihaddr_msi_haddr12_0_a2_0_a2_0_a2_0_a2 ( + .I0(com_cmm_u_cmm_cfgspace_N_55870_i), + .I1(com_cmm_u_cmm_cfgspace_sel_5x_5771), + .I2(com_cmm_u_cmm_cfgspace_sel_x0_5788), + .O(com_cmm_u_cmm_cfgspace_msi_haddr12) + ); + defparam com_cmm_u_cmm_cfgspace_x3gio_msihaddr_msi_haddr35_0_a2_0_a2_0_a2_0_a2.INIT = 8'h80; + LUT3 com_cmm_u_cmm_cfgspace_x3gio_msihaddr_msi_haddr35_0_a2_0_a2_0_a2_0_a2 ( + .I0(com_cmm_u_cmm_cfgspace_N_55870_i), + .I1(com_cmm_u_cmm_cfgspace_sel_5x_5771), + .I2(com_cmm_u_cmm_cfgspace_sel_x2_5786), + .O(com_cmm_u_cmm_cfgspace_msi_haddr35) + ); + defparam com_cmm_u_cmm_cfgspace_x3gio_msihaddr_msi_haddr46_0_a2_0_a2_0_a2_0_a2.INIT = 8'h80; + LUT3 com_cmm_u_cmm_cfgspace_x3gio_msihaddr_msi_haddr46_0_a2_0_a2_0_a2_0_a2 ( + .I0(com_cmm_u_cmm_cfgspace_N_55870_i), + .I1(com_cmm_u_cmm_cfgspace_sel_5x_5771), + .I2(com_cmm_u_cmm_cfgspace_sel_x3_5785), + .O(com_cmm_u_cmm_cfgspace_msi_haddr46) + ); + defparam com_cmm_u_cmm_cfgspace_x3gio_msihaddr_msi_haddr23_0_a2_0_a2_0_a2_0_a2.INIT = 8'h80; + LUT3 com_cmm_u_cmm_cfgspace_x3gio_msihaddr_msi_haddr23_0_a2_0_a2_0_a2_0_a2 ( + .I0(com_cmm_u_cmm_cfgspace_N_55870_i), + .I1(com_cmm_u_cmm_cfgspace_sel_5x_5771), + .I2(com_cmm_u_cmm_cfgspace_sel_x1_5787), + .O(com_cmm_u_cmm_cfgspace_msi_haddr23) + ); + defparam com_cmm_u_cmm_cfgspace_x3gio_msidata_msi_data12_0_a2_0_a2_0_a2_0_a2.INIT = 8'h80; + LUT3 com_cmm_u_cmm_cfgspace_x3gio_msidata_msi_data12_0_a2_0_a2_0_a2_0_a2 ( + .I0(com_cmm_u_cmm_cfgspace_N_55870_i), + .I1(com_cmm_u_cmm_cfgspace_sel_5x_5771), + .I2(com_cmm_u_cmm_cfgspace_sel_x4_5784), + .O(com_cmm_u_cmm_cfgspace_msi_data12) + ); + defparam com_cmm_u_cmm_cfgspace_x3gio_msidata_msi_data22_0_a2_0_a2_0_a2_0_a2.INIT = 8'h80; + LUT3 com_cmm_u_cmm_cfgspace_x3gio_msidata_msi_data22_0_a2_0_a2_0_a2_0_a2 ( + .I0(com_cmm_u_cmm_cfgspace_N_55870_i), + .I1(com_cmm_u_cmm_cfgspace_sel_5x_5771), + .I2(com_cmm_u_cmm_cfgspace_sel_x5_5783), + .O(com_cmm_u_cmm_cfgspace_msi_data22) + ); + defparam com_cmm_u_cmm_cfgspace_x3gio_dsts_x_dsts_9_iv_0_0_0_0_a2_0_1_3_.INIT = 4'h8; + LUT2 com_cmm_u_cmm_cfgspace_x3gio_dsts_x_dsts_9_iv_0_0_0_0_a2_0_1_3_ ( + .I0(com_cmm_u_cmm_cfgspace_N_55912_i), + .I1(com_cmm_u_cmm_cfgspace_sel_x2_5786), + .O(com_cmm_u_cmm_cfgspace_N_58304_1) + ); + defparam com_cmm_u_cmm_cfgspace_x3gio_status_status_28_iv_0_0_0_0_a2_0_1_8_.INIT = 4'h8; + LUT2 com_cmm_u_cmm_cfgspace_x3gio_status_status_28_iv_0_0_0_0_a2_0_1_8_ ( + .I0(com_cmm_u_cmm_cfgspace_N_61391), + .I1(com_cmm_u_cmm_cfgspace_sel_x7_5781), + .O(com_cmm_u_cmm_cfgspace_N_58308_1) + ); + defparam com_cmm_u_cmm_cfgspace_x3gio_pmcsr_pme_pmcsr_21_i_0_0_0_o3_0_.INIT = 4'h8; + LUT2 com_cmm_u_cmm_cfgspace_x3gio_pmcsr_pme_pmcsr_21_i_0_0_0_o3_0_ ( + .I0(com_cmm_u_cmm_cfgspace_N_55964_i), + .I1(com_cmm_u_cmm_cfgspace_sel_x4_5784), + .O(com_cmm_u_cmm_cfgspace_pme_pmcsr_21_i_0_0_0_o3[0]) + ); + defparam com_cmm_u_cmm_cfgspace_x3gio_xrom_xrom_reg_9_0_0_0_0_o3_11_.INIT = 8'h80; + LUT3 com_cmm_u_cmm_cfgspace_x3gio_xrom_xrom_reg_9_0_0_0_0_o3_11_ ( + .I0(com_cmm_u_cmm_cfgspace_N_55870_i), + .I1(com_cmm_u_cmm_cfgspace_sel_3x_5773), + .I2(com_cmm_u_cmm_cfgspace_sel_x1_5787), + .O(com_cmm_u_cmm_cfgspace_N_56033_i) + ); + defparam com_cmm_u_cmm_cfgspace_x_dcmd_18_i_0_0_0_o3_11_.INIT = 4'h8; + LUT2 com_cmm_u_cmm_cfgspace_x_dcmd_18_i_0_0_0_o3_11_ ( + .I0(com_cmm_u_cmm_cfgspace_N_55912_i), + .I1(com_cmm_u_cmm_cfgspace_sel_x1_5787), + .O(com_cmm_u_cmm_cfgspace_N_55990_i) + ); + defparam com_cmm_u_cmm_cfgspace_x3gio_bar3_bar3_reg_8_1_0_0_0_o3_0_.INIT = 4'h8; + LUT2 com_cmm_u_cmm_cfgspace_x3gio_bar3_bar3_reg_8_1_0_0_0_o3_0_ ( + .I0(com_cmm_u_cmm_cfgspace_N_55892_i), + .I1(com_cmm_u_cmm_cfgspace_sel_xc_5792), + .O(com_cmm_u_cmm_cfgspace_N_55974_i) + ); + defparam com_cmm_u_cmm_cfgspace_x3gio_bar2_bar2_reg_8_1_0_0_0_o3_0_.INIT = 4'h8; + LUT2 com_cmm_u_cmm_cfgspace_x3gio_bar2_bar2_reg_8_1_0_0_0_o3_0_ ( + .I0(com_cmm_u_cmm_cfgspace_N_55892_i), + .I1(com_cmm_u_cmm_cfgspace_sel_x8_5780), + .O(com_cmm_u_cmm_cfgspace_N_55973_i) + ); + defparam com_cmm_u_cmm_cfgspace_x3gio_bar1_bar1_reg_8_1_0_0_0_o3_0_.INIT = 4'h8; + LUT2 com_cmm_u_cmm_cfgspace_x3gio_bar1_bar1_reg_8_1_0_0_0_o3_0_ ( + .I0(com_cmm_u_cmm_cfgspace_N_55892_i), + .I1(com_cmm_u_cmm_cfgspace_sel_x4_5784), + .O(com_cmm_u_cmm_cfgspace_N_55972_i) + ); + defparam com_cmm_u_cmm_cfgspace_x3gio_bar5_bar5_reg_8_1_0_0_0_o3_0_.INIT = 4'h8; + LUT2 com_cmm_u_cmm_cfgspace_x3gio_bar5_bar5_reg_8_1_0_0_0_o3_0_ ( + .I0(com_cmm_u_cmm_cfgspace_N_55910_i), + .I1(com_cmm_u_cmm_cfgspace_sel_x4_5784), + .O(com_cmm_u_cmm_cfgspace_N_55971_i) + ); + defparam com_cmm_u_cmm_cfgspace_x3gio_bar4_bar4_reg_8_1_0_0_0_o3_0_.INIT = 4'h8; + LUT2 com_cmm_u_cmm_cfgspace_x3gio_bar4_bar4_reg_8_1_0_0_0_o3_0_ ( + .I0(com_cmm_u_cmm_cfgspace_N_55910_i), + .I1(com_cmm_u_cmm_cfgspace_sel_x0_5788), + .O(com_cmm_u_cmm_cfgspace_N_55970_i) + ); + defparam com_cmm_u_cmm_cfgspace_x3gio_xrom_xrom_reg_15_0_0_0_0_o3_24_.INIT = 8'h80; + LUT3 com_cmm_u_cmm_cfgspace_x3gio_xrom_xrom_reg_15_0_0_0_0_o3_24_ ( + .I0(com_cmm_u_cmm_cfgspace_N_55870_i), + .I1(com_cmm_u_cmm_cfgspace_sel_3x_5773), + .I2(com_cmm_u_cmm_cfgspace_sel_x3_5785), + .O(com_cmm_u_cmm_cfgspace_N_55962_i) + ); + defparam com_cmm_u_cmm_cfgspace_x3gio_xrom_xrom_reg_12_0_0_0_o3_16_.INIT = 8'h80; + LUT3 com_cmm_u_cmm_cfgspace_x3gio_xrom_xrom_reg_12_0_0_0_o3_16_ ( + .I0(com_cmm_u_cmm_cfgspace_N_55870_i), + .I1(com_cmm_u_cmm_cfgspace_sel_3x_5773), + .I2(com_cmm_u_cmm_cfgspace_sel_x2_5786), + .O(com_cmm_u_cmm_cfgspace_N_55961_i) + ); + defparam com_cmm_u_cmm_cfgspace_x_dcmd_18_i_0_0_o3_1_.INIT = 4'h8; + LUT2 com_cmm_u_cmm_cfgspace_x_dcmd_18_i_0_0_o3_1_ ( + .I0(com_cmm_u_cmm_cfgspace_N_55912_i), + .I1(com_cmm_u_cmm_cfgspace_sel_x0_5788), + .O(com_cmm_u_cmm_cfgspace_x_dcmd_18_i_0_0_o3[1]) + ); + defparam com_cmm_u_cmm_cfgspace_x3gio_bar5_bar5_reg45_0_a2_0_a2_0_a2_0_a2.INIT = 4'h8; + LUT2 com_cmm_u_cmm_cfgspace_x3gio_bar5_bar5_reg45_0_a2_0_a2_0_a2_0_a2 ( + .I0(com_cmm_u_cmm_cfgspace_N_55910_i), + .I1(com_cmm_u_cmm_cfgspace_sel_x5_5783), + .O(com_cmm_u_cmm_cfgspace_bar5_reg45) + ); + defparam com_cmm_u_cmm_cfgspace_x3gio_bar1_bar1_reg45_0_a2_0_a2_0_a2_0_a2.INIT = 4'h8; + LUT2 com_cmm_u_cmm_cfgspace_x3gio_bar1_bar1_reg45_0_a2_0_a2_0_a2_0_a2 ( + .I0(com_cmm_u_cmm_cfgspace_N_55892_i), + .I1(com_cmm_u_cmm_cfgspace_sel_x5_5783), + .O(com_cmm_u_cmm_cfgspace_bar1_reg45) + ); + defparam com_cmm_u_cmm_cfgspace_x3gio_command_command93_0_a2_0_a2_0_a2_0_a2.INIT = 4'h8; + LUT2 com_cmm_u_cmm_cfgspace_x3gio_command_command93_0_a2_0_a2_0_a2_0_a2 ( + .I0(com_cmm_u_cmm_cfgspace_N_61391), + .I1(com_cmm_u_cmm_cfgspace_sel_x5_5783), + .O(com_cmm_u_cmm_cfgspace_command93) + ); + defparam com_cmm_u_cmm_cfgspace_x3gio_bar5_bar5_reg70_0_a2_0_a2_0_a2_0_a2.INIT = 4'h8; + LUT2 com_cmm_u_cmm_cfgspace_x3gio_bar5_bar5_reg70_0_a2_0_a2_0_a2_0_a2 ( + .I0(com_cmm_u_cmm_cfgspace_N_55910_i), + .I1(com_cmm_u_cmm_cfgspace_sel_x7_5781), + .O(com_cmm_u_cmm_cfgspace_bar5_reg70) + ); + defparam com_cmm_u_cmm_cfgspace_x3gio_bar1_bar1_reg70_0_a2_0_a2_0_a2_0_a2.INIT = 4'h8; + LUT2 com_cmm_u_cmm_cfgspace_x3gio_bar1_bar1_reg70_0_a2_0_a2_0_a2_0_a2 ( + .I0(com_cmm_u_cmm_cfgspace_N_55892_i), + .I1(com_cmm_u_cmm_cfgspace_sel_x7_5781), + .O(com_cmm_u_cmm_cfgspace_bar1_reg70) + ); + defparam com_cmm_u_cmm_cfgspace_x3gio_lcmd_x_lcmd22_0_a2_0_a2_0_a2_0_a2.INIT = 4'h8; + LUT2 com_cmm_u_cmm_cfgspace_x3gio_lcmd_x_lcmd22_0_a2_0_a2_0_a2_0_a2 ( + .I0(com_cmm_u_cmm_cfgspace_N_55912_i), + .I1(com_cmm_u_cmm_cfgspace_sel_x8_5780), + .O(com_cmm_u_cmm_cfgspace_x_lcmd22) + ); + defparam com_cmm_u_cmm_cfgspace_x3gio_bar4_bar4_reg45_0_a2_0_a2_0_a2_0_a2.INIT = 4'h8; + LUT2 com_cmm_u_cmm_cfgspace_x3gio_bar4_bar4_reg45_0_a2_0_a2_0_a2_0_a2 ( + .I0(com_cmm_u_cmm_cfgspace_N_55910_i), + .I1(com_cmm_u_cmm_cfgspace_sel_x1_5787), + .O(com_cmm_u_cmm_cfgspace_bar4_reg45) + ); + defparam com_cmm_u_cmm_cfgspace_x3gio_bar0_bar0_reg31_0_a2_0_a2_0_a2_0_a2.INIT = 4'h8; + LUT2 com_cmm_u_cmm_cfgspace_x3gio_bar0_bar0_reg31_0_a2_0_a2_0_a2_0_a2 ( + .I0(com_cmm_u_cmm_cfgspace_N_55892_i), + .I1(com_cmm_u_cmm_cfgspace_sel_x1_5787), + .O(com_cmm_u_cmm_cfgspace_bar0_reg31) + ); + defparam com_cmm_u_cmm_cfgspace_x3gio_command_command67_0_a2_0_a2_0_a2_0_a2.INIT = 4'h8; + LUT2 com_cmm_u_cmm_cfgspace_x3gio_command_command67_0_a2_0_a2_0_a2_0_a2 ( + .I0(com_cmm_u_cmm_cfgspace_N_61391), + .I1(com_cmm_u_cmm_cfgspace_sel_x4_5784), + .O(com_cmm_u_cmm_cfgspace_command67) + ); + defparam com_cmm_u_cmm_cfgspace_x3gio_msiladdr_msi_laddr51_0_a2_0_a2_0_a2_0_a2.INIT = 4'h8; + LUT2 com_cmm_u_cmm_cfgspace_x3gio_msiladdr_msi_laddr51_0_a2_0_a2_0_a2_0_a2 ( + .I0(com_cmm_u_cmm_cfgspace_N_55964_i), + .I1(com_cmm_u_cmm_cfgspace_sel_xf_5789), + .O(com_cmm_u_cmm_cfgspace_msi_laddr51) + ); + defparam com_cmm_u_cmm_cfgspace_x3gio_msiladdr_msi_laddr40_0_a2_0_a2_0_a2_0_a2.INIT = 4'h8; + LUT2 com_cmm_u_cmm_cfgspace_x3gio_msiladdr_msi_laddr40_0_a2_0_a2_0_a2_0_a2 ( + .I0(com_cmm_u_cmm_cfgspace_N_55964_i), + .I1(com_cmm_u_cmm_cfgspace_sel_xe_5790), + .O(com_cmm_u_cmm_cfgspace_msi_laddr40) + ); + defparam com_cmm_u_cmm_cfgspace_x3gio_msiladdr_msi_laddr28_0_a2_0_a2_0_a2_0_a2.INIT = 4'h8; + LUT2 com_cmm_u_cmm_cfgspace_x3gio_msiladdr_msi_laddr28_0_a2_0_a2_0_a2_0_a2 ( + .I0(com_cmm_u_cmm_cfgspace_N_55964_i), + .I1(com_cmm_u_cmm_cfgspace_sel_xd_5791), + .O(com_cmm_u_cmm_cfgspace_msi_laddr28) + ); + defparam com_cmm_u_cmm_cfgspace_x3gio_msiladdr_msi_laddr16_0_a2_0_a2_0_a2_0_a2.INIT = 4'h8; + LUT2 com_cmm_u_cmm_cfgspace_x3gio_msiladdr_msi_laddr16_0_a2_0_a2_0_a2_0_a2 ( + .I0(com_cmm_u_cmm_cfgspace_N_55964_i), + .I1(com_cmm_u_cmm_cfgspace_sel_xc_5792), + .O(com_cmm_u_cmm_cfgspace_msi_laddr16) + ); + defparam com_cmm_u_cmm_cfgspace_x3gio_msictrl_msi_control27_0_a2_0_a2_0_a2_0_a2.INIT = 4'h8; + LUT2 com_cmm_u_cmm_cfgspace_x3gio_msictrl_msi_control27_0_a2_0_a2_0_a2_0_a2 ( + .I0(com_cmm_u_cmm_cfgspace_N_55964_i), + .I1(com_cmm_u_cmm_cfgspace_sel_xa_5778), + .O(com_cmm_u_cmm_cfgspace_msi_control27) + ); + defparam com_cmm_u_cmm_cfgspace_x3gio_intline_int_line8_0_a2_0_a2_0_a2_0_a2.INIT = 8'h80; + LUT3 com_cmm_u_cmm_cfgspace_x3gio_intline_int_line8_0_a2_0_a2_0_a2_0_a2 ( + .I0(com_cmm_u_cmm_cfgspace_N_55870_i), + .I1(com_cmm_u_cmm_cfgspace_sel_3x_5773), + .I2(com_cmm_u_cmm_cfgspace_sel_xc_5792), + .O(com_cmm_u_cmm_cfgspace_int_line8) + ); + defparam com_cmm_u_cmm_cfgspace_x3gio_bar3_bar3_reg70_0_a2_0_a2_0_a2_0_a2.INIT = 4'h8; + LUT2 com_cmm_u_cmm_cfgspace_x3gio_bar3_bar3_reg70_0_a2_0_a2_0_a2_0_a2 ( + .I0(com_cmm_u_cmm_cfgspace_N_55892_i), + .I1(com_cmm_u_cmm_cfgspace_sel_xf_5789), + .O(com_cmm_u_cmm_cfgspace_bar3_reg70) + ); + defparam com_cmm_u_cmm_cfgspace_x3gio_bar3_bar3_reg58_0_a2_0_a2_0_a2_0_a2.INIT = 4'h8; + LUT2 com_cmm_u_cmm_cfgspace_x3gio_bar3_bar3_reg58_0_a2_0_a2_0_a2_0_a2 ( + .I0(com_cmm_u_cmm_cfgspace_N_55892_i), + .I1(com_cmm_u_cmm_cfgspace_sel_xe_5790), + .O(com_cmm_u_cmm_cfgspace_bar3_reg58) + ); + defparam com_cmm_u_cmm_cfgspace_x3gio_bar3_bar3_reg45_0_a2_0_a2_0_a2_0_a2.INIT = 4'h8; + LUT2 com_cmm_u_cmm_cfgspace_x3gio_bar3_bar3_reg45_0_a2_0_a2_0_a2_0_a2 ( + .I0(com_cmm_u_cmm_cfgspace_N_55892_i), + .I1(com_cmm_u_cmm_cfgspace_sel_xd_5791), + .O(com_cmm_u_cmm_cfgspace_bar3_reg45) + ); + defparam com_cmm_u_cmm_cfgspace_x3gio_bar2_bar2_reg70_0_a2_0_a2_0_a2_0_a2.INIT = 4'h8; + LUT2 com_cmm_u_cmm_cfgspace_x3gio_bar2_bar2_reg70_0_a2_0_a2_0_a2_0_a2 ( + .I0(com_cmm_u_cmm_cfgspace_N_55892_i), + .I1(com_cmm_u_cmm_cfgspace_sel_xb_5793), + .O(com_cmm_u_cmm_cfgspace_bar2_reg70) + ); + defparam com_cmm_u_cmm_cfgspace_x3gio_bar2_bar2_reg58_0_a2_0_a2_0_a2_0_a2.INIT = 4'h8; + LUT2 com_cmm_u_cmm_cfgspace_x3gio_bar2_bar2_reg58_0_a2_0_a2_0_a2_0_a2 ( + .I0(com_cmm_u_cmm_cfgspace_N_55892_i), + .I1(com_cmm_u_cmm_cfgspace_sel_xa_5778), + .O(com_cmm_u_cmm_cfgspace_bar2_reg58) + ); + defparam com_cmm_u_cmm_cfgspace_x3gio_bar2_bar2_reg45_0_a2_0_a2_0_a2_0_a2.INIT = 4'h8; + LUT2 com_cmm_u_cmm_cfgspace_x3gio_bar2_bar2_reg45_0_a2_0_a2_0_a2_0_a2 ( + .I0(com_cmm_u_cmm_cfgspace_N_55892_i), + .I1(com_cmm_u_cmm_cfgspace_sel_x9_5779), + .O(com_cmm_u_cmm_cfgspace_bar2_reg45) + ); + defparam com_cmm_u_cmm_cfgspace_x3gio_cacheline_cache_line8_0_a2_0_a2_0_a2_0_a2.INIT = 4'h8; + LUT2 com_cmm_u_cmm_cfgspace_x3gio_cacheline_cache_line8_0_a2_0_a2_0_a2_0_a2 ( + .I0(com_cmm_u_cmm_cfgspace_N_61391), + .I1(com_cmm_u_cmm_cfgspace_sel_xc_5792), + .O(com_cmm_u_cmm_cfgspace_cache_line8) + ); + defparam com_cmm_u_cmm_cfgspace_x3gio_bar5_bar5_reg58_0_a2_0_a2_0_a2_0_a2.INIT = 4'h8; + LUT2 com_cmm_u_cmm_cfgspace_x3gio_bar5_bar5_reg58_0_a2_0_a2_0_a2_0_a2 ( + .I0(com_cmm_u_cmm_cfgspace_N_55910_i), + .I1(com_cmm_u_cmm_cfgspace_sel_x6_5782), + .O(com_cmm_u_cmm_cfgspace_bar5_reg58) + ); + defparam com_cmm_u_cmm_cfgspace_x3gio_bar4_bar4_reg70_0_a2_0_a2_0_a2_0_a2.INIT = 4'h8; + LUT2 com_cmm_u_cmm_cfgspace_x3gio_bar4_bar4_reg70_0_a2_0_a2_0_a2_0_a2 ( + .I0(com_cmm_u_cmm_cfgspace_N_55910_i), + .I1(com_cmm_u_cmm_cfgspace_sel_x3_5785), + .O(com_cmm_u_cmm_cfgspace_bar4_reg70) + ); + defparam com_cmm_u_cmm_cfgspace_x3gio_bar4_bar4_reg58_0_a2_0_a2_0_a2_0_a2.INIT = 4'h8; + LUT2 com_cmm_u_cmm_cfgspace_x3gio_bar4_bar4_reg58_0_a2_0_a2_0_a2_0_a2 ( + .I0(com_cmm_u_cmm_cfgspace_N_55910_i), + .I1(com_cmm_u_cmm_cfgspace_sel_x2_5786), + .O(com_cmm_u_cmm_cfgspace_bar4_reg58) + ); + defparam com_cmm_u_cmm_cfgspace_x3gio_bar1_bar1_reg58_0_a2_0_a2_0_a2_0_a2.INIT = 4'h8; + LUT2 com_cmm_u_cmm_cfgspace_x3gio_bar1_bar1_reg58_0_a2_0_a2_0_a2_0_a2 ( + .I0(com_cmm_u_cmm_cfgspace_N_55892_i), + .I1(com_cmm_u_cmm_cfgspace_sel_x6_5782), + .O(com_cmm_u_cmm_cfgspace_bar1_reg58) + ); + defparam com_cmm_u_cmm_cfgspace_x3gio_bar0_bar0_reg56_0_a2_0_a2_0_a2_0_a2.INIT = 4'h8; + LUT2 com_cmm_u_cmm_cfgspace_x3gio_bar0_bar0_reg56_0_a2_0_a2_0_a2_0_a2 ( + .I0(com_cmm_u_cmm_cfgspace_N_55892_i), + .I1(com_cmm_u_cmm_cfgspace_sel_x3_5785), + .O(com_cmm_u_cmm_cfgspace_bar0_reg56) + ); + defparam com_cmm_u_cmm_cfgspace_x3gio_bar0_bar0_reg44_0_a2_0_a2_0_a2_0_a2.INIT = 4'h8; + LUT2 com_cmm_u_cmm_cfgspace_x3gio_bar0_bar0_reg44_0_a2_0_a2_0_a2_0_a2 ( + .I0(com_cmm_u_cmm_cfgspace_N_55892_i), + .I1(com_cmm_u_cmm_cfgspace_sel_x2_5786), + .O(com_cmm_u_cmm_cfgspace_bar0_reg44) + ); + defparam com_cmm_u_cmm_cfgspace_cfg2ulm_rddata_0_a2_0_a2_0_a2_0_a2_31_.INIT = 4'h8; + LUT2 com_cmm_u_cmm_cfgspace_cfg2ulm_rddata_0_a2_0_a2_0_a2_0_a2_31_ ( + .I0(com_cmm_u_cmm_cfgspace_cfg2ulm_valid), + .I1(com_cmm_u_cmm_cfgspace_decoder_read_data[31]), + .O(cfg_do_6096[31]) + ); + defparam com_cmm_u_cmm_cfgspace_cfg2ulm_rddata_0_a2_0_a2_0_a2_0_a2_30_.INIT = 4'h8; + LUT2 com_cmm_u_cmm_cfgspace_cfg2ulm_rddata_0_a2_0_a2_0_a2_0_a2_30_ ( + .I0(com_cmm_u_cmm_cfgspace_cfg2ulm_valid), + .I1(com_cmm_u_cmm_cfgspace_decoder_read_data[30]), + .O(cfg_do_6096[30]) + ); + defparam com_cmm_u_cmm_cfgspace_cfg2ulm_rddata_0_a2_0_a2_0_a2_0_a2_29_.INIT = 4'h8; + LUT2 com_cmm_u_cmm_cfgspace_cfg2ulm_rddata_0_a2_0_a2_0_a2_0_a2_29_ ( + .I0(com_cmm_u_cmm_cfgspace_cfg2ulm_valid), + .I1(com_cmm_u_cmm_cfgspace_decoder_read_data[29]), + .O(cfg_do_6096[29]) + ); + defparam com_cmm_u_cmm_cfgspace_cfg2ulm_rddata_0_a2_0_a2_0_a2_0_a2_28_.INIT = 4'h8; + LUT2 com_cmm_u_cmm_cfgspace_cfg2ulm_rddata_0_a2_0_a2_0_a2_0_a2_28_ ( + .I0(com_cmm_u_cmm_cfgspace_cfg2ulm_valid), + .I1(com_cmm_u_cmm_cfgspace_decoder_read_data[28]), + .O(cfg_do_6096[28]) + ); + defparam com_cmm_u_cmm_cfgspace_cfg2ulm_rddata_0_a2_0_a2_0_a2_0_a2_27_.INIT = 4'h8; + LUT2 com_cmm_u_cmm_cfgspace_cfg2ulm_rddata_0_a2_0_a2_0_a2_0_a2_27_ ( + .I0(com_cmm_u_cmm_cfgspace_cfg2ulm_valid), + .I1(com_cmm_u_cmm_cfgspace_decoder_read_data[27]), + .O(cfg_do_6096[27]) + ); + defparam com_cmm_u_cmm_cfgspace_cfg2ulm_rddata_0_a2_0_a2_0_a2_0_a2_26_.INIT = 4'h8; + LUT2 com_cmm_u_cmm_cfgspace_cfg2ulm_rddata_0_a2_0_a2_0_a2_0_a2_26_ ( + .I0(com_cmm_u_cmm_cfgspace_cfg2ulm_valid), + .I1(com_cmm_u_cmm_cfgspace_decoder_read_data[26]), + .O(cfg_do_6096[26]) + ); + defparam com_cmm_u_cmm_cfgspace_cfg2ulm_rddata_0_a2_0_a2_0_a2_0_a2_24_.INIT = 4'h8; + LUT2 com_cmm_u_cmm_cfgspace_cfg2ulm_rddata_0_a2_0_a2_0_a2_0_a2_24_ ( + .I0(com_cmm_u_cmm_cfgspace_cfg2ulm_valid), + .I1(com_cmm_u_cmm_cfgspace_decoder_read_data[24]), + .O(cfg_do_6096[24]) + ); + defparam com_cmm_u_cmm_cfgspace_cfg2ulm_rddata_0_a2_0_a2_0_a2_0_a2_23_.INIT = 4'h8; + LUT2 com_cmm_u_cmm_cfgspace_cfg2ulm_rddata_0_a2_0_a2_0_a2_0_a2_23_ ( + .I0(com_cmm_u_cmm_cfgspace_cfg2ulm_valid), + .I1(com_cmm_u_cmm_cfgspace_decoder_read_data[23]), + .O(cfg_do_6096[23]) + ); + defparam com_cmm_u_cmm_cfgspace_cfg2ulm_rddata_0_a2_0_a2_0_a2_0_a2_22_.INIT = 4'h8; + LUT2 com_cmm_u_cmm_cfgspace_cfg2ulm_rddata_0_a2_0_a2_0_a2_0_a2_22_ ( + .I0(com_cmm_u_cmm_cfgspace_cfg2ulm_valid), + .I1(com_cmm_u_cmm_cfgspace_decoder_read_data[22]), + .O(cfg_do_6096[22]) + ); + defparam com_cmm_u_cmm_cfgspace_cfg2ulm_rddata_0_a2_0_a2_0_a2_0_a2_21_.INIT = 4'h8; + LUT2 com_cmm_u_cmm_cfgspace_cfg2ulm_rddata_0_a2_0_a2_0_a2_0_a2_21_ ( + .I0(com_cmm_u_cmm_cfgspace_cfg2ulm_valid), + .I1(com_cmm_u_cmm_cfgspace_decoder_read_data[21]), + .O(cfg_do_6096[21]) + ); + defparam com_cmm_u_cmm_cfgspace_cfg2ulm_rddata_0_a2_0_a2_0_a2_0_a2_20_.INIT = 4'h8; + LUT2 com_cmm_u_cmm_cfgspace_cfg2ulm_rddata_0_a2_0_a2_0_a2_0_a2_20_ ( + .I0(com_cmm_u_cmm_cfgspace_cfg2ulm_valid), + .I1(com_cmm_u_cmm_cfgspace_decoder_read_data[20]), + .O(cfg_do_6096[20]) + ); + defparam com_cmm_u_cmm_cfgspace_cfg2ulm_rddata_0_a2_0_a2_0_a2_0_a2_19_.INIT = 4'h8; + LUT2 com_cmm_u_cmm_cfgspace_cfg2ulm_rddata_0_a2_0_a2_0_a2_0_a2_19_ ( + .I0(com_cmm_u_cmm_cfgspace_cfg2ulm_valid), + .I1(com_cmm_u_cmm_cfgspace_decoder_read_data[19]), + .O(cfg_do_6096[19]) + ); + defparam com_cmm_u_cmm_cfgspace_cfg2ulm_rddata_0_a2_0_a2_0_a2_0_a2_18_.INIT = 4'h8; + LUT2 com_cmm_u_cmm_cfgspace_cfg2ulm_rddata_0_a2_0_a2_0_a2_0_a2_18_ ( + .I0(com_cmm_u_cmm_cfgspace_cfg2ulm_valid), + .I1(com_cmm_u_cmm_cfgspace_decoder_read_data[18]), + .O(cfg_do_6096[18]) + ); + defparam com_cmm_u_cmm_cfgspace_cfg2ulm_rddata_0_a2_0_a2_0_a2_0_a2_17_.INIT = 4'h8; + LUT2 com_cmm_u_cmm_cfgspace_cfg2ulm_rddata_0_a2_0_a2_0_a2_0_a2_17_ ( + .I0(com_cmm_u_cmm_cfgspace_cfg2ulm_valid), + .I1(com_cmm_u_cmm_cfgspace_decoder_read_data[17]), + .O(cfg_do_6096[17]) + ); + defparam com_cmm_u_cmm_cfgspace_cfg2ulm_rddata_0_a2_0_a2_0_a2_0_a2_16_.INIT = 4'h8; + LUT2 com_cmm_u_cmm_cfgspace_cfg2ulm_rddata_0_a2_0_a2_0_a2_0_a2_16_ ( + .I0(com_cmm_u_cmm_cfgspace_cfg2ulm_valid), + .I1(com_cmm_u_cmm_cfgspace_decoder_read_data[16]), + .O(cfg_do_6096[16]) + ); + defparam com_cmm_u_cmm_cfgspace_cfg2ulm_rddata_0_a2_0_a2_0_a2_0_a2_15_.INIT = 4'h8; + LUT2 com_cmm_u_cmm_cfgspace_cfg2ulm_rddata_0_a2_0_a2_0_a2_0_a2_15_ ( + .I0(com_cmm_u_cmm_cfgspace_cfg2ulm_valid), + .I1(com_cmm_u_cmm_cfgspace_decoder_read_data[15]), + .O(cfg_do_6096[15]) + ); + defparam com_cmm_u_cmm_cfgspace_cfg2ulm_rddata_0_a2_0_a2_0_a2_0_a2_14_.INIT = 4'h8; + LUT2 com_cmm_u_cmm_cfgspace_cfg2ulm_rddata_0_a2_0_a2_0_a2_0_a2_14_ ( + .I0(com_cmm_u_cmm_cfgspace_cfg2ulm_valid), + .I1(com_cmm_u_cmm_cfgspace_decoder_read_data[14]), + .O(cfg_do_6096[14]) + ); + defparam com_cmm_u_cmm_cfgspace_cfg2ulm_rddata_0_a2_0_a2_0_a2_0_a2_13_.INIT = 4'h8; + LUT2 com_cmm_u_cmm_cfgspace_cfg2ulm_rddata_0_a2_0_a2_0_a2_0_a2_13_ ( + .I0(com_cmm_u_cmm_cfgspace_cfg2ulm_valid), + .I1(com_cmm_u_cmm_cfgspace_decoder_read_data[13]), + .O(cfg_do_6096[13]) + ); + defparam com_cmm_u_cmm_cfgspace_cfg2ulm_rddata_0_a2_0_a2_0_a2_0_a2_12_.INIT = 4'h8; + LUT2 com_cmm_u_cmm_cfgspace_cfg2ulm_rddata_0_a2_0_a2_0_a2_0_a2_12_ ( + .I0(com_cmm_u_cmm_cfgspace_cfg2ulm_valid), + .I1(com_cmm_u_cmm_cfgspace_decoder_read_data[12]), + .O(cfg_do_6096[12]) + ); + defparam com_cmm_u_cmm_cfgspace_cfg2ulm_rddata_0_a2_0_a2_0_a2_0_a2_11_.INIT = 4'h8; + LUT2 com_cmm_u_cmm_cfgspace_cfg2ulm_rddata_0_a2_0_a2_0_a2_0_a2_11_ ( + .I0(com_cmm_u_cmm_cfgspace_cfg2ulm_valid), + .I1(com_cmm_u_cmm_cfgspace_decoder_read_data[11]), + .O(cfg_do_6096[11]) + ); + defparam com_cmm_u_cmm_cfgspace_cfg2ulm_rddata_0_a2_0_a2_0_a2_0_a2_10_.INIT = 4'h8; + LUT2 com_cmm_u_cmm_cfgspace_cfg2ulm_rddata_0_a2_0_a2_0_a2_0_a2_10_ ( + .I0(com_cmm_u_cmm_cfgspace_cfg2ulm_valid), + .I1(com_cmm_u_cmm_cfgspace_decoder_read_data[10]), + .O(cfg_do_6096[10]) + ); + defparam com_cmm_u_cmm_cfgspace_cfg2ulm_rddata_0_a2_0_a2_0_a2_0_a2_9_.INIT = 4'h8; + LUT2 com_cmm_u_cmm_cfgspace_cfg2ulm_rddata_0_a2_0_a2_0_a2_0_a2_9_ ( + .I0(com_cmm_u_cmm_cfgspace_cfg2ulm_valid), + .I1(com_cmm_u_cmm_cfgspace_decoder_read_data[9]), + .O(cfg_do_6096[9]) + ); + defparam com_cmm_u_cmm_cfgspace_cfg2ulm_rddata_0_a2_0_a2_0_a2_0_a2_8_.INIT = 4'h8; + LUT2 com_cmm_u_cmm_cfgspace_cfg2ulm_rddata_0_a2_0_a2_0_a2_0_a2_8_ ( + .I0(com_cmm_u_cmm_cfgspace_cfg2ulm_valid), + .I1(com_cmm_u_cmm_cfgspace_decoder_read_data[8]), + .O(cfg_do_6096[8]) + ); + defparam com_cmm_u_cmm_cfgspace_cfg2ulm_rddata_0_a2_0_a2_0_a2_0_a2_7_.INIT = 4'h8; + LUT2 com_cmm_u_cmm_cfgspace_cfg2ulm_rddata_0_a2_0_a2_0_a2_0_a2_7_ ( + .I0(com_cmm_u_cmm_cfgspace_cfg2ulm_valid), + .I1(com_cmm_u_cmm_cfgspace_decoder_read_data[7]), + .O(cfg_do_6096[7]) + ); + defparam com_cmm_u_cmm_cfgspace_cfg2ulm_rddata_0_a2_0_a2_0_a2_0_a2_6_.INIT = 4'h8; + LUT2 com_cmm_u_cmm_cfgspace_cfg2ulm_rddata_0_a2_0_a2_0_a2_0_a2_6_ ( + .I0(com_cmm_u_cmm_cfgspace_cfg2ulm_valid), + .I1(com_cmm_u_cmm_cfgspace_decoder_read_data[6]), + .O(cfg_do_6096[6]) + ); + defparam com_cmm_u_cmm_cfgspace_cfg2ulm_rddata_0_a2_0_a2_0_a2_0_a2_5_.INIT = 4'h8; + LUT2 com_cmm_u_cmm_cfgspace_cfg2ulm_rddata_0_a2_0_a2_0_a2_0_a2_5_ ( + .I0(com_cmm_u_cmm_cfgspace_cfg2ulm_valid), + .I1(com_cmm_u_cmm_cfgspace_decoder_read_data[5]), + .O(cfg_do_6096[5]) + ); + defparam com_cmm_u_cmm_cfgspace_cfg2ulm_rddata_0_a2_0_a2_0_a2_0_a2_4_.INIT = 4'h8; + LUT2 com_cmm_u_cmm_cfgspace_cfg2ulm_rddata_0_a2_0_a2_0_a2_0_a2_4_ ( + .I0(com_cmm_u_cmm_cfgspace_cfg2ulm_valid), + .I1(com_cmm_u_cmm_cfgspace_decoder_read_data[4]), + .O(cfg_do_6096[4]) + ); + defparam com_cmm_u_cmm_cfgspace_cfg2ulm_rddata_0_a2_0_a2_0_a2_0_a2_3_.INIT = 4'h8; + LUT2 com_cmm_u_cmm_cfgspace_cfg2ulm_rddata_0_a2_0_a2_0_a2_0_a2_3_ ( + .I0(com_cmm_u_cmm_cfgspace_cfg2ulm_valid), + .I1(com_cmm_u_cmm_cfgspace_decoder_read_data[3]), + .O(cfg_do_6096[3]) + ); + defparam com_cmm_u_cmm_cfgspace_cfg2ulm_rddata_0_a2_0_a2_0_a2_0_a2_2_.INIT = 4'h8; + LUT2 com_cmm_u_cmm_cfgspace_cfg2ulm_rddata_0_a2_0_a2_0_a2_0_a2_2_ ( + .I0(com_cmm_u_cmm_cfgspace_cfg2ulm_valid), + .I1(com_cmm_u_cmm_cfgspace_decoder_read_data[2]), + .O(cfg_do_6096[2]) + ); + defparam com_cmm_u_cmm_cfgspace_cfg2ulm_rddata_0_a2_0_a2_0_a2_0_a2_1_.INIT = 4'h8; + LUT2 com_cmm_u_cmm_cfgspace_cfg2ulm_rddata_0_a2_0_a2_0_a2_0_a2_1_ ( + .I0(com_cmm_u_cmm_cfgspace_cfg2ulm_valid), + .I1(com_cmm_u_cmm_cfgspace_decoder_read_data[1]), + .O(cfg_do_6096[1]) + ); + defparam com_cmm_u_cmm_cfgspace_cfg2ulm_rddata_0_a2_0_a2_0_a2_0_a2_0_.INIT = 4'h8; + LUT2 com_cmm_u_cmm_cfgspace_cfg2ulm_rddata_0_a2_0_a2_0_a2_0_a2_0_ ( + .I0(com_cmm_u_cmm_cfgspace_cfg2ulm_valid), + .I1(com_cmm_u_cmm_cfgspace_decoder_read_data[0]), + .O(cfg_do_6096[0]) + ); + defparam com_cmm_u_cmm_cfgspace_x3gio_bar0_bar0_reg18_0_a2_0_a2_0_a2_0_a2.INIT = 4'h8; + LUT2 com_cmm_u_cmm_cfgspace_x3gio_bar0_bar0_reg18_0_a2_0_a2_0_a2_0_a2 ( + .I0(com_cmm_u_cmm_cfgspace_N_55892_i), + .I1(com_cmm_u_cmm_cfgspace_sel_x0_5788), + .O(com_cmm_u_cmm_cfgspace_bar0_reg18) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_01_7_0_am_20_.INIT = 16'hA0CF; + LUT4 com_cmm_u_cmm_cfgspace_low_addr_01_7_0_am_20_ ( + .I0(cfg_cfg_6102[420]), + .I1(com_cmm_bar5_reg[20]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex_1[1]), + .I3(com_cmm_u_cmm_cfgspace_sel_encodex[2]), + .O(com_cmm_u_cmm_cfgspace_low_addr_01_7_0_am_20__5569) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_01_7_0_bm_20_.INIT = 16'hA00C; + LUT4 com_cmm_u_cmm_cfgspace_low_addr_01_7_0_bm_20_ ( + .I0(cfg_cfg_6102[676]), + .I1(com_cmm_bar1_reg[20]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex_1[1]), + .I3(com_cmm_u_cmm_cfgspace_sel_encodex[2]), + .O(com_cmm_u_cmm_cfgspace_low_addr_01_7_0_bm_20__5568) + ); + MUXF5 com_cmm_u_cmm_cfgspace_low_addr_01_7_0_20_ ( + .I0(com_cmm_u_cmm_cfgspace_low_addr_01_7_0_am_20__5569), + .I1(com_cmm_u_cmm_cfgspace_low_addr_01_7_0_bm_20__5568), + .O(com_cmm_u_cmm_cfgspace_low_addr_01[20]), + .S(com_cmm_u_cmm_cfgspace_sel_encodex_1[0]) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_01_7_0_am_21_.INIT = 16'hA0C0; + LUT4 com_cmm_u_cmm_cfgspace_low_addr_01_7_0_am_21_ ( + .I0(cfg_cfg_6102[421]), + .I1(com_cmm_bar5_reg[21]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex_1[1]), + .I3(com_cmm_u_cmm_cfgspace_sel_encodex[2]), + .O(com_cmm_u_cmm_cfgspace_low_addr_01_7_0_am_21__5571) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_01_7_0_bm_21_.INIT = 16'hA00C; + LUT4 com_cmm_u_cmm_cfgspace_low_addr_01_7_0_bm_21_ ( + .I0(cfg_cfg_6102[677]), + .I1(com_cmm_bar1_reg[21]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex_1[1]), + .I3(com_cmm_u_cmm_cfgspace_sel_encodex[2]), + .O(com_cmm_u_cmm_cfgspace_low_addr_01_7_0_bm_21__5570) + ); + MUXF5 com_cmm_u_cmm_cfgspace_low_addr_01_7_0_21_ ( + .I0(com_cmm_u_cmm_cfgspace_low_addr_01_7_0_am_21__5571), + .I1(com_cmm_u_cmm_cfgspace_low_addr_01_7_0_bm_21__5570), + .O(com_cmm_u_cmm_cfgspace_low_addr_01[21]), + .S(com_cmm_u_cmm_cfgspace_sel_encodex_1[0]) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_01_7_0_am_22_.INIT = 16'hA0C0; + LUT4 com_cmm_u_cmm_cfgspace_low_addr_01_7_0_am_22_ ( + .I0(cfg_cfg_6102[422]), + .I1(com_cmm_bar5_reg[22]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex_1[1]), + .I3(com_cmm_u_cmm_cfgspace_sel_encodex[2]), + .O(com_cmm_u_cmm_cfgspace_low_addr_01_7_0_am_22__5573) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_01_7_0_bm_22_.INIT = 16'hA00C; + LUT4 com_cmm_u_cmm_cfgspace_low_addr_01_7_0_bm_22_ ( + .I0(cfg_cfg_6102[678]), + .I1(com_cmm_bar1_reg[22]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex_1[1]), + .I3(com_cmm_u_cmm_cfgspace_sel_encodex[2]), + .O(com_cmm_u_cmm_cfgspace_low_addr_01_7_0_bm_22__5572) + ); + MUXF5 com_cmm_u_cmm_cfgspace_low_addr_01_7_0_22_ ( + .I0(com_cmm_u_cmm_cfgspace_low_addr_01_7_0_am_22__5573), + .I1(com_cmm_u_cmm_cfgspace_low_addr_01_7_0_bm_22__5572), + .O(com_cmm_u_cmm_cfgspace_low_addr_01[22]), + .S(com_cmm_u_cmm_cfgspace_sel_encodex_1[0]) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_01_7_0_am_23_.INIT = 16'hA0C0; + LUT4 com_cmm_u_cmm_cfgspace_low_addr_01_7_0_am_23_ ( + .I0(cfg_cfg_6102[423]), + .I1(com_cmm_bar5_reg[23]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex_1[1]), + .I3(com_cmm_u_cmm_cfgspace_sel_encodex[2]), + .O(com_cmm_u_cmm_cfgspace_low_addr_01_7_0_am_23__5575) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_01_7_0_bm_23_.INIT = 16'hA00C; + LUT4 com_cmm_u_cmm_cfgspace_low_addr_01_7_0_bm_23_ ( + .I0(cfg_cfg_6102[679]), + .I1(com_cmm_bar1_reg[23]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex_1[1]), + .I3(com_cmm_u_cmm_cfgspace_sel_encodex[2]), + .O(com_cmm_u_cmm_cfgspace_low_addr_01_7_0_bm_23__5574) + ); + MUXF5 com_cmm_u_cmm_cfgspace_low_addr_01_7_0_23_ ( + .I0(com_cmm_u_cmm_cfgspace_low_addr_01_7_0_am_23__5575), + .I1(com_cmm_u_cmm_cfgspace_low_addr_01_7_0_bm_23__5574), + .O(com_cmm_u_cmm_cfgspace_low_addr_01[23]), + .S(com_cmm_u_cmm_cfgspace_sel_encodex_1[0]) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_am_8_.INIT = 16'h0CA0; + LUT4 com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_am_8_ ( + .I0(cfg_cfg_6102[296]), + .I1(com_cmm_msi_laddr[8]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex_1[1]), + .I3(com_cmm_u_cmm_cfgspace_sel_encodex[2]), + .O(com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_am[8]) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_bm_8_.INIT = 16'h3E0E; + LUT4 com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_bm_8_ ( + .I0(com_cmm_bar3_reg[8]), + .I1(com_cmm_u_cmm_cfgspace_sel_encodex_1[1]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex[2]), + .I3(com_cmm_u_cmm_cfgspace_x_dcap[8]), + .O(com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_bm[8]) + ); + MUXF5 com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_8_ ( + .I0(com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_am[8]), + .I1(com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_bm[8]), + .O(com_cmm_u_cmm_cfgspace_low_addr_03_q_4[8]), + .S(com_cmm_u_cmm_cfgspace_sel_encodex_1[0]) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_am_9_.INIT = 16'h0CA0; + LUT4 com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_am_9_ ( + .I0(cfg_cfg_6102[297]), + .I1(com_cmm_msi_laddr[9]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex_1[1]), + .I3(com_cmm_u_cmm_cfgspace_sel_encodex[2]), + .O(com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_am[9]) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_bm_9_.INIT = 16'h3202; + LUT4 com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_bm_9_ ( + .I0(com_cmm_bar3_reg[9]), + .I1(com_cmm_u_cmm_cfgspace_sel_encodex_1[1]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex[2]), + .I3(com_cmm_u_cmm_cfgspace_x_dcap[9]), + .O(com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_bm[9]) + ); + MUXF5 com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_9_ ( + .I0(com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_am[9]), + .I1(com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_bm[9]), + .O(com_cmm_u_cmm_cfgspace_low_addr_03_q_4[9]), + .S(com_cmm_u_cmm_cfgspace_sel_encodex_1[0]) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_am_10_.INIT = 16'h0CA0; + LUT4 com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_am_10_ ( + .I0(cfg_cfg_6102[298]), + .I1(com_cmm_msi_laddr[10]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex_1[1]), + .I3(com_cmm_u_cmm_cfgspace_sel_encodex[2]), + .O(com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_am[10]) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_bm_10_.INIT = 16'h3202; + LUT4 com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_bm_10_ ( + .I0(com_cmm_bar3_reg[10]), + .I1(com_cmm_u_cmm_cfgspace_sel_encodex_1[1]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex[2]), + .I3(com_cmm_u_cmm_cfgspace_x_dcap[10]), + .O(com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_bm[10]) + ); + MUXF5 com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_10_ ( + .I0(com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_am[10]), + .I1(com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_bm[10]), + .O(com_cmm_u_cmm_cfgspace_low_addr_03_q_4[10]), + .S(com_cmm_u_cmm_cfgspace_sel_encodex_1[0]) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_am_11_.INIT = 16'h0CA0; + LUT4 com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_am_11_ ( + .I0(cfg_cfg_6102[299]), + .I1(com_cmm_msi_laddr[11]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex_1[1]), + .I3(com_cmm_u_cmm_cfgspace_sel_encodex[2]), + .O(com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_am[11]) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_bm_11_.INIT = 16'h3202; + LUT4 com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_bm_11_ ( + .I0(com_cmm_bar3_reg[11]), + .I1(com_cmm_u_cmm_cfgspace_sel_encodex_1[1]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex[2]), + .I3(com_cmm_u_cmm_cfgspace_x_dcap[11]), + .O(com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_bm[11]) + ); + MUXF5 com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_11_ ( + .I0(com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_am[11]), + .I1(com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_bm[11]), + .O(com_cmm_u_cmm_cfgspace_low_addr_03_q_4[11]), + .S(com_cmm_u_cmm_cfgspace_sel_encodex_1[0]) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_am_12_.INIT = 16'h0CA0; + LUT4 com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_am_12_ ( + .I0(cfg_cfg_6102[300]), + .I1(com_cmm_msi_laddr[12]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex_1[1]), + .I3(com_cmm_u_cmm_cfgspace_sel_encodex[2]), + .O(com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_am[12]) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_bm_12_.INIT = 16'h3202; + LUT4 com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_bm_12_ ( + .I0(com_cmm_bar3_reg[12]), + .I1(com_cmm_u_cmm_cfgspace_sel_encodex_1[1]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex[2]), + .I3(com_cmm_u_cmm_cfgspace_x_dcap[12]), + .O(com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_bm[12]) + ); + MUXF5 com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_12_ ( + .I0(com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_am[12]), + .I1(com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_bm[12]), + .O(com_cmm_u_cmm_cfgspace_low_addr_03_q_4[12]), + .S(com_cmm_u_cmm_cfgspace_sel_encodex_1[0]) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_am_13_.INIT = 16'h0CA0; + LUT4 com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_am_13_ ( + .I0(cfg_cfg_6102[301]), + .I1(com_cmm_msi_laddr[13]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex_1[1]), + .I3(com_cmm_u_cmm_cfgspace_sel_encodex[2]), + .O(com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_am[13]) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_bm_13_.INIT = 16'h3202; + LUT4 com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_bm_13_ ( + .I0(com_cmm_bar3_reg[13]), + .I1(com_cmm_u_cmm_cfgspace_sel_encodex_1[1]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex[2]), + .I3(com_cmm_u_cmm_cfgspace_x_dcap[13]), + .O(com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_bm[13]) + ); + MUXF5 com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_13_ ( + .I0(com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_am[13]), + .I1(com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_bm[13]), + .O(com_cmm_u_cmm_cfgspace_low_addr_03_q_4[13]), + .S(com_cmm_u_cmm_cfgspace_sel_encodex_1[0]) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_am_14_.INIT = 16'h0CA0; + LUT4 com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_am_14_ ( + .I0(cfg_cfg_6102[302]), + .I1(com_cmm_msi_laddr[14]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex_1[1]), + .I3(com_cmm_u_cmm_cfgspace_sel_encodex[2]), + .O(com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_am[14]) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_bm_14_.INIT = 16'h3202; + LUT4 com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_bm_14_ ( + .I0(com_cmm_bar3_reg[14]), + .I1(com_cmm_u_cmm_cfgspace_sel_encodex_1[1]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex[2]), + .I3(com_cmm_u_cmm_cfgspace_x_dcap[14]), + .O(com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_bm[14]) + ); + MUXF5 com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_14_ ( + .I0(com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_am[14]), + .I1(com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_bm[14]), + .O(com_cmm_u_cmm_cfgspace_low_addr_03_q_4[14]), + .S(com_cmm_u_cmm_cfgspace_sel_encodex_1[0]) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_am_15_.INIT = 16'h0CA0; + LUT4 com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_am_15_ ( + .I0(cfg_cfg_6102[303]), + .I1(com_cmm_msi_laddr[15]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex_1[1]), + .I3(com_cmm_u_cmm_cfgspace_sel_encodex[2]), + .O(com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_am[15]) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_bm_15_.INIT = 16'h3202; + LUT4 com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_bm_15_ ( + .I0(com_cmm_bar3_reg[15]), + .I1(com_cmm_u_cmm_cfgspace_sel_encodex_1[1]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex[2]), + .I3(com_cmm_u_cmm_cfgspace_x_dcap[15]), + .O(com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_bm[15]) + ); + MUXF5 com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_15_ ( + .I0(com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_am[15]), + .I1(com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_bm[15]), + .O(com_cmm_u_cmm_cfgspace_low_addr_03_q_4[15]), + .S(com_cmm_u_cmm_cfgspace_sel_encodex_1[0]) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_am_16_.INIT = 16'h0CA0; + LUT4 com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_am_16_ ( + .I0(cfg_cfg_6102[304]), + .I1(com_cmm_msi_laddr[16]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex_1[1]), + .I3(com_cmm_u_cmm_cfgspace_sel_encodex[2]), + .O(com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_am[16]) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_bm_16_.INIT = 16'h3202; + LUT4 com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_bm_16_ ( + .I0(com_cmm_bar3_reg[16]), + .I1(com_cmm_u_cmm_cfgspace_sel_encodex_1[1]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex[2]), + .I3(com_cmm_u_cmm_cfgspace_x_dcap[16]), + .O(com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_bm[16]) + ); + MUXF5 com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_16_ ( + .I0(com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_am[16]), + .I1(com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_bm[16]), + .O(com_cmm_u_cmm_cfgspace_low_addr_03_q_4[16]), + .S(com_cmm_u_cmm_cfgspace_sel_encodex_1[0]) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_am_17_.INIT = 16'h0CA0; + LUT4 com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_am_17_ ( + .I0(cfg_cfg_6102[305]), + .I1(com_cmm_msi_laddr[17]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex_1[1]), + .I3(com_cmm_u_cmm_cfgspace_sel_encodex[2]), + .O(com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_am[17]) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_bm_17_.INIT = 16'h3202; + LUT4 com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_bm_17_ ( + .I0(com_cmm_bar3_reg[17]), + .I1(com_cmm_u_cmm_cfgspace_sel_encodex_1[1]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex[2]), + .I3(com_cmm_u_cmm_cfgspace_x_dcap[17]), + .O(com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_bm[17]) + ); + MUXF5 com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_17_ ( + .I0(com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_am[17]), + .I1(com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_bm[17]), + .O(com_cmm_u_cmm_cfgspace_low_addr_03_q_4[17]), + .S(com_cmm_u_cmm_cfgspace_sel_encodex_1[0]) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_am_18_.INIT = 16'h0CA0; + LUT4 com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_am_18_ ( + .I0(cfg_cfg_6102[306]), + .I1(com_cmm_msi_laddr[18]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex_1[1]), + .I3(com_cmm_u_cmm_cfgspace_sel_encodex[2]), + .O(com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_am[18]) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_bm_18_.INIT = 16'h3202; + LUT4 com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_bm_18_ ( + .I0(com_cmm_bar3_reg[18]), + .I1(com_cmm_u_cmm_cfgspace_sel_encodex_1[1]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex[2]), + .I3(com_cmm_u_cmm_cfgspace_x_dcap[18]), + .O(com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_bm[18]) + ); + MUXF5 com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_18_ ( + .I0(com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_am[18]), + .I1(com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_bm[18]), + .O(com_cmm_u_cmm_cfgspace_low_addr_03_q_4[18]), + .S(com_cmm_u_cmm_cfgspace_sel_encodex_1[0]) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_am_19_.INIT = 16'h0CA0; + LUT4 com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_am_19_ ( + .I0(cfg_cfg_6102[307]), + .I1(com_cmm_msi_laddr[19]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex_1[1]), + .I3(com_cmm_u_cmm_cfgspace_sel_encodex[2]), + .O(com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_am[19]) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_bm_19_.INIT = 16'h3202; + LUT4 com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_bm_19_ ( + .I0(com_cmm_bar3_reg[19]), + .I1(com_cmm_u_cmm_cfgspace_sel_encodex_1[1]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex[2]), + .I3(com_cmm_u_cmm_cfgspace_x_dcap[19]), + .O(com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_bm[19]) + ); + MUXF5 com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_19_ ( + .I0(com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_am[19]), + .I1(com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_bm[19]), + .O(com_cmm_u_cmm_cfgspace_low_addr_03_q_4[19]), + .S(com_cmm_u_cmm_cfgspace_sel_encodex_1[0]) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_am_20_.INIT = 16'h0CA0; + LUT4 com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_am_20_ ( + .I0(cfg_cfg_6102[308]), + .I1(com_cmm_msi_laddr[20]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex_1[1]), + .I3(com_cmm_u_cmm_cfgspace_sel_encodex[2]), + .O(com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_am[20]) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_bm_20_.INIT = 16'h3202; + LUT4 com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_bm_20_ ( + .I0(com_cmm_bar3_reg[20]), + .I1(com_cmm_u_cmm_cfgspace_sel_encodex_1[1]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex[2]), + .I3(com_cmm_u_cmm_cfgspace_x_dcap[20]), + .O(com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_bm[20]) + ); + MUXF5 com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_20_ ( + .I0(com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_am[20]), + .I1(com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_bm[20]), + .O(com_cmm_u_cmm_cfgspace_low_addr_03_q_4[20]), + .S(com_cmm_u_cmm_cfgspace_sel_encodex_1[0]) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_am_21_.INIT = 16'h0CA0; + LUT4 com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_am_21_ ( + .I0(cfg_cfg_6102[309]), + .I1(com_cmm_msi_laddr[21]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex_1[1]), + .I3(com_cmm_u_cmm_cfgspace_sel_encodex[2]), + .O(com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_am[21]) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_bm_21_.INIT = 16'h3202; + LUT4 com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_bm_21_ ( + .I0(com_cmm_bar3_reg[21]), + .I1(com_cmm_u_cmm_cfgspace_sel_encodex_1[1]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex[2]), + .I3(com_cmm_u_cmm_cfgspace_x_dcap[21]), + .O(com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_bm[21]) + ); + MUXF5 com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_21_ ( + .I0(com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_am[21]), + .I1(com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_bm[21]), + .O(com_cmm_u_cmm_cfgspace_low_addr_03_q_4[21]), + .S(com_cmm_u_cmm_cfgspace_sel_encodex_1[0]) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_am_22_.INIT = 16'h0CA0; + LUT4 com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_am_22_ ( + .I0(cfg_cfg_6102[310]), + .I1(com_cmm_msi_laddr[22]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex_1[1]), + .I3(com_cmm_u_cmm_cfgspace_sel_encodex[2]), + .O(com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_am[22]) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_bm_22_.INIT = 16'h3202; + LUT4 com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_bm_22_ ( + .I0(com_cmm_bar3_reg[22]), + .I1(com_cmm_u_cmm_cfgspace_sel_encodex_1[1]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex[2]), + .I3(com_cmm_u_cmm_cfgspace_x_dcap[22]), + .O(com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_bm[22]) + ); + MUXF5 com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_22_ ( + .I0(com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_am[22]), + .I1(com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_bm[22]), + .O(com_cmm_u_cmm_cfgspace_low_addr_03_q_4[22]), + .S(com_cmm_u_cmm_cfgspace_sel_encodex_1[0]) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_am_23_.INIT = 16'h0CA0; + LUT4 com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_am_23_ ( + .I0(cfg_cfg_6102[311]), + .I1(com_cmm_msi_laddr[23]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex_1[1]), + .I3(com_cmm_u_cmm_cfgspace_sel_encodex[2]), + .O(com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_am[23]) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_bm_23_.INIT = 16'h3202; + LUT4 com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_bm_23_ ( + .I0(com_cmm_bar3_reg[23]), + .I1(com_cmm_u_cmm_cfgspace_sel_encodex_1[1]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex[2]), + .I3(com_cmm_u_cmm_cfgspace_x_dcap[23]), + .O(com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_bm[23]) + ); + MUXF5 com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_23_ ( + .I0(com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_am[23]), + .I1(com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_bm[23]), + .O(com_cmm_u_cmm_cfgspace_low_addr_03_q_4[23]), + .S(com_cmm_u_cmm_cfgspace_sel_encodex_1[0]) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_am_24_.INIT = 16'h0CA0; + LUT4 com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_am_24_ ( + .I0(cfg_cfg_6102[312]), + .I1(com_cmm_msi_laddr[24]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex_1[1]), + .I3(com_cmm_u_cmm_cfgspace_sel_encodex[2]), + .O(com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_am[24]) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_bm_24_.INIT = 16'h3202; + LUT4 com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_bm_24_ ( + .I0(com_cmm_bar3_reg[24]), + .I1(com_cmm_u_cmm_cfgspace_sel_encodex_1[1]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex[2]), + .I3(com_cmm_u_cmm_cfgspace_x_dcap[24]), + .O(com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_bm[24]) + ); + MUXF5 com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_24_ ( + .I0(com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_am[24]), + .I1(com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_bm[24]), + .O(com_cmm_u_cmm_cfgspace_low_addr_03_q_4[24]), + .S(com_cmm_u_cmm_cfgspace_sel_encodex_1[0]) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_am_25_.INIT = 16'h0CA0; + LUT4 com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_am_25_ ( + .I0(cfg_cfg_6102[313]), + .I1(com_cmm_msi_laddr[25]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex_1[1]), + .I3(com_cmm_u_cmm_cfgspace_sel_encodex[2]), + .O(com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_am[25]) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_bm_25_.INIT = 16'h3202; + LUT4 com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_bm_25_ ( + .I0(com_cmm_bar3_reg[25]), + .I1(com_cmm_u_cmm_cfgspace_sel_encodex_1[1]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex[2]), + .I3(com_cmm_u_cmm_cfgspace_x_dcap[25]), + .O(com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_bm[25]) + ); + MUXF5 com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_25_ ( + .I0(com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_am[25]), + .I1(com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_bm[25]), + .O(com_cmm_u_cmm_cfgspace_low_addr_03_q_4[25]), + .S(com_cmm_u_cmm_cfgspace_sel_encodex_1[0]) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_am_26_.INIT = 16'h0CA0; + LUT4 com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_am_26_ ( + .I0(cfg_cfg_6102[314]), + .I1(com_cmm_msi_laddr[26]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex_1[1]), + .I3(com_cmm_u_cmm_cfgspace_sel_encodex[2]), + .O(com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_am[26]) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_bm_26_.INIT = 16'h3202; + LUT4 com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_bm_26_ ( + .I0(com_cmm_bar3_reg[26]), + .I1(com_cmm_u_cmm_cfgspace_sel_encodex_1[1]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex[2]), + .I3(com_cmm_u_cmm_cfgspace_x_dcap[26]), + .O(com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_bm[26]) + ); + MUXF5 com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_26_ ( + .I0(com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_am[26]), + .I1(com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_bm[26]), + .O(com_cmm_u_cmm_cfgspace_low_addr_03_q_4[26]), + .S(com_cmm_u_cmm_cfgspace_sel_encodex_1[0]) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_am_27_.INIT = 16'h0CA0; + LUT4 com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_am_27_ ( + .I0(cfg_cfg_6102[315]), + .I1(com_cmm_msi_laddr[27]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex_1[1]), + .I3(com_cmm_u_cmm_cfgspace_sel_encodex[2]), + .O(com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_am[27]) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_bm_27_.INIT = 16'h3202; + LUT4 com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_bm_27_ ( + .I0(com_cmm_bar3_reg[27]), + .I1(com_cmm_u_cmm_cfgspace_sel_encodex_1[1]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex[2]), + .I3(com_cmm_u_cmm_cfgspace_x_dcap[27]), + .O(com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_bm[27]) + ); + MUXF5 com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_27_ ( + .I0(com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_am[27]), + .I1(com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_bm[27]), + .O(com_cmm_u_cmm_cfgspace_low_addr_03_q_4[27]), + .S(com_cmm_u_cmm_cfgspace_sel_encodex_1[0]) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_am_28_.INIT = 16'h0CA0; + LUT4 com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_am_28_ ( + .I0(cfg_cfg_6102[316]), + .I1(com_cmm_msi_laddr[28]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex_1[1]), + .I3(com_cmm_u_cmm_cfgspace_sel_encodex[2]), + .O(com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_am[28]) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_bm_28_.INIT = 16'h3202; + LUT4 com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_bm_28_ ( + .I0(com_cmm_bar3_reg[28]), + .I1(com_cmm_u_cmm_cfgspace_sel_encodex_1[1]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex_1[2]), + .I3(com_cmm_u_cmm_cfgspace_x_dcap[28]), + .O(com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_bm[28]) + ); + MUXF5 com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_28_ ( + .I0(com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_am[28]), + .I1(com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_bm[28]), + .O(com_cmm_u_cmm_cfgspace_low_addr_03_q_4[28]), + .S(com_cmm_u_cmm_cfgspace_sel_encodex_1[0]) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_am_29_.INIT = 16'h0CA0; + LUT4 com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_am_29_ ( + .I0(cfg_cfg_6102[317]), + .I1(com_cmm_msi_laddr[29]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex_1[1]), + .I3(com_cmm_u_cmm_cfgspace_sel_encodex_1[2]), + .O(com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_am[29]) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_bm_29_.INIT = 16'h3202; + LUT4 com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_bm_29_ ( + .I0(com_cmm_bar3_reg[29]), + .I1(com_cmm_u_cmm_cfgspace_sel_encodex_1[1]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex_1[2]), + .I3(com_cmm_u_cmm_cfgspace_x_dcap[29]), + .O(com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_bm[29]) + ); + MUXF5 com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_29_ ( + .I0(com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_am[29]), + .I1(com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_bm[29]), + .O(com_cmm_u_cmm_cfgspace_low_addr_03_q_4[29]), + .S(com_cmm_u_cmm_cfgspace_sel_encodex_1[0]) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_am_30_.INIT = 16'h0CA0; + LUT4 com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_am_30_ ( + .I0(cfg_cfg_6102[318]), + .I1(com_cmm_msi_laddr[30]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex_1[1]), + .I3(com_cmm_u_cmm_cfgspace_sel_encodex_1[2]), + .O(com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_am[30]) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_bm_30_.INIT = 16'h3202; + LUT4 com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_bm_30_ ( + .I0(com_cmm_bar3_reg[30]), + .I1(com_cmm_u_cmm_cfgspace_sel_encodex_1[1]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex_1[2]), + .I3(com_cmm_u_cmm_cfgspace_x_dcap[30]), + .O(com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_bm[30]) + ); + MUXF5 com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_30_ ( + .I0(com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_am[30]), + .I1(com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_bm[30]), + .O(com_cmm_u_cmm_cfgspace_low_addr_03_q_4[30]), + .S(com_cmm_u_cmm_cfgspace_sel_encodex_1[0]) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_am_31_.INIT = 16'h0CA0; + LUT4 com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_am_31_ ( + .I0(cfg_cfg_6102[319]), + .I1(com_cmm_msi_laddr[31]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex_1[1]), + .I3(com_cmm_u_cmm_cfgspace_sel_encodex_1[2]), + .O(com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_am[31]) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_bm_31_.INIT = 16'h3202; + LUT4 com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_bm_31_ ( + .I0(com_cmm_bar3_reg[31]), + .I1(com_cmm_u_cmm_cfgspace_sel_encodex_1[1]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex_1[2]), + .I3(com_cmm_u_cmm_cfgspace_x_dcap[31]), + .O(com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_bm[31]) + ); + MUXF5 com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_31_ ( + .I0(com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_am[31]), + .I1(com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_bm[31]), + .O(com_cmm_u_cmm_cfgspace_low_addr_03_q_4[31]), + .S(com_cmm_u_cmm_cfgspace_sel_encodex_1[0]) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_01_7_0_am_18_.INIT = 16'hA0C0; + LUT4 com_cmm_u_cmm_cfgspace_low_addr_01_7_0_am_18_ ( + .I0(cfg_cfg_6102[418]), + .I1(com_cmm_bar5_reg[18]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex_1[1]), + .I3(com_cmm_u_cmm_cfgspace_sel_encodex_1[2]), + .O(com_cmm_u_cmm_cfgspace_low_addr_01_7_0_am_18__5577) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_01_7_0_bm_18_.INIT = 16'hA00C; + LUT4 com_cmm_u_cmm_cfgspace_low_addr_01_7_0_bm_18_ ( + .I0(cfg_cfg_6102[674]), + .I1(com_cmm_bar1_reg[18]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex_1[1]), + .I3(com_cmm_u_cmm_cfgspace_sel_encodex_1[2]), + .O(com_cmm_u_cmm_cfgspace_low_addr_01_7_0_bm_18__5576) + ); + MUXF5 com_cmm_u_cmm_cfgspace_low_addr_01_7_0_18_ ( + .I0(com_cmm_u_cmm_cfgspace_low_addr_01_7_0_am_18__5577), + .I1(com_cmm_u_cmm_cfgspace_low_addr_01_7_0_bm_18__5576), + .O(com_cmm_u_cmm_cfgspace_low_addr_01[18]), + .S(com_cmm_u_cmm_cfgspace_sel_encodex_1[0]) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_01_7_0_am_17_.INIT = 16'hC808; + LUT4 com_cmm_u_cmm_cfgspace_low_addr_01_7_0_am_17_ ( + .I0(com_cmm_bar5_reg[17]), + .I1(com_cmm_u_cmm_cfgspace_sel_encodex_1[1]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex_1[2]), + .I3(com_cmm_u_cmm_cfgspace_x_lcap[0]), + .O(com_cmm_u_cmm_cfgspace_low_addr_01_7_0_am_17__5579) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_01_7_0_bm_17_.INIT = 16'hA00C; + LUT4 com_cmm_u_cmm_cfgspace_low_addr_01_7_0_bm_17_ ( + .I0(cfg_cfg_6102[673]), + .I1(com_cmm_bar1_reg[17]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex_1[1]), + .I3(com_cmm_u_cmm_cfgspace_sel_encodex_1[2]), + .O(com_cmm_u_cmm_cfgspace_low_addr_01_7_0_bm_17__5578) + ); + MUXF5 com_cmm_u_cmm_cfgspace_low_addr_01_7_0_17_ ( + .I0(com_cmm_u_cmm_cfgspace_low_addr_01_7_0_am_17__5579), + .I1(com_cmm_u_cmm_cfgspace_low_addr_01_7_0_bm_17__5578), + .O(com_cmm_u_cmm_cfgspace_low_addr_01[17]), + .S(com_cmm_u_cmm_cfgspace_sel_encodex_1[0]) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_01_7_0_am_16_.INIT = 16'hC808; + LUT4 com_cmm_u_cmm_cfgspace_low_addr_01_7_0_am_16_ ( + .I0(com_cmm_bar5_reg[16]), + .I1(com_cmm_u_cmm_cfgspace_sel_encodex_1[1]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex_1[2]), + .I3(com_cmm_u_cmm_cfgspace_x_lcap[0]), + .O(com_cmm_u_cmm_cfgspace_low_addr_01_7_0_am_16__5581) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_01_7_0_bm_16_.INIT = 16'hA00C; + LUT4 com_cmm_u_cmm_cfgspace_low_addr_01_7_0_bm_16_ ( + .I0(cfg_cfg_6102[672]), + .I1(com_cmm_bar1_reg[16]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex_1[1]), + .I3(com_cmm_u_cmm_cfgspace_sel_encodex_1[2]), + .O(com_cmm_u_cmm_cfgspace_low_addr_01_7_0_bm_16__5580) + ); + MUXF5 com_cmm_u_cmm_cfgspace_low_addr_01_7_0_16_ ( + .I0(com_cmm_u_cmm_cfgspace_low_addr_01_7_0_am_16__5581), + .I1(com_cmm_u_cmm_cfgspace_low_addr_01_7_0_bm_16__5580), + .O(com_cmm_u_cmm_cfgspace_low_addr_01[16]), + .S(com_cmm_u_cmm_cfgspace_sel_encodex_1[0]) + ); + defparam com_cmm_u_cmm_cfgspace_next_state_0_i_0_0_0_a2_1_0_.INIT = 16'h1F00; + LUT4 com_cmm_u_cmm_cfgspace_next_state_0_i_0_0_0_a2_1_0_ ( + .I0(com_cmm_N_55868_i), + .I1(com_cmm_cfg_rd), + .I2(com_cmm_state_0[1]), + .I3(com_cmm_u_cmm_cfgspace_state_0__5800), + .O(com_cmm_u_cmm_cfgspace_N_58586_1) + ); + defparam com_cmm_u_cmm_cfgspace_sel_encodex_en_3_i_0_0_0_a2_3.INIT = 16'h0080; + LUT4 com_cmm_u_cmm_cfgspace_sel_encodex_en_3_i_0_0_0_a2_3 ( + .I0(com_cmm_u_cmm_cfgspace_N_55879_i), + .I1(com_cmm_u_cmm_cfgspace_N_58591_1), + .I2(com_cmm_u_cmm_cfgspace_N_61290_2), + .I3(com_cmm_cfg_addr[2]), + .O(com_cmm_u_cmm_cfgspace_N_58591) + ); + defparam com_cmm_u_cmm_cfgspace_xrom_reg_0_sqmuxa_0_a2_0_a2_0_a2_0_a2.INIT = 16'h8000; + LUT4 com_cmm_u_cmm_cfgspace_xrom_reg_0_sqmuxa_0_a2_0_a2_0_a2_0_a2 ( + .I0(com_cmm_u_cmm_cfgspace_N_55870_i), + .I1(cfg_cfg_6102[320]), + .I2(com_cmm_u_cmm_cfgspace_sel_3x_5773), + .I3(com_cmm_u_cmm_cfgspace_sel_x0_5788), + .O(com_cmm_u_cmm_cfgspace_xrom_reg_0_sqmuxa) + ); + defparam com_cmm_u_cmm_cfgspace_sel_encodex_en_3_i_0_0_0_a2_1.INIT = 16'h0400; + LUT4 com_cmm_u_cmm_cfgspace_sel_encodex_en_3_i_0_0_0_a2_1 ( + .I0(com_cmm_u_cmm_cfgspace_N_55879_i), + .I1(com_cmm_u_cmm_cfgspace_N_58589_2), + .I2(cfg_dwaddr_6099[2]), + .I3(com_cmm_u_cmm_cfgspace_sel_1x_3_0_0_0_0_o3_2), + .O(com_cmm_u_cmm_cfgspace_N_58589) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_00_i_0_1_39299.INIT = 16'hAA8A; + LUT4_L com_cmm_u_cmm_cfgspace_low_addr_00_i_0_1_39299 ( + .I0(com_cmm_u_cmm_cfgspace_low_addr_00_i_0_1_39297_5582), + .I1(com_cmm_bar0_reg_1_), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex[0]), + .I3(com_cmm_u_cmm_cfgspace_sel_encodex_1[2]), + .LO(com_cmm_u_cmm_cfgspace_low_addr_00_i_0_1_39299_5742) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_00_i_0_15_39327.INIT = 8'h31; + LUT3_L com_cmm_u_cmm_cfgspace_low_addr_00_i_0_15_39327 ( + .I0(com_cmm_u_cmm_cfgspace_N_61330), + .I1(com_cmm_u_cmm_cfgspace_N_61347), + .I2(com_cmm_bar0_reg_15_), + .LO(com_cmm_u_cmm_cfgspace_low_addr_00_i_0_15_39327_5669) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_00_i_0_0_0_31_39351.INIT = 8'h51; + LUT3_L com_cmm_u_cmm_cfgspace_low_addr_00_i_0_0_0_31_39351 ( + .I0(com_cmm_u_cmm_cfgspace_N_58663), + .I1(com_cmm_u_cmm_cfgspace_N_61340), + .I2(cfg_cfg_6102[31]), + .LO(com_cmm_u_cmm_cfgspace_low_addr_00_i_0_0_0_31_39351_5671) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_00_i_0_0_0_28_39356.INIT = 8'h51; + LUT3_L com_cmm_u_cmm_cfgspace_low_addr_00_i_0_0_0_28_39356 ( + .I0(com_cmm_u_cmm_cfgspace_N_58663), + .I1(com_cmm_u_cmm_cfgspace_N_61340), + .I2(cfg_cfg_6102[28]), + .LO(com_cmm_u_cmm_cfgspace_low_addr_00_i_0_0_0_28_39356_5673) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_00_i_0_0_0_27_39361.INIT = 8'h51; + LUT3_L com_cmm_u_cmm_cfgspace_low_addr_00_i_0_0_0_27_39361 ( + .I0(com_cmm_u_cmm_cfgspace_N_58663), + .I1(com_cmm_u_cmm_cfgspace_N_61340), + .I2(cfg_cfg_6102[27]), + .LO(com_cmm_u_cmm_cfgspace_low_addr_00_i_0_0_0_27_39361_5675) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_00_0_0_0_1_14_.INIT = 16'h7050; + LUT4_L com_cmm_u_cmm_cfgspace_low_addr_00_0_0_0_1_14_ ( + .I0(com_cmm_u_cmm_cfgspace_N_61347), + .I1(NlwRenamedSig_OI_cfg_dcommand[14]), + .I2(com_cmm_u_cmm_cfgspace_low_addr_00_0_0_0_0_14__5583), + .I3(com_cmm_u_cmm_cfgspace_sel_encodex_1[1]), + .LO(com_cmm_u_cmm_cfgspace_low_addr_00_0_0_0_1_14__5709) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_00_0_0_0_2_14_.INIT = 16'h135F; + LUT4 com_cmm_u_cmm_cfgspace_low_addr_00_0_0_0_2_14_ ( + .I0(com_cmm_u_cmm_cfgspace_N_61330), + .I1(com_cmm_u_cmm_cfgspace_N_61371), + .I2(com_cmm_bar0_reg_14_), + .I3(com_cmm_xrom_reg_14_), + .O(com_cmm_u_cmm_cfgspace_low_addr_00_0_0_0_2[14]) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_00_0_0_0_0_1_11_.INIT = 16'h7050; + LUT4_L com_cmm_u_cmm_cfgspace_low_addr_00_0_0_0_0_1_11_ ( + .I0(com_cmm_u_cmm_cfgspace_N_61347), + .I1(NlwRenamedSig_OI_cfg_dcommand[11]), + .I2(com_cmm_u_cmm_cfgspace_low_addr_00_0_0_0_0_0[11]), + .I3(com_cmm_u_cmm_cfgspace_sel_encodex_1[1]), + .LO(com_cmm_u_cmm_cfgspace_low_addr_00_0_0_0_0_1[11]) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_00_0_0_0_0_2_11_.INIT = 16'h135F; + LUT4 com_cmm_u_cmm_cfgspace_low_addr_00_0_0_0_0_2_11_ ( + .I0(com_cmm_u_cmm_cfgspace_N_61330), + .I1(com_cmm_u_cmm_cfgspace_N_61371), + .I2(com_cmm_bar0_reg_11_), + .I3(com_cmm_xrom_reg_11_), + .O(com_cmm_u_cmm_cfgspace_low_addr_00_0_0_0_0_2[11]) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_00_0_0_0_8_.INIT = 16'h153F; + LUT4_L com_cmm_u_cmm_cfgspace_low_addr_00_0_0_0_8_ ( + .I0(com_cmm_u_cmm_cfgspace_N_61330), + .I1(com_cmm_u_cmm_cfgspace_N_61340), + .I2(cfg_cfg_6102[8]), + .I3(com_cmm_bar0_reg_8_), + .LO(com_cmm_u_cmm_cfgspace_low_addr_00_0_0_0_8__5723) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_00_0_0_1_8_.INIT = 16'h153F; + LUT4 com_cmm_u_cmm_cfgspace_low_addr_00_0_0_1_8_ ( + .I0(com_cmm_u_cmm_cfgspace_N_61356), + .I1(com_cmm_u_cmm_cfgspace_N_61360), + .I2(NlwRenamedSig_OI_cfg_dcommand[8]), + .I3(com_cmm_msi_haddr[8]), + .O(com_cmm_u_cmm_cfgspace_low_addr_00_0_0_1_8__5722) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_00_0_0_0_3_.INIT = 16'h153F; + LUT4_L com_cmm_u_cmm_cfgspace_low_addr_00_0_0_0_3_ ( + .I0(com_cmm_u_cmm_cfgspace_N_61330), + .I1(com_cmm_u_cmm_cfgspace_N_61340), + .I2(cfg_cfg_6102[3]), + .I3(com_cmm_u_cmm_cfgspace_bar0_reg[3]), + .LO(com_cmm_u_cmm_cfgspace_low_addr_00_0_0_0_3__5738) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_00_0_0_1_3_.INIT = 16'h153F; + LUT4 com_cmm_u_cmm_cfgspace_low_addr_00_0_0_1_3_ ( + .I0(com_cmm_u_cmm_cfgspace_N_61356), + .I1(com_cmm_u_cmm_cfgspace_N_61360), + .I2(NlwRenamedSig_OI_cfg_dcommand[3]), + .I3(com_cmm_msi_haddr[3]), + .O(com_cmm_u_cmm_cfgspace_low_addr_00_0_0_1_3__5737) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_00_0_0_0_7_.INIT = 16'h153F; + LUT4_L com_cmm_u_cmm_cfgspace_low_addr_00_0_0_0_7_ ( + .I0(com_cmm_u_cmm_cfgspace_N_61330), + .I1(com_cmm_u_cmm_cfgspace_N_61340), + .I2(cfg_cfg_6102[7]), + .I3(com_cmm_bar0_reg_7_), + .LO(com_cmm_u_cmm_cfgspace_low_addr_00_0_0_0_7__5726) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_00_0_0_1_7_.INIT = 16'h153F; + LUT4 com_cmm_u_cmm_cfgspace_low_addr_00_0_0_1_7_ ( + .I0(com_cmm_u_cmm_cfgspace_N_61356), + .I1(com_cmm_u_cmm_cfgspace_N_61360), + .I2(NlwRenamedSig_OI_cfg_dcommand[7]), + .I3(com_cmm_msi_haddr[7]), + .O(com_cmm_u_cmm_cfgspace_low_addr_00_0_0_1_7__5725) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_00_0_0_0_0_10_.INIT = 16'h153F; + LUT4_L com_cmm_u_cmm_cfgspace_low_addr_00_0_0_0_0_10_ ( + .I0(com_cmm_u_cmm_cfgspace_N_61330), + .I1(com_cmm_u_cmm_cfgspace_N_61340), + .I2(cfg_cfg_6102[10]), + .I3(com_cmm_bar0_reg_10_), + .LO(com_cmm_u_cmm_cfgspace_low_addr_00_0_0_0_0_10__5717) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_00_0_0_0_1_10_.INIT = 16'h153F; + LUT4 com_cmm_u_cmm_cfgspace_low_addr_00_0_0_0_1_10_ ( + .I0(com_cmm_u_cmm_cfgspace_N_61356), + .I1(com_cmm_u_cmm_cfgspace_N_61360), + .I2(NlwRenamedSig_OI_cfg_dcommand[10]), + .I3(com_cmm_msi_haddr[10]), + .O(com_cmm_u_cmm_cfgspace_low_addr_00_0_0_0_1_10__5716) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_00_0_0_0_6_.INIT = 16'h153F; + LUT4_L com_cmm_u_cmm_cfgspace_low_addr_00_0_0_0_6_ ( + .I0(com_cmm_u_cmm_cfgspace_N_61330), + .I1(com_cmm_u_cmm_cfgspace_N_61340), + .I2(cfg_cfg_6102[6]), + .I3(com_cmm_bar0_reg_6_), + .LO(com_cmm_u_cmm_cfgspace_low_addr_00_0_0_0_6__5729) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_00_0_0_1_6_.INIT = 16'h153F; + LUT4 com_cmm_u_cmm_cfgspace_low_addr_00_0_0_1_6_ ( + .I0(com_cmm_u_cmm_cfgspace_N_61356), + .I1(com_cmm_u_cmm_cfgspace_N_61360), + .I2(NlwRenamedSig_OI_cfg_dcommand[6]), + .I3(com_cmm_msi_haddr[6]), + .O(com_cmm_u_cmm_cfgspace_low_addr_00_0_0_1_6__5728) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_00_0_0_0_0_9_.INIT = 16'h153F; + LUT4_L com_cmm_u_cmm_cfgspace_low_addr_00_0_0_0_0_9_ ( + .I0(com_cmm_u_cmm_cfgspace_N_61330), + .I1(com_cmm_u_cmm_cfgspace_N_61340), + .I2(cfg_cfg_6102[9]), + .I3(com_cmm_bar0_reg_9_), + .LO(com_cmm_u_cmm_cfgspace_low_addr_00_0_0_0_0_9__5720) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_00_0_0_0_1_9_.INIT = 16'h153F; + LUT4 com_cmm_u_cmm_cfgspace_low_addr_00_0_0_0_1_9_ ( + .I0(com_cmm_u_cmm_cfgspace_N_61356), + .I1(com_cmm_u_cmm_cfgspace_N_61360), + .I2(NlwRenamedSig_OI_cfg_dcommand[9]), + .I3(com_cmm_msi_haddr[9]), + .O(com_cmm_u_cmm_cfgspace_low_addr_00_0_0_0_1_9__5719) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_00_0_0_0_5_.INIT = 16'h153F; + LUT4_L com_cmm_u_cmm_cfgspace_low_addr_00_0_0_0_5_ ( + .I0(com_cmm_u_cmm_cfgspace_N_61330), + .I1(com_cmm_u_cmm_cfgspace_N_61340), + .I2(cfg_cfg_6102[5]), + .I3(com_cmm_bar0_reg_5_), + .LO(com_cmm_u_cmm_cfgspace_low_addr_00_0_0_0_5__5732) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_00_0_0_1_5_.INIT = 16'h153F; + LUT4 com_cmm_u_cmm_cfgspace_low_addr_00_0_0_1_5_ ( + .I0(com_cmm_u_cmm_cfgspace_N_61356), + .I1(com_cmm_u_cmm_cfgspace_N_61360), + .I2(NlwRenamedSig_OI_cfg_dcommand[5]), + .I3(com_cmm_msi_haddr[5]), + .O(com_cmm_u_cmm_cfgspace_low_addr_00_0_0_1_5__5731) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_00_0_0_0_0_2_.INIT = 16'h153F; + LUT4_L com_cmm_u_cmm_cfgspace_low_addr_00_0_0_0_0_2_ ( + .I0(com_cmm_u_cmm_cfgspace_N_61330), + .I1(com_cmm_u_cmm_cfgspace_N_61340), + .I2(cfg_cfg_6102[2]), + .I3(com_cmm_bar0_reg_2_), + .LO(com_cmm_u_cmm_cfgspace_low_addr_00_0_0_0_0_2__5741) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_00_0_0_0_1_2_.INIT = 16'h153F; + LUT4 com_cmm_u_cmm_cfgspace_low_addr_00_0_0_0_1_2_ ( + .I0(com_cmm_u_cmm_cfgspace_N_61356), + .I1(com_cmm_u_cmm_cfgspace_N_61360), + .I2(NlwRenamedSig_OI_cfg_dcommand[2]), + .I3(com_cmm_msi_haddr[2]), + .O(com_cmm_u_cmm_cfgspace_low_addr_00_0_0_0_1_2__5740) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_00_0_0_0_0_4_.INIT = 16'h153F; + LUT4_L com_cmm_u_cmm_cfgspace_low_addr_00_0_0_0_0_4_ ( + .I0(com_cmm_u_cmm_cfgspace_N_61330), + .I1(com_cmm_u_cmm_cfgspace_N_61340), + .I2(cfg_cfg_6102[4]), + .I3(com_cmm_bar0_reg_4_), + .LO(com_cmm_u_cmm_cfgspace_low_addr_00_0_0_0_0_4__5735) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_00_0_0_0_1_4_.INIT = 16'h153F; + LUT4 com_cmm_u_cmm_cfgspace_low_addr_00_0_0_0_1_4_ ( + .I0(com_cmm_u_cmm_cfgspace_N_61356), + .I1(com_cmm_u_cmm_cfgspace_N_61360), + .I2(NlwRenamedSig_OI_cfg_dcommand[4]), + .I3(com_cmm_msi_haddr[4]), + .O(com_cmm_u_cmm_cfgspace_low_addr_00_0_0_0_1_4__5734) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_00_i_0_0_0_0_0_.INIT = 16'hF351; + LUT4_L com_cmm_u_cmm_cfgspace_low_addr_00_i_0_0_0_0_0_ ( + .I0(com_cmm_u_cmm_cfgspace_N_61330), + .I1(com_cmm_u_cmm_cfgspace_N_61340), + .I2(cfg_cfg_6102[0]), + .I3(com_cmm_bar0_reg_0_), + .LO(com_cmm_u_cmm_cfgspace_low_addr_00_i_0_0_0_0[0]) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_00_i_0_0_0_1_0_.INIT = 16'hF531; + LUT4 com_cmm_u_cmm_cfgspace_low_addr_00_i_0_0_0_1_0_ ( + .I0(com_cmm_u_cmm_cfgspace_N_61356), + .I1(com_cmm_u_cmm_cfgspace_N_61371), + .I2(com_cmm_msi_haddr[0]), + .I3(com_cmm_xrom_reg_0_), + .O(com_cmm_u_cmm_cfgspace_low_addr_00_i_0_0_0_1_0__5745) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_00_i_0_0_0_2_0_.INIT = 16'hDDF5; + LUT4 com_cmm_u_cmm_cfgspace_low_addr_00_i_0_0_0_2_0_ ( + .I0(com_cmm_u_cmm_cfgspace_N_61316), + .I1(NlwRenamedSig_OI_cfg_dcommand[0]), + .I2(com_cmm_bar4_reg[0]), + .I3(com_cmm_u_cmm_cfgspace_sel_encodex_1[2]), + .O(com_cmm_u_cmm_cfgspace_low_addr_00_i_0_0_0_2_0__5744) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_00_i_0_0_0_1_16_.INIT = 16'hF531; + LUT4 com_cmm_u_cmm_cfgspace_low_addr_00_i_0_0_0_1_16_ ( + .I0(com_cmm_u_cmm_cfgspace_N_61356), + .I1(com_cmm_u_cmm_cfgspace_N_61371), + .I2(com_cmm_msi_haddr[16]), + .I3(com_cmm_xrom_reg_16_), + .O(com_cmm_u_cmm_cfgspace_low_addr_00_i_0_0_0_1_16__5705) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_00_i_0_0_0_2_16_.INIT = 16'hDDF5; + LUT4 com_cmm_u_cmm_cfgspace_low_addr_00_i_0_0_0_2_16_ ( + .I0(com_cmm_u_cmm_cfgspace_N_61316), + .I1(NlwRenamedSig_OI_cfg_dstatus_0_), + .I2(com_cmm_bar4_reg[16]), + .I3(com_cmm_u_cmm_cfgspace_sel_encodex_1[2]), + .O(com_cmm_u_cmm_cfgspace_low_addr_00_i_0_0_0_2_16__5704) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_00_0_0_0_0_0_12_.INIT = 16'h153F; + LUT4_L com_cmm_u_cmm_cfgspace_low_addr_00_0_0_0_0_0_12_ ( + .I0(com_cmm_u_cmm_cfgspace_N_61330), + .I1(com_cmm_u_cmm_cfgspace_N_61340), + .I2(cfg_cfg_6102[12]), + .I3(com_cmm_bar0_reg_12_), + .LO(com_cmm_u_cmm_cfgspace_low_addr_00_0_0_0_0_0[12]) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_00_0_0_0_0_1_12_.INIT = 16'h135F; + LUT4 com_cmm_u_cmm_cfgspace_low_addr_00_0_0_0_0_1_12_ ( + .I0(com_cmm_u_cmm_cfgspace_N_61356), + .I1(com_cmm_u_cmm_cfgspace_N_61371), + .I2(com_cmm_msi_haddr[12]), + .I3(com_cmm_xrom_reg_12_), + .O(com_cmm_u_cmm_cfgspace_low_addr_00_0_0_0_0_1[12]) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_00_0_0_0_0_2_12_.INIT = 16'h775F; + LUT4 com_cmm_u_cmm_cfgspace_low_addr_00_0_0_0_0_2_12_ ( + .I0(com_cmm_u_cmm_cfgspace_N_61316), + .I1(NlwRenamedSig_OI_cfg_dcommand[12]), + .I2(com_cmm_bar4_reg[12]), + .I3(com_cmm_u_cmm_cfgspace_sel_encodex_1[2]), + .O(com_cmm_u_cmm_cfgspace_low_addr_00_0_0_0_0_2[12]) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_00_0_0_0_0_13_.INIT = 16'h153F; + LUT4_L com_cmm_u_cmm_cfgspace_low_addr_00_0_0_0_0_13_ ( + .I0(com_cmm_u_cmm_cfgspace_N_61330), + .I1(com_cmm_u_cmm_cfgspace_N_61340), + .I2(cfg_cfg_6102[13]), + .I3(com_cmm_bar0_reg_13_), + .LO(com_cmm_u_cmm_cfgspace_low_addr_00_0_0_0_0_13__5712) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_00_0_0_0_1_13_.INIT = 16'h135F; + LUT4 com_cmm_u_cmm_cfgspace_low_addr_00_0_0_0_1_13_ ( + .I0(com_cmm_u_cmm_cfgspace_N_61356), + .I1(com_cmm_u_cmm_cfgspace_N_61371), + .I2(com_cmm_msi_haddr[13]), + .I3(com_cmm_xrom_reg_13_), + .O(com_cmm_u_cmm_cfgspace_low_addr_00_0_0_0_1_13__5711) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_00_0_0_0_2_13_.INIT = 16'h775F; + LUT4 com_cmm_u_cmm_cfgspace_low_addr_00_0_0_0_2_13_ ( + .I0(com_cmm_u_cmm_cfgspace_N_61316), + .I1(NlwRenamedSig_OI_cfg_dcommand[13]), + .I2(com_cmm_bar4_reg[13]), + .I3(com_cmm_u_cmm_cfgspace_sel_encodex_1[2]), + .O(com_cmm_u_cmm_cfgspace_low_addr_00_0_0_0_2[13]) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_00_0_0_0_21_.INIT = 16'h153F; + LUT4_L com_cmm_u_cmm_cfgspace_low_addr_00_0_0_0_21_ ( + .I0(com_cmm_u_cmm_cfgspace_N_59578_1), + .I1(com_cmm_u_cmm_cfgspace_N_61340), + .I2(cfg_cfg_6102[21]), + .I3(cfg_cfg_6102[517]), + .LO(com_cmm_u_cmm_cfgspace_low_addr_00_0_0_0_21__5700) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_00_0_0_1_21_.INIT = 16'h135F; + LUT4 com_cmm_u_cmm_cfgspace_low_addr_00_0_0_1_21_ ( + .I0(com_cmm_u_cmm_cfgspace_N_61330), + .I1(com_cmm_u_cmm_cfgspace_N_61356), + .I2(com_cmm_bar0_reg_21_), + .I3(com_cmm_msi_haddr[21]), + .O(com_cmm_u_cmm_cfgspace_low_addr_00_0_0_1_21__5699) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_00_0_0_2_21_.INIT = 16'h135F; + LUT4 com_cmm_u_cmm_cfgspace_low_addr_00_0_0_2_21_ ( + .I0(com_cmm_u_cmm_cfgspace_N_61360), + .I1(com_cmm_u_cmm_cfgspace_N_61371), + .I2(NlwRenamedSig_OI_cfg_dstatus_5_), + .I3(com_cmm_xrom_reg_21_), + .O(com_cmm_u_cmm_cfgspace_low_addr_00_0_0_2[21]) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_00_i_i_0_0_17_.INIT = 16'h153F; + LUT4_L com_cmm_u_cmm_cfgspace_low_addr_00_i_i_0_0_17_ ( + .I0(com_cmm_u_cmm_cfgspace_N_59578_1), + .I1(com_cmm_u_cmm_cfgspace_N_61340), + .I2(cfg_cfg_6102[17]), + .I3(cfg_cfg_6102[513]), + .LO(com_cmm_u_cmm_cfgspace_low_addr_00_i_i_0_0[17]) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_00_i_i_0_1_17_.INIT = 16'h135F; + LUT4 com_cmm_u_cmm_cfgspace_low_addr_00_i_i_0_1_17_ ( + .I0(com_cmm_u_cmm_cfgspace_N_61330), + .I1(com_cmm_u_cmm_cfgspace_N_61356), + .I2(com_cmm_bar0_reg_17_), + .I3(com_cmm_msi_haddr[17]), + .O(com_cmm_u_cmm_cfgspace_low_addr_00_i_i_0_1[17]) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_00_i_i_0_2_17_.INIT = 16'h135F; + LUT4 com_cmm_u_cmm_cfgspace_low_addr_00_i_i_0_2_17_ ( + .I0(com_cmm_u_cmm_cfgspace_N_61360), + .I1(com_cmm_u_cmm_cfgspace_N_61371), + .I2(NlwRenamedSig_OI_cfg_dstatus_1_), + .I3(com_cmm_xrom_reg_17_), + .O(com_cmm_u_cmm_cfgspace_low_addr_00_i_i_0_2[17]) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_00_i_i_0_0_19_.INIT = 16'h153F; + LUT4_L com_cmm_u_cmm_cfgspace_low_addr_00_i_i_0_0_19_ ( + .I0(com_cmm_u_cmm_cfgspace_N_59578_1), + .I1(com_cmm_u_cmm_cfgspace_N_61340), + .I2(cfg_cfg_6102[19]), + .I3(cfg_cfg_6102[515]), + .LO(com_cmm_u_cmm_cfgspace_low_addr_00_i_i_0_0[19]) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_00_i_i_0_1_19_.INIT = 16'h135F; + LUT4 com_cmm_u_cmm_cfgspace_low_addr_00_i_i_0_1_19_ ( + .I0(com_cmm_u_cmm_cfgspace_N_61330), + .I1(com_cmm_u_cmm_cfgspace_N_61356), + .I2(com_cmm_bar0_reg_19_), + .I3(com_cmm_msi_haddr[19]), + .O(com_cmm_u_cmm_cfgspace_low_addr_00_i_i_0_1[19]) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_00_i_i_0_2_19_.INIT = 16'h135F; + LUT4 com_cmm_u_cmm_cfgspace_low_addr_00_i_i_0_2_19_ ( + .I0(com_cmm_u_cmm_cfgspace_N_61360), + .I1(com_cmm_u_cmm_cfgspace_N_61371), + .I2(NlwRenamedSig_OI_cfg_dstatus_3_), + .I3(com_cmm_xrom_reg_19_), + .O(com_cmm_u_cmm_cfgspace_low_addr_00_i_i_0_2[19]) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_00_i_i_0_0_18_.INIT = 16'h153F; + LUT4_L com_cmm_u_cmm_cfgspace_low_addr_00_i_i_0_0_18_ ( + .I0(com_cmm_u_cmm_cfgspace_N_59578_1), + .I1(com_cmm_u_cmm_cfgspace_N_61340), + .I2(cfg_cfg_6102[18]), + .I3(cfg_cfg_6102[514]), + .LO(com_cmm_u_cmm_cfgspace_low_addr_00_i_i_0_0[18]) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_00_i_i_0_1_18_.INIT = 16'h135F; + LUT4 com_cmm_u_cmm_cfgspace_low_addr_00_i_i_0_1_18_ ( + .I0(com_cmm_u_cmm_cfgspace_N_61330), + .I1(com_cmm_u_cmm_cfgspace_N_61356), + .I2(com_cmm_bar0_reg_18_), + .I3(com_cmm_msi_haddr[18]), + .O(com_cmm_u_cmm_cfgspace_low_addr_00_i_i_0_1[18]) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_00_i_i_0_2_18_.INIT = 16'h135F; + LUT4 com_cmm_u_cmm_cfgspace_low_addr_00_i_i_0_2_18_ ( + .I0(com_cmm_u_cmm_cfgspace_N_61360), + .I1(com_cmm_u_cmm_cfgspace_N_61371), + .I2(NlwRenamedSig_OI_cfg_dstatus_2_), + .I3(com_cmm_xrom_reg_18_), + .O(com_cmm_u_cmm_cfgspace_low_addr_00_i_i_0_2[18]) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_00_i_i_0_0_0_29_.INIT = 16'h153F; + LUT4_L com_cmm_u_cmm_cfgspace_low_addr_00_i_i_0_0_0_29_ ( + .I0(com_cmm_u_cmm_cfgspace_N_59578_1), + .I1(com_cmm_u_cmm_cfgspace_N_61340), + .I2(cfg_cfg_6102[29]), + .I3(cfg_cfg_6102[525]), + .LO(com_cmm_u_cmm_cfgspace_low_addr_00_i_i_0_0_0[29]) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_00_i_i_0_0_1_29_.INIT = 16'h135F; + LUT4_L com_cmm_u_cmm_cfgspace_low_addr_00_i_i_0_0_1_29_ ( + .I0(com_cmm_u_cmm_cfgspace_N_61330), + .I1(com_cmm_u_cmm_cfgspace_N_61371), + .I2(com_cmm_bar0_reg_29_), + .I3(com_cmm_xrom_reg_29_), + .LO(com_cmm_u_cmm_cfgspace_low_addr_00_i_i_0_0_1[29]) + ); + defparam com_cmm_u_cmm_cfgspace_x3gio_decodepipe_l_sel_x4_3_i_0_0_o3.INIT = 16'h3210; + LUT4 com_cmm_u_cmm_cfgspace_x3gio_decodepipe_l_sel_x4_3_i_0_0_o3 ( + .I0(com_cmm_u_cmm_cfgspace_N_55879_i), + .I1(com_cmm_u_cmm_cfgspace_N_61355), + .I2(cfg_dwaddr_6099[0]), + .I3(com_cmm_cfg_addr[0]), + .O(com_cmm_u_cmm_cfgspace_sel_x4_3_i_0_0_o3) + ); + defparam com_cmm_u_cmm_cfgspace_x3gio_decodepipe_l_sel_x0_3_i_0_0_o3.INIT = 16'h0123; + LUT4 com_cmm_u_cmm_cfgspace_x3gio_decodepipe_l_sel_x0_3_i_0_0_o3 ( + .I0(com_cmm_u_cmm_cfgspace_N_55879_i), + .I1(com_cmm_u_cmm_cfgspace_N_61355), + .I2(cfg_dwaddr_6099[0]), + .I3(com_cmm_cfg_addr[0]), + .O(com_cmm_u_cmm_cfgspace_sel_x0_3_i_0_0_o3) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_01_7_0_am_1_.INIT = 16'h0CAA; + LUT4 com_cmm_u_cmm_cfgspace_low_addr_01_7_0_am_1_ ( + .I0(com_cmm_u_cmm_cfgspace_N_3731), + .I1(com_cmm_pme_pmcsr[1]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex_1[1]), + .I3(com_cmm_u_cmm_cfgspace_sel_encodex_1[2]), + .O(com_cmm_u_cmm_cfgspace_low_addr_01_7_0_am_1__5585) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_01_7_0_bm_1_.INIT = 16'hAA0C; + LUT4 com_cmm_u_cmm_cfgspace_low_addr_01_7_0_bm_1_ ( + .I0(com_cmm_u_cmm_cfgspace_N_3859), + .I1(com_cmm_bar1_reg[1]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex_1[1]), + .I3(com_cmm_u_cmm_cfgspace_sel_encodex_1[2]), + .O(com_cmm_u_cmm_cfgspace_low_addr_01_7_0_bm_1__5584) + ); + MUXF5 com_cmm_u_cmm_cfgspace_low_addr_01_7_0_1_ ( + .I0(com_cmm_u_cmm_cfgspace_low_addr_01_7_0_am_1__5585), + .I1(com_cmm_u_cmm_cfgspace_low_addr_01_7_0_bm_1__5584), + .O(com_cmm_u_cmm_cfgspace_low_addr_01[1]), + .S(com_cmm_u_cmm_cfgspace_sel_encodex_1[0]) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_01_7_0_am_2_.INIT = 16'h00CA; + LUT4 com_cmm_u_cmm_cfgspace_low_addr_01_7_0_am_2_ ( + .I0(NlwRenamedSig_OI_cfg_command_2_), + .I1(com_cmm_bar5_reg[2]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex_1[1]), + .I3(com_cmm_u_cmm_cfgspace_sel_encodex_1[2]), + .O(com_cmm_u_cmm_cfgspace_low_addr_01_7_0_am_2__5587) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_01_7_0_bm_2_.INIT = 16'hAA0C; + LUT4 com_cmm_u_cmm_cfgspace_low_addr_01_7_0_bm_2_ ( + .I0(com_cmm_u_cmm_cfgspace_N_3860), + .I1(com_cmm_bar1_reg[2]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex_1[1]), + .I3(com_cmm_u_cmm_cfgspace_sel_encodex_1[2]), + .O(com_cmm_u_cmm_cfgspace_low_addr_01_7_0_bm_2__5586) + ); + MUXF5 com_cmm_u_cmm_cfgspace_low_addr_01_7_0_2_ ( + .I0(com_cmm_u_cmm_cfgspace_low_addr_01_7_0_am_2__5587), + .I1(com_cmm_u_cmm_cfgspace_low_addr_01_7_0_bm_2__5586), + .O(com_cmm_u_cmm_cfgspace_low_addr_01[2]), + .S(com_cmm_u_cmm_cfgspace_sel_encodex_1[0]) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_01_7_0_bm_3_.INIT = 16'hAA0C; + LUT4 com_cmm_u_cmm_cfgspace_low_addr_01_7_0_bm_3_ ( + .I0(com_cmm_u_cmm_cfgspace_N_3861), + .I1(com_cmm_bar1_reg[3]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex_1[1]), + .I3(com_cmm_u_cmm_cfgspace_sel_encodex_1[2]), + .O(com_cmm_u_cmm_cfgspace_low_addr_01_7_0_bm_3__5588) + ); + MUXF5 com_cmm_u_cmm_cfgspace_low_addr_01_7_0_3_ ( + .I0(com_cmm_u_cmm_cfgspace_low_addr_01_7_0_am_0[3]), + .I1(com_cmm_u_cmm_cfgspace_low_addr_01_7_0_bm_3__5588), + .O(com_cmm_u_cmm_cfgspace_low_addr_01[3]), + .S(com_cmm_u_cmm_cfgspace_sel_encodex_1[0]) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_01_7_0_am_4_.INIT = 8'h08; + LUT3 com_cmm_u_cmm_cfgspace_low_addr_01_7_0_am_4_ ( + .I0(com_cmm_bar5_reg[4]), + .I1(com_cmm_u_cmm_cfgspace_sel_encodex_1[1]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex_1[2]), + .O(com_cmm_u_cmm_cfgspace_low_addr_01_7_0_am_4__5590) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_01_7_0_bm_4_.INIT = 16'hAA0C; + LUT4 com_cmm_u_cmm_cfgspace_low_addr_01_7_0_bm_4_ ( + .I0(com_cmm_u_cmm_cfgspace_N_3862), + .I1(com_cmm_bar1_reg[4]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex_1[1]), + .I3(com_cmm_u_cmm_cfgspace_sel_encodex_1[2]), + .O(com_cmm_u_cmm_cfgspace_low_addr_01_7_0_bm_4__5589) + ); + MUXF5 com_cmm_u_cmm_cfgspace_low_addr_01_7_0_4_ ( + .I0(com_cmm_u_cmm_cfgspace_low_addr_01_7_0_am_4__5590), + .I1(com_cmm_u_cmm_cfgspace_low_addr_01_7_0_bm_4__5589), + .O(com_cmm_u_cmm_cfgspace_low_addr_01[4]), + .S(com_cmm_u_cmm_cfgspace_sel_encodex_1[0]) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_01_7_0_am_5_.INIT = 8'h08; + LUT3 com_cmm_u_cmm_cfgspace_low_addr_01_7_0_am_5_ ( + .I0(com_cmm_bar5_reg[5]), + .I1(com_cmm_u_cmm_cfgspace_sel_encodex_1[1]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex_1[2]), + .O(com_cmm_u_cmm_cfgspace_low_addr_01_7_0_am_5__5592) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_01_7_0_bm_5_.INIT = 16'hAA0C; + LUT4 com_cmm_u_cmm_cfgspace_low_addr_01_7_0_bm_5_ ( + .I0(com_cmm_u_cmm_cfgspace_N_3863), + .I1(com_cmm_bar1_reg[5]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex_1[1]), + .I3(com_cmm_u_cmm_cfgspace_sel_encodex_1[2]), + .O(com_cmm_u_cmm_cfgspace_low_addr_01_7_0_bm_5__5591) + ); + MUXF5 com_cmm_u_cmm_cfgspace_low_addr_01_7_0_5_ ( + .I0(com_cmm_u_cmm_cfgspace_low_addr_01_7_0_am_5__5592), + .I1(com_cmm_u_cmm_cfgspace_low_addr_01_7_0_bm_5__5591), + .O(com_cmm_u_cmm_cfgspace_low_addr_01[5]), + .S(com_cmm_u_cmm_cfgspace_sel_encodex_1[0]) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_01_7_0_am_7_.INIT = 8'h08; + LUT3 com_cmm_u_cmm_cfgspace_low_addr_01_7_0_am_7_ ( + .I0(com_cmm_bar5_reg[7]), + .I1(com_cmm_u_cmm_cfgspace_sel_encodex_2[1]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex_1[2]), + .O(com_cmm_u_cmm_cfgspace_low_addr_01_7_0_am_7__5594) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_01_7_0_bm_7_.INIT = 16'hAA0C; + LUT4 com_cmm_u_cmm_cfgspace_low_addr_01_7_0_bm_7_ ( + .I0(com_cmm_u_cmm_cfgspace_N_3865), + .I1(com_cmm_bar1_reg[7]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex_2[1]), + .I3(com_cmm_u_cmm_cfgspace_sel_encodex_1[2]), + .O(com_cmm_u_cmm_cfgspace_low_addr_01_7_0_bm_7__5593) + ); + MUXF5 com_cmm_u_cmm_cfgspace_low_addr_01_7_0_7_ ( + .I0(com_cmm_u_cmm_cfgspace_low_addr_01_7_0_am_7__5594), + .I1(com_cmm_u_cmm_cfgspace_low_addr_01_7_0_bm_7__5593), + .O(com_cmm_u_cmm_cfgspace_low_addr_01[7]), + .S(com_cmm_u_cmm_cfgspace_sel_encodex_1[0]) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_01_7_0_am_8_.INIT = 16'h0CAA; + LUT4 com_cmm_u_cmm_cfgspace_low_addr_01_7_0_am_8_ ( + .I0(com_cmm_u_cmm_cfgspace_N_3738), + .I1(com_cmm_u_cmm_cfgspace_pme_pmcsr[8]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex_2[1]), + .I3(com_cmm_u_cmm_cfgspace_sel_encodex_1[2]), + .O(com_cmm_u_cmm_cfgspace_low_addr_01_7_0_am_8__5596) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_01_7_0_bm_8_.INIT = 16'hAA0C; + LUT4 com_cmm_u_cmm_cfgspace_low_addr_01_7_0_bm_8_ ( + .I0(com_cmm_u_cmm_cfgspace_N_3866), + .I1(com_cmm_bar1_reg[8]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex_2[1]), + .I3(com_cmm_u_cmm_cfgspace_sel_encodex_1[2]), + .O(com_cmm_u_cmm_cfgspace_low_addr_01_7_0_bm_8__5595) + ); + MUXF5 com_cmm_u_cmm_cfgspace_low_addr_01_7_0_8_ ( + .I0(com_cmm_u_cmm_cfgspace_low_addr_01_7_0_am_8__5596), + .I1(com_cmm_u_cmm_cfgspace_low_addr_01_7_0_bm_8__5595), + .O(com_cmm_u_cmm_cfgspace_low_addr_01[8]), + .S(com_cmm_u_cmm_cfgspace_sel_encodex_1[0]) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_01_7_0_am_9_.INIT = 16'h0CA0; + LUT4 com_cmm_u_cmm_cfgspace_low_addr_01_7_0_am_9_ ( + .I0(com_cmm_bar5_reg[9]), + .I1(com_cmm_u_cmm_cfgspace_pme_pmcsr[9]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex_2[1]), + .I3(com_cmm_u_cmm_cfgspace_sel_encodex_1[2]), + .O(com_cmm_u_cmm_cfgspace_low_addr_01_7_0_am_9__5598) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_01_7_0_bm_9_.INIT = 16'hAA0C; + LUT4 com_cmm_u_cmm_cfgspace_low_addr_01_7_0_bm_9_ ( + .I0(com_cmm_u_cmm_cfgspace_N_3867), + .I1(com_cmm_bar1_reg[9]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex_2[1]), + .I3(com_cmm_u_cmm_cfgspace_sel_encodex_1[2]), + .O(com_cmm_u_cmm_cfgspace_low_addr_01_7_0_bm_9__5597) + ); + MUXF5 com_cmm_u_cmm_cfgspace_low_addr_01_7_0_9_ ( + .I0(com_cmm_u_cmm_cfgspace_low_addr_01_7_0_am_9__5598), + .I1(com_cmm_u_cmm_cfgspace_low_addr_01_7_0_bm_9__5597), + .O(com_cmm_u_cmm_cfgspace_low_addr_01[9]), + .S(com_cmm_u_cmm_cfgspace_sel_encodex_1[0]) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_01_7_0_am_11_.INIT = 16'hAAC0; + LUT4 com_cmm_u_cmm_cfgspace_low_addr_01_7_0_am_11_ ( + .I0(com_cmm_u_cmm_cfgspace_N_3773), + .I1(com_cmm_bar5_reg[11]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex_2[1]), + .I3(com_cmm_u_cmm_cfgspace_sel_encodex_1[2]), + .O(com_cmm_u_cmm_cfgspace_low_addr_01_7_0_am_11__5600) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_01_7_0_bm_11_.INIT = 16'hAA0C; + LUT4 com_cmm_u_cmm_cfgspace_low_addr_01_7_0_bm_11_ ( + .I0(com_cmm_u_cmm_cfgspace_N_3869), + .I1(com_cmm_bar1_reg[11]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex_2[1]), + .I3(com_cmm_u_cmm_cfgspace_sel_encodex_1[2]), + .O(com_cmm_u_cmm_cfgspace_low_addr_01_7_0_bm_11__5599) + ); + MUXF5 com_cmm_u_cmm_cfgspace_low_addr_01_7_0_11_ ( + .I0(com_cmm_u_cmm_cfgspace_low_addr_01_7_0_am_11__5600), + .I1(com_cmm_u_cmm_cfgspace_low_addr_01_7_0_bm_11__5599), + .O(com_cmm_u_cmm_cfgspace_low_addr_01[11]), + .S(com_cmm_u_cmm_cfgspace_sel_encodex_1[0]) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_01_7_0_am_13_.INIT = 16'hAAC0; + LUT4 com_cmm_u_cmm_cfgspace_low_addr_01_7_0_am_13_ ( + .I0(com_cmm_u_cmm_cfgspace_N_3775), + .I1(com_cmm_bar5_reg[13]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex_2[1]), + .I3(com_cmm_u_cmm_cfgspace_sel_encodex_1[2]), + .O(com_cmm_u_cmm_cfgspace_low_addr_01_7_0_am_13__5602) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_01_7_0_bm_13_.INIT = 16'hAA0C; + LUT4 com_cmm_u_cmm_cfgspace_low_addr_01_7_0_bm_13_ ( + .I0(com_cmm_u_cmm_cfgspace_N_3871), + .I1(com_cmm_bar1_reg[13]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex_2[1]), + .I3(com_cmm_u_cmm_cfgspace_sel_encodex_1[2]), + .O(com_cmm_u_cmm_cfgspace_low_addr_01_7_0_bm_13__5601) + ); + MUXF5 com_cmm_u_cmm_cfgspace_low_addr_01_7_0_13_ ( + .I0(com_cmm_u_cmm_cfgspace_low_addr_01_7_0_am_13__5602), + .I1(com_cmm_u_cmm_cfgspace_low_addr_01_7_0_bm_13__5601), + .O(com_cmm_u_cmm_cfgspace_low_addr_01[13]), + .S(com_cmm_u_cmm_cfgspace_sel_encodex_1[0]) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_01_7_0_am_15_.INIT = 16'hAAC0; + LUT4 com_cmm_u_cmm_cfgspace_low_addr_01_7_0_am_15_ ( + .I0(com_cmm_u_cmm_cfgspace_N_3777), + .I1(com_cmm_bar5_reg[15]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex_2[1]), + .I3(com_cmm_u_cmm_cfgspace_sel_encodex_1[2]), + .O(com_cmm_u_cmm_cfgspace_low_addr_01_7_0_am_15__5604) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_01_7_0_bm_15_.INIT = 16'hAA0C; + LUT4 com_cmm_u_cmm_cfgspace_low_addr_01_7_0_bm_15_ ( + .I0(com_cmm_u_cmm_cfgspace_N_3873), + .I1(com_cmm_bar1_reg[15]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex_2[1]), + .I3(com_cmm_u_cmm_cfgspace_sel_encodex_1[2]), + .O(com_cmm_u_cmm_cfgspace_low_addr_01_7_0_bm_15__5603) + ); + MUXF5 com_cmm_u_cmm_cfgspace_low_addr_01_7_0_15_ ( + .I0(com_cmm_u_cmm_cfgspace_low_addr_01_7_0_am_15__5604), + .I1(com_cmm_u_cmm_cfgspace_low_addr_01_7_0_bm_15__5603), + .O(com_cmm_u_cmm_cfgspace_low_addr_01[15]), + .S(com_cmm_u_cmm_cfgspace_sel_encodex_1[0]) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_01_7_0_am_19_.INIT = 16'hC0AA; + LUT4 com_cmm_u_cmm_cfgspace_low_addr_01_7_0_am_19_ ( + .I0(com_cmm_u_cmm_cfgspace_N_3749), + .I1(cfg_cfg_6102[419]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex_2[1]), + .I3(com_cmm_u_cmm_cfgspace_sel_encodex_1[2]), + .O(com_cmm_u_cmm_cfgspace_low_addr_01_7_0_am_19__5606) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_01_7_0_bm_19_.INIT = 16'hA00C; + LUT4 com_cmm_u_cmm_cfgspace_low_addr_01_7_0_bm_19_ ( + .I0(cfg_cfg_6102[675]), + .I1(com_cmm_bar1_reg[19]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex_2[1]), + .I3(com_cmm_u_cmm_cfgspace_sel_encodex_1[2]), + .O(com_cmm_u_cmm_cfgspace_low_addr_01_7_0_bm_19__5605) + ); + MUXF5 com_cmm_u_cmm_cfgspace_low_addr_01_7_0_19_ ( + .I0(com_cmm_u_cmm_cfgspace_low_addr_01_7_0_am_19__5606), + .I1(com_cmm_u_cmm_cfgspace_low_addr_01_7_0_bm_19__5605), + .O(com_cmm_u_cmm_cfgspace_low_addr_01[19]), + .S(com_cmm_u_cmm_cfgspace_sel_encodex_1[0]) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_am_0_.INIT = 16'h00AC; + LUT4 com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_am_0_ ( + .I0(cfg_cfg_6102[288]), + .I1(com_cmm_u_cmm_cfgspace_cache_line[0]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex_2[1]), + .I3(com_cmm_u_cmm_cfgspace_sel_encodex_1[2]), + .O(com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_am[0]) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_bm_0_.INIT = 16'h3A0A; + LUT4 com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_bm_0_ ( + .I0(com_cmm_u_cmm_cfgspace_N_4050), + .I1(com_cmm_u_cmm_cfgspace_sel_encodex_2[1]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex_1[2]), + .I3(com_cmm_u_cmm_cfgspace_x_dcap[0]), + .O(com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_bm[0]) + ); + MUXF5 com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_0_ ( + .I0(com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_am[0]), + .I1(com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_bm[0]), + .O(com_cmm_u_cmm_cfgspace_low_addr_03_q_4[0]), + .S(com_cmm_u_cmm_cfgspace_sel_encodex_1[0]) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_am_1_.INIT = 16'h00AC; + LUT4 com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_am_1_ ( + .I0(cfg_cfg_6102[289]), + .I1(com_cmm_u_cmm_cfgspace_cache_line[1]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex_2[1]), + .I3(com_cmm_u_cmm_cfgspace_sel_encodex_1[2]), + .O(com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_am[1]) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_bm_1_.INIT = 16'h3A0A; + LUT4 com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_bm_1_ ( + .I0(com_cmm_u_cmm_cfgspace_N_4051), + .I1(com_cmm_u_cmm_cfgspace_sel_encodex_2[1]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex_1[2]), + .I3(com_cmm_u_cmm_cfgspace_x_dcap[1]), + .O(com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_bm[1]) + ); + MUXF5 com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_1_ ( + .I0(com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_am[1]), + .I1(com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_bm[1]), + .O(com_cmm_u_cmm_cfgspace_low_addr_03_q_4[1]), + .S(com_cmm_u_cmm_cfgspace_sel_encodex_1[0]) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_am_2_.INIT = 16'h0CAA; + LUT4 com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_am_2_ ( + .I0(com_cmm_u_cmm_cfgspace_N_3956), + .I1(com_cmm_msi_laddr[2]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex_2[1]), + .I3(com_cmm_u_cmm_cfgspace_sel_encodex_1[2]), + .O(com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_am[2]) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_bm_2_.INIT = 16'h3A0A; + LUT4 com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_bm_2_ ( + .I0(com_cmm_u_cmm_cfgspace_N_4052), + .I1(com_cmm_u_cmm_cfgspace_sel_encodex_2[1]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex_1[2]), + .I3(com_cmm_u_cmm_cfgspace_x_dcap[2]), + .O(com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_bm[2]) + ); + MUXF5 com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_2_ ( + .I0(com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_am[2]), + .I1(com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_bm[2]), + .O(com_cmm_u_cmm_cfgspace_low_addr_03_q_4[2]), + .S(com_cmm_u_cmm_cfgspace_sel_encodex_1[0]) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_am_3_.INIT = 16'h0CAA; + LUT4 com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_am_3_ ( + .I0(com_cmm_u_cmm_cfgspace_N_3957), + .I1(com_cmm_msi_laddr[3]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex_2[1]), + .I3(com_cmm_u_cmm_cfgspace_sel_encodex_1[2]), + .O(com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_am[3]) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_bm_3_.INIT = 16'h3A0A; + LUT4 com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_bm_3_ ( + .I0(com_cmm_u_cmm_cfgspace_N_4053), + .I1(com_cmm_u_cmm_cfgspace_sel_encodex_2[1]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex_1[2]), + .I3(com_cmm_u_cmm_cfgspace_x_dcap[3]), + .O(com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_bm[3]) + ); + MUXF5 com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_3_ ( + .I0(com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_am[3]), + .I1(com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_bm[3]), + .O(com_cmm_u_cmm_cfgspace_low_addr_03_q_4[3]), + .S(com_cmm_u_cmm_cfgspace_sel_encodex_1[0]) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_am_4_.INIT = 16'h0CAA; + LUT4 com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_am_4_ ( + .I0(com_cmm_u_cmm_cfgspace_N_3958), + .I1(com_cmm_msi_laddr[4]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex_2[1]), + .I3(com_cmm_u_cmm_cfgspace_sel_encodex_1[2]), + .O(com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_am[4]) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_bm_4_.INIT = 16'h3A0A; + LUT4 com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_bm_4_ ( + .I0(com_cmm_u_cmm_cfgspace_N_4054), + .I1(com_cmm_u_cmm_cfgspace_sel_encodex_2[1]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex_1[2]), + .I3(com_cmm_u_cmm_cfgspace_x_dcap[4]), + .O(com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_bm[4]) + ); + MUXF5 com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_4_ ( + .I0(com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_am[4]), + .I1(com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_bm[4]), + .O(com_cmm_u_cmm_cfgspace_low_addr_03_q_4[4]), + .S(com_cmm_u_cmm_cfgspace_sel_encodex_1[0]) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_am_5_.INIT = 16'h0CAA; + LUT4 com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_am_5_ ( + .I0(com_cmm_u_cmm_cfgspace_N_3959), + .I1(com_cmm_msi_laddr[5]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex_2[1]), + .I3(com_cmm_u_cmm_cfgspace_sel_encodex_1[2]), + .O(com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_am[5]) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_bm_5_.INIT = 16'h3A0A; + LUT4 com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_bm_5_ ( + .I0(com_cmm_u_cmm_cfgspace_N_4055), + .I1(com_cmm_u_cmm_cfgspace_sel_encodex_2[1]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex_1[2]), + .I3(com_cmm_u_cmm_cfgspace_x_dcap[5]), + .O(com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_bm[5]) + ); + MUXF5 com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_5_ ( + .I0(com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_am[5]), + .I1(com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_bm[5]), + .O(com_cmm_u_cmm_cfgspace_low_addr_03_q_4[5]), + .S(com_cmm_u_cmm_cfgspace_sel_encodex_1[0]) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_am_6_.INIT = 16'h0CAA; + LUT4 com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_am_6_ ( + .I0(com_cmm_u_cmm_cfgspace_N_3960), + .I1(com_cmm_msi_laddr[6]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex_2[1]), + .I3(com_cmm_u_cmm_cfgspace_sel_encodex_1[2]), + .O(com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_am[6]) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_bm_6_.INIT = 16'h3A0A; + LUT4 com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_bm_6_ ( + .I0(com_cmm_u_cmm_cfgspace_N_4056), + .I1(com_cmm_u_cmm_cfgspace_sel_encodex_2[1]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex_1[2]), + .I3(com_cmm_u_cmm_cfgspace_x_dcap[6]), + .O(com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_bm[6]) + ); + MUXF5 com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_6_ ( + .I0(com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_am[6]), + .I1(com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_bm[6]), + .O(com_cmm_u_cmm_cfgspace_low_addr_03_q_4[6]), + .S(com_cmm_u_cmm_cfgspace_sel_encodex_1[0]) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_am_7_.INIT = 16'h0CAA; + LUT4 com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_am_7_ ( + .I0(com_cmm_u_cmm_cfgspace_N_3961), + .I1(com_cmm_msi_laddr[7]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex_2[1]), + .I3(com_cmm_u_cmm_cfgspace_sel_encodex_1[2]), + .O(com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_am[7]) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_bm_7_.INIT = 16'h3A0A; + LUT4 com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_bm_7_ ( + .I0(com_cmm_u_cmm_cfgspace_N_4057), + .I1(com_cmm_u_cmm_cfgspace_sel_encodex_2[1]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex_1[2]), + .I3(com_cmm_u_cmm_cfgspace_x_dcap[7]), + .O(com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_bm[7]) + ); + MUXF5 com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_7_ ( + .I0(com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_am[7]), + .I1(com_cmm_u_cmm_cfgspace_low_addr_03_q_4_7_0_bm[7]), + .O(com_cmm_u_cmm_cfgspace_low_addr_03_q_4[7]), + .S(com_cmm_u_cmm_cfgspace_sel_encodex_1[0]) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_02_7_0_am_0_.INIT = 16'hCFAA; + LUT4 com_cmm_u_cmm_cfgspace_low_addr_02_7_0_am_0_ ( + .I0(com_cmm_u_cmm_cfgspace_N_4578), + .I1(NlwRenamedSig_OI_cfg_lcommand_0_), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex_2[1]), + .I3(com_cmm_u_cmm_cfgspace_sel_encodex_1[2]), + .O(com_cmm_u_cmm_cfgspace_low_addr_02_7_0_am_0__5608) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_02_7_0_bm_0_.INIT = 16'hAA0C; + LUT4 com_cmm_u_cmm_cfgspace_low_addr_02_7_0_bm_0_ ( + .I0(com_cmm_u_cmm_cfgspace_N_4706), + .I1(com_cmm_bar2_reg[0]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex_2[1]), + .I3(com_cmm_u_cmm_cfgspace_sel_encodex_1[2]), + .O(com_cmm_u_cmm_cfgspace_low_addr_02_7_0_bm_0__5607) + ); + MUXF5 com_cmm_u_cmm_cfgspace_low_addr_02_7_0_0_ ( + .I0(com_cmm_u_cmm_cfgspace_low_addr_02_7_0_am_0__5608), + .I1(com_cmm_u_cmm_cfgspace_low_addr_02_7_0_bm_0__5607), + .O(com_cmm_u_cmm_cfgspace_low_addr_02[0]), + .S(com_cmm_u_cmm_cfgspace_sel_encodex_1[0]) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_02_7_0_am_1_.INIT = 16'hC0AA; + LUT4 com_cmm_u_cmm_cfgspace_low_addr_02_7_0_am_1_ ( + .I0(com_cmm_u_cmm_cfgspace_N_4579), + .I1(NlwRenamedSig_OI_cfg_lcommand_1_), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex_2[1]), + .I3(com_cmm_u_cmm_cfgspace_sel_encodex_1[2]), + .O(com_cmm_u_cmm_cfgspace_low_addr_02_7_0_am_1__5610) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_02_7_0_bm_1_.INIT = 16'hAA0C; + LUT4 com_cmm_u_cmm_cfgspace_low_addr_02_7_0_bm_1_ ( + .I0(com_cmm_u_cmm_cfgspace_N_4707), + .I1(com_cmm_bar2_reg[1]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex_2[1]), + .I3(com_cmm_u_cmm_cfgspace_sel_encodex_1[2]), + .O(com_cmm_u_cmm_cfgspace_low_addr_02_7_0_bm_1__5609) + ); + MUXF5 com_cmm_u_cmm_cfgspace_low_addr_02_7_0_1_ ( + .I0(com_cmm_u_cmm_cfgspace_low_addr_02_7_0_am_1__5610), + .I1(com_cmm_u_cmm_cfgspace_low_addr_02_7_0_bm_1__5609), + .O(com_cmm_u_cmm_cfgspace_low_addr_02[1]), + .S(com_cmm_u_cmm_cfgspace_sel_encodex_1[0]) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_02_7_0_am_2_.INIT = 16'h0FCA; + LUT4 com_cmm_u_cmm_cfgspace_low_addr_02_7_0_am_2_ ( + .I0(cfg_cfg_6102[34]), + .I1(cfg_cfg_6102[258]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex_2[1]), + .I3(com_cmm_u_cmm_cfgspace_sel_encodex_1[2]), + .O(com_cmm_u_cmm_cfgspace_low_addr_02_7_0_am_2__5612) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_02_7_0_bm_2_.INIT = 16'hAA0C; + LUT4 com_cmm_u_cmm_cfgspace_low_addr_02_7_0_bm_2_ ( + .I0(com_cmm_u_cmm_cfgspace_N_4708), + .I1(com_cmm_bar2_reg[2]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex_2[1]), + .I3(com_cmm_u_cmm_cfgspace_sel_encodex_1[2]), + .O(com_cmm_u_cmm_cfgspace_low_addr_02_7_0_bm_2__5611) + ); + MUXF5 com_cmm_u_cmm_cfgspace_low_addr_02_7_0_2_ ( + .I0(com_cmm_u_cmm_cfgspace_low_addr_02_7_0_am_2__5612), + .I1(com_cmm_u_cmm_cfgspace_low_addr_02_7_0_bm_2__5611), + .O(com_cmm_u_cmm_cfgspace_low_addr_02[2]), + .S(com_cmm_u_cmm_cfgspace_sel_encodex_1[0]) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_02_7_0_am_3_.INIT = 16'hC0AA; + LUT4 com_cmm_u_cmm_cfgspace_low_addr_02_7_0_am_3_ ( + .I0(com_cmm_u_cmm_cfgspace_N_4581), + .I1(NlwRenamedSig_OI_cfg_lcommand_3_), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex_2[1]), + .I3(com_cmm_u_cmm_cfgspace_sel_encodex_1[2]), + .O(com_cmm_u_cmm_cfgspace_low_addr_02_7_0_am_3__5614) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_02_7_0_bm_3_.INIT = 16'hAA0C; + LUT4 com_cmm_u_cmm_cfgspace_low_addr_02_7_0_bm_3_ ( + .I0(com_cmm_u_cmm_cfgspace_N_4709), + .I1(com_cmm_bar2_reg[3]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex_2[1]), + .I3(com_cmm_u_cmm_cfgspace_sel_encodex_1[2]), + .O(com_cmm_u_cmm_cfgspace_low_addr_02_7_0_bm_3__5613) + ); + MUXF5 com_cmm_u_cmm_cfgspace_low_addr_02_7_0_3_ ( + .I0(com_cmm_u_cmm_cfgspace_low_addr_02_7_0_am_3__5614), + .I1(com_cmm_u_cmm_cfgspace_low_addr_02_7_0_bm_3__5613), + .O(com_cmm_u_cmm_cfgspace_low_addr_02[3]), + .S(com_cmm_u_cmm_cfgspace_sel_encodex_1[0]) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_02_7_0_am_4_.INIT = 16'h00CA; + LUT4 com_cmm_u_cmm_cfgspace_low_addr_02_7_0_am_4_ ( + .I0(cfg_cfg_6102[36]), + .I1(cfg_cfg_6102[260]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex_2[1]), + .I3(com_cmm_u_cmm_cfgspace_sel_encodex_1[2]), + .O(com_cmm_u_cmm_cfgspace_low_addr_02_7_0_am_4__5616) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_02_7_0_bm_4_.INIT = 16'hAA0C; + LUT4 com_cmm_u_cmm_cfgspace_low_addr_02_7_0_bm_4_ ( + .I0(com_cmm_u_cmm_cfgspace_N_4710), + .I1(com_cmm_bar2_reg[4]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex_2[1]), + .I3(com_cmm_u_cmm_cfgspace_sel_encodex_1[2]), + .O(com_cmm_u_cmm_cfgspace_low_addr_02_7_0_bm_4__5615) + ); + MUXF5 com_cmm_u_cmm_cfgspace_low_addr_02_7_0_4_ ( + .I0(com_cmm_u_cmm_cfgspace_low_addr_02_7_0_am_4__5616), + .I1(com_cmm_u_cmm_cfgspace_low_addr_02_7_0_bm_4__5615), + .O(com_cmm_u_cmm_cfgspace_low_addr_02[4]), + .S(com_cmm_u_cmm_cfgspace_sel_encodex_1[0]) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_02_7_0_am_5_.INIT = 16'h00CA; + LUT4 com_cmm_u_cmm_cfgspace_low_addr_02_7_0_am_5_ ( + .I0(cfg_cfg_6102[37]), + .I1(cfg_cfg_6102[261]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex_2[1]), + .I3(com_cmm_u_cmm_cfgspace_sel_encodex_1[2]), + .O(com_cmm_u_cmm_cfgspace_low_addr_02_7_0_am_5__5618) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_02_7_0_bm_5_.INIT = 16'hAA0C; + LUT4 com_cmm_u_cmm_cfgspace_low_addr_02_7_0_bm_5_ ( + .I0(com_cmm_u_cmm_cfgspace_N_4711), + .I1(com_cmm_bar2_reg[5]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex_2[1]), + .I3(com_cmm_u_cmm_cfgspace_sel_encodex_1[2]), + .O(com_cmm_u_cmm_cfgspace_low_addr_02_7_0_bm_5__5617) + ); + MUXF5 com_cmm_u_cmm_cfgspace_low_addr_02_7_0_5_ ( + .I0(com_cmm_u_cmm_cfgspace_low_addr_02_7_0_am_5__5618), + .I1(com_cmm_u_cmm_cfgspace_low_addr_02_7_0_bm_5__5617), + .O(com_cmm_u_cmm_cfgspace_low_addr_02[5]), + .S(com_cmm_u_cmm_cfgspace_sel_encodex_1[0]) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_02_7_0_am_17_.INIT = 16'h00CA; + LUT4 com_cmm_u_cmm_cfgspace_low_addr_02_7_0_am_17_ ( + .I0(cfg_cfg_6102[49]), + .I1(cfg_cfg_6102[273]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex_2[1]), + .I3(com_cmm_u_cmm_cfgspace_sel_encodex_1[2]), + .O(com_cmm_u_cmm_cfgspace_low_addr_02_7_0_am_17__5620) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_02_7_0_bm_17_.INIT = 16'hAA0C; + LUT4 com_cmm_u_cmm_cfgspace_low_addr_02_7_0_bm_17_ ( + .I0(com_cmm_u_cmm_cfgspace_N_4723), + .I1(com_cmm_bar2_reg[17]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex_2[1]), + .I3(com_cmm_u_cmm_cfgspace_sel_encodex_1[2]), + .O(com_cmm_u_cmm_cfgspace_low_addr_02_7_0_bm_17__5619) + ); + MUXF5 com_cmm_u_cmm_cfgspace_low_addr_02_7_0_17_ ( + .I0(com_cmm_u_cmm_cfgspace_low_addr_02_7_0_am_17__5620), + .I1(com_cmm_u_cmm_cfgspace_low_addr_02_7_0_bm_17__5619), + .O(com_cmm_u_cmm_cfgspace_low_addr_02[17]), + .S(com_cmm_u_cmm_cfgspace_sel_encodex_1[0]) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_02_7_0_am_18_.INIT = 16'h00CA; + LUT4 com_cmm_u_cmm_cfgspace_low_addr_02_7_0_am_18_ ( + .I0(cfg_cfg_6102[50]), + .I1(cfg_cfg_6102[274]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex_2[1]), + .I3(com_cmm_u_cmm_cfgspace_sel_encodex_2[2]), + .O(com_cmm_u_cmm_cfgspace_low_addr_02_7_0_am_18__5622) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_02_7_0_bm_18_.INIT = 16'hAA0C; + LUT4 com_cmm_u_cmm_cfgspace_low_addr_02_7_0_bm_18_ ( + .I0(com_cmm_u_cmm_cfgspace_N_4724), + .I1(com_cmm_bar2_reg[18]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex_2[1]), + .I3(com_cmm_u_cmm_cfgspace_sel_encodex_2[2]), + .O(com_cmm_u_cmm_cfgspace_low_addr_02_7_0_bm_18__5621) + ); + MUXF5 com_cmm_u_cmm_cfgspace_low_addr_02_7_0_18_ ( + .I0(com_cmm_u_cmm_cfgspace_low_addr_02_7_0_am_18__5622), + .I1(com_cmm_u_cmm_cfgspace_low_addr_02_7_0_bm_18__5621), + .O(com_cmm_u_cmm_cfgspace_low_addr_02[18]), + .S(com_cmm_u_cmm_cfgspace_sel_encodex_1[0]) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_02_7_0_am_19_.INIT = 16'h00CA; + LUT4 com_cmm_u_cmm_cfgspace_low_addr_02_7_0_am_19_ ( + .I0(cfg_cfg_6102[51]), + .I1(cfg_cfg_6102[275]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex_2[1]), + .I3(com_cmm_u_cmm_cfgspace_sel_encodex_2[2]), + .O(com_cmm_u_cmm_cfgspace_low_addr_02_7_0_am_19__5624) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_02_7_0_bm_19_.INIT = 16'hAA0C; + LUT4 com_cmm_u_cmm_cfgspace_low_addr_02_7_0_bm_19_ ( + .I0(com_cmm_u_cmm_cfgspace_N_4725), + .I1(com_cmm_bar2_reg[19]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex_2[1]), + .I3(com_cmm_u_cmm_cfgspace_sel_encodex_2[2]), + .O(com_cmm_u_cmm_cfgspace_low_addr_02_7_0_bm_19__5623) + ); + MUXF5 com_cmm_u_cmm_cfgspace_low_addr_02_7_0_19_ ( + .I0(com_cmm_u_cmm_cfgspace_low_addr_02_7_0_am_19__5624), + .I1(com_cmm_u_cmm_cfgspace_low_addr_02_7_0_bm_19__5623), + .O(com_cmm_u_cmm_cfgspace_low_addr_02[19]), + .S(com_cmm_u_cmm_cfgspace_sel_encodex_1[0]) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_02_7_0_am_20_.INIT = 16'hC0AA; + LUT4 com_cmm_u_cmm_cfgspace_low_addr_02_7_0_am_20_ ( + .I0(com_cmm_u_cmm_cfgspace_N_4598), + .I1(NlwRenamedSig_OI_cfg_lstatus_4_), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex_2[1]), + .I3(com_cmm_u_cmm_cfgspace_sel_encodex_2[2]), + .O(com_cmm_u_cmm_cfgspace_low_addr_02_7_0_am_20__5626) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_02_7_0_bm_20_.INIT = 16'hAA0C; + LUT4 com_cmm_u_cmm_cfgspace_low_addr_02_7_0_bm_20_ ( + .I0(com_cmm_u_cmm_cfgspace_N_4726), + .I1(com_cmm_bar2_reg[20]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex_2[1]), + .I3(com_cmm_u_cmm_cfgspace_sel_encodex_2[2]), + .O(com_cmm_u_cmm_cfgspace_low_addr_02_7_0_bm_20__5625) + ); + MUXF5 com_cmm_u_cmm_cfgspace_low_addr_02_7_0_20_ ( + .I0(com_cmm_u_cmm_cfgspace_low_addr_02_7_0_am_20__5626), + .I1(com_cmm_u_cmm_cfgspace_low_addr_02_7_0_bm_20__5625), + .O(com_cmm_u_cmm_cfgspace_low_addr_02[20]), + .S(com_cmm_u_cmm_cfgspace_sel_encodex_1[0]) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_02_7_0_am_21_.INIT = 16'h00CA; + LUT4 com_cmm_u_cmm_cfgspace_low_addr_02_7_0_am_21_ ( + .I0(cfg_cfg_6102[53]), + .I1(cfg_cfg_6102[277]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex_2[1]), + .I3(com_cmm_u_cmm_cfgspace_sel_encodex_2[2]), + .O(com_cmm_u_cmm_cfgspace_low_addr_02_7_0_am_21__5628) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_02_7_0_bm_21_.INIT = 16'hAA0C; + LUT4 com_cmm_u_cmm_cfgspace_low_addr_02_7_0_bm_21_ ( + .I0(com_cmm_u_cmm_cfgspace_N_4727), + .I1(com_cmm_bar2_reg[21]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex_2[1]), + .I3(com_cmm_u_cmm_cfgspace_sel_encodex_2[2]), + .O(com_cmm_u_cmm_cfgspace_low_addr_02_7_0_bm_21__5627) + ); + MUXF5 com_cmm_u_cmm_cfgspace_low_addr_02_7_0_21_ ( + .I0(com_cmm_u_cmm_cfgspace_low_addr_02_7_0_am_21__5628), + .I1(com_cmm_u_cmm_cfgspace_low_addr_02_7_0_bm_21__5627), + .O(com_cmm_u_cmm_cfgspace_low_addr_02[21]), + .S(com_cmm_u_cmm_cfgspace_sel_encodex[0]) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_02_7_0_am_22_.INIT = 16'hA0CC; + LUT4 com_cmm_u_cmm_cfgspace_low_addr_02_7_0_am_22_ ( + .I0(NlwRenamedSig_OI_cfg_lstatus_6_), + .I1(com_cmm_u_cmm_cfgspace_N_4600), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex_2[1]), + .I3(com_cmm_u_cmm_cfgspace_sel_encodex_2[2]), + .O(com_cmm_u_cmm_cfgspace_low_addr_02_7_0_am_22__5630) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_02_7_0_bm_22_.INIT = 16'hAA0C; + LUT4 com_cmm_u_cmm_cfgspace_low_addr_02_7_0_bm_22_ ( + .I0(com_cmm_u_cmm_cfgspace_N_4728), + .I1(com_cmm_bar2_reg[22]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex_2[1]), + .I3(com_cmm_u_cmm_cfgspace_sel_encodex_2[2]), + .O(com_cmm_u_cmm_cfgspace_low_addr_02_7_0_bm_22__5629) + ); + MUXF5 com_cmm_u_cmm_cfgspace_low_addr_02_7_0_22_ ( + .I0(com_cmm_u_cmm_cfgspace_low_addr_02_7_0_am_22__5630), + .I1(com_cmm_u_cmm_cfgspace_low_addr_02_7_0_bm_22__5629), + .O(com_cmm_u_cmm_cfgspace_low_addr_02[22]), + .S(com_cmm_u_cmm_cfgspace_sel_encodex[0]) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_02_7_0_am_23_.INIT = 16'h0FCA; + LUT4 com_cmm_u_cmm_cfgspace_low_addr_02_7_0_am_23_ ( + .I0(cfg_cfg_6102[55]), + .I1(cfg_cfg_6102[279]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex_2[1]), + .I3(com_cmm_u_cmm_cfgspace_sel_encodex_2[2]), + .O(com_cmm_u_cmm_cfgspace_low_addr_02_7_0_am_23__5632) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_02_7_0_bm_23_.INIT = 16'hAA0C; + LUT4 com_cmm_u_cmm_cfgspace_low_addr_02_7_0_bm_23_ ( + .I0(com_cmm_u_cmm_cfgspace_N_4729), + .I1(com_cmm_bar2_reg[23]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex_2[1]), + .I3(com_cmm_u_cmm_cfgspace_sel_encodex_2[2]), + .O(com_cmm_u_cmm_cfgspace_low_addr_02_7_0_bm_23__5631) + ); + MUXF5 com_cmm_u_cmm_cfgspace_low_addr_02_7_0_23_ ( + .I0(com_cmm_u_cmm_cfgspace_low_addr_02_7_0_am_23__5632), + .I1(com_cmm_u_cmm_cfgspace_low_addr_02_7_0_bm_23__5631), + .O(com_cmm_u_cmm_cfgspace_low_addr_02[23]), + .S(com_cmm_u_cmm_cfgspace_sel_encodex[0]) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_02_7_0_am_24_.INIT = 16'h00CA; + LUT4 com_cmm_u_cmm_cfgspace_low_addr_02_7_0_am_24_ ( + .I0(cfg_cfg_6102[56]), + .I1(cfg_cfg_6102[280]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex_2[1]), + .I3(com_cmm_u_cmm_cfgspace_sel_encodex_2[2]), + .O(com_cmm_u_cmm_cfgspace_low_addr_02_7_0_am_24__5634) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_02_7_0_bm_24_.INIT = 16'hAA0C; + LUT4 com_cmm_u_cmm_cfgspace_low_addr_02_7_0_bm_24_ ( + .I0(com_cmm_u_cmm_cfgspace_N_4730), + .I1(com_cmm_bar2_reg[24]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex_2[1]), + .I3(com_cmm_u_cmm_cfgspace_sel_encodex_2[2]), + .O(com_cmm_u_cmm_cfgspace_low_addr_02_7_0_bm_24__5633) + ); + MUXF5 com_cmm_u_cmm_cfgspace_low_addr_02_7_0_24_ ( + .I0(com_cmm_u_cmm_cfgspace_low_addr_02_7_0_am_24__5634), + .I1(com_cmm_u_cmm_cfgspace_low_addr_02_7_0_bm_24__5633), + .O(com_cmm_u_cmm_cfgspace_low_addr_02[24]), + .S(com_cmm_u_cmm_cfgspace_sel_encodex[0]) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_02_7_0_am_25_.INIT = 16'h00CA; + LUT4 com_cmm_u_cmm_cfgspace_low_addr_02_7_0_am_25_ ( + .I0(cfg_cfg_6102[57]), + .I1(cfg_cfg_6102[281]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex_2[1]), + .I3(com_cmm_u_cmm_cfgspace_sel_encodex_2[2]), + .O(com_cmm_u_cmm_cfgspace_low_addr_02_7_0_am_25__5636) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_02_7_0_bm_25_.INIT = 16'hAA0C; + LUT4 com_cmm_u_cmm_cfgspace_low_addr_02_7_0_bm_25_ ( + .I0(com_cmm_u_cmm_cfgspace_N_4731), + .I1(com_cmm_bar2_reg[25]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex_2[1]), + .I3(com_cmm_u_cmm_cfgspace_sel_encodex_2[2]), + .O(com_cmm_u_cmm_cfgspace_low_addr_02_7_0_bm_25__5635) + ); + MUXF5 com_cmm_u_cmm_cfgspace_low_addr_02_7_0_25_ ( + .I0(com_cmm_u_cmm_cfgspace_low_addr_02_7_0_am_25__5636), + .I1(com_cmm_u_cmm_cfgspace_low_addr_02_7_0_bm_25__5635), + .O(com_cmm_u_cmm_cfgspace_low_addr_02[25]), + .S(com_cmm_u_cmm_cfgspace_sel_encodex[0]) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_02_7_0_am_26_.INIT = 16'h00CA; + LUT4 com_cmm_u_cmm_cfgspace_low_addr_02_7_0_am_26_ ( + .I0(cfg_cfg_6102[58]), + .I1(cfg_cfg_6102[282]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex_2[1]), + .I3(com_cmm_u_cmm_cfgspace_sel_encodex_2[2]), + .O(com_cmm_u_cmm_cfgspace_low_addr_02_7_0_am_26__5638) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_02_7_0_bm_26_.INIT = 16'hAA0C; + LUT4 com_cmm_u_cmm_cfgspace_low_addr_02_7_0_bm_26_ ( + .I0(com_cmm_u_cmm_cfgspace_N_4732), + .I1(com_cmm_bar2_reg[26]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex_2[1]), + .I3(com_cmm_u_cmm_cfgspace_sel_encodex_2[2]), + .O(com_cmm_u_cmm_cfgspace_low_addr_02_7_0_bm_26__5637) + ); + MUXF5 com_cmm_u_cmm_cfgspace_low_addr_02_7_0_26_ ( + .I0(com_cmm_u_cmm_cfgspace_low_addr_02_7_0_am_26__5638), + .I1(com_cmm_u_cmm_cfgspace_low_addr_02_7_0_bm_26__5637), + .O(com_cmm_u_cmm_cfgspace_low_addr_02[26]), + .S(com_cmm_u_cmm_cfgspace_sel_encodex[0]) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_02_7_0_am_27_.INIT = 16'h00CA; + LUT4 com_cmm_u_cmm_cfgspace_low_addr_02_7_0_am_27_ ( + .I0(cfg_cfg_6102[59]), + .I1(cfg_cfg_6102[283]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex_2[1]), + .I3(com_cmm_u_cmm_cfgspace_sel_encodex_2[2]), + .O(com_cmm_u_cmm_cfgspace_low_addr_02_7_0_am_27__5640) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_02_7_0_bm_27_.INIT = 16'hAA0C; + LUT4 com_cmm_u_cmm_cfgspace_low_addr_02_7_0_bm_27_ ( + .I0(com_cmm_u_cmm_cfgspace_N_4733), + .I1(com_cmm_bar2_reg[27]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex_2[1]), + .I3(com_cmm_u_cmm_cfgspace_sel_encodex_2[2]), + .O(com_cmm_u_cmm_cfgspace_low_addr_02_7_0_bm_27__5639) + ); + MUXF5 com_cmm_u_cmm_cfgspace_low_addr_02_7_0_27_ ( + .I0(com_cmm_u_cmm_cfgspace_low_addr_02_7_0_am_27__5640), + .I1(com_cmm_u_cmm_cfgspace_low_addr_02_7_0_bm_27__5639), + .O(com_cmm_u_cmm_cfgspace_low_addr_02[27]), + .S(com_cmm_u_cmm_cfgspace_sel_encodex[0]) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_02_7_0_am_28_.INIT = 16'hC0AA; + LUT4 com_cmm_u_cmm_cfgspace_low_addr_02_7_0_am_28_ ( + .I0(com_cmm_u_cmm_cfgspace_N_4606), + .I1(NlwRenamedSig_OI_cfg_lstatus_12_), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex_2[1]), + .I3(com_cmm_u_cmm_cfgspace_sel_encodex_2[2]), + .O(com_cmm_u_cmm_cfgspace_low_addr_02_7_0_am_28__5642) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_02_7_0_bm_28_.INIT = 16'hAA0C; + LUT4 com_cmm_u_cmm_cfgspace_low_addr_02_7_0_bm_28_ ( + .I0(com_cmm_u_cmm_cfgspace_N_4734), + .I1(com_cmm_bar2_reg[28]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex_2[1]), + .I3(com_cmm_u_cmm_cfgspace_sel_encodex_2[2]), + .O(com_cmm_u_cmm_cfgspace_low_addr_02_7_0_bm_28__5641) + ); + MUXF5 com_cmm_u_cmm_cfgspace_low_addr_02_7_0_28_ ( + .I0(com_cmm_u_cmm_cfgspace_low_addr_02_7_0_am_28__5642), + .I1(com_cmm_u_cmm_cfgspace_low_addr_02_7_0_bm_28__5641), + .O(com_cmm_u_cmm_cfgspace_low_addr_02[28]), + .S(com_cmm_u_cmm_cfgspace_sel_encodex[0]) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_02_7_0_am_29_.INIT = 16'h00CA; + LUT4 com_cmm_u_cmm_cfgspace_low_addr_02_7_0_am_29_ ( + .I0(cfg_cfg_6102[61]), + .I1(cfg_cfg_6102[285]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex_2[1]), + .I3(com_cmm_u_cmm_cfgspace_sel_encodex_2[2]), + .O(com_cmm_u_cmm_cfgspace_low_addr_02_7_0_am_29__5644) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_02_7_0_bm_29_.INIT = 16'hAA0C; + LUT4 com_cmm_u_cmm_cfgspace_low_addr_02_7_0_bm_29_ ( + .I0(com_cmm_u_cmm_cfgspace_N_4735), + .I1(com_cmm_bar2_reg[29]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex_2[1]), + .I3(com_cmm_u_cmm_cfgspace_sel_encodex_2[2]), + .O(com_cmm_u_cmm_cfgspace_low_addr_02_7_0_bm_29__5643) + ); + MUXF5 com_cmm_u_cmm_cfgspace_low_addr_02_7_0_29_ ( + .I0(com_cmm_u_cmm_cfgspace_low_addr_02_7_0_am_29__5644), + .I1(com_cmm_u_cmm_cfgspace_low_addr_02_7_0_bm_29__5643), + .O(com_cmm_u_cmm_cfgspace_low_addr_02[29]), + .S(com_cmm_u_cmm_cfgspace_sel_encodex[0]) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_02_7_0_am_30_.INIT = 16'h00CA; + LUT4 com_cmm_u_cmm_cfgspace_low_addr_02_7_0_am_30_ ( + .I0(cfg_cfg_6102[62]), + .I1(cfg_cfg_6102[286]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex_2[1]), + .I3(com_cmm_u_cmm_cfgspace_sel_encodex_2[2]), + .O(com_cmm_u_cmm_cfgspace_low_addr_02_7_0_am_30__5646) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_02_7_0_bm_30_.INIT = 16'hAA0C; + LUT4 com_cmm_u_cmm_cfgspace_low_addr_02_7_0_bm_30_ ( + .I0(com_cmm_u_cmm_cfgspace_N_4736), + .I1(com_cmm_bar2_reg[30]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex_2[1]), + .I3(com_cmm_u_cmm_cfgspace_sel_encodex_2[2]), + .O(com_cmm_u_cmm_cfgspace_low_addr_02_7_0_bm_30__5645) + ); + MUXF5 com_cmm_u_cmm_cfgspace_low_addr_02_7_0_30_ ( + .I0(com_cmm_u_cmm_cfgspace_low_addr_02_7_0_am_30__5646), + .I1(com_cmm_u_cmm_cfgspace_low_addr_02_7_0_bm_30__5645), + .O(com_cmm_u_cmm_cfgspace_low_addr_02[30]), + .S(com_cmm_u_cmm_cfgspace_sel_encodex[0]) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_02_7_0_am_31_.INIT = 16'h00CA; + LUT4 com_cmm_u_cmm_cfgspace_low_addr_02_7_0_am_31_ ( + .I0(cfg_cfg_6102[63]), + .I1(cfg_cfg_6102[287]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex_2[1]), + .I3(com_cmm_u_cmm_cfgspace_sel_encodex_2[2]), + .O(com_cmm_u_cmm_cfgspace_low_addr_02_7_0_am_31__5648) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_02_7_0_bm_31_.INIT = 16'hAA0C; + LUT4 com_cmm_u_cmm_cfgspace_low_addr_02_7_0_bm_31_ ( + .I0(com_cmm_u_cmm_cfgspace_N_4737), + .I1(com_cmm_bar2_reg[31]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex_2[1]), + .I3(com_cmm_u_cmm_cfgspace_sel_encodex_2[2]), + .O(com_cmm_u_cmm_cfgspace_low_addr_02_7_0_bm_31__5647) + ); + MUXF5 com_cmm_u_cmm_cfgspace_low_addr_02_7_0_31_ ( + .I0(com_cmm_u_cmm_cfgspace_low_addr_02_7_0_am_31__5648), + .I1(com_cmm_u_cmm_cfgspace_low_addr_02_7_0_bm_31__5647), + .O(com_cmm_u_cmm_cfgspace_low_addr_02[31]), + .S(com_cmm_u_cmm_cfgspace_sel_encodex[0]) + ); + MUXF6 com_cmm_u_cmm_cfgspace_pme_data_6_i_m2_i_m4_i_m3_0_0_ ( + .I0(com_cmm_u_cmm_cfgspace_N_63586), + .I1(com_cmm_u_cmm_cfgspace_N_63556), + .O(com_cmm_u_cmm_cfgspace_N_63596), + .S(com_cmm_u_cmm_cfgspace_pme_pmcsr[10]) + ); + MUXF6 com_cmm_u_cmm_cfgspace_pme_data_6_i_m2_i_m4_i_m3_0_3_ ( + .I0(com_cmm_u_cmm_cfgspace_N_63589), + .I1(com_cmm_u_cmm_cfgspace_N_63559), + .O(com_cmm_u_cmm_cfgspace_N_63599), + .S(com_cmm_u_cmm_cfgspace_pme_pmcsr[10]) + ); + MUXF6 com_cmm_u_cmm_cfgspace_pme_data_6_i_m2_i_m4_i_m3_0_4_ ( + .I0(com_cmm_u_cmm_cfgspace_N_63590), + .I1(com_cmm_u_cmm_cfgspace_N_63560), + .O(com_cmm_u_cmm_cfgspace_N_63600), + .S(com_cmm_u_cmm_cfgspace_pme_pmcsr[10]) + ); + MUXF6 com_cmm_u_cmm_cfgspace_pme_data_6_i_m2_i_m4_i_m3_0_5_ ( + .I0(com_cmm_u_cmm_cfgspace_N_63591), + .I1(com_cmm_u_cmm_cfgspace_N_63561), + .O(com_cmm_u_cmm_cfgspace_N_63601), + .S(com_cmm_u_cmm_cfgspace_pme_pmcsr[10]) + ); + MUXF6 com_cmm_u_cmm_cfgspace_pme_data_6_i_m2_i_m4_i_m3_0_6_ ( + .I0(com_cmm_u_cmm_cfgspace_N_63592), + .I1(com_cmm_u_cmm_cfgspace_N_63562), + .O(com_cmm_u_cmm_cfgspace_N_63602), + .S(com_cmm_u_cmm_cfgspace_pme_pmcsr[10]) + ); + MUXF6 com_cmm_u_cmm_cfgspace_pme_data_6_i_m2_i_m4_i_m3_0_7_ ( + .I0(com_cmm_u_cmm_cfgspace_N_63593), + .I1(com_cmm_u_cmm_cfgspace_N_63563), + .O(com_cmm_u_cmm_cfgspace_N_63603), + .S(com_cmm_u_cmm_cfgspace_pme_pmcsr[10]) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_02_7_0_am_7_.INIT = 16'hC0AA; + LUT4 com_cmm_u_cmm_cfgspace_low_addr_02_7_0_am_7_ ( + .I0(com_cmm_u_cmm_cfgspace_N_4585), + .I1(NlwRenamedSig_OI_cfg_lcommand_7_), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex_2[1]), + .I3(com_cmm_u_cmm_cfgspace_sel_encodex_2[2]), + .O(com_cmm_u_cmm_cfgspace_low_addr_02_7_0_am_7__5650) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_02_7_0_bm_7_.INIT = 16'hAA0C; + LUT4 com_cmm_u_cmm_cfgspace_low_addr_02_7_0_bm_7_ ( + .I0(com_cmm_u_cmm_cfgspace_N_4713), + .I1(com_cmm_bar2_reg[7]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex_2[1]), + .I3(com_cmm_u_cmm_cfgspace_sel_encodex_2[2]), + .O(com_cmm_u_cmm_cfgspace_low_addr_02_7_0_bm_7__5649) + ); + MUXF5 com_cmm_u_cmm_cfgspace_low_addr_02_7_0_7_ ( + .I0(com_cmm_u_cmm_cfgspace_low_addr_02_7_0_am_7__5650), + .I1(com_cmm_u_cmm_cfgspace_low_addr_02_7_0_bm_7__5649), + .O(com_cmm_u_cmm_cfgspace_low_addr_02[7]), + .S(com_cmm_u_cmm_cfgspace_sel_encodex[0]) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_02_7_0_am_6_.INIT = 16'hC0AA; + LUT4 com_cmm_u_cmm_cfgspace_low_addr_02_7_0_am_6_ ( + .I0(com_cmm_u_cmm_cfgspace_N_4584), + .I1(NlwRenamedSig_OI_cfg_lcommand_6_), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex_2[1]), + .I3(com_cmm_u_cmm_cfgspace_sel_encodex_2[2]), + .O(com_cmm_u_cmm_cfgspace_low_addr_02_7_0_am_6__5652) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_02_7_0_bm_6_.INIT = 16'hAA0C; + LUT4 com_cmm_u_cmm_cfgspace_low_addr_02_7_0_bm_6_ ( + .I0(com_cmm_u_cmm_cfgspace_N_4712), + .I1(com_cmm_bar2_reg[6]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex_2[1]), + .I3(com_cmm_u_cmm_cfgspace_sel_encodex_2[2]), + .O(com_cmm_u_cmm_cfgspace_low_addr_02_7_0_bm_6__5651) + ); + MUXF5 com_cmm_u_cmm_cfgspace_low_addr_02_7_0_6_ ( + .I0(com_cmm_u_cmm_cfgspace_low_addr_02_7_0_am_6__5652), + .I1(com_cmm_u_cmm_cfgspace_low_addr_02_7_0_bm_6__5651), + .O(com_cmm_u_cmm_cfgspace_low_addr_02[6]), + .S(com_cmm_u_cmm_cfgspace_sel_encodex[0]) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_01_7_0_am_14_.INIT = 16'hAAC0; + LUT4 com_cmm_u_cmm_cfgspace_low_addr_01_7_0_am_14_ ( + .I0(com_cmm_u_cmm_cfgspace_N_3776), + .I1(com_cmm_bar5_reg[14]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex_2[1]), + .I3(com_cmm_u_cmm_cfgspace_sel_encodex_2[2]), + .O(com_cmm_u_cmm_cfgspace_low_addr_01_7_0_am_14__5654) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_01_7_0_bm_14_.INIT = 16'hAA0C; + LUT4 com_cmm_u_cmm_cfgspace_low_addr_01_7_0_bm_14_ ( + .I0(com_cmm_u_cmm_cfgspace_N_3872), + .I1(com_cmm_bar1_reg[14]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex_2[1]), + .I3(com_cmm_u_cmm_cfgspace_sel_encodex_2[2]), + .O(com_cmm_u_cmm_cfgspace_low_addr_01_7_0_bm_14__5653) + ); + MUXF5 com_cmm_u_cmm_cfgspace_low_addr_01_7_0_14_ ( + .I0(com_cmm_u_cmm_cfgspace_low_addr_01_7_0_am_14__5654), + .I1(com_cmm_u_cmm_cfgspace_low_addr_01_7_0_bm_14__5653), + .O(com_cmm_u_cmm_cfgspace_low_addr_01[14]), + .S(com_cmm_u_cmm_cfgspace_sel_encodex[0]) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_01_7_0_am_12_.INIT = 16'hAAC0; + LUT4 com_cmm_u_cmm_cfgspace_low_addr_01_7_0_am_12_ ( + .I0(com_cmm_u_cmm_cfgspace_N_3774), + .I1(com_cmm_bar5_reg[12]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex_2[1]), + .I3(com_cmm_u_cmm_cfgspace_sel_encodex_2[2]), + .O(com_cmm_u_cmm_cfgspace_low_addr_01_7_0_am_12__5656) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_01_7_0_bm_12_.INIT = 16'hAA0C; + LUT4 com_cmm_u_cmm_cfgspace_low_addr_01_7_0_bm_12_ ( + .I0(com_cmm_u_cmm_cfgspace_N_3870), + .I1(com_cmm_bar1_reg[12]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex_2[1]), + .I3(com_cmm_u_cmm_cfgspace_sel_encodex_2[2]), + .O(com_cmm_u_cmm_cfgspace_low_addr_01_7_0_bm_12__5655) + ); + MUXF5 com_cmm_u_cmm_cfgspace_low_addr_01_7_0_12_ ( + .I0(com_cmm_u_cmm_cfgspace_low_addr_01_7_0_am_12__5656), + .I1(com_cmm_u_cmm_cfgspace_low_addr_01_7_0_bm_12__5655), + .O(com_cmm_u_cmm_cfgspace_low_addr_01[12]), + .S(com_cmm_u_cmm_cfgspace_sel_encodex[0]) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_01_7_0_am_6_.INIT = 16'hCA0A; + LUT4 com_cmm_u_cmm_cfgspace_low_addr_01_7_0_am_6_ ( + .I0(com_cmm_u_cmm_cfgspace_N_3736), + .I1(com_cmm_u_cmm_cfgspace_sel_encodex_2[1]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex_2[2]), + .I3(com_cmm_u_cmm_cfgspace_x_lcap[0]), + .O(com_cmm_u_cmm_cfgspace_low_addr_01_7_0_am_6__5658) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_01_7_0_bm_6_.INIT = 16'hAAFC; + LUT4 com_cmm_u_cmm_cfgspace_low_addr_01_7_0_bm_6_ ( + .I0(com_cmm_u_cmm_cfgspace_N_3864), + .I1(com_cmm_bar1_reg[6]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex_2[1]), + .I3(com_cmm_u_cmm_cfgspace_sel_encodex_2[2]), + .O(com_cmm_u_cmm_cfgspace_low_addr_01_7_0_bm_6__5657) + ); + MUXF5 com_cmm_u_cmm_cfgspace_low_addr_01_7_0_6_ ( + .I0(com_cmm_u_cmm_cfgspace_low_addr_01_7_0_am_6__5658), + .I1(com_cmm_u_cmm_cfgspace_low_addr_01_7_0_bm_6__5657), + .O(com_cmm_u_cmm_cfgspace_low_addr_01[6]), + .S(com_cmm_u_cmm_cfgspace_sel_encodex[0]) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_02_7_0_am_8_.INIT = 16'hC0AA; + LUT4 com_cmm_u_cmm_cfgspace_low_addr_02_7_0_am_8_ ( + .I0(com_cmm_u_cmm_cfgspace_N_4586), + .I1(com_cmm_u_cmm_cfgspace_N_59052_1), + .I2(cfg_cfg_6102[483]), + .I3(com_cmm_u_cmm_cfgspace_sel_encodex_2[2]), + .O(com_cmm_u_cmm_cfgspace_low_addr_02_7_0_am_8__5660) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_02_7_0_bm_8_.INIT = 16'hA00C; + LUT4 com_cmm_u_cmm_cfgspace_low_addr_02_7_0_bm_8_ ( + .I0(cfg_cfg_6102[696]), + .I1(com_cmm_bar2_reg[8]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex_2[1]), + .I3(com_cmm_u_cmm_cfgspace_sel_encodex_2[2]), + .O(com_cmm_u_cmm_cfgspace_low_addr_02_7_0_bm_8__5659) + ); + MUXF5 com_cmm_u_cmm_cfgspace_low_addr_02_7_0_8_ ( + .I0(com_cmm_u_cmm_cfgspace_low_addr_02_7_0_am_8__5660), + .I1(com_cmm_u_cmm_cfgspace_low_addr_02_7_0_bm_8__5659), + .O(com_cmm_u_cmm_cfgspace_low_addr_02[8]), + .S(com_cmm_u_cmm_cfgspace_sel_encodex[0]) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_02_7_0_am_9_.INIT = 16'hC0AA; + LUT4 com_cmm_u_cmm_cfgspace_low_addr_02_7_0_am_9_ ( + .I0(com_cmm_u_cmm_cfgspace_N_4587), + .I1(com_cmm_u_cmm_cfgspace_N_59052_1), + .I2(cfg_cfg_6102[484]), + .I3(com_cmm_u_cmm_cfgspace_sel_encodex_2[2]), + .O(com_cmm_u_cmm_cfgspace_low_addr_02_7_0_am_9__5662) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_02_7_0_bm_9_.INIT = 16'hA00C; + LUT4 com_cmm_u_cmm_cfgspace_low_addr_02_7_0_bm_9_ ( + .I0(cfg_cfg_6102[697]), + .I1(com_cmm_bar2_reg[9]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex_2[1]), + .I3(com_cmm_u_cmm_cfgspace_sel_encodex_2[2]), + .O(com_cmm_u_cmm_cfgspace_low_addr_02_7_0_bm_9__5661) + ); + MUXF5 com_cmm_u_cmm_cfgspace_low_addr_02_7_0_9_ ( + .I0(com_cmm_u_cmm_cfgspace_low_addr_02_7_0_am_9__5662), + .I1(com_cmm_u_cmm_cfgspace_low_addr_02_7_0_bm_9__5661), + .O(com_cmm_u_cmm_cfgspace_low_addr_02[9]), + .S(com_cmm_u_cmm_cfgspace_sel_encodex[0]) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_02_7_0_am_10_.INIT = 16'hC0AA; + LUT4 com_cmm_u_cmm_cfgspace_low_addr_02_7_0_am_10_ ( + .I0(com_cmm_u_cmm_cfgspace_N_4588), + .I1(com_cmm_u_cmm_cfgspace_N_59052_1), + .I2(cfg_cfg_6102[485]), + .I3(com_cmm_u_cmm_cfgspace_sel_encodex_2[2]), + .O(com_cmm_u_cmm_cfgspace_low_addr_02_7_0_am_10__5664) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_02_7_0_bm_10_.INIT = 16'hA00C; + LUT4 com_cmm_u_cmm_cfgspace_low_addr_02_7_0_bm_10_ ( + .I0(cfg_cfg_6102[698]), + .I1(com_cmm_bar2_reg[10]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex_2[1]), + .I3(com_cmm_u_cmm_cfgspace_sel_encodex_2[2]), + .O(com_cmm_u_cmm_cfgspace_low_addr_02_7_0_bm_10__5663) + ); + MUXF5 com_cmm_u_cmm_cfgspace_low_addr_02_7_0_10_ ( + .I0(com_cmm_u_cmm_cfgspace_low_addr_02_7_0_am_10__5664), + .I1(com_cmm_u_cmm_cfgspace_low_addr_02_7_0_bm_10__5663), + .O(com_cmm_u_cmm_cfgspace_low_addr_02[10]), + .S(com_cmm_u_cmm_cfgspace_sel_encodex[0]) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_02_7_0_am_13_.INIT = 16'hC0AA; + LUT4 com_cmm_u_cmm_cfgspace_low_addr_02_7_0_am_13_ ( + .I0(com_cmm_u_cmm_cfgspace_N_4591), + .I1(com_cmm_u_cmm_cfgspace_N_59052_1), + .I2(cfg_cfg_6102[488]), + .I3(com_cmm_u_cmm_cfgspace_sel_encodex_2[2]), + .O(com_cmm_u_cmm_cfgspace_low_addr_02_7_0_am_13__5666) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_02_7_0_bm_13_.INIT = 16'hA00C; + LUT4 com_cmm_u_cmm_cfgspace_low_addr_02_7_0_bm_13_ ( + .I0(cfg_cfg_6102[701]), + .I1(com_cmm_bar2_reg[13]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex_2[1]), + .I3(com_cmm_u_cmm_cfgspace_sel_encodex_2[2]), + .O(com_cmm_u_cmm_cfgspace_low_addr_02_7_0_bm_13__5665) + ); + MUXF5 com_cmm_u_cmm_cfgspace_low_addr_02_7_0_13_ ( + .I0(com_cmm_u_cmm_cfgspace_low_addr_02_7_0_am_13__5666), + .I1(com_cmm_u_cmm_cfgspace_low_addr_02_7_0_bm_13__5665), + .O(com_cmm_u_cmm_cfgspace_low_addr_02[13]), + .S(com_cmm_u_cmm_cfgspace_sel_encodex[0]) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_02_7_0_am_15_.INIT = 16'hC0AA; + LUT4 com_cmm_u_cmm_cfgspace_low_addr_02_7_0_am_15_ ( + .I0(com_cmm_u_cmm_cfgspace_N_4593), + .I1(com_cmm_u_cmm_cfgspace_N_59052_1), + .I2(cfg_cfg_6102[490]), + .I3(com_cmm_u_cmm_cfgspace_sel_encodex_2[2]), + .O(com_cmm_u_cmm_cfgspace_low_addr_02_7_0_am_15__5668) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_02_7_0_bm_15_.INIT = 16'hAA0C; + LUT4 com_cmm_u_cmm_cfgspace_low_addr_02_7_0_bm_15_ ( + .I0(com_cmm_u_cmm_cfgspace_N_4721), + .I1(com_cmm_bar2_reg[15]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex_2[1]), + .I3(com_cmm_u_cmm_cfgspace_sel_encodex_2[2]), + .O(com_cmm_u_cmm_cfgspace_low_addr_02_7_0_bm_15__5667) + ); + MUXF5 com_cmm_u_cmm_cfgspace_low_addr_02_7_0_15_ ( + .I0(com_cmm_u_cmm_cfgspace_low_addr_02_7_0_am_15__5668), + .I1(com_cmm_u_cmm_cfgspace_low_addr_02_7_0_bm_15__5667), + .O(com_cmm_u_cmm_cfgspace_low_addr_02[15]), + .S(com_cmm_u_cmm_cfgspace_sel_encodex[0]) + ); + defparam com_cmm_u_cmm_cfgspace_sel_encodex_en_3_i_0_0_0_a2_0.INIT = 16'h2AAA; + LUT4_L com_cmm_u_cmm_cfgspace_sel_encodex_en_3_i_0_0_0_a2_0 ( + .I0(com_cmm_u_cmm_cfgspace_N_57266_1), + .I1(cfg_dwaddr_6099[2]), + .I2(cfg_dwaddr_6099[3]), + .I3(cfg_dwaddr_6099[4]), + .LO(com_cmm_u_cmm_cfgspace_N_58588) + ); + defparam com_cmm_u_cmm_cfgspace_x3gio_decodepipe_h_sel_6x_3_0_0_0_0_a2.INIT = 16'h2000; + LUT4_L com_cmm_u_cmm_cfgspace_x3gio_decodepipe_h_sel_6x_3_0_0_0_0_a2 ( + .I0(com_cmm_u_cmm_cfgspace_N_57266_1), + .I1(cfg_dwaddr_6099[2]), + .I2(cfg_dwaddr_6099[3]), + .I3(cfg_dwaddr_6099[4]), + .LO(com_cmm_u_cmm_cfgspace_N_57266) + ); + defparam com_cmm_u_cmm_cfgspace_x3gio_decodepipe_h_sel_4x_3_0_0_0_0_a2_1.INIT = 8'h20; + LUT3 com_cmm_u_cmm_cfgspace_x3gio_decodepipe_h_sel_4x_3_0_0_0_0_a2_1 ( + .I0(com_cmm_u_cmm_cfgspace_N_57266_1), + .I1(cfg_dwaddr_6099[3]), + .I2(cfg_dwaddr_6099[4]), + .O(com_cmm_u_cmm_cfgspace_N_57264_2) + ); + defparam com_cmm_u_cmm_cfgspace_x3gio_decodepipe_h_sel_2x_3_0_0_0_0_a2_1.INIT = 8'h08; + LUT3 com_cmm_u_cmm_cfgspace_x3gio_decodepipe_h_sel_2x_3_0_0_0_0_a2_1 ( + .I0(com_cmm_u_cmm_cfgspace_N_57266_1), + .I1(cfg_dwaddr_6099[3]), + .I2(cfg_dwaddr_6099[4]), + .O(com_cmm_u_cmm_cfgspace_N_57260_2) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_00_i_0_15_39329.INIT = 16'h08AA; + LUT4_L com_cmm_u_cmm_cfgspace_low_addr_00_i_0_15_39329 ( + .I0(com_cmm_u_cmm_cfgspace_low_addr_00_i_0_15_39327_5669), + .I1(com_cmm_msi_haddr[15]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex_2[1]), + .I3(com_cmm_u_cmm_cfgspace_sel_encodex_2[2]), + .LO(com_cmm_u_cmm_cfgspace_low_addr_00_i_0_15_39329_5706) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_00_i_i_0_0_3_29_.INIT = 16'h1500; + LUT4 com_cmm_u_cmm_cfgspace_low_addr_00_i_i_0_0_3_29_ ( + .I0(com_cmm_u_cmm_cfgspace_N_59358), + .I1(com_cmm_u_cmm_cfgspace_N_61356), + .I2(com_cmm_msi_haddr[29]), + .I3(com_cmm_u_cmm_cfgspace_low_addr_00_i_i_0_0_1[29]), + .O(com_cmm_u_cmm_cfgspace_low_addr_00_i_i_0_0_3[29]) + ); + defparam com_cmm_u_cmm_cfgspace_sel_encodex_en_3_i_0_0_0_0.INIT = 16'hF755; + LUT4 com_cmm_u_cmm_cfgspace_sel_encodex_en_3_i_0_0_0_0 ( + .I0(com_cmm_u_cmm_cfgspace_N_55879_i), + .I1(com_cmm_u_cmm_cfgspace_N_61379), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex_en_3_i_0_0_0_o3_0_5759), + .I3(com_cmm_state_0[1]), + .O(com_cmm_u_cmm_cfgspace_sel_encodex_en_3_i_0_0_0_0_5747) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_01_2_0_a2_0_a2_0_a2_26_.INIT = 16'h88A0; + LUT4_L com_cmm_u_cmm_cfgspace_low_addr_01_2_0_a2_0_a2_0_a2_26_ ( + .I0(com_cmm_u_cmm_cfgspace_N_61397), + .I1(com_cmm_u_cmm_cfgspace_N_63558), + .I2(com_cmm_u_cmm_cfgspace_N_63588), + .I3(com_cmm_u_cmm_cfgspace_pme_pmcsr[10]), + .LO(com_cmm_u_cmm_cfgspace_N_59876) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_01_2_0_a2_0_a2_0_a2_25_.INIT = 16'h88A0; + LUT4_L com_cmm_u_cmm_cfgspace_low_addr_01_2_0_a2_0_a2_0_a2_25_ ( + .I0(com_cmm_u_cmm_cfgspace_N_61397), + .I1(com_cmm_u_cmm_cfgspace_N_63557), + .I2(com_cmm_u_cmm_cfgspace_N_63587), + .I3(com_cmm_u_cmm_cfgspace_pme_pmcsr[10]), + .LO(com_cmm_u_cmm_cfgspace_N_59875) + ); + defparam com_cmm_u_cmm_cfgspace_x_dcmd_18_1_i_0_m3_0_8_.INIT = 8'hE4; + LUT3_L com_cmm_u_cmm_cfgspace_x_dcmd_18_1_i_0_m3_0_8_ ( + .I0(com_cmm_u_cmm_cfgspace_N_55990_i), + .I1(NlwRenamedSig_OI_cfg_dcommand[8]), + .I2(com_cmm_cfg_wr_data_16_), + .LO(com_cmm_u_cmm_cfgspace_N_57085) + ); + defparam com_cmm_u_cmm_cfgspace_N_86244_i.INIT = 16'hE444; + LUT4 com_cmm_u_cmm_cfgspace_N_86244_i ( + .I0(com_cmm_u_cmm_cfgspace_N_55879_i), + .I1(cfg_dwaddr_6099[6]), + .I2(com_cmm_cfg_addr[6]), + .I3(com_cmm_state_0[1]), + .O(com_cmm_u_cmm_cfgspace_N_86244_i_5757) + ); + defparam com_cmm_u_cmm_cfgspace_x3gio_decodepipe_h_sel_1x_3_0_0_0_0_a2_0.INIT = 8'h80; + LUT3_L com_cmm_u_cmm_cfgspace_x3gio_decodepipe_h_sel_1x_3_0_0_0_0_a2_0 ( + .I0(com_cmm_u_cmm_cfgspace_N_57206), + .I1(com_cmm_u_cmm_cfgspace_N_61290_2), + .I2(com_cmm_u_cmm_cfgspace_N_61379), + .LO(com_cmm_u_cmm_cfgspace_N_57257) + ); + defparam com_cmm_u_cmm_cfgspace_x3gio_decodepipe_h_sel_2x_3_0_0_0_0_a2_0.INIT = 16'h0800; + LUT4 com_cmm_u_cmm_cfgspace_x3gio_decodepipe_h_sel_2x_3_0_0_0_0_a2_0 ( + .I0(com_cmm_u_cmm_cfgspace_N_57261_1), + .I1(com_cmm_u_cmm_cfgspace_N_61378), + .I2(com_cmm_cfg_addr[2]), + .I3(com_cmm_cfg_addr[3]), + .O(com_cmm_u_cmm_cfgspace_N_57259) + ); + defparam com_cmm_u_cmm_cfgspace_x3gio_decodepipe_h_sel_5x_3_0_0_0_0_a2_0.INIT = 16'h0800; + LUT4 com_cmm_u_cmm_cfgspace_x3gio_decodepipe_h_sel_5x_3_0_0_0_0_a2_0 ( + .I0(com_cmm_u_cmm_cfgspace_N_57206), + .I1(com_cmm_u_cmm_cfgspace_N_61379), + .I2(com_cmm_cfg_addr[3]), + .I3(com_cmm_cfg_addr[4]), + .O(com_cmm_u_cmm_cfgspace_N_57265) + ); + defparam com_cmm_u_cmm_cfgspace_x3gio_decodepipe_h_sel_4x_3_0_0_0_0_a2_0.INIT = 16'h0800; + LUT4 com_cmm_u_cmm_cfgspace_x3gio_decodepipe_h_sel_4x_3_0_0_0_0_a2_0 ( + .I0(com_cmm_u_cmm_cfgspace_N_61290_1), + .I1(com_cmm_u_cmm_cfgspace_N_61378), + .I2(com_cmm_cfg_addr[3]), + .I3(com_cmm_cfg_addr[4]), + .O(com_cmm_u_cmm_cfgspace_N_57263) + ); + defparam com_cmm_u_cmm_cfgspace_x3gio_decodepipe_h_sel_3x_3_0_0_0_0_a2_0.INIT = 8'h80; + LUT3 com_cmm_u_cmm_cfgspace_x3gio_decodepipe_h_sel_3x_3_0_0_0_0_a2_0 ( + .I0(com_cmm_u_cmm_cfgspace_N_57206), + .I1(com_cmm_u_cmm_cfgspace_N_57261_1), + .I2(com_cmm_cfg_addr[3]), + .O(com_cmm_u_cmm_cfgspace_N_57261) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_00_i_0_0_0_31_39355.INIT = 16'hC040; + LUT4_L com_cmm_u_cmm_cfgspace_low_addr_00_i_0_0_0_31_39355 ( + .I0(com_cmm_u_cmm_cfgspace_N_61330), + .I1(com_cmm_u_cmm_cfgspace_low_addr_00_i_0_0_0_31_39351_5671), + .I2(com_cmm_u_cmm_cfgspace_low_addr_00_i_0_0_0_31_39352_5670), + .I3(com_cmm_bar0_reg_31_), + .LO(com_cmm_u_cmm_cfgspace_low_addr_00_i_0_0_0_31_39355_5694) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_00_i_0_0_0_28_39360.INIT = 16'hC040; + LUT4_L com_cmm_u_cmm_cfgspace_low_addr_00_i_0_0_0_28_39360 ( + .I0(com_cmm_u_cmm_cfgspace_N_61330), + .I1(com_cmm_u_cmm_cfgspace_low_addr_00_i_0_0_0_28_39356_5673), + .I2(com_cmm_u_cmm_cfgspace_low_addr_00_i_0_0_0_28_39357_5672), + .I3(com_cmm_bar0_reg_28_), + .LO(com_cmm_u_cmm_cfgspace_low_addr_00_i_0_0_0_28_39360_5696) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_00_i_0_0_0_27_39365.INIT = 16'hC040; + LUT4_L com_cmm_u_cmm_cfgspace_low_addr_00_i_0_0_0_27_39365 ( + .I0(com_cmm_u_cmm_cfgspace_N_61330), + .I1(com_cmm_u_cmm_cfgspace_low_addr_00_i_0_0_0_27_39361_5675), + .I2(com_cmm_u_cmm_cfgspace_low_addr_00_i_0_0_0_27_39362_5674), + .I3(com_cmm_bar0_reg_27_), + .LO(com_cmm_u_cmm_cfgspace_low_addr_00_i_0_0_0_27_39365_5697) + ); + defparam com_cmm_u_cmm_cfgspace_x3gio_decodepipe_h_sel_0x_3_0_0_0_0_0.INIT = 16'h7F55; + LUT4 com_cmm_u_cmm_cfgspace_x3gio_decodepipe_h_sel_0x_3_0_0_0_0_0 ( + .I0(com_cmm_u_cmm_cfgspace_N_55879_i), + .I1(com_cmm_u_cmm_cfgspace_N_61290_1), + .I2(com_cmm_u_cmm_cfgspace_N_61290_2), + .I3(com_cmm_state_0[1]), + .O(com_cmm_u_cmm_cfgspace_sel_0x_3_0_0_0_0_0) + ); + defparam com_cmm_u_cmm_cfgspace_x3gio_bar4_bar4_reg_8_1_0_0_0_0_3_.INIT = 16'h4FCF; + LUT4_L com_cmm_u_cmm_cfgspace_x3gio_bar4_bar4_reg_8_1_0_0_0_0_3_ ( + .I0(com_cmm_u_cmm_cfgspace_N_55970_i), + .I1(com_cmm_u_cmm_cfgspace_N_56068_i), + .I2(cfg_cfg_6102[195]), + .I3(com_cmm_cfg_wr_data[27]), + .LO(com_cmm_u_cmm_cfgspace_bar4_reg_8_1_0_0_0_0[3]) + ); + defparam com_cmm_u_cmm_cfgspace_x3gio_bar4_bar4_reg_8_1_0_0_0_0_1_.INIT = 16'h4FCF; + LUT4_L com_cmm_u_cmm_cfgspace_x3gio_bar4_bar4_reg_8_1_0_0_0_0_1_ ( + .I0(com_cmm_u_cmm_cfgspace_N_55970_i), + .I1(com_cmm_u_cmm_cfgspace_N_56068_i), + .I2(cfg_cfg_6102[193]), + .I3(com_cmm_cfg_wr_data[25]), + .LO(com_cmm_u_cmm_cfgspace_bar4_reg_8_1_0_0_0_0[1]) + ); + defparam com_cmm_u_cmm_cfgspace_x3gio_bar5_bar5_reg_8_1_0_0_0_0_3_.INIT = 16'h4FCF; + LUT4_L com_cmm_u_cmm_cfgspace_x3gio_bar5_bar5_reg_8_1_0_0_0_0_3_ ( + .I0(com_cmm_u_cmm_cfgspace_N_55971_i), + .I1(com_cmm_u_cmm_cfgspace_N_56067_i), + .I2(cfg_cfg_6102[227]), + .I3(com_cmm_cfg_wr_data[27]), + .LO(com_cmm_u_cmm_cfgspace_bar5_reg_8_1_0_0_0_0[3]) + ); + defparam com_cmm_u_cmm_cfgspace_x3gio_bar4_bar4_reg_8_1_0_0_0_0_2_.INIT = 16'h4FCF; + LUT4_L com_cmm_u_cmm_cfgspace_x3gio_bar4_bar4_reg_8_1_0_0_0_0_2_ ( + .I0(com_cmm_u_cmm_cfgspace_N_55970_i), + .I1(com_cmm_u_cmm_cfgspace_N_56068_i), + .I2(cfg_cfg_6102[194]), + .I3(com_cmm_cfg_wr_data[26]), + .LO(com_cmm_u_cmm_cfgspace_bar4_reg_8_1_0_0_0_0[2]) + ); + defparam com_cmm_u_cmm_cfgspace_x3gio_bar5_bar5_reg_8_1_0_0_0_0_0_.INIT = 16'h4FCF; + LUT4_L com_cmm_u_cmm_cfgspace_x3gio_bar5_bar5_reg_8_1_0_0_0_0_0_ ( + .I0(com_cmm_u_cmm_cfgspace_N_55971_i), + .I1(com_cmm_u_cmm_cfgspace_N_56067_i), + .I2(cfg_cfg_6102[224]), + .I3(com_cmm_cfg_wr_data[24]), + .LO(com_cmm_u_cmm_cfgspace_bar5_reg_8_1_0_0_0_0[0]) + ); + defparam com_cmm_u_cmm_cfgspace_x3gio_bar4_bar4_reg_8_1_0_0_0_0_0_.INIT = 16'h4FCF; + LUT4_L com_cmm_u_cmm_cfgspace_x3gio_bar4_bar4_reg_8_1_0_0_0_0_0_ ( + .I0(com_cmm_u_cmm_cfgspace_N_55970_i), + .I1(com_cmm_u_cmm_cfgspace_N_56068_i), + .I2(cfg_cfg_6102[192]), + .I3(com_cmm_cfg_wr_data[24]), + .LO(com_cmm_u_cmm_cfgspace_bar4_reg_8_1_0_0_0_0[0]) + ); + defparam com_cmm_u_cmm_cfgspace_x3gio_bar5_bar5_reg_8_1_0_0_0_0_1_.INIT = 16'h4FCF; + LUT4_L com_cmm_u_cmm_cfgspace_x3gio_bar5_bar5_reg_8_1_0_0_0_0_1_ ( + .I0(com_cmm_u_cmm_cfgspace_N_55971_i), + .I1(com_cmm_u_cmm_cfgspace_N_56067_i), + .I2(cfg_cfg_6102[225]), + .I3(com_cmm_cfg_wr_data[25]), + .LO(com_cmm_u_cmm_cfgspace_bar5_reg_8_1_0_0_0_0[1]) + ); + defparam com_cmm_u_cmm_cfgspace_x3gio_bar5_bar5_reg_8_1_0_0_0_0_2_.INIT = 16'h4FCF; + LUT4_L com_cmm_u_cmm_cfgspace_x3gio_bar5_bar5_reg_8_1_0_0_0_0_2_ ( + .I0(com_cmm_u_cmm_cfgspace_N_55971_i), + .I1(com_cmm_u_cmm_cfgspace_N_56067_i), + .I2(cfg_cfg_6102[226]), + .I3(com_cmm_cfg_wr_data[26]), + .LO(com_cmm_u_cmm_cfgspace_bar5_reg_8_1_0_0_0_0[2]) + ); + defparam com_cmm_u_cmm_cfgspace_x3gio_bar3_bar3_reg_8_1_0_0_0_0_1_.INIT = 16'h4FCF; + LUT4_L com_cmm_u_cmm_cfgspace_x3gio_bar3_bar3_reg_8_1_0_0_0_0_1_ ( + .I0(com_cmm_u_cmm_cfgspace_N_55974_i), + .I1(com_cmm_u_cmm_cfgspace_N_56069_i), + .I2(cfg_cfg_6102[161]), + .I3(com_cmm_cfg_wr_data[25]), + .LO(com_cmm_u_cmm_cfgspace_bar3_reg_8_1_0_0_0_0[1]) + ); + defparam com_cmm_u_cmm_cfgspace_x3gio_bar2_bar2_reg_8_1_0_0_0_0_3_.INIT = 16'h4FCF; + LUT4_L com_cmm_u_cmm_cfgspace_x3gio_bar2_bar2_reg_8_1_0_0_0_0_3_ ( + .I0(com_cmm_u_cmm_cfgspace_N_55973_i), + .I1(com_cmm_u_cmm_cfgspace_N_56070_i), + .I2(cfg_cfg_6102[131]), + .I3(com_cmm_cfg_wr_data[27]), + .LO(com_cmm_u_cmm_cfgspace_bar2_reg_8_1_0_0_0_0[3]) + ); + defparam com_cmm_u_cmm_cfgspace_x3gio_bar1_bar1_reg_8_1_0_0_0_0_1_.INIT = 16'h4FCF; + LUT4_L com_cmm_u_cmm_cfgspace_x3gio_bar1_bar1_reg_8_1_0_0_0_0_1_ ( + .I0(com_cmm_u_cmm_cfgspace_N_55972_i), + .I1(com_cmm_u_cmm_cfgspace_N_56071_i), + .I2(cfg_cfg_6102[97]), + .I3(com_cmm_cfg_wr_data[25]), + .LO(com_cmm_u_cmm_cfgspace_bar1_reg_8_1_0_0_0_0[1]) + ); + defparam com_cmm_u_cmm_cfgspace_x3gio_bar2_bar2_reg_8_1_0_0_0_0_1_.INIT = 16'h4FCF; + LUT4_L com_cmm_u_cmm_cfgspace_x3gio_bar2_bar2_reg_8_1_0_0_0_0_1_ ( + .I0(com_cmm_u_cmm_cfgspace_N_55973_i), + .I1(com_cmm_u_cmm_cfgspace_N_56070_i), + .I2(cfg_cfg_6102[129]), + .I3(com_cmm_cfg_wr_data[25]), + .LO(com_cmm_u_cmm_cfgspace_bar2_reg_8_1_0_0_0_0[1]) + ); + defparam com_cmm_u_cmm_cfgspace_x3gio_bar3_bar3_reg_8_1_0_0_0_0_3_.INIT = 16'h4FCF; + LUT4_L com_cmm_u_cmm_cfgspace_x3gio_bar3_bar3_reg_8_1_0_0_0_0_3_ ( + .I0(com_cmm_u_cmm_cfgspace_N_55974_i), + .I1(com_cmm_u_cmm_cfgspace_N_56069_i), + .I2(cfg_cfg_6102[163]), + .I3(com_cmm_cfg_wr_data[27]), + .LO(com_cmm_u_cmm_cfgspace_bar3_reg_8_1_0_0_0_0[3]) + ); + defparam com_cmm_u_cmm_cfgspace_x3gio_bar3_bar3_reg_8_1_0_0_0_0_2_.INIT = 16'h4FCF; + LUT4_L com_cmm_u_cmm_cfgspace_x3gio_bar3_bar3_reg_8_1_0_0_0_0_2_ ( + .I0(com_cmm_u_cmm_cfgspace_N_55974_i), + .I1(com_cmm_u_cmm_cfgspace_N_56069_i), + .I2(cfg_cfg_6102[162]), + .I3(com_cmm_cfg_wr_data[26]), + .LO(com_cmm_u_cmm_cfgspace_bar3_reg_8_1_0_0_0_0[2]) + ); + defparam com_cmm_u_cmm_cfgspace_x3gio_bar2_bar2_reg_8_1_0_0_0_0_2_.INIT = 16'h4FCF; + LUT4_L com_cmm_u_cmm_cfgspace_x3gio_bar2_bar2_reg_8_1_0_0_0_0_2_ ( + .I0(com_cmm_u_cmm_cfgspace_N_55973_i), + .I1(com_cmm_u_cmm_cfgspace_N_56070_i), + .I2(cfg_cfg_6102[130]), + .I3(com_cmm_cfg_wr_data[26]), + .LO(com_cmm_u_cmm_cfgspace_bar2_reg_8_1_0_0_0_0[2]) + ); + defparam com_cmm_u_cmm_cfgspace_x3gio_bar1_bar1_reg_8_1_0_0_0_3_.INIT = 16'h4FCF; + LUT4_L com_cmm_u_cmm_cfgspace_x3gio_bar1_bar1_reg_8_1_0_0_0_3_ ( + .I0(com_cmm_u_cmm_cfgspace_N_55972_i), + .I1(com_cmm_u_cmm_cfgspace_N_56071_i), + .I2(cfg_cfg_6102[99]), + .I3(com_cmm_cfg_wr_data[27]), + .LO(com_cmm_u_cmm_cfgspace_bar1_reg_8_1_0_0_0[3]) + ); + defparam com_cmm_u_cmm_cfgspace_x3gio_bar1_bar1_reg_8_1_0_0_0_0_0_.INIT = 16'h4FCF; + LUT4_L com_cmm_u_cmm_cfgspace_x3gio_bar1_bar1_reg_8_1_0_0_0_0_0_ ( + .I0(com_cmm_u_cmm_cfgspace_N_55972_i), + .I1(com_cmm_u_cmm_cfgspace_N_56071_i), + .I2(cfg_cfg_6102[96]), + .I3(com_cmm_cfg_wr_data[24]), + .LO(com_cmm_u_cmm_cfgspace_bar1_reg_8_1_0_0_0_0[0]) + ); + defparam com_cmm_u_cmm_cfgspace_x3gio_bar2_bar2_reg_8_1_0_0_0_0_0_.INIT = 16'h4FCF; + LUT4_L com_cmm_u_cmm_cfgspace_x3gio_bar2_bar2_reg_8_1_0_0_0_0_0_ ( + .I0(com_cmm_u_cmm_cfgspace_N_55973_i), + .I1(com_cmm_u_cmm_cfgspace_N_56070_i), + .I2(cfg_cfg_6102[128]), + .I3(com_cmm_cfg_wr_data[24]), + .LO(com_cmm_u_cmm_cfgspace_bar2_reg_8_1_0_0_0_0[0]) + ); + defparam com_cmm_u_cmm_cfgspace_x3gio_bar3_bar3_reg_8_1_0_0_0_0_0_.INIT = 16'h4FCF; + LUT4_L com_cmm_u_cmm_cfgspace_x3gio_bar3_bar3_reg_8_1_0_0_0_0_0_ ( + .I0(com_cmm_u_cmm_cfgspace_N_55974_i), + .I1(com_cmm_u_cmm_cfgspace_N_56069_i), + .I2(cfg_cfg_6102[160]), + .I3(com_cmm_cfg_wr_data[24]), + .LO(com_cmm_u_cmm_cfgspace_bar3_reg_8_1_0_0_0_0[0]) + ); + defparam com_cmm_u_cmm_cfgspace_x3gio_bar1_bar1_reg_8_1_0_0_0_0_2_.INIT = 16'h4FCF; + LUT4_L com_cmm_u_cmm_cfgspace_x3gio_bar1_bar1_reg_8_1_0_0_0_0_2_ ( + .I0(com_cmm_u_cmm_cfgspace_N_55972_i), + .I1(com_cmm_u_cmm_cfgspace_N_56071_i), + .I2(cfg_cfg_6102[98]), + .I3(com_cmm_cfg_wr_data[26]), + .LO(com_cmm_u_cmm_cfgspace_bar1_reg_8_1_0_0_0_0[2]) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_01_7_0_am_24_.INIT = 16'hC0AA; + LUT4 com_cmm_u_cmm_cfgspace_low_addr_01_7_0_am_24_ ( + .I0(com_cmm_u_cmm_cfgspace_N_3754), + .I1(com_cmm_u_cmm_cfgspace_N_61397), + .I2(com_cmm_u_cmm_cfgspace_N_63596), + .I3(com_cmm_u_cmm_cfgspace_sel_encodex_2[2]), + .O(com_cmm_u_cmm_cfgspace_low_addr_01_7_0_am_24__5677) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_01_7_0_bm_24_.INIT = 16'hA00C; + LUT4 com_cmm_u_cmm_cfgspace_low_addr_01_7_0_bm_24_ ( + .I0(cfg_cfg_6102[680]), + .I1(com_cmm_bar1_reg[24]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex_2[1]), + .I3(com_cmm_u_cmm_cfgspace_sel_encodex_2[2]), + .O(com_cmm_u_cmm_cfgspace_low_addr_01_7_0_bm_24__5676) + ); + MUXF5 com_cmm_u_cmm_cfgspace_low_addr_01_7_0_24_ ( + .I0(com_cmm_u_cmm_cfgspace_low_addr_01_7_0_am_24__5677), + .I1(com_cmm_u_cmm_cfgspace_low_addr_01_7_0_bm_24__5676), + .O(com_cmm_u_cmm_cfgspace_low_addr_01[24]), + .S(com_cmm_u_cmm_cfgspace_sel_encodex[0]) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_01_7_0_am_25_.INIT = 16'hAAC0; + LUT4 com_cmm_u_cmm_cfgspace_low_addr_01_7_0_am_25_ ( + .I0(com_cmm_u_cmm_cfgspace_N_59875), + .I1(com_cmm_bar5_reg[25]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex_2[1]), + .I3(com_cmm_u_cmm_cfgspace_sel_encodex_2[2]), + .O(com_cmm_u_cmm_cfgspace_low_addr_01_7_0_am_25__5679) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_01_7_0_bm_25_.INIT = 16'hA00C; + LUT4 com_cmm_u_cmm_cfgspace_low_addr_01_7_0_bm_25_ ( + .I0(cfg_cfg_6102[681]), + .I1(com_cmm_bar1_reg[25]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex_2[1]), + .I3(com_cmm_u_cmm_cfgspace_sel_encodex_2[2]), + .O(com_cmm_u_cmm_cfgspace_low_addr_01_7_0_bm_25__5678) + ); + MUXF5 com_cmm_u_cmm_cfgspace_low_addr_01_7_0_25_ ( + .I0(com_cmm_u_cmm_cfgspace_low_addr_01_7_0_am_25__5679), + .I1(com_cmm_u_cmm_cfgspace_low_addr_01_7_0_bm_25__5678), + .O(com_cmm_u_cmm_cfgspace_low_addr_01[25]), + .S(com_cmm_u_cmm_cfgspace_sel_encodex[0]) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_01_7_0_am_26_.INIT = 16'hAAC0; + LUT4 com_cmm_u_cmm_cfgspace_low_addr_01_7_0_am_26_ ( + .I0(com_cmm_u_cmm_cfgspace_N_59876), + .I1(com_cmm_bar5_reg[26]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex_2[1]), + .I3(com_cmm_u_cmm_cfgspace_sel_encodex_2[2]), + .O(com_cmm_u_cmm_cfgspace_low_addr_01_7_0_am_26__5681) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_01_7_0_bm_26_.INIT = 16'hA00C; + LUT4 com_cmm_u_cmm_cfgspace_low_addr_01_7_0_bm_26_ ( + .I0(cfg_cfg_6102[682]), + .I1(com_cmm_bar1_reg[26]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex_2[1]), + .I3(com_cmm_u_cmm_cfgspace_sel_encodex_2[2]), + .O(com_cmm_u_cmm_cfgspace_low_addr_01_7_0_bm_26__5680) + ); + MUXF5 com_cmm_u_cmm_cfgspace_low_addr_01_7_0_26_ ( + .I0(com_cmm_u_cmm_cfgspace_low_addr_01_7_0_am_26__5681), + .I1(com_cmm_u_cmm_cfgspace_low_addr_01_7_0_bm_26__5680), + .O(com_cmm_u_cmm_cfgspace_low_addr_01[26]), + .S(com_cmm_u_cmm_cfgspace_sel_encodex[0]) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_01_7_0_am_27_.INIT = 16'hC0AA; + LUT4 com_cmm_u_cmm_cfgspace_low_addr_01_7_0_am_27_ ( + .I0(com_cmm_u_cmm_cfgspace_N_3757), + .I1(com_cmm_u_cmm_cfgspace_N_61397), + .I2(com_cmm_u_cmm_cfgspace_N_63599), + .I3(com_cmm_u_cmm_cfgspace_sel_encodex_2[2]), + .O(com_cmm_u_cmm_cfgspace_low_addr_01_7_0_am_27__5683) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_01_7_0_bm_27_.INIT = 16'hA00C; + LUT4 com_cmm_u_cmm_cfgspace_low_addr_01_7_0_bm_27_ ( + .I0(cfg_cfg_6102[683]), + .I1(com_cmm_bar1_reg[27]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex_2[1]), + .I3(com_cmm_u_cmm_cfgspace_sel_encodex_2[2]), + .O(com_cmm_u_cmm_cfgspace_low_addr_01_7_0_bm_27__5682) + ); + MUXF5 com_cmm_u_cmm_cfgspace_low_addr_01_7_0_27_ ( + .I0(com_cmm_u_cmm_cfgspace_low_addr_01_7_0_am_27__5683), + .I1(com_cmm_u_cmm_cfgspace_low_addr_01_7_0_bm_27__5682), + .O(com_cmm_u_cmm_cfgspace_low_addr_01[27]), + .S(com_cmm_u_cmm_cfgspace_sel_encodex[0]) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_01_7_0_am_28_.INIT = 16'hC0AA; + LUT4 com_cmm_u_cmm_cfgspace_low_addr_01_7_0_am_28_ ( + .I0(com_cmm_u_cmm_cfgspace_N_3758), + .I1(com_cmm_u_cmm_cfgspace_N_61397), + .I2(com_cmm_u_cmm_cfgspace_N_63600), + .I3(com_cmm_u_cmm_cfgspace_sel_encodex_2[2]), + .O(com_cmm_u_cmm_cfgspace_low_addr_01_7_0_am_28__5685) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_01_7_0_bm_28_.INIT = 16'hA00C; + LUT4 com_cmm_u_cmm_cfgspace_low_addr_01_7_0_bm_28_ ( + .I0(cfg_cfg_6102[684]), + .I1(com_cmm_bar1_reg[28]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex_2[1]), + .I3(com_cmm_u_cmm_cfgspace_sel_encodex_2[2]), + .O(com_cmm_u_cmm_cfgspace_low_addr_01_7_0_bm_28__5684) + ); + MUXF5 com_cmm_u_cmm_cfgspace_low_addr_01_7_0_28_ ( + .I0(com_cmm_u_cmm_cfgspace_low_addr_01_7_0_am_28__5685), + .I1(com_cmm_u_cmm_cfgspace_low_addr_01_7_0_bm_28__5684), + .O(com_cmm_u_cmm_cfgspace_low_addr_01[28]), + .S(com_cmm_u_cmm_cfgspace_sel_encodex[0]) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_01_7_0_am_29_.INIT = 16'hC0AA; + LUT4 com_cmm_u_cmm_cfgspace_low_addr_01_7_0_am_29_ ( + .I0(com_cmm_u_cmm_cfgspace_N_3759), + .I1(com_cmm_u_cmm_cfgspace_N_61397), + .I2(com_cmm_u_cmm_cfgspace_N_63601), + .I3(com_cmm_u_cmm_cfgspace_sel_encodex_2[2]), + .O(com_cmm_u_cmm_cfgspace_low_addr_01_7_0_am_29__5687) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_01_7_0_bm_29_.INIT = 16'hA00C; + LUT4 com_cmm_u_cmm_cfgspace_low_addr_01_7_0_bm_29_ ( + .I0(cfg_cfg_6102[685]), + .I1(com_cmm_bar1_reg[29]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex_2[1]), + .I3(com_cmm_u_cmm_cfgspace_sel_encodex_2[2]), + .O(com_cmm_u_cmm_cfgspace_low_addr_01_7_0_bm_29__5686) + ); + MUXF5 com_cmm_u_cmm_cfgspace_low_addr_01_7_0_29_ ( + .I0(com_cmm_u_cmm_cfgspace_low_addr_01_7_0_am_29__5687), + .I1(com_cmm_u_cmm_cfgspace_low_addr_01_7_0_bm_29__5686), + .O(com_cmm_u_cmm_cfgspace_low_addr_01[29]), + .S(com_cmm_u_cmm_cfgspace_sel_encodex[0]) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_01_7_0_am_30_.INIT = 16'hC0AA; + LUT4 com_cmm_u_cmm_cfgspace_low_addr_01_7_0_am_30_ ( + .I0(com_cmm_u_cmm_cfgspace_N_3760), + .I1(com_cmm_u_cmm_cfgspace_N_61397), + .I2(com_cmm_u_cmm_cfgspace_N_63602), + .I3(com_cmm_u_cmm_cfgspace_sel_encodex_2[2]), + .O(com_cmm_u_cmm_cfgspace_low_addr_01_7_0_am_30__5689) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_01_7_0_bm_30_.INIT = 16'hA00C; + LUT4 com_cmm_u_cmm_cfgspace_low_addr_01_7_0_bm_30_ ( + .I0(cfg_cfg_6102[686]), + .I1(com_cmm_bar1_reg[30]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex_2[1]), + .I3(com_cmm_u_cmm_cfgspace_sel_encodex_2[2]), + .O(com_cmm_u_cmm_cfgspace_low_addr_01_7_0_bm_30__5688) + ); + MUXF5 com_cmm_u_cmm_cfgspace_low_addr_01_7_0_30_ ( + .I0(com_cmm_u_cmm_cfgspace_low_addr_01_7_0_am_30__5689), + .I1(com_cmm_u_cmm_cfgspace_low_addr_01_7_0_bm_30__5688), + .O(com_cmm_u_cmm_cfgspace_low_addr_01[30]), + .S(com_cmm_u_cmm_cfgspace_sel_encodex[0]) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_01_7_0_am_31_.INIT = 16'hC0AA; + LUT4 com_cmm_u_cmm_cfgspace_low_addr_01_7_0_am_31_ ( + .I0(com_cmm_u_cmm_cfgspace_N_3761), + .I1(com_cmm_u_cmm_cfgspace_N_61397), + .I2(com_cmm_u_cmm_cfgspace_N_63603), + .I3(com_cmm_u_cmm_cfgspace_sel_encodex_2[2]), + .O(com_cmm_u_cmm_cfgspace_low_addr_01_7_0_am_31__5691) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_01_7_0_bm_31_.INIT = 16'hA00C; + LUT4 com_cmm_u_cmm_cfgspace_low_addr_01_7_0_bm_31_ ( + .I0(cfg_cfg_6102[687]), + .I1(com_cmm_bar1_reg[31]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex_2[1]), + .I3(com_cmm_u_cmm_cfgspace_sel_encodex_2[2]), + .O(com_cmm_u_cmm_cfgspace_low_addr_01_7_0_bm_31__5690) + ); + MUXF5 com_cmm_u_cmm_cfgspace_low_addr_01_7_0_31_ ( + .I0(com_cmm_u_cmm_cfgspace_low_addr_01_7_0_am_31__5691), + .I1(com_cmm_u_cmm_cfgspace_low_addr_01_7_0_bm_31__5690), + .O(com_cmm_u_cmm_cfgspace_low_addr_01[31]), + .S(com_cmm_u_cmm_cfgspace_sel_encodex[0]) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_00_i_0_a3_1_.INIT = 8'h08; + LUT3 com_cmm_u_cmm_cfgspace_low_addr_00_i_0_a3_1_ ( + .I0(com_cmm_u_cmm_cfgspace_sel_encodex[0]), + .I1(com_cmm_u_cmm_cfgspace_sel_encodex_2[1]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex_2[2]), + .O(com_cmm_u_cmm_cfgspace_N_61371) + ); + defparam com_cmm_u_cmm_cfgspace_x3gio_decodepipe_h_N_86820_i.INIT = 8'hEC; + LUT3_L com_cmm_u_cmm_cfgspace_x3gio_decodepipe_h_N_86820_i ( + .I0(com_cmm_u_cmm_cfgspace_N_57264_2), + .I1(com_cmm_u_cmm_cfgspace_N_57265), + .I2(cfg_dwaddr_6099[2]), + .LO(com_cmm_u_cmm_cfgspace_N_86820_i) + ); + defparam com_cmm_u_cmm_cfgspace_x3gio_decodepipe_h_N_86821_i.INIT = 8'hAE; + LUT3_L com_cmm_u_cmm_cfgspace_x3gio_decodepipe_h_N_86821_i ( + .I0(com_cmm_u_cmm_cfgspace_N_57263), + .I1(com_cmm_u_cmm_cfgspace_N_57264_2), + .I2(cfg_dwaddr_6099[2]), + .LO(com_cmm_u_cmm_cfgspace_N_86821_i) + ); + defparam com_cmm_u_cmm_cfgspace_x3gio_decodepipe_h_N_86822_i.INIT = 8'hEC; + LUT3_L com_cmm_u_cmm_cfgspace_x3gio_decodepipe_h_N_86822_i ( + .I0(com_cmm_u_cmm_cfgspace_N_57260_2), + .I1(com_cmm_u_cmm_cfgspace_N_57261), + .I2(cfg_dwaddr_6099[2]), + .LO(com_cmm_u_cmm_cfgspace_N_86822_i) + ); + defparam com_cmm_u_cmm_cfgspace_x3gio_decodepipe_h_N_86266_i.INIT = 8'hAE; + LUT3_L com_cmm_u_cmm_cfgspace_x3gio_decodepipe_h_N_86266_i ( + .I0(com_cmm_u_cmm_cfgspace_N_57259), + .I1(com_cmm_u_cmm_cfgspace_N_57260_2), + .I2(cfg_dwaddr_6099[2]), + .LO(com_cmm_u_cmm_cfgspace_N_86266_i) + ); + defparam com_cmm_u_cmm_cfgspace_x3gio_decodepipe_h_N_86823_i.INIT = 16'hEAAA; + LUT4_L com_cmm_u_cmm_cfgspace_x3gio_decodepipe_h_N_86823_i ( + .I0(com_cmm_u_cmm_cfgspace_N_57257), + .I1(com_cmm_u_cmm_cfgspace_N_57266_1), + .I2(com_cmm_u_cmm_cfgspace_N_58589_2), + .I3(cfg_dwaddr_6099[2]), + .LO(com_cmm_u_cmm_cfgspace_N_86823_i) + ); + defparam com_cmm_u_cmm_cfgspace_x3gio_decodepipe_h_N_85811_i.INIT = 8'h2F; + LUT3_L com_cmm_u_cmm_cfgspace_x3gio_decodepipe_h_N_85811_i ( + .I0(com_cmm_u_cmm_cfgspace_N_58589), + .I1(cfg_dwaddr_6099[6]), + .I2(com_cmm_u_cmm_cfgspace_sel_0x_3_0_0_0_0_0), + .LO(com_cmm_u_cmm_cfgspace_N_85811_i) + ); + defparam com_cmm_u_cmm_cfgspace_x3gio_decodepipe_h_N_86819_i.INIT = 16'hECCC; + LUT4_L com_cmm_u_cmm_cfgspace_x3gio_decodepipe_h_N_86819_i ( + .I0(com_cmm_u_cmm_cfgspace_N_56350_i), + .I1(com_cmm_u_cmm_cfgspace_N_57266), + .I2(com_cmm_u_cmm_cfgspace_N_61290_1), + .I3(com_cmm_u_cmm_cfgspace_N_61378), + .LO(com_cmm_u_cmm_cfgspace_N_86819_i) + ); + defparam com_cmm_u_cmm_cfgspace_x3gio_decodepipe_l_sel_xa_3_i_0_0.INIT = 16'hA020; + LUT4_L com_cmm_u_cmm_cfgspace_x3gio_decodepipe_l_sel_xa_3_i_0_0 ( + .I0(com_cmm_u_cmm_cfgspace_N_55900), + .I1(com_cmm_u_cmm_cfgspace_N_59237_1), + .I2(com_cmm_u_cmm_cfgspace_sel_x0_3_i_0_0_o3), + .I3(com_cmm_cfg_be[2]), + .LO(com_cmm_u_cmm_cfgspace_N_33690_i) + ); + defparam com_cmm_u_cmm_cfgspace_x3gio_decodepipe_l_sel_x9_3_i_0_0.INIT = 16'hA020; + LUT4_L com_cmm_u_cmm_cfgspace_x3gio_decodepipe_l_sel_x9_3_i_0_0 ( + .I0(com_cmm_u_cmm_cfgspace_N_55900), + .I1(com_cmm_u_cmm_cfgspace_N_59237_1), + .I2(com_cmm_u_cmm_cfgspace_sel_x0_3_i_0_0_o3), + .I3(com_cmm_cfg_be[1]), + .LO(com_cmm_u_cmm_cfgspace_N_33688_i) + ); + defparam com_cmm_u_cmm_cfgspace_x3gio_decodepipe_l_sel_x8_3_i_0_0.INIT = 16'hA020; + LUT4_L com_cmm_u_cmm_cfgspace_x3gio_decodepipe_l_sel_x8_3_i_0_0 ( + .I0(com_cmm_u_cmm_cfgspace_N_55900), + .I1(com_cmm_u_cmm_cfgspace_N_59237_1), + .I2(com_cmm_u_cmm_cfgspace_sel_x0_3_i_0_0_o3), + .I3(com_cmm_cfg_be[0]), + .LO(com_cmm_u_cmm_cfgspace_N_33686_i) + ); + defparam com_cmm_u_cmm_cfgspace_x3gio_decodepipe_l_sel_x7_3_i_0_0.INIT = 16'h5010; + LUT4_L com_cmm_u_cmm_cfgspace_x3gio_decodepipe_l_sel_x7_3_i_0_0 ( + .I0(com_cmm_u_cmm_cfgspace_N_55900), + .I1(com_cmm_u_cmm_cfgspace_N_59237_1), + .I2(com_cmm_u_cmm_cfgspace_sel_x4_3_i_0_0_o3), + .I3(com_cmm_cfg_be[3]), + .LO(com_cmm_u_cmm_cfgspace_N_33684_i) + ); + defparam com_cmm_u_cmm_cfgspace_x3gio_decodepipe_l_sel_x6_3_i_0_0.INIT = 16'h5010; + LUT4_L com_cmm_u_cmm_cfgspace_x3gio_decodepipe_l_sel_x6_3_i_0_0 ( + .I0(com_cmm_u_cmm_cfgspace_N_55900), + .I1(com_cmm_u_cmm_cfgspace_N_59237_1), + .I2(com_cmm_u_cmm_cfgspace_sel_x4_3_i_0_0_o3), + .I3(com_cmm_cfg_be[2]), + .LO(com_cmm_u_cmm_cfgspace_N_33682_i) + ); + defparam com_cmm_u_cmm_cfgspace_x3gio_decodepipe_l_sel_x5_3_i_0_0.INIT = 16'h5010; + LUT4_L com_cmm_u_cmm_cfgspace_x3gio_decodepipe_l_sel_x5_3_i_0_0 ( + .I0(com_cmm_u_cmm_cfgspace_N_55900), + .I1(com_cmm_u_cmm_cfgspace_N_59237_1), + .I2(com_cmm_u_cmm_cfgspace_sel_x4_3_i_0_0_o3), + .I3(com_cmm_cfg_be[1]), + .LO(com_cmm_u_cmm_cfgspace_N_33680_i) + ); + defparam com_cmm_u_cmm_cfgspace_x3gio_decodepipe_l_sel_x4_3_i_0_0.INIT = 16'h5010; + LUT4_L com_cmm_u_cmm_cfgspace_x3gio_decodepipe_l_sel_x4_3_i_0_0 ( + .I0(com_cmm_u_cmm_cfgspace_N_55900), + .I1(com_cmm_u_cmm_cfgspace_N_59237_1), + .I2(com_cmm_u_cmm_cfgspace_sel_x4_3_i_0_0_o3), + .I3(com_cmm_cfg_be[0]), + .LO(com_cmm_u_cmm_cfgspace_N_33678_i) + ); + defparam com_cmm_u_cmm_cfgspace_x3gio_decodepipe_l_sel_x3_3_i_0_0.INIT = 16'h5010; + LUT4_L com_cmm_u_cmm_cfgspace_x3gio_decodepipe_l_sel_x3_3_i_0_0 ( + .I0(com_cmm_u_cmm_cfgspace_N_55900), + .I1(com_cmm_u_cmm_cfgspace_N_59237_1), + .I2(com_cmm_u_cmm_cfgspace_sel_x0_3_i_0_0_o3), + .I3(com_cmm_cfg_be[3]), + .LO(com_cmm_u_cmm_cfgspace_N_33676_i) + ); + defparam com_cmm_u_cmm_cfgspace_x3gio_decodepipe_l_sel_x2_3_i_0_0.INIT = 16'h5010; + LUT4_L com_cmm_u_cmm_cfgspace_x3gio_decodepipe_l_sel_x2_3_i_0_0 ( + .I0(com_cmm_u_cmm_cfgspace_N_55900), + .I1(com_cmm_u_cmm_cfgspace_N_59237_1), + .I2(com_cmm_u_cmm_cfgspace_sel_x0_3_i_0_0_o3), + .I3(com_cmm_cfg_be[2]), + .LO(com_cmm_u_cmm_cfgspace_N_33674_i) + ); + defparam com_cmm_u_cmm_cfgspace_x3gio_decodepipe_l_sel_x1_3_i_0_0.INIT = 16'h5010; + LUT4_L com_cmm_u_cmm_cfgspace_x3gio_decodepipe_l_sel_x1_3_i_0_0 ( + .I0(com_cmm_u_cmm_cfgspace_N_55900), + .I1(com_cmm_u_cmm_cfgspace_N_59237_1), + .I2(com_cmm_u_cmm_cfgspace_sel_x0_3_i_0_0_o3), + .I3(com_cmm_cfg_be[1]), + .LO(com_cmm_u_cmm_cfgspace_N_33672_i) + ); + defparam com_cmm_u_cmm_cfgspace_x3gio_decodepipe_l_sel_x0_3_i_0_0.INIT = 16'h5010; + LUT4_L com_cmm_u_cmm_cfgspace_x3gio_decodepipe_l_sel_x0_3_i_0_0 ( + .I0(com_cmm_u_cmm_cfgspace_N_55900), + .I1(com_cmm_u_cmm_cfgspace_N_59237_1), + .I2(com_cmm_u_cmm_cfgspace_sel_x0_3_i_0_0_o3), + .I3(com_cmm_cfg_be[0]), + .LO(com_cmm_u_cmm_cfgspace_N_33670_i) + ); + defparam com_cmm_u_cmm_cfgspace_x3gio_decodepipe_l_sel_xf_3_i_0_0.INIT = 16'hA020; + LUT4_L com_cmm_u_cmm_cfgspace_x3gio_decodepipe_l_sel_xf_3_i_0_0 ( + .I0(com_cmm_u_cmm_cfgspace_N_55900), + .I1(com_cmm_u_cmm_cfgspace_N_59237_1), + .I2(com_cmm_u_cmm_cfgspace_sel_x4_3_i_0_0_o3), + .I3(com_cmm_cfg_be[3]), + .LO(com_cmm_u_cmm_cfgspace_N_33700_i) + ); + defparam com_cmm_u_cmm_cfgspace_x3gio_decodepipe_l_sel_xe_3_i_0_0.INIT = 16'hA020; + LUT4_L com_cmm_u_cmm_cfgspace_x3gio_decodepipe_l_sel_xe_3_i_0_0 ( + .I0(com_cmm_u_cmm_cfgspace_N_55900), + .I1(com_cmm_u_cmm_cfgspace_N_59237_1), + .I2(com_cmm_u_cmm_cfgspace_sel_x4_3_i_0_0_o3), + .I3(com_cmm_cfg_be[2]), + .LO(com_cmm_u_cmm_cfgspace_N_33698_i) + ); + defparam com_cmm_u_cmm_cfgspace_x3gio_decodepipe_l_sel_xd_3_i_0_0.INIT = 16'hA020; + LUT4_L com_cmm_u_cmm_cfgspace_x3gio_decodepipe_l_sel_xd_3_i_0_0 ( + .I0(com_cmm_u_cmm_cfgspace_N_55900), + .I1(com_cmm_u_cmm_cfgspace_N_59237_1), + .I2(com_cmm_u_cmm_cfgspace_sel_x4_3_i_0_0_o3), + .I3(com_cmm_cfg_be[1]), + .LO(com_cmm_u_cmm_cfgspace_N_33696_i) + ); + defparam com_cmm_u_cmm_cfgspace_x3gio_decodepipe_l_sel_xc_3_i_0_0.INIT = 16'hA020; + LUT4_L com_cmm_u_cmm_cfgspace_x3gio_decodepipe_l_sel_xc_3_i_0_0 ( + .I0(com_cmm_u_cmm_cfgspace_N_55900), + .I1(com_cmm_u_cmm_cfgspace_N_59237_1), + .I2(com_cmm_u_cmm_cfgspace_sel_x4_3_i_0_0_o3), + .I3(com_cmm_cfg_be[0]), + .LO(com_cmm_u_cmm_cfgspace_N_33694_i) + ); + defparam com_cmm_u_cmm_cfgspace_x3gio_decodepipe_l_sel_xb_3_i_0_0.INIT = 16'hA020; + LUT4_L com_cmm_u_cmm_cfgspace_x3gio_decodepipe_l_sel_xb_3_i_0_0 ( + .I0(com_cmm_u_cmm_cfgspace_N_55900), + .I1(com_cmm_u_cmm_cfgspace_N_59237_1), + .I2(com_cmm_u_cmm_cfgspace_sel_x0_3_i_0_0_o3), + .I3(com_cmm_cfg_be[3]), + .LO(com_cmm_u_cmm_cfgspace_N_33692_i) + ); + defparam com_cmm_u_cmm_cfgspace_x3gio_pmcsr_pme_pmcsr_21_i_0_0_0_1_.INIT = 16'h00D8; + LUT4_L com_cmm_u_cmm_cfgspace_x3gio_pmcsr_pme_pmcsr_21_i_0_0_0_1_ ( + .I0(com_cmm_u_cmm_cfgspace_pme_pmcsr_21_i_0_0_0_o3[0]), + .I1(com_cmm_cfg_wr_data[25]), + .I2(com_cmm_pme_pmcsr[1]), + .I3(com_cmm_rst_351), + .LO(com_cmm_u_cmm_cfgspace_N_17863_i) + ); + defparam com_cmm_u_cmm_cfgspace_x3gio_pmcsr_pme_pmcsr_21_i_0_0_0_0_.INIT = 16'h00D8; + LUT4_L com_cmm_u_cmm_cfgspace_x3gio_pmcsr_pme_pmcsr_21_i_0_0_0_0_ ( + .I0(com_cmm_u_cmm_cfgspace_pme_pmcsr_21_i_0_0_0_o3[0]), + .I1(com_cmm_cfg_wr_data[24]), + .I2(com_cmm_pme_pmcsr[0]), + .I3(com_cmm_rst_351), + .LO(com_cmm_u_cmm_cfgspace_N_17861_i) + ); + defparam com_cmm_u_cmm_cfgspace_x3gio_status_status_10_iv_0_0_0_0_14_.INIT = 16'hFF4C; + LUT4_L com_cmm_u_cmm_cfgspace_x3gio_status_status_10_iv_0_0_0_0_14_ ( + .I0(com_cmm_u_cmm_cfgspace_N_58308_1), + .I1(NlwRenamedSig_OI_cfg_status_14_), + .I2(com_cmm_cfg_wr_data_6_), + .I3(com_cmm_u_cmm_cfgspace_set_signaledsystemerror_5762), + .LO(com_cmm_u_cmm_cfgspace_N_9940_i) + ); + defparam com_cmm_u_cmm_cfgspace_x3gio_status_status_14_iv_0_0_0_0_13_.INIT = 16'hFF4C; + LUT4_L com_cmm_u_cmm_cfgspace_x3gio_status_status_14_iv_0_0_0_0_13_ ( + .I0(com_cmm_u_cmm_cfgspace_N_58308_1), + .I1(NlwRenamedSig_OI_cfg_status_13_), + .I2(com_cmm_cfg_wr_data_5_), + .I3(com_cmm_u_cmm_cfgspace_set_receivedmasterabort_5765), + .LO(com_cmm_u_cmm_cfgspace_N_9939_i) + ); + defparam com_cmm_u_cmm_cfgspace_x3gio_status_status_18_iv_0_0_0_0_12_.INIT = 16'hFF4C; + LUT4_L com_cmm_u_cmm_cfgspace_x3gio_status_status_18_iv_0_0_0_0_12_ ( + .I0(com_cmm_u_cmm_cfgspace_N_58308_1), + .I1(NlwRenamedSig_OI_cfg_status_12_), + .I2(com_cmm_cfg_wr_data_4_), + .I3(com_cmm_u_cmm_cfgspace_set_receivedtargetabort_5764), + .LO(com_cmm_u_cmm_cfgspace_N_9938_i) + ); + defparam com_cmm_u_cmm_cfgspace_x3gio_status_status_22_iv_0_0_0_0_11_.INIT = 16'hFF4C; + LUT4_L com_cmm_u_cmm_cfgspace_x3gio_status_status_22_iv_0_0_0_0_11_ ( + .I0(com_cmm_u_cmm_cfgspace_N_58308_1), + .I1(NlwRenamedSig_OI_cfg_status_11_), + .I2(com_cmm_cfg_wr_data_3_), + .I3(com_cmm_u_cmm_cfgspace_set_signaledtargetabort_5761), + .LO(com_cmm_u_cmm_cfgspace_N_9937_i) + ); + defparam com_cmm_u_cmm_cfgspace_x3gio_status_status_28_iv_0_0_0_0_8_.INIT = 16'hFF4C; + LUT4_L com_cmm_u_cmm_cfgspace_x3gio_status_status_28_iv_0_0_0_0_8_ ( + .I0(com_cmm_u_cmm_cfgspace_N_58308_1), + .I1(NlwRenamedSig_OI_cfg_status_8_), + .I2(com_cmm_cfg_wr_data_0_), + .I3(com_cmm_u_cmm_cfgspace_set_masterdataparityerror_5766), + .LO(com_cmm_u_cmm_cfgspace_N_9951_i) + ); + defparam com_cmm_u_cmm_cfgspace_x3gio_pmcsr_pme_pmcsr_20_iv_0_0_0_0_15_.INIT = 16'hFF70; + LUT4_L com_cmm_u_cmm_cfgspace_x3gio_pmcsr_pme_pmcsr_20_iv_0_0_0_0_15_ ( + .I0(N_56053_i), + .I1(com_cmm_cfg_wr_data_23_), + .I2(com_cmm_u_cmm_cfgspace_pme_pmcsr[15]), + .I3(com_cmm_u_cmm_cfgspace_set_signaledpme_5763), + .LO(com_cmm_u_cmm_cfgspace_N_9950_i) + ); + defparam com_cmm_u_cmm_cfgspace_x3gio_pmcsr_pme_pmcsr_21_0_a2_0_a2_0_a2_14_.INIT = 16'hAC00; + LUT4_L com_cmm_u_cmm_cfgspace_x3gio_pmcsr_pme_pmcsr_21_0_a2_0_a2_0_a2_14_ ( + .I0(com_cmm_u_cmm_cfgspace_N_63539), + .I1(com_cmm_u_cmm_cfgspace_N_63569), + .I2(com_cmm_u_cmm_cfgspace_pme_pmcsr[10]), + .I3(com_cmm_u_cmm_cfgspace_pme_pmcsr_21_1[14]), + .LO(com_cmm_u_cmm_cfgspace_pme_pmcsr_21[14]) + ); + defparam com_cmm_u_cmm_cfgspace_x3gio_pmcsr_pme_pmcsr_21_0_a2_0_a2_0_a2_13_.INIT = 16'hAC00; + LUT4_L com_cmm_u_cmm_cfgspace_x3gio_pmcsr_pme_pmcsr_21_0_a2_0_a2_0_a2_13_ ( + .I0(com_cmm_u_cmm_cfgspace_N_63538), + .I1(com_cmm_u_cmm_cfgspace_N_63568), + .I2(com_cmm_u_cmm_cfgspace_pme_pmcsr[10]), + .I3(com_cmm_u_cmm_cfgspace_pme_pmcsr_21_1[14]), + .LO(com_cmm_u_cmm_cfgspace_pme_pmcsr_21[13]) + ); + defparam com_cmm_u_cmm_cfgspace_x3gio_pmcsr_pme_pmcsr_21_0_i_0_0_12_.INIT = 16'h00D8; + LUT4_L com_cmm_u_cmm_cfgspace_x3gio_pmcsr_pme_pmcsr_21_0_i_0_0_12_ ( + .I0(N_56053_i), + .I1(com_cmm_cfg_wr_data_20_), + .I2(com_cmm_u_cmm_cfgspace_pme_pmcsr[12]), + .I3(com_cmm_rst_351), + .LO(com_cmm_u_cmm_cfgspace_N_35656_i) + ); + defparam com_cmm_u_cmm_cfgspace_x3gio_pmcsr_pme_pmcsr_21_0_i_0_11_.INIT = 16'h00D8; + LUT4_L com_cmm_u_cmm_cfgspace_x3gio_pmcsr_pme_pmcsr_21_0_i_0_11_ ( + .I0(N_56053_i), + .I1(com_cmm_cfg_wr_data_19_), + .I2(com_cmm_u_cmm_cfgspace_pme_pmcsr[11]), + .I3(com_cmm_rst_351), + .LO(com_cmm_u_cmm_cfgspace_N_39977_i) + ); + defparam com_cmm_u_cmm_cfgspace_x3gio_pmcsr_pme_pmcsr_21_0_i_0_10_.INIT = 16'h00D8; + LUT4_L com_cmm_u_cmm_cfgspace_x3gio_pmcsr_pme_pmcsr_21_0_i_0_10_ ( + .I0(N_56053_i), + .I1(com_cmm_cfg_wr_data_18_), + .I2(com_cmm_u_cmm_cfgspace_pme_pmcsr[10]), + .I3(com_cmm_rst_351), + .LO(com_cmm_u_cmm_cfgspace_N_39975_i) + ); + defparam com_cmm_u_cmm_cfgspace_x3gio_pmcsr_pme_pmcsr_21_0_i_0_0_9_.INIT = 16'h00D8; + LUT4_L com_cmm_u_cmm_cfgspace_x3gio_pmcsr_pme_pmcsr_21_0_i_0_0_9_ ( + .I0(N_56053_i), + .I1(com_cmm_cfg_wr_data_17_), + .I2(com_cmm_u_cmm_cfgspace_pme_pmcsr[9]), + .I3(com_cmm_rst_351), + .LO(com_cmm_u_cmm_cfgspace_N_35654_i) + ); + defparam com_cmm_u_cmm_cfgspace_x3gio_bar1_N_85866_i.INIT = 8'h8F; + LUT3_L com_cmm_u_cmm_cfgspace_x3gio_bar1_N_85866_i ( + .I0(com_cmm_u_cmm_cfgspace_N_57880_1), + .I1(com_cmm_bar1_reg[1]), + .I2(com_cmm_u_cmm_cfgspace_bar1_reg_8_1_0_0_0_0[1]), + .LO(com_cmm_u_cmm_cfgspace_N_85866_i) + ); + defparam com_cmm_u_cmm_cfgspace_x3gio_bar1_N_85865_i.INIT = 8'h8F; + LUT3_L com_cmm_u_cmm_cfgspace_x3gio_bar1_N_85865_i ( + .I0(com_cmm_u_cmm_cfgspace_N_57880_1), + .I1(com_cmm_bar1_reg[0]), + .I2(com_cmm_u_cmm_cfgspace_bar1_reg_8_1_0_0_0_0[0]), + .LO(com_cmm_u_cmm_cfgspace_N_85865_i) + ); + defparam com_cmm_u_cmm_cfgspace_next_state_0_sqmuxa_i_0_0.INIT = 16'hE000; + LUT4_L com_cmm_u_cmm_cfgspace_next_state_0_sqmuxa_i_0_0 ( + .I0(com_cmm_N_55868_i), + .I1(com_cmm_cfg_rd), + .I2(com_cmm_state_0[1]), + .I3(com_cmm_u_cmm_cfgspace_state_0__5800), + .LO(com_cmm_u_cmm_cfgspace_N_33655_i) + ); + defparam com_cmm_u_cmm_cfgspace_next_state_1_sqmuxa_i_0_0_0.INIT = 4'h2; + LUT2_L com_cmm_u_cmm_cfgspace_next_state_1_sqmuxa_i_0_0_0 ( + .I0(com_cmm_u_cmm_cfgspace_N_58586_1), + .I1(cfg_rd_en_n), + .LO(com_cmm_u_cmm_cfgspace_N_18655_i) + ); + defparam com_cmm_u_cmm_cfgspace_N_85892_i.INIT = 16'hFFF8; + LUT4_L com_cmm_u_cmm_cfgspace_N_85892_i ( + .I0(com_cmm_u_cmm_cfgspace_N_58586_1), + .I1(cfg_rd_en_n), + .I2(com_cmm_u_cmm_cfgspace_cfg2ulm_valid), + .I3(com_cmm_state[6]), + .LO(com_cmm_u_cmm_cfgspace_N_85892_i_5799) + ); + defparam com_cmm_u_cmm_cfgspace_x3gio_dsts_x_dsts_9_iv_0_0_0_0_3_.INIT = 16'hFF4C; + LUT4_L com_cmm_u_cmm_cfgspace_x3gio_dsts_x_dsts_9_iv_0_0_0_0_3_ ( + .I0(com_cmm_u_cmm_cfgspace_N_58304_1), + .I1(NlwRenamedSig_OI_cfg_dstatus_3_), + .I2(com_cmm_cfg_wr_data_11_), + .I3(com_cmm_u_cmm_cfgspace_set_unsupportedreq_5768), + .LO(com_cmm_u_cmm_cfgspace_N_9949_i) + ); + defparam com_cmm_u_cmm_cfgspace_x3gio_dsts_x_dsts_13_iv_0_0_0_0_2_.INIT = 16'hFF4C; + LUT4_L com_cmm_u_cmm_cfgspace_x3gio_dsts_x_dsts_13_iv_0_0_0_0_2_ ( + .I0(com_cmm_u_cmm_cfgspace_N_58304_1), + .I1(NlwRenamedSig_OI_cfg_dstatus_2_), + .I2(com_cmm_cfg_wr_data_10_), + .I3(com_cmm_u_cmm_cfgspace_set_detectedfatal_5770), + .LO(com_cmm_u_cmm_cfgspace_N_9948_i) + ); + defparam com_cmm_u_cmm_cfgspace_x3gio_dsts_x_dsts_17_iv_0_0_0_0_1_.INIT = 16'hFF4C; + LUT4_L com_cmm_u_cmm_cfgspace_x3gio_dsts_x_dsts_17_iv_0_0_0_0_1_ ( + .I0(com_cmm_u_cmm_cfgspace_N_58304_1), + .I1(NlwRenamedSig_OI_cfg_dstatus_1_), + .I2(com_cmm_cfg_wr_data_9_), + .I3(com_cmm_u_cmm_cfgspace_set_detectednonfatal_5769), + .LO(com_cmm_u_cmm_cfgspace_N_9947_i) + ); + defparam com_cmm_u_cmm_cfgspace_x3gio_dsts_x_dsts_21_iv_0_0_0_0_0_.INIT = 16'hFF4C; + LUT4_L com_cmm_u_cmm_cfgspace_x3gio_dsts_x_dsts_21_iv_0_0_0_0_0_ ( + .I0(com_cmm_u_cmm_cfgspace_N_58304_1), + .I1(NlwRenamedSig_OI_cfg_dstatus_0_), + .I2(com_cmm_cfg_wr_data_8_), + .I3(com_cmm_u_cmm_cfgspace_set_detectedcorrectable_5760), + .LO(com_cmm_u_cmm_cfgspace_N_9946_i) + ); + defparam com_cmm_u_cmm_cfgspace_x3gio_status_status_6_iv_0_0_0_0_15_.INIT = 16'hFF4C; + LUT4_L com_cmm_u_cmm_cfgspace_x3gio_status_status_6_iv_0_0_0_0_15_ ( + .I0(com_cmm_u_cmm_cfgspace_N_58308_1), + .I1(NlwRenamedSig_OI_cfg_status_15_), + .I2(com_cmm_cfg_wr_data_7_), + .I3(com_cmm_u_cmm_cfgspace_set_detectedparityerror_5767), + .LO(com_cmm_u_cmm_cfgspace_N_9941_i) + ); + defparam com_cmm_u_cmm_cfgspace_x3gio_bar1_N_85868_i.INIT = 8'h8F; + LUT3_L com_cmm_u_cmm_cfgspace_x3gio_bar1_N_85868_i ( + .I0(com_cmm_u_cmm_cfgspace_N_57880_1), + .I1(com_cmm_bar1_reg[3]), + .I2(com_cmm_u_cmm_cfgspace_bar1_reg_8_1_0_0_0[3]), + .LO(com_cmm_u_cmm_cfgspace_N_85868_i) + ); + defparam com_cmm_u_cmm_cfgspace_x3gio_bar1_N_85867_i.INIT = 8'h8F; + LUT3_L com_cmm_u_cmm_cfgspace_x3gio_bar1_N_85867_i ( + .I0(com_cmm_u_cmm_cfgspace_N_57880_1), + .I1(com_cmm_bar1_reg[2]), + .I2(com_cmm_u_cmm_cfgspace_bar1_reg_8_1_0_0_0_0[2]), + .LO(com_cmm_u_cmm_cfgspace_N_85867_i) + ); + defparam com_cmm_u_cmm_cfgspace_x3gio_bar2_N_85872_i.INIT = 8'h8F; + LUT3_L com_cmm_u_cmm_cfgspace_x3gio_bar2_N_85872_i ( + .I0(com_cmm_u_cmm_cfgspace_N_57892_1), + .I1(com_cmm_bar2_reg[3]), + .I2(com_cmm_u_cmm_cfgspace_bar2_reg_8_1_0_0_0_0[3]), + .LO(com_cmm_u_cmm_cfgspace_N_85872_i) + ); + defparam com_cmm_u_cmm_cfgspace_x3gio_bar2_N_85871_i.INIT = 8'h8F; + LUT3_L com_cmm_u_cmm_cfgspace_x3gio_bar2_N_85871_i ( + .I0(com_cmm_u_cmm_cfgspace_N_57892_1), + .I1(com_cmm_bar2_reg[2]), + .I2(com_cmm_u_cmm_cfgspace_bar2_reg_8_1_0_0_0_0[2]), + .LO(com_cmm_u_cmm_cfgspace_N_85871_i) + ); + defparam com_cmm_u_cmm_cfgspace_x3gio_bar2_N_85870_i.INIT = 8'h8F; + LUT3_L com_cmm_u_cmm_cfgspace_x3gio_bar2_N_85870_i ( + .I0(com_cmm_u_cmm_cfgspace_N_57892_1), + .I1(com_cmm_bar2_reg[1]), + .I2(com_cmm_u_cmm_cfgspace_bar2_reg_8_1_0_0_0_0[1]), + .LO(com_cmm_u_cmm_cfgspace_N_85870_i) + ); + defparam com_cmm_u_cmm_cfgspace_x3gio_bar2_N_85869_i.INIT = 8'h8F; + LUT3_L com_cmm_u_cmm_cfgspace_x3gio_bar2_N_85869_i ( + .I0(com_cmm_u_cmm_cfgspace_N_57892_1), + .I1(com_cmm_bar2_reg[0]), + .I2(com_cmm_u_cmm_cfgspace_bar2_reg_8_1_0_0_0_0[0]), + .LO(com_cmm_u_cmm_cfgspace_N_85869_i) + ); + defparam com_cmm_u_cmm_cfgspace_x3gio_bar3_N_85876_i.INIT = 16'h40FF; + LUT4_L com_cmm_u_cmm_cfgspace_x3gio_bar3_N_85876_i ( + .I0(com_cmm_u_cmm_cfgspace_N_55974_i), + .I1(com_cmm_u_cmm_cfgspace_N_56069_i), + .I2(com_cmm_bar3_reg[3]), + .I3(com_cmm_u_cmm_cfgspace_bar3_reg_8_1_0_0_0_0[3]), + .LO(com_cmm_u_cmm_cfgspace_N_85876_i) + ); + defparam com_cmm_u_cmm_cfgspace_x3gio_bar3_N_85875_i.INIT = 16'h40FF; + LUT4_L com_cmm_u_cmm_cfgspace_x3gio_bar3_N_85875_i ( + .I0(com_cmm_u_cmm_cfgspace_N_55974_i), + .I1(com_cmm_u_cmm_cfgspace_N_56069_i), + .I2(com_cmm_bar3_reg[2]), + .I3(com_cmm_u_cmm_cfgspace_bar3_reg_8_1_0_0_0_0[2]), + .LO(com_cmm_u_cmm_cfgspace_N_85875_i) + ); + defparam com_cmm_u_cmm_cfgspace_x3gio_bar3_N_85874_i.INIT = 16'h40FF; + LUT4_L com_cmm_u_cmm_cfgspace_x3gio_bar3_N_85874_i ( + .I0(com_cmm_u_cmm_cfgspace_N_55974_i), + .I1(com_cmm_u_cmm_cfgspace_N_56069_i), + .I2(com_cmm_bar3_reg[1]), + .I3(com_cmm_u_cmm_cfgspace_bar3_reg_8_1_0_0_0_0[1]), + .LO(com_cmm_u_cmm_cfgspace_N_85874_i) + ); + defparam com_cmm_u_cmm_cfgspace_x3gio_bar3_N_85873_i.INIT = 16'h40FF; + LUT4_L com_cmm_u_cmm_cfgspace_x3gio_bar3_N_85873_i ( + .I0(com_cmm_u_cmm_cfgspace_N_55974_i), + .I1(com_cmm_u_cmm_cfgspace_N_56069_i), + .I2(com_cmm_bar3_reg[0]), + .I3(com_cmm_u_cmm_cfgspace_bar3_reg_8_1_0_0_0_0[0]), + .LO(com_cmm_u_cmm_cfgspace_N_85873_i) + ); + defparam com_cmm_u_cmm_cfgspace_x3gio_bar4_N_85880_i.INIT = 8'h8F; + LUT3_L com_cmm_u_cmm_cfgspace_x3gio_bar4_N_85880_i ( + .I0(com_cmm_u_cmm_cfgspace_N_57916_1), + .I1(com_cmm_bar4_reg[3]), + .I2(com_cmm_u_cmm_cfgspace_bar4_reg_8_1_0_0_0_0[3]), + .LO(com_cmm_u_cmm_cfgspace_N_85880_i) + ); + defparam com_cmm_u_cmm_cfgspace_x3gio_bar4_N_85879_i.INIT = 8'h8F; + LUT3_L com_cmm_u_cmm_cfgspace_x3gio_bar4_N_85879_i ( + .I0(com_cmm_u_cmm_cfgspace_N_57916_1), + .I1(com_cmm_bar4_reg[2]), + .I2(com_cmm_u_cmm_cfgspace_bar4_reg_8_1_0_0_0_0[2]), + .LO(com_cmm_u_cmm_cfgspace_N_85879_i) + ); + defparam com_cmm_u_cmm_cfgspace_x3gio_bar4_N_85878_i.INIT = 8'h8F; + LUT3_L com_cmm_u_cmm_cfgspace_x3gio_bar4_N_85878_i ( + .I0(com_cmm_u_cmm_cfgspace_N_57916_1), + .I1(com_cmm_bar4_reg[1]), + .I2(com_cmm_u_cmm_cfgspace_bar4_reg_8_1_0_0_0_0[1]), + .LO(com_cmm_u_cmm_cfgspace_N_85878_i) + ); + defparam com_cmm_u_cmm_cfgspace_x3gio_bar4_N_85877_i.INIT = 8'h8F; + LUT3_L com_cmm_u_cmm_cfgspace_x3gio_bar4_N_85877_i ( + .I0(com_cmm_u_cmm_cfgspace_N_57916_1), + .I1(com_cmm_bar4_reg[0]), + .I2(com_cmm_u_cmm_cfgspace_bar4_reg_8_1_0_0_0_0[0]), + .LO(com_cmm_u_cmm_cfgspace_N_85877_i) + ); + defparam com_cmm_u_cmm_cfgspace_x3gio_bar5_N_85884_i.INIT = 16'h40FF; + LUT4_L com_cmm_u_cmm_cfgspace_x3gio_bar5_N_85884_i ( + .I0(com_cmm_u_cmm_cfgspace_N_55971_i), + .I1(com_cmm_u_cmm_cfgspace_N_56067_i), + .I2(com_cmm_bar5_reg[3]), + .I3(com_cmm_u_cmm_cfgspace_bar5_reg_8_1_0_0_0_0[3]), + .LO(com_cmm_u_cmm_cfgspace_N_85884_i) + ); + defparam com_cmm_u_cmm_cfgspace_x3gio_bar5_N_85883_i.INIT = 16'h40FF; + LUT4_L com_cmm_u_cmm_cfgspace_x3gio_bar5_N_85883_i ( + .I0(com_cmm_u_cmm_cfgspace_N_55971_i), + .I1(com_cmm_u_cmm_cfgspace_N_56067_i), + .I2(com_cmm_bar5_reg[2]), + .I3(com_cmm_u_cmm_cfgspace_bar5_reg_8_1_0_0_0_0[2]), + .LO(com_cmm_u_cmm_cfgspace_N_85883_i) + ); + defparam com_cmm_u_cmm_cfgspace_x3gio_bar5_N_85882_i.INIT = 16'h40FF; + LUT4_L com_cmm_u_cmm_cfgspace_x3gio_bar5_N_85882_i ( + .I0(com_cmm_u_cmm_cfgspace_N_55971_i), + .I1(com_cmm_u_cmm_cfgspace_N_56067_i), + .I2(com_cmm_bar5_reg[1]), + .I3(com_cmm_u_cmm_cfgspace_bar5_reg_8_1_0_0_0_0[1]), + .LO(com_cmm_u_cmm_cfgspace_N_85882_i) + ); + defparam com_cmm_u_cmm_cfgspace_x3gio_bar5_N_85881_i.INIT = 16'h40FF; + LUT4_L com_cmm_u_cmm_cfgspace_x3gio_bar5_N_85881_i ( + .I0(com_cmm_u_cmm_cfgspace_N_55971_i), + .I1(com_cmm_u_cmm_cfgspace_N_56067_i), + .I2(com_cmm_bar5_reg[0]), + .I3(com_cmm_u_cmm_cfgspace_bar5_reg_8_1_0_0_0_0[0]), + .LO(com_cmm_u_cmm_cfgspace_N_85881_i) + ); + defparam com_cmm_u_cmm_cfgspace_x_dcmd_18_i_i_i_0_6_.INIT = 16'h00E4; + LUT4_L com_cmm_u_cmm_cfgspace_x_dcmd_18_i_i_i_0_6_ ( + .I0(com_cmm_u_cmm_cfgspace_x_dcmd_18_i_0_0_o3[1]), + .I1(NlwRenamedSig_OI_cfg_dcommand[6]), + .I2(com_cmm_cfg_wr_data_30_), + .I3(com_cmm_rst_351), + .LO(com_cmm_u_cmm_cfgspace_N_40410_i) + ); + defparam com_cmm_u_cmm_cfgspace_x_dcmd_18_i_i_i_0_5_.INIT = 16'h00E4; + LUT4_L com_cmm_u_cmm_cfgspace_x_dcmd_18_i_i_i_0_5_ ( + .I0(com_cmm_u_cmm_cfgspace_x_dcmd_18_i_0_0_o3[1]), + .I1(NlwRenamedSig_OI_cfg_dcommand[5]), + .I2(com_cmm_cfg_wr_data_29_), + .I3(com_cmm_rst_351), + .LO(com_cmm_u_cmm_cfgspace_N_40408_i) + ); + defparam com_cmm_u_cmm_cfgspace_N_86401_i.INIT = 16'hFFE4; + LUT4_L com_cmm_u_cmm_cfgspace_N_86401_i ( + .I0(com_cmm_u_cmm_cfgspace_x_dcmd_18_i_0_0_o3[1]), + .I1(NlwRenamedSig_OI_cfg_dcommand[4]), + .I2(com_cmm_cfg_wr_data_28_), + .I3(com_cmm_rst_351), + .LO(com_cmm_u_cmm_cfgspace_N_86401_i_5802) + ); + defparam com_cmm_u_cmm_cfgspace_x_dcmd_18_i_0_3_.INIT = 16'h00E4; + LUT4_L com_cmm_u_cmm_cfgspace_x_dcmd_18_i_0_3_ ( + .I0(com_cmm_u_cmm_cfgspace_x_dcmd_18_i_0_0_o3[1]), + .I1(NlwRenamedSig_OI_cfg_dcommand[3]), + .I2(com_cmm_cfg_wr_data[27]), + .I3(com_cmm_rst_351), + .LO(com_cmm_u_cmm_cfgspace_N_40001_i) + ); + defparam com_cmm_u_cmm_cfgspace_x_dcmd_18_i_0_0_2_.INIT = 16'h00E4; + LUT4_L com_cmm_u_cmm_cfgspace_x_dcmd_18_i_0_0_2_ ( + .I0(com_cmm_u_cmm_cfgspace_x_dcmd_18_i_0_0_o3[1]), + .I1(NlwRenamedSig_OI_cfg_dcommand[2]), + .I2(com_cmm_cfg_wr_data[26]), + .I3(com_cmm_rst_351), + .LO(com_cmm_u_cmm_cfgspace_N_17888_i) + ); + defparam com_cmm_u_cmm_cfgspace_x_dcmd_18_i_0_0_1_.INIT = 16'h00E4; + LUT4_L com_cmm_u_cmm_cfgspace_x_dcmd_18_i_0_0_1_ ( + .I0(com_cmm_u_cmm_cfgspace_x_dcmd_18_i_0_0_o3[1]), + .I1(NlwRenamedSig_OI_cfg_dcommand[1]), + .I2(com_cmm_cfg_wr_data[25]), + .I3(com_cmm_rst_351), + .LO(com_cmm_u_cmm_cfgspace_N_17886_i) + ); + defparam com_cmm_u_cmm_cfgspace_x_dcmd_18_i_0_0_0_0_.INIT = 16'h00E4; + LUT4_L com_cmm_u_cmm_cfgspace_x_dcmd_18_i_0_0_0_0_ ( + .I0(com_cmm_u_cmm_cfgspace_x_dcmd_18_i_0_0_o3[1]), + .I1(NlwRenamedSig_OI_cfg_dcommand[0]), + .I2(com_cmm_cfg_wr_data[24]), + .I3(com_cmm_rst_351), + .LO(com_cmm_u_cmm_cfgspace_N_17884_i) + ); + defparam com_cmm_u_cmm_cfgspace_x_dcmd_18_i_0_0_14_.INIT = 16'h00E4; + LUT4_L com_cmm_u_cmm_cfgspace_x_dcmd_18_i_0_0_14_ ( + .I0(com_cmm_u_cmm_cfgspace_N_55990_i), + .I1(NlwRenamedSig_OI_cfg_dcommand[14]), + .I2(com_cmm_cfg_wr_data_22_), + .I3(com_cmm_rst_351), + .LO(com_cmm_u_cmm_cfgspace_N_35664_i) + ); + defparam com_cmm_u_cmm_cfgspace_N_86412_i.INIT = 16'hFFE4; + LUT4_L com_cmm_u_cmm_cfgspace_N_86412_i ( + .I0(com_cmm_u_cmm_cfgspace_N_55990_i), + .I1(NlwRenamedSig_OI_cfg_dcommand[13]), + .I2(com_cmm_cfg_wr_data_21_), + .I3(com_cmm_rst_351), + .LO(com_cmm_u_cmm_cfgspace_N_86412_i_5803) + ); + defparam com_cmm_u_cmm_cfgspace_x_dcmd_18_1_i_0_0_12_.INIT = 16'h00E4; + LUT4_L com_cmm_u_cmm_cfgspace_x_dcmd_18_1_i_0_0_12_ ( + .I0(com_cmm_u_cmm_cfgspace_N_55990_i), + .I1(NlwRenamedSig_OI_cfg_dcommand[12]), + .I2(com_cmm_cfg_wr_data_20_), + .I3(com_cmm_rst_351), + .LO(com_cmm_u_cmm_cfgspace_N_35662_i) + ); + defparam com_cmm_u_cmm_cfgspace_N_86410_i.INIT = 16'hFFE4; + LUT4_L com_cmm_u_cmm_cfgspace_N_86410_i ( + .I0(com_cmm_u_cmm_cfgspace_N_55990_i), + .I1(NlwRenamedSig_OI_cfg_dcommand[11]), + .I2(com_cmm_cfg_wr_data_19_), + .I3(com_cmm_rst_351), + .LO(com_cmm_u_cmm_cfgspace_N_86410_i_5804) + ); + defparam com_cmm_u_cmm_cfgspace_x_dcmd_18_i_0_0_9_.INIT = 16'h00E4; + LUT4_L com_cmm_u_cmm_cfgspace_x_dcmd_18_i_0_0_9_ ( + .I0(com_cmm_u_cmm_cfgspace_N_55990_i), + .I1(NlwRenamedSig_OI_cfg_dcommand[9]), + .I2(com_cmm_cfg_wr_data_17_), + .I3(com_cmm_rst_351), + .LO(com_cmm_u_cmm_cfgspace_N_35660_i) + ); + defparam com_cmm_u_cmm_cfgspace_x_dcmd_18_1_i_0_8_.INIT = 16'h0C04; + LUT4_L com_cmm_u_cmm_cfgspace_x_dcmd_18_1_i_0_8_ ( + .I0(com_cmm_u_cmm_cfgspace_N_55990_i), + .I1(com_cmm_u_cmm_cfgspace_N_57085), + .I2(com_cmm_rst_351), + .I3(com_cmm_u_cmm_cfgspace_x_dcap[5]), + .LO(com_cmm_u_cmm_cfgspace_N_40003_i) + ); + defparam com_cmm_u_cmm_cfgspace_x_dcmd_18_i_i_i_0_7_.INIT = 16'h00E4; + LUT4_L com_cmm_u_cmm_cfgspace_x_dcmd_18_i_i_i_0_7_ ( + .I0(com_cmm_u_cmm_cfgspace_x_dcmd_18_i_0_0_o3[1]), + .I1(NlwRenamedSig_OI_cfg_dcommand[7]), + .I2(com_cmm_cfg_wr_data_31_), + .I3(com_cmm_rst_351), + .LO(com_cmm_u_cmm_cfgspace_N_40412_i) + ); + defparam com_cmm_u_cmm_cfgspace_cfg2tlm_rddata_0_a2_0_a2_0_a2_0_a2_31_.INIT = 4'h8; + LUT2_L com_cmm_u_cmm_cfgspace_cfg2tlm_rddata_0_a2_0_a2_0_a2_0_a2_31_ ( + .I0(com_cmm_u_cmm_cfgspace_decoder_read_data[31]), + .I1(com_cmm_state[6]), + .LO(com_cmm_cfg2tlm_rddata[31]) + ); + defparam com_cmm_u_cmm_cfgspace_cfg2tlm_rddata_0_a2_0_a2_0_a2_0_a2_30_.INIT = 4'h8; + LUT2_L com_cmm_u_cmm_cfgspace_cfg2tlm_rddata_0_a2_0_a2_0_a2_0_a2_30_ ( + .I0(com_cmm_u_cmm_cfgspace_decoder_read_data[30]), + .I1(com_cmm_state[6]), + .LO(com_cmm_cfg2tlm_rddata[30]) + ); + defparam com_cmm_u_cmm_cfgspace_cfg2tlm_rddata_0_a2_0_a2_0_a2_0_a2_29_.INIT = 4'h8; + LUT2_L com_cmm_u_cmm_cfgspace_cfg2tlm_rddata_0_a2_0_a2_0_a2_0_a2_29_ ( + .I0(com_cmm_u_cmm_cfgspace_decoder_read_data[29]), + .I1(com_cmm_state[6]), + .LO(com_cmm_cfg2tlm_rddata[29]) + ); + defparam com_cmm_u_cmm_cfgspace_cfg2tlm_rddata_0_a2_0_a2_0_a2_0_a2_28_.INIT = 4'h8; + LUT2_L com_cmm_u_cmm_cfgspace_cfg2tlm_rddata_0_a2_0_a2_0_a2_0_a2_28_ ( + .I0(com_cmm_u_cmm_cfgspace_decoder_read_data[28]), + .I1(com_cmm_state[6]), + .LO(com_cmm_cfg2tlm_rddata[28]) + ); + defparam com_cmm_u_cmm_cfgspace_cfg2tlm_rddata_0_a2_0_a2_0_a2_0_a2_27_.INIT = 4'h8; + LUT2_L com_cmm_u_cmm_cfgspace_cfg2tlm_rddata_0_a2_0_a2_0_a2_0_a2_27_ ( + .I0(com_cmm_u_cmm_cfgspace_decoder_read_data[27]), + .I1(com_cmm_state[6]), + .LO(com_cmm_cfg2tlm_rddata[27]) + ); + defparam com_cmm_u_cmm_cfgspace_cfg2tlm_rddata_0_a2_0_a2_0_a2_0_a2_26_.INIT = 4'h8; + LUT2_L com_cmm_u_cmm_cfgspace_cfg2tlm_rddata_0_a2_0_a2_0_a2_0_a2_26_ ( + .I0(com_cmm_u_cmm_cfgspace_decoder_read_data[26]), + .I1(com_cmm_state[6]), + .LO(com_cmm_cfg2tlm_rddata[26]) + ); + defparam com_cmm_u_cmm_cfgspace_cfg2tlm_rddata_0_a2_0_a2_0_a2_0_a2_25_.INIT = 4'h8; + LUT2_L com_cmm_u_cmm_cfgspace_cfg2tlm_rddata_0_a2_0_a2_0_a2_0_a2_25_ ( + .I0(com_cmm_u_cmm_cfgspace_decoder_read_data[25]), + .I1(com_cmm_state[6]), + .LO(com_cmm_cfg2tlm_rddata[25]) + ); + defparam com_cmm_u_cmm_cfgspace_cfg2tlm_rddata_0_a2_0_a2_0_a2_0_a2_24_.INIT = 4'h8; + LUT2_L com_cmm_u_cmm_cfgspace_cfg2tlm_rddata_0_a2_0_a2_0_a2_0_a2_24_ ( + .I0(com_cmm_u_cmm_cfgspace_decoder_read_data[24]), + .I1(com_cmm_state[6]), + .LO(com_cmm_cfg2tlm_rddata[24]) + ); + defparam com_cmm_u_cmm_cfgspace_cfg2tlm_rddata_0_a2_0_a2_0_a2_0_a2_23_.INIT = 4'h8; + LUT2_L com_cmm_u_cmm_cfgspace_cfg2tlm_rddata_0_a2_0_a2_0_a2_0_a2_23_ ( + .I0(com_cmm_u_cmm_cfgspace_decoder_read_data[23]), + .I1(com_cmm_state[6]), + .LO(com_cmm_cfg2tlm_rddata[23]) + ); + defparam com_cmm_u_cmm_cfgspace_cfg2tlm_rddata_0_a2_0_a2_0_a2_0_a2_22_.INIT = 4'h8; + LUT2_L com_cmm_u_cmm_cfgspace_cfg2tlm_rddata_0_a2_0_a2_0_a2_0_a2_22_ ( + .I0(com_cmm_u_cmm_cfgspace_decoder_read_data[22]), + .I1(com_cmm_state[6]), + .LO(com_cmm_cfg2tlm_rddata[22]) + ); + defparam com_cmm_u_cmm_cfgspace_cfg2tlm_rddata_0_a2_0_a2_0_a2_0_a2_21_.INIT = 4'h8; + LUT2_L com_cmm_u_cmm_cfgspace_cfg2tlm_rddata_0_a2_0_a2_0_a2_0_a2_21_ ( + .I0(com_cmm_u_cmm_cfgspace_decoder_read_data[21]), + .I1(com_cmm_state[6]), + .LO(com_cmm_cfg2tlm_rddata[21]) + ); + defparam com_cmm_u_cmm_cfgspace_cfg2tlm_rddata_0_a2_0_a2_0_a2_0_a2_20_.INIT = 4'h8; + LUT2_L com_cmm_u_cmm_cfgspace_cfg2tlm_rddata_0_a2_0_a2_0_a2_0_a2_20_ ( + .I0(com_cmm_u_cmm_cfgspace_decoder_read_data[20]), + .I1(com_cmm_state[6]), + .LO(com_cmm_cfg2tlm_rddata[20]) + ); + defparam com_cmm_u_cmm_cfgspace_cfg2tlm_rddata_0_a2_0_a2_0_a2_0_a2_19_.INIT = 4'h8; + LUT2_L com_cmm_u_cmm_cfgspace_cfg2tlm_rddata_0_a2_0_a2_0_a2_0_a2_19_ ( + .I0(com_cmm_u_cmm_cfgspace_decoder_read_data[19]), + .I1(com_cmm_state[6]), + .LO(com_cmm_cfg2tlm_rddata[19]) + ); + defparam com_cmm_u_cmm_cfgspace_cfg2tlm_rddata_0_a2_0_a2_0_a2_0_a2_18_.INIT = 4'h8; + LUT2_L com_cmm_u_cmm_cfgspace_cfg2tlm_rddata_0_a2_0_a2_0_a2_0_a2_18_ ( + .I0(com_cmm_u_cmm_cfgspace_decoder_read_data[18]), + .I1(com_cmm_state[6]), + .LO(com_cmm_cfg2tlm_rddata[18]) + ); + defparam com_cmm_u_cmm_cfgspace_cfg2tlm_rddata_0_a2_0_a2_0_a2_0_a2_17_.INIT = 4'h8; + LUT2_L com_cmm_u_cmm_cfgspace_cfg2tlm_rddata_0_a2_0_a2_0_a2_0_a2_17_ ( + .I0(com_cmm_u_cmm_cfgspace_decoder_read_data[17]), + .I1(com_cmm_state[6]), + .LO(com_cmm_cfg2tlm_rddata[17]) + ); + defparam com_cmm_u_cmm_cfgspace_cfg2tlm_rddata_0_a2_0_a2_0_a2_0_a2_16_.INIT = 4'h8; + LUT2_L com_cmm_u_cmm_cfgspace_cfg2tlm_rddata_0_a2_0_a2_0_a2_0_a2_16_ ( + .I0(com_cmm_u_cmm_cfgspace_decoder_read_data[16]), + .I1(com_cmm_state[6]), + .LO(com_cmm_cfg2tlm_rddata[16]) + ); + defparam com_cmm_u_cmm_cfgspace_cfg2tlm_rddata_0_a2_0_a2_0_a2_0_a2_15_.INIT = 4'h8; + LUT2_L com_cmm_u_cmm_cfgspace_cfg2tlm_rddata_0_a2_0_a2_0_a2_0_a2_15_ ( + .I0(com_cmm_u_cmm_cfgspace_decoder_read_data[15]), + .I1(com_cmm_state[6]), + .LO(com_cmm_cfg2tlm_rddata[15]) + ); + defparam com_cmm_u_cmm_cfgspace_cfg2tlm_rddata_0_a2_0_a2_0_a2_0_a2_14_.INIT = 4'h8; + LUT2_L com_cmm_u_cmm_cfgspace_cfg2tlm_rddata_0_a2_0_a2_0_a2_0_a2_14_ ( + .I0(com_cmm_u_cmm_cfgspace_decoder_read_data[14]), + .I1(com_cmm_state[6]), + .LO(com_cmm_cfg2tlm_rddata[14]) + ); + defparam com_cmm_u_cmm_cfgspace_cfg2tlm_rddata_0_a2_0_a2_0_a2_0_a2_13_.INIT = 4'h8; + LUT2_L com_cmm_u_cmm_cfgspace_cfg2tlm_rddata_0_a2_0_a2_0_a2_0_a2_13_ ( + .I0(com_cmm_u_cmm_cfgspace_decoder_read_data[13]), + .I1(com_cmm_state[6]), + .LO(com_cmm_cfg2tlm_rddata[13]) + ); + defparam com_cmm_u_cmm_cfgspace_cfg2tlm_rddata_0_a2_0_a2_0_a2_0_a2_12_.INIT = 4'h8; + LUT2_L com_cmm_u_cmm_cfgspace_cfg2tlm_rddata_0_a2_0_a2_0_a2_0_a2_12_ ( + .I0(com_cmm_u_cmm_cfgspace_decoder_read_data[12]), + .I1(com_cmm_state[6]), + .LO(com_cmm_cfg2tlm_rddata[12]) + ); + defparam com_cmm_u_cmm_cfgspace_cfg2tlm_rddata_0_a2_0_a2_0_a2_0_a2_11_.INIT = 4'h8; + LUT2_L com_cmm_u_cmm_cfgspace_cfg2tlm_rddata_0_a2_0_a2_0_a2_0_a2_11_ ( + .I0(com_cmm_u_cmm_cfgspace_decoder_read_data[11]), + .I1(com_cmm_state[6]), + .LO(com_cmm_cfg2tlm_rddata[11]) + ); + defparam com_cmm_u_cmm_cfgspace_cfg2tlm_rddata_0_a2_0_a2_0_a2_0_a2_10_.INIT = 4'h8; + LUT2_L com_cmm_u_cmm_cfgspace_cfg2tlm_rddata_0_a2_0_a2_0_a2_0_a2_10_ ( + .I0(com_cmm_u_cmm_cfgspace_decoder_read_data[10]), + .I1(com_cmm_state[6]), + .LO(com_cmm_cfg2tlm_rddata[10]) + ); + defparam com_cmm_u_cmm_cfgspace_cfg2tlm_rddata_0_a2_0_a2_0_a2_0_a2_9_.INIT = 4'h8; + LUT2_L com_cmm_u_cmm_cfgspace_cfg2tlm_rddata_0_a2_0_a2_0_a2_0_a2_9_ ( + .I0(com_cmm_u_cmm_cfgspace_decoder_read_data[9]), + .I1(com_cmm_state[6]), + .LO(com_cmm_cfg2tlm_rddata[9]) + ); + defparam com_cmm_u_cmm_cfgspace_cfg2tlm_rddata_0_a2_0_a2_0_a2_0_a2_8_.INIT = 4'h8; + LUT2_L com_cmm_u_cmm_cfgspace_cfg2tlm_rddata_0_a2_0_a2_0_a2_0_a2_8_ ( + .I0(com_cmm_u_cmm_cfgspace_decoder_read_data[8]), + .I1(com_cmm_state[6]), + .LO(com_cmm_cfg2tlm_rddata[8]) + ); + defparam com_cmm_u_cmm_cfgspace_cfg2tlm_rddata_0_a2_0_a2_0_a2_0_a2_7_.INIT = 4'h8; + LUT2_L com_cmm_u_cmm_cfgspace_cfg2tlm_rddata_0_a2_0_a2_0_a2_0_a2_7_ ( + .I0(com_cmm_u_cmm_cfgspace_decoder_read_data[7]), + .I1(com_cmm_state[6]), + .LO(com_cmm_cfg2tlm_rddata[7]) + ); + defparam com_cmm_u_cmm_cfgspace_cfg2tlm_rddata_0_a2_0_a2_0_a2_0_a2_6_.INIT = 4'h8; + LUT2_L com_cmm_u_cmm_cfgspace_cfg2tlm_rddata_0_a2_0_a2_0_a2_0_a2_6_ ( + .I0(com_cmm_u_cmm_cfgspace_decoder_read_data[6]), + .I1(com_cmm_state[6]), + .LO(com_cmm_cfg2tlm_rddata[6]) + ); + defparam com_cmm_u_cmm_cfgspace_cfg2tlm_rddata_0_a2_0_a2_0_a2_0_a2_5_.INIT = 4'h8; + LUT2_L com_cmm_u_cmm_cfgspace_cfg2tlm_rddata_0_a2_0_a2_0_a2_0_a2_5_ ( + .I0(com_cmm_u_cmm_cfgspace_decoder_read_data[5]), + .I1(com_cmm_state[6]), + .LO(com_cmm_cfg2tlm_rddata[5]) + ); + defparam com_cmm_u_cmm_cfgspace_cfg2tlm_rddata_0_a2_0_a2_0_a2_0_a2_4_.INIT = 4'h8; + LUT2_L com_cmm_u_cmm_cfgspace_cfg2tlm_rddata_0_a2_0_a2_0_a2_0_a2_4_ ( + .I0(com_cmm_u_cmm_cfgspace_decoder_read_data[4]), + .I1(com_cmm_state[6]), + .LO(com_cmm_cfg2tlm_rddata[4]) + ); + defparam com_cmm_u_cmm_cfgspace_cfg2tlm_rddata_0_a2_0_a2_0_a2_0_a2_3_.INIT = 4'h8; + LUT2_L com_cmm_u_cmm_cfgspace_cfg2tlm_rddata_0_a2_0_a2_0_a2_0_a2_3_ ( + .I0(com_cmm_u_cmm_cfgspace_decoder_read_data[3]), + .I1(com_cmm_state[6]), + .LO(com_cmm_cfg2tlm_rddata[3]) + ); + defparam com_cmm_u_cmm_cfgspace_cfg2tlm_rddata_0_a2_0_a2_0_a2_0_a2_2_.INIT = 4'h8; + LUT2_L com_cmm_u_cmm_cfgspace_cfg2tlm_rddata_0_a2_0_a2_0_a2_0_a2_2_ ( + .I0(com_cmm_u_cmm_cfgspace_decoder_read_data[2]), + .I1(com_cmm_state[6]), + .LO(com_cmm_cfg2tlm_rddata[2]) + ); + defparam com_cmm_u_cmm_cfgspace_cfg2tlm_rddata_0_a2_0_a2_0_a2_0_a2_1_.INIT = 4'h8; + LUT2_L com_cmm_u_cmm_cfgspace_cfg2tlm_rddata_0_a2_0_a2_0_a2_0_a2_1_ ( + .I0(com_cmm_u_cmm_cfgspace_decoder_read_data[1]), + .I1(com_cmm_state[6]), + .LO(com_cmm_cfg2tlm_rddata[1]) + ); + defparam com_cmm_u_cmm_cfgspace_cfg2tlm_rddata_0_a2_0_a2_0_a2_0_a2_0_.INIT = 4'h8; + LUT2_L com_cmm_u_cmm_cfgspace_cfg2tlm_rddata_0_a2_0_a2_0_a2_0_a2_0_ ( + .I0(com_cmm_u_cmm_cfgspace_decoder_read_data[0]), + .I1(com_cmm_state[6]), + .LO(com_cmm_cfg2tlm_rddata[0]) + ); + defparam com_cmm_u_cmm_cfgspace_N_86824_i.INIT = 16'hE444; + LUT4_L com_cmm_u_cmm_cfgspace_N_86824_i ( + .I0(com_cmm_u_cmm_cfgspace_N_55879_i), + .I1(cfg_dwaddr_6099[4]), + .I2(com_cmm_cfg_addr[4]), + .I3(com_cmm_state_0[1]), + .LO(com_cmm_u_cmm_cfgspace_N_86824_i_5756) + ); + defparam com_cmm_u_cmm_cfgspace_N_86243_i.INIT = 16'hE444; + LUT4_L com_cmm_u_cmm_cfgspace_N_86243_i ( + .I0(com_cmm_u_cmm_cfgspace_N_55879_i), + .I1(cfg_dwaddr_6099[3]), + .I2(com_cmm_cfg_addr[3]), + .I3(com_cmm_state_0[1]), + .LO(com_cmm_u_cmm_cfgspace_N_86243_i_5755) + ); + defparam com_cmm_u_cmm_cfgspace_N_86825_i.INIT = 8'hDC; + LUT3_L com_cmm_u_cmm_cfgspace_N_86825_i ( + .I0(com_cmm_u_cmm_cfgspace_N_55879_i), + .I1(com_cmm_u_cmm_cfgspace_N_57206), + .I2(cfg_dwaddr_6099[2]), + .LO(com_cmm_u_cmm_cfgspace_N_86825_i_5758) + ); + defparam com_cmm_u_cmm_cfgspace_N_86826_i.INIT = 16'hE444; + LUT4_L com_cmm_u_cmm_cfgspace_N_86826_i ( + .I0(com_cmm_u_cmm_cfgspace_N_55879_i), + .I1(cfg_dwaddr_6099[1]), + .I2(com_cmm_cfg_addr[1]), + .I3(com_cmm_state_0[1]), + .LO(com_cmm_u_cmm_cfgspace_N_86826_i_5692) + ); + defparam com_cmm_u_cmm_cfgspace_N_86827_i.INIT = 16'hE444; + LUT4_L com_cmm_u_cmm_cfgspace_N_86827_i ( + .I0(com_cmm_u_cmm_cfgspace_N_55879_i), + .I1(cfg_dwaddr_6099[0]), + .I2(com_cmm_cfg_addr[0]), + .I3(com_cmm_state_0[1]), + .LO(com_cmm_u_cmm_cfgspace_N_86827_i_5693) + ); + defparam com_cmm_u_cmm_cfgspace_x3gio_xrom_N_86265_i.INIT = 16'hD580; + LUT4_L com_cmm_u_cmm_cfgspace_x3gio_xrom_N_86265_i ( + .I0(com_cmm_u_cmm_cfgspace_N_55962_i), + .I1(cfg_cfg_6102[351]), + .I2(com_cmm_cfg_wr_data_7_), + .I3(com_cmm_xrom_reg_31_), + .LO(com_cmm_u_cmm_cfgspace_N_86265_i) + ); + defparam com_cmm_u_cmm_cfgspace_x3gio_xrom_N_86264_i.INIT = 16'hD580; + LUT4_L com_cmm_u_cmm_cfgspace_x3gio_xrom_N_86264_i ( + .I0(com_cmm_u_cmm_cfgspace_N_55962_i), + .I1(cfg_cfg_6102[350]), + .I2(com_cmm_cfg_wr_data_6_), + .I3(com_cmm_xrom_reg_30_), + .LO(com_cmm_u_cmm_cfgspace_N_86264_i) + ); + defparam com_cmm_u_cmm_cfgspace_x3gio_xrom_N_86263_i.INIT = 16'hD580; + LUT4_L com_cmm_u_cmm_cfgspace_x3gio_xrom_N_86263_i ( + .I0(com_cmm_u_cmm_cfgspace_N_55962_i), + .I1(cfg_cfg_6102[349]), + .I2(com_cmm_cfg_wr_data_5_), + .I3(com_cmm_xrom_reg_29_), + .LO(com_cmm_u_cmm_cfgspace_N_86263_i) + ); + defparam com_cmm_u_cmm_cfgspace_x3gio_xrom_N_86262_i.INIT = 16'hD580; + LUT4_L com_cmm_u_cmm_cfgspace_x3gio_xrom_N_86262_i ( + .I0(com_cmm_u_cmm_cfgspace_N_55962_i), + .I1(cfg_cfg_6102[348]), + .I2(com_cmm_cfg_wr_data_4_), + .I3(com_cmm_xrom_reg_28_), + .LO(com_cmm_u_cmm_cfgspace_N_86262_i) + ); + defparam com_cmm_u_cmm_cfgspace_x3gio_xrom_N_86261_i.INIT = 16'hD580; + LUT4_L com_cmm_u_cmm_cfgspace_x3gio_xrom_N_86261_i ( + .I0(com_cmm_u_cmm_cfgspace_N_55962_i), + .I1(cfg_cfg_6102[347]), + .I2(com_cmm_cfg_wr_data_3_), + .I3(com_cmm_xrom_reg_27_), + .LO(com_cmm_u_cmm_cfgspace_N_86261_i) + ); + defparam com_cmm_u_cmm_cfgspace_x3gio_xrom_N_86260_i.INIT = 16'hD580; + LUT4_L com_cmm_u_cmm_cfgspace_x3gio_xrom_N_86260_i ( + .I0(com_cmm_u_cmm_cfgspace_N_55962_i), + .I1(cfg_cfg_6102[346]), + .I2(com_cmm_cfg_wr_data_2_), + .I3(com_cmm_xrom_reg_26_), + .LO(com_cmm_u_cmm_cfgspace_N_86260_i) + ); + defparam com_cmm_u_cmm_cfgspace_x3gio_xrom_N_86259_i.INIT = 16'hD580; + LUT4_L com_cmm_u_cmm_cfgspace_x3gio_xrom_N_86259_i ( + .I0(com_cmm_u_cmm_cfgspace_N_55962_i), + .I1(cfg_cfg_6102[345]), + .I2(com_cmm_cfg_wr_data_1_), + .I3(com_cmm_xrom_reg_25_), + .LO(com_cmm_u_cmm_cfgspace_N_86259_i) + ); + defparam com_cmm_u_cmm_cfgspace_x3gio_xrom_N_86258_i.INIT = 16'hD580; + LUT4_L com_cmm_u_cmm_cfgspace_x3gio_xrom_N_86258_i ( + .I0(com_cmm_u_cmm_cfgspace_N_55962_i), + .I1(cfg_cfg_6102[344]), + .I2(com_cmm_cfg_wr_data_0_), + .I3(com_cmm_xrom_reg_24_), + .LO(com_cmm_u_cmm_cfgspace_N_86258_i) + ); + defparam com_cmm_u_cmm_cfgspace_x3gio_xrom_N_86257_i.INIT = 16'hD580; + LUT4_L com_cmm_u_cmm_cfgspace_x3gio_xrom_N_86257_i ( + .I0(com_cmm_u_cmm_cfgspace_N_55961_i), + .I1(cfg_cfg_6102[343]), + .I2(com_cmm_cfg_wr_data_15_), + .I3(com_cmm_xrom_reg_23_), + .LO(com_cmm_u_cmm_cfgspace_N_86257_i) + ); + defparam com_cmm_u_cmm_cfgspace_x3gio_xrom_N_86256_i.INIT = 16'hD580; + LUT4_L com_cmm_u_cmm_cfgspace_x3gio_xrom_N_86256_i ( + .I0(com_cmm_u_cmm_cfgspace_N_55961_i), + .I1(cfg_cfg_6102[342]), + .I2(com_cmm_cfg_wr_data_14_), + .I3(com_cmm_xrom_reg_22_), + .LO(com_cmm_u_cmm_cfgspace_N_86256_i) + ); + defparam com_cmm_u_cmm_cfgspace_x3gio_xrom_N_86255_i.INIT = 16'hD580; + LUT4_L com_cmm_u_cmm_cfgspace_x3gio_xrom_N_86255_i ( + .I0(com_cmm_u_cmm_cfgspace_N_55961_i), + .I1(cfg_cfg_6102[341]), + .I2(com_cmm_cfg_wr_data_13_), + .I3(com_cmm_xrom_reg_21_), + .LO(com_cmm_u_cmm_cfgspace_N_86255_i) + ); + defparam com_cmm_u_cmm_cfgspace_x3gio_xrom_N_86254_i.INIT = 16'hD580; + LUT4_L com_cmm_u_cmm_cfgspace_x3gio_xrom_N_86254_i ( + .I0(com_cmm_u_cmm_cfgspace_N_55961_i), + .I1(cfg_cfg_6102[340]), + .I2(com_cmm_cfg_wr_data_12_), + .I3(com_cmm_xrom_reg_20_), + .LO(com_cmm_u_cmm_cfgspace_N_86254_i) + ); + defparam com_cmm_u_cmm_cfgspace_x3gio_xrom_N_86253_i.INIT = 16'hD580; + LUT4_L com_cmm_u_cmm_cfgspace_x3gio_xrom_N_86253_i ( + .I0(com_cmm_u_cmm_cfgspace_N_55961_i), + .I1(cfg_cfg_6102[339]), + .I2(com_cmm_cfg_wr_data_11_), + .I3(com_cmm_xrom_reg_19_), + .LO(com_cmm_u_cmm_cfgspace_N_86253_i) + ); + defparam com_cmm_u_cmm_cfgspace_x3gio_xrom_N_86252_i.INIT = 16'hD580; + LUT4_L com_cmm_u_cmm_cfgspace_x3gio_xrom_N_86252_i ( + .I0(com_cmm_u_cmm_cfgspace_N_55961_i), + .I1(cfg_cfg_6102[338]), + .I2(com_cmm_cfg_wr_data_10_), + .I3(com_cmm_xrom_reg_18_), + .LO(com_cmm_u_cmm_cfgspace_N_86252_i) + ); + defparam com_cmm_u_cmm_cfgspace_x3gio_xrom_N_86251_i.INIT = 16'hD580; + LUT4_L com_cmm_u_cmm_cfgspace_x3gio_xrom_N_86251_i ( + .I0(com_cmm_u_cmm_cfgspace_N_55961_i), + .I1(cfg_cfg_6102[337]), + .I2(com_cmm_cfg_wr_data_9_), + .I3(com_cmm_xrom_reg_17_), + .LO(com_cmm_u_cmm_cfgspace_N_86251_i) + ); + defparam com_cmm_u_cmm_cfgspace_x3gio_xrom_N_86250_i.INIT = 16'hD580; + LUT4_L com_cmm_u_cmm_cfgspace_x3gio_xrom_N_86250_i ( + .I0(com_cmm_u_cmm_cfgspace_N_55961_i), + .I1(cfg_cfg_6102[336]), + .I2(com_cmm_cfg_wr_data_8_), + .I3(com_cmm_xrom_reg_16_), + .LO(com_cmm_u_cmm_cfgspace_N_86250_i) + ); + defparam com_cmm_u_cmm_cfgspace_x3gio_xrom_N_86249_i.INIT = 16'hD580; + LUT4_L com_cmm_u_cmm_cfgspace_x3gio_xrom_N_86249_i ( + .I0(com_cmm_u_cmm_cfgspace_N_56033_i), + .I1(cfg_cfg_6102[335]), + .I2(com_cmm_cfg_wr_data_23_), + .I3(com_cmm_xrom_reg_15_), + .LO(com_cmm_u_cmm_cfgspace_N_86249_i) + ); + defparam com_cmm_u_cmm_cfgspace_x3gio_xrom_N_86248_i.INIT = 16'hD580; + LUT4_L com_cmm_u_cmm_cfgspace_x3gio_xrom_N_86248_i ( + .I0(com_cmm_u_cmm_cfgspace_N_56033_i), + .I1(cfg_cfg_6102[334]), + .I2(com_cmm_cfg_wr_data_22_), + .I3(com_cmm_xrom_reg_14_), + .LO(com_cmm_u_cmm_cfgspace_N_86248_i) + ); + defparam com_cmm_u_cmm_cfgspace_x3gio_xrom_N_86247_i.INIT = 16'hD580; + LUT4_L com_cmm_u_cmm_cfgspace_x3gio_xrom_N_86247_i ( + .I0(com_cmm_u_cmm_cfgspace_N_56033_i), + .I1(cfg_cfg_6102[333]), + .I2(com_cmm_cfg_wr_data_21_), + .I3(com_cmm_xrom_reg_13_), + .LO(com_cmm_u_cmm_cfgspace_N_86247_i) + ); + defparam com_cmm_u_cmm_cfgspace_x3gio_xrom_N_86246_i.INIT = 16'hD580; + LUT4_L com_cmm_u_cmm_cfgspace_x3gio_xrom_N_86246_i ( + .I0(com_cmm_u_cmm_cfgspace_N_56033_i), + .I1(cfg_cfg_6102[332]), + .I2(com_cmm_cfg_wr_data_20_), + .I3(com_cmm_xrom_reg_12_), + .LO(com_cmm_u_cmm_cfgspace_N_86246_i) + ); + defparam com_cmm_u_cmm_cfgspace_x3gio_xrom_N_86245_i.INIT = 16'hD580; + LUT4_L com_cmm_u_cmm_cfgspace_x3gio_xrom_N_86245_i ( + .I0(com_cmm_u_cmm_cfgspace_N_56033_i), + .I1(cfg_cfg_6102[331]), + .I2(com_cmm_cfg_wr_data_19_), + .I3(com_cmm_xrom_reg_11_), + .LO(com_cmm_u_cmm_cfgspace_N_86245_i) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_00_i_0_0_0_31_.INIT = 16'h5010; + LUT4_L com_cmm_u_cmm_cfgspace_low_addr_00_i_0_0_0_31_ ( + .I0(com_cmm_u_cmm_cfgspace_N_59010), + .I1(com_cmm_u_cmm_cfgspace_N_61336), + .I2(com_cmm_u_cmm_cfgspace_low_addr_00_i_0_0_0_31_39355_5694), + .I3(com_cmm_msi_haddr[31]), + .LO(com_cmm_u_cmm_cfgspace_N_25331_i) + ); + defparam com_cmm_u_cmm_cfgspace_N_85969_i.INIT = 16'h8FFF; + LUT4_L com_cmm_u_cmm_cfgspace_N_85969_i ( + .I0(com_cmm_u_cmm_cfgspace_N_61350), + .I1(com_cmm_bar4_reg[29]), + .I2(com_cmm_u_cmm_cfgspace_low_addr_00_i_i_0_0_0[29]), + .I3(com_cmm_u_cmm_cfgspace_low_addr_00_i_i_0_0_3[29]), + .LO(com_cmm_u_cmm_cfgspace_N_85969_i_5695) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_00_i_0_0_0_28_.INIT = 16'h5010; + LUT4_L com_cmm_u_cmm_cfgspace_low_addr_00_i_0_0_0_28_ ( + .I0(com_cmm_u_cmm_cfgspace_N_59004), + .I1(com_cmm_u_cmm_cfgspace_N_61336), + .I2(com_cmm_u_cmm_cfgspace_low_addr_00_i_0_0_0_28_39360_5696), + .I3(com_cmm_msi_haddr[28]), + .LO(com_cmm_u_cmm_cfgspace_N_25327_i) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_00_i_0_0_0_27_.INIT = 16'h5010; + LUT4_L com_cmm_u_cmm_cfgspace_low_addr_00_i_0_0_0_27_ ( + .I0(com_cmm_u_cmm_cfgspace_N_58666), + .I1(com_cmm_u_cmm_cfgspace_N_61336), + .I2(com_cmm_u_cmm_cfgspace_low_addr_00_i_0_0_0_27_39365_5697), + .I3(com_cmm_msi_haddr[27]), + .LO(com_cmm_u_cmm_cfgspace_N_19325_i) + ); + defparam com_cmm_u_cmm_cfgspace_N_85939_i.INIT = 16'hBFFF; + LUT4_L com_cmm_u_cmm_cfgspace_N_85939_i ( + .I0(com_cmm_u_cmm_cfgspace_N_58005), + .I1(com_cmm_u_cmm_cfgspace_low_addr_00_0_0_0_21__5700), + .I2(com_cmm_u_cmm_cfgspace_low_addr_00_0_0_1_21__5699), + .I3(com_cmm_u_cmm_cfgspace_low_addr_00_0_0_2[21]), + .LO(com_cmm_u_cmm_cfgspace_N_85939_i_5698) + ); + defparam com_cmm_u_cmm_cfgspace_N_85978_i.INIT = 16'hBFFF; + LUT4_L com_cmm_u_cmm_cfgspace_N_85978_i ( + .I0(com_cmm_u_cmm_cfgspace_N_59581), + .I1(com_cmm_u_cmm_cfgspace_low_addr_00_i_i_0_0[19]), + .I2(com_cmm_u_cmm_cfgspace_low_addr_00_i_i_0_1[19]), + .I3(com_cmm_u_cmm_cfgspace_low_addr_00_i_i_0_2[19]), + .LO(com_cmm_u_cmm_cfgspace_N_85978_i_5701) + ); + defparam com_cmm_u_cmm_cfgspace_N_85977_i.INIT = 16'hBFFF; + LUT4_L com_cmm_u_cmm_cfgspace_N_85977_i ( + .I0(com_cmm_u_cmm_cfgspace_N_59574), + .I1(com_cmm_u_cmm_cfgspace_low_addr_00_i_i_0_0[18]), + .I2(com_cmm_u_cmm_cfgspace_low_addr_00_i_i_0_1[18]), + .I3(com_cmm_u_cmm_cfgspace_low_addr_00_i_i_0_2[18]), + .LO(com_cmm_u_cmm_cfgspace_N_85977_i_5702) + ); + defparam com_cmm_u_cmm_cfgspace_N_85976_i.INIT = 16'hBFFF; + LUT4_L com_cmm_u_cmm_cfgspace_N_85976_i ( + .I0(com_cmm_u_cmm_cfgspace_N_59567), + .I1(com_cmm_u_cmm_cfgspace_low_addr_00_i_i_0_0[17]), + .I2(com_cmm_u_cmm_cfgspace_low_addr_00_i_i_0_1[17]), + .I3(com_cmm_u_cmm_cfgspace_low_addr_00_i_i_0_2[17]), + .LO(com_cmm_u_cmm_cfgspace_N_85976_i_5703) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_00_i_0_0_0_16_.INIT = 16'h1000; + LUT4_L com_cmm_u_cmm_cfgspace_low_addr_00_i_0_0_0_16_ ( + .I0(com_cmm_u_cmm_cfgspace_N_58545), + .I1(com_cmm_u_cmm_cfgspace_N_58548), + .I2(com_cmm_u_cmm_cfgspace_low_addr_00_i_0_0_0_1_16__5705), + .I3(com_cmm_u_cmm_cfgspace_low_addr_00_i_0_0_0_2_16__5704), + .LO(com_cmm_u_cmm_cfgspace_N_17891_i) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_00_i_0_15_.INIT = 16'hC040; + LUT4_L com_cmm_u_cmm_cfgspace_low_addr_00_i_0_15_ ( + .I0(com_cmm_u_cmm_cfgspace_N_59538_1), + .I1(com_cmm_u_cmm_cfgspace_low_addr_00_i_0_15_39328_5707), + .I2(com_cmm_u_cmm_cfgspace_low_addr_00_i_0_15_39329_5706), + .I3(cfg_cfg_6102[15]), + .LO(com_cmm_u_cmm_cfgspace_N_40020_i) + ); + defparam com_cmm_u_cmm_cfgspace_N_85938_i.INIT = 16'h8FFF; + LUT4_L com_cmm_u_cmm_cfgspace_N_85938_i ( + .I0(com_cmm_u_cmm_cfgspace_N_61350), + .I1(com_cmm_bar4_reg[14]), + .I2(com_cmm_u_cmm_cfgspace_low_addr_00_0_0_0_1_14__5709), + .I3(com_cmm_u_cmm_cfgspace_low_addr_00_0_0_0_2[14]), + .LO(com_cmm_u_cmm_cfgspace_N_85938_i_5708) + ); + defparam com_cmm_u_cmm_cfgspace_N_85937_i.INIT = 8'h7F; + LUT3_L com_cmm_u_cmm_cfgspace_N_85937_i ( + .I0(com_cmm_u_cmm_cfgspace_low_addr_00_0_0_0_0_13__5712), + .I1(com_cmm_u_cmm_cfgspace_low_addr_00_0_0_0_1_13__5711), + .I2(com_cmm_u_cmm_cfgspace_low_addr_00_0_0_0_2[13]), + .LO(com_cmm_u_cmm_cfgspace_N_85937_i_5710) + ); + defparam com_cmm_u_cmm_cfgspace_N_85936_i.INIT = 8'h7F; + LUT3_L com_cmm_u_cmm_cfgspace_N_85936_i ( + .I0(com_cmm_u_cmm_cfgspace_low_addr_00_0_0_0_0_0[12]), + .I1(com_cmm_u_cmm_cfgspace_low_addr_00_0_0_0_0_1[12]), + .I2(com_cmm_u_cmm_cfgspace_low_addr_00_0_0_0_0_2[12]), + .LO(com_cmm_u_cmm_cfgspace_N_85936_i_5713) + ); + defparam com_cmm_u_cmm_cfgspace_N_85935_i.INIT = 16'h8FFF; + LUT4_L com_cmm_u_cmm_cfgspace_N_85935_i ( + .I0(com_cmm_u_cmm_cfgspace_N_61350), + .I1(com_cmm_bar4_reg[11]), + .I2(com_cmm_u_cmm_cfgspace_low_addr_00_0_0_0_0_1[11]), + .I3(com_cmm_u_cmm_cfgspace_low_addr_00_0_0_0_0_2[11]), + .LO(com_cmm_u_cmm_cfgspace_N_85935_i_5714) + ); + defparam com_cmm_u_cmm_cfgspace_N_85934_i.INIT = 16'h8FFF; + LUT4_L com_cmm_u_cmm_cfgspace_N_85934_i ( + .I0(com_cmm_u_cmm_cfgspace_N_61350), + .I1(com_cmm_bar4_reg[10]), + .I2(com_cmm_u_cmm_cfgspace_low_addr_00_0_0_0_0_10__5717), + .I3(com_cmm_u_cmm_cfgspace_low_addr_00_0_0_0_1_10__5716), + .LO(com_cmm_u_cmm_cfgspace_N_85934_i_5715) + ); + defparam com_cmm_u_cmm_cfgspace_N_85933_i.INIT = 16'h8FFF; + LUT4_L com_cmm_u_cmm_cfgspace_N_85933_i ( + .I0(com_cmm_u_cmm_cfgspace_N_61350), + .I1(com_cmm_bar4_reg[9]), + .I2(com_cmm_u_cmm_cfgspace_low_addr_00_0_0_0_0_9__5720), + .I3(com_cmm_u_cmm_cfgspace_low_addr_00_0_0_0_1_9__5719), + .LO(com_cmm_u_cmm_cfgspace_N_85933_i_5718) + ); + defparam com_cmm_u_cmm_cfgspace_N_85932_i.INIT = 16'h8FFF; + LUT4_L com_cmm_u_cmm_cfgspace_N_85932_i ( + .I0(com_cmm_u_cmm_cfgspace_N_61350), + .I1(com_cmm_bar4_reg[8]), + .I2(com_cmm_u_cmm_cfgspace_low_addr_00_0_0_0_8__5723), + .I3(com_cmm_u_cmm_cfgspace_low_addr_00_0_0_1_8__5722), + .LO(com_cmm_u_cmm_cfgspace_N_85932_i_5721) + ); + defparam com_cmm_u_cmm_cfgspace_N_85931_i.INIT = 16'h8FFF; + LUT4_L com_cmm_u_cmm_cfgspace_N_85931_i ( + .I0(com_cmm_u_cmm_cfgspace_N_61350), + .I1(com_cmm_bar4_reg[7]), + .I2(com_cmm_u_cmm_cfgspace_low_addr_00_0_0_0_7__5726), + .I3(com_cmm_u_cmm_cfgspace_low_addr_00_0_0_1_7__5725), + .LO(com_cmm_u_cmm_cfgspace_N_85931_i_5724) + ); + defparam com_cmm_u_cmm_cfgspace_N_85930_i.INIT = 16'h8FFF; + LUT4_L com_cmm_u_cmm_cfgspace_N_85930_i ( + .I0(com_cmm_u_cmm_cfgspace_N_61350), + .I1(com_cmm_bar4_reg[6]), + .I2(com_cmm_u_cmm_cfgspace_low_addr_00_0_0_0_6__5729), + .I3(com_cmm_u_cmm_cfgspace_low_addr_00_0_0_1_6__5728), + .LO(com_cmm_u_cmm_cfgspace_N_85930_i_5727) + ); + defparam com_cmm_u_cmm_cfgspace_N_85929_i.INIT = 16'h8FFF; + LUT4_L com_cmm_u_cmm_cfgspace_N_85929_i ( + .I0(com_cmm_u_cmm_cfgspace_N_61350), + .I1(com_cmm_bar4_reg[5]), + .I2(com_cmm_u_cmm_cfgspace_low_addr_00_0_0_0_5__5732), + .I3(com_cmm_u_cmm_cfgspace_low_addr_00_0_0_1_5__5731), + .LO(com_cmm_u_cmm_cfgspace_N_85929_i_5730) + ); + defparam com_cmm_u_cmm_cfgspace_N_85928_i.INIT = 16'h8FFF; + LUT4_L com_cmm_u_cmm_cfgspace_N_85928_i ( + .I0(com_cmm_u_cmm_cfgspace_N_61350), + .I1(com_cmm_bar4_reg[4]), + .I2(com_cmm_u_cmm_cfgspace_low_addr_00_0_0_0_0_4__5735), + .I3(com_cmm_u_cmm_cfgspace_low_addr_00_0_0_0_1_4__5734), + .LO(com_cmm_u_cmm_cfgspace_N_85928_i_5733) + ); + defparam com_cmm_u_cmm_cfgspace_N_85927_i.INIT = 16'h8FFF; + LUT4_L com_cmm_u_cmm_cfgspace_N_85927_i ( + .I0(com_cmm_u_cmm_cfgspace_N_61350), + .I1(com_cmm_bar4_reg[3]), + .I2(com_cmm_u_cmm_cfgspace_low_addr_00_0_0_0_3__5738), + .I3(com_cmm_u_cmm_cfgspace_low_addr_00_0_0_1_3__5737), + .LO(com_cmm_u_cmm_cfgspace_N_85927_i_5736) + ); + defparam com_cmm_u_cmm_cfgspace_N_85926_i.INIT = 16'h8FFF; + LUT4_L com_cmm_u_cmm_cfgspace_N_85926_i ( + .I0(com_cmm_u_cmm_cfgspace_N_61350), + .I1(com_cmm_bar4_reg[2]), + .I2(com_cmm_u_cmm_cfgspace_low_addr_00_0_0_0_0_2__5741), + .I3(com_cmm_u_cmm_cfgspace_low_addr_00_0_0_0_1_2__5740), + .LO(com_cmm_u_cmm_cfgspace_N_85926_i_5739) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_00_i_0_1_.INIT = 16'hC040; + LUT4_L com_cmm_u_cmm_cfgspace_low_addr_00_i_0_1_ ( + .I0(com_cmm_u_cmm_cfgspace_N_59538_1), + .I1(com_cmm_u_cmm_cfgspace_low_addr_00_i_0_1_39298_5743), + .I2(com_cmm_u_cmm_cfgspace_low_addr_00_i_0_1_39299_5742), + .I3(cfg_cfg_6102[1]), + .LO(com_cmm_u_cmm_cfgspace_N_40005_i) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_00_i_0_0_0_0_.INIT = 8'h80; + LUT3_L com_cmm_u_cmm_cfgspace_low_addr_00_i_0_0_0_0_ ( + .I0(com_cmm_u_cmm_cfgspace_low_addr_00_i_0_0_0_0[0]), + .I1(com_cmm_u_cmm_cfgspace_low_addr_00_i_0_0_0_1_0__5745), + .I2(com_cmm_u_cmm_cfgspace_low_addr_00_i_0_0_0_2_0__5744), + .LO(com_cmm_u_cmm_cfgspace_N_25682_i) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_02_7_0_16_.INIT = 8'hCA; + LUT3_L com_cmm_u_cmm_cfgspace_low_addr_02_7_0_16_ ( + .I0(com_cmm_u_cmm_cfgspace_N_4658), + .I1(com_cmm_u_cmm_cfgspace_N_4754), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex[0]), + .LO(com_cmm_u_cmm_cfgspace_low_addr_02[16]) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_02_7_0_14_.INIT = 8'hCA; + LUT3_L com_cmm_u_cmm_cfgspace_low_addr_02_7_0_14_ ( + .I0(com_cmm_u_cmm_cfgspace_N_4656), + .I1(com_cmm_u_cmm_cfgspace_N_4752), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex[0]), + .LO(com_cmm_u_cmm_cfgspace_low_addr_02[14]) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_02_7_0_12_.INIT = 8'hCA; + LUT3_L com_cmm_u_cmm_cfgspace_low_addr_02_7_0_12_ ( + .I0(com_cmm_u_cmm_cfgspace_N_4654), + .I1(com_cmm_u_cmm_cfgspace_N_4750), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex[0]), + .LO(com_cmm_u_cmm_cfgspace_low_addr_02[12]) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_02_7_0_11_.INIT = 8'hCA; + LUT3_L com_cmm_u_cmm_cfgspace_low_addr_02_7_0_11_ ( + .I0(com_cmm_u_cmm_cfgspace_N_4653), + .I1(com_cmm_u_cmm_cfgspace_N_4749), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex[0]), + .LO(com_cmm_u_cmm_cfgspace_low_addr_02[11]) + ); + defparam com_cmm_u_cmm_cfgspace_N_85958_i.INIT = 16'hFEFF; + LUT4_L com_cmm_u_cmm_cfgspace_N_85958_i ( + .I0(com_cmm_u_cmm_cfgspace_N_58588), + .I1(com_cmm_u_cmm_cfgspace_N_58589), + .I2(com_cmm_u_cmm_cfgspace_N_58591), + .I3(com_cmm_u_cmm_cfgspace_sel_encodex_en_3_i_0_0_0_0_5747), + .LO(com_cmm_u_cmm_cfgspace_N_85958_i_5746) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_01_7_0_10_.INIT = 8'hCA; + LUT3_L com_cmm_u_cmm_cfgspace_low_addr_01_7_0_10_ ( + .I0(com_cmm_u_cmm_cfgspace_N_3804), + .I1(com_cmm_u_cmm_cfgspace_N_3900), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex[0]), + .LO(com_cmm_u_cmm_cfgspace_low_addr_01[10]) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_01_7_0_0_.INIT = 8'hCA; + LUT3_L com_cmm_u_cmm_cfgspace_low_addr_01_7_0_0_ ( + .I0(com_cmm_u_cmm_cfgspace_N_3794), + .I1(com_cmm_u_cmm_cfgspace_N_3890), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex[0]), + .LO(com_cmm_u_cmm_cfgspace_low_addr_01[0]) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_00_i_0_1_20_.INIT = 16'h5010; + LUT4_L com_cmm_u_cmm_cfgspace_low_addr_00_i_0_1_20_ ( + .I0(com_cmm_u_cmm_cfgspace_N_58663), + .I1(com_cmm_u_cmm_cfgspace_N_61340), + .I2(com_cmm_u_cmm_cfgspace_low_addr_00_i_0_20_39323_5748), + .I3(cfg_cfg_6102[20]), + .LO(com_cmm_u_cmm_cfgspace_low_addr_00_i_0_1_20__5820) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_00_i_0_1_22_.INIT = 16'h5010; + LUT4_L com_cmm_u_cmm_cfgspace_low_addr_00_i_0_1_22_ ( + .I0(com_cmm_u_cmm_cfgspace_N_58663), + .I1(com_cmm_u_cmm_cfgspace_N_61340), + .I2(com_cmm_u_cmm_cfgspace_low_addr_00_i_0_22_39318_5749), + .I3(cfg_cfg_6102[22]), + .LO(com_cmm_u_cmm_cfgspace_low_addr_00_i_0_1_22__5818) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_00_i_0_0_1_23_.INIT = 16'h5010; + LUT4_L com_cmm_u_cmm_cfgspace_low_addr_00_i_0_0_1_23_ ( + .I0(com_cmm_u_cmm_cfgspace_N_58663), + .I1(com_cmm_u_cmm_cfgspace_N_61340), + .I2(com_cmm_u_cmm_cfgspace_low_addr_00_i_0_0_23_39342_5750), + .I3(cfg_cfg_6102[23]), + .LO(com_cmm_u_cmm_cfgspace_low_addr_00_i_0_0_1_23__5816) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_00_i_0_1_24_.INIT = 16'h5010; + LUT4_L com_cmm_u_cmm_cfgspace_low_addr_00_i_0_1_24_ ( + .I0(com_cmm_u_cmm_cfgspace_N_58663), + .I1(com_cmm_u_cmm_cfgspace_N_61340), + .I2(com_cmm_u_cmm_cfgspace_low_addr_00_i_0_24_39313_5751), + .I3(cfg_cfg_6102[24]), + .LO(com_cmm_u_cmm_cfgspace_low_addr_00_i_0_1_24__5814) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_00_i_0_0_1_25_.INIT = 16'h5010; + LUT4_L com_cmm_u_cmm_cfgspace_low_addr_00_i_0_0_1_25_ ( + .I0(com_cmm_u_cmm_cfgspace_N_58663), + .I1(com_cmm_u_cmm_cfgspace_N_61340), + .I2(com_cmm_u_cmm_cfgspace_low_addr_00_i_0_0_25_39337_5752), + .I3(cfg_cfg_6102[25]), + .LO(com_cmm_u_cmm_cfgspace_low_addr_00_i_0_0_1_25__5812) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_00_i_0_0_1_26_.INIT = 16'h5010; + LUT4_L com_cmm_u_cmm_cfgspace_low_addr_00_i_0_0_1_26_ ( + .I0(com_cmm_u_cmm_cfgspace_N_58663), + .I1(com_cmm_u_cmm_cfgspace_N_61340), + .I2(com_cmm_u_cmm_cfgspace_low_addr_00_i_0_0_26_39332_5753), + .I3(cfg_cfg_6102[26]), + .LO(com_cmm_u_cmm_cfgspace_low_addr_00_i_0_0_1_26__5810) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_00_i_0_0_1_30_.INIT = 16'h5010; + LUT4_L com_cmm_u_cmm_cfgspace_low_addr_00_i_0_0_1_30_ ( + .I0(com_cmm_u_cmm_cfgspace_N_58663), + .I1(com_cmm_u_cmm_cfgspace_N_61340), + .I2(com_cmm_u_cmm_cfgspace_low_addr_00_i_0_0_30_39347_5754), + .I3(cfg_cfg_6102[30]), + .LO(com_cmm_u_cmm_cfgspace_low_addr_00_i_0_0_1_30__5808) + ); + FDRS com_cmm_u_cmm_cfgspace_sel_encodex_1_1_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_cfgspace_N_86243_i_5755), + .Q(com_cmm_u_cmm_cfgspace_sel_encodex_1[1]), + .R(com_cmm_rst_351), + .S(com_cmm_u_cmm_cfgspace_N_86244_i_5757) + ); + FDRS com_cmm_u_cmm_cfgspace_sel_encodex_2_1_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_cfgspace_N_86243_i_5755), + .Q(com_cmm_u_cmm_cfgspace_sel_encodex_2[1]), + .R(com_cmm_rst_351), + .S(com_cmm_u_cmm_cfgspace_N_86244_i_5757) + ); + FDRS com_cmm_u_cmm_cfgspace_sel_encodex_1_2_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_cfgspace_N_86824_i_5756), + .Q(com_cmm_u_cmm_cfgspace_sel_encodex_1[2]), + .R(com_cmm_rst_351), + .S(com_cmm_u_cmm_cfgspace_N_86244_i_5757) + ); + FDRS com_cmm_u_cmm_cfgspace_sel_encodex_2_2_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_cfgspace_N_86824_i_5756), + .Q(com_cmm_u_cmm_cfgspace_sel_encodex_2[2]), + .R(com_cmm_rst_351), + .S(com_cmm_u_cmm_cfgspace_N_86244_i_5757) + ); + FDRS com_cmm_u_cmm_cfgspace_sel_encodex_1_0_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_cfgspace_N_86825_i_5758), + .Q(com_cmm_u_cmm_cfgspace_sel_encodex_1[0]), + .R(com_cmm_rst_351), + .S(com_cmm_u_cmm_cfgspace_N_86244_i_5757) + ); + defparam com_cmm_u_cmm_cfgspace_sel_encodex_en_3_i_0_0_0_o3_0.INIT = 8'h80; + LUT3 com_cmm_u_cmm_cfgspace_sel_encodex_en_3_i_0_0_0_o3_0 ( + .I0(com_cmm_cfg_addr[2]), + .I1(com_cmm_cfg_addr[4]), + .I2(com_cmm_cfg_addr[3]), + .O(com_cmm_u_cmm_cfgspace_sel_encodex_en_3_i_0_0_0_o3_0_5759) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_00_0_0_0_a3_2_2_.INIT = 8'h40; + LUT3 com_cmm_u_cmm_cfgspace_low_addr_00_0_0_0_a3_2_2_ ( + .I0(com_cmm_u_cmm_cfgspace_sel_encodex[1]), + .I1(com_cmm_u_cmm_cfgspace_sel_encodex[2]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex[0]), + .O(com_cmm_u_cmm_cfgspace_N_61356) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_00_0_0_0_a3_3_2_.INIT = 8'h08; + LUT3 com_cmm_u_cmm_cfgspace_low_addr_00_0_0_0_a3_3_2_ ( + .I0(com_cmm_u_cmm_cfgspace_sel_encodex[2]), + .I1(com_cmm_u_cmm_cfgspace_sel_encodex[1]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex[0]), + .O(com_cmm_u_cmm_cfgspace_N_61360) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_00_0_0_0_a3_1_2_.INIT = 8'h04; + LUT3 com_cmm_u_cmm_cfgspace_low_addr_00_0_0_0_a3_1_2_ ( + .I0(com_cmm_u_cmm_cfgspace_sel_encodex[2]), + .I1(com_cmm_u_cmm_cfgspace_sel_encodex[1]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex[0]), + .O(com_cmm_u_cmm_cfgspace_N_61350) + ); + defparam com_cmm_u_cmm_cfgspace_x3gio_decodepipe_h_sel_0x_3_0_0_0_0_a3_1.INIT = 8'h10; + LUT3 com_cmm_u_cmm_cfgspace_x3gio_decodepipe_h_sel_0x_3_0_0_0_0_a3_1 ( + .I0(com_cmm_cfg_addr[2]), + .I1(com_cmm_cfg_addr[6]), + .I2(com_cmm_u_cmm_cfgspace_N_58591_1), + .O(com_cmm_u_cmm_cfgspace_N_61290_1) + ); + defparam com_cmm_u_cmm_cfgspace_decoder_sel_addr_0_0_0_0_a2_0_2_.INIT = 8'h80; + LUT3 com_cmm_u_cmm_cfgspace_decoder_sel_addr_0_0_0_0_a2_0_2_ ( + .I0(com_cmm_cfg_addr[2]), + .I1(com_cmm_state_0[1]), + .I2(com_cmm_u_cmm_cfgspace_N_55879_i), + .O(com_cmm_u_cmm_cfgspace_N_57206) + ); + defparam com_cmm_u_cmm_cfgspace_x3gio_pmcsr_pme_pmcsr_21_0_i_0_0_o3_12_.INIT = 8'h80; + LUT3 com_cmm_u_cmm_cfgspace_x3gio_pmcsr_pme_pmcsr_21_0_i_0_0_o3_12_ ( + .I0(com_cmm_u_cmm_cfgspace_sel_x5_5783), + .I1(com_cmm_u_cmm_cfgspace_sel_4x_5772), + .I2(com_cmm_u_cmm_cfgspace_N_55870_i), + .O(N_56053_i) + ); + defparam com_cmm_u_cmm_cfgspace_x_dcmd_1_sqmuxa_1_0_a2_0_a2_0_a2.INIT = 8'h40; + LUT3 com_cmm_u_cmm_cfgspace_x_dcmd_1_sqmuxa_1_0_a2_0_a2_0_a2 ( + .I0(com_cmm_rst_351), + .I1(com_cmm_u_cmm_cfgspace_sel_x1_5787), + .I2(com_cmm_u_cmm_cfgspace_N_55912_i), + .O(com_cmm_u_cmm_cfgspace_x_dcmd_1_sqmuxa_1) + ); + defparam com_cmm_u_cmm_cfgspace_x3gio_bar2_bar2_reg_8_1_0_0_0_a2_0_1_3_.INIT = 8'h2A; + LUT3 com_cmm_u_cmm_cfgspace_x3gio_bar2_bar2_reg_8_1_0_0_0_a2_0_1_3_ ( + .I0(com_cmm_u_cmm_cfgspace_N_56070_i), + .I1(com_cmm_u_cmm_cfgspace_sel_x8_5780), + .I2(com_cmm_u_cmm_cfgspace_N_55892_i), + .O(com_cmm_u_cmm_cfgspace_N_57892_1) + ); + defparam com_cmm_u_cmm_cfgspace_x3gio_bar1_bar1_reg_8_1_0_0_a2_0_1_3_.INIT = 8'h2A; + LUT3 com_cmm_u_cmm_cfgspace_x3gio_bar1_bar1_reg_8_1_0_0_a2_0_1_3_ ( + .I0(com_cmm_u_cmm_cfgspace_N_56071_i), + .I1(com_cmm_u_cmm_cfgspace_sel_x4_5784), + .I2(com_cmm_u_cmm_cfgspace_N_55892_i), + .O(com_cmm_u_cmm_cfgspace_N_57880_1) + ); + defparam com_cmm_u_cmm_cfgspace_x3gio_bar4_bar4_reg_8_1_0_0_0_a2_0_1_3_.INIT = 8'h2A; + LUT3 com_cmm_u_cmm_cfgspace_x3gio_bar4_bar4_reg_8_1_0_0_0_a2_0_1_3_ ( + .I0(com_cmm_u_cmm_cfgspace_N_56068_i), + .I1(com_cmm_u_cmm_cfgspace_sel_x0_5788), + .I2(com_cmm_u_cmm_cfgspace_N_55910_i), + .O(com_cmm_u_cmm_cfgspace_N_57916_1) + ); + FDC com_cmm_u_cmm_cfgspace_set_detectedcorrectable ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_detectedcorrectable), + .Q(com_cmm_u_cmm_cfgspace_set_detectedcorrectable_5760), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_cfgspace_set_signaledtargetabort ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_signaledtargetabort), + .Q(com_cmm_u_cmm_cfgspace_set_signaledtargetabort_5761), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_cfgspace_set_signaledsystemerror ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_signaledsystemerror), + .Q(com_cmm_u_cmm_cfgspace_set_signaledsystemerror_5762), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_cfgspace_set_signaledpme ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_pme_sent), + .Q(com_cmm_u_cmm_cfgspace_set_signaledpme_5763), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_cfgspace_set_signaledint ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_signaledint), + .Q(com_cmm_u_cmm_cfgspace_set_signaledint_5794), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_cfgspace_set_receivedtargetabort ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_receivedtargetabort), + .Q(com_cmm_u_cmm_cfgspace_set_receivedtargetabort_5764), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_cfgspace_set_receivedmasterabort ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_receivedmasterabort), + .Q(com_cmm_u_cmm_cfgspace_set_receivedmasterabort_5765), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_cfgspace_set_masterdataparityerror ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_masterdataparityerror), + .Q(com_cmm_u_cmm_cfgspace_set_masterdataparityerror_5766), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_cfgspace_set_detectedparityerror ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_detectedparityerror), + .Q(com_cmm_u_cmm_cfgspace_set_detectedparityerror_5767), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_cfgspace_set_unsupportedreq ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_unsupportedreq), + .Q(com_cmm_u_cmm_cfgspace_set_unsupportedreq_5768), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_cfgspace_set_transaction_pending ( + .C(NlwRenamedSig_OI_trn_clk), + .D(cfg_trn_pending_n_i), + .Q(com_cmm_u_cmm_cfgspace_set_transaction_pending_5801), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_cfgspace_set_detectednonfatal ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_detectednonfatal), + .Q(com_cmm_u_cmm_cfgspace_set_detectednonfatal_5769), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_cfgspace_set_detectedfatal ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_detectedfatal), + .Q(com_cmm_u_cmm_cfgspace_set_detectedfatal_5770), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_cfgspace_sel_5x ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_cfgspace_N_86820_i), + .Q(com_cmm_u_cmm_cfgspace_sel_5x_5771), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_cfgspace_sel_4x ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_cfgspace_N_86821_i), + .Q(com_cmm_u_cmm_cfgspace_sel_4x_5772), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_cfgspace_sel_3x ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_cfgspace_N_86822_i), + .Q(com_cmm_u_cmm_cfgspace_sel_3x_5773), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_cfgspace_sel_2x ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_cfgspace_N_86266_i), + .Q(com_cmm_u_cmm_cfgspace_sel_2x_5774), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_cfgspace_sel_1x ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_cfgspace_N_86823_i), + .Q(com_cmm_u_cmm_cfgspace_sel_1x_5775), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_cfgspace_sel_0x ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_cfgspace_N_85811_i), + .Q(com_cmm_u_cmm_cfgspace_sel_0x_5776), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_cfgspace_sel_6x ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_cfgspace_N_86819_i), + .Q(com_cmm_u_cmm_cfgspace_sel_6x_5777), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_cfgspace_sel_xa ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_cfgspace_N_33690_i), + .Q(com_cmm_u_cmm_cfgspace_sel_xa_5778), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_cfgspace_sel_x9 ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_cfgspace_N_33688_i), + .Q(com_cmm_u_cmm_cfgspace_sel_x9_5779), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_cfgspace_sel_x8 ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_cfgspace_N_33686_i), + .Q(com_cmm_u_cmm_cfgspace_sel_x8_5780), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_cfgspace_sel_x7 ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_cfgspace_N_33684_i), + .Q(com_cmm_u_cmm_cfgspace_sel_x7_5781), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_cfgspace_sel_x6 ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_cfgspace_N_33682_i), + .Q(com_cmm_u_cmm_cfgspace_sel_x6_5782), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_cfgspace_sel_x5 ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_cfgspace_N_33680_i), + .Q(com_cmm_u_cmm_cfgspace_sel_x5_5783), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_cfgspace_sel_x4 ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_cfgspace_N_33678_i), + .Q(com_cmm_u_cmm_cfgspace_sel_x4_5784), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_cfgspace_sel_x3 ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_cfgspace_N_33676_i), + .Q(com_cmm_u_cmm_cfgspace_sel_x3_5785), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_cfgspace_sel_x2 ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_cfgspace_N_33674_i), + .Q(com_cmm_u_cmm_cfgspace_sel_x2_5786), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_cfgspace_sel_x1 ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_cfgspace_N_33672_i), + .Q(com_cmm_u_cmm_cfgspace_sel_x1_5787), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_cfgspace_sel_x0 ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_cfgspace_N_33670_i), + .Q(com_cmm_u_cmm_cfgspace_sel_x0_5788), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_cfgspace_sel_xf ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_cfgspace_N_33700_i), + .Q(com_cmm_u_cmm_cfgspace_sel_xf_5789), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_cfgspace_sel_xe ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_cfgspace_N_33698_i), + .Q(com_cmm_u_cmm_cfgspace_sel_xe_5790), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_cfgspace_sel_xd ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_cfgspace_N_33696_i), + .Q(com_cmm_u_cmm_cfgspace_sel_xd_5791), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_cfgspace_sel_xc ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_cfgspace_N_33694_i), + .Q(com_cmm_u_cmm_cfgspace_sel_xc_5792), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_cfgspace_sel_xb ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_cfgspace_N_33692_i), + .Q(com_cmm_u_cmm_cfgspace_sel_xb_5793), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_cfgspace_pme_pmcsr_1_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_cfgspace_N_17863_i), + .Q(com_cmm_pme_pmcsr[1]), + .CLR(trn_reset_n_i) + ); + FDC com_cmm_u_cmm_cfgspace_pme_pmcsr_0_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_cfgspace_N_17861_i), + .Q(com_cmm_pme_pmcsr[0]), + .CLR(trn_reset_n_i) + ); + FDC com_cmm_u_cmm_cfgspace_status_1_14_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_cfgspace_N_9940_i), + .Q(NlwRenamedSig_OI_cfg_status_14_), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_cfgspace_status_1_13_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_cfgspace_N_9939_i), + .Q(NlwRenamedSig_OI_cfg_status_13_), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_cfgspace_status_1_12_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_cfgspace_N_9938_i), + .Q(NlwRenamedSig_OI_cfg_status_12_), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_cfgspace_status_1_11_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_cfgspace_N_9937_i), + .Q(NlwRenamedSig_OI_cfg_status_11_), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_cfgspace_status_1_10_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_cfgspace_N_9951_i), + .Q(NlwRenamedSig_OI_cfg_status_8_), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_cfgspace_status_1_9_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_cfgspace_set_signaledint_5794), + .Q(NlwRenamedSig_OI_cfg_status_3_), + .CLR(com_cmm_rst_351) + ); + FDCE com_cmm_u_cmm_cfgspace_pme_pmcsr_15_ ( + .CE(com_cmm_rst_i_5321), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_cfgspace_N_9950_i), + .Q(com_cmm_u_cmm_cfgspace_pme_pmcsr[15]), + .CLR(trn_reset_n_i) + ); + FDC com_cmm_u_cmm_cfgspace_pme_pmcsr_14_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_cfgspace_pme_pmcsr_21[14]), + .Q(com_cmm_u_cmm_cfgspace_pme_pmcsr[14]), + .CLR(trn_reset_n_i) + ); + FDC com_cmm_u_cmm_cfgspace_pme_pmcsr_13_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_cfgspace_pme_pmcsr_21[13]), + .Q(com_cmm_u_cmm_cfgspace_pme_pmcsr[13]), + .CLR(trn_reset_n_i) + ); + FDC com_cmm_u_cmm_cfgspace_pme_pmcsr_12_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_cfgspace_N_35656_i), + .Q(com_cmm_u_cmm_cfgspace_pme_pmcsr[12]), + .CLR(trn_reset_n_i) + ); + FDC com_cmm_u_cmm_cfgspace_pme_pmcsr_11_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_cfgspace_N_39977_i), + .Q(com_cmm_u_cmm_cfgspace_pme_pmcsr[11]), + .CLR(trn_reset_n_i) + ); + FDC com_cmm_u_cmm_cfgspace_pme_pmcsr_10_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_cfgspace_N_39975_i), + .Q(com_cmm_u_cmm_cfgspace_pme_pmcsr[10]), + .CLR(trn_reset_n_i) + ); + FDC com_cmm_u_cmm_cfgspace_pme_pmcsr_9_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_cfgspace_N_35654_i), + .Q(com_cmm_u_cmm_cfgspace_pme_pmcsr[9]), + .CLR(trn_reset_n_i) + ); + FDCE com_cmm_u_cmm_cfgspace_pme_pmcsr_8_ ( + .CE(G_2710_0_a2_0_a2_0_a2_0_a2_352), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_cfg_wr_data_16_), + .Q(com_cmm_u_cmm_cfgspace_pme_pmcsr[8]), + .CLR(trn_reset_n_i) + ); + FDC com_cmm_u_cmm_cfgspace_bar1_reg_1_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_cfgspace_N_85866_i), + .Q(com_cmm_bar1_reg[1]), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_cfgspace_bar1_reg_0_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_cfgspace_N_85865_i), + .Q(com_cmm_bar1_reg[0]), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_cfgspace_state_6_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_cfgspace_state_5__5795), + .Q(com_cmm_state[6]), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_cfgspace_state_5_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_cfgspace_state_4__5796), + .Q(com_cmm_u_cmm_cfgspace_state_5__5795), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_cfgspace_state_4_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_cfgspace_N_33655_i), + .Q(com_cmm_u_cmm_cfgspace_state_4__5796), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_cfgspace_state_3_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_cfgspace_state_2__5797), + .Q(com_cmm_u_cmm_cfgspace_cfg2ulm_valid), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_cfgspace_state_2_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_cfgspace_state_1__5798), + .Q(com_cmm_u_cmm_cfgspace_state_2__5797), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_cfgspace_state_1_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_cfgspace_N_18655_i), + .Q(com_cmm_u_cmm_cfgspace_state_1__5798), + .CLR(com_cmm_rst_351) + ); + FDP com_cmm_u_cmm_cfgspace_state_0_ ( + .PRE(com_cmm_rst_351), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_cfgspace_N_85892_i_5799), + .Q(com_cmm_u_cmm_cfgspace_state_0__5800) + ); + FDC com_cmm_u_cmm_cfgspace_x_dsts_1_5_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_cfgspace_set_transaction_pending_5801), + .Q(NlwRenamedSig_OI_cfg_dstatus_5_), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_cfgspace_x_dsts_1_3_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_cfgspace_N_9949_i), + .Q(NlwRenamedSig_OI_cfg_dstatus_3_), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_cfgspace_x_dsts_1_2_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_cfgspace_N_9948_i), + .Q(NlwRenamedSig_OI_cfg_dstatus_2_), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_cfgspace_x_dsts_1_1_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_cfgspace_N_9947_i), + .Q(NlwRenamedSig_OI_cfg_dstatus_1_), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_cfgspace_x_dsts_1_0_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_cfgspace_N_9946_i), + .Q(NlwRenamedSig_OI_cfg_dstatus_0_), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_cfgspace_status_1_15_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_cfgspace_N_9941_i), + .Q(NlwRenamedSig_OI_cfg_status_15_), + .CLR(com_cmm_rst_351) + ); + FDCE com_cmm_u_cmm_cfgspace_bar1_reg_16_ ( + .CE(com_cmm_u_cmm_cfgspace_bar1_reg58), + .C(NlwRenamedSig_OI_trn_clk), + .D(I_4148_0_a2_0_a2_0_a2_0_a2_291), + .Q(com_cmm_bar1_reg[16]), + .CLR(com_cmm_rst_351) + ); + FDCE com_cmm_u_cmm_cfgspace_bar1_reg_15_ ( + .CE(com_cmm_u_cmm_cfgspace_bar1_reg45), + .C(NlwRenamedSig_OI_trn_clk), + .D(I_4153_0_a2_0_a2_0_a2_0_a2_290), + .Q(com_cmm_bar1_reg[15]), + .CLR(com_cmm_rst_351) + ); + FDCE com_cmm_u_cmm_cfgspace_bar1_reg_14_ ( + .CE(com_cmm_u_cmm_cfgspace_bar1_reg45), + .C(NlwRenamedSig_OI_trn_clk), + .D(I_4158_0_a2_0_a2_0_a2_0_a2_289), + .Q(com_cmm_bar1_reg[14]), + .CLR(com_cmm_rst_351) + ); + FDCE com_cmm_u_cmm_cfgspace_bar1_reg_13_ ( + .CE(com_cmm_u_cmm_cfgspace_bar1_reg45), + .C(NlwRenamedSig_OI_trn_clk), + .D(I_4163_0_a2_0_a2_0_a2_0_a2_288), + .Q(com_cmm_bar1_reg[13]), + .CLR(com_cmm_rst_351) + ); + FDCE com_cmm_u_cmm_cfgspace_bar1_reg_12_ ( + .CE(com_cmm_u_cmm_cfgspace_bar1_reg45), + .C(NlwRenamedSig_OI_trn_clk), + .D(I_4168_0_a2_0_a2_0_a2_0_a2_287), + .Q(com_cmm_bar1_reg[12]), + .CLR(com_cmm_rst_351) + ); + FDCE com_cmm_u_cmm_cfgspace_bar1_reg_11_ ( + .CE(com_cmm_u_cmm_cfgspace_bar1_reg45), + .C(NlwRenamedSig_OI_trn_clk), + .D(I_4173_0_a2_0_a2_0_a2_286), + .Q(com_cmm_bar1_reg[11]), + .CLR(com_cmm_rst_351) + ); + FDCE com_cmm_u_cmm_cfgspace_bar1_reg_10_ ( + .CE(com_cmm_u_cmm_cfgspace_bar1_reg45), + .C(NlwRenamedSig_OI_trn_clk), + .D(I_4178_0_a2_0_a2_0_a2_285), + .Q(com_cmm_bar1_reg[10]), + .CLR(com_cmm_rst_351) + ); + FDCE com_cmm_u_cmm_cfgspace_bar1_reg_9_ ( + .CE(com_cmm_u_cmm_cfgspace_bar1_reg45), + .C(NlwRenamedSig_OI_trn_clk), + .D(I_4183_0_a2_0_a2_0_a2_284), + .Q(com_cmm_bar1_reg[9]), + .CLR(com_cmm_rst_351) + ); + FDCE com_cmm_u_cmm_cfgspace_bar1_reg_8_ ( + .CE(com_cmm_u_cmm_cfgspace_bar1_reg45), + .C(NlwRenamedSig_OI_trn_clk), + .D(I_4188_0_a2_0_a2_0_a2_283), + .Q(com_cmm_bar1_reg[8]), + .CLR(com_cmm_rst_351) + ); + FDCE com_cmm_u_cmm_cfgspace_bar1_reg_7_ ( + .CE(com_cmm_u_cmm_cfgspace_N_55972_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(I_4193_0_a2_0_a2_0_a2_0_a2_282), + .Q(com_cmm_bar1_reg[7]), + .CLR(com_cmm_rst_351) + ); + FDCE com_cmm_u_cmm_cfgspace_bar1_reg_6_ ( + .CE(com_cmm_u_cmm_cfgspace_N_55972_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(I_4198_0_a2_0_a2_0_a2_0_a2_281), + .Q(com_cmm_bar1_reg[6]), + .CLR(com_cmm_rst_351) + ); + FDCE com_cmm_u_cmm_cfgspace_bar1_reg_5_ ( + .CE(com_cmm_u_cmm_cfgspace_N_55972_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(I_4203_0_a2_0_a2_0_a2_0_a2_280), + .Q(com_cmm_bar1_reg[5]), + .CLR(com_cmm_rst_351) + ); + FDCE com_cmm_u_cmm_cfgspace_bar1_reg_4_ ( + .CE(com_cmm_u_cmm_cfgspace_N_55972_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(I_4208_0_a2_0_a2_0_a2_0_a2_279), + .Q(com_cmm_bar1_reg[4]), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_cfgspace_bar1_reg_3_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_cfgspace_N_85868_i), + .Q(com_cmm_bar1_reg[3]), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_cfgspace_bar1_reg_2_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_cfgspace_N_85867_i), + .Q(com_cmm_bar1_reg[2]), + .CLR(com_cmm_rst_351) + ); + FDCE com_cmm_u_cmm_cfgspace_bar1_reg_31_ ( + .CE(com_cmm_u_cmm_cfgspace_bar1_reg70), + .C(NlwRenamedSig_OI_trn_clk), + .D(I_4213_0_a2_0_a2_0_a2_278), + .Q(com_cmm_bar1_reg[31]), + .CLR(com_cmm_rst_351) + ); + FDCE com_cmm_u_cmm_cfgspace_bar1_reg_30_ ( + .CE(com_cmm_u_cmm_cfgspace_bar1_reg70), + .C(NlwRenamedSig_OI_trn_clk), + .D(I_4218_0_a2_0_a2_0_a2_277), + .Q(com_cmm_bar1_reg[30]), + .CLR(com_cmm_rst_351) + ); + FDCE com_cmm_u_cmm_cfgspace_bar1_reg_29_ ( + .CE(com_cmm_u_cmm_cfgspace_bar1_reg70), + .C(NlwRenamedSig_OI_trn_clk), + .D(I_4223_0_a2_0_a2_0_a2_276), + .Q(com_cmm_bar1_reg[29]), + .CLR(com_cmm_rst_351) + ); + FDCE com_cmm_u_cmm_cfgspace_bar1_reg_28_ ( + .CE(com_cmm_u_cmm_cfgspace_bar1_reg70), + .C(NlwRenamedSig_OI_trn_clk), + .D(I_4228_0_a2_0_a2_0_a2_275), + .Q(com_cmm_bar1_reg[28]), + .CLR(com_cmm_rst_351) + ); + FDCE com_cmm_u_cmm_cfgspace_bar1_reg_27_ ( + .CE(com_cmm_u_cmm_cfgspace_bar1_reg70), + .C(NlwRenamedSig_OI_trn_clk), + .D(I_4233_0_a2_0_a2_0_a2_274), + .Q(com_cmm_bar1_reg[27]), + .CLR(com_cmm_rst_351) + ); + FDCE com_cmm_u_cmm_cfgspace_bar1_reg_26_ ( + .CE(com_cmm_u_cmm_cfgspace_bar1_reg70), + .C(NlwRenamedSig_OI_trn_clk), + .D(I_4238_0_a2_0_a2_0_a2_273), + .Q(com_cmm_bar1_reg[26]), + .CLR(com_cmm_rst_351) + ); + FDCE com_cmm_u_cmm_cfgspace_bar1_reg_25_ ( + .CE(com_cmm_u_cmm_cfgspace_bar1_reg70), + .C(NlwRenamedSig_OI_trn_clk), + .D(I_4243_0_a2_0_a2_0_a2_272), + .Q(com_cmm_bar1_reg[25]), + .CLR(com_cmm_rst_351) + ); + FDCE com_cmm_u_cmm_cfgspace_bar1_reg_24_ ( + .CE(com_cmm_u_cmm_cfgspace_bar1_reg70), + .C(NlwRenamedSig_OI_trn_clk), + .D(I_4248_0_a2_0_a2_0_a2_271), + .Q(com_cmm_bar1_reg[24]), + .CLR(com_cmm_rst_351) + ); + FDCE com_cmm_u_cmm_cfgspace_bar1_reg_23_ ( + .CE(com_cmm_u_cmm_cfgspace_bar1_reg58), + .C(NlwRenamedSig_OI_trn_clk), + .D(I_4253_0_a2_0_a2_0_a2_270), + .Q(com_cmm_bar1_reg[23]), + .CLR(com_cmm_rst_351) + ); + FDCE com_cmm_u_cmm_cfgspace_bar1_reg_22_ ( + .CE(com_cmm_u_cmm_cfgspace_bar1_reg58), + .C(NlwRenamedSig_OI_trn_clk), + .D(I_4258_0_a2_0_a2_0_a2_269), + .Q(com_cmm_bar1_reg[22]), + .CLR(com_cmm_rst_351) + ); + FDCE com_cmm_u_cmm_cfgspace_bar1_reg_21_ ( + .CE(com_cmm_u_cmm_cfgspace_bar1_reg58), + .C(NlwRenamedSig_OI_trn_clk), + .D(I_4263_0_a2_0_a2_0_a2_268), + .Q(com_cmm_bar1_reg[21]), + .CLR(com_cmm_rst_351) + ); + FDCE com_cmm_u_cmm_cfgspace_bar1_reg_20_ ( + .CE(com_cmm_u_cmm_cfgspace_bar1_reg58), + .C(NlwRenamedSig_OI_trn_clk), + .D(I_4268_0_a2_0_a2_0_a2_267), + .Q(com_cmm_bar1_reg[20]), + .CLR(com_cmm_rst_351) + ); + FDCE com_cmm_u_cmm_cfgspace_bar1_reg_19_ ( + .CE(com_cmm_u_cmm_cfgspace_bar1_reg58), + .C(NlwRenamedSig_OI_trn_clk), + .D(I_4273_0_a2_0_a2_0_a2_0_a2_266), + .Q(com_cmm_bar1_reg[19]), + .CLR(com_cmm_rst_351) + ); + FDCE com_cmm_u_cmm_cfgspace_bar1_reg_18_ ( + .CE(com_cmm_u_cmm_cfgspace_bar1_reg58), + .C(NlwRenamedSig_OI_trn_clk), + .D(I_4278_0_a2_0_a2_0_a2_0_a2_265), + .Q(com_cmm_bar1_reg[18]), + .CLR(com_cmm_rst_351) + ); + FDCE com_cmm_u_cmm_cfgspace_bar1_reg_17_ ( + .CE(com_cmm_u_cmm_cfgspace_bar1_reg58), + .C(NlwRenamedSig_OI_trn_clk), + .D(I_4283_0_a2_0_a2_0_a2_0_a2_264), + .Q(com_cmm_bar1_reg[17]), + .CLR(com_cmm_rst_351) + ); + FDCE com_cmm_u_cmm_cfgspace_bar2_reg_14_ ( + .CE(com_cmm_u_cmm_cfgspace_bar2_reg45), + .C(NlwRenamedSig_OI_trn_clk), + .D(I_4288_0_a2_0_a2_0_a2_0_a2_263), + .Q(com_cmm_bar2_reg[14]), + .CLR(com_cmm_rst_351) + ); + FDCE com_cmm_u_cmm_cfgspace_bar2_reg_13_ ( + .CE(com_cmm_u_cmm_cfgspace_bar2_reg45), + .C(NlwRenamedSig_OI_trn_clk), + .D(I_4293_0_a2_0_a2_0_a2_0_a2_262), + .Q(com_cmm_bar2_reg[13]), + .CLR(com_cmm_rst_351) + ); + FDCE com_cmm_u_cmm_cfgspace_bar2_reg_12_ ( + .CE(com_cmm_u_cmm_cfgspace_bar2_reg45), + .C(NlwRenamedSig_OI_trn_clk), + .D(I_4298_0_a2_0_a2_0_a2_0_a2_261), + .Q(com_cmm_bar2_reg[12]), + .CLR(com_cmm_rst_351) + ); + FDCE com_cmm_u_cmm_cfgspace_bar2_reg_11_ ( + .CE(com_cmm_u_cmm_cfgspace_bar2_reg45), + .C(NlwRenamedSig_OI_trn_clk), + .D(I_4303_0_a2_0_a2_0_a2_260), + .Q(com_cmm_bar2_reg[11]), + .CLR(com_cmm_rst_351) + ); + FDCE com_cmm_u_cmm_cfgspace_bar2_reg_10_ ( + .CE(com_cmm_u_cmm_cfgspace_bar2_reg45), + .C(NlwRenamedSig_OI_trn_clk), + .D(I_4308_0_a2_0_a2_0_a2_259), + .Q(com_cmm_bar2_reg[10]), + .CLR(com_cmm_rst_351) + ); + FDCE com_cmm_u_cmm_cfgspace_bar2_reg_9_ ( + .CE(com_cmm_u_cmm_cfgspace_bar2_reg45), + .C(NlwRenamedSig_OI_trn_clk), + .D(I_4313_0_a2_0_a2_0_a2_258), + .Q(com_cmm_bar2_reg[9]), + .CLR(com_cmm_rst_351) + ); + FDCE com_cmm_u_cmm_cfgspace_bar2_reg_8_ ( + .CE(com_cmm_u_cmm_cfgspace_bar2_reg45), + .C(NlwRenamedSig_OI_trn_clk), + .D(I_4318_0_a2_0_a2_0_a2_257), + .Q(com_cmm_bar2_reg[8]), + .CLR(com_cmm_rst_351) + ); + FDCE com_cmm_u_cmm_cfgspace_bar2_reg_7_ ( + .CE(com_cmm_u_cmm_cfgspace_N_55973_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(I_4323_0_a2_0_a2_0_a2_0_a2_256), + .Q(com_cmm_bar2_reg[7]), + .CLR(com_cmm_rst_351) + ); + FDCE com_cmm_u_cmm_cfgspace_bar2_reg_6_ ( + .CE(com_cmm_u_cmm_cfgspace_N_55973_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(I_4328_0_a2_0_a2_0_a2_0_a2_255), + .Q(com_cmm_bar2_reg[6]), + .CLR(com_cmm_rst_351) + ); + FDCE com_cmm_u_cmm_cfgspace_bar2_reg_5_ ( + .CE(com_cmm_u_cmm_cfgspace_N_55973_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(I_4333_0_a2_0_a2_0_a2_0_a2_254), + .Q(com_cmm_bar2_reg[5]), + .CLR(com_cmm_rst_351) + ); + FDCE com_cmm_u_cmm_cfgspace_bar2_reg_4_ ( + .CE(com_cmm_u_cmm_cfgspace_N_55973_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(I_4338_0_a2_0_a2_0_a2_0_a2_253), + .Q(com_cmm_bar2_reg[4]), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_cfgspace_bar2_reg_3_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_cfgspace_N_85872_i), + .Q(com_cmm_bar2_reg[3]), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_cfgspace_bar2_reg_2_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_cfgspace_N_85871_i), + .Q(com_cmm_bar2_reg[2]), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_cfgspace_bar2_reg_1_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_cfgspace_N_85870_i), + .Q(com_cmm_bar2_reg[1]), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_cfgspace_bar2_reg_0_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_cfgspace_N_85869_i), + .Q(com_cmm_bar2_reg[0]), + .CLR(com_cmm_rst_351) + ); + FDCE com_cmm_u_cmm_cfgspace_bar2_reg_29_ ( + .CE(com_cmm_u_cmm_cfgspace_bar2_reg70), + .C(NlwRenamedSig_OI_trn_clk), + .D(I_4343_0_a2_0_a2_0_a2_252), + .Q(com_cmm_bar2_reg[29]), + .CLR(com_cmm_rst_351) + ); + FDCE com_cmm_u_cmm_cfgspace_bar2_reg_28_ ( + .CE(com_cmm_u_cmm_cfgspace_bar2_reg70), + .C(NlwRenamedSig_OI_trn_clk), + .D(I_4348_0_a2_0_a2_0_a2_251), + .Q(com_cmm_bar2_reg[28]), + .CLR(com_cmm_rst_351) + ); + FDCE com_cmm_u_cmm_cfgspace_bar2_reg_27_ ( + .CE(com_cmm_u_cmm_cfgspace_bar2_reg70), + .C(NlwRenamedSig_OI_trn_clk), + .D(I_4353_0_a2_0_a2_0_a2_250), + .Q(com_cmm_bar2_reg[27]), + .CLR(com_cmm_rst_351) + ); + FDCE com_cmm_u_cmm_cfgspace_bar2_reg_26_ ( + .CE(com_cmm_u_cmm_cfgspace_bar2_reg70), + .C(NlwRenamedSig_OI_trn_clk), + .D(I_4358_0_a2_0_a2_0_a2_249), + .Q(com_cmm_bar2_reg[26]), + .CLR(com_cmm_rst_351) + ); + FDCE com_cmm_u_cmm_cfgspace_bar2_reg_25_ ( + .CE(com_cmm_u_cmm_cfgspace_bar2_reg70), + .C(NlwRenamedSig_OI_trn_clk), + .D(I_4363_0_a2_0_a2_0_a2_248), + .Q(com_cmm_bar2_reg[25]), + .CLR(com_cmm_rst_351) + ); + FDCE com_cmm_u_cmm_cfgspace_bar2_reg_24_ ( + .CE(com_cmm_u_cmm_cfgspace_bar2_reg70), + .C(NlwRenamedSig_OI_trn_clk), + .D(I_4368_0_a2_0_a2_0_a2_247), + .Q(com_cmm_bar2_reg[24]), + .CLR(com_cmm_rst_351) + ); + FDCE com_cmm_u_cmm_cfgspace_bar2_reg_23_ ( + .CE(com_cmm_u_cmm_cfgspace_bar2_reg58), + .C(NlwRenamedSig_OI_trn_clk), + .D(I_4373_0_a2_0_a2_0_a2_246), + .Q(com_cmm_bar2_reg[23]), + .CLR(com_cmm_rst_351) + ); + FDCE com_cmm_u_cmm_cfgspace_bar2_reg_22_ ( + .CE(com_cmm_u_cmm_cfgspace_bar2_reg58), + .C(NlwRenamedSig_OI_trn_clk), + .D(I_4378_0_a2_0_a2_0_a2_245), + .Q(com_cmm_bar2_reg[22]), + .CLR(com_cmm_rst_351) + ); + FDCE com_cmm_u_cmm_cfgspace_bar2_reg_21_ ( + .CE(com_cmm_u_cmm_cfgspace_bar2_reg58), + .C(NlwRenamedSig_OI_trn_clk), + .D(I_4383_0_a2_0_a2_0_a2_244), + .Q(com_cmm_bar2_reg[21]), + .CLR(com_cmm_rst_351) + ); + FDCE com_cmm_u_cmm_cfgspace_bar2_reg_20_ ( + .CE(com_cmm_u_cmm_cfgspace_bar2_reg58), + .C(NlwRenamedSig_OI_trn_clk), + .D(I_4388_0_a2_0_a2_0_a2_243), + .Q(com_cmm_bar2_reg[20]), + .CLR(com_cmm_rst_351) + ); + FDCE com_cmm_u_cmm_cfgspace_bar2_reg_19_ ( + .CE(com_cmm_u_cmm_cfgspace_bar2_reg58), + .C(NlwRenamedSig_OI_trn_clk), + .D(I_4393_0_a2_0_a2_0_a2_0_a2_242), + .Q(com_cmm_bar2_reg[19]), + .CLR(com_cmm_rst_351) + ); + FDCE com_cmm_u_cmm_cfgspace_bar2_reg_18_ ( + .CE(com_cmm_u_cmm_cfgspace_bar2_reg58), + .C(NlwRenamedSig_OI_trn_clk), + .D(I_4398_0_a2_0_a2_0_a2_0_a2_241), + .Q(com_cmm_bar2_reg[18]), + .CLR(com_cmm_rst_351) + ); + FDCE com_cmm_u_cmm_cfgspace_bar2_reg_17_ ( + .CE(com_cmm_u_cmm_cfgspace_bar2_reg58), + .C(NlwRenamedSig_OI_trn_clk), + .D(I_4403_0_a2_0_a2_0_a2_0_a2_240), + .Q(com_cmm_bar2_reg[17]), + .CLR(com_cmm_rst_351) + ); + FDCE com_cmm_u_cmm_cfgspace_bar2_reg_16_ ( + .CE(com_cmm_u_cmm_cfgspace_bar2_reg58), + .C(NlwRenamedSig_OI_trn_clk), + .D(I_4408_0_a2_0_a2_0_a2_0_a2_239), + .Q(com_cmm_bar2_reg[16]), + .CLR(com_cmm_rst_351) + ); + FDCE com_cmm_u_cmm_cfgspace_bar2_reg_15_ ( + .CE(com_cmm_u_cmm_cfgspace_bar2_reg45), + .C(NlwRenamedSig_OI_trn_clk), + .D(I_4413_0_a2_0_a2_0_a2_0_a2_238), + .Q(com_cmm_bar2_reg[15]), + .CLR(com_cmm_rst_351) + ); + FDCE com_cmm_u_cmm_cfgspace_bar3_reg_12_ ( + .CE(com_cmm_u_cmm_cfgspace_bar3_reg45), + .C(NlwRenamedSig_OI_trn_clk), + .D(I_4418_0_a2_0_a2_0_a2_0_a2_237), + .Q(com_cmm_bar3_reg[12]), + .CLR(com_cmm_rst_351) + ); + FDCE com_cmm_u_cmm_cfgspace_bar3_reg_11_ ( + .CE(com_cmm_u_cmm_cfgspace_bar3_reg45), + .C(NlwRenamedSig_OI_trn_clk), + .D(I_4423_0_a2_0_a2_0_a2_236), + .Q(com_cmm_bar3_reg[11]), + .CLR(com_cmm_rst_351) + ); + FDCE com_cmm_u_cmm_cfgspace_bar3_reg_10_ ( + .CE(com_cmm_u_cmm_cfgspace_bar3_reg45), + .C(NlwRenamedSig_OI_trn_clk), + .D(I_4428_0_a2_0_a2_0_a2_235), + .Q(com_cmm_bar3_reg[10]), + .CLR(com_cmm_rst_351) + ); + FDCE com_cmm_u_cmm_cfgspace_bar3_reg_9_ ( + .CE(com_cmm_u_cmm_cfgspace_bar3_reg45), + .C(NlwRenamedSig_OI_trn_clk), + .D(I_4433_0_a2_0_a2_0_a2_234), + .Q(com_cmm_bar3_reg[9]), + .CLR(com_cmm_rst_351) + ); + FDCE com_cmm_u_cmm_cfgspace_bar3_reg_8_ ( + .CE(com_cmm_u_cmm_cfgspace_bar3_reg45), + .C(NlwRenamedSig_OI_trn_clk), + .D(I_4438_0_a2_0_a2_0_a2_233), + .Q(com_cmm_bar3_reg[8]), + .CLR(com_cmm_rst_351) + ); + FDCE com_cmm_u_cmm_cfgspace_bar3_reg_7_ ( + .CE(com_cmm_u_cmm_cfgspace_N_55974_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(I_4443_0_a2_0_a2_0_a2_0_a2_232), + .Q(com_cmm_bar3_reg[7]), + .CLR(com_cmm_rst_351) + ); + FDCE com_cmm_u_cmm_cfgspace_bar3_reg_6_ ( + .CE(com_cmm_u_cmm_cfgspace_N_55974_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(I_4448_0_a2_0_a2_0_a2_0_a2_231), + .Q(com_cmm_bar3_reg[6]), + .CLR(com_cmm_rst_351) + ); + FDCE com_cmm_u_cmm_cfgspace_bar3_reg_5_ ( + .CE(com_cmm_u_cmm_cfgspace_N_55974_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(I_4453_0_a2_0_a2_0_a2_0_a2_230), + .Q(com_cmm_bar3_reg[5]), + .CLR(com_cmm_rst_351) + ); + FDCE com_cmm_u_cmm_cfgspace_bar3_reg_4_ ( + .CE(com_cmm_u_cmm_cfgspace_N_55974_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(I_4458_0_a2_0_a2_0_a2_0_a2_229), + .Q(com_cmm_bar3_reg[4]), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_cfgspace_bar3_reg_3_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_cfgspace_N_85876_i), + .Q(com_cmm_bar3_reg[3]), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_cfgspace_bar3_reg_2_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_cfgspace_N_85875_i), + .Q(com_cmm_bar3_reg[2]), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_cfgspace_bar3_reg_1_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_cfgspace_N_85874_i), + .Q(com_cmm_bar3_reg[1]), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_cfgspace_bar3_reg_0_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_cfgspace_N_85873_i), + .Q(com_cmm_bar3_reg[0]), + .CLR(com_cmm_rst_351) + ); + FDCE com_cmm_u_cmm_cfgspace_bar2_reg_31_ ( + .CE(com_cmm_u_cmm_cfgspace_bar2_reg70), + .C(NlwRenamedSig_OI_trn_clk), + .D(I_4463_0_a2_0_a2_0_a2_228), + .Q(com_cmm_bar2_reg[31]), + .CLR(com_cmm_rst_351) + ); + FDCE com_cmm_u_cmm_cfgspace_bar2_reg_30_ ( + .CE(com_cmm_u_cmm_cfgspace_bar2_reg70), + .C(NlwRenamedSig_OI_trn_clk), + .D(I_4468_0_a2_0_a2_0_a2_227), + .Q(com_cmm_bar2_reg[30]), + .CLR(com_cmm_rst_351) + ); + FDCE com_cmm_u_cmm_cfgspace_bar3_reg_27_ ( + .CE(com_cmm_u_cmm_cfgspace_bar3_reg70), + .C(NlwRenamedSig_OI_trn_clk), + .D(I_4473_0_a2_0_a2_0_a2_226), + .Q(com_cmm_bar3_reg[27]), + .CLR(com_cmm_rst_351) + ); + FDCE com_cmm_u_cmm_cfgspace_bar3_reg_26_ ( + .CE(com_cmm_u_cmm_cfgspace_bar3_reg70), + .C(NlwRenamedSig_OI_trn_clk), + .D(I_4478_0_a2_0_a2_0_a2_225), + .Q(com_cmm_bar3_reg[26]), + .CLR(com_cmm_rst_351) + ); + FDCE com_cmm_u_cmm_cfgspace_bar3_reg_25_ ( + .CE(com_cmm_u_cmm_cfgspace_bar3_reg70), + .C(NlwRenamedSig_OI_trn_clk), + .D(I_4483_0_a2_0_a2_0_a2_224), + .Q(com_cmm_bar3_reg[25]), + .CLR(com_cmm_rst_351) + ); + FDCE com_cmm_u_cmm_cfgspace_bar3_reg_24_ ( + .CE(com_cmm_u_cmm_cfgspace_bar3_reg70), + .C(NlwRenamedSig_OI_trn_clk), + .D(I_4488_0_a2_0_a2_0_a2_223), + .Q(com_cmm_bar3_reg[24]), + .CLR(com_cmm_rst_351) + ); + FDCE com_cmm_u_cmm_cfgspace_bar3_reg_23_ ( + .CE(com_cmm_u_cmm_cfgspace_bar3_reg58), + .C(NlwRenamedSig_OI_trn_clk), + .D(I_4493_0_a2_0_a2_0_a2_222), + .Q(com_cmm_bar3_reg[23]), + .CLR(com_cmm_rst_351) + ); + FDCE com_cmm_u_cmm_cfgspace_bar3_reg_22_ ( + .CE(com_cmm_u_cmm_cfgspace_bar3_reg58), + .C(NlwRenamedSig_OI_trn_clk), + .D(I_4498_0_a2_0_a2_0_a2_221), + .Q(com_cmm_bar3_reg[22]), + .CLR(com_cmm_rst_351) + ); + FDCE com_cmm_u_cmm_cfgspace_bar3_reg_21_ ( + .CE(com_cmm_u_cmm_cfgspace_bar3_reg58), + .C(NlwRenamedSig_OI_trn_clk), + .D(I_4503_0_a2_0_a2_0_a2_220), + .Q(com_cmm_bar3_reg[21]), + .CLR(com_cmm_rst_351) + ); + FDCE com_cmm_u_cmm_cfgspace_bar3_reg_20_ ( + .CE(com_cmm_u_cmm_cfgspace_bar3_reg58), + .C(NlwRenamedSig_OI_trn_clk), + .D(I_4508_0_a2_0_a2_0_a2_219), + .Q(com_cmm_bar3_reg[20]), + .CLR(com_cmm_rst_351) + ); + FDCE com_cmm_u_cmm_cfgspace_bar3_reg_19_ ( + .CE(com_cmm_u_cmm_cfgspace_bar3_reg58), + .C(NlwRenamedSig_OI_trn_clk), + .D(I_4513_0_a2_0_a2_0_a2_0_a2_218), + .Q(com_cmm_bar3_reg[19]), + .CLR(com_cmm_rst_351) + ); + FDCE com_cmm_u_cmm_cfgspace_bar3_reg_18_ ( + .CE(com_cmm_u_cmm_cfgspace_bar3_reg58), + .C(NlwRenamedSig_OI_trn_clk), + .D(I_4518_0_a2_0_a2_0_a2_0_a2_217), + .Q(com_cmm_bar3_reg[18]), + .CLR(com_cmm_rst_351) + ); + FDCE com_cmm_u_cmm_cfgspace_bar3_reg_17_ ( + .CE(com_cmm_u_cmm_cfgspace_bar3_reg58), + .C(NlwRenamedSig_OI_trn_clk), + .D(I_4523_0_a2_0_a2_0_a2_0_a2_216), + .Q(com_cmm_bar3_reg[17]), + .CLR(com_cmm_rst_351) + ); + FDCE com_cmm_u_cmm_cfgspace_bar3_reg_16_ ( + .CE(com_cmm_u_cmm_cfgspace_bar3_reg58), + .C(NlwRenamedSig_OI_trn_clk), + .D(I_4528_0_a2_0_a2_0_a2_0_a2_215), + .Q(com_cmm_bar3_reg[16]), + .CLR(com_cmm_rst_351) + ); + FDCE com_cmm_u_cmm_cfgspace_bar3_reg_15_ ( + .CE(com_cmm_u_cmm_cfgspace_bar3_reg45), + .C(NlwRenamedSig_OI_trn_clk), + .D(I_4533_0_a2_0_a2_0_a2_0_a2_214), + .Q(com_cmm_bar3_reg[15]), + .CLR(com_cmm_rst_351) + ); + FDCE com_cmm_u_cmm_cfgspace_bar3_reg_14_ ( + .CE(com_cmm_u_cmm_cfgspace_bar3_reg45), + .C(NlwRenamedSig_OI_trn_clk), + .D(I_4538_0_a2_0_a2_0_a2_0_a2_213), + .Q(com_cmm_bar3_reg[14]), + .CLR(com_cmm_rst_351) + ); + FDCE com_cmm_u_cmm_cfgspace_bar3_reg_13_ ( + .CE(com_cmm_u_cmm_cfgspace_bar3_reg45), + .C(NlwRenamedSig_OI_trn_clk), + .D(I_4543_0_a2_0_a2_0_a2_0_a2_212), + .Q(com_cmm_bar3_reg[13]), + .CLR(com_cmm_rst_351) + ); + FDCE com_cmm_u_cmm_cfgspace_bar4_reg_10_ ( + .CE(com_cmm_u_cmm_cfgspace_bar4_reg45), + .C(NlwRenamedSig_OI_trn_clk), + .D(I_4548_0_a2_0_a2_0_a2_211), + .Q(com_cmm_bar4_reg[10]), + .CLR(com_cmm_rst_351) + ); + FDCE com_cmm_u_cmm_cfgspace_bar4_reg_9_ ( + .CE(com_cmm_u_cmm_cfgspace_bar4_reg45), + .C(NlwRenamedSig_OI_trn_clk), + .D(I_4553_0_a2_0_a2_0_a2_210), + .Q(com_cmm_bar4_reg[9]), + .CLR(com_cmm_rst_351) + ); + FDCE com_cmm_u_cmm_cfgspace_bar4_reg_8_ ( + .CE(com_cmm_u_cmm_cfgspace_bar4_reg45), + .C(NlwRenamedSig_OI_trn_clk), + .D(I_4558_0_a2_0_a2_0_a2_209), + .Q(com_cmm_bar4_reg[8]), + .CLR(com_cmm_rst_351) + ); + FDCE com_cmm_u_cmm_cfgspace_bar4_reg_7_ ( + .CE(com_cmm_u_cmm_cfgspace_N_55970_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(I_4563_0_a2_0_a2_0_a2_0_a2_208), + .Q(com_cmm_bar4_reg[7]), + .CLR(com_cmm_rst_351) + ); + FDCE com_cmm_u_cmm_cfgspace_bar4_reg_6_ ( + .CE(com_cmm_u_cmm_cfgspace_N_55970_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(I_4568_0_a2_0_a2_0_a2_0_a2_207), + .Q(com_cmm_bar4_reg[6]), + .CLR(com_cmm_rst_351) + ); + FDCE com_cmm_u_cmm_cfgspace_bar4_reg_5_ ( + .CE(com_cmm_u_cmm_cfgspace_N_55970_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(I_4573_0_a2_0_a2_0_a2_0_a2_206), + .Q(com_cmm_bar4_reg[5]), + .CLR(com_cmm_rst_351) + ); + FDCE com_cmm_u_cmm_cfgspace_bar4_reg_4_ ( + .CE(com_cmm_u_cmm_cfgspace_N_55970_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(I_4578_0_a2_0_a2_0_a2_0_a2_205), + .Q(com_cmm_bar4_reg[4]), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_cfgspace_bar4_reg_3_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_cfgspace_N_85880_i), + .Q(com_cmm_bar4_reg[3]), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_cfgspace_bar4_reg_2_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_cfgspace_N_85879_i), + .Q(com_cmm_bar4_reg[2]), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_cfgspace_bar4_reg_1_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_cfgspace_N_85878_i), + .Q(com_cmm_bar4_reg[1]), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_cfgspace_bar4_reg_0_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_cfgspace_N_85877_i), + .Q(com_cmm_bar4_reg[0]), + .CLR(com_cmm_rst_351) + ); + FDCE com_cmm_u_cmm_cfgspace_bar3_reg_31_ ( + .CE(com_cmm_u_cmm_cfgspace_bar3_reg70), + .C(NlwRenamedSig_OI_trn_clk), + .D(I_4583_0_a2_0_a2_0_a2_204), + .Q(com_cmm_bar3_reg[31]), + .CLR(com_cmm_rst_351) + ); + FDCE com_cmm_u_cmm_cfgspace_bar3_reg_30_ ( + .CE(com_cmm_u_cmm_cfgspace_bar3_reg70), + .C(NlwRenamedSig_OI_trn_clk), + .D(I_4588_0_a2_0_a2_0_a2_203), + .Q(com_cmm_bar3_reg[30]), + .CLR(com_cmm_rst_351) + ); + FDCE com_cmm_u_cmm_cfgspace_bar3_reg_29_ ( + .CE(com_cmm_u_cmm_cfgspace_bar3_reg70), + .C(NlwRenamedSig_OI_trn_clk), + .D(I_4593_0_a2_0_a2_0_a2_202), + .Q(com_cmm_bar3_reg[29]), + .CLR(com_cmm_rst_351) + ); + FDCE com_cmm_u_cmm_cfgspace_bar3_reg_28_ ( + .CE(com_cmm_u_cmm_cfgspace_bar3_reg70), + .C(NlwRenamedSig_OI_trn_clk), + .D(I_4598_0_a2_0_a2_0_a2_201), + .Q(com_cmm_bar3_reg[28]), + .CLR(com_cmm_rst_351) + ); + FDCE com_cmm_u_cmm_cfgspace_bar4_reg_25_ ( + .CE(com_cmm_u_cmm_cfgspace_bar4_reg70), + .C(NlwRenamedSig_OI_trn_clk), + .D(I_4603_0_a2_0_a2_0_a2_200), + .Q(com_cmm_bar4_reg[25]), + .CLR(com_cmm_rst_351) + ); + FDCE com_cmm_u_cmm_cfgspace_bar4_reg_24_ ( + .CE(com_cmm_u_cmm_cfgspace_bar4_reg70), + .C(NlwRenamedSig_OI_trn_clk), + .D(I_4608_0_a2_0_a2_0_a2_199), + .Q(com_cmm_bar4_reg[24]), + .CLR(com_cmm_rst_351) + ); + FDCE com_cmm_u_cmm_cfgspace_bar4_reg_23_ ( + .CE(com_cmm_u_cmm_cfgspace_bar4_reg58), + .C(NlwRenamedSig_OI_trn_clk), + .D(I_4613_0_a2_0_a2_0_a2_198), + .Q(com_cmm_bar4_reg[23]), + .CLR(com_cmm_rst_351) + ); + FDCE com_cmm_u_cmm_cfgspace_bar4_reg_22_ ( + .CE(com_cmm_u_cmm_cfgspace_bar4_reg58), + .C(NlwRenamedSig_OI_trn_clk), + .D(I_4618_0_a2_0_a2_0_a2_197), + .Q(com_cmm_bar4_reg[22]), + .CLR(com_cmm_rst_351) + ); + FDCE com_cmm_u_cmm_cfgspace_bar4_reg_21_ ( + .CE(com_cmm_u_cmm_cfgspace_bar4_reg58), + .C(NlwRenamedSig_OI_trn_clk), + .D(I_4623_0_a2_0_a2_0_a2_196), + .Q(com_cmm_bar4_reg[21]), + .CLR(com_cmm_rst_351) + ); + FDCE com_cmm_u_cmm_cfgspace_bar4_reg_20_ ( + .CE(com_cmm_u_cmm_cfgspace_bar4_reg58), + .C(NlwRenamedSig_OI_trn_clk), + .D(I_4628_0_a2_0_a2_0_a2_195), + .Q(com_cmm_bar4_reg[20]), + .CLR(com_cmm_rst_351) + ); + FDCE com_cmm_u_cmm_cfgspace_bar4_reg_19_ ( + .CE(com_cmm_u_cmm_cfgspace_bar4_reg58), + .C(NlwRenamedSig_OI_trn_clk), + .D(I_4633_0_a2_0_a2_0_a2_0_a2_194), + .Q(com_cmm_bar4_reg[19]), + .CLR(com_cmm_rst_351) + ); + FDCE com_cmm_u_cmm_cfgspace_bar4_reg_18_ ( + .CE(com_cmm_u_cmm_cfgspace_bar4_reg58), + .C(NlwRenamedSig_OI_trn_clk), + .D(I_4638_0_a2_0_a2_0_a2_0_a2_193), + .Q(com_cmm_bar4_reg[18]), + .CLR(com_cmm_rst_351) + ); + FDCE com_cmm_u_cmm_cfgspace_bar4_reg_17_ ( + .CE(com_cmm_u_cmm_cfgspace_bar4_reg58), + .C(NlwRenamedSig_OI_trn_clk), + .D(I_4643_0_a2_0_a2_0_a2_0_a2_192), + .Q(com_cmm_bar4_reg[17]), + .CLR(com_cmm_rst_351) + ); + FDCE com_cmm_u_cmm_cfgspace_bar4_reg_16_ ( + .CE(com_cmm_u_cmm_cfgspace_bar4_reg58), + .C(NlwRenamedSig_OI_trn_clk), + .D(I_4648_0_a2_0_a2_0_a2_0_a2_191), + .Q(com_cmm_bar4_reg[16]), + .CLR(com_cmm_rst_351) + ); + FDCE com_cmm_u_cmm_cfgspace_bar4_reg_15_ ( + .CE(com_cmm_u_cmm_cfgspace_bar4_reg45), + .C(NlwRenamedSig_OI_trn_clk), + .D(I_4653_0_a2_0_a2_0_a2_0_a2_190), + .Q(com_cmm_bar4_reg[15]), + .CLR(com_cmm_rst_351) + ); + FDCE com_cmm_u_cmm_cfgspace_bar4_reg_14_ ( + .CE(com_cmm_u_cmm_cfgspace_bar4_reg45), + .C(NlwRenamedSig_OI_trn_clk), + .D(I_4658_0_a2_0_a2_0_a2_0_a2_189), + .Q(com_cmm_bar4_reg[14]), + .CLR(com_cmm_rst_351) + ); + FDCE com_cmm_u_cmm_cfgspace_bar4_reg_13_ ( + .CE(com_cmm_u_cmm_cfgspace_bar4_reg45), + .C(NlwRenamedSig_OI_trn_clk), + .D(I_4663_0_a2_0_a2_0_a2_0_a2_188), + .Q(com_cmm_bar4_reg[13]), + .CLR(com_cmm_rst_351) + ); + FDCE com_cmm_u_cmm_cfgspace_bar4_reg_12_ ( + .CE(com_cmm_u_cmm_cfgspace_bar4_reg45), + .C(NlwRenamedSig_OI_trn_clk), + .D(I_4668_0_a2_0_a2_0_a2_0_a2_187), + .Q(com_cmm_bar4_reg[12]), + .CLR(com_cmm_rst_351) + ); + FDCE com_cmm_u_cmm_cfgspace_bar4_reg_11_ ( + .CE(com_cmm_u_cmm_cfgspace_bar4_reg45), + .C(NlwRenamedSig_OI_trn_clk), + .D(I_4673_0_a2_0_a2_0_a2_186), + .Q(com_cmm_bar4_reg[11]), + .CLR(com_cmm_rst_351) + ); + FDCE com_cmm_u_cmm_cfgspace_bar5_reg_8_ ( + .CE(com_cmm_u_cmm_cfgspace_bar5_reg45), + .C(NlwRenamedSig_OI_trn_clk), + .D(I_4678_0_a2_0_a2_0_a2_0_a2_185), + .Q(com_cmm_bar5_reg[8]), + .CLR(com_cmm_rst_351) + ); + FDCE com_cmm_u_cmm_cfgspace_bar5_reg_7_ ( + .CE(com_cmm_u_cmm_cfgspace_N_55971_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(I_4683_0_a2_0_a2_0_a2_0_a2_184), + .Q(com_cmm_bar5_reg[7]), + .CLR(com_cmm_rst_351) + ); + FDCE com_cmm_u_cmm_cfgspace_bar5_reg_6_ ( + .CE(com_cmm_u_cmm_cfgspace_N_55971_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(I_4688_0_a2_0_a2_0_a2_0_a2_183), + .Q(com_cmm_bar5_reg[6]), + .CLR(com_cmm_rst_351) + ); + FDCE com_cmm_u_cmm_cfgspace_bar5_reg_5_ ( + .CE(com_cmm_u_cmm_cfgspace_N_55971_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(I_4693_0_a2_0_a2_0_a2_0_a2_182), + .Q(com_cmm_bar5_reg[5]), + .CLR(com_cmm_rst_351) + ); + FDCE com_cmm_u_cmm_cfgspace_bar5_reg_4_ ( + .CE(com_cmm_u_cmm_cfgspace_N_55971_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(I_4698_0_a2_0_a2_0_a2_0_a2_181), + .Q(com_cmm_bar5_reg[4]), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_cfgspace_bar5_reg_3_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_cfgspace_N_85884_i), + .Q(com_cmm_bar5_reg[3]), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_cfgspace_bar5_reg_2_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_cfgspace_N_85883_i), + .Q(com_cmm_bar5_reg[2]), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_cfgspace_bar5_reg_1_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_cfgspace_N_85882_i), + .Q(com_cmm_bar5_reg[1]), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_cfgspace_bar5_reg_0_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_cfgspace_N_85881_i), + .Q(com_cmm_bar5_reg[0]), + .CLR(com_cmm_rst_351) + ); + FDCE com_cmm_u_cmm_cfgspace_bar4_reg_31_ ( + .CE(com_cmm_u_cmm_cfgspace_bar4_reg70), + .C(NlwRenamedSig_OI_trn_clk), + .D(I_4703_0_a2_0_a2_0_a2_180), + .Q(com_cmm_bar4_reg[31]), + .CLR(com_cmm_rst_351) + ); + FDCE com_cmm_u_cmm_cfgspace_bar4_reg_30_ ( + .CE(com_cmm_u_cmm_cfgspace_bar4_reg70), + .C(NlwRenamedSig_OI_trn_clk), + .D(I_4708_0_a2_0_a2_0_a2_179), + .Q(com_cmm_bar4_reg[30]), + .CLR(com_cmm_rst_351) + ); + FDCE com_cmm_u_cmm_cfgspace_bar4_reg_29_ ( + .CE(com_cmm_u_cmm_cfgspace_bar4_reg70), + .C(NlwRenamedSig_OI_trn_clk), + .D(I_4713_0_a2_0_a2_0_a2_178), + .Q(com_cmm_bar4_reg[29]), + .CLR(com_cmm_rst_351) + ); + FDCE com_cmm_u_cmm_cfgspace_bar4_reg_28_ ( + .CE(com_cmm_u_cmm_cfgspace_bar4_reg70), + .C(NlwRenamedSig_OI_trn_clk), + .D(I_4718_0_a2_0_a2_0_a2_177), + .Q(com_cmm_bar4_reg[28]), + .CLR(com_cmm_rst_351) + ); + FDCE com_cmm_u_cmm_cfgspace_bar4_reg_27_ ( + .CE(com_cmm_u_cmm_cfgspace_bar4_reg70), + .C(NlwRenamedSig_OI_trn_clk), + .D(I_4723_0_a2_0_a2_0_a2_176), + .Q(com_cmm_bar4_reg[27]), + .CLR(com_cmm_rst_351) + ); + FDCE com_cmm_u_cmm_cfgspace_bar4_reg_26_ ( + .CE(com_cmm_u_cmm_cfgspace_bar4_reg70), + .C(NlwRenamedSig_OI_trn_clk), + .D(I_4728_0_a2_0_a2_0_a2_175), + .Q(com_cmm_bar4_reg[26]), + .CLR(com_cmm_rst_351) + ); + FDCE com_cmm_u_cmm_cfgspace_bar5_reg_23_ ( + .CE(com_cmm_u_cmm_cfgspace_bar5_reg58), + .C(NlwRenamedSig_OI_trn_clk), + .D(I_4733_0_a2_0_a2_0_a2_174), + .Q(com_cmm_bar5_reg[23]), + .CLR(com_cmm_rst_351) + ); + FDCE com_cmm_u_cmm_cfgspace_bar5_reg_22_ ( + .CE(com_cmm_u_cmm_cfgspace_bar5_reg58), + .C(NlwRenamedSig_OI_trn_clk), + .D(I_4738_0_a2_0_a2_0_a2_173), + .Q(com_cmm_bar5_reg[22]), + .CLR(com_cmm_rst_351) + ); + FDCE com_cmm_u_cmm_cfgspace_bar5_reg_21_ ( + .CE(com_cmm_u_cmm_cfgspace_bar5_reg58), + .C(NlwRenamedSig_OI_trn_clk), + .D(I_4743_0_a2_0_a2_0_a2_172), + .Q(com_cmm_bar5_reg[21]), + .CLR(com_cmm_rst_351) + ); + FDCE com_cmm_u_cmm_cfgspace_bar5_reg_20_ ( + .CE(com_cmm_u_cmm_cfgspace_bar5_reg58), + .C(NlwRenamedSig_OI_trn_clk), + .D(I_4748_0_a2_0_a2_0_a2_171), + .Q(com_cmm_bar5_reg[20]), + .CLR(com_cmm_rst_351) + ); + FDCE com_cmm_u_cmm_cfgspace_bar5_reg_19_ ( + .CE(com_cmm_u_cmm_cfgspace_bar5_reg58), + .C(NlwRenamedSig_OI_trn_clk), + .D(I_4753_0_a2_0_a2_0_a2_0_a2_170), + .Q(com_cmm_bar5_reg[19]), + .CLR(com_cmm_rst_351) + ); + FDCE com_cmm_u_cmm_cfgspace_bar5_reg_18_ ( + .CE(com_cmm_u_cmm_cfgspace_bar5_reg58), + .C(NlwRenamedSig_OI_trn_clk), + .D(I_4758_0_a2_0_a2_0_a2_0_a2_169), + .Q(com_cmm_bar5_reg[18]), + .CLR(com_cmm_rst_351) + ); + FDCE com_cmm_u_cmm_cfgspace_bar5_reg_17_ ( + .CE(com_cmm_u_cmm_cfgspace_bar5_reg58), + .C(NlwRenamedSig_OI_trn_clk), + .D(I_4763_0_a2_0_a2_0_a2_0_a2_168), + .Q(com_cmm_bar5_reg[17]), + .CLR(com_cmm_rst_351) + ); + FDCE com_cmm_u_cmm_cfgspace_bar5_reg_16_ ( + .CE(com_cmm_u_cmm_cfgspace_bar5_reg58), + .C(NlwRenamedSig_OI_trn_clk), + .D(I_4768_0_a2_0_a2_0_a2_0_a2_167), + .Q(com_cmm_bar5_reg[16]), + .CLR(com_cmm_rst_351) + ); + FDCE com_cmm_u_cmm_cfgspace_bar5_reg_15_ ( + .CE(com_cmm_u_cmm_cfgspace_bar5_reg45), + .C(NlwRenamedSig_OI_trn_clk), + .D(I_4773_0_a2_0_a2_0_a2_0_a2_166), + .Q(com_cmm_bar5_reg[15]), + .CLR(com_cmm_rst_351) + ); + FDCE com_cmm_u_cmm_cfgspace_bar5_reg_14_ ( + .CE(com_cmm_u_cmm_cfgspace_bar5_reg45), + .C(NlwRenamedSig_OI_trn_clk), + .D(I_4778_0_a2_0_a2_0_a2_0_a2_165), + .Q(com_cmm_bar5_reg[14]), + .CLR(com_cmm_rst_351) + ); + FDCE com_cmm_u_cmm_cfgspace_bar5_reg_13_ ( + .CE(com_cmm_u_cmm_cfgspace_bar5_reg45), + .C(NlwRenamedSig_OI_trn_clk), + .D(I_4783_0_a2_0_a2_0_a2_0_a2_164), + .Q(com_cmm_bar5_reg[13]), + .CLR(com_cmm_rst_351) + ); + FDCE com_cmm_u_cmm_cfgspace_bar5_reg_12_ ( + .CE(com_cmm_u_cmm_cfgspace_bar5_reg45), + .C(NlwRenamedSig_OI_trn_clk), + .D(I_4788_0_a2_0_a2_0_a2_0_a2_163), + .Q(com_cmm_bar5_reg[12]), + .CLR(com_cmm_rst_351) + ); + FDCE com_cmm_u_cmm_cfgspace_bar5_reg_11_ ( + .CE(com_cmm_u_cmm_cfgspace_bar5_reg45), + .C(NlwRenamedSig_OI_trn_clk), + .D(I_4793_0_a2_0_a2_0_a2_162), + .Q(com_cmm_bar5_reg[11]), + .CLR(com_cmm_rst_351) + ); + FDCE com_cmm_u_cmm_cfgspace_bar5_reg_10_ ( + .CE(com_cmm_u_cmm_cfgspace_bar5_reg45), + .C(NlwRenamedSig_OI_trn_clk), + .D(I_4798_0_a2_0_a2_0_a2_161), + .Q(com_cmm_bar5_reg[10]), + .CLR(com_cmm_rst_351) + ); + FDCE com_cmm_u_cmm_cfgspace_bar5_reg_9_ ( + .CE(com_cmm_u_cmm_cfgspace_bar5_reg45), + .C(NlwRenamedSig_OI_trn_clk), + .D(I_4803_0_a2_0_a2_0_a2_160), + .Q(com_cmm_bar5_reg[9]), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_cfgspace_x_dcmd_1_6_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_cfgspace_N_40410_i), + .Q(NlwRenamedSig_OI_cfg_dcommand[6]), + .CLR(trn_reset_n_i) + ); + FDC com_cmm_u_cmm_cfgspace_x_dcmd_1_5_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_cfgspace_N_40408_i), + .Q(NlwRenamedSig_OI_cfg_dcommand[5]), + .CLR(trn_reset_n_i) + ); + FDP com_cmm_u_cmm_cfgspace_x_dcmd_1_4_ ( + .PRE(trn_reset_n_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_cfgspace_N_86401_i_5802), + .Q(NlwRenamedSig_OI_cfg_dcommand[4]) + ); + FDC com_cmm_u_cmm_cfgspace_x_dcmd_1_3_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_cfgspace_N_40001_i), + .Q(NlwRenamedSig_OI_cfg_dcommand[3]), + .CLR(trn_reset_n_i) + ); + FDC com_cmm_u_cmm_cfgspace_x_dcmd_1_2_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_cfgspace_N_17888_i), + .Q(NlwRenamedSig_OI_cfg_dcommand[2]), + .CLR(trn_reset_n_i) + ); + FDC com_cmm_u_cmm_cfgspace_x_dcmd_1_1_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_cfgspace_N_17886_i), + .Q(NlwRenamedSig_OI_cfg_dcommand[1]), + .CLR(trn_reset_n_i) + ); + FDC com_cmm_u_cmm_cfgspace_x_dcmd_1_0_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_cfgspace_N_17884_i), + .Q(NlwRenamedSig_OI_cfg_dcommand[0]), + .CLR(trn_reset_n_i) + ); + FDCE com_cmm_u_cmm_cfgspace_bar5_reg_31_ ( + .CE(com_cmm_u_cmm_cfgspace_bar5_reg70), + .C(NlwRenamedSig_OI_trn_clk), + .D(I_4808_0_a2_0_a2_0_a2_159), + .Q(com_cmm_bar5_reg[31]), + .CLR(com_cmm_rst_351) + ); + FDCE com_cmm_u_cmm_cfgspace_bar5_reg_30_ ( + .CE(com_cmm_u_cmm_cfgspace_bar5_reg70), + .C(NlwRenamedSig_OI_trn_clk), + .D(I_4813_0_a2_0_a2_0_a2_158), + .Q(com_cmm_bar5_reg[30]), + .CLR(com_cmm_rst_351) + ); + FDCE com_cmm_u_cmm_cfgspace_bar5_reg_29_ ( + .CE(com_cmm_u_cmm_cfgspace_bar5_reg70), + .C(NlwRenamedSig_OI_trn_clk), + .D(I_4818_0_a2_0_a2_0_a2_157), + .Q(com_cmm_bar5_reg[29]), + .CLR(com_cmm_rst_351) + ); + FDCE com_cmm_u_cmm_cfgspace_bar5_reg_28_ ( + .CE(com_cmm_u_cmm_cfgspace_bar5_reg70), + .C(NlwRenamedSig_OI_trn_clk), + .D(I_4823_0_a2_0_a2_0_a2_156), + .Q(com_cmm_bar5_reg[28]), + .CLR(com_cmm_rst_351) + ); + FDCE com_cmm_u_cmm_cfgspace_bar5_reg_27_ ( + .CE(com_cmm_u_cmm_cfgspace_bar5_reg70), + .C(NlwRenamedSig_OI_trn_clk), + .D(I_4828_0_a2_0_a2_0_a2_155), + .Q(com_cmm_bar5_reg[27]), + .CLR(com_cmm_rst_351) + ); + FDCE com_cmm_u_cmm_cfgspace_bar5_reg_26_ ( + .CE(com_cmm_u_cmm_cfgspace_bar5_reg70), + .C(NlwRenamedSig_OI_trn_clk), + .D(I_4833_0_a2_0_a2_0_a2_154), + .Q(com_cmm_bar5_reg[26]), + .CLR(com_cmm_rst_351) + ); + FDCE com_cmm_u_cmm_cfgspace_bar5_reg_25_ ( + .CE(com_cmm_u_cmm_cfgspace_bar5_reg70), + .C(NlwRenamedSig_OI_trn_clk), + .D(I_4838_0_a2_0_a2_0_a2_153), + .Q(com_cmm_bar5_reg[25]), + .CLR(com_cmm_rst_351) + ); + FDCE com_cmm_u_cmm_cfgspace_bar5_reg_24_ ( + .CE(com_cmm_u_cmm_cfgspace_bar5_reg70), + .C(NlwRenamedSig_OI_trn_clk), + .D(I_4843_0_a2_0_a2_0_a2_152), + .Q(com_cmm_bar5_reg[24]), + .CLR(com_cmm_rst_351) + ); + FDCE com_cmm_u_cmm_cfgspace_bar0_reg_6_ ( + .CE(com_cmm_u_cmm_cfgspace_bar0_reg18), + .C(NlwRenamedSig_OI_trn_clk), + .D(I_4848_0_a2_0_a2_0_a2_0_a2_151), + .Q(com_cmm_bar0_reg_6_), + .CLR(com_cmm_rst_351) + ); + FDCE com_cmm_u_cmm_cfgspace_bar0_reg_5_ ( + .CE(com_cmm_u_cmm_cfgspace_bar0_reg18), + .C(NlwRenamedSig_OI_trn_clk), + .D(I_4853_0_a2_0_a2_0_a2_0_a2_150), + .Q(com_cmm_bar0_reg_5_), + .CLR(com_cmm_rst_351) + ); + FDCE com_cmm_u_cmm_cfgspace_bar0_reg_4_ ( + .CE(com_cmm_u_cmm_cfgspace_bar0_reg18), + .C(NlwRenamedSig_OI_trn_clk), + .D(I_4858_0_a2_0_a2_0_a2_0_a2_149), + .Q(com_cmm_bar0_reg_4_), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_cfgspace_bar0_reg_3_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(cfg_cfg_6102[67]), + .Q(com_cmm_u_cmm_cfgspace_bar0_reg[3]), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_cfgspace_bar0_reg_2_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(cfg_cfg_6102[66]), + .Q(com_cmm_bar0_reg_2_), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_cfgspace_bar0_reg_1_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(cfg_cfg_6102[65]), + .Q(com_cmm_bar0_reg_1_), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_cfgspace_bar0_reg_0_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(cfg_cfg_6102[64]), + .Q(com_cmm_bar0_reg_0_), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_cfgspace_x_dcmd_1_14_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_cfgspace_N_35664_i), + .Q(NlwRenamedSig_OI_cfg_dcommand[14]), + .CLR(trn_reset_n_i) + ); + FDP com_cmm_u_cmm_cfgspace_x_dcmd_1_13_ ( + .PRE(trn_reset_n_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_cfgspace_N_86412_i_5803), + .Q(NlwRenamedSig_OI_cfg_dcommand[13]) + ); + FDC com_cmm_u_cmm_cfgspace_x_dcmd_1_12_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_cfgspace_N_35662_i), + .Q(NlwRenamedSig_OI_cfg_dcommand[12]), + .CLR(trn_reset_n_i) + ); + FDP com_cmm_u_cmm_cfgspace_x_dcmd_1_11_ ( + .PRE(trn_reset_n_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_cfgspace_N_86410_i_5804), + .Q(NlwRenamedSig_OI_cfg_dcommand[11]) + ); + FDCE com_cmm_u_cmm_cfgspace_x_dcmd_1_10_ ( + .CE(com_cmm_u_cmm_cfgspace_x_dcmd_1_sqmuxa_1), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_cfg_wr_data_18_), + .Q(NlwRenamedSig_OI_cfg_dcommand[10]), + .CLR(trn_reset_n_i) + ); + FDC com_cmm_u_cmm_cfgspace_x_dcmd_1_9_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_cfgspace_N_35660_i), + .Q(NlwRenamedSig_OI_cfg_dcommand[9]), + .CLR(trn_reset_n_i) + ); + FDC com_cmm_u_cmm_cfgspace_x_dcmd_1_8_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_cfgspace_N_40003_i), + .Q(NlwRenamedSig_OI_cfg_dcommand[8]), + .CLR(trn_reset_n_i) + ); + FDC com_cmm_u_cmm_cfgspace_x_dcmd_1_7_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_cfgspace_N_40412_i), + .Q(NlwRenamedSig_OI_cfg_dcommand[7]), + .CLR(trn_reset_n_i) + ); + FDCE com_cmm_u_cmm_cfgspace_bar0_reg_21_ ( + .CE(com_cmm_u_cmm_cfgspace_bar0_reg44), + .C(NlwRenamedSig_OI_trn_clk), + .D(I_4863_0_a2_0_a2_0_a2_148), + .Q(com_cmm_bar0_reg_21_), + .CLR(com_cmm_rst_351) + ); + FDCE com_cmm_u_cmm_cfgspace_bar0_reg_20_ ( + .CE(com_cmm_u_cmm_cfgspace_bar0_reg44), + .C(NlwRenamedSig_OI_trn_clk), + .D(I_4868_0_a2_0_a2_0_a2_147), + .Q(com_cmm_bar0_reg_20_), + .CLR(com_cmm_rst_351) + ); + FDCE com_cmm_u_cmm_cfgspace_bar0_reg_19_ ( + .CE(com_cmm_u_cmm_cfgspace_bar0_reg44), + .C(NlwRenamedSig_OI_trn_clk), + .D(I_4873_0_a2_0_a2_0_a2_0_a2_146), + .Q(com_cmm_bar0_reg_19_), + .CLR(com_cmm_rst_351) + ); + FDCE com_cmm_u_cmm_cfgspace_bar0_reg_18_ ( + .CE(com_cmm_u_cmm_cfgspace_bar0_reg44), + .C(NlwRenamedSig_OI_trn_clk), + .D(I_4878_0_a2_0_a2_0_a2_0_a2_145), + .Q(com_cmm_bar0_reg_18_), + .CLR(com_cmm_rst_351) + ); + FDCE com_cmm_u_cmm_cfgspace_bar0_reg_17_ ( + .CE(com_cmm_u_cmm_cfgspace_bar0_reg44), + .C(NlwRenamedSig_OI_trn_clk), + .D(I_4883_0_a2_0_a2_0_a2_0_a2_144), + .Q(com_cmm_bar0_reg_17_), + .CLR(com_cmm_rst_351) + ); + FDCE com_cmm_u_cmm_cfgspace_bar0_reg_16_ ( + .CE(com_cmm_u_cmm_cfgspace_bar0_reg44), + .C(NlwRenamedSig_OI_trn_clk), + .D(I_4888_0_a2_0_a2_0_a2_0_a2_143), + .Q(com_cmm_bar0_reg_16_), + .CLR(com_cmm_rst_351) + ); + FDCE com_cmm_u_cmm_cfgspace_bar0_reg_15_ ( + .CE(com_cmm_u_cmm_cfgspace_bar0_reg31), + .C(NlwRenamedSig_OI_trn_clk), + .D(I_4893_0_a2_0_a2_0_a2_0_a2_142), + .Q(com_cmm_bar0_reg_15_), + .CLR(com_cmm_rst_351) + ); + FDCE com_cmm_u_cmm_cfgspace_bar0_reg_14_ ( + .CE(com_cmm_u_cmm_cfgspace_bar0_reg31), + .C(NlwRenamedSig_OI_trn_clk), + .D(I_4898_0_a2_0_a2_0_a2_0_a2_141), + .Q(com_cmm_bar0_reg_14_), + .CLR(com_cmm_rst_351) + ); + FDCE com_cmm_u_cmm_cfgspace_bar0_reg_13_ ( + .CE(com_cmm_u_cmm_cfgspace_bar0_reg31), + .C(NlwRenamedSig_OI_trn_clk), + .D(I_4903_0_a2_0_a2_0_a2_0_a2_140), + .Q(com_cmm_bar0_reg_13_), + .CLR(com_cmm_rst_351) + ); + FDCE com_cmm_u_cmm_cfgspace_bar0_reg_12_ ( + .CE(com_cmm_u_cmm_cfgspace_bar0_reg31), + .C(NlwRenamedSig_OI_trn_clk), + .D(I_4908_0_a2_0_a2_0_a2_0_a2_139), + .Q(com_cmm_bar0_reg_12_), + .CLR(com_cmm_rst_351) + ); + FDCE com_cmm_u_cmm_cfgspace_bar0_reg_11_ ( + .CE(com_cmm_u_cmm_cfgspace_bar0_reg31), + .C(NlwRenamedSig_OI_trn_clk), + .D(I_4913_0_a2_0_a2_0_a2_138), + .Q(com_cmm_bar0_reg_11_), + .CLR(com_cmm_rst_351) + ); + FDCE com_cmm_u_cmm_cfgspace_bar0_reg_10_ ( + .CE(com_cmm_u_cmm_cfgspace_bar0_reg31), + .C(NlwRenamedSig_OI_trn_clk), + .D(I_4918_0_a2_0_a2_0_a2_137), + .Q(com_cmm_bar0_reg_10_), + .CLR(com_cmm_rst_351) + ); + FDCE com_cmm_u_cmm_cfgspace_bar0_reg_9_ ( + .CE(com_cmm_u_cmm_cfgspace_bar0_reg31), + .C(NlwRenamedSig_OI_trn_clk), + .D(I_4923_0_a2_0_a2_0_a2_136), + .Q(com_cmm_bar0_reg_9_), + .CLR(com_cmm_rst_351) + ); + FDCE com_cmm_u_cmm_cfgspace_bar0_reg_8_ ( + .CE(com_cmm_u_cmm_cfgspace_bar0_reg31), + .C(NlwRenamedSig_OI_trn_clk), + .D(I_4928_0_a2_0_a2_0_a2_135), + .Q(com_cmm_bar0_reg_8_), + .CLR(com_cmm_rst_351) + ); + FDCE com_cmm_u_cmm_cfgspace_bar0_reg_7_ ( + .CE(com_cmm_u_cmm_cfgspace_bar0_reg18), + .C(NlwRenamedSig_OI_trn_clk), + .D(I_4933_0_a2_0_a2_0_a2_0_a2_134), + .Q(com_cmm_bar0_reg_7_), + .CLR(com_cmm_rst_351) + ); + FDCE com_cmm_u_cmm_cfgspace_msi_laddr_1_6_ ( + .CE(com_cmm_u_cmm_cfgspace_msi_laddr16), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_cfg_wr_data_30_), + .Q(com_cmm_msi_laddr[6]), + .CLR(com_cmm_rst_351) + ); + FDCE com_cmm_u_cmm_cfgspace_msi_laddr_1_5_ ( + .CE(com_cmm_u_cmm_cfgspace_msi_laddr16), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_cfg_wr_data_29_), + .Q(com_cmm_msi_laddr[5]), + .CLR(com_cmm_rst_351) + ); + FDCE com_cmm_u_cmm_cfgspace_msi_laddr_1_4_ ( + .CE(com_cmm_u_cmm_cfgspace_msi_laddr16), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_cfg_wr_data_28_), + .Q(com_cmm_msi_laddr[4]), + .CLR(com_cmm_rst_351) + ); + FDCE com_cmm_u_cmm_cfgspace_msi_laddr_1_3_ ( + .CE(com_cmm_u_cmm_cfgspace_msi_laddr16), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_cfg_wr_data[27]), + .Q(com_cmm_msi_laddr[3]), + .CLR(com_cmm_rst_351) + ); + FDCE com_cmm_u_cmm_cfgspace_msi_laddr_1_2_ ( + .CE(com_cmm_u_cmm_cfgspace_msi_laddr16), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_cfg_wr_data[26]), + .Q(com_cmm_msi_laddr[2]), + .CLR(com_cmm_rst_351) + ); + FDCE com_cmm_u_cmm_cfgspace_bar0_reg_31_ ( + .CE(com_cmm_u_cmm_cfgspace_bar0_reg56), + .C(NlwRenamedSig_OI_trn_clk), + .D(I_4938_0_a2_0_a2_0_a2_133), + .Q(com_cmm_bar0_reg_31_), + .CLR(com_cmm_rst_351) + ); + FDCE com_cmm_u_cmm_cfgspace_bar0_reg_30_ ( + .CE(com_cmm_u_cmm_cfgspace_bar0_reg56), + .C(NlwRenamedSig_OI_trn_clk), + .D(I_4943_0_a2_0_a2_0_a2_132), + .Q(com_cmm_bar0_reg_30_), + .CLR(com_cmm_rst_351) + ); + FDCE com_cmm_u_cmm_cfgspace_bar0_reg_29_ ( + .CE(com_cmm_u_cmm_cfgspace_bar0_reg56), + .C(NlwRenamedSig_OI_trn_clk), + .D(I_4948_0_a2_0_a2_0_a2_131), + .Q(com_cmm_bar0_reg_29_), + .CLR(com_cmm_rst_351) + ); + FDCE com_cmm_u_cmm_cfgspace_bar0_reg_28_ ( + .CE(com_cmm_u_cmm_cfgspace_bar0_reg56), + .C(NlwRenamedSig_OI_trn_clk), + .D(I_4953_0_a2_0_a2_0_a2_130), + .Q(com_cmm_bar0_reg_28_), + .CLR(com_cmm_rst_351) + ); + FDCE com_cmm_u_cmm_cfgspace_bar0_reg_27_ ( + .CE(com_cmm_u_cmm_cfgspace_bar0_reg56), + .C(NlwRenamedSig_OI_trn_clk), + .D(I_4958_0_a2_0_a2_0_a2_129), + .Q(com_cmm_bar0_reg_27_), + .CLR(com_cmm_rst_351) + ); + FDCE com_cmm_u_cmm_cfgspace_bar0_reg_26_ ( + .CE(com_cmm_u_cmm_cfgspace_bar0_reg56), + .C(NlwRenamedSig_OI_trn_clk), + .D(I_4963_0_a2_0_a2_0_a2_128), + .Q(com_cmm_bar0_reg_26_), + .CLR(com_cmm_rst_351) + ); + FDCE com_cmm_u_cmm_cfgspace_bar0_reg_25_ ( + .CE(com_cmm_u_cmm_cfgspace_bar0_reg56), + .C(NlwRenamedSig_OI_trn_clk), + .D(I_4968_0_a2_0_a2_0_a2_127), + .Q(com_cmm_bar0_reg_25_), + .CLR(com_cmm_rst_351) + ); + FDCE com_cmm_u_cmm_cfgspace_bar0_reg_24_ ( + .CE(com_cmm_u_cmm_cfgspace_bar0_reg56), + .C(NlwRenamedSig_OI_trn_clk), + .D(I_4973_0_a2_0_a2_0_a2_126), + .Q(com_cmm_bar0_reg_24_), + .CLR(com_cmm_rst_351) + ); + FDCE com_cmm_u_cmm_cfgspace_bar0_reg_23_ ( + .CE(com_cmm_u_cmm_cfgspace_bar0_reg44), + .C(NlwRenamedSig_OI_trn_clk), + .D(I_4978_0_a2_0_a2_0_a2_125), + .Q(com_cmm_bar0_reg_23_), + .CLR(com_cmm_rst_351) + ); + FDCE com_cmm_u_cmm_cfgspace_bar0_reg_22_ ( + .CE(com_cmm_u_cmm_cfgspace_bar0_reg44), + .C(NlwRenamedSig_OI_trn_clk), + .D(I_4983_0_a2_0_a2_0_a2_124), + .Q(com_cmm_bar0_reg_22_), + .CLR(com_cmm_rst_351) + ); + FDCE com_cmm_u_cmm_cfgspace_msi_laddr_1_21_ ( + .CE(com_cmm_u_cmm_cfgspace_msi_laddr40), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_cfg_wr_data_13_), + .Q(com_cmm_msi_laddr[21]), + .CLR(com_cmm_rst_351) + ); + FDCE com_cmm_u_cmm_cfgspace_msi_laddr_1_20_ ( + .CE(com_cmm_u_cmm_cfgspace_msi_laddr40), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_cfg_wr_data_12_), + .Q(com_cmm_msi_laddr[20]), + .CLR(com_cmm_rst_351) + ); + FDCE com_cmm_u_cmm_cfgspace_msi_laddr_1_19_ ( + .CE(com_cmm_u_cmm_cfgspace_msi_laddr40), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_cfg_wr_data_11_), + .Q(com_cmm_msi_laddr[19]), + .CLR(com_cmm_rst_351) + ); + FDCE com_cmm_u_cmm_cfgspace_msi_laddr_1_18_ ( + .CE(com_cmm_u_cmm_cfgspace_msi_laddr40), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_cfg_wr_data_10_), + .Q(com_cmm_msi_laddr[18]), + .CLR(com_cmm_rst_351) + ); + FDCE com_cmm_u_cmm_cfgspace_msi_laddr_1_17_ ( + .CE(com_cmm_u_cmm_cfgspace_msi_laddr40), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_cfg_wr_data_9_), + .Q(com_cmm_msi_laddr[17]), + .CLR(com_cmm_rst_351) + ); + FDCE com_cmm_u_cmm_cfgspace_msi_laddr_1_16_ ( + .CE(com_cmm_u_cmm_cfgspace_msi_laddr40), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_cfg_wr_data_8_), + .Q(com_cmm_msi_laddr[16]), + .CLR(com_cmm_rst_351) + ); + FDCE com_cmm_u_cmm_cfgspace_msi_laddr_1_15_ ( + .CE(com_cmm_u_cmm_cfgspace_msi_laddr28), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_cfg_wr_data_23_), + .Q(com_cmm_msi_laddr[15]), + .CLR(com_cmm_rst_351) + ); + FDCE com_cmm_u_cmm_cfgspace_msi_laddr_1_14_ ( + .CE(com_cmm_u_cmm_cfgspace_msi_laddr28), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_cfg_wr_data_22_), + .Q(com_cmm_msi_laddr[14]), + .CLR(com_cmm_rst_351) + ); + FDCE com_cmm_u_cmm_cfgspace_msi_laddr_1_13_ ( + .CE(com_cmm_u_cmm_cfgspace_msi_laddr28), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_cfg_wr_data_21_), + .Q(com_cmm_msi_laddr[13]), + .CLR(com_cmm_rst_351) + ); + FDCE com_cmm_u_cmm_cfgspace_msi_laddr_1_12_ ( + .CE(com_cmm_u_cmm_cfgspace_msi_laddr28), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_cfg_wr_data_20_), + .Q(com_cmm_msi_laddr[12]), + .CLR(com_cmm_rst_351) + ); + FDCE com_cmm_u_cmm_cfgspace_msi_laddr_1_11_ ( + .CE(com_cmm_u_cmm_cfgspace_msi_laddr28), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_cfg_wr_data_19_), + .Q(com_cmm_msi_laddr[11]), + .CLR(com_cmm_rst_351) + ); + FDCE com_cmm_u_cmm_cfgspace_msi_laddr_1_10_ ( + .CE(com_cmm_u_cmm_cfgspace_msi_laddr28), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_cfg_wr_data_18_), + .Q(com_cmm_msi_laddr[10]), + .CLR(com_cmm_rst_351) + ); + FDCE com_cmm_u_cmm_cfgspace_msi_laddr_1_9_ ( + .CE(com_cmm_u_cmm_cfgspace_msi_laddr28), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_cfg_wr_data_17_), + .Q(com_cmm_msi_laddr[9]), + .CLR(com_cmm_rst_351) + ); + FDCE com_cmm_u_cmm_cfgspace_msi_laddr_1_8_ ( + .CE(com_cmm_u_cmm_cfgspace_msi_laddr28), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_cfg_wr_data_16_), + .Q(com_cmm_msi_laddr[8]), + .CLR(com_cmm_rst_351) + ); + FDCE com_cmm_u_cmm_cfgspace_msi_laddr_1_7_ ( + .CE(com_cmm_u_cmm_cfgspace_msi_laddr16), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_cfg_wr_data_31_), + .Q(com_cmm_msi_laddr[7]), + .CLR(com_cmm_rst_351) + ); + FDCE com_cmm_u_cmm_cfgspace_msi_haddr_4_ ( + .CE(com_cmm_u_cmm_cfgspace_msi_haddr12), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_cfg_wr_data_28_), + .Q(com_cmm_msi_haddr[4]), + .CLR(com_cmm_rst_351) + ); + FDCE com_cmm_u_cmm_cfgspace_msi_haddr_3_ ( + .CE(com_cmm_u_cmm_cfgspace_msi_haddr12), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_cfg_wr_data[27]), + .Q(com_cmm_msi_haddr[3]), + .CLR(com_cmm_rst_351) + ); + FDCE com_cmm_u_cmm_cfgspace_msi_haddr_2_ ( + .CE(com_cmm_u_cmm_cfgspace_msi_haddr12), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_cfg_wr_data[26]), + .Q(com_cmm_msi_haddr[2]), + .CLR(com_cmm_rst_351) + ); + FDCE com_cmm_u_cmm_cfgspace_msi_haddr_1_ ( + .CE(com_cmm_u_cmm_cfgspace_msi_haddr12), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_cfg_wr_data[25]), + .Q(com_cmm_msi_haddr[1]), + .CLR(com_cmm_rst_351) + ); + FDCE com_cmm_u_cmm_cfgspace_msi_haddr_0_ ( + .CE(com_cmm_u_cmm_cfgspace_msi_haddr12), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_cfg_wr_data[24]), + .Q(com_cmm_msi_haddr[0]), + .CLR(com_cmm_rst_351) + ); + FDCE com_cmm_u_cmm_cfgspace_msi_laddr_1_31_ ( + .CE(com_cmm_u_cmm_cfgspace_msi_laddr51), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_cfg_wr_data_7_), + .Q(com_cmm_msi_laddr[31]), + .CLR(com_cmm_rst_351) + ); + FDCE com_cmm_u_cmm_cfgspace_msi_laddr_1_30_ ( + .CE(com_cmm_u_cmm_cfgspace_msi_laddr51), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_cfg_wr_data_6_), + .Q(com_cmm_msi_laddr[30]), + .CLR(com_cmm_rst_351) + ); + FDCE com_cmm_u_cmm_cfgspace_msi_laddr_1_29_ ( + .CE(com_cmm_u_cmm_cfgspace_msi_laddr51), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_cfg_wr_data_5_), + .Q(com_cmm_msi_laddr[29]), + .CLR(com_cmm_rst_351) + ); + FDCE com_cmm_u_cmm_cfgspace_msi_laddr_1_28_ ( + .CE(com_cmm_u_cmm_cfgspace_msi_laddr51), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_cfg_wr_data_4_), + .Q(com_cmm_msi_laddr[28]), + .CLR(com_cmm_rst_351) + ); + FDCE com_cmm_u_cmm_cfgspace_msi_laddr_1_27_ ( + .CE(com_cmm_u_cmm_cfgspace_msi_laddr51), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_cfg_wr_data_3_), + .Q(com_cmm_msi_laddr[27]), + .CLR(com_cmm_rst_351) + ); + FDCE com_cmm_u_cmm_cfgspace_msi_laddr_1_26_ ( + .CE(com_cmm_u_cmm_cfgspace_msi_laddr51), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_cfg_wr_data_2_), + .Q(com_cmm_msi_laddr[26]), + .CLR(com_cmm_rst_351) + ); + FDCE com_cmm_u_cmm_cfgspace_msi_laddr_1_25_ ( + .CE(com_cmm_u_cmm_cfgspace_msi_laddr51), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_cfg_wr_data_1_), + .Q(com_cmm_msi_laddr[25]), + .CLR(com_cmm_rst_351) + ); + FDCE com_cmm_u_cmm_cfgspace_msi_laddr_1_24_ ( + .CE(com_cmm_u_cmm_cfgspace_msi_laddr51), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_cfg_wr_data_0_), + .Q(com_cmm_msi_laddr[24]), + .CLR(com_cmm_rst_351) + ); + FDCE com_cmm_u_cmm_cfgspace_msi_laddr_1_23_ ( + .CE(com_cmm_u_cmm_cfgspace_msi_laddr40), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_cfg_wr_data_15_), + .Q(com_cmm_msi_laddr[23]), + .CLR(com_cmm_rst_351) + ); + FDCE com_cmm_u_cmm_cfgspace_msi_laddr_1_22_ ( + .CE(com_cmm_u_cmm_cfgspace_msi_laddr40), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_cfg_wr_data_14_), + .Q(com_cmm_msi_laddr[22]), + .CLR(com_cmm_rst_351) + ); + FDCE com_cmm_u_cmm_cfgspace_msi_haddr_19_ ( + .CE(com_cmm_u_cmm_cfgspace_msi_haddr35), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_cfg_wr_data_11_), + .Q(com_cmm_msi_haddr[19]), + .CLR(com_cmm_rst_351) + ); + FDCE com_cmm_u_cmm_cfgspace_msi_haddr_18_ ( + .CE(com_cmm_u_cmm_cfgspace_msi_haddr35), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_cfg_wr_data_10_), + .Q(com_cmm_msi_haddr[18]), + .CLR(com_cmm_rst_351) + ); + FDCE com_cmm_u_cmm_cfgspace_msi_haddr_17_ ( + .CE(com_cmm_u_cmm_cfgspace_msi_haddr35), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_cfg_wr_data_9_), + .Q(com_cmm_msi_haddr[17]), + .CLR(com_cmm_rst_351) + ); + FDCE com_cmm_u_cmm_cfgspace_msi_haddr_16_ ( + .CE(com_cmm_u_cmm_cfgspace_msi_haddr35), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_cfg_wr_data_8_), + .Q(com_cmm_msi_haddr[16]), + .CLR(com_cmm_rst_351) + ); + FDCE com_cmm_u_cmm_cfgspace_msi_haddr_15_ ( + .CE(com_cmm_u_cmm_cfgspace_msi_haddr23), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_cfg_wr_data_23_), + .Q(com_cmm_msi_haddr[15]), + .CLR(com_cmm_rst_351) + ); + FDCE com_cmm_u_cmm_cfgspace_msi_haddr_14_ ( + .CE(com_cmm_u_cmm_cfgspace_msi_haddr23), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_cfg_wr_data_22_), + .Q(com_cmm_msi_haddr[14]), + .CLR(com_cmm_rst_351) + ); + FDCE com_cmm_u_cmm_cfgspace_msi_haddr_13_ ( + .CE(com_cmm_u_cmm_cfgspace_msi_haddr23), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_cfg_wr_data_21_), + .Q(com_cmm_msi_haddr[13]), + .CLR(com_cmm_rst_351) + ); + FDCE com_cmm_u_cmm_cfgspace_msi_haddr_12_ ( + .CE(com_cmm_u_cmm_cfgspace_msi_haddr23), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_cfg_wr_data_20_), + .Q(com_cmm_msi_haddr[12]), + .CLR(com_cmm_rst_351) + ); + FDCE com_cmm_u_cmm_cfgspace_msi_haddr_11_ ( + .CE(com_cmm_u_cmm_cfgspace_msi_haddr23), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_cfg_wr_data_19_), + .Q(com_cmm_msi_haddr[11]), + .CLR(com_cmm_rst_351) + ); + FDCE com_cmm_u_cmm_cfgspace_msi_haddr_10_ ( + .CE(com_cmm_u_cmm_cfgspace_msi_haddr23), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_cfg_wr_data_18_), + .Q(com_cmm_msi_haddr[10]), + .CLR(com_cmm_rst_351) + ); + FDCE com_cmm_u_cmm_cfgspace_msi_haddr_9_ ( + .CE(com_cmm_u_cmm_cfgspace_msi_haddr23), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_cfg_wr_data_17_), + .Q(com_cmm_msi_haddr[9]), + .CLR(com_cmm_rst_351) + ); + FDCE com_cmm_u_cmm_cfgspace_msi_haddr_8_ ( + .CE(com_cmm_u_cmm_cfgspace_msi_haddr23), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_cfg_wr_data_16_), + .Q(com_cmm_msi_haddr[8]), + .CLR(com_cmm_rst_351) + ); + FDCE com_cmm_u_cmm_cfgspace_msi_haddr_7_ ( + .CE(com_cmm_u_cmm_cfgspace_msi_haddr12), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_cfg_wr_data_31_), + .Q(com_cmm_msi_haddr[7]), + .CLR(com_cmm_rst_351) + ); + FDCE com_cmm_u_cmm_cfgspace_msi_haddr_6_ ( + .CE(com_cmm_u_cmm_cfgspace_msi_haddr12), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_cfg_wr_data_30_), + .Q(com_cmm_msi_haddr[6]), + .CLR(com_cmm_rst_351) + ); + FDCE com_cmm_u_cmm_cfgspace_msi_haddr_5_ ( + .CE(com_cmm_u_cmm_cfgspace_msi_haddr12), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_cfg_wr_data_29_), + .Q(com_cmm_msi_haddr[5]), + .CLR(com_cmm_rst_351) + ); + FDCE com_cmm_u_cmm_cfgspace_msi_data_2_ ( + .CE(com_cmm_u_cmm_cfgspace_msi_data12), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_cfg_wr_data[26]), + .Q(com_cmm_msi_data[2]), + .CLR(com_cmm_rst_351) + ); + FDCE com_cmm_u_cmm_cfgspace_msi_data_1_ ( + .CE(com_cmm_u_cmm_cfgspace_msi_data12), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_cfg_wr_data[25]), + .Q(com_cmm_msi_data[1]), + .CLR(com_cmm_rst_351) + ); + FDCE com_cmm_u_cmm_cfgspace_msi_data_0_ ( + .CE(com_cmm_u_cmm_cfgspace_msi_data12), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_cfg_wr_data[24]), + .Q(com_cmm_msi_data[0]), + .CLR(com_cmm_rst_351) + ); + FDCE com_cmm_u_cmm_cfgspace_msi_haddr_31_ ( + .CE(com_cmm_u_cmm_cfgspace_msi_haddr46), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_cfg_wr_data_7_), + .Q(com_cmm_msi_haddr[31]), + .CLR(com_cmm_rst_351) + ); + FDCE com_cmm_u_cmm_cfgspace_msi_haddr_30_ ( + .CE(com_cmm_u_cmm_cfgspace_msi_haddr46), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_cfg_wr_data_6_), + .Q(com_cmm_msi_haddr[30]), + .CLR(com_cmm_rst_351) + ); + FDCE com_cmm_u_cmm_cfgspace_msi_haddr_29_ ( + .CE(com_cmm_u_cmm_cfgspace_msi_haddr46), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_cfg_wr_data_5_), + .Q(com_cmm_msi_haddr[29]), + .CLR(com_cmm_rst_351) + ); + FDCE com_cmm_u_cmm_cfgspace_msi_haddr_28_ ( + .CE(com_cmm_u_cmm_cfgspace_msi_haddr46), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_cfg_wr_data_4_), + .Q(com_cmm_msi_haddr[28]), + .CLR(com_cmm_rst_351) + ); + FDCE com_cmm_u_cmm_cfgspace_msi_haddr_27_ ( + .CE(com_cmm_u_cmm_cfgspace_msi_haddr46), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_cfg_wr_data_3_), + .Q(com_cmm_msi_haddr[27]), + .CLR(com_cmm_rst_351) + ); + FDCE com_cmm_u_cmm_cfgspace_msi_haddr_26_ ( + .CE(com_cmm_u_cmm_cfgspace_msi_haddr46), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_cfg_wr_data_2_), + .Q(com_cmm_msi_haddr[26]), + .CLR(com_cmm_rst_351) + ); + FDCE com_cmm_u_cmm_cfgspace_msi_haddr_25_ ( + .CE(com_cmm_u_cmm_cfgspace_msi_haddr46), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_cfg_wr_data_1_), + .Q(com_cmm_msi_haddr[25]), + .CLR(com_cmm_rst_351) + ); + FDCE com_cmm_u_cmm_cfgspace_msi_haddr_24_ ( + .CE(com_cmm_u_cmm_cfgspace_msi_haddr46), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_cfg_wr_data_0_), + .Q(com_cmm_msi_haddr[24]), + .CLR(com_cmm_rst_351) + ); + FDCE com_cmm_u_cmm_cfgspace_msi_haddr_23_ ( + .CE(com_cmm_u_cmm_cfgspace_msi_haddr35), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_cfg_wr_data_15_), + .Q(com_cmm_msi_haddr[23]), + .CLR(com_cmm_rst_351) + ); + FDCE com_cmm_u_cmm_cfgspace_msi_haddr_22_ ( + .CE(com_cmm_u_cmm_cfgspace_msi_haddr35), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_cfg_wr_data_14_), + .Q(com_cmm_msi_haddr[22]), + .CLR(com_cmm_rst_351) + ); + FDCE com_cmm_u_cmm_cfgspace_msi_haddr_21_ ( + .CE(com_cmm_u_cmm_cfgspace_msi_haddr35), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_cfg_wr_data_13_), + .Q(com_cmm_msi_haddr[21]), + .CLR(com_cmm_rst_351) + ); + FDCE com_cmm_u_cmm_cfgspace_msi_haddr_20_ ( + .CE(com_cmm_u_cmm_cfgspace_msi_haddr35), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_cfg_wr_data_12_), + .Q(com_cmm_msi_haddr[20]), + .CLR(com_cmm_rst_351) + ); + FDCE com_cmm_u_cmm_cfgspace_x_lcmd_1_4_ ( + .CE(com_cmm_u_cmm_cfgspace_x_lcmd22), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_cfg_wr_data[25]), + .Q(NlwRenamedSig_OI_cfg_lcommand_1_), + .CLR(com_cmm_rst_351) + ); + FDCE com_cmm_u_cmm_cfgspace_x_lcmd_1_3_ ( + .CE(com_cmm_u_cmm_cfgspace_x_lcmd22), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_cfg_wr_data[24]), + .Q(NlwRenamedSig_OI_cfg_lcommand_0_), + .CLR(com_cmm_rst_351) + ); + FDCE com_cmm_u_cmm_cfgspace_msi_data_15_ ( + .CE(com_cmm_u_cmm_cfgspace_msi_data22), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_cfg_wr_data_23_), + .Q(com_cmm_msi_data[15]), + .CLR(com_cmm_rst_351) + ); + FDCE com_cmm_u_cmm_cfgspace_msi_data_14_ ( + .CE(com_cmm_u_cmm_cfgspace_msi_data22), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_cfg_wr_data_22_), + .Q(com_cmm_msi_data[14]), + .CLR(com_cmm_rst_351) + ); + FDCE com_cmm_u_cmm_cfgspace_msi_data_13_ ( + .CE(com_cmm_u_cmm_cfgspace_msi_data22), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_cfg_wr_data_21_), + .Q(com_cmm_msi_data[13]), + .CLR(com_cmm_rst_351) + ); + FDCE com_cmm_u_cmm_cfgspace_msi_data_12_ ( + .CE(com_cmm_u_cmm_cfgspace_msi_data22), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_cfg_wr_data_20_), + .Q(com_cmm_msi_data[12]), + .CLR(com_cmm_rst_351) + ); + FDCE com_cmm_u_cmm_cfgspace_msi_data_11_ ( + .CE(com_cmm_u_cmm_cfgspace_msi_data22), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_cfg_wr_data_19_), + .Q(com_cmm_msi_data[11]), + .CLR(com_cmm_rst_351) + ); + FDCE com_cmm_u_cmm_cfgspace_msi_data_10_ ( + .CE(com_cmm_u_cmm_cfgspace_msi_data22), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_cfg_wr_data_18_), + .Q(com_cmm_msi_data[10]), + .CLR(com_cmm_rst_351) + ); + FDCE com_cmm_u_cmm_cfgspace_msi_data_9_ ( + .CE(com_cmm_u_cmm_cfgspace_msi_data22), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_cfg_wr_data_17_), + .Q(com_cmm_msi_data[9]), + .CLR(com_cmm_rst_351) + ); + FDCE com_cmm_u_cmm_cfgspace_msi_data_8_ ( + .CE(com_cmm_u_cmm_cfgspace_msi_data22), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_cfg_wr_data_16_), + .Q(com_cmm_msi_data[8]), + .CLR(com_cmm_rst_351) + ); + FDCE com_cmm_u_cmm_cfgspace_msi_data_7_ ( + .CE(com_cmm_u_cmm_cfgspace_msi_data12), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_cfg_wr_data_31_), + .Q(com_cmm_msi_data[7]), + .CLR(com_cmm_rst_351) + ); + FDCE com_cmm_u_cmm_cfgspace_msi_data_6_ ( + .CE(com_cmm_u_cmm_cfgspace_msi_data12), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_cfg_wr_data_30_), + .Q(com_cmm_msi_data[6]), + .CLR(com_cmm_rst_351) + ); + FDCE com_cmm_u_cmm_cfgspace_msi_data_5_ ( + .CE(com_cmm_u_cmm_cfgspace_msi_data12), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_cfg_wr_data_29_), + .Q(com_cmm_msi_data[5]), + .CLR(com_cmm_rst_351) + ); + FDCE com_cmm_u_cmm_cfgspace_msi_data_4_ ( + .CE(com_cmm_u_cmm_cfgspace_msi_data12), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_cfg_wr_data_28_), + .Q(com_cmm_msi_data[4]), + .CLR(com_cmm_rst_351) + ); + FDCE com_cmm_u_cmm_cfgspace_msi_data_3_ ( + .CE(com_cmm_u_cmm_cfgspace_msi_data12), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_cfg_wr_data[27]), + .Q(com_cmm_msi_data[3]), + .CLR(com_cmm_rst_351) + ); + FDCE com_cmm_u_cmm_cfgspace_command_1_10_ ( + .CE(com_cmm_u_cmm_cfgspace_command93), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_cfg_wr_data_18_), + .Q(NlwRenamedSig_OI_cfg_command_10_), + .CLR(com_cmm_rst_351) + ); + FDCE com_cmm_u_cmm_cfgspace_command_1_9_ ( + .CE(com_cmm_u_cmm_cfgspace_command93), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_cfg_wr_data_16_), + .Q(NlwRenamedSig_OI_cfg_command_8_), + .CLR(com_cmm_rst_351) + ); + FDCE com_cmm_u_cmm_cfgspace_command_1_8_ ( + .CE(com_cmm_u_cmm_cfgspace_command67), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_cfg_wr_data_30_), + .Q(NlwRenamedSig_OI_cfg_command_6_), + .CLR(com_cmm_rst_351) + ); + FDCE com_cmm_u_cmm_cfgspace_command_1_7_ ( + .CE(com_cmm_u_cmm_cfgspace_command67), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_cfg_wr_data[26]), + .Q(NlwRenamedSig_OI_cfg_command_2_), + .CLR(com_cmm_rst_351) + ); + FDCE com_cmm_u_cmm_cfgspace_command_1_6_ ( + .CE(com_cmm_u_cmm_cfgspace_command67), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_cfg_wr_data[25]), + .Q(NlwRenamedSig_OI_cfg_command_1_), + .CLR(com_cmm_rst_351) + ); + FDCE com_cmm_u_cmm_cfgspace_command_1_5_ ( + .CE(com_cmm_u_cmm_cfgspace_command67), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_cfg_wr_data[24]), + .Q(NlwRenamedSig_OI_cfg_command_0_), + .CLR(com_cmm_rst_351) + ); + FDCE com_cmm_u_cmm_cfgspace_x_lcmd_1_7_ ( + .CE(com_cmm_u_cmm_cfgspace_x_lcmd22), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_cfg_wr_data_31_), + .Q(NlwRenamedSig_OI_cfg_lcommand_7_), + .CLR(com_cmm_rst_351) + ); + FDCE com_cmm_u_cmm_cfgspace_x_lcmd_1_6_ ( + .CE(com_cmm_u_cmm_cfgspace_x_lcmd22), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_cfg_wr_data_30_), + .Q(NlwRenamedSig_OI_cfg_lcommand_6_), + .CLR(com_cmm_rst_351) + ); + FDCE com_cmm_u_cmm_cfgspace_x_lcmd_1_5_ ( + .CE(com_cmm_u_cmm_cfgspace_x_lcmd22), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_cfg_wr_data[27]), + .Q(NlwRenamedSig_OI_cfg_lcommand_3_), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_cfgspace_x_dcap_10_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(cfg_cfg_6102[378]), + .Q(com_cmm_u_cmm_cfgspace_x_dcap[10]), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_cfgspace_x_dcap_9_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(cfg_cfg_6102[377]), + .Q(com_cmm_u_cmm_cfgspace_x_dcap[9]), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_cfgspace_x_dcap_8_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(cfg_cfg_6102[376]), + .Q(com_cmm_u_cmm_cfgspace_x_dcap[8]), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_cfgspace_x_dcap_7_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(cfg_cfg_6102[375]), + .Q(com_cmm_u_cmm_cfgspace_x_dcap[7]), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_cfgspace_x_dcap_6_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(cfg_cfg_6102[374]), + .Q(com_cmm_u_cmm_cfgspace_x_dcap[6]), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_cfgspace_x_dcap_5_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(cfg_cfg_6102[373]), + .Q(com_cmm_u_cmm_cfgspace_x_dcap[5]), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_cfgspace_x_dcap_4_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(cfg_cfg_6102[372]), + .Q(com_cmm_u_cmm_cfgspace_x_dcap[4]), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_cfgspace_x_dcap_3_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(cfg_cfg_6102[371]), + .Q(com_cmm_u_cmm_cfgspace_x_dcap[3]), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_cfgspace_x_dcap_2_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(cfg_cfg_6102[370]), + .Q(com_cmm_u_cmm_cfgspace_x_dcap[2]), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_cfgspace_x_dcap_1_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(cfg_cfg_6102[369]), + .Q(com_cmm_u_cmm_cfgspace_x_dcap[1]), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_cfgspace_x_dcap_0_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(cfg_cfg_6102[368]), + .Q(com_cmm_u_cmm_cfgspace_x_dcap[0]), + .CLR(com_cmm_rst_351) + ); + FDCE com_cmm_u_cmm_cfgspace_x_dcap_25_ ( + .CE(com_cmmt_rpm_set_slot_pwr), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmmt_rpm_set_slot_pwr_data[7]), + .Q(com_cmm_u_cmm_cfgspace_x_dcap[25]), + .CLR(com_cmm_rst_351) + ); + FDCE com_cmm_u_cmm_cfgspace_x_dcap_24_ ( + .CE(com_cmmt_rpm_set_slot_pwr), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmmt_rpm_set_slot_pwr_data[6]), + .Q(com_cmm_u_cmm_cfgspace_x_dcap[24]), + .CLR(com_cmm_rst_351) + ); + FDCE com_cmm_u_cmm_cfgspace_x_dcap_23_ ( + .CE(com_cmmt_rpm_set_slot_pwr), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmmt_rpm_set_slot_pwr_data[5]), + .Q(com_cmm_u_cmm_cfgspace_x_dcap[23]), + .CLR(com_cmm_rst_351) + ); + FDCE com_cmm_u_cmm_cfgspace_x_dcap_22_ ( + .CE(com_cmmt_rpm_set_slot_pwr), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmmt_rpm_set_slot_pwr_data[4]), + .Q(com_cmm_u_cmm_cfgspace_x_dcap[22]), + .CLR(com_cmm_rst_351) + ); + FDCE com_cmm_u_cmm_cfgspace_x_dcap_21_ ( + .CE(com_cmmt_rpm_set_slot_pwr), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmmt_rpm_set_slot_pwr_data[3]), + .Q(com_cmm_u_cmm_cfgspace_x_dcap[21]), + .CLR(com_cmm_rst_351) + ); + FDCE com_cmm_u_cmm_cfgspace_x_dcap_20_ ( + .CE(com_cmmt_rpm_set_slot_pwr), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmmt_rpm_set_slot_pwr_data[2]), + .Q(com_cmm_u_cmm_cfgspace_x_dcap[20]), + .CLR(com_cmm_rst_351) + ); + FDCE com_cmm_u_cmm_cfgspace_x_dcap_19_ ( + .CE(com_cmmt_rpm_set_slot_pwr), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmmt_rpm_set_slot_pwr_data[1]), + .Q(com_cmm_u_cmm_cfgspace_x_dcap[19]), + .CLR(com_cmm_rst_351) + ); + FDCE com_cmm_u_cmm_cfgspace_x_dcap_18_ ( + .CE(com_cmmt_rpm_set_slot_pwr), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmmt_rpm_set_slot_pwr_data[0]), + .Q(com_cmm_u_cmm_cfgspace_x_dcap[18]), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_cfgspace_x_dcap_17_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(cfg_cfg_6102[385]), + .Q(com_cmm_u_cmm_cfgspace_x_dcap[17]), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_cfgspace_x_dcap_16_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(cfg_cfg_6102[384]), + .Q(com_cmm_u_cmm_cfgspace_x_dcap[16]), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_cfgspace_x_dcap_15_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(cfg_cfg_6102[383]), + .Q(com_cmm_u_cmm_cfgspace_x_dcap[15]), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_cfgspace_x_dcap_14_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(cfg_cfg_6102[382]), + .Q(com_cmm_u_cmm_cfgspace_x_dcap[14]), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_cfgspace_x_dcap_13_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(cfg_cfg_6102[381]), + .Q(com_cmm_u_cmm_cfgspace_x_dcap[13]), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_cfgspace_x_dcap_12_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(cfg_cfg_6102[380]), + .Q(com_cmm_u_cmm_cfgspace_x_dcap[12]), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_cfgspace_x_dcap_11_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(cfg_cfg_6102[379]), + .Q(com_cmm_u_cmm_cfgspace_x_dcap[11]), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_cfgspace_x_dcap_31_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(cfg_cfg_6102[399]), + .Q(com_cmm_u_cmm_cfgspace_x_dcap[31]), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_cfgspace_x_dcap_30_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(cfg_cfg_6102[398]), + .Q(com_cmm_u_cmm_cfgspace_x_dcap[30]), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_cfgspace_x_dcap_29_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(cfg_cfg_6102[397]), + .Q(com_cmm_u_cmm_cfgspace_x_dcap[29]), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_cfgspace_x_dcap_28_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(cfg_cfg_6102[396]), + .Q(com_cmm_u_cmm_cfgspace_x_dcap[28]), + .CLR(com_cmm_rst_351) + ); + FDCE com_cmm_u_cmm_cfgspace_x_dcap_27_ ( + .CE(com_cmmt_rpm_set_slot_pwr), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmmt_rpm_set_slot_pwr_data[9]), + .Q(com_cmm_u_cmm_cfgspace_x_dcap[27]), + .CLR(com_cmm_rst_351) + ); + FDCE com_cmm_u_cmm_cfgspace_x_dcap_26_ ( + .CE(com_cmmt_rpm_set_slot_pwr), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmmt_rpm_set_slot_pwr_data[8]), + .Q(com_cmm_u_cmm_cfgspace_x_dcap[26]), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_cfgspace_x_lsts_1_2_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_cfgspace_x_lcap[0]), + .Q(NlwRenamedSig_OI_cfg_lstatus_0_), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_cfgspace_set_negotiatedwidth_2_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(cmmp_negotiated_width_0[0]), + .Q(com_cmm_u_cmm_cfgspace_set_negotiatedwidth_2__5806), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_cfgspace_set_negotiatedwidth_0_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(cmmp_negotiated_width_1[0]), + .Q(com_cmm_u_cmm_cfgspace_set_negotiatedwidth_0__5807), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_cfgspace_set_max_width_2_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_cfgspace_VCC_5805), + .Q(com_cmm_u_cmm_cfgspace_x_lcap[0]), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_cfgspace_x_lsts_1_12_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(cfg_cfg_6102[504]), + .Q(NlwRenamedSig_OI_cfg_lstatus_12_), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_cfgspace_x_lsts_1_8_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_cfgspace_set_negotiatedwidth_2__5806), + .Q(NlwRenamedSig_OI_cfg_lstatus_6_), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_cfgspace_x_lsts_1_6_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_cfgspace_set_negotiatedwidth_0__5807), + .Q(NlwRenamedSig_OI_cfg_lstatus_4_), + .CLR(com_cmm_rst_351) + ); + FDCE com_cmm_u_cmm_cfgspace_cache_line_7_ ( + .CE(com_cmm_u_cmm_cfgspace_cache_line8), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_tlm2cfg_wrdata_7_), + .Q(com_cmm_u_cmm_cfgspace_cache_line[7]), + .CLR(com_cmm_rst_351) + ); + FDCE com_cmm_u_cmm_cfgspace_cache_line_6_ ( + .CE(com_cmm_u_cmm_cfgspace_cache_line8), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_tlm2cfg_wrdata_6_), + .Q(com_cmm_u_cmm_cfgspace_cache_line[6]), + .CLR(com_cmm_rst_351) + ); + FDCE com_cmm_u_cmm_cfgspace_cache_line_5_ ( + .CE(com_cmm_u_cmm_cfgspace_cache_line8), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_tlm2cfg_wrdata_5_), + .Q(com_cmm_u_cmm_cfgspace_cache_line[5]), + .CLR(com_cmm_rst_351) + ); + FDCE com_cmm_u_cmm_cfgspace_cache_line_4_ ( + .CE(com_cmm_u_cmm_cfgspace_cache_line8), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_tlm2cfg_wrdata_4_), + .Q(com_cmm_u_cmm_cfgspace_cache_line[4]), + .CLR(com_cmm_rst_351) + ); + FDCE com_cmm_u_cmm_cfgspace_cache_line_3_ ( + .CE(com_cmm_u_cmm_cfgspace_cache_line8), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_tlm2cfg_wrdata_3_), + .Q(com_cmm_u_cmm_cfgspace_cache_line[3]), + .CLR(com_cmm_rst_351) + ); + FDCE com_cmm_u_cmm_cfgspace_cache_line_2_ ( + .CE(com_cmm_u_cmm_cfgspace_cache_line8), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_tlm2cfg_wrdata_2_), + .Q(com_cmm_u_cmm_cfgspace_cache_line[2]), + .CLR(com_cmm_rst_351) + ); + FDCE com_cmm_u_cmm_cfgspace_cache_line_1_ ( + .CE(com_cmm_u_cmm_cfgspace_cache_line8), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_N_33410_i_0), + .Q(com_cmm_u_cmm_cfgspace_cache_line[1]), + .CLR(com_cmm_rst_351) + ); + FDCE com_cmm_u_cmm_cfgspace_cache_line_0_ ( + .CE(com_cmm_u_cmm_cfgspace_cache_line8), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_N_33408_i_0), + .Q(com_cmm_u_cmm_cfgspace_cache_line[0]), + .CLR(com_cmm_rst_351) + ); + FDPE com_cmm_u_cmm_cfgspace_int_line_7_ ( + .PRE(com_cmm_rst_351), + .CE(com_cmm_u_cmm_cfgspace_int_line8), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_tlm2cfg_wrdata_7_), + .Q(com_cmm_u_cmm_cfgspace_int_line[7]) + ); + FDPE com_cmm_u_cmm_cfgspace_int_line_6_ ( + .PRE(com_cmm_rst_351), + .CE(com_cmm_u_cmm_cfgspace_int_line8), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_tlm2cfg_wrdata_6_), + .Q(com_cmm_u_cmm_cfgspace_int_line[6]) + ); + FDPE com_cmm_u_cmm_cfgspace_int_line_5_ ( + .PRE(com_cmm_rst_351), + .CE(com_cmm_u_cmm_cfgspace_int_line8), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_tlm2cfg_wrdata_5_), + .Q(com_cmm_u_cmm_cfgspace_int_line[5]) + ); + FDPE com_cmm_u_cmm_cfgspace_int_line_4_ ( + .PRE(com_cmm_rst_351), + .CE(com_cmm_u_cmm_cfgspace_int_line8), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_tlm2cfg_wrdata_4_), + .Q(com_cmm_u_cmm_cfgspace_int_line[4]) + ); + FDPE com_cmm_u_cmm_cfgspace_int_line_3_ ( + .PRE(com_cmm_rst_351), + .CE(com_cmm_u_cmm_cfgspace_int_line8), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_tlm2cfg_wrdata_3_), + .Q(com_cmm_u_cmm_cfgspace_int_line[3]) + ); + FDPE com_cmm_u_cmm_cfgspace_int_line_2_ ( + .PRE(com_cmm_rst_351), + .CE(com_cmm_u_cmm_cfgspace_int_line8), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_tlm2cfg_wrdata_2_), + .Q(com_cmm_u_cmm_cfgspace_int_line[2]) + ); + FDPE com_cmm_u_cmm_cfgspace_int_line_1_ ( + .PRE(com_cmm_rst_351), + .CE(com_cmm_u_cmm_cfgspace_int_line8), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_N_33410_i_0), + .Q(com_cmm_u_cmm_cfgspace_int_line[1]) + ); + FDPE com_cmm_u_cmm_cfgspace_int_line_0_ ( + .PRE(com_cmm_rst_351), + .CE(com_cmm_u_cmm_cfgspace_int_line8), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_N_33408_i_0), + .Q(com_cmm_u_cmm_cfgspace_int_line[0]) + ); + FDCE com_cmm_u_cmm_cfgspace_msi_control_1_0_ ( + .CE(com_cmm_u_cmm_cfgspace_msi_control27), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_tlm2cfg_wrdata_16_), + .Q(com_cmm_msi_control_1[0]), + .CLR(com_cmm_rst_351) + ); + FDCE com_cmm_u_cmm_cfgspace_xrom_reg_1_0_ ( + .CE(com_cmm_u_cmm_cfgspace_xrom_reg_0_sqmuxa), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_N_33408_i_0), + .Q(com_cmm_xrom_reg_0_), + .CLR(com_cmm_rst_351) + ); + FDCE com_cmm_u_cmm_cfgspace_xrom_reg_1_31_ ( + .CE(cfg_cfg_6102[320]), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_cfgspace_N_86265_i), + .Q(com_cmm_xrom_reg_31_), + .CLR(com_cmm_rst_351) + ); + FDCE com_cmm_u_cmm_cfgspace_xrom_reg_1_30_ ( + .CE(cfg_cfg_6102[320]), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_cfgspace_N_86264_i), + .Q(com_cmm_xrom_reg_30_), + .CLR(com_cmm_rst_351) + ); + FDCE com_cmm_u_cmm_cfgspace_xrom_reg_1_29_ ( + .CE(cfg_cfg_6102[320]), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_cfgspace_N_86263_i), + .Q(com_cmm_xrom_reg_29_), + .CLR(com_cmm_rst_351) + ); + FDCE com_cmm_u_cmm_cfgspace_xrom_reg_1_28_ ( + .CE(cfg_cfg_6102[320]), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_cfgspace_N_86262_i), + .Q(com_cmm_xrom_reg_28_), + .CLR(com_cmm_rst_351) + ); + FDCE com_cmm_u_cmm_cfgspace_xrom_reg_1_27_ ( + .CE(cfg_cfg_6102[320]), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_cfgspace_N_86261_i), + .Q(com_cmm_xrom_reg_27_), + .CLR(com_cmm_rst_351) + ); + FDCE com_cmm_u_cmm_cfgspace_xrom_reg_1_26_ ( + .CE(cfg_cfg_6102[320]), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_cfgspace_N_86260_i), + .Q(com_cmm_xrom_reg_26_), + .CLR(com_cmm_rst_351) + ); + FDCE com_cmm_u_cmm_cfgspace_xrom_reg_1_25_ ( + .CE(cfg_cfg_6102[320]), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_cfgspace_N_86259_i), + .Q(com_cmm_xrom_reg_25_), + .CLR(com_cmm_rst_351) + ); + FDCE com_cmm_u_cmm_cfgspace_xrom_reg_1_24_ ( + .CE(cfg_cfg_6102[320]), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_cfgspace_N_86258_i), + .Q(com_cmm_xrom_reg_24_), + .CLR(com_cmm_rst_351) + ); + FDCE com_cmm_u_cmm_cfgspace_xrom_reg_1_23_ ( + .CE(cfg_cfg_6102[320]), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_cfgspace_N_86257_i), + .Q(com_cmm_xrom_reg_23_), + .CLR(com_cmm_rst_351) + ); + FDCE com_cmm_u_cmm_cfgspace_xrom_reg_1_22_ ( + .CE(cfg_cfg_6102[320]), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_cfgspace_N_86256_i), + .Q(com_cmm_xrom_reg_22_), + .CLR(com_cmm_rst_351) + ); + FDCE com_cmm_u_cmm_cfgspace_xrom_reg_1_21_ ( + .CE(cfg_cfg_6102[320]), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_cfgspace_N_86255_i), + .Q(com_cmm_xrom_reg_21_), + .CLR(com_cmm_rst_351) + ); + FDCE com_cmm_u_cmm_cfgspace_xrom_reg_1_20_ ( + .CE(cfg_cfg_6102[320]), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_cfgspace_N_86254_i), + .Q(com_cmm_xrom_reg_20_), + .CLR(com_cmm_rst_351) + ); + FDCE com_cmm_u_cmm_cfgspace_xrom_reg_1_19_ ( + .CE(cfg_cfg_6102[320]), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_cfgspace_N_86253_i), + .Q(com_cmm_xrom_reg_19_), + .CLR(com_cmm_rst_351) + ); + FDCE com_cmm_u_cmm_cfgspace_xrom_reg_1_18_ ( + .CE(cfg_cfg_6102[320]), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_cfgspace_N_86252_i), + .Q(com_cmm_xrom_reg_18_), + .CLR(com_cmm_rst_351) + ); + FDCE com_cmm_u_cmm_cfgspace_xrom_reg_1_17_ ( + .CE(cfg_cfg_6102[320]), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_cfgspace_N_86251_i), + .Q(com_cmm_xrom_reg_17_), + .CLR(com_cmm_rst_351) + ); + FDCE com_cmm_u_cmm_cfgspace_xrom_reg_1_16_ ( + .CE(cfg_cfg_6102[320]), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_cfgspace_N_86250_i), + .Q(com_cmm_xrom_reg_16_), + .CLR(com_cmm_rst_351) + ); + FDCE com_cmm_u_cmm_cfgspace_xrom_reg_1_15_ ( + .CE(cfg_cfg_6102[320]), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_cfgspace_N_86249_i), + .Q(com_cmm_xrom_reg_15_), + .CLR(com_cmm_rst_351) + ); + FDCE com_cmm_u_cmm_cfgspace_xrom_reg_1_14_ ( + .CE(cfg_cfg_6102[320]), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_cfgspace_N_86248_i), + .Q(com_cmm_xrom_reg_14_), + .CLR(com_cmm_rst_351) + ); + FDCE com_cmm_u_cmm_cfgspace_xrom_reg_1_13_ ( + .CE(cfg_cfg_6102[320]), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_cfgspace_N_86247_i), + .Q(com_cmm_xrom_reg_13_), + .CLR(com_cmm_rst_351) + ); + FDCE com_cmm_u_cmm_cfgspace_xrom_reg_1_12_ ( + .CE(cfg_cfg_6102[320]), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_cfgspace_N_86246_i), + .Q(com_cmm_xrom_reg_12_), + .CLR(com_cmm_rst_351) + ); + FDCE com_cmm_u_cmm_cfgspace_xrom_reg_1_11_ ( + .CE(cfg_cfg_6102[320]), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_cfgspace_N_86245_i), + .Q(com_cmm_xrom_reg_11_), + .CLR(com_cmm_rst_351) + ); + INV com_cmm_u_cmm_cfgspace_N_3206_i_i ( + .I(NlwRenamedSig_OI_cfg_lstatus_6_), + .O(com_N_3206_i_i) + ); + INV com_cmm_u_cmm_cfgspace_cfg2ulm_valid_i ( + .I(com_cmm_u_cmm_cfgspace_cfg2ulm_valid), + .O(cfg_rd_wr_done_n) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_01_7_0_am_0_3_.INIT = 8'h38; + LUT3 com_cmm_u_cmm_cfgspace_low_addr_01_7_0_am_0_3_ ( + .I0(com_cmm_bar5_reg[3]), + .I1(com_cmm_u_cmm_cfgspace_sel_encodex_1[1]), + .I2(com_cmm_u_cmm_cfgspace_sel_encodex_1[2]), + .O(com_cmm_u_cmm_cfgspace_low_addr_01_7_0_am_0[3]) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_00_i_0_0_30_.INIT = 16'hC400; + LUT4_L com_cmm_u_cmm_cfgspace_low_addr_00_i_0_0_30_ ( + .I0(com_cmm_u_cmm_cfgspace_N_61330), + .I1(com_cmm_u_cmm_cfgspace_low_addr_00_i_0_0_30_39348_5809), + .I2(com_cmm_bar0_reg_30_), + .I3(com_cmm_u_cmm_cfgspace_low_addr_00_i_0_0_1_30__5808), + .LO(com_cmm_u_cmm_cfgspace_N_33956_i) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_00_i_0_0_26_.INIT = 16'hC400; + LUT4_L com_cmm_u_cmm_cfgspace_low_addr_00_i_0_0_26_ ( + .I0(com_cmm_u_cmm_cfgspace_N_61330), + .I1(com_cmm_u_cmm_cfgspace_low_addr_00_i_0_0_26_39333_5811), + .I2(com_cmm_bar0_reg_26_), + .I3(com_cmm_u_cmm_cfgspace_low_addr_00_i_0_0_1_26__5810), + .LO(com_cmm_u_cmm_cfgspace_N_35672_i) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_00_i_0_0_25_.INIT = 16'hC400; + LUT4_L com_cmm_u_cmm_cfgspace_low_addr_00_i_0_0_25_ ( + .I0(com_cmm_u_cmm_cfgspace_N_61330), + .I1(com_cmm_u_cmm_cfgspace_low_addr_00_i_0_0_25_39338_5813), + .I2(com_cmm_bar0_reg_25_), + .I3(com_cmm_u_cmm_cfgspace_low_addr_00_i_0_0_1_25__5812), + .LO(com_cmm_u_cmm_cfgspace_N_35670_i) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_00_i_0_24_.INIT = 16'hC400; + LUT4_L com_cmm_u_cmm_cfgspace_low_addr_00_i_0_24_ ( + .I0(com_cmm_u_cmm_cfgspace_N_61330), + .I1(com_cmm_u_cmm_cfgspace_low_addr_00_i_0_24_39314_5815), + .I2(com_cmm_bar0_reg_24_), + .I3(com_cmm_u_cmm_cfgspace_low_addr_00_i_0_1_24__5814), + .LO(com_cmm_u_cmm_cfgspace_N_40027_i) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_00_i_0_0_23_.INIT = 16'hC400; + LUT4_L com_cmm_u_cmm_cfgspace_low_addr_00_i_0_0_23_ ( + .I0(com_cmm_u_cmm_cfgspace_N_61330), + .I1(com_cmm_u_cmm_cfgspace_low_addr_00_i_0_0_23_39343_5817), + .I2(com_cmm_bar0_reg_23_), + .I3(com_cmm_u_cmm_cfgspace_low_addr_00_i_0_0_1_23__5816), + .LO(com_cmm_u_cmm_cfgspace_N_35668_i) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_00_i_0_22_.INIT = 16'hC400; + LUT4_L com_cmm_u_cmm_cfgspace_low_addr_00_i_0_22_ ( + .I0(com_cmm_u_cmm_cfgspace_N_61330), + .I1(com_cmm_u_cmm_cfgspace_low_addr_00_i_0_22_39319_5819), + .I2(com_cmm_bar0_reg_22_), + .I3(com_cmm_u_cmm_cfgspace_low_addr_00_i_0_1_22__5818), + .LO(com_cmm_u_cmm_cfgspace_N_40025_i) + ); + defparam com_cmm_u_cmm_cfgspace_low_addr_00_i_0_20_.INIT = 16'hC400; + LUT4_L com_cmm_u_cmm_cfgspace_low_addr_00_i_0_20_ ( + .I0(com_cmm_u_cmm_cfgspace_N_61330), + .I1(com_cmm_u_cmm_cfgspace_low_addr_00_i_0_20_39324_5821), + .I2(com_cmm_bar0_reg_20_), + .I3(com_cmm_u_cmm_cfgspace_low_addr_00_i_0_1_20__5820), + .LO(com_cmm_u_cmm_cfgspace_N_40022_i) + ); + defparam com_cmm_u_cmm_errman_reg_detectedcorrectable_3_i_0_0_0_a2_1.INIT = 4'h4; + LUT2 com_cmm_u_cmm_errman_reg_detectedcorrectable_3_i_0_0_0_a2_1 ( + .I0(com_replay_timer_expire), + .I1(com_replay_timer_expire_pre), + .O(com_replay_vld) + ); + defparam com_cmm_u_cmm_errman_reg_detectedcorrectable_3_i_0_0_0_a2_0.INIT = 4'h8; + LUT2 com_cmm_u_cmm_errman_reg_detectedcorrectable_3_i_0_0_0_a2_0 ( + .I0(cmmp_receiver_err), + .I1(plm_link_up_1), + .O(com_cmm_u_cmm_errman_reg_detectedcorrectable_3_i_0_0_0_a2_0_5827) + ); + defparam com_cmm_u_cmm_errman_reg_detectedcorrectable_3_i_0_0_0_o3.INIT = 4'h1; + LUT2 com_cmm_u_cmm_errman_reg_detectedcorrectable_3_i_0_0_0_o3 ( + .I0(com_link_status[3]), + .I1(com_link_status[4]), + .O(com_N_56127_i) + ); + defparam com_cmm_u_cmm_errman_cfg_is_np_and_cpl_abort_0_a2_0_a2.INIT = 4'h4; + LUT2 com_cmm_u_cmm_errman_cfg_is_np_and_cpl_abort_0_a2_0_a2 ( + .I0(cfg_err_cpl_abort_n), + .I1(cfg_err_posted_n), + .O(com_cmm_u_cmm_errman_cfg_is_np_and_cpl_abort) + ); + defparam com_cmm_u_cmm_errman_ns_fsm_0_i_0_a2_0_1_1_.INIT = 4'h1; + LUT2 com_cmm_u_cmm_errman_ns_fsm_0_i_0_a2_0_1_1_ ( + .I0(com_cmm_u_cmm_errman_cs_fsm[3]), + .I1(com_cmm_u_cmm_errman_send_cplu_5845), + .O(com_cmm_u_cmm_errman_N_58735_1) + ); + defparam com_cmm_u_cmm_errman_ns_fsm_0_i_0_o3_0_2_.INIT = 4'h8; + LUT2 com_cmm_u_cmm_errman_ns_fsm_0_i_0_o3_0_2_ ( + .I0(com_cmm_u_cmm_errman_cs_fsm[0]), + .I1(com_cmm_u_cmm_errman_cs_fsm[1]), + .O(com_cmm_u_cmm_errman_N_56493_i) + ); + defparam com_cmm_u_cmm_errman_decr_cplt_0_o3.INIT = 4'h8; + LUT2 com_cmm_u_cmm_errman_decr_cplt_0_o3 ( + .I0(com_cmm_gnt_errman), + .I1(com_cmm_u_cmm_errman_cs_is_cplt_5836), + .O(com_cmm_u_cmm_errman_N_56322_i) + ); + defparam com_cmm_u_cmm_errman_ns_fsm_0_i_0_o3_0_1_.INIT = 4'h1; + LUT2 com_cmm_u_cmm_errman_ns_fsm_0_i_0_o3_0_1_ ( + .I0(com_cmm_u_cmm_errman_send_cplt_5847), + .I1(com_cmm_u_cmm_errman_send_ftl_5843), + .O(com_cmm_u_cmm_errman_N_56317_i) + ); + defparam com_cmm_u_cmm_errman_decr_ftl_0_o3.INIT = 4'h8; + LUT2 com_cmm_u_cmm_errman_decr_ftl_0_o3 ( + .I0(com_cmm_gnt_errman), + .I1(com_cmm_u_cmm_errman_cs_is_ftl_5834), + .O(N_56022_i) + ); + defparam com_cmm_u_cmm_errman_ns_fsm_0_i_0_o3_1_.INIT = 4'h1; + LUT2 com_cmm_u_cmm_errman_ns_fsm_0_i_0_o3_1_ ( + .I0(com_cmm_u_cmm_errman_cs_fsm[0]), + .I1(com_cmm_u_cmm_errman_cs_fsm[2]), + .O(com_cmm_u_cmm_errman_N_55917_i) + ); + defparam com_cmm_u_cmm_errman_cor_num_axb0.INIT = 4'h9; + LUT2 com_cmm_u_cmm_errman_cor_num_axb0 ( + .I0(com_cmm_u_cmm_errman_cor_num_int[0]), + .I1(com_cmm_u_cmm_errman_reg_decr_cor), + .O(com_cmm_u_cmm_errman_cor_num_i[0]) + ); + defparam com_cmm_u_cmm_errman_reg_detectedcorrectable_3_i_0_0_0_a2.INIT = 8'h51; + LUT3 com_cmm_u_cmm_errman_reg_detectedcorrectable_3_i_0_0_0_a2 ( + .I0(com_N_56127_i), + .I1(com_rx_tlp_range_err_n), + .I2(com_rx_tlp_tsn_err_crc_or_ferr), + .O(com_cmm_u_cmm_errman_reg_detectedcorrectable_3_i_0_0_0_a2_5829) + ); + defparam com_cmm_u_cmm_errman_un1_cmmt_err_tlp_ur_i_0_a2.INIT = 8'h15; + LUT3 com_cmm_u_cmm_errman_un1_cmmt_err_tlp_ur_i_0_a2 ( + .I0(NlwRenamedSig_OI_cfg_command_8_), + .I1(NlwRenamedSig_OI_cfg_dcommand[1]), + .I2(NlwRenamedSig_OI_cfg_dcommand[3]), + .O(com_cmm_u_cmm_errman_N_58592) + ); + defparam com_cmm_u_cmm_errman_request_9_i_i_i_a2_0_.INIT = 8'h10; + LUT3 com_cmm_u_cmm_errman_request_9_i_i_i_a2_0_ ( + .I0(com_cmm_u_cmm_errman_cs_fsm[0]), + .I1(com_cmm_u_cmm_errman_cs_fsm[1]), + .I2(com_cmm_u_cmm_errman_cs_fsm[2]), + .O(com_cmm_u_cmm_errman_request_data31) + ); + defparam com_cmm_u_cmm_errman_request_data28_0_a3.INIT = 8'h02; + LUT3 com_cmm_u_cmm_errman_request_data28_0_a3 ( + .I0(com_cmm_u_cmm_errman_cs_fsm[0]), + .I1(com_cmm_u_cmm_errman_cs_fsm[1]), + .I2(com_cmm_u_cmm_errman_cs_fsm[2]), + .O(com_cmm_u_cmm_errman_request_data28) + ); + defparam com_cmm_u_cmm_errman_request_9_i_0_0_a2_0_2_.INIT = 4'h2; + LUT2 com_cmm_u_cmm_errman_request_9_i_0_0_a2_0_2_ ( + .I0(com_cmm_u_cmm_errman_N_56493_i), + .I1(com_cmm_u_cmm_errman_cs_fsm[2]), + .O(com_cmm_u_cmm_errman_request_data30) + ); + defparam com_cmm_u_cmm_errman_nfl_num_axb0.INIT = 8'h95; + LUT3 com_cmm_u_cmm_errman_nfl_num_axb0 ( + .I0(com_cmm_u_cmm_errman_reg_decr_nfl), + .I1(com_cmm_u_cmm_errman_to_incr_0ro), + .I2(com_cmm_u_cmm_pm_dev_power_state_eq_d0), + .O(com_cmm_u_cmm_errman_nfl_num_i[0]) + ); + defparam com_cmm_u_cmm_errman_send_ftl_3_0_a2.INIT = 16'h0001; + LUT4 com_cmm_u_cmm_errman_send_ftl_3_0_a2 ( + .I0(com_cmm_u_cmm_errman_cnt_ftl[0]), + .I1(com_cmm_u_cmm_errman_cnt_ftl[1]), + .I2(com_cmm_u_cmm_errman_cnt_ftl[2]), + .I3(com_cmm_u_cmm_errman_cnt_ftl[3]), + .O(com_cmm_u_cmm_errman_send_ftl_3_0_a2_5823) + ); + defparam com_cmm_u_cmm_errman_send_cor_3_0_a2.INIT = 16'h0001; + LUT4 com_cmm_u_cmm_errman_send_cor_3_0_a2 ( + .I0(com_cmm_u_cmm_errman_cnt_cor[0]), + .I1(com_cmm_u_cmm_errman_cnt_cor[1]), + .I2(com_cmm_u_cmm_errman_cnt_cor[2]), + .I3(com_cmm_u_cmm_errman_cnt_cor[3]), + .O(com_cmm_u_cmm_errman_send_cor_3_0_a2_5824) + ); + defparam com_cmm_u_cmm_errman_send_nfl_3_0_a2.INIT = 16'h0001; + LUT4 com_cmm_u_cmm_errman_send_nfl_3_0_a2 ( + .I0(com_cmm_u_cmm_errman_cnt_nfl[0]), + .I1(com_cmm_u_cmm_errman_cnt_nfl[1]), + .I2(com_cmm_u_cmm_errman_cnt_nfl[2]), + .I3(com_cmm_u_cmm_errman_cnt_nfl[3]), + .O(com_cmm_u_cmm_errman_un1_reg_uflow_3_1) + ); + defparam com_cmm_u_cmm_errman_send_cplu_3_0_a2.INIT = 16'h0001; + LUT4 com_cmm_u_cmm_errman_send_cplu_3_0_a2 ( + .I0(com_cmm_u_cmm_errman_cnt_cplu[0]), + .I1(com_cmm_u_cmm_errman_cnt_cplu[1]), + .I2(com_cmm_u_cmm_errman_cnt_cplu[2]), + .I3(com_cmm_u_cmm_errman_cnt_cplu[3]), + .O(com_cmm_u_cmm_errman_un1_reg_uflow_3_0) + ); + defparam com_cmm_u_cmm_errman_send_cplt_3_0_a2.INIT = 16'h0001; + LUT4 com_cmm_u_cmm_errman_send_cplt_3_0_a2 ( + .I0(com_cmm_u_cmm_errman_cnt_cplt[0]), + .I1(com_cmm_u_cmm_errman_cnt_cplt[1]), + .I2(com_cmm_u_cmm_errman_cnt_cplt[2]), + .I3(com_cmm_u_cmm_errman_cnt_cplt[3]), + .O(com_cmm_u_cmm_errman_un1_reg_uflow_3) + ); + defparam com_cmm_u_cmm_errman_ns_fsm_0_i_0_a2_1_1_2_.INIT = 16'h1110; + LUT4 com_cmm_u_cmm_errman_ns_fsm_0_i_0_a2_1_1_2_ ( + .I0(com_cmm_u_cmm_errman_cs_fsm[0]), + .I1(com_cmm_u_cmm_errman_cs_fsm[1]), + .I2(com_cmm_u_cmm_errman_send_cor_5849), + .I3(com_cmm_u_cmm_errman_send_nfl_5841), + .O(com_cmm_u_cmm_errman_ns_fsm_0_i_0_a2_1_1[2]) + ); + defparam com_cmm_u_cmm_errman_ns_fsm_0_i_0_a2_1_0_0_.INIT = 8'h02; + LUT3_L com_cmm_u_cmm_errman_ns_fsm_0_i_0_a2_1_0_0_ ( + .I0(com_cmm_u_cmm_errman_N_55917_i), + .I1(com_cmm_u_cmm_errman_cs_fsm[1]), + .I2(com_cmm_u_cmm_errman_cs_fsm[3]), + .LO(com_cmm_u_cmm_errman_ns_fsm_0_i_0_a2_1[0]) + ); + defparam com_cmm_u_cmm_errman_ns_fsm_0_i_0_a2_2_.INIT = 16'h08A8; + LUT4 com_cmm_u_cmm_errman_ns_fsm_0_i_0_a2_2_ ( + .I0(com_cmm_gnt_errman), + .I1(com_cmm_u_cmm_errman_cs_fsm[0]), + .I2(com_cmm_u_cmm_errman_cs_fsm[1]), + .I3(com_cmm_u_cmm_errman_cs_fsm[2]), + .O(com_cmm_u_cmm_errman_N_58731) + ); + defparam com_cmm_u_cmm_errman_ns_fsm_0_i_0_a3_0_.INIT = 16'h3032; + LUT4 com_cmm_u_cmm_errman_ns_fsm_0_i_0_a3_0_ ( + .I0(com_cmm_u_cmm_errman_send_cor_5849), + .I1(com_cmm_u_cmm_errman_send_cplt_5847), + .I2(com_cmm_u_cmm_errman_send_ftl_5843), + .I3(com_cmm_u_cmm_errman_send_nfl_5841), + .O(com_cmm_u_cmm_errman_N_62516) + ); + defparam com_cmm_u_cmm_errman_nfl_num_c1.INIT = 8'h2A; + LUT3 com_cmm_u_cmm_errman_nfl_num_c1 ( + .I0(com_cmm_u_cmm_errman_reg_decr_nfl), + .I1(com_cmm_u_cmm_errman_to_incr_0ro), + .I2(com_cmm_u_cmm_pm_dev_power_state_eq_d0), + .O(com_cmm_u_cmm_errman_nfl_num_c1_5822) + ); + defparam com_cmm_u_cmm_errman_ns_fsm_0_i_0_a2_1_2_.INIT = 8'h80; + LUT3_L com_cmm_u_cmm_errman_ns_fsm_0_i_0_a2_1_2_ ( + .I0(com_cmm_u_cmm_errman_N_56317_i), + .I1(com_cmm_u_cmm_errman_N_58735_1), + .I2(com_cmm_u_cmm_errman_ns_fsm_0_i_0_a2_1_1[2]), + .LO(com_cmm_u_cmm_errman_N_58733) + ); + defparam com_cmm_u_cmm_errman_ns_fsm_0_i_0_0_1_.INIT = 16'hC507; + LUT4 com_cmm_u_cmm_errman_ns_fsm_0_i_0_0_1_ ( + .I0(com_cmm_gnt_errman), + .I1(com_cmm_u_cmm_errman_cs_fsm[0]), + .I2(com_cmm_u_cmm_errman_cs_fsm[1]), + .I3(com_cmm_u_cmm_errman_cs_fsm[2]), + .O(com_cmm_u_cmm_errman_ns_fsm_0_i_0_0[1]) + ); + defparam com_cmm_u_cmm_errman_reg_detectednonfatal_3_i_0_1.INIT = 16'h0888; + LUT4_L com_cmm_u_cmm_errman_reg_detectednonfatal_3_i_0_1 ( + .I0(cfg_err_cpl_timeout_n), + .I1(cfg_err_ecrc_n), + .I2(com_cmmt_err_tlp_p_cpl), + .I3(com_cmmt_err_tlp_ur), + .LO(com_cmm_u_cmm_errman_reg_detectednonfatal_3_i_0_1_5825) + ); + defparam com_cmm_u_cmm_errman_reg_detectedcorrectable_3_i_0_0_0_3.INIT = 8'h01; + LUT3_L com_cmm_u_cmm_errman_reg_detectedcorrectable_3_i_0_0_0_3 ( + .I0(l0_exit_reason_0_0_0_a2_2), + .I1(com_cmm_u_cmm_errman_reg_detectedcorrectable_3_i_0_0_0_a2_5829), + .I2(com_replay_vld), + .LO(com_cmm_u_cmm_errman_reg_detectedcorrectable_3_i_0_0_0_3_5826) + ); + defparam com_cmm_u_cmm_errman_ns_fsm_0_i_0_0_0_.INIT = 16'hCBBB; + LUT4 com_cmm_u_cmm_errman_ns_fsm_0_i_0_0_0_ ( + .I0(com_cmm_gnt_errman), + .I1(com_cmm_u_cmm_errman_cs_fsm[0]), + .I2(com_cmm_u_cmm_errman_cs_fsm[1]), + .I3(com_cmm_u_cmm_errman_cs_fsm[2]), + .O(com_cmm_u_cmm_errman_ns_fsm_0_i_0_0[0]) + ); + defparam com_cmm_u_cmm_errman_cor_num_i_1_.INIT = 8'h63; + LUT3 com_cmm_u_cmm_errman_cor_num_i_1_ ( + .I0(com_cmm_u_cmm_errman_cor_num_int[0]), + .I1(com_cmm_u_cmm_errman_cor_num_int[1]), + .I2(com_cmm_u_cmm_errman_reg_decr_cor), + .O(com_cmm_u_cmm_errman_cor_num_i[1]) + ); + defparam com_cmm_u_cmm_errman_cor_num_axbxc2.INIT = 16'hE1F0; + LUT4 com_cmm_u_cmm_errman_cor_num_axbxc2 ( + .I0(com_cmm_u_cmm_errman_cor_num_int[0]), + .I1(com_cmm_u_cmm_errman_cor_num_int[1]), + .I2(com_cmm_u_cmm_errman_cor_num_int[2]), + .I3(com_cmm_u_cmm_errman_reg_decr_cor), + .O(com_cmm_u_cmm_errman_cor_num[2]) + ); + defparam com_cmm_u_cmm_errman_nfl_num_i_1_.INIT = 8'h95; + LUT3 com_cmm_u_cmm_errman_nfl_num_i_1_ ( + .I0(com_cmm_u_cmm_errman_nfl_num_c1_5822), + .I1(com_cmm_u_cmm_errman_to_incr_1ro), + .I2(com_cmm_u_cmm_pm_dev_power_state_eq_d0), + .O(com_cmm_u_cmm_errman_nfl_num_i[1]) + ); + defparam com_cmm_u_cmm_errman_nfl_num_axbxc2.INIT = 16'hD2AA; + LUT4 com_cmm_u_cmm_errman_nfl_num_axbxc2 ( + .I0(com_cmm_u_cmm_errman_nfl_num_c1_5822), + .I1(com_cmm_u_cmm_errman_to_incr_1ro), + .I2(com_cmm_u_cmm_errman_to_incr_2ro), + .I3(com_cmm_u_cmm_pm_dev_power_state_eq_d0), + .O(com_cmm_u_cmm_errman_nfl_num[2]) + ); + defparam com_cmm_u_cmm_errman_request_data32_0_a2_0_a2.INIT = 8'h20; + LUT3_L com_cmm_u_cmm_errman_request_data32_0_a2_0_a2 ( + .I0(com_cmm_u_cmm_errman_cs_fsm[0]), + .I1(com_cmm_u_cmm_errman_cs_fsm[1]), + .I2(com_cmm_u_cmm_errman_cs_fsm[2]), + .LO(com_cmm_u_cmm_errman_request_data32) + ); + defparam com_cmm_u_cmm_errman_N_86725_i.INIT = 16'hF111; + LUT4_L com_cmm_u_cmm_errman_N_86725_i ( + .I0(cfg_err_posted_n), + .I1(cfg_err_ur_n), + .I2(com_cmmt_err_tlp_p_cpl), + .I3(com_cmmt_err_tlp_ur), + .LO(com_cmm_u_cmm_errman_N_86725_i_5838) + ); + defparam com_cmm_u_cmm_errman_reg_masterdataparityerror_3.INIT = 8'hA8; + LUT3_L com_cmm_u_cmm_errman_reg_masterdataparityerror_3 ( + .I0(NlwRenamedSig_OI_cfg_command_6_), + .I1(com_cmmt_stat_tlp_rx_cpl_ep), + .I2(com_cmmt_stat_tlp_tx_wr_ep), + .LO(com_cmm_u_cmm_errman_reg_masterdataparityerror_3_5839) + ); + defparam com_cmm_u_cmm_errman_un1_reg_uflow_3_i.INIT = 4'h1; + LUT1_L com_cmm_u_cmm_errman_un1_reg_uflow_3_i ( + .I0(com_cmm_u_cmm_errman_un1_reg_uflow_3_1), + .LO(com_cmm_u_cmm_errman_un1_reg_uflow_3_i_1_5840) + ); + defparam com_cmm_u_cmm_errman_N_62936_i.INIT = 4'h1; + LUT1_L com_cmm_u_cmm_errman_N_62936_i ( + .I0(com_cmm_u_cmm_errman_send_ftl_3_0_a2_5823), + .LO(com_cmm_u_cmm_errman_N_62936_i_5842) + ); + defparam com_cmm_u_cmm_errman_un1_reg_uflow_3_i_0.INIT = 4'h1; + LUT1_L com_cmm_u_cmm_errman_un1_reg_uflow_3_i_0 ( + .I0(com_cmm_u_cmm_errman_un1_reg_uflow_3_0), + .LO(com_cmm_u_cmm_errman_un1_reg_uflow_3_i_0_5844) + ); + defparam com_cmm_u_cmm_errman_un1_reg_uflow_3_i_1.INIT = 4'h1; + LUT1_L com_cmm_u_cmm_errman_un1_reg_uflow_3_i_1 ( + .I0(com_cmm_u_cmm_errman_un1_reg_uflow_3), + .LO(com_cmm_u_cmm_errman_un1_reg_uflow_3_i_5846) + ); + defparam com_cmm_u_cmm_errman_N_62928_i.INIT = 4'h1; + LUT1_L com_cmm_u_cmm_errman_N_62928_i ( + .I0(com_cmm_u_cmm_errman_send_cor_3_0_a2_5824), + .LO(com_cmm_u_cmm_errman_N_62928_i_5848) + ); + defparam com_cmm_u_cmm_errman_N_85959_i.INIT = 16'h13FF; + LUT4_L com_cmm_u_cmm_errman_N_85959_i ( + .I0(cfg_err_cpl_abort_n), + .I1(cfg_err_posted_n), + .I2(cfg_err_ur_n), + .I3(com_cmm_u_cmm_errman_reg_detectednonfatal_3_i_0_1_5825), + .LO(com_cmm_u_cmm_errman_N_85959_i_5850) + ); + defparam com_cmm_u_cmm_errman_N_85494_i.INIT = 16'hBFFF; + LUT4_L com_cmm_u_cmm_errman_N_85494_i ( + .I0(com_cmm_u_cmm_errman_reg_detectedcorrectable_3_i_0_0_0_a2_0_5827), + .I1(cfg_err_cor_n), + .I2(com_cmm_u_cmm_errman_reg_detectedcorrectable_3_i_0_0_0_3_5826), + .I3(com_cmml_bad_dllp_err_n), + .LO(com_cmm_u_cmm_errman_N_85494_i_5851) + ); + defparam com_cmm_u_cmm_errman_N_86299_i.INIT = 16'hECA0; + LUT4_L com_cmm_u_cmm_errman_N_86299_i ( + .I0(com_cmm_u_cmm_errman_N_20280_i_0), + .I1(com_cmm_u_cmm_errman_cfg_rd_hdr[2]), + .I2(com_cmm_u_cmm_errman_cmt_rd_hdr[2]), + .I3(com_cmm_u_cmm_errman_request_data28), + .LO(com_cmm_u_cmm_errman_N_86299_i_5853) + ); + defparam com_cmm_u_cmm_errman_N_86298_i.INIT = 16'hECA0; + LUT4_L com_cmm_u_cmm_errman_N_86298_i ( + .I0(com_cmm_u_cmm_errman_N_20280_i_0), + .I1(com_cmm_u_cmm_errman_cfg_rd_hdr[1]), + .I2(com_cmm_u_cmm_errman_cmt_rd_hdr[1]), + .I3(com_cmm_u_cmm_errman_request_data28), + .LO(com_cmm_u_cmm_errman_N_86298_i_5854) + ); + defparam com_cmm_u_cmm_errman_N_86297_i.INIT = 16'hECA0; + LUT4_L com_cmm_u_cmm_errman_N_86297_i ( + .I0(com_cmm_u_cmm_errman_N_20280_i_0), + .I1(com_cmm_u_cmm_errman_cfg_rd_hdr[0]), + .I2(com_cmm_u_cmm_errman_cmt_rd_hdr[0]), + .I3(com_cmm_u_cmm_errman_request_data28), + .LO(com_cmm_u_cmm_errman_N_86297_i_5855) + ); + defparam com_cmm_u_cmm_errman_N_86314_i.INIT = 16'hECA0; + LUT4_L com_cmm_u_cmm_errman_N_86314_i ( + .I0(com_cmm_u_cmm_errman_N_20280_i_0), + .I1(com_cmm_u_cmm_errman_cfg_rd_hdr[17]), + .I2(com_cmm_u_cmm_errman_cmt_rd_hdr[17]), + .I3(com_cmm_u_cmm_errman_request_data28), + .LO(com_cmm_u_cmm_errman_N_86314_i_5856) + ); + defparam com_cmm_u_cmm_errman_N_86313_i.INIT = 16'hECA0; + LUT4_L com_cmm_u_cmm_errman_N_86313_i ( + .I0(com_cmm_u_cmm_errman_N_20280_i_0), + .I1(com_cmm_u_cmm_errman_cfg_rd_hdr[16]), + .I2(com_cmm_u_cmm_errman_cmt_rd_hdr[16]), + .I3(com_cmm_u_cmm_errman_request_data28), + .LO(com_cmm_u_cmm_errman_N_86313_i_5857) + ); + defparam com_cmm_u_cmm_errman_N_86312_i.INIT = 16'hECA0; + LUT4_L com_cmm_u_cmm_errman_N_86312_i ( + .I0(com_cmm_u_cmm_errman_N_20280_i_0), + .I1(com_cmm_u_cmm_errman_cfg_rd_hdr[15]), + .I2(com_cmm_u_cmm_errman_cmt_rd_hdr[15]), + .I3(com_cmm_u_cmm_errman_request_data28), + .LO(com_cmm_u_cmm_errman_N_86312_i_5858) + ); + defparam com_cmm_u_cmm_errman_N_86311_i.INIT = 16'hECA0; + LUT4_L com_cmm_u_cmm_errman_N_86311_i ( + .I0(com_cmm_u_cmm_errman_N_20280_i_0), + .I1(com_cmm_u_cmm_errman_cfg_rd_hdr[14]), + .I2(com_cmm_u_cmm_errman_cmt_rd_hdr[14]), + .I3(com_cmm_u_cmm_errman_request_data28), + .LO(com_cmm_u_cmm_errman_N_86311_i_5859) + ); + defparam com_cmm_u_cmm_errman_N_86310_i.INIT = 16'hECA0; + LUT4_L com_cmm_u_cmm_errman_N_86310_i ( + .I0(com_cmm_u_cmm_errman_N_20280_i_0), + .I1(com_cmm_u_cmm_errman_cfg_rd_hdr[13]), + .I2(com_cmm_u_cmm_errman_cmt_rd_hdr[13]), + .I3(com_cmm_u_cmm_errman_request_data28), + .LO(com_cmm_u_cmm_errman_N_86310_i_5860) + ); + defparam com_cmm_u_cmm_errman_N_86309_i.INIT = 16'hECA0; + LUT4_L com_cmm_u_cmm_errman_N_86309_i ( + .I0(com_cmm_u_cmm_errman_N_20280_i_0), + .I1(com_cmm_u_cmm_errman_cfg_rd_hdr[12]), + .I2(com_cmm_u_cmm_errman_cmt_rd_hdr[12]), + .I3(com_cmm_u_cmm_errman_request_data28), + .LO(com_cmm_u_cmm_errman_N_86309_i_5861) + ); + defparam com_cmm_u_cmm_errman_N_86308_i.INIT = 16'hECA0; + LUT4_L com_cmm_u_cmm_errman_N_86308_i ( + .I0(com_cmm_u_cmm_errman_N_20280_i_0), + .I1(com_cmm_u_cmm_errman_cfg_rd_hdr[11]), + .I2(com_cmm_u_cmm_errman_cmt_rd_hdr[11]), + .I3(com_cmm_u_cmm_errman_request_data28), + .LO(com_cmm_u_cmm_errman_N_86308_i_5862) + ); + defparam com_cmm_u_cmm_errman_N_86307_i.INIT = 16'hECA0; + LUT4_L com_cmm_u_cmm_errman_N_86307_i ( + .I0(com_cmm_u_cmm_errman_N_20280_i_0), + .I1(com_cmm_u_cmm_errman_cfg_rd_hdr[10]), + .I2(com_cmm_u_cmm_errman_cmt_rd_hdr[10]), + .I3(com_cmm_u_cmm_errman_request_data28), + .LO(com_cmm_u_cmm_errman_N_86307_i_5863) + ); + defparam com_cmm_u_cmm_errman_N_86306_i.INIT = 16'hECA0; + LUT4_L com_cmm_u_cmm_errman_N_86306_i ( + .I0(com_cmm_u_cmm_errman_N_20280_i_0), + .I1(com_cmm_u_cmm_errman_cfg_rd_hdr[9]), + .I2(com_cmm_u_cmm_errman_cmt_rd_hdr[9]), + .I3(com_cmm_u_cmm_errman_request_data28), + .LO(com_cmm_u_cmm_errman_N_86306_i_5864) + ); + defparam com_cmm_u_cmm_errman_N_86305_i.INIT = 16'hECA0; + LUT4_L com_cmm_u_cmm_errman_N_86305_i ( + .I0(com_cmm_u_cmm_errman_N_20280_i_0), + .I1(com_cmm_u_cmm_errman_cfg_rd_hdr[8]), + .I2(com_cmm_u_cmm_errman_cmt_rd_hdr[8]), + .I3(com_cmm_u_cmm_errman_request_data28), + .LO(com_cmm_u_cmm_errman_N_86305_i_5865) + ); + defparam com_cmm_u_cmm_errman_N_86304_i.INIT = 16'hECA0; + LUT4_L com_cmm_u_cmm_errman_N_86304_i ( + .I0(com_cmm_u_cmm_errman_N_20280_i_0), + .I1(com_cmm_u_cmm_errman_cfg_rd_hdr[7]), + .I2(com_cmm_u_cmm_errman_cmt_rd_hdr[7]), + .I3(com_cmm_u_cmm_errman_request_data28), + .LO(com_cmm_u_cmm_errman_N_86304_i_5866) + ); + defparam com_cmm_u_cmm_errman_N_86303_i.INIT = 16'hECA0; + LUT4_L com_cmm_u_cmm_errman_N_86303_i ( + .I0(com_cmm_u_cmm_errman_N_20280_i_0), + .I1(com_cmm_u_cmm_errman_cfg_rd_hdr[6]), + .I2(com_cmm_u_cmm_errman_cmt_rd_hdr[6]), + .I3(com_cmm_u_cmm_errman_request_data28), + .LO(com_cmm_u_cmm_errman_N_86303_i_5867) + ); + defparam com_cmm_u_cmm_errman_N_86302_i.INIT = 16'hECA0; + LUT4_L com_cmm_u_cmm_errman_N_86302_i ( + .I0(com_cmm_u_cmm_errman_N_20280_i_0), + .I1(com_cmm_u_cmm_errman_cfg_rd_hdr[5]), + .I2(com_cmm_u_cmm_errman_cmt_rd_hdr[5]), + .I3(com_cmm_u_cmm_errman_request_data28), + .LO(com_cmm_u_cmm_errman_N_86302_i_5868) + ); + defparam com_cmm_u_cmm_errman_N_86301_i.INIT = 16'hECA0; + LUT4_L com_cmm_u_cmm_errman_N_86301_i ( + .I0(com_cmm_u_cmm_errman_N_20280_i_0), + .I1(com_cmm_u_cmm_errman_cfg_rd_hdr[4]), + .I2(com_cmm_u_cmm_errman_cmt_rd_hdr[4]), + .I3(com_cmm_u_cmm_errman_request_data28), + .LO(com_cmm_u_cmm_errman_N_86301_i_5869) + ); + defparam com_cmm_u_cmm_errman_N_86300_i.INIT = 16'hECA0; + LUT4_L com_cmm_u_cmm_errman_N_86300_i ( + .I0(com_cmm_u_cmm_errman_N_20280_i_0), + .I1(com_cmm_u_cmm_errman_cfg_rd_hdr[3]), + .I2(com_cmm_u_cmm_errman_cmt_rd_hdr[3]), + .I3(com_cmm_u_cmm_errman_request_data28), + .LO(com_cmm_u_cmm_errman_N_86300_i_5870) + ); + defparam com_cmm_u_cmm_errman_N_86329_i.INIT = 16'hECA0; + LUT4_L com_cmm_u_cmm_errman_N_86329_i ( + .I0(com_cmm_u_cmm_errman_N_20280_i_0), + .I1(com_cmm_u_cmm_errman_cfg_rd_hdr[32]), + .I2(com_cmm_u_cmm_errman_cmt_rd_hdr[32]), + .I3(com_cmm_u_cmm_errman_request_data28), + .LO(com_cmm_u_cmm_errman_N_86329_i_5871) + ); + defparam com_cmm_u_cmm_errman_N_86328_i.INIT = 16'hECA0; + LUT4_L com_cmm_u_cmm_errman_N_86328_i ( + .I0(com_cmm_u_cmm_errman_N_20280_i_0), + .I1(com_cmm_u_cmm_errman_cfg_rd_hdr[31]), + .I2(com_cmm_u_cmm_errman_cmt_rd_hdr[31]), + .I3(com_cmm_u_cmm_errman_request_data28), + .LO(com_cmm_u_cmm_errman_N_86328_i_5872) + ); + defparam com_cmm_u_cmm_errman_N_86327_i.INIT = 16'hECA0; + LUT4_L com_cmm_u_cmm_errman_N_86327_i ( + .I0(com_cmm_u_cmm_errman_N_20280_i_0), + .I1(com_cmm_u_cmm_errman_cfg_rd_hdr[30]), + .I2(com_cmm_u_cmm_errman_cmt_rd_hdr[30]), + .I3(com_cmm_u_cmm_errman_request_data28), + .LO(com_cmm_u_cmm_errman_N_86327_i_5873) + ); + defparam com_cmm_u_cmm_errman_N_86326_i.INIT = 16'hECA0; + LUT4_L com_cmm_u_cmm_errman_N_86326_i ( + .I0(com_cmm_u_cmm_errman_N_20280_i_0), + .I1(com_cmm_u_cmm_errman_cfg_rd_hdr[29]), + .I2(com_cmm_u_cmm_errman_cmt_rd_hdr[29]), + .I3(com_cmm_u_cmm_errman_request_data28), + .LO(com_cmm_u_cmm_errman_N_86326_i_5874) + ); + defparam com_cmm_u_cmm_errman_N_86325_i.INIT = 16'hECA0; + LUT4_L com_cmm_u_cmm_errman_N_86325_i ( + .I0(com_cmm_u_cmm_errman_N_20280_i_0), + .I1(com_cmm_u_cmm_errman_cfg_rd_hdr[28]), + .I2(com_cmm_u_cmm_errman_cmt_rd_hdr[28]), + .I3(com_cmm_u_cmm_errman_request_data28), + .LO(com_cmm_u_cmm_errman_N_86325_i_5875) + ); + defparam com_cmm_u_cmm_errman_N_86324_i.INIT = 16'hECA0; + LUT4_L com_cmm_u_cmm_errman_N_86324_i ( + .I0(com_cmm_u_cmm_errman_N_20280_i_0), + .I1(com_cmm_u_cmm_errman_cfg_rd_hdr[27]), + .I2(com_cmm_u_cmm_errman_cmt_rd_hdr[27]), + .I3(com_cmm_u_cmm_errman_request_data28), + .LO(com_cmm_u_cmm_errman_N_86324_i_5876) + ); + defparam com_cmm_u_cmm_errman_N_86323_i.INIT = 16'hECA0; + LUT4_L com_cmm_u_cmm_errman_N_86323_i ( + .I0(com_cmm_u_cmm_errman_N_20280_i_0), + .I1(com_cmm_u_cmm_errman_cfg_rd_hdr[26]), + .I2(com_cmm_u_cmm_errman_cmt_rd_hdr[26]), + .I3(com_cmm_u_cmm_errman_request_data28), + .LO(com_cmm_u_cmm_errman_N_86323_i_5877) + ); + defparam com_cmm_u_cmm_errman_N_86322_i.INIT = 16'hECA0; + LUT4_L com_cmm_u_cmm_errman_N_86322_i ( + .I0(com_cmm_u_cmm_errman_N_20280_i_0), + .I1(com_cmm_u_cmm_errman_cfg_rd_hdr[25]), + .I2(com_cmm_u_cmm_errman_cmt_rd_hdr[25]), + .I3(com_cmm_u_cmm_errman_request_data28), + .LO(com_cmm_u_cmm_errman_N_86322_i_5878) + ); + defparam com_cmm_u_cmm_errman_N_86321_i.INIT = 16'hECA0; + LUT4_L com_cmm_u_cmm_errman_N_86321_i ( + .I0(com_cmm_u_cmm_errman_N_20280_i_0), + .I1(com_cmm_u_cmm_errman_cfg_rd_hdr[24]), + .I2(com_cmm_u_cmm_errman_cmt_rd_hdr[24]), + .I3(com_cmm_u_cmm_errman_request_data28), + .LO(com_cmm_u_cmm_errman_N_86321_i_5879) + ); + defparam com_cmm_u_cmm_errman_N_86320_i.INIT = 16'hECA0; + LUT4_L com_cmm_u_cmm_errman_N_86320_i ( + .I0(com_cmm_u_cmm_errman_N_20280_i_0), + .I1(com_cmm_u_cmm_errman_cfg_rd_hdr[23]), + .I2(com_cmm_u_cmm_errman_cmt_rd_hdr[23]), + .I3(com_cmm_u_cmm_errman_request_data28), + .LO(com_cmm_u_cmm_errman_N_86320_i_5880) + ); + defparam com_cmm_u_cmm_errman_N_86319_i.INIT = 16'hECA0; + LUT4_L com_cmm_u_cmm_errman_N_86319_i ( + .I0(com_cmm_u_cmm_errman_N_20280_i_0), + .I1(com_cmm_u_cmm_errman_cfg_rd_hdr[22]), + .I2(com_cmm_u_cmm_errman_cmt_rd_hdr[22]), + .I3(com_cmm_u_cmm_errman_request_data28), + .LO(com_cmm_u_cmm_errman_N_86319_i_5881) + ); + defparam com_cmm_u_cmm_errman_N_86318_i.INIT = 16'hECA0; + LUT4_L com_cmm_u_cmm_errman_N_86318_i ( + .I0(com_cmm_u_cmm_errman_N_20280_i_0), + .I1(com_cmm_u_cmm_errman_cfg_rd_hdr[21]), + .I2(com_cmm_u_cmm_errman_cmt_rd_hdr[21]), + .I3(com_cmm_u_cmm_errman_request_data28), + .LO(com_cmm_u_cmm_errman_N_86318_i_5882) + ); + defparam com_cmm_u_cmm_errman_N_86317_i.INIT = 16'hECA0; + LUT4_L com_cmm_u_cmm_errman_N_86317_i ( + .I0(com_cmm_u_cmm_errman_N_20280_i_0), + .I1(com_cmm_u_cmm_errman_cfg_rd_hdr[20]), + .I2(com_cmm_u_cmm_errman_cmt_rd_hdr[20]), + .I3(com_cmm_u_cmm_errman_request_data28), + .LO(com_cmm_u_cmm_errman_N_86317_i_5883) + ); + defparam com_cmm_u_cmm_errman_N_86316_i.INIT = 16'hECA0; + LUT4_L com_cmm_u_cmm_errman_N_86316_i ( + .I0(com_cmm_u_cmm_errman_N_20280_i_0), + .I1(com_cmm_u_cmm_errman_cfg_rd_hdr[19]), + .I2(com_cmm_u_cmm_errman_cmt_rd_hdr[19]), + .I3(com_cmm_u_cmm_errman_request_data28), + .LO(com_cmm_u_cmm_errman_N_86316_i_5884) + ); + defparam com_cmm_u_cmm_errman_N_86315_i.INIT = 16'hECA0; + LUT4_L com_cmm_u_cmm_errman_N_86315_i ( + .I0(com_cmm_u_cmm_errman_N_20280_i_0), + .I1(com_cmm_u_cmm_errman_cfg_rd_hdr[18]), + .I2(com_cmm_u_cmm_errman_cmt_rd_hdr[18]), + .I3(com_cmm_u_cmm_errman_request_data28), + .LO(com_cmm_u_cmm_errman_N_86315_i_5885) + ); + defparam com_cmm_u_cmm_errman_N_86344_i.INIT = 16'hECA0; + LUT4_L com_cmm_u_cmm_errman_N_86344_i ( + .I0(com_cmm_u_cmm_errman_N_20280_i_0), + .I1(com_cmm_u_cmm_errman_cfg_rd_hdr[47]), + .I2(com_cmm_u_cmm_errman_cmt_rd_hdr[47]), + .I3(com_cmm_u_cmm_errman_request_data28), + .LO(com_cmm_u_cmm_errman_N_86344_i_5886) + ); + defparam com_cmm_u_cmm_errman_N_86343_i.INIT = 16'hECA0; + LUT4_L com_cmm_u_cmm_errman_N_86343_i ( + .I0(com_cmm_u_cmm_errman_N_20280_i_0), + .I1(com_cmm_u_cmm_errman_cfg_rd_hdr[46]), + .I2(com_cmm_u_cmm_errman_cmt_rd_hdr[46]), + .I3(com_cmm_u_cmm_errman_request_data28), + .LO(com_cmm_u_cmm_errman_N_86343_i_5887) + ); + defparam com_cmm_u_cmm_errman_N_86342_i.INIT = 16'hECA0; + LUT4_L com_cmm_u_cmm_errman_N_86342_i ( + .I0(com_cmm_u_cmm_errman_N_20280_i_0), + .I1(com_cmm_u_cmm_errman_cfg_rd_hdr[45]), + .I2(com_cmm_u_cmm_errman_cmt_rd_hdr[45]), + .I3(com_cmm_u_cmm_errman_request_data28), + .LO(com_cmm_u_cmm_errman_N_86342_i_5888) + ); + defparam com_cmm_u_cmm_errman_N_86341_i.INIT = 16'hECA0; + LUT4_L com_cmm_u_cmm_errman_N_86341_i ( + .I0(com_cmm_u_cmm_errman_N_20280_i_0), + .I1(com_cmm_u_cmm_errman_cfg_rd_hdr[44]), + .I2(com_cmm_u_cmm_errman_cmt_rd_hdr[44]), + .I3(com_cmm_u_cmm_errman_request_data28), + .LO(com_cmm_u_cmm_errman_N_86341_i_5889) + ); + defparam com_cmm_u_cmm_errman_N_86340_i.INIT = 16'hECA0; + LUT4_L com_cmm_u_cmm_errman_N_86340_i ( + .I0(com_cmm_u_cmm_errman_N_20280_i_0), + .I1(com_cmm_u_cmm_errman_cfg_rd_hdr[43]), + .I2(com_cmm_u_cmm_errman_cmt_rd_hdr[43]), + .I3(com_cmm_u_cmm_errman_request_data28), + .LO(com_cmm_u_cmm_errman_N_86340_i_5890) + ); + defparam com_cmm_u_cmm_errman_N_86339_i.INIT = 16'hECA0; + LUT4_L com_cmm_u_cmm_errman_N_86339_i ( + .I0(com_cmm_u_cmm_errman_N_20280_i_0), + .I1(com_cmm_u_cmm_errman_cfg_rd_hdr[42]), + .I2(com_cmm_u_cmm_errman_cmt_rd_hdr[42]), + .I3(com_cmm_u_cmm_errman_request_data28), + .LO(com_cmm_u_cmm_errman_N_86339_i_5891) + ); + defparam com_cmm_u_cmm_errman_N_86338_i.INIT = 16'hECA0; + LUT4_L com_cmm_u_cmm_errman_N_86338_i ( + .I0(com_cmm_u_cmm_errman_N_20280_i_0), + .I1(com_cmm_u_cmm_errman_cfg_rd_hdr[41]), + .I2(com_cmm_u_cmm_errman_cmt_rd_hdr[41]), + .I3(com_cmm_u_cmm_errman_request_data28), + .LO(com_cmm_u_cmm_errman_N_86338_i_5892) + ); + defparam com_cmm_u_cmm_errman_N_86337_i.INIT = 16'hECA0; + LUT4_L com_cmm_u_cmm_errman_N_86337_i ( + .I0(com_cmm_u_cmm_errman_N_20280_i_0), + .I1(com_cmm_u_cmm_errman_cfg_rd_hdr[40]), + .I2(com_cmm_u_cmm_errman_cmt_rd_hdr[40]), + .I3(com_cmm_u_cmm_errman_request_data28), + .LO(com_cmm_u_cmm_errman_N_86337_i_5893) + ); + defparam com_cmm_u_cmm_errman_N_86336_i.INIT = 16'hECA0; + LUT4_L com_cmm_u_cmm_errman_N_86336_i ( + .I0(com_cmm_u_cmm_errman_N_20280_i_0), + .I1(com_cmm_u_cmm_errman_cfg_rd_hdr[39]), + .I2(com_cmm_u_cmm_errman_cmt_rd_hdr[39]), + .I3(com_cmm_u_cmm_errman_request_data28), + .LO(com_cmm_u_cmm_errman_N_86336_i_5894) + ); + defparam com_cmm_u_cmm_errman_N_86335_i.INIT = 16'hECA0; + LUT4_L com_cmm_u_cmm_errman_N_86335_i ( + .I0(com_cmm_u_cmm_errman_N_20280_i_0), + .I1(com_cmm_u_cmm_errman_cfg_rd_hdr[38]), + .I2(com_cmm_u_cmm_errman_cmt_rd_hdr[38]), + .I3(com_cmm_u_cmm_errman_request_data28), + .LO(com_cmm_u_cmm_errman_N_86335_i_5895) + ); + defparam com_cmm_u_cmm_errman_N_86334_i.INIT = 16'hECA0; + LUT4_L com_cmm_u_cmm_errman_N_86334_i ( + .I0(com_cmm_u_cmm_errman_N_20280_i_0), + .I1(com_cmm_u_cmm_errman_cfg_rd_hdr[37]), + .I2(com_cmm_u_cmm_errman_cmt_rd_hdr[37]), + .I3(com_cmm_u_cmm_errman_request_data28), + .LO(com_cmm_u_cmm_errman_N_86334_i_5896) + ); + defparam com_cmm_u_cmm_errman_N_86333_i.INIT = 16'hECA0; + LUT4_L com_cmm_u_cmm_errman_N_86333_i ( + .I0(com_cmm_u_cmm_errman_N_20280_i_0), + .I1(com_cmm_u_cmm_errman_cfg_rd_hdr[36]), + .I2(com_cmm_u_cmm_errman_cmt_rd_hdr[36]), + .I3(com_cmm_u_cmm_errman_request_data28), + .LO(com_cmm_u_cmm_errman_N_86333_i_5897) + ); + defparam com_cmm_u_cmm_errman_N_86332_i.INIT = 16'hECA0; + LUT4_L com_cmm_u_cmm_errman_N_86332_i ( + .I0(com_cmm_u_cmm_errman_N_20280_i_0), + .I1(com_cmm_u_cmm_errman_cfg_rd_hdr[35]), + .I2(com_cmm_u_cmm_errman_cmt_rd_hdr[35]), + .I3(com_cmm_u_cmm_errman_request_data28), + .LO(com_cmm_u_cmm_errman_N_86332_i_5898) + ); + defparam com_cmm_u_cmm_errman_N_86331_i.INIT = 16'hECA0; + LUT4_L com_cmm_u_cmm_errman_N_86331_i ( + .I0(com_cmm_u_cmm_errman_N_20280_i_0), + .I1(com_cmm_u_cmm_errman_cfg_rd_hdr[34]), + .I2(com_cmm_u_cmm_errman_cmt_rd_hdr[34]), + .I3(com_cmm_u_cmm_errman_request_data28), + .LO(com_cmm_u_cmm_errman_N_86331_i_5899) + ); + defparam com_cmm_u_cmm_errman_N_86330_i.INIT = 16'hECA0; + LUT4_L com_cmm_u_cmm_errman_N_86330_i ( + .I0(com_cmm_u_cmm_errman_N_20280_i_0), + .I1(com_cmm_u_cmm_errman_cfg_rd_hdr[33]), + .I2(com_cmm_u_cmm_errman_cmt_rd_hdr[33]), + .I3(com_cmm_u_cmm_errman_request_data28), + .LO(com_cmm_u_cmm_errman_N_86330_i_5900) + ); + defparam com_cmm_u_cmm_errman_reg_cfg_wr_hdr_6_i_0_1_.INIT = 4'h8; + LUT2_L com_cmm_u_cmm_errman_reg_cfg_wr_hdr_6_i_0_1_ ( + .I0(com_cmm_u_cmm_errman_N_59526), + .I1(cfg_err_tlp_cpl_header_6100[1]), + .LO(com_cmm_u_cmm_errman_N_39843_i) + ); + defparam com_cmm_u_cmm_errman_reg_cfg_wr_hdr_6_i_0_0_.INIT = 4'h8; + LUT2_L com_cmm_u_cmm_errman_reg_cfg_wr_hdr_6_i_0_0_ ( + .I0(com_cmm_u_cmm_errman_N_59526), + .I1(cfg_err_tlp_cpl_header_6100[0]), + .LO(com_cmm_u_cmm_errman_N_39841_i) + ); + defparam com_cmm_u_cmm_errman_reg_cfg_rp_4_axbxc1.INIT = 8'h78; + LUT3_L com_cmm_u_cmm_errman_reg_cfg_rp_4_axbxc1 ( + .I0(com_cmm_u_cmm_errman_N_56208_i), + .I1(com_cmm_u_cmm_errman_reg_cfg_rp[0]), + .I2(com_cmm_u_cmm_errman_reg_cfg_rp[1]), + .LO(com_cmm_u_cmm_errman_reg_cfg_rp_4[1]) + ); + defparam com_cmm_u_cmm_errman_reg_cfg_rp_4_axbxc0.INIT = 4'h6; + LUT2_L com_cmm_u_cmm_errman_reg_cfg_rp_4_axbxc0 ( + .I0(com_cmm_u_cmm_errman_N_56208_i), + .I1(com_cmm_u_cmm_errman_reg_cfg_rp[0]), + .LO(com_cmm_u_cmm_errman_reg_cfg_rp_4[0]) + ); + defparam com_cmm_u_cmm_errman_reg_cmt_rp_4_axbxc1.INIT = 8'h78; + LUT3_L com_cmm_u_cmm_errman_reg_cmt_rp_4_axbxc1 ( + .I0(com_cmm_u_cmm_errman_N_56322_i), + .I1(com_cmm_u_cmm_errman_reg_cmt_rp[0]), + .I2(com_cmm_u_cmm_errman_reg_cmt_rp[1]), + .LO(com_cmm_u_cmm_errman_reg_cmt_rp_4[1]) + ); + defparam com_cmm_u_cmm_errman_reg_cmt_rp_4_axbxc0.INIT = 4'h6; + LUT2_L com_cmm_u_cmm_errman_reg_cmt_rp_4_axbxc0 ( + .I0(com_cmm_u_cmm_errman_N_56322_i), + .I1(com_cmm_u_cmm_errman_reg_cmt_rp[0]), + .LO(com_cmm_u_cmm_errman_reg_cmt_rp_4[0]) + ); + defparam com_cmm_u_cmm_errman_un1_cs_fsm_1_0_a2_0_a2.INIT = 8'h80; + LUT3_L com_cmm_u_cmm_errman_un1_cs_fsm_1_0_a2_0_a2 ( + .I0(com_cmm_u_cmm_errman_cs_fsm[0]), + .I1(com_cmm_u_cmm_errman_cs_fsm[1]), + .I2(com_cmm_u_cmm_errman_cs_fsm[2]), + .LO(com_cmm_u_cmm_errman_un1_cs_fsm_1_0_a2_0_a2_5901) + ); + defparam com_cmm_u_cmm_errman_N_85896_i.INIT = 16'hFDFC; + LUT4_L com_cmm_u_cmm_errman_N_85896_i ( + .I0(com_cmm_u_cmm_errman_N_56493_i), + .I1(com_cmm_u_cmm_errman_N_58731), + .I2(com_cmm_u_cmm_errman_N_58733), + .I3(com_cmm_u_cmm_errman_cs_fsm[2]), + .LO(com_cmm_u_cmm_errman_N_85896_i_5902) + ); + defparam com_cmm_u_cmm_errman_N_85897_i.INIT = 16'h20FF; + LUT4_L com_cmm_u_cmm_errman_N_85897_i ( + .I0(com_cmm_u_cmm_errman_N_55917_i), + .I1(com_cmm_u_cmm_errman_N_56317_i), + .I2(com_cmm_u_cmm_errman_N_58735_1), + .I3(com_cmm_u_cmm_errman_ns_fsm_0_i_0_0[1]), + .LO(com_cmm_u_cmm_errman_N_85897_i_5903) + ); + defparam com_cmm_u_cmm_errman_N_85997_i.INIT = 16'hF3B3; + LUT4_L com_cmm_u_cmm_errman_N_85997_i ( + .I0(com_cmm_u_cmm_errman_N_62516), + .I1(com_cmm_u_cmm_errman_ns_fsm_0_i_0_0[0]), + .I2(com_cmm_u_cmm_errman_ns_fsm_0_i_0_a2_1[0]), + .I3(com_cmm_u_cmm_errman_send_cplu_5845), + .LO(com_cmm_u_cmm_errman_N_85997_i_5904) + ); + defparam com_cmm_u_cmm_errman_N_86360_i.INIT = 8'hF4; + LUT3_L com_cmm_u_cmm_errman_N_86360_i ( + .I0(com_cmm_u_cmm_errman_cs_fsm[1]), + .I1(com_cmm_u_cmm_errman_cs_fsm[2]), + .I2(com_cmm_u_cmm_errman_request_data30), + .LO(com_cmm_u_cmm_errman_N_86360_i_5905) + ); + defparam com_cmm_u_cmm_errman_N_86399_i.INIT = 8'h26; + LUT3_L com_cmm_u_cmm_errman_N_86399_i ( + .I0(com_cmm_u_cmm_errman_cs_fsm[0]), + .I1(com_cmm_u_cmm_errman_cs_fsm[1]), + .I2(com_cmm_u_cmm_errman_cs_fsm[2]), + .LO(com_cmm_u_cmm_errman_N_86399_i_5906) + ); + defparam com_cmm_u_cmm_errman_N_86398_i.INIT = 4'hE; + LUT2_L com_cmm_u_cmm_errman_N_86398_i ( + .I0(com_cmm_u_cmm_errman_N_20280_i_0), + .I1(com_cmm_u_cmm_errman_request_data31), + .LO(com_cmm_u_cmm_errman_N_86398_i_5907) + ); + defparam com_cmm_u_cmm_errman_N_86346_i.INIT = 16'hECA0; + LUT4_L com_cmm_u_cmm_errman_N_86346_i ( + .I0(com_cmm_u_cmm_errman_N_20280_i_0), + .I1(com_cmm_u_cmm_errman_cfg_rd_hdr[49]), + .I2(com_cmm_u_cmm_errman_cmt_rd_hdr[49]), + .I3(com_cmm_u_cmm_errman_request_data28), + .LO(com_cmm_u_cmm_errman_N_86346_i_5908) + ); + defparam com_cmm_u_cmm_errman_N_86345_i.INIT = 16'hECA0; + LUT4_L com_cmm_u_cmm_errman_N_86345_i ( + .I0(com_cmm_u_cmm_errman_N_20280_i_0), + .I1(com_cmm_u_cmm_errman_cfg_rd_hdr[48]), + .I2(com_cmm_u_cmm_errman_cmt_rd_hdr[48]), + .I3(com_cmm_u_cmm_errman_request_data28), + .LO(com_cmm_u_cmm_errman_N_86345_i_5909) + ); + defparam com_cmm_u_cmm_errman_reg_cfg_wr_hdr_6_i_0_16_.INIT = 4'h8; + LUT2_L com_cmm_u_cmm_errman_reg_cfg_wr_hdr_6_i_0_16_ ( + .I0(com_cmm_u_cmm_errman_N_59526), + .I1(cfg_err_tlp_cpl_header_6100[16]), + .LO(com_cmm_u_cmm_errman_N_39873_i) + ); + defparam com_cmm_u_cmm_errman_reg_cfg_wr_hdr_6_i_0_15_.INIT = 4'h8; + LUT2_L com_cmm_u_cmm_errman_reg_cfg_wr_hdr_6_i_0_15_ ( + .I0(com_cmm_u_cmm_errman_N_59526), + .I1(cfg_err_tlp_cpl_header_6100[15]), + .LO(com_cmm_u_cmm_errman_N_39871_i) + ); + defparam com_cmm_u_cmm_errman_reg_cfg_wr_hdr_6_i_0_14_.INIT = 4'h8; + LUT2_L com_cmm_u_cmm_errman_reg_cfg_wr_hdr_6_i_0_14_ ( + .I0(com_cmm_u_cmm_errman_N_59526), + .I1(cfg_err_tlp_cpl_header_6100[14]), + .LO(com_cmm_u_cmm_errman_N_39869_i) + ); + defparam com_cmm_u_cmm_errman_reg_cfg_wr_hdr_6_i_0_13_.INIT = 4'h8; + LUT2_L com_cmm_u_cmm_errman_reg_cfg_wr_hdr_6_i_0_13_ ( + .I0(com_cmm_u_cmm_errman_N_59526), + .I1(cfg_err_tlp_cpl_header_6100[13]), + .LO(com_cmm_u_cmm_errman_N_39867_i) + ); + defparam com_cmm_u_cmm_errman_reg_cfg_wr_hdr_6_i_0_12_.INIT = 4'h8; + LUT2_L com_cmm_u_cmm_errman_reg_cfg_wr_hdr_6_i_0_12_ ( + .I0(com_cmm_u_cmm_errman_N_59526), + .I1(cfg_err_tlp_cpl_header_6100[12]), + .LO(com_cmm_u_cmm_errman_N_39865_i) + ); + defparam com_cmm_u_cmm_errman_reg_cfg_wr_hdr_6_i_0_11_.INIT = 4'h8; + LUT2_L com_cmm_u_cmm_errman_reg_cfg_wr_hdr_6_i_0_11_ ( + .I0(com_cmm_u_cmm_errman_N_59526), + .I1(cfg_err_tlp_cpl_header_6100[11]), + .LO(com_cmm_u_cmm_errman_N_39863_i) + ); + defparam com_cmm_u_cmm_errman_reg_cfg_wr_hdr_6_i_0_10_.INIT = 4'h8; + LUT2_L com_cmm_u_cmm_errman_reg_cfg_wr_hdr_6_i_0_10_ ( + .I0(com_cmm_u_cmm_errman_N_59526), + .I1(cfg_err_tlp_cpl_header_6100[10]), + .LO(com_cmm_u_cmm_errman_N_39861_i) + ); + defparam com_cmm_u_cmm_errman_reg_cfg_wr_hdr_6_i_0_9_.INIT = 4'h8; + LUT2_L com_cmm_u_cmm_errman_reg_cfg_wr_hdr_6_i_0_9_ ( + .I0(com_cmm_u_cmm_errman_N_59526), + .I1(cfg_err_tlp_cpl_header_6100[9]), + .LO(com_cmm_u_cmm_errman_N_39859_i) + ); + defparam com_cmm_u_cmm_errman_reg_cfg_wr_hdr_6_i_0_8_.INIT = 4'h8; + LUT2_L com_cmm_u_cmm_errman_reg_cfg_wr_hdr_6_i_0_8_ ( + .I0(com_cmm_u_cmm_errman_N_59526), + .I1(cfg_err_tlp_cpl_header_6100[8]), + .LO(com_cmm_u_cmm_errman_N_39857_i) + ); + defparam com_cmm_u_cmm_errman_reg_cfg_wr_hdr_6_i_0_7_.INIT = 4'h8; + LUT2_L com_cmm_u_cmm_errman_reg_cfg_wr_hdr_6_i_0_7_ ( + .I0(com_cmm_u_cmm_errman_N_59526), + .I1(cfg_err_tlp_cpl_header_6100[7]), + .LO(com_cmm_u_cmm_errman_N_39855_i) + ); + defparam com_cmm_u_cmm_errman_reg_cfg_wr_hdr_6_i_0_6_.INIT = 4'h8; + LUT2_L com_cmm_u_cmm_errman_reg_cfg_wr_hdr_6_i_0_6_ ( + .I0(com_cmm_u_cmm_errman_N_59526), + .I1(cfg_err_tlp_cpl_header_6100[6]), + .LO(com_cmm_u_cmm_errman_N_39853_i) + ); + defparam com_cmm_u_cmm_errman_reg_cfg_wr_hdr_6_i_0_5_.INIT = 4'h8; + LUT2_L com_cmm_u_cmm_errman_reg_cfg_wr_hdr_6_i_0_5_ ( + .I0(com_cmm_u_cmm_errman_N_59526), + .I1(cfg_err_tlp_cpl_header_6100[5]), + .LO(com_cmm_u_cmm_errman_N_39851_i) + ); + defparam com_cmm_u_cmm_errman_reg_cfg_wr_hdr_6_i_0_4_.INIT = 4'h8; + LUT2_L com_cmm_u_cmm_errman_reg_cfg_wr_hdr_6_i_0_4_ ( + .I0(com_cmm_u_cmm_errman_N_59526), + .I1(cfg_err_tlp_cpl_header_6100[4]), + .LO(com_cmm_u_cmm_errman_N_39849_i) + ); + defparam com_cmm_u_cmm_errman_reg_cfg_wr_hdr_6_i_0_3_.INIT = 4'h8; + LUT2_L com_cmm_u_cmm_errman_reg_cfg_wr_hdr_6_i_0_3_ ( + .I0(com_cmm_u_cmm_errman_N_59526), + .I1(cfg_err_tlp_cpl_header_6100[3]), + .LO(com_cmm_u_cmm_errman_N_39847_i) + ); + defparam com_cmm_u_cmm_errman_reg_cfg_wr_hdr_6_i_0_2_.INIT = 4'h8; + LUT2_L com_cmm_u_cmm_errman_reg_cfg_wr_hdr_6_i_0_2_ ( + .I0(com_cmm_u_cmm_errman_N_59526), + .I1(cfg_err_tlp_cpl_header_6100[2]), + .LO(com_cmm_u_cmm_errman_N_39845_i) + ); + defparam com_cmm_u_cmm_errman_reg_cfg_wr_hdr_6_i_0_31_.INIT = 4'h8; + LUT2_L com_cmm_u_cmm_errman_reg_cfg_wr_hdr_6_i_0_31_ ( + .I0(com_cmm_u_cmm_errman_N_59526), + .I1(cfg_err_tlp_cpl_header_6100[31]), + .LO(com_cmm_u_cmm_errman_N_39903_i) + ); + defparam com_cmm_u_cmm_errman_reg_cfg_wr_hdr_6_i_0_30_.INIT = 4'h8; + LUT2_L com_cmm_u_cmm_errman_reg_cfg_wr_hdr_6_i_0_30_ ( + .I0(com_cmm_u_cmm_errman_N_59526), + .I1(cfg_err_tlp_cpl_header_6100[30]), + .LO(com_cmm_u_cmm_errman_N_39901_i) + ); + defparam com_cmm_u_cmm_errman_reg_cfg_wr_hdr_6_i_0_29_.INIT = 4'h8; + LUT2_L com_cmm_u_cmm_errman_reg_cfg_wr_hdr_6_i_0_29_ ( + .I0(com_cmm_u_cmm_errman_N_59526), + .I1(cfg_err_tlp_cpl_header_6100[29]), + .LO(com_cmm_u_cmm_errman_N_39899_i) + ); + defparam com_cmm_u_cmm_errman_reg_cfg_wr_hdr_6_i_0_28_.INIT = 4'h8; + LUT2_L com_cmm_u_cmm_errman_reg_cfg_wr_hdr_6_i_0_28_ ( + .I0(com_cmm_u_cmm_errman_N_59526), + .I1(cfg_err_tlp_cpl_header_6100[28]), + .LO(com_cmm_u_cmm_errman_N_39897_i) + ); + defparam com_cmm_u_cmm_errman_reg_cfg_wr_hdr_6_i_0_27_.INIT = 4'h8; + LUT2_L com_cmm_u_cmm_errman_reg_cfg_wr_hdr_6_i_0_27_ ( + .I0(com_cmm_u_cmm_errman_N_59526), + .I1(cfg_err_tlp_cpl_header_6100[27]), + .LO(com_cmm_u_cmm_errman_N_39895_i) + ); + defparam com_cmm_u_cmm_errman_reg_cfg_wr_hdr_6_i_0_26_.INIT = 4'h8; + LUT2_L com_cmm_u_cmm_errman_reg_cfg_wr_hdr_6_i_0_26_ ( + .I0(com_cmm_u_cmm_errman_N_59526), + .I1(cfg_err_tlp_cpl_header_6100[26]), + .LO(com_cmm_u_cmm_errman_N_39893_i) + ); + defparam com_cmm_u_cmm_errman_reg_cfg_wr_hdr_6_i_0_25_.INIT = 4'h8; + LUT2_L com_cmm_u_cmm_errman_reg_cfg_wr_hdr_6_i_0_25_ ( + .I0(com_cmm_u_cmm_errman_N_59526), + .I1(cfg_err_tlp_cpl_header_6100[25]), + .LO(com_cmm_u_cmm_errman_N_39891_i) + ); + defparam com_cmm_u_cmm_errman_reg_cfg_wr_hdr_6_i_0_24_.INIT = 4'h8; + LUT2_L com_cmm_u_cmm_errman_reg_cfg_wr_hdr_6_i_0_24_ ( + .I0(com_cmm_u_cmm_errman_N_59526), + .I1(cfg_err_tlp_cpl_header_6100[24]), + .LO(com_cmm_u_cmm_errman_N_39889_i) + ); + defparam com_cmm_u_cmm_errman_reg_cfg_wr_hdr_6_i_0_23_.INIT = 4'h8; + LUT2_L com_cmm_u_cmm_errman_reg_cfg_wr_hdr_6_i_0_23_ ( + .I0(com_cmm_u_cmm_errman_N_59526), + .I1(cfg_err_tlp_cpl_header_6100[23]), + .LO(com_cmm_u_cmm_errman_N_39887_i) + ); + defparam com_cmm_u_cmm_errman_reg_cfg_wr_hdr_6_i_0_22_.INIT = 4'h8; + LUT2_L com_cmm_u_cmm_errman_reg_cfg_wr_hdr_6_i_0_22_ ( + .I0(com_cmm_u_cmm_errman_N_59526), + .I1(cfg_err_tlp_cpl_header_6100[22]), + .LO(com_cmm_u_cmm_errman_N_39885_i) + ); + defparam com_cmm_u_cmm_errman_reg_cfg_wr_hdr_6_i_0_21_.INIT = 4'h8; + LUT2_L com_cmm_u_cmm_errman_reg_cfg_wr_hdr_6_i_0_21_ ( + .I0(com_cmm_u_cmm_errman_N_59526), + .I1(cfg_err_tlp_cpl_header_6100[21]), + .LO(com_cmm_u_cmm_errman_N_39883_i) + ); + defparam com_cmm_u_cmm_errman_reg_cfg_wr_hdr_6_i_0_20_.INIT = 4'h8; + LUT2_L com_cmm_u_cmm_errman_reg_cfg_wr_hdr_6_i_0_20_ ( + .I0(com_cmm_u_cmm_errman_N_59526), + .I1(cfg_err_tlp_cpl_header_6100[20]), + .LO(com_cmm_u_cmm_errman_N_39881_i) + ); + defparam com_cmm_u_cmm_errman_reg_cfg_wr_hdr_6_i_0_19_.INIT = 4'h8; + LUT2_L com_cmm_u_cmm_errman_reg_cfg_wr_hdr_6_i_0_19_ ( + .I0(com_cmm_u_cmm_errman_N_59526), + .I1(cfg_err_tlp_cpl_header_6100[19]), + .LO(com_cmm_u_cmm_errman_N_39879_i) + ); + defparam com_cmm_u_cmm_errman_reg_cfg_wr_hdr_6_i_0_18_.INIT = 4'h8; + LUT2_L com_cmm_u_cmm_errman_reg_cfg_wr_hdr_6_i_0_18_ ( + .I0(com_cmm_u_cmm_errman_N_59526), + .I1(cfg_err_tlp_cpl_header_6100[18]), + .LO(com_cmm_u_cmm_errman_N_39877_i) + ); + defparam com_cmm_u_cmm_errman_reg_cfg_wr_hdr_6_i_0_17_.INIT = 4'h8; + LUT2_L com_cmm_u_cmm_errman_reg_cfg_wr_hdr_6_i_0_17_ ( + .I0(com_cmm_u_cmm_errman_N_59526), + .I1(cfg_err_tlp_cpl_header_6100[17]), + .LO(com_cmm_u_cmm_errman_N_39875_i) + ); + defparam com_cmm_u_cmm_errman_reg_cfg_wr_hdr_6_i_0_46_.INIT = 4'h8; + LUT2_L com_cmm_u_cmm_errman_reg_cfg_wr_hdr_6_i_0_46_ ( + .I0(com_cmm_u_cmm_errman_N_59526), + .I1(cfg_err_tlp_cpl_header_6100[46]), + .LO(com_cmm_u_cmm_errman_N_39933_i) + ); + defparam com_cmm_u_cmm_errman_reg_cfg_wr_hdr_6_i_0_45_.INIT = 4'h8; + LUT2_L com_cmm_u_cmm_errman_reg_cfg_wr_hdr_6_i_0_45_ ( + .I0(com_cmm_u_cmm_errman_N_59526), + .I1(cfg_err_tlp_cpl_header_6100[45]), + .LO(com_cmm_u_cmm_errman_N_39931_i) + ); + defparam com_cmm_u_cmm_errman_reg_cfg_wr_hdr_6_i_0_44_.INIT = 4'h8; + LUT2_L com_cmm_u_cmm_errman_reg_cfg_wr_hdr_6_i_0_44_ ( + .I0(com_cmm_u_cmm_errman_N_59526), + .I1(cfg_err_tlp_cpl_header_6100[44]), + .LO(com_cmm_u_cmm_errman_N_39929_i) + ); + defparam com_cmm_u_cmm_errman_reg_cfg_wr_hdr_6_i_0_43_.INIT = 4'h8; + LUT2_L com_cmm_u_cmm_errman_reg_cfg_wr_hdr_6_i_0_43_ ( + .I0(com_cmm_u_cmm_errman_N_59526), + .I1(cfg_err_tlp_cpl_header_6100[43]), + .LO(com_cmm_u_cmm_errman_N_39927_i) + ); + defparam com_cmm_u_cmm_errman_reg_cfg_wr_hdr_6_i_0_42_.INIT = 4'h8; + LUT2_L com_cmm_u_cmm_errman_reg_cfg_wr_hdr_6_i_0_42_ ( + .I0(com_cmm_u_cmm_errman_N_59526), + .I1(cfg_err_tlp_cpl_header_6100[42]), + .LO(com_cmm_u_cmm_errman_N_39925_i) + ); + defparam com_cmm_u_cmm_errman_reg_cfg_wr_hdr_6_i_0_41_.INIT = 4'h8; + LUT2_L com_cmm_u_cmm_errman_reg_cfg_wr_hdr_6_i_0_41_ ( + .I0(com_cmm_u_cmm_errman_N_59526), + .I1(cfg_err_tlp_cpl_header_6100[41]), + .LO(com_cmm_u_cmm_errman_N_39923_i) + ); + defparam com_cmm_u_cmm_errman_reg_cfg_wr_hdr_6_i_0_40_.INIT = 4'h8; + LUT2_L com_cmm_u_cmm_errman_reg_cfg_wr_hdr_6_i_0_40_ ( + .I0(com_cmm_u_cmm_errman_N_59526), + .I1(cfg_err_tlp_cpl_header_6100[40]), + .LO(com_cmm_u_cmm_errman_N_39921_i) + ); + defparam com_cmm_u_cmm_errman_reg_cfg_wr_hdr_6_i_0_39_.INIT = 4'h8; + LUT2_L com_cmm_u_cmm_errman_reg_cfg_wr_hdr_6_i_0_39_ ( + .I0(com_cmm_u_cmm_errman_N_59526), + .I1(cfg_err_tlp_cpl_header_6100[39]), + .LO(com_cmm_u_cmm_errman_N_39919_i) + ); + defparam com_cmm_u_cmm_errman_reg_cfg_wr_hdr_6_i_0_38_.INIT = 4'h8; + LUT2_L com_cmm_u_cmm_errman_reg_cfg_wr_hdr_6_i_0_38_ ( + .I0(com_cmm_u_cmm_errman_N_59526), + .I1(cfg_err_tlp_cpl_header_6100[38]), + .LO(com_cmm_u_cmm_errman_N_39917_i) + ); + defparam com_cmm_u_cmm_errman_reg_cfg_wr_hdr_6_i_0_37_.INIT = 4'h8; + LUT2_L com_cmm_u_cmm_errman_reg_cfg_wr_hdr_6_i_0_37_ ( + .I0(com_cmm_u_cmm_errman_N_59526), + .I1(cfg_err_tlp_cpl_header_6100[37]), + .LO(com_cmm_u_cmm_errman_N_39915_i) + ); + defparam com_cmm_u_cmm_errman_reg_cfg_wr_hdr_6_i_0_36_.INIT = 4'h8; + LUT2_L com_cmm_u_cmm_errman_reg_cfg_wr_hdr_6_i_0_36_ ( + .I0(com_cmm_u_cmm_errman_N_59526), + .I1(cfg_err_tlp_cpl_header_6100[36]), + .LO(com_cmm_u_cmm_errman_N_39913_i) + ); + defparam com_cmm_u_cmm_errman_reg_cfg_wr_hdr_6_i_0_35_.INIT = 4'h8; + LUT2_L com_cmm_u_cmm_errman_reg_cfg_wr_hdr_6_i_0_35_ ( + .I0(com_cmm_u_cmm_errman_N_59526), + .I1(cfg_err_tlp_cpl_header_6100[35]), + .LO(com_cmm_u_cmm_errman_N_39911_i) + ); + defparam com_cmm_u_cmm_errman_reg_cfg_wr_hdr_6_i_0_34_.INIT = 4'h8; + LUT2_L com_cmm_u_cmm_errman_reg_cfg_wr_hdr_6_i_0_34_ ( + .I0(com_cmm_u_cmm_errman_N_59526), + .I1(cfg_err_tlp_cpl_header_6100[34]), + .LO(com_cmm_u_cmm_errman_N_39909_i) + ); + defparam com_cmm_u_cmm_errman_reg_cfg_wr_hdr_6_i_0_33_.INIT = 4'h8; + LUT2_L com_cmm_u_cmm_errman_reg_cfg_wr_hdr_6_i_0_33_ ( + .I0(com_cmm_u_cmm_errman_N_59526), + .I1(cfg_err_tlp_cpl_header_6100[33]), + .LO(com_cmm_u_cmm_errman_N_39907_i) + ); + defparam com_cmm_u_cmm_errman_reg_cfg_wr_hdr_6_i_0_32_.INIT = 4'h8; + LUT2_L com_cmm_u_cmm_errman_reg_cfg_wr_hdr_6_i_0_32_ ( + .I0(com_cmm_u_cmm_errman_N_59526), + .I1(cfg_err_tlp_cpl_header_6100[32]), + .LO(com_cmm_u_cmm_errman_N_39905_i) + ); + defparam com_cmm_u_cmm_errman_reg_cmt_wr_hdr_5_0_a2_0_a2_9_.INIT = 4'h8; + LUT2_L com_cmm_u_cmm_errman_reg_cmt_wr_hdr_5_0_a2_0_a2_9_ ( + .I0(com_cmm_u_cmm_errman_N_55916_i), + .I1(com_cmmt_err_tlp_hdr[9]), + .LO(com_cmm_u_cmm_errman_reg_cmt_wr_hdr_5[9]) + ); + defparam com_cmm_u_cmm_errman_reg_cmt_wr_hdr_5_0_a2_0_a2_8_.INIT = 4'h8; + LUT2_L com_cmm_u_cmm_errman_reg_cmt_wr_hdr_5_0_a2_0_a2_8_ ( + .I0(com_cmm_u_cmm_errman_N_55916_i), + .I1(com_cmmt_err_tlp_hdr[8]), + .LO(com_cmm_u_cmm_errman_reg_cmt_wr_hdr_5[8]) + ); + defparam com_cmm_u_cmm_errman_reg_cmt_wr_hdr_5_0_a2_0_a2_7_.INIT = 4'h8; + LUT2_L com_cmm_u_cmm_errman_reg_cmt_wr_hdr_5_0_a2_0_a2_7_ ( + .I0(com_cmm_u_cmm_errman_N_55916_i), + .I1(com_cmmt_err_tlp_hdr[7]), + .LO(com_cmm_u_cmm_errman_reg_cmt_wr_hdr_5[7]) + ); + defparam com_cmm_u_cmm_errman_reg_cmt_wr_hdr_5_0_a2_0_a2_6_.INIT = 4'h8; + LUT2_L com_cmm_u_cmm_errman_reg_cmt_wr_hdr_5_0_a2_0_a2_6_ ( + .I0(com_cmm_u_cmm_errman_N_55916_i), + .I1(com_cmmt_err_tlp_hdr[6]), + .LO(com_cmm_u_cmm_errman_reg_cmt_wr_hdr_5[6]) + ); + defparam com_cmm_u_cmm_errman_reg_cmt_wr_hdr_5_0_a2_0_a2_5_.INIT = 4'h8; + LUT2_L com_cmm_u_cmm_errman_reg_cmt_wr_hdr_5_0_a2_0_a2_5_ ( + .I0(com_cmm_u_cmm_errman_N_55916_i), + .I1(com_cmmt_err_tlp_hdr[5]), + .LO(com_cmm_u_cmm_errman_reg_cmt_wr_hdr_5[5]) + ); + defparam com_cmm_u_cmm_errman_reg_cmt_wr_hdr_5_0_a2_0_a2_4_.INIT = 4'h8; + LUT2_L com_cmm_u_cmm_errman_reg_cmt_wr_hdr_5_0_a2_0_a2_4_ ( + .I0(com_cmm_u_cmm_errman_N_55916_i), + .I1(com_cmmt_err_tlp_hdr[4]), + .LO(com_cmm_u_cmm_errman_reg_cmt_wr_hdr_5[4]) + ); + defparam com_cmm_u_cmm_errman_reg_cmt_wr_hdr_5_0_a2_0_a2_3_.INIT = 4'h8; + LUT2_L com_cmm_u_cmm_errman_reg_cmt_wr_hdr_5_0_a2_0_a2_3_ ( + .I0(com_cmm_u_cmm_errman_N_55916_i), + .I1(com_cmmt_err_tlp_hdr[3]), + .LO(com_cmm_u_cmm_errman_reg_cmt_wr_hdr_5[3]) + ); + defparam com_cmm_u_cmm_errman_reg_cmt_wr_hdr_5_0_a2_0_a2_2_.INIT = 4'h8; + LUT2_L com_cmm_u_cmm_errman_reg_cmt_wr_hdr_5_0_a2_0_a2_2_ ( + .I0(com_cmm_u_cmm_errman_N_55916_i), + .I1(com_cmmt_err_tlp_hdr[2]), + .LO(com_cmm_u_cmm_errman_reg_cmt_wr_hdr_5[2]) + ); + defparam com_cmm_u_cmm_errman_reg_cmt_wr_hdr_5_0_a2_0_a2_1_.INIT = 4'h8; + LUT2_L com_cmm_u_cmm_errman_reg_cmt_wr_hdr_5_0_a2_0_a2_1_ ( + .I0(com_cmm_u_cmm_errman_N_55916_i), + .I1(com_cmmt_err_tlp_hdr[1]), + .LO(com_cmm_u_cmm_errman_reg_cmt_wr_hdr_5[1]) + ); + defparam com_cmm_u_cmm_errman_reg_cmt_wr_hdr_5_0_a2_0_a2_0_.INIT = 4'h8; + LUT2_L com_cmm_u_cmm_errman_reg_cmt_wr_hdr_5_0_a2_0_a2_0_ ( + .I0(com_cmm_u_cmm_errman_N_55916_i), + .I1(com_cmmt_err_tlp_hdr[0]), + .LO(com_cmm_u_cmm_errman_reg_cmt_wr_hdr_5[0]) + ); + defparam com_cmm_u_cmm_errman_reg_cfg_wp_4_axbxc1.INIT = 8'h6C; + LUT3_L com_cmm_u_cmm_errman_reg_cfg_wp_4_axbxc1 ( + .I0(com_cmm_u_cmm_errman_reg_cfg_wp[0]), + .I1(com_cmm_u_cmm_errman_reg_cfg_wp[1]), + .I2(com_cmm_u_cmm_errman_reg_incr_cplu_5852), + .LO(com_cmm_u_cmm_errman_reg_cfg_wp_4[1]) + ); + defparam com_cmm_u_cmm_errman_reg_cfg_wp_4_axbxc0.INIT = 4'h6; + LUT2_L com_cmm_u_cmm_errman_reg_cfg_wp_4_axbxc0 ( + .I0(com_cmm_u_cmm_errman_reg_cfg_wp[0]), + .I1(com_cmm_u_cmm_errman_reg_incr_cplu_5852), + .LO(com_cmm_u_cmm_errman_reg_cfg_wp_4[0]) + ); + defparam com_cmm_u_cmm_errman_reg_cfg_wr_hdr20_0_a2.INIT = 4'h8; + LUT2_L com_cmm_u_cmm_errman_reg_cfg_wr_hdr20_0_a2 ( + .I0(cfg_err_ur_n), + .I1(com_cmm_u_cmm_errman_cfg_is_np_and_cpl_abort), + .LO(com_cmm_u_cmm_errman_reg_cfg_wr_hdr20) + ); + defparam com_cmm_u_cmm_errman_cfg_is_np_and_ur_0_a2_0_a2.INIT = 4'h2; + LUT2_L com_cmm_u_cmm_errman_cfg_is_np_and_ur_0_a2_0_a2 ( + .I0(cfg_err_posted_n), + .I1(cfg_err_ur_n), + .LO(com_cmm_u_cmm_errman_cfg_is_np_and_ur) + ); + defparam com_cmm_u_cmm_errman_reg_cfg_wr_hdr_6_i_0_47_.INIT = 4'h8; + LUT2_L com_cmm_u_cmm_errman_reg_cfg_wr_hdr_6_i_0_47_ ( + .I0(com_cmm_u_cmm_errman_N_59526), + .I1(cfg_err_tlp_cpl_header_6100[47]), + .LO(com_cmm_u_cmm_errman_N_39935_i) + ); + defparam com_cmm_u_cmm_errman_reg_cmt_wr_hdr_5_0_a2_0_a2_24_.INIT = 4'h8; + LUT2_L com_cmm_u_cmm_errman_reg_cmt_wr_hdr_5_0_a2_0_a2_24_ ( + .I0(com_cmm_u_cmm_errman_N_55916_i), + .I1(com_cmmt_err_tlp_hdr[24]), + .LO(com_cmm_u_cmm_errman_reg_cmt_wr_hdr_5[24]) + ); + defparam com_cmm_u_cmm_errman_reg_cmt_wr_hdr_5_0_a2_0_a2_23_.INIT = 4'h8; + LUT2_L com_cmm_u_cmm_errman_reg_cmt_wr_hdr_5_0_a2_0_a2_23_ ( + .I0(com_cmm_u_cmm_errman_N_55916_i), + .I1(com_cmmt_err_tlp_hdr[23]), + .LO(com_cmm_u_cmm_errman_reg_cmt_wr_hdr_5[23]) + ); + defparam com_cmm_u_cmm_errman_reg_cmt_wr_hdr_5_0_a2_0_a2_22_.INIT = 4'h8; + LUT2_L com_cmm_u_cmm_errman_reg_cmt_wr_hdr_5_0_a2_0_a2_22_ ( + .I0(com_cmm_u_cmm_errman_N_55916_i), + .I1(com_cmmt_err_tlp_hdr[22]), + .LO(com_cmm_u_cmm_errman_reg_cmt_wr_hdr_5[22]) + ); + defparam com_cmm_u_cmm_errman_reg_cmt_wr_hdr_5_0_a2_0_a2_21_.INIT = 4'h8; + LUT2_L com_cmm_u_cmm_errman_reg_cmt_wr_hdr_5_0_a2_0_a2_21_ ( + .I0(com_cmm_u_cmm_errman_N_55916_i), + .I1(com_cmmt_err_tlp_hdr[21]), + .LO(com_cmm_u_cmm_errman_reg_cmt_wr_hdr_5[21]) + ); + defparam com_cmm_u_cmm_errman_reg_cmt_wr_hdr_5_0_a2_0_a2_20_.INIT = 4'h8; + LUT2_L com_cmm_u_cmm_errman_reg_cmt_wr_hdr_5_0_a2_0_a2_20_ ( + .I0(com_cmm_u_cmm_errman_N_55916_i), + .I1(com_cmmt_err_tlp_hdr[20]), + .LO(com_cmm_u_cmm_errman_reg_cmt_wr_hdr_5[20]) + ); + defparam com_cmm_u_cmm_errman_reg_cmt_wr_hdr_5_0_a2_0_a2_19_.INIT = 4'h8; + LUT2_L com_cmm_u_cmm_errman_reg_cmt_wr_hdr_5_0_a2_0_a2_19_ ( + .I0(com_cmm_u_cmm_errman_N_55916_i), + .I1(com_cmmt_err_tlp_hdr[19]), + .LO(com_cmm_u_cmm_errman_reg_cmt_wr_hdr_5[19]) + ); + defparam com_cmm_u_cmm_errman_reg_cmt_wr_hdr_5_0_a2_0_a2_18_.INIT = 4'h8; + LUT2_L com_cmm_u_cmm_errman_reg_cmt_wr_hdr_5_0_a2_0_a2_18_ ( + .I0(com_cmm_u_cmm_errman_N_55916_i), + .I1(com_cmmt_err_tlp_hdr[18]), + .LO(com_cmm_u_cmm_errman_reg_cmt_wr_hdr_5[18]) + ); + defparam com_cmm_u_cmm_errman_reg_cmt_wr_hdr_5_0_a2_0_a2_17_.INIT = 4'h8; + LUT2_L com_cmm_u_cmm_errman_reg_cmt_wr_hdr_5_0_a2_0_a2_17_ ( + .I0(com_cmm_u_cmm_errman_N_55916_i), + .I1(com_cmmt_err_tlp_hdr[17]), + .LO(com_cmm_u_cmm_errman_reg_cmt_wr_hdr_5[17]) + ); + defparam com_cmm_u_cmm_errman_reg_cmt_wr_hdr_5_0_a2_0_a2_16_.INIT = 4'h8; + LUT2_L com_cmm_u_cmm_errman_reg_cmt_wr_hdr_5_0_a2_0_a2_16_ ( + .I0(com_cmm_u_cmm_errman_N_55916_i), + .I1(com_cmmt_err_tlp_hdr[16]), + .LO(com_cmm_u_cmm_errman_reg_cmt_wr_hdr_5[16]) + ); + defparam com_cmm_u_cmm_errman_reg_cmt_wr_hdr_5_0_a2_0_a2_15_.INIT = 4'h8; + LUT2_L com_cmm_u_cmm_errman_reg_cmt_wr_hdr_5_0_a2_0_a2_15_ ( + .I0(com_cmm_u_cmm_errman_N_55916_i), + .I1(com_cmmt_err_tlp_hdr[15]), + .LO(com_cmm_u_cmm_errman_reg_cmt_wr_hdr_5[15]) + ); + defparam com_cmm_u_cmm_errman_reg_cmt_wr_hdr_5_0_a2_0_a2_14_.INIT = 4'h8; + LUT2_L com_cmm_u_cmm_errman_reg_cmt_wr_hdr_5_0_a2_0_a2_14_ ( + .I0(com_cmm_u_cmm_errman_N_55916_i), + .I1(com_cmmt_err_tlp_hdr[14]), + .LO(com_cmm_u_cmm_errman_reg_cmt_wr_hdr_5[14]) + ); + defparam com_cmm_u_cmm_errman_reg_cmt_wr_hdr_5_0_a2_0_a2_13_.INIT = 4'h8; + LUT2_L com_cmm_u_cmm_errman_reg_cmt_wr_hdr_5_0_a2_0_a2_13_ ( + .I0(com_cmm_u_cmm_errman_N_55916_i), + .I1(com_cmmt_err_tlp_hdr[13]), + .LO(com_cmm_u_cmm_errman_reg_cmt_wr_hdr_5[13]) + ); + defparam com_cmm_u_cmm_errman_reg_cmt_wr_hdr_5_0_a2_0_a2_12_.INIT = 4'h8; + LUT2_L com_cmm_u_cmm_errman_reg_cmt_wr_hdr_5_0_a2_0_a2_12_ ( + .I0(com_cmm_u_cmm_errman_N_55916_i), + .I1(com_cmmt_err_tlp_hdr[12]), + .LO(com_cmm_u_cmm_errman_reg_cmt_wr_hdr_5[12]) + ); + defparam com_cmm_u_cmm_errman_reg_cmt_wr_hdr_5_0_a2_0_a2_11_.INIT = 4'h8; + LUT2_L com_cmm_u_cmm_errman_reg_cmt_wr_hdr_5_0_a2_0_a2_11_ ( + .I0(com_cmm_u_cmm_errman_N_55916_i), + .I1(com_cmmt_err_tlp_hdr[11]), + .LO(com_cmm_u_cmm_errman_reg_cmt_wr_hdr_5[11]) + ); + defparam com_cmm_u_cmm_errman_reg_cmt_wr_hdr_5_0_a2_0_a2_10_.INIT = 4'h8; + LUT2_L com_cmm_u_cmm_errman_reg_cmt_wr_hdr_5_0_a2_0_a2_10_ ( + .I0(com_cmm_u_cmm_errman_N_55916_i), + .I1(com_cmmt_err_tlp_hdr[10]), + .LO(com_cmm_u_cmm_errman_reg_cmt_wr_hdr_5[10]) + ); + defparam com_cmm_u_cmm_errman_reg_cmt_wr_hdr_5_0_a2_0_a2_39_.INIT = 4'h8; + LUT2_L com_cmm_u_cmm_errman_reg_cmt_wr_hdr_5_0_a2_0_a2_39_ ( + .I0(com_cmm_u_cmm_errman_N_55916_i), + .I1(com_cmmt_err_tlp_hdr[39]), + .LO(com_cmm_u_cmm_errman_reg_cmt_wr_hdr_5[39]) + ); + defparam com_cmm_u_cmm_errman_reg_cmt_wr_hdr_5_0_a2_0_a2_38_.INIT = 4'h8; + LUT2_L com_cmm_u_cmm_errman_reg_cmt_wr_hdr_5_0_a2_0_a2_38_ ( + .I0(com_cmm_u_cmm_errman_N_55916_i), + .I1(com_cmmt_err_tlp_hdr[38]), + .LO(com_cmm_u_cmm_errman_reg_cmt_wr_hdr_5[38]) + ); + defparam com_cmm_u_cmm_errman_reg_cmt_wr_hdr_5_0_a2_0_a2_37_.INIT = 4'h8; + LUT2_L com_cmm_u_cmm_errman_reg_cmt_wr_hdr_5_0_a2_0_a2_37_ ( + .I0(com_cmm_u_cmm_errman_N_55916_i), + .I1(com_cmmt_err_tlp_hdr[37]), + .LO(com_cmm_u_cmm_errman_reg_cmt_wr_hdr_5[37]) + ); + defparam com_cmm_u_cmm_errman_reg_cmt_wr_hdr_5_0_a2_0_a2_36_.INIT = 4'h8; + LUT2_L com_cmm_u_cmm_errman_reg_cmt_wr_hdr_5_0_a2_0_a2_36_ ( + .I0(com_cmm_u_cmm_errman_N_55916_i), + .I1(com_cmmt_err_tlp_hdr[36]), + .LO(com_cmm_u_cmm_errman_reg_cmt_wr_hdr_5[36]) + ); + defparam com_cmm_u_cmm_errman_reg_cmt_wr_hdr_5_0_a2_0_a2_35_.INIT = 4'h8; + LUT2_L com_cmm_u_cmm_errman_reg_cmt_wr_hdr_5_0_a2_0_a2_35_ ( + .I0(com_cmm_u_cmm_errman_N_55916_i), + .I1(com_cmmt_err_tlp_hdr[35]), + .LO(com_cmm_u_cmm_errman_reg_cmt_wr_hdr_5[35]) + ); + defparam com_cmm_u_cmm_errman_reg_cmt_wr_hdr_5_0_a2_0_a2_34_.INIT = 4'h8; + LUT2_L com_cmm_u_cmm_errman_reg_cmt_wr_hdr_5_0_a2_0_a2_34_ ( + .I0(com_cmm_u_cmm_errman_N_55916_i), + .I1(com_cmmt_err_tlp_hdr[34]), + .LO(com_cmm_u_cmm_errman_reg_cmt_wr_hdr_5[34]) + ); + defparam com_cmm_u_cmm_errman_reg_cmt_wr_hdr_5_0_a2_0_a2_33_.INIT = 4'h8; + LUT2_L com_cmm_u_cmm_errman_reg_cmt_wr_hdr_5_0_a2_0_a2_33_ ( + .I0(com_cmm_u_cmm_errman_N_55916_i), + .I1(com_cmmt_err_tlp_hdr[33]), + .LO(com_cmm_u_cmm_errman_reg_cmt_wr_hdr_5[33]) + ); + defparam com_cmm_u_cmm_errman_reg_cmt_wr_hdr_5_0_a2_0_a2_32_.INIT = 4'h8; + LUT2_L com_cmm_u_cmm_errman_reg_cmt_wr_hdr_5_0_a2_0_a2_32_ ( + .I0(com_cmm_u_cmm_errman_N_55916_i), + .I1(com_cmmt_err_tlp_hdr[32]), + .LO(com_cmm_u_cmm_errman_reg_cmt_wr_hdr_5[32]) + ); + defparam com_cmm_u_cmm_errman_reg_cmt_wr_hdr_5_0_a2_0_a2_31_.INIT = 4'h8; + LUT2_L com_cmm_u_cmm_errman_reg_cmt_wr_hdr_5_0_a2_0_a2_31_ ( + .I0(com_cmm_u_cmm_errman_N_55916_i), + .I1(com_cmmt_err_tlp_hdr[31]), + .LO(com_cmm_u_cmm_errman_reg_cmt_wr_hdr_5[31]) + ); + defparam com_cmm_u_cmm_errman_reg_cmt_wr_hdr_5_0_a2_0_a2_30_.INIT = 4'h8; + LUT2_L com_cmm_u_cmm_errman_reg_cmt_wr_hdr_5_0_a2_0_a2_30_ ( + .I0(com_cmm_u_cmm_errman_N_55916_i), + .I1(com_cmmt_err_tlp_hdr[30]), + .LO(com_cmm_u_cmm_errman_reg_cmt_wr_hdr_5[30]) + ); + defparam com_cmm_u_cmm_errman_reg_cmt_wr_hdr_5_0_a2_0_a2_29_.INIT = 4'h8; + LUT2_L com_cmm_u_cmm_errman_reg_cmt_wr_hdr_5_0_a2_0_a2_29_ ( + .I0(com_cmm_u_cmm_errman_N_55916_i), + .I1(com_cmmt_err_tlp_hdr[29]), + .LO(com_cmm_u_cmm_errman_reg_cmt_wr_hdr_5[29]) + ); + defparam com_cmm_u_cmm_errman_reg_cmt_wr_hdr_5_0_a2_0_a2_28_.INIT = 4'h8; + LUT2_L com_cmm_u_cmm_errman_reg_cmt_wr_hdr_5_0_a2_0_a2_28_ ( + .I0(com_cmm_u_cmm_errman_N_55916_i), + .I1(com_cmmt_err_tlp_hdr[28]), + .LO(com_cmm_u_cmm_errman_reg_cmt_wr_hdr_5[28]) + ); + defparam com_cmm_u_cmm_errman_reg_cmt_wr_hdr_5_0_a2_0_a2_27_.INIT = 4'h8; + LUT2_L com_cmm_u_cmm_errman_reg_cmt_wr_hdr_5_0_a2_0_a2_27_ ( + .I0(com_cmm_u_cmm_errman_N_55916_i), + .I1(com_cmmt_err_tlp_hdr[27]), + .LO(com_cmm_u_cmm_errman_reg_cmt_wr_hdr_5[27]) + ); + defparam com_cmm_u_cmm_errman_reg_cmt_wr_hdr_5_0_a2_0_a2_26_.INIT = 4'h8; + LUT2_L com_cmm_u_cmm_errman_reg_cmt_wr_hdr_5_0_a2_0_a2_26_ ( + .I0(com_cmm_u_cmm_errman_N_55916_i), + .I1(com_cmmt_err_tlp_hdr[26]), + .LO(com_cmm_u_cmm_errman_reg_cmt_wr_hdr_5[26]) + ); + defparam com_cmm_u_cmm_errman_reg_cmt_wr_hdr_5_0_a2_0_a2_25_.INIT = 4'h8; + LUT2_L com_cmm_u_cmm_errman_reg_cmt_wr_hdr_5_0_a2_0_a2_25_ ( + .I0(com_cmm_u_cmm_errman_N_55916_i), + .I1(com_cmmt_err_tlp_hdr[25]), + .LO(com_cmm_u_cmm_errman_reg_cmt_wr_hdr_5[25]) + ); + defparam com_cmm_u_cmm_errman_reg_cmt_wp_4_axbxc1.INIT = 8'h6C; + LUT3_L com_cmm_u_cmm_errman_reg_cmt_wp_4_axbxc1 ( + .I0(com_cmm_u_cmm_errman_reg_cmt_wp[0]), + .I1(com_cmm_u_cmm_errman_reg_cmt_wp[1]), + .I2(com_cmm_u_cmm_errman_reg_cmt_wr_hdr[48]), + .LO(com_cmm_u_cmm_errman_reg_cmt_wp_4[1]) + ); + defparam com_cmm_u_cmm_errman_reg_cmt_wp_4_axbxc0.INIT = 4'h6; + LUT2_L com_cmm_u_cmm_errman_reg_cmt_wp_4_axbxc0 ( + .I0(com_cmm_u_cmm_errman_reg_cmt_wp[0]), + .I1(com_cmm_u_cmm_errman_reg_cmt_wr_hdr[48]), + .LO(com_cmm_u_cmm_errman_reg_cmt_wp_4[0]) + ); + defparam com_cmm_u_cmm_errman_reg_cmt_wr_hdr_5_0_a2_0_a2_47_.INIT = 4'h8; + LUT2_L com_cmm_u_cmm_errman_reg_cmt_wr_hdr_5_0_a2_0_a2_47_ ( + .I0(com_cmm_u_cmm_errman_N_55916_i), + .I1(com_cmmt_err_tlp_hdr[47]), + .LO(com_cmm_u_cmm_errman_reg_cmt_wr_hdr_5[47]) + ); + defparam com_cmm_u_cmm_errman_reg_cmt_wr_hdr_5_0_a2_0_a2_46_.INIT = 4'h8; + LUT2_L com_cmm_u_cmm_errman_reg_cmt_wr_hdr_5_0_a2_0_a2_46_ ( + .I0(com_cmm_u_cmm_errman_N_55916_i), + .I1(com_cmmt_err_tlp_hdr[46]), + .LO(com_cmm_u_cmm_errman_reg_cmt_wr_hdr_5[46]) + ); + defparam com_cmm_u_cmm_errman_reg_cmt_wr_hdr_5_0_a2_0_a2_45_.INIT = 4'h8; + LUT2_L com_cmm_u_cmm_errman_reg_cmt_wr_hdr_5_0_a2_0_a2_45_ ( + .I0(com_cmm_u_cmm_errman_N_55916_i), + .I1(com_cmmt_err_tlp_hdr[45]), + .LO(com_cmm_u_cmm_errman_reg_cmt_wr_hdr_5[45]) + ); + defparam com_cmm_u_cmm_errman_reg_cmt_wr_hdr_5_0_a2_0_a2_44_.INIT = 4'h8; + LUT2_L com_cmm_u_cmm_errman_reg_cmt_wr_hdr_5_0_a2_0_a2_44_ ( + .I0(com_cmm_u_cmm_errman_N_55916_i), + .I1(com_cmmt_err_tlp_hdr[44]), + .LO(com_cmm_u_cmm_errman_reg_cmt_wr_hdr_5[44]) + ); + defparam com_cmm_u_cmm_errman_reg_cmt_wr_hdr_5_0_a2_0_a2_43_.INIT = 4'h8; + LUT2_L com_cmm_u_cmm_errman_reg_cmt_wr_hdr_5_0_a2_0_a2_43_ ( + .I0(com_cmm_u_cmm_errman_N_55916_i), + .I1(com_cmmt_err_tlp_hdr[43]), + .LO(com_cmm_u_cmm_errman_reg_cmt_wr_hdr_5[43]) + ); + defparam com_cmm_u_cmm_errman_reg_cmt_wr_hdr_5_0_a2_0_a2_42_.INIT = 4'h8; + LUT2_L com_cmm_u_cmm_errman_reg_cmt_wr_hdr_5_0_a2_0_a2_42_ ( + .I0(com_cmm_u_cmm_errman_N_55916_i), + .I1(com_cmmt_err_tlp_hdr[42]), + .LO(com_cmm_u_cmm_errman_reg_cmt_wr_hdr_5[42]) + ); + defparam com_cmm_u_cmm_errman_reg_cmt_wr_hdr_5_0_a2_0_a2_41_.INIT = 4'h8; + LUT2_L com_cmm_u_cmm_errman_reg_cmt_wr_hdr_5_0_a2_0_a2_41_ ( + .I0(com_cmm_u_cmm_errman_N_55916_i), + .I1(com_cmmt_err_tlp_hdr[41]), + .LO(com_cmm_u_cmm_errman_reg_cmt_wr_hdr_5[41]) + ); + defparam com_cmm_u_cmm_errman_reg_cmt_wr_hdr_5_0_a2_0_a2_40_.INIT = 4'h8; + LUT2_L com_cmm_u_cmm_errman_reg_cmt_wr_hdr_5_0_a2_0_a2_40_ ( + .I0(com_cmm_u_cmm_errman_N_55916_i), + .I1(com_cmmt_err_tlp_hdr[40]), + .LO(com_cmm_u_cmm_errman_reg_cmt_wr_hdr_5[40]) + ); + defparam com_cmm_u_cmm_errman_N_58392_i.INIT = 4'h1; + LUT1_L com_cmm_u_cmm_errman_N_58392_i ( + .I0(com_cmm_u_cmm_errman_reg_detectedcorrectable_3_i_0_0_0_a2_5829), + .LO(com_cmm_u_cmm_errman_N_58392_i_5828) + ); + defparam com_cmm_u_cmm_errman_replay_vld_i.INIT = 4'h1; + LUT1_L com_cmm_u_cmm_errman_replay_vld_i ( + .I0(com_replay_vld), + .LO(com_cmm_u_cmm_errman_replay_vld_i_5830) + ); + defparam com_cmm_u_cmm_errman_un1_cmmt_err_tlp_ur_i_0.INIT = 8'h40; + LUT3_L com_cmm_u_cmm_errman_un1_cmmt_err_tlp_ur_i_0 ( + .I0(com_cmm_u_cmm_errman_N_58592), + .I1(com_cmmt_err_tlp_p_cpl), + .I2(com_cmmt_err_tlp_ur), + .LO(com_cmm_u_cmm_errman_N_19038_i) + ); + defparam com_cmm_u_cmm_errman_N_86726_i.INIT = 8'hFE; + LUT3_L com_cmm_u_cmm_errman_N_86726_i ( + .I0(com_cmm_u_cmm_errman_N_58592), + .I1(cfg_err_posted_n), + .I2(cfg_err_ur_n), + .LO(com_cmm_u_cmm_errman_N_86726_i_5831) + ); + defparam com_cmm_u_cmm_errman_N_86392_i.INIT = 8'hF1; + LUT3_L com_cmm_u_cmm_errman_N_86392_i ( + .I0(NlwRenamedSig_OI_cfg_command_8_), + .I1(NlwRenamedSig_OI_cfg_dcommand[1]), + .I2(cfg_err_ecrc_n), + .LO(com_cmm_u_cmm_errman_N_86392_i_5832) + ); + defparam com_cmm_u_cmm_errman_N_86391_i.INIT = 8'hF1; + LUT3_L com_cmm_u_cmm_errman_N_86391_i ( + .I0(NlwRenamedSig_OI_cfg_command_8_), + .I1(NlwRenamedSig_OI_cfg_dcommand[1]), + .I2(cfg_err_cpl_timeout_n), + .LO(com_cmm_u_cmm_errman_N_86391_i_5833) + ); + defparam com_cmm_u_cmm_errman_reg_signaledsystemerror_9_i_0_1.INIT = 16'h0007; + LUT4_L com_cmm_u_cmm_errman_reg_signaledsystemerror_9_i_0_1 ( + .I0(com_cmm_N_56318_i), + .I1(NlwRenamedSig_OI_cfg_dcommand[3]), + .I2(com_cmm_u_cmm_errman_cs_is_cplu_5835), + .I3(com_cmm_u_cmm_errman_cs_is_ftl_5834), + .LO(com_cmm_u_cmm_errman_reg_signaledsystemerror_9_i_0_1_5910) + ); + defparam com_cmm_u_cmm_errman_request_9_i_i_i_a3_0_.INIT = 8'h02; + LUT3 com_cmm_u_cmm_errman_request_9_i_i_i_a3_0_ ( + .I0(com_cmm_u_cmm_errman_cs_fsm[1]), + .I1(com_cmm_u_cmm_errman_cs_fsm[2]), + .I2(com_cmm_u_cmm_errman_cs_fsm[0]), + .O(com_cmm_u_cmm_errman_N_20280_i_0) + ); + FDC com_cmm_u_cmm_errman_reg_receivedtargetabort ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmmt_stat_tlp_rx_cpl_abort), + .Q(com_cmm_receivedtargetabort), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_errman_reg_receivedmasterabort ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmmt_stat_tlp_rx_cpl_ur), + .Q(com_cmm_receivedmasterabort), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_errman_reg_detectedparityerror ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmmt_stat_tlp_rx_ep), + .Q(com_cmm_detectedparityerror), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_errman_cs_is_nfl ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_request_data31), + .Q(com_cmm_u_cmm_errman_cs_is_nfl_5911), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_errman_cs_is_ftl ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_request_data30), + .Q(com_cmm_u_cmm_errman_cs_is_ftl_5834), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_errman_cs_is_cplu ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_request_data28), + .Q(com_cmm_u_cmm_errman_cs_is_cplu_5835), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_errman_cs_is_cplt ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_N_20280_i_0), + .Q(com_cmm_u_cmm_errman_cs_is_cplt_5836), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_errman_cs_is_cor ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_request_data32), + .Q(com_cmm_u_cmm_errman_cs_is_cor_5837), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_errman_reg_signaledtargetabort ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_cfg_is_np_and_cpl_abort), + .Q(com_cmm_signaledtargetabort), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_errman_reg_unsupportedreq ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_N_86725_i_5838), + .Q(com_cmm_unsupportedreq), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_errman_reg_masterdataparityerror ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_reg_masterdataparityerror_3_5839), + .Q(com_cmm_masterdataparityerror), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_errman_send_nfl ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_un1_reg_uflow_3_i_1_5840), + .Q(com_cmm_u_cmm_errman_send_nfl_5841), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_errman_send_ftl ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_N_62936_i_5842), + .Q(com_cmm_u_cmm_errman_send_ftl_5843), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_errman_send_cplu ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_un1_reg_uflow_3_i_0_5844), + .Q(com_cmm_u_cmm_errman_send_cplu_5845), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_errman_send_cplt ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_un1_reg_uflow_3_i_5846), + .Q(com_cmm_u_cmm_errman_send_cplt_5847), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_errman_send_cor ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_N_62928_i_5848), + .Q(com_cmm_u_cmm_errman_send_cor_5849), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_errman_reg_detectedfatal ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_N_74_2_i), + .Q(com_cmm_detectedfatal), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_errman_reg_signaledsystemerror ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_N_39937_i), + .Q(com_cmm_signaledsystemerror), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_errman_reg_detectednonfatal ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_N_85959_i_5850), + .Q(com_cmm_detectednonfatal), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_errman_reg_detectedcorrectable ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_N_85494_i_5851), + .Q(com_cmm_detectedcorrectable), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_errman_reg_incr_cplu ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_N_59526), + .Q(com_cmm_u_cmm_errman_reg_incr_cplu_5852), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_errman_request_data_2_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_N_86299_i_5853), + .Q(com_cmm_data_errmanager[2]), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_errman_request_data_1_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_N_86298_i_5854), + .Q(com_cmm_data_errmanager[1]), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_errman_request_data_0_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_N_86297_i_5855), + .Q(com_cmm_data_errmanager[0]), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_errman_request_data_17_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_N_86314_i_5856), + .Q(com_cmm_data_errmanager[17]), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_errman_request_data_16_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_N_86313_i_5857), + .Q(com_cmm_data_errmanager[16]), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_errman_request_data_15_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_N_86312_i_5858), + .Q(com_cmm_data_errmanager[15]), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_errman_request_data_14_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_N_86311_i_5859), + .Q(com_cmm_data_errmanager[14]), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_errman_request_data_13_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_N_86310_i_5860), + .Q(com_cmm_data_errmanager[13]), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_errman_request_data_12_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_N_86309_i_5861), + .Q(com_cmm_data_errmanager[12]), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_errman_request_data_11_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_N_86308_i_5862), + .Q(com_cmm_data_errmanager[11]), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_errman_request_data_10_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_N_86307_i_5863), + .Q(com_cmm_data_errmanager[10]), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_errman_request_data_9_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_N_86306_i_5864), + .Q(com_cmm_data_errmanager[9]), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_errman_request_data_8_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_N_86305_i_5865), + .Q(com_cmm_data_errmanager[8]), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_errman_request_data_7_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_N_86304_i_5866), + .Q(com_cmm_data_errmanager[7]), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_errman_request_data_6_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_N_86303_i_5867), + .Q(com_cmm_data_errmanager[6]), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_errman_request_data_5_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_N_86302_i_5868), + .Q(com_cmm_data_errmanager[5]), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_errman_request_data_4_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_N_86301_i_5869), + .Q(com_cmm_data_errmanager[4]), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_errman_request_data_3_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_N_86300_i_5870), + .Q(com_cmm_data_errmanager[3]), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_errman_request_data_32_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_N_86329_i_5871), + .Q(com_cmm_data_errmanager[32]), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_errman_request_data_31_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_N_86328_i_5872), + .Q(com_cmm_data_errmanager[31]), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_errman_request_data_30_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_N_86327_i_5873), + .Q(com_cmm_data_errmanager[30]), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_errman_request_data_29_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_N_86326_i_5874), + .Q(com_cmm_data_errmanager[29]), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_errman_request_data_28_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_N_86325_i_5875), + .Q(com_cmm_data_errmanager[28]), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_errman_request_data_27_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_N_86324_i_5876), + .Q(com_cmm_data_errmanager[27]), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_errman_request_data_26_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_N_86323_i_5877), + .Q(com_cmm_data_errmanager[26]), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_errman_request_data_25_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_N_86322_i_5878), + .Q(com_cmm_data_errmanager[25]), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_errman_request_data_24_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_N_86321_i_5879), + .Q(com_cmm_data_errmanager[24]), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_errman_request_data_23_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_N_86320_i_5880), + .Q(com_cmm_data_errmanager[23]), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_errman_request_data_22_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_N_86319_i_5881), + .Q(com_cmm_data_errmanager[22]), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_errman_request_data_21_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_N_86318_i_5882), + .Q(com_cmm_data_errmanager[21]), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_errman_request_data_20_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_N_86317_i_5883), + .Q(com_cmm_data_errmanager[20]), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_errman_request_data_19_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_N_86316_i_5884), + .Q(com_cmm_data_errmanager[19]), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_errman_request_data_18_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_N_86315_i_5885), + .Q(com_cmm_data_errmanager[18]), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_errman_request_data_47_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_N_86344_i_5886), + .Q(com_cmm_data_errmanager[47]), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_errman_request_data_46_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_N_86343_i_5887), + .Q(com_cmm_data_errmanager[46]), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_errman_request_data_45_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_N_86342_i_5888), + .Q(com_cmm_data_errmanager[45]), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_errman_request_data_44_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_N_86341_i_5889), + .Q(com_cmm_data_errmanager[44]), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_errman_request_data_43_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_N_86340_i_5890), + .Q(com_cmm_data_errmanager[43]), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_errman_request_data_42_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_N_86339_i_5891), + .Q(com_cmm_data_errmanager[42]), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_errman_request_data_41_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_N_86338_i_5892), + .Q(com_cmm_data_errmanager[41]), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_errman_request_data_40_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_N_86337_i_5893), + .Q(com_cmm_data_errmanager[40]), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_errman_request_data_39_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_N_86336_i_5894), + .Q(com_cmm_data_errmanager[39]), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_errman_request_data_38_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_N_86335_i_5895), + .Q(com_cmm_data_errmanager[38]), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_errman_request_data_37_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_N_86334_i_5896), + .Q(com_cmm_data_errmanager[37]), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_errman_request_data_36_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_N_86333_i_5897), + .Q(com_cmm_data_errmanager[36]), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_errman_request_data_35_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_N_86332_i_5898), + .Q(com_cmm_data_errmanager[35]), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_errman_request_data_34_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_N_86331_i_5899), + .Q(com_cmm_data_errmanager[34]), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_errman_request_data_33_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_N_86330_i_5900), + .Q(com_cmm_data_errmanager[33]), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_errman_reg_cfg_wr_hdr_1_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_N_39843_i), + .Q(com_cmm_u_cmm_errman_reg_cfg_wr_hdr[1]), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_errman_reg_cfg_wr_hdr_0_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_N_39841_i), + .Q(com_cmm_u_cmm_errman_reg_cfg_wr_hdr[0]), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_errman_reg_cfg_rp_1_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_reg_cfg_rp_4[1]), + .Q(com_cmm_u_cmm_errman_reg_cfg_rp[1]), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_errman_reg_cfg_rp_0_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_reg_cfg_rp_4[0]), + .Q(com_cmm_u_cmm_errman_reg_cfg_rp[0]), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_errman_reg_cmt_rp_1_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_reg_cmt_rp_4[1]), + .Q(com_cmm_u_cmm_errman_reg_cmt_rp[1]), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_errman_reg_cmt_rp_0_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_reg_cmt_rp_4[0]), + .Q(com_cmm_u_cmm_errman_reg_cmt_rp[0]), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_errman_cs_fsm_3_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_un1_cs_fsm_1_0_a2_0_a2_5901), + .Q(com_cmm_u_cmm_errman_cs_fsm[3]), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_errman_cs_fsm_2_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_N_85896_i_5902), + .Q(com_cmm_u_cmm_errman_cs_fsm[2]), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_errman_cs_fsm_1_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_N_85897_i_5903), + .Q(com_cmm_u_cmm_errman_cs_fsm[1]), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_errman_cs_fsm_0_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_N_85997_i_5904), + .Q(com_cmm_u_cmm_errman_cs_fsm[0]), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_errman_request_2_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_N_86360_i_5905), + .Q(com_cmm_req_errman[2]), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_errman_request_1_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_N_86399_i_5906), + .Q(com_cmm_req_errman[1]), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_errman_request_0_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_N_86398_i_5907), + .Q(com_cmm_req_errman[0]), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_errman_request_data_49_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_N_86346_i_5908), + .Q(com_cmm_data_errmanager[49]), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_errman_request_data_48_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_N_86345_i_5909), + .Q(com_cmm_data_errmanager[48]), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_errman_reg_cfg_wr_hdr_16_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_N_39873_i), + .Q(com_cmm_u_cmm_errman_reg_cfg_wr_hdr[16]), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_errman_reg_cfg_wr_hdr_15_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_N_39871_i), + .Q(com_cmm_u_cmm_errman_reg_cfg_wr_hdr[15]), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_errman_reg_cfg_wr_hdr_14_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_N_39869_i), + .Q(com_cmm_u_cmm_errman_reg_cfg_wr_hdr[14]), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_errman_reg_cfg_wr_hdr_13_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_N_39867_i), + .Q(com_cmm_u_cmm_errman_reg_cfg_wr_hdr[13]), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_errman_reg_cfg_wr_hdr_12_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_N_39865_i), + .Q(com_cmm_u_cmm_errman_reg_cfg_wr_hdr[12]), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_errman_reg_cfg_wr_hdr_11_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_N_39863_i), + .Q(com_cmm_u_cmm_errman_reg_cfg_wr_hdr[11]), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_errman_reg_cfg_wr_hdr_10_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_N_39861_i), + .Q(com_cmm_u_cmm_errman_reg_cfg_wr_hdr[10]), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_errman_reg_cfg_wr_hdr_9_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_N_39859_i), + .Q(com_cmm_u_cmm_errman_reg_cfg_wr_hdr[9]), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_errman_reg_cfg_wr_hdr_8_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_N_39857_i), + .Q(com_cmm_u_cmm_errman_reg_cfg_wr_hdr[8]), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_errman_reg_cfg_wr_hdr_7_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_N_39855_i), + .Q(com_cmm_u_cmm_errman_reg_cfg_wr_hdr[7]), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_errman_reg_cfg_wr_hdr_6_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_N_39853_i), + .Q(com_cmm_u_cmm_errman_reg_cfg_wr_hdr[6]), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_errman_reg_cfg_wr_hdr_5_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_N_39851_i), + .Q(com_cmm_u_cmm_errman_reg_cfg_wr_hdr[5]), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_errman_reg_cfg_wr_hdr_4_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_N_39849_i), + .Q(com_cmm_u_cmm_errman_reg_cfg_wr_hdr[4]), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_errman_reg_cfg_wr_hdr_3_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_N_39847_i), + .Q(com_cmm_u_cmm_errman_reg_cfg_wr_hdr[3]), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_errman_reg_cfg_wr_hdr_2_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_N_39845_i), + .Q(com_cmm_u_cmm_errman_reg_cfg_wr_hdr[2]), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_errman_reg_cfg_wr_hdr_31_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_N_39903_i), + .Q(com_cmm_u_cmm_errman_reg_cfg_wr_hdr[31]), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_errman_reg_cfg_wr_hdr_30_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_N_39901_i), + .Q(com_cmm_u_cmm_errman_reg_cfg_wr_hdr[30]), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_errman_reg_cfg_wr_hdr_29_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_N_39899_i), + .Q(com_cmm_u_cmm_errman_reg_cfg_wr_hdr[29]), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_errman_reg_cfg_wr_hdr_28_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_N_39897_i), + .Q(com_cmm_u_cmm_errman_reg_cfg_wr_hdr[28]), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_errman_reg_cfg_wr_hdr_27_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_N_39895_i), + .Q(com_cmm_u_cmm_errman_reg_cfg_wr_hdr[27]), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_errman_reg_cfg_wr_hdr_26_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_N_39893_i), + .Q(com_cmm_u_cmm_errman_reg_cfg_wr_hdr[26]), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_errman_reg_cfg_wr_hdr_25_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_N_39891_i), + .Q(com_cmm_u_cmm_errman_reg_cfg_wr_hdr[25]), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_errman_reg_cfg_wr_hdr_24_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_N_39889_i), + .Q(com_cmm_u_cmm_errman_reg_cfg_wr_hdr[24]), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_errman_reg_cfg_wr_hdr_23_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_N_39887_i), + .Q(com_cmm_u_cmm_errman_reg_cfg_wr_hdr[23]), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_errman_reg_cfg_wr_hdr_22_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_N_39885_i), + .Q(com_cmm_u_cmm_errman_reg_cfg_wr_hdr[22]), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_errman_reg_cfg_wr_hdr_21_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_N_39883_i), + .Q(com_cmm_u_cmm_errman_reg_cfg_wr_hdr[21]), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_errman_reg_cfg_wr_hdr_20_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_N_39881_i), + .Q(com_cmm_u_cmm_errman_reg_cfg_wr_hdr[20]), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_errman_reg_cfg_wr_hdr_19_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_N_39879_i), + .Q(com_cmm_u_cmm_errman_reg_cfg_wr_hdr[19]), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_errman_reg_cfg_wr_hdr_18_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_N_39877_i), + .Q(com_cmm_u_cmm_errman_reg_cfg_wr_hdr[18]), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_errman_reg_cfg_wr_hdr_17_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_N_39875_i), + .Q(com_cmm_u_cmm_errman_reg_cfg_wr_hdr[17]), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_errman_reg_cfg_wr_hdr_46_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_N_39933_i), + .Q(com_cmm_u_cmm_errman_reg_cfg_wr_hdr[46]), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_errman_reg_cfg_wr_hdr_45_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_N_39931_i), + .Q(com_cmm_u_cmm_errman_reg_cfg_wr_hdr[45]), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_errman_reg_cfg_wr_hdr_44_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_N_39929_i), + .Q(com_cmm_u_cmm_errman_reg_cfg_wr_hdr[44]), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_errman_reg_cfg_wr_hdr_43_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_N_39927_i), + .Q(com_cmm_u_cmm_errman_reg_cfg_wr_hdr[43]), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_errman_reg_cfg_wr_hdr_42_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_N_39925_i), + .Q(com_cmm_u_cmm_errman_reg_cfg_wr_hdr[42]), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_errman_reg_cfg_wr_hdr_41_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_N_39923_i), + .Q(com_cmm_u_cmm_errman_reg_cfg_wr_hdr[41]), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_errman_reg_cfg_wr_hdr_40_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_N_39921_i), + .Q(com_cmm_u_cmm_errman_reg_cfg_wr_hdr[40]), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_errman_reg_cfg_wr_hdr_39_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_N_39919_i), + .Q(com_cmm_u_cmm_errman_reg_cfg_wr_hdr[39]), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_errman_reg_cfg_wr_hdr_38_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_N_39917_i), + .Q(com_cmm_u_cmm_errman_reg_cfg_wr_hdr[38]), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_errman_reg_cfg_wr_hdr_37_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_N_39915_i), + .Q(com_cmm_u_cmm_errman_reg_cfg_wr_hdr[37]), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_errman_reg_cfg_wr_hdr_36_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_N_39913_i), + .Q(com_cmm_u_cmm_errman_reg_cfg_wr_hdr[36]), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_errman_reg_cfg_wr_hdr_35_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_N_39911_i), + .Q(com_cmm_u_cmm_errman_reg_cfg_wr_hdr[35]), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_errman_reg_cfg_wr_hdr_34_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_N_39909_i), + .Q(com_cmm_u_cmm_errman_reg_cfg_wr_hdr[34]), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_errman_reg_cfg_wr_hdr_33_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_N_39907_i), + .Q(com_cmm_u_cmm_errman_reg_cfg_wr_hdr[33]), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_errman_reg_cfg_wr_hdr_32_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_N_39905_i), + .Q(com_cmm_u_cmm_errman_reg_cfg_wr_hdr[32]), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_errman_reg_cmt_wr_hdr_9_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_reg_cmt_wr_hdr_5[9]), + .Q(com_cmm_u_cmm_errman_reg_cmt_wr_hdr[9]), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_errman_reg_cmt_wr_hdr_8_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_reg_cmt_wr_hdr_5[8]), + .Q(com_cmm_u_cmm_errman_reg_cmt_wr_hdr[8]), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_errman_reg_cmt_wr_hdr_7_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_reg_cmt_wr_hdr_5[7]), + .Q(com_cmm_u_cmm_errman_reg_cmt_wr_hdr[7]), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_errman_reg_cmt_wr_hdr_6_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_reg_cmt_wr_hdr_5[6]), + .Q(com_cmm_u_cmm_errman_reg_cmt_wr_hdr[6]), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_errman_reg_cmt_wr_hdr_5_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_reg_cmt_wr_hdr_5[5]), + .Q(com_cmm_u_cmm_errman_reg_cmt_wr_hdr[5]), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_errman_reg_cmt_wr_hdr_4_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_reg_cmt_wr_hdr_5[4]), + .Q(com_cmm_u_cmm_errman_reg_cmt_wr_hdr[4]), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_errman_reg_cmt_wr_hdr_3_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_reg_cmt_wr_hdr_5[3]), + .Q(com_cmm_u_cmm_errman_reg_cmt_wr_hdr[3]), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_errman_reg_cmt_wr_hdr_2_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_reg_cmt_wr_hdr_5[2]), + .Q(com_cmm_u_cmm_errman_reg_cmt_wr_hdr[2]), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_errman_reg_cmt_wr_hdr_1_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_reg_cmt_wr_hdr_5[1]), + .Q(com_cmm_u_cmm_errman_reg_cmt_wr_hdr[1]), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_errman_reg_cmt_wr_hdr_0_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_reg_cmt_wr_hdr_5[0]), + .Q(com_cmm_u_cmm_errman_reg_cmt_wr_hdr[0]), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_errman_reg_cfg_wp_1_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_reg_cfg_wp_4[1]), + .Q(com_cmm_u_cmm_errman_reg_cfg_wp[1]), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_errman_reg_cfg_wp_0_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_reg_cfg_wp_4[0]), + .Q(com_cmm_u_cmm_errman_reg_cfg_wp[0]), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_errman_reg_cfg_wr_hdr_49_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_reg_cfg_wr_hdr20), + .Q(com_cmm_u_cmm_errman_reg_cfg_wr_hdr[49]), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_errman_reg_cfg_wr_hdr_48_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_cfg_is_np_and_ur), + .Q(com_cmm_u_cmm_errman_reg_cfg_wr_hdr[48]), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_errman_reg_cfg_wr_hdr_47_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_N_39935_i), + .Q(com_cmm_u_cmm_errman_reg_cfg_wr_hdr[47]), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_errman_reg_cmt_wr_hdr_24_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_reg_cmt_wr_hdr_5[24]), + .Q(com_cmm_u_cmm_errman_reg_cmt_wr_hdr[24]), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_errman_reg_cmt_wr_hdr_23_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_reg_cmt_wr_hdr_5[23]), + .Q(com_cmm_u_cmm_errman_reg_cmt_wr_hdr[23]), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_errman_reg_cmt_wr_hdr_22_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_reg_cmt_wr_hdr_5[22]), + .Q(com_cmm_u_cmm_errman_reg_cmt_wr_hdr[22]), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_errman_reg_cmt_wr_hdr_21_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_reg_cmt_wr_hdr_5[21]), + .Q(com_cmm_u_cmm_errman_reg_cmt_wr_hdr[21]), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_errman_reg_cmt_wr_hdr_20_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_reg_cmt_wr_hdr_5[20]), + .Q(com_cmm_u_cmm_errman_reg_cmt_wr_hdr[20]), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_errman_reg_cmt_wr_hdr_19_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_reg_cmt_wr_hdr_5[19]), + .Q(com_cmm_u_cmm_errman_reg_cmt_wr_hdr[19]), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_errman_reg_cmt_wr_hdr_18_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_reg_cmt_wr_hdr_5[18]), + .Q(com_cmm_u_cmm_errman_reg_cmt_wr_hdr[18]), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_errman_reg_cmt_wr_hdr_17_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_reg_cmt_wr_hdr_5[17]), + .Q(com_cmm_u_cmm_errman_reg_cmt_wr_hdr[17]), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_errman_reg_cmt_wr_hdr_16_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_reg_cmt_wr_hdr_5[16]), + .Q(com_cmm_u_cmm_errman_reg_cmt_wr_hdr[16]), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_errman_reg_cmt_wr_hdr_15_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_reg_cmt_wr_hdr_5[15]), + .Q(com_cmm_u_cmm_errman_reg_cmt_wr_hdr[15]), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_errman_reg_cmt_wr_hdr_14_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_reg_cmt_wr_hdr_5[14]), + .Q(com_cmm_u_cmm_errman_reg_cmt_wr_hdr[14]), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_errman_reg_cmt_wr_hdr_13_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_reg_cmt_wr_hdr_5[13]), + .Q(com_cmm_u_cmm_errman_reg_cmt_wr_hdr[13]), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_errman_reg_cmt_wr_hdr_12_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_reg_cmt_wr_hdr_5[12]), + .Q(com_cmm_u_cmm_errman_reg_cmt_wr_hdr[12]), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_errman_reg_cmt_wr_hdr_11_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_reg_cmt_wr_hdr_5[11]), + .Q(com_cmm_u_cmm_errman_reg_cmt_wr_hdr[11]), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_errman_reg_cmt_wr_hdr_10_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_reg_cmt_wr_hdr_5[10]), + .Q(com_cmm_u_cmm_errman_reg_cmt_wr_hdr[10]), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_errman_reg_cmt_wr_hdr_39_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_reg_cmt_wr_hdr_5[39]), + .Q(com_cmm_u_cmm_errman_reg_cmt_wr_hdr[39]), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_errman_reg_cmt_wr_hdr_38_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_reg_cmt_wr_hdr_5[38]), + .Q(com_cmm_u_cmm_errman_reg_cmt_wr_hdr[38]), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_errman_reg_cmt_wr_hdr_37_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_reg_cmt_wr_hdr_5[37]), + .Q(com_cmm_u_cmm_errman_reg_cmt_wr_hdr[37]), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_errman_reg_cmt_wr_hdr_36_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_reg_cmt_wr_hdr_5[36]), + .Q(com_cmm_u_cmm_errman_reg_cmt_wr_hdr[36]), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_errman_reg_cmt_wr_hdr_35_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_reg_cmt_wr_hdr_5[35]), + .Q(com_cmm_u_cmm_errman_reg_cmt_wr_hdr[35]), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_errman_reg_cmt_wr_hdr_34_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_reg_cmt_wr_hdr_5[34]), + .Q(com_cmm_u_cmm_errman_reg_cmt_wr_hdr[34]), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_errman_reg_cmt_wr_hdr_33_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_reg_cmt_wr_hdr_5[33]), + .Q(com_cmm_u_cmm_errman_reg_cmt_wr_hdr[33]), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_errman_reg_cmt_wr_hdr_32_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_reg_cmt_wr_hdr_5[32]), + .Q(com_cmm_u_cmm_errman_reg_cmt_wr_hdr[32]), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_errman_reg_cmt_wr_hdr_31_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_reg_cmt_wr_hdr_5[31]), + .Q(com_cmm_u_cmm_errman_reg_cmt_wr_hdr[31]), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_errman_reg_cmt_wr_hdr_30_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_reg_cmt_wr_hdr_5[30]), + .Q(com_cmm_u_cmm_errman_reg_cmt_wr_hdr[30]), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_errman_reg_cmt_wr_hdr_29_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_reg_cmt_wr_hdr_5[29]), + .Q(com_cmm_u_cmm_errman_reg_cmt_wr_hdr[29]), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_errman_reg_cmt_wr_hdr_28_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_reg_cmt_wr_hdr_5[28]), + .Q(com_cmm_u_cmm_errman_reg_cmt_wr_hdr[28]), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_errman_reg_cmt_wr_hdr_27_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_reg_cmt_wr_hdr_5[27]), + .Q(com_cmm_u_cmm_errman_reg_cmt_wr_hdr[27]), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_errman_reg_cmt_wr_hdr_26_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_reg_cmt_wr_hdr_5[26]), + .Q(com_cmm_u_cmm_errman_reg_cmt_wr_hdr[26]), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_errman_reg_cmt_wr_hdr_25_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_reg_cmt_wr_hdr_5[25]), + .Q(com_cmm_u_cmm_errman_reg_cmt_wr_hdr[25]), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_errman_reg_cmt_wp_1_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_reg_cmt_wp_4[1]), + .Q(com_cmm_u_cmm_errman_reg_cmt_wp[1]), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_errman_reg_cmt_wp_0_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_reg_cmt_wp_4[0]), + .Q(com_cmm_u_cmm_errman_reg_cmt_wp[0]), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_errman_reg_cmt_wr_hdr_48_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_N_55916_i), + .Q(com_cmm_u_cmm_errman_reg_cmt_wr_hdr[48]), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_errman_reg_cmt_wr_hdr_47_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_reg_cmt_wr_hdr_5[47]), + .Q(com_cmm_u_cmm_errman_reg_cmt_wr_hdr[47]), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_errman_reg_cmt_wr_hdr_46_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_reg_cmt_wr_hdr_5[46]), + .Q(com_cmm_u_cmm_errman_reg_cmt_wr_hdr[46]), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_errman_reg_cmt_wr_hdr_45_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_reg_cmt_wr_hdr_5[45]), + .Q(com_cmm_u_cmm_errman_reg_cmt_wr_hdr[45]), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_errman_reg_cmt_wr_hdr_44_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_reg_cmt_wr_hdr_5[44]), + .Q(com_cmm_u_cmm_errman_reg_cmt_wr_hdr[44]), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_errman_reg_cmt_wr_hdr_43_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_reg_cmt_wr_hdr_5[43]), + .Q(com_cmm_u_cmm_errman_reg_cmt_wr_hdr[43]), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_errman_reg_cmt_wr_hdr_42_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_reg_cmt_wr_hdr_5[42]), + .Q(com_cmm_u_cmm_errman_reg_cmt_wr_hdr[42]), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_errman_reg_cmt_wr_hdr_41_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_reg_cmt_wr_hdr_5[41]), + .Q(com_cmm_u_cmm_errman_reg_cmt_wr_hdr[41]), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_errman_reg_cmt_wr_hdr_40_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_reg_cmt_wr_hdr_5[40]), + .Q(com_cmm_u_cmm_errman_reg_cmt_wr_hdr[40]), + .CLR(com_cmm_rst_351) + ); + INV com_cmm_u_cmm_errman_cor_num_i_2_ ( + .I(com_cmm_u_cmm_errman_cor_num[2]), + .O(com_cmm_u_cmm_errman_cor_num_i[2]) + ); + INV com_cmm_u_cmm_errman_nfl_num_i_2_ ( + .I(com_cmm_u_cmm_errman_nfl_num[2]), + .O(com_cmm_u_cmm_errman_nfl_num_i[2]) + ); + defparam com_cmm_u_cmm_errman_reg_signaledsystemerror_9_i_0.INIT = 16'h8088; + LUT4_L com_cmm_u_cmm_errman_reg_signaledsystemerror_9_i_0 ( + .I0(NlwRenamedSig_OI_cfg_command_8_), + .I1(com_cmm_gnt_errman), + .I2(com_cmm_u_cmm_errman_cs_is_nfl_5911), + .I3(com_cmm_u_cmm_errman_reg_signaledsystemerror_9_i_0_1_5910), + .LO(com_cmm_u_cmm_errman_N_39937_i) + ); + FDR com_cmm_u_cmm_errman_wtd_cor_reg_decr_cor ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_wtd_cor_N_56483_i_0), + .Q(com_cmm_u_cmm_errman_reg_decr_cor), + .R(com_cmm_rst_351) + ); + FDR com_cmm_u_cmm_errman_wtd_cor_reg_inc_dec_b ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_wtd_cor_N_57200_i_5912), + .Q(com_cmm_u_cmm_errman_cor_add_sub_b), + .R(com_cmm_rst_351) + ); + FDS com_cmm_u_cmm_errman_wtd_cor_add_input_two_n_d ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_replay_vld_i_5830), + .Q(com_cmm_u_cmm_errman_wtd_cor_add_input_two_n_d_106), + .S(com_cmm_rst_351) + ); + FDS com_cmm_u_cmm_errman_wtd_cor_add_input_three_n_d ( + .C(NlwRenamedSig_OI_trn_clk), + .D(N_57535_i), + .Q(com_cmm_u_cmm_errman_wtd_cor_add_input_three_n_d_105), + .S(com_cmm_rst_351) + ); + FDS com_cmm_u_cmm_errman_wtd_cor_add_input_six_n_d ( + .C(NlwRenamedSig_OI_trn_clk), + .D(cfg_err_cor_n), + .Q(com_cmm_u_cmm_errman_wtd_cor_add_input_six_n_d_110), + .S(com_cmm_rst_351) + ); + FDS com_cmm_u_cmm_errman_wtd_cor_add_input_four_n_d ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmml_bad_dllp_err_n), + .Q(com_cmm_u_cmm_errman_wtd_cor_add_input_four_n_d_629), + .S(com_cmm_rst_351) + ); + FDS com_cmm_u_cmm_errman_wtd_cor_add_input_five_n_d ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_N_58392_i_5828), + .Q(com_cmm_u_cmm_errman_wtd_cor_add_input_five_n_d_104), + .S(com_cmm_rst_351) + ); + FDR com_cmm_u_cmm_errman_wtd_cor_add_input_one_d ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_reg_detectedcorrectable_3_i_0_0_0_a2_0_5827), + .Q(com_cmm_u_cmm_errman_wtd_cor_add_input_one_d_109), + .R(com_cmm_rst_351) + ); + FDR com_cmm_u_cmm_errman_wtd_cor_to_incr_0_dreg_0_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(N_78313_i_304), + .Q(com_cmm_u_cmm_errman_cor_num_int[0]), + .R(com_cmm_rst_351) + ); + FDR com_cmm_u_cmm_errman_wtd_cor_to_incr_0_dreg_1_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_wtd_cor_to_incr_0df1), + .Q(com_cmm_u_cmm_errman_cor_num_int[1]), + .R(com_cmm_rst_351) + ); + FDR com_cmm_u_cmm_errman_wtd_cor_to_incr_0_dreg_2_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_wtd_cor_to_incr_0df2), + .Q(com_cmm_u_cmm_errman_cor_num_int[2]), + .R(com_cmm_rst_351) + ); + defparam com_cmm_u_cmm_errman_wtd_cor_un4_reg_inc_dec_b_0_o3_0_2.INIT = 16'h8000; + LUT4 com_cmm_u_cmm_errman_wtd_cor_un4_reg_inc_dec_b_0_o3_0_2 ( + .I0(com_cmm_u_cmm_errman_wtd_cor_add_input_five_n_d_104), + .I1(com_cmm_u_cmm_errman_wtd_cor_add_input_four_n_d_629), + .I2(com_cmm_u_cmm_errman_wtd_cor_add_input_six_n_d_110), + .I3(com_cmm_u_cmm_errman_wtd_cor_add_input_three_n_d_105), + .O(com_cmm_u_cmm_errman_wtd_cor_un4_reg_inc_dec_b_0_o3_0_2_5913) + ); + defparam com_cmm_u_cmm_errman_wtd_cor_N_57200_i.INIT = 16'h7FFF; + LUT4_L com_cmm_u_cmm_errman_wtd_cor_N_57200_i ( + .I0(m10_630), + .I1(com_cmm_gnt_errman), + .I2(com_cmm_u_cmm_errman_cs_is_cor_5837), + .I3(com_cmm_u_cmm_errman_wtd_cor_un4_reg_inc_dec_b_0_o3_0_2_5913), + .LO(com_cmm_u_cmm_errman_wtd_cor_N_57200_i_5912) + ); + defparam com_cmm_u_cmm_errman_wtd_cor_reg_decr_cor_4_0_x3.INIT = 16'h6AC0; + LUT4_L com_cmm_u_cmm_errman_wtd_cor_reg_decr_cor_4_0_x3 ( + .I0(m10_630), + .I1(com_cmm_gnt_errman), + .I2(com_cmm_u_cmm_errman_cs_is_cor_5837), + .I3(com_cmm_u_cmm_errman_wtd_cor_un4_reg_inc_dec_b_0_o3_0_2_5913), + .LO(com_cmm_u_cmm_errman_wtd_cor_N_56483_i_0) + ); + VCC com_cmm_u_cmm_errman_cor_cntr_VCC ( + .P(com_cmm_u_cmm_errman_cor_cntr_VCC_5920) + ); + GND com_cmm_u_cmm_errman_cor_cntr_GND ( + .G(com_cmm_u_cmm_errman_cor_cntr_GND_5916) + ); + MUXCY_L com_cmm_u_cmm_errman_cor_cntr_un14_reg_cnt_cry_0 ( + .CI(com_cmm_u_cmm_errman_cor_cntr_GND_5916), + .DI(com_cmm_u_cmm_errman_cor_cntr_N_24801_i), + .LO(com_cmm_u_cmm_errman_cor_cntr_un14_reg_cnt_cry_0_5914), + .S(com_cmm_u_cmm_errman_cor_cntr_un14_reg_cnt_axb_0_5931) + ); + MUXCY_L com_cmm_u_cmm_errman_cor_cntr_un14_reg_cnt_cry_1 ( + .CI(com_cmm_u_cmm_errman_cor_cntr_un14_reg_cnt_cry_0_5914), + .DI(com_cmm_u_cmm_errman_cor_cntr_N_24803_i), + .LO(com_cmm_u_cmm_errman_cor_cntr_un14_reg_cnt_cry_1_5915), + .S(com_cmm_u_cmm_errman_cor_cntr_un14_reg_cnt_axb_1_5942) + ); + XORCY com_cmm_u_cmm_errman_cor_cntr_un14_reg_cnt_s_1 ( + .CI(com_cmm_u_cmm_errman_cor_cntr_un14_reg_cnt_cry_0_5914), + .LI(com_cmm_u_cmm_errman_cor_cntr_un14_reg_cnt_axb_1_5942), + .O(com_cmm_u_cmm_errman_cor_cntr_un14_reg_cnt_s_1_5928) + ); + MUXCY_L com_cmm_u_cmm_errman_cor_cntr_un14_reg_cnt_cry_2 ( + .CI(com_cmm_u_cmm_errman_cor_cntr_un14_reg_cnt_cry_1_5915), + .DI(com_cmm_u_cmm_errman_cor_cntr_N_24805_i), + .LO(com_cmm_u_cmm_errman_cor_cntr_un14_reg_cnt_cry_2_5917), + .S(com_cmm_u_cmm_errman_cor_cntr_un14_reg_cnt_axb_2_5941) + ); + XORCY com_cmm_u_cmm_errman_cor_cntr_un14_reg_cnt_s_2 ( + .CI(com_cmm_u_cmm_errman_cor_cntr_un14_reg_cnt_cry_1_5915), + .LI(com_cmm_u_cmm_errman_cor_cntr_un14_reg_cnt_axb_2_5941), + .O(com_cmm_u_cmm_errman_cor_cntr_un14_reg_cnt_s_2_5926) + ); + MUXCY com_cmm_u_cmm_errman_cor_cntr_un14_reg_cnt_cry_3 ( + .CI(com_cmm_u_cmm_errman_cor_cntr_un14_reg_cnt_cry_2_5917), + .DI(com_cmm_u_cmm_errman_cor_cntr_GND_5916), + .O(com_cmm_u_cmm_errman_cor_cntr_un14_reg_cnt_cry_3_5922), + .S(com_cmm_u_cmm_errman_cor_cntr_un14_reg_cnt_axb_3_5939) + ); + XORCY com_cmm_u_cmm_errman_cor_cntr_un14_reg_cnt_s_3 ( + .CI(com_cmm_u_cmm_errman_cor_cntr_un14_reg_cnt_cry_2_5917), + .LI(com_cmm_u_cmm_errman_cor_cntr_un14_reg_cnt_axb_3_5939), + .O(com_cmm_u_cmm_errman_cor_cntr_un14_reg_cnt_s_3_5924) + ); + MUXCY_L com_cmm_u_cmm_errman_cor_cntr_un25_reg_cnt_cry_0 ( + .CI(com_cmm_u_cmm_errman_cor_cntr_VCC_5920), + .DI(com_cmm_u_cmm_errman_cor_num_i[0]), + .LO(com_cmm_u_cmm_errman_cor_cntr_un25_reg_cnt_cry_0_5918), + .S(com_cmm_u_cmm_errman_cor_cntr_un25_reg_cnt_axb_0_5930) + ); + MUXCY_L com_cmm_u_cmm_errman_cor_cntr_un25_reg_cnt_cry_1 ( + .CI(com_cmm_u_cmm_errman_cor_cntr_un25_reg_cnt_cry_0_5918), + .DI(com_cmm_u_cmm_errman_cor_num_i[1]), + .LO(com_cmm_u_cmm_errman_cor_cntr_un25_reg_cnt_cry_1_5919), + .S(com_cmm_u_cmm_errman_cor_cntr_un25_reg_cnt_axb_1_5938) + ); + XORCY com_cmm_u_cmm_errman_cor_cntr_un25_reg_cnt_s_1 ( + .CI(com_cmm_u_cmm_errman_cor_cntr_un25_reg_cnt_cry_0_5918), + .LI(com_cmm_u_cmm_errman_cor_cntr_un25_reg_cnt_axb_1_5938), + .O(com_cmm_u_cmm_errman_cor_cntr_un25_reg_cnt_s_1_5929) + ); + MUXCY_L com_cmm_u_cmm_errman_cor_cntr_un25_reg_cnt_cry_2 ( + .CI(com_cmm_u_cmm_errman_cor_cntr_un25_reg_cnt_cry_1_5919), + .DI(com_cmm_u_cmm_errman_cor_num_i[2]), + .LO(com_cmm_u_cmm_errman_cor_cntr_un25_reg_cnt_cry_2_5921), + .S(com_cmm_u_cmm_errman_cor_cntr_un25_reg_cnt_axb_2_5937) + ); + XORCY com_cmm_u_cmm_errman_cor_cntr_un25_reg_cnt_s_2 ( + .CI(com_cmm_u_cmm_errman_cor_cntr_un25_reg_cnt_cry_1_5919), + .LI(com_cmm_u_cmm_errman_cor_cntr_un25_reg_cnt_axb_2_5937), + .O(com_cmm_u_cmm_errman_cor_cntr_un25_reg_cnt_s_2_5927) + ); + MUXCY_L com_cmm_u_cmm_errman_cor_cntr_un25_reg_cnt_cry_3 ( + .CI(com_cmm_u_cmm_errman_cor_cntr_un25_reg_cnt_cry_2_5921), + .DI(com_cmm_u_cmm_errman_cor_cntr_VCC_5920), + .LO(com_cmm_u_cmm_errman_cor_cntr_un25_reg_cnt_cry_3_5935), + .S(com_cmm_u_cmm_errman_cor_cntr_un25_reg_cnt_axb_3_i_i_5936) + ); + XORCY com_cmm_u_cmm_errman_cor_cntr_un25_reg_cnt_s_3 ( + .CI(com_cmm_u_cmm_errman_cor_cntr_un25_reg_cnt_cry_2_5921), + .LI(com_cmm_u_cmm_errman_cor_cntr_un25_reg_cnt_axb_3_i_i_5936), + .O(com_cmm_u_cmm_errman_cor_cntr_un25_reg_cnt_s_3_5925) + ); + defparam com_cmm_u_cmm_errman_cor_cntr_oflow_0_a2_0_a2.INIT = 4'h8; + LUT2 com_cmm_u_cmm_errman_cor_cntr_oflow_0_a2_0_a2 ( + .I0(com_cmm_u_cmm_errman_cor_cntr_reg_extra_5932), + .I1(com_cmm_u_cmm_errman_cor_cntr_reg_inc_dec_b_5933), + .O(com_cmm_u_cmm_errman_cor_cntr_oflow) + ); + defparam com_cmm_u_cmm_errman_cor_cntr_un14_reg_cnt_axb_0.INIT = 4'h9; + LUT2 com_cmm_u_cmm_errman_cor_cntr_un14_reg_cnt_axb_0 ( + .I0(com_cmm_u_cmm_errman_cor_cntr_N_24801_i), + .I1(com_cmm_u_cmm_errman_cor_num_i[0]), + .O(com_cmm_u_cmm_errman_cor_cntr_un14_reg_cnt_axb_0_5931) + ); + defparam com_cmm_u_cmm_errman_cor_cntr_cnt_f0_i_0_0_0_2_.INIT = 8'h0E; + LUT3 com_cmm_u_cmm_errman_cor_cntr_cnt_f0_i_0_0_0_2_ ( + .I0(com_cmm_u_cmm_errman_cor_cntr_oflow), + .I1(com_cmm_u_cmm_errman_cor_cntr_reg_cnt[2]), + .I2(com_cmm_u_cmm_errman_cor_cntr_reg_uflow_5940), + .O(com_cmm_u_cmm_errman_cor_cntr_N_24805_i) + ); + defparam com_cmm_u_cmm_errman_cor_cntr_cnt_f0_i_0_0_0_1_.INIT = 8'h0E; + LUT3 com_cmm_u_cmm_errman_cor_cntr_cnt_f0_i_0_0_0_1_ ( + .I0(com_cmm_u_cmm_errman_cor_cntr_oflow), + .I1(com_cmm_u_cmm_errman_cor_cntr_reg_cnt[1]), + .I2(com_cmm_u_cmm_errman_cor_cntr_reg_uflow_5940), + .O(com_cmm_u_cmm_errman_cor_cntr_N_24803_i) + ); + defparam com_cmm_u_cmm_errman_cor_cntr_cnt_f0_i_0_0_0_0_.INIT = 8'h0E; + LUT3 com_cmm_u_cmm_errman_cor_cntr_cnt_f0_i_0_0_0_0_ ( + .I0(com_cmm_u_cmm_errman_cor_cntr_oflow), + .I1(com_cmm_u_cmm_errman_cor_cntr_reg_cnt[0]), + .I2(com_cmm_u_cmm_errman_cor_cntr_reg_uflow_5940), + .O(com_cmm_u_cmm_errman_cor_cntr_N_24801_i) + ); + defparam com_cmm_u_cmm_errman_cor_cntr_un25_reg_cnt_axb_0.INIT = 4'h6; + LUT2 com_cmm_u_cmm_errman_cor_cntr_un25_reg_cnt_axb_0 ( + .I0(com_cmm_u_cmm_errman_cor_cntr_N_24801_i), + .I1(com_cmm_u_cmm_errman_cor_num_i[0]), + .O(com_cmm_u_cmm_errman_cor_cntr_un25_reg_cnt_axb_0_5930) + ); + defparam com_cmm_u_cmm_errman_cor_cntr_reg_uflow_3_i_a2_0.INIT = 8'h21; + LUT3 com_cmm_u_cmm_errman_cor_cntr_reg_uflow_3_i_a2_0 ( + .I0(com_cmm_u_cmm_errman_cor_num_int[0]), + .I1(com_cmm_u_cmm_errman_cor_num_int[1]), + .I2(com_cmm_u_cmm_errman_reg_decr_cor), + .O(com_cmm_u_cmm_errman_cor_cntr_reg_uflow_3_i_a2_0_5923) + ); + defparam com_cmm_u_cmm_errman_cor_cntr_reg_extra_6_u_0_a2_0_a2_0_a2_0_a2.INIT = 16'hC808; + LUT4_L com_cmm_u_cmm_errman_cor_cntr_reg_extra_6_u_0_a2_0_a2_0_a2_0_a2 ( + .I0(com_cmm_u_cmm_errman_cor_cntr_un25_reg_cnt_s_4_5934), + .I1(NlwRenamedSig_OI_cfg_dcommand[0]), + .I2(com_cmm_u_cmm_errman_cor_add_sub_b), + .I3(com_cmm_u_cmm_errman_cor_cntr_un14_reg_cnt_cry_3_5922), + .LO(com_cmm_u_cmm_errman_cor_cntr_reg_extra_6) + ); + defparam com_cmm_u_cmm_errman_cor_cntr_reg_uflow_3_i.INIT = 16'h2202; + LUT4_L com_cmm_u_cmm_errman_cor_cntr_reg_uflow_3_i ( + .I0(com_cmm_u_cmm_errman_send_cor_3_0_a2_5824), + .I1(com_cmm_u_cmm_errman_cor_add_sub_b), + .I2(com_cmm_u_cmm_errman_cor_cntr_reg_uflow_3_i_a2_0_5923), + .I3(com_cmm_u_cmm_errman_cor_num[2]), + .LO(com_cmm_u_cmm_errman_cor_cntr_N_18826_i) + ); + defparam com_cmm_u_cmm_errman_cor_cntr_reg_count_7_f0_i_0_0_0_1_.INIT = 16'h00A8; + LUT4_L com_cmm_u_cmm_errman_cor_cntr_reg_count_7_f0_i_0_0_0_1_ ( + .I0(NlwRenamedSig_OI_cfg_dcommand[0]), + .I1(com_cmm_u_cmm_errman_cor_cntr_oflow), + .I2(com_cmm_u_cmm_errman_cor_cntr_reg_cnt[1]), + .I3(com_cmm_u_cmm_errman_cor_cntr_reg_uflow_5940), + .LO(com_cmm_u_cmm_errman_cor_cntr_N_24811_i) + ); + defparam com_cmm_u_cmm_errman_cor_cntr_reg_count_7_f0_i_0_0_0_0_.INIT = 16'h00A8; + LUT4_L com_cmm_u_cmm_errman_cor_cntr_reg_count_7_f0_i_0_0_0_0_ ( + .I0(NlwRenamedSig_OI_cfg_dcommand[0]), + .I1(com_cmm_u_cmm_errman_cor_cntr_oflow), + .I2(com_cmm_u_cmm_errman_cor_cntr_reg_cnt[0]), + .I3(com_cmm_u_cmm_errman_cor_cntr_reg_uflow_5940), + .LO(com_cmm_u_cmm_errman_cor_cntr_N_24809_i) + ); + defparam com_cmm_u_cmm_errman_cor_cntr_reg_cnt_6_0_a2_0_a2_0_a2_0_a2_3_.INIT = 16'hC808; + LUT4_L com_cmm_u_cmm_errman_cor_cntr_reg_cnt_6_0_a2_0_a2_0_a2_0_a2_3_ ( + .I0(com_cmm_u_cmm_errman_cor_cntr_un25_reg_cnt_s_3_5925), + .I1(NlwRenamedSig_OI_cfg_dcommand[0]), + .I2(com_cmm_u_cmm_errman_cor_add_sub_b), + .I3(com_cmm_u_cmm_errman_cor_cntr_un14_reg_cnt_s_3_5924), + .LO(com_cmm_u_cmm_errman_cor_cntr_reg_cnt_6[3]) + ); + defparam com_cmm_u_cmm_errman_cor_cntr_reg_cnt_6_0_a2_0_a2_0_a2_0_a2_2_.INIT = 16'hC808; + LUT4_L com_cmm_u_cmm_errman_cor_cntr_reg_cnt_6_0_a2_0_a2_0_a2_0_a2_2_ ( + .I0(com_cmm_u_cmm_errman_cor_cntr_un25_reg_cnt_s_2_5927), + .I1(NlwRenamedSig_OI_cfg_dcommand[0]), + .I2(com_cmm_u_cmm_errman_cor_add_sub_b), + .I3(com_cmm_u_cmm_errman_cor_cntr_un14_reg_cnt_s_2_5926), + .LO(com_cmm_u_cmm_errman_cor_cntr_reg_cnt_6[2]) + ); + defparam com_cmm_u_cmm_errman_cor_cntr_reg_cnt_6_0_a2_0_a2_0_a2_0_a2_1_.INIT = 16'hC808; + LUT4_L com_cmm_u_cmm_errman_cor_cntr_reg_cnt_6_0_a2_0_a2_0_a2_0_a2_1_ ( + .I0(com_cmm_u_cmm_errman_cor_cntr_un25_reg_cnt_s_1_5929), + .I1(NlwRenamedSig_OI_cfg_dcommand[0]), + .I2(com_cmm_u_cmm_errman_cor_add_sub_b), + .I3(com_cmm_u_cmm_errman_cor_cntr_un14_reg_cnt_s_1_5928), + .LO(com_cmm_u_cmm_errman_cor_cntr_reg_cnt_6[1]) + ); + defparam com_cmm_u_cmm_errman_cor_cntr_reg_cnt_6_0_a2_0_a2_0_a2_0_a2_0_.INIT = 16'h80A2; + LUT4_L com_cmm_u_cmm_errman_cor_cntr_reg_cnt_6_0_a2_0_a2_0_a2_0_a2_0_ ( + .I0(NlwRenamedSig_OI_cfg_dcommand[0]), + .I1(com_cmm_u_cmm_errman_cor_add_sub_b), + .I2(com_cmm_u_cmm_errman_cor_cntr_un14_reg_cnt_axb_0_5931), + .I3(com_cmm_u_cmm_errman_cor_cntr_un25_reg_cnt_axb_0_5930), + .LO(com_cmm_u_cmm_errman_cor_cntr_reg_cnt_6[0]) + ); + defparam com_cmm_u_cmm_errman_cor_cntr_reg_count_7_f0_i_0_0_0_3_.INIT = 16'h00A8; + LUT4_L com_cmm_u_cmm_errman_cor_cntr_reg_count_7_f0_i_0_0_0_3_ ( + .I0(NlwRenamedSig_OI_cfg_dcommand[0]), + .I1(com_cmm_u_cmm_errman_cor_cntr_oflow), + .I2(com_cmm_u_cmm_errman_cor_cntr_reg_cnt[3]), + .I3(com_cmm_u_cmm_errman_cor_cntr_reg_uflow_5940), + .LO(com_cmm_u_cmm_errman_cor_cntr_N_24815_i) + ); + defparam com_cmm_u_cmm_errman_cor_cntr_reg_count_7_f0_i_0_0_0_2_.INIT = 16'h00A8; + LUT4_L com_cmm_u_cmm_errman_cor_cntr_reg_count_7_f0_i_0_0_0_2_ ( + .I0(NlwRenamedSig_OI_cfg_dcommand[0]), + .I1(com_cmm_u_cmm_errman_cor_cntr_oflow), + .I2(com_cmm_u_cmm_errman_cor_cntr_reg_cnt[2]), + .I3(com_cmm_u_cmm_errman_cor_cntr_reg_uflow_5940), + .LO(com_cmm_u_cmm_errman_cor_cntr_N_24813_i) + ); + FDC com_cmm_u_cmm_errman_cor_cntr_reg_extra ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_cor_cntr_reg_extra_6), + .Q(com_cmm_u_cmm_errman_cor_cntr_reg_extra_5932), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_errman_cor_cntr_reg_uflow ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_cor_cntr_N_18826_i), + .Q(com_cmm_u_cmm_errman_cor_cntr_reg_uflow_5940), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_errman_cor_cntr_reg_inc_dec_b ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_cor_add_sub_b), + .Q(com_cmm_u_cmm_errman_cor_cntr_reg_inc_dec_b_5933), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_errman_cor_cntr_reg_count_1_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_cor_cntr_N_24811_i), + .Q(com_cmm_u_cmm_errman_cnt_cor[1]), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_errman_cor_cntr_reg_count_0_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_cor_cntr_N_24809_i), + .Q(com_cmm_u_cmm_errman_cnt_cor[0]), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_errman_cor_cntr_reg_cnt_3_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_cor_cntr_reg_cnt_6[3]), + .Q(com_cmm_u_cmm_errman_cor_cntr_reg_cnt[3]), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_errman_cor_cntr_reg_cnt_2_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_cor_cntr_reg_cnt_6[2]), + .Q(com_cmm_u_cmm_errman_cor_cntr_reg_cnt[2]), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_errman_cor_cntr_reg_cnt_1_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_cor_cntr_reg_cnt_6[1]), + .Q(com_cmm_u_cmm_errman_cor_cntr_reg_cnt[1]), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_errman_cor_cntr_reg_cnt_0_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_cor_cntr_reg_cnt_6[0]), + .Q(com_cmm_u_cmm_errman_cor_cntr_reg_cnt[0]), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_errman_cor_cntr_reg_count_3_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_cor_cntr_N_24815_i), + .Q(com_cmm_u_cmm_errman_cnt_cor[3]), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_errman_cor_cntr_reg_count_2_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_cor_cntr_N_24813_i), + .Q(com_cmm_u_cmm_errman_cnt_cor[2]), + .CLR(com_cmm_rst_351) + ); + defparam com_cmm_u_cmm_errman_cor_cntr_un25_reg_cnt_s_4.INIT = 4'h1; + LUT1_L com_cmm_u_cmm_errman_cor_cntr_un25_reg_cnt_s_4 ( + .I0(com_cmm_u_cmm_errman_cor_cntr_un25_reg_cnt_cry_3_5935), + .LO(com_cmm_u_cmm_errman_cor_cntr_un25_reg_cnt_s_4_5934) + ); + defparam com_cmm_u_cmm_errman_cor_cntr_un25_reg_cnt_axb_3_i_i.INIT = 8'hF1; + LUT3 com_cmm_u_cmm_errman_cor_cntr_un25_reg_cnt_axb_3_i_i ( + .I0(com_cmm_u_cmm_errman_cor_cntr_oflow), + .I1(com_cmm_u_cmm_errman_cor_cntr_reg_cnt[3]), + .I2(com_cmm_u_cmm_errman_cor_cntr_reg_uflow_5940), + .O(com_cmm_u_cmm_errman_cor_cntr_un25_reg_cnt_axb_3_i_i_5936) + ); + defparam com_cmm_u_cmm_errman_cor_cntr_un25_reg_cnt_axb_2.INIT = 4'h9; + LUT2 com_cmm_u_cmm_errman_cor_cntr_un25_reg_cnt_axb_2 ( + .I0(com_cmm_u_cmm_errman_cor_cntr_N_24805_i), + .I1(com_cmm_u_cmm_errman_cor_num[2]), + .O(com_cmm_u_cmm_errman_cor_cntr_un25_reg_cnt_axb_2_5937) + ); + defparam com_cmm_u_cmm_errman_cor_cntr_un25_reg_cnt_axb_1.INIT = 16'h96A5; + LUT4 com_cmm_u_cmm_errman_cor_cntr_un25_reg_cnt_axb_1 ( + .I0(com_cmm_u_cmm_errman_cor_cntr_N_24803_i), + .I1(com_cmm_u_cmm_errman_cor_num_int[0]), + .I2(com_cmm_u_cmm_errman_cor_num_int[1]), + .I3(com_cmm_u_cmm_errman_reg_decr_cor), + .O(com_cmm_u_cmm_errman_cor_cntr_un25_reg_cnt_axb_1_5938) + ); + defparam com_cmm_u_cmm_errman_cor_cntr_un14_reg_cnt_axb_3.INIT = 8'h0E; + LUT3 com_cmm_u_cmm_errman_cor_cntr_un14_reg_cnt_axb_3 ( + .I0(com_cmm_u_cmm_errman_cor_cntr_oflow), + .I1(com_cmm_u_cmm_errman_cor_cntr_reg_cnt[3]), + .I2(com_cmm_u_cmm_errman_cor_cntr_reg_uflow_5940), + .O(com_cmm_u_cmm_errman_cor_cntr_un14_reg_cnt_axb_3_5939) + ); + defparam com_cmm_u_cmm_errman_cor_cntr_un14_reg_cnt_axb_2.INIT = 4'h6; + LUT2 com_cmm_u_cmm_errman_cor_cntr_un14_reg_cnt_axb_2 ( + .I0(com_cmm_u_cmm_errman_cor_cntr_N_24805_i), + .I1(com_cmm_u_cmm_errman_cor_num[2]), + .O(com_cmm_u_cmm_errman_cor_cntr_un14_reg_cnt_axb_2_5941) + ); + defparam com_cmm_u_cmm_errman_cor_cntr_un14_reg_cnt_axb_1.INIT = 16'h695A; + LUT4 com_cmm_u_cmm_errman_cor_cntr_un14_reg_cnt_axb_1 ( + .I0(com_cmm_u_cmm_errman_cor_cntr_N_24803_i), + .I1(com_cmm_u_cmm_errman_cor_num_int[0]), + .I2(com_cmm_u_cmm_errman_cor_num_int[1]), + .I3(com_cmm_u_cmm_errman_reg_decr_cor), + .O(com_cmm_u_cmm_errman_cor_cntr_un14_reg_cnt_axb_1_5942) + ); + FDR com_cmm_u_cmm_errman_wtd_nfl_reg_decr_cor ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_wtd_nfl_N_56487_i_0), + .Q(com_cmm_u_cmm_errman_reg_decr_nfl), + .R(com_cmm_rst_351) + ); + FDR com_cmm_u_cmm_errman_wtd_nfl_reg_inc_dec_b ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_wtd_nfl_un4_reg_inc_dec_b_i_5943), + .Q(com_cmm_u_cmm_errman_nfl_add_sub_b), + .R(com_cmm_rst_351) + ); + FDS com_cmm_u_cmm_errman_wtd_nfl_add_input_two_n_d ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_N_86391_i_5833), + .Q(com_cmm_u_cmm_errman_wtd_nfl_add_input_two_n_d_299), + .S(com_cmm_rst_351) + ); + FDS com_cmm_u_cmm_errman_wtd_nfl_add_input_four_n_d ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_N_86392_i_5832), + .Q(com_cmm_u_cmm_errman_wtd_nfl_add_input_four_n_d_297), + .S(com_cmm_rst_351) + ); + FDS com_cmm_u_cmm_errman_wtd_nfl_add_input_five_n_d ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_N_86726_i_5831), + .Q(com_cmm_u_cmm_errman_wtd_nfl_add_input_five_n_d_296), + .S(com_cmm_rst_351) + ); + FDR com_cmm_u_cmm_errman_wtd_nfl_add_input_one_d ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_N_19038_i), + .Q(com_cmm_u_cmm_errman_wtd_nfl_add_input_one_d_298), + .R(com_cmm_rst_351) + ); + FDR com_cmm_u_cmm_errman_wtd_nfl_to_incr_0_dreg_0_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(N_6_i_300), + .Q(com_cmm_u_cmm_errman_to_incr_0ro), + .R(com_cmm_rst_351) + ); + FDR com_cmm_u_cmm_errman_wtd_nfl_to_incr_0_dreg_1_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_wtd_nfl_to_incr_0df1), + .Q(com_cmm_u_cmm_errman_to_incr_1ro), + .R(com_cmm_rst_351) + ); + FDR com_cmm_u_cmm_errman_wtd_nfl_to_incr_0_dreg_2_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_wtd_nfl_to_incr_0df2), + .Q(com_cmm_u_cmm_errman_to_incr_2ro), + .R(com_cmm_rst_351) + ); + defparam com_cmm_u_cmm_errman_wtd_nfl_un4_reg_inc_dec_b_0_o3_0.INIT = 16'h0800; + LUT4 com_cmm_u_cmm_errman_wtd_nfl_un4_reg_inc_dec_b_0_o3_0 ( + .I0(com_cmm_u_cmm_errman_wtd_nfl_add_input_five_n_d_296), + .I1(com_cmm_u_cmm_errman_wtd_nfl_add_input_four_n_d_297), + .I2(com_cmm_u_cmm_errman_wtd_nfl_add_input_one_d_298), + .I3(com_cmm_u_cmm_errman_wtd_nfl_add_input_two_n_d_299), + .O(com_cmm_u_cmm_errman_wtd_nfl_N_56481_i) + ); + defparam com_cmm_u_cmm_errman_wtd_nfl_un4_reg_inc_dec_b_i.INIT = 8'h7F; + LUT3_L com_cmm_u_cmm_errman_wtd_nfl_un4_reg_inc_dec_b_i ( + .I0(com_cmm_u_cmm_errman_wtd_nfl_N_56481_i), + .I1(com_cmm_gnt_errman), + .I2(com_cmm_u_cmm_errman_cs_is_nfl_5911), + .LO(com_cmm_u_cmm_errman_wtd_nfl_un4_reg_inc_dec_b_i_5943) + ); + defparam com_cmm_u_cmm_errman_wtd_nfl_reg_decr_cor_4_0_x3.INIT = 8'h6A; + LUT3_L com_cmm_u_cmm_errman_wtd_nfl_reg_decr_cor_4_0_x3 ( + .I0(com_cmm_u_cmm_errman_wtd_nfl_N_56481_i), + .I1(com_cmm_gnt_errman), + .I2(com_cmm_u_cmm_errman_cs_is_nfl_5911), + .LO(com_cmm_u_cmm_errman_wtd_nfl_N_56487_i_0) + ); + VCC com_cmm_u_cmm_errman_nfl_cntr_VCC ( + .P(com_cmm_u_cmm_errman_nfl_cntr_VCC_5950) + ); + GND com_cmm_u_cmm_errman_nfl_cntr_GND ( + .G(com_cmm_u_cmm_errman_nfl_cntr_GND_5946) + ); + MUXCY_L com_cmm_u_cmm_errman_nfl_cntr_un14_reg_cnt_cry_0 ( + .CI(com_cmm_u_cmm_errman_nfl_cntr_GND_5946), + .DI(com_cmm_u_cmm_errman_nfl_cntr_N_26170_i), + .LO(com_cmm_u_cmm_errman_nfl_cntr_un14_reg_cnt_cry_0_5944), + .S(com_cmm_u_cmm_errman_nfl_cntr_un14_reg_cnt[0]) + ); + MUXCY_L com_cmm_u_cmm_errman_nfl_cntr_un14_reg_cnt_cry_1 ( + .CI(com_cmm_u_cmm_errman_nfl_cntr_un14_reg_cnt_cry_0_5944), + .DI(com_cmm_u_cmm_errman_nfl_cntr_N_26172_i), + .LO(com_cmm_u_cmm_errman_nfl_cntr_un14_reg_cnt_cry_1_5945), + .S(com_cmm_u_cmm_errman_nfl_cntr_un14_reg_cnt_axb_1_5963) + ); + XORCY com_cmm_u_cmm_errman_nfl_cntr_un14_reg_cnt_s_1 ( + .CI(com_cmm_u_cmm_errman_nfl_cntr_un14_reg_cnt_cry_0_5944), + .LI(com_cmm_u_cmm_errman_nfl_cntr_un14_reg_cnt_axb_1_5963), + .O(com_cmm_u_cmm_errman_nfl_cntr_un14_reg_cnt[1]) + ); + MUXCY_L com_cmm_u_cmm_errman_nfl_cntr_un14_reg_cnt_cry_2 ( + .CI(com_cmm_u_cmm_errman_nfl_cntr_un14_reg_cnt_cry_1_5945), + .DI(com_cmm_u_cmm_errman_nfl_cntr_N_26174_i), + .LO(com_cmm_u_cmm_errman_nfl_cntr_un14_reg_cnt_cry_2_5947), + .S(com_cmm_u_cmm_errman_nfl_cntr_un14_reg_cnt_axb_2_5962) + ); + XORCY com_cmm_u_cmm_errman_nfl_cntr_un14_reg_cnt_s_2 ( + .CI(com_cmm_u_cmm_errman_nfl_cntr_un14_reg_cnt_cry_1_5945), + .LI(com_cmm_u_cmm_errman_nfl_cntr_un14_reg_cnt_axb_2_5962), + .O(com_cmm_u_cmm_errman_nfl_cntr_un14_reg_cnt[2]) + ); + MUXCY com_cmm_u_cmm_errman_nfl_cntr_un14_reg_cnt_cry_3 ( + .CI(com_cmm_u_cmm_errman_nfl_cntr_un14_reg_cnt_cry_2_5947), + .DI(com_cmm_u_cmm_errman_nfl_cntr_GND_5946), + .O(com_cmm_u_cmm_errman_nfl_cntr_un14_reg_cnt[4]), + .S(com_cmm_u_cmm_errman_nfl_cntr_un14_reg_cnt_axb_3_5961) + ); + XORCY com_cmm_u_cmm_errman_nfl_cntr_un14_reg_cnt_s_3 ( + .CI(com_cmm_u_cmm_errman_nfl_cntr_un14_reg_cnt_cry_2_5947), + .LI(com_cmm_u_cmm_errman_nfl_cntr_un14_reg_cnt_axb_3_5961), + .O(com_cmm_u_cmm_errman_nfl_cntr_un14_reg_cnt[3]) + ); + MUXCY_L com_cmm_u_cmm_errman_nfl_cntr_un25_reg_cnt_cry_0 ( + .CI(com_cmm_u_cmm_errman_nfl_cntr_VCC_5950), + .DI(com_cmm_u_cmm_errman_nfl_num_i[0]), + .LO(com_cmm_u_cmm_errman_nfl_cntr_un25_reg_cnt_cry_0_5948), + .S(com_cmm_u_cmm_errman_nfl_cntr_un25_reg_cnt_axb_0_5953) + ); + MUXCY_L com_cmm_u_cmm_errman_nfl_cntr_un25_reg_cnt_cry_1 ( + .CI(com_cmm_u_cmm_errman_nfl_cntr_un25_reg_cnt_cry_0_5948), + .DI(com_cmm_u_cmm_errman_nfl_num_i[1]), + .LO(com_cmm_u_cmm_errman_nfl_cntr_un25_reg_cnt_cry_1_5949), + .S(com_cmm_u_cmm_errman_nfl_cntr_un25_reg_cnt_axb_1_5960) + ); + XORCY com_cmm_u_cmm_errman_nfl_cntr_un25_reg_cnt_s_1 ( + .CI(com_cmm_u_cmm_errman_nfl_cntr_un25_reg_cnt_cry_0_5948), + .LI(com_cmm_u_cmm_errman_nfl_cntr_un25_reg_cnt_axb_1_5960), + .O(com_cmm_u_cmm_errman_nfl_cntr_un25_reg_cnt[1]) + ); + MUXCY_L com_cmm_u_cmm_errman_nfl_cntr_un25_reg_cnt_cry_2 ( + .CI(com_cmm_u_cmm_errman_nfl_cntr_un25_reg_cnt_cry_1_5949), + .DI(com_cmm_u_cmm_errman_nfl_num_i[2]), + .LO(com_cmm_u_cmm_errman_nfl_cntr_un25_reg_cnt_cry_2_5951), + .S(com_cmm_u_cmm_errman_nfl_cntr_un25_reg_cnt_axb_2_5959) + ); + XORCY com_cmm_u_cmm_errman_nfl_cntr_un25_reg_cnt_s_2 ( + .CI(com_cmm_u_cmm_errman_nfl_cntr_un25_reg_cnt_cry_1_5949), + .LI(com_cmm_u_cmm_errman_nfl_cntr_un25_reg_cnt_axb_2_5959), + .O(com_cmm_u_cmm_errman_nfl_cntr_un25_reg_cnt[2]) + ); + MUXCY_L com_cmm_u_cmm_errman_nfl_cntr_un25_reg_cnt_cry_3 ( + .CI(com_cmm_u_cmm_errman_nfl_cntr_un25_reg_cnt_cry_2_5951), + .DI(com_cmm_u_cmm_errman_nfl_cntr_VCC_5950), + .LO(com_cmm_u_cmm_errman_nfl_cntr_un25_reg_cnt_cry_3_5957), + .S(com_cmm_u_cmm_errman_nfl_cntr_un25_reg_cnt_axb_3_i_i_5958) + ); + XORCY com_cmm_u_cmm_errman_nfl_cntr_un25_reg_cnt_s_3 ( + .CI(com_cmm_u_cmm_errman_nfl_cntr_un25_reg_cnt_cry_2_5951), + .LI(com_cmm_u_cmm_errman_nfl_cntr_un25_reg_cnt_axb_3_i_i_5958), + .O(com_cmm_u_cmm_errman_nfl_cntr_un25_reg_cnt[3]) + ); + defparam com_cmm_u_cmm_errman_nfl_cntr_cnt_f0_i_0_.INIT = 16'h00EA; + LUT4 com_cmm_u_cmm_errman_nfl_cntr_cnt_f0_i_0_ ( + .I0(com_cmm_u_cmm_errman_nfl_cntr_reg_cnt[0]), + .I1(com_cmm_u_cmm_errman_nfl_cntr_reg_extra_5954), + .I2(com_cmm_u_cmm_errman_nfl_cntr_reg_inc_dec_b_5956), + .I3(com_cmm_u_cmm_errman_nfl_cntr_reg_uflow_5955), + .O(com_cmm_u_cmm_errman_nfl_cntr_N_26170_i) + ); + defparam com_cmm_u_cmm_errman_nfl_cntr_cnt_f0_i_1_.INIT = 16'h00EA; + LUT4 com_cmm_u_cmm_errman_nfl_cntr_cnt_f0_i_1_ ( + .I0(com_cmm_u_cmm_errman_nfl_cntr_reg_cnt[1]), + .I1(com_cmm_u_cmm_errman_nfl_cntr_reg_extra_5954), + .I2(com_cmm_u_cmm_errman_nfl_cntr_reg_inc_dec_b_5956), + .I3(com_cmm_u_cmm_errman_nfl_cntr_reg_uflow_5955), + .O(com_cmm_u_cmm_errman_nfl_cntr_N_26172_i) + ); + defparam com_cmm_u_cmm_errman_nfl_cntr_cnt_f0_i_2_.INIT = 16'h00EA; + LUT4 com_cmm_u_cmm_errman_nfl_cntr_cnt_f0_i_2_ ( + .I0(com_cmm_u_cmm_errman_nfl_cntr_reg_cnt[2]), + .I1(com_cmm_u_cmm_errman_nfl_cntr_reg_extra_5954), + .I2(com_cmm_u_cmm_errman_nfl_cntr_reg_inc_dec_b_5956), + .I3(com_cmm_u_cmm_errman_nfl_cntr_reg_uflow_5955), + .O(com_cmm_u_cmm_errman_nfl_cntr_N_26174_i) + ); + defparam com_cmm_u_cmm_errman_nfl_cntr_cnt_f0_i_3_.INIT = 16'h00EA; + LUT4 com_cmm_u_cmm_errman_nfl_cntr_cnt_f0_i_3_ ( + .I0(com_cmm_u_cmm_errman_nfl_cntr_reg_cnt[3]), + .I1(com_cmm_u_cmm_errman_nfl_cntr_reg_extra_5954), + .I2(com_cmm_u_cmm_errman_nfl_cntr_reg_inc_dec_b_5956), + .I3(com_cmm_u_cmm_errman_nfl_cntr_reg_uflow_5955), + .O(com_cmm_u_cmm_errman_nfl_cntr_un25_reg_cnt_axb_3_i) + ); + defparam com_cmm_u_cmm_errman_nfl_cntr_un14_reg_cnt_axb_0.INIT = 4'h9; + LUT2 com_cmm_u_cmm_errman_nfl_cntr_un14_reg_cnt_axb_0 ( + .I0(com_cmm_u_cmm_errman_nfl_cntr_N_26170_i), + .I1(com_cmm_u_cmm_errman_nfl_num_i[0]), + .O(com_cmm_u_cmm_errman_nfl_cntr_un14_reg_cnt[0]) + ); + defparam com_cmm_u_cmm_errman_nfl_cntr_un25_reg_cnt_axb_0.INIT = 4'h6; + LUT2 com_cmm_u_cmm_errman_nfl_cntr_un25_reg_cnt_axb_0 ( + .I0(com_cmm_u_cmm_errman_nfl_cntr_N_26170_i), + .I1(com_cmm_u_cmm_errman_nfl_num_i[0]), + .O(com_cmm_u_cmm_errman_nfl_cntr_un25_reg_cnt_axb_0_5953) + ); + defparam com_cmm_u_cmm_errman_nfl_cntr_reg_uflow_3_i_a2_0.INIT = 16'h8444; + LUT4 com_cmm_u_cmm_errman_nfl_cntr_reg_uflow_3_i_a2_0 ( + .I0(com_cmm_u_cmm_errman_nfl_num_c1_5822), + .I1(com_cmm_u_cmm_errman_nfl_num_i[0]), + .I2(com_cmm_u_cmm_errman_to_incr_1ro), + .I3(com_cmm_u_cmm_pm_dev_power_state_eq_d0), + .O(com_cmm_u_cmm_errman_nfl_cntr_reg_uflow_3_i_a2_0_5952) + ); + defparam com_cmm_u_cmm_errman_nfl_cntr_reg_extra_6_0_u_i_m2_0.INIT = 8'hD8; + LUT3_L com_cmm_u_cmm_errman_nfl_cntr_reg_extra_6_0_u_i_m2_0 ( + .I0(com_cmm_u_cmm_errman_nfl_add_sub_b), + .I1(com_cmm_u_cmm_errman_nfl_cntr_un14_reg_cnt[4]), + .I2(com_cmm_u_cmm_errman_nfl_cntr_un25_reg_cnt[4]), + .LO(com_cmm_u_cmm_errman_nfl_cntr_reg_extra_6_0_u_i_m2_0_1) + ); + defparam com_cmm_u_cmm_errman_nfl_cntr_reg_uflow_3_i.INIT = 16'h5010; + LUT4_L com_cmm_u_cmm_errman_nfl_cntr_reg_uflow_3_i ( + .I0(com_cmm_u_cmm_errman_nfl_add_sub_b), + .I1(com_cmm_u_cmm_errman_nfl_cntr_reg_uflow_3_i_a2_0_5952), + .I2(com_cmm_u_cmm_errman_un1_reg_uflow_3_1), + .I3(com_cmm_u_cmm_errman_nfl_num[2]), + .LO(com_cmm_u_cmm_errman_nfl_cntr_N_18916_i) + ); + defparam com_cmm_u_cmm_errman_nfl_cntr_reg_cnt_6_0_i_m2_0_3_.INIT = 8'hD8; + LUT3_L com_cmm_u_cmm_errman_nfl_cntr_reg_cnt_6_0_i_m2_0_3_ ( + .I0(com_cmm_u_cmm_errman_nfl_add_sub_b), + .I1(com_cmm_u_cmm_errman_nfl_cntr_un14_reg_cnt[3]), + .I2(com_cmm_u_cmm_errman_nfl_cntr_un25_reg_cnt[3]), + .LO(com_cmm_u_cmm_errman_nfl_cntr_reg_cnt_6_0_i_m2_0_1[3]) + ); + defparam com_cmm_u_cmm_errman_nfl_cntr_reg_cnt_6_0_i_m2_0_2_.INIT = 8'hD8; + LUT3_L com_cmm_u_cmm_errman_nfl_cntr_reg_cnt_6_0_i_m2_0_2_ ( + .I0(com_cmm_u_cmm_errman_nfl_add_sub_b), + .I1(com_cmm_u_cmm_errman_nfl_cntr_un14_reg_cnt[2]), + .I2(com_cmm_u_cmm_errman_nfl_cntr_un25_reg_cnt[2]), + .LO(com_cmm_u_cmm_errman_nfl_cntr_reg_cnt_6_0_i_m2_0_1[2]) + ); + defparam com_cmm_u_cmm_errman_nfl_cntr_reg_cnt_6_0_i_m2_0_1_.INIT = 8'hD8; + LUT3_L com_cmm_u_cmm_errman_nfl_cntr_reg_cnt_6_0_i_m2_0_1_ ( + .I0(com_cmm_u_cmm_errman_nfl_add_sub_b), + .I1(com_cmm_u_cmm_errman_nfl_cntr_un14_reg_cnt[1]), + .I2(com_cmm_u_cmm_errman_nfl_cntr_un25_reg_cnt[1]), + .LO(com_cmm_u_cmm_errman_nfl_cntr_reg_cnt_6_0_i_m2_0_1[1]) + ); + defparam com_cmm_u_cmm_errman_nfl_cntr_reg_cnt_6_0_i_m2_0_0_.INIT = 8'h8D; + LUT3_L com_cmm_u_cmm_errman_nfl_cntr_reg_cnt_6_0_i_m2_0_0_ ( + .I0(com_cmm_u_cmm_errman_nfl_add_sub_b), + .I1(com_cmm_u_cmm_errman_nfl_cntr_un14_reg_cnt[0]), + .I2(com_cmm_u_cmm_errman_nfl_cntr_un25_reg_cnt_axb_0_5953), + .LO(com_cmm_u_cmm_errman_nfl_cntr_reg_cnt_6_0_i_m2_0_1[0]) + ); + FDC com_cmm_u_cmm_errman_nfl_cntr_reg_extra ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_nfl_cntr_reg_extra_6_0_u_i_m2_0_1), + .Q(com_cmm_u_cmm_errman_nfl_cntr_reg_extra_5954), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_errman_nfl_cntr_reg_uflow ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_nfl_cntr_N_18916_i), + .Q(com_cmm_u_cmm_errman_nfl_cntr_reg_uflow_5955), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_errman_nfl_cntr_reg_inc_dec_b ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_nfl_add_sub_b), + .Q(com_cmm_u_cmm_errman_nfl_cntr_reg_inc_dec_b_5956), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_errman_nfl_cntr_reg_cnt_3_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_nfl_cntr_reg_cnt_6_0_i_m2_0_1[3]), + .Q(com_cmm_u_cmm_errman_nfl_cntr_reg_cnt[3]), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_errman_nfl_cntr_reg_cnt_2_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_nfl_cntr_reg_cnt_6_0_i_m2_0_1[2]), + .Q(com_cmm_u_cmm_errman_nfl_cntr_reg_cnt[2]), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_errman_nfl_cntr_reg_cnt_1_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_nfl_cntr_reg_cnt_6_0_i_m2_0_1[1]), + .Q(com_cmm_u_cmm_errman_nfl_cntr_reg_cnt[1]), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_errman_nfl_cntr_reg_cnt_0_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_nfl_cntr_reg_cnt_6_0_i_m2_0_1[0]), + .Q(com_cmm_u_cmm_errman_nfl_cntr_reg_cnt[0]), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_errman_nfl_cntr_reg_count_3_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_nfl_cntr_un25_reg_cnt_axb_3_i), + .Q(com_cmm_u_cmm_errman_cnt_nfl[3]), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_errman_nfl_cntr_reg_count_2_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_nfl_cntr_N_26174_i), + .Q(com_cmm_u_cmm_errman_cnt_nfl[2]), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_errman_nfl_cntr_reg_count_1_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_nfl_cntr_N_26172_i), + .Q(com_cmm_u_cmm_errman_cnt_nfl[1]), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_errman_nfl_cntr_reg_count_0_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_nfl_cntr_N_26170_i), + .Q(com_cmm_u_cmm_errman_cnt_nfl[0]), + .CLR(com_cmm_rst_351) + ); + defparam com_cmm_u_cmm_errman_nfl_cntr_un25_reg_cnt_s_4.INIT = 4'h1; + LUT1_L com_cmm_u_cmm_errman_nfl_cntr_un25_reg_cnt_s_4 ( + .I0(com_cmm_u_cmm_errman_nfl_cntr_un25_reg_cnt_cry_3_5957), + .LO(com_cmm_u_cmm_errman_nfl_cntr_un25_reg_cnt[4]) + ); + defparam com_cmm_u_cmm_errman_nfl_cntr_un25_reg_cnt_axb_3_i_i.INIT = 4'h1; + LUT1 com_cmm_u_cmm_errman_nfl_cntr_un25_reg_cnt_axb_3_i_i ( + .I0(com_cmm_u_cmm_errman_nfl_cntr_un25_reg_cnt_axb_3_i), + .O(com_cmm_u_cmm_errman_nfl_cntr_un25_reg_cnt_axb_3_i_i_5958) + ); + defparam com_cmm_u_cmm_errman_nfl_cntr_un25_reg_cnt_axb_2.INIT = 4'h9; + LUT2 com_cmm_u_cmm_errman_nfl_cntr_un25_reg_cnt_axb_2 ( + .I0(com_cmm_u_cmm_errman_nfl_cntr_N_26174_i), + .I1(com_cmm_u_cmm_errman_nfl_num[2]), + .O(com_cmm_u_cmm_errman_nfl_cntr_un25_reg_cnt_axb_2_5959) + ); + defparam com_cmm_u_cmm_errman_nfl_cntr_un25_reg_cnt_axb_1.INIT = 16'h6999; + LUT4 com_cmm_u_cmm_errman_nfl_cntr_un25_reg_cnt_axb_1 ( + .I0(com_cmm_u_cmm_errman_nfl_cntr_N_26172_i), + .I1(com_cmm_u_cmm_errman_nfl_num_c1_5822), + .I2(com_cmm_u_cmm_errman_to_incr_1ro), + .I3(com_cmm_u_cmm_pm_dev_power_state_eq_d0), + .O(com_cmm_u_cmm_errman_nfl_cntr_un25_reg_cnt_axb_1_5960) + ); + defparam com_cmm_u_cmm_errman_nfl_cntr_un14_reg_cnt_axb_3.INIT = 4'h2; + LUT1 com_cmm_u_cmm_errman_nfl_cntr_un14_reg_cnt_axb_3 ( + .I0(com_cmm_u_cmm_errman_nfl_cntr_un25_reg_cnt_axb_3_i), + .O(com_cmm_u_cmm_errman_nfl_cntr_un14_reg_cnt_axb_3_5961) + ); + defparam com_cmm_u_cmm_errman_nfl_cntr_un14_reg_cnt_axb_2.INIT = 4'h6; + LUT2 com_cmm_u_cmm_errman_nfl_cntr_un14_reg_cnt_axb_2 ( + .I0(com_cmm_u_cmm_errman_nfl_cntr_N_26174_i), + .I1(com_cmm_u_cmm_errman_nfl_num[2]), + .O(com_cmm_u_cmm_errman_nfl_cntr_un14_reg_cnt_axb_2_5962) + ); + defparam com_cmm_u_cmm_errman_nfl_cntr_un14_reg_cnt_axb_1.INIT = 16'h9666; + LUT4 com_cmm_u_cmm_errman_nfl_cntr_un14_reg_cnt_axb_1 ( + .I0(com_cmm_u_cmm_errman_nfl_cntr_N_26172_i), + .I1(com_cmm_u_cmm_errman_nfl_num_c1_5822), + .I2(com_cmm_u_cmm_errman_to_incr_1ro), + .I3(com_cmm_u_cmm_pm_dev_power_state_eq_d0), + .O(com_cmm_u_cmm_errman_nfl_cntr_un14_reg_cnt_axb_1_5963) + ); + defparam com_cmm_u_cmm_errman_wtd_ftl_N_57663_i.INIT = 8'hF7; + LUT3_L com_cmm_u_cmm_errman_wtd_ftl_N_57663_i ( + .I0(N_56022_i), + .I1(N_57661), + .I2(com_tlm_cmmt_err_tlp_malformed), + .LO(com_cmm_u_cmm_errman_wtd_ftl_N_57663_i_5964) + ); + defparam com_cmm_u_cmm_errman_wtd_ftl_N_74_2_i.INIT = 4'hD; + LUT2_L com_cmm_u_cmm_errman_wtd_ftl_N_74_2_i ( + .I0(N_57661), + .I1(com_tlm_cmmt_err_tlp_malformed), + .LO(com_cmm_u_cmm_errman_N_74_2_i) + ); + FDC com_cmm_u_cmm_errman_wtd_ftl_reg_inc_dec_b ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_wtd_ftl_N_57663_i_5964), + .Q(com_cmm_u_cmm_errman_ftl_add_sub_b), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_errman_wtd_ftl_reg_ftl_num_2_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_wtd_ftl_to_incrdf2), + .Q(com_cmm_u_cmm_errman_ftl_num[2]), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_errman_wtd_ftl_reg_ftl_num_1_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(N_13_i), + .Q(com_cmm_u_cmm_errman_ftl_num[1]), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_errman_wtd_ftl_reg_ftl_num_0_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(N_5_i), + .Q(com_cmm_u_cmm_errman_ftl_num[0]), + .CLR(com_cmm_rst_351) + ); + INV com_cmm_u_cmm_errman_wtd_ftl_ftl_num_i_2_ ( + .I(com_cmm_u_cmm_errman_ftl_num[2]), + .O(com_cmm_u_cmm_errman_ftl_num_i[2]) + ); + INV com_cmm_u_cmm_errman_wtd_ftl_ftl_num_i_1_ ( + .I(com_cmm_u_cmm_errman_ftl_num[1]), + .O(com_cmm_u_cmm_errman_ftl_num_i[1]) + ); + INV com_cmm_u_cmm_errman_wtd_ftl_ftl_num_i_0_ ( + .I(com_cmm_u_cmm_errman_ftl_num[0]), + .O(com_cmm_u_cmm_errman_ftl_num_i[0]) + ); + VCC com_cmm_u_cmm_errman_ftl_cntr_VCC ( + .P(com_cmm_u_cmm_errman_ftl_cntr_VCC_5971) + ); + GND com_cmm_u_cmm_errman_ftl_cntr_GND ( + .G(com_cmm_u_cmm_errman_ftl_cntr_GND_5967) + ); + MUXCY_L com_cmm_u_cmm_errman_ftl_cntr_un14_reg_cnt_cry_0 ( + .CI(com_cmm_u_cmm_errman_ftl_cntr_GND_5967), + .DI(com_cmm_u_cmm_errman_ftl_cntr_N_17829_i), + .LO(com_cmm_u_cmm_errman_ftl_cntr_un14_reg_cnt_cry_0_5965), + .S(com_cmm_u_cmm_errman_ftl_cntr_un14_reg_cnt_axb_0_5975) + ); + MUXCY_L com_cmm_u_cmm_errman_ftl_cntr_un14_reg_cnt_cry_1 ( + .CI(com_cmm_u_cmm_errman_ftl_cntr_un14_reg_cnt_cry_0_5965), + .DI(com_cmm_u_cmm_errman_ftl_cntr_N_17831_i), + .LO(com_cmm_u_cmm_errman_ftl_cntr_un14_reg_cnt_cry_1_5966), + .S(com_cmm_u_cmm_errman_ftl_cntr_un14_reg_cnt_axb_1_5986) + ); + XORCY com_cmm_u_cmm_errman_ftl_cntr_un14_reg_cnt_s_1 ( + .CI(com_cmm_u_cmm_errman_ftl_cntr_un14_reg_cnt_cry_0_5965), + .LI(com_cmm_u_cmm_errman_ftl_cntr_un14_reg_cnt_axb_1_5986), + .O(com_cmm_u_cmm_errman_ftl_cntr_un14_reg_cnt_s_1_0) + ); + MUXCY_L com_cmm_u_cmm_errman_ftl_cntr_un14_reg_cnt_cry_2 ( + .CI(com_cmm_u_cmm_errman_ftl_cntr_un14_reg_cnt_cry_1_5966), + .DI(com_cmm_u_cmm_errman_ftl_cntr_N_17833_i), + .LO(com_cmm_u_cmm_errman_ftl_cntr_un14_reg_cnt_cry_2_5968), + .S(com_cmm_u_cmm_errman_ftl_cntr_un14_reg_cnt_axb_2_5985) + ); + XORCY com_cmm_u_cmm_errman_ftl_cntr_un14_reg_cnt_s_2 ( + .CI(com_cmm_u_cmm_errman_ftl_cntr_un14_reg_cnt_cry_1_5966), + .LI(com_cmm_u_cmm_errman_ftl_cntr_un14_reg_cnt_axb_2_5985), + .O(com_cmm_u_cmm_errman_ftl_cntr_un14_reg_cnt_s_2_0) + ); + MUXCY com_cmm_u_cmm_errman_ftl_cntr_un14_reg_cnt_cry_3 ( + .CI(com_cmm_u_cmm_errman_ftl_cntr_un14_reg_cnt_cry_2_5968), + .DI(com_cmm_u_cmm_errman_ftl_cntr_GND_5967), + .O(com_cmm_u_cmm_errman_ftl_cntr_un14_reg_cnt_cry_3_5973), + .S(com_cmm_u_cmm_errman_ftl_cntr_un14_reg_cnt_axb_3_5983) + ); + XORCY com_cmm_u_cmm_errman_ftl_cntr_un14_reg_cnt_s_3 ( + .CI(com_cmm_u_cmm_errman_ftl_cntr_un14_reg_cnt_cry_2_5968), + .LI(com_cmm_u_cmm_errman_ftl_cntr_un14_reg_cnt_axb_3_5983), + .O(com_cmm_u_cmm_errman_ftl_cntr_un14_reg_cnt_s_3_0) + ); + MUXCY_L com_cmm_u_cmm_errman_ftl_cntr_un25_reg_cnt_cry_0 ( + .CI(com_cmm_u_cmm_errman_ftl_cntr_VCC_5971), + .DI(com_cmm_u_cmm_errman_ftl_num_i[0]), + .LO(com_cmm_u_cmm_errman_ftl_cntr_un25_reg_cnt_cry_0_5969), + .S(com_cmm_u_cmm_errman_ftl_cntr_un25_reg_cnt_axb_0_5976) + ); + MUXCY_L com_cmm_u_cmm_errman_ftl_cntr_un25_reg_cnt_cry_1 ( + .CI(com_cmm_u_cmm_errman_ftl_cntr_un25_reg_cnt_cry_0_5969), + .DI(com_cmm_u_cmm_errman_ftl_num_i[1]), + .LO(com_cmm_u_cmm_errman_ftl_cntr_un25_reg_cnt_cry_1_5970), + .S(com_cmm_u_cmm_errman_ftl_cntr_un25_reg_cnt_axb_1_5982) + ); + XORCY com_cmm_u_cmm_errman_ftl_cntr_un25_reg_cnt_s_1 ( + .CI(com_cmm_u_cmm_errman_ftl_cntr_un25_reg_cnt_cry_0_5969), + .LI(com_cmm_u_cmm_errman_ftl_cntr_un25_reg_cnt_axb_1_5982), + .O(com_cmm_u_cmm_errman_ftl_cntr_un25_reg_cnt_s_1_0) + ); + MUXCY_L com_cmm_u_cmm_errman_ftl_cntr_un25_reg_cnt_cry_2 ( + .CI(com_cmm_u_cmm_errman_ftl_cntr_un25_reg_cnt_cry_1_5970), + .DI(com_cmm_u_cmm_errman_ftl_num_i[2]), + .LO(com_cmm_u_cmm_errman_ftl_cntr_un25_reg_cnt_cry_2_5972), + .S(com_cmm_u_cmm_errman_ftl_cntr_un25_reg_cnt_axb_2_5981) + ); + XORCY com_cmm_u_cmm_errman_ftl_cntr_un25_reg_cnt_s_2 ( + .CI(com_cmm_u_cmm_errman_ftl_cntr_un25_reg_cnt_cry_1_5970), + .LI(com_cmm_u_cmm_errman_ftl_cntr_un25_reg_cnt_axb_2_5981), + .O(com_cmm_u_cmm_errman_ftl_cntr_un25_reg_cnt_s_2_0) + ); + MUXCY_L com_cmm_u_cmm_errman_ftl_cntr_un25_reg_cnt_cry_3 ( + .CI(com_cmm_u_cmm_errman_ftl_cntr_un25_reg_cnt_cry_2_5972), + .DI(com_cmm_u_cmm_errman_ftl_cntr_VCC_5971), + .LO(com_cmm_u_cmm_errman_ftl_cntr_un25_reg_cnt_cry_3_5979), + .S(com_cmm_u_cmm_errman_ftl_cntr_un25_reg_cnt_axb_3_i_i_5980) + ); + XORCY com_cmm_u_cmm_errman_ftl_cntr_un25_reg_cnt_s_3 ( + .CI(com_cmm_u_cmm_errman_ftl_cntr_un25_reg_cnt_cry_2_5972), + .LI(com_cmm_u_cmm_errman_ftl_cntr_un25_reg_cnt_axb_3_i_i_5980), + .O(com_cmm_u_cmm_errman_ftl_cntr_un25_reg_cnt_s_3_0) + ); + defparam com_cmm_u_cmm_errman_ftl_cntr_reg_cnt_6_i_0_0_a2_0_.INIT = 4'h1; + LUT2 com_cmm_u_cmm_errman_ftl_cntr_reg_cnt_6_i_0_0_a2_0_ ( + .I0(NlwRenamedSig_OI_cfg_command_8_), + .I1(NlwRenamedSig_OI_cfg_dcommand[2]), + .O(com_cmm_u_cmm_errman_ftl_cntr_N_58544) + ); + defparam com_cmm_u_cmm_errman_ftl_cntr_oflow_0_a2.INIT = 4'h8; + LUT2 com_cmm_u_cmm_errman_ftl_cntr_oflow_0_a2 ( + .I0(com_cmm_u_cmm_errman_ftl_cntr_reg_extra_5977), + .I1(com_cmm_u_cmm_errman_ftl_cntr_reg_inc_dec_b_5978), + .O(com_cmm_u_cmm_errman_ftl_cntr_oflow) + ); + defparam com_cmm_u_cmm_errman_ftl_cntr_un14_reg_cnt_axb_0.INIT = 4'h6; + LUT2 com_cmm_u_cmm_errman_ftl_cntr_un14_reg_cnt_axb_0 ( + .I0(com_cmm_u_cmm_errman_ftl_cntr_N_17829_i), + .I1(com_cmm_u_cmm_errman_ftl_num[0]), + .O(com_cmm_u_cmm_errman_ftl_cntr_un14_reg_cnt_axb_0_5975) + ); + defparam com_cmm_u_cmm_errman_ftl_cntr_reg_uflow_3_i_a2_0.INIT = 4'h1; + LUT2 com_cmm_u_cmm_errman_ftl_cntr_reg_uflow_3_i_a2_0 ( + .I0(com_cmm_u_cmm_errman_ftl_num[0]), + .I1(com_cmm_u_cmm_errman_ftl_num[1]), + .O(com_cmm_u_cmm_errman_ftl_cntr_reg_uflow_3_i_a2_0_5974) + ); + defparam com_cmm_u_cmm_errman_ftl_cntr_cnt_f0_i_0_0_2_.INIT = 8'h0E; + LUT3 com_cmm_u_cmm_errman_ftl_cntr_cnt_f0_i_0_0_2_ ( + .I0(com_cmm_u_cmm_errman_ftl_cntr_oflow), + .I1(com_cmm_u_cmm_errman_ftl_cntr_reg_cnt[2]), + .I2(com_cmm_u_cmm_errman_ftl_cntr_reg_uflow_5984), + .O(com_cmm_u_cmm_errman_ftl_cntr_N_17833_i) + ); + defparam com_cmm_u_cmm_errman_ftl_cntr_cnt_f0_i_0_0_1_.INIT = 8'h0E; + LUT3 com_cmm_u_cmm_errman_ftl_cntr_cnt_f0_i_0_0_1_ ( + .I0(com_cmm_u_cmm_errman_ftl_cntr_oflow), + .I1(com_cmm_u_cmm_errman_ftl_cntr_reg_cnt[1]), + .I2(com_cmm_u_cmm_errman_ftl_cntr_reg_uflow_5984), + .O(com_cmm_u_cmm_errman_ftl_cntr_N_17831_i) + ); + defparam com_cmm_u_cmm_errman_ftl_cntr_cnt_f0_i_0_0_0_.INIT = 8'h0E; + LUT3 com_cmm_u_cmm_errman_ftl_cntr_cnt_f0_i_0_0_0_ ( + .I0(com_cmm_u_cmm_errman_ftl_cntr_oflow), + .I1(com_cmm_u_cmm_errman_ftl_cntr_reg_cnt[0]), + .I2(com_cmm_u_cmm_errman_ftl_cntr_reg_uflow_5984), + .O(com_cmm_u_cmm_errman_ftl_cntr_N_17829_i) + ); + defparam com_cmm_u_cmm_errman_ftl_cntr_reg_extra_6_u_i_0_0.INIT = 16'h5404; + LUT4_L com_cmm_u_cmm_errman_ftl_cntr_reg_extra_6_u_i_0_0 ( + .I0(com_cmm_u_cmm_errman_ftl_cntr_N_58544), + .I1(com_cmm_u_cmm_errman_ftl_cntr_un25_reg_cnt_s_4_0), + .I2(com_cmm_u_cmm_errman_ftl_add_sub_b), + .I3(com_cmm_u_cmm_errman_ftl_cntr_un14_reg_cnt_cry_3_5973), + .LO(com_cmm_u_cmm_errman_ftl_cntr_N_17881_i) + ); + defparam com_cmm_u_cmm_errman_ftl_cntr_reg_uflow_3_i.INIT = 16'h2202; + LUT4_L com_cmm_u_cmm_errman_ftl_cntr_reg_uflow_3_i ( + .I0(com_cmm_u_cmm_errman_send_ftl_3_0_a2_5823), + .I1(com_cmm_u_cmm_errman_ftl_add_sub_b), + .I2(com_cmm_u_cmm_errman_ftl_cntr_reg_uflow_3_i_a2_0_5974), + .I3(com_cmm_u_cmm_errman_ftl_num[2]), + .LO(com_cmm_u_cmm_errman_ftl_cntr_N_18871_i) + ); + defparam com_cmm_u_cmm_errman_ftl_cntr_reg_cnt_6_i_0_0_1_.INIT = 16'h5404; + LUT4_L com_cmm_u_cmm_errman_ftl_cntr_reg_cnt_6_i_0_0_1_ ( + .I0(com_cmm_u_cmm_errman_ftl_cntr_N_58544), + .I1(com_cmm_u_cmm_errman_ftl_cntr_un25_reg_cnt_s_1_0), + .I2(com_cmm_u_cmm_errman_ftl_add_sub_b), + .I3(com_cmm_u_cmm_errman_ftl_cntr_un14_reg_cnt_s_1_0), + .LO(com_cmm_u_cmm_errman_ftl_cntr_N_17875_i) + ); + defparam com_cmm_u_cmm_errman_ftl_cntr_reg_cnt_6_i_0_0_0_.INIT = 16'h4051; + LUT4_L com_cmm_u_cmm_errman_ftl_cntr_reg_cnt_6_i_0_0_0_ ( + .I0(com_cmm_u_cmm_errman_ftl_cntr_N_58544), + .I1(com_cmm_u_cmm_errman_ftl_add_sub_b), + .I2(com_cmm_u_cmm_errman_ftl_cntr_un14_reg_cnt_axb_0_5975), + .I3(com_cmm_u_cmm_errman_ftl_cntr_un25_reg_cnt_axb_0_5976), + .LO(com_cmm_u_cmm_errman_ftl_cntr_N_17873_i) + ); + defparam com_cmm_u_cmm_errman_ftl_cntr_reg_count_7_f0_i_0_0_3_.INIT = 16'h0054; + LUT4_L com_cmm_u_cmm_errman_ftl_cntr_reg_count_7_f0_i_0_0_3_ ( + .I0(com_cmm_u_cmm_errman_ftl_cntr_N_58544), + .I1(com_cmm_u_cmm_errman_ftl_cntr_oflow), + .I2(com_cmm_u_cmm_errman_ftl_cntr_reg_cnt[3]), + .I3(com_cmm_u_cmm_errman_ftl_cntr_reg_uflow_5984), + .LO(com_cmm_u_cmm_errman_ftl_cntr_N_17843_i) + ); + defparam com_cmm_u_cmm_errman_ftl_cntr_reg_count_7_f0_i_0_0_2_.INIT = 16'h0054; + LUT4_L com_cmm_u_cmm_errman_ftl_cntr_reg_count_7_f0_i_0_0_2_ ( + .I0(com_cmm_u_cmm_errman_ftl_cntr_N_58544), + .I1(com_cmm_u_cmm_errman_ftl_cntr_oflow), + .I2(com_cmm_u_cmm_errman_ftl_cntr_reg_cnt[2]), + .I3(com_cmm_u_cmm_errman_ftl_cntr_reg_uflow_5984), + .LO(com_cmm_u_cmm_errman_ftl_cntr_N_17841_i) + ); + defparam com_cmm_u_cmm_errman_ftl_cntr_reg_count_7_f0_i_0_0_1_.INIT = 16'h0054; + LUT4_L com_cmm_u_cmm_errman_ftl_cntr_reg_count_7_f0_i_0_0_1_ ( + .I0(com_cmm_u_cmm_errman_ftl_cntr_N_58544), + .I1(com_cmm_u_cmm_errman_ftl_cntr_oflow), + .I2(com_cmm_u_cmm_errman_ftl_cntr_reg_cnt[1]), + .I3(com_cmm_u_cmm_errman_ftl_cntr_reg_uflow_5984), + .LO(com_cmm_u_cmm_errman_ftl_cntr_N_17839_i) + ); + defparam com_cmm_u_cmm_errman_ftl_cntr_reg_count_7_f0_i_0_0_0_.INIT = 16'h0054; + LUT4_L com_cmm_u_cmm_errman_ftl_cntr_reg_count_7_f0_i_0_0_0_ ( + .I0(com_cmm_u_cmm_errman_ftl_cntr_N_58544), + .I1(com_cmm_u_cmm_errman_ftl_cntr_oflow), + .I2(com_cmm_u_cmm_errman_ftl_cntr_reg_cnt[0]), + .I3(com_cmm_u_cmm_errman_ftl_cntr_reg_uflow_5984), + .LO(com_cmm_u_cmm_errman_ftl_cntr_N_17837_i) + ); + defparam com_cmm_u_cmm_errman_ftl_cntr_reg_cnt_6_i_0_0_3_.INIT = 16'h5404; + LUT4_L com_cmm_u_cmm_errman_ftl_cntr_reg_cnt_6_i_0_0_3_ ( + .I0(com_cmm_u_cmm_errman_ftl_cntr_N_58544), + .I1(com_cmm_u_cmm_errman_ftl_cntr_un25_reg_cnt_s_3_0), + .I2(com_cmm_u_cmm_errman_ftl_add_sub_b), + .I3(com_cmm_u_cmm_errman_ftl_cntr_un14_reg_cnt_s_3_0), + .LO(com_cmm_u_cmm_errman_ftl_cntr_N_17879_i) + ); + defparam com_cmm_u_cmm_errman_ftl_cntr_reg_cnt_6_i_0_0_2_.INIT = 16'h5404; + LUT4_L com_cmm_u_cmm_errman_ftl_cntr_reg_cnt_6_i_0_0_2_ ( + .I0(com_cmm_u_cmm_errman_ftl_cntr_N_58544), + .I1(com_cmm_u_cmm_errman_ftl_cntr_un25_reg_cnt_s_2_0), + .I2(com_cmm_u_cmm_errman_ftl_add_sub_b), + .I3(com_cmm_u_cmm_errman_ftl_cntr_un14_reg_cnt_s_2_0), + .LO(com_cmm_u_cmm_errman_ftl_cntr_N_17877_i) + ); + defparam com_cmm_u_cmm_errman_ftl_cntr_un25_reg_cnt_axb_0.INIT = 4'h6; + LUT2 com_cmm_u_cmm_errman_ftl_cntr_un25_reg_cnt_axb_0 ( + .I0(com_cmm_u_cmm_errman_ftl_cntr_N_17829_i), + .I1(com_cmm_u_cmm_errman_ftl_num_i[0]), + .O(com_cmm_u_cmm_errman_ftl_cntr_un25_reg_cnt_axb_0_5976) + ); + FDC com_cmm_u_cmm_errman_ftl_cntr_reg_extra ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_ftl_cntr_N_17881_i), + .Q(com_cmm_u_cmm_errman_ftl_cntr_reg_extra_5977), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_errman_ftl_cntr_reg_uflow ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_ftl_cntr_N_18871_i), + .Q(com_cmm_u_cmm_errman_ftl_cntr_reg_uflow_5984), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_errman_ftl_cntr_reg_inc_dec_b ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_ftl_add_sub_b), + .Q(com_cmm_u_cmm_errman_ftl_cntr_reg_inc_dec_b_5978), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_errman_ftl_cntr_reg_cnt_1_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_ftl_cntr_N_17875_i), + .Q(com_cmm_u_cmm_errman_ftl_cntr_reg_cnt[1]), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_errman_ftl_cntr_reg_cnt_0_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_ftl_cntr_N_17873_i), + .Q(com_cmm_u_cmm_errman_ftl_cntr_reg_cnt[0]), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_errman_ftl_cntr_reg_count_3_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_ftl_cntr_N_17843_i), + .Q(com_cmm_u_cmm_errman_cnt_ftl[3]), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_errman_ftl_cntr_reg_count_2_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_ftl_cntr_N_17841_i), + .Q(com_cmm_u_cmm_errman_cnt_ftl[2]), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_errman_ftl_cntr_reg_count_1_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_ftl_cntr_N_17839_i), + .Q(com_cmm_u_cmm_errman_cnt_ftl[1]), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_errman_ftl_cntr_reg_count_0_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_ftl_cntr_N_17837_i), + .Q(com_cmm_u_cmm_errman_cnt_ftl[0]), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_errman_ftl_cntr_reg_cnt_3_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_ftl_cntr_N_17879_i), + .Q(com_cmm_u_cmm_errman_ftl_cntr_reg_cnt[3]), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_errman_ftl_cntr_reg_cnt_2_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_ftl_cntr_N_17877_i), + .Q(com_cmm_u_cmm_errman_ftl_cntr_reg_cnt[2]), + .CLR(com_cmm_rst_351) + ); + defparam com_cmm_u_cmm_errman_ftl_cntr_un25_reg_cnt_s_4.INIT = 4'h1; + LUT1_L com_cmm_u_cmm_errman_ftl_cntr_un25_reg_cnt_s_4 ( + .I0(com_cmm_u_cmm_errman_ftl_cntr_un25_reg_cnt_cry_3_5979), + .LO(com_cmm_u_cmm_errman_ftl_cntr_un25_reg_cnt_s_4_0) + ); + defparam com_cmm_u_cmm_errman_ftl_cntr_un25_reg_cnt_axb_3_i_i.INIT = 8'hF1; + LUT3 com_cmm_u_cmm_errman_ftl_cntr_un25_reg_cnt_axb_3_i_i ( + .I0(com_cmm_u_cmm_errman_ftl_cntr_oflow), + .I1(com_cmm_u_cmm_errman_ftl_cntr_reg_cnt[3]), + .I2(com_cmm_u_cmm_errman_ftl_cntr_reg_uflow_5984), + .O(com_cmm_u_cmm_errman_ftl_cntr_un25_reg_cnt_axb_3_i_i_5980) + ); + defparam com_cmm_u_cmm_errman_ftl_cntr_un25_reg_cnt_axb_2.INIT = 4'h9; + LUT2 com_cmm_u_cmm_errman_ftl_cntr_un25_reg_cnt_axb_2 ( + .I0(com_cmm_u_cmm_errman_ftl_cntr_N_17833_i), + .I1(com_cmm_u_cmm_errman_ftl_num[2]), + .O(com_cmm_u_cmm_errman_ftl_cntr_un25_reg_cnt_axb_2_5981) + ); + defparam com_cmm_u_cmm_errman_ftl_cntr_un25_reg_cnt_axb_1.INIT = 4'h9; + LUT2 com_cmm_u_cmm_errman_ftl_cntr_un25_reg_cnt_axb_1 ( + .I0(com_cmm_u_cmm_errman_ftl_cntr_N_17831_i), + .I1(com_cmm_u_cmm_errman_ftl_num[1]), + .O(com_cmm_u_cmm_errman_ftl_cntr_un25_reg_cnt_axb_1_5982) + ); + defparam com_cmm_u_cmm_errman_ftl_cntr_un14_reg_cnt_axb_3.INIT = 8'h0E; + LUT3 com_cmm_u_cmm_errman_ftl_cntr_un14_reg_cnt_axb_3 ( + .I0(com_cmm_u_cmm_errman_ftl_cntr_oflow), + .I1(com_cmm_u_cmm_errman_ftl_cntr_reg_cnt[3]), + .I2(com_cmm_u_cmm_errman_ftl_cntr_reg_uflow_5984), + .O(com_cmm_u_cmm_errman_ftl_cntr_un14_reg_cnt_axb_3_5983) + ); + defparam com_cmm_u_cmm_errman_ftl_cntr_un14_reg_cnt_axb_2.INIT = 4'h6; + LUT2 com_cmm_u_cmm_errman_ftl_cntr_un14_reg_cnt_axb_2 ( + .I0(com_cmm_u_cmm_errman_ftl_cntr_N_17833_i), + .I1(com_cmm_u_cmm_errman_ftl_num[2]), + .O(com_cmm_u_cmm_errman_ftl_cntr_un14_reg_cnt_axb_2_5985) + ); + defparam com_cmm_u_cmm_errman_ftl_cntr_un14_reg_cnt_axb_1.INIT = 4'h6; + LUT2 com_cmm_u_cmm_errman_ftl_cntr_un14_reg_cnt_axb_1 ( + .I0(com_cmm_u_cmm_errman_ftl_cntr_N_17831_i), + .I1(com_cmm_u_cmm_errman_ftl_num[1]), + .O(com_cmm_u_cmm_errman_ftl_cntr_un14_reg_cnt_axb_1_5986) + ); + defparam com_cmm_u_cmm_errman_wtd_cplt_mod_add_sub_b23_i_0_i_o3.INIT = 4'h4; + LUT2 com_cmm_u_cmm_errman_wtd_cplt_mod_add_sub_b23_i_0_i_o3 ( + .I0(com_cmmt_err_tlp_p_cpl), + .I1(com_cmmt_err_tlp_ur), + .O(com_cmm_u_cmm_errman_N_55916_i) + ); + defparam com_cmm_u_cmm_errman_wtd_cplt_N_58593_i.INIT = 4'hB; + LUT2_L com_cmm_u_cmm_errman_wtd_cplt_N_58593_i ( + .I0(com_cmm_u_cmm_errman_N_55916_i), + .I1(com_cmm_u_cmm_errman_N_56322_i), + .LO(com_cmm_u_cmm_errman_wtd_cplt_N_58593_i_5987) + ); + defparam com_cmm_u_cmm_errman_wtd_cplt_mod_to_incr_0_x2_i_x3_i_x3_0_.INIT = 4'h6; + LUT2_L com_cmm_u_cmm_errman_wtd_cplt_mod_to_incr_0_x2_i_x3_i_x3_0_ ( + .I0(com_cmm_u_cmm_errman_N_55916_i), + .I1(com_cmm_u_cmm_errman_N_56322_i), + .LO(com_cmm_u_cmm_errman_wtd_cplt_N_56474_i_0) + ); + FDC com_cmm_u_cmm_errman_wtd_cplt_reg_inc_dec_b ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_wtd_cplt_N_58593_i_5987), + .Q(com_cmm_u_cmm_errman_cplt_add_sub_b), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_errman_wtd_cplt_reg_cpl_num_0_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_wtd_cplt_N_56474_i_0), + .Q(com_cmm_u_cmm_errman_cplt_num[0]), + .CLR(com_cmm_rst_351) + ); + defparam com_cmm_u_cmm_errman_cplt_cntr_un14_reg_cnt_p4.INIT = 16'h8000; + LUT4 com_cmm_u_cmm_errman_cplt_cntr_un14_reg_cnt_p4 ( + .I0(com_cmm_u_cmm_errman_cplt_cntr_N_26185_i), + .I1(com_cmm_u_cmm_errman_cplt_cntr_un25_reg_cnt_axb1_i), + .I2(com_cmm_u_cmm_errman_cplt_cntr_un25_reg_cnt_axb2_i), + .I3(com_cmm_u_cmm_errman_cplt_num[0]), + .O(com_cmm_u_cmm_errman_cplt_cntr_un14_reg_cnt_p4_5990) + ); + defparam com_cmm_u_cmm_errman_cplt_cntr_un14_reg_cnt_p4_0.INIT = 4'h8; + LUT2_L com_cmm_u_cmm_errman_cplt_cntr_un14_reg_cnt_p4_0 ( + .I0(com_cmm_u_cmm_errman_cplt_cntr_un14_reg_cnt_p4_5990), + .I1(com_cmm_u_cmm_errman_cplt_cntr_un25_reg_cnt_axb3_i), + .LO(com_cmm_u_cmm_errman_cplt_cntr_un14_reg_cnt[4]) + ); + defparam com_cmm_u_cmm_errman_cplt_cntr_un25_reg_cnt_p4.INIT = 16'hFEFF; + LUT4 com_cmm_u_cmm_errman_cplt_cntr_un25_reg_cnt_p4 ( + .I0(com_cmm_u_cmm_errman_cplt_cntr_N_26185_i), + .I1(com_cmm_u_cmm_errman_cplt_cntr_un25_reg_cnt_axb1_i), + .I2(com_cmm_u_cmm_errman_cplt_cntr_un25_reg_cnt_axb2_i), + .I3(com_cmm_u_cmm_errman_cplt_num[0]), + .O(com_cmm_u_cmm_errman_cplt_cntr_un25_reg_cnt_p4_5989) + ); + defparam com_cmm_u_cmm_errman_cplt_cntr_cnt_f0_i_0_.INIT = 16'h00EA; + LUT4 com_cmm_u_cmm_errman_cplt_cntr_cnt_f0_i_0_ ( + .I0(com_cmm_u_cmm_errman_cplt_cntr_reg_cnt[0]), + .I1(com_cmm_u_cmm_errman_cplt_cntr_reg_extra_5992), + .I2(com_cmm_u_cmm_errman_cplt_cntr_reg_inc_dec_b_5994), + .I3(com_cmm_u_cmm_errman_cplt_cntr_reg_uflow_5993), + .O(com_cmm_u_cmm_errman_cplt_cntr_N_26185_i) + ); + defparam com_cmm_u_cmm_errman_cplt_cntr_cnt_f0_i_1_.INIT = 16'h00EA; + LUT4 com_cmm_u_cmm_errman_cplt_cntr_cnt_f0_i_1_ ( + .I0(com_cmm_u_cmm_errman_cplt_cntr_reg_cnt[1]), + .I1(com_cmm_u_cmm_errman_cplt_cntr_reg_extra_5992), + .I2(com_cmm_u_cmm_errman_cplt_cntr_reg_inc_dec_b_5994), + .I3(com_cmm_u_cmm_errman_cplt_cntr_reg_uflow_5993), + .O(com_cmm_u_cmm_errman_cplt_cntr_un25_reg_cnt_axb1_i) + ); + defparam com_cmm_u_cmm_errman_cplt_cntr_cnt_f0_i_2_.INIT = 16'h00EA; + LUT4 com_cmm_u_cmm_errman_cplt_cntr_cnt_f0_i_2_ ( + .I0(com_cmm_u_cmm_errman_cplt_cntr_reg_cnt[2]), + .I1(com_cmm_u_cmm_errman_cplt_cntr_reg_extra_5992), + .I2(com_cmm_u_cmm_errman_cplt_cntr_reg_inc_dec_b_5994), + .I3(com_cmm_u_cmm_errman_cplt_cntr_reg_uflow_5993), + .O(com_cmm_u_cmm_errman_cplt_cntr_un25_reg_cnt_axb2_i) + ); + defparam com_cmm_u_cmm_errman_cplt_cntr_cnt_f0_i_3_.INIT = 16'h00EA; + LUT4 com_cmm_u_cmm_errman_cplt_cntr_cnt_f0_i_3_ ( + .I0(com_cmm_u_cmm_errman_cplt_cntr_reg_cnt[3]), + .I1(com_cmm_u_cmm_errman_cplt_cntr_reg_extra_5992), + .I2(com_cmm_u_cmm_errman_cplt_cntr_reg_inc_dec_b_5994), + .I3(com_cmm_u_cmm_errman_cplt_cntr_reg_uflow_5993), + .O(com_cmm_u_cmm_errman_cplt_cntr_un25_reg_cnt_axb3_i) + ); + defparam com_cmm_u_cmm_errman_cplt_cntr_un25_reg_cnt_c1.INIT = 4'h4; + LUT2_L com_cmm_u_cmm_errman_cplt_cntr_un25_reg_cnt_c1 ( + .I0(com_cmm_u_cmm_errman_cplt_cntr_N_26185_i), + .I1(com_cmm_u_cmm_errman_cplt_num[0]), + .LO(com_cmm_u_cmm_errman_cplt_cntr_un25_reg_cnt_c1_5988) + ); + defparam com_cmm_u_cmm_errman_cplt_cntr_reg_cnt_6_0_i_m2_0_am_2_.INIT = 8'hD2; + LUT3 com_cmm_u_cmm_errman_cplt_cntr_reg_cnt_6_0_i_m2_0_am_2_ ( + .I0(com_cmm_u_cmm_errman_cplt_cntr_un25_reg_cnt_c1_5988), + .I1(com_cmm_u_cmm_errman_cplt_cntr_un25_reg_cnt_axb1_i), + .I2(com_cmm_u_cmm_errman_cplt_cntr_un25_reg_cnt_axb2_i), + .O(com_cmm_u_cmm_errman_cplt_cntr_reg_cnt_6_0_i_m2_0_am_0[2]) + ); + defparam com_cmm_u_cmm_errman_cplt_cntr_reg_cnt_6_0_i_m2_0_bm_2_.INIT = 16'h78F0; + LUT4 com_cmm_u_cmm_errman_cplt_cntr_reg_cnt_6_0_i_m2_0_bm_2_ ( + .I0(com_cmm_u_cmm_errman_cplt_cntr_N_26185_i), + .I1(com_cmm_u_cmm_errman_cplt_cntr_un25_reg_cnt_axb1_i), + .I2(com_cmm_u_cmm_errman_cplt_cntr_un25_reg_cnt_axb2_i), + .I3(com_cmm_u_cmm_errman_cplt_num[0]), + .O(com_cmm_u_cmm_errman_cplt_cntr_reg_cnt_6_0_i_m2_0_bm_0[2]) + ); + MUXF5 com_cmm_u_cmm_errman_cplt_cntr_reg_cnt_6_0_i_m2_0_2_ ( + .I0(com_cmm_u_cmm_errman_cplt_cntr_reg_cnt_6_0_i_m2_0_am_0[2]), + .I1(com_cmm_u_cmm_errman_cplt_cntr_reg_cnt_6_0_i_m2_0_bm_0[2]), + .O(com_cmm_u_cmm_errman_cplt_cntr_reg_cnt_6_0_i_m2_0[2]), + .S(com_cmm_u_cmm_errman_cplt_add_sub_b) + ); + defparam com_cmm_u_cmm_errman_cplt_cntr_reg_extra_6_0_u_i_m2_0.INIT = 16'h888D; + LUT4_L com_cmm_u_cmm_errman_cplt_cntr_reg_extra_6_0_u_i_m2_0 ( + .I0(com_cmm_u_cmm_errman_cplt_add_sub_b), + .I1(com_cmm_u_cmm_errman_cplt_cntr_un14_reg_cnt[4]), + .I2(com_cmm_u_cmm_errman_cplt_cntr_un25_reg_cnt_axb3_i), + .I3(com_cmm_u_cmm_errman_cplt_cntr_un25_reg_cnt_p4_5989), + .LO(com_cmm_u_cmm_errman_cplt_cntr_reg_extra_6_0_u_i_m2_0_5991) + ); + defparam com_cmm_u_cmm_errman_cplt_cntr_reg_uflow_3_0_a2.INIT = 8'h40; + LUT3_L com_cmm_u_cmm_errman_cplt_cntr_reg_uflow_3_0_a2 ( + .I0(com_cmm_u_cmm_errman_cplt_add_sub_b), + .I1(com_cmm_u_cmm_errman_un1_reg_uflow_3), + .I2(com_cmm_u_cmm_errman_cplt_num[0]), + .LO(com_cmm_u_cmm_errman_cplt_cntr_reg_uflow_3) + ); + defparam com_cmm_u_cmm_errman_cplt_cntr_reg_cnt_6_0_i_m2_0_3_.INIT = 16'h782D; + LUT4_L com_cmm_u_cmm_errman_cplt_cntr_reg_cnt_6_0_i_m2_0_3_ ( + .I0(com_cmm_u_cmm_errman_cplt_add_sub_b), + .I1(com_cmm_u_cmm_errman_cplt_cntr_un14_reg_cnt_p4_5990), + .I2(com_cmm_u_cmm_errman_cplt_cntr_un25_reg_cnt_axb3_i), + .I3(com_cmm_u_cmm_errman_cplt_cntr_un25_reg_cnt_p4_5989), + .LO(com_cmm_u_cmm_errman_cplt_cntr_reg_cnt_6_0_i_m2_0[3]) + ); + defparam com_cmm_u_cmm_errman_cplt_cntr_reg_cnt_6_0_i_m2_0_1_.INIT = 16'h69F0; + LUT4_L com_cmm_u_cmm_errman_cplt_cntr_reg_cnt_6_0_i_m2_0_1_ ( + .I0(com_cmm_u_cmm_errman_cplt_cntr_N_26185_i), + .I1(com_cmm_u_cmm_errman_cplt_add_sub_b), + .I2(com_cmm_u_cmm_errman_cplt_cntr_un25_reg_cnt_axb1_i), + .I3(com_cmm_u_cmm_errman_cplt_num[0]), + .LO(com_cmm_u_cmm_errman_cplt_cntr_reg_cnt_6_0_i_m2_0[1]) + ); + defparam com_cmm_u_cmm_errman_cplt_cntr_reg_cnt_6_0_i_m2_0_0_.INIT = 4'h6; + LUT2_L com_cmm_u_cmm_errman_cplt_cntr_reg_cnt_6_0_i_m2_0_0_ ( + .I0(com_cmm_u_cmm_errman_cplt_cntr_N_26185_i), + .I1(com_cmm_u_cmm_errman_cplt_num[0]), + .LO(com_cmm_u_cmm_errman_cplt_cntr_reg_cnt_6_0_i_m2_0[0]) + ); + FDC com_cmm_u_cmm_errman_cplt_cntr_reg_extra ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_cplt_cntr_reg_extra_6_0_u_i_m2_0_5991), + .Q(com_cmm_u_cmm_errman_cplt_cntr_reg_extra_5992), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_errman_cplt_cntr_reg_uflow ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_cplt_cntr_reg_uflow_3), + .Q(com_cmm_u_cmm_errman_cplt_cntr_reg_uflow_5993), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_errman_cplt_cntr_reg_inc_dec_b ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_cplt_add_sub_b), + .Q(com_cmm_u_cmm_errman_cplt_cntr_reg_inc_dec_b_5994), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_errman_cplt_cntr_reg_cnt_3_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_cplt_cntr_reg_cnt_6_0_i_m2_0[3]), + .Q(com_cmm_u_cmm_errman_cplt_cntr_reg_cnt[3]), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_errman_cplt_cntr_reg_cnt_2_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_cplt_cntr_reg_cnt_6_0_i_m2_0[2]), + .Q(com_cmm_u_cmm_errman_cplt_cntr_reg_cnt[2]), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_errman_cplt_cntr_reg_cnt_1_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_cplt_cntr_reg_cnt_6_0_i_m2_0[1]), + .Q(com_cmm_u_cmm_errman_cplt_cntr_reg_cnt[1]), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_errman_cplt_cntr_reg_cnt_0_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_cplt_cntr_reg_cnt_6_0_i_m2_0[0]), + .Q(com_cmm_u_cmm_errman_cplt_cntr_reg_cnt[0]), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_errman_cplt_cntr_reg_count_3_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_cplt_cntr_un25_reg_cnt_axb3_i), + .Q(com_cmm_u_cmm_errman_cnt_cplt[3]), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_errman_cplt_cntr_reg_count_2_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_cplt_cntr_un25_reg_cnt_axb2_i), + .Q(com_cmm_u_cmm_errman_cnt_cplt[2]), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_errman_cplt_cntr_reg_count_1_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_cplt_cntr_un25_reg_cnt_axb1_i), + .Q(com_cmm_u_cmm_errman_cnt_cplt[1]), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_errman_cplt_cntr_reg_count_0_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_cplt_cntr_N_26185_i), + .Q(com_cmm_u_cmm_errman_cnt_cplt[0]), + .CLR(com_cmm_rst_351) + ); + defparam com_cmm_u_cmm_errman_wtd_cplu_mod_add_sub_b23_i_0_0_o2.INIT = 4'h8; + LUT2 com_cmm_u_cmm_errman_wtd_cplu_mod_add_sub_b23_i_0_0_o2 ( + .I0(com_cmm_gnt_errman), + .I1(com_cmm_u_cmm_errman_cs_is_cplu_5835), + .O(com_cmm_u_cmm_errman_N_56208_i) + ); + defparam com_cmm_u_cmm_errman_wtd_cplu_mod_add_sub_b23_i_0_0_a2.INIT = 8'h4C; + LUT3 com_cmm_u_cmm_errman_wtd_cplu_mod_add_sub_b23_i_0_0_a2 ( + .I0(cfg_err_cpl_abort_n), + .I1(cfg_err_posted_n), + .I2(cfg_err_ur_n), + .O(com_cmm_u_cmm_errman_N_59526) + ); + defparam com_cmm_u_cmm_errman_wtd_cplu_N_86724_i.INIT = 4'hD; + LUT2_L com_cmm_u_cmm_errman_wtd_cplu_N_86724_i ( + .I0(com_cmm_u_cmm_errman_N_56208_i), + .I1(com_cmm_u_cmm_errman_N_59526), + .LO(com_cmm_u_cmm_errman_wtd_cplu_N_86724_i_5995) + ); + defparam com_cmm_u_cmm_errman_wtd_cplu_mod_to_incr_0_x2_i_0_0_.INIT = 4'h6; + LUT2_L com_cmm_u_cmm_errman_wtd_cplu_mod_to_incr_0_x2_i_0_0_ ( + .I0(com_cmm_u_cmm_errman_N_56208_i), + .I1(com_cmm_u_cmm_errman_N_59526), + .LO(com_cmm_u_cmm_errman_wtd_cplu_N_39979_i) + ); + FDC com_cmm_u_cmm_errman_wtd_cplu_reg_inc_dec_b ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_wtd_cplu_N_86724_i_5995), + .Q(com_cmm_u_cmm_errman_cplu_add_sub_b), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_errman_wtd_cplu_reg_cpl_num_0_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_wtd_cplu_N_39979_i), + .Q(com_cmm_u_cmm_errman_cplu_num[0]), + .CLR(com_cmm_rst_351) + ); + defparam com_cmm_u_cmm_errman_cplu_cntr_un14_reg_cnt_p4.INIT = 16'h8000; + LUT4 com_cmm_u_cmm_errman_cplu_cntr_un14_reg_cnt_p4 ( + .I0(com_cmm_u_cmm_errman_cplu_cntr_N_26200_i), + .I1(com_cmm_u_cmm_errman_cplu_cntr_un25_reg_cnt_axb1_i), + .I2(com_cmm_u_cmm_errman_cplu_cntr_un25_reg_cnt_axb2_i), + .I3(com_cmm_u_cmm_errman_cplu_num[0]), + .O(com_cmm_u_cmm_errman_cplu_cntr_un14_reg_cnt_p4_5997) + ); + defparam com_cmm_u_cmm_errman_cplu_cntr_un14_reg_cnt_p4_0.INIT = 4'h8; + LUT2_L com_cmm_u_cmm_errman_cplu_cntr_un14_reg_cnt_p4_0 ( + .I0(com_cmm_u_cmm_errman_cplu_cntr_un14_reg_cnt_p4_5997), + .I1(com_cmm_u_cmm_errman_cplu_cntr_un25_reg_cnt_axb3_i), + .LO(com_cmm_u_cmm_errman_cplu_cntr_un14_reg_cnt[4]) + ); + defparam com_cmm_u_cmm_errman_cplu_cntr_un25_reg_cnt_p4.INIT = 16'hFEFF; + LUT4 com_cmm_u_cmm_errman_cplu_cntr_un25_reg_cnt_p4 ( + .I0(com_cmm_u_cmm_errman_cplu_cntr_N_26200_i), + .I1(com_cmm_u_cmm_errman_cplu_cntr_un25_reg_cnt_axb1_i), + .I2(com_cmm_u_cmm_errman_cplu_cntr_un25_reg_cnt_axb2_i), + .I3(com_cmm_u_cmm_errman_cplu_num[0]), + .O(com_cmm_u_cmm_errman_cplu_cntr_un25_reg_cnt_p4_5996) + ); + defparam com_cmm_u_cmm_errman_cplu_cntr_cnt_f0_i_0_.INIT = 16'h00EA; + LUT4 com_cmm_u_cmm_errman_cplu_cntr_cnt_f0_i_0_ ( + .I0(com_cmm_u_cmm_errman_cplu_cntr_reg_cnt[0]), + .I1(com_cmm_u_cmm_errman_cplu_cntr_reg_extra_5999), + .I2(com_cmm_u_cmm_errman_cplu_cntr_reg_inc_dec_b_5998), + .I3(com_cmm_u_cmm_errman_cplu_cntr_reg_uflow_6000), + .O(com_cmm_u_cmm_errman_cplu_cntr_N_26200_i) + ); + defparam com_cmm_u_cmm_errman_cplu_cntr_cnt_f0_i_1_.INIT = 16'h00EA; + LUT4 com_cmm_u_cmm_errman_cplu_cntr_cnt_f0_i_1_ ( + .I0(com_cmm_u_cmm_errman_cplu_cntr_reg_cnt[1]), + .I1(com_cmm_u_cmm_errman_cplu_cntr_reg_extra_5999), + .I2(com_cmm_u_cmm_errman_cplu_cntr_reg_inc_dec_b_5998), + .I3(com_cmm_u_cmm_errman_cplu_cntr_reg_uflow_6000), + .O(com_cmm_u_cmm_errman_cplu_cntr_un25_reg_cnt_axb1_i) + ); + defparam com_cmm_u_cmm_errman_cplu_cntr_cnt_f0_i_2_.INIT = 16'h00EA; + LUT4 com_cmm_u_cmm_errman_cplu_cntr_cnt_f0_i_2_ ( + .I0(com_cmm_u_cmm_errman_cplu_cntr_reg_cnt[2]), + .I1(com_cmm_u_cmm_errman_cplu_cntr_reg_extra_5999), + .I2(com_cmm_u_cmm_errman_cplu_cntr_reg_inc_dec_b_5998), + .I3(com_cmm_u_cmm_errman_cplu_cntr_reg_uflow_6000), + .O(com_cmm_u_cmm_errman_cplu_cntr_un25_reg_cnt_axb2_i) + ); + defparam com_cmm_u_cmm_errman_cplu_cntr_cnt_f0_i_3_.INIT = 16'h00EA; + LUT4 com_cmm_u_cmm_errman_cplu_cntr_cnt_f0_i_3_ ( + .I0(com_cmm_u_cmm_errman_cplu_cntr_reg_cnt[3]), + .I1(com_cmm_u_cmm_errman_cplu_cntr_reg_extra_5999), + .I2(com_cmm_u_cmm_errman_cplu_cntr_reg_inc_dec_b_5998), + .I3(com_cmm_u_cmm_errman_cplu_cntr_reg_uflow_6000), + .O(com_cmm_u_cmm_errman_cplu_cntr_un25_reg_cnt_axb3_i) + ); + defparam com_cmm_u_cmm_errman_cplu_cntr_un25_reg_cnt_c1.INIT = 4'h4; + LUT2_L com_cmm_u_cmm_errman_cplu_cntr_un25_reg_cnt_c1 ( + .I0(com_cmm_u_cmm_errman_cplu_cntr_N_26200_i), + .I1(com_cmm_u_cmm_errman_cplu_num[0]), + .LO(com_cmm_u_cmm_errman_cplu_cntr_un25_reg_cnt_c1_0) + ); + defparam com_cmm_u_cmm_errman_cplu_cntr_reg_cnt_6_0_i_m2_0_am_2_.INIT = 8'hD2; + LUT3 com_cmm_u_cmm_errman_cplu_cntr_reg_cnt_6_0_i_m2_0_am_2_ ( + .I0(com_cmm_u_cmm_errman_cplu_cntr_un25_reg_cnt_c1_0), + .I1(com_cmm_u_cmm_errman_cplu_cntr_un25_reg_cnt_axb1_i), + .I2(com_cmm_u_cmm_errman_cplu_cntr_un25_reg_cnt_axb2_i), + .O(com_cmm_u_cmm_errman_cplu_cntr_reg_cnt_6_0_i_m2_0_am[2]) + ); + defparam com_cmm_u_cmm_errman_cplu_cntr_reg_cnt_6_0_i_m2_0_bm_2_.INIT = 16'h78F0; + LUT4 com_cmm_u_cmm_errman_cplu_cntr_reg_cnt_6_0_i_m2_0_bm_2_ ( + .I0(com_cmm_u_cmm_errman_cplu_cntr_N_26200_i), + .I1(com_cmm_u_cmm_errman_cplu_cntr_un25_reg_cnt_axb1_i), + .I2(com_cmm_u_cmm_errman_cplu_cntr_un25_reg_cnt_axb2_i), + .I3(com_cmm_u_cmm_errman_cplu_num[0]), + .O(com_cmm_u_cmm_errman_cplu_cntr_reg_cnt_6_0_i_m2_0_bm[2]) + ); + MUXF5 com_cmm_u_cmm_errman_cplu_cntr_reg_cnt_6_0_i_m2_0_2_ ( + .I0(com_cmm_u_cmm_errman_cplu_cntr_reg_cnt_6_0_i_m2_0_am[2]), + .I1(com_cmm_u_cmm_errman_cplu_cntr_reg_cnt_6_0_i_m2_0_bm[2]), + .O(com_cmm_u_cmm_errman_cplu_cntr_reg_cnt_6_0_i_m2_0_0[2]), + .S(com_cmm_u_cmm_errman_cplu_add_sub_b) + ); + defparam com_cmm_u_cmm_errman_cplu_cntr_reg_extra_6_0_u_i_m2_0.INIT = 16'h888D; + LUT4_L com_cmm_u_cmm_errman_cplu_cntr_reg_extra_6_0_u_i_m2_0 ( + .I0(com_cmm_u_cmm_errman_cplu_add_sub_b), + .I1(com_cmm_u_cmm_errman_cplu_cntr_un14_reg_cnt[4]), + .I2(com_cmm_u_cmm_errman_cplu_cntr_un25_reg_cnt_axb3_i), + .I3(com_cmm_u_cmm_errman_cplu_cntr_un25_reg_cnt_p4_5996), + .LO(com_cmm_u_cmm_errman_cplu_cntr_reg_extra_6_0_u_i_m2_0_0) + ); + defparam com_cmm_u_cmm_errman_cplu_cntr_reg_uflow_3_0_a2.INIT = 8'h40; + LUT3_L com_cmm_u_cmm_errman_cplu_cntr_reg_uflow_3_0_a2 ( + .I0(com_cmm_u_cmm_errman_cplu_add_sub_b), + .I1(com_cmm_u_cmm_errman_un1_reg_uflow_3_0), + .I2(com_cmm_u_cmm_errman_cplu_num[0]), + .LO(com_cmm_u_cmm_errman_cplu_cntr_reg_uflow_3) + ); + defparam com_cmm_u_cmm_errman_cplu_cntr_reg_cnt_6_0_i_m2_0_3_.INIT = 16'h782D; + LUT4_L com_cmm_u_cmm_errman_cplu_cntr_reg_cnt_6_0_i_m2_0_3_ ( + .I0(com_cmm_u_cmm_errman_cplu_add_sub_b), + .I1(com_cmm_u_cmm_errman_cplu_cntr_un14_reg_cnt_p4_5997), + .I2(com_cmm_u_cmm_errman_cplu_cntr_un25_reg_cnt_axb3_i), + .I3(com_cmm_u_cmm_errman_cplu_cntr_un25_reg_cnt_p4_5996), + .LO(com_cmm_u_cmm_errman_cplu_cntr_reg_cnt_6_0_i_m2_0_0[3]) + ); + defparam com_cmm_u_cmm_errman_cplu_cntr_reg_cnt_6_0_i_m2_0_1_.INIT = 16'h69F0; + LUT4_L com_cmm_u_cmm_errman_cplu_cntr_reg_cnt_6_0_i_m2_0_1_ ( + .I0(com_cmm_u_cmm_errman_cplu_cntr_N_26200_i), + .I1(com_cmm_u_cmm_errman_cplu_add_sub_b), + .I2(com_cmm_u_cmm_errman_cplu_cntr_un25_reg_cnt_axb1_i), + .I3(com_cmm_u_cmm_errman_cplu_num[0]), + .LO(com_cmm_u_cmm_errman_cplu_cntr_reg_cnt_6_0_i_m2_0_0[1]) + ); + defparam com_cmm_u_cmm_errman_cplu_cntr_reg_cnt_6_0_i_m2_0_0_.INIT = 4'h6; + LUT2_L com_cmm_u_cmm_errman_cplu_cntr_reg_cnt_6_0_i_m2_0_0_ ( + .I0(com_cmm_u_cmm_errman_cplu_cntr_N_26200_i), + .I1(com_cmm_u_cmm_errman_cplu_num[0]), + .LO(com_cmm_u_cmm_errman_cplu_cntr_reg_cnt_6_0_i_m2_0_0[0]) + ); + FDC com_cmm_u_cmm_errman_cplu_cntr_reg_inc_dec_b ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_cplu_add_sub_b), + .Q(com_cmm_u_cmm_errman_cplu_cntr_reg_inc_dec_b_5998), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_errman_cplu_cntr_reg_extra ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_cplu_cntr_reg_extra_6_0_u_i_m2_0_0), + .Q(com_cmm_u_cmm_errman_cplu_cntr_reg_extra_5999), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_errman_cplu_cntr_reg_uflow ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_cplu_cntr_reg_uflow_3), + .Q(com_cmm_u_cmm_errman_cplu_cntr_reg_uflow_6000), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_errman_cplu_cntr_reg_cnt_3_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_cplu_cntr_reg_cnt_6_0_i_m2_0_0[3]), + .Q(com_cmm_u_cmm_errman_cplu_cntr_reg_cnt[3]), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_errman_cplu_cntr_reg_cnt_2_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_cplu_cntr_reg_cnt_6_0_i_m2_0_0[2]), + .Q(com_cmm_u_cmm_errman_cplu_cntr_reg_cnt[2]), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_errman_cplu_cntr_reg_cnt_1_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_cplu_cntr_reg_cnt_6_0_i_m2_0_0[1]), + .Q(com_cmm_u_cmm_errman_cplu_cntr_reg_cnt[1]), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_errman_cplu_cntr_reg_cnt_0_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_cplu_cntr_reg_cnt_6_0_i_m2_0_0[0]), + .Q(com_cmm_u_cmm_errman_cplu_cntr_reg_cnt[0]), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_errman_cplu_cntr_reg_count_3_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_cplu_cntr_un25_reg_cnt_axb3_i), + .Q(com_cmm_u_cmm_errman_cnt_cplu[3]), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_errman_cplu_cntr_reg_count_2_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_cplu_cntr_un25_reg_cnt_axb2_i), + .Q(com_cmm_u_cmm_errman_cnt_cplu[2]), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_errman_cplu_cntr_reg_count_1_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_cplu_cntr_un25_reg_cnt_axb1_i), + .Q(com_cmm_u_cmm_errman_cnt_cplu[1]), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_errman_cplu_cntr_reg_count_0_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_cplu_cntr_N_26200_i), + .Q(com_cmm_u_cmm_errman_cnt_cplu[0]), + .CLR(com_cmm_rst_351) + ); + VCC com_cmm_u_cmm_errman_cmt_hdr_buf_VCC ( + .P(com_cmm_u_cmm_errman_cmt_hdr_buf_VCC_6001) + ); + GND com_cmm_u_cmm_errman_cmt_hdr_buf_GND ( + .G(com_cmm_u_cmm_errman_cmt_hdr_buf_GND_6002) + ); + RAM16X1D com_cmm_u_cmm_errman_cmt_hdr_buf_lutram_data_I_1 ( + .DPO(com_cmm_u_cmm_errman_cmt_hdr_buf_lutram_data[40]), + .WCLK(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_reg_cmt_wr_hdr[40]), + .A0(com_cmm_u_cmm_errman_reg_cmt_wp[0]), + .A1(com_cmm_u_cmm_errman_reg_cmt_wp[1]), + .A2(com_cmm_u_cmm_errman_cmt_hdr_buf_GND_6002), + .A3(com_cmm_u_cmm_errman_cmt_hdr_buf_GND_6002), + .DPRA0(com_cmm_u_cmm_errman_reg_cmt_rp[0]), + .DPRA1(com_cmm_u_cmm_errman_reg_cmt_rp[1]), + .DPRA2(com_cmm_u_cmm_errman_cmt_hdr_buf_GND_6002), + .DPRA3(com_cmm_u_cmm_errman_cmt_hdr_buf_GND_6002), + .SPO(NLW_com_cmm_u_cmm_errman_cmt_hdr_buf_lutram_data_I_1_SPO_UNCONNECTED), + .WE(com_cmm_u_cmm_errman_reg_cmt_wr_hdr[48]) + ); + RAM16X1D com_cmm_u_cmm_errman_cmt_hdr_buf_lutram_data_I_2 ( + .DPO(com_cmm_u_cmm_errman_cmt_hdr_buf_lutram_data[27]), + .WCLK(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_reg_cmt_wr_hdr[27]), + .A0(com_cmm_u_cmm_errman_reg_cmt_wp[0]), + .A1(com_cmm_u_cmm_errman_reg_cmt_wp[1]), + .A2(com_cmm_u_cmm_errman_cmt_hdr_buf_GND_6002), + .A3(com_cmm_u_cmm_errman_cmt_hdr_buf_GND_6002), + .DPRA0(com_cmm_u_cmm_errman_reg_cmt_rp[0]), + .DPRA1(com_cmm_u_cmm_errman_reg_cmt_rp[1]), + .DPRA2(com_cmm_u_cmm_errman_cmt_hdr_buf_GND_6002), + .DPRA3(com_cmm_u_cmm_errman_cmt_hdr_buf_GND_6002), + .SPO(NLW_com_cmm_u_cmm_errman_cmt_hdr_buf_lutram_data_I_2_SPO_UNCONNECTED), + .WE(com_cmm_u_cmm_errman_reg_cmt_wr_hdr[48]) + ); + RAM16X1D com_cmm_u_cmm_errman_cmt_hdr_buf_lutram_data_I_3 ( + .DPO(com_cmm_u_cmm_errman_cmt_hdr_buf_lutram_data[1]), + .WCLK(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_reg_cmt_wr_hdr[1]), + .A0(com_cmm_u_cmm_errman_reg_cmt_wp[0]), + .A1(com_cmm_u_cmm_errman_reg_cmt_wp[1]), + .A2(com_cmm_u_cmm_errman_cmt_hdr_buf_GND_6002), + .A3(com_cmm_u_cmm_errman_cmt_hdr_buf_GND_6002), + .DPRA0(com_cmm_u_cmm_errman_reg_cmt_rp[0]), + .DPRA1(com_cmm_u_cmm_errman_reg_cmt_rp[1]), + .DPRA2(com_cmm_u_cmm_errman_cmt_hdr_buf_GND_6002), + .DPRA3(com_cmm_u_cmm_errman_cmt_hdr_buf_GND_6002), + .SPO(NLW_com_cmm_u_cmm_errman_cmt_hdr_buf_lutram_data_I_3_SPO_UNCONNECTED), + .WE(com_cmm_u_cmm_errman_reg_cmt_wr_hdr[48]) + ); + RAM16X1D com_cmm_u_cmm_errman_cmt_hdr_buf_lutram_data_I_4 ( + .DPO(com_cmm_u_cmm_errman_cmt_hdr_buf_lutram_data[5]), + .WCLK(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_reg_cmt_wr_hdr[5]), + .A0(com_cmm_u_cmm_errman_reg_cmt_wp[0]), + .A1(com_cmm_u_cmm_errman_reg_cmt_wp[1]), + .A2(com_cmm_u_cmm_errman_cmt_hdr_buf_GND_6002), + .A3(com_cmm_u_cmm_errman_cmt_hdr_buf_GND_6002), + .DPRA0(com_cmm_u_cmm_errman_reg_cmt_rp[0]), + .DPRA1(com_cmm_u_cmm_errman_reg_cmt_rp[1]), + .DPRA2(com_cmm_u_cmm_errman_cmt_hdr_buf_GND_6002), + .DPRA3(com_cmm_u_cmm_errman_cmt_hdr_buf_GND_6002), + .SPO(NLW_com_cmm_u_cmm_errman_cmt_hdr_buf_lutram_data_I_4_SPO_UNCONNECTED), + .WE(com_cmm_u_cmm_errman_reg_cmt_wr_hdr[48]) + ); + RAM16X1D com_cmm_u_cmm_errman_cmt_hdr_buf_lutram_data_I_5 ( + .DPO(com_cmm_u_cmm_errman_cmt_hdr_buf_lutram_data[30]), + .WCLK(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_reg_cmt_wr_hdr[30]), + .A0(com_cmm_u_cmm_errman_reg_cmt_wp[0]), + .A1(com_cmm_u_cmm_errman_reg_cmt_wp[1]), + .A2(com_cmm_u_cmm_errman_cmt_hdr_buf_GND_6002), + .A3(com_cmm_u_cmm_errman_cmt_hdr_buf_GND_6002), + .DPRA0(com_cmm_u_cmm_errman_reg_cmt_rp[0]), + .DPRA1(com_cmm_u_cmm_errman_reg_cmt_rp[1]), + .DPRA2(com_cmm_u_cmm_errman_cmt_hdr_buf_GND_6002), + .DPRA3(com_cmm_u_cmm_errman_cmt_hdr_buf_GND_6002), + .SPO(NLW_com_cmm_u_cmm_errman_cmt_hdr_buf_lutram_data_I_5_SPO_UNCONNECTED), + .WE(com_cmm_u_cmm_errman_reg_cmt_wr_hdr[48]) + ); + RAM16X1D com_cmm_u_cmm_errman_cmt_hdr_buf_lutram_data_I_6 ( + .DPO(com_cmm_u_cmm_errman_cmt_hdr_buf_lutram_data[43]), + .WCLK(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_reg_cmt_wr_hdr[43]), + .A0(com_cmm_u_cmm_errman_reg_cmt_wp[0]), + .A1(com_cmm_u_cmm_errman_reg_cmt_wp[1]), + .A2(com_cmm_u_cmm_errman_cmt_hdr_buf_GND_6002), + .A3(com_cmm_u_cmm_errman_cmt_hdr_buf_GND_6002), + .DPRA0(com_cmm_u_cmm_errman_reg_cmt_rp[0]), + .DPRA1(com_cmm_u_cmm_errman_reg_cmt_rp[1]), + .DPRA2(com_cmm_u_cmm_errman_cmt_hdr_buf_GND_6002), + .DPRA3(com_cmm_u_cmm_errman_cmt_hdr_buf_GND_6002), + .SPO(NLW_com_cmm_u_cmm_errman_cmt_hdr_buf_lutram_data_I_6_SPO_UNCONNECTED), + .WE(com_cmm_u_cmm_errman_reg_cmt_wr_hdr[48]) + ); + RAM16X1D com_cmm_u_cmm_errman_cmt_hdr_buf_lutram_data_I_7 ( + .DPO(com_cmm_u_cmm_errman_cmt_hdr_buf_lutram_data[16]), + .WCLK(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_reg_cmt_wr_hdr[16]), + .A0(com_cmm_u_cmm_errman_reg_cmt_wp[0]), + .A1(com_cmm_u_cmm_errman_reg_cmt_wp[1]), + .A2(com_cmm_u_cmm_errman_cmt_hdr_buf_GND_6002), + .A3(com_cmm_u_cmm_errman_cmt_hdr_buf_GND_6002), + .DPRA0(com_cmm_u_cmm_errman_reg_cmt_rp[0]), + .DPRA1(com_cmm_u_cmm_errman_reg_cmt_rp[1]), + .DPRA2(com_cmm_u_cmm_errman_cmt_hdr_buf_GND_6002), + .DPRA3(com_cmm_u_cmm_errman_cmt_hdr_buf_GND_6002), + .SPO(NLW_com_cmm_u_cmm_errman_cmt_hdr_buf_lutram_data_I_7_SPO_UNCONNECTED), + .WE(com_cmm_u_cmm_errman_reg_cmt_wr_hdr[48]) + ); + RAM16X1D com_cmm_u_cmm_errman_cmt_hdr_buf_lutram_data_I_8 ( + .DPO(com_cmm_u_cmm_errman_cmt_hdr_buf_lutram_data[29]), + .WCLK(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_reg_cmt_wr_hdr[29]), + .A0(com_cmm_u_cmm_errman_reg_cmt_wp[0]), + .A1(com_cmm_u_cmm_errman_reg_cmt_wp[1]), + .A2(com_cmm_u_cmm_errman_cmt_hdr_buf_GND_6002), + .A3(com_cmm_u_cmm_errman_cmt_hdr_buf_GND_6002), + .DPRA0(com_cmm_u_cmm_errman_reg_cmt_rp[0]), + .DPRA1(com_cmm_u_cmm_errman_reg_cmt_rp[1]), + .DPRA2(com_cmm_u_cmm_errman_cmt_hdr_buf_GND_6002), + .DPRA3(com_cmm_u_cmm_errman_cmt_hdr_buf_GND_6002), + .SPO(NLW_com_cmm_u_cmm_errman_cmt_hdr_buf_lutram_data_I_8_SPO_UNCONNECTED), + .WE(com_cmm_u_cmm_errman_reg_cmt_wr_hdr[48]) + ); + RAM16X1D com_cmm_u_cmm_errman_cmt_hdr_buf_lutram_data_I_9 ( + .DPO(com_cmm_u_cmm_errman_cmt_hdr_buf_lutram_data[42]), + .WCLK(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_reg_cmt_wr_hdr[42]), + .A0(com_cmm_u_cmm_errman_reg_cmt_wp[0]), + .A1(com_cmm_u_cmm_errman_reg_cmt_wp[1]), + .A2(com_cmm_u_cmm_errman_cmt_hdr_buf_GND_6002), + .A3(com_cmm_u_cmm_errman_cmt_hdr_buf_GND_6002), + .DPRA0(com_cmm_u_cmm_errman_reg_cmt_rp[0]), + .DPRA1(com_cmm_u_cmm_errman_reg_cmt_rp[1]), + .DPRA2(com_cmm_u_cmm_errman_cmt_hdr_buf_GND_6002), + .DPRA3(com_cmm_u_cmm_errman_cmt_hdr_buf_GND_6002), + .SPO(NLW_com_cmm_u_cmm_errman_cmt_hdr_buf_lutram_data_I_9_SPO_UNCONNECTED), + .WE(com_cmm_u_cmm_errman_reg_cmt_wr_hdr[48]) + ); + RAM16X1D com_cmm_u_cmm_errman_cmt_hdr_buf_lutram_data_I_10 ( + .DPO(com_cmm_u_cmm_errman_cmt_hdr_buf_lutram_data[15]), + .WCLK(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_reg_cmt_wr_hdr[15]), + .A0(com_cmm_u_cmm_errman_reg_cmt_wp[0]), + .A1(com_cmm_u_cmm_errman_reg_cmt_wp[1]), + .A2(com_cmm_u_cmm_errman_cmt_hdr_buf_GND_6002), + .A3(com_cmm_u_cmm_errman_cmt_hdr_buf_GND_6002), + .DPRA0(com_cmm_u_cmm_errman_reg_cmt_rp[0]), + .DPRA1(com_cmm_u_cmm_errman_reg_cmt_rp[1]), + .DPRA2(com_cmm_u_cmm_errman_cmt_hdr_buf_GND_6002), + .DPRA3(com_cmm_u_cmm_errman_cmt_hdr_buf_GND_6002), + .SPO(NLW_com_cmm_u_cmm_errman_cmt_hdr_buf_lutram_data_I_10_SPO_UNCONNECTED), + .WE(com_cmm_u_cmm_errman_reg_cmt_wr_hdr[48]) + ); + RAM16X1D com_cmm_u_cmm_errman_cmt_hdr_buf_lutram_data_I_11 ( + .DPO(com_cmm_u_cmm_errman_cmt_hdr_buf_lutram_data[18]), + .WCLK(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_reg_cmt_wr_hdr[18]), + .A0(com_cmm_u_cmm_errman_reg_cmt_wp[0]), + .A1(com_cmm_u_cmm_errman_reg_cmt_wp[1]), + .A2(com_cmm_u_cmm_errman_cmt_hdr_buf_GND_6002), + .A3(com_cmm_u_cmm_errman_cmt_hdr_buf_GND_6002), + .DPRA0(com_cmm_u_cmm_errman_reg_cmt_rp[0]), + .DPRA1(com_cmm_u_cmm_errman_reg_cmt_rp[1]), + .DPRA2(com_cmm_u_cmm_errman_cmt_hdr_buf_GND_6002), + .DPRA3(com_cmm_u_cmm_errman_cmt_hdr_buf_GND_6002), + .SPO(NLW_com_cmm_u_cmm_errman_cmt_hdr_buf_lutram_data_I_11_SPO_UNCONNECTED), + .WE(com_cmm_u_cmm_errman_reg_cmt_wr_hdr[48]) + ); + RAM16X1D com_cmm_u_cmm_errman_cmt_hdr_buf_lutram_data_I_12 ( + .DPO(com_cmm_u_cmm_errman_cmt_hdr_buf_lutram_data[32]), + .WCLK(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_reg_cmt_wr_hdr[32]), + .A0(com_cmm_u_cmm_errman_reg_cmt_wp[0]), + .A1(com_cmm_u_cmm_errman_reg_cmt_wp[1]), + .A2(com_cmm_u_cmm_errman_cmt_hdr_buf_GND_6002), + .A3(com_cmm_u_cmm_errman_cmt_hdr_buf_GND_6002), + .DPRA0(com_cmm_u_cmm_errman_reg_cmt_rp[0]), + .DPRA1(com_cmm_u_cmm_errman_reg_cmt_rp[1]), + .DPRA2(com_cmm_u_cmm_errman_cmt_hdr_buf_GND_6002), + .DPRA3(com_cmm_u_cmm_errman_cmt_hdr_buf_GND_6002), + .SPO(NLW_com_cmm_u_cmm_errman_cmt_hdr_buf_lutram_data_I_12_SPO_UNCONNECTED), + .WE(com_cmm_u_cmm_errman_reg_cmt_wr_hdr[48]) + ); + RAM16X1D com_cmm_u_cmm_errman_cmt_hdr_buf_lutram_data_I_13 ( + .DPO(com_cmm_u_cmm_errman_cmt_hdr_buf_lutram_data[45]), + .WCLK(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_reg_cmt_wr_hdr[45]), + .A0(com_cmm_u_cmm_errman_reg_cmt_wp[0]), + .A1(com_cmm_u_cmm_errman_reg_cmt_wp[1]), + .A2(com_cmm_u_cmm_errman_cmt_hdr_buf_GND_6002), + .A3(com_cmm_u_cmm_errman_cmt_hdr_buf_GND_6002), + .DPRA0(com_cmm_u_cmm_errman_reg_cmt_rp[0]), + .DPRA1(com_cmm_u_cmm_errman_reg_cmt_rp[1]), + .DPRA2(com_cmm_u_cmm_errman_cmt_hdr_buf_GND_6002), + .DPRA3(com_cmm_u_cmm_errman_cmt_hdr_buf_GND_6002), + .SPO(NLW_com_cmm_u_cmm_errman_cmt_hdr_buf_lutram_data_I_13_SPO_UNCONNECTED), + .WE(com_cmm_u_cmm_errman_reg_cmt_wr_hdr[48]) + ); + RAM16X1D com_cmm_u_cmm_errman_cmt_hdr_buf_lutram_data_I_14 ( + .DPO(com_cmm_u_cmm_errman_cmt_hdr_buf_lutram_data[28]), + .WCLK(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_reg_cmt_wr_hdr[28]), + .A0(com_cmm_u_cmm_errman_reg_cmt_wp[0]), + .A1(com_cmm_u_cmm_errman_reg_cmt_wp[1]), + .A2(com_cmm_u_cmm_errman_cmt_hdr_buf_GND_6002), + .A3(com_cmm_u_cmm_errman_cmt_hdr_buf_GND_6002), + .DPRA0(com_cmm_u_cmm_errman_reg_cmt_rp[0]), + .DPRA1(com_cmm_u_cmm_errman_reg_cmt_rp[1]), + .DPRA2(com_cmm_u_cmm_errman_cmt_hdr_buf_GND_6002), + .DPRA3(com_cmm_u_cmm_errman_cmt_hdr_buf_GND_6002), + .SPO(NLW_com_cmm_u_cmm_errman_cmt_hdr_buf_lutram_data_I_14_SPO_UNCONNECTED), + .WE(com_cmm_u_cmm_errman_reg_cmt_wr_hdr[48]) + ); + RAM16X1D com_cmm_u_cmm_errman_cmt_hdr_buf_lutram_data_I_15 ( + .DPO(com_cmm_u_cmm_errman_cmt_hdr_buf_lutram_data[0]), + .WCLK(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_reg_cmt_wr_hdr[0]), + .A0(com_cmm_u_cmm_errman_reg_cmt_wp[0]), + .A1(com_cmm_u_cmm_errman_reg_cmt_wp[1]), + .A2(com_cmm_u_cmm_errman_cmt_hdr_buf_GND_6002), + .A3(com_cmm_u_cmm_errman_cmt_hdr_buf_GND_6002), + .DPRA0(com_cmm_u_cmm_errman_reg_cmt_rp[0]), + .DPRA1(com_cmm_u_cmm_errman_reg_cmt_rp[1]), + .DPRA2(com_cmm_u_cmm_errman_cmt_hdr_buf_GND_6002), + .DPRA3(com_cmm_u_cmm_errman_cmt_hdr_buf_GND_6002), + .SPO(NLW_com_cmm_u_cmm_errman_cmt_hdr_buf_lutram_data_I_15_SPO_UNCONNECTED), + .WE(com_cmm_u_cmm_errman_reg_cmt_wr_hdr[48]) + ); + RAM16X1D com_cmm_u_cmm_errman_cmt_hdr_buf_lutram_data_I_16 ( + .DPO(com_cmm_u_cmm_errman_cmt_hdr_buf_lutram_data[4]), + .WCLK(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_reg_cmt_wr_hdr[4]), + .A0(com_cmm_u_cmm_errman_reg_cmt_wp[0]), + .A1(com_cmm_u_cmm_errman_reg_cmt_wp[1]), + .A2(com_cmm_u_cmm_errman_cmt_hdr_buf_GND_6002), + .A3(com_cmm_u_cmm_errman_cmt_hdr_buf_GND_6002), + .DPRA0(com_cmm_u_cmm_errman_reg_cmt_rp[0]), + .DPRA1(com_cmm_u_cmm_errman_reg_cmt_rp[1]), + .DPRA2(com_cmm_u_cmm_errman_cmt_hdr_buf_GND_6002), + .DPRA3(com_cmm_u_cmm_errman_cmt_hdr_buf_GND_6002), + .SPO(NLW_com_cmm_u_cmm_errman_cmt_hdr_buf_lutram_data_I_16_SPO_UNCONNECTED), + .WE(com_cmm_u_cmm_errman_reg_cmt_wr_hdr[48]) + ); + RAM16X1D com_cmm_u_cmm_errman_cmt_hdr_buf_lutram_data_I_17 ( + .DPO(com_cmm_u_cmm_errman_cmt_hdr_buf_lutram_data[8]), + .WCLK(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_reg_cmt_wr_hdr[8]), + .A0(com_cmm_u_cmm_errman_reg_cmt_wp[0]), + .A1(com_cmm_u_cmm_errman_reg_cmt_wp[1]), + .A2(com_cmm_u_cmm_errman_cmt_hdr_buf_GND_6002), + .A3(com_cmm_u_cmm_errman_cmt_hdr_buf_GND_6002), + .DPRA0(com_cmm_u_cmm_errman_reg_cmt_rp[0]), + .DPRA1(com_cmm_u_cmm_errman_reg_cmt_rp[1]), + .DPRA2(com_cmm_u_cmm_errman_cmt_hdr_buf_GND_6002), + .DPRA3(com_cmm_u_cmm_errman_cmt_hdr_buf_GND_6002), + .SPO(NLW_com_cmm_u_cmm_errman_cmt_hdr_buf_lutram_data_I_17_SPO_UNCONNECTED), + .WE(com_cmm_u_cmm_errman_reg_cmt_wr_hdr[48]) + ); + RAM16X1D com_cmm_u_cmm_errman_cmt_hdr_buf_lutram_data_I_18 ( + .DPO(com_cmm_u_cmm_errman_cmt_hdr_buf_lutram_data[2]), + .WCLK(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_reg_cmt_wr_hdr[2]), + .A0(com_cmm_u_cmm_errman_reg_cmt_wp[0]), + .A1(com_cmm_u_cmm_errman_reg_cmt_wp[1]), + .A2(com_cmm_u_cmm_errman_cmt_hdr_buf_GND_6002), + .A3(com_cmm_u_cmm_errman_cmt_hdr_buf_GND_6002), + .DPRA0(com_cmm_u_cmm_errman_reg_cmt_rp[0]), + .DPRA1(com_cmm_u_cmm_errman_reg_cmt_rp[1]), + .DPRA2(com_cmm_u_cmm_errman_cmt_hdr_buf_GND_6002), + .DPRA3(com_cmm_u_cmm_errman_cmt_hdr_buf_GND_6002), + .SPO(NLW_com_cmm_u_cmm_errman_cmt_hdr_buf_lutram_data_I_18_SPO_UNCONNECTED), + .WE(com_cmm_u_cmm_errman_reg_cmt_wr_hdr[48]) + ); + RAM16X1D com_cmm_u_cmm_errman_cmt_hdr_buf_lutram_data_I_19 ( + .DPO(com_cmm_u_cmm_errman_cmt_hdr_buf_lutram_data[3]), + .WCLK(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_reg_cmt_wr_hdr[3]), + .A0(com_cmm_u_cmm_errman_reg_cmt_wp[0]), + .A1(com_cmm_u_cmm_errman_reg_cmt_wp[1]), + .A2(com_cmm_u_cmm_errman_cmt_hdr_buf_GND_6002), + .A3(com_cmm_u_cmm_errman_cmt_hdr_buf_GND_6002), + .DPRA0(com_cmm_u_cmm_errman_reg_cmt_rp[0]), + .DPRA1(com_cmm_u_cmm_errman_reg_cmt_rp[1]), + .DPRA2(com_cmm_u_cmm_errman_cmt_hdr_buf_GND_6002), + .DPRA3(com_cmm_u_cmm_errman_cmt_hdr_buf_GND_6002), + .SPO(NLW_com_cmm_u_cmm_errman_cmt_hdr_buf_lutram_data_I_19_SPO_UNCONNECTED), + .WE(com_cmm_u_cmm_errman_reg_cmt_wr_hdr[48]) + ); + RAM16X1D com_cmm_u_cmm_errman_cmt_hdr_buf_lutram_data_I_20 ( + .DPO(com_cmm_u_cmm_errman_cmt_hdr_buf_lutram_data[7]), + .WCLK(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_reg_cmt_wr_hdr[7]), + .A0(com_cmm_u_cmm_errman_reg_cmt_wp[0]), + .A1(com_cmm_u_cmm_errman_reg_cmt_wp[1]), + .A2(com_cmm_u_cmm_errman_cmt_hdr_buf_GND_6002), + .A3(com_cmm_u_cmm_errman_cmt_hdr_buf_GND_6002), + .DPRA0(com_cmm_u_cmm_errman_reg_cmt_rp[0]), + .DPRA1(com_cmm_u_cmm_errman_reg_cmt_rp[1]), + .DPRA2(com_cmm_u_cmm_errman_cmt_hdr_buf_GND_6002), + .DPRA3(com_cmm_u_cmm_errman_cmt_hdr_buf_GND_6002), + .SPO(NLW_com_cmm_u_cmm_errman_cmt_hdr_buf_lutram_data_I_20_SPO_UNCONNECTED), + .WE(com_cmm_u_cmm_errman_reg_cmt_wr_hdr[48]) + ); + RAM16X1D com_cmm_u_cmm_errman_cmt_hdr_buf_lutram_data_I_21 ( + .DPO(com_cmm_u_cmm_errman_cmt_hdr_buf_lutram_data[20]), + .WCLK(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_reg_cmt_wr_hdr[20]), + .A0(com_cmm_u_cmm_errman_reg_cmt_wp[0]), + .A1(com_cmm_u_cmm_errman_reg_cmt_wp[1]), + .A2(com_cmm_u_cmm_errman_cmt_hdr_buf_GND_6002), + .A3(com_cmm_u_cmm_errman_cmt_hdr_buf_GND_6002), + .DPRA0(com_cmm_u_cmm_errman_reg_cmt_rp[0]), + .DPRA1(com_cmm_u_cmm_errman_reg_cmt_rp[1]), + .DPRA2(com_cmm_u_cmm_errman_cmt_hdr_buf_GND_6002), + .DPRA3(com_cmm_u_cmm_errman_cmt_hdr_buf_GND_6002), + .SPO(NLW_com_cmm_u_cmm_errman_cmt_hdr_buf_lutram_data_I_21_SPO_UNCONNECTED), + .WE(com_cmm_u_cmm_errman_reg_cmt_wr_hdr[48]) + ); + RAM16X1D com_cmm_u_cmm_errman_cmt_hdr_buf_lutram_data_I_22 ( + .DPO(com_cmm_u_cmm_errman_cmt_hdr_buf_lutram_data[33]), + .WCLK(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_reg_cmt_wr_hdr[33]), + .A0(com_cmm_u_cmm_errman_reg_cmt_wp[0]), + .A1(com_cmm_u_cmm_errman_reg_cmt_wp[1]), + .A2(com_cmm_u_cmm_errman_cmt_hdr_buf_GND_6002), + .A3(com_cmm_u_cmm_errman_cmt_hdr_buf_GND_6002), + .DPRA0(com_cmm_u_cmm_errman_reg_cmt_rp[0]), + .DPRA1(com_cmm_u_cmm_errman_reg_cmt_rp[1]), + .DPRA2(com_cmm_u_cmm_errman_cmt_hdr_buf_GND_6002), + .DPRA3(com_cmm_u_cmm_errman_cmt_hdr_buf_GND_6002), + .SPO(NLW_com_cmm_u_cmm_errman_cmt_hdr_buf_lutram_data_I_22_SPO_UNCONNECTED), + .WE(com_cmm_u_cmm_errman_reg_cmt_wr_hdr[48]) + ); + RAM16X1D com_cmm_u_cmm_errman_cmt_hdr_buf_lutram_data_I_23 ( + .DPO(com_cmm_u_cmm_errman_cmt_hdr_buf_lutram_data[46]), + .WCLK(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_reg_cmt_wr_hdr[46]), + .A0(com_cmm_u_cmm_errman_reg_cmt_wp[0]), + .A1(com_cmm_u_cmm_errman_reg_cmt_wp[1]), + .A2(com_cmm_u_cmm_errman_cmt_hdr_buf_GND_6002), + .A3(com_cmm_u_cmm_errman_cmt_hdr_buf_GND_6002), + .DPRA0(com_cmm_u_cmm_errman_reg_cmt_rp[0]), + .DPRA1(com_cmm_u_cmm_errman_reg_cmt_rp[1]), + .DPRA2(com_cmm_u_cmm_errman_cmt_hdr_buf_GND_6002), + .DPRA3(com_cmm_u_cmm_errman_cmt_hdr_buf_GND_6002), + .SPO(NLW_com_cmm_u_cmm_errman_cmt_hdr_buf_lutram_data_I_23_SPO_UNCONNECTED), + .WE(com_cmm_u_cmm_errman_reg_cmt_wr_hdr[48]) + ); + RAM16X1D com_cmm_u_cmm_errman_cmt_hdr_buf_lutram_data_I_24 ( + .DPO(com_cmm_u_cmm_errman_cmt_hdr_buf_lutram_data[9]), + .WCLK(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_reg_cmt_wr_hdr[9]), + .A0(com_cmm_u_cmm_errman_reg_cmt_wp[0]), + .A1(com_cmm_u_cmm_errman_reg_cmt_wp[1]), + .A2(com_cmm_u_cmm_errman_cmt_hdr_buf_GND_6002), + .A3(com_cmm_u_cmm_errman_cmt_hdr_buf_GND_6002), + .DPRA0(com_cmm_u_cmm_errman_reg_cmt_rp[0]), + .DPRA1(com_cmm_u_cmm_errman_reg_cmt_rp[1]), + .DPRA2(com_cmm_u_cmm_errman_cmt_hdr_buf_GND_6002), + .DPRA3(com_cmm_u_cmm_errman_cmt_hdr_buf_GND_6002), + .SPO(NLW_com_cmm_u_cmm_errman_cmt_hdr_buf_lutram_data_I_24_SPO_UNCONNECTED), + .WE(com_cmm_u_cmm_errman_reg_cmt_wr_hdr[48]) + ); + RAM16X1D com_cmm_u_cmm_errman_cmt_hdr_buf_lutram_data_I_25 ( + .DPO(com_cmm_u_cmm_errman_cmt_hdr_buf_lutram_data[41]), + .WCLK(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_reg_cmt_wr_hdr[41]), + .A0(com_cmm_u_cmm_errman_reg_cmt_wp[0]), + .A1(com_cmm_u_cmm_errman_reg_cmt_wp[1]), + .A2(com_cmm_u_cmm_errman_cmt_hdr_buf_GND_6002), + .A3(com_cmm_u_cmm_errman_cmt_hdr_buf_GND_6002), + .DPRA0(com_cmm_u_cmm_errman_reg_cmt_rp[0]), + .DPRA1(com_cmm_u_cmm_errman_reg_cmt_rp[1]), + .DPRA2(com_cmm_u_cmm_errman_cmt_hdr_buf_GND_6002), + .DPRA3(com_cmm_u_cmm_errman_cmt_hdr_buf_GND_6002), + .SPO(NLW_com_cmm_u_cmm_errman_cmt_hdr_buf_lutram_data_I_25_SPO_UNCONNECTED), + .WE(com_cmm_u_cmm_errman_reg_cmt_wr_hdr[48]) + ); + RAM16X1D com_cmm_u_cmm_errman_cmt_hdr_buf_lutram_data_I_26 ( + .DPO(com_cmm_u_cmm_errman_cmt_hdr_buf_lutram_data[14]), + .WCLK(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_reg_cmt_wr_hdr[14]), + .A0(com_cmm_u_cmm_errman_reg_cmt_wp[0]), + .A1(com_cmm_u_cmm_errman_reg_cmt_wp[1]), + .A2(com_cmm_u_cmm_errman_cmt_hdr_buf_GND_6002), + .A3(com_cmm_u_cmm_errman_cmt_hdr_buf_GND_6002), + .DPRA0(com_cmm_u_cmm_errman_reg_cmt_rp[0]), + .DPRA1(com_cmm_u_cmm_errman_reg_cmt_rp[1]), + .DPRA2(com_cmm_u_cmm_errman_cmt_hdr_buf_GND_6002), + .DPRA3(com_cmm_u_cmm_errman_cmt_hdr_buf_GND_6002), + .SPO(NLW_com_cmm_u_cmm_errman_cmt_hdr_buf_lutram_data_I_26_SPO_UNCONNECTED), + .WE(com_cmm_u_cmm_errman_reg_cmt_wr_hdr[48]) + ); + RAM16X1D com_cmm_u_cmm_errman_cmt_hdr_buf_lutram_data_I_27 ( + .DPO(com_cmm_u_cmm_errman_cmt_hdr_buf_lutram_data[19]), + .WCLK(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_reg_cmt_wr_hdr[19]), + .A0(com_cmm_u_cmm_errman_reg_cmt_wp[0]), + .A1(com_cmm_u_cmm_errman_reg_cmt_wp[1]), + .A2(com_cmm_u_cmm_errman_cmt_hdr_buf_GND_6002), + .A3(com_cmm_u_cmm_errman_cmt_hdr_buf_GND_6002), + .DPRA0(com_cmm_u_cmm_errman_reg_cmt_rp[0]), + .DPRA1(com_cmm_u_cmm_errman_reg_cmt_rp[1]), + .DPRA2(com_cmm_u_cmm_errman_cmt_hdr_buf_GND_6002), + .DPRA3(com_cmm_u_cmm_errman_cmt_hdr_buf_GND_6002), + .SPO(NLW_com_cmm_u_cmm_errman_cmt_hdr_buf_lutram_data_I_27_SPO_UNCONNECTED), + .WE(com_cmm_u_cmm_errman_reg_cmt_wr_hdr[48]) + ); + RAM16X1D com_cmm_u_cmm_errman_cmt_hdr_buf_lutram_data_I_28 ( + .DPO(com_cmm_u_cmm_errman_cmt_hdr_buf_lutram_data[6]), + .WCLK(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_reg_cmt_wr_hdr[6]), + .A0(com_cmm_u_cmm_errman_reg_cmt_wp[0]), + .A1(com_cmm_u_cmm_errman_reg_cmt_wp[1]), + .A2(com_cmm_u_cmm_errman_cmt_hdr_buf_GND_6002), + .A3(com_cmm_u_cmm_errman_cmt_hdr_buf_GND_6002), + .DPRA0(com_cmm_u_cmm_errman_reg_cmt_rp[0]), + .DPRA1(com_cmm_u_cmm_errman_reg_cmt_rp[1]), + .DPRA2(com_cmm_u_cmm_errman_cmt_hdr_buf_GND_6002), + .DPRA3(com_cmm_u_cmm_errman_cmt_hdr_buf_GND_6002), + .SPO(NLW_com_cmm_u_cmm_errman_cmt_hdr_buf_lutram_data_I_28_SPO_UNCONNECTED), + .WE(com_cmm_u_cmm_errman_reg_cmt_wr_hdr[48]) + ); + RAM16X1D com_cmm_u_cmm_errman_cmt_hdr_buf_lutram_data_I_29 ( + .DPO(com_cmm_u_cmm_errman_cmt_hdr_buf_lutram_data[11]), + .WCLK(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_reg_cmt_wr_hdr[11]), + .A0(com_cmm_u_cmm_errman_reg_cmt_wp[0]), + .A1(com_cmm_u_cmm_errman_reg_cmt_wp[1]), + .A2(com_cmm_u_cmm_errman_cmt_hdr_buf_GND_6002), + .A3(com_cmm_u_cmm_errman_cmt_hdr_buf_GND_6002), + .DPRA0(com_cmm_u_cmm_errman_reg_cmt_rp[0]), + .DPRA1(com_cmm_u_cmm_errman_reg_cmt_rp[1]), + .DPRA2(com_cmm_u_cmm_errman_cmt_hdr_buf_GND_6002), + .DPRA3(com_cmm_u_cmm_errman_cmt_hdr_buf_GND_6002), + .SPO(NLW_com_cmm_u_cmm_errman_cmt_hdr_buf_lutram_data_I_29_SPO_UNCONNECTED), + .WE(com_cmm_u_cmm_errman_reg_cmt_wr_hdr[48]) + ); + RAM16X1D com_cmm_u_cmm_errman_cmt_hdr_buf_lutram_data_I_30 ( + .DPO(com_cmm_u_cmm_errman_cmt_hdr_buf_lutram_data[24]), + .WCLK(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_reg_cmt_wr_hdr[24]), + .A0(com_cmm_u_cmm_errman_reg_cmt_wp[0]), + .A1(com_cmm_u_cmm_errman_reg_cmt_wp[1]), + .A2(com_cmm_u_cmm_errman_cmt_hdr_buf_GND_6002), + .A3(com_cmm_u_cmm_errman_cmt_hdr_buf_GND_6002), + .DPRA0(com_cmm_u_cmm_errman_reg_cmt_rp[0]), + .DPRA1(com_cmm_u_cmm_errman_reg_cmt_rp[1]), + .DPRA2(com_cmm_u_cmm_errman_cmt_hdr_buf_GND_6002), + .DPRA3(com_cmm_u_cmm_errman_cmt_hdr_buf_GND_6002), + .SPO(NLW_com_cmm_u_cmm_errman_cmt_hdr_buf_lutram_data_I_30_SPO_UNCONNECTED), + .WE(com_cmm_u_cmm_errman_reg_cmt_wr_hdr[48]) + ); + RAM16X1D com_cmm_u_cmm_errman_cmt_hdr_buf_lutram_data_I_31 ( + .DPO(com_cmm_u_cmm_errman_cmt_hdr_buf_lutram_data[39]), + .WCLK(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_reg_cmt_wr_hdr[39]), + .A0(com_cmm_u_cmm_errman_reg_cmt_wp[0]), + .A1(com_cmm_u_cmm_errman_reg_cmt_wp[1]), + .A2(com_cmm_u_cmm_errman_cmt_hdr_buf_GND_6002), + .A3(com_cmm_u_cmm_errman_cmt_hdr_buf_GND_6002), + .DPRA0(com_cmm_u_cmm_errman_reg_cmt_rp[0]), + .DPRA1(com_cmm_u_cmm_errman_reg_cmt_rp[1]), + .DPRA2(com_cmm_u_cmm_errman_cmt_hdr_buf_GND_6002), + .DPRA3(com_cmm_u_cmm_errman_cmt_hdr_buf_GND_6002), + .SPO(NLW_com_cmm_u_cmm_errman_cmt_hdr_buf_lutram_data_I_31_SPO_UNCONNECTED), + .WE(com_cmm_u_cmm_errman_reg_cmt_wr_hdr[48]) + ); + RAM16X1D com_cmm_u_cmm_errman_cmt_hdr_buf_lutram_data_I_32 ( + .DPO(com_cmm_u_cmm_errman_cmt_hdr_buf_lutram_data[12]), + .WCLK(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_reg_cmt_wr_hdr[12]), + .A0(com_cmm_u_cmm_errman_reg_cmt_wp[0]), + .A1(com_cmm_u_cmm_errman_reg_cmt_wp[1]), + .A2(com_cmm_u_cmm_errman_cmt_hdr_buf_GND_6002), + .A3(com_cmm_u_cmm_errman_cmt_hdr_buf_GND_6002), + .DPRA0(com_cmm_u_cmm_errman_reg_cmt_rp[0]), + .DPRA1(com_cmm_u_cmm_errman_reg_cmt_rp[1]), + .DPRA2(com_cmm_u_cmm_errman_cmt_hdr_buf_GND_6002), + .DPRA3(com_cmm_u_cmm_errman_cmt_hdr_buf_GND_6002), + .SPO(NLW_com_cmm_u_cmm_errman_cmt_hdr_buf_lutram_data_I_32_SPO_UNCONNECTED), + .WE(com_cmm_u_cmm_errman_reg_cmt_wr_hdr[48]) + ); + RAM16X1D com_cmm_u_cmm_errman_cmt_hdr_buf_lutram_data_I_33 ( + .DPO(com_cmm_u_cmm_errman_cmt_hdr_buf_lutram_data[25]), + .WCLK(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_reg_cmt_wr_hdr[25]), + .A0(com_cmm_u_cmm_errman_reg_cmt_wp[0]), + .A1(com_cmm_u_cmm_errman_reg_cmt_wp[1]), + .A2(com_cmm_u_cmm_errman_cmt_hdr_buf_GND_6002), + .A3(com_cmm_u_cmm_errman_cmt_hdr_buf_GND_6002), + .DPRA0(com_cmm_u_cmm_errman_reg_cmt_rp[0]), + .DPRA1(com_cmm_u_cmm_errman_reg_cmt_rp[1]), + .DPRA2(com_cmm_u_cmm_errman_cmt_hdr_buf_GND_6002), + .DPRA3(com_cmm_u_cmm_errman_cmt_hdr_buf_GND_6002), + .SPO(NLW_com_cmm_u_cmm_errman_cmt_hdr_buf_lutram_data_I_33_SPO_UNCONNECTED), + .WE(com_cmm_u_cmm_errman_reg_cmt_wr_hdr[48]) + ); + RAM16X1D com_cmm_u_cmm_errman_cmt_hdr_buf_lutram_data_I_34 ( + .DPO(com_cmm_u_cmm_errman_cmt_hdr_buf_lutram_data[38]), + .WCLK(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_reg_cmt_wr_hdr[38]), + .A0(com_cmm_u_cmm_errman_reg_cmt_wp[0]), + .A1(com_cmm_u_cmm_errman_reg_cmt_wp[1]), + .A2(com_cmm_u_cmm_errman_cmt_hdr_buf_GND_6002), + .A3(com_cmm_u_cmm_errman_cmt_hdr_buf_GND_6002), + .DPRA0(com_cmm_u_cmm_errman_reg_cmt_rp[0]), + .DPRA1(com_cmm_u_cmm_errman_reg_cmt_rp[1]), + .DPRA2(com_cmm_u_cmm_errman_cmt_hdr_buf_GND_6002), + .DPRA3(com_cmm_u_cmm_errman_cmt_hdr_buf_GND_6002), + .SPO(NLW_com_cmm_u_cmm_errman_cmt_hdr_buf_lutram_data_I_34_SPO_UNCONNECTED), + .WE(com_cmm_u_cmm_errman_reg_cmt_wr_hdr[48]) + ); + RAM16X1D com_cmm_u_cmm_errman_cmt_hdr_buf_lutram_data_I_35 ( + .DPO(com_cmm_u_cmm_errman_cmt_hdr_buf_lutram_data[13]), + .WCLK(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_reg_cmt_wr_hdr[13]), + .A0(com_cmm_u_cmm_errman_reg_cmt_wp[0]), + .A1(com_cmm_u_cmm_errman_reg_cmt_wp[1]), + .A2(com_cmm_u_cmm_errman_cmt_hdr_buf_GND_6002), + .A3(com_cmm_u_cmm_errman_cmt_hdr_buf_GND_6002), + .DPRA0(com_cmm_u_cmm_errman_reg_cmt_rp[0]), + .DPRA1(com_cmm_u_cmm_errman_reg_cmt_rp[1]), + .DPRA2(com_cmm_u_cmm_errman_cmt_hdr_buf_GND_6002), + .DPRA3(com_cmm_u_cmm_errman_cmt_hdr_buf_GND_6002), + .SPO(NLW_com_cmm_u_cmm_errman_cmt_hdr_buf_lutram_data_I_35_SPO_UNCONNECTED), + .WE(com_cmm_u_cmm_errman_reg_cmt_wr_hdr[48]) + ); + RAM16X1D com_cmm_u_cmm_errman_cmt_hdr_buf_lutram_data_I_36 ( + .DPO(com_cmm_u_cmm_errman_cmt_hdr_buf_lutram_data[26]), + .WCLK(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_reg_cmt_wr_hdr[26]), + .A0(com_cmm_u_cmm_errman_reg_cmt_wp[0]), + .A1(com_cmm_u_cmm_errman_reg_cmt_wp[1]), + .A2(com_cmm_u_cmm_errman_cmt_hdr_buf_GND_6002), + .A3(com_cmm_u_cmm_errman_cmt_hdr_buf_GND_6002), + .DPRA0(com_cmm_u_cmm_errman_reg_cmt_rp[0]), + .DPRA1(com_cmm_u_cmm_errman_reg_cmt_rp[1]), + .DPRA2(com_cmm_u_cmm_errman_cmt_hdr_buf_GND_6002), + .DPRA3(com_cmm_u_cmm_errman_cmt_hdr_buf_GND_6002), + .SPO(NLW_com_cmm_u_cmm_errman_cmt_hdr_buf_lutram_data_I_36_SPO_UNCONNECTED), + .WE(com_cmm_u_cmm_errman_reg_cmt_wr_hdr[48]) + ); + RAM16X1D com_cmm_u_cmm_errman_cmt_hdr_buf_lutram_data_I_37 ( + .DPO(com_cmm_u_cmm_errman_cmt_hdr_buf_lutram_data[22]), + .WCLK(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_reg_cmt_wr_hdr[22]), + .A0(com_cmm_u_cmm_errman_reg_cmt_wp[0]), + .A1(com_cmm_u_cmm_errman_reg_cmt_wp[1]), + .A2(com_cmm_u_cmm_errman_cmt_hdr_buf_GND_6002), + .A3(com_cmm_u_cmm_errman_cmt_hdr_buf_GND_6002), + .DPRA0(com_cmm_u_cmm_errman_reg_cmt_rp[0]), + .DPRA1(com_cmm_u_cmm_errman_reg_cmt_rp[1]), + .DPRA2(com_cmm_u_cmm_errman_cmt_hdr_buf_GND_6002), + .DPRA3(com_cmm_u_cmm_errman_cmt_hdr_buf_GND_6002), + .SPO(NLW_com_cmm_u_cmm_errman_cmt_hdr_buf_lutram_data_I_37_SPO_UNCONNECTED), + .WE(com_cmm_u_cmm_errman_reg_cmt_wr_hdr[48]) + ); + RAM16X1D com_cmm_u_cmm_errman_cmt_hdr_buf_lutram_data_I_38 ( + .DPO(com_cmm_u_cmm_errman_cmt_hdr_buf_lutram_data[49]), + .WCLK(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_cmt_hdr_buf_GND_6002), + .A0(com_cmm_u_cmm_errman_reg_cmt_wp[0]), + .A1(com_cmm_u_cmm_errman_reg_cmt_wp[1]), + .A2(com_cmm_u_cmm_errman_cmt_hdr_buf_GND_6002), + .A3(com_cmm_u_cmm_errman_cmt_hdr_buf_GND_6002), + .DPRA0(com_cmm_u_cmm_errman_reg_cmt_rp[0]), + .DPRA1(com_cmm_u_cmm_errman_reg_cmt_rp[1]), + .DPRA2(com_cmm_u_cmm_errman_cmt_hdr_buf_GND_6002), + .DPRA3(com_cmm_u_cmm_errman_cmt_hdr_buf_GND_6002), + .SPO(NLW_com_cmm_u_cmm_errman_cmt_hdr_buf_lutram_data_I_38_SPO_UNCONNECTED), + .WE(com_cmm_u_cmm_errman_reg_cmt_wr_hdr[48]) + ); + RAM16X1D com_cmm_u_cmm_errman_cmt_hdr_buf_lutram_data_I_39 ( + .DPO(com_cmm_u_cmm_errman_cmt_hdr_buf_lutram_data[23]), + .WCLK(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_reg_cmt_wr_hdr[23]), + .A0(com_cmm_u_cmm_errman_reg_cmt_wp[0]), + .A1(com_cmm_u_cmm_errman_reg_cmt_wp[1]), + .A2(com_cmm_u_cmm_errman_cmt_hdr_buf_GND_6002), + .A3(com_cmm_u_cmm_errman_cmt_hdr_buf_GND_6002), + .DPRA0(com_cmm_u_cmm_errman_reg_cmt_rp[0]), + .DPRA1(com_cmm_u_cmm_errman_reg_cmt_rp[1]), + .DPRA2(com_cmm_u_cmm_errman_cmt_hdr_buf_GND_6002), + .DPRA3(com_cmm_u_cmm_errman_cmt_hdr_buf_GND_6002), + .SPO(NLW_com_cmm_u_cmm_errman_cmt_hdr_buf_lutram_data_I_39_SPO_UNCONNECTED), + .WE(com_cmm_u_cmm_errman_reg_cmt_wr_hdr[48]) + ); + RAM16X1D com_cmm_u_cmm_errman_cmt_hdr_buf_lutram_data_I_40 ( + .DPO(com_cmm_u_cmm_errman_cmt_hdr_buf_lutram_data[36]), + .WCLK(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_reg_cmt_wr_hdr[36]), + .A0(com_cmm_u_cmm_errman_reg_cmt_wp[0]), + .A1(com_cmm_u_cmm_errman_reg_cmt_wp[1]), + .A2(com_cmm_u_cmm_errman_cmt_hdr_buf_GND_6002), + .A3(com_cmm_u_cmm_errman_cmt_hdr_buf_GND_6002), + .DPRA0(com_cmm_u_cmm_errman_reg_cmt_rp[0]), + .DPRA1(com_cmm_u_cmm_errman_reg_cmt_rp[1]), + .DPRA2(com_cmm_u_cmm_errman_cmt_hdr_buf_GND_6002), + .DPRA3(com_cmm_u_cmm_errman_cmt_hdr_buf_GND_6002), + .SPO(NLW_com_cmm_u_cmm_errman_cmt_hdr_buf_lutram_data_I_40_SPO_UNCONNECTED), + .WE(com_cmm_u_cmm_errman_reg_cmt_wr_hdr[48]) + ); + RAM16X1D com_cmm_u_cmm_errman_cmt_hdr_buf_lutram_data_I_41 ( + .DPO(com_cmm_u_cmm_errman_cmt_hdr_buf_lutram_data[10]), + .WCLK(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_reg_cmt_wr_hdr[10]), + .A0(com_cmm_u_cmm_errman_reg_cmt_wp[0]), + .A1(com_cmm_u_cmm_errman_reg_cmt_wp[1]), + .A2(com_cmm_u_cmm_errman_cmt_hdr_buf_GND_6002), + .A3(com_cmm_u_cmm_errman_cmt_hdr_buf_GND_6002), + .DPRA0(com_cmm_u_cmm_errman_reg_cmt_rp[0]), + .DPRA1(com_cmm_u_cmm_errman_reg_cmt_rp[1]), + .DPRA2(com_cmm_u_cmm_errman_cmt_hdr_buf_GND_6002), + .DPRA3(com_cmm_u_cmm_errman_cmt_hdr_buf_GND_6002), + .SPO(NLW_com_cmm_u_cmm_errman_cmt_hdr_buf_lutram_data_I_41_SPO_UNCONNECTED), + .WE(com_cmm_u_cmm_errman_reg_cmt_wr_hdr[48]) + ); + RAM16X1D com_cmm_u_cmm_errman_cmt_hdr_buf_lutram_data_I_42 ( + .DPO(com_cmm_u_cmm_errman_cmt_hdr_buf_lutram_data[31]), + .WCLK(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_reg_cmt_wr_hdr[31]), + .A0(com_cmm_u_cmm_errman_reg_cmt_wp[0]), + .A1(com_cmm_u_cmm_errman_reg_cmt_wp[1]), + .A2(com_cmm_u_cmm_errman_cmt_hdr_buf_GND_6002), + .A3(com_cmm_u_cmm_errman_cmt_hdr_buf_GND_6002), + .DPRA0(com_cmm_u_cmm_errman_reg_cmt_rp[0]), + .DPRA1(com_cmm_u_cmm_errman_reg_cmt_rp[1]), + .DPRA2(com_cmm_u_cmm_errman_cmt_hdr_buf_GND_6002), + .DPRA3(com_cmm_u_cmm_errman_cmt_hdr_buf_GND_6002), + .SPO(NLW_com_cmm_u_cmm_errman_cmt_hdr_buf_lutram_data_I_42_SPO_UNCONNECTED), + .WE(com_cmm_u_cmm_errman_reg_cmt_wr_hdr[48]) + ); + RAM16X1D com_cmm_u_cmm_errman_cmt_hdr_buf_lutram_data_I_43 ( + .DPO(com_cmm_u_cmm_errman_cmt_hdr_buf_lutram_data[44]), + .WCLK(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_reg_cmt_wr_hdr[44]), + .A0(com_cmm_u_cmm_errman_reg_cmt_wp[0]), + .A1(com_cmm_u_cmm_errman_reg_cmt_wp[1]), + .A2(com_cmm_u_cmm_errman_cmt_hdr_buf_GND_6002), + .A3(com_cmm_u_cmm_errman_cmt_hdr_buf_GND_6002), + .DPRA0(com_cmm_u_cmm_errman_reg_cmt_rp[0]), + .DPRA1(com_cmm_u_cmm_errman_reg_cmt_rp[1]), + .DPRA2(com_cmm_u_cmm_errman_cmt_hdr_buf_GND_6002), + .DPRA3(com_cmm_u_cmm_errman_cmt_hdr_buf_GND_6002), + .SPO(NLW_com_cmm_u_cmm_errman_cmt_hdr_buf_lutram_data_I_43_SPO_UNCONNECTED), + .WE(com_cmm_u_cmm_errman_reg_cmt_wr_hdr[48]) + ); + RAM16X1D com_cmm_u_cmm_errman_cmt_hdr_buf_lutram_data_I_44 ( + .DPO(com_cmm_u_cmm_errman_cmt_hdr_buf_lutram_data[17]), + .WCLK(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_reg_cmt_wr_hdr[17]), + .A0(com_cmm_u_cmm_errman_reg_cmt_wp[0]), + .A1(com_cmm_u_cmm_errman_reg_cmt_wp[1]), + .A2(com_cmm_u_cmm_errman_cmt_hdr_buf_GND_6002), + .A3(com_cmm_u_cmm_errman_cmt_hdr_buf_GND_6002), + .DPRA0(com_cmm_u_cmm_errman_reg_cmt_rp[0]), + .DPRA1(com_cmm_u_cmm_errman_reg_cmt_rp[1]), + .DPRA2(com_cmm_u_cmm_errman_cmt_hdr_buf_GND_6002), + .DPRA3(com_cmm_u_cmm_errman_cmt_hdr_buf_GND_6002), + .SPO(NLW_com_cmm_u_cmm_errman_cmt_hdr_buf_lutram_data_I_44_SPO_UNCONNECTED), + .WE(com_cmm_u_cmm_errman_reg_cmt_wr_hdr[48]) + ); + RAM16X1D com_cmm_u_cmm_errman_cmt_hdr_buf_lutram_data_I_45 ( + .DPO(com_cmm_u_cmm_errman_cmt_hdr_buf_lutram_data[21]), + .WCLK(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_reg_cmt_wr_hdr[21]), + .A0(com_cmm_u_cmm_errman_reg_cmt_wp[0]), + .A1(com_cmm_u_cmm_errman_reg_cmt_wp[1]), + .A2(com_cmm_u_cmm_errman_cmt_hdr_buf_GND_6002), + .A3(com_cmm_u_cmm_errman_cmt_hdr_buf_GND_6002), + .DPRA0(com_cmm_u_cmm_errman_reg_cmt_rp[0]), + .DPRA1(com_cmm_u_cmm_errman_reg_cmt_rp[1]), + .DPRA2(com_cmm_u_cmm_errman_cmt_hdr_buf_GND_6002), + .DPRA3(com_cmm_u_cmm_errman_cmt_hdr_buf_GND_6002), + .SPO(NLW_com_cmm_u_cmm_errman_cmt_hdr_buf_lutram_data_I_45_SPO_UNCONNECTED), + .WE(com_cmm_u_cmm_errman_reg_cmt_wr_hdr[48]) + ); + RAM16X1D com_cmm_u_cmm_errman_cmt_hdr_buf_lutram_data_I_46 ( + .DPO(com_cmm_u_cmm_errman_cmt_hdr_buf_lutram_data[34]), + .WCLK(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_reg_cmt_wr_hdr[34]), + .A0(com_cmm_u_cmm_errman_reg_cmt_wp[0]), + .A1(com_cmm_u_cmm_errman_reg_cmt_wp[1]), + .A2(com_cmm_u_cmm_errman_cmt_hdr_buf_GND_6002), + .A3(com_cmm_u_cmm_errman_cmt_hdr_buf_GND_6002), + .DPRA0(com_cmm_u_cmm_errman_reg_cmt_rp[0]), + .DPRA1(com_cmm_u_cmm_errman_reg_cmt_rp[1]), + .DPRA2(com_cmm_u_cmm_errman_cmt_hdr_buf_GND_6002), + .DPRA3(com_cmm_u_cmm_errman_cmt_hdr_buf_GND_6002), + .SPO(NLW_com_cmm_u_cmm_errman_cmt_hdr_buf_lutram_data_I_46_SPO_UNCONNECTED), + .WE(com_cmm_u_cmm_errman_reg_cmt_wr_hdr[48]) + ); + RAM16X1D com_cmm_u_cmm_errman_cmt_hdr_buf_lutram_data_I_47 ( + .DPO(com_cmm_u_cmm_errman_cmt_hdr_buf_lutram_data[47]), + .WCLK(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_reg_cmt_wr_hdr[47]), + .A0(com_cmm_u_cmm_errman_reg_cmt_wp[0]), + .A1(com_cmm_u_cmm_errman_reg_cmt_wp[1]), + .A2(com_cmm_u_cmm_errman_cmt_hdr_buf_GND_6002), + .A3(com_cmm_u_cmm_errman_cmt_hdr_buf_GND_6002), + .DPRA0(com_cmm_u_cmm_errman_reg_cmt_rp[0]), + .DPRA1(com_cmm_u_cmm_errman_reg_cmt_rp[1]), + .DPRA2(com_cmm_u_cmm_errman_cmt_hdr_buf_GND_6002), + .DPRA3(com_cmm_u_cmm_errman_cmt_hdr_buf_GND_6002), + .SPO(NLW_com_cmm_u_cmm_errman_cmt_hdr_buf_lutram_data_I_47_SPO_UNCONNECTED), + .WE(com_cmm_u_cmm_errman_reg_cmt_wr_hdr[48]) + ); + RAM16X1D com_cmm_u_cmm_errman_cmt_hdr_buf_lutram_data_I_48 ( + .DPO(com_cmm_u_cmm_errman_cmt_hdr_buf_lutram_data[35]), + .WCLK(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_reg_cmt_wr_hdr[35]), + .A0(com_cmm_u_cmm_errman_reg_cmt_wp[0]), + .A1(com_cmm_u_cmm_errman_reg_cmt_wp[1]), + .A2(com_cmm_u_cmm_errman_cmt_hdr_buf_GND_6002), + .A3(com_cmm_u_cmm_errman_cmt_hdr_buf_GND_6002), + .DPRA0(com_cmm_u_cmm_errman_reg_cmt_rp[0]), + .DPRA1(com_cmm_u_cmm_errman_reg_cmt_rp[1]), + .DPRA2(com_cmm_u_cmm_errman_cmt_hdr_buf_GND_6002), + .DPRA3(com_cmm_u_cmm_errman_cmt_hdr_buf_GND_6002), + .SPO(NLW_com_cmm_u_cmm_errman_cmt_hdr_buf_lutram_data_I_48_SPO_UNCONNECTED), + .WE(com_cmm_u_cmm_errman_reg_cmt_wr_hdr[48]) + ); + RAM16X1D com_cmm_u_cmm_errman_cmt_hdr_buf_lutram_data_I_49 ( + .DPO(com_cmm_u_cmm_errman_cmt_hdr_buf_lutram_data[48]), + .WCLK(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_cmt_hdr_buf_VCC_6001), + .A0(com_cmm_u_cmm_errman_reg_cmt_wp[0]), + .A1(com_cmm_u_cmm_errman_reg_cmt_wp[1]), + .A2(com_cmm_u_cmm_errman_cmt_hdr_buf_GND_6002), + .A3(com_cmm_u_cmm_errman_cmt_hdr_buf_GND_6002), + .DPRA0(com_cmm_u_cmm_errman_reg_cmt_rp[0]), + .DPRA1(com_cmm_u_cmm_errman_reg_cmt_rp[1]), + .DPRA2(com_cmm_u_cmm_errman_cmt_hdr_buf_GND_6002), + .DPRA3(com_cmm_u_cmm_errman_cmt_hdr_buf_GND_6002), + .SPO(NLW_com_cmm_u_cmm_errman_cmt_hdr_buf_lutram_data_I_49_SPO_UNCONNECTED), + .WE(com_cmm_u_cmm_errman_reg_cmt_wr_hdr[48]) + ); + RAM16X1D com_cmm_u_cmm_errman_cmt_hdr_buf_lutram_data_I_50 ( + .DPO(com_cmm_u_cmm_errman_cmt_hdr_buf_lutram_data[37]), + .WCLK(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_reg_cmt_wr_hdr[37]), + .A0(com_cmm_u_cmm_errman_reg_cmt_wp[0]), + .A1(com_cmm_u_cmm_errman_reg_cmt_wp[1]), + .A2(com_cmm_u_cmm_errman_cmt_hdr_buf_GND_6002), + .A3(com_cmm_u_cmm_errman_cmt_hdr_buf_GND_6002), + .DPRA0(com_cmm_u_cmm_errman_reg_cmt_rp[0]), + .DPRA1(com_cmm_u_cmm_errman_reg_cmt_rp[1]), + .DPRA2(com_cmm_u_cmm_errman_cmt_hdr_buf_GND_6002), + .DPRA3(com_cmm_u_cmm_errman_cmt_hdr_buf_GND_6002), + .SPO(NLW_com_cmm_u_cmm_errman_cmt_hdr_buf_lutram_data_I_50_SPO_UNCONNECTED), + .WE(com_cmm_u_cmm_errman_reg_cmt_wr_hdr[48]) + ); + FDC com_cmm_u_cmm_errman_cmt_hdr_buf_reg_rdata_5_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_cmt_hdr_buf_lutram_data[5]), + .Q(com_cmm_u_cmm_errman_cmt_rd_hdr[5]), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_errman_cmt_hdr_buf_reg_rdata_4_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_cmt_hdr_buf_lutram_data[4]), + .Q(com_cmm_u_cmm_errman_cmt_rd_hdr[4]), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_errman_cmt_hdr_buf_reg_rdata_3_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_cmt_hdr_buf_lutram_data[3]), + .Q(com_cmm_u_cmm_errman_cmt_rd_hdr[3]), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_errman_cmt_hdr_buf_reg_rdata_2_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_cmt_hdr_buf_lutram_data[2]), + .Q(com_cmm_u_cmm_errman_cmt_rd_hdr[2]), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_errman_cmt_hdr_buf_reg_rdata_1_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_cmt_hdr_buf_lutram_data[1]), + .Q(com_cmm_u_cmm_errman_cmt_rd_hdr[1]), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_errman_cmt_hdr_buf_reg_rdata_0_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_cmt_hdr_buf_lutram_data[0]), + .Q(com_cmm_u_cmm_errman_cmt_rd_hdr[0]), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_errman_cmt_hdr_buf_reg_rdata_20_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_cmt_hdr_buf_lutram_data[20]), + .Q(com_cmm_u_cmm_errman_cmt_rd_hdr[20]), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_errman_cmt_hdr_buf_reg_rdata_19_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_cmt_hdr_buf_lutram_data[19]), + .Q(com_cmm_u_cmm_errman_cmt_rd_hdr[19]), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_errman_cmt_hdr_buf_reg_rdata_18_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_cmt_hdr_buf_lutram_data[18]), + .Q(com_cmm_u_cmm_errman_cmt_rd_hdr[18]), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_errman_cmt_hdr_buf_reg_rdata_17_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_cmt_hdr_buf_lutram_data[17]), + .Q(com_cmm_u_cmm_errman_cmt_rd_hdr[17]), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_errman_cmt_hdr_buf_reg_rdata_16_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_cmt_hdr_buf_lutram_data[16]), + .Q(com_cmm_u_cmm_errman_cmt_rd_hdr[16]), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_errman_cmt_hdr_buf_reg_rdata_15_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_cmt_hdr_buf_lutram_data[15]), + .Q(com_cmm_u_cmm_errman_cmt_rd_hdr[15]), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_errman_cmt_hdr_buf_reg_rdata_14_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_cmt_hdr_buf_lutram_data[14]), + .Q(com_cmm_u_cmm_errman_cmt_rd_hdr[14]), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_errman_cmt_hdr_buf_reg_rdata_13_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_cmt_hdr_buf_lutram_data[13]), + .Q(com_cmm_u_cmm_errman_cmt_rd_hdr[13]), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_errman_cmt_hdr_buf_reg_rdata_12_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_cmt_hdr_buf_lutram_data[12]), + .Q(com_cmm_u_cmm_errman_cmt_rd_hdr[12]), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_errman_cmt_hdr_buf_reg_rdata_11_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_cmt_hdr_buf_lutram_data[11]), + .Q(com_cmm_u_cmm_errman_cmt_rd_hdr[11]), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_errman_cmt_hdr_buf_reg_rdata_10_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_cmt_hdr_buf_lutram_data[10]), + .Q(com_cmm_u_cmm_errman_cmt_rd_hdr[10]), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_errman_cmt_hdr_buf_reg_rdata_9_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_cmt_hdr_buf_lutram_data[9]), + .Q(com_cmm_u_cmm_errman_cmt_rd_hdr[9]), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_errman_cmt_hdr_buf_reg_rdata_8_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_cmt_hdr_buf_lutram_data[8]), + .Q(com_cmm_u_cmm_errman_cmt_rd_hdr[8]), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_errman_cmt_hdr_buf_reg_rdata_7_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_cmt_hdr_buf_lutram_data[7]), + .Q(com_cmm_u_cmm_errman_cmt_rd_hdr[7]), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_errman_cmt_hdr_buf_reg_rdata_6_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_cmt_hdr_buf_lutram_data[6]), + .Q(com_cmm_u_cmm_errman_cmt_rd_hdr[6]), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_errman_cmt_hdr_buf_reg_rdata_35_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_cmt_hdr_buf_lutram_data[35]), + .Q(com_cmm_u_cmm_errman_cmt_rd_hdr[35]), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_errman_cmt_hdr_buf_reg_rdata_34_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_cmt_hdr_buf_lutram_data[34]), + .Q(com_cmm_u_cmm_errman_cmt_rd_hdr[34]), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_errman_cmt_hdr_buf_reg_rdata_33_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_cmt_hdr_buf_lutram_data[33]), + .Q(com_cmm_u_cmm_errman_cmt_rd_hdr[33]), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_errman_cmt_hdr_buf_reg_rdata_32_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_cmt_hdr_buf_lutram_data[32]), + .Q(com_cmm_u_cmm_errman_cmt_rd_hdr[32]), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_errman_cmt_hdr_buf_reg_rdata_31_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_cmt_hdr_buf_lutram_data[31]), + .Q(com_cmm_u_cmm_errman_cmt_rd_hdr[31]), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_errman_cmt_hdr_buf_reg_rdata_30_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_cmt_hdr_buf_lutram_data[30]), + .Q(com_cmm_u_cmm_errman_cmt_rd_hdr[30]), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_errman_cmt_hdr_buf_reg_rdata_29_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_cmt_hdr_buf_lutram_data[29]), + .Q(com_cmm_u_cmm_errman_cmt_rd_hdr[29]), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_errman_cmt_hdr_buf_reg_rdata_28_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_cmt_hdr_buf_lutram_data[28]), + .Q(com_cmm_u_cmm_errman_cmt_rd_hdr[28]), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_errman_cmt_hdr_buf_reg_rdata_27_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_cmt_hdr_buf_lutram_data[27]), + .Q(com_cmm_u_cmm_errman_cmt_rd_hdr[27]), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_errman_cmt_hdr_buf_reg_rdata_26_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_cmt_hdr_buf_lutram_data[26]), + .Q(com_cmm_u_cmm_errman_cmt_rd_hdr[26]), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_errman_cmt_hdr_buf_reg_rdata_25_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_cmt_hdr_buf_lutram_data[25]), + .Q(com_cmm_u_cmm_errman_cmt_rd_hdr[25]), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_errman_cmt_hdr_buf_reg_rdata_24_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_cmt_hdr_buf_lutram_data[24]), + .Q(com_cmm_u_cmm_errman_cmt_rd_hdr[24]), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_errman_cmt_hdr_buf_reg_rdata_23_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_cmt_hdr_buf_lutram_data[23]), + .Q(com_cmm_u_cmm_errman_cmt_rd_hdr[23]), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_errman_cmt_hdr_buf_reg_rdata_22_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_cmt_hdr_buf_lutram_data[22]), + .Q(com_cmm_u_cmm_errman_cmt_rd_hdr[22]), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_errman_cmt_hdr_buf_reg_rdata_21_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_cmt_hdr_buf_lutram_data[21]), + .Q(com_cmm_u_cmm_errman_cmt_rd_hdr[21]), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_errman_cmt_hdr_buf_reg_rdata_49_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_cmt_hdr_buf_lutram_data[49]), + .Q(com_cmm_u_cmm_errman_cmt_rd_hdr[49]), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_errman_cmt_hdr_buf_reg_rdata_48_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_cmt_hdr_buf_lutram_data[48]), + .Q(com_cmm_u_cmm_errman_cmt_rd_hdr[48]), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_errman_cmt_hdr_buf_reg_rdata_47_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_cmt_hdr_buf_lutram_data[47]), + .Q(com_cmm_u_cmm_errman_cmt_rd_hdr[47]), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_errman_cmt_hdr_buf_reg_rdata_46_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_cmt_hdr_buf_lutram_data[46]), + .Q(com_cmm_u_cmm_errman_cmt_rd_hdr[46]), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_errman_cmt_hdr_buf_reg_rdata_45_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_cmt_hdr_buf_lutram_data[45]), + .Q(com_cmm_u_cmm_errman_cmt_rd_hdr[45]), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_errman_cmt_hdr_buf_reg_rdata_44_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_cmt_hdr_buf_lutram_data[44]), + .Q(com_cmm_u_cmm_errman_cmt_rd_hdr[44]), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_errman_cmt_hdr_buf_reg_rdata_43_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_cmt_hdr_buf_lutram_data[43]), + .Q(com_cmm_u_cmm_errman_cmt_rd_hdr[43]), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_errman_cmt_hdr_buf_reg_rdata_42_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_cmt_hdr_buf_lutram_data[42]), + .Q(com_cmm_u_cmm_errman_cmt_rd_hdr[42]), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_errman_cmt_hdr_buf_reg_rdata_41_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_cmt_hdr_buf_lutram_data[41]), + .Q(com_cmm_u_cmm_errman_cmt_rd_hdr[41]), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_errman_cmt_hdr_buf_reg_rdata_40_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_cmt_hdr_buf_lutram_data[40]), + .Q(com_cmm_u_cmm_errman_cmt_rd_hdr[40]), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_errman_cmt_hdr_buf_reg_rdata_39_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_cmt_hdr_buf_lutram_data[39]), + .Q(com_cmm_u_cmm_errman_cmt_rd_hdr[39]), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_errman_cmt_hdr_buf_reg_rdata_38_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_cmt_hdr_buf_lutram_data[38]), + .Q(com_cmm_u_cmm_errman_cmt_rd_hdr[38]), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_errman_cmt_hdr_buf_reg_rdata_37_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_cmt_hdr_buf_lutram_data[37]), + .Q(com_cmm_u_cmm_errman_cmt_rd_hdr[37]), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_errman_cmt_hdr_buf_reg_rdata_36_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_cmt_hdr_buf_lutram_data[36]), + .Q(com_cmm_u_cmm_errman_cmt_rd_hdr[36]), + .CLR(com_cmm_rst_351) + ); + GND com_cmm_u_cmm_errman_cfg_hdr_buf_GND ( + .G(com_cmm_u_cmm_errman_cfg_hdr_buf_GND_6003) + ); + RAM16X1D com_cmm_u_cmm_errman_cfg_hdr_buf_lutram_data_I_1 ( + .DPO(com_cmm_u_cmm_errman_cfg_hdr_buf_lutram_data[40]), + .WCLK(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_reg_cfg_wr_hdr[40]), + .A0(com_cmm_u_cmm_errman_reg_cfg_wp[0]), + .A1(com_cmm_u_cmm_errman_reg_cfg_wp[1]), + .A2(com_cmm_u_cmm_errman_cfg_hdr_buf_GND_6003), + .A3(com_cmm_u_cmm_errman_cfg_hdr_buf_GND_6003), + .DPRA0(com_cmm_u_cmm_errman_reg_cfg_rp[0]), + .DPRA1(com_cmm_u_cmm_errman_reg_cfg_rp[1]), + .DPRA2(com_cmm_u_cmm_errman_cfg_hdr_buf_GND_6003), + .DPRA3(com_cmm_u_cmm_errman_cfg_hdr_buf_GND_6003), + .SPO(NLW_com_cmm_u_cmm_errman_cfg_hdr_buf_lutram_data_I_1_SPO_UNCONNECTED), + .WE(com_cmm_u_cmm_errman_reg_incr_cplu_5852) + ); + RAM16X1D com_cmm_u_cmm_errman_cfg_hdr_buf_lutram_data_I_2 ( + .DPO(com_cmm_u_cmm_errman_cfg_hdr_buf_lutram_data[27]), + .WCLK(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_reg_cfg_wr_hdr[27]), + .A0(com_cmm_u_cmm_errman_reg_cfg_wp[0]), + .A1(com_cmm_u_cmm_errman_reg_cfg_wp[1]), + .A2(com_cmm_u_cmm_errman_cfg_hdr_buf_GND_6003), + .A3(com_cmm_u_cmm_errman_cfg_hdr_buf_GND_6003), + .DPRA0(com_cmm_u_cmm_errman_reg_cfg_rp[0]), + .DPRA1(com_cmm_u_cmm_errman_reg_cfg_rp[1]), + .DPRA2(com_cmm_u_cmm_errman_cfg_hdr_buf_GND_6003), + .DPRA3(com_cmm_u_cmm_errman_cfg_hdr_buf_GND_6003), + .SPO(NLW_com_cmm_u_cmm_errman_cfg_hdr_buf_lutram_data_I_2_SPO_UNCONNECTED), + .WE(com_cmm_u_cmm_errman_reg_incr_cplu_5852) + ); + RAM16X1D com_cmm_u_cmm_errman_cfg_hdr_buf_lutram_data_I_3 ( + .DPO(com_cmm_u_cmm_errman_cfg_hdr_buf_lutram_data[1]), + .WCLK(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_reg_cfg_wr_hdr[1]), + .A0(com_cmm_u_cmm_errman_reg_cfg_wp[0]), + .A1(com_cmm_u_cmm_errman_reg_cfg_wp[1]), + .A2(com_cmm_u_cmm_errman_cfg_hdr_buf_GND_6003), + .A3(com_cmm_u_cmm_errman_cfg_hdr_buf_GND_6003), + .DPRA0(com_cmm_u_cmm_errman_reg_cfg_rp[0]), + .DPRA1(com_cmm_u_cmm_errman_reg_cfg_rp[1]), + .DPRA2(com_cmm_u_cmm_errman_cfg_hdr_buf_GND_6003), + .DPRA3(com_cmm_u_cmm_errman_cfg_hdr_buf_GND_6003), + .SPO(NLW_com_cmm_u_cmm_errman_cfg_hdr_buf_lutram_data_I_3_SPO_UNCONNECTED), + .WE(com_cmm_u_cmm_errman_reg_incr_cplu_5852) + ); + RAM16X1D com_cmm_u_cmm_errman_cfg_hdr_buf_lutram_data_I_4 ( + .DPO(com_cmm_u_cmm_errman_cfg_hdr_buf_lutram_data[5]), + .WCLK(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_reg_cfg_wr_hdr[5]), + .A0(com_cmm_u_cmm_errman_reg_cfg_wp[0]), + .A1(com_cmm_u_cmm_errman_reg_cfg_wp[1]), + .A2(com_cmm_u_cmm_errman_cfg_hdr_buf_GND_6003), + .A3(com_cmm_u_cmm_errman_cfg_hdr_buf_GND_6003), + .DPRA0(com_cmm_u_cmm_errman_reg_cfg_rp[0]), + .DPRA1(com_cmm_u_cmm_errman_reg_cfg_rp[1]), + .DPRA2(com_cmm_u_cmm_errman_cfg_hdr_buf_GND_6003), + .DPRA3(com_cmm_u_cmm_errman_cfg_hdr_buf_GND_6003), + .SPO(NLW_com_cmm_u_cmm_errman_cfg_hdr_buf_lutram_data_I_4_SPO_UNCONNECTED), + .WE(com_cmm_u_cmm_errman_reg_incr_cplu_5852) + ); + RAM16X1D com_cmm_u_cmm_errman_cfg_hdr_buf_lutram_data_I_5 ( + .DPO(com_cmm_u_cmm_errman_cfg_hdr_buf_lutram_data[30]), + .WCLK(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_reg_cfg_wr_hdr[30]), + .A0(com_cmm_u_cmm_errman_reg_cfg_wp[0]), + .A1(com_cmm_u_cmm_errman_reg_cfg_wp[1]), + .A2(com_cmm_u_cmm_errman_cfg_hdr_buf_GND_6003), + .A3(com_cmm_u_cmm_errman_cfg_hdr_buf_GND_6003), + .DPRA0(com_cmm_u_cmm_errman_reg_cfg_rp[0]), + .DPRA1(com_cmm_u_cmm_errman_reg_cfg_rp[1]), + .DPRA2(com_cmm_u_cmm_errman_cfg_hdr_buf_GND_6003), + .DPRA3(com_cmm_u_cmm_errman_cfg_hdr_buf_GND_6003), + .SPO(NLW_com_cmm_u_cmm_errman_cfg_hdr_buf_lutram_data_I_5_SPO_UNCONNECTED), + .WE(com_cmm_u_cmm_errman_reg_incr_cplu_5852) + ); + RAM16X1D com_cmm_u_cmm_errman_cfg_hdr_buf_lutram_data_I_6 ( + .DPO(com_cmm_u_cmm_errman_cfg_hdr_buf_lutram_data[43]), + .WCLK(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_reg_cfg_wr_hdr[43]), + .A0(com_cmm_u_cmm_errman_reg_cfg_wp[0]), + .A1(com_cmm_u_cmm_errman_reg_cfg_wp[1]), + .A2(com_cmm_u_cmm_errman_cfg_hdr_buf_GND_6003), + .A3(com_cmm_u_cmm_errman_cfg_hdr_buf_GND_6003), + .DPRA0(com_cmm_u_cmm_errman_reg_cfg_rp[0]), + .DPRA1(com_cmm_u_cmm_errman_reg_cfg_rp[1]), + .DPRA2(com_cmm_u_cmm_errman_cfg_hdr_buf_GND_6003), + .DPRA3(com_cmm_u_cmm_errman_cfg_hdr_buf_GND_6003), + .SPO(NLW_com_cmm_u_cmm_errman_cfg_hdr_buf_lutram_data_I_6_SPO_UNCONNECTED), + .WE(com_cmm_u_cmm_errman_reg_incr_cplu_5852) + ); + RAM16X1D com_cmm_u_cmm_errman_cfg_hdr_buf_lutram_data_I_7 ( + .DPO(com_cmm_u_cmm_errman_cfg_hdr_buf_lutram_data[16]), + .WCLK(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_reg_cfg_wr_hdr[16]), + .A0(com_cmm_u_cmm_errman_reg_cfg_wp[0]), + .A1(com_cmm_u_cmm_errman_reg_cfg_wp[1]), + .A2(com_cmm_u_cmm_errman_cfg_hdr_buf_GND_6003), + .A3(com_cmm_u_cmm_errman_cfg_hdr_buf_GND_6003), + .DPRA0(com_cmm_u_cmm_errman_reg_cfg_rp[0]), + .DPRA1(com_cmm_u_cmm_errman_reg_cfg_rp[1]), + .DPRA2(com_cmm_u_cmm_errman_cfg_hdr_buf_GND_6003), + .DPRA3(com_cmm_u_cmm_errman_cfg_hdr_buf_GND_6003), + .SPO(NLW_com_cmm_u_cmm_errman_cfg_hdr_buf_lutram_data_I_7_SPO_UNCONNECTED), + .WE(com_cmm_u_cmm_errman_reg_incr_cplu_5852) + ); + RAM16X1D com_cmm_u_cmm_errman_cfg_hdr_buf_lutram_data_I_8 ( + .DPO(com_cmm_u_cmm_errman_cfg_hdr_buf_lutram_data[29]), + .WCLK(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_reg_cfg_wr_hdr[29]), + .A0(com_cmm_u_cmm_errman_reg_cfg_wp[0]), + .A1(com_cmm_u_cmm_errman_reg_cfg_wp[1]), + .A2(com_cmm_u_cmm_errman_cfg_hdr_buf_GND_6003), + .A3(com_cmm_u_cmm_errman_cfg_hdr_buf_GND_6003), + .DPRA0(com_cmm_u_cmm_errman_reg_cfg_rp[0]), + .DPRA1(com_cmm_u_cmm_errman_reg_cfg_rp[1]), + .DPRA2(com_cmm_u_cmm_errman_cfg_hdr_buf_GND_6003), + .DPRA3(com_cmm_u_cmm_errman_cfg_hdr_buf_GND_6003), + .SPO(NLW_com_cmm_u_cmm_errman_cfg_hdr_buf_lutram_data_I_8_SPO_UNCONNECTED), + .WE(com_cmm_u_cmm_errman_reg_incr_cplu_5852) + ); + RAM16X1D com_cmm_u_cmm_errman_cfg_hdr_buf_lutram_data_I_9 ( + .DPO(com_cmm_u_cmm_errman_cfg_hdr_buf_lutram_data[42]), + .WCLK(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_reg_cfg_wr_hdr[42]), + .A0(com_cmm_u_cmm_errman_reg_cfg_wp[0]), + .A1(com_cmm_u_cmm_errman_reg_cfg_wp[1]), + .A2(com_cmm_u_cmm_errman_cfg_hdr_buf_GND_6003), + .A3(com_cmm_u_cmm_errman_cfg_hdr_buf_GND_6003), + .DPRA0(com_cmm_u_cmm_errman_reg_cfg_rp[0]), + .DPRA1(com_cmm_u_cmm_errman_reg_cfg_rp[1]), + .DPRA2(com_cmm_u_cmm_errman_cfg_hdr_buf_GND_6003), + .DPRA3(com_cmm_u_cmm_errman_cfg_hdr_buf_GND_6003), + .SPO(NLW_com_cmm_u_cmm_errman_cfg_hdr_buf_lutram_data_I_9_SPO_UNCONNECTED), + .WE(com_cmm_u_cmm_errman_reg_incr_cplu_5852) + ); + RAM16X1D com_cmm_u_cmm_errman_cfg_hdr_buf_lutram_data_I_10 ( + .DPO(com_cmm_u_cmm_errman_cfg_hdr_buf_lutram_data[15]), + .WCLK(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_reg_cfg_wr_hdr[15]), + .A0(com_cmm_u_cmm_errman_reg_cfg_wp[0]), + .A1(com_cmm_u_cmm_errman_reg_cfg_wp[1]), + .A2(com_cmm_u_cmm_errman_cfg_hdr_buf_GND_6003), + .A3(com_cmm_u_cmm_errman_cfg_hdr_buf_GND_6003), + .DPRA0(com_cmm_u_cmm_errman_reg_cfg_rp[0]), + .DPRA1(com_cmm_u_cmm_errman_reg_cfg_rp[1]), + .DPRA2(com_cmm_u_cmm_errman_cfg_hdr_buf_GND_6003), + .DPRA3(com_cmm_u_cmm_errman_cfg_hdr_buf_GND_6003), + .SPO(NLW_com_cmm_u_cmm_errman_cfg_hdr_buf_lutram_data_I_10_SPO_UNCONNECTED), + .WE(com_cmm_u_cmm_errman_reg_incr_cplu_5852) + ); + RAM16X1D com_cmm_u_cmm_errman_cfg_hdr_buf_lutram_data_I_11 ( + .DPO(com_cmm_u_cmm_errman_cfg_hdr_buf_lutram_data[18]), + .WCLK(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_reg_cfg_wr_hdr[18]), + .A0(com_cmm_u_cmm_errman_reg_cfg_wp[0]), + .A1(com_cmm_u_cmm_errman_reg_cfg_wp[1]), + .A2(com_cmm_u_cmm_errman_cfg_hdr_buf_GND_6003), + .A3(com_cmm_u_cmm_errman_cfg_hdr_buf_GND_6003), + .DPRA0(com_cmm_u_cmm_errman_reg_cfg_rp[0]), + .DPRA1(com_cmm_u_cmm_errman_reg_cfg_rp[1]), + .DPRA2(com_cmm_u_cmm_errman_cfg_hdr_buf_GND_6003), + .DPRA3(com_cmm_u_cmm_errman_cfg_hdr_buf_GND_6003), + .SPO(NLW_com_cmm_u_cmm_errman_cfg_hdr_buf_lutram_data_I_11_SPO_UNCONNECTED), + .WE(com_cmm_u_cmm_errman_reg_incr_cplu_5852) + ); + RAM16X1D com_cmm_u_cmm_errman_cfg_hdr_buf_lutram_data_I_12 ( + .DPO(com_cmm_u_cmm_errman_cfg_hdr_buf_lutram_data[32]), + .WCLK(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_reg_cfg_wr_hdr[32]), + .A0(com_cmm_u_cmm_errman_reg_cfg_wp[0]), + .A1(com_cmm_u_cmm_errman_reg_cfg_wp[1]), + .A2(com_cmm_u_cmm_errman_cfg_hdr_buf_GND_6003), + .A3(com_cmm_u_cmm_errman_cfg_hdr_buf_GND_6003), + .DPRA0(com_cmm_u_cmm_errman_reg_cfg_rp[0]), + .DPRA1(com_cmm_u_cmm_errman_reg_cfg_rp[1]), + .DPRA2(com_cmm_u_cmm_errman_cfg_hdr_buf_GND_6003), + .DPRA3(com_cmm_u_cmm_errman_cfg_hdr_buf_GND_6003), + .SPO(NLW_com_cmm_u_cmm_errman_cfg_hdr_buf_lutram_data_I_12_SPO_UNCONNECTED), + .WE(com_cmm_u_cmm_errman_reg_incr_cplu_5852) + ); + RAM16X1D com_cmm_u_cmm_errman_cfg_hdr_buf_lutram_data_I_13 ( + .DPO(com_cmm_u_cmm_errman_cfg_hdr_buf_lutram_data[45]), + .WCLK(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_reg_cfg_wr_hdr[45]), + .A0(com_cmm_u_cmm_errman_reg_cfg_wp[0]), + .A1(com_cmm_u_cmm_errman_reg_cfg_wp[1]), + .A2(com_cmm_u_cmm_errman_cfg_hdr_buf_GND_6003), + .A3(com_cmm_u_cmm_errman_cfg_hdr_buf_GND_6003), + .DPRA0(com_cmm_u_cmm_errman_reg_cfg_rp[0]), + .DPRA1(com_cmm_u_cmm_errman_reg_cfg_rp[1]), + .DPRA2(com_cmm_u_cmm_errman_cfg_hdr_buf_GND_6003), + .DPRA3(com_cmm_u_cmm_errman_cfg_hdr_buf_GND_6003), + .SPO(NLW_com_cmm_u_cmm_errman_cfg_hdr_buf_lutram_data_I_13_SPO_UNCONNECTED), + .WE(com_cmm_u_cmm_errman_reg_incr_cplu_5852) + ); + RAM16X1D com_cmm_u_cmm_errman_cfg_hdr_buf_lutram_data_I_14 ( + .DPO(com_cmm_u_cmm_errman_cfg_hdr_buf_lutram_data[28]), + .WCLK(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_reg_cfg_wr_hdr[28]), + .A0(com_cmm_u_cmm_errman_reg_cfg_wp[0]), + .A1(com_cmm_u_cmm_errman_reg_cfg_wp[1]), + .A2(com_cmm_u_cmm_errman_cfg_hdr_buf_GND_6003), + .A3(com_cmm_u_cmm_errman_cfg_hdr_buf_GND_6003), + .DPRA0(com_cmm_u_cmm_errman_reg_cfg_rp[0]), + .DPRA1(com_cmm_u_cmm_errman_reg_cfg_rp[1]), + .DPRA2(com_cmm_u_cmm_errman_cfg_hdr_buf_GND_6003), + .DPRA3(com_cmm_u_cmm_errman_cfg_hdr_buf_GND_6003), + .SPO(NLW_com_cmm_u_cmm_errman_cfg_hdr_buf_lutram_data_I_14_SPO_UNCONNECTED), + .WE(com_cmm_u_cmm_errman_reg_incr_cplu_5852) + ); + RAM16X1D com_cmm_u_cmm_errman_cfg_hdr_buf_lutram_data_I_15 ( + .DPO(com_cmm_u_cmm_errman_cfg_hdr_buf_lutram_data[0]), + .WCLK(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_reg_cfg_wr_hdr[0]), + .A0(com_cmm_u_cmm_errman_reg_cfg_wp[0]), + .A1(com_cmm_u_cmm_errman_reg_cfg_wp[1]), + .A2(com_cmm_u_cmm_errman_cfg_hdr_buf_GND_6003), + .A3(com_cmm_u_cmm_errman_cfg_hdr_buf_GND_6003), + .DPRA0(com_cmm_u_cmm_errman_reg_cfg_rp[0]), + .DPRA1(com_cmm_u_cmm_errman_reg_cfg_rp[1]), + .DPRA2(com_cmm_u_cmm_errman_cfg_hdr_buf_GND_6003), + .DPRA3(com_cmm_u_cmm_errman_cfg_hdr_buf_GND_6003), + .SPO(NLW_com_cmm_u_cmm_errman_cfg_hdr_buf_lutram_data_I_15_SPO_UNCONNECTED), + .WE(com_cmm_u_cmm_errman_reg_incr_cplu_5852) + ); + RAM16X1D com_cmm_u_cmm_errman_cfg_hdr_buf_lutram_data_I_16 ( + .DPO(com_cmm_u_cmm_errman_cfg_hdr_buf_lutram_data[4]), + .WCLK(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_reg_cfg_wr_hdr[4]), + .A0(com_cmm_u_cmm_errman_reg_cfg_wp[0]), + .A1(com_cmm_u_cmm_errman_reg_cfg_wp[1]), + .A2(com_cmm_u_cmm_errman_cfg_hdr_buf_GND_6003), + .A3(com_cmm_u_cmm_errman_cfg_hdr_buf_GND_6003), + .DPRA0(com_cmm_u_cmm_errman_reg_cfg_rp[0]), + .DPRA1(com_cmm_u_cmm_errman_reg_cfg_rp[1]), + .DPRA2(com_cmm_u_cmm_errman_cfg_hdr_buf_GND_6003), + .DPRA3(com_cmm_u_cmm_errman_cfg_hdr_buf_GND_6003), + .SPO(NLW_com_cmm_u_cmm_errman_cfg_hdr_buf_lutram_data_I_16_SPO_UNCONNECTED), + .WE(com_cmm_u_cmm_errman_reg_incr_cplu_5852) + ); + RAM16X1D com_cmm_u_cmm_errman_cfg_hdr_buf_lutram_data_I_17 ( + .DPO(com_cmm_u_cmm_errman_cfg_hdr_buf_lutram_data[8]), + .WCLK(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_reg_cfg_wr_hdr[8]), + .A0(com_cmm_u_cmm_errman_reg_cfg_wp[0]), + .A1(com_cmm_u_cmm_errman_reg_cfg_wp[1]), + .A2(com_cmm_u_cmm_errman_cfg_hdr_buf_GND_6003), + .A3(com_cmm_u_cmm_errman_cfg_hdr_buf_GND_6003), + .DPRA0(com_cmm_u_cmm_errman_reg_cfg_rp[0]), + .DPRA1(com_cmm_u_cmm_errman_reg_cfg_rp[1]), + .DPRA2(com_cmm_u_cmm_errman_cfg_hdr_buf_GND_6003), + .DPRA3(com_cmm_u_cmm_errman_cfg_hdr_buf_GND_6003), + .SPO(NLW_com_cmm_u_cmm_errman_cfg_hdr_buf_lutram_data_I_17_SPO_UNCONNECTED), + .WE(com_cmm_u_cmm_errman_reg_incr_cplu_5852) + ); + RAM16X1D com_cmm_u_cmm_errman_cfg_hdr_buf_lutram_data_I_18 ( + .DPO(com_cmm_u_cmm_errman_cfg_hdr_buf_lutram_data[2]), + .WCLK(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_reg_cfg_wr_hdr[2]), + .A0(com_cmm_u_cmm_errman_reg_cfg_wp[0]), + .A1(com_cmm_u_cmm_errman_reg_cfg_wp[1]), + .A2(com_cmm_u_cmm_errman_cfg_hdr_buf_GND_6003), + .A3(com_cmm_u_cmm_errman_cfg_hdr_buf_GND_6003), + .DPRA0(com_cmm_u_cmm_errman_reg_cfg_rp[0]), + .DPRA1(com_cmm_u_cmm_errman_reg_cfg_rp[1]), + .DPRA2(com_cmm_u_cmm_errman_cfg_hdr_buf_GND_6003), + .DPRA3(com_cmm_u_cmm_errman_cfg_hdr_buf_GND_6003), + .SPO(NLW_com_cmm_u_cmm_errman_cfg_hdr_buf_lutram_data_I_18_SPO_UNCONNECTED), + .WE(com_cmm_u_cmm_errman_reg_incr_cplu_5852) + ); + RAM16X1D com_cmm_u_cmm_errman_cfg_hdr_buf_lutram_data_I_19 ( + .DPO(com_cmm_u_cmm_errman_cfg_hdr_buf_lutram_data[3]), + .WCLK(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_reg_cfg_wr_hdr[3]), + .A0(com_cmm_u_cmm_errman_reg_cfg_wp[0]), + .A1(com_cmm_u_cmm_errman_reg_cfg_wp[1]), + .A2(com_cmm_u_cmm_errman_cfg_hdr_buf_GND_6003), + .A3(com_cmm_u_cmm_errman_cfg_hdr_buf_GND_6003), + .DPRA0(com_cmm_u_cmm_errman_reg_cfg_rp[0]), + .DPRA1(com_cmm_u_cmm_errman_reg_cfg_rp[1]), + .DPRA2(com_cmm_u_cmm_errman_cfg_hdr_buf_GND_6003), + .DPRA3(com_cmm_u_cmm_errman_cfg_hdr_buf_GND_6003), + .SPO(NLW_com_cmm_u_cmm_errman_cfg_hdr_buf_lutram_data_I_19_SPO_UNCONNECTED), + .WE(com_cmm_u_cmm_errman_reg_incr_cplu_5852) + ); + RAM16X1D com_cmm_u_cmm_errman_cfg_hdr_buf_lutram_data_I_20 ( + .DPO(com_cmm_u_cmm_errman_cfg_hdr_buf_lutram_data[7]), + .WCLK(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_reg_cfg_wr_hdr[7]), + .A0(com_cmm_u_cmm_errman_reg_cfg_wp[0]), + .A1(com_cmm_u_cmm_errman_reg_cfg_wp[1]), + .A2(com_cmm_u_cmm_errman_cfg_hdr_buf_GND_6003), + .A3(com_cmm_u_cmm_errman_cfg_hdr_buf_GND_6003), + .DPRA0(com_cmm_u_cmm_errman_reg_cfg_rp[0]), + .DPRA1(com_cmm_u_cmm_errman_reg_cfg_rp[1]), + .DPRA2(com_cmm_u_cmm_errman_cfg_hdr_buf_GND_6003), + .DPRA3(com_cmm_u_cmm_errman_cfg_hdr_buf_GND_6003), + .SPO(NLW_com_cmm_u_cmm_errman_cfg_hdr_buf_lutram_data_I_20_SPO_UNCONNECTED), + .WE(com_cmm_u_cmm_errman_reg_incr_cplu_5852) + ); + RAM16X1D com_cmm_u_cmm_errman_cfg_hdr_buf_lutram_data_I_21 ( + .DPO(com_cmm_u_cmm_errman_cfg_hdr_buf_lutram_data[20]), + .WCLK(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_reg_cfg_wr_hdr[20]), + .A0(com_cmm_u_cmm_errman_reg_cfg_wp[0]), + .A1(com_cmm_u_cmm_errman_reg_cfg_wp[1]), + .A2(com_cmm_u_cmm_errman_cfg_hdr_buf_GND_6003), + .A3(com_cmm_u_cmm_errman_cfg_hdr_buf_GND_6003), + .DPRA0(com_cmm_u_cmm_errman_reg_cfg_rp[0]), + .DPRA1(com_cmm_u_cmm_errman_reg_cfg_rp[1]), + .DPRA2(com_cmm_u_cmm_errman_cfg_hdr_buf_GND_6003), + .DPRA3(com_cmm_u_cmm_errman_cfg_hdr_buf_GND_6003), + .SPO(NLW_com_cmm_u_cmm_errman_cfg_hdr_buf_lutram_data_I_21_SPO_UNCONNECTED), + .WE(com_cmm_u_cmm_errman_reg_incr_cplu_5852) + ); + RAM16X1D com_cmm_u_cmm_errman_cfg_hdr_buf_lutram_data_I_22 ( + .DPO(com_cmm_u_cmm_errman_cfg_hdr_buf_lutram_data[33]), + .WCLK(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_reg_cfg_wr_hdr[33]), + .A0(com_cmm_u_cmm_errman_reg_cfg_wp[0]), + .A1(com_cmm_u_cmm_errman_reg_cfg_wp[1]), + .A2(com_cmm_u_cmm_errman_cfg_hdr_buf_GND_6003), + .A3(com_cmm_u_cmm_errman_cfg_hdr_buf_GND_6003), + .DPRA0(com_cmm_u_cmm_errman_reg_cfg_rp[0]), + .DPRA1(com_cmm_u_cmm_errman_reg_cfg_rp[1]), + .DPRA2(com_cmm_u_cmm_errman_cfg_hdr_buf_GND_6003), + .DPRA3(com_cmm_u_cmm_errman_cfg_hdr_buf_GND_6003), + .SPO(NLW_com_cmm_u_cmm_errman_cfg_hdr_buf_lutram_data_I_22_SPO_UNCONNECTED), + .WE(com_cmm_u_cmm_errman_reg_incr_cplu_5852) + ); + RAM16X1D com_cmm_u_cmm_errman_cfg_hdr_buf_lutram_data_I_23 ( + .DPO(com_cmm_u_cmm_errman_cfg_hdr_buf_lutram_data[46]), + .WCLK(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_reg_cfg_wr_hdr[46]), + .A0(com_cmm_u_cmm_errman_reg_cfg_wp[0]), + .A1(com_cmm_u_cmm_errman_reg_cfg_wp[1]), + .A2(com_cmm_u_cmm_errman_cfg_hdr_buf_GND_6003), + .A3(com_cmm_u_cmm_errman_cfg_hdr_buf_GND_6003), + .DPRA0(com_cmm_u_cmm_errman_reg_cfg_rp[0]), + .DPRA1(com_cmm_u_cmm_errman_reg_cfg_rp[1]), + .DPRA2(com_cmm_u_cmm_errman_cfg_hdr_buf_GND_6003), + .DPRA3(com_cmm_u_cmm_errman_cfg_hdr_buf_GND_6003), + .SPO(NLW_com_cmm_u_cmm_errman_cfg_hdr_buf_lutram_data_I_23_SPO_UNCONNECTED), + .WE(com_cmm_u_cmm_errman_reg_incr_cplu_5852) + ); + RAM16X1D com_cmm_u_cmm_errman_cfg_hdr_buf_lutram_data_I_24 ( + .DPO(com_cmm_u_cmm_errman_cfg_hdr_buf_lutram_data[9]), + .WCLK(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_reg_cfg_wr_hdr[9]), + .A0(com_cmm_u_cmm_errman_reg_cfg_wp[0]), + .A1(com_cmm_u_cmm_errman_reg_cfg_wp[1]), + .A2(com_cmm_u_cmm_errman_cfg_hdr_buf_GND_6003), + .A3(com_cmm_u_cmm_errman_cfg_hdr_buf_GND_6003), + .DPRA0(com_cmm_u_cmm_errman_reg_cfg_rp[0]), + .DPRA1(com_cmm_u_cmm_errman_reg_cfg_rp[1]), + .DPRA2(com_cmm_u_cmm_errman_cfg_hdr_buf_GND_6003), + .DPRA3(com_cmm_u_cmm_errman_cfg_hdr_buf_GND_6003), + .SPO(NLW_com_cmm_u_cmm_errman_cfg_hdr_buf_lutram_data_I_24_SPO_UNCONNECTED), + .WE(com_cmm_u_cmm_errman_reg_incr_cplu_5852) + ); + RAM16X1D com_cmm_u_cmm_errman_cfg_hdr_buf_lutram_data_I_25 ( + .DPO(com_cmm_u_cmm_errman_cfg_hdr_buf_lutram_data[41]), + .WCLK(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_reg_cfg_wr_hdr[41]), + .A0(com_cmm_u_cmm_errman_reg_cfg_wp[0]), + .A1(com_cmm_u_cmm_errman_reg_cfg_wp[1]), + .A2(com_cmm_u_cmm_errman_cfg_hdr_buf_GND_6003), + .A3(com_cmm_u_cmm_errman_cfg_hdr_buf_GND_6003), + .DPRA0(com_cmm_u_cmm_errman_reg_cfg_rp[0]), + .DPRA1(com_cmm_u_cmm_errman_reg_cfg_rp[1]), + .DPRA2(com_cmm_u_cmm_errman_cfg_hdr_buf_GND_6003), + .DPRA3(com_cmm_u_cmm_errman_cfg_hdr_buf_GND_6003), + .SPO(NLW_com_cmm_u_cmm_errman_cfg_hdr_buf_lutram_data_I_25_SPO_UNCONNECTED), + .WE(com_cmm_u_cmm_errman_reg_incr_cplu_5852) + ); + RAM16X1D com_cmm_u_cmm_errman_cfg_hdr_buf_lutram_data_I_26 ( + .DPO(com_cmm_u_cmm_errman_cfg_hdr_buf_lutram_data[14]), + .WCLK(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_reg_cfg_wr_hdr[14]), + .A0(com_cmm_u_cmm_errman_reg_cfg_wp[0]), + .A1(com_cmm_u_cmm_errman_reg_cfg_wp[1]), + .A2(com_cmm_u_cmm_errman_cfg_hdr_buf_GND_6003), + .A3(com_cmm_u_cmm_errman_cfg_hdr_buf_GND_6003), + .DPRA0(com_cmm_u_cmm_errman_reg_cfg_rp[0]), + .DPRA1(com_cmm_u_cmm_errman_reg_cfg_rp[1]), + .DPRA2(com_cmm_u_cmm_errman_cfg_hdr_buf_GND_6003), + .DPRA3(com_cmm_u_cmm_errman_cfg_hdr_buf_GND_6003), + .SPO(NLW_com_cmm_u_cmm_errman_cfg_hdr_buf_lutram_data_I_26_SPO_UNCONNECTED), + .WE(com_cmm_u_cmm_errman_reg_incr_cplu_5852) + ); + RAM16X1D com_cmm_u_cmm_errman_cfg_hdr_buf_lutram_data_I_27 ( + .DPO(com_cmm_u_cmm_errman_cfg_hdr_buf_lutram_data[19]), + .WCLK(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_reg_cfg_wr_hdr[19]), + .A0(com_cmm_u_cmm_errman_reg_cfg_wp[0]), + .A1(com_cmm_u_cmm_errman_reg_cfg_wp[1]), + .A2(com_cmm_u_cmm_errman_cfg_hdr_buf_GND_6003), + .A3(com_cmm_u_cmm_errman_cfg_hdr_buf_GND_6003), + .DPRA0(com_cmm_u_cmm_errman_reg_cfg_rp[0]), + .DPRA1(com_cmm_u_cmm_errman_reg_cfg_rp[1]), + .DPRA2(com_cmm_u_cmm_errman_cfg_hdr_buf_GND_6003), + .DPRA3(com_cmm_u_cmm_errman_cfg_hdr_buf_GND_6003), + .SPO(NLW_com_cmm_u_cmm_errman_cfg_hdr_buf_lutram_data_I_27_SPO_UNCONNECTED), + .WE(com_cmm_u_cmm_errman_reg_incr_cplu_5852) + ); + RAM16X1D com_cmm_u_cmm_errman_cfg_hdr_buf_lutram_data_I_28 ( + .DPO(com_cmm_u_cmm_errman_cfg_hdr_buf_lutram_data[6]), + .WCLK(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_reg_cfg_wr_hdr[6]), + .A0(com_cmm_u_cmm_errman_reg_cfg_wp[0]), + .A1(com_cmm_u_cmm_errman_reg_cfg_wp[1]), + .A2(com_cmm_u_cmm_errman_cfg_hdr_buf_GND_6003), + .A3(com_cmm_u_cmm_errman_cfg_hdr_buf_GND_6003), + .DPRA0(com_cmm_u_cmm_errman_reg_cfg_rp[0]), + .DPRA1(com_cmm_u_cmm_errman_reg_cfg_rp[1]), + .DPRA2(com_cmm_u_cmm_errman_cfg_hdr_buf_GND_6003), + .DPRA3(com_cmm_u_cmm_errman_cfg_hdr_buf_GND_6003), + .SPO(NLW_com_cmm_u_cmm_errman_cfg_hdr_buf_lutram_data_I_28_SPO_UNCONNECTED), + .WE(com_cmm_u_cmm_errman_reg_incr_cplu_5852) + ); + RAM16X1D com_cmm_u_cmm_errman_cfg_hdr_buf_lutram_data_I_29 ( + .DPO(com_cmm_u_cmm_errman_cfg_hdr_buf_lutram_data[11]), + .WCLK(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_reg_cfg_wr_hdr[11]), + .A0(com_cmm_u_cmm_errman_reg_cfg_wp[0]), + .A1(com_cmm_u_cmm_errman_reg_cfg_wp[1]), + .A2(com_cmm_u_cmm_errman_cfg_hdr_buf_GND_6003), + .A3(com_cmm_u_cmm_errman_cfg_hdr_buf_GND_6003), + .DPRA0(com_cmm_u_cmm_errman_reg_cfg_rp[0]), + .DPRA1(com_cmm_u_cmm_errman_reg_cfg_rp[1]), + .DPRA2(com_cmm_u_cmm_errman_cfg_hdr_buf_GND_6003), + .DPRA3(com_cmm_u_cmm_errman_cfg_hdr_buf_GND_6003), + .SPO(NLW_com_cmm_u_cmm_errman_cfg_hdr_buf_lutram_data_I_29_SPO_UNCONNECTED), + .WE(com_cmm_u_cmm_errman_reg_incr_cplu_5852) + ); + RAM16X1D com_cmm_u_cmm_errman_cfg_hdr_buf_lutram_data_I_30 ( + .DPO(com_cmm_u_cmm_errman_cfg_hdr_buf_lutram_data[24]), + .WCLK(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_reg_cfg_wr_hdr[24]), + .A0(com_cmm_u_cmm_errman_reg_cfg_wp[0]), + .A1(com_cmm_u_cmm_errman_reg_cfg_wp[1]), + .A2(com_cmm_u_cmm_errman_cfg_hdr_buf_GND_6003), + .A3(com_cmm_u_cmm_errman_cfg_hdr_buf_GND_6003), + .DPRA0(com_cmm_u_cmm_errman_reg_cfg_rp[0]), + .DPRA1(com_cmm_u_cmm_errman_reg_cfg_rp[1]), + .DPRA2(com_cmm_u_cmm_errman_cfg_hdr_buf_GND_6003), + .DPRA3(com_cmm_u_cmm_errman_cfg_hdr_buf_GND_6003), + .SPO(NLW_com_cmm_u_cmm_errman_cfg_hdr_buf_lutram_data_I_30_SPO_UNCONNECTED), + .WE(com_cmm_u_cmm_errman_reg_incr_cplu_5852) + ); + RAM16X1D com_cmm_u_cmm_errman_cfg_hdr_buf_lutram_data_I_31 ( + .DPO(com_cmm_u_cmm_errman_cfg_hdr_buf_lutram_data[39]), + .WCLK(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_reg_cfg_wr_hdr[39]), + .A0(com_cmm_u_cmm_errman_reg_cfg_wp[0]), + .A1(com_cmm_u_cmm_errman_reg_cfg_wp[1]), + .A2(com_cmm_u_cmm_errman_cfg_hdr_buf_GND_6003), + .A3(com_cmm_u_cmm_errman_cfg_hdr_buf_GND_6003), + .DPRA0(com_cmm_u_cmm_errman_reg_cfg_rp[0]), + .DPRA1(com_cmm_u_cmm_errman_reg_cfg_rp[1]), + .DPRA2(com_cmm_u_cmm_errman_cfg_hdr_buf_GND_6003), + .DPRA3(com_cmm_u_cmm_errman_cfg_hdr_buf_GND_6003), + .SPO(NLW_com_cmm_u_cmm_errman_cfg_hdr_buf_lutram_data_I_31_SPO_UNCONNECTED), + .WE(com_cmm_u_cmm_errman_reg_incr_cplu_5852) + ); + RAM16X1D com_cmm_u_cmm_errman_cfg_hdr_buf_lutram_data_I_32 ( + .DPO(com_cmm_u_cmm_errman_cfg_hdr_buf_lutram_data[12]), + .WCLK(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_reg_cfg_wr_hdr[12]), + .A0(com_cmm_u_cmm_errman_reg_cfg_wp[0]), + .A1(com_cmm_u_cmm_errman_reg_cfg_wp[1]), + .A2(com_cmm_u_cmm_errman_cfg_hdr_buf_GND_6003), + .A3(com_cmm_u_cmm_errman_cfg_hdr_buf_GND_6003), + .DPRA0(com_cmm_u_cmm_errman_reg_cfg_rp[0]), + .DPRA1(com_cmm_u_cmm_errman_reg_cfg_rp[1]), + .DPRA2(com_cmm_u_cmm_errman_cfg_hdr_buf_GND_6003), + .DPRA3(com_cmm_u_cmm_errman_cfg_hdr_buf_GND_6003), + .SPO(NLW_com_cmm_u_cmm_errman_cfg_hdr_buf_lutram_data_I_32_SPO_UNCONNECTED), + .WE(com_cmm_u_cmm_errman_reg_incr_cplu_5852) + ); + RAM16X1D com_cmm_u_cmm_errman_cfg_hdr_buf_lutram_data_I_33 ( + .DPO(com_cmm_u_cmm_errman_cfg_hdr_buf_lutram_data[25]), + .WCLK(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_reg_cfg_wr_hdr[25]), + .A0(com_cmm_u_cmm_errman_reg_cfg_wp[0]), + .A1(com_cmm_u_cmm_errman_reg_cfg_wp[1]), + .A2(com_cmm_u_cmm_errman_cfg_hdr_buf_GND_6003), + .A3(com_cmm_u_cmm_errman_cfg_hdr_buf_GND_6003), + .DPRA0(com_cmm_u_cmm_errman_reg_cfg_rp[0]), + .DPRA1(com_cmm_u_cmm_errman_reg_cfg_rp[1]), + .DPRA2(com_cmm_u_cmm_errman_cfg_hdr_buf_GND_6003), + .DPRA3(com_cmm_u_cmm_errman_cfg_hdr_buf_GND_6003), + .SPO(NLW_com_cmm_u_cmm_errman_cfg_hdr_buf_lutram_data_I_33_SPO_UNCONNECTED), + .WE(com_cmm_u_cmm_errman_reg_incr_cplu_5852) + ); + RAM16X1D com_cmm_u_cmm_errman_cfg_hdr_buf_lutram_data_I_34 ( + .DPO(com_cmm_u_cmm_errman_cfg_hdr_buf_lutram_data[38]), + .WCLK(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_reg_cfg_wr_hdr[38]), + .A0(com_cmm_u_cmm_errman_reg_cfg_wp[0]), + .A1(com_cmm_u_cmm_errman_reg_cfg_wp[1]), + .A2(com_cmm_u_cmm_errman_cfg_hdr_buf_GND_6003), + .A3(com_cmm_u_cmm_errman_cfg_hdr_buf_GND_6003), + .DPRA0(com_cmm_u_cmm_errman_reg_cfg_rp[0]), + .DPRA1(com_cmm_u_cmm_errman_reg_cfg_rp[1]), + .DPRA2(com_cmm_u_cmm_errman_cfg_hdr_buf_GND_6003), + .DPRA3(com_cmm_u_cmm_errman_cfg_hdr_buf_GND_6003), + .SPO(NLW_com_cmm_u_cmm_errman_cfg_hdr_buf_lutram_data_I_34_SPO_UNCONNECTED), + .WE(com_cmm_u_cmm_errman_reg_incr_cplu_5852) + ); + RAM16X1D com_cmm_u_cmm_errman_cfg_hdr_buf_lutram_data_I_35 ( + .DPO(com_cmm_u_cmm_errman_cfg_hdr_buf_lutram_data[13]), + .WCLK(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_reg_cfg_wr_hdr[13]), + .A0(com_cmm_u_cmm_errman_reg_cfg_wp[0]), + .A1(com_cmm_u_cmm_errman_reg_cfg_wp[1]), + .A2(com_cmm_u_cmm_errman_cfg_hdr_buf_GND_6003), + .A3(com_cmm_u_cmm_errman_cfg_hdr_buf_GND_6003), + .DPRA0(com_cmm_u_cmm_errman_reg_cfg_rp[0]), + .DPRA1(com_cmm_u_cmm_errman_reg_cfg_rp[1]), + .DPRA2(com_cmm_u_cmm_errman_cfg_hdr_buf_GND_6003), + .DPRA3(com_cmm_u_cmm_errman_cfg_hdr_buf_GND_6003), + .SPO(NLW_com_cmm_u_cmm_errman_cfg_hdr_buf_lutram_data_I_35_SPO_UNCONNECTED), + .WE(com_cmm_u_cmm_errman_reg_incr_cplu_5852) + ); + RAM16X1D com_cmm_u_cmm_errman_cfg_hdr_buf_lutram_data_I_36 ( + .DPO(com_cmm_u_cmm_errman_cfg_hdr_buf_lutram_data[26]), + .WCLK(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_reg_cfg_wr_hdr[26]), + .A0(com_cmm_u_cmm_errman_reg_cfg_wp[0]), + .A1(com_cmm_u_cmm_errman_reg_cfg_wp[1]), + .A2(com_cmm_u_cmm_errman_cfg_hdr_buf_GND_6003), + .A3(com_cmm_u_cmm_errman_cfg_hdr_buf_GND_6003), + .DPRA0(com_cmm_u_cmm_errman_reg_cfg_rp[0]), + .DPRA1(com_cmm_u_cmm_errman_reg_cfg_rp[1]), + .DPRA2(com_cmm_u_cmm_errman_cfg_hdr_buf_GND_6003), + .DPRA3(com_cmm_u_cmm_errman_cfg_hdr_buf_GND_6003), + .SPO(NLW_com_cmm_u_cmm_errman_cfg_hdr_buf_lutram_data_I_36_SPO_UNCONNECTED), + .WE(com_cmm_u_cmm_errman_reg_incr_cplu_5852) + ); + RAM16X1D com_cmm_u_cmm_errman_cfg_hdr_buf_lutram_data_I_37 ( + .DPO(com_cmm_u_cmm_errman_cfg_hdr_buf_lutram_data[22]), + .WCLK(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_reg_cfg_wr_hdr[22]), + .A0(com_cmm_u_cmm_errman_reg_cfg_wp[0]), + .A1(com_cmm_u_cmm_errman_reg_cfg_wp[1]), + .A2(com_cmm_u_cmm_errman_cfg_hdr_buf_GND_6003), + .A3(com_cmm_u_cmm_errman_cfg_hdr_buf_GND_6003), + .DPRA0(com_cmm_u_cmm_errman_reg_cfg_rp[0]), + .DPRA1(com_cmm_u_cmm_errman_reg_cfg_rp[1]), + .DPRA2(com_cmm_u_cmm_errman_cfg_hdr_buf_GND_6003), + .DPRA3(com_cmm_u_cmm_errman_cfg_hdr_buf_GND_6003), + .SPO(NLW_com_cmm_u_cmm_errman_cfg_hdr_buf_lutram_data_I_37_SPO_UNCONNECTED), + .WE(com_cmm_u_cmm_errman_reg_incr_cplu_5852) + ); + RAM16X1D com_cmm_u_cmm_errman_cfg_hdr_buf_lutram_data_I_38 ( + .DPO(com_cmm_u_cmm_errman_cfg_hdr_buf_lutram_data[49]), + .WCLK(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_reg_cfg_wr_hdr[49]), + .A0(com_cmm_u_cmm_errman_reg_cfg_wp[0]), + .A1(com_cmm_u_cmm_errman_reg_cfg_wp[1]), + .A2(com_cmm_u_cmm_errman_cfg_hdr_buf_GND_6003), + .A3(com_cmm_u_cmm_errman_cfg_hdr_buf_GND_6003), + .DPRA0(com_cmm_u_cmm_errman_reg_cfg_rp[0]), + .DPRA1(com_cmm_u_cmm_errman_reg_cfg_rp[1]), + .DPRA2(com_cmm_u_cmm_errman_cfg_hdr_buf_GND_6003), + .DPRA3(com_cmm_u_cmm_errman_cfg_hdr_buf_GND_6003), + .SPO(NLW_com_cmm_u_cmm_errman_cfg_hdr_buf_lutram_data_I_38_SPO_UNCONNECTED), + .WE(com_cmm_u_cmm_errman_reg_incr_cplu_5852) + ); + RAM16X1D com_cmm_u_cmm_errman_cfg_hdr_buf_lutram_data_I_39 ( + .DPO(com_cmm_u_cmm_errman_cfg_hdr_buf_lutram_data[23]), + .WCLK(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_reg_cfg_wr_hdr[23]), + .A0(com_cmm_u_cmm_errman_reg_cfg_wp[0]), + .A1(com_cmm_u_cmm_errman_reg_cfg_wp[1]), + .A2(com_cmm_u_cmm_errman_cfg_hdr_buf_GND_6003), + .A3(com_cmm_u_cmm_errman_cfg_hdr_buf_GND_6003), + .DPRA0(com_cmm_u_cmm_errman_reg_cfg_rp[0]), + .DPRA1(com_cmm_u_cmm_errman_reg_cfg_rp[1]), + .DPRA2(com_cmm_u_cmm_errman_cfg_hdr_buf_GND_6003), + .DPRA3(com_cmm_u_cmm_errman_cfg_hdr_buf_GND_6003), + .SPO(NLW_com_cmm_u_cmm_errman_cfg_hdr_buf_lutram_data_I_39_SPO_UNCONNECTED), + .WE(com_cmm_u_cmm_errman_reg_incr_cplu_5852) + ); + RAM16X1D com_cmm_u_cmm_errman_cfg_hdr_buf_lutram_data_I_40 ( + .DPO(com_cmm_u_cmm_errman_cfg_hdr_buf_lutram_data[36]), + .WCLK(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_reg_cfg_wr_hdr[36]), + .A0(com_cmm_u_cmm_errman_reg_cfg_wp[0]), + .A1(com_cmm_u_cmm_errman_reg_cfg_wp[1]), + .A2(com_cmm_u_cmm_errman_cfg_hdr_buf_GND_6003), + .A3(com_cmm_u_cmm_errman_cfg_hdr_buf_GND_6003), + .DPRA0(com_cmm_u_cmm_errman_reg_cfg_rp[0]), + .DPRA1(com_cmm_u_cmm_errman_reg_cfg_rp[1]), + .DPRA2(com_cmm_u_cmm_errman_cfg_hdr_buf_GND_6003), + .DPRA3(com_cmm_u_cmm_errman_cfg_hdr_buf_GND_6003), + .SPO(NLW_com_cmm_u_cmm_errman_cfg_hdr_buf_lutram_data_I_40_SPO_UNCONNECTED), + .WE(com_cmm_u_cmm_errman_reg_incr_cplu_5852) + ); + RAM16X1D com_cmm_u_cmm_errman_cfg_hdr_buf_lutram_data_I_41 ( + .DPO(com_cmm_u_cmm_errman_cfg_hdr_buf_lutram_data[10]), + .WCLK(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_reg_cfg_wr_hdr[10]), + .A0(com_cmm_u_cmm_errman_reg_cfg_wp[0]), + .A1(com_cmm_u_cmm_errman_reg_cfg_wp[1]), + .A2(com_cmm_u_cmm_errman_cfg_hdr_buf_GND_6003), + .A3(com_cmm_u_cmm_errman_cfg_hdr_buf_GND_6003), + .DPRA0(com_cmm_u_cmm_errman_reg_cfg_rp[0]), + .DPRA1(com_cmm_u_cmm_errman_reg_cfg_rp[1]), + .DPRA2(com_cmm_u_cmm_errman_cfg_hdr_buf_GND_6003), + .DPRA3(com_cmm_u_cmm_errman_cfg_hdr_buf_GND_6003), + .SPO(NLW_com_cmm_u_cmm_errman_cfg_hdr_buf_lutram_data_I_41_SPO_UNCONNECTED), + .WE(com_cmm_u_cmm_errman_reg_incr_cplu_5852) + ); + RAM16X1D com_cmm_u_cmm_errman_cfg_hdr_buf_lutram_data_I_42 ( + .DPO(com_cmm_u_cmm_errman_cfg_hdr_buf_lutram_data[31]), + .WCLK(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_reg_cfg_wr_hdr[31]), + .A0(com_cmm_u_cmm_errman_reg_cfg_wp[0]), + .A1(com_cmm_u_cmm_errman_reg_cfg_wp[1]), + .A2(com_cmm_u_cmm_errman_cfg_hdr_buf_GND_6003), + .A3(com_cmm_u_cmm_errman_cfg_hdr_buf_GND_6003), + .DPRA0(com_cmm_u_cmm_errman_reg_cfg_rp[0]), + .DPRA1(com_cmm_u_cmm_errman_reg_cfg_rp[1]), + .DPRA2(com_cmm_u_cmm_errman_cfg_hdr_buf_GND_6003), + .DPRA3(com_cmm_u_cmm_errman_cfg_hdr_buf_GND_6003), + .SPO(NLW_com_cmm_u_cmm_errman_cfg_hdr_buf_lutram_data_I_42_SPO_UNCONNECTED), + .WE(com_cmm_u_cmm_errman_reg_incr_cplu_5852) + ); + RAM16X1D com_cmm_u_cmm_errman_cfg_hdr_buf_lutram_data_I_43 ( + .DPO(com_cmm_u_cmm_errman_cfg_hdr_buf_lutram_data[44]), + .WCLK(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_reg_cfg_wr_hdr[44]), + .A0(com_cmm_u_cmm_errman_reg_cfg_wp[0]), + .A1(com_cmm_u_cmm_errman_reg_cfg_wp[1]), + .A2(com_cmm_u_cmm_errman_cfg_hdr_buf_GND_6003), + .A3(com_cmm_u_cmm_errman_cfg_hdr_buf_GND_6003), + .DPRA0(com_cmm_u_cmm_errman_reg_cfg_rp[0]), + .DPRA1(com_cmm_u_cmm_errman_reg_cfg_rp[1]), + .DPRA2(com_cmm_u_cmm_errman_cfg_hdr_buf_GND_6003), + .DPRA3(com_cmm_u_cmm_errman_cfg_hdr_buf_GND_6003), + .SPO(NLW_com_cmm_u_cmm_errman_cfg_hdr_buf_lutram_data_I_43_SPO_UNCONNECTED), + .WE(com_cmm_u_cmm_errman_reg_incr_cplu_5852) + ); + RAM16X1D com_cmm_u_cmm_errman_cfg_hdr_buf_lutram_data_I_44 ( + .DPO(com_cmm_u_cmm_errman_cfg_hdr_buf_lutram_data[17]), + .WCLK(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_reg_cfg_wr_hdr[17]), + .A0(com_cmm_u_cmm_errman_reg_cfg_wp[0]), + .A1(com_cmm_u_cmm_errman_reg_cfg_wp[1]), + .A2(com_cmm_u_cmm_errman_cfg_hdr_buf_GND_6003), + .A3(com_cmm_u_cmm_errman_cfg_hdr_buf_GND_6003), + .DPRA0(com_cmm_u_cmm_errman_reg_cfg_rp[0]), + .DPRA1(com_cmm_u_cmm_errman_reg_cfg_rp[1]), + .DPRA2(com_cmm_u_cmm_errman_cfg_hdr_buf_GND_6003), + .DPRA3(com_cmm_u_cmm_errman_cfg_hdr_buf_GND_6003), + .SPO(NLW_com_cmm_u_cmm_errman_cfg_hdr_buf_lutram_data_I_44_SPO_UNCONNECTED), + .WE(com_cmm_u_cmm_errman_reg_incr_cplu_5852) + ); + RAM16X1D com_cmm_u_cmm_errman_cfg_hdr_buf_lutram_data_I_45 ( + .DPO(com_cmm_u_cmm_errman_cfg_hdr_buf_lutram_data[21]), + .WCLK(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_reg_cfg_wr_hdr[21]), + .A0(com_cmm_u_cmm_errman_reg_cfg_wp[0]), + .A1(com_cmm_u_cmm_errman_reg_cfg_wp[1]), + .A2(com_cmm_u_cmm_errman_cfg_hdr_buf_GND_6003), + .A3(com_cmm_u_cmm_errman_cfg_hdr_buf_GND_6003), + .DPRA0(com_cmm_u_cmm_errman_reg_cfg_rp[0]), + .DPRA1(com_cmm_u_cmm_errman_reg_cfg_rp[1]), + .DPRA2(com_cmm_u_cmm_errman_cfg_hdr_buf_GND_6003), + .DPRA3(com_cmm_u_cmm_errman_cfg_hdr_buf_GND_6003), + .SPO(NLW_com_cmm_u_cmm_errman_cfg_hdr_buf_lutram_data_I_45_SPO_UNCONNECTED), + .WE(com_cmm_u_cmm_errman_reg_incr_cplu_5852) + ); + RAM16X1D com_cmm_u_cmm_errman_cfg_hdr_buf_lutram_data_I_46 ( + .DPO(com_cmm_u_cmm_errman_cfg_hdr_buf_lutram_data[34]), + .WCLK(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_reg_cfg_wr_hdr[34]), + .A0(com_cmm_u_cmm_errman_reg_cfg_wp[0]), + .A1(com_cmm_u_cmm_errman_reg_cfg_wp[1]), + .A2(com_cmm_u_cmm_errman_cfg_hdr_buf_GND_6003), + .A3(com_cmm_u_cmm_errman_cfg_hdr_buf_GND_6003), + .DPRA0(com_cmm_u_cmm_errman_reg_cfg_rp[0]), + .DPRA1(com_cmm_u_cmm_errman_reg_cfg_rp[1]), + .DPRA2(com_cmm_u_cmm_errman_cfg_hdr_buf_GND_6003), + .DPRA3(com_cmm_u_cmm_errman_cfg_hdr_buf_GND_6003), + .SPO(NLW_com_cmm_u_cmm_errman_cfg_hdr_buf_lutram_data_I_46_SPO_UNCONNECTED), + .WE(com_cmm_u_cmm_errman_reg_incr_cplu_5852) + ); + RAM16X1D com_cmm_u_cmm_errman_cfg_hdr_buf_lutram_data_I_47 ( + .DPO(com_cmm_u_cmm_errman_cfg_hdr_buf_lutram_data[47]), + .WCLK(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_reg_cfg_wr_hdr[47]), + .A0(com_cmm_u_cmm_errman_reg_cfg_wp[0]), + .A1(com_cmm_u_cmm_errman_reg_cfg_wp[1]), + .A2(com_cmm_u_cmm_errman_cfg_hdr_buf_GND_6003), + .A3(com_cmm_u_cmm_errman_cfg_hdr_buf_GND_6003), + .DPRA0(com_cmm_u_cmm_errman_reg_cfg_rp[0]), + .DPRA1(com_cmm_u_cmm_errman_reg_cfg_rp[1]), + .DPRA2(com_cmm_u_cmm_errman_cfg_hdr_buf_GND_6003), + .DPRA3(com_cmm_u_cmm_errman_cfg_hdr_buf_GND_6003), + .SPO(NLW_com_cmm_u_cmm_errman_cfg_hdr_buf_lutram_data_I_47_SPO_UNCONNECTED), + .WE(com_cmm_u_cmm_errman_reg_incr_cplu_5852) + ); + RAM16X1D com_cmm_u_cmm_errman_cfg_hdr_buf_lutram_data_I_48 ( + .DPO(com_cmm_u_cmm_errman_cfg_hdr_buf_lutram_data[35]), + .WCLK(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_reg_cfg_wr_hdr[35]), + .A0(com_cmm_u_cmm_errman_reg_cfg_wp[0]), + .A1(com_cmm_u_cmm_errman_reg_cfg_wp[1]), + .A2(com_cmm_u_cmm_errman_cfg_hdr_buf_GND_6003), + .A3(com_cmm_u_cmm_errman_cfg_hdr_buf_GND_6003), + .DPRA0(com_cmm_u_cmm_errman_reg_cfg_rp[0]), + .DPRA1(com_cmm_u_cmm_errman_reg_cfg_rp[1]), + .DPRA2(com_cmm_u_cmm_errman_cfg_hdr_buf_GND_6003), + .DPRA3(com_cmm_u_cmm_errman_cfg_hdr_buf_GND_6003), + .SPO(NLW_com_cmm_u_cmm_errman_cfg_hdr_buf_lutram_data_I_48_SPO_UNCONNECTED), + .WE(com_cmm_u_cmm_errman_reg_incr_cplu_5852) + ); + RAM16X1D com_cmm_u_cmm_errman_cfg_hdr_buf_lutram_data_I_49 ( + .DPO(com_cmm_u_cmm_errman_cfg_hdr_buf_lutram_data[48]), + .WCLK(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_reg_cfg_wr_hdr[48]), + .A0(com_cmm_u_cmm_errman_reg_cfg_wp[0]), + .A1(com_cmm_u_cmm_errman_reg_cfg_wp[1]), + .A2(com_cmm_u_cmm_errman_cfg_hdr_buf_GND_6003), + .A3(com_cmm_u_cmm_errman_cfg_hdr_buf_GND_6003), + .DPRA0(com_cmm_u_cmm_errman_reg_cfg_rp[0]), + .DPRA1(com_cmm_u_cmm_errman_reg_cfg_rp[1]), + .DPRA2(com_cmm_u_cmm_errman_cfg_hdr_buf_GND_6003), + .DPRA3(com_cmm_u_cmm_errman_cfg_hdr_buf_GND_6003), + .SPO(NLW_com_cmm_u_cmm_errman_cfg_hdr_buf_lutram_data_I_49_SPO_UNCONNECTED), + .WE(com_cmm_u_cmm_errman_reg_incr_cplu_5852) + ); + RAM16X1D com_cmm_u_cmm_errman_cfg_hdr_buf_lutram_data_I_50 ( + .DPO(com_cmm_u_cmm_errman_cfg_hdr_buf_lutram_data[37]), + .WCLK(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_reg_cfg_wr_hdr[37]), + .A0(com_cmm_u_cmm_errman_reg_cfg_wp[0]), + .A1(com_cmm_u_cmm_errman_reg_cfg_wp[1]), + .A2(com_cmm_u_cmm_errman_cfg_hdr_buf_GND_6003), + .A3(com_cmm_u_cmm_errman_cfg_hdr_buf_GND_6003), + .DPRA0(com_cmm_u_cmm_errman_reg_cfg_rp[0]), + .DPRA1(com_cmm_u_cmm_errman_reg_cfg_rp[1]), + .DPRA2(com_cmm_u_cmm_errman_cfg_hdr_buf_GND_6003), + .DPRA3(com_cmm_u_cmm_errman_cfg_hdr_buf_GND_6003), + .SPO(NLW_com_cmm_u_cmm_errman_cfg_hdr_buf_lutram_data_I_50_SPO_UNCONNECTED), + .WE(com_cmm_u_cmm_errman_reg_incr_cplu_5852) + ); + FDC com_cmm_u_cmm_errman_cfg_hdr_buf_reg_rdata_3_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_cfg_hdr_buf_lutram_data[3]), + .Q(com_cmm_u_cmm_errman_cfg_rd_hdr[3]), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_errman_cfg_hdr_buf_reg_rdata_2_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_cfg_hdr_buf_lutram_data[2]), + .Q(com_cmm_u_cmm_errman_cfg_rd_hdr[2]), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_errman_cfg_hdr_buf_reg_rdata_1_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_cfg_hdr_buf_lutram_data[1]), + .Q(com_cmm_u_cmm_errman_cfg_rd_hdr[1]), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_errman_cfg_hdr_buf_reg_rdata_0_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_cfg_hdr_buf_lutram_data[0]), + .Q(com_cmm_u_cmm_errman_cfg_rd_hdr[0]), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_errman_cfg_hdr_buf_reg_rdata_18_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_cfg_hdr_buf_lutram_data[18]), + .Q(com_cmm_u_cmm_errman_cfg_rd_hdr[18]), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_errman_cfg_hdr_buf_reg_rdata_17_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_cfg_hdr_buf_lutram_data[17]), + .Q(com_cmm_u_cmm_errman_cfg_rd_hdr[17]), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_errman_cfg_hdr_buf_reg_rdata_16_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_cfg_hdr_buf_lutram_data[16]), + .Q(com_cmm_u_cmm_errman_cfg_rd_hdr[16]), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_errman_cfg_hdr_buf_reg_rdata_15_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_cfg_hdr_buf_lutram_data[15]), + .Q(com_cmm_u_cmm_errman_cfg_rd_hdr[15]), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_errman_cfg_hdr_buf_reg_rdata_14_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_cfg_hdr_buf_lutram_data[14]), + .Q(com_cmm_u_cmm_errman_cfg_rd_hdr[14]), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_errman_cfg_hdr_buf_reg_rdata_13_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_cfg_hdr_buf_lutram_data[13]), + .Q(com_cmm_u_cmm_errman_cfg_rd_hdr[13]), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_errman_cfg_hdr_buf_reg_rdata_12_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_cfg_hdr_buf_lutram_data[12]), + .Q(com_cmm_u_cmm_errman_cfg_rd_hdr[12]), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_errman_cfg_hdr_buf_reg_rdata_11_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_cfg_hdr_buf_lutram_data[11]), + .Q(com_cmm_u_cmm_errman_cfg_rd_hdr[11]), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_errman_cfg_hdr_buf_reg_rdata_10_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_cfg_hdr_buf_lutram_data[10]), + .Q(com_cmm_u_cmm_errman_cfg_rd_hdr[10]), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_errman_cfg_hdr_buf_reg_rdata_9_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_cfg_hdr_buf_lutram_data[9]), + .Q(com_cmm_u_cmm_errman_cfg_rd_hdr[9]), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_errman_cfg_hdr_buf_reg_rdata_8_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_cfg_hdr_buf_lutram_data[8]), + .Q(com_cmm_u_cmm_errman_cfg_rd_hdr[8]), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_errman_cfg_hdr_buf_reg_rdata_7_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_cfg_hdr_buf_lutram_data[7]), + .Q(com_cmm_u_cmm_errman_cfg_rd_hdr[7]), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_errman_cfg_hdr_buf_reg_rdata_6_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_cfg_hdr_buf_lutram_data[6]), + .Q(com_cmm_u_cmm_errman_cfg_rd_hdr[6]), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_errman_cfg_hdr_buf_reg_rdata_5_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_cfg_hdr_buf_lutram_data[5]), + .Q(com_cmm_u_cmm_errman_cfg_rd_hdr[5]), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_errman_cfg_hdr_buf_reg_rdata_4_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_cfg_hdr_buf_lutram_data[4]), + .Q(com_cmm_u_cmm_errman_cfg_rd_hdr[4]), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_errman_cfg_hdr_buf_reg_rdata_33_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_cfg_hdr_buf_lutram_data[33]), + .Q(com_cmm_u_cmm_errman_cfg_rd_hdr[33]), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_errman_cfg_hdr_buf_reg_rdata_32_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_cfg_hdr_buf_lutram_data[32]), + .Q(com_cmm_u_cmm_errman_cfg_rd_hdr[32]), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_errman_cfg_hdr_buf_reg_rdata_31_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_cfg_hdr_buf_lutram_data[31]), + .Q(com_cmm_u_cmm_errman_cfg_rd_hdr[31]), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_errman_cfg_hdr_buf_reg_rdata_30_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_cfg_hdr_buf_lutram_data[30]), + .Q(com_cmm_u_cmm_errman_cfg_rd_hdr[30]), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_errman_cfg_hdr_buf_reg_rdata_29_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_cfg_hdr_buf_lutram_data[29]), + .Q(com_cmm_u_cmm_errman_cfg_rd_hdr[29]), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_errman_cfg_hdr_buf_reg_rdata_28_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_cfg_hdr_buf_lutram_data[28]), + .Q(com_cmm_u_cmm_errman_cfg_rd_hdr[28]), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_errman_cfg_hdr_buf_reg_rdata_27_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_cfg_hdr_buf_lutram_data[27]), + .Q(com_cmm_u_cmm_errman_cfg_rd_hdr[27]), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_errman_cfg_hdr_buf_reg_rdata_26_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_cfg_hdr_buf_lutram_data[26]), + .Q(com_cmm_u_cmm_errman_cfg_rd_hdr[26]), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_errman_cfg_hdr_buf_reg_rdata_25_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_cfg_hdr_buf_lutram_data[25]), + .Q(com_cmm_u_cmm_errman_cfg_rd_hdr[25]), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_errman_cfg_hdr_buf_reg_rdata_24_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_cfg_hdr_buf_lutram_data[24]), + .Q(com_cmm_u_cmm_errman_cfg_rd_hdr[24]), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_errman_cfg_hdr_buf_reg_rdata_23_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_cfg_hdr_buf_lutram_data[23]), + .Q(com_cmm_u_cmm_errman_cfg_rd_hdr[23]), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_errman_cfg_hdr_buf_reg_rdata_22_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_cfg_hdr_buf_lutram_data[22]), + .Q(com_cmm_u_cmm_errman_cfg_rd_hdr[22]), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_errman_cfg_hdr_buf_reg_rdata_21_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_cfg_hdr_buf_lutram_data[21]), + .Q(com_cmm_u_cmm_errman_cfg_rd_hdr[21]), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_errman_cfg_hdr_buf_reg_rdata_20_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_cfg_hdr_buf_lutram_data[20]), + .Q(com_cmm_u_cmm_errman_cfg_rd_hdr[20]), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_errman_cfg_hdr_buf_reg_rdata_19_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_cfg_hdr_buf_lutram_data[19]), + .Q(com_cmm_u_cmm_errman_cfg_rd_hdr[19]), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_errman_cfg_hdr_buf_reg_rdata_48_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_cfg_hdr_buf_lutram_data[48]), + .Q(com_cmm_u_cmm_errman_cfg_rd_hdr[48]), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_errman_cfg_hdr_buf_reg_rdata_47_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_cfg_hdr_buf_lutram_data[47]), + .Q(com_cmm_u_cmm_errman_cfg_rd_hdr[47]), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_errman_cfg_hdr_buf_reg_rdata_46_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_cfg_hdr_buf_lutram_data[46]), + .Q(com_cmm_u_cmm_errman_cfg_rd_hdr[46]), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_errman_cfg_hdr_buf_reg_rdata_45_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_cfg_hdr_buf_lutram_data[45]), + .Q(com_cmm_u_cmm_errman_cfg_rd_hdr[45]), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_errman_cfg_hdr_buf_reg_rdata_44_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_cfg_hdr_buf_lutram_data[44]), + .Q(com_cmm_u_cmm_errman_cfg_rd_hdr[44]), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_errman_cfg_hdr_buf_reg_rdata_43_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_cfg_hdr_buf_lutram_data[43]), + .Q(com_cmm_u_cmm_errman_cfg_rd_hdr[43]), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_errman_cfg_hdr_buf_reg_rdata_42_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_cfg_hdr_buf_lutram_data[42]), + .Q(com_cmm_u_cmm_errman_cfg_rd_hdr[42]), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_errman_cfg_hdr_buf_reg_rdata_41_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_cfg_hdr_buf_lutram_data[41]), + .Q(com_cmm_u_cmm_errman_cfg_rd_hdr[41]), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_errman_cfg_hdr_buf_reg_rdata_40_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_cfg_hdr_buf_lutram_data[40]), + .Q(com_cmm_u_cmm_errman_cfg_rd_hdr[40]), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_errman_cfg_hdr_buf_reg_rdata_39_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_cfg_hdr_buf_lutram_data[39]), + .Q(com_cmm_u_cmm_errman_cfg_rd_hdr[39]), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_errman_cfg_hdr_buf_reg_rdata_38_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_cfg_hdr_buf_lutram_data[38]), + .Q(com_cmm_u_cmm_errman_cfg_rd_hdr[38]), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_errman_cfg_hdr_buf_reg_rdata_37_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_cfg_hdr_buf_lutram_data[37]), + .Q(com_cmm_u_cmm_errman_cfg_rd_hdr[37]), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_errman_cfg_hdr_buf_reg_rdata_36_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_cfg_hdr_buf_lutram_data[36]), + .Q(com_cmm_u_cmm_errman_cfg_rd_hdr[36]), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_errman_cfg_hdr_buf_reg_rdata_35_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_cfg_hdr_buf_lutram_data[35]), + .Q(com_cmm_u_cmm_errman_cfg_rd_hdr[35]), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_errman_cfg_hdr_buf_reg_rdata_34_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_cfg_hdr_buf_lutram_data[34]), + .Q(com_cmm_u_cmm_errman_cfg_rd_hdr[34]), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_errman_cfg_hdr_buf_reg_rdata_49_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_errman_cfg_hdr_buf_lutram_data[49]), + .Q(com_cmm_u_cmm_errman_cfg_rd_hdr[49]), + .CLR(com_cmm_rst_351) + ); + VCC com_cmm_u_cmm_pm_VCC ( + .P(com_cmm_u_cmm_pm_VCC_6030) + ); + GND com_cmm_u_cmm_pm_GND ( + .G(com_cmm_u_cmm_pm_GND_6004) + ); + MUXCY_L com_cmm_u_cmm_pm_inactivity_timer_cry_0_ ( + .CI(com_cmm_u_cmm_pm_inactivity_timer24), + .DI(com_cmm_u_cmm_pm_GND_6004), + .LO(com_cmm_u_cmm_pm_inactivity_timer_cry[0]), + .S(com_cmm_u_cmm_pm_inactivity_timer_qxu[0]) + ); + XORCY com_cmm_u_cmm_pm_inactivity_timer_s_0_ ( + .CI(com_cmm_u_cmm_pm_inactivity_timer24), + .LI(com_cmm_u_cmm_pm_inactivity_timer_qxu[0]), + .O(com_cmm_u_cmm_pm_inactivity_timer_s[0]) + ); + MUXCY_L com_cmm_u_cmm_pm_inactivity_timer_cry_1_ ( + .CI(com_cmm_u_cmm_pm_inactivity_timer_cry[0]), + .DI(com_cmm_u_cmm_pm_GND_6004), + .LO(com_cmm_u_cmm_pm_inactivity_timer_cry[1]), + .S(com_cmm_u_cmm_pm_inactivity_timer_qxu[1]) + ); + XORCY com_cmm_u_cmm_pm_inactivity_timer_s_1_ ( + .CI(com_cmm_u_cmm_pm_inactivity_timer_cry[0]), + .LI(com_cmm_u_cmm_pm_inactivity_timer_qxu[1]), + .O(com_cmm_u_cmm_pm_inactivity_timer_s[1]) + ); + MUXCY_L com_cmm_u_cmm_pm_inactivity_timer_cry_2_ ( + .CI(com_cmm_u_cmm_pm_inactivity_timer_cry[1]), + .DI(com_cmm_u_cmm_pm_GND_6004), + .LO(com_cmm_u_cmm_pm_inactivity_timer_cry[2]), + .S(com_cmm_u_cmm_pm_inactivity_timer_qxu[2]) + ); + XORCY com_cmm_u_cmm_pm_inactivity_timer_s_2_ ( + .CI(com_cmm_u_cmm_pm_inactivity_timer_cry[1]), + .LI(com_cmm_u_cmm_pm_inactivity_timer_qxu[2]), + .O(com_cmm_u_cmm_pm_inactivity_timer_s[2]) + ); + MUXCY_L com_cmm_u_cmm_pm_inactivity_timer_cry_3_ ( + .CI(com_cmm_u_cmm_pm_inactivity_timer_cry[2]), + .DI(com_cmm_u_cmm_pm_GND_6004), + .LO(com_cmm_u_cmm_pm_inactivity_timer_cry[3]), + .S(com_cmm_u_cmm_pm_inactivity_timer_qxu[3]) + ); + XORCY com_cmm_u_cmm_pm_inactivity_timer_s_3_ ( + .CI(com_cmm_u_cmm_pm_inactivity_timer_cry[2]), + .LI(com_cmm_u_cmm_pm_inactivity_timer_qxu[3]), + .O(com_cmm_u_cmm_pm_inactivity_timer_s[3]) + ); + MUXCY_L com_cmm_u_cmm_pm_inactivity_timer_cry_4_ ( + .CI(com_cmm_u_cmm_pm_inactivity_timer_cry[3]), + .DI(com_cmm_u_cmm_pm_GND_6004), + .LO(com_cmm_u_cmm_pm_inactivity_timer_cry[4]), + .S(com_cmm_u_cmm_pm_inactivity_timer_qxu[4]) + ); + XORCY com_cmm_u_cmm_pm_inactivity_timer_s_4_ ( + .CI(com_cmm_u_cmm_pm_inactivity_timer_cry[3]), + .LI(com_cmm_u_cmm_pm_inactivity_timer_qxu[4]), + .O(com_cmm_u_cmm_pm_inactivity_timer_s[4]) + ); + MUXCY_L com_cmm_u_cmm_pm_inactivity_timer_cry_5_ ( + .CI(com_cmm_u_cmm_pm_inactivity_timer_cry[4]), + .DI(com_cmm_u_cmm_pm_GND_6004), + .LO(com_cmm_u_cmm_pm_inactivity_timer_cry[5]), + .S(com_cmm_u_cmm_pm_inactivity_timer_qxu[5]) + ); + XORCY com_cmm_u_cmm_pm_inactivity_timer_s_5_ ( + .CI(com_cmm_u_cmm_pm_inactivity_timer_cry[4]), + .LI(com_cmm_u_cmm_pm_inactivity_timer_qxu[5]), + .O(com_cmm_u_cmm_pm_inactivity_timer_s[5]) + ); + MUXCY_L com_cmm_u_cmm_pm_inactivity_timer_cry_6_ ( + .CI(com_cmm_u_cmm_pm_inactivity_timer_cry[5]), + .DI(com_cmm_u_cmm_pm_GND_6004), + .LO(com_cmm_u_cmm_pm_inactivity_timer_cry[6]), + .S(com_cmm_u_cmm_pm_inactivity_timer_qxu[6]) + ); + XORCY com_cmm_u_cmm_pm_inactivity_timer_s_6_ ( + .CI(com_cmm_u_cmm_pm_inactivity_timer_cry[5]), + .LI(com_cmm_u_cmm_pm_inactivity_timer_qxu[6]), + .O(com_cmm_u_cmm_pm_inactivity_timer_s[6]) + ); + MUXCY_L com_cmm_u_cmm_pm_inactivity_timer_cry_7_ ( + .CI(com_cmm_u_cmm_pm_inactivity_timer_cry[6]), + .DI(com_cmm_u_cmm_pm_GND_6004), + .LO(com_cmm_u_cmm_pm_inactivity_timer_cry[7]), + .S(com_cmm_u_cmm_pm_inactivity_timer_qxu[7]) + ); + XORCY com_cmm_u_cmm_pm_inactivity_timer_s_7_ ( + .CI(com_cmm_u_cmm_pm_inactivity_timer_cry[6]), + .LI(com_cmm_u_cmm_pm_inactivity_timer_qxu[7]), + .O(com_cmm_u_cmm_pm_inactivity_timer_s[7]) + ); + XORCY com_cmm_u_cmm_pm_inactivity_timer_s_8_ ( + .CI(com_cmm_u_cmm_pm_inactivity_timer_cry[7]), + .LI(com_cmm_u_cmm_pm_inactivity_timer_qxu[8]), + .O(com_cmm_u_cmm_pm_inactivity_timer_s[8]) + ); + defparam com_cmm_u_cmm_pm_st_pm_next_0_0_0_iv_1_i_0_0_0_a2_14_.INIT = 4'h8; + LUT2 com_cmm_u_cmm_pm_st_pm_next_0_0_0_iv_1_i_0_0_0_a2_14_ ( + .I0(com_st_pm_13_), + .I1(com_cmml_rpm_ra), + .O(com_cmm_u_cmm_pm_N_58679) + ); + defparam com_cmm_u_cmm_pm_st_pm_next_0_0_0_iv_1_i_0_0_0_a2_19_.INIT = 4'h8; + LUT2 com_cmm_u_cmm_pm_st_pm_next_0_0_0_iv_1_i_0_0_0_a2_19_ ( + .I0(com_cmm_u_cmm_pm_st_pm_18__6010), + .I1(com_cmml_suspend_ok), + .O(com_cmm_u_cmm_pm_N_58708) + ); + defparam com_cmm_u_cmm_pm_un1_cmmt_ppm_suspend_req_n_comb_0_sqmuxa_i_0_0_0_a2.INIT = 4'h8; + LUT2 com_cmm_u_cmm_pm_un1_cmmt_ppm_suspend_req_n_comb_0_sqmuxa_i_0_0_0_a2 ( + .I0(com_cmm_u_cmm_pm_cfg_pcie_link_state[0]), + .I1(com_cmmt_rpm_turn_off), + .O(com_cmm_u_cmm_pm_N_58675) + ); + defparam com_cmm_u_cmm_pm_pme_sent13_0_a2_0_a2_0_a3_0_a2_0_a2.INIT = 4'h8; + LUT2 com_cmm_u_cmm_pm_pme_sent13_0_a2_0_a2_0_a3_0_a2_0_a2 ( + .I0(com_cmm_gnt_pm), + .I1(com_cmm_pme_ack_bar), + .O(com_cmm_u_cmm_pm_pme_sent13) + ); + defparam com_cmm_u_cmm_pm_un1_cmmt_ppm_suspend_req_n_comb_0_sqmuxa_i_0_0_0_o3.INIT = 4'h1; + LUT2 com_cmm_u_cmm_pm_un1_cmmt_ppm_suspend_req_n_comb_0_sqmuxa_i_0_0_0_o3 ( + .I0(com_cmm_u_cmm_pm_cfg_pcie_link_state[0]), + .I1(com_cmm_u_cmm_pm_enable_cmm_tx[1]), + .O(com_cmm_u_cmm_pm_N_56201_i) + ); + defparam com_cmm_u_cmm_pm_st_pm_next_0_0_0_iv_i_i_a2_i_0_a2_2_1_1_.INIT = 4'h2; + LUT2 com_cmm_u_cmm_pm_st_pm_next_0_0_0_iv_i_i_a2_i_0_a2_2_1_1_ ( + .I0(com_st_pm_13_), + .I1(com_cmml_rpm_ra), + .O(com_cmm_u_cmm_pm_N_60460_1) + ); + defparam com_cmm_u_cmm_pm_un1_cmmt_ppm_suspend_req_n_comb_0_sqmuxa_i_0_0_0_a2_2_1.INIT = 4'h8; + LUT2 com_cmm_u_cmm_pm_un1_cmmt_ppm_suspend_req_n_comb_0_sqmuxa_i_0_0_0_a2_2_1 ( + .I0(com_cmm_cmm_arb_pend_req_n), + .I1(com_cmm_u_cmm_pm_st_pm_25__6024), + .O(com_cmm_u_cmm_pm_N_58678_1) + ); + defparam com_cmm_u_cmm_pm_un1_cmml_suspend_now_n21_i_0_0_0_o3_1.INIT = 4'h2; + LUT2 com_cmm_u_cmm_pm_un1_cmml_suspend_now_n21_i_0_0_0_o3_1 ( + .I0(com_cmm_cmm_arb_pend_req_n), + .I1(com_cmmt_rpm_turn_off), + .O(com_cmm_u_cmm_pm_N_56319_i) + ); + defparam com_cmm_u_cmm_pm_un1_cmml_suspend_now_n21_i_0_0_0_o3.INIT = 4'h1; + LUT2 com_cmm_u_cmm_pm_un1_cmml_suspend_now_n21_i_0_0_0_o3 ( + .I0(com_cmm_u_cmm_pm_st_pm_24__6026), + .I1(com_cmm_u_cmm_pm_st_pm_28__6020), + .O(com_cmm_u_cmm_pm_un1_cmml_suspend_now_n21_i_0_0_0_o3_6038) + ); + defparam com_cmm_u_cmm_pm_st_pm_next_0_0_0_iv_1_i_0_0_0_o3_9_.INIT = 4'h2; + LUT2 com_cmm_u_cmm_pm_st_pm_next_0_0_0_iv_1_i_0_0_0_o3_9_ ( + .I0(cfg_cfg_6102[523]), + .I1(cfg_pm_wake_n), + .O(com_cmm_u_cmm_pm_N_56002_i) + ); + defparam com_cmm_u_cmm_pm_inactivity_timer24_0_a2_0_a2_0_a2_0_a2.INIT = 4'h4; + LUT2 com_cmm_u_cmm_pm_inactivity_timer24_0_a2_0_a2_0_a2_0_a2 ( + .I0(com_cmm_u_cmm_pm_inactivity_timer[8]), + .I1(com_cmm_u_cmm_pm_st_pm_24__6026), + .O(com_cmm_u_cmm_pm_inactivity_timer24) + ); + defparam com_cmm_u_cmm_pm_un1_cmml_suspend_now_n21_i_0_0_0_a2_1.INIT = 4'h8; + LUT2 com_cmm_u_cmm_pm_un1_cmml_suspend_now_n21_i_0_0_0_a2_1 ( + .I0(com_cmm_u_cmm_pm_inactivity_timer[8]), + .I1(com_cmm_u_cmm_pm_st_pm_24__6026), + .O(com_cmm_u_cmm_pm_N_58674) + ); + defparam com_cmm_u_cmm_pm_un1_cmmt_ppm_suspend_req_n_comb_0_sqmuxa_i_0_0_0_a2_2_2.INIT = 4'h8; + LUT2_L com_cmm_u_cmm_pm_un1_cmmt_ppm_suspend_req_n_comb_0_sqmuxa_i_0_0_0_a2_2_2 ( + .I0(com_cmm_u_cmm_pm_N_56201_i), + .I1(com_cmm_u_cmm_pm_dev_power_state_eq_d0), + .LO(com_cmm_u_cmm_pm_N_58678_2) + ); + defparam com_cmm_u_cmm_pm_un1_cmml_suspend_now_n21_i_0_0_0_a2_0.INIT = 8'hE0; + LUT3 com_cmm_u_cmm_pm_un1_cmml_suspend_now_n21_i_0_0_0_a2_0 ( + .I0(com_st_pm_17_), + .I1(com_st_pm_27_), + .I2(com_cmml_rpm_ra), + .O(com_cmm_u_cmm_pm_un1_cmml_suspend_now_n21_i_0_0_0_a2_0_6006) + ); + defparam com_cmm_u_cmm_pm_st_pm_next_0_0_0_iv_1_i_0_0_0_a2_1_0_9_.INIT = 8'h80; + LUT3 com_cmm_u_cmm_pm_st_pm_next_0_0_0_iv_1_i_0_0_0_a2_1_0_9_ ( + .I0(com_cmm_cmm_arb_pend_req_n), + .I1(com_cmml_suspend_ok), + .I2(com_cmmt_aspm_suspend_req), + .O(com_cmm_u_cmm_pm_N_58659_1_0) + ); + defparam com_cmm_u_cmm_pm_un936_st_pm_next_m_0_a2_0_a2_0_a2_0_a2_0_a2_6_0_.INIT = 16'h0001; + LUT4_L com_cmm_u_cmm_pm_un936_st_pm_next_m_0_a2_0_a2_0_a2_0_a2_0_a2_6_0_ ( + .I0(com_cmm_u_cmm_pm_st_pm_0__6008), + .I1(com_cmm_u_cmm_pm_st_pm_16__6013), + .I2(com_cmm_u_cmm_pm_st_pm_21__6029), + .I3(com_cmm_u_cmm_pm_st_pm_23__6027), + .LO(com_cmm_u_cmm_pm_un936_st_pm_next_m_0_a2_0_a2_0_a2_0_a2_0_a2_6[0]) + ); + defparam com_cmm_u_cmm_pm_un936_st_pm_next_m_0_a2_0_a2_0_a2_0_a2_0_a2_7_0_.INIT = 16'h0001; + LUT4 com_cmm_u_cmm_pm_un936_st_pm_next_m_0_a2_0_a2_0_a2_0_a2_0_a2_7_0_ ( + .I0(com_cmm_u_cmm_pm_st_pm_6__6018), + .I1(com_cmm_u_cmm_pm_st_pm_8__6016), + .I2(com_cmm_u_cmm_pm_st_pm_18__6010), + .I3(com_cmm_u_cmm_pm_st_pm_30__6035), + .O(com_cmm_u_cmm_pm_un936_st_pm_next_m_0_a2_0_a2_0_a2_0_a2_0_a2_7[0]) + ); + defparam com_cmm_u_cmm_pm_un936_st_pm_next_m_0_a2_0_a2_0_a2_0_a2_0_a2_9_0_.INIT = 16'h0100; + LUT4 com_cmm_u_cmm_pm_un936_st_pm_next_m_0_a2_0_a2_0_a2_0_a2_0_a2_9_0_ ( + .I0(com_cmm_u_cmm_pm_st_pm_10__6015), + .I1(com_cmm_u_cmm_pm_st_pm_14__6014), + .I2(com_cmm_u_cmm_pm_st_pm_19__6031), + .I3(com_cmm_u_cmm_pm_un936_st_pm_next_m_0_a2_0_a2_0_a2_0_a2_0_a2_6[0]), + .O(com_cmm_u_cmm_pm_un936_st_pm_next_m_0_a2_0_a2_0_a2_0_a2_0_a2_9[0]) + ); + defparam com_cmm_u_cmm_pm_st_pm_next_0_0_0_iv_i_i_a2_i_0_1_1_.INIT = 16'h153F; + LUT4_L com_cmm_u_cmm_pm_st_pm_next_0_0_0_iv_i_i_a2_i_0_1_1_ ( + .I0(com_cmm_u_cmm_pm_N_60460_1), + .I1(com_cmm_u_cmm_pm_dev_power_state_eq_d0), + .I2(com_cmm_u_cmm_pm_pme_sent13), + .I3(com_cmmt_rpm_as_nak_l1), + .LO(com_cmm_u_cmm_pm_st_pm_next_0_0_0_iv_i_i_a2_i_0_1[1]) + ); + defparam com_cmm_u_cmm_pm_un1_cmmt_ppm_suspend_req_n_comb_0_sqmuxa_i_0_0_0_39392.INIT = 16'h33F7; + LUT4_L com_cmm_u_cmm_pm_un1_cmmt_ppm_suspend_req_n_comb_0_sqmuxa_i_0_0_0_39392 ( + .I0(com_cmm_u_cmm_pm_N_58678_1), + .I1(com_cmm_u_cmm_pm_N_58678_2), + .I2(com_cmm_pme_ack_bar), + .I3(com_cmm_u_cmm_pm_pme_sent13), + .LO(com_cmm_u_cmm_pm_un1_cmmt_ppm_suspend_req_n_comb_0_sqmuxa_i_0_0_0_39392_6005) + ); + defparam com_cmm_u_cmm_pm_un936_st_pm_next_m_0_a2_0_a2_0_a2_0_a2_0_a2_12_0_.INIT = 16'h8000; + LUT4_L com_cmm_u_cmm_pm_un936_st_pm_next_m_0_a2_0_a2_0_a2_0_a2_0_a2_12_0_ ( + .I0(com_cmm_N_56064_i), + .I1(com_cmm_u_cmm_pm_N_56201_i), + .I2(com_cmm_u_cmm_pm_un936_st_pm_next_m_0_a2_0_a2_0_a2_0_a2_0_a2_7[0]), + .I3(com_cmm_u_cmm_pm_un936_st_pm_next_m_0_a2_0_a2_0_a2_0_a2_0_a2_9[0]), + .LO(com_cmm_u_cmm_pm_un936_st_pm_next_m_0_a2_0_a2_0_a2_0_a2_0_a2_12[0]) + ); + defparam com_cmm_u_cmm_pm_st_pm_next_0_0_0_iv_i_i_a2_i_0_2_1_.INIT = 16'h0700; + LUT4_L com_cmm_u_cmm_pm_st_pm_next_0_0_0_iv_i_i_a2_i_0_2_1_ ( + .I0(com_cmm_u_cmm_pm_N_58678_1), + .I1(com_cmm_u_cmm_pm_dev_power_state_eq_d0), + .I2(com_cmm_u_cmm_pm_st_pm_0__6008), + .I3(com_cmm_u_cmm_pm_st_pm_next_0_0_0_iv_i_i_a2_i_0_1[1]), + .LO(com_cmm_u_cmm_pm_st_pm_next_0_0_0_iv_i_i_a2_i_0_2[1]) + ); + defparam com_cmm_u_cmm_pm_N_85895_i.INIT = 16'hFCFD; + LUT4 com_cmm_u_cmm_pm_N_85895_i ( + .I0(com_cmm_u_cmm_pm_N_56319_i), + .I1(com_cmm_u_cmm_pm_un1_cmml_suspend_now_n21_i_0_0_0_a2_0_6006), + .I2(com_cmm_u_cmm_pm_N_58674), + .I3(com_cmm_u_cmm_pm_un1_cmml_suspend_now_n21_i_0_0_0_o3_6038), + .O(com_cmm_u_cmm_pm_N_85895_i_6033) + ); + defparam com_cmm_u_cmm_pm_N_85829_i.INIT = 16'hF2FF; + LUT4 com_cmm_u_cmm_pm_N_85829_i ( + .I0(com_cmm_u_cmm_pm_N_56002_i), + .I1(com_cmm_u_cmm_pm_N_56201_i), + .I2(com_cmm_u_cmm_pm_N_58675), + .I3(com_cmm_u_cmm_pm_un1_cmmt_ppm_suspend_req_n_comb_0_sqmuxa_i_0_0_0_39392_6005), + .O(com_cmm_u_cmm_pm_N_85829_i_6032) + ); + defparam com_cmm_u_cmm_pm_N_60852_i.INIT = 8'hFD; + LUT3_L com_cmm_u_cmm_pm_N_60852_i ( + .I0(com_cmm_N_56064_i), + .I1(com_cmm_u_cmm_pm_cfg_pcie_link_state[0]), + .I2(com_cmm_u_cmm_pm_st_pm_24__6026), + .LO(com_cmm_N_60852_i) + ); + defparam com_cmm_u_cmm_pm_N_85828_i.INIT = 16'h0F4F; + LUT4_L com_cmm_u_cmm_pm_N_85828_i ( + .I0(com_cmm_u_cmm_pm_N_56002_i), + .I1(com_cmm_u_cmm_pm_cfg_pcie_link_state[0]), + .I2(com_cmm_u_cmm_pm_st_pm_next_0_0_0_iv_i_i_a2_i_0_2[1]), + .I3(com_cmmt_rpm_turn_off), + .LO(com_cmm_u_cmm_pm_N_85828_i_6007) + ); + defparam com_cmm_u_cmm_pm_un936_st_pm_next_m_0_a2_0_a2_0_a2_0_a2_0_a2_0_.INIT = 16'h0800; + LUT4_L com_cmm_u_cmm_pm_un936_st_pm_next_m_0_a2_0_a2_0_a2_0_a2_0_a2_0_ ( + .I0(com_pm_type_q_4_i_0_0_0_a2[2]), + .I1(com_cmm_u_cmm_pm_un1_cmml_suspend_now_n21_i_0_0_0_o3_6038), + .I2(com_cmm_u_cmm_pm_st_pm_25__6024), + .I3(com_cmm_u_cmm_pm_un936_st_pm_next_m_0_a2_0_a2_0_a2_0_a2_0_a2_12[0]), + .LO(com_cmm_u_cmm_pm_st_pm_next[0]) + ); + defparam com_cmm_u_cmm_pm_N_86397_i.INIT = 16'hA0EC; + LUT4_L com_cmm_u_cmm_pm_N_86397_i ( + .I0(com_st_pm_17_), + .I1(com_cmm_u_cmm_pm_st_pm_18__6010), + .I2(com_cmml_rpm_ra), + .I3(com_cmml_suspend_ok), + .LO(com_cmm_u_cmm_pm_N_86397_i_6009) + ); + defparam com_cmm_u_cmm_pm_N_86427_i.INIT = 16'hAE0C; + LUT4_L com_cmm_u_cmm_pm_N_86427_i ( + .I0(com_cmm_u_cmm_pm_st_pm_6__6018), + .I1(com_st_pm_17_), + .I2(com_cmml_rpm_ra), + .I3(com_cmmt_ppm_suspend_ok), + .LO(com_cmm_u_cmm_pm_N_86427_i_6011) + ); + defparam com_cmm_u_cmm_pm_N_86691_i.INIT = 16'h8F88; + LUT4_L com_cmm_u_cmm_pm_N_86691_i ( + .I0(com_cmm_u_cmm_pm_N_56319_i), + .I1(com_cmm_u_cmm_pm_N_58674), + .I2(com_cmm_u_cmm_pm_dev_power_state_eq_d0), + .I3(com_cmm_u_cmm_pm_pme_sent13), + .LO(com_cmm_u_cmm_pm_N_86691_i_6012) + ); + defparam com_cmm_u_cmm_pm_st_pm_next_0_0_0_iv_1_i_0_0_0_a2_0_13_.INIT = 4'h2; + LUT2_L com_cmm_u_cmm_pm_st_pm_next_0_0_0_iv_1_i_0_0_0_a2_0_13_ ( + .I0(com_cmm_u_cmm_pm_N_60460_1), + .I1(com_cmmt_rpm_as_nak_l1), + .LO(com_cmm_u_cmm_pm_N_58657) + ); + defparam com_cmm_u_cmm_pm_st_pm_next_0_0_0_iv_0_0_0_0_10_.INIT = 16'hFF10; + LUT4_L com_cmm_u_cmm_pm_st_pm_next_0_0_0_iv_0_0_0_0_10_ ( + .I0(com_cmm_u_cmm_pm_N_56002_i), + .I1(com_cmm_u_cmm_pm_N_58659_1_0), + .I2(com_cmm_u_cmm_pm_enable_cmm_tx[1]), + .I3(com_cmm_u_cmm_pm_st_pm_10__6015), + .LO(com_cmm_u_cmm_pm_N_10381_i) + ); + defparam com_cmm_u_cmm_pm_st_pm_next_0_0_0_iv_1_i_0_0_0_a2_9_.INIT = 8'h40; + LUT3_L com_cmm_u_cmm_pm_st_pm_next_0_0_0_iv_1_i_0_0_0_a2_9_ ( + .I0(com_cmm_u_cmm_pm_N_56002_i), + .I1(com_cmm_u_cmm_pm_N_58659_1_0), + .I2(com_cmm_u_cmm_pm_enable_cmm_tx[1]), + .LO(com_cmm_u_cmm_pm_N_58659) + ); + defparam com_cmm_u_cmm_pm_N_86396_i.INIT = 8'hCE; + LUT3_L com_cmm_u_cmm_pm_N_86396_i ( + .I0(com_cmm_u_cmm_pm_st_pm_6__6018), + .I1(com_cmm_u_cmm_pm_st_pm_16__6013), + .I2(com_cmmt_ppm_suspend_ok), + .LO(com_cmm_u_cmm_pm_N_86396_i_6017) + ); + defparam com_cmm_u_cmm_pm_N_86426_i.INIT = 16'hECA0; + LUT4_L com_cmm_u_cmm_pm_N_86426_i ( + .I0(com_cmm_u_cmm_pm_N_56319_i), + .I1(com_st_pm_27_), + .I2(com_cmm_u_cmm_pm_st_pm_28__6020), + .I3(com_cmml_rpm_ra), + .LO(com_cmm_u_cmm_pm_N_86426_i_6019) + ); + defparam com_cmm_u_cmm_pm_N_86395_i.INIT = 16'h88F8; + LUT4_L com_cmm_u_cmm_pm_N_86395_i ( + .I0(com_cmm_gnt_pm), + .I1(com_cmm_st_pm[26]), + .I2(com_st_pm_27_), + .I3(com_cmml_rpm_ra), + .LO(com_cmm_u_cmm_pm_N_86395_i_6021) + ); + defparam com_cmm_u_cmm_pm_N_86393_i.INIT = 16'h7530; + LUT4_L com_cmm_u_cmm_pm_N_86393_i ( + .I0(cfg_turnoff_ok_n), + .I1(com_cmm_gnt_pm), + .I2(com_cmm_st_pm[26]), + .I3(com_cmm_u_cmm_pm_st_pm_30__6035), + .LO(com_cmm_u_cmm_pm_N_86393_i_6022) + ); + defparam com_cmm_u_cmm_pm_N_86394_i.INIT = 16'h3F11; + LUT4_L com_cmm_u_cmm_pm_N_86394_i ( + .I0(com_cmm_u_cmm_pm_un1_cmml_suspend_now_n21_i_0_0_0_o3_6038), + .I1(com_cmm_cmm_arb_pend_req_n), + .I2(com_cmm_u_cmm_pm_dev_power_state_eq_d0), + .I3(com_cmm_u_cmm_pm_st_pm_25__6024), + .LO(com_cmm_u_cmm_pm_N_86394_i_6023) + ); + defparam com_cmm_u_cmm_pm_st_pm_next_3_sqmuxa_i_i_a2_0_a2_0_a2_0_a2.INIT = 4'h8; + LUT2_L com_cmm_u_cmm_pm_st_pm_next_3_sqmuxa_i_i_a2_0_a2_0_a2_0_a2 ( + .I0(com_cmm_u_cmm_pm_N_56319_i), + .I1(com_cmm_u_cmm_pm_inactivity_timer24), + .LO(com_cmm_u_cmm_pm_st_pm_next_3_sqmuxa_i_i_a2_0_a2_0_a2_0_a2_6025) + ); + defparam com_cmm_u_cmm_pm_N_86715_i.INIT = 16'h8F88; + LUT4_L com_cmm_u_cmm_pm_N_86715_i ( + .I0(com_cmm_u_cmm_pm_N_56002_i), + .I1(com_cmm_u_cmm_pm_cfg_pcie_link_state[0]), + .I2(com_cmm_gnt_pm), + .I3(com_cmm_pme_ack_bar), + .LO(com_cmm_u_cmm_pm_N_86715_i_6028) + ); + defparam com_cmm_u_cmm_pm_st_pm_i_17_.INIT = 4'h1; + LUT1_L com_cmm_u_cmm_pm_st_pm_i_17_ ( + .I0(com_st_pm_17_), + .LO(com_st_pm_i[17]) + ); + defparam com_cmm_u_cmm_pm_cmml_suspend_now_n_i.INIT = 4'h1; + LUT1_L com_cmm_u_cmm_pm_cmml_suspend_now_n_i ( + .I0(com_cmml_suspend_now_n), + .LO(com_cmml_suspend_now_n_i) + ); + defparam com_cmm_u_cmm_pm_cmmt_ppm_suspend_req_n_i.INIT = 4'h1; + LUT1_L com_cmm_u_cmm_pm_cmmt_ppm_suspend_req_n_i ( + .I0(com_cmmt_ppm_suspend_req_n), + .LO(com_cmmt_ppm_suspend_req_n_i) + ); + defparam com_cmm_u_cmm_pm_N_58673_i.INIT = 4'h1; + LUT1_L com_cmm_u_cmm_pm_N_58673_i ( + .I0(com_cmm_u_cmm_pm_un1_cmml_suspend_now_n21_i_0_0_0_a2_0_6006), + .LO(com_cmm_u_cmm_pm_N_58673_i_6034) + ); + defparam com_cmm_u_cmm_pm_N_85830_i_1.INIT = 16'h0BBB; + LUT4_L com_cmm_u_cmm_pm_N_85830_i_1 ( + .I0(com_cmm_u_cmm_pm_N_56002_i), + .I1(com_cmm_u_cmm_pm_N_58675), + .I2(cfg_turnoff_ok_n), + .I3(com_cmm_u_cmm_pm_st_pm_30__6035), + .LO(com_cmm_u_cmm_pm_N_85830_i_1_6037) + ); + defparam com_cmm_u_cmm_pm_st_pm_next_0_0_0_iv_i_i_i_0_a2_21_.INIT = 8'h20; + LUT3 com_cmm_u_cmm_pm_st_pm_next_0_0_0_iv_i_i_i_0_a2_21_ ( + .I0(com_cmm_u_cmm_pm_enable_cmm_tx[1]), + .I1(cfg_pm_wake_n), + .I2(cfg_cfg_6102[523]), + .O(com_cmm_u_cmm_pm_N_59582) + ); + FDC com_cmm_u_cmm_pm_inactivity_timer_8_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_pm_inactivity_timer_s[8]), + .Q(com_cmm_u_cmm_pm_inactivity_timer[8]), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_pm_inactivity_timer_7_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_pm_inactivity_timer_s[7]), + .Q(com_cmm_u_cmm_pm_inactivity_timer[7]), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_pm_inactivity_timer_6_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_pm_inactivity_timer_s[6]), + .Q(com_cmm_u_cmm_pm_inactivity_timer[6]), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_pm_inactivity_timer_5_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_pm_inactivity_timer_s[5]), + .Q(com_cmm_u_cmm_pm_inactivity_timer[5]), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_pm_inactivity_timer_4_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_pm_inactivity_timer_s[4]), + .Q(com_cmm_u_cmm_pm_inactivity_timer[4]), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_pm_inactivity_timer_3_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_pm_inactivity_timer_s[3]), + .Q(com_cmm_u_cmm_pm_inactivity_timer[3]), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_pm_inactivity_timer_2_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_pm_inactivity_timer_s[2]), + .Q(com_cmm_u_cmm_pm_inactivity_timer[2]), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_pm_inactivity_timer_1_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_pm_inactivity_timer_s[1]), + .Q(com_cmm_u_cmm_pm_inactivity_timer[1]), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_pm_inactivity_timer_0_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_pm_inactivity_timer_s[0]), + .Q(com_cmm_u_cmm_pm_inactivity_timer[0]), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_pm_pme_sent ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_pm_pme_sent13), + .Q(com_cmm_pme_sent), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_pm_st_pm_1_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_pm_N_85828_i_6007), + .Q(com_cmm_u_cmm_pm_cfg_pcie_link_state[0]), + .CLR(com_cmm_rst_351) + ); + FDP com_cmm_u_cmm_pm_st_pm_0_ ( + .PRE(com_cmm_rst_351), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_pm_st_pm_next[0]), + .Q(com_cmm_u_cmm_pm_st_pm_0__6008) + ); + FDC com_cmm_u_cmm_pm_st_pm_18_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_pm_N_86397_i_6009), + .Q(com_cmm_u_cmm_pm_st_pm_18__6010), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_pm_st_pm_17_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_pm_N_86427_i_6011), + .Q(com_st_pm_17_), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_pm_st_pm_16_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_pm_N_86691_i_6012), + .Q(com_cmm_u_cmm_pm_st_pm_16__6013), + .CLR(com_cmm_rst_351) + ); + FDCE com_cmm_u_cmm_pm_st_pm_14_ ( + .CE(com_cmm_u_cmm_pm_N_58679), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_pm_VCC_6030), + .Q(com_cmm_u_cmm_pm_st_pm_14__6014), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_pm_st_pm_13_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_pm_N_58657), + .Q(com_st_pm_13_), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_pm_st_pm_10_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_pm_N_10381_i), + .Q(com_cmm_u_cmm_pm_st_pm_10__6015), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_pm_st_pm_9_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_pm_N_58659), + .Q(com_cmm_u_cmm_pm_enable_cmm_tx[1]), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_pm_st_pm_8_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_pm_st_pm_8__6016), + .Q(com_cmm_u_cmm_pm_st_pm_8__6016), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_pm_st_pm_6_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_pm_N_86396_i_6017), + .Q(com_cmm_u_cmm_pm_st_pm_6__6018), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_pm_st_pm_30_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_pm_N_85830_i_6036), + .Q(com_cmm_u_cmm_pm_st_pm_30__6035), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_pm_st_pm_28_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_pm_N_86426_i_6019), + .Q(com_cmm_u_cmm_pm_st_pm_28__6020), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_pm_st_pm_27_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_pm_N_86395_i_6021), + .Q(com_st_pm_27_), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_pm_st_pm_26_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_pm_N_86393_i_6022), + .Q(com_cmm_st_pm[26]), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_pm_st_pm_25_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_pm_N_86394_i_6023), + .Q(com_cmm_u_cmm_pm_st_pm_25__6024), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_pm_st_pm_24_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_pm_st_pm_next_3_sqmuxa_i_i_a2_0_a2_0_a2_0_a2_6025), + .Q(com_cmm_u_cmm_pm_st_pm_24__6026), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_pm_st_pm_23_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_pm_st_pm_23__6027), + .Q(com_cmm_u_cmm_pm_st_pm_23__6027), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_pm_st_pm_22_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_pm_N_86715_i_6028), + .Q(com_cmm_pme_ack_bar), + .CLR(com_cmm_rst_351) + ); + FDCE com_cmm_u_cmm_pm_st_pm_21_ ( + .CE(com_cmm_u_cmm_pm_N_59582), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_pm_VCC_6030), + .Q(com_cmm_u_cmm_pm_st_pm_21__6029), + .CLR(com_cmm_rst_351) + ); + FDCE com_cmm_u_cmm_pm_st_pm_19_ ( + .CE(com_cmm_u_cmm_pm_N_58708), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_pm_VCC_6030), + .Q(com_cmm_u_cmm_pm_st_pm_19__6031), + .CLR(com_cmm_rst_351) + ); + FDPE com_cmm_u_cmm_pm_cmmt_ppm_suspend_req_n ( + .PRE(com_cmm_rst_351), + .CE(com_cmm_u_cmm_pm_N_85829_i_6032), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_pm_N_56201_i), + .Q(com_cmmt_ppm_suspend_req_n) + ); + FDPE com_cmm_u_cmm_pm_cmml_suspend_now_n ( + .PRE(com_cmm_rst_351), + .CE(com_cmm_u_cmm_pm_N_85895_i_6033), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_pm_N_58673_i_6034), + .Q(com_cmml_suspend_now_n) + ); + INV com_cmm_u_cmm_pm_cfg_pcie_link_state_i_0_ ( + .I(com_cmm_u_cmm_pm_cfg_pcie_link_state[0]), + .O(cfg_pcie_link_state_n_6101[0]) + ); + INV com_cmm_u_cmm_pm_enable_cmm_tx_i_1_ ( + .I(com_cmm_u_cmm_pm_enable_cmm_tx[1]), + .O(cfg_pcie_link_state_n_6101[1]) + ); + INV com_cmm_u_cmm_pm_st_pm_i_30_ ( + .I(com_cmm_u_cmm_pm_st_pm_30__6035), + .O(cfg_to_turnoff_n) + ); + defparam com_cmm_u_cmm_pm_N_85830_i.INIT = 16'h4F0F; + LUT4_L com_cmm_u_cmm_pm_N_85830_i ( + .I0(com_cmm_u_cmm_pm_un1_cmml_suspend_now_n21_i_0_0_0_o3_6038), + .I1(com_cmm_cmm_arb_pend_req_n), + .I2(com_cmm_u_cmm_pm_N_85830_i_1_6037), + .I3(com_cmmt_rpm_turn_off), + .LO(com_cmm_u_cmm_pm_N_85830_i_6036) + ); + defparam com_cmm_u_cmm_pm_inactivity_timer_qxu_0_0_.INIT = 4'h8; + LUT2_L com_cmm_u_cmm_pm_inactivity_timer_qxu_0_0_ ( + .I0(com_cmm_u_cmm_pm_inactivity_timer24), + .I1(com_cmm_u_cmm_pm_inactivity_timer[0]), + .LO(com_cmm_u_cmm_pm_inactivity_timer_qxu[0]) + ); + defparam com_cmm_u_cmm_pm_inactivity_timer_qxu_0_1_.INIT = 4'h8; + LUT2_L com_cmm_u_cmm_pm_inactivity_timer_qxu_0_1_ ( + .I0(com_cmm_u_cmm_pm_inactivity_timer24), + .I1(com_cmm_u_cmm_pm_inactivity_timer[1]), + .LO(com_cmm_u_cmm_pm_inactivity_timer_qxu[1]) + ); + defparam com_cmm_u_cmm_pm_inactivity_timer_qxu_0_2_.INIT = 4'h8; + LUT2_L com_cmm_u_cmm_pm_inactivity_timer_qxu_0_2_ ( + .I0(com_cmm_u_cmm_pm_inactivity_timer24), + .I1(com_cmm_u_cmm_pm_inactivity_timer[2]), + .LO(com_cmm_u_cmm_pm_inactivity_timer_qxu[2]) + ); + defparam com_cmm_u_cmm_pm_inactivity_timer_qxu_0_3_.INIT = 4'h8; + LUT2_L com_cmm_u_cmm_pm_inactivity_timer_qxu_0_3_ ( + .I0(com_cmm_u_cmm_pm_inactivity_timer24), + .I1(com_cmm_u_cmm_pm_inactivity_timer[3]), + .LO(com_cmm_u_cmm_pm_inactivity_timer_qxu[3]) + ); + defparam com_cmm_u_cmm_pm_inactivity_timer_qxu_0_4_.INIT = 4'h8; + LUT2_L com_cmm_u_cmm_pm_inactivity_timer_qxu_0_4_ ( + .I0(com_cmm_u_cmm_pm_inactivity_timer24), + .I1(com_cmm_u_cmm_pm_inactivity_timer[4]), + .LO(com_cmm_u_cmm_pm_inactivity_timer_qxu[4]) + ); + defparam com_cmm_u_cmm_pm_inactivity_timer_qxu_0_5_.INIT = 4'h8; + LUT2_L com_cmm_u_cmm_pm_inactivity_timer_qxu_0_5_ ( + .I0(com_cmm_u_cmm_pm_inactivity_timer24), + .I1(com_cmm_u_cmm_pm_inactivity_timer[5]), + .LO(com_cmm_u_cmm_pm_inactivity_timer_qxu[5]) + ); + defparam com_cmm_u_cmm_pm_inactivity_timer_qxu_0_6_.INIT = 4'h8; + LUT2_L com_cmm_u_cmm_pm_inactivity_timer_qxu_0_6_ ( + .I0(com_cmm_u_cmm_pm_inactivity_timer24), + .I1(com_cmm_u_cmm_pm_inactivity_timer[6]), + .LO(com_cmm_u_cmm_pm_inactivity_timer_qxu[6]) + ); + defparam com_cmm_u_cmm_pm_inactivity_timer_qxu_0_7_.INIT = 4'h8; + LUT2_L com_cmm_u_cmm_pm_inactivity_timer_qxu_0_7_ ( + .I0(com_cmm_u_cmm_pm_inactivity_timer24), + .I1(com_cmm_u_cmm_pm_inactivity_timer[7]), + .LO(com_cmm_u_cmm_pm_inactivity_timer_qxu[7]) + ); + defparam com_cmm_u_cmm_pm_inactivity_timer_qxu_0_8_.INIT = 4'h8; + LUT2_L com_cmm_u_cmm_pm_inactivity_timer_qxu_0_8_ ( + .I0(com_cmm_u_cmm_pm_inactivity_timer24), + .I1(com_cmm_u_cmm_pm_inactivity_timer[8]), + .LO(com_cmm_u_cmm_pm_inactivity_timer_qxu[8]) + ); + FDR com_cmm_u_cmm_arbiter_req_errman_d_0_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_req_errman[0]), + .Q(com_cmm_u_cmm_arbiter_req_errman_d[0]), + .R(com_cmm_u_cmm_arbiter_N_85985_i_6043) + ); + FDR com_cmm_u_cmm_arbiter_req_errman_d_1_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_req_errman[1]), + .Q(com_cmm_u_cmm_arbiter_req_errman_d[1]), + .R(com_cmm_u_cmm_arbiter_N_85985_i_6043) + ); + FDR com_cmm_u_cmm_arbiter_req_errman_d_2_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_req_errman[2]), + .Q(com_cmm_u_cmm_arbiter_req_errman_d[2]), + .R(com_cmm_u_cmm_arbiter_N_85985_i_6043) + ); + FDR com_cmm_u_cmm_arbiter_req_arbiter_0_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_arbiter_N_42987_i), + .Q(com_cmm_req_arbiter[0]), + .R(com_cmm_rst_351) + ); + FDR com_cmm_u_cmm_arbiter_req_arbiter_1_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_arbiter_N_42989_i), + .Q(com_cmm_req_arbiter[1]), + .R(com_cmm_rst_351) + ); + FDR com_cmm_u_cmm_arbiter_req_arbiter_2_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_arbiter_N_42991_i), + .Q(com_cmm_req_arbiter[2]), + .R(com_cmm_rst_351) + ); + FDR com_cmm_u_cmm_arbiter_req_arbiter_3_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_arbiter_N_42758_i), + .Q(com_cmm_req_arbiter[3]), + .R(com_cmm_rst_351) + ); + FDS com_cmm_u_cmm_arbiter_cmm_arb_pend_req_n ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_arbiter_N_43125_i), + .Q(com_cmm_cmm_arb_pend_req_n), + .S(com_cmm_rst_351) + ); + defparam com_cmm_u_cmm_arbiter_ns_fsm_i_i_0_o3_3_.INIT = 4'h4; + LUT2 com_cmm_u_cmm_arbiter_ns_fsm_i_i_0_o3_3_ ( + .I0(com_cmm_req_cfgctrl), + .I1(com_cmm_req_intr), + .O(com_cmm_u_cmm_arbiter_ns_fsm_i_i_0_o3[3]) + ); + defparam com_cmm_u_cmm_arbiter_req_arbiter_6_i_0_o3_3_.INIT = 4'h8; + LUT2_L com_cmm_u_cmm_arbiter_req_arbiter_6_i_0_o3_3_ ( + .I0(com_cmm_u_cmm_arbiter_cs_fsm[1]), + .I1(com_cmm_u_cmm_arbiter_cs_fsm[2]), + .LO(com_cmm_u_cmm_arbiter_N_56357_i) + ); + defparam com_cmm_u_cmm_arbiter_ns_fsm_i_i_0_o2_3_.INIT = 4'h1; + LUT2 com_cmm_u_cmm_arbiter_ns_fsm_i_i_0_o2_3_ ( + .I0(com_cmm_u_cmm_arbiter_cs_fsm[0]), + .I1(com_cmm_u_cmm_arbiter_cs_fsm[2]), + .O(com_cmm_u_cmm_arbiter_N_56341_i) + ); + defparam com_cmm_u_cmm_arbiter_req_errman_d8_i_0_o3.INIT = 4'h1; + LUT2 com_cmm_u_cmm_arbiter_req_errman_d8_i_0_o3 ( + .I0(com_cmm_req_cfgctrl), + .I1(com_cmm_req_intr), + .O(com_cmm_u_cmm_arbiter_N_56158_i) + ); + defparam com_cmm_u_cmm_arbiter_req_arbiter_6_i_0_o3_2_.INIT = 4'h1; + LUT2 com_cmm_u_cmm_arbiter_req_arbiter_6_i_0_o3_2_ ( + .I0(com_cmm_u_cmm_arbiter_cs_fsm[1]), + .I1(com_cmm_u_cmm_arbiter_cs_fsm[3]), + .O(com_cmm_u_cmm_arbiter_N_56091_i) + ); + defparam com_cmm_u_cmm_arbiter_ns_fsm_0_i_0_o3_0_.INIT = 4'h1; + LUT2 com_cmm_u_cmm_arbiter_ns_fsm_0_i_0_o3_0_ ( + .I0(com_cmm_pme_ack_bar), + .I1(com_cmm_st_pm[26]), + .O(com_cmm_N_56064_i) + ); + defparam com_cmm_u_cmm_arbiter_req_arbiter_6_i_0_a2_0_0_.INIT = 4'h4; + LUT2 com_cmm_u_cmm_arbiter_req_arbiter_6_i_0_a2_0_0_ ( + .I0(com_cmm_u_cmm_arbiter_cs_fsm[0]), + .I1(com_cmm_u_cmm_arbiter_cs_fsm[3]), + .O(com_cmm_u_cmm_arbiter_N_60428) + ); + defparam com_cmm_u_cmm_arbiter_ns_fsm_i_i_i_i_a2_1_1_.INIT = 4'h2; + LUT2 com_cmm_u_cmm_arbiter_ns_fsm_i_i_i_i_a2_1_1_ ( + .I0(com_cmm_u_cmm_arbiter_N_56091_i), + .I1(com_cmm_u_cmm_arbiter_cs_fsm[0]), + .O(com_cmm_u_cmm_arbiter_N_60462_1) + ); + defparam com_cmm_u_cmm_arbiter_req_errman_d8_i_o3_1.INIT = 8'h01; + LUT3 com_cmm_u_cmm_arbiter_req_errman_d8_i_o3_1 ( + .I0(com_cmm_req_errman[0]), + .I1(com_cmm_req_errman[1]), + .I2(com_cmm_req_errman[2]), + .O(com_cmm_u_cmm_arbiter_N_44141_i) + ); + defparam com_cmm_u_cmm_arbiter_ns_fsm_i_i_i_i_a2_0_1_.INIT = 8'h10; + LUT3 com_cmm_u_cmm_arbiter_ns_fsm_i_i_i_i_a2_0_1_ ( + .I0(com_cmm_gnt_arbiter), + .I1(com_cmm_u_cmm_arbiter_cs_fsm[0]), + .I2(com_cmm_u_cmm_arbiter_cs_fsm[1]), + .O(com_cmm_u_cmm_arbiter_N_60463) + ); + defparam com_cmm_u_cmm_arbiter_req_arbiter_6_i_0_a2_1_.INIT = 16'h080C; + LUT4_L com_cmm_u_cmm_arbiter_req_arbiter_6_i_0_a2_1_ ( + .I0(com_cmm_u_cmm_arbiter_N_56091_i), + .I1(com_cmm_u_cmm_arbiter_cs_fsm[0]), + .I2(com_cmm_u_cmm_arbiter_cs_fsm[2]), + .I3(com_cmm_u_cmm_arbiter_req_errman_d[1]), + .LO(com_cmm_u_cmm_arbiter_N_60429) + ); + defparam com_cmm_u_cmm_arbiter_req_arbiter_6_i_0_a2_2_2_.INIT = 8'h08; + LUT3 com_cmm_u_cmm_arbiter_req_arbiter_6_i_0_a2_2_2_ ( + .I0(com_cmm_u_cmm_arbiter_N_56091_i), + .I1(com_cmm_u_cmm_arbiter_cs_fsm[0]), + .I2(com_cmm_u_cmm_arbiter_cs_fsm[2]), + .O(com_cmm_u_cmm_arbiter_N_60435) + ); + defparam com_cmm_u_cmm_arbiter_req_arbiter_6_i_0_a2_2_.INIT = 16'h0015; + LUT4 com_cmm_u_cmm_arbiter_req_arbiter_6_i_0_a2_2_ ( + .I0(com_cmm_u_cmm_arbiter_N_60428), + .I1(com_cmm_u_cmm_arbiter_cs_fsm[0]), + .I2(com_cmm_u_cmm_arbiter_cs_fsm[1]), + .I3(com_cmm_u_cmm_arbiter_req_errman_d[2]), + .O(com_cmm_u_cmm_arbiter_N_60432) + ); + defparam com_cmm_u_cmm_arbiter_ns_fsm_0_0_0_a2_0_2_.INIT = 16'h000B; + LUT4 com_cmm_u_cmm_arbiter_ns_fsm_0_0_0_a2_0_2_ ( + .I0(com_cmm_N_56064_i), + .I1(com_cmm_u_cmm_arbiter_N_56158_i), + .I2(com_cmm_u_cmm_arbiter_cs_fsm[0]), + .I3(com_cmm_u_cmm_arbiter_cs_fsm[1]), + .O(com_cmm_u_cmm_arbiter_N_58326) + ); + defparam com_cmm_u_cmm_arbiter_ns_fsm_0_i_0_0_39306.INIT = 16'hA0FB; + LUT4 com_cmm_u_cmm_arbiter_ns_fsm_0_i_0_0_39306 ( + .I0(com_cmm_gnt_arbiter), + .I1(com_cmm_u_cmm_arbiter_cs_fsm[0]), + .I2(com_cmm_u_cmm_arbiter_cs_fsm[1]), + .I3(com_cmm_u_cmm_arbiter_cs_fsm[2]), + .O(com_cmm_u_cmm_arbiter_ns_fsm_0_i_0_0_39306_6040) + ); + defparam com_cmm_u_cmm_arbiter_ns_fsm_0_0_0_2_39423.INIT = 16'hC03B; + LUT4_L com_cmm_u_cmm_arbiter_ns_fsm_0_0_0_2_39423 ( + .I0(com_cmm_gnt_arbiter), + .I1(com_cmm_u_cmm_arbiter_cs_fsm[0]), + .I2(com_cmm_u_cmm_arbiter_cs_fsm[1]), + .I3(com_cmm_u_cmm_arbiter_cs_fsm[2]), + .LO(com_cmm_u_cmm_arbiter_ns_fsm_0_0_0_2_39423_6039) + ); + defparam com_cmm_u_cmm_arbiter_ns_fsm_0_i_0_a2_0_.INIT = 16'h00E4; + LUT4 com_cmm_u_cmm_arbiter_ns_fsm_0_i_0_a2_0_ ( + .I0(com_cmm_u_cmm_arbiter_N_56091_i), + .I1(com_cmm_gnt_arbiter), + .I2(com_cmm_req_cfgctrl), + .I3(com_cmm_u_cmm_arbiter_cs_fsm[0]), + .O(com_cmm_u_cmm_arbiter_N_60439) + ); + defparam com_cmm_u_cmm_arbiter_req_arbiter_6_i_0_1_39419.INIT = 16'hEFC8; + LUT4 com_cmm_u_cmm_arbiter_req_arbiter_6_i_0_1_39419 ( + .I0(com_cmm_u_cmm_arbiter_cs_fsm[0]), + .I1(com_cmm_u_cmm_arbiter_cs_fsm[1]), + .I2(com_cmm_u_cmm_arbiter_cs_fsm[3]), + .I3(com_cmm_u_cmm_arbiter_req_errman_d[1]), + .O(com_cmm_u_cmm_arbiter_req_arbiter_6_i_0_1_39419_6042) + ); + defparam com_cmm_u_cmm_arbiter_req_arbiter_6_i_0_o3_0_.INIT = 16'h8082; + LUT4 com_cmm_u_cmm_arbiter_req_arbiter_6_i_0_o3_0_ ( + .I0(com_cmm_u_cmm_arbiter_cs_fsm[0]), + .I1(com_cmm_u_cmm_arbiter_cs_fsm[1]), + .I2(com_cmm_u_cmm_arbiter_cs_fsm[2]), + .I3(com_cmm_u_cmm_arbiter_cs_fsm[3]), + .O(com_cmm_u_cmm_arbiter_N_56482_i) + ); + defparam com_cmm_u_cmm_arbiter_req_errman_d8_i_0_o2.INIT = 8'h35; + LUT3 com_cmm_u_cmm_arbiter_req_errman_d8_i_0_o2 ( + .I0(com_cmm_u_cmm_arbiter_N_44141_i), + .I1(com_cmm_gnt_arbiter), + .I2(com_cmm_u_cmm_arbiter_cs_fsm[1]), + .O(com_cmm_u_cmm_arbiter_N_56179_i) + ); + defparam com_cmm_u_cmm_arbiter_ns_fsm_0_i_0_a2_1_0_.INIT = 16'h0020; + LUT4_L com_cmm_u_cmm_arbiter_ns_fsm_0_i_0_a2_1_0_ ( + .I0(com_cmm_u_cmm_arbiter_N_44141_i), + .I1(com_cmm_N_56064_i), + .I2(com_cmm_u_cmm_arbiter_N_60462_1), + .I3(com_cmm_req_intr), + .LO(com_cmm_u_cmm_arbiter_N_60441) + ); + defparam com_cmm_u_cmm_arbiter_ns_fsm_i_i_i_i_a2_1_.INIT = 16'h7000; + LUT4_L com_cmm_u_cmm_arbiter_ns_fsm_i_i_i_i_a2_1_ ( + .I0(com_cmm_u_cmm_arbiter_N_44141_i), + .I1(com_cmm_N_56064_i), + .I2(com_cmm_u_cmm_arbiter_N_56158_i), + .I3(com_cmm_u_cmm_arbiter_N_60462_1), + .LO(com_cmm_u_cmm_arbiter_N_60462) + ); + defparam com_cmm_u_cmm_arbiter_ns_fsm_0_0_0_0_2_.INIT = 8'h8A; + LUT3 com_cmm_u_cmm_arbiter_ns_fsm_0_0_0_0_2_ ( + .I0(com_cmm_u_cmm_arbiter_ns_fsm_0_0_0_2_39423_6039), + .I1(com_cmm_u_cmm_arbiter_cs_fsm[1]), + .I2(com_cmm_u_cmm_arbiter_cs_fsm[3]), + .O(com_cmm_u_cmm_arbiter_ns_fsm_0_0_0_0[2]) + ); + defparam com_cmm_u_cmm_arbiter_req_arbiter_6_i_0_2_39310.INIT = 16'h0103; + LUT4_L com_cmm_u_cmm_arbiter_req_arbiter_6_i_0_2_39310 ( + .I0(com_cmm_u_cmm_arbiter_N_56341_i), + .I1(com_cmm_u_cmm_arbiter_N_60432), + .I2(com_cmm_u_cmm_arbiter_N_60435), + .I3(com_cmm_u_cmm_arbiter_cs_fsm[3]), + .LO(com_cmm_u_cmm_arbiter_req_arbiter_6_i_0_2_39310_6041) + ); + defparam com_cmm_u_cmm_arbiter_ns_fsm_0_sqmuxa_4_0_a2_0_a2.INIT = 4'h8; + LUT2_L com_cmm_u_cmm_arbiter_ns_fsm_0_sqmuxa_4_0_a2_0_a2 ( + .I0(com_cmm_u_cmm_arbiter_N_60435), + .I1(com_cmm_gnt_arbiter), + .LO(com_cmm_u_cmm_arbiter_ns_fsm_0_sqmuxa_4) + ); + defparam com_cmm_u_cmm_arbiter_ns_fsm_0_sqmuxa_2_0_a2_0_a2.INIT = 4'h8; + LUT2_L com_cmm_u_cmm_arbiter_ns_fsm_0_sqmuxa_2_0_a2_0_a2 ( + .I0(com_cmm_u_cmm_arbiter_N_60428), + .I1(com_cmm_gnt_arbiter), + .LO(com_cmm_u_cmm_arbiter_ns_fsm_0_sqmuxa_2) + ); + defparam com_cmm_u_cmm_arbiter_ns_fsm_0_a4_0_0_a2_0_a2_2_.INIT = 8'h80; + LUT3_L com_cmm_u_cmm_arbiter_ns_fsm_0_a4_0_0_a2_0_a2_2_ ( + .I0(com_cmm_u_cmm_arbiter_N_56341_i), + .I1(com_cmm_gnt_arbiter), + .I2(com_cmm_u_cmm_arbiter_cs_fsm[1]), + .LO(com_cmm_u_cmm_arbiter_ns_fsm_0_a4_0_0_a2_0_a2[2]) + ); + defparam com_cmm_u_cmm_arbiter_ns_fsm_0_sqmuxa_0_a2_0_a2.INIT = 16'h8000; + LUT4_L com_cmm_u_cmm_arbiter_ns_fsm_0_sqmuxa_0_a2_0_a2 ( + .I0(com_cmm_gnt_arbiter), + .I1(com_cmm_u_cmm_arbiter_cs_fsm[0]), + .I2(com_cmm_u_cmm_arbiter_cs_fsm[1]), + .I3(com_cmm_u_cmm_arbiter_cs_fsm[2]), + .LO(com_cmm_u_cmm_arbiter_ns_fsm_0_sqmuxa) + ); + defparam com_cmm_u_cmm_arbiter_ns_fsm_i_i_0_3_.INIT = 16'h0A08; + LUT4_L com_cmm_u_cmm_arbiter_ns_fsm_i_i_0_3_ ( + .I0(com_cmm_u_cmm_arbiter_N_56341_i), + .I1(com_cmm_u_cmm_arbiter_ns_fsm_i_i_0_o3[3]), + .I2(com_cmm_u_cmm_arbiter_cs_fsm[1]), + .I3(com_cmm_u_cmm_arbiter_cs_fsm[3]), + .LO(com_cmm_u_cmm_arbiter_N_43044_i) + ); + defparam com_cmm_u_cmm_arbiter_ns_fsm_0_0_0_2_.INIT = 16'h3100; + LUT4_L com_cmm_u_cmm_arbiter_ns_fsm_0_0_0_2_ ( + .I0(com_cmm_u_cmm_arbiter_N_56179_i), + .I1(com_cmm_u_cmm_arbiter_N_58326), + .I2(com_cmm_u_cmm_arbiter_cs_fsm[0]), + .I3(com_cmm_u_cmm_arbiter_ns_fsm_0_0_0_0[2]), + .LO(com_cmm_u_cmm_arbiter_N_10094_i) + ); + defparam com_cmm_u_cmm_arbiter_N_85986_i.INIT = 16'hFFFE; + LUT4_L com_cmm_u_cmm_arbiter_N_85986_i ( + .I0(com_cmm_u_cmm_arbiter_N_60462), + .I1(com_cmm_u_cmm_arbiter_N_60463), + .I2(com_cmm_gnt_intr), + .I3(com_cmm_u_cmm_arbiter_cs_fsm[2]), + .LO(com_cmm_u_cmm_arbiter_N_85986_i_6045) + ); + defparam com_cmm_u_cmm_arbiter_N_85984_i.INIT = 16'hFFEF; + LUT4_L com_cmm_u_cmm_arbiter_N_85984_i ( + .I0(com_cmm_u_cmm_arbiter_N_60439), + .I1(com_cmm_u_cmm_arbiter_N_60441), + .I2(com_cmm_u_cmm_arbiter_ns_fsm_0_i_0_0_39306_6040), + .I3(com_cmm_gnt_intr), + .LO(com_cmm_u_cmm_arbiter_N_85984_i_6046) + ); + defparam com_cmm_u_cmm_arbiter_un1_pass_state22_i_0.INIT = 16'h0103; + LUT4_L com_cmm_u_cmm_arbiter_un1_pass_state22_i_0 ( + .I0(com_cmm_u_cmm_arbiter_N_56341_i), + .I1(com_cmm_u_cmm_arbiter_N_56482_i), + .I2(com_cmm_u_cmm_arbiter_N_60428), + .I3(com_cmm_u_cmm_arbiter_cs_fsm[1]), + .LO(com_cmm_u_cmm_arbiter_N_43125_i) + ); + defparam com_cmm_u_cmm_arbiter_req_arbiter_6_i_0_3_.INIT = 16'h2300; + LUT4_L com_cmm_u_cmm_arbiter_req_arbiter_6_i_0_3_ ( + .I0(com_cmm_u_cmm_arbiter_N_56357_i), + .I1(com_cmm_gnt_arbiter), + .I2(com_cmm_u_cmm_arbiter_cs_fsm[0]), + .I3(com_cmm_u_cmm_arbiter_cs_fsm[3]), + .LO(com_cmm_u_cmm_arbiter_N_42758_i) + ); + defparam com_cmm_u_cmm_arbiter_req_arbiter_6_i_0_2_.INIT = 16'h2220; + LUT4_L com_cmm_u_cmm_arbiter_req_arbiter_6_i_0_2_ ( + .I0(com_cmm_u_cmm_arbiter_req_arbiter_6_i_0_2_39310_6041), + .I1(com_cmm_gnt_arbiter), + .I2(com_cmm_u_cmm_arbiter_cs_fsm[2]), + .I3(com_cmm_u_cmm_arbiter_req_errman_d[2]), + .LO(com_cmm_u_cmm_arbiter_N_42991_i) + ); + defparam com_cmm_u_cmm_arbiter_req_arbiter_6_i_0_1_.INIT = 8'h04; + LUT3_L com_cmm_u_cmm_arbiter_req_arbiter_6_i_0_1_ ( + .I0(com_cmm_u_cmm_arbiter_N_60429), + .I1(com_cmm_u_cmm_arbiter_req_arbiter_6_i_0_1_39419_6042), + .I2(com_cmm_gnt_arbiter), + .LO(com_cmm_u_cmm_arbiter_N_42989_i) + ); + defparam com_cmm_u_cmm_arbiter_req_arbiter_6_i_0_0_.INIT = 16'h0302; + LUT4_L com_cmm_u_cmm_arbiter_req_arbiter_6_i_0_0_ ( + .I0(com_cmm_u_cmm_arbiter_N_56482_i), + .I1(com_cmm_u_cmm_arbiter_N_60428), + .I2(com_cmm_gnt_arbiter), + .I3(com_cmm_u_cmm_arbiter_req_errman_d[0]), + .LO(com_cmm_u_cmm_arbiter_N_42987_i) + ); + defparam com_cmm_u_cmm_arbiter_N_85985_i_1.INIT = 16'h3032; + LUT4 com_cmm_u_cmm_arbiter_N_85985_i_1 ( + .I0(com_cmm_u_cmm_arbiter_N_56158_i), + .I1(com_cmm_gnt_intr), + .I2(com_cmm_u_cmm_arbiter_cs_fsm[1]), + .I3(com_cmm_u_cmm_arbiter_cs_fsm[3]), + .O(com_cmm_u_cmm_arbiter_N_85985_i_1_6044) + ); + defparam com_cmm_u_cmm_arbiter_N_85985_i.INIT = 16'hF7FF; + LUT4 com_cmm_u_cmm_arbiter_N_85985_i ( + .I0(com_cmm_u_cmm_arbiter_N_56179_i), + .I1(com_cmm_u_cmm_arbiter_N_56341_i), + .I2(com_cmm_rst_351), + .I3(com_cmm_u_cmm_arbiter_N_85985_i_1_6044), + .O(com_cmm_u_cmm_arbiter_N_85985_i_6043) + ); + FDC com_cmm_u_cmm_arbiter_gnt_cfgctrl ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_arbiter_ns_fsm_0_sqmuxa_4), + .Q(com_cmm_gnt_cfgctrl), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_arbiter_gnt_intr ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_arbiter_ns_fsm_0_sqmuxa_2), + .Q(com_cmm_gnt_intr), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_arbiter_gnt_errman ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_arbiter_ns_fsm_0_a4_0_0_a2_0_a2[2]), + .Q(com_cmm_gnt_errman), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_arbiter_gnt_pm ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_arbiter_ns_fsm_0_sqmuxa), + .Q(com_cmm_gnt_pm), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_arbiter_cs_fsm_3_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_arbiter_N_43044_i), + .Q(com_cmm_u_cmm_arbiter_cs_fsm[3]), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_arbiter_cs_fsm_2_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_arbiter_N_10094_i), + .Q(com_cmm_u_cmm_arbiter_cs_fsm[2]), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_arbiter_cs_fsm_1_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_arbiter_N_85986_i_6045), + .Q(com_cmm_u_cmm_arbiter_cs_fsm[1]), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_arbiter_cs_fsm_0_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_arbiter_N_85984_i_6046), + .Q(com_cmm_u_cmm_arbiter_cs_fsm[0]), + .CLR(com_cmm_rst_351) + ); + FDR com_cmm_u_cmm_dataproducer_req_gnt_state_0_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_dataproducer_N_17573_i), + .Q(com_cmm_u_cmm_dataproducer_req_gnt_state[0]), + .R(com_cmm_rst_351) + ); + FDR com_cmm_u_cmm_dataproducer_req_gnt_state_1_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_dataproducer_N_17557_i), + .Q(com_cmm_u_cmm_dataproducer_req_gnt_state[1]), + .R(com_cmm_rst_351) + ); + FDRE com_cmm_u_cmm_dataproducer_req_gnt_code_0_ ( + .CE(com_cmm_u_cmm_dataproducer_N_10527_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_dataproducer_N_17563_i), + .Q(com_cmm_u_cmm_dataproducer_req_gnt_code[0]), + .R(com_cmm_rst_351) + ); + FDRE com_cmm_u_cmm_dataproducer_req_gnt_code_1_ ( + .CE(com_cmm_u_cmm_dataproducer_N_10527_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_dataproducer_N_17565_i), + .Q(com_cmm_u_cmm_dataproducer_req_gnt_code[1]), + .R(com_cmm_rst_351) + ); + FDRE com_cmm_u_cmm_dataproducer_req_gnt_code_2_ ( + .CE(com_cmm_u_cmm_dataproducer_N_10527_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_dataproducer_N_17567_i), + .Q(com_cmm_u_cmm_dataproducer_req_gnt_code[2]), + .R(com_cmm_rst_351) + ); + FDRE com_cmm_u_cmm_dataproducer_req_gnt_code_3_ ( + .CE(com_cmm_u_cmm_dataproducer_N_10527_i), + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_dataproducer_N_17569_i), + .Q(com_cmm_u_cmm_dataproducer_req_gnt_code[3]), + .R(com_cmm_rst_351) + ); + defparam com_cmm_u_cmm_dataproducer_byte_06_21_0_a2_0_a2_0_o3_7_.INIT = 4'h4; + LUT2 com_cmm_u_cmm_dataproducer_byte_06_21_0_a2_0_a2_0_o3_7_ ( + .I0(com_cmm_data_errmanager[48]), + .I1(com_cmm_data_errmanager[49]), + .O(com_cmm_N_56318_i) + ); + defparam com_cmm_u_cmm_dataproducer_req_gnt_code_8_i_0_0_o3_3_.INIT = 4'h1; + LUT2 com_cmm_u_cmm_dataproducer_req_gnt_code_8_i_0_0_o3_3_ ( + .I0(com_cmm_req_arbiter[1]), + .I1(com_cmm_req_arbiter[2]), + .O(com_cmm_u_cmm_dataproducer_N_56514_i) + ); + defparam com_cmm_u_cmm_dataproducer_byte_07_27_0_1_iv_i_0_0_0_a2_4_.INIT = 4'h2; + LUT2 com_cmm_u_cmm_dataproducer_byte_07_27_0_1_iv_i_0_0_0_a2_4_ ( + .I0(com_cmm_u_cmm_dataproducer_req_gnt_code[2]), + .I1(com_cmm_u_cmm_dataproducer_req_gnt_code[3]), + .O(N_58537) + ); + defparam com_cmm_u_cmm_dataproducer_byte_00_19_i_0_0_0_a2_5_.INIT = 8'h4C; + LUT3 com_cmm_u_cmm_dataproducer_byte_00_19_i_0_0_0_a2_5_ ( + .I0(com_cmm_u_cmm_dataproducer_req_gnt_code[1]), + .I1(com_cmm_u_cmm_dataproducer_req_gnt_code[2]), + .I2(com_cmm_u_cmm_dataproducer_req_gnt_code[3]), + .O(com_cmm_u_cmm_dataproducer_byte_00_19[4]) + ); + defparam com_cmm_u_cmm_dataproducer_byte_07_27_0_1_iv_i_0_0_a2_0_0_.INIT = 16'h4000; + LUT4 com_cmm_u_cmm_dataproducer_byte_07_27_0_1_iv_i_0_0_a2_0_0_ ( + .I0(com_cmm_pme_ack_bar), + .I1(com_cmm_u_cmm_dataproducer_req_gnt_code[0]), + .I2(com_cmm_u_cmm_dataproducer_req_gnt_code[1]), + .I3(com_cmm_u_cmm_dataproducer_req_gnt_code[2]), + .O(com_cmm_u_cmm_dataproducer_N_58535) + ); + defparam com_cmm_u_cmm_dataproducer_byte_02_20_1_0_0_a3_4_.INIT = 8'h02; + LUT3 com_cmm_u_cmm_dataproducer_byte_02_20_1_0_0_a3_4_ ( + .I0(com_cmm_u_cmm_dataproducer_req_gnt_code[1]), + .I1(com_cmm_u_cmm_dataproducer_req_gnt_code[2]), + .I2(com_cmm_u_cmm_dataproducer_req_gnt_code[3]), + .O(com_cmm_u_cmm_dataproducer_N_61357) + ); + defparam com_cmm_u_cmm_dataproducer_byte_07_27_0_1_iv_i_0_0_a2_3_.INIT = 8'h80; + LUT3 com_cmm_u_cmm_dataproducer_byte_07_27_0_1_iv_i_0_0_a2_3_ ( + .I0(com_cmm_u_cmm_dataproducer_req_gnt_code[0]), + .I1(com_cmm_u_cmm_dataproducer_req_gnt_code[1]), + .I2(com_cmm_u_cmm_dataproducer_req_gnt_code[2]), + .O(com_cmm_u_cmm_dataproducer_N_58650) + ); + defparam com_cmm_u_cmm_dataproducer_byte_07_27_0_1_iv_i_0_0_a2_2_.INIT = 16'hE000; + LUT4 com_cmm_u_cmm_dataproducer_byte_07_27_0_1_iv_i_0_0_a2_2_ ( + .I0(com_cmm_u_cmm_dataproducer_req_gnt_code[0]), + .I1(com_cmm_u_cmm_dataproducer_req_gnt_code[1]), + .I2(com_cmm_u_cmm_dataproducer_req_gnt_code[2]), + .I3(com_cmm_u_cmm_dataproducer_req_gnt_code[3]), + .O(com_cmm_u_cmm_dataproducer_N_58647) + ); + defparam com_cmm_u_cmm_dataproducer_byte_07_27_0_1_iv_i_0_0_a2_0_2_.INIT = 8'h02; + LUT3 com_cmm_u_cmm_dataproducer_byte_07_27_0_1_iv_i_0_0_a2_0_2_ ( + .I0(com_cmm_u_cmm_dataproducer_req_gnt_code[0]), + .I1(com_cmm_u_cmm_dataproducer_req_gnt_code[1]), + .I2(com_cmm_u_cmm_dataproducer_req_gnt_code[2]), + .O(com_cmm_u_cmm_dataproducer_N_58648) + ); + defparam com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_sn_m5_i_0_0_a3.INIT = 8'h80; + LUT3 com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_sn_m5_i_0_0_a3 ( + .I0(com_cmm_u_cmm_dataproducer_req_gnt_code[1]), + .I1(com_cmm_u_cmm_dataproducer_req_gnt_code[2]), + .I2(com_cmm_u_cmm_dataproducer_req_gnt_code[3]), + .O(com_cmm_u_cmm_dataproducer_N_61299) + ); + defparam com_cmm_u_cmm_dataproducer_byte_07_27_0_1_iv_i_0_0_a2_0_.INIT = 8'h84; + LUT3 com_cmm_u_cmm_dataproducer_byte_07_27_0_1_iv_i_0_0_a2_0_ ( + .I0(com_cmm_u_cmm_dataproducer_req_gnt_code[1]), + .I1(com_cmm_u_cmm_dataproducer_req_gnt_code[2]), + .I2(com_cmm_u_cmm_dataproducer_req_gnt_code[3]), + .O(com_cmm_u_cmm_dataproducer_N_58534) + ); + defparam com_cmm_u_cmm_dataproducer_req_gnt_code_8_i_0_0_o3_2_.INIT = 8'h08; + LUT3 com_cmm_u_cmm_dataproducer_req_gnt_code_8_i_0_0_o3_2_ ( + .I0(com_cmm_req_arbiter[3]), + .I1(com_cmm_u_cmm_dataproducer_pcie_link_state_d[0]), + .I2(com_cmm_u_cmm_dataproducer_req_gnt_state[1]), + .O(com_cmm_u_cmm_dataproducer_req_gnt_code_8_i_0_0_o3[2]) + ); + defparam com_cmm_u_cmm_dataproducer_req_gnt_code_8_i_0_0_a2_1_3_.INIT = 16'h0001; + LUT4 com_cmm_u_cmm_dataproducer_req_gnt_code_8_i_0_0_a2_1_3_ ( + .I0(com_cmm_bdf_err_rd_pack), + .I1(com_cmm_posnd_wr_pack), + .I2(com_cmm_req_arbiter[3]), + .I3(com_cmm_type1_type0_bar), + .O(com_cmm_u_cmm_dataproducer_N_58531) + ); + defparam com_cmm_u_cmm_dataproducer_byte_01_20_i_0_0_1_1_5_.INIT = 8'h02; + LUT3 com_cmm_u_cmm_dataproducer_byte_01_20_i_0_0_1_1_5_ ( + .I0(com_cmm_u_cmm_dataproducer_req_gnt_code[1]), + .I1(com_cmm_u_cmm_dataproducer_req_gnt_code[2]), + .I2(com_cmm_u_cmm_dataproducer_req_gnt_code[3]), + .O(com_cmm_u_cmm_dataproducer_byte_01_20_i_0_0_1_1[5]) + ); + defparam com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_sn_m5_i_0_0_a3_0_2.INIT = 16'h0008; + LUT4_L com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_sn_m5_i_0_0_a3_0_2 ( + .I0(com_cmm_req_cfgctrl), + .I1(com_cmm_u_cmm_dataproducer_req_gnt_code[0]), + .I2(com_cmm_u_cmm_dataproducer_req_gnt_code[1]), + .I3(com_cmm_u_cmm_dataproducer_req_gnt_code[2]), + .LO(com_cmm_u_cmm_dataproducer_m5_i_0_0_a3_0_2) + ); + defparam com_cmm_u_cmm_dataproducer_req_gnt_code_8_i_0_0_1_3_.INIT = 16'h000E; + LUT4_L com_cmm_u_cmm_dataproducer_req_gnt_code_8_i_0_0_1_3_ ( + .I0(com_cmm_req_arbiter[3]), + .I1(com_cmm_req_cfgctrl), + .I2(com_cmm_u_cmm_dataproducer_req_gnt_state[0]), + .I3(com_cmm_u_cmm_dataproducer_req_gnt_state[1]), + .LO(com_cmm_u_cmm_dataproducer_req_gnt_code_8_i_0_0_1[3]) + ); + defparam com_cmm_u_cmm_dataproducer_un1_nxt_req_gnt_state36_1_0_0_0.INIT = 16'h00AC; + LUT4 com_cmm_u_cmm_dataproducer_un1_nxt_req_gnt_state36_1_0_0_0 ( + .I0(com_cmm_gnt_pkt_tx), + .I1(com_cmm_u_cmm_dataproducer_pcie_link_state_d[0]), + .I2(com_cmm_u_cmm_dataproducer_req_gnt_state[0]), + .I3(com_cmm_u_cmm_dataproducer_req_gnt_state[1]), + .O(com_cmm_u_cmm_dataproducer_N_10527_i) + ); + defparam com_cmm_u_cmm_dataproducer_byte_06_21_iv_i_0_i_1_5_.INIT = 16'h0C50; + LUT4_L com_cmm_u_cmm_dataproducer_byte_06_21_iv_i_0_i_1_5_ ( + .I0(com_cmm_data_errmanager[49]), + .I1(com_cmm_u_cmm_dataproducer_req_gnt_code[0]), + .I2(com_cmm_u_cmm_dataproducer_req_gnt_code[1]), + .I3(com_cmm_u_cmm_dataproducer_req_gnt_code[3]), + .LO(com_cmm_u_cmm_dataproducer_byte_06_21_iv_i_0_i_1[5]) + ); + defparam com_cmm_u_cmm_dataproducer_byte_04_17_i_0_0_a2_0_.INIT = 16'h0D01; + LUT4 com_cmm_u_cmm_dataproducer_byte_04_17_i_0_0_a2_0_ ( + .I0(com_cmm_u_cmm_dataproducer_req_gnt_code[0]), + .I1(com_cmm_u_cmm_dataproducer_req_gnt_code[1]), + .I2(com_cmm_u_cmm_dataproducer_req_gnt_code[2]), + .I3(com_cmm_u_cmm_dataproducer_req_gnt_code[3]), + .O(com_cmm_u_cmm_dataproducer_byte_04_17_i_0_0_a2[0]) + ); + defparam com_cmm_u_cmm_dataproducer_un1_byte_1062_1_i_i_i_a3.INIT = 16'h020E; + LUT4 com_cmm_u_cmm_dataproducer_un1_byte_1062_1_i_i_i_a3 ( + .I0(com_cmm_u_cmm_dataproducer_req_gnt_code[0]), + .I1(com_cmm_u_cmm_dataproducer_req_gnt_code[1]), + .I2(com_cmm_u_cmm_dataproducer_req_gnt_code[2]), + .I3(com_cmm_u_cmm_dataproducer_req_gnt_code[3]), + .O(com_cmm_u_cmm_dataproducer_un1_byte_1062_1_i_i_i_a3_6048) + ); + defparam com_cmm_u_cmm_dataproducer_byte_02_20_1_0_0_a2_1_5_.INIT = 8'h28; + LUT3 com_cmm_u_cmm_dataproducer_byte_02_20_1_0_0_a2_1_5_ ( + .I0(com_cmm_u_cmm_dataproducer_N_61357), + .I1(com_cmm_data_errmanager[48]), + .I2(com_cmm_data_errmanager[49]), + .O(com_cmm_u_cmm_dataproducer_N_57748_1) + ); + defparam com_cmm_u_cmm_dataproducer_byte_11_17_m0_0_a2_0_a2_i_o2_0_.INIT = 16'h800C; + LUT4 com_cmm_u_cmm_dataproducer_byte_11_17_m0_0_a2_0_a2_i_o2_0_ ( + .I0(com_cmm_u_cmm_dataproducer_req_gnt_code[0]), + .I1(com_cmm_u_cmm_dataproducer_req_gnt_code[1]), + .I2(com_cmm_u_cmm_dataproducer_req_gnt_code[2]), + .I3(com_cmm_u_cmm_dataproducer_req_gnt_code[3]), + .O(com_cmm_u_cmm_dataproducer_byte_11_17_m0_0_a2_0_a2_i_o2[0]) + ); + defparam com_cmm_u_cmm_dataproducer_req_gnt_state_4s2_i_0_0_a2_0.INIT = 16'h0002; + LUT4_L com_cmm_u_cmm_dataproducer_req_gnt_state_4s2_i_0_0_a2_0 ( + .I0(com_cmm_u_cmm_dataproducer_N_56514_i), + .I1(com_cmm_req_arbiter[0]), + .I2(com_cmm_req_arbiter[3]), + .I3(com_cmm_u_cmm_dataproducer_req_gnt_state[0]), + .LO(com_cmm_u_cmm_dataproducer_N_58533) + ); + defparam com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_sn_m5_i_0_0_a3_0.INIT = 16'h0080; + LUT4 com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_sn_m5_i_0_0_a3_0 ( + .I0(com_cmm_cfg_rd), + .I1(com_cmm_req_valid), + .I2(com_cmm_u_cmm_dataproducer_m5_i_0_0_a3_0_2), + .I3(com_cmm_u_cmm_dataproducer_req_gnt_code[3]), + .O(com_cmm_u_cmm_dataproducer_N_61317) + ); + defparam com_cmm_u_cmm_dataproducer_req_gnt_code_8_i_0_0_2_3_.INIT = 16'hE200; + LUT4_L com_cmm_u_cmm_dataproducer_req_gnt_code_8_i_0_0_2_3_ ( + .I0(com_cmm_req_arbiter[0]), + .I1(com_cmm_req_arbiter[3]), + .I2(com_cmm_u_cmm_dataproducer_pcie_link_state_d[0]), + .I3(com_cmm_u_cmm_dataproducer_req_gnt_code_8_i_0_0_1[3]), + .LO(com_cmm_u_cmm_dataproducer_req_gnt_code_8_i_0_0_2[3]) + ); + defparam com_cmm_u_cmm_dataproducer_byte_07_27_0_1_iv_i_0_0_0_5_.INIT = 16'hCF8F; + LUT4 com_cmm_u_cmm_dataproducer_byte_07_27_0_1_iv_i_0_0_0_5_ ( + .I0(com_cmm_u_cmm_dataproducer_req_gnt_code[0]), + .I1(com_cmm_u_cmm_dataproducer_req_gnt_code[1]), + .I2(com_cmm_u_cmm_dataproducer_req_gnt_code[2]), + .I3(com_cmm_u_cmm_dataproducer_req_gnt_code[3]), + .O(com_cmm_u_cmm_dataproducer_byte_07_27_0_1_iv_i_0_0_0[5]) + ); + defparam com_cmm_u_cmm_dataproducer_byte_10_17_1_0_a2_7_.INIT = 16'h88A0; + LUT4_L com_cmm_u_cmm_dataproducer_byte_10_17_1_0_a2_7_ ( + .I0(com_cmm_u_cmm_dataproducer_un1_byte_1062_1_i_i_i_a3_6048), + .I1(com_cmm_data_errmanager[7]), + .I2(com_cmm_tag[7]), + .I3(com_cmm_u_cmm_dataproducer_req_gnt_code[1]), + .LO(com_cmm_u_cmm_dataproducer_N_57743) + ); + defparam com_cmm_u_cmm_dataproducer_byte_10_17_1_0_a2_6_.INIT = 16'h88A0; + LUT4_L com_cmm_u_cmm_dataproducer_byte_10_17_1_0_a2_6_ ( + .I0(com_cmm_u_cmm_dataproducer_un1_byte_1062_1_i_i_i_a3_6048), + .I1(com_cmm_data_errmanager[6]), + .I2(com_cmm_tag[6]), + .I3(com_cmm_u_cmm_dataproducer_req_gnt_code[1]), + .LO(com_cmm_u_cmm_dataproducer_N_57740) + ); + defparam com_cmm_u_cmm_dataproducer_byte_10_17_1_0_a2_5_.INIT = 16'h88A0; + LUT4_L com_cmm_u_cmm_dataproducer_byte_10_17_1_0_a2_5_ ( + .I0(com_cmm_u_cmm_dataproducer_un1_byte_1062_1_i_i_i_a3_6048), + .I1(com_cmm_data_errmanager[5]), + .I2(com_cmm_tag[5]), + .I3(com_cmm_u_cmm_dataproducer_req_gnt_code[1]), + .LO(com_cmm_u_cmm_dataproducer_N_57737) + ); + defparam com_cmm_u_cmm_dataproducer_byte_10_17_1_0_a2_4_.INIT = 16'h88A0; + LUT4_L com_cmm_u_cmm_dataproducer_byte_10_17_1_0_a2_4_ ( + .I0(com_cmm_u_cmm_dataproducer_un1_byte_1062_1_i_i_i_a3_6048), + .I1(com_cmm_data_errmanager[4]), + .I2(com_cmm_tag[4]), + .I3(com_cmm_u_cmm_dataproducer_req_gnt_code[1]), + .LO(com_cmm_u_cmm_dataproducer_N_57734) + ); + defparam com_cmm_u_cmm_dataproducer_byte_10_17_1_0_a2_3_.INIT = 16'h88A0; + LUT4_L com_cmm_u_cmm_dataproducer_byte_10_17_1_0_a2_3_ ( + .I0(com_cmm_u_cmm_dataproducer_un1_byte_1062_1_i_i_i_a3_6048), + .I1(com_cmm_data_errmanager[3]), + .I2(com_cmm_tag[3]), + .I3(com_cmm_u_cmm_dataproducer_req_gnt_code[1]), + .LO(com_cmm_u_cmm_dataproducer_N_57731) + ); + defparam com_cmm_u_cmm_dataproducer_byte_10_17_1_0_a2_2_.INIT = 16'h88A0; + LUT4_L com_cmm_u_cmm_dataproducer_byte_10_17_1_0_a2_2_ ( + .I0(com_cmm_u_cmm_dataproducer_un1_byte_1062_1_i_i_i_a3_6048), + .I1(com_cmm_data_errmanager[2]), + .I2(com_cmm_tag[2]), + .I3(com_cmm_u_cmm_dataproducer_req_gnt_code[1]), + .LO(com_cmm_u_cmm_dataproducer_N_57728) + ); + defparam com_cmm_u_cmm_dataproducer_byte_10_17_1_0_a2_1_.INIT = 16'h88A0; + LUT4_L com_cmm_u_cmm_dataproducer_byte_10_17_1_0_a2_1_ ( + .I0(com_cmm_u_cmm_dataproducer_un1_byte_1062_1_i_i_i_a3_6048), + .I1(com_cmm_data_errmanager[1]), + .I2(com_cmm_tag[1]), + .I3(com_cmm_u_cmm_dataproducer_req_gnt_code[1]), + .LO(com_cmm_u_cmm_dataproducer_N_57725) + ); + defparam com_cmm_u_cmm_dataproducer_byte_10_17_1_0_a2_0_.INIT = 16'h88A0; + LUT4_L com_cmm_u_cmm_dataproducer_byte_10_17_1_0_a2_0_ ( + .I0(com_cmm_u_cmm_dataproducer_un1_byte_1062_1_i_i_i_a3_6048), + .I1(com_cmm_data_errmanager[0]), + .I2(com_cmm_tag[0]), + .I3(com_cmm_u_cmm_dataproducer_req_gnt_code[1]), + .LO(com_cmm_u_cmm_dataproducer_N_57722) + ); + defparam com_cmm_u_cmm_dataproducer_byte_09_17_0_0_a2_7_.INIT = 16'h88A0; + LUT4_L com_cmm_u_cmm_dataproducer_byte_09_17_0_0_a2_7_ ( + .I0(com_cmm_u_cmm_dataproducer_un1_byte_1062_1_i_i_i_a3_6048), + .I1(com_cmm_data_errmanager[15]), + .I2(com_cmm_req_id[7]), + .I3(com_cmm_u_cmm_dataproducer_req_gnt_code[1]), + .LO(com_cmm_u_cmm_dataproducer_N_57719) + ); + defparam com_cmm_u_cmm_dataproducer_byte_09_17_1_0_a2_6_.INIT = 16'h88A0; + LUT4_L com_cmm_u_cmm_dataproducer_byte_09_17_1_0_a2_6_ ( + .I0(com_cmm_u_cmm_dataproducer_un1_byte_1062_1_i_i_i_a3_6048), + .I1(com_cmm_data_errmanager[14]), + .I2(com_cmm_req_id[6]), + .I3(com_cmm_u_cmm_dataproducer_req_gnt_code[1]), + .LO(com_cmm_u_cmm_dataproducer_N_57716) + ); + defparam com_cmm_u_cmm_dataproducer_byte_09_17_1_0_a2_5_.INIT = 16'h88A0; + LUT4_L com_cmm_u_cmm_dataproducer_byte_09_17_1_0_a2_5_ ( + .I0(com_cmm_u_cmm_dataproducer_un1_byte_1062_1_i_i_i_a3_6048), + .I1(com_cmm_data_errmanager[13]), + .I2(com_cmm_req_id[5]), + .I3(com_cmm_u_cmm_dataproducer_req_gnt_code[1]), + .LO(com_cmm_u_cmm_dataproducer_N_57713) + ); + defparam com_cmm_u_cmm_dataproducer_byte_09_17_1_0_a2_4_.INIT = 16'h88A0; + LUT4_L com_cmm_u_cmm_dataproducer_byte_09_17_1_0_a2_4_ ( + .I0(com_cmm_u_cmm_dataproducer_un1_byte_1062_1_i_i_i_a3_6048), + .I1(com_cmm_data_errmanager[12]), + .I2(com_cmm_req_id[4]), + .I3(com_cmm_u_cmm_dataproducer_req_gnt_code[1]), + .LO(com_cmm_u_cmm_dataproducer_N_57710) + ); + defparam com_cmm_u_cmm_dataproducer_byte_09_17_1_0_a2_3_.INIT = 16'h88A0; + LUT4_L com_cmm_u_cmm_dataproducer_byte_09_17_1_0_a2_3_ ( + .I0(com_cmm_u_cmm_dataproducer_un1_byte_1062_1_i_i_i_a3_6048), + .I1(com_cmm_data_errmanager[11]), + .I2(com_cmm_req_id[3]), + .I3(com_cmm_u_cmm_dataproducer_req_gnt_code[1]), + .LO(com_cmm_u_cmm_dataproducer_N_57707) + ); + defparam com_cmm_u_cmm_dataproducer_byte_09_17_1_0_a2_2_.INIT = 16'h88A0; + LUT4_L com_cmm_u_cmm_dataproducer_byte_09_17_1_0_a2_2_ ( + .I0(com_cmm_u_cmm_dataproducer_un1_byte_1062_1_i_i_i_a3_6048), + .I1(com_cmm_data_errmanager[10]), + .I2(com_cmm_req_id[2]), + .I3(com_cmm_u_cmm_dataproducer_req_gnt_code[1]), + .LO(com_cmm_u_cmm_dataproducer_N_57704) + ); + defparam com_cmm_u_cmm_dataproducer_byte_09_17_1_0_a2_1_.INIT = 16'h88A0; + LUT4_L com_cmm_u_cmm_dataproducer_byte_09_17_1_0_a2_1_ ( + .I0(com_cmm_u_cmm_dataproducer_un1_byte_1062_1_i_i_i_a3_6048), + .I1(com_cmm_data_errmanager[9]), + .I2(com_cmm_req_id[1]), + .I3(com_cmm_u_cmm_dataproducer_req_gnt_code[1]), + .LO(com_cmm_u_cmm_dataproducer_N_57701) + ); + defparam com_cmm_u_cmm_dataproducer_byte_09_17_1_0_a2_0_.INIT = 16'h88A0; + LUT4_L com_cmm_u_cmm_dataproducer_byte_09_17_1_0_a2_0_ ( + .I0(com_cmm_u_cmm_dataproducer_un1_byte_1062_1_i_i_i_a3_6048), + .I1(com_cmm_data_errmanager[8]), + .I2(com_cmm_req_id[0]), + .I3(com_cmm_u_cmm_dataproducer_req_gnt_code[1]), + .LO(com_cmm_u_cmm_dataproducer_N_57698) + ); + defparam com_cmm_u_cmm_dataproducer_byte_08_17_1_0_a2_7_.INIT = 16'h88A0; + LUT4_L com_cmm_u_cmm_dataproducer_byte_08_17_1_0_a2_7_ ( + .I0(com_cmm_u_cmm_dataproducer_un1_byte_1062_1_i_i_i_a3_6048), + .I1(com_cmm_data_errmanager[23]), + .I2(com_cmm_req_id[15]), + .I3(com_cmm_u_cmm_dataproducer_req_gnt_code[1]), + .LO(com_cmm_u_cmm_dataproducer_N_57695) + ); + defparam com_cmm_u_cmm_dataproducer_byte_08_17_1_0_a2_6_.INIT = 16'h88A0; + LUT4_L com_cmm_u_cmm_dataproducer_byte_08_17_1_0_a2_6_ ( + .I0(com_cmm_u_cmm_dataproducer_un1_byte_1062_1_i_i_i_a3_6048), + .I1(com_cmm_data_errmanager[22]), + .I2(com_cmm_req_id[14]), + .I3(com_cmm_u_cmm_dataproducer_req_gnt_code[1]), + .LO(com_cmm_u_cmm_dataproducer_N_57692) + ); + defparam com_cmm_u_cmm_dataproducer_byte_08_17_1_0_a2_5_.INIT = 16'h88A0; + LUT4_L com_cmm_u_cmm_dataproducer_byte_08_17_1_0_a2_5_ ( + .I0(com_cmm_u_cmm_dataproducer_un1_byte_1062_1_i_i_i_a3_6048), + .I1(com_cmm_data_errmanager[21]), + .I2(com_cmm_req_id[13]), + .I3(com_cmm_u_cmm_dataproducer_req_gnt_code[1]), + .LO(com_cmm_u_cmm_dataproducer_N_57689) + ); + defparam com_cmm_u_cmm_dataproducer_byte_08_17_1_0_a2_4_.INIT = 16'h88A0; + LUT4_L com_cmm_u_cmm_dataproducer_byte_08_17_1_0_a2_4_ ( + .I0(com_cmm_u_cmm_dataproducer_un1_byte_1062_1_i_i_i_a3_6048), + .I1(com_cmm_data_errmanager[20]), + .I2(com_cmm_req_id[12]), + .I3(com_cmm_u_cmm_dataproducer_req_gnt_code[1]), + .LO(com_cmm_u_cmm_dataproducer_N_57686) + ); + defparam com_cmm_u_cmm_dataproducer_byte_08_17_1_0_a2_3_.INIT = 16'h88A0; + LUT4_L com_cmm_u_cmm_dataproducer_byte_08_17_1_0_a2_3_ ( + .I0(com_cmm_u_cmm_dataproducer_un1_byte_1062_1_i_i_i_a3_6048), + .I1(com_cmm_data_errmanager[19]), + .I2(com_cmm_req_id[11]), + .I3(com_cmm_u_cmm_dataproducer_req_gnt_code[1]), + .LO(com_cmm_u_cmm_dataproducer_N_57683) + ); + defparam com_cmm_u_cmm_dataproducer_byte_08_17_1_0_a2_2_.INIT = 16'h88A0; + LUT4_L com_cmm_u_cmm_dataproducer_byte_08_17_1_0_a2_2_ ( + .I0(com_cmm_u_cmm_dataproducer_un1_byte_1062_1_i_i_i_a3_6048), + .I1(com_cmm_data_errmanager[18]), + .I2(com_cmm_req_id[10]), + .I3(com_cmm_u_cmm_dataproducer_req_gnt_code[1]), + .LO(com_cmm_u_cmm_dataproducer_N_57680) + ); + defparam com_cmm_u_cmm_dataproducer_byte_08_17_1_0_a2_1_.INIT = 16'h88A0; + LUT4_L com_cmm_u_cmm_dataproducer_byte_08_17_1_0_a2_1_ ( + .I0(com_cmm_u_cmm_dataproducer_un1_byte_1062_1_i_i_i_a3_6048), + .I1(com_cmm_data_errmanager[17]), + .I2(com_cmm_req_id[9]), + .I3(com_cmm_u_cmm_dataproducer_req_gnt_code[1]), + .LO(com_cmm_u_cmm_dataproducer_N_57677) + ); + defparam com_cmm_u_cmm_dataproducer_byte_08_17_1_0_a2_0_.INIT = 16'h88A0; + LUT4_L com_cmm_u_cmm_dataproducer_byte_08_17_1_0_a2_0_ ( + .I0(com_cmm_u_cmm_dataproducer_un1_byte_1062_1_i_i_i_a3_6048), + .I1(com_cmm_data_errmanager[16]), + .I2(com_cmm_req_id[8]), + .I3(com_cmm_u_cmm_dataproducer_req_gnt_code[1]), + .LO(com_cmm_u_cmm_dataproducer_N_57674) + ); + defparam com_cmm_u_cmm_dataproducer_byte_11_17_m0_0_2_.INIT = 8'hD8; + LUT3_L com_cmm_u_cmm_dataproducer_byte_11_17_m0_0_2_ ( + .I0(com_cmm_u_cmm_dataproducer_byte_11_17_m0_0_a2_0_a2_i_o2[0]), + .I1(com_cmm_msi_haddr[2]), + .I2(com_cmm_msi_laddr[2]), + .LO(com_cmm_u_cmm_dataproducer_byte_11_17_m0[2]) + ); + defparam com_cmm_u_cmm_dataproducer_byte_11_17_m0_0_3_.INIT = 8'hD8; + LUT3_L com_cmm_u_cmm_dataproducer_byte_11_17_m0_0_3_ ( + .I0(com_cmm_u_cmm_dataproducer_byte_11_17_m0_0_a2_0_a2_i_o2[0]), + .I1(com_cmm_msi_haddr[3]), + .I2(com_cmm_msi_laddr[3]), + .LO(com_cmm_u_cmm_dataproducer_byte_11_17_m0[3]) + ); + defparam com_cmm_u_cmm_dataproducer_byte_11_17_m0_0_6_.INIT = 8'hD8; + LUT3_L com_cmm_u_cmm_dataproducer_byte_11_17_m0_0_6_ ( + .I0(com_cmm_u_cmm_dataproducer_byte_11_17_m0_0_a2_0_a2_i_o2[0]), + .I1(com_cmm_msi_haddr[6]), + .I2(com_cmm_msi_laddr[6]), + .LO(com_cmm_u_cmm_dataproducer_byte_11_17_m0[6]) + ); + defparam com_cmm_u_cmm_dataproducer_byte_11_17_m0_0_5_.INIT = 8'hD8; + LUT3_L com_cmm_u_cmm_dataproducer_byte_11_17_m0_0_5_ ( + .I0(com_cmm_u_cmm_dataproducer_byte_11_17_m0_0_a2_0_a2_i_o2[0]), + .I1(com_cmm_msi_haddr[5]), + .I2(com_cmm_msi_laddr[5]), + .LO(com_cmm_u_cmm_dataproducer_byte_11_17_m0[5]) + ); + defparam com_cmm_u_cmm_dataproducer_byte_11_17_m0_0_4_.INIT = 8'hD8; + LUT3_L com_cmm_u_cmm_dataproducer_byte_11_17_m0_0_4_ ( + .I0(com_cmm_u_cmm_dataproducer_byte_11_17_m0_0_a2_0_a2_i_o2[0]), + .I1(com_cmm_msi_haddr[4]), + .I2(com_cmm_msi_laddr[4]), + .LO(com_cmm_u_cmm_dataproducer_byte_11_17_m0[4]) + ); + defparam com_cmm_u_cmm_dataproducer_byte_09_17_1_0_0_0_.INIT = 16'h5515; + LUT4_L com_cmm_u_cmm_dataproducer_byte_09_17_1_0_0_0_ ( + .I0(com_cmm_u_cmm_dataproducer_N_57698), + .I1(com_cmm_u_cmm_dataproducer_N_61299), + .I2(com_cmm_msi_laddr[16]), + .I3(com_cmm_u_cmm_dataproducer_req_gnt_code[0]), + .LO(com_cmm_u_cmm_dataproducer_byte_09_17_1_0_0[0]) + ); + defparam com_cmm_u_cmm_dataproducer_byte_08_17_1_0_0_2_.INIT = 16'h5515; + LUT4_L com_cmm_u_cmm_dataproducer_byte_08_17_1_0_0_2_ ( + .I0(com_cmm_u_cmm_dataproducer_N_57680), + .I1(com_cmm_u_cmm_dataproducer_N_61299), + .I2(com_cmm_msi_laddr[26]), + .I3(com_cmm_u_cmm_dataproducer_req_gnt_code[0]), + .LO(com_cmm_u_cmm_dataproducer_byte_08_17_1_0_0[2]) + ); + defparam com_cmm_u_cmm_dataproducer_byte_10_17_1_0_0_5_.INIT = 16'h5515; + LUT4_L com_cmm_u_cmm_dataproducer_byte_10_17_1_0_0_5_ ( + .I0(com_cmm_u_cmm_dataproducer_N_57737), + .I1(com_cmm_u_cmm_dataproducer_N_61299), + .I2(com_cmm_msi_laddr[13]), + .I3(com_cmm_u_cmm_dataproducer_req_gnt_code[0]), + .LO(com_cmm_u_cmm_dataproducer_byte_10_17_1_0_0[5]) + ); + defparam com_cmm_u_cmm_dataproducer_byte_09_17_1_0_0_4_.INIT = 16'h5515; + LUT4_L com_cmm_u_cmm_dataproducer_byte_09_17_1_0_0_4_ ( + .I0(com_cmm_u_cmm_dataproducer_N_57710), + .I1(com_cmm_u_cmm_dataproducer_N_61299), + .I2(com_cmm_msi_laddr[20]), + .I3(com_cmm_u_cmm_dataproducer_req_gnt_code[0]), + .LO(com_cmm_u_cmm_dataproducer_byte_09_17_1_0_0[4]) + ); + defparam com_cmm_u_cmm_dataproducer_byte_09_17_1_0_0_3_.INIT = 16'h5515; + LUT4_L com_cmm_u_cmm_dataproducer_byte_09_17_1_0_0_3_ ( + .I0(com_cmm_u_cmm_dataproducer_N_57707), + .I1(com_cmm_u_cmm_dataproducer_N_61299), + .I2(com_cmm_msi_laddr[19]), + .I3(com_cmm_u_cmm_dataproducer_req_gnt_code[0]), + .LO(com_cmm_u_cmm_dataproducer_byte_09_17_1_0_0[3]) + ); + defparam com_cmm_u_cmm_dataproducer_byte_08_17_1_0_0_3_.INIT = 16'h5515; + LUT4_L com_cmm_u_cmm_dataproducer_byte_08_17_1_0_0_3_ ( + .I0(com_cmm_u_cmm_dataproducer_N_57683), + .I1(com_cmm_u_cmm_dataproducer_N_61299), + .I2(com_cmm_msi_laddr[27]), + .I3(com_cmm_u_cmm_dataproducer_req_gnt_code[0]), + .LO(com_cmm_u_cmm_dataproducer_byte_08_17_1_0_0[3]) + ); + defparam com_cmm_u_cmm_dataproducer_byte_08_17_1_0_0_6_.INIT = 16'h5515; + LUT4_L com_cmm_u_cmm_dataproducer_byte_08_17_1_0_0_6_ ( + .I0(com_cmm_u_cmm_dataproducer_N_57692), + .I1(com_cmm_u_cmm_dataproducer_N_61299), + .I2(com_cmm_msi_laddr[30]), + .I3(com_cmm_u_cmm_dataproducer_req_gnt_code[0]), + .LO(com_cmm_u_cmm_dataproducer_byte_08_17_1_0_0[6]) + ); + defparam com_cmm_u_cmm_dataproducer_byte_09_17_0_0_0_7_.INIT = 16'h5515; + LUT4_L com_cmm_u_cmm_dataproducer_byte_09_17_0_0_0_7_ ( + .I0(com_cmm_u_cmm_dataproducer_N_57719), + .I1(com_cmm_u_cmm_dataproducer_N_61299), + .I2(com_cmm_msi_laddr[23]), + .I3(com_cmm_u_cmm_dataproducer_req_gnt_code[0]), + .LO(com_cmm_u_cmm_dataproducer_byte_09_17_0_0_0[7]) + ); + defparam com_cmm_u_cmm_dataproducer_byte_09_17_1_0_0_1_.INIT = 16'h5515; + LUT4_L com_cmm_u_cmm_dataproducer_byte_09_17_1_0_0_1_ ( + .I0(com_cmm_u_cmm_dataproducer_N_57701), + .I1(com_cmm_u_cmm_dataproducer_N_61299), + .I2(com_cmm_msi_laddr[17]), + .I3(com_cmm_u_cmm_dataproducer_req_gnt_code[0]), + .LO(com_cmm_u_cmm_dataproducer_byte_09_17_1_0_0[1]) + ); + defparam com_cmm_u_cmm_dataproducer_byte_08_17_1_0_0_1_.INIT = 16'h5515; + LUT4_L com_cmm_u_cmm_dataproducer_byte_08_17_1_0_0_1_ ( + .I0(com_cmm_u_cmm_dataproducer_N_57677), + .I1(com_cmm_u_cmm_dataproducer_N_61299), + .I2(com_cmm_msi_laddr[25]), + .I3(com_cmm_u_cmm_dataproducer_req_gnt_code[0]), + .LO(com_cmm_u_cmm_dataproducer_byte_08_17_1_0_0[1]) + ); + defparam com_cmm_u_cmm_dataproducer_byte_08_17_1_0_0_0_.INIT = 16'h5515; + LUT4_L com_cmm_u_cmm_dataproducer_byte_08_17_1_0_0_0_ ( + .I0(com_cmm_u_cmm_dataproducer_N_57674), + .I1(com_cmm_u_cmm_dataproducer_N_61299), + .I2(com_cmm_msi_laddr[24]), + .I3(com_cmm_u_cmm_dataproducer_req_gnt_code[0]), + .LO(com_cmm_u_cmm_dataproducer_byte_08_17_1_0_0[0]) + ); + defparam com_cmm_u_cmm_dataproducer_byte_08_17_1_0_0_5_.INIT = 16'h5515; + LUT4_L com_cmm_u_cmm_dataproducer_byte_08_17_1_0_0_5_ ( + .I0(com_cmm_u_cmm_dataproducer_N_57689), + .I1(com_cmm_u_cmm_dataproducer_N_61299), + .I2(com_cmm_msi_laddr[29]), + .I3(com_cmm_u_cmm_dataproducer_req_gnt_code[0]), + .LO(com_cmm_u_cmm_dataproducer_byte_08_17_1_0_0[5]) + ); + defparam com_cmm_u_cmm_dataproducer_byte_10_17_1_0_0_2_.INIT = 16'h5515; + LUT4_L com_cmm_u_cmm_dataproducer_byte_10_17_1_0_0_2_ ( + .I0(com_cmm_u_cmm_dataproducer_N_57728), + .I1(com_cmm_u_cmm_dataproducer_N_61299), + .I2(com_cmm_msi_laddr[10]), + .I3(com_cmm_u_cmm_dataproducer_req_gnt_code[0]), + .LO(com_cmm_u_cmm_dataproducer_byte_10_17_1_0_0[2]) + ); + defparam com_cmm_u_cmm_dataproducer_byte_09_17_1_0_0_2_.INIT = 16'h5515; + LUT4_L com_cmm_u_cmm_dataproducer_byte_09_17_1_0_0_2_ ( + .I0(com_cmm_u_cmm_dataproducer_N_57704), + .I1(com_cmm_u_cmm_dataproducer_N_61299), + .I2(com_cmm_msi_laddr[18]), + .I3(com_cmm_u_cmm_dataproducer_req_gnt_code[0]), + .LO(com_cmm_u_cmm_dataproducer_byte_09_17_1_0_0[2]) + ); + defparam com_cmm_u_cmm_dataproducer_byte_10_17_1_0_0_6_.INIT = 16'h5515; + LUT4_L com_cmm_u_cmm_dataproducer_byte_10_17_1_0_0_6_ ( + .I0(com_cmm_u_cmm_dataproducer_N_57740), + .I1(com_cmm_u_cmm_dataproducer_N_61299), + .I2(com_cmm_msi_laddr[14]), + .I3(com_cmm_u_cmm_dataproducer_req_gnt_code[0]), + .LO(com_cmm_u_cmm_dataproducer_byte_10_17_1_0_0[6]) + ); + defparam com_cmm_u_cmm_dataproducer_byte_10_17_1_0_0_0_.INIT = 16'h5515; + LUT4_L com_cmm_u_cmm_dataproducer_byte_10_17_1_0_0_0_ ( + .I0(com_cmm_u_cmm_dataproducer_N_57722), + .I1(com_cmm_u_cmm_dataproducer_N_61299), + .I2(com_cmm_msi_laddr[8]), + .I3(com_cmm_u_cmm_dataproducer_req_gnt_code[0]), + .LO(com_cmm_u_cmm_dataproducer_byte_10_17_1_0_0[0]) + ); + defparam com_cmm_u_cmm_dataproducer_byte_08_17_1_0_0_4_.INIT = 16'h5515; + LUT4_L com_cmm_u_cmm_dataproducer_byte_08_17_1_0_0_4_ ( + .I0(com_cmm_u_cmm_dataproducer_N_57686), + .I1(com_cmm_u_cmm_dataproducer_N_61299), + .I2(com_cmm_msi_laddr[28]), + .I3(com_cmm_u_cmm_dataproducer_req_gnt_code[0]), + .LO(com_cmm_u_cmm_dataproducer_byte_08_17_1_0_0[4]) + ); + defparam com_cmm_u_cmm_dataproducer_byte_10_17_1_0_0_1_.INIT = 16'h5515; + LUT4_L com_cmm_u_cmm_dataproducer_byte_10_17_1_0_0_1_ ( + .I0(com_cmm_u_cmm_dataproducer_N_57725), + .I1(com_cmm_u_cmm_dataproducer_N_61299), + .I2(com_cmm_msi_laddr[9]), + .I3(com_cmm_u_cmm_dataproducer_req_gnt_code[0]), + .LO(com_cmm_u_cmm_dataproducer_byte_10_17_1_0_0[1]) + ); + defparam com_cmm_u_cmm_dataproducer_byte_10_17_1_0_0_4_.INIT = 16'h5515; + LUT4_L com_cmm_u_cmm_dataproducer_byte_10_17_1_0_0_4_ ( + .I0(com_cmm_u_cmm_dataproducer_N_57734), + .I1(com_cmm_u_cmm_dataproducer_N_61299), + .I2(com_cmm_msi_laddr[12]), + .I3(com_cmm_u_cmm_dataproducer_req_gnt_code[0]), + .LO(com_cmm_u_cmm_dataproducer_byte_10_17_1_0_0[4]) + ); + defparam com_cmm_u_cmm_dataproducer_byte_08_17_1_0_0_7_.INIT = 16'h5515; + LUT4_L com_cmm_u_cmm_dataproducer_byte_08_17_1_0_0_7_ ( + .I0(com_cmm_u_cmm_dataproducer_N_57695), + .I1(com_cmm_u_cmm_dataproducer_N_61299), + .I2(com_cmm_msi_laddr[31]), + .I3(com_cmm_u_cmm_dataproducer_req_gnt_code[0]), + .LO(com_cmm_u_cmm_dataproducer_byte_08_17_1_0_0[7]) + ); + defparam com_cmm_u_cmm_dataproducer_byte_09_17_1_0_0_6_.INIT = 16'h5515; + LUT4_L com_cmm_u_cmm_dataproducer_byte_09_17_1_0_0_6_ ( + .I0(com_cmm_u_cmm_dataproducer_N_57716), + .I1(com_cmm_u_cmm_dataproducer_N_61299), + .I2(com_cmm_msi_laddr[22]), + .I3(com_cmm_u_cmm_dataproducer_req_gnt_code[0]), + .LO(com_cmm_u_cmm_dataproducer_byte_09_17_1_0_0[6]) + ); + defparam com_cmm_u_cmm_dataproducer_byte_10_17_1_0_0_3_.INIT = 16'h5515; + LUT4_L com_cmm_u_cmm_dataproducer_byte_10_17_1_0_0_3_ ( + .I0(com_cmm_u_cmm_dataproducer_N_57731), + .I1(com_cmm_u_cmm_dataproducer_N_61299), + .I2(com_cmm_msi_laddr[11]), + .I3(com_cmm_u_cmm_dataproducer_req_gnt_code[0]), + .LO(com_cmm_u_cmm_dataproducer_byte_10_17_1_0_0[3]) + ); + defparam com_cmm_u_cmm_dataproducer_byte_09_17_1_0_0_5_.INIT = 16'h5515; + LUT4_L com_cmm_u_cmm_dataproducer_byte_09_17_1_0_0_5_ ( + .I0(com_cmm_u_cmm_dataproducer_N_57713), + .I1(com_cmm_u_cmm_dataproducer_N_61299), + .I2(com_cmm_msi_laddr[21]), + .I3(com_cmm_u_cmm_dataproducer_req_gnt_code[0]), + .LO(com_cmm_u_cmm_dataproducer_byte_09_17_1_0_0[5]) + ); + defparam com_cmm_u_cmm_dataproducer_byte_10_17_1_0_0_7_.INIT = 16'h5515; + LUT4_L com_cmm_u_cmm_dataproducer_byte_10_17_1_0_0_7_ ( + .I0(com_cmm_u_cmm_dataproducer_N_57743), + .I1(com_cmm_u_cmm_dataproducer_N_61299), + .I2(com_cmm_msi_laddr[15]), + .I3(com_cmm_u_cmm_dataproducer_req_gnt_code[0]), + .LO(com_cmm_u_cmm_dataproducer_byte_10_17_1_0_0[7]) + ); + defparam com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_am_5_.INIT = 4'h8; + LUT2 com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_am_5_ ( + .I0(com_cmm_u_cmm_dataproducer_N_61317), + .I1(com_cmm_cfg_rd_data[29]), + .O(com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_am[5]) + ); + defparam com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_bm_5_.INIT = 8'hC8; + LUT3 com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_bm_5_ ( + .I0(com_cmm_u_cmm_dataproducer_N_61317), + .I1(com_cmm_msi_laddr[5]), + .I2(com_cmm_u_cmm_dataproducer_req_gnt_code[0]), + .O(com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_bm[5]) + ); + MUXF5 com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_5_ ( + .I0(com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_am[5]), + .I1(com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_bm[5]), + .O(com_cmm_u_cmm_dataproducer_bytes_12_to_15_17[5]), + .S(com_cmm_u_cmm_dataproducer_N_61299) + ); + defparam com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_am_6_.INIT = 4'h8; + LUT2 com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_am_6_ ( + .I0(com_cmm_u_cmm_dataproducer_N_61317), + .I1(com_cmm_cfg_rd_data[30]), + .O(com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_am[6]) + ); + defparam com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_bm_6_.INIT = 8'hC8; + LUT3 com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_bm_6_ ( + .I0(com_cmm_u_cmm_dataproducer_N_61317), + .I1(com_cmm_msi_laddr[6]), + .I2(com_cmm_u_cmm_dataproducer_req_gnt_code[0]), + .O(com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_bm[6]) + ); + MUXF5 com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_6_ ( + .I0(com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_am[6]), + .I1(com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_bm[6]), + .O(com_cmm_u_cmm_dataproducer_bytes_12_to_15_17[6]), + .S(com_cmm_u_cmm_dataproducer_N_61299) + ); + defparam com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_am_7_.INIT = 4'h8; + LUT2 com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_am_7_ ( + .I0(com_cmm_u_cmm_dataproducer_N_61317), + .I1(com_cmm_cfg_rd_data[31]), + .O(com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_am[7]) + ); + defparam com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_bm_7_.INIT = 8'hC8; + LUT3 com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_bm_7_ ( + .I0(com_cmm_u_cmm_dataproducer_N_61317), + .I1(com_cmm_msi_laddr[7]), + .I2(com_cmm_u_cmm_dataproducer_req_gnt_code[0]), + .O(com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_bm[7]) + ); + MUXF5 com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_7_ ( + .I0(com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_am[7]), + .I1(com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_bm[7]), + .O(com_cmm_u_cmm_dataproducer_bytes_12_to_15_17[7]), + .S(com_cmm_u_cmm_dataproducer_N_61299) + ); + defparam com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_am_8_.INIT = 4'h8; + LUT2 com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_am_8_ ( + .I0(com_cmm_u_cmm_dataproducer_N_61317), + .I1(com_cmm_cfg_rd_data[16]), + .O(com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_am[8]) + ); + defparam com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_bm_8_.INIT = 8'hC8; + LUT3 com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_bm_8_ ( + .I0(com_cmm_u_cmm_dataproducer_N_61317), + .I1(com_cmm_msi_laddr[8]), + .I2(com_cmm_u_cmm_dataproducer_req_gnt_code[0]), + .O(com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_bm[8]) + ); + MUXF5 com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_8_ ( + .I0(com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_am[8]), + .I1(com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_bm[8]), + .O(com_cmm_u_cmm_dataproducer_bytes_12_to_15_17[8]), + .S(com_cmm_u_cmm_dataproducer_N_61299) + ); + defparam com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_am_10_.INIT = 4'h8; + LUT2 com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_am_10_ ( + .I0(com_cmm_u_cmm_dataproducer_N_61317), + .I1(com_cmm_cfg_rd_data[18]), + .O(com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_am[10]) + ); + defparam com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_bm_10_.INIT = 8'hC8; + LUT3 com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_bm_10_ ( + .I0(com_cmm_u_cmm_dataproducer_N_61317), + .I1(com_cmm_msi_laddr[10]), + .I2(com_cmm_u_cmm_dataproducer_req_gnt_code[0]), + .O(com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_bm[10]) + ); + MUXF5 com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_10_ ( + .I0(com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_am[10]), + .I1(com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_bm[10]), + .O(com_cmm_u_cmm_dataproducer_bytes_12_to_15_17[10]), + .S(com_cmm_u_cmm_dataproducer_N_61299) + ); + defparam com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_am_11_.INIT = 4'h8; + LUT2 com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_am_11_ ( + .I0(com_cmm_u_cmm_dataproducer_N_61317), + .I1(com_cmm_cfg_rd_data[19]), + .O(com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_am[11]) + ); + defparam com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_bm_11_.INIT = 8'hC8; + LUT3 com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_bm_11_ ( + .I0(com_cmm_u_cmm_dataproducer_N_61317), + .I1(com_cmm_msi_laddr[11]), + .I2(com_cmm_u_cmm_dataproducer_req_gnt_code[0]), + .O(com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_bm[11]) + ); + MUXF5 com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_11_ ( + .I0(com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_am[11]), + .I1(com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_bm[11]), + .O(com_cmm_u_cmm_dataproducer_bytes_12_to_15_17[11]), + .S(com_cmm_u_cmm_dataproducer_N_61299) + ); + defparam com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_am_13_.INIT = 4'h8; + LUT2 com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_am_13_ ( + .I0(com_cmm_u_cmm_dataproducer_N_61317), + .I1(com_cmm_cfg_rd_data[21]), + .O(com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_am[13]) + ); + defparam com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_bm_13_.INIT = 8'hC8; + LUT3 com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_bm_13_ ( + .I0(com_cmm_u_cmm_dataproducer_N_61317), + .I1(com_cmm_msi_laddr[13]), + .I2(com_cmm_u_cmm_dataproducer_req_gnt_code[0]), + .O(com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_bm[13]) + ); + MUXF5 com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_13_ ( + .I0(com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_am[13]), + .I1(com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_bm[13]), + .O(com_cmm_u_cmm_dataproducer_bytes_12_to_15_17[13]), + .S(com_cmm_u_cmm_dataproducer_N_61299) + ); + defparam com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_am_14_.INIT = 4'h8; + LUT2 com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_am_14_ ( + .I0(com_cmm_u_cmm_dataproducer_N_61317), + .I1(com_cmm_cfg_rd_data[22]), + .O(com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_am[14]) + ); + defparam com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_bm_14_.INIT = 8'hC8; + LUT3 com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_bm_14_ ( + .I0(com_cmm_u_cmm_dataproducer_N_61317), + .I1(com_cmm_msi_laddr[14]), + .I2(com_cmm_u_cmm_dataproducer_req_gnt_code[0]), + .O(com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_bm[14]) + ); + MUXF5 com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_14_ ( + .I0(com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_am[14]), + .I1(com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_bm[14]), + .O(com_cmm_u_cmm_dataproducer_bytes_12_to_15_17[14]), + .S(com_cmm_u_cmm_dataproducer_N_61299) + ); + defparam com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_am_15_.INIT = 4'h8; + LUT2 com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_am_15_ ( + .I0(com_cmm_u_cmm_dataproducer_N_61317), + .I1(com_cmm_cfg_rd_data[23]), + .O(com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_am[15]) + ); + defparam com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_bm_15_.INIT = 8'hC8; + LUT3 com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_bm_15_ ( + .I0(com_cmm_u_cmm_dataproducer_N_61317), + .I1(com_cmm_msi_laddr[15]), + .I2(com_cmm_u_cmm_dataproducer_req_gnt_code[0]), + .O(com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_bm[15]) + ); + MUXF5 com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_15_ ( + .I0(com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_am[15]), + .I1(com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_bm[15]), + .O(com_cmm_u_cmm_dataproducer_bytes_12_to_15_17[15]), + .S(com_cmm_u_cmm_dataproducer_N_61299) + ); + defparam com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_am_12_.INIT = 4'h8; + LUT2 com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_am_12_ ( + .I0(com_cmm_u_cmm_dataproducer_N_61317), + .I1(com_cmm_cfg_rd_data[20]), + .O(com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_am[12]) + ); + defparam com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_bm_12_.INIT = 8'hC8; + LUT3 com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_bm_12_ ( + .I0(com_cmm_u_cmm_dataproducer_N_61317), + .I1(com_cmm_msi_laddr[12]), + .I2(com_cmm_u_cmm_dataproducer_req_gnt_code[0]), + .O(com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_bm[12]) + ); + MUXF5 com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_12_ ( + .I0(com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_am[12]), + .I1(com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_bm[12]), + .O(com_cmm_u_cmm_dataproducer_bytes_12_to_15_17[12]), + .S(com_cmm_u_cmm_dataproducer_N_61299) + ); + defparam com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_am_9_.INIT = 4'h8; + LUT2 com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_am_9_ ( + .I0(com_cmm_u_cmm_dataproducer_N_61317), + .I1(com_cmm_cfg_rd_data[17]), + .O(com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_am[9]) + ); + defparam com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_bm_9_.INIT = 8'hC8; + LUT3 com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_bm_9_ ( + .I0(com_cmm_u_cmm_dataproducer_N_61317), + .I1(com_cmm_msi_laddr[9]), + .I2(com_cmm_u_cmm_dataproducer_req_gnt_code[0]), + .O(com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_bm[9]) + ); + MUXF5 com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_9_ ( + .I0(com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_am[9]), + .I1(com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_bm[9]), + .O(com_cmm_u_cmm_dataproducer_bytes_12_to_15_17[9]), + .S(com_cmm_u_cmm_dataproducer_N_61299) + ); + defparam com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_am_4_.INIT = 4'h8; + LUT2 com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_am_4_ ( + .I0(com_cmm_u_cmm_dataproducer_N_61317), + .I1(com_cmm_cfg_rd_data[28]), + .O(com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_am[4]) + ); + defparam com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_bm_4_.INIT = 8'hC8; + LUT3 com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_bm_4_ ( + .I0(com_cmm_u_cmm_dataproducer_N_61317), + .I1(com_cmm_msi_laddr[4]), + .I2(com_cmm_u_cmm_dataproducer_req_gnt_code[0]), + .O(com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_bm[4]) + ); + MUXF5 com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_4_ ( + .I0(com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_am[4]), + .I1(com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_bm[4]), + .O(com_cmm_u_cmm_dataproducer_bytes_12_to_15_17[4]), + .S(com_cmm_u_cmm_dataproducer_N_61299) + ); + defparam com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_am_3_.INIT = 4'h8; + LUT2 com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_am_3_ ( + .I0(com_cmm_u_cmm_dataproducer_N_61317), + .I1(com_cmm_cfg_rd_data[27]), + .O(com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_am[3]) + ); + defparam com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_bm_3_.INIT = 8'hC8; + LUT3 com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_bm_3_ ( + .I0(com_cmm_u_cmm_dataproducer_N_61317), + .I1(com_cmm_msi_laddr[3]), + .I2(com_cmm_u_cmm_dataproducer_req_gnt_code[0]), + .O(com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_bm[3]) + ); + MUXF5 com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_3_ ( + .I0(com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_am[3]), + .I1(com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_bm[3]), + .O(com_cmm_u_cmm_dataproducer_bytes_12_to_15_17[3]), + .S(com_cmm_u_cmm_dataproducer_N_61299) + ); + defparam com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_am_2_.INIT = 4'h8; + LUT2 com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_am_2_ ( + .I0(com_cmm_u_cmm_dataproducer_N_61317), + .I1(com_cmm_cfg_rd_data[26]), + .O(com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_am[2]) + ); + defparam com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_bm_2_.INIT = 8'hC8; + LUT3 com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_bm_2_ ( + .I0(com_cmm_u_cmm_dataproducer_N_61317), + .I1(com_cmm_msi_laddr[2]), + .I2(com_cmm_u_cmm_dataproducer_req_gnt_code[0]), + .O(com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_bm[2]) + ); + MUXF5 com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_2_ ( + .I0(com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_am[2]), + .I1(com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_bm[2]), + .O(com_cmm_u_cmm_dataproducer_bytes_12_to_15_17[2]), + .S(com_cmm_u_cmm_dataproducer_N_61299) + ); + defparam com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_am_16_.INIT = 4'h8; + LUT2 com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_am_16_ ( + .I0(com_cmm_u_cmm_dataproducer_N_61317), + .I1(com_cmm_cfg_rd_data[8]), + .O(com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_am[16]) + ); + defparam com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_bm_16_.INIT = 16'hF0E4; + LUT4 com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_bm_16_ ( + .I0(com_cmm_u_cmm_dataproducer_N_61317), + .I1(com_cmm_msi_data[8]), + .I2(com_cmm_msi_laddr[16]), + .I3(com_cmm_u_cmm_dataproducer_req_gnt_code[0]), + .O(com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_bm[16]) + ); + MUXF5 com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_16_ ( + .I0(com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_am[16]), + .I1(com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_bm[16]), + .O(com_cmm_u_cmm_dataproducer_bytes_12_to_15_17[16]), + .S(com_cmm_u_cmm_dataproducer_N_61299) + ); + defparam com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_am_17_.INIT = 4'h8; + LUT2 com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_am_17_ ( + .I0(com_cmm_u_cmm_dataproducer_N_61317), + .I1(com_cmm_cfg_rd_data[9]), + .O(com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_am[17]) + ); + defparam com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_bm_17_.INIT = 16'hF0E4; + LUT4 com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_bm_17_ ( + .I0(com_cmm_u_cmm_dataproducer_N_61317), + .I1(com_cmm_msi_data[9]), + .I2(com_cmm_msi_laddr[17]), + .I3(com_cmm_u_cmm_dataproducer_req_gnt_code[0]), + .O(com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_bm[17]) + ); + MUXF5 com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_17_ ( + .I0(com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_am[17]), + .I1(com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_bm[17]), + .O(com_cmm_u_cmm_dataproducer_bytes_12_to_15_17[17]), + .S(com_cmm_u_cmm_dataproducer_N_61299) + ); + defparam com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_am_19_.INIT = 4'h8; + LUT2 com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_am_19_ ( + .I0(com_cmm_u_cmm_dataproducer_N_61317), + .I1(com_cmm_cfg_rd_data[11]), + .O(com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_am[19]) + ); + defparam com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_bm_19_.INIT = 16'hF0E4; + LUT4 com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_bm_19_ ( + .I0(com_cmm_u_cmm_dataproducer_N_61317), + .I1(com_cmm_msi_data[11]), + .I2(com_cmm_msi_laddr[19]), + .I3(com_cmm_u_cmm_dataproducer_req_gnt_code[0]), + .O(com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_bm[19]) + ); + MUXF5 com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_19_ ( + .I0(com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_am[19]), + .I1(com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_bm[19]), + .O(com_cmm_u_cmm_dataproducer_bytes_12_to_15_17[19]), + .S(com_cmm_u_cmm_dataproducer_N_61299) + ); + defparam com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_am_20_.INIT = 4'h8; + LUT2 com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_am_20_ ( + .I0(com_cmm_u_cmm_dataproducer_N_61317), + .I1(com_cmm_cfg_rd_data[12]), + .O(com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_am[20]) + ); + defparam com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_bm_20_.INIT = 16'hF0E4; + LUT4 com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_bm_20_ ( + .I0(com_cmm_u_cmm_dataproducer_N_61317), + .I1(com_cmm_msi_data[12]), + .I2(com_cmm_msi_laddr[20]), + .I3(com_cmm_u_cmm_dataproducer_req_gnt_code[0]), + .O(com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_bm[20]) + ); + MUXF5 com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_20_ ( + .I0(com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_am[20]), + .I1(com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_bm[20]), + .O(com_cmm_u_cmm_dataproducer_bytes_12_to_15_17[20]), + .S(com_cmm_u_cmm_dataproducer_N_61299) + ); + defparam com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_am_21_.INIT = 4'h8; + LUT2 com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_am_21_ ( + .I0(com_cmm_u_cmm_dataproducer_N_61317), + .I1(com_cmm_cfg_rd_data[13]), + .O(com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_am[21]) + ); + defparam com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_bm_21_.INIT = 16'hF0E4; + LUT4 com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_bm_21_ ( + .I0(com_cmm_u_cmm_dataproducer_N_61317), + .I1(com_cmm_msi_data[13]), + .I2(com_cmm_msi_laddr[21]), + .I3(com_cmm_u_cmm_dataproducer_req_gnt_code[0]), + .O(com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_bm[21]) + ); + MUXF5 com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_21_ ( + .I0(com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_am[21]), + .I1(com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_bm[21]), + .O(com_cmm_u_cmm_dataproducer_bytes_12_to_15_17[21]), + .S(com_cmm_u_cmm_dataproducer_N_61299) + ); + defparam com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_am_23_.INIT = 4'h8; + LUT2 com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_am_23_ ( + .I0(com_cmm_u_cmm_dataproducer_N_61317), + .I1(com_cmm_cfg_rd_data[15]), + .O(com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_am[23]) + ); + defparam com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_bm_23_.INIT = 16'hF0E4; + LUT4 com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_bm_23_ ( + .I0(com_cmm_u_cmm_dataproducer_N_61317), + .I1(com_cmm_msi_data[15]), + .I2(com_cmm_msi_laddr[23]), + .I3(com_cmm_u_cmm_dataproducer_req_gnt_code[0]), + .O(com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_bm[23]) + ); + MUXF5 com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_23_ ( + .I0(com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_am[23]), + .I1(com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_bm[23]), + .O(com_cmm_u_cmm_dataproducer_bytes_12_to_15_17[23]), + .S(com_cmm_u_cmm_dataproducer_N_61299) + ); + defparam com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_am_24_.INIT = 4'h8; + LUT2 com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_am_24_ ( + .I0(com_cmm_u_cmm_dataproducer_N_61317), + .I1(com_cmm_cfg_rd_data[0]), + .O(com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_am[24]) + ); + defparam com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_bm_24_.INIT = 16'hF0E4; + LUT4 com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_bm_24_ ( + .I0(com_cmm_u_cmm_dataproducer_N_61317), + .I1(com_cmm_msi_data[0]), + .I2(com_cmm_msi_laddr[24]), + .I3(com_cmm_u_cmm_dataproducer_req_gnt_code[0]), + .O(com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_bm[24]) + ); + MUXF5 com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_24_ ( + .I0(com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_am[24]), + .I1(com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_bm[24]), + .O(com_cmm_u_cmm_dataproducer_bytes_12_to_15_17[24]), + .S(com_cmm_u_cmm_dataproducer_N_61299) + ); + defparam com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_am_25_.INIT = 4'h8; + LUT2 com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_am_25_ ( + .I0(com_cmm_u_cmm_dataproducer_N_61317), + .I1(com_cmm_cfg_rd_data[1]), + .O(com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_am[25]) + ); + defparam com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_bm_25_.INIT = 16'hF0E4; + LUT4 com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_bm_25_ ( + .I0(com_cmm_u_cmm_dataproducer_N_61317), + .I1(com_cmm_msi_data[1]), + .I2(com_cmm_msi_laddr[25]), + .I3(com_cmm_u_cmm_dataproducer_req_gnt_code[0]), + .O(com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_bm[25]) + ); + MUXF5 com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_25_ ( + .I0(com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_am[25]), + .I1(com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_bm[25]), + .O(com_cmm_u_cmm_dataproducer_bytes_12_to_15_17[25]), + .S(com_cmm_u_cmm_dataproducer_N_61299) + ); + defparam com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_am_26_.INIT = 4'h8; + LUT2 com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_am_26_ ( + .I0(com_cmm_u_cmm_dataproducer_N_61317), + .I1(com_cmm_cfg_rd_data[2]), + .O(com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_am[26]) + ); + defparam com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_bm_26_.INIT = 16'hF0E4; + LUT4 com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_bm_26_ ( + .I0(com_cmm_u_cmm_dataproducer_N_61317), + .I1(com_cmm_msi_data[2]), + .I2(com_cmm_msi_laddr[26]), + .I3(com_cmm_u_cmm_dataproducer_req_gnt_code[0]), + .O(com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_bm[26]) + ); + MUXF5 com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_26_ ( + .I0(com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_am[26]), + .I1(com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_bm[26]), + .O(com_cmm_u_cmm_dataproducer_bytes_12_to_15_17[26]), + .S(com_cmm_u_cmm_dataproducer_N_61299) + ); + defparam com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_am_27_.INIT = 4'h8; + LUT2 com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_am_27_ ( + .I0(com_cmm_u_cmm_dataproducer_N_61317), + .I1(com_cmm_cfg_rd_data[3]), + .O(com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_am[27]) + ); + defparam com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_bm_27_.INIT = 16'hF0E4; + LUT4 com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_bm_27_ ( + .I0(com_cmm_u_cmm_dataproducer_N_61317), + .I1(com_cmm_msi_data[3]), + .I2(com_cmm_msi_laddr[27]), + .I3(com_cmm_u_cmm_dataproducer_req_gnt_code[0]), + .O(com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_bm[27]) + ); + MUXF5 com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_27_ ( + .I0(com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_am[27]), + .I1(com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_bm[27]), + .O(com_cmm_u_cmm_dataproducer_bytes_12_to_15_17[27]), + .S(com_cmm_u_cmm_dataproducer_N_61299) + ); + defparam com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_am_28_.INIT = 4'h8; + LUT2 com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_am_28_ ( + .I0(com_cmm_u_cmm_dataproducer_N_61317), + .I1(com_cmm_cfg_rd_data[4]), + .O(com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_am[28]) + ); + defparam com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_bm_28_.INIT = 16'hF0E4; + LUT4 com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_bm_28_ ( + .I0(com_cmm_u_cmm_dataproducer_N_61317), + .I1(com_cmm_msi_data[4]), + .I2(com_cmm_msi_laddr[28]), + .I3(com_cmm_u_cmm_dataproducer_req_gnt_code[0]), + .O(com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_bm[28]) + ); + MUXF5 com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_28_ ( + .I0(com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_am[28]), + .I1(com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_bm[28]), + .O(com_cmm_u_cmm_dataproducer_bytes_12_to_15_17[28]), + .S(com_cmm_u_cmm_dataproducer_N_61299) + ); + defparam com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_am_29_.INIT = 4'h8; + LUT2 com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_am_29_ ( + .I0(com_cmm_u_cmm_dataproducer_N_61317), + .I1(com_cmm_cfg_rd_data[5]), + .O(com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_am[29]) + ); + defparam com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_bm_29_.INIT = 16'hF0E4; + LUT4 com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_bm_29_ ( + .I0(com_cmm_u_cmm_dataproducer_N_61317), + .I1(com_cmm_msi_data[5]), + .I2(com_cmm_msi_laddr[29]), + .I3(com_cmm_u_cmm_dataproducer_req_gnt_code[0]), + .O(com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_bm[29]) + ); + MUXF5 com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_29_ ( + .I0(com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_am[29]), + .I1(com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_bm[29]), + .O(com_cmm_u_cmm_dataproducer_bytes_12_to_15_17[29]), + .S(com_cmm_u_cmm_dataproducer_N_61299) + ); + defparam com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_am_30_.INIT = 4'h8; + LUT2 com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_am_30_ ( + .I0(com_cmm_u_cmm_dataproducer_N_61317), + .I1(com_cmm_cfg_rd_data[6]), + .O(com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_am[30]) + ); + defparam com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_bm_30_.INIT = 16'hF0E4; + LUT4 com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_bm_30_ ( + .I0(com_cmm_u_cmm_dataproducer_N_61317), + .I1(com_cmm_msi_data[6]), + .I2(com_cmm_msi_laddr[30]), + .I3(com_cmm_u_cmm_dataproducer_req_gnt_code[0]), + .O(com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_bm[30]) + ); + MUXF5 com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_30_ ( + .I0(com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_am[30]), + .I1(com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_bm[30]), + .O(com_cmm_u_cmm_dataproducer_bytes_12_to_15_17[30]), + .S(com_cmm_u_cmm_dataproducer_N_61299) + ); + defparam com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_am_31_.INIT = 4'h8; + LUT2 com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_am_31_ ( + .I0(com_cmm_u_cmm_dataproducer_N_61317), + .I1(com_cmm_cfg_rd_data[7]), + .O(com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_am[31]) + ); + defparam com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_bm_31_.INIT = 16'hF0E4; + LUT4 com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_bm_31_ ( + .I0(com_cmm_u_cmm_dataproducer_N_61317), + .I1(com_cmm_msi_data[7]), + .I2(com_cmm_msi_laddr[31]), + .I3(com_cmm_u_cmm_dataproducer_req_gnt_code[0]), + .O(com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_bm[31]) + ); + MUXF5 com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_31_ ( + .I0(com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_am[31]), + .I1(com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_bm[31]), + .O(com_cmm_u_cmm_dataproducer_bytes_12_to_15_17[31]), + .S(com_cmm_u_cmm_dataproducer_N_61299) + ); + defparam com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_am_22_.INIT = 4'h8; + LUT2 com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_am_22_ ( + .I0(com_cmm_u_cmm_dataproducer_N_61317), + .I1(com_cmm_cfg_rd_data[14]), + .O(com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_am[22]) + ); + defparam com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_bm_22_.INIT = 16'hF0E4; + LUT4 com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_bm_22_ ( + .I0(com_cmm_u_cmm_dataproducer_N_61317), + .I1(com_cmm_msi_data[14]), + .I2(com_cmm_msi_laddr[22]), + .I3(com_cmm_u_cmm_dataproducer_req_gnt_code[0]), + .O(com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_bm[22]) + ); + MUXF5 com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_22_ ( + .I0(com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_am[22]), + .I1(com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_bm[22]), + .O(com_cmm_u_cmm_dataproducer_bytes_12_to_15_17[22]), + .S(com_cmm_u_cmm_dataproducer_N_61299) + ); + defparam com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_am_18_.INIT = 4'h8; + LUT2 com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_am_18_ ( + .I0(com_cmm_u_cmm_dataproducer_N_61317), + .I1(com_cmm_cfg_rd_data[10]), + .O(com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_am[18]) + ); + defparam com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_bm_18_.INIT = 16'hF0E4; + LUT4 com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_bm_18_ ( + .I0(com_cmm_u_cmm_dataproducer_N_61317), + .I1(com_cmm_msi_data[10]), + .I2(com_cmm_msi_laddr[18]), + .I3(com_cmm_u_cmm_dataproducer_req_gnt_code[0]), + .O(com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_bm[18]) + ); + MUXF5 com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_18_ ( + .I0(com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_am[18]), + .I1(com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_bm[18]), + .O(com_cmm_u_cmm_dataproducer_bytes_12_to_15_17[18]), + .S(com_cmm_u_cmm_dataproducer_N_61299) + ); + defparam com_cmm_u_cmm_dataproducer_nxt_req_gnt_state38_0_a2_0_a2_0_a2.INIT = 4'h8; + LUT2_L com_cmm_u_cmm_dataproducer_nxt_req_gnt_state38_0_a2_0_a2_0_a2 ( + .I0(com_cmm_u_cmm_dataproducer_req_gnt_state[0]), + .I1(com_cmm_u_cmm_dataproducer_req_gnt_state[1]), + .LO(com_cmm_u_cmm_dataproducer_nxt_req_gnt_state38) + ); + defparam com_cmm_u_cmm_dataproducer_byte_06_21_0_a2_0_a2_0_a2_7_.INIT = 4'h8; + LUT2_L com_cmm_u_cmm_dataproducer_byte_06_21_0_a2_0_a2_0_a2_7_ ( + .I0(com_cmm_N_56318_i), + .I1(com_cmm_u_cmm_dataproducer_N_61357), + .LO(com_cmm_u_cmm_dataproducer_byte_06_21_7_) + ); + defparam com_cmm_u_cmm_dataproducer_byte_06_21_iv_i_0_i_5_.INIT = 16'h008C; + LUT4_L com_cmm_u_cmm_dataproducer_byte_06_21_iv_i_0_i_5_ ( + .I0(com_cmm_data_errmanager[48]), + .I1(com_cmm_u_cmm_dataproducer_byte_06_21_iv_i_0_i_1[5]), + .I2(com_cmm_u_cmm_dataproducer_req_gnt_code[1]), + .I3(com_cmm_u_cmm_dataproducer_req_gnt_code[2]), + .LO(com_cmm_u_cmm_dataproducer_N_52293_i) + ); + defparam com_cmm_u_cmm_dataproducer_N_58643_i.INIT = 4'h1; + LUT1_L com_cmm_u_cmm_dataproducer_N_58643_i ( + .I0(com_cmm_u_cmm_dataproducer_byte_04_17_i_0_0_a2[0]), + .LO(com_cmm_u_cmm_dataproducer_N_58643_i_6047) + ); + defparam com_cmm_u_cmm_dataproducer_N_86296_i.INIT = 16'hEAC0; + LUT4_L com_cmm_u_cmm_dataproducer_N_86296_i ( + .I0(com_cmm_u_cmm_dataproducer_N_57748_1), + .I1(com_cmm_u_cmm_dataproducer_N_58648), + .I2(com_cmm_attr[1]), + .I3(com_cmm_data_errmanager[25]), + .LO(com_cmm_u_cmm_dataproducer_N_86296_i_6049) + ); + defparam com_cmm_u_cmm_dataproducer_N_86295_i.INIT = 16'hEAC0; + LUT4_L com_cmm_u_cmm_dataproducer_N_86295_i ( + .I0(com_cmm_u_cmm_dataproducer_N_57748_1), + .I1(com_cmm_u_cmm_dataproducer_N_58648), + .I2(com_cmm_attr[0]), + .I3(com_cmm_data_errmanager[24]), + .LO(com_cmm_u_cmm_dataproducer_N_86295_i_6050) + ); + defparam com_cmm_u_cmm_dataproducer_byte_11_17_0_4_.INIT = 16'hEA40; + LUT4_L com_cmm_u_cmm_dataproducer_byte_11_17_0_4_ ( + .I0(com_cmm_u_cmm_dataproducer_N_61299), + .I1(com_cmm_u_cmm_dataproducer_byte_11_17_m0_0_a2_0_a2_i_o2[0]), + .I2(com_cmm_data_errmanager[45]), + .I3(com_cmm_u_cmm_dataproducer_byte_11_17_m0[4]), + .LO(com_cmm_u_cmm_dataproducer_byte_11_17[4]) + ); + defparam com_cmm_u_cmm_dataproducer_byte_11_17_0_3_.INIT = 16'hEA40; + LUT4_L com_cmm_u_cmm_dataproducer_byte_11_17_0_3_ ( + .I0(com_cmm_u_cmm_dataproducer_N_61299), + .I1(com_cmm_u_cmm_dataproducer_byte_11_17_m0_0_a2_0_a2_i_o2[0]), + .I2(com_cmm_data_errmanager[44]), + .I3(com_cmm_u_cmm_dataproducer_byte_11_17_m0[3]), + .LO(com_cmm_u_cmm_dataproducer_byte_11_17[3]) + ); + defparam com_cmm_u_cmm_dataproducer_byte_11_17_0_2_.INIT = 16'hEA40; + LUT4_L com_cmm_u_cmm_dataproducer_byte_11_17_0_2_ ( + .I0(com_cmm_u_cmm_dataproducer_N_61299), + .I1(com_cmm_u_cmm_dataproducer_byte_11_17_m0_0_a2_0_a2_i_o2[0]), + .I2(com_cmm_data_errmanager[43]), + .I3(com_cmm_u_cmm_dataproducer_byte_11_17_m0[2]), + .LO(com_cmm_u_cmm_dataproducer_byte_11_17[2]) + ); + defparam com_cmm_u_cmm_dataproducer_byte_11_17_0_1_.INIT = 16'hC840; + LUT4_L com_cmm_u_cmm_dataproducer_byte_11_17_0_1_ ( + .I0(com_cmm_u_cmm_dataproducer_N_61299), + .I1(com_cmm_u_cmm_dataproducer_byte_11_17_m0_0_a2_0_a2_i_o2[0]), + .I2(com_cmm_data_errmanager[42]), + .I3(com_cmm_msi_haddr[1]), + .LO(com_cmm_u_cmm_dataproducer_byte_11_17[1]) + ); + defparam com_cmm_u_cmm_dataproducer_byte_11_17_0_0_.INIT = 16'hC840; + LUT4_L com_cmm_u_cmm_dataproducer_byte_11_17_0_0_ ( + .I0(com_cmm_u_cmm_dataproducer_N_61299), + .I1(com_cmm_u_cmm_dataproducer_byte_11_17_m0_0_a2_0_a2_i_o2[0]), + .I2(com_cmm_data_errmanager[41]), + .I3(com_cmm_msi_haddr[0]), + .LO(com_cmm_u_cmm_dataproducer_byte_11_17[0]) + ); + defparam com_cmm_u_cmm_dataproducer_byte_07_27_0_0_a2_0_a2_0_a2_7_.INIT = 4'h8; + LUT2_L com_cmm_u_cmm_dataproducer_byte_07_27_0_0_a2_0_a2_0_a2_7_ ( + .I0(com_cmm_u_cmm_dataproducer_N_61357), + .I1(com_cmm_data_errmanager[36]), + .LO(com_cmm_u_cmm_dataproducer_byte_07_27[7]) + ); + defparam com_cmm_u_cmm_dataproducer_byte_07_27_0_0_a2_0_a2_0_a2_6_.INIT = 4'h8; + LUT2_L com_cmm_u_cmm_dataproducer_byte_07_27_0_0_a2_0_a2_0_a2_6_ ( + .I0(com_cmm_u_cmm_dataproducer_N_61357), + .I1(com_cmm_data_errmanager[35]), + .LO(com_cmm_u_cmm_dataproducer_byte_07_27[6]) + ); + defparam com_cmm_u_cmm_dataproducer_N_85894_i.INIT = 8'h8F; + LUT3_L com_cmm_u_cmm_dataproducer_N_85894_i ( + .I0(com_cmm_u_cmm_dataproducer_N_61357), + .I1(com_cmm_data_errmanager[34]), + .I2(com_cmm_u_cmm_dataproducer_byte_07_27_0_1_iv_i_0_0_0[5]), + .LO(com_cmm_u_cmm_dataproducer_N_85894_i_6051) + ); + defparam com_cmm_u_cmm_dataproducer_N_86372_i.INIT = 16'hAAEA; + LUT4_L com_cmm_u_cmm_dataproducer_N_86372_i ( + .I0(N_58537), + .I1(com_cmm_data_errmanager[33]), + .I2(com_cmm_u_cmm_dataproducer_req_gnt_code[1]), + .I3(com_cmm_u_cmm_dataproducer_req_gnt_code[3]), + .LO(com_cmm_u_cmm_dataproducer_N_86372_i_6052) + ); + defparam com_cmm_u_cmm_dataproducer_N_85819_i.INIT = 16'hFEEE; + LUT4_L com_cmm_u_cmm_dataproducer_N_85819_i ( + .I0(com_cmm_u_cmm_dataproducer_N_58650), + .I1(com_cmm_u_cmm_dataproducer_N_61299), + .I2(com_cmm_u_cmm_dataproducer_N_61357), + .I3(com_cmm_data_errmanager[32]), + .LO(com_cmm_u_cmm_dataproducer_N_85819_i_6053) + ); + defparam com_cmm_u_cmm_dataproducer_N_85893_i.INIT = 16'hFEEE; + LUT4_L com_cmm_u_cmm_dataproducer_N_85893_i ( + .I0(com_cmm_u_cmm_dataproducer_N_58647), + .I1(com_cmm_u_cmm_dataproducer_N_58648), + .I2(com_cmm_u_cmm_dataproducer_N_61357), + .I3(com_cmm_data_errmanager[31]), + .LO(com_cmm_u_cmm_dataproducer_N_85893_i_6054) + ); + defparam com_cmm_u_cmm_dataproducer_N_85891_i.INIT = 16'hFEEE; + LUT4_L com_cmm_u_cmm_dataproducer_N_85891_i ( + .I0(com_cmm_u_cmm_dataproducer_N_58534), + .I1(com_cmm_u_cmm_dataproducer_N_58535), + .I2(com_cmm_u_cmm_dataproducer_N_61357), + .I3(com_cmm_data_errmanager[29]), + .LO(com_cmm_u_cmm_dataproducer_N_85891_i_6055) + ); + defparam com_cmm_u_cmm_dataproducer_N_86779_i.INIT = 8'hEA; + LUT3_L com_cmm_u_cmm_dataproducer_N_86779_i ( + .I0(com_cmm_u_cmm_dataproducer_byte_00_19[4]), + .I1(com_cmm_u_cmm_dataproducer_req_gnt_code[0]), + .I2(com_cmm_u_cmm_dataproducer_req_gnt_code[2]), + .LO(com_cmm_u_cmm_dataproducer_N_86779_i_6056) + ); + defparam com_cmm_u_cmm_dataproducer_N_85852_i.INIT = 16'h8F0F; + LUT4_L com_cmm_u_cmm_dataproducer_N_85852_i ( + .I0(com_cmm_u_cmm_dataproducer_N_61299), + .I1(com_cmm_msi_haddr[19]), + .I2(com_cmm_u_cmm_dataproducer_byte_09_17_1_0_0[3]), + .I3(com_cmm_u_cmm_dataproducer_req_gnt_code[0]), + .LO(com_cmm_u_cmm_dataproducer_N_85852_i_6057) + ); + defparam com_cmm_u_cmm_dataproducer_N_85851_i.INIT = 16'h8F0F; + LUT4_L com_cmm_u_cmm_dataproducer_N_85851_i ( + .I0(com_cmm_u_cmm_dataproducer_N_61299), + .I1(com_cmm_msi_haddr[18]), + .I2(com_cmm_u_cmm_dataproducer_byte_09_17_1_0_0[2]), + .I3(com_cmm_u_cmm_dataproducer_req_gnt_code[0]), + .LO(com_cmm_u_cmm_dataproducer_N_85851_i_6058) + ); + defparam com_cmm_u_cmm_dataproducer_N_85850_i.INIT = 16'h8F0F; + LUT4_L com_cmm_u_cmm_dataproducer_N_85850_i ( + .I0(com_cmm_u_cmm_dataproducer_N_61299), + .I1(com_cmm_msi_haddr[17]), + .I2(com_cmm_u_cmm_dataproducer_byte_09_17_1_0_0[1]), + .I3(com_cmm_u_cmm_dataproducer_req_gnt_code[0]), + .LO(com_cmm_u_cmm_dataproducer_N_85850_i_6059) + ); + defparam com_cmm_u_cmm_dataproducer_N_85849_i.INIT = 16'h8F0F; + LUT4_L com_cmm_u_cmm_dataproducer_N_85849_i ( + .I0(com_cmm_u_cmm_dataproducer_N_61299), + .I1(com_cmm_msi_haddr[16]), + .I2(com_cmm_u_cmm_dataproducer_byte_09_17_1_0_0[0]), + .I3(com_cmm_u_cmm_dataproducer_req_gnt_code[0]), + .LO(com_cmm_u_cmm_dataproducer_N_85849_i_6060) + ); + defparam com_cmm_u_cmm_dataproducer_N_85848_i.INIT = 16'h8F0F; + LUT4_L com_cmm_u_cmm_dataproducer_N_85848_i ( + .I0(com_cmm_u_cmm_dataproducer_N_61299), + .I1(com_cmm_msi_haddr[31]), + .I2(com_cmm_u_cmm_dataproducer_byte_08_17_1_0_0[7]), + .I3(com_cmm_u_cmm_dataproducer_req_gnt_code[0]), + .LO(com_cmm_u_cmm_dataproducer_N_85848_i_6061) + ); + defparam com_cmm_u_cmm_dataproducer_N_85847_i.INIT = 16'h8F0F; + LUT4_L com_cmm_u_cmm_dataproducer_N_85847_i ( + .I0(com_cmm_u_cmm_dataproducer_N_61299), + .I1(com_cmm_msi_haddr[30]), + .I2(com_cmm_u_cmm_dataproducer_byte_08_17_1_0_0[6]), + .I3(com_cmm_u_cmm_dataproducer_req_gnt_code[0]), + .LO(com_cmm_u_cmm_dataproducer_N_85847_i_6062) + ); + defparam com_cmm_u_cmm_dataproducer_N_85846_i.INIT = 16'h8F0F; + LUT4_L com_cmm_u_cmm_dataproducer_N_85846_i ( + .I0(com_cmm_u_cmm_dataproducer_N_61299), + .I1(com_cmm_msi_haddr[29]), + .I2(com_cmm_u_cmm_dataproducer_byte_08_17_1_0_0[5]), + .I3(com_cmm_u_cmm_dataproducer_req_gnt_code[0]), + .LO(com_cmm_u_cmm_dataproducer_N_85846_i_6063) + ); + defparam com_cmm_u_cmm_dataproducer_N_85845_i.INIT = 16'h8F0F; + LUT4_L com_cmm_u_cmm_dataproducer_N_85845_i ( + .I0(com_cmm_u_cmm_dataproducer_N_61299), + .I1(com_cmm_msi_haddr[28]), + .I2(com_cmm_u_cmm_dataproducer_byte_08_17_1_0_0[4]), + .I3(com_cmm_u_cmm_dataproducer_req_gnt_code[0]), + .LO(com_cmm_u_cmm_dataproducer_N_85845_i_6064) + ); + defparam com_cmm_u_cmm_dataproducer_N_85844_i.INIT = 16'h8F0F; + LUT4_L com_cmm_u_cmm_dataproducer_N_85844_i ( + .I0(com_cmm_u_cmm_dataproducer_N_61299), + .I1(com_cmm_msi_haddr[27]), + .I2(com_cmm_u_cmm_dataproducer_byte_08_17_1_0_0[3]), + .I3(com_cmm_u_cmm_dataproducer_req_gnt_code[0]), + .LO(com_cmm_u_cmm_dataproducer_N_85844_i_6065) + ); + defparam com_cmm_u_cmm_dataproducer_N_85843_i.INIT = 16'h8F0F; + LUT4_L com_cmm_u_cmm_dataproducer_N_85843_i ( + .I0(com_cmm_u_cmm_dataproducer_N_61299), + .I1(com_cmm_msi_haddr[26]), + .I2(com_cmm_u_cmm_dataproducer_byte_08_17_1_0_0[2]), + .I3(com_cmm_u_cmm_dataproducer_req_gnt_code[0]), + .LO(com_cmm_u_cmm_dataproducer_N_85843_i_6066) + ); + defparam com_cmm_u_cmm_dataproducer_N_85842_i.INIT = 16'h8F0F; + LUT4_L com_cmm_u_cmm_dataproducer_N_85842_i ( + .I0(com_cmm_u_cmm_dataproducer_N_61299), + .I1(com_cmm_msi_haddr[25]), + .I2(com_cmm_u_cmm_dataproducer_byte_08_17_1_0_0[1]), + .I3(com_cmm_u_cmm_dataproducer_req_gnt_code[0]), + .LO(com_cmm_u_cmm_dataproducer_N_85842_i_6067) + ); + defparam com_cmm_u_cmm_dataproducer_N_85841_i.INIT = 16'h8F0F; + LUT4_L com_cmm_u_cmm_dataproducer_N_85841_i ( + .I0(com_cmm_u_cmm_dataproducer_N_61299), + .I1(com_cmm_msi_haddr[24]), + .I2(com_cmm_u_cmm_dataproducer_byte_08_17_1_0_0[0]), + .I3(com_cmm_u_cmm_dataproducer_req_gnt_code[0]), + .LO(com_cmm_u_cmm_dataproducer_N_85841_i_6068) + ); + defparam com_cmm_u_cmm_dataproducer_byte_11_17_0_a2_0_a2_0_a2_7_.INIT = 16'hA280; + LUT4_L com_cmm_u_cmm_dataproducer_byte_11_17_0_a2_0_a2_0_a2_7_ ( + .I0(com_cmm_u_cmm_dataproducer_N_61299), + .I1(com_cmm_u_cmm_dataproducer_byte_11_17_m0_0_a2_0_a2_i_o2[0]), + .I2(com_cmm_msi_haddr[7]), + .I3(com_cmm_msi_laddr[7]), + .LO(com_cmm_u_cmm_dataproducer_byte_11_17[7]) + ); + defparam com_cmm_u_cmm_dataproducer_byte_11_17_0_6_.INIT = 16'hEA40; + LUT4_L com_cmm_u_cmm_dataproducer_byte_11_17_0_6_ ( + .I0(com_cmm_u_cmm_dataproducer_N_61299), + .I1(com_cmm_u_cmm_dataproducer_byte_11_17_m0_0_a2_0_a2_i_o2[0]), + .I2(com_cmm_data_errmanager[47]), + .I3(com_cmm_u_cmm_dataproducer_byte_11_17_m0[6]), + .LO(com_cmm_u_cmm_dataproducer_byte_11_17[6]) + ); + defparam com_cmm_u_cmm_dataproducer_byte_11_17_0_5_.INIT = 16'hEA40; + LUT4_L com_cmm_u_cmm_dataproducer_byte_11_17_0_5_ ( + .I0(com_cmm_u_cmm_dataproducer_N_61299), + .I1(com_cmm_u_cmm_dataproducer_byte_11_17_m0_0_a2_0_a2_i_o2[0]), + .I2(com_cmm_data_errmanager[46]), + .I3(com_cmm_u_cmm_dataproducer_byte_11_17_m0[5]), + .LO(com_cmm_u_cmm_dataproducer_byte_11_17[5]) + ); + defparam com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_a2_0_a2_0_a2_1_.INIT = 4'h8; + LUT2_L com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_a2_0_a2_0_a2_1_ ( + .I0(com_cmm_u_cmm_dataproducer_N_61317), + .I1(com_cmm_cfg_rd_data[25]), + .LO(com_cmm_u_cmm_dataproducer_bytes_12_to_15_17[1]) + ); + defparam com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_a2_0_a2_0_a2_0_.INIT = 4'h8; + LUT2_L com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_0_a2_0_a2_0_a2_0_ ( + .I0(com_cmm_u_cmm_dataproducer_N_61317), + .I1(com_cmm_cfg_rd_data[24]), + .LO(com_cmm_u_cmm_dataproducer_bytes_12_to_15_17[0]) + ); + defparam com_cmm_u_cmm_dataproducer_N_85864_i.INIT = 16'h8F0F; + LUT4_L com_cmm_u_cmm_dataproducer_N_85864_i ( + .I0(com_cmm_u_cmm_dataproducer_N_61299), + .I1(com_cmm_msi_haddr[15]), + .I2(com_cmm_u_cmm_dataproducer_byte_10_17_1_0_0[7]), + .I3(com_cmm_u_cmm_dataproducer_req_gnt_code[0]), + .LO(com_cmm_u_cmm_dataproducer_N_85864_i_6069) + ); + defparam com_cmm_u_cmm_dataproducer_N_85863_i.INIT = 16'h8F0F; + LUT4_L com_cmm_u_cmm_dataproducer_N_85863_i ( + .I0(com_cmm_u_cmm_dataproducer_N_61299), + .I1(com_cmm_msi_haddr[14]), + .I2(com_cmm_u_cmm_dataproducer_byte_10_17_1_0_0[6]), + .I3(com_cmm_u_cmm_dataproducer_req_gnt_code[0]), + .LO(com_cmm_u_cmm_dataproducer_N_85863_i_6070) + ); + defparam com_cmm_u_cmm_dataproducer_N_85862_i.INIT = 16'h8F0F; + LUT4_L com_cmm_u_cmm_dataproducer_N_85862_i ( + .I0(com_cmm_u_cmm_dataproducer_N_61299), + .I1(com_cmm_msi_haddr[13]), + .I2(com_cmm_u_cmm_dataproducer_byte_10_17_1_0_0[5]), + .I3(com_cmm_u_cmm_dataproducer_req_gnt_code[0]), + .LO(com_cmm_u_cmm_dataproducer_N_85862_i_6071) + ); + defparam com_cmm_u_cmm_dataproducer_N_85861_i.INIT = 16'h8F0F; + LUT4_L com_cmm_u_cmm_dataproducer_N_85861_i ( + .I0(com_cmm_u_cmm_dataproducer_N_61299), + .I1(com_cmm_msi_haddr[12]), + .I2(com_cmm_u_cmm_dataproducer_byte_10_17_1_0_0[4]), + .I3(com_cmm_u_cmm_dataproducer_req_gnt_code[0]), + .LO(com_cmm_u_cmm_dataproducer_N_85861_i_6072) + ); + defparam com_cmm_u_cmm_dataproducer_N_85860_i.INIT = 16'h8F0F; + LUT4_L com_cmm_u_cmm_dataproducer_N_85860_i ( + .I0(com_cmm_u_cmm_dataproducer_N_61299), + .I1(com_cmm_msi_haddr[11]), + .I2(com_cmm_u_cmm_dataproducer_byte_10_17_1_0_0[3]), + .I3(com_cmm_u_cmm_dataproducer_req_gnt_code[0]), + .LO(com_cmm_u_cmm_dataproducer_N_85860_i_6073) + ); + defparam com_cmm_u_cmm_dataproducer_N_85859_i.INIT = 16'h8F0F; + LUT4_L com_cmm_u_cmm_dataproducer_N_85859_i ( + .I0(com_cmm_u_cmm_dataproducer_N_61299), + .I1(com_cmm_msi_haddr[10]), + .I2(com_cmm_u_cmm_dataproducer_byte_10_17_1_0_0[2]), + .I3(com_cmm_u_cmm_dataproducer_req_gnt_code[0]), + .LO(com_cmm_u_cmm_dataproducer_N_85859_i_6074) + ); + defparam com_cmm_u_cmm_dataproducer_N_85858_i.INIT = 16'h8F0F; + LUT4_L com_cmm_u_cmm_dataproducer_N_85858_i ( + .I0(com_cmm_u_cmm_dataproducer_N_61299), + .I1(com_cmm_msi_haddr[9]), + .I2(com_cmm_u_cmm_dataproducer_byte_10_17_1_0_0[1]), + .I3(com_cmm_u_cmm_dataproducer_req_gnt_code[0]), + .LO(com_cmm_u_cmm_dataproducer_N_85858_i_6075) + ); + defparam com_cmm_u_cmm_dataproducer_N_85857_i.INIT = 16'h8F0F; + LUT4_L com_cmm_u_cmm_dataproducer_N_85857_i ( + .I0(com_cmm_u_cmm_dataproducer_N_61299), + .I1(com_cmm_msi_haddr[8]), + .I2(com_cmm_u_cmm_dataproducer_byte_10_17_1_0_0[0]), + .I3(com_cmm_u_cmm_dataproducer_req_gnt_code[0]), + .LO(com_cmm_u_cmm_dataproducer_N_85857_i_6076) + ); + defparam com_cmm_u_cmm_dataproducer_N_85856_i.INIT = 16'h8F0F; + LUT4_L com_cmm_u_cmm_dataproducer_N_85856_i ( + .I0(com_cmm_u_cmm_dataproducer_N_61299), + .I1(com_cmm_msi_haddr[23]), + .I2(com_cmm_u_cmm_dataproducer_byte_09_17_0_0_0[7]), + .I3(com_cmm_u_cmm_dataproducer_req_gnt_code[0]), + .LO(com_cmm_u_cmm_dataproducer_N_85856_i_6077) + ); + defparam com_cmm_u_cmm_dataproducer_N_85855_i.INIT = 16'h8F0F; + LUT4_L com_cmm_u_cmm_dataproducer_N_85855_i ( + .I0(com_cmm_u_cmm_dataproducer_N_61299), + .I1(com_cmm_msi_haddr[22]), + .I2(com_cmm_u_cmm_dataproducer_byte_09_17_1_0_0[6]), + .I3(com_cmm_u_cmm_dataproducer_req_gnt_code[0]), + .LO(com_cmm_u_cmm_dataproducer_N_85855_i_6078) + ); + defparam com_cmm_u_cmm_dataproducer_N_85854_i.INIT = 16'h8F0F; + LUT4_L com_cmm_u_cmm_dataproducer_N_85854_i ( + .I0(com_cmm_u_cmm_dataproducer_N_61299), + .I1(com_cmm_msi_haddr[21]), + .I2(com_cmm_u_cmm_dataproducer_byte_09_17_1_0_0[5]), + .I3(com_cmm_u_cmm_dataproducer_req_gnt_code[0]), + .LO(com_cmm_u_cmm_dataproducer_N_85854_i_6079) + ); + defparam com_cmm_u_cmm_dataproducer_N_85853_i.INIT = 16'h8F0F; + LUT4_L com_cmm_u_cmm_dataproducer_N_85853_i ( + .I0(com_cmm_u_cmm_dataproducer_N_61299), + .I1(com_cmm_msi_haddr[20]), + .I2(com_cmm_u_cmm_dataproducer_byte_09_17_1_0_0[4]), + .I3(com_cmm_u_cmm_dataproducer_req_gnt_code[0]), + .LO(com_cmm_u_cmm_dataproducer_N_85853_i_6080) + ); + defparam com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_sn_N_86765_i.INIT = 4'hE; + LUT2_L com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_sn_N_86765_i ( + .I0(com_cmm_u_cmm_dataproducer_N_61299), + .I1(com_cmm_u_cmm_dataproducer_N_61317), + .LO(com_cmm_u_cmm_dataproducer_N_86765_i) + ); + defparam com_cmm_u_cmm_dataproducer_byte_05_17_i_0_0_6_.INIT = 4'h4; + LUT2_L com_cmm_u_cmm_dataproducer_byte_05_17_i_0_0_6_ ( + .I0(com_cmm_u_cmm_dataproducer_byte_04_17_i_0_0_a2[0]), + .I1(NlwRenamedSig_OI_cfg_device_number[3]), + .LO(com_cmm_u_cmm_dataproducer_N_19187_i) + ); + defparam com_cmm_u_cmm_dataproducer_byte_05_17_i_0_0_5_.INIT = 4'h4; + LUT2_L com_cmm_u_cmm_dataproducer_byte_05_17_i_0_0_5_ ( + .I0(com_cmm_u_cmm_dataproducer_byte_04_17_i_0_0_a2[0]), + .I1(NlwRenamedSig_OI_cfg_device_number[2]), + .LO(com_cmm_u_cmm_dataproducer_N_19185_i) + ); + defparam com_cmm_u_cmm_dataproducer_byte_05_17_i_0_0_4_.INIT = 4'h4; + LUT2_L com_cmm_u_cmm_dataproducer_byte_05_17_i_0_0_4_ ( + .I0(com_cmm_u_cmm_dataproducer_byte_04_17_i_0_0_a2[0]), + .I1(NlwRenamedSig_OI_cfg_device_number[1]), + .LO(com_cmm_u_cmm_dataproducer_N_19183_i) + ); + defparam com_cmm_u_cmm_dataproducer_byte_05_17_i_0_0_3_.INIT = 4'h4; + LUT2_L com_cmm_u_cmm_dataproducer_byte_05_17_i_0_0_3_ ( + .I0(com_cmm_u_cmm_dataproducer_byte_04_17_i_0_0_a2[0]), + .I1(NlwRenamedSig_OI_cfg_device_number[0]), + .LO(com_cmm_u_cmm_dataproducer_N_19181_i) + ); + defparam com_cmm_u_cmm_dataproducer_byte_04_17_i_0_0_7_.INIT = 4'h4; + LUT2_L com_cmm_u_cmm_dataproducer_byte_04_17_i_0_0_7_ ( + .I0(com_cmm_u_cmm_dataproducer_byte_04_17_i_0_0_a2[0]), + .I1(NlwRenamedSig_OI_cfg_bus_number[7]), + .LO(com_cmm_u_cmm_dataproducer_N_19179_i) + ); + defparam com_cmm_u_cmm_dataproducer_byte_04_17_i_0_0_6_.INIT = 4'h4; + LUT2_L com_cmm_u_cmm_dataproducer_byte_04_17_i_0_0_6_ ( + .I0(com_cmm_u_cmm_dataproducer_byte_04_17_i_0_0_a2[0]), + .I1(NlwRenamedSig_OI_cfg_bus_number[6]), + .LO(com_cmm_u_cmm_dataproducer_N_19177_i) + ); + defparam com_cmm_u_cmm_dataproducer_byte_04_17_i_0_0_5_.INIT = 4'h4; + LUT2_L com_cmm_u_cmm_dataproducer_byte_04_17_i_0_0_5_ ( + .I0(com_cmm_u_cmm_dataproducer_byte_04_17_i_0_0_a2[0]), + .I1(NlwRenamedSig_OI_cfg_bus_number[5]), + .LO(com_cmm_u_cmm_dataproducer_N_19175_i) + ); + defparam com_cmm_u_cmm_dataproducer_byte_04_17_i_0_0_4_.INIT = 4'h4; + LUT2_L com_cmm_u_cmm_dataproducer_byte_04_17_i_0_0_4_ ( + .I0(com_cmm_u_cmm_dataproducer_byte_04_17_i_0_0_a2[0]), + .I1(NlwRenamedSig_OI_cfg_bus_number[4]), + .LO(com_cmm_u_cmm_dataproducer_N_19173_i) + ); + defparam com_cmm_u_cmm_dataproducer_byte_04_17_i_0_0_3_.INIT = 4'h4; + LUT2_L com_cmm_u_cmm_dataproducer_byte_04_17_i_0_0_3_ ( + .I0(com_cmm_u_cmm_dataproducer_byte_04_17_i_0_0_a2[0]), + .I1(NlwRenamedSig_OI_cfg_bus_number[3]), + .LO(com_cmm_u_cmm_dataproducer_N_19171_i) + ); + defparam com_cmm_u_cmm_dataproducer_byte_04_17_i_0_0_2_.INIT = 4'h4; + LUT2_L com_cmm_u_cmm_dataproducer_byte_04_17_i_0_0_2_ ( + .I0(com_cmm_u_cmm_dataproducer_byte_04_17_i_0_0_a2[0]), + .I1(NlwRenamedSig_OI_cfg_bus_number[2]), + .LO(com_cmm_u_cmm_dataproducer_N_19169_i) + ); + defparam com_cmm_u_cmm_dataproducer_byte_04_17_i_0_0_1_.INIT = 4'h4; + LUT2_L com_cmm_u_cmm_dataproducer_byte_04_17_i_0_0_1_ ( + .I0(com_cmm_u_cmm_dataproducer_byte_04_17_i_0_0_a2[0]), + .I1(NlwRenamedSig_OI_cfg_bus_number[1]), + .LO(com_cmm_u_cmm_dataproducer_N_19167_i) + ); + defparam com_cmm_u_cmm_dataproducer_byte_04_17_i_0_0_0_.INIT = 4'h4; + LUT2_L com_cmm_u_cmm_dataproducer_byte_04_17_i_0_0_0_ ( + .I0(com_cmm_u_cmm_dataproducer_byte_04_17_i_0_0_a2[0]), + .I1(NlwRenamedSig_OI_cfg_bus_number[0]), + .LO(com_cmm_u_cmm_dataproducer_N_19165_i) + ); + defparam com_cmm_u_cmm_dataproducer_byte_01_20_i_0_0_6_.INIT = 16'h2800; + LUT4_L com_cmm_u_cmm_dataproducer_byte_01_20_i_0_0_6_ ( + .I0(com_cmm_data_errmanager[28]), + .I1(com_cmm_data_errmanager[48]), + .I2(com_cmm_data_errmanager[49]), + .I3(com_cmm_u_cmm_dataproducer_byte_01_20_i_0_0_1_1[5]), + .LO(com_cmm_u_cmm_dataproducer_N_17522_i) + ); + defparam com_cmm_u_cmm_dataproducer_byte_01_20_i_0_0_5_.INIT = 16'h2800; + LUT4_L com_cmm_u_cmm_dataproducer_byte_01_20_i_0_0_5_ ( + .I0(com_cmm_data_errmanager[27]), + .I1(com_cmm_data_errmanager[48]), + .I2(com_cmm_data_errmanager[49]), + .I3(com_cmm_u_cmm_dataproducer_byte_01_20_i_0_0_1_1[5]), + .LO(com_cmm_u_cmm_dataproducer_N_17520_i) + ); + defparam com_cmm_u_cmm_dataproducer_byte_01_20_i_0_0_4_.INIT = 16'h2800; + LUT4_L com_cmm_u_cmm_dataproducer_byte_01_20_i_0_0_4_ ( + .I0(com_cmm_data_errmanager[26]), + .I1(com_cmm_data_errmanager[48]), + .I2(com_cmm_data_errmanager[49]), + .I3(com_cmm_u_cmm_dataproducer_byte_01_20_i_0_0_1_1[5]), + .LO(com_cmm_u_cmm_dataproducer_N_17518_i) + ); + defparam com_cmm_u_cmm_dataproducer_byte_06_21_0_a2_0_a2_0_a2_3_.INIT = 4'h8; + LUT2_L com_cmm_u_cmm_dataproducer_byte_06_21_0_a2_0_a2_0_a2_3_ ( + .I0(com_cmm_u_cmm_dataproducer_N_61357), + .I1(com_cmm_data_errmanager[40]), + .LO(com_cmm_u_cmm_dataproducer_byte_06_21_3_) + ); + defparam com_cmm_u_cmm_dataproducer_byte_06_21_0_a2_0_a2_0_a2_2_.INIT = 4'h8; + LUT2_L com_cmm_u_cmm_dataproducer_byte_06_21_0_a2_0_a2_0_a2_2_ ( + .I0(com_cmm_u_cmm_dataproducer_N_61357), + .I1(com_cmm_data_errmanager[39]), + .LO(com_cmm_u_cmm_dataproducer_byte_06_21_2_) + ); + defparam com_cmm_u_cmm_dataproducer_byte_06_21_0_a2_0_a2_0_a2_1_.INIT = 4'h8; + LUT2_L com_cmm_u_cmm_dataproducer_byte_06_21_0_a2_0_a2_0_a2_1_ ( + .I0(com_cmm_u_cmm_dataproducer_N_61357), + .I1(com_cmm_data_errmanager[38]), + .LO(com_cmm_u_cmm_dataproducer_byte_06_21_1_) + ); + defparam com_cmm_u_cmm_dataproducer_byte_06_21_0_a2_0_a2_0_a2_0_.INIT = 4'h8; + LUT2_L com_cmm_u_cmm_dataproducer_byte_06_21_0_a2_0_a2_0_a2_0_ ( + .I0(com_cmm_u_cmm_dataproducer_N_61357), + .I1(com_cmm_data_errmanager[37]), + .LO(com_cmm_u_cmm_dataproducer_byte_06_21_0_) + ); + defparam com_cmm_u_cmm_dataproducer_byte_05_17_i_0_0_7_.INIT = 4'h4; + LUT2_L com_cmm_u_cmm_dataproducer_byte_05_17_i_0_0_7_ ( + .I0(com_cmm_u_cmm_dataproducer_byte_04_17_i_0_0_a2[0]), + .I1(NlwRenamedSig_OI_cfg_device_number[4]), + .LO(com_cmm_u_cmm_dataproducer_N_19189_i) + ); + defparam com_cmm_u_cmm_dataproducer_req_gnt_code_8_i_0_0_3_.INIT = 16'h3200; + LUT4_L com_cmm_u_cmm_dataproducer_req_gnt_code_8_i_0_0_3_ ( + .I0(com_cmm_u_cmm_dataproducer_N_56514_i), + .I1(com_cmm_u_cmm_dataproducer_N_58531), + .I2(com_cmm_req_arbiter[3]), + .I3(com_cmm_u_cmm_dataproducer_req_gnt_code_8_i_0_0_2[3]), + .LO(com_cmm_u_cmm_dataproducer_N_17569_i) + ); + defparam com_cmm_u_cmm_dataproducer_req_gnt_code_8_i_0_0_2_.INIT = 8'h0E; + LUT3_L com_cmm_u_cmm_dataproducer_req_gnt_code_8_i_0_0_2_ ( + .I0(com_cmm_u_cmm_dataproducer_req_gnt_code_8_i_0_0_o3[2]), + .I1(com_cmm_req_arbiter[2]), + .I2(com_cmm_u_cmm_dataproducer_req_gnt_state[0]), + .LO(com_cmm_u_cmm_dataproducer_N_17567_i) + ); + defparam com_cmm_u_cmm_dataproducer_req_gnt_code_8_i_0_0_1_.INIT = 16'h00D8; + LUT4_L com_cmm_u_cmm_dataproducer_req_gnt_code_8_i_0_0_1_ ( + .I0(com_cmm_u_cmm_dataproducer_req_gnt_code_8_i_0_0_o3[2]), + .I1(com_cmm_intr_req_type[1]), + .I2(com_cmm_req_arbiter[1]), + .I3(com_cmm_u_cmm_dataproducer_req_gnt_state[0]), + .LO(com_cmm_u_cmm_dataproducer_N_17565_i) + ); + defparam com_cmm_u_cmm_dataproducer_req_gnt_code_8_i_0_0_0_.INIT = 16'h00D8; + LUT4_L com_cmm_u_cmm_dataproducer_req_gnt_code_8_i_0_0_0_ ( + .I0(com_cmm_u_cmm_dataproducer_req_gnt_code_8_i_0_0_o3[2]), + .I1(com_cmm_intr_req_type[0]), + .I2(com_cmm_req_arbiter[0]), + .I3(com_cmm_u_cmm_dataproducer_req_gnt_state[0]), + .LO(com_cmm_u_cmm_dataproducer_N_17563_i) + ); + defparam com_cmm_u_cmm_dataproducer_req_gnt_state_4_ss0_i_0_0.INIT = 8'hC8; + LUT3_L com_cmm_u_cmm_dataproducer_req_gnt_state_4_ss0_i_0_0 ( + .I0(com_cmm_gnt_pkt_tx), + .I1(com_cmm_u_cmm_dataproducer_req_gnt_state[0]), + .I2(com_cmm_u_cmm_dataproducer_req_gnt_state[1]), + .LO(com_cmm_u_cmm_dataproducer_N_17557_i) + ); + defparam com_cmm_u_cmm_dataproducer_req_gnt_state_4s2_i_0_0.INIT = 16'h0054; + LUT4_L com_cmm_u_cmm_dataproducer_req_gnt_state_4s2_i_0_0 ( + .I0(com_cmm_u_cmm_dataproducer_N_58533), + .I1(com_cmm_u_cmm_dataproducer_pcie_link_state_d[0]), + .I2(com_cmm_u_cmm_dataproducer_req_gnt_state[0]), + .I3(com_cmm_u_cmm_dataproducer_req_gnt_state[1]), + .LO(com_cmm_u_cmm_dataproducer_N_17573_i) + ); + defparam com_cmm_u_cmm_dataproducer_N_85818_i_1.INIT = 16'h5551; + LUT4_L com_cmm_u_cmm_dataproducer_N_85818_i_1 ( + .I0(com_cmm_u_cmm_dataproducer_N_58535), + .I1(N_58537), + .I2(com_cmm_u_cmm_dataproducer_req_gnt_code[0]), + .I3(com_cmm_u_cmm_dataproducer_req_gnt_code[1]), + .LO(com_cmm_u_cmm_dataproducer_N_85818_i_1_6082) + ); + FDC com_cmm_u_cmm_dataproducer_gnt_arbiter ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_dataproducer_nxt_req_gnt_state38), + .Q(com_cmm_gnt_arbiter), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_dataproducer_pcie_link_state_d_0_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_N_60852_i), + .Q(com_cmm_u_cmm_dataproducer_pcie_link_state_d[0]), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_dataproducer_byte_06_7_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_dataproducer_byte_06_21_7_), + .Q(com_cmm_tlp_data_47_), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_dataproducer_byte_06_5_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_dataproducer_N_52293_i), + .Q(com_cmm_tlp_data_45_), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_dataproducer_reg_req_pkt_tx ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_dataproducer_N_58643_i_6047), + .Q(com_cmm_req_pkt_tx), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_dataproducer_byte_00_2_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(N_86294_i_295), + .Q(com_cmm_tlp_data_26_), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_dataproducer_byte_00_1_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_dataproducer_un1_byte_1062_1_i_i_i_a3_6048), + .Q(com_tlp_data_27_), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_dataproducer_byte_00_0_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(m4_3_0_0_0_0_a2_0_294), + .Q(com_cmm_tlp_data_24_), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_dataproducer_byte_02_5_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_dataproducer_N_86296_i_6049), + .Q(com_cmm_tlp_data_13_), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_dataproducer_byte_02_4_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_dataproducer_N_86295_i_6050), + .Q(com_cmm_tlp_data_12_), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_dataproducer_byte_11_4_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_dataproducer_byte_11_17[4]), + .Q(com_cmm_tlp_data_68_), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_dataproducer_byte_11_3_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_dataproducer_byte_11_17[3]), + .Q(com_cmm_tlp_data_67_), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_dataproducer_byte_11_2_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_dataproducer_byte_11_17[2]), + .Q(com_cmm_tlp_data_66_), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_dataproducer_byte_11_1_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_dataproducer_byte_11_17[1]), + .Q(com_cmm_tlp_data_65_), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_dataproducer_byte_11_0_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_dataproducer_byte_11_17[0]), + .Q(com_cmm_tlp_data_64_), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_dataproducer_byte_07_7_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_dataproducer_byte_07_27[7]), + .Q(com_cmm_tlp_data_39_), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_dataproducer_byte_07_6_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_dataproducer_byte_07_27[6]), + .Q(com_cmm_tlp_data_38_), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_dataproducer_byte_07_5_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_dataproducer_N_85894_i_6051), + .Q(com_cmm_tlp_data_37_), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_dataproducer_byte_07_4_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_dataproducer_N_86372_i_6052), + .Q(com_cmm_tlp_data_36_), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_dataproducer_byte_07_3_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_dataproducer_N_85819_i_6053), + .Q(com_cmm_tlp_data_35_), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_dataproducer_byte_07_2_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_dataproducer_N_85893_i_6054), + .Q(com_cmm_tlp_data_34_), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_dataproducer_byte_07_1_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_dataproducer_N_85818_i_6081), + .Q(com_cmm_tlp_data_33_), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_dataproducer_byte_07_0_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_dataproducer_N_85891_i_6055), + .Q(com_cmm_tlp_data_32_), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_dataproducer_byte_00_5_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_dataproducer_N_86779_i_6056), + .Q(com_tlp_data_29_), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_dataproducer_byte_00_4_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_dataproducer_byte_00_19[4]), + .Q(com_cmm_tlp_data_28_), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_dataproducer_byte_09_3_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_dataproducer_N_85852_i_6057), + .Q(com_cmm_tlp_data_83_), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_dataproducer_byte_09_2_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_dataproducer_N_85851_i_6058), + .Q(com_cmm_tlp_data_82_), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_dataproducer_byte_09_1_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_dataproducer_N_85850_i_6059), + .Q(com_cmm_tlp_data_81_), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_dataproducer_byte_09_0_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_dataproducer_N_85849_i_6060), + .Q(com_cmm_tlp_data_80_), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_dataproducer_byte_08_7_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_dataproducer_N_85848_i_6061), + .Q(com_cmm_tlp_data_95_), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_dataproducer_byte_08_6_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_dataproducer_N_85847_i_6062), + .Q(com_cmm_tlp_data_94_), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_dataproducer_byte_08_5_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_dataproducer_N_85846_i_6063), + .Q(com_cmm_tlp_data_93_), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_dataproducer_byte_08_4_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_dataproducer_N_85845_i_6064), + .Q(com_cmm_tlp_data_92_), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_dataproducer_byte_08_3_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_dataproducer_N_85844_i_6065), + .Q(com_cmm_tlp_data_91_), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_dataproducer_byte_08_2_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_dataproducer_N_85843_i_6066), + .Q(com_cmm_tlp_data_90_), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_dataproducer_byte_08_1_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_dataproducer_N_85842_i_6067), + .Q(com_cmm_tlp_data_89_), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_dataproducer_byte_08_0_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_dataproducer_N_85841_i_6068), + .Q(com_cmm_tlp_data_88_), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_dataproducer_byte_11_7_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_dataproducer_byte_11_17[7]), + .Q(com_cmm_tlp_data_71_), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_dataproducer_byte_11_6_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_dataproducer_byte_11_17[6]), + .Q(com_cmm_tlp_data_70_), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_dataproducer_byte_11_5_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_dataproducer_byte_11_17[5]), + .Q(com_cmm_tlp_data_69_), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_dataproducer_bytes_12_to_15_2_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_dataproducer_bytes_12_to_15_17[2]), + .Q(com_cmm_tlp_data_98_), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_dataproducer_bytes_12_to_15_1_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_dataproducer_bytes_12_to_15_17[1]), + .Q(com_cmm_tlp_data_97_), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_dataproducer_bytes_12_to_15_0_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_dataproducer_bytes_12_to_15_17[0]), + .Q(com_cmm_tlp_data_96_), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_dataproducer_byte_10_7_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_dataproducer_N_85864_i_6069), + .Q(com_cmm_tlp_data_79_), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_dataproducer_byte_10_6_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_dataproducer_N_85863_i_6070), + .Q(com_cmm_tlp_data_78_), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_dataproducer_byte_10_5_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_dataproducer_N_85862_i_6071), + .Q(com_cmm_tlp_data_77_), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_dataproducer_byte_10_4_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_dataproducer_N_85861_i_6072), + .Q(com_cmm_tlp_data_76_), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_dataproducer_byte_10_3_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_dataproducer_N_85860_i_6073), + .Q(com_cmm_tlp_data_75_), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_dataproducer_byte_10_2_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_dataproducer_N_85859_i_6074), + .Q(com_cmm_tlp_data_74_), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_dataproducer_byte_10_1_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_dataproducer_N_85858_i_6075), + .Q(com_cmm_tlp_data_73_), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_dataproducer_byte_10_0_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_dataproducer_N_85857_i_6076), + .Q(com_cmm_tlp_data_72_), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_dataproducer_byte_09_7_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_dataproducer_N_85856_i_6077), + .Q(com_cmm_tlp_data_87_), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_dataproducer_byte_09_6_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_dataproducer_N_85855_i_6078), + .Q(com_cmm_tlp_data_86_), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_dataproducer_byte_09_5_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_dataproducer_N_85854_i_6079), + .Q(com_cmm_tlp_data_85_), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_dataproducer_byte_09_4_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_dataproducer_N_85853_i_6080), + .Q(com_cmm_tlp_data_84_), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_dataproducer_bytes_12_to_15_17_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_dataproducer_bytes_12_to_15_17[17]), + .Q(com_cmm_tlp_data_113_), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_dataproducer_bytes_12_to_15_16_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_dataproducer_bytes_12_to_15_17[16]), + .Q(com_cmm_tlp_data_112_), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_dataproducer_bytes_12_to_15_15_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_dataproducer_bytes_12_to_15_17[15]), + .Q(com_cmm_tlp_data_111_), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_dataproducer_bytes_12_to_15_14_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_dataproducer_bytes_12_to_15_17[14]), + .Q(com_cmm_tlp_data_110_), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_dataproducer_bytes_12_to_15_13_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_dataproducer_bytes_12_to_15_17[13]), + .Q(com_cmm_tlp_data_109_), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_dataproducer_bytes_12_to_15_12_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_dataproducer_bytes_12_to_15_17[12]), + .Q(com_cmm_tlp_data_108_), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_dataproducer_bytes_12_to_15_11_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_dataproducer_bytes_12_to_15_17[11]), + .Q(com_cmm_tlp_data_107_), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_dataproducer_bytes_12_to_15_10_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_dataproducer_bytes_12_to_15_17[10]), + .Q(com_cmm_tlp_data_106_), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_dataproducer_bytes_12_to_15_9_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_dataproducer_bytes_12_to_15_17[9]), + .Q(com_cmm_tlp_data_105_), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_dataproducer_bytes_12_to_15_8_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_dataproducer_bytes_12_to_15_17[8]), + .Q(com_cmm_tlp_data_104_), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_dataproducer_bytes_12_to_15_7_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_dataproducer_bytes_12_to_15_17[7]), + .Q(com_cmm_tlp_data_103_), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_dataproducer_bytes_12_to_15_6_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_dataproducer_bytes_12_to_15_17[6]), + .Q(com_cmm_tlp_data_102_), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_dataproducer_bytes_12_to_15_5_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_dataproducer_bytes_12_to_15_17[5]), + .Q(com_cmm_tlp_data_101_), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_dataproducer_bytes_12_to_15_4_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_dataproducer_bytes_12_to_15_17[4]), + .Q(com_cmm_tlp_data_100_), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_dataproducer_bytes_12_to_15_3_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_dataproducer_bytes_12_to_15_17[3]), + .Q(com_cmm_tlp_data_99_), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_dataproducer_byte_03_0_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_dataproducer_N_86765_i), + .Q(com_tlp_data_0_), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_dataproducer_bytes_12_to_15_31_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_dataproducer_bytes_12_to_15_17[31]), + .Q(com_cmm_tlp_data_127_), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_dataproducer_bytes_12_to_15_30_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_dataproducer_bytes_12_to_15_17[30]), + .Q(com_cmm_tlp_data_126_), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_dataproducer_bytes_12_to_15_29_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_dataproducer_bytes_12_to_15_17[29]), + .Q(com_cmm_tlp_data_125_), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_dataproducer_bytes_12_to_15_28_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_dataproducer_bytes_12_to_15_17[28]), + .Q(com_cmm_tlp_data_124_), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_dataproducer_bytes_12_to_15_27_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_dataproducer_bytes_12_to_15_17[27]), + .Q(com_cmm_tlp_data_123_), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_dataproducer_bytes_12_to_15_26_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_dataproducer_bytes_12_to_15_17[26]), + .Q(com_cmm_tlp_data_122_), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_dataproducer_bytes_12_to_15_25_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_dataproducer_bytes_12_to_15_17[25]), + .Q(com_cmm_tlp_data_121_), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_dataproducer_bytes_12_to_15_24_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_dataproducer_bytes_12_to_15_17[24]), + .Q(com_cmm_tlp_data_120_), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_dataproducer_bytes_12_to_15_23_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_dataproducer_bytes_12_to_15_17[23]), + .Q(com_cmm_tlp_data_119_), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_dataproducer_bytes_12_to_15_22_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_dataproducer_bytes_12_to_15_17[22]), + .Q(com_cmm_tlp_data_118_), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_dataproducer_bytes_12_to_15_21_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_dataproducer_bytes_12_to_15_17[21]), + .Q(com_cmm_tlp_data_117_), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_dataproducer_bytes_12_to_15_20_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_dataproducer_bytes_12_to_15_17[20]), + .Q(com_cmm_tlp_data_116_), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_dataproducer_bytes_12_to_15_19_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_dataproducer_bytes_12_to_15_17[19]), + .Q(com_cmm_tlp_data_115_), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_dataproducer_bytes_12_to_15_18_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_dataproducer_bytes_12_to_15_17[18]), + .Q(com_cmm_tlp_data_114_), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_dataproducer_byte_05_6_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_dataproducer_N_19187_i), + .Q(com_cmm_tlp_data_54_), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_dataproducer_byte_05_5_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_dataproducer_N_19185_i), + .Q(com_cmm_tlp_data_53_), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_dataproducer_byte_05_4_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_dataproducer_N_19183_i), + .Q(com_cmm_tlp_data_52_), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_dataproducer_byte_05_3_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_dataproducer_N_19181_i), + .Q(com_cmm_tlp_data_51_), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_dataproducer_byte_04_7_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_dataproducer_N_19179_i), + .Q(com_cmm_tlp_data_63_), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_dataproducer_byte_04_6_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_dataproducer_N_19177_i), + .Q(com_cmm_tlp_data_62_), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_dataproducer_byte_04_5_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_dataproducer_N_19175_i), + .Q(com_cmm_tlp_data_61_), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_dataproducer_byte_04_4_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_dataproducer_N_19173_i), + .Q(com_cmm_tlp_data_60_), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_dataproducer_byte_04_3_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_dataproducer_N_19171_i), + .Q(com_cmm_tlp_data_59_), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_dataproducer_byte_04_2_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_dataproducer_N_19169_i), + .Q(com_cmm_tlp_data_58_), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_dataproducer_byte_04_1_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_dataproducer_N_19167_i), + .Q(com_cmm_tlp_data_57_), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_dataproducer_byte_04_0_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_dataproducer_N_19165_i), + .Q(com_cmm_tlp_data_56_), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_dataproducer_byte_01_6_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_dataproducer_N_17522_i), + .Q(com_cmm_tlp_data_22_), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_dataproducer_byte_01_5_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_dataproducer_N_17520_i), + .Q(com_cmm_tlp_data_21_), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_dataproducer_byte_01_4_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_dataproducer_N_17518_i), + .Q(com_cmm_tlp_data_20_), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_dataproducer_byte_06_3_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_dataproducer_byte_06_21_3_), + .Q(com_cmm_tlp_data_43_), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_dataproducer_byte_06_2_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_dataproducer_byte_06_21_2_), + .Q(com_cmm_tlp_data_42_), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_dataproducer_byte_06_1_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_dataproducer_byte_06_21_1_), + .Q(com_cmm_tlp_data_41_), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_dataproducer_byte_06_0_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_dataproducer_byte_06_21_0_), + .Q(com_cmm_tlp_data_40_), + .CLR(com_cmm_rst_351) + ); + FDC com_cmm_u_cmm_dataproducer_byte_05_7_ ( + .C(NlwRenamedSig_OI_trn_clk), + .D(com_cmm_u_cmm_dataproducer_N_19189_i), + .Q(com_cmm_tlp_data_55_), + .CLR(com_cmm_rst_351) + ); + defparam com_cmm_u_cmm_dataproducer_N_85818_i.INIT = 16'hEAFF; + LUT4_L com_cmm_u_cmm_dataproducer_N_85818_i ( + .I0(com_cmm_u_cmm_dataproducer_N_61299), + .I1(com_cmm_u_cmm_dataproducer_N_61357), + .I2(com_cmm_data_errmanager[30]), + .I3(com_cmm_u_cmm_dataproducer_N_85818_i_1_6082), + .LO(com_cmm_u_cmm_dataproducer_N_85818_i_6081) + ); +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/verilog_analyze_order b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/verilog_analyze_order new file mode 100644 index 0000000..c98b467 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/verilog_analyze_order @@ -0,0 +1,165 @@ +# Verilog Simulation file list. Files are not order dependent. + +# This file is provided to be backward compatible. + +C_BIT_CORRELATOR_V3_0.v +PIPE_BHV_V5_0.v +TRIG_TABLE_V5_0.v +C_SIN_COS_V5_0.v +PIPE_BHV_V5_1.v +TRIG_TABLE_V5_1.v +C_SIN_COS_V5_1.v +C_DA_FIR_V9_0.v +C_DA_FIR_V7_0.v +pci_exp_1_lane_64b_dsport.v +pci_exp_4_lane_64b_dsport.v +FAMILY.v +BLKMEMDP_V6_2.v +BLK_MEM_GEN_V3_1_xst.v +BLK_MEM_GEN_V3_1.v +C_GATE_BIT_BUS_V5_0.v +C_DECODE_BINARY_V5_0.v +C_SHIFT_FD_V5_0.v +C_COUNTER_BINARY_V5_0.v +C_ACCUM_V5_0.v +C_MUX_BIT_V5_0.v +C_GATE_BIT_V5_0.v +C_REG_LD_V5_0.v +PIPELINE_V5_0.v +C_MUX_SLICE_BUFE_V5_0.v +C_REG_FD_V5_0.v +C_COMPARE_V5_0.v +C_TWOS_COMP_V5_0.v +C_ADDSUB_V5_0.v +C_SHIFT_RAM_V5_0.v +C_MUX_BUS_V5_0.v +C_GATE_BUS_V5_0.v +C_ACCUM_V5_1.v +C_MUX_SLICE_BUFT_V5_0.v +BLKMEMDP_V6_3.v +BLK_MEM_GEN_V3_2_xst.v +BLK_MEM_GEN_V3_2.v +BLK_MEM_GEN_V3_3.v +BLK_MEM_GEN_V3_3_xst.v +FIFO_GENERATOR_V5_1_XST.v +FIFO_GENERATOR_V5_1.v +C_DIST_MEM_V5_0.v +FIFO_GENERATOR_V5_2_XST.v +FIFO_GENERATOR_V5_2.v +FIFO_GENERATOR_V5_3.v +FIFO_GENERATOR_V5_3_XST.v +DIST_MEM_GEN_V4_1_XST.v +DIST_MEM_GEN_V4_1.v +BLKMEMSP_V5_0.v +DIST_MEM_GEN_V4_2_XST.v +DIST_MEM_GEN_V4_2.v +DIST_MEM_GEN_V4_3.v +DIST_MEM_GEN_V4_3_XST.v +BLK_MEM_GEN_V4_1_xst.v +BLK_MEM_GEN_V4_1.v +SYNC_FIFO_V5_0.v +C_ADDSUB_V6_0.v +C_SHIFT_RAM_V6_0.v +C_MUX_BUS_V6_0.v +C_GATE_BUS_V6_0.v +C_MUX_SLICE_BUFT_V6_0.v +C_DECODE_BINARY_V6_0.v +C_GATE_BIT_BUS_V6_0.v +C_SHIFT_FD_V6_0.v +C_COUNTER_BINARY_V6_0.v +C_ACCUM_V6_0.v +C_MUX_BIT_V6_0.v +C_GATE_BIT_V6_0.v +C_REG_LD_V6_0.v +PIPELINE_V6_0.v +C_MUX_SLICE_BUFE_V6_0.v +C_COMPARE_V6_0.v +C_REG_FD_V6_0.v +C_TWOS_COMP_V6_0.v +BLK_MEM_GEN_V4_2.v +BLK_MEM_GEN_V4_2_xst.v +FIFO_GENERATOR_V6_1_XST.v +FIFO_GENERATOR_V6_1.v +C_DIST_MEM_V6_0.v +FIFO_GENERATOR_V6_2.v +FIFO_GENERATOR_V6_2_XST.v +BLKMEMDP_V4_0.v +DIST_MEM_GEN_V5_1_XST.v +DIST_MEM_GEN_V5_1.v +BLKMEMSP_V6_0.v +MULT_GEN_V6_0_SEQ.v +MULT_GEN_V6_0_NON_SEQ.v +MULT_GEN_V6_0.v +BLKMEMSP_V6_2.v +CAM_V5_0.v +C_COUNTER_BINARY_V7_0.v +C_ACCUM_V7_0.v +C_MUX_BIT_V7_0.v +C_GATE_BIT_V7_0.v +C_REG_LD_V7_0.v +PIPELINE_V7_0.v +C_MUX_SLICE_BUFE_V7_0.v +C_REG_FD_V7_0.v +C_COMPARE_V7_0.v +C_TWOS_COMP_V7_0.v +C_ADDSUB_V7_0.v +C_SHIFT_RAM_V7_0.v +C_MUX_BUS_V7_0.v +C_GATE_BUS_V7_0.v +C_MUX_SLICE_BUFT_V7_0.v +C_GATE_BIT_BUS_V7_0.v +C_DECODE_BINARY_V7_0.v +C_SHIFT_FD_V7_0.v +CAM_V5_1.v +ASYNC_FIFO_V5_1.v +FIFO_GENERATOR_V3_3_XST.v +FIFO_GENERATOR_V3_3.v +C_DIST_MEM_V7_0.v +C_DIST_MEM_V7_1.v +BLKMEMDP_V5_0.v +MULT_GEN_V7_0_SEQ.v +MULT_GEN_V7_0_NON_SEQ.v +MULT_GEN_V7_0.v +BLK_MEM_GEN_V2_1.v +BLK_MEM_GEN_V2_1_xst.v +C_ADDSUB_V4_0.v +C_SHIFT_RAM_V4_0.v +C_MUX_BUS_V4_0.v +C_GATE_BUS_V4_0.v +C_MUX_SLICE_BUFT_V4_0.v +C_DECODE_BINARY_V4_0.v +C_GATE_BIT_BUS_V4_0.v +C_SHIFT_FD_V4_0.v +C_COUNTER_BINARY_V4_0.v +C_ACCUM_V4_0.v +C_MUX_BIT_V4_0.v +C_GATE_BIT_V4_0.v +C_REG_LD_V4_0.v +PIPELINE_V4_0.v +C_MUX_SLICE_BUFE_V4_0.v +C_COMPARE_V4_0.v +C_REG_FD_V4_0.v +C_TWOS_COMP_V4_0.v +BLK_MEM_GEN_V2_2_xst.v +BLK_MEM_GEN_V2_2.v +BLK_MEM_GEN_V2_4.v +BLK_MEM_GEN_V2_4_xst.v +BLK_MEM_GEN_V2_5.v +BLK_MEM_GEN_V2_5_xst.v +BLK_MEM_GEN_V2_6_xst.v +BLK_MEM_GEN_V2_6.v +CAM_V6_1.v +FIFO_GENERATOR_V4_3_XST.v +FIFO_GENERATOR_V4_3.v +BLK_MEM_GEN_V2_7_xst.v +BLK_MEM_GEN_V2_7.v +FIFO_GENERATOR_V4_4.v +FIFO_GENERATOR_V4_4_XST.v +DIST_MEM_GEN_V3_1.v +BLKMEMSP_V4_0.v +DIST_MEM_GEN_V3_2.v +DIST_MEM_GEN_V3_3.v +DIST_MEM_GEN_V3_4.v +DIST_MEM_GEN_V3_4_XST.v +BLKMEMDP_V6_0.v +BLKMEMDP_V6_1.v diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/AFIFO36_INTERNAL.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/AFIFO36_INTERNAL.v new file mode 100644 index 0000000..0a5ca3a --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/AFIFO36_INTERNAL.v @@ -0,0 +1,1847 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/rainier/AFIFO36_INTERNAL.v,v 1.20 2009/09/10 19:45:20 wloo Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2005 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : This is not an user primitive. +// / / Xilinx Functional Simulation Library Component 36K-Bit FIFO. +// /___/ /\ Filename : AFIFO36_INTERNAL.v +// \ \ / \ Timestamp : Tues July 26 16:44:06 PST 2005 +// \___\/\___\ +// +// Revision: +// 07/26/05 - Initial version. +// 12/16/05 - Added independent read and write ecc features. +// 08/16/06 - Fixed the faulty deassign for invalid rst (CR 234092). +// 10/16/06 - Fixed the unused bits of wrcount and rdcount to match the hardware (CR 426347). +// 01/24/07 - Removed DRC warning for RST in ECC mode (CR 432367). +// 06/01/07 - Added wire declaration for internal signals. +// 06/14/07 - Implemented high performace version of the model. +// 10/26/07 - Changed wren_in to wren_reg to fix FULL flag (CR 452554). +// 11/06/08 - Added DRC for invalid input parity for ECC (CR 482976). +// 03/25/09 - Implemented DRC check for ALMOST_EMPTY_OFFSET (CR 511589). +// 09/10/09 - No ALMOST_EMPTY_OFFSET check when RST is high (CR 531946). +// End Revision + +`timescale 1 ps/1 ps + +module AFIFO36_INTERNAL (ALMOSTEMPTY, ALMOSTFULL, DBITERR, DO, DOP, ECCPARITY, EMPTY, FULL, RDCOUNT, RDERR, SBITERR, WRCOUNT, WRERR, + DI, DIP, RDCLK, RDEN, RDRCLK, RST, WRCLK, WREN); + + output ALMOSTEMPTY; + output ALMOSTFULL; + output DBITERR; + output [63:0] DO; + output [7:0] DOP; + output [7:0] ECCPARITY; + output EMPTY; + output FULL; + output [12:0] RDCOUNT; + output RDERR; + output SBITERR; + output [12:0] WRCOUNT; + output WRERR; + + input [63:0] DI; + input [7:0] DIP; + input RDCLK; + input RDEN; + input RDRCLK; + input RST; + input WRCLK; + input WREN; + + tri0 GSR = glbl.GSR; + + parameter integer DATA_WIDTH = 4; + parameter integer DO_REG = 1; + parameter EN_SYN = "FALSE"; + parameter FIRST_WORD_FALL_THROUGH = "FALSE"; + parameter ALMOST_EMPTY_OFFSET = 13'h0080; + parameter ALMOST_FULL_OFFSET = 13'h0080; + parameter EN_ECC_WRITE = "FALSE"; + parameter EN_ECC_READ = "FALSE"; + parameter SIM_MODE = "SAFE"; + + reg [63:0] do_in = 64'b0; + reg [63:0] do_out = 64'b0; + reg [63:0] do_outreg = 64'b0; + reg [63:0] do_out_mux = 64'b0; + wire [63:0] do_out_out; + reg [7:0] dop_in = 8'b0, dop_out = 8'b0; + wire [7:0] dop_out_out; + reg [7:0] dop_outreg = 8'b0, dop_out_mux = 8'b0; + reg almostempty_out = 1'b1, almostfull_out = 1'b0, empty_out = 1'b1; + reg full_out = 1'b0, rderr_out = 0, wrerr_out = 0; + + reg dbiterr_out = 0, sbiterr_out = 0; + reg dbiterr_out_out = 0, sbiterr_out_out = 0; + reg [71:0] ecc_bit_position; + reg [7:0] eccparity_out; + reg [7:0] dopr_ecc, dop_buf, dip_ecc, dip_int; + reg [63:0] do_buf, di_in_ecc_corrected; + reg [7:0] syndrome, dip_in_ecc_corrected; + + wire [63:0] di_in; + wire [7:0] dip_in; + wire rdclk_in, rden_in, rst_in, wrclk_in, wren_in; + wire rdrclk_in, gsr_in; + + reg rden_reg, wren_reg; + reg [12:0] ae_empty, ae_full; + reg fwft; + + integer addr_limit, rd_prefetch = 0; + integer wr1_addr = 0; + + reg [12:0] rdcount_out = 13'b0, wr_addr = 0, rd_addr = 0; + reg [12:0] rdcount_out_out = 13'h1fff, wr_addr_out = 13'h1fff; + reg rd_flag = 0, rdcount_flag = 0, rdprefetch_flag = 0, wr_flag = 0; + reg wr1_flag = 0, awr_flag = 0; + reg [3:0] almostfull_int = 4'b0000, almostempty_int = 4'b1111; + + reg [3:0] full_int = 4'b0000; + reg [3:0] empty_ram = 4'b1111; + reg [8:0] i, j; + reg rst_tmp1 = 0, rst_tmp2 = 0; + reg [2:0] rst_rdckreg = 3'b0, rst_wrckreg = 3'b0; + reg rst_rdclk_flag = 0, rst_wrclk_flag = 0; + + integer aempty_flag = 0, afull_flag = 0; + time rise_rdclk, period_rdclk, rise_wrclk, period_wrclk; + +// xilinx_internal_parameter on + // WARNING !!!: This model may not work properly if the following parameter is changed. + parameter integer FIFO_SIZE = 36; +// xilinx_internal_parameter off + + localparam mem_size4 = (FIFO_SIZE == 18) ? 4095 : (FIFO_SIZE == 36) ? 8191 : 0; + localparam mem_size9 = (FIFO_SIZE == 18) ? 2047 : (FIFO_SIZE == 36) ? 4095 : 0; + localparam mem_size18 = (FIFO_SIZE == 18) ? 1023 : (FIFO_SIZE == 36) ? 2047 : 0; + localparam mem_size36 = (FIFO_SIZE == 18) ? 511 : (FIFO_SIZE == 36) ? 1023 : 0; + localparam mem_size72 = (FIFO_SIZE == 18) ? 0 : (FIFO_SIZE == 36) ? 511 : 0; + + localparam mem_depth = (DATA_WIDTH == 4) ? mem_size4 : (DATA_WIDTH == 9) ? mem_size9 : + (DATA_WIDTH == 18) ? mem_size18 : (DATA_WIDTH == 36) ? mem_size36 : + (DATA_WIDTH == 72) ? mem_size72 : 0; + + + localparam mem_width = (DATA_WIDTH == 4) ? 3 : (DATA_WIDTH == 9) ? 7 : + (DATA_WIDTH == 18) ? 15 : (DATA_WIDTH == 36) ? 31 : (DATA_WIDTH == 72) ? 63 : 0; + + + localparam memp_depth = (DATA_WIDTH == 4) ? 0 : (DATA_WIDTH == 9) ? mem_size9 : + (DATA_WIDTH == 18) ? mem_size18 : (DATA_WIDTH == 36) ? mem_size36 : + (DATA_WIDTH == 72) ? mem_size72 : 0; + + + localparam memp_width = (DATA_WIDTH == 4 || DATA_WIDTH == 9) ? 0 : + (DATA_WIDTH == 18) ? 1 : (DATA_WIDTH == 36) ? 3 : (DATA_WIDTH == 72) ? 7 : 0; + + reg [mem_width : 0] mem [mem_depth : 0]; + reg [memp_width : 0] memp [memp_depth : 0]; + reg sync; + + initial + if ((SIM_MODE != "FAST") && (SIM_MODE != "SAFE")) begin + $display("Attribute Syntax Error : The attribute SIM_MODE on AFIFO36_INTERNAL instance %m is set to %s. Legal values for this attribute are FAST or SAFE.", SIM_MODE); + $finish; + + end + + + +/********************* SAFE mode **************************/ + generate if (SIM_MODE == "SAFE") begin + + buf b_di[63:0] (di_in, DI); + buf b_dip[7:0] (dip_in, DIP); + buf b_do[63:0] (DO, do_out_out); + buf b_dop[7:0] (DOP, dop_out_out); + buf b_rdclk (rdclk_in, RDCLK); + buf b_rdrclk (rdrclk_in, RDRCLK); + buf b_rden (rden_in, RDEN); + buf b_rst (rst_in, RST); + buf b_wrclk (wrclk_in, WRCLK); + buf b_wren (wren_in, WREN); + buf b_in5 (gsr_in, GSR); + + buf b_out0 (ALMOSTEMPTY, almostempty_out); + buf b_out1 (ALMOSTFULL, almostfull_out); + buf b_empty (EMPTY, empty_out); + buf b_full (FULL, full_out); + buf b_rderr (RDERR, rderr_out); + buf b_wrerr (WRERR, wrerr_out); + buf b_sbiterr (SBITERR, sbiterr_out_out); + buf b_dbiterr (DBITERR, dbiterr_out_out); + buf b_eccparity[7:0] (ECCPARITY, eccparity_out); + buf b_rdcount[12:0] (RDCOUNT, rdcount_out_out); + buf b_wrcount[12:0] (WRCOUNT, wr_addr_out); + + + always @(gsr_in) + if (gsr_in == 1'b1) begin + assign do_out = 64'b0; + assign dop_out = 8'b0; + assign do_outreg = 64'b0; + assign dop_outreg = 8'b0; + end + else if (gsr_in == 1'b0) begin + deassign do_out; + deassign dop_out; + deassign do_outreg; + deassign dop_outreg; + end + + always @(gsr_in or rst_in) + if (gsr_in == 1'b1 || rst_in == 1'b1) begin + assign almostempty_int = 4'b1111; + assign almostempty_out = 1'b1; + assign almostfull_int = 4'b0000; + assign almostfull_out = 1'b0; + assign do_in = 64'b00000000000000000000000000000000; + assign dop_in = 8'b0000; + assign empty_ram = 4'b1111; + assign empty_out = 1'b1; + assign full_int = 4'b0000; + assign full_out = 1'b0; + assign rdcount_out = 13'b0; + assign rdcount_out_out = 13'b0; + assign wr_addr_out = 13'b0; + assign rderr_out = 0; + assign wrerr_out = 0; + assign sbiterr_out_out = 1'b0; + assign dbiterr_out_out = 1'b0; + assign rd_addr = 0; + assign rd_prefetch = 0; + assign wr_addr = 0; + assign wr1_addr = 0; + assign rdcount_flag = 0; + assign rd_flag = 0; + assign rdprefetch_flag = 0; + assign wr_flag = 0; + assign wr1_flag = 0; + assign awr_flag = 0; + end + else if (gsr_in == 1'b0 && rst_in == 1'b0) begin + deassign almostempty_int; + deassign almostempty_out; + deassign almostfull_int; + deassign almostfull_out; + deassign do_in; + deassign dop_in; + deassign empty_ram; + deassign empty_out; + deassign full_int; + deassign full_out; + deassign rdcount_out; + deassign rdcount_out_out; + deassign wr_addr_out; + deassign rderr_out; + deassign wrerr_out; + deassign sbiterr_out_out; + deassign dbiterr_out_out; + deassign rd_addr; + deassign rd_prefetch; + deassign wr_addr; + deassign wr1_addr; + deassign rdcount_flag; + deassign rd_flag; + deassign rdprefetch_flag; + deassign wr_flag; + deassign wr1_flag; + deassign awr_flag; + end + + initial begin + + case (DATA_WIDTH) + 4 : begin + if (FIFO_SIZE == 36) + addr_limit = 8192; + else + addr_limit = 4096; + end + 9 : begin + if (FIFO_SIZE == 36) + addr_limit = 4096; + else + addr_limit = 2048; + end + 18 : begin + if (FIFO_SIZE == 36) + addr_limit = 2048; + else + addr_limit = 1024; + end + 36 : begin + if (FIFO_SIZE == 36) + addr_limit = 1024; + else + addr_limit = 512; + end + 72 : begin + addr_limit = 512; + end + default : + begin + $display("Attribute Syntax Error : The attribute DATA_WIDTH on AFIFO36_INTERNAL instance %m is set to %d. Legal values for this attribute are 4, 9, 18, 36 or 72.", DATA_WIDTH); + $finish; + end + endcase + + + case (EN_SYN) + "FALSE" : sync = 0; + "TRUE" : sync = 1; + default : begin + $display("Attribute Syntax Error : The attribute EN_SYN on AFIFO36_INTERNAL instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", EN_SYN); + $finish; + end + endcase // case(EN_SYN) + + + case (FIRST_WORD_FALL_THROUGH) + "FALSE" : begin + fwft = 0; + if (EN_SYN == "FALSE") begin + ae_empty = ALMOST_EMPTY_OFFSET - 1; + ae_full = ALMOST_FULL_OFFSET; + end + else begin + ae_empty = ALMOST_EMPTY_OFFSET; + ae_full = ALMOST_FULL_OFFSET; + end + end + "TRUE" : begin + fwft = 1; + ae_empty = ALMOST_EMPTY_OFFSET - 2; + ae_full = ALMOST_FULL_OFFSET; + end + default : begin + $display("Attribute Syntax Error : The attribute FIRST_WORD_FALL_THROUGH on AFIFO36_INTERNAL instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", FIRST_WORD_FALL_THROUGH); + $finish; + end + endcase + + + if (EN_SYN == "FALSE") begin + + if (fwft == 1'b0) begin + + if ((ALMOST_EMPTY_OFFSET < 5) || (ALMOST_EMPTY_OFFSET > addr_limit - 5)) begin + $display("Attribute Syntax Error : The attribute ALMOST_EMPTY_OFFSET on AFIFO36_INTERNAL instance %m is set to %d. Legal values for this attribute are %d to %d", ALMOST_EMPTY_OFFSET, 5, addr_limit - 5); + $finish; + end + + if ((ALMOST_FULL_OFFSET < 4) || (ALMOST_FULL_OFFSET > addr_limit - 5)) begin + $display("Attribute Syntax Error : The attribute ALMOST_FULL_OFFSET on AFIFO36_INTERNAL instance %m is set to %d. Legal values for this attribute are %d to %d", ALMOST_FULL_OFFSET, 4, addr_limit - 5); + $finish; + end + + end // if (fwft == 1'b0) + else begin + + if ((ALMOST_EMPTY_OFFSET < 6) || (ALMOST_EMPTY_OFFSET > addr_limit - 4)) begin + $display("Attribute Syntax Error : The attribute ALMOST_EMPTY_OFFSET on AFIFO36_INTERNAL instance %m is set to %d. Legal values for this attribute are %d to %d", ALMOST_EMPTY_OFFSET, 6, addr_limit - 4); + $finish; + end + + if ((ALMOST_FULL_OFFSET < 4) || (ALMOST_FULL_OFFSET > addr_limit - 5)) begin + $display("Attribute Syntax Error : The attribute ALMOST_FULL_OFFSET on AFIFO36_INTERNAL instance %m is set to %d. Legal values for this attribute are %d to %d", ALMOST_FULL_OFFSET, 4, addr_limit - 5); + $finish; + end + + end // else: !if(fwft == 1'b0) + end + else begin + + if ((fwft == 1'b0) && ((ALMOST_EMPTY_OFFSET < 1) || (ALMOST_EMPTY_OFFSET > addr_limit - 2))) begin + $display("Attribute Syntax Error : The attribute ALMOST_EMPTY_OFFSET on AFIFO36_INTERNAL instance %m is set to %d. Legal values for this attribute are %d to %d", ALMOST_EMPTY_OFFSET, 1, addr_limit - 2); + $finish; + end + + if ((fwft == 1'b0) && ((ALMOST_FULL_OFFSET < 1) || (ALMOST_FULL_OFFSET > addr_limit - 2))) begin + $display("Attribute Syntax Error : The attribute ALMOST_FULL_OFFSET on AFIFO36_INTERNAL instance %m is set to %d. Legal values for this attribute are %d to %d", ALMOST_FULL_OFFSET, 1, addr_limit - 2); + $finish; + end + + end // else: !if(EN_SYN == "FALSE") + + + // DRC for fwft in sync mode + if (fwft == 1'b1 && EN_SYN == "TRUE") begin + $display("DRC Error : First word fall through is not supported in synchronous mode on AFIFO36_INTERNAL instance %m."); + $finish; + end + + if (EN_SYN == "FALSE" && DO_REG == 0) begin + $display("DRC Error : DO_REG = 0 is invalid when EN_SYN is set to FALSE on AFIFO36_INTERNAL instance %m."); + $finish; + end + + + if (!(EN_ECC_WRITE == "TRUE" || EN_ECC_WRITE == "FALSE")) begin + $display("Attribute Syntax Error : The attribute EN_ECC_WRITE on AFIFO36_INTERNAL instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", EN_ECC_WRITE); + $finish; + end + + + if (!(EN_ECC_READ == "TRUE" || EN_ECC_READ == "FALSE")) begin + $display("Attribute Syntax Error : The attribute EN_ECC_READ on AFIFO36_INTERNAL instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", EN_ECC_READ); + $finish; + end + + + if ((EN_ECC_READ == "TRUE" || EN_ECC_WRITE == "TRUE") && DATA_WIDTH != 72) begin + $display("DRC Error : The attribute DATA_WIDTH must be set to 72 when AFIFO36_INTERNAL is configured in the ECC mode."); + $finish; + end + + + end // initial begin + + + always @(rst_in or rden_in or wren_in) begin + if (rst_in ==1 && rden_in==1 ) + $display("Warning : At time %t, RDEN on AFIFO36_INTERNAL instance %m is high when RST is high. RDEN should be low during reset.", $stime); + if (rst_in ==1 && wren_in ==1) + $display("Warning : At time %t, WREN on AFIFO36_INTERNAL instance %m is high when RST is high. WREN should be low during reset.", $stime); + end + + always @(posedge rdclk_in) begin + rst_rdckreg[0] <= rst_in; + rst_rdckreg[1] <= rst_rdckreg[0] & rst_in; + rst_rdckreg[2] <= rst_rdckreg[1] & rst_in; + end + + always @(posedge wrclk_in) begin + rst_wrckreg[0] <= rst_in ; + rst_wrckreg[1] <= rst_wrckreg[0] & rst_in; + rst_wrckreg[2] <= rst_wrckreg[1] & rst_in; + end + + always @(rst_in) + begin + rst_tmp1 = rst_in; + rst_rdclk_flag = 0; + rst_wrclk_flag = 0; + + if (rst_tmp1 == 0 && rst_tmp2 == 1) begin + if ((rst_rdckreg[2] & rst_rdckreg[1] & rst_rdckreg[0]) == 0) begin + $display("Error : At time %t, RST high on AFIFO36_INTERNAL instance %m is short than three RDCLK clock cycles. RST high need be more that three RDCLK clock cycles.", $stime); + rst_rdclk_flag = 1; + end + + if ((rst_wrckreg[2] & rst_wrckreg[1] & rst_wrckreg[0]) == 0) begin + $display("Error : At time %t, RST high on AFIFO36_INTERNAL instance %m is short than three WRCLK clock cycles. RST high need be more that three WRCLK clock cycles.", $stime); + rst_wrclk_flag = 1; + end + + if ((rst_rdclk_flag | rst_wrclk_flag) == 1) begin + assign do_out = 64'bx; + assign dop_out = 8'bx; + assign do_outreg = 64'bx; + assign dop_outreg = 8'bx; + assign full_out = 1'bX; + assign empty_out = 1'bX; + assign rderr_out = 1'bX; + assign wrerr_out = 1'bX; + assign sbiterr_out_out = 1'bx; + assign dbiterr_out_out = 1'bx; + assign eccparity_out = 8'bx; + assign rdcount_out = 13'bx; + assign rdcount_out_out = 13'bx; + assign wr_addr_out = 13'bx; + assign wr_addr = 13'bx; + assign wr1_addr = 0; + assign almostempty_int = 4'b1111; + assign almostempty_out = 1'bx; + assign almostfull_int = 4'b0000; + assign almostfull_out = 1'bx; + assign do_in = 64'b00000000000000000000000000000000; + assign dop_in = 8'b0000; + assign empty_ram = 4'b1111; + assign full_int = 4'b0000; + assign rd_addr = 0; + assign rd_prefetch = 0; + assign rdcount_flag = 0; + assign rd_flag = 0; + assign rdprefetch_flag = 0; + assign wr_flag = 0; + assign wr1_flag = 0; + assign awr_flag = 0; + + end + else if (gsr_in == 1'b0 && rst_in == 1'b0) begin + deassign do_out; + deassign dop_out; + deassign do_outreg; + deassign dop_outreg; + deassign full_out; + deassign empty_out; + deassign rderr_out; + deassign wrerr_out; + deassign sbiterr_out_out; + deassign dbiterr_out_out; + deassign eccparity_out; + deassign rdcount_out; + rdcount_out = 13'b0; + deassign wr_addr; + wr_addr = 13'b0; + deassign rdcount_out_out; + deassign wr_addr_out; + deassign wr1_addr; + deassign almostempty_int; + deassign almostempty_out; + deassign almostfull_int; + deassign almostfull_out; + deassign do_in; + deassign dop_in; + deassign empty_ram; + deassign full_int; + deassign rd_addr; + deassign rd_prefetch; + deassign rdcount_flag; + deassign rd_flag; + deassign rdprefetch_flag; + deassign wr_flag; + deassign wr1_flag; + deassign awr_flag; + end + end + rst_tmp2 = rst_tmp1; + + end + + + always @(posedge rdclk_in) begin + + if (rst_in == 1'b0) begin + if (fwft == 1 && $time > 100000 && aempty_flag < 2) begin + + if (aempty_flag == 0) + rise_rdclk = $time; + else + period_rdclk = $time - rise_rdclk; + + aempty_flag = aempty_flag + 1; + + end + + if (aempty_flag == 2 && afull_flag == 2) begin + if (ALMOST_EMPTY_OFFSET <= 4 * (period_rdclk / period_wrclk)) begin // in period + $display("DRC Error : The attribute ALMOST_EMPTY_OFFSET on AFIFO36_INTERNAL instance %m is set to %d. It must be set to a value greater than (4 * WRCLK frequency / RDCLK frequency) when AFIFO36_INTERNAL is configured in FIRST_WORD_FALL_THROUGH mode.", ALMOST_EMPTY_OFFSET); + $finish; + + end + end + end // if (rst_in == 1'b0) + + + if (sync == 1'b1) begin + + do_outreg = do_out; + dop_outreg = dop_out; + + if (rden_in == 1'b1) begin + + if (empty_out == 1'b0) begin + + do_buf = mem[rdcount_out]; + dop_buf = memp[rdcount_out]; + + // ECC decode + if (EN_ECC_READ == "TRUE") begin + + // regenerate parity + dopr_ecc[0] = do_buf[0]^do_buf[1]^do_buf[3]^do_buf[4]^do_buf[6]^do_buf[8] + ^do_buf[10]^do_buf[11]^do_buf[13]^do_buf[15]^do_buf[17]^do_buf[19] + ^do_buf[21]^do_buf[23]^do_buf[25]^do_buf[26]^do_buf[28] + ^do_buf[30]^do_buf[32]^do_buf[34]^do_buf[36]^do_buf[38] + ^do_buf[40]^do_buf[42]^do_buf[44]^do_buf[46]^do_buf[48] + ^do_buf[50]^do_buf[52]^do_buf[54]^do_buf[56]^do_buf[57]^do_buf[59] + ^do_buf[61]^do_buf[63]; + + dopr_ecc[1] = do_buf[0]^do_buf[2]^do_buf[3]^do_buf[5]^do_buf[6]^do_buf[9] + ^do_buf[10]^do_buf[12]^do_buf[13]^do_buf[16]^do_buf[17] + ^do_buf[20]^do_buf[21]^do_buf[24]^do_buf[25]^do_buf[27]^do_buf[28] + ^do_buf[31]^do_buf[32]^do_buf[35]^do_buf[36]^do_buf[39] + ^do_buf[40]^do_buf[43]^do_buf[44]^do_buf[47]^do_buf[48] + ^do_buf[51]^do_buf[52]^do_buf[55]^do_buf[56]^do_buf[58]^do_buf[59] + ^do_buf[62]^do_buf[63]; + + dopr_ecc[2] = do_buf[1]^do_buf[2]^do_buf[3]^do_buf[7]^do_buf[8]^do_buf[9] + ^do_buf[10]^do_buf[14]^do_buf[15]^do_buf[16]^do_buf[17] + ^do_buf[22]^do_buf[23]^do_buf[24]^do_buf[25]^do_buf[29] + ^do_buf[30]^do_buf[31]^do_buf[32]^do_buf[37]^do_buf[38]^do_buf[39] + ^do_buf[40]^do_buf[45]^do_buf[46]^do_buf[47]^do_buf[48] + ^do_buf[53]^do_buf[54]^do_buf[55]^do_buf[56] + ^do_buf[60]^do_buf[61]^do_buf[62]^do_buf[63]; + + dopr_ecc[3] = do_buf[4]^do_buf[5]^do_buf[6]^do_buf[7]^do_buf[8]^do_buf[9] + ^do_buf[10]^do_buf[18]^do_buf[19] + ^do_buf[20]^do_buf[21]^do_buf[22]^do_buf[23]^do_buf[24]^do_buf[25] + ^do_buf[33]^do_buf[34]^do_buf[35]^do_buf[36]^do_buf[37]^do_buf[38] + ^do_buf[39]^do_buf[40]^do_buf[49]^do_buf[50] + ^do_buf[51]^do_buf[52]^do_buf[53]^do_buf[54]^do_buf[55]^do_buf[56]; + + dopr_ecc[4] = do_buf[11]^do_buf[12]^do_buf[13]^do_buf[14]^do_buf[15]^do_buf[16] + ^do_buf[17]^do_buf[18]^do_buf[19]^do_buf[20]^do_buf[21]^do_buf[22] + ^do_buf[23]^do_buf[24]^do_buf[25]^do_buf[41]^do_buf[42]^do_buf[43] + ^do_buf[44]^do_buf[45]^do_buf[46]^do_buf[47]^do_buf[48]^do_buf[49] + ^do_buf[50]^do_buf[51]^do_buf[52]^do_buf[53]^do_buf[54]^do_buf[55]^do_buf[56]; + + + dopr_ecc[5] = do_buf[26]^do_buf[27]^do_buf[28]^do_buf[29] + ^do_buf[30]^do_buf[31]^do_buf[32]^do_buf[33]^do_buf[34]^do_buf[35] + ^do_buf[36]^do_buf[37]^do_buf[38]^do_buf[39]^do_buf[40] + ^do_buf[41]^do_buf[42]^do_buf[43]^do_buf[44]^do_buf[45] + ^do_buf[46]^do_buf[47]^do_buf[48]^do_buf[49]^do_buf[50] + ^do_buf[51]^do_buf[52]^do_buf[53]^do_buf[54]^do_buf[55]^do_buf[56]; + + dopr_ecc[6] = do_buf[57]^do_buf[58]^do_buf[59] + ^do_buf[60]^do_buf[61]^do_buf[62]^do_buf[63]; + + dopr_ecc[7] = dop_buf[0]^dop_buf[1]^dop_buf[2]^dop_buf[3]^dop_buf[4]^dop_buf[5] + ^dop_buf[6]^do_buf[0]^do_buf[1]^do_buf[2]^do_buf[3]^do_buf[4] + ^do_buf[5]^do_buf[6]^do_buf[7]^do_buf[8]^do_buf[9]^do_buf[10] + ^do_buf[11]^do_buf[12]^do_buf[13]^do_buf[14]^do_buf[15]^do_buf[16] + ^do_buf[17]^do_buf[18]^do_buf[19]^do_buf[20]^do_buf[21]^do_buf[22] + ^do_buf[23]^do_buf[24]^do_buf[25]^do_buf[26]^do_buf[27]^do_buf[28] + ^do_buf[29]^do_buf[30]^do_buf[31]^do_buf[32]^do_buf[33]^do_buf[34] + ^do_buf[35]^do_buf[36]^do_buf[37]^do_buf[38]^do_buf[39]^do_buf[40] + ^do_buf[41]^do_buf[42]^do_buf[43]^do_buf[44]^do_buf[45]^do_buf[46] + ^do_buf[47]^do_buf[48]^do_buf[49]^do_buf[50]^do_buf[51]^do_buf[52] + ^do_buf[53]^do_buf[54]^do_buf[55]^do_buf[56]^do_buf[57]^do_buf[58] + ^do_buf[59]^do_buf[60]^do_buf[61]^do_buf[62]^do_buf[63]; + + syndrome = dopr_ecc ^ dop_buf; + + if (syndrome !== 0) begin + + if (syndrome[7]) begin // dectect single bit error + + ecc_bit_position = {do_buf[63:57], dop_buf[6], do_buf[56:26], dop_buf[5], do_buf[25:11], dop_buf[4], do_buf[10:4], dop_buf[3], do_buf[3:1], dop_buf[2], do_buf[0], dop_buf[1:0], dop_buf[7]}; + + if (syndrome[6:0] > 71) begin + $display ("DRC Error : Simulation halted due Corrupted DIP. To correct this problem, make sure that reliable data is fed to the DIP. The correct Parity must be generated by a Hamming code encoder or encoder in the Block RAM. The output from the model is unreliable if there are more than 2 bit errors. The model doesn't warn if there is sporadic input of more than 2 bit errors due to the limitation in Hamming code."); + $finish; + end + + ecc_bit_position[syndrome[6:0]] = ~ecc_bit_position[syndrome[6:0]]; // correct single bit error in the output + + di_in_ecc_corrected = {ecc_bit_position[71:65], ecc_bit_position[63:33], ecc_bit_position[31:17], ecc_bit_position[15:9], ecc_bit_position[7:5], ecc_bit_position[3]}; // correct single bit error in the memory + + do_buf = di_in_ecc_corrected; + + dip_in_ecc_corrected = {ecc_bit_position[0], ecc_bit_position[64], ecc_bit_position[32], ecc_bit_position[16], ecc_bit_position[8], ecc_bit_position[4], ecc_bit_position[2:1]}; // correct single bit error in the parity memory + + dop_buf = dip_in_ecc_corrected; + + dbiterr_out_out = 0; // latch out in sync mode + sbiterr_out_out = 1; + + end + else if (!syndrome[7]) begin // double bit error + sbiterr_out_out = 0; + dbiterr_out_out = 1; + + end + end // if (syndrome !== 0) + else begin + dbiterr_out_out = 0; + sbiterr_out_out = 0; + + end // else: !if(syndrome !== 0) + + end // if (EN_ECC_READ == "TRUE") + // end ecc decode + + do_out = do_buf; + dop_out = dop_buf; + + rdcount_out = (rdcount_out + 1) % addr_limit; + + if (rdcount_out == 0) + rdcount_flag = ~rdcount_flag; + + end + end + + + rderr_out = (rden_in == 1'b1) && (empty_out == 1'b1); + + + if (wren_in == 1'b1) begin + empty_out = 1'b0; + end + else if (rdcount_out == wr_addr && rdcount_flag == wr_flag) + empty_out = 1'b1; + + if ((((rdcount_out + ae_empty) >= wr_addr) && (rdcount_flag == wr_flag)) || (((rdcount_out + ae_empty) >= (wr_addr + addr_limit) && (rdcount_flag != wr_flag)))) begin + almostempty_out = 1'b1; + end + + if ((((rdcount_out + addr_limit) > (wr_addr + ae_full)) && (rdcount_flag == wr_flag)) || ((rdcount_out > (wr_addr + ae_full)) && (rdcount_flag != wr_flag))) begin + if (wr_addr <= wr_addr + ae_full || rdcount_flag == wr_flag) + almostfull_out = 1'b0; + end + + end + else if (sync == 1'b0) begin + + dbiterr_out_out = dbiterr_out; // reg out in async mode + sbiterr_out_out = sbiterr_out; + + rden_reg = rden_in; + if (fwft == 1'b0) begin + if ((rden_reg == 1'b1) && (rd_addr != rdcount_out)) begin + do_out = do_in; + if (DATA_WIDTH != 4) + dop_out = dop_in; + rd_addr = (rd_addr + 1) % addr_limit; + if (rd_addr == 0) + rd_flag = ~rd_flag; + end + if (((rd_addr == rdcount_out) && (empty_ram[3] == 1'b0)) || + ((rden_reg == 1'b1) && (empty_ram[1] == 1'b0))) begin + + do_buf = mem[rdcount_out]; + dop_buf = memp[rdcount_out]; + + // ECC decode + if (EN_ECC_READ == "TRUE") begin + + // regenerate parity + dopr_ecc[0] = do_buf[0]^do_buf[1]^do_buf[3]^do_buf[4]^do_buf[6]^do_buf[8] + ^do_buf[10]^do_buf[11]^do_buf[13]^do_buf[15]^do_buf[17]^do_buf[19] + ^do_buf[21]^do_buf[23]^do_buf[25]^do_buf[26]^do_buf[28] + ^do_buf[30]^do_buf[32]^do_buf[34]^do_buf[36]^do_buf[38] + ^do_buf[40]^do_buf[42]^do_buf[44]^do_buf[46]^do_buf[48] + ^do_buf[50]^do_buf[52]^do_buf[54]^do_buf[56]^do_buf[57]^do_buf[59] + ^do_buf[61]^do_buf[63]; + + dopr_ecc[1] = do_buf[0]^do_buf[2]^do_buf[3]^do_buf[5]^do_buf[6]^do_buf[9] + ^do_buf[10]^do_buf[12]^do_buf[13]^do_buf[16]^do_buf[17] + ^do_buf[20]^do_buf[21]^do_buf[24]^do_buf[25]^do_buf[27]^do_buf[28] + ^do_buf[31]^do_buf[32]^do_buf[35]^do_buf[36]^do_buf[39] + ^do_buf[40]^do_buf[43]^do_buf[44]^do_buf[47]^do_buf[48] + ^do_buf[51]^do_buf[52]^do_buf[55]^do_buf[56]^do_buf[58]^do_buf[59] + ^do_buf[62]^do_buf[63]; + + dopr_ecc[2] = do_buf[1]^do_buf[2]^do_buf[3]^do_buf[7]^do_buf[8]^do_buf[9] + ^do_buf[10]^do_buf[14]^do_buf[15]^do_buf[16]^do_buf[17] + ^do_buf[22]^do_buf[23]^do_buf[24]^do_buf[25]^do_buf[29] + ^do_buf[30]^do_buf[31]^do_buf[32]^do_buf[37]^do_buf[38]^do_buf[39] + ^do_buf[40]^do_buf[45]^do_buf[46]^do_buf[47]^do_buf[48] + ^do_buf[53]^do_buf[54]^do_buf[55]^do_buf[56] + ^do_buf[60]^do_buf[61]^do_buf[62]^do_buf[63]; + + dopr_ecc[3] = do_buf[4]^do_buf[5]^do_buf[6]^do_buf[7]^do_buf[8]^do_buf[9] + ^do_buf[10]^do_buf[18]^do_buf[19] + ^do_buf[20]^do_buf[21]^do_buf[22]^do_buf[23]^do_buf[24]^do_buf[25] + ^do_buf[33]^do_buf[34]^do_buf[35]^do_buf[36]^do_buf[37]^do_buf[38] + ^do_buf[39]^do_buf[40]^do_buf[49]^do_buf[50] + ^do_buf[51]^do_buf[52]^do_buf[53]^do_buf[54]^do_buf[55]^do_buf[56]; + + dopr_ecc[4] = do_buf[11]^do_buf[12]^do_buf[13]^do_buf[14]^do_buf[15]^do_buf[16] + ^do_buf[17]^do_buf[18]^do_buf[19]^do_buf[20]^do_buf[21]^do_buf[22] + ^do_buf[23]^do_buf[24]^do_buf[25]^do_buf[41]^do_buf[42]^do_buf[43] + ^do_buf[44]^do_buf[45]^do_buf[46]^do_buf[47]^do_buf[48]^do_buf[49] + ^do_buf[50]^do_buf[51]^do_buf[52]^do_buf[53]^do_buf[54]^do_buf[55]^do_buf[56]; + + + dopr_ecc[5] = do_buf[26]^do_buf[27]^do_buf[28]^do_buf[29] + ^do_buf[30]^do_buf[31]^do_buf[32]^do_buf[33]^do_buf[34]^do_buf[35] + ^do_buf[36]^do_buf[37]^do_buf[38]^do_buf[39]^do_buf[40] + ^do_buf[41]^do_buf[42]^do_buf[43]^do_buf[44]^do_buf[45] + ^do_buf[46]^do_buf[47]^do_buf[48]^do_buf[49]^do_buf[50] + ^do_buf[51]^do_buf[52]^do_buf[53]^do_buf[54]^do_buf[55]^do_buf[56]; + + dopr_ecc[6] = do_buf[57]^do_buf[58]^do_buf[59] + ^do_buf[60]^do_buf[61]^do_buf[62]^do_buf[63]; + + dopr_ecc[7] = dop_buf[0]^dop_buf[1]^dop_buf[2]^dop_buf[3]^dop_buf[4]^dop_buf[5] + ^dop_buf[6]^do_buf[0]^do_buf[1]^do_buf[2]^do_buf[3]^do_buf[4] + ^do_buf[5]^do_buf[6]^do_buf[7]^do_buf[8]^do_buf[9]^do_buf[10] + ^do_buf[11]^do_buf[12]^do_buf[13]^do_buf[14]^do_buf[15]^do_buf[16] + ^do_buf[17]^do_buf[18]^do_buf[19]^do_buf[20]^do_buf[21]^do_buf[22] + ^do_buf[23]^do_buf[24]^do_buf[25]^do_buf[26]^do_buf[27]^do_buf[28] + ^do_buf[29]^do_buf[30]^do_buf[31]^do_buf[32]^do_buf[33]^do_buf[34] + ^do_buf[35]^do_buf[36]^do_buf[37]^do_buf[38]^do_buf[39]^do_buf[40] + ^do_buf[41]^do_buf[42]^do_buf[43]^do_buf[44]^do_buf[45]^do_buf[46] + ^do_buf[47]^do_buf[48]^do_buf[49]^do_buf[50]^do_buf[51]^do_buf[52] + ^do_buf[53]^do_buf[54]^do_buf[55]^do_buf[56]^do_buf[57]^do_buf[58] + ^do_buf[59]^do_buf[60]^do_buf[61]^do_buf[62]^do_buf[63]; + + syndrome = dopr_ecc ^ dop_buf; + + if (syndrome !== 0) begin + + if (syndrome[7]) begin // dectect single bit error + + ecc_bit_position = {do_buf[63:57], dop_buf[6], do_buf[56:26], dop_buf[5], do_buf[25:11], dop_buf[4], do_buf[10:4], dop_buf[3], do_buf[3:1], dop_buf[2], do_buf[0], dop_buf[1:0], dop_buf[7]}; + + if (syndrome[6:0] > 71) begin + $display ("DRC Error : Simulation halted due Corrupted DIP. To correct this problem, make sure that reliable data is fed to the DIP. The correct Parity must be generated by a Hamming code encoder or encoder in the Block RAM. The output from the model is unreliable if there are more than 2 bit errors. The model doesn't warn if there is sporadic input of more than 2 bit errors due to the limitation in Hamming code."); + $finish; + end + + ecc_bit_position[syndrome[6:0]] = ~ecc_bit_position[syndrome[6:0]]; // correct single bit error in the output + + di_in_ecc_corrected = {ecc_bit_position[71:65], ecc_bit_position[63:33], ecc_bit_position[31:17], ecc_bit_position[15:9], ecc_bit_position[7:5], ecc_bit_position[3]}; // correct single bit error in the memory + + do_buf = di_in_ecc_corrected; + + dip_in_ecc_corrected = {ecc_bit_position[0], ecc_bit_position[64], ecc_bit_position[32], ecc_bit_position[16], ecc_bit_position[8], ecc_bit_position[4], ecc_bit_position[2:1]}; // correct single bit error in the parity memory + + dop_buf = dip_in_ecc_corrected; + + dbiterr_out = 0; + sbiterr_out = 1; + + end + else if (!syndrome[7]) begin // double bit error + sbiterr_out = 0; + dbiterr_out = 1; + + end + end // if (syndrome !== 0) + else begin + dbiterr_out = 0; + sbiterr_out = 0; + + end // else: !if(syndrome !== 0) + + end // if (EN_ECC_READ == "TRUE") + // end ecc decode + + do_in = do_buf; + dop_in = dop_buf; + + #1; + rdcount_out = (rdcount_out + 1) % addr_limit; + if (rdcount_out == 0) begin + rdcount_flag = ~rdcount_flag; + end + end + end + + if (fwft == 1'b1) begin + + if ((rden_reg == 1'b1) && (rd_addr != rd_prefetch)) begin + rd_prefetch = (rd_prefetch + 1) % addr_limit; + if (rd_prefetch == 0) + rdprefetch_flag = ~rdprefetch_flag; + end + if ((rd_prefetch == rd_addr) && (rd_addr != rdcount_out)) begin + do_out = do_in; + if (DATA_WIDTH != 4) + dop_out = dop_in; + rd_addr = (rd_addr + 1) % addr_limit; + if (rd_addr == 0) + rd_flag = ~rd_flag; + end + if (((rd_addr == rdcount_out) && (empty_ram[3] == 1'b0)) || + ((rden_reg == 1'b1) && (empty_ram[1] == 1'b0)) || + ((rden_reg == 1'b0) && (empty_ram[1] == 1'b0) && (rd_addr == rdcount_out))) begin + + do_buf = mem[rdcount_out]; + dop_buf = memp[rdcount_out]; + + // ECC decode + if (EN_ECC_READ == "TRUE") begin + + // regenerate parity + dopr_ecc[0] = do_buf[0]^do_buf[1]^do_buf[3]^do_buf[4]^do_buf[6]^do_buf[8] + ^do_buf[10]^do_buf[11]^do_buf[13]^do_buf[15]^do_buf[17]^do_buf[19] + ^do_buf[21]^do_buf[23]^do_buf[25]^do_buf[26]^do_buf[28] + ^do_buf[30]^do_buf[32]^do_buf[34]^do_buf[36]^do_buf[38] + ^do_buf[40]^do_buf[42]^do_buf[44]^do_buf[46]^do_buf[48] + ^do_buf[50]^do_buf[52]^do_buf[54]^do_buf[56]^do_buf[57]^do_buf[59] + ^do_buf[61]^do_buf[63]; + + dopr_ecc[1] = do_buf[0]^do_buf[2]^do_buf[3]^do_buf[5]^do_buf[6]^do_buf[9] + ^do_buf[10]^do_buf[12]^do_buf[13]^do_buf[16]^do_buf[17] + ^do_buf[20]^do_buf[21]^do_buf[24]^do_buf[25]^do_buf[27]^do_buf[28] + ^do_buf[31]^do_buf[32]^do_buf[35]^do_buf[36]^do_buf[39] + ^do_buf[40]^do_buf[43]^do_buf[44]^do_buf[47]^do_buf[48] + ^do_buf[51]^do_buf[52]^do_buf[55]^do_buf[56]^do_buf[58]^do_buf[59] + ^do_buf[62]^do_buf[63]; + + dopr_ecc[2] = do_buf[1]^do_buf[2]^do_buf[3]^do_buf[7]^do_buf[8]^do_buf[9] + ^do_buf[10]^do_buf[14]^do_buf[15]^do_buf[16]^do_buf[17] + ^do_buf[22]^do_buf[23]^do_buf[24]^do_buf[25]^do_buf[29] + ^do_buf[30]^do_buf[31]^do_buf[32]^do_buf[37]^do_buf[38]^do_buf[39] + ^do_buf[40]^do_buf[45]^do_buf[46]^do_buf[47]^do_buf[48] + ^do_buf[53]^do_buf[54]^do_buf[55]^do_buf[56] + ^do_buf[60]^do_buf[61]^do_buf[62]^do_buf[63]; + + dopr_ecc[3] = do_buf[4]^do_buf[5]^do_buf[6]^do_buf[7]^do_buf[8]^do_buf[9] + ^do_buf[10]^do_buf[18]^do_buf[19] + ^do_buf[20]^do_buf[21]^do_buf[22]^do_buf[23]^do_buf[24]^do_buf[25] + ^do_buf[33]^do_buf[34]^do_buf[35]^do_buf[36]^do_buf[37]^do_buf[38] + ^do_buf[39]^do_buf[40]^do_buf[49]^do_buf[50] + ^do_buf[51]^do_buf[52]^do_buf[53]^do_buf[54]^do_buf[55]^do_buf[56]; + + dopr_ecc[4] = do_buf[11]^do_buf[12]^do_buf[13]^do_buf[14]^do_buf[15]^do_buf[16] + ^do_buf[17]^do_buf[18]^do_buf[19]^do_buf[20]^do_buf[21]^do_buf[22] + ^do_buf[23]^do_buf[24]^do_buf[25]^do_buf[41]^do_buf[42]^do_buf[43] + ^do_buf[44]^do_buf[45]^do_buf[46]^do_buf[47]^do_buf[48]^do_buf[49] + ^do_buf[50]^do_buf[51]^do_buf[52]^do_buf[53]^do_buf[54]^do_buf[55]^do_buf[56]; + + + dopr_ecc[5] = do_buf[26]^do_buf[27]^do_buf[28]^do_buf[29] + ^do_buf[30]^do_buf[31]^do_buf[32]^do_buf[33]^do_buf[34]^do_buf[35] + ^do_buf[36]^do_buf[37]^do_buf[38]^do_buf[39]^do_buf[40] + ^do_buf[41]^do_buf[42]^do_buf[43]^do_buf[44]^do_buf[45] + ^do_buf[46]^do_buf[47]^do_buf[48]^do_buf[49]^do_buf[50] + ^do_buf[51]^do_buf[52]^do_buf[53]^do_buf[54]^do_buf[55]^do_buf[56]; + + dopr_ecc[6] = do_buf[57]^do_buf[58]^do_buf[59] + ^do_buf[60]^do_buf[61]^do_buf[62]^do_buf[63]; + + dopr_ecc[7] = dop_buf[0]^dop_buf[1]^dop_buf[2]^dop_buf[3]^dop_buf[4]^dop_buf[5] + ^dop_buf[6]^do_buf[0]^do_buf[1]^do_buf[2]^do_buf[3]^do_buf[4] + ^do_buf[5]^do_buf[6]^do_buf[7]^do_buf[8]^do_buf[9]^do_buf[10] + ^do_buf[11]^do_buf[12]^do_buf[13]^do_buf[14]^do_buf[15]^do_buf[16] + ^do_buf[17]^do_buf[18]^do_buf[19]^do_buf[20]^do_buf[21]^do_buf[22] + ^do_buf[23]^do_buf[24]^do_buf[25]^do_buf[26]^do_buf[27]^do_buf[28] + ^do_buf[29]^do_buf[30]^do_buf[31]^do_buf[32]^do_buf[33]^do_buf[34] + ^do_buf[35]^do_buf[36]^do_buf[37]^do_buf[38]^do_buf[39]^do_buf[40] + ^do_buf[41]^do_buf[42]^do_buf[43]^do_buf[44]^do_buf[45]^do_buf[46] + ^do_buf[47]^do_buf[48]^do_buf[49]^do_buf[50]^do_buf[51]^do_buf[52] + ^do_buf[53]^do_buf[54]^do_buf[55]^do_buf[56]^do_buf[57]^do_buf[58] + ^do_buf[59]^do_buf[60]^do_buf[61]^do_buf[62]^do_buf[63]; + + syndrome = dopr_ecc ^ dop_buf; + + if (syndrome !== 0) begin + + if (syndrome[7]) begin // dectect single bit error + + ecc_bit_position = {do_buf[63:57], dop_buf[6], do_buf[56:26], dop_buf[5], do_buf[25:11], dop_buf[4], do_buf[10:4], dop_buf[3], do_buf[3:1], dop_buf[2], do_buf[0], dop_buf[1:0], dop_buf[7]}; + + if (syndrome[6:0] > 71) begin + $display ("DRC Error : Simulation halted due Corrupted DIP. To correct this problem, make sure that reliable data is fed to the DIP. The correct Parity must be generated by a Hamming code encoder or encoder in the Block RAM. The output from the model is unreliable if there are more than 2 bit errors. The model doesn't warn if there is sporadic input of more than 2 bit errors due to the limitation in Hamming code."); + $finish; + end + + ecc_bit_position[syndrome[6:0]] = ~ecc_bit_position[syndrome[6:0]]; // correct single bit error in the output + + di_in_ecc_corrected = {ecc_bit_position[71:65], ecc_bit_position[63:33], ecc_bit_position[31:17], ecc_bit_position[15:9], ecc_bit_position[7:5], ecc_bit_position[3]}; // correct single bit error in the memory + + do_buf = di_in_ecc_corrected; + + dip_in_ecc_corrected = {ecc_bit_position[0], ecc_bit_position[64], ecc_bit_position[32], ecc_bit_position[16], ecc_bit_position[8], ecc_bit_position[4], ecc_bit_position[2:1]}; // correct single bit error in the parity memory + + dop_buf = dip_in_ecc_corrected; + + dbiterr_out = 0; + sbiterr_out = 1; + + end + else if (!syndrome[7]) begin // double bit error + sbiterr_out = 0; + dbiterr_out = 1; + + end + end // if (syndrome !== 0) + else begin + dbiterr_out = 0; + sbiterr_out = 0; + + end // else: !if(syndrome !== 0) + + end // if (EN_ECC_READ == "TRUE") + // end ecc decode + + do_in = do_buf; + dop_in = dop_buf; + + #1; + rdcount_out = (rdcount_out + 1) % addr_limit; + if (rdcount_out == 0) + rdcount_flag = ~rdcount_flag; + end + end // if (fwft == 1'b1) + + + rderr_out = (rden_reg == 1'b1) && (empty_out == 1'b1); + + almostempty_out = almostempty_int[3]; + + if ((((rdcount_out + ae_empty) >= wr_addr) && (rdcount_flag == awr_flag)) || (((rdcount_out + ae_empty) >= (wr_addr + addr_limit)) && (rdcount_flag != awr_flag))) begin + almostempty_int[3] = 1'b1; + almostempty_int[2] = 1'b1; + almostempty_int[1] = 1'b1; + almostempty_int[0] = 1'b1; + end + else if (almostempty_int[2] == 1'b0) begin + + if (rdcount_out <= rdcount_out + ae_empty || rdcount_flag != awr_flag) begin + almostempty_int[3] = almostempty_int[0]; + almostempty_int[0] = 1'b0; + end + end + + if ((((rdcount_out + addr_limit) > (wr_addr + ae_full)) && (rdcount_flag == awr_flag)) || ((rdcount_out > (wr_addr + ae_full)) && (rdcount_flag != awr_flag))) begin + + if (((rden_reg == 1'b1) && (empty_out == 1'b0)) || ((((rd_addr + 1) % addr_limit) == rdcount_out) && (almostfull_int[1] == 1'b1))) begin + almostfull_int[2] = almostfull_int[1]; + almostfull_int[1] = 1'b0; + end + end + else begin + almostfull_int[2] = 1'b1; + almostfull_int[1] = 1'b1; + end + + if (fwft == 1'b0) begin + if ((rdcount_out == rd_addr) && (rdcount_flag == rd_flag)) begin + empty_out = 1'b1; + end + else begin + empty_out = 1'b0; + end + end // if (fwft == 1'b0) + else if (fwft == 1'b1) begin + if ((rd_prefetch == rd_addr) && (rdprefetch_flag == rd_flag)) begin + empty_out = 1'b1; + end + else begin + empty_out = 1'b0; + end + end + + if ((rdcount_out == wr_addr) && (rdcount_flag == awr_flag)) begin + empty_ram[2] = 1'b1; + empty_ram[1] = 1'b1; + empty_ram[0] = 1'b1; + end + else begin + empty_ram[2] = empty_ram[1]; + empty_ram[1] = empty_ram[0]; + empty_ram[0] = 1'b0; + end + + if ((rdcount_out == wr1_addr) && (rdcount_flag == wr1_flag)) begin + empty_ram[3] = 1'b1; + end + else begin + empty_ram[3] = 1'b0; + end + + wr1_addr = wr_addr; + wr1_flag = awr_flag; + + end // if (sync == 1'b0) + end // always @ (posedge rdclk_in) + + + always @(posedge wrclk_in) begin + + if (rst_in == 1'b0) begin + if (fwft == 1 && $time > 100000 && afull_flag < 2) begin + + if (afull_flag == 0) + rise_wrclk = $time; + else + period_wrclk = $time - rise_wrclk; + + afull_flag = afull_flag + 1; + + end + end // if (rst_in == 1'b0) + + + if (sync == 1'b1) begin + + if (wren_in == 1'b1) begin + + if (full_out == 1'b0) begin + + // ECC encode + if (EN_ECC_WRITE == "TRUE") begin + + dip_ecc[0] = di_in[0]^di_in[1]^di_in[3]^di_in[4]^di_in[6]^di_in[8] + ^di_in[10]^di_in[11]^di_in[13]^di_in[15]^di_in[17]^di_in[19] + ^di_in[21]^di_in[23]^di_in[25]^di_in[26]^di_in[28] + ^di_in[30]^di_in[32]^di_in[34]^di_in[36]^di_in[38] + ^di_in[40]^di_in[42]^di_in[44]^di_in[46]^di_in[48] + ^di_in[50]^di_in[52]^di_in[54]^di_in[56]^di_in[57]^di_in[59] + ^di_in[61]^di_in[63]; + + dip_ecc[1] = di_in[0]^di_in[2]^di_in[3]^di_in[5]^di_in[6]^di_in[9] + ^di_in[10]^di_in[12]^di_in[13]^di_in[16]^di_in[17] + ^di_in[20]^di_in[21]^di_in[24]^di_in[25]^di_in[27]^di_in[28] + ^di_in[31]^di_in[32]^di_in[35]^di_in[36]^di_in[39] + ^di_in[40]^di_in[43]^di_in[44]^di_in[47]^di_in[48] + ^di_in[51]^di_in[52]^di_in[55]^di_in[56]^di_in[58]^di_in[59] + ^di_in[62]^di_in[63]; + + dip_ecc[2] = di_in[1]^di_in[2]^di_in[3]^di_in[7]^di_in[8]^di_in[9] + ^di_in[10]^di_in[14]^di_in[15]^di_in[16]^di_in[17] + ^di_in[22]^di_in[23]^di_in[24]^di_in[25]^di_in[29] + ^di_in[30]^di_in[31]^di_in[32]^di_in[37]^di_in[38]^di_in[39] + ^di_in[40]^di_in[45]^di_in[46]^di_in[47]^di_in[48] + ^di_in[53]^di_in[54]^di_in[55]^di_in[56] + ^di_in[60]^di_in[61]^di_in[62]^di_in[63]; + + dip_ecc[3] = di_in[4]^di_in[5]^di_in[6]^di_in[7]^di_in[8]^di_in[9] + ^di_in[10]^di_in[18]^di_in[19] + ^di_in[20]^di_in[21]^di_in[22]^di_in[23]^di_in[24]^di_in[25] + ^di_in[33]^di_in[34]^di_in[35]^di_in[36]^di_in[37]^di_in[38]^di_in[39] + ^di_in[40]^di_in[49] + ^di_in[50]^di_in[51]^di_in[52]^di_in[53]^di_in[54]^di_in[55]^di_in[56]; + + dip_ecc[4] = di_in[11]^di_in[12]^di_in[13]^di_in[14]^di_in[15]^di_in[16]^di_in[17]^di_in[18]^di_in[19] + ^di_in[20]^di_in[21]^di_in[22]^di_in[23]^di_in[24]^di_in[25] + ^di_in[41]^di_in[42]^di_in[43]^di_in[44]^di_in[45]^di_in[46]^di_in[47]^di_in[48]^di_in[49] + ^di_in[50]^di_in[51]^di_in[52]^di_in[53]^di_in[54]^di_in[55]^di_in[56]; + + + dip_ecc[5] = di_in[26]^di_in[27]^di_in[28]^di_in[29] + ^di_in[30]^di_in[31]^di_in[32]^di_in[33]^di_in[34]^di_in[35]^di_in[36]^di_in[37]^di_in[38]^di_in[39] + ^di_in[40]^di_in[41]^di_in[42]^di_in[43]^di_in[44]^di_in[45]^di_in[46]^di_in[47]^di_in[48]^di_in[49] + ^di_in[50]^di_in[51]^di_in[52]^di_in[53]^di_in[54]^di_in[55]^di_in[56]; + + dip_ecc[6] = di_in[57]^di_in[58]^di_in[59] + ^di_in[60]^di_in[61]^di_in[62]^di_in[63]; + + dip_ecc[7] = dip_ecc[0]^dip_ecc[1]^dip_ecc[2]^dip_ecc[3]^dip_ecc[4]^dip_ecc[5]^dip_ecc[6] + ^di_in[0]^di_in[1]^di_in[2]^di_in[3]^di_in[4]^di_in[5]^di_in[6]^di_in[7]^di_in[8]^di_in[9] + ^di_in[10]^di_in[11]^di_in[12]^di_in[13]^di_in[14]^di_in[15]^di_in[16]^di_in[17]^di_in[18]^di_in[19] + ^di_in[20]^di_in[21]^di_in[22]^di_in[23]^di_in[24]^di_in[25]^di_in[26]^di_in[27]^di_in[28]^di_in[29] + ^di_in[30]^di_in[31]^di_in[32]^di_in[33]^di_in[34]^di_in[35]^di_in[36]^di_in[37]^di_in[38]^di_in[39] + ^di_in[40]^di_in[41]^di_in[42]^di_in[43]^di_in[44]^di_in[45]^di_in[46]^di_in[47]^di_in[48]^di_in[49] + ^di_in[50]^di_in[51]^di_in[52]^di_in[53]^di_in[54]^di_in[55]^di_in[56]^di_in[57]^di_in[58]^di_in[59] + ^di_in[60]^di_in[61]^di_in[62]^di_in[63]; + + eccparity_out = dip_ecc; + + dip_int = dip_ecc; // only 64 bits width + + end // if (EN_ECC_WRITE == "TRUE") + else begin + + dip_int = dip_in; // only 64 bits width + + end // else: !if(EN_ECC_WRITE == "TRUE") + // end ecc encode + + mem[wr_addr] = di_in; + memp[wr_addr] = dip_int; + + wr_addr = (wr_addr + 1) % addr_limit; + if (wr_addr == 0) + wr_flag = ~wr_flag; + + end + end + + + wrerr_out = (wren_in == 1'b1) && (full_out == 1'b1); + + + if (rden_in == 1'b1) begin + full_out = 1'b0; + end + else if (rdcount_out == wr_addr && rdcount_flag != wr_flag) + full_out = 1'b1; + + if ((((rdcount_out + ae_empty) < wr_addr) && (rdcount_flag == wr_flag)) || (((rdcount_out + ae_empty) < (wr_addr + addr_limit) && (rdcount_flag != wr_flag)))) begin + + if (rdcount_out <= rdcount_out + ae_empty || rdcount_flag != wr_flag) + almostempty_out = 1'b0; + + end + + if ((((rdcount_out + addr_limit) <= (wr_addr + ae_full)) && (rdcount_flag == wr_flag)) || ((rdcount_out <= (wr_addr + ae_full)) && (rdcount_flag != wr_flag))) begin + almostfull_out = 1'b1; + end + + end + else if (sync == 1'b0) begin + + wren_reg = wren_in; + + if (wren_reg == 1'b1 && (full_out == 1'b0)) begin + + // ECC encode + if (EN_ECC_WRITE == "TRUE") begin + + dip_ecc[0] = di_in[0]^di_in[1]^di_in[3]^di_in[4]^di_in[6]^di_in[8] + ^di_in[10]^di_in[11]^di_in[13]^di_in[15]^di_in[17]^di_in[19] + ^di_in[21]^di_in[23]^di_in[25]^di_in[26]^di_in[28] + ^di_in[30]^di_in[32]^di_in[34]^di_in[36]^di_in[38] + ^di_in[40]^di_in[42]^di_in[44]^di_in[46]^di_in[48] + ^di_in[50]^di_in[52]^di_in[54]^di_in[56]^di_in[57]^di_in[59] + ^di_in[61]^di_in[63]; + + dip_ecc[1] = di_in[0]^di_in[2]^di_in[3]^di_in[5]^di_in[6]^di_in[9] + ^di_in[10]^di_in[12]^di_in[13]^di_in[16]^di_in[17] + ^di_in[20]^di_in[21]^di_in[24]^di_in[25]^di_in[27]^di_in[28] + ^di_in[31]^di_in[32]^di_in[35]^di_in[36]^di_in[39] + ^di_in[40]^di_in[43]^di_in[44]^di_in[47]^di_in[48] + ^di_in[51]^di_in[52]^di_in[55]^di_in[56]^di_in[58]^di_in[59] + ^di_in[62]^di_in[63]; + + dip_ecc[2] = di_in[1]^di_in[2]^di_in[3]^di_in[7]^di_in[8]^di_in[9] + ^di_in[10]^di_in[14]^di_in[15]^di_in[16]^di_in[17] + ^di_in[22]^di_in[23]^di_in[24]^di_in[25]^di_in[29] + ^di_in[30]^di_in[31]^di_in[32]^di_in[37]^di_in[38]^di_in[39] + ^di_in[40]^di_in[45]^di_in[46]^di_in[47]^di_in[48] + ^di_in[53]^di_in[54]^di_in[55]^di_in[56] + ^di_in[60]^di_in[61]^di_in[62]^di_in[63]; + + dip_ecc[3] = di_in[4]^di_in[5]^di_in[6]^di_in[7]^di_in[8]^di_in[9] + ^di_in[10]^di_in[18]^di_in[19] + ^di_in[20]^di_in[21]^di_in[22]^di_in[23]^di_in[24]^di_in[25] + ^di_in[33]^di_in[34]^di_in[35]^di_in[36]^di_in[37]^di_in[38]^di_in[39] + ^di_in[40]^di_in[49] + ^di_in[50]^di_in[51]^di_in[52]^di_in[53]^di_in[54]^di_in[55]^di_in[56]; + + dip_ecc[4] = di_in[11]^di_in[12]^di_in[13]^di_in[14]^di_in[15]^di_in[16]^di_in[17]^di_in[18]^di_in[19] + ^di_in[20]^di_in[21]^di_in[22]^di_in[23]^di_in[24]^di_in[25] + ^di_in[41]^di_in[42]^di_in[43]^di_in[44]^di_in[45]^di_in[46]^di_in[47]^di_in[48]^di_in[49] + ^di_in[50]^di_in[51]^di_in[52]^di_in[53]^di_in[54]^di_in[55]^di_in[56]; + + + dip_ecc[5] = di_in[26]^di_in[27]^di_in[28]^di_in[29] + ^di_in[30]^di_in[31]^di_in[32]^di_in[33]^di_in[34]^di_in[35]^di_in[36]^di_in[37]^di_in[38]^di_in[39] + ^di_in[40]^di_in[41]^di_in[42]^di_in[43]^di_in[44]^di_in[45]^di_in[46]^di_in[47]^di_in[48]^di_in[49] + ^di_in[50]^di_in[51]^di_in[52]^di_in[53]^di_in[54]^di_in[55]^di_in[56]; + + dip_ecc[6] = di_in[57]^di_in[58]^di_in[59] + ^di_in[60]^di_in[61]^di_in[62]^di_in[63]; + + dip_ecc[7] = dip_ecc[0]^dip_ecc[1]^dip_ecc[2]^dip_ecc[3]^dip_ecc[4]^dip_ecc[5]^dip_ecc[6] + ^di_in[0]^di_in[1]^di_in[2]^di_in[3]^di_in[4]^di_in[5]^di_in[6]^di_in[7]^di_in[8]^di_in[9] + ^di_in[10]^di_in[11]^di_in[12]^di_in[13]^di_in[14]^di_in[15]^di_in[16]^di_in[17]^di_in[18]^di_in[19] + ^di_in[20]^di_in[21]^di_in[22]^di_in[23]^di_in[24]^di_in[25]^di_in[26]^di_in[27]^di_in[28]^di_in[29] + ^di_in[30]^di_in[31]^di_in[32]^di_in[33]^di_in[34]^di_in[35]^di_in[36]^di_in[37]^di_in[38]^di_in[39] + ^di_in[40]^di_in[41]^di_in[42]^di_in[43]^di_in[44]^di_in[45]^di_in[46]^di_in[47]^di_in[48]^di_in[49] + ^di_in[50]^di_in[51]^di_in[52]^di_in[53]^di_in[54]^di_in[55]^di_in[56]^di_in[57]^di_in[58]^di_in[59] + ^di_in[60]^di_in[61]^di_in[62]^di_in[63]; + + eccparity_out = dip_ecc; + + dip_int = dip_ecc; // only 64 bits width + + end // if (EN_ECC_WRITE == "TRUE") + else begin + + dip_int = dip_in; // only 64 bits width + + end // else: !if(EN_ECC_WRITE == "TRUE") + // end ecc encode + + mem[wr_addr] = di_in; + memp[wr_addr] = dip_int; + + #1; + wr_addr = (wr_addr + 1) % addr_limit; + + if (wr_addr == 0) + awr_flag = ~awr_flag; + + if (wr_addr == addr_limit - 1) + wr_flag = ~wr_flag; + end + + wrerr_out = (wren_reg == 1'b1) && (full_out == 1'b1); + + almostfull_out = almostfull_int[3]; + + if ((((rdcount_out + addr_limit) <= (wr_addr + ae_full)) && (rdcount_flag == awr_flag)) || ((rdcount_out <= (wr_addr + ae_full)) && (rdcount_flag != awr_flag))) begin + almostfull_int[3] = 1'b1; + almostfull_int[2] = 1'b1; + almostfull_int[1] = 1'b1; + almostfull_int[0] = 1'b1; + end + else if (almostfull_int[2] == 1'b0) begin + + if (wr_addr <= wr_addr + ae_full || rdcount_flag == awr_flag) begin + almostfull_int[3] = almostfull_int[0]; + almostfull_int[0] = 1'b0; + end + end + + if ((((rdcount_out + ae_empty) < wr_addr) && (rdcount_flag == awr_flag)) || (((rdcount_out + ae_empty) < (wr_addr + addr_limit)) && (rdcount_flag != awr_flag))) begin + if (wren_reg == 1'b1) begin + almostempty_int[2] = almostempty_int[1]; + almostempty_int[1] = 1'b0; + end + end + else begin + almostempty_int[2] = 1'b1; + almostempty_int[1] = 1'b1; + end + + if (wren_reg == 1'b1 || full_out == 1'b1) + full_out = full_int[1]; + + if (((rdcount_out == wr_addr) || (rdcount_out - 1 == wr_addr || (rdcount_out + addr_limit - 1 == wr_addr))) && almostfull_out) begin + full_int[1] = 1'b1; + full_int[0] = 1'b1; + end + else begin + full_int[1] = full_int[0]; + full_int[0] = 0; + end + + end // if (sync == 1'b0) + end // always @ (posedge wrclk_in) + + + always @(do_out or dop_out or do_outreg or dop_outreg) begin + + if (sync == 1) + + case (DO_REG) + + 0 : begin + do_out_mux = do_out; + dop_out_mux = dop_out; + end + 1 : begin + do_out_mux = do_outreg; + dop_out_mux = dop_outreg; + end + default : begin + $display("Attribute Syntax Error : The attribute DO_REG on AFIFO36_INTERNAL instance %m is set to %2d. Legal values for this attribute are 0 or 1.", DO_REG); + $finish; + end + endcase + + else begin + do_out_mux = do_out; + dop_out_mux = dop_out; + end // else: !if(sync == 1) + + end // always @ (do_out or dop_out or do_outreg or dop_outreg) + + + // matching HW behavior to X the unused output bits + assign do_out_out = (DATA_WIDTH == 4) ? {60'bx, do_out_mux[3:0]} + : (DATA_WIDTH == 9) ? {56'bx, do_out_mux[7:0]} + : (DATA_WIDTH == 18) ? {48'bx, do_out_mux[15:0]} + : (DATA_WIDTH == 36) ? {32'bx, do_out_mux[31:0]} + : (DATA_WIDTH == 72) ? do_out_mux + : do_out_mux; + + // matching HW behavior to X the unused output bits + assign dop_out_out = (DATA_WIDTH == 9) ? {7'bx, dop_out_mux[0:0]} + : (DATA_WIDTH == 18) ? {6'bx, dop_out_mux[1:0]} + : (DATA_WIDTH == 36) ? {4'bx, dop_out_mux[3:0]} + : (DATA_WIDTH == 72) ? dop_out_mux + : 8'bx; + + // matching HW behavior to pull up the unused output bits + always @(wr_addr) begin + + if (FIFO_SIZE == 18) + case (DATA_WIDTH) + 4 : wr_addr_out = {1'b1, wr_addr[11:0]}; + 9 : wr_addr_out = {2'b11, wr_addr[10:0]}; + 18 : wr_addr_out = {3'b111, wr_addr[9:0]}; + 36 : wr_addr_out = {4'hf, wr_addr[8:0]}; + default : wr_addr_out = wr_addr; + endcase // case(DATA_WIDTH) + else + case (DATA_WIDTH) + 4 : wr_addr_out = wr_addr; + 9 : wr_addr_out = {1'b1, wr_addr[11:0]}; + 18 : wr_addr_out = {2'b11, wr_addr[10:0]}; + 36 : wr_addr_out = {3'b111, wr_addr[9:0]}; + 72 : wr_addr_out = {4'hf, wr_addr[8:0]}; + default : wr_addr_out = wr_addr; + endcase // case(DATA_WIDTH) + + end // always @ (wr_addr) + + + // matching HW behavior to pull up the unused output bits + always @(rdcount_out) begin + + if (FIFO_SIZE == 18) + case (DATA_WIDTH) + 4 : rdcount_out_out = {1'b1, rdcount_out[11:0]}; + 9 : rdcount_out_out = {2'b11, rdcount_out[10:0]}; + 18 : rdcount_out_out = {3'b111, rdcount_out[9:0]}; + 36 : rdcount_out_out = {4'hf, rdcount_out[8:0]}; + default : rdcount_out_out = rdcount_out; + endcase // case(DATA_WIDTH) + else + case (DATA_WIDTH) + 4 : rdcount_out_out = rdcount_out; + 9 : rdcount_out_out = {1'b1, rdcount_out[11:0]}; + 18 : rdcount_out_out = {2'b11, rdcount_out[10:0]}; + 36 : rdcount_out_out = {3'b111, rdcount_out[9:0]}; + 72 : rdcount_out_out = {4'hf, rdcount_out[8:0]}; + default : rdcount_out_out = rdcount_out; + endcase // case(DATA_WIDTH) + + end // always @ (rdcount_out) + + end // if (SIM_MODE == "SAFE") + endgenerate + // end SAFE mode + + +/*************************** FAST mode *********************************/ + generate if (SIM_MODE == "FAST") begin + + assign DO = do_out_mux; + assign DOP = dop_out_mux; + assign ALMOSTEMPTY = almostempty_out; + assign ALMOSTFULL = almostfull_out; + assign EMPTY = empty_out; + assign FULL = full_out; + assign RDERR = rderr_out; + assign WRERR = wrerr_out; + assign SBITERR = sbiterr_out_out; + assign DBITERR = dbiterr_out_out; + assign ECCPARITY = eccparity_out; + assign RDCOUNT = rdcount_out; + assign WRCOUNT = wr_addr; + + always @(GSR) + if (GSR == 1'b1) begin + assign do_out = 64'b0; + assign dop_out = 8'b0; + assign do_outreg = 64'b0; + assign dop_outreg = 8'b0; + end + else if (GSR == 1'b0) begin + deassign do_out; + deassign dop_out; + deassign do_outreg; + deassign dop_outreg; + end + + always @(GSR or RST) + if (GSR == 1'b1 || RST == 1'b1) begin + assign almostempty_int = 4'b1111; + assign almostempty_out = 1'b1; + assign almostfull_int = 4'b0000; + assign almostfull_out = 1'b0; + assign do_in = 64'b00000000000000000000000000000000; + assign dop_in = 8'b0000; + assign empty_ram = 4'b1111; + assign empty_out = 1'b1; + assign full_int = 4'b0000; + assign full_out = 1'b0; + assign rdcount_out = 13'b0; + assign rderr_out = 0; + assign wrerr_out = 0; + assign rd_addr = 0; + assign rd_prefetch = 0; + assign wr_addr = 0; + assign wr1_addr = 0; + assign rdcount_flag = 0; + assign rd_flag = 0; + assign rdprefetch_flag = 0; + assign wr_flag = 0; + assign wr1_flag = 0; + assign awr_flag = 0; + end + else if (GSR == 1'b0 || RST == 1'b0) begin + deassign almostempty_int; + deassign almostempty_out; + deassign almostfull_int; + deassign almostfull_out; + deassign do_in; + deassign dop_in; + deassign empty_ram; + deassign empty_out; + deassign full_int; + deassign full_out; + deassign rdcount_out; + deassign rderr_out; + deassign wrerr_out; + deassign rd_addr; + deassign rd_prefetch; + deassign wr_addr; + deassign wr1_addr; + deassign rdcount_flag; + deassign rd_flag; + deassign rdprefetch_flag; + deassign wr_flag; + deassign wr1_flag; + deassign awr_flag; + end + + initial begin + + case (DATA_WIDTH) + 4 : begin + if (FIFO_SIZE == 36) + addr_limit = 8192; + else + addr_limit = 4096; + end + 9 : begin + if (FIFO_SIZE == 36) + addr_limit = 4096; + else + addr_limit = 2048; + end + 18 : begin + if (FIFO_SIZE == 36) + addr_limit = 2048; + else + addr_limit = 1024; + end + 36 : begin + if (FIFO_SIZE == 36) + addr_limit = 1024; + else + addr_limit = 512; + end + 72 : begin + addr_limit = 512; + end + endcase + + + case (EN_SYN) + "FALSE" : sync = 0; + "TRUE" : sync = 1; + endcase // case(EN_SYN) + + + case (FIRST_WORD_FALL_THROUGH) + "FALSE" : begin + fwft = 0; + if (EN_SYN == "FALSE") begin + ae_empty = ALMOST_EMPTY_OFFSET - 1; + ae_full = ALMOST_FULL_OFFSET; + end + else begin + ae_empty = ALMOST_EMPTY_OFFSET; + ae_full = ALMOST_FULL_OFFSET; + end + end + "TRUE" : begin + fwft = 1; + ae_empty = ALMOST_EMPTY_OFFSET - 2; + ae_full = ALMOST_FULL_OFFSET; + end + + endcase + + + end // initial begin + + + always @(posedge RDCLK) begin + + if (sync == 1'b1) begin + + do_outreg = do_out; + dop_outreg = dop_out; + + if (RDEN == 1'b1) begin + + if (empty_out == 1'b0) begin + + do_out = mem[rdcount_out]; + dop_out = memp[rdcount_out]; + + rdcount_out = (rdcount_out + 1) % addr_limit; + + if (rdcount_out == 0) + rdcount_flag = ~rdcount_flag; + + end + end + + + rderr_out = (RDEN == 1'b1) && (empty_out == 1'b1); + + + if (WREN == 1'b1) begin + empty_out = 1'b0; + end + else if (rdcount_out == wr_addr && rdcount_flag == wr_flag) + empty_out = 1'b1; + + if ((((rdcount_out + ae_empty) >= wr_addr) && (rdcount_flag == wr_flag)) || (((rdcount_out + ae_empty) >= (wr_addr + addr_limit) && (rdcount_flag != wr_flag)))) begin + almostempty_out = 1'b1; + end + + if ((((rdcount_out + addr_limit) > (wr_addr + ae_full)) && (rdcount_flag == wr_flag)) || ((rdcount_out > (wr_addr + ae_full)) && (rdcount_flag != wr_flag))) begin + if (wr_addr <= wr_addr + ae_full || rdcount_flag == wr_flag) + almostfull_out = 1'b0; + end + + end + else if (sync == 1'b0) begin + + rden_reg = RDEN; + if (fwft == 1'b0) begin + if ((rden_reg == 1'b1) && (rd_addr != rdcount_out)) begin + do_out = do_in; + if (DATA_WIDTH != 4) + dop_out = dop_in; + rd_addr = (rd_addr + 1) % addr_limit; + if (rd_addr == 0) + rd_flag = ~rd_flag; + end + if (((rd_addr == rdcount_out) && (empty_ram[3] == 1'b0)) || + ((rden_reg == 1'b1) && (empty_ram[1] == 1'b0))) begin + + do_in = mem[rdcount_out]; + dop_in = memp[rdcount_out]; + + #1; + rdcount_out = (rdcount_out + 1) % addr_limit; + if (rdcount_out == 0) begin + rdcount_flag = ~rdcount_flag; + end + end + end + + if (fwft == 1'b1) begin + + if ((rden_reg == 1'b1) && (rd_addr != rd_prefetch)) begin + rd_prefetch = (rd_prefetch + 1) % addr_limit; + if (rd_prefetch == 0) + rdprefetch_flag = ~rdprefetch_flag; + end + if ((rd_prefetch == rd_addr) && (rd_addr != rdcount_out)) begin + do_out = do_in; + if (DATA_WIDTH != 4) + dop_out = dop_in; + rd_addr = (rd_addr + 1) % addr_limit; + if (rd_addr == 0) + rd_flag = ~rd_flag; + end + if (((rd_addr == rdcount_out) && (empty_ram[3] == 1'b0)) || + ((rden_reg == 1'b1) && (empty_ram[1] == 1'b0)) || + ((rden_reg == 1'b0) && (empty_ram[1] == 1'b0) && (rd_addr == rdcount_out))) begin + + do_in = mem[rdcount_out]; + dop_in = memp[rdcount_out]; + + #1; + rdcount_out = (rdcount_out + 1) % addr_limit; + if (rdcount_out == 0) + rdcount_flag = ~rdcount_flag; + end + end // if (fwft == 1'b1) + + + rderr_out = (rden_reg == 1'b1) && (empty_out == 1'b1); + + almostempty_out = almostempty_int[3]; + + if ((((rdcount_out + ae_empty) >= wr_addr) && (rdcount_flag == awr_flag)) || (((rdcount_out + ae_empty) >= (wr_addr + addr_limit)) && (rdcount_flag != awr_flag))) begin + almostempty_int[3] = 1'b1; + almostempty_int[2] = 1'b1; + almostempty_int[1] = 1'b1; + almostempty_int[0] = 1'b1; + end + else if (almostempty_int[2] == 1'b0) begin + + if (rdcount_out <= rdcount_out + ae_empty || rdcount_flag != awr_flag) begin + almostempty_int[3] = almostempty_int[0]; + almostempty_int[0] = 1'b0; + end + end + + if ((((rdcount_out + addr_limit) > (wr_addr + ae_full)) && (rdcount_flag == awr_flag)) || ((rdcount_out > (wr_addr + ae_full)) && (rdcount_flag != awr_flag))) begin + + if (((rden_reg == 1'b1) && (empty_out == 1'b0)) || ((((rd_addr + 1) % addr_limit) == rdcount_out) && (almostfull_int[1] == 1'b1))) begin + almostfull_int[2] = almostfull_int[1]; + almostfull_int[1] = 1'b0; + end + end + else begin + almostfull_int[2] = 1'b1; + almostfull_int[1] = 1'b1; + end + + if (fwft == 1'b0) begin + if ((rdcount_out == rd_addr) && (rdcount_flag == rd_flag)) begin + empty_out = 1'b1; + end + else begin + empty_out = 1'b0; + end + end // if (fwft == 1'b0) + else if (fwft == 1'b1) begin + if ((rd_prefetch == rd_addr) && (rdprefetch_flag == rd_flag)) begin + empty_out = 1'b1; + end + else begin + empty_out = 1'b0; + end + end + + if ((rdcount_out == wr_addr) && (rdcount_flag == awr_flag)) begin + empty_ram[2] = 1'b1; + empty_ram[1] = 1'b1; + empty_ram[0] = 1'b1; + end + else begin + empty_ram[2] = empty_ram[1]; + empty_ram[1] = empty_ram[0]; + empty_ram[0] = 1'b0; + end + + if ((rdcount_out == wr1_addr) && (rdcount_flag == wr1_flag)) begin + empty_ram[3] = 1'b1; + end + else begin + empty_ram[3] = 1'b0; + end + + wr1_addr = wr_addr; + wr1_flag = awr_flag; + + end // if (sync == 1'b0) + end // always @ (posedge RDCLK) + + + always @(posedge WRCLK) begin + + if (sync == 1'b1) begin + + if (WREN == 1'b1) begin + + if (full_out == 1'b0) begin + + mem[wr_addr] = DI; + memp[wr_addr] = DIP; + + wr_addr = (wr_addr + 1) % addr_limit; + if (wr_addr == 0) + wr_flag = ~wr_flag; + + end + end + + + wrerr_out = (WREN == 1'b1) && (full_out == 1'b1); + + + if (RDEN == 1'b1) begin + full_out = 1'b0; + end + else if (rdcount_out == wr_addr && rdcount_flag != wr_flag) + full_out = 1'b1; + + if ((((rdcount_out + ae_empty) < wr_addr) && (rdcount_flag == wr_flag)) || (((rdcount_out + ae_empty) < (wr_addr + addr_limit) && (rdcount_flag != wr_flag)))) begin + + if (rdcount_out <= rdcount_out + ae_empty || rdcount_flag != wr_flag) + almostempty_out = 1'b0; + + end + + if ((((rdcount_out + addr_limit) <= (wr_addr + ae_full)) && (rdcount_flag == wr_flag)) || ((rdcount_out <= (wr_addr + ae_full)) && (rdcount_flag != wr_flag))) begin + almostfull_out = 1'b1; + end + + end + else if (sync == 1'b0) begin + + wren_reg = WREN; + + if (wren_reg == 1'b1 && (full_out == 1'b0)) begin + + mem[wr_addr] = DI; + memp[wr_addr] = DIP; + + #1; + wr_addr = (wr_addr + 1) % addr_limit; + + if (wr_addr == 0) + awr_flag = ~awr_flag; + + if (wr_addr == addr_limit - 1) + wr_flag = ~wr_flag; + end + + wrerr_out = (wren_reg == 1'b1) && (full_out == 1'b1); + + almostfull_out = almostfull_int[3]; + + if ((((rdcount_out + addr_limit) <= (wr_addr + ae_full)) && (rdcount_flag == awr_flag)) || ((rdcount_out <= (wr_addr + ae_full)) && (rdcount_flag != awr_flag))) begin + almostfull_int[3] = 1'b1; + almostfull_int[2] = 1'b1; + almostfull_int[1] = 1'b1; + almostfull_int[0] = 1'b1; + end + else if (almostfull_int[2] == 1'b0) begin + + if (wr_addr <= wr_addr + ae_full || rdcount_flag == awr_flag) begin + almostfull_int[3] = almostfull_int[0]; + almostfull_int[0] = 1'b0; + end + end + + if ((((rdcount_out + ae_empty) < wr_addr) && (rdcount_flag == awr_flag)) || (((rdcount_out + ae_empty) < (wr_addr + addr_limit)) && (rdcount_flag != awr_flag))) begin + if (wren_reg == 1'b1) begin + almostempty_int[2] = almostempty_int[1]; + almostempty_int[1] = 1'b0; + end + end + else begin + almostempty_int[2] = 1'b1; + almostempty_int[1] = 1'b1; + end + + if (wren_reg == 1'b1 || full_out == 1'b1) + full_out = full_int[1]; + + if (((rdcount_out == wr_addr) || (rdcount_out - 1 == wr_addr || (rdcount_out + addr_limit - 1 == wr_addr))) && almostfull_out) begin + full_int[1] = 1'b1; + full_int[0] = 1'b1; + end + else begin + full_int[1] = full_int[0]; + full_int[0] = 0; + end + + end // if (sync == 1'b0) + end // always @ (posedge WRCLK) + + + always @(do_out or dop_out or do_outreg or dop_outreg) begin + + if (sync == 1) + + case (DO_REG) + + 0 : begin + do_out_mux = do_out; + dop_out_mux = dop_out; + end + 1 : begin + do_out_mux = do_outreg; + dop_out_mux = dop_outreg; + end + endcase + + else begin + do_out_mux = do_out; + dop_out_mux = dop_out; + end // else: !if(sync == 1) + + end // always @ (do_out or dop_out or do_outreg or dop_outreg) + + + end // if (SIM_MODE == "FAST") + endgenerate + // end FAST mode + + +endmodule diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/AND2.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/AND2.v new file mode 100644 index 0000000..c2a2ea3 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/AND2.v @@ -0,0 +1,32 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/AND2.v,v 1.7 2007/05/23 21:43:33 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / 2-input AND Gate +// /___/ /\ Filename : AND2.v +// \ \ / \ Timestamp : Thu Mar 25 16:42:11 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. + +`timescale 1 ps / 1 ps + + +module AND2 (O, I0, I1); + + output O; + + input I0, I1; + + and A1 (O, I0, I1); + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/AND2B1.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/AND2B1.v new file mode 100644 index 0000000..2752a44 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/AND2B1.v @@ -0,0 +1,37 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/AND2B1.v,v 1.6 2007/05/23 21:43:32 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / 2-input AND Gate +// /___/ /\ Filename : AND2B1.v +// \ \ / \ Timestamp : Thu Mar 25 16:42:11 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. +// 05/23/07 - Added wire declaration for internal signals. + +`timescale 1 ps / 1 ps + + +module AND2B1 (O, I0, I1); + + output O; + + input I0, I1; + + wire i0_inv; + + not N0 (i0_inv, I0); + and A1 (O, i0_inv, I1); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/AND2B1L.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/AND2B1L.v new file mode 100644 index 0000000..5c6d487 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/AND2B1L.v @@ -0,0 +1,38 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/blanc/AND2B1L.v,v 1.4 2009/08/21 23:55:39 harikr Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Latch used as 2-input AND Gate +// /___/ /\ Filename : AND2B1L.v +// \ \ / \ Timestamp : Tue Feb 26 11:11:42 PST 2008 +// \___\/\___\ +// +// Revision: +// 04/01/08 - Initial version. +// 04/14/09 - Invert SRI not DI (CR517897) +// End Revision + +`timescale 1 ps / 1 ps + +module AND2B1L (O, DI, SRI); + + output O; + + input SRI, DI; + + tri0 GSR = glbl.GSR; + wire o_out, sri_b; + + + assign O = (GSR) ? 0 : o_out; + + not A0 (sri_b, SRI); + and A1 (o_out, sri_b, DI); + +endmodule diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/AND2B2.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/AND2B2.v new file mode 100644 index 0000000..8e1909c --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/AND2B2.v @@ -0,0 +1,39 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/AND2B2.v,v 1.6 2007/05/23 21:43:33 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / 2-input AND Gate +// /___/ /\ Filename : AND2B2.v +// \ \ / \ Timestamp : Thu Mar 25 16:42:11 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. +// 05/23/07 - Added wire declaration for internal signals. + +`timescale 1 ps / 1 ps + + +module AND2B2 (O, I0, I1); + + output O; + + input I0, I1; + + wire i0_inv; + wire i1_inv; + + not N1 (i1_inv, I1); + not N0 (i0_inv, I0); + and A1 (O, i0_inv, i1_inv); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/AND3.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/AND3.v new file mode 100644 index 0000000..741630a --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/AND3.v @@ -0,0 +1,33 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/AND3.v,v 1.6 2007/05/23 21:43:33 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / 3-input AND Gate +// /___/ /\ Filename : AND3.v +// \ \ / \ Timestamp : Thu Mar 25 16:42:12 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. + +`timescale 1 ps / 1 ps + + +module AND3 (O, I0, I1, I2); + + output O; + + input I0, I1, I2; + + and A1 (O, I0, I1, I2); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/AND3B1.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/AND3B1.v new file mode 100644 index 0000000..14987f0 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/AND3B1.v @@ -0,0 +1,37 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/AND3B1.v,v 1.6 2007/05/23 21:43:33 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / 3-input AND Gate +// /___/ /\ Filename : AND3B1.v +// \ \ / \ Timestamp : Thu Mar 25 16:42:12 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. +// 05/23/07 - Added wire declaration for internal signals. + +`timescale 1 ps / 1 ps + + +module AND3B1 (O, I0, I1, I2); + + output O; + + input I0, I1, I2; + + wire i0_inv; + + not N0 (i0_inv, I0); + and A1 (O, i0_inv, I1, I2); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/AND3B2.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/AND3B2.v new file mode 100644 index 0000000..95df643 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/AND3B2.v @@ -0,0 +1,39 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/AND3B2.v,v 1.6 2007/05/23 21:43:33 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / 3-input AND Gate +// /___/ /\ Filename : AND3B2.v +// \ \ / \ Timestamp : Thu Mar 25 16:42:12 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. +// 05/23/07 - Added wire declaration for internal signals. + +`timescale 1 ps / 1 ps + + +module AND3B2 (O, I0, I1, I2); + + output O; + + input I0, I1, I2; + + wire i0_inv; + wire i1_inv; + + not N1 (i1_inv, I1); + not N0 (i0_inv, I0); + and A1 (O, i0_inv, i1_inv, I2); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/AND3B3.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/AND3B3.v new file mode 100644 index 0000000..3805cb8 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/AND3B3.v @@ -0,0 +1,41 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/AND3B3.v,v 1.6 2007/05/23 21:43:33 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / 3-input AND Gate +// /___/ /\ Filename : AND3B3.v +// \ \ / \ Timestamp : Thu Mar 25 16:42:12 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. +// 05/23/07 - Added wire declaration for internal signals. + +`timescale 1 ps / 1 ps + + +module AND3B3 (O, I0, I1, I2); + + output O; + + input I0, I1, I2; + + wire i0_inv; + wire i1_inv; + wire i2_inv; + + not N2 (i2_inv, I2); + not N1 (i1_inv, I1); + not N0 (i0_inv, I0); + and A1 (O, i0_inv, i1_inv, i2_inv); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/AND4.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/AND4.v new file mode 100644 index 0000000..ac200f0 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/AND4.v @@ -0,0 +1,33 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/AND4.v,v 1.6 2007/05/23 21:43:33 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / 4-input AND Gate +// /___/ /\ Filename : AND4.v +// \ \ / \ Timestamp : Thu Mar 25 16:42:12 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. + +`timescale 1 ps / 1 ps + + +module AND4 (O, I0, I1, I2, I3); + + output O; + + input I0, I1, I2, I3; + + and A1 (O, I0, I1, I2, I3); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/AND4B1.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/AND4B1.v new file mode 100644 index 0000000..dbf7ca1 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/AND4B1.v @@ -0,0 +1,37 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/AND4B1.v,v 1.6 2007/05/23 21:43:33 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / 4-input AND Gate +// /___/ /\ Filename : AND4B1.v +// \ \ / \ Timestamp : Thu Mar 25 16:42:12 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. +// 05/23/07 - Added wire declaration for internal signals. + +`timescale 1 ps / 1 ps + + +module AND4B1 (O, I0, I1, I2, I3); + + output O; + + input I0, I1, I2, I3; + + wire i0_inv; + + not N0 (i0_inv, I0); + and A1 (O, i0_inv, I1, I2, I3); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/AND4B2.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/AND4B2.v new file mode 100644 index 0000000..f481d7f --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/AND4B2.v @@ -0,0 +1,39 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/AND4B2.v,v 1.6 2007/05/23 21:43:33 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / 4-input AND Gate +// /___/ /\ Filename : AND4B2.v +// \ \ / \ Timestamp : Thu Mar 25 16:42:12 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. +// 05/23/07 - Added wire declaration for internal signals. + +`timescale 1 ps / 1 ps + + +module AND4B2 (O, I0, I1, I2, I3); + + output O; + + input I0, I1, I2, I3; + + wire i0_inv; + wire i1_inv; + + not N1 (i1_inv, I1); + not N0 (i0_inv, I0); + and A1 (O, i0_inv, i1_inv, I2, I3); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/AND4B3.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/AND4B3.v new file mode 100644 index 0000000..21ce133 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/AND4B3.v @@ -0,0 +1,41 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/AND4B3.v,v 1.6 2007/05/23 21:43:33 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / 4-input AND Gate +// /___/ /\ Filename : AND4B3.v +// \ \ / \ Timestamp : Thu Mar 25 16:42:12 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. +// 05/23/07 - Added wire declaration for internal signals. + +`timescale 1 ps / 1 ps + + +module AND4B3 (O, I0, I1, I2, I3); + + output O; + + input I0, I1, I2, I3; + + wire i0_inv; + wire i1_inv; + wire i2_inv; + + not N2 (i2_inv, I2); + not N1 (i1_inv, I1); + not N0 (i0_inv, I0); + and A1 (O, i0_inv, i1_inv, i2_inv, I3); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/AND4B4.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/AND4B4.v new file mode 100644 index 0000000..0bacc6c --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/AND4B4.v @@ -0,0 +1,43 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/AND4B4.v,v 1.6 2007/05/23 21:43:33 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / 4-input AND Gate +// /___/ /\ Filename : AND4B4.v +// \ \ / \ Timestamp : Thu Mar 25 16:42:12 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. +// 05/23/07 - Added wire declaration for internal signals. + +`timescale 1 ps / 1 ps + + +module AND4B4 (O, I0, I1, I2, I3); + + output O; + + input I0, I1, I2, I3; + + wire i0_inv; + wire i1_inv; + wire i2_inv; + wire i3_inv; + + not N3 (i3_inv, I3); + not N2 (i2_inv, I2); + not N1 (i1_inv, I1); + not N0 (i0_inv, I0); + and A1 (O, i0_inv, i1_inv, i2_inv, i3_inv); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/AND5.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/AND5.v new file mode 100644 index 0000000..0114827 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/AND5.v @@ -0,0 +1,33 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/AND5.v,v 1.6 2007/05/23 21:43:33 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / 5-input AND Gate +// /___/ /\ Filename : AND5.v +// \ \ / \ Timestamp : Thu Mar 25 16:42:12 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. + +`timescale 1 ps / 1 ps + + +module AND5 (O, I0, I1, I2, I3, I4); + + output O; + + input I0, I1, I2, I3, I4; + + and A1 (O, I0, I1, I2, I3, I4); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/AND5B1.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/AND5B1.v new file mode 100644 index 0000000..9dff05a --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/AND5B1.v @@ -0,0 +1,37 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/AND5B1.v,v 1.6 2007/05/23 21:43:33 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / 5-input AND Gate +// /___/ /\ Filename : AND5B1.v +// \ \ / \ Timestamp : Thu Mar 25 16:42:12 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. +// 05/23/07 - Added wire declaration for internal signals. + +`timescale 1 ps / 1 ps + + +module AND5B1 (O, I0, I1, I2, I3, I4); + + output O; + + input I0, I1, I2, I3, I4; + + wire i0_inv; + + not N0 (i0_inv, I0); + and A1 (O, i0_inv, I1, I2, I3, I4); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/AND5B2.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/AND5B2.v new file mode 100644 index 0000000..2fe62fb --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/AND5B2.v @@ -0,0 +1,39 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/AND5B2.v,v 1.6 2007/05/23 21:43:33 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / 5-input AND Gate +// /___/ /\ Filename : AND5B2.v +// \ \ / \ Timestamp : Thu Mar 25 16:42:13 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. +// 05/23/07 - Added wire declaration for internal signals. + +`timescale 1 ps / 1 ps + + +module AND5B2 (O, I0, I1, I2, I3, I4); + + output O; + + input I0, I1, I2, I3, I4; + + wire i0_inv; + wire i1_inv; + + not N1 (i1_inv, I1); + not N0 (i0_inv, I0); + and A1 (O, i0_inv, i1_inv, I2, I3, I4); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/AND5B3.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/AND5B3.v new file mode 100644 index 0000000..bd57eef --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/AND5B3.v @@ -0,0 +1,41 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/AND5B3.v,v 1.6 2007/05/23 21:43:33 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / 5-input AND Gate +// /___/ /\ Filename : AND5B3.v +// \ \ / \ Timestamp : Thu Mar 25 16:42:13 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. +// 05/23/07 - Added wire declaration for internal signals. + +`timescale 1 ps / 1 ps + + +module AND5B3 (O, I0, I1, I2, I3, I4); + + output O; + + input I0, I1, I2, I3, I4; + + wire i0_inv; + wire i1_inv; + wire i2_inv; + + not N2 (i2_inv, I2); + not N1 (i1_inv, I1); + not N0 (i0_inv, I0); + and A1 (O, i0_inv, i1_inv, i2_inv, I3, I4); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/AND5B4.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/AND5B4.v new file mode 100644 index 0000000..3d750eb --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/AND5B4.v @@ -0,0 +1,43 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/AND5B4.v,v 1.6 2007/05/23 21:43:33 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / 5-input AND Gate +// /___/ /\ Filename : AND5B4.v +// \ \ / \ Timestamp : Thu Mar 25 16:42:13 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. +// 05/23/07 - Added wire declaration for internal signals. + +`timescale 1 ps / 1 ps + + +module AND5B4 (O, I0, I1, I2, I3, I4); + + output O; + + input I0, I1, I2, I3, I4; + + wire i0_inv; + wire i1_inv; + wire i2_inv; + wire i3_inv; + + not N3 (i3_inv, I3); + not N2 (i2_inv, I2); + not N1 (i1_inv, I1); + not N0 (i0_inv, I0); + and A1 (O, i0_inv, i1_inv, i2_inv, i3_inv, I4); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/AND5B5.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/AND5B5.v new file mode 100644 index 0000000..fac57d5 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/AND5B5.v @@ -0,0 +1,45 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/AND5B5.v,v 1.6 2007/05/23 21:43:33 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / 5-input AND Gate +// /___/ /\ Filename : AND5B5.v +// \ \ / \ Timestamp : Thu Mar 25 16:42:13 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. +// 05/23/07 - Added wire declaration for internal signals. + +`timescale 1 ps / 1 ps + + +module AND5B5 (O, I0, I1, I2, I3, I4); + + output O; + + input I0, I1, I2, I3, I4; + + wire i0_inv; + wire i1_inv; + wire i2_inv; + wire i3_inv; + wire i4_inv; + + not N4 (i4_inv, I4); + not N3 (i3_inv, I3); + not N2 (i2_inv, I2); + not N1 (i1_inv, I1); + not N0 (i0_inv, I0); + and A1 (O, i0_inv, i1_inv, i2_inv, i3_inv, i4_inv); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/ARAMB36_INTERNAL.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/ARAMB36_INTERNAL.v new file mode 100644 index 0000000..21e2aa1 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/ARAMB36_INTERNAL.v @@ -0,0 +1,3327 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/rainier/ARAMB36_INTERNAL.v,v 1.37 2010/01/21 19:36:41 wloo Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2005 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : This is not an user primitive. +// / / Xilinx Functional Simulation Library Component 32K-Bit Data and 4K-Bit Parity Dual Port Block RAM. +// /___/ /\ Filename : ARAMB36_INTERNAL.v +// \ \ / \ Timestamp : Tues July 26 16:43:59 PST 2005 +// \___\/\___\ +// +// Revision: +// 07/26/05 - Initial version. +// 12/14/05 - Cleaned up parameter checking. +// 02/09/06 - Added collision support. +// 06/15/06 - Fixed clock edge detection (CR 232994). +// 06/27/06 - Added 2 dimensional memory array support for Virtex 4 block ram. +// 09/14/06 - Fixed collision (CR 422406). +// 10/09/06 - Fixed collision case when READ_WIDTH_A/B = 16 (CR 424558). +// 11/01/06 - Fixed collision (CR 427720). +// 12/06/06 - Added DRC to disable EN_ECC_SCRUB feature (CR 427875). +// 12/07/06 - Updated functional warning for Virtex 4 byte write feature (CR 428207). +// 01/02/07 - Fixed parity bit for Virtex 4 byte write feature (CR 431583). +// 01/04/07 - Added support of memory file to initialize memory and parity (CR 431584). +// 03/13/07 - Removed attribute INITP_FILE (CR 436003). +// 03/28/07 - Disabled V4 byte write warning when READ_WIDTH_* = 0 (CR 429400). +// 04/03/07 - Changed INIT_FILE = "NONE" as default (CR 436812). +// 06/01/07 - Added wire declaration for internal signals. +// 06/13/07 - Implemented high performace version of the model. +// 06/20/07 - Fixed collision address when cascaded block rams (CR 440250). +// 08/15/07 - Updated SSR as not supported feature in output register mode for ramb16 (CR 445314). +// 08/17/07 - Supported new memory file format (SLIB_M2.3). +// 09/18/07 - Fixed DRC check for V4 ramb16 (CR 448739). +// 10/01/07 - Added conditional statement for SSRA in cascade mode (CR 449340). +// 02/20/08 - Updated collison address when cascaded block rams (CR 451722). +// 11/04/08 - Fixed incorrect output during first clock cycle (CR 470964). +// 11/06/08 - Added DRC for invalid input parity for ECC (CR 482976). +// 04/24/09 - Implemented X's in sbiterr and dbiterr outputs during collision in ECC mode (CR 508071). +// 08/21/09 - Fixed address checking for collision (CR 529759). +// 11/17/09 - Implemented DRC for ADDR[15] in non-cascade mode (CR 535882). +// 11/18/09 - Define tasks and functions before calling (CR 532610). +// 11/24/09 - Undo CR 535882, bitgen or map is going to tie off ADDR[15] instead. +// 12/16/09 - Enhanced memory initialization (CR 540764). +// 01/21/10 - Fixed duplicated task and function names (CR 541993). +// End Revision + +`timescale 1 ps/1 ps + +module ARAMB36_INTERNAL (CASCADEOUTLATA, CASCADEOUTLATB, CASCADEOUTREGA, CASCADEOUTREGB, DBITERR, DOA, DOB, DOPA, DOPB, ECCPARITY, SBITERR, + ADDRA, ADDRB, CASCADEINLATA, CASCADEINLATB, CASCADEINREGA, CASCADEINREGB, CLKA, CLKB, DIA, DIB, DIPA, DIPB, ENA, ENB, GSR, REGCEA, REGCEB, REGCLKA, REGCLKB, SSRA, SSRB, WEA, WEB); + + output CASCADEOUTLATA, CASCADEOUTREGA; + output CASCADEOUTLATB, CASCADEOUTREGB; + output SBITERR, DBITERR; + output [63:0] DOA; + output [31:0] DOB; + output [7:0] DOPA; + output [3:0] DOPB; + output [7:0] ECCPARITY; + + input ENA, CLKA, REGCLKA, SSRA, CASCADEINLATA, CASCADEINREGA, REGCEA; + input ENB, CLKB, REGCLKB, SSRB, CASCADEINLATB, CASCADEINREGB, REGCEB; + input GSR; + input [15:0] ADDRA; + input [15:0] ADDRB; + input [63:0] DIA; + input [63:0] DIB; + input [3:0] DIPA; + input [7:0] DIPB; + input [7:0] WEA; + input [7:0] WEB; + + parameter DOA_REG = 0; + parameter DOB_REG = 0; + parameter EN_ECC_READ = "FALSE"; + parameter EN_ECC_SCRUB = "FALSE"; + parameter EN_ECC_WRITE = "FALSE"; + parameter INIT_A = 72'h0; + parameter INIT_B = 72'h0; + parameter RAM_EXTENSION_A = "NONE"; + parameter RAM_EXTENSION_B = "NONE"; + parameter READ_WIDTH_A = 0; + parameter READ_WIDTH_B = 0; + parameter SETUP_ALL = 1000; + parameter SETUP_READ_FIRST = 3000; + parameter SIM_COLLISION_CHECK = "ALL"; + parameter SRVAL_A = 72'h0; + parameter SRVAL_B = 72'h0; + parameter WRITE_MODE_A = "WRITE_FIRST"; + parameter WRITE_MODE_B = "WRITE_FIRST"; + parameter WRITE_WIDTH_A = 0; + parameter WRITE_WIDTH_B = 0; + parameter INIT_FILE = "NONE"; + parameter SIM_MODE = "SAFE"; + + parameter INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_40 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_41 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_42 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_43 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_44 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_45 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_46 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_47 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_48 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_49 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_4A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_4B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_4C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_4D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_4E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_4F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_50 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_51 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_52 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_53 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_54 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_55 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_56 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_57 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_58 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_59 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_5A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_5B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_5C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_5D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_5E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_5F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_60 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_61 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_62 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_63 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_64 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_65 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_66 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_67 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_68 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_69 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_6A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_6B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_6C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_6D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_6E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_6F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_70 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_71 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_72 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_73 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_74 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_75 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_76 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_77 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_78 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_79 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_7A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_7B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_7C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_7D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_7E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_7F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + +// xilinx_internal_parameter on + // WARNING !!!: This model may not work properly if the following parameters are changed. + parameter BRAM_MODE = "TRUE_DUAL_PORT"; + parameter BRAM_SIZE = 36; +// xilinx_internal_parameter off + + localparam widest_width = (WRITE_WIDTH_A >= WRITE_WIDTH_B && WRITE_WIDTH_A >= READ_WIDTH_A && + WRITE_WIDTH_A >= READ_WIDTH_B) ? WRITE_WIDTH_A : + (WRITE_WIDTH_B >= WRITE_WIDTH_A && WRITE_WIDTH_B >= READ_WIDTH_A && + WRITE_WIDTH_B >= READ_WIDTH_B) ? WRITE_WIDTH_B : + (READ_WIDTH_A >= WRITE_WIDTH_A && READ_WIDTH_A >= WRITE_WIDTH_B && + READ_WIDTH_A >= READ_WIDTH_B) ? READ_WIDTH_A : + (READ_WIDTH_B >= WRITE_WIDTH_A && READ_WIDTH_B >= WRITE_WIDTH_B && + READ_WIDTH_B >= READ_WIDTH_A) ? READ_WIDTH_B : 64; + + localparam wa_width = (WRITE_WIDTH_A == 1) ? 1 : (WRITE_WIDTH_A == 2) ? 2 : (WRITE_WIDTH_A == 4) ? 4 : + (WRITE_WIDTH_A == 9) ? 8 : (WRITE_WIDTH_A == 18) ? 16 : (WRITE_WIDTH_A == 36) ? 32 : + (WRITE_WIDTH_A == 72) ? 64 : 64; + + localparam wb_width = (WRITE_WIDTH_B == 1) ? 1 : (WRITE_WIDTH_B == 2) ? 2 : (WRITE_WIDTH_B == 4) ? 4 : + (WRITE_WIDTH_B == 9) ? 8 : (WRITE_WIDTH_B == 18) ? 16 : (WRITE_WIDTH_B == 36) ? 32 : + (WRITE_WIDTH_B == 72) ? 64 : 64; + + + localparam wa_widthp = (WRITE_WIDTH_A == 9) ? 1 : (WRITE_WIDTH_A == 18) ? 2 : (WRITE_WIDTH_A == 36) ? 4 : + (WRITE_WIDTH_A == 72) ? 8 : 8; + + localparam wb_widthp = (WRITE_WIDTH_B == 9) ? 1 : (WRITE_WIDTH_B == 18) ? 2 : (WRITE_WIDTH_B == 36) ? 4 : + (WRITE_WIDTH_B == 72) ? 8 : 8; + + + localparam ra_width = (READ_WIDTH_A == 1) ? 1 : (READ_WIDTH_A == 2) ? 2 : (READ_WIDTH_A == 4) ? 4 : + (READ_WIDTH_A == 9) ? 8 : (READ_WIDTH_A == 18) ? 16 : (READ_WIDTH_A == 36) ? 32 : + (READ_WIDTH_A == 72) ? 64 : 64; + + localparam rb_width = (READ_WIDTH_B == 1) ? 1 : (READ_WIDTH_B == 2) ? 2 : (READ_WIDTH_B == 4) ? 4 : + (READ_WIDTH_B == 9) ? 8 : (READ_WIDTH_B == 18) ? 16 : (READ_WIDTH_B == 36) ? 32 : + (READ_WIDTH_B == 72) ? 64 : 64; + + + localparam ra_widthp = (READ_WIDTH_A == 9) ? 1 : (READ_WIDTH_A == 18) ? 2 : (READ_WIDTH_A == 36) ? 4 : + (READ_WIDTH_A == 72) ? 8 : 8; + + localparam rb_widthp = (READ_WIDTH_B == 9) ? 1 : (READ_WIDTH_B == 18) ? 2 : (READ_WIDTH_B == 36) ? 4 : + (READ_WIDTH_B == 72) ? 8 : 8; + + localparam col_addr_lsb = (widest_width == 1) ? 0 : (widest_width == 2) ? 1 : (widest_width == 4) ? 2 : + (widest_width == 9) ? 3 : (widest_width == 18) ? 4 : (widest_width == 36) ? 5 : + (widest_width == 72) ? 6 : 0; + + localparam width = (widest_width == 1) ? 1 : (widest_width == 2) ? 2 : (widest_width == 4) ? 4 : + (widest_width == 9) ? 8 : (widest_width == 18) ? 16 : (widest_width == 36) ? 32 : + (widest_width == 72) ? 64 : 64; + + localparam widthp = (widest_width == 9) ? 1 : (widest_width == 18) ? 2 : (widest_width == 36) ? 4 : + (widest_width == 72) ? 8 : 8; + + + localparam r_addra_lbit_124 = (READ_WIDTH_A == 1) ? 0 : (READ_WIDTH_A == 2) ? 1 : + (READ_WIDTH_A == 4) ? 2 : (READ_WIDTH_A == 9) ? 3 : + (READ_WIDTH_A == 18) ? 4 : (READ_WIDTH_A == 36) ? 5 : + (READ_WIDTH_A == 72) ? 6 : 10; + + localparam r_addrb_lbit_124 = (READ_WIDTH_B == 1) ? 0 : (READ_WIDTH_B == 2) ? 1 : + (READ_WIDTH_B == 4) ? 2 : (READ_WIDTH_B == 9) ? 3 : + (READ_WIDTH_B == 18) ? 4 : (READ_WIDTH_B == 36) ? 5 : + (READ_WIDTH_B == 72) ? 6 : 10; + + localparam addra_lbit_124 = (WRITE_WIDTH_A == 1) ? 0 : (WRITE_WIDTH_A == 2) ? 1 : + (WRITE_WIDTH_A == 4) ? 2 : (WRITE_WIDTH_A == 9) ? 3 : + (WRITE_WIDTH_A == 18) ? 4 : (WRITE_WIDTH_A == 36) ? 5 : + (WRITE_WIDTH_A == 72) ? 6 : 10; + + localparam addrb_lbit_124 = (WRITE_WIDTH_B == 1) ? 0 : (WRITE_WIDTH_B == 2) ? 1 : + (WRITE_WIDTH_B == 4) ? 2 : (WRITE_WIDTH_B == 9) ? 3 : + (WRITE_WIDTH_B == 18) ? 4 : (WRITE_WIDTH_B == 36) ? 5 : + (WRITE_WIDTH_B == 72) ? 6 : 10; + + localparam addra_bit_124 = (WRITE_WIDTH_A == 1 && widest_width == 2) ? 0 : (WRITE_WIDTH_A == 1 && widest_width == 4) ? 1 : + (WRITE_WIDTH_A == 1 && widest_width == 9) ? 2 : (WRITE_WIDTH_A == 1 && widest_width == 18) ? 3 : + (WRITE_WIDTH_A == 1 && widest_width == 36) ? 4 : (WRITE_WIDTH_A == 1 && widest_width == 72) ? 5 : + (WRITE_WIDTH_A == 2 && widest_width == 4) ? 1 : (WRITE_WIDTH_A == 2 && widest_width == 9) ? 2 : + (WRITE_WIDTH_A == 2 && widest_width == 18) ? 3 : (WRITE_WIDTH_A == 2 && widest_width == 36) ? 4 : + (WRITE_WIDTH_A == 2 && widest_width == 72) ? 5 : (WRITE_WIDTH_A == 4 && widest_width == 9) ? 2 : + (WRITE_WIDTH_A == 4 && widest_width == 18) ? 3 : (WRITE_WIDTH_A == 4 && widest_width == 36) ? 4 : + (WRITE_WIDTH_A == 4 && widest_width == 72) ? 5 : 10; + + localparam r_addra_bit_124 = (READ_WIDTH_A == 1 && widest_width == 2) ? 0 : (READ_WIDTH_A == 1 && widest_width == 4) ? 1 : + (READ_WIDTH_A == 1 && widest_width == 9) ? 2 : (READ_WIDTH_A == 1 && widest_width == 18) ? 3 : + (READ_WIDTH_A == 1 && widest_width == 36) ? 4 : (READ_WIDTH_A == 1 && widest_width == 72) ? 5 : + (READ_WIDTH_A == 2 && widest_width == 4) ? 1 : (READ_WIDTH_A == 2 && widest_width == 9) ? 2 : + (READ_WIDTH_A == 2 && widest_width == 18) ? 3 : (READ_WIDTH_A == 2 && widest_width == 36) ? 4 : + (READ_WIDTH_A == 2 && widest_width == 72) ? 5 : (READ_WIDTH_A == 4 && widest_width == 9) ? 2 : + (READ_WIDTH_A == 4 && widest_width == 18) ? 3 : (READ_WIDTH_A == 4 && widest_width == 36) ? 4 : + (READ_WIDTH_A == 4 && widest_width == 72) ? 5 : 10; + + localparam addrb_bit_124 = (WRITE_WIDTH_B == 1 && widest_width == 2) ? 0 : (WRITE_WIDTH_B == 1 && widest_width == 4) ? 1 : + (WRITE_WIDTH_B == 1 && widest_width == 9) ? 2 : (WRITE_WIDTH_B == 1 && widest_width == 18) ? 3 : + (WRITE_WIDTH_B == 1 && widest_width == 36) ? 4 : (WRITE_WIDTH_B == 1 && widest_width == 72) ? 5 : + (WRITE_WIDTH_B == 2 && widest_width == 4) ? 1 : (WRITE_WIDTH_B == 2 && widest_width == 9) ? 2 : + (WRITE_WIDTH_B == 2 && widest_width == 18) ? 3 : (WRITE_WIDTH_B == 2 && widest_width == 36) ? 4 : + (WRITE_WIDTH_B == 2 && widest_width == 72) ? 5 : (WRITE_WIDTH_B == 4 && widest_width == 9) ? 2 : + (WRITE_WIDTH_B == 4 && widest_width == 18) ? 3 : (WRITE_WIDTH_B == 4 && widest_width == 36) ? 4 : + (WRITE_WIDTH_B == 4 && widest_width == 72) ? 5 : 10; + + localparam r_addrb_bit_124 = (READ_WIDTH_B == 1 && widest_width == 2) ? 0 : (READ_WIDTH_B == 1 && widest_width == 4) ? 1 : + (READ_WIDTH_B == 1 && widest_width == 9) ? 2 : (READ_WIDTH_B == 1 && widest_width == 18) ? 3 : + (READ_WIDTH_B == 1 && widest_width == 36) ? 4 : (READ_WIDTH_B == 1 && widest_width == 72) ? 5 : + (READ_WIDTH_B == 2 && widest_width == 4) ? 1 : (READ_WIDTH_B == 2 && widest_width == 9) ? 2 : + (READ_WIDTH_B == 2 && widest_width == 18) ? 3 : (READ_WIDTH_B == 2 && widest_width == 36) ? 4 : + (READ_WIDTH_B == 2 && widest_width == 72) ? 5 : (READ_WIDTH_B == 4 && widest_width == 9) ? 2 : + (READ_WIDTH_B == 4 && widest_width == 18) ? 3 : (READ_WIDTH_B == 4 && widest_width == 36) ? 4 : + (READ_WIDTH_B == 4 && widest_width == 72) ? 5 : 10; + + localparam addra_bit_8 = (WRITE_WIDTH_A == 9 && widest_width == 18) ? 3 : (WRITE_WIDTH_A == 9 && widest_width == 36) ? 4 : + (WRITE_WIDTH_A == 9 && widest_width == 72) ? 5 : 10; + + localparam addra_bit_16 = (WRITE_WIDTH_A == 18 && widest_width == 36) ? 4 : (WRITE_WIDTH_A == 18 && widest_width == 72) ? 5 : 10; + + localparam addra_bit_32 = (WRITE_WIDTH_A == 36 && widest_width == 72) ? 5 : 10; + + + localparam r_addra_bit_8 = (READ_WIDTH_A == 9 && widest_width == 18) ? 3 : (READ_WIDTH_A == 9 && widest_width == 36) ? 4 : + (READ_WIDTH_A == 9 && widest_width == 72) ? 5 : 10; + + localparam r_addra_bit_16 = (READ_WIDTH_A == 18 && widest_width == 36) ? 4 : (READ_WIDTH_A == 18 && widest_width == 72) ? 5 : 10; + + localparam r_addra_bit_32 = (READ_WIDTH_A == 36 && widest_width == 72) ? 5 : 10; + + localparam addrb_bit_8 = (WRITE_WIDTH_B == 9 && widest_width == 18) ? 3 : (WRITE_WIDTH_B == 9 && widest_width == 36) ? 4 : + (WRITE_WIDTH_B == 9 && widest_width == 72) ? 5 : 10; + + localparam addrb_bit_16 = (WRITE_WIDTH_B == 18 && widest_width == 36) ? 4 : (WRITE_WIDTH_B == 18 && widest_width == 72) ? 5 : 10; + + localparam addrb_bit_32 = (WRITE_WIDTH_B == 36 && widest_width == 72) ? 5 : 10; + + + localparam r_addrb_bit_8 = (READ_WIDTH_B == 9 && widest_width == 18) ? 3 : (READ_WIDTH_B == 9 && widest_width == 36) ? 4 : + (READ_WIDTH_B == 9 && widest_width == 72) ? 5 : 10; + + localparam r_addrb_bit_16 = (READ_WIDTH_B == 18 && widest_width == 36) ? 4 : (READ_WIDTH_B == 18 && widest_width == 72) ? 5 : 10; + + localparam r_addrb_bit_32 = (READ_WIDTH_B == 36 && widest_width == 72) ? 5 : 10; + + localparam mem_size1 = (BRAM_SIZE == 18) ? 16384 : (BRAM_SIZE == 36) ? 32768 : 32768; + localparam mem_size2 = (BRAM_SIZE == 18) ? 8192 : (BRAM_SIZE == 36) ? 16384 : 16384; + localparam mem_size4 = (BRAM_SIZE == 18) ? 4096 : (BRAM_SIZE == 36) ? 8192 : 8192; + localparam mem_size9 = (BRAM_SIZE == 18) ? 2048 : (BRAM_SIZE == 36) ? 4096 : 4096; + localparam mem_size18 = (BRAM_SIZE == 18) ? 1024 : (BRAM_SIZE == 36) ? 2048 : 2048; + localparam mem_size36 = (BRAM_SIZE == 18) ? 512 : (BRAM_SIZE == 36) ? 1024 : 1024; + localparam mem_size72 = (BRAM_SIZE == 18) ? 0 : (BRAM_SIZE == 36) ? 512 : 512; + + localparam mem_depth = (widest_width == 1) ? mem_size1 : (widest_width == 2) ? mem_size2 : (widest_width == 4) ? mem_size4 : + (widest_width == 9) ? mem_size9 :(widest_width == 18) ? mem_size18 : (widest_width == 36) ? mem_size36 : + (widest_width == 72) ? mem_size72 : 32768; + + localparam memp_depth = (widest_width == 9) ? mem_size9 :(widest_width == 18) ? mem_size18 : (widest_width == 36) ? mem_size36 : + (widest_width == 72) ? mem_size72 : 4096; + + reg [widest_width-1:0] tmp_mem [mem_depth-1:0]; + + reg [width-1:0] mem [mem_depth-1:0]; + reg [widthp-1:0] memp [memp_depth-1:0]; + + integer count, countp, init_mult, initp_mult, large_width; + integer count1, countp1, i, i1, i_p, i_mem, init_offset, initp_offset; + + reg addra_in_15_reg_bram, addrb_in_15_reg_bram; + reg addra_in_15_reg, addrb_in_15_reg; + reg addra_in_15_reg1, addrb_in_15_reg1; + reg junk1; + reg [1:0] wr_mode_a, wr_mode_b, cascade_a, cascade_b; + reg [63:0] doa_out = 64'b0, doa_buf = 64'b0, doa_outreg = 64'b0, doa_out_out = 64'b0; + reg [31:0] dob_out = 32'b0, dob_buf = 32'b0, dob_outreg = 32'b0, dob_out_out = 32'b0; + reg [3:0] dopb_out = 4'b0, dopb_buf = 4'b0, dopb_outreg = 4'b0, dopb_out_out = 4'b0; + reg [7:0] dopa_out = 8'b0, dopa_buf = 8'b0, dopa_outreg = 8'b0, dopa_out_out = 8'b0; + reg [63:0] doa_out_mux = 64'b0, doa_outreg_mux = 64'b0; + reg [7:0] dopa_out_mux = 8'b0, dopa_outreg_mux = 8'b0; + reg [63:0] dob_out_mux = 64'b0, dob_outreg_mux = 64'b0; + reg [7:0] dopb_out_mux = 8'b0, dopb_outreg_mux = 8'b0; + + reg [7:0] eccparity_out; + reg [7:0] dopr_ecc, syndrome = 8'b0; + reg [7:0] dipb_in_ecc; + reg [71:0] ecc_bit_position; + reg [7:0] dip_ecc, dip_ecc_col, dipa_in_ecc_corrected; + reg [63:0] dia_in_ecc_corrected, di_x = 64'bx; + reg dbiterr_out = 0, sbiterr_out = 0; + reg dbiterr_outreg = 0, sbiterr_outreg = 0; + reg dbiterr_out_out = 0, sbiterr_out_out = 0; + + reg [7:0] wea_reg; + reg enb_reg; + reg [7:0] out_a = 8'b0, out_b = 8'b0, junk, web_reg, web_tmp; + reg outp_a = 1'b0, outp_b = 1'b0, junkp; + reg rising_clka = 1'b0, rising_clkb = 1'b0; + reg [15:0] addra_reg, addrb_reg, addra_tmp, addrb_tmp; + + reg [63:0] dia_reg, dib_reg; + reg [3:0] dipa_reg; + reg [7:0] dipb_reg; + reg [1:0] viol_type = 2'b00, seq = 2'b00; + reg [15:0] addr_tmp; + reg [7:0] we_tmp; + integer viol_time = 0; + reg col_wr_wr_msg = 1, col_wra_rdb_msg = 1, col_wrb_rda_msg = 1; + reg [7:0] no_col = 8'b0; + reg addr_col = 0; + + time curr_time, prev_time; + + wire [63:0] dib_in; + wire [63:0] dia_in; + wire [15:0] addra_in, addrb_in; + wire clka_in, clkb_in, regclka_in, regclkb_in; + wire [7:0] dipb_in; + wire [3:0] dipa_in; + wire ena_in, enb_in, gsr_in, regcea_in, regceb_in, ssra_in, ssrb_in; + wire [7:0] wea_in; + wire [7:0] web_in; + wire cascadeinlata_in, cascadeinlatb_in; + wire cascadeinrega_in, cascadeinregb_in; + wire temp_wire; // trigger NCsim at initial time + assign temp_wire = 1; + + + initial begin + + if (INIT_FILE == "NONE") begin + + init_mult = 256/width; + + for (count = 0; count < init_mult; count = count + 1) begin + + init_offset = count * width; + + mem[count] = INIT_00[init_offset +:width]; + mem[count + (init_mult * 1)] = INIT_01[init_offset +:width]; + mem[count + (init_mult * 2)] = INIT_02[init_offset +:width]; + mem[count + (init_mult * 3)] = INIT_03[init_offset +:width]; + mem[count + (init_mult * 4)] = INIT_04[init_offset +:width]; + mem[count + (init_mult * 5)] = INIT_05[init_offset +:width]; + mem[count + (init_mult * 6)] = INIT_06[init_offset +:width]; + mem[count + (init_mult * 7)] = INIT_07[init_offset +:width]; + mem[count + (init_mult * 8)] = INIT_08[init_offset +:width]; + mem[count + (init_mult * 9)] = INIT_09[init_offset +:width]; + mem[count + (init_mult * 10)] = INIT_0A[init_offset +:width]; + mem[count + (init_mult * 11)] = INIT_0B[init_offset +:width]; + mem[count + (init_mult * 12)] = INIT_0C[init_offset +:width]; + mem[count + (init_mult * 13)] = INIT_0D[init_offset +:width]; + mem[count + (init_mult * 14)] = INIT_0E[init_offset +:width]; + mem[count + (init_mult * 15)] = INIT_0F[init_offset +:width]; + mem[count + (init_mult * 16)] = INIT_10[init_offset +:width]; + mem[count + (init_mult * 17)] = INIT_11[init_offset +:width]; + mem[count + (init_mult * 18)] = INIT_12[init_offset +:width]; + mem[count + (init_mult * 19)] = INIT_13[init_offset +:width]; + mem[count + (init_mult * 20)] = INIT_14[init_offset +:width]; + mem[count + (init_mult * 21)] = INIT_15[init_offset +:width]; + mem[count + (init_mult * 22)] = INIT_16[init_offset +:width]; + mem[count + (init_mult * 23)] = INIT_17[init_offset +:width]; + mem[count + (init_mult * 24)] = INIT_18[init_offset +:width]; + mem[count + (init_mult * 25)] = INIT_19[init_offset +:width]; + mem[count + (init_mult * 26)] = INIT_1A[init_offset +:width]; + mem[count + (init_mult * 27)] = INIT_1B[init_offset +:width]; + mem[count + (init_mult * 28)] = INIT_1C[init_offset +:width]; + mem[count + (init_mult * 29)] = INIT_1D[init_offset +:width]; + mem[count + (init_mult * 30)] = INIT_1E[init_offset +:width]; + mem[count + (init_mult * 31)] = INIT_1F[init_offset +:width]; + mem[count + (init_mult * 32)] = INIT_20[init_offset +:width]; + mem[count + (init_mult * 33)] = INIT_21[init_offset +:width]; + mem[count + (init_mult * 34)] = INIT_22[init_offset +:width]; + mem[count + (init_mult * 35)] = INIT_23[init_offset +:width]; + mem[count + (init_mult * 36)] = INIT_24[init_offset +:width]; + mem[count + (init_mult * 37)] = INIT_25[init_offset +:width]; + mem[count + (init_mult * 38)] = INIT_26[init_offset +:width]; + mem[count + (init_mult * 39)] = INIT_27[init_offset +:width]; + mem[count + (init_mult * 40)] = INIT_28[init_offset +:width]; + mem[count + (init_mult * 41)] = INIT_29[init_offset +:width]; + mem[count + (init_mult * 42)] = INIT_2A[init_offset +:width]; + mem[count + (init_mult * 43)] = INIT_2B[init_offset +:width]; + mem[count + (init_mult * 44)] = INIT_2C[init_offset +:width]; + mem[count + (init_mult * 45)] = INIT_2D[init_offset +:width]; + mem[count + (init_mult * 46)] = INIT_2E[init_offset +:width]; + mem[count + (init_mult * 47)] = INIT_2F[init_offset +:width]; + mem[count + (init_mult * 48)] = INIT_30[init_offset +:width]; + mem[count + (init_mult * 49)] = INIT_31[init_offset +:width]; + mem[count + (init_mult * 50)] = INIT_32[init_offset +:width]; + mem[count + (init_mult * 51)] = INIT_33[init_offset +:width]; + mem[count + (init_mult * 52)] = INIT_34[init_offset +:width]; + mem[count + (init_mult * 53)] = INIT_35[init_offset +:width]; + mem[count + (init_mult * 54)] = INIT_36[init_offset +:width]; + mem[count + (init_mult * 55)] = INIT_37[init_offset +:width]; + mem[count + (init_mult * 56)] = INIT_38[init_offset +:width]; + mem[count + (init_mult * 57)] = INIT_39[init_offset +:width]; + mem[count + (init_mult * 58)] = INIT_3A[init_offset +:width]; + mem[count + (init_mult * 59)] = INIT_3B[init_offset +:width]; + mem[count + (init_mult * 60)] = INIT_3C[init_offset +:width]; + mem[count + (init_mult * 61)] = INIT_3D[init_offset +:width]; + mem[count + (init_mult * 62)] = INIT_3E[init_offset +:width]; + mem[count + (init_mult * 63)] = INIT_3F[init_offset +:width]; + + if (BRAM_SIZE == 36) begin + mem[count + (init_mult * 64)] = INIT_40[init_offset +:width]; + mem[count + (init_mult * 65)] = INIT_41[init_offset +:width]; + mem[count + (init_mult * 66)] = INIT_42[init_offset +:width]; + mem[count + (init_mult * 67)] = INIT_43[init_offset +:width]; + mem[count + (init_mult * 68)] = INIT_44[init_offset +:width]; + mem[count + (init_mult * 69)] = INIT_45[init_offset +:width]; + mem[count + (init_mult * 70)] = INIT_46[init_offset +:width]; + mem[count + (init_mult * 71)] = INIT_47[init_offset +:width]; + mem[count + (init_mult * 72)] = INIT_48[init_offset +:width]; + mem[count + (init_mult * 73)] = INIT_49[init_offset +:width]; + mem[count + (init_mult * 74)] = INIT_4A[init_offset +:width]; + mem[count + (init_mult * 75)] = INIT_4B[init_offset +:width]; + mem[count + (init_mult * 76)] = INIT_4C[init_offset +:width]; + mem[count + (init_mult * 77)] = INIT_4D[init_offset +:width]; + mem[count + (init_mult * 78)] = INIT_4E[init_offset +:width]; + mem[count + (init_mult * 79)] = INIT_4F[init_offset +:width]; + mem[count + (init_mult * 80)] = INIT_50[init_offset +:width]; + mem[count + (init_mult * 81)] = INIT_51[init_offset +:width]; + mem[count + (init_mult * 82)] = INIT_52[init_offset +:width]; + mem[count + (init_mult * 83)] = INIT_53[init_offset +:width]; + mem[count + (init_mult * 84)] = INIT_54[init_offset +:width]; + mem[count + (init_mult * 85)] = INIT_55[init_offset +:width]; + mem[count + (init_mult * 86)] = INIT_56[init_offset +:width]; + mem[count + (init_mult * 87)] = INIT_57[init_offset +:width]; + mem[count + (init_mult * 88)] = INIT_58[init_offset +:width]; + mem[count + (init_mult * 89)] = INIT_59[init_offset +:width]; + mem[count + (init_mult * 90)] = INIT_5A[init_offset +:width]; + mem[count + (init_mult * 91)] = INIT_5B[init_offset +:width]; + mem[count + (init_mult * 92)] = INIT_5C[init_offset +:width]; + mem[count + (init_mult * 93)] = INIT_5D[init_offset +:width]; + mem[count + (init_mult * 94)] = INIT_5E[init_offset +:width]; + mem[count + (init_mult * 95)] = INIT_5F[init_offset +:width]; + mem[count + (init_mult * 96)] = INIT_60[init_offset +:width]; + mem[count + (init_mult * 97)] = INIT_61[init_offset +:width]; + mem[count + (init_mult * 98)] = INIT_62[init_offset +:width]; + mem[count + (init_mult * 99)] = INIT_63[init_offset +:width]; + mem[count + (init_mult * 100)] = INIT_64[init_offset +:width]; + mem[count + (init_mult * 101)] = INIT_65[init_offset +:width]; + mem[count + (init_mult * 102)] = INIT_66[init_offset +:width]; + mem[count + (init_mult * 103)] = INIT_67[init_offset +:width]; + mem[count + (init_mult * 104)] = INIT_68[init_offset +:width]; + mem[count + (init_mult * 105)] = INIT_69[init_offset +:width]; + mem[count + (init_mult * 106)] = INIT_6A[init_offset +:width]; + mem[count + (init_mult * 107)] = INIT_6B[init_offset +:width]; + mem[count + (init_mult * 108)] = INIT_6C[init_offset +:width]; + mem[count + (init_mult * 109)] = INIT_6D[init_offset +:width]; + mem[count + (init_mult * 110)] = INIT_6E[init_offset +:width]; + mem[count + (init_mult * 111)] = INIT_6F[init_offset +:width]; + mem[count + (init_mult * 112)] = INIT_70[init_offset +:width]; + mem[count + (init_mult * 113)] = INIT_71[init_offset +:width]; + mem[count + (init_mult * 114)] = INIT_72[init_offset +:width]; + mem[count + (init_mult * 115)] = INIT_73[init_offset +:width]; + mem[count + (init_mult * 116)] = INIT_74[init_offset +:width]; + mem[count + (init_mult * 117)] = INIT_75[init_offset +:width]; + mem[count + (init_mult * 118)] = INIT_76[init_offset +:width]; + mem[count + (init_mult * 119)] = INIT_77[init_offset +:width]; + mem[count + (init_mult * 120)] = INIT_78[init_offset +:width]; + mem[count + (init_mult * 121)] = INIT_79[init_offset +:width]; + mem[count + (init_mult * 122)] = INIT_7A[init_offset +:width]; + mem[count + (init_mult * 123)] = INIT_7B[init_offset +:width]; + mem[count + (init_mult * 124)] = INIT_7C[init_offset +:width]; + mem[count + (init_mult * 125)] = INIT_7D[init_offset +:width]; + mem[count + (init_mult * 126)] = INIT_7E[init_offset +:width]; + mem[count + (init_mult * 127)] = INIT_7F[init_offset +:width]; + end // if (BRAM_SIZE == 36) + end // for (count = 0; count < init_mult; count = count + 1) + + + + if (width >= 8) begin + + initp_mult = 256/widthp; + + for (countp = 0; countp < initp_mult; countp = countp + 1) begin + + initp_offset = countp * widthp; + + memp[countp] = INITP_00[initp_offset +:widthp]; + memp[countp + (initp_mult * 1)] = INITP_01[initp_offset +:widthp]; + memp[countp + (initp_mult * 2)] = INITP_02[initp_offset +:widthp]; + memp[countp + (initp_mult * 3)] = INITP_03[initp_offset +:widthp]; + memp[countp + (initp_mult * 4)] = INITP_04[initp_offset +:widthp]; + memp[countp + (initp_mult * 5)] = INITP_05[initp_offset +:widthp]; + memp[countp + (initp_mult * 6)] = INITP_06[initp_offset +:widthp]; + memp[countp + (initp_mult * 7)] = INITP_07[initp_offset +:widthp]; + + if (BRAM_SIZE == 36) begin + memp[countp + (initp_mult * 8)] = INITP_08[initp_offset +:widthp]; + memp[countp + (initp_mult * 9)] = INITP_09[initp_offset +:widthp]; + memp[countp + (initp_mult * 10)] = INITP_0A[initp_offset +:widthp]; + memp[countp + (initp_mult * 11)] = INITP_0B[initp_offset +:widthp]; + memp[countp + (initp_mult * 12)] = INITP_0C[initp_offset +:widthp]; + memp[countp + (initp_mult * 13)] = INITP_0D[initp_offset +:widthp]; + memp[countp + (initp_mult * 14)] = INITP_0E[initp_offset +:widthp]; + memp[countp + (initp_mult * 15)] = INITP_0F[initp_offset +:widthp]; + end + end // for (countp = 0; countp < initp_mult; countp = countp + 1) + end // if (width >= 8) + + end // if (INIT_FILE == "NONE") + else begin + + $readmemh (INIT_FILE, tmp_mem); + + case (widest_width) + + 1, 2, 4 : for (i_mem = 0; i_mem <= mem_depth; i_mem = i_mem + 1) + mem[i_mem] = tmp_mem [i_mem]; + + 9 : for (i_mem = 0; i_mem <= mem_depth; i_mem = i_mem + 1) begin + mem[i_mem] = tmp_mem[i_mem][0 +: 8]; + memp[i_mem] = tmp_mem[i_mem][8 +: 1]; + end + + 18 : for (i_mem = 0; i_mem <= mem_depth; i_mem = i_mem + 1) begin + mem[i_mem] = tmp_mem[i_mem][0 +: 16]; + memp[i_mem] = tmp_mem[i_mem][16 +: 2]; + end + + 36 : for (i_mem = 0; i_mem <= mem_depth; i_mem = i_mem + 1) begin + mem[i_mem] = tmp_mem[i_mem][0 +: 32]; + memp[i_mem] = tmp_mem[i_mem][32 +: 4]; + end + + 72 : for (i_mem = 0; i_mem <= mem_depth; i_mem = i_mem + 1) begin + mem[i_mem] = tmp_mem[i_mem][0 +: 64]; + memp[i_mem] = tmp_mem[i_mem][64 +: 8]; + end + + endcase // case(widest_width) + + end // else: !if(INIT_FILE == "NONE") + + + if ((SIM_MODE != "FAST") && (SIM_MODE != "SAFE")) begin + $display("Attribute Syntax Error : The attribute SIM_MODE on ARAMB36_INTERNAL instance %m is set to %s. Legal values for this attribute are FAST or SAFE.", SIM_MODE); + $finish; + end + end // initial begin + + + /********************* SAFE mode **************************/ + generate if (SIM_MODE == "SAFE") begin + +/******************************************** task and function **************************************/ + + task task_ram; + + input we; + input [7:0] di; + input dip; + inout [7:0] mem_task; + inout memp_task; + + begin + + if (we == 1'b1) begin + + mem_task = di; + + if (width >= 8) + memp_task = dip; + end + end + + endtask // task_ram + + + task task_ram_col; + + input we_o; + input we; + input [7:0] di; + input dip; + inout [7:0] mem_task; + inout memp_task; + integer i; + + begin + + if (we == 1'b1) begin + + for (i = 0; i < 8; i = i + 1) + if (mem_task[i] !== 1'bx || !(we === we_o && we === 1'b1)) + mem_task[i] = di[i]; + + if (width >= 8 && (memp_task !== 1'bx || !(we === we_o && we === 1'b1))) + memp_task = dip; + + end + end + + endtask // task_ram_col + + + task task_x_buf; + input [1:0] wr_rd_mode; + input integer do_uindex; + input integer do_lindex; + input integer dop_index; + input [63:0] do_ltmp; + inout [63:0] do_tmp; + input [7:0] dop_ltmp; + inout [7:0] dop_tmp; + integer i; + + begin + + if (wr_rd_mode == 2'b01) begin + for (i = do_lindex; i <= do_uindex; i = i + 1) begin + if (do_ltmp[i] === 1'bx) + do_tmp[i] = 1'bx; + end + + if (dop_ltmp[dop_index] === 1'bx) + dop_tmp[dop_index] = 1'bx; + + end // if (wr_rd_mode == 2'b01) + else begin + do_tmp[do_lindex +: 8] = do_ltmp[do_lindex +: 8]; + dop_tmp[dop_index] = dop_ltmp[dop_index]; + + end // else: !if(wr_rd_mode == 2'b01) + end + + endtask // task_x_buf + + + task task_col_wr_ram_a; + + input [1:0] seq; + input [7:0] web_tmp; + input [7:0] wea_tmp; + input [63:0] dia_tmp; + input [7:0] dipa_tmp; + input [15:0] addrb_tmp; + input [15:0] addra_tmp; + + begin + + case (wa_width) + + 1, 2, 4 : begin + if (!(wea_tmp[0] === 1'b1 && web_tmp[0] === 1'b1 && wa_width > wb_width) || seq == 2'b10) begin + if (wa_width >= width) + task_ram_col (web_tmp[0], wea_tmp[0], dia_tmp[wa_width-1:0], 1'b0, mem[addra_tmp[14:addra_lbit_124]], junk1); + else + task_ram_col (web_tmp[0], wea_tmp[0], dia_tmp[wa_width-1:0], 1'b0, mem[addra_tmp[14:addra_bit_124+1]][(addra_tmp[addra_bit_124:addra_lbit_124] * wa_width) +: wa_width], junk1); + + if (seq == 2'b00) + chk_for_col_msg (wea_tmp[0], web_tmp[0], addra_tmp, addrb_tmp); + + end // if (!(wea_tmp[0] === 1'b1 && web_tmp[0] === 1'b1 && wa_width > wb_width) || seq == 2'b10) + end // case: 1, 2, 4 + 8 : begin + if (!(wea_tmp[0] === 1'b1 && web_tmp[0] === 1'b1 && wa_width > wb_width) || seq == 2'b10) begin + if (wa_width >= width) + task_ram_col (web_tmp[0], wea_tmp[0], dia_tmp[7:0], dipa_tmp[0], mem[addra_tmp[14:3]], memp[addra_tmp[14:3]]); + else + task_ram_col (web_tmp[0], wea_tmp[0], dia_tmp[7:0], dipa_tmp[0], mem[addra_tmp[14:addra_bit_8+1]][(addra_tmp[addra_bit_8:3] * 8) +: 8], memp[addra_tmp[14:addra_bit_8+1]][(addra_tmp[addra_bit_8:3] * 1) +: 1]); + + if (seq == 2'b00) + chk_for_col_msg (wea_tmp[0], web_tmp[0], addra_tmp, addrb_tmp); + + end // if (wa_width <= wb_width) + end // case: 8 + 16 : begin + if (!(wea_tmp[0] === 1'b1 && web_tmp[0] === 1'b1 && wa_width > wb_width) || seq == 2'b10) begin + if (wa_width >= width) + task_ram_col (web_tmp[0], wea_tmp[0], dia_tmp[7:0], dipa_tmp[0], mem[addra_tmp[14:4]][0 +: 8], memp[addra_tmp[14:4]][0]); + else + task_ram_col (web_tmp[0], wea_tmp[0], dia_tmp[7:0], dipa_tmp[0], mem[addra_tmp[14:addra_bit_16+1]][(addra_tmp[addra_bit_16:4] * 16) +: 8], memp[addra_tmp[14:addra_bit_16+1]][(addra_tmp[addra_bit_16:4] * 2) +: 1]); + + if (seq == 2'b00) + chk_for_col_msg (wea_tmp[0], web_tmp[0], addra_tmp, addrb_tmp); + + if (wa_width >= width) + task_ram_col (web_tmp[1], wea_tmp[1], dia_tmp[15:8], dipa_tmp[1], mem[addra_tmp[14:4]][8 +: 8], memp[addra_tmp[14:4]][1]); + else + task_ram_col (web_tmp[1], wea_tmp[1], dia_tmp[15:8], dipa_tmp[1], mem[addra_tmp[14:addra_bit_16+1]][((addra_tmp[addra_bit_16:4] * 16) + 8) +: 8], memp[addra_tmp[14:addra_bit_16+1]][((addra_tmp[addra_bit_16:4] * 2) + 1) +: 1]); + + if (seq == 2'b00) + chk_for_col_msg (wea_tmp[1], web_tmp[1], addra_tmp, addrb_tmp); + + end // if (wa_width <= wb_width) + end // case: 16 + 32 : begin + if (!(wea_tmp[0] === 1'b1 && web_tmp[0] === 1'b1 && wa_width > wb_width) || seq == 2'b10) begin + task_ram_col (web_tmp[0], wea_tmp[0], dia_tmp[7:0], dipa_tmp[0], mem[addra_tmp[14:5]][0 +: 8], memp[addra_tmp[14:5]][0]); + if (seq == 2'b00) + chk_for_col_msg (wea_tmp[0], web_tmp[0], addra_tmp, addrb_tmp); + + task_ram_col (web_tmp[1], wea_tmp[1], dia_tmp[15:8], dipa_tmp[1], mem[addra_tmp[14:5]][8 +: 8], memp[addra_tmp[14:5]][1]); + if (seq == 2'b00) + chk_for_col_msg (wea_tmp[1], web_tmp[1], addra_tmp, addrb_tmp); + + task_ram_col (web_tmp[2], wea_tmp[2], dia_tmp[23:16], dipa_tmp[2], mem[addra_tmp[14:5]][16 +: 8], memp[addra_tmp[14:5]][2]); + if (seq == 2'b00) + chk_for_col_msg (wea_tmp[2], web_tmp[2], addra_tmp, addrb_tmp); + + task_ram_col (web_tmp[3], wea_tmp[3], dia_tmp[31:24], dipa_tmp[3], mem[addra_tmp[14:5]][24 +: 8], memp[addra_tmp[14:5]][3]); + if (seq == 2'b00) + chk_for_col_msg (wea_tmp[3], web_tmp[3], addra_tmp, addrb_tmp); + + end // if (wa_width <= wb_width) + end // case: 32 + 64 : ; + + endcase // case(wa_width) + + end + + endtask // task_col_wr_ram_a + + + task task_col_wr_ram_b; + + input [1:0] seq; + input [7:0] wea_tmp; + input [7:0] web_tmp; + input [63:0] dib_tmp; + input [7:0] dipb_tmp; + input [15:0] addra_tmp; + input [15:0] addrb_tmp; + + begin + + case (wb_width) + + 1, 2, 4 : begin + if (!(wea_tmp[0] === 1'b1 && web_tmp[0] === 1'b1 && wb_width > wa_width) || seq == 2'b10) begin + if (wb_width >= width) + task_ram_col (wea_tmp[0], web_tmp[0], dib_tmp[wb_width-1:0], 1'b0, mem[addrb_tmp[14:addrb_lbit_124]], junk1); + else + task_ram_col (wea_tmp[0], web_tmp[0], dib_tmp[wb_width-1:0], 1'b0, mem[addrb_tmp[14:addrb_bit_124+1]][(addrb_tmp[addrb_bit_124:addrb_lbit_124] * wb_width) +: wb_width], junk1); + + if (seq == 2'b00) + chk_for_col_msg (wea_tmp[0], web_tmp[0], addra_tmp, addrb_tmp); + + end // if (wb_width <= wa_width) + end // case: 1, 2, 4 + 8 : begin + if (!(wea_tmp[0] === 1'b1 && web_tmp[0] === 1'b1 && wb_width > wa_width) || seq == 2'b10) begin + if (wb_width >= width) + task_ram_col (wea_tmp[0], web_tmp[0], dib_tmp[7:0], dipb_tmp[0], mem[addrb_tmp[14:3]], memp[addrb_tmp[14:3]]); + else + task_ram_col (wea_tmp[0], web_tmp[0], dib_tmp[7:0], dipb_tmp[0], mem[addrb_tmp[14:addrb_bit_8+1]][(addrb_tmp[addrb_bit_8:3] * 8) +: 8], memp[addrb_tmp[14:addrb_bit_8+1]][(addrb_tmp[addrb_bit_8:3] * 1) +: 1]); + + if (seq == 2'b00) + chk_for_col_msg (wea_tmp[0], web_tmp[0], addra_tmp, addrb_tmp); + + end // if (wb_width <= wa_width) + end // case: 8 + 16 : begin + if (!(wea_tmp[0] === 1'b1 && web_tmp[0] === 1'b1 && wb_width > wa_width) || seq == 2'b10) begin + if (wb_width >= width) + task_ram_col (wea_tmp[0], web_tmp[0], dib_tmp[7:0], dipb_tmp[0], mem[addrb_tmp[14:4]][0 +: 8], memp[addrb_tmp[14:4]][0:0]); + else + task_ram_col (wea_tmp[0], web_tmp[0], dib_tmp[7:0], dipb_tmp[0], mem[addrb_tmp[14:addrb_bit_16+1]][(addrb_tmp[addrb_bit_16:4] * 16) +: 8], memp[addrb_tmp[14:addrb_bit_16+1]][(addrb_tmp[addrb_bit_16:4] * 2) +: 1]); + + if (seq == 2'b00) + chk_for_col_msg (wea_tmp[0], web_tmp[0], addra_tmp, addrb_tmp); + + + if (wb_width >= width) + task_ram_col (wea_tmp[1], web_tmp[1], dib_tmp[15:8], dipb_tmp[1], mem[addrb_tmp[14:4]][8 +: 8], memp[addrb_tmp[14:4]][1:1]); + else + task_ram_col (wea_tmp[1], web_tmp[1], dib_tmp[15:8], dipb_tmp[1], mem[addrb_tmp[14:addrb_bit_16+1]][((addrb_tmp[addrb_bit_16:4] * 16) + 8) +: 8], memp[addrb_tmp[14:addrb_bit_16+1]][((addrb_tmp[addrb_bit_16:4] * 2) + 1) +: 1]); + + if (seq == 2'b00) + chk_for_col_msg (wea_tmp[1], web_tmp[1], addra_tmp, addrb_tmp); + + end // if (!(wea_tmp[0] === 1'b1 && web_tmp[0] === 1'b1 && wb_width > wa_width) || seq == 2'b10) + end // case: 16 + 32 : begin + if (!(wea_tmp[0] === 1'b1 && web_tmp[0] === 1'b1 && wb_width > wa_width) || seq == 2'b10) begin + task_ram_col (wea_tmp[0], web_tmp[0], dib_tmp[7:0], dipb_tmp[0], mem[addrb_tmp[14:5]][0 +: 8], memp[addrb_tmp[14:5]][0:0]); + if (seq == 2'b00) + chk_for_col_msg (wea_tmp[0], web_tmp[0], addra_tmp, addrb_tmp); + + task_ram_col (wea_tmp[1], web_tmp[1], dib_tmp[15:8], dipb_tmp[1], mem[addrb_tmp[14:5]][8 +: 8], memp[addrb_tmp[14:5]][1:1]); + if (seq == 2'b00) + chk_for_col_msg (wea_tmp[1], web_tmp[1], addra_tmp, addrb_tmp); + + task_ram_col (wea_tmp[2], web_tmp[2], dib_tmp[23:16], dipb_tmp[2], mem[addrb_tmp[14:5]][16 +: 8], memp[addrb_tmp[14:5]][2:2]); + if (seq == 2'b00) + chk_for_col_msg (wea_tmp[2], web_tmp[2], addra_tmp, addrb_tmp); + + task_ram_col (wea_tmp[3], web_tmp[3], dib_tmp[31:24], dipb_tmp[3], mem[addrb_tmp[14:5]][24 +: 8], memp[addrb_tmp[14:5]][3:3]); + if (seq == 2'b00) + chk_for_col_msg (wea_tmp[3], web_tmp[3], addra_tmp, addrb_tmp); + + end // if (wb_width <= wa_width) + end // case: 32 + 64 : begin + + task_ram_col (wea_tmp[0], web_tmp[0], dib_tmp[7:0], dipb_tmp[0], mem[addrb_tmp[14:6]][0 +: 8], memp[addrb_tmp[14:6]][0:0]); + if (seq == 2'b00) + chk_for_col_msg (wea_tmp[0], web_tmp[0], addra_tmp, addrb_tmp); + + task_ram_col (wea_tmp[1], web_tmp[1], dib_tmp[15:8], dipb_tmp[1], mem[addrb_tmp[14:6]][8 +: 8], memp[addrb_tmp[14:6]][1:1]); + if (seq == 2'b00) + chk_for_col_msg (wea_tmp[1], web_tmp[1], addra_tmp, addrb_tmp); + + task_ram_col (wea_tmp[2], web_tmp[2], dib_tmp[23:16], dipb_tmp[2], mem[addrb_tmp[14:6]][16 +: 8], memp[addrb_tmp[14:6]][2:2]); + if (seq == 2'b00) + chk_for_col_msg (wea_tmp[2], web_tmp[2], addra_tmp, addrb_tmp); + + task_ram_col (wea_tmp[3], web_tmp[3], dib_tmp[31:24], dipb_tmp[3], mem[addrb_tmp[14:6]][24 +: 8], memp[addrb_tmp[14:6]][3:3]); + if (seq == 2'b00) + chk_for_col_msg (wea_tmp[3], web_tmp[3], addra_tmp, addrb_tmp); + + task_ram_col (wea_tmp[4], web_tmp[4], dib_tmp[39:32], dipb_tmp[4], mem[addrb_tmp[14:6]][32 +: 8], memp[addrb_tmp[14:6]][4:4]); + if (seq == 2'b00) + chk_for_col_msg (wea_tmp[4], web_tmp[4], addra_tmp, addrb_tmp); + + task_ram_col (wea_tmp[5], web_tmp[5], dib_tmp[47:40], dipb_tmp[5], mem[addrb_tmp[14:6]][40 +: 8], memp[addrb_tmp[14:6]][5:5]); + if (seq == 2'b00) + chk_for_col_msg (wea_tmp[5], web_tmp[5], addra_tmp, addrb_tmp); + + task_ram_col (wea_tmp[6], web_tmp[6], dib_tmp[55:48], dipb_tmp[6], mem[addrb_tmp[14:6]][48 +: 8], memp[addrb_tmp[14:6]][6:6]); + if (seq == 2'b00) + chk_for_col_msg (wea_tmp[6], web_tmp[6], addra_tmp, addrb_tmp); + + task_ram_col (wea_tmp[7], web_tmp[7], dib_tmp[63:56], dipb_tmp[7], mem[addrb_tmp[14:6]][56 +: 8], memp[addrb_tmp[14:6]][7:7]); + if (seq == 2'b00) + chk_for_col_msg (wea_tmp[7], web_tmp[7], addra_tmp, addrb_tmp); + + end // case: 64 + + endcase // case(wb_width) + + end + + endtask // task_col_wr_ram_b + + + task task_wr_ram_a; + + input [7:0] wea_tmp; + input [63:0] dia_tmp; + input [7:0] dipa_tmp; + input [15:0] addra_tmp; + + begin + + case (wa_width) + + 1, 2, 4 : begin + + if (wa_width >= width) + task_ram (wea_tmp[0], dia_tmp[wa_width-1:0], 1'b0, mem[addra_tmp[14:addra_lbit_124]], junk1); + else + task_ram (wea_tmp[0], dia_tmp[wa_width-1:0], 1'b0, mem[addra_tmp[14:addra_bit_124+1]][(addra_tmp[addra_bit_124:addra_lbit_124] * wa_width) +: wa_width], junk1); + + end + 8 : begin + + if (wa_width >= width) + task_ram (wea_tmp[0], dia_tmp[7:0], dipa_tmp[0], mem[addra_tmp[14:3]], memp[addra_tmp[14:3]]); + else + task_ram (wea_tmp[0], dia_tmp[7:0], dipa_tmp[0], mem[addra_tmp[14:addra_bit_8+1]][(addra_tmp[addra_bit_8:3] * 8) +: 8], memp[addra_tmp[14:addra_bit_8+1]][(addra_tmp[addra_bit_8:3] * 1) +: 1]); + + end + 16 : begin + + if (wa_width >= width) begin + task_ram (wea_tmp[0], dia_tmp[7:0], dipa_tmp[0], mem[addra_tmp[14:4]][0 +: 8], memp[addra_tmp[14:4]][0:0]); + task_ram (wea_tmp[1], dia_tmp[15:8], dipa_tmp[1], mem[addra_tmp[14:4]][8 +: 8], memp[addra_tmp[14:4]][1:1]); + end + else begin + task_ram (wea_tmp[0], dia_tmp[7:0], dipa_tmp[0], mem[addra_tmp[14:addra_bit_16+1]][(addra_tmp[addra_bit_16:4] * 16) +: 8], memp[addra_tmp[14:addra_bit_16+1]][(addra_tmp[addra_bit_16:4] * 2) +: 1]); + task_ram (wea_tmp[1], dia_tmp[15:8], dipa_tmp[1], mem[addra_tmp[14:addra_bit_16+1]][((addra_tmp[addra_bit_16:4] * 16) + 8) +: 8], memp[addra_tmp[14:addra_bit_16+1]][((addra_tmp[addra_bit_16:4] * 2) + 1) +: 1]); + end // else: !if(wa_width >= wb_width) + + end // case: 16 + 32 : begin + + task_ram (wea_tmp[0], dia_tmp[7:0], dipa_tmp[0], mem[addra_tmp[14:5]][0 +: 8], memp[addra_tmp[14:5]][0:0]); + task_ram (wea_tmp[1], dia_tmp[15:8], dipa_tmp[1], mem[addra_tmp[14:5]][8 +: 8], memp[addra_tmp[14:5]][1:1]); + task_ram (wea_tmp[2], dia_tmp[23:16], dipa_tmp[2], mem[addra_tmp[14:5]][16 +: 8], memp[addra_tmp[14:5]][2:2]); + task_ram (wea_tmp[3], dia_tmp[31:24], dipa_tmp[3], mem[addra_tmp[14:5]][24 +: 8], memp[addra_tmp[14:5]][3:3]); + + end // case: 32 + 64 : begin // only valid with ECC single bit correction for 64 bits + + if (syndrome !== 0 && syndrome[7] === 1 && EN_ECC_SCRUB == "TRUE") begin // if ecc corrected + task_ram (1'b1, dia_tmp[7:0], dipa_tmp[0], mem[addra_tmp[14:6]][0 +: 8], memp[addra_tmp[14:6]][0:0]); + task_ram (1'b1, dia_tmp[15:8], dipa_tmp[1], mem[addra_tmp[14:6]][8 +: 8], memp[addra_tmp[14:6]][1:1]); + task_ram (1'b1, dia_tmp[23:16], dipa_tmp[2], mem[addra_tmp[14:6]][16 +: 8], memp[addra_tmp[14:6]][2:2]); + task_ram (1'b1, dia_tmp[31:24], dipa_tmp[3], mem[addra_tmp[14:6]][24 +: 8], memp[addra_tmp[14:6]][3:3]); + task_ram (1'b1, dia_tmp[39:32], dipa_tmp[4], mem[addra_tmp[14:6]][32 +: 8], memp[addra_tmp[14:6]][4:4]); + task_ram (1'b1, dia_tmp[47:40], dipa_tmp[5], mem[addra_tmp[14:6]][40 +: 8], memp[addra_tmp[14:6]][5:5]); + task_ram (1'b1, dia_tmp[55:48], dipa_tmp[6], mem[addra_tmp[14:6]][48 +: 8], memp[addra_tmp[14:6]][6:6]); + task_ram (1'b1, dia_tmp[63:56], dipa_tmp[7], mem[addra_tmp[14:6]][56 +: 8], memp[addra_tmp[14:6]][7:7]); + end + + end // case: 64 + endcase // case(wa_width) + end + + endtask // task_wr_ram_a + + + task task_wr_ram_b; + + input [7:0] web_tmp; + input [63:0] dib_tmp; + input [7:0] dipb_tmp; + input [15:0] addrb_tmp; + + begin + + case (wb_width) + + 1, 2, 4 : begin + + if (wb_width >= width) + task_ram (web_tmp[0], dib_tmp[wb_width-1:0], 1'b0, mem[addrb_tmp[14:addrb_lbit_124]], junk1); + else + task_ram (web_tmp[0], dib_tmp[wb_width-1:0], 1'b0, mem[addrb_tmp[14:addrb_bit_124+1]][(addrb_tmp[addrb_bit_124:addrb_lbit_124] * wb_width) +: wb_width], junk1); + end + 8 : begin + + if (wb_width >= width) + task_ram (web_tmp[0], dib_tmp[7:0], dipb_tmp[0], mem[addrb_tmp[14:3]], memp[addrb_tmp[14:3]]); + else + task_ram (web_tmp[0], dib_tmp[7:0], dipb_tmp[0], mem[addrb_tmp[14:addrb_bit_8+1]][(addrb_tmp[addrb_bit_8:3] * 8) +: 8], memp[addrb_tmp[14:addrb_bit_8+1]][(addrb_tmp[addrb_bit_8:3] * 1) +: 1]); + + end + 16 : begin + + if (wb_width >= width) begin + task_ram (web_tmp[0], dib_tmp[7:0], dipb_tmp[0], mem[addrb_tmp[14:4]][0 +: 8], memp[addrb_tmp[14:4]][0:0]); + task_ram (web_tmp[1], dib_tmp[15:8], dipb_tmp[1], mem[addrb_tmp[14:4]][8 +: 8], memp[addrb_tmp[14:4]][1:1]); + end + else begin + task_ram (web_tmp[0], dib_tmp[7:0], dipb_tmp[0], mem[addrb_tmp[14:addrb_bit_16+1]][(addrb_tmp[addrb_bit_16:4] * 16) +: 8], memp[addrb_tmp[14:addrb_bit_16+1]][(addrb_tmp[addrb_bit_16:4] * 2) +: 1]); + task_ram (web_tmp[1], dib_tmp[15:8], dipb_tmp[1], mem[addrb_tmp[14:addrb_bit_16+1]][((addrb_tmp[addrb_bit_16:4] * 16) + 8) +: 8], memp[addrb_tmp[14:addrb_bit_16+1]][((addrb_tmp[addrb_bit_16:4] * 2) + 1) +: 1]); + end + + end // case: 16 + 32 : begin + + task_ram (web_tmp[0], dib_tmp[7:0], dipb_tmp[0], mem[addrb_tmp[14:5]][0 +: 8], memp[addrb_tmp[14:5]][0:0]); + task_ram (web_tmp[1], dib_tmp[15:8], dipb_tmp[1], mem[addrb_tmp[14:5]][8 +: 8], memp[addrb_tmp[14:5]][1:1]); + task_ram (web_tmp[2], dib_tmp[23:16], dipb_tmp[2], mem[addrb_tmp[14:5]][16 +: 8], memp[addrb_tmp[14:5]][2:2]); + task_ram (web_tmp[3], dib_tmp[31:24], dipb_tmp[3], mem[addrb_tmp[14:5]][24 +: 8], memp[addrb_tmp[14:5]][3:3]); + + end // case: 32 + 64 : begin // only valid with ECC single bit correction for 64 bits + + task_ram (web_tmp[0], dib_tmp[7:0], dipb_tmp[0], mem[addrb_tmp[14:6]][0 +: 8], memp[addrb_tmp[14:6]][0:0]); + task_ram (web_tmp[1], dib_tmp[15:8], dipb_tmp[1], mem[addrb_tmp[14:6]][8 +: 8], memp[addrb_tmp[14:6]][1:1]); + task_ram (web_tmp[2], dib_tmp[23:16], dipb_tmp[2], mem[addrb_tmp[14:6]][16 +: 8], memp[addrb_tmp[14:6]][2:2]); + task_ram (web_tmp[3], dib_tmp[31:24], dipb_tmp[3], mem[addrb_tmp[14:6]][24 +: 8], memp[addrb_tmp[14:6]][3:3]); + task_ram (web_tmp[4], dib_tmp[39:32], dipb_tmp[4], mem[addrb_tmp[14:6]][32 +: 8], memp[addrb_tmp[14:6]][4:4]); + task_ram (web_tmp[5], dib_tmp[47:40], dipb_tmp[5], mem[addrb_tmp[14:6]][40 +: 8], memp[addrb_tmp[14:6]][5:5]); + task_ram (web_tmp[6], dib_tmp[55:48], dipb_tmp[6], mem[addrb_tmp[14:6]][48 +: 8], memp[addrb_tmp[14:6]][6:6]); + task_ram (web_tmp[7], dib_tmp[63:56], dipb_tmp[7], mem[addrb_tmp[14:6]][56 +: 8], memp[addrb_tmp[14:6]][7:7]); + + end // case: 64 + endcase // case(wb_width) + end + + endtask // task_wr_ram_b + + + task task_col_rd_ram_a; + + input [1:0] seq; // 1 is bypass + input [7:0] web_tmp; + input [7:0] wea_tmp; + input [15:0] addra_tmp; + inout [63:0] doa_tmp; + inout [7:0] dopa_tmp; + reg [63:0] doa_ltmp; + reg [7:0] dopa_ltmp; + + begin + + doa_ltmp= 64'b0; + dopa_ltmp= 8'b0; + + case (ra_width) + 1, 2, 4 : begin + + if ((web_tmp[0] === 1'b1 && wea_tmp[0] === 1'b1) || (seq == 2'b01 && web_tmp[0] === 1'b1 && wea_tmp[0] === 1'b0 && viol_type == 2'b10) || (seq == 2'b01 && wr_mode_a != 2'b01 && wr_mode_b != 2'b01) || (seq == 2'b01 && wr_mode_a == 2'b01 && wr_mode_b != 2'b01 && web_tmp[0] === 1'b1) || (seq == 2'b11 && wr_mode_a == 2'b00 && web_tmp[0] !== 1'b1)) begin + if (ra_width >= width) + doa_ltmp = mem[addra_tmp[14:r_addra_lbit_124]]; + else + doa_ltmp = mem[addra_tmp[14:r_addra_bit_124+1]][(addra_tmp[r_addra_bit_124:r_addra_lbit_124] * ra_width) +: ra_width]; + task_x_buf (wr_mode_a, 3, 0, 0, doa_ltmp, doa_tmp, dopa_ltmp, dopa_tmp); + end + end // case: 1, 2, 4 + 8 : begin + + if ((web_tmp[0] === 1'b1 && wea_tmp[0] === 1'b1) || (seq == 2'b01 && web_tmp[0] === 1'b1 && wea_tmp[0] === 1'b0 && viol_type == 2'b10) || (seq == 2'b01 && wr_mode_a != 2'b01 && wr_mode_b != 2'b01) || (seq == 2'b01 && wr_mode_a == 2'b01 && wr_mode_b != 2'b01 && web_tmp[0] === 1'b1) || (seq == 2'b11 && wr_mode_a == 2'b00 && web_tmp[0] !== 1'b1)) begin + if (ra_width >= width) begin + doa_ltmp = mem[addra_tmp[14:3]]; + dopa_ltmp = memp[addra_tmp[14:3]]; + end + else begin + doa_ltmp = mem[addra_tmp[14:r_addra_bit_8+1]][(addra_tmp[r_addra_bit_8:3] * 8) +: 8]; + dopa_ltmp = memp[addra_tmp[14:r_addra_bit_8+1]][(addra_tmp[r_addra_bit_8:3] * 1) +: 1]; + end + + task_x_buf (wr_mode_a, 7, 0, 0, doa_ltmp, doa_tmp, dopa_ltmp, dopa_tmp); + + end + end // case: 8 + 16 : begin + + if ((web_tmp[0] === 1'b1 && wea_tmp[0] === 1'b1) || (seq == 2'b01 && web_tmp[0] === 1'b1 && wea_tmp[0] === 1'b0 && viol_type == 2'b10) || (seq == 2'b01 && wr_mode_a != 2'b01 && wr_mode_b != 2'b01) || (seq == 2'b01 && wr_mode_a == 2'b01 && wr_mode_b != 2'b01 && web_tmp[0] === 1'b1) || (seq == 2'b11 && wr_mode_a == 2'b00 && web_tmp[0] !== 1'b1)) begin + if (ra_width >= width) begin + doa_ltmp[7:0] = mem[addra_tmp[14:4]][7:0]; + dopa_ltmp[0:0] = memp[addra_tmp[14:4]][0:0]; + end + else begin + doa_ltmp[7:0] = mem[addra_tmp[14:r_addra_bit_16+1]][(addra_tmp[r_addra_bit_16:4] * 16) +: 8]; + dopa_ltmp[0:0] = memp[addra_tmp[14:r_addra_bit_16+1]][(addra_tmp[r_addra_bit_16:4] * 2) +: 1]; + end + task_x_buf (wr_mode_a, 7, 0, 0, doa_ltmp, doa_tmp, dopa_ltmp, dopa_tmp); + end + + if ((web_tmp[1] === 1'b1 && wea_tmp[1] === 1'b1) || (seq == 2'b01 && web_tmp[1] === 1'b1 && wea_tmp[1] === 1'b0 && viol_type == 2'b10) || (seq == 2'b01 && wr_mode_a != 2'b01 && wr_mode_b != 2'b01) || (seq == 2'b01 && wr_mode_a == 2'b01 && wr_mode_b != 2'b01 && web_tmp[1] === 1'b1) || (seq == 2'b11 && wr_mode_a == 2'b00 && web_tmp[1] !== 1'b1)) begin + if (ra_width >= width) begin + doa_ltmp[15:8] = mem[addra_tmp[14:4]][15:8]; + dopa_ltmp[1:1] = memp[addra_tmp[14:4]][1:1]; + end + else begin + doa_ltmp[15:8] = mem[addra_tmp[14:r_addra_bit_16+1]][((addra_tmp[r_addra_bit_16:4] * 16) + 8) +: 8]; + dopa_ltmp[1:1] = memp[addra_tmp[14:r_addra_bit_16+1]][((addra_tmp[r_addra_bit_16:4] * 2) + 1) +: 1]; + end + task_x_buf (wr_mode_a, 15, 8, 1, doa_ltmp, doa_tmp, dopa_ltmp, dopa_tmp); + end + + end + 32 : begin + if (ra_width >= width) begin + + if ((web_tmp[0] === 1'b1 && wea_tmp[0] === 1'b1) || (seq == 2'b01 && web_tmp[0] === 1'b1 && wea_tmp[0] === 1'b0 && viol_type == 2'b10) || (seq == 2'b01 && wr_mode_a != 2'b01 && wr_mode_b != 2'b01) || (seq == 2'b01 && wr_mode_a == 2'b01 && wr_mode_b != 2'b01 && web_tmp[0] === 1'b1) || (seq == 2'b11 && wr_mode_a == 2'b00 && web_tmp[0] !== 1'b1)) begin + doa_ltmp[7:0] = mem[addra_tmp[14:5]][7:0]; + dopa_ltmp[0:0] = memp[addra_tmp[14:5]][0:0]; + task_x_buf (wr_mode_a, 7, 0, 0, doa_ltmp, doa_tmp, dopa_ltmp, dopa_tmp); + end + + if ((web_tmp[1] === 1'b1 && wea_tmp[1] === 1'b1) || (seq == 2'b01 && web_tmp[1] === 1'b1 && wea_tmp[1] === 1'b0 && viol_type == 2'b10) || (seq == 2'b01 && wr_mode_a != 2'b01 && wr_mode_b != 2'b01) || (seq == 2'b01 && wr_mode_a == 2'b01 && wr_mode_b != 2'b01 && web_tmp[1] === 1'b1) || (seq == 2'b11 && wr_mode_a == 2'b00 && web_tmp[1] !== 1'b1)) begin + doa_ltmp[15:8] = mem[addra_tmp[14:5]][15:8]; + dopa_ltmp[1:1] = memp[addra_tmp[14:5]][1:1]; + task_x_buf (wr_mode_a, 15, 8, 1, doa_ltmp, doa_tmp, dopa_ltmp, dopa_tmp); + end + + if ((web_tmp[2] === 1'b1 && wea_tmp[2] === 1'b1) || (seq == 2'b01 && web_tmp[2] === 1'b1 && wea_tmp[2] === 1'b0 && viol_type == 2'b10) || (seq == 2'b01 && wr_mode_a != 2'b01 && wr_mode_b != 2'b01) || (seq == 2'b01 && wr_mode_a == 2'b01 && wr_mode_b != 2'b01 && web_tmp[2] === 1'b1) || (seq == 2'b11 && wr_mode_a == 2'b00 && web_tmp[2] !== 1'b1)) begin + doa_ltmp[23:16] = mem[addra_tmp[14:5]][23:16]; + dopa_ltmp[2:2] = memp[addra_tmp[14:5]][2:2]; + task_x_buf (wr_mode_a, 23, 16, 2, doa_ltmp, doa_tmp, dopa_ltmp, dopa_tmp); + end + + if ((web_tmp[3] === 1'b1 && wea_tmp[3] === 1'b1) || (seq == 2'b01 && web_tmp[3] === 1'b1 && wea_tmp[3] === 1'b0 && viol_type == 2'b10) || (seq == 2'b01 && wr_mode_a != 2'b01 && wr_mode_b != 2'b01) || (seq == 2'b01 && wr_mode_a == 2'b01 && wr_mode_b != 2'b01 && web_tmp[3] === 1'b1) || (seq == 2'b11 && wr_mode_a == 2'b00 && web_tmp[3] !== 1'b1)) begin + doa_ltmp[31:24] = mem[addra_tmp[14:5]][31:24]; + dopa_ltmp[3:3] = memp[addra_tmp[14:5]][3:3]; + task_x_buf (wr_mode_a, 31, 24, 3, doa_ltmp, doa_tmp, dopa_ltmp, dopa_tmp); + end + + end // if (ra_width >= width) + end + 64 : begin + + if ((web_tmp[0] === 1'b1 && wea_tmp[0] === 1'b1) || (seq == 2'b01 && web_tmp[0] === 1'b1 && wea_tmp[0] === 1'b0 && viol_type == 2'b10) || (seq == 2'b01 && wr_mode_a != 2'b01 && wr_mode_b != 2'b01) || (seq == 2'b01 && wr_mode_a == 2'b01 && wr_mode_b != 2'b01 && web_tmp[0] === 1'b1) || (seq == 2'b11 && wr_mode_a == 2'b00 && web_tmp[0] !== 1'b1)) begin + doa_ltmp[7:0] = mem[addra_tmp[14:6]][7:0]; + dopa_ltmp[0:0] = memp[addra_tmp[14:6]][0:0]; + task_x_buf (wr_mode_a, 7, 0, 0, doa_ltmp, doa_tmp, dopa_ltmp, dopa_tmp); + end + + if ((web_tmp[1] === 1'b1 && wea_tmp[1] === 1'b1) || (seq == 2'b01 && web_tmp[1] === 1'b1 && wea_tmp[1] === 1'b0 && viol_type == 2'b10) || (seq == 2'b01 && wr_mode_a != 2'b01 && wr_mode_b != 2'b01) || (seq == 2'b01 && wr_mode_a == 2'b01 && wr_mode_b != 2'b01 && web_tmp[1] === 1'b1) || (seq == 2'b11 && wr_mode_a == 2'b00 && web_tmp[1] !== 1'b1)) begin + doa_ltmp[15:8] = mem[addra_tmp[14:6]][15:8]; + dopa_ltmp[1:1] = memp[addra_tmp[14:6]][1:1]; + task_x_buf (wr_mode_a, 15, 8, 1, doa_ltmp, doa_tmp, dopa_ltmp, dopa_tmp); + end + + if ((web_tmp[2] === 1'b1 && wea_tmp[2] === 1'b1) || (seq == 2'b01 && web_tmp[2] === 1'b1 && wea_tmp[2] === 1'b0 && viol_type == 2'b10) || (seq == 2'b01 && wr_mode_a != 2'b01 && wr_mode_b != 2'b01) || (seq == 2'b01 && wr_mode_a == 2'b01 && wr_mode_b != 2'b01 && web_tmp[2] === 1'b1) || (seq == 2'b11 && wr_mode_a == 2'b00 && web_tmp[2] !== 1'b1)) begin + doa_ltmp[23:16] = mem[addra_tmp[14:6]][23:16]; + dopa_ltmp[2:2] = memp[addra_tmp[14:6]][2:2]; + task_x_buf (wr_mode_a, 23, 16, 2, doa_ltmp, doa_tmp, dopa_ltmp, dopa_tmp); + end + + if ((web_tmp[3] === 1'b1 && wea_tmp[3] === 1'b1) || (seq == 2'b01 && web_tmp[3] === 1'b1 && wea_tmp[3] === 1'b0 && viol_type == 2'b10) || (seq == 2'b01 && wr_mode_a != 2'b01 && wr_mode_b != 2'b01) || (seq == 2'b01 && wr_mode_a == 2'b01 && wr_mode_b != 2'b01 && web_tmp[3] === 1'b1) || (seq == 2'b11 && wr_mode_a == 2'b00 && web_tmp[3] !== 1'b1)) begin + doa_ltmp[31:24] = mem[addra_tmp[14:6]][31:24]; + dopa_ltmp[3:3] = memp[addra_tmp[14:6]][3:3]; + task_x_buf (wr_mode_a, 31, 24, 3, doa_ltmp, doa_tmp, dopa_ltmp, dopa_tmp); + end + + if ((web_tmp[4] === 1'b1 && wea_tmp[4] === 1'b1) || (seq == 2'b01 && web_tmp[4] === 1'b1 && wea_tmp[4] === 1'b0 && viol_type == 2'b10) || (seq == 2'b01 && wr_mode_a != 2'b01 && wr_mode_b != 2'b01) || (seq == 2'b01 && wr_mode_a == 2'b01 && wr_mode_b != 2'b01 && web_tmp[4] === 1'b1) || (seq == 2'b11 && wr_mode_a == 2'b00 && web_tmp[4] !== 1'b1)) begin + doa_ltmp[39:32] = mem[addra_tmp[14:6]][39:32]; + dopa_ltmp[4:4] = memp[addra_tmp[14:6]][4:4]; + task_x_buf (wr_mode_a, 39, 32, 4, doa_ltmp, doa_tmp, dopa_ltmp, dopa_tmp); + end + + if ((web_tmp[5] === 1'b1 && wea_tmp[5] === 1'b1) || (seq == 2'b01 && web_tmp[5] === 1'b1 && wea_tmp[5] === 1'b0 && viol_type == 2'b10) || (seq == 2'b01 && wr_mode_a != 2'b01 && wr_mode_b != 2'b01) || (seq == 2'b01 && wr_mode_a == 2'b01 && wr_mode_b != 2'b01 && web_tmp[5] === 1'b1) || (seq == 2'b11 && wr_mode_a == 2'b00 && web_tmp[5] !== 1'b1)) begin + doa_ltmp[47:40] = mem[addra_tmp[14:6]][47:40]; + dopa_ltmp[5:5] = memp[addra_tmp[14:6]][5:5]; + task_x_buf (wr_mode_a, 47, 40, 5, doa_ltmp, doa_tmp, dopa_ltmp, dopa_tmp); + end + + if ((web_tmp[6] === 1'b1 && wea_tmp[6] === 1'b1) || (seq == 2'b01 && web_tmp[6] === 1'b1 && wea_tmp[6] === 1'b0 && viol_type == 2'b10) || (seq == 2'b01 && wr_mode_a != 2'b01 && wr_mode_b != 2'b01) || (seq == 2'b01 && wr_mode_a == 2'b01 && wr_mode_b != 2'b01 && web_tmp[6] === 1'b1) || (seq == 2'b11 && wr_mode_a == 2'b00 && web_tmp[6] !== 1'b1)) begin + doa_ltmp[55:48] = mem[addra_tmp[14:6]][55:48]; + dopa_ltmp[6:6] = memp[addra_tmp[14:6]][6:6]; + task_x_buf (wr_mode_a, 55, 48, 6, doa_ltmp, doa_tmp, dopa_ltmp, dopa_tmp); + end + + if ((web_tmp[7] === 1'b1 && wea_tmp[7] === 1'b1) || (seq == 2'b01 && web_tmp[7] === 1'b1 && wea_tmp[7] === 1'b0 && viol_type == 2'b10) || (seq == 2'b01 && wr_mode_a != 2'b01 && wr_mode_b != 2'b01) || (seq == 2'b01 && wr_mode_a == 2'b01 && wr_mode_b != 2'b01 && web_tmp[7] === 1'b1) || (seq == 2'b11 && wr_mode_a == 2'b00 && web_tmp[7] !== 1'b1)) begin + doa_ltmp[63:56] = mem[addra_tmp[14:6]][63:56]; + dopa_ltmp[7:7] = memp[addra_tmp[14:6]][7:7]; + task_x_buf (wr_mode_a, 63, 56, 7, doa_ltmp, doa_tmp, dopa_ltmp, dopa_tmp); + end + + end + endcase // case(ra_width) + end + endtask // task_col_rd_ram_a + + + task task_col_rd_ram_b; + + input [1:0] seq; // 1 is bypass + input [7:0] wea_tmp; + input [7:0] web_tmp; + input [15:0] addrb_tmp; + inout [63:0] dob_tmp; + inout [7:0] dopb_tmp; + reg [63:0] dob_ltmp; + reg [7:0] dopb_ltmp; + + begin + + dob_ltmp= 64'b0; + dopb_ltmp= 8'b0; + + case (rb_width) + 1, 2, 4 : begin + + if ((web_tmp[0] === 1'b1 && wea_tmp[0] === 1'b1) || (seq == 2'b01 && wea_tmp[0] === 1'b1 && web_tmp[0] === 1'b0 && viol_type == 2'b11) || (seq == 2'b01 && wr_mode_b != 2'b01 && wr_mode_a != 2'b01) || (seq == 2'b01 && wr_mode_b == 2'b01 && wr_mode_a != 2'b01 && wea_tmp[0] === 1'b1) || (seq == 2'b11 && wr_mode_b == 2'b00 && wea_tmp[0] !== 1'b1)) begin + if (rb_width >= width) + dob_ltmp = mem[addrb_tmp[14:r_addrb_lbit_124]]; + else + dob_ltmp = mem[addrb_tmp[14:r_addrb_bit_124+1]][(addrb_tmp[r_addrb_bit_124:r_addrb_lbit_124] * rb_width) +: rb_width]; + + task_x_buf (wr_mode_b, 3, 0, 0, dob_ltmp, dob_tmp, dopb_ltmp, dopb_tmp); + + end + end // case: 1, 2, 4 + 8 : begin + + if ((web_tmp[0] === 1'b1 && wea_tmp[0] === 1'b1) || (seq == 2'b01 && wea_tmp[0] === 1'b1 && web_tmp[0] === 1'b0 && viol_type == 2'b11) || (seq == 2'b01 && wr_mode_b != 2'b01 && wr_mode_a != 2'b01) || (seq == 2'b01 && wr_mode_b == 2'b01 && wr_mode_a != 2'b01 && wea_tmp[0] === 1'b1) || (seq == 2'b11 && wr_mode_b == 2'b00 && wea_tmp[0] !== 1'b1)) begin + + if (rb_width >= width) begin + dob_ltmp = mem[addrb_tmp[14:3]]; + dopb_ltmp = memp[addrb_tmp[14:3]]; + end + else begin + dob_ltmp = mem[addrb_tmp[14:r_addrb_bit_8+1]][(addrb_tmp[r_addrb_bit_8:3] * 8) +: 8]; + dopb_ltmp = memp[addrb_tmp[14:r_addrb_bit_8+1]][(addrb_tmp[r_addrb_bit_8:3] * 1) +: 1]; + end + + task_x_buf (wr_mode_b, 7, 0, 0, dob_ltmp, dob_tmp, dopb_ltmp, dopb_tmp); + + end + end // case: 8 + 16 : begin + + if ((web_tmp[0] === 1'b1 && wea_tmp[0] === 1'b1) || (seq == 2'b01 && wea_tmp[0] === 1'b1 && web_tmp[0] === 1'b0 && viol_type == 2'b11) || (seq == 2'b01 && wr_mode_b != 2'b01 && wr_mode_a != 2'b01) || (seq == 2'b01 && wr_mode_b == 2'b01 && wr_mode_a != 2'b01 && wea_tmp[0] === 1'b1) || (seq == 2'b11 && wr_mode_b == 2'b00 && wea_tmp[0] !== 1'b1)) begin + if (rb_width >= width) begin + dob_ltmp[7:0] = mem[addrb_tmp[14:4]][7:0]; + dopb_ltmp[0:0] = memp[addrb_tmp[14:4]][0:0]; + end + else begin + dob_ltmp[7:0] = mem[addrb_tmp[14:r_addrb_bit_16+1]][(addrb_tmp[r_addrb_bit_16:4] * 16) +: 8]; + dopb_ltmp[0:0] = memp[addrb_tmp[14:r_addrb_bit_16+1]][(addrb_tmp[r_addrb_bit_16:4] * 2) +: 1]; + end + task_x_buf (wr_mode_b, 7, 0, 0, dob_ltmp, dob_tmp, dopb_ltmp, dopb_tmp); + end + + + if ((web_tmp[1] === 1'b1 && wea_tmp[1] === 1'b1) || (seq == 2'b01 && wea_tmp[1] === 1'b1 && web_tmp[1] === 1'b0 && viol_type == 2'b11) || (seq == 2'b01 && wr_mode_b != 2'b01 && wr_mode_a != 2'b01) || (seq == 2'b01 && wr_mode_b == 2'b01 && wr_mode_a != 2'b01 && wea_tmp[1] === 1'b1) || (seq == 2'b11 && wr_mode_b == 2'b00 && wea_tmp[1] !== 1'b1)) begin + + if (rb_width >= width) begin + dob_ltmp[15:8] = mem[addrb_tmp[14:4]][15:8]; + dopb_ltmp[1:1] = memp[addrb_tmp[14:4]][1:1]; + end + else begin + dob_ltmp[15:8] = mem[addrb_tmp[14:r_addrb_bit_16+1]][((addrb_tmp[r_addrb_bit_16:4] * 16) + 8) +: 8]; + dopb_ltmp[1:1] = memp[addrb_tmp[14:r_addrb_bit_16+1]][((addrb_tmp[r_addrb_bit_16:4] * 2) + 1) +: 1]; + end + task_x_buf (wr_mode_b, 15, 8, 1, dob_ltmp, dob_tmp, dopb_ltmp, dopb_tmp); + end + + end + 32 : begin + if (rb_width >= width) begin + + if ((web_tmp[0] === 1'b1 && wea_tmp[0] === 1'b1) || (seq == 2'b01 && wea_tmp[0] === 1'b1 && web_tmp[0] === 1'b0 && viol_type == 2'b11) || (seq == 2'b01 && wr_mode_b != 2'b01 && wr_mode_a != 2'b01) || (seq == 2'b01 && wr_mode_b == 2'b01 && wr_mode_a != 2'b01 && wea_tmp[0] === 1'b1) || (seq == 2'b11 && wr_mode_b == 2'b00 && wea_tmp[0] !== 1'b1)) begin + dob_ltmp[7:0] = mem[addrb_tmp[14:5]][7:0]; + dopb_ltmp[0:0] = memp[addrb_tmp[14:5]][0:0]; + task_x_buf (wr_mode_b, 7, 0, 0, dob_ltmp, dob_tmp, dopb_ltmp, dopb_tmp); + end + + if ((web_tmp[1] === 1'b1 && wea_tmp[1] === 1'b1) || (seq == 2'b01 && wea_tmp[1] === 1'b1 && web_tmp[1] === 1'b0 && viol_type == 2'b11) || (seq == 2'b01 && wr_mode_b != 2'b01 && wr_mode_a != 2'b01) || (seq == 2'b01 && wr_mode_b == 2'b01 && wr_mode_a != 2'b01 && wea_tmp[1] === 1'b1) || (seq == 2'b11 && wr_mode_b == 2'b00 && wea_tmp[1] !== 1'b1)) begin + dob_ltmp[15:8] = mem[addrb_tmp[14:5]][15:8]; + dopb_ltmp[1:1] = memp[addrb_tmp[14:5]][1:1]; + task_x_buf (wr_mode_b, 15, 8, 1, dob_ltmp, dob_tmp, dopb_ltmp, dopb_tmp); + end + + if ((web_tmp[2] === 1'b1 && wea_tmp[2] === 1'b1) || (seq == 2'b01 && wea_tmp[2] === 1'b1 && web_tmp[2] === 1'b0 && viol_type == 2'b11) || (seq == 2'b01 && wr_mode_b != 2'b01 && wr_mode_a != 2'b01) || (seq == 2'b01 && wr_mode_b == 2'b01 && wr_mode_a != 2'b01 && wea_tmp[2] === 1'b1) || (seq == 2'b11 && wr_mode_b == 2'b00 && wea_tmp[2] !== 1'b1)) begin + dob_ltmp[23:16] = mem[addrb_tmp[14:5]][23:16]; + dopb_ltmp[2:2] = memp[addrb_tmp[14:5]][2:2]; + task_x_buf (wr_mode_b, 23, 16, 2, dob_ltmp, dob_tmp, dopb_ltmp, dopb_tmp); + end + + if ((web_tmp[3] === 1'b1 && wea_tmp[3] === 1'b1) || (seq == 2'b01 && wea_tmp[3] === 1'b1 && web_tmp[3] === 1'b0 && viol_type == 2'b11) || (seq == 2'b01 && wr_mode_b != 2'b01 && wr_mode_a != 2'b01) || (seq == 2'b01 && wr_mode_b == 2'b01 && wr_mode_a != 2'b01 && wea_tmp[3] === 1'b1) || (seq == 2'b11 && wr_mode_b == 2'b00 && wea_tmp[3] !== 1'b1)) begin + dob_ltmp[31:24] = mem[addrb_tmp[14:5]][31:24]; + dopb_ltmp[3:3] = memp[addrb_tmp[14:5]][3:3]; + task_x_buf (wr_mode_b, 31, 24, 3, dob_ltmp, dob_tmp, dopb_ltmp, dopb_tmp); + end + + end // if (rb_width >= width) + end + 64 : begin + + if ((web_tmp[0] === 1'b1 && wea_tmp[0] === 1'b1) || (seq == 2'b01 && wea_tmp[0] === 1'b1 && web_tmp[0] === 1'b0 && viol_type == 2'b11) || (seq == 2'b01 && wr_mode_b != 2'b01 && wr_mode_a != 2'b01) || (seq == 2'b01 && wr_mode_b == 2'b01 && wr_mode_a != 2'b01 && wea_tmp[0] === 1'b1) || (seq == 2'b11 && wr_mode_b == 2'b00 && wea_tmp[0] !== 1'b1)) begin + dob_ltmp[7:0] = mem[addrb_tmp[14:6]][7:0]; + dopb_ltmp[0:0] = memp[addrb_tmp[14:6]][0:0]; + task_x_buf (wr_mode_b, 7, 0, 0, dob_ltmp, dob_tmp, dopb_ltmp, dopb_tmp); + end + + if ((web_tmp[1] === 1'b1 && wea_tmp[1] === 1'b1) || (seq == 2'b01 && wea_tmp[1] === 1'b1 && web_tmp[1] === 1'b0 && viol_type == 2'b11) || (seq == 2'b01 && wr_mode_b != 2'b01 && wr_mode_a != 2'b01) || (seq == 2'b01 && wr_mode_b == 2'b01 && wr_mode_a != 2'b01 && wea_tmp[1] === 1'b1) || (seq == 2'b11 && wr_mode_b == 2'b00 && wea_tmp[1] !== 1'b1)) begin + dob_ltmp[15:8] = mem[addrb_tmp[14:6]][15:8]; + dopb_ltmp[1:1] = memp[addrb_tmp[14:6]][1:1]; + task_x_buf (wr_mode_b, 15, 8, 1, dob_ltmp, dob_tmp, dopb_ltmp, dopb_tmp); + end + + if ((web_tmp[2] === 1'b1 && wea_tmp[2] === 1'b1) || (seq == 2'b01 && wea_tmp[2] === 1'b1 && web_tmp[2] === 1'b0 && viol_type == 2'b11) || (seq == 2'b01 && wr_mode_b != 2'b01 && wr_mode_a != 2'b01) || (seq == 2'b01 && wr_mode_b == 2'b01 && wr_mode_a != 2'b01 && wea_tmp[2] === 1'b1) || (seq == 2'b11 && wr_mode_b == 2'b00 && wea_tmp[2] !== 1'b1)) begin + dob_ltmp[23:16] = mem[addrb_tmp[14:6]][23:16]; + dopb_ltmp[2:2] = memp[addrb_tmp[14:6]][2:2]; + task_x_buf (wr_mode_b, 23, 16, 2, dob_ltmp, dob_tmp, dopb_ltmp, dopb_tmp); + end + + if ((web_tmp[3] === 1'b1 && wea_tmp[3] === 1'b1) || (seq == 2'b01 && wea_tmp[3] === 1'b1 && web_tmp[3] === 1'b0 && viol_type == 2'b11) || (seq == 2'b01 && wr_mode_b != 2'b01 && wr_mode_a != 2'b01) || (seq == 2'b01 && wr_mode_b == 2'b01 && wr_mode_a != 2'b01 && wea_tmp[3] === 1'b1) || (seq == 2'b11 && wr_mode_b == 2'b00 && wea_tmp[3] !== 1'b1)) begin + dob_ltmp[31:24] = mem[addrb_tmp[14:6]][31:24]; + dopb_ltmp[3:3] = memp[addrb_tmp[14:6]][3:3]; + task_x_buf (wr_mode_b, 31, 24, 3, dob_ltmp, dob_tmp, dopb_ltmp, dopb_tmp); + end + + if ((web_tmp[4] === 1'b1 && wea_tmp[4] === 1'b1) || (seq == 2'b01 && wea_tmp[4] === 1'b1 && web_tmp[4] === 1'b0 && viol_type == 2'b11) || (seq == 2'b01 && wr_mode_b != 2'b01 && wr_mode_a != 2'b01) || (seq == 2'b01 && wr_mode_b == 2'b01 && wr_mode_a != 2'b01 && wea_tmp[4] === 1'b1) || (seq == 2'b11 && wr_mode_b == 2'b00 && wea_tmp[4] !== 1'b1)) begin + dob_ltmp[39:32] = mem[addrb_tmp[14:6]][39:32]; + dopb_ltmp[4:4] = memp[addrb_tmp[14:6]][4:4]; + task_x_buf (wr_mode_b, 39, 32, 4, dob_ltmp, dob_tmp, dopb_ltmp, dopb_tmp); + end + + if ((web_tmp[5] === 1'b1 && wea_tmp[5] === 1'b1) || (seq == 2'b01 && wea_tmp[5] === 1'b1 && web_tmp[5] === 1'b0 && viol_type == 2'b11) || (seq == 2'b01 && wr_mode_b != 2'b01 && wr_mode_a != 2'b01) || (seq == 2'b01 && wr_mode_b == 2'b01 && wr_mode_a != 2'b01 && wea_tmp[5] === 1'b1) || (seq == 2'b11 && wr_mode_b == 2'b00 && wea_tmp[5] !== 1'b1)) begin + dob_ltmp[47:40] = mem[addrb_tmp[14:6]][47:40]; + dopb_ltmp[5:5] = memp[addrb_tmp[14:6]][5:5]; + task_x_buf (wr_mode_b, 47, 40, 5, dob_ltmp, dob_tmp, dopb_ltmp, dopb_tmp); + end + + if ((web_tmp[6] === 1'b1 && wea_tmp[6] === 1'b1) || (seq == 2'b01 && wea_tmp[6] === 1'b1 && web_tmp[6] === 1'b0 && viol_type == 2'b11) || (seq == 2'b01 && wr_mode_b != 2'b01 && wr_mode_a != 2'b01) || (seq == 2'b01 && wr_mode_b == 2'b01 && wr_mode_a != 2'b01 && wea_tmp[6] === 1'b1) || (seq == 2'b11 && wr_mode_b == 2'b00 && wea_tmp[6] !== 1'b1)) begin + dob_ltmp[55:48] = mem[addrb_tmp[14:6]][55:48]; + dopb_ltmp[6:6] = memp[addrb_tmp[14:6]][6:6]; + task_x_buf (wr_mode_b, 55, 48, 6, dob_ltmp, dob_tmp, dopb_ltmp, dopb_tmp); + end + + if ((web_tmp[7] === 1'b1 && wea_tmp[7] === 1'b1) || (seq == 2'b01 && wea_tmp[7] === 1'b1 && web_tmp[7] === 1'b0 && viol_type == 2'b11) || (seq == 2'b01 && wr_mode_b != 2'b01 && wr_mode_a != 2'b01) || (seq == 2'b01 && wr_mode_b == 2'b01 && wr_mode_a != 2'b01 && wea_tmp[7] === 1'b1) || (seq == 2'b11 && wr_mode_b == 2'b00 && wea_tmp[7] !== 1'b1)) begin + dob_ltmp[63:56] = mem[addrb_tmp[14:6]][63:56]; + dopb_ltmp[7:7] = memp[addrb_tmp[14:6]][7:7]; + task_x_buf (wr_mode_b, 63, 56, 7, dob_ltmp, dob_tmp, dopb_ltmp, dopb_tmp); + end + + end + endcase // case(rb_width) + end + endtask // task_col_rd_ram_b + + + task task_rd_ram_a; + + input [15:0] addra_tmp; + inout [63:0] doa_tmp; + inout [7:0] dopa_tmp; + + begin + + case (ra_width) + 1, 2, 4 : begin + if (ra_width >= width) + doa_tmp = mem[addra_tmp[14:r_addra_lbit_124]]; + + else + doa_tmp = mem[addra_tmp[14:r_addra_bit_124+1]][(addra_tmp[r_addra_bit_124:r_addra_lbit_124] * ra_width) +: ra_width]; + end + 8 : begin + if (ra_width >= width) begin + doa_tmp = mem[addra_tmp[14:3]]; + dopa_tmp = memp[addra_tmp[14:3]]; + end + else begin + doa_tmp = mem[addra_tmp[14:r_addra_bit_8+1]][(addra_tmp[r_addra_bit_8:3] * 8) +: 8]; + dopa_tmp = memp[addra_tmp[14:r_addra_bit_8+1]][(addra_tmp[r_addra_bit_8:3] * 1) +: 1]; + end + end + 16 : begin + if (ra_width >= width) begin + doa_tmp = mem[addra_tmp[14:4]]; + dopa_tmp = memp[addra_tmp[14:4]]; + end + else begin + doa_tmp = mem[addra_tmp[14:r_addra_bit_16+1]][(addra_tmp[r_addra_bit_16:4] * 16) +: 16]; + dopa_tmp = memp[addra_tmp[14:r_addra_bit_16+1]][(addra_tmp[r_addra_bit_16:4] * 2) +: 2]; + end + end + 32 : begin + if (ra_width >= width) begin + doa_tmp = mem[addra_tmp[14:5]]; + dopa_tmp = memp[addra_tmp[14:5]]; + end + end + 64 : begin + if (ra_width >= width) begin + doa_tmp = mem[addra_tmp[14:6]]; + dopa_tmp = memp[addra_tmp[14:6]]; + end + end + endcase // case(ra_width) + + end + endtask // task_rd_ram_a + + + task task_rd_ram_b; + + input [15:0] addrb_tmp; + inout [31:0] dob_tmp; + inout [3:0] dopb_tmp; + + begin + + case (rb_width) + 1, 2, 4 : begin + if (rb_width >= width) + dob_tmp = mem[addrb_tmp[14:r_addrb_lbit_124]]; + else + dob_tmp = mem[addrb_tmp[14:r_addrb_bit_124+1]][(addrb_tmp[r_addrb_bit_124:r_addrb_lbit_124] * rb_width) +: rb_width]; + end + 8 : begin + if (rb_width >= width) begin + dob_tmp = mem[addrb_tmp[14:3]]; + dopb_tmp = memp[addrb_tmp[14:3]]; + end + else begin + dob_tmp = mem[addrb_tmp[14:r_addrb_bit_8+1]][(addrb_tmp[r_addrb_bit_8:3] * 8) +: 8]; + dopb_tmp = memp[addrb_tmp[14:r_addrb_bit_8+1]][(addrb_tmp[r_addrb_bit_8:3] * 1) +: 1]; + end + end + 16 : begin + if (rb_width >= width) begin + dob_tmp = mem[addrb_tmp[14:4]]; + dopb_tmp = memp[addrb_tmp[14:4]]; + end + else begin + dob_tmp = mem[addrb_tmp[14:r_addrb_bit_16+1]][(addrb_tmp[r_addrb_bit_16:4] * 16) +: 16]; + dopb_tmp = memp[addrb_tmp[14:r_addrb_bit_16+1]][(addrb_tmp[r_addrb_bit_16:4] * 2) +: 2]; + end + end + 32 : begin + dob_tmp = mem[addrb_tmp[14:5]]; + dopb_tmp = memp[addrb_tmp[14:5]]; + end + + endcase + end + endtask // task_rd_ram_b + + + task chk_for_col_msg; + + input wea_tmp; + input web_tmp; + input [15:0] addra_tmp; + input [15:0] addrb_tmp; + + begin + + if ((SIM_COLLISION_CHECK == "ALL" || SIM_COLLISION_CHECK == "WARNING_ONLY") && !(((wr_mode_b == 2'b01 && web_tmp === 1'b1 && wea_tmp === 1'b0) && !(rising_clka && !rising_clkb)) || ((wr_mode_a == 2'b01 && wea_tmp === 1'b1 && web_tmp === 1'b0) && !(rising_clkb && !rising_clka)))) + + if (wea_tmp === 1'b1 && web_tmp === 1'b1 && col_wr_wr_msg == 1) begin + $display("Memory Collision Error on ARAMB36_INTERNAL : %m at simulation time %.3f ns.\nA write was requested to the same address simultaneously at both port A and port B of the RAM. The contents written to the RAM at address location %h (hex) of port A and address location %h (hex) of port B are unknown.", $time/1000.0, addra_tmp, addrb_tmp); + col_wr_wr_msg = 0; + end + + else if (wea_tmp === 1'b1 && web_tmp === 1'b0 && col_wra_rdb_msg == 1) begin + $display("Memory Collision Error on ARAMB36_INTERNAL : %m at simulation time %.3f ns.\nA read was performed on address %h (hex) of port B while a write was requested to the same address on port A. The write will be successful however the read value on port B is unknown until the next CLKB cycle.", $time/1000.0, addrb_tmp); + col_wra_rdb_msg = 0; + end + + else if (wea_tmp === 1'b0 && web_tmp === 1'b1 && col_wrb_rda_msg == 1) begin + $display("Memory Collision Error on ARAMB36_INTERNAL : %m at simulation time %.3f ns.\nA read was performed on address %h (hex) of port A while a write was requested to the same address on port B. The write will be successful however the read value on port A is unknown until the next CLKA cycle.", $time/1000.0, addra_tmp); + col_wrb_rda_msg = 0; + end + + end + + endtask // chk_for_col_msg + + + task task_col_ecc_read; + + inout [63:0] do_tmp; + inout [7:0] dop_tmp; + input [15:0] addr_tmp; + + reg [71:0] task_ecc_bit_position; + reg [7:0] task_dopr_ecc, task_syndrome; + reg [63:0] task_di_in_ecc_corrected; + reg [7:0] task_dip_in_ecc_corrected; + + begin + + if (|do_tmp === 1'bx) begin // if there is collision + dbiterr_out <= 1'bx; + sbiterr_out <= 1'bx; + end + else begin + + task_dopr_ecc = fn_dip_ecc(1'b0, do_tmp, dop_tmp); + + task_syndrome = task_dopr_ecc ^ dop_tmp; + + if (task_syndrome !== 0) begin + + if (task_syndrome[7]) begin // dectect single bit error + + task_ecc_bit_position = {do_tmp[63:57], dop_tmp[6], do_tmp[56:26], dop_tmp[5], do_tmp[25:11], dop_tmp[4], do_tmp[10:4], dop_tmp[3], do_tmp[3:1], dop_tmp[2], do_tmp[0], dop_tmp[1:0], dop_tmp[7]}; + + if (task_syndrome[6:0] > 71) begin + $display ("DRC Error : Simulation halted due Corrupted DIP. To correct this problem, make sure that reliable data is fed to the DIP. The correct Parity must be generated by a Hamming code encoder or encoder in the Block RAM. The output from the model is unreliable if there are more than 2 bit errors. The model doesn't warn if there is sporadic input of more than 2 bit errors due to the limitation in Hamming code."); + $finish; + end + + task_ecc_bit_position[task_syndrome[6:0]] = ~task_ecc_bit_position[task_syndrome[6:0]]; // correct single bit error in the output + + task_di_in_ecc_corrected = {task_ecc_bit_position[71:65], task_ecc_bit_position[63:33], task_ecc_bit_position[31:17], task_ecc_bit_position[15:9], task_ecc_bit_position[7:5], task_ecc_bit_position[3]}; // correct single bit error in the memory + + do_tmp = task_di_in_ecc_corrected; + + task_dip_in_ecc_corrected = {task_ecc_bit_position[0], task_ecc_bit_position[64], task_ecc_bit_position[32], task_ecc_bit_position[16], task_ecc_bit_position[8], task_ecc_bit_position[4], task_ecc_bit_position[2:1]}; // correct single bit error in the parity memory + + dop_tmp = task_dip_in_ecc_corrected; + + dbiterr_out <= 0; + sbiterr_out <= 1; + + end + else if (!task_syndrome[7]) begin // double bit error + sbiterr_out <= 0; + dbiterr_out <= 1; + + end + end // if (task_syndrome !== 0) + else begin + dbiterr_out <= 0; + sbiterr_out <= 0; + + end // else: !if(task_syndrome !== 0) + + if (ssra_in == 1'b1) begin + dbiterr_out <= 0; + sbiterr_out <= 0; + end + + if (task_syndrome !== 0 && task_syndrome[7] === 1 && EN_ECC_SCRUB == "TRUE") + task_wr_ram_a (8'hff, task_di_in_ecc_corrected, task_dip_in_ecc_corrected, addr_tmp); + + end // else: !if(|do_tmp === 1'bx) + end + + endtask // task_col_ecc_read + + + function [7:0] fn_dip_ecc; + + input encode; + input [63:0] di_in; + input [7:0] dip_in; + + begin + + fn_dip_ecc[0] = di_in[0]^di_in[1]^di_in[3]^di_in[4]^di_in[6]^di_in[8] + ^di_in[10]^di_in[11]^di_in[13]^di_in[15]^di_in[17]^di_in[19] + ^di_in[21]^di_in[23]^di_in[25]^di_in[26]^di_in[28] + ^di_in[30]^di_in[32]^di_in[34]^di_in[36]^di_in[38] + ^di_in[40]^di_in[42]^di_in[44]^di_in[46]^di_in[48] + ^di_in[50]^di_in[52]^di_in[54]^di_in[56]^di_in[57]^di_in[59] + ^di_in[61]^di_in[63]; + + fn_dip_ecc[1] = di_in[0]^di_in[2]^di_in[3]^di_in[5]^di_in[6]^di_in[9] + ^di_in[10]^di_in[12]^di_in[13]^di_in[16]^di_in[17] + ^di_in[20]^di_in[21]^di_in[24]^di_in[25]^di_in[27]^di_in[28] + ^di_in[31]^di_in[32]^di_in[35]^di_in[36]^di_in[39] + ^di_in[40]^di_in[43]^di_in[44]^di_in[47]^di_in[48] + ^di_in[51]^di_in[52]^di_in[55]^di_in[56]^di_in[58]^di_in[59] + ^di_in[62]^di_in[63]; + + fn_dip_ecc[2] = di_in[1]^di_in[2]^di_in[3]^di_in[7]^di_in[8]^di_in[9] + ^di_in[10]^di_in[14]^di_in[15]^di_in[16]^di_in[17] + ^di_in[22]^di_in[23]^di_in[24]^di_in[25]^di_in[29] + ^di_in[30]^di_in[31]^di_in[32]^di_in[37]^di_in[38]^di_in[39] + ^di_in[40]^di_in[45]^di_in[46]^di_in[47]^di_in[48] + ^di_in[53]^di_in[54]^di_in[55]^di_in[56] + ^di_in[60]^di_in[61]^di_in[62]^di_in[63]; + + fn_dip_ecc[3] = di_in[4]^di_in[5]^di_in[6]^di_in[7]^di_in[8]^di_in[9] + ^di_in[10]^di_in[18]^di_in[19] + ^di_in[20]^di_in[21]^di_in[22]^di_in[23]^di_in[24]^di_in[25] + ^di_in[33]^di_in[34]^di_in[35]^di_in[36]^di_in[37]^di_in[38]^di_in[39] + ^di_in[40]^di_in[49] + ^di_in[50]^di_in[51]^di_in[52]^di_in[53]^di_in[54]^di_in[55]^di_in[56]; + + fn_dip_ecc[4] = di_in[11]^di_in[12]^di_in[13]^di_in[14]^di_in[15]^di_in[16]^di_in[17]^di_in[18]^di_in[19] + ^di_in[20]^di_in[21]^di_in[22]^di_in[23]^di_in[24]^di_in[25] + ^di_in[41]^di_in[42]^di_in[43]^di_in[44]^di_in[45]^di_in[46]^di_in[47]^di_in[48]^di_in[49] + ^di_in[50]^di_in[51]^di_in[52]^di_in[53]^di_in[54]^di_in[55]^di_in[56]; + + + fn_dip_ecc[5] = di_in[26]^di_in[27]^di_in[28]^di_in[29] + ^di_in[30]^di_in[31]^di_in[32]^di_in[33]^di_in[34]^di_in[35]^di_in[36]^di_in[37]^di_in[38]^di_in[39] + ^di_in[40]^di_in[41]^di_in[42]^di_in[43]^di_in[44]^di_in[45]^di_in[46]^di_in[47]^di_in[48]^di_in[49] + ^di_in[50]^di_in[51]^di_in[52]^di_in[53]^di_in[54]^di_in[55]^di_in[56]; + + fn_dip_ecc[6] = di_in[57]^di_in[58]^di_in[59] + ^di_in[60]^di_in[61]^di_in[62]^di_in[63]; + + if (encode == 1'b1) + + fn_dip_ecc[7] = fn_dip_ecc[0]^fn_dip_ecc[1]^fn_dip_ecc[2]^fn_dip_ecc[3]^fn_dip_ecc[4]^fn_dip_ecc[5]^fn_dip_ecc[6] + ^di_in[0]^di_in[1]^di_in[2]^di_in[3]^di_in[4]^di_in[5]^di_in[6]^di_in[7]^di_in[8]^di_in[9] + ^di_in[10]^di_in[11]^di_in[12]^di_in[13]^di_in[14]^di_in[15]^di_in[16]^di_in[17]^di_in[18]^di_in[19] + ^di_in[20]^di_in[21]^di_in[22]^di_in[23]^di_in[24]^di_in[25]^di_in[26]^di_in[27]^di_in[28]^di_in[29] + ^di_in[30]^di_in[31]^di_in[32]^di_in[33]^di_in[34]^di_in[35]^di_in[36]^di_in[37]^di_in[38]^di_in[39] + ^di_in[40]^di_in[41]^di_in[42]^di_in[43]^di_in[44]^di_in[45]^di_in[46]^di_in[47]^di_in[48]^di_in[49] + ^di_in[50]^di_in[51]^di_in[52]^di_in[53]^di_in[54]^di_in[55]^di_in[56]^di_in[57]^di_in[58]^di_in[59] + ^di_in[60]^di_in[61]^di_in[62]^di_in[63]; + else + fn_dip_ecc[7] = dip_in[0]^dip_in[1]^dip_in[2]^dip_in[3]^dip_in[4]^dip_in[5]^dip_in[6] + ^di_in[0]^di_in[1]^di_in[2]^di_in[3]^di_in[4]^di_in[5]^di_in[6]^di_in[7]^di_in[8]^di_in[9] + ^di_in[10]^di_in[11]^di_in[12]^di_in[13]^di_in[14]^di_in[15]^di_in[16]^di_in[17]^di_in[18]^di_in[19] + ^di_in[20]^di_in[21]^di_in[22]^di_in[23]^di_in[24]^di_in[25]^di_in[26]^di_in[27]^di_in[28]^di_in[29] + ^di_in[30]^di_in[31]^di_in[32]^di_in[33]^di_in[34]^di_in[35]^di_in[36]^di_in[37]^di_in[38]^di_in[39] + ^di_in[40]^di_in[41]^di_in[42]^di_in[43]^di_in[44]^di_in[45]^di_in[46]^di_in[47]^di_in[48]^di_in[49] + ^di_in[50]^di_in[51]^di_in[52]^di_in[53]^di_in[54]^di_in[55]^di_in[56]^di_in[57]^di_in[58]^di_in[59] + ^di_in[60]^di_in[61]^di_in[62]^di_in[63]; + + end + + endfunction // fn_dip_ecc + +/******************************************** END task and function **************************************/ + + buf b_addra[15:0] (addra_in, ADDRA); + buf b_addrb[15:0] (addrb_in, ADDRB); + buf b_clka (clka_in, CLKA); + buf b_clkb (clkb_in, CLKB); + buf b_regclka (regclka_in, REGCLKA); + buf b_regclkb (regclkb_in, REGCLKB); + + buf b_dia[63:0] (dia_in, DIA); + buf b_dib[63:0] (dib_in, DIB); + buf b_dipa[3:0] (dipa_in, DIPA); + buf b_dipb[7:0] (dipb_in, DIPB); + buf b_doa[63:0] (DOA, doa_out_out); + buf b_dopa[7:0] (DOPA, dopa_out_out); + buf b_dob[31:0] (DOB, dob_out_out); + buf b_dopb[3:0] (DOPB, dopb_out_out); + + buf b_ena (ena_in, ENA); + buf b_enb (enb_in, ENB); + buf b_gsr (gsr_in, GSR); + buf b_regcea (regcea_in, REGCEA); + buf b_regceb (regceb_in, REGCEB); + buf b_ssra (ssra_in, SSRA); + buf b_ssrb (ssrb_in, SSRB); + buf b_wea[7:0] (wea_in, WEA); + buf b_web[7:0] (web_in, WEB); + buf b_cascadeinlata (cascadeinlata_in, CASCADEINLATA); + buf b_cascadeinlatb (cascadeinlatb_in, CASCADEINLATB); + buf b_cascadeoutlata (CASCADEOUTLATA, doa_out[0]); + buf b_cascadeoutlatb (CASCADEOUTLATB, dob_out[0]); + buf b_cascadeinrega (cascadeinrega_in, CASCADEINREGA); + buf b_cascadeinregb (cascadeinregb_in, CASCADEINREGB); + buf b_cascadeoutrega (CASCADEOUTREGA, doa_outreg[0]); + buf b_cascadeoutregb (CASCADEOUTREGB, dob_outreg[0]); + buf b_sbiterr (SBITERR, sbiterr_out_out); + buf b_dbiterr (DBITERR, dbiterr_out_out); + buf b_eccparity[7:0] (ECCPARITY, eccparity_out); + + + initial begin + + case (WRITE_WIDTH_A) + + 0, 1, 2, 4, 9, 18 : ; + 36 : begin + if (BRAM_SIZE == 18 && BRAM_MODE == "TRUE_DUAL_PORT") begin + $display("Attribute Syntax Error : The attribute WRITE_WIDTH_A on ARAMB36_INTERNAL instance %m is set to %d. Legal values for this attribute are 0, 1, 2, 4, 9 or 18.", WRITE_WIDTH_A); + $finish; + end + end + 72 : begin + if (BRAM_SIZE == 18) begin + $display("Attribute Syntax Error : The attribute WRITE_WIDTH_A on ARAMB36_INTERNAL instance %m is set to %d. Legal values for this attribute are 0, 1, 2, 4, 9 or 18.", WRITE_WIDTH_A); + $finish; + end + else if ((BRAM_SIZE == 16 || BRAM_SIZE == 36) && BRAM_MODE == "TRUE_DUAL_PORT") begin // BRAM_SIZE == 16 - Virtex 4 + $display("Attribute Syntax Error : The attribute WRITE_WIDTH_A on ARAMB36_INTERNAL instance %m is set to %d. Legal values for this attribute are 0, 1, 2, 4, 9, 18 or 36.", WRITE_WIDTH_A); + $finish; + end + end + default : begin + if (BRAM_SIZE == 18) begin + $display("Attribute Syntax Error : The attribute WRITE_WIDTH_A on ARAMB36_INTERNAL instance %m is set to %d. Legal values for this attribute are 0, 1, 2, 4, 9 or 18.", WRITE_WIDTH_A); + $finish; + end + else if (BRAM_SIZE == 16 || BRAM_SIZE == 36) begin + $display("Attribute Syntax Error : The attribute WRITE_WIDTH_A on ARAMB36_INTERNAL instance %m is set to %d. Legal values for this attribute are 0, 1, 2, 4, 9, 18 or 36.", WRITE_WIDTH_A); + $finish; + end + end + + endcase // case(WRITE_WIDTH_A) + + + case (WRITE_WIDTH_B) + + 0, 1, 2, 4, 9, 18 : ; + 36 : begin + if (BRAM_SIZE == 18 && BRAM_MODE == "TRUE_DUAL_PORT") begin + $display("Attribute Syntax Error : The attribute WRITE_WIDTH_B on ARAMB36_INTERNAL instance %m is set to %d. Legal values for this attribute are 0, 1, 2, 4, 9 or 18.", WRITE_WIDTH_B); + $finish; + end + end + 72 : begin + if (BRAM_SIZE == 18) begin + $display("Attribute Syntax Error : The attribute WRITE_WIDTH_B on ARAMB36_INTERNAL instance %m is set to %d. Legal values for this attribute are 0, 1, 2, 4, 9 or 18.", WRITE_WIDTH_B); + $finish; + end + else if ((BRAM_SIZE == 16 || BRAM_SIZE == 36) && BRAM_MODE == "TRUE_DUAL_PORT") begin + $display("Attribute Syntax Error : The attribute WRITE_WIDTH_B on ARAMB36_INTERNAL instance %m is set to %d. Legal values for this attribute are 0, 1, 2, 4, 9, 18 or 36.", WRITE_WIDTH_B); + $finish; + end + end + default : begin + if (BRAM_SIZE == 18) begin + $display("Attribute Syntax Error : The attribute WRITE_WIDTH_B on ARAMB36_INTERNAL instance %m is set to %d. Legal values for this attribute are 0, 1, 2, 4, 9 or 18.", WRITE_WIDTH_B); + $finish; + end + else if (BRAM_SIZE == 16 || BRAM_SIZE == 36) begin + $display("Attribute Syntax Error : The attribute WRITE_WIDTH_B on ARAMB36_INTERNAL instance %m is set to %d. Legal values for this attribute are 0, 1, 2, 4, 9, 18 or 36.", WRITE_WIDTH_B); + $finish; + end + end + + endcase // case(WRITE_WIDTH_B) + + + case (READ_WIDTH_A) + + 0, 1, 2, 4, 9, 18 : ; + 36 : begin + if (BRAM_SIZE == 18 && BRAM_MODE == "TRUE_DUAL_PORT") begin + $display("Attribute Syntax Error : The attribute READ_WIDTH_A on ARAMB36_INTERNAL instance %m is set to %d. Legal values for this attribute are 0, 1, 2, 4, 9 or 18.", READ_WIDTH_A); + $finish; + end + end + 72 : begin + if (BRAM_SIZE == 18) begin + $display("Attribute Syntax Error : The attribute READ_WIDTH_A on ARAMB36_INTERNAL instance %m is set to %d. Legal values for this attribute are 0, 1, 2, 4, 9 or 18.", READ_WIDTH_A); + $finish; + end + else if ((BRAM_SIZE == 16 || BRAM_SIZE == 36) && BRAM_MODE == "TRUE_DUAL_PORT") begin + $display("Attribute Syntax Error : The attribute READ_WIDTH_A on ARAMB36_INTERNAL instance %m is set to %d. Legal values for this attribute are 0, 1, 2, 4, 9, 18 or 36.", READ_WIDTH_A); + $finish; + end + end + default : begin + if (BRAM_SIZE == 18) begin + $display("Attribute Syntax Error : The attribute READ_WIDTH_A on ARAMB36_INTERNAL instance %m is set to %d. Legal values for this attribute are 0, 1, 2, 4, 9 or 18.", READ_WIDTH_A); + $finish; + end + else if (BRAM_SIZE == 16 || BRAM_SIZE == 36) begin + $display("Attribute Syntax Error : The attribute READ_WIDTH_A on ARAMB36_INTERNAL instance %m is set to %d. Legal values for this attribute are 0, 1, 2, 4, 9, 18 or 36.", READ_WIDTH_A); + $finish; + end + end + + endcase // case(READ_WIDTH_A) + + + case (READ_WIDTH_B) + + 0, 1, 2, 4, 9, 18 : ; + 36 : begin + if (BRAM_SIZE == 18 && BRAM_MODE == "TRUE_DUAL_PORT") begin + $display("Attribute Syntax Error : The attribute READ_WIDTH_B on ARAMB36_INTERNAL instance %m is set to %d. Legal values for this attribute are 0, 1, 2, 4, 9 or 18.", READ_WIDTH_B); + $finish; + end + end + 72 : begin + if (BRAM_SIZE == 18) begin + $display("Attribute Syntax Error : The attribute READ_WIDTH_B on ARAMB36_INTERNAL instance %m is set to %d. Legal values for this attribute are 0, 1, 2, 4, 9 or 18.", READ_WIDTH_B); + $finish; + end + else if ((BRAM_SIZE == 16 || BRAM_SIZE == 36) && BRAM_MODE == "TRUE_DUAL_PORT") begin + $display("Attribute Syntax Error : The attribute READ_WIDTH_B on ARAMB36_INTERNAL instance %m is set to %d. Legal values for this attribute are 0, 1, 2, 4, 9, 18 or 36.", READ_WIDTH_B); + $finish; + end + end + default : begin + if (BRAM_SIZE == 18) begin + $display("Attribute Syntax Error : The attribute READ_WIDTH_B on ARAMB36_INTERNAL instance %m is set to %d. Legal values for this attribute are 0, 1, 2, 4, 9 or 18.", READ_WIDTH_B); + $finish; + end + else if (BRAM_SIZE == 16 || BRAM_SIZE == 36) begin + $display("Attribute Syntax Error : The attribute READ_WIDTH_B on ARAMB36_INTERNAL instance %m is set to %d. Legal values for this attribute are 0, 1, 2, 4, 9, 18 or 36.", READ_WIDTH_B); + $finish; + end + end + + endcase // case(READ_WIDTH_B) + + + if ((RAM_EXTENSION_A == "LOWER" || RAM_EXTENSION_A == "UPPER") && READ_WIDTH_A != 1) begin + $display("Attribute Syntax Error : If attribute RAM_EXTENSION_A on ARAMB36_INTERNAL instance %m is set to either LOWER or UPPER, then READ_WIDTH_A has to be set to 1."); + $finish; + end + + + if ((RAM_EXTENSION_A == "LOWER" || RAM_EXTENSION_A == "UPPER") && WRITE_WIDTH_A != 1) begin + $display("Attribute Syntax Error : If attribute RAM_EXTENSION_A on ARAMB36_INTERNAL instance %m is set to either LOWER or UPPER, then WRITE_WIDTH_A has to be set to 1."); + $finish; + end + + + if ((RAM_EXTENSION_B == "LOWER" || RAM_EXTENSION_B == "UPPER") && READ_WIDTH_B != 1) begin + $display("Attribute Syntax Error : If attribute RAM_EXTENSION_B on ARAMB36_INTERNAL instance %m is set to either LOWER or UPPER, then READ_WIDTH_B has to be set to 1."); + $finish; + end + + + if ((RAM_EXTENSION_B == "LOWER" || RAM_EXTENSION_B == "UPPER") && WRITE_WIDTH_B != 1) begin + $display("Attribute Syntax Error : If attribute RAM_EXTENSION_B on ARAMB36_INTERNAL instance %m is set to either LOWER or UPPER, then WRITE_WIDTH_B has to be set to 1."); + $finish; + end + + + if (READ_WIDTH_A == 0 && READ_WIDTH_B == 0) begin + $display("Attribute Syntax Error : Attributes READ_WIDTH_A and READ_WIDTH_B on ARAMB36_INTERNAL instance %m, both can not be 0."); + $finish; + end + + + case (WRITE_MODE_A) + "WRITE_FIRST" : wr_mode_a <= 2'b00; + "READ_FIRST" : wr_mode_a <= 2'b01; + "NO_CHANGE" : wr_mode_a <= 2'b10; + default : begin + $display("Attribute Syntax Error : The Attribute WRITE_MODE_A on ARAMB36_INTERNAL instance %m is set to %s. Legal values for this attribute are WRITE_FIRST, READ_FIRST or NO_CHANGE.", WRITE_MODE_A); + $finish; + end + endcase + + + case (WRITE_MODE_B) + "WRITE_FIRST" : wr_mode_b <= 2'b00; + "READ_FIRST" : wr_mode_b <= 2'b01; + "NO_CHANGE" : wr_mode_b <= 2'b10; + default : begin + $display("Attribute Syntax Error : The Attribute WRITE_MODE_B on ARAMB36_INTERNAL instance %m is set to %s. Legal values for this attribute are WRITE_FIRST, READ_FIRST or NO_CHANGE.", WRITE_MODE_B); + $finish; + end + endcase + + case (RAM_EXTENSION_A) + "UPPER" : cascade_a <= 2'b11; + "LOWER" : cascade_a <= 2'b01; + "NONE" : cascade_a <= 2'b00; + default : begin + $display("Attribute Syntax Error : The attribute RAM_EXTENSION_A on ARAMB36_INTERNAL instance %m is set to %s. Legal values for this attribute are LOWER, NONE or UPPER.", RAM_EXTENSION_A); + $finish; + end + endcase + + + case (RAM_EXTENSION_B) + "UPPER" : cascade_b <= 2'b11; + "LOWER" : cascade_b <= 2'b01; + "NONE" : cascade_b <= 2'b00; + default : begin + $display("Attribute Syntax Error : The attribute RAM_EXTENSION_B on ARAMB36_INTERNAL instance %m is set to %s. Legal values for this attribute are LOWER, NONE or UPPER.", RAM_EXTENSION_B); + $finish; + end + endcase + + + if (!(EN_ECC_WRITE == "TRUE" || EN_ECC_WRITE == "FALSE")) begin + $display("Attribute Syntax Error : The attribute EN_ECC_WRITE on ARAMB36_INTERNAL instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", EN_ECC_WRITE); + $finish; + end + + + if (!(EN_ECC_READ == "TRUE" || EN_ECC_READ == "FALSE")) begin + $display("Attribute Syntax Error : The attribute EN_ECC_READ on ARAMB36_INTERNAL instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", EN_ECC_READ); + $finish; + end + + if (EN_ECC_SCRUB == "TRUE") begin + $display("DRC Error : The attribute EN_ECC_SCRUB = TRUE is not supported on ARAMB36_INTERNAL instance %m."); + $finish; + end + + if (!(EN_ECC_SCRUB == "TRUE" || EN_ECC_SCRUB == "FALSE")) begin + $display("Attribute Syntax Error : The attribute EN_ECC_SCRUB on ARAMB36_INTERNAL instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", EN_ECC_SCRUB); + $finish; + end + + + if (EN_ECC_READ == "FALSE" && EN_ECC_SCRUB == "TRUE") begin + $display("DRC Error : The attribute EN_ECC_SCRUB = TRUE is vaild only if the attribute EN_ECC_READ set to TRUE on ARAMB36_INTERNAL instance %m."); + $finish; + end + + + if ((SIM_COLLISION_CHECK != "ALL") && (SIM_COLLISION_CHECK != "NONE") && (SIM_COLLISION_CHECK != "WARNING_ONLY") && (SIM_COLLISION_CHECK != "GENERATE_X_ONLY")) begin + + $display("Attribute Syntax Error : The attribute SIM_COLLISION_CHECK on ARAMB36_INTERNAL instance %m is set to %s. Legal values for this attribute are ALL, NONE, WARNING_ONLY or GENERATE_X_ONLY.", SIM_COLLISION_CHECK); + $finish; + + end + + end // initial begin + + + always @(gsr_in) + if (gsr_in) begin + + assign doa_out_out = INIT_A[0 +: ra_width]; + assign doa_out = INIT_A[0 +: ra_width]; + + if (ra_width >= 8) begin + assign dopa_out_out = INIT_A[ra_width +: ra_widthp]; + assign dopa_out = INIT_A[ra_width +: ra_widthp]; + end + + assign dob_out_out = INIT_B[0 +: rb_width]; + assign dob_out = INIT_B[0 +: rb_width]; + + if (rb_width >= 8) begin + assign dopb_out_out = INIT_B[rb_width +: rb_widthp]; + assign dopb_out = INIT_B[rb_width +: rb_widthp]; + end + + assign dbiterr_out = 0; + assign sbiterr_out = 0; + + end + else begin + deassign doa_out_out; + deassign dopa_out_out; + deassign dob_out_out; + deassign dopb_out_out; + deassign doa_out; + deassign dopa_out; + deassign dob_out; + deassign dopb_out; + deassign dbiterr_out; + deassign sbiterr_out; + end + + + always @(posedge clka_in) begin + + rising_clka = 1; + + if (ena_in === 1'b1) begin + prev_time = curr_time; + curr_time = $time; + addra_reg = addra_in; + wea_reg = wea_in; + dia_reg = dia_in; + dipa_reg = dipa_in; + end + + end + + always @(posedge clkb_in) begin + + rising_clkb = 1; + + if (enb_in === 1'b1) begin + prev_time = curr_time; + curr_time = $time; + addrb_reg = addrb_in; + web_reg = web_in; + enb_reg = enb_in; + dib_reg = dib_in; + dipb_reg = dipb_in; + end + + end // always @ (posedge clkb_in) + + + always @(posedge rising_clka or posedge rising_clkb) begin + + if (rising_clka) + if (cascade_a[1]) + addra_in_15_reg_bram = ~addra_in[15]; + else + addra_in_15_reg_bram = addra_in[15]; + + if (rising_clkb) + if (cascade_b[1]) + addrb_in_15_reg_bram = ~addrb_in[15]; + else + addrb_in_15_reg_bram = addrb_in[15]; + + if ((cascade_a == 2'b00 || (addra_in_15_reg_bram == 1'b0 && cascade_a != 2'b00)) && (cascade_b == 2'b00 || (addrb_in_15_reg_bram == 1'b0 && cascade_b != 2'b00))) begin + +/************************************* Collision starts *****************************************/ + + if (SIM_COLLISION_CHECK != "NONE") begin + + if (gsr_in === 1'b0) begin + if (curr_time - prev_time == 0) begin + viol_time = 1; + end + else if (curr_time - prev_time <= SETUP_READ_FIRST) begin + viol_time = 2; + end + + + if (ena_in === 1'b0 || enb_in === 1'b0) + viol_time = 0; + + + if ((WRITE_WIDTH_A <= 9 && wea_in[0] === 1'b0) || (WRITE_WIDTH_A == 18 && wea_in[1:0] === 2'b00) || ((WRITE_WIDTH_A == 36 || WRITE_WIDTH_A == 72) && wea_in[3:0] === 4'b0000)) + if ((WRITE_WIDTH_B <= 9 && web_in[0] === 1'b0) || (WRITE_WIDTH_B == 18 && web_in[1:0] === 2'b00) || (WRITE_WIDTH_B == 36 && web_in[3:0] === 4'b0000) || (WRITE_WIDTH_B == 72 && web_in[7:0] === 8'h00)) + viol_time = 0; + + + if (viol_time != 0) begin + + if (rising_clka && rising_clkb) begin + + if (cascade_a[0] || cascade_b[0] == 1) begin + if (addra_in[15:col_addr_lsb] === addrb_in[15:col_addr_lsb]) + addr_col = 1; + else + addr_col = 0; + end + else begin + if (addra_in[14:col_addr_lsb] === addrb_in[14:col_addr_lsb]) + addr_col = 1; + else + addr_col = 0; + end // else: !if(cascade_a[0] || cascade_b[0] == 1) + + + if (addr_col) begin + + viol_type = 2'b01; + + task_rd_ram_a (addra_in, doa_buf, dopa_buf); + task_rd_ram_b (addrb_in, dob_buf, dopb_buf); + + task_col_wr_ram_a (2'b00, web_in, wea_in, di_x, di_x[7:0], addrb_in, addra_in); + task_col_wr_ram_b (2'b00, wea_in, web_in, di_x, di_x[7:0], addra_in, addrb_in); + + task_col_rd_ram_a (2'b01, web_in, wea_in, addra_in, doa_buf, dopa_buf); + task_col_rd_ram_b (2'b01, wea_in, web_in, addrb_in, dob_buf, dopb_buf); + + task_col_wr_ram_a (2'b10, web_in, wea_in, dia_in, dipa_in, addrb_in, addra_in); + + + if (BRAM_MODE == "ECC" && EN_ECC_WRITE == "TRUE" && enb_in === 1'b1) begin + + dip_ecc_col = fn_dip_ecc(1'b1, dib_in, dipb_in); + eccparity_out = dip_ecc_col; + task_col_wr_ram_b (2'b10, wea_in, web_in, dib_in, dip_ecc_col, addra_in, addrb_in); + + end + else + task_col_wr_ram_b (2'b10, wea_in, web_in, dib_in, dipb_in, addra_in, addrb_in); + + + if (wr_mode_a != 2'b01) + task_col_rd_ram_a (2'b11, web_in, wea_in, addra_in, doa_buf, dopa_buf); + if (wr_mode_b != 2'b01) + task_col_rd_ram_b (2'b11, wea_in, web_in, addrb_in, dob_buf, dopb_buf); + + + if (BRAM_MODE == "ECC" && EN_ECC_READ == "TRUE") + task_col_ecc_read (doa_buf, dopa_buf, addra_in); + + + end // if (addr_col) + else + viol_time = 0; + + end + else if (rising_clka && !rising_clkb) begin + + if (cascade_a[0] || cascade_b[0] == 1) begin + if (addra_in[15:col_addr_lsb] === addrb_reg[15:col_addr_lsb]) + addr_col = 1; + else + addr_col = 0; + end + else begin + if (addra_in[14:col_addr_lsb] === addrb_reg[14:col_addr_lsb]) + addr_col = 1; + else + addr_col = 0; + end // else: !if(cascade_a[0] || cascade_b[0] == 1) + + + if (addr_col) begin + + viol_type = 2'b10; + + task_rd_ram_a (addra_in, doa_buf, dopa_buf); + + task_col_wr_ram_a (2'b00, web_reg, wea_in, di_x, di_x[7:0], addrb_reg, addra_in); + task_col_wr_ram_b (2'b00, wea_in, web_reg, di_x, di_x[7:0], addra_in, addrb_reg); + + task_col_rd_ram_a (2'b01, web_reg, wea_in, addra_in, doa_buf, dopa_buf); + task_col_rd_ram_b (2'b01, wea_in, web_reg, addrb_reg, dob_buf, dopb_buf); + + task_col_wr_ram_a (2'b10, web_reg, wea_in, dia_in, dipa_in, addrb_reg, addra_in); + + + if (BRAM_MODE == "ECC" && EN_ECC_WRITE == "TRUE" && enb_reg === 1'b1) begin + + dip_ecc_col = fn_dip_ecc(1'b1, dib_reg, dipb_reg); + eccparity_out = dip_ecc_col; + task_col_wr_ram_b (2'b10, wea_in, web_reg, dib_reg, dip_ecc_col, addra_in, addrb_reg); + + end + else + task_col_wr_ram_b (2'b10, wea_in, web_reg, dib_reg, dipb_reg, addra_in, addrb_reg); + + + if (wr_mode_a != 2'b01) + task_col_rd_ram_a (2'b11, web_reg, wea_in, addra_in, doa_buf, dopa_buf); + if (wr_mode_b != 2'b01) + task_col_rd_ram_b (2'b11, wea_in, web_reg, addrb_reg, dob_buf, dopb_buf); + + if (BRAM_MODE == "ECC" && EN_ECC_READ == "TRUE") + task_col_ecc_read (doa_buf, dopa_buf, addra_in); + + + end // if (addr_col) + else + viol_time = 0; + + end + else if (!rising_clka && rising_clkb) begin + + if (cascade_a[0] || cascade_b[0] == 1) begin + if (addra_reg[15:col_addr_lsb] === addrb_in[15:col_addr_lsb]) + addr_col = 1; + else + addr_col = 0; + end + else begin + if (addra_reg[14:col_addr_lsb] === addrb_in[14:col_addr_lsb]) + addr_col = 1; + else + addr_col = 0; + end // else: !if(cascade_a[0] || cascade_b[0] == 1) + + + if (addr_col) begin + + viol_type = 2'b11; + + task_rd_ram_b (addrb_in, dob_buf, dopb_buf); + + task_col_wr_ram_a (2'b00, web_in, wea_reg, di_x, di_x[7:0], addrb_in, addra_reg); + task_col_wr_ram_b (2'b00, wea_reg, web_in, di_x, di_x[7:0], addra_reg, addrb_in); + + task_col_rd_ram_a (2'b01, web_in, wea_reg, addra_reg, doa_buf, dopa_buf); + task_col_rd_ram_b (2'b01, wea_reg, web_in, addrb_in, dob_buf, dopb_buf); + + task_col_wr_ram_a (2'b10, web_in, wea_reg, dia_reg, dipa_reg, addrb_in, addra_reg); + + + if (BRAM_MODE == "ECC" && EN_ECC_WRITE == "TRUE" && enb_in === 1'b1) begin + + dip_ecc_col = fn_dip_ecc(1'b1, dib_in, dipb_in); + eccparity_out = dip_ecc_col; + task_col_wr_ram_b (2'b10, wea_reg, web_in, dib_in, dip_ecc_col, addra_reg, addrb_in); + + end + else + task_col_wr_ram_b (2'b10, wea_reg, web_in, dib_in, dipb_in, addra_reg, addrb_in); + + + if (wr_mode_a != 2'b01) + task_col_rd_ram_a (2'b11, web_in, wea_reg, addra_reg, doa_buf, dopa_buf); + if (wr_mode_b != 2'b01) + task_col_rd_ram_b (2'b11, wea_reg, web_in, addrb_in, dob_buf, dopb_buf); + + if (BRAM_MODE == "ECC" && EN_ECC_READ == "TRUE") + task_col_ecc_read (doa_buf, dopa_buf, addra_reg); + + + end // if (addr_col) + else + viol_time = 0; + + end + + end // if (viol_time != 0) + end // if (gsr_in === 1'b0) + + if (SIM_COLLISION_CHECK == "WARNING_ONLY") + viol_time = 0; + + end // if (SIM_COLLISION_CHECK != "NONE") + + +/*************************************** end collision ********************************/ + + end // if ((cascade_a == 2'b00 || (addra_in_15_reg_bram == 1'b0 && cascade_a != 2'b00)) && (cascade_b == 2'b00 || (addrb_in_15_reg_bram == 1'b0 && cascade_b != 2'b00))) + + +/**************************** Port A ****************************************/ + if (rising_clka) begin + + // DRC + if (ssra_in === 1 && BRAM_MODE == "ECC") + $display("DRC Warning : SET/RESET (SSR) is not supported in ECC mode on ARAMB36_INTERNAL instance %m."); + + if (ssra_in === 1 && BRAM_SIZE == 16 && DOA_REG == 1) begin + $display("DRC Error : SET/RESET (SSR) is not supported when optional output registers are used on ARAMB36_INTERNAL instance %m."); + $finish; + end + + + + // registering addra_in[15] the second time + if (regcea_in) + addra_in_15_reg1 = addra_in_15_reg; + + + if (ena_in && (wr_mode_a != 2'b10 || wea_in[0] == 0 || ssra_in == 1'b1)) + if (cascade_a[1]) + addra_in_15_reg = ~addra_in[15]; + else + addra_in_15_reg = addra_in[15]; + + + if (gsr_in == 1'b0 && ena_in == 1'b1 && (cascade_a == 2'b00 || (addra_in_15_reg_bram == 1'b0 && cascade_a != 2'b00))) begin + + if (ssra_in == 1'b1 && DOA_REG == 0) begin + doa_buf = SRVAL_A[0 +: ra_width]; + doa_out = SRVAL_A[0 +: ra_width]; + + if (ra_width >= 8) begin + dopa_buf = SRVAL_A[ra_width +: ra_widthp]; + dopa_out = SRVAL_A[ra_width +: ra_widthp]; + end + end + + + if (viol_time == 0) begin + + if ((wr_mode_a == 2'b01 && (ssra_in === 1'b0 || DOA_REG == 1)) || (BRAM_MODE == "ECC" && EN_ECC_READ == "TRUE")) begin + task_rd_ram_a (addra_in, doa_buf, dopa_buf); + + + if (BRAM_MODE == "ECC" && EN_ECC_READ == "TRUE") begin + + dopr_ecc = fn_dip_ecc(1'b0, doa_buf, dopa_buf); + + syndrome = dopr_ecc ^ dopa_buf; + + if (syndrome !== 0) begin + + if (syndrome[7]) begin // dectect single bit error + + ecc_bit_position = {doa_buf[63:57], dopa_buf[6], doa_buf[56:26], dopa_buf[5], doa_buf[25:11], dopa_buf[4], doa_buf[10:4], dopa_buf[3], doa_buf[3:1], dopa_buf[2], doa_buf[0], dopa_buf[1:0], dopa_buf[7]}; + + if (syndrome[6:0] > 71) begin + $display ("DRC Error : Simulation halted due Corrupted DIP. To correct this problem, make sure that reliable data is fed to the DIP. The correct Parity must be generated by a Hamming code encoder or encoder in the Block RAM. The output from the model is unreliable if there are more than 2 bit errors. The model doesn't warn if there is sporadic input of more than 2 bit errors due to the limitation in Hamming code."); + $finish; + end + + ecc_bit_position[syndrome[6:0]] = ~ecc_bit_position[syndrome[6:0]]; // correct single bit error in the output + + dia_in_ecc_corrected = {ecc_bit_position[71:65], ecc_bit_position[63:33], ecc_bit_position[31:17], ecc_bit_position[15:9], ecc_bit_position[7:5], ecc_bit_position[3]}; // correct single bit error in the memory + + doa_buf = dia_in_ecc_corrected; + + dipa_in_ecc_corrected = {ecc_bit_position[0], ecc_bit_position[64], ecc_bit_position[32], ecc_bit_position[16], ecc_bit_position[8], ecc_bit_position[4], ecc_bit_position[2:1]}; // correct single bit error in the parity memory + + dopa_buf = dipa_in_ecc_corrected; + + dbiterr_out <= 0; + sbiterr_out <= 1; + + end + else if (!syndrome[7]) begin // double bit error + sbiterr_out <= 0; + dbiterr_out <= 1; + + end + end // if (syndrome !== 0) + else begin + dbiterr_out <= 0; + sbiterr_out <= 0; + + end // else: !if(syndrome !== 0) + + if (ssra_in == 1'b1) begin + dbiterr_out <= 0; + sbiterr_out <= 0; + end + + end // if (BRAM_MODE == "ECC" && EN_ECC_READ == "TRUE") + end // if (((wr_mode_a == 2'b01) && (ssra_in === 1'b0 || DOA_REG == 1)) || (BRAM_MODE == "ECC" && EN_ECC_READ == "TRUE")) + + if (syndrome !== 0 && syndrome[7] === 1 && EN_ECC_SCRUB == "TRUE") + task_wr_ram_a (8'hff, dia_in_ecc_corrected, dipa_in_ecc_corrected, addra_in); + else + task_wr_ram_a (wea_in, dia_in, dipa_in, addra_in); + + + if ((wr_mode_a != 2'b01 && (ssra_in === 1'b0 || DOA_REG == 1)) && !(BRAM_MODE == "ECC" && EN_ECC_READ == "TRUE")) + task_rd_ram_a (addra_in, doa_buf, dopa_buf); + + end // if (viol_time == 0) + + end // if (gsr_in == 1'b0 && ena_in == 1'b1 && (cascade_a == 2'b00 || (addra_in_15_reg_bram == 1'b0 && cascade_a != 2'b00))) + + end // if (rising_clka) + // end of port A + + +/************************************** port B ***************************************************************/ + if (rising_clkb) begin + + // DRC + if (ssrb_in === 1 && BRAM_MODE == "ECC") + $display("DRC Warning : SET/RESET (SSR) is not supported in ECC mode on ARAMB36_INTERNAL instance %m."); + + if (ssrb_in === 1 && BRAM_SIZE == 16 && DOB_REG == 1) begin + $display("DRC Error : SET/RESET (SSR) is not supported when optional output registers are used on ARAMB36_INTERNAL instance %m."); + $finish; + end + + if (regceb_in) + addrb_in_15_reg1 = addrb_in_15_reg; + + + if (enb_in && (wr_mode_b != 2'b10 || web_in[0] == 0 || ssrb_in == 1'b1)) + if (cascade_b[1]) + addrb_in_15_reg = ~addrb_in[15]; + else + addrb_in_15_reg = addrb_in[15]; + + + if (gsr_in == 1'b0 && enb_in == 1'b1 && (cascade_b == 2'b00 || (addrb_in_15_reg_bram == 1'b0 && cascade_b != 2'b00))) begin + if (ssrb_in == 1'b1 && DOB_REG == 0) begin + + dob_buf = SRVAL_B[0 +: rb_width]; + dob_out = SRVAL_B[0 +: rb_width]; + + if (rb_width >= 8) begin + dopb_buf = SRVAL_B[rb_width +: rb_widthp]; + dopb_out = SRVAL_B[rb_width +: rb_widthp]; + end + + end + + + dip_ecc = fn_dip_ecc(1'b1, dib_in, dipb_in); + + eccparity_out = dip_ecc; + + + if (BRAM_MODE == "ECC" && EN_ECC_WRITE == "TRUE") + dipb_in_ecc = dip_ecc; + else + dipb_in_ecc = dipb_in; + + + if (viol_time == 0) begin + + if (wr_mode_b == 2'b01 && (ssrb_in === 1'b0 || DOB_REG == 1)) + task_rd_ram_b (addrb_in, dob_buf, dopb_buf); + + + if (BRAM_MODE == "ECC" && EN_ECC_WRITE == "TRUE") + task_wr_ram_b (web_in, dib_in, dipb_in_ecc, addrb_in); + else + task_wr_ram_b (web_in, dib_in, dipb_in, addrb_in); + + + if (wr_mode_b != 2'b01 && (ssrb_in === 1'b0 || DOB_REG == 1)) + task_rd_ram_b (addrb_in, dob_buf, dopb_buf); + + end // if (viol_time == 0) + + + end // if (gsr_in == 1'b0 && enb_in == 1'b1 && (cascade_b == 2'b00 || addrb_in_15_reg_bram == 1'b0)) + + end // if (rising_clkb) + // end of port B + + + // writing outputs of port A + if (ena_in && (rising_clka || viol_time != 0)) begin + + if ((ssra_in === 1'b0 || DOA_REG == 1) && (wr_mode_a != 2'b10 || (WRITE_WIDTH_A <= 9 && wea_in[0] === 1'b0) || (WRITE_WIDTH_A == 18 && wea_in[1:0] === 2'b00) || ((WRITE_WIDTH_A == 36 || WRITE_WIDTH_A == 72) && wea_in[3:0] === 4'b0000))) begin + + // Virtex4 feature + if (wr_mode_a == 2'b00 && BRAM_SIZE == 16) begin + + if ((WRITE_WIDTH_A == 18 && !(wea_in[1:0] === 2'b00 || wea_in[1:0] === 2'b11)) || (WRITE_WIDTH_A == 36 && !(wea_in[3:0] === 4'b0000 || wea_in[3:0] === 4'b1111))) begin + + if (WRITE_WIDTH_A != READ_WIDTH_A) begin + + doa_buf[ra_width-1:0] = di_x[ra_width-1:0]; + + if (READ_WIDTH_A >= 9) + dopa_buf[ra_widthp-1:0] = di_x[ra_widthp-1:0]; + + if (READ_WIDTH_A != 0) + $display("Functional warning at simulation time (%.3f ns) : ARAMB36_INTERNAL (%m) port A is in WRITE_FIRST mode with parameter WRITE_WIDTH_A = %d, which is different from READ_WIDTH_A = %d. The write will be successful however the read value of all bits on port A is unknown until the next CLKA cycle and all bits of WEA is set to all 1s or 0s.", $time/1000.0, WRITE_WIDTH_A, READ_WIDTH_A); + + end + else if (WRITE_WIDTH_A == 18) begin + for (i = 0; i <= 1; i = i + 1) begin + + if (wea_in[i] === 1'b0) begin + for (i1 = (8 * i); i1 < (8 * (i + 1)); i1 = i1 + 1) + doa_buf[i1] = di_x[i1]; + + for (i_p = i; i_p < (i + 1); i_p = i_p + 1) + dopa_buf[i_p] = di_x[i_p]; + + end + + end // for (i = 0; i <= 1; i = i + 1) + + if (READ_WIDTH_A != 0) + $display("Functional warning at simulation time (%.3f ns) : ARAMB36_INTERNAL (%m) port A is in WRITE_FIRST mode. The write will be successful, however DOA shows only the enabled newly written byte(s). The other byte values on DOA are unknown until the next CLKA cycle and all bits of WEA is set to all 1s or 0s.", $time/1000.0); + + end // if (WRITE_WIDTH_A == 18) + else if (WRITE_WIDTH_A == 36) begin + for (i = 0; i <= 3; i = i + 1) begin + + if (wea_in[i] === 1'b0) begin + for (i1 = (8 * i); i1 < (8 * (i + 1)); i1 = i1 + 1) + doa_buf[i1] = di_x[i1]; + + for (i_p = i; i_p < (i + 1); i_p = i_p + 1) + dopa_buf[i_p] = di_x[i_p]; + + end + + end // for (i = 0; i <= 3; i = i + 1) + + if (READ_WIDTH_A != 0) + $display("Functional warning at simulation time (%.3f ns) : ARAMB36_INTERNAL (%m) port A is in WRITE_FIRST mode. The write will be successful, however DOA shows only the enabled newly written byte(s). The other byte values on DOA are unknown until the next CLKA cycle and all bits of WEA is set to all 1s or 0s.", $time/1000.0); + + end // if (WRITE_WIDTH_A == 36) + + end // if ((WRITE_WIDTH_A == 18 && !(wea_in[1:0] === 2'b00 || wea_in[1:0] === 2'b11)) || (WRITE_WIDTH_A == 36 && !(wea_in[3:0] === 4'b0000 || wea_in[3:0] === 4'b1111))) + end // if (wr_mode_a == 2'b00 && BRAM_SIZE == 16) + + doa_out <= doa_buf; + dopa_out <= dopa_buf; + + end + + end + + + // writing outputs of port B + if (enb_in && (rising_clkb || viol_time != 0)) begin + + if ((ssrb_in === 1'b0 || DOB_REG == 1) && (wr_mode_b != 2'b10 || (WRITE_WIDTH_B <= 9 && web_in[0] === 1'b0) || (WRITE_WIDTH_B == 18 && web_in[1:0] === 2'b00) || (WRITE_WIDTH_B == 36 && web_in[3:0] === 4'b0000) || (WRITE_WIDTH_B == 72 && web_in[7:0] === 8'h00))) begin + + // Virtex4 feature + if (wr_mode_b == 2'b00 && BRAM_SIZE == 16) begin + + if ((WRITE_WIDTH_B == 18 && !(web_in[1:0] === 2'b00 || web_in[1:0] === 2'b11)) || (WRITE_WIDTH_B == 36 && !(web_in[3:0] === 4'b0000 || web_in[3:0] === 4'b1111))) begin + + if (WRITE_WIDTH_B != READ_WIDTH_B) begin + + dob_buf[rb_width-1:0] = di_x[rb_width-1:0]; + + if (READ_WIDTH_B >= 9) + dopb_buf[rb_widthp-1:0] = di_x[rb_widthp-1:0]; + + if (READ_WIDTH_B != 0) + $display("Functional warning at simulation time (%.3f ns) : ARAMB36_INTERNAL (%m) port B is in WRITE_FIRST mode with parameter WRITE_WIDTH_B = %d, which is different from READ_WIDTH_B = %d. The write will be successful however the read value of all bits on port B is unknown until the next CLKB cycle and all bits of WEB is set to all 1s or 0s.", $time/1000.0, WRITE_WIDTH_B, READ_WIDTH_B); + + end + else if (WRITE_WIDTH_B == 18) begin + for (i = 0; i <= 1; i = i + 1) begin + + if (web_in[i] === 1'b0) begin + for (i1 = (8 * i); i1 < (8 * (i + 1)); i1 = i1 + 1) + dob_buf[i1] = di_x[i1]; + + for (i_p = i; i_p < (i + 1); i_p = i_p + 1) + dopb_buf[i_p] = di_x[i_p]; + + end + + end // for (i = 0; i <= 1; i = i + 1) + + if (READ_WIDTH_B != 0) + $display("Functional warning at simulation time (%.3f ns) : ARAMB36_INTERNAL (%m) port B is in WRITE_FIRST mode. The write will be successful, however DOB shows only the enabled newly written byte(s). The other byte values on DOB are unknown until the next CLKB cycle and all bits of WEB is set to all 1s or 0s.", $time/1000.0); + + end // if (WRITE_WIDTH_B == 18) + else if (WRITE_WIDTH_B == 36) begin + for (i = 0; i <= 3; i = i + 1) begin + + if (web_in[i] === 1'b0) begin + for (i1 = (8 * i); i1 < (8 * (i + 1)); i1 = i1 + 1) + dob_buf[i1] = di_x[i1]; + + for (i_p = i; i_p < (i + 1); i_p = i_p + 1) + dopb_buf[i_p] = di_x[i_p]; + + end + + end // for (i = 0; i <= 3; i = i + 1) + + if (READ_WIDTH_B != 0) + $display("Functional warning at simulation time (%.3f ns) : ARAMB36_INTERNAL (%m) port B is in WRITE_FIRST mode. The write will be successful, however DOB shows only the enabled newly written byte(s). The other byte values on DOB are unknown until the next CLKB cycle and all bits of WEB is set to all 1s or 0s.", $time/1000.0); + + end // if (WRITE_WIDTH_B == 36) + + end // if ((WRITE_WIDTH_B == 18 && !(web_in[1:0] === 2'b00 || web_in[1:0] === 2'b11)) || (WRITE_WIDTH_B == 36 && !(web_in[3:0] === 4'b0000 || web_in[3:0] === 4'b1111))) + end // if (wr_mode_b == 2'b00 && BRAM_SIZE == 16) + + dob_out <= dob_buf; + dopb_out <= dopb_buf; + + end + + end + + + viol_time = 0; + rising_clka = 0; + rising_clkb = 0; + viol_type = 2'b00; + col_wr_wr_msg = 1; + col_wra_rdb_msg = 1; + col_wrb_rda_msg = 1; + + end // always @ (posedge rising_clka or posedge rising_clkb) + + + // ********* Cascade Port A ******** + always @(posedge clka_in or cascadeinlata_in or addra_in_15_reg or doa_out or dopa_out) begin + + if (cascade_a[1] == 1'b1 && addra_in_15_reg == 1'b1) begin + doa_out_mux[0] = cascadeinlata_in; + end + else begin + doa_out_mux = doa_out; + dopa_out_mux = dopa_out; + end + + end + + + always @(posedge regclka_in or cascadeinrega_in or addra_in_15_reg1 or doa_outreg or dopa_outreg) begin + + if (cascade_a[1] == 1'b1 && addra_in_15_reg1 == 1'b1) begin + doa_outreg_mux[0] = cascadeinrega_in; + end + else begin + doa_outreg_mux = doa_outreg; + dopa_outreg_mux = dopa_outreg; + end + + end + + + // ********* Cascade Port B ******** + always @(posedge clkb_in or cascadeinlatb_in or addrb_in_15_reg or dob_out or dopb_out) begin + + if (cascade_b[1] == 1'b1 && addrb_in_15_reg == 1'b1) begin + dob_out_mux[0] = cascadeinlatb_in; + end + else begin + dob_out_mux = dob_out; + dopb_out_mux = dopb_out; + end + + end + + + always @(posedge regclkb_in or cascadeinregb_in or addrb_in_15_reg1 or dob_outreg or dopb_outreg) begin + + if (cascade_b[1] == 1'b1 && addrb_in_15_reg1 == 1'b1) begin + dob_outreg_mux[0] = cascadeinregb_in; + end + else begin + dob_outreg_mux = dob_outreg; + dopb_outreg_mux = dopb_outreg; + end + + end + + + // ***** Output Registers **** Port A ***** + always @(posedge regclka_in or posedge gsr_in) begin + + if (DOA_REG == 1) begin + + if (gsr_in == 1'b1) begin + + dbiterr_outreg <= 0; + sbiterr_outreg <= 0; + doa_outreg <= INIT_A[0 +: ra_width]; + + if (ra_width >= 8) + dopa_outreg <= INIT_A[ra_width +: ra_widthp]; + + end + else if (gsr_in == 1'b0) begin + + dbiterr_outreg <= dbiterr_out; + sbiterr_outreg <= sbiterr_out; + + if (regcea_in == 1'b1) begin + if (ssra_in == 1'b1) begin + + doa_outreg <= SRVAL_A[0 +: ra_width]; + + if (ra_width >= 8) + dopa_outreg <= SRVAL_A[ra_width +: ra_widthp]; + + end + else if (ssra_in == 1'b0) begin + + doa_outreg <= doa_out; + dopa_outreg <= dopa_out; + + end + end // if (regcea_in == 1'b1) + + end // if (gsr_in == 1'b0) + + end // if (DOA_REG == 1) + + end // always @ (posedge clka_in or posedge gsr_in) + + + always @(temp_wire or doa_out_mux or dopa_out_mux or doa_outreg_mux or dopa_outreg_mux or dbiterr_out or dbiterr_outreg or sbiterr_out or sbiterr_outreg) begin + + case (DOA_REG) + + 0 : begin + dbiterr_out_out = dbiterr_out; + sbiterr_out_out = sbiterr_out; + doa_out_out = doa_out_mux; + dopa_out_out = dopa_out_mux; + end + 1 : begin + dbiterr_out_out = dbiterr_outreg; + sbiterr_out_out = sbiterr_outreg; + doa_out_out = doa_outreg_mux; + dopa_out_out = dopa_outreg_mux; + end + default : begin + $display("Attribute Syntax Error : The attribute DOA_REG on ARAMB36_INTERNAL instance %m is set to %2d. Legal values for this attribute are 0 or 1.", DOA_REG); + $finish; + end + + endcase + + end // always @ (doa_out_mux or dopa_out_mux or doa_outreg_mux or dopa_outreg_mux or dbiterr_out or dbiterr_outreg or sbiterr_out or sbiterr_outreg) + + +// ***** Output Registers **** Port B ***** + always @(posedge regclkb_in or posedge gsr_in) begin + + if (DOB_REG == 1) begin + + if (gsr_in == 1'b1) begin + + dob_outreg <= INIT_B[0 +: rb_width]; + + if (rb_width >= 8) + dopb_outreg <= INIT_B[rb_width +: rb_widthp]; + + end + else if (gsr_in == 1'b0) begin + + if (regceb_in == 1'b1) begin + if (ssrb_in == 1'b1) begin + + dob_outreg <= SRVAL_B[0 +: rb_width]; + + if (rb_width >= 8) + dopb_outreg <= SRVAL_B[rb_width +: rb_widthp]; + + end + else if (ssrb_in == 1'b0) begin + + dob_outreg <= dob_out; + dopb_outreg <= dopb_out; + + end + end // if (regceb_in == 1'b1) + + end // if (gsr_in == 1'b0) + + end // if (DOB_REG == 1) + + end // always @ (posedge clkb_in or posedge gsr_in) + + + always @(temp_wire or dob_out_mux or dopb_out_mux or dob_outreg_mux or dopb_outreg_mux) begin + + case (DOB_REG) + + 0 : begin + dob_out_out = dob_out_mux; + dopb_out_out = dopb_out_mux; + end + 1 : begin + dob_out_out = dob_outreg_mux; + dopb_out_out = dopb_outreg_mux; + end + default : begin + $display("Attribute Syntax Error : The attribute DOB_REG on ARAMB36_INTERNAL instance %m is set to %2d. Legal values for this attribute are 0 or 1.", DOB_REG); + $finish; + end + + endcase + + end // always @ (dob_out_mux or dopb_out_mux or dob_outreg_mux or dopb_outreg_mux) + + + end + endgenerate + // end SAFE mode + + +/*************************** FAST mode *********************************/ + generate if (SIM_MODE == "FAST") begin + + assign DOA = doa_out_out; + assign DOB = dob_out_out; + assign DOPA = dopa_out_out; + assign DOPB = dopb_out_out; + assign CASCADEOUTLATA = doa_out[0]; + assign CASCADEOUTLATB = dob_out[0]; + assign CASCADEOUTREGA = doa_outreg[0]; + assign CASCADEOUTREGB = dob_outreg[0]; + + +/******************************************** task and function **************************************/ + + task task_ram; + + input we; + input [7:0] di; + input dip; + inout [7:0] mem_task; + inout memp_task; + + begin + + if (we == 1'b1) begin + + mem_task = di; + + if (width >= 8) + memp_task = dip; + end + end + + endtask // task_ram + + + task task_wr_ram_a; + + input [7:0] wea_tmp; + input [63:0] dia_tmp; + input [7:0] dipa_tmp; + input [15:0] addra_tmp; + + begin + + case (wa_width) + + 1, 2, 4 : begin + + if (wa_width >= width) + task_ram (wea_tmp[0], dia_tmp[wa_width-1:0], 1'b0, mem[addra_tmp[14:addra_lbit_124]], junk1); + else + task_ram (wea_tmp[0], dia_tmp[wa_width-1:0], 1'b0, mem[addra_tmp[14:addra_bit_124+1]][(addra_tmp[addra_bit_124:addra_lbit_124] * wa_width) +: wa_width], junk1); + + end + 8 : begin + + if (wa_width >= width) + task_ram (wea_tmp[0], dia_tmp[7:0], dipa_tmp[0], mem[addra_tmp[14:3]], memp[addra_tmp[14:3]]); + else + task_ram (wea_tmp[0], dia_tmp[7:0], dipa_tmp[0], mem[addra_tmp[14:addra_bit_8+1]][(addra_tmp[addra_bit_8:3] * 8) +: 8], memp[addra_tmp[14:addra_bit_8+1]][(addra_tmp[addra_bit_8:3] * 1) +: 1]); + + end + 16 : begin + + if (wa_width >= width) begin + task_ram (wea_tmp[0], dia_tmp[7:0], dipa_tmp[0], mem[addra_tmp[14:4]][0 +: 8], memp[addra_tmp[14:4]][0]); + task_ram (wea_tmp[1], dia_tmp[15:8], dipa_tmp[1], mem[addra_tmp[14:4]][8 +: 8], memp[addra_tmp[14:4]][1]); + end + else begin + task_ram (wea_tmp[0], dia_tmp[7:0], dipa_tmp[0], mem[addra_tmp[14:addra_bit_16+1]][(addra_tmp[addra_bit_16:4] * 16) +: 8], memp[addra_tmp[14:addra_bit_16+1]][(addra_tmp[addra_bit_16:4] * 2) +: 1]); + task_ram (wea_tmp[1], dia_tmp[15:8], dipa_tmp[1], mem[addra_tmp[14:addra_bit_16+1]][((addra_tmp[addra_bit_16:4] * 16) + 8) +: 8], memp[addra_tmp[14:addra_bit_16+1]][((addra_tmp[addra_bit_16:4] * 2) + 1) +: 1]); + end // else: !if(wa_width >= wb_width) + + end // case: 16 + 32 : begin + + task_ram (wea_tmp[0], dia_tmp[7:0], dipa_tmp[0], mem[addra_tmp[14:5]][0 +: 8], memp[addra_tmp[14:5]][0]); + task_ram (wea_tmp[1], dia_tmp[15:8], dipa_tmp[1], mem[addra_tmp[14:5]][8 +: 8], memp[addra_tmp[14:5]][1]); + task_ram (wea_tmp[2], dia_tmp[23:16], dipa_tmp[2], mem[addra_tmp[14:5]][16 +: 8], memp[addra_tmp[14:5]][2]); + task_ram (wea_tmp[3], dia_tmp[31:24], dipa_tmp[3], mem[addra_tmp[14:5]][24 +: 8], memp[addra_tmp[14:5]][3]); + + end // case: 32 + endcase // case(wa_width) + end + + endtask // task_wr_ram_a + + + task task_wr_ram_b; + + input [7:0] web_tmp; + input [63:0] dib_tmp; + input [7:0] dipb_tmp; + input [15:0] addrb_tmp; + + begin + + case (wb_width) + + 1, 2, 4 : begin + + if (wb_width >= width) + task_ram (web_tmp[0], dib_tmp[wb_width-1:0], 1'b0, mem[addrb_tmp[14:addrb_lbit_124]], junk1); + else + task_ram (web_tmp[0], dib_tmp[wb_width-1:0], 1'b0, mem[addrb_tmp[14:addrb_bit_124+1]][(addrb_tmp[addrb_bit_124:addrb_lbit_124] * wb_width) +: wb_width], junk1); + end + 8 : begin + + if (wb_width >= width) + task_ram (web_tmp[0], dib_tmp[7:0], dipb_tmp[0], mem[addrb_tmp[14:3]], memp[addrb_tmp[14:3]]); + else + task_ram (web_tmp[0], dib_tmp[7:0], dipb_tmp[0], mem[addrb_tmp[14:addrb_bit_8+1]][(addrb_tmp[addrb_bit_8:3] * 8) +: 8], memp[addrb_tmp[14:addrb_bit_8+1]][(addrb_tmp[addrb_bit_8:3] * 1) +: 1]); + + end + 16 : begin + + if (wb_width >= width) begin + task_ram (web_tmp[0], dib_tmp[7:0], dipb_tmp[0], mem[addrb_tmp[14:4]][0 +: 8], memp[addrb_tmp[14:4]][0]); + task_ram (web_tmp[1], dib_tmp[15:8], dipb_tmp[1], mem[addrb_tmp[14:4]][8 +: 8], memp[addrb_tmp[14:4]][1]); + end + else begin + task_ram (web_tmp[0], dib_tmp[7:0], dipb_tmp[0], mem[addrb_tmp[14:addrb_bit_16+1]][(addrb_tmp[addrb_bit_16:4] * 16) +: 8], memp[addrb_tmp[14:addrb_bit_16+1]][(addrb_tmp[addrb_bit_16:4] * 2) +: 1]); + task_ram (web_tmp[1], dib_tmp[15:8], dipb_tmp[1], mem[addrb_tmp[14:addrb_bit_16+1]][((addrb_tmp[addrb_bit_16:4] * 16) + 8) +: 8], memp[addrb_tmp[14:addrb_bit_16+1]][((addrb_tmp[addrb_bit_16:4] * 2) + 1) +: 1]); + end + + end // case: 16 + 32 : begin + + task_ram (web_tmp[0], dib_tmp[7:0], dipb_tmp[0], mem[addrb_tmp[14:5]][0 +: 8], memp[addrb_tmp[14:5]][0]); + task_ram (web_tmp[1], dib_tmp[15:8], dipb_tmp[1], mem[addrb_tmp[14:5]][8 +: 8], memp[addrb_tmp[14:5]][1]); + task_ram (web_tmp[2], dib_tmp[23:16], dipb_tmp[2], mem[addrb_tmp[14:5]][16 +: 8], memp[addrb_tmp[14:5]][2]); + task_ram (web_tmp[3], dib_tmp[31:24], dipb_tmp[3], mem[addrb_tmp[14:5]][24 +: 8], memp[addrb_tmp[14:5]][3]); + + end // case: 32 + 64 : begin + + task_ram (web_tmp[0], dib_tmp[7:0], dipb_tmp[0], mem[addrb_tmp[14:6]][0 +: 8], memp[addrb_tmp[14:6]][0]); + task_ram (web_tmp[1], dib_tmp[15:8], dipb_tmp[1], mem[addrb_tmp[14:6]][8 +: 8], memp[addrb_tmp[14:6]][1]); + task_ram (web_tmp[2], dib_tmp[23:16], dipb_tmp[2], mem[addrb_tmp[14:6]][16 +: 8], memp[addrb_tmp[14:6]][2]); + task_ram (web_tmp[3], dib_tmp[31:24], dipb_tmp[3], mem[addrb_tmp[14:6]][24 +: 8], memp[addrb_tmp[14:6]][3]); + task_ram (web_tmp[4], dib_tmp[39:32], dipb_tmp[4], mem[addrb_tmp[14:6]][32 +: 8], memp[addrb_tmp[14:6]][4]); + task_ram (web_tmp[5], dib_tmp[47:40], dipb_tmp[5], mem[addrb_tmp[14:6]][40 +: 8], memp[addrb_tmp[14:6]][5]); + task_ram (web_tmp[6], dib_tmp[55:48], dipb_tmp[6], mem[addrb_tmp[14:6]][48 +: 8], memp[addrb_tmp[14:6]][6]); + task_ram (web_tmp[7], dib_tmp[63:56], dipb_tmp[7], mem[addrb_tmp[14:6]][56 +: 8], memp[addrb_tmp[14:6]][7]); + + end // case: 64 + endcase // case(wb_width) + end + + endtask // task_wr_ram_b + + + task task_rd_ram_a; + + input [15:0] addra_tmp; + inout [63:0] doa_tmp; + inout [7:0] dopa_tmp; + + begin + + case (ra_width) + 1, 2, 4 : begin + if (ra_width >= width) + doa_tmp = mem[addra_tmp[14:r_addra_lbit_124]]; + + else + doa_tmp = mem[addra_tmp[14:r_addra_bit_124+1]][(addra_tmp[r_addra_bit_124:r_addra_lbit_124] * ra_width) +: ra_width]; + end + 8 : begin + if (ra_width >= width) begin + doa_tmp = mem[addra_tmp[14:3]]; + dopa_tmp = memp[addra_tmp[14:3]]; + end + else begin + doa_tmp = mem[addra_tmp[14:r_addra_bit_8+1]][(addra_tmp[r_addra_bit_8:3] * 8) +: 8]; + dopa_tmp = memp[addra_tmp[14:r_addra_bit_8+1]][(addra_tmp[r_addra_bit_8:3] * 1) +: 1]; + end + end + 16 : begin + if (ra_width >= width) begin + doa_tmp = mem[addra_tmp[14:4]]; + dopa_tmp = memp[addra_tmp[14:4]]; + end + else begin + doa_tmp = mem[addra_tmp[14:r_addra_bit_16+1]][(addra_tmp[r_addra_bit_16:4] * 16) +: 16]; + dopa_tmp = memp[addra_tmp[14:r_addra_bit_16+1]][(addra_tmp[r_addra_bit_16:4] * 2) +: 2]; + end + end + 32 : begin + if (ra_width >= width) begin + doa_tmp = mem[addra_tmp[14:5]]; + dopa_tmp = memp[addra_tmp[14:5]]; + end + end + 64 : begin + if (ra_width >= width) begin + doa_tmp = mem[addra_tmp[14:6]]; + dopa_tmp = memp[addra_tmp[14:6]]; + end + end + endcase // case(ra_width) + + end + endtask // task_rd_ram_a + + + task task_rd_ram_b; + + input [15:0] addrb_tmp; + inout [31:0] dob_tmp; + inout [3:0] dopb_tmp; + + begin + + case (rb_width) + 1, 2, 4 : begin + if (rb_width >= width) + dob_tmp = mem[addrb_tmp[14:r_addrb_lbit_124]]; + else + dob_tmp = mem[addrb_tmp[14:r_addrb_bit_124+1]][(addrb_tmp[r_addrb_bit_124:r_addrb_lbit_124] * rb_width) +: rb_width]; + end + 8 : begin + if (rb_width >= width) begin + dob_tmp = mem[addrb_tmp[14:3]]; + dopb_tmp = memp[addrb_tmp[14:3]]; + end + else begin + dob_tmp = mem[addrb_tmp[14:r_addrb_bit_8+1]][(addrb_tmp[r_addrb_bit_8:3] * 8) +: 8]; + dopb_tmp = memp[addrb_tmp[14:r_addrb_bit_8+1]][(addrb_tmp[r_addrb_bit_8:3] * 1) +: 1]; + end + end + 16 : begin + if (rb_width >= width) begin + dob_tmp = mem[addrb_tmp[14:4]]; + dopb_tmp = memp[addrb_tmp[14:4]]; + end + else begin + dob_tmp = mem[addrb_tmp[14:r_addrb_bit_16+1]][(addrb_tmp[r_addrb_bit_16:4] * 16) +: 16]; + dopb_tmp = memp[addrb_tmp[14:r_addrb_bit_16+1]][(addrb_tmp[r_addrb_bit_16:4] * 2) +: 2]; + end + end + 32 : begin + dob_tmp = mem[addrb_tmp[14:5]]; + dopb_tmp = memp[addrb_tmp[14:5]]; + end + + endcase + end + endtask // task_rd_ram_b + +/******************************************** END task and function **************************************/ + + + initial begin + + case (WRITE_MODE_A) + "WRITE_FIRST" : wr_mode_a <= 2'b00; + "READ_FIRST" : wr_mode_a <= 2'b01; + "NO_CHANGE" : wr_mode_a <= 2'b10; + endcase + + + case (WRITE_MODE_B) + "WRITE_FIRST" : wr_mode_b <= 2'b00; + "READ_FIRST" : wr_mode_b <= 2'b01; + "NO_CHANGE" : wr_mode_b <= 2'b10; + endcase + + end // initial begin + + + always @(GSR) + if (GSR) begin + + assign doa_out_out = INIT_A[0 +: ra_width]; + assign doa_out = INIT_A[0 +: ra_width]; + + if (ra_width >= 8) begin + assign dopa_out_out = INIT_A[ra_width +: ra_widthp]; + assign dopa_out = INIT_A[ra_width +: ra_widthp]; + end + + assign dob_out_out = INIT_B[0 +: rb_width]; + assign dob_out = INIT_B[0 +: rb_width]; + + if (rb_width >= 8) begin + assign dopb_out_out = INIT_B[rb_width +: rb_widthp]; + assign dopb_out = INIT_B[rb_width +: rb_widthp]; + end + + assign dbiterr_out = 0; + assign sbiterr_out = 0; + + end + else begin + deassign doa_out_out; + deassign dopa_out_out; + deassign dob_out_out; + deassign dopb_out_out; + deassign doa_out; + deassign dopa_out; + deassign dob_out; + deassign dopb_out; + deassign dbiterr_out; + deassign sbiterr_out; + end // else: !if(GSR) + + +/**************************** Port A ****************************************/ + always @(posedge CLKA) begin + + if (GSR == 1'b0 && ENA == 1'b1) begin + + if (SSRA == 1'b1 && DOA_REG == 0) begin + doa_buf = SRVAL_A[0 +: ra_width]; + doa_out = SRVAL_A[0 +: ra_width]; + + if (ra_width >= 8) begin + dopa_buf = SRVAL_A[ra_width +: ra_widthp]; + dopa_out = SRVAL_A[ra_width +: ra_widthp]; + end + end + + if ((wr_mode_a == 2'b01 && (SSRA === 1'b0 || DOA_REG == 1))) begin + task_rd_ram_a (ADDRA, doa_buf, dopa_buf); + end + + + task_wr_ram_a (WEA, DIA, DIPA, ADDRA); + + + if ((wr_mode_a != 2'b01 && (SSRA === 1'b0 || DOA_REG == 1))) + task_rd_ram_a (ADDRA, doa_buf, dopa_buf); + + + if ((SSRA === 1'b0 || DOA_REG == 1) && (wr_mode_a != 2'b10 || (WRITE_WIDTH_A <= 9 && WEA[0] === 1'b0) || (WRITE_WIDTH_A == 18 && WEA[1:0] === 2'b00) || ((WRITE_WIDTH_A == 36 || WRITE_WIDTH_A == 72) && WEA[3:0] === 4'b0000))) begin + + doa_out <= doa_buf; + dopa_out <= dopa_buf; + + end + + end // if (ENA == 1'b1) + + end // always @ (posedge CLKA) + // end of port A + + +/************************************** port B ***************************************************************/ + always @(posedge CLKB) begin + + if (GSR == 1'b0 && ENB == 1'b1) begin + if (SSRB == 1'b1 && DOB_REG == 0) begin + + dob_buf = SRVAL_B[0 +: rb_width]; + dob_out = SRVAL_B[0 +: rb_width]; + + if (rb_width >= 8) begin + dopb_buf = SRVAL_B[rb_width +: rb_widthp]; + dopb_out = SRVAL_B[rb_width +: rb_widthp]; + end + + end + + + if (wr_mode_b == 2'b01 && (SSRB === 1'b0 || DOB_REG == 1)) + task_rd_ram_b (ADDRB, dob_buf, dopb_buf); + + + task_wr_ram_b (WEB, DIB, DIPB, ADDRB); + + + if (wr_mode_b != 2'b01 && (SSRB === 1'b0 || DOB_REG == 1)) + task_rd_ram_b (ADDRB, dob_buf, dopb_buf); + + + if ((SSRB === 1'b0 || DOB_REG == 1) && (wr_mode_b != 2'b10 || (WRITE_WIDTH_B <= 9 && WEB[0] === 1'b0) || (WRITE_WIDTH_B == 18 && WEB[1:0] === 2'b00) || (WRITE_WIDTH_B == 36 && WEB[3:0] === 4'b0000) || (WRITE_WIDTH_B == 72 && WEB[7:0] === 8'h00))) begin + + dob_out <= dob_buf; + dopb_out <= dopb_buf; + + end // if ((SSRB === 1'b0 || DOB_REG == 1) && (wr_mode_b != 2'b10 || (WRITE_WIDTH_B <= 9 && WEB[0] === 1'b0) || (WRITE_WIDTH_B == 18 && WEB[1:0] === 2'b00) || (WRITE_WIDTH_B == 36 && WEB[3:0] === 4'b0000) || (WRITE_WIDTH_B == 72 && WEB[7:0] === 8'h00))) + + end // if (ENB == 1'b1) + + end // always @ (posedge CLKB) + // end of port B + + + // ***** Output Registers **** Port A ***** + always @(posedge REGCLKA or posedge GSR) begin + + if (DOA_REG == 1) begin + + if (GSR == 1'b1) begin + + dbiterr_outreg <= 0; + sbiterr_outreg <= 0; + doa_outreg <= INIT_A[0 +: ra_width]; + + if (ra_width >= 8) + dopa_outreg <= INIT_A[ra_width +: ra_widthp]; + + end + else if (GSR == 1'b0) begin + + if (REGCEA == 1'b1) begin + if (SSRA == 1'b1) begin + + doa_outreg <= SRVAL_A[0 +: ra_width]; + + if (ra_width >= 8) + dopa_outreg <= SRVAL_A[ra_width +: ra_widthp]; + + end + else if (SSRA == 1'b0) begin + + doa_outreg <= doa_out; + dopa_outreg <= dopa_out; + + end + + end // if (REGCEA == 1'b1) + + end // if (GSR == 1'b0) + + end // if (DOA_REG == 1) + + end // always @ (posedge REGCLKA or posedge GSR) + + + always @(doa_out or dopa_out or doa_outreg or dopa_outreg) begin + + case (DOA_REG) + + 0 : begin + doa_out_out = doa_out; + dopa_out_out = dopa_out; + end + 1 : begin + doa_out_out = doa_outreg; + dopa_out_out = dopa_outreg; + end + + endcase + + end // always @ (doa_out or dopa_out or doa_outreg or dopa_outreg) + + +// ***** Output Registers **** Port B ***** + always @(posedge REGCLKB or posedge GSR) begin + + if (DOB_REG == 1) begin + + if (GSR == 1'b1) begin + + dob_outreg <= INIT_B[0 +: rb_width]; + + if (rb_width >= 8) + dopb_outreg <= INIT_B[rb_width +: rb_widthp]; + + end + else if (GSR == 1'b0) begin + + if (REGCEB == 1'b1) begin + if (SSRB == 1'b1) begin + + dob_outreg <= SRVAL_B[0 +: rb_width]; + + if (rb_width >= 8) + dopb_outreg <= SRVAL_B[rb_width +: rb_widthp]; + + end + else if (SSRB == 1'b0) begin + + dob_outreg <= dob_out; + dopb_outreg <= dopb_out; + + end + + end // if (REGCEB == 1'b1) + + end // if (GSR == 1'b0) + + end // if (DOB_REG == 1) + + end // always @ (posedge REGCLKB or posedge GSR) + + + always @(dob_out or dopb_out or dob_outreg or dopb_outreg) begin + + case (DOB_REG) + + 0 : begin + dob_out_out = dob_out; + dopb_out_out = dopb_out; + end + 1 : begin + dob_out_out = dob_outreg; + dopb_out_out = dopb_outreg; + end + + endcase + + end // always @ (dob_out or dopb_out or dob_outreg or dopb_outreg) + + + end + endgenerate + // end FAST mode + +endmodule // ARAMB36_INTERNAL diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/AUTOBUF.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/AUTOBUF.v new file mode 100644 index 0000000..fc8d438 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/AUTOBUF.v @@ -0,0 +1,57 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/blanc/AUTOBUF.v,v 1.3 2009/08/21 23:55:39 harikr Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Clock Buffer +// /___/ /\ Filename : AUTOBUF.v +// \ \ / \ Timestamp : +// \___\/\___\ +// +// Revision: +// 04/08/08 - Initial version. +// 07/23/09 - Add more attrute values (CR521811) +// End Revision + +`timescale 1 ps / 1 ps + + +module AUTOBUF (O, I); + + parameter BUFFER_TYPE = "AUTO"; + + output O; + + input I; + + initial begin + case (BUFFER_TYPE) + "AUTO" : ; + "BUF" : ; + "BUFG" : ; + "BUFGP" : ; + "BUFH" : ; + "BUFIO" : ; + "BUFIO2" : ; + "BUFIO2FB" : ; + "BUFR" : ; + "IBUF" : ; + "IBUFG" : ; + "NONE" : ; + "OBUF" : ; + default : begin + $display("Attribute Syntax Error : The Attribute BUFFER_TYPE on AUTOBUF instance %m is set to %s. Legal values for this attribute are AUTO, BUF, BUFG, BUFGP, BUFH, BUFIO, BUFIO2, BUFIO2FB, BUFR, IBUF, IBUFG, NONE, and OBUF.", BUFFER_TYPE); + end + endcase + end + + buf B1 (O, I); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/BSCAN_FPGACORE.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/BSCAN_FPGACORE.v new file mode 100644 index 0000000..1eb3a55 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/BSCAN_FPGACORE.v @@ -0,0 +1,40 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/BSCAN_FPGACORE.v,v 1.6 2007/05/23 21:43:33 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Boundary Scan Logic Control Circuit for FPGACORE +// /___/ /\ Filename : BSCAN_FPGACORE.v +// \ \ / \ Timestamp : Thu Mar 25 16:42:13 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. + +`timescale 1 ps / 1 ps + + +module BSCAN_FPGACORE (CAPTURE, DRCK1, DRCK2, RESET, SEL1, SEL2, SHIFT, TDI, UPDATE, TDO1, TDO2); + + input TDO1, TDO2; + + output CAPTURE, DRCK1, DRCK2, RESET, SEL1, SEL2, SHIFT, TDI, UPDATE; + + pulldown (DRCK1); + pulldown (DRCK2); + pulldown (RESET); + pulldown (SEL1); + pulldown (SEL2); + pulldown (SHIFT); + pulldown (TDI); + pulldown (UPDATE); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/BSCAN_SPARTAN3.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/BSCAN_SPARTAN3.v new file mode 100644 index 0000000..f5a0821 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/BSCAN_SPARTAN3.v @@ -0,0 +1,40 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/BSCAN_SPARTAN3.v,v 1.6 2007/05/23 21:43:33 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Boundary Scan Logic Control Circuit for SPARTAN3 +// /___/ /\ Filename : BSCAN_SPARTAN3.v +// \ \ / \ Timestamp : Thu Mar 25 16:42:13 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. + +`timescale 1 ps / 1 ps + + +module BSCAN_SPARTAN3 (CAPTURE, DRCK1, DRCK2, RESET, SEL1, SEL2, SHIFT, TDI, UPDATE, TDO1, TDO2); + + input TDO1, TDO2; + + output CAPTURE, DRCK1, DRCK2, RESET, SEL1, SEL2, SHIFT, TDI, UPDATE; + + pulldown (DRCK1); + pulldown (DRCK2); + pulldown (RESET); + pulldown (SEL1); + pulldown (SEL2); + pulldown (SHIFT); + pulldown (TDI); + pulldown (UPDATE); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/BSCAN_SPARTAN3A.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/BSCAN_SPARTAN3A.v new file mode 100644 index 0000000..4e82e96 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/BSCAN_SPARTAN3A.v @@ -0,0 +1,72 @@ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Boundary Scan Logic Control Circuit for SPARTAN3A +// /___/ /\ Filename : BSCAN_SPARTAN3A.v +// \ \ / \ Timestamp : Tue Jul 5 09:41:40 PDT 2005 +// \___\/\___\ +// +// Revision: +// 07/05/05 - Initial version. +// 01/24/06 - CR 224623, added TCK and TMS ports +// End Revision + +`timescale 1 ps / 1 ps + +module BSCAN_SPARTAN3A (CAPTURE, DRCK1, DRCK2, RESET, SEL1, SEL2, SHIFT, TCK, TDI, TMS, UPDATE, TDO1, TDO2); + + output CAPTURE, DRCK1, DRCK2, RESET, SEL1, SEL2, SHIFT, TCK, TDI, TMS, UPDATE; + + input TDO1, TDO2; + + + + pulldown (CAPTURE); + pulldown (DRCK1); + pulldown (DRCK2); + pulldown (RESET); + pulldown (SEL1); + pulldown (SEL2); + pulldown (SHIFT); + pulldown (TCK); + pulldown (TDI); + pulldown (TMS); + pulldown (UPDATE); + +//--#################################################################### +//--##### Output ### +//--#################################################################### + assign CAPTURE = glbl.JTAG_CAPTURE_GLBL; + + assign #1 DRCK1 = ((glbl.JTAG_SEL1_GLBL & !glbl.JTAG_SHIFT_GLBL & !glbl.JTAG_CAPTURE_GLBL) + || + (glbl.JTAG_SEL1_GLBL & glbl.JTAG_SHIFT_GLBL & glbl.JTAG_TCK_GLBL) + || + (glbl.JTAG_SEL1_GLBL & glbl.JTAG_CAPTURE_GLBL & glbl.JTAG_TCK_GLBL)); + assign #1 DRCK2 = ((glbl.JTAG_SEL2_GLBL & !glbl.JTAG_SHIFT_GLBL & !glbl.JTAG_CAPTURE_GLBL) + || + (glbl.JTAG_SEL2_GLBL & glbl.JTAG_SHIFT_GLBL & glbl.JTAG_TCK_GLBL) + || + (glbl.JTAG_SEL2_GLBL & glbl.JTAG_CAPTURE_GLBL & glbl.JTAG_TCK_GLBL)); + assign RESET = glbl.JTAG_RESET_GLBL; + assign SEL1 = glbl.JTAG_SEL1_GLBL; + assign SEL2 = glbl.JTAG_SEL2_GLBL; + assign SHIFT = glbl.JTAG_SHIFT_GLBL; + assign TCK = glbl.JTAG_TCK_GLBL; + assign TDI = glbl.JTAG_TDI_GLBL; + assign TMS = glbl.JTAG_TMS_GLBL; + assign UPDATE = glbl.JTAG_UPDATE_GLBL; + + always@(TDO1, TDO2) begin + glbl.JTAG_USER_TDO1_GLBL <= TDO1; + glbl.JTAG_USER_TDO2_GLBL <= TDO2; + end + + +endmodule // BSCAN_SPARTAN3A diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/BSCAN_SPARTAN6.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/BSCAN_SPARTAN6.v new file mode 100644 index 0000000..3e5e7b8 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/BSCAN_SPARTAN6.v @@ -0,0 +1,87 @@ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Boundary Scan Logic Control Circuit for SPARTAN6 +// /___/ /\ Filename : BSCAN_SPARTAN6.v +// \ \ / \ Timestamp : Fri Jan 16 14:48:42 PST 2009 +// \___\/\___\ +// +// Revision: +// 01/16/09 - Initial version. +// End Revision + +`timescale 1 ps / 1 ps + + +module BSCAN_SPARTAN6 (CAPTURE, DRCK, RESET, RUNTEST, SEL, SHIFT, TCK, TDI, TMS, UPDATE, TDO); + + output CAPTURE, DRCK, RESET, RUNTEST, SEL, SHIFT, TCK, TDI, TMS, UPDATE; + + input TDO; + + reg SEL_zd; + + parameter integer JTAG_CHAIN = 1; + + pulldown (DRCK); + pulldown (RESET); + pulldown (SEL); + pulldown (SHIFT); + pulldown (TDI); + pulldown (UPDATE); + +//--#################################################################### +//--##### Initialization ### +//--#################################################################### + initial begin + if ((JTAG_CHAIN != 1) && (JTAG_CHAIN != 2) && (JTAG_CHAIN != 3) && (JTAG_CHAIN != 4)) begin + $display("Attribute Syntax Error : The attribute JTAG_CHAIN on BSCAN_SPARTAN6 instance %m is set to %d. Legal values for this attribute are 1, 2, 3 or 4.", JTAG_CHAIN); + $finish; + end + + end +//--#################################################################### +//--##### Jtag_select ### +//--#################################################################### + always@(glbl.JTAG_SEL1_GLBL or glbl.JTAG_SEL2_GLBL or glbl.JTAG_SEL3_GLBL or glbl.JTAG_SEL4_GLBL) begin + if (JTAG_CHAIN == 1) SEL_zd = glbl.JTAG_SEL1_GLBL; + else if (JTAG_CHAIN == 2) SEL_zd = glbl.JTAG_SEL2_GLBL; + else if (JTAG_CHAIN == 3) SEL_zd = glbl.JTAG_SEL3_GLBL; + else if (JTAG_CHAIN == 4) SEL_zd = glbl.JTAG_SEL4_GLBL; + end +//--#################################################################### +//--##### USER_TDO ### +//--#################################################################### + always@(TDO) begin + if (JTAG_CHAIN == 1) glbl.JTAG_USER_TDO1_GLBL = TDO; + else if (JTAG_CHAIN == 2) glbl.JTAG_USER_TDO2_GLBL = TDO; + else if (JTAG_CHAIN == 3) glbl.JTAG_USER_TDO3_GLBL = TDO; + else if (JTAG_CHAIN == 4) glbl.JTAG_USER_TDO4_GLBL = TDO; + end +//--#################################################################### +//--##### Output ### +//--#################################################################### + +assign CAPTURE = glbl.JTAG_CAPTURE_GLBL; +assign #5 DRCK = ((SEL_zd & !glbl.JTAG_SHIFT_GLBL & !glbl.JTAG_CAPTURE_GLBL) + || + (SEL_zd & glbl.JTAG_SHIFT_GLBL & glbl.JTAG_TCK_GLBL) + || + (SEL_zd & glbl.JTAG_CAPTURE_GLBL & glbl.JTAG_TCK_GLBL)); + +assign RESET = glbl.JTAG_RESET_GLBL; +assign RUNTEST = glbl.JTAG_RUNTEST_GLBL; +assign SEL = SEL_zd; +assign SHIFT = glbl.JTAG_SHIFT_GLBL; +assign TDI = glbl.JTAG_TDI_GLBL; +assign TCK = glbl.JTAG_TCK_GLBL; +assign TMS = glbl.JTAG_TMS_GLBL; +assign UPDATE = glbl.JTAG_UPDATE_GLBL; + +endmodule diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/BSCAN_VIRTEX4.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/BSCAN_VIRTEX4.v new file mode 100644 index 0000000..be1f45f --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/BSCAN_VIRTEX4.v @@ -0,0 +1,88 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/virtex4/BSCAN_VIRTEX4.v,v 1.5 2006/03/08 01:52:48 fphillip Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Boundary Scan Logic Control Circuit for VIRTEX4 +// /___/ /\ Filename : BSCAN_VIRTEX4.v +// \ \ / \ Timestamp : Thu Mar 25 16:43:43 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 02/28/06 - CR 225753 -- Removed Timing +// 02/28/06 - CR 226003 -- Added Parameter Types (integer/real). +// End Revision + + +`timescale 1 ps / 1 ps + + +module BSCAN_VIRTEX4 (CAPTURE, DRCK, RESET, SEL, SHIFT, TDI, UPDATE, TDO); + + output CAPTURE, DRCK, RESET, SEL, SHIFT, TDI, UPDATE; + + input TDO; + + reg SEL_zd; + + parameter integer JTAG_CHAIN = 1; + + pulldown (DRCK); + pulldown (RESET); + pulldown (SEL); + pulldown (SHIFT); + pulldown (TDI); + pulldown (UPDATE); + +//--#################################################################### +//--##### Initialization ### +//--#################################################################### + initial begin + if ((JTAG_CHAIN != 1) && (JTAG_CHAIN != 2) && (JTAG_CHAIN != 3) && (JTAG_CHAIN != 4)) begin + $display("Attribute Syntax Error : The attribute JTAG_CHAIN on BSCAN_VIRTEX4 instance %m is set to %d. Legal values for this attribute are 1, 2, 3 or 4.", JTAG_CHAIN); + $finish; + end + + end +//--#################################################################### +//--##### Jtag_select ### +//--#################################################################### + always@(glbl.JTAG_SEL1_GLBL or glbl.JTAG_SEL2_GLBL or glbl.JTAG_SEL3_GLBL or glbl.JTAG_SEL4_GLBL) begin + if (JTAG_CHAIN == 1) SEL_zd = glbl.JTAG_SEL1_GLBL; + else if (JTAG_CHAIN == 2) SEL_zd = glbl.JTAG_SEL2_GLBL; + else if (JTAG_CHAIN == 3) SEL_zd = glbl.JTAG_SEL3_GLBL; + else if (JTAG_CHAIN == 4) SEL_zd = glbl.JTAG_SEL4_GLBL; + end +//--#################################################################### +//--##### USER_TDO ### +//--#################################################################### + always@(TDO) begin + if (JTAG_CHAIN == 1) glbl.JTAG_USER_TDO1_GLBL = TDO; + else if (JTAG_CHAIN == 2) glbl.JTAG_USER_TDO2_GLBL = TDO; + else if (JTAG_CHAIN == 3) glbl.JTAG_USER_TDO3_GLBL = TDO; + else if (JTAG_CHAIN == 4) glbl.JTAG_USER_TDO4_GLBL = TDO; + end +//--#################################################################### +//--##### Output ### +//--#################################################################### + +assign CAPTURE = glbl.JTAG_CAPTURE_GLBL; +assign #5 DRCK = ((SEL_zd & !glbl.JTAG_SHIFT_GLBL & !glbl.JTAG_CAPTURE_GLBL) + || + (SEL_zd & glbl.JTAG_SHIFT_GLBL & glbl.JTAG_TCK_GLBL) + || + (SEL_zd & glbl.JTAG_CAPTURE_GLBL & glbl.JTAG_TCK_GLBL)); + +assign SHIFT = glbl.JTAG_SHIFT_GLBL; +assign SEL = SEL_zd; +assign TDI = glbl.JTAG_TDI_GLBL; +assign UPDATE = glbl.JTAG_UPDATE_GLBL; +assign RESET = glbl.JTAG_RESET_GLBL; + +endmodule diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/BSCAN_VIRTEX5.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/BSCAN_VIRTEX5.v new file mode 100644 index 0000000..1774fd7 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/BSCAN_VIRTEX5.v @@ -0,0 +1,90 @@ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Boundary Scan Logic Control Circuit for VIRTEX5 +// /___/ /\ Filename : BSCAN_VIRTEX5.v +// \ \ / \ Timestamp : Thu Jul 21 13:42:30 PDT 2005 +// \___\/\___\ +// +// Revision: +// 07/21/05 - Initial version. +// 02/28/06 - CR 225753 -- Removed Timing +// 02/28/06 - CR 226003 -- Added Parameter Types (integer/real). +// End Revision + +`timescale 1 ps / 1 ps + + +module BSCAN_VIRTEX5 (CAPTURE, DRCK, RESET, SEL, SHIFT, TDI, UPDATE, TDO); + + output CAPTURE, DRCK, RESET, SEL, SHIFT, TDI, UPDATE; + + input TDO; + + reg SEL_zd; + + parameter integer JTAG_CHAIN = 1; + + pulldown (DRCK); + pulldown (RESET); + pulldown (SEL); + pulldown (SHIFT); + pulldown (TDI); + pulldown (UPDATE); + +//--#################################################################### +//--##### Initialization ### +//--#################################################################### + initial begin + if ((JTAG_CHAIN != 1) && (JTAG_CHAIN != 2) && (JTAG_CHAIN != 3) && (JTAG_CHAIN != 4)) begin + $display("Attribute Syntax Error : The attribute JTAG_CHAIN on BSCAN_VIRTEX5 instance %m is set to %d. Legal values for this attribute are 1, 2, 3 or 4.", JTAG_CHAIN); + $finish; + end + + end +//--#################################################################### +//--##### Jtag_select ### +//--#################################################################### + always@(glbl.JTAG_SEL1_GLBL or glbl.JTAG_SEL2_GLBL or glbl.JTAG_SEL3_GLBL or glbl.JTAG_SEL4_GLBL) begin + if (JTAG_CHAIN == 1) SEL_zd = glbl.JTAG_SEL1_GLBL; + else if (JTAG_CHAIN == 2) SEL_zd = glbl.JTAG_SEL2_GLBL; + else if (JTAG_CHAIN == 3) SEL_zd = glbl.JTAG_SEL3_GLBL; + else if (JTAG_CHAIN == 4) SEL_zd = glbl.JTAG_SEL4_GLBL; + end +//--#################################################################### +//--##### USER_TDO ### +//--#################################################################### + always@(TDO) begin + if (JTAG_CHAIN == 1) glbl.JTAG_USER_TDO1_GLBL = TDO; + else if (JTAG_CHAIN == 2) glbl.JTAG_USER_TDO2_GLBL = TDO; + else if (JTAG_CHAIN == 3) glbl.JTAG_USER_TDO3_GLBL = TDO; + else if (JTAG_CHAIN == 4) glbl.JTAG_USER_TDO4_GLBL = TDO; + end +//--#################################################################### +//--##### Output ### +//--#################################################################### + +assign CAPTURE = glbl.JTAG_CAPTURE_GLBL; +assign #5 DRCK = ((SEL_zd & !glbl.JTAG_SHIFT_GLBL & !glbl.JTAG_CAPTURE_GLBL) + || + (SEL_zd & glbl.JTAG_SHIFT_GLBL & glbl.JTAG_TCK_GLBL) + || + (SEL_zd & glbl.JTAG_CAPTURE_GLBL & glbl.JTAG_TCK_GLBL)); + +assign SHIFT = glbl.JTAG_SHIFT_GLBL; +assign SEL = SEL_zd; +assign TDI = glbl.JTAG_TDI_GLBL; +assign UPDATE = glbl.JTAG_UPDATE_GLBL; +assign RESET = glbl.JTAG_RESET_GLBL; + +//--#################################################################### +//--##### Timing ### +//--#################################################################### + +endmodule diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/BSCAN_VIRTEX6.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/BSCAN_VIRTEX6.v new file mode 100644 index 0000000..30b95be --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/BSCAN_VIRTEX6.v @@ -0,0 +1,122 @@ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Boundary Scan Logic Control Circuit for VIRTEX6 +// /___/ /\ Filename : BSCAN_VIRTEX6.v +// \ \ / \ Timestamp : Mon Jan 5 10:28:18 PST 2009 +// \___\/\___\ +// +// Revision: +// 01/05/09 - Initial version. +// End Revision + + +`timescale 1 ps / 1 ps + +module BSCAN_VIRTEX6 ( + CAPTURE, + DRCK, + RESET, + RUNTEST, + SEL, + SHIFT, + TCK, + TDI, + TMS, + UPDATE, + TDO +); + + parameter DISABLE_JTAG = "FALSE"; + parameter integer JTAG_CHAIN = 1; + + output CAPTURE; + output DRCK; + output RESET; + output RUNTEST; + output SEL; + output SHIFT; + output TCK; + output TDI; + output TMS; + output UPDATE; + + input TDO; + reg SEL_zd; + + pulldown (DRCK); + pulldown (RESET); + pulldown (SEL); + pulldown (SHIFT); + pulldown (TDI); + pulldown (UPDATE); + +//--#################################################################### +//--##### Initialization ### +//--#################################################################### + initial begin + + //-------- JTAG_CHAIN + + if ((JTAG_CHAIN != 1) && (JTAG_CHAIN != 2) && (JTAG_CHAIN != 3) && (JTAG_CHAIN != 4)) begin + $display("Attribute Syntax Error : The attribute JTAG_CHAIN on BSCAN_VIRTEX5 instance %m is set to %d. Legal values for this attribute are 1, 2, 3 or 4.", JTAG_CHAIN); + $finish; + end + + //-------- DISABLE_JTAG + + case (DISABLE_JTAG) + "TRUE", "FALSE" : ; + default : begin + $display("Attribute Syntax Error : The attribute DISABLE_JTAG on BSCAN_VIRTEX6 instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", DISABLE_JTAG); + $finish; + end + endcase + end + +//--#################################################################### +//--##### Jtag_select ### +//--#################################################################### + always@(glbl.JTAG_SEL1_GLBL or glbl.JTAG_SEL2_GLBL or glbl.JTAG_SEL3_GLBL or glbl.JTAG_SEL4_GLBL) begin + if (JTAG_CHAIN == 1) SEL_zd = glbl.JTAG_SEL1_GLBL; + else if (JTAG_CHAIN == 2) SEL_zd = glbl.JTAG_SEL2_GLBL; + else if (JTAG_CHAIN == 3) SEL_zd = glbl.JTAG_SEL3_GLBL; + else if (JTAG_CHAIN == 4) SEL_zd = glbl.JTAG_SEL4_GLBL; + end +//--#################################################################### +//--#################################################################### +//--##### USER_TDO ### +//--#################################################################### + always@(TDO) begin + if (JTAG_CHAIN == 1) glbl.JTAG_USER_TDO1_GLBL = TDO; + else if (JTAG_CHAIN == 2) glbl.JTAG_USER_TDO2_GLBL = TDO; + else if (JTAG_CHAIN == 3) glbl.JTAG_USER_TDO3_GLBL = TDO; + else if (JTAG_CHAIN == 4) glbl.JTAG_USER_TDO4_GLBL = TDO; + end +//--#################################################################### +//--##### Output ### +//--#################################################################### + +assign CAPTURE = glbl.JTAG_CAPTURE_GLBL; +assign #5 DRCK = ((SEL_zd & !glbl.JTAG_SHIFT_GLBL & !glbl.JTAG_CAPTURE_GLBL) + || + (SEL_zd & glbl.JTAG_SHIFT_GLBL & glbl.JTAG_TCK_GLBL) + || + (SEL_zd & glbl.JTAG_CAPTURE_GLBL & glbl.JTAG_TCK_GLBL)); + +assign RESET = glbl.JTAG_RESET_GLBL; +assign RUNTEST = glbl.JTAG_RUNTEST_GLBL; +assign SEL = SEL_zd; +assign SHIFT = glbl.JTAG_SHIFT_GLBL; +assign TDI = glbl.JTAG_TDI_GLBL; +assign TCK = glbl.JTAG_TCK_GLBL; +assign TMS = glbl.JTAG_TMS_GLBL; +assign UPDATE = glbl.JTAG_UPDATE_GLBL; + +endmodule diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/BUF.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/BUF.v new file mode 100644 index 0000000..acb1ba8 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/BUF.v @@ -0,0 +1,33 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/BUF.v,v 1.6 2007/05/23 21:43:33 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / General Purpose Buffer +// /___/ /\ Filename : BUF.v +// \ \ / \ Timestamp : Thu Mar 25 16:42:13 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. + +`timescale 1 ps / 1 ps + + +module BUF (O, I); + + output O; + + input I; + + buf B1 (O, I); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/BUFCF.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/BUFCF.v new file mode 100644 index 0000000..57ce42d --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/BUFCF.v @@ -0,0 +1,33 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/BUFCF.v,v 1.6 2007/05/23 21:43:33 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Fast Connect Buffer +// /___/ /\ Filename : BUFCF.v +// \ \ / \ Timestamp : Thu Mar 25 16:42:13 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. + +`timescale 1 ps / 1 ps + + +module BUFCF (O, I); + + output O; + + input I; + + buf B1 (O, I); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/BUFE.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/BUFE.v new file mode 100644 index 0000000..296ac58 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/BUFE.v @@ -0,0 +1,33 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/BUFE.v,v 1.6 2007/05/23 21:43:33 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Internal 3-State Buffer with Active High Enable +// /___/ /\ Filename : BUFE.v +// \ \ / \ Timestamp : Thu Mar 25 16:42:14 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. + +`timescale 1 ps / 1 ps + + +module BUFE (O, E, I); + + output O; + + input E, I; + + bufif1 B1 (O, I, E); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/BUFG.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/BUFG.v new file mode 100644 index 0000000..c01d66d --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/BUFG.v @@ -0,0 +1,33 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/BUFG.v,v 1.6 2007/05/23 21:43:33 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Global Clock Buffer +// /___/ /\ Filename : BUFG.v +// \ \ / \ Timestamp : Thu Mar 25 16:42:14 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. + +`timescale 1 ps / 1 ps + + +module BUFG (O, I); + + output O; + + input I; + + buf B1 (O, I); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/BUFGCE.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/BUFGCE.v new file mode 100644 index 0000000..aeff81a --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/BUFGCE.v @@ -0,0 +1,38 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/BUFGCE.v,v 1.7 2007/05/23 21:43:33 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Global Clock Mux Buffer with Clock Enable and Output State 0 +// /___/ /\ Filename : BUFGCE.v +// \ \ / \ Timestamp : Thu Mar 25 16:42:14 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. + +`timescale 1 ps / 1 ps + +module BUFGCE (O, CE, I); + + output O; + + input CE, I; + + wire NCE; + + BUFGMUX B1 (.I0(I), + .I1(1'b0), + .O(O), + .S(NCE)); + + INV I1 (.I(CE), + .O(NCE)); + +endmodule diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/BUFGCE_1.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/BUFGCE_1.v new file mode 100644 index 0000000..b8b435b --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/BUFGCE_1.v @@ -0,0 +1,38 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/BUFGCE_1.v,v 1.5 2007/05/23 21:43:33 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Global Clock Mux Buffer with Clock Enable and Output State 1 +// /___/ /\ Filename : BUFGCE_1.v +// \ \ / \ Timestamp : Thu Mar 25 16:42:14 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. + +`timescale 1 ps / 1 ps + +module BUFGCE_1 (O, CE, I); + + output O; + + input CE, I; + + wire NCE; + + BUFGMUX_1 B1 (.I0(I), + .I1(1'b1), + .O(O), + .S(NCE)); + + INV I1 (.I(CE), + .O(NCE)); + +endmodule diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/BUFGCTRL.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/BUFGCTRL.v new file mode 100644 index 0000000..834165f --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/BUFGCTRL.v @@ -0,0 +1,166 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/virtex4/BUFGCTRL.v,v 1.9 2007/06/06 18:05:48 yanx Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2005 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Global Clock Mux Buffer +// /___/ /\ Filename : BUFGCTRL.v +// \ \ / \ Timestamp : Thu Mar 11 16:43:43 PST 2005 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 03/11/05 - Initialized outpus. +// 05/31/07 - Add wire definition, remove buf. +// End Revision + +`timescale 1 ps/1 ps + +module BUFGCTRL (O, CE0, CE1, I0, I1, IGNORE0, IGNORE1, S0, S1); + + output O; + input CE0; + input CE1; + tri0 GSR = glbl.GSR; + input I0; + input I1; + input IGNORE0; + input IGNORE1; + input S0; + input S1; + + parameter integer INIT_OUT = 0; + parameter PRESELECT_I0 = "FALSE"; + parameter PRESELECT_I1 = "FALSE"; + + reg O; + reg q0, q1; + reg q0_enable, q1_enable; + reg preselect_i0, preselect_i1; + reg task_input_ce0, task_input_ce1, task_input_i0; + reg task_input_i1, task_input_ignore0, task_input_ignore1; + reg task_input_gsr, task_input_s0, task_input_s1; + + wire I0t, I1t; + + + +// *** parameter checking + + initial begin + case (PRESELECT_I0) + "TRUE" : preselect_i0 = 1'b1; + "FALSE" : preselect_i0 = 1'b0; + default : begin + $display("Attribute Syntax Error : The attribute PRESELECT_I0 on BUFGCTRL instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", PRESELECT_I0); + $finish; + end + endcase + end + + initial begin + case (PRESELECT_I1) + "TRUE" : preselect_i1 = 1'b1; + "FALSE" : preselect_i1 = 1'b0; + default : begin + $display("Attribute Syntax Error : The attribute PRESELECT_I1 on BUFGCTRL instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", PRESELECT_I1); + $finish; + end + endcase + end + + +// *** both preselects can not be 1 simultaneously. + initial begin + if (preselect_i0 && preselect_i1) begin + $display("Attribute Syntax Error : The attributes PRESELECT_I0 and PRESELECT_I1 on BUFGCTRL instance %m should not be set to TRUE simultaneously."); + $finish; + end + end + + initial begin + if ((INIT_OUT != 0) && (INIT_OUT != 1)) begin + $display("Attribute Syntax Error : The attribute INIT_OUT on BUFGCTRL instance %m is set to %d. Legal values for this attribute are 0 or 1.", INIT_OUT); + $finish; + end + end + + +// *** Start here + assign I0t = INIT_OUT ? ~I0 : I0; + assign I1t = INIT_OUT ? ~I1 : I1; + +// *** Input enable for i1 + always @(IGNORE1 or I1t or S1 or GSR or q0) begin + if (GSR == 1) + q1_enable <= preselect_i1; + + else if (GSR == 0) begin + if ((I1t == 0) && (IGNORE1 == 0)) + q1_enable <= q1_enable; + else if ((I1t == 1) || (IGNORE1 == 1)) + q1_enable <= (~q0 && S1); + end + end + +// *** Output q1 for i1 + always @(q1_enable or CE1 or I1t or IGNORE1 or GSR) begin + if (GSR == 1) + q1 <= preselect_i1; + + else if (GSR == 0) begin + if ((I1t == 1)&& (IGNORE1 == 0)) + q1 <= q1; + else if ((I1t == 0) || (IGNORE1 == 1)) + q1 <= (CE1 && q1_enable); + end + end + +// *** input enable for i0 + always @(IGNORE0 or I0t or S0 or GSR or q1) begin + if (GSR == 1) + q0_enable <= preselect_i0; + + else if (GSR == 0) begin + if ((I0t == 0) && (IGNORE0 == 0)) + q0_enable <= q0_enable; + else if ((I0t == 1) || (IGNORE0 == 1)) + q0_enable <= (~q1 && S0); + end + end + +// *** Output q0 for i0 + always @(q0_enable or CE0 or I0t or IGNORE0 or GSR) begin + if (GSR == 1) + q0 <= preselect_i0; + + else if (GSR == 0) begin + if ((I0t == 1) && (IGNORE0 == 0)) + q0 <= q0; + else if ((I0t == 0) || (IGNORE0 == 1)) + q0 <= (CE0 && q0_enable); + end + end + + + always @(q0 or q1 or I0t or I1t) begin + case ({q1, q0}) + 2'b01: O = I0; + 2'b10: O = I1; + 2'b00: O = INIT_OUT; + 2'b11: begin + q0 = 1'bx; + q1 = 1'bx; + q0_enable = 1'bx; + q1_enable = 1'bx; + O = 1'bx; + end + endcase + end + +endmodule diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/BUFGDLL.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/BUFGDLL.v new file mode 100644 index 0000000..d5672ad --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/BUFGDLL.v @@ -0,0 +1,42 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/BUFGDLL.v,v 1.5 2007/05/23 21:43:33 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Clock Delay Locked Loop Buffer +// /___/ /\ Filename : BUFGDLL.v +// \ \ / \ Timestamp : Thu Mar 25 16:42:14 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. + +`timescale 1 ps / 1 ps + + +module BUFGDLL (O, I); + + output O; + input I; + + parameter DUTY_CYCLE_CORRECTION = "TRUE"; + + wire clkin_int; + wire clk0_out, clk180_out, clk270_out, clk2x_out; + wire clk90_out, clkdv_out, locked_out; + + CLKDLL clkdll_inst (.CLK0(clk0_out), .CLK180(clk180_out), .CLK270(clk270_out), .CLK2X(clk2x_out), .CLK90(clk90_out), .CLKDV(clkdv_out), .LOCKED(locked_out), .CLKFB(O), .CLKIN(clkin_int), .RST(1'b0)); + defparam clkdll_inst.DUTY_CYCLE_CORRECTION = DUTY_CYCLE_CORRECTION; + + IBUFG ibufg_inst (.O(clkin_int), .I(I)); + + BUFG bufg_inst (.O(O), .I(clk0_out)); + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/BUFGMUX.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/BUFGMUX.v new file mode 100644 index 0000000..b66033b --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/BUFGMUX.v @@ -0,0 +1,75 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/BUFGMUX.v,v 1.16 2009/08/21 23:55:43 harikr Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Global Clock Mux Buffer with Output State 0 +// /___/ /\ Filename : BUFGMUX.v +// \ \ / \ Timestamp : Thu Mar 25 16:42:14 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. +// 01/11/08 - Add CLK_SEL_TYPE attribute. +// End Revision + +`timescale 1 ps / 1 ps + +module BUFGMUX (O, I0, I1, S); + + parameter CLK_SEL_TYPE = "SYNC"; + output O; + input I0, I1, S; + + reg q0, q1; + reg q0_enable, q1_enable; + wire q0_t, q1_t; + reg clk_sel_in; + + tri0 GSR = glbl.GSR; + + bufif1 B0 (O, I0, q0_t); + bufif1 B1 (O, I1, q1_t); + pulldown P1 (O); + + initial + clk_sel_in = (CLK_SEL_TYPE == "ASYNC") ? 1 : 0; + + assign q0_t = (clk_sel_in) ? ~S : q0; + assign q1_t = (clk_sel_in) ? S : q1; + + always @(GSR or I0 or S or q0_enable) + if (GSR) + q0 <= 1; + else if (!I0) + q0 <= !S && q0_enable; + + always @(GSR or I1 or S or q1_enable) + if (GSR) + q1 <= 0; + else if (!I1) + q1 <= S && q1_enable; + + always @(GSR or q1 or I0) + if (GSR) + q0_enable <= 1; + else if (q1) + q0_enable <= 0; + else if (I0) + q0_enable <= !q1; + + always @(GSR or q0 or I1) + if (GSR) + q1_enable <= 0; + else if (q0) + q1_enable <= 0; + else if (I1) + q1_enable <= !q0; + +endmodule diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/BUFGMUX_1.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/BUFGMUX_1.v new file mode 100644 index 0000000..fb39e7c --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/BUFGMUX_1.v @@ -0,0 +1,76 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/BUFGMUX_1.v,v 1.15 2009/08/21 23:55:43 harikr Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Global Clock Mux Buffer with Output State 1 +// /___/ /\ Filename : BUFGMUX_1.v +// \ \ / \ Timestamp : Thu Mar 25 16:42:14 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. +// 01/11/08 - Add CLK_SEL_TYPE attribute. +// End Revision + +`timescale 1 ps / 1 ps + +module BUFGMUX_1 (O, I0, I1, S); + + parameter CLK_SEL_TYPE = "SYNC"; + output O; + + input I0, I1, S; + + reg q0, q1; + reg q0_enable, q1_enable; + wire q0_t, q1_t; + reg clk_sel_in; + + tri0 GSR = glbl.GSR; + + bufif1 B0 (O, I0, q0_t); + bufif1 B1 (O, I1, q1_t); + pullup P1 (O); + + initial + clk_sel_in = (CLK_SEL_TYPE == "ASYNC") ? 1 : 0; + + assign q0_t = (clk_sel_in) ? ~S : q0; + assign q1_t = (clk_sel_in) ? S : q1; + + always @(GSR or I0 or S or q0_enable) + if (GSR) + q0 <= 1; + else if (I0) + q0 <= !S && q0_enable; + + always @(GSR or I1 or S or q1_enable) + if (GSR) + q1 <= 0; + else if (I1) + q1 <= S && q1_enable; + + always @(GSR or q1 or I0) + if (GSR) + q0_enable <= 1; + else if (q1) + q0_enable <= 0; + else if (!I0) + q0_enable <= !q1; + + always @(GSR or q0 or I1) + if (GSR) + q1_enable <= 0; + else if (q0) + q1_enable <= 0; + else if (!I1) + q1_enable <= !q0; + +endmodule diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/BUFGMUX_CTRL.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/BUFGMUX_CTRL.v new file mode 100644 index 0000000..df0b43e --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/BUFGMUX_CTRL.v @@ -0,0 +1,35 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/rainier/BUFGMUX_CTRL.v,v 1.2 2006/03/11 00:25:33 yanx Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Global Clock Mux Buffer +// /___/ /\ Filename : BUFGMUX_CTRL.v +// \ \ / \ Timestamp : Thu Mar 25 16:43:43 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/10/06 - Initial version. + +`timescale 1 ps / 1 ps + +module BUFGMUX_CTRL (O, I0, I1, S); + + output O; + + input I0; + input I1; + input S; + + BUFGCTRL bufgctrl_inst (.O(O), .CE0(1'b1), .CE1(1'b1), .I0(I0), .I1(I1), .IGNORE0(1'b0), .IGNORE1(1'b0), .S0(~S), .S1(S)); + + defparam bufgctrl_inst.INIT_OUT = 1'b0; + defparam bufgctrl_inst.PRESELECT_I0 = "TRUE"; + defparam bufgctrl_inst.PRESELECT_I1 = "FALSE"; + +endmodule diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/BUFGMUX_VIRTEX4.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/BUFGMUX_VIRTEX4.v new file mode 100644 index 0000000..a613687 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/BUFGMUX_VIRTEX4.v @@ -0,0 +1,35 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/virtex4/BUFGMUX_VIRTEX4.v,v 1.3 2004/03/31 22:39:41 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Global Clock Mux Buffer +// /___/ /\ Filename : BUFGMUX_VIRTEX4.v +// \ \ / \ Timestamp : Thu Mar 25 16:43:43 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. + +`timescale 1 ps / 1 ps + +module BUFGMUX_VIRTEX4 (O, I0, I1, S); + + output O; + + input I0; + input I1; + input S; + + BUFGCTRL bufgctrl_inst (.O(O), .CE0(1'b1), .CE1(1'b1), .I0(I0), .I1(I1), .IGNORE0(1'b0), .IGNORE1(1'b0), .S0(~S), .S1(S)); + + defparam bufgctrl_inst.INIT_OUT = 1'b0; + defparam bufgctrl_inst.PRESELECT_I0 = "TRUE"; + defparam bufgctrl_inst.PRESELECT_I1 = "FALSE"; + +endmodule diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/BUFGP.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/BUFGP.v new file mode 100644 index 0000000..7848347 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/BUFGP.v @@ -0,0 +1,33 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/BUFGP.v,v 1.6 2007/05/23 21:43:33 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Primary Global Buffer for Driving Clocks or Long Lines +// /___/ /\ Filename : BUFGP.v +// \ \ / \ Timestamp : Thu Mar 25 16:42:14 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. + +`timescale 1 ps / 1 ps + + +module BUFGP (O, I); + + output O; + + input I; + + buf B1 (O, I); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/BUFH.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/BUFH.v new file mode 100644 index 0000000..a405dd1 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/BUFH.v @@ -0,0 +1,35 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/blanc/BUFH.v,v 1.3 2008/11/11 21:41:06 yanx Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / H Clock Buffer +// /___/ /\ Filename : BUFH.v +// \ \ / \ Timestamp : +// \___\/\___\ +// +// Revision: +// 04/08/08 - Initial version. +// 09//9/08 - Change to use BUFHCE according to yaml. +// 11/11/08 - Change to not use BUFHCE. +// End Revision + +`timescale 1 ps / 1 ps + + +module BUFH (O, I); + + output O; + + input I; + + + buf B1 (O, I); + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/BUFHCE.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/BUFHCE.v new file mode 100644 index 0000000..ce734ad --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/BUFHCE.v @@ -0,0 +1,52 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/blanc/BUFHCE.v,v 1.4 2008/10/21 20:28:29 yanx Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / H Clock Buffer with Active High Enable +// /___/ /\ Filename : BUFHCE.v +// \ \ / \ Timestamp : +// \___\/\___\ +// +// Revision: +// 04/08/08 - Initial version. +// 09/19/08 - Add GSR. +// 10/19/08 - Recoding to same as BUFGCE according to hardware. +// End Revision + +`timescale 1 ps / 1 ps + + +module BUFHCE (O, CE, I); + + parameter integer INIT_OUT = 0; + + output O; + + input CE; + input I; + + wire NCE, o_bufg_o, o_bufg1_o; + + BUFGMUX B1 (.I0(I), + .I1(1'b0), + .O(o_bufg_o), + .S(NCE)); + + INV I1 (.I(CE), + .O(NCE)); + + BUFGMUX_1 B2 (.I0(I), + .I1(1'b1), + .O(o_bufg1_o), + .S(NCE)); + + assign O = (INIT_OUT == 1) ? o_bufg1_o : o_bufg_o; + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/BUFIO.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/BUFIO.v new file mode 100644 index 0000000..ecb3d80 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/BUFIO.v @@ -0,0 +1,32 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/virtex4/BUFIO.v,v 1.4 2007/06/01 22:41:59 yanx Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Local Clock Buffer for I/O +// /___/ /\ Filename : BUFIO.v +// \ \ / \ Timestamp : Thu Mar 25 16:43:43 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/30/07 - change timescale to 1ps/1ps. + +`timescale 1 ps / 1 ps + + +module BUFIO (O, I); + + output O; + + input I; + + buf B1 (O, I); + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/BUFIO2.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/BUFIO2.v new file mode 100644 index 0000000..eb03309 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/BUFIO2.v @@ -0,0 +1,362 @@ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2007 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / I/O Clock Buffer/Divider for the Spartan Series +// /___/ /\ Filename : BUFIO2.v +// \ \ / \ Timestamp : Tue Feb 12 16:34:29 PST 2008 +// \___\/\___\ +// +// Revision: +// 02/12/08 - Initial version. +// 08/19/08 - IR 479918 fix ... added 100 ps latency to unisim sequential paths. +// 10/16/08 - Added default timing to simprims +// 01/22/09 - Added attribute I_INVERT +// 02/03/09 - CR 506731 -- Add attribute USE_DOUBLER +// 02/06/09 - IR 507303 -- Removed 100 ps delay from DIVCLK +// 02/15/09 - CR 508344 -- Fixed USE_DOUBLER effects +// 02/25/09 - CR 508344 -- Rework DIVCLK when DIVIDE=1 and USE_DOUBLER=TRUE +// -- Fixed IOCLK to be the same as I. +// 02/25/09 - CR 509386 -- Added 100 ps delay to DIVCLK output +// 03/10/09 - CR 511512 -- Ingored x->1 transition at time=0 -- Verilog fix only +// 03/12/09 - CR 511597 -- DRC check for invalid combination -- USE_DOUBLER=TRUE and DIVIDE=1 +// 07/07/09 - CR 526436 -- DRC check for DIVIDE_BYPASS{TRUE}/DIVIDE{2...8} combinations +// 09/09/09 - CR 531517 -- DRC check for invalid combination -- USE_DOUBLER=TRUE and I_INVERT=TRUE +// 12/07/09 - CR 540087 -- Aligned serdesstrobe to the falling edge of the divclk +// 02/18/10 - Reverted back the above CR +// 05/25/09 - CR 561858 -- when DDR/DIVIDE=even #s, DIVCLK/SERDESSTROBE should rise 1/2 period sooner than the current version +// End Revision + +`timescale 1 ps / 1 ps + +module BUFIO2 (DIVCLK, IOCLK, SERDESSTROBE, I); + + + + parameter DIVIDE_BYPASS = "TRUE"; // TRUE, FALSE + parameter integer DIVIDE = 1; // {1..8} + parameter I_INVERT = "FALSE"; // TRUE, FALSE + parameter USE_DOUBLER = "FALSE"; // TRUE, FALSE + + + output DIVCLK; + output IOCLK; + output SERDESSTROBE; + + input I; + +// Output signals + reg divclk_out=0, ioclk_out=0, serdesstrobe_out=0; + +// Counters and Flags + reg [2:0] ce_count = 0; + reg [2:0] edge_count = 0; + reg [2:0] RisingEdgeCount = 0; + reg [2:0] FallingEdgeCount = 0; + reg TriggerOnRise; // FP + + reg allEqual=0, RisingEdgeMatch=0, FallingEdgeMatch=0, match=0, nmatch=0; + reg divclk_bypass_attr; + reg Ivert_attr; + reg use_doubler_attr; + + reg divclk_int=0; + + reg I_int; + reg i1_int, i2_int; + wire doubled_clk_int; + + wire div1_clk; + +// Attribute settings + +// Other signals + reg attr_err_flag = 0; + tri0 GSR = glbl.GSR; + + + +// Optional inverter for I + generate + case (I_INVERT) + "FALSE" : always @(I) I_int <= I; + "TRUE" : always @(I) I_int <= ~I; + endcase + endgenerate + + + initial begin + ce_count = DIVIDE - 1; + allEqual = 0; + match = 0; + nmatch = 0; +// FP #1; +//------------------------------------------------- +//----- DIVIDE check +//------------------------------------------------- + case (DIVIDE) + 1 : begin + RisingEdgeCount = 3'b000; + FallingEdgeCount = 3'b000; + TriggerOnRise = 1; + end + + 2 : begin + RisingEdgeCount = 3'b001; + FallingEdgeCount = 3'b000; + TriggerOnRise = 1; + end + + 3 : begin + RisingEdgeCount = 3'b010; + FallingEdgeCount = 3'b000; + TriggerOnRise = 0; + end + + 4 : begin + RisingEdgeCount = 3'b011; + FallingEdgeCount = 3'b001; + TriggerOnRise = 1; + end + + 5 : begin + RisingEdgeCount = 3'b100; + FallingEdgeCount = 3'b001; + TriggerOnRise = 0; + end + + 6 : begin + RisingEdgeCount = 3'b101; + FallingEdgeCount = 3'b010; + TriggerOnRise = 1; + end + + 7 : begin + RisingEdgeCount = 3'b110; + FallingEdgeCount = 3'b010; + TriggerOnRise = 0; + end + + 8 : begin + RisingEdgeCount = 3'b111; + FallingEdgeCount = 3'b011; + TriggerOnRise = 1; + end + + default : begin + $display("Attribute Syntax Error : The attribute DIVIDE on BUFIO2 instance %m is set to %d. Legal values for this attribute are 1, 2, 3, 4, 5, 6, 7 or 8.", DIVIDE); + attr_err_flag = 1; + end + endcase // (DIVIDE) +//------------------------------------------------- +//----- DIVIDE_BYPASS Check +//------------------------------------------------- + case (DIVIDE_BYPASS) + "TRUE" : divclk_bypass_attr <= 1'b1; + "FALSE" :divclk_bypass_attr <= 1'b0; + default : begin + $display("Attribute Syntax Error : The attribute DIVIDE_BYPASS on BUFIO2 instance %m is set to %s. Legal values for this attribute are TRUE or FALSE", DIVIDE_BYPASS); + attr_err_flag = 1; + end + endcase // (DIVIDE_BYPASS) + +//------------------------------------------------- +//----- I_INVERT Check +//------------------------------------------------- + case (I_INVERT) + "TRUE" : Ivert_attr <= 1'b1; + "FALSE" :Ivert_attr <= 1'b0; + default : begin + $display("Attribute Syntax Error : The attribute I_INVERT on BUFIO2 instance %m is set to %s. Legal values for this attribute are TRUE or FALSE", I_INVERT); + attr_err_flag = 1; + end + endcase // (I_INVERT) + +//------------------------------------------------- +//----- USE_DOUBLER Check +//------------------------------------------------- + case (USE_DOUBLER) + "TRUE" : use_doubler_attr <= 1'b1; + "FALSE" : use_doubler_attr <= 1'b0; + default : begin + $display("Attribute Syntax Error : The attribute USE_DOUBLER on BUFIO2 instance %m is set to %s. Legal values for this attribute are TRUE or FALSE", USE_DOUBLER); + attr_err_flag = 1; + end + endcase // (USE_DOUBLER) + +//------------------------------------------------------------------- +//----- Invalid combination DRC check for USE_DOUBLER = TRUE and DIVIDE=1 +//------------------------------------------------------------------- + case (USE_DOUBLER) + "TRUE" : + if(DIVIDE == 1) begin + $display("DRC Error : The attribute USE_DOUBLER on BUFIO2 instance %m is set to %s when DIVIDE is set to 1.\n Legal values for DIVIDE when USE_DOUBLER = TRUE are: 2, 4, 6 or 8", USE_DOUBLER); + attr_err_flag = 1; + end + endcase // (USE_DOUBLER == "TRUE" and DIVIDE == 1) + +//------------------------------------------------------------------- +//----- Invalid combination DRC check for DIVIDE_BYPASS = TRUE and DIVIDE={2..8} +//------------------------------------------------------------------- + case (DIVIDE_BYPASS) + "TRUE" : + if(DIVIDE != 1) begin + $display("DRC Error : The attribute DIVIDE_BYPASS on BUFIO2 instance %m is set to TRUE when DIVIDE is set to %d.\n The DIVIDE_BYPASS must be set to FALSE for any DIVIDE value other than 1", DIVIDE); + attr_err_flag = 1; + end + endcase // (UDIVIDE_BYPASS == "TRUE" and DIVIDE == {2..8}) + +//------------------------------------------------------------------- +//----- Invalid combination DRC check for USE_DOUBLER = TRUE and I_INVERT = TRUE +//------------------------------------------------------------------- + case (USE_DOUBLER) + "TRUE" : + if(I_INVERT == "TRUE") begin + $display("DRC Error : The attribute I_INVERT on BUFIO2 instance %m is set to %s when USE_DOUBLER is set to TRUE.\n I_INVERT must be set to FALSE when USE_DOUBLER = TRUE", I_INVERT); + attr_err_flag = 1; + end + endcase // (USE_DOUBLER == "TRUE" and I_INVERT == "TRUE") + +//------------------------------------------------- +//------ Other Initializations -------- +//------------------------------------------------- + + if (attr_err_flag) + begin + #1; + $finish; + end + + + end // initial begin + + +//----------------------------------------------------------------------------------- + + generate if (USE_DOUBLER == "TRUE") + begin + // ===================== + // clock doubler + // ===================== + always @(posedge I_int) begin + i1_int = 1; + #100 i1_int = 0; + end + + always @(negedge I_int) begin + i2_int = 1; + #100 i2_int = 0; + end + + assign doubled_clk_int = i1_int | i2_int; + end + else + assign doubled_clk_int = I_int; + endgenerate + +// CR 561858 -- for various DIVIDE widths, the count is set differently to match the BUFIO2_2CLK's CR 512001 +// ===================== +// Count the rising edges of the clk +// ===================== +// always @(posedge doubled_clk_int) begin +// if(allEqual || $time < 1) +// edge_count <= 3'b000; +// else +// edge_count <= edge_count + 1; +// end + generate + case(DIVIDE) + 2,4,6,8 : begin + + always @(posedge doubled_clk_int) begin + if($time < 1 ) + edge_count <= DIVIDE-1; //001 for 5 and 7 + else if (allEqual) + edge_count <= 3'b000; + else + edge_count <= edge_count + 1; + end + end + 3,5,7 : begin + //for 1, 3, 5 and 7 below + + always @(posedge doubled_clk_int) begin + if($time < 1 ) + edge_count <= 3'b001; //001 for 5 and 7 + else if (allEqual) + edge_count <= 3'b000; + else + edge_count <= edge_count + 1; + end + end + endcase + endgenerate + +// Generate synchronous reset after DIVIDE number of counts + always @(edge_count) + if (edge_count == ce_count) + allEqual = 1; + else + allEqual = 0; + +// ===================== +// Generate IOCE +// ===================== + always @(posedge doubled_clk_int) + serdesstrobe_out <= allEqual; + +// ===================== +// Generate IOCLK +// ===================== + always @(I_int) + ioclk_out <= I_int; + +// ===================== +// Generate Divided Clock +// ===================== + always @(edge_count) + if (edge_count == RisingEdgeCount) + RisingEdgeMatch = 1; + else + RisingEdgeMatch = 0; + + always @(edge_count) + if (edge_count == FallingEdgeCount) + FallingEdgeMatch = 1; + else + FallingEdgeMatch = 0; + + always @(posedge doubled_clk_int) + match <= RisingEdgeMatch | (match & ~FallingEdgeMatch); + + always @(negedge doubled_clk_int) + if(~TriggerOnRise) + nmatch <= match; + else + nmatch <= 0; + + always@(match or nmatch) divclk_int = match | nmatch; + + always @(divclk_int or I_int) + divclk_out = (divclk_bypass_attr | (DIVIDE == 1))? I_int : divclk_int; + + + + assign DIVCLK = divclk_out; + assign IOCLK = ioclk_out; + assign SERDESSTROBE = serdesstrobe_out; + + specify + (I => DIVCLK) = (100, 100); + (I => IOCLK) = (0, 0); + (I => SERDESSTROBE) = (100, 100); + specparam PATHPULSE$ = 0; + endspecify + +endmodule // BUFIO2 + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/BUFIO2FB.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/BUFIO2FB.v new file mode 100644 index 0000000..188227c --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/BUFIO2FB.v @@ -0,0 +1,59 @@ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2007 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / I/O Clock Buffer/Divider with Feedback for the Spartan Series +// /___/ /\ Filename : BUFIO2FB.v +// \ \ / \ Timestamp : Fri Mar 21 13:47:03 PDT 2008 +// \___\/\___\ +// +// Revision: +// 03/21/08 - Initial version. +// End Revision + +`timescale 1 ps / 1 ps + +module BUFIO2FB (O, I); + + parameter DIVIDE_BYPASS = "TRUE"; // TRUE, FALSE + + output O; + input I; + + reg divclk_bypass_attr; + +// Other signals + reg attr_err_flag = 0; + +//---------------------------------------------------------------------- +//------------------------ Output Ports ------------------------------ +//---------------------------------------------------------------------- + buf buf_o(O, I); + + initial begin +//------------------------------------------------- +//----- DIVIDE_BYPASS Check +//------------------------------------------------- + case (DIVIDE_BYPASS) + "TRUE" : divclk_bypass_attr <= 1'b1; + "FALSE" :divclk_bypass_attr <= 1'b0; + default : begin + $display("Attribute Syntax Error : The attribute DIVIDE_BYPASS on BUFIO2FB instance %m is set to %s. Legal values for this attribute are TRUE or FALSE", DIVIDE_BYPASS); + attr_err_flag = 1; + end + endcase // (DIVIDE_BYPASS) + + if (attr_err_flag) + begin + #1; + $finish; + end + + end // initial begin + +endmodule // BUFIO2FB diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/BUFIO2_2CLK.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/BUFIO2_2CLK.v new file mode 100644 index 0000000..8e7977d --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/BUFIO2_2CLK.v @@ -0,0 +1,264 @@ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2007 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / I/O Clock Buffer/Divider for the Spartan Series +// /___/ /\ Filename : BUFIO2_2CLK.v +// \ \ / \ Timestamp : Tue Feb 12 16:34:29 PST 2008 +// \___\/\___\ +// +// Revision: +// 02/12/08 - Initial version. +// 08/19/08 - IR 479918 fix ... added 100 ps latency to sequential paths. +// 08/19/08 - IR 491038 fix ... IOCLK is forwarded single clk +// 10/16/08 - DIVCLK needs to get doubled input clock +// 12/01/08 - IR 497760 fix +// 02/25/09 - CR 509386 -- Added 100 ps delay to DIVCLK output +// 03/10/09 - CR 511512 -- Ingored x->1 transition at time=0 -- Verilog fix only +// 03/18/09 - CR 511597 -- Disallow DIVIDE=1 +// 04/29/09 - CR 512001 -- Matched the hw latency at startup for various DIVIDEs +// 09/09/09 - CR 531517 -- Added I_INVERT support feature -- Simprim Only +// 12/08/09 - CR 540087 -- Aligned serdesstrobe to the falling edge of the divclk +// 02/18/10 - Revert above CR +// End Revision + +`timescale 1 ps / 1 ps + +module BUFIO2_2CLK (DIVCLK, IOCLK, SERDESSTROBE, I, IB); + + + + parameter integer DIVIDE = 2; // {2..8} + + + output DIVCLK; + output IOCLK; + output SERDESSTROBE; + + input I; + input IB; + +// Output signals + reg divclk_out=0, ioclk_out=0, serdesstrobe_out=0; + +// Counters and Flags + reg [2:0] ce_count = 0; + reg [2:0] edge_count = 0; + reg [2:0] RisingEdgeCount = 0; + reg [2:0] FallingEdgeCount = 0; + reg TriggerOnRise; // FP + + reg allEqual=0, RisingEdgeMatch=0, FallingEdgeMatch=0, match=0, nmatch=0; + + reg divclk_int=0; + reg i1_int=0, i2_int=0; + +// Attribute settings + +// Other signals + reg attr_err_flag = 0; + tri0 GSR = glbl.GSR; + + + initial begin + ce_count = DIVIDE - 1; + allEqual = 0; + match = 0; + nmatch = 0; +// FP #1; +//------------------------------------------------- +//----- DIVIDE check +//------------------------------------------------- + case (DIVIDE) +// 1 : begin +// RisingEdgeCount = 3'b000; +// FallingEdgeCount = 3'b000; +// TriggerOnRise = 1; +// end + + 2 : begin + RisingEdgeCount = 3'b001; + FallingEdgeCount = 3'b000; + TriggerOnRise = 1; + end + + 3 : begin + RisingEdgeCount = 3'b010; + FallingEdgeCount = 3'b000; + TriggerOnRise = 0; + end + + 4 : begin + RisingEdgeCount = 3'b011; + FallingEdgeCount = 3'b001; + TriggerOnRise = 1; + end + + 5 : begin + RisingEdgeCount = 3'b100; + FallingEdgeCount = 3'b001; + TriggerOnRise = 0; + end + + 6 : begin + RisingEdgeCount = 3'b101; + FallingEdgeCount = 3'b010; + TriggerOnRise = 1; + end + + 7 : begin + RisingEdgeCount = 3'b110; + FallingEdgeCount = 3'b010; + TriggerOnRise = 0; + end + + 8 : begin + RisingEdgeCount = 3'b111; + FallingEdgeCount = 3'b011; + TriggerOnRise = 1; + end + + default : begin + $display("Attribute Syntax Error : The attribute DIVIDE on BUFIO2_2CLK instance %m is set to %d. Legal values for this attribute are 2, 3, 4, 5, 6, 7 or 8.", DIVIDE); + attr_err_flag = 1; + end + endcase // (DIVIDE) + +//------------------------------------------------- +//------ Other Initializations -------- +//------------------------------------------------- + + if (attr_err_flag) + begin + #1; + $finish; + end + + + end // initial begin + + +//----------------------------------------------------------------------------------- + +// ===================== +// clock doubler +// ===================== + always @(posedge I) begin + i1_int = 1; + #100 i1_int = 0; + end + + always @(posedge IB) begin + i2_int = 1; + #100 i2_int = 0; + end + + assign doubled_clk_int = i1_int | i2_int; + + +// ===================== +// Count the rising edges of the clk +// ===================== +// CR 512001 -- for various DIVIDE widths, the count is set differently to match the hw startup + generate + case(DIVIDE) + 2,4,6,8 : begin + + always @(posedge doubled_clk_int) begin + if($time < 1 ) + edge_count <= DIVIDE-1; //001 for 5 and 7 + else if (allEqual) + edge_count <= 3'b000; + else + edge_count <= edge_count + 1; + end + end + 3,5,7 : begin + //for 1, 3, 5 and 7 below + + always @(posedge doubled_clk_int) begin + if($time < 1 ) + edge_count <= 3'b001; //001 for 5 and 7 + else if (allEqual) + edge_count <= 3'b000; + else + edge_count <= edge_count + 1; + end + end + endcase + endgenerate + +// Generate synchronous reset after DIVIDE number of counts + always @(edge_count) + if (edge_count == ce_count) + allEqual = 1; + else + allEqual = 0; + +// ===================== +// Generate IOCE +// ===================== + always @(posedge doubled_clk_int) + serdesstrobe_out <= allEqual; + +// ===================== +// Generate IOCLK +// ===================== + always @(I) + ioclk_out <= I; + +// ===================== +// Generate Divided Clock +// ===================== + always @(edge_count) + if (edge_count == RisingEdgeCount) + RisingEdgeMatch = 1; + else + RisingEdgeMatch = 0; + + always @(edge_count) + if (edge_count == FallingEdgeCount) + FallingEdgeMatch = 1; + else + FallingEdgeMatch = 0; + + always @(posedge doubled_clk_int) +// if (GSR == 1'b0) + match <= RisingEdgeMatch | (match & ~FallingEdgeMatch); + + always @(negedge doubled_clk_int) +// if (GSR == 1'b0) + if(~TriggerOnRise) + nmatch <= match; + else + nmatch <= 0; + + always@(match or nmatch) divclk_int = match | nmatch; + +// IR 497760 fix + always @(divclk_int or doubled_clk_int) + divclk_out = (DIVIDE == 1)? ioclk_out : divclk_int; + + + + + assign DIVCLK = divclk_out; + assign IOCLK = ioclk_out; + assign SERDESSTROBE = serdesstrobe_out; + specify + + (I *> DIVCLK) = (100, 100); + (I *> IOCLK) = (0, 0); + (I *> SERDESSTROBE) = (100, 100); + (IB *> DIVCLK) = (100, 100); + (IB *> IOCLK) = (0, 0); + (IB *> SERDESSTROBE) = (100, 100); + endspecify + +endmodule // BUFIO2_2CLK + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/BUFIODQS.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/BUFIODQS.v new file mode 100644 index 0000000..3bb3ae1 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/BUFIODQS.v @@ -0,0 +1,87 @@ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2007 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / +// /___/ /\ Filename : BUFIODQS.v +// \ \ / \ Timestamp : Mon Jul 14 13:48:38 PDT 2008 +// \___\/\___\ +// +// Revision: +// 07/14/08 - Initial version. +// 03/20/09 - CR 513938 remove DELAY_BYPASS +// 05/12/09 - CR 521124 changed functionality as specified by hw. +// 09/01/09 - CR 532419 Changed default value of DQSMASK_ENABLE +// End Revision + +`timescale 1 ps / 1 ps + +module BUFIODQS (O, DQSMASK, I); + + parameter DQSMASK_ENABLE = "FALSE"; // TRUE, FALSE + + output O; + input DQSMASK; + input I; + + reg delay_bypass_attr; + reg dqsmask_enable_attr; + + wire o_out; + +// Other signals + reg attr_err_flag = 0; + +//---------------------------------------------------------------------- +//------------------------ Output Ports ------------------------------ +//---------------------------------------------------------------------- + buf buf_o(O, o_out); + + initial begin + +//------------------------------------------------- +//----- DQSMASK_ENABLE Check +//------------------------------------------------- + case (DQSMASK_ENABLE) + "TRUE" : dqsmask_enable_attr <= 1'b1; + "FALSE" :dqsmask_enable_attr <= 1'b0; + default : begin + $display("Attribute Syntax Error : The attribute DQSMASK_ENABLE on BUFIODQS instance %m is set to %s. Legal values for this attribute are TRUE or FALSE", DQSMASK_ENABLE); + attr_err_flag = 1; + end + endcase // (DQSMASK_ENABLE) + + if (attr_err_flag) + begin + #1; + $finish; + end + + end // initial begin + + reg q1, q2; + wire clk, dglitch_en; + + assign clk = (dglitch_en == 1'b1) ? I : 1'b0; + + always @(DQSMASK or clk) begin + if (DQSMASK == 1'b1) q1 = 0; + else #(300) if (clk == 1) q1 = 1; + end + + always @(DQSMASK or clk) begin + if (DQSMASK == 1'b1) q2 = 0; + else #(400) if (clk == 0) q2 = q1; + end + + assign dglitch_en = (~q2 | DQSMASK); + + assign o_out = (DQSMASK_ENABLE == "TRUE") ? clk : I; + + +endmodule // BUFIODQS diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/BUFPLL.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/BUFPLL.v new file mode 100644 index 0000000..8c91442 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/BUFPLL.v @@ -0,0 +1,284 @@ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2007 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Phase Locked Loop buffer for Spartan Series +// /___/ /\ Filename : BUFPLL.v +// \ \ / \ Timestamp : Mon Jun 9 13:50:25 PDT 2008 +// \___\/\___\ +// +// Revision: +// 06/09/08 - Initial version. +// 08/19/08 - IR 479918 -- added 100 ps latency to sequential paths. +// 02/10/09 - IR 505709 -- correlate SERDESSTROBE to GLCK +// 03/24/09 - CR 514119 -- sync output to LOCKED high signal +// 06/16/09 - CR 525221 -- added ENABLE_SYNC attribute +// End Revision + +`timescale 1 ps / 1 ps + +module BUFPLL (IOCLK, LOCK, SERDESSTROBE, GCLK, LOCKED, PLLIN); + + + + parameter integer DIVIDE = 1; // {1..8} + parameter ENABLE_SYNC = "TRUE"; + + + output IOCLK; + output LOCK; + output SERDESSTROBE; + + input GCLK; + input LOCKED; + input PLLIN; + + +// Output signals + reg ioclk_out = 0, lock_out = 0, serdesstrobe_out = 0; + +// Counters and Flags + reg [2:0] ce_count = 0; + reg [2:0] edge_count = 0; + reg [2:0] RisingEdgeCount = 0; + reg [2:0] FallingEdgeCount = 0; + reg TriggerOnRise = 0; + reg divclk_int; + + reg allEqual, RisingEdgeMatch, FallingEdgeMatch, match, nmatch; + + reg lock_src_indepn_attr = 0, lock_src_0_attr = 0, lock_src_1_attr= 0; + + reg enable_sync_strobe_out = 0, strobe_out = 0; + +// Attribute settings + +// Other signals + reg attr_err_flag = 0; + tri0 GSR = glbl.GSR; + + + + + initial begin + //--- clk + allEqual = 0; + ce_count = DIVIDE - 1; + match = 0; + nmatch = 0; + +//------------------------------------------------- +//----- DIVIDE check +//------------------------------------------------- + case (DIVIDE) + 1 : begin + RisingEdgeCount = 3'b000; + FallingEdgeCount = 3'b000; + TriggerOnRise = 1; + end + + 2 : begin + RisingEdgeCount = 3'b001; + FallingEdgeCount = 3'b000; + TriggerOnRise = 1; + end + + 3 : begin + RisingEdgeCount = 3'b010; + FallingEdgeCount = 3'b000; + TriggerOnRise = 0; + end + + 4 : begin + RisingEdgeCount = 3'b011; + FallingEdgeCount = 3'b001; + TriggerOnRise = 1; + end + + 5 : begin + RisingEdgeCount = 3'b100; + FallingEdgeCount = 3'b001; + TriggerOnRise = 0; + end + + 6 : begin + RisingEdgeCount = 3'b101; + FallingEdgeCount = 3'b010; + TriggerOnRise = 1; + end + + 7 : begin + RisingEdgeCount = 3'b110; + FallingEdgeCount = 3'b010; + TriggerOnRise = 0; + end + + 8 : begin + RisingEdgeCount = 3'b111; + FallingEdgeCount = 3'b011; + TriggerOnRise = 1; + end + + default : begin + $display("Attribute Syntax Error : The attribute DIVIDE on BUFPLL instance %m is set to %d. Legal values for this attribute are 1, 2, 3, 4, 5, 6, 7 or 8.", DIVIDE); + attr_err_flag = 1; + end + endcase // (DIVIDE) + + //-------- ENABLE_SYNC + + case (ENABLE_SYNC) + "TRUE", "FALSE" : ; + default : begin + $display("Attribute Syntax Error : The attribute ENABLE_SYNC on BUFPLL instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", ENABLE_SYNC); + $finish; + end + endcase + +//------------------------------------------------- +//------ Other Initializations -------- +//------------------------------------------------- + + if (attr_err_flag) + begin + #1; + $finish; + end + + + end // initial begin + + +// ===================== +// Count the rising edges of the clk +// ===================== + always @(posedge PLLIN) begin + if(allEqual) + edge_count <= 3'b000; + else + edge_count <= edge_count + 1; + end + +// Generate synchronous reset after DIVIDE number of counts + always @(edge_count) + if (edge_count == ce_count) + allEqual = 1; + else + allEqual = 0; + +// ======================================= +// Generate SERDESSTROBE when ENABLE_SYNC +// ======================================= + reg time_cal = 0; + time clkin_edge = 0; + time clkin_period = 0; + time start_wait_time = 0; + time end_wait_time = 0; + + always @(posedge PLLIN) + begin + if((time_cal == 0) && (LOCKED == 1'b1)) begin + clkin_edge <= $time; + if (clkin_edge != 0 ) begin + clkin_period = $time - clkin_edge; + time_cal <= 1; + + start_wait_time <= (clkin_period)* ((2.0 *(DIVIDE-1))/4.0); + end_wait_time <= clkin_period; + end + end + end + + generate + case(DIVIDE) + 1: begin + always @(posedge GCLK) + begin + if(time_cal == 1) begin + #start_wait_time; + enable_sync_strobe_out <= 1'b1; + end + end + end + + 2, 3, 4, 5, 6, 7, 8: begin + always @(posedge GCLK) + begin + if(time_cal == 1) begin + #start_wait_time; + enable_sync_strobe_out <= 1'b1; + #end_wait_time; + enable_sync_strobe_out <= 1'b0; + end + end + end + endcase + endgenerate + +// ===================== +// Generate divided clk +// ===================== + always @(edge_count) + if (edge_count == RisingEdgeCount) + RisingEdgeMatch = 1; + else + RisingEdgeMatch = 0; + + always @(edge_count) + if (edge_count == FallingEdgeCount) + FallingEdgeMatch = 1; + else + FallingEdgeMatch = 0; + + always @(posedge PLLIN) + match <= RisingEdgeMatch | (match & ~FallingEdgeMatch); + + always @(negedge PLLIN) + if(~TriggerOnRise) + nmatch <= match; + else + nmatch <= 0; + + always@(match or nmatch) divclk_int = match | nmatch; + + always @(PLLIN) + ioclk_out <= PLLIN; + +// ===================== +// Generate strobe_out +// ===================== + always @(posedge PLLIN) + strobe_out <= allEqual; + +// ========================= +// Generate serdesstrobe_out +// ========================= + + always @(strobe_out or enable_sync_strobe_out) + serdesstrobe_out = (ENABLE_SYNC == "TRUE")? enable_sync_strobe_out : strobe_out; + +// ===================== +// Generate LOCK +// ===================== + always @(LOCKED) + lock_out <= LOCKED; + + + + assign IOCLK = ioclk_out; + assign LOCK = lock_out; + assign SERDESSTROBE = serdesstrobe_out; + + specify + ( PLLIN => IOCLK) = (0, 0); + ( PLLIN => LOCK) = (0, 0); + ( PLLIN => SERDESSTROBE) = (100, 100); + endspecify + +endmodule // BUFPLL + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/BUFPLL_MCB.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/BUFPLL_MCB.v new file mode 100644 index 0000000..2f91b9b --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/BUFPLL_MCB.v @@ -0,0 +1,298 @@ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2007 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Double Phase Locked Loop buffers for Spartan Series +// /___/ /\ Filename : BUFPLL_MCB.v +// \ \ / \ Timestamp : Mon Jun 9 13:50:25 PDT 2008 +// \___\/\___\ +// +// Revision: +// 08/12/08 - Initial version. +// 08/19/08 - IR 479918 fix ... added 100 ps latency to sequential paths. +// 03/25/09 - CR 516636 -- Fixed output clocks in simprim +// 04/07/09 - CR 517605 -- Removed 100 ps path delays in simprims IOCLK{0/1} +// 11/04/09 - CR 537806 -- Removed extra timing arcs +// 06/02/10 - CR 563356 -- Added ports GCLK, LOCKED and LOCK +// End Revision + +`timescale 1 ps / 1 ps + +module BUFPLL_MCB ( + IOCLK0, + IOCLK1, + LOCK, + SERDESSTROBE0, + SERDESSTROBE1, + + GCLK, + LOCKED, + PLLIN0, + PLLIN1 +); + + + + parameter integer DIVIDE = 2; // {1..8} + parameter LOCK_SRC = "LOCK_TO_0"; + + + output IOCLK0; + output IOCLK1; + output LOCK; + output SERDESSTROBE0; + output SERDESSTROBE1; + + input GCLK; + input LOCKED; + input PLLIN0; + input PLLIN1; + + +// Output signals + reg ioclk0_out = 0, ioclk1_out = 0, lock_out = 0, serdesstrobe0_out = 0, serdesstrobe1_out = 0; + +// Counters and Flags + reg [2:0] ce_count = 0; + reg [2:0] edge_count = 0; + reg [2:0] RisingEdgeCount = 0; + reg [2:0] FallingEdgeCount = 0; + reg TriggerOnRise = 0; + reg divclk_int; + + reg allEqual, RisingEdgeMatch, FallingEdgeMatch, match, nmatch; + + reg lock_src_0_attr = 0, lock_src_1_attr= 0; + +// Attribute settings + +// Other signals + reg attr_err_flag = 0; + tri0 GSR = glbl.GSR; + + + + + + + initial begin + //--- clk + allEqual = 0; + ce_count = DIVIDE - 1; + match = 0; + nmatch = 0; + +//------------------------------------------------- +//----- DIVIDE check +//------------------------------------------------- + case (DIVIDE) + 1 : begin + RisingEdgeCount = 3'b000; + FallingEdgeCount = 3'b000; + TriggerOnRise = 1; + end + + 2 : begin + RisingEdgeCount = 3'b001; + FallingEdgeCount = 3'b000; + TriggerOnRise = 1; + end + + 3 : begin + RisingEdgeCount = 3'b010; + FallingEdgeCount = 3'b000; + TriggerOnRise = 0; + end + + 4 : begin + RisingEdgeCount = 3'b011; + FallingEdgeCount = 3'b001; + TriggerOnRise = 1; + end + + 5 : begin + RisingEdgeCount = 3'b100; + FallingEdgeCount = 3'b001; + TriggerOnRise = 0; + end + + 6 : begin + RisingEdgeCount = 3'b101; + FallingEdgeCount = 3'b010; + TriggerOnRise = 1; + end + + 7 : begin + RisingEdgeCount = 3'b110; + FallingEdgeCount = 3'b010; + TriggerOnRise = 0; + end + + 8 : begin + RisingEdgeCount = 3'b111; + FallingEdgeCount = 3'b011; + TriggerOnRise = 1; + end + + default : begin + $display("Attribute Syntax Error : The attribute DIVIDE on BUFPLL_MCB instance %m is set to %d. Legal values for this attribute are 1, 2, 3, 4, 5, 6, 7 or 8.", DIVIDE); + attr_err_flag = 1; + end + endcase // (DIVIDE) + +//------------------------------------------------- +//----- LOCK_SRC check +//------------------------------------------------- + case (LOCK_SRC) + "LOCK_TO_0" : lock_src_0_attr <= 1'b1; + "LOCK_TO_1" : lock_src_1_attr <= 1'b1; + default : begin + $display("Attribute Syntax Error : The attribute LOCK_SRC on BUFPLL_MCB instance %m is set to %s. Legal values for this attribute are LOCK_TO_0 or LOCK_TO_1", LOCK_SRC); + attr_err_flag = 1; + end + endcase // (LOCK_SRC) + + +//------------------------------------------------- +//------ Other Initializations -------- +//------------------------------------------------- + + if (attr_err_flag) + begin + #1; + $finish; + end + + + end // initial begin + + +// ===================== +// Count the rising edges of the clk +// ===================== + generate if (LOCK_SRC == "LOCK_TO_0") + begin + always @(posedge PLLIN0) + if(allEqual) + edge_count <= 3'b000; + else + edge_count <= edge_count + 1; + end + else + begin + always @(posedge PLLIN1) + if(allEqual) + edge_count <= 3'b000; + else + edge_count <= edge_count + 1; + end + endgenerate + +// Generate synchronous reset after DIVIDE number of counts + always @(edge_count) + if (edge_count == ce_count) + allEqual = 1; + else + allEqual = 0; + +// ===================== +// Generate SERDESSTROBE +// ===================== + generate if(LOCK_SRC == "LOCK_TO_0") + begin + always @(posedge PLLIN0) + serdesstrobe0_out <= allEqual; + always @(posedge PLLIN1) + serdesstrobe1_out <= serdesstrobe0_out; + end + else + begin + always @(posedge PLLIN1) + serdesstrobe1_out <= allEqual; + always @(posedge PLLIN0) + serdesstrobe0_out <= serdesstrobe1_out; + end + endgenerate + +// ===================== +// Generate divided clk +// ===================== + always @(edge_count) + if (edge_count == RisingEdgeCount) + RisingEdgeMatch = 1; + else + RisingEdgeMatch = 0; + + always @(edge_count) + if (edge_count == FallingEdgeCount) + FallingEdgeMatch = 1; + else + FallingEdgeMatch = 0; + + generate if(LOCK_SRC == "LOCK_TO_0") + begin + always @(posedge PLLIN0) + match <= RisingEdgeMatch | (match & ~FallingEdgeMatch); + + always @(negedge PLLIN0) + if(~TriggerOnRise) + nmatch <= match; + else + nmatch <= 0; + end + else + begin + always @(posedge PLLIN1) + match <= RisingEdgeMatch | (match & ~FallingEdgeMatch); + + always @(negedge PLLIN1) + if(~TriggerOnRise) + nmatch <= match; + else + nmatch <= 0; + end + endgenerate + + always@(match or nmatch) divclk_int = match | nmatch; +// ===================== +// Generate IOCLKs +// ===================== + + always @(PLLIN0) + ioclk0_out = PLLIN0; + + always @(PLLIN1) + ioclk1_out = PLLIN1; + +// ===================== +// Generate LOCK +// ===================== + always @(LOCKED) + lock_out <= LOCKED; + + + assign IOCLK0 = ioclk0_out; + assign IOCLK1 = ioclk1_out; + assign LOCK = lock_out; + assign SERDESSTROBE0 = serdesstrobe0_out; + assign SERDESSTROBE1 = serdesstrobe1_out; + + specify + ( PLLIN0 => IOCLK0) = (0, 0); + ( PLLIN0 => IOCLK1) = (0, 0); + ( PLLIN0 => LOCK) = (0, 0); + ( PLLIN0 => SERDESSTROBE0) = (100, 100); + ( PLLIN0 => SERDESSTROBE1) = (100, 100); + ( PLLIN1 => IOCLK0) = (0, 0); + ( PLLIN1 => IOCLK1) = (0, 0); + ( PLLIN1 => SERDESSTROBE0) = (100, 100); + ( PLLIN1 => SERDESSTROBE1) = (100, 100); + endspecify + +endmodule // BUFPLL_MCB + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/BUFR.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/BUFR.v new file mode 100644 index 0000000..5a29d5d --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/BUFR.v @@ -0,0 +1,179 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/virtex4/BUFR.v,v 1.15 2010/02/22 23:41:05 yanx Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Regional Clock Buffer +// /___/ /\ Filename : BUFR.v +// \ \ / \ Timestamp : Thu Mar 25 16:43:43 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 03/11/05 - Initialized outpus. +// 04/04/2005 - Add SIM_DEVICE paramter to support rainier. CE pin has 4 clock +// latency for Virtex 4 and none for Rainier +// 07/25/05 - Updated names to Virtex5 +// 08/31/05 - Add ce_en to sensitivity list of i_in which make ce asynch. +// 05/23/06 - Add count =0 and first_rise=1 when CE = 0 (CR 232206). +// 07/19/06 - Add wire declaration for undeclared wire signals. +// 04/01/09 - CR 517236 -- Added VIRTEX6 support +// 02/23/10 - Use assign for o_out (CR543271) +// End Revision + +`timescale 1 ps / 1 ps + +module BUFR (O, CE, CLR, I); + + output O; + + input CE; + input CLR; + tri0 GSR = glbl.GSR; + input I; + + parameter BUFR_DIVIDE = "BYPASS"; + parameter SIM_DEVICE = "VIRTEX4"; + + integer count, period_toggle, half_period_toggle; + reg first_rise, half_period_done; + reg o_out_divide = 0; + wire o_out; + reg ce_enable1, ce_enable2, ce_enable3, ce_enable4; + wire i_in, ce_in, clr_in, gsr_in, ce_en; + + buf buf_i (i_in, I); + buf buf_ce (ce_in, CE); + buf buf_clr (clr_in, CLR); + buf buf_gsr (gsr_in, GSR); + buf buf_o (O, o_out); + + + initial begin + case (BUFR_DIVIDE) + "BYPASS" : period_toggle = 0; + "1" : begin + period_toggle = 1; + half_period_toggle = 1; + end + "2" : begin + period_toggle = 2; + half_period_toggle = 2; + end + "3" : begin + period_toggle = 4; + half_period_toggle = 2; + end + "4" : begin + period_toggle = 4; + half_period_toggle = 4; + end + "5" : begin + period_toggle = 6; + half_period_toggle = 4; + end + "6" : begin + period_toggle = 6; + half_period_toggle = 6; + end + "7" : begin + period_toggle = 8; + half_period_toggle = 6; + end + "8" : begin + period_toggle = 8; + half_period_toggle = 8; + end + default : begin + $display("Attribute Syntax Error : The attribute BUFR_DIVIDE on BUFR instance %m is set to %s. Legal values for this attribute are BYPASS, 1, 2, 3, 4, 5, 6, 7 or 8.", BUFR_DIVIDE); + $finish; + end + endcase // case(BUFR_DIVIDE) + + case (SIM_DEVICE) + "VIRTEX4" : ; + "VIRTEX5" : ; + "VIRTEX6" : ; + default : begin + $display("Attribute Syntax Error : The attribute SIM_DEVICE on BUFR instance %m is set to %s. Legal values for this attribute are VIRTEX4 or VIRTEX5 or VIRTEX6.", SIM_DEVICE); + $finish; + end + endcase + end // initial begin + + + always @(gsr_in or clr_in) + if (gsr_in == 1'b1 || clr_in == 1'b1) begin + assign o_out_divide = 1'b0; + assign count = 0; + assign first_rise = 1'b1; + assign half_period_done = 1'b0; + if (gsr_in == 1'b1) begin + assign ce_enable1 = 1'b0; + assign ce_enable2 = 1'b0; + assign ce_enable3 = 1'b0; + assign ce_enable4 = 1'b0; + end + end + else if (gsr_in == 1'b0 || clr_in == 1'b0) begin + deassign o_out_divide; + deassign count; + deassign first_rise; + deassign half_period_done; + if (gsr_in == 1'b0) begin + deassign ce_enable1; + deassign ce_enable2; + deassign ce_enable3; + deassign ce_enable4; + end + end + + initial ce_enable4 =0; + + + always @(negedge i_in) + begin + ce_enable1 <= ce_in; + ce_enable2 <= ce_enable1; + ce_enable3 <= ce_enable2; + ce_enable4 <= ce_enable3; + end + + assign ce_en = ((SIM_DEVICE == "VIRTEX5") || (SIM_DEVICE == "VIRTEX6")) ? ce_in : ce_enable4; + + always @(i_in or ce_en) + if (ce_en == 1'b1) begin + if (i_in == 1'b1 && first_rise == 1'b1) begin + o_out_divide = 1'b1; + first_rise = 1'b0; + end + else if (count == half_period_toggle && half_period_done == 1'b0) begin + o_out_divide = ~o_out_divide; + half_period_done = 1'b1; + count = 0; + end + else if (count == period_toggle && half_period_done == 1'b1) begin + o_out_divide = ~o_out_divide; + half_period_done = 1'b0; + count = 0; + end + + if (first_rise == 1'b0) + count = count + 1; + end // if (ce_in == 1'b1) + else begin + count = 0; + first_rise = 1; + end + + + assign o_out = (period_toggle == 0) ? i_in : o_out_divide; + + + +endmodule // BUFR diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/BUFT.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/BUFT.v new file mode 100644 index 0000000..0067c4d --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/BUFT.v @@ -0,0 +1,33 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/BUFT.v,v 1.6 2007/05/23 21:43:33 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Internal 3-State Buffers with Active Low Enable +// /___/ /\ Filename : BUFT.v +// \ \ / \ Timestamp : Thu Mar 25 16:42:14 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. + +`timescale 1 ps / 1 ps + + +module BUFT (O, I, T); + + output O; + + input I, T; + + bufif0 T1 (O, I, T); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/CAPTURE_FPGACORE.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/CAPTURE_FPGACORE.v new file mode 100644 index 0000000..d1dc255 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/CAPTURE_FPGACORE.v @@ -0,0 +1,31 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/CAPTURE_FPGACORE.v,v 1.7 2007/05/23 21:43:33 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Register State Capture for Bitstream Readback for FPGACORE +// /___/ /\ Filename : CAPTURE_FPGACORE.v +// \ \ / \ Timestamp : Thu Mar 25 16:42:14 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 07/23/05 - Added ONESHOT to all CAPUTURE comps; CR # 212645 +// 01/19/06 - made ONESHOT false; CR # 220151 +// 05/23/07 - Changed timescale to 1 ps / 1 ps. + +`timescale 1 ps / 1 ps + + +module CAPTURE_FPGACORE (CAP, CLK); + + input CAP, CLK; + + parameter ONESHOT = "FALSE"; + +endmodule diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/CAPTURE_SPARTAN3.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/CAPTURE_SPARTAN3.v new file mode 100644 index 0000000..c5f79a2 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/CAPTURE_SPARTAN3.v @@ -0,0 +1,32 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/CAPTURE_SPARTAN3.v,v 1.7 2007/05/23 21:43:33 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Register State Capture for Bitstream Readback for SPARTAN3 +// /___/ /\ Filename : CAPTURE_SPARTAN3.v +// \ \ / \ Timestamp : Thu Mar 25 16:42:15 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 07/23/05 - Added ONESHOT to all CAPUTURE comps; CR # 212645 +// 01/19/06 - made ONESHOT false; CR # 220151 +// 05/23/07 - Changed timescale to 1 ps / 1 ps. + +`timescale 1 ps / 1 ps + + +module CAPTURE_SPARTAN3 (CAP, CLK); + + input CAP, CLK; + + parameter ONESHOT = "FALSE"; + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/CAPTURE_SPARTAN3A.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/CAPTURE_SPARTAN3A.v new file mode 100644 index 0000000..c1b2b6f --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/CAPTURE_SPARTAN3A.v @@ -0,0 +1,28 @@ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Register State Capture for Bitstream Readback for SPARTAN3A +// /___/ /\ Filename : CAPTURE_SPARTAN3A.v +// \ \ / \ Timestamp : Fri Jul 1 14:45:00 PDT 2005 +// \___\/\___\ +// +// Revision: +// 07/01/05 - Initial version. +// End Revision + +`timescale 1 ps / 1 ps + + +module CAPTURE_SPARTAN3A (CAP, CLK); + + input CAP, CLK; + + parameter ONESHOT = "TRUE"; + +endmodule diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/CAPTURE_VIRTEX4.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/CAPTURE_VIRTEX4.v new file mode 100644 index 0000000..9c3517a --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/CAPTURE_VIRTEX4.v @@ -0,0 +1,31 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/virtex4/CAPTURE_VIRTEX4.v,v 1.4 2007/06/06 22:14:07 fphillip Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Register State Capture for Bitstream Readback for VIRTEX4 +// /___/ /\ Filename : CAPTURE_VIRTEX4.v +// \ \ / \ Timestamp : Thu Mar 25 16:43:43 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 06/06/07 - Fixed timescale values +// End Revision + + +`timescale 1 ps / 1 ps + + +module CAPTURE_VIRTEX4 (CAP, CLK); + + input CAP, CLK; + + parameter ONESHOT = "TRUE"; + +endmodule diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/CAPTURE_VIRTEX5.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/CAPTURE_VIRTEX5.v new file mode 100644 index 0000000..40400b6 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/CAPTURE_VIRTEX5.v @@ -0,0 +1,35 @@ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Register State Capture for Bitstream Readback for VIRTEX5 +// /___/ /\ Filename : CAPTURE_VIRTEX5.v +// \ \ / \ Timestamp : Thu Jul 21 13:42:30 PDT 2005 +// \___\/\___\ +// +// Revision: +// 07/21/05 - Initial version. +// End Revision + +`timescale 1 ps / 1 ps + +module CAPTURE_VIRTEX5 ( + CAP, + CLK +); + +input CAP; +input CLK; + +parameter ONESHOT = "TRUE"; + +specify + specparam PATHPULSE$ = 0; +endspecify + +endmodule diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/CAPTURE_VIRTEX6.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/CAPTURE_VIRTEX6.v new file mode 100644 index 0000000..e47148b --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/CAPTURE_VIRTEX6.v @@ -0,0 +1,31 @@ +/////////////////////////////////////////////////////// +// Copyright (c) 1995/2006 Xilinx Inc. +// All Right Reserved. +/////////////////////////////////////////////////////// +// +// ____ ___ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : +// / / +// /__/ /\ Filename : CAPTURE_VIRTEX6.v +// \ \ / \ +// \__\/\__ \ +// +// Revision: 1.0 +/////////////////////////////////////////////////////// + +`timescale 1 ps / 1 ps + +module CAPTURE_VIRTEX6 ( + CAP, + CLK +); + parameter ONESHOT = "TRUE"; + + + input CAP; + input CLK; + +endmodule diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/CARRY4.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/CARRY4.v new file mode 100644 index 0000000..fbc1e4a --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/CARRY4.v @@ -0,0 +1,60 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/rainier/CARRY4.v,v 1.5 2007/06/01 00:24:45 yanx Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Fast Carry Logic with Look Ahead +// /___/ /\ Filename : CARRY4.v +// \ \ / \ Timestamp : Thu Mar 25 16:42:55 PST 2004 +// \___\/\___\ +// +// Revision: +// 04/11/05 - Initial version. +// 05/06/05 - Unused CYINT or CI pin need grounded instead of open (CR207752) +// 05/31/05 - Change pin order, remove connection check for CYINIT and CI. +// 05/30/07 - Change timescale to 1 ps / 1ps. +// End Revision + +`timescale 1 ps / 1 ps + + +module CARRY4 (CO, O, CI, CYINIT, DI, S); + + output [3:0] CO; + output [3:0] O; + input CI; + input CYINIT; + input [3:0] DI; + input [3:0] S; + + wire ci_or_cyinit; + +// initial +// ci_or_cyinit = 0; + + assign O = S ^ {CO[2:0], ci_or_cyinit}; + assign CO[0] = S[0] ? ci_or_cyinit : DI[0]; + assign CO[1] = S[1] ? CO[0] : DI[1]; + assign CO[2] = S[2] ? CO[1] : DI[2]; + assign CO[3] = S[3] ? CO[2] : DI[3]; + assign ci_or_cyinit = CYINIT | CI; + +// always @(CYINIT or CI) +// if (CYINIT === 1'bz || CYINIT === 1'bx) begin +// $display("Error: CARRY4 instance, %m, detects CYINIT unconnected. Only one of CI and CYINIT inputs can be used and other one need be grounded."); +// $finish; +// end +// else if (CI=== 1'bz || CI=== 1'bx) begin +// $display("Error: CARRY4 instance, %m, detects CI unconnected. Only one of CI and CYINIT inputs can be used and other one need be grounded."); +// $finish; +// end +// else +// ci_or_cyinit = CYINIT | CI; + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/CFGLUT5.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/CFGLUT5.v new file mode 100644 index 0000000..940b481 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/CFGLUT5.v @@ -0,0 +1,56 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/rainier/CFGLUT5.v,v 1.1 2006/02/01 21:08:56 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / 5-input Dynamically Reconfigurable Look-Up-Table with Carry and Clock Enable +// /___/ /\ Filename : CFGLUT5.v +// \ \ / \ Timestamp : Thu Mar 25 16:43:40 PST 2004 +// \___\/\___\ +// +// Revision: +// 12/27/05 - Initial version. +// End Revision + +`timescale 1 ps / 1 ps + + +module CFGLUT5 (CDO, O5, O6, CDI, CE, CLK, I0, I1, I2, I3, I4); + + parameter INIT = 32'h00000000; + + output CDO; + output O5; + output O6; + + input I4, I3, I2, I1, I0; + input CDI, CE, CLK; + + reg [31:0] data; + + + assign O6 = data[{I4, I3, I2, I1, I0}]; + assign O5 = data[{I3, I2, I1, I0}]; + assign CDO = data[31]; + + initial + begin + assign data = INIT; + while (CLK === 1'b1 || CLK===1'bX) + #10; + deassign data; + end + + always @(posedge CLK) + if (CE == 1'b1) begin + data <= #100 {data[30:0], CDI}; + end + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/CLKDLL.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/CLKDLL.v new file mode 100644 index 0000000..0b2fcb5 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/CLKDLL.v @@ -0,0 +1,472 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/CLKDLL.v,v 1.14 2006/05/26 21:59:24 yanx Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ UNISIM : Xilinx Functional Simulation Library Component +// / / Clock Delay Locked Loop +// /___/ /\ Filename : CLKDLL.v +// \ \ / \ Timestamp : Thu Mar 25 16:42:15 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 03/11/05 - Add GSR global signal. +// 03/18/05 - Change RST check from 3 clkin cycles to 2 ns (CR200477). +// 03/14/06 - Add parameter declaration (CR 226003) +// 05/25/06 - Remove GSR (232012). +// End Revision + +`timescale 1 ps / 1 ps + +module CLKDLL ( + CLK0, CLK180, CLK270, CLK2X, CLK90, CLKDV, LOCKED, + CLKFB, CLKIN, RST); + +parameter real CLKDV_DIVIDE = 2.0; +parameter DUTY_CYCLE_CORRECTION = "TRUE"; +parameter FACTORY_JF = 16'hC080; // non-simulatable +localparam integer MAXPERCLKIN = 40000; // simulation parameter +localparam integer SIM_CLKIN_CYCLE_JITTER = 300; // simulation parameter +localparam integer SIM_CLKIN_PERIOD_JITTER = 1000; // simulation parameter +parameter STARTUP_WAIT = "FALSE"; // non-simulatable + +input CLKFB, CLKIN, RST; + +output CLK0, CLK180, CLK270, CLK2X, CLK90, CLKDV, LOCKED; + +reg CLK0, CLK180, CLK270, CLK2X, CLK90, CLKDV; + +wire clkfb_in, clkin_in, rst_in; +wire clk0_out; +reg clk2x_out, clkdv_out, locked_out; + +reg [1:0] clkfb_type; +reg [8:0] divide_type; +reg clk1x_type; + +reg lock_period, lock_delay, lock_clkin, lock_clkfb; +reg [1:0] lock_out; +reg lock_fb; +reg fb_delay_found; +reg clock_stopped; + +reg clkin_ps; +reg clkin_fb; + +time clkin_edge; +time clkin_ps_edge; +time delay_edge; +time clkin_period [2:0]; +time period; +time period_ps; +time period_orig; +time clkout_delay; +time fb_delay; +time period_dv_high, period_dv_low; +time cycle_jitter, period_jitter; + +reg clkin_window, clkfb_window; +reg clkin_5050; +reg [2:0] rst_reg; +reg [23:0] i, n, d, p; + + +reg notifier; + +initial begin + #1; + if ($realtime == 0) begin + $display ("Simulator Resolution Error : Simulator resolution is set to a value greater than 1 ps."); + $display ("In order to simulate the CLKDLL, the simulator resolution must be set to 1ps or smaller."); + $finish; + end +end + +initial begin + case (CLKDV_DIVIDE) + 1.5 : divide_type = 'd3; + 2.0 : divide_type = 'd4; + 2.5 : divide_type = 'd5; + 3.0 : divide_type = 'd6; + 4.0 : divide_type = 'd8; + 5.0 : divide_type = 'd10; + 8.0 : divide_type = 'd16; + 16.0 : divide_type = 'd32; + default : begin + $display("Attribute Syntax Error : The attribute CLKDV_DIVIDE on CLKDLL instance %m is set to %0.1f. Legal values for this attribute are 1.5, 2.0, 2.5, 3.0, 4.0, 5.0, 8.0 or 16.0.", CLKDV_DIVIDE); + $finish; + end + endcase + + clkfb_type = 2; + + period_jitter = SIM_CLKIN_PERIOD_JITTER; + cycle_jitter = SIM_CLKIN_CYCLE_JITTER; + + case (DUTY_CYCLE_CORRECTION) + "false" : clk1x_type <= 0; + "FALSE" : clk1x_type <= 0; + "true" : clk1x_type <= 1; + "TRUE" : clk1x_type <= 1; + default : begin + $display("Attribute Syntax Error : The attribute DUTY_CYCLE_CORRECTION on CLKDLL instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", DUTY_CYCLE_CORRECTION); + $finish; + end + endcase + + case (STARTUP_WAIT) + "false" : ; + "FALSE" : ; + "true" : ; + "TRUE" : ; + default : begin + $display("Attribute Syntax Error : The attribute STARTUP_WAIT on CLKDLL instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", STARTUP_WAIT); + $finish; + end + endcase +end + +// +// input wire delays +// + +buf b_clkin (clkin_in, CLKIN); +buf b_clkfb (clkfb_in, CLKFB); +buf b_rst (rst_in, RST); +buf #100 b_locked (LOCKED, locked_out); + +clkdll_maximum_period_check #("CLKIN", MAXPERCLKIN) i_max_clkin (clkin_in, rst_in); + + +always @(clkin_in or rst_in) + if (rst_in == 1'b0) + clkin_ps <= clkin_in; + else if (rst_in == 1'b1) begin + clkin_ps <= 1'b0; + @(negedge rst_reg[2]); + end + +always @(clkin_ps or lock_fb) + clkin_fb <= #(period_ps) clkin_ps & lock_fb; + +always @(posedge clkin_ps) begin + clkin_ps_edge <= $time; + if (($time - clkin_ps_edge) <= (1.5 * period_ps)) + period_ps <= $time - clkin_ps_edge; + else if ((period_ps == 0) && (clkin_ps_edge != 0)) + period_ps <= $time - clkin_ps_edge; +end + +always @(posedge clkin_ps) + lock_fb <= lock_period; + +always @(period or fb_delay) + clkout_delay <= period - fb_delay; + +// +// generate master reset signal +// + +always @(posedge clkin_in) begin + rst_reg[0] <= rst_in; + rst_reg[1] <= rst_reg[0] & rst_in; + rst_reg[2] <= rst_reg[1] & rst_reg[0] & rst_in; +end + +time rst_tmp1, rst_tmp2; +initial +begin +rst_tmp1 = 0; +rst_tmp2 = 0; +end + + +always @(posedge rst_in or negedge rst_in) +begin + if (rst_in ==1) + rst_tmp1 <= $time; + else if (rst_in==0 ) begin + rst_tmp2 = $time - rst_tmp1; + if (rst_tmp2 < 2000 && rst_tmp2 != 0) + $display("Input Error : RST on instance %m must be asserted at least for 2 ns."); + end +end + + +initial begin + clk2x_out = 0; + clkdv_out = 0; + clkin_5050 = 0; + clkfb_window = 0; + clkin_period[0] = 0; + clkin_period[1] = 0; + clkin_period[2] = 0; + clkin_ps_edge = 0; + clkin_window = 0; + clkout_delay = 0; + clock_stopped = 1; + fb_delay = 0; + fb_delay_found = 0; + lock_clkfb = 0; + lock_clkin = 0; + lock_delay = 0; + lock_fb = 0; + lock_out = 2'b00; + lock_period = 0; + locked_out = 0; + period = 0; + period_ps = 0; + period_orig = 0; + rst_reg = 3'b000; +end + +always @(rst_in) begin + clkin_5050 <= 0; + clkfb_window <= 0; + clkin_period[0] <= 0; + clkin_period[1] <= 0; + clkin_period[2] <= 0; + clkin_ps_edge <= 0; + clkin_window <= 0; + clkout_delay <= 0; + clock_stopped <= 1; + fb_delay <= 0; + fb_delay_found <= 0; + lock_clkfb <= 0; + lock_clkin <= 0; + lock_delay <= 0; + lock_fb <= 0; + lock_out <= 2'b00; + lock_period <= 0; + locked_out <= 0; + period_ps <= 0; +end + +// +// determine clock period +// + +always @(posedge clkin_ps) begin + clkin_edge <= $time; + clkin_period[2] <= clkin_period[1]; + clkin_period[1] <= clkin_period[0]; + if (clkin_edge != 0) + clkin_period[0] <= $time - clkin_edge; +end + +always @(negedge clkin_ps) begin + if (lock_period == 1'b0) begin + if ((clkin_period[0] != 0) && + (clkin_period[0] - cycle_jitter <= clkin_period[1]) && + (clkin_period[1] <= clkin_period[0] + cycle_jitter) && + (clkin_period[1] - cycle_jitter <= clkin_period[2]) && + (clkin_period[2] <= clkin_period[1] + cycle_jitter)) begin + lock_period <= 1; + period_orig <= (clkin_period[0] + + clkin_period[1] + + clkin_period[2]) / 3; + period <= clkin_period[0]; + end + end + else if (lock_period == 1'b1) begin + if (100000000 < (clkin_period[0] / 1000)) begin + $display("Warning : CLKIN stopped toggling on instance %m exceeds %d ms. Current CLKIN Period = %1.3f ns.", 100, clkin_period[0] / 1000.0); + lock_period <= 0; + @(negedge rst_reg[2]); + end + else if ((period_orig * 2 < clkin_period[0]) && clock_stopped == 1'b0) begin + clkin_period[0] = clkin_period[1]; + clock_stopped = 1'b1; + end + else if ((clkin_period[0] < period_orig - period_jitter) || + (period_orig + period_jitter < clkin_period[0])) begin + $display("Warning : Input Clock Period Jitter on instance %m exceeds %1.3f ns. Locked CLKIN Period = %1.3f. Current CLKIN Period = %1.3f.", period_jitter / 1000.0, period_orig / 1000.0, clkin_period[0] / 1000.0); + lock_period <= 0; + @(negedge rst_reg[2]); + end + else if ((clkin_period[0] < clkin_period[1] - cycle_jitter) || + (clkin_period[1] + cycle_jitter < clkin_period[0])) begin + $display("Warning : Input Clock Cycle-Cycle Jitter on instance %m exceeds %1.3f ns. Previous CLKIN Period = %1.3f. Current CLKIN Period = %1.3f.", cycle_jitter / 1000.0, clkin_period[1] / 1000.0, clkin_period[0] / 1000.0); + lock_period <= 0; + @(negedge rst_reg[2]); + end + else begin + period <= clkin_period[0]; + clock_stopped = 1'b0; + end + end +end + +// +// determine clock delay +// + +always @(posedge lock_period) begin + if (lock_period && clkfb_type != 0) begin + if (clkfb_type == 1) begin + @(posedge CLK0 or rst_in) + delay_edge = $time; + end + else if (clkfb_type == 2) begin + @(posedge CLK2X or rst_in) + delay_edge = $time; + end + @(posedge clkfb_in or rst_in) + fb_delay = ($time - delay_edge) % period_orig; + end + fb_delay_found = 1; +end + +// +// determine feedback lock +// + +always @(posedge clkfb_in) begin + #0 clkfb_window <= 1; + #cycle_jitter clkfb_window <= 0; +end + +always @(posedge clkin_fb) begin + #0 clkin_window <= 1; + #cycle_jitter clkin_window <= 0; +end + +always @(posedge clkin_fb) begin + #1 + if (clkfb_window && fb_delay_found) + lock_clkin <= 1; + else + lock_clkin <= 0; +end + +always @(posedge clkfb_in) begin + #1 + if (clkin_window && fb_delay_found) + lock_clkfb <= 1; + else + lock_clkfb <= 0; +end + +always @(negedge clkin_fb) + lock_delay <= lock_clkin || lock_clkfb; + +// +// generate lock signal +// + +always @(posedge clkin_ps) begin + lock_out[0] <= lock_period & lock_delay & lock_fb; + lock_out[1] <= lock_out[0]; + locked_out <= lock_out[1]; +end + +// +// generate the clk1x_out +// + +always @(posedge clkin_ps) begin + clkin_5050 <= 1; + #(period / 2) + clkin_5050 <= 0; +end + +assign clk0_out = (clk1x_type) ? clkin_5050 : clkin_ps; + +// +// generate the clk2x_out +// + +always @(posedge clkin_ps) begin + clk2x_out <= 1; + #(period / 4) + clk2x_out <= 0; + if (lock_out[0]) begin + #(period / 4) + clk2x_out <= 1; + #(period / 4) + clk2x_out <= 0; + end + else begin + #(period / 2); + end +end + +// +// generate the clkdv_out +// + +always @(period) begin +// period_dv_high = (period / 2) * (divide_type / 2); +// period_dv_low = (period / 2) * (divide_type / 2 + divide_type % 2); + period_dv_high = (period * divide_type) / 4; + period_dv_low = (period * divide_type) / 4; +end + +always @(posedge clkin_ps) begin + if (lock_out[0]) begin + clkdv_out = 1'b1; + #(period_dv_high); + clkdv_out = 1'b0; + #(period_dv_low); + clkdv_out = 1'b1; + #(period_dv_high); + clkdv_out = 1'b0; + #(period_dv_low - period / 2); + end +end + +// +// generate all output signal +// + +always @(clk0_out) + CLK0 <= #(clkout_delay) clk0_out; + +always @(clk0_out) + CLK90 <= #(clkout_delay + period / 4) clk0_out; + +always @(clk0_out) + CLK180 <= #(clkout_delay + period / 2) clk0_out; + +always @(clk0_out) + CLK270 <= #(clkout_delay + (3 * period) / 4) clk0_out; + +always @(clk2x_out) + CLK2X <= #(clkout_delay) clk2x_out; + +always @(clkdv_out) + CLKDV <= #(clkout_delay) clkdv_out; + + +endmodule + +////////////////////////////////////////////////////// + +module clkdll_maximum_period_check (clock, rst); +parameter clock_name = ""; +parameter maximum_period = 0; +input clock; +input rst; + +time clock_edge; +time clock_period; + +initial begin + clock_edge = 0; + clock_period = 0; +end + +always @(posedge clock) begin + clock_edge <= $time; + clock_period <= $time - clock_edge; + if (clock_period > maximum_period && rst == 0) begin + $display("Warning : Input clock period of, %1.3f ns, on the %s port of instance %m exceeds allotted value of %1.3f ns at simulation time %1.3f ns.", clock_period/1000.0, clock_name, maximum_period/1000.0, $time/1000.0); + end +end +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/CLKDLLE.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/CLKDLLE.v new file mode 100644 index 0000000..b94b8a7 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/CLKDLLE.v @@ -0,0 +1,499 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/CLKDLLE.v,v 1.12 2006/05/26 21:59:24 yanx Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ UNISIM : Xilinx Functional Simulation Library Component +// / / Clock Delay Locked Loop for Virtex-E +// /___/ /\ Filename : CLKDLLE.v +// \ \ / \ Timestamp : Thu Mar 25 16:42:15 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 03/11/04 - Add GSR global signal. +// 03/18/05 - Change RST check from 3 clkin cycles to 2 ns (CR200477). +// 03/14/06 - Add parameter declaration (CR 226003) +// 05/25/06 - Remove GSR (232012). +// End Revision + +`timescale 1 ps / 1 ps + +module CLKDLLE ( + CLK0, CLK180, CLK270, CLK2X, CLK2X180, CLK90, CLKDV, LOCKED, + CLKFB, CLKIN, RST); + +parameter real CLKDV_DIVIDE = 2.0; +parameter DUTY_CYCLE_CORRECTION = "TRUE"; +parameter FACTORY_JF = 16'hC080; // non-simulatable +localparam integer MAXPERCLKIN = 40000; // simulation parameter +localparam integer SIM_CLKIN_CYCLE_JITTER = 300; // simulation parameter +localparam integer SIM_CLKIN_PERIOD_JITTER = 1000; // simulation parameter +parameter STARTUP_WAIT = "FALSE"; // non-simulatable + +input CLKFB, CLKIN, RST; + +output CLK0, CLK180, CLK270, CLK2X, CLK2X180, CLK90, CLKDV, LOCKED; + +reg CLK0, CLK180, CLK270, CLK2X, CLK2X180, CLK90, CLKDV; + +wire clkfb_in, clkin_in, rst_in; +wire clk0_out; +reg clk2x_out, clkdv_out, locked_out; + +reg [1:0] clkfb_type; +reg [8:0] divide_type; +reg clk1x_type; + +reg lock_period, lock_delay, lock_clkin, lock_clkfb; +reg [1:0] lock_out; +reg lock_fb; +reg fb_delay_found; +reg clock_stopped; + +reg clkin_ps; +reg clkin_fb; + +time clkin_edge; +time clkin_ps_edge; +time delay_edge; +time clkin_period [2:0]; +time period; +time period_ps; +time period_orig; +time clkout_delay; +time fb_delay; +time period_dv_high, period_dv_low; +time cycle_jitter, period_jitter; + +reg clkin_window, clkfb_window; +reg clkin_5050; +reg [2:0] rst_reg; +reg [23:0] i, n, d, p; + +reg notifier; + +initial begin + #1; + if ($realtime == 0) begin + $display ("Simulator Resolution Error : Simulator resolution is set to a value greater than 1 ps."); + $display ("In order to simulate the CLKDLLE, the simulator resolution must be set to 1ps or smaller."); + $finish; + end +end + +initial begin + case (CLKDV_DIVIDE) + 1.5 : divide_type <= 'd3; + 2.0 : divide_type <= 'd4; + 2.5 : divide_type <= 'd5; + 3.0 : divide_type <= 'd6; + 3.5 : divide_type <= 'd7; + 4.0 : divide_type <= 'd8; + 4.5 : divide_type <= 'd9; + 5.0 : divide_type <= 'd10; + 5.5 : divide_type <= 'd11; + 6.0 : divide_type <= 'd12; + 6.5 : divide_type <= 'd13; + 7.0 : divide_type <= 'd14; + 7.5 : divide_type <= 'd15; + 8.0 : divide_type <= 'd16; + 9.0 : divide_type <= 'd18; + 10.0 : divide_type <= 'd20; + 11.0 : divide_type <= 'd22; + 12.0 : divide_type <= 'd24; + 13.0 : divide_type <= 'd26; + 14.0 : divide_type <= 'd28; + 15.0 : divide_type <= 'd30; + 16.0 : divide_type <= 'd32; + default : begin + $display("Attribute Syntax Error : The attribute CLKDV_DIVIDE on CLKDLLE instance %m is set to %0.1f. Legal values for this attribute are 1.5, 2.0, 2.5, 3.0, 3.5, 4.0, 4.5, 5.0, 5.5, 6.0, 6.5, 7.0, 7.5, 8.0, 9.0, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0, or 16.0.", CLKDV_DIVIDE); + $finish; + end + endcase + + clkfb_type <= 2; + + period_jitter <= SIM_CLKIN_PERIOD_JITTER; + cycle_jitter <= SIM_CLKIN_CYCLE_JITTER; + + case (DUTY_CYCLE_CORRECTION) + "false" : clk1x_type <= 0; + "FALSE" : clk1x_type <= 0; + "true" : clk1x_type <= 1; + "TRUE" : clk1x_type <= 1; + default : begin + $display("Attribute Syntax Error : The attribute DUTY_CYCLE_CORRECTION on CLKDLLE instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", DUTY_CYCLE_CORRECTION); + $finish; + end + endcase + + case (STARTUP_WAIT) + "false" : ; + "FALSE" : ; + "true" : ; + "TRUE" : ; + default : begin + $display("Attribute Syntax Error : The attribute STARTUP_WAIT on CLKDLLE instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", STARTUP_WAIT); + $finish; + end + endcase +end + +// +// input wire delays +// + +buf b_clkin (clkin_in, CLKIN); +buf b_clkfb (clkfb_in, CLKFB); +buf b_rst (rst_in, RST); +buf #100 b_locked (LOCKED, locked_out); + + +clkdlle_maximum_period_check #("CLKIN", MAXPERCLKIN) i_max_clkin (clkin_in, rst_in); + +always @(clkin_in or rst_in) begin + if (rst_in == 1'b0) + clkin_ps <= clkin_in; + else if (rst_in == 1'b1) begin + clkin_ps <= 1'b0; + @(negedge rst_reg[2]); + end +end + +always @(clkin_ps or lock_fb) begin + clkin_fb <= #(period_ps) clkin_ps & lock_fb; +end + +always @(posedge clkin_ps) begin + clkin_ps_edge <= $time; + if (($time - clkin_ps_edge) <= (1.5 * period_ps)) + period_ps <= $time - clkin_ps_edge; + else if ((period_ps == 0) && (clkin_ps_edge != 0)) + period_ps <= $time - clkin_ps_edge; +end + +always @(posedge clkin_ps) begin + lock_fb <= lock_period; +end + +always @(period or fb_delay) + clkout_delay <= period - fb_delay; + +// +// generate master reset signal +// + +always @(posedge clkin_in) begin + rst_reg[0] <= rst_in; + rst_reg[1] <= rst_reg[0] & rst_in; + rst_reg[2] <= rst_reg[1] & rst_reg[0] & rst_in; +end + +time rst_tmp1, rst_tmp2; +initial +begin +rst_tmp1 = 0; +rst_tmp2 = 0; +end + + +always @(posedge rst_in or negedge rst_in) +begin + if (rst_in ==1) + rst_tmp1 <= $time; + else if (rst_in==0 ) begin + rst_tmp2 = $time - rst_tmp1; + if (rst_tmp2 < 2000 && rst_tmp2 != 0) + $display("Input Error : RST on instance %m must be asserted at least for 2 ns."); + end +end + +initial begin + clk2x_out <= 0; + clkdv_out <= 0; + clkin_5050 <= 0; + clkfb_window <= 0; + clkin_period[0] <= 0; + clkin_period[1] <= 0; + clkin_period[2] <= 0; + clkin_ps_edge <= 0; + clkin_window <= 0; + clkout_delay <= 0; + clock_stopped <= 1; + fb_delay <= 0; + fb_delay_found <= 0; + lock_clkfb <= 0; + lock_clkin <= 0; + lock_delay <= 0; + lock_fb <= 0; + lock_out <= 2'b00; + lock_period <= 0; + locked_out <= 0; + period <= 0; + period_ps <= 0; + period_orig <= 0; + rst_reg <= 3'b000; +end + +always @(rst_in) begin + clkin_5050 <= 0; + clkfb_window <= 0; + clkin_period[0] <= 0; + clkin_period[1] <= 0; + clkin_period[2] <= 0; + clkin_ps_edge <= 0; + clkin_window <= 0; + clkout_delay <= 0; + clock_stopped <= 1; + fb_delay <= 0; + fb_delay_found <= 0; + lock_clkfb <= 0; + lock_clkin <= 0; + lock_delay <= 0; + lock_fb <= 0; + lock_out <= 2'b00; + lock_period <= 0; + locked_out <= 0; + period_ps <= 0; +end + +// +// determine clock period +// + +always @(posedge clkin_ps) begin + clkin_edge <= $time; + clkin_period[2] <= clkin_period[1]; + clkin_period[1] <= clkin_period[0]; + if (clkin_edge != 0) + clkin_period[0] <= $time - clkin_edge; +end + +always @(negedge clkin_ps) begin + if (lock_period == 1'b0) begin + if ((clkin_period[0] != 0) && + (clkin_period[0] - cycle_jitter <= clkin_period[1]) && + (clkin_period[1] <= clkin_period[0] + cycle_jitter) && + (clkin_period[1] - cycle_jitter <= clkin_period[2]) && + (clkin_period[2] <= clkin_period[1] + cycle_jitter)) begin + lock_period <= 1; + period_orig <= (clkin_period[0] + + clkin_period[1] + + clkin_period[2]) / 3; + period <= clkin_period[0]; + end + end + else if (lock_period == 1'b1) begin + if (100000000 < (clkin_period[0] / 1000)) begin + $display("Warning : CLKIN stopped toggling on instance %m exceeds %d ms. Current CLKIN Period = %1.3f ns.", 100, clkin_period[0] / 1000.0); + lock_period <= 0; + @(negedge rst_reg[2]); + end + else if ((period_orig * 2 < clkin_period[0]) && clock_stopped == 1'b0) begin + clkin_period[0] = clkin_period[1]; + clock_stopped = 1'b1; + end + else if ((clkin_period[0] < period_orig - period_jitter) || + (period_orig + period_jitter < clkin_period[0])) begin + $display("Warning : Input Clock Period Jitter on instance %m exceeds %1.3f ns. Locked CLKIN Period = %1.3f. Current CLKIN Period = %1.3f.", period_jitter / 1000.0, period_orig / 1000.0, clkin_period[0] / 1000.0); + lock_period <= 0; + @(negedge rst_reg[2]); + end + else if ((clkin_period[0] < clkin_period[1] - cycle_jitter) || + (clkin_period[1] + cycle_jitter < clkin_period[0])) begin + $display("Warning : Input Clock Cycle-Cycle Jitter on instance %m exceeds %1.3f ns. Previous CLKIN Period = %1.3f. Current CLKIN Period = %1.3f.", cycle_jitter / 1000.0, clkin_period[1] / 1000.0, clkin_period[0] / 1000.0); + lock_period <= 0; + @(negedge rst_reg[2]); + end + else begin + period <= clkin_period[0]; + clock_stopped = 1'b0; + end + end +end + +// +// determine clock delay +// + +always @(posedge lock_period) begin + if (lock_period && clkfb_type != 0) begin + if (clkfb_type == 1) begin + @(posedge CLK0 or rst_in) + delay_edge = $time; + end + else if (clkfb_type == 2) begin + @(posedge CLK2X or rst_in) + delay_edge = $time; + end + @(posedge clkfb_in or rst_in) + fb_delay = ($time - delay_edge) % period_orig; + end + fb_delay_found = 1; +end + +// +// determine feedback lock +// + +always @(posedge clkfb_in) begin + #0 clkfb_window <= 1; + #cycle_jitter clkfb_window <= 0; +end + +always @(posedge clkin_fb) begin + #0 clkin_window <= 1; + #cycle_jitter clkin_window <= 0; +end + +always @(posedge clkin_fb) begin + #1 + if (clkfb_window && fb_delay_found) + lock_clkin <= 1; + else + lock_clkin <= 0; +end + +always @(posedge clkfb_in) begin + #1 + if (clkin_window && fb_delay_found) + lock_clkfb <= 1; + else + lock_clkfb <= 0; +end + +always @(negedge clkin_fb) begin + lock_delay <= lock_clkin || lock_clkfb; +end + +// +// generate lock signal +// + +always @(posedge clkin_ps) begin + lock_out[0] <= lock_period & lock_delay & lock_fb; + lock_out[1] <= lock_out[0]; + locked_out <= lock_out[1]; +end + +// +// generate the clk1x_out +// + +always @(posedge clkin_ps) begin + clkin_5050 <= 1; + #(period / 2) + clkin_5050 <= 0; +end + +assign clk0_out = (clk1x_type) ? clkin_5050 : clkin_ps; + +// +// generate the clk2x_out +// + +always @(posedge clkin_ps) begin + clk2x_out <= 1; + #(period / 4) + clk2x_out <= 0; + if (lock_out[0]) begin + #(period / 4) + clk2x_out <= 1; + #(period / 4) + clk2x_out <= 0; + end + else begin + #(period / 2); + end +end + +// +// generate the clkdv_out +// + +always @(period) begin +// period_dv_high = (period / 2) * (divide_type / 2); +// period_dv_low = (period / 2) * (divide_type / 2 + divide_type % 2); + period_dv_high = (period * divide_type) / 4; + period_dv_low = (period * divide_type) / 4; + +end + +always @(posedge clkin_ps) begin + if (lock_out[0]) begin + clkdv_out = 1'b1; + #(period_dv_high); + clkdv_out = 1'b0; + #(period_dv_low); + clkdv_out = 1'b1; + #(period_dv_high); + clkdv_out = 1'b0; + #(period_dv_low - period / 2); + end +end + +// +// generate all output signal +// + +always @(clk0_out) begin + CLK0 <= #(clkout_delay) clk0_out; +end + +always @(clk0_out) begin + CLK90 <= #(clkout_delay + period / 4) clk0_out; +end + +always @(clk0_out) begin + CLK180 <= #(clkout_delay + period / 2) clk0_out; +end + +always @(clk0_out) begin + CLK270 <= #(clkout_delay + (3 * period) / 4) clk0_out; +end + +always @(clk2x_out) begin + CLK2X <= #(clkout_delay) clk2x_out; +end + +always @(clk2x_out) begin + CLK2X180 <= #(clkout_delay + period / 4) clk2x_out; +end + +always @(clkdv_out) begin + CLKDV <= #(clkout_delay) clkdv_out; +end + + +endmodule + +////////////////////////////////////////////////////// + +module clkdlle_maximum_period_check (clock, rst); +parameter clock_name = ""; +parameter maximum_period = 0; +input clock; +input rst; + +time clock_edge; +time clock_period; + +initial begin + clock_edge <= 0; + clock_period <= 0; +end + +always @(posedge clock) begin + clock_edge <= $time; + clock_period <= $time - clock_edge; + if (clock_period > maximum_period && rst == 0) begin + $display("Warning : Input clock period of, %1.3f ns, on the %s port of instance %m exceeds allotted value of %1.3f ns at simulation time %1.3f ns.", clock_period/1000.0, clock_name, maximum_period/1000.0, $time/1000.0); + end +end +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/CLKDLLHF.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/CLKDLLHF.v new file mode 100644 index 0000000..442715e --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/CLKDLLHF.v @@ -0,0 +1,447 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/CLKDLLHF.v,v 1.11 2006/05/26 21:59:24 yanx Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ UNISIM : Xilinx Functional Simulation Library Component +// / / High Frequency Clcok Delay Locked Loop +// /___/ /\ Filename : CLKDLLHF.v +// \ \ / \ Timestamp : Thu Mar 25 16:42:15 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 03/11/05 - Add GSR global signal +// 03/18/05 - Change RST check from 3 clkin cycles to 2 ns (CR200477). +// 03/14/06 - Add parameter declaration (CR 226003) +// 05/25/06 - Remove GSR (232012). +// End Revision + +`timescale 1 ps / 1 ps + +module CLKDLLHF ( + CLK0, CLK180, CLKDV, LOCKED, + CLKFB, CLKIN, RST); + +parameter real CLKDV_DIVIDE = 2.0; +parameter DUTY_CYCLE_CORRECTION = "TRUE"; +parameter FACTORY_JF = 16'hFFF0; // non-simulatable +localparam integer MAXPERCLKIN = 40000; // simulation parameter +localparam integer SIM_CLKIN_CYCLE_JITTER = 300; // simulation parameter +localparam integer SIM_CLKIN_PERIOD_JITTER = 1000; // simulation parameter +parameter STARTUP_WAIT = "FALSE"; // non-simulatable + +input CLKFB, CLKIN, RST; + +output CLK0, CLK180, CLKDV, LOCKED; + +reg CLK0, CLK180, CLKDV; +reg CLK2X; + +wire clkfb_in, clkin_in, rst_in; +wire clk0_out; +reg clkdv_out, locked_out; + +reg [1:0] clkfb_type; +reg [8:0] divide_type; +reg clk1x_type; + +reg lock_period, lock_delay, lock_clkin, lock_clkfb; +reg [1:0] lock_out; +reg lock_fb; +reg fb_delay_found; +reg clock_stopped; + +reg clkin_ps; +reg clkin_fb; + +time clkin_edge; +time clkin_ps_edge; +time delay_edge; +time clkin_period [2:0]; +time period; +time period_ps; +time period_orig; +time clkout_delay; +time fb_delay; +time period_dv_high, period_dv_low; +time cycle_jitter, period_jitter; + +reg clkin_window, clkfb_window; +reg clkin_5050; +reg [2:0] rst_reg; +reg [23:0] i, n, d, p; + +reg notifier; + +initial begin + #1; + if ($realtime == 0) begin + $display ("Simulator Resolution Error : Simulator resolution is set to a value greater than 1 ps."); + $display ("In order to simulate the CLKDLLHF, the simulator resolution must be set to 1ps or smaller."); + $finish; + end +end + +initial begin + case (CLKDV_DIVIDE) + 1.5 : divide_type <= 'd3; + 2.0 : divide_type <= 'd4; + 2.5 : divide_type <= 'd5; + 3.0 : divide_type <= 'd6; + 4.0 : divide_type <= 'd8; + 5.0 : divide_type <= 'd10; + 8.0 : divide_type <= 'd16; + 16.0 : divide_type <= 'd32; + default : begin + $display("Attribute Syntax Error : The attribute CLKDV_DIVIDE on CLKDLLHF instance %m is set to %0.1f. Legal values for this attribute are 1.5, 2.0, 2.5, 3.0, 4.0, 5.0, 8.0 or 16.0.", CLKDV_DIVIDE); + $finish; + end + endcase + + clkfb_type <= 1; + + period_jitter <= SIM_CLKIN_PERIOD_JITTER; + cycle_jitter <= SIM_CLKIN_CYCLE_JITTER; + + case (DUTY_CYCLE_CORRECTION) + "false" : clk1x_type <= 0; + "FALSE" : clk1x_type <= 0; + "true" : clk1x_type <= 1; + "TRUE" : clk1x_type <= 1; + default : begin + $display("Attribute Syntax Error : The attribute DUTY_CYCLE_CORRECTION on CLKDLLHF instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", DUTY_CYCLE_CORRECTION); + $finish; + end + endcase + + case (STARTUP_WAIT) + "false" : ; + "FALSE" : ; + "true" : ; + "TRUE" : ; + default : begin + $display("Attribute Syntax Error : The attribute STARTUP_WAIT on CLKDLLHF instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", STARTUP_WAIT); + $finish; + end + endcase +end + +// +// input wire delays +// + +buf b_clkin (clkin_in, CLKIN); +buf b_clkfb (clkfb_in, CLKFB); +buf b_rst (rst_in, RST); +buf #100 b_locked (LOCKED, locked_out); + +clkdllhf_maximum_period_check #("CLKIN", MAXPERCLKIN) i_max_clkin (clkin_in, rst_in); + + +always @(clkin_in or rst_in) begin + if (rst_in == 1'b0) + clkin_ps <= clkin_in; + else if (rst_in == 1'b1) begin + clkin_ps <= 1'b0; + @(negedge rst_reg[2]); + end +end + +always @(clkin_ps or lock_fb) begin + clkin_fb <= #(period_ps) clkin_ps & lock_fb; +end + +always @(posedge clkin_ps) begin + clkin_ps_edge <= $time; + if (($time - clkin_ps_edge) <= (1.5 * period_ps)) + period_ps <= $time - clkin_ps_edge; + else if ((period_ps == 0) && (clkin_ps_edge != 0)) + period_ps <= $time - clkin_ps_edge; +end + +always @(posedge clkin_ps) begin + lock_fb <= lock_period; +end + +always @(period or fb_delay) + clkout_delay <= period - fb_delay; + +// +// generate master reset signal +// + +always @(posedge clkin_in) begin + rst_reg[0] <= rst_in; + rst_reg[1] <= rst_reg[0] & rst_in; + rst_reg[2] <= rst_reg[1] & rst_reg[0] & rst_in; +end + +time rst_tmp1, rst_tmp2; +initial +begin +rst_tmp1 = 0; +rst_tmp2 = 0; +end + + +always @(posedge rst_in or negedge rst_in) +begin + if (rst_in ==1) + rst_tmp1 <= $time; + else if (rst_in==0 ) begin + rst_tmp2 = $time - rst_tmp1; + if (rst_tmp2 < 2000 && rst_tmp2 != 0) + $display("Input Error : RST on instance %m must be asserted at least for 2 ns."); + end +end + +initial begin + clkdv_out <= 0; + clkin_5050 <= 0; + clkfb_window <= 0; + clkin_period[0] <= 0; + clkin_period[1] <= 0; + clkin_period[2] <= 0; + clkin_ps_edge <= 0; + clkin_window <= 0; + clkout_delay <= 0; + clock_stopped <= 1; + fb_delay <= 0; + fb_delay_found <= 0; + lock_clkfb <= 0; + lock_clkin <= 0; + lock_delay <= 0; + lock_fb <= 0; + lock_out <= 2'b00; + lock_period <= 0; + locked_out <= 0; + period <= 0; + period_ps <= 0; + period_orig <= 0; + rst_reg <= 3'b000; +end + +always @(rst_in) begin + clkin_5050 <= 0; + clkfb_window <= 0; + clkin_period[0] <= 0; + clkin_period[1] <= 0; + clkin_period[2] <= 0; + clkin_ps_edge <= 0; + clkin_window <= 0; + clkout_delay <= 0; + clock_stopped <= 1; + fb_delay <= 0; + fb_delay_found <= 0; + lock_clkfb <= 0; + lock_clkin <= 0; + lock_delay <= 0; + lock_fb <= 0; + lock_out <= 2'b00; + lock_period <= 0; + locked_out <= 0; + period_ps <= 0; +end + +// +// determine clock period +// + +always @(posedge clkin_ps) begin + clkin_edge <= $time; + clkin_period[2] <= clkin_period[1]; + clkin_period[1] <= clkin_period[0]; + if (clkin_edge != 0) + clkin_period[0] <= $time - clkin_edge; +end + +always @(negedge clkin_ps) begin + if (lock_period == 1'b0) begin + if ((clkin_period[0] != 0) && + (clkin_period[0] - cycle_jitter <= clkin_period[1]) && + (clkin_period[1] <= clkin_period[0] + cycle_jitter) && + (clkin_period[1] - cycle_jitter <= clkin_period[2]) && + (clkin_period[2] <= clkin_period[1] + cycle_jitter)) begin + lock_period <= 1; + period_orig <= (clkin_period[0] + + clkin_period[1] + + clkin_period[2]) / 3; + period <= clkin_period[0]; + end + end + else if (lock_period == 1'b1) begin + if (100000000 < (clkin_period[0] / 1000)) begin + $display("Warning : CLKIN stopped toggling on instance %m exceeds %d ms. Current CLKIN Period = %1.3f ns.", 100, clkin_period[0] / 1000.0); + lock_period <= 0; + @(negedge rst_reg[2]); + end + else if ((period_orig * 2 < clkin_period[0]) && clock_stopped == 1'b0) begin + clkin_period[0] = clkin_period[1]; + clock_stopped = 1'b1; + end + else if ((clkin_period[0] < period_orig - period_jitter) || + (period_orig + period_jitter < clkin_period[0])) begin + $display("Warning : Input Clock Period Jitter on instance %m exceeds %1.3f ns. Locked CLKIN Period = %1.3f. Current CLKIN Period = %1.3f.", period_jitter / 1000.0, period_orig / 1000.0, clkin_period[0] / 1000.0); + lock_period <= 0; + @(negedge rst_reg[2]); + end + else if ((clkin_period[0] < clkin_period[1] - cycle_jitter) || + (clkin_period[1] + cycle_jitter < clkin_period[0])) begin + $display("Warning : Input Clock Cycle-Cycle Jitter on instance %m exceeds %1.3f ns. Previous CLKIN Period = %1.3f. Current CLKIN Period = %1.3f.", cycle_jitter / 1000.0, clkin_period[1] / 1000.0, clkin_period[0] / 1000.0); + lock_period <= 0; + @(negedge rst_reg[2]); + end + else begin + period <= clkin_period[0]; + clock_stopped = 1'b0; + end + end +end + +// +// determine clock delay +// + +always @(posedge lock_period) begin + if (lock_period && clkfb_type != 0) begin + if (clkfb_type == 1) begin + @(posedge CLK0 or rst_in) + delay_edge = $time; + end + else if (clkfb_type == 2) begin + @(posedge CLK2X or rst_in) + delay_edge = $time; + end + @(posedge clkfb_in or rst_in) + fb_delay = ($time - delay_edge) % period_orig; + end + fb_delay_found = 1; +end + +// +// determine feedback lock +// + +always @(posedge clkfb_in) begin + #0 clkfb_window <= 1; + #cycle_jitter clkfb_window <= 0; +end + +always @(posedge clkin_fb) begin + #0 clkin_window <= 1; + #cycle_jitter clkin_window <= 0; +end + +always @(posedge clkin_fb) begin + #1 + if (clkfb_window && fb_delay_found) + lock_clkin <= 1; + else + lock_clkin <= 0; +end + +always @(posedge clkfb_in) begin + #1 + if (clkin_window && fb_delay_found) + lock_clkfb <= 1; + else + lock_clkfb <= 0; +end + +always @(negedge clkin_fb) begin + lock_delay <= lock_clkin || lock_clkfb; +end + +// +// generate lock signal +// + +always @(posedge clkin_ps) begin + lock_out[0] <= lock_period & lock_delay & lock_fb; + lock_out[1] <= lock_out[0]; + locked_out <= lock_out[1]; +end + +// +// generate the clk1x_out +// + +always @(posedge clkin_ps) begin + clkin_5050 <= 1; + #(period / 2) + clkin_5050 <= 0; +end + +assign clk0_out = (clk1x_type) ? clkin_5050 : clkin_ps; + +// +// generate the clkdv_out +// + +always @(period) begin + period_dv_high = (period / 2) * (divide_type / 2); + period_dv_low = (period / 2) * (divide_type / 2 + divide_type % 2); +end + +always @(posedge clkin_ps) begin + if (lock_out[0]) begin + clkdv_out = 1'b1; + #(period_dv_high); + clkdv_out = 1'b0; + #(period_dv_low); + clkdv_out = 1'b1; + #(period_dv_high); + clkdv_out = 1'b0; + #(period_dv_low - period / 2); + end +end + +// +// generate all output signal +// + +always @(clk0_out) begin + CLK0 <= #(clkout_delay) clk0_out; +end + +always @(clk0_out) begin + CLK180 <= #(clkout_delay + period / 2) clk0_out; +end + +always @(clkdv_out) begin + CLKDV <= #(clkout_delay) clkdv_out; +end + + +endmodule + +////////////////////////////////////////////////////// + +module clkdllhf_maximum_period_check (clock, rst); +parameter clock_name = ""; +parameter maximum_period = 0; +input clock; +input rst; + +time clock_edge; +time clock_period; + +initial begin + clock_edge <= 0; + clock_period <= 0; +end + +always @(posedge clock) begin + clock_edge <= $time; + clock_period <= $time - clock_edge; + if (clock_period > maximum_period && rst == 0) begin + $display("Warning : Input clock period of, %1.3f ns, on the %s port of instance %m exceeds allotted value of %1.3f ns at simulation time %1.3f ns.", clock_period/1000.0, clock_name, maximum_period/1000.0, $time/1000.0); + end +end +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/CONFIG.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/CONFIG.v new file mode 100644 index 0000000..9b01afc --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/CONFIG.v @@ -0,0 +1,26 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/CONFIG.v,v 1.5 2007/05/23 21:43:33 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / +// /___/ /\ Filename : CONFIG.v +// \ \ / \ Timestamp : Thu Mar 25 16:42:15 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. + +`timescale 1 ps / 1 ps + + +module CONFIG (); + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/CRC32.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/CRC32.v new file mode 100644 index 0000000..890b122 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/CRC32.v @@ -0,0 +1,225 @@ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2006 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Cyclic Redundancy Check 32-bit Input Simulation Model +// /___/ /\ Filename : CRC32.v +// \ \ / \ Timestamp : Fri Jun 18 10:57:01 PDT 2004 +// \___\/\___\ +// +// Revision: +// 10/04/05 - Initial version. +// 12/04/05 - Added functionality +// 01/09/06 - Added Timing +// 08/18/06 - CR#421781 - CRCOUT initialized to 0 when GSR is high +// 09/14/06 - CR#423918 - CRCRESET is high, CRCOUT is INIT +// 07/24/07 - CR#442758 - Use CRCCLK instead of crcclk_int in always block +// 08/16/07 - CR#446564 - Add data_width as part of always block sensitivity list +// 10/22/07 - CR#452418 - Add all to sensitivity list +// End Revision +//////////////////////////////////////////////////////////////////////////////// + +`timescale 1 ps / 1 ps + +`define POLYNOMIAL 32'h04C11DB7 // 00000100 11000001 00011101 10110111 + +module CRC32 (CRCOUT, + CRCCLK, + CRCDATAVALID, + CRCDATAWIDTH, + CRCIN, + CRCRESET + ); + + parameter CRC_INIT = 32'hFFFFFFFF; + + output [31:0] CRCOUT; + reg [31:0] crcout_out = 32'h00000000; + + input CRCCLK; + input CRCDATAVALID; + input [2:0] CRCDATAWIDTH; + input [31:0] CRCIN; + input CRCRESET; + + tri0 GSR = glbl.GSR; + + wire gsr_in; + + reg [7:0] data_in_32, data_in_24, data_in_16, data_in_8; + reg [2:0] data_width; + reg data_valid; + + reg [31:0] crcd, crcreg; + reg [40:0] msg; + reg [63:0] i; + + reg [31:0] crcgen_out_32, crcgen_out_24, crcgen_out_16, crcgen_out_8; + wire [31:0] crcgen_in_32, crcgen_in_24, crcgen_in_16, crcgen_in_8; + + //wire crcclk_int; + wire crcreset_int; + + buf b_gsr (gsr_in, GSR); + buf b_crcout[31:0] (CRCOUT, crcout_out); + + always @(gsr_in, crcreg) + begin + if (gsr_in == 1'b1) + begin + assign crcout_out = 32'h00000000; + end + else + begin + assign crcout_out = {!crcreg[24],!crcreg[25],!crcreg[26], + !crcreg[27],!crcreg[28],!crcreg[29],!crcreg[30], + !crcreg[31],!crcreg[16],!crcreg[17],!crcreg[18], + !crcreg[19],!crcreg[20],!crcreg[21],!crcreg[22], + !crcreg[23], + !crcreg[8],!crcreg[9],!crcreg[10],!crcreg[11], + !crcreg[12],!crcreg[13],!crcreg[14],!crcreg[15], + !crcreg[0],!crcreg[1],!crcreg[2],!crcreg[3], + !crcreg[4],!crcreg[5],!crcreg[6],!crcreg[7]}; + end // if (gsr_in == 1'b0) + end + + + + + + // Optional inverters for clocks and reset + + assign crcreset_int = CRCRESET; + + //assign crcclk_int = (CRCCLK); + + + // Register input data + + always @ (posedge CRCCLK) + begin + data_in_8 <= CRCIN[31:24]; + data_in_16 <= CRCIN[23:16]; + data_in_24 <= CRCIN[15:8]; + data_in_32 <= CRCIN[7:0]; + data_valid <= CRCDATAVALID; + data_width <= CRCDATAWIDTH; + end + + + // Select between CRC8, CRC16, CRC24, CRC32 based on CRCDATAWIDTH + + always @ (crcgen_out_8 or crcgen_out_16 or crcgen_out_24 or crcgen_out_32 or crcd or data_width) + begin + casex (data_width) + 3'b000: crcd <= crcgen_out_8; + 3'b001: crcd <= crcgen_out_16; + 3'b010: crcd <= crcgen_out_24; + 3'b011: crcd <= crcgen_out_32; + default: crcd <= crcgen_out_8; + endcase + end + + // 32-bit CRC internal register + + always @ (posedge CRCCLK) + begin + + if (crcreset_int) + begin + crcreg <= CRC_INIT; + end + else if (!data_valid) + begin + crcreg <= crcreg; + end + else + begin + crcreg <= crcd; + end + end + + + // CRC Generator Logic + + always @(crcreg or CRCIN or data_width or data_in_8 or data_in_16 or data_in_24 or data_in_32) + + begin + + // CRC-8 + + if (data_width == 3'b000) begin + msg = crcreg ^ {data_in_8[0], data_in_8[1], data_in_8[2], data_in_8[3], data_in_8[4], data_in_8[5], data_in_8[6], data_in_8[7],24'h0}; + msg = msg << 8; + + for (i = 0; i < 8; i = i + 1) begin + msg = msg << 1; + if (msg[40] == 1'b1) begin + msg[39:8] = msg[39:8] ^ `POLYNOMIAL; + end + end + crcgen_out_8 = msg[39:8]; + end + + // CRC-16 + + else if (data_width == 3'b001) begin + msg = crcreg ^ {data_in_8[0], data_in_8[1], data_in_8[2], data_in_8[3], data_in_8[4], data_in_8[5], data_in_8[6], data_in_8[7],data_in_16[0], data_in_16[1], data_in_16[2], data_in_16[3], data_in_16[4], data_in_16[5], data_in_16[6], data_in_16[7], 16'h0}; + msg = msg << 8; + + for (i = 0; i < 16; i = i + 1) begin + msg = msg << 1; + if (msg[40] == 1'b1) begin + msg[39:8] = msg[39:8] ^ `POLYNOMIAL; + end + end + crcgen_out_16 = msg[39:8]; + end + + //CRC-24 + + else if (data_width == 3'b010) begin + msg = crcreg ^ {data_in_8[0], data_in_8[1], data_in_8[2], data_in_8[3], data_in_8[4], data_in_8[5], data_in_8[6], data_in_8[7], data_in_16[0], data_in_16[1], data_in_16[2], data_in_16[3], data_in_16[4], data_in_16[5], data_in_16[6], data_in_16[7], data_in_24[0], data_in_24[1], data_in_24[2], data_in_24[3], data_in_24[4], data_in_24[5], data_in_24[6], data_in_24[7],8'h0}; + msg = msg << 8; + + for (i = 0; i < 24; i = i + 1) begin + msg = msg << 1; + if (msg[40] == 1'b1) begin + msg[39:8] = msg[39:8] ^ `POLYNOMIAL; + end + end + crcgen_out_24 = msg[39:8]; + + end + + //CRC-32 + + else if (data_width == 3'b011) begin + msg = crcreg ^ {data_in_8[0], data_in_8[1], data_in_8[2], data_in_8[3], data_in_8[4], data_in_8[5], data_in_8[6], data_in_8[7], data_in_16[0], data_in_16[1], data_in_16[2], data_in_16[3], data_in_16[4], data_in_16[5], data_in_16[6], data_in_16[7], data_in_24[0], data_in_24[1], data_in_24[2], data_in_24[3], data_in_24[4], data_in_24[5], data_in_24[6], data_in_24[7], data_in_32[0], data_in_32[1], data_in_32[2], data_in_32[3], data_in_32[4], data_in_32[5], data_in_32[6], data_in_32[7]}; + msg = msg << 8; + + for (i = 0; i < 32; i = i + 1) begin + msg = msg << 1; + if (msg[40] == 1'b1) begin + msg[39:8] = msg[39:8] ^ `POLYNOMIAL; + end + end + crcgen_out_32 = msg[39:8]; + + end + + end // always @ (crcreg) + + + specify + (CRCCLK => CRCOUT) = (100, 100); + specparam PATHPULSE$ = 0; + endspecify + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/CRC64.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/CRC64.v new file mode 100644 index 0000000..991e87e --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/CRC64.v @@ -0,0 +1,300 @@ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2006 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Cyclic Redundancy Check 64-bit Input Simulation Model +// /___/ /\ Filename : CRC64.v +// \ \ / \ Timestamp : Fri Jun 18 10:57:01 PDT 2004 +// \___\/\___\ +// +// Revision: +// 10/04/05 - Initial version. +// 12/06/05 - Added functionality +// 01/09/06 - Added Timing +// 08/18/06 - CR#421781 - CRCOUT initialized to 0 when GSR is high +// 09/14/06 - CR#423918 - CRCRESET is high, CRCOUT is INIT +// 09/27/06 - CR#425422 - added CRCIN in CRC_GEN process to match vhdl +// 07/24/07 - CR#442758 - Use CRCCLK instead of crcclk_int in always block +// 08/16/07 - CR#446564 - Add data_width as part of always block sensitivity list +// 10/22/07 - CR#452418 - Add all to sensitivity list +// End Revision +/////////////////////////////////////////////////////// + +`timescale 1 ps / 1 ps + +`define POLYNOMIAL 32'h04C11DB7 // 00000100 11000001 00011101 10110111 + +module CRC64 ( + CRCOUT, + CRCCLK, + CRCDATAVALID, + CRCDATAWIDTH, + CRCIN, + CRCRESET + ); + + parameter CRC_INIT = 32'hFFFFFFFF; + + output [31:0] CRCOUT; + reg [31:0] crcout_out = 32'h00000000; + + input CRCCLK; + input CRCDATAVALID; + input [2:0] CRCDATAWIDTH; + input [63:0] CRCIN; + input CRCRESET; + + tri0 GSR = glbl.GSR; + wire gsr_in; + + reg [7:0] data_in_32, data_in_24, data_in_16, data_in_8; + reg [7:0] data_in_64, data_in_56, data_in_48, data_in_40; + + reg [2:0] data_width; + reg data_valid; + + reg [31:0] crcd, crcreg; + reg [72:0] msg; + reg [63:0] i; + + reg [31:0] crcgen_out_32, crcgen_out_24, crcgen_out_16, crcgen_out_8; + reg [31:0] crcgen_out_64, crcgen_out_56, crcgen_out_48, crcgen_out_40; + +// wire crcclk_int; + wire crcreset_int; + + buf b_gsr (gsr_in, GSR); + buf b_crcout[31:0] (CRCOUT, crcout_out); + + + always @(gsr_in, crcreg) + begin + if (gsr_in) + begin + assign crcout_out = 32'h00000000; + end + else + begin + assign crcout_out = {!crcreg[24],!crcreg[25],!crcreg[26], + !crcreg[27],!crcreg[28],!crcreg[29],!crcreg[30], + !crcreg[31],!crcreg[16],!crcreg[17],!crcreg[18], + !crcreg[19],!crcreg[20],!crcreg[21],!crcreg[22], + !crcreg[23], + !crcreg[8],!crcreg[9],!crcreg[10],!crcreg[11], + !crcreg[12],!crcreg[13],!crcreg[14],!crcreg[15], + !crcreg[0],!crcreg[1],!crcreg[2],!crcreg[3], + !crcreg[4],!crcreg[5],!crcreg[6],!crcreg[7]}; + end + end + + + + // Optional inverters for clocks and reset + assign crcreset_int = CRCRESET; + +// assign crcclk_int = (CRCCLK); + + // Register input data + + always @ (posedge CRCCLK) + begin + data_in_8 <= CRCIN[63:56]; + data_in_16 <= CRCIN[55:48]; + data_in_24 <= CRCIN[47:40]; + data_in_32 <= CRCIN[39:32]; + data_in_40 <= CRCIN[31:24]; + data_in_48 <= CRCIN[23:16]; + data_in_56 <= CRCIN[15:8]; + data_in_64 <= CRCIN[7:0]; + data_valid <= CRCDATAVALID; + data_width <= CRCDATAWIDTH; + end + + + + + // Select between 8-bit, 16-bit, 24-bit, 32-bit, 40-bit, 48-bit, 56-bit and 64-bit based on CRCDATAWIDTH + + always @ (crcgen_out_8 or crcgen_out_16 or crcgen_out_24 or crcgen_out_32 or + crcgen_out_40 or crcgen_out_48 or crcgen_out_56 or crcgen_out_64 or + crcd or data_width) + begin + casex (data_width) + 3'b000: crcd <= crcgen_out_8; + 3'b001: crcd <= crcgen_out_16; + 3'b010: crcd <= crcgen_out_24; + 3'b011: crcd <= crcgen_out_32; + 3'b100: crcd <= crcgen_out_40; + 3'b101: crcd <= crcgen_out_48; + 3'b110: crcd <= crcgen_out_56; + 3'b111: crcd <= crcgen_out_64; + default: crcd <= crcgen_out_8; + endcase + end + + // 32-bit CRC internal register + + always @ (posedge CRCCLK) + begin + + if (crcreset_int) + begin + crcreg <= CRC_INIT; + end + else if (!data_valid) + begin + crcreg <= crcreg; + end + else + begin + crcreg <= crcd; + end + end + + + //CRC Generator Logic + + always @(crcreg or CRCIN or data_width or data_in_8 or data_in_16 or data_in_24 or data_in_32 or data_in_40 or data_in_48 or data_in_56 or data_in_64) + + begin + + //CRC-8 + + if (data_width == 3'b000) begin + msg = {crcreg, 32'h0} ^ {data_in_8[0], data_in_8[1], data_in_8[2], data_in_8[3], data_in_8[4], data_in_8[5], data_in_8[6], data_in_8[7],56'h0}; + msg = msg << 8; + + for (i = 0; i < 8; i = i + 1) begin + msg = msg << 1; + if (msg[72] == 1'b1) begin + msg[71:40] = msg[71:40] ^ `POLYNOMIAL; + end + end + crcgen_out_8 = msg[71:40]; + end // if (data_width == 3'b000) + + //CRC-16 + + else if (data_width ==3'b001) begin + msg = {crcreg, 32'h0} ^ {data_in_8[0], data_in_8[1], data_in_8[2], data_in_8[3], data_in_8[4], data_in_8[5], data_in_8[6], data_in_8[7],data_in_16[0], data_in_16[1], data_in_16[2], data_in_16[3], data_in_16[4], data_in_16[5], data_in_16[6], data_in_16[7], 48'h0}; + msg = msg << 8; + + for (i = 0; i < 16; i = i + 1) begin + msg = msg << 1; + if (msg[72] == 1'b1) begin + msg[71:40] = msg[71:40] ^ `POLYNOMIAL; + end + end + crcgen_out_16 = msg[71:40]; + end + + //CRC-24 + + else if (data_width == 3'b010) begin + msg = {crcreg, 32'h0} ^ {data_in_8[0], data_in_8[1], data_in_8[2], data_in_8[3], data_in_8[4], data_in_8[5], data_in_8[6], data_in_8[7], data_in_16[0], data_in_16[1], data_in_16[2], data_in_16[3], data_in_16[4], data_in_16[5], data_in_16[6], data_in_16[7], data_in_24[0], data_in_24[1], data_in_24[2], data_in_24[3], data_in_24[4], data_in_24[5], data_in_24[6], data_in_24[7],40'h0}; + msg = msg << 8; + + for (i = 0; i < 24; i = i + 1) begin + msg = msg << 1; + if (msg[72] == 1'b1) begin + msg[71:40] = msg[71:40] ^ `POLYNOMIAL; + end + end + crcgen_out_24 = msg[71:40]; + + end // if (data_width == 3'b010) + + //CRC-32 + + else if (data_width == 3'b011) begin + msg = {crcreg, 32'h0} ^ {data_in_8[0], data_in_8[1], data_in_8[2], data_in_8[3], data_in_8[4], data_in_8[5], data_in_8[6], data_in_8[7], data_in_16[0], data_in_16[1], data_in_16[2], data_in_16[3], data_in_16[4], data_in_16[5], data_in_16[6], data_in_16[7], data_in_24[0], data_in_24[1], data_in_24[2], data_in_24[3], data_in_24[4], data_in_24[5], data_in_24[6], data_in_24[7], data_in_32[0], data_in_32[1], data_in_32[2], data_in_32[3], data_in_32[4], data_in_32[5], data_in_32[6], data_in_32[7], 32'h0}; + msg = msg << 8; + + for (i = 0; i < 32; i = i + 1) begin + msg = msg << 1; + if (msg[72] == 1'b1) begin + msg[71:40] = msg[71:40] ^ `POLYNOMIAL; + end + end + crcgen_out_32 = msg[71:40]; + + end // if (data_width == 3'b011) + + //CRC-40 + + else if (data_width == 3'b100) begin + msg = {crcreg, 32'h0} ^ {data_in_8[0], data_in_8[1], data_in_8[2], data_in_8[3], data_in_8[4], data_in_8[5], data_in_8[6], data_in_8[7], data_in_16[0], data_in_16[1], data_in_16[2], data_in_16[3], data_in_16[4], data_in_16[5], data_in_16[6], data_in_16[7], data_in_24[0], data_in_24[1], data_in_24[2], data_in_24[3], data_in_24[4], data_in_24[5], data_in_24[6], data_in_24[7], data_in_32[0], data_in_32[1], data_in_32[2], data_in_32[3], data_in_32[4], data_in_32[5], data_in_32[6], data_in_32[7], data_in_40[0], data_in_40[1], data_in_40[2], data_in_40[3], data_in_40[4], data_in_40[5], data_in_40[6], data_in_40[7], 24'h0}; + msg = msg << 8; + + for (i = 0; i < 40; i = i + 1) begin + msg = msg << 1; + if (msg[72] == 1'b1) begin + msg[71:40] = msg[71:40] ^ `POLYNOMIAL; + end + end + crcgen_out_40 = msg[71:40]; + + end // if (data_width == 3'b100) + + //CRC-48 + + else if (data_width == 3'b101) begin + msg = {crcreg, 32'h0} ^ {data_in_8[0], data_in_8[1], data_in_8[2], data_in_8[3], data_in_8[4], data_in_8[5], data_in_8[6], data_in_8[7], data_in_16[0], data_in_16[1], data_in_16[2], data_in_16[3], data_in_16[4], data_in_16[5], data_in_16[6], data_in_16[7], data_in_24[0], data_in_24[1], data_in_24[2], data_in_24[3], data_in_24[4], data_in_24[5], data_in_24[6], data_in_24[7], data_in_32[0], data_in_32[1], data_in_32[2], data_in_32[3], data_in_32[4], data_in_32[5], data_in_32[6], data_in_32[7], data_in_40[0], data_in_40[1], data_in_40[2], data_in_40[3], data_in_40[4], data_in_40[5], data_in_40[6], data_in_40[7], data_in_48[0], data_in_48[1], data_in_48[2], data_in_48[3], data_in_48[4], data_in_48[5], data_in_48[6], data_in_48[7], 16'h0}; + msg = msg << 8; + + for (i = 0; i < 48; i = i + 1) begin + msg = msg << 1; + if (msg[72] == 1'b1) begin + msg[71:40] = msg[71:40] ^ `POLYNOMIAL; + end + end + crcgen_out_48 = msg[71:40]; + + end // if (data_width == 3'b101) + + //CRC-56 + + else if (data_width == 3'b110) begin + msg = {crcreg, 32'h0} ^ {data_in_8[0], data_in_8[1], data_in_8[2], data_in_8[3], data_in_8[4], data_in_8[5], data_in_8[6], data_in_8[7], data_in_16[0], data_in_16[1], data_in_16[2], data_in_16[3], data_in_16[4], data_in_16[5], data_in_16[6], data_in_16[7], data_in_24[0], data_in_24[1], data_in_24[2], data_in_24[3], data_in_24[4], data_in_24[5], data_in_24[6], data_in_24[7], data_in_32[0], data_in_32[1], data_in_32[2], data_in_32[3], data_in_32[4], data_in_32[5], data_in_32[6], data_in_32[7], data_in_40[0], data_in_40[1], data_in_40[2], data_in_40[3], data_in_40[4], data_in_40[5], data_in_40[6], data_in_40[7], data_in_48[0], data_in_48[1], data_in_48[2], data_in_48[3], data_in_48[4], data_in_48[5], data_in_48[6], data_in_48[7], data_in_56[0], data_in_56[1], data_in_56[2], data_in_56[3], data_in_56[4], data_in_56[5], data_in_56[6], data_in_56[7], 8'h0}; + msg = msg << 8; + + for (i = 0; i < 56; i = i + 1) begin + msg = msg << 1; + if (msg[72] == 1'b1) begin + msg[71:40] = msg[71:40] ^ `POLYNOMIAL; + end + end + crcgen_out_56 = msg[71:40]; + + end // if (data_width == 3'b110) + + //CRC-64 + + else if (data_width == 3'b111) begin + msg = {crcreg, 32'h0} ^ {data_in_8[0], data_in_8[1], data_in_8[2], data_in_8[3], data_in_8[4], data_in_8[5], data_in_8[6], data_in_8[7], data_in_16[0], data_in_16[1], data_in_16[2], data_in_16[3], data_in_16[4], data_in_16[5], data_in_16[6], data_in_16[7], data_in_24[0], data_in_24[1], data_in_24[2], data_in_24[3], data_in_24[4], data_in_24[5], data_in_24[6], data_in_24[7], data_in_32[0], data_in_32[1], data_in_32[2], data_in_32[3], data_in_32[4], data_in_32[5], data_in_32[6], data_in_32[7], data_in_40[0], data_in_40[1], data_in_40[2], data_in_40[3], data_in_40[4], data_in_40[5], data_in_40[6], data_in_40[7], data_in_48[0], data_in_48[1], data_in_48[2], data_in_48[3], data_in_48[4], data_in_48[5], data_in_48[6], data_in_48[7], data_in_56[0], data_in_56[1], data_in_56[2], data_in_56[3], data_in_56[4], data_in_56[5], data_in_56[6], data_in_56[7], data_in_64[0], data_in_64[1], data_in_64[2], data_in_64[3], data_in_64[4], data_in_64[5], data_in_64[6], data_in_64[7]}; + msg = msg << 8; + + for (i = 0; i < 64; i = i + 1) begin + msg = msg << 1; + if (msg[72] == 1'b1) begin + msg[71:40] = msg[71:40] ^ `POLYNOMIAL; + end + end + crcgen_out_64 = msg[71:40]; + + end // if (data_width == 3'b111) + end // always @ (crcreg) + + specify + (CRCCLK => CRCOUT) = (100, 100); + specparam PATHPULSE$ = 0; + endspecify + +endmodule + + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/DCIRESET.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/DCIRESET.v new file mode 100644 index 0000000..f66b064 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/DCIRESET.v @@ -0,0 +1,50 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/virtex4/DCIRESET.v,v 1.7 2009/08/21 23:55:43 harikr Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Reset for DCI State Machine +// /___/ /\ Filename : DCIRESET.v +// \ \ / \ Timestamp : Thu Mar 25 16:43:43 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 08/17/09 - CR 531087 -- re-installation of the model +// End Revision + +`timescale 1 ps / 1 ps + +module DCIRESET (LOCKED, RST); + + output LOCKED; + input RST; + + time sample_rising, sample_falling; + + always @(RST) + begin + + if (RST) + sample_rising = $time; + else if (!RST) + sample_falling = $time; + + + if (sample_falling - sample_rising < 100000) + $display ("Timing Violation Error : The high pulse of RST signal at time %.3f ns in DCIRESET has to be greater than 100 ns", $time/1000.0); + + if (sample_rising - sample_falling < 100000) + $display ("Timing Violation Error : The low pulse of RST signal at time %.3f ns in DCIRESET has to be greater than 100 ns", $time/1000.0); + + + end // always @ (RST) + + assign #(100000, 0) LOCKED = RST ? 1'b0 : 1'b1; + +endmodule diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/DCM.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/DCM.v new file mode 100644 index 0000000..5497f9b --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/DCM.v @@ -0,0 +1,1511 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/DCM.v,v 1.36 2008/07/11 20:26:52 yanx Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Function Simulation Library Component +// / / Digital Clock Manager +// /___/ /\ Filename : DCM.v +// \ \ / \ Timestamp : Thu Mar 25 16:43:54 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 03/11/05 - Add LOC parameter. +// 04/11/05 - Initial all output signals.. +// 05/06/05 - Use assign/deassign to reset all output clocks. CR 207692. +// 05/11/05 - Add clkin alignment check control to remove the glitch when +// clkin stopped. (CR207409). +// 05/25/05 - Seperate clock_second_pos and neg to another process due to +// wait caused unreset. Set fb_delay_found after fb_delay computed. +// Enable clkfb_div after lock_fb high (CR 208771) +// 07/05/05 - Use counter to generate clkdv_out to align with clk0_out. (CR211465). +// Add lock_fb_dly to alignment check. (CR210755). +// 07/25/05 - Set CLKIN_PERIOD default to 10.0ns to (CR 213190) +// 12/22/05 - LOCKED = x when RST less than 3 clock cycles (CR 222795) +// 01/12/06 - Add rst_in to period_div and period_ps block to handle clkin frequency +// change case. (CR 221989). +// 02/28/06 - Add integer and real to parameter declaration. +// 09/22/06 - Add lock_period and lock_fb to clkfb_div block (CR418722). +// 12/19/06 - Add clkfb_div_en for clkfb2x divider (CR431210). +// 04/06/07 - Enable the clock out in clock low time after reset in model +// clock_divide_by_2 (CR 437471). +// 06/04/07 - Add parameter SIM_MODE (SLIB_M2.1) +// 02/21/08 - Align clk2x to both clk0 pos and neg edges (CR467858). +// 03/01/08 - Disable alignment of clkfb and clkin_fb check when ps_lock high (CR468893). +// 07/08/08 - Use clkin_div instead of period to generate lock_period_dly (CR476425) +// End Revision + + +`timescale 1 ps / 1 ps + +module DCM ( + CLK0, CLK180, CLK270, CLK2X, CLK2X180, CLK90, + CLKDV, CLKFX, CLKFX180, LOCKED, PSDONE, STATUS, + CLKFB, CLKIN, DSSEN, PSCLK, PSEN, PSINCDEC, RST); + +parameter real CLKDV_DIVIDE = 2.0; +parameter integer CLKFX_DIVIDE = 1; +parameter integer CLKFX_MULTIPLY = 4; +parameter CLKIN_DIVIDE_BY_2 = "FALSE"; +parameter real CLKIN_PERIOD = 10.0; // non-simulatable +parameter CLKOUT_PHASE_SHIFT = "NONE"; +parameter CLK_FEEDBACK = "1X"; +parameter DESKEW_ADJUST = "SYSTEM_SYNCHRONOUS"; // non-simulatable +parameter DFS_FREQUENCY_MODE = "LOW"; +parameter DLL_FREQUENCY_MODE = "LOW"; +parameter DSS_MODE = "NONE"; // non-simulatable +parameter DUTY_CYCLE_CORRECTION = "TRUE"; +parameter FACTORY_JF = 16'hC080; // non-simulatable +localparam integer MAXPERCLKIN = 1000000; // non-modifiable simulation parameter +localparam integer MAXPERPSCLK = 100000000; // non-modifiable simulation parameter +parameter integer PHASE_SHIFT = 0; +localparam integer SIM_CLKIN_CYCLE_JITTER = 300; // non-modifiable simulation parameter +localparam integer SIM_CLKIN_PERIOD_JITTER = 1000; // non-modifiable simulation parameter +parameter SIM_MODE = "SAFE"; +parameter STARTUP_WAIT = "FALSE"; // non-simulatable + + +input CLKFB, CLKIN, DSSEN; +input PSCLK, PSEN, PSINCDEC, RST; + +output CLK0, CLK180, CLK270, CLK2X, CLK2X180, CLK90; +output CLKDV, CLKFX, CLKFX180, LOCKED, PSDONE; +output [7:0] STATUS; + +reg CLK0=0, CLK180=0, CLK270=0, CLK2X=0, CLK2X180=0, CLK90=0; +reg CLKDV=0, CLKFX=0, CLKFX180=0; + +wire clkfx_lost_out, clkin_lost_out; +wire locked_out_out; +wire clkfb_in, clkin_in, dssen_in; +wire psclk_in, psen_in, psincdec_in, rst_in; +reg clk0_out; +reg clk2x_out, clkdv_out; +reg clkfx_out, clkfx180_en; +reg rst_flag; +reg locked_out, psdone_out, ps_overflow_out, ps_lock; +reg clkfb_div, clkfb_chk, clkfb_div_en; +integer clkdv_cnt; + +reg [1:0] clkfb_type; +reg [8:0] divide_type; +reg clkin_type; +reg [1:0] ps_type; +reg [3:0] deskew_adjust_mode; +reg dfs_mode_type; +reg dll_mode_type; +reg clk1x_type; +integer ps_in, ps_in_ps; + +reg lock_period, lock_delay, lock_clkin, lock_clkfb; +reg first_time_locked; +reg en_status; +reg ps_overflow_out_ext = 0; +reg clkin_lost_out_ext = 0; +reg clkfx_lost_out_ext = 0; +reg [1:0] lock_out; +reg lock_out1_neg; +reg lock_fb, lock_ps, lock_ps_dly, lock_fb_dly, lock_fb_dly_tmp; +reg fb_delay_found; +reg clock_stopped; +reg clkin_chkin, clkfb_chkin; + +wire chk_enable, chk_rst; +wire clkin_div; +wire lock_period_pulse; +reg lock_period_dly; + +reg clkin_ps; +reg clkin_fb; + +time FINE_SHIFT_RANGE; +time ps_delay; +time clkin_edge; +time clkin_div_edge; +time clkin_ps_edge; +time delay_edge; +time clkin_period [2:0]; +time period; +time period_div; +time period_orig; +time period_ps; +time clkout_delay; +time fb_delay; +time period_fx, remain_fx; +time period_dv_high, period_dv_low; +time cycle_jitter, period_jitter; + +reg clkin_window, clkfb_window; +reg [2:0] rst_reg; +reg [12:0] numerator, denominator, gcd; +reg [23:0] i, n, d, p; + +reg notifier; + + reg LOCKED_out ; + + reg align, clkin_divide, fbsync = 0; + reg [2:0] pos_shift, neg_shift; + reg [2:0] pos_shift_st, neg_shift_st; + reg [1:0] clkin_cnt, old_clkin_cnt; + reg clkin_error; + reg period_updated; + reg clkin_cnt_en; + reg rst_tmp, rst_done_fx, rst_done_dv; + integer shift; + + realtime clk_period; // = (250*CLKIN_PERIOD); + realtime clkfx_period; // = ((CLKIN_PERIOD*CLKFX_DIVIDE*1000)/(CLKFX_MULTIPLY*2)); + realtime shift_ammount; // = ((CLKIN_PERIOD*1000)/256); + realtime clkdv_period; // = ((CLKIN_PERIOD*CLKDV_DIVIDE*1000)/2); + realtime clkin_time1, clkin_time2, period_clkin; + + time start_time, delay_time; + integer t; + +initial begin + #1; + if ($realtime == 0) begin + $display ("Simulator Resolution Error : Simulator resolution is set to a value greater than 1 ps."); + $display ("In order to simulate the DCM, the simulator resolution must be set to 1ps or smaller."); + $finish; + end +end + +initial begin + case (CLKDV_DIVIDE) + 1.5 : divide_type = 'd3; + 2.0 : divide_type = 'd4; + 2.5 : divide_type = 'd5; + 3.0 : divide_type = 'd6; + 3.5 : divide_type = 'd7; + 4.0 : divide_type = 'd8; + 4.5 : divide_type = 'd9; + 5.0 : divide_type = 'd10; + 5.5 : divide_type = 'd11; + 6.0 : divide_type = 'd12; + 6.5 : divide_type = 'd13; + 7.0 : divide_type = 'd14; + 7.5 : divide_type = 'd15; + 8.0 : divide_type = 'd16; + 9.0 : divide_type = 'd18; + 10.0 : divide_type = 'd20; + 11.0 : divide_type = 'd22; + 12.0 : divide_type = 'd24; + 13.0 : divide_type = 'd26; + 14.0 : divide_type = 'd28; + 15.0 : divide_type = 'd30; + 16.0 : divide_type = 'd32; + default : begin + $display("Attribute Syntax Error : The attribute CLKDV_DIVIDE on DCM instance %m is set to %0.1f. Legal values for this attribute are 1.5, 2.0, 2.5, 3.0, 3.5, 4.0, 4.5, 5.0, 5.5, 6.0, 6.5, 7.0, 7.5, 8.0, 9.0, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0, or 16.0.", CLKDV_DIVIDE); + $finish; + end + endcase + + if ((CLKFX_DIVIDE <= 0) || (32 < CLKFX_DIVIDE)) begin + $display("Attribute Syntax Error : The attribute CLKFX_DIVIDE on DCM instance %m is set to %d. Legal values for this attribute are 1 ... 32.", CLKFX_DIVIDE); + $finish; + end + + if ((CLKFX_MULTIPLY <= 1) || (32 < CLKFX_MULTIPLY)) begin + $display("Attribute Syntax Error : The attribute CLKFX_MULTIPLY on DCM instance %m is set to %d. Legal values for this attribute are 2 ... 32.", CLKFX_MULTIPLY); + $finish; + end + + case (CLKIN_DIVIDE_BY_2) + "false" : clkin_type = 0; + "FALSE" : clkin_type = 0; + "true" : clkin_type = 1; + "TRUE" : clkin_type = 1; + default : begin + $display("Attribute Syntax Error : The attribute CLKIN_DIVIDE_BY_2 on DCM instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", CLKIN_DIVIDE_BY_2); + $finish; + end + endcase + + case (CLKOUT_PHASE_SHIFT) + "NONE" : begin + ps_in = 256; + ps_type = 0; + end + "none" : begin + ps_in = 256; + ps_type = 0; + end + "FIXED" : begin + ps_in = PHASE_SHIFT + 256; + ps_type = 1; + end + "fixed" : begin + ps_in = PHASE_SHIFT + 256; + ps_type = 1; + end + "VARIABLE" : begin + ps_in = PHASE_SHIFT + 256; + ps_type = 2; + end + "variable" : begin + ps_in = PHASE_SHIFT + 256; + ps_type = 2; + end + default : begin + $display("Attribute Syntax Error : The attribute CLKOUT_PHASE_SHIFT on DCM instance %m is set to %s. Legal values for this attribute are NONE, FIXED or VARIABLE.", CLKOUT_PHASE_SHIFT); + $finish; + end + endcase + + ps_in_ps = ps_in; + + case (CLK_FEEDBACK) + "none" : clkfb_type = 2'b00; + "NONE" : clkfb_type = 2'b00; + "1x" : clkfb_type = 2'b01; + "1X" : clkfb_type = 2'b01; + "2x" : clkfb_type = 2'b10; + "2X" : clkfb_type = 2'b10; + default : begin + $display("Attribute Syntax Error : The attribute CLK_FEEDBACK on DCM instance %m is set to %s. Legal values for this attribute are NONE, 1X or 2X.", CLK_FEEDBACK); + $finish; + end + endcase + + case (DESKEW_ADJUST) + "source_synchronous" : deskew_adjust_mode = 8; + "SOURCE_SYNCHRONOUS" : deskew_adjust_mode = 8; + "system_synchronous" : deskew_adjust_mode = 11; + "SYSTEM_SYNCHRONOUS" : deskew_adjust_mode = 11; + "0" : deskew_adjust_mode = 0; + "1" : deskew_adjust_mode = 1; + "2" : deskew_adjust_mode = 2; + "3" : deskew_adjust_mode = 3; + "4" : deskew_adjust_mode = 4; + "5" : deskew_adjust_mode = 5; + "6" : deskew_adjust_mode = 6; + "7" : deskew_adjust_mode = 7; + "8" : deskew_adjust_mode = 8; + "9" : deskew_adjust_mode = 9; + "10" : deskew_adjust_mode = 10; + "11" : deskew_adjust_mode = 11; + "12" : deskew_adjust_mode = 12; + "13" : deskew_adjust_mode = 13; + "14" : deskew_adjust_mode = 14; + "15" : deskew_adjust_mode = 15; + default : begin + $display("Attribute Syntax Error : The attribute DESKEW_ADJUST on DCM instance %m is set to %s. Legal values for this attribute are SOURCE_SYNCHRONOUS, SYSTEM_SYNCHRONOUS or 0 ... 15.", DESKEW_ADJUST); + $finish; + end + endcase + + case (DFS_FREQUENCY_MODE) + "high" : dfs_mode_type = 1; + "HIGH" : dfs_mode_type = 1; + "low" : dfs_mode_type = 0; + "LOW" : dfs_mode_type = 0; + default : begin + $display("Attribute Syntax Error : The attribute DFS_FREQUENCY_MODE on DCM instance %m is set to %s. Legal values for this attribute are HIGH or LOW.", DFS_FREQUENCY_MODE); + $finish; + end + endcase + + period_jitter = SIM_CLKIN_PERIOD_JITTER; + cycle_jitter = SIM_CLKIN_CYCLE_JITTER; + + case (DLL_FREQUENCY_MODE) + "high" : dll_mode_type = 1; + "HIGH" : dll_mode_type = 1; + "low" : dll_mode_type = 0; + "LOW" : dll_mode_type = 0; + default : begin + $display("Attribute Syntax Error : The attribute DLL_FREQUENCY_MODE on DCM instance %m is set to %s. Legal values for this attribute are HIGH or LOW.", DLL_FREQUENCY_MODE); + $finish; + end + endcase + + if ((dll_mode_type ==1) && (clkfb_type == 2'b10)) begin + $display("Attribute Syntax Error : The attributes DLL_FREQUENCY_MODE on DCM instance %m is set to %s and CLK_FEEDBACK is set to %s. CLK_FEEDBACK 2X is not supported when DLL_FREQUENCY_MODE is HIGH.", DLL_FREQUENCY_MODE, CLK_FEEDBACK); + $finish; + end + + case (DSS_MODE) + "none" : ; + "NONE" : ; + default : begin + $display("Attribute Syntax Error : The attribute DSS_MODE on DCM instance %m is set to %s. Legal values for this attribute is NONE.", DSS_MODE); + $finish; + end + endcase + + case (DUTY_CYCLE_CORRECTION) + "false" : clk1x_type = 0; + "FALSE" : clk1x_type = 0; + "true" : clk1x_type = 1; + "TRUE" : clk1x_type = 1; + default : begin + $display("Attribute Syntax Error : The attribute DUTY_CYCLE_CORRECTION on DCM instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", DUTY_CYCLE_CORRECTION); + $finish; + end + endcase + + if ((PHASE_SHIFT < -255) || (PHASE_SHIFT > 255)) begin + $display("Attribute Syntax Error : The attribute PHASE_SHIFT on DCM instance %m is set to %d. Legal values for this attribute are -255 ... 255.", PHASE_SHIFT); + $display("Error : PHASE_SHIFT = %d is not -255 ... 255.", PHASE_SHIFT); + $finish; + end + + case (STARTUP_WAIT) + "false" : ; + "FALSE" : ; + "true" : ; + "TRUE" : ; + default : begin + $display("Attribute Syntax Error : The attribute STARTUP_WAIT on DCM instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", STARTUP_WAIT); + $finish; + end + endcase + + case (SIM_MODE) + "FAST" : ; + "SAFE" : ; + default : begin + $display("Attribute Syntax Error : The attribute SIM_MODE on DCM instance %m is set to %s. Legal values for this attribute are FAST or SAFE.", SIM_MODE); + $finish; + end + endcase + +end + +generate if (SIM_MODE !== "FAST") +begin +// +// fx parameters +// + +initial begin + gcd = 1; + for (i = 2; i <= CLKFX_MULTIPLY; i = i + 1) begin + if (((CLKFX_MULTIPLY % i) == 0) && ((CLKFX_DIVIDE % i) == 0)) + gcd = i; + end + numerator = CLKFX_MULTIPLY / gcd; + denominator = CLKFX_DIVIDE / gcd; +end + +// +// input wire delays +// + + assign clkin_in = CLKIN; + assign clkfb_in = CLKFB; + assign dssen_in = DSSEN; + assign psclk_in = PSCLK; + assign psen_in = PSEN; + assign psincdec_in = PSINCDEC; + assign rst_in = RST; + assign #100 LOCKED = locked_out_out; + assign #100 PSDONE = psdone_out; + assign STATUS[0] = ps_overflow_out_ext; + assign STATUS[1] = clkin_lost_out_ext; + assign STATUS[2] = clkfx_lost_out_ext; + +assign STATUS[7:3] = 5'b0; + +dcm_clock_divide_by_2 i_clock_divide_by_2 (clkin_in, clkin_type, clkin_div, rst_in); + +dcm_maximum_period_check #("CLKIN", MAXPERCLKIN) i_max_clkin (clkin_in); +dcm_maximum_period_check #("PSCLK", MAXPERPSCLK) i_max_psclk (psclk_in); + +dcm_clock_lost i_clkin_lost (clkin_in, first_time_locked, clkin_lost_out, rst_in); +dcm_clock_lost i_clkfx_lost (CLKFX, first_time_locked, clkfx_lost_out, rst_in); + +always @(rst_in or en_status or clkfx_lost_out or clkin_lost_out or ps_overflow_out) + if (rst_in == 1 || en_status == 0) begin + ps_overflow_out_ext = 0; + clkin_lost_out_ext = 0; + clkfx_lost_out_ext = 0; + end + else + begin + ps_overflow_out_ext = ps_overflow_out; + clkin_lost_out_ext = clkin_lost_out; + clkfx_lost_out_ext = clkfx_lost_out; + end + +always @(posedge rst_in or posedge LOCKED) + if (rst_in == 1) + en_status <= 0; + else + en_status <= 1; + + +always @(clkin_div) + clkin_ps <= #(ps_delay) clkin_div; + +always @(clkin_ps or lock_fb) + clkin_fb = clkin_ps & lock_fb; + + +always @(negedge clkfb_in or posedge rst_in) + if (rst_in) + clkfb_div_en <= 0; + else + if (lock_fb_dly && lock_period && lock_fb && ~clkin_ps) + clkfb_div_en <= 1; + +always @(posedge clkfb_in or posedge rst_in) + if (rst_in) + clkfb_div <= 0; + else + if (clkfb_div_en ) + clkfb_div <= ~clkfb_div; + +always @(clkfb_in or clkfb_div) + if (clkfb_type == 2'b10 ) + clkfb_chk = clkfb_div; + else + clkfb_chk = clkfb_in & lock_fb_dly; + +always @(posedge clkin_fb or posedge chk_rst) + if (chk_rst) + clkin_chkin <= 0; + else + clkin_chkin <= 1; + +always @(posedge clkfb_chk or posedge chk_rst) + if (chk_rst) + clkfb_chkin <= 0; + else + clkfb_chkin <= 1; + + assign chk_rst = (rst_in==1 || clock_stopped==1 ) ? 1 : 0; + assign chk_enable = (clkin_chkin == 1 && clkfb_chkin == 1 && + lock_ps ==1 && lock_fb ==1 && lock_fb_dly == 1) ? 1 : 0; + +always @(posedge clkin_div or posedge rst_in) + if (rst_in) begin + period_div <= 0; + clkin_div_edge <= 0; + end + else + if ( clkin_div ==1 ) begin + clkin_div_edge <= $time; + if (($time - clkin_div_edge) <= (1.5 * period_div)) + period_div <= $time - clkin_div_edge; + else if ((period_div == 0) && (clkin_div_edge != 0)) + period_div <= $time - clkin_div_edge; + end + +always @(posedge clkin_ps or posedge rst_in) + if (rst_in) begin + period_ps <= 0; + clkin_ps_edge <= 0; + end + else + if (clkin_ps == 1 ) begin + clkin_ps_edge <= $time; + if (($time - clkin_ps_edge) <= (1.5 * period_ps)) + period_ps <= $time - clkin_ps_edge; + else if ((period_ps == 0) && (clkin_ps_edge != 0)) + period_ps <= $time - clkin_ps_edge; + end + +always @(posedge clkin_ps) begin + lock_ps <= lock_period; + lock_ps_dly <= lock_ps; + lock_fb <= lock_ps_dly; + lock_fb_dly_tmp <= lock_fb; +end + +always @(negedge clkin_ps or posedge rst_in) + if (rst_in) + lock_fb_dly <= 1'b0; + else + lock_fb_dly <= #(period * 0.75) lock_fb_dly_tmp; + + +always @(period or fb_delay ) + if (fb_delay == 0) + clkout_delay = 0; + else + clkout_delay = period - fb_delay; + +// +// generate master reset signal +// + +always @(posedge clkin_in) begin + rst_reg[0] <= rst_in; + rst_reg[1] <= rst_reg[0] & rst_in; + rst_reg[2] <= rst_reg[1] & rst_reg[0] & rst_in; +end + +reg rst_tmp1, rst_tmp2; +initial +begin +rst_tmp1 = 0; +rst_tmp2 = 0; +rst_flag = 0; +end + +always @(rst_in) +begin + if (rst_in) + rst_flag = 0; + + rst_tmp1 = rst_in; + if (rst_tmp1 == 0 && rst_tmp2 == 1) begin + if ((rst_reg[2] & rst_reg[1] & rst_reg[0]) == 0) begin + rst_flag = 1; + $display("Input Error : RST on instance %m must be asserted for 3 CLKIN clock cycles."); + end + end + rst_tmp2 = rst_tmp1; +end + +initial begin + CLK0 = 0; + CLK180 = 0; + CLK270 = 0; + CLK2X = 0; + CLK2X180 = 0; + CLK90 = 0; + CLKDV = 0; + CLKFX = 0; + CLKFX180 = 0; + clk0_out = 0; + clk2x_out = 0; + clkdv_out = 0; + clkdv_cnt = 0; + clkfb_window = 0; + clkfx_out = 0; + clkfx180_en = 0; + clkin_div_edge = 0; + clkin_period[0] = 0; + clkin_period[1] = 0; + clkin_period[2] = 0; + clkin_edge = 0; + clkin_ps_edge = 0; + clkin_window = 0; + clkout_delay = 0; + clock_stopped = 1; + fb_delay = 0; + fb_delay_found = 0; + lock_clkfb = 0; + lock_clkin = 0; + lock_delay = 0; + lock_fb = 0; + lock_fb_dly = 0; + lock_out = 2'b00; + lock_out1_neg = 0; + lock_period = 0; + lock_period_dly = 0; + lock_ps = 0; + lock_ps_dly = 0; + locked_out = 0; + period = 0; + period_div = 0; + period_fx = 0; + period_orig = 0; + period_ps = 0; + psdone_out = 0; + ps_delay = 0; + ps_lock = 0; + ps_overflow_out = 0; + ps_overflow_out_ext = 0; + clkin_lost_out_ext = 0; + clkfx_lost_out_ext = 0; + rst_reg = 3'b000; + first_time_locked = 0; + en_status = 0; + clkfb_div = 0; + clkin_chkin = 0; + clkfb_chkin = 0; +end + +// RST less than 3 cycles, lock = x + + assign locked_out_out = (rst_flag) ? 1'bx : locked_out; + +// +// detect_first_time_locked +// +always @(posedge locked_out) + if (first_time_locked == 0) + first_time_locked <= 1; + +// +// phase shift parameters +// + +always @(posedge lock_period) begin + if (ps_type == 2'b01) + FINE_SHIFT_RANGE = 10000; + else if (ps_type == 2'b10) + FINE_SHIFT_RANGE = 5000; + if (PHASE_SHIFT > 0) begin + if ((ps_in * period_orig / 256) > period_orig + FINE_SHIFT_RANGE) begin + $display("Function Error : Instance %m Requested Phase Shift = PHASE_SHIFT * PERIOD / 256 = %d * %1.3f / 256 = %1.3f. This exceeds the FINE_SHIFT_RANGE of %1.3f ns.", PHASE_SHIFT, period_orig / 1000.0, PHASE_SHIFT * period_orig / 256 / 1000.0, FINE_SHIFT_RANGE / 1000.0); + $finish; + end + end + else if (PHASE_SHIFT < 0) begin + if ((period_orig > FINE_SHIFT_RANGE) && + ((ps_in * period_orig / 256) < period_orig - FINE_SHIFT_RANGE)) begin + $display("Function Error : Instance %m Requested Phase Shift = PHASE_SHIFT * PERIOD / 256 = %d * %1.3f / 256 = %1.3f. This exceeds the FINE_SHIFT_RANGE of %1.3f ns.", PHASE_SHIFT, period_orig / 1000.0, -(PHASE_SHIFT) * period_orig / 256 / 1000.0, FINE_SHIFT_RANGE / 1000.0); + $finish; + end + end +end + +always @(posedge lock_period_pulse or posedge rst_in or ps_in_ps) + if (rst_in) begin + ps_delay <= 0; + end + else if (lock_period_pulse) begin + ps_delay <= (ps_in * period_div / 256); + end + else begin + if (ps_type == 2'b10 && ps_lock ==1) + begin + ps_delay = (ps_in_ps * period_div / 256); + end + end + + +always @(posedge psclk_in or rst_in) + if (rst_in) begin + ps_in_ps <= ps_in; + ps_overflow_out <= 0; + end + else begin + if (ps_type == 2'b10) + if (psen_in) + if (ps_lock == 1) + $display(" Warning : Please wait for PSDONE signal before adjusting the Phase Shift."); + else + if (psincdec_in == 1) begin + if (ps_in_ps == 511) + ps_overflow_out <= 1; + else if (((ps_in_ps + 1) * period_orig / 256) > period_orig + FINE_SHIFT_RANGE) + ps_overflow_out <= 1; + else begin + ps_in_ps <= ps_in_ps + 1; + ps_overflow_out <= 0; + end + ps_lock <= 1; + end + else if (psincdec_in == 0) begin + if (ps_in_ps == 1) + ps_overflow_out <= 1; + else if ((period_orig > FINE_SHIFT_RANGE) && + (((ps_in_ps - 1) * period_orig / 256) < period_orig - FINE_SHIFT_RANGE)) + ps_overflow_out <= 1; + else begin + ps_in_ps <= ps_in_ps - 1; + ps_overflow_out <= 0; + end + ps_lock <= 1; + end +end + +always @(posedge ps_lock) begin + @(posedge clkin_ps) + @(posedge psclk_in) + @(posedge psclk_in) + @(posedge psclk_in) + psdone_out <= 1; + @(posedge psclk_in) + psdone_out <= 0; + ps_lock <= 0; +end + +// +// determine clock period +// + +always @(posedge clkin_div or negedge clkin_div or posedge rst_in) + if (rst_in == 1) begin + clkin_period[0] <= 0; + clkin_period[1] <= 0; + clkin_period[2] <= 0; + clkin_edge <= 0; + end + else + if (clkin_div == 1) begin + clkin_edge <= $time; + clkin_period[2] <= clkin_period[1]; + clkin_period[1] <= clkin_period[0]; + if (clkin_edge != 0) + clkin_period[0] <= $time - clkin_edge; + end + else if (clkin_div == 0) + if (lock_period == 1) + if (100000000 < clkin_period[0]/1000) + begin + end + else if ((period_orig * 2 < clkin_period[0]) && (clock_stopped == 0)) begin + clkin_period[0] <= clkin_period[1]; + end + +always @(negedge clkin_div or posedge rst_in) + if (rst_in == 1) begin + lock_period <= 0; + clock_stopped <= 1; + end + else begin + if (lock_period == 1'b0) begin + if ((clkin_period[0] != 0) && + (clkin_period[0] - cycle_jitter <= clkin_period[1]) && + (clkin_period[1] <= clkin_period[0] + cycle_jitter) && + (clkin_period[1] - cycle_jitter <= clkin_period[2]) && + (clkin_period[2] <= clkin_period[1] + cycle_jitter)) begin + lock_period <= 1; + period_orig <= (clkin_period[0] + + clkin_period[1] + + clkin_period[2]) / 3; + period <= clkin_period[0]; + end + end + else if (lock_period == 1'b1) begin + if (100000000 < (clkin_period[0] / 1000)) begin + $display(" Warning : CLKIN stopped toggling on instance %m exceeds %d ms. Current CLKIN Period = %1.3f ns.", 100, clkin_period[0] / 1000.0); + lock_period <= 0; + @(negedge rst_reg[2]); + end + else if ((period_orig * 2 < clkin_period[0]) && clock_stopped == 1'b0) begin + clock_stopped <= 1'b1; + end + else if ((clkin_period[0] < period_orig - period_jitter) || + (period_orig + period_jitter < clkin_period[0])) begin + $display(" Warning : Input Clock Period Jitter on instance %m exceeds %1.3f ns. Locked CLKIN Period = %1.3f. Current CLKIN Period = %1.3f.", period_jitter / 1000.0, period_orig / 1000.0, clkin_period[0] / 1000.0); + lock_period <= 0; + @(negedge rst_reg[2]); + end + else if ((clkin_period[0] < clkin_period[1] - cycle_jitter) || + (clkin_period[1] + cycle_jitter < clkin_period[0])) begin + $display(" Warning : Input Clock Cycle-Cycle Jitter on instance %m exceeds %1.3f ns. Previous CLKIN Period = %1.3f. Current CLKIN Period = %1.3f.", cycle_jitter / 1000.0, clkin_period[1] / 1000.0, clkin_period[0] / 1000.0); + lock_period <= 0; + @(negedge rst_reg[2]); + end + else begin + period <= clkin_period[0]; + clock_stopped <= 1'b0; + end + end +end + + always @(posedge clkin_div or posedge rst_in) + if (rst_in) + lock_period_dly <= 0; + else + lock_period_dly <= lock_period; + +// assign #(period/2) lock_period_dly = lock_period; + assign lock_period_pulse = (lock_period==1 && lock_period_dly==0) ? 1 : 0; + +// +// determine clock delay +// + +//always @(posedge lock_period or posedge rst_in) +always @(posedge lock_ps_dly or posedge rst_in) + if (rst_in) begin + fb_delay <= 0; + fb_delay_found <= 0; + end + else begin + if (lock_period && clkfb_type != 2'b00) begin + if (clkfb_type == 2'b01) begin + @(posedge CLK0 or rst_in) + delay_edge = $time; + end + else if (clkfb_type == 2'b10) begin + @(posedge CLK2X or rst_in) + delay_edge = $time; + end + @(posedge clkfb_in or rst_in) begin + fb_delay <= ($time - delay_edge) % period_orig; + fb_delay_found <= 1; + end + end + end + +// +// determine feedback lock +// + +//always @(posedge clkfb_in or posedge rst_in) +always @(posedge clkfb_chk or posedge rst_in) + if (rst_in) + clkfb_window <= 0; + else begin + clkfb_window <= 1; + #cycle_jitter clkfb_window <= 0; + end + +always @(posedge clkin_fb or posedge rst_in) + if (rst_in) + clkin_window <= 0; + else begin + clkin_window <= 1; + #cycle_jitter clkin_window <= 0; + end + +always @(posedge clkin_fb or posedge rst_in) + if (rst_in) + lock_clkin <= 0; + else begin + #1 + if ((clkfb_window && fb_delay_found) || (clkin_lost_out == 1'b1 && lock_out[0]==1'b1)) + lock_clkin <= 1; + else + if (chk_enable==1 && ps_lock == 0) + lock_clkin <= 0; + end + +always @(posedge clkfb_chk or posedge rst_in) + if (rst_in) + lock_clkfb <= 0; + else begin + #1 + if ((clkin_window && fb_delay_found) || (clkin_lost_out == 1'b1 && lock_out[0]==1'b1)) + lock_clkfb <= 1; + else + if (chk_enable ==1 && ps_lock == 0) + lock_clkfb <= 0; + end + +always @(negedge clkin_fb or posedge rst_in) + if (rst_in) + lock_delay <= 0; + else + lock_delay <= lock_clkin || lock_clkfb; + +// +// generate lock signal +// + +always @(posedge clkin_ps or posedge rst_in) + if (rst_in) begin + lock_out <= 2'b0; + locked_out <=0; + end + else begin + if (clkfb_type == 2'b00) + lock_out[0] <= lock_period; + else + lock_out[0] <= lock_period & lock_delay & lock_fb; + lock_out[1] <= lock_out[0]; + locked_out <= lock_out[1]; + end + +always @(negedge clkin_ps or posedge rst_in) + if (rst_in) + lock_out1_neg <= 0; + else + lock_out1_neg <= lock_out[1]; + + +// +// generate the clk1x_out +// + +always @(posedge clkin_ps or negedge clkin_ps or posedge rst_in) + if (rst_in) + clk0_out <= 0; + else + if (clkin_ps ==1) + if (clk1x_type==1 && lock_out[0]) begin + clk0_out <= 1; + #(period / 2) + clk0_out <= 0; + end + else + clk0_out <= 1; + else + if (clkin_ps == 0 && ((clk1x_type && lock_out[0]) == 0 || (lock_out[0]== 1 && lock_out[1]== 0))) + clk0_out <= 0; + +// +// generate the clk2x_out +// + +always @(posedge clkin_ps or negedge clkin_ps or posedge rst_in) + if (rst_in) + clk2x_out <= 0; + else begin + clk2x_out <= 1; + #(period / 4) + clk2x_out <= 0; + end + +// +// generate the clkdv_out +// + +always @(posedge clkin_ps or negedge clkin_ps or posedge rst_in) + if (rst_in) begin + clkdv_out <= 1'b0; + clkdv_cnt <= 0; + end + else + if (lock_out1_neg) begin + if (clkdv_cnt >= divide_type -1) + clkdv_cnt <= 0; + else + clkdv_cnt <= clkdv_cnt + 1; + + if (clkdv_cnt < divide_type /2) + clkdv_out <= 1'b1; + else + if ( (divide_type[0] == 1'b1) && dll_mode_type == 1'b0) + clkdv_out <= #(period/4) 1'b0; + else + clkdv_out <= 1'b0; + end + + +// +// generate fx output signal +// + +always @(lock_period or period or denominator or numerator) begin + if (lock_period == 1'b1) begin + period_fx = (period * denominator) / (numerator * 2); + remain_fx = (period * denominator) % (numerator * 2); + end +end + +always @(posedge clkin_ps or posedge clkin_lost_out or posedge rst_in ) + if (rst_in == 1) + clkfx_out = 1'b0; + else if (clkin_lost_out == 1'b1 ) begin + if (locked_out == 1) + @(negedge rst_reg[2]); + end + else + if (lock_out[1] == 1) begin + clkfx_out = 1'b1; + for (p = 0; p < (numerator * 2 - 1); p = p + 1) begin + #(period_fx); + if (p < remain_fx) + #1; + clkfx_out = !clkfx_out; + end + if (period_fx > (period / 2)) begin + #(period_fx - (period / 2)); + end + end + +// +// generate all output signal +// + +always @(rst_in) +if (rst_in) begin + assign CLK0 = 0; + assign CLK90 = 0; + assign CLK180 = 0; + assign CLK270 = 0; + assign CLK2X = 0; + assign CLK2X180 =0; + assign CLKDV = 0; + assign CLKFX = 0; + assign CLKFX180 = 0; +end +else begin + deassign CLK0; + deassign CLK90; + deassign CLK180; + deassign CLK270; + deassign CLK2X; + deassign CLK2X180; + deassign CLKDV; + deassign CLKFX; + deassign CLKFX180; +end + +always @(clk0_out) begin + CLK0 <= #(clkout_delay) clk0_out && (clkfb_type != 2'b00); + CLK90 <= #(clkout_delay + period / 4) clk0_out && !dll_mode_type && (clkfb_type != 2'b00); + CLK180 <= #(clkout_delay) ~clk0_out && (clkfb_type != 2'b00); + CLK270 <= #(clkout_delay + period / 4) ~clk0_out && !dll_mode_type && (clkfb_type != 2'b00); + end + +always @(clk2x_out) begin + CLK2X <= #(clkout_delay) clk2x_out && !dll_mode_type && (clkfb_type != 2'b00); + CLK2X180 <= #(clkout_delay) ~clk2x_out && !dll_mode_type && (clkfb_type != 2'b00); +end + +always @(clkdv_out) + CLKDV <= #(clkout_delay) clkdv_out && (clkfb_type != 2'b00); + +always @(clkfx_out ) + CLKFX <= #(clkout_delay) clkfx_out; + +always @( clkfx_out or first_time_locked or locked_out) + if ( ~first_time_locked) + CLKFX180 = 0; + else + CLKFX180 <= #(clkout_delay) ~clkfx_out; + + +end +endgenerate + + + +generate if (SIM_MODE === "FAST") +begin + + + always begin: feedback_dcm + fbsync = 0; + wait (RST==0); + wait (period_updated==1) + @(posedge CLKFB); + delay_time = $time - start_time; + @(posedge CLKIN); + #(((12*clk_period)-(delay_time))); + fbsync = 1; + wait (RST==1); + end + + assign locked_out_out = LOCKED_out; + + always begin: main_dcm + pos_shift[0] = 1'b0; + neg_shift[0] = 1'b0; + align = 0; + LOCKED_out = 1'b0; + period_updated = 0; + clkin_cnt_en = 0; + CLK0 = 1'b0; + CLK90 = 1'b0; + CLK180 = 1'b0; + CLK270 = 1'b0; + CLK2X = 1'b0; + CLK2X180 = 1'b0; + rst_tmp <= 1'b1; + wait (RST==0); + wait (rst_done_fx==1 ); + wait (rst_done_dv==1); + rst_tmp <= 1'b0; + @(posedge CLKIN); + clkin_time1 = $time; + @(posedge CLKIN); + clkin_time2 = $time; + period_clkin = clkin_time2 - clkin_time1; + + clk_period = (0.25*period_clkin); + clkfx_period = ((period_clkin*CLKFX_DIVIDE)/(CLKFX_MULTIPLY*2)); + shift_ammount = ((period_clkin)/256); + clkdv_period = ((period_clkin*CLKDV_DIVIDE)/2); + + @(posedge CLKIN); + period_updated = 1; + start_time = $time; + repeat (6) begin + CLK0 = ~CLK0; + CLK2X = ~CLK2X; + #(clk_period); + CLK2X = ~CLK2X; + #(clk_period); + end + repeat (6) begin + CLK0 = ~CLK0; + CLK2X = ~CLK2X; + #(clk_period); + CLK2X = ~CLK2X; + #(clk_period); + end + if (clkfb_type != 0) + wait(fbsync==1); + if (ps_type != 0) + if (PHASE_SHIFT > 0) + #((period_clkin*PHASE_SHIFT)/256); + else if (PHASE_SHIFT < 0) + #((period_clkin)-((period_clkin*PHASE_SHIFT)/256)); + align = 1; + CLK0 = ~CLK0; + CLK2X = ~CLK2X; + #(clk_period); + CLK90 = ~CLK90; + CLK2X = ~CLK2X; + CLK2X180 = ~CLK2X180; + #(clk_period); + repeat (7) begin + CLK0 = ~CLK0; + CLK180 = ~CLK180; + CLK2X = ~CLK2X; + CLK2X180 = ~CLK2X180; + #(clk_period); + CLK90 = ~CLK90; + CLK2X = ~CLK2X; + CLK2X180 = ~CLK2X180; + CLK270 = ~CLK270; + #(clk_period); + end + LOCKED_out = 1'b1; + clkin_cnt_en = 1'b1; + while (RST==0) begin + CLK0 = ~CLK0; + CLK180 = ~CLK180; + CLK2X = ~CLK2X; + CLK2X180 = ~CLK2X180; + #(clk_period); + CLK90 = ~CLK90; + CLK270 = ~CLK270; + CLK2X = ~CLK2X; + CLK2X180 = ~CLK2X180; + #(clk_period); + CLK0 = ~CLK0; + CLK180 = ~CLK180; + CLK2X = ~CLK2X; + CLK2X180 = ~CLK2X180; + #(clk_period); + CLK90 = ~CLK90; + CLK270 = ~CLK270; + CLK2X = ~CLK2X; + CLK2X180 = ~CLK2X180; + if (pos_shift_st[0]==1'b1 && pos_shift[0]==1'b0) begin + #((clk_period)+shift_ammount); + pos_shift[0] = 1; + end + else if (neg_shift_st[0]==1'b1 && neg_shift[0]==1'b0) begin + #((clk_period)-shift_ammount); + neg_shift[0] = 1; + end + else begin + if (pos_shift_st[0] == 1'b0) + pos_shift[0] = 0; + if (neg_shift_st[0] == 1'b0) + neg_shift[0] = 0; + #(clk_period); + end + if (clkin_error) + wait (0); + end + end + + always begin: clkfx_dcm + pos_shift[1]=1'b0; + neg_shift[1]=1'b0; + CLKFX = 1'b0; + CLKFX180 = 1'b0; + rst_done_fx <= 1'b1; + wait (rst_tmp==0 && RST==0); + wait (LOCKED_out==1); + rst_done_fx <= 1'b0; + CLKFX = 1; + CLKFX180 = 0; + while (RST== 0 && rst_tmp==0) begin + #(clkfx_period); + CLKFX = ~CLKFX; + CLKFX180 = ~CLKFX180; + if (pos_shift_st[1]==1'b1 && pos_shift[1]==1'b0) begin + #((clkfx_period)+shift_ammount); + pos_shift[1] <= 1; + end + else if (neg_shift_st[1]==1'b1 && neg_shift[1]==1'b0) begin + #((clkfx_period)-shift_ammount); + neg_shift[1] <= 1; + end + else begin + if (pos_shift_st[1] == 1'b0) + pos_shift[1] <= 0; + if (neg_shift_st[1] == 1'b0) + neg_shift[1] <= 0; + #(clkfx_period); + end + CLKFX = ~CLKFX; + CLKFX180 = ~CLKFX180; + if (clkin_error) + wait(0); + end + end + + always begin: clkdv_dcm + pos_shift[2] = 0; + neg_shift[2] = 0; + CLKDV = 1'b0; + rst_done_dv <= 1'b1; + wait (rst_tmp==0 && RST==0); + wait (LOCKED_out==1); + rst_done_dv <= 1'b0; + CLKDV = ~CLKDV; + while (RST==0 && rst_tmp==0) begin + if (pos_shift_st[2]==1'b1 && pos_shift[2]==1'b0) begin + #(clkdv_period+shift_ammount); + pos_shift[2] = 1; + end + else if (neg_shift_st[2]==1'b1 && neg_shift[2]==1'b0) begin + #(clkdv_period-shift_ammount); + neg_shift[2] = 1; + end + else begin + if (pos_shift_st[2] == 1'b0) + pos_shift[2] <= 0; + if (neg_shift_st[2] == 1'b0) + neg_shift[2] <= 0; + #(clkdv_period); + end + CLKDV = ~CLKDV; + if (clkin_error) + wait(0); + end + end + + initial shift = 0; + + always @(posedge PSCLK) begin: dps_dcm + psdone_out <= 1'b0; + if (ps_type==2) begin + if (PSEN) begin + if (pos_shift != 3'b000 || neg_shift != 3'b000) + $display("Warning : Please wait for PSDONE signal before adjusting the Phase Shift. %m at time %t. ", $time); + else begin + if (PSINCDEC==1'b1 && pos_shift==3'b000) begin + pos_shift_st <= 3'b111; + shift = shift + 1; + if (shift > 256) + ps_overflow_out_ext <= 1; + else + ps_overflow_out_ext <= 0; + end + else if (PSINCDEC==1'b0 && neg_shift==3'b000) begin + neg_shift_st <= 3'b111; + shift = shift - 1; + if (shift < -256) + ps_overflow_out_ext <= 1; + else + ps_overflow_out_ext <= 0; + end + end + end + if (pos_shift==3'b111) begin + pos_shift_st <= 3'b000; + psdone_out <= 1'b1; + end + if (neg_shift==3'b111) begin + neg_shift_st <= 3'b000; + psdone_out <= 1'b1; + end + end + end // block: dps_dcm + + + always @(posedge CLKIN) + if (RST) begin + clkin_cnt <= 2'b00; + end + else begin + if (clkin_cnt_en ==1) + clkin_cnt <= clkin_cnt + 1; + end + + always @(posedge CLK0 or posedge RST) begin : status_dcm + if (RST) begin + old_clkin_cnt <= 0; + clkin_error <= 1'b0; + end + else + if (clkin_cnt_en== 1'b1) begin + #1 clkin_error <= 1'b0; + @(posedge CLK0); + if (clkin_cnt == old_clkin_cnt) begin + $display("Error: This DCM simulation for %m does not support the stopping of CLKIN.\nPlease use the standard DCM model to properly view this behavior.\nAll DCM outputs will be suspended until the DCM is reset."); + clkin_error <= 1; + wait (RST==1); + end + else + old_clkin_cnt <= clkin_cnt; + end + end + +end +endgenerate + + +endmodule + + +////////////////////////////////////////////////////// + +module dcm_clock_divide_by_2 (clock, clock_type, clock_out, rst); +input clock; +input clock_type; +input rst; +output clock_out; + +reg clock_out; +reg clock_div2; +reg [2:0] rst_reg; + +wire clk_src; + +initial begin + clock_out = 1'b0; + clock_div2 = 1'b0; +end + +always @(posedge clock) + clock_div2 <= ~clock_div2; + +always @(posedge clock) begin + rst_reg[0] <= rst; + rst_reg[1] <= rst_reg[0] & rst; + rst_reg[2] <= rst_reg[1] & rst_reg[0] & rst; +end + +assign clk_src = (clock_type) ? clock_div2 : clock; + +always @(clk_src or rst or rst_reg) + if (rst == 1'b0) + clock_out = clk_src; + else if (rst == 1'b1) begin + clock_out = 1'b0; + @(negedge rst_reg[2]); + if (clk_src == 1'b1) + @(negedge clk_src); + end + + +endmodule + +module dcm_maximum_period_check (clock); +parameter clock_name = ""; +parameter maximum_period = 0; +input clock; + +time clock_edge; +time clock_period; + +initial begin + clock_edge = 0; + clock_period = 0; +end + +always @(posedge clock) begin + clock_edge <= $time; + clock_period <= $time - clock_edge; + if (clock_period > maximum_period ) begin + $display(" Warning : Input clock period of, %1.3f ns, on the %s port of instance %m exceeds allotted value of %1.3f ns at simulation time %1.3f ns.", clock_period/1000.0, clock_name, maximum_period/1000.0, $time/1000.0); + end +end +endmodule + +module dcm_clock_lost (clock, enable, lost, rst); +input clock; +input enable; +input rst; +output lost; + +time clock_edge; +reg [63:0] period; +reg clock_low, clock_high; +reg clock_posedge, clock_negedge; +reg lost_r, lost_f, lost; +reg clock_second_pos, clock_second_neg; + +initial begin + clock_edge = 0; + clock_high = 0; + clock_low = 0; + lost_r = 0; + lost_f = 0; + period = 0; + clock_posedge = 0; + clock_negedge = 0; + clock_second_pos = 0; + clock_second_neg = 0; +end + +always @(posedge clock or posedge rst) + if (rst==1) + period <= 0; + else begin + clock_edge <= $time; + if (period != 0 && (($time - clock_edge) <= (1.5 * period))) + period <= $time - clock_edge; + else if (period != 0 && (($time - clock_edge) > (1.5 * period))) + period <= 0; + else if ((period == 0) && (clock_edge != 0) && clock_second_pos == 1) + period <= $time - clock_edge; + end + + +always @(posedge clock or posedge rst) + if (rst) + lost_r <= 0; + else + if (enable == 1 && clock_second_pos == 1) begin + #1; + if ( period != 0) + lost_r <= 0; + #((period * 9.1) / 10) + if ((clock_low != 1'b1) && (clock_posedge != 1'b1) && rst == 0) + lost_r <= 1; + end + +always @(posedge clock or negedge clock or posedge rst) + if (rst) begin + clock_second_pos <= 0; + clock_second_neg <= 0; + end + else if (clock) + clock_second_pos <= 1; + else if (~clock) + clock_second_neg <= 1; + +always @(negedge clock or posedge rst) + if (rst==1) begin + lost_f <= 0; + end + else begin + if (enable == 1 && clock_second_neg == 1) begin + if ( period != 0) + lost_f <= 0; + #((period * 9.1) / 10) + if ((clock_high != 1'b1) && (clock_negedge != 1'b1) && rst == 0) + lost_f <= 1; + end + end + +always @( lost_r or lost_f or enable) +begin + if (enable == 1) + lost = lost_r | lost_f; + else + lost = 0; +end + + +always @(posedge clock or negedge clock or posedge rst) + if (rst==1) begin + clock_low <= 1'b0; + clock_high <= 1'b0; + clock_posedge <= 1'b0; + clock_negedge <= 1'b0; + end + else begin + if (clock ==1) begin + clock_low <= 1'b0; + clock_high <= 1'b1; + clock_posedge <= 1'b0; + clock_negedge <= 1'b1; + end + else if (clock == 0) begin + clock_low <= 1'b1; + clock_high <= 1'b0; + clock_posedge <= 1'b1; + clock_negedge <= 1'b0; + end +end + + +endmodule diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/DCM_ADV.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/DCM_ADV.v new file mode 100644 index 0000000..d95388e --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/DCM_ADV.v @@ -0,0 +1,1754 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/virtex4/DCM_ADV.v,v 1.43 2008/10/02 22:39:17 yanx Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Digital Clock Manager with Advanced Features +// /___/ /\ Filename : DCM_ADV.v +// \ \ / \ Timestamp : Thu Mar 25 16:43:43 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 04/11/05 - Add parameter DFS_OSCILLATOR_MODE to support R. +// 04/22/05 - Change DRP set clkfx M/D value effected on RST=1, not rising +// edge. (CR 206731) +// 05/11/05 - Add parameter DCM_AUTOCALIBRATION (CR 208095). +// - Add clkin alignment check control to remove the glitch when +// clkin stopped. (CR207409). +// 05/19/05 - Add initial to all clock outputs. (CR 208380). +// 05/25/05 - Seperate clock_second_pos and neg to another process due to +// wait caused unreset. Set fb_delay_found after fb_delay computed. +// (CR 208771) +// 07/05/05 - Use counter to generate clkdv_out to align with clk0_out. (CR211465). +// 07/25/05 - Set CLKIN_PERIOD default to 10.0ns to (CR 213190). +// 12/02/05 - Add warning for un-used DRP address use. (CR 221885) +// 12/22/05 - LOCKED = x when RST less than 3 clock cycles (CR 222795) +// 01/06/06 - Remove GSR from 3 cycle check. (223099). +// 01/12/06 - Remove GSR from reset logic. (223099). +// 01/12/06 - Add rst_in to period_div and period_ps block to handle clkin frequency +// change case. (CR 221989). +// 01/26/06 - Remove $finish from DRP Warning and change invalid to unsupported +// address. (CR 224743) +// Add reset to maximum period check module (CR224287). +// 02/28/06 - Add SIM_DEVICE generic to support V5 and V4 M and D for CLKFX (BT#1003). +// Add integer and real to parameter declaration. +// 03/10/06 - Add wire declaration for lock_period_dly signal (CR 227126) +// 08/10/06 - Set PSDONE to 0 when CLKOUT_PHASE_SHIFT=FIXED (CR 227018). +// 03/07/07 - Change DRP CLKFX Multiplier to bit 15 to 8 and Divider to bit 7 to 0. +// (CR 435600). +// 04/06/07 - Enable the clock out in clock low time after reset in model +// clock_divide_by_2 (CR 437471). +// 06/04/07 - Add wire declaration for internal signals, Remove buf from unisim. +// 09/20/07 - Use 1.5 factor for clock stopped check when CLKIN divide by 2 set(CR446707). +// 11/01/07 - Add DRP DFS_FREQUENCY_MODE and DLL_FREQUENCY_MODE read/write support (CR435651) +// 12/20/07 - Add DRP CLKIN_DIVIDE_BY_2 read/write support (CR457282) +// 02/21/08 - Align clk2x to both clk0 pos and neg edges. (CR467858). +// 03/01/08 - Disable alignment of clkfb and clkin_fb check when ps_lock high (CR468893). +// 03/11/08 - Not check clock lost when negative edge period smaller than positive edge +// period in dcm_adv_clock_lost module (CR469499). +// 03/12/08 - always generate clk2x with even duty cycle regardless CLKIN duty cycle.(CR467858). +// 07/08/08 - Use clkin_div instead of period to generate lock_period_dly (CR476425) +// 10/02/08 - Reset ps_kick_off_cmd after phase shifting (CR490447) +// End Revision + +`timescale 1 ps / 1 ps +`define CLKFX_MULTIPLY_ADDR 80 +`define CLKFX_DIVIDE_ADDR 82 +`define PHASE_SHIFT_ADDR 85 +`define PHASE_SHIFT_KICK_OFF_ADDR 17 +`define DCM_DEFAULT_STATUS_ADDR 0 +`define DFS_FREQ_MODE_ADDR 65 +`define DLL_FREQ_MODE_ADDR 81 +`define CLKIN_DIV_BY2_ADDR 68 + + +module DCM_ADV ( + CLK0, + CLK180, + CLK270, + CLK2X, + CLK2X180, + CLK90, + CLKDV, + CLKFX, + CLKFX180, + DO, + DRDY, + LOCKED, + PSDONE, + CLKFB, + CLKIN, + DADDR, + DCLK, + DEN, + DI, + DWE, + PSCLK, + PSEN, + PSINCDEC, + RST +); + +parameter real CLKDV_DIVIDE = 2.0; +parameter integer CLKFX_DIVIDE = 1; +parameter integer CLKFX_MULTIPLY = 4; +parameter CLKIN_DIVIDE_BY_2 = "FALSE"; +parameter real CLKIN_PERIOD = 10.0; // non-simulatable +parameter CLKOUT_PHASE_SHIFT = "NONE"; +parameter CLK_FEEDBACK = "1X"; +parameter DCM_AUTOCALIBRATION = "TRUE"; +parameter DCM_PERFORMANCE_MODE = "MAX_SPEED"; // non-simulatable +parameter DESKEW_ADJUST = "SYSTEM_SYNCHRONOUS"; // non-simulatable +parameter DFS_FREQUENCY_MODE = "LOW"; +parameter DLL_FREQUENCY_MODE = "LOW"; +parameter DUTY_CYCLE_CORRECTION = "TRUE"; +parameter FACTORY_JF = 16'hF0F0; // non-simulatable +localparam integer MAXPERCLKIN = 1000000; // non-modifiable simulation parameter +localparam integer MAXPERPSCLK = 100000000; // non-modifiable simulation parameter +parameter integer PHASE_SHIFT = 0; +localparam integer SIM_CLKIN_CYCLE_JITTER = 300; // non-modifiable simulation parameter +localparam integer SIM_CLKIN_PERIOD_JITTER = 1000; // non-modifiable simulation parameter +parameter SIM_DEVICE ="VIRTEX4"; +parameter STARTUP_WAIT = "FALSE"; // non-simulatable + +localparam DFS_OSCILLATOR_MODE = "PHASE_FREQ_LOCK"; + +output CLK0; +output CLK180; +output CLK270; +output CLK2X180; +output CLK2X; +output CLK90; +output CLKDV; +output CLKFX180; +output CLKFX; +output DRDY; +output LOCKED; +output PSDONE; +output [15:0] DO; + +input CLKFB; +input CLKIN; +input DCLK; +input DEN; +input DWE; +input PSCLK; +input PSEN; +input PSINCDEC; +tri0 GSR = glbl.GSR; +input RST; +input [15:0] DI; +input [6:0] DADDR; + +reg CLK0; +reg CLK180; +reg CLK270; +reg CLK2X180; +reg CLK2X; +reg CLK90; +reg CLKDV; +reg CLKFX180; +reg CLKFX; + +wire [15:0] di_in; +wire [6:0] daddr_in; + +wire clkfb_in, clkin_in, dssen_in; +wire psclk_in, psen_in, psincdec_in, rst_in, gsr_in, rst_input ; +wire locked_out_out; +wire dwe_in, den_in, dclk_in, clkin_lost_out, clkfx_lost_out, clkfb_lost_out; +reg rst_flag; +reg clk0_out; +reg clk2x_out, clkdv_out; +reg clkfx_out, locked_out, psdone_out, ps_overflow_out; +reg clkfx_out_avg, clkfx_out_ph; +reg ps_lock; +reg drdy_out; +wire [15:0] do_out; +reg [15:0] do_out_s, do_out_drp, do_out_drp1; +reg do_stat_en; +reg [6:0] daddr_in_lat; +reg valid_daddr; + + +reg [1:0] clkfb_type; +reg [8:0] divide_type; +reg clkin_type_i; +wire clkin_type; +reg [2:0] ps_type; +reg [3:0] deskew_adjust_mode; +wire dfs_mode_type; +reg dfs_mode_type_i; +wire [1:0] dll_mode_type; +reg [1:0] dll_mode_type_i; +reg sim_device_type; +reg clk1x_type; +integer ps_in, ps_min, ps_max; +integer ps_in_ps, ps_in_psdrp, ps_in_curr; +integer ps_delay_ps, ps_delay_drp; +integer clkdv_cnt; + +reg lock_period, lock_delay, lock_clkin, lock_clkfb; +reg [1:0] lock_out; +reg lock_out1_neg; +reg lock_fb, lock_ps, lock_ps_dly; +reg fb_delay_found; +reg clock_stopped; +reg clkin_chkin, clkfb_chkin; + +wire chk_enable, chk_rst; +wire clkin_div; +wire locked_out_tmp; +wire lock_period_pulse; +reg lock_period_dly; + +reg clkin_ps; +reg clkin_fb; + +time FINE_SHIFT_RANGE; +time ps_delay; +time delay_edge; +time clkin_period [2:0]; +time period, period_50, period_25, period_25_rm; +time period_div; +time period_orig; +time period_stop_ck; +time period_ps; +time clkout_delay; +time fb_delay; +time period_fx, remain_fx; +time period_fxtmp, period_fxavg; +time period_dv_high, period_dv_low; +time cycle_jitter, period_jitter; +time clkin_div_edge, clkin_ps_edge, clkin_edge; +time tap_delay_step; + +reg clkin_window, clkfb_window; +reg [2:0] rst_reg; +reg [12:0] numerator, denominator, gcd; +reg [23:0] i, n, d, p; + +reg first_time_locked; +reg en_status; +reg [1521:0] mem_drp; +reg drp_lock; +reg drp_lock1; +reg ps_drp_lock, ps_drp_lock_tmp, ps_drp_lock_tmp1; +integer ps_drp, ps_in_drp; +reg ps_kick_off_cmd; + +reg single_step_lock, single_step_lock_tmp, single_step_done; +integer clkfx_multiply_drp, clkfx_divide_drp; +reg [7:0] clkfx_m_reg, clkfx_d_reg; +reg [15:0] clkfx_md_reg, dfs_mode_reg, dll_mode_reg, clkin_div2_reg; +reg inc_dec; + +real clock_stopped_factor; + + +reg notifier; + +initial begin + #1; + if ($realtime == 0) begin + $display ("Simulator Resolution Error : Simulator resolution is set to a value greater than 1 ps."); + $display ("In order to simulate the DCM_ADV, the simulator resolution must be set to 1ps or smaller."); + $finish; + end +end + +initial begin + case (CLKDV_DIVIDE) + 1.5 : divide_type = 'd3; + 2.0 : divide_type = 'd4; + 2.5 : divide_type = 'd5; + 3.0 : divide_type = 'd6; + 3.5 : divide_type = 'd7; + 4.0 : divide_type = 'd8; + 4.5 : divide_type = 'd9; + 5.0 : divide_type = 'd10; + 5.5 : divide_type = 'd11; + 6.0 : divide_type = 'd12; + 6.5 : divide_type = 'd13; + 7.0 : divide_type = 'd14; + 7.5 : divide_type = 'd15; + 8.0 : divide_type = 'd16; + 9.0 : divide_type = 'd18; + 10.0 : divide_type = 'd20; + 11.0 : divide_type = 'd22; + 12.0 : divide_type = 'd24; + 13.0 : divide_type = 'd26; + 14.0 : divide_type = 'd28; + 15.0 : divide_type = 'd30; + 16.0 : divide_type = 'd32; + default : begin + $display("Attribute Syntax Error : The attribute CLKDV_DIVIDE on DCM_ADV instance %m is set to %0.1f. Legal values for this attribute are 1.5, 2.0, 2.5, 3.0, 3.5, 4.0, 4.5, 5.0, 5.5, 6.0, 6.5, 7.0, 7.5, 8.0, 9.0, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0, or 16.0.", CLKDV_DIVIDE); + $finish; + end + endcase + +// if (DFS_OSCILLATOR_MODE == "AVE_FREQ_LOCK") +// if ((CLKFX_DIVIDE <= 0) || (4096 < CLKFX_DIVIDE)) begin +// $display("Attribute Syntax Error : The attribute CLKFX_DIVIDE on DCM_ADV instance %m is set to %d. Legal values for this attribute are 1 ... 4096.", CLKFX_DIVIDE); +// $finish; +// end +// else + if ((CLKFX_DIVIDE <= 0) || (32 < CLKFX_DIVIDE)) begin + $display("Attribute Syntax Error : The attribute CLKFX_DIVIDE on DCM_ADV instance %m is set to %d. Legal values for this attribute are 1 ... 32.", CLKFX_DIVIDE); + $finish; + end + +// if (DFS_OSCILLATOR_MODE == "AVE_FREQ_LOCK") +// if ((CLKFX_MULTIPLY <= 1) || (4096 < CLKFX_MULTIPLY)) begin +// $display("Attribute Syntax Error : The attribute CLKFX_MULTIPLY on DCM_ADV instance %m is set to %d. Legal values for this attribute are 2 ... 4096.", CLKFX_MULTIPLY); +// $finish; +// end +// else + if ((CLKFX_MULTIPLY <= 1) || (32 < CLKFX_MULTIPLY)) begin + $display("Attribute Syntax Error : The attribute CLKFX_MULTIPLY on DCM_ADV instance %m is set to %d. Legal values for this attribute are 2 ... 32.", CLKFX_MULTIPLY); + $finish; + end + + case (CLKIN_DIVIDE_BY_2) + "FALSE" : begin + clkin_type_i = 0; + clock_stopped_factor = 2.0; + end + "TRUE" : begin + clkin_type_i = 1; + clock_stopped_factor = 1.5; + end + default : begin + $display("Attribute Syntax Error : The attribute CLKIN_DIVIDE_BY_2 on DCM_ADV instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", CLKIN_DIVIDE_BY_2); + $finish; + end + endcase + + case (CLKOUT_PHASE_SHIFT) + "NONE" : begin + ps_in = 0 + 256; + ps_type = 3'b000; + end + "FIXED" : begin + ps_in = PHASE_SHIFT + 256; + ps_max = 255 + 256; + ps_min = -255 + 256; + ps_type = 3'b001; + if ( DCM_PERFORMANCE_MODE == "MAX_RANGE" ) + FINE_SHIFT_RANGE = 10000; + else + FINE_SHIFT_RANGE = 7000; + if ((PHASE_SHIFT < -255) || (PHASE_SHIFT > 255)) begin + $display("Attribute Syntax Error : The attribute PHASE_SHIFT on DCM_ADV instance %m is set to %d. Legal values for this attribute are -255 ... 255.", PHASE_SHIFT); + $display("Error : PHASE_SHIFT = %d is not -255 ... 255.", PHASE_SHIFT); + $finish; + end + end + "VARIABLE_POSITIVE" : begin + ps_in = PHASE_SHIFT + 256; + ps_max = 255 + 256; + ps_min = 0 + 256; + ps_type = 3'b011; + if ( DCM_PERFORMANCE_MODE == "MAX_RANGE" ) + FINE_SHIFT_RANGE = 10000; + else + FINE_SHIFT_RANGE = 7000; + if ((PHASE_SHIFT < 0) || (PHASE_SHIFT > 255)) begin + $display("Attribute Syntax Error : The attribute PHASE_SHIFT on DCM_ADV instance %m is set to %d. Legal values for this attribute are 0 ... 255.", PHASE_SHIFT); + $display("Error : PHASE_SHIFT = %d is not 0 ... 255.", PHASE_SHIFT); + $finish; + end + end + "VARIABLE_CENTER" : begin + ps_in = PHASE_SHIFT + 256; + ps_max = 255 + 256; + ps_min = -255 + 256; + ps_type = 3'b100; + if ( DCM_PERFORMANCE_MODE == "MAX_RANGE" ) + FINE_SHIFT_RANGE = 5000; + else + FINE_SHIFT_RANGE = 3500; + if ((PHASE_SHIFT < -255) || (PHASE_SHIFT > 255)) begin + $display("Attribute Syntax Error : The attribute PHASE_SHIFT on DCM_ADV instance %m is set to %d. Legal values for this attribute are -255 ... 255.", PHASE_SHIFT); + $display("Error : PHASE_SHIFT = %d is not -255 ... 255.", PHASE_SHIFT); + $finish; + end + end + "DIRECT" : begin + ps_in = PHASE_SHIFT; + ps_max = 1023; + ps_min = 0; + ps_type = 3'b101; + if (DCM_PERFORMANCE_MODE == "MAX_RANGE") + begin + tap_delay_step = 18; + FINE_SHIFT_RANGE = 10000; + end + else + begin + tap_delay_step = 11; + FINE_SHIFT_RANGE = 7000; + end + if ((PHASE_SHIFT < 0) || (PHASE_SHIFT > 1023)) begin + $display("Attribute Syntax Error : The attribute PHASE_SHIFT on DCM_ADV instance %m is set to %d. Legal values for this attribute is 0 to 1023.", PHASE_SHIFT); + $display("Error : PHASE_SHIFT = %d is not 0 to 1023.", PHASE_SHIFT); + $finish; + end + end + default : begin + $display("Attribute Syntax Error : The Attribute CLKOUT_PHASE_SHIFT on DCM_ADV instance %m is set to %s. Legal values for this attribute are NONE, FIXED, VARIABLE_POSITIVE, VARIABLE_CENTER or DIRECT.", CLKOUT_PHASE_SHIFT); + $finish; + end + endcase + + ps_in_curr = ps_in; + ps_in_ps = ps_in; + ps_in_psdrp = ps_in; + + case (CLK_FEEDBACK) + "NONE" : begin + clkfb_type = 0; + $display("Attribute CLK_FEEDBACK is set to value NONE."); + $display("In this mode, the output ports CLK0, CLK180, CLK270, CLK2X, CLK2X180, CLK90 and CLKDV can have any random phase relation w.r.t. input port CLKIN"); + end + "1X" : clkfb_type = 1; + default : begin + $display("Attribute Syntax Error : The attribute CLK_FEEDBACK on DCM_ADV instance %m is set to %s. Legal values for this attribute are NONE or 1X.", CLK_FEEDBACK); + $finish; + end + endcase + + case (DCM_PERFORMANCE_MODE) + "MAX_SPEED" : ; + "MAX_RANGE" : ; + default : begin + $display("Attribute Syntax Error : The Attribute DCM_PERFORMANCE_MODE on DCM_ADV instance %m is set to %s. Legal values for this attribute are MAX_SPEED or MAX_RANGE.", DCM_PERFORMANCE_MODE); + $finish; + end + endcase + + case (DESKEW_ADJUST) + "SOURCE_SYNCHRONOUS" : deskew_adjust_mode = 0; + "SYSTEM_SYNCHRONOUS" : deskew_adjust_mode = 11; + "0" : deskew_adjust_mode = 0; + "1" : deskew_adjust_mode = 1; + "2" : deskew_adjust_mode = 2; + "3" : deskew_adjust_mode = 3; + "4" : deskew_adjust_mode = 4; + "5" : deskew_adjust_mode = 5; + "6" : deskew_adjust_mode = 6; + "7" : deskew_adjust_mode = 7; + "8" : deskew_adjust_mode = 8; + "9" : deskew_adjust_mode = 9; + "10" : deskew_adjust_mode = 10; + "11" : deskew_adjust_mode = 11; + "12" : deskew_adjust_mode = 12; + "13" : deskew_adjust_mode = 13; + "14" : deskew_adjust_mode = 14; + "15" : deskew_adjust_mode = 15; + "16" : deskew_adjust_mode = 16; + "17" : deskew_adjust_mode = 17; + "18" : deskew_adjust_mode = 18; + "19" : deskew_adjust_mode = 19; + "20" : deskew_adjust_mode = 20; + "21" : deskew_adjust_mode = 21; + "22" : deskew_adjust_mode = 22; + "23" : deskew_adjust_mode = 23; + "24" : deskew_adjust_mode = 24; + "25" : deskew_adjust_mode = 25; + "26" : deskew_adjust_mode = 26; + "27" : deskew_adjust_mode = 27; + "28" : deskew_adjust_mode = 28; + "29" : deskew_adjust_mode = 29; + "30" : deskew_adjust_mode = 30; + "31" : deskew_adjust_mode = 31; + default : begin + $display("Attribute Syntax Error : The attribute DESKEW_ADJUST on DCM_ADV instance %m is set to %s. Legal values for this attribute are SOURCE_SYNCHRONOUS, SYSTEM_SYNCHRONOUS or 0 ... 15.", DESKEW_ADJUST); + $finish; + end + endcase + + case (DFS_FREQUENCY_MODE) + "HIGH" : dfs_mode_type_i = 1; + "LOW" : dfs_mode_type_i = 0; + default : begin + $display(" Attribute Syntax Error : The attribute DFS_FREQUENCY_MODE on DCM_ADV instance %m is set to %s. Legal values for this attribute are HIGH or LOW.", DFS_FREQUENCY_MODE); + $finish; + end + endcase + + period_jitter = SIM_CLKIN_PERIOD_JITTER; + cycle_jitter = SIM_CLKIN_CYCLE_JITTER; + + case (DLL_FREQUENCY_MODE) + "HIGH" : dll_mode_type_i = 2'b11; + "LOW" : dll_mode_type_i = 2'b00; + default : begin + $display("Attribute Syntax Error : The attribute DLL_FREQUENCY_MODE on DCM_ADV instance %m is set to %s. Legal values for this attribute are HIGH or LOW.", DLL_FREQUENCY_MODE); + $finish; + end + endcase + + case (FACTORY_JF) + 16'hF0F0 : ; + default : + $display("Attribute Syntax Warning : The attribute FACTORY_JF on DCM_ADV instance %m is set to %h. Legal value is F0F0.", FACTORY_JF); + endcase + + case (DUTY_CYCLE_CORRECTION) + "FALSE" : if (SIM_DEVICE=="VIRTEX4") clk1x_type = 0; else clk1x_type = 1; + "TRUE" : clk1x_type = 1; + default : begin + $display("Attribute Syntax Error : The attribute DUTY_CYCLE_CORRECTION on DCM_ADV instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", DUTY_CYCLE_CORRECTION); + $finish; + end + endcase + + case (STARTUP_WAIT) + "FALSE" : ; + "TRUE" : ; + default : begin + $display("Attribute Syntax Error : The attribute STARTUP_WAIT on DCM_ADV instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", STARTUP_WAIT); + $finish; + end + endcase + + case (DCM_AUTOCALIBRATION) + "FALSE" : ; + "TRUE" : ; + default : begin + $display("Attribute Syntax Error : The attribute DCM_AUTOCALIBRATION on DCM_ADV instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", DCM_AUTOCALIBRATION); + $finish; + end + endcase + + case (SIM_DEVICE) + "VIRTEX5" : sim_device_type = 1; + "VIRTEX4" : sim_device_type = 0; + default : begin + $display("Attribute Syntax Error : The Attribute SIM_DEVICE on DCM_ADV instance %m is set to %s. Legal values for this attribute are VIRTEX5 or VIRTEX4.", SIM_DEVICE); + $finish; + end + endcase + +end + + +// +// input wire delays +// + + assign #100 LOCKED = locked_out_out; + assign #100 PSDONE = psdone_out; + assign #100 DO = do_out; + assign #100 DRDY = drdy_out; + assign clkin_in = CLKIN; + assign clkfb_in = CLKFB; + assign psclk_in = PSCLK; + assign psen_in = PSEN; + assign psincdec_in = PSINCDEC; + assign gsr_in = GSR; + assign rst_input = RST; + assign daddr_in = DADDR; + assign di_in = DI; + assign dwe_in = DWE; + assign den_in = DEN; + assign dclk_in = DCLK; + +assign rst_in = rst_input; + +dcm_adv_clock_divide_by_2 i_clock_divide_by_2 (clkin_in, clkin_type, clkin_div, rst_in); + +dcm_adv_maximum_period_check #("CLKIN", MAXPERCLKIN) i_max_clkin (clkin_in, rst_in); +dcm_adv_maximum_period_check #("PSCLK", MAXPERPSCLK) i_max_psclk (psclk_in, rst_in); + +dcm_adv_clock_lost i_clkin_lost (clkin_in, first_time_locked, clkin_lost_out, rst_in); +dcm_adv_clock_lost i_clkfx_lost (CLKFX, first_time_locked, clkfx_lost_out, rst_in); +dcm_adv_clock_lost i_clkfb_lost (CLKFB, first_time_locked, clkfb_lost_out, rst_in); + + +always @(clkin_div) + clkin_ps <= #(ps_delay) clkin_div; + +always @(clkin_ps or lock_fb) + clkin_fb = clkin_ps & lock_fb; + +always @(posedge clkin_fb or posedge chk_rst) + if (chk_rst) + clkin_chkin <= 0; + else + clkin_chkin <= 1; + +always @(posedge clkfb_in or posedge chk_rst) + if (chk_rst) + clkfb_chkin <= 0; + else + clkfb_chkin <= 1; + + assign chk_rst = (rst_in==1 || clock_stopped==1 ) ? 1 : 0; + assign chk_enable = (clkin_chkin == 1 && clkfb_chkin == 1 && + lock_ps ==1 && lock_fb ==1 ) ? 1 : 0; + +always @(posedge clkin_div or posedge rst_in) + if (rst_in) begin + period_div <= 0; + clkin_div_edge <= 0; + end + else + if ( clkin_div == 1) begin + clkin_div_edge <= $time; + if (($time - clkin_div_edge) <= (1.5 * period_div)) + period_div <= $time - clkin_div_edge; + else if ((period_div == 0) && (clkin_div_edge != 0)) + period_div <= $time - clkin_div_edge; + end + + +always @(posedge clkin_ps or posedge rst_in) + if (rst_in) begin + period_ps <= 0; + clkin_ps_edge <= 0; + end + else + if (clkin_ps==1) begin + clkin_ps_edge <= $time; + if (($time - clkin_ps_edge) <= (1.5 * period_ps)) + period_ps <= $time - clkin_ps_edge; + else if ((period_ps == 0) && (clkin_ps_edge != 0)) + period_ps <= $time - clkin_ps_edge; + end + +always @(posedge clkin_ps) begin + lock_ps <= lock_period; + lock_ps_dly <= lock_ps; + lock_fb <= lock_ps_dly; +end + +always @(period or fb_delay) + if (fb_delay ==0) + clkout_delay = 0; + else + clkout_delay = period - fb_delay; + +// +// generate master reset signal +// + +always @(posedge clkin_in) begin + rst_reg[0] <= rst_input; + rst_reg[1] <= rst_reg[0] & rst_input; + rst_reg[2] <= rst_reg[1] & rst_reg[0] & rst_input; +end + +reg rst_tmp1, rst_tmp2; +initial +begin +rst_tmp1 = 0; +rst_tmp2 = 0; +rst_flag = 0; +end + +always @(rst_input) +begin + if (rst_input) + rst_flag = 0; + + rst_tmp1 = rst_input; + if (rst_tmp1 == 0 && rst_tmp2 == 1) begin + if ((rst_reg[2] & rst_reg[1] & rst_reg[0]) == 0) begin + rst_flag = 1; + $display("Input Error : RST on instance %m must be asserted for 3 CLKIN clock cycles."); + end + end + rst_tmp2 = rst_tmp1; +end + +initial begin + CLK0 = 0; + CLK2X =0; + CLK2X180 = 0; + CLK90 = 0; + CLK180 =0; + CLK270 = 0; + CLKDV = 0; + CLKFX = 0; + CLKFX180 =0; + clk0_out = 0; + clk2x_out = 0; + clkdv_cnt = 0; + clkdv_out = 0; + clkfb_window = 0; + clkfx_out = 0; + clkfx_out_avg = 0; + clkfx_out_ph = 0; + clkin_div_edge = 0; + clkin_period[0] = 0; + clkin_period[1] = 0; + clkin_period[2] = 0; + period = 0; + clkin_ps_edge = 0; + clkin_window = 0; + clkout_delay = 0; + clock_stopped = 1; + fb_delay = 0; + fb_delay_found = 0; + lock_clkfb = 0; + lock_clkin = 0; + lock_delay = 0; + lock_fb = 0; + lock_out = 2'b00; + lock_out1_neg = 0; + lock_period = 0; + lock_period_dly = 0; + lock_ps = 0; + lock_ps_dly = 0; + locked_out = 0; + period = 0; + period_div = 0; + period_fx = 0; + period_fxavg = 0; + period_orig = 0; + period_stop_ck = 0; + period_ps = 0; + delay_edge = 0; + psdone_out = 0; + ps_delay = 0; + ps_lock = 0; + inc_dec = 0; + ps_overflow_out = 0; + ps_delay_ps = 0; + ps_delay_drp = 0; + rst_reg = 3'b000; + numerator = CLKFX_MULTIPLY; + denominator = CLKFX_DIVIDE; + clkfx_multiply_drp = CLKFX_MULTIPLY; + clkfx_divide_drp = CLKFX_DIVIDE; + clkfx_m_reg = CLKFX_MULTIPLY; + clkfx_d_reg = CLKFX_DIVIDE; + clkfx_md_reg = {clkfx_m_reg, clkfx_d_reg}; + gcd = 1; + drdy_out = 0; + do_out_drp = 16'h0000; + do_out_drp1 = 16'h0000; + do_out_s = 16'h0000; + valid_daddr = 0; + + first_time_locked = 0; + en_status = 0; + drp_lock = 0; + ps_drp = 0; + ps_kick_off_cmd = 0; + single_step_lock = 0; + single_step_lock_tmp = 0; + single_step_done = 0; + ps_drp_lock = 0; + ps_drp_lock_tmp = 0; + clkin_chkin = 0; + clkfb_chkin = 0; + + dfs_mode_reg = {13'bxxxxxxxxxxxxx, dfs_mode_type_i, 2'bxx}; + dll_mode_reg = {12'bxxxxxxxxxxxx, dll_mode_type_i, 2'bxx}; + clkin_div2_reg = {5'bxxxxx, clkin_type_i, 10'bxxxxxxxxxx}; + do_stat_en = 1; +end + + + assign dfs_mode_type = dfs_mode_reg[2]; + assign dll_mode_type = dll_mode_reg[3:2]; + assign clkin_type = clkin_div2_reg[10]; +// +// phase shift parameters +// + +always @(posedge lock_period) begin + if ((ps_type == 3'b000) || (ps_type == 3'b001) || (ps_type == 3'b011) || (ps_type == 3'b100)) begin + if (PHASE_SHIFT > 0) begin + if ((ps_in * period_orig / 256) > period_orig + FINE_SHIFT_RANGE) begin + $display("Function Error : Instance %m Requested Phase Shift = PHASE_SHIFT * PERIOD / 256 = %d * %1.3f / 256 = %1.3f. This exceeds the FINE_SHIFT_RANGE of %1.3f ns.", PHASE_SHIFT, period_orig / 1000.0, PHASE_SHIFT * period_orig/ 256 / 1000.0, FINE_SHIFT_RANGE / 1000.0); + $finish; + end + end + else if (PHASE_SHIFT < 0) begin + if ((period_orig > FINE_SHIFT_RANGE) && + ((ps_in * period_orig / 256) < period_orig - FINE_SHIFT_RANGE)) begin + $display("Function Error : Instance %m Requested Phase Shift = PHASE_SHIFT * PERIOD / 256 = %d * %1.3f / 256 = %1.3f. This exceeds the FINE_SHIFT_RANGE of %1.3f ns.", PHASE_SHIFT, period_orig / 1000.0, -(PHASE_SHIFT) * period_orig / 256 / 1000.0, FINE_SHIFT_RANGE / 1000.0); + $finish; + end + end + end + else if (ps_type == 3'b101) begin + if ((ps_in * tap_delay_step) > FINE_SHIFT_RANGE) begin + $display(" Phase shift Error : Allowed phase shift range on instance %m is between 0 to %d. ", FINE_SHIFT_RANGE / tap_delay_step); + $finish; + end + end +end + +always @(posedge lock_period_pulse or posedge rst_in or ps_delay_ps or ps_delay_drp or ps_in_ps + or ps_in_psdrp) + if (rst_in) begin + ps_delay <= 0; + ps_in_curr <= ps_in; + end + else if (lock_period_pulse) begin + if ((ps_type == 3'b000) || (ps_type == 3'b001) || (ps_type == 3'b011) || (ps_type == 3'b100)) + ps_delay <= (ps_in * period_div / 256); + else if (ps_type == 3'b101) + ps_delay <= ps_in * tap_delay_step; + end + else begin + if (((ps_type == 3'b011) || (ps_type == 3'b100) ) ) + begin + ps_in_curr = ps_in_ps; + ps_delay = (ps_in_ps * period_div / 256); + end + else if ((ps_type == 3'b101) && (ps_lock==1)) + begin + ps_in_curr = ps_in_ps; + ps_delay = ps_in_ps * tap_delay_step; + end + else if ((ps_type == 3'b101) && (ps_drp_lock==1)) + begin + ps_in_curr = ps_in_psdrp; + ps_delay = ps_delay_drp; + end + end + + + + +always @(posedge psclk_in or posedge rst_in) + if (rst_in) begin + ps_in_ps <= ps_in; + ps_overflow_out <= 0; +// ps_delay_ps <= 0; + end + else begin + if ((ps_type == 3'b011) || (ps_type == 3'b100) ) begin + if (psen_in) + if (ps_lock == 1) + $display(" Warning : Please wait for PSDONE signal before adjusting the Phase Shift."); + else + if (psincdec_in == 1) begin + if (ps_in_ps == ps_max) + ps_overflow_out <= 1; + else if (((ps_in_ps + 1) * period_orig / 256) > period_orig + FINE_SHIFT_RANGE) + ps_overflow_out <= 1; + else begin + ps_in_ps <= ps_in_ps + 1; + ps_overflow_out <= 0; + end + ps_lock <= 1; + end + else if (psincdec_in == 0) begin + if (ps_in_ps == ps_min) + ps_overflow_out <= 1; + else if ((period_orig > FINE_SHIFT_RANGE) && + (((ps_in_ps - 1) * period_orig / 256) < period_orig - FINE_SHIFT_RANGE)) + ps_overflow_out <= 1; + else begin + ps_in_ps <= ps_in_ps - 1; + ps_overflow_out <= 0; + end + ps_lock <= 1; + end + end + if (ps_type == 3'b101) begin + if (psen_in == 1) begin + if (ps_lock == 1) begin + $display(" Warning : Please wait for PSDONE signal before adjusting the Phase Shift. "); + end + else + begin + if (psincdec_in == 1) begin + if (ps_in_curr == ps_max) + ps_overflow_out <= 1; + else if (ps_in_curr * tap_delay_step > FINE_SHIFT_RANGE) + ps_overflow_out <= 1; + else + begin + ps_in_ps <= ps_in_curr + 1; + ps_overflow_out <= 0; + end + ps_lock <= 1; + end + else if (psincdec_in == 0) begin + if (ps_in_curr == ps_min) + ps_overflow_out <= 1; + else if (ps_in_curr * tap_delay_step > FINE_SHIFT_RANGE) + ps_overflow_out <= 1; + else + begin + ps_in_ps <= ps_in_curr - 1; + ps_overflow_out <= 0; + end + ps_lock <= 1; + end + end + end + end + if ( psdone_out == 1) + ps_lock <= 0; +end + +always @(posedge clkin_ps or posedge rst_in) + if (rst_in) begin + single_step_lock <= 0; + ps_in_psdrp <= ps_in; + ps_delay_drp <= 0; + end + else begin + if (ps_type == 3'b101) begin + if (ps_drp_lock == 1) begin + if (inc_dec == 1) begin + if (ps_in_curr < ps_in_drp) begin + if (single_step_lock == 0) + begin + single_step_lock <= 1; + ps_in_psdrp <= ps_in_curr + 1; + ps_delay_drp <= ps_delay + tap_delay_step; + end + end + else if (ps_in_curr == ps_in_drp) + ps_drp_lock <= 0; + end + else if (inc_dec == 0) begin + if (ps_in_curr > ps_in_drp) begin + if (single_step_lock == 0) + begin + single_step_lock <= 1; + ps_in_psdrp <= ps_in_curr - 1; + ps_delay_drp <= ps_delay - tap_delay_step; + end + end + else if (ps_in_psdrp == ps_in_drp) + ps_drp_lock <= 0; + end + end + + if ( single_step_lock_tmp == 1) + single_step_lock <= 0; + + if (ps_drp_lock_tmp == 1) + ps_drp_lock <= 1; + end +end + +always @( single_step_lock or clkin_ps) +begin + @( posedge single_step_lock) + @( posedge clkin_ps) + @( posedge clkin_ps) + @( posedge clkin_ps) + single_step_lock_tmp <= 1; + @( posedge clkin_ps) + single_step_lock_tmp <= 0; +end + +always @( ps_kick_off_cmd or dclk_in or clkin_in or ps_drp_lock ) +begin + @(posedge ps_kick_off_cmd) + @( posedge dclk_in) + @( posedge dclk_in) + @( posedge clkin_in) + @( posedge clkin_in) + @( posedge clkin_in) + @( posedge clkin_in) + @( posedge clkin_in) + ps_drp_lock_tmp <= 1; + @( posedge ps_drp_lock) + ps_drp_lock_tmp <= 0; +end + +always @(posedge ps_lock or negedge ps_drp_lock ) + if (ps_type != 3'b000 || ps_type != 3'b001) begin + @(posedge clkin_ps) + @(posedge clkin_ps) + @(posedge clkin_ps) + @(posedge clkin_ps) + @(posedge psclk_in) + @(posedge psclk_in) + begin + psdone_out = 1; + @(posedge psclk_in); + psdone_out = 0; + end + end + +// +// determine clock period +// + +always @(period_orig) + period_stop_ck = period_orig * clock_stopped_factor; + + +always @(posedge clkin_div or negedge clkin_div or posedge rst_in) + if ( rst_in == 1) + begin + clkin_period[0] <= 0; + clkin_period[1] <= 0; + clkin_period[2] <= 0; + clkin_edge <= 0; + end + else + if (clkin_div == 1) begin + clkin_edge <= $time; + clkin_period[2] <= clkin_period[1]; + clkin_period[1] <= clkin_period[0]; + if (clkin_edge != 0) + clkin_period[0] <= $time - clkin_edge; + end + else if (clkin_div == 0) + if (lock_period == 1) begin + if (100000000 < clkin_period[0]/1000) + begin + end +// else if ((period_orig * 2 < clkin_period[0]) && (clock_stopped == 0)) begin + else if ((period_stop_ck <= clkin_period[0]) && (clock_stopped == 0)) begin + clkin_period[0] <= clkin_period[1]; + end + end + +// +// evaluate_clock_period process +// +always @(negedge clkin_div or posedge rst_in) + if (rst_in == 1) begin + lock_period <= 0; + clock_stopped <= 1; + period_fxtmp <= 0; + end + else begin + if (lock_period == 1'b0) begin + if ((clkin_period[0] != 0) && + (clkin_period[0] - cycle_jitter <= clkin_period[1]) && + (clkin_period[1] <= clkin_period[0] + cycle_jitter) && + (clkin_period[1] - cycle_jitter <= clkin_period[2]) && + (clkin_period[2] <= clkin_period[1] + cycle_jitter)) begin + lock_period <= 1; + period_orig <= (clkin_period[0] + + clkin_period[1] + + clkin_period[2]) / 3; + period_fxtmp <= (clkin_period[0] + + clkin_period[1] + + clkin_period[2]) / 3; + period <= clkin_period[0]; + end + end + else if (lock_period == 1'b1) begin + if (100000000 < (clkin_period[0] / 1000)) begin + $display(" Warning : CLKIN stopped toggling on instance %m exceeds %d ms. Current CLKIN Period = %1.3f ns.", 10000, clkin_period[0] / 1000.0); + lock_period <= 0; + @(negedge rst_reg[2]); + end +// else if ((period_orig * 2 < clkin_period[0]) && clock_stopped == 1'b0) begin + else if ((period_stop_ck <= clkin_period[0]) && clock_stopped == 1'b0) begin +// clkin_period[0] = clkin_period[1]; + clock_stopped <= 1'b1; + end + else if ((clkin_period[0] < period_orig - period_jitter) || + (period_orig + period_jitter < clkin_period[0])) begin + $display(" Warning : Input Clock Period Jitter on instance %m exceeds %1.3f ns. Locked CLKIN Period = %1.3f. Current CLKIN Period = %1.3f.", period_jitter / 1000.0, period_orig / 1000.0, clkin_period[0] / 1000.0); + lock_period <= 0; + @(negedge rst_reg[2]); + end + else if ((clkin_period[0] < clkin_period[1] - cycle_jitter) || + (clkin_period[1] + cycle_jitter < clkin_period[0])) begin + $display(" Warning : Input Clock Cycle-Cycle Jitter on instance %m exceeds %1.3f ns. Previous CLKIN Period = %1.3f. Current CLKIN Period = %1.3f.", cycle_jitter / 1000.0, clkin_period[1] / 1000.0, clkin_period[0] / 1000.0); + lock_period <= 0; + @(negedge rst_reg[2]); + end + else begin + period <= clkin_period[0]; + clock_stopped <= 1'b0; + period_fxtmp <= (clkin_period[0] + + clkin_period[1] + + clkin_period[2]) / 3; + end + end +end + + always @(posedge clkin_div or posedge rst_in) + if (rst_in) + lock_period_dly <= 0; + else + lock_period_dly <= lock_period; + +// assign #(period_50) lock_period_dly = lock_period; + assign lock_period_pulse = (lock_period==1 && lock_period_dly==0) ? 1 : 0; + +// +// determine clock delay +// + + +//always @(posedge lock_period or posedge rst_in) begin +always @(posedge lock_ps_dly or posedge rst_in) + if (rst_in) begin + fb_delay <= 0; + fb_delay_found <= 0; + end + else begin + if (lock_period && clkfb_type != 0) begin + if (clkfb_type == 1) begin + @(posedge CLK0 or rst_in) + delay_edge = $time; + end + else if (clkfb_type == 2) begin + @(posedge CLK2X or rst_in) + delay_edge = $time; + end + @(posedge clkfb_in or rst_in) begin + fb_delay <= ($time - delay_edge) % period_orig; + fb_delay_found <= 1; + end + end + end + +// +// determine feedback lock +// + +always @(posedge clkfb_in or posedge rst_in) begin + if (rst_in) + clkfb_window <= 0; + else begin + #0 clkfb_window <= 1; + #cycle_jitter clkfb_window <= 0; + end +end + +always @(posedge clkin_fb or posedge rst_in) begin + if (rst_in) + clkin_window <= 0; + else begin + #0 clkin_window <= 1; + #cycle_jitter clkin_window <= 0; + end +end + +always @(posedge clkin_fb or posedge rst_in) begin + if (rst_in) + lock_clkin <= 0; + else begin + #1 + if ((clkfb_window && fb_delay_found ) || (clkin_lost_out == 1'b1 && lock_out[0]==1'b1)) + lock_clkin <= 1; + else + if (chk_enable ==1 && ps_lock == 0) + lock_clkin <= 0; + end +end + +always @(posedge clkfb_in or posedge rst_in) begin + if (rst_in) + lock_clkfb <= 0; + else begin + #1 + if ((clkin_window && fb_delay_found) || (clkin_lost_out == 1'b1 && lock_out[0]==1'b1)) + lock_clkfb <= 1; + else + if (chk_enable ==1 && ps_lock == 0) + lock_clkfb <= 0; + end +end + +always @(negedge clkin_fb or posedge rst_in) begin + if (rst_in) + lock_delay <= 0; + else + lock_delay <= lock_clkin || lock_clkfb; +end + +// +// generate lock signal +// + + assign locked_out_out = (rst_flag) ? 1'bx : locked_out; + +always @(posedge clkin_ps or posedge rst_in) + if (rst_in) begin + lock_out <= 2'b00; + locked_out <=0; + end + else begin + if (clkfb_type == 0) + lock_out[0] <= lock_period; + else + lock_out[0] <= lock_period & lock_delay & lock_fb; + lock_out[1] <= lock_out[0]; + locked_out <= lock_out[1]; + end + +always @(negedge clkin_ps or posedge rst_in) + if (rst_in) + lock_out1_neg <= 0; + else + lock_out1_neg <= lock_out[1]; + + +// +// generate the clk1x_out +// + +always @(period) begin + period_25 = period /4; + period_50 = 2 * period_25; +end + +always @(posedge clkin_ps or negedge clkin_ps or posedge rst_in) + if (rst_in) + clk0_out <= 0; + else if (clkin_ps ==1) + if (clk1x_type==1 && lock_out[0]) begin + clk0_out <= 1; + #(period_50); + clk0_out <= 0; + end + else + clk0_out <= 1; + else if (clkin_ps == 0 && ((clk1x_type && lock_out[0]) == 0 || (lock_out[0] ==1 && lock_out[1] == 0))) + clk0_out <= 0; + +// +// generate the clk2x_out +// + +always @(posedge clkin_ps or posedge rst_in ) + if (rst_in) + clk2x_out <= 0; + else begin + clk2x_out <= 1; + #(period_25) + clk2x_out <= 0; + if (lock_out[0]) begin + #(period_25); + clk2x_out <= 1; + #(period_25); + clk2x_out <= 0; + end + else begin + #(period_50); + end + end + +// +// generate the clkdv_out +// + +always @(posedge clkin_ps or negedge clkin_ps or posedge rst_in) + if (rst_in) begin + clkdv_out <= 1'b0; + clkdv_cnt <= 0; + end + else + if (lock_out1_neg) begin + if (clkdv_cnt >= divide_type -1) + clkdv_cnt <= 0; + else + clkdv_cnt <= clkdv_cnt + 1; + + if (clkdv_cnt < divide_type /2) + clkdv_out <= 1'b1; + else + if ( (divide_type[0] == 1'b1) && dll_mode_type == 2'b00) + clkdv_out <= #(period/4) 1'b0; + else + clkdv_out <= 1'b0; + end + +// +//determine_clkfx_divide_multiply +// +always @( rst_in or clkfx_multiply_drp or clkfx_divide_drp) +begin + if (rst_in == 1 ) begin + numerator = clkfx_multiply_drp; + denominator = clkfx_divide_drp; + end +end + +// +// generate fx output signal +// + +always @(lock_period or period_fxtmp or denominator or numerator ) + if (lock_period == 1'b1) + period_fxavg = (period_fxtmp * denominator) / (numerator * 2); + + +always @(lock_period or period or denominator or numerator ) + if (lock_period == 1'b1) begin + period_fx = (period * denominator) / (numerator * 2); + remain_fx = (period * denominator) % (numerator * 2); + end + +always @(clkfx_out_avg or clkfx_out_ph) + if (DFS_OSCILLATOR_MODE == "AVE_FREQ_LOCK") + clkfx_out = clkfx_out_avg; + else + clkfx_out = clkfx_out_ph; + + +always @(locked_out or posedge rst_in or clkfx_out_avg ) + if (rst_in == 1) + clkfx_out_avg <= 0; + else if (locked_out == 1) + if (DFS_OSCILLATOR_MODE == "AVE_FREQ_LOCK") + clkfx_out_avg <= #(period_fxavg) ~clkfx_out_avg; + +always @(posedge clkin_ps or posedge clkin_lost_out or posedge rst_in) + if (rst_in == 1) + clkfx_out_ph = 0; + else if (clkin_lost_out == 1'b1 ) begin + if (locked_out == 1) + @(negedge rst_reg[2]); + end + else + if (lock_out[1] == 1 && DFS_OSCILLATOR_MODE == "PHASE_FREQ_LOCK") begin + if (lock_out[1] == 1 ) begin + clkfx_out_ph = 1'b1; + for (p = 0; p < (numerator * 2 - 1); p = p + 1) begin + #(period_fx); + if (p < remain_fx) + #1; + clkfx_out_ph = !clkfx_out_ph; + end + if (period_fx > (period / 2)) begin + #(period_fx - (period / 2)); + end + end + end + +// +// detect_first_time_locked +// + +always @(posedge locked_out) + if (first_time_locked == 0) + first_time_locked <= 1; + +always @(ps_overflow_out or clkin_lost_out or clkfx_lost_out or + clkfb_lost_out or en_status) + if ( en_status != 1) + do_out_s[3:0] = 4'b0; + else + begin + do_out_s[0] = ps_overflow_out; + do_out_s[1] = clkin_lost_out; + do_out_s[2] = clkfx_lost_out; + do_out_s[3] = clkfb_lost_out; + end + + assign do_out = (do_stat_en == 0) ? do_out_drp1 : do_out_s; + +always @(posedge rst_in or posedge LOCKED) + if (rst_in == 1) + en_status <= 0; + else + en_status <= 1; + +// +// drp process +// + +always @(posedge dclk_in or posedge gsr_in) + if (gsr_in == 1) begin + drp_lock <= 0; + ps_in_drp <= 0; + ps_kick_off_cmd <= 0; + do_out_drp <= 16'b0; + do_out_drp1 <= 16'b0; + do_stat_en <= 1; + drdy_out <= 0; + end + else begin + valid_daddr = addr_is_valid(daddr_in); + if (DEN == 1) begin + if (drp_lock == 1) + $display(" Warning : DEN is high at DCM_ADV instance %m at time %t. Please wait for DRDY signal before next read/write operation through DRP. ", $time); + else begin + drp_lock <= 1; + + if (DWE == 0 && sim_device_type == 1 ) begin + if (daddr_in == `DCM_DEFAULT_STATUS_ADDR) + do_stat_en <= 1; + else begin + do_stat_en <= 0; + if (daddr_in == `DFS_FREQ_MODE_ADDR) + do_out_drp <= dfs_mode_reg; + else if (daddr_in == `DLL_FREQ_MODE_ADDR) + do_out_drp <= dll_mode_reg; + else if (daddr_in == `CLKFX_MULTIPLY_ADDR) + do_out_drp <= clkfx_md_reg; + else if (daddr_in == `CLKIN_DIV_BY2_ADDR) + do_out_drp <= clkin_div2_reg; + else + do_out_drp <= 16'b0; + end + end + + if (DWE == 1) begin + if (valid_daddr) begin + if (daddr_in == `CLKFX_MULTIPLY_ADDR) begin + if (sim_device_type == 1) begin + clkfx_divide_drp <= di_in[7:0] + 1; + clkfx_multiply_drp <= di_in[15:8] + 1; + clkfx_md_reg <= di_in; + end + else + clkfx_multiply_drp <= di_in[4:0] + 1; + end + else if (daddr_in == `CLKFX_DIVIDE_ADDR && sim_device_type == 0) begin + clkfx_divide_drp <= di_in[4:0] + 1; + end + else if (daddr_in == `PHASE_SHIFT_ADDR) begin + ps_drp <= di_in[10:0]; + end + else if (daddr_in == `PHASE_SHIFT_KICK_OFF_ADDR) begin + if (ps_kick_off_cmd == 0) begin + ps_kick_off_cmd <= 1; + ps_in_drp <= ps_drp; + if (ps_in < ps_drp) + inc_dec <= 1; + else if (ps_in > ps_drp) + inc_dec <= 0; + end + end + else if (daddr_in == `DFS_FREQ_MODE_ADDR && sim_device_type == 1) begin + dfs_mode_reg <= di_in; + end + else if (daddr_in == `DLL_FREQ_MODE_ADDR && sim_device_type == 1) begin + dll_mode_reg <= di_in; + end + else if (daddr_in == `CLKIN_DIV_BY2_ADDR && sim_device_type == 1) begin + clkin_div2_reg <= di_in; + end + else + $display(" Warning : Address DADDR=%b is unsupported at DCM_ADV instance %m at time %t. ", daddr_in, $time); + + end + end + end + end + + if ( drp_lock == 1) + drp_lock1 <= 1; + + if ( drp_lock1 == 1) begin + drp_lock <= 0; + drp_lock1 <= 0; + drdy_out <= 1; + do_out_drp1 <= do_out_drp; + do_out_drp <= 16'b0; + end + + if (drdy_out == 1) begin + drdy_out <= 0; + do_out_drp1 <= 16'b0; + end + if (ps_drp_lock_tmp1 == 1) begin + if (ps_kick_off_cmd == 1) + ps_kick_off_cmd <= 0; + end + end + + always @(negedge ps_drp_lock) begin + @(posedge dclk_in) + ps_drp_lock_tmp1 <= 1; + @(posedge dclk_in) + ps_drp_lock_tmp1 <= 0; + end + +function addr_is_valid; +input [6:0] daddr_funcin; +begin + addr_is_valid = 1; + for (i=0; i<=6; i=i+1) + if ( daddr_funcin[i] != 0 && daddr_funcin[i] != 1) + addr_is_valid = 0; +end +endfunction + +// end process drp; + +// +// drive_drdy_out process +// + +//always @(drp_lock or dclk_in or gsr_in) +// @(negedge drp_lock) +// @(posedge dclk_in) begin +// if (gsr_in == 0) +// drdy_out = 1; +// @(posedge dclk_in) +// drdy_out = 0; +// end + +// +// generate all output signal +// + +always @(rst_in) +if (rst_in) begin + assign CLK0 = 0; + assign CLK90 = 0; + assign CLK180 = 0; + assign CLK270 = 0; + assign CLK2X = 0; + assign CLK2X180 =0; + assign CLKDV = 0; + assign CLKFX = 0; + assign CLKFX180 = 0; +end +else begin + deassign CLK0; + deassign CLK90; + deassign CLK180; + deassign CLK270; + deassign CLK2X; + deassign CLK2X180; + deassign CLKDV; + deassign CLKFX; + deassign CLKFX180; +end + +always @(clk0_out) begin + CLK0 <= #(clkout_delay) clk0_out; + CLK90 <= #(clkout_delay + period / 4) clk0_out; + CLK180 <= #(clkout_delay + period / 2) clk0_out; + CLK270 <= #(clkout_delay + period / 4) ~clk0_out; + end + +always @(clk2x_out) begin + CLK2X <= #(clkout_delay) clk2x_out; + CLK2X180 <= #(clkout_delay) ~clk2x_out ; +end + + +always @(clkdv_out) + CLKDV <= #(clkout_delay) clkdv_out; + +always @(clkfx_out ) + CLKFX <= #(clkout_delay) clkfx_out; + +always @( clkfx_out or first_time_locked or locked_out) begin + if ( ~first_time_locked) + CLKFX180 <= 0; + else + CLKFX180 <= #(clkout_delay) ~clkfx_out; +end + + +endmodule + +////////////////////////////////////////////////////// + +module dcm_adv_clock_divide_by_2 (clock, clock_type, clock_out, rst); +input clock; +input clock_type; +input rst; +output clock_out; + +reg clock_out; +reg clock_div2; +reg [2:0] rst_reg; +wire clk_src; + +initial begin + clock_out = 1'b0; + clock_div2 = 1'b0; +end + +always @(posedge clock) + clock_div2 <= ~clock_div2; + +always @(posedge clock) begin + rst_reg[0] <= rst; + rst_reg[1] <= rst_reg[0] & rst; + rst_reg[2] <= rst_reg[1] & rst_reg[0] & rst; +end + +assign clk_src = (clock_type) ? clock_div2 : clock; + +always @(clk_src or rst or rst_reg) + if (rst == 1'b0) + clock_out = clk_src; + else if (rst == 1'b1) begin + clock_out = 1'b0; + @(negedge rst_reg[2]); + if (clk_src == 1'b1) + @(negedge clk_src); + end + + +endmodule + +module dcm_adv_maximum_period_check (clock, rst); +parameter clock_name = ""; +parameter maximum_period = 0; +input clock; +input rst; + +time clock_edge; +time clock_period; + +initial begin + clock_edge = 0; + clock_period = 0; +end + +always @(posedge clock ) +begin + clock_edge <= $time; + clock_period <= $time - clock_edge; + if (clock_period > maximum_period && rst == 0 ) begin + $display(" Warning : Input clock period of, %1.3f ns, on the %s port of instance %m exceeds allowed value of %1.3f ns at simulation time %1.3f ns.", clock_period/1000.0, clock_name, maximum_period/1000.0, $time/1000.0); + end +end +endmodule + +module dcm_adv_clock_lost (clock, enable, lost, rst); +input clock; +input enable; +input rst; +output lost; + +reg lost_r, lost_f, lost; + +time clock_edge, clock_edge_neg; +time period, period_neg, period_tmp, period_neg_tmp, period_tmp_win, period_neg_tmp_win; +time period_chk_win; +integer clock_low, clock_high; +integer clock_posedge, clock_negedge; +integer clock_second_pos, clock_second_neg; + +initial begin + clock_edge = 0; + clock_edge_neg = 0; + clock_high = 0; + clock_low = 0; + lost_r = 0; + lost_f = 0; + period = 0; + period_neg = 0; + period_tmp = 0; + period_tmp_win = 0; + period_neg_tmp = 0; + period_neg_tmp_win = 0; + period_chk_win = 0; + clock_posedge = 0; + clock_negedge = 0; + clock_second_pos = 0; + clock_second_neg = 0; +end + +always @(posedge clock or negedge clock or posedge rst) + if (rst) begin + clock_second_pos <= 0; + clock_second_neg <= 0; + end + else if (clock) + clock_second_pos <= 1; + else if (~clock) + clock_second_neg <= 1; + +always @(posedge clock or posedge rst) + if (rst) begin + period <= 0; + end + else begin + clock_edge <= $time; + period_tmp = $time - clock_edge; + if (period != 0 && (period_tmp <= period_tmp_win)) + period <= period_tmp; + else if (period != 0 && (period_tmp > period_tmp_win)) + period <= 0; + else if ((period == 0) && (clock_edge != 0) && clock_second_pos == 1) + period <= period_tmp; + end + +always @(period) begin + period_tmp_win = 1.5 * period; + period_chk_win = (period * 9.1) / 10; +end + +always @(negedge clock or posedge rst) + if (rst) + period_neg <= 0; + else begin + clock_edge_neg <= $time; + period_neg_tmp = $time - clock_edge_neg; + if (period_neg != 0 && ( period_neg_tmp <= period_neg_tmp_win)) + period_neg <= period_neg_tmp; + else if (period_neg != 0 && (period_neg_tmp > period_neg_tmp_win)) + period_neg <= 0; + else if ((period_neg == 0) && (clock_edge_neg != 0) && clock_second_neg == 1) + period_neg <= period_neg_tmp; + end + +always @(period_neg) + period_neg_tmp_win = 1.5 * period_neg; + +always @(posedge clock or posedge rst) + if (rst) + lost_r <= 0; + else + if (enable == 1 && clock_second_pos == 1) begin + #1; + if ( period != 0) + lost_r <= 0; + #(period_chk_win) + if ((clock_low != 1) && (clock_posedge != 1) && rst == 0 ) + lost_r <= 1; + end + +always @(negedge clock or posedge rst) + if (rst==1) begin + lost_f <= 0; + end + else begin + if (enable == 1 && clock_second_neg == 1) begin + if ( period != 0) + lost_f <= 0; + #(period_chk_win) + if ((clock_high != 1) && (clock_negedge != 1) && rst == 0 && (period <= period_neg)) + lost_f <= 1; + end + end + +always @( lost_r or lost_f or enable) + if (enable == 1) + lost = lost_r | lost_f; + else + lost = 0; + +always @(posedge clock or negedge clock or posedge rst) + if (rst==1) begin + clock_low <= 0; + clock_high <= 0; + clock_posedge <= 0; + clock_negedge <= 0; + end + else + if (clock ==1) begin + clock_low <= 0; + clock_high <= 1; + clock_posedge <= 0; + clock_negedge <= 1; + end + else if (clock == 0) begin + clock_low <= 1; + clock_high <= 0; + clock_posedge <= 1; + clock_negedge <= 0; + end + +endmodule diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/DCM_BASE.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/DCM_BASE.v new file mode 100644 index 0000000..999735f --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/DCM_BASE.v @@ -0,0 +1,137 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/virtex4/DCM_BASE.v,v 1.12 2007/02/13 01:01:27 yanx Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Digital Clock Manager with Basic Features +// /___/ /\ Filename : DCM_BASE.v +// \ \ / \ Timestamp : Thu Mar 25 16:43:43 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 07/25/05 - Set CLKIN_PERIOD default to 10.0ns to (CR 213190). +// 02/09/07 - Add parameter DCM_AUTOCALIBRATION (CR 433184). +// End Revision + +`timescale 1 ps / 1 ps + +module DCM_BASE ( + CLK0, + CLK180, + CLK270, + CLK2X, + CLK2X180, + CLK90, + CLKDV, + CLKFX, + CLKFX180, + LOCKED, + CLKFB, + CLKIN, + RST +); + +parameter real CLKDV_DIVIDE = 2.0; +parameter integer CLKFX_DIVIDE = 1; +parameter integer CLKFX_MULTIPLY = 4; +parameter CLKIN_DIVIDE_BY_2 = "FALSE"; +parameter real CLKIN_PERIOD = 10.0; +parameter CLKOUT_PHASE_SHIFT = "NONE"; +parameter CLK_FEEDBACK = "1X"; +parameter DCM_AUTOCALIBRATION = "TRUE"; +parameter DCM_PERFORMANCE_MODE = "MAX_SPEED"; +parameter DESKEW_ADJUST = "SYSTEM_SYNCHRONOUS"; +parameter DFS_FREQUENCY_MODE = "LOW"; +parameter DLL_FREQUENCY_MODE = "LOW"; +parameter DUTY_CYCLE_CORRECTION = "TRUE"; +parameter FACTORY_JF = 16'hF0F0; +parameter integer PHASE_SHIFT = 0; +parameter STARTUP_WAIT = "FALSE"; + + +output CLK0; +output CLK180; +output CLK270; +output CLK2X180; +output CLK2X; +output CLK90; +output CLKDV; +output CLKFX180; +output CLKFX; +output LOCKED; + +input CLKFB; +input CLKIN; +input RST; + +wire OPEN_DRDY; +wire OPEN_PSDONE; +wire [15:0] OPEN_DO; + +initial +begin + if (CLKOUT_PHASE_SHIFT != "NONE" && CLKOUT_PHASE_SHIFT != "FIXED") + begin + $display(" Attribute Syntax Error :The attribute CLKOUT_PHASE_SHIFT on DCM_BASE instance %m is set to %s. Legal values for this attribute is NONE or FIXED", CLKOUT_PHASE_SHIFT); + $finish; + end + + if (CLK_FEEDBACK != "NONE" && CLK_FEEDBACK != "1X") + begin + $display("Attribute Syntax Error : The attribute CLK_FEEDBACK on DCM_BASE instance %m is set to %s. Legal values for this attribute are NONE or 1X.", CLK_FEEDBACK); + $finish; + end + +end + +DCM_ADV dcm_adv_1 ( + .CLK0 (CLK0), + .CLK180 (CLK180), + .CLK270 (CLK270), + .CLK2X (CLK2X), + .CLK2X180 (CLK2X180), + .CLK90 (CLK90), + .CLKDV (CLKDV), + .CLKFB (CLKFB), + .CLKFX (CLKFX), + .CLKFX180 (CLKFX180), + .CLKIN (CLKIN), + .DO (OPEN_DO), + .DRDY (OPEN_DRDY), + .LOCKED (LOCKED), + .DADDR (7'b0000000), + .DCLK (1'b0), + .DEN (1'b0), + .DI (16'h0000), + .DWE (1'b0), + .PSDONE (OPEN_PSDONE), + .PSCLK (1'b0), + .PSEN (1'b0), + .PSINCDEC (1'b0), + .RST (RST) +); + +defparam dcm_adv_1.CLKDV_DIVIDE = CLKDV_DIVIDE; +defparam dcm_adv_1.CLKFX_DIVIDE = CLKFX_DIVIDE; +defparam dcm_adv_1.CLKFX_MULTIPLY = CLKFX_MULTIPLY; +defparam dcm_adv_1.CLKIN_DIVIDE_BY_2 = CLKIN_DIVIDE_BY_2; +defparam dcm_adv_1.CLKIN_PERIOD = CLKIN_PERIOD; +defparam dcm_adv_1.CLKOUT_PHASE_SHIFT = CLKOUT_PHASE_SHIFT; +defparam dcm_adv_1.CLK_FEEDBACK = CLK_FEEDBACK; +defparam dcm_adv_1.DCM_AUTOCALIBRATION = DCM_AUTOCALIBRATION; +defparam dcm_adv_1.DCM_PERFORMANCE_MODE = DCM_PERFORMANCE_MODE; +defparam dcm_adv_1.DESKEW_ADJUST = DESKEW_ADJUST; +defparam dcm_adv_1.DFS_FREQUENCY_MODE = DFS_FREQUENCY_MODE; +defparam dcm_adv_1.DLL_FREQUENCY_MODE = DLL_FREQUENCY_MODE; +defparam dcm_adv_1.DUTY_CYCLE_CORRECTION = DUTY_CYCLE_CORRECTION; +defparam dcm_adv_1.FACTORY_JF = FACTORY_JF; +defparam dcm_adv_1.PHASE_SHIFT = PHASE_SHIFT; +defparam dcm_adv_1.STARTUP_WAIT = STARTUP_WAIT; + +endmodule diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/DCM_CLKGEN.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/DCM_CLKGEN.v new file mode 100644 index 0000000..9015282 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/DCM_CLKGEN.v @@ -0,0 +1,737 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/stan/DCM_CLKGEN.v,v 1.15 2010/01/15 20:44:32 yanx Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Function Simulation Library Component +// / / Digital Clock Manager +// /___/ /\ Filename : DCM_CLKGEN.v +// \ \ / \ Timestamp : +// \___\/\___\ +// +// Revision: +// 01/08/06 - Initial version. +// 07/25/08 - Add attributes SPREAD_SPECTRUM, CLKIN_PERIOD. Remove CLK_SOURCE. +// 09/02/08 - Add STATUS[2:1] pin +// 09/23/08 - Change CLKFX_MULTIPLY range to 2 to 256 (CR490109). +// 11/20/08 - Update timeing check. +// 04/10/09 - Progdata pin loads M-1 and D-1. (CR518158) +// 05/15/09 - Remove DFS_BANDWIDTH & PROG_MD_BANDWIDTH attributes (CR521993) +// 06/18/09 - change SPREAD_SPECTRUM values (CR525436) +// 09/30/09 - Add spread sprectrum function. +// 11/20/09 - Add STATUS[7:0] pin to simprim. (CR538362) +// End Revision + + +`timescale 1 ps / 1 ps + +module DCM_CLKGEN ( + CLKFX, + CLKFX180, + CLKFXDV, + LOCKED, + PROGDONE, + STATUS, + CLKIN, + FREEZEDCM, + PROGCLK, + PROGDATA, + PROGEN, + RST +); + parameter SPREAD_SPECTRUM = "NONE"; + parameter STARTUP_WAIT = "FALSE"; + parameter integer CLKFXDV_DIVIDE = 2; + parameter integer CLKFX_DIVIDE = 1; + parameter integer CLKFX_MULTIPLY = 4; + parameter real CLKFX_MD_MAX = 0.0; + parameter real CLKIN_PERIOD = 0.0; + + + output CLKFX180; + output CLKFX; + output CLKFXDV; + output LOCKED; + output PROGDONE; + output [2:1] STATUS; + + input CLKIN; + input FREEZEDCM; + input PROGCLK; + input PROGDATA; + input PROGEN; + input RST; + + localparam OSC_P2 = 250; + + reg clkfx_out = 0; + reg clkfx180_out = 0; + reg clkfxdv_out = 0; + wire clkfx_out1; + wire clkfx180_out1; + wire clkfxdv_out1; + reg rst_tmp1 = 0; + reg rst_tmp2 = 0; + reg [2:0] rst_reg = 3'b000; + reg rst_prog = 0; + reg locked_out = 0; + reg locked_out_out_u = 0; + reg progdone_out = 0; + reg progdone_out_u = 0; + reg lk_pd = 0; + reg lk_pd1 = 0; + reg lk_pd0 = 0; + reg clkfx_clk = 0; + reg clkin_ls_out = 0; + reg clkfx_ls_out = 0; + reg clk_osc = 0; + reg clkin_p = 0; + reg clkfx_p = 0; + reg [9:0] pg_sf_reg; + reg [7:0] pg_m_reg; + reg [7:0] pg_d_reg; + + integer clkin_ls_val = 0; + integer clkfx_ls_val = 0; + integer clkin_ls_cnt = 0; + integer clkfx_ls_cnt = 0; + integer clkin_pd_init = 1000 * CLKIN_PERIOD; + integer lk_cnt = 0; + integer go_cmd = 0; + integer dcm_en_prog = 0; + integer pg_cnt = 0; + integer bit0_flag = 0; + integer first_time = 1; + integer attr_err_flag = 0; + integer period_sample = 0; + + integer clkdv_cnt = 0; + integer fx_m = CLKFX_MULTIPLY; + integer fx_mt = CLKFX_MULTIPLY; + integer fx_d = CLKFX_DIVIDE; + integer fx_dt = CLKFX_DIVIDE; + real fx_n, fx_o; + real clkfx_md_ratio; + time clkin_edge = 0; + time clkin_pd = 0; + time clkin_pd1 = 0; + time lk_delay = 0; + integer spa; + integer fx_sn = 1024; + integer fx_sn1 = 512; + integer fx_sn2 = 512; + integer fx_sn11 = 256; + integer fx_sn12 = 256; + integer fx_sn21 = 256; + integer fx_sn22 = 256; + integer spju = 0, spd = 0; + real sps = 0.0; + real spst = 0.0; + real spst_tmp = 0.0; + real spst_tmp1 = 0.0; + reg spse = 0; + reg spse0 = 0; + reg spse1 = 0; + integer pd_fx = 0; + integer pd_fx_i = 0; + integer pdhf_fx = 0; + integer pdhf_fx1 = 0; + integer pdh_fx = 0; + integer pdh_fx_t = 0; + real pdh_fx_r = 0.0; + integer pdhfh_fx = 0; + integer pdhfh_fx_t = 0; + integer pdhfh_fx1 = 0; + integer rm_fx = 0; + integer rmh_fx = 0; + integer fxdv_div1; + integer fxdv_div_half; + integer rst_flag = 0; + time rst_pulse_wid = 0; + time rst_pos_edge = 0; + + wire clkin_in; + wire freezedcm_in; + wire progclk_in; + wire progen_in; + wire progdata_in; + wire rst_in; + wire locked_out_out; + wire rst_ms; + wire locked_out_ms; + wire locked_out_ms1; + reg locked_out_ms2 = 0; + wire clkfx_ms_clk; + + reg notifier; + + wire delay_CLKIN; + wire delay_FREEZEDCM; + wire delay_PROGCLK; + wire delay_PROGDATA; + wire delay_PROGEN; + + initial begin + attr_err_flag = 0; + + case (CLKFXDV_DIVIDE) + 2 : ; + 4 : ; + 8 : ; + 16 : ; + 32 : ; + default : begin + $display("Attribute Syntax Error : The Attribute CLKFXDV_DIVIDE on DCM_CLKGEN instance %m is set to %d. Legal values for this attribute are 2, 4, 8, 16, or 32.", CLKFXDV_DIVIDE); + attr_err_flag = 1; + end + endcase + + if (SPREAD_SPECTRUM == "NONE") begin + if ((CLKFX_DIVIDE < 1) || (CLKFX_DIVIDE > 256)) begin + $display("Attribute Syntax Error : The attribute CLKFX_DIVIDE on DCM_CLKGEN instance %m is set to %d. Legal values for this attribute are 1 ... 256.", CLKFX_DIVIDE); + attr_err_flag = 1; + end + end + else begin + if ((CLKFX_DIVIDE < 1) || (CLKFX_DIVIDE > 4)) begin + $display("Attribute Syntax Error : The attribute CLKFX_DIVIDE on DCM_CLKGEN instance %m is set to %d. Legal values for this attribute are 1 ... 4 in spread spectrum mode.", CLKFX_DIVIDE); + attr_err_flag = 1; + end + end + + clkfx_md_ratio = CLKFX_MULTIPLY / CLKFX_DIVIDE; + if (CLKFX_MD_MAX > 0.0 && clkfx_md_ratio > CLKFX_MD_MAX) begin + $display("Attribute Syntax Error : The ratio of CLKFX_MULTIPLY / CLKFX_DIVIDE is %f on DCM_CLKGEN instance %m. It is over the value %f of attribute CLKFX_MD_MAX.", clkfx_md_ratio, CLKFX_MD_MAX); + attr_err_flag = 1; + end + + if (SPREAD_SPECTRUM == "NONE") begin + if ((CLKFX_MULTIPLY < 2) || (CLKFX_MULTIPLY > 256)) begin + $display("Attribute Syntax Error : The attribute CLKFX_MULTIPLY on DCM_CLKGEN instance %m is set to %d. Legal values for this attribute are 2 ... 256.", CLKFX_MULTIPLY); + attr_err_flag = 1; + end + end + else begin + if ((CLKFX_MULTIPLY < 2) || (CLKFX_MULTIPLY > 32)) begin + $display("Attribute Syntax Error : The attribute CLKFX_MULTIPLY on DCM_CLKGEN instance %m is set to %d. Legal values for this attribute are 2 ... 32 in spread spectrum mode.", CLKFX_MULTIPLY); + attr_err_flag = 1; + end + end + + case (SPREAD_SPECTRUM) + "NONE" : spa = 0; + "CENTER_HIGH_SPREAD" : spa = 1; + "CENTER_LOW_SPREAD" : spa = 2; + "VIDEO_LINK_M0" : spa = 3; + "VIDEO_LINK_M1" : spa = 4; + "VIDEO_LINK_M2" : spa = 5; + default : begin + $display("Attribute Syntax Error : The Attribute SPREAD_SPECTRUM on DCM_CLKGEN instance %m is set to %s. Legal values for this attribute are NONE, CENTER_HIGH_SPREAD, CENTER_LOW_SPREAD, VIDEO_LINK_M0, VIDEO_LINK_M1, or VIDEO_LINK_M2.", SPREAD_SPECTRUM); + end + endcase + + + case (STARTUP_WAIT) + "FALSE" : ; + "TRUE" : ; + default : begin + $display("Attribute Syntax Error : The Attribute STARTUP_WAIT on DCM_CLKGEN instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", STARTUP_WAIT); + attr_err_flag = 1; + end + endcase + + #1; + if ($realtime == 0) begin + $display ("Simulator Resolution Error : Simulator resolution is set to a value greater than 1 ps."); + $display ("In order to simulate the DCM_CLKGEN, the simulator resolution must be set to 1ps."); + attr_err_flag = 1; + end + + if (attr_err_flag == 1) begin + #1; + $finish; + end + + end + + assign STATUS[1] = clkin_ls_out; + assign STATUS[2] = clkfx_ls_out; + assign clkin_in = CLKIN; + assign freezedcm_in = FREEZEDCM; + assign progclk_in = PROGCLK; + assign progen_in = PROGEN; + assign progdata_in = PROGDATA; + assign rst_in = RST; + assign LOCKED = locked_out_out_u; + assign PROGDONE = progdone_out_u; + + always @(locked_out_out) + locked_out_out_u <= #100 locked_out_out; + + always @(progdone_out) + progdone_out_u <= #100 progdone_out; + + + assign CLKFX = clkfx_out1; + assign CLKFX180 = clkfx180_out1; + assign CLKFXDV = clkfxdv_out1; + + initial begin + fxdv_div1 = CLKFXDV_DIVIDE - 1; + fxdv_div_half = CLKFXDV_DIVIDE/2; + pg_sf_reg = 10'b0; + pg_m_reg = fx_m - 1; + pg_d_reg = fx_d - 1; + end + + +// generate master reset signal +// + +// assign rst_ms = rst_in | rst_prog; + assign rst_ms = rst_in; + + always @(posedge clkin_in) begin + rst_reg[0] <= rst_in; + rst_reg[1] <= rst_reg[0] & rst_in; + rst_reg[2] <= rst_reg[1] & rst_reg[0] & rst_in; + end + + always @(rst_in) begin + if (rst_in == 1) + rst_flag <= #1 0; + + rst_tmp1 = rst_in; + if (rst_tmp1 == 0 && rst_tmp2 == 1) begin + if ((rst_reg[2] & rst_reg[1] & rst_reg[0]) == 0) begin + rst_flag = 1; + $display("Input Error : RST on DCM_CLKGEN instance %m at time %t must be asserted for 3 CLKIN clock cycles.", $time); + end + end + rst_tmp2 = rst_tmp1; + end + + +// RST less than 3 cycles, lock = x + + assign locked_out_out = (rst_flag == 1) ? 1'bx : locked_out_ms1; + + +// +// CLKIN period calculation +// + + always @(posedge clkin_in or posedge rst_in) + if (rst_in == 1) begin + clkin_pd <= clkin_pd_init; + clkin_pd1 <= clkin_pd_init; + clkin_edge <= 0; + period_sample <= 0; + end + else begin + if ( freezedcm_in == 0) begin + clkin_edge <= $time; + if (clkin_edge != 0) begin + clkin_pd1 <= clkin_pd; + clkin_pd <= $time - clkin_edge; + period_sample <= 1; + end + end + end + + always @(negedge clkin_in or posedge rst_in) + if (rst_in == 1) begin + lk_cnt <= 0; + lk_pd0 <= 0; + end + else begin + if (lk_pd0 == 0) begin + if (freezedcm_in == 0) begin + lk_cnt <= lk_cnt + 1; + if (lk_cnt >= 14) begin + lk_pd0 <= 1; + + end + end + else begin + if (clkin_pd == clkin_pd1 && period_sample == 1) + lk_pd0 <= 1; + end + end + end + +// +// generate lock signal +// + + always @(posedge lk_pd0 or posedge dcm_en_prog or posedge rst_ms) + if (rst_ms == 1) begin + locked_out <= 0; + lk_pd1 <= 0; + lk_pd <= 0; + end + else begin + locked_out <= #(lk_delay) lk_pd0; + lk_pd1 <= #1 lk_pd0; + lk_pd <= #2 lk_pd0; + end + + + assign locked_out_ms = locked_out; + + assign locked_out_ms1 = (spa == 0 || (spa >= 3 && spa <= 5 && spse == 0)) ? locked_out : 0; + +// +// generate fx clk from CLKIN period +// + + always @(lk_pd0 or clkin_pd or fx_d or fx_m) begin + lk_delay = (clkin_pd / 2) - 1; + if (lk_pd0 == 1 ) begin + pd_fx = (clkin_pd * fx_d) / fx_m; + if (spse0 == 0) + pd_fx_i = pd_fx; + pdhf_fx = pd_fx / 2; + pdhf_fx1 = pdhf_fx - 1; + rm_fx = pd_fx - pdhf_fx; + clkin_ls_val = (clkin_pd * 2) / 500; + clkfx_ls_val = (pd_fx * 2) / 500; + fx_sn = (fx_m * 1024) / fx_d; + fx_sn1 = fx_sn / 2; + fx_sn2 = fx_sn - fx_sn1; + fx_sn11 = fx_sn1 /2; + fx_sn12 = fx_sn1 - fx_sn11; + fx_sn21 = fx_sn2 / 2; + fx_sn22 = fx_sn1 + fx_sn21; + if (spa == 1) begin + if (fx_d == 1) + sps = 200.0 / fx_sn; + else if (fx_d == 2) + sps = 125.0 / fx_sn; + else if (fx_d == 3) + sps = 100.0 / fx_sn; + else if (fx_d == 4) + sps = 75.0 / fx_sn; + end + else if (spa == 2) begin + if (fx_d == 1) + sps = 125.0 / fx_sn; + else if (fx_d == 2) + sps = 75.0 / fx_sn; + else if (fx_d == 3 ) + sps = 65.0 / fx_sn; + else if (fx_d == 4) + sps = 60.0 / fx_sn; + end + else if (spa == 3) + sps = 5.4 / fx_m; + else if (spa == 4) + sps = 1.1 / fx_m; + else if (spa == 5) + sps = 0.3 / fx_m; + end + end + +// always @(negedge clkfx_clk or rst_ms or rst_prog or lk_pd1) + always @(negedge clkfx_clk or rst_ms or lk_pd1 or lk_pd or posedge spse1 ) + if (rst_ms == 1 || lk_pd1 == 0 ) begin + spju = 0; + spst = 0; + pdh_fx = pd_fx; + pdh_fx_t = pd_fx; + pdh_fx_r = pd_fx; + pdhfh_fx = pd_fx / 2; + pdhfh_fx_t = pd_fx / 2; + pdhfh_fx1 = pdhfh_fx - 1; + rmh_fx = pd_fx - pdhfh_fx; + end + else if (spse1 == 1) begin + pdh_fx = pd_fx_i; + pdh_fx_t = pd_fx_i; + pdh_fx_r = pd_fx_i; + pdhfh_fx = pd_fx_i / 2; + pdhfh_fx_t = pd_fx_i / 2; + pdhfh_fx1 = pdhfh_fx - 1; + rmh_fx = pd_fx_i - pdhfh_fx; + spst_tmp = 0.0; + spst = 0.0; + spst_tmp1 = 0.0; + end + else begin + if (lk_pd1 == 1) begin + if (spa == 1 || spa == 2) begin + if (spju >= fx_sn) + spju <= 0; + else + spju <= spju + 1; + + if (spju == 0 || spju == fx_sn1) begin + spst <= 0; + pdh_fx_t = pd_fx; + end + else if ((spju > 0 && spju <= fx_sn11) || (spju > fx_sn22 && spju <= fx_sn)) begin + spst <= spst + sps; + pdh_fx_t = pd_fx + spst; + end + else if (spju > fx_sn11 && spju <= fx_sn22) begin + spst <= spst - sps; + pdh_fx_t = pd_fx + spst; + end + end + else if (spa >= 3 && spa <= 5 && spse == 1) begin + spst_tmp = spst + sps; + if (spst_tmp >= 1.0 ) begin + spst_tmp1 = $rtoi(spst_tmp); + spst <= spst_tmp - spst_tmp1; + end + else begin + spst_tmp1 = 0.0; + spst <= spst_tmp; + + end + if (spd == 1) + pdh_fx_t = pdh_fx - spst_tmp1; + else + pdh_fx_t = pdh_fx + spst_tmp1; + end + + if (spa != 0) begin + pdhfh_fx_t = pdh_fx_t / 2; + pdh_fx <= pdh_fx_t; + pdhfh_fx <= pdhfh_fx_t; + pdhfh_fx1 <= pdhfh_fx_t - 1; + rmh_fx <= pdh_fx_t - pdhfh_fx_t; + end + end + end + + always @(clkfx_clk or posedge locked_out_ms or posedge rst_ms) + if (rst_ms == 1) begin + clkfx_clk = 0; + first_time <= 1; + end + else begin + if (locked_out_ms == 1) begin + if (first_time == 1) begin + clkfx_clk <= 1; + first_time <= 0; + end + else if (clkfx_clk == 1) begin + if (spa == 0 || (spse == 0 && spa >= 3 && spa <= 5)) + clkfx_clk <= #(pdhf_fx) 0; + else + clkfx_clk <= #(pdhfh_fx) 0; + end + else if (clkfx_clk == 0) begin + if (spa == 0 || (spse == 0 && spa >= 3 && spa <= 5)) + clkfx_clk <= #(rm_fx) 1; + else + clkfx_clk <= #(rmh_fx) 1; + end + end + end + + + always @(clk_osc or rst_ms) + if (rst_ms) + clk_osc <= 0; + else + clk_osc <= #OSC_P2 ~clk_osc; + + always @(posedge clkin_in or negedge clkin_in) begin + clkin_p <= 1; + clkin_p <= #100 0; + end + + always @(posedge clkfx_out or negedge clkfx_out) begin + clkfx_p <= 1; + clkfx_p <= #100 0; + end + + always @(posedge clk_osc or posedge rst_ms or posedge clkin_p) + if (rst_ms == 1 || clkin_p == 1) begin + clkin_ls_out <= 0; + clkin_ls_cnt <= 0; + end + else if (locked_out && freezedcm_in == 0) begin + if (clkin_ls_cnt < clkin_ls_val) begin + clkin_ls_cnt <= clkin_ls_cnt + 1; + clkin_ls_out <= 0; + end + else + clkin_ls_out <= 1; + end + + always @(posedge clk_osc or posedge rst_ms or posedge clkfx_p) + if (rst_ms == 1 || clkfx_p == 1) begin + clkfx_ls_out <= 0; + clkfx_ls_cnt <= 0; + end + else if (locked_out && spa == 0) begin + if (clkfx_ls_cnt < clkfx_ls_val) begin + clkfx_ls_cnt <= clkfx_ls_cnt + 1; + clkfx_ls_out <= 0; + end + else + clkfx_ls_out <= 1; + end + +// +// generate all output signal +// + + assign clkfx_ms_clk = clkfx_clk; + + always @(locked_out_ms) + locked_out_ms2 <= #1 locked_out_ms; + + assign clkfx_out1 = (locked_out_ms2) ? clkfx_out : 0; + assign clkfx180_out1 = (locked_out_ms2) ? clkfx180_out : 0; + assign clkfxdv_out1 = (locked_out_ms2) ? clkfxdv_out : 0; + + always @(posedge clkfx_ms_clk or negedge clkfx_ms_clk or posedge rst_ms) + if (rst_ms == 1) begin + clkfx_out = 0; + clkfx180_out = 0; + end + else + if (locked_out_ms == 1) begin + clkfx_out <= clkfx_ms_clk; + clkfx180_out <= !clkfx_ms_clk; + end + + + always @(posedge clkfx_ms_clk or posedge rst_ms) + if (rst_ms == 1) begin + clkfxdv_out = 0; + clkdv_cnt = 0; + end + else + begin + if (clkdv_cnt >= fxdv_div1) + clkdv_cnt <= 0; + else + clkdv_cnt <= clkdv_cnt + 1; + + if (clkdv_cnt < fxdv_div_half ) + clkfxdv_out <= 1; + else + clkfxdv_out <= 0; + end + + +// +//SPI for M/D dynamic change +// + + always @(posedge progclk_in or posedge rst_in) + if (rst_in == 1) begin + progdone_out <= 1; + bit0_flag <= 0; + pg_cnt <= 0; + end + else begin + if (progen_in == 1) begin + if (bit0_flag == 0) begin + if (progdata_in == 0) begin + go_cmd <= 1; + end + else begin + progdone_out <= 0; + bit0_flag <= 1; + pg_cnt <= 1; + pg_sf_reg[9] <= progdata_in; + pg_sf_reg[8:0] <= 9'b0; + end + end + else begin + progdone_out <= 0; + if (pg_cnt >= 10) begin + $display("Warning : PROGDATA over 10 bit limit on X_DCMCLK_GEN on instance %m at time %t.", $time); + end + pg_sf_reg[8:0] <= pg_sf_reg[9:1]; + pg_sf_reg[9] <= progdata_in; + pg_cnt <= pg_cnt + 1; + end + end + else begin + bit0_flag <= 0; + pg_cnt <= 0; + end + + if (dcm_en_prog == 1) + progdone_out <= 1; + + if (go_cmd ==1) + go_cmd <= 0; + end + + + always @(negedge progen_in) + if ( pg_sf_reg[1:0] == 2'b11) + pg_m_reg = pg_sf_reg[9:2]; + else if ( pg_sf_reg[1:0] == 2'b01) + pg_d_reg = pg_sf_reg[9:2]; + + + always @(posedge go_cmd) begin + @(negedge clkfx_out) begin +// rst_prog <= #pdhf_fx1 1; +// rst_prog <= #(pdhf_fx1 + pdhf_fx1) 0; + end + @(posedge clkin_in); + @(posedge clkin_in); + @(posedge clkin_in); + @(posedge clkin_in); + if (spa >= 3 && spa <= 5) begin + spse0 <= 1; + end + @(posedge clkin_in) begin + fx_mt = pg_m_reg + 1; + fx_dt = pg_d_reg + 1; + fx_n = fx_mt / fx_dt; + fx_o = fx_m / fx_d; + if (fx_n > fx_o) + spd <= 1; + else if (fx_n < fx_o) + spd <= 0; + + fx_m <= pg_m_reg + 1; + fx_d <= pg_d_reg + 1; + if (spa >= 3 && spa <= 5) begin + if (spse == 0) begin + spse1 <= #1 1; + spse1 <= #2 0; + spse <= #2 1; + end + end + else + spse <= 0; + end + @(posedge clkin_in); + clkfx_md_ratio = fx_m / fx_d; + if (CLKFX_MD_MAX > 0.0 && clkfx_md_ratio > CLKFX_MD_MAX) begin + $display("Error : The CLKFX MULTIPLIER and DIVIDER are programed to %d and %d on DCM_CLKGEN instance %m. The ratio of CLKFX MULTIPLIER / CLKFX DIVIDER is %f. It is over the value %f set by attribute CLKFX_MD_MAX.", fx_m, fx_d, clkfx_md_ratio, CLKFX_MD_MAX); + end + @(posedge clkin_in); + @(posedge clkin_in) + rst_prog <= 0; + @(posedge clkin_in); + @(posedge clkin_in); + @(posedge clkin_in); + @(posedge clkin_in); + @(posedge clkin_in); + @(posedge progclk_in) + dcm_en_prog <= 1; + @(posedge progclk_in) + dcm_en_prog <= 0; + end + + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/DCM_PS.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/DCM_PS.v new file mode 100644 index 0000000..652dc84 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/DCM_PS.v @@ -0,0 +1,140 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/virtex4/DCM_PS.v,v 1.12 2007/02/13 01:01:27 yanx Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Digital Clock Manager with Basic and Phase Shift Features +// /___/ /\ Filename : DCM_PS.v +// \ \ / \ Timestamp : Thu Mar 25 16:43:43 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 07/25/05 - Set CLKIN_PERIOD default to 10.0ns to (CR 213190). +// 03/10/06 - Add parameter type (CR 226003). +// 02/09/07 - Add parameter DCM_AUTOCALIBRATION (CR 433184). +// End Revision + +`timescale 1 ps / 1 ps + +module DCM_PS ( + CLK0, + CLK180, + CLK270, + CLK2X, + CLK2X180, + CLK90, + CLKDV, + CLKFX, + CLKFX180, + DO, + LOCKED, + PSDONE, + CLKFB, + CLKIN, + PSCLK, + PSEN, + PSINCDEC, + RST +); + +parameter real CLKDV_DIVIDE = 2.0; +parameter integer CLKFX_DIVIDE = 1; +parameter integer CLKFX_MULTIPLY = 4; +parameter CLKIN_DIVIDE_BY_2 = "FALSE"; +parameter real CLKIN_PERIOD = 10.0; +parameter CLKOUT_PHASE_SHIFT = "NONE"; +parameter CLK_FEEDBACK = "1X"; +parameter DCM_AUTOCALIBRATION = "TRUE"; +parameter DCM_PERFORMANCE_MODE = "MAX_SPEED"; +parameter DESKEW_ADJUST = "SYSTEM_SYNCHRONOUS"; +parameter DFS_FREQUENCY_MODE = "LOW"; +parameter DLL_FREQUENCY_MODE = "LOW"; +parameter DUTY_CYCLE_CORRECTION = "TRUE"; +parameter FACTORY_JF = 16'hF0F0; +parameter integer PHASE_SHIFT = 0; +parameter STARTUP_WAIT = "FALSE"; + + +output CLK0; +output CLK180; +output CLK270; +output CLK2X180; +output CLK2X; +output CLK90; +output CLKDV; +output CLKFX180; +output CLKFX; +output LOCKED; +output PSDONE; +output [15:0] DO; + +input CLKFB; +input CLKIN; +input PSCLK; +input PSEN; +input PSINCDEC; +input RST; + +wire OPEN_DRDY; + +initial +begin + if (CLK_FEEDBACK != "NONE" && CLK_FEEDBACK != "1X") + begin + $display("Attribute Syntax Error : The attribute CLK_FEEDBACK on DCM_PS instance %m is set to %s. Legal values for this attribute are NONE or 1X.", CLK_FEEDBACK); + $finish; + end + +end + +DCM_ADV dcm_adv_1 ( + .CLK0 (CLK0), + .CLK180 (CLK180), + .CLK270 (CLK270), + .CLK2X (CLK2X), + .CLK2X180 (CLK2X180), + .CLK90 (CLK90), + .CLKDV (CLKDV), + .CLKFB (CLKFB), + .CLKFX (CLKFX), + .CLKFX180 (CLKFX180), + .CLKIN (CLKIN), + .DO (DO), + .DRDY (OPEN_DRDY), + .LOCKED (LOCKED), + .DADDR (7'b0000000), + .DCLK (1'b0), + .DEN (1'b0), + .DI (16'h0000), + .DWE (1'b0), + .PSCLK (PSCLK), + .PSDONE (PSDONE), + .PSEN (PSEN), + .PSINCDEC (PSINCDEC), + .RST (RST) +); + +defparam dcm_adv_1.CLKDV_DIVIDE = CLKDV_DIVIDE; +defparam dcm_adv_1.CLKFX_DIVIDE = CLKFX_DIVIDE; +defparam dcm_adv_1.CLKFX_MULTIPLY = CLKFX_MULTIPLY; +defparam dcm_adv_1.CLKIN_DIVIDE_BY_2 = CLKIN_DIVIDE_BY_2; +defparam dcm_adv_1.CLKIN_PERIOD = CLKIN_PERIOD; +defparam dcm_adv_1.CLKOUT_PHASE_SHIFT = CLKOUT_PHASE_SHIFT; +defparam dcm_adv_1.CLK_FEEDBACK = CLK_FEEDBACK; +defparam dcm_adv_1.DCM_AUTOCALIBRATION = DCM_AUTOCALIBRATION; +defparam dcm_adv_1.DCM_PERFORMANCE_MODE = DCM_PERFORMANCE_MODE; +defparam dcm_adv_1.DESKEW_ADJUST = DESKEW_ADJUST; +defparam dcm_adv_1.DFS_FREQUENCY_MODE = DFS_FREQUENCY_MODE; +defparam dcm_adv_1.DLL_FREQUENCY_MODE = DLL_FREQUENCY_MODE; +defparam dcm_adv_1.DUTY_CYCLE_CORRECTION = DUTY_CYCLE_CORRECTION; +defparam dcm_adv_1.FACTORY_JF = FACTORY_JF; +defparam dcm_adv_1.PHASE_SHIFT = PHASE_SHIFT; +defparam dcm_adv_1.STARTUP_WAIT = STARTUP_WAIT; + +endmodule diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/DCM_SP.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/DCM_SP.v new file mode 100644 index 0000000..28b3612 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/DCM_SP.v @@ -0,0 +1,1327 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/DCM_SP.v,v 1.24 2009/12/04 23:41:27 yanx Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Function Simulation Library Component +// / / Digital Clock Manager +// /___/ /\ Filename : DCM_SP.v +// \ \ / \ Timestamp : +// \___\/\___\ +// +// Revision: +// 02/28/06 - Initial version. +// 05/09/06 - Add clkin_ps_mkup and clkin_ps_mkup_win for phase shifting (CR 229789). +// 06/14/06 - Add clkin_ps_mkup_flag for multiple cycle delays (CR233283). +// 07/21/06 - Change range of variable phase shifting to +/- integer of 20*(Period-3ns). +// Give warning not support initial phase shifting for variable phase shifting. +// (CR 235216). +// 09/22/06 - Add lock_period and lock_fb to clkfb_div block (CR 418722). +// 12/19/06 - Add clkfb_div_en for clkfb2x divider (CR431210). +// 04/06/07 - Enable the clock out in clock low time after reset in model +// clock_divide_by_2 (CR 437471). +// 07/10/07 - Remove modulaton of ps_delay_md for none and fixed delay type (CR441155) +// 08/29/07 - Change delay of lock_fb_dly to 0.75*period, same as verilog (CR447628). +// 01/22/08 - Add () to ps_in * period_in of ps_delay_md calculation (CR466293). +// 02/21/08 - Align clk2x to both clk0 pos and neg edges. (CR467858). +// 03/01/08 - Disable alignment of clkfb and clkin_fb check when ps_lock high (CR468893) +// 03/20/08 - Not check clock lost when negative edge period smaller than positive +// edge period in dcm_sp_clock_lost module (CR469499). +// - always generate clk2x with even duty cycle regardless CLKIN duty cycle.(CR467858). +// 05/13/08 - Change min input clock freq from 1.0Mhz to 0.2Mhz (CR467770) +// 07/16/08 - remove condition for lock_out[0] when 2x feedback (CR476637). +// 04/20/09 - Delay LOCKED (CR518620) +// 12/03/09 - Add STATUS[5]=CLKFX STATUS[7]=CLKIN (CR538362) +// End Revision + + +`timescale 1 ps / 1 ps + +module DCM_SP ( + CLK0, CLK180, CLK270, CLK2X, CLK2X180, CLK90, + CLKDV, CLKFX, CLKFX180, LOCKED, PSDONE, STATUS, + CLKFB, CLKIN, DSSEN, PSCLK, PSEN, PSINCDEC, RST); + +parameter real CLKDV_DIVIDE = 2.0; +parameter integer CLKFX_DIVIDE = 1; +parameter integer CLKFX_MULTIPLY = 4; +parameter CLKIN_DIVIDE_BY_2 = "FALSE"; +parameter real CLKIN_PERIOD = 10.0; // non-simulatable +parameter CLKOUT_PHASE_SHIFT = "NONE"; +parameter CLK_FEEDBACK = "1X"; +parameter DESKEW_ADJUST = "SYSTEM_SYNCHRONOUS"; // non-simulatable +parameter DFS_FREQUENCY_MODE = "LOW"; +parameter DLL_FREQUENCY_MODE = "LOW"; +parameter DSS_MODE = "NONE"; // non-simulatable +parameter DUTY_CYCLE_CORRECTION = "TRUE"; +parameter FACTORY_JF = 16'hC080; // non-simulatable +localparam integer MAXPERCLKIN = 5000000; // non-modifiable simulation parameter +localparam integer MAXPERPSCLK = 100000000; // non-modifiable simulation parameter +parameter integer PHASE_SHIFT = 0; +localparam integer SIM_CLKIN_CYCLE_JITTER = 300; // non-modifiable simulation parameter +localparam integer SIM_CLKIN_PERIOD_JITTER = 1000; // non-modifiable simulation parameter +parameter STARTUP_WAIT = "FALSE"; // non-simulatable + + +localparam PS_STEP = 25; + +input CLKFB, CLKIN, DSSEN; +input PSCLK, PSEN, PSINCDEC, RST; + +output CLK0, CLK180, CLK270, CLK2X, CLK2X180, CLK90; +output CLKDV, CLKFX, CLKFX180, LOCKED, PSDONE; +output [7:0] STATUS; + +reg CLK0, CLK180, CLK270, CLK2X, CLK2X180, CLK90; +reg CLKDV, CLKFX, CLKFX180; + +wire clkin_lost_out, clkfx_lost_out; +wire locked_out_out; +wire clkfb_in, clkin_in, dssen_in; +wire psclk_in, psen_in, psincdec_in, rst_in; +reg clk0_out; +reg clk2x_out, clkdv_out; +reg clkfx_out, clkfx180_en; +reg rst_flag; +reg locked_out, psdone_out, ps_overflow_out, ps_lock; +reg locked_out0; +reg locked_out_dly; +reg clkfb_div, clkfb_chk, clkfb_div_en; +integer clkdv_cnt; + +reg [1:0] clkfb_type; +reg [8:0] divide_type; +reg clkin_type; +reg [1:0] ps_type; +reg [3:0] deskew_adjust_mode; +reg dfs_mode_type; +reg dll_mode_type; +reg clk1x_type; +integer ps_in; + +reg lock_period, lock_delay, lock_clkin, lock_clkfb; +reg first_time_locked; +reg en_status; +reg ps_overflow_out_ext; +reg clkin_lost_out_ext; +reg clkfx_lost_out_ext; +reg [1:0] lock_out; +reg lock_out1_neg; +reg lock_fb, lock_ps, lock_ps_dly, lock_fb_dly, lock_fb_dly_tmp; +reg fb_delay_found; +reg clock_stopped; +reg clkin_chkin, clkfb_chkin; + +wire chk_enable, chk_rst; +wire clkin_div; +wire lock_period_pulse; +wire lock_period_dly, lock_period_dly1; + +reg clkin_ps, clkin_ps_tmp, clkin_ps_mkup, clkin_ps_mkup_win, clkin_ps_mkup_flag; +reg clkin_fb; + +time FINE_SHIFT_RANGE; +//time ps_delay, ps_delay_init, ps_delay_md, ps_delay_all, ps_max_range; +integer ps_delay, ps_delay_init, ps_delay_md, ps_delay_all, ps_max_range; +integer ps_delay_last; +integer ps_acc; +time clkin_edge; +time clkin_div_edge; +time clkin_ps_edge; +time delay_edge; +time clkin_period [2:0]; +time period, period_50, period_25; +integer period_int, period_int2, period_int3, period_ps_tmp; +time period_div; +integer period_orig_int; +time period_orig1; +time period_orig; +time period_ps; +time clkout_delay; +time fb_delay; +time period_fx, remain_fx; +time period_dv_high, period_dv_low; +time cycle_jitter, period_jitter; + +reg clkin_window, clkfb_window; +reg [2:0] rst_reg; +reg [12:0] numerator, denominator, gcd; +reg [23:0] i, n, d, p; + +reg notifier; + +initial begin + #1; + if ($realtime == 0) begin + $display ("Simulator Resolution Error : Simulator resolution is set to a value greater than 1 ps."); + $display ("In order to simulate the DCM_SP, the simulator resolution must be set to 1ps or smaller."); + $finish; + end +end + +initial begin + case (CLKDV_DIVIDE) + 1.5 : divide_type = 'd3; + 2.0 : divide_type = 'd4; + 2.5 : divide_type = 'd5; + 3.0 : divide_type = 'd6; + 3.5 : divide_type = 'd7; + 4.0 : divide_type = 'd8; + 4.5 : divide_type = 'd9; + 5.0 : divide_type = 'd10; + 5.5 : divide_type = 'd11; + 6.0 : divide_type = 'd12; + 6.5 : divide_type = 'd13; + 7.0 : divide_type = 'd14; + 7.5 : divide_type = 'd15; + 8.0 : divide_type = 'd16; + 9.0 : divide_type = 'd18; + 10.0 : divide_type = 'd20; + 11.0 : divide_type = 'd22; + 12.0 : divide_type = 'd24; + 13.0 : divide_type = 'd26; + 14.0 : divide_type = 'd28; + 15.0 : divide_type = 'd30; + 16.0 : divide_type = 'd32; + default : begin + $display("Attribute Syntax Error : The attribute CLKDV_DIVIDE on DCM_SP instance %m is set to %0.1f. Legal values for this attribute are 1.5, 2.0, 2.5, 3.0, 3.5, 4.0, 4.5, 5.0, 5.5, 6.0, 6.5, 7.0, 7.5, 8.0, 9.0, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0, or 16.0.", CLKDV_DIVIDE); + $finish; + end + endcase + + if ((CLKFX_DIVIDE <= 0) || (32 < CLKFX_DIVIDE)) begin + $display("Attribute Syntax Error : The attribute CLKFX_DIVIDE on DCM_SP instance %m is set to %d. Legal values for this attribute are 1 ... 32.", CLKFX_DIVIDE); + $finish; + end + + if ((CLKFX_MULTIPLY <= 1) || (32 < CLKFX_MULTIPLY)) begin + $display("Attribute Syntax Error : The attribute CLKFX_MULTIPLY on DCM_SP instance %m is set to %d. Legal values for this attribute are 2 ... 32.", CLKFX_MULTIPLY); + $finish; + end + + case (CLKIN_DIVIDE_BY_2) + "false" : clkin_type = 0; + "FALSE" : clkin_type = 0; + "true" : clkin_type = 1; + "TRUE" : clkin_type = 1; + default : begin + $display("Attribute Syntax Error : The attribute CLKIN_DIVIDE_BY_2 on DCM_SP instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", CLKIN_DIVIDE_BY_2); + $finish; + end + endcase + + case (CLKOUT_PHASE_SHIFT) + "NONE" : begin + ps_in = 256; + ps_type = 2'b0; + end + "none" : begin + ps_in = 256; + ps_type = 2'b0; + end + "FIXED" : begin + ps_in = PHASE_SHIFT + 256; + ps_type = 2'b01; + end + "fixed" : begin + ps_in = PHASE_SHIFT + 256; + ps_type = 2'b01; + end + "VARIABLE" : begin + ps_in = PHASE_SHIFT + 256; + ps_type = 2'b10; + end + "variable" : begin + ps_in = PHASE_SHIFT + 256; + ps_type = 2'b10; + if (PHASE_SHIFT != 0) + $display("Attribute Syntax Warning : The attribute PHASE_SHIFT on DCM_SP instance %m is set to %d. The maximum variable phase shift range is only valid when initial phase shift PHASE_SHIFT is zero.", PHASE_SHIFT); + end + default : begin + $display("Attribute Syntax Error : The attribute CLKOUT_PHASE_SHIFT on DCM_SP instance %m is set to %s. Legal values for this attribute are NONE, FIXED or VARIABLE.", CLKOUT_PHASE_SHIFT); + $finish; + end + endcase + + + case (CLK_FEEDBACK) + "none" : clkfb_type = 2'b00; + "NONE" : clkfb_type = 2'b00; + "1x" : clkfb_type = 2'b01; + "1X" : clkfb_type = 2'b01; + "2x" : clkfb_type = 2'b10; + "2X" : clkfb_type = 2'b10; + default : begin + $display("Attribute Syntax Error : The attribute CLK_FEEDBACK on DCM_SP instance %m is set to %s. Legal values for this attribute are NONE, 1X or 2X.", CLK_FEEDBACK); + $finish; + end + endcase + + case (DESKEW_ADJUST) + "source_synchronous" : deskew_adjust_mode = 8; + "SOURCE_SYNCHRONOUS" : deskew_adjust_mode = 8; + "system_synchronous" : deskew_adjust_mode = 11; + "SYSTEM_SYNCHRONOUS" : deskew_adjust_mode = 11; + "0" : deskew_adjust_mode = 0; + "1" : deskew_adjust_mode = 1; + "2" : deskew_adjust_mode = 2; + "3" : deskew_adjust_mode = 3; + "4" : deskew_adjust_mode = 4; + "5" : deskew_adjust_mode = 5; + "6" : deskew_adjust_mode = 6; + "7" : deskew_adjust_mode = 7; + "8" : deskew_adjust_mode = 8; + "9" : deskew_adjust_mode = 9; + "10" : deskew_adjust_mode = 10; + "11" : deskew_adjust_mode = 11; + "12" : deskew_adjust_mode = 12; + "13" : deskew_adjust_mode = 13; + "14" : deskew_adjust_mode = 14; + "15" : deskew_adjust_mode = 15; + default : begin + $display("Attribute Syntax Error : The attribute DESKEW_ADJUST on DCM_SP instance %m is set to %s. Legal values for this attribute are SOURCE_SYNCHRONOUS, SYSTEM_SYNCHRONOUS or 0 ... 15.", DESKEW_ADJUST); + $finish; + end + endcase + + case (DFS_FREQUENCY_MODE) + "high" : dfs_mode_type = 1; + "HIGH" : dfs_mode_type = 1; + "low" : dfs_mode_type = 0; + "LOW" : dfs_mode_type = 0; + default : begin + $display("Attribute Syntax Error : The attribute DFS_FREQUENCY_MODE on DCM_SP instance %m is set to %s. Legal values for this attribute are HIGH or LOW.", DFS_FREQUENCY_MODE); + $finish; + end + endcase + + period_jitter = SIM_CLKIN_PERIOD_JITTER; + cycle_jitter = SIM_CLKIN_CYCLE_JITTER; + + case (DLL_FREQUENCY_MODE) + "high" : dll_mode_type = 1; + "HIGH" : dll_mode_type = 1; + "low" : dll_mode_type = 0; + "LOW" : dll_mode_type = 0; + default : begin + $display("Attribute Syntax Error : The attribute DLL_FREQUENCY_MODE on DCM_SP instance %m is set to %s. Legal values for this attribute are HIGH or LOW.", DLL_FREQUENCY_MODE); + $finish; + end + endcase + + if ((dll_mode_type ==1) && (clkfb_type == 2'b10)) begin + $display("Attribute Syntax Error : The attributes DLL_FREQUENCY_MODE on DCM_SP instance %m is set to %s and CLK_FEEDBACK is set to %s. CLK_FEEDBACK 2X is not supported when DLL_FREQUENCY_MODE is HIGH.", DLL_FREQUENCY_MODE, CLK_FEEDBACK); + $finish; + end + + case (DSS_MODE) + "none" : ; + "NONE" : ; + default : begin + $display("Attribute Syntax Error : The attribute DSS_MODE on DCM_SP instance %m is set to %s. Legal values for this attribute is NONE.", DSS_MODE); + $finish; + end + endcase + + case (DUTY_CYCLE_CORRECTION) + "false" : clk1x_type = 0; + "FALSE" : clk1x_type = 0; + "true" : clk1x_type = 1; + "TRUE" : clk1x_type = 1; + default : begin + $display("Attribute Syntax Error : The attribute DUTY_CYCLE_CORRECTION on DCM_SP instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", DUTY_CYCLE_CORRECTION); + $finish; + end + endcase + + if ((PHASE_SHIFT < -255) || (PHASE_SHIFT > 255)) begin + $display("Attribute Syntax Error : The attribute PHASE_SHIFT on DCM_SP instance %m is set to %d. Legal values for this attribute are -255 ... 255.", PHASE_SHIFT); + $display("Error : PHASE_SHIFT = %d is not -255 ... 255.", PHASE_SHIFT); + $finish; + end + + case (STARTUP_WAIT) + "false" : ; + "FALSE" : ; + "true" : ; + "TRUE" : ; + default : begin + $display("Attribute Syntax Error : The attribute STARTUP_WAIT on DCM_SP instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", STARTUP_WAIT); + $finish; + end + endcase +end + +// +// fx parameters +// + +initial begin + gcd = 1; + for (i = 2; i <= CLKFX_MULTIPLY; i = i + 1) begin + if (((CLKFX_MULTIPLY % i) == 0) && ((CLKFX_DIVIDE % i) == 0)) + gcd = i; + end + numerator = CLKFX_MULTIPLY / gcd; + denominator = CLKFX_DIVIDE / gcd; +end + +// +// input wire delays +// + +buf b_clkin (clkin_in, CLKIN); +buf b_clkfb (clkfb_in, CLKFB); +buf b_dssen (dssen_in, DSSEN); +buf b_psclk (psclk_in, PSCLK); +buf b_psen (psen_in, PSEN); +buf b_psincdec (psincdec_in, PSINCDEC); +buf b_rst (rst_in, RST); +buf #100 b_LOCKED (LOCKED, locked_out_out); +buf #100 b_PSDONE (PSDONE, psdone_out); +buf b_ps_overflow (STATUS[0], ps_overflow_out_ext); +buf b_clkin_lost (STATUS[1], clkin_lost_out_ext); +buf b_clkfx_lost (STATUS[2], clkfx_lost_out_ext); +buf b_sts_5 (STATUS[5], clkfx_out); +buf b_sts_7 (STATUS[7], clkin_in); + +assign STATUS[4:3] = 2'b0; +assign STATUS[6] = 1'b0; + +dcm_sp_clock_divide_by_2 i_clock_divide_by_2 (clkin_in, clkin_type, clkin_div, rst_in); + +dcm_sp_maximum_period_check #("CLKIN", MAXPERCLKIN) i_max_clkin (clkin_in, rst_in); +dcm_sp_maximum_period_check #("PSCLK", MAXPERPSCLK) i_max_psclk (psclk_in, rst_in); + +dcm_sp_clock_lost i_clkin_lost (clkin_in, first_time_locked, clkin_lost_out, rst_in); +dcm_sp_clock_lost i_clkfx_lost (CLKFX, first_time_locked, clkfx_lost_out, rst_in); + +always @(rst_in or en_status or clkfx_lost_out or clkin_lost_out or ps_overflow_out) + if (rst_in == 1 || en_status == 0) begin + ps_overflow_out_ext = 0; + clkin_lost_out_ext = 0; + clkfx_lost_out_ext = 0; + end + else + begin + ps_overflow_out_ext = ps_overflow_out; + clkin_lost_out_ext = clkin_lost_out; + clkfx_lost_out_ext = clkfx_lost_out; + end + +always @(posedge rst_in or posedge LOCKED) + if (rst_in == 1) + en_status <= 0; + else + en_status <= 1; + + +always @(clkin_div) + clkin_ps_tmp <= #(ps_delay_md) clkin_div; + +always @(clkin_ps_tmp or clkin_ps_mkup or clkin_ps_mkup_win) + if (clkin_ps_mkup_win) + clkin_ps = clkin_ps_mkup; + else + clkin_ps = clkin_ps_tmp; + +always @(ps_delay_last or period_int or ps_delay) begin + period_int2 = 2 * period_int; + period_int3 = 3 * period_int; + if ((ps_delay_last >= period_int && ps_delay < period_int) || + (ps_delay_last >= period_int2 && ps_delay < period_int2) || + (ps_delay_last >= period_int3 && ps_delay < period_int3)) + clkin_ps_mkup_flag = 1; + else + clkin_ps_mkup_flag = 0; +end + +always @(posedge clkin_div or negedge clkin_div) begin + if (ps_type == 2'b10) begin + if ((ps_delay_last > 0 && ps_delay <= 0 ) || clkin_ps_mkup_flag == 1) begin + if (clkin_div) begin + clkin_ps_mkup_win <= 1; + clkin_ps_mkup <= 1; + #1; + @(negedge clkin_div) begin + clkin_ps_mkup_win <= 1; + clkin_ps_mkup <= 0; + end + end + else begin + clkin_ps_mkup_win <= 0; + clkin_ps_mkup <= 0; + #1; + @(posedge clkin_div) begin + clkin_ps_mkup_win <= 1; + clkin_ps_mkup <= 1; + end + @(negedge clkin_div) begin + clkin_ps_mkup_win <= 1; + clkin_ps_mkup <= 0; + end + end + end + else begin + clkin_ps_mkup_win <= 0; + clkin_ps_mkup <= 0; + end + ps_delay_last <= ps_delay; + end +end + +always @(clkin_ps or lock_fb) + clkin_fb = clkin_ps & lock_fb; + +always @(negedge clkfb_in or posedge rst_in) + if (rst_in) + clkfb_div_en <= 0; + else + if (lock_fb_dly && lock_period && lock_fb && ~clkin_ps) + clkfb_div_en <= 1; + +always @(posedge clkfb_in or posedge rst_in) + if (rst_in) + clkfb_div <= 0; + else + if (clkfb_div_en ) + clkfb_div <= ~clkfb_div; + +always @(clkfb_in or clkfb_div ) + if (clkfb_type == 2'b10 ) + clkfb_chk = clkfb_div; + else + clkfb_chk = clkfb_in & lock_fb_dly; + +always @(posedge clkin_fb or posedge chk_rst) + if (chk_rst) + clkin_chkin <= 0; + else + clkin_chkin <= 1; + +always @(posedge clkfb_chk or posedge chk_rst) + if (chk_rst) + clkfb_chkin <= 0; + else + clkfb_chkin <= 1; + + assign chk_rst = (rst_in==1 || clock_stopped==1 ) ? 1 : 0; + assign chk_enable = (clkin_chkin == 1 && clkfb_chkin == 1 && + lock_ps ==1 && lock_fb ==1 && lock_fb_dly == 1) ? 1 : 0; + +always @(posedge clkin_div or posedge rst_in) + if (rst_in) begin + period_div <= 0; + clkin_div_edge <= 0; + end + else + if ( clkin_div ==1 ) begin + clkin_div_edge <= $time; + if (($time - clkin_div_edge) <= (1.5 * period_div)) + period_div <= $time - clkin_div_edge; + else if ((period_div == 0) && (clkin_div_edge != 0)) + period_div <= $time - clkin_div_edge; + end + +always @(posedge clkin_ps or posedge rst_in) + if (rst_in) begin + period_ps <= 0; + clkin_ps_edge <= 0; + end + else + if (clkin_ps == 1 ) begin + clkin_ps_edge <= $time; + if (($time - clkin_ps_edge) <= (1.5 * period_ps)) + period_ps <= $time - clkin_ps_edge; + else if ((period_ps == 0) && (clkin_ps_edge != 0)) + period_ps <= $time - clkin_ps_edge; + end + +always @(posedge clkin_ps) begin + lock_ps <= lock_period; + lock_ps_dly <= lock_ps; + lock_fb <= lock_ps_dly; + lock_fb_dly_tmp <= lock_fb; +end + +always @(negedge clkin_ps or posedge rst_in) + if (rst_in) + lock_fb_dly <= 1'b0; + else + lock_fb_dly <= #(period * 0.75) lock_fb_dly_tmp; + + +always @(period or fb_delay or posedge rst_in) + if (rst_in) + clkout_delay = 0; + else begin + if (fb_delay == 0) + clkout_delay = 0; + else + clkout_delay = period - fb_delay; + end + +// +// generate master reset signal +// + +always @(posedge clkin_in) begin + rst_reg[0] <= rst_in; + rst_reg[1] <= rst_reg[0] & rst_in; + rst_reg[2] <= rst_reg[1] & rst_reg[0] & rst_in; +end + +reg rst_tmp1, rst_tmp2; +initial +begin +rst_tmp1 = 0; +rst_tmp2 = 0; +rst_flag = 0; +end + +always @(rst_in) +begin + if (rst_in) + rst_flag = 0; + + rst_tmp1 = rst_in; + if (rst_tmp1 == 0 && rst_tmp2 == 1) begin + if ((rst_reg[2] & rst_reg[1] & rst_reg[0]) == 0) begin + rst_flag = 1; + $display("Input Error : RST on instance %m must be asserted for 3 CLKIN clock cycles."); + end + end + rst_tmp2 = rst_tmp1; +end + +initial begin + CLK0 = 0; + CLK180 = 0; + CLK270 = 0; + CLK2X = 0; + CLK2X180 = 0; + CLK90 = 0; + CLKDV = 0; + CLKFX = 0; + CLKFX180 = 0; + clk0_out = 0; + clk2x_out = 0; + clkdv_out = 0; + clkdv_cnt = 0; + clkfb_window = 0; + clkfx_out = 0; + clkfx180_en = 0; + clkin_div_edge = 0; + clkin_period[0] = 0; + clkin_period[1] = 0; + clkin_period[2] = 0; + clkin_edge = 0; + clkin_ps_edge = 0; + clkin_window = 0; + clkout_delay = 0; + clock_stopped = 1; + fb_delay = 0; + fb_delay_found = 0; + lock_clkfb = 0; + lock_clkin = 0; + lock_delay = 0; + lock_fb = 0; + lock_fb_dly = 0; + lock_out = 2'b00; + lock_out1_neg = 0; + lock_period = 0; + lock_ps = 0; + lock_ps_dly = 0; + locked_out = 0; + locked_out0 = 0; + locked_out_dly = 0; + period = 0; + period_int = 0; + period_int2 = 0; + period_int3 = 0; + period_div = 0; + period_fx = 0; + period_orig = 0; + period_orig_int = 0; + period_ps = 0; + psdone_out = 0; + ps_delay = 0; + ps_delay_md = 0; + ps_delay_init = 0; + ps_acc = 0; + ps_delay_all = 0; + ps_lock = 0; + ps_overflow_out = 0; + ps_overflow_out_ext = 0; + clkin_lost_out_ext = 0; + clkfx_lost_out_ext = 0; + rst_reg = 3'b000; + first_time_locked = 0; + en_status = 0; + clkfb_div = 0; + clkin_chkin = 0; + clkfb_chkin = 0; + clkin_ps_mkup = 0; + clkin_ps_mkup_win = 0; + clkin_ps_mkup_flag = 0; + ps_delay_last = 0; + clkin_ps_tmp = 0; +end + +// RST less than 3 cycles, lock = x + + assign locked_out_out = (rst_flag) ? 1'bx : locked_out_dly; + + always @(locked_out) + locked_out_dly <= #clkout_delay locked_out; + +// +// detect_first_time_locked +// +always @(posedge locked_out) + if (first_time_locked == 0) + first_time_locked <= 1; + +// +// phase shift parameters +// + +always @(posedge lock_period) + ps_delay_init <= ps_in * period_orig /256; + + +always @(period) begin + period_int = period; + if (clkin_type==1) + period_ps_tmp = 2 * period; + else + period_ps_tmp = period; + + if (period_ps_tmp > 3000) + ps_max_range = (20 * (period_ps_tmp - 3000))/1000; + else + ps_max_range = 0; +end + +always @(ps_delay or rst_in or period_int or fb_delay_found) + if ( rst_in) + ps_delay_md = 0; + else if (fb_delay_found) begin + if (ps_type == 2'b10) + ps_delay_md = period_int + ps_delay % period_int; + else + ps_delay_md = period_int + (ps_in * period_int) /256; + end + +always @(posedge psclk_in or posedge rst_in or posedge lock_period_pulse) + if (rst_in) begin + ps_delay <= 0; + ps_overflow_out <= 0; + ps_acc <= 0; + end + else if (lock_period_pulse) + ps_delay <= ps_delay_init; + else begin + if (ps_type == 2'b10) + if (psen_in) begin + if (ps_lock == 1) + $display(" Warning : Please wait for PSDONE signal before adjusting the Phase Shift."); + else if (lock_ps) begin + if (psincdec_in == 1) begin + if (ps_acc > ps_max_range) + ps_overflow_out <= 1; + else begin + ps_delay <= ps_delay + PS_STEP; + ps_acc <= ps_acc + 1; + ps_overflow_out <= 0; + end + ps_lock <= 1; + end + else if (psincdec_in == 0) begin + if (ps_acc < -ps_max_range) + ps_overflow_out <= 1; + else begin + ps_delay <= ps_delay - PS_STEP; + ps_acc <= ps_acc - 1; + ps_overflow_out <= 0; + end + ps_lock <= 1; + end + end + end + if (psdone_out) + ps_lock <= 0; + end + +always @(posedge ps_lock) begin + @(posedge clkin_ps); + @(posedge psclk_in); + @(posedge psclk_in); + @(posedge psclk_in) + psdone_out <= 1; + @(posedge psclk_in) + psdone_out <= 0; +// ps_lock <= 0; +end + +// +// determine clock period +// + +always @(posedge clkin_div or negedge clkin_div or posedge rst_in) + if (rst_in == 1) begin + clkin_period[0] <= 0; + clkin_period[1] <= 0; + clkin_period[2] <= 0; + clkin_edge <= 0; + end + else + if (clkin_div == 1) begin + clkin_edge <= $time; + clkin_period[2] <= clkin_period[1]; + clkin_period[1] <= clkin_period[0]; + if (clkin_edge != 0) + clkin_period[0] <= $time - clkin_edge; + end + else if (clkin_div == 0) + if (lock_period == 1) + if (100000000 < clkin_period[0]/1000) + begin + end + else if ((period_orig * 2 < clkin_period[0]) && (clock_stopped == 0)) begin + clkin_period[0] <= clkin_period[1]; + end + +always @(negedge clkin_div or posedge rst_in) + if (rst_in == 1) begin + lock_period <= 0; + clock_stopped <= 1; + end + else begin + if (lock_period == 1'b0) begin + if ((clkin_period[0] != 0) && + (clkin_period[0] - cycle_jitter <= clkin_period[1]) && + (clkin_period[1] <= clkin_period[0] + cycle_jitter) && + (clkin_period[1] - cycle_jitter <= clkin_period[2]) && + (clkin_period[2] <= clkin_period[1] + cycle_jitter)) begin + lock_period <= 1; + period_orig <= (clkin_period[0] + + clkin_period[1] + + clkin_period[2]) / 3; + period <= clkin_period[0]; + end + end + else if (lock_period == 1'b1) begin + if (100000000 < (clkin_period[0] / 1000)) begin + $display(" Warning : CLKIN stopped toggling on instance %m exceeds %d ms. Current CLKIN Period = %1.3f ns.", 100, clkin_period[0] / 1000.0); + lock_period <= 0; + @(negedge rst_reg[2]); + end + else if ((period_orig * 2 < clkin_period[0]) && clock_stopped == 1'b0) begin + clock_stopped <= 1'b1; + end + else if ((clkin_period[0] < period_orig - period_jitter) || + (period_orig + period_jitter < clkin_period[0])) begin + $display(" Warning : Input Clock Period Jitter on instance %m exceeds %1.3f ns. Locked CLKIN Period = %1.3f. Current CLKIN Period = %1.3f.", period_jitter / 1000.0, period_orig / 1000.0, clkin_period[0] / 1000.0); + lock_period <= 0; + @(negedge rst_reg[2]); + end + else if ((clkin_period[0] < clkin_period[1] - cycle_jitter) || + (clkin_period[1] + cycle_jitter < clkin_period[0])) begin + $display(" Warning : Input Clock Cycle-Cycle Jitter on instance %m exceeds %1.3f ns. Previous CLKIN Period = %1.3f. Current CLKIN Period = %1.3f.", cycle_jitter / 1000.0, clkin_period[1] / 1000.0, clkin_period[0] / 1000.0); + lock_period <= 0; + @(negedge rst_reg[2]); + end + else begin + period <= clkin_period[0]; + clock_stopped <= 1'b0; + end + end +end + + assign #1 lock_period_dly1 = lock_period; + assign #(period_50) lock_period_dly = lock_period_dly1; + assign lock_period_pulse = (lock_period_dly1==1 && lock_period_dly==0) ? 1 : 0; + +// +// determine clock delay +// + + assign lock_out_fbd = lock_out[0]; + +always @(posedge lock_out_fbd or posedge rst_in) + if (rst_in) begin + fb_delay <= 0; + fb_delay_found <= 0; + end + else begin + if ( clkfb_type != 2'b00 && fb_delay_found == 0) begin + if (clkfb_type == 2'b01) begin + @(posedge CLK0 or rst_in) + delay_edge = $time; + end + else if (clkfb_type == 2'b10) begin + @(posedge CLK2X or rst_in) + delay_edge = $time; + end + @(posedge clkfb_in or rst_in) begin + if (clkfb_type == 2'b10) begin + period_orig1 = period_orig / 2; + fb_delay <= ($time - delay_edge) % period_orig1; + end + else + fb_delay <= ($time - delay_edge) % period_orig; + + fb_delay_found <= 1; + end + end + end + +// +// determine feedback lock +// + +always @(posedge clkfb_chk or posedge rst_in) + if (rst_in) + clkfb_window <= 0; + else begin + clkfb_window <= 1; + #cycle_jitter clkfb_window <= 0; + end + +always @(posedge clkin_fb or posedge rst_in) + if (rst_in) + clkin_window <= 0; + else begin + clkin_window <= 1; + #cycle_jitter clkin_window <= 0; + end + +always @(posedge clkin_fb or posedge rst_in) + if (rst_in) + lock_clkin <= 0; + else begin + #1 + if ((clkfb_window && fb_delay_found) || (clkin_lost_out == 1'b1 && lock_out[0]==1'b1)) + lock_clkin <= 1; + else + if (chk_enable==1 && ps_lock == 0) + lock_clkin <= 0; + end + +always @(posedge clkfb_chk or posedge rst_in) + if (rst_in) + lock_clkfb <= 0; + else begin + #1 + if ((clkin_window && fb_delay_found) || (clkin_lost_out == 1'b1 && lock_out[0]==1'b1)) + lock_clkfb <= 1; + else + if (chk_enable ==1 && ps_lock == 0) + lock_clkfb <= 0; + end + +always @(negedge clkin_fb or posedge rst_in) + if (rst_in) + lock_delay <= 0; + else + lock_delay <= lock_clkin || lock_clkfb; + +// +// generate lock signal +// + +always @(posedge clkin_ps or posedge rst_in) + if (rst_in) begin + lock_out <= 2'b0; + locked_out <=0; + locked_out0 <=0; + end + else begin + lock_out[0] <= lock_period; + lock_out[1] <= lock_out[0]; + if (lock_fb_dly_tmp == 1) + locked_out0 <= lock_out[1]; + locked_out <= locked_out0; + end + +always @(negedge clkin_ps or posedge rst_in) + if (rst_in) + lock_out1_neg <= 0; + else +// lock_out1_neg <= lock_out[1]; + lock_out1_neg <= locked_out0; + + +// +// generate the clk1x_out +// + +always @(period) begin + period_25 = period /4; + period_50 = 2 * period_25; +end + +always @(posedge clkin_ps or negedge clkin_ps or posedge rst_in) + if (rst_in) + clk0_out <= 0; + else + if (clkin_ps ==1) + if (clk1x_type==1 && lock_out[0]) begin + clk0_out <= 1; + #(period_50) + clk0_out <= 0; + end + else + clk0_out <= 1; + else + if (clkin_ps == 0 && ((clk1x_type && lock_out[0]) == 0 || (lock_out[0]== 1 && lock_out[1]== 0))) + clk0_out <= 0; + +// +// generate the clk2x_out +// + +always @(posedge clkin_ps or posedge rst_in ) + if (rst_in) + clk2x_out <= 0; + else begin + clk2x_out <= 1; + #(period_25) + clk2x_out <= 0; + if (lock_out[0]) begin + #(period_25); + clk2x_out <= 1; + #(period_25); + clk2x_out <= 0; + end + else begin + #(period_50); + end + end + +// +// generate the clkdv_out +// + +always @(posedge clkin_ps or negedge clkin_ps or posedge rst_in) + if (rst_in) begin + clkdv_out <= 1'b0; + clkdv_cnt <= 0; + end + else + if (lock_out1_neg) begin + if (clkdv_cnt >= divide_type -1) + clkdv_cnt <= 0; + else + clkdv_cnt <= clkdv_cnt + 1; + + if (clkdv_cnt < divide_type /2) + clkdv_out <= 1'b1; + else + if ( (divide_type[0] == 1'b1) && dll_mode_type == 1'b0) + clkdv_out <= #(period_25) 1'b0; + else + clkdv_out <= 1'b0; + end + + +// +// generate fx output signal +// + +always @(lock_period or period or denominator or numerator) begin + if (lock_period == 1'b1) begin + period_fx = (period * denominator) / (numerator * 2); + remain_fx = (period * denominator) % (numerator * 2); + end +end + +always @(posedge clkin_ps or posedge clkin_lost_out or posedge rst_in ) + if (rst_in == 1) + clkfx_out = 1'b0; + else if (clkin_lost_out == 1'b1 ) begin + if (locked_out == 1) + @(negedge rst_reg[2]); + end + else + if (locked_out0 == 1) begin + clkfx_out = 1'b1; + for (p = 0; p < (numerator * 2 - 1); p = p + 1) begin + #(period_fx); + if (p < remain_fx) + #1; + clkfx_out = !clkfx_out; + end + if (period_fx > (period_50)) begin + #(period_fx - (period_50)); + end + end + +// +// generate all output signal +// + +always @(rst_in) +if (rst_in) begin + assign CLK0 = 0; + assign CLK90 = 0; + assign CLK180 = 0; + assign CLK270 = 0; + assign CLK2X = 0; + assign CLK2X180 =0; + assign CLKDV = 0; + assign CLKFX = 0; + assign CLKFX180 = 0; +end +else begin + deassign CLK0; + deassign CLK90; + deassign CLK180; + deassign CLK270; + deassign CLK2X; + deassign CLK2X180; + deassign CLKDV; + deassign CLKFX; + deassign CLKFX180; +end + +always @(clk0_out) begin + CLK0 <= #(clkout_delay) clk0_out && (clkfb_type != 2'b00); + CLK90 <= #(clkout_delay + period_25) clk0_out && !dll_mode_type && (clkfb_type != 2'b00); + CLK180 <= #(clkout_delay) ~clk0_out && (clkfb_type != 2'b00); + CLK270 <= #(clkout_delay + period_25) ~clk0_out && !dll_mode_type && (clkfb_type != 2'b00); + end + +always @(clk2x_out) begin + CLK2X <= #(clkout_delay) clk2x_out && !dll_mode_type && (clkfb_type != 2'b00); + CLK2X180 <= #(clkout_delay) ~clk2x_out && !dll_mode_type && (clkfb_type != 2'b00); +end + +always @(clkdv_out) + CLKDV <= #(clkout_delay) clkdv_out && (clkfb_type != 2'b00); + +always @(clkfx_out ) + CLKFX <= #(clkout_delay) clkfx_out; + +always @( clkfx_out or first_time_locked or locked_out) + if ( ~first_time_locked) + CLKFX180 = 0; + else + CLKFX180 <= #(clkout_delay) ~clkfx_out; + + +endmodule + +////////////////////////////////////////////////////// + +module dcm_sp_clock_divide_by_2 (clock, clock_type, clock_out, rst); +input clock; +input clock_type; +input rst; +output clock_out; + +reg clock_out; +reg clock_div2; +reg [2:0] rst_reg; +wire clk_src; + +initial begin + clock_out = 1'b0; + clock_div2 = 1'b0; +end + +always @(posedge clock) + clock_div2 <= ~clock_div2; + +always @(posedge clock) begin + rst_reg[0] <= rst; + rst_reg[1] <= rst_reg[0] & rst; + rst_reg[2] <= rst_reg[1] & rst_reg[0] & rst; +end + +assign clk_src = (clock_type) ? clock_div2 : clock; + +always @(clk_src or rst or rst_reg) + if (rst == 1'b0) + clock_out = clk_src; + else if (rst == 1'b1) begin + clock_out = 1'b0; + @(negedge rst_reg[2]); + if (clk_src == 1'b1) + @(negedge clk_src); + end + + +endmodule + +module dcm_sp_maximum_period_check (clock, rst); +parameter clock_name = ""; +parameter maximum_period = 0; +input clock; +input rst; + +time clock_edge; +time clock_period; + +initial begin + clock_edge = 0; + clock_period = 0; +end + +always @(posedge clock) begin + clock_edge <= $time; +// clock_period <= $time - clock_edge; + clock_period = $time - clock_edge; + if (clock_period > maximum_period ) begin + if (rst == 0) + $display(" Warning : Input clock period of %1.3f ns, on the %s port of instance %m exceeds allowed value of %1.3f ns at time %1.3f ns.", clock_period/1000.0, clock_name, maximum_period/1000.0, $time/1000.0); + end +end +endmodule + +module dcm_sp_clock_lost (clock, enable, lost, rst); +input clock; +input enable; +input rst; +output lost; + +time clock_edge, clock_edge_neg; +time period, period_neg, period_tmp, period_neg_tmp, period_tmp_win, period_neg_tmp_win; +time period_chk_win; +integer clock_low, clock_high; +integer clock_posedge, clock_negedge; +integer clock_second_pos, clock_second_neg; +reg lost_r, lost_f, lost; + +initial begin + clock_edge = 0; + clock_edge_neg = 0; + clock_high = 0; + clock_low = 0; + lost_r = 0; + lost_f = 0; + period = 0; + period_neg = 0; + period_tmp = 0; + period_tmp_win = 0; + period_neg_tmp = 0; + period_neg_tmp_win = 0; + period_chk_win = 0; + clock_posedge = 0; + clock_negedge = 0; + clock_second_pos = 0; + clock_second_neg = 0; +end + +always @(posedge clock or posedge rst) + if (rst==1) + period <= 0; + else begin + clock_edge <= $time; + period_tmp = $time - clock_edge; + if (period != 0 && (period_tmp <= period_tmp_win)) + period <= period_tmp; + else if (period != 0 && (period_tmp > period_tmp_win)) + period <= 0; + else if ((period == 0) && (clock_edge != 0) && clock_second_pos == 1) + period <= period_tmp; + end + +always @(period) begin + period_tmp_win = 1.5 * period; + period_chk_win = (period * 9.1) / 10; +end + +always @(negedge clock or posedge rst) + if (rst) + period_neg <= 0; + else begin + clock_edge_neg <= $time; + period_neg_tmp = $time - clock_edge_neg; + if (period_neg != 0 && ( period_neg_tmp <= period_neg_tmp_win)) + period_neg <= period_neg_tmp; + else if (period_neg != 0 && (period_neg_tmp > period_neg_tmp_win)) + period_neg <= 0; + else if ((period_neg == 0) && (clock_edge_neg != 0) && clock_second_neg == 1) + period_neg <= period_neg_tmp; + end + +always @(period_neg) + period_neg_tmp_win = 1.5 * period_neg; + + +always @(posedge clock or posedge rst) + if (rst) + lost_r <= 0; + else + if (enable == 1 && clock_second_pos == 1) begin + #1; + if ( period != 0) + lost_r <= 0; + #(period_chk_win) + if ((clock_low != 1) && (clock_posedge != 1) && rst == 0) + lost_r <= 1; + end + +always @(posedge clock or negedge clock or posedge rst) + if (rst) begin + clock_second_pos <= 0; + clock_second_neg <= 0; + end + else if (clock) + clock_second_pos <= 1; + else if (~clock) + clock_second_neg <= 1; + +always @(negedge clock or posedge rst) + if (rst==1) begin + lost_f <= 0; + end + else begin + if (enable == 1 && clock_second_neg == 1) begin + if ( period != 0) + lost_f <= 0; + #(period_chk_win) + if ((clock_high != 1) && (clock_negedge != 1) && rst == 0 && (period <= period_neg)) + lost_f <= 1; + end + end + +always @( lost_r or lost_f or enable) +begin + if (enable == 1) + lost = lost_r | lost_f; + else + lost = 0; +end + + +always @(posedge clock or negedge clock or posedge rst) + if (rst==1) begin + clock_low <= 0; + clock_high <= 0; + clock_posedge <= 0; + clock_negedge <= 0; + end + else begin + if (clock ==1) begin + clock_low <= 0; + clock_high <= 1; + clock_posedge <= 0; + clock_negedge <= 1; + end + else if (clock == 0) begin + clock_low <= 1; + clock_high <= 0; + clock_posedge <= 1; + clock_negedge <= 0; + end +end + + +endmodule diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/DNA_PORT.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/DNA_PORT.v new file mode 100644 index 0000000..92bd107 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/DNA_PORT.v @@ -0,0 +1,84 @@ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Device DNA Data Access Port +// /___/ /\ Filename : DNA_PORT.v +// \ \ / \ Timestamp : Mon Oct 10 14:55:34 PDT 2005 +// \___\/\___\ +// +// Revision: +// 10/10/05 - Initial version. +// 05/29/07 - Added wire declaration for internal signals +// 04/07/08 - CR 469973 -- Header Description fix +// 06/04/08 - CR 472697 -- added check for SIM_DNA_VALUE[56:55] +// 09/18/08 - CR 488646 -- added period check for simprim +// 10/28/08 - IR 494079 -- Shifting of dna_value is corrected to MSB first out +// End Revision + +`timescale 1 ps / 1 ps + +module DNA_PORT (DOUT, CLK, DIN, READ, SHIFT); + + parameter SIM_DNA_VALUE = 57'h0; + + output DOUT; + + input CLK, DIN, READ, SHIFT; + + tri0 GSR = glbl.GSR; + + localparam MAX_DNA_BITS = 57; + localparam MSB_DNA_BITS = MAX_DNA_BITS - 1; + + reg [MSB_DNA_BITS:0] dna_val = SIM_DNA_VALUE; + reg dout_out; + + + wire clk_in, din_in, gsr_in, read_in, shift_in; + + buf b_dout (DOUT, dout_out); + buf b_clk (clk_in, CLK); + buf b_din (din_in, DIN); + buf buf_gsr (gsr_in, GSR); + buf b_read (read_in, READ); + buf b_shift (shift_in, SHIFT); + + initial begin + dna_val = SIM_DNA_VALUE; + if(dna_val[MSB_DNA_BITS : (MSB_DNA_BITS -1)] != 2'b10) begin + $display("Attribute Syntax Warning : SIM_DNA_VALUE bits [56:55] on instance %m do not match the expected value \"10\". The simulation will not exactly model the hardware behavior, as detailed in the Spartan-3 Generation FPGA User Guide"); + end + + end + +// GSR has no effect + + always @(posedge clk_in) begin + if(read_in == 1'b1) begin + dna_val = SIM_DNA_VALUE; + dout_out = 1'b1; + end // read_in == 1'b1 + else if(read_in == 1'b0) + if(shift_in == 1'b1) begin +// IR 494079 +// dna_val = {din_in, dna_val[MSB_DNA_BITS :1]}; + dna_val = {dna_val[MSB_DNA_BITS-1 : 0], din_in}; + dout_out = dna_val[MSB_DNA_BITS]; + end // shift_in == 1'b1 + end // always @ (posedge clk_in) + + + specify + + (CLK => DOUT) = (100, 100); + specparam PATHPULSE$ = 0; + + endspecify + +endmodule // DNA_PORT diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/DSP48.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/DSP48.v new file mode 100644 index 0000000..0813f1b --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/DSP48.v @@ -0,0 +1,1027 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/virtex4/DSP48.v,v 1.15 2008/08/20 23:54:41 fphillip Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2005 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / 18X18 Signed Multiplier Followed by Three-Input Adder with Pipeline Registers +// /___/ /\ Filename : DSP48.v +// \ \ / \ Timestamp : Thu Mar 11 16:43:44 PST 2005 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 03/11/05 - Initialized outpus. +// 08/21/06 - CR 232521 -- fixed DRC check to allow "0010101_11" +// 05/29/07 - Added wire declaration for internal signals +// 02/06/08 - CR 455601 -- DRC relax for OPMODEREG/CARRYINSELREG +// 08/20/08 - CR 479833 -- DRC relax for OPMODEREG/CARRYINSELREG +// End Revision + +`timescale 1 ps / 1 ps + +module DSP48 (BCOUT, P, PCOUT, A, B, BCIN, C, CARRYIN, CARRYINSEL, CEA, CEB, CEC, CECARRYIN, CECINSUB, CECTRL, CEM, CEP, CLK, OPMODE, PCIN, RSTA, RSTB, RSTC, RSTCARRYIN, RSTCTRL, RSTM, RSTP, SUBTRACT); + + output [17:0] BCOUT; + output [47:0] P; + output [47:0] PCOUT; + + input [17:0] A; + input [17:0] B; + input [17:0] BCIN; + input [47:0] C; + input CARRYIN; + input [1:0] CARRYINSEL; + input CEA; + input CEB; + input CEC; + input CECARRYIN; + input CECINSUB; + input CECTRL; + input CEM; + input CEP; + input CLK; + tri0 GSR = glbl.GSR; + input [6:0] OPMODE; + input [47:0] PCIN; + input RSTA; + input RSTB; + input RSTC; + input RSTCARRYIN; + input RSTCTRL; + input RSTM; + input RSTP; + input SUBTRACT; + + parameter integer AREG = 1; + parameter integer BREG = 1; + parameter B_INPUT = "DIRECT"; + parameter integer CARRYINREG = 1; + parameter integer CARRYINSELREG = 1; + parameter integer CREG = 1; + parameter LEGACY_MODE = "MULT18X18S"; + parameter integer MREG = 1; + parameter integer OPMODEREG = 1; + parameter integer PREG = 1; + parameter integer SUBTRACTREG = 1; + + reg [17:0] a_in_int; + reg [17:0] b_o_mux, qb_o_mux = 18'b0, qb_o_reg1, qb_o_reg2; + reg [17:0] qa_o_mux, qa_o_reg1, qa_o_reg2; + reg [1:0] qcarryinsel_o_mux, qcarryinsel_o_reg1; + reg [35:0] qmult_o_mux, qmult_o_reg1; + reg [47:0] qc_o_mux, qc_o_reg1; + reg [47:0] qp_o_mux = 48'b0, qp_o_reg1; + reg [47:0] qx_o_mux, qy_o_mux, qz_o_mux; + reg [6:0] qopmode_o_mux, qopmode_o_reg1; + reg carryin_o_mux2, carryin_o_mux4, qcarryin_o_mux1, qcarryin_o_reg3; + reg qcarryin_o_mux, qcarryin_o_reg1; + reg qsubtract_o_mux, qsubtract_o_reg1; + reg invalid_opmode, add_flag; + reg [47:0] add_o; + + wire [17:0] bcin_in, a_in, b_in; + wire [1:0] carryinsel_in; + wire [35:0] mult_o; + wire [47:0] pcin_in, c_in; + wire [6:0] opmode_in; + wire qb_o_mux0, qb_o_mux1, qb_o_mux2, qb_o_mux3, qb_o_mux4, qb_o_mux5, qb_o_mux6, qb_o_mux7, qb_o_mux8, qb_o_mux9, qb_o_mux10, qb_o_mux11, qb_o_mux12, qb_o_mux13, qb_o_mux14, qb_o_mux15, qb_o_mux16, qb_o_mux17; + wire qp_o_mux0, qp_o_mux1, qp_o_mux2, qp_o_mux3, qp_o_mux4, qp_o_mux5, qp_o_mux6, qp_o_mux7, qp_o_mux8, qp_o_mux9, qp_o_mux10, qp_o_mux11, qp_o_mux12, qp_o_mux13, qp_o_mux14, qp_o_mux15, qp_o_mux16, qp_o_mux17, qp_o_mux18, qp_o_mux19, qp_o_mux20, qp_o_mux21, qp_o_mux22, qp_o_mux23, qp_o_mux24, qp_o_mux25, qp_o_mux26, qp_o_mux27, qp_o_mux28, qp_o_mux29, qp_o_mux30, qp_o_mux31, qp_o_mux32, qp_o_mux33, qp_o_mux34, qp_o_mux35, qp_o_mux36, qp_o_mux37, qp_o_mux38, qp_o_mux39, qp_o_mux40, qp_o_mux41, qp_o_mux42, qp_o_mux43, qp_o_mux44, qp_o_mux45, qp_o_mux46, qp_o_mux47; + wire selp47; + + wire carryin_in; + wire cea_in; + wire ceb_in; + wire cec_in; + wire cecarryin_in; + wire cecinsub_in; + wire cectrl_in; + wire cem_in; + wire cep_in; + wire clk_in; + wire gsr_in; + + wire rsta_in; + wire rstb_in; + wire rstcarryin_in; + wire rstc_in; + wire rstctrl_in; + wire rstm_in; + wire rstp_in; + wire subtract_in; + + buf b_qp_o_mux_0 (qp_o_mux0, qp_o_mux[0]); + buf b_qp_o_mux_1 (qp_o_mux1, qp_o_mux[1]); + buf b_qp_o_mux_2 (qp_o_mux2, qp_o_mux[2]); + buf b_qp_o_mux_3 (qp_o_mux3, qp_o_mux[3]); + buf b_qp_o_mux_4 (qp_o_mux4, qp_o_mux[4]); + buf b_qp_o_mux_5 (qp_o_mux5, qp_o_mux[5]); + buf b_qp_o_mux_6 (qp_o_mux6, qp_o_mux[6]); + buf b_qp_o_mux_7 (qp_o_mux7, qp_o_mux[7]); + buf b_qp_o_mux_8 (qp_o_mux8, qp_o_mux[8]); + buf b_qp_o_mux_9 (qp_o_mux9, qp_o_mux[9]); + buf b_qp_o_mux_10 (qp_o_mux10, qp_o_mux[10]); + buf b_qp_o_mux_11 (qp_o_mux11, qp_o_mux[11]); + buf b_qp_o_mux_12 (qp_o_mux12, qp_o_mux[12]); + buf b_qp_o_mux_13 (qp_o_mux13, qp_o_mux[13]); + buf b_qp_o_mux_14 (qp_o_mux14, qp_o_mux[14]); + buf b_qp_o_mux_15 (qp_o_mux15, qp_o_mux[15]); + buf b_qp_o_mux_16 (qp_o_mux16, qp_o_mux[16]); + buf b_qp_o_mux_17 (qp_o_mux17, qp_o_mux[17]); + buf b_qp_o_mux_18 (qp_o_mux18, qp_o_mux[18]); + buf b_qp_o_mux_19 (qp_o_mux19, qp_o_mux[19]); + buf b_qp_o_mux_20 (qp_o_mux20, qp_o_mux[20]); + buf b_qp_o_mux_21 (qp_o_mux21, qp_o_mux[21]); + buf b_qp_o_mux_22 (qp_o_mux22, qp_o_mux[22]); + buf b_qp_o_mux_23 (qp_o_mux23, qp_o_mux[23]); + buf b_qp_o_mux_24 (qp_o_mux24, qp_o_mux[24]); + buf b_qp_o_mux_25 (qp_o_mux25, qp_o_mux[25]); + buf b_qp_o_mux_26 (qp_o_mux26, qp_o_mux[26]); + buf b_qp_o_mux_27 (qp_o_mux27, qp_o_mux[27]); + buf b_qp_o_mux_28 (qp_o_mux28, qp_o_mux[28]); + buf b_qp_o_mux_29 (qp_o_mux29, qp_o_mux[29]); + buf b_qp_o_mux_30 (qp_o_mux30, qp_o_mux[30]); + buf b_qp_o_mux_31 (qp_o_mux31, qp_o_mux[31]); + buf b_qp_o_mux_32 (qp_o_mux32, qp_o_mux[32]); + buf b_qp_o_mux_33 (qp_o_mux33, qp_o_mux[33]); + buf b_qp_o_mux_34 (qp_o_mux34, qp_o_mux[34]); + buf b_qp_o_mux_35 (qp_o_mux35, qp_o_mux[35]); + buf b_qp_o_mux_36 (qp_o_mux36, qp_o_mux[36]); + buf b_qp_o_mux_37 (qp_o_mux37, qp_o_mux[37]); + buf b_qp_o_mux_38 (qp_o_mux38, qp_o_mux[38]); + buf b_qp_o_mux_39 (qp_o_mux39, qp_o_mux[39]); + buf b_qp_o_mux_40 (qp_o_mux40, qp_o_mux[40]); + buf b_qp_o_mux_41 (qp_o_mux41, qp_o_mux[41]); + buf b_qp_o_mux_42 (qp_o_mux42, qp_o_mux[42]); + buf b_qp_o_mux_43 (qp_o_mux43, qp_o_mux[43]); + buf b_qp_o_mux_44 (qp_o_mux44, qp_o_mux[44]); + buf b_qp_o_mux_45 (qp_o_mux45, qp_o_mux[45]); + buf b_qp_o_mux_46 (qp_o_mux46, qp_o_mux[46]); + buf b_qp_o_mux_47 (qp_o_mux47, qp_o_mux[47]); + + buf b_p_o_0 (P[0], qp_o_mux0); + buf b_p_o_1 (P[1], qp_o_mux1); + buf b_p_o_2 (P[2], qp_o_mux2); + buf b_p_o_3 (P[3], qp_o_mux3); + buf b_p_o_4 (P[4], qp_o_mux4); + buf b_p_o_5 (P[5], qp_o_mux5); + buf b_p_o_6 (P[6], qp_o_mux6); + buf b_p_o_7 (P[7], qp_o_mux7); + buf b_p_o_8 (P[8], qp_o_mux8); + buf b_p_o_9 (P[9], qp_o_mux9); + buf b_p_o_10 (P[10], qp_o_mux10); + buf b_p_o_11 (P[11], qp_o_mux11); + buf b_p_o_12 (P[12], qp_o_mux12); + buf b_p_o_13 (P[13], qp_o_mux13); + buf b_p_o_14 (P[14], qp_o_mux14); + buf b_p_o_15 (P[15], qp_o_mux15); + buf b_p_o_16 (P[16], qp_o_mux16); + buf b_p_o_17 (P[17], qp_o_mux17); + buf b_p_o_18 (P[18], qp_o_mux18); + buf b_p_o_19 (P[19], qp_o_mux19); + buf b_p_o_20 (P[20], qp_o_mux20); + buf b_p_o_21 (P[21], qp_o_mux21); + buf b_p_o_22 (P[22], qp_o_mux22); + buf b_p_o_23 (P[23], qp_o_mux23); + buf b_p_o_24 (P[24], qp_o_mux24); + buf b_p_o_25 (P[25], qp_o_mux25); + buf b_p_o_26 (P[26], qp_o_mux26); + buf b_p_o_27 (P[27], qp_o_mux27); + buf b_p_o_28 (P[28], qp_o_mux28); + buf b_p_o_29 (P[29], qp_o_mux29); + buf b_p_o_30 (P[30], qp_o_mux30); + buf b_p_o_31 (P[31], qp_o_mux31); + buf b_p_o_32 (P[32], qp_o_mux32); + buf b_p_o_33 (P[33], qp_o_mux33); + buf b_p_o_34 (P[34], qp_o_mux34); + buf b_p_o_35 (P[35], qp_o_mux35); + buf b_p_o_36 (P[36], qp_o_mux36); + buf b_p_o_37 (P[37], qp_o_mux37); + buf b_p_o_38 (P[38], qp_o_mux38); + buf b_p_o_39 (P[39], qp_o_mux39); + buf b_p_o_40 (P[40], qp_o_mux40); + buf b_p_o_41 (P[41], qp_o_mux41); + buf b_p_o_42 (P[42], qp_o_mux42); + buf b_p_o_43 (P[43], qp_o_mux43); + buf b_p_o_44 (P[44], qp_o_mux44); + buf b_p_o_45 (P[45], qp_o_mux45); + buf b_p_o_46 (P[46], qp_o_mux46); + buf b_p_o_47 (P[47], qp_o_mux47); + + buf b_pcout_out_0 (PCOUT[0], qp_o_mux0); + buf b_pcout_out_1 (PCOUT[1], qp_o_mux1); + buf b_pcout_out_2 (PCOUT[2], qp_o_mux2); + buf b_pcout_out_3 (PCOUT[3], qp_o_mux3); + buf b_pcout_out_4 (PCOUT[4], qp_o_mux4); + buf b_pcout_out_5 (PCOUT[5], qp_o_mux5); + buf b_pcout_out_6 (PCOUT[6], qp_o_mux6); + buf b_pcout_out_7 (PCOUT[7], qp_o_mux7); + buf b_pcout_out_8 (PCOUT[8], qp_o_mux8); + buf b_pcout_out_9 (PCOUT[9], qp_o_mux9); + buf b_pcout_out_10 (PCOUT[10], qp_o_mux10); + buf b_pcout_out_11 (PCOUT[11], qp_o_mux11); + buf b_pcout_out_12 (PCOUT[12], qp_o_mux12); + buf b_pcout_out_13 (PCOUT[13], qp_o_mux13); + buf b_pcout_out_14 (PCOUT[14], qp_o_mux14); + buf b_pcout_out_15 (PCOUT[15], qp_o_mux15); + buf b_pcout_out_16 (PCOUT[16], qp_o_mux16); + buf b_pcout_out_17 (PCOUT[17], qp_o_mux17); + buf b_pcout_out_18 (PCOUT[18], qp_o_mux18); + buf b_pcout_out_19 (PCOUT[19], qp_o_mux19); + buf b_pcout_out_20 (PCOUT[20], qp_o_mux20); + buf b_pcout_out_21 (PCOUT[21], qp_o_mux21); + buf b_pcout_out_22 (PCOUT[22], qp_o_mux22); + buf b_pcout_out_23 (PCOUT[23], qp_o_mux23); + buf b_pcout_out_24 (PCOUT[24], qp_o_mux24); + buf b_pcout_out_25 (PCOUT[25], qp_o_mux25); + buf b_pcout_out_26 (PCOUT[26], qp_o_mux26); + buf b_pcout_out_27 (PCOUT[27], qp_o_mux27); + buf b_pcout_out_28 (PCOUT[28], qp_o_mux28); + buf b_pcout_out_29 (PCOUT[29], qp_o_mux29); + buf b_pcout_out_30 (PCOUT[30], qp_o_mux30); + buf b_pcout_out_31 (PCOUT[31], qp_o_mux31); + buf b_pcout_out_32 (PCOUT[32], qp_o_mux32); + buf b_pcout_out_33 (PCOUT[33], qp_o_mux33); + buf b_pcout_out_34 (PCOUT[34], qp_o_mux34); + buf b_pcout_out_35 (PCOUT[35], qp_o_mux35); + buf b_pcout_out_36 (PCOUT[36], qp_o_mux36); + buf b_pcout_out_37 (PCOUT[37], qp_o_mux37); + buf b_pcout_out_38 (PCOUT[38], qp_o_mux38); + buf b_pcout_out_39 (PCOUT[39], qp_o_mux39); + buf b_pcout_out_40 (PCOUT[40], qp_o_mux40); + buf b_pcout_out_41 (PCOUT[41], qp_o_mux41); + buf b_pcout_out_42 (PCOUT[42], qp_o_mux42); + buf b_pcout_out_43 (PCOUT[43], qp_o_mux43); + buf b_pcout_out_44 (PCOUT[44], qp_o_mux44); + buf b_pcout_out_45 (PCOUT[45], qp_o_mux45); + buf b_pcout_out_46 (PCOUT[46], qp_o_mux46); + buf b_pcout_out_47 (PCOUT[47], qp_o_mux47); + + buf b_qb_o_mux_0 (qb_o_mux0, qb_o_mux[0]); + buf b_qb_o_mux_1 (qb_o_mux1, qb_o_mux[1]); + buf b_qb_o_mux_2 (qb_o_mux2, qb_o_mux[2]); + buf b_qb_o_mux_3 (qb_o_mux3, qb_o_mux[3]); + buf b_qb_o_mux_4 (qb_o_mux4, qb_o_mux[4]); + buf b_qb_o_mux_5 (qb_o_mux5, qb_o_mux[5]); + buf b_qb_o_mux_6 (qb_o_mux6, qb_o_mux[6]); + buf b_qb_o_mux_7 (qb_o_mux7, qb_o_mux[7]); + buf b_qb_o_mux_8 (qb_o_mux8, qb_o_mux[8]); + buf b_qb_o_mux_9 (qb_o_mux9, qb_o_mux[9]); + buf b_qb_o_mux_10 (qb_o_mux10, qb_o_mux[10]); + buf b_qb_o_mux_11 (qb_o_mux11, qb_o_mux[11]); + buf b_qb_o_mux_12 (qb_o_mux12, qb_o_mux[12]); + buf b_qb_o_mux_13 (qb_o_mux13, qb_o_mux[13]); + buf b_qb_o_mux_14 (qb_o_mux14, qb_o_mux[14]); + buf b_qb_o_mux_15 (qb_o_mux15, qb_o_mux[15]); + buf b_qb_o_mux_16 (qb_o_mux16, qb_o_mux[16]); + buf b_qb_o_mux_17 (qb_o_mux17, qb_o_mux[17]); + + buf b_bcout_0 (BCOUT[0], qb_o_mux0); + buf b_bcout_1 (BCOUT[1], qb_o_mux1); + buf b_bcout_2 (BCOUT[2], qb_o_mux2); + buf b_bcout_3 (BCOUT[3], qb_o_mux3); + buf b_bcout_4 (BCOUT[4], qb_o_mux4); + buf b_bcout_5 (BCOUT[5], qb_o_mux5); + buf b_bcout_6 (BCOUT[6], qb_o_mux6); + buf b_bcout_7 (BCOUT[7], qb_o_mux7); + buf b_bcout_8 (BCOUT[8], qb_o_mux8); + buf b_bcout_9 (BCOUT[9], qb_o_mux9); + buf b_bcout_10 (BCOUT[10], qb_o_mux10); + buf b_bcout_11 (BCOUT[11], qb_o_mux11); + buf b_bcout_12 (BCOUT[12], qb_o_mux12); + buf b_bcout_13 (BCOUT[13], qb_o_mux13); + buf b_bcout_14 (BCOUT[14], qb_o_mux14); + buf b_bcout_15 (BCOUT[15], qb_o_mux15); + buf b_bcout_16 (BCOUT[16], qb_o_mux16); + buf b_bcout_17 (BCOUT[17], qb_o_mux17); + + buf b_carryin (carryin_in, CARRYIN); + buf b_carryinsel_0 (carryinsel_in[0], CARRYINSEL[0]); + buf b_carryinsel_1 (carryinsel_in[1], CARRYINSEL[1]); + buf b_cep (cep_in, CEP); + buf b_cea (cea_in, CEA); + buf b_ceb (ceb_in, CEB); + buf b_cec (cec_in, CEC); + buf b_cecarryin (cecarryin_in, CECARRYIN); + buf b_cecinsub (cecinsub_in, CECINSUB); + buf b_cectrl (cectrl_in, CECTRL); + buf b_cem (cem_in, CEM); + buf b_clk (clk_in, CLK); + buf b_gsr (gsr_in, GSR); + + buf b_pcin_0 (pcin_in[0], PCIN[0]); + buf b_pcin_1 (pcin_in[1], PCIN[1]); + buf b_pcin_2 (pcin_in[2], PCIN[2]); + buf b_pcin_3 (pcin_in[3], PCIN[3]); + buf b_pcin_4 (pcin_in[4], PCIN[4]); + buf b_pcin_5 (pcin_in[5], PCIN[5]); + buf b_pcin_6 (pcin_in[6], PCIN[6]); + buf b_pcin_7 (pcin_in[7], PCIN[7]); + buf b_pcin_8 (pcin_in[8], PCIN[8]); + buf b_pcin_9 (pcin_in[9], PCIN[9]); + buf b_pcin_10 (pcin_in[10], PCIN[10]); + buf b_pcin_11 (pcin_in[11], PCIN[11]); + buf b_pcin_12 (pcin_in[12], PCIN[12]); + buf b_pcin_13 (pcin_in[13], PCIN[13]); + buf b_pcin_14 (pcin_in[14], PCIN[14]); + buf b_pcin_15 (pcin_in[15], PCIN[15]); + buf b_pcin_16 (pcin_in[16], PCIN[16]); + buf b_pcin_17 (pcin_in[17], PCIN[17]); + buf b_pcin_18 (pcin_in[18], PCIN[18]); + buf b_pcin_19 (pcin_in[19], PCIN[19]); + buf b_pcin_20 (pcin_in[20], PCIN[20]); + buf b_pcin_21 (pcin_in[21], PCIN[21]); + buf b_pcin_22 (pcin_in[22], PCIN[22]); + buf b_pcin_23 (pcin_in[23], PCIN[23]); + buf b_pcin_24 (pcin_in[24], PCIN[24]); + buf b_pcin_25 (pcin_in[25], PCIN[25]); + buf b_pcin_26 (pcin_in[26], PCIN[26]); + buf b_pcin_27 (pcin_in[27], PCIN[27]); + buf b_pcin_28 (pcin_in[28], PCIN[28]); + buf b_pcin_29 (pcin_in[29], PCIN[29]); + buf b_pcin_30 (pcin_in[30], PCIN[30]); + buf b_pcin_31 (pcin_in[31], PCIN[31]); + buf b_pcin_32 (pcin_in[32], PCIN[32]); + buf b_pcin_33 (pcin_in[33], PCIN[33]); + buf b_pcin_34 (pcin_in[34], PCIN[34]); + buf b_pcin_35 (pcin_in[35], PCIN[35]); + buf b_pcin_36 (pcin_in[36], PCIN[36]); + buf b_pcin_37 (pcin_in[37], PCIN[37]); + buf b_pcin_38 (pcin_in[38], PCIN[38]); + buf b_pcin_39 (pcin_in[39], PCIN[39]); + buf b_pcin_40 (pcin_in[40], PCIN[40]); + buf b_pcin_41 (pcin_in[41], PCIN[41]); + buf b_pcin_42 (pcin_in[42], PCIN[42]); + buf b_pcin_43 (pcin_in[43], PCIN[43]); + buf b_pcin_44 (pcin_in[44], PCIN[44]); + buf b_pcin_45 (pcin_in[45], PCIN[45]); + buf b_pcin_46 (pcin_in[46], PCIN[46]); + buf b_pcin_47 (pcin_in[47], PCIN[47]); + + buf b_opmode_0 (opmode_in[0], OPMODE[0]); + buf b_opmode_1 (opmode_in[1], OPMODE[1]); + buf b_opmode_2 (opmode_in[2], OPMODE[2]); + buf b_opmode_3 (opmode_in[3], OPMODE[3]); + buf b_opmode_4 (opmode_in[4], OPMODE[4]); + buf b_opmode_5 (opmode_in[5], OPMODE[5]); + buf b_opmode_6 (opmode_in[6], OPMODE[6]); + + buf b_rstp (rstp_in, RSTP); + buf b_rsta (rsta_in, RSTA); + buf b_rstb (rstb_in, RSTB); + buf b_rstcarryin (rstcarryin_in, RSTCARRYIN); + buf b_rstc (rstc_in, RSTC); + buf b_rstctrl (rstctrl_in, RSTCTRL); + buf b_rstm (rstm_in, RSTM); + + buf b_bcin_0 (bcin_in[0], BCIN[0]); + buf b_bcin_1 (bcin_in[1], BCIN[1]); + buf b_bcin_2 (bcin_in[2], BCIN[2]); + buf b_bcin_3 (bcin_in[3], BCIN[3]); + buf b_bcin_4 (bcin_in[4], BCIN[4]); + buf b_bcin_5 (bcin_in[5], BCIN[5]); + buf b_bcin_6 (bcin_in[6], BCIN[6]); + buf b_bcin_7 (bcin_in[7], BCIN[7]); + buf b_bcin_8 (bcin_in[8], BCIN[8]); + buf b_bcin_9 (bcin_in[9], BCIN[9]); + buf b_bcin_10 (bcin_in[10], BCIN[10]); + buf b_bcin_11 (bcin_in[11], BCIN[11]); + buf b_bcin_12 (bcin_in[12], BCIN[12]); + buf b_bcin_13 (bcin_in[13], BCIN[13]); + buf b_bcin_14 (bcin_in[14], BCIN[14]); + buf b_bcin_15 (bcin_in[15], BCIN[15]); + buf b_bcin_16 (bcin_in[16], BCIN[16]); + buf b_bcin_17 (bcin_in[17], BCIN[17]); + + buf b_subtract (subtract_in, SUBTRACT); + + buf b_a_0 (a_in[0], A[0]); + buf b_a_1 (a_in[1], A[1]); + buf b_a_2 (a_in[2], A[2]); + buf b_a_3 (a_in[3], A[3]); + buf b_a_4 (a_in[4], A[4]); + buf b_a_5 (a_in[5], A[5]); + buf b_a_6 (a_in[6], A[6]); + buf b_a_7 (a_in[7], A[7]); + buf b_a_8 (a_in[8], A[8]); + buf b_a_9 (a_in[9], A[9]); + buf b_a_10 (a_in[10], A[10]); + buf b_a_11 (a_in[11], A[11]); + buf b_a_12 (a_in[12], A[12]); + buf b_a_13 (a_in[13], A[13]); + buf b_a_14 (a_in[14], A[14]); + buf b_a_15 (a_in[15], A[15]); + buf b_a_16 (a_in[16], A[16]); + buf b_a_17 (a_in[17], A[17]); + + buf b_b_0 (b_in[0], B[0]); + buf b_b_1 (b_in[1], B[1]); + buf b_b_2 (b_in[2], B[2]); + buf b_b_3 (b_in[3], B[3]); + buf b_b_4 (b_in[4], B[4]); + buf b_b_5 (b_in[5], B[5]); + buf b_b_6 (b_in[6], B[6]); + buf b_b_7 (b_in[7], B[7]); + buf b_b_8 (b_in[8], B[8]); + buf b_b_9 (b_in[9], B[9]); + buf b_b_10 (b_in[10], B[10]); + buf b_b_11 (b_in[11], B[11]); + buf b_b_12 (b_in[12], B[12]); + buf b_b_13 (b_in[13], B[13]); + buf b_b_14 (b_in[14], B[14]); + buf b_b_15 (b_in[15], B[15]); + buf b_b_16 (b_in[16], B[16]); + buf b_b_17 (b_in[17], B[17]); + + buf b_c_0 (c_in[0], C[0]); + buf b_c_1 (c_in[1], C[1]); + buf b_c_2 (c_in[2], C[2]); + buf b_c_3 (c_in[3], C[3]); + buf b_c_4 (c_in[4], C[4]); + buf b_c_5 (c_in[5], C[5]); + buf b_c_6 (c_in[6], C[6]); + buf b_c_7 (c_in[7], C[7]); + buf b_c_8 (c_in[8], C[8]); + buf b_c_9 (c_in[9], C[9]); + buf b_c_10 (c_in[10], C[10]); + buf b_c_11 (c_in[11], C[11]); + buf b_c_12 (c_in[12], C[12]); + buf b_c_13 (c_in[13], C[13]); + buf b_c_14 (c_in[14], C[14]); + buf b_c_15 (c_in[15], C[15]); + buf b_c_16 (c_in[16], C[16]); + buf b_c_17 (c_in[17], C[17]); + buf b_c_18 (c_in[18], C[18]); + buf b_c_19 (c_in[19], C[19]); + buf b_c_20 (c_in[20], C[20]); + buf b_c_21 (c_in[21], C[21]); + buf b_c_22 (c_in[22], C[22]); + buf b_c_23 (c_in[23], C[23]); + buf b_c_24 (c_in[24], C[24]); + buf b_c_25 (c_in[25], C[25]); + buf b_c_26 (c_in[26], C[26]); + buf b_c_27 (c_in[27], C[27]); + buf b_c_28 (c_in[28], C[28]); + buf b_c_29 (c_in[29], C[29]); + buf b_c_30 (c_in[30], C[30]); + buf b_c_31 (c_in[31], C[31]); + buf b_c_32 (c_in[32], C[32]); + buf b_c_33 (c_in[33], C[33]); + buf b_c_34 (c_in[34], C[34]); + buf b_c_35 (c_in[35], C[35]); + buf b_c_36 (c_in[36], C[36]); + buf b_c_37 (c_in[37], C[37]); + buf b_c_38 (c_in[38], C[38]); + buf b_c_39 (c_in[39], C[39]); + buf b_c_40 (c_in[40], C[40]); + buf b_c_41 (c_in[41], C[41]); + buf b_c_42 (c_in[42], C[42]); + buf b_c_43 (c_in[43], C[43]); + buf b_c_44 (c_in[44], C[44]); + buf b_c_45 (c_in[45], C[45]); + buf b_c_46 (c_in[46], C[46]); + buf b_c_47 (c_in[47], C[47]); + + + +//*** GSR pin + always @(gsr_in) begin + if (gsr_in) begin + assign qcarryin_o_reg1 = 1'b0; + assign qcarryinsel_o_reg1 = 2'b0; + assign qopmode_o_reg1 = 7'b0; + assign qa_o_reg1 = 18'b0; + assign qa_o_reg2 = 18'b0; + assign qb_o_reg1 = 18'b0; + assign qb_o_reg2 = 18'b0; + assign qc_o_reg1 = 48'b0; + assign qp_o_reg1 = 48'b0; + assign qmult_o_reg1 = 36'b0; + assign qsubtract_o_reg1 = 1'b0; + end + else begin + deassign qcarryin_o_reg1; + deassign qcarryinsel_o_reg1; + deassign qopmode_o_reg1; + deassign qa_o_reg1; + deassign qa_o_reg2; + deassign qb_o_reg1; + deassign qb_o_reg2; + deassign qc_o_reg1; + deassign qp_o_reg1; + deassign qmult_o_reg1; + deassign qsubtract_o_reg1; + end + end + + + initial begin + + add_flag <= 1; + invalid_opmode <= 1; + + case (LEGACY_MODE) + + "NONE", "MULT18X18" : ; + "MULT18X18S" : if (MREG == 0) begin + $display("Attribute Syntax Error : The attribute LEGACY_MODE on DSP48 instance %m is set to %s. This requires attribute MREG to be set to 1.", LEGACY_MODE); + $finish; + end + default : begin + $display("Attribute Syntax Error : The attribute LEGACY_MODE on DSP48 instance %m is set to %s. Legal values for this attribute are NONE, MULT18X18 or MULT18X18S.", LEGACY_MODE); + $finish; + end + + endcase + end + + +//*** Input register C with 1 level deep of register + + always @(posedge clk_in) begin + if (rstc_in) + qc_o_reg1 <= 48'b0; + else if (cec_in) + qc_o_reg1 <= c_in; + end + + always @(c_in or qc_o_reg1) begin + case (CREG) + 0 : qc_o_mux <= c_in; + 1 : qc_o_mux <= qc_o_reg1; + default : begin + $display("Attribute Syntax Error : The attribute CREG on DSP48 instance %m is set to %d. Legal values for this attribute are 0 or 1.", CREG); + $finish; + end + endcase + end + + +//*** Input register B with 2 level deep of registers + + always @(bcin_in or b_in) begin + case (B_INPUT) + "DIRECT" : b_o_mux <= b_in; + "CASCADE" : b_o_mux <= bcin_in; + default : begin + $display("Attribute Syntax Error : The attribute B_INPUT on DSP48 instance %m is set to %s. Legal values for this attribute are DIRECT or CASCADE.", B_INPUT); + $finish; + end + endcase + end + + always @(posedge clk_in) begin + if (rstb_in) begin + qb_o_reg1 <= 18'b0; + qb_o_reg2 <= 18'b0; + end + else if (ceb_in) begin + qb_o_reg1 <= b_o_mux; + qb_o_reg2 <= qb_o_reg1; + end + end + + always @(b_o_mux or qb_o_reg1 or qb_o_reg2) begin + case (BREG) + 0 : qb_o_mux <= b_o_mux; + 1 : qb_o_mux <= qb_o_reg1; + 2 : qb_o_mux <= qb_o_reg2; + default : begin + $display("Attribute Syntax Error : The attribute BREG on DSP48 instance %m is set to %d. Legal values for this attribute are 0, 1 or 2.", BREG); + $finish; + end + endcase + end + + +//*** Input register A with 2 level deep of registers + + always @(posedge clk_in) begin + if (rsta_in) begin + qa_o_reg1 <= 18'b0; + qa_o_reg2 <= 18'b0; + end + else if (cea_in) begin + qa_o_reg1 <= a_in; + qa_o_reg2 <= qa_o_reg1; + end + end + + always @(a_in or qa_o_reg1 or qa_o_reg2) begin + case (AREG) + 0 : qa_o_mux <= a_in; + 1 : qa_o_mux <= qa_o_reg1; + 2 : qa_o_mux <= qa_o_reg2; + default : begin + $display("Attribute Syntax Error : The attribute AREG on DSP48 instance %m is set to %d. Legal values for this attribute are 0, 1 or 2.", AREG); + $finish; + end + endcase + end + + +//*** 18x18 Multiplier + assign mult_o = {{18{qa_o_mux[17]}}, qa_o_mux} * {{18{qb_o_mux[17]}}, qb_o_mux}; + + always @(posedge clk_in) begin + if (rstm_in) begin + qmult_o_reg1 <= 36'b0; + end + else if (cem_in) begin + qmult_o_reg1 <= mult_o; + end + end + + always @(mult_o or qmult_o_reg1) begin + case (MREG) + 0 : qmult_o_mux <= mult_o; + 1 : qmult_o_mux <= qmult_o_reg1; + default : begin + $display("Attribute Syntax Error : The attribute MREG on DSP48 instance %m is set to %d. Legal values for this attribute are 0 or 1.", MREG); + $finish; + end + endcase + end + + +//*** X mux + + always @(qp_o_mux or qa_o_mux or qb_o_mux or qmult_o_mux or qopmode_o_mux) begin + case (qopmode_o_mux[1:0]) + 2'b00 : qx_o_mux <= 48'b0; + 2'b01 : qx_o_mux <= {{12{qmult_o_mux[35]}}, qmult_o_mux}; + 2'b10 : qx_o_mux <= qp_o_mux; + 2'b11 : qx_o_mux <= {{12{qa_o_mux[17]}}, qa_o_mux[17:0], qb_o_mux[17:0]}; + default : begin + end + endcase + end + + +//*** Y mux + + always @(qc_o_mux or qopmode_o_mux) begin + case (qopmode_o_mux[3:2]) + 2'b00 : qy_o_mux <= 48'b0; + 2'b01 : qy_o_mux <= 48'b0; + 2'b11 : qy_o_mux <= qc_o_mux; + default : begin + end + endcase + end + + +//*** Z mux + + always @(qp_o_mux or qc_o_mux or pcin_in or qopmode_o_mux) begin + case (qopmode_o_mux[6:4]) + 3'b000 : qz_o_mux <= 48'b0; + 3'b001 : qz_o_mux <= pcin_in; + 3'b010 : qz_o_mux <= qp_o_mux; + 3'b011 : qz_o_mux <= qc_o_mux; + 3'b101 : qz_o_mux <= {{17{pcin_in[47]}}, pcin_in[47:17]}; + 3'b110 : qz_o_mux <= {{17{qp_o_mux[47]}}, qp_o_mux[47:17]}; + default : begin + end + endcase + end + + + +//*** CarryInSel and OpMode with 1 level of register + always @(posedge clk_in) begin + if (rstctrl_in) begin + qcarryinsel_o_reg1 <= 2'b0; + qopmode_o_reg1 <= 7'b0; + end + else if (cectrl_in) begin + qcarryinsel_o_reg1 <= carryinsel_in; + qopmode_o_reg1 <= opmode_in; + end + end + + + always @(carryinsel_in or qcarryinsel_o_reg1) begin + case (CARRYINSELREG) + 0 : qcarryinsel_o_mux <= carryinsel_in; + 1 : qcarryinsel_o_mux <= qcarryinsel_o_reg1; + default : begin + $display("Attribute Syntax Error : The attribute CARRYINSELREG on DSP48 instance %m is set to %d. Legal values for this attribute are 0 or 1.", CARRYINSELREG); + $finish; + end + endcase + end + + + always @(opmode_in or qopmode_o_reg1) begin + case (OPMODEREG) + 0 : qopmode_o_mux <= opmode_in; + 1 : qopmode_o_mux <= qopmode_o_reg1; + default : begin + $display("Attribute Syntax Error : The attribute OPMODEREG on DSP48 instance %m is set to %d. Legal values for this attribute are 0 or 1.", OPMODEREG); + $finish; + end + endcase + end + + + +//*** Subtract with 1 level of register + always @(posedge clk_in) begin + if (rstctrl_in) + qsubtract_o_reg1 <= 1'b0; + else if (cecinsub_in) + qsubtract_o_reg1 <= subtract_in; + end + + + always @(subtract_in or qsubtract_o_reg1) begin + case (SUBTRACTREG) + 0 : qsubtract_o_mux <= subtract_in; + 1 : qsubtract_o_mux <= qsubtract_o_reg1; + default : begin + $display("Attribute Syntax Error : The attribute SUBTRACTREG on DSP48 instance %m is set to %d. Legal values for this attribute are 0 or 1.", SUBTRACTREG); + $finish; + end + endcase + end + + +//*** DRC for OPMODE + + always @(qopmode_o_mux or qcarryinsel_o_mux or qsubtract_o_mux or qz_o_mux or qx_o_mux or qy_o_mux or qcarryin_o_mux) begin + + if ($time > 100000) begin // no check at first 100ns + + case ({qopmode_o_mux, qcarryinsel_o_mux}) + + 9'b000000000 : deassign_xyz_mux; + 9'b000001000 : if (PREG != 1) display_invalid_opmode; else deassign_xyz_mux; +// CR 455601 eased the following drc + 9'b000001001 : if (PREG != 1) display_invalid_opmode; else deassign_xyz_mux; +// + + 9'b000001100 : deassign_xyz_mux; + 9'b000010100 : deassign_xyz_mux; + 9'b000110000 : deassign_xyz_mux; + 9'b000111000 : if (PREG != 1) display_invalid_opmode; else deassign_xyz_mux; + 9'b000111001 : if (PREG != 1) display_invalid_opmode; else deassign_xyz_mux; + 9'b000111100 : deassign_xyz_mux; + 9'b000111110 : deassign_xyz_mux; +// CR 479833 eased the following drc + 9'b000111111 : deassign_xyz_mux; +// + 9'b001000000 : deassign_xyz_mux; + 9'b001001000 : if (PREG != 1) display_invalid_opmode; else deassign_xyz_mux; + 9'b001001001 : if (PREG != 1) display_invalid_opmode; else deassign_xyz_mux; + 9'b001001100 : deassign_xyz_mux; + 9'b001001101 : deassign_xyz_mux; + 9'b001001110 : deassign_xyz_mux; + 9'b001010100 : deassign_xyz_mux; + 9'b001010101 : deassign_xyz_mux; + 9'b001010110 : deassign_xyz_mux; + 9'b001010111 : deassign_xyz_mux; + 9'b001110000 : deassign_xyz_mux; + 9'b001110001 : deassign_xyz_mux; + 9'b001111000 : if (PREG != 1) display_invalid_opmode; else deassign_xyz_mux; + 9'b001111001 : if (PREG != 1) display_invalid_opmode; else deassign_xyz_mux; + 9'b001111100 : deassign_xyz_mux; + 9'b001111101 : deassign_xyz_mux; + 9'b001111110 : deassign_xyz_mux; + 9'b010000000 : if (PREG != 1) display_invalid_opmode; else deassign_xyz_mux; + 9'b010001000 : if (PREG != 1) display_invalid_opmode; else deassign_xyz_mux; + 9'b010001100 : if (PREG != 1) display_invalid_opmode; else deassign_xyz_mux; + 9'b010001101 : if (PREG != 1) display_invalid_opmode; else deassign_xyz_mux; + 9'b010010100 : if (PREG != 1) display_invalid_opmode; else deassign_xyz_mux; + 9'b010010101 : if (PREG != 1) display_invalid_opmode; else deassign_xyz_mux; + 9'b010110000 : if (PREG != 1) display_invalid_opmode; else deassign_xyz_mux; + 9'b010110001 : if (PREG != 1) display_invalid_opmode; else deassign_xyz_mux; + 9'b010111000 : if (PREG != 1) display_invalid_opmode; else deassign_xyz_mux; + 9'b010111001 : if (PREG != 1) display_invalid_opmode; else deassign_xyz_mux; + 9'b010111100 : if (PREG != 1) display_invalid_opmode; else deassign_xyz_mux; + 9'b010111101 : if (PREG != 1) display_invalid_opmode; else deassign_xyz_mux; + 9'b010111110 : if (PREG != 1) display_invalid_opmode; else deassign_xyz_mux; + 9'b011000000 : deassign_xyz_mux; + 9'b011001000 : if (PREG != 1) display_invalid_opmode; else deassign_xyz_mux; + 9'b011001001 : if (PREG != 1) display_invalid_opmode; else deassign_xyz_mux; + 9'b011001100 : deassign_xyz_mux; + 9'b011001110 : deassign_xyz_mux; + 9'b011010100 : deassign_xyz_mux; + 9'b011010110 : if (MREG != 0) display_invalid_opmode_no_mreg; else deassign_xyz_mux; + 9'b011010111 : if (MREG != 1) display_invalid_opmode_mreg; else deassign_xyz_mux; + 9'b011110000 : deassign_xyz_mux; + 9'b011111000 : if (PREG != 1) display_invalid_opmode; else deassign_xyz_mux; + 9'b011111100 : deassign_xyz_mux; + 9'b011111101 : deassign_xyz_mux; + 9'b101000000 : deassign_xyz_mux; + 9'b101001000 : if (PREG != 1) display_invalid_opmode; else deassign_xyz_mux; + 9'b101001100 : deassign_xyz_mux; + 9'b101001101 : deassign_xyz_mux; + 9'b101001110 : deassign_xyz_mux; + 9'b101010100 : deassign_xyz_mux; + 9'b101010101 : deassign_xyz_mux; + 9'b101010110 : if (MREG != 0) display_invalid_opmode_no_mreg; else deassign_xyz_mux; + 9'b101010111 : if (MREG != 1) display_invalid_opmode_mreg; else deassign_xyz_mux; + 9'b101110000 : deassign_xyz_mux; + 9'b101110001 : deassign_xyz_mux; + 9'b101111000 : if (PREG != 1) display_invalid_opmode; else deassign_xyz_mux; + 9'b101111001 : if (PREG != 1) display_invalid_opmode; else deassign_xyz_mux; + 9'b101111100 : deassign_xyz_mux; + 9'b101111101 : deassign_xyz_mux; + 9'b101111110 : deassign_xyz_mux; + 9'b110000000 : if (PREG != 1) display_invalid_opmode; else deassign_xyz_mux; + 9'b110001000 : if (PREG != 1) display_invalid_opmode; else deassign_xyz_mux; + 9'b110001100 : if (PREG != 1) display_invalid_opmode; else deassign_xyz_mux; + 9'b110001101 : if (PREG != 1) display_invalid_opmode; else deassign_xyz_mux; + 9'b110010100 : if (PREG != 1) display_invalid_opmode; else deassign_xyz_mux; + 9'b110010101 : if (PREG != 1) display_invalid_opmode; else deassign_xyz_mux; + 9'b110110000 : if (PREG != 1) display_invalid_opmode; else deassign_xyz_mux; + 9'b110110001 : if (PREG != 1) display_invalid_opmode; else deassign_xyz_mux; + 9'b110111000 : if (PREG != 1) display_invalid_opmode; else deassign_xyz_mux; + 9'b110111001 : if (PREG != 1) display_invalid_opmode; else deassign_xyz_mux; + 9'b110111100 : if (PREG != 1) display_invalid_opmode; else deassign_xyz_mux; + 9'b110111101 : if (PREG != 1) display_invalid_opmode; else deassign_xyz_mux; + 9'b110111110 : if (PREG != 1) display_invalid_opmode; else deassign_xyz_mux; + default : begin + if (invalid_opmode) begin + + add_flag = 0; + invalid_opmode = 0; + assign qx_o_mux = 48'bx; + assign qy_o_mux = 48'bx; + assign qz_o_mux = 48'bx; + assign add_o = 48'bx; + $display("OPMODE Input Warning : The OPMODE %b to DSP48 instance %m is either invalid or the CARRYINSEL %b for that specific OPMODE is invalid at %.3f ns.", qopmode_o_mux, qcarryinsel_o_mux, $time/1000.0); + + end + end + + endcase // case(opmode_in) + + end // if ($time > 100000) + +// *** Adder + if (add_flag) begin + + if (qsubtract_o_mux == 1'b1) + + add_o = qz_o_mux - (qx_o_mux + qy_o_mux + qcarryin_o_mux); + + else if (qsubtract_o_mux == 1'b0) + + add_o = qz_o_mux + (qx_o_mux + qy_o_mux + qcarryin_o_mux); + + end // if (add_flag = 1) + + end // always @ (qopmode_o_mux) + + task deassign_xyz_mux; + begin + add_flag = 1; + invalid_opmode = 1; // reset invalid opmode + deassign qx_o_mux; + deassign qy_o_mux; + deassign qz_o_mux; + deassign add_o; + end + endtask // deassign_xyz_mux + + task display_invalid_opmode_no_mreg; + begin + if (invalid_opmode) begin + + add_flag = 0; + invalid_opmode = 0; + assign qx_o_mux = 48'bx; + assign qy_o_mux = 48'bx; + assign qz_o_mux = 48'bx; + assign add_o = 48'bx; + $display("OPMODE Input Warning : The OPMODE %b with CARRYINSEL %b to DSP48 instance %m at %.3f ns requires attribute MREG set to 0.", qopmode_o_mux, qcarryinsel_o_mux, $time/1000.0); + end + end + endtask // display_invalid_opmode_no_mreg + + task display_invalid_opmode_mreg; + begin + if (invalid_opmode) begin + add_flag = 0; + invalid_opmode = 0; + assign qx_o_mux = 48'bx; + assign qy_o_mux = 48'bx; + assign qz_o_mux = 48'bx; + assign add_o = 48'bx; + $display("OPMODE Input Warning : The OPMODE %b with CARRYINSEL %b to DSP48 instance %m at %.3f ns requires attribute MREG set to 1.", qopmode_o_mux, qcarryinsel_o_mux, $time/1000.0); + end + end + endtask // display_invalid_opmode_mreg + + task display_invalid_opmode; + begin + if (invalid_opmode) begin + add_flag = 0; + invalid_opmode = 0; + assign qx_o_mux = 48'bx; + assign qy_o_mux = 48'bx; + assign qz_o_mux = 48'bx; + assign add_o = 48'bx; + $display("OPMODE Input Warning : The OPMODE %b to DSP48 instance %m at %.3f ns requires attribute PREG set to 1.", qopmode_o_mux, $time/1000.0); + end + end + endtask // display_invalid_opmode + + +//*** CarryIn Mux and Register + always @(qa_o_mux[17] or qb_o_mux[17] or qopmode_o_mux[0] or qopmode_o_mux[1]) begin + case (qopmode_o_mux[0] && qopmode_o_mux[1]) + 1'b0 : carryin_o_mux2 <= qa_o_mux[17] ~^ qb_o_mux[17]; // xnor + 1'b1 : carryin_o_mux2 <= ~qa_o_mux[17]; + default : begin + end + endcase + end + + always @(carryin_in or qcarryin_o_reg1) begin + case (CARRYINREG) + 0 : qcarryin_o_mux1 <= carryin_in; + 1 : qcarryin_o_mux1 <= qcarryin_o_reg1; + default : begin + $display("Attribute Syntax Error : The attribute CARRYINREG on DSP48 instance %m is set to %d. Legal values for this attribute are 0 or 1.", CARRYINREG); + $finish; + end + endcase + end + + always @(posedge clk_in) begin + if (rstcarryin_in) + qcarryin_o_reg1 <= 1'b0; + else if (cecinsub_in) + qcarryin_o_reg1 <= carryin_in; + end + + always @(posedge clk_in) begin + if (rstcarryin_in) begin + qcarryin_o_reg3 <= 1'b0; + end + else if (cecarryin_in) begin + qcarryin_o_reg3 <= carryin_o_mux2; + end + end + + assign selp47 = (qopmode_o_mux[1] & ~qopmode_o_mux[0]) | qopmode_o_mux[5] | ~(qopmode_o_mux[6] | qopmode_o_mux[4]); + + always @(qp_o_mux[47] or pcin_in[47] or selp47) begin + case (selp47) + 1'b0 : carryin_o_mux4 <= ~pcin_in[47]; + 1'b1 : carryin_o_mux4 <= ~qp_o_mux[47]; + default : begin + end + endcase + end + + + always @(qcarryin_o_mux1 or carryin_o_mux2 or qcarryin_o_reg3 or carryin_o_mux4 or qcarryinsel_o_mux) begin + case (qcarryinsel_o_mux) + 2'b00 : qcarryin_o_mux <= qcarryin_o_mux1; + 2'b01 : qcarryin_o_mux <= carryin_o_mux4; + 2'b10 : qcarryin_o_mux <= carryin_o_mux2; + 2'b11 : qcarryin_o_mux <= qcarryin_o_reg3; + default : begin + end + endcase + end + + +//*** Output register P with 1 level of register + always @(posedge clk_in) begin + if (rstp_in) + qp_o_reg1 <= 48'b0; + else if (cep_in) + qp_o_reg1 <= add_o; + end + + always @(qp_o_reg1 or add_o) begin + case (PREG) + 0 : qp_o_mux <= add_o; + 1 : qp_o_mux <= qp_o_reg1; + default : begin + $display("Attribute Syntax Error : The attribute PREG on DSP48 instance %m is set to %d. Legal values for this attribute are 0 or 1.", PREG); + $finish; + end + endcase + end + + + specify + + (CLK *> P) = (100, 100); + (CLK *> PCOUT) = (100, 100); + (CLK *> BCOUT) = (100, 100); + specparam PATHPULSE$ = 0; + + endspecify + +endmodule // DSP48 diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/DSP48A.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/DSP48A.v new file mode 100644 index 0000000..6bb20cf --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/DSP48A.v @@ -0,0 +1,1354 @@ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2006 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Multifunctional, Cascadable, 48-bit Output Arithmetic Block +// /___/ /\ Filename : DSP48A.v +// \ \ / \ Timestamp : Thu Feb 23 17:09:20 PST 2006 +// \___\/\___\ +// +// Revision: +// 04/21/06 - Initial version. +// 12/21/06 - bcin_in width not declared. CR 430133 fix. +// 05/29/07 - Added wire declaration for internal signals +// 05/15/08 - CR 468871 Negative SetupHold fix. +// 06/24/08 - CR 475318 fixed unintentional buffer removal in unisim model +// 07/08/08 - CR 473297 and 475997 fix -- removed input buffers that were causing NCSIM failures when sdf was backannotated +// End Revision + +`timescale 1 ps / 1 ps + +module DSP48A (BCOUT, CARRYOUT, P, PCOUT, A, B, C, CARRYIN, CEA, CEB, CEC, CECARRYIN, CED, CEM, CEOPMODE, CEP, CLK, D, OPMODE, PCIN, RSTA, RSTB, RSTC, RSTCARRYIN, RSTD, RSTM, RSTOPMODE, RSTP); + + parameter integer A0REG = 0; + parameter integer A1REG = 1; + parameter integer B0REG = 0; + parameter integer B1REG = 1; + parameter integer CARRYINREG = 1; + parameter CARRYINSEL = "CARRYIN"; + parameter integer CREG = 1; + parameter integer DREG = 1; + parameter integer MREG = 1; + parameter integer OPMODEREG = 1; + parameter integer PREG = 1; + parameter RSTTYPE = "SYNC"; + + + output [17:0] BCOUT; + output CARRYOUT; + output [47:0] P; + output [47:0] PCOUT; + + input [17:0] A; + input [17:0] B; + + input [47:0] C; + input CARRYIN; + input CEA; + input CEB; + input CEC; + input CECARRYIN; + input CED; + input CEM; + input CEOPMODE; + input CEP; + input CLK; + input [17:0] D; + input [7:0] OPMODE; + input [47:0] PCIN; + input RSTA; + input RSTB; + input RSTC; + input RSTCARRYIN; + input RSTD; + input RSTM; + input RSTOPMODE; + input RSTP; + + tri0 GSR = glbl.GSR; + +//------------------- constants ------------------------- + localparam MAX_BCOUT = 18; + localparam MAX_P = 48; + localparam MAX_PCOUT = 48; + + localparam MAX_A = 18; + localparam MAX_B = 18; + localparam MAX_BCIN = 18; + localparam MAX_C = 48; + localparam MAX_D = 18; + localparam MAX_OPMODE = 8; + localparam MAX_PCIN = 48; + + + localparam MAX_MULT_A = 18; + localparam MAX_MULT_B = 18; + localparam MAX_MULT_AB = 36; + localparam MAX_MUX_XZ = 48; + + localparam MSB_BCOUT = MAX_BCOUT - 1; + localparam MSB_P = MAX_P - 1; + localparam MSB_PCOUT = MAX_PCOUT - 1; + + localparam MSB_A = MAX_A - 1; + localparam MSB_B = MAX_B - 1; + localparam MSB_BCIN = MAX_BCIN - 1; + localparam MSB_C = MAX_C - 1; + localparam MSB_D = MAX_D - 1; + localparam MSB_OPMODE = MAX_OPMODE - 1; + localparam MSB_PCIN = MAX_PCIN - 1; + + localparam MSB_MULT_A = MAX_MULT_A - 1; + localparam MSB_MULT_B = MAX_MULT_B - 1; + + localparam MSB_MULT_AB = MAX_MULT_AB - 1; +//-------------------------------------------------------------- + reg [MSB_A:0] qa_o_mux, qa_o_reg1, qa_o_reg2; + reg [MSB_B:0] b_o_mux, qb_o_mux0 = 18'b0, qb_o_mux = 18'b0, qb_o_reg1, qb_o_reg2, preadd, mux_preadd; + reg [MSB_C:0] qc_o_mux, qc_o_reg1; + + reg carryinsel_attr, carryinsel_o_mux; + reg qcarryin_o_mux, qcarryin_o_reg1; + reg carryout_o; + + reg [MSB_MULT_AB:0] qmult_o_mux, qmult_o_reg1; + + reg [MSB_D:0] qd_o_mux, qd_o_reg1; + + reg [MSB_P:0] qp_o_mux = 48'b0, qp_o_reg1; + reg [(MAX_MUX_XZ-1):0] qx_o_mux, qz_o_mux; + reg [MSB_OPMODE:0] qopmode_o_mux, qopmode_o_reg1; + + + reg invalid_opmode, add_flag, rst_async_flag = 0; + reg [(MAX_MUX_XZ-1):0] add_o; + + wire [MSB_A:0] a_in; + wire [MSB_B:0] b_in; + wire [MSB_BCIN:0] bcin_in; + wire [MSB_C:0] c_in; + wire [MSB_D:0] d_in; + wire [MSB_MULT_AB:0] mult_o; + wire [MSB_OPMODE:0] opmode_in; + wire [MSB_PCIN:0] pcin_in; + + wire carryout_x_o; + wire carryin_in; + wire cea_in; + wire ceb_in; + wire cec_in; + wire cecarryin_in; + wire ced_in; + wire cem_in; + wire ceopmode_in; + wire cep_in; + wire clk_in; + wire rsta_in; + wire rstb_in; + wire rstc_in; + wire rstcarryin_in; + wire rstd_in; + wire rstm_in; + wire rstopmode_in; + wire rstp_in; + wire gsr_in; + +//---------------------------------------------------------------------- +//------------------------ Output Ports ------------------------------ +//---------------------------------------------------------------------- + buf b_bcout_o[MSB_BCOUT:0] (BCOUT, qb_o_mux); + buf b_carryout (CARRYOUT, carryout_x_o); + buf b_p_o[MSB_P:0] (P, qp_o_mux); + buf b_pcout_o[MSB_PCOUT:0] (PCOUT, qp_o_mux); + +//----------------------------------------------------- +//----------- Inputs -------------------------------- +//----------------------------------------------------- + buf b_a[MSB_A:0] (a_in, A); + buf b_b[MSB_B:0] (b_in, B); + buf b_c[MSB_C:0] (c_in, C); + buf b_carryin (carryin_in, CARRYIN); + buf b_cea (cea_in, CEA); + buf b_ceb (ceb_in, CEB); + buf b_cec (cec_in, CEC); + buf b_cecarryin (cecarryin_in, CECARRYIN); + buf b_ced (ced_in, CED); + buf b_cem (cem_in, CEM); + buf b_ceopmode (ceopmode_in, CEOPMODE); + buf b_cep (cep_in, CEP); + buf b_clk (clk_in, CLK); + buf b_d[MSB_D:0] (d_in, D); + buf b_opmode[MSB_OPMODE:0] (opmode_in, OPMODE); + buf b_pcin[MSB_PCIN:0] (pcin_in, PCIN); + buf b_rsta (rsta_in, RSTA); + buf b_rstb (rstb_in, RSTB); + buf b_rstc (rstc_in, RSTC); + buf b_rstcarryin (rstcarryin_in, RSTCARRYIN); + buf b_rstd (rstd_in, RSTD); + buf b_rstm (rstm_in, RSTM); + buf b_rstopmode (rstopmode_in, RSTOPMODE); + buf b_rstp (rstp_in, RSTP); + + + buf b_gsr (gsr_in, GSR); + +//*** GSR pin + always @(gsr_in) begin + if (gsr_in) begin + assign qa_o_reg1 = 18'b0; + assign qa_o_reg2 = 18'b0; + assign qb_o_reg1 = 18'b0; + assign qb_o_reg2 = 18'b0; + assign qc_o_reg1 = 48'b0; + assign qd_o_reg1 = 18'b0; + assign qmult_o_reg1 = 36'b0; + assign qopmode_o_reg1 = 8'b0; + assign qcarryin_o_reg1 = 1'b0; + assign qp_o_reg1 = 48'b0; + + end + else begin + deassign qa_o_reg1; + deassign qa_o_reg2; + deassign qb_o_reg1; + deassign qb_o_reg2; + deassign qc_o_reg1; + deassign qd_o_reg1; + deassign qmult_o_reg1; + deassign qopmode_o_reg1; + deassign qcarryin_o_reg1; + deassign qp_o_reg1; + end + end + +//---------------------------------------------------- +//*** Initialization +//---------------------------------------------------- + + + + initial begin + +//-------- A0REG/A1REG & B0REG/B1REG ------ + + if ((A0REG != 0) && (A0REG != 1)) + begin + $display("Attribute Syntax Error : The attribute A0REG on DSP48A instance %m is set to %d. Legal values for this attribute are 0 or 1.", A0REG); + $finish; + end + + if ((A1REG != 0) && (A1REG != 1)) + begin + $display("Attribute Syntax Error : The attribute A1REG on DSP48A instance %m is set to %d. Legal values for this attribute are 0 or 1.", A1REG); + $finish; + end + + if ((B0REG != 0) && (B0REG != 1)) + begin + $display("Attribute Syntax Error : The attribute B0REG on DSP48A instance %m is set to %d. Legal values for this attribute are 0 or 1.", B0REG); + $finish; + end + + if ((B1REG != 0) && (B1REG != 1)) + begin + $display("Attribute Syntax Error : The attribute B1REG on DSP48A instance %m is set to %d. Legal values for this attribute are 0 or 1.", B1REG); + $finish; + end + +//-------- RSTTYPE ------ + + case (RSTTYPE) + "SYNC": rst_async_flag = 0; + "ASYNC": rst_async_flag = 1; + default : begin + $display("Attribute Syntax Error : The attribute RSTTYPE on DSP48A instance %m is set to %s. Legal values for this attribute are SYNC or ASYNC.", RSTTYPE); + $finish; + end + endcase + +//-------- CARRYINSEL ------ + + case (CARRYINSEL) + "CARRYIN" : carryinsel_attr <= 1'b0; + "OPMODE5" : carryinsel_attr <= 1'b1; + default : begin + $display("Attribute Syntax Error : The attribute CARRYINSEL on DSP48A instance %m is set to %s. Legal valuesfor this attribute are CARRYIN or OPMODE5.", CARRYINSEL); + $finish; + end + endcase + + add_flag <= 1; + invalid_opmode <= 1; + + end + + + +//---------------------------------------------------- +//*** Input register A with 2 level deep of registers +//---------------------------------------------------- +// Asynchronous Operation + always @(posedge clk_in, posedge rsta_in) begin + if(rst_async_flag) begin + if(rsta_in) begin + qa_o_reg1 <= 18'b0; + qa_o_reg2 <= 18'b0; + end // if rsta_in + else if(cea_in) begin + qa_o_reg1 <= a_in; + qa_o_reg2 <= qa_o_reg1; + end // cea_in + end // if rst_async_flg + end // always + +// Synchronous Operation + always @(posedge clk_in) begin + if(!rst_async_flag) begin + if(rsta_in) begin + qa_o_reg1 <= 18'b0; + qa_o_reg2 <= 18'b0; + end // if rsta_in + else if(cea_in) begin + qa_o_reg1 <= a_in; + qa_o_reg2 <= qa_o_reg1; + end // cea_in + end // if rst_async_flg + end // always + + always @(a_in or qa_o_reg1 or qa_o_reg2) begin + if((A0REG==0) && (A1REG==0)) + qa_o_mux <= a_in; + else if(((A0REG==0) && (A1REG==1)) || ((A0REG==1) && (A1REG==0))) + qa_o_mux <= qa_o_reg1; + else if((A0REG==1) && (A1REG==1)) + qa_o_mux <= qa_o_reg2; + end + + +//---------------------------------------------------- +//*** Input register B with 2 level deep of registers +//---------------------------------------------------- +// Asynchronous Operation + always @(posedge clk_in, posedge rstb_in) begin + if(rst_async_flag) begin + if(rstb_in) begin + qb_o_reg1 <= 18'b0; + qb_o_reg2 <= 18'b0; + end // if rstb_in + else if(ceb_in) begin + qb_o_reg1 <= b_in; + qb_o_reg2 <= mux_preadd; + end // ceb_in + end // if rst_async_flg + end // always + +// Synchronous Operation + always @(posedge clk_in) begin + if(!rst_async_flag) begin + if(rstb_in) begin + qb_o_reg1 <= 18'b0; + qb_o_reg2 <= 18'b0; + end // if rstb_in + else if(ceb_in) begin + qb_o_reg1 <= b_in; + qb_o_reg2 <= mux_preadd; + end // ceb_in + end // if rst_async_flg + end // always + + +//*** PRE_ADD + always @(qopmode_o_mux, b_in, qd_o_mux, qb_o_reg1) begin + if(((B0REG==0) && (B1REG==0)) || ((B0REG==0) && (B1REG==1))) begin + qb_o_mux0 = b_in; + if(qopmode_o_mux[6] == 0) + preadd = (qd_o_mux + b_in); + else if(qopmode_o_mux[6] == 1) + preadd = (qd_o_mux - b_in); + end + else if(((B0REG==1) && (B1REG==1)) || ((B0REG==1) && (B1REG==0))) begin + qb_o_mux0 = qb_o_reg1; + if(qopmode_o_mux[6] == 0) + preadd = (qd_o_mux + qb_o_reg1); + else if(qopmode_o_mux[6] == 1) + preadd = (qd_o_mux - qb_o_reg1); + end + end + + always @(qopmode_o_mux[4], preadd, qb_o_mux0) begin + if(qopmode_o_mux[4] == 1) + mux_preadd = preadd; + else if(qopmode_o_mux[4] == 0) + mux_preadd = qb_o_mux0; + end + + always @(mux_preadd, qb_o_reg2) begin + if(((B0REG==0) && (B1REG==0)) || ((B0REG==1) && (B1REG==0))) + qb_o_mux = mux_preadd; + else if(((B0REG==1) && (B1REG==1)) || ((B0REG==0) && (B1REG==1))) + qb_o_mux = qb_o_reg2; + end + + +//---------------------------------------------------- +//*** Input register C with 1 level deep of registers +//---------------------------------------------------- +// Asynchronous Operation + always @(posedge clk_in, posedge rstc_in) begin + if(rst_async_flag) begin + if(rstc_in) begin + qc_o_reg1 <= 18'b0; + end // if rstc_in + else if(cec_in) begin + qc_o_reg1 <= c_in; + end // cec_in + end // if rst_async_flg + end // always + +// Synchronous Operation + always @(posedge clk_in) begin + if(!rst_async_flag) begin + if(rstc_in) begin + qc_o_reg1 <= 18'b0; + end // if rstc_in + else if(cec_in) begin + qc_o_reg1 <= c_in; + end // cec_in + end // if rst_async_flg + end // always + + always @(c_in or qc_o_reg1) begin + case (CREG) + 0 : qc_o_mux <= c_in; + 1 : qc_o_mux <= qc_o_reg1; + default : begin + $display("Attribute Syntax Error : The attribute CREG on DSP48A instance %m is set to %d. Legal values for this attribute are 0 or 1.", CREG); + $finish; + end + endcase + end + +//---------------------------------------------------- +//*** Input register D with 1 level deep of registers +//---------------------------------------------------- +// Asynchronous Operation + always @(posedge clk_in, posedge rstd_in) begin + if(rst_async_flag) begin + if(rstd_in) begin + qd_o_reg1 <= 18'b0; + end // if rstd_in + else if(ced_in) begin + qd_o_reg1 <= d_in; + end // ced_in + end // if rst_async_flg + end // always + +// Synchronous Operation + always @(posedge clk_in) begin + if(!rst_async_flag) begin + if(rstd_in) begin + qd_o_reg1 <= 18'b0; + end // if rstd_in + else if(ced_in) begin + qd_o_reg1 <= d_in; + end // ced_in + end // if rst_async_flg + end // always + + always @(d_in or qd_o_reg1) begin + case (DREG) + 0 : qd_o_mux <= d_in; + 1 : qd_o_mux <= qd_o_reg1; + default : begin + $display("Attribute Syntax Error : The attribute DREG on DSP48A instance %m is set to %d. Legal values for this attribute are 0 or 1.", DREG); + $finish; + end + endcase + end + + +//---------------------------------------------------- +//*** 18x18 Multiplier +//---------------------------------------------------- + assign mult_o = {{MAX_MULT_A{qa_o_mux[MSB_MULT_A]}}, qa_o_mux} * {{MAX_MULT_B{qb_o_mux[MSB_MULT_B]}}, qb_o_mux}; + +// Asynchronous Operation + always @(posedge clk_in, posedge rstm_in) begin + if(rst_async_flag) begin + if(rstm_in) begin + qmult_o_reg1 <= 36'b0; + end // if rstm_in + else if(cem_in) begin + qmult_o_reg1 <= mult_o; + end // cem_in + end // if rst_async_flg + end // always + +// Synchronous Operation + always @(posedge clk_in) begin + if(!rst_async_flag) begin + if(rstm_in) begin + qmult_o_reg1 <= 36'b0; + end // if rstm_in + else if(cem_in) begin + qmult_o_reg1 <= mult_o; + end // cem_in + end // if rst_async_flg + end // always + + always @(mult_o or qmult_o_reg1) begin + case (MREG) + 0 : qmult_o_mux <= mult_o; + 1 : qmult_o_mux <= qmult_o_reg1; + default : begin + $display("Attribute Syntax Error : The attribute MREG on DSP48A instance %m is set to %d. Legal values for this attribute are 0 or 1.", MREG); + $finish; + end + endcase + end + + +//*** X mux + + always @(qp_o_mux or qa_o_mux or qd_o_mux or qb_o_mux or qmult_o_mux or qopmode_o_mux) begin + case (qopmode_o_mux[1:0]) + 2'b00 : qx_o_mux <= 48'b0; + 2'b01 : qx_o_mux <= {{12{qmult_o_mux[MSB_MULT_AB]}}, qmult_o_mux}; + 2'b10 : qx_o_mux <= qp_o_mux; + 2'b11 : qx_o_mux <= {qd_o_mux[11:0], qa_o_mux[17:0], qb_o_mux[17:0]}; + default : begin + end + endcase + end + + +//*** Z mux + + always @(qp_o_mux or qc_o_mux or pcin_in or qopmode_o_mux) begin + case (qopmode_o_mux[3:2]) + 3'b00 : qz_o_mux <= 48'b0; + 3'b01 : qz_o_mux <= pcin_in; + 3'b10 : qz_o_mux <= qp_o_mux; + 3'b11 : qz_o_mux <= qc_o_mux; + default : begin + end + endcase + end + + +//---------------------------------------------------- +//*** CarryIn 1 level of register +//---------------------------------------------------- + always @(qopmode_o_mux[5], carryin_in) begin + case (CARRYINSEL) + "CARRYIN" : carryinsel_o_mux <= carryin_in; + "OPMODE5" : carryinsel_o_mux <= qopmode_o_mux[5]; + default : begin + $display("Attribute Syntax Error : The attribute CARRYINSEL on DSP48A instance %m is set to %s. Legal values for this attribute are CARRYIN or OPMODE5.", CARRYINSEL); + $finish; + end + endcase + end + +// Asynchronous Operation + always @(posedge clk_in, posedge rstcarryin_in) begin + if(rst_async_flag) begin + if(rstcarryin_in) begin + qcarryin_o_reg1 <= 1'b0; + end // if rstcarryin_in + else if(cecarryin_in) begin + qcarryin_o_reg1 <= carryinsel_o_mux; + end // cecarryin_in + end // if rst_async_flg + end // always + +// Synchronous Operation + always @(posedge clk_in) begin + if (rstcarryin_in) begin + qcarryin_o_reg1 <= 1'b0; + end + else if (cecarryin_in) begin + qcarryin_o_reg1 <= carryinsel_o_mux; + end + end + + + always @(carryinsel_o_mux or qcarryin_o_reg1) begin + case (CARRYINREG) + 0 : qcarryin_o_mux <= carryinsel_o_mux; + 1 : qcarryin_o_mux <= qcarryin_o_reg1; + default : begin + $display("Attribute Syntax Error : The attribute CARRYINREG on DSP48A instance %m is set to %d. Legal values for this attribute are 0 or 1.", CARRYINREG); + $finish; + end + endcase + end + + +//---------------------------------------------------- +//*** Opmode 1 level of register +//---------------------------------------------------- +// Asynchronous Operation + always @(posedge clk_in, posedge rstopmode_in) begin + if(rst_async_flag) begin + if(rstopmode_in) begin + qopmode_o_reg1 <= 8'b0; + end // if rstopmode_in + else if(ceopmode_in) begin + qopmode_o_reg1 <= opmode_in; + end // ceopmode_in + end // if rst_async_flg + end // always + +// Synchronous Operation + always @(posedge clk_in) begin + if (rstopmode_in) begin + qopmode_o_reg1 <= 8'b0; + end + else if (ceopmode_in) begin + qopmode_o_reg1 <= opmode_in; + end + end + + + always @(opmode_in or qopmode_o_reg1) begin + case (OPMODEREG) + 0 : qopmode_o_mux <= opmode_in; + 1 : qopmode_o_mux <= qopmode_o_reg1; + default : begin + $display("Attribute Syntax Error : The attribute OPMODEREG on DSP48A instance %m is set to %d. Legal values for this attribute are 0 or 1.", OPMODEREG); + $finish; + end + endcase + end + + + +//---------------------------------------------------- +//*** DRC for OPMODE +//---------------------------------------------------- + + always @(qopmode_o_mux or carryinsel_attr or qz_o_mux or qx_o_mux or qcarryin_o_mux) begin + + if ($time > 100000) begin // no check at first 100ns + + case ({qopmode_o_mux, carryinsel_attr}) + + 9'b000000000 : deassign_xz_mux; + 9'b000100000 : deassign_xz_mux; + 9'b001000000 : deassign_xz_mux; + 9'b001100000 : deassign_xz_mux; + 9'b010000000 : deassign_xz_mux; + 9'b010100000 : deassign_xz_mux; + 9'b011000000 : deassign_xz_mux; + 9'b011100000 : deassign_xz_mux; + 9'b100000000 : deassign_xz_mux; + 9'b100100000 : deassign_xz_mux; + 9'b101000000 : deassign_xz_mux; + 9'b101100000 : deassign_xz_mux; + 9'b110000000 : deassign_xz_mux; + 9'b110100000 : deassign_xz_mux; + 9'b111000000 : deassign_xz_mux; + 9'b111100000 : deassign_xz_mux; + 9'b000000001 : deassign_xz_mux; + 9'b000100001 : deassign_xz_mux; + 9'b001000001 : deassign_xz_mux; + 9'b001100001 : deassign_xz_mux; + 9'b010000001 : deassign_xz_mux; + 9'b010100001 : deassign_xz_mux; + 9'b011000001 : deassign_xz_mux; + 9'b011100001 : deassign_xz_mux; + 9'b100000001 : deassign_xz_mux; + 9'b100100001 : deassign_xz_mux; + 9'b101000001 : deassign_xz_mux; + 9'b101100001 : deassign_xz_mux; + 9'b110000001 : deassign_xz_mux; + 9'b110100001 : deassign_xz_mux; + 9'b111000001 : deassign_xz_mux; + 9'b111100001 : deassign_xz_mux; + 9'b000000100 : if (PREG != 1) display_invalid_opmode; else deassign_xz_mux; + 9'b000000101 : if (PREG != 1) display_invalid_opmode; else deassign_xz_mux; + 9'b000100100 : if (PREG != 1) display_invalid_opmode; else deassign_xz_mux; + 9'b000100101 : if (PREG != 1) display_invalid_opmode; else deassign_xz_mux; + 9'b001000100 : if (PREG != 1) display_invalid_opmode; else deassign_xz_mux; + 9'b001000101 : if (PREG != 1) display_invalid_opmode; else deassign_xz_mux; + 9'b001100100 : if (PREG != 1) display_invalid_opmode; else deassign_xz_mux; + 9'b001100101 : if (PREG != 1) display_invalid_opmode; else deassign_xz_mux; + 9'b010000100 : if (PREG != 1) display_invalid_opmode; else deassign_xz_mux; + 9'b010000101 : if (PREG != 1) display_invalid_opmode; else deassign_xz_mux; + 9'b010100100 : if (PREG != 1) display_invalid_opmode; else deassign_xz_mux; + 9'b010100101 : if (PREG != 1) display_invalid_opmode; else deassign_xz_mux; + 9'b011000100 : if (PREG != 1) display_invalid_opmode; else deassign_xz_mux; + 9'b011000101 : if (PREG != 1) display_invalid_opmode; else deassign_xz_mux; + 9'b011100100 : if (PREG != 1) display_invalid_opmode; else deassign_xz_mux; + 9'b011100101 : if (PREG != 1) display_invalid_opmode; else deassign_xz_mux; + 9'b100000100 : if (PREG != 1) display_invalid_opmode; else deassign_xz_mux; + 9'b100000101 : if (PREG != 1) display_invalid_opmode; else deassign_xz_mux; + 9'b100100100 : if (PREG != 1) display_invalid_opmode; else deassign_xz_mux; + 9'b100100101 : if (PREG != 1) display_invalid_opmode; else deassign_xz_mux; + 9'b101000100 : if (PREG != 1) display_invalid_opmode; else deassign_xz_mux; + 9'b101000101 : if (PREG != 1) display_invalid_opmode; else deassign_xz_mux; + 9'b101100100 : if (PREG != 1) display_invalid_opmode; else deassign_xz_mux; + 9'b101100101 : if (PREG != 1) display_invalid_opmode; else deassign_xz_mux; + 9'b110000100 : if (PREG != 1) display_invalid_opmode; else deassign_xz_mux; + 9'b110000101 : if (PREG != 1) display_invalid_opmode; else deassign_xz_mux; + 9'b110100100 : if (PREG != 1) display_invalid_opmode; else deassign_xz_mux; + 9'b110100101 : if (PREG != 1) display_invalid_opmode; else deassign_xz_mux; + 9'b111000100 : if (PREG != 1) display_invalid_opmode; else deassign_xz_mux; + 9'b111000101 : if (PREG != 1) display_invalid_opmode; else deassign_xz_mux; + 9'b111100100 : if (PREG != 1) display_invalid_opmode; else deassign_xz_mux; + 9'b111100101 : if (PREG != 1) display_invalid_opmode; else deassign_xz_mux; + 9'b000000110 : deassign_xz_mux; + 9'b000000111 : deassign_xz_mux; + 9'b001000110 : deassign_xz_mux; + 9'b001000111 : deassign_xz_mux; + 9'b010000110 : deassign_xz_mux; + 9'b010000111 : deassign_xz_mux; + 9'b011000110 : deassign_xz_mux; + 9'b011000111 : deassign_xz_mux; + 9'b100000110 : deassign_xz_mux; + 9'b100000111 : deassign_xz_mux; + 9'b101000110 : deassign_xz_mux; + 9'b101000111 : deassign_xz_mux; + 9'b110000110 : deassign_xz_mux; + 9'b110000111 : deassign_xz_mux; + 9'b111000110 : deassign_xz_mux; + 9'b111000111 : deassign_xz_mux; + 9'b000100110 : deassign_xz_mux; + 9'b000100111 : deassign_xz_mux; + 9'b001100110 : deassign_xz_mux; + 9'b001100111 : deassign_xz_mux; + 9'b010100110 : deassign_xz_mux; + 9'b010100111 : deassign_xz_mux; + 9'b011100110 : deassign_xz_mux; + 9'b011100111 : deassign_xz_mux; + 9'b100100110 : deassign_xz_mux; + 9'b100100111 : deassign_xz_mux; + 9'b101100110 : deassign_xz_mux; + 9'b101100111 : deassign_xz_mux; + 9'b110100110 : deassign_xz_mux; + 9'b110100111 : deassign_xz_mux; + 9'b111100110 : deassign_xz_mux; + 9'b111100111 : deassign_xz_mux; + 9'b000000010 : deassign_xz_mux; + 9'b000000011 : deassign_xz_mux; + 9'b001000010 : deassign_xz_mux; + 9'b001000011 : deassign_xz_mux; + 9'b010000010 : deassign_xz_mux; + 9'b010000011 : deassign_xz_mux; + 9'b011000010 : deassign_xz_mux; + 9'b011000011 : deassign_xz_mux; + 9'b100000010 : deassign_xz_mux; + 9'b100000011 : deassign_xz_mux; + 9'b101000010 : deassign_xz_mux; + 9'b101000011 : deassign_xz_mux; + 9'b110000010 : deassign_xz_mux; + 9'b110000011 : deassign_xz_mux; + 9'b111000010 : deassign_xz_mux; + 9'b111000011 : deassign_xz_mux; + 9'b000100010 : deassign_xz_mux; + 9'b000100011 : deassign_xz_mux; + 9'b001100010 : deassign_xz_mux; + 9'b001100011 : deassign_xz_mux; + 9'b100100010 : deassign_xz_mux; + 9'b100100011 : deassign_xz_mux; + 9'b101100010 : deassign_xz_mux; + 9'b101100011 : deassign_xz_mux; + 9'b010100010 : deassign_xz_mux; + 9'b010100011 : deassign_xz_mux; + 9'b011100010 : deassign_xz_mux; + 9'b011100011 : deassign_xz_mux; + 9'b110100010 : deassign_xz_mux; + 9'b110100011 : deassign_xz_mux; + 9'b111100010 : deassign_xz_mux; + 9'b111100011 : deassign_xz_mux; + 9'b000001000 : deassign_xz_mux; + 9'b000001001 : deassign_xz_mux; + 9'b000101000 : deassign_xz_mux; + 9'b000101001 : deassign_xz_mux; + 9'b001001000 : deassign_xz_mux; + 9'b001001001 : deassign_xz_mux; + 9'b001101000 : deassign_xz_mux; + 9'b001101001 : deassign_xz_mux; + 9'b010001000 : deassign_xz_mux; + 9'b010001001 : deassign_xz_mux; + 9'b010101000 : deassign_xz_mux; + 9'b010101001 : deassign_xz_mux; + 9'b011001000 : deassign_xz_mux; + 9'b011001001 : deassign_xz_mux; + 9'b011101000 : deassign_xz_mux; + 9'b011101001 : deassign_xz_mux; + 9'b100001000 : deassign_xz_mux; + 9'b100001001 : deassign_xz_mux; + 9'b100101000 : deassign_xz_mux; + 9'b100101001 : deassign_xz_mux; + 9'b101001000 : deassign_xz_mux; + 9'b101001001 : deassign_xz_mux; + 9'b101101000 : deassign_xz_mux; + 9'b101101001 : deassign_xz_mux; + 9'b110001000 : deassign_xz_mux; + 9'b110001001 : deassign_xz_mux; + 9'b110101000 : deassign_xz_mux; + 9'b110101001 : deassign_xz_mux; + 9'b111001000 : deassign_xz_mux; + 9'b111001001 : deassign_xz_mux; + 9'b111101000 : deassign_xz_mux; + 9'b111101001 : deassign_xz_mux; + 9'b000001100 : if (PREG != 1) display_invalid_opmode; else deassign_xz_mux; + 9'b000001101 : if (PREG != 1) display_invalid_opmode; else deassign_xz_mux; + 9'b000101100 : if (PREG != 1) display_invalid_opmode; else deassign_xz_mux; + 9'b000101101 : if (PREG != 1) display_invalid_opmode; else deassign_xz_mux; + 9'b001001100 : if (PREG != 1) display_invalid_opmode; else deassign_xz_mux; + 9'b001001101 : if (PREG != 1) display_invalid_opmode; else deassign_xz_mux; + 9'b001101100 : if (PREG != 1) display_invalid_opmode; else deassign_xz_mux; + 9'b001101101 : if (PREG != 1) display_invalid_opmode; else deassign_xz_mux; + 9'b010001100 : if (PREG != 1) display_invalid_opmode; else deassign_xz_mux; + 9'b010001101 : if (PREG != 1) display_invalid_opmode; else deassign_xz_mux; + 9'b010101100 : if (PREG != 1) display_invalid_opmode; else deassign_xz_mux; + 9'b010101101 : if (PREG != 1) display_invalid_opmode; else deassign_xz_mux; + 9'b011001100 : if (PREG != 1) display_invalid_opmode; else deassign_xz_mux; + 9'b011001101 : if (PREG != 1) display_invalid_opmode; else deassign_xz_mux; + 9'b011101100 : if (PREG != 1) display_invalid_opmode; else deassign_xz_mux; + 9'b011101101 : if (PREG != 1) display_invalid_opmode; else deassign_xz_mux; + 9'b100001100 : if (PREG != 1) display_invalid_opmode; else deassign_xz_mux; + 9'b100001101 : if (PREG != 1) display_invalid_opmode; else deassign_xz_mux; + 9'b100101100 : if (PREG != 1) display_invalid_opmode; else deassign_xz_mux; + 9'b100101101 : if (PREG != 1) display_invalid_opmode; else deassign_xz_mux; + 9'b101001100 : if (PREG != 1) display_invalid_opmode; else deassign_xz_mux; + 9'b101001101 : if (PREG != 1) display_invalid_opmode; else deassign_xz_mux; + 9'b101101100 : if (PREG != 1) display_invalid_opmode; else deassign_xz_mux; + 9'b101101101 : if (PREG != 1) display_invalid_opmode; else deassign_xz_mux; + 9'b110001100 : if (PREG != 1) display_invalid_opmode; else deassign_xz_mux; + 9'b110001101 : if (PREG != 1) display_invalid_opmode; else deassign_xz_mux; + 9'b110101100 : if (PREG != 1) display_invalid_opmode; else deassign_xz_mux; + 9'b110101101 : if (PREG != 1) display_invalid_opmode; else deassign_xz_mux; + 9'b111001100 : if (PREG != 1) display_invalid_opmode; else deassign_xz_mux; + 9'b111001101 : if (PREG != 1) display_invalid_opmode; else deassign_xz_mux; + 9'b111101100 : if (PREG != 1) display_invalid_opmode; else deassign_xz_mux; + 9'b111101101 : if (PREG != 1) display_invalid_opmode; else deassign_xz_mux; + 9'b000001110 : deassign_xz_mux; + 9'b000001111 : deassign_xz_mux; + 9'b001001110 : deassign_xz_mux; + 9'b001001111 : deassign_xz_mux; + 9'b010001110 : deassign_xz_mux; + 9'b010001111 : deassign_xz_mux; + 9'b011001110 : deassign_xz_mux; + 9'b011001111 : deassign_xz_mux; + 9'b100001110 : deassign_xz_mux; + 9'b100001111 : deassign_xz_mux; + 9'b101001110 : deassign_xz_mux; + 9'b101001111 : deassign_xz_mux; + 9'b110001110 : deassign_xz_mux; + 9'b110001111 : deassign_xz_mux; + 9'b111001110 : deassign_xz_mux; + 9'b111001111 : deassign_xz_mux; + 9'b000101110 : deassign_xz_mux; + 9'b000101111 : deassign_xz_mux; + 9'b001101110 : deassign_xz_mux; + 9'b001101111 : deassign_xz_mux; + 9'b010101110 : deassign_xz_mux; + 9'b010101111 : deassign_xz_mux; + 9'b011101110 : deassign_xz_mux; + 9'b011101111 : deassign_xz_mux; + 9'b100101110 : deassign_xz_mux; + 9'b100101111 : deassign_xz_mux; + 9'b101101110 : deassign_xz_mux; + 9'b101101111 : deassign_xz_mux; + 9'b110101110 : deassign_xz_mux; + 9'b110101111 : deassign_xz_mux; + 9'b111101110 : deassign_xz_mux; + 9'b111101111 : deassign_xz_mux; + 9'b000001010 : deassign_xz_mux; + 9'b000001011 : deassign_xz_mux; + 9'b001001010 : deassign_xz_mux; + 9'b001001011 : deassign_xz_mux; + 9'b010001010 : deassign_xz_mux; + 9'b010001011 : deassign_xz_mux; + 9'b011001010 : deassign_xz_mux; + 9'b011001011 : deassign_xz_mux; + 9'b100001010 : deassign_xz_mux; + 9'b100001011 : deassign_xz_mux; + 9'b101001010 : deassign_xz_mux; + 9'b101001011 : deassign_xz_mux; + 9'b110001010 : deassign_xz_mux; + 9'b110001011 : deassign_xz_mux; + 9'b111001010 : deassign_xz_mux; + 9'b111001011 : deassign_xz_mux; + 9'b000101010 : deassign_xz_mux; + 9'b000101011 : deassign_xz_mux; + 9'b001101010 : deassign_xz_mux; + 9'b001101011 : deassign_xz_mux; + 9'b100101010 : deassign_xz_mux; + 9'b100101011 : deassign_xz_mux; + 9'b101101010 : deassign_xz_mux; + 9'b101101011 : deassign_xz_mux; + 9'b010101010 : deassign_xz_mux; + 9'b010101011 : deassign_xz_mux; + 9'b011101010 : deassign_xz_mux; + 9'b011101011 : deassign_xz_mux; + 9'b110101010 : deassign_xz_mux; + 9'b110101011 : deassign_xz_mux; + 9'b111101010 : deassign_xz_mux; + 9'b111101011 : deassign_xz_mux; + 9'b000010000 : if (PREG != 1) display_invalid_opmode; else deassign_xz_mux; + 9'b000010001 : if (PREG != 1) display_invalid_opmode; else deassign_xz_mux; + 9'b000110000 : if (PREG != 1) display_invalid_opmode; else deassign_xz_mux; + 9'b000110001 : if (PREG != 1) display_invalid_opmode; else deassign_xz_mux; + 9'b001010000 : if (PREG != 1) display_invalid_opmode; else deassign_xz_mux; + 9'b001010001 : if (PREG != 1) display_invalid_opmode; else deassign_xz_mux; + 9'b001110000 : if (PREG != 1) display_invalid_opmode; else deassign_xz_mux; + 9'b001110001 : if (PREG != 1) display_invalid_opmode; else deassign_xz_mux; + 9'b010010000 : if (PREG != 1) display_invalid_opmode; else deassign_xz_mux; + 9'b010010001 : if (PREG != 1) display_invalid_opmode; else deassign_xz_mux; + 9'b010110000 : if (PREG != 1) display_invalid_opmode; else deassign_xz_mux; + 9'b010110001 : if (PREG != 1) display_invalid_opmode; else deassign_xz_mux; + 9'b011010000 : if (PREG != 1) display_invalid_opmode; else deassign_xz_mux; + 9'b011010001 : if (PREG != 1) display_invalid_opmode; else deassign_xz_mux; + 9'b011110000 : if (PREG != 1) display_invalid_opmode; else deassign_xz_mux; + 9'b011110001 : if (PREG != 1) display_invalid_opmode; else deassign_xz_mux; + 9'b100010000 : if (PREG != 1) display_invalid_opmode; else deassign_xz_mux; + 9'b100010001 : if (PREG != 1) display_invalid_opmode; else deassign_xz_mux; + 9'b100110000 : if (PREG != 1) display_invalid_opmode; else deassign_xz_mux; + 9'b100110001 : if (PREG != 1) display_invalid_opmode; else deassign_xz_mux; + 9'b101010000 : if (PREG != 1) display_invalid_opmode; else deassign_xz_mux; + 9'b101010001 : if (PREG != 1) display_invalid_opmode; else deassign_xz_mux; + 9'b101110000 : if (PREG != 1) display_invalid_opmode; else deassign_xz_mux; + 9'b101110001 : if (PREG != 1) display_invalid_opmode; else deassign_xz_mux; + 9'b110010000 : if (PREG != 1) display_invalid_opmode; else deassign_xz_mux; + 9'b110010001 : if (PREG != 1) display_invalid_opmode; else deassign_xz_mux; + 9'b110110000 : if (PREG != 1) display_invalid_opmode; else deassign_xz_mux; + 9'b110110001 : if (PREG != 1) display_invalid_opmode; else deassign_xz_mux; + 9'b111010000 : if (PREG != 1) display_invalid_opmode; else deassign_xz_mux; + 9'b111010001 : if (PREG != 1) display_invalid_opmode; else deassign_xz_mux; + 9'b111110000 : if (PREG != 1) display_invalid_opmode; else deassign_xz_mux; + 9'b111110001 : if (PREG != 1) display_invalid_opmode; else deassign_xz_mux; + 9'b000010100 : if (PREG != 1) display_invalid_opmode; else deassign_xz_mux; + 9'b000010101 : if (PREG != 1) display_invalid_opmode; else deassign_xz_mux; + 9'b000110100 : if (PREG != 1) display_invalid_opmode; else deassign_xz_mux; + 9'b000110101 : if (PREG != 1) display_invalid_opmode; else deassign_xz_mux; + 9'b001010100 : if (PREG != 1) display_invalid_opmode; else deassign_xz_mux; + 9'b001010101 : if (PREG != 1) display_invalid_opmode; else deassign_xz_mux; + 9'b001110100 : if (PREG != 1) display_invalid_opmode; else deassign_xz_mux; + 9'b001110101 : if (PREG != 1) display_invalid_opmode; else deassign_xz_mux; + 9'b010010100 : if (PREG != 1) display_invalid_opmode; else deassign_xz_mux; + 9'b010010101 : if (PREG != 1) display_invalid_opmode; else deassign_xz_mux; + 9'b010110100 : if (PREG != 1) display_invalid_opmode; else deassign_xz_mux; + 9'b010110101 : if (PREG != 1) display_invalid_opmode; else deassign_xz_mux; + 9'b011010100 : if (PREG != 1) display_invalid_opmode; else deassign_xz_mux; + 9'b011010101 : if (PREG != 1) display_invalid_opmode; else deassign_xz_mux; + 9'b011110100 : if (PREG != 1) display_invalid_opmode; else deassign_xz_mux; + 9'b011110101 : if (PREG != 1) display_invalid_opmode; else deassign_xz_mux; + 9'b100010100 : if (PREG != 1) display_invalid_opmode; else deassign_xz_mux; + 9'b100010101 : if (PREG != 1) display_invalid_opmode; else deassign_xz_mux; + 9'b100110100 : if (PREG != 1) display_invalid_opmode; else deassign_xz_mux; + 9'b100110101 : if (PREG != 1) display_invalid_opmode; else deassign_xz_mux; + 9'b101010100 : if (PREG != 1) display_invalid_opmode; else deassign_xz_mux; + 9'b101010101 : if (PREG != 1) display_invalid_opmode; else deassign_xz_mux; + 9'b101110100 : if (PREG != 1) display_invalid_opmode; else deassign_xz_mux; + 9'b101110101 : if (PREG != 1) display_invalid_opmode; else deassign_xz_mux; + 9'b110010100 : if (PREG != 1) display_invalid_opmode; else deassign_xz_mux; + 9'b110010101 : if (PREG != 1) display_invalid_opmode; else deassign_xz_mux; + 9'b110110100 : if (PREG != 1) display_invalid_opmode; else deassign_xz_mux; + 9'b110110101 : if (PREG != 1) display_invalid_opmode; else deassign_xz_mux; + 9'b111010100 : if (PREG != 1) display_invalid_opmode; else deassign_xz_mux; + 9'b111010101 : if (PREG != 1) display_invalid_opmode; else deassign_xz_mux; + 9'b111110100 : if (PREG != 1) display_invalid_opmode; else deassign_xz_mux; + 9'b111110101 : if (PREG != 1) display_invalid_opmode; else deassign_xz_mux; + 9'b000010110 : if (PREG != 1) display_invalid_opmode; else deassign_xz_mux; + 9'b000010111 : if (PREG != 1) display_invalid_opmode; else deassign_xz_mux; + 9'b001010110 : if (PREG != 1) display_invalid_opmode; else deassign_xz_mux; + 9'b001010111 : if (PREG != 1) display_invalid_opmode; else deassign_xz_mux; + 9'b010010110 : if (PREG != 1) display_invalid_opmode; else deassign_xz_mux; + 9'b010010111 : if (PREG != 1) display_invalid_opmode; else deassign_xz_mux; + 9'b011010110 : if (PREG != 1) display_invalid_opmode; else deassign_xz_mux; + 9'b011010111 : if (PREG != 1) display_invalid_opmode; else deassign_xz_mux; + 9'b100010110 : if (PREG != 1) display_invalid_opmode; else deassign_xz_mux; + 9'b100010111 : if (PREG != 1) display_invalid_opmode; else deassign_xz_mux; + 9'b101010110 : if (PREG != 1) display_invalid_opmode; else deassign_xz_mux; + 9'b101010111 : if (PREG != 1) display_invalid_opmode; else deassign_xz_mux; + 9'b110010110 : if (PREG != 1) display_invalid_opmode; else deassign_xz_mux; + 9'b110010111 : if (PREG != 1) display_invalid_opmode; else deassign_xz_mux; + 9'b111010110 : if (PREG != 1) display_invalid_opmode; else deassign_xz_mux; + 9'b111010111 : if (PREG != 1) display_invalid_opmode; else deassign_xz_mux; + 9'b000110110 : if (PREG != 1) display_invalid_opmode; else deassign_xz_mux; + 9'b000110111 : if (PREG != 1) display_invalid_opmode; else deassign_xz_mux; + 9'b001110110 : if (PREG != 1) display_invalid_opmode; else deassign_xz_mux; + 9'b001110111 : if (PREG != 1) display_invalid_opmode; else deassign_xz_mux; + 9'b010110110 : if (PREG != 1) display_invalid_opmode; else deassign_xz_mux; + 9'b010110111 : if (PREG != 1) display_invalid_opmode; else deassign_xz_mux; + 9'b011110110 : if (PREG != 1) display_invalid_opmode; else deassign_xz_mux; + 9'b011110111 : if (PREG != 1) display_invalid_opmode; else deassign_xz_mux; + 9'b100110110 : if (PREG != 1) display_invalid_opmode; else deassign_xz_mux; + 9'b100110111 : if (PREG != 1) display_invalid_opmode; else deassign_xz_mux; + 9'b101110110 : if (PREG != 1) display_invalid_opmode; else deassign_xz_mux; + 9'b101110111 : if (PREG != 1) display_invalid_opmode; else deassign_xz_mux; + 9'b110110110 : if (PREG != 1) display_invalid_opmode; else deassign_xz_mux; + 9'b110110111 : if (PREG != 1) display_invalid_opmode; else deassign_xz_mux; + 9'b111110110 : if (PREG != 1) display_invalid_opmode; else deassign_xz_mux; + 9'b111110111 : if (PREG != 1) display_invalid_opmode; else deassign_xz_mux; + 9'b000010010 : if (PREG != 1) display_invalid_opmode; else deassign_xz_mux; + 9'b000010011 : if (PREG != 1) display_invalid_opmode; else deassign_xz_mux; + 9'b001010010 : if (PREG != 1) display_invalid_opmode; else deassign_xz_mux; + 9'b001010011 : if (PREG != 1) display_invalid_opmode; else deassign_xz_mux; + 9'b010010010 : if (PREG != 1) display_invalid_opmode; else deassign_xz_mux; + 9'b010010011 : if (PREG != 1) display_invalid_opmode; else deassign_xz_mux; + 9'b011010010 : if (PREG != 1) display_invalid_opmode; else deassign_xz_mux; + 9'b011010011 : if (PREG != 1) display_invalid_opmode; else deassign_xz_mux; + 9'b100010010 : if (PREG != 1) display_invalid_opmode; else deassign_xz_mux; + 9'b100010011 : if (PREG != 1) display_invalid_opmode; else deassign_xz_mux; + 9'b101010010 : if (PREG != 1) display_invalid_opmode; else deassign_xz_mux; + 9'b101010011 : if (PREG != 1) display_invalid_opmode; else deassign_xz_mux; + 9'b110010010 : if (PREG != 1) display_invalid_opmode; else deassign_xz_mux; + 9'b110010011 : if (PREG != 1) display_invalid_opmode; else deassign_xz_mux; + 9'b111010010 : if (PREG != 1) display_invalid_opmode; else deassign_xz_mux; + 9'b111010011 : if (PREG != 1) display_invalid_opmode; else deassign_xz_mux; + 9'b000110010 : if (PREG != 1) display_invalid_opmode; else deassign_xz_mux; + 9'b000110011 : if (PREG != 1) display_invalid_opmode; else deassign_xz_mux; + 9'b001110010 : if (PREG != 1) display_invalid_opmode; else deassign_xz_mux; + 9'b001110011 : if (PREG != 1) display_invalid_opmode; else deassign_xz_mux; + 9'b100110010 : if (PREG != 1) display_invalid_opmode; else deassign_xz_mux; + 9'b100110011 : if (PREG != 1) display_invalid_opmode; else deassign_xz_mux; + 9'b101110010 : if (PREG != 1) display_invalid_opmode; else deassign_xz_mux; + 9'b101110011 : if (PREG != 1) display_invalid_opmode; else deassign_xz_mux; + 9'b010110010 : if (PREG != 1) display_invalid_opmode; else deassign_xz_mux; + 9'b010110011 : if (PREG != 1) display_invalid_opmode; else deassign_xz_mux; + 9'b011110010 : if (PREG != 1) display_invalid_opmode; else deassign_xz_mux; + 9'b011110011 : if (PREG != 1) display_invalid_opmode; else deassign_xz_mux; + 9'b110110010 : if (PREG != 1) display_invalid_opmode; else deassign_xz_mux; + 9'b110110011 : if (PREG != 1) display_invalid_opmode; else deassign_xz_mux; + 9'b111110010 : if (PREG != 1) display_invalid_opmode; else deassign_xz_mux; + 9'b111110011 : if (PREG != 1) display_invalid_opmode; else deassign_xz_mux; + 9'b000011000 : deassign_xz_mux; + 9'b000011001 : deassign_xz_mux; + 9'b000111000 : deassign_xz_mux; + 9'b000111001 : deassign_xz_mux; + 9'b001011000 : deassign_xz_mux; + 9'b001011001 : deassign_xz_mux; + 9'b001111000 : deassign_xz_mux; + 9'b001111001 : deassign_xz_mux; + 9'b010011000 : deassign_xz_mux; + 9'b010011001 : deassign_xz_mux; + 9'b010111000 : deassign_xz_mux; + 9'b010111001 : deassign_xz_mux; + 9'b011011000 : deassign_xz_mux; + 9'b011011001 : deassign_xz_mux; + 9'b011111000 : deassign_xz_mux; + 9'b011111001 : deassign_xz_mux; + 9'b100011000 : deassign_xz_mux; + 9'b100011001 : deassign_xz_mux; + 9'b100111000 : deassign_xz_mux; + 9'b100111001 : deassign_xz_mux; + 9'b101011000 : deassign_xz_mux; + 9'b101011001 : deassign_xz_mux; + 9'b101111000 : deassign_xz_mux; + 9'b101111001 : deassign_xz_mux; + 9'b110011000 : deassign_xz_mux; + 9'b110011001 : deassign_xz_mux; + 9'b110111000 : deassign_xz_mux; + 9'b110111001 : deassign_xz_mux; + 9'b111011000 : deassign_xz_mux; + 9'b111011001 : deassign_xz_mux; + 9'b111111000 : deassign_xz_mux; + 9'b111111001 : deassign_xz_mux; + 9'b000011100 : if (PREG != 1) display_invalid_opmode; else deassign_xz_mux; + 9'b000011101 : if (PREG != 1) display_invalid_opmode; else deassign_xz_mux; + 9'b000111100 : if (PREG != 1) display_invalid_opmode; else deassign_xz_mux; + 9'b000111101 : if (PREG != 1) display_invalid_opmode; else deassign_xz_mux; + 9'b001011100 : if (PREG != 1) display_invalid_opmode; else deassign_xz_mux; + 9'b001011101 : if (PREG != 1) display_invalid_opmode; else deassign_xz_mux; + 9'b001111100 : if (PREG != 1) display_invalid_opmode; else deassign_xz_mux; + 9'b001111101 : if (PREG != 1) display_invalid_opmode; else deassign_xz_mux; + 9'b010011100 : if (PREG != 1) display_invalid_opmode; else deassign_xz_mux; + 9'b010011101 : if (PREG != 1) display_invalid_opmode; else deassign_xz_mux; + 9'b010111100 : if (PREG != 1) display_invalid_opmode; else deassign_xz_mux; + 9'b010111101 : if (PREG != 1) display_invalid_opmode; else deassign_xz_mux; + 9'b011011100 : if (PREG != 1) display_invalid_opmode; else deassign_xz_mux; + 9'b011011101 : if (PREG != 1) display_invalid_opmode; else deassign_xz_mux; + 9'b011111100 : if (PREG != 1) display_invalid_opmode; else deassign_xz_mux; + 9'b011111101 : if (PREG != 1) display_invalid_opmode; else deassign_xz_mux; + 9'b100011100 : if (PREG != 1) display_invalid_opmode; else deassign_xz_mux; + 9'b100011101 : if (PREG != 1) display_invalid_opmode; else deassign_xz_mux; + 9'b100111100 : if (PREG != 1) display_invalid_opmode; else deassign_xz_mux; + 9'b100111101 : if (PREG != 1) display_invalid_opmode; else deassign_xz_mux; + 9'b101011100 : if (PREG != 1) display_invalid_opmode; else deassign_xz_mux; + 9'b101011101 : if (PREG != 1) display_invalid_opmode; else deassign_xz_mux; + 9'b101111100 : if (PREG != 1) display_invalid_opmode; else deassign_xz_mux; + 9'b101111101 : if (PREG != 1) display_invalid_opmode; else deassign_xz_mux; + 9'b110011100 : if (PREG != 1) display_invalid_opmode; else deassign_xz_mux; + 9'b110011101 : if (PREG != 1) display_invalid_opmode; else deassign_xz_mux; + 9'b110111100 : if (PREG != 1) display_invalid_opmode; else deassign_xz_mux; + 9'b110111101 : if (PREG != 1) display_invalid_opmode; else deassign_xz_mux; + 9'b111011100 : if (PREG != 1) display_invalid_opmode; else deassign_xz_mux; + 9'b111011101 : if (PREG != 1) display_invalid_opmode; else deassign_xz_mux; + 9'b111111100 : if (PREG != 1) display_invalid_opmode; else deassign_xz_mux; + 9'b111111101 : if (PREG != 1) display_invalid_opmode; else deassign_xz_mux; + 9'b000011110 : deassign_xz_mux; + 9'b000011111 : deassign_xz_mux; + 9'b001011110 : deassign_xz_mux; + 9'b001011111 : deassign_xz_mux; + 9'b010011110 : deassign_xz_mux; + 9'b010011111 : deassign_xz_mux; + 9'b011011110 : deassign_xz_mux; + 9'b011011111 : deassign_xz_mux; + 9'b100011110 : deassign_xz_mux; + 9'b100011111 : deassign_xz_mux; + 9'b101011110 : deassign_xz_mux; + 9'b101011111 : deassign_xz_mux; + 9'b110011110 : deassign_xz_mux; + 9'b110011111 : deassign_xz_mux; + 9'b111011110 : deassign_xz_mux; + 9'b111011111 : deassign_xz_mux; + 9'b000011010 : deassign_xz_mux; + 9'b000011011 : deassign_xz_mux; + 9'b001011010 : deassign_xz_mux; + 9'b001011011 : deassign_xz_mux; + 9'b010011010 : deassign_xz_mux; + 9'b010011011 : deassign_xz_mux; + 9'b011011010 : deassign_xz_mux; + 9'b011011011 : deassign_xz_mux; + 9'b100011010 : deassign_xz_mux; + 9'b100011011 : deassign_xz_mux; + 9'b101011010 : deassign_xz_mux; + 9'b101011011 : deassign_xz_mux; + 9'b110011010 : deassign_xz_mux; + 9'b110011011 : deassign_xz_mux; + 9'b111011010 : deassign_xz_mux; + 9'b111011011 : deassign_xz_mux; + 9'b000111010 : deassign_xz_mux; + 9'b000111011 : deassign_xz_mux; + 9'b001111010 : deassign_xz_mux; + 9'b001111011 : deassign_xz_mux; + 9'b100111010 : deassign_xz_mux; + 9'b100111011 : deassign_xz_mux; + 9'b101111010 : deassign_xz_mux; + 9'b101111011 : deassign_xz_mux; + 9'b010111010 : deassign_xz_mux; + 9'b010111011 : deassign_xz_mux; + 9'b011111010 : deassign_xz_mux; + 9'b011111011 : deassign_xz_mux; + 9'b110111010 : deassign_xz_mux; + 9'b110111011 : deassign_xz_mux; + 9'b111111010 : deassign_xz_mux; + 9'b111111011 : deassign_xz_mux; + 9'b000111110 : deassign_xz_mux; + 9'b000111111 : deassign_xz_mux; + 9'b001111110 : deassign_xz_mux; + 9'b001111111 : deassign_xz_mux; + 9'b010111110 : deassign_xz_mux; + 9'b010111111 : deassign_xz_mux; + 9'b011111110 : deassign_xz_mux; + 9'b011111111 : deassign_xz_mux; + 9'b100111110 : deassign_xz_mux; + 9'b100111111 : deassign_xz_mux; + 9'b101111110 : deassign_xz_mux; + 9'b101111111 : deassign_xz_mux; + 9'b110111110 : deassign_xz_mux; + 9'b110111111 : deassign_xz_mux; + 9'b111111110 : deassign_xz_mux; + 9'b111111111 : deassign_xz_mux; + default : begin + if (invalid_opmode) begin + + invalid_opmode = 0; + assign qx_o_mux = 48'bx; + assign qz_o_mux = 48'bx; + assign add_o = 48'bx; + $display("OPMODE Input Warning : The OPMODE %b to DSP48A instance %m is either invalid or the CARRYINSEL %b for that specific OPMODE at %.3f ns.", qopmode_o_mux, carryinsel_attr, $time/1000.0); + + end + end + + endcase // case(opmode_in) + + end // if ($time > 100000) + +// *** Add/Subtract + if (add_flag) begin + if (qopmode_o_mux[7] == 1'b1) + {carryout_o, add_o} = qz_o_mux - qx_o_mux - qcarryin_o_mux; + else if (qopmode_o_mux[7] == 1'b0) + {carryout_o, add_o} = qz_o_mux + qx_o_mux + qcarryin_o_mux; + end // if (add_flag = 1) + + end // always @ (qopmode_o_mux) + +//---------------------------------------------------- + + task deassign_xz_mux; + begin + add_flag = 1; + invalid_opmode = 1; // reset invalid opmode + deassign qx_o_mux; + deassign qz_o_mux; + deassign add_o; + end + endtask // deassign_xz_mux + + task display_invalid_opmode_no_mreg; + begin + if (invalid_opmode) begin + + add_flag = 0; + invalid_opmode = 0; + assign qx_o_mux = 48'bx; + assign qz_o_mux = 48'bx; + assign add_o = 48'bx; + $display("OPMODE Input Warning : The OPMODE %b with CARRYINSEL %b to DSP48A instance %m at %.3f ns requires attribute MREG set to 0.", qopmode_o_mux, carryinsel_attr, $time/1000.0); + end + end + endtask // display_invalid_opmode_no_mreg + + task display_invalid_opmode_mreg; + begin + if (invalid_opmode) begin + add_flag = 0; + invalid_opmode = 0; + assign qx_o_mux = 48'bx; + assign qz_o_mux = 48'bx; + assign add_o = 48'bx; + $display("OPMODE Input Warning : The OPMODE %b with CARRYINSEL %b to DSP48A instance %m at %.3f ns requires attribute MREG set to 1.", qopmode_o_mux, carryinsel_attr, $time/1000.0); + end + end + endtask // display_invalid_opmode_mreg + + task display_invalid_opmode; + begin + if (invalid_opmode) begin + add_flag = 0; + invalid_opmode = 0; + assign qx_o_mux = 48'bx; + assign qz_o_mux = 48'bx; + assign add_o = 48'bx; + $display("OPMODE Input Warning : The OPMODE %b to DSP48A instance %m at %.3f ns requires attribute PREG set to 1.", qopmode_o_mux, $time/1000.0); + end + end + endtask // display_invalid_opmode + +//---------------------------------------------------- +//*** Output register P with 1 level of register +//---------------------------------------------------- +// Asynchronous Operation + always @(posedge clk_in, posedge rstp_in) begin + if(rst_async_flag) begin + if(rstp_in) begin + qp_o_reg1 <= 48'b0; + end // if rstp_in + else if(cep_in) begin + qp_o_reg1 <= add_o; + end // cep_in + end // if rst_async_flg + end + +// Synchronous Operation + always @(posedge clk_in) begin + if (rstp_in) + qp_o_reg1 <= 48'b0; + else if (cep_in) + qp_o_reg1 <= add_o; + end + + always @(qp_o_reg1 or add_o) begin + case (PREG) + 0 : qp_o_mux <= add_o; + 1 : qp_o_mux <= qp_o_reg1; + default : begin + $display("Attribute Syntax Error : The attribute PREG on DSP48A instance %m is set to %d. Legal values for this attribute are 0 or 1.", PREG); + $finish; + end + endcase + end + +//---------------------------------------------------- +//*** CARRYOUT +//---------------------------------------------------- +assign carryout_x_o = carryout_o; + + + specify + + (A *> CARRYOUT) = (0:0:0, 0:0:0); + (A *> P) = (0:0:0, 0:0:0); + (A *> PCOUT) = (0:0:0, 0:0:0); + + (B *> BCOUT) = (0:0:0, 0:0:0); + (B *> CARRYOUT) = (0:0:0, 0:0:0); + (B *> P) = (0:0:0, 0:0:0); + (B *> PCOUT) = (0:0:0, 0:0:0); + +// (BCIN *> BCOUT) = (0:0:0, 0:0:0); +// (BCIN *> CARRYOUT) = (0:0:0, 0:0:0); +// (BCIN *> P) = (0:0:0, 0:0:0); +// (BCIN *> PCOUT) = (0:0:0, 0:0:0); + + (C *> CARRYOUT) = (0:0:0, 0:0:0); + (C *> P) = (0:0:0, 0:0:0); + (C *> PCOUT) = (0:0:0, 0:0:0); + + (D *> BCOUT) = (0:0:0, 0:0:0); + (D *> CARRYOUT) = (0:0:0, 0:0:0); + (D *> P) = (0:0:0, 0:0:0); + (D *> PCOUT) = (0:0:0, 0:0:0); + + (CARRYIN *> CARRYOUT) = (0:0:0, 0:0:0); + (CARRYIN *> P) = (0:0:0, 0:0:0); + (CARRYIN *> PCOUT) = (0:0:0, 0:0:0); + + (CLK *> BCOUT) = (100:100:100, 100:100:100); + (CLK *> CARRYOUT) = (100:100:100, 100:100:100); + (CLK *> P) = (100:100:100, 100:100:100); + (CLK *> PCOUT) = (100:100:100, 100:100:100); + + (OPMODE *> BCOUT) = (0:0:0, 0:0:0); + (OPMODE *> CARRYOUT) = (0:0:0, 0:0:0); + (OPMODE *> P) = (0:0:0, 0:0:0); + (OPMODE *> PCOUT) = (0:0:0, 0:0:0); + + (PCIN *> CARRYOUT) = (0:0:0, 0:0:0); + (PCIN *> P) = (0:0:0, 0:0:0); + (PCIN *> PCOUT) = (0:0:0, 0:0:0); +// Asynchronous + (RSTA *> CARRYOUT) = (0:0:0, 0:0:0); + (RSTA *> P) = (0:0:0, 0:0:0); + (RSTA *> PCOUT) = (0:0:0, 0:0:0); + + (RSTB *> CARRYOUT) = (0:0:0, 0:0:0); + (RSTB *> BCOUT) = (0:0:0, 0:0:0); + (RSTB *> P) = (0:0:0, 0:0:0); + (RSTB *> PCOUT) = (0:0:0, 0:0:0); + + (RSTC *> CARRYOUT) = (0:0:0, 0:0:0); + (RSTC *> P) = (0:0:0, 0:0:0); + (RSTC *> PCOUT) = (0:0:0, 0:0:0); + + (RSTCARRYIN *> CARRYOUT) = (0:0:0, 0:0:0); + (RSTCARRYIN *> P) = (0:0:0, 0:0:0); + (RSTCARRYIN *> PCOUT) = (0:0:0, 0:0:0); + + (RSTD *> BCOUT) = (0:0:0, 0:0:0); + (RSTD *> CARRYOUT) = (0:0:0, 0:0:0); + (RSTD *> P) = (0:0:0, 0:0:0); + (RSTD *> PCOUT) = (0:0:0, 0:0:0); + + (RSTM *> CARRYOUT) = (0:0:0, 0:0:0); + (RSTM *> P) = (0:0:0, 0:0:0); + (RSTM *> PCOUT) = (0:0:0, 0:0:0); + + (RSTOPMODE *> BCOUT) = (0:0:0, 0:0:0); + (RSTOPMODE *> CARRYOUT) = (0:0:0, 0:0:0); + (RSTOPMODE *> P) = (0:0:0, 0:0:0); + (RSTOPMODE *> PCOUT) = (0:0:0, 0:0:0); + + (RSTP *> P) = (0:0:0, 0:0:0); + (RSTP *> PCOUT) = (0:0:0, 0:0:0); + + specparam PATHPULSE$ = 0; + + endspecify + +endmodule // DSP48A + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/DSP48A1.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/DSP48A1.v new file mode 100644 index 0000000..cf1bf5e --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/DSP48A1.v @@ -0,0 +1,1358 @@ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2006 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Multifunctional, Cascadable, 48-bit Output Arithmetic Block +// /___/ /\ Filename : DSP48A1.v +// \ \ / \ Timestamp : Thu Aug 16 14:46:39 PDT 2007 +// \___\/\___\ +// +// Revision: +// 08/16/07 - Initial version. +// 05/07/08 - IR # 467568, pulldown CARRYIN, BCIN and PCIN -- both unisim and simprim +// 07/08/08 - CR 473297 and 475997 fix -- removed input buffers that were causing NCSIM failures when sdf was backannotated +// 10/28/08 - IR 493742 initialized CARRYOUTs +// 02/09/09 - CR 503828 -- VCS compile warnings +// End Revision + +`timescale 1 ps / 1 ps + +module DSP48A1 (BCOUT, CARRYOUT, CARRYOUTF, M, P, PCOUT, A, B, C, CARRYIN, CEA, CEB, CEC, CECARRYIN, CED, CEM, CEOPMODE, CEP, CLK, D, OPMODE, PCIN, RSTA, RSTB, RSTC, RSTCARRYIN, RSTD, RSTM, RSTOPMODE, RSTP); + + parameter integer A0REG = 0; + parameter integer A1REG = 1; + parameter integer B0REG = 0; + parameter integer B1REG = 1; + parameter integer CARRYINREG = 1; + parameter integer CARRYOUTREG = 1; + parameter CARRYINSEL = "OPMODE5"; + parameter integer CREG = 1; + parameter integer DREG = 1; + parameter integer MREG = 1; + parameter integer OPMODEREG = 1; + parameter integer PREG = 1; + parameter RSTTYPE = "SYNC"; + + + output [17:0] BCOUT; + output CARRYOUT; + output CARRYOUTF; + output [35:0] M; + output [47:0] P; + output [47:0] PCOUT; + + input [17:0] A; + input [17:0] B; + + input [47:0] C; + input CARRYIN; + input CEA; + input CEB; + input CEC; + input CECARRYIN; + input CED; + input CEM; + input CEOPMODE; + input CEP; + input CLK; + input [17:0] D; + input [7:0] OPMODE; + input [47:0] PCIN; + input RSTA; + input RSTB; + input RSTC; + input RSTCARRYIN; + input RSTD; + input RSTM; + input RSTOPMODE; + input RSTP; + + pulldown BCIN_tmp[17:0] (BCIN); + pulldown(CARRYIN); + pulldown PCIN_tmp[47:0] (PCIN); + + tri0 GSR = glbl.GSR; + +//------------------- constants ------------------------- + localparam MAX_BCOUT = 18; + localparam MAX_P = 48; + localparam MAX_PCOUT = 48; + + localparam MAX_A = 18; + localparam MAX_B = 18; + localparam MAX_BCIN = 18; + localparam MAX_C = 48; + localparam MAX_D = 18; + localparam MAX_OPMODE = 8; + localparam MAX_PCIN = 48; + + + localparam MAX_MULT_A = 18; + localparam MAX_MULT_B = 18; + localparam MAX_MULT_AB = 36; + localparam MAX_MUX_XZ = 48; + + localparam MSB_BCOUT = MAX_BCOUT - 1; + localparam MSB_P = MAX_P - 1; + localparam MSB_M = MAX_MULT_AB - 1; + localparam MSB_PCOUT = MAX_PCOUT - 1; + + localparam MSB_A = MAX_A - 1; + localparam MSB_B = MAX_B - 1; + localparam MSB_BCIN = MAX_BCIN - 1; + localparam MSB_C = MAX_C - 1; + localparam MSB_D = MAX_D - 1; + localparam MSB_OPMODE = MAX_OPMODE - 1; + localparam MSB_PCIN = MAX_PCIN - 1; + + localparam MSB_MULT_A = MAX_MULT_A - 1; + localparam MSB_MULT_B = MAX_MULT_B - 1; + + localparam MSB_MULT_AB = MAX_MULT_AB - 1; +//-------------------------------------------------------------- + reg [MSB_A:0] qa_o_mux, qa_o_reg1, qa_o_reg2; + reg [MSB_B:0] b_o_mux, qb_o_mux0 = 18'b0, qb_o_mux = 18'b0, qb_o_reg1, qb_o_reg2, preadd, mux_preadd; + reg [MSB_C:0] qc_o_mux, qc_o_reg1; + reg carryinsel_attr, carryinsel_o_mux; + reg qcarryin_o_mux, qcarryin_o_reg1; + reg carryout_o = 1'b0; + reg qcarryout_o_mux = 1'b0; + reg qcarryout_o_reg1 = 1'b0; + + reg [MSB_MULT_AB:0] qmult_o_mux, qmult_o_reg1; + + reg [MSB_D:0] qd_o_mux, qd_o_reg1; + + reg [MSB_P:0] qp_o_mux = 48'b0, qp_o_reg1; + + reg [(MAX_MUX_XZ-1):0] qx_o_mux, qz_o_mux; + reg [MSB_OPMODE:0] qopmode_o_mux, qopmode_o_reg1; + + + reg invalid_opmode, add_flag, rst_async_flag = 0; + + reg B_INPUT_flag; + + reg [(MAX_MUX_XZ-1):0] add_o; + + wire [MSB_MULT_AB:0] mult_o; + + wire carryout_x_o; + + +//*** GSR pin + always @(GSR) begin + if (GSR) begin + assign qa_o_reg1 = 18'b0; + assign qa_o_reg2 = 18'b0; + assign qb_o_reg1 = 18'b0; + assign qb_o_reg2 = 18'b0; + assign qc_o_reg1 = 48'b0; + assign qd_o_reg1 = 18'b0; + assign qmult_o_reg1 = 36'b0; + assign qopmode_o_reg1 = 8'b0; + assign qcarryin_o_reg1 = 1'b0; + assign qp_o_reg1 = 48'b0; + + end + else begin + deassign qa_o_reg1; + deassign qa_o_reg2; + deassign qb_o_reg1; + deassign qb_o_reg2; + deassign qc_o_reg1; + deassign qd_o_reg1; + deassign qmult_o_reg1; + deassign qopmode_o_reg1; + deassign qcarryin_o_reg1; + deassign qp_o_reg1; + end + end + +//---------------------------------------------------- +//*** Initialization +//---------------------------------------------------- + + + + initial begin + +//-------- A0REG/A1REG & B0REG/B1REG ------ + + if ((A0REG != 0) && (A0REG != 1)) + begin + $display("Attribute Syntax Error : The attribute A0REG on DSP48A1 instance %m is set to %d. Legal values for this attribute are 0 or 1.", A0REG); + $finish; + end + + if ((A1REG != 0) && (A1REG != 1)) + begin + $display("Attribute Syntax Error : The attribute A1REG on DSP48A1 instance %m is set to %d. Legal values for this attribute are 0 or 1.", A1REG); + $finish; + end + + if ((B0REG != 0) && (B0REG != 1)) + begin + $display("Attribute Syntax Error : The attribute B0REG on DSP48A1 instance %m is set to %d. Legal values for this attribute are 0 or 1.", B0REG); + $finish; + end + + if ((B1REG != 0) && (B1REG != 1)) + begin + $display("Attribute Syntax Error : The attribute B1REG on DSP48A1 instance %m is set to %d. Legal values for this attribute are 0 or 1.", B1REG); + $finish; + end + +//-------- RSTTYPE ------ + + case (RSTTYPE) + "SYNC": rst_async_flag = 0; + "ASYNC": rst_async_flag = 1; + default : begin + $display("Attribute Syntax Error : The attribute RSTTYPE on DSP48A1 instance %m is set to %s. Legal values for this attribute are SYNC or ASYNC.", RSTTYPE); + $finish; + end + endcase + +//-------- CARRYINSEL ------ + + case (CARRYINSEL) + "CARRYIN" : carryinsel_attr <= 1'b0; + "OPMODE5" : carryinsel_attr <= 1'b1; + default : begin + $display("Attribute Syntax Error : The attribute CARRYINSEL on DSP48A1 instance %m is set to %s. Legal valuesfor this attribute are CARRYIN or OPMODE5.", CARRYINSEL); + $finish; + end + endcase + + add_flag <= 1; + invalid_opmode <= 1; + + end + + + +//---------------------------------------------------- +//*** Input register A with 2 level deep of registers +//---------------------------------------------------- +// Asynchronous Operation + always @(posedge CLK, posedge RSTA) begin + if(rst_async_flag) begin + if(RSTA) begin + qa_o_reg1 <= 18'b0; + qa_o_reg2 <= 18'b0; + end // if RSTA + else if(CEA) begin + qa_o_reg1 <= A; + qa_o_reg2 <= qa_o_reg1; + end // CEA + end // if rst_async_flg + end // always + +// Synchronous Operation + always @(posedge CLK) begin + if(!rst_async_flag) begin + if(RSTA) begin + qa_o_reg1 <= 18'b0; + qa_o_reg2 <= 18'b0; + end // if RSTA + else if(CEA) begin + qa_o_reg1 <= A; + qa_o_reg2 <= qa_o_reg1; + end // CEA + end // if rst_async_flg + end // always + + always @(A or qa_o_reg1 or qa_o_reg2) begin + if((A0REG==0) && (A1REG==0)) + qa_o_mux <= A; + else if(((A0REG==0) && (A1REG==1)) || ((A0REG==1) && (A1REG==0))) + qa_o_mux <= qa_o_reg1; + else if((A0REG==1) && (A1REG==1)) + qa_o_mux <= qa_o_reg2; + end + + +//---------------------------------------------------- +//*** Input register B with 2 level deep of registers +//---------------------------------------------------- +// Asynchronous Operation + always @(posedge CLK, posedge RSTB) begin + if(rst_async_flag) begin + if(RSTB) begin + qb_o_reg1 <= 18'b0; + qb_o_reg2 <= 18'b0; + end // if RSTB + else if(CEB) begin + qb_o_reg1 <= B; + qb_o_reg2 <= mux_preadd; + end // CEB + end // if rst_async_flg + end // always + +// Synchronous Operation + always @(posedge CLK) begin + if(!rst_async_flag) begin + if(RSTB) begin + qb_o_reg1 <= 18'b0; + qb_o_reg2 <= 18'b0; + end // if RSTB + else if(CEB) begin + qb_o_reg1 <= B; + qb_o_reg2 <= mux_preadd; + end // CEB + end // if rst_async_flg + end // always + + +//*** PRE_ADD + always @(qopmode_o_mux, B, qd_o_mux, qb_o_reg1) begin + if(((B0REG==0) && (B1REG==0)) || ((B0REG==0) && (B1REG==1))) begin + qb_o_mux0 = B; + if(qopmode_o_mux[6] == 0) + preadd = (qd_o_mux + B); + else if(qopmode_o_mux[6] == 1) + preadd = (qd_o_mux - B); + end + else if(((B0REG==1) && (B1REG==1)) || ((B0REG==1) && (B1REG==0))) begin + qb_o_mux0 = qb_o_reg1; + if(qopmode_o_mux[6] == 0) + preadd = (qd_o_mux + qb_o_reg1); + else if(qopmode_o_mux[6] == 1) + preadd = (qd_o_mux - qb_o_reg1); + end + end + + always @(qopmode_o_mux[4], preadd, qb_o_mux0) begin + if(qopmode_o_mux[4] == 1) + mux_preadd = preadd; + else if(qopmode_o_mux[4] == 0) + mux_preadd = qb_o_mux0; + end + + always @(mux_preadd, qb_o_reg2) begin + if(((B0REG==0) && (B1REG==0)) || ((B0REG==1) && (B1REG==0))) + qb_o_mux = mux_preadd; + else if(((B0REG==1) && (B1REG==1)) || ((B0REG==0) && (B1REG==1))) + qb_o_mux = qb_o_reg2; + end + + +//---------------------------------------------------- +//*** Input register C with 1 level deep of registers +//---------------------------------------------------- +// Asynchronous Operation + always @(posedge CLK, posedge RSTC) begin + if(rst_async_flag) begin + if(RSTC) begin + qc_o_reg1 <= 18'b0; + end // if RSTC + else if(CEC) begin + qc_o_reg1 <= C; + end // CEC + end // if rst_async_flg + end // always + +// Synchronous Operation + always @(posedge CLK) begin + if(!rst_async_flag) begin + if(RSTC) begin + qc_o_reg1 <= 18'b0; + end // if RSTC + else if(CEC) begin + qc_o_reg1 <= C; + end // CEC + end // if rst_async_flg + end // always + + always @(C or qc_o_reg1) begin + case (CREG) + 0 : qc_o_mux <= C; + 1 : qc_o_mux <= qc_o_reg1; + default : begin + $display("Attribute Syntax Error : The attribute CREG on DSP48A1 instance %m is set to %d. Legal values for this attribute are 0 or 1.", CREG); + $finish; + end + endcase + end + +//---------------------------------------------------- +//*** Input register D with 1 level deep of registers +//---------------------------------------------------- +// Asynchronous Operation + always @(posedge CLK, posedge RSTD) begin + if(rst_async_flag) begin + if(RSTD) begin + qd_o_reg1 <= 18'b0; + end // if RSTD + else if(CED) begin + qd_o_reg1 <= D; + end // CED + end // if rst_async_flg + end // always + +// Synchronous Operation + always @(posedge CLK) begin + if(!rst_async_flag) begin + if(RSTD) begin + qd_o_reg1 <= 18'b0; + end // if RSTD + else if(CED) begin + qd_o_reg1 <= D; + end // CED + end // if rst_async_flg + end // always + + always @(D or qd_o_reg1) begin + case (DREG) + 0 : qd_o_mux <= D; + 1 : qd_o_mux <= qd_o_reg1; + default : begin + $display("Attribute Syntax Error : The attribute DREG on DSP48A1 instance %m is set to %d. Legal values for this attribute are 0 or 1.", DREG); + $finish; + end + endcase + end + + +//---------------------------------------------------- +//*** 18x18 Multiplier +//---------------------------------------------------- + assign mult_o = {{MAX_MULT_A{qa_o_mux[MSB_MULT_A]}}, qa_o_mux} * {{MAX_MULT_B{qb_o_mux[MSB_MULT_B]}}, qb_o_mux}; + +// Asynchronous Operation + always @(posedge CLK, posedge RSTM) begin + if(rst_async_flag) begin + if(RSTM) begin + qmult_o_reg1 <= 36'b0; + end // if RSTM + else if(CEM) begin + qmult_o_reg1 <= mult_o; + end // CEM + end // if rst_async_flg + end // always + +// Synchronous Operation + always @(posedge CLK) begin + if(!rst_async_flag) begin + if(RSTM) begin + qmult_o_reg1 <= 36'b0; + end // if RSTM + else if(CEM) begin + qmult_o_reg1 <= mult_o; + end // CEM + end // if rst_async_flg + end // always + + always @(mult_o or qmult_o_reg1) begin + case (MREG) + 0 : qmult_o_mux <= mult_o; + 1 : qmult_o_mux <= qmult_o_reg1; + default : begin + $display("Attribute Syntax Error : The attribute MREG on DSP48A1 instance %m is set to %d. Legal values for this attribute are 0 or 1.", MREG); + $finish; + end + endcase + end + + +//*** X mux + + always @(qp_o_mux or qa_o_mux or qd_o_mux or qb_o_mux or qmult_o_mux or qopmode_o_mux) begin + case (qopmode_o_mux[1:0]) + 2'b00 : qx_o_mux <= 48'b0; + 2'b01 : qx_o_mux <= {{12{qmult_o_mux[MSB_MULT_AB]}}, qmult_o_mux}; + 2'b10 : qx_o_mux <= qp_o_mux; + 2'b11 : qx_o_mux <= {qd_o_mux[11:0], qa_o_mux[17:0], qb_o_mux[17:0]}; + default : begin + end + endcase + end + + +//*** Z mux + + always @(qp_o_mux or qc_o_mux or PCIN or qopmode_o_mux) begin + case (qopmode_o_mux[3:2]) + 3'b00 : qz_o_mux <= 48'b0; + 3'b01 : qz_o_mux <= PCIN; + 3'b10 : qz_o_mux <= qp_o_mux; + 3'b11 : qz_o_mux <= qc_o_mux; + default : begin + end + endcase + end + + +//---------------------------------------------------- +//*** CarryIn 1 level of register +//---------------------------------------------------- + always @(qopmode_o_mux[5], CARRYIN) begin + case (CARRYINSEL) + "CARRYIN" : carryinsel_o_mux <= CARRYIN; + "OPMODE5" : carryinsel_o_mux <= qopmode_o_mux[5]; + default : begin + $display("Attribute Syntax Error : The attribute CARRYINSEL on DSP48A1 instance %m is set to %s. Legal values for this attribute are CARRYIN or OPMODE5.", CARRYINSEL); + $finish; + end + endcase + end + +// Asynchronous Operation + always @(posedge CLK, posedge RSTCARRYIN) begin + if(rst_async_flag) begin + if(RSTCARRYIN) begin + qcarryin_o_reg1 <= 1'b0; + qcarryout_o_reg1 <= 1'b0; + end // if RSTCARRYIN + else if(CECARRYIN) begin + qcarryin_o_reg1 <= carryinsel_o_mux; + qcarryout_o_reg1 <= carryout_o; + end // CECARRYIN + end // if rst_async_flg + end // always + +// Synchronous Operation + always @(posedge CLK) begin + if (RSTCARRYIN) begin + qcarryin_o_reg1 <= 1'b0; + qcarryout_o_reg1 <= 1'b0; + end + else if (CECARRYIN) begin + qcarryin_o_reg1 <= carryinsel_o_mux; + qcarryout_o_reg1 <= carryout_o; + end + end + + + always @(carryinsel_o_mux or qcarryin_o_reg1) begin + case (CARRYINREG) + 0 : qcarryin_o_mux <= carryinsel_o_mux; + 1 : qcarryin_o_mux <= qcarryin_o_reg1; + default : begin + $display("Attribute Syntax Error : The attribute CARRYINREG on DSP48A1 instance %m is set to %d. Legal values for this attribute are 0 or 1.", CARRYINREG); + $finish; + end + endcase + end + + +//---------------------------------------------------- +//*** Opmode 1 level of register +//---------------------------------------------------- +// Asynchronous Operation + always @(posedge CLK, posedge RSTOPMODE) begin + if(rst_async_flag) begin + if(RSTOPMODE) begin + qopmode_o_reg1 <= 8'b0; + end // if RSTOPMODE + else if(CEOPMODE) begin + qopmode_o_reg1 <= OPMODE; + end // CEOPMODE + end // if rst_async_flg + end // always + +// Synchronous Operation + always @(posedge CLK) begin + if (RSTOPMODE) begin + qopmode_o_reg1 <= 8'b0; + end + else if (CEOPMODE) begin + qopmode_o_reg1 <= OPMODE; + end + end + + + always @(OPMODE or qopmode_o_reg1) begin + case (OPMODEREG) + 0 : qopmode_o_mux <= OPMODE; + 1 : qopmode_o_mux <= qopmode_o_reg1; + default : begin + $display("Attribute Syntax Error : The attribute OPMODEREG on DSP48A1 instance %m is set to %d. Legal values for this attribute are 0 or 1.", OPMODEREG); + $finish; + end + endcase + end + + + +//---------------------------------------------------- +//*** CarryOut/CarryOutF 1 level of register +//---------------------------------------------------- + + always @(carryout_o or qcarryout_o_reg1) begin + case (CARRYOUTREG) + 0 : qcarryout_o_mux <= carryout_o; + 1 : qcarryout_o_mux <= qcarryout_o_reg1; + default : begin + $display("Attribute Syntax Error : The attribute CARRYOUTREG on DSP48A1 instance %m is set to %d. Legal values for this attribute are 0 or 1.", OPMODEREG); + $finish; + end + endcase + end +//---------------------------------------------------- +//*** DRC for OPMODE +//---------------------------------------------------- + + always @(qopmode_o_mux or carryinsel_attr or qz_o_mux or qx_o_mux or qcarryin_o_mux) begin + + if ($time > 100000) begin // no check at first 100ns + + case ({qopmode_o_mux, carryinsel_attr}) + + 9'b000000000 : deassign_xz_mux; + 9'b000100000 : deassign_xz_mux; + 9'b001000000 : deassign_xz_mux; + 9'b001100000 : deassign_xz_mux; + 9'b010000000 : deassign_xz_mux; + 9'b010100000 : deassign_xz_mux; + 9'b011000000 : deassign_xz_mux; + 9'b011100000 : deassign_xz_mux; + 9'b100000000 : deassign_xz_mux; + 9'b100100000 : deassign_xz_mux; + 9'b101000000 : deassign_xz_mux; + 9'b101100000 : deassign_xz_mux; + 9'b110000000 : deassign_xz_mux; + 9'b110100000 : deassign_xz_mux; + 9'b111000000 : deassign_xz_mux; + 9'b111100000 : deassign_xz_mux; + 9'b000000001 : deassign_xz_mux; + 9'b000100001 : deassign_xz_mux; + 9'b001000001 : deassign_xz_mux; + 9'b001100001 : deassign_xz_mux; + 9'b010000001 : deassign_xz_mux; + 9'b010100001 : deassign_xz_mux; + 9'b011000001 : deassign_xz_mux; + 9'b011100001 : deassign_xz_mux; + 9'b100000001 : deassign_xz_mux; + 9'b100100001 : deassign_xz_mux; + 9'b101000001 : deassign_xz_mux; + 9'b101100001 : deassign_xz_mux; + 9'b110000001 : deassign_xz_mux; + 9'b110100001 : deassign_xz_mux; + 9'b111000001 : deassign_xz_mux; + 9'b111100001 : deassign_xz_mux; + 9'b000000100 : if (PREG != 1) display_invalid_opmode; else deassign_xz_mux; + 9'b000000101 : if (PREG != 1) display_invalid_opmode; else deassign_xz_mux; + 9'b000100100 : if (PREG != 1) display_invalid_opmode; else deassign_xz_mux; + 9'b000100101 : if (PREG != 1) display_invalid_opmode; else deassign_xz_mux; + 9'b001000100 : if (PREG != 1) display_invalid_opmode; else deassign_xz_mux; + 9'b001000101 : if (PREG != 1) display_invalid_opmode; else deassign_xz_mux; + 9'b001100100 : if (PREG != 1) display_invalid_opmode; else deassign_xz_mux; + 9'b001100101 : if (PREG != 1) display_invalid_opmode; else deassign_xz_mux; + 9'b010000100 : if (PREG != 1) display_invalid_opmode; else deassign_xz_mux; + 9'b010000101 : if (PREG != 1) display_invalid_opmode; else deassign_xz_mux; + 9'b010100100 : if (PREG != 1) display_invalid_opmode; else deassign_xz_mux; + 9'b010100101 : if (PREG != 1) display_invalid_opmode; else deassign_xz_mux; + 9'b011000100 : if (PREG != 1) display_invalid_opmode; else deassign_xz_mux; + 9'b011000101 : if (PREG != 1) display_invalid_opmode; else deassign_xz_mux; + 9'b011100100 : if (PREG != 1) display_invalid_opmode; else deassign_xz_mux; + 9'b011100101 : if (PREG != 1) display_invalid_opmode; else deassign_xz_mux; + 9'b100000100 : if (PREG != 1) display_invalid_opmode; else deassign_xz_mux; + 9'b100000101 : if (PREG != 1) display_invalid_opmode; else deassign_xz_mux; + 9'b100100100 : if (PREG != 1) display_invalid_opmode; else deassign_xz_mux; + 9'b100100101 : if (PREG != 1) display_invalid_opmode; else deassign_xz_mux; + 9'b101000100 : if (PREG != 1) display_invalid_opmode; else deassign_xz_mux; + 9'b101000101 : if (PREG != 1) display_invalid_opmode; else deassign_xz_mux; + 9'b101100100 : if (PREG != 1) display_invalid_opmode; else deassign_xz_mux; + 9'b101100101 : if (PREG != 1) display_invalid_opmode; else deassign_xz_mux; + 9'b110000100 : if (PREG != 1) display_invalid_opmode; else deassign_xz_mux; + 9'b110000101 : if (PREG != 1) display_invalid_opmode; else deassign_xz_mux; + 9'b110100100 : if (PREG != 1) display_invalid_opmode; else deassign_xz_mux; + 9'b110100101 : if (PREG != 1) display_invalid_opmode; else deassign_xz_mux; + 9'b111000100 : if (PREG != 1) display_invalid_opmode; else deassign_xz_mux; + 9'b111000101 : if (PREG != 1) display_invalid_opmode; else deassign_xz_mux; + 9'b111100100 : if (PREG != 1) display_invalid_opmode; else deassign_xz_mux; + 9'b111100101 : if (PREG != 1) display_invalid_opmode; else deassign_xz_mux; + 9'b000000110 : deassign_xz_mux; + 9'b000000111 : deassign_xz_mux; + 9'b001000110 : deassign_xz_mux; + 9'b001000111 : deassign_xz_mux; + 9'b010000110 : deassign_xz_mux; + 9'b010000111 : deassign_xz_mux; + 9'b011000110 : deassign_xz_mux; + 9'b011000111 : deassign_xz_mux; + 9'b100000110 : deassign_xz_mux; + 9'b100000111 : deassign_xz_mux; + 9'b101000110 : deassign_xz_mux; + 9'b101000111 : deassign_xz_mux; + 9'b110000110 : deassign_xz_mux; + 9'b110000111 : deassign_xz_mux; + 9'b111000110 : deassign_xz_mux; + 9'b111000111 : deassign_xz_mux; + 9'b000100110 : deassign_xz_mux; + 9'b000100111 : deassign_xz_mux; + 9'b001100110 : deassign_xz_mux; + 9'b001100111 : deassign_xz_mux; + 9'b010100110 : deassign_xz_mux; + 9'b010100111 : deassign_xz_mux; + 9'b011100110 : deassign_xz_mux; + 9'b011100111 : deassign_xz_mux; + 9'b100100110 : deassign_xz_mux; + 9'b100100111 : deassign_xz_mux; + 9'b101100110 : deassign_xz_mux; + 9'b101100111 : deassign_xz_mux; + 9'b110100110 : deassign_xz_mux; + 9'b110100111 : deassign_xz_mux; + 9'b111100110 : deassign_xz_mux; + 9'b111100111 : deassign_xz_mux; + 9'b000000010 : deassign_xz_mux; + 9'b000000011 : deassign_xz_mux; + 9'b001000010 : deassign_xz_mux; + 9'b001000011 : deassign_xz_mux; + 9'b010000010 : deassign_xz_mux; + 9'b010000011 : deassign_xz_mux; + 9'b011000010 : deassign_xz_mux; + 9'b011000011 : deassign_xz_mux; + 9'b100000010 : deassign_xz_mux; + 9'b100000011 : deassign_xz_mux; + 9'b101000010 : deassign_xz_mux; + 9'b101000011 : deassign_xz_mux; + 9'b110000010 : deassign_xz_mux; + 9'b110000011 : deassign_xz_mux; + 9'b111000010 : deassign_xz_mux; + 9'b111000011 : deassign_xz_mux; + 9'b000100010 : deassign_xz_mux; + 9'b000100011 : deassign_xz_mux; + 9'b001100010 : deassign_xz_mux; + 9'b001100011 : deassign_xz_mux; + 9'b100100010 : deassign_xz_mux; + 9'b100100011 : deassign_xz_mux; + 9'b101100010 : deassign_xz_mux; + 9'b101100011 : deassign_xz_mux; + 9'b010100010 : deassign_xz_mux; + 9'b010100011 : deassign_xz_mux; + 9'b011100010 : deassign_xz_mux; + 9'b011100011 : deassign_xz_mux; + 9'b110100010 : deassign_xz_mux; + 9'b110100011 : deassign_xz_mux; + 9'b111100010 : deassign_xz_mux; + 9'b111100011 : deassign_xz_mux; + 9'b000001000 : deassign_xz_mux; + 9'b000001001 : deassign_xz_mux; + 9'b000101000 : deassign_xz_mux; + 9'b000101001 : deassign_xz_mux; + 9'b001001000 : deassign_xz_mux; + 9'b001001001 : deassign_xz_mux; + 9'b001101000 : deassign_xz_mux; + 9'b001101001 : deassign_xz_mux; + 9'b010001000 : deassign_xz_mux; + 9'b010001001 : deassign_xz_mux; + 9'b010101000 : deassign_xz_mux; + 9'b010101001 : deassign_xz_mux; + 9'b011001000 : deassign_xz_mux; + 9'b011001001 : deassign_xz_mux; + 9'b011101000 : deassign_xz_mux; + 9'b011101001 : deassign_xz_mux; + 9'b100001000 : deassign_xz_mux; + 9'b100001001 : deassign_xz_mux; + 9'b100101000 : deassign_xz_mux; + 9'b100101001 : deassign_xz_mux; + 9'b101001000 : deassign_xz_mux; + 9'b101001001 : deassign_xz_mux; + 9'b101101000 : deassign_xz_mux; + 9'b101101001 : deassign_xz_mux; + 9'b110001000 : deassign_xz_mux; + 9'b110001001 : deassign_xz_mux; + 9'b110101000 : deassign_xz_mux; + 9'b110101001 : deassign_xz_mux; + 9'b111001000 : deassign_xz_mux; + 9'b111001001 : deassign_xz_mux; + 9'b111101000 : deassign_xz_mux; + 9'b111101001 : deassign_xz_mux; + 9'b000001100 : if (PREG != 1) display_invalid_opmode; else deassign_xz_mux; + 9'b000001101 : if (PREG != 1) display_invalid_opmode; else deassign_xz_mux; + 9'b000101100 : if (PREG != 1) display_invalid_opmode; else deassign_xz_mux; + 9'b000101101 : if (PREG != 1) display_invalid_opmode; else deassign_xz_mux; + 9'b001001100 : if (PREG != 1) display_invalid_opmode; else deassign_xz_mux; + 9'b001001101 : if (PREG != 1) display_invalid_opmode; else deassign_xz_mux; + 9'b001101100 : if (PREG != 1) display_invalid_opmode; else deassign_xz_mux; + 9'b001101101 : if (PREG != 1) display_invalid_opmode; else deassign_xz_mux; + 9'b010001100 : if (PREG != 1) display_invalid_opmode; else deassign_xz_mux; + 9'b010001101 : if (PREG != 1) display_invalid_opmode; else deassign_xz_mux; + 9'b010101100 : if (PREG != 1) display_invalid_opmode; else deassign_xz_mux; + 9'b010101101 : if (PREG != 1) display_invalid_opmode; else deassign_xz_mux; + 9'b011001100 : if (PREG != 1) display_invalid_opmode; else deassign_xz_mux; + 9'b011001101 : if (PREG != 1) display_invalid_opmode; else deassign_xz_mux; + 9'b011101100 : if (PREG != 1) display_invalid_opmode; else deassign_xz_mux; + 9'b011101101 : if (PREG != 1) display_invalid_opmode; else deassign_xz_mux; + 9'b100001100 : if (PREG != 1) display_invalid_opmode; else deassign_xz_mux; + 9'b100001101 : if (PREG != 1) display_invalid_opmode; else deassign_xz_mux; + 9'b100101100 : if (PREG != 1) display_invalid_opmode; else deassign_xz_mux; + 9'b100101101 : if (PREG != 1) display_invalid_opmode; else deassign_xz_mux; + 9'b101001100 : if (PREG != 1) display_invalid_opmode; else deassign_xz_mux; + 9'b101001101 : if (PREG != 1) display_invalid_opmode; else deassign_xz_mux; + 9'b101101100 : if (PREG != 1) display_invalid_opmode; else deassign_xz_mux; + 9'b101101101 : if (PREG != 1) display_invalid_opmode; else deassign_xz_mux; + 9'b110001100 : if (PREG != 1) display_invalid_opmode; else deassign_xz_mux; + 9'b110001101 : if (PREG != 1) display_invalid_opmode; else deassign_xz_mux; + 9'b110101100 : if (PREG != 1) display_invalid_opmode; else deassign_xz_mux; + 9'b110101101 : if (PREG != 1) display_invalid_opmode; else deassign_xz_mux; + 9'b111001100 : if (PREG != 1) display_invalid_opmode; else deassign_xz_mux; + 9'b111001101 : if (PREG != 1) display_invalid_opmode; else deassign_xz_mux; + 9'b111101100 : if (PREG != 1) display_invalid_opmode; else deassign_xz_mux; + 9'b111101101 : if (PREG != 1) display_invalid_opmode; else deassign_xz_mux; + 9'b000001110 : deassign_xz_mux; + 9'b000001111 : deassign_xz_mux; + 9'b001001110 : deassign_xz_mux; + 9'b001001111 : deassign_xz_mux; + 9'b010001110 : deassign_xz_mux; + 9'b010001111 : deassign_xz_mux; + 9'b011001110 : deassign_xz_mux; + 9'b011001111 : deassign_xz_mux; + 9'b100001110 : deassign_xz_mux; + 9'b100001111 : deassign_xz_mux; + 9'b101001110 : deassign_xz_mux; + 9'b101001111 : deassign_xz_mux; + 9'b110001110 : deassign_xz_mux; + 9'b110001111 : deassign_xz_mux; + 9'b111001110 : deassign_xz_mux; + 9'b111001111 : deassign_xz_mux; + 9'b000101110 : deassign_xz_mux; + 9'b000101111 : deassign_xz_mux; + 9'b001101110 : deassign_xz_mux; + 9'b001101111 : deassign_xz_mux; + 9'b010101110 : deassign_xz_mux; + 9'b010101111 : deassign_xz_mux; + 9'b011101110 : deassign_xz_mux; + 9'b011101111 : deassign_xz_mux; + 9'b100101110 : deassign_xz_mux; + 9'b100101111 : deassign_xz_mux; + 9'b101101110 : deassign_xz_mux; + 9'b101101111 : deassign_xz_mux; + 9'b110101110 : deassign_xz_mux; + 9'b110101111 : deassign_xz_mux; + 9'b111101110 : deassign_xz_mux; + 9'b111101111 : deassign_xz_mux; + 9'b000001010 : deassign_xz_mux; + 9'b000001011 : deassign_xz_mux; + 9'b001001010 : deassign_xz_mux; + 9'b001001011 : deassign_xz_mux; + 9'b010001010 : deassign_xz_mux; + 9'b010001011 : deassign_xz_mux; + 9'b011001010 : deassign_xz_mux; + 9'b011001011 : deassign_xz_mux; + 9'b100001010 : deassign_xz_mux; + 9'b100001011 : deassign_xz_mux; + 9'b101001010 : deassign_xz_mux; + 9'b101001011 : deassign_xz_mux; + 9'b110001010 : deassign_xz_mux; + 9'b110001011 : deassign_xz_mux; + 9'b111001010 : deassign_xz_mux; + 9'b111001011 : deassign_xz_mux; + 9'b000101010 : deassign_xz_mux; + 9'b000101011 : deassign_xz_mux; + 9'b001101010 : deassign_xz_mux; + 9'b001101011 : deassign_xz_mux; + 9'b100101010 : deassign_xz_mux; + 9'b100101011 : deassign_xz_mux; + 9'b101101010 : deassign_xz_mux; + 9'b101101011 : deassign_xz_mux; + 9'b010101010 : deassign_xz_mux; + 9'b010101011 : deassign_xz_mux; + 9'b011101010 : deassign_xz_mux; + 9'b011101011 : deassign_xz_mux; + 9'b110101010 : deassign_xz_mux; + 9'b110101011 : deassign_xz_mux; + 9'b111101010 : deassign_xz_mux; + 9'b111101011 : deassign_xz_mux; + 9'b000010000 : if (PREG != 1) display_invalid_opmode; else deassign_xz_mux; + 9'b000010001 : if (PREG != 1) display_invalid_opmode; else deassign_xz_mux; + 9'b000110000 : if (PREG != 1) display_invalid_opmode; else deassign_xz_mux; + 9'b000110001 : if (PREG != 1) display_invalid_opmode; else deassign_xz_mux; + 9'b001010000 : if (PREG != 1) display_invalid_opmode; else deassign_xz_mux; + 9'b001010001 : if (PREG != 1) display_invalid_opmode; else deassign_xz_mux; + 9'b001110000 : if (PREG != 1) display_invalid_opmode; else deassign_xz_mux; + 9'b001110001 : if (PREG != 1) display_invalid_opmode; else deassign_xz_mux; + 9'b010010000 : if (PREG != 1) display_invalid_opmode; else deassign_xz_mux; + 9'b010010001 : if (PREG != 1) display_invalid_opmode; else deassign_xz_mux; + 9'b010110000 : if (PREG != 1) display_invalid_opmode; else deassign_xz_mux; + 9'b010110001 : if (PREG != 1) display_invalid_opmode; else deassign_xz_mux; + 9'b011010000 : if (PREG != 1) display_invalid_opmode; else deassign_xz_mux; + 9'b011010001 : if (PREG != 1) display_invalid_opmode; else deassign_xz_mux; + 9'b011110000 : if (PREG != 1) display_invalid_opmode; else deassign_xz_mux; + 9'b011110001 : if (PREG != 1) display_invalid_opmode; else deassign_xz_mux; + 9'b100010000 : if (PREG != 1) display_invalid_opmode; else deassign_xz_mux; + 9'b100010001 : if (PREG != 1) display_invalid_opmode; else deassign_xz_mux; + 9'b100110000 : if (PREG != 1) display_invalid_opmode; else deassign_xz_mux; + 9'b100110001 : if (PREG != 1) display_invalid_opmode; else deassign_xz_mux; + 9'b101010000 : if (PREG != 1) display_invalid_opmode; else deassign_xz_mux; + 9'b101010001 : if (PREG != 1) display_invalid_opmode; else deassign_xz_mux; + 9'b101110000 : if (PREG != 1) display_invalid_opmode; else deassign_xz_mux; + 9'b101110001 : if (PREG != 1) display_invalid_opmode; else deassign_xz_mux; + 9'b110010000 : if (PREG != 1) display_invalid_opmode; else deassign_xz_mux; + 9'b110010001 : if (PREG != 1) display_invalid_opmode; else deassign_xz_mux; + 9'b110110000 : if (PREG != 1) display_invalid_opmode; else deassign_xz_mux; + 9'b110110001 : if (PREG != 1) display_invalid_opmode; else deassign_xz_mux; + 9'b111010000 : if (PREG != 1) display_invalid_opmode; else deassign_xz_mux; + 9'b111010001 : if (PREG != 1) display_invalid_opmode; else deassign_xz_mux; + 9'b111110000 : if (PREG != 1) display_invalid_opmode; else deassign_xz_mux; + 9'b111110001 : if (PREG != 1) display_invalid_opmode; else deassign_xz_mux; + 9'b000010100 : if (PREG != 1) display_invalid_opmode; else deassign_xz_mux; + 9'b000010101 : if (PREG != 1) display_invalid_opmode; else deassign_xz_mux; + 9'b000110100 : if (PREG != 1) display_invalid_opmode; else deassign_xz_mux; + 9'b000110101 : if (PREG != 1) display_invalid_opmode; else deassign_xz_mux; + 9'b001010100 : if (PREG != 1) display_invalid_opmode; else deassign_xz_mux; + 9'b001010101 : if (PREG != 1) display_invalid_opmode; else deassign_xz_mux; + 9'b001110100 : if (PREG != 1) display_invalid_opmode; else deassign_xz_mux; + 9'b001110101 : if (PREG != 1) display_invalid_opmode; else deassign_xz_mux; + 9'b010010100 : if (PREG != 1) display_invalid_opmode; else deassign_xz_mux; + 9'b010010101 : if (PREG != 1) display_invalid_opmode; else deassign_xz_mux; + 9'b010110100 : if (PREG != 1) display_invalid_opmode; else deassign_xz_mux; + 9'b010110101 : if (PREG != 1) display_invalid_opmode; else deassign_xz_mux; + 9'b011010100 : if (PREG != 1) display_invalid_opmode; else deassign_xz_mux; + 9'b011010101 : if (PREG != 1) display_invalid_opmode; else deassign_xz_mux; + 9'b011110100 : if (PREG != 1) display_invalid_opmode; else deassign_xz_mux; + 9'b011110101 : if (PREG != 1) display_invalid_opmode; else deassign_xz_mux; + 9'b100010100 : if (PREG != 1) display_invalid_opmode; else deassign_xz_mux; + 9'b100010101 : if (PREG != 1) display_invalid_opmode; else deassign_xz_mux; + 9'b100110100 : if (PREG != 1) display_invalid_opmode; else deassign_xz_mux; + 9'b100110101 : if (PREG != 1) display_invalid_opmode; else deassign_xz_mux; + 9'b101010100 : if (PREG != 1) display_invalid_opmode; else deassign_xz_mux; + 9'b101010101 : if (PREG != 1) display_invalid_opmode; else deassign_xz_mux; + 9'b101110100 : if (PREG != 1) display_invalid_opmode; else deassign_xz_mux; + 9'b101110101 : if (PREG != 1) display_invalid_opmode; else deassign_xz_mux; + 9'b110010100 : if (PREG != 1) display_invalid_opmode; else deassign_xz_mux; + 9'b110010101 : if (PREG != 1) display_invalid_opmode; else deassign_xz_mux; + 9'b110110100 : if (PREG != 1) display_invalid_opmode; else deassign_xz_mux; + 9'b110110101 : if (PREG != 1) display_invalid_opmode; else deassign_xz_mux; + 9'b111010100 : if (PREG != 1) display_invalid_opmode; else deassign_xz_mux; + 9'b111010101 : if (PREG != 1) display_invalid_opmode; else deassign_xz_mux; + 9'b111110100 : if (PREG != 1) display_invalid_opmode; else deassign_xz_mux; + 9'b111110101 : if (PREG != 1) display_invalid_opmode; else deassign_xz_mux; + 9'b000010110 : if (PREG != 1) display_invalid_opmode; else deassign_xz_mux; + 9'b000010111 : if (PREG != 1) display_invalid_opmode; else deassign_xz_mux; + 9'b001010110 : if (PREG != 1) display_invalid_opmode; else deassign_xz_mux; + 9'b001010111 : if (PREG != 1) display_invalid_opmode; else deassign_xz_mux; + 9'b010010110 : if (PREG != 1) display_invalid_opmode; else deassign_xz_mux; + 9'b010010111 : if (PREG != 1) display_invalid_opmode; else deassign_xz_mux; + 9'b011010110 : if (PREG != 1) display_invalid_opmode; else deassign_xz_mux; + 9'b011010111 : if (PREG != 1) display_invalid_opmode; else deassign_xz_mux; + 9'b100010110 : if (PREG != 1) display_invalid_opmode; else deassign_xz_mux; + 9'b100010111 : if (PREG != 1) display_invalid_opmode; else deassign_xz_mux; + 9'b101010110 : if (PREG != 1) display_invalid_opmode; else deassign_xz_mux; + 9'b101010111 : if (PREG != 1) display_invalid_opmode; else deassign_xz_mux; + 9'b110010110 : if (PREG != 1) display_invalid_opmode; else deassign_xz_mux; + 9'b110010111 : if (PREG != 1) display_invalid_opmode; else deassign_xz_mux; + 9'b111010110 : if (PREG != 1) display_invalid_opmode; else deassign_xz_mux; + 9'b111010111 : if (PREG != 1) display_invalid_opmode; else deassign_xz_mux; + 9'b000110110 : if (PREG != 1) display_invalid_opmode; else deassign_xz_mux; + 9'b000110111 : if (PREG != 1) display_invalid_opmode; else deassign_xz_mux; + 9'b001110110 : if (PREG != 1) display_invalid_opmode; else deassign_xz_mux; + 9'b001110111 : if (PREG != 1) display_invalid_opmode; else deassign_xz_mux; + 9'b010110110 : if (PREG != 1) display_invalid_opmode; else deassign_xz_mux; + 9'b010110111 : if (PREG != 1) display_invalid_opmode; else deassign_xz_mux; + 9'b011110110 : if (PREG != 1) display_invalid_opmode; else deassign_xz_mux; + 9'b011110111 : if (PREG != 1) display_invalid_opmode; else deassign_xz_mux; + 9'b100110110 : if (PREG != 1) display_invalid_opmode; else deassign_xz_mux; + 9'b100110111 : if (PREG != 1) display_invalid_opmode; else deassign_xz_mux; + 9'b101110110 : if (PREG != 1) display_invalid_opmode; else deassign_xz_mux; + 9'b101110111 : if (PREG != 1) display_invalid_opmode; else deassign_xz_mux; + 9'b110110110 : if (PREG != 1) display_invalid_opmode; else deassign_xz_mux; + 9'b110110111 : if (PREG != 1) display_invalid_opmode; else deassign_xz_mux; + 9'b111110110 : if (PREG != 1) display_invalid_opmode; else deassign_xz_mux; + 9'b111110111 : if (PREG != 1) display_invalid_opmode; else deassign_xz_mux; + 9'b000010010 : if (PREG != 1) display_invalid_opmode; else deassign_xz_mux; + 9'b000010011 : if (PREG != 1) display_invalid_opmode; else deassign_xz_mux; + 9'b001010010 : if (PREG != 1) display_invalid_opmode; else deassign_xz_mux; + 9'b001010011 : if (PREG != 1) display_invalid_opmode; else deassign_xz_mux; + 9'b010010010 : if (PREG != 1) display_invalid_opmode; else deassign_xz_mux; + 9'b010010011 : if (PREG != 1) display_invalid_opmode; else deassign_xz_mux; + 9'b011010010 : if (PREG != 1) display_invalid_opmode; else deassign_xz_mux; + 9'b011010011 : if (PREG != 1) display_invalid_opmode; else deassign_xz_mux; + 9'b100010010 : if (PREG != 1) display_invalid_opmode; else deassign_xz_mux; + 9'b100010011 : if (PREG != 1) display_invalid_opmode; else deassign_xz_mux; + 9'b101010010 : if (PREG != 1) display_invalid_opmode; else deassign_xz_mux; + 9'b101010011 : if (PREG != 1) display_invalid_opmode; else deassign_xz_mux; + 9'b110010010 : if (PREG != 1) display_invalid_opmode; else deassign_xz_mux; + 9'b110010011 : if (PREG != 1) display_invalid_opmode; else deassign_xz_mux; + 9'b111010010 : if (PREG != 1) display_invalid_opmode; else deassign_xz_mux; + 9'b111010011 : if (PREG != 1) display_invalid_opmode; else deassign_xz_mux; + 9'b000110010 : if (PREG != 1) display_invalid_opmode; else deassign_xz_mux; + 9'b000110011 : if (PREG != 1) display_invalid_opmode; else deassign_xz_mux; + 9'b001110010 : if (PREG != 1) display_invalid_opmode; else deassign_xz_mux; + 9'b001110011 : if (PREG != 1) display_invalid_opmode; else deassign_xz_mux; + 9'b100110010 : if (PREG != 1) display_invalid_opmode; else deassign_xz_mux; + 9'b100110011 : if (PREG != 1) display_invalid_opmode; else deassign_xz_mux; + 9'b101110010 : if (PREG != 1) display_invalid_opmode; else deassign_xz_mux; + 9'b101110011 : if (PREG != 1) display_invalid_opmode; else deassign_xz_mux; + 9'b010110010 : if (PREG != 1) display_invalid_opmode; else deassign_xz_mux; + 9'b010110011 : if (PREG != 1) display_invalid_opmode; else deassign_xz_mux; + 9'b011110010 : if (PREG != 1) display_invalid_opmode; else deassign_xz_mux; + 9'b011110011 : if (PREG != 1) display_invalid_opmode; else deassign_xz_mux; + 9'b110110010 : if (PREG != 1) display_invalid_opmode; else deassign_xz_mux; + 9'b110110011 : if (PREG != 1) display_invalid_opmode; else deassign_xz_mux; + 9'b111110010 : if (PREG != 1) display_invalid_opmode; else deassign_xz_mux; + 9'b111110011 : if (PREG != 1) display_invalid_opmode; else deassign_xz_mux; + 9'b000011000 : deassign_xz_mux; + 9'b000011001 : deassign_xz_mux; + 9'b000111000 : deassign_xz_mux; + 9'b000111001 : deassign_xz_mux; + 9'b001011000 : deassign_xz_mux; + 9'b001011001 : deassign_xz_mux; + 9'b001111000 : deassign_xz_mux; + 9'b001111001 : deassign_xz_mux; + 9'b010011000 : deassign_xz_mux; + 9'b010011001 : deassign_xz_mux; + 9'b010111000 : deassign_xz_mux; + 9'b010111001 : deassign_xz_mux; + 9'b011011000 : deassign_xz_mux; + 9'b011011001 : deassign_xz_mux; + 9'b011111000 : deassign_xz_mux; + 9'b011111001 : deassign_xz_mux; + 9'b100011000 : deassign_xz_mux; + 9'b100011001 : deassign_xz_mux; + 9'b100111000 : deassign_xz_mux; + 9'b100111001 : deassign_xz_mux; + 9'b101011000 : deassign_xz_mux; + 9'b101011001 : deassign_xz_mux; + 9'b101111000 : deassign_xz_mux; + 9'b101111001 : deassign_xz_mux; + 9'b110011000 : deassign_xz_mux; + 9'b110011001 : deassign_xz_mux; + 9'b110111000 : deassign_xz_mux; + 9'b110111001 : deassign_xz_mux; + 9'b111011000 : deassign_xz_mux; + 9'b111011001 : deassign_xz_mux; + 9'b111111000 : deassign_xz_mux; + 9'b111111001 : deassign_xz_mux; + 9'b000011100 : if (PREG != 1) display_invalid_opmode; else deassign_xz_mux; + 9'b000011101 : if (PREG != 1) display_invalid_opmode; else deassign_xz_mux; + 9'b000111100 : if (PREG != 1) display_invalid_opmode; else deassign_xz_mux; + 9'b000111101 : if (PREG != 1) display_invalid_opmode; else deassign_xz_mux; + 9'b001011100 : if (PREG != 1) display_invalid_opmode; else deassign_xz_mux; + 9'b001011101 : if (PREG != 1) display_invalid_opmode; else deassign_xz_mux; + 9'b001111100 : if (PREG != 1) display_invalid_opmode; else deassign_xz_mux; + 9'b001111101 : if (PREG != 1) display_invalid_opmode; else deassign_xz_mux; + 9'b010011100 : if (PREG != 1) display_invalid_opmode; else deassign_xz_mux; + 9'b010011101 : if (PREG != 1) display_invalid_opmode; else deassign_xz_mux; + 9'b010111100 : if (PREG != 1) display_invalid_opmode; else deassign_xz_mux; + 9'b010111101 : if (PREG != 1) display_invalid_opmode; else deassign_xz_mux; + 9'b011011100 : if (PREG != 1) display_invalid_opmode; else deassign_xz_mux; + 9'b011011101 : if (PREG != 1) display_invalid_opmode; else deassign_xz_mux; + 9'b011111100 : if (PREG != 1) display_invalid_opmode; else deassign_xz_mux; + 9'b011111101 : if (PREG != 1) display_invalid_opmode; else deassign_xz_mux; + 9'b100011100 : if (PREG != 1) display_invalid_opmode; else deassign_xz_mux; + 9'b100011101 : if (PREG != 1) display_invalid_opmode; else deassign_xz_mux; + 9'b100111100 : if (PREG != 1) display_invalid_opmode; else deassign_xz_mux; + 9'b100111101 : if (PREG != 1) display_invalid_opmode; else deassign_xz_mux; + 9'b101011100 : if (PREG != 1) display_invalid_opmode; else deassign_xz_mux; + 9'b101011101 : if (PREG != 1) display_invalid_opmode; else deassign_xz_mux; + 9'b101111100 : if (PREG != 1) display_invalid_opmode; else deassign_xz_mux; + 9'b101111101 : if (PREG != 1) display_invalid_opmode; else deassign_xz_mux; + 9'b110011100 : if (PREG != 1) display_invalid_opmode; else deassign_xz_mux; + 9'b110011101 : if (PREG != 1) display_invalid_opmode; else deassign_xz_mux; + 9'b110111100 : if (PREG != 1) display_invalid_opmode; else deassign_xz_mux; + 9'b110111101 : if (PREG != 1) display_invalid_opmode; else deassign_xz_mux; + 9'b111011100 : if (PREG != 1) display_invalid_opmode; else deassign_xz_mux; + 9'b111011101 : if (PREG != 1) display_invalid_opmode; else deassign_xz_mux; + 9'b111111100 : if (PREG != 1) display_invalid_opmode; else deassign_xz_mux; + 9'b111111101 : if (PREG != 1) display_invalid_opmode; else deassign_xz_mux; + 9'b000011110 : deassign_xz_mux; + 9'b000011111 : deassign_xz_mux; + 9'b001011110 : deassign_xz_mux; + 9'b001011111 : deassign_xz_mux; + 9'b010011110 : deassign_xz_mux; + 9'b010011111 : deassign_xz_mux; + 9'b011011110 : deassign_xz_mux; + 9'b011011111 : deassign_xz_mux; + 9'b100011110 : deassign_xz_mux; + 9'b100011111 : deassign_xz_mux; + 9'b101011110 : deassign_xz_mux; + 9'b101011111 : deassign_xz_mux; + 9'b110011110 : deassign_xz_mux; + 9'b110011111 : deassign_xz_mux; + 9'b111011110 : deassign_xz_mux; + 9'b111011111 : deassign_xz_mux; + 9'b000011010 : deassign_xz_mux; + 9'b000011011 : deassign_xz_mux; + 9'b001011010 : deassign_xz_mux; + 9'b001011011 : deassign_xz_mux; + 9'b010011010 : deassign_xz_mux; + 9'b010011011 : deassign_xz_mux; + 9'b011011010 : deassign_xz_mux; + 9'b011011011 : deassign_xz_mux; + 9'b100011010 : deassign_xz_mux; + 9'b100011011 : deassign_xz_mux; + 9'b101011010 : deassign_xz_mux; + 9'b101011011 : deassign_xz_mux; + 9'b110011010 : deassign_xz_mux; + 9'b110011011 : deassign_xz_mux; + 9'b111011010 : deassign_xz_mux; + 9'b111011011 : deassign_xz_mux; + 9'b000111010 : deassign_xz_mux; + 9'b000111011 : deassign_xz_mux; + 9'b001111010 : deassign_xz_mux; + 9'b001111011 : deassign_xz_mux; + 9'b100111010 : deassign_xz_mux; + 9'b100111011 : deassign_xz_mux; + 9'b101111010 : deassign_xz_mux; + 9'b101111011 : deassign_xz_mux; + 9'b010111010 : deassign_xz_mux; + 9'b010111011 : deassign_xz_mux; + 9'b011111010 : deassign_xz_mux; + 9'b011111011 : deassign_xz_mux; + 9'b110111010 : deassign_xz_mux; + 9'b110111011 : deassign_xz_mux; + 9'b111111010 : deassign_xz_mux; + 9'b111111011 : deassign_xz_mux; + 9'b000111110 : deassign_xz_mux; + 9'b000111111 : deassign_xz_mux; + 9'b001111110 : deassign_xz_mux; + 9'b001111111 : deassign_xz_mux; + 9'b010111110 : deassign_xz_mux; + 9'b010111111 : deassign_xz_mux; + 9'b011111110 : deassign_xz_mux; + 9'b011111111 : deassign_xz_mux; + 9'b100111110 : deassign_xz_mux; + 9'b100111111 : deassign_xz_mux; + 9'b101111110 : deassign_xz_mux; + 9'b101111111 : deassign_xz_mux; + 9'b110111110 : deassign_xz_mux; + 9'b110111111 : deassign_xz_mux; + 9'b111111110 : deassign_xz_mux; + 9'b111111111 : deassign_xz_mux; + default : begin + if (invalid_opmode) begin + + invalid_opmode = 0; + assign qx_o_mux = 48'bx; + assign qz_o_mux = 48'bx; + assign add_o = 48'bx; + $display("OPMODE Input Warning : The OPMODE %b to DSP48A1 instance %m is either invalid or the CARRYINSEL %b for that specific OPMODE at %.3f ns.", qopmode_o_mux, carryinsel_attr, $time/1000.0); + + end + end + + endcase // case(OPMODE) + + end // if ($time > 100000) + +// *** Add/Subtract + if (add_flag) begin + if (qopmode_o_mux[7] == 1'b1) + {carryout_o, add_o} = qz_o_mux - qx_o_mux - qcarryin_o_mux; + else if (qopmode_o_mux[7] == 1'b0) + {carryout_o, add_o} = qz_o_mux + qx_o_mux + qcarryin_o_mux; + end // if (add_flag = 1) + + end // always @ (qopmode_o_mux) + +//---------------------------------------------------- + + task deassign_xz_mux; + begin + add_flag = 1; + invalid_opmode = 1; // reset invalid opmode + deassign qx_o_mux; + deassign qz_o_mux; + deassign add_o; + end + endtask // deassign_xz_mux + + task display_invalid_opmode_no_mreg; + begin + if (invalid_opmode) begin + + add_flag = 0; + invalid_opmode = 0; + assign qx_o_mux = 48'bx; + assign qz_o_mux = 48'bx; + assign add_o = 48'bx; + $display("OPMODE Input Warning : The OPMODE %b with CARRYINSEL %b to DSP48A1 instance %m at %.3f ns requires attribute MREG set to 0.", qopmode_o_mux, carryinsel_attr, $time/1000.0); + end + end + endtask // display_invalid_opmode_no_mreg + + task display_invalid_opmode_mreg; + begin + if (invalid_opmode) begin + add_flag = 0; + invalid_opmode = 0; + assign qx_o_mux = 48'bx; + assign qz_o_mux = 48'bx; + assign add_o = 48'bx; + $display("OPMODE Input Warning : The OPMODE %b with CARRYINSEL %b to DSP48A1 instance %m at %.3f ns requires attribute MREG set to 1.", qopmode_o_mux, carryinsel_attr, $time/1000.0); + end + end + endtask // display_invalid_opmode_mreg + + task display_invalid_opmode; + begin + if (invalid_opmode) begin + add_flag = 0; + invalid_opmode = 0; + assign qx_o_mux = 48'bx; + assign qz_o_mux = 48'bx; + assign add_o = 48'bx; + $display("OPMODE Input Warning : The OPMODE %b to DSP48A1 instance %m at %.3f ns requires attribute PREG set to 1.", qopmode_o_mux, $time/1000.0); + end + end + endtask // display_invalid_opmode + +//---------------------------------------------------- +//*** Output register P with 1 level of register +//---------------------------------------------------- +// Asynchronous Operation + always @(posedge CLK, posedge RSTP) begin + if(rst_async_flag) begin + if(RSTP) begin + qp_o_reg1 <= 48'b0; + end // if RSTP + else if(CEP) begin + qp_o_reg1 <= add_o; + end // CEP + end // if rst_async_flg + end + +// Synchronous Operation + always @(posedge CLK) begin + if (RSTP) + qp_o_reg1 <= 48'b0; + else if (CEP) + qp_o_reg1 <= add_o; + end + + always @(qp_o_reg1 or add_o) begin + case (PREG) + 0 : qp_o_mux <= add_o; + 1 : qp_o_mux <= qp_o_reg1; + default : begin + $display("Attribute Syntax Error : The attribute PREG on DSP48A1 instance %m is set to %d. Legal values for this attribute are 0 or 1.", PREG); + $finish; + end + endcase + end + +//---------------------------------------------------- +//*** CARRYOUT +//---------------------------------------------------- +assign carryout_x_o = qcarryout_o_mux; + + + + assign BCOUT = qb_o_mux; + assign CARRYOUT = carryout_x_o; + assign CARRYOUTF = carryout_x_o; + assign M = qmult_o_mux; + assign P = qp_o_mux; + assign PCOUT = qp_o_mux; + + specify + + (A *> CARRYOUT) = (0:0:0, 0:0:0); + (A *> CARRYOUTF) = (0:0:0, 0:0:0); + (A *> M) = (0:0:0, 0:0:0); + (A *> P) = (0:0:0, 0:0:0); + (A *> PCOUT) = (0:0:0, 0:0:0); + + (B *> BCOUT) = (0:0:0, 0:0:0); + (B *> CARRYOUT) = (0:0:0, 0:0:0); + (B *> CARRYOUTF) = (0:0:0, 0:0:0); + (B *> M) = (0:0:0, 0:0:0); + (B *> P) = (0:0:0, 0:0:0); + (B *> PCOUT) = (0:0:0, 0:0:0); + +// (BCIN *> BCOUT) = (0:0:0, 0:0:0); +// (BCIN *> CARRYOUT) = (0:0:0, 0:0:0); +// (BCIN *> P) = (0:0:0, 0:0:0); +// (BCIN *> PCOUT) = (0:0:0, 0:0:0); + + (C *> CARRYOUT) = (0:0:0, 0:0:0); + (C *> CARRYOUTF) = (0:0:0, 0:0:0); + (C *> M) = (0:0:0, 0:0:0); + (C *> P) = (0:0:0, 0:0:0); + (C *> PCOUT) = (0:0:0, 0:0:0); + + (D *> BCOUT) = (0:0:0, 0:0:0); + (D *> CARRYOUT) = (0:0:0, 0:0:0); + (D *> CARRYOUTF) = (0:0:0, 0:0:0); + (D *> M) = (0:0:0, 0:0:0); + (D *> P) = (0:0:0, 0:0:0); + (D *> PCOUT) = (0:0:0, 0:0:0); + + (CARRYIN *> CARRYOUT) = (0:0:0, 0:0:0); + (CARRYIN *> CARRYOUTF) = (0:0:0, 0:0:0); + (CARRYIN *> M) = (0:0:0, 0:0:0); + (CARRYIN *> P) = (0:0:0, 0:0:0); + (CARRYIN *> PCOUT) = (0:0:0, 0:0:0); + + (CLK *> BCOUT) = (100:100:100, 100:100:100); + (CLK *> CARRYOUT) = (100:100:100, 100:100:100); + (CLK *> CARRYOUTF) = (100:100:100, 100:100:100); + (CLK *> M) = (100:100:100, 100:100:100); + (CLK *> P) = (100:100:100, 100:100:100); + (CLK *> PCOUT) = (100:100:100, 100:100:100); + + (OPMODE *> BCOUT) = (0:0:0, 0:0:0); + (OPMODE *> CARRYOUT) = (0:0:0, 0:0:0); + (OPMODE *> CARRYOUTF) = (0:0:0, 0:0:0); + (OPMODE *> M) = (0:0:0, 0:0:0); + (OPMODE *> P) = (0:0:0, 0:0:0); + (OPMODE *> PCOUT) = (0:0:0, 0:0:0); + + (PCIN *> CARRYOUT) = (0:0:0, 0:0:0); + (PCIN *> CARRYOUTF) = (0:0:0, 0:0:0); + (PCIN *> M) = (0:0:0, 0:0:0); + (PCIN *> P) = (0:0:0, 0:0:0); + (PCIN *> PCOUT) = (0:0:0, 0:0:0); +// Asynchronous + (RSTA *> CARRYOUT) = (0:0:0, 0:0:0); + (RSTA *> CARRYOUTF) = (0:0:0, 0:0:0); + (RSTA *> M) = (0:0:0, 0:0:0); + (RSTA *> P) = (0:0:0, 0:0:0); + (RSTA *> PCOUT) = (0:0:0, 0:0:0); + + (RSTB *> CARRYOUT) = (0:0:0, 0:0:0); + (RSTB *> CARRYOUTF) = (0:0:0, 0:0:0); + (RSTB *> BCOUT) = (0:0:0, 0:0:0); + (RSTB *> M) = (0:0:0, 0:0:0); + (RSTB *> P) = (0:0:0, 0:0:0); + (RSTB *> PCOUT) = (0:0:0, 0:0:0); + + (RSTC *> CARRYOUT) = (0:0:0, 0:0:0); + (RSTC *> CARRYOUTF) = (0:0:0, 0:0:0); + (RSTC *> M) = (0:0:0, 0:0:0); + (RSTC *> P) = (0:0:0, 0:0:0); + (RSTC *> PCOUT) = (0:0:0, 0:0:0); + + (RSTCARRYIN *> CARRYOUT) = (0:0:0, 0:0:0); + (RSTCARRYIN *> CARRYOUTF) = (0:0:0, 0:0:0); + (RSTCARRYIN *> M) = (0:0:0, 0:0:0); + (RSTCARRYIN *> P) = (0:0:0, 0:0:0); + (RSTCARRYIN *> PCOUT) = (0:0:0, 0:0:0); + + (RSTD *> BCOUT) = (0:0:0, 0:0:0); + (RSTD *> CARRYOUT) = (0:0:0, 0:0:0); + (RSTD *> CARRYOUTF) = (0:0:0, 0:0:0); + (RSTD *> M) = (0:0:0, 0:0:0); + (RSTD *> P) = (0:0:0, 0:0:0); + (RSTD *> PCOUT) = (0:0:0, 0:0:0); + + (RSTM *> CARRYOUT) = (0:0:0, 0:0:0); + (RSTM *> CARRYOUTF) = (0:0:0, 0:0:0); + (RSTM *> M) = (0:0:0, 0:0:0); + (RSTM *> P) = (0:0:0, 0:0:0); + (RSTM *> PCOUT) = (0:0:0, 0:0:0); + + (RSTOPMODE *> BCOUT) = (0:0:0, 0:0:0); + (RSTOPMODE *> CARRYOUT) = (0:0:0, 0:0:0); + (RSTOPMODE *> CARRYOUTF) = (0:0:0, 0:0:0); + (RSTOPMODE *> M) = (0:0:0, 0:0:0); + (RSTOPMODE *> P) = (0:0:0, 0:0:0); + (RSTOPMODE *> PCOUT) = (0:0:0, 0:0:0); + + (RSTP *> P) = (0:0:0, 0:0:0); + (RSTP *> PCOUT) = (0:0:0, 0:0:0); + + specparam PATHPULSE$ = 0; + + endspecify + +endmodule // DSP48A1 + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/DSP48E.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/DSP48E.v new file mode 100644 index 0000000..ff78f8a --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/DSP48E.v @@ -0,0 +1,2897 @@ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / 18X18 Signed Multiplier Followed by Three-Input Adder plus ALU with Pipeline Registers +// /___/ /\ Filename : DSP48E.v +// \ \ / \ Timestamp : Thu Mar 24 16:44:06 PST 2005 +// \___\/\___\ +// +// Revision: +// 03/23/05 - Initial version. +// 05/26/05 - BTrack 191 mult not valid in TWO24/FOUR12/USE_MULT=NONE. +// 06/16/05 - Added MULTSIGNIN/OUT pins and functionality +// 09/29/05 - Made xyz muxes to be sensitive to carryinsel when recovering from invalid opmode/carryinsel +// 10/05/05 - Added more valid DRC check entries. +// 10/25/05 - CR 219047 +// 11/03/05 - Added two DRC checks -- ARITHMETIC and LOGIC +// 11/07/05 - 'X'ed out carrycascout in LOGIC modes (like the carryout) +// 11/21/05 - 'X'ed out pattern detect signals when in illegal opmodes. +// 02/28/06 - CR 225886 -- USE_MULT check updates. +// 02/28/06 - CR 226267 -- Changed USE_MULT default to MULT_S. +// 02/28/06 - CR 226003 -- Added Parameter Types (integer/real) +// 05/28/06 - CR 230656 -- disabled timing checks for all RSTs when GSR is active. +// 12/10/06 - CR 429825 -- Added timing checks for CARRYCASCIN. +// 05/30/07 - Added FAST SIM MODEL +// 06/01/07 - Added wire declaration for internal signals +// 06/29/07 - CR 438456 -- Added DRC to output X when USE_MULT=MULT_S is set and not using the multiplier opmode through muxX +// 10/01/07 - CR 448147 -- Fixed error introduced by 438456 +// 10/10/07 - CR 451453 -- DRC warning timescale +// 10/15/07 - CR 444150 -- DRC check enhancements for OPMODEREG/CARRYINSELREG +// 11/06/07 - CR 451178 -- DRC warning enhancement +// 02/06/08 - CR 455601 -- DRC relax for OPMODEREG/CARRYINSELREG +// 04/17/08 - CR 468871 -- Negative SetupHold fix +// 07/08/08 - CR 473297 and 475997 fix -- removed input buffers that were causing NCSIM failures when sdf was backannotated +// 12/01/09 - CR 532611 -- Spyglass lint error fix -- Define(move) the tasks before the calls +// 04/29/10 - CR 558562 -- Changed keyword "error" to "warning" in a warning message +// End Revision + +`timescale 1 ps / 1 ps + +module DSP48E (ACOUT, BCOUT, CARRYCASCOUT, CARRYOUT, MULTSIGNOUT, OVERFLOW, P, PATTERNBDETECT, PATTERNDETECT, PCOUT, UNDERFLOW, A, ACIN, ALUMODE, B, BCIN, C, CARRYCASCIN, CARRYIN, CARRYINSEL, CEA1, CEA2, CEALUMODE, CEB1, CEB2, CEC, CECARRYIN, CECTRL, CEM, CEMULTCARRYIN, CEP, CLK, MULTSIGNIN, OPMODE, PCIN, RSTA, RSTALLCARRYIN, RSTALUMODE, RSTB, RSTC, RSTCTRL, RSTM, RSTP); + + parameter SIM_MODE = "SAFE"; + + parameter integer ACASCREG = 1; + parameter integer ALUMODEREG = 1; + parameter integer AREG = 1; + parameter AUTORESET_PATTERN_DETECT = "FALSE"; + parameter AUTORESET_PATTERN_DETECT_OPTINV = "MATCH"; + parameter A_INPUT = "DIRECT"; + parameter integer BCASCREG = 1; + parameter integer BREG = 1; + parameter B_INPUT = "DIRECT"; + parameter integer CARRYINREG = 1; + parameter integer CARRYINSELREG = 1; + parameter integer CREG = 1; + parameter MASK = 48'h3FFFFFFFFFFF; + parameter integer MREG = 1; + parameter integer MULTCARRYINREG = 1; + parameter integer OPMODEREG = 1; + parameter PATTERN = 48'h000000000000; + parameter integer PREG = 1; + parameter SEL_MASK = "MASK"; + parameter SEL_PATTERN = "PATTERN"; + parameter SEL_ROUNDING_MASK = "SEL_MASK"; + parameter USE_MULT = "MULT_S"; + parameter USE_PATTERN_DETECT = "NO_PATDET"; + parameter USE_SIMD = "ONE48"; + + output [29:0] ACOUT; + output [17:0] BCOUT; + output CARRYCASCOUT; + output [3:0] CARRYOUT; + output MULTSIGNOUT; + output OVERFLOW; + output [47:0] P; + output PATTERNBDETECT; + output PATTERNDETECT; + output [47:0] PCOUT; + output UNDERFLOW; + + input [29:0] A; + input [29:0] ACIN; + input [3:0] ALUMODE; + input [17:0] B; + input [17:0] BCIN; + input [47:0] C; + input CARRYCASCIN; + input CARRYIN; + input [2:0] CARRYINSEL; + input CEA1; + input CEA2; + input CEALUMODE; + input CEB1; + input CEB2; + input CEC; + input CECARRYIN; + input CECTRL; + input CEM; + input CEMULTCARRYIN; + input CEP; + input CLK; + input MULTSIGNIN; + input [6:0] OPMODE; + input [47:0] PCIN; + input RSTA; + input RSTALLCARRYIN; + input RSTALUMODE; + input RSTB; + input RSTC; + input RSTCTRL; + input RSTM; + input RSTP; + + tri0 GSR = glbl.GSR; + +//------------------- constants ------------------------- + localparam MAX_ACOUT = 30; + localparam MAX_BCOUT = 18; + localparam MAX_CARRYOUT = 4; + localparam MAX_P = 48; + localparam MAX_PCOUT = 48; + + localparam MAX_A = 30; + localparam MAX_ACIN = 30; + localparam MAX_ALUMODE = 4; + localparam MAX_A_MULT = 25; + localparam MAX_B = 18; + localparam MAX_B_MULT = 18; + localparam MAX_BCIN = 18; + localparam MAX_C = 48; + localparam MAX_CARRYINSEL = 3; + localparam MAX_OPMODE = 7; + localparam MAX_PCIN = 48; + + localparam MAX_ALU_FULL = 48; + localparam MAX_ALU_HALF = 24; + localparam MAX_ALU_QUART = 12; + + localparam MSB_ACOUT = MAX_ACOUT - 1; + localparam MSB_BCOUT = MAX_BCOUT - 1; + localparam MSB_CARRYOUT = MAX_CARRYOUT - 1; + localparam MSB_P = MAX_P - 1; + localparam MSB_PCOUT = MAX_PCOUT - 1; + + localparam MSB_A = MAX_A - 1; + localparam MSB_ACIN = MAX_ACIN - 1; + localparam MSB_ALUMODE = MAX_ALUMODE - 1; + localparam MSB_A_MULT = MAX_A_MULT - 1; + localparam MSB_B = MAX_B - 1; + localparam MSB_B_MULT = MAX_B_MULT - 1; + localparam MSB_BCIN = MAX_BCIN - 1; + localparam MSB_C = MAX_C - 1; + localparam MSB_CARRYINSEL = MAX_CARRYINSEL - 1; + localparam MSB_OPMODE = MAX_OPMODE - 1; + localparam MSB_PCIN = MAX_PCIN - 1; + + localparam MSB_ALU_FULL = MAX_ALU_FULL - 1; + localparam MSB_ALU_HALF = MAX_ALU_HALF - 1; + localparam MSB_ALU_QUART = MAX_ALU_QUART - 1; + + localparam SHIFT_MUXZ = 17; + + reg [29:0] a_o_mux, qa_o_mux, qa_o_reg1, qa_o_reg2, qacout_o_mux; + reg [17:0] b_o_mux, qb_o_mux, qb_o_reg1, qb_o_reg2, qbcout_o_mux; + reg [2:0] qcarryinsel_o_mux, qcarryinsel_o_reg1; + reg [(MSB_A_MULT+MSB_B_MULT+1):0] qmult_o_mux, qmult_o_reg; + reg [47:0] qc_o_mux, qc_o_reg1; + reg [47:0] qp_o_mux, qp_o_reg1; + reg [47:0] qx_o_mux, qy_o_mux, qz_o_mux; + reg [6:0] qopmode_o_mux, qopmode_o_reg1; + + + + reg qcarryin_o_mux0, qcarryin_o_reg0, qcarryin_o_mux7, qcarryin_o_reg7; + reg qcarryin_o_mux, qcarryin_o_reg; + + reg [3:0] qalumode_o_mux, qalumode_o_reg1; + + reg invalid_opmode, opmode_valid_flag, alumode_valid_flag, ping_opmode_drc_check = 0; + + reg [47:0] alu_o; + + reg qmultsignout_o_reg, multsignout_o_mux, multsignout_o_opmode; + + reg [MAX_ALU_FULL:0] alu_full_tmp; + reg [MAX_ALU_HALF:0] alu_hlf1_tmp, alu_hlf2_tmp; + reg [MAX_ALU_QUART:0] alu_qrt1_tmp, alu_qrt2_tmp, alu_qrt3_tmp, alu_qrt4_tmp; + + wire [29:0] ACIN, A; + wire [17:0] BCIN, B; + wire [2:0] CARRYINSEL; + wire [(MSB_A_MULT+MSB_B_MULT+1):0] mult_o; + wire [47:0] PCIN, C; + wire [6:0] OPMODE; + wire [3:0] ALUMODE; + wire pdet_o_mux, pdetb_o_mux; + + reg [47:0] pattern_qp = 0, mask_qp = 0; + reg carrycascout_o; + reg carrycascout_o_reg = 0; + reg carrycascout_o_mux = 0; + + reg [3:0] carryout_o = 0; + reg [3:0] carryout_o_reg = 0; + reg [3:0] carryout_o_mux = 0; + wire [3:0] carryout_x_o; + + reg pdet_o, pdetb_o, pdet_o_reg1, pdet_o_reg2, pdetb_o_reg1, pdetb_o_reg2; + reg overflow_o, underflow_o; + + +generate if (SIM_MODE == "SAFE") begin +//*** GLOBAL hidden GSR pin + always @(GSR) begin + if (GSR) begin + assign qcarryin_o_reg0 = 1'b0; + assign qcarryinsel_o_reg1 = 3'b0; + assign qopmode_o_reg1 = 7'b0; + assign qalumode_o_reg1 = 4'b0; + assign qa_o_reg1 = 30'b0; + assign qa_o_reg2 = 30'b0; + assign qb_o_reg1 = 18'b0; + assign qb_o_reg2 = 18'b0; + assign qc_o_reg1 = 48'b0; + assign qp_o_reg1 = 48'b0; + assign qmult_o_reg = 36'b0; + + assign underflow_o = 1'b0; + assign overflow_o = 1'b0; + assign pdet_o = 1'b0; + assign pdetb_o = 1'b0; + assign pdet_o_reg1 = 1'b0; + assign pdet_o_reg2 = 1'b0; + assign pdetb_o_reg1 = 1'b0; + assign pdetb_o_reg2 = 1'b0; + + assign carryout_o_reg = 4'b0; + assign carrycascout_o_reg = 1'b0; + + assign qmultsignout_o_reg = 1'b0; + end + else begin + deassign qcarryin_o_reg0; + deassign qcarryinsel_o_reg1; + deassign qopmode_o_reg1; + deassign qalumode_o_reg1; + deassign qa_o_reg1; + deassign qa_o_reg2; + deassign qb_o_reg1; + deassign qb_o_reg2; + deassign qc_o_reg1; + deassign qp_o_reg1; + deassign qmult_o_reg; + + deassign underflow_o; + deassign overflow_o; + deassign pdet_o; + deassign pdetb_o; + deassign pdet_o_reg1; + deassign pdet_o_reg2; + deassign pdetb_o_reg1; + deassign pdetb_o_reg2; + + deassign carryout_o_reg; + deassign carrycascout_o_reg; + + deassign qmultsignout_o_reg; + end + end + + + initial begin + opmode_valid_flag <= 1; + alumode_valid_flag <= 1; + invalid_opmode <= 1; + + //-------- AREG check + + case (AREG) + 0, 1, 2 : ; + default : begin + $display("Attribute Syntax Error : The attribute AREG on DSP48E instance %m is set to %d. Legal values for this attribute are 0, 1 or 2.", AREG); + $finish; + end + endcase + + //-------- (ACASCREG) and (ACASCREG vs AREG) check + + case (AREG) + 0 : if(AREG != ACASCREG) begin + $display("Attribute Syntax Error : The attribute ACASCREG on DSP48E instance %m is set to %d. ACASCREG has to be set to 0 when attribute AREG = 0.", ACASCREG); + $finish; + end + 1 : if(AREG != ACASCREG) begin + $display("Attribute Syntax Error : The attribute ACASCREG on DSP48E instance %m is set to %d. ACASCREG has to be set to 1 when attribute AREG = 1.", ACASCREG); + $finish; + end + 2 : if((AREG != ACASCREG) && ((AREG-1) != ACASCREG)) begin + $display("Attribute Syntax Error : The attribute ACASCREG on DSP48E instance %m is set to %d. ACASCREG has to be set to either 2 or 1 when attribute AREG = 2.", ACASCREG); + $finish; + end + default : ; + endcase + + //-------- BREG check + + case (BREG) + 0, 1, 2 : ; + default : begin + $display("Attribute Syntax Error : The attribute BREG on DSP48E instance %m is set to %d. Legal values for this attribute are 0, 1 or 2.", BREG); + $finish; + end + endcase + + //-------- (BCASCREG) and (BCASCREG vs BREG) check + + case (BREG) + 0 : if(BREG != BCASCREG) begin + $display("Attribute Syntax Error : The attribute BCASCREG on DSP48E instance %m is set to %d. BCASCREG has to be set to 0 when attribute BREG = 0.", BCASCREG); + $finish; + end + 1 : if(BREG != BCASCREG) begin + $display("Attribute Syntax Error : The attribute BCASCREG on DSP48E instance %m is set to %d. BCASCREG has to be set to 1 when attribute BREG = 1.", BCASCREG); + $finish; + end + 2 : if((BREG != BCASCREG) && ((BREG-1) != BCASCREG)) begin + $display("Attribute Syntax Error : The attribute BCASCREG on DSP48E instance %m is set to %d. BCASCREG has to be set to either 2 or 1 when attribute BREG = 2.", BCASCREG); + $finish; + end + default : ; + endcase + + + //-------- AUTORESET_PATTERN_DETECT + + case (AUTORESET_PATTERN_DETECT) + "TRUE", "FALSE" : ; + default : begin + $display("Attribute Syntax Error : The attribute AUTORESET_PATTERN_DETECT on DSP48E instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", AUTORESET_PATTERN_DETECT); + $finish; + end + endcase + + //-------- AUTORESET_PATTERN_DETECT_OPTINV + + case (AUTORESET_PATTERN_DETECT_OPTINV) + "MATCH", "NOT_MATCH" : ; + default : begin + $display("Attribute Syntax Error : The attribute AUTORESET_PATTERN_DETECT_OPTINV on DSP48E instance %m is set to %s. Legal values for this attribute are MATCH or NOT_MATCH.", AUTORESET_PATTERN_DETECT_OPTINV); + $finish; + end + endcase + + //-------- USE_MULT + + case (USE_MULT) + "NONE" : ; + "MULT" : if (MREG != 0) begin + $display("Attribute Syntax Error : The attribute USE_MULT on DSP48E instance %m is set to %s. This requires attribute MREG to be set to 0.", USE_MULT); + $finish; + end + "MULT_S" : if (MREG != 1) begin + $display("Attribute Syntax Error : The attribute USE_MULT on DSP48E instance %m is set to %s. This requires attribute MREG to be set to 1.", USE_MULT); + $finish; + end + default : begin + $display("Attribute Syntax Error : The attribute USE_MULT on DSP48E instance %m is set to %s. Legal values for this attribute are NONE, MULT or MULT_S.", USE_MULT); + $finish; + end + endcase + + //-------- USE_PATTERN_DETECT + + case (USE_PATTERN_DETECT) + "PATDET", "NO_PATDET" : ; + default : begin + $display("Attribute Syntax Error : The attribute USE_PATTERN_DETECT on DSP48E instance %m is set to %s. Legal values for this attribute are PATDET or NO_PATDET.", USE_PATTERN_DETECT); + $finish; + end + endcase + + #100010 ping_opmode_drc_check <= 1; + + +//********************************************************* +//*** ADDITIONAL DRC +//********************************************************* +// CR 219407 -- (1) + if((AUTORESET_PATTERN_DETECT == "TRUE") && (USE_PATTERN_DETECT == "NO_PATDET")) begin + $display("Attribute Syntax Error : The attribute USE_PATTERN_DETECT on DSP48E instance %m must be set to PATDET in order to use AUTORESET_PATTERN_DETECT equals TRUE. Failure to do so could make timing reports inaccurate. "); + end + + end + +//********************************************************* +//*** Input register A with 2 level deep of registers +//********************************************************* + + always @(ACIN or A) begin + case (A_INPUT) + "DIRECT" : a_o_mux <= A; + "CASCADE" : a_o_mux <= ACIN; + default : begin + $display("Attribute Syntax Error : The attribute A_INPUT on DSP48E instance %m is set to %s. Legal values for this attribute are DIRECT or CASCADE.", A_INPUT); + $finish; + end + endcase + end + + always @(posedge CLK) begin + if (RSTA) begin + qa_o_reg1 <= 30'b0; + qa_o_reg2 <= 30'b0; + end + else begin + case (AREG) + 1 : if (CEA2) + qa_o_reg2 <= a_o_mux; + + 2 : begin + if (CEA1) + qa_o_reg1 <= a_o_mux; + if (CEA2) + qa_o_reg2 <= qa_o_reg1; + end + default : ; + endcase + end + end + + always @(a_o_mux or qa_o_reg1 or qa_o_reg2) begin + case (AREG) + 0 : qa_o_mux <= a_o_mux; + 1,2 : qa_o_mux <= qa_o_reg2; + default : begin + $display("Attribute Syntax Error : The attribute AREG on DSP48E instance %m is set to %d. Legal values for this attribute are 0, 1 or 2.", AREG); + $finish; + end + endcase + end + + always @(qa_o_mux or qa_o_reg1 or qa_o_reg2) begin + case (ACASCREG) + 1 : if(AREG == 2) + qacout_o_mux <= qa_o_reg1; + else + qacout_o_mux <= qa_o_mux; + default : qacout_o_mux <= qa_o_mux; + endcase + end + +//********************************************************* +//*** Input register B with 2 level deep of registers +//********************************************************* + + always @(BCIN or B) begin + case (B_INPUT) + "DIRECT" : b_o_mux <= B; + "CASCADE" : b_o_mux <= BCIN; + default : begin + $display("Attribute Syntax Error : The attribute B_INPUT on DSP48E instance %m is set to %s. Legal values for this attribute are DIRECT or CASCADE.", B_INPUT); + $finish; + end + endcase + end + + always @(posedge CLK) begin + if (RSTB) begin + qb_o_reg1 <= 18'b0; + qb_o_reg2 <= 18'b0; + end + else begin + case (BREG) + 1 : if (CEB2) + qb_o_reg2 <= b_o_mux; + + 2 : begin + if (CEB1) + qb_o_reg1 <= b_o_mux; + if (CEB2) + qb_o_reg2 <= qb_o_reg1; + end + default : ; + endcase + end + end + + always @(b_o_mux or qb_o_reg1 or qb_o_reg2) begin + case (BREG) + 0 : qb_o_mux <= b_o_mux; + 1,2 : qb_o_mux <= qb_o_reg2; + default : begin + $display("Attribute Syntax Error : The attribute BREG on DSP48E instance %m is set to %d. Legal values for this attribute are 0, 1 or 2.", BREG); + $finish; + end + endcase + end + + always @(qb_o_mux or qb_o_reg1 or qb_o_reg2) begin + case (BCASCREG) + 1 : if(BREG == 2) + qbcout_o_mux <= qb_o_reg1; + else + qbcout_o_mux <= qb_o_mux; + default : qbcout_o_mux <= qb_o_mux; + endcase + end + +//********************************************************* +//*** Input register C with 1 level deep of register +//********************************************************* + + always @(posedge CLK) begin + if (RSTC) + qc_o_reg1 <= 48'b0; + else if (CEC) + qc_o_reg1 <= C; + end + + always @(C or qc_o_reg1) begin + case (CREG) + 0 : qc_o_mux <= C; + 1 : qc_o_mux <= qc_o_reg1; + default : begin + $display("Attribute Syntax Error : The attribute CREG on DSP48E instance %m is set to %d. Legal values for this attribute are 0 or 1.", CREG); + $finish; + end + endcase + end + +//********************************************************* +//*************** 25x18 Multiplier *************** +//********************************************************* +// 05/26/05 -- FP -- Added warning for invalid mult when USE_MULT=NONE +// SIMD=FOUR12 and SIMD=TWO24 +// Made mult_o to be "X" + + always @(qopmode_o_mux) begin + if(qopmode_o_mux[3:0] == 4'b0101) + if((USE_MULT == "NONE") || (USE_SIMD == "TWO24") || (USE_SIMD == "FOUR12")) + $display("OPMODE Input Warning : The OPMODE[3:0] %b to DSP48E instance %m is invalid when using attributes USE_MULT = NONE, or USE_SIMD = TWO24 or FOUR12 at %.3f ns.", qopmode_o_mux[3:0], $time/1000.0); + end + + assign mult_o = ((USE_MULT == "NONE") || (USE_SIMD == "TWO24") || (USE_SIMD == "FOUR12"))? 43'b0 : {{18{qa_o_mux[24]}}, qa_o_mux[24:0]} * {{25{qb_o_mux[17]}}, qb_o_mux}; + + always @(posedge CLK) begin + if (RSTM) begin + qmult_o_reg <= 18'b0; + end + else if (CEM) begin + qmult_o_reg <= mult_o; + end + end + + always @(mult_o or qmult_o_reg) begin + case (MREG) + 0 : qmult_o_mux <= mult_o; + 1 : qmult_o_mux <= qmult_o_reg; + default : begin + $display("Attribute Syntax Error : The attribute MREG on DSP48E instance %m is set to %d. Legal values for this attribute are 0 or 1.", MREG); + $finish; + end + endcase + end + + +//*** X mux + + always @(qp_o_mux or qa_o_mux or qb_o_mux or qmult_o_mux or qopmode_o_mux or qcarryinsel_o_mux) begin + case (qopmode_o_mux[1:0]) + 2'b00 : qx_o_mux <= 48'b0; + 2'b01 : qx_o_mux <= {{5{qmult_o_mux[MSB_A_MULT + MSB_B_MULT + 1]}}, qmult_o_mux}; + 2'b10 : qx_o_mux <= qp_o_mux; +// 438456 & 448147 & 451453 + 2'b11 : begin + qx_o_mux <= ((USE_MULT == "MULT_S") && (AREG == 0 || BREG == 0 ))? 48'bx : {qa_o_mux[MSB_A:0], qb_o_mux[MSB_B:0]}; + if((USE_MULT == "MULT_S") && (AREG == 0 || BREG == 0 )) + $display("DRC warning: When attribute USE_MULT on DSP48E instance %m is set to MULT_S, the A:B opmode selection is not permitted when AREG or BREG=0. If the multiplier is not used, set USE_MULT = NONE. For dynamic switching between multiply and add operation, set AREG and BREG=1 or MREG=0 and USE_MULT=MULT."); + end + + default : begin + end + endcase + end + + +//*** Y mux + + always @(qc_o_mux or qopmode_o_mux or qcarryinsel_o_mux or MULTSIGNIN) begin + case (qopmode_o_mux[3:2]) + 2'b00 : qy_o_mux <= 48'b0; + 2'b01 : qy_o_mux <= 48'b0; + + 2'b10 : if((qopmode_o_mux[6:4]) == 3'b100) + qy_o_mux <= {48{MULTSIGNIN}}; + else + qy_o_mux <= 48'hFFFFFFFFFFFF; + + 2'b11 : qy_o_mux <= qc_o_mux; + default : begin + end + endcase + end + + +//*** Z mux + + always @(qp_o_mux or qc_o_mux or PCIN or qopmode_o_mux or qcarryinsel_o_mux) begin + case (qopmode_o_mux[6:4]) + 3'b000 : qz_o_mux <= 48'b0; + 3'b001 : qz_o_mux <= PCIN; + 3'b010 : qz_o_mux <= qp_o_mux; + 3'b011 : qz_o_mux <= qc_o_mux; + 3'b100 : qz_o_mux <= qp_o_mux; // Use for MACC extend -- multsignin + 3'b101 : qz_o_mux <= {{17{PCIN[47]}}, PCIN[47:17]}; + 3'b110 : qz_o_mux <= {{17{qp_o_mux[47]}}, qp_o_mux[47:17]}; + default : begin + end + endcase + end + + + +//*** CarryInSel and OpMode with 1 level of register + always @(posedge CLK) begin + if (RSTCTRL) begin + qcarryinsel_o_reg1 <= 3'b0; + qopmode_o_reg1 <= 7'b0; + end + else if (CECTRL) begin + qcarryinsel_o_reg1 <= CARRYINSEL; + qopmode_o_reg1 <= OPMODE; + end + end + + + always @(CARRYINSEL or qcarryinsel_o_reg1) begin + case (CARRYINSELREG) + 0 : qcarryinsel_o_mux <= CARRYINSEL; + 1 : qcarryinsel_o_mux <= qcarryinsel_o_reg1; + default : begin + $display("Attribute Syntax Error : The attribute CARRYINSELREG on DSP48E instance %m is set to %d. Legal values for this attribute are 0 or 1.", CARRYINSELREG); + $finish; + end + endcase + end + +//CR 219047 (3) + +// always @(qcarryinsel_o_mux or MULTSIGNIN or qopmode_o_mux) begin +// always @(CARRYCASCIN or MULTSIGNIN or qopmode_o_mux) begin + always @(qcarryinsel_o_mux or CARRYCASCIN or MULTSIGNIN or qopmode_o_mux) begin + if(qcarryinsel_o_mux == 3'b010) begin + if(!((MULTSIGNIN === 1'bx) || ((qopmode_o_mux == 7'b1001000) && !(MULTSIGNIN === 1'bx)) + || ((MULTSIGNIN == 1'b0) && (CARRYCASCIN == 1'b0)))) begin +// CR 451453 -- DRC warning timescale +// CR 451178 -- DRC warning Enhancement + $display("DRC warning : CARRYCASCIN can only be used in the current DSP48E instance %m if the previous DSP48E is performing a two input ADD operation, or the current DSP48E is configured in the MAC extend opmode 7'b1001000 at %.3f ns. This warning can be also triggered if OPMODEREG is set to 1 and CARRYINSELREG is set to 0 - in which case please set CARRYINSELREG to 1.", $time/1000.0); + end + end + end + +//CR 219047 (4) + always @(qcarryinsel_o_mux) begin + if((qcarryinsel_o_mux == 3'b110) && (MULTCARRYINREG != MREG)) begin + $display("Attribute Syntax Warning : It is recommended that MREG and MULTCARRYINREG on DSP48E instance %m be set to the same value when using CARRYINSEL = 110 for multiply rounding."); + end + end + + + always @(OPMODE or qopmode_o_reg1) begin + case (OPMODEREG) + 0 : qopmode_o_mux <= OPMODE; + 1 : qopmode_o_mux <= qopmode_o_reg1; + default : begin + $display("Attribute Syntax Error : The attribute OPMODEREG on DSP48E instance %m is set to %d. Legal values for this attribute are 0 or 1.", OPMODEREG); + $finish; + end + endcase + end + + + +//*** ALUMODE with 1 level of register + always @(posedge CLK) begin + if (RSTALUMODE) + qalumode_o_reg1 <= 4'b0; + else if (CEALUMODE) + qalumode_o_reg1 <= ALUMODE; + end + + + always @(ALUMODE or qalumode_o_reg1) begin + case (ALUMODEREG) + 0 : qalumode_o_mux <= ALUMODE; + 1 : qalumode_o_mux <= qalumode_o_reg1; + default : begin + $display("Attribute Syntax Error : The attribute ALUMODEREG on DSP48E instance %m is set to %d. Legal values for this attribute are 0 or 1.", ALUMODEREG); + $finish; + end + endcase + end + + +//------------------------------------------------------------------ +//*** DRC for OPMODE +//------------------------------------------------------------------ + task deassign_xyz_mux; + begin + opmode_valid_flag = 1; + invalid_opmode = 1; // reset invalid opmode + deassign qx_o_mux; + deassign qy_o_mux; + deassign qz_o_mux; + deassign alu_o; + end + endtask // deassign_xyz_mux + + task display_invalid_opmode_no_mreg; + begin + if (invalid_opmode) begin + + opmode_valid_flag = 0; + invalid_opmode = 0; + assign qx_o_mux = 48'bx; + assign qy_o_mux = 48'bx; + assign qz_o_mux = 48'bx; + assign alu_o = 48'bx; + $display("OPMODE Input Warning : The OPMODE %b with CARRYINSEL %b to DSP48E instance %m at %.3f ns requires attribute MREG set to 0.", qopmode_o_mux, qcarryinsel_o_mux, $time/1000.0); + end + end + endtask // display_invalid_opmode_no_mreg + + task display_invalid_opmode_mreg; + begin + if (invalid_opmode) begin + opmode_valid_flag = 0; + invalid_opmode = 0; + assign qx_o_mux = 48'bx; + assign qy_o_mux = 48'bx; + assign qz_o_mux = 48'bx; + assign alu_o = 48'bx; + $display("OPMODE Input Warning : The OPMODE %b with CARRYINSEL %b to DSP48E instance %m at %.3f ns requires attribute MREG set to 1.", qopmode_o_mux, qcarryinsel_o_mux, $time/1000.0); + end + end + endtask // display_invalid_opmode_mreg + + task display_invalid_opmode; + begin + if (invalid_opmode) begin + opmode_valid_flag = 0; + invalid_opmode = 0; + assign qx_o_mux = 48'bx; + assign qy_o_mux = 48'bx; + assign qz_o_mux = 48'bx; + assign alu_o = 48'bx; + $display("OPMODE Input Warning : The OPMODE %b to DSP48E instance %m at %.3f ns requires attribute PREG set to 1.", qopmode_o_mux, $time/1000.0); + end + end + endtask // display_invalid_opmode + + +//*** CarryIn Mux and Register + + always @(ping_opmode_drc_check or qalumode_o_mux or qopmode_o_mux or qcarryinsel_o_mux ) begin + + if ($time > 100000) begin // no check at first 100ns + case (qalumode_o_mux[3:2]) + 2'b00 : + //-- ARITHMETIC MODES DRC + case ({qopmode_o_mux, qcarryinsel_o_mux}) + 10'b0000000000 : deassign_xyz_mux; + 10'b0000010000 : if (PREG != 1) display_invalid_opmode; else deassign_xyz_mux; + 10'b0000010010 : if (PREG != 1) display_invalid_opmode; else deassign_xyz_mux; +// CR 455601 added the following two lines + 10'b0000010101 : if (PREG != 1) display_invalid_opmode; else deassign_xyz_mux; + 10'b0000010111 : if (PREG != 1) display_invalid_opmode; else deassign_xyz_mux; + + 10'b0000011000 : deassign_xyz_mux; + 10'b0000011010 : deassign_xyz_mux; + 10'b0000011100 : deassign_xyz_mux; + 10'b0000101000 : deassign_xyz_mux; + 10'b0001000000 : deassign_xyz_mux; + 10'b0001010000 : if (PREG != 1) display_invalid_opmode; else deassign_xyz_mux; + 10'b0001010010 : if (PREG != 1) display_invalid_opmode; else deassign_xyz_mux; + 10'b0001011000 : deassign_xyz_mux; + 10'b0001011010 : deassign_xyz_mux; + 10'b0001011100 : deassign_xyz_mux; + 10'b0001100000 : deassign_xyz_mux; + 10'b0001100010 : deassign_xyz_mux; + 10'b0001100100 : deassign_xyz_mux; + 10'b0001110000 : if (PREG != 1) display_invalid_opmode; else deassign_xyz_mux; + 10'b0001110010 : if (PREG != 1) display_invalid_opmode; else deassign_xyz_mux; + 10'b0001110101 : if (PREG != 1) display_invalid_opmode; else deassign_xyz_mux; + 10'b0001110111 : if (PREG != 1) display_invalid_opmode; else deassign_xyz_mux; + 10'b0001111000 : deassign_xyz_mux; + 10'b0001111010 : deassign_xyz_mux; + 10'b0001111100 : deassign_xyz_mux; + 10'b0010000000 : deassign_xyz_mux; + 10'b0010010000 : if (PREG != 1) display_invalid_opmode; else deassign_xyz_mux; + 10'b0010010101 : if (PREG != 1) display_invalid_opmode; else deassign_xyz_mux; + 10'b0010010111 : if (PREG != 1) display_invalid_opmode; else deassign_xyz_mux; + 10'b0010011000 : deassign_xyz_mux; + 10'b0010011001 : deassign_xyz_mux; + 10'b0010011011 : deassign_xyz_mux; + 10'b0010101000 : deassign_xyz_mux; + 10'b0010101001 : deassign_xyz_mux; + 10'b0010101011 : deassign_xyz_mux; + 10'b0010101110 : deassign_xyz_mux; + 10'b0011000000 : deassign_xyz_mux; + 10'b0011010000 : if (PREG != 1) display_invalid_opmode; else deassign_xyz_mux; + 10'b0011010101 : if (PREG != 1) display_invalid_opmode; else deassign_xyz_mux; + 10'b0011010111 : if (PREG != 1) display_invalid_opmode; else deassign_xyz_mux; + 10'b0011011000 : deassign_xyz_mux; + 10'b0011011001 : deassign_xyz_mux; + 10'b0011011011 : deassign_xyz_mux; + 10'b0011100000 : deassign_xyz_mux; + 10'b0011100001 : deassign_xyz_mux; + 10'b0011100011 : deassign_xyz_mux; + 10'b0011110000 : if (PREG != 1) display_invalid_opmode; else deassign_xyz_mux; + 10'b0011110101 : if (PREG != 1) display_invalid_opmode; else deassign_xyz_mux; + 10'b0011110111 : if (PREG != 1) display_invalid_opmode; else deassign_xyz_mux; + 10'b0011110001 : if (PREG != 1) display_invalid_opmode; else deassign_xyz_mux; + 10'b0011110011 : if (PREG != 1) display_invalid_opmode; else deassign_xyz_mux; + 10'b0011111000 : deassign_xyz_mux; + 10'b0011111001 : deassign_xyz_mux; + 10'b0011111011 : deassign_xyz_mux; + 10'b0100000000 : if (PREG != 1) display_invalid_opmode; else deassign_xyz_mux; + 10'b0100000010 : if (PREG != 1) display_invalid_opmode; else deassign_xyz_mux; + 10'b0100010000 : if (PREG != 1) display_invalid_opmode; else deassign_xyz_mux; + 10'b0100010010 : if (PREG != 1) display_invalid_opmode; else deassign_xyz_mux; + 10'b0100011000 : if (PREG != 1) display_invalid_opmode; else deassign_xyz_mux; + 10'b0100011010 : if (PREG != 1) display_invalid_opmode; else deassign_xyz_mux; + 10'b0100011101 : if (PREG != 1) display_invalid_opmode; else deassign_xyz_mux; + 10'b0100011111 : if (PREG != 1) display_invalid_opmode; else deassign_xyz_mux; + 10'b0100101000 : if (PREG != 1) display_invalid_opmode; else deassign_xyz_mux; + 10'b0100101101 : if (PREG != 1) display_invalid_opmode; else deassign_xyz_mux; + 10'b0100101111 : if (PREG != 1) display_invalid_opmode; else deassign_xyz_mux; + 10'b0101000000 : if (PREG != 1) display_invalid_opmode; else deassign_xyz_mux; + 10'b0101000010 : if (PREG != 1) display_invalid_opmode; else deassign_xyz_mux; + 10'b0101010000 : if (PREG != 1) display_invalid_opmode; else deassign_xyz_mux; + 10'b0101011000 : if (PREG != 1) display_invalid_opmode; else deassign_xyz_mux; + 10'b0101011101 : if (PREG != 1) display_invalid_opmode; else deassign_xyz_mux; + 10'b0101011111 : if (PREG != 1) display_invalid_opmode; else deassign_xyz_mux; + 10'b0101100000 : if (PREG != 1) display_invalid_opmode; else deassign_xyz_mux; + 10'b0101100010 : if (PREG != 1) display_invalid_opmode; else deassign_xyz_mux; + 10'b0101100101 : if (PREG != 1) display_invalid_opmode; else deassign_xyz_mux; + 10'b0101100111 : if (PREG != 1) display_invalid_opmode; else deassign_xyz_mux; + 10'b0101110000 : if (PREG != 1) display_invalid_opmode; else deassign_xyz_mux; + 10'b0101110101 : if (PREG != 1) display_invalid_opmode; else deassign_xyz_mux; + 10'b0101110111 : if (PREG != 1) display_invalid_opmode; else deassign_xyz_mux; + 10'b0101111000 : if (PREG != 1) display_invalid_opmode; else deassign_xyz_mux; + 10'b0101111101 : if (PREG != 1) display_invalid_opmode; else deassign_xyz_mux; + 10'b0101111111 : if (PREG != 1) display_invalid_opmode; else deassign_xyz_mux; + 10'b0110000000 : deassign_xyz_mux; + 10'b0110000010 : deassign_xyz_mux; + 10'b0110000100 : deassign_xyz_mux; + 10'b0110010000 : if (PREG != 1) display_invalid_opmode; else deassign_xyz_mux; + 10'b0110010010 : if (PREG != 1) display_invalid_opmode; else deassign_xyz_mux; + 10'b0110010101 : if (PREG != 1) display_invalid_opmode; else deassign_xyz_mux; + 10'b0110010111 : if (PREG != 1) display_invalid_opmode; else deassign_xyz_mux; + 10'b0110011000 : deassign_xyz_mux; + 10'b0110011010 : deassign_xyz_mux; + 10'b0110011100 : deassign_xyz_mux; + 10'b0110101000 : deassign_xyz_mux; + 10'b0110101110 : deassign_xyz_mux; + 10'b0111000000 : deassign_xyz_mux; + 10'b0111000010 : deassign_xyz_mux; + 10'b0111000100 : deassign_xyz_mux; + 10'b0111010000 : if (PREG != 1) display_invalid_opmode; else deassign_xyz_mux; + 10'b0111010101 : if (PREG != 1) display_invalid_opmode; else deassign_xyz_mux; + 10'b0111010111 : if (PREG != 1) display_invalid_opmode; else deassign_xyz_mux; + 10'b0111011000 : deassign_xyz_mux; + 10'b0111100000 : deassign_xyz_mux; + 10'b0111100010 : deassign_xyz_mux; + 10'b0111110000 : if (PREG != 1) display_invalid_opmode; else deassign_xyz_mux; + 10'b0111111000 : deassign_xyz_mux; + 10'b1001000010 : if (PREG != 1) display_invalid_opmode; else deassign_xyz_mux; + 10'b1010000000 : deassign_xyz_mux; + 10'b1010010000 : if (PREG != 1) display_invalid_opmode; else deassign_xyz_mux; + 10'b1010010101 : if (PREG != 1) display_invalid_opmode; else deassign_xyz_mux; + 10'b1010010111 : if (PREG != 1) display_invalid_opmode; else deassign_xyz_mux; + 10'b1010011000 : deassign_xyz_mux; + 10'b1010011001 : deassign_xyz_mux; + 10'b1010011011 : deassign_xyz_mux; + 10'b1010101000 : deassign_xyz_mux; + 10'b1010101001 : deassign_xyz_mux; + 10'b1010101011 : deassign_xyz_mux; + 10'b1010101110 : deassign_xyz_mux; + 10'b1011000000 : deassign_xyz_mux; + 10'b1011010000 : if (PREG != 1) display_invalid_opmode; else deassign_xyz_mux; + 10'b1011010101 : if (PREG != 1) display_invalid_opmode; else deassign_xyz_mux; + 10'b1011010111 : if (PREG != 1) display_invalid_opmode; else deassign_xyz_mux; + 10'b1011011000 : deassign_xyz_mux; + 10'b1011011001 : deassign_xyz_mux; + 10'b1011011011 : deassign_xyz_mux; + 10'b1011100000 : deassign_xyz_mux; + 10'b1011100001 : deassign_xyz_mux; + 10'b1011100011 : deassign_xyz_mux; + 10'b1011110000 : if (PREG != 1) display_invalid_opmode; else deassign_xyz_mux; + 10'b1011110101 : if (PREG != 1) display_invalid_opmode; else deassign_xyz_mux; + 10'b1011110111 : if (PREG != 1) display_invalid_opmode; else deassign_xyz_mux; + 10'b1011110001 : if (PREG != 1) display_invalid_opmode; else deassign_xyz_mux; + 10'b1011110011 : if (PREG != 1) display_invalid_opmode; else deassign_xyz_mux; + 10'b1011111000 : deassign_xyz_mux; + 10'b1011111001 : deassign_xyz_mux; + 10'b1011111011 : deassign_xyz_mux; + 10'b1100000000 : if (PREG != 1) display_invalid_opmode; else deassign_xyz_mux; + 10'b1100010000 : if (PREG != 1) display_invalid_opmode; else deassign_xyz_mux; + 10'b1100011000 : if (PREG != 1) display_invalid_opmode; else deassign_xyz_mux; + 10'b1100011101 : if (PREG != 1) display_invalid_opmode; else deassign_xyz_mux; + 10'b1100011111 : if (PREG != 1) display_invalid_opmode; else deassign_xyz_mux; + 10'b1100101000 : if (PREG != 1) display_invalid_opmode; else deassign_xyz_mux; + 10'b1100101101 : if (PREG != 1) display_invalid_opmode; else deassign_xyz_mux; + 10'b1100101111 : if (PREG != 1) display_invalid_opmode; else deassign_xyz_mux; + 10'b1101000000 : if (PREG != 1) display_invalid_opmode; else deassign_xyz_mux; + 10'b1101010000 : if (PREG != 1) display_invalid_opmode; else deassign_xyz_mux; + 10'b1101011000 : if (PREG != 1) display_invalid_opmode; else deassign_xyz_mux; + 10'b1101011101 : if (PREG != 1) display_invalid_opmode; else deassign_xyz_mux; + 10'b1101011111 : if (PREG != 1) display_invalid_opmode; else deassign_xyz_mux; + 10'b1101100000 : if (PREG != 1) display_invalid_opmode; else deassign_xyz_mux; + 10'b1101100101 : if (PREG != 1) display_invalid_opmode; else deassign_xyz_mux; + 10'b1101100111 : if (PREG != 1) display_invalid_opmode; else deassign_xyz_mux; + 10'b1101110000 : if (PREG != 1) display_invalid_opmode; else deassign_xyz_mux; + 10'b1101110101 : if (PREG != 1) display_invalid_opmode; else deassign_xyz_mux; + 10'b1101110111 : if (PREG != 1) display_invalid_opmode; else deassign_xyz_mux; + 10'b1101111000 : if (PREG != 1) display_invalid_opmode; else deassign_xyz_mux; + 10'b1101111101 : if (PREG != 1) display_invalid_opmode; else deassign_xyz_mux; + 10'b1101111111 : if (PREG != 1) display_invalid_opmode; else deassign_xyz_mux; + default : begin + if (invalid_opmode) begin + + opmode_valid_flag = 0; + invalid_opmode = 0; + assign qx_o_mux = 48'bx; + assign qy_o_mux = 48'bx; + assign qz_o_mux = 48'bx; + assign alu_o = 48'bx; +// CR 444150 + if( ({qopmode_o_mux, qcarryinsel_o_mux} == 10'b0000000010) && ((OPMODEREG==1) && (CARRYINSELREG ==0)) ) + $display("DRC warning : The attribute CARRYINSELREG on DSP48E instance %m is set to %d. It is required to have CARRYINSELREG be set to 1 to match OPMODEREG, in order to ensure that the simulation model will match the hardware behavior in all use cases.", CARRYINSELREG); + + + + $display("OPMODE Input Warning : The OPMODE %b to DSP48E instance %m is either invalid or the CARRYINSEL %b for that specific OPMODE is invalid at %.3f ns. This warning may be due to a mismatch in the OPMODEREG and CARRYINSELREG attribute settings. It is recommended that OPMODEREG and CARRYINSELREG always be set to the same value. ", qopmode_o_mux, qcarryinsel_o_mux, $time/1000.0); + + end + end + + endcase // case(OPMODE) + + 2'b01, 2'b11 : + //-- LOGIC MODES DRC + case (qopmode_o_mux) + 7'b0000000 : deassign_xyz_mux; + 7'b0000010 : if (PREG != 1) display_invalid_opmode; else deassign_xyz_mux; + 7'b0000011 : deassign_xyz_mux; + 7'b0010000 : deassign_xyz_mux; + 7'b0010010 : if (PREG != 1) display_invalid_opmode; else deassign_xyz_mux; + 7'b0010011 : deassign_xyz_mux; + 7'b0100000 : if (PREG != 1) display_invalid_opmode; else deassign_xyz_mux; + 7'b0100010 : if (PREG != 1) display_invalid_opmode; else deassign_xyz_mux; + 7'b0100011 : if (PREG != 1) display_invalid_opmode; else deassign_xyz_mux; + 7'b0110000 : deassign_xyz_mux; + 7'b0110010 : if (PREG != 1) display_invalid_opmode; else deassign_xyz_mux; + 7'b0110011 : deassign_xyz_mux; + 7'b1010000 : deassign_xyz_mux; + 7'b1010010 : if (PREG != 1) display_invalid_opmode; else deassign_xyz_mux; + 7'b1010011 : deassign_xyz_mux; + 7'b1100000 : if (PREG != 1) display_invalid_opmode; else deassign_xyz_mux; + 7'b1100010 : if (PREG != 1) display_invalid_opmode; else deassign_xyz_mux; + 7'b1100011 : if (PREG != 1) display_invalid_opmode; else deassign_xyz_mux; + 7'b0001000 : deassign_xyz_mux; + 7'b0001010 : if (PREG != 1) display_invalid_opmode; else deassign_xyz_mux; + 7'b0001011 : deassign_xyz_mux; + 7'b0011000 : deassign_xyz_mux; + 7'b0011010 : if (PREG != 1) display_invalid_opmode; else deassign_xyz_mux; + 7'b0011011 : deassign_xyz_mux; + 7'b0101000 : if (PREG != 1) display_invalid_opmode; else deassign_xyz_mux; + 7'b0101010 : if (PREG != 1) display_invalid_opmode; else deassign_xyz_mux; + 7'b0101011 : if (PREG != 1) display_invalid_opmode; else deassign_xyz_mux; + 7'b0111000 : deassign_xyz_mux; + 7'b0111010 : if (PREG != 1) display_invalid_opmode; else deassign_xyz_mux; + 7'b0111011 : deassign_xyz_mux; + 7'b1011000 : deassign_xyz_mux; + 7'b1011010 : if (PREG != 1) display_invalid_opmode; else deassign_xyz_mux; + 7'b1011011 : deassign_xyz_mux; + 7'b1101000 : if (PREG != 1) display_invalid_opmode; else deassign_xyz_mux; + 7'b1101010 : if (PREG != 1) display_invalid_opmode; else deassign_xyz_mux; + 7'b1101011 : if (PREG != 1) display_invalid_opmode; else deassign_xyz_mux; + default : begin + if (invalid_opmode) begin + + opmode_valid_flag = 0; + invalid_opmode = 0; + assign qx_o_mux = 48'bx; + assign qy_o_mux = 48'bx; + assign qz_o_mux = 48'bx; + assign alu_o = 48'bx; + $display("OPMODE Input Warning : The OPMODE %b to DSP48E instance %m is invalid for LOGIC MODES at %.3f ns.", qopmode_o_mux, $time/1000.0); + + end + end + + endcase // case(OPMODE) + + endcase // case(qalumode_o_mux) + + end // if ($time > 100000) + + end // always @ (qopmode_o_mux) + +//--#################################################################### +//--##### ALU ##### +//--#################################################################### + + always @(qx_o_mux or qy_o_mux or qz_o_mux or qalumode_o_mux, qopmode_o_mux or qcarryin_o_mux) begin + if (opmode_valid_flag) begin + + casex ({qopmode_o_mux[3:2], qalumode_o_mux}) + //--------- ADD -------------- + 6'bXX0000 : begin + + alumode_valid_flag = 1; + + case (USE_SIMD) + "ONE48", "one48" : begin + // verilog will zero_pad qx, qy and qz before addition + alu_full_tmp = qz_o_mux + (qx_o_mux + qy_o_mux + qcarryin_o_mux); + alu_o = alu_full_tmp[MSB_ALU_FULL:0]; + carrycascout_o = alu_full_tmp[MAX_ALU_FULL]; + // -- if multiply operation then "X"out the carryout + if((qopmode_o_mux[1:0] == 2'b01) || (qopmode_o_mux[3:2] == 2'b01)) + carryout_o = 4'bx; + else begin + carryout_o[3] = alu_full_tmp[MAX_ALU_FULL]; + carryout_o[2] = 1'bx; + carryout_o[1] = 1'bx; + carryout_o[0] = 1'bx; + end + end + "TWO24", "two24" : begin + alu_hlf1_tmp = qz_o_mux[((1*MAX_ALU_HALF)-1):0] + (qx_o_mux[((1*MAX_ALU_HALF)-1):0] + + qy_o_mux[((1*MAX_ALU_HALF)-1):0] + qcarryin_o_mux); + + alu_hlf2_tmp = qz_o_mux[((2*MAX_ALU_HALF)-1):(1*MAX_ALU_HALF)] + + (qx_o_mux[((2*MAX_ALU_HALF)-1):(1*MAX_ALU_HALF)] + + qy_o_mux[((2*MAX_ALU_HALF)-1):(1*MAX_ALU_HALF)] ); + + alu_o = { alu_hlf2_tmp[MSB_ALU_HALF:0], alu_hlf1_tmp[MSB_ALU_HALF:0]}; + + carrycascout_o = alu_hlf2_tmp[MAX_ALU_HALF]; + // -- if multiply operation then "X"out the carryout + if((qopmode_o_mux[1:0] == 2'b01) || (qopmode_o_mux[3:2] == 2'b01)) + carryout_o = 4'bx; + else begin + carryout_o[3] = alu_hlf2_tmp[MAX_ALU_HALF]; + carryout_o[2] = 1'bx; + carryout_o[1] = alu_hlf1_tmp[MAX_ALU_HALF]; + carryout_o[0] = 1'bx; + end + end + "FOUR12", "four12" : begin + alu_qrt1_tmp = qz_o_mux[((1*MAX_ALU_QUART)-1):0] + (qx_o_mux[((1*MAX_ALU_QUART)-1):0] + + qy_o_mux[((1*MAX_ALU_QUART)-1):0] + qcarryin_o_mux); + + alu_qrt2_tmp = qz_o_mux[((2*MAX_ALU_QUART)-1):(1*MAX_ALU_QUART)] + + (qx_o_mux[((2*MAX_ALU_QUART)-1):(1*MAX_ALU_QUART)] + + qy_o_mux[((2*MAX_ALU_QUART)-1):(1*MAX_ALU_QUART)] ); + + alu_qrt3_tmp = qz_o_mux[((3*MAX_ALU_QUART)-1):(2*MAX_ALU_QUART)] + + (qx_o_mux[((3*MAX_ALU_QUART)-1):(2*MAX_ALU_QUART)] + + qy_o_mux[((3*MAX_ALU_QUART)-1):(2*MAX_ALU_QUART)] ); + + alu_qrt4_tmp = qz_o_mux[((4*MAX_ALU_QUART)-1):(3*MAX_ALU_QUART)] + + (qx_o_mux[((4*MAX_ALU_QUART)-1):(3*MAX_ALU_QUART)] + + qy_o_mux[((4*MAX_ALU_QUART)-1):(3*MAX_ALU_QUART)] ); + + alu_o = { alu_qrt4_tmp[MSB_ALU_QUART:0], alu_qrt3_tmp[MSB_ALU_QUART:0], + alu_qrt2_tmp[MSB_ALU_QUART:0], alu_qrt1_tmp[MSB_ALU_QUART:0]}; + + carrycascout_o = alu_qrt4_tmp[MAX_ALU_QUART]; + // -- if multiply operation then "X"out the carryout + if((qopmode_o_mux[1:0] == 2'b01) || (qopmode_o_mux[3:2] == 2'b01)) + carryout_o = 4'bx; + else begin + carryout_o[3] = alu_qrt4_tmp[MAX_ALU_QUART]; + carryout_o[2] = alu_qrt3_tmp[MAX_ALU_QUART]; + carryout_o[1] = alu_qrt2_tmp[MAX_ALU_QUART]; + carryout_o[0] = alu_qrt1_tmp[MAX_ALU_QUART]; + end + + end + default : begin + $display("Attribute Syntax Error : The attribute USE_SIMD on DSP48E instance %m is set to %s. Legal values for this attribute are ONE48 or TWO24 or FOUR12.", USE_SIMD); + $finish; + end + endcase + end + //----------------- SUBTRACT (X + ~Z ) carryin must be 1 --------------- + 6'bXX0001 : begin + + alumode_valid_flag = 1; + + case (USE_SIMD) + "ONE48", "one48" : begin + // verilog will zero_pad qx, qy and qz before inversing/addition + alu_full_tmp = ~qz_o_mux + (qx_o_mux + qy_o_mux + qcarryin_o_mux); + alu_o = alu_full_tmp[MSB_ALU_FULL:0]; + carrycascout_o = ~alu_full_tmp[MAX_ALU_FULL]; + // -- if multiply operation then "X"out the carryout + if((qopmode_o_mux[1:0] == 2'b01) || (qopmode_o_mux[3:2] == 2'b01)) + carryout_o = 4'bx; + else begin + carryout_o[3] = ~alu_full_tmp[MAX_ALU_FULL]; + carryout_o[2] = 1'bx; + carryout_o[1] = 1'bx; + carryout_o[0] = 1'bx; + end + end + "TWO24", "two24" : begin + alu_hlf1_tmp = ~qz_o_mux[((1*MAX_ALU_HALF)-1):0] + (qx_o_mux[((1*MAX_ALU_HALF)-1):0] + + qy_o_mux[((1*MAX_ALU_HALF)-1):0] + qcarryin_o_mux); + + alu_hlf2_tmp = ~qz_o_mux[((2*MAX_ALU_HALF)-1):(1*MAX_ALU_HALF)] + + (qx_o_mux[((2*MAX_ALU_HALF)-1):(1*MAX_ALU_HALF)] + + qy_o_mux[((2*MAX_ALU_HALF)-1):(1*MAX_ALU_HALF)] ); + + alu_o = { alu_hlf2_tmp[MSB_ALU_HALF:0], alu_hlf1_tmp[MSB_ALU_HALF:0]}; + + carrycascout_o = ~alu_hlf2_tmp[MAX_ALU_HALF]; + // -- if multiply operation then "X"out the carryout + if((qopmode_o_mux[1:0] == 2'b01) || (qopmode_o_mux[3:2] == 2'b01)) + carryout_o = 4'bx; + else begin + carryout_o[3] = ~alu_hlf2_tmp[MAX_ALU_HALF]; + carryout_o[2] = 1'bx; + carryout_o[1] = ~alu_hlf1_tmp[MAX_ALU_HALF]; + carryout_o[0] = 1'bx; + end + end + "FOUR12", "four12" : begin + alu_qrt1_tmp = ~qz_o_mux[((1*MAX_ALU_QUART)-1):0] + (qx_o_mux[((1*MAX_ALU_QUART)-1):0] + + qy_o_mux[((1*MAX_ALU_QUART)-1):0] + qcarryin_o_mux); + + alu_qrt2_tmp = ~qz_o_mux[((2*MAX_ALU_QUART)-1):(1*MAX_ALU_QUART)] + + (qx_o_mux[((2*MAX_ALU_QUART)-1):(1*MAX_ALU_QUART)] + + qy_o_mux[((2*MAX_ALU_QUART)-1):(1*MAX_ALU_QUART)] ); + + alu_qrt3_tmp = ~qz_o_mux[((3*MAX_ALU_QUART)-1):(2*MAX_ALU_QUART)] + + (qx_o_mux[((3*MAX_ALU_QUART)-1):(2*MAX_ALU_QUART)] + + qy_o_mux[((3*MAX_ALU_QUART)-1):(2*MAX_ALU_QUART)] ); + + alu_qrt4_tmp = ~qz_o_mux[((4*MAX_ALU_QUART)-1):(3*MAX_ALU_QUART)] + + (qx_o_mux[((4*MAX_ALU_QUART)-1):(3*MAX_ALU_QUART)] + + qy_o_mux[((4*MAX_ALU_QUART)-1):(3*MAX_ALU_QUART)] ); + + alu_o = { alu_qrt4_tmp[MSB_ALU_QUART:0], alu_qrt3_tmp[MSB_ALU_QUART:0], + alu_qrt2_tmp[MSB_ALU_QUART:0], alu_qrt1_tmp[MSB_ALU_QUART:0]}; + + carrycascout_o = ~alu_qrt4_tmp[MAX_ALU_QUART]; + // -- if multiply operation then "X"out the carryout + if((qopmode_o_mux[1:0] == 2'b01) || (qopmode_o_mux[3:2] == 2'b01)) + carryout_o = 4'bx; + else begin + carryout_o[3] = ~alu_qrt4_tmp[MAX_ALU_QUART]; + carryout_o[2] = ~alu_qrt3_tmp[MAX_ALU_QUART]; + carryout_o[1] = ~alu_qrt2_tmp[MAX_ALU_QUART]; + carryout_o[0] = ~alu_qrt1_tmp[MAX_ALU_QUART]; + end + + end + default : begin + $display("Attribute Syntax Error : The attribute USE_SIMD on DSP48E instance %m is set to %s. Legal values for this attribute are ONE48 or TWO24 or FOUR12.", USE_SIMD); + $finish; + end + endcase + end + + //----------------- NOT (X + Z) ---------------------------------------- + 6'bXX0010 : begin + + alumode_valid_flag = 1; + + case (USE_SIMD) + "ONE48", "one48" : begin + alu_full_tmp = ~(qz_o_mux + (qx_o_mux + qy_o_mux + qcarryin_o_mux)); + alu_o = alu_full_tmp[MSB_ALU_FULL:0]; + carrycascout_o = ~alu_full_tmp[MAX_ALU_FULL]; + // -- if multiply operation then "X"out the carryout + if((qopmode_o_mux[1:0] == 2'b01) || (qopmode_o_mux[3:2] == 2'b01)) + carryout_o = 4'bx; + else begin + carryout_o[3] = ~alu_full_tmp[MAX_ALU_FULL]; + carryout_o[2] = 1'bx; + carryout_o[1] = 1'bx; + carryout_o[0] = 1'bx; + end + end + "TWO24", "two24" : begin + alu_hlf1_tmp = ~(qz_o_mux[((1*MAX_ALU_HALF)-1):0] + (qx_o_mux[((1*MAX_ALU_HALF)-1):0] + + qy_o_mux[((1*MAX_ALU_HALF)-1):0] + qcarryin_o_mux)); + + alu_hlf2_tmp = ~(qz_o_mux[((2*MAX_ALU_HALF)-1):(1*MAX_ALU_HALF)] + + (qx_o_mux[((2*MAX_ALU_HALF)-1):(1*MAX_ALU_HALF)] + + qy_o_mux[((2*MAX_ALU_HALF)-1):(1*MAX_ALU_HALF)] )); + + alu_o = { alu_hlf2_tmp[MSB_ALU_HALF:0], alu_hlf1_tmp[MSB_ALU_HALF:0]}; + + carrycascout_o = ~alu_hlf2_tmp[MAX_ALU_HALF]; + // -- if multiply operation then "X"out the carryout + if((qopmode_o_mux[1:0] == 2'b01) || (qopmode_o_mux[3:2] == 2'b01)) + carryout_o = 4'bx; + else begin + carryout_o[3] = ~alu_hlf2_tmp[MAX_ALU_HALF]; + carryout_o[2] = 1'bx; + carryout_o[1] = ~alu_hlf1_tmp[MAX_ALU_HALF]; + carryout_o[0] = 1'bx; + end + end + "FOUR12", "four12" : begin + alu_qrt1_tmp = ~(qz_o_mux[((1*MAX_ALU_QUART)-1):0] + (qx_o_mux[((1*MAX_ALU_QUART)-1):0] + + qy_o_mux[((1*MAX_ALU_QUART)-1):0] + qcarryin_o_mux)); + + alu_qrt2_tmp = ~(qz_o_mux[((2*MAX_ALU_QUART)-1):(1*MAX_ALU_QUART)] + + (qx_o_mux[((2*MAX_ALU_QUART)-1):(1*MAX_ALU_QUART)] + + qy_o_mux[((2*MAX_ALU_QUART)-1):(1*MAX_ALU_QUART)] )); + + alu_qrt3_tmp = ~(qz_o_mux[((3*MAX_ALU_QUART)-1):(2*MAX_ALU_QUART)] + + (qx_o_mux[((3*MAX_ALU_QUART)-1):(2*MAX_ALU_QUART)] + + qy_o_mux[((3*MAX_ALU_QUART)-1):(2*MAX_ALU_QUART)] )); + + alu_qrt4_tmp = ~(qz_o_mux[((4*MAX_ALU_QUART)-1):(3*MAX_ALU_QUART)] + + (qx_o_mux[((4*MAX_ALU_QUART)-1):(3*MAX_ALU_QUART)] + + qy_o_mux[((4*MAX_ALU_QUART)-1):(3*MAX_ALU_QUART)] )); + + alu_o = { alu_qrt4_tmp[MSB_ALU_QUART:0], alu_qrt3_tmp[MSB_ALU_QUART:0], + alu_qrt2_tmp[MSB_ALU_QUART:0], alu_qrt1_tmp[MSB_ALU_QUART:0]}; + + carrycascout_o = ~alu_qrt4_tmp[MAX_ALU_QUART]; + // -- if multiply operation then "X"out the carryout + if((qopmode_o_mux[1:0] == 2'b01) || (qopmode_o_mux[3:2] == 2'b01)) + carryout_o = 4'bx; + else begin + carryout_o[3] = ~alu_qrt4_tmp[MAX_ALU_QUART]; + carryout_o[2] = ~alu_qrt3_tmp[MAX_ALU_QUART]; + carryout_o[1] = ~alu_qrt2_tmp[MAX_ALU_QUART]; + carryout_o[0] = ~alu_qrt1_tmp[MAX_ALU_QUART]; + end + + end + default : begin + $display("Attribute Syntax Error : The attribute USE_SIMD on DSP48E instance %m is set to %s. Legal values for this attribute are ONE48 or TWO24 or FOUR12.", USE_SIMD); + $finish; + end + endcase + end + //----------------- SUBTRACT (Z - X) ---------------------------------- + 6'bXX0011 : begin + + alumode_valid_flag = 1; + + case (USE_SIMD) + "ONE48", "one48" : begin + alu_full_tmp = qz_o_mux - (qx_o_mux + qy_o_mux + qcarryin_o_mux); + alu_o = alu_full_tmp[MSB_ALU_FULL:0]; + carrycascout_o = alu_full_tmp[MAX_ALU_FULL]; + // -- if multiply operation then "X"out the carryout + if((qopmode_o_mux[1:0] == 2'b01) || (qopmode_o_mux[3:2] == 2'b01)) + carryout_o = 4'bx; + else begin + carryout_o[3] = ~alu_full_tmp[MAX_ALU_FULL]; + carryout_o[2] = 1'bx; + carryout_o[1] = 1'bx; + carryout_o[0] = 1'bx; + end + end + "TWO24", "two24" : begin + alu_hlf1_tmp = qz_o_mux[((1*MAX_ALU_HALF)-1):0] - (qx_o_mux[((1*MAX_ALU_HALF)-1):0] + + qy_o_mux[((1*MAX_ALU_HALF)-1):0] + qcarryin_o_mux); + + alu_hlf2_tmp = qz_o_mux[((2*MAX_ALU_HALF)-1):(1*MAX_ALU_HALF)] - + (qx_o_mux[((2*MAX_ALU_HALF)-1):(1*MAX_ALU_HALF)] + + qy_o_mux[((2*MAX_ALU_HALF)-1):(1*MAX_ALU_HALF)] ); + + alu_o = { alu_hlf2_tmp[MSB_ALU_HALF:0], alu_hlf1_tmp[MSB_ALU_HALF:0]}; + + carrycascout_o = alu_hlf2_tmp[MAX_ALU_HALF]; + // -- if multiply operation then "X"out the carryout + if((qopmode_o_mux[1:0] == 2'b01) || (qopmode_o_mux[3:2] == 2'b01)) + carryout_o = 4'bx; + else begin + carryout_o[3] = ~alu_hlf2_tmp[MAX_ALU_HALF]; + carryout_o[2] = 1'bx; + carryout_o[1] = ~alu_hlf1_tmp[MAX_ALU_HALF]; + carryout_o[0] = 1'bx; + end + end + "FOUR12", "four12" : begin + alu_qrt1_tmp = qz_o_mux[((1*MAX_ALU_QUART)-1):0] - (qx_o_mux[((1*MAX_ALU_QUART)-1):0] + + qy_o_mux[((1*MAX_ALU_QUART)-1):0] + qcarryin_o_mux); + + alu_qrt2_tmp = qz_o_mux[((2*MAX_ALU_QUART)-1):(1*MAX_ALU_QUART)] - + (qx_o_mux[((2*MAX_ALU_QUART)-1):(1*MAX_ALU_QUART)] + + qy_o_mux[((2*MAX_ALU_QUART)-1):(1*MAX_ALU_QUART)] ); + + alu_qrt3_tmp = qz_o_mux[((3*MAX_ALU_QUART)-1):(2*MAX_ALU_QUART)] - + (qx_o_mux[((3*MAX_ALU_QUART)-1):(2*MAX_ALU_QUART)] + + qy_o_mux[((3*MAX_ALU_QUART)-1):(2*MAX_ALU_QUART)] ); + + alu_qrt4_tmp = qz_o_mux[((4*MAX_ALU_QUART)-1):(3*MAX_ALU_QUART)] - + (qx_o_mux[((4*MAX_ALU_QUART)-1):(3*MAX_ALU_QUART)] + + qy_o_mux[((4*MAX_ALU_QUART)-1):(3*MAX_ALU_QUART)] ); + + alu_o = { alu_qrt4_tmp[MSB_ALU_QUART:0], alu_qrt3_tmp[MSB_ALU_QUART:0], + alu_qrt2_tmp[MSB_ALU_QUART:0], alu_qrt1_tmp[MSB_ALU_QUART:0]}; + + carrycascout_o = alu_qrt4_tmp[MAX_ALU_QUART]; + // -- if multiply operation then "X"out the carryout + if((qopmode_o_mux[1:0] == 2'b01) || (qopmode_o_mux[3:2] == 2'b01)) + carryout_o = 4'bx; + else begin + carryout_o[3] = ~alu_qrt4_tmp[MAX_ALU_QUART]; + carryout_o[2] = ~alu_qrt3_tmp[MAX_ALU_QUART]; + carryout_o[1] = ~alu_qrt2_tmp[MAX_ALU_QUART]; + carryout_o[0] = ~alu_qrt1_tmp[MAX_ALU_QUART]; + end + + end + default : begin + $display("Attribute Syntax Error : The attribute USE_SIMD on DSP48E instance %m is set to %s. Legal values for this attribute are ONE48 or TWO24 or FOUR12.", USE_SIMD); + $finish; + end + endcase + end +//---------------------------------------------------------- + //--------------- XOR ------------------ + 6'b000100, 6'b000111, 6'b100101, 6'b100110 : begin + alu_o = qx_o_mux ^ qz_o_mux; + carryout_o = 4'bx; + carrycascout_o = 1'bx; + alumode_valid_flag = 1; + end + + //--------------- XNOR ------------------ + 6'b000101, 6'b000110, 6'b100100, 6'b100111 : begin + alu_o = qx_o_mux ~^ qz_o_mux; + carryout_o = 4'bx; + carrycascout_o = 1'bx; + alumode_valid_flag = 1; + end +//---------------------------------------------------------- + + //--------------- AND ------------------ + 6'b001100 : begin + alu_o = qx_o_mux & qz_o_mux; + carryout_o = 4'bx; + carrycascout_o = 1'bx; + alumode_valid_flag = 1; + end + + //--------------- X AND (NOT Z) ------------------ + 6'b001101 : begin + alu_o = qx_o_mux & (~qz_o_mux); + carryout_o = 4'bx; + carrycascout_o = 1'bx; + alumode_valid_flag = 1; + end + + //--------------- X NAND Z ------------------ + 6'b001110 : begin + alu_o = ~(qx_o_mux & qz_o_mux); + carryout_o = 4'bx; + carrycascout_o = 1'bx; + alumode_valid_flag = 1; + end + + //--------------- (NOT X) OR Z ------------------ + 6'b001111 : begin + alu_o = (~qx_o_mux) | (qz_o_mux); + carryout_o = 4'bx; + carrycascout_o = 1'bx; + alumode_valid_flag = 1; + end +//---------------------------------------------------------- + + //--------------- X OR Z ------------------ + 6'b101100 : begin + alu_o = qx_o_mux | qz_o_mux; + carryout_o = 4'bx; + carrycascout_o = 1'bx; + alumode_valid_flag = 1; + end + + //--------------- X OR ~Z ------------------ + 6'b101101 : begin + alu_o = (qx_o_mux) | (~qz_o_mux); + carryout_o = 4'bx; + carrycascout_o = 1'bx; + alumode_valid_flag = 1; + end + + //--------------- X NOR Z ------------------ + 6'b101110 : begin + alu_o = ~((qx_o_mux) | (qz_o_mux)); + carryout_o = 4'bx; + carrycascout_o = 1'bx; + alumode_valid_flag = 1; + end + + //--------------- (NOT X) and Z ------------------ + 6'b101111 : begin + alu_o = (~qx_o_mux) & (qz_o_mux); + carryout_o = 4'bx; + carrycascout_o = 1'bx; + alumode_valid_flag = 1; + end + +//---------------------------------------------------------- +//---------------------------------------------------------- + + default : begin + alu_o = 48'bx; + carryout_o = 4'bx; + carrycascout_o = 1'bx; + + alumode_valid_flag = 0; + + $display("ALUMODE Input Warning : The ALUMODE %b to DSP48E instance %m is either invalid or the OPMODE %b for that specific ALUMODE is invalid at %.3f ns.", qalumode_o_mux, qopmode_o_mux, $time/1000.0); + end + endcase + + end + + end // always @ (qalumode_o_mux) + + +//------- input 0 + always @(posedge CLK) begin + if (RSTALLCARRYIN) + qcarryin_o_reg0 <= 1'b0; + else if (CECARRYIN) + qcarryin_o_reg0 <= CARRYIN; + end + + always @(CARRYIN or qcarryin_o_reg0) begin + case (CARRYINREG) + 0 : qcarryin_o_mux0 <= CARRYIN; + 1 : qcarryin_o_mux0 <= qcarryin_o_reg0; + default : begin + $display("Attribute Syntax Error : The attribute CARRYINREG on DSP48E instance %m is set to %d. Legal values for this attribute are 0 or 1.", CARRYINREG); + $finish; + end + endcase + end + +//------- input 7 + always @(posedge CLK) begin + if (RSTALLCARRYIN) + qcarryin_o_reg7 <= 1'b0; + else if (CEMULTCARRYIN) + qcarryin_o_reg7 <= qa_o_mux[24] ~^ qb_o_mux[17]; // xnor + end + + always @(qa_o_mux[24] or qb_o_mux[17] or qcarryin_o_reg7) begin + case (MULTCARRYINREG) + 0 : qcarryin_o_mux7 <= qa_o_mux[24] ~^ qb_o_mux[17]; + 1 : qcarryin_o_mux7 <= qcarryin_o_reg7; + default : begin + $display("Attribute Syntax Error : The attribute MULTCARRYINREG on DSP48E instance %m is set to %d. Legal values for this attribute are 0 or 1.", MULTCARRYINREG); + $finish; + end + endcase + end + + + always @(qcarryin_o_mux0 or PCIN[47] or CARRYCASCIN or carrycascout_o_mux or qp_o_mux[47], qcarryin_o_mux7, qcarryinsel_o_mux) begin + case (qcarryinsel_o_mux) + 3'b000 : qcarryin_o_mux <= qcarryin_o_mux0; + 3'b001 : qcarryin_o_mux <= ~PCIN[47]; + 3'b010 : qcarryin_o_mux <= CARRYCASCIN; + 3'b011 : qcarryin_o_mux <= PCIN[47]; + 3'b100 : qcarryin_o_mux <= carrycascout_o_mux; + 3'b101 : qcarryin_o_mux <= ~qp_o_mux[47]; + 3'b110 : qcarryin_o_mux <= qcarryin_o_mux7; + 3'b111 : qcarryin_o_mux <= qp_o_mux[47]; + default : begin + end + endcase + end +//--#################################################################### +//--##### CARRYOUT and CARRYCASCOUT ##### +//--#################################################################### +//*** register with 1 level of register + always @(posedge CLK) begin + if ((RSTP) || + ((AUTORESET_PATTERN_DETECT == "TRUE") && ( + ((AUTORESET_PATTERN_DETECT_OPTINV == "MATCH") && pdet_o_reg1) || + ((AUTORESET_PATTERN_DETECT_OPTINV == "NOT_MATCH") && (pdet_o_reg2 && !pdet_o_reg1))) + ) + ) begin + carrycascout_o_reg <= 1'b0; + carryout_o_reg <= 4'b0; + end + else if (CEP) begin + carrycascout_o_reg <= carrycascout_o; + carryout_o_reg <= carryout_o; + end + end + + always @(carryout_o or carryout_o_reg) begin + case (PREG) + 0 : carryout_o_mux <= carryout_o; + 1 : carryout_o_mux <= carryout_o_reg; + default : begin +// $display("Attribute Syntax Error : The attribute PREG on DSP48E instance %m is set to %d. Legal values for this attribute are 0 or 1.", PREG); +// $finish; + end + endcase + end + + always @(carrycascout_o or carrycascout_o_reg) begin + case (PREG) + 0 : carrycascout_o_mux <= carrycascout_o; + 1 : carrycascout_o_mux <= carrycascout_o_reg; + default : begin +// $display("Attribute Syntax Error : The attribute PREG on DSP48E instance %m is set to %d. Legal values for this attribute are 0 or 1.", PREG); +// $finish; + end + endcase + end + +//CR 219047 (2) + + always @(qmult_o_mux[(MSB_A_MULT+MSB_B_MULT+1)] or qopmode_o_mux[3:0]) begin + if(qopmode_o_mux[3:0] == 4'b0101) + multsignout_o_opmode = qmult_o_mux[(MSB_A_MULT+MSB_B_MULT+1)]; + else + multsignout_o_opmode = 1'bx; + end + + + always @(multsignout_o_opmode or qmultsignout_o_reg) begin + case (PREG) + 0 : multsignout_o_mux <= multsignout_o_opmode; + 1 : multsignout_o_mux <= qmultsignout_o_reg; + + default : begin +// $display("Attribute Syntax Error : The attribute PREG on DSP48E instance %m is set to %d. Legal values for this attribute are 0 or 1.", PREG); +// $finish; + end + endcase + end + + assign carryout_x_o[3] = carryout_o_mux[3]; + assign carryout_x_o[2] = (USE_SIMD == "FOUR12") ? carryout_o_mux[2] : 1'bx; + assign carryout_x_o[1] = ((USE_SIMD == "TWO24") || (USE_SIMD == "FOUR12")) ? carryout_o_mux[1] : 1'bx; + assign carryout_x_o[0] = (USE_SIMD == "FOUR12") ? carryout_o_mux[0] : 1'bx; + +//--#################################################################### +//--##### PCOUT and MULTSIGNOUT ##### +//--#################################################################### +//*** Output register P with 1 level of register + always @(posedge CLK) begin + if ((RSTP) || + ((AUTORESET_PATTERN_DETECT == "TRUE") && ( + ((AUTORESET_PATTERN_DETECT_OPTINV == "MATCH") && pdet_o_reg1) || + ((AUTORESET_PATTERN_DETECT_OPTINV == "NOT_MATCH") && (pdet_o_reg2 && !pdet_o_reg1))) + ) + ) + begin + qp_o_reg1 <= 48'b0; + qmultsignout_o_reg <= 1'b0; + end + else if (CEP) begin + qp_o_reg1 <= alu_o; + qmultsignout_o_reg <= multsignout_o_opmode; + end + end + + always @(qp_o_reg1 or alu_o) begin + case (PREG) + 0 : qp_o_mux <= alu_o; + 1 : qp_o_mux <= qp_o_reg1; + default : begin + $display("Attribute Syntax Error : The attribute PREG on DSP48E instance %m is set to %d. Legal values for this attribute are 0 or 1.", PREG); + $finish; + end + endcase + end + +//--#################################################################### +//--##### Pattern Detector ##### +//--#################################################################### + assign pdet_o_mux = ((USE_PATTERN_DETECT == "NO_PATDET") | ~opmode_valid_flag | ~alumode_valid_flag) ? 1'bx : (PREG == 1) ? pdet_o_reg1 : pdet_o; + assign pdetb_o_mux = ((USE_PATTERN_DETECT == "NO_PATDET") | ~opmode_valid_flag | ~alumode_valid_flag) ? 1'bx : (PREG == 1) ? pdetb_o_reg1 : pdetb_o; + + always @(alu_o, qc_o_mux, negedge GSR) begin + + //-- Select the pattern + case(SEL_PATTERN) + "PATTERN" : pattern_qp <= PATTERN; + "C" : pattern_qp <= qc_o_mux; + default : begin + $display("Attribute Syntax Error : The attribute SEL_PATTERN on DSP48E instance %m is set to %s. Legal values for this attribute are PATTERN or C.", SEL_PATTERN); + $finish; + end + endcase + + //-- Select the mask -- if ROUNDING MASK set, use rounding mode, else use SEL_MASK + case(SEL_ROUNDING_MASK) + "SEL_MASK" : + case(SEL_MASK) + "MASK" : mask_qp <= MASK; + "C" : mask_qp <= qc_o_mux; + default : begin + $display("Attribute Syntax Error : The attribute SEL_MASK on DSP48E instance %m is set to %s. Legal values for this attribute are MASK or C.", SEL_MASK); + $finish; + end + endcase + "MODE1" : mask_qp <= ~qc_o_mux << 1; + "MODE2" : mask_qp <= ~qc_o_mux << 2; + default : begin + $display("Attribute Syntax Error : The attribute SEL_ROUNDING_MASK on DSP48E instance %m is set to %s. Legal values for this attribute are SEL_MASK or MODE1 or MODE2.", SEL_ROUNDING_MASK); + $finish; + end + endcase + + end + + //-- now do the pattern detection + + always @(alu_o, mask_qp, pattern_qp, GSR) begin + if((alu_o | mask_qp) == (pattern_qp | mask_qp)) + pdet_o <= 1'b1; + else + pdet_o <= 1'b0; + + if((alu_o | mask_qp) == (~pattern_qp | mask_qp)) + pdetb_o <= 1'b1; + else + pdetb_o <= 1'b0; + end + +//*** Output register PATTERN DETECT and UNDERFLOW / OVERFLOW + always @(posedge CLK) begin + if((RSTP) || + ((AUTORESET_PATTERN_DETECT == "TRUE") && ( + ((AUTORESET_PATTERN_DETECT_OPTINV == "MATCH") && pdet_o_reg1) || + ((AUTORESET_PATTERN_DETECT_OPTINV == "NOT_MATCH") && (pdet_o_reg2 && !pdet_o_reg1))) + ) + ) + begin + pdet_o_reg1 <= 1'b0; + pdet_o_reg2 <= 1'b0; + pdetb_o_reg1 <= 1'b0; + pdetb_o_reg2 <= 1'b0; + end + else if(CEP) + begin + //-- the previous values are used in Underflow/Overflow + pdet_o_reg2 <= pdet_o_reg1; + pdet_o_reg1 <= pdet_o; + pdetb_o_reg2 <= pdetb_o_reg1; + pdetb_o_reg1 <= pdetb_o; + end + end + +//--#################################################################### +//--##### Underflow / Overflow ##### +//--#################################################################### + always @(pdet_o_reg1 or pdet_o_reg2 or pdetb_o_reg1 or pdetb_o_reg2) begin + case (USE_PATTERN_DETECT) + "NO_PATDET" : begin + overflow_o <= 1'bx; + underflow_o <= 1'bx; + end + default : begin + case (PREG) + + 0 : begin + overflow_o <= 1'bx; + underflow_o <= 1'bx; + end + default : begin + + overflow_o <= pdet_o_reg2 & !pdet_o_reg1 & !pdetb_o_reg1; + underflow_o <= pdetb_o_reg2 & !pdet_o_reg1 & !pdetb_o_reg1; + end + endcase + end + endcase + end + + end +endgenerate +generate if (SIM_MODE == "FAST") begin +//*** GLOBAL hidden GSR pin + always @(GSR) begin + if (GSR) begin + assign qcarryin_o_reg0 = 1'b0; + assign qcarryinsel_o_reg1 = 3'b0; + assign qopmode_o_reg1 = 7'b0; + assign qalumode_o_reg1 = 4'b0; + assign qa_o_reg1 = 30'b0; + assign qa_o_reg2 = 30'b0; + assign qb_o_reg1 = 18'b0; + assign qb_o_reg2 = 18'b0; + assign qc_o_reg1 = 48'b0; + assign qp_o_reg1 = 48'b0; + assign qmult_o_reg = 36'b0; + + assign underflow_o = 1'b0; + assign overflow_o = 1'b0; + assign pdet_o = 1'b0; + assign pdetb_o = 1'b0; + assign pdet_o_reg1 = 1'b0; + assign pdet_o_reg2 = 1'b0; + assign pdetb_o_reg1 = 1'b0; + assign pdetb_o_reg2 = 1'b0; + + assign carryout_o_reg = 4'b0; + assign carrycascout_o_reg = 1'b0; + + assign qmultsignout_o_reg = 1'b0; + end + else begin + deassign qcarryin_o_reg0; + deassign qcarryinsel_o_reg1; + deassign qopmode_o_reg1; + deassign qalumode_o_reg1; + deassign qa_o_reg1; + deassign qa_o_reg2; + deassign qb_o_reg1; + deassign qb_o_reg2; + deassign qc_o_reg1; + deassign qp_o_reg1; + deassign qmult_o_reg; + + deassign underflow_o; + deassign overflow_o; + deassign pdet_o; + deassign pdetb_o; + deassign pdet_o_reg1; + deassign pdet_o_reg2; + deassign pdetb_o_reg1; + deassign pdetb_o_reg2; + + deassign carryout_o_reg; + deassign carrycascout_o_reg; + + deassign qmultsignout_o_reg; + end + end + + + initial begin + opmode_valid_flag <= 1; + alumode_valid_flag <= 1; + invalid_opmode <= 1; + + //-------- AREG check + + case (AREG) + 0, 1, 2 : ; + default : begin + $display("Attribute Syntax Error : The attribute AREG on DSP48E instance %m is set to %d. Legal values for this attribute are 0, 1 or 2.", AREG); + $finish; + end + endcase + + //-------- (ACASCREG) and (ACASCREG vs AREG) check + + case (AREG) + 0 : if(AREG != ACASCREG) begin + $display("Attribute Syntax Error : The attribute ACASCREG on DSP48E instance %m is set to %d. ACASCREG has to be set to 0 when attribute AREG = 0.", ACASCREG); + $finish; + end + 1 : if(AREG != ACASCREG) begin + $display("Attribute Syntax Error : The attribute ACASCREG on DSP48E instance %m is set to %d. ACASCREG has to be set to 1 when attribute AREG = 1.", ACASCREG); + $finish; + end + 2 : if((AREG != ACASCREG) && ((AREG-1) != ACASCREG)) begin + $display("Attribute Syntax Error : The attribute ACASCREG on DSP48E instance %m is set to %d. ACASCREG has to be set to either 2 or 1 when attribute AREG = 2.", ACASCREG); + $finish; + end + default : ; + endcase + + //-------- BREG check + + case (BREG) + 0, 1, 2 : ; + default : begin + $display("Attribute Syntax Error : The attribute BREG on DSP48E instance %m is set to %d. Legal values for this attribute are 0, 1 or 2.", BREG); + $finish; + end + endcase + + //-------- (BCASCREG) and (BCASCREG vs BREG) check + + case (BREG) + 0 : if(BREG != BCASCREG) begin + $display("Attribute Syntax Error : The attribute BCASCREG on DSP48E instance %m is set to %d. BCASCREG has to be set to 0 when attribute BREG = 0.", BCASCREG); + $finish; + end + 1 : if(BREG != BCASCREG) begin + $display("Attribute Syntax Error : The attribute BCASCREG on DSP48E instance %m is set to %d. BCASCREG has to be set to 1 when attribute BREG = 1.", BCASCREG); + $finish; + end + 2 : if((BREG != BCASCREG) && ((BREG-1) != BCASCREG)) begin + $display("Attribute Syntax Error : The attribute BCASCREG on DSP48E instance %m is set to %d. BCASCREG has to be set to either 2 or 1 when attribute BREG = 2.", BCASCREG); + $finish; + end + default : ; + endcase + + + //-------- AUTORESET_PATTERN_DETECT + + case (AUTORESET_PATTERN_DETECT) + "TRUE", "FALSE" : ; + default : begin + $display("Attribute Syntax Error : The attribute AUTORESET_PATTERN_DETECT on DSP48E instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", AUTORESET_PATTERN_DETECT); + $finish; + end + endcase + + //-------- AUTORESET_PATTERN_DETECT_OPTINV + + case (AUTORESET_PATTERN_DETECT_OPTINV) + "MATCH", "NOT_MATCH" : ; + default : begin + $display("Attribute Syntax Error : The attribute AUTORESET_PATTERN_DETECT_OPTINV on DSP48E instance %m is set to %s. Legal values for this attribute are MATCH or NOT_MATCH.", AUTORESET_PATTERN_DETECT_OPTINV); + $finish; + end + endcase + + //-------- USE_MULT + + case (USE_MULT) + "NONE" : ; + "MULT" : if (MREG != 0) begin + $display("Attribute Syntax Error : The attribute USE_MULT on DSP48E instance %m is set to %s. This requires attribute MREG to be set to 0.", USE_MULT); + $finish; + end + "MULT_S" : if (MREG != 1) begin + $display("Attribute Syntax Error : The attribute USE_MULT on DSP48E instance %m is set to %s. This requires attribute MREG to be set to 1.", USE_MULT); + $finish; + end + default : begin + $display("Attribute Syntax Error : The attribute USE_MULT on DSP48E instance %m is set to %s. Legal values for this attribute are NONE, MULT or MULT_S.", USE_MULT); + $finish; + end + endcase + + //-------- USE_PATTERN_DETECT + + case (USE_PATTERN_DETECT) + "PATDET", "NO_PATDET" : ; + default : begin + $display("Attribute Syntax Error : The attribute USE_PATTERN_DETECT on DSP48E instance %m is set to %s. Legal values for this attribute are PATDET or NO_PATDET.", USE_PATTERN_DETECT); + $finish; + end + endcase + +// FP #100010 ping_opmode_drc_check <= 1; + + +//********************************************************* +//*** ADDITIONAL DRC +//********************************************************* +// CR 219407 -- (1) + if((AUTORESET_PATTERN_DETECT == "TRUE") && (USE_PATTERN_DETECT == "NO_PATDET")) begin + $display("Attribute Syntax Error : The attribute USE_PATTERN_DETECT on DSP48E instance %m must be set to PATDET in order to use AUTORESET_PATTERN_DETECT equals TRUE. Failure to do so could make timing reports inaccurate. "); + end + + end + +//********************************************************* +//*** Input register A with 2 level deep of registers +//********************************************************* + + always @(ACIN or A) begin + case (A_INPUT) + "DIRECT" : a_o_mux <= A; + "CASCADE" : a_o_mux <= ACIN; + default : begin + $display("Attribute Syntax Error : The attribute A_INPUT on DSP48E instance %m is set to %s. Legal values for this attribute are DIRECT or CASCADE.", A_INPUT); + $finish; + end + endcase + end + + always @(posedge CLK) begin + if (RSTA) begin + qa_o_reg1 <= 30'b0; + qa_o_reg2 <= 30'b0; + end + else begin + case (AREG) + 1 : if (CEA2) + qa_o_reg2 <= a_o_mux; + + 2 : begin + if (CEA1) + qa_o_reg1 <= a_o_mux; + if (CEA2) + qa_o_reg2 <= qa_o_reg1; + end + default : ; + endcase + end + end + + always @(a_o_mux or qa_o_reg1 or qa_o_reg2) begin + case (AREG) + 0 : qa_o_mux <= a_o_mux; + 1,2 : qa_o_mux <= qa_o_reg2; + default : begin + $display("Attribute Syntax Error : The attribute AREG on DSP48E instance %m is set to %d. Legal values for this attribute are 0, 1 or 2.", AREG); + $finish; + end + endcase + end + + always @(qa_o_mux or qa_o_reg1 or qa_o_reg2) begin + case (ACASCREG) + 1 : if(AREG == 2) + qacout_o_mux <= qa_o_reg1; + else + qacout_o_mux <= qa_o_mux; + default : qacout_o_mux <= qa_o_mux; + endcase + end + +//********************************************************* +//*** Input register B with 2 level deep of registers +//********************************************************* + + always @(BCIN or B) begin + case (B_INPUT) + "DIRECT" : b_o_mux <= B; + "CASCADE" : b_o_mux <= BCIN; + default : begin + $display("Attribute Syntax Error : The attribute B_INPUT on DSP48E instance %m is set to %s. Legal values for this attribute are DIRECT or CASCADE.", B_INPUT); + $finish; + end + endcase + end + + always @(posedge CLK) begin + if (RSTB) begin + qb_o_reg1 <= 18'b0; + qb_o_reg2 <= 18'b0; + end + else begin + case (BREG) + 1 : if (CEB2) + qb_o_reg2 <= b_o_mux; + + 2 : begin + if (CEB1) + qb_o_reg1 <= b_o_mux; + if (CEB2) + qb_o_reg2 <= qb_o_reg1; + end + default : ; + endcase + end + end + + always @(b_o_mux or qb_o_reg1 or qb_o_reg2) begin + case (BREG) + 0 : qb_o_mux <= b_o_mux; + 1,2 : qb_o_mux <= qb_o_reg2; + default : begin + $display("Attribute Syntax Error : The attribute BREG on DSP48E instance %m is set to %d. Legal values for this attribute are 0, 1 or 2.", BREG); + $finish; + end + endcase + end + + always @(qb_o_mux or qb_o_reg1 or qb_o_reg2) begin + case (BCASCREG) + 1 : if(BREG == 2) + qbcout_o_mux <= qb_o_reg1; + else + qbcout_o_mux <= qb_o_mux; + default : qbcout_o_mux <= qb_o_mux; + endcase + end + +//********************************************************* +//*** Input register C with 1 level deep of register +//********************************************************* + + always @(posedge CLK) begin + if (RSTC) + qc_o_reg1 <= 48'b0; + else if (CEC) + qc_o_reg1 <= C; + end + + always @(C or qc_o_reg1) begin + case (CREG) + 0 : qc_o_mux <= C; + 1 : qc_o_mux <= qc_o_reg1; + default : begin + $display("Attribute Syntax Error : The attribute CREG on DSP48E instance %m is set to %d. Legal values for this attribute are 0 or 1.", CREG); + $finish; + end + endcase + end + +//********************************************************* +//*************** 25x18 Multiplier *************** +//********************************************************* +// 05/26/05 -- FP -- Added warning for invalid mult when USE_MULT=NONE +// SIMD=FOUR12 and SIMD=TWO24 +// Made mult_o to be "X" + + always @(qopmode_o_mux) begin + if(qopmode_o_mux[3:0] == 4'b0101) + if((USE_MULT == "NONE") || (USE_SIMD == "TWO24") || (USE_SIMD == "FOUR12")) + $display("OPMODE Input Warning : The OPMODE[3:0] %b to DSP48E instance %m is invalid when using attributes USE_MULT = NONE, or USE_SIMD = TWO24 or FOUR12 at %.3f ns.", qopmode_o_mux[3:0], $time/1000.0); + end + + assign mult_o = ((USE_MULT == "NONE") || (USE_SIMD == "TWO24") || (USE_SIMD == "FOUR12"))? 43'b0 : {{18{qa_o_mux[24]}}, qa_o_mux[24:0]} * {{25{qb_o_mux[17]}}, qb_o_mux}; + + always @(posedge CLK) begin + if (RSTM) begin + qmult_o_reg <= 18'b0; + end + else if (CEM) begin + qmult_o_reg <= mult_o; + end + end + + always @(mult_o or qmult_o_reg) begin + case (MREG) + 0 : qmult_o_mux <= mult_o; + 1 : qmult_o_mux <= qmult_o_reg; + default : begin + $display("Attribute Syntax Error : The attribute MREG on DSP48E instance %m is set to %d. Legal values for this attribute are 0 or 1.", MREG); + $finish; + end + endcase + end + + +//*** X mux + + always @(qp_o_mux or qa_o_mux or qb_o_mux or qmult_o_mux or qopmode_o_mux or qcarryinsel_o_mux) begin + case (qopmode_o_mux[1:0]) + 2'b00 : qx_o_mux <= 48'b0; + 2'b01 : qx_o_mux <= {{5{qmult_o_mux[MSB_A_MULT + MSB_B_MULT + 1]}}, qmult_o_mux}; + 2'b10 : qx_o_mux <= qp_o_mux; +// 438456 & 448147 & 451453 + 2'b11 : begin + qx_o_mux <= ((USE_MULT == "MULT_S") && (AREG == 0 || BREG == 0 ))? 48'bx : {qa_o_mux[MSB_A:0], qb_o_mux[MSB_B:0]}; + if((USE_MULT == "MULT_S") && (AREG == 0 || BREG == 0 )) + $display("DRC warning: When attribute USE_MULT on DSP48E instance %m is set to MULT_S, the A:B opmode selection is not permitted when AREG or BREG=0. If the multiplier is not used, set USE_MULT = NONE. For dynamic switching between multiply and add operation, set AREG and BREG=1 or MREG=0 and USE_MULT=MULT."); + end + default : begin + end + endcase + end + + +//*** Y mux + + always @(qc_o_mux or qopmode_o_mux or qcarryinsel_o_mux or MULTSIGNIN) begin + case (qopmode_o_mux[3:2]) + 2'b00 : qy_o_mux <= 48'b0; + 2'b01 : qy_o_mux <= 48'b0; + + 2'b10 : if((qopmode_o_mux[6:4]) == 3'b100) + qy_o_mux <= {48{MULTSIGNIN}}; + else + qy_o_mux <= 48'hFFFFFFFFFFFF; + + 2'b11 : qy_o_mux <= qc_o_mux; + default : begin + end + endcase + end + + +//*** Z mux + + always @(qp_o_mux or qc_o_mux or PCIN or qopmode_o_mux or qcarryinsel_o_mux) begin + case (qopmode_o_mux[6:4]) + 3'b000 : qz_o_mux <= 48'b0; + 3'b001 : qz_o_mux <= PCIN; + 3'b010 : qz_o_mux <= qp_o_mux; + 3'b011 : qz_o_mux <= qc_o_mux; + 3'b100 : qz_o_mux <= qp_o_mux; // Use for MACC extend -- multsignin + 3'b101 : qz_o_mux <= {{17{PCIN[47]}}, PCIN[47:17]}; + 3'b110 : qz_o_mux <= {{17{qp_o_mux[47]}}, qp_o_mux[47:17]}; + default : begin + end + endcase + end + + + +//*** CarryInSel and OpMode with 1 level of register + always @(posedge CLK) begin + if (RSTCTRL) begin + qcarryinsel_o_reg1 <= 3'b0; + qopmode_o_reg1 <= 7'b0; + end + else if (CECTRL) begin + qcarryinsel_o_reg1 <= CARRYINSEL; + qopmode_o_reg1 <= OPMODE; + end + end + + + always @(CARRYINSEL or qcarryinsel_o_reg1) begin + case (CARRYINSELREG) + 0 : qcarryinsel_o_mux <= CARRYINSEL; + 1 : qcarryinsel_o_mux <= qcarryinsel_o_reg1; + default : begin + $display("Attribute Syntax Error : The attribute CARRYINSELREG on DSP48E instance %m is set to %d. Legal values for this attribute are 0 or 1.", CARRYINSELREG); + $finish; + end + endcase + end + +//CR 219047 (3) + +// always @(qcarryinsel_o_mux or MULTSIGNIN or qopmode_o_mux) begin +// always @(CARRYCASCIN or MULTSIGNIN or qopmode_o_mux) begin + always @(qcarryinsel_o_mux or CARRYCASCIN or MULTSIGNIN or qopmode_o_mux) begin + if(qcarryinsel_o_mux == 3'b010) begin + if(!((MULTSIGNIN === 1'bx) || ((qopmode_o_mux == 7'b1001000) && !(MULTSIGNIN === 1'bx)) + || ((MULTSIGNIN == 1'b0) && (CARRYCASCIN == 1'b0)))) begin +// CR 451453 -- DRC warning timescale +// CR 451178 -- DRC warning Enhancement + $display("DRC warning : CARRYCASCIN can only be used in the current DSP48E instance %m if the previous DSP48E is performing a two input ADD operation, or the current DSP48E is configured in the MAC extend opmode 7'b1001000 at %.3f ns. This warning can be also triggered if OPMODEREG is set to 1 and CARRYINSELREG is set to 0 - in which case please set CARRYINSELREG to 1.", $time/1000.0); + end + end + end + +//CR 219047 (4) + always @(qcarryinsel_o_mux) begin + if((qcarryinsel_o_mux == 3'b110) && (MULTCARRYINREG != MREG)) begin + $display("Attribute Syntax Warning : It is recommended that MREG and MULTCARRYINREG on DSP48E instance %m be set to the same value when using CARRYINSEL = 110 for multiply rounding."); + end + end + + + always @(OPMODE or qopmode_o_reg1) begin + case (OPMODEREG) + 0 : qopmode_o_mux <= OPMODE; + 1 : qopmode_o_mux <= qopmode_o_reg1; + default : begin + $display("Attribute Syntax Error : The attribute OPMODEREG on DSP48E instance %m is set to %d. Legal values for this attribute are 0 or 1.", OPMODEREG); + $finish; + end + endcase + end + + + +//*** ALUMODE with 1 level of register + always @(posedge CLK) begin + if (RSTALUMODE) + qalumode_o_reg1 <= 4'b0; + else if (CEALUMODE) + qalumode_o_reg1 <= ALUMODE; + end + + + always @(ALUMODE or qalumode_o_reg1) begin + case (ALUMODEREG) + 0 : qalumode_o_mux <= ALUMODE; + 1 : qalumode_o_mux <= qalumode_o_reg1; + default : begin + $display("Attribute Syntax Error : The attribute ALUMODEREG on DSP48E instance %m is set to %d. Legal values for this attribute are 0 or 1.", ALUMODEREG); + $finish; + end + endcase + end + + +//------------------------------------------------------------------ +//*** DRC for OPMODE +//------------------------------------------------------------------ + +//--#################################################################### +//--##### ALU ##### +//--#################################################################### + + always @(qx_o_mux or qy_o_mux or qz_o_mux or qalumode_o_mux, qopmode_o_mux or qcarryin_o_mux) begin + if (opmode_valid_flag) begin + + casex ({qopmode_o_mux[3:2], qalumode_o_mux}) + //--------- ADD -------------- + 6'bXX0000 : begin + + case (USE_SIMD) + "ONE48", "one48" : begin + // verilog will zero_pad qx, qy and qz before addition + alu_full_tmp = qz_o_mux + (qx_o_mux + qy_o_mux + qcarryin_o_mux); + alu_o = alu_full_tmp[MSB_ALU_FULL:0]; + carrycascout_o = alu_full_tmp[MAX_ALU_FULL]; + // -- if multiply operation then "X"out the carryout + if((qopmode_o_mux[1:0] == 2'b01) || (qopmode_o_mux[3:2] == 2'b01)) + carryout_o = 4'bx; + else begin + carryout_o[3] = alu_full_tmp[MAX_ALU_FULL]; + carryout_o[2] = 1'bx; + carryout_o[1] = 1'bx; + carryout_o[0] = 1'bx; + end + end + "TWO24", "two24" : begin + alu_hlf1_tmp = qz_o_mux[((1*MAX_ALU_HALF)-1):0] + (qx_o_mux[((1*MAX_ALU_HALF)-1):0] + + qy_o_mux[((1*MAX_ALU_HALF)-1):0] + qcarryin_o_mux); + + alu_hlf2_tmp = qz_o_mux[((2*MAX_ALU_HALF)-1):(1*MAX_ALU_HALF)] + + (qx_o_mux[((2*MAX_ALU_HALF)-1):(1*MAX_ALU_HALF)] + + qy_o_mux[((2*MAX_ALU_HALF)-1):(1*MAX_ALU_HALF)] ); + + alu_o = { alu_hlf2_tmp[MSB_ALU_HALF:0], alu_hlf1_tmp[MSB_ALU_HALF:0]}; + + carrycascout_o = alu_hlf2_tmp[MAX_ALU_HALF]; + // -- if multiply operation then "X"out the carryout + if((qopmode_o_mux[1:0] == 2'b01) || (qopmode_o_mux[3:2] == 2'b01)) + carryout_o = 4'bx; + else begin + carryout_o[3] = alu_hlf2_tmp[MAX_ALU_HALF]; + carryout_o[2] = 1'bx; + carryout_o[1] = alu_hlf1_tmp[MAX_ALU_HALF]; + carryout_o[0] = 1'bx; + end + end + "FOUR12", "four12" : begin + alu_qrt1_tmp = qz_o_mux[((1*MAX_ALU_QUART)-1):0] + (qx_o_mux[((1*MAX_ALU_QUART)-1):0] + + qy_o_mux[((1*MAX_ALU_QUART)-1):0] + qcarryin_o_mux); + + alu_qrt2_tmp = qz_o_mux[((2*MAX_ALU_QUART)-1):(1*MAX_ALU_QUART)] + + (qx_o_mux[((2*MAX_ALU_QUART)-1):(1*MAX_ALU_QUART)] + + qy_o_mux[((2*MAX_ALU_QUART)-1):(1*MAX_ALU_QUART)] ); + + alu_qrt3_tmp = qz_o_mux[((3*MAX_ALU_QUART)-1):(2*MAX_ALU_QUART)] + + (qx_o_mux[((3*MAX_ALU_QUART)-1):(2*MAX_ALU_QUART)] + + qy_o_mux[((3*MAX_ALU_QUART)-1):(2*MAX_ALU_QUART)] ); + + alu_qrt4_tmp = qz_o_mux[((4*MAX_ALU_QUART)-1):(3*MAX_ALU_QUART)] + + (qx_o_mux[((4*MAX_ALU_QUART)-1):(3*MAX_ALU_QUART)] + + qy_o_mux[((4*MAX_ALU_QUART)-1):(3*MAX_ALU_QUART)] ); + + alu_o = { alu_qrt4_tmp[MSB_ALU_QUART:0], alu_qrt3_tmp[MSB_ALU_QUART:0], + alu_qrt2_tmp[MSB_ALU_QUART:0], alu_qrt1_tmp[MSB_ALU_QUART:0]}; + + carrycascout_o = alu_qrt4_tmp[MAX_ALU_QUART]; + // -- if multiply operation then "X"out the carryout + if((qopmode_o_mux[1:0] == 2'b01) || (qopmode_o_mux[3:2] == 2'b01)) + carryout_o = 4'bx; + else begin + carryout_o[3] = alu_qrt4_tmp[MAX_ALU_QUART]; + carryout_o[2] = alu_qrt3_tmp[MAX_ALU_QUART]; + carryout_o[1] = alu_qrt2_tmp[MAX_ALU_QUART]; + carryout_o[0] = alu_qrt1_tmp[MAX_ALU_QUART]; + end + + end + default : begin + $display("Attribute Syntax Error : The attribute USE_SIMD on DSP48E instance %m is set to %s. Legal values for this attribute are ONE48 or TWO24 or FOUR12.", USE_SIMD); + $finish; + end + endcase + end + //----------------- SUBTRACT (X + ~Z ) carryin must be 1 --------------- + 6'bXX0001 : begin + + case (USE_SIMD) + "ONE48", "one48" : begin + // verilog will zero_pad qx, qy and qz before inversing/addition + alu_full_tmp = ~qz_o_mux + (qx_o_mux + qy_o_mux + qcarryin_o_mux); + alu_o = alu_full_tmp[MSB_ALU_FULL:0]; + carrycascout_o = ~alu_full_tmp[MAX_ALU_FULL]; + // -- if multiply operation then "X"out the carryout + if((qopmode_o_mux[1:0] == 2'b01) || (qopmode_o_mux[3:2] == 2'b01)) + carryout_o = 4'bx; + else begin + carryout_o[3] = ~alu_full_tmp[MAX_ALU_FULL]; + carryout_o[2] = 1'bx; + carryout_o[1] = 1'bx; + carryout_o[0] = 1'bx; + end + end + "TWO24", "two24" : begin + alu_hlf1_tmp = ~qz_o_mux[((1*MAX_ALU_HALF)-1):0] + (qx_o_mux[((1*MAX_ALU_HALF)-1):0] + + qy_o_mux[((1*MAX_ALU_HALF)-1):0] + qcarryin_o_mux); + + alu_hlf2_tmp = ~qz_o_mux[((2*MAX_ALU_HALF)-1):(1*MAX_ALU_HALF)] + + (qx_o_mux[((2*MAX_ALU_HALF)-1):(1*MAX_ALU_HALF)] + + qy_o_mux[((2*MAX_ALU_HALF)-1):(1*MAX_ALU_HALF)] ); + + alu_o = { alu_hlf2_tmp[MSB_ALU_HALF:0], alu_hlf1_tmp[MSB_ALU_HALF:0]}; + + carrycascout_o = ~alu_hlf2_tmp[MAX_ALU_HALF]; + // -- if multiply operation then "X"out the carryout + if((qopmode_o_mux[1:0] == 2'b01) || (qopmode_o_mux[3:2] == 2'b01)) + carryout_o = 4'bx; + else begin + carryout_o[3] = ~alu_hlf2_tmp[MAX_ALU_HALF]; + carryout_o[2] = 1'bx; + carryout_o[1] = ~alu_hlf1_tmp[MAX_ALU_HALF]; + carryout_o[0] = 1'bx; + end + end + "FOUR12", "four12" : begin + alu_qrt1_tmp = ~qz_o_mux[((1*MAX_ALU_QUART)-1):0] + (qx_o_mux[((1*MAX_ALU_QUART)-1):0] + + qy_o_mux[((1*MAX_ALU_QUART)-1):0] + qcarryin_o_mux); + + alu_qrt2_tmp = ~qz_o_mux[((2*MAX_ALU_QUART)-1):(1*MAX_ALU_QUART)] + + (qx_o_mux[((2*MAX_ALU_QUART)-1):(1*MAX_ALU_QUART)] + + qy_o_mux[((2*MAX_ALU_QUART)-1):(1*MAX_ALU_QUART)] ); + + alu_qrt3_tmp = ~qz_o_mux[((3*MAX_ALU_QUART)-1):(2*MAX_ALU_QUART)] + + (qx_o_mux[((3*MAX_ALU_QUART)-1):(2*MAX_ALU_QUART)] + + qy_o_mux[((3*MAX_ALU_QUART)-1):(2*MAX_ALU_QUART)] ); + + alu_qrt4_tmp = ~qz_o_mux[((4*MAX_ALU_QUART)-1):(3*MAX_ALU_QUART)] + + (qx_o_mux[((4*MAX_ALU_QUART)-1):(3*MAX_ALU_QUART)] + + qy_o_mux[((4*MAX_ALU_QUART)-1):(3*MAX_ALU_QUART)] ); + + alu_o = { alu_qrt4_tmp[MSB_ALU_QUART:0], alu_qrt3_tmp[MSB_ALU_QUART:0], + alu_qrt2_tmp[MSB_ALU_QUART:0], alu_qrt1_tmp[MSB_ALU_QUART:0]}; + + carrycascout_o = ~alu_qrt4_tmp[MAX_ALU_QUART]; + // -- if multiply operation then "X"out the carryout + if((qopmode_o_mux[1:0] == 2'b01) || (qopmode_o_mux[3:2] == 2'b01)) + carryout_o = 4'bx; + else begin + carryout_o[3] = ~alu_qrt4_tmp[MAX_ALU_QUART]; + carryout_o[2] = ~alu_qrt3_tmp[MAX_ALU_QUART]; + carryout_o[1] = ~alu_qrt2_tmp[MAX_ALU_QUART]; + carryout_o[0] = ~alu_qrt1_tmp[MAX_ALU_QUART]; + end + + end + default : begin + $display("Attribute Syntax Error : The attribute USE_SIMD on DSP48E instance %m is set to %s. Legal values for this attribute are ONE48 or TWO24 or FOUR12.", USE_SIMD); + $finish; + end + endcase + end + + //----------------- NOT (X + Z) ---------------------------------------- + 6'bXX0010 : begin + + case (USE_SIMD) + "ONE48", "one48" : begin + alu_full_tmp = ~(qz_o_mux + (qx_o_mux + qy_o_mux + qcarryin_o_mux)); + alu_o = alu_full_tmp[MSB_ALU_FULL:0]; + carrycascout_o = ~alu_full_tmp[MAX_ALU_FULL]; + // -- if multiply operation then "X"out the carryout + if((qopmode_o_mux[1:0] == 2'b01) || (qopmode_o_mux[3:2] == 2'b01)) + carryout_o = 4'bx; + else begin + carryout_o[3] = ~alu_full_tmp[MAX_ALU_FULL]; + carryout_o[2] = 1'bx; + carryout_o[1] = 1'bx; + carryout_o[0] = 1'bx; + end + end + "TWO24", "two24" : begin + alu_hlf1_tmp = ~(qz_o_mux[((1*MAX_ALU_HALF)-1):0] + (qx_o_mux[((1*MAX_ALU_HALF)-1):0] + + qy_o_mux[((1*MAX_ALU_HALF)-1):0] + qcarryin_o_mux)); + + alu_hlf2_tmp = ~(qz_o_mux[((2*MAX_ALU_HALF)-1):(1*MAX_ALU_HALF)] + + (qx_o_mux[((2*MAX_ALU_HALF)-1):(1*MAX_ALU_HALF)] + + qy_o_mux[((2*MAX_ALU_HALF)-1):(1*MAX_ALU_HALF)] )); + + alu_o = { alu_hlf2_tmp[MSB_ALU_HALF:0], alu_hlf1_tmp[MSB_ALU_HALF:0]}; + + carrycascout_o = ~alu_hlf2_tmp[MAX_ALU_HALF]; + // -- if multiply operation then "X"out the carryout + if((qopmode_o_mux[1:0] == 2'b01) || (qopmode_o_mux[3:2] == 2'b01)) + carryout_o = 4'bx; + else begin + carryout_o[3] = ~alu_hlf2_tmp[MAX_ALU_HALF]; + carryout_o[2] = 1'bx; + carryout_o[1] = ~alu_hlf1_tmp[MAX_ALU_HALF]; + carryout_o[0] = 1'bx; + end + end + "FOUR12", "four12" : begin + alu_qrt1_tmp = ~(qz_o_mux[((1*MAX_ALU_QUART)-1):0] + (qx_o_mux[((1*MAX_ALU_QUART)-1):0] + + qy_o_mux[((1*MAX_ALU_QUART)-1):0] + qcarryin_o_mux)); + + alu_qrt2_tmp = ~(qz_o_mux[((2*MAX_ALU_QUART)-1):(1*MAX_ALU_QUART)] + + (qx_o_mux[((2*MAX_ALU_QUART)-1):(1*MAX_ALU_QUART)] + + qy_o_mux[((2*MAX_ALU_QUART)-1):(1*MAX_ALU_QUART)] )); + + alu_qrt3_tmp = ~(qz_o_mux[((3*MAX_ALU_QUART)-1):(2*MAX_ALU_QUART)] + + (qx_o_mux[((3*MAX_ALU_QUART)-1):(2*MAX_ALU_QUART)] + + qy_o_mux[((3*MAX_ALU_QUART)-1):(2*MAX_ALU_QUART)] )); + + alu_qrt4_tmp = ~(qz_o_mux[((4*MAX_ALU_QUART)-1):(3*MAX_ALU_QUART)] + + (qx_o_mux[((4*MAX_ALU_QUART)-1):(3*MAX_ALU_QUART)] + + qy_o_mux[((4*MAX_ALU_QUART)-1):(3*MAX_ALU_QUART)] )); + + alu_o = { alu_qrt4_tmp[MSB_ALU_QUART:0], alu_qrt3_tmp[MSB_ALU_QUART:0], + alu_qrt2_tmp[MSB_ALU_QUART:0], alu_qrt1_tmp[MSB_ALU_QUART:0]}; + + carrycascout_o = ~alu_qrt4_tmp[MAX_ALU_QUART]; + // -- if multiply operation then "X"out the carryout + if((qopmode_o_mux[1:0] == 2'b01) || (qopmode_o_mux[3:2] == 2'b01)) + carryout_o = 4'bx; + else begin + carryout_o[3] = ~alu_qrt4_tmp[MAX_ALU_QUART]; + carryout_o[2] = ~alu_qrt3_tmp[MAX_ALU_QUART]; + carryout_o[1] = ~alu_qrt2_tmp[MAX_ALU_QUART]; + carryout_o[0] = ~alu_qrt1_tmp[MAX_ALU_QUART]; + end + + end + default : begin + $display("Attribute Syntax Error : The attribute USE_SIMD on DSP48E instance %m is set to %s. Legal values for this attribute are ONE48 or TWO24 or FOUR12.", USE_SIMD); + $finish; + end + endcase + end + //----------------- SUBTRACT (Z - X) ---------------------------------- + 6'bXX0011 : begin + + case (USE_SIMD) + "ONE48", "one48" : begin + alu_full_tmp = qz_o_mux - (qx_o_mux + qy_o_mux + qcarryin_o_mux); + alu_o = alu_full_tmp[MSB_ALU_FULL:0]; + carrycascout_o = alu_full_tmp[MAX_ALU_FULL]; + // -- if multiply operation then "X"out the carryout + if((qopmode_o_mux[1:0] == 2'b01) || (qopmode_o_mux[3:2] == 2'b01)) + carryout_o = 4'bx; + else begin + carryout_o[3] = ~alu_full_tmp[MAX_ALU_FULL]; + carryout_o[2] = 1'bx; + carryout_o[1] = 1'bx; + carryout_o[0] = 1'bx; + end + end + "TWO24", "two24" : begin + alu_hlf1_tmp = qz_o_mux[((1*MAX_ALU_HALF)-1):0] - (qx_o_mux[((1*MAX_ALU_HALF)-1):0] + + qy_o_mux[((1*MAX_ALU_HALF)-1):0] + qcarryin_o_mux); + + alu_hlf2_tmp = qz_o_mux[((2*MAX_ALU_HALF)-1):(1*MAX_ALU_HALF)] - + (qx_o_mux[((2*MAX_ALU_HALF)-1):(1*MAX_ALU_HALF)] + + qy_o_mux[((2*MAX_ALU_HALF)-1):(1*MAX_ALU_HALF)] ); + + alu_o = { alu_hlf2_tmp[MSB_ALU_HALF:0], alu_hlf1_tmp[MSB_ALU_HALF:0]}; + + carrycascout_o = alu_hlf2_tmp[MAX_ALU_HALF]; + // -- if multiply operation then "X"out the carryout + if((qopmode_o_mux[1:0] == 2'b01) || (qopmode_o_mux[3:2] == 2'b01)) + carryout_o = 4'bx; + else begin + carryout_o[3] = ~alu_hlf2_tmp[MAX_ALU_HALF]; + carryout_o[2] = 1'bx; + carryout_o[1] = ~alu_hlf1_tmp[MAX_ALU_HALF]; + carryout_o[0] = 1'bx; + end + end + "FOUR12", "four12" : begin + alu_qrt1_tmp = qz_o_mux[((1*MAX_ALU_QUART)-1):0] - (qx_o_mux[((1*MAX_ALU_QUART)-1):0] + + qy_o_mux[((1*MAX_ALU_QUART)-1):0] + qcarryin_o_mux); + + alu_qrt2_tmp = qz_o_mux[((2*MAX_ALU_QUART)-1):(1*MAX_ALU_QUART)] - + (qx_o_mux[((2*MAX_ALU_QUART)-1):(1*MAX_ALU_QUART)] + + qy_o_mux[((2*MAX_ALU_QUART)-1):(1*MAX_ALU_QUART)] ); + + alu_qrt3_tmp = qz_o_mux[((3*MAX_ALU_QUART)-1):(2*MAX_ALU_QUART)] - + (qx_o_mux[((3*MAX_ALU_QUART)-1):(2*MAX_ALU_QUART)] + + qy_o_mux[((3*MAX_ALU_QUART)-1):(2*MAX_ALU_QUART)] ); + + alu_qrt4_tmp = qz_o_mux[((4*MAX_ALU_QUART)-1):(3*MAX_ALU_QUART)] - + (qx_o_mux[((4*MAX_ALU_QUART)-1):(3*MAX_ALU_QUART)] + + qy_o_mux[((4*MAX_ALU_QUART)-1):(3*MAX_ALU_QUART)] ); + + alu_o = { alu_qrt4_tmp[MSB_ALU_QUART:0], alu_qrt3_tmp[MSB_ALU_QUART:0], + alu_qrt2_tmp[MSB_ALU_QUART:0], alu_qrt1_tmp[MSB_ALU_QUART:0]}; + + carrycascout_o = alu_qrt4_tmp[MAX_ALU_QUART]; + // -- if multiply operation then "X"out the carryout + if((qopmode_o_mux[1:0] == 2'b01) || (qopmode_o_mux[3:2] == 2'b01)) + carryout_o = 4'bx; + else begin + carryout_o[3] = ~alu_qrt4_tmp[MAX_ALU_QUART]; + carryout_o[2] = ~alu_qrt3_tmp[MAX_ALU_QUART]; + carryout_o[1] = ~alu_qrt2_tmp[MAX_ALU_QUART]; + carryout_o[0] = ~alu_qrt1_tmp[MAX_ALU_QUART]; + end + + end + default : begin + $display("Attribute Syntax Error : The attribute USE_SIMD on DSP48E instance %m is set to %s. Legal values for this attribute are ONE48 or TWO24 or FOUR12.", USE_SIMD); + $finish; + end + endcase + end +//---------------------------------------------------------- + //--------------- XOR ------------------ + 6'b000100, 6'b000111, 6'b100101, 6'b100110 : begin + alu_o = qx_o_mux ^ qz_o_mux; + carryout_o = 4'bx; + carrycascout_o = 1'bx; + end + + //--------------- XNOR ------------------ + 6'b000101, 6'b000110, 6'b100100, 6'b100111 : begin + alu_o = qx_o_mux ~^ qz_o_mux; + carryout_o = 4'bx; + carrycascout_o = 1'bx; + end +//---------------------------------------------------------- + + //--------------- AND ------------------ + 6'b001100 : begin + alu_o = qx_o_mux & qz_o_mux; + carryout_o = 4'bx; + carrycascout_o = 1'bx; + end + + //--------------- X AND (NOT Z) ------------------ + 6'b001101 : begin + alu_o = qx_o_mux & (~qz_o_mux); + carryout_o = 4'bx; + carrycascout_o = 1'bx; + end + + //--------------- X NAND Z ------------------ + 6'b001110 : begin + alu_o = ~(qx_o_mux & qz_o_mux); + carryout_o = 4'bx; + carrycascout_o = 1'bx; + end + + //--------------- (NOT X) OR Z ------------------ + 6'b001111 : begin + alu_o = (~qx_o_mux) | (qz_o_mux); + carryout_o = 4'bx; + carrycascout_o = 1'bx; + end +//---------------------------------------------------------- + + //--------------- X OR Z ------------------ + 6'b101100 : begin + alu_o = qx_o_mux | qz_o_mux; + carryout_o = 4'bx; + carrycascout_o = 1'bx; + end + + //--------------- X OR ~Z ------------------ + 6'b101101 : begin + alu_o = (qx_o_mux) | (~qz_o_mux); + carryout_o = 4'bx; + carrycascout_o = 1'bx; + end + + //--------------- X NOR Z ------------------ + 6'b101110 : begin + alu_o = ~((qx_o_mux) | (qz_o_mux)); + carryout_o = 4'bx; + carrycascout_o = 1'bx; + end + + //--------------- (NOT X) and Z ------------------ + 6'b101111 : begin + alu_o = (~qx_o_mux) & (qz_o_mux); + carryout_o = 4'bx; + carrycascout_o = 1'bx; + end + +//---------------------------------------------------------- +//---------------------------------------------------------- + + default : begin + alu_o = 48'bx; + carryout_o = 4'bx; + carrycascout_o = 1'bx; + + $display("ALUMODE Input Warning : The ALUMODE %b to DSP48E instance %m is either invalid or the OPMODE %b for that specific ALUMODE is invalid at %.3f ns.", qalumode_o_mux, qopmode_o_mux, $time/1000.0); + end + endcase + + end + + end // always @ (qalumode_o_mux) + +//*** CarryIn Mux and Register + +//------- input 0 + always @(posedge CLK) begin + if (RSTALLCARRYIN) + qcarryin_o_reg0 <= 1'b0; + else if (CECARRYIN) + qcarryin_o_reg0 <= CARRYIN; + end + + always @(CARRYIN or qcarryin_o_reg0) begin + case (CARRYINREG) + 0 : qcarryin_o_mux0 <= CARRYIN; + 1 : qcarryin_o_mux0 <= qcarryin_o_reg0; + default : begin + $display("Attribute Syntax Error : The attribute CARRYINREG on DSP48E instance %m is set to %d. Legal values for this attribute are 0 or 1.", CARRYINREG); + $finish; + end + endcase + end + +//------- input 7 + always @(posedge CLK) begin + if (RSTALLCARRYIN) + qcarryin_o_reg7 <= 1'b0; + else if (CEMULTCARRYIN) + qcarryin_o_reg7 <= qa_o_mux[24] ~^ qb_o_mux[17]; // xnor + end + + always @(qa_o_mux[24] or qb_o_mux[17] or qcarryin_o_reg7) begin + case (MULTCARRYINREG) + 0 : qcarryin_o_mux7 <= qa_o_mux[24] ~^ qb_o_mux[17]; + 1 : qcarryin_o_mux7 <= qcarryin_o_reg7; + default : begin + $display("Attribute Syntax Error : The attribute MULTCARRYINREG on DSP48E instance %m is set to %d. Legal values for this attribute are 0 or 1.", MULTCARRYINREG); + $finish; + end + endcase + end + + + always @(qcarryin_o_mux0 or PCIN[47] or CARRYCASCIN or carrycascout_o_mux or qp_o_mux[47], qcarryin_o_mux7, qcarryinsel_o_mux) begin + case (qcarryinsel_o_mux) + 3'b000 : qcarryin_o_mux <= qcarryin_o_mux0; + 3'b001 : qcarryin_o_mux <= ~PCIN[47]; + 3'b010 : qcarryin_o_mux <= CARRYCASCIN; + 3'b011 : qcarryin_o_mux <= PCIN[47]; + 3'b100 : qcarryin_o_mux <= carrycascout_o_mux; + 3'b101 : qcarryin_o_mux <= ~qp_o_mux[47]; + 3'b110 : qcarryin_o_mux <= qcarryin_o_mux7; + 3'b111 : qcarryin_o_mux <= qp_o_mux[47]; + default : begin + end + endcase + end +//--#################################################################### +//--##### CARRYOUT and CARRYCASCOUT ##### +//--#################################################################### +//*** register with 1 level of register + always @(posedge CLK) begin + if ((RSTP) || + ((AUTORESET_PATTERN_DETECT == "TRUE") && ( + ((AUTORESET_PATTERN_DETECT_OPTINV == "MATCH") && pdet_o_reg1) || + ((AUTORESET_PATTERN_DETECT_OPTINV == "NOT_MATCH") && (pdet_o_reg2 && !pdet_o_reg1))) + ) + ) begin + carrycascout_o_reg <= 1'b0; + carryout_o_reg <= 4'b0; + end + else if (CEP) begin + carrycascout_o_reg <= carrycascout_o; + carryout_o_reg <= carryout_o; + end + end + + always @(carryout_o or carryout_o_reg) begin + case (PREG) + 0 : carryout_o_mux <= carryout_o; + 1 : carryout_o_mux <= carryout_o_reg; + default : begin +// $display("Attribute Syntax Error : The attribute PREG on DSP48E instance %m is set to %d. Legal values for this attribute are 0 or 1.", PREG); +// $finish; + end + endcase + end + + always @(carrycascout_o or carrycascout_o_reg) begin + case (PREG) + 0 : carrycascout_o_mux <= carrycascout_o; + 1 : carrycascout_o_mux <= carrycascout_o_reg; + default : begin +// $display("Attribute Syntax Error : The attribute PREG on DSP48E instance %m is set to %d. Legal values for this attribute are 0 or 1.", PREG); +// $finish; + end + endcase + end + +//CR 219047 (2) + + always @(qmult_o_mux[(MSB_A_MULT+MSB_B_MULT+1)] or qopmode_o_mux[3:0]) begin + if(qopmode_o_mux[3:0] == 4'b0101) + multsignout_o_opmode = qmult_o_mux[(MSB_A_MULT+MSB_B_MULT+1)]; + else + multsignout_o_opmode = 1'bx; + end + + + always @(multsignout_o_opmode or qmultsignout_o_reg) begin + case (PREG) + 0 : multsignout_o_mux <= multsignout_o_opmode; + 1 : multsignout_o_mux <= qmultsignout_o_reg; + + default : begin +// $display("Attribute Syntax Error : The attribute PREG on DSP48E instance %m is set to %d. Legal values for this attribute are 0 or 1.", PREG); +// $finish; + end + endcase + end + + assign carryout_x_o[3] = carryout_o_mux[3]; + assign carryout_x_o[2] = (USE_SIMD == "FOUR12") ? carryout_o_mux[2] : 1'bx; + assign carryout_x_o[1] = ((USE_SIMD == "TWO24") || (USE_SIMD == "FOUR12")) ? carryout_o_mux[1] : 1'bx; + assign carryout_x_o[0] = (USE_SIMD == "FOUR12") ? carryout_o_mux[0] : 1'bx; + +//--#################################################################### +//--##### PCOUT and MULTSIGNOUT ##### +//--#################################################################### +//*** Output register P with 1 level of register + always @(posedge CLK) begin + if ((RSTP) || + ((AUTORESET_PATTERN_DETECT == "TRUE") && ( + ((AUTORESET_PATTERN_DETECT_OPTINV == "MATCH") && pdet_o_reg1) || + ((AUTORESET_PATTERN_DETECT_OPTINV == "NOT_MATCH") && (pdet_o_reg2 && !pdet_o_reg1))) + ) + ) + begin + qp_o_reg1 <= 48'b0; + qmultsignout_o_reg <= 1'b0; + end + else if (CEP) begin + qp_o_reg1 <= alu_o; + qmultsignout_o_reg <= multsignout_o_opmode; + end + end + + always @(qp_o_reg1 or alu_o) begin + case (PREG) + 0 : qp_o_mux <= alu_o; + 1 : qp_o_mux <= qp_o_reg1; + default : begin + $display("Attribute Syntax Error : The attribute PREG on DSP48E instance %m is set to %d. Legal values for this attribute are 0 or 1.", PREG); + $finish; + end + endcase + end + +//--#################################################################### +//--##### Pattern Detector ##### +//--#################################################################### + assign pdet_o_mux = ((USE_PATTERN_DETECT == "NO_PATDET") | ~opmode_valid_flag | ~alumode_valid_flag) ? 1'bx : (PREG == 1) ? pdet_o_reg1 : pdet_o; + assign pdetb_o_mux = ((USE_PATTERN_DETECT == "NO_PATDET") | ~opmode_valid_flag | ~alumode_valid_flag) ? 1'bx : (PREG == 1) ? pdetb_o_reg1 : pdetb_o; + + always @(alu_o, qc_o_mux, negedge GSR) begin + + //-- Select the pattern + case(SEL_PATTERN) + "PATTERN" : pattern_qp <= PATTERN; + "C" : pattern_qp <= qc_o_mux; + default : begin + $display("Attribute Syntax Error : The attribute SEL_PATTERN on DSP48E instance %m is set to %s. Legal values for this attribute are PATTERN or C.", SEL_PATTERN); + $finish; + end + endcase + + //-- Select the mask -- if ROUNDING MASK set, use rounding mode, else use SEL_MASK + case(SEL_ROUNDING_MASK) + "SEL_MASK" : + case(SEL_MASK) + "MASK" : mask_qp <= MASK; + "C" : mask_qp <= qc_o_mux; + default : begin + $display("Attribute Syntax Error : The attribute SEL_MASK on DSP48E instance %m is set to %s. Legal values for this attribute are MASK or C.", SEL_MASK); + $finish; + end + endcase + "MODE1" : mask_qp <= ~qc_o_mux << 1; + "MODE2" : mask_qp <= ~qc_o_mux << 2; + default : begin + $display("Attribute Syntax Error : The attribute SEL_ROUNDING_MASK on DSP48E instance %m is set to %s. Legal values for this attribute are SEL_MASK or MODE1 or MODE2.", SEL_ROUNDING_MASK); + $finish; + end + endcase + + end + + //-- now do the pattern detection + + always @(alu_o, mask_qp, pattern_qp, GSR) begin + if((alu_o | mask_qp) == (pattern_qp | mask_qp)) + pdet_o <= 1'b1; + else + pdet_o <= 1'b0; + + if((alu_o | mask_qp) == (~pattern_qp | mask_qp)) + pdetb_o <= 1'b1; + else + pdetb_o <= 1'b0; + end + +//*** Output register PATTERN DETECT and UNDERFLOW / OVERFLOW + always @(posedge CLK) begin + if((RSTP) || + ((AUTORESET_PATTERN_DETECT == "TRUE") && ( + ((AUTORESET_PATTERN_DETECT_OPTINV == "MATCH") && pdet_o_reg1) || + ((AUTORESET_PATTERN_DETECT_OPTINV == "NOT_MATCH") && (pdet_o_reg2 && !pdet_o_reg1))) + ) + ) + begin + pdet_o_reg1 <= 1'b0; + pdet_o_reg2 <= 1'b0; + pdetb_o_reg1 <= 1'b0; + pdetb_o_reg2 <= 1'b0; + end + else if(CEP) + begin + //-- the previous values are used in Underflow/Overflow + pdet_o_reg2 <= pdet_o_reg1; + pdet_o_reg1 <= pdet_o; + pdetb_o_reg2 <= pdetb_o_reg1; + pdetb_o_reg1 <= pdetb_o; + end + end + +//--#################################################################### +//--##### Underflow / Overflow ##### +//--#################################################################### + always @(pdet_o_reg1 or pdet_o_reg2 or pdetb_o_reg1 or pdetb_o_reg2) begin + case (USE_PATTERN_DETECT) + "NO_PATDET" : begin + overflow_o <= 1'bx; + underflow_o <= 1'bx; + end + default : begin + case (PREG) + + 0 : begin + overflow_o <= 1'bx; + underflow_o <= 1'bx; + end + default : begin + + overflow_o <= pdet_o_reg2 & !pdet_o_reg1 & !pdetb_o_reg1; + underflow_o <= pdetb_o_reg2 & !pdet_o_reg1 & !pdetb_o_reg1; + end + endcase + end + endcase + end + + + end +endgenerate + + + assign ACOUT = qacout_o_mux; + assign BCOUT = qbcout_o_mux; + assign CARRYCASCOUT = carrycascout_o_mux; + assign CARRYOUT = carryout_x_o; + assign MULTSIGNOUT = multsignout_o_mux; + assign OVERFLOW = overflow_o; + assign P = qp_o_mux; + assign PCOUT = qp_o_mux; + assign PATTERNDETECT = pdet_o_mux; + assign PATTERNBDETECT = pdetb_o_mux; + assign UNDERFLOW = underflow_o; + specify + + (CLK *> ACOUT) = (100, 100); + (CLK *> BCOUT) = (100, 100); + (CLK *> CARRYCASCOUT) = (100, 100); + (CLK *> CARRYOUT) = (100, 100); + (CLK *> MULTSIGNOUT) = (100, 100); + (CLK *> OVERFLOW) = (100, 100); + (CLK *> P) = (100, 100); + (CLK *> PATTERNBDETECT) = (100, 100); + (CLK *> PATTERNDETECT) = (100, 100); + (CLK *> PCOUT) = (100, 100); + (CLK *> UNDERFLOW) = (100, 100); + + specparam PATHPULSE$ = 0; + + endspecify + +endmodule // DSP48E + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/DSP48E1.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/DSP48E1.v new file mode 100644 index 0000000..eaedbf1 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/DSP48E1.v @@ -0,0 +1,1545 @@ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / 18X18 Signed Multiplier Followed by Three-Input Adder plus ALU with Pipeline Registers +// /___/ /\ Filename : DSP48E1.v +// \ \ / \ Timestamp : Mon Sep 17 15:06:46 PDT 2007 +// \___\/\___\ +// +// Revision: +// 09/17/07 - Initial version. +// 04/15/08 - CR 468871 Negative SetupHold fix +// 05/19/08 - IR 473330 Fix for qa/qb_o_reg1 when AREG/BREG = 1 +// 06/06/08 - IR 474312 fix +// 07/08/08 - CR 473297 and 475997 fix -- removed input buffers that were causing NCSIM failures when sdf was backannotated +// 07/12/08 - IR 472222 Removed SIM_MODE attribute +// 07/18/08 - IR 477318 Overflow/Underflow generate statment issue +// 07/31/08 - IR 478377 Fixed qcarryin_o_mux7 +// 08/06/08 - IR 478378 Fixed mult sign extension +// 10/02/08 - IR 491365 Fixed timing constructs +// 03/02/09 - CR 510304 Carryout should output "X" during multiply +// 06/02/09 - CR 523600 Carryout "X"ed out before the register +// 07/07/09 - CR 525163 DRC checks for USE_MULT/OPMODE combinations +// 09/23/09 - CR 532623 Initalized interal registers +// 10/12/09 - CR 535687 Initalized d and ad registers +// 02/17/10 - CR 548358 Updated DRC check warning message +// End Revision + +`timescale 1 ps / 1 ps + +module DSP48E1 (ACOUT, BCOUT, CARRYCASCOUT, CARRYOUT, MULTSIGNOUT, OVERFLOW, P, PATTERNBDETECT, PATTERNDETECT, PCOUT, UNDERFLOW, A, ACIN, ALUMODE, B, BCIN, C, CARRYCASCIN, CARRYIN, CARRYINSEL, CEA1, CEA2, CEAD, CEALUMODE, CEB1, CEB2, CEC, CECARRYIN, CECTRL, CED, CEINMODE, CEM, CEP, CLK, D, INMODE, MULTSIGNIN, OPMODE, PCIN, RSTA, RSTALLCARRYIN, RSTALUMODE, RSTB, RSTC, RSTCTRL, RSTD, RSTINMODE, RSTM, RSTP); + + + parameter integer ACASCREG = 1; + parameter integer ADREG = 1; + parameter integer ALUMODEREG = 1; + parameter integer AREG = 1; + parameter AUTORESET_PATDET = "NO_RESET"; // {NO_RESET, RESET_MATCH, RESET_NOT_MATCH} + parameter A_INPUT = "DIRECT"; + parameter integer BCASCREG = 1; + parameter integer BREG = 1; + parameter B_INPUT = "DIRECT"; + parameter integer CARRYINREG = 1; + parameter integer CARRYINSELREG = 1; + parameter integer CREG = 1; + parameter integer DREG = 1; + parameter integer INMODEREG = 1; + parameter MASK = 48'h3FFFFFFFFFFF; + parameter integer MREG = 1; + parameter integer OPMODEREG = 1; + parameter PATTERN = 48'h000000000000; + parameter integer PREG = 1; + parameter SEL_MASK = "MASK"; + parameter SEL_PATTERN = "PATTERN"; + parameter USE_DPORT = "FALSE"; + parameter USE_MULT = "MULTIPLY"; + parameter USE_PATTERN_DETECT = "NO_PATDET"; + parameter USE_SIMD = "ONE48"; + + output [29:0] ACOUT; + output [17:0] BCOUT; + output CARRYCASCOUT; + output [3:0] CARRYOUT; + output MULTSIGNOUT; + output OVERFLOW; + output [47:0] P; + output PATTERNBDETECT; + output PATTERNDETECT; + output [47:0] PCOUT; + output UNDERFLOW; + + input [29:0] A; + input [29:0] ACIN; + input [3:0] ALUMODE; + input [17:0] B; + input [17:0] BCIN; + input [47:0] C; + input CARRYCASCIN; + input CARRYIN; + input [2:0] CARRYINSEL; + input CEA1; + input CEA2; + input CEAD; // new + input CEALUMODE; + input CEB1; + input CEB2; + input CEC; + input CECARRYIN; + input CECTRL; + input CED; // new + input CEINMODE; // new + input CEM; + input CEP; + input CLK; + input [24:0] D; // new + input [4:0] INMODE; // new + input MULTSIGNIN; + input [6:0] OPMODE; + input [47:0] PCIN; + input RSTA; + input RSTALLCARRYIN; + input RSTALUMODE; + input RSTB; + input RSTC; + input RSTCTRL; + input RSTD; // new + input RSTINMODE; // new + input RSTM; + input RSTP; + + tri0 GSR = glbl.GSR; + +//------------------- constants ------------------------- + localparam MAX_ACOUT = 30; + localparam MAX_BCOUT = 18; + localparam MAX_CARRYOUT = 4; + localparam MAX_P = 48; + localparam MAX_PCOUT = 48; + + localparam MAX_A = 30; + localparam MAX_ACIN = 30; + localparam MAX_ALUMODE = 4; + localparam MAX_A_MULT = 25; + localparam MAX_B = 18; + localparam MAX_B_MULT = 18; + localparam MAX_BCIN = 18; + localparam MAX_C = 48; + localparam MAX_CARRYINSEL = 3; + localparam MAX_D = 25; + localparam MAX_INMODE = 5; + localparam MAX_OPMODE = 7; + localparam MAX_PCIN = 48; + + localparam MAX_ALU_FULL = 48; + localparam MAX_ALU_HALF = 24; + localparam MAX_ALU_QUART = 12; + + localparam MSB_ACOUT = MAX_ACOUT - 1; + localparam MSB_BCOUT = MAX_BCOUT - 1; + localparam MSB_CARRYOUT = MAX_CARRYOUT - 1; + localparam MSB_P = MAX_P - 1; + localparam MSB_PCOUT = MAX_PCOUT - 1; + + localparam MSB_A = MAX_A - 1; + localparam MSB_ACIN = MAX_ACIN - 1; + localparam MSB_ALUMODE = MAX_ALUMODE - 1; + localparam MSB_A_MULT = MAX_A_MULT - 1; + localparam MSB_B = MAX_B - 1; + localparam MSB_B_MULT = MAX_B_MULT - 1; + localparam MSB_BCIN = MAX_BCIN - 1; + localparam MSB_C = MAX_C - 1; + localparam MSB_CARRYINSEL = MAX_CARRYINSEL - 1; + localparam MSB_D = MAX_D - 1; + localparam MSB_INMODE = MAX_INMODE - 1; + localparam MSB_OPMODE = MAX_OPMODE - 1; + localparam MSB_PCIN = MAX_PCIN - 1; + + localparam MSB_ALU_FULL = MAX_ALU_FULL - 1; + localparam MSB_ALU_HALF = MAX_ALU_HALF - 1; + localparam MSB_ALU_QUART = MAX_ALU_QUART - 1; + + localparam SHIFT_MUXZ = 17; + + reg [29:0] a_o_mux, qa_o_mux, qa_o_reg1, qa_o_reg2, qacout_o_mux; + +// new + reg [4:0] qinmode_o_mux, qinmode_o_reg; +// new + wire [24:0] a_preaddsub; + + reg [17:0] b_o_mux, qb_o_mux, qb_o_reg1, qb_o_reg2, qbcout_o_mux; + reg [2:0] qcarryinsel_o_mux, qcarryinsel_o_reg1; + +// new + reg [MSB_D:0] d_o_mux, qd_o_mux, qd_o_reg1; + + reg [(MSB_A_MULT+MSB_B_MULT+1):0] qmult_o_mux, qmult_o_reg; + reg [47:0] qc_o_mux, qc_o_reg1; + reg [47:0] qp_o_mux, qp_o_reg1; + reg [47:0] qx_o_mux, qy_o_mux, qz_o_mux; + reg [6:0] qopmode_o_mux, qopmode_o_reg1; + + + + reg qcarryin_o_mux0, qcarryin_o_reg0, qcarryin_o_mux7, qcarryin_o_reg7; + reg qcarryin_o_mux, qcarryin_o_reg; + + reg [3:0] qalumode_o_mux, qalumode_o_reg1; + + reg invalid_opmode, opmode_valid_flag, ping_opmode_drc_check = 0; + +// reg [47:0] alu_o; + wire [47:0] alu_o; + + reg qmultsignout_o_reg, multsignout_o_mux; + wire multsignout_o_opmode; + + reg [MAX_ALU_FULL:0] alu_full_tmp; + reg [MAX_ALU_HALF:0] alu_hlf1_tmp, alu_hlf2_tmp; + reg [MAX_ALU_QUART:0] alu_qrt1_tmp, alu_qrt2_tmp, alu_qrt3_tmp, alu_qrt4_tmp; + + wire pdet_o_mux, pdetb_o_mux; + + wire [47:0] the_pattern; + reg [47:0] the_mask = 0; + wire carrycascout_o; + reg carrycascout_o_reg = 0; + reg carrycascout_o_mux = 0; + +// reg [3:0] carryout_o = 0; + reg [3:0] carryout_o_reg = 0; + reg [3:0] carryout_o_mux = 0; + wire [3:0] carryout_x_o; + + wire pdet_o, pdetb_o; + reg pdet_o_reg1, pdet_o_reg2, pdetb_o_reg1, pdetb_o_reg2; + wire overflow_o, underflow_o; + + wire [(MSB_A_MULT+MSB_B_MULT+1):0] mult_o; +// new + wire [MSB_A_MULT:0] ad_addsub, ad_mult; + reg [MSB_A_MULT:0] qad_o_reg1, qad_o_mux; + wire [MSB_B_MULT:0] b_mult; + + +//*** GLOBAL hidden GSR pin + always @(GSR) begin + if (GSR) begin + assign qcarryin_o_reg0 = 1'b0; + assign qcarryinsel_o_reg1 = 3'b0; + assign qopmode_o_reg1 = 7'b0; + assign qalumode_o_reg1 = 4'b0; + assign qa_o_reg1 = 30'b0; + assign qa_o_reg2 = 30'b0; + assign qb_o_reg1 = 18'b0; + assign qb_o_reg2 = 18'b0; + assign qc_o_reg1 = 48'b0; + assign qp_o_reg1 = 48'b0; + assign qmult_o_reg = 36'b0; + assign pdet_o_reg1 = 1'b0; + assign pdet_o_reg2 = 1'b0; + assign pdetb_o_reg1 = 1'b0; + assign pdetb_o_reg2 = 1'b0; + + assign carryout_o_reg = 4'b0; + assign carrycascout_o_reg = 1'b0; + + assign qmultsignout_o_reg = 1'b0; + + assign qd_o_reg1 = 25'b0; + assign qad_o_reg1 = 25'b0; + assign qinmode_o_reg = 5'b0; + end + else begin + deassign qcarryin_o_reg0; + deassign qcarryinsel_o_reg1; + deassign qopmode_o_reg1; + deassign qalumode_o_reg1; + deassign qa_o_reg1; + deassign qa_o_reg2; + deassign qb_o_reg1; + deassign qb_o_reg2; + deassign qc_o_reg1; + deassign qp_o_reg1; + deassign qmult_o_reg; + + deassign pdet_o_reg1; + deassign pdet_o_reg2; + deassign pdetb_o_reg1; + deassign pdetb_o_reg2; + + deassign carryout_o_reg; + deassign carrycascout_o_reg; + + deassign qmultsignout_o_reg; + + deassign qd_o_reg1; + deassign qad_o_reg1; + deassign qinmode_o_reg; + end + end + + + initial begin + opmode_valid_flag <= 1; + invalid_opmode <= 1; + + //-------- A_INPUT check + + case (A_INPUT) + "DIRECT", "CASCADE" : ; + default : begin + $display("Attribute Syntax Error : The attribute A_INPUT on DSP48E1 instance %m is set to %s. Legal values for this attribute are DIRECT or CASCADE.", A_INPUT); + $finish; + end + endcase + + //-------- ALUMODEREG check + + case (ALUMODEREG) + 0, 1 : ; + default : begin + $display("Attribute Syntax Error : The attribute ALUMODEREG on DSP48E1 instance %m is set to %d. Legal values for this attribute are 0, 1.", ALUMODEREG); + $finish; + end + endcase + + //-------- AREG check + + case (AREG) + 0, 1, 2 : ; + default : begin + $display("Attribute Syntax Error : The attribute AREG on DSP48E1 instance %m is set to %d. Legal values for this attribute are 0, 1 or 2.", AREG); + $finish; + end + endcase + + //-------- (ACASCREG) and (ACASCREG vs AREG) check + + case (AREG) + 0 : if(AREG != ACASCREG) begin + $display("Attribute Syntax Error : The attribute ACASCREG on DSP48E1 instance %m is set to %d. ACASCREG has to be set to 0 when attribute AREG = 0.", ACASCREG); + $finish; + end + 1 : if(AREG != ACASCREG) begin + $display("Attribute Syntax Error : The attribute ACASCREG on DSP48E1 instance %m is set to %d. ACASCREG has to be set to 1 when attribute AREG = 1.", ACASCREG); + $finish; + end + 2 : if((AREG != ACASCREG) && ((AREG-1) != ACASCREG)) begin + $display("Attribute Syntax Error : The attribute ACASCREG on DSP48E1 instance %m is set to %d. ACASCREG has to be set to either 2 or 1 when attribute AREG = 2.", ACASCREG); + $finish; + end + default : ; + endcase + + //-------- B_INPUT check + + case (B_INPUT) + "DIRECT", "CASCADE" : ; + default : begin + $display("Attribute Syntax Error : The attribute B_INPUT on DSP48E1 instance %m is set to %s. Legal values for this attribute are DIRECT or CASCADE.", B_INPUT); + $finish; + end + endcase + + + //-------- BREG check + + case (BREG) + 0, 1, 2 : ; + default : begin + $display("Attribute Syntax Error : The attribute BREG on DSP48E1 instance %m is set to %d. Legal values for this attribute are 0, 1 or 2.", BREG); + $finish; + end + endcase + + //-------- (BCASCREG) and (BCASCREG vs BREG) check + + case (BREG) + 0 : if(BREG != BCASCREG) begin + $display("Attribute Syntax Error : The attribute BCASCREG on DSP48E1 instance %m is set to %d. BCASCREG has to be set to 0 when attribute BREG = 0.", BCASCREG); + $finish; + end + 1 : if(BREG != BCASCREG) begin + $display("Attribute Syntax Error : The attribute BCASCREG on DSP48E1 instance %m is set to %d. BCASCREG has to be set to 1 when attribute BREG = 1.", BCASCREG); + $finish; + end + 2 : if((BREG != BCASCREG) && ((BREG-1) != BCASCREG)) begin + $display("Attribute Syntax Error : The attribute BCASCREG on DSP48E1 instance %m is set to %d. BCASCREG has to be set to either 2 or 1 when attribute BREG = 2.", BCASCREG); + $finish; + end + default : ; + endcase + + //-------- CARRYINREG check + + case (CARRYINREG) + 0, 1 : ; + default : begin + $display("Attribute Syntax Error : The attribute CARRYINREG on DSP48E1 instance %m is set to %d. Legal values for this attribute are 0, 1.", CARRYINREG); + $finish; + end + endcase + + //-------- CARRYINSELREG check + + case (CARRYINSELREG) + 0, 1 : ; + default : begin + $display("Attribute Syntax Error : The attribute CARRYINSELREG on DSP48E1 instance %m is set to %d. Legal values for this attribute are 0, 1.", CARRYINSELREG); + $finish; + end + endcase + + //-------- CREG check + + case (CREG) + 0, 1 : ; + default : begin + $display("Attribute Syntax Error : The attribute CREG on DSP48E1 instance %m is set to %d. Legal values for this attribute are 0, or 1.", CREG); + $finish; + end + endcase + + + //-------- OPMODEREG check + + case (OPMODEREG) + 0, 1 : ; + default : begin + $display("Attribute Syntax Error : The attribute OPMODEREG on DSP48E1 instance %m is set to %d. Legal values for this attribute are 0, 1.", OPMODEREG); + $finish; + end + endcase + + //-------- USE_MULT + + case (USE_MULT) + "NONE", "MULTIPLY", "DYNAMIC" : ; + default : begin + $display("Attribute Syntax Error : The attribute USE_MULT on DSP48E1 instance %m is set to %s. Legal values for this attribute are MULTIPLY, DYNAMIC or NONE.", USE_MULT); + $finish; + end +/* + "MULT" : if (MREG != 0) begin + $display("Attribute Syntax Error : The attribute USE_MULT on DSP48E1 instance %m is set to %s. This requires attribute MREG to be set to 0.", USE_MULT); + $finish; + end + "MULT_S" : if (MREG != 1) begin + $display("Attribute Syntax Error : The attribute USE_MULT on DSP48E1 instance %m is set to %s. This requires attribute MREG to be set to 1.", USE_MULT); + $finish; + end + default : begin + $display("Attribute Syntax Error : The attribute USE_MULT on DSP48E1 instance %m is set to %s. Legal values for this attribute are NONE, MULT or MULT_S.", USE_MULT); + $finish; + end +*/ + endcase + + //-------- USE_PATTERN_DETECT + + case (USE_PATTERN_DETECT) + "PATDET", "NO_PATDET" : ; + default : begin + $display("Attribute Syntax Error : The attribute USE_PATTERN_DETECT on DSP48E1 instance %m is set to %s. Legal values for this attribute are PATDET or NO_PATDET.", USE_PATTERN_DETECT); + $finish; + end + endcase + + //-------- AUTORESET_PATDET check + + case (AUTORESET_PATDET) + "NO_RESET", "RESET_MATCH", "RESET_NOT_MATCH" : ; + default : begin + $display("Attribute Syntax Error : The attribute AUTORESET_PATDET on DSP48E1 instance %m is set to %s. Legal values for this attribute are NO_RESET or RESET_MATCH or RESET_NOT_MATCH.", AUTORESET_PATDET); + $finish; + end + endcase + + //-------- SEL_PATTERN check + + case(SEL_PATTERN) + "PATTERN", "C" : ; + default : begin + $display("Attribute Syntax Error : The attribute SEL_PATTERN on DSP48E1 instance %m is set to %s. Legal values for this attribute are PATTERN or C.", SEL_PATTERN); + $finish; + end + endcase + + //-------- SEL_MASK check + + case(SEL_MASK) + "MASK", "C", "ROUNDING_MODE1", "ROUNDING_MODE2" : ; + default : begin + $display("Attribute Syntax Error : The attribute SEL_MASK on DSP48E1 instance %m is set to %s. Legal values for this attribute are MASK or C or ROUNDING_MODE1 or ROUNDING_MODE2.", SEL_MASK); + $finish; + end + endcase + + //-------- MREG check + + case (MREG) + 0, 1 : ; + default : begin + $display("Attribute Syntax Error : The attribute MREG on DSP48E1 instance %m is set to %d. Legal values for this attribute are 0, 1.", MREG); + $finish; + end + endcase + + + //-------- PREG check + + case (PREG) + 0, 1 : ; + default : begin + $display("Attribute Syntax Error : The attribute PREG on DSP48E1 instance %m is set to %d. Legal values for this attribute are 0, 1.", PREG); + $finish; + end + endcase + + + #100010 ping_opmode_drc_check <= 1; + + +//********************************************************* +//*** ADDITIONAL DRC +//********************************************************* +// CR 219407 -- (1) +// old ask vicv +/* + if((AUTORESET_PATTERN_DETECT == "TRUE") && (USE_PATTERN_DETECT == "NO_PATDET")) begin + $display("Attribute Syntax Error : The attribute USE_PATTERN_DETECT on DSP48E1 instance %m must be set to PATDET in order to use AUTORESET_PATTERN_DETECT equals TRUE. Failure to do so could make timing reports inaccurate. "); + end +*/ +//********************************************************* +//*** new attribute DRC +//********************************************************* + + //-------- ADREG check + + case (ADREG) + 0, 1 : ; + default : begin + $display("Attribute Syntax Error : The attribute ADREG on DSP48E1 instance %m is set to %d. Legal values for this attribute are 0, 1.", ADREG); + $finish; + end + endcase + + //-------- DREG check + + case (DREG) + 0, 1 : ; + default : begin + $display("Attribute Syntax Error : The attribute DREG on DSP48E1 instance %m is set to %d. Legal values for this attribute are 0, 1.", DREG); + $finish; + end + endcase + + //-------- INMODEREG check + + case (INMODEREG) + 0, 1 : ; + default : begin + $display("Attribute Syntax Error : The attribute INMODEREG on DSP48E1 instance %m is set to %d. Legal values for this attribute are 0, 1.", INMODEREG); + $finish; + end + endcase + + //-------- USE_DPORT + + case (USE_DPORT) + "TRUE", "FALSE" : ; + default : begin + $display("Attribute Syntax Error : The attribute USE_DPORT on DSP48E1 instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", USE_DPORT); + $finish; + end + endcase + // New Additional DRCs for Power Saving -- Warning Only + + //------------- USE_DPORT + + if(((DREG == 1) || (ADREG == 1 )) && (USE_DPORT == "FALSE")) + $display("DRC Warning : Since D port is not used, please set DREG and ADREG to 0 to save power"); + + + //------------- USE_MULT + + if(((DREG == 1) || (ADREG == 1 )) && (USE_MULT == "NONE")) + $display("DRC Warning : Since Multiplier is not used, please set DREG and ADREG to 0 to save power"); + + if((MREG == 1) && (USE_MULT == "NONE")) + $display("DRC Warning : Since Multiplier is not used, please set MREG to 0 to save power"); + + end + + +//********************************************************* +//********** INMODE signal registering ************ +//********************************************************* +// new + always @(posedge CLK) begin + if (RSTINMODE) + qinmode_o_reg <= 5'b0; + else if (CEINMODE) + qinmode_o_reg <= INMODE; + end + + generate + case (INMODEREG) + 0: begin + always @(INMODE) + qinmode_o_mux <= INMODE; + end + + 1: begin + always @(qinmode_o_reg) + qinmode_o_mux <= qinmode_o_reg; + end + endcase + endgenerate + +//********************************************************* +//*** Input register A with 2 level deep of registers +//********************************************************* + + generate + case (A_INPUT) + "DIRECT" : always @(A) a_o_mux <= A; + "CASCADE" : always @(ACIN) a_o_mux <= ACIN; + endcase + endgenerate + + generate + case (AREG) + 1 : begin + always @(posedge CLK) begin + if (RSTA) begin + qa_o_reg1 <= 30'b0; + qa_o_reg2 <= 30'b0; + end + else begin + if (CEA1) + qa_o_reg1 <= a_o_mux; + if (CEA2) + qa_o_reg2 <= a_o_mux; + end + end + end + + 2 : begin + always @(posedge CLK) begin + if (RSTA) begin + qa_o_reg1 <= 30'b0; + qa_o_reg2 <= 30'b0; + end + else begin + if (CEA1) + qa_o_reg1 <= a_o_mux; + if (CEA2) + qa_o_reg2 <= qa_o_reg1; + end + end + end + endcase + endgenerate + + generate + case (AREG) + 0: always @(a_o_mux) qa_o_mux <= a_o_mux; + 1,2 : always @(qa_o_reg2) qa_o_mux <= qa_o_reg2; + endcase + endgenerate + + generate + case (ACASCREG) + 1: always @(qa_o_mux or qa_o_reg1) begin + if(AREG == 2) + qacout_o_mux <= qa_o_reg1; + else + qacout_o_mux <= qa_o_mux; + end + 0,2 : always @(qa_o_mux) qacout_o_mux <= qa_o_mux; + endcase + endgenerate + +// new + + assign a_preaddsub = qinmode_o_mux[1]? 25'b0:(qinmode_o_mux[0]?qa_o_reg1[24:0]:qa_o_mux[24:0]); + +//********************************************************* +//*** Input register B with 2 level deep of registers +//********************************************************* + + generate + case (B_INPUT) + "DIRECT" : always @(B) b_o_mux <= B; + "CASCADE" : always @(BCIN) b_o_mux <= BCIN; + endcase + endgenerate + + generate + case (BREG) + 1 : begin + always @(posedge CLK) begin + if (RSTB) begin + qb_o_reg1 <= 18'b0; + qb_o_reg2 <= 18'b0; + end + else begin + if (CEB1) + qb_o_reg1 <= b_o_mux; + if (CEB2) + qb_o_reg2 <= b_o_mux; + end + end + end + + 2 : begin + always @(posedge CLK) begin + if (RSTB) begin + qb_o_reg1 <= 18'b0; + qb_o_reg2 <= 18'b0; + end + else begin + if (CEB1) + qb_o_reg1 <= b_o_mux; + if (CEB2) + qb_o_reg2 <= qb_o_reg1; + end + end + end + endcase + endgenerate + + generate + case (BREG) + 0: always @(b_o_mux) qb_o_mux <= b_o_mux; + 1,2 : always @(qb_o_reg2) qb_o_mux <= qb_o_reg2; + endcase + endgenerate + + generate + case (BCASCREG) + 1: always @(qb_o_mux or qb_o_reg1) begin + if(BREG == 2) + qbcout_o_mux <= qb_o_reg1; + else + qbcout_o_mux <= qb_o_mux; + end + 0,2 : always @(qb_o_mux) qbcout_o_mux <= qb_o_mux; + endcase + endgenerate + + +// new + + assign b_mult = qinmode_o_mux[4]?qb_o_reg1:qb_o_mux; + +//********************************************************* +//*** Input register C with 1 level deep of register +//********************************************************* + + always @(posedge CLK) begin + if (RSTC) + qc_o_reg1 <= 48'b0; + else if (CEC) + qc_o_reg1 <= C; + end + + + generate + case (CREG) + 0 : always @(C) qc_o_mux <= C; + 1 : always @(qc_o_reg1) qc_o_mux <= qc_o_reg1; + endcase + endgenerate + + +// new + +//********************************************************* +//*** Input register D with 1 level deep of register +//********************************************************* + always @(posedge CLK) begin + if (RSTD) + qd_o_reg1 <= 25'b0; + else if (CED) + qd_o_reg1 <= D; + end + + generate + case (DREG) + 0 : always @(D) qd_o_mux <= D; + 1 : always @(qd_o_reg1) qd_o_mux <= qd_o_reg1; + endcase + endgenerate + + + + +//********************************************************* +//*** Preaddsub AD register with 1 level deep of register +//********************************************************* +// new + assign ad_addsub = qinmode_o_mux[3]?(-a_preaddsub + (qinmode_o_mux[2]?qd_o_mux:25'b0)):(a_preaddsub + (qinmode_o_mux[2]?qd_o_mux:25'b0)); + + always @(posedge CLK) begin + if (RSTD) + qad_o_reg1 <= 25'b0; + else if (CEAD) + qad_o_reg1 <= ad_addsub; + end + + generate + case (ADREG) + 0 : always @(ad_addsub) qad_o_mux <= ad_addsub; + 1 : always @(qad_o_reg1) qad_o_mux <= qad_o_reg1; + endcase + endgenerate + +/*------------------------------------------------- */ +/*------------------------------------------------- */ + + assign ad_mult = (USE_DPORT=="TRUE")? qad_o_mux : a_preaddsub; +//********************************************************* + +//********************************************************* +//*************** 25x18 Multiplier *************** +//********************************************************* +// 05/26/05 -- FP -- Added warning for invalid mult when USE_MULT=NONE +// SIMD=FOUR12 and SIMD=TWO24 +// Made mult_o to be "X" + + always @(qopmode_o_mux) begin + if(qopmode_o_mux[3:0] == 4'b0101) + if((USE_MULT == "NONE") || (USE_SIMD == "TWO24") || (USE_SIMD == "FOUR12")) + $display("OPMODE Input Warning : The OPMODE[3:0] %b to DSP48E1 instance %m is invalid when using attributes USE_MULT = NONE, or USE_SIMD = TWO24 or FOUR12 at %.3f ns.", qopmode_o_mux[3:0], $time/1000.0); + end + + assign mult_o = ((USE_MULT == "NONE") || (USE_SIMD == "TWO24") || (USE_SIMD == "FOUR12"))? 43'b0 : {{18{ad_mult[24]}}, ad_mult[24:0]} * {{25{b_mult[17]}}, b_mult}; + + always @(posedge CLK) begin + if (RSTM) begin + qmult_o_reg <= 18'b0; + end + else if (CEM) begin + qmult_o_reg <= mult_o; + end + end + + generate + case (MREG) + 0 : always @(mult_o) qmult_o_mux <= mult_o; + 1 : always @(qmult_o_reg) qmult_o_mux <= qmult_o_reg; + endcase + endgenerate + + +//*** X mux +// ask jmt + + always @(qp_o_mux or qa_o_mux or qb_o_mux or qmult_o_mux or qopmode_o_mux[1:0] or qcarryinsel_o_mux) begin + case (qopmode_o_mux[1:0]) + 2'b00 : qx_o_mux <= 48'b0; + 2'b01 : qx_o_mux <= {{5{qmult_o_mux[MSB_A_MULT + MSB_B_MULT + 1]}}, qmult_o_mux}; + 2'b10 : qx_o_mux <= qp_o_mux; +// new DRC + 2'b11 : begin + if((USE_MULT == "MULTIPLY") && ( + (AREG==0 && BREG==0 && MREG==0) || + (AREG==0 && BREG==0 && PREG==0) || + (MREG==0 && PREG==0))) + $display("OPMODE Input Warning : The OPMODE[1:0] %b to DSP48E1 instance %m is invalid when using attributes USE_MULT = MULTIPLY at %.3f ns. Please set USE_MULT to either NONE or DYNAMIC.", qopmode_o_mux[1:0], $time/1000.0); + else + qx_o_mux <= {qa_o_mux[MSB_A:0], qb_o_mux[MSB_B:0]}; + end + + default : begin + end + endcase + end + + +//*** Y mux + +// 08-06-08 +// IR 478378 + wire [47:0] y_mac_cascd = (qopmode_o_mux[6:4] == 3'b100) ? {48{MULTSIGNIN}} : {48{1'b1}}; + + always @(qc_o_mux or qopmode_o_mux[3:2] or qcarryinsel_o_mux or y_mac_cascd) begin + case (qopmode_o_mux[3:2]) + 2'b00 : qy_o_mux <= 48'b0; + 2'b01 : qy_o_mux <= 48'b0; +// 08-06-08 + 2'b10 : qy_o_mux <= y_mac_cascd; // choose all ones or mult-sign-extend + 2'b11 : qy_o_mux <= qc_o_mux; + default : begin + end + endcase + end + + +//*** Z mux + + always @(qp_o_mux or qc_o_mux or PCIN or qopmode_o_mux[6:4] or qcarryinsel_o_mux) begin +// ask jmt + casex (qopmode_o_mux[6:4]) + 3'b000 : qz_o_mux <= 48'b0; + 3'b001 : qz_o_mux <= PCIN; + 3'b010 : qz_o_mux <= qp_o_mux; + 3'b011 : qz_o_mux <= qc_o_mux; + 3'b100 : qz_o_mux <= qp_o_mux; + 3'b101 : qz_o_mux <= {{17{PCIN[47]}}, PCIN[47:17]}; +// ask jmt + 3'b11x : qz_o_mux <= {{17{qp_o_mux[47]}}, qp_o_mux[47:17]}; + default : begin + end + endcase + end + + + +//*** CarryInSel and OpMode with 1 level of register + always @(posedge CLK) begin + if (RSTCTRL) begin + qcarryinsel_o_reg1 <= 3'b0; + qopmode_o_reg1 <= 7'b0; + end + else if (CECTRL) begin + qcarryinsel_o_reg1 <= CARRYINSEL; + qopmode_o_reg1 <= OPMODE; + end + end + + generate + case (CARRYINSELREG) + 0 : always @(CARRYINSEL) qcarryinsel_o_mux <= CARRYINSEL; + 1 : always @(qcarryinsel_o_reg1) qcarryinsel_o_mux <= qcarryinsel_o_reg1; + endcase + endgenerate + + +//CR 219047 (3) + +// always @(qcarryinsel_o_mux or MULTSIGNIN or qopmode_o_mux) begin +// always @(CARRYCASCIN or MULTSIGNIN or qopmode_o_mux) begin + always @(qcarryinsel_o_mux or CARRYCASCIN or MULTSIGNIN or qopmode_o_mux) begin + if(qcarryinsel_o_mux == 3'b010) begin + if(!((MULTSIGNIN === 1'bx) || ((qopmode_o_mux == 7'b1001000) && !(MULTSIGNIN === 1'bx)) + || ((MULTSIGNIN == 1'b0) && (CARRYCASCIN == 1'b0)))) begin + $display("DRC warning : CARRYCASCIN can only be used in the current DSP48E1 instance %m if the previous DSP48E1 is performing a two input ADD operation, or the current DSP48E1 is configured in the MAC extend opmode 7'b1001000 at %.3f ns.", $time); + end + end + end +/* +// old +// ask jmt +//CR 219047 (4) + always @(qcarryinsel_o_mux) begin + if((qcarryinsel_o_mux == 3'b110) && (MULTCARRYINREG != MREG)) begin + $display("Attribute Syntax Warning : It is recommended that MREG and MULTCARRYINREG on DSP48E1 instance %m be set to the same value when using CARRYINSEL = 110 for multiply rounding."); + end + end +*/ + + generate + case (OPMODEREG) + 0 : always @(OPMODE) qopmode_o_mux <= OPMODE; + 1 : always @(qopmode_o_reg1) qopmode_o_mux <= qopmode_o_reg1; + endcase + endgenerate + + +//*** ALUMODE with 1 level of register + always @(posedge CLK) begin + if (RSTALUMODE) + qalumode_o_reg1 <= 4'b0; + else if (CEALUMODE) + qalumode_o_reg1 <= ALUMODE; + end + + + generate + case (ALUMODEREG) + 0 : always @(ALUMODE) qalumode_o_mux <= ALUMODE; + 1 : always @(qalumode_o_reg1) qalumode_o_mux <= qalumode_o_reg1; + endcase + endgenerate + +//------------------------------------------------------------------ +//*** DRC for OPMODE +//------------------------------------------------------------------ + + task deassign_xyz_mux; + begin + opmode_valid_flag = 1; + invalid_opmode = 1; // reset invalid opmode + end + endtask // deassign_xyz_mux + + + task display_invalid_opmode; + begin + if (invalid_opmode) begin + opmode_valid_flag = 0; + invalid_opmode = 0; + $display("OPMODE Input Warning : The OPMODE %b to DSP48E1 instance %m at %.3f ns requires attribute PREG set to 1.", qopmode_o_mux, $time/1000.0); + end + end + endtask // display_invalid_opmode + + always @(ping_opmode_drc_check or qalumode_o_mux or qopmode_o_mux or qcarryinsel_o_mux ) begin + + if ($time > 100000) begin // no check at first 100ns + case (qalumode_o_mux[3:2]) + 2'b00 : + //-- ARITHMETIC MODES DRC + case ({qopmode_o_mux, qcarryinsel_o_mux}) + 10'b0000000000 : deassign_xyz_mux; + 10'b0000010000 : if (PREG != 1) display_invalid_opmode; else deassign_xyz_mux; + 10'b0000010010 : if (PREG != 1) display_invalid_opmode; else deassign_xyz_mux; + 10'b0000011000 : deassign_xyz_mux; + 10'b0000011010 : deassign_xyz_mux; + 10'b0000011100 : deassign_xyz_mux; + 10'b0000101000 : deassign_xyz_mux; + 10'b0001000000 : deassign_xyz_mux; + 10'b0001010000 : if (PREG != 1) display_invalid_opmode; else deassign_xyz_mux; + 10'b0001010010 : if (PREG != 1) display_invalid_opmode; else deassign_xyz_mux; + 10'b0001011000 : deassign_xyz_mux; + 10'b0001011010 : deassign_xyz_mux; + 10'b0001011100 : deassign_xyz_mux; + 10'b0001100000 : deassign_xyz_mux; + 10'b0001100010 : deassign_xyz_mux; + 10'b0001100100 : deassign_xyz_mux; + 10'b0001110000 : if (PREG != 1) display_invalid_opmode; else deassign_xyz_mux; + 10'b0001110010 : if (PREG != 1) display_invalid_opmode; else deassign_xyz_mux; + 10'b0001110101 : if (PREG != 1) display_invalid_opmode; else deassign_xyz_mux; + 10'b0001110111 : if (PREG != 1) display_invalid_opmode; else deassign_xyz_mux; + 10'b0001111000 : deassign_xyz_mux; + 10'b0001111010 : deassign_xyz_mux; + 10'b0001111100 : deassign_xyz_mux; + 10'b0010000000 : deassign_xyz_mux; + 10'b0010010000 : if (PREG != 1) display_invalid_opmode; else deassign_xyz_mux; + 10'b0010010101 : if (PREG != 1) display_invalid_opmode; else deassign_xyz_mux; + 10'b0010010111 : if (PREG != 1) display_invalid_opmode; else deassign_xyz_mux; + 10'b0010011000 : deassign_xyz_mux; + 10'b0010011001 : deassign_xyz_mux; + 10'b0010011011 : deassign_xyz_mux; + 10'b0010101000 : deassign_xyz_mux; + 10'b0010101001 : deassign_xyz_mux; + 10'b0010101011 : deassign_xyz_mux; + 10'b0010101110 : deassign_xyz_mux; + 10'b0011000000 : deassign_xyz_mux; + 10'b0011010000 : if (PREG != 1) display_invalid_opmode; else deassign_xyz_mux; + 10'b0011010101 : if (PREG != 1) display_invalid_opmode; else deassign_xyz_mux; + 10'b0011010111 : if (PREG != 1) display_invalid_opmode; else deassign_xyz_mux; + 10'b0011011000 : deassign_xyz_mux; + 10'b0011011001 : deassign_xyz_mux; + 10'b0011011011 : deassign_xyz_mux; + 10'b0011100000 : deassign_xyz_mux; + 10'b0011100001 : deassign_xyz_mux; + 10'b0011100011 : deassign_xyz_mux; + 10'b0011110000 : if (PREG != 1) display_invalid_opmode; else deassign_xyz_mux; + 10'b0011110101 : if (PREG != 1) display_invalid_opmode; else deassign_xyz_mux; + 10'b0011110111 : if (PREG != 1) display_invalid_opmode; else deassign_xyz_mux; + 10'b0011110001 : if (PREG != 1) display_invalid_opmode; else deassign_xyz_mux; + 10'b0011110011 : if (PREG != 1) display_invalid_opmode; else deassign_xyz_mux; + 10'b0011111000 : deassign_xyz_mux; + 10'b0011111001 : deassign_xyz_mux; + 10'b0011111011 : deassign_xyz_mux; + 10'b0100000000 : if (PREG != 1) display_invalid_opmode; else deassign_xyz_mux; + 10'b0100000010 : if (PREG != 1) display_invalid_opmode; else deassign_xyz_mux; + 10'b0100010000 : if (PREG != 1) display_invalid_opmode; else deassign_xyz_mux; + 10'b0100010010 : if (PREG != 1) display_invalid_opmode; else deassign_xyz_mux; + 10'b0100011000 : if (PREG != 1) display_invalid_opmode; else deassign_xyz_mux; + 10'b0100011010 : if (PREG != 1) display_invalid_opmode; else deassign_xyz_mux; + 10'b0100011101 : if (PREG != 1) display_invalid_opmode; else deassign_xyz_mux; + 10'b0100011111 : if (PREG != 1) display_invalid_opmode; else deassign_xyz_mux; + 10'b0100101000 : if (PREG != 1) display_invalid_opmode; else deassign_xyz_mux; + 10'b0100101101 : if (PREG != 1) display_invalid_opmode; else deassign_xyz_mux; + 10'b0100101111 : if (PREG != 1) display_invalid_opmode; else deassign_xyz_mux; + 10'b0101000000 : if (PREG != 1) display_invalid_opmode; else deassign_xyz_mux; + 10'b0101000010 : if (PREG != 1) display_invalid_opmode; else deassign_xyz_mux; + 10'b0101010000 : if (PREG != 1) display_invalid_opmode; else deassign_xyz_mux; + 10'b0101011000 : if (PREG != 1) display_invalid_opmode; else deassign_xyz_mux; + 10'b0101011101 : if (PREG != 1) display_invalid_opmode; else deassign_xyz_mux; + 10'b0101011111 : if (PREG != 1) display_invalid_opmode; else deassign_xyz_mux; + 10'b0101100000 : if (PREG != 1) display_invalid_opmode; else deassign_xyz_mux; + 10'b0101100010 : if (PREG != 1) display_invalid_opmode; else deassign_xyz_mux; + 10'b0101100101 : if (PREG != 1) display_invalid_opmode; else deassign_xyz_mux; + 10'b0101100111 : if (PREG != 1) display_invalid_opmode; else deassign_xyz_mux; + 10'b0101110000 : if (PREG != 1) display_invalid_opmode; else deassign_xyz_mux; + 10'b0101110101 : if (PREG != 1) display_invalid_opmode; else deassign_xyz_mux; + 10'b0101110111 : if (PREG != 1) display_invalid_opmode; else deassign_xyz_mux; + 10'b0101111000 : if (PREG != 1) display_invalid_opmode; else deassign_xyz_mux; + 10'b0101111101 : if (PREG != 1) display_invalid_opmode; else deassign_xyz_mux; + 10'b0101111111 : if (PREG != 1) display_invalid_opmode; else deassign_xyz_mux; + 10'b0110000000 : deassign_xyz_mux; + 10'b0110000010 : deassign_xyz_mux; + 10'b0110000100 : deassign_xyz_mux; + 10'b0110010000 : if (PREG != 1) display_invalid_opmode; else deassign_xyz_mux; + 10'b0110010010 : if (PREG != 1) display_invalid_opmode; else deassign_xyz_mux; + 10'b0110010101 : if (PREG != 1) display_invalid_opmode; else deassign_xyz_mux; + 10'b0110010111 : if (PREG != 1) display_invalid_opmode; else deassign_xyz_mux; + 10'b0110011000 : deassign_xyz_mux; + 10'b0110011010 : deassign_xyz_mux; + 10'b0110011100 : deassign_xyz_mux; + 10'b0110101000 : deassign_xyz_mux; + 10'b0110101110 : deassign_xyz_mux; + 10'b0111000000 : deassign_xyz_mux; + 10'b0111000010 : deassign_xyz_mux; + 10'b0111000100 : deassign_xyz_mux; + 10'b0111010000 : if (PREG != 1) display_invalid_opmode; else deassign_xyz_mux; + 10'b0111010101 : if (PREG != 1) display_invalid_opmode; else deassign_xyz_mux; + 10'b0111010111 : if (PREG != 1) display_invalid_opmode; else deassign_xyz_mux; + 10'b0111011000 : deassign_xyz_mux; + 10'b0111100000 : deassign_xyz_mux; + 10'b0111100010 : deassign_xyz_mux; + 10'b0111110000 : if (PREG != 1) display_invalid_opmode; else deassign_xyz_mux; + 10'b0111111000 : deassign_xyz_mux; + 10'b1001000010 : if (PREG != 1) display_invalid_opmode; else deassign_xyz_mux; + 10'b1010000000 : deassign_xyz_mux; + 10'b1010010000 : if (PREG != 1) display_invalid_opmode; else deassign_xyz_mux; + 10'b1010010101 : if (PREG != 1) display_invalid_opmode; else deassign_xyz_mux; + 10'b1010010111 : if (PREG != 1) display_invalid_opmode; else deassign_xyz_mux; + 10'b1010011000 : deassign_xyz_mux; + 10'b1010011001 : deassign_xyz_mux; + 10'b1010011011 : deassign_xyz_mux; + 10'b1010101000 : deassign_xyz_mux; + 10'b1010101001 : deassign_xyz_mux; + 10'b1010101011 : deassign_xyz_mux; + 10'b1010101110 : deassign_xyz_mux; + 10'b1011000000 : deassign_xyz_mux; + 10'b1011010000 : if (PREG != 1) display_invalid_opmode; else deassign_xyz_mux; + 10'b1011010101 : if (PREG != 1) display_invalid_opmode; else deassign_xyz_mux; + 10'b1011010111 : if (PREG != 1) display_invalid_opmode; else deassign_xyz_mux; + 10'b1011011000 : deassign_xyz_mux; + 10'b1011011001 : deassign_xyz_mux; + 10'b1011011011 : deassign_xyz_mux; + 10'b1011100000 : deassign_xyz_mux; + 10'b1011100001 : deassign_xyz_mux; + 10'b1011100011 : deassign_xyz_mux; + 10'b1011110000 : if (PREG != 1) display_invalid_opmode; else deassign_xyz_mux; + 10'b1011110101 : if (PREG != 1) display_invalid_opmode; else deassign_xyz_mux; + 10'b1011110111 : if (PREG != 1) display_invalid_opmode; else deassign_xyz_mux; + 10'b1011110001 : if (PREG != 1) display_invalid_opmode; else deassign_xyz_mux; + 10'b1011110011 : if (PREG != 1) display_invalid_opmode; else deassign_xyz_mux; + 10'b1011111000 : deassign_xyz_mux; + 10'b1011111001 : deassign_xyz_mux; + 10'b1011111011 : deassign_xyz_mux; + 10'b1100000000 : if (PREG != 1) display_invalid_opmode; else deassign_xyz_mux; + 10'b1100010000 : if (PREG != 1) display_invalid_opmode; else deassign_xyz_mux; + 10'b1100011000 : if (PREG != 1) display_invalid_opmode; else deassign_xyz_mux; + 10'b1100011101 : if (PREG != 1) display_invalid_opmode; else deassign_xyz_mux; + 10'b1100011111 : if (PREG != 1) display_invalid_opmode; else deassign_xyz_mux; + 10'b1100101000 : if (PREG != 1) display_invalid_opmode; else deassign_xyz_mux; + 10'b1100101101 : if (PREG != 1) display_invalid_opmode; else deassign_xyz_mux; + 10'b1100101111 : if (PREG != 1) display_invalid_opmode; else deassign_xyz_mux; + 10'b1101000000 : if (PREG != 1) display_invalid_opmode; else deassign_xyz_mux; + 10'b1101010000 : if (PREG != 1) display_invalid_opmode; else deassign_xyz_mux; + 10'b1101011000 : if (PREG != 1) display_invalid_opmode; else deassign_xyz_mux; + 10'b1101011101 : if (PREG != 1) display_invalid_opmode; else deassign_xyz_mux; + 10'b1101011111 : if (PREG != 1) display_invalid_opmode; else deassign_xyz_mux; + 10'b1101100000 : if (PREG != 1) display_invalid_opmode; else deassign_xyz_mux; + 10'b1101100101 : if (PREG != 1) display_invalid_opmode; else deassign_xyz_mux; + 10'b1101100111 : if (PREG != 1) display_invalid_opmode; else deassign_xyz_mux; + 10'b1101110000 : if (PREG != 1) display_invalid_opmode; else deassign_xyz_mux; + 10'b1101110101 : if (PREG != 1) display_invalid_opmode; else deassign_xyz_mux; + 10'b1101110111 : if (PREG != 1) display_invalid_opmode; else deassign_xyz_mux; + 10'b1101111000 : if (PREG != 1) display_invalid_opmode; else deassign_xyz_mux; + 10'b1101111101 : if (PREG != 1) display_invalid_opmode; else deassign_xyz_mux; + 10'b1101111111 : if (PREG != 1) display_invalid_opmode; else deassign_xyz_mux; + default : begin + if (invalid_opmode) begin + + opmode_valid_flag = 0; + invalid_opmode = 0; +// CR 444150 + if( ({qopmode_o_mux, qcarryinsel_o_mux} == 10'b0000000010) && ((OPMODEREG==1) && (CARRYINSELREG ==0)) ) + $display("DRC warning : The attribute CARRYINSELREG on DSP48E1 instance %m is set to %d. It is required to have CARRYINSELREG be set to 1 to match OPMODEREG, in order to ensure that the simulation model will match the hardware behavior in all use cases.", CARRYINSELREG); + + + + $display("OPMODE Input Warning : The OPMODE %b to DSP48E1 instance %m is either invalid or the CARRYINSEL %b for that specific OPMODE is invalid at %.3f ns. This warning may be due to a mismatch in the OPMODEREG and CARRYINSELREG attribute settings. It is recommended that OPMODEREG and CARRYINSELREG always be set to the same value. ", qopmode_o_mux, qcarryinsel_o_mux, $time/1000.0); + + end + end + + endcase // case(OPMODE) + + 2'b01, 2'b11 : + //-- LOGIC MODES DRC + case (qopmode_o_mux) + 7'b0000000 : deassign_xyz_mux; + 7'b0000010 : if (PREG != 1) display_invalid_opmode; else deassign_xyz_mux; + 7'b0000011 : deassign_xyz_mux; + 7'b0010000 : deassign_xyz_mux; + 7'b0010010 : if (PREG != 1) display_invalid_opmode; else deassign_xyz_mux; + 7'b0010011 : deassign_xyz_mux; + 7'b0100000 : if (PREG != 1) display_invalid_opmode; else deassign_xyz_mux; + 7'b0100010 : if (PREG != 1) display_invalid_opmode; else deassign_xyz_mux; + 7'b0100011 : if (PREG != 1) display_invalid_opmode; else deassign_xyz_mux; + 7'b0110000 : deassign_xyz_mux; + 7'b0110010 : if (PREG != 1) display_invalid_opmode; else deassign_xyz_mux; + 7'b0110011 : deassign_xyz_mux; + 7'b1010000 : deassign_xyz_mux; + 7'b1010010 : if (PREG != 1) display_invalid_opmode; else deassign_xyz_mux; + 7'b1010011 : deassign_xyz_mux; + 7'b1100000 : if (PREG != 1) display_invalid_opmode; else deassign_xyz_mux; + 7'b1100010 : if (PREG != 1) display_invalid_opmode; else deassign_xyz_mux; + 7'b1100011 : if (PREG != 1) display_invalid_opmode; else deassign_xyz_mux; + 7'b0001000 : deassign_xyz_mux; + 7'b0001010 : if (PREG != 1) display_invalid_opmode; else deassign_xyz_mux; + 7'b0001011 : deassign_xyz_mux; + 7'b0011000 : deassign_xyz_mux; + 7'b0011010 : if (PREG != 1) display_invalid_opmode; else deassign_xyz_mux; + 7'b0011011 : deassign_xyz_mux; + 7'b0101000 : if (PREG != 1) display_invalid_opmode; else deassign_xyz_mux; + 7'b0101010 : if (PREG != 1) display_invalid_opmode; else deassign_xyz_mux; + 7'b0101011 : if (PREG != 1) display_invalid_opmode; else deassign_xyz_mux; + 7'b0111000 : deassign_xyz_mux; + 7'b0111010 : if (PREG != 1) display_invalid_opmode; else deassign_xyz_mux; + 7'b0111011 : deassign_xyz_mux; + 7'b1011000 : deassign_xyz_mux; + 7'b1011010 : if (PREG != 1) display_invalid_opmode; else deassign_xyz_mux; + 7'b1011011 : deassign_xyz_mux; + 7'b1101000 : if (PREG != 1) display_invalid_opmode; else deassign_xyz_mux; + 7'b1101010 : if (PREG != 1) display_invalid_opmode; else deassign_xyz_mux; + 7'b1101011 : if (PREG != 1) display_invalid_opmode; else deassign_xyz_mux; + default : begin + if (invalid_opmode) begin + + opmode_valid_flag = 0; + invalid_opmode = 0; + $display("OPMODE Input Warning : The OPMODE %b to DSP48E1 instance %m is invalid for LOGIC MODES at %.3f ns.", qopmode_o_mux, $time/1000.0); + + end + end + + endcase // case(OPMODE) + + endcase // case(qalumode_o_mux) + + end // if ($time > 100000) + + end // always @ (qopmode_o_mux) + + +//--#################################################################### +//--##### ALU ##### +//--#################################################################### + + wire mult_cout = ~qp_o_mux[42]; + reg [MSB_ALU_FULL:0] co; + reg [MSB_ALU_FULL:0] s; + wire [MSB_ALU_FULL:0] comux,smux; + wire [MSB_CARRYOUT:0] carryout_o_hw; + wire [MSB_CARRYOUT:0] carryout_o; + wire tmp_carrycascout_in; + + always @ (qx_o_mux or qy_o_mux or qz_o_mux or qalumode_o_mux[0]) begin + if (qalumode_o_mux[0]) begin + co = ((qx_o_mux & qy_o_mux)|((~qz_o_mux) & qy_o_mux)|(qx_o_mux & (~qz_o_mux))); + s = (~qz_o_mux) ^ qx_o_mux ^ qy_o_mux; + end + else begin + co = ((qx_o_mux & qy_o_mux)|(qz_o_mux & qy_o_mux)|(qx_o_mux & qz_o_mux)); + s = qz_o_mux ^ qx_o_mux ^ qy_o_mux; + end + end + + assign comux = qalumode_o_mux[2] ? 0 : co; + assign smux = qalumode_o_mux[3] ? co : s; + + // FINAL ADDER + wire [12:0] s0 = {comux[10:0],qcarryin_o_mux}+smux[11:0]; + wire cout0 = (comux[11] + s0[12]); + assign carryout_o_hw[0] = (qalumode_o_mux[0] & qalumode_o_mux[1]) ? ~cout0 : cout0; + wire C1 = (USE_SIMD == "FOUR12") ? 1'b0 : s0[12]; + + wire co11_lsb = (USE_SIMD == "FOUR12") ? 1'b0 : comux[11]; + wire [12:0] s1 = {comux[22:12],co11_lsb}+smux[23:12]+C1; + wire cout1 = (comux[23] + s1[12]); + assign carryout_o_hw[1] = (qalumode_o_mux[0] & qalumode_o_mux[1]) ? ~cout1 : cout1; + wire C2 = ((USE_SIMD == "TWO24") || (USE_SIMD == "FOUR12")) ? 1'b0 : s1[12]; + + wire co23_lsb = ((USE_SIMD == "TWO24") || (USE_SIMD == "FOUR12")) ? + 1'b0 : comux[23]; + + wire [12:0] s2 = {comux[34:24],co23_lsb}+smux[35:24]+C2; + wire cout2 = (comux[35] + s2[12]); + assign carryout_o_hw[2] = (qalumode_o_mux[0] & qalumode_o_mux[1]) ? ~cout2 : cout2; + wire C3 = (USE_SIMD == "FOUR12") ? 1'b0 : s2[12]; + + wire co35_lsb = (USE_SIMD == "FOUR12") ? 1'b0 : comux[35]; + wire [13:0] s3 = {comux[47:36],co35_lsb}+smux[47:36]+C3; + wire cout3 = s3[12]; + + assign carryout_o_hw[3] = (qalumode_o_mux[0] & qalumode_o_mux[1]) ? ~cout3 : cout3; + + wire cout4 = s3[13]; +// assign carryout_o_hw[4] = (qalumode_o_mux[0] & qalumode_o_mux[1]) ? ~cout4 : cout4; + + assign alu_o = qalumode_o_mux[1] ? ~{s3[11:0],s2[11:0],s1[11:0],s0[11:0]} : + {s3[11:0],s2[11:0],s1[11:0],s0[11:0]}; + // COMPUTE CARRYCASCOUT + assign carrycascout_o = cout3; + + // COMPUTE MULTSIGNOUT + // 08-06-08 assign multsignout_o_opmode = (qopmode_o_mux[3:0] === 4'b100) ? MULTSIGNIN : ~qp_o_mux[42]; + // IR 478378 + assign multsignout_o_opmode = (qopmode_o_mux[6:4] === 3'b100) ? MULTSIGNIN : qmult_o_mux[42]; + + // CR 523600 -- "X" carryout for multiply and logic operations + assign carryout_o[3] = ((qopmode_o_mux[3:0] == 4'b0101) || (qalumode_o_mux[3:2] != 2'b00))? 1'bx : carryout_o_hw[3]; + assign carryout_o[2] = ((qopmode_o_mux[3:0] == 4'b0101) || (qalumode_o_mux[3:2] != 2'b00))? 1'bx : (USE_SIMD == "FOUR12") ? carryout_o_hw[2] : 1'bx; + assign carryout_o[1] = ((qopmode_o_mux[3:0] == 4'b0101) || (qalumode_o_mux[3:2] != 2'b00))? 1'bx : ((USE_SIMD == "TWO24") || (USE_SIMD == "FOUR12")) ? carryout_o_hw[1] : 1'bx; + assign carryout_o[0] = ((qopmode_o_mux[3:0] == 4'b0101) || (qalumode_o_mux[3:2] != 2'b00))? 1'bx : (USE_SIMD == "FOUR12") ? carryout_o_hw[0] : 1'bx; + +//--########################### END ALU ################################ + + +//*** CarryIn Mux and Register + +//------- input 0 + always @(posedge CLK) begin + if (RSTALLCARRYIN) + qcarryin_o_reg0 <= 1'b0; + else if (CECARRYIN) + qcarryin_o_reg0 <= CARRYIN; + end + + generate + case (CARRYINREG) + 0 : always @(CARRYIN) qcarryin_o_mux0 <= CARRYIN; + 1 : always @(qcarryin_o_reg0) qcarryin_o_mux0 <= qcarryin_o_reg0; + endcase + endgenerate + +//------- input 7 + always @(posedge CLK) begin + if (RSTALLCARRYIN) + qcarryin_o_reg7 <= 1'b0; +// old else if (CEMULTCARRYIN) +// new + else if (CEM) +// IR 478377 + qcarryin_o_reg7 <= ad_mult[24] ~^ b_mult[17]; // xnor + end + +// always @(qa_o_mux[24] or qb_o_mux[17] or qcarryin_o_reg7) begin + always @(ad_mult[24] or b_mult[17] or qcarryin_o_reg7) begin +// old case (MULTCARRYINREG) +// new + case (MREG) +// IR 478377 + 0 : qcarryin_o_mux7 <= ad_mult[24] ~^ b_mult[17]; + 1 : qcarryin_o_mux7 <= qcarryin_o_reg7; + default : begin + $display("Attribute Syntax Error : The attribute MREG on DSP48E1 instance %m is set to %d. Legal values for this attribute are 0 or 1.", MREG); + $finish; + end + endcase + end + + reg qcarryin_o_mux_tmp; + always @(qcarryin_o_mux0 or PCIN[47] or CARRYCASCIN or carrycascout_o_mux or qp_o_mux[47] or qcarryin_o_mux7 or qcarryinsel_o_mux) begin + case (qcarryinsel_o_mux) + 3'b000 : qcarryin_o_mux_tmp <= qcarryin_o_mux0; + 3'b001 : qcarryin_o_mux_tmp <= ~PCIN[47]; + 3'b010 : qcarryin_o_mux_tmp <= CARRYCASCIN; + 3'b011 : qcarryin_o_mux_tmp <= PCIN[47]; + 3'b100 : qcarryin_o_mux_tmp <= carrycascout_o_mux; + 3'b101 : qcarryin_o_mux_tmp <= ~qp_o_mux[47]; + 3'b110 : qcarryin_o_mux_tmp <= qcarryin_o_mux7; + 3'b111 : qcarryin_o_mux_tmp <= qp_o_mux[47]; + default : begin + end + endcase + end + // disable carryin when performing logic operation + always @(qcarryin_o_mux_tmp or qalumode_o_mux[3:2]) begin + qcarryin_o_mux <= (qalumode_o_mux[3] || qalumode_o_mux[2]) ? 1'b0 : qcarryin_o_mux_tmp; + end + + +//--#################################################################### +//--##### AUTORESET_PATDET ##### +//--#################################################################### + assign the_auto_reset_patdet = ((AUTORESET_PATDET == "RESET_MATCH") && pdet_o_reg1) + || + ((AUTORESET_PATDET == "RESET_NOT_MATCH") && (pdet_o_reg2 && !pdet_o_reg1)); +//--#################################################################### +//--##### CARRYOUT, CARRYCASCOUT. MULTSIGNOUT and PCOUT ###### +//--#################################################################### +//*** register with 1 level of register + always @(posedge CLK) begin + if(RSTP || the_auto_reset_patdet) + begin + carryout_o_reg <= 4'b0; + carrycascout_o_reg <= 1'b0; + qmultsignout_o_reg <= 1'b0; + qp_o_reg1 <= 48'b0; + end + else if (CEP) begin + carryout_o_reg <= carryout_o; + carrycascout_o_reg <= carrycascout_o; + qmultsignout_o_reg <= multsignout_o_opmode; + qp_o_reg1 <= alu_o; + end + end + + generate + case (PREG) + 0: begin + always @(carryout_o) + carryout_o_mux <= carryout_o; + always @(carrycascout_o) + carrycascout_o_mux <= carrycascout_o; + always @(multsignout_o_opmode) + multsignout_o_mux <= multsignout_o_opmode; + always @(alu_o) + qp_o_mux <= alu_o; + end + + 1: begin + always @(carryout_o_reg) + carryout_o_mux <= carryout_o_reg; + always @(carrycascout_o_reg) + carrycascout_o_mux <= carrycascout_o_reg; + always @(qmultsignout_o_reg) + multsignout_o_mux <= qmultsignout_o_reg; + always @(qp_o_reg1) + qp_o_mux <= qp_o_reg1; + end + endcase + endgenerate + + + +//CR 219047 (2) +// ask jmt whether i should comment this out +/* + always @(qmult_o_mux[(MSB_A_MULT+MSB_B_MULT+1)] or qopmode_o_mux[3:0]) begin + if(qopmode_o_mux[3:0] == 4'b0101) + multsignout_o_opmode = qmult_o_mux[(MSB_A_MULT+MSB_B_MULT+1)]; + else + multsignout_o_opmode = 1'bx; + end +*/ + + + +// assign carryout_x_o[4] = carryout_o_mux[4]; +// CR 510304 output X during multiply operation + + assign carryout_x_o[3] = carryout_o_mux[3]; + assign carryout_x_o[2] = (USE_SIMD == "FOUR12") ? carryout_o_mux[2] : 1'bx; + assign carryout_x_o[1] = ((USE_SIMD == "TWO24") || (USE_SIMD == "FOUR12")) ? carryout_o_mux[1] : 1'bx; + assign carryout_x_o[0] = (USE_SIMD == "FOUR12") ? carryout_o_mux[0] : 1'bx; + + +//--#################################################################### +//--##### Pattern Detector ##### +//--#################################################################### + + +// new + // selet pattern + assign the_pattern = (SEL_PATTERN == "PATTERN") ? PATTERN : qc_o_mux; + + // selet mask + always @(qc_o_mux) begin + case(SEL_MASK) + "MASK" : the_mask <= MASK; + "C" : the_mask <= qc_o_mux; + "ROUNDING_MODE1" : the_mask <= ~qc_o_mux << 1; + "ROUNDING_MODE2" : the_mask <= ~qc_o_mux << 2; + default : ; + endcase + end + + //-- now do the pattern detection + + assign pdet_o = &(~(the_pattern ^ alu_o) | the_mask); + assign pdetb_o = &((the_pattern ^ alu_o) | the_mask); + + assign pdet_o_mux = (~opmode_valid_flag) ? 1'bx : (PREG == 1) ? pdet_o_reg1 : pdet_o; + assign pdetb_o_mux = (~opmode_valid_flag) ? 1'bx : (PREG == 1) ? pdetb_o_reg1 : pdetb_o; + +//*** Output register PATTERN DETECT and UNDERFLOW / OVERFLOW + + always @(posedge CLK) begin + if((RSTP) || the_auto_reset_patdet) + begin + pdet_o_reg1 <= 1'b0; + pdet_o_reg2 <= 1'b0; + pdetb_o_reg1 <= 1'b0; + pdetb_o_reg2 <= 1'b0; + end + else if(CEP) + begin + //-- the previous values are used in Underflow/Overflow + pdet_o_reg2 <= pdet_o_reg1; + pdet_o_reg1 <= pdet_o; + pdetb_o_reg2 <= pdetb_o_reg1; + pdetb_o_reg1 <= pdetb_o; + end + end + + +//--#################################################################### +//--##### Underflow / Overflow ##### +//--#################################################################### + generate if ((USE_PATTERN_DETECT == "PATDET") || (PREG == 1)) + begin + assign overflow_o = pdet_o_reg2 & !pdet_o_reg1 & !pdetb_o_reg1; + assign underflow_o = pdetb_o_reg2 & !pdet_o_reg1 & !pdetb_o_reg1; + end + else + begin + assign overflow_o = 1'bx; + assign underflow_o = 1'bx; + end + endgenerate + + + + + assign ACOUT = qacout_o_mux; + assign BCOUT = qbcout_o_mux; + assign CARRYCASCOUT = carrycascout_o_mux; + assign CARRYOUT = carryout_x_o; + assign MULTSIGNOUT = multsignout_o_mux; + assign OVERFLOW = overflow_o; + assign P = qp_o_mux; + assign PCOUT = qp_o_mux; + assign PATTERNDETECT = pdet_o_mux; + assign PATTERNBDETECT = pdetb_o_mux; + assign UNDERFLOW = underflow_o; + specify + + (CLK *> ACOUT) = (100, 100); + (CLK *> BCOUT) = (100, 100); + (CLK *> CARRYCASCOUT) = (100, 100); + (CLK *> CARRYOUT) = (100, 100); + (CLK *> MULTSIGNOUT) = (100, 100); + (CLK *> OVERFLOW) = (100, 100); + (CLK *> P) = (100, 100); + (CLK *> PATTERNBDETECT) = (100, 100); + (CLK *> PATTERNDETECT) = (100, 100); + (CLK *> PCOUT) = (100, 100); + (CLK *> UNDERFLOW) = (100, 100); + + specparam PATHPULSE$ = 0; + + endspecify + +endmodule // DSP48E1 + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/EFUSE_USR.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/EFUSE_USR.v new file mode 100644 index 0000000..ca0e1c7 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/EFUSE_USR.v @@ -0,0 +1,32 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/blanc/EFUSE_USR.v,v 1.3 2009/08/21 23:55:39 harikr Exp $ +/////////////////////////////////////////////////////// +// Copyright (c) 2009 Xilinx Inc. +// All Right Reserved. +/////////////////////////////////////////////////////// +// +// ____ ___ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : +// / / +// /__/ /\ Filename : EFUSE_USR.v +// \ \ / \ +// \__\/\__ \ +// +// Revision: 1.0 +/////////////////////////////////////////////////////// + +`timescale 1 ps / 1 ps + +module EFUSE_USR ( + EFUSEUSR +); + + parameter [31:0] SIM_EFUSE_VALUE = 32'h00000000; + + output [31:0] EFUSEUSR; + + assign EFUSEUSR = SIM_EFUSE_VALUE; + +endmodule diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/EMAC.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/EMAC.v new file mode 100644 index 0000000..5f4f5ce --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/EMAC.v @@ -0,0 +1,663 @@ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Ethernet Media Access Controller +// /___/ /\ Filename : EMAC.v +// \ \ / \ Timestamp : Fri Jun 18 10:57:22 PDT 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 12/07/07 - CR 455025 - Added delays for 16 bit client mode. +// 02/04/08 - CR 460680 - Changed delay to 125ps. +// 09/11/08 - Fixed CR#476740. Added 10 ps delay to dcremacclk +// 01/01/09 - Fixed CR504192,3. Changed delays to 50,0 ps. + +`timescale 1 ps / 1 ps + +module EMAC ( + DCRHOSTDONEIR, + EMAC0CLIENTANINTERRUPT, + EMAC0CLIENTRXBADFRAME, + EMAC0CLIENTRXCLIENTCLKOUT, + EMAC0CLIENTRXD, + EMAC0CLIENTRXDVLD, + EMAC0CLIENTRXDVLDMSW, + EMAC0CLIENTRXDVREG6, + EMAC0CLIENTRXFRAMEDROP, + EMAC0CLIENTRXGOODFRAME, + EMAC0CLIENTRXSTATS, + EMAC0CLIENTRXSTATSBYTEVLD, + EMAC0CLIENTRXSTATSVLD, + EMAC0CLIENTTXACK, + EMAC0CLIENTTXCLIENTCLKOUT, + EMAC0CLIENTTXCOLLISION, + EMAC0CLIENTTXGMIIMIICLKOUT, + EMAC0CLIENTTXRETRANSMIT, + EMAC0CLIENTTXSTATS, + EMAC0CLIENTTXSTATSBYTEVLD, + EMAC0CLIENTTXSTATSVLD, + EMAC0PHYENCOMMAALIGN, + EMAC0PHYLOOPBACKMSB, + EMAC0PHYMCLKOUT, + EMAC0PHYMDOUT, + EMAC0PHYMDTRI, + EMAC0PHYMGTRXRESET, + EMAC0PHYMGTTXRESET, + EMAC0PHYPOWERDOWN, + EMAC0PHYSYNCACQSTATUS, + EMAC0PHYTXCHARDISPMODE, + EMAC0PHYTXCHARDISPVAL, + EMAC0PHYTXCHARISK, + EMAC0PHYTXCLK, + EMAC0PHYTXD, + EMAC0PHYTXEN, + EMAC0PHYTXER, + EMAC1CLIENTANINTERRUPT, + EMAC1CLIENTRXBADFRAME, + EMAC1CLIENTRXCLIENTCLKOUT, + EMAC1CLIENTRXD, + EMAC1CLIENTRXDVLD, + EMAC1CLIENTRXDVLDMSW, + EMAC1CLIENTRXDVREG6, + EMAC1CLIENTRXFRAMEDROP, + EMAC1CLIENTRXGOODFRAME, + EMAC1CLIENTRXSTATS, + EMAC1CLIENTRXSTATSBYTEVLD, + EMAC1CLIENTRXSTATSVLD, + EMAC1CLIENTTXACK, + EMAC1CLIENTTXCLIENTCLKOUT, + EMAC1CLIENTTXCOLLISION, + EMAC1CLIENTTXGMIIMIICLKOUT, + EMAC1CLIENTTXRETRANSMIT, + EMAC1CLIENTTXSTATS, + EMAC1CLIENTTXSTATSBYTEVLD, + EMAC1CLIENTTXSTATSVLD, + EMAC1PHYENCOMMAALIGN, + EMAC1PHYLOOPBACKMSB, + EMAC1PHYMCLKOUT, + EMAC1PHYMDOUT, + EMAC1PHYMDTRI, + EMAC1PHYMGTRXRESET, + EMAC1PHYMGTTXRESET, + EMAC1PHYPOWERDOWN, + EMAC1PHYSYNCACQSTATUS, + EMAC1PHYTXCHARDISPMODE, + EMAC1PHYTXCHARDISPVAL, + EMAC1PHYTXCHARISK, + EMAC1PHYTXCLK, + EMAC1PHYTXD, + EMAC1PHYTXEN, + EMAC1PHYTXER, + EMACDCRACK, + EMACDCRDBUS, + HOSTMIIMRDY, + HOSTRDDATA, + CLIENTEMAC0DCMLOCKED, + CLIENTEMAC0PAUSEREQ, + CLIENTEMAC0PAUSEVAL, + CLIENTEMAC0RXCLIENTCLKIN, + CLIENTEMAC0TXCLIENTCLKIN, + CLIENTEMAC0TXD, + CLIENTEMAC0TXDVLD, + CLIENTEMAC0TXDVLDMSW, + CLIENTEMAC0TXFIRSTBYTE, + CLIENTEMAC0TXGMIIMIICLKIN, + CLIENTEMAC0TXIFGDELAY, + CLIENTEMAC0TXUNDERRUN, + CLIENTEMAC1DCMLOCKED, + CLIENTEMAC1PAUSEREQ, + CLIENTEMAC1PAUSEVAL, + CLIENTEMAC1RXCLIENTCLKIN, + CLIENTEMAC1TXCLIENTCLKIN, + CLIENTEMAC1TXD, + CLIENTEMAC1TXDVLD, + CLIENTEMAC1TXDVLDMSW, + CLIENTEMAC1TXFIRSTBYTE, + CLIENTEMAC1TXGMIIMIICLKIN, + CLIENTEMAC1TXIFGDELAY, + CLIENTEMAC1TXUNDERRUN, + DCREMACABUS, + DCREMACCLK, + DCREMACDBUS, + DCREMACENABLE, + DCREMACREAD, + DCREMACWRITE, + HOSTADDR, + HOSTCLK, + HOSTEMAC1SEL, + HOSTMIIMSEL, + HOSTOPCODE, + HOSTREQ, + HOSTWRDATA, + PHYEMAC0COL, + PHYEMAC0CRS, + PHYEMAC0GTXCLK, + PHYEMAC0MCLKIN, + PHYEMAC0MDIN, + PHYEMAC0MIITXCLK, + PHYEMAC0PHYAD, + PHYEMAC0RXBUFERR, + PHYEMAC0RXBUFSTATUS, + PHYEMAC0RXCHARISCOMMA, + PHYEMAC0RXCHARISK, + PHYEMAC0RXCHECKINGCRC, + PHYEMAC0RXCLK, + PHYEMAC0RXCLKCORCNT, + PHYEMAC0RXCOMMADET, + PHYEMAC0RXD, + PHYEMAC0RXDISPERR, + PHYEMAC0RXDV, + PHYEMAC0RXER, + PHYEMAC0RXLOSSOFSYNC, + PHYEMAC0RXNOTINTABLE, + PHYEMAC0RXRUNDISP, + PHYEMAC0SIGNALDET, + PHYEMAC0TXBUFERR, + PHYEMAC1COL, + PHYEMAC1CRS, + PHYEMAC1GTXCLK, + PHYEMAC1MCLKIN, + PHYEMAC1MDIN, + PHYEMAC1MIITXCLK, + PHYEMAC1PHYAD, + PHYEMAC1RXBUFERR, + PHYEMAC1RXBUFSTATUS, + PHYEMAC1RXCHARISCOMMA, + PHYEMAC1RXCHARISK, + PHYEMAC1RXCHECKINGCRC, + PHYEMAC1RXCLK, + PHYEMAC1RXCLKCORCNT, + PHYEMAC1RXCOMMADET, + PHYEMAC1RXD, + PHYEMAC1RXDISPERR, + PHYEMAC1RXDV, + PHYEMAC1RXER, + PHYEMAC1RXLOSSOFSYNC, + PHYEMAC1RXNOTINTABLE, + PHYEMAC1RXRUNDISP, + PHYEMAC1SIGNALDET, + PHYEMAC1TXBUFERR, + RESET, + TIEEMAC0CONFIGVEC, + TIEEMAC0UNICASTADDR, + TIEEMAC1CONFIGVEC, + TIEEMAC1UNICASTADDR +); + + +output DCRHOSTDONEIR; +output EMAC0CLIENTANINTERRUPT; +output EMAC0CLIENTRXBADFRAME; +output EMAC0CLIENTRXCLIENTCLKOUT; +output EMAC0CLIENTRXDVLD; +output EMAC0CLIENTRXDVLDMSW; +output EMAC0CLIENTRXDVREG6; +output EMAC0CLIENTRXFRAMEDROP; +output EMAC0CLIENTRXGOODFRAME; +output EMAC0CLIENTRXSTATSBYTEVLD; +output EMAC0CLIENTRXSTATSVLD; +output EMAC0CLIENTTXACK; +output EMAC0CLIENTTXCLIENTCLKOUT; +output EMAC0CLIENTTXCOLLISION; +output EMAC0CLIENTTXGMIIMIICLKOUT; +output EMAC0CLIENTTXRETRANSMIT; +output EMAC0CLIENTTXSTATS; +output EMAC0CLIENTTXSTATSBYTEVLD; +output EMAC0CLIENTTXSTATSVLD; +output EMAC0PHYENCOMMAALIGN; +output EMAC0PHYLOOPBACKMSB; +output EMAC0PHYMCLKOUT; +output EMAC0PHYMDOUT; +output EMAC0PHYMDTRI; +output EMAC0PHYMGTRXRESET; +output EMAC0PHYMGTTXRESET; +output EMAC0PHYPOWERDOWN; +output EMAC0PHYSYNCACQSTATUS; +output EMAC0PHYTXCHARDISPMODE; +output EMAC0PHYTXCHARDISPVAL; +output EMAC0PHYTXCHARISK; +output EMAC0PHYTXCLK; +output EMAC0PHYTXEN; +output EMAC0PHYTXER; +output EMAC1CLIENTANINTERRUPT; +output EMAC1CLIENTRXBADFRAME; +output EMAC1CLIENTRXCLIENTCLKOUT; +output EMAC1CLIENTRXDVLD; +output EMAC1CLIENTRXDVLDMSW; +output EMAC1CLIENTRXDVREG6; +output EMAC1CLIENTRXFRAMEDROP; +output EMAC1CLIENTRXGOODFRAME; +output EMAC1CLIENTRXSTATSBYTEVLD; +output EMAC1CLIENTRXSTATSVLD; +output EMAC1CLIENTTXACK; +output EMAC1CLIENTTXCLIENTCLKOUT; +output EMAC1CLIENTTXCOLLISION; +output EMAC1CLIENTTXGMIIMIICLKOUT; +output EMAC1CLIENTTXRETRANSMIT; +output EMAC1CLIENTTXSTATS; +output EMAC1CLIENTTXSTATSBYTEVLD; +output EMAC1CLIENTTXSTATSVLD; +output EMAC1PHYENCOMMAALIGN; +output EMAC1PHYLOOPBACKMSB; +output EMAC1PHYMCLKOUT; +output EMAC1PHYMDOUT; +output EMAC1PHYMDTRI; +output EMAC1PHYMGTRXRESET; +output EMAC1PHYMGTTXRESET; +output EMAC1PHYPOWERDOWN; +output EMAC1PHYSYNCACQSTATUS; +output EMAC1PHYTXCHARDISPMODE; +output EMAC1PHYTXCHARDISPVAL; +output EMAC1PHYTXCHARISK; +output EMAC1PHYTXCLK; +output EMAC1PHYTXEN; +output EMAC1PHYTXER; +output EMACDCRACK; +output HOSTMIIMRDY; +output [0:31] EMACDCRDBUS; +output [15:0] EMAC0CLIENTRXD; +output [15:0] EMAC1CLIENTRXD; +output [31:0] HOSTRDDATA; +output [6:0] EMAC0CLIENTRXSTATS; +output [6:0] EMAC1CLIENTRXSTATS; +output [7:0] EMAC0PHYTXD; +output [7:0] EMAC1PHYTXD; + +input CLIENTEMAC0DCMLOCKED; +input CLIENTEMAC0PAUSEREQ; +input CLIENTEMAC0RXCLIENTCLKIN; +input CLIENTEMAC0TXCLIENTCLKIN; +input CLIENTEMAC0TXDVLD; +input CLIENTEMAC0TXDVLDMSW; +input CLIENTEMAC0TXFIRSTBYTE; +input CLIENTEMAC0TXGMIIMIICLKIN; +input CLIENTEMAC0TXUNDERRUN; +input CLIENTEMAC1DCMLOCKED; +input CLIENTEMAC1PAUSEREQ; +input CLIENTEMAC1RXCLIENTCLKIN; +input CLIENTEMAC1TXCLIENTCLKIN; +input CLIENTEMAC1TXDVLD; +input CLIENTEMAC1TXDVLDMSW; +input CLIENTEMAC1TXFIRSTBYTE; +input CLIENTEMAC1TXGMIIMIICLKIN; +input CLIENTEMAC1TXUNDERRUN; +input DCREMACCLK; +input DCREMACENABLE; +input DCREMACREAD; +input DCREMACWRITE; +input HOSTCLK; +input HOSTEMAC1SEL; +input HOSTMIIMSEL; +input HOSTREQ; +input PHYEMAC0COL; +input PHYEMAC0CRS; +input PHYEMAC0GTXCLK; +input PHYEMAC0MCLKIN; +input PHYEMAC0MDIN; +input PHYEMAC0MIITXCLK; +input PHYEMAC0RXBUFERR; +input PHYEMAC0RXCHARISCOMMA; +input PHYEMAC0RXCHARISK; +input PHYEMAC0RXCHECKINGCRC; +input PHYEMAC0RXCLK; +input PHYEMAC0RXCOMMADET; +input PHYEMAC0RXDISPERR; +input PHYEMAC0RXDV; +input PHYEMAC0RXER; +input PHYEMAC0RXNOTINTABLE; +input PHYEMAC0RXRUNDISP; +input PHYEMAC0SIGNALDET; +input PHYEMAC0TXBUFERR; +input PHYEMAC1COL; +input PHYEMAC1CRS; +input PHYEMAC1GTXCLK; +input PHYEMAC1MCLKIN; +input PHYEMAC1MDIN; +input PHYEMAC1MIITXCLK; +input PHYEMAC1RXBUFERR; +input PHYEMAC1RXCHARISCOMMA; +input PHYEMAC1RXCHARISK; +input PHYEMAC1RXCHECKINGCRC; +input PHYEMAC1RXCLK; +input PHYEMAC1RXCOMMADET; +input PHYEMAC1RXDISPERR; +input PHYEMAC1RXDV; +input PHYEMAC1RXER; +input PHYEMAC1RXNOTINTABLE; +input PHYEMAC1RXRUNDISP; +input PHYEMAC1SIGNALDET; +input PHYEMAC1TXBUFERR; +input RESET; +input [0:31] DCREMACDBUS; +input [15:0] CLIENTEMAC0PAUSEVAL; +input [15:0] CLIENTEMAC0TXD; +input [15:0] CLIENTEMAC1PAUSEVAL; +input [15:0] CLIENTEMAC1TXD; +input [1:0] HOSTOPCODE; +input [1:0] PHYEMAC0RXBUFSTATUS; +input [1:0] PHYEMAC0RXLOSSOFSYNC; +input [1:0] PHYEMAC1RXBUFSTATUS; +input [1:0] PHYEMAC1RXLOSSOFSYNC; +input [2:0] PHYEMAC0RXCLKCORCNT; +input [2:0] PHYEMAC1RXCLKCORCNT; +input [31:0] HOSTWRDATA; +input [47:0] TIEEMAC0UNICASTADDR; +input [47:0] TIEEMAC1UNICASTADDR; +input [4:0] PHYEMAC0PHYAD; +input [4:0] PHYEMAC1PHYAD; +input [79:0] TIEEMAC0CONFIGVEC; +input [79:0] TIEEMAC1CONFIGVEC; +input [7:0] CLIENTEMAC0TXIFGDELAY; +input [7:0] CLIENTEMAC1TXIFGDELAY; +input [7:0] PHYEMAC0RXD; +input [7:0] PHYEMAC1RXD; +input [8:9] DCREMACABUS; +input [9:0] HOSTADDR; + +reg notifier; + +// Delay wrapper for 16-bit client mode +wire PHYEMAC0MIITXCLK_delay; +wire [15:0] CLIENTEMAC0TXD_delay; +wire CLIENTEMAC0TXDVLD_delay; +wire CLIENTEMAC0TXDVLDMSW_delay; +wire PHYEMAC0MIITXCLK_skewed; +wire [15:0] CLIENTEMAC0TXD_client16_delay; +wire CLIENTEMAC0TXDVLD_client16_delay; +wire CLIENTEMAC0TXDVLDMSW_client16_delay; + +wire PHYEMAC1MIITXCLK_delay; +wire [15:0] CLIENTEMAC1TXD_delay; +wire CLIENTEMAC1TXDVLD_delay; +wire CLIENTEMAC1TXDVLDMSW_delay; +wire PHYEMAC1MIITXCLK_skewed; +wire [15:0] CLIENTEMAC1TXD_client16_delay; +wire CLIENTEMAC1TXDVLD_client16_delay; +wire CLIENTEMAC1TXDVLDMSW_client16_delay; + +localparam client_in_delay = 50; +localparam miitxclk_delay = 0; + +/*Delay EMAC# client input signals in 16-bit client mode*/ +// EMAC0 +assign #(client_in_delay) CLIENTEMAC0TXD_delay = CLIENTEMAC0TXD; +assign #(client_in_delay) CLIENTEMAC0TXDVLD_delay = CLIENTEMAC0TXDVLD; +assign #(client_in_delay) CLIENTEMAC0TXDVLDMSW_delay = CLIENTEMAC0TXDVLDMSW; + +assign CLIENTEMAC0TXD_client16_delay = (TIEEMAC0CONFIGVEC[66] == 1'b1) ? CLIENTEMAC0TXD_delay : CLIENTEMAC0TXD; // CONFIGVEC[66] is 16-bit Tx client +assign CLIENTEMAC0TXDVLD_client16_delay = (TIEEMAC0CONFIGVEC[66] == 1'b1) ? CLIENTEMAC0TXDVLD_delay : CLIENTEMAC0TXDVLD; +assign CLIENTEMAC0TXDVLDMSW_client16_delay = (TIEEMAC0CONFIGVEC[66] == 1'b1) ? CLIENTEMAC0TXDVLDMSW_delay : CLIENTEMAC0TXDVLDMSW; + +// EMAC1 +assign #(client_in_delay) CLIENTEMAC1TXD_delay = CLIENTEMAC1TXD; +assign #(client_in_delay) CLIENTEMAC1TXDVLD_delay = CLIENTEMAC1TXDVLD; +assign #(client_in_delay) CLIENTEMAC1TXDVLDMSW_delay = CLIENTEMAC1TXDVLDMSW; + +assign CLIENTEMAC1TXD_client16_delay = (TIEEMAC1CONFIGVEC[66] == 1'b1) ? CLIENTEMAC1TXD_delay : CLIENTEMAC1TXD; // CONFIGVEC[66] is 16-bit Tx client +assign CLIENTEMAC1TXDVLD_client16_delay = (TIEEMAC1CONFIGVEC[66] == 1'b1) ? CLIENTEMAC1TXDVLD_delay : CLIENTEMAC1TXDVLD; +assign CLIENTEMAC1TXDVLDMSW_client16_delay = (TIEEMAC1CONFIGVEC[66] == 1'b1) ? CLIENTEMAC1TXDVLDMSW_delay : CLIENTEMAC1TXDVLDMSW; + +/*Skew 125 MHz clock EMAC#MIITXCLK against 250 MHz clock in 16-bit client mode*/ +assign #(miitxclk_delay) PHYEMAC0MIITXCLK_delay = PHYEMAC0MIITXCLK; +assign PHYEMAC0MIITXCLK_skewed = (TIEEMAC0CONFIGVEC[66] == 1'b1) ? PHYEMAC0MIITXCLK_delay : PHYEMAC0MIITXCLK; // In TXCLIENT16 mode + +assign #(miitxclk_delay) PHYEMAC1MIITXCLK_delay = PHYEMAC1MIITXCLK; +assign PHYEMAC1MIITXCLK_skewed = (TIEEMAC1CONFIGVEC[66] == 1'b1) ? PHYEMAC1MIITXCLK_delay : PHYEMAC1MIITXCLK; // In TXCLIENT16 mode +wire dcremacclk_delay; +assign #10 dcremacclk_delay = DCREMACCLK; + +EMAC_SWIFT emac_swift_1 ( + .CLIENTEMAC0DCMLOCKED (CLIENTEMAC0DCMLOCKED), + .CLIENTEMAC0PAUSEREQ (CLIENTEMAC0PAUSEREQ), + .CLIENTEMAC0PAUSEVAL (CLIENTEMAC0PAUSEVAL), + .CLIENTEMAC0RXCLIENTCLKIN (CLIENTEMAC0RXCLIENTCLKIN), + .CLIENTEMAC0TXCLIENTCLKIN (CLIENTEMAC0TXCLIENTCLKIN), + .CLIENTEMAC0TXD (CLIENTEMAC0TXD_client16_delay), + .CLIENTEMAC0TXDVLD (CLIENTEMAC0TXDVLD_client16_delay), + .CLIENTEMAC0TXDVLDMSW (CLIENTEMAC0TXDVLDMSW_client16_delay), + .CLIENTEMAC0TXFIRSTBYTE (CLIENTEMAC0TXFIRSTBYTE), + .CLIENTEMAC0TXGMIIMIICLKIN (CLIENTEMAC0TXGMIIMIICLKIN), + .CLIENTEMAC0TXIFGDELAY (CLIENTEMAC0TXIFGDELAY), + .CLIENTEMAC0TXUNDERRUN (CLIENTEMAC0TXUNDERRUN), + .CLIENTEMAC1DCMLOCKED (CLIENTEMAC1DCMLOCKED), + .CLIENTEMAC1PAUSEREQ (CLIENTEMAC1PAUSEREQ), + .CLIENTEMAC1PAUSEVAL (CLIENTEMAC1PAUSEVAL), + .CLIENTEMAC1RXCLIENTCLKIN (CLIENTEMAC1RXCLIENTCLKIN), + .CLIENTEMAC1TXCLIENTCLKIN (CLIENTEMAC1TXCLIENTCLKIN), + .CLIENTEMAC1TXD (CLIENTEMAC1TXD_client16_delay), + .CLIENTEMAC1TXDVLD (CLIENTEMAC1TXDVLD_client16_delay), + .CLIENTEMAC1TXDVLDMSW (CLIENTEMAC1TXDVLDMSW_client16_delay), + .CLIENTEMAC1TXFIRSTBYTE (CLIENTEMAC1TXFIRSTBYTE), + .CLIENTEMAC1TXGMIIMIICLKIN (CLIENTEMAC1TXGMIIMIICLKIN), + .CLIENTEMAC1TXIFGDELAY (CLIENTEMAC1TXIFGDELAY), + .CLIENTEMAC1TXUNDERRUN (CLIENTEMAC1TXUNDERRUN), + .DCREMACABUS (DCREMACABUS), + .DCREMACCLK (dcremacclk_delay), + .DCREMACDBUS (DCREMACDBUS), + .DCREMACENABLE (DCREMACENABLE), + .DCREMACREAD (DCREMACREAD), + .DCREMACWRITE (DCREMACWRITE), + .DCRHOSTDONEIR (DCRHOSTDONEIR), + .EMAC0CLIENTANINTERRUPT (EMAC0CLIENTANINTERRUPT), + .EMAC0CLIENTRXBADFRAME (EMAC0CLIENTRXBADFRAME), + .EMAC0CLIENTRXCLIENTCLKOUT (EMAC0CLIENTRXCLIENTCLKOUT), + .EMAC0CLIENTRXD (EMAC0CLIENTRXD), + .EMAC0CLIENTRXDVLD (EMAC0CLIENTRXDVLD), + .EMAC0CLIENTRXDVLDMSW (EMAC0CLIENTRXDVLDMSW), + .EMAC0CLIENTRXDVREG6 (EMAC0CLIENTRXDVREG6), + .EMAC0CLIENTRXFRAMEDROP (EMAC0CLIENTRXFRAMEDROP), + .EMAC0CLIENTRXGOODFRAME (EMAC0CLIENTRXGOODFRAME), + .EMAC0CLIENTRXSTATS (EMAC0CLIENTRXSTATS), + .EMAC0CLIENTRXSTATSBYTEVLD (EMAC0CLIENTRXSTATSBYTEVLD), + .EMAC0CLIENTRXSTATSVLD (EMAC0CLIENTRXSTATSVLD), + .EMAC0CLIENTTXACK (EMAC0CLIENTTXACK), + .EMAC0CLIENTTXCLIENTCLKOUT (EMAC0CLIENTTXCLIENTCLKOUT), + .EMAC0CLIENTTXCOLLISION (EMAC0CLIENTTXCOLLISION), + .EMAC0CLIENTTXGMIIMIICLKOUT (EMAC0CLIENTTXGMIIMIICLKOUT), + .EMAC0CLIENTTXRETRANSMIT (EMAC0CLIENTTXRETRANSMIT), + .EMAC0CLIENTTXSTATS (EMAC0CLIENTTXSTATS), + .EMAC0CLIENTTXSTATSBYTEVLD (EMAC0CLIENTTXSTATSBYTEVLD), + .EMAC0CLIENTTXSTATSVLD (EMAC0CLIENTTXSTATSVLD), + .EMAC0PHYENCOMMAALIGN (EMAC0PHYENCOMMAALIGN), + .EMAC0PHYLOOPBACKMSB (EMAC0PHYLOOPBACKMSB), + .EMAC0PHYMCLKOUT (EMAC0PHYMCLKOUT), + .EMAC0PHYMDOUT (EMAC0PHYMDOUT), + .EMAC0PHYMDTRI (EMAC0PHYMDTRI), + .EMAC0PHYMGTRXRESET (EMAC0PHYMGTRXRESET), + .EMAC0PHYMGTTXRESET (EMAC0PHYMGTTXRESET), + .EMAC0PHYPOWERDOWN (EMAC0PHYPOWERDOWN), + .EMAC0PHYSYNCACQSTATUS (EMAC0PHYSYNCACQSTATUS), + .EMAC0PHYTXCHARDISPMODE (EMAC0PHYTXCHARDISPMODE), + .EMAC0PHYTXCHARDISPVAL (EMAC0PHYTXCHARDISPVAL), + .EMAC0PHYTXCHARISK (EMAC0PHYTXCHARISK), + .EMAC0PHYTXCLK (EMAC0PHYTXCLK), + .EMAC0PHYTXD (EMAC0PHYTXD), + .EMAC0PHYTXEN (EMAC0PHYTXEN), + .EMAC0PHYTXER (EMAC0PHYTXER), + .EMAC1CLIENTANINTERRUPT (EMAC1CLIENTANINTERRUPT), + .EMAC1CLIENTRXBADFRAME (EMAC1CLIENTRXBADFRAME), + .EMAC1CLIENTRXCLIENTCLKOUT (EMAC1CLIENTRXCLIENTCLKOUT), + .EMAC1CLIENTRXD (EMAC1CLIENTRXD), + .EMAC1CLIENTRXDVLD (EMAC1CLIENTRXDVLD), + .EMAC1CLIENTRXDVLDMSW (EMAC1CLIENTRXDVLDMSW), + .EMAC1CLIENTRXDVREG6 (EMAC1CLIENTRXDVREG6), + .EMAC1CLIENTRXFRAMEDROP (EMAC1CLIENTRXFRAMEDROP), + .EMAC1CLIENTRXGOODFRAME (EMAC1CLIENTRXGOODFRAME), + .EMAC1CLIENTRXSTATS (EMAC1CLIENTRXSTATS), + .EMAC1CLIENTRXSTATSBYTEVLD (EMAC1CLIENTRXSTATSBYTEVLD), + .EMAC1CLIENTRXSTATSVLD (EMAC1CLIENTRXSTATSVLD), + .EMAC1CLIENTTXACK (EMAC1CLIENTTXACK), + .EMAC1CLIENTTXCLIENTCLKOUT (EMAC1CLIENTTXCLIENTCLKOUT), + .EMAC1CLIENTTXCOLLISION (EMAC1CLIENTTXCOLLISION), + .EMAC1CLIENTTXGMIIMIICLKOUT (EMAC1CLIENTTXGMIIMIICLKOUT), + .EMAC1CLIENTTXRETRANSMIT (EMAC1CLIENTTXRETRANSMIT), + .EMAC1CLIENTTXSTATS (EMAC1CLIENTTXSTATS), + .EMAC1CLIENTTXSTATSBYTEVLD (EMAC1CLIENTTXSTATSBYTEVLD), + .EMAC1CLIENTTXSTATSVLD (EMAC1CLIENTTXSTATSVLD), + .EMAC1PHYENCOMMAALIGN (EMAC1PHYENCOMMAALIGN), + .EMAC1PHYLOOPBACKMSB (EMAC1PHYLOOPBACKMSB), + .EMAC1PHYMCLKOUT (EMAC1PHYMCLKOUT), + .EMAC1PHYMDOUT (EMAC1PHYMDOUT), + .EMAC1PHYMDTRI (EMAC1PHYMDTRI), + .EMAC1PHYMGTRXRESET (EMAC1PHYMGTRXRESET), + .EMAC1PHYMGTTXRESET (EMAC1PHYMGTTXRESET), + .EMAC1PHYPOWERDOWN (EMAC1PHYPOWERDOWN), + .EMAC1PHYSYNCACQSTATUS (EMAC1PHYSYNCACQSTATUS), + .EMAC1PHYTXCHARDISPMODE (EMAC1PHYTXCHARDISPMODE), + .EMAC1PHYTXCHARDISPVAL (EMAC1PHYTXCHARDISPVAL), + .EMAC1PHYTXCHARISK (EMAC1PHYTXCHARISK), + .EMAC1PHYTXCLK (EMAC1PHYTXCLK), + .EMAC1PHYTXD (EMAC1PHYTXD), + .EMAC1PHYTXEN (EMAC1PHYTXEN), + .EMAC1PHYTXER (EMAC1PHYTXER), + .EMACDCRACK (EMACDCRACK), + .EMACDCRDBUS (EMACDCRDBUS), + .HOSTADDR (HOSTADDR), + .HOSTCLK (HOSTCLK), + .HOSTEMAC1SEL (HOSTEMAC1SEL), + .HOSTMIIMRDY (HOSTMIIMRDY), + .HOSTMIIMSEL (HOSTMIIMSEL), + .HOSTOPCODE (HOSTOPCODE), + .HOSTRDDATA (HOSTRDDATA), + .HOSTREQ (HOSTREQ), + .HOSTWRDATA (HOSTWRDATA), + .PHYEMAC0COL (PHYEMAC0COL), + .PHYEMAC0CRS (PHYEMAC0CRS), + .PHYEMAC0GTXCLK (PHYEMAC0GTXCLK), + .PHYEMAC0MCLKIN (PHYEMAC0MCLKIN), + .PHYEMAC0MDIN (PHYEMAC0MDIN), + .PHYEMAC0MIITXCLK (PHYEMAC0MIITXCLK_skewed), + .PHYEMAC0PHYAD (PHYEMAC0PHYAD), + .PHYEMAC0RXBUFERR (PHYEMAC0RXBUFERR), + .PHYEMAC0RXBUFSTATUS (PHYEMAC0RXBUFSTATUS), + .PHYEMAC0RXCHARISCOMMA (PHYEMAC0RXCHARISCOMMA), + .PHYEMAC0RXCHARISK (PHYEMAC0RXCHARISK), + .PHYEMAC0RXCHECKINGCRC (PHYEMAC0RXCHECKINGCRC), + .PHYEMAC0RXCLK (PHYEMAC0RXCLK), + .PHYEMAC0RXCLKCORCNT (PHYEMAC0RXCLKCORCNT), + .PHYEMAC0RXCOMMADET (PHYEMAC0RXCOMMADET), + .PHYEMAC0RXD (PHYEMAC0RXD), + .PHYEMAC0RXDISPERR (PHYEMAC0RXDISPERR), + .PHYEMAC0RXDV (PHYEMAC0RXDV), + .PHYEMAC0RXER (PHYEMAC0RXER), + .PHYEMAC0RXLOSSOFSYNC (PHYEMAC0RXLOSSOFSYNC), + .PHYEMAC0RXNOTINTABLE (PHYEMAC0RXNOTINTABLE), + .PHYEMAC0RXRUNDISP (PHYEMAC0RXRUNDISP), + .PHYEMAC0SIGNALDET (PHYEMAC0SIGNALDET), + .PHYEMAC0TXBUFERR (PHYEMAC0TXBUFERR), + .PHYEMAC1COL (PHYEMAC1COL), + .PHYEMAC1CRS (PHYEMAC1CRS), + .PHYEMAC1GTXCLK (PHYEMAC1GTXCLK), + .PHYEMAC1MCLKIN (PHYEMAC1MCLKIN), + .PHYEMAC1MDIN (PHYEMAC1MDIN), + .PHYEMAC1MIITXCLK (PHYEMAC1MIITXCLK_skewed), + .PHYEMAC1PHYAD (PHYEMAC1PHYAD), + .PHYEMAC1RXBUFERR (PHYEMAC1RXBUFERR), + .PHYEMAC1RXBUFSTATUS (PHYEMAC1RXBUFSTATUS), + .PHYEMAC1RXCHARISCOMMA (PHYEMAC1RXCHARISCOMMA), + .PHYEMAC1RXCHARISK (PHYEMAC1RXCHARISK), + .PHYEMAC1RXCHECKINGCRC (PHYEMAC1RXCHECKINGCRC), + .PHYEMAC1RXCLK (PHYEMAC1RXCLK), + .PHYEMAC1RXCLKCORCNT (PHYEMAC1RXCLKCORCNT), + .PHYEMAC1RXCOMMADET (PHYEMAC1RXCOMMADET), + .PHYEMAC1RXD (PHYEMAC1RXD), + .PHYEMAC1RXDISPERR (PHYEMAC1RXDISPERR), + .PHYEMAC1RXDV (PHYEMAC1RXDV), + .PHYEMAC1RXER (PHYEMAC1RXER), + .PHYEMAC1RXLOSSOFSYNC (PHYEMAC1RXLOSSOFSYNC), + .PHYEMAC1RXNOTINTABLE (PHYEMAC1RXNOTINTABLE), + .PHYEMAC1RXRUNDISP (PHYEMAC1RXRUNDISP), + .PHYEMAC1SIGNALDET (PHYEMAC1SIGNALDET), + .PHYEMAC1TXBUFERR (PHYEMAC1TXBUFERR), + .RESET (RESET), + .TIEEMAC0CONFIGVEC (TIEEMAC0CONFIGVEC), + .TIEEMAC0UNICASTADDR (TIEEMAC0UNICASTADDR), + .TIEEMAC1CONFIGVEC (TIEEMAC1CONFIGVEC), + .TIEEMAC1UNICASTADDR (TIEEMAC1UNICASTADDR) +); + +specify + (CLIENTEMAC0RXCLIENTCLKIN => EMAC0CLIENTRXBADFRAME) = (100, 100); + (CLIENTEMAC0RXCLIENTCLKIN => EMAC0CLIENTRXD) = (100, 100); + (CLIENTEMAC0RXCLIENTCLKIN => EMAC0CLIENTRXDVLD) = (100, 100); + (CLIENTEMAC0RXCLIENTCLKIN => EMAC0CLIENTRXDVLDMSW) = (100, 100); + (CLIENTEMAC0RXCLIENTCLKIN => EMAC0CLIENTRXDVREG6) = (100, 100); + (CLIENTEMAC0RXCLIENTCLKIN => EMAC0CLIENTRXFRAMEDROP) = (100, 100); + (CLIENTEMAC0RXCLIENTCLKIN => EMAC0CLIENTRXGOODFRAME) = (100, 100); + (CLIENTEMAC0RXCLIENTCLKIN => EMAC0CLIENTRXSTATS) = (100, 100); + (CLIENTEMAC0RXCLIENTCLKIN => EMAC0CLIENTRXSTATSBYTEVLD) = (100, 100); + (CLIENTEMAC0RXCLIENTCLKIN => EMAC0CLIENTRXSTATSVLD) = (100, 100); + (CLIENTEMAC0TXCLIENTCLKIN => EMAC0CLIENTTXACK) = (100, 100); + (CLIENTEMAC0TXCLIENTCLKIN => EMAC0CLIENTTXCOLLISION) = (100, 100); + (CLIENTEMAC0TXCLIENTCLKIN => EMAC0CLIENTTXRETRANSMIT) = (100, 100); + (CLIENTEMAC0TXCLIENTCLKIN => EMAC0CLIENTTXSTATS) = (100, 100); + (CLIENTEMAC0TXCLIENTCLKIN => EMAC0CLIENTTXSTATSBYTEVLD) = (100, 100); + (CLIENTEMAC0TXCLIENTCLKIN => EMAC0CLIENTTXSTATSVLD) = (100, 100); + (CLIENTEMAC0TXGMIIMIICLKIN => EMAC0PHYTXD) = (100, 100); + (CLIENTEMAC0TXGMIIMIICLKIN => EMAC0PHYTXEN) = (100, 100); + (CLIENTEMAC0TXGMIIMIICLKIN => EMAC0PHYTXER) = (100, 100); + (CLIENTEMAC1RXCLIENTCLKIN => EMAC1CLIENTRXBADFRAME) = (100, 100); + (CLIENTEMAC1RXCLIENTCLKIN => EMAC1CLIENTRXD) = (100, 100); + (CLIENTEMAC1RXCLIENTCLKIN => EMAC1CLIENTRXDVLD) = (100, 100); + (CLIENTEMAC1RXCLIENTCLKIN => EMAC1CLIENTRXDVLDMSW) = (100, 100); + (CLIENTEMAC1RXCLIENTCLKIN => EMAC1CLIENTRXDVREG6) = (100, 100); + (CLIENTEMAC1RXCLIENTCLKIN => EMAC1CLIENTRXFRAMEDROP) = (100, 100); + (CLIENTEMAC1RXCLIENTCLKIN => EMAC1CLIENTRXGOODFRAME) = (100, 100); + (CLIENTEMAC1RXCLIENTCLKIN => EMAC1CLIENTRXSTATS) = (100, 100); + (CLIENTEMAC1RXCLIENTCLKIN => EMAC1CLIENTRXSTATSBYTEVLD) = (100, 100); + (CLIENTEMAC1RXCLIENTCLKIN => EMAC1CLIENTRXSTATSVLD) = (100, 100); + (CLIENTEMAC1TXCLIENTCLKIN => EMAC1CLIENTTXACK) = (100, 100); + (CLIENTEMAC1TXCLIENTCLKIN => EMAC1CLIENTTXCOLLISION) = (100, 100); + (CLIENTEMAC1TXCLIENTCLKIN => EMAC1CLIENTTXRETRANSMIT) = (100, 100); + (CLIENTEMAC1TXCLIENTCLKIN => EMAC1CLIENTTXSTATS) = (100, 100); + (CLIENTEMAC1TXCLIENTCLKIN => EMAC1CLIENTTXSTATSBYTEVLD) = (100, 100); + (CLIENTEMAC1TXCLIENTCLKIN => EMAC1CLIENTTXSTATSVLD) = (100, 100); + (CLIENTEMAC1TXGMIIMIICLKIN => EMAC1PHYTXD) = (100, 100); + (CLIENTEMAC1TXGMIIMIICLKIN => EMAC1PHYTXEN) = (100, 100); + (CLIENTEMAC1TXGMIIMIICLKIN => EMAC1PHYTXER) = (100, 100); + (HOSTCLK => EMAC0PHYMCLKOUT) = (100, 100); + (HOSTCLK => EMAC0PHYMDOUT) = (100, 100); + (HOSTCLK => EMAC0PHYMDTRI) = (100, 100); + (HOSTCLK => EMAC1PHYMCLKOUT) = (100, 100); + (HOSTCLK => EMAC1PHYMDOUT) = (100, 100); + (HOSTCLK => EMAC1PHYMDTRI) = (100, 100); + (HOSTCLK => HOSTMIIMRDY) = (100, 100); + (HOSTCLK => HOSTRDDATA) = (100, 100); + (PHYEMAC0GTXCLK => EMAC0CLIENTANINTERRUPT) = (100, 100); + (PHYEMAC0GTXCLK => EMAC0CLIENTRXCLIENTCLKOUT) = (100, 100); + (PHYEMAC0GTXCLK => EMAC0CLIENTTXCLIENTCLKOUT) = (100, 100); + (PHYEMAC0GTXCLK => EMAC0CLIENTTXGMIIMIICLKOUT) = (100, 100); + (PHYEMAC0GTXCLK => EMAC0PHYENCOMMAALIGN) = (100, 100); + (PHYEMAC0GTXCLK => EMAC0PHYLOOPBACKMSB) = (100, 100); + (PHYEMAC0GTXCLK => EMAC0PHYMGTRXRESET) = (100, 100); + (PHYEMAC0GTXCLK => EMAC0PHYMGTTXRESET) = (100, 100); + (PHYEMAC0GTXCLK => EMAC0PHYPOWERDOWN) = (100, 100); + (PHYEMAC0GTXCLK => EMAC0PHYSYNCACQSTATUS) = (100, 100); + (PHYEMAC0GTXCLK => EMAC0PHYTXCHARDISPMODE) = (100, 100); + (PHYEMAC0GTXCLK => EMAC0PHYTXCHARDISPVAL) = (100, 100); + (PHYEMAC0GTXCLK => EMAC0PHYTXCHARISK) = (100, 100); + (PHYEMAC0GTXCLK => EMAC0PHYTXCLK) = (100, 100); + (PHYEMAC1GTXCLK => EMAC1CLIENTANINTERRUPT) = (100, 100); + (PHYEMAC1GTXCLK => EMAC1CLIENTRXCLIENTCLKOUT) = (100, 100); + (PHYEMAC1GTXCLK => EMAC1CLIENTTXCLIENTCLKOUT) = (100, 100); + (PHYEMAC1GTXCLK => EMAC1CLIENTTXGMIIMIICLKOUT) = (100, 100); + (PHYEMAC1GTXCLK => EMAC1PHYENCOMMAALIGN) = (100, 100); + (PHYEMAC1GTXCLK => EMAC1PHYLOOPBACKMSB) = (100, 100); + (PHYEMAC1GTXCLK => EMAC1PHYMGTRXRESET) = (100, 100); + (PHYEMAC1GTXCLK => EMAC1PHYMGTTXRESET) = (100, 100); + (PHYEMAC1GTXCLK => EMAC1PHYPOWERDOWN) = (100, 100); + (PHYEMAC1GTXCLK => EMAC1PHYSYNCACQSTATUS) = (100, 100); + (PHYEMAC1GTXCLK => EMAC1PHYTXCHARDISPMODE) = (100, 100); + (PHYEMAC1GTXCLK => EMAC1PHYTXCHARDISPVAL) = (100, 100); + (PHYEMAC1GTXCLK => EMAC1PHYTXCHARISK) = (100, 100); + (PHYEMAC1GTXCLK => EMAC1PHYTXCLK) = (100, 100); + specparam PATHPULSE$ = 0; +endspecify +endmodule diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/FD.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/FD.v new file mode 100644 index 0000000..addb00b --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/FD.v @@ -0,0 +1,59 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/FD.v,v 1.13 2006/02/13 22:07:02 yanx Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / D Flip-Flop +// /___/ /\ Filename : FD.v +// \ \ / \ Timestamp : Thu Mar 25 16:42:16 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 02/04/05 - Rev 0.0.1 Remove input/output bufs; Seperate GSR from clock block. +// 08/09/05 - Add GSR to main block (CR 215196). +// 10/20/05 - Add set & reset check to main block. (CR219794) +// 2/07/06 - Remove set & reset from main block and add specify block (CR225119) +// 2/10/06 - Change Q from reg to net. (CR ) +// End Revision + +`timescale 1 ps / 1 ps + + +module FD (Q, C, D); + + parameter INIT = 1'b0; + + output Q; + + input C, D; + + wire Q; + reg q_out; + tri0 GSR = glbl.GSR; + + initial q_out = INIT; + + + + always @(GSR) + if (GSR) + assign q_out = INIT; + else + deassign q_out; + + always @(posedge C) + q_out <= D; + + assign Q = q_out; + + specify + (posedge C => (Q +: D)) = (100, 100); + endspecify + +endmodule diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/FDC.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/FDC.v new file mode 100644 index 0000000..ef9d290 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/FDC.v @@ -0,0 +1,61 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/FDC.v,v 1.13 2006/02/13 22:07:02 yanx Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / D Flip-Flop with Asynchronous Clear +// /___/ /\ Filename : FDC.v +// \ \ / \ Timestamp : Thu Mar 25 16:42:16 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 02/04/05 - Rev 0.0.1 Remove input/output bufs; Seperate GSR from clock block. +// 08/09/05 - Add CLR t0 GSR block (CR 215196). +// 10/20/05 - Add set & reset check to main block. (CR219794) +// 2/07/06 - Remove set & reset from main block and add specify block (CR225119) +// 2/10/06 - Change Q from reg to wire (CR 225613) +// End Revision + +`timescale 1 ps / 1 ps + + +module FDC (Q, C, CLR, D); + + parameter INIT = 1'b0; + + output Q; + + input C, CLR, D; + + wire Q; + reg q_out; + tri0 GSR = glbl.GSR; + + initial q_out = INIT; + + + always @(GSR or CLR) + if (GSR) + assign q_out = INIT; + else if (CLR) + assign q_out = 0; + else + deassign q_out; + + always @(posedge C) + q_out <= D; + + assign Q = q_out; + + specify + (posedge CLR => (Q +: 1'b0)) = (0, 0); + if (!CLR) + (posedge C => (Q +: D)) = (100, 100); + endspecify +endmodule diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/FDCE.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/FDCE.v new file mode 100644 index 0000000..e19a902 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/FDCE.v @@ -0,0 +1,63 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/FDCE.v,v 1.13 2006/02/13 22:07:02 yanx Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / D Flip-Flop with Asynchronous Clear and Clock Enable +// /___/ /\ Filename : FDCE.v +// \ \ / \ Timestamp : Thu Mar 25 16:42:16 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 02/04/05 - Rev 0.0.1 Remove input/output bufs; Seperate GSR from clock block. +// 08/09/05 - Add CLR to GSR block (CR 215196). +// 10/20/05 - Add set & reset check to main block. (CR219794) +// 2/07/06 - Remove set & reset from main block and add specify block (CR225119) +// 2/10/06 - Change Q from reg to wire (CR 225613) +// End Revision + +`timescale 1 ps / 1 ps + +module FDCE (Q, C, CE, CLR, D); + + parameter INIT = 1'b0; + + output Q; + + input C, CE, CLR, D; + + wire Q; + reg q_out; + tri0 GSR = glbl.GSR; + + initial q_out = INIT; + + assign Q = q_out; + + + always @(GSR or CLR) + if (GSR ) + assign q_out = INIT; + else if (CLR) + assign q_out = 0; + else + deassign q_out; + + always @(posedge C) + if (CE) + q_out <= D; + + specify + (posedge CLR => (Q +: 1'b0)) = (0, 0); + if (!CLR && CE) + (posedge C => (Q +: D)) = (100, 100); + endspecify + + +endmodule diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/FDCE_1.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/FDCE_1.v new file mode 100644 index 0000000..31633b8 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/FDCE_1.v @@ -0,0 +1,64 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/FDCE_1.v,v 1.13 2006/02/13 22:07:02 yanx Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / D Flip-Flop with Asynchronous Clear, Clock Enable and Negative-Edge Clock +// /___/ /\ Filename : FDCE_1.v +// \ \ / \ Timestamp : Thu Mar 25 16:42:16 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 02/04/05 - Rev 0.0.1 Remove input/output bufs; Seperate GSR from clock block. +// 08/09/05 - Add CLR to GSR block (CR 215196). +// 10/20/05 - Add set & reset check to main block. (CR219794) +// 2/07/06 - Remove set & reset from main block and add specify block (CR225119) +// 2/10/06 - Change Q from reg to wire (CR 225613) +// End Revision + +`timescale 1 ps / 1 ps + + +module FDCE_1 (Q, C, CE, CLR, D); + + parameter INIT = 1'b0; + + output Q; + + input C, CE, CLR, D; + + wire Q; + reg q_out; + + tri0 GSR = glbl.GSR; + + initial q_out = INIT; + + assign Q = q_out; + + + always @(GSR or CLR) + if (GSR) + assign q_out = INIT; + else if (CLR) + assign q_out = 0; + else + deassign q_out; + + always @(negedge C) + if (CE) + q_out <= D; + + specify + (posedge CLR => (Q +: 1'b0)) = (0, 0); + if (!CLR && CE) + (negedge C => (Q +: D)) = (100, 100); + endspecify + +endmodule diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/FDCP.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/FDCP.v new file mode 100644 index 0000000..aac6044 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/FDCP.v @@ -0,0 +1,65 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/FDCP.v,v 1.12 2006/02/13 22:07:02 yanx Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / D Flip-Flop with Asynchronous Clear and Preset +// /___/ /\ Filename : FDCP.v +// \ \ / \ Timestamp : Thu Mar 25 16:42:16 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 02/04/05 - Rev 0.0.1 Remove input/output bufs; Seperate GSR from clock block. +// 10/20/05 - Add set & reset check to main block. (CR219794) +// 2/07/06 - Remove set & reset from main block and add specify block (CR225119) +// 2/10/06 - Change Q from reg to wire (CR 225613) +// End Revision + +`timescale 1 ps / 1 ps + + +module FDCP (Q, C, CLR, D, PRE); + + parameter INIT = 1'b0; + + output Q; + input C, CLR, D, PRE; + + wire Q; + reg q_out; + + tri0 GSR = glbl.GSR; + + initial q_out = INIT; + + assign Q = q_out; + + + always @(GSR or CLR or PRE) + if (GSR) + assign q_out = INIT; + else if (CLR) + assign q_out = 0; + else if (PRE) + assign q_out = 1; + else + deassign q_out; + + always @(posedge C ) + q_out <= D; + + specify + (posedge CLR => (Q +: 1'b0)) = (0, 0); + if (!CLR) + (posedge PRE => (Q +: 1'b1)) = (0, 0); + if (!CLR && !PRE) + (posedge C => (Q +: D)) = (100, 100); + endspecify + +endmodule diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/FDCPE.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/FDCPE.v new file mode 100644 index 0000000..d7783d8 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/FDCPE.v @@ -0,0 +1,65 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/FDCPE.v,v 1.12 2006/02/13 22:07:02 yanx Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / D Flip-Flop with Asynchronous Clear and Preset and Clock Enable +// /___/ /\ Filename : FDCPE.v +// \ \ / \ Timestamp : Thu Mar 25 16:42:16 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 02/04/05 - Rev 0.0.1 Remove input/output bufs; Seperate GSR from clock block. +// 10/20/05 - Add set & reset check to main block. (CR219794) +// 2/07/06 - Remove set & reset from main block and add specify block (CR225119) +// 2/10/06 - Change Q from reg to wire (CR 225613) +// End Revision + +`timescale 1 ps / 1 ps + + +module FDCPE (Q, C, CE, CLR, D, PRE); + + parameter INIT = 1'b0; + + output Q; + + input C, CE, CLR, D, PRE; + + wire Q; + reg q_out; + tri0 GSR = glbl.GSR; + + initial q_out = INIT; + + assign Q = q_out; + + always @(GSR or CLR or PRE) + if (GSR) + assign q_out = INIT; + else if (CLR) + assign q_out = 0; + else if (PRE) + assign q_out = 1; + else + deassign q_out; + + always @(posedge C ) + if (CE) + q_out <= D; + + specify + (posedge CLR => (Q +: 1'b0)) = (0, 0); + if (!CLR) + (posedge PRE => (Q +: 1'b1)) = (0, 0); + if (!CLR && !PRE && CE) + (posedge C => (Q +: D)) = (100, 100); + endspecify + +endmodule diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/FDCPE_1.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/FDCPE_1.v new file mode 100644 index 0000000..6b66712 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/FDCPE_1.v @@ -0,0 +1,65 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/FDCPE_1.v,v 1.12 2006/02/13 22:07:02 yanx Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / D Flip-Flop with Asynchronous Clear and Preset, Clock Enable and Negative-Edge Clock +// /___/ /\ Filename : FDCPE_1.v +// \ \ / \ Timestamp : Thu Mar 25 16:42:16 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 02/04/05 - Rev 0.0.1 Remove input/output bufs; Seperate GSR from clock block. +// 10/20/05 - Add set & reset check to main block. (CR219794) +// 2/07/06 - Remove set & reset from main block and add specify block (CR225119) +// 2/10/06 - Change Q from reg to wire (CR 225613) +// End Revision + +`timescale 1 ps / 1 ps + + +module FDCPE_1 (Q, C, CE, CLR, D, PRE); + + parameter INIT = 1'b0; + + output Q; + + input C, CE, CLR, D, PRE; + + wire Q; + reg q_out; + tri0 GSR = glbl.GSR; + + initial q_out = INIT; + + assign Q = q_out; + + always @(GSR or CLR or PRE) + if (GSR) + assign q_out = INIT; + else if (CLR) + assign q_out = 0; + else if (PRE) + assign q_out = 1; + else + deassign q_out; + + always @(negedge C ) + if ( CE ==1) + q_out <= D; + + specify + (posedge CLR => (Q +: 1'b0)) = (0, 0); + if (!CLR) + (posedge PRE => (Q +: 1'b1)) = (0, 0); + if (!CLR && !PRE && CE) + (negedge C => (Q +: D)) = (100, 100); + endspecify + +endmodule diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/FDCP_1.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/FDCP_1.v new file mode 100644 index 0000000..7685bb5 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/FDCP_1.v @@ -0,0 +1,65 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/FDCP_1.v,v 1.12 2006/02/13 22:07:02 yanx Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / D Flip-Flop with Asynchronous Clear and Preset and Negative-Edge Clock +// /___/ /\ Filename : FDCP_1.v +// \ \ / \ Timestamp : Thu Mar 25 16:42:16 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 02/04/05 - Rev 0.0.1 Remove input/output bufs; Seperate GSR from clock block. +// 10/20/05 - Add set & reset check to main block. (CR219794) +// 2/07/06 - Remove set & reset from main block and add specify block (CR225119) +// 2/10/06 - Change Q from reg to wire (CR 225613) +// End Revision + +`timescale 1 ps / 1 ps + + +module FDCP_1 (Q, C, CLR, D, PRE); + + parameter INIT = 1'b0; + + output Q; + + input C, CLR, D, PRE; + + wire Q; + reg q_out; + tri0 GSR = glbl.GSR; + + initial q_out = INIT; + + assign Q = q_out; + + + always @(GSR or CLR or PRE) + if (GSR) + assign q_out = INIT; + else if (CLR) + assign q_out = 0; + else if (PRE) + assign q_out = 1; + else + deassign q_out; + + always @(negedge C ) + q_out <= D; + + specify + (posedge CLR => (Q +: 1'b0)) = (0, 0); + if (!CLR) + (posedge PRE => (Q +: 1'b1)) = (0, 0); + if (!CLR && !PRE) + (negedge C => (Q +: D)) = (100, 100); + endspecify + +endmodule diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/FDC_1.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/FDC_1.v new file mode 100644 index 0000000..cdb44a3 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/FDC_1.v @@ -0,0 +1,61 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/FDC_1.v,v 1.13 2006/02/13 22:07:02 yanx Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / D Flip-Flop with Asynchronous Clear and Negative-Edge Clock +// /___/ /\ Filename : FDC_1.v +// \ \ / \ Timestamp : Thu Mar 25 16:42:16 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 02/04/05 - Rev 0.0.1 Remove input/output bufs; Seperate GSR from clock block. +// 08/09/05 - Add CLR to GSR block (CR 215196). +// 10/20/05 - Add set & reset check to main block. (CR219794) +// 2/07/06 - Remove set & reset from main block and add specify block (CR225119) +// 2/10/06 - Change Q from reg to wire (CR 225613) +// End Revision + +`timescale 1 ps / 1 ps + + +module FDC_1 (Q, C, CLR, D); + + parameter INIT = 1'b0; + + output Q; + + input C, CLR, D; + + wire Q; + reg q_out; + tri0 GSR = glbl.GSR; + + initial q_out = INIT; + + assign Q = q_out; + + always @(GSR or CLR) + if (GSR) + assign q_out = INIT; + else if (CLR) + assign q_out = 0; + else + deassign q_out; + + always @(negedge C) + q_out <= D; + + specify + (posedge CLR => (Q +: 1'b0)) = (0, 0); + if (!CLR) + (negedge C => (Q +: D)) = (100, 100); + endspecify + +endmodule diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/FDDRCPE.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/FDDRCPE.v new file mode 100644 index 0000000..f124adb --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/FDDRCPE.v @@ -0,0 +1,114 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/FDDRCPE.v,v 1.16 2007/06/19 20:02:43 yanx Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Dual Data Rate D Flip-Flop with Asynchronous Clear and Preset and Clock Enable +// /___/ /\ Filename : FDDRCPE.v +// \ \ / \ Timestamp : Thu Mar 25 16:42:16 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 02/04/05 - Rev 0.0.1 Remove input/output bufs; Seperate GSR from clock block. +// 05/06/05 - Remove internal input data strobe and add to the output. (CR207678) +// 10/20/05 - Add set & reset check to main block. (CR219794) +// 10/28/05 - combine strobe block and data block. (CR220298). +// 2/07/06 - Remove set & reset from main block and add specify block (CR225119) +// 06/19/07 - Change INIT to 1 bit (CR441955) +// End Revision + +`timescale 1 ps / 1 ps + + +module FDDRCPE (Q, C0, C1, CE, CLR, D0, D1, PRE); + + parameter INIT = 1'b0; + + output Q; + + input C0, C1, CE, CLR, D0, D1, PRE; + + wire Q; + reg q_out; + tri0 GSR = glbl.GSR; + + reg q0_out, q1_out; + reg C0_tmp, C1_tmp; + + initial begin + q_out = INIT; + q0_out = INIT; + q1_out = INIT; + C0_tmp = 0; + C1_tmp = 0; + end + + assign Q = q_out; + + always @(GSR or CLR or PRE) + if (GSR) begin + assign q_out = INIT; + assign q0_out = INIT; + assign q1_out = INIT; + assign C0_tmp = 0; + assign C1_tmp = 0; + end + else if (CLR) begin + assign q_out = 0; + assign q0_out = 0; + assign q1_out = 0; + assign C0_tmp = 0; + assign C1_tmp = 0; + end + else if (PRE) begin + assign q_out = 1; + assign q0_out = 1; + assign q1_out = 1; + assign C0_tmp = 0; + assign C1_tmp = 0; + end + else begin + deassign q_out; + deassign q0_out; + deassign q1_out; + deassign C0_tmp; + deassign C1_tmp; + end + + always @(posedge C0) + if ( CE) begin + C0_tmp <= 1; + C0_tmp <= #100 0; + q0_out <= D0; + end + + always @(posedge C1) + if ( CE ) begin + C1_tmp <= 1; + C1_tmp <= #100 0; + q1_out <= D1; + end + + always @(posedge C0_tmp or posedge C1_tmp ) + if (C1_tmp) + q_out = q1_out; + else + q_out = q0_out; + + specify + (posedge CLR => (Q +: 1'b0)) = (0, 0); + if (!CLR) + (posedge PRE => (Q +: 1'b1)) = (0, 0); + if (!CLR && !PRE && CE) + (posedge C0 => (Q +: D0)) = (100, 100); + if (!CLR && !PRE && CE) + (posedge C1 => (Q +: D1)) = (100, 100); + endspecify + +endmodule diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/FDDRRSE.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/FDDRRSE.v new file mode 100644 index 0000000..789fc5e --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/FDDRRSE.v @@ -0,0 +1,120 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/FDDRRSE.v,v 1.16 2007/06/19 20:02:43 yanx Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Dual Data Rate D Flip-Flop with Synchronous Reset and Set and Clock Enable +// /___/ /\ Filename : FDDRRSE.v +// \ \ / \ Timestamp : Thu Mar 25 16:42:16 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 02/04/05 - Rev 0.0.1 Remove input/output bufs; Seperate GSR from clock block. +// 05/06/05 - Remove internal input data strobe and add to the output. (CR207678) +// 10/20/05 - Add set & reset check to main block. (CR219794) +// 10/28/05 - combine strobe block and data block. (CR220298). +// 2/07/06 - Remove set & reset from main block and add specify block (CR225119) +// 2/10/06 - Change Q from reg to wire (CR 225613) +// 06/19/07 - Change INIT to 1 bit (CR441955). +// End Revision + +`timescale 1 ps / 1 ps + + +module FDDRRSE (Q, C0, C1, CE, D0, D1, R, S); + + parameter INIT = 1'b0; + + output Q; + + input C0, C1, CE, D0, D1, R, S; + + wire Q; + reg q_out; + tri0 GSR = glbl.GSR; + + reg q0_out, q1_out; + reg C0_tmp, C1_tmp; + + always @(GSR) + if (GSR) begin + assign q_out = INIT; + assign q0_out = INIT; + assign q1_out = INIT; + assign C0_tmp = 0; + assign C1_tmp = 0; + end + else begin + deassign q_out; + deassign q0_out; + deassign q1_out; + deassign C0_tmp; + deassign C1_tmp; + end + + initial begin + q_out = INIT; + q0_out = INIT; + q1_out = INIT; + C0_tmp = 0; + C1_tmp = 0; + end + + assign Q = q_out; + + always @(posedge C0) + if (CE == 1 || R == 1 || S == 1) begin + C0_tmp <= 1; + C0_tmp <= #100 0; + end + + always @(posedge C1) + if (CE == 1 || R == 1 || S == 1) begin + C1_tmp <= 1; + C1_tmp <= #100 0; + end + + always @(posedge C0) + if (R) + q0_out <= 0; + else if (S) + q0_out <= 1; + else if (CE) + q0_out <= D0; + + always @(posedge C1) + if (R) + q1_out <= 0; + else if (S) + q1_out <= 1; + else if (CE) + q1_out <= D1; + + always @(posedge C0_tmp or posedge C1_tmp ) + if (C1_tmp) + q_out = q1_out; + else + q_out = q0_out; + + specify + if (R) + (posedge C0 => (Q +: 1'b0)) = (100, 100); + if (!R && S) + (posedge C0 => (Q +: 1'b1)) = (100, 100); + if (!R && !S && CE) + (posedge C0 => (Q +: D0)) = (100, 100); + if (R) + (posedge C1 => (Q +: 1'b0)) = (100, 100); + if (!R && S) + (posedge C1 => (Q +: 1'b1)) = (100, 100); + if (!R && !S && CE) + (posedge C1 => (Q +: D1)) = (100, 100); + endspecify + +endmodule diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/FDE.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/FDE.v new file mode 100644 index 0000000..12da69c --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/FDE.v @@ -0,0 +1,58 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/FDE.v,v 1.11 2006/02/13 22:07:02 yanx Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / D Flip-Flop with Clock Enable +// /___/ /\ Filename : FDE.v +// \ \ / \ Timestamp : Thu Mar 25 16:42:17 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 02/04/05 - Rev 0.0.1 Remove input/output bufs; Seperate GSR from clock block. +// 10/20/05 - Add set & reset check to main block. (CR219794) +// 2/07/06 - Remove set & reset from main block and add specify block (CR225119) +// 2/10/06 - Change Q from reg to wire (CR 225613) +// End Revision + +`timescale 1 ps / 1 ps + + +module FDE (Q, C, CE, D); + + parameter INIT = 1'b0; + + output Q; + + input C, CE, D; + + wire Q; + reg q_out; + tri0 GSR = glbl.GSR; + + initial q_out = INIT; + + assign Q = q_out; + + always @(GSR) + if (GSR) + assign q_out = INIT; + else + deassign q_out; + + always @(posedge C) + if (CE) + q_out <= D; + + specify + if (CE) + (posedge C => (Q +: D)) = (100, 100); + endspecify + +endmodule diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/FDE_1.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/FDE_1.v new file mode 100644 index 0000000..61a4ada --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/FDE_1.v @@ -0,0 +1,60 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/FDE_1.v,v 1.11 2006/02/13 22:07:02 yanx Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / D Flip-Flop with Clock Enable and Negative-Edge Clock +// /___/ /\ Filename : FDE_1.v +// \ \ / \ Timestamp : Thu Mar 25 16:42:17 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 02/04/05 - Rev 0.0.1 Remove input/output bufs; Seperate GSR from clock block. +// 10/20/05 - Add set & reset check to main block. (CR219794) +// 2/07/06 - Remove set & reset from main block and add specify block (CR225119) +// 2/10/06 - Change Q from reg to wire (CR 225613) +// End Revision + +`timescale 1 ps / 1 ps + + +module FDE_1 (Q, C, CE, D); + + parameter INIT = 1'b0; + + output Q; + + input C, CE, D; + + wire Q; + reg q_out; + tri0 GSR = glbl.GSR; + + initial q_out = INIT; + + assign Q = q_out; + + + always @(GSR) + if (GSR) + assign q_out = INIT; + else + deassign q_out; + + always @(negedge C ) + if (CE) + q_out <= D; + + specify + if (CE) + (negedge C => (Q +: D)) = (100, 100); + endspecify + + +endmodule diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/FDP.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/FDP.v new file mode 100644 index 0000000..cd6f7aa --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/FDP.v @@ -0,0 +1,61 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/FDP.v,v 1.13 2006/02/13 22:07:02 yanx Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / D Flip-Flop with Asynchronous Preset +// /___/ /\ Filename : FDP.v +// \ \ / \ Timestamp : Thu Mar 25 16:42:17 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 02/04/05 - Rev 0.0.1 Remove input/output bufs; Seperate GSR from clock block. +// 08/09/05 - Add PRE to GSR block (CR 215196). +// 10/20/05 - Add set & reset check to main block. (CR219794) +// 2/07/06 - Remove set & reset from main block and add specify block (CR225119) +// 2/10/06 - Change Q from reg to wire (CR 225613) +// End Revision + +`timescale 1 ps / 1 ps + + +module FDP (Q, C, D, PRE); + + parameter INIT = 1'b1; + + output Q; + + input C, D, PRE; + + wire Q; + reg q_out; + tri0 GSR = glbl.GSR; + + initial q_out = INIT; + + assign Q = q_out; + + always @(GSR or PRE) + if (GSR) + assign q_out = INIT; + else if (PRE) + assign q_out = 1; + else + deassign q_out; + + always @(posedge C ) + q_out <= D; + + specify + (posedge PRE => (Q +: 1'b1)) = (0, 0); + if (!PRE) + (posedge C => (Q +: D)) = (100, 100); + endspecify + +endmodule diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/FDPE.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/FDPE.v new file mode 100644 index 0000000..7940ea1 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/FDPE.v @@ -0,0 +1,64 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/FDPE.v,v 1.13 2006/02/13 22:07:02 yanx Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / D Flip-Flop with Asynchronous Preset and Clock Enable +// /___/ /\ Filename : FDPE.v +// \ \ / \ Timestamp : Thu Mar 25 16:42:17 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 02/04/05 - Rev 0.0.1 Remove input/output bufs; Seperate GSR from clock block. +// 08/09/05 - Add PRE to GSR block (CR 215196). +// 10/20/05 - Add set & reset check to main block. (CR219794) +// 2/07/06 - Remove set & reset from main block and add specify block (CR225119) +// 2/10/06 - Change Q from reg to wire (CR 225613) +// End Revision + +`timescale 1 ps / 1 ps + + +module FDPE (Q, C, CE, D, PRE); + + parameter INIT = 1'b1; + + output Q; + + input C, CE, D, PRE; + + wire Q; + reg q_out; + tri0 GSR = glbl.GSR; + + initial q_out = INIT; + + + assign Q = q_out; + + always @(GSR or PRE) + if (GSR) + assign q_out = INIT; + else if (PRE) + assign q_out = 1; + else + deassign q_out; + + always @(posedge C ) + if (CE) + q_out <= D; + + specify + (posedge PRE => (Q +: 1'b1)) = (0, 0); + if (!PRE && CE) + (posedge C => (Q +: D)) = (100, 100); + endspecify + + +endmodule diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/FDPE_1.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/FDPE_1.v new file mode 100644 index 0000000..b517940 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/FDPE_1.v @@ -0,0 +1,63 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/FDPE_1.v,v 1.13 2006/02/13 22:07:02 yanx Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / D Flip-Flop with Asynchronous Preset, Clock Enable and Negative-Edge Clock +// /___/ /\ Filename : FDPE_1.v +// \ \ / \ Timestamp : Thu Mar 25 16:42:17 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 02/04/05 - Rev 0.0.1 Remove input/output bufs; Seperate GSR from clock block. +// 08/09/05 - Add PRE to GSR block (CR 215196). +// 10/20/05 - Add set & reset check to main block. (CR219794) +// 2/07/06 - Remove set & reset from main block and add specify block (CR225119) +// 2/10/06 - Change Q from reg to wire (CR 225613) +// End Revision + +`timescale 1 ps / 1 ps + + +module FDPE_1 (Q, C, CE, D, PRE); + + parameter INIT = 1'b1; + + output Q; + + input C, CE, D, PRE; + + wire Q; + reg q_out; + tri0 GSR = glbl.GSR; + + initial q_out = INIT; + + assign Q = q_out; + + + always @(GSR or PRE) + if (GSR) + assign q_out = INIT; + else if (PRE) + assign q_out = 1; + else + deassign q_out; + + always @(negedge C ) + if (CE) + q_out <= D; + + specify + (posedge PRE => (Q +: 1'b1)) = (0, 0); + if (!PRE && CE) + (negedge C => (Q +: D)) = (100, 100); + endspecify + +endmodule diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/FDP_1.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/FDP_1.v new file mode 100644 index 0000000..8abfdb6 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/FDP_1.v @@ -0,0 +1,64 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/FDP_1.v,v 1.13 2006/02/13 22:07:02 yanx Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / D Flip-Flop with Asynchronous Preset and Negative-Edge Clock +// /___/ /\ Filename : FDP_1.v +// \ \ / \ Timestamp : Thu Mar 25 16:42:17 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 02/04/05 - Rev 0.0.1 Remove input/output bufs; Seperate GSR from clock block. +// 08/09/05 - Add PRE to GSR block (CR 215196). +// 10/20/05 - Add set & reset check to main block. (CR219794) +// 2/07/06 - Remove set & reset from main block and add specify block (CR225119) +// 2/10/06 - Change Q from reg to wire (CR 225613) +// End Revision + + +`timescale 1 ps / 1 ps + + +module FDP_1 (Q, C, D, PRE); + + parameter INIT = 1'b1; + + output Q; + + input C, D, PRE; + + wire Q; + reg q_out; + tri0 GSR = glbl.GSR; + + initial q_out = INIT; + + assign Q = q_out; + + + always @(GSR or PRE) + if (GSR) + assign q_out = INIT; + else if (PRE) + assign q_out = 1; + else + deassign q_out; + + always @(negedge C) + q_out <= D; + + specify + (posedge PRE => (Q +: 1'b1)) = (0, 0); + if (!PRE) + (negedge C => (Q +: D)) = (100, 100); + endspecify + + +endmodule diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/FDR.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/FDR.v new file mode 100644 index 0000000..0074458 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/FDR.v @@ -0,0 +1,62 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/FDR.v,v 1.11 2006/02/13 22:07:02 yanx Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / D Flip-Flop with Synchronous Reset +// /___/ /\ Filename : FDR.v +// \ \ / \ Timestamp : Thu Mar 25 16:42:17 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 02/04/05 - Rev 0.0.1 Remove input/output bufs; Seperate GSR from clock block. +// 10/20/05 - Add set & reset check to main block. (CR219794) +// 2/07/06 - Remove set & reset from main block and add specify block (CR225119) +// 2/10/06 - Change Q from reg to wire (CR 225613) +// End Revision + +`timescale 1 ps / 1 ps + + +module FDR (Q, C, D, R); + + parameter INIT = 1'b0; + + output Q; + + input C, D, R; + + wire Q; + reg q_out; + tri0 GSR = glbl.GSR; + + initial q_out = INIT; + + assign Q = q_out; + + always @(GSR) + if (GSR) + assign q_out = INIT; + else + deassign q_out; + + always @(posedge C ) + if (R) + q_out <= 0; + else + q_out <= D; + + specify + if (R) + (posedge C => (Q +: 1'b0)) = (100, 100); + if (!R) + (posedge C => (Q +: D)) = (100, 100); + endspecify + +endmodule diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/FDRE.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/FDRE.v new file mode 100644 index 0000000..5121e44 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/FDRE.v @@ -0,0 +1,64 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/FDRE.v,v 1.11 2006/02/13 22:07:02 yanx Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / D Flip-Flop with Synchronous Reset and Clock Enable +// /___/ /\ Filename : FDRE.v +// \ \ / \ Timestamp : Thu Mar 25 16:42:17 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 02/04/05 - Rev 0.0.1 Remove input/output bufs; Seperate GSR from clock block. +// 10/20/05 - Add set & reset check to main block. (CR219794) +// 2/07/06 - Remove set & reset from main block and add specify block (CR225119) +// 2/10/06 - Change Q from reg to wire (CR 225613) +// End Revision + +`timescale 1 ps / 1 ps + + +module FDRE (Q, C, CE, D, R); + + parameter INIT = 1'b0; + + output Q; + + input C, CE, D, R; + + wire Q; + reg q_out; + tri0 GSR = glbl.GSR; + + initial q_out = INIT; + + assign Q = q_out; + + + always @(GSR) + if (GSR) + assign q_out = INIT; + else + deassign q_out; + + always @(posedge C ) + if (R) + q_out <= 0; + else if (CE) + q_out <= D; + + specify + if (R) + (posedge C => (Q +: 1'b0)) = (100, 100); + if (!R && CE) + (posedge C => (Q +: D)) = (100, 100); + endspecify + + +endmodule diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/FDRE_1.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/FDRE_1.v new file mode 100644 index 0000000..8fe8a8a --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/FDRE_1.v @@ -0,0 +1,63 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/FDRE_1.v,v 1.11 2006/02/13 22:07:02 yanx Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / D Flip-Flop with Synchronous Reset, Clock Enable and Negative-Edge Clock +// /___/ /\ Filename : FDRE_1.v +// \ \ / \ Timestamp : Thu Mar 25 16:42:17 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 02/04/05 - Rev 0.0.1 Remove input/output bufs; Seperate GSR from clock block. +// 10/20/05 - Add set & reset check to main block. (CR219794) +// 2/07/06 - Remove set & reset from main block and add specify block (CR225119) +// 2/10/06 - Change Q from reg to wire (CR 225613) +// End Revision + +`timescale 1 ps / 1 ps + + +module FDRE_1 (Q, C, CE, D, R); + + parameter INIT = 1'b0; + + output Q; + + input C, CE, D, R; + + wire Q; + reg q_out; + tri0 GSR = glbl.GSR; + + initial q_out = INIT; + + assign Q = q_out; + + + always @(GSR) + if (GSR) + assign q_out = INIT; + else + deassign q_out; + + always @(negedge C ) + if (R) + q_out <= 0; + else if (CE) + q_out <= D; + + specify + if (R) + (negedge C => (Q +: 1'b0)) = (100, 100); + if (!R && CE) + (negedge C => (Q +: D)) = (100, 100); + endspecify + +endmodule diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/FDRS.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/FDRS.v new file mode 100644 index 0000000..8c9d44e --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/FDRS.v @@ -0,0 +1,67 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/FDRS.v,v 1.11 2006/02/13 22:07:02 yanx Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / D Flip-Flop with Synchronous Reset and Set +// /___/ /\ Filename : FDRS.v +// \ \ / \ Timestamp : Thu Mar 25 16:42:17 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 02/04/05 - Rev 0.0.1 Remove input/output bufs; Seperate GSR from clock block. +// 10/20/05 - Add set & reset check to main block. (CR219794) +// 2/07/06 - Remove set & reset from main block and add specify block (CR225119) +// 2/10/06 - Change Q from reg to wire (CR 225613) +// End Revision + +`timescale 1 ps / 1 ps + + +module FDRS (Q, C, D, R, S); + + parameter INIT = 1'b0; + + output Q; + + input C, D, R, S; + + wire Q; + reg q_out; + tri0 GSR = glbl.GSR; + + initial q_out = INIT; + + assign Q = q_out; + + + always @(GSR) + if (GSR) + assign q_out = INIT; + else + deassign q_out; + + always @(posedge C ) + if (R) + q_out <= 0; + else if (S) + q_out <= 1; + else + q_out <= D; + + specify + if (R) + (posedge C => (Q +: 1'b0)) = (100, 100); + if (!R && S) + (posedge C => (Q +: 1'b1)) = (100, 100); + if (!R && !S) + (posedge C => (Q +: D)) = (100, 100); + endspecify + +endmodule diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/FDRSE.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/FDRSE.v new file mode 100644 index 0000000..ddf5dc0 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/FDRSE.v @@ -0,0 +1,66 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/FDRSE.v,v 1.11 2006/02/13 22:07:02 yanx Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / D Flip-Flop with Synchronous Reset and Set and Clock Enable +// /___/ /\ Filename : FDRSE.v +// \ \ / \ Timestamp : Thu Mar 25 16:42:18 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 02/04/05 - Rev 0.0.1 Remove input/output bufs; Seperate GSR from clock block. +// 10/20/05 - Add set & reset check to main block. (CR219794) +// 2/07/06 - Remove set & reset from main block and add specify block (CR225119) +// 2/10/06 - Change Q from reg to wire (CR 225613) +// End Revision + +`timescale 1 ps / 1 ps + + +module FDRSE (Q, C, CE, D, R, S); + + parameter INIT = 1'b0; + + output Q; + + input C, CE, D, R, S; + + wire Q; + reg q_out; + tri0 GSR = glbl.GSR; + + initial q_out = INIT; + + assign Q = q_out; + + + always @(GSR) + if (GSR) + assign q_out = INIT; + else + deassign q_out; + + always @(posedge C ) + if (R) + q_out <= 0; + else if (S) + q_out <= 1; + else if (CE) + q_out <= D; + + specify + if (R) + (posedge C => (Q +: 1'b0)) = (100, 100); + if (!R && S) + (posedge C => (Q +: 1'b1)) = (100, 100); + if (!R && !S && CE) + (posedge C => (Q +: D)) = (100, 100); + endspecify +endmodule diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/FDRSE_1.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/FDRSE_1.v new file mode 100644 index 0000000..4e71715 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/FDRSE_1.v @@ -0,0 +1,66 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/FDRSE_1.v,v 1.11 2006/02/13 22:07:02 yanx Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / D Flip-Flop with Synchronous Reset and Set, Clock Enable and Negative-Edge Clock +// /___/ /\ Filename : FDRSE_1.v +// \ \ / \ Timestamp : Thu Mar 25 16:42:18 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 02/04/05 - Rev 0.0.1 Remove input/output bufs; Seperate GSR from clock block. +// 10/20/05 - Add set & reset check to main block. (CR219794) +// 2/07/06 - Remove set & reset from main block and add specify block (CR225119) +// 2/10/06 - Change Q from reg to wire (CR 225613) +// End Revision + +`timescale 1 ps / 1 ps + + +module FDRSE_1 (Q, C, CE, D, R, S); + + parameter INIT = 1'b0; + + output Q; + + input C, CE, D, R, S; + + wire Q; + reg q_out; + tri0 GSR = glbl.GSR; + + initial q_out = INIT; + + assign Q = q_out; + + always @(GSR) + if (GSR) + assign q_out = INIT; + else + deassign q_out; + + always @(negedge C ) + if (R) + q_out <= 0; + else if (S) + q_out <= 1; + else if (CE) + q_out <= D; + + specify + if (R) + (negedge C => (Q +: 1'b0)) = (100, 100); + if (!R && S) + (negedge C => (Q +: 1'b1)) = (100, 100); + if (!R && !S && CE) + (negedge C => (Q +: D)) = (100, 100); + endspecify + +endmodule diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/FDRS_1.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/FDRS_1.v new file mode 100644 index 0000000..52987aa --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/FDRS_1.v @@ -0,0 +1,67 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/FDRS_1.v,v 1.11 2006/02/13 22:07:02 yanx Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / D Flip-Flop with Synchronous Reset and Set and Negative-Edge Clock +// /___/ /\ Filename : FDRS_1.v +// \ \ / \ Timestamp : Thu Mar 25 16:42:18 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 02/04/05 - Rev 0.0.1 Remove input/output bufs; Seperate GSR from clock block. +// 10/20/05 - Add set & reset check to main block. (CR219794) +// 2/07/06 - Remove set & reset from main block and add specify block (CR225119) +// 2/10/06 - Change Q from reg to wire (CR 225613) +// End Revision + +`timescale 1 ps / 1 ps + + +module FDRS_1 (Q, C, D, R, S); + + parameter INIT = 1'b0; + + output Q; + + input C, D, R, S; + + wire Q; + reg q_out; + tri0 GSR = glbl.GSR; + + initial q_out = INIT; + + assign Q = q_out; + + + always @(GSR) + if (GSR) + assign q_out = INIT; + else + deassign q_out; + + always @(negedge C) + if (R) + q_out <= 0; + else if (S) + q_out <= 1; + else + q_out <= D; + + specify + if (R) + (negedge C => (Q +: 1'b0)) = (100, 100); + if (!R && S) + (negedge C => (Q +: 1'b1)) = (100, 100); + if (!R && !S) + (negedge C => (Q +: D)) = (100, 100); + endspecify + +endmodule diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/FDR_1.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/FDR_1.v new file mode 100644 index 0000000..8b6c6d0 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/FDR_1.v @@ -0,0 +1,63 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/FDR_1.v,v 1.11 2006/02/13 22:07:03 yanx Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / D Flip-Flop with Synchronous Reset and Negative-Edge Clock +// /___/ /\ Filename : FDR_1.v +// \ \ / \ Timestamp : Thu Mar 25 16:42:18 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 02/04/05 - Rev 0.0.1 Remove input/output bufs; Seperate GSR from clock block. +// 10/20/05 - Add set & reset check to main block. (CR219794) +// 2/07/06 - Remove set & reset from main block and add specify block (CR225119) +// 2/10/06 - Change Q from reg to wire (CR 225613) +// End Revision + +`timescale 1 ps / 1 ps + + +module FDR_1 (Q, C, D, R); + + parameter INIT = 1'b0; + + output Q; + + input C, D, R; + + wire Q; + reg q_out; + tri0 GSR = glbl.GSR; + + initial q_out = INIT; + + assign Q = q_out; + + + always @(GSR) + if (GSR) + assign q_out = INIT; + else + deassign q_out; + + always @(negedge C ) + if (R) + q_out <= 0; + else + q_out <= D; + + specify + if (R) + (negedge C => (Q +: 1'b0)) = (100, 100); + if (!R) + (negedge C => (Q +: D)) = (100, 100); + endspecify + +endmodule diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/FDS.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/FDS.v new file mode 100644 index 0000000..6c91971 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/FDS.v @@ -0,0 +1,63 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/FDS.v,v 1.11 2006/02/13 22:07:03 yanx Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / D Flip-Flop with Synchronous Set +// /___/ /\ Filename : FDS.v +// \ \ / \ Timestamp : Thu Mar 25 16:42:18 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 02/04/05 - Rev 0.0.1 Remove input/output bufs; Seperate GSR from clock block. +// 10/20/05 - Add set & reset check to main block. (CR219794) +// 2/07/06 - Remove set & reset from main block and add specify block (CR225119) +// 2/10/06 - Change Q from reg to wire (CR 225613) +// End Revision + +`timescale 1 ps / 1 ps + + +module FDS (Q, C, D, S); + + parameter INIT = 1'b1; + + output Q; + + input C, D, S; + + wire Q; + reg q_out; + tri0 GSR = glbl.GSR; + + initial q_out = INIT; + + assign Q = q_out; + + + always @(GSR) + if (GSR) + assign q_out = INIT; + else + deassign q_out; + + always @(posedge C ) + if (S) + q_out <= 1; + else + q_out <= D; + + specify + if (S) + (posedge C => (Q +: 1'b1)) = (100, 100); + if (!S) + (posedge C => (Q +: D)) = (100, 100); + endspecify + +endmodule diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/FDSE.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/FDSE.v new file mode 100644 index 0000000..37ec79e --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/FDSE.v @@ -0,0 +1,63 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/FDSE.v,v 1.11 2006/02/13 22:07:03 yanx Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / D Flip-Flop with Synchronous Set and Clock Enable +// /___/ /\ Filename : FDSE.v +// \ \ / \ Timestamp : Thu Mar 25 16:42:18 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 02/04/05 - Rev 0.0.1 Remove input/output bufs; Seperate GSR from clock block. +// 10/20/05 - Add set & reset check to main block. (CR219794) +// 2/07/06 - Remove set & reset from main block and add specify block (CR225119) +// 2/10/06 - Change Q from reg to wire (CR 225613) +// End Revision + +`timescale 1 ps / 1 ps + + +module FDSE (Q, C, CE, D, S); + + parameter INIT = 1'b1; + + output Q; + + input C, CE, D, S; + + wire Q; + reg q_out; + tri0 GSR = glbl.GSR; + + initial q_out = INIT; + + assign Q = q_out; + + + always @(GSR) + if (GSR) + assign q_out = INIT; + else + deassign q_out; + + always @(posedge C ) + if (S) + q_out <= 1; + else if (CE) + q_out <= D; + + specify + if (S) + (posedge C => (Q +: 1'b1)) = (100, 100); + if (!S && CE) + (posedge C => (Q +: D)) = (100, 100); + endspecify + +endmodule diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/FDSE_1.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/FDSE_1.v new file mode 100644 index 0000000..e5cecae --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/FDSE_1.v @@ -0,0 +1,63 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/FDSE_1.v,v 1.11 2006/02/13 22:07:03 yanx Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / D Flip-Flop with Synchronous Set, Clock Enable and Negative-Edge Clock +// /___/ /\ Filename : FDSE_1.v +// \ \ / \ Timestamp : Thu Mar 25 16:42:18 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 02/04/05 - Rev 0.0.1 Remove input/output bufs; Seperate GSR from clock block. +// 10/20/05 - Add set & reset check to main block. (CR219794) +// 2/07/06 - Remove set & reset from main block and add specify block (CR225119) +// 2/10/06 - Change Q from reg to wire (CR 225613) +// End Revision + +`timescale 1 ps / 1 ps + + +module FDSE_1 (Q, C, CE, D, S); + + parameter INIT = 1'b1; + + output Q; + + input C, CE, D, S; + + wire Q; + reg q_out; + tri0 GSR = glbl.GSR; + + initial q_out = INIT; + + assign Q = q_out; + + + always @(GSR) + if (GSR) + assign q_out = INIT; + else + deassign q_out; + + always @(negedge C ) + if (S) + q_out <= 1; + else if (CE) + q_out <= D; + + specify + if (S) + (negedge C => (Q +: 1'b1)) = (100, 100); + if (!S && CE) + (negedge C => (Q +: D)) = (100, 100); + endspecify + +endmodule diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/FDS_1.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/FDS_1.v new file mode 100644 index 0000000..7f3a939 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/FDS_1.v @@ -0,0 +1,63 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/FDS_1.v,v 1.11 2006/02/13 22:07:03 yanx Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / D Flip-Flop with Synchronous Set and Negative-Edge Clock +// /___/ /\ Filename : FDS_1.v +// \ \ / \ Timestamp : Thu Mar 25 16:42:18 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 02/04/05 - Rev 0.0.1 Remove input/output bufs; Seperate GSR from clock block. +// 10/20/05 - Add set & reset check to main block. (CR219794) +// 2/07/06 - Remove set & reset from main block and add specify block (CR225119) +// 2/10/06 - Change Q from reg to wire (CR 225613) +// End Revision + +`timescale 1 ps / 1 ps + + +module FDS_1 (Q, C, D, S); + + parameter INIT = 1'b1; + + output Q; + + input C, D, S; + + wire Q; + reg q_out; + tri0 GSR = glbl.GSR; + + initial q_out = INIT; + + assign Q = q_out; + + + always @(GSR) + if (GSR) + assign q_out = INIT; + else + deassign q_out; + + always @(negedge C ) + if (S) + q_out <= 1; + else + q_out <= D; + + specify + if (S) + (negedge C => (Q +: 1'b1)) = (100, 100); + if (!S) + (negedge C => (Q +: D)) = (100, 100); + endspecify + +endmodule diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/FD_1.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/FD_1.v new file mode 100644 index 0000000..3e02b75 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/FD_1.v @@ -0,0 +1,56 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/FD_1.v,v 1.11 2006/02/13 22:07:03 yanx Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / D Flip-Flop with Negative-Edge Clock +// /___/ /\ Filename : FD_1.v +// \ \ / \ Timestamp : Thu Mar 25 16:42:18 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 02/04/05 - Rev 0.0.1 Remove input/output bufs; Seperate GSR from clock block. +// 10/20/05 - Add set & reset check to main block. (CR219794) +// 2/07/06 - Remove set & reset from main block and add specify block (CR225119) +// 2/10/06 - Change Q from reg to wire (CR 225613) +// End Revision + +`timescale 1 ps / 1 ps + + +module FD_1 (Q, C, D); + + parameter INIT = 1'b0; + + output Q; + + input C, D; + + wire Q; + reg q_out; + tri0 GSR = glbl.GSR; + + initial q_out = INIT; + + assign Q = q_out; + + always @(GSR) + if (GSR) + assign q_out = INIT; + else + deassign q_out; + + always @(negedge C ) + q_out <= D; + + specify + (negedge C => (Q +: D)) = (100, 100); + endspecify + +endmodule diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/FIFO16.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/FIFO16.v new file mode 100644 index 0000000..d035488 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/FIFO16.v @@ -0,0 +1,798 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/virtex4/FIFO16.v,v 1.14 2007/06/06 22:10:08 wloo Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2005 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / 16K-Bit FIFO +// /___/ /\ Filename : FIFO16.v +// \ \ / \ Timestamp : Thu Mar 11 16:44:06 PST 2005 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 03/11/05 - Added LOC parameter, removed GSR ports and initialized outpus. +// 12/08/05 - Pulled up the unused bits in wrcount and rdcount. Xs the unused bits in DO and DOP. +// 02/06/06 - Updated the reset requirement message. +// 05/31/06 - Added feature for invalid reset condition. (CR 223364). +// 06/06/07 - Added wire declaration for internal signals. +// End Revision + +`timescale 1 ps/1 ps + +module FIFO16 (ALMOSTEMPTY, ALMOSTFULL, DO, DOP, EMPTY, FULL, RDCOUNT, RDERR, WRCOUNT, WRERR, DI, DIP, RDCLK, RDEN, RST, WRCLK, WREN +); + + output ALMOSTEMPTY; + output ALMOSTFULL; + output [31:0] DO; + output [3:0] DOP; + output EMPTY; + output FULL; + output [11:0] RDCOUNT; + output RDERR; + output [11:0] WRCOUNT; + output WRERR; + + input [31:0] DI; + input [3:0] DIP; + tri0 GSR = glbl.GSR; + input RDCLK; + input RDEN; + input RST; + input WRCLK; + input WREN; + + parameter ALMOST_FULL_OFFSET = 12'h080; + parameter ALMOST_EMPTY_OFFSET = 12'h080; + parameter integer DATA_WIDTH = 36; + parameter FIRST_WORD_FALL_THROUGH = "FALSE"; + + reg [31:0] do_in, do_out = 32'b0; + reg [3:0] dop_in, dop_out = 4'b0; + reg almostempty_out = 1, almostfull_out = 0, empty_out = 1, full_out = 0, rderr_out = 0, wrerr_out = 0; + reg [11:0] rdcount_out = 12'b0; + + wire [31:0] di_in; + wire [3:0] dip_in; + wire rdclk_in, rden_in, rst_in, wrclk_in, wren_in; + wire gsr_in; + + reg rden_reg, wren_reg; + reg [11:0] ae_empty; + reg [31:0] d_w; + reg [31:0] p_w; + reg fwft; + reg [16383:0] mem; + reg [2047:0] memp; + integer addr_limit, wr_addr = 0, rd_addr, rd_prefetch; + integer wr1_addr; + reg rd_flag, rdcount_flag, rdprefetch_flag, wr_flag; + reg wr1_flag; + reg [3:0] almostfull_int, almostempty_int; + reg [3:0] full_int; + reg [3:0] empty_ram; + reg [7:0] i, j; + reg rst_tmp1, rst_tmp2; + reg [2:0] rst_rdckreg, rst_wrckreg; + reg [11:0] wr_addr_out = 12'hfff; + reg [11:0] rdcount_out_out = 12'hfff; + wire [31:0] do_out_out; + wire [3:0] dop_out_out; + reg rst_rdclk_flag = 0, rst_wrclk_flag = 0; + + reg notifier; + + wire do_out0, do_out1, do_out2, do_out3, do_out4, do_out5, do_out6, do_out7, do_out8, do_out9, do_out10, do_out11, do_out12, do_out13, do_out14, do_out15, do_out16, do_out17, do_out18, do_out19, do_out20, do_out21, do_out22, do_out23, do_out24, do_out25, do_out26, do_out27, do_out28, do_out29, do_out30, do_out31, dop_out0, dop_out1, dop_out2, dop_out3; + wire rdcount_out0, rdcount_out1, rdcount_out2, rdcount_out3, rdcount_out4, rdcount_out5, rdcount_out6, rdcount_out7, rdcount_out8, rdcount_out9, rdcount_out10, rdcount_out11; + wire wrcount_out0, wrcount_out1, wrcount_out2, wrcount_out3, wrcount_out4, wrcount_out5, wrcount_out6, wrcount_out7, wrcount_out8, wrcount_out9, wrcount_out10, wrcount_out11; + + buf b_di_0 (di_in[0], DI[0]); + buf b_di_1 (di_in[1], DI[1]); + buf b_di_2 (di_in[2], DI[2]); + buf b_di_3 (di_in[3], DI[3]); + buf b_di_4 (di_in[4], DI[4]); + buf b_di_5 (di_in[5], DI[5]); + buf b_di_6 (di_in[6], DI[6]); + buf b_di_7 (di_in[7], DI[7]); + buf b_di_8 (di_in[8], DI[8]); + buf b_di_9 (di_in[9], DI[9]); + buf b_di_10 (di_in[10], DI[10]); + buf b_di_11 (di_in[11], DI[11]); + buf b_di_12 (di_in[12], DI[12]); + buf b_di_13 (di_in[13], DI[13]); + buf b_di_14 (di_in[14], DI[14]); + buf b_di_15 (di_in[15], DI[15]); + buf b_di_16 (di_in[16], DI[16]); + buf b_di_17 (di_in[17], DI[17]); + buf b_di_18 (di_in[18], DI[18]); + buf b_di_19 (di_in[19], DI[19]); + buf b_di_20 (di_in[20], DI[20]); + buf b_di_21 (di_in[21], DI[21]); + buf b_di_22 (di_in[22], DI[22]); + buf b_di_23 (di_in[23], DI[23]); + buf b_di_24 (di_in[24], DI[24]); + buf b_di_25 (di_in[25], DI[25]); + buf b_di_26 (di_in[26], DI[26]); + buf b_di_27 (di_in[27], DI[27]); + buf b_di_28 (di_in[28], DI[28]); + buf b_di_29 (di_in[29], DI[29]); + buf b_di_30 (di_in[30], DI[30]); + buf b_di_31 (di_in[31], DI[31]); + buf b_dip_0 (dip_in[0], DIP[0]); + buf b_dip_1 (dip_in[1], DIP[1]); + buf b_dip_2 (dip_in[2], DIP[2]); + buf b_dip_3 (dip_in[3], DIP[3]); + + buf b_do_out0 (do_out0, do_out_out[0]); + buf b_do_out1 (do_out1, do_out_out[1]); + buf b_do_out2 (do_out2, do_out_out[2]); + buf b_do_out3 (do_out3, do_out_out[3]); + buf b_do_out4 (do_out4, do_out_out[4]); + buf b_do_out5 (do_out5, do_out_out[5]); + buf b_do_out6 (do_out6, do_out_out[6]); + buf b_do_out7 (do_out7, do_out_out[7]); + buf b_do_out8 (do_out8, do_out_out[8]); + buf b_do_out9 (do_out9, do_out_out[9]); + buf b_do_out10 (do_out10, do_out_out[10]); + buf b_do_out11 (do_out11, do_out_out[11]); + buf b_do_out12 (do_out12, do_out_out[12]); + buf b_do_out13 (do_out13, do_out_out[13]); + buf b_do_out14 (do_out14, do_out_out[14]); + buf b_do_out15 (do_out15, do_out_out[15]); + buf b_do_out16 (do_out16, do_out_out[16]); + buf b_do_out17 (do_out17, do_out_out[17]); + buf b_do_out18 (do_out18, do_out_out[18]); + buf b_do_out19 (do_out19, do_out_out[19]); + buf b_do_out20 (do_out20, do_out_out[20]); + buf b_do_out21 (do_out21, do_out_out[21]); + buf b_do_out22 (do_out22, do_out_out[22]); + buf b_do_out23 (do_out23, do_out_out[23]); + buf b_do_out24 (do_out24, do_out_out[24]); + buf b_do_out25 (do_out25, do_out_out[25]); + buf b_do_out26 (do_out26, do_out_out[26]); + buf b_do_out27 (do_out27, do_out_out[27]); + buf b_do_out28 (do_out28, do_out_out[28]); + buf b_do_out29 (do_out29, do_out_out[29]); + buf b_do_out30 (do_out30, do_out_out[30]); + buf b_do_out31 (do_out31, do_out_out[31]); + buf b_dop_out0 (dop_out0, dop_out_out[0]); + buf b_dop_out1 (dop_out1, dop_out_out[1]); + buf b_dop_out2 (dop_out2, dop_out_out[2]); + buf b_dop_out3 (dop_out3, dop_out_out[3]); + + buf b_do0 (DO[0], do_out0); + buf b_do1 (DO[1], do_out1); + buf b_do2 (DO[2], do_out2); + buf b_do3 (DO[3], do_out3); + buf b_do4 (DO[4], do_out4); + buf b_do5 (DO[5], do_out5); + buf b_do6 (DO[6], do_out6); + buf b_do7 (DO[7], do_out7); + buf b_do8 (DO[8], do_out8); + buf b_do9 (DO[9], do_out9); + buf b_do10 (DO[10], do_out10); + buf b_do11 (DO[11], do_out11); + buf b_do12 (DO[12], do_out12); + buf b_do13 (DO[13], do_out13); + buf b_do14 (DO[14], do_out14); + buf b_do15 (DO[15], do_out15); + buf b_do16 (DO[16], do_out16); + buf b_do17 (DO[17], do_out17); + buf b_do18 (DO[18], do_out18); + buf b_do19 (DO[19], do_out19); + buf b_do20 (DO[20], do_out20); + buf b_do21 (DO[21], do_out21); + buf b_do22 (DO[22], do_out22); + buf b_do23 (DO[23], do_out23); + buf b_do24 (DO[24], do_out24); + buf b_do25 (DO[25], do_out25); + buf b_do26 (DO[26], do_out26); + buf b_do27 (DO[27], do_out27); + buf b_do28 (DO[28], do_out28); + buf b_do29 (DO[29], do_out29); + buf b_do30 (DO[30], do_out30); + buf b_do31 (DO[31], do_out31); + buf b_dop0 (DOP[0], dop_out0); + buf b_dop1 (DOP[1], dop_out1); + buf b_dop2 (DOP[2], dop_out2); + buf b_dop3 (DOP[3], dop_out3); + + buf b_in3 (rdclk_in, RDCLK); + buf b_in0 (rden_in, RDEN); + buf b_in4 (rst_in, RST); + buf b_in2 (wrclk_in, WRCLK); + buf b_in1 (wren_in, WREN); + buf b_in5 (gsr_in, GSR); + + buf b_out0 (ALMOSTEMPTY, almostempty_out); + buf b_out1 (ALMOSTFULL, almostfull_out); + buf b_out2 (EMPTY, empty_out); + buf b_out3 (FULL, full_out); + buf b_out4 (RDERR, rderr_out); + buf b_out5 (WRERR, wrerr_out); + + buf b_rdcount_out0 (rdcount_out0, rdcount_out_out[0]); + buf b_rdcount_out1 (rdcount_out1, rdcount_out_out[1]); + buf b_rdcount_out2 (rdcount_out2, rdcount_out_out[2]); + buf b_rdcount_out3 (rdcount_out3, rdcount_out_out[3]); + buf b_rdcount_out4 (rdcount_out4, rdcount_out_out[4]); + buf b_rdcount_out5 (rdcount_out5, rdcount_out_out[5]); + buf b_rdcount_out6 (rdcount_out6, rdcount_out_out[6]); + buf b_rdcount_out7 (rdcount_out7, rdcount_out_out[7]); + buf b_rdcount_out8 (rdcount_out8, rdcount_out_out[8]); + buf b_rdcount_out9 (rdcount_out9, rdcount_out_out[9]); + buf b_rdcount_out10 (rdcount_out10, rdcount_out_out[10]); + buf b_rdcount_out11 (rdcount_out11, rdcount_out_out[11]); + buf b_rdcount0 (RDCOUNT[0], rdcount_out0); + buf b_rdcount1 (RDCOUNT[1], rdcount_out1); + buf b_rdcount2 (RDCOUNT[2], rdcount_out2); + buf b_rdcount3 (RDCOUNT[3], rdcount_out3); + buf b_rdcount4 (RDCOUNT[4], rdcount_out4); + buf b_rdcount5 (RDCOUNT[5], rdcount_out5); + buf b_rdcount6 (RDCOUNT[6], rdcount_out6); + buf b_rdcount7 (RDCOUNT[7], rdcount_out7); + buf b_rdcount8 (RDCOUNT[8], rdcount_out8); + buf b_rdcount9 (RDCOUNT[9], rdcount_out9); + buf b_rdcount10 (RDCOUNT[10], rdcount_out10); + buf b_rdcount11 (RDCOUNT[11], rdcount_out11); + buf b_wrcount_out0 (wrcount_out0, wr_addr_out[0]); + buf b_wrcount_out1 (wrcount_out1, wr_addr_out[1]); + buf b_wrcount_out2 (wrcount_out2, wr_addr_out[2]); + buf b_wrcount_out3 (wrcount_out3, wr_addr_out[3]); + buf b_wrcount_out4 (wrcount_out4, wr_addr_out[4]); + buf b_wrcount_out5 (wrcount_out5, wr_addr_out[5]); + buf b_wrcount_out6 (wrcount_out6, wr_addr_out[6]); + buf b_wrcount_out7 (wrcount_out7, wr_addr_out[7]); + buf b_wrcount_out8 (wrcount_out8, wr_addr_out[8]); + buf b_wrcount_out9 (wrcount_out9, wr_addr_out[9]); + buf b_wrcount_out10 (wrcount_out10, wr_addr_out[10]); + buf b_wrcount_out11 (wrcount_out11, wr_addr_out[11]); + buf b_wrcount0 (WRCOUNT[0], wrcount_out0); + buf b_wrcount1 (WRCOUNT[1], wrcount_out1); + buf b_wrcount2 (WRCOUNT[2], wrcount_out2); + buf b_wrcount3 (WRCOUNT[3], wrcount_out3); + buf b_wrcount4 (WRCOUNT[4], wrcount_out4); + buf b_wrcount5 (WRCOUNT[5], wrcount_out5); + buf b_wrcount6 (WRCOUNT[6], wrcount_out6); + buf b_wrcount7 (WRCOUNT[7], wrcount_out7); + buf b_wrcount8 (WRCOUNT[8], wrcount_out8); + buf b_wrcount9 (WRCOUNT[9], wrcount_out9); + buf b_wrcount10 (WRCOUNT[10], wrcount_out10); + buf b_wrcount11 (WRCOUNT[11], wrcount_out11); + + always @(gsr_in) + if (gsr_in == 1'b1) begin + assign do_out = 32'b00000000000000000000000000000000; + assign dop_out = 4'b0000; + end + else if (gsr_in == 1'b0) begin + deassign do_out; + deassign dop_out; + end + + always @(gsr_in or rst_in) + if (gsr_in == 1'b1 || rst_in == 1'b1) begin + assign almostempty_int = 4'b1111; + assign almostempty_out = 1'b1; + assign almostfull_int = 4'b0000; + assign almostfull_out = 1'b0; + assign do_in = 32'b00000000000000000000000000000000; + assign dop_in = 4'b0000; + assign empty_ram = 4'b1111; + assign empty_out = 1'b1; + assign full_int = 4'b0000; + assign full_out = 1'b0; + assign rdcount_out = 12'b0; + assign rderr_out = 0; + assign wrerr_out = 0; + assign rd_addr = 0; + assign rd_prefetch = 0; + assign wr_addr = 0; + assign wr1_addr = 0; + assign rdcount_flag = 0; + assign rd_flag = 0; + assign rdprefetch_flag = 0; + assign wr_flag = 0; + assign wr1_flag = 0; + end + else if (gsr_in == 1'b0 && rst_in == 1'b0) begin + deassign almostempty_int; + deassign almostempty_out; + deassign almostfull_int; + deassign almostfull_out; + deassign do_in; + deassign dop_in; + deassign empty_ram; + deassign empty_out; + deassign full_int; + deassign full_out; + deassign rdcount_out; + deassign rderr_out; + deassign wrerr_out; + deassign rd_addr; + deassign rd_prefetch; + deassign wr_addr; + deassign wr1_addr; + deassign rdcount_flag; + deassign rd_flag; + deassign rdprefetch_flag; + deassign wr_flag; + deassign wr1_flag; + end + + initial begin + almostempty_int = 4'b1111; + almostempty_out = 1'b1; + almostfull_int = 4'b0000; + almostfull_out = 1'b0; + do_in = 32'b00000000000000000000000000000000; + do_out = 32'b00000000000000000000000000000000; + dop_in = 4'b0000; + dop_out = 4'b0000; + empty_ram = 4'b1111; + empty_out = 1'b1; + full_int = 4'b0000; + full_out = 1'b0; + rdcount_out = 12'b0; + rderr_out = 0; + wrerr_out = 0; + + rd_addr = 0; + rd_prefetch = 0; + wr_addr = 0; + wr1_addr = 0; + rdcount_flag = 0; + rd_flag = 0; + rdprefetch_flag = 0; + wr_flag = 0; + wr1_flag = 0; + rst_wrckreg = 3'b0; + rst_rdckreg = 3'b0; + rst_tmp1 = 0; + rst_tmp2 = 0; + + case (DATA_WIDTH) + 4 : begin + addr_limit = 4096; + d_w = 4; + p_w = 0; + end + 9 : begin + addr_limit = 2048; + d_w = 8; + p_w = 1; + end + 18 : begin + addr_limit = 1024; + d_w = 16; + p_w = 2; + end + 36 : begin + addr_limit = 512; + d_w = 32; + p_w = 4; + end + default : + begin + $display("Attribute Syntax Error : The attribute DATA_WIDTH on FIFO16 instance %m is set to %d. Legal values for this attribute are 4, 9, 18 or 36.", DATA_WIDTH); + $finish; + end + endcase + + case (FIRST_WORD_FALL_THROUGH) + "FALSE" : begin + fwft = 0; + ae_empty = ALMOST_EMPTY_OFFSET - 1; + end + "TRUE" : begin + fwft = 1; + ae_empty = ALMOST_EMPTY_OFFSET - 2; + end + default : begin + $display("Attribute Syntax Error : The attribute FIRST_WORD_FALL_THROUGH on FIFO16 instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", FIRST_WORD_FALL_THROUGH); + $finish; + end + endcase + + if ((fwft == 1'b0) && ((ALMOST_EMPTY_OFFSET < 5) || (ALMOST_EMPTY_OFFSET > addr_limit - 4))) + $display("Attribute Syntax Error : The attribute ALMOST_EMPTY_OFFSET on FIFO16 instance %m is set to %d. Legal values for this attribute are %d to %d", ALMOST_EMPTY_OFFSET, 5, addr_limit - 4); + if ((fwft == 1'b0) && ((ALMOST_FULL_OFFSET < 4) || (ALMOST_FULL_OFFSET > addr_limit - 5))) + $display("Attribute Syntax Error : The attribute ALMOST_FULL_OFFSET on FIFO16 instance %m is set to %d. Legal values for this attribute are %d to %d", ALMOST_FULL_OFFSET, 4, addr_limit - 5); + + if ((fwft == 1'b1) && ((ALMOST_EMPTY_OFFSET < 6) || (ALMOST_EMPTY_OFFSET > addr_limit - 3))) + $display("Attribute Syntax Error : The attribute ALMOST_EMPTY_OFFSET on FIFO16 instance %m is set to %d. Legal values for this attribute are %d to %d", ALMOST_EMPTY_OFFSET, 6, addr_limit - 3); + if ((fwft == 1'b1) && ((ALMOST_FULL_OFFSET < 4) || (ALMOST_FULL_OFFSET > addr_limit - 5))) + $display("Attribute Syntax Error : The attribute ALMOST_FULL_OFFSET on FIFO16 instance %m is set to %d. Legal values for this attribute are %d to %d", ALMOST_FULL_OFFSET, 4, addr_limit - 5); + end + + always @(rst_in or rden_in or wren_in) begin + if (rst_in ==1 && rden_in==1 ) + $display("Warning : At time %t, RDEN on FIFO16 instance %m is high when RST is high. RDEN should be low during reset.", $stime); + if (rst_in ==1 && wren_in ==1) + $display("Warning : At time %t, WREN on FIFO16 instance %m is high when RST is high. WREN should be low during reset.", $stime); + end + + always @(posedge rdclk_in) begin + rst_rdckreg[0] <= rst_in; + rst_rdckreg[1] <= rst_rdckreg[0] & rst_in; + rst_rdckreg[2] <= rst_rdckreg[1] & rst_in; + end + + always @(posedge wrclk_in) begin + rst_wrckreg[0] <= rst_in ; + rst_wrckreg[1] <= rst_wrckreg[0] & rst_in; + rst_wrckreg[2] <= rst_wrckreg[1] & rst_in; + end + + always @(rst_in) + begin + rst_tmp1 = rst_in; + rst_rdclk_flag = 0; + rst_wrclk_flag = 0; + + if (rst_tmp1 == 0 && rst_tmp2 == 1) begin + if ((rst_rdckreg[2] & rst_rdckreg[1] & rst_rdckreg[0]) == 0) begin + $display("Error : At time %t, RST high on FIFO16 instance %m is short than three RDCLK clock cycles. RST high need be more that three RDCLK clock cycles.", $stime); + rst_rdclk_flag = 1; + end + + if ((rst_wrckreg[2] & rst_wrckreg[1] & rst_wrckreg[0]) == 0) begin + $display("Error : At time %t, RST high on FIFO16 instance %m is short than three WRCLK clock cycles. RST high need be more that three WRCLK clock cycles.", $stime); + rst_wrclk_flag = 1; + end + + if ((rst_rdclk_flag | rst_wrclk_flag) == 1) begin + assign do_out = 32'bx; + assign dop_out = 4'bx; + assign full_out = 1'bX; + assign empty_out = 1'bX; + assign rderr_out = 1'bX; + assign wrerr_out = 1'bX; + assign rdcount_out = 12'bx; + assign wr_addr = 12'bx; + assign wr1_addr = 0; + assign almostempty_int = 4'b1111; + assign almostempty_out = 1'bx; + assign almostfull_int = 4'b0000; + assign almostfull_out = 1'bx; + assign do_in = 32'b00000000000000000000000000000000; + assign dop_in = 4'b0000; + assign empty_ram = 4'b1111; + assign full_int = 4'b0000; + assign rd_addr = 0; + assign rd_prefetch = 0; + assign rdcount_flag = 0; + assign rd_flag = 0; + assign rdprefetch_flag = 0; + assign wr_flag = 0; + assign wr1_flag = 0; + end + else begin + deassign do_out; + deassign dop_out; + deassign full_out; + deassign empty_out; + deassign rderr_out; + deassign wrerr_out; + deassign rdcount_out; + rdcount_out = 13'b0; + deassign wr_addr; + wr_addr = 13'b0; + deassign wr1_addr; + deassign almostempty_int; + deassign almostempty_out; + deassign almostfull_int; + deassign almostfull_out; + deassign do_in; + deassign dop_in; + deassign empty_ram; + deassign full_int; + deassign rd_addr; + deassign rd_prefetch; + deassign rdcount_flag; + deassign rd_flag; + deassign rdprefetch_flag; + deassign wr_flag; + deassign wr1_flag; + end + end + rst_tmp2 = rst_tmp1; + end + + + always @(posedge rdclk_in) begin + rden_reg = rden_in; + if (fwft == 1'b0) begin + if ((rden_reg == 1'b1) && (rd_addr != rdcount_out)) begin + do_out = do_in; + dop_out = dop_in; + rd_addr = (rd_addr + 1) % addr_limit; + if (rd_addr == 0) + rd_flag = ~rd_flag; + end + if (((rd_addr == rdcount_out) && (empty_ram[3] == 1'b0)) || + ((rden_reg == 1'b1) && (empty_ram[1] == 1'b0))) begin + for (i = 0; i < d_w; i = i + 1) begin + do_in[i] = mem[rdcount_out * d_w + i]; + end + for (i = 0; i < p_w; i = i + 1) begin + dop_in[i] = memp[rdcount_out * p_w + i]; + end + #1; + rdcount_out = (rdcount_out + 1) % addr_limit; + if (rdcount_out == 0) begin + rdcount_flag = ~rdcount_flag; + end + end + end + + if (fwft == 1'b1) begin + if ((rden_reg == 1'b1) && (rd_addr != rd_prefetch)) begin + rd_prefetch = (rd_prefetch + 1) % addr_limit; + if (rd_prefetch == 0) + rdprefetch_flag = ~rdprefetch_flag; + end + if ((rd_prefetch == rd_addr) && (rd_addr != rdcount_out)) begin + do_out = do_in; + dop_out = dop_in; + rd_addr = (rd_addr + 1) % addr_limit; + if (rd_addr == 0) + rd_flag = ~rd_flag; + end + if (((rd_addr == rdcount_out) && (empty_ram[3] == 1'b0)) || + ((rden_reg == 1'b1) && (empty_ram[1] == 1'b0)) || + ((rden_reg == 1'b0) && (empty_ram[1] == 1'b0) && (rd_addr == rdcount_out))) begin + for (i = 0; i < d_w; i = i + 1) begin + do_in[i] = mem[rdcount_out * d_w + i]; + end + for (i = 0; i < p_w; i = i + 1) begin + dop_in[i] = memp[rdcount_out * p_w + i]; + end + #1; + rdcount_out = (rdcount_out + 1) % addr_limit; + if (rdcount_out == 0) + rdcount_flag = ~rdcount_flag; + end + end + + rderr_out = (rden_reg == 1'b1) && (empty_out == 1'b1); + + almostempty_out = almostempty_int[3]; + if ((((rdcount_out + ae_empty) >= wr_addr) && (rdcount_flag == wr_flag)) || (((rdcount_out + ae_empty) >= (wr_addr + addr_limit)) && (rdcount_flag != wr_flag))) begin + almostempty_int[3] = 1'b1; + almostempty_int[2] = 1'b1; + almostempty_int[1] = 1'b1; + almostempty_int[0] = 1'b1; + end + else if (almostempty_int[2] == 1'b0) begin + almostempty_int[3] = almostempty_int[0]; + almostempty_int[0] = 1'b0; + end + + if ((((rdcount_out + addr_limit) > (wr_addr + ALMOST_FULL_OFFSET)) && (rdcount_flag == wr_flag)) || ((rdcount_out > (wr_addr + ALMOST_FULL_OFFSET)) && (rdcount_flag != wr_flag))) begin + if (((rden_reg == 1'b1) && (empty_out == 1'b0)) || ((((rd_addr + 1) % addr_limit) == rdcount_out) && (almostfull_int[1] == 1'b1))) begin + almostfull_int[2] = almostfull_int[1]; + almostfull_int[1] = 1'b0; + end + end + else begin + almostfull_int[2] = 1'b1; + almostfull_int[1] = 1'b1; + end + + if (fwft == 1'b0) begin + if ((rdcount_out == rd_addr) && (rdcount_flag == rd_flag)) begin + empty_out = 1'b1; + end + else begin + empty_out = 1'b0; + end + end + else if (fwft == 1'b1) begin + if ((rd_prefetch == rd_addr) && (rdprefetch_flag == rd_flag)) begin + empty_out = 1'b1; + end + else begin + empty_out = 1'b0; + end + end + + if ((rdcount_out == wr_addr) && (rdcount_flag == wr_flag)) begin + empty_ram[2] = 1'b1; + empty_ram[1] = 1'b1; + empty_ram[0] = 1'b1; + end + else begin + empty_ram[2] = empty_ram[1]; + empty_ram[1] = empty_ram[0]; + empty_ram[0] = 1'b0; + end + + if ((rdcount_out == wr1_addr) && (rdcount_flag == wr1_flag)) begin + empty_ram[3] = 1'b1; + end + else begin + empty_ram[3] = 1'b0; + end + + wr1_addr = wr_addr; + wr1_flag = wr_flag; + end + + always @(posedge wrclk_in) begin + wren_reg = wren_in; + if (wren_reg == 1'b1 && (full_int[1] == 1'b0)) begin + for (j = 0; j < d_w; j = j + 1) begin + mem[wr_addr * d_w + j] = di_in[j]; + end + for (j = 0; j < p_w; j = j + 1) begin + memp[wr_addr * p_w + j] = dip_in[j]; + end + #1; + wr_addr = (wr_addr + 1) % addr_limit; + if (wr_addr == 0) + wr_flag = ~wr_flag; + end + wrerr_out = (wren_reg == 1'b1) && (full_int[1] == 1'b1); + + almostfull_out = almostfull_int[3]; + if ((((rdcount_out + addr_limit) <= (wr_addr + ALMOST_FULL_OFFSET)) && (rdcount_flag == wr_flag)) || ((rdcount_out <= (wr_addr + ALMOST_FULL_OFFSET)) && (rdcount_flag != wr_flag))) begin + almostfull_int[3] = 1'b1; + almostfull_int[2] = 1'b1; + almostfull_int[1] = 1'b1; + almostfull_int[0] = 1'b1; + end + else if (almostfull_int[2] == 1'b0) begin + almostfull_int[3] = almostfull_int[0]; + almostfull_int[0] = 1'b0; + end + + if ((((rdcount_out + ae_empty) < wr_addr) && (rdcount_flag == wr_flag)) || (((rdcount_out + ae_empty) < (wr_addr + addr_limit)) && (rdcount_flag != wr_flag))) begin + if (wren_reg == 1'b1) begin + almostempty_int[2] = almostempty_int[1]; + almostempty_int[1] = 1'b0; + end + end + else begin + almostempty_int[2] = 1'b1; + almostempty_int[1] = 1'b1; + end + + full_out = full_int[1]; + if ((rdcount_out == wr_addr) && (rdcount_flag != wr_flag)) begin + full_int[1] = 1'b1; + full_int[0] = 1'b1; + end + else begin + full_int[1] = full_int[0]; + full_int[0] = 0; + end + end + + + // matching HW behavior to X the unused output bits + assign do_out_out = (DATA_WIDTH == 4) ? {28'bx, do_out[3:0]} + : (DATA_WIDTH == 9) ? {24'bx, do_out[7:0]} + : (DATA_WIDTH == 18) ? {16'bx, do_out[15:0]} + : (DATA_WIDTH == 36) ? do_out + : do_out; + + // matching HW behavior to X the unused output bits + assign dop_out_out = (DATA_WIDTH == 9) ? {3'bx, dop_out[0:0]} + : (DATA_WIDTH == 18) ? {2'bx, dop_out[1:0]} + : (DATA_WIDTH == 36) ? dop_out + : 4'bx; + + // matching HW behavior to pull up the unused output bits + always @(wr_addr) begin + + case (DATA_WIDTH) + 4 : wr_addr_out = wr_addr; + 9 : wr_addr_out[10:0] = wr_addr; + 18 : wr_addr_out[9:0] = wr_addr; + 36 : wr_addr_out[8:0] = wr_addr; + default : wr_addr_out = wr_addr; + endcase + end // always @ (wr_addr) + + + // matching HW behavior to pull up the unused output bits + always @(rdcount_out) begin + + case (DATA_WIDTH) + 4 : rdcount_out_out = rdcount_out; + 9 : rdcount_out_out[10:0] = rdcount_out; + 18 : rdcount_out_out[9:0] = rdcount_out; + 36 : rdcount_out_out[8:0] = rdcount_out; + default : rdcount_out_out = rdcount_out; + endcase + end // always @ (rdcount_out) + + +//*** Timing Checks Start here + + always @(notifier) begin + do_out <= 32'bx; + dop_out <= 4'bx; + end + + + specify + + (RDCLK => ALMOSTEMPTY) = (100:100:100, 100:100:100); + (RDCLK => DOP[0]) = (100:100:100, 100:100:100); + (RDCLK => DOP[1]) = (100:100:100, 100:100:100); + (RDCLK => DOP[2]) = (100:100:100, 100:100:100); + (RDCLK => DOP[3]) = (100:100:100, 100:100:100); + (RDCLK => DO[0]) = (100:100:100, 100:100:100); + (RDCLK => DO[10]) = (100:100:100, 100:100:100); + (RDCLK => DO[11]) = (100:100:100, 100:100:100); + (RDCLK => DO[12]) = (100:100:100, 100:100:100); + (RDCLK => DO[13]) = (100:100:100, 100:100:100); + (RDCLK => DO[14]) = (100:100:100, 100:100:100); + (RDCLK => DO[15]) = (100:100:100, 100:100:100); + (RDCLK => DO[16]) = (100:100:100, 100:100:100); + (RDCLK => DO[17]) = (100:100:100, 100:100:100); + (RDCLK => DO[18]) = (100:100:100, 100:100:100); + (RDCLK => DO[19]) = (100:100:100, 100:100:100); + (RDCLK => DO[1]) = (100:100:100, 100:100:100); + (RDCLK => DO[20]) = (100:100:100, 100:100:100); + (RDCLK => DO[21]) = (100:100:100, 100:100:100); + (RDCLK => DO[22]) = (100:100:100, 100:100:100); + (RDCLK => DO[23]) = (100:100:100, 100:100:100); + (RDCLK => DO[24]) = (100:100:100, 100:100:100); + (RDCLK => DO[25]) = (100:100:100, 100:100:100); + (RDCLK => DO[26]) = (100:100:100, 100:100:100); + (RDCLK => DO[27]) = (100:100:100, 100:100:100); + (RDCLK => DO[28]) = (100:100:100, 100:100:100); + (RDCLK => DO[29]) = (100:100:100, 100:100:100); + (RDCLK => DO[2]) = (100:100:100, 100:100:100); + (RDCLK => DO[30]) = (100:100:100, 100:100:100); + (RDCLK => DO[31]) = (100:100:100, 100:100:100); + (RDCLK => DO[3]) = (100:100:100, 100:100:100); + (RDCLK => DO[4]) = (100:100:100, 100:100:100); + (RDCLK => DO[5]) = (100:100:100, 100:100:100); + (RDCLK => DO[6]) = (100:100:100, 100:100:100); + (RDCLK => DO[7]) = (100:100:100, 100:100:100); + (RDCLK => DO[8]) = (100:100:100, 100:100:100); + (RDCLK => DO[9]) = (100:100:100, 100:100:100); + (RDCLK => EMPTY) = (100:100:100, 100:100:100); + (RDCLK => RDCOUNT[0]) = (100:100:100, 100:100:100); + (RDCLK => RDCOUNT[10]) = (100:100:100, 100:100:100); + (RDCLK => RDCOUNT[11]) = (100:100:100, 100:100:100); + (RDCLK => RDCOUNT[1]) = (100:100:100, 100:100:100); + (RDCLK => RDCOUNT[2]) = (100:100:100, 100:100:100); + (RDCLK => RDCOUNT[3]) = (100:100:100, 100:100:100); + (RDCLK => RDCOUNT[4]) = (100:100:100, 100:100:100); + (RDCLK => RDCOUNT[5]) = (100:100:100, 100:100:100); + (RDCLK => RDCOUNT[6]) = (100:100:100, 100:100:100); + (RDCLK => RDCOUNT[7]) = (100:100:100, 100:100:100); + (RDCLK => RDCOUNT[8]) = (100:100:100, 100:100:100); + (RDCLK => RDCOUNT[9]) = (100:100:100, 100:100:100); + (RDCLK => RDERR) = (100:100:100, 100:100:100); + (WRCLK => ALMOSTFULL) = (100:100:100, 100:100:100); + (WRCLK => FULL) = (100:100:100, 100:100:100); + (WRCLK => WRCOUNT[0]) = (100:100:100, 100:100:100); + (WRCLK => WRCOUNT[10]) = (100:100:100, 100:100:100); + (WRCLK => WRCOUNT[11]) = (100:100:100, 100:100:100); + (WRCLK => WRCOUNT[1]) = (100:100:100, 100:100:100); + (WRCLK => WRCOUNT[2]) = (100:100:100, 100:100:100); + (WRCLK => WRCOUNT[3]) = (100:100:100, 100:100:100); + (WRCLK => WRCOUNT[4]) = (100:100:100, 100:100:100); + (WRCLK => WRCOUNT[5]) = (100:100:100, 100:100:100); + (WRCLK => WRCOUNT[6]) = (100:100:100, 100:100:100); + (WRCLK => WRCOUNT[7]) = (100:100:100, 100:100:100); + (WRCLK => WRCOUNT[8]) = (100:100:100, 100:100:100); + (WRCLK => WRCOUNT[9]) = (100:100:100, 100:100:100); + (WRCLK => WRERR) = (100:100:100, 100:100:100); + + specparam PATHPULSE$ = 0; + + endspecify + +endmodule diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/FIFO18.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/FIFO18.v new file mode 100644 index 0000000..736d96d --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/FIFO18.v @@ -0,0 +1,142 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/rainier/FIFO18.v,v 1.12 2007/06/15 20:58:41 wloo Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2005 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / 18K-Bit FIFO +// /___/ /\ Filename : FIFO18.v +// \ \ / \ Timestamp : Tues July 26 16:44:06 PST 2005 +// \___\/\___\ +// +// Revision: +// 07/26/05 - Initial version. +// 06/14/07 - Implemented high performace version of the model. +// End Revision + +`timescale 1 ps/1 ps + +module FIFO18 (ALMOSTEMPTY, ALMOSTFULL, DO, DOP, EMPTY, FULL, RDCOUNT, RDERR, WRCOUNT, WRERR, + DI, DIP, RDCLK, RDEN, RST, WRCLK, WREN); + + parameter ALMOST_EMPTY_OFFSET = 12'h080; + parameter ALMOST_FULL_OFFSET = 12'h080; + parameter integer DATA_WIDTH = 4; + parameter integer DO_REG = 1; + parameter EN_SYN = "FALSE"; + parameter FIRST_WORD_FALL_THROUGH = "FALSE"; + parameter SIM_MODE = "SAFE"; + + output ALMOSTEMPTY; + output ALMOSTFULL; + output [15:0] DO; + output [1:0] DOP; + output EMPTY; + output FULL; + output [11:0] RDCOUNT; + output RDERR; + output [11:0] WRCOUNT; + output WRERR; + + input [15:0] DI; + input [1:0] DIP; + input RDCLK; + input RDEN; + input RST; + input WRCLK; + input WREN; + + tri0 GSR = glbl.GSR; + + wire [47:0] dangle_out48; + wire [5:0] dangle_out6; + wire [7:0] dangle_out8; + wire dangle_out; + + + initial begin + + case (DATA_WIDTH) + 4, 9, 18 : ; + default : + begin + $display("Attribute Syntax Error : The attribute DATA_WIDTH on FIFO18 instance %m is set to %d. Legal values for this attribute are 4, 9 or 18.", DATA_WIDTH); + $finish; + end + endcase // case(DATA_WIDTH) + + end // initial begin + + + AFIFO36_INTERNAL INT_FIFO (.ALMOSTEMPTY(ALMOSTEMPTY), .ALMOSTFULL(ALMOSTFULL), .DBITERR(dangle_out), .DO({dangle_out48,DO}), .DOP({dangle_out6,DOP}), .ECCPARITY(dangle_out8), .EMPTY(EMPTY), .FULL(FULL), .RDCOUNT({dangle_out,RDCOUNT}), .RDERR(RDERR), .SBITERR(dangle_out), .WRCOUNT({dangle_out,WRCOUNT}), .WRERR(WRERR), .DI({48'b0,DI}), .DIP({6'b0,DIP}), .RDCLK(RDCLK), .RDEN(RDEN), .RDRCLK(RDCLK), .RST(RST), .WRCLK(WRCLK), .WREN(WREN)); + + defparam INT_FIFO.FIFO_SIZE = 18; + defparam INT_FIFO.ALMOST_EMPTY_OFFSET = ALMOST_EMPTY_OFFSET; + defparam INT_FIFO.ALMOST_FULL_OFFSET = ALMOST_FULL_OFFSET; + defparam INT_FIFO.DATA_WIDTH = DATA_WIDTH; + defparam INT_FIFO.DO_REG = DO_REG; + defparam INT_FIFO.EN_SYN = EN_SYN; + defparam INT_FIFO.FIRST_WORD_FALL_THROUGH = FIRST_WORD_FALL_THROUGH; + defparam INT_FIFO.SIM_MODE = SIM_MODE; + + specify + + (RDCLK => ALMOSTEMPTY) = (100, 100); + (RDCLK => DOP[0]) = (100, 100); + (RDCLK => DOP[1]) = (100, 100); + (RDCLK => DO[0]) = (100, 100); + (RDCLK => DO[10]) = (100, 100); + (RDCLK => DO[11]) = (100, 100); + (RDCLK => DO[12]) = (100, 100); + (RDCLK => DO[13]) = (100, 100); + (RDCLK => DO[14]) = (100, 100); + (RDCLK => DO[15]) = (100, 100); + (RDCLK => DO[1]) = (100, 100); + (RDCLK => DO[2]) = (100, 100); + (RDCLK => DO[3]) = (100, 100); + (RDCLK => DO[4]) = (100, 100); + (RDCLK => DO[5]) = (100, 100); + (RDCLK => DO[6]) = (100, 100); + (RDCLK => DO[7]) = (100, 100); + (RDCLK => DO[8]) = (100, 100); + (RDCLK => DO[9]) = (100, 100); + (RDCLK => EMPTY) = (100, 100); + (RDCLK => RDCOUNT[0]) = (100, 100); + (RDCLK => RDCOUNT[10]) = (100, 100); + (RDCLK => RDCOUNT[11]) = (100, 100); + (RDCLK => RDCOUNT[1]) = (100, 100); + (RDCLK => RDCOUNT[2]) = (100, 100); + (RDCLK => RDCOUNT[3]) = (100, 100); + (RDCLK => RDCOUNT[4]) = (100, 100); + (RDCLK => RDCOUNT[5]) = (100, 100); + (RDCLK => RDCOUNT[6]) = (100, 100); + (RDCLK => RDCOUNT[7]) = (100, 100); + (RDCLK => RDCOUNT[8]) = (100, 100); + (RDCLK => RDCOUNT[9]) = (100, 100); + (RDCLK => RDERR) = (100, 100); + + (WRCLK => ALMOSTFULL) = (100, 100); + (WRCLK => FULL) = (100, 100); + (WRCLK => WRCOUNT[0]) = (100, 100); + (WRCLK => WRCOUNT[10]) = (100, 100); + (WRCLK => WRCOUNT[11]) = (100, 100); + (WRCLK => WRCOUNT[1]) = (100, 100); + (WRCLK => WRCOUNT[2]) = (100, 100); + (WRCLK => WRCOUNT[3]) = (100, 100); + (WRCLK => WRCOUNT[4]) = (100, 100); + (WRCLK => WRCOUNT[5]) = (100, 100); + (WRCLK => WRCOUNT[6]) = (100, 100); + (WRCLK => WRCOUNT[7]) = (100, 100); + (WRCLK => WRCOUNT[8]) = (100, 100); + (WRCLK => WRCOUNT[9]) = (100, 100); + (WRCLK => WRERR) = (100, 100); + + specparam PATHPULSE$ = 0; + + endspecify + +endmodule // FIFO18 diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/FIFO18E1.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/FIFO18E1.v new file mode 100644 index 0000000..beb3205 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/FIFO18E1.v @@ -0,0 +1,1681 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/blanc/FIFO18E1.v,v 1.14 2009/11/19 21:57:25 wloo Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2008 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / 18K-Bit FIFO +// /___/ /\ Filename : FIFO18E1.v +// \ \ / \ Timestamp : Tue Mar 18 16:55:14 PDT 2008 +// \___\/\___\ +// +// Revision: +// 03/18/08 - Initial version. +// 07/10/08 - IR476500 Add INIT parameter support, sync with FIFO36 internal +// 08/22/08 - Updated SRVAL and INIT port mapping for FIFO_MODE = FIFO18_36. (IR 479958) +// 08/26/08 - Updated unused bit on wrcount and rdcount to match the hardware. +// 04/02/09 - Implemented DRC for FIFO_MODE (CR 517127). +// 10/07/09 - Fixed reset behavior (CR 532794). +// 10/23/09 - Fixed RST and RSTREG (CR 537067). +// End Revision + +`timescale 1 ps/1 ps + +module FIFO18E1 (ALMOSTEMPTY, ALMOSTFULL, DO, DOP, EMPTY, FULL, RDCOUNT, RDERR, WRCOUNT, WRERR, + DI, DIP, RDCLK, RDEN, REGCE, RST, RSTREG, WRCLK, WREN); + + parameter ALMOST_EMPTY_OFFSET = 13'h0080; + parameter ALMOST_FULL_OFFSET = 13'h0080; + parameter integer DATA_WIDTH = 4; + parameter integer DO_REG = 1; + parameter EN_SYN = "FALSE"; + parameter FIFO_MODE = "FIFO18"; + parameter FIRST_WORD_FALL_THROUGH = "FALSE"; + parameter INIT = 36'h0; + parameter SRVAL = 36'h0; + + output ALMOSTEMPTY; + output ALMOSTFULL; + output [31:0] DO; + output [3:0] DOP; + output EMPTY; + output FULL; + output [11:0] RDCOUNT; + output RDERR; + output [11:0] WRCOUNT; + output WRERR; + + input [31:0] DI; + input [3:0] DIP; + input RDCLK; + input RDEN; + input REGCE; + input RST; + input RSTREG; + input WRCLK; + input WREN; + + tri0 GSR = glbl.GSR; + + wire dangle_out, dangle_out1, dangle_out1_1, dangle_out1_2; + wire [3:0] dangle_out4; + wire [7:0] dangle_out8; + wire [31:0] dangle_out32; + reg finish_error = 0; + + + initial begin + + case (FIFO_MODE) + "FIFO18" : ; + "FIFO18_36" : if (DATA_WIDTH != 36) begin + $display("DRC Error : The attribute DATA_WIDTH must be set to 36 when attribute FIFO_MODE = FIFO18_36."); + finish_error = 1; + end + default : begin + $display("Attribute Syntax Error : The attribute FIFO_MODE on FIFO18E1 instance %m is set to %s. Legal values for this attribute are FIFO18 or FIFO18_36.", FIFO_MODE); + finish_error = 1; + end + + endcase // case(FIFO_MODE) + + + case (DATA_WIDTH) + + 4, 9, 18 : ; + 36 : if (FIFO_MODE != "FIFO18_36") begin + $display("DRC Error : The attribute FIFO_MODE must be set to FIFO18_36 when attribute DATA_WIDTH = 36."); + finish_error = 1; + end + default : begin + $display("Attribute Syntax Error : The attribute DATA_WIDTH on FIFO18E1 instance %m is set to %d. Legal values for this attribute are 4, 9, 18 or 36.", DATA_WIDTH); + finish_error = 1; + + end + endcase + + + if (finish_error == 1) + $finish; + + + end // initial begin + + + // Matching HW + localparam init_sdp = (FIFO_MODE == "FIFO18_36") ? {36'h0,INIT[35:34],INIT[17:16],INIT[33:18],INIT[15:0]} : {36'h0, INIT}; + localparam srval_sdp = (FIFO_MODE == "FIFO18_36") ? {36'h0,SRVAL[35:34],SRVAL[17:16],SRVAL[33:18],SRVAL[15:0]} : {36'h0, SRVAL}; + + + FF18_INTERNAL_VLOG #(.ALMOST_EMPTY_OFFSET(ALMOST_EMPTY_OFFSET), + .ALMOST_FULL_OFFSET(ALMOST_FULL_OFFSET), + .DATA_WIDTH(DATA_WIDTH), + .DO_REG(DO_REG), + .EN_SYN(EN_SYN), + .FIFO_MODE(FIFO_MODE), + .FIFO_SIZE(18), + .FIRST_WORD_FALL_THROUGH(FIRST_WORD_FALL_THROUGH), + .INIT({36'h0,init_sdp}), + .SRVAL({36'h0,srval_sdp})) + + INT_FIFO (.ALMOSTEMPTY(ALMOSTEMPTY), + .ALMOSTFULL(ALMOSTFULL), + .DBITERR(dangle_out), + .DI({32'b0,DI}), + .DIP({4'b0,DIP}), + .DO({dangle_out32,DO}), + .DOP({dangle_out4,DOP}), + .ECCPARITY(dangle_out8), + .EMPTY(EMPTY), + .FULL(FULL), + .GSR(GSR), + .INJECTDBITERR(1'b0), + .INJECTSBITERR(1'b0), + .RDCLK(RDCLK), + .RDCOUNT({dangle_out1,RDCOUNT}), + .RDEN(RDEN), + .RDERR(RDERR), + .REGCE(REGCE), + .RST(RST), + .RSTREG(RSTREG), + .SBITERR(dangle_out1_2), + .WRCLK(WRCLK), + .WRCOUNT({dangle_out1_1,WRCOUNT}), + .WREN(WREN), + .WRERR(WRERR)); + + + specify + + (RDCLK => DO[0]) = (100, 100); + (RDCLK => DO[1]) = (100, 100); + (RDCLK => DO[2]) = (100, 100); + (RDCLK => DO[3]) = (100, 100); + (RDCLK => DO[4]) = (100, 100); + (RDCLK => DO[5]) = (100, 100); + (RDCLK => DO[6]) = (100, 100); + (RDCLK => DO[7]) = (100, 100); + (RDCLK => DO[8]) = (100, 100); + (RDCLK => DO[9]) = (100, 100); + (RDCLK => DO[10]) = (100, 100); + (RDCLK => DO[11]) = (100, 100); + (RDCLK => DO[12]) = (100, 100); + (RDCLK => DO[13]) = (100, 100); + (RDCLK => DO[14]) = (100, 100); + (RDCLK => DO[15]) = (100, 100); + (RDCLK => DO[16]) = (100, 100); + (RDCLK => DO[17]) = (100, 100); + (RDCLK => DO[18]) = (100, 100); + (RDCLK => DO[19]) = (100, 100); + (RDCLK => DO[20]) = (100, 100); + (RDCLK => DO[21]) = (100, 100); + (RDCLK => DO[22]) = (100, 100); + (RDCLK => DO[23]) = (100, 100); + (RDCLK => DO[24]) = (100, 100); + (RDCLK => DO[25]) = (100, 100); + (RDCLK => DO[26]) = (100, 100); + (RDCLK => DO[27]) = (100, 100); + (RDCLK => DO[28]) = (100, 100); + (RDCLK => DO[29]) = (100, 100); + (RDCLK => DO[30]) = (100, 100); + (RDCLK => DO[31]) = (100, 100); + (RDCLK => DOP[0]) = (100, 100); + (RDCLK => DOP[1]) = (100, 100); + (RDCLK => DOP[2]) = (100, 100); + (RDCLK => DOP[3]) = (100, 100); + + (RDCLK => ALMOSTEMPTY) = (100, 100); + (RDCLK => EMPTY) = (100, 100); + (RDCLK => RDCOUNT[0]) = (100, 100); + (RDCLK => RDCOUNT[1]) = (100, 100); + (RDCLK => RDCOUNT[2]) = (100, 100); + (RDCLK => RDCOUNT[3]) = (100, 100); + (RDCLK => RDCOUNT[4]) = (100, 100); + (RDCLK => RDCOUNT[5]) = (100, 100); + (RDCLK => RDCOUNT[6]) = (100, 100); + (RDCLK => RDCOUNT[7]) = (100, 100); + (RDCLK => RDCOUNT[8]) = (100, 100); + (RDCLK => RDCOUNT[9]) = (100, 100); + (RDCLK => RDCOUNT[10]) = (100, 100); + (RDCLK => RDCOUNT[11]) = (100, 100); + (RDCLK => RDERR) = (100, 100); + + (WRCLK => ALMOSTFULL) = (100, 100); + (WRCLK => FULL) = (100, 100); + (WRCLK => WRCOUNT[0]) = (100, 100); + (WRCLK => WRCOUNT[1]) = (100, 100); + (WRCLK => WRCOUNT[2]) = (100, 100); + (WRCLK => WRCOUNT[3]) = (100, 100); + (WRCLK => WRCOUNT[4]) = (100, 100); + (WRCLK => WRCOUNT[5]) = (100, 100); + (WRCLK => WRCOUNT[6]) = (100, 100); + (WRCLK => WRCOUNT[7]) = (100, 100); + (WRCLK => WRCOUNT[8]) = (100, 100); + (WRCLK => WRCOUNT[9]) = (100, 100); + (WRCLK => WRCOUNT[10]) = (100, 100); + (WRCLK => WRCOUNT[11]) = (100, 100); + (WRCLK => WRERR) = (100, 100); + + specparam PATHPULSE$ = 0; + + endspecify + +endmodule // FIFO18E1 + + +// WARNING !!!: The following model is not an user primitive. +// Please do not modify any part of it. FIFO18E1 may not work properly if do so. +// +`timescale 1 ps/1 ps + +module FF18_INTERNAL_VLOG (ALMOSTEMPTY, ALMOSTFULL, DBITERR, DO, DOP, ECCPARITY, EMPTY, FULL, RDCOUNT, RDERR, SBITERR, WRCOUNT, WRERR, + DI, DIP, GSR, INJECTDBITERR, INJECTSBITERR, RDCLK, RDEN, REGCE, RST, RSTREG, WRCLK, WREN); + + output ALMOSTEMPTY; + output ALMOSTFULL; + output DBITERR; + output [63:0] DO; + output [7:0] DOP; + output [7:0] ECCPARITY; + output EMPTY; + output FULL; + output [12:0] RDCOUNT; + output RDERR; + output SBITERR; + output [12:0] WRCOUNT; + output WRERR; + + input [63:0] DI; + input [7:0] DIP; + input RDCLK; + input RDEN; + input REGCE; + input RST; + input RSTREG; + input WRCLK; + input WREN; + input GSR; + input INJECTDBITERR; + input INJECTSBITERR; + + parameter integer DATA_WIDTH = 4; + parameter integer DO_REG = 1; + parameter EN_SYN = "FALSE"; + parameter FIFO_MODE = "FIFO36"; + parameter FIRST_WORD_FALL_THROUGH = "FALSE"; + parameter ALMOST_EMPTY_OFFSET = 13'h0080; + parameter ALMOST_FULL_OFFSET = 13'h0080; + parameter EN_ECC_WRITE = "FALSE"; + parameter EN_ECC_READ = "FALSE"; + parameter INIT = 72'h0; + parameter SRVAL = 72'h0; + + reg [63:0] do_in = 64'b0; + reg [63:0] do_out = 64'b0; + reg [63:0] do_outreg = 64'b0; + reg [63:0] do_out_mux = 64'b0; + wire [63:0] do_out_out; + reg [7:0] dop_in = 8'b0, dop_out = 8'b0; + wire [7:0] dop_out_out; + reg [7:0] dop_outreg = 8'b0, dop_out_mux = 8'b0; + reg almostempty_out = 1'b1, almostfull_out = 1'b0, empty_out = 1'b1; + reg full_out = 1'b0, rderr_out = 0, wrerr_out = 0; + + reg dbiterr_out = 0, sbiterr_out = 0; + reg dbiterr_out_out = 0, sbiterr_out_out = 0; + reg [71:0] ecc_bit_position; + reg [7:0] eccparity_out = 8'b0; + reg [7:0] dopr_ecc, dop_buf, dip_ecc, dip_int; + reg [63:0] do_buf, di_in_ecc_corrected; + reg [7:0] syndrome, dip_in_ecc_corrected; + + wire [63:0] di_in; + wire [7:0] dip_in; + wire rdclk_in, rden_in, rst_in, rstreg_in, wrclk_in, wren_in; + wire regce_in, gsr_in; + wire injectdbiterr_in, injectsbiterr_in; + + reg rden_reg, wren_reg; + reg [12:0] ae_empty, ae_full; + reg fwft; + + integer addr_limit, rd_prefetch = 0; + integer wr1_addr = 0; + + reg [12:0] rdcount_out = 13'b0, wr_addr = 0, rd_addr = 0; + reg [12:0] rdcount_out_out = 13'b0, wr_addr_out = 13'b0; + reg rd_flag = 0, rdcount_flag = 0, rdprefetch_flag = 0, wr_flag = 0; + reg wr1_flag = 0, awr_flag = 0; + reg [3:0] almostfull_int = 4'b0000, almostempty_int = 4'b1111; + + reg [3:0] full_int = 4'b0000; + reg [3:0] empty_ram = 4'b1111; + reg [8:0] i, j; + reg rst_tmp1 = 0, rst_tmp2 = 0; + reg [2:0] rst_rdckreg = 3'b0, rst_wrckreg = 3'b0; + reg rst_rdclk_flag = 0, rst_wrclk_flag = 0; + reg en_ecc_write_int, en_ecc_read_int, finish_error = 0; + reg [63:0] di_ecc_col; + + +// xilinx_internal_parameter on + // WARNING !!!: This model may not work properly if the following parameter is changed. + parameter integer FIFO_SIZE = 36; +// xilinx_internal_parameter off + + + // Determinte memory size + localparam mem_size4 = (FIFO_SIZE == 18) ? 4095 : (FIFO_SIZE == 36) ? 8191 : 0; + localparam mem_size9 = (FIFO_SIZE == 18) ? 2047 : (FIFO_SIZE == 36) ? 4095 : 0; + localparam mem_size18 = (FIFO_SIZE == 18) ? 1023 : (FIFO_SIZE == 36) ? 2047 : 0; + localparam mem_size36 = (FIFO_SIZE == 18) ? 511 : (FIFO_SIZE == 36) ? 1023 : 0; + localparam mem_size72 = (FIFO_SIZE == 18) ? 0 : (FIFO_SIZE == 36) ? 511 : 0; + + localparam mem_depth = (DATA_WIDTH == 4) ? mem_size4 : (DATA_WIDTH == 9) ? mem_size9 : + (DATA_WIDTH == 18) ? mem_size18 : (DATA_WIDTH == 36) ? mem_size36 : + (DATA_WIDTH == 72) ? mem_size72 : 0; + + localparam mem_width = (DATA_WIDTH == 4) ? 3 : (DATA_WIDTH == 9) ? 7 : + (DATA_WIDTH == 18) ? 15 : (DATA_WIDTH == 36) ? 31 : (DATA_WIDTH == 72) ? 63 : 0; + + localparam memp_depth = (DATA_WIDTH == 4) ? 0 : (DATA_WIDTH == 9) ? mem_size9 : + (DATA_WIDTH == 18) ? mem_size18 : (DATA_WIDTH == 36) ? mem_size36 : + (DATA_WIDTH == 72) ? mem_size72 : 0; + + localparam memp_width = (DATA_WIDTH == 4 || DATA_WIDTH == 9) ? 0 : + (DATA_WIDTH == 18) ? 1 : (DATA_WIDTH == 36) ? 3 : (DATA_WIDTH == 72) ? 7 : 0; + + reg [mem_width : 0] mem [mem_depth : 0]; + reg [memp_width : 0] memp [memp_depth : 0]; + reg sync; + + + // Input and output ports + assign di_in = DI; + assign dip_in = DIP; + assign DO = do_out_out; + assign DOP = dop_out_out; + assign rdclk_in = RDCLK; + assign regce_in = REGCE; + assign rden_in = RDEN; + assign rst_in = RST; + assign rstreg_in = RSTREG; + assign wrclk_in = WRCLK; + assign wren_in = WREN; + assign gsr_in = GSR; + + assign ALMOSTEMPTY = almostempty_out; + assign ALMOSTFULL = almostfull_out; + assign EMPTY = empty_out; + assign FULL = full_out; + assign RDERR = rderr_out; + assign WRERR = wrerr_out; + assign SBITERR = sbiterr_out_out; + assign DBITERR = dbiterr_out_out; + assign ECCPARITY = eccparity_out; + assign RDCOUNT = rdcount_out_out; + assign WRCOUNT = wr_addr_out; + assign injectdbiterr_in = INJECTDBITERR; + assign injectsbiterr_in = INJECTSBITERR; + + + initial begin + + // Determine address limit + case (DATA_WIDTH) + 4 : begin + if (FIFO_SIZE == 36) + addr_limit = 8192; + else + addr_limit = 4096; + end + 9 : begin + if (FIFO_SIZE == 36) + addr_limit = 4096; + else + addr_limit = 2048; + end + 18 : begin + if (FIFO_SIZE == 36) + addr_limit = 2048; + else + addr_limit = 1024; + end + 36 : begin + if (FIFO_SIZE == 36) + addr_limit = 1024; + else + addr_limit = 512; + end + 72 : begin + addr_limit = 512; + end + default : + begin + $display("Attribute Syntax Error : The attribute DATA_WIDTH on FF18_INTERNAL_VLOG instance %m is set to %d. Legal values for this attribute are 4, 9, 18, 36 or 72.", DATA_WIDTH); + finish_error = 1; + end + endcase + + + case (EN_SYN) + "FALSE" : sync = 0; + "TRUE" : sync = 1; + default : begin + $display("Attribute Syntax Error : The attribute EN_SYN on FF18_INTERNAL_VLOG instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", EN_SYN); + finish_error = 1; + end + endcase // case(EN_SYN) + + + case (FIRST_WORD_FALL_THROUGH) + "FALSE" : begin + fwft = 0; + if (EN_SYN == "FALSE") begin + ae_empty = ALMOST_EMPTY_OFFSET - 1; + ae_full = ALMOST_FULL_OFFSET; + end + else begin + ae_empty = ALMOST_EMPTY_OFFSET; + ae_full = ALMOST_FULL_OFFSET; + end + end + "TRUE" : begin + fwft = 1; + ae_empty = ALMOST_EMPTY_OFFSET - 2; + ae_full = ALMOST_FULL_OFFSET; + end + default : begin + $display("Attribute Syntax Error : The attribute FIRST_WORD_FALL_THROUGH on FF18_INTERNAL_VLOG instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", FIRST_WORD_FALL_THROUGH); + finish_error = 1; + end + endcase + + + // Setup ranges for almostfull and almostempty + if (EN_SYN == "FALSE") begin + + if (fwft == 1'b0) begin + + if ((ALMOST_EMPTY_OFFSET < 5) || (ALMOST_EMPTY_OFFSET > addr_limit - 5)) begin + $display("Attribute Syntax Error : The attribute ALMOST_EMPTY_OFFSET on FF18_INTERNAL_VLOG instance %m is set to %d. Legal values for this attribute are %d to %d", ALMOST_EMPTY_OFFSET, 5, addr_limit - 5); + finish_error = 1; + end + + if ((ALMOST_FULL_OFFSET < 4) || (ALMOST_FULL_OFFSET > addr_limit - 5)) begin + $display("Attribute Syntax Error : The attribute ALMOST_FULL_OFFSET on FF18_INTERNAL_VLOG instance %m is set to %d. Legal values for this attribute are %d to %d", ALMOST_FULL_OFFSET, 4, addr_limit - 5); + finish_error = 1; + end + + end // if (fwft == 1'b0) + else begin + + if ((ALMOST_EMPTY_OFFSET < 6) || (ALMOST_EMPTY_OFFSET > addr_limit - 4)) begin + $display("Attribute Syntax Error : The attribute ALMOST_EMPTY_OFFSET on FF18_INTERNAL_VLOG instance %m is set to %d. Legal values for this attribute are %d to %d", ALMOST_EMPTY_OFFSET, 6, addr_limit - 4); + finish_error = 1; + end + + if ((ALMOST_FULL_OFFSET < 4) || (ALMOST_FULL_OFFSET > addr_limit - 5)) begin + $display("Attribute Syntax Error : The attribute ALMOST_FULL_OFFSET on FF18_INTERNAL_VLOG instance %m is set to %d. Legal values for this attribute are %d to %d", ALMOST_FULL_OFFSET, 4, addr_limit - 5); + finish_error = 1; + end + + end // else: !if(fwft == 1'b0) + end + else begin + + if ((fwft == 1'b0) && ((ALMOST_EMPTY_OFFSET < 1) || (ALMOST_EMPTY_OFFSET > addr_limit - 2))) begin + $display("Attribute Syntax Error : The attribute ALMOST_EMPTY_OFFSET on FF18_INTERNAL_VLOG instance %m is set to %d. Legal values for this attribute are %d to %d", ALMOST_EMPTY_OFFSET, 1, addr_limit - 2); + finish_error = 1; + end + + if ((fwft == 1'b0) && ((ALMOST_FULL_OFFSET < 1) || (ALMOST_FULL_OFFSET > addr_limit - 2))) begin + $display("Attribute Syntax Error : The attribute ALMOST_FULL_OFFSET on FF18_INTERNAL_VLOG instance %m is set to %d. Legal values for this attribute are %d to %d", ALMOST_FULL_OFFSET, 1, addr_limit - 2); + finish_error = 1; + end + + end // else: !if(EN_SYN == "FALSE") + + + // DRC for fwft in sync mode + if (fwft == 1'b1 && EN_SYN == "TRUE") begin + $display("DRC Error : First word fall through is not supported in synchronous mode on FF18_INTERNAL_VLOG instance %m."); + finish_error = 1; + end + + if (EN_SYN == "FALSE" && DO_REG == 0) begin + $display("DRC Error : DO_REG = 0 is invalid when EN_SYN is set to FALSE on FF18_INTERNAL_VLOG instance %m."); + finish_error = 1; + end + + + case (EN_ECC_WRITE) + "TRUE" : en_ecc_write_int <= 1; + "FALSE" : en_ecc_write_int <= 0; + default : begin + $display("Attribute Syntax Error : The attribute EN_ECC_WRITE on FF18_INTERNAL_VLOG instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", EN_ECC_WRITE); + finish_error = 1; + end + endcase + + + case (EN_ECC_READ) + "TRUE" : en_ecc_read_int <= 1; + "FALSE" : en_ecc_read_int <= 0; + default : begin + $display("Attribute Syntax Error : The attribute EN_ECC_READ on FF18_INTERNAL_VLOG instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", EN_ECC_READ); + finish_error = 1; + end + endcase + + + if ((EN_ECC_READ == "TRUE" || EN_ECC_WRITE == "TRUE") && DATA_WIDTH != 72) begin + $display("DRC Error : The attribute DATA_WIDTH must be set to 72 when FF18_INTERNAL_VLOG is configured in the ECC mode."); + finish_error = 1; + end + + + if (finish_error == 1) + $finish; + + + end // initial begin + + + // GSR and RST + always @(gsr_in) + if (gsr_in == 1'b1) begin + if (DO_REG == 1'b1 && sync == 1'b1) begin + assign do_out = INIT[0 +: mem_width+1]; + assign dop_out = INIT[mem_width+1 +: memp_width+1]; + assign do_outreg = INIT[0 +: mem_width+1]; + assign dop_outreg = INIT[mem_width+1 +: memp_width+1]; + end + else begin + assign do_out = 64'b0; + assign dop_out = 8'b0; + assign do_outreg = 64'b0; + assign dop_outreg = 8'b0; + end + end + else if (gsr_in == 1'b0) begin + deassign do_out; + deassign dop_out; + deassign do_outreg; + deassign dop_outreg; + end + + + always @(gsr_in or rst_in) + if (gsr_in == 1'b1 || rst_in == 1'b1) begin + assign almostempty_int = 4'b1111; + assign almostempty_out = 1'b1; + assign almostfull_int = 4'b0000; + assign almostfull_out = 1'b0; + assign do_in = 64'b00000000000000000000000000000000; + assign dop_in = 8'b0000; + assign empty_ram = 4'b1111; + assign empty_out = 1'b1; + assign full_int = 4'b0000; + assign full_out = 1'b0; + assign rdcount_out = 13'b0; + assign rdcount_out_out = 13'b0; + assign wr_addr_out = 13'b0; + assign rderr_out = 0; + assign wrerr_out = 0; + assign rd_addr = 0; + assign rd_prefetch = 0; + assign wr_addr = 0; + assign wr1_addr = 0; + assign rdcount_flag = 0; + assign rd_flag = 0; + assign rdprefetch_flag = 0; + assign wr_flag = 0; + assign wr1_flag = 0; + assign awr_flag = 0; + end + else if (gsr_in == 1'b0 && rst_in == 1'b0) begin + deassign almostempty_int; + deassign almostempty_out; + deassign almostfull_int; + deassign almostfull_out; + deassign do_in; + deassign dop_in; + deassign empty_ram; + deassign empty_out; + deassign full_int; + deassign full_out; + deassign rdcount_out; + deassign rdcount_out_out; + deassign wr_addr_out; + deassign rderr_out; + deassign wrerr_out; + deassign rd_addr; + deassign rd_prefetch; + deassign wr_addr; + deassign wr1_addr; + deassign rdcount_flag; + deassign rd_flag; + deassign rdprefetch_flag; + deassign wr_flag; + deassign wr1_flag; + deassign awr_flag; + end + + + // DRC + always @(rst_in or rden_in or wren_in) begin + if (rst_in ==1 && rden_in==1 ) + $display("Warning : At time %t, RDEN on FF18_INTERNAL_VLOG instance %m is high when RST is high. RDEN should be low during reset.", $stime); + if (rst_in ==1 && wren_in ==1) + $display("Warning : At time %t, WREN on FF18_INTERNAL_VLOG instance %m is high when RST is high. WREN should be low during reset.", $stime); + end + + + // 3 clock cycles required for RST, if not X outputs + always @(posedge rdclk_in) begin + rst_rdckreg[0] <= rst_in; + rst_rdckreg[1] <= rst_rdckreg[0] & rst_in; + rst_rdckreg[2] <= rst_rdckreg[1] & rst_in; + end + + always @(posedge wrclk_in) begin + rst_wrckreg[0] <= rst_in ; + rst_wrckreg[1] <= rst_wrckreg[0] & rst_in; + rst_wrckreg[2] <= rst_wrckreg[1] & rst_in; + end + + always @(rst_in) + begin + rst_tmp1 = rst_in; + rst_rdclk_flag = 0; + rst_wrclk_flag = 0; + + if (rst_tmp1 == 0 && rst_tmp2 == 1) begin + if ((rst_rdckreg[2] & rst_rdckreg[1] & rst_rdckreg[0]) == 0) begin + $display("Error : At time %t, RST high on FF18_INTERNAL_VLOG instance %m is short than three RDCLK clock cycles. RST high need be more that three RDCLK clock cycles.", $stime); + rst_rdclk_flag = 1; + end + + if ((rst_wrckreg[2] & rst_wrckreg[1] & rst_wrckreg[0]) == 0) begin + $display("Error : At time %t, RST high on FF18_INTERNAL_VLOG instance %m is short than three WRCLK clock cycles. RST high need be more that three WRCLK clock cycles.", $stime); + rst_wrclk_flag = 1; + end + + if ((rst_rdclk_flag | rst_wrclk_flag) == 1) begin + assign do_out = 64'bx; + assign dop_out = 8'bx; + assign do_outreg = 64'bx; + assign dop_outreg = 8'bx; + assign full_out = 1'bX; + assign empty_out = 1'bX; + assign rderr_out = 1'bX; + assign wrerr_out = 1'bX; + assign eccparity_out = 8'bx; + assign rdcount_out = 13'bx; + assign rdcount_out_out = 13'bx; + assign wr_addr_out = 13'bx; + assign wr_addr = 13'bx; + assign wr1_addr = 0; + assign almostempty_int = 4'b1111; + assign almostempty_out = 1'bx; + assign almostfull_int = 4'b0000; + assign almostfull_out = 1'bx; + assign do_in = 64'b00000000000000000000000000000000; + assign dop_in = 8'b0000; + assign empty_ram = 4'b1111; + assign full_int = 4'b0000; + assign rd_addr = 0; + assign rd_prefetch = 0; + assign rdcount_flag = 0; + assign rd_flag = 0; + assign rdprefetch_flag = 0; + assign wr_flag = 0; + assign wr1_flag = 0; + assign awr_flag = 0; + + end + else if (gsr_in == 1'b0 && rst_in == 1'b0) begin + deassign do_out; + deassign dop_out; + deassign do_outreg; + deassign dop_outreg; + deassign full_out; + deassign empty_out; + deassign rderr_out; + deassign wrerr_out; + deassign eccparity_out; + deassign rdcount_out; + rdcount_out = 13'b0; + deassign wr_addr; + wr_addr = 13'b0; + deassign rdcount_out_out; + deassign wr_addr_out; + deassign wr1_addr; + deassign almostempty_int; + deassign almostempty_out; + deassign almostfull_int; + deassign almostfull_out; + deassign do_in; + deassign dop_in; + deassign empty_ram; + deassign full_int; + deassign rd_addr; + deassign rd_prefetch; + deassign rdcount_flag; + deassign rd_flag; + deassign rdprefetch_flag; + deassign wr_flag; + deassign wr1_flag; + deassign awr_flag; + end + end // if (rst_tmp1 == 0 && rst_tmp2 == 1) + rst_tmp2 = rst_tmp1; + + end + + + // read clock + always @(posedge rdclk_in) begin + + // SRVAL in output register mode + if (DO_REG == 1 && sync == 1'b1 && rstreg_in === 1'b1) begin + + do_outreg = SRVAL[0 +: mem_width+1]; + + if (mem_width+1 >= 8) + dop_outreg = SRVAL[mem_width+1 +: memp_width+1]; + end + + + if (rst_in === 1'b0) begin + + // sync mode + if (sync == 1'b1) begin + + // output register + if (DO_REG == 1 && regce_in === 1'b1 && rstreg_in === 1'b0) begin + + do_outreg = do_out; + dop_outreg = dop_out; + dbiterr_out_out = dbiterr_out; // reg out in sync mode + sbiterr_out_out = sbiterr_out; + + end + + + if (rden_in == 1'b1) begin + + if (empty_out == 1'b0) begin + + do_buf = mem[rdcount_out]; + dop_buf = memp[rdcount_out]; + + // ECC decode + if (EN_ECC_READ == "TRUE") begin + + // regenerate parity + dopr_ecc[0] = do_buf[0]^do_buf[1]^do_buf[3]^do_buf[4]^do_buf[6]^do_buf[8] + ^do_buf[10]^do_buf[11]^do_buf[13]^do_buf[15]^do_buf[17]^do_buf[19] + ^do_buf[21]^do_buf[23]^do_buf[25]^do_buf[26]^do_buf[28] + ^do_buf[30]^do_buf[32]^do_buf[34]^do_buf[36]^do_buf[38] + ^do_buf[40]^do_buf[42]^do_buf[44]^do_buf[46]^do_buf[48] + ^do_buf[50]^do_buf[52]^do_buf[54]^do_buf[56]^do_buf[57]^do_buf[59] + ^do_buf[61]^do_buf[63]; + + dopr_ecc[1] = do_buf[0]^do_buf[2]^do_buf[3]^do_buf[5]^do_buf[6]^do_buf[9] + ^do_buf[10]^do_buf[12]^do_buf[13]^do_buf[16]^do_buf[17] + ^do_buf[20]^do_buf[21]^do_buf[24]^do_buf[25]^do_buf[27]^do_buf[28] + ^do_buf[31]^do_buf[32]^do_buf[35]^do_buf[36]^do_buf[39] + ^do_buf[40]^do_buf[43]^do_buf[44]^do_buf[47]^do_buf[48] + ^do_buf[51]^do_buf[52]^do_buf[55]^do_buf[56]^do_buf[58]^do_buf[59] + ^do_buf[62]^do_buf[63]; + + dopr_ecc[2] = do_buf[1]^do_buf[2]^do_buf[3]^do_buf[7]^do_buf[8]^do_buf[9] + ^do_buf[10]^do_buf[14]^do_buf[15]^do_buf[16]^do_buf[17] + ^do_buf[22]^do_buf[23]^do_buf[24]^do_buf[25]^do_buf[29] + ^do_buf[30]^do_buf[31]^do_buf[32]^do_buf[37]^do_buf[38]^do_buf[39] + ^do_buf[40]^do_buf[45]^do_buf[46]^do_buf[47]^do_buf[48] + ^do_buf[53]^do_buf[54]^do_buf[55]^do_buf[56] + ^do_buf[60]^do_buf[61]^do_buf[62]^do_buf[63]; + + dopr_ecc[3] = do_buf[4]^do_buf[5]^do_buf[6]^do_buf[7]^do_buf[8]^do_buf[9] + ^do_buf[10]^do_buf[18]^do_buf[19] + ^do_buf[20]^do_buf[21]^do_buf[22]^do_buf[23]^do_buf[24]^do_buf[25] + ^do_buf[33]^do_buf[34]^do_buf[35]^do_buf[36]^do_buf[37]^do_buf[38] + ^do_buf[39]^do_buf[40]^do_buf[49]^do_buf[50] + ^do_buf[51]^do_buf[52]^do_buf[53]^do_buf[54]^do_buf[55]^do_buf[56]; + + dopr_ecc[4] = do_buf[11]^do_buf[12]^do_buf[13]^do_buf[14]^do_buf[15]^do_buf[16] + ^do_buf[17]^do_buf[18]^do_buf[19]^do_buf[20]^do_buf[21]^do_buf[22] + ^do_buf[23]^do_buf[24]^do_buf[25]^do_buf[41]^do_buf[42]^do_buf[43] + ^do_buf[44]^do_buf[45]^do_buf[46]^do_buf[47]^do_buf[48]^do_buf[49] + ^do_buf[50]^do_buf[51]^do_buf[52]^do_buf[53]^do_buf[54]^do_buf[55]^do_buf[56]; + + + dopr_ecc[5] = do_buf[26]^do_buf[27]^do_buf[28]^do_buf[29] + ^do_buf[30]^do_buf[31]^do_buf[32]^do_buf[33]^do_buf[34]^do_buf[35] + ^do_buf[36]^do_buf[37]^do_buf[38]^do_buf[39]^do_buf[40] + ^do_buf[41]^do_buf[42]^do_buf[43]^do_buf[44]^do_buf[45] + ^do_buf[46]^do_buf[47]^do_buf[48]^do_buf[49]^do_buf[50] + ^do_buf[51]^do_buf[52]^do_buf[53]^do_buf[54]^do_buf[55]^do_buf[56]; + + dopr_ecc[6] = do_buf[57]^do_buf[58]^do_buf[59] + ^do_buf[60]^do_buf[61]^do_buf[62]^do_buf[63]; + + dopr_ecc[7] = dop_buf[0]^dop_buf[1]^dop_buf[2]^dop_buf[3]^dop_buf[4]^dop_buf[5] + ^dop_buf[6]^do_buf[0]^do_buf[1]^do_buf[2]^do_buf[3]^do_buf[4] + ^do_buf[5]^do_buf[6]^do_buf[7]^do_buf[8]^do_buf[9]^do_buf[10] + ^do_buf[11]^do_buf[12]^do_buf[13]^do_buf[14]^do_buf[15]^do_buf[16] + ^do_buf[17]^do_buf[18]^do_buf[19]^do_buf[20]^do_buf[21]^do_buf[22] + ^do_buf[23]^do_buf[24]^do_buf[25]^do_buf[26]^do_buf[27]^do_buf[28] + ^do_buf[29]^do_buf[30]^do_buf[31]^do_buf[32]^do_buf[33]^do_buf[34] + ^do_buf[35]^do_buf[36]^do_buf[37]^do_buf[38]^do_buf[39]^do_buf[40] + ^do_buf[41]^do_buf[42]^do_buf[43]^do_buf[44]^do_buf[45]^do_buf[46] + ^do_buf[47]^do_buf[48]^do_buf[49]^do_buf[50]^do_buf[51]^do_buf[52] + ^do_buf[53]^do_buf[54]^do_buf[55]^do_buf[56]^do_buf[57]^do_buf[58] + ^do_buf[59]^do_buf[60]^do_buf[61]^do_buf[62]^do_buf[63]; + + syndrome = dopr_ecc ^ dop_buf; + + // checking error + if (syndrome !== 0) begin + + if (syndrome[7]) begin // dectect single bit error + + ecc_bit_position = {do_buf[63:57], dop_buf[6], do_buf[56:26], dop_buf[5], do_buf[25:11], dop_buf[4], do_buf[10:4], dop_buf[3], do_buf[3:1], dop_buf[2], do_buf[0], dop_buf[1:0], dop_buf[7]}; + + if (syndrome[6:0] > 71) begin + $display ("DRC Error : Simulation halted due Corrupted DIP. To correct this problem, make sure that reliable data is fed to the DIP. The correct Parity must be generated by a Hamming code encoder or encoder in the Block RAM. The output from the model is unreliable if there are more than 2 bit errors. The model doesn't warn if there is sporadic input of more than 2 bit errors due to the limitation in Hamming code."); + $finish; + end + + ecc_bit_position[syndrome[6:0]] = ~ecc_bit_position[syndrome[6:0]]; // correct single bit error in the output + + di_in_ecc_corrected = {ecc_bit_position[71:65], ecc_bit_position[63:33], ecc_bit_position[31:17], ecc_bit_position[15:9], ecc_bit_position[7:5], ecc_bit_position[3]}; // correct single bit error in the memory + + do_buf = di_in_ecc_corrected; + + dip_in_ecc_corrected = {ecc_bit_position[0], ecc_bit_position[64], ecc_bit_position[32], ecc_bit_position[16], ecc_bit_position[8], ecc_bit_position[4], ecc_bit_position[2:1]}; // correct single bit error in the parity memory + + dop_buf = dip_in_ecc_corrected; + + dbiterr_out = 0; // latch out in sync mode + sbiterr_out = 1; + + end + else if (!syndrome[7]) begin // double bit error + sbiterr_out = 0; + dbiterr_out = 1; + + end + end // if (syndrome !== 0) + else begin + dbiterr_out = 0; + sbiterr_out = 0; + + end // else: !if(syndrome !== 0) + + end // if (EN_ECC_READ == "TRUE") + // end ecc decode + + + if (DO_REG == 0) begin + dbiterr_out_out = dbiterr_out; + sbiterr_out_out = sbiterr_out; + end + + + do_out = do_buf; + dop_out = dop_buf; + + rdcount_out = (rdcount_out + 1) % addr_limit; + + if (rdcount_out == 0) + rdcount_flag = ~rdcount_flag; + + end + end + + + rderr_out = (rden_in == 1'b1) && (empty_out == 1'b1); + + + if (wren_in == 1'b1) begin + empty_out = 1'b0; + end + else if (rdcount_out == wr_addr && rdcount_flag == wr_flag) + empty_out = 1'b1; + + if ((((rdcount_out + ae_empty) >= wr_addr) && (rdcount_flag == wr_flag)) || (((rdcount_out + ae_empty) >= (wr_addr + addr_limit) && (rdcount_flag != wr_flag)))) begin + almostempty_out = 1'b1; + end + + if ((((rdcount_out + addr_limit) > (wr_addr + ae_full)) && (rdcount_flag == wr_flag)) || ((rdcount_out > (wr_addr + ae_full)) && (rdcount_flag != wr_flag))) begin + if (wr_addr <= wr_addr + ae_full || rdcount_flag == wr_flag) + almostfull_out = 1'b0; + end + + end // if (sync == 1'b1) + + // async mode + else if (sync == 1'b0) begin + + rden_reg = rden_in; + if (fwft == 1'b0) begin + if ((rden_reg == 1'b1) && (rd_addr != rdcount_out)) begin + do_out = do_in; + if (DATA_WIDTH != 4) + dop_out = dop_in; + rd_addr = (rd_addr + 1) % addr_limit; + if (rd_addr == 0) + rd_flag = ~rd_flag; + + dbiterr_out_out = dbiterr_out; // reg out in async mode + sbiterr_out_out = sbiterr_out; + + end + if (((rd_addr == rdcount_out) && (empty_ram[3] == 1'b0)) || + ((rden_reg == 1'b1) && (empty_ram[1] == 1'b0))) begin + + do_buf = mem[rdcount_out]; + dop_buf = memp[rdcount_out]; + + // ECC decode + if (EN_ECC_READ == "TRUE") begin + + // regenerate parity + dopr_ecc[0] = do_buf[0]^do_buf[1]^do_buf[3]^do_buf[4]^do_buf[6]^do_buf[8] + ^do_buf[10]^do_buf[11]^do_buf[13]^do_buf[15]^do_buf[17]^do_buf[19] + ^do_buf[21]^do_buf[23]^do_buf[25]^do_buf[26]^do_buf[28] + ^do_buf[30]^do_buf[32]^do_buf[34]^do_buf[36]^do_buf[38] + ^do_buf[40]^do_buf[42]^do_buf[44]^do_buf[46]^do_buf[48] + ^do_buf[50]^do_buf[52]^do_buf[54]^do_buf[56]^do_buf[57]^do_buf[59] + ^do_buf[61]^do_buf[63]; + + dopr_ecc[1] = do_buf[0]^do_buf[2]^do_buf[3]^do_buf[5]^do_buf[6]^do_buf[9] + ^do_buf[10]^do_buf[12]^do_buf[13]^do_buf[16]^do_buf[17] + ^do_buf[20]^do_buf[21]^do_buf[24]^do_buf[25]^do_buf[27]^do_buf[28] + ^do_buf[31]^do_buf[32]^do_buf[35]^do_buf[36]^do_buf[39] + ^do_buf[40]^do_buf[43]^do_buf[44]^do_buf[47]^do_buf[48] + ^do_buf[51]^do_buf[52]^do_buf[55]^do_buf[56]^do_buf[58]^do_buf[59] + ^do_buf[62]^do_buf[63]; + + dopr_ecc[2] = do_buf[1]^do_buf[2]^do_buf[3]^do_buf[7]^do_buf[8]^do_buf[9] + ^do_buf[10]^do_buf[14]^do_buf[15]^do_buf[16]^do_buf[17] + ^do_buf[22]^do_buf[23]^do_buf[24]^do_buf[25]^do_buf[29] + ^do_buf[30]^do_buf[31]^do_buf[32]^do_buf[37]^do_buf[38]^do_buf[39] + ^do_buf[40]^do_buf[45]^do_buf[46]^do_buf[47]^do_buf[48] + ^do_buf[53]^do_buf[54]^do_buf[55]^do_buf[56] + ^do_buf[60]^do_buf[61]^do_buf[62]^do_buf[63]; + + dopr_ecc[3] = do_buf[4]^do_buf[5]^do_buf[6]^do_buf[7]^do_buf[8]^do_buf[9] + ^do_buf[10]^do_buf[18]^do_buf[19] + ^do_buf[20]^do_buf[21]^do_buf[22]^do_buf[23]^do_buf[24]^do_buf[25] + ^do_buf[33]^do_buf[34]^do_buf[35]^do_buf[36]^do_buf[37]^do_buf[38] + ^do_buf[39]^do_buf[40]^do_buf[49]^do_buf[50] + ^do_buf[51]^do_buf[52]^do_buf[53]^do_buf[54]^do_buf[55]^do_buf[56]; + + dopr_ecc[4] = do_buf[11]^do_buf[12]^do_buf[13]^do_buf[14]^do_buf[15]^do_buf[16] + ^do_buf[17]^do_buf[18]^do_buf[19]^do_buf[20]^do_buf[21]^do_buf[22] + ^do_buf[23]^do_buf[24]^do_buf[25]^do_buf[41]^do_buf[42]^do_buf[43] + ^do_buf[44]^do_buf[45]^do_buf[46]^do_buf[47]^do_buf[48]^do_buf[49] + ^do_buf[50]^do_buf[51]^do_buf[52]^do_buf[53]^do_buf[54]^do_buf[55]^do_buf[56]; + + + dopr_ecc[5] = do_buf[26]^do_buf[27]^do_buf[28]^do_buf[29] + ^do_buf[30]^do_buf[31]^do_buf[32]^do_buf[33]^do_buf[34]^do_buf[35] + ^do_buf[36]^do_buf[37]^do_buf[38]^do_buf[39]^do_buf[40] + ^do_buf[41]^do_buf[42]^do_buf[43]^do_buf[44]^do_buf[45] + ^do_buf[46]^do_buf[47]^do_buf[48]^do_buf[49]^do_buf[50] + ^do_buf[51]^do_buf[52]^do_buf[53]^do_buf[54]^do_buf[55]^do_buf[56]; + + dopr_ecc[6] = do_buf[57]^do_buf[58]^do_buf[59] + ^do_buf[60]^do_buf[61]^do_buf[62]^do_buf[63]; + + dopr_ecc[7] = dop_buf[0]^dop_buf[1]^dop_buf[2]^dop_buf[3]^dop_buf[4]^dop_buf[5] + ^dop_buf[6]^do_buf[0]^do_buf[1]^do_buf[2]^do_buf[3]^do_buf[4] + ^do_buf[5]^do_buf[6]^do_buf[7]^do_buf[8]^do_buf[9]^do_buf[10] + ^do_buf[11]^do_buf[12]^do_buf[13]^do_buf[14]^do_buf[15]^do_buf[16] + ^do_buf[17]^do_buf[18]^do_buf[19]^do_buf[20]^do_buf[21]^do_buf[22] + ^do_buf[23]^do_buf[24]^do_buf[25]^do_buf[26]^do_buf[27]^do_buf[28] + ^do_buf[29]^do_buf[30]^do_buf[31]^do_buf[32]^do_buf[33]^do_buf[34] + ^do_buf[35]^do_buf[36]^do_buf[37]^do_buf[38]^do_buf[39]^do_buf[40] + ^do_buf[41]^do_buf[42]^do_buf[43]^do_buf[44]^do_buf[45]^do_buf[46] + ^do_buf[47]^do_buf[48]^do_buf[49]^do_buf[50]^do_buf[51]^do_buf[52] + ^do_buf[53]^do_buf[54]^do_buf[55]^do_buf[56]^do_buf[57]^do_buf[58] + ^do_buf[59]^do_buf[60]^do_buf[61]^do_buf[62]^do_buf[63]; + + syndrome = dopr_ecc ^ dop_buf; + + if (syndrome !== 0) begin + + if (syndrome[7]) begin // dectect single bit error + + ecc_bit_position = {do_buf[63:57], dop_buf[6], do_buf[56:26], dop_buf[5], do_buf[25:11], dop_buf[4], do_buf[10:4], dop_buf[3], do_buf[3:1], dop_buf[2], do_buf[0], dop_buf[1:0], dop_buf[7]}; + + if (syndrome[6:0] > 71) begin + $display ("DRC Error : Simulation halted due Corrupted DIP. To correct this problem, make sure that reliable data is fed to the DIP. The correct Parity must be generated by a Hamming code encoder or encoder in the Block RAM. The output from the model is unreliable if there are more than 2 bit errors. The model doesn't warn if there is sporadic input of more than 2 bit errors due to the limitation in Hamming code."); + $finish; + end + + ecc_bit_position[syndrome[6:0]] = ~ecc_bit_position[syndrome[6:0]]; // correct single bit error in the output + + di_in_ecc_corrected = {ecc_bit_position[71:65], ecc_bit_position[63:33], ecc_bit_position[31:17], ecc_bit_position[15:9], ecc_bit_position[7:5], ecc_bit_position[3]}; // correct single bit error in the memory + + do_buf = di_in_ecc_corrected; + + dip_in_ecc_corrected = {ecc_bit_position[0], ecc_bit_position[64], ecc_bit_position[32], ecc_bit_position[16], ecc_bit_position[8], ecc_bit_position[4], ecc_bit_position[2:1]}; // correct single bit error in the parity memory + + dop_buf = dip_in_ecc_corrected; + + dbiterr_out = 0; + sbiterr_out = 1; + + end + else if (!syndrome[7]) begin // double bit error + sbiterr_out = 0; + dbiterr_out = 1; + + end + end // if (syndrome !== 0) + else begin + dbiterr_out = 0; + sbiterr_out = 0; + + end // else: !if(syndrome !== 0) + + end // if (EN_ECC_READ == "TRUE") + // end ecc decode + + do_in = do_buf; + dop_in = dop_buf; + + #1; + rdcount_out = (rdcount_out + 1) % addr_limit; + if (rdcount_out == 0) begin + rdcount_flag = ~rdcount_flag; + end + end + end + + // First word fall through = true + if (fwft == 1'b1) begin + + if ((rden_reg == 1'b1) && (rd_addr != rd_prefetch)) begin + rd_prefetch = (rd_prefetch + 1) % addr_limit; + if (rd_prefetch == 0) + rdprefetch_flag = ~rdprefetch_flag; + end + if ((rd_prefetch == rd_addr) && (rd_addr != rdcount_out)) begin + do_out = do_in; + if (DATA_WIDTH != 4) + dop_out = dop_in; + rd_addr = (rd_addr + 1) % addr_limit; + if (rd_addr == 0) + rd_flag = ~rd_flag; + + dbiterr_out_out = dbiterr_out; // reg out in async mode + sbiterr_out_out = sbiterr_out; + + end + if (((rd_addr == rdcount_out) && (empty_ram[3] == 1'b0)) || + ((rden_reg == 1'b1) && (empty_ram[1] == 1'b0)) || + ((rden_reg == 1'b0) && (empty_ram[1] == 1'b0) && (rd_addr == rdcount_out))) begin + + do_buf = mem[rdcount_out]; + dop_buf = memp[rdcount_out]; + + // ECC decode + if (EN_ECC_READ == "TRUE") begin + + // regenerate parity + dopr_ecc[0] = do_buf[0]^do_buf[1]^do_buf[3]^do_buf[4]^do_buf[6]^do_buf[8] + ^do_buf[10]^do_buf[11]^do_buf[13]^do_buf[15]^do_buf[17]^do_buf[19] + ^do_buf[21]^do_buf[23]^do_buf[25]^do_buf[26]^do_buf[28] + ^do_buf[30]^do_buf[32]^do_buf[34]^do_buf[36]^do_buf[38] + ^do_buf[40]^do_buf[42]^do_buf[44]^do_buf[46]^do_buf[48] + ^do_buf[50]^do_buf[52]^do_buf[54]^do_buf[56]^do_buf[57]^do_buf[59] + ^do_buf[61]^do_buf[63]; + + dopr_ecc[1] = do_buf[0]^do_buf[2]^do_buf[3]^do_buf[5]^do_buf[6]^do_buf[9] + ^do_buf[10]^do_buf[12]^do_buf[13]^do_buf[16]^do_buf[17] + ^do_buf[20]^do_buf[21]^do_buf[24]^do_buf[25]^do_buf[27]^do_buf[28] + ^do_buf[31]^do_buf[32]^do_buf[35]^do_buf[36]^do_buf[39] + ^do_buf[40]^do_buf[43]^do_buf[44]^do_buf[47]^do_buf[48] + ^do_buf[51]^do_buf[52]^do_buf[55]^do_buf[56]^do_buf[58]^do_buf[59] + ^do_buf[62]^do_buf[63]; + + dopr_ecc[2] = do_buf[1]^do_buf[2]^do_buf[3]^do_buf[7]^do_buf[8]^do_buf[9] + ^do_buf[10]^do_buf[14]^do_buf[15]^do_buf[16]^do_buf[17] + ^do_buf[22]^do_buf[23]^do_buf[24]^do_buf[25]^do_buf[29] + ^do_buf[30]^do_buf[31]^do_buf[32]^do_buf[37]^do_buf[38]^do_buf[39] + ^do_buf[40]^do_buf[45]^do_buf[46]^do_buf[47]^do_buf[48] + ^do_buf[53]^do_buf[54]^do_buf[55]^do_buf[56] + ^do_buf[60]^do_buf[61]^do_buf[62]^do_buf[63]; + + dopr_ecc[3] = do_buf[4]^do_buf[5]^do_buf[6]^do_buf[7]^do_buf[8]^do_buf[9] + ^do_buf[10]^do_buf[18]^do_buf[19] + ^do_buf[20]^do_buf[21]^do_buf[22]^do_buf[23]^do_buf[24]^do_buf[25] + ^do_buf[33]^do_buf[34]^do_buf[35]^do_buf[36]^do_buf[37]^do_buf[38] + ^do_buf[39]^do_buf[40]^do_buf[49]^do_buf[50] + ^do_buf[51]^do_buf[52]^do_buf[53]^do_buf[54]^do_buf[55]^do_buf[56]; + + dopr_ecc[4] = do_buf[11]^do_buf[12]^do_buf[13]^do_buf[14]^do_buf[15]^do_buf[16] + ^do_buf[17]^do_buf[18]^do_buf[19]^do_buf[20]^do_buf[21]^do_buf[22] + ^do_buf[23]^do_buf[24]^do_buf[25]^do_buf[41]^do_buf[42]^do_buf[43] + ^do_buf[44]^do_buf[45]^do_buf[46]^do_buf[47]^do_buf[48]^do_buf[49] + ^do_buf[50]^do_buf[51]^do_buf[52]^do_buf[53]^do_buf[54]^do_buf[55]^do_buf[56]; + + + dopr_ecc[5] = do_buf[26]^do_buf[27]^do_buf[28]^do_buf[29] + ^do_buf[30]^do_buf[31]^do_buf[32]^do_buf[33]^do_buf[34]^do_buf[35] + ^do_buf[36]^do_buf[37]^do_buf[38]^do_buf[39]^do_buf[40] + ^do_buf[41]^do_buf[42]^do_buf[43]^do_buf[44]^do_buf[45] + ^do_buf[46]^do_buf[47]^do_buf[48]^do_buf[49]^do_buf[50] + ^do_buf[51]^do_buf[52]^do_buf[53]^do_buf[54]^do_buf[55]^do_buf[56]; + + dopr_ecc[6] = do_buf[57]^do_buf[58]^do_buf[59] + ^do_buf[60]^do_buf[61]^do_buf[62]^do_buf[63]; + + dopr_ecc[7] = dop_buf[0]^dop_buf[1]^dop_buf[2]^dop_buf[3]^dop_buf[4]^dop_buf[5] + ^dop_buf[6]^do_buf[0]^do_buf[1]^do_buf[2]^do_buf[3]^do_buf[4] + ^do_buf[5]^do_buf[6]^do_buf[7]^do_buf[8]^do_buf[9]^do_buf[10] + ^do_buf[11]^do_buf[12]^do_buf[13]^do_buf[14]^do_buf[15]^do_buf[16] + ^do_buf[17]^do_buf[18]^do_buf[19]^do_buf[20]^do_buf[21]^do_buf[22] + ^do_buf[23]^do_buf[24]^do_buf[25]^do_buf[26]^do_buf[27]^do_buf[28] + ^do_buf[29]^do_buf[30]^do_buf[31]^do_buf[32]^do_buf[33]^do_buf[34] + ^do_buf[35]^do_buf[36]^do_buf[37]^do_buf[38]^do_buf[39]^do_buf[40] + ^do_buf[41]^do_buf[42]^do_buf[43]^do_buf[44]^do_buf[45]^do_buf[46] + ^do_buf[47]^do_buf[48]^do_buf[49]^do_buf[50]^do_buf[51]^do_buf[52] + ^do_buf[53]^do_buf[54]^do_buf[55]^do_buf[56]^do_buf[57]^do_buf[58] + ^do_buf[59]^do_buf[60]^do_buf[61]^do_buf[62]^do_buf[63]; + + syndrome = dopr_ecc ^ dop_buf; + + if (syndrome !== 0) begin + + if (syndrome[7]) begin // dectect single bit error + + ecc_bit_position = {do_buf[63:57], dop_buf[6], do_buf[56:26], dop_buf[5], do_buf[25:11], dop_buf[4], do_buf[10:4], dop_buf[3], do_buf[3:1], dop_buf[2], do_buf[0], dop_buf[1:0], dop_buf[7]}; + + if (syndrome[6:0] > 71) begin + $display ("DRC Error : Simulation halted due Corrupted DIP. To correct this problem, make sure that reliable data is fed to the DIP. The correct Parity must be generated by a Hamming code encoder or encoder in the Block RAM. The output from the model is unreliable if there are more than 2 bit errors. The model doesn't warn if there is sporadic input of more than 2 bit errors due to the limitation in Hamming code."); + $finish; + end + + ecc_bit_position[syndrome[6:0]] = ~ecc_bit_position[syndrome[6:0]]; // correct single bit error in the output + + di_in_ecc_corrected = {ecc_bit_position[71:65], ecc_bit_position[63:33], ecc_bit_position[31:17], ecc_bit_position[15:9], ecc_bit_position[7:5], ecc_bit_position[3]}; // correct single bit error in the memory + + do_buf = di_in_ecc_corrected; + + dip_in_ecc_corrected = {ecc_bit_position[0], ecc_bit_position[64], ecc_bit_position[32], ecc_bit_position[16], ecc_bit_position[8], ecc_bit_position[4], ecc_bit_position[2:1]}; // correct single bit error in the parity memory + + dop_buf = dip_in_ecc_corrected; + + dbiterr_out = 0; + sbiterr_out = 1; + + end + else if (!syndrome[7]) begin // double bit error + sbiterr_out = 0; + dbiterr_out = 1; + + end + end // if (syndrome !== 0) + else begin + dbiterr_out = 0; + sbiterr_out = 0; + + end // else: !if(syndrome !== 0) + + end // if (EN_ECC_READ == "TRUE") + // end ecc decode + + do_in = do_buf; + dop_in = dop_buf; + + #1; + rdcount_out = (rdcount_out + 1) % addr_limit; + if (rdcount_out == 0) + rdcount_flag = ~rdcount_flag; + end + end // if (fwft == 1'b1) + + + rderr_out = (rden_reg == 1'b1) && (empty_out == 1'b1); + + almostempty_out = almostempty_int[3]; + + if ((((rdcount_out + ae_empty) >= wr_addr) && (rdcount_flag == awr_flag)) || (((rdcount_out + ae_empty) >= (wr_addr + addr_limit)) && (rdcount_flag != awr_flag))) begin + almostempty_int[3] = 1'b1; + almostempty_int[2] = 1'b1; + almostempty_int[1] = 1'b1; + almostempty_int[0] = 1'b1; + end + else if (almostempty_int[2] == 1'b0) begin + + if (rdcount_out <= rdcount_out + ae_empty || rdcount_flag != awr_flag) begin + almostempty_int[3] = almostempty_int[0]; + almostempty_int[0] = 1'b0; + end + end + + if ((((rdcount_out + addr_limit) > (wr_addr + ae_full)) && (rdcount_flag == awr_flag)) || ((rdcount_out > (wr_addr + ae_full)) && (rdcount_flag != awr_flag))) begin + + if (((rden_reg == 1'b1) && (empty_out == 1'b0)) || ((((rd_addr + 1) % addr_limit) == rdcount_out) && (almostfull_int[1] == 1'b1))) begin + almostfull_int[2] = almostfull_int[1]; + almostfull_int[1] = 1'b0; + end + end + else begin + almostfull_int[2] = 1'b1; + almostfull_int[1] = 1'b1; + end + + if (fwft == 1'b0) begin + if ((rdcount_out == rd_addr) && (rdcount_flag == rd_flag)) begin + empty_out = 1'b1; + end + else begin + empty_out = 1'b0; + end + end // if (fwft == 1'b0) + else if (fwft == 1'b1) begin + if ((rd_prefetch == rd_addr) && (rdprefetch_flag == rd_flag)) begin + empty_out = 1'b1; + end + else begin + empty_out = 1'b0; + end + end + + + if ((rdcount_out == wr_addr) && (rdcount_flag == awr_flag)) begin + empty_ram[2] = 1'b1; + empty_ram[1] = 1'b1; + empty_ram[0] = 1'b1; + end + else begin + empty_ram[2] = empty_ram[1]; + empty_ram[1] = empty_ram[0]; + empty_ram[0] = 1'b0; + end + + if ((rdcount_out == wr1_addr) && (rdcount_flag == wr1_flag)) begin + empty_ram[3] = 1'b1; + end + else begin + empty_ram[3] = 1'b0; + end + + wr1_addr = wr_addr; + wr1_flag = awr_flag; + + end // if (sync == 1'b0) + + end // if (rst_in === 1'b0) + + end // always @ (posedge rdclk_in) + + + // Write clock + always @(posedge wrclk_in) begin + + // DRC + if ((injectsbiterr_in === 1) && !(en_ecc_write_int == 1 || en_ecc_read_int == 1)) + $display("DRC Warning : INJECTSBITERR is not supported when neither EN_ECC_WRITE nor EN_ECCREAD = TRUE on FF18_INTERNAL_VLOG instance %m."); + + if ((injectdbiterr_in === 1) && !(en_ecc_write_int == 1 || en_ecc_read_int == 1)) + $display("DRC Warning : INJECTDBITERR is not supported when neither EN_ECC_WRITE nor EN_ECCREAD = TRUE on FF18_INTERNAL_VLOG instance %m."); + + + // sync mode + if (sync == 1'b1) begin + + if (wren_in == 1'b1) begin + + if (full_out == 1'b0) begin + + // ECC encode + if (EN_ECC_WRITE == "TRUE") begin + + dip_ecc[0] = di_in[0]^di_in[1]^di_in[3]^di_in[4]^di_in[6]^di_in[8] + ^di_in[10]^di_in[11]^di_in[13]^di_in[15]^di_in[17]^di_in[19] + ^di_in[21]^di_in[23]^di_in[25]^di_in[26]^di_in[28] + ^di_in[30]^di_in[32]^di_in[34]^di_in[36]^di_in[38] + ^di_in[40]^di_in[42]^di_in[44]^di_in[46]^di_in[48] + ^di_in[50]^di_in[52]^di_in[54]^di_in[56]^di_in[57]^di_in[59] + ^di_in[61]^di_in[63]; + + dip_ecc[1] = di_in[0]^di_in[2]^di_in[3]^di_in[5]^di_in[6]^di_in[9] + ^di_in[10]^di_in[12]^di_in[13]^di_in[16]^di_in[17] + ^di_in[20]^di_in[21]^di_in[24]^di_in[25]^di_in[27]^di_in[28] + ^di_in[31]^di_in[32]^di_in[35]^di_in[36]^di_in[39] + ^di_in[40]^di_in[43]^di_in[44]^di_in[47]^di_in[48] + ^di_in[51]^di_in[52]^di_in[55]^di_in[56]^di_in[58]^di_in[59] + ^di_in[62]^di_in[63]; + + dip_ecc[2] = di_in[1]^di_in[2]^di_in[3]^di_in[7]^di_in[8]^di_in[9] + ^di_in[10]^di_in[14]^di_in[15]^di_in[16]^di_in[17] + ^di_in[22]^di_in[23]^di_in[24]^di_in[25]^di_in[29] + ^di_in[30]^di_in[31]^di_in[32]^di_in[37]^di_in[38]^di_in[39] + ^di_in[40]^di_in[45]^di_in[46]^di_in[47]^di_in[48] + ^di_in[53]^di_in[54]^di_in[55]^di_in[56] + ^di_in[60]^di_in[61]^di_in[62]^di_in[63]; + + dip_ecc[3] = di_in[4]^di_in[5]^di_in[6]^di_in[7]^di_in[8]^di_in[9] + ^di_in[10]^di_in[18]^di_in[19] + ^di_in[20]^di_in[21]^di_in[22]^di_in[23]^di_in[24]^di_in[25] + ^di_in[33]^di_in[34]^di_in[35]^di_in[36]^di_in[37]^di_in[38]^di_in[39] + ^di_in[40]^di_in[49] + ^di_in[50]^di_in[51]^di_in[52]^di_in[53]^di_in[54]^di_in[55]^di_in[56]; + + dip_ecc[4] = di_in[11]^di_in[12]^di_in[13]^di_in[14]^di_in[15]^di_in[16]^di_in[17]^di_in[18]^di_in[19] + ^di_in[20]^di_in[21]^di_in[22]^di_in[23]^di_in[24]^di_in[25] + ^di_in[41]^di_in[42]^di_in[43]^di_in[44]^di_in[45]^di_in[46]^di_in[47]^di_in[48]^di_in[49] + ^di_in[50]^di_in[51]^di_in[52]^di_in[53]^di_in[54]^di_in[55]^di_in[56]; + + + dip_ecc[5] = di_in[26]^di_in[27]^di_in[28]^di_in[29] + ^di_in[30]^di_in[31]^di_in[32]^di_in[33]^di_in[34]^di_in[35]^di_in[36]^di_in[37]^di_in[38]^di_in[39] + ^di_in[40]^di_in[41]^di_in[42]^di_in[43]^di_in[44]^di_in[45]^di_in[46]^di_in[47]^di_in[48]^di_in[49] + ^di_in[50]^di_in[51]^di_in[52]^di_in[53]^di_in[54]^di_in[55]^di_in[56]; + + dip_ecc[6] = di_in[57]^di_in[58]^di_in[59] + ^di_in[60]^di_in[61]^di_in[62]^di_in[63]; + + dip_ecc[7] = dip_ecc[0]^dip_ecc[1]^dip_ecc[2]^dip_ecc[3]^dip_ecc[4]^dip_ecc[5]^dip_ecc[6] + ^di_in[0]^di_in[1]^di_in[2]^di_in[3]^di_in[4]^di_in[5]^di_in[6]^di_in[7]^di_in[8]^di_in[9] + ^di_in[10]^di_in[11]^di_in[12]^di_in[13]^di_in[14]^di_in[15]^di_in[16]^di_in[17]^di_in[18]^di_in[19] + ^di_in[20]^di_in[21]^di_in[22]^di_in[23]^di_in[24]^di_in[25]^di_in[26]^di_in[27]^di_in[28]^di_in[29] + ^di_in[30]^di_in[31]^di_in[32]^di_in[33]^di_in[34]^di_in[35]^di_in[36]^di_in[37]^di_in[38]^di_in[39] + ^di_in[40]^di_in[41]^di_in[42]^di_in[43]^di_in[44]^di_in[45]^di_in[46]^di_in[47]^di_in[48]^di_in[49] + ^di_in[50]^di_in[51]^di_in[52]^di_in[53]^di_in[54]^di_in[55]^di_in[56]^di_in[57]^di_in[58]^di_in[59] + ^di_in[60]^di_in[61]^di_in[62]^di_in[63]; + + eccparity_out = dip_ecc; + + dip_int = dip_ecc; // only 64 bits width + + end // if (EN_ECC_WRITE == "TRUE") + else begin + + dip_int = dip_in; // only 64 bits width + + end // else: !if(EN_ECC_WRITE == "TRUE") + // end ecc encode + + + if (rst_in === 1'b0) begin + + + // injecting error + di_ecc_col = di_in; + + if (injectdbiterr_in === 1) begin + di_ecc_col[30] = ~di_ecc_col[30]; + di_ecc_col[62] = ~di_ecc_col[62]; + end + else if (injectsbiterr_in === 1) begin + di_ecc_col[30] = ~di_ecc_col[30]; + end + + + mem[wr_addr] = di_ecc_col; + memp[wr_addr] = dip_int; + + wr_addr = (wr_addr + 1) % addr_limit; + if (wr_addr == 0) + wr_flag = ~wr_flag; + + end + end + end // if (wren_in == 1'b1) + + + if (rst_in === 1'b0) begin + + wrerr_out = (wren_in == 1'b1) && (full_out == 1'b1); + + + if (rden_in == 1'b1) begin + full_out = 1'b0; + end + else if (rdcount_out == wr_addr && rdcount_flag != wr_flag) + full_out = 1'b1; + + if ((((rdcount_out + ae_empty) < wr_addr) && (rdcount_flag == wr_flag)) || (((rdcount_out + ae_empty) < (wr_addr + addr_limit) && (rdcount_flag != wr_flag)))) begin + + if (rdcount_out <= rdcount_out + ae_empty || rdcount_flag != wr_flag) + almostempty_out = 1'b0; + + end + + if ((((rdcount_out + addr_limit) <= (wr_addr + ae_full)) && (rdcount_flag == wr_flag)) || ((rdcount_out <= (wr_addr + ae_full)) && (rdcount_flag != wr_flag))) begin + almostfull_out = 1'b1; + end + + end // if (rst_in === 1'b0) + + end // if (sync == 1'b1) + + // async mode + else if (sync == 1'b0) begin + + wren_reg = wren_in; + + if (wren_reg == 1'b1 && full_out == 1'b0) begin + + // ECC encode + if (EN_ECC_WRITE == "TRUE") begin + + dip_ecc[0] = di_in[0]^di_in[1]^di_in[3]^di_in[4]^di_in[6]^di_in[8] + ^di_in[10]^di_in[11]^di_in[13]^di_in[15]^di_in[17]^di_in[19] + ^di_in[21]^di_in[23]^di_in[25]^di_in[26]^di_in[28] + ^di_in[30]^di_in[32]^di_in[34]^di_in[36]^di_in[38] + ^di_in[40]^di_in[42]^di_in[44]^di_in[46]^di_in[48] + ^di_in[50]^di_in[52]^di_in[54]^di_in[56]^di_in[57]^di_in[59] + ^di_in[61]^di_in[63]; + + dip_ecc[1] = di_in[0]^di_in[2]^di_in[3]^di_in[5]^di_in[6]^di_in[9] + ^di_in[10]^di_in[12]^di_in[13]^di_in[16]^di_in[17] + ^di_in[20]^di_in[21]^di_in[24]^di_in[25]^di_in[27]^di_in[28] + ^di_in[31]^di_in[32]^di_in[35]^di_in[36]^di_in[39] + ^di_in[40]^di_in[43]^di_in[44]^di_in[47]^di_in[48] + ^di_in[51]^di_in[52]^di_in[55]^di_in[56]^di_in[58]^di_in[59] + ^di_in[62]^di_in[63]; + + dip_ecc[2] = di_in[1]^di_in[2]^di_in[3]^di_in[7]^di_in[8]^di_in[9] + ^di_in[10]^di_in[14]^di_in[15]^di_in[16]^di_in[17] + ^di_in[22]^di_in[23]^di_in[24]^di_in[25]^di_in[29] + ^di_in[30]^di_in[31]^di_in[32]^di_in[37]^di_in[38]^di_in[39] + ^di_in[40]^di_in[45]^di_in[46]^di_in[47]^di_in[48] + ^di_in[53]^di_in[54]^di_in[55]^di_in[56] + ^di_in[60]^di_in[61]^di_in[62]^di_in[63]; + + dip_ecc[3] = di_in[4]^di_in[5]^di_in[6]^di_in[7]^di_in[8]^di_in[9] + ^di_in[10]^di_in[18]^di_in[19] + ^di_in[20]^di_in[21]^di_in[22]^di_in[23]^di_in[24]^di_in[25] + ^di_in[33]^di_in[34]^di_in[35]^di_in[36]^di_in[37]^di_in[38]^di_in[39] + ^di_in[40]^di_in[49] + ^di_in[50]^di_in[51]^di_in[52]^di_in[53]^di_in[54]^di_in[55]^di_in[56]; + + dip_ecc[4] = di_in[11]^di_in[12]^di_in[13]^di_in[14]^di_in[15]^di_in[16]^di_in[17]^di_in[18]^di_in[19] + ^di_in[20]^di_in[21]^di_in[22]^di_in[23]^di_in[24]^di_in[25] + ^di_in[41]^di_in[42]^di_in[43]^di_in[44]^di_in[45]^di_in[46]^di_in[47]^di_in[48]^di_in[49] + ^di_in[50]^di_in[51]^di_in[52]^di_in[53]^di_in[54]^di_in[55]^di_in[56]; + + + dip_ecc[5] = di_in[26]^di_in[27]^di_in[28]^di_in[29] + ^di_in[30]^di_in[31]^di_in[32]^di_in[33]^di_in[34]^di_in[35]^di_in[36]^di_in[37]^di_in[38]^di_in[39] + ^di_in[40]^di_in[41]^di_in[42]^di_in[43]^di_in[44]^di_in[45]^di_in[46]^di_in[47]^di_in[48]^di_in[49] + ^di_in[50]^di_in[51]^di_in[52]^di_in[53]^di_in[54]^di_in[55]^di_in[56]; + + dip_ecc[6] = di_in[57]^di_in[58]^di_in[59] + ^di_in[60]^di_in[61]^di_in[62]^di_in[63]; + + dip_ecc[7] = dip_ecc[0]^dip_ecc[1]^dip_ecc[2]^dip_ecc[3]^dip_ecc[4]^dip_ecc[5]^dip_ecc[6] + ^di_in[0]^di_in[1]^di_in[2]^di_in[3]^di_in[4]^di_in[5]^di_in[6]^di_in[7]^di_in[8]^di_in[9] + ^di_in[10]^di_in[11]^di_in[12]^di_in[13]^di_in[14]^di_in[15]^di_in[16]^di_in[17]^di_in[18]^di_in[19] + ^di_in[20]^di_in[21]^di_in[22]^di_in[23]^di_in[24]^di_in[25]^di_in[26]^di_in[27]^di_in[28]^di_in[29] + ^di_in[30]^di_in[31]^di_in[32]^di_in[33]^di_in[34]^di_in[35]^di_in[36]^di_in[37]^di_in[38]^di_in[39] + ^di_in[40]^di_in[41]^di_in[42]^di_in[43]^di_in[44]^di_in[45]^di_in[46]^di_in[47]^di_in[48]^di_in[49] + ^di_in[50]^di_in[51]^di_in[52]^di_in[53]^di_in[54]^di_in[55]^di_in[56]^di_in[57]^di_in[58]^di_in[59] + ^di_in[60]^di_in[61]^di_in[62]^di_in[63]; + + eccparity_out = dip_ecc; + + dip_int = dip_ecc; // only 64 bits width + + end // if (EN_ECC_WRITE == "TRUE") + else begin + + dip_int = dip_in; // only 64 bits width + + end // else: !if(EN_ECC_WRITE == "TRUE") + // end ecc encode + + if (rst_in === 1'b0) begin + + // injecting error + di_ecc_col = di_in; + + if (injectdbiterr_in === 1) begin + di_ecc_col[30] = ~di_ecc_col[30]; + di_ecc_col[62] = ~di_ecc_col[62]; + end + else if (injectsbiterr_in === 1) begin + di_ecc_col[30] = ~di_ecc_col[30]; + end + + + mem[wr_addr] = di_ecc_col; + memp[wr_addr] = dip_int; + + #1; + wr_addr = (wr_addr + 1) % addr_limit; + + if (wr_addr == 0) + awr_flag = ~awr_flag; + + if (wr_addr == addr_limit - 1) + wr_flag = ~wr_flag; + + + end // if (rst_in === 1'b0) + + end // if (wren_reg == 1'b1 && full_out == 1'b0) + + + if (rst_in === 1'b0) begin + + wrerr_out = (wren_reg == 1'b1) && (full_out == 1'b1); + + almostfull_out = almostfull_int[3]; + + if ((((rdcount_out + addr_limit) <= (wr_addr + ae_full)) && (rdcount_flag == awr_flag)) || ((rdcount_out <= (wr_addr + ae_full)) && (rdcount_flag != awr_flag))) begin + almostfull_int[3] = 1'b1; + almostfull_int[2] = 1'b1; + almostfull_int[1] = 1'b1; + almostfull_int[0] = 1'b1; + end + else if (almostfull_int[2] == 1'b0) begin + + if (wr_addr <= wr_addr + ae_full || rdcount_flag == awr_flag) begin + almostfull_int[3] = almostfull_int[0]; + almostfull_int[0] = 1'b0; + end + end + + if ((((rdcount_out + ae_empty) < wr_addr) && (rdcount_flag == awr_flag)) || (((rdcount_out + ae_empty) < (wr_addr + addr_limit)) && (rdcount_flag != awr_flag))) begin + if (wren_reg == 1'b1) begin + almostempty_int[2] = almostempty_int[1]; + almostempty_int[1] = 1'b0; + end + end + else begin + almostempty_int[2] = 1'b1; + almostempty_int[1] = 1'b1; + end + + if (wren_reg == 1'b1 || full_out == 1'b1) + full_out = full_int[1]; + + if (((rdcount_out == wr_addr) || (rdcount_out - 1 == wr_addr || (rdcount_out + addr_limit - 1 == wr_addr))) && almostfull_out) begin + full_int[1] = 1'b1; + full_int[0] = 1'b1; + end + else begin + full_int[1] = full_int[0]; + full_int[0] = 0; + end + + end // if (rst_in === 1'b0) + + end // if (sync == 1'b0) + + end // always @ (posedge wrclk_in) + + + + // output register + always @(do_out or dop_out or do_outreg or dop_outreg) begin + + if (sync == 1) + + case (DO_REG) + + 0 : begin + do_out_mux = do_out; + dop_out_mux = dop_out; + end + 1 : begin + do_out_mux = do_outreg; + dop_out_mux = dop_outreg; + end + default : begin + $display("Attribute Syntax Error : The attribute DO_REG on FF18_INTERNAL_VLOG instance %m is set to %2d. Legal values for this attribute are 0 or 1.", DO_REG); + $finish; + end + endcase + + else begin + do_out_mux = do_out; + dop_out_mux = dop_out; + end // else: !if(sync == 1) + + end // always @ (do_out or dop_out or do_outreg or dop_outreg) + + + // matching HW behavior to X the unused output bits + assign do_out_out = (DATA_WIDTH == 4) ? {60'bx, do_out_mux[3:0]} + : (DATA_WIDTH == 9) ? {56'bx, do_out_mux[7:0]} + : (DATA_WIDTH == 18) ? {48'bx, do_out_mux[15:0]} + : (DATA_WIDTH == 36) ? {32'bx, do_out_mux[31:0]} + : (DATA_WIDTH == 72) ? do_out_mux + : do_out_mux; + + // matching HW behavior to X the unused output bits + assign dop_out_out = (DATA_WIDTH == 9) ? {7'bx, dop_out_mux[0:0]} + : (DATA_WIDTH == 18) ? {6'bx, dop_out_mux[1:0]} + : (DATA_WIDTH == 36) ? {4'bx, dop_out_mux[3:0]} + : (DATA_WIDTH == 72) ? dop_out_mux + : 8'bx; + + // matching HW behavior to pull up the unused output bits + always @(wr_addr) begin + + if (FIFO_SIZE == 18) + case (DATA_WIDTH) + 4 : wr_addr_out = {1'b1, wr_addr[11:0]}; + 9 : wr_addr_out = {2'b11, wr_addr[10:0]}; + 18 : wr_addr_out = {3'b111, wr_addr[9:0]}; + 36 : wr_addr_out = {4'hf, wr_addr[8:0]}; + default : wr_addr_out = wr_addr; + endcase // case(DATA_WIDTH) + else + case (DATA_WIDTH) + 4 : wr_addr_out = wr_addr; + 9 : wr_addr_out = {1'b1, wr_addr[11:0]}; + 18 : wr_addr_out = {2'b11, wr_addr[10:0]}; + 36 : wr_addr_out = {3'b111, wr_addr[9:0]}; + 72 : wr_addr_out = {4'hf, wr_addr[8:0]}; + default : wr_addr_out = wr_addr; + endcase // case(DATA_WIDTH) + + end // always @ (wr_addr) + + + // matching HW behavior to pull up the unused output bits + always @(rdcount_out) begin + + if (FIFO_SIZE == 18) + case (DATA_WIDTH) + 4 : rdcount_out_out = {1'b1, rdcount_out[11:0]}; + 9 : rdcount_out_out = {2'b11, rdcount_out[10:0]}; + 18 : rdcount_out_out = {3'b111, rdcount_out[9:0]}; + 36 : rdcount_out_out = {4'hf, rdcount_out[8:0]}; + default : rdcount_out_out = rdcount_out; + endcase // case(DATA_WIDTH) + else + case (DATA_WIDTH) + 4 : rdcount_out_out = rdcount_out; + 9 : rdcount_out_out = {1'b1, rdcount_out[11:0]}; + 18 : rdcount_out_out = {2'b11, rdcount_out[10:0]}; + 36 : rdcount_out_out = {3'b111, rdcount_out[9:0]}; + 72 : rdcount_out_out = {4'hf, rdcount_out[8:0]}; + default : rdcount_out_out = rdcount_out; + endcase // case(DATA_WIDTH) + + end // always @ (rdcount_out) + + +endmodule + +// end of FF18_INTERNAL_VLOG - Note: Not an user primitive diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/FIFO18_36.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/FIFO18_36.v new file mode 100644 index 0000000..eab698e --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/FIFO18_36.v @@ -0,0 +1,139 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/rainier/FIFO18_36.v,v 1.12 2007/06/15 20:58:41 wloo Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2005 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / 18K-Bit FIFO +// /___/ /\ Filename : FIFO18_36.v +// \ \ / \ Timestamp : Tues July 26 16:44:06 PST 2005 +// \___\/\___\ +// +// Revision: +// 07/26/05 - Initial version. +// 06/14/07 - Implemented high performace version of the model. +// End Revision + +`timescale 1 ps/1 ps + +module FIFO18_36 (ALMOSTEMPTY, ALMOSTFULL, DO, DOP, EMPTY, FULL, RDCOUNT, RDERR, WRCOUNT, WRERR, + DI, DIP, RDCLK, RDEN, RST, WRCLK, WREN); + + parameter ALMOST_EMPTY_OFFSET = 9'h080; + parameter ALMOST_FULL_OFFSET = 9'h080; + parameter integer DO_REG = 1; + parameter EN_SYN = "FALSE"; + parameter FIRST_WORD_FALL_THROUGH = "FALSE"; + parameter SIM_MODE = "SAFE"; + + output ALMOSTEMPTY; + output ALMOSTFULL; + output [31:0] DO; + output [3:0] DOP; + output EMPTY; + output FULL; + output [8:0] RDCOUNT; + output RDERR; + output [8:0] WRCOUNT; + output WRERR; + + input [31:0] DI; + input [3:0] DIP; + input RDCLK; + input RDEN; + input RST; + input WRCLK; + input WREN; + + tri0 GSR = glbl.GSR; + + wire [31:0] dangle_out32; + wire [3:0] dangle_out4; + wire [7:0] dangle_out8; + wire dangle_out; + + AFIFO36_INTERNAL INT_FIFO (.ALMOSTEMPTY(ALMOSTEMPTY), .ALMOSTFULL(ALMOSTFULL), .DBITERR(dangle_out), .DO({dangle_out32,DO}), .DOP({dangle_out4,DOP}), .ECCPARITY(dangle_out8), .EMPTY(EMPTY), .FULL(FULL), .RDCOUNT({dangle_out4,RDCOUNT}), .RDERR(RDERR), .SBITERR(dangle_out), .WRCOUNT({dangle_out4,WRCOUNT}), .WRERR(WRERR), .DI({32'b0,DI}), .DIP({4'b0,DIP}), .RDCLK(RDCLK), .RDEN(RDEN), .RDRCLK(RDCLK), .RST(RST), .WRCLK(WRCLK), .WREN(WREN)); + + defparam INT_FIFO.FIFO_SIZE = 18; + defparam INT_FIFO.ALMOST_EMPTY_OFFSET = ALMOST_EMPTY_OFFSET; + defparam INT_FIFO.ALMOST_FULL_OFFSET = ALMOST_FULL_OFFSET; + defparam INT_FIFO.DATA_WIDTH = 36; + defparam INT_FIFO.DO_REG = DO_REG; + defparam INT_FIFO.EN_SYN = EN_SYN; + defparam INT_FIFO.FIRST_WORD_FALL_THROUGH = FIRST_WORD_FALL_THROUGH; + defparam INT_FIFO.SIM_MODE = SIM_MODE; + + specify + + (RDCLK => DO[0]) = (100, 100); + (RDCLK => DO[1]) = (100, 100); + (RDCLK => DO[2]) = (100, 100); + (RDCLK => DO[3]) = (100, 100); + (RDCLK => DO[4]) = (100, 100); + (RDCLK => DO[5]) = (100, 100); + (RDCLK => DO[6]) = (100, 100); + (RDCLK => DO[7]) = (100, 100); + (RDCLK => DO[8]) = (100, 100); + (RDCLK => DO[9]) = (100, 100); + (RDCLK => DO[10]) = (100, 100); + (RDCLK => DO[11]) = (100, 100); + (RDCLK => DO[12]) = (100, 100); + (RDCLK => DO[13]) = (100, 100); + (RDCLK => DO[14]) = (100, 100); + (RDCLK => DO[15]) = (100, 100); + (RDCLK => DO[16]) = (100, 100); + (RDCLK => DO[17]) = (100, 100); + (RDCLK => DO[18]) = (100, 100); + (RDCLK => DO[19]) = (100, 100); + (RDCLK => DO[20]) = (100, 100); + (RDCLK => DO[21]) = (100, 100); + (RDCLK => DO[22]) = (100, 100); + (RDCLK => DO[23]) = (100, 100); + (RDCLK => DO[24]) = (100, 100); + (RDCLK => DO[25]) = (100, 100); + (RDCLK => DO[26]) = (100, 100); + (RDCLK => DO[27]) = (100, 100); + (RDCLK => DO[28]) = (100, 100); + (RDCLK => DO[29]) = (100, 100); + (RDCLK => DO[30]) = (100, 100); + (RDCLK => DO[31]) = (100, 100); + (RDCLK => DOP[0]) = (100, 100); + (RDCLK => DOP[1]) = (100, 100); + (RDCLK => DOP[2]) = (100, 100); + (RDCLK => DOP[3]) = (100, 100); + + (RDCLK => ALMOSTEMPTY) = (100, 100); + (RDCLK => EMPTY) = (100, 100); + (RDCLK => RDCOUNT[0]) = (100, 100); + (RDCLK => RDCOUNT[1]) = (100, 100); + (RDCLK => RDCOUNT[2]) = (100, 100); + (RDCLK => RDCOUNT[3]) = (100, 100); + (RDCLK => RDCOUNT[4]) = (100, 100); + (RDCLK => RDCOUNT[5]) = (100, 100); + (RDCLK => RDCOUNT[6]) = (100, 100); + (RDCLK => RDCOUNT[7]) = (100, 100); + (RDCLK => RDCOUNT[8]) = (100, 100); + (RDCLK => RDERR) = (100, 100); + + (WRCLK => ALMOSTFULL) = (100, 100); + (WRCLK => FULL) = (100, 100); + (WRCLK => WRCOUNT[0]) = (100, 100); + (WRCLK => WRCOUNT[1]) = (100, 100); + (WRCLK => WRCOUNT[2]) = (100, 100); + (WRCLK => WRCOUNT[3]) = (100, 100); + (WRCLK => WRCOUNT[4]) = (100, 100); + (WRCLK => WRCOUNT[5]) = (100, 100); + (WRCLK => WRCOUNT[6]) = (100, 100); + (WRCLK => WRCOUNT[7]) = (100, 100); + (WRCLK => WRCOUNT[8]) = (100, 100); + (WRCLK => WRERR) = (100, 100); + + specparam PATHPULSE$ = 0; + + endspecify + +endmodule // FIFO18_36 diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/FIFO36.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/FIFO36.v new file mode 100644 index 0000000..05d9d31 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/FIFO36.v @@ -0,0 +1,162 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/rainier/FIFO36.v,v 1.12 2007/06/15 20:58:41 wloo Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2005 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / 36K-Bit FIFO +// /___/ /\ Filename : FIFO36.v +// \ \ / \ Timestamp : Tues July 26 16:44:06 PST 2005 +// \___\/\___\ +// +// Revision: +// 07/26/05 - Initial version. +// 06/14/07 - Implemented high performace version of the model. +// End Revision + +`timescale 1 ps/1 ps + +module FIFO36 (ALMOSTEMPTY, ALMOSTFULL, DO, DOP, EMPTY, FULL, RDCOUNT, RDERR, WRCOUNT, WRERR, + DI, DIP, RDCLK, RDEN, RST, WRCLK, WREN); + + parameter ALMOST_EMPTY_OFFSET = 13'h0080; + parameter ALMOST_FULL_OFFSET = 13'h0080; + parameter integer DATA_WIDTH = 4; + parameter integer DO_REG = 1; + parameter EN_SYN = "FALSE"; + parameter FIRST_WORD_FALL_THROUGH = "FALSE"; + parameter SIM_MODE = "SAFE"; + + output ALMOSTEMPTY; + output ALMOSTFULL; + output [31:0] DO; + output [3:0] DOP; + output EMPTY; + output FULL; + output [12:0] RDCOUNT; + output RDERR; + output [12:0] WRCOUNT; + output WRERR; + + input [31:0] DI; + input [3:0] DIP; + input RDCLK; + input RDEN; + input RST; + input WRCLK; + input WREN; + + tri0 GSR = glbl.GSR; + + wire [31:0] dangle_out32; + wire [3:0] dangle_out4; + wire [7:0] dangle_out8; + wire dangle_out; + + + initial begin + + case (DATA_WIDTH) + 4, 9, 18, 36 : ; + default : + begin + $display("Attribute Syntax Error : The attribute DATA_WIDTH on FIFO36 instance %m is set to %d. Legal values for this attribute are 4, 9, 18 or 36.", DATA_WIDTH); + $finish; + end + endcase // case(DATA_WIDTH) + + end // initial begin + + + AFIFO36_INTERNAL INT_FIFO (.ALMOSTEMPTY(ALMOSTEMPTY), .ALMOSTFULL(ALMOSTFULL), .DBITERR(dangle_out), .DO({dangle_out32,DO}), .DOP({dangle_out4,DOP}), .ECCPARITY(dangle_out8), .EMPTY(EMPTY), .FULL(FULL), .RDCOUNT(RDCOUNT), .RDERR(RDERR), .SBITERR(dangle_out), .WRCOUNT(WRCOUNT), .WRERR(WRERR), + .DI({32'b0,DI}), .DIP({4'b0,DIP}), .RDCLK(RDCLK), .RDEN(RDEN), .RDRCLK(RDCLK), .RST(RST), .WRCLK(WRCLK), .WREN(WREN)); + + defparam INT_FIFO.ALMOST_EMPTY_OFFSET = ALMOST_EMPTY_OFFSET; + defparam INT_FIFO.ALMOST_FULL_OFFSET = ALMOST_FULL_OFFSET; + defparam INT_FIFO.DATA_WIDTH = DATA_WIDTH; + defparam INT_FIFO.DO_REG = DO_REG; + defparam INT_FIFO.EN_SYN = EN_SYN; + defparam INT_FIFO.FIRST_WORD_FALL_THROUGH = FIRST_WORD_FALL_THROUGH; + defparam INT_FIFO.SIM_MODE = SIM_MODE; + + specify + + (RDCLK => ALMOSTEMPTY) = (100, 100); + (RDCLK => DOP[0]) = (100, 100); + (RDCLK => DOP[1]) = (100, 100); + (RDCLK => DOP[2]) = (100, 100); + (RDCLK => DOP[3]) = (100, 100); + (RDCLK => DO[0]) = (100, 100); + (RDCLK => DO[10]) = (100, 100); + (RDCLK => DO[11]) = (100, 100); + (RDCLK => DO[12]) = (100, 100); + (RDCLK => DO[13]) = (100, 100); + (RDCLK => DO[14]) = (100, 100); + (RDCLK => DO[15]) = (100, 100); + (RDCLK => DO[16]) = (100, 100); + (RDCLK => DO[17]) = (100, 100); + (RDCLK => DO[18]) = (100, 100); + (RDCLK => DO[19]) = (100, 100); + (RDCLK => DO[1]) = (100, 100); + (RDCLK => DO[20]) = (100, 100); + (RDCLK => DO[21]) = (100, 100); + (RDCLK => DO[22]) = (100, 100); + (RDCLK => DO[23]) = (100, 100); + (RDCLK => DO[24]) = (100, 100); + (RDCLK => DO[25]) = (100, 100); + (RDCLK => DO[26]) = (100, 100); + (RDCLK => DO[27]) = (100, 100); + (RDCLK => DO[28]) = (100, 100); + (RDCLK => DO[29]) = (100, 100); + (RDCLK => DO[2]) = (100, 100); + (RDCLK => DO[30]) = (100, 100); + (RDCLK => DO[31]) = (100, 100); + (RDCLK => DO[3]) = (100, 100); + (RDCLK => DO[4]) = (100, 100); + (RDCLK => DO[5]) = (100, 100); + (RDCLK => DO[6]) = (100, 100); + (RDCLK => DO[7]) = (100, 100); + (RDCLK => DO[8]) = (100, 100); + (RDCLK => DO[9]) = (100, 100); + (RDCLK => EMPTY) = (100, 100); + (RDCLK => RDCOUNT[0]) = (100, 100); + (RDCLK => RDCOUNT[10]) = (100, 100); + (RDCLK => RDCOUNT[11]) = (100, 100); + (RDCLK => RDCOUNT[12]) = (100, 100); + (RDCLK => RDCOUNT[1]) = (100, 100); + (RDCLK => RDCOUNT[2]) = (100, 100); + (RDCLK => RDCOUNT[3]) = (100, 100); + (RDCLK => RDCOUNT[4]) = (100, 100); + (RDCLK => RDCOUNT[5]) = (100, 100); + (RDCLK => RDCOUNT[6]) = (100, 100); + (RDCLK => RDCOUNT[7]) = (100, 100); + (RDCLK => RDCOUNT[8]) = (100, 100); + (RDCLK => RDCOUNT[9]) = (100, 100); + (RDCLK => RDERR) = (100, 100); + + (WRCLK => ALMOSTFULL) = (100, 100); + (WRCLK => FULL) = (100, 100); + (WRCLK => WRCOUNT[0]) = (100, 100); + (WRCLK => WRCOUNT[10]) = (100, 100); + (WRCLK => WRCOUNT[11]) = (100, 100); + (WRCLK => WRCOUNT[12]) = (100, 100); + (WRCLK => WRCOUNT[1]) = (100, 100); + (WRCLK => WRCOUNT[2]) = (100, 100); + (WRCLK => WRCOUNT[3]) = (100, 100); + (WRCLK => WRCOUNT[4]) = (100, 100); + (WRCLK => WRCOUNT[5]) = (100, 100); + (WRCLK => WRCOUNT[6]) = (100, 100); + (WRCLK => WRCOUNT[7]) = (100, 100); + (WRCLK => WRCOUNT[8]) = (100, 100); + (WRCLK => WRCOUNT[9]) = (100, 100); + (WRCLK => WRERR) = (100, 100); + + specparam PATHPULSE$ = 0; + + endspecify + +endmodule // FIFO36 diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/FIFO36E1.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/FIFO36E1.v new file mode 100644 index 0000000..bb4f3cf --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/FIFO36E1.v @@ -0,0 +1,1739 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/blanc/FIFO36E1.v,v 1.15 2009/12/03 02:16:12 wloo Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2008 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / 36K-Bit FIFO +// /___/ /\ Filename : FIFO36E1.v +// \ \ / \ Timestamp : Tue Mar 18 16:55:14 PDT 2008 +// \___\/\___\ +// +// Revision: +// 03/18/08 - Initial version. +// 07/10/08 - IR476500 Add INIT parameter support +// 08/08/08 - Updated ECC to match hardware. (IR 479250) +// 08/26/08 - Updated unused bit on wrcount and rdcount to match the hardware. +// 09/02/08 - Fixed ECC mismatch with hardware. (IR 479250) +// 11/10/08 - Added DRC for invalid input parity for ECC (CR 482976). +// 01/30/09 - Fixed eccparity when reset (IR 501358). +// 03/17/09 - Undo IR 501358 (CR 511331). +// 04/02/09 - Implemented DRC for FIFO_MODE (CR 517127). +// 10/07/09 - Fixed reset behavior (CR 532794). +// 10/23/09 - Fixed RST and RSTREG (CR 537067). +// 11/17/09 - Fixed ECCPARITY behavior during RST (CR 537360). +// 12/02/09 - Updated SRVAL and INIT port mapping for FIFO_MODE = FIFO36_72 (CR 539776). +// End Revision + +`timescale 1 ps/1 ps + +module FIFO36E1 (ALMOSTEMPTY, ALMOSTFULL, DBITERR, DO, DOP, ECCPARITY, EMPTY, FULL, RDCOUNT, RDERR, SBITERR, WRCOUNT, WRERR, + DI, DIP, INJECTDBITERR, INJECTSBITERR, RDCLK, RDEN, REGCE, RST, RSTREG, WRCLK, WREN); + + parameter ALMOST_EMPTY_OFFSET = 13'h0080; + parameter ALMOST_FULL_OFFSET = 13'h0080; + parameter integer DATA_WIDTH = 4; + parameter integer DO_REG = 1; + parameter EN_ECC_READ = "FALSE"; + parameter EN_ECC_WRITE = "FALSE"; + parameter EN_SYN = "FALSE"; + parameter FIFO_MODE = "FIFO36"; + parameter FIRST_WORD_FALL_THROUGH = "FALSE"; + parameter INIT = 72'h0; + parameter SRVAL = 72'h0; + + output ALMOSTEMPTY; + output ALMOSTFULL; + output DBITERR; + output [63:0] DO; + output [7:0] DOP; + output [7:0] ECCPARITY; + output EMPTY; + output FULL; + output [12:0] RDCOUNT; + output RDERR; + output SBITERR; + output [12:0] WRCOUNT; + output WRERR; + + input [63:0] DI; + input [7:0] DIP; + input INJECTDBITERR; + input INJECTSBITERR; + input RDCLK; + input RDEN; + input REGCE; + input RST; + input RSTREG; + input WRCLK; + input WREN; + + tri0 GSR = glbl.GSR; + + reg finish_error = 0; + + + initial begin + + case (FIFO_MODE) + "FIFO36" : ; + "FIFO36_72" : if (DATA_WIDTH != 72) begin + $display("DRC Error : The attribute DATA_WIDTH must be set to 72 when attribute FIFO_MODE = FIFO36_72."); + finish_error = 1; + end + default : begin + $display("Attribute Syntax Error : The attribute FIFO_MODE on FIFO36E1 instance %m is set to %s. Legal values for this attribute are FIFO36 or FIFO36_72.", FIFO_MODE); + finish_error = 1; + end + + endcase // case(FIFO_MODE) + + + case (DATA_WIDTH) + + 4, 9, 18, 36 : ; + 72 : if (FIFO_MODE != "FIFO36_72") begin + $display("DRC Error : The attribute FIFO_MODE must be set to FIFO36_72 when attribute DATA_WIDTH = 72."); + finish_error = 1; + end + default : begin + $display("Attribute Syntax Error : The attribute DATA_WIDTH on FIFO36E1 instance %m is set to %d. Legal values for this attribute are 4, 9, 18, 36 or 72.", DATA_WIDTH); + finish_error = 1; + + end + endcase + + + if (finish_error == 1) + $finish; + + + end // initial begin + + + // Matching HW + localparam init_sdp = (FIFO_MODE == "FIFO36_72") ? {INIT[71:68],INIT[35:32],INIT[67:36],INIT[31:0]} : INIT; + localparam srval_sdp = (FIFO_MODE == "FIFO36_72") ? {SRVAL[71:68],SRVAL[35:32],SRVAL[67:36],SRVAL[31:0]} : SRVAL; + + + FF36_INTERNAL_VLOG #(.ALMOST_EMPTY_OFFSET(ALMOST_EMPTY_OFFSET), + .ALMOST_FULL_OFFSET(ALMOST_FULL_OFFSET), + .DATA_WIDTH(DATA_WIDTH), + .DO_REG(DO_REG), + .EN_ECC_WRITE(EN_ECC_WRITE), + .EN_ECC_READ(EN_ECC_READ), + .EN_SYN(EN_SYN), + .FIRST_WORD_FALL_THROUGH(FIRST_WORD_FALL_THROUGH), + .FIFO_MODE(FIFO_MODE), + .INIT(init_sdp), + .SRVAL(srval_sdp)) + + INT_FIFO (.ALMOSTEMPTY(ALMOSTEMPTY), + .ALMOSTFULL(ALMOSTFULL), + .DBITERR(DBITERR), + .DI(DI), + .DIP(DIP), + .DO(DO), + .DOP(DOP), + .ECCPARITY(ECCPARITY), + .EMPTY(EMPTY), + .FULL(FULL), + .GSR(GSR), + .INJECTDBITERR(INJECTDBITERR), + .INJECTSBITERR(INJECTSBITERR), + .RDCLK(RDCLK), + .RDCOUNT(RDCOUNT), + .RDEN(RDEN), + .RDERR(RDERR), + .REGCE(REGCE), + .RST(RST), + .RSTREG(RSTREG), + .SBITERR(SBITERR), + .WRCLK(WRCLK), + .WRCOUNT(WRCOUNT), + .WREN(WREN), + .WRERR(WRERR)); + + + specify + + (RDCLK => DO[0]) = (100, 100); + (RDCLK => DO[1]) = (100, 100); + (RDCLK => DO[2]) = (100, 100); + (RDCLK => DO[3]) = (100, 100); + (RDCLK => DO[4]) = (100, 100); + (RDCLK => DO[5]) = (100, 100); + (RDCLK => DO[6]) = (100, 100); + (RDCLK => DO[7]) = (100, 100); + (RDCLK => DO[8]) = (100, 100); + (RDCLK => DO[9]) = (100, 100); + (RDCLK => DO[10]) = (100, 100); + (RDCLK => DO[11]) = (100, 100); + (RDCLK => DO[12]) = (100, 100); + (RDCLK => DO[13]) = (100, 100); + (RDCLK => DO[14]) = (100, 100); + (RDCLK => DO[15]) = (100, 100); + (RDCLK => DO[16]) = (100, 100); + (RDCLK => DO[17]) = (100, 100); + (RDCLK => DO[18]) = (100, 100); + (RDCLK => DO[19]) = (100, 100); + (RDCLK => DO[20]) = (100, 100); + (RDCLK => DO[21]) = (100, 100); + (RDCLK => DO[22]) = (100, 100); + (RDCLK => DO[23]) = (100, 100); + (RDCLK => DO[24]) = (100, 100); + (RDCLK => DO[25]) = (100, 100); + (RDCLK => DO[26]) = (100, 100); + (RDCLK => DO[27]) = (100, 100); + (RDCLK => DO[28]) = (100, 100); + (RDCLK => DO[29]) = (100, 100); + (RDCLK => DO[30]) = (100, 100); + (RDCLK => DO[31]) = (100, 100); + (RDCLK => DO[32]) = (100, 100); + (RDCLK => DO[33]) = (100, 100); + (RDCLK => DO[34]) = (100, 100); + (RDCLK => DO[35]) = (100, 100); + (RDCLK => DO[36]) = (100, 100); + (RDCLK => DO[37]) = (100, 100); + (RDCLK => DO[38]) = (100, 100); + (RDCLK => DO[39]) = (100, 100); + (RDCLK => DO[40]) = (100, 100); + (RDCLK => DO[41]) = (100, 100); + (RDCLK => DO[42]) = (100, 100); + (RDCLK => DO[43]) = (100, 100); + (RDCLK => DO[44]) = (100, 100); + (RDCLK => DO[45]) = (100, 100); + (RDCLK => DO[46]) = (100, 100); + (RDCLK => DO[47]) = (100, 100); + (RDCLK => DO[48]) = (100, 100); + (RDCLK => DO[49]) = (100, 100); + (RDCLK => DO[50]) = (100, 100); + (RDCLK => DO[51]) = (100, 100); + (RDCLK => DO[52]) = (100, 100); + (RDCLK => DO[53]) = (100, 100); + (RDCLK => DO[54]) = (100, 100); + (RDCLK => DO[55]) = (100, 100); + (RDCLK => DO[56]) = (100, 100); + (RDCLK => DO[57]) = (100, 100); + (RDCLK => DO[58]) = (100, 100); + (RDCLK => DO[59]) = (100, 100); + (RDCLK => DO[60]) = (100, 100); + (RDCLK => DO[61]) = (100, 100); + (RDCLK => DO[62]) = (100, 100); + (RDCLK => DO[63]) = (100, 100); + (RDCLK => DOP[0]) = (100, 100); + (RDCLK => DOP[1]) = (100, 100); + (RDCLK => DOP[2]) = (100, 100); + (RDCLK => DOP[3]) = (100, 100); + (RDCLK => DOP[4]) = (100, 100); + (RDCLK => DOP[5]) = (100, 100); + (RDCLK => DOP[6]) = (100, 100); + (RDCLK => DOP[7]) = (100, 100); + (RDCLK => DBITERR) = (100, 100); + (RDCLK => SBITERR) = (100, 100); + (WRCLK => ECCPARITY[0]) = (100, 100); + (WRCLK => ECCPARITY[1]) = (100, 100); + (WRCLK => ECCPARITY[2]) = (100, 100); + (WRCLK => ECCPARITY[3]) = (100, 100); + (WRCLK => ECCPARITY[4]) = (100, 100); + (WRCLK => ECCPARITY[5]) = (100, 100); + (WRCLK => ECCPARITY[6]) = (100, 100); + (WRCLK => ECCPARITY[7]) = (100, 100); + + (RDCLK => ALMOSTEMPTY) = (100, 100); + (RDCLK => EMPTY) = (100, 100); + (RDCLK => RDCOUNT[0]) = (100, 100); + (RDCLK => RDCOUNT[1]) = (100, 100); + (RDCLK => RDCOUNT[2]) = (100, 100); + (RDCLK => RDCOUNT[3]) = (100, 100); + (RDCLK => RDCOUNT[4]) = (100, 100); + (RDCLK => RDCOUNT[5]) = (100, 100); + (RDCLK => RDCOUNT[6]) = (100, 100); + (RDCLK => RDCOUNT[7]) = (100, 100); + (RDCLK => RDCOUNT[8]) = (100, 100); + (RDCLK => RDCOUNT[9]) = (100, 100); + (RDCLK => RDCOUNT[10]) = (100, 100); + (RDCLK => RDCOUNT[11]) = (100, 100); + (RDCLK => RDCOUNT[12]) = (100, 100); + (RDCLK => RDERR) = (100, 100); + + (WRCLK => ALMOSTFULL) = (100, 100); + (WRCLK => FULL) = (100, 100); + (WRCLK => WRCOUNT[0]) = (100, 100); + (WRCLK => WRCOUNT[1]) = (100, 100); + (WRCLK => WRCOUNT[2]) = (100, 100); + (WRCLK => WRCOUNT[3]) = (100, 100); + (WRCLK => WRCOUNT[4]) = (100, 100); + (WRCLK => WRCOUNT[5]) = (100, 100); + (WRCLK => WRCOUNT[6]) = (100, 100); + (WRCLK => WRCOUNT[7]) = (100, 100); + (WRCLK => WRCOUNT[8]) = (100, 100); + (WRCLK => WRCOUNT[9]) = (100, 100); + (WRCLK => WRCOUNT[10]) = (100, 100); + (WRCLK => WRCOUNT[11]) = (100, 100); + (WRCLK => WRCOUNT[12]) = (100, 100); + (WRCLK => WRERR) = (100, 100); + + specparam PATHPULSE$ = 0; + + endspecify + +endmodule // FIFO36E1 + + +// WARNING !!!: The following model is not an user primitive. +// Please do not modify any part of it. FIFO36E1 may not work properly if do so. +// +`timescale 1 ps/1 ps + +module FF36_INTERNAL_VLOG (ALMOSTEMPTY, ALMOSTFULL, DBITERR, DO, DOP, ECCPARITY, EMPTY, FULL, RDCOUNT, RDERR, SBITERR, WRCOUNT, WRERR, + DI, DIP, GSR, INJECTDBITERR, INJECTSBITERR, RDCLK, RDEN, REGCE, RST, RSTREG, WRCLK, WREN); + + output ALMOSTEMPTY; + output ALMOSTFULL; + output DBITERR; + output [63:0] DO; + output [7:0] DOP; + output [7:0] ECCPARITY; + output EMPTY; + output FULL; + output [12:0] RDCOUNT; + output RDERR; + output SBITERR; + output [12:0] WRCOUNT; + output WRERR; + + input [63:0] DI; + input [7:0] DIP; + input RDCLK; + input RDEN; + input REGCE; + input RST; + input RSTREG; + input WRCLK; + input WREN; + input GSR; + input INJECTDBITERR; + input INJECTSBITERR; + + parameter integer DATA_WIDTH = 4; + parameter integer DO_REG = 1; + parameter EN_SYN = "FALSE"; + parameter FIFO_MODE = "FIFO36"; + parameter FIRST_WORD_FALL_THROUGH = "FALSE"; + parameter ALMOST_EMPTY_OFFSET = 13'h0080; + parameter ALMOST_FULL_OFFSET = 13'h0080; + parameter EN_ECC_WRITE = "FALSE"; + parameter EN_ECC_READ = "FALSE"; + parameter INIT = 72'h0; + parameter SRVAL = 72'h0; + + reg [63:0] do_in = 64'b0; + reg [63:0] do_out = 64'b0; + reg [63:0] do_outreg = 64'b0; + reg [63:0] do_out_mux = 64'b0; + wire [63:0] do_out_out; + reg [7:0] dop_in = 8'b0, dop_out = 8'b0; + wire [7:0] dop_out_out; + reg [7:0] dop_outreg = 8'b0, dop_out_mux = 8'b0; + reg almostempty_out = 1'b1, almostfull_out = 1'b0, empty_out = 1'b1; + reg full_out = 1'b0, rderr_out = 0, wrerr_out = 0; + + reg dbiterr_out = 0, sbiterr_out = 0; + reg dbiterr_out_out = 0, sbiterr_out_out = 0; + reg [71:0] ecc_bit_position; + reg [7:0] eccparity_out = 8'b0; + reg [7:0] dopr_ecc, dop_buf, dip_ecc, dip_int; + reg [63:0] do_buf, di_in_ecc_corrected; + reg [7:0] syndrome, dip_in_ecc_corrected; + + wire [63:0] di_in; + wire [7:0] dip_in; + wire rdclk_in, rden_in, rst_in, rstreg_in, wrclk_in, wren_in; + wire regce_in, gsr_in; + wire injectdbiterr_in, injectsbiterr_in; + + reg rden_reg, wren_reg; + reg [12:0] ae_empty, ae_full; + reg fwft; + + integer addr_limit, rd_prefetch = 0; + integer wr1_addr = 0; + + reg [12:0] rdcount_out = 13'b0, wr_addr = 0, rd_addr = 0; + reg [12:0] rdcount_out_out = 13'b0, wr_addr_out = 13'b0; + reg rd_flag = 0, rdcount_flag = 0, rdprefetch_flag = 0, wr_flag = 0; + reg wr1_flag = 0, awr_flag = 0; + reg [3:0] almostfull_int = 4'b0000, almostempty_int = 4'b1111; + + reg [3:0] full_int = 4'b0000; + reg [3:0] empty_ram = 4'b1111; + reg [8:0] i, j; + reg rst_tmp1 = 0, rst_tmp2 = 0; + reg [2:0] rst_rdckreg = 3'b0, rst_wrckreg = 3'b0; + reg rst_rdclk_flag = 0, rst_wrclk_flag = 0; + reg en_ecc_write_int, en_ecc_read_int, finish_error = 0; + reg [63:0] di_ecc_col; + + +// xilinx_internal_parameter on + // WARNING !!!: This model may not work properly if the following parameter is changed. + parameter integer FIFO_SIZE = 36; +// xilinx_internal_parameter off + + + // Determinte memory size + localparam mem_size4 = (FIFO_SIZE == 18) ? 4095 : (FIFO_SIZE == 36) ? 8191 : 0; + localparam mem_size9 = (FIFO_SIZE == 18) ? 2047 : (FIFO_SIZE == 36) ? 4095 : 0; + localparam mem_size18 = (FIFO_SIZE == 18) ? 1023 : (FIFO_SIZE == 36) ? 2047 : 0; + localparam mem_size36 = (FIFO_SIZE == 18) ? 511 : (FIFO_SIZE == 36) ? 1023 : 0; + localparam mem_size72 = (FIFO_SIZE == 18) ? 0 : (FIFO_SIZE == 36) ? 511 : 0; + + localparam mem_depth = (DATA_WIDTH == 4) ? mem_size4 : (DATA_WIDTH == 9) ? mem_size9 : + (DATA_WIDTH == 18) ? mem_size18 : (DATA_WIDTH == 36) ? mem_size36 : + (DATA_WIDTH == 72) ? mem_size72 : 0; + + localparam mem_width = (DATA_WIDTH == 4) ? 3 : (DATA_WIDTH == 9) ? 7 : + (DATA_WIDTH == 18) ? 15 : (DATA_WIDTH == 36) ? 31 : (DATA_WIDTH == 72) ? 63 : 0; + + localparam memp_depth = (DATA_WIDTH == 4) ? 0 : (DATA_WIDTH == 9) ? mem_size9 : + (DATA_WIDTH == 18) ? mem_size18 : (DATA_WIDTH == 36) ? mem_size36 : + (DATA_WIDTH == 72) ? mem_size72 : 0; + + localparam memp_width = (DATA_WIDTH == 4 || DATA_WIDTH == 9) ? 0 : + (DATA_WIDTH == 18) ? 1 : (DATA_WIDTH == 36) ? 3 : (DATA_WIDTH == 72) ? 7 : 0; + + reg [mem_width : 0] mem [mem_depth : 0]; + reg [memp_width : 0] memp [memp_depth : 0]; + reg sync; + + + // Input and output ports + assign di_in = DI; + assign dip_in = DIP; + assign DO = do_out_out; + assign DOP = dop_out_out; + assign rdclk_in = RDCLK; + assign regce_in = REGCE; + assign rden_in = RDEN; + assign rst_in = RST; + assign rstreg_in = RSTREG; + assign wrclk_in = WRCLK; + assign wren_in = WREN; + assign gsr_in = GSR; + + assign ALMOSTEMPTY = almostempty_out; + assign ALMOSTFULL = almostfull_out; + assign EMPTY = empty_out; + assign FULL = full_out; + assign RDERR = rderr_out; + assign WRERR = wrerr_out; + assign SBITERR = sbiterr_out_out; + assign DBITERR = dbiterr_out_out; + assign ECCPARITY = eccparity_out; + assign RDCOUNT = rdcount_out_out; + assign WRCOUNT = wr_addr_out; + assign injectdbiterr_in = INJECTDBITERR; + assign injectsbiterr_in = INJECTSBITERR; + + + initial begin + + // Determine address limit + case (DATA_WIDTH) + 4 : begin + if (FIFO_SIZE == 36) + addr_limit = 8192; + else + addr_limit = 4096; + end + 9 : begin + if (FIFO_SIZE == 36) + addr_limit = 4096; + else + addr_limit = 2048; + end + 18 : begin + if (FIFO_SIZE == 36) + addr_limit = 2048; + else + addr_limit = 1024; + end + 36 : begin + if (FIFO_SIZE == 36) + addr_limit = 1024; + else + addr_limit = 512; + end + 72 : begin + addr_limit = 512; + end + default : + begin + $display("Attribute Syntax Error : The attribute DATA_WIDTH on FF36_INTERNAL_VLOG instance %m is set to %d. Legal values for this attribute are 4, 9, 18, 36 or 72.", DATA_WIDTH); + finish_error = 1; + end + endcase + + + case (EN_SYN) + "FALSE" : sync = 0; + "TRUE" : sync = 1; + default : begin + $display("Attribute Syntax Error : The attribute EN_SYN on FF36_INTERNAL_VLOG instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", EN_SYN); + finish_error = 1; + end + endcase // case(EN_SYN) + + + case (FIRST_WORD_FALL_THROUGH) + "FALSE" : begin + fwft = 0; + if (EN_SYN == "FALSE") begin + ae_empty = ALMOST_EMPTY_OFFSET - 1; + ae_full = ALMOST_FULL_OFFSET; + end + else begin + ae_empty = ALMOST_EMPTY_OFFSET; + ae_full = ALMOST_FULL_OFFSET; + end + end + "TRUE" : begin + fwft = 1; + ae_empty = ALMOST_EMPTY_OFFSET - 2; + ae_full = ALMOST_FULL_OFFSET; + end + default : begin + $display("Attribute Syntax Error : The attribute FIRST_WORD_FALL_THROUGH on FF36_INTERNAL_VLOG instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", FIRST_WORD_FALL_THROUGH); + finish_error = 1; + end + endcase + + + // Setup ranges for almostfull and almostempty + if (EN_SYN == "FALSE") begin + + if (fwft == 1'b0) begin + + if ((ALMOST_EMPTY_OFFSET < 5) || (ALMOST_EMPTY_OFFSET > addr_limit - 5)) begin + $display("Attribute Syntax Error : The attribute ALMOST_EMPTY_OFFSET on FF36_INTERNAL_VLOG instance %m is set to %d. Legal values for this attribute are %d to %d", ALMOST_EMPTY_OFFSET, 5, addr_limit - 5); + finish_error = 1; + end + + if ((ALMOST_FULL_OFFSET < 4) || (ALMOST_FULL_OFFSET > addr_limit - 5)) begin + $display("Attribute Syntax Error : The attribute ALMOST_FULL_OFFSET on FF36_INTERNAL_VLOG instance %m is set to %d. Legal values for this attribute are %d to %d", ALMOST_FULL_OFFSET, 4, addr_limit - 5); + finish_error = 1; + end + + end // if (fwft == 1'b0) + else begin + + if ((ALMOST_EMPTY_OFFSET < 6) || (ALMOST_EMPTY_OFFSET > addr_limit - 4)) begin + $display("Attribute Syntax Error : The attribute ALMOST_EMPTY_OFFSET on FF36_INTERNAL_VLOG instance %m is set to %d. Legal values for this attribute are %d to %d", ALMOST_EMPTY_OFFSET, 6, addr_limit - 4); + finish_error = 1; + end + + if ((ALMOST_FULL_OFFSET < 4) || (ALMOST_FULL_OFFSET > addr_limit - 5)) begin + $display("Attribute Syntax Error : The attribute ALMOST_FULL_OFFSET on FF36_INTERNAL_VLOG instance %m is set to %d. Legal values for this attribute are %d to %d", ALMOST_FULL_OFFSET, 4, addr_limit - 5); + finish_error = 1; + end + + end // else: !if(fwft == 1'b0) + end + else begin + + if ((fwft == 1'b0) && ((ALMOST_EMPTY_OFFSET < 1) || (ALMOST_EMPTY_OFFSET > addr_limit - 2))) begin + $display("Attribute Syntax Error : The attribute ALMOST_EMPTY_OFFSET on FF36_INTERNAL_VLOG instance %m is set to %d. Legal values for this attribute are %d to %d", ALMOST_EMPTY_OFFSET, 1, addr_limit - 2); + finish_error = 1; + end + + if ((fwft == 1'b0) && ((ALMOST_FULL_OFFSET < 1) || (ALMOST_FULL_OFFSET > addr_limit - 2))) begin + $display("Attribute Syntax Error : The attribute ALMOST_FULL_OFFSET on FF36_INTERNAL_VLOG instance %m is set to %d. Legal values for this attribute are %d to %d", ALMOST_FULL_OFFSET, 1, addr_limit - 2); + finish_error = 1; + end + + end // else: !if(EN_SYN == "FALSE") + + + // DRC for fwft in sync mode + if (fwft == 1'b1 && EN_SYN == "TRUE") begin + $display("DRC Error : First word fall through is not supported in synchronous mode on FF36_INTERNAL_VLOG instance %m."); + finish_error = 1; + end + + if (EN_SYN == "FALSE" && DO_REG == 0) begin + $display("DRC Error : DO_REG = 0 is invalid when EN_SYN is set to FALSE on FF36_INTERNAL_VLOG instance %m."); + finish_error = 1; + end + + + case (EN_ECC_WRITE) + "TRUE" : en_ecc_write_int <= 1; + "FALSE" : en_ecc_write_int <= 0; + default : begin + $display("Attribute Syntax Error : The attribute EN_ECC_WRITE on FF36_INTERNAL_VLOG instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", EN_ECC_WRITE); + finish_error = 1; + end + endcase + + + case (EN_ECC_READ) + "TRUE" : en_ecc_read_int <= 1; + "FALSE" : en_ecc_read_int <= 0; + default : begin + $display("Attribute Syntax Error : The attribute EN_ECC_READ on FF36_INTERNAL_VLOG instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", EN_ECC_READ); + finish_error = 1; + end + endcase + + + if ((EN_ECC_READ == "TRUE" || EN_ECC_WRITE == "TRUE") && DATA_WIDTH != 72) begin + $display("DRC Error : The attribute DATA_WIDTH must be set to 72 when FF36_INTERNAL_VLOG is configured in the ECC mode."); + finish_error = 1; + end + + + if (finish_error == 1) + $finish; + + + end // initial begin + + + // GSR and RST + always @(gsr_in) + if (gsr_in == 1'b1) begin + if (DO_REG == 1'b1 && sync == 1'b1) begin + assign do_out = INIT[0 +: mem_width+1]; + assign dop_out = INIT[mem_width+1 +: memp_width+1]; + assign do_outreg = INIT[0 +: mem_width+1]; + assign dop_outreg = INIT[mem_width+1 +: memp_width+1]; + end + else begin + assign do_out = 64'b0; + assign dop_out = 8'b0; + assign do_outreg = 64'b0; + assign dop_outreg = 8'b0; + end + end + else if (gsr_in == 1'b0) begin + deassign do_out; + deassign dop_out; + deassign do_outreg; + deassign dop_outreg; + end + + + always @(gsr_in or rst_in) + if (gsr_in == 1'b1 || rst_in == 1'b1) begin + assign almostempty_int = 4'b1111; + assign almostempty_out = 1'b1; + assign almostfull_int = 4'b0000; + assign almostfull_out = 1'b0; + assign do_in = 64'b00000000000000000000000000000000; + assign dop_in = 8'b0000; + assign empty_ram = 4'b1111; + assign empty_out = 1'b1; + assign full_int = 4'b0000; + assign full_out = 1'b0; + assign rdcount_out = 13'b0; + assign rdcount_out_out = 13'b0; + assign wr_addr_out = 13'b0; + assign rderr_out = 0; + assign wrerr_out = 0; + assign rd_addr = 0; + assign rd_prefetch = 0; + assign wr_addr = 0; + assign wr1_addr = 0; + assign rdcount_flag = 0; + assign rd_flag = 0; + assign rdprefetch_flag = 0; + assign wr_flag = 0; + assign wr1_flag = 0; + assign awr_flag = 0; + end + else if (gsr_in == 1'b0 && rst_in == 1'b0) begin + deassign almostempty_int; + deassign almostempty_out; + deassign almostfull_int; + deassign almostfull_out; + deassign do_in; + deassign dop_in; + deassign empty_ram; + deassign empty_out; + deassign full_int; + deassign full_out; + deassign rdcount_out; + deassign rdcount_out_out; + deassign wr_addr_out; + deassign rderr_out; + deassign wrerr_out; + deassign rd_addr; + deassign rd_prefetch; + deassign wr_addr; + deassign wr1_addr; + deassign rdcount_flag; + deassign rd_flag; + deassign rdprefetch_flag; + deassign wr_flag; + deassign wr1_flag; + deassign awr_flag; + end + + + // DRC + always @(rst_in or rden_in or wren_in) begin + if (rst_in ==1 && rden_in==1 ) + $display("Warning : At time %t, RDEN on FF36_INTERNAL_VLOG instance %m is high when RST is high. RDEN should be low during reset.", $stime); + if (rst_in ==1 && wren_in ==1) + $display("Warning : At time %t, WREN on FF36_INTERNAL_VLOG instance %m is high when RST is high. WREN should be low during reset.", $stime); + end + + + // 3 clock cycles required for RST, if not X outputs + always @(posedge rdclk_in) begin + rst_rdckreg[0] <= rst_in; + rst_rdckreg[1] <= rst_rdckreg[0] & rst_in; + rst_rdckreg[2] <= rst_rdckreg[1] & rst_in; + end + + always @(posedge wrclk_in) begin + rst_wrckreg[0] <= rst_in ; + rst_wrckreg[1] <= rst_wrckreg[0] & rst_in; + rst_wrckreg[2] <= rst_wrckreg[1] & rst_in; + end + + always @(rst_in) + begin + rst_tmp1 = rst_in; + rst_rdclk_flag = 0; + rst_wrclk_flag = 0; + + if (rst_tmp1 == 0 && rst_tmp2 == 1) begin + if ((rst_rdckreg[2] & rst_rdckreg[1] & rst_rdckreg[0]) == 0) begin + $display("Error : At time %t, RST high on FF36_INTERNAL_VLOG instance %m is short than three RDCLK clock cycles. RST high need be more that three RDCLK clock cycles.", $stime); + rst_rdclk_flag = 1; + end + + if ((rst_wrckreg[2] & rst_wrckreg[1] & rst_wrckreg[0]) == 0) begin + $display("Error : At time %t, RST high on FF36_INTERNAL_VLOG instance %m is short than three WRCLK clock cycles. RST high need be more that three WRCLK clock cycles.", $stime); + rst_wrclk_flag = 1; + end + + if ((rst_rdclk_flag | rst_wrclk_flag) == 1) begin + assign do_out = 64'bx; + assign dop_out = 8'bx; + assign do_outreg = 64'bx; + assign dop_outreg = 8'bx; + assign full_out = 1'bX; + assign empty_out = 1'bX; + assign rderr_out = 1'bX; + assign wrerr_out = 1'bX; + assign eccparity_out = 8'bx; + assign rdcount_out = 13'bx; + assign rdcount_out_out = 13'bx; + assign wr_addr_out = 13'bx; + assign wr_addr = 13'bx; + assign wr1_addr = 0; + assign almostempty_int = 4'b1111; + assign almostempty_out = 1'bx; + assign almostfull_int = 4'b0000; + assign almostfull_out = 1'bx; + assign do_in = 64'b00000000000000000000000000000000; + assign dop_in = 8'b0000; + assign empty_ram = 4'b1111; + assign full_int = 4'b0000; + assign rd_addr = 0; + assign rd_prefetch = 0; + assign rdcount_flag = 0; + assign rd_flag = 0; + assign rdprefetch_flag = 0; + assign wr_flag = 0; + assign wr1_flag = 0; + assign awr_flag = 0; + + end + else if (gsr_in == 1'b0 && rst_in == 1'b0) begin + deassign do_out; + deassign dop_out; + deassign do_outreg; + deassign dop_outreg; + deassign full_out; + deassign empty_out; + deassign rderr_out; + deassign wrerr_out; + deassign eccparity_out; + deassign rdcount_out; + rdcount_out = 13'b0; + deassign wr_addr; + wr_addr = 13'b0; + deassign rdcount_out_out; + deassign wr_addr_out; + deassign wr1_addr; + deassign almostempty_int; + deassign almostempty_out; + deassign almostfull_int; + deassign almostfull_out; + deassign do_in; + deassign dop_in; + deassign empty_ram; + deassign full_int; + deassign rd_addr; + deassign rd_prefetch; + deassign rdcount_flag; + deassign rd_flag; + deassign rdprefetch_flag; + deassign wr_flag; + deassign wr1_flag; + deassign awr_flag; + end + end // if (rst_tmp1 == 0 && rst_tmp2 == 1) + rst_tmp2 = rst_tmp1; + + end + + + // read clock + always @(posedge rdclk_in) begin + + // SRVAL in output register mode + if (DO_REG == 1 && sync == 1'b1 && rstreg_in === 1'b1) begin + + do_outreg = SRVAL[0 +: mem_width+1]; + + if (mem_width+1 >= 8) + dop_outreg = SRVAL[mem_width+1 +: memp_width+1]; + end + + + if (rst_in === 1'b0) begin + + // sync mode + if (sync == 1'b1) begin + + // output register + if (DO_REG == 1 && regce_in === 1'b1 && rstreg_in === 1'b0) begin + + do_outreg = do_out; + dop_outreg = dop_out; + dbiterr_out_out = dbiterr_out; // reg out in sync mode + sbiterr_out_out = sbiterr_out; + + end + + + if (rden_in == 1'b1) begin + + if (empty_out == 1'b0) begin + + do_buf = mem[rdcount_out]; + dop_buf = memp[rdcount_out]; + + // ECC decode + if (EN_ECC_READ == "TRUE") begin + + // regenerate parity + dopr_ecc[0] = do_buf[0]^do_buf[1]^do_buf[3]^do_buf[4]^do_buf[6]^do_buf[8] + ^do_buf[10]^do_buf[11]^do_buf[13]^do_buf[15]^do_buf[17]^do_buf[19] + ^do_buf[21]^do_buf[23]^do_buf[25]^do_buf[26]^do_buf[28] + ^do_buf[30]^do_buf[32]^do_buf[34]^do_buf[36]^do_buf[38] + ^do_buf[40]^do_buf[42]^do_buf[44]^do_buf[46]^do_buf[48] + ^do_buf[50]^do_buf[52]^do_buf[54]^do_buf[56]^do_buf[57]^do_buf[59] + ^do_buf[61]^do_buf[63]; + + dopr_ecc[1] = do_buf[0]^do_buf[2]^do_buf[3]^do_buf[5]^do_buf[6]^do_buf[9] + ^do_buf[10]^do_buf[12]^do_buf[13]^do_buf[16]^do_buf[17] + ^do_buf[20]^do_buf[21]^do_buf[24]^do_buf[25]^do_buf[27]^do_buf[28] + ^do_buf[31]^do_buf[32]^do_buf[35]^do_buf[36]^do_buf[39] + ^do_buf[40]^do_buf[43]^do_buf[44]^do_buf[47]^do_buf[48] + ^do_buf[51]^do_buf[52]^do_buf[55]^do_buf[56]^do_buf[58]^do_buf[59] + ^do_buf[62]^do_buf[63]; + + dopr_ecc[2] = do_buf[1]^do_buf[2]^do_buf[3]^do_buf[7]^do_buf[8]^do_buf[9] + ^do_buf[10]^do_buf[14]^do_buf[15]^do_buf[16]^do_buf[17] + ^do_buf[22]^do_buf[23]^do_buf[24]^do_buf[25]^do_buf[29] + ^do_buf[30]^do_buf[31]^do_buf[32]^do_buf[37]^do_buf[38]^do_buf[39] + ^do_buf[40]^do_buf[45]^do_buf[46]^do_buf[47]^do_buf[48] + ^do_buf[53]^do_buf[54]^do_buf[55]^do_buf[56] + ^do_buf[60]^do_buf[61]^do_buf[62]^do_buf[63]; + + dopr_ecc[3] = do_buf[4]^do_buf[5]^do_buf[6]^do_buf[7]^do_buf[8]^do_buf[9] + ^do_buf[10]^do_buf[18]^do_buf[19] + ^do_buf[20]^do_buf[21]^do_buf[22]^do_buf[23]^do_buf[24]^do_buf[25] + ^do_buf[33]^do_buf[34]^do_buf[35]^do_buf[36]^do_buf[37]^do_buf[38] + ^do_buf[39]^do_buf[40]^do_buf[49]^do_buf[50] + ^do_buf[51]^do_buf[52]^do_buf[53]^do_buf[54]^do_buf[55]^do_buf[56]; + + dopr_ecc[4] = do_buf[11]^do_buf[12]^do_buf[13]^do_buf[14]^do_buf[15]^do_buf[16] + ^do_buf[17]^do_buf[18]^do_buf[19]^do_buf[20]^do_buf[21]^do_buf[22] + ^do_buf[23]^do_buf[24]^do_buf[25]^do_buf[41]^do_buf[42]^do_buf[43] + ^do_buf[44]^do_buf[45]^do_buf[46]^do_buf[47]^do_buf[48]^do_buf[49] + ^do_buf[50]^do_buf[51]^do_buf[52]^do_buf[53]^do_buf[54]^do_buf[55]^do_buf[56]; + + + dopr_ecc[5] = do_buf[26]^do_buf[27]^do_buf[28]^do_buf[29] + ^do_buf[30]^do_buf[31]^do_buf[32]^do_buf[33]^do_buf[34]^do_buf[35] + ^do_buf[36]^do_buf[37]^do_buf[38]^do_buf[39]^do_buf[40] + ^do_buf[41]^do_buf[42]^do_buf[43]^do_buf[44]^do_buf[45] + ^do_buf[46]^do_buf[47]^do_buf[48]^do_buf[49]^do_buf[50] + ^do_buf[51]^do_buf[52]^do_buf[53]^do_buf[54]^do_buf[55]^do_buf[56]; + + dopr_ecc[6] = do_buf[57]^do_buf[58]^do_buf[59] + ^do_buf[60]^do_buf[61]^do_buf[62]^do_buf[63]; + + dopr_ecc[7] = dop_buf[0]^dop_buf[1]^dop_buf[2]^dop_buf[3]^dop_buf[4]^dop_buf[5] + ^dop_buf[6]^do_buf[0]^do_buf[1]^do_buf[2]^do_buf[3]^do_buf[4] + ^do_buf[5]^do_buf[6]^do_buf[7]^do_buf[8]^do_buf[9]^do_buf[10] + ^do_buf[11]^do_buf[12]^do_buf[13]^do_buf[14]^do_buf[15]^do_buf[16] + ^do_buf[17]^do_buf[18]^do_buf[19]^do_buf[20]^do_buf[21]^do_buf[22] + ^do_buf[23]^do_buf[24]^do_buf[25]^do_buf[26]^do_buf[27]^do_buf[28] + ^do_buf[29]^do_buf[30]^do_buf[31]^do_buf[32]^do_buf[33]^do_buf[34] + ^do_buf[35]^do_buf[36]^do_buf[37]^do_buf[38]^do_buf[39]^do_buf[40] + ^do_buf[41]^do_buf[42]^do_buf[43]^do_buf[44]^do_buf[45]^do_buf[46] + ^do_buf[47]^do_buf[48]^do_buf[49]^do_buf[50]^do_buf[51]^do_buf[52] + ^do_buf[53]^do_buf[54]^do_buf[55]^do_buf[56]^do_buf[57]^do_buf[58] + ^do_buf[59]^do_buf[60]^do_buf[61]^do_buf[62]^do_buf[63]; + + syndrome = dopr_ecc ^ dop_buf; + + // checking error + if (syndrome !== 0) begin + + if (syndrome[7]) begin // dectect single bit error + + ecc_bit_position = {do_buf[63:57], dop_buf[6], do_buf[56:26], dop_buf[5], do_buf[25:11], dop_buf[4], do_buf[10:4], dop_buf[3], do_buf[3:1], dop_buf[2], do_buf[0], dop_buf[1:0], dop_buf[7]}; + + if (syndrome[6:0] > 71) begin + $display ("DRC Error : Simulation halted due Corrupted DIP. To correct this problem, make sure that reliable data is fed to the DIP. The correct Parity must be generated by a Hamming code encoder or encoder in the Block RAM. The output from the model is unreliable if there are more than 2 bit errors. The model doesn't warn if there is sporadic input of more than 2 bit errors due to the limitation in Hamming code."); + $finish; + end + + ecc_bit_position[syndrome[6:0]] = ~ecc_bit_position[syndrome[6:0]]; // correct single bit error in the output + + di_in_ecc_corrected = {ecc_bit_position[71:65], ecc_bit_position[63:33], ecc_bit_position[31:17], ecc_bit_position[15:9], ecc_bit_position[7:5], ecc_bit_position[3]}; // correct single bit error in the memory + + do_buf = di_in_ecc_corrected; + + dip_in_ecc_corrected = {ecc_bit_position[0], ecc_bit_position[64], ecc_bit_position[32], ecc_bit_position[16], ecc_bit_position[8], ecc_bit_position[4], ecc_bit_position[2:1]}; // correct single bit error in the parity memory + + dop_buf = dip_in_ecc_corrected; + + dbiterr_out = 0; // latch out in sync mode + sbiterr_out = 1; + + end + else if (!syndrome[7]) begin // double bit error + sbiterr_out = 0; + dbiterr_out = 1; + + end + end // if (syndrome !== 0) + else begin + dbiterr_out = 0; + sbiterr_out = 0; + + end // else: !if(syndrome !== 0) + + end // if (EN_ECC_READ == "TRUE") + // end ecc decode + + + if (DO_REG == 0) begin + dbiterr_out_out = dbiterr_out; + sbiterr_out_out = sbiterr_out; + end + + + do_out = do_buf; + dop_out = dop_buf; + + rdcount_out = (rdcount_out + 1) % addr_limit; + + if (rdcount_out == 0) + rdcount_flag = ~rdcount_flag; + + end + end + + + rderr_out = (rden_in == 1'b1) && (empty_out == 1'b1); + + + if (wren_in == 1'b1) begin + empty_out = 1'b0; + end + else if (rdcount_out == wr_addr && rdcount_flag == wr_flag) + empty_out = 1'b1; + + if ((((rdcount_out + ae_empty) >= wr_addr) && (rdcount_flag == wr_flag)) || (((rdcount_out + ae_empty) >= (wr_addr + addr_limit) && (rdcount_flag != wr_flag)))) begin + almostempty_out = 1'b1; + end + + if ((((rdcount_out + addr_limit) > (wr_addr + ae_full)) && (rdcount_flag == wr_flag)) || ((rdcount_out > (wr_addr + ae_full)) && (rdcount_flag != wr_flag))) begin + if (wr_addr <= wr_addr + ae_full || rdcount_flag == wr_flag) + almostfull_out = 1'b0; + end + + end // if (sync == 1'b1) + + // async mode + else if (sync == 1'b0) begin + + rden_reg = rden_in; + if (fwft == 1'b0) begin + if ((rden_reg == 1'b1) && (rd_addr != rdcount_out)) begin + do_out = do_in; + if (DATA_WIDTH != 4) + dop_out = dop_in; + rd_addr = (rd_addr + 1) % addr_limit; + if (rd_addr == 0) + rd_flag = ~rd_flag; + + dbiterr_out_out = dbiterr_out; // reg out in async mode + sbiterr_out_out = sbiterr_out; + + end + if (((rd_addr == rdcount_out) && (empty_ram[3] == 1'b0)) || + ((rden_reg == 1'b1) && (empty_ram[1] == 1'b0))) begin + + do_buf = mem[rdcount_out]; + dop_buf = memp[rdcount_out]; + + // ECC decode + if (EN_ECC_READ == "TRUE") begin + + // regenerate parity + dopr_ecc[0] = do_buf[0]^do_buf[1]^do_buf[3]^do_buf[4]^do_buf[6]^do_buf[8] + ^do_buf[10]^do_buf[11]^do_buf[13]^do_buf[15]^do_buf[17]^do_buf[19] + ^do_buf[21]^do_buf[23]^do_buf[25]^do_buf[26]^do_buf[28] + ^do_buf[30]^do_buf[32]^do_buf[34]^do_buf[36]^do_buf[38] + ^do_buf[40]^do_buf[42]^do_buf[44]^do_buf[46]^do_buf[48] + ^do_buf[50]^do_buf[52]^do_buf[54]^do_buf[56]^do_buf[57]^do_buf[59] + ^do_buf[61]^do_buf[63]; + + dopr_ecc[1] = do_buf[0]^do_buf[2]^do_buf[3]^do_buf[5]^do_buf[6]^do_buf[9] + ^do_buf[10]^do_buf[12]^do_buf[13]^do_buf[16]^do_buf[17] + ^do_buf[20]^do_buf[21]^do_buf[24]^do_buf[25]^do_buf[27]^do_buf[28] + ^do_buf[31]^do_buf[32]^do_buf[35]^do_buf[36]^do_buf[39] + ^do_buf[40]^do_buf[43]^do_buf[44]^do_buf[47]^do_buf[48] + ^do_buf[51]^do_buf[52]^do_buf[55]^do_buf[56]^do_buf[58]^do_buf[59] + ^do_buf[62]^do_buf[63]; + + dopr_ecc[2] = do_buf[1]^do_buf[2]^do_buf[3]^do_buf[7]^do_buf[8]^do_buf[9] + ^do_buf[10]^do_buf[14]^do_buf[15]^do_buf[16]^do_buf[17] + ^do_buf[22]^do_buf[23]^do_buf[24]^do_buf[25]^do_buf[29] + ^do_buf[30]^do_buf[31]^do_buf[32]^do_buf[37]^do_buf[38]^do_buf[39] + ^do_buf[40]^do_buf[45]^do_buf[46]^do_buf[47]^do_buf[48] + ^do_buf[53]^do_buf[54]^do_buf[55]^do_buf[56] + ^do_buf[60]^do_buf[61]^do_buf[62]^do_buf[63]; + + dopr_ecc[3] = do_buf[4]^do_buf[5]^do_buf[6]^do_buf[7]^do_buf[8]^do_buf[9] + ^do_buf[10]^do_buf[18]^do_buf[19] + ^do_buf[20]^do_buf[21]^do_buf[22]^do_buf[23]^do_buf[24]^do_buf[25] + ^do_buf[33]^do_buf[34]^do_buf[35]^do_buf[36]^do_buf[37]^do_buf[38] + ^do_buf[39]^do_buf[40]^do_buf[49]^do_buf[50] + ^do_buf[51]^do_buf[52]^do_buf[53]^do_buf[54]^do_buf[55]^do_buf[56]; + + dopr_ecc[4] = do_buf[11]^do_buf[12]^do_buf[13]^do_buf[14]^do_buf[15]^do_buf[16] + ^do_buf[17]^do_buf[18]^do_buf[19]^do_buf[20]^do_buf[21]^do_buf[22] + ^do_buf[23]^do_buf[24]^do_buf[25]^do_buf[41]^do_buf[42]^do_buf[43] + ^do_buf[44]^do_buf[45]^do_buf[46]^do_buf[47]^do_buf[48]^do_buf[49] + ^do_buf[50]^do_buf[51]^do_buf[52]^do_buf[53]^do_buf[54]^do_buf[55]^do_buf[56]; + + + dopr_ecc[5] = do_buf[26]^do_buf[27]^do_buf[28]^do_buf[29] + ^do_buf[30]^do_buf[31]^do_buf[32]^do_buf[33]^do_buf[34]^do_buf[35] + ^do_buf[36]^do_buf[37]^do_buf[38]^do_buf[39]^do_buf[40] + ^do_buf[41]^do_buf[42]^do_buf[43]^do_buf[44]^do_buf[45] + ^do_buf[46]^do_buf[47]^do_buf[48]^do_buf[49]^do_buf[50] + ^do_buf[51]^do_buf[52]^do_buf[53]^do_buf[54]^do_buf[55]^do_buf[56]; + + dopr_ecc[6] = do_buf[57]^do_buf[58]^do_buf[59] + ^do_buf[60]^do_buf[61]^do_buf[62]^do_buf[63]; + + dopr_ecc[7] = dop_buf[0]^dop_buf[1]^dop_buf[2]^dop_buf[3]^dop_buf[4]^dop_buf[5] + ^dop_buf[6]^do_buf[0]^do_buf[1]^do_buf[2]^do_buf[3]^do_buf[4] + ^do_buf[5]^do_buf[6]^do_buf[7]^do_buf[8]^do_buf[9]^do_buf[10] + ^do_buf[11]^do_buf[12]^do_buf[13]^do_buf[14]^do_buf[15]^do_buf[16] + ^do_buf[17]^do_buf[18]^do_buf[19]^do_buf[20]^do_buf[21]^do_buf[22] + ^do_buf[23]^do_buf[24]^do_buf[25]^do_buf[26]^do_buf[27]^do_buf[28] + ^do_buf[29]^do_buf[30]^do_buf[31]^do_buf[32]^do_buf[33]^do_buf[34] + ^do_buf[35]^do_buf[36]^do_buf[37]^do_buf[38]^do_buf[39]^do_buf[40] + ^do_buf[41]^do_buf[42]^do_buf[43]^do_buf[44]^do_buf[45]^do_buf[46] + ^do_buf[47]^do_buf[48]^do_buf[49]^do_buf[50]^do_buf[51]^do_buf[52] + ^do_buf[53]^do_buf[54]^do_buf[55]^do_buf[56]^do_buf[57]^do_buf[58] + ^do_buf[59]^do_buf[60]^do_buf[61]^do_buf[62]^do_buf[63]; + + syndrome = dopr_ecc ^ dop_buf; + + if (syndrome !== 0) begin + + if (syndrome[7]) begin // dectect single bit error + + ecc_bit_position = {do_buf[63:57], dop_buf[6], do_buf[56:26], dop_buf[5], do_buf[25:11], dop_buf[4], do_buf[10:4], dop_buf[3], do_buf[3:1], dop_buf[2], do_buf[0], dop_buf[1:0], dop_buf[7]}; + + if (syndrome[6:0] > 71) begin + $display ("DRC Error : Simulation halted due Corrupted DIP. To correct this problem, make sure that reliable data is fed to the DIP. The correct Parity must be generated by a Hamming code encoder or encoder in the Block RAM. The output from the model is unreliable if there are more than 2 bit errors. The model doesn't warn if there is sporadic input of more than 2 bit errors due to the limitation in Hamming code."); + $finish; + end + + ecc_bit_position[syndrome[6:0]] = ~ecc_bit_position[syndrome[6:0]]; // correct single bit error in the output + + di_in_ecc_corrected = {ecc_bit_position[71:65], ecc_bit_position[63:33], ecc_bit_position[31:17], ecc_bit_position[15:9], ecc_bit_position[7:5], ecc_bit_position[3]}; // correct single bit error in the memory + + do_buf = di_in_ecc_corrected; + + dip_in_ecc_corrected = {ecc_bit_position[0], ecc_bit_position[64], ecc_bit_position[32], ecc_bit_position[16], ecc_bit_position[8], ecc_bit_position[4], ecc_bit_position[2:1]}; // correct single bit error in the parity memory + + dop_buf = dip_in_ecc_corrected; + + dbiterr_out = 0; + sbiterr_out = 1; + + end + else if (!syndrome[7]) begin // double bit error + sbiterr_out = 0; + dbiterr_out = 1; + + end + end // if (syndrome !== 0) + else begin + dbiterr_out = 0; + sbiterr_out = 0; + + end // else: !if(syndrome !== 0) + + end // if (EN_ECC_READ == "TRUE") + // end ecc decode + + do_in = do_buf; + dop_in = dop_buf; + + #1; + rdcount_out = (rdcount_out + 1) % addr_limit; + if (rdcount_out == 0) begin + rdcount_flag = ~rdcount_flag; + end + end + end + + // First word fall through = true + if (fwft == 1'b1) begin + + if ((rden_reg == 1'b1) && (rd_addr != rd_prefetch)) begin + rd_prefetch = (rd_prefetch + 1) % addr_limit; + if (rd_prefetch == 0) + rdprefetch_flag = ~rdprefetch_flag; + end + if ((rd_prefetch == rd_addr) && (rd_addr != rdcount_out)) begin + do_out = do_in; + if (DATA_WIDTH != 4) + dop_out = dop_in; + rd_addr = (rd_addr + 1) % addr_limit; + if (rd_addr == 0) + rd_flag = ~rd_flag; + + dbiterr_out_out = dbiterr_out; // reg out in async mode + sbiterr_out_out = sbiterr_out; + + end + if (((rd_addr == rdcount_out) && (empty_ram[3] == 1'b0)) || + ((rden_reg == 1'b1) && (empty_ram[1] == 1'b0)) || + ((rden_reg == 1'b0) && (empty_ram[1] == 1'b0) && (rd_addr == rdcount_out))) begin + + do_buf = mem[rdcount_out]; + dop_buf = memp[rdcount_out]; + + // ECC decode + if (EN_ECC_READ == "TRUE") begin + + // regenerate parity + dopr_ecc[0] = do_buf[0]^do_buf[1]^do_buf[3]^do_buf[4]^do_buf[6]^do_buf[8] + ^do_buf[10]^do_buf[11]^do_buf[13]^do_buf[15]^do_buf[17]^do_buf[19] + ^do_buf[21]^do_buf[23]^do_buf[25]^do_buf[26]^do_buf[28] + ^do_buf[30]^do_buf[32]^do_buf[34]^do_buf[36]^do_buf[38] + ^do_buf[40]^do_buf[42]^do_buf[44]^do_buf[46]^do_buf[48] + ^do_buf[50]^do_buf[52]^do_buf[54]^do_buf[56]^do_buf[57]^do_buf[59] + ^do_buf[61]^do_buf[63]; + + dopr_ecc[1] = do_buf[0]^do_buf[2]^do_buf[3]^do_buf[5]^do_buf[6]^do_buf[9] + ^do_buf[10]^do_buf[12]^do_buf[13]^do_buf[16]^do_buf[17] + ^do_buf[20]^do_buf[21]^do_buf[24]^do_buf[25]^do_buf[27]^do_buf[28] + ^do_buf[31]^do_buf[32]^do_buf[35]^do_buf[36]^do_buf[39] + ^do_buf[40]^do_buf[43]^do_buf[44]^do_buf[47]^do_buf[48] + ^do_buf[51]^do_buf[52]^do_buf[55]^do_buf[56]^do_buf[58]^do_buf[59] + ^do_buf[62]^do_buf[63]; + + dopr_ecc[2] = do_buf[1]^do_buf[2]^do_buf[3]^do_buf[7]^do_buf[8]^do_buf[9] + ^do_buf[10]^do_buf[14]^do_buf[15]^do_buf[16]^do_buf[17] + ^do_buf[22]^do_buf[23]^do_buf[24]^do_buf[25]^do_buf[29] + ^do_buf[30]^do_buf[31]^do_buf[32]^do_buf[37]^do_buf[38]^do_buf[39] + ^do_buf[40]^do_buf[45]^do_buf[46]^do_buf[47]^do_buf[48] + ^do_buf[53]^do_buf[54]^do_buf[55]^do_buf[56] + ^do_buf[60]^do_buf[61]^do_buf[62]^do_buf[63]; + + dopr_ecc[3] = do_buf[4]^do_buf[5]^do_buf[6]^do_buf[7]^do_buf[8]^do_buf[9] + ^do_buf[10]^do_buf[18]^do_buf[19] + ^do_buf[20]^do_buf[21]^do_buf[22]^do_buf[23]^do_buf[24]^do_buf[25] + ^do_buf[33]^do_buf[34]^do_buf[35]^do_buf[36]^do_buf[37]^do_buf[38] + ^do_buf[39]^do_buf[40]^do_buf[49]^do_buf[50] + ^do_buf[51]^do_buf[52]^do_buf[53]^do_buf[54]^do_buf[55]^do_buf[56]; + + dopr_ecc[4] = do_buf[11]^do_buf[12]^do_buf[13]^do_buf[14]^do_buf[15]^do_buf[16] + ^do_buf[17]^do_buf[18]^do_buf[19]^do_buf[20]^do_buf[21]^do_buf[22] + ^do_buf[23]^do_buf[24]^do_buf[25]^do_buf[41]^do_buf[42]^do_buf[43] + ^do_buf[44]^do_buf[45]^do_buf[46]^do_buf[47]^do_buf[48]^do_buf[49] + ^do_buf[50]^do_buf[51]^do_buf[52]^do_buf[53]^do_buf[54]^do_buf[55]^do_buf[56]; + + + dopr_ecc[5] = do_buf[26]^do_buf[27]^do_buf[28]^do_buf[29] + ^do_buf[30]^do_buf[31]^do_buf[32]^do_buf[33]^do_buf[34]^do_buf[35] + ^do_buf[36]^do_buf[37]^do_buf[38]^do_buf[39]^do_buf[40] + ^do_buf[41]^do_buf[42]^do_buf[43]^do_buf[44]^do_buf[45] + ^do_buf[46]^do_buf[47]^do_buf[48]^do_buf[49]^do_buf[50] + ^do_buf[51]^do_buf[52]^do_buf[53]^do_buf[54]^do_buf[55]^do_buf[56]; + + dopr_ecc[6] = do_buf[57]^do_buf[58]^do_buf[59] + ^do_buf[60]^do_buf[61]^do_buf[62]^do_buf[63]; + + dopr_ecc[7] = dop_buf[0]^dop_buf[1]^dop_buf[2]^dop_buf[3]^dop_buf[4]^dop_buf[5] + ^dop_buf[6]^do_buf[0]^do_buf[1]^do_buf[2]^do_buf[3]^do_buf[4] + ^do_buf[5]^do_buf[6]^do_buf[7]^do_buf[8]^do_buf[9]^do_buf[10] + ^do_buf[11]^do_buf[12]^do_buf[13]^do_buf[14]^do_buf[15]^do_buf[16] + ^do_buf[17]^do_buf[18]^do_buf[19]^do_buf[20]^do_buf[21]^do_buf[22] + ^do_buf[23]^do_buf[24]^do_buf[25]^do_buf[26]^do_buf[27]^do_buf[28] + ^do_buf[29]^do_buf[30]^do_buf[31]^do_buf[32]^do_buf[33]^do_buf[34] + ^do_buf[35]^do_buf[36]^do_buf[37]^do_buf[38]^do_buf[39]^do_buf[40] + ^do_buf[41]^do_buf[42]^do_buf[43]^do_buf[44]^do_buf[45]^do_buf[46] + ^do_buf[47]^do_buf[48]^do_buf[49]^do_buf[50]^do_buf[51]^do_buf[52] + ^do_buf[53]^do_buf[54]^do_buf[55]^do_buf[56]^do_buf[57]^do_buf[58] + ^do_buf[59]^do_buf[60]^do_buf[61]^do_buf[62]^do_buf[63]; + + syndrome = dopr_ecc ^ dop_buf; + + if (syndrome !== 0) begin + + if (syndrome[7]) begin // dectect single bit error + + ecc_bit_position = {do_buf[63:57], dop_buf[6], do_buf[56:26], dop_buf[5], do_buf[25:11], dop_buf[4], do_buf[10:4], dop_buf[3], do_buf[3:1], dop_buf[2], do_buf[0], dop_buf[1:0], dop_buf[7]}; + + if (syndrome[6:0] > 71) begin + $display ("DRC Error : Simulation halted due Corrupted DIP. To correct this problem, make sure that reliable data is fed to the DIP. The correct Parity must be generated by a Hamming code encoder or encoder in the Block RAM. The output from the model is unreliable if there are more than 2 bit errors. The model doesn't warn if there is sporadic input of more than 2 bit errors due to the limitation in Hamming code."); + $finish; + end + + ecc_bit_position[syndrome[6:0]] = ~ecc_bit_position[syndrome[6:0]]; // correct single bit error in the output + + di_in_ecc_corrected = {ecc_bit_position[71:65], ecc_bit_position[63:33], ecc_bit_position[31:17], ecc_bit_position[15:9], ecc_bit_position[7:5], ecc_bit_position[3]}; // correct single bit error in the memory + + do_buf = di_in_ecc_corrected; + + dip_in_ecc_corrected = {ecc_bit_position[0], ecc_bit_position[64], ecc_bit_position[32], ecc_bit_position[16], ecc_bit_position[8], ecc_bit_position[4], ecc_bit_position[2:1]}; // correct single bit error in the parity memory + + dop_buf = dip_in_ecc_corrected; + + dbiterr_out = 0; + sbiterr_out = 1; + + end + else if (!syndrome[7]) begin // double bit error + sbiterr_out = 0; + dbiterr_out = 1; + + end + end // if (syndrome !== 0) + else begin + dbiterr_out = 0; + sbiterr_out = 0; + + end // else: !if(syndrome !== 0) + + end // if (EN_ECC_READ == "TRUE") + // end ecc decode + + do_in = do_buf; + dop_in = dop_buf; + + #1; + rdcount_out = (rdcount_out + 1) % addr_limit; + if (rdcount_out == 0) + rdcount_flag = ~rdcount_flag; + end + end // if (fwft == 1'b1) + + + rderr_out = (rden_reg == 1'b1) && (empty_out == 1'b1); + + almostempty_out = almostempty_int[3]; + + if ((((rdcount_out + ae_empty) >= wr_addr) && (rdcount_flag == awr_flag)) || (((rdcount_out + ae_empty) >= (wr_addr + addr_limit)) && (rdcount_flag != awr_flag))) begin + almostempty_int[3] = 1'b1; + almostempty_int[2] = 1'b1; + almostempty_int[1] = 1'b1; + almostempty_int[0] = 1'b1; + end + else if (almostempty_int[2] == 1'b0) begin + + if (rdcount_out <= rdcount_out + ae_empty || rdcount_flag != awr_flag) begin + almostempty_int[3] = almostempty_int[0]; + almostempty_int[0] = 1'b0; + end + end + + if ((((rdcount_out + addr_limit) > (wr_addr + ae_full)) && (rdcount_flag == awr_flag)) || ((rdcount_out > (wr_addr + ae_full)) && (rdcount_flag != awr_flag))) begin + + if (((rden_reg == 1'b1) && (empty_out == 1'b0)) || ((((rd_addr + 1) % addr_limit) == rdcount_out) && (almostfull_int[1] == 1'b1))) begin + almostfull_int[2] = almostfull_int[1]; + almostfull_int[1] = 1'b0; + end + end + else begin + almostfull_int[2] = 1'b1; + almostfull_int[1] = 1'b1; + end + + if (fwft == 1'b0) begin + if ((rdcount_out == rd_addr) && (rdcount_flag == rd_flag)) begin + empty_out = 1'b1; + end + else begin + empty_out = 1'b0; + end + end // if (fwft == 1'b0) + else if (fwft == 1'b1) begin + if ((rd_prefetch == rd_addr) && (rdprefetch_flag == rd_flag)) begin + empty_out = 1'b1; + end + else begin + empty_out = 1'b0; + end + end + + + if ((rdcount_out == wr_addr) && (rdcount_flag == awr_flag)) begin + empty_ram[2] = 1'b1; + empty_ram[1] = 1'b1; + empty_ram[0] = 1'b1; + end + else begin + empty_ram[2] = empty_ram[1]; + empty_ram[1] = empty_ram[0]; + empty_ram[0] = 1'b0; + end + + if ((rdcount_out == wr1_addr) && (rdcount_flag == wr1_flag)) begin + empty_ram[3] = 1'b1; + end + else begin + empty_ram[3] = 1'b0; + end + + wr1_addr = wr_addr; + wr1_flag = awr_flag; + + end // if (sync == 1'b0) + + end // if (rst_in === 1'b0) + + end // always @ (posedge rdclk_in) + + + // Write clock + always @(posedge wrclk_in) begin + + // DRC + if ((injectsbiterr_in === 1) && !(en_ecc_write_int == 1 || en_ecc_read_int == 1)) + $display("DRC Warning : INJECTSBITERR is not supported when neither EN_ECC_WRITE nor EN_ECCREAD = TRUE on FF36_INTERNAL_VLOG instance %m."); + + if ((injectdbiterr_in === 1) && !(en_ecc_write_int == 1 || en_ecc_read_int == 1)) + $display("DRC Warning : INJECTDBITERR is not supported when neither EN_ECC_WRITE nor EN_ECCREAD = TRUE on FF36_INTERNAL_VLOG instance %m."); + + + // sync mode + if (sync == 1'b1) begin + + if (wren_in == 1'b1) begin + + if (full_out == 1'b0) begin + + // ECC encode + if (EN_ECC_WRITE == "TRUE") begin + + dip_ecc[0] = di_in[0]^di_in[1]^di_in[3]^di_in[4]^di_in[6]^di_in[8] + ^di_in[10]^di_in[11]^di_in[13]^di_in[15]^di_in[17]^di_in[19] + ^di_in[21]^di_in[23]^di_in[25]^di_in[26]^di_in[28] + ^di_in[30]^di_in[32]^di_in[34]^di_in[36]^di_in[38] + ^di_in[40]^di_in[42]^di_in[44]^di_in[46]^di_in[48] + ^di_in[50]^di_in[52]^di_in[54]^di_in[56]^di_in[57]^di_in[59] + ^di_in[61]^di_in[63]; + + dip_ecc[1] = di_in[0]^di_in[2]^di_in[3]^di_in[5]^di_in[6]^di_in[9] + ^di_in[10]^di_in[12]^di_in[13]^di_in[16]^di_in[17] + ^di_in[20]^di_in[21]^di_in[24]^di_in[25]^di_in[27]^di_in[28] + ^di_in[31]^di_in[32]^di_in[35]^di_in[36]^di_in[39] + ^di_in[40]^di_in[43]^di_in[44]^di_in[47]^di_in[48] + ^di_in[51]^di_in[52]^di_in[55]^di_in[56]^di_in[58]^di_in[59] + ^di_in[62]^di_in[63]; + + dip_ecc[2] = di_in[1]^di_in[2]^di_in[3]^di_in[7]^di_in[8]^di_in[9] + ^di_in[10]^di_in[14]^di_in[15]^di_in[16]^di_in[17] + ^di_in[22]^di_in[23]^di_in[24]^di_in[25]^di_in[29] + ^di_in[30]^di_in[31]^di_in[32]^di_in[37]^di_in[38]^di_in[39] + ^di_in[40]^di_in[45]^di_in[46]^di_in[47]^di_in[48] + ^di_in[53]^di_in[54]^di_in[55]^di_in[56] + ^di_in[60]^di_in[61]^di_in[62]^di_in[63]; + + dip_ecc[3] = di_in[4]^di_in[5]^di_in[6]^di_in[7]^di_in[8]^di_in[9] + ^di_in[10]^di_in[18]^di_in[19] + ^di_in[20]^di_in[21]^di_in[22]^di_in[23]^di_in[24]^di_in[25] + ^di_in[33]^di_in[34]^di_in[35]^di_in[36]^di_in[37]^di_in[38]^di_in[39] + ^di_in[40]^di_in[49] + ^di_in[50]^di_in[51]^di_in[52]^di_in[53]^di_in[54]^di_in[55]^di_in[56]; + + dip_ecc[4] = di_in[11]^di_in[12]^di_in[13]^di_in[14]^di_in[15]^di_in[16]^di_in[17]^di_in[18]^di_in[19] + ^di_in[20]^di_in[21]^di_in[22]^di_in[23]^di_in[24]^di_in[25] + ^di_in[41]^di_in[42]^di_in[43]^di_in[44]^di_in[45]^di_in[46]^di_in[47]^di_in[48]^di_in[49] + ^di_in[50]^di_in[51]^di_in[52]^di_in[53]^di_in[54]^di_in[55]^di_in[56]; + + + dip_ecc[5] = di_in[26]^di_in[27]^di_in[28]^di_in[29] + ^di_in[30]^di_in[31]^di_in[32]^di_in[33]^di_in[34]^di_in[35]^di_in[36]^di_in[37]^di_in[38]^di_in[39] + ^di_in[40]^di_in[41]^di_in[42]^di_in[43]^di_in[44]^di_in[45]^di_in[46]^di_in[47]^di_in[48]^di_in[49] + ^di_in[50]^di_in[51]^di_in[52]^di_in[53]^di_in[54]^di_in[55]^di_in[56]; + + dip_ecc[6] = di_in[57]^di_in[58]^di_in[59] + ^di_in[60]^di_in[61]^di_in[62]^di_in[63]; + + dip_ecc[7] = dip_ecc[0]^dip_ecc[1]^dip_ecc[2]^dip_ecc[3]^dip_ecc[4]^dip_ecc[5]^dip_ecc[6] + ^di_in[0]^di_in[1]^di_in[2]^di_in[3]^di_in[4]^di_in[5]^di_in[6]^di_in[7]^di_in[8]^di_in[9] + ^di_in[10]^di_in[11]^di_in[12]^di_in[13]^di_in[14]^di_in[15]^di_in[16]^di_in[17]^di_in[18]^di_in[19] + ^di_in[20]^di_in[21]^di_in[22]^di_in[23]^di_in[24]^di_in[25]^di_in[26]^di_in[27]^di_in[28]^di_in[29] + ^di_in[30]^di_in[31]^di_in[32]^di_in[33]^di_in[34]^di_in[35]^di_in[36]^di_in[37]^di_in[38]^di_in[39] + ^di_in[40]^di_in[41]^di_in[42]^di_in[43]^di_in[44]^di_in[45]^di_in[46]^di_in[47]^di_in[48]^di_in[49] + ^di_in[50]^di_in[51]^di_in[52]^di_in[53]^di_in[54]^di_in[55]^di_in[56]^di_in[57]^di_in[58]^di_in[59] + ^di_in[60]^di_in[61]^di_in[62]^di_in[63]; + + eccparity_out = dip_ecc; + + dip_int = dip_ecc; // only 64 bits width + + end // if (EN_ECC_WRITE == "TRUE") + else begin + + dip_int = dip_in; // only 64 bits width + + end // else: !if(EN_ECC_WRITE == "TRUE") + // end ecc encode + + + if (rst_in === 1'b0) begin + + + // injecting error + di_ecc_col = di_in; + + if (injectdbiterr_in === 1) begin + di_ecc_col[30] = ~di_ecc_col[30]; + di_ecc_col[62] = ~di_ecc_col[62]; + end + else if (injectsbiterr_in === 1) begin + di_ecc_col[30] = ~di_ecc_col[30]; + end + + + mem[wr_addr] = di_ecc_col; + memp[wr_addr] = dip_int; + + wr_addr = (wr_addr + 1) % addr_limit; + if (wr_addr == 0) + wr_flag = ~wr_flag; + + end + end + end // if (wren_in == 1'b1) + + + if (rst_in === 1'b0) begin + + wrerr_out = (wren_in == 1'b1) && (full_out == 1'b1); + + + if (rden_in == 1'b1) begin + full_out = 1'b0; + end + else if (rdcount_out == wr_addr && rdcount_flag != wr_flag) + full_out = 1'b1; + + if ((((rdcount_out + ae_empty) < wr_addr) && (rdcount_flag == wr_flag)) || (((rdcount_out + ae_empty) < (wr_addr + addr_limit) && (rdcount_flag != wr_flag)))) begin + + if (rdcount_out <= rdcount_out + ae_empty || rdcount_flag != wr_flag) + almostempty_out = 1'b0; + + end + + if ((((rdcount_out + addr_limit) <= (wr_addr + ae_full)) && (rdcount_flag == wr_flag)) || ((rdcount_out <= (wr_addr + ae_full)) && (rdcount_flag != wr_flag))) begin + almostfull_out = 1'b1; + end + + end // if (rst_in === 1'b0) + + end // if (sync == 1'b1) + + // async mode + else if (sync == 1'b0) begin + + wren_reg = wren_in; + + if (wren_reg == 1'b1 && full_out == 1'b0) begin + + // ECC encode + if (EN_ECC_WRITE == "TRUE") begin + + dip_ecc[0] = di_in[0]^di_in[1]^di_in[3]^di_in[4]^di_in[6]^di_in[8] + ^di_in[10]^di_in[11]^di_in[13]^di_in[15]^di_in[17]^di_in[19] + ^di_in[21]^di_in[23]^di_in[25]^di_in[26]^di_in[28] + ^di_in[30]^di_in[32]^di_in[34]^di_in[36]^di_in[38] + ^di_in[40]^di_in[42]^di_in[44]^di_in[46]^di_in[48] + ^di_in[50]^di_in[52]^di_in[54]^di_in[56]^di_in[57]^di_in[59] + ^di_in[61]^di_in[63]; + + dip_ecc[1] = di_in[0]^di_in[2]^di_in[3]^di_in[5]^di_in[6]^di_in[9] + ^di_in[10]^di_in[12]^di_in[13]^di_in[16]^di_in[17] + ^di_in[20]^di_in[21]^di_in[24]^di_in[25]^di_in[27]^di_in[28] + ^di_in[31]^di_in[32]^di_in[35]^di_in[36]^di_in[39] + ^di_in[40]^di_in[43]^di_in[44]^di_in[47]^di_in[48] + ^di_in[51]^di_in[52]^di_in[55]^di_in[56]^di_in[58]^di_in[59] + ^di_in[62]^di_in[63]; + + dip_ecc[2] = di_in[1]^di_in[2]^di_in[3]^di_in[7]^di_in[8]^di_in[9] + ^di_in[10]^di_in[14]^di_in[15]^di_in[16]^di_in[17] + ^di_in[22]^di_in[23]^di_in[24]^di_in[25]^di_in[29] + ^di_in[30]^di_in[31]^di_in[32]^di_in[37]^di_in[38]^di_in[39] + ^di_in[40]^di_in[45]^di_in[46]^di_in[47]^di_in[48] + ^di_in[53]^di_in[54]^di_in[55]^di_in[56] + ^di_in[60]^di_in[61]^di_in[62]^di_in[63]; + + dip_ecc[3] = di_in[4]^di_in[5]^di_in[6]^di_in[7]^di_in[8]^di_in[9] + ^di_in[10]^di_in[18]^di_in[19] + ^di_in[20]^di_in[21]^di_in[22]^di_in[23]^di_in[24]^di_in[25] + ^di_in[33]^di_in[34]^di_in[35]^di_in[36]^di_in[37]^di_in[38]^di_in[39] + ^di_in[40]^di_in[49] + ^di_in[50]^di_in[51]^di_in[52]^di_in[53]^di_in[54]^di_in[55]^di_in[56]; + + dip_ecc[4] = di_in[11]^di_in[12]^di_in[13]^di_in[14]^di_in[15]^di_in[16]^di_in[17]^di_in[18]^di_in[19] + ^di_in[20]^di_in[21]^di_in[22]^di_in[23]^di_in[24]^di_in[25] + ^di_in[41]^di_in[42]^di_in[43]^di_in[44]^di_in[45]^di_in[46]^di_in[47]^di_in[48]^di_in[49] + ^di_in[50]^di_in[51]^di_in[52]^di_in[53]^di_in[54]^di_in[55]^di_in[56]; + + + dip_ecc[5] = di_in[26]^di_in[27]^di_in[28]^di_in[29] + ^di_in[30]^di_in[31]^di_in[32]^di_in[33]^di_in[34]^di_in[35]^di_in[36]^di_in[37]^di_in[38]^di_in[39] + ^di_in[40]^di_in[41]^di_in[42]^di_in[43]^di_in[44]^di_in[45]^di_in[46]^di_in[47]^di_in[48]^di_in[49] + ^di_in[50]^di_in[51]^di_in[52]^di_in[53]^di_in[54]^di_in[55]^di_in[56]; + + dip_ecc[6] = di_in[57]^di_in[58]^di_in[59] + ^di_in[60]^di_in[61]^di_in[62]^di_in[63]; + + dip_ecc[7] = dip_ecc[0]^dip_ecc[1]^dip_ecc[2]^dip_ecc[3]^dip_ecc[4]^dip_ecc[5]^dip_ecc[6] + ^di_in[0]^di_in[1]^di_in[2]^di_in[3]^di_in[4]^di_in[5]^di_in[6]^di_in[7]^di_in[8]^di_in[9] + ^di_in[10]^di_in[11]^di_in[12]^di_in[13]^di_in[14]^di_in[15]^di_in[16]^di_in[17]^di_in[18]^di_in[19] + ^di_in[20]^di_in[21]^di_in[22]^di_in[23]^di_in[24]^di_in[25]^di_in[26]^di_in[27]^di_in[28]^di_in[29] + ^di_in[30]^di_in[31]^di_in[32]^di_in[33]^di_in[34]^di_in[35]^di_in[36]^di_in[37]^di_in[38]^di_in[39] + ^di_in[40]^di_in[41]^di_in[42]^di_in[43]^di_in[44]^di_in[45]^di_in[46]^di_in[47]^di_in[48]^di_in[49] + ^di_in[50]^di_in[51]^di_in[52]^di_in[53]^di_in[54]^di_in[55]^di_in[56]^di_in[57]^di_in[58]^di_in[59] + ^di_in[60]^di_in[61]^di_in[62]^di_in[63]; + + eccparity_out = dip_ecc; + + dip_int = dip_ecc; // only 64 bits width + + end // if (EN_ECC_WRITE == "TRUE") + else begin + + dip_int = dip_in; // only 64 bits width + + end // else: !if(EN_ECC_WRITE == "TRUE") + // end ecc encode + + if (rst_in === 1'b0) begin + + // injecting error + di_ecc_col = di_in; + + if (injectdbiterr_in === 1) begin + di_ecc_col[30] = ~di_ecc_col[30]; + di_ecc_col[62] = ~di_ecc_col[62]; + end + else if (injectsbiterr_in === 1) begin + di_ecc_col[30] = ~di_ecc_col[30]; + end + + + mem[wr_addr] = di_ecc_col; + memp[wr_addr] = dip_int; + + #1; + wr_addr = (wr_addr + 1) % addr_limit; + + if (wr_addr == 0) + awr_flag = ~awr_flag; + + if (wr_addr == addr_limit - 1) + wr_flag = ~wr_flag; + + + end // if (rst_in === 1'b0) + + end // if (wren_reg == 1'b1 && full_out == 1'b0) + + + if (rst_in === 1'b0) begin + + wrerr_out = (wren_reg == 1'b1) && (full_out == 1'b1); + + almostfull_out = almostfull_int[3]; + + if ((((rdcount_out + addr_limit) <= (wr_addr + ae_full)) && (rdcount_flag == awr_flag)) || ((rdcount_out <= (wr_addr + ae_full)) && (rdcount_flag != awr_flag))) begin + almostfull_int[3] = 1'b1; + almostfull_int[2] = 1'b1; + almostfull_int[1] = 1'b1; + almostfull_int[0] = 1'b1; + end + else if (almostfull_int[2] == 1'b0) begin + + if (wr_addr <= wr_addr + ae_full || rdcount_flag == awr_flag) begin + almostfull_int[3] = almostfull_int[0]; + almostfull_int[0] = 1'b0; + end + end + + if ((((rdcount_out + ae_empty) < wr_addr) && (rdcount_flag == awr_flag)) || (((rdcount_out + ae_empty) < (wr_addr + addr_limit)) && (rdcount_flag != awr_flag))) begin + if (wren_reg == 1'b1) begin + almostempty_int[2] = almostempty_int[1]; + almostempty_int[1] = 1'b0; + end + end + else begin + almostempty_int[2] = 1'b1; + almostempty_int[1] = 1'b1; + end + + if (wren_reg == 1'b1 || full_out == 1'b1) + full_out = full_int[1]; + + if (((rdcount_out == wr_addr) || (rdcount_out - 1 == wr_addr || (rdcount_out + addr_limit - 1 == wr_addr))) && almostfull_out) begin + full_int[1] = 1'b1; + full_int[0] = 1'b1; + end + else begin + full_int[1] = full_int[0]; + full_int[0] = 0; + end + + end // if (rst_in === 1'b0) + + end // if (sync == 1'b0) + + end // always @ (posedge wrclk_in) + + + + // output register + always @(do_out or dop_out or do_outreg or dop_outreg) begin + + if (sync == 1) + + case (DO_REG) + + 0 : begin + do_out_mux = do_out; + dop_out_mux = dop_out; + end + 1 : begin + do_out_mux = do_outreg; + dop_out_mux = dop_outreg; + end + default : begin + $display("Attribute Syntax Error : The attribute DO_REG on FF36_INTERNAL_VLOG instance %m is set to %2d. Legal values for this attribute are 0 or 1.", DO_REG); + $finish; + end + endcase + + else begin + do_out_mux = do_out; + dop_out_mux = dop_out; + end // else: !if(sync == 1) + + end // always @ (do_out or dop_out or do_outreg or dop_outreg) + + + // matching HW behavior to X the unused output bits + assign do_out_out = (DATA_WIDTH == 4) ? {60'bx, do_out_mux[3:0]} + : (DATA_WIDTH == 9) ? {56'bx, do_out_mux[7:0]} + : (DATA_WIDTH == 18) ? {48'bx, do_out_mux[15:0]} + : (DATA_WIDTH == 36) ? {32'bx, do_out_mux[31:0]} + : (DATA_WIDTH == 72) ? do_out_mux + : do_out_mux; + + // matching HW behavior to X the unused output bits + assign dop_out_out = (DATA_WIDTH == 9) ? {7'bx, dop_out_mux[0:0]} + : (DATA_WIDTH == 18) ? {6'bx, dop_out_mux[1:0]} + : (DATA_WIDTH == 36) ? {4'bx, dop_out_mux[3:0]} + : (DATA_WIDTH == 72) ? dop_out_mux + : 8'bx; + + // matching HW behavior to pull up the unused output bits + always @(wr_addr) begin + + if (FIFO_SIZE == 18) + case (DATA_WIDTH) + 4 : wr_addr_out = {1'b1, wr_addr[11:0]}; + 9 : wr_addr_out = {2'b11, wr_addr[10:0]}; + 18 : wr_addr_out = {3'b111, wr_addr[9:0]}; + 36 : wr_addr_out = {4'hf, wr_addr[8:0]}; + default : wr_addr_out = wr_addr; + endcase // case(DATA_WIDTH) + else + case (DATA_WIDTH) + 4 : wr_addr_out = wr_addr; + 9 : wr_addr_out = {1'b1, wr_addr[11:0]}; + 18 : wr_addr_out = {2'b11, wr_addr[10:0]}; + 36 : wr_addr_out = {3'b111, wr_addr[9:0]}; + 72 : wr_addr_out = {4'hf, wr_addr[8:0]}; + default : wr_addr_out = wr_addr; + endcase // case(DATA_WIDTH) + + end // always @ (wr_addr) + + + // matching HW behavior to pull up the unused output bits + always @(rdcount_out) begin + + if (FIFO_SIZE == 18) + case (DATA_WIDTH) + 4 : rdcount_out_out = {1'b1, rdcount_out[11:0]}; + 9 : rdcount_out_out = {2'b11, rdcount_out[10:0]}; + 18 : rdcount_out_out = {3'b111, rdcount_out[9:0]}; + 36 : rdcount_out_out = {4'hf, rdcount_out[8:0]}; + default : rdcount_out_out = rdcount_out; + endcase // case(DATA_WIDTH) + else + case (DATA_WIDTH) + 4 : rdcount_out_out = rdcount_out; + 9 : rdcount_out_out = {1'b1, rdcount_out[11:0]}; + 18 : rdcount_out_out = {2'b11, rdcount_out[10:0]}; + 36 : rdcount_out_out = {3'b111, rdcount_out[9:0]}; + 72 : rdcount_out_out = {4'hf, rdcount_out[8:0]}; + default : rdcount_out_out = rdcount_out; + endcase // case(DATA_WIDTH) + + end // always @ (rdcount_out) + + +endmodule + +// end of FF36_INTERNAL_VLOG - Note: Not an user primitive diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/FIFO36_72.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/FIFO36_72.v new file mode 100644 index 0000000..6fbe3df --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/FIFO36_72.v @@ -0,0 +1,189 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/rainier/FIFO36_72.v,v 1.14 2007/06/15 20:58:41 wloo Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2005 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / 36K-Bit FIFO +// /___/ /\ Filename : FIFO36_72.v +// \ \ / \ Timestamp : Tues July 26 16:44:06 PST 2005 +// \___\/\___\ +// +// Revision: +// 07/26/05 - Initial version. +// 06/14/07 - Implemented high performace version of the model. +// End Revision + +`timescale 1 ps/1 ps + +module FIFO36_72 (ALMOSTEMPTY, ALMOSTFULL, DBITERR, DO, DOP, ECCPARITY, EMPTY, FULL, RDCOUNT, RDERR, SBITERR, WRCOUNT, WRERR, + DI, DIP, RDCLK, RDEN, RST, WRCLK, WREN); + + parameter ALMOST_EMPTY_OFFSET = 9'h080; + parameter ALMOST_FULL_OFFSET = 9'h080; + parameter integer DO_REG = 1; + parameter EN_ECC_WRITE = "FALSE"; + parameter EN_ECC_READ = "FALSE"; + parameter EN_SYN = "FALSE"; + parameter FIRST_WORD_FALL_THROUGH = "FALSE"; + parameter SIM_MODE = "SAFE"; + + output ALMOSTEMPTY; + output ALMOSTFULL; + output DBITERR; + output [63:0] DO; + output [7:0] DOP; + output [7:0] ECCPARITY; + output EMPTY; + output FULL; + output [8:0] RDCOUNT; + output RDERR; + output SBITERR; + output [8:0] WRCOUNT; + output WRERR; + + input [63:0] DI; + input [7:0] DIP; + input RDCLK; + input RDEN; + input RST; + input WRCLK; + input WREN; + + tri0 GSR = glbl.GSR; + + wire [3:0] dangle_out4; + wire [3:0] dangle_out4_1; + + AFIFO36_INTERNAL INT_FIFO (.ALMOSTEMPTY(ALMOSTEMPTY), .ALMOSTFULL(ALMOSTFULL), .DBITERR(DBITERR), .DO(DO), .DOP(DOP), .ECCPARITY(ECCPARITY), .EMPTY(EMPTY), .FULL(FULL), .RDCOUNT({dangle_out4, RDCOUNT}), .RDERR(RDERR), .SBITERR(SBITERR), .WRCOUNT({dangle_out4_1, WRCOUNT}), .WRERR(WRERR), .DI(DI), .DIP(DIP), .RDCLK(RDCLK), .RDEN(RDEN), .RDRCLK(RDCLK), .RST(RST), .WRCLK(WRCLK), .WREN(WREN)); + + defparam INT_FIFO.ALMOST_EMPTY_OFFSET = ALMOST_EMPTY_OFFSET; + defparam INT_FIFO.ALMOST_FULL_OFFSET = ALMOST_FULL_OFFSET; + defparam INT_FIFO.DATA_WIDTH = 72; + defparam INT_FIFO.DO_REG = DO_REG; + defparam INT_FIFO.EN_ECC_WRITE = EN_ECC_WRITE; + defparam INT_FIFO.EN_ECC_READ = EN_ECC_READ; + defparam INT_FIFO.EN_SYN = EN_SYN; + defparam INT_FIFO.FIRST_WORD_FALL_THROUGH = FIRST_WORD_FALL_THROUGH; + defparam INT_FIFO.SIM_MODE = SIM_MODE; + + specify + + (RDCLK => DO[0]) = (100, 100); + (RDCLK => DO[1]) = (100, 100); + (RDCLK => DO[2]) = (100, 100); + (RDCLK => DO[3]) = (100, 100); + (RDCLK => DO[4]) = (100, 100); + (RDCLK => DO[5]) = (100, 100); + (RDCLK => DO[6]) = (100, 100); + (RDCLK => DO[7]) = (100, 100); + (RDCLK => DO[8]) = (100, 100); + (RDCLK => DO[9]) = (100, 100); + (RDCLK => DO[10]) = (100, 100); + (RDCLK => DO[11]) = (100, 100); + (RDCLK => DO[12]) = (100, 100); + (RDCLK => DO[13]) = (100, 100); + (RDCLK => DO[14]) = (100, 100); + (RDCLK => DO[15]) = (100, 100); + (RDCLK => DO[16]) = (100, 100); + (RDCLK => DO[17]) = (100, 100); + (RDCLK => DO[18]) = (100, 100); + (RDCLK => DO[19]) = (100, 100); + (RDCLK => DO[20]) = (100, 100); + (RDCLK => DO[21]) = (100, 100); + (RDCLK => DO[22]) = (100, 100); + (RDCLK => DO[23]) = (100, 100); + (RDCLK => DO[24]) = (100, 100); + (RDCLK => DO[25]) = (100, 100); + (RDCLK => DO[26]) = (100, 100); + (RDCLK => DO[27]) = (100, 100); + (RDCLK => DO[28]) = (100, 100); + (RDCLK => DO[29]) = (100, 100); + (RDCLK => DO[30]) = (100, 100); + (RDCLK => DO[31]) = (100, 100); + (RDCLK => DO[32]) = (100, 100); + (RDCLK => DO[33]) = (100, 100); + (RDCLK => DO[34]) = (100, 100); + (RDCLK => DO[35]) = (100, 100); + (RDCLK => DO[36]) = (100, 100); + (RDCLK => DO[37]) = (100, 100); + (RDCLK => DO[38]) = (100, 100); + (RDCLK => DO[39]) = (100, 100); + (RDCLK => DO[40]) = (100, 100); + (RDCLK => DO[41]) = (100, 100); + (RDCLK => DO[42]) = (100, 100); + (RDCLK => DO[43]) = (100, 100); + (RDCLK => DO[44]) = (100, 100); + (RDCLK => DO[45]) = (100, 100); + (RDCLK => DO[46]) = (100, 100); + (RDCLK => DO[47]) = (100, 100); + (RDCLK => DO[48]) = (100, 100); + (RDCLK => DO[49]) = (100, 100); + (RDCLK => DO[50]) = (100, 100); + (RDCLK => DO[51]) = (100, 100); + (RDCLK => DO[52]) = (100, 100); + (RDCLK => DO[53]) = (100, 100); + (RDCLK => DO[54]) = (100, 100); + (RDCLK => DO[55]) = (100, 100); + (RDCLK => DO[56]) = (100, 100); + (RDCLK => DO[57]) = (100, 100); + (RDCLK => DO[58]) = (100, 100); + (RDCLK => DO[59]) = (100, 100); + (RDCLK => DO[60]) = (100, 100); + (RDCLK => DO[61]) = (100, 100); + (RDCLK => DO[62]) = (100, 100); + (RDCLK => DO[63]) = (100, 100); + (RDCLK => DOP[0]) = (100, 100); + (RDCLK => DOP[1]) = (100, 100); + (RDCLK => DOP[2]) = (100, 100); + (RDCLK => DOP[3]) = (100, 100); + (RDCLK => DOP[4]) = (100, 100); + (RDCLK => DOP[5]) = (100, 100); + (RDCLK => DOP[6]) = (100, 100); + (RDCLK => DOP[7]) = (100, 100); + (RDCLK => DBITERR) = (100, 100); + (RDCLK => SBITERR) = (100, 100); + (WRCLK => ECCPARITY[0]) = (100, 100); + (WRCLK => ECCPARITY[1]) = (100, 100); + (WRCLK => ECCPARITY[2]) = (100, 100); + (WRCLK => ECCPARITY[3]) = (100, 100); + (WRCLK => ECCPARITY[4]) = (100, 100); + (WRCLK => ECCPARITY[5]) = (100, 100); + (WRCLK => ECCPARITY[6]) = (100, 100); + (WRCLK => ECCPARITY[7]) = (100, 100); + + (RDCLK => ALMOSTEMPTY) = (100, 100); + (RDCLK => EMPTY) = (100, 100); + (RDCLK => RDCOUNT[0]) = (100, 100); + (RDCLK => RDCOUNT[1]) = (100, 100); + (RDCLK => RDCOUNT[2]) = (100, 100); + (RDCLK => RDCOUNT[3]) = (100, 100); + (RDCLK => RDCOUNT[4]) = (100, 100); + (RDCLK => RDCOUNT[5]) = (100, 100); + (RDCLK => RDCOUNT[6]) = (100, 100); + (RDCLK => RDCOUNT[7]) = (100, 100); + (RDCLK => RDCOUNT[8]) = (100, 100); + (RDCLK => RDERR) = (100, 100); + + (WRCLK => ALMOSTFULL) = (100, 100); + (WRCLK => FULL) = (100, 100); + (WRCLK => WRCOUNT[0]) = (100, 100); + (WRCLK => WRCOUNT[1]) = (100, 100); + (WRCLK => WRCOUNT[2]) = (100, 100); + (WRCLK => WRCOUNT[3]) = (100, 100); + (WRCLK => WRCOUNT[4]) = (100, 100); + (WRCLK => WRCOUNT[5]) = (100, 100); + (WRCLK => WRCOUNT[6]) = (100, 100); + (WRCLK => WRCOUNT[7]) = (100, 100); + (WRCLK => WRCOUNT[8]) = (100, 100); + (WRCLK => WRERR) = (100, 100); + + specparam PATHPULSE$ = 0; + + endspecify + +endmodule // FIFO36_72 diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/FIFO36_72_EXP.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/FIFO36_72_EXP.v new file mode 100644 index 0000000..2f78e3b --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/FIFO36_72_EXP.v @@ -0,0 +1,498 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/rainier/FIFO36_72_EXP.v,v 1.13 2007/06/15 20:58:41 wloo Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2005 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / 36K-Bit FIFO +// /___/ /\ Filename : FIFO36_72_EXP.v +// \ \ / \ Timestamp : Tues July 26 16:44:06 PST 2005 +// \___\/\___\ +// +// Revision: +// 07/26/05 - Initial version. +// 06/14/07 - Implemented high performace version of the model. +// End Revision + +`timescale 1 ps/1 ps + +module FIFO36_72_EXP (ALMOSTEMPTY, ALMOSTFULL, DBITERR, DO, DOP, ECCPARITY, EMPTY, FULL, RDCOUNT, RDERR, SBITERR, WRCOUNT, WRERR, + DI, DIP, RDCLKL, RDCLKU, RDEN, RDRCLKL, RDRCLKU, RST, WRCLKL, WRCLKU, WREN); + + parameter ALMOST_EMPTY_OFFSET = 9'h080; + parameter ALMOST_FULL_OFFSET = 9'h080; + parameter integer DO_REG = 1; + parameter EN_ECC_WRITE = "FALSE"; + parameter EN_ECC_READ = "FALSE"; + parameter EN_SYN = "FALSE"; + parameter FIRST_WORD_FALL_THROUGH = "FALSE"; + parameter SIM_MODE = "SAFE"; + + output ALMOSTEMPTY; + output ALMOSTFULL; + output DBITERR; + output [63:0] DO; + output [7:0] DOP; + output [7:0] ECCPARITY; + output EMPTY; + output FULL; + output [12:0] RDCOUNT; + output RDERR; + output SBITERR; + output [12:0] WRCOUNT; + output WRERR; + + input [63:0] DI; + input [7:0] DIP; + input RDCLKL; + input RDCLKU; + input RDEN; + input RDRCLKL; + input RDRCLKU; + input RST; + input WRCLKL; + input WRCLKU; + input WREN; + + tri0 GSR = glbl.GSR; + + AFIFO36_INTERNAL INT_FIFO (.ALMOSTEMPTY(ALMOSTEMPTY), .ALMOSTFULL(ALMOSTFULL), .DBITERR(DBITERR), .DO(DO), .DOP(DOP), .ECCPARITY(ECCPARITY), .EMPTY(EMPTY), .FULL(FULL), .RDCOUNT(RDCOUNT), .RDERR(RDERR), .SBITERR(SBITERR), .WRCOUNT(WRCOUNT), .WRERR(WRERR), .DI(DI), .DIP(DIP), .RDCLK(RDCLKL), .RDEN(RDEN), .RDRCLK(RDRCLKL), .RST(RST), .WRCLK(WRCLKL), .WREN(WREN)); + + defparam INT_FIFO.ALMOST_EMPTY_OFFSET = ALMOST_EMPTY_OFFSET; + defparam INT_FIFO.ALMOST_FULL_OFFSET = ALMOST_FULL_OFFSET; + defparam INT_FIFO.DATA_WIDTH = 72; + defparam INT_FIFO.DO_REG = DO_REG; + defparam INT_FIFO.EN_ECC_WRITE = EN_ECC_WRITE; + defparam INT_FIFO.EN_ECC_READ = EN_ECC_READ; + defparam INT_FIFO.EN_SYN = EN_SYN; + defparam INT_FIFO.FIRST_WORD_FALL_THROUGH = FIRST_WORD_FALL_THROUGH; + defparam INT_FIFO.SIM_MODE = SIM_MODE; + + specify + + (RDCLKL => DO[0]) = (100, 100); + (RDCLKL => DO[1]) = (100, 100); + (RDCLKL => DO[2]) = (100, 100); + (RDCLKL => DO[3]) = (100, 100); + (RDCLKL => DO[4]) = (100, 100); + (RDCLKL => DO[5]) = (100, 100); + (RDCLKL => DO[6]) = (100, 100); + (RDCLKL => DO[7]) = (100, 100); + (RDCLKL => DO[8]) = (100, 100); + (RDCLKL => DO[9]) = (100, 100); + (RDCLKL => DO[10]) = (100, 100); + (RDCLKL => DO[11]) = (100, 100); + (RDCLKL => DO[12]) = (100, 100); + (RDCLKL => DO[13]) = (100, 100); + (RDCLKL => DO[14]) = (100, 100); + (RDCLKL => DO[15]) = (100, 100); + (RDCLKL => DO[16]) = (100, 100); + (RDCLKL => DO[17]) = (100, 100); + (RDCLKL => DO[18]) = (100, 100); + (RDCLKL => DO[19]) = (100, 100); + (RDCLKL => DO[20]) = (100, 100); + (RDCLKL => DO[21]) = (100, 100); + (RDCLKL => DO[22]) = (100, 100); + (RDCLKL => DO[23]) = (100, 100); + (RDCLKL => DO[24]) = (100, 100); + (RDCLKL => DO[25]) = (100, 100); + (RDCLKL => DO[26]) = (100, 100); + (RDCLKL => DO[27]) = (100, 100); + (RDCLKL => DO[28]) = (100, 100); + (RDCLKL => DO[29]) = (100, 100); + (RDCLKL => DO[30]) = (100, 100); + (RDCLKL => DO[31]) = (100, 100); + (RDCLKL => DO[32]) = (100, 100); + (RDCLKL => DO[33]) = (100, 100); + (RDCLKL => DO[34]) = (100, 100); + (RDCLKL => DO[35]) = (100, 100); + (RDCLKL => DO[36]) = (100, 100); + (RDCLKL => DO[37]) = (100, 100); + (RDCLKL => DO[38]) = (100, 100); + (RDCLKL => DO[39]) = (100, 100); + (RDCLKL => DO[40]) = (100, 100); + (RDCLKL => DO[41]) = (100, 100); + (RDCLKL => DO[42]) = (100, 100); + (RDCLKL => DO[43]) = (100, 100); + (RDCLKL => DO[44]) = (100, 100); + (RDCLKL => DO[45]) = (100, 100); + (RDCLKL => DO[46]) = (100, 100); + (RDCLKL => DO[47]) = (100, 100); + (RDCLKL => DO[48]) = (100, 100); + (RDCLKL => DO[49]) = (100, 100); + (RDCLKL => DO[50]) = (100, 100); + (RDCLKL => DO[51]) = (100, 100); + (RDCLKL => DO[52]) = (100, 100); + (RDCLKL => DO[53]) = (100, 100); + (RDCLKL => DO[54]) = (100, 100); + (RDCLKL => DO[55]) = (100, 100); + (RDCLKL => DO[56]) = (100, 100); + (RDCLKL => DO[57]) = (100, 100); + (RDCLKL => DO[58]) = (100, 100); + (RDCLKL => DO[59]) = (100, 100); + (RDCLKL => DO[60]) = (100, 100); + (RDCLKL => DO[61]) = (100, 100); + (RDCLKL => DO[62]) = (100, 100); + (RDCLKL => DO[63]) = (100, 100); + (RDCLKL => DOP[0]) = (100, 100); + (RDCLKL => DOP[1]) = (100, 100); + (RDCLKL => DOP[2]) = (100, 100); + (RDCLKL => DOP[3]) = (100, 100); + (RDCLKL => DOP[4]) = (100, 100); + (RDCLKL => DOP[5]) = (100, 100); + (RDCLKL => DOP[6]) = (100, 100); + (RDCLKL => DOP[7]) = (100, 100); + (RDCLKL => DBITERR) = (100, 100); + (RDCLKL => SBITERR) = (100, 100); + (RDRCLKL => DO[0]) = (100, 100); + (RDRCLKL => DO[1]) = (100, 100); + (RDRCLKL => DO[2]) = (100, 100); + (RDRCLKL => DO[3]) = (100, 100); + (RDRCLKL => DO[4]) = (100, 100); + (RDRCLKL => DO[5]) = (100, 100); + (RDRCLKL => DO[6]) = (100, 100); + (RDRCLKL => DO[7]) = (100, 100); + (RDRCLKL => DO[8]) = (100, 100); + (RDRCLKL => DO[9]) = (100, 100); + (RDRCLKL => DO[10]) = (100, 100); + (RDRCLKL => DO[11]) = (100, 100); + (RDRCLKL => DO[12]) = (100, 100); + (RDRCLKL => DO[13]) = (100, 100); + (RDRCLKL => DO[14]) = (100, 100); + (RDRCLKL => DO[15]) = (100, 100); + (RDRCLKL => DO[16]) = (100, 100); + (RDRCLKL => DO[17]) = (100, 100); + (RDRCLKL => DO[18]) = (100, 100); + (RDRCLKL => DO[19]) = (100, 100); + (RDRCLKL => DO[20]) = (100, 100); + (RDRCLKL => DO[21]) = (100, 100); + (RDRCLKL => DO[22]) = (100, 100); + (RDRCLKL => DO[23]) = (100, 100); + (RDRCLKL => DO[24]) = (100, 100); + (RDRCLKL => DO[25]) = (100, 100); + (RDRCLKL => DO[26]) = (100, 100); + (RDRCLKL => DO[27]) = (100, 100); + (RDRCLKL => DO[28]) = (100, 100); + (RDRCLKL => DO[29]) = (100, 100); + (RDRCLKL => DO[30]) = (100, 100); + (RDRCLKL => DO[31]) = (100, 100); + (RDRCLKL => DO[32]) = (100, 100); + (RDRCLKL => DO[33]) = (100, 100); + (RDRCLKL => DO[34]) = (100, 100); + (RDRCLKL => DO[35]) = (100, 100); + (RDRCLKL => DO[36]) = (100, 100); + (RDRCLKL => DO[37]) = (100, 100); + (RDRCLKL => DO[38]) = (100, 100); + (RDRCLKL => DO[39]) = (100, 100); + (RDRCLKL => DO[40]) = (100, 100); + (RDRCLKL => DO[41]) = (100, 100); + (RDRCLKL => DO[42]) = (100, 100); + (RDRCLKL => DO[43]) = (100, 100); + (RDRCLKL => DO[44]) = (100, 100); + (RDRCLKL => DO[45]) = (100, 100); + (RDRCLKL => DO[46]) = (100, 100); + (RDRCLKL => DO[47]) = (100, 100); + (RDRCLKL => DO[48]) = (100, 100); + (RDRCLKL => DO[49]) = (100, 100); + (RDRCLKL => DO[50]) = (100, 100); + (RDRCLKL => DO[51]) = (100, 100); + (RDRCLKL => DO[52]) = (100, 100); + (RDRCLKL => DO[53]) = (100, 100); + (RDRCLKL => DO[54]) = (100, 100); + (RDRCLKL => DO[55]) = (100, 100); + (RDRCLKL => DO[56]) = (100, 100); + (RDRCLKL => DO[57]) = (100, 100); + (RDRCLKL => DO[58]) = (100, 100); + (RDRCLKL => DO[59]) = (100, 100); + (RDRCLKL => DO[60]) = (100, 100); + (RDRCLKL => DO[61]) = (100, 100); + (RDRCLKL => DO[62]) = (100, 100); + (RDRCLKL => DO[63]) = (100, 100); + (RDRCLKL => DOP[0]) = (100, 100); + (RDRCLKL => DOP[1]) = (100, 100); + (RDRCLKL => DOP[2]) = (100, 100); + (RDRCLKL => DOP[3]) = (100, 100); + (RDRCLKL => DOP[4]) = (100, 100); + (RDRCLKL => DOP[5]) = (100, 100); + (RDRCLKL => DOP[6]) = (100, 100); + (RDRCLKL => DOP[7]) = (100, 100); + (RDRCLKL => DBITERR) = (100, 100); + (RDRCLKL => SBITERR) = (100, 100); + (WRCLKL => ECCPARITY[0]) = (100, 100); + (WRCLKL => ECCPARITY[1]) = (100, 100); + (WRCLKL => ECCPARITY[2]) = (100, 100); + (WRCLKL => ECCPARITY[3]) = (100, 100); + (WRCLKL => ECCPARITY[4]) = (100, 100); + (WRCLKL => ECCPARITY[5]) = (100, 100); + (WRCLKL => ECCPARITY[6]) = (100, 100); + (WRCLKL => ECCPARITY[7]) = (100, 100); + + (RDCLKL => ALMOSTEMPTY) = (100, 100); + (RDCLKL => EMPTY) = (100, 100); + (RDCLKL => RDCOUNT[0]) = (100, 100); + (RDCLKL => RDCOUNT[10]) = (100, 100); + (RDCLKL => RDCOUNT[11]) = (100, 100); + (RDCLKL => RDCOUNT[12]) = (100, 100); + (RDCLKL => RDCOUNT[1]) = (100, 100); + (RDCLKL => RDCOUNT[2]) = (100, 100); + (RDCLKL => RDCOUNT[3]) = (100, 100); + (RDCLKL => RDCOUNT[4]) = (100, 100); + (RDCLKL => RDCOUNT[5]) = (100, 100); + (RDCLKL => RDCOUNT[6]) = (100, 100); + (RDCLKL => RDCOUNT[7]) = (100, 100); + (RDCLKL => RDCOUNT[8]) = (100, 100); + (RDCLKL => RDCOUNT[9]) = (100, 100); + (RDCLKL => RDERR) = (100, 100); + + (RDRCLKL => ALMOSTEMPTY) = (100, 100); + (RDRCLKL => EMPTY) = (100, 100); + (RDRCLKL => RDCOUNT[0]) = (100, 100); + (RDRCLKL => RDCOUNT[10]) = (100, 100); + (RDRCLKL => RDCOUNT[11]) = (100, 100); + (RDRCLKL => RDCOUNT[12]) = (100, 100); + (RDRCLKL => RDCOUNT[1]) = (100, 100); + (RDRCLKL => RDCOUNT[2]) = (100, 100); + (RDRCLKL => RDCOUNT[3]) = (100, 100); + (RDRCLKL => RDCOUNT[4]) = (100, 100); + (RDRCLKL => RDCOUNT[5]) = (100, 100); + (RDRCLKL => RDCOUNT[6]) = (100, 100); + (RDRCLKL => RDCOUNT[7]) = (100, 100); + (RDRCLKL => RDCOUNT[8]) = (100, 100); + (RDRCLKL => RDCOUNT[9]) = (100, 100); + (RDRCLKL => RDERR) = (100, 100); + + (WRCLKL => ALMOSTFULL) = (100, 100); + (WRCLKL => FULL) = (100, 100); + (WRCLKL => WRCOUNT[0]) = (100, 100); + (WRCLKL => WRCOUNT[10]) = (100, 100); + (WRCLKL => WRCOUNT[11]) = (100, 100); + (WRCLKL => WRCOUNT[12]) = (100, 100); + (WRCLKL => WRCOUNT[1]) = (100, 100); + (WRCLKL => WRCOUNT[2]) = (100, 100); + (WRCLKL => WRCOUNT[3]) = (100, 100); + (WRCLKL => WRCOUNT[4]) = (100, 100); + (WRCLKL => WRCOUNT[5]) = (100, 100); + (WRCLKL => WRCOUNT[6]) = (100, 100); + (WRCLKL => WRCOUNT[7]) = (100, 100); + (WRCLKL => WRCOUNT[8]) = (100, 100); + (WRCLKL => WRCOUNT[9]) = (100, 100); + (WRCLKL => WRERR) = (100, 100); + + (RDCLKU => DO[0]) = (100, 100); + (RDCLKU => DO[1]) = (100, 100); + (RDCLKU => DO[2]) = (100, 100); + (RDCLKU => DO[3]) = (100, 100); + (RDCLKU => DO[4]) = (100, 100); + (RDCLKU => DO[5]) = (100, 100); + (RDCLKU => DO[6]) = (100, 100); + (RDCLKU => DO[7]) = (100, 100); + (RDCLKU => DO[8]) = (100, 100); + (RDCLKU => DO[9]) = (100, 100); + (RDCLKU => DO[10]) = (100, 100); + (RDCLKU => DO[11]) = (100, 100); + (RDCLKU => DO[12]) = (100, 100); + (RDCLKU => DO[13]) = (100, 100); + (RDCLKU => DO[14]) = (100, 100); + (RDCLKU => DO[15]) = (100, 100); + (RDCLKU => DO[16]) = (100, 100); + (RDCLKU => DO[17]) = (100, 100); + (RDCLKU => DO[18]) = (100, 100); + (RDCLKU => DO[19]) = (100, 100); + (RDCLKU => DO[20]) = (100, 100); + (RDCLKU => DO[21]) = (100, 100); + (RDCLKU => DO[22]) = (100, 100); + (RDCLKU => DO[23]) = (100, 100); + (RDCLKU => DO[24]) = (100, 100); + (RDCLKU => DO[25]) = (100, 100); + (RDCLKU => DO[26]) = (100, 100); + (RDCLKU => DO[27]) = (100, 100); + (RDCLKU => DO[28]) = (100, 100); + (RDCLKU => DO[29]) = (100, 100); + (RDCLKU => DO[30]) = (100, 100); + (RDCLKU => DO[31]) = (100, 100); + (RDCLKU => DO[32]) = (100, 100); + (RDCLKU => DO[33]) = (100, 100); + (RDCLKU => DO[34]) = (100, 100); + (RDCLKU => DO[35]) = (100, 100); + (RDCLKU => DO[36]) = (100, 100); + (RDCLKU => DO[37]) = (100, 100); + (RDCLKU => DO[38]) = (100, 100); + (RDCLKU => DO[39]) = (100, 100); + (RDCLKU => DO[40]) = (100, 100); + (RDCLKU => DO[41]) = (100, 100); + (RDCLKU => DO[42]) = (100, 100); + (RDCLKU => DO[43]) = (100, 100); + (RDCLKU => DO[44]) = (100, 100); + (RDCLKU => DO[45]) = (100, 100); + (RDCLKU => DO[46]) = (100, 100); + (RDCLKU => DO[47]) = (100, 100); + (RDCLKU => DO[48]) = (100, 100); + (RDCLKU => DO[49]) = (100, 100); + (RDCLKU => DO[50]) = (100, 100); + (RDCLKU => DO[51]) = (100, 100); + (RDCLKU => DO[52]) = (100, 100); + (RDCLKU => DO[53]) = (100, 100); + (RDCLKU => DO[54]) = (100, 100); + (RDCLKU => DO[55]) = (100, 100); + (RDCLKU => DO[56]) = (100, 100); + (RDCLKU => DO[57]) = (100, 100); + (RDCLKU => DO[58]) = (100, 100); + (RDCLKU => DO[59]) = (100, 100); + (RDCLKU => DO[60]) = (100, 100); + (RDCLKU => DO[61]) = (100, 100); + (RDCLKU => DO[62]) = (100, 100); + (RDCLKU => DO[63]) = (100, 100); + (RDCLKU => DOP[0]) = (100, 100); + (RDCLKU => DOP[1]) = (100, 100); + (RDCLKU => DOP[2]) = (100, 100); + (RDCLKU => DOP[3]) = (100, 100); + (RDCLKU => DOP[4]) = (100, 100); + (RDCLKU => DOP[5]) = (100, 100); + (RDCLKU => DOP[6]) = (100, 100); + (RDCLKU => DOP[7]) = (100, 100); + (RDCLKU => DBITERR) = (100, 100); + (RDCLKU => SBITERR) = (100, 100); + (RDRCLKU => DO[0]) = (100, 100); + (RDRCLKU => DO[1]) = (100, 100); + (RDRCLKU => DO[2]) = (100, 100); + (RDRCLKU => DO[3]) = (100, 100); + (RDRCLKU => DO[4]) = (100, 100); + (RDRCLKU => DO[5]) = (100, 100); + (RDRCLKU => DO[6]) = (100, 100); + (RDRCLKU => DO[7]) = (100, 100); + (RDRCLKU => DO[8]) = (100, 100); + (RDRCLKU => DO[9]) = (100, 100); + (RDRCLKU => DO[10]) = (100, 100); + (RDRCLKU => DO[11]) = (100, 100); + (RDRCLKU => DO[12]) = (100, 100); + (RDRCLKU => DO[13]) = (100, 100); + (RDRCLKU => DO[14]) = (100, 100); + (RDRCLKU => DO[15]) = (100, 100); + (RDRCLKU => DO[16]) = (100, 100); + (RDRCLKU => DO[17]) = (100, 100); + (RDRCLKU => DO[18]) = (100, 100); + (RDRCLKU => DO[19]) = (100, 100); + (RDRCLKU => DO[20]) = (100, 100); + (RDRCLKU => DO[21]) = (100, 100); + (RDRCLKU => DO[22]) = (100, 100); + (RDRCLKU => DO[23]) = (100, 100); + (RDRCLKU => DO[24]) = (100, 100); + (RDRCLKU => DO[25]) = (100, 100); + (RDRCLKU => DO[26]) = (100, 100); + (RDRCLKU => DO[27]) = (100, 100); + (RDRCLKU => DO[28]) = (100, 100); + (RDRCLKU => DO[29]) = (100, 100); + (RDRCLKU => DO[30]) = (100, 100); + (RDRCLKU => DO[31]) = (100, 100); + (RDRCLKU => DO[32]) = (100, 100); + (RDRCLKU => DO[33]) = (100, 100); + (RDRCLKU => DO[34]) = (100, 100); + (RDRCLKU => DO[35]) = (100, 100); + (RDRCLKU => DO[36]) = (100, 100); + (RDRCLKU => DO[37]) = (100, 100); + (RDRCLKU => DO[38]) = (100, 100); + (RDRCLKU => DO[39]) = (100, 100); + (RDRCLKU => DO[40]) = (100, 100); + (RDRCLKU => DO[41]) = (100, 100); + (RDRCLKU => DO[42]) = (100, 100); + (RDRCLKU => DO[43]) = (100, 100); + (RDRCLKU => DO[44]) = (100, 100); + (RDRCLKU => DO[45]) = (100, 100); + (RDRCLKU => DO[46]) = (100, 100); + (RDRCLKU => DO[47]) = (100, 100); + (RDRCLKU => DO[48]) = (100, 100); + (RDRCLKU => DO[49]) = (100, 100); + (RDRCLKU => DO[50]) = (100, 100); + (RDRCLKU => DO[51]) = (100, 100); + (RDRCLKU => DO[52]) = (100, 100); + (RDRCLKU => DO[53]) = (100, 100); + (RDRCLKU => DO[54]) = (100, 100); + (RDRCLKU => DO[55]) = (100, 100); + (RDRCLKU => DO[56]) = (100, 100); + (RDRCLKU => DO[57]) = (100, 100); + (RDRCLKU => DO[58]) = (100, 100); + (RDRCLKU => DO[59]) = (100, 100); + (RDRCLKU => DO[60]) = (100, 100); + (RDRCLKU => DO[61]) = (100, 100); + (RDRCLKU => DO[62]) = (100, 100); + (RDRCLKU => DO[63]) = (100, 100); + (RDRCLKU => DOP[0]) = (100, 100); + (RDRCLKU => DOP[1]) = (100, 100); + (RDRCLKU => DOP[2]) = (100, 100); + (RDRCLKU => DOP[3]) = (100, 100); + (RDRCLKU => DOP[4]) = (100, 100); + (RDRCLKU => DOP[5]) = (100, 100); + (RDRCLKU => DOP[6]) = (100, 100); + (RDRCLKU => DOP[7]) = (100, 100); + (RDRCLKU => DBITERR) = (100, 100); + (RDRCLKU => SBITERR) = (100, 100); + (WRCLKU => ECCPARITY[0]) = (100, 100); + (WRCLKU => ECCPARITY[1]) = (100, 100); + (WRCLKU => ECCPARITY[2]) = (100, 100); + (WRCLKU => ECCPARITY[3]) = (100, 100); + (WRCLKU => ECCPARITY[4]) = (100, 100); + (WRCLKU => ECCPARITY[5]) = (100, 100); + (WRCLKU => ECCPARITY[6]) = (100, 100); + (WRCLKU => ECCPARITY[7]) = (100, 100); + + (RDCLKU => ALMOSTEMPTY) = (100, 100); + (RDCLKU => EMPTY) = (100, 100); + (RDCLKU => RDCOUNT[0]) = (100, 100); + (RDCLKU => RDCOUNT[10]) = (100, 100); + (RDCLKU => RDCOUNT[11]) = (100, 100); + (RDCLKU => RDCOUNT[12]) = (100, 100); + (RDCLKU => RDCOUNT[1]) = (100, 100); + (RDCLKU => RDCOUNT[2]) = (100, 100); + (RDCLKU => RDCOUNT[3]) = (100, 100); + (RDCLKU => RDCOUNT[4]) = (100, 100); + (RDCLKU => RDCOUNT[5]) = (100, 100); + (RDCLKU => RDCOUNT[6]) = (100, 100); + (RDCLKU => RDCOUNT[7]) = (100, 100); + (RDCLKU => RDCOUNT[8]) = (100, 100); + (RDCLKU => RDCOUNT[9]) = (100, 100); + (RDCLKU => RDERR) = (100, 100); + + (RDRCLKU => ALMOSTEMPTY) = (100, 100); + (RDRCLKU => EMPTY) = (100, 100); + (RDRCLKU => RDCOUNT[0]) = (100, 100); + (RDRCLKU => RDCOUNT[10]) = (100, 100); + (RDRCLKU => RDCOUNT[11]) = (100, 100); + (RDRCLKU => RDCOUNT[12]) = (100, 100); + (RDRCLKU => RDCOUNT[1]) = (100, 100); + (RDRCLKU => RDCOUNT[2]) = (100, 100); + (RDRCLKU => RDCOUNT[3]) = (100, 100); + (RDRCLKU => RDCOUNT[4]) = (100, 100); + (RDRCLKU => RDCOUNT[5]) = (100, 100); + (RDRCLKU => RDCOUNT[6]) = (100, 100); + (RDRCLKU => RDCOUNT[7]) = (100, 100); + (RDRCLKU => RDCOUNT[8]) = (100, 100); + (RDRCLKU => RDCOUNT[9]) = (100, 100); + (RDRCLKU => RDERR) = (100, 100); + + (WRCLKU => ALMOSTFULL) = (100, 100); + (WRCLKU => FULL) = (100, 100); + (WRCLKU => WRCOUNT[0]) = (100, 100); + (WRCLKU => WRCOUNT[10]) = (100, 100); + (WRCLKU => WRCOUNT[11]) = (100, 100); + (WRCLKU => WRCOUNT[12]) = (100, 100); + (WRCLKU => WRCOUNT[1]) = (100, 100); + (WRCLKU => WRCOUNT[2]) = (100, 100); + (WRCLKU => WRCOUNT[3]) = (100, 100); + (WRCLKU => WRCOUNT[4]) = (100, 100); + (WRCLKU => WRCOUNT[5]) = (100, 100); + (WRCLKU => WRCOUNT[6]) = (100, 100); + (WRCLKU => WRCOUNT[7]) = (100, 100); + (WRCLKU => WRCOUNT[8]) = (100, 100); + (WRCLKU => WRCOUNT[9]) = (100, 100); + (WRCLKU => WRERR) = (100, 100); + + specparam PATHPULSE$ = 0; + + endspecify + +endmodule // FIFO36_72_EXP + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/FIFO36_EXP.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/FIFO36_EXP.v new file mode 100644 index 0000000..ce539d6 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/FIFO36_EXP.v @@ -0,0 +1,327 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/rainier/FIFO36_EXP.v,v 1.12 2007/06/15 20:58:41 wloo Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2005 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / 36K-Bit FIFO +// /___/ /\ Filename : FIFO36_EXP.v +// \ \ / \ Timestamp : Tues July 26 16:44:06 PST 2005 +// \___\/\___\ +// +// Revision: +// 07/26/05 - Initial version. +// 06/14/07 - Implemented high performace version of the model. +// End Revision + +`timescale 1 ps/1 ps + +module FIFO36_EXP (ALMOSTEMPTY, ALMOSTFULL, DO, DOP, EMPTY, FULL, RDCOUNT, RDERR, WRCOUNT, WRERR, + DI, DIP, RDCLKL, RDCLKU, RDEN, RDRCLKL, RDRCLKU, RST, WRCLKL, WRCLKU, WREN); + + parameter ALMOST_EMPTY_OFFSET = 13'h0080; + parameter ALMOST_FULL_OFFSET = 13'h0080; + parameter integer DATA_WIDTH = 4; + parameter integer DO_REG = 1; + parameter EN_SYN = "FALSE"; + parameter FIRST_WORD_FALL_THROUGH = "FALSE"; + parameter SIM_MODE = "SAFE"; + + output ALMOSTEMPTY; + output ALMOSTFULL; + output [31:0] DO; + output [3:0] DOP; + output EMPTY; + output FULL; + output [12:0] RDCOUNT; + output RDERR; + output [12:0] WRCOUNT; + output WRERR; + + input [31:0] DI; + input [3:0] DIP; + input RDCLKL; + input RDCLKU; + input RDEN; + input RDRCLKL; + input RDRCLKU; + input RST; + input WRCLKL; + input WRCLKU; + input WREN; + + tri0 GSR = glbl.GSR; + + wire [31:0] dangle_out32; + wire [3:0] dangle_out4; + wire [7:0] dangle_out8; + wire dangle_out; + + AFIFO36_INTERNAL INT_FIFO (.ALMOSTEMPTY(ALMOSTEMPTY), .ALMOSTFULL(ALMOSTFULL), .DBITERR(dangle_out), .DO({dangle_out32,DO}), .DOP({dangle_out4,DOP}), .ECCPARITY(dangle_out8), .EMPTY(EMPTY), .FULL(FULL), .RDCOUNT(RDCOUNT), .RDERR(RDERR), .SBITERR(dangle_out), .WRCOUNT(WRCOUNT), .WRERR(WRERR), + .DI({32'b0,DI}), .DIP({4'b0,DIP}), .RDCLK(RDCLKL), .RDEN(RDEN), .RDRCLK(RDRCLKL), .RST(RST), .WRCLK(WRCLKL), .WREN(WREN)); + + defparam INT_FIFO.ALMOST_EMPTY_OFFSET = ALMOST_EMPTY_OFFSET; + defparam INT_FIFO.ALMOST_FULL_OFFSET = ALMOST_FULL_OFFSET; + defparam INT_FIFO.DATA_WIDTH = DATA_WIDTH; + defparam INT_FIFO.DO_REG = DO_REG; + defparam INT_FIFO.EN_SYN = EN_SYN; + defparam INT_FIFO.FIRST_WORD_FALL_THROUGH = FIRST_WORD_FALL_THROUGH; + defparam INT_FIFO.SIM_MODE = SIM_MODE; + + specify + + (RDCLKL => ALMOSTEMPTY) = (100, 100); + (RDCLKL => DOP[0]) = (100, 100); + (RDCLKL => DOP[1]) = (100, 100); + (RDCLKL => DOP[2]) = (100, 100); + (RDCLKL => DOP[3]) = (100, 100); + (RDCLKL => DO[0]) = (100, 100); + (RDCLKL => DO[10]) = (100, 100); + (RDCLKL => DO[11]) = (100, 100); + (RDCLKL => DO[12]) = (100, 100); + (RDCLKL => DO[13]) = (100, 100); + (RDCLKL => DO[14]) = (100, 100); + (RDCLKL => DO[15]) = (100, 100); + (RDCLKL => DO[16]) = (100, 100); + (RDCLKL => DO[17]) = (100, 100); + (RDCLKL => DO[18]) = (100, 100); + (RDCLKL => DO[19]) = (100, 100); + (RDCLKL => DO[1]) = (100, 100); + (RDCLKL => DO[20]) = (100, 100); + (RDCLKL => DO[21]) = (100, 100); + (RDCLKL => DO[22]) = (100, 100); + (RDCLKL => DO[23]) = (100, 100); + (RDCLKL => DO[24]) = (100, 100); + (RDCLKL => DO[25]) = (100, 100); + (RDCLKL => DO[26]) = (100, 100); + (RDCLKL => DO[27]) = (100, 100); + (RDCLKL => DO[28]) = (100, 100); + (RDCLKL => DO[29]) = (100, 100); + (RDCLKL => DO[2]) = (100, 100); + (RDCLKL => DO[30]) = (100, 100); + (RDCLKL => DO[31]) = (100, 100); + (RDCLKL => DO[3]) = (100, 100); + (RDCLKL => DO[4]) = (100, 100); + (RDCLKL => DO[5]) = (100, 100); + (RDCLKL => DO[6]) = (100, 100); + (RDCLKL => DO[7]) = (100, 100); + (RDCLKL => DO[8]) = (100, 100); + (RDCLKL => DO[9]) = (100, 100); + (RDCLKL => EMPTY) = (100, 100); + (RDCLKL => RDCOUNT[0]) = (100, 100); + (RDCLKL => RDCOUNT[10]) = (100, 100); + (RDCLKL => RDCOUNT[11]) = (100, 100); + (RDCLKL => RDCOUNT[12]) = (100, 100); + (RDCLKL => RDCOUNT[1]) = (100, 100); + (RDCLKL => RDCOUNT[2]) = (100, 100); + (RDCLKL => RDCOUNT[3]) = (100, 100); + (RDCLKL => RDCOUNT[4]) = (100, 100); + (RDCLKL => RDCOUNT[5]) = (100, 100); + (RDCLKL => RDCOUNT[6]) = (100, 100); + (RDCLKL => RDCOUNT[7]) = (100, 100); + (RDCLKL => RDCOUNT[8]) = (100, 100); + (RDCLKL => RDCOUNT[9]) = (100, 100); + (RDCLKL => RDERR) = (100, 100); + + (RDRCLKL => ALMOSTEMPTY) = (100, 100); + (RDRCLKL => DOP[0]) = (100, 100); + (RDRCLKL => DOP[1]) = (100, 100); + (RDRCLKL => DOP[2]) = (100, 100); + (RDRCLKL => DOP[3]) = (100, 100); + (RDRCLKL => DO[0]) = (100, 100); + (RDRCLKL => DO[10]) = (100, 100); + (RDRCLKL => DO[11]) = (100, 100); + (RDRCLKL => DO[12]) = (100, 100); + (RDRCLKL => DO[13]) = (100, 100); + (RDRCLKL => DO[14]) = (100, 100); + (RDRCLKL => DO[15]) = (100, 100); + (RDRCLKL => DO[16]) = (100, 100); + (RDRCLKL => DO[17]) = (100, 100); + (RDRCLKL => DO[18]) = (100, 100); + (RDRCLKL => DO[19]) = (100, 100); + (RDRCLKL => DO[1]) = (100, 100); + (RDRCLKL => DO[20]) = (100, 100); + (RDRCLKL => DO[21]) = (100, 100); + (RDRCLKL => DO[22]) = (100, 100); + (RDRCLKL => DO[23]) = (100, 100); + (RDRCLKL => DO[24]) = (100, 100); + (RDRCLKL => DO[25]) = (100, 100); + (RDRCLKL => DO[26]) = (100, 100); + (RDRCLKL => DO[27]) = (100, 100); + (RDRCLKL => DO[28]) = (100, 100); + (RDRCLKL => DO[29]) = (100, 100); + (RDRCLKL => DO[2]) = (100, 100); + (RDRCLKL => DO[30]) = (100, 100); + (RDRCLKL => DO[31]) = (100, 100); + (RDRCLKL => DO[3]) = (100, 100); + (RDRCLKL => DO[4]) = (100, 100); + (RDRCLKL => DO[5]) = (100, 100); + (RDRCLKL => DO[6]) = (100, 100); + (RDRCLKL => DO[7]) = (100, 100); + (RDRCLKL => DO[8]) = (100, 100); + (RDRCLKL => DO[9]) = (100, 100); + (RDRCLKL => EMPTY) = (100, 100); + (RDRCLKL => RDCOUNT[0]) = (100, 100); + (RDRCLKL => RDCOUNT[10]) = (100, 100); + (RDRCLKL => RDCOUNT[11]) = (100, 100); + (RDRCLKL => RDCOUNT[12]) = (100, 100); + (RDRCLKL => RDCOUNT[1]) = (100, 100); + (RDRCLKL => RDCOUNT[2]) = (100, 100); + (RDRCLKL => RDCOUNT[3]) = (100, 100); + (RDRCLKL => RDCOUNT[4]) = (100, 100); + (RDRCLKL => RDCOUNT[5]) = (100, 100); + (RDRCLKL => RDCOUNT[6]) = (100, 100); + (RDRCLKL => RDCOUNT[7]) = (100, 100); + (RDRCLKL => RDCOUNT[8]) = (100, 100); + (RDRCLKL => RDCOUNT[9]) = (100, 100); + (RDRCLKL => RDERR) = (100, 100); + + (WRCLKL => ALMOSTFULL) = (100, 100); + (WRCLKL => FULL) = (100, 100); + (WRCLKL => WRCOUNT[0]) = (100, 100); + (WRCLKL => WRCOUNT[10]) = (100, 100); + (WRCLKL => WRCOUNT[11]) = (100, 100); + (WRCLKL => WRCOUNT[12]) = (100, 100); + (WRCLKL => WRCOUNT[1]) = (100, 100); + (WRCLKL => WRCOUNT[2]) = (100, 100); + (WRCLKL => WRCOUNT[3]) = (100, 100); + (WRCLKL => WRCOUNT[4]) = (100, 100); + (WRCLKL => WRCOUNT[5]) = (100, 100); + (WRCLKL => WRCOUNT[6]) = (100, 100); + (WRCLKL => WRCOUNT[7]) = (100, 100); + (WRCLKL => WRCOUNT[8]) = (100, 100); + (WRCLKL => WRCOUNT[9]) = (100, 100); + (WRCLKL => WRERR) = (100, 100); + + (RDCLKU => ALMOSTEMPTY) = (100, 100); + (RDCLKU => DOP[0]) = (100, 100); + (RDCLKU => DOP[1]) = (100, 100); + (RDCLKU => DOP[2]) = (100, 100); + (RDCLKU => DOP[3]) = (100, 100); + (RDCLKU => DO[0]) = (100, 100); + (RDCLKU => DO[10]) = (100, 100); + (RDCLKU => DO[11]) = (100, 100); + (RDCLKU => DO[12]) = (100, 100); + (RDCLKU => DO[13]) = (100, 100); + (RDCLKU => DO[14]) = (100, 100); + (RDCLKU => DO[15]) = (100, 100); + (RDCLKU => DO[16]) = (100, 100); + (RDCLKU => DO[17]) = (100, 100); + (RDCLKU => DO[18]) = (100, 100); + (RDCLKU => DO[19]) = (100, 100); + (RDCLKU => DO[1]) = (100, 100); + (RDCLKU => DO[20]) = (100, 100); + (RDCLKU => DO[21]) = (100, 100); + (RDCLKU => DO[22]) = (100, 100); + (RDCLKU => DO[23]) = (100, 100); + (RDCLKU => DO[24]) = (100, 100); + (RDCLKU => DO[25]) = (100, 100); + (RDCLKU => DO[26]) = (100, 100); + (RDCLKU => DO[27]) = (100, 100); + (RDCLKU => DO[28]) = (100, 100); + (RDCLKU => DO[29]) = (100, 100); + (RDCLKU => DO[2]) = (100, 100); + (RDCLKU => DO[30]) = (100, 100); + (RDCLKU => DO[31]) = (100, 100); + (RDCLKU => DO[3]) = (100, 100); + (RDCLKU => DO[4]) = (100, 100); + (RDCLKU => DO[5]) = (100, 100); + (RDCLKU => DO[6]) = (100, 100); + (RDCLKU => DO[7]) = (100, 100); + (RDCLKU => DO[8]) = (100, 100); + (RDCLKU => DO[9]) = (100, 100); + (RDCLKU => EMPTY) = (100, 100); + (RDCLKU => RDCOUNT[0]) = (100, 100); + (RDCLKU => RDCOUNT[10]) = (100, 100); + (RDCLKU => RDCOUNT[11]) = (100, 100); + (RDCLKU => RDCOUNT[12]) = (100, 100); + (RDCLKU => RDCOUNT[1]) = (100, 100); + (RDCLKU => RDCOUNT[2]) = (100, 100); + (RDCLKU => RDCOUNT[3]) = (100, 100); + (RDCLKU => RDCOUNT[4]) = (100, 100); + (RDCLKU => RDCOUNT[5]) = (100, 100); + (RDCLKU => RDCOUNT[6]) = (100, 100); + (RDCLKU => RDCOUNT[7]) = (100, 100); + (RDCLKU => RDCOUNT[8]) = (100, 100); + (RDCLKU => RDCOUNT[9]) = (100, 100); + (RDCLKU => RDERR) = (100, 100); + + (RDRCLKU => ALMOSTEMPTY) = (100, 100); + (RDRCLKU => DOP[0]) = (100, 100); + (RDRCLKU => DOP[1]) = (100, 100); + (RDRCLKU => DOP[2]) = (100, 100); + (RDRCLKU => DOP[3]) = (100, 100); + (RDRCLKU => DO[0]) = (100, 100); + (RDRCLKU => DO[10]) = (100, 100); + (RDRCLKU => DO[11]) = (100, 100); + (RDRCLKU => DO[12]) = (100, 100); + (RDRCLKU => DO[13]) = (100, 100); + (RDRCLKU => DO[14]) = (100, 100); + (RDRCLKU => DO[15]) = (100, 100); + (RDRCLKU => DO[16]) = (100, 100); + (RDRCLKU => DO[17]) = (100, 100); + (RDRCLKU => DO[18]) = (100, 100); + (RDRCLKU => DO[19]) = (100, 100); + (RDRCLKU => DO[1]) = (100, 100); + (RDRCLKU => DO[20]) = (100, 100); + (RDRCLKU => DO[21]) = (100, 100); + (RDRCLKU => DO[22]) = (100, 100); + (RDRCLKU => DO[23]) = (100, 100); + (RDRCLKU => DO[24]) = (100, 100); + (RDRCLKU => DO[25]) = (100, 100); + (RDRCLKU => DO[26]) = (100, 100); + (RDRCLKU => DO[27]) = (100, 100); + (RDRCLKU => DO[28]) = (100, 100); + (RDRCLKU => DO[29]) = (100, 100); + (RDRCLKU => DO[2]) = (100, 100); + (RDRCLKU => DO[30]) = (100, 100); + (RDRCLKU => DO[31]) = (100, 100); + (RDRCLKU => DO[3]) = (100, 100); + (RDRCLKU => DO[4]) = (100, 100); + (RDRCLKU => DO[5]) = (100, 100); + (RDRCLKU => DO[6]) = (100, 100); + (RDRCLKU => DO[7]) = (100, 100); + (RDRCLKU => DO[8]) = (100, 100); + (RDRCLKU => DO[9]) = (100, 100); + (RDRCLKU => EMPTY) = (100, 100); + (RDRCLKU => RDCOUNT[0]) = (100, 100); + (RDRCLKU => RDCOUNT[10]) = (100, 100); + (RDRCLKU => RDCOUNT[11]) = (100, 100); + (RDRCLKU => RDCOUNT[12]) = (100, 100); + (RDRCLKU => RDCOUNT[1]) = (100, 100); + (RDRCLKU => RDCOUNT[2]) = (100, 100); + (RDRCLKU => RDCOUNT[3]) = (100, 100); + (RDRCLKU => RDCOUNT[4]) = (100, 100); + (RDRCLKU => RDCOUNT[5]) = (100, 100); + (RDRCLKU => RDCOUNT[6]) = (100, 100); + (RDRCLKU => RDCOUNT[7]) = (100, 100); + (RDRCLKU => RDCOUNT[8]) = (100, 100); + (RDRCLKU => RDCOUNT[9]) = (100, 100); + (RDRCLKU => RDERR) = (100, 100); + + (WRCLKU => ALMOSTFULL) = (100, 100); + (WRCLKU => FULL) = (100, 100); + (WRCLKU => WRCOUNT[0]) = (100, 100); + (WRCLKU => WRCOUNT[10]) = (100, 100); + (WRCLKU => WRCOUNT[11]) = (100, 100); + (WRCLKU => WRCOUNT[12]) = (100, 100); + (WRCLKU => WRCOUNT[1]) = (100, 100); + (WRCLKU => WRCOUNT[2]) = (100, 100); + (WRCLKU => WRCOUNT[3]) = (100, 100); + (WRCLKU => WRCOUNT[4]) = (100, 100); + (WRCLKU => WRCOUNT[5]) = (100, 100); + (WRCLKU => WRCOUNT[6]) = (100, 100); + (WRCLKU => WRCOUNT[7]) = (100, 100); + (WRCLKU => WRCOUNT[8]) = (100, 100); + (WRCLKU => WRCOUNT[9]) = (100, 100); + (WRCLKU => WRERR) = (100, 100); + + specparam PATHPULSE$ = 0; + + endspecify + +endmodule // FIFO36_EXP diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/FMAP.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/FMAP.v new file mode 100644 index 0000000..e92ab16 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/FMAP.v @@ -0,0 +1,28 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/FMAP.v,v 1.5 2007/05/23 21:43:33 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / F Function Generator Partitioning Control Symbol +// /___/ /\ Filename : FMAP.v +// \ \ / \ Timestamp : Thu Mar 25 16:42:18 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. + +`timescale 1 ps / 1 ps + + +module FMAP (I1, I2, I3, I4, O); + + input I1, I2, I3, I4, O; + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/FRAME_ECC_VIRTEX4.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/FRAME_ECC_VIRTEX4.v new file mode 100644 index 0000000..8499e40 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/FRAME_ECC_VIRTEX4.v @@ -0,0 +1,28 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/virtex4/FRAME_ECC_VIRTEX4.v,v 1.3 2004/03/31 22:39:42 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / +// /___/ /\ Filename : FRAME_ECC_VIRTEX4.v +// \ \ / \ Timestamp : Thu Mar 25 16:43:44 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. + +`timescale 1 ps / 1 ps + +module FRAME_ECC_VIRTEX4 (ERROR, SYNDROME, SYNDROMEVALID); + + output ERROR; + output [11:0] SYNDROME; + output SYNDROMEVALID; + +endmodule // FRAME_ECC_VIRTEX4 + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/FRAME_ECC_VIRTEX5.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/FRAME_ECC_VIRTEX5.v new file mode 100644 index 0000000..0075713 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/FRAME_ECC_VIRTEX5.v @@ -0,0 +1,38 @@ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / +// /___/ /\ Filename : FRAME_ECC_VIRTEX5.v +// \ \ / \ Timestamp : Thu Jul 21 13:42:30 PDT 2005 +// \___\/\___\ +// +// Revision: +// 07/21/05 - Initial version. +// End Revision + +`timescale 1 ps / 1 ps + +module FRAME_ECC_VIRTEX5 ( + CRCERROR, + ECCERROR, + SYNDROME, + SYNDROMEVALID +); + +output CRCERROR; +output ECCERROR; +output SYNDROMEVALID; +output [11:0] SYNDROME; + +specify + specparam PATHPULSE$ = 0; +endspecify + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/FRAME_ECC_VIRTEX6.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/FRAME_ECC_VIRTEX6.v new file mode 100644 index 0000000..8d58f07 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/FRAME_ECC_VIRTEX6.v @@ -0,0 +1,461 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/blanc/FRAME_ECC_VIRTEX6.v,v 1.4 2010/02/10 23:34:59 yanx Exp $ +/////////////////////////////////////////////////////// +// Copyright (c) 2009 Xilinx Inc. +// All Right Reserved. +/////////////////////////////////////////////////////// +// +// ____ ___ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : +// / / +// /__/ /\ Filename : FRAME_ECC_VIRTEX6.v +// \ \ / \ +// \__\/\__ \ +// +// Revision: 1.0 +/////////////////////////////////////////////////////// + +`timescale 1 ps / 1 ps + +module FRAME_ECC_VIRTEX6 ( + CRCERROR, + ECCERROR, + ECCERRORSINGLE, + FAR, + SYNBIT, + SYNDROME, + SYNDROMEVALID, + SYNWORD +); + + + parameter FARSRC = "EFAR"; + parameter FRAME_RBT_IN_FILENAME = "frame_rbt_v6.txt"; + localparam FRAME_ECC_OUT_RBT_FILENAME = "frame_rbt_out_v6.txt"; + localparam FRAME_ECC_OUT_ECC_FILENAME = "frame_ecc_out_v6.txt"; + + output CRCERROR; + output ECCERROR; + output ECCERRORSINGLE; + output SYNDROMEVALID; + output [12:0] SYNDROME; + output [23:0] FAR; + output [4:0] SYNBIT; + output [6:0] SYNWORD; + + reg clk_osc = 0; + integer rbt_fd; + integer ecc_ecc_out_fd; + integer ecc_rbt_out_fd; + reg [31:0] rb_data = 32'b0; + reg [31:0] data_rbt; + reg [31:0] tmpwd1; + reg [31:0] tmpwd2; + reg sim_file_flag = 0; + reg [31:0] frame_data_bak[255:174]; + reg [31:0] frame_data[255:174]; + integer frame_addr_i; + reg [31:0] frame_addr; + reg [31:0] rb_crc_rbt; + reg [31:0] crc_curr = 32'b0; + reg [31:0] crc_new = 32'b0; + reg [36:0] crc_input = 32'b0; + reg rbcrc_err = 0; + reg rd_rbt_hold = 0; + reg rd_rbt_hold1 = 0; + reg rd_rbt_hold2 = 0; + reg [6:0] ecc_wadr; + reg [4:0] ecc_badr; + reg [31:0] corr_wd; + reg [31:0] corr_wd1; + reg rb_data_en = 0; + reg end_rbt = 0; + reg rd_rbt_en = 0; + reg hamming_rst = 0; + integer i = 0; + integer bi = 174; + integer nbi = 174; + integer n = 174; + + reg ecc_run = 0; + reg calc_syndrome = 1; + wire [12:0] new_S; + wire [12:0] next_S; + reg [12:0] S = 13'd0; + reg S_valid = 0; + reg S_valid_ungated = 0; + reg [31:0] ecc_corr_mask = 32'b0; + reg ecc_error = 0; + reg ecc_error_single = 0; + reg ecc_error_ungated = 0; + reg [4:0] ecc_synbit = 5'b0; + reg [6:0] ecc_synword = 7'b0; + reg [4:0] ecc_synbit_next = 5'b0; + reg [6:0] ecc_synword_next = 7'b0; + reg efar_save = 0; + reg [11:5] hiaddr = 7'd46; + wire [11:5] hiaddrp1; + wire hiaddr63; + wire hiaddr127; + wire hclk; + wire xorall; + wire overall; + wire S_valid_next; + wire S_valid_ungated_next; + wire next_error; + wire [12:0] new_S_xor_S; + wire [6:0] ecc_synword_next_not_par; + reg [160:0] tmps1; + reg [160:0] tmps2; + reg [160:0] tmps3; + + + initial begin + case (FARSRC) + "EFAR" : ; + "FAR" : ; + default : begin + $display("Attribute Syntax Error : The Attribute FARSRC on FRAME_ECC_VIRTEX6 instance %m is set to %s. Legal values for this attribute are EFAR, or FAR.", FARSRC); + $finish; + end + endcase + + sim_file_flag = 0; + if (FRAME_RBT_IN_FILENAME == "NONE") + $display(" Error: The configuration frame data file for FRAME_ECC_VIRTEX6 instance %m was not found. Use X_ICAP_VIRTEX6 to generate frame data file and then use the FRAME_RBT_IN_FILENAME parameter to pass the file name.\n"); + else begin + rbt_fd = $fopen(FRAME_RBT_IN_FILENAME, "r"); + ecc_ecc_out_fd = $fopen(FRAME_ECC_OUT_ECC_FILENAME, "w"); + ecc_rbt_out_fd = $fopen(FRAME_ECC_OUT_RBT_FILENAME, "w"); + if (rbt_fd == 0) + $display(" Error: The configuration frame data file %s for FRAME_ECC_VIRTEX6 instance %m was not found. Use X_ICAP_VIRTEX6 to generate frame data file and then use the FRAME_RBT_IN_FILENAME parameter to pass the file name.\n", FRAME_RBT_IN_FILENAME); + else + if ($fscanf(rbt_fd, "%s\t%s\t%s", tmps1, tmps2, tmps3) != -1) + rd_rbt_en <= #1 1; + + if (ecc_ecc_out_fd == 0) + $display(" Error: The ecc frame data out file frame_ecc_out_v6.txt for FRAME_ECC_VIRTEX6 instance %m can not created.\n"); + if (ecc_rbt_out_fd == 0) + $display(" Error: The rbt frame data out file frame_rbt_out_v6.txt for FRAME_ECC_VIRTEX6 instance %m can not created.\n"); + if (rbt_fd !=0 && ecc_ecc_out_fd != 0 && ecc_rbt_out_fd != 0 ) + sim_file_flag = 1; + end + end + + assign CRCERROR = rbcrc_err; + assign ECCERROR = ecc_error; + assign ECCERRORSINGLE = ecc_error_single; + assign SYNDROMEVALID = S_valid; + assign SYNDROME = S; + assign FAR = frame_addr[23:0]; + assign SYNBIT = ecc_synbit; + assign SYNWORD = ecc_synword; + + + always + #2000 clk_osc <= ~clk_osc; + + always @(negedge clk_osc ) + if (sim_file_flag == 1 && rd_rbt_en == 1 && rd_rbt_hold1 == 0 ) begin + if ( $fscanf(rbt_fd, "%d\t%b\t%b", frame_addr_i, data_rbt, rb_crc_rbt) != -1) begin + rb_data_en <= 1; + frame_addr <= frame_addr_i; + rb_data <= data_rbt; + crc_input[36:0] = {5'b00011, data_rbt}; + crc_new[31:0] = bcc_next(crc_curr, crc_input); + crc_curr[31:0] <= crc_new; + if (n <= 255) begin + frame_data[n] <= data_rbt[31:0]; + if (n == 255) + n <= 174; + else if (n==191) + n <= 193; + else + n <= n+ 1; + end + end + else begin + rb_data_en <= 0; + end_rbt <= 1; + n <= 173; + if ( crc_new != rb_crc_rbt) + rbcrc_err <= 1; + else + rbcrc_err <= 0; + $fclose(rbt_fd); + end + end + + always @(negedge clk_osc) + if (rb_data_en == 1) begin + if ( rd_rbt_hold1 == 1 && rd_rbt_hold == 1 && rd_rbt_hold2 == 0) begin + for (bi = 174; bi<= 255; bi=bi+1) + frame_data_bak[bi] = frame_data[bi]; + if (ecc_error_single == 1) begin + ecc_wadr[6:0] = SYNDROME[11:5]; + ecc_badr[4:0] = SYNDROME[4:0]; + corr_wd = frame_data[ecc_wadr]; + corr_wd1 = frame_data[ecc_wadr]; + corr_wd[ecc_badr] = ~corr_wd1[ecc_badr]; + frame_data_bak[ecc_wadr] = corr_wd; + end + for (nbi = 174; nbi<= 255; nbi=nbi+1) begin + if (nbi != 192) begin + tmpwd1 = frame_data[nbi]; + tmpwd2 = frame_data_bak[nbi]; + $fwriteb(ecc_rbt_out_fd, tmpwd1); + $fwriteb(ecc_rbt_out_fd, "\n"); + $fwriteb(ecc_ecc_out_fd, tmpwd2); + $fwriteb(ecc_ecc_out_fd, "\n"); + end + end + end + end + else if (end_rbt ==1) begin + $fclose(ecc_ecc_out_fd); + $fclose(ecc_rbt_out_fd); + end + + always @(posedge clk_osc) + if (rb_data_en == 1) begin + if (n == 255) + rd_rbt_hold <= 1; + rd_rbt_hold2 <= rd_rbt_hold1; + rd_rbt_hold1 <= rd_rbt_hold; + if (rd_rbt_hold2 ==1) begin + rd_rbt_hold <= 0; + rd_rbt_hold1 <= 0; + rd_rbt_hold2 <= 0; + end + end + else if ( end_rbt == 1) begin + rd_rbt_hold <= 1; + rd_rbt_hold1 <= 1; + rd_rbt_hold2 <= 1; + end + + always @(negedge clk_osc) + if (rd_rbt_hold2 == 1 && hamming_rst == 0) + hamming_rst <= 1; + else + hamming_rst <= 0; + + assign S_valid_next = rb_data_en & hiaddr127 & ~ecc_run; + assign S_valid_ungated_next = rb_data_en & hiaddr127; + assign next_error = (| next_S); + assign hiaddrp1 = hiaddr + 1; + assign hiaddr63 = & hiaddr[10:5]; + assign hiaddr127 = & hiaddr[11:5]; + assign hclk = ( hiaddr == 7'd87 ) ? 1 : 0; + + always @( posedge clk_osc or posedge hamming_rst) + if (hamming_rst == 1) + hiaddr <= 7'd46; + else if ( rb_data_en == 1 ) begin + if ( hiaddr127 ) + hiaddr <= 7'd46; + else + hiaddr <= { hiaddrp1[11:6], ( hiaddr63 | hiaddrp1[5] ) }; + end + + assign xorall = ( ^ rb_data[31:13] ) ^ ( ( ~ hclk ) & ( ^ rb_data[12:0] ) ); + assign overall = ( ^ rb_data[31:13] ) ^ ( ~(hclk & calc_syndrome) & ( ^ rb_data[12:0] ) ); + + assign new_S[12] = overall; + + assign new_S[4] = rb_data[31] ^ rb_data[30] ^ rb_data[29] ^ rb_data[28] ^ + rb_data[27] ^ rb_data[26] ^ rb_data[25] ^ rb_data[24] ^ + rb_data[23] ^ rb_data[22] ^ rb_data[21] ^ rb_data[20] ^ + rb_data[19] ^ rb_data[18] ^ rb_data[17] ^ rb_data[16] ^ + ( hclk & ~calc_syndrome & rb_data[4] ); + assign new_S[3] = rb_data[31] ^ rb_data[30] ^ rb_data[29] ^ rb_data[28] ^ + rb_data[27] ^ rb_data[26] ^ rb_data[25] ^ rb_data[24] ^ + rb_data[15] ^ rb_data[14] ^ rb_data[13] ^ + ( hclk ? ~calc_syndrome & rb_data[3] : + ( rb_data[12] ^ rb_data[11] ^ rb_data[10] ^ rb_data[9] ^ rb_data[8]) ); + assign new_S[2] = rb_data[31] ^ rb_data[30] ^ rb_data[29] ^ rb_data[28] ^ + rb_data[23] ^ rb_data[22] ^ rb_data[21] ^ rb_data[20] ^ + rb_data[15] ^ rb_data[14] ^ rb_data[13] ^ + ( hclk ? ~calc_syndrome & rb_data[2] : + ( rb_data[12] ^ rb_data[7] ^ rb_data[6] ^ rb_data[5] ^ rb_data[4] ) ); + assign new_S[1] = rb_data[31] ^ rb_data[30] ^ rb_data[27] ^ rb_data[26] ^ + rb_data[23] ^ rb_data[22] ^ rb_data[19] ^ rb_data[18] ^ + rb_data[15] ^ rb_data[14] ^ + ( hclk ? ~calc_syndrome & rb_data[1] : + ( rb_data[11] ^ rb_data[10] ^ rb_data[7] ^ rb_data[6] ^ rb_data[3] ^ rb_data[2] )); + assign new_S[0] = rb_data[31] ^ rb_data[29] ^ rb_data[27] ^ rb_data[25] ^ + rb_data[23] ^ rb_data[21] ^ rb_data[19] ^ rb_data[17] ^ + rb_data[15] ^ rb_data[13] ^ + ( hclk ? ~calc_syndrome & rb_data[0] : + ( rb_data[11] ^ rb_data[9] ^ rb_data[7] ^ rb_data[5] ^ rb_data[3] ^ rb_data[1] ) ); + + assign new_S[11:5] = ( hiaddr & { 7 { xorall } } ) ^ + ( { 7 { hclk & ~calc_syndrome } } & + { rb_data[11], rb_data[10], rb_data[9], rb_data[8], + rb_data[7], rb_data[6], rb_data[5] } ); + + assign new_S_xor_S = S ^ new_S; + assign next_S = (hiaddr127 & calc_syndrome) ? {(^new_S_xor_S), new_S_xor_S[11:0]} : + (hiaddr == 7'd46) ? new_S : new_S_xor_S; + + assign ecc_synword_next_not_par = new_S_xor_S[11:5] - 7'd46 - {6'b0, new_S_xor_S[11]}; + + always @(ecc_synword_next_not_par, new_S_xor_S) begin + if (!new_S_xor_S[12]) begin + ecc_synword_next = 7'd0; + ecc_synbit_next = 5'd0; + end else begin + case (new_S_xor_S[11:0]) + 12'h000 : begin + ecc_synword_next = 7'd40; + ecc_synbit_next = 5'd12; + end + 12'h001 : begin + ecc_synword_next = 7'd40; + ecc_synbit_next = 5'd0; + end + 12'h002 : begin + ecc_synword_next = 7'd40; + ecc_synbit_next = 5'd1; + end + 12'h004 : begin + ecc_synword_next = 7'd40; + ecc_synbit_next = 5'd2; + end + 12'h008 : begin + ecc_synword_next = 7'd40; + ecc_synbit_next = 5'd3; + end + 12'h010 : begin + ecc_synword_next = 7'd40; + ecc_synbit_next = 5'd4; + end + 12'h020 : begin + ecc_synword_next = 7'd40; + ecc_synbit_next = 5'd5; + end + 12'h040 : begin + ecc_synword_next = 7'd40; + ecc_synbit_next = 5'd6; + end + 12'h080 : begin + ecc_synword_next = 7'd40; + ecc_synbit_next = 5'd7; + end + 12'h100 : begin + ecc_synword_next = 7'd40; + ecc_synbit_next = 5'd8; + end + 12'h200 : begin + ecc_synword_next = 7'd40; + ecc_synbit_next = 5'd9; + end + 12'h400 : begin + ecc_synword_next = 7'd40; + ecc_synbit_next = 5'd10; + end + 12'h800 : begin + ecc_synword_next = 7'd40; + ecc_synbit_next = 5'd11; + end + default : begin + ecc_synword_next = ecc_synword_next_not_par; + ecc_synbit_next = new_S_xor_S[4:0]; + end + endcase + end + end + + always @( posedge clk_osc or posedge hamming_rst) begin + if ( hamming_rst == 1 ) begin + S_valid <= 0; + S_valid_ungated <= 0; + S <= 13'd0; + end + else if ( rb_data_en == 1 ) begin + S_valid_ungated <= S_valid_ungated_next; + S_valid <= S_valid_next; + S <= next_S; + end else begin + S_valid_ungated <= 0; + S_valid <= 0; + end + + if (hamming_rst == 1 ) begin + ecc_synword <= 7'd0; + ecc_synbit <= 5'd0; + end + else if ( S_valid_next & ~efar_save ) begin + ecc_synword <= ecc_synword_next; + ecc_synbit <= ecc_synbit_next; + end + + if (hamming_rst == 1) begin + ecc_error <= 0; + ecc_error_single <= 0; + end + else if (S_valid_next == 1) begin + ecc_error <= next_error; + ecc_error_single <= next_S[12]; + end + + if (hamming_rst == 1) + ecc_error_ungated <= 0; + else if (S_valid_ungated_next == 1) + ecc_error_ungated <= next_error; + + if (hamming_rst == 1) + efar_save <= 0; + else if (ecc_error == 1 | ((S_valid_ungated_next & next_error) == 1)) + efar_save <= 1; + + end + + + function [31:0] bcc_next; + input [31:0] bcc; + input [36:0] in; + reg [31:0] x; + reg [36:0] m; + begin + m = in; + x = in[31:0] ^ bcc; + + bcc_next[31] = m[32]^m[36]^x[31]^x[30]^x[29]^x[28]^x[27]^x[24]^x[20]^x[19]^x[18]^x[15]^x[13]^x[11]^x[10]^x[9]^x[8]^x[6]^x[5]^x[1]^x[0]; + bcc_next[30] = m[35]^x[31]^x[30]^x[29]^x[28]^x[27]^x[26]^x[23]^x[19]^x[18]^x[17]^x[14]^x[12]^x[10]^x[9]^x[8]^x[7]^x[5]^x[4]^x[0]; + bcc_next[29] = m[34]^x[30]^x[29]^x[28]^x[27]^x[26]^x[25]^x[22]^x[18]^x[17]^x[16]^x[13]^x[11]^x[9]^x[8]^x[7]^x[6]^x[4]^x[3]; + bcc_next[28] = m[33]^x[29]^x[28]^x[27]^x[26]^x[25]^x[24]^x[21]^x[17]^x[16]^x[15]^x[12]^x[10]^x[8]^x[7]^x[6]^x[5]^x[3]^x[2]; + bcc_next[27] = m[32]^x[28]^x[27]^x[26]^x[25]^x[24]^x[23]^x[20]^x[16]^x[15]^x[14]^x[11]^x[9]^x[7]^x[6]^x[5]^x[4]^x[2]^x[1]; + bcc_next[26] = x[31]^x[27]^x[26]^x[25]^x[24]^x[23]^x[22]^x[19]^x[15]^x[14]^x[13]^x[10]^x[8]^x[6]^x[5]^x[4]^x[3]^x[1]^x[0]; + bcc_next[25] = m[32]^m[36]^x[31]^x[29]^x[28]^x[27]^x[26]^x[25]^x[23]^x[22]^x[21]^x[20]^x[19]^x[15]^x[14]^x[12]^x[11]^x[10]^x[8]^x[7]^x[6]^x[4]^x[3]^x[2]^x[1]; + bcc_next[24] = m[35]^x[31]^x[30]^x[28]^x[27]^x[26]^x[25]^x[24]^x[22]^x[21]^x[20]^x[19]^x[18]^x[14]^x[13]^x[11]^x[10]^x[9]^x[7]^x[6]^x[5]^x[3]^x[2]^x[1]^x[0]; + bcc_next[23] = m[32]^m[34]^m[36]^x[31]^x[28]^x[26]^x[25]^x[23]^x[21]^x[17]^x[15]^x[12]^x[11]^x[4]^x[2]; + bcc_next[22] = m[32]^m[33]^m[35]^m[36]^x[29]^x[28]^x[25]^x[22]^x[19]^x[18]^x[16]^x[15]^x[14]^x[13]^x[9]^x[8]^x[6]^x[5]^x[3]^x[0]; + bcc_next[21] = m[34]^m[35]^m[36]^x[30]^x[29]^x[21]^x[20]^x[19]^x[17]^x[14]^x[12]^x[11]^x[10]^x[9]^x[7]^x[6]^x[4]^x[2]^x[1]^x[0]; + bcc_next[20] = m[32]^m[33]^m[34]^m[35]^m[36]^x[31]^x[30]^x[27]^x[24]^x[16]^x[15]^x[3]; + bcc_next[19] = m[32]^m[33]^m[34]^m[35]^x[31]^x[30]^x[29]^x[26]^x[23]^x[15]^x[14]^x[2]; + bcc_next[18] = m[33]^m[34]^m[36]^x[27]^x[25]^x[24]^x[22]^x[20]^x[19]^x[18]^x[15]^x[14]^x[11]^x[10]^x[9]^x[8]^x[6]^x[5]^x[0]; + bcc_next[17] = m[33]^m[35]^m[36]^x[31]^x[30]^x[29]^x[28]^x[27]^x[26]^x[23]^x[21]^x[20]^x[17]^x[15]^x[14]^x[11]^x[7]^x[6]^x[4]^x[1]^x[0]; + bcc_next[16] = m[32]^m[34]^m[35]^x[30]^x[29]^x[28]^x[27]^x[26]^x[25]^x[22]^x[20]^x[19]^x[16]^x[14]^x[13]^x[10]^x[6]^x[5]^x[3]^x[0]; + bcc_next[15] = m[33]^m[34]^x[31]^x[29]^x[28]^x[27]^x[26]^x[25]^x[24]^x[21]^x[19]^x[18]^x[15]^x[13]^x[12]^x[9]^x[5]^x[4]^x[2]; + bcc_next[14] = m[32]^m[33]^x[30]^x[28]^x[27]^x[26]^x[25]^x[24]^x[23]^x[20]^x[18]^x[17]^x[14]^x[12]^x[11]^x[8]^x[4]^x[3]^x[1]; + bcc_next[13] = m[36]^x[30]^x[28]^x[26]^x[25]^x[23]^x[22]^x[20]^x[18]^x[17]^x[16]^x[15]^x[9]^x[8]^x[7]^x[6]^x[5]^x[3]^x[2]^x[1]; + bcc_next[12] = m[32]^m[35]^m[36]^x[31]^x[30]^x[28]^x[25]^x[22]^x[21]^x[20]^x[18]^x[17]^x[16]^x[14]^x[13]^x[11]^x[10]^x[9]^x[7]^x[4]^x[2]; + bcc_next[11] = m[32]^m[34]^m[35]^m[36]^x[28]^x[21]^x[18]^x[17]^x[16]^x[12]^x[11]^x[5]^x[3]^x[0]; + bcc_next[10] = m[33]^m[34]^m[35]^x[31]^x[27]^x[20]^x[17]^x[16]^x[15]^x[11]^x[10]^x[4]^x[2]; + bcc_next[9] = m[33]^m[34]^m[36]^x[31]^x[29]^x[28]^x[27]^x[26]^x[24]^x[20]^x[18]^x[16]^x[14]^x[13]^x[11]^x[8]^x[6]^x[5]^x[3]^x[0]; + bcc_next[8] = m[33]^m[35]^m[36]^x[31]^x[29]^x[26]^x[25]^x[24]^x[23]^x[20]^x[18]^x[17]^x[12]^x[11]^x[9]^x[8]^x[7]^x[6]^x[4]^x[2]^x[1]^x[0]; + bcc_next[7] = m[32]^m[34]^m[35]^x[30]^x[28]^x[25]^x[24]^x[23]^x[22]^x[19]^x[17]^x[16]^x[11]^x[10]^x[8]^x[7]^x[6]^x[5]^x[3]^x[1]^x[0]; + bcc_next[6] = m[32]^m[33]^m[34]^m[36]^x[30]^x[28]^x[23]^x[22]^x[21]^x[20]^x[19]^x[16]^x[13]^x[11]^x[8]^x[7]^x[4]^x[2]^x[1]; + bcc_next[5] = m[33]^m[35]^m[36]^x[30]^x[28]^x[24]^x[22]^x[21]^x[13]^x[12]^x[11]^x[9]^x[8]^x[7]^x[5]^x[3]; + bcc_next[4] = m[34]^m[35]^m[36]^x[31]^x[30]^x[28]^x[24]^x[23]^x[21]^x[19]^x[18]^x[15]^x[13]^x[12]^x[9]^x[7]^x[5]^x[4]^x[2]^x[1]^x[0]; + bcc_next[3] = m[32]^m[33]^m[34]^m[35]^m[36]^x[31]^x[28]^x[24]^x[23]^x[22]^x[19]^x[17]^x[15]^x[14]^x[13]^x[12]^x[10]^x[9]^x[5]^x[4]^x[3]; + bcc_next[2] = m[32]^m[33]^m[34]^m[35]^x[31]^x[30]^x[27]^x[23]^x[22]^x[21]^x[18]^x[16]^x[14]^x[13]^x[12]^x[11]^x[9]^x[8]^x[4]^x[3]^x[2]; + bcc_next[1] = m[32]^m[33]^m[34]^x[31]^x[30]^x[29]^x[26]^x[22]^x[21]^x[20]^x[17]^x[15]^x[13]^x[12]^x[11]^x[10]^x[8]^x[7]^x[3]^x[2]^x[1]; + bcc_next[0] = m[32]^m[33]^x[31]^x[30]^x[29]^x[28]^x[25]^x[21]^x[20]^x[19]^x[16]^x[14]^x[12]^x[11]^x[10]^x[9]^x[7]^x[6]^x[2]^x[1]^x[0]; + end + endfunction + +endmodule diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/GND.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/GND.v new file mode 100644 index 0000000..d3ed609 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/GND.v @@ -0,0 +1,30 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/GND.v,v 1.5 2007/05/23 21:43:33 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / GND Connection +// /___/ /\ Filename : GND.v +// \ \ / \ Timestamp : Thu Mar 25 16:42:19 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. + +`timescale 1 ps / 1 ps + + +module GND(G); + + output G; + + assign G = 1'b0; + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/GT11.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/GT11.v new file mode 100644 index 0000000..f6cab05 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/GT11.v @@ -0,0 +1,2594 @@ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / 11-Gigabit Transceiver for High-Speed I/O Simulation Model +// /___/ /\ Filename : GT11.v +// \ \ / \ Timestamp : Fri Jun 18 10:57:01 PDT 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/16/05 - Changed default values for some parameters and removed two parameters. Fixed CR#207101. +// 08/08/05 - Changed default parameter values for some parameters (CR 214282). +// 02/22/06 - CR#226003 - Added integer, real parameter type +// 02/28/06 - CR#226322 - Addition of new parameters and change of default values for some parameters. +// End Revision + +`timescale 1 ps / 1 ps + +module GT11 ( + CHBONDO, + COMBUSOUT, + DO, + DRDY, + RXBUFERR, + RXCALFAIL, + RXCHARISCOMMA, + RXCHARISK, + RXCOMMADET, + RXCRCOUT, + RXCYCLELIMIT, + RXDATA, + RXDISPERR, + RXLOCK, + RXLOSSOFSYNC, + RXMCLK, + RXNOTINTABLE, + RXPCSHCLKOUT, + RXREALIGN, + RXRECCLK1, + RXRECCLK2, + RXRUNDISP, + RXSIGDET, + RXSTATUS, + TX1N, + TX1P, + TXBUFERR, + TXCALFAIL, + TXCRCOUT, + TXCYCLELIMIT, + TXKERR, + TXLOCK, + TXOUTCLK1, + TXOUTCLK2, + TXPCSHCLKOUT, + TXRUNDISP, + CHBONDI, + COMBUSIN, + DADDR, + DCLK, + DEN, + DI, + DWE, + ENCHANSYNC, + ENMCOMMAALIGN, + ENPCOMMAALIGN, + GREFCLK, + LOOPBACK, + POWERDOWN, + REFCLK1, + REFCLK2, + RX1N, + RX1P, + RXBLOCKSYNC64B66BUSE, + RXCLKSTABLE, + RXCOMMADETUSE, + RXCRCCLK, + RXCRCDATAVALID, + RXCRCDATAWIDTH, + RXCRCIN, + RXCRCINIT, + RXCRCINTCLK, + RXCRCPD, + RXCRCRESET, + RXDATAWIDTH, + RXDEC64B66BUSE, + RXDEC8B10BUSE, + RXDESCRAM64B66BUSE, + RXIGNOREBTF, + RXINTDATAWIDTH, + RXPMARESET, + RXPOLARITY, + RXRESET, + RXSLIDE, + RXSYNC, + RXUSRCLK, + RXUSRCLK2, + TXBYPASS8B10B, + TXCHARDISPMODE, + TXCHARDISPVAL, + TXCHARISK, + TXCLKSTABLE, + TXCRCCLK, + TXCRCDATAVALID, + TXCRCDATAWIDTH, + TXCRCIN, + TXCRCINIT, + TXCRCINTCLK, + TXCRCPD, + TXCRCRESET, + TXDATA, + TXDATAWIDTH, + TXENC64B66BUSE, + TXENC8B10BUSE, + TXENOOB, + TXGEARBOX64B66BUSE, + TXINHIBIT, + TXINTDATAWIDTH, + TXPMARESET, + TXPOLARITY, + TXRESET, + TXSCRAM64B66BUSE, + TXSYNC, + TXUSRCLK, + TXUSRCLK2 +); + +parameter BANDGAPSEL = "FALSE"; +parameter BIASRESSEL = "FALSE"; +parameter CCCB_ARBITRATOR_DISABLE = "FALSE"; +parameter CHAN_BOND_MODE = "NONE"; +parameter CHAN_BOND_ONE_SHOT = "FALSE"; +parameter CHAN_BOND_SEQ_1_1 = 11'b00000000000; +parameter CHAN_BOND_SEQ_1_2 = 11'b00000000000; +parameter CHAN_BOND_SEQ_1_3 = 11'b00000000000; +parameter CHAN_BOND_SEQ_1_4 = 11'b00000000000; +parameter CHAN_BOND_SEQ_1_MASK = 4'b1110; +parameter CHAN_BOND_SEQ_2_1 = 11'b00000000000; +parameter CHAN_BOND_SEQ_2_2 = 11'b00000000000; +parameter CHAN_BOND_SEQ_2_3 = 11'b00000000000; +parameter CHAN_BOND_SEQ_2_4 = 11'b00000000000; +parameter CHAN_BOND_SEQ_2_MASK = 4'b1110; +parameter CHAN_BOND_SEQ_2_USE = "FALSE"; +parameter CLK_CORRECT_USE = "FALSE"; +parameter CLK_COR_8B10B_DE = "FALSE"; +parameter CLK_COR_SEQ_1_1 = 11'b00000000000; +parameter CLK_COR_SEQ_1_2 = 11'b00000000000; +parameter CLK_COR_SEQ_1_3 = 11'b00000000000; +parameter CLK_COR_SEQ_1_4 = 11'b00000000000; +parameter CLK_COR_SEQ_1_MASK = 4'b1110; +parameter CLK_COR_SEQ_2_1 = 11'b00000000000; +parameter CLK_COR_SEQ_2_2 = 11'b00000000000; +parameter CLK_COR_SEQ_2_3 = 11'b00000000000; +parameter CLK_COR_SEQ_2_4 = 11'b00000000000; +parameter CLK_COR_SEQ_2_MASK = 4'b1110; +parameter CLK_COR_SEQ_2_USE = "FALSE"; +parameter CLK_COR_SEQ_DROP = "FALSE"; +parameter COMMA32 = "FALSE"; +parameter COMMA_10B_MASK = 10'h3FF; +parameter CYCLE_LIMIT_SEL = 2'b00; +parameter DCDR_FILTER = 3'b010; +parameter DEC_MCOMMA_DETECT = "TRUE"; +parameter DEC_PCOMMA_DETECT = "TRUE"; +parameter DEC_VALID_COMMA_ONLY = "TRUE"; +parameter DIGRX_FWDCLK = 2'b00; +parameter DIGRX_SYNC_MODE = "FALSE"; +parameter ENABLE_DCDR = "FALSE"; +parameter FDET_HYS_CAL = 3'b010; +parameter FDET_HYS_SEL = 3'b100; +parameter FDET_LCK_CAL = 3'b100; +parameter FDET_LCK_SEL = 3'b001; +parameter GT11_MODE = "DONT_CARE"; +parameter IREFBIASMODE = 2'b11; +parameter LOOPCAL_WAIT = 2'b00; +parameter MCOMMA_32B_VALUE = 32'h00000000; +parameter MCOMMA_DETECT = "TRUE"; +parameter OPPOSITE_SELECT = "FALSE"; +parameter PCOMMA_32B_VALUE = 32'h00000000; +parameter PCOMMA_DETECT = "TRUE"; +parameter PCS_BIT_SLIP = "FALSE"; +parameter PMACLKENABLE = "TRUE"; +parameter PMACOREPWRENABLE = "TRUE"; +parameter PMAIREFTRIM = 4'b0111; +parameter PMAVBGCTRL = 5'b00000; +parameter PMAVREFTRIM = 4'b0111; +parameter PMA_BIT_SLIP = "FALSE"; +parameter POWER_ENABLE = "TRUE"; +parameter REPEATER = "FALSE"; +parameter RXACTST = "FALSE"; +parameter RXAFEEQ = 9'b000000000; +parameter RXAFEPD = "FALSE"; +parameter RXAFETST = "FALSE"; +parameter RXAPD = "FALSE"; +parameter RXAREGCTRL = 5'b00000; +parameter RXASYNCDIVIDE = 2'b11; +parameter RXBY_32 = "FALSE"; +parameter RXCDRLOS = 6'b000000; +parameter RXCLK0_FORCE_PMACLK = "FALSE"; +parameter RXCLKMODE = 6'b110001; +parameter RXCLMODE = 2'b00; +parameter RXCMADJ = 2'b01; +parameter RXCPSEL = "TRUE"; +parameter RXCPTST = "FALSE"; +parameter RXCRCCLOCKDOUBLE = "FALSE"; +parameter RXCRCENABLE = "FALSE"; +parameter RXCRCINITVAL = 32'h00000000; +parameter RXCRCINVERTGEN = "FALSE"; +parameter RXCRCSAMECLOCK = "FALSE"; +parameter RXCTRL1 = 10'h200; +parameter RXCYCLE_LIMIT_SEL = 2'b00; +parameter RXDATA_SEL = 2'b00; +parameter RXDCCOUPLE = "FALSE"; +parameter RXDIGRESET = "FALSE"; +parameter RXDIGRX = "FALSE"; +parameter RXEQ = 64'h4000000000000000; +parameter RXFDCAL_CLOCK_DIVIDE = "NONE"; +parameter RXFDET_HYS_CAL = 3'b010; +parameter RXFDET_HYS_SEL = 3'b100; +parameter RXFDET_LCK_CAL = 3'b100; +parameter RXFDET_LCK_SEL = 3'b001; +parameter RXFECONTROL1 = 2'b00; +parameter RXFECONTROL2 = 3'b000; +parameter RXFETUNE = 2'b01; +parameter RXLB = "FALSE"; +parameter RXLKADJ = 5'b00000; +parameter RXLKAPD = "FALSE"; +parameter RXLOOPCAL_WAIT = 2'b00; +parameter RXLOOPFILT = 4'b0111; +parameter RXMODE = 6'b000000; +parameter RXPD = "FALSE"; +parameter RXPDDTST = "TRUE"; +parameter RXPMACLKSEL = "REFCLK1"; +parameter RXRCPADJ = 3'b011; +parameter RXRCPPD = "FALSE"; +parameter RXRECCLK1_USE_SYNC = "FALSE"; +parameter RXRIBADJ = 2'b11; +parameter RXRPDPD = "FALSE"; +parameter RXRSDPD = "FALSE"; +parameter RXSLOWDOWN_CAL = 2'b00; +parameter RXTUNE = 13'h0000; +parameter RXVCODAC_INIT = 10'b1010000000; +parameter RXVCO_CTRL_ENABLE = "FALSE"; +parameter RX_BUFFER_USE = "TRUE"; +parameter RX_CLOCK_DIVIDER = 2'b00; +parameter SAMPLE_8X = "FALSE"; +parameter SLOWDOWN_CAL = 2'b00; +parameter TXABPMACLKSEL = "REFCLK1"; +parameter TXAPD = "FALSE"; +parameter TXAREFBIASSEL = "TRUE"; +parameter TXASYNCDIVIDE = 2'b11; +parameter TXCLK0_FORCE_PMACLK = "FALSE"; +parameter TXCLKMODE = 4'b1001; +parameter TXCLMODE = 2'b00; +parameter TXCPSEL = "TRUE"; +parameter TXCRCCLOCKDOUBLE = "FALSE"; +parameter TXCRCENABLE = "FALSE"; +parameter TXCRCINITVAL = 32'h00000000; +parameter TXCRCINVERTGEN = "FALSE"; +parameter TXCRCSAMECLOCK = "FALSE"; +parameter TXCTRL1 = 10'h200; +parameter TXDATA_SEL = 2'b00; +parameter TXDAT_PRDRV_DAC = 3'b111; +parameter TXDAT_TAP_DAC = 5'b10110; +parameter TXDIGPD = "FALSE"; +parameter TXFDCAL_CLOCK_DIVIDE = "NONE"; +parameter TXHIGHSIGNALEN = "TRUE"; +parameter TXLOOPFILT = 4'b0111; +parameter TXLVLSHFTPD = "FALSE"; +parameter TXOUTCLK1_USE_SYNC = "FALSE"; +parameter TXPD = "FALSE"; +parameter TXPHASESEL = "FALSE"; +parameter TXPOST_PRDRV_DAC = 3'b111; +parameter TXPOST_TAP_DAC = 5'b01110; +parameter TXPOST_TAP_PD = "TRUE"; +parameter TXPRE_PRDRV_DAC = 3'b111; +parameter TXPRE_TAP_DAC = 5'b00000; +parameter TXPRE_TAP_PD = "TRUE"; +parameter TXSLEWRATE = "FALSE"; +parameter TXTERMTRIM = 4'b1100; +parameter TXTUNE = 13'h0000; +parameter TX_BUFFER_USE = "TRUE"; +parameter TX_CLOCK_DIVIDER = 2'b00; +parameter VCODAC_INIT = 10'b1010000000; +parameter VCO_CTRL_ENABLE = "FALSE"; +parameter VREFBIASMODE = 2'b11; +parameter integer ALIGN_COMMA_WORD = 4; +parameter integer CHAN_BOND_LIMIT = 16; +parameter integer CHAN_BOND_SEQ_LEN = 1; +parameter integer CLK_COR_MAX_LAT = 48; +parameter integer CLK_COR_MIN_LAT = 36; +parameter integer CLK_COR_SEQ_LEN = 1; +parameter integer RXOUTDIV2SEL = 1; +parameter integer RXPLLNDIVSEL = 8; +parameter integer RXUSRDIVISOR = 1; +parameter integer SH_CNT_MAX = 64; +parameter integer SH_INVALID_CNT_MAX = 16; +parameter integer TXOUTDIV2SEL = 1; +parameter integer TXPLLNDIVSEL = 8; + + +output DRDY; +output RXBUFERR; +output RXCALFAIL; +output RXCOMMADET; +output RXCYCLELIMIT; +output RXLOCK; +output RXMCLK; +output RXPCSHCLKOUT; +output RXREALIGN; +output RXRECCLK1; +output RXRECCLK2; +output RXSIGDET; +output TX1N; +output TX1P; +output TXBUFERR; +output TXCALFAIL; +output TXCYCLELIMIT; +output TXLOCK; +output TXOUTCLK1; +output TXOUTCLK2; +output TXPCSHCLKOUT; +output [15:0] COMBUSOUT; +output [15:0] DO; +output [1:0] RXLOSSOFSYNC; +output [31:0] RXCRCOUT; +output [31:0] TXCRCOUT; +output [4:0] CHBONDO; +output [5:0] RXSTATUS; +output [63:0] RXDATA; +output [7:0] RXCHARISCOMMA; +output [7:0] RXCHARISK; +output [7:0] RXDISPERR; +output [7:0] RXNOTINTABLE; +output [7:0] RXRUNDISP; +output [7:0] TXKERR; +output [7:0] TXRUNDISP; + +input DCLK; +input DEN; +input DWE; +input ENCHANSYNC; +input ENMCOMMAALIGN; +input ENPCOMMAALIGN; +input GREFCLK; +input POWERDOWN; +input REFCLK1; +input REFCLK2; +input RX1N; +input RX1P; +input RXBLOCKSYNC64B66BUSE; +input RXCLKSTABLE; +input RXCOMMADETUSE; +input RXCRCCLK; +input RXCRCDATAVALID; +input RXCRCINIT; +input RXCRCINTCLK; +input RXCRCPD; +input RXCRCRESET; +input RXDEC64B66BUSE; +input RXDEC8B10BUSE; +input RXDESCRAM64B66BUSE; +input RXIGNOREBTF; +input RXPMARESET; +input RXPOLARITY; +input RXRESET; +input RXSLIDE; +input RXSYNC; +input RXUSRCLK2; +input RXUSRCLK; +input TXCLKSTABLE; +input TXCRCCLK; +input TXCRCDATAVALID; +input TXCRCINIT; +input TXCRCINTCLK; +input TXCRCPD; +input TXCRCRESET; +input TXENC64B66BUSE; +input TXENC8B10BUSE; +input TXENOOB; +input TXGEARBOX64B66BUSE; +input TXINHIBIT; +input TXPMARESET; +input TXPOLARITY; +input TXRESET; +input TXSCRAM64B66BUSE; +input TXSYNC; +input TXUSRCLK2; +input TXUSRCLK; +input [15:0] COMBUSIN; +input [15:0] DI; +input [1:0] LOOPBACK; +input [1:0] RXDATAWIDTH; +input [1:0] RXINTDATAWIDTH; +input [1:0] TXDATAWIDTH; +input [1:0] TXINTDATAWIDTH; +input [2:0] RXCRCDATAWIDTH; +input [2:0] TXCRCDATAWIDTH; +input [4:0] CHBONDI; +input [63:0] RXCRCIN; +input [63:0] TXCRCIN; +input [63:0] TXDATA; +input [7:0] DADDR; +input [7:0] TXBYPASS8B10B; +input [7:0] TXCHARDISPMODE; +input [7:0] TXCHARDISPVAL; +input [7:0] TXCHARISK; + +reg BANDGAPSEL_BINARY; +reg BIASRESSEL_BINARY; +reg CCCB_ARBITRATOR_DISABLE_BINARY; +reg CHAN_BOND_ONE_SHOT_BINARY; +reg CHAN_BOND_SEQ_2_USE_BINARY; +reg CLK_CORRECT_USE_BINARY; +reg CLK_COR_8B10B_DE_BINARY; +reg CLK_COR_SEQ_2_USE_BINARY; +reg CLK_COR_SEQ_DROP_BINARY; +reg COMMA32_BINARY; +reg DEC_MCOMMA_DETECT_BINARY; +reg DEC_PCOMMA_DETECT_BINARY; +reg DEC_VALID_COMMA_ONLY_BINARY; +reg DIGRX_SYNC_MODE_BINARY; +reg ENABLE_DCDR_BINARY; +reg MCOMMA_DETECT_BINARY; +reg OPPOSITE_SELECT_BINARY; +reg PCOMMA_DETECT_BINARY; +reg PCS_BIT_SLIP_BINARY; +reg PMACLKENABLE_BINARY; +reg PMACOREPWRENABLE_BINARY; +reg PMA_BIT_SLIP_BINARY; +reg POWER_ENABLE_BINARY; +reg REPEATER_BINARY; +reg RXACTST_BINARY; +reg RXAFEPD_BINARY; +reg RXAFETST_BINARY; +reg RXAPD_BINARY; +reg RXBY_32_BINARY; +reg RXCLK0_FORCE_PMACLK_BINARY; +reg RXCPSEL_BINARY; +reg RXCPTST_BINARY; +reg RXCRCCLOCKDOUBLE_BINARY; +reg RXCRCENABLE_BINARY; +reg RXCRCINVERTGEN_BINARY; +reg RXCRCSAMECLOCK_BINARY; +reg RXDCCOUPLE_BINARY; +reg RXDIGRESET_BINARY; +reg RXDIGRX_BINARY; +reg RXLB_BINARY; +reg RXLKAPD_BINARY; +reg RXPDDTST_BINARY; +reg RXPD_BINARY; +reg RXRCPPD_BINARY; +reg RXRECCLK1_USE_SYNC_BINARY; +reg RXRPDPD_BINARY; +reg RXRSDPD_BINARY; +reg RXVCO_CTRL_ENABLE_BINARY; +reg RX_BUFFER_USE_BINARY; +reg SAMPLE_8X_BINARY; +reg TXAPD_BINARY; +reg TXAREFBIASSEL_BINARY; +reg TXCLK0_FORCE_PMACLK_BINARY; +reg TXCPSEL_BINARY; +reg TXCRCCLOCKDOUBLE_BINARY; +reg TXCRCENABLE_BINARY; +reg TXCRCINVERTGEN_BINARY; +reg TXCRCSAMECLOCK_BINARY; +reg TXDIGPD_BINARY; +reg TXHIGHSIGNALEN_BINARY; +reg TXLVLSHFTPD_BINARY; +reg TXOUTCLK1_USE_SYNC_BINARY; +reg TXPD_BINARY; +reg TXPHASESEL_BINARY; +reg TXPOST_TAP_PD_BINARY; +reg TXPRE_TAP_PD_BINARY; +reg TXSLEWRATE_BINARY; +reg TX_BUFFER_USE_BINARY; +reg VCO_CTRL_ENABLE_BINARY; +reg [1:0] GT11_MODE_BINARY; +reg [12:0] RXTUNE_BINARY; +reg [12:0] TXTUNE_BINARY; +reg [1:0] ALIGN_COMMA_WORD_BINARY; +reg [1:0] CHAN_BOND_MODE_BINARY; +reg [1:0] RXFDCAL_CLOCK_DIVIDE_BINARY; +reg [1:0] RXPMACLKSEL_BINARY; +reg [1:0] TXABPMACLKSEL_BINARY; +reg [1:0] TXFDCAL_CLOCK_DIVIDE_BINARY; +reg [2:0] CHAN_BOND_SEQ_LEN_BINARY; +reg [2:0] CLK_COR_SEQ_LEN_BINARY; +reg [31:0] MCOMMA_32B_VALUE_BINARY; +reg [31:0] PCOMMA_32B_VALUE_BINARY; +reg [31:0] RXCRCINITVAL_BINARY; +reg [31:0] TXCRCINITVAL_BINARY; +reg [3:0] RXPLLNDIVSEL_BINARY; +reg [3:0] TXOUTDIV2SEL_BINARY; +reg [3:0] TXPLLNDIVSEL_BINARY; +reg [4:0] RXUSRDIVISOR_BINARY; +reg [5:0] CHAN_BOND_LIMIT_BINARY; +reg [5:0] CLK_COR_MAX_LAT_BINARY; +reg [5:0] CLK_COR_MIN_LAT_BINARY; +reg [63:0] RXEQ_BINARY; +reg [7:0] RXOUTDIV2SEL_BINARY; +reg [7:0] SH_CNT_MAX_BINARY; +reg [7:0] SH_INVALID_CNT_MAX_BINARY; +reg [9:0] COMMA_10B_MASK_BINARY; +reg [9:0] RXCTRL1_BINARY; +reg [9:0] TXCTRL1_BINARY; + +tri0 GSR = glbl.GSR; + +reg notifier; + +wire DCLK_IN; +wire DEN_IN; +wire DRDY_OUT; +wire DWE_IN; +wire ENCHANSYNC_IN; +wire ENMCOMMAALIGN_IN; +wire ENPCOMMAALIGN_IN; +wire GREFCLK_IN; +wire POWERDOWN_IN; +wire REFCLK1_IN; +wire REFCLK2_IN; +wire RX1N_IN; +wire RX1P_IN; +wire RXBLOCKSYNC64B66BUSE_IN; +wire RXBUFERR_OUT; +wire RXCALFAIL_OUT; +wire RXCLKSTABLE_IN; +wire RXCOMMADETUSE_IN; +wire RXCOMMADET_OUT; +wire RXCRCCLK_IN; +wire RXCRCDATAVALID_IN; +wire RXCRCINIT_IN; +wire RXCRCINTCLK_IN; +wire RXCRCPD_IN; +wire RXCRCRESET_IN; +wire RXCYCLELIMIT_OUT; +wire RXDEC64B66BUSE_IN; +wire RXDEC8B10BUSE_IN; +wire RXDESCRAM64B66BUSE_IN; +wire RXIGNOREBTF_IN; +wire RXLOCK_OUT; +wire RXMCLK_OUT; +wire RXPCSHCLKOUT_OUT; +wire RXPMARESET_IN; +wire RXPOLARITY_IN; +wire RXREALIGN_OUT; +wire RXRECCLK1_OUT; +wire RXRECCLK2_OUT; +wire RXRESET_IN; +wire RXSIGDET_OUT; +wire RXSLIDE_IN; +wire RXSYNC_IN; +wire RXUSRCLK2_IN; +wire RXUSRCLK_IN; +wire TX1N_OUT; +wire TX1P_OUT; +wire TXBUFERR_OUT; +wire TXCALFAIL_OUT; +wire TXCLKSTABLE_IN; +wire TXCRCCLK_IN; +wire TXCRCDATAVALID_IN; +wire TXCRCINIT_IN; +wire TXCRCINTCLK_IN; +wire TXCRCPD_IN; +wire TXCRCRESET_IN; +wire TXCYCLELIMIT_OUT; +wire TXENC64B66BUSE_IN; +wire TXENC8B10BUSE_IN; +wire TXENOOB_IN; +wire TXGEARBOX64B66BUSE_IN; +wire TXINHIBIT_IN; +wire TXLOCK_OUT; +wire TXOUTCLK1_OUT; +wire TXOUTCLK2_OUT; +wire TXPCSHCLKOUT_OUT; +wire TXPMARESET_IN; +wire TXPOLARITY_IN; +wire TXRESET_IN; +wire TXSCRAM64B66BUSE_IN; +wire TXSYNC_IN; +wire TXUSRCLK2_IN; +wire TXUSRCLK_IN; +wire [15:0] COMBUSIN_IN; +wire [15:0] COMBUSOUT_OUT; +wire [15:0] DI_IN; +wire [15:0] DO_OUT; +wire [1:0] LOOPBACK_IN; +wire [1:0] RXDATAWIDTH_IN; +wire [1:0] RXINTDATAWIDTH_IN; +wire [1:0] RXLOSSOFSYNC_OUT; +wire [1:0] TXDATAWIDTH_IN; +wire [1:0] TXINTDATAWIDTH_IN; +wire [2:0] RXCRCDATAWIDTH_IN; +wire [2:0] TXCRCDATAWIDTH_IN; +wire [31:0] RXCRCOUT_OUT; +wire [31:0] TXCRCOUT_OUT; +wire [4:0] CHBONDI_IN; +wire [4:0] CHBONDO_OUT; +wire [5:0] RXSTATUS_OUT; +wire [63:0] RXCRCIN_IN; +wire [63:0] RXDATA_OUT; +wire [63:0] TXCRCIN_IN; +wire [63:0] TXDATA_IN; +wire [7:0] DADDR_IN; +wire [7:0] RXCHARISCOMMA_OUT; +wire [7:0] RXCHARISK_OUT; +wire [7:0] RXDISPERR_OUT; +wire [7:0] RXNOTINTABLE_OUT; +wire [7:0] RXRUNDISP_OUT; +wire [7:0] TXBYPASS8B10B_IN; +wire [7:0] TXCHARDISPMODE_IN; +wire [7:0] TXCHARDISPVAL_IN; +wire [7:0] TXCHARISK_IN; +wire [7:0] TXKERR_OUT; +wire [7:0] TXRUNDISP_OUT; + +initial begin + case (GT11_MODE) + "B" : GT11_MODE_BINARY <= 2'b00; + "A" : GT11_MODE_BINARY <= 2'b01; + "DONT_CARE" : GT11_MODE_BINARY <= 2'b10; + "SINGLE" : GT11_MODE_BINARY <= 2'b11; + default : begin + $display("Attribute Syntax Error : The Attribute GT11_MODE on GT11 instance %m is set to %s. Legal values for this attribute are DONT_CARE, A, B or SINGLE.", GT11_MODE); + $finish; + end + endcase + + case (CHAN_BOND_LIMIT) + 0 : CHAN_BOND_LIMIT_BINARY <= 6'b000000; + 1 : CHAN_BOND_LIMIT_BINARY <= 6'b000001; + 2 : CHAN_BOND_LIMIT_BINARY <= 6'b000010; + 3 : CHAN_BOND_LIMIT_BINARY <= 6'b000011; + 4 : CHAN_BOND_LIMIT_BINARY <= 6'b000100; + 5 : CHAN_BOND_LIMIT_BINARY <= 6'b000101; + 6 : CHAN_BOND_LIMIT_BINARY <= 6'b000110; + 7 : CHAN_BOND_LIMIT_BINARY <= 6'b000111; + 8 : CHAN_BOND_LIMIT_BINARY <= 6'b001000; + 9 : CHAN_BOND_LIMIT_BINARY <= 6'b001001; + 10 : CHAN_BOND_LIMIT_BINARY <= 6'b001010; + 11 : CHAN_BOND_LIMIT_BINARY <= 6'b001011; + 12 : CHAN_BOND_LIMIT_BINARY <= 6'b001100; + 13 : CHAN_BOND_LIMIT_BINARY <= 6'b001101; + 14 : CHAN_BOND_LIMIT_BINARY <= 6'b001110; + 15 : CHAN_BOND_LIMIT_BINARY <= 6'b001111; + 16 : CHAN_BOND_LIMIT_BINARY <= 6'b010000; + 17 : CHAN_BOND_LIMIT_BINARY <= 6'b010001; + 18 : CHAN_BOND_LIMIT_BINARY <= 6'b010010; + 19 : CHAN_BOND_LIMIT_BINARY <= 6'b010011; + 20 : CHAN_BOND_LIMIT_BINARY <= 6'b010100; + 21 : CHAN_BOND_LIMIT_BINARY <= 6'b010101; + 22 : CHAN_BOND_LIMIT_BINARY <= 6'b010110; + 23 : CHAN_BOND_LIMIT_BINARY <= 6'b010111; + 24 : CHAN_BOND_LIMIT_BINARY <= 6'b011000; + 25 : CHAN_BOND_LIMIT_BINARY <= 6'b011001; + 26 : CHAN_BOND_LIMIT_BINARY <= 6'b011010; + 27 : CHAN_BOND_LIMIT_BINARY <= 6'b011011; + 28 : CHAN_BOND_LIMIT_BINARY <= 6'b011100; + 29 : CHAN_BOND_LIMIT_BINARY <= 6'b011101; + 30 : CHAN_BOND_LIMIT_BINARY <= 6'b011110; + 31 : CHAN_BOND_LIMIT_BINARY <= 6'b011111; + default : begin + $display("Attribute Syntax Error : The Attribute CHAN_BOND_LIMIT on GT11 instance %m is set to %d. Legal values for this attribute are 0 to 31.", CHAN_BOND_LIMIT); + $finish; + end + endcase + + case (CHAN_BOND_MODE) + "NONE" : CHAN_BOND_MODE_BINARY <= 2'b00; + "MASTER" : CHAN_BOND_MODE_BINARY <= 2'b01; + "SLAVE_1_HOP" : CHAN_BOND_MODE_BINARY <= 2'b10; + "SLAVE_2_HOPS" : CHAN_BOND_MODE_BINARY <= 2'b11; + default : begin + $display("Attribute Syntax Error : The Attribute CHAN_BOND_MODE on GT11 instance %m is set to %s. Legal values for this attribute are NONE, MASTER, SLAVE_1_HOP or SLAVE_2_HOPS.", CHAN_BOND_MODE); + $finish; + end + endcase + + case (CHAN_BOND_ONE_SHOT) + "FALSE" : CHAN_BOND_ONE_SHOT_BINARY <= 0; + "TRUE" : CHAN_BOND_ONE_SHOT_BINARY <= 1; + default : begin + $display("Attribute Syntax Error : The Attribute CHAN_BOND_ONE_SHOT on GT11 instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", CHAN_BOND_ONE_SHOT); + $finish; + end + endcase + + case (CHAN_BOND_SEQ_2_USE) + "FALSE" : CHAN_BOND_SEQ_2_USE_BINARY <= 0; + "TRUE" : CHAN_BOND_SEQ_2_USE_BINARY <= 1; + default : begin + $display("Attribute Syntax Error : The Attribute CHAN_BOND_SEQ_2_USE on GT11 instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", CHAN_BOND_SEQ_2_USE); + $finish; + end + endcase + + case (CHAN_BOND_SEQ_LEN) + 1 : CHAN_BOND_SEQ_LEN_BINARY <= 3'b000; + 2 : CHAN_BOND_SEQ_LEN_BINARY <= 3'b001; + 3 : CHAN_BOND_SEQ_LEN_BINARY <= 3'b010; + 4 : CHAN_BOND_SEQ_LEN_BINARY <= 3'b011; + 8 : CHAN_BOND_SEQ_LEN_BINARY <= 3'b111; + default : begin + $display("Attribute Syntax Error : The Attribute CHAN_BOND_SEQ_LEN on GT11 instance %m is set to %d. Legal values for this attribute are 1, 2, 3, 4 or 8.", CHAN_BOND_SEQ_LEN); + $finish; + end + endcase + + case (RX_BUFFER_USE) + "FALSE" : RX_BUFFER_USE_BINARY <= 0; + "TRUE" : RX_BUFFER_USE_BINARY <= 1; + default : begin + $display("Attribute Syntax Error : The Attribute RX_BUFFER_USE on GT11 instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", RX_BUFFER_USE); + $finish; + end + endcase + + case (TX_BUFFER_USE) + "FALSE" : TX_BUFFER_USE_BINARY <= 0; + "TRUE" : TX_BUFFER_USE_BINARY <= 1; + default : begin + $display("Attribute Syntax Error : The Attribute TX_BUFFER_USE on GT11 instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", TX_BUFFER_USE); + $finish; + end + endcase + + case (POWER_ENABLE) + "FALSE" : POWER_ENABLE_BINARY <= 0; + "TRUE" : POWER_ENABLE_BINARY <= 1; + default : begin + $display("Attribute Syntax Error : The Attribute POWER_ENABLE on GT11 instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", POWER_ENABLE); + $finish; + end + endcase + + case (OPPOSITE_SELECT) + "FALSE" : OPPOSITE_SELECT_BINARY <= 0; + "TRUE" : OPPOSITE_SELECT_BINARY <= 1; + default : begin + $display("Attribute Syntax Error : The Attribute OPPOSITE_SELECT on GT11 instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", OPPOSITE_SELECT); + $finish; + end + endcase + + case (CCCB_ARBITRATOR_DISABLE) + "FALSE" : CCCB_ARBITRATOR_DISABLE_BINARY <= 0; + "TRUE" : CCCB_ARBITRATOR_DISABLE_BINARY <= 1; + default : begin + $display("Attribute Syntax Error : The Attribute CCCB_ARBITRATOR_DISABLE on GT11 instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", CCCB_ARBITRATOR_DISABLE); + $finish; + end + endcase + + case (DIGRX_SYNC_MODE) + "FALSE" : DIGRX_SYNC_MODE_BINARY <= 0; + "TRUE" : DIGRX_SYNC_MODE_BINARY <= 1; + default : begin + $display("Attribute Syntax Error : The Attribute DIGRX_SYNC_MODE on GT11 instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", DIGRX_SYNC_MODE); + $finish; + end + endcase + + case (PCS_BIT_SLIP) + "FALSE" : PCS_BIT_SLIP_BINARY <= 0; + "TRUE" : PCS_BIT_SLIP_BINARY <= 1; + default : begin + $display("Attribute Syntax Error : The Attribute PCS_BIT_SLIP on GT11 instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", PCS_BIT_SLIP); + $finish; + end + endcase + + case (CLK_COR_MIN_LAT) + 0 : CLK_COR_MIN_LAT_BINARY <= 6'b000000; + 1 : CLK_COR_MIN_LAT_BINARY <= 6'b000001; + 2 : CLK_COR_MIN_LAT_BINARY <= 6'b000010; + 3 : CLK_COR_MIN_LAT_BINARY <= 6'b000011; + 4 : CLK_COR_MIN_LAT_BINARY <= 6'b000100; + 5 : CLK_COR_MIN_LAT_BINARY <= 6'b000101; + 6 : CLK_COR_MIN_LAT_BINARY <= 6'b000110; + 7 : CLK_COR_MIN_LAT_BINARY <= 6'b000111; + 8 : CLK_COR_MIN_LAT_BINARY <= 6'b001000; + 9 : CLK_COR_MIN_LAT_BINARY <= 6'b001001; + 10 : CLK_COR_MIN_LAT_BINARY <= 6'b001010; + 11 : CLK_COR_MIN_LAT_BINARY <= 6'b001011; + 12 : CLK_COR_MIN_LAT_BINARY <= 6'b001100; + 13 : CLK_COR_MIN_LAT_BINARY <= 6'b001101; + 14 : CLK_COR_MIN_LAT_BINARY <= 6'b001110; + 15 : CLK_COR_MIN_LAT_BINARY <= 6'b001111; + 16 : CLK_COR_MIN_LAT_BINARY <= 6'b010000; + 17 : CLK_COR_MIN_LAT_BINARY <= 6'b010001; + 18 : CLK_COR_MIN_LAT_BINARY <= 6'b010010; + 19 : CLK_COR_MIN_LAT_BINARY <= 6'b010011; + 20 : CLK_COR_MIN_LAT_BINARY <= 6'b010100; + 21 : CLK_COR_MIN_LAT_BINARY <= 6'b010101; + 22 : CLK_COR_MIN_LAT_BINARY <= 6'b010110; + 23 : CLK_COR_MIN_LAT_BINARY <= 6'b010111; + 24 : CLK_COR_MIN_LAT_BINARY <= 6'b011000; + 25 : CLK_COR_MIN_LAT_BINARY <= 6'b011001; + 26 : CLK_COR_MIN_LAT_BINARY <= 6'b011010; + 27 : CLK_COR_MIN_LAT_BINARY <= 6'b011011; + 28 : CLK_COR_MIN_LAT_BINARY <= 6'b011100; + 29 : CLK_COR_MIN_LAT_BINARY <= 6'b011101; + 30 : CLK_COR_MIN_LAT_BINARY <= 6'b011110; + 31 : CLK_COR_MIN_LAT_BINARY <= 6'b011111; + 32 : CLK_COR_MIN_LAT_BINARY <= 6'b100000; + 33 : CLK_COR_MIN_LAT_BINARY <= 6'b100001; + 34 : CLK_COR_MIN_LAT_BINARY <= 6'b100010; + 35 : CLK_COR_MIN_LAT_BINARY <= 6'b100011; + 36 : CLK_COR_MIN_LAT_BINARY <= 6'b100100; + 37 : CLK_COR_MIN_LAT_BINARY <= 6'b100101; + 38 : CLK_COR_MIN_LAT_BINARY <= 6'b100110; + 39 : CLK_COR_MIN_LAT_BINARY <= 6'b100111; + 40 : CLK_COR_MIN_LAT_BINARY <= 6'b101000; + 41 : CLK_COR_MIN_LAT_BINARY <= 6'b101001; + 42 : CLK_COR_MIN_LAT_BINARY <= 6'b101010; + 43 : CLK_COR_MIN_LAT_BINARY <= 6'b101011; + 44 : CLK_COR_MIN_LAT_BINARY <= 6'b101100; + 45 : CLK_COR_MIN_LAT_BINARY <= 6'b101101; + 46 : CLK_COR_MIN_LAT_BINARY <= 6'b101110; + 47 : CLK_COR_MIN_LAT_BINARY <= 6'b101111; + 48 : CLK_COR_MIN_LAT_BINARY <= 6'b110000; + 49 : CLK_COR_MIN_LAT_BINARY <= 6'b110001; + 50 : CLK_COR_MIN_LAT_BINARY <= 6'b110010; + 51 : CLK_COR_MIN_LAT_BINARY <= 6'b110011; + 52 : CLK_COR_MIN_LAT_BINARY <= 6'b110100; + 53 : CLK_COR_MIN_LAT_BINARY <= 6'b110101; + 54 : CLK_COR_MIN_LAT_BINARY <= 6'b110110; + 55 : CLK_COR_MIN_LAT_BINARY <= 6'b110111; + 56 : CLK_COR_MIN_LAT_BINARY <= 6'b111000; + 57 : CLK_COR_MIN_LAT_BINARY <= 6'b111001; + 58 : CLK_COR_MIN_LAT_BINARY <= 6'b111010; + 59 : CLK_COR_MIN_LAT_BINARY <= 6'b111011; + 60 : CLK_COR_MIN_LAT_BINARY <= 6'b111100; + 61 : CLK_COR_MIN_LAT_BINARY <= 6'b111101; + 62 : CLK_COR_MIN_LAT_BINARY <= 6'b111110; + 63 : CLK_COR_MIN_LAT_BINARY <= 6'b111111; + default : begin + $display("Attribute Syntax Error : The Attribute CLK_COR_MIN_LAT on GT11 instance %m is set to %d. Legal values for this attribute are 0 to 63.", CLK_COR_MIN_LAT); + $finish; + end + endcase + + case (CLK_COR_MAX_LAT) + 0 : CLK_COR_MAX_LAT_BINARY <= 6'b000000; + 1 : CLK_COR_MAX_LAT_BINARY <= 6'b000001; + 2 : CLK_COR_MAX_LAT_BINARY <= 6'b000010; + 3 : CLK_COR_MAX_LAT_BINARY <= 6'b000011; + 4 : CLK_COR_MAX_LAT_BINARY <= 6'b000100; + 5 : CLK_COR_MAX_LAT_BINARY <= 6'b000101; + 6 : CLK_COR_MAX_LAT_BINARY <= 6'b000110; + 7 : CLK_COR_MAX_LAT_BINARY <= 6'b000111; + 8 : CLK_COR_MAX_LAT_BINARY <= 6'b001000; + 9 : CLK_COR_MAX_LAT_BINARY <= 6'b001001; + 10 : CLK_COR_MAX_LAT_BINARY <= 6'b001010; + 11 : CLK_COR_MAX_LAT_BINARY <= 6'b001011; + 12 : CLK_COR_MAX_LAT_BINARY <= 6'b001100; + 13 : CLK_COR_MAX_LAT_BINARY <= 6'b001101; + 14 : CLK_COR_MAX_LAT_BINARY <= 6'b001110; + 15 : CLK_COR_MAX_LAT_BINARY <= 6'b001111; + 16 : CLK_COR_MAX_LAT_BINARY <= 6'b010000; + 17 : CLK_COR_MAX_LAT_BINARY <= 6'b010001; + 18 : CLK_COR_MAX_LAT_BINARY <= 6'b010010; + 19 : CLK_COR_MAX_LAT_BINARY <= 6'b010011; + 20 : CLK_COR_MAX_LAT_BINARY <= 6'b010100; + 21 : CLK_COR_MAX_LAT_BINARY <= 6'b010101; + 22 : CLK_COR_MAX_LAT_BINARY <= 6'b010110; + 23 : CLK_COR_MAX_LAT_BINARY <= 6'b010111; + 24 : CLK_COR_MAX_LAT_BINARY <= 6'b011000; + 25 : CLK_COR_MAX_LAT_BINARY <= 6'b011001; + 26 : CLK_COR_MAX_LAT_BINARY <= 6'b011010; + 27 : CLK_COR_MAX_LAT_BINARY <= 6'b011011; + 28 : CLK_COR_MAX_LAT_BINARY <= 6'b011100; + 29 : CLK_COR_MAX_LAT_BINARY <= 6'b011101; + 30 : CLK_COR_MAX_LAT_BINARY <= 6'b011110; + 31 : CLK_COR_MAX_LAT_BINARY <= 6'b011111; + 32 : CLK_COR_MAX_LAT_BINARY <= 6'b100000; + 33 : CLK_COR_MAX_LAT_BINARY <= 6'b100001; + 34 : CLK_COR_MAX_LAT_BINARY <= 6'b100010; + 35 : CLK_COR_MAX_LAT_BINARY <= 6'b100011; + 36 : CLK_COR_MAX_LAT_BINARY <= 6'b100100; + 37 : CLK_COR_MAX_LAT_BINARY <= 6'b100101; + 38 : CLK_COR_MAX_LAT_BINARY <= 6'b100110; + 39 : CLK_COR_MAX_LAT_BINARY <= 6'b100111; + 40 : CLK_COR_MAX_LAT_BINARY <= 6'b101000; + 41 : CLK_COR_MAX_LAT_BINARY <= 6'b101001; + 42 : CLK_COR_MAX_LAT_BINARY <= 6'b101010; + 43 : CLK_COR_MAX_LAT_BINARY <= 6'b101011; + 44 : CLK_COR_MAX_LAT_BINARY <= 6'b101100; + 45 : CLK_COR_MAX_LAT_BINARY <= 6'b101101; + 46 : CLK_COR_MAX_LAT_BINARY <= 6'b101110; + 47 : CLK_COR_MAX_LAT_BINARY <= 6'b101111; + 48 : CLK_COR_MAX_LAT_BINARY <= 6'b110000; + 49 : CLK_COR_MAX_LAT_BINARY <= 6'b110001; + 50 : CLK_COR_MAX_LAT_BINARY <= 6'b110010; + 51 : CLK_COR_MAX_LAT_BINARY <= 6'b110011; + 52 : CLK_COR_MAX_LAT_BINARY <= 6'b110100; + 53 : CLK_COR_MAX_LAT_BINARY <= 6'b110101; + 54 : CLK_COR_MAX_LAT_BINARY <= 6'b110110; + 55 : CLK_COR_MAX_LAT_BINARY <= 6'b110111; + 56 : CLK_COR_MAX_LAT_BINARY <= 6'b111000; + 57 : CLK_COR_MAX_LAT_BINARY <= 6'b111001; + 58 : CLK_COR_MAX_LAT_BINARY <= 6'b111010; + 59 : CLK_COR_MAX_LAT_BINARY <= 6'b111011; + 60 : CLK_COR_MAX_LAT_BINARY <= 6'b111100; + 61 : CLK_COR_MAX_LAT_BINARY <= 6'b111101; + 62 : CLK_COR_MAX_LAT_BINARY <= 6'b111110; + 63 : CLK_COR_MAX_LAT_BINARY <= 6'b111111; + default : begin + $display("Attribute Syntax Error : The Attribute CLK_COR_MAX_LAT on GT11 instance %m is set to %d. Legal values for this attribute are 0 to 63.", CLK_COR_MAX_LAT); + $finish; + end + endcase + + case (CLK_COR_SEQ_2_USE) + "FALSE" : CLK_COR_SEQ_2_USE_BINARY <= 0; + "TRUE" : CLK_COR_SEQ_2_USE_BINARY <= 1; + default : begin + $display("Attribute Syntax Error : The Attribute CLK_COR_SEQ_2_USE on GT11 instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", CLK_COR_SEQ_2_USE); + $finish; + end + endcase + + case (CLK_COR_SEQ_DROP) + "FALSE" : CLK_COR_SEQ_DROP_BINARY <= 0; + "TRUE" : CLK_COR_SEQ_DROP_BINARY <= 1; + default : begin + $display("Attribute Syntax Error : The Attribute CLK_COR_SEQ_DROP on GT11 instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", CLK_COR_SEQ_DROP); + $finish; + end + endcase + + case (CLK_COR_SEQ_LEN) + 1 : CLK_COR_SEQ_LEN_BINARY <= 3'b000; + 2 : CLK_COR_SEQ_LEN_BINARY <= 3'b001; + 3 : CLK_COR_SEQ_LEN_BINARY <= 3'b010; + 4 : CLK_COR_SEQ_LEN_BINARY <= 3'b011; + 8 : CLK_COR_SEQ_LEN_BINARY <= 3'b111; + default : begin + $display("Attribute Syntax Error : The Attribute CLK_COR_SEQ_LEN on GT11 instance %m is set to %d. Legal values for this attribute are 1, 2, 3, 4 or 8.", CLK_COR_SEQ_LEN); + $finish; + end + endcase + + case (CLK_CORRECT_USE) + "FALSE" : CLK_CORRECT_USE_BINARY <= 0; + "TRUE" : CLK_CORRECT_USE_BINARY <= 1; + default : begin + $display("Attribute Syntax Error : The Attribute CLK_CORRECT_USE on GT11 instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", CLK_CORRECT_USE); + $finish; + end + endcase + + case (CLK_COR_8B10B_DE) + "FALSE" : CLK_COR_8B10B_DE_BINARY <= 0; + "TRUE" : CLK_COR_8B10B_DE_BINARY <= 1; + default : begin + $display("Attribute Syntax Error : The Attribute CLK_COR_8B10B_DE on GT11 instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", CLK_COR_8B10B_DE); + $finish; + end + endcase + + case (SH_CNT_MAX) + 0 : SH_CNT_MAX_BINARY <= 8'b00000000; + 1 : SH_CNT_MAX_BINARY <= 8'b00000001; + 2 : SH_CNT_MAX_BINARY <= 8'b00000010; + 3 : SH_CNT_MAX_BINARY <= 8'b00000011; + 4 : SH_CNT_MAX_BINARY <= 8'b00000100; + 5 : SH_CNT_MAX_BINARY <= 8'b00000101; + 6 : SH_CNT_MAX_BINARY <= 8'b00000110; + 7 : SH_CNT_MAX_BINARY <= 8'b00000111; + 8 : SH_CNT_MAX_BINARY <= 8'b00001000; + 9 : SH_CNT_MAX_BINARY <= 8'b00001001; + 10 : SH_CNT_MAX_BINARY <= 8'b00001010; + 11 : SH_CNT_MAX_BINARY <= 8'b00001011; + 12 : SH_CNT_MAX_BINARY <= 8'b00001100; + 13 : SH_CNT_MAX_BINARY <= 8'b00001101; + 14 : SH_CNT_MAX_BINARY <= 8'b00001110; + 15 : SH_CNT_MAX_BINARY <= 8'b00001111; + 16 : SH_CNT_MAX_BINARY <= 8'b00010000; + 17 : SH_CNT_MAX_BINARY <= 8'b00010001; + 18 : SH_CNT_MAX_BINARY <= 8'b00010010; + 19 : SH_CNT_MAX_BINARY <= 8'b00010011; + 20 : SH_CNT_MAX_BINARY <= 8'b00010100; + 21 : SH_CNT_MAX_BINARY <= 8'b00010101; + 22 : SH_CNT_MAX_BINARY <= 8'b00010110; + 23 : SH_CNT_MAX_BINARY <= 8'b00010111; + 24 : SH_CNT_MAX_BINARY <= 8'b00011000; + 25 : SH_CNT_MAX_BINARY <= 8'b00011001; + 26 : SH_CNT_MAX_BINARY <= 8'b00011010; + 27 : SH_CNT_MAX_BINARY <= 8'b00011011; + 28 : SH_CNT_MAX_BINARY <= 8'b00011100; + 29 : SH_CNT_MAX_BINARY <= 8'b00011101; + 30 : SH_CNT_MAX_BINARY <= 8'b00011110; + 31 : SH_CNT_MAX_BINARY <= 8'b00011111; + 32 : SH_CNT_MAX_BINARY <= 8'b00100000; + 33 : SH_CNT_MAX_BINARY <= 8'b00100001; + 34 : SH_CNT_MAX_BINARY <= 8'b00100010; + 35 : SH_CNT_MAX_BINARY <= 8'b00100011; + 36 : SH_CNT_MAX_BINARY <= 8'b00100100; + 37 : SH_CNT_MAX_BINARY <= 8'b00100101; + 38 : SH_CNT_MAX_BINARY <= 8'b00100110; + 39 : SH_CNT_MAX_BINARY <= 8'b00100111; + 40 : SH_CNT_MAX_BINARY <= 8'b00101000; + 41 : SH_CNT_MAX_BINARY <= 8'b00101001; + 42 : SH_CNT_MAX_BINARY <= 8'b00101010; + 43 : SH_CNT_MAX_BINARY <= 8'b00101011; + 44 : SH_CNT_MAX_BINARY <= 8'b00101100; + 45 : SH_CNT_MAX_BINARY <= 8'b00101101; + 46 : SH_CNT_MAX_BINARY <= 8'b00101110; + 47 : SH_CNT_MAX_BINARY <= 8'b00101111; + 48 : SH_CNT_MAX_BINARY <= 8'b00110000; + 49 : SH_CNT_MAX_BINARY <= 8'b00110001; + 50 : SH_CNT_MAX_BINARY <= 8'b00110010; + 51 : SH_CNT_MAX_BINARY <= 8'b00110011; + 52 : SH_CNT_MAX_BINARY <= 8'b00110100; + 53 : SH_CNT_MAX_BINARY <= 8'b00110101; + 54 : SH_CNT_MAX_BINARY <= 8'b00110110; + 55 : SH_CNT_MAX_BINARY <= 8'b00110111; + 56 : SH_CNT_MAX_BINARY <= 8'b00111000; + 57 : SH_CNT_MAX_BINARY <= 8'b00111001; + 58 : SH_CNT_MAX_BINARY <= 8'b00111010; + 59 : SH_CNT_MAX_BINARY <= 8'b00111011; + 60 : SH_CNT_MAX_BINARY <= 8'b00111100; + 61 : SH_CNT_MAX_BINARY <= 8'b00111101; + 62 : SH_CNT_MAX_BINARY <= 8'b00111110; + 63 : SH_CNT_MAX_BINARY <= 8'b00111111; + 64 : SH_CNT_MAX_BINARY <= 8'b01000000; + 65 : SH_CNT_MAX_BINARY <= 8'b01000001; + 66 : SH_CNT_MAX_BINARY <= 8'b01000010; + 67 : SH_CNT_MAX_BINARY <= 8'b01000011; + 68 : SH_CNT_MAX_BINARY <= 8'b01000100; + 69 : SH_CNT_MAX_BINARY <= 8'b01000101; + 70 : SH_CNT_MAX_BINARY <= 8'b01000110; + 71 : SH_CNT_MAX_BINARY <= 8'b01000111; + 72 : SH_CNT_MAX_BINARY <= 8'b01001000; + 73 : SH_CNT_MAX_BINARY <= 8'b01001001; + 74 : SH_CNT_MAX_BINARY <= 8'b01001010; + 75 : SH_CNT_MAX_BINARY <= 8'b01001011; + 76 : SH_CNT_MAX_BINARY <= 8'b01001100; + 77 : SH_CNT_MAX_BINARY <= 8'b01001101; + 78 : SH_CNT_MAX_BINARY <= 8'b01001110; + 79 : SH_CNT_MAX_BINARY <= 8'b01001111; + 80 : SH_CNT_MAX_BINARY <= 8'b01010000; + 81 : SH_CNT_MAX_BINARY <= 8'b01010001; + 82 : SH_CNT_MAX_BINARY <= 8'b01010010; + 83 : SH_CNT_MAX_BINARY <= 8'b01010011; + 84 : SH_CNT_MAX_BINARY <= 8'b01010100; + 85 : SH_CNT_MAX_BINARY <= 8'b01010101; + 86 : SH_CNT_MAX_BINARY <= 8'b01010110; + 87 : SH_CNT_MAX_BINARY <= 8'b01010111; + 88 : SH_CNT_MAX_BINARY <= 8'b01011000; + 89 : SH_CNT_MAX_BINARY <= 8'b01011001; + 90 : SH_CNT_MAX_BINARY <= 8'b01011010; + 91 : SH_CNT_MAX_BINARY <= 8'b01011011; + 92 : SH_CNT_MAX_BINARY <= 8'b01011100; + 93 : SH_CNT_MAX_BINARY <= 8'b01011101; + 94 : SH_CNT_MAX_BINARY <= 8'b01011110; + 95 : SH_CNT_MAX_BINARY <= 8'b01011111; + 96 : SH_CNT_MAX_BINARY <= 8'b01100000; + 97 : SH_CNT_MAX_BINARY <= 8'b01100001; + 98 : SH_CNT_MAX_BINARY <= 8'b01100010; + 99 : SH_CNT_MAX_BINARY <= 8'b01100011; + 100 : SH_CNT_MAX_BINARY <= 8'b01100100; + 101 : SH_CNT_MAX_BINARY <= 8'b01100101; + 102 : SH_CNT_MAX_BINARY <= 8'b01100110; + 103 : SH_CNT_MAX_BINARY <= 8'b01100111; + 104 : SH_CNT_MAX_BINARY <= 8'b01101000; + 105 : SH_CNT_MAX_BINARY <= 8'b01101001; + 106 : SH_CNT_MAX_BINARY <= 8'b01101010; + 107 : SH_CNT_MAX_BINARY <= 8'b01101011; + 108 : SH_CNT_MAX_BINARY <= 8'b01101100; + 109 : SH_CNT_MAX_BINARY <= 8'b01101101; + 110 : SH_CNT_MAX_BINARY <= 8'b01101110; + 111 : SH_CNT_MAX_BINARY <= 8'b01101111; + 112 : SH_CNT_MAX_BINARY <= 8'b01110000; + 113 : SH_CNT_MAX_BINARY <= 8'b01110001; + 114 : SH_CNT_MAX_BINARY <= 8'b01110010; + 115 : SH_CNT_MAX_BINARY <= 8'b01110011; + 116 : SH_CNT_MAX_BINARY <= 8'b01110100; + 117 : SH_CNT_MAX_BINARY <= 8'b01110101; + 118 : SH_CNT_MAX_BINARY <= 8'b01110110; + 119 : SH_CNT_MAX_BINARY <= 8'b01110111; + 120 : SH_CNT_MAX_BINARY <= 8'b01111000; + 121 : SH_CNT_MAX_BINARY <= 8'b01111001; + 122 : SH_CNT_MAX_BINARY <= 8'b01111010; + 123 : SH_CNT_MAX_BINARY <= 8'b01111011; + 124 : SH_CNT_MAX_BINARY <= 8'b01111100; + 125 : SH_CNT_MAX_BINARY <= 8'b01111101; + 126 : SH_CNT_MAX_BINARY <= 8'b01111110; + 127 : SH_CNT_MAX_BINARY <= 8'b01111111; + 128 : SH_CNT_MAX_BINARY <= 8'b10000000; + 129 : SH_CNT_MAX_BINARY <= 8'b10000001; + 130 : SH_CNT_MAX_BINARY <= 8'b10000010; + 131 : SH_CNT_MAX_BINARY <= 8'b10000011; + 132 : SH_CNT_MAX_BINARY <= 8'b10000100; + 133 : SH_CNT_MAX_BINARY <= 8'b10000101; + 134 : SH_CNT_MAX_BINARY <= 8'b10000110; + 135 : SH_CNT_MAX_BINARY <= 8'b10000111; + 136 : SH_CNT_MAX_BINARY <= 8'b10001000; + 137 : SH_CNT_MAX_BINARY <= 8'b10001001; + 138 : SH_CNT_MAX_BINARY <= 8'b10001010; + 139 : SH_CNT_MAX_BINARY <= 8'b10001011; + 140 : SH_CNT_MAX_BINARY <= 8'b10001100; + 141 : SH_CNT_MAX_BINARY <= 8'b10001101; + 142 : SH_CNT_MAX_BINARY <= 8'b10001110; + 143 : SH_CNT_MAX_BINARY <= 8'b10001111; + 144 : SH_CNT_MAX_BINARY <= 8'b10010000; + 145 : SH_CNT_MAX_BINARY <= 8'b10010001; + 146 : SH_CNT_MAX_BINARY <= 8'b10010010; + 147 : SH_CNT_MAX_BINARY <= 8'b10010011; + 148 : SH_CNT_MAX_BINARY <= 8'b10010100; + 149 : SH_CNT_MAX_BINARY <= 8'b10010101; + 150 : SH_CNT_MAX_BINARY <= 8'b10010110; + 151 : SH_CNT_MAX_BINARY <= 8'b10010111; + 152 : SH_CNT_MAX_BINARY <= 8'b10011000; + 153 : SH_CNT_MAX_BINARY <= 8'b10011001; + 154 : SH_CNT_MAX_BINARY <= 8'b10011010; + 155 : SH_CNT_MAX_BINARY <= 8'b10011011; + 156 : SH_CNT_MAX_BINARY <= 8'b10011100; + 157 : SH_CNT_MAX_BINARY <= 8'b10011101; + 158 : SH_CNT_MAX_BINARY <= 8'b10011110; + 159 : SH_CNT_MAX_BINARY <= 8'b10011111; + 160 : SH_CNT_MAX_BINARY <= 8'b10100000; + 161 : SH_CNT_MAX_BINARY <= 8'b10100001; + 162 : SH_CNT_MAX_BINARY <= 8'b10100010; + 163 : SH_CNT_MAX_BINARY <= 8'b10100011; + 164 : SH_CNT_MAX_BINARY <= 8'b10100100; + 165 : SH_CNT_MAX_BINARY <= 8'b10100101; + 166 : SH_CNT_MAX_BINARY <= 8'b10100110; + 167 : SH_CNT_MAX_BINARY <= 8'b10100111; + 168 : SH_CNT_MAX_BINARY <= 8'b10101000; + 169 : SH_CNT_MAX_BINARY <= 8'b10101001; + 170 : SH_CNT_MAX_BINARY <= 8'b10101010; + 171 : SH_CNT_MAX_BINARY <= 8'b10101011; + 172 : SH_CNT_MAX_BINARY <= 8'b10101100; + 173 : SH_CNT_MAX_BINARY <= 8'b10101101; + 174 : SH_CNT_MAX_BINARY <= 8'b10101110; + 175 : SH_CNT_MAX_BINARY <= 8'b10101111; + 176 : SH_CNT_MAX_BINARY <= 8'b10110000; + 177 : SH_CNT_MAX_BINARY <= 8'b10110001; + 178 : SH_CNT_MAX_BINARY <= 8'b10110010; + 179 : SH_CNT_MAX_BINARY <= 8'b10110011; + 180 : SH_CNT_MAX_BINARY <= 8'b10110100; + 181 : SH_CNT_MAX_BINARY <= 8'b10110101; + 182 : SH_CNT_MAX_BINARY <= 8'b10110110; + 183 : SH_CNT_MAX_BINARY <= 8'b10110111; + 184 : SH_CNT_MAX_BINARY <= 8'b10111000; + 185 : SH_CNT_MAX_BINARY <= 8'b10111001; + 186 : SH_CNT_MAX_BINARY <= 8'b10111010; + 187 : SH_CNT_MAX_BINARY <= 8'b10111011; + 188 : SH_CNT_MAX_BINARY <= 8'b10111100; + 189 : SH_CNT_MAX_BINARY <= 8'b10111101; + 190 : SH_CNT_MAX_BINARY <= 8'b10111110; + 191 : SH_CNT_MAX_BINARY <= 8'b10111111; + 192 : SH_CNT_MAX_BINARY <= 8'b11000000; + 193 : SH_CNT_MAX_BINARY <= 8'b11000001; + 194 : SH_CNT_MAX_BINARY <= 8'b11000010; + 195 : SH_CNT_MAX_BINARY <= 8'b11000011; + 196 : SH_CNT_MAX_BINARY <= 8'b11000100; + 197 : SH_CNT_MAX_BINARY <= 8'b11000101; + 198 : SH_CNT_MAX_BINARY <= 8'b11000110; + 199 : SH_CNT_MAX_BINARY <= 8'b11000111; + 200 : SH_CNT_MAX_BINARY <= 8'b11001000; + 201 : SH_CNT_MAX_BINARY <= 8'b11001001; + 202 : SH_CNT_MAX_BINARY <= 8'b11001010; + 203 : SH_CNT_MAX_BINARY <= 8'b11001011; + 204 : SH_CNT_MAX_BINARY <= 8'b11001100; + 205 : SH_CNT_MAX_BINARY <= 8'b11001101; + 206 : SH_CNT_MAX_BINARY <= 8'b11001110; + 207 : SH_CNT_MAX_BINARY <= 8'b11001111; + 208 : SH_CNT_MAX_BINARY <= 8'b11010000; + 209 : SH_CNT_MAX_BINARY <= 8'b11010001; + 210 : SH_CNT_MAX_BINARY <= 8'b11010010; + 211 : SH_CNT_MAX_BINARY <= 8'b11010011; + 212 : SH_CNT_MAX_BINARY <= 8'b11010100; + 213 : SH_CNT_MAX_BINARY <= 8'b11010101; + 214 : SH_CNT_MAX_BINARY <= 8'b11010110; + 215 : SH_CNT_MAX_BINARY <= 8'b11010111; + 216 : SH_CNT_MAX_BINARY <= 8'b11011000; + 217 : SH_CNT_MAX_BINARY <= 8'b11011001; + 218 : SH_CNT_MAX_BINARY <= 8'b11011010; + 219 : SH_CNT_MAX_BINARY <= 8'b11011011; + 220 : SH_CNT_MAX_BINARY <= 8'b11011100; + 221 : SH_CNT_MAX_BINARY <= 8'b11011101; + 222 : SH_CNT_MAX_BINARY <= 8'b11011110; + 223 : SH_CNT_MAX_BINARY <= 8'b11011111; + 224 : SH_CNT_MAX_BINARY <= 8'b11100000; + 225 : SH_CNT_MAX_BINARY <= 8'b11100001; + 226 : SH_CNT_MAX_BINARY <= 8'b11100010; + 227 : SH_CNT_MAX_BINARY <= 8'b11100011; + 228 : SH_CNT_MAX_BINARY <= 8'b11100100; + 229 : SH_CNT_MAX_BINARY <= 8'b11100101; + 230 : SH_CNT_MAX_BINARY <= 8'b11100110; + 231 : SH_CNT_MAX_BINARY <= 8'b11100111; + 232 : SH_CNT_MAX_BINARY <= 8'b11101000; + 233 : SH_CNT_MAX_BINARY <= 8'b11101001; + 234 : SH_CNT_MAX_BINARY <= 8'b11101010; + 235 : SH_CNT_MAX_BINARY <= 8'b11101011; + 236 : SH_CNT_MAX_BINARY <= 8'b11101100; + 237 : SH_CNT_MAX_BINARY <= 8'b11101101; + 238 : SH_CNT_MAX_BINARY <= 8'b11101110; + 239 : SH_CNT_MAX_BINARY <= 8'b11101111; + 240 : SH_CNT_MAX_BINARY <= 8'b11110000; + 241 : SH_CNT_MAX_BINARY <= 8'b11110001; + 242 : SH_CNT_MAX_BINARY <= 8'b11110010; + 243 : SH_CNT_MAX_BINARY <= 8'b11110011; + 244 : SH_CNT_MAX_BINARY <= 8'b11110100; + 245 : SH_CNT_MAX_BINARY <= 8'b11110101; + 246 : SH_CNT_MAX_BINARY <= 8'b11110110; + 247 : SH_CNT_MAX_BINARY <= 8'b11110111; + 248 : SH_CNT_MAX_BINARY <= 8'b11111000; + 249 : SH_CNT_MAX_BINARY <= 8'b11111001; + 250 : SH_CNT_MAX_BINARY <= 8'b11111010; + 251 : SH_CNT_MAX_BINARY <= 8'b11111011; + 252 : SH_CNT_MAX_BINARY <= 8'b11111100; + 253 : SH_CNT_MAX_BINARY <= 8'b11111101; + 254 : SH_CNT_MAX_BINARY <= 8'b11111110; + 255 : SH_CNT_MAX_BINARY <= 8'b11111111; + default : begin + $display("Attribute Syntax Error : The Attribute SH_CNT_MAX on GT11 instance %m is set to %d. Legal values for this attribute are 0 to 255.", SH_CNT_MAX); + $finish; + end + endcase + + case (SH_INVALID_CNT_MAX) + 0 : SH_INVALID_CNT_MAX_BINARY <= 8'b00000000; + 1 : SH_INVALID_CNT_MAX_BINARY <= 8'b00000001; + 2 : SH_INVALID_CNT_MAX_BINARY <= 8'b00000010; + 3 : SH_INVALID_CNT_MAX_BINARY <= 8'b00000011; + 4 : SH_INVALID_CNT_MAX_BINARY <= 8'b00000100; + 5 : SH_INVALID_CNT_MAX_BINARY <= 8'b00000101; + 6 : SH_INVALID_CNT_MAX_BINARY <= 8'b00000110; + 7 : SH_INVALID_CNT_MAX_BINARY <= 8'b00000111; + 8 : SH_INVALID_CNT_MAX_BINARY <= 8'b00001000; + 9 : SH_INVALID_CNT_MAX_BINARY <= 8'b00001001; + 10 : SH_INVALID_CNT_MAX_BINARY <= 8'b00001010; + 11 : SH_INVALID_CNT_MAX_BINARY <= 8'b00001011; + 12 : SH_INVALID_CNT_MAX_BINARY <= 8'b00001100; + 13 : SH_INVALID_CNT_MAX_BINARY <= 8'b00001101; + 14 : SH_INVALID_CNT_MAX_BINARY <= 8'b00001110; + 15 : SH_INVALID_CNT_MAX_BINARY <= 8'b00001111; + 16 : SH_INVALID_CNT_MAX_BINARY <= 8'b00010000; + 17 : SH_INVALID_CNT_MAX_BINARY <= 8'b00010001; + 18 : SH_INVALID_CNT_MAX_BINARY <= 8'b00010010; + 19 : SH_INVALID_CNT_MAX_BINARY <= 8'b00010011; + 20 : SH_INVALID_CNT_MAX_BINARY <= 8'b00010100; + 21 : SH_INVALID_CNT_MAX_BINARY <= 8'b00010101; + 22 : SH_INVALID_CNT_MAX_BINARY <= 8'b00010110; + 23 : SH_INVALID_CNT_MAX_BINARY <= 8'b00010111; + 24 : SH_INVALID_CNT_MAX_BINARY <= 8'b00011000; + 25 : SH_INVALID_CNT_MAX_BINARY <= 8'b00011001; + 26 : SH_INVALID_CNT_MAX_BINARY <= 8'b00011010; + 27 : SH_INVALID_CNT_MAX_BINARY <= 8'b00011011; + 28 : SH_INVALID_CNT_MAX_BINARY <= 8'b00011100; + 29 : SH_INVALID_CNT_MAX_BINARY <= 8'b00011101; + 30 : SH_INVALID_CNT_MAX_BINARY <= 8'b00011110; + 31 : SH_INVALID_CNT_MAX_BINARY <= 8'b00011111; + 32 : SH_INVALID_CNT_MAX_BINARY <= 8'b00100000; + 33 : SH_INVALID_CNT_MAX_BINARY <= 8'b00100001; + 34 : SH_INVALID_CNT_MAX_BINARY <= 8'b00100010; + 35 : SH_INVALID_CNT_MAX_BINARY <= 8'b00100011; + 36 : SH_INVALID_CNT_MAX_BINARY <= 8'b00100100; + 37 : SH_INVALID_CNT_MAX_BINARY <= 8'b00100101; + 38 : SH_INVALID_CNT_MAX_BINARY <= 8'b00100110; + 39 : SH_INVALID_CNT_MAX_BINARY <= 8'b00100111; + 40 : SH_INVALID_CNT_MAX_BINARY <= 8'b00101000; + 41 : SH_INVALID_CNT_MAX_BINARY <= 8'b00101001; + 42 : SH_INVALID_CNT_MAX_BINARY <= 8'b00101010; + 43 : SH_INVALID_CNT_MAX_BINARY <= 8'b00101011; + 44 : SH_INVALID_CNT_MAX_BINARY <= 8'b00101100; + 45 : SH_INVALID_CNT_MAX_BINARY <= 8'b00101101; + 46 : SH_INVALID_CNT_MAX_BINARY <= 8'b00101110; + 47 : SH_INVALID_CNT_MAX_BINARY <= 8'b00101111; + 48 : SH_INVALID_CNT_MAX_BINARY <= 8'b00110000; + 49 : SH_INVALID_CNT_MAX_BINARY <= 8'b00110001; + 50 : SH_INVALID_CNT_MAX_BINARY <= 8'b00110010; + 51 : SH_INVALID_CNT_MAX_BINARY <= 8'b00110011; + 52 : SH_INVALID_CNT_MAX_BINARY <= 8'b00110100; + 53 : SH_INVALID_CNT_MAX_BINARY <= 8'b00110101; + 54 : SH_INVALID_CNT_MAX_BINARY <= 8'b00110110; + 55 : SH_INVALID_CNT_MAX_BINARY <= 8'b00110111; + 56 : SH_INVALID_CNT_MAX_BINARY <= 8'b00111000; + 57 : SH_INVALID_CNT_MAX_BINARY <= 8'b00111001; + 58 : SH_INVALID_CNT_MAX_BINARY <= 8'b00111010; + 59 : SH_INVALID_CNT_MAX_BINARY <= 8'b00111011; + 60 : SH_INVALID_CNT_MAX_BINARY <= 8'b00111100; + 61 : SH_INVALID_CNT_MAX_BINARY <= 8'b00111101; + 62 : SH_INVALID_CNT_MAX_BINARY <= 8'b00111110; + 63 : SH_INVALID_CNT_MAX_BINARY <= 8'b00111111; + 64 : SH_INVALID_CNT_MAX_BINARY <= 8'b01000000; + 65 : SH_INVALID_CNT_MAX_BINARY <= 8'b01000001; + 66 : SH_INVALID_CNT_MAX_BINARY <= 8'b01000010; + 67 : SH_INVALID_CNT_MAX_BINARY <= 8'b01000011; + 68 : SH_INVALID_CNT_MAX_BINARY <= 8'b01000100; + 69 : SH_INVALID_CNT_MAX_BINARY <= 8'b01000101; + 70 : SH_INVALID_CNT_MAX_BINARY <= 8'b01000110; + 71 : SH_INVALID_CNT_MAX_BINARY <= 8'b01000111; + 72 : SH_INVALID_CNT_MAX_BINARY <= 8'b01001000; + 73 : SH_INVALID_CNT_MAX_BINARY <= 8'b01001001; + 74 : SH_INVALID_CNT_MAX_BINARY <= 8'b01001010; + 75 : SH_INVALID_CNT_MAX_BINARY <= 8'b01001011; + 76 : SH_INVALID_CNT_MAX_BINARY <= 8'b01001100; + 77 : SH_INVALID_CNT_MAX_BINARY <= 8'b01001101; + 78 : SH_INVALID_CNT_MAX_BINARY <= 8'b01001110; + 79 : SH_INVALID_CNT_MAX_BINARY <= 8'b01001111; + 80 : SH_INVALID_CNT_MAX_BINARY <= 8'b01010000; + 81 : SH_INVALID_CNT_MAX_BINARY <= 8'b01010001; + 82 : SH_INVALID_CNT_MAX_BINARY <= 8'b01010010; + 83 : SH_INVALID_CNT_MAX_BINARY <= 8'b01010011; + 84 : SH_INVALID_CNT_MAX_BINARY <= 8'b01010100; + 85 : SH_INVALID_CNT_MAX_BINARY <= 8'b01010101; + 86 : SH_INVALID_CNT_MAX_BINARY <= 8'b01010110; + 87 : SH_INVALID_CNT_MAX_BINARY <= 8'b01010111; + 88 : SH_INVALID_CNT_MAX_BINARY <= 8'b01011000; + 89 : SH_INVALID_CNT_MAX_BINARY <= 8'b01011001; + 90 : SH_INVALID_CNT_MAX_BINARY <= 8'b01011010; + 91 : SH_INVALID_CNT_MAX_BINARY <= 8'b01011011; + 92 : SH_INVALID_CNT_MAX_BINARY <= 8'b01011100; + 93 : SH_INVALID_CNT_MAX_BINARY <= 8'b01011101; + 94 : SH_INVALID_CNT_MAX_BINARY <= 8'b01011110; + 95 : SH_INVALID_CNT_MAX_BINARY <= 8'b01011111; + 96 : SH_INVALID_CNT_MAX_BINARY <= 8'b01100000; + 97 : SH_INVALID_CNT_MAX_BINARY <= 8'b01100001; + 98 : SH_INVALID_CNT_MAX_BINARY <= 8'b01100010; + 99 : SH_INVALID_CNT_MAX_BINARY <= 8'b01100011; + 100 : SH_INVALID_CNT_MAX_BINARY <= 8'b01100100; + 101 : SH_INVALID_CNT_MAX_BINARY <= 8'b01100101; + 102 : SH_INVALID_CNT_MAX_BINARY <= 8'b01100110; + 103 : SH_INVALID_CNT_MAX_BINARY <= 8'b01100111; + 104 : SH_INVALID_CNT_MAX_BINARY <= 8'b01101000; + 105 : SH_INVALID_CNT_MAX_BINARY <= 8'b01101001; + 106 : SH_INVALID_CNT_MAX_BINARY <= 8'b01101010; + 107 : SH_INVALID_CNT_MAX_BINARY <= 8'b01101011; + 108 : SH_INVALID_CNT_MAX_BINARY <= 8'b01101100; + 109 : SH_INVALID_CNT_MAX_BINARY <= 8'b01101101; + 110 : SH_INVALID_CNT_MAX_BINARY <= 8'b01101110; + 111 : SH_INVALID_CNT_MAX_BINARY <= 8'b01101111; + 112 : SH_INVALID_CNT_MAX_BINARY <= 8'b01110000; + 113 : SH_INVALID_CNT_MAX_BINARY <= 8'b01110001; + 114 : SH_INVALID_CNT_MAX_BINARY <= 8'b01110010; + 115 : SH_INVALID_CNT_MAX_BINARY <= 8'b01110011; + 116 : SH_INVALID_CNT_MAX_BINARY <= 8'b01110100; + 117 : SH_INVALID_CNT_MAX_BINARY <= 8'b01110101; + 118 : SH_INVALID_CNT_MAX_BINARY <= 8'b01110110; + 119 : SH_INVALID_CNT_MAX_BINARY <= 8'b01110111; + 120 : SH_INVALID_CNT_MAX_BINARY <= 8'b01111000; + 121 : SH_INVALID_CNT_MAX_BINARY <= 8'b01111001; + 122 : SH_INVALID_CNT_MAX_BINARY <= 8'b01111010; + 123 : SH_INVALID_CNT_MAX_BINARY <= 8'b01111011; + 124 : SH_INVALID_CNT_MAX_BINARY <= 8'b01111100; + 125 : SH_INVALID_CNT_MAX_BINARY <= 8'b01111101; + 126 : SH_INVALID_CNT_MAX_BINARY <= 8'b01111110; + 127 : SH_INVALID_CNT_MAX_BINARY <= 8'b01111111; + 128 : SH_INVALID_CNT_MAX_BINARY <= 8'b10000000; + 129 : SH_INVALID_CNT_MAX_BINARY <= 8'b10000001; + 130 : SH_INVALID_CNT_MAX_BINARY <= 8'b10000010; + 131 : SH_INVALID_CNT_MAX_BINARY <= 8'b10000011; + 132 : SH_INVALID_CNT_MAX_BINARY <= 8'b10000100; + 133 : SH_INVALID_CNT_MAX_BINARY <= 8'b10000101; + 134 : SH_INVALID_CNT_MAX_BINARY <= 8'b10000110; + 135 : SH_INVALID_CNT_MAX_BINARY <= 8'b10000111; + 136 : SH_INVALID_CNT_MAX_BINARY <= 8'b10001000; + 137 : SH_INVALID_CNT_MAX_BINARY <= 8'b10001001; + 138 : SH_INVALID_CNT_MAX_BINARY <= 8'b10001010; + 139 : SH_INVALID_CNT_MAX_BINARY <= 8'b10001011; + 140 : SH_INVALID_CNT_MAX_BINARY <= 8'b10001100; + 141 : SH_INVALID_CNT_MAX_BINARY <= 8'b10001101; + 142 : SH_INVALID_CNT_MAX_BINARY <= 8'b10001110; + 143 : SH_INVALID_CNT_MAX_BINARY <= 8'b10001111; + 144 : SH_INVALID_CNT_MAX_BINARY <= 8'b10010000; + 145 : SH_INVALID_CNT_MAX_BINARY <= 8'b10010001; + 146 : SH_INVALID_CNT_MAX_BINARY <= 8'b10010010; + 147 : SH_INVALID_CNT_MAX_BINARY <= 8'b10010011; + 148 : SH_INVALID_CNT_MAX_BINARY <= 8'b10010100; + 149 : SH_INVALID_CNT_MAX_BINARY <= 8'b10010101; + 150 : SH_INVALID_CNT_MAX_BINARY <= 8'b10010110; + 151 : SH_INVALID_CNT_MAX_BINARY <= 8'b10010111; + 152 : SH_INVALID_CNT_MAX_BINARY <= 8'b10011000; + 153 : SH_INVALID_CNT_MAX_BINARY <= 8'b10011001; + 154 : SH_INVALID_CNT_MAX_BINARY <= 8'b10011010; + 155 : SH_INVALID_CNT_MAX_BINARY <= 8'b10011011; + 156 : SH_INVALID_CNT_MAX_BINARY <= 8'b10011100; + 157 : SH_INVALID_CNT_MAX_BINARY <= 8'b10011101; + 158 : SH_INVALID_CNT_MAX_BINARY <= 8'b10011110; + 159 : SH_INVALID_CNT_MAX_BINARY <= 8'b10011111; + 160 : SH_INVALID_CNT_MAX_BINARY <= 8'b10100000; + 161 : SH_INVALID_CNT_MAX_BINARY <= 8'b10100001; + 162 : SH_INVALID_CNT_MAX_BINARY <= 8'b10100010; + 163 : SH_INVALID_CNT_MAX_BINARY <= 8'b10100011; + 164 : SH_INVALID_CNT_MAX_BINARY <= 8'b10100100; + 165 : SH_INVALID_CNT_MAX_BINARY <= 8'b10100101; + 166 : SH_INVALID_CNT_MAX_BINARY <= 8'b10100110; + 167 : SH_INVALID_CNT_MAX_BINARY <= 8'b10100111; + 168 : SH_INVALID_CNT_MAX_BINARY <= 8'b10101000; + 169 : SH_INVALID_CNT_MAX_BINARY <= 8'b10101001; + 170 : SH_INVALID_CNT_MAX_BINARY <= 8'b10101010; + 171 : SH_INVALID_CNT_MAX_BINARY <= 8'b10101011; + 172 : SH_INVALID_CNT_MAX_BINARY <= 8'b10101100; + 173 : SH_INVALID_CNT_MAX_BINARY <= 8'b10101101; + 174 : SH_INVALID_CNT_MAX_BINARY <= 8'b10101110; + 175 : SH_INVALID_CNT_MAX_BINARY <= 8'b10101111; + 176 : SH_INVALID_CNT_MAX_BINARY <= 8'b10110000; + 177 : SH_INVALID_CNT_MAX_BINARY <= 8'b10110001; + 178 : SH_INVALID_CNT_MAX_BINARY <= 8'b10110010; + 179 : SH_INVALID_CNT_MAX_BINARY <= 8'b10110011; + 180 : SH_INVALID_CNT_MAX_BINARY <= 8'b10110100; + 181 : SH_INVALID_CNT_MAX_BINARY <= 8'b10110101; + 182 : SH_INVALID_CNT_MAX_BINARY <= 8'b10110110; + 183 : SH_INVALID_CNT_MAX_BINARY <= 8'b10110111; + 184 : SH_INVALID_CNT_MAX_BINARY <= 8'b10111000; + 185 : SH_INVALID_CNT_MAX_BINARY <= 8'b10111001; + 186 : SH_INVALID_CNT_MAX_BINARY <= 8'b10111010; + 187 : SH_INVALID_CNT_MAX_BINARY <= 8'b10111011; + 188 : SH_INVALID_CNT_MAX_BINARY <= 8'b10111100; + 189 : SH_INVALID_CNT_MAX_BINARY <= 8'b10111101; + 190 : SH_INVALID_CNT_MAX_BINARY <= 8'b10111110; + 191 : SH_INVALID_CNT_MAX_BINARY <= 8'b10111111; + 192 : SH_INVALID_CNT_MAX_BINARY <= 8'b11000000; + 193 : SH_INVALID_CNT_MAX_BINARY <= 8'b11000001; + 194 : SH_INVALID_CNT_MAX_BINARY <= 8'b11000010; + 195 : SH_INVALID_CNT_MAX_BINARY <= 8'b11000011; + 196 : SH_INVALID_CNT_MAX_BINARY <= 8'b11000100; + 197 : SH_INVALID_CNT_MAX_BINARY <= 8'b11000101; + 198 : SH_INVALID_CNT_MAX_BINARY <= 8'b11000110; + 199 : SH_INVALID_CNT_MAX_BINARY <= 8'b11000111; + 200 : SH_INVALID_CNT_MAX_BINARY <= 8'b11001000; + 201 : SH_INVALID_CNT_MAX_BINARY <= 8'b11001001; + 202 : SH_INVALID_CNT_MAX_BINARY <= 8'b11001010; + 203 : SH_INVALID_CNT_MAX_BINARY <= 8'b11001011; + 204 : SH_INVALID_CNT_MAX_BINARY <= 8'b11001100; + 205 : SH_INVALID_CNT_MAX_BINARY <= 8'b11001101; + 206 : SH_INVALID_CNT_MAX_BINARY <= 8'b11001110; + 207 : SH_INVALID_CNT_MAX_BINARY <= 8'b11001111; + 208 : SH_INVALID_CNT_MAX_BINARY <= 8'b11010000; + 209 : SH_INVALID_CNT_MAX_BINARY <= 8'b11010001; + 210 : SH_INVALID_CNT_MAX_BINARY <= 8'b11010010; + 211 : SH_INVALID_CNT_MAX_BINARY <= 8'b11010011; + 212 : SH_INVALID_CNT_MAX_BINARY <= 8'b11010100; + 213 : SH_INVALID_CNT_MAX_BINARY <= 8'b11010101; + 214 : SH_INVALID_CNT_MAX_BINARY <= 8'b11010110; + 215 : SH_INVALID_CNT_MAX_BINARY <= 8'b11010111; + 216 : SH_INVALID_CNT_MAX_BINARY <= 8'b11011000; + 217 : SH_INVALID_CNT_MAX_BINARY <= 8'b11011001; + 218 : SH_INVALID_CNT_MAX_BINARY <= 8'b11011010; + 219 : SH_INVALID_CNT_MAX_BINARY <= 8'b11011011; + 220 : SH_INVALID_CNT_MAX_BINARY <= 8'b11011100; + 221 : SH_INVALID_CNT_MAX_BINARY <= 8'b11011101; + 222 : SH_INVALID_CNT_MAX_BINARY <= 8'b11011110; + 223 : SH_INVALID_CNT_MAX_BINARY <= 8'b11011111; + 224 : SH_INVALID_CNT_MAX_BINARY <= 8'b11100000; + 225 : SH_INVALID_CNT_MAX_BINARY <= 8'b11100001; + 226 : SH_INVALID_CNT_MAX_BINARY <= 8'b11100010; + 227 : SH_INVALID_CNT_MAX_BINARY <= 8'b11100011; + 228 : SH_INVALID_CNT_MAX_BINARY <= 8'b11100100; + 229 : SH_INVALID_CNT_MAX_BINARY <= 8'b11100101; + 230 : SH_INVALID_CNT_MAX_BINARY <= 8'b11100110; + 231 : SH_INVALID_CNT_MAX_BINARY <= 8'b11100111; + 232 : SH_INVALID_CNT_MAX_BINARY <= 8'b11101000; + 233 : SH_INVALID_CNT_MAX_BINARY <= 8'b11101001; + 234 : SH_INVALID_CNT_MAX_BINARY <= 8'b11101010; + 235 : SH_INVALID_CNT_MAX_BINARY <= 8'b11101011; + 236 : SH_INVALID_CNT_MAX_BINARY <= 8'b11101100; + 237 : SH_INVALID_CNT_MAX_BINARY <= 8'b11101101; + 238 : SH_INVALID_CNT_MAX_BINARY <= 8'b11101110; + 239 : SH_INVALID_CNT_MAX_BINARY <= 8'b11101111; + 240 : SH_INVALID_CNT_MAX_BINARY <= 8'b11110000; + 241 : SH_INVALID_CNT_MAX_BINARY <= 8'b11110001; + 242 : SH_INVALID_CNT_MAX_BINARY <= 8'b11110010; + 243 : SH_INVALID_CNT_MAX_BINARY <= 8'b11110011; + 244 : SH_INVALID_CNT_MAX_BINARY <= 8'b11110100; + 245 : SH_INVALID_CNT_MAX_BINARY <= 8'b11110101; + 246 : SH_INVALID_CNT_MAX_BINARY <= 8'b11110110; + 247 : SH_INVALID_CNT_MAX_BINARY <= 8'b11110111; + 248 : SH_INVALID_CNT_MAX_BINARY <= 8'b11111000; + 249 : SH_INVALID_CNT_MAX_BINARY <= 8'b11111001; + 250 : SH_INVALID_CNT_MAX_BINARY <= 8'b11111010; + 251 : SH_INVALID_CNT_MAX_BINARY <= 8'b11111011; + 252 : SH_INVALID_CNT_MAX_BINARY <= 8'b11111100; + 253 : SH_INVALID_CNT_MAX_BINARY <= 8'b11111101; + 254 : SH_INVALID_CNT_MAX_BINARY <= 8'b11111110; + 255 : SH_INVALID_CNT_MAX_BINARY <= 8'b11111111; + default : begin + $display("Attribute Syntax Error : The Attribute SH_INVALID_CNT_MAX on GT11 instance %m is set to %d. Legal values for this attribute are 0 to 255.", SH_INVALID_CNT_MAX); + $finish; + end + endcase + + case (ALIGN_COMMA_WORD) + 1 : ALIGN_COMMA_WORD_BINARY <= 2'b00; + 2 : ALIGN_COMMA_WORD_BINARY <= 2'b01; + 4 : ALIGN_COMMA_WORD_BINARY <= 2'b10; + default : begin + $display("Attribute Syntax Error : The Attribute ALIGN_COMMA_WORD on GT11 instance %m is set to %d. Legal values for this attribute are 1, 2 or 4.", ALIGN_COMMA_WORD); + $finish; + end + endcase + + case (DEC_MCOMMA_DETECT) + "FALSE" : DEC_MCOMMA_DETECT_BINARY <= 0; + "TRUE" : DEC_MCOMMA_DETECT_BINARY <= 1; + default : begin + $display("Attribute Syntax Error : The Attribute DEC_MCOMMA_DETECT on GT11 instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", DEC_MCOMMA_DETECT); + $finish; + end + endcase + + case (DEC_PCOMMA_DETECT) + "FALSE" : DEC_PCOMMA_DETECT_BINARY <= 0; + "TRUE" : DEC_PCOMMA_DETECT_BINARY <= 1; + default : begin + $display("Attribute Syntax Error : The Attribute DEC_PCOMMA_DETECT on GT11 instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", DEC_PCOMMA_DETECT); + $finish; + end + endcase + + case (DEC_VALID_COMMA_ONLY) + "FALSE" : DEC_VALID_COMMA_ONLY_BINARY <= 0; + "TRUE" : DEC_VALID_COMMA_ONLY_BINARY <= 1; + default : begin + $display("Attribute Syntax Error : The Attribute DEC_VALID_COMMA_ONLY on GT11 instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", DEC_VALID_COMMA_ONLY); + $finish; + end + endcase + + case (MCOMMA_DETECT) + "FALSE" : MCOMMA_DETECT_BINARY <= 0; + "TRUE" : MCOMMA_DETECT_BINARY <= 1; + default : begin + $display("Attribute Syntax Error : The Attribute MCOMMA_DETECT on GT11 instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", MCOMMA_DETECT); + $finish; + end + endcase + + case (PCOMMA_DETECT) + "FALSE" : PCOMMA_DETECT_BINARY <= 0; + "TRUE" : PCOMMA_DETECT_BINARY <= 1; + default : begin + $display("Attribute Syntax Error : The Attribute PCOMMA_DETECT on GT11 instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", PCOMMA_DETECT); + $finish; + end + endcase + + case (COMMA32) + "FALSE" : COMMA32_BINARY <= 0; + "TRUE" : COMMA32_BINARY <= 1; + default : begin + $display("Attribute Syntax Error : The Attribute COMMA32 on GT11 instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", COMMA32); + $finish; + end + endcase + + case (RXUSRDIVISOR) + 1 : RXUSRDIVISOR_BINARY <= 5'b00001; + 2 : RXUSRDIVISOR_BINARY <= 5'b00010; + 4 : RXUSRDIVISOR_BINARY <= 5'b00100; + 8 : RXUSRDIVISOR_BINARY <= 5'b01000; + 16 : RXUSRDIVISOR_BINARY <= 5'b10000; + default : begin + $display("Attribute Syntax Error : The Attribute RXUSRDIVISOR on GT11 instance %m is set to %d. Legal values for this attribute are 1, 2, 4, 8 or 16.", RXUSRDIVISOR); + $finish; + end + endcase + + case (SAMPLE_8X) + "FALSE" : SAMPLE_8X_BINARY <= 0; + "TRUE" : SAMPLE_8X_BINARY <= 1; + default : begin + $display("Attribute Syntax Error : The Attribute SAMPLE_8X on GT11 instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", SAMPLE_8X); + $finish; + end + endcase + + case (ENABLE_DCDR) + "FALSE" : ENABLE_DCDR_BINARY <= 0; + "TRUE" : ENABLE_DCDR_BINARY <= 1; + default : begin + $display("Attribute Syntax Error : The Attribute ENABLE_DCDR on GT11 instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", ENABLE_DCDR); + $finish; + end + endcase + + case (REPEATER) + "FALSE" : REPEATER_BINARY <= 0; + "TRUE" : REPEATER_BINARY <= 1; + default : begin + $display("Attribute Syntax Error : The Attribute REPEATER on GT11 instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", REPEATER); + $finish; + end + endcase + + case (RXBY_32) + "FALSE" : RXBY_32_BINARY <= 0; + "TRUE" : RXBY_32_BINARY <= 1; + default : begin + $display("Attribute Syntax Error : The Attribute RXBY_32 on GT11 instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", RXBY_32); + $finish; + end + endcase + + case (TXFDCAL_CLOCK_DIVIDE) + "NONE" : TXFDCAL_CLOCK_DIVIDE_BINARY <= 2'b00; + "TWO" : TXFDCAL_CLOCK_DIVIDE_BINARY <= 2'b01; + "FOUR" : TXFDCAL_CLOCK_DIVIDE_BINARY <= 2'b10; + default : begin + $display("Attribute Syntax Error : The Attribute TXFDCAL_CLOCK_DIVIDE on GT11 instance %m is set to %s. Legal values for this attribute are NONE, TWO or FOUR.", TXFDCAL_CLOCK_DIVIDE); + $finish; + end + endcase + + case (RXFDCAL_CLOCK_DIVIDE) + "NONE" : RXFDCAL_CLOCK_DIVIDE_BINARY <= 2'b00; + "TWO" : RXFDCAL_CLOCK_DIVIDE_BINARY <= 2'b01; + "FOUR" : RXFDCAL_CLOCK_DIVIDE_BINARY <= 2'b10; + default : begin + $display("Attribute Syntax Error : The Attribute RXFDCAL_CLOCK_DIVIDE on GT11 instance %m is set to %s. Legal values for this attribute are NONE, TWO or FOUR.", RXFDCAL_CLOCK_DIVIDE); + $finish; + end + endcase + + case (RXVCO_CTRL_ENABLE) + "FALSE" : RXVCO_CTRL_ENABLE_BINARY <= 0; + "TRUE" : RXVCO_CTRL_ENABLE_BINARY <= 1; + default : begin + $display("Attribute Syntax Error : The Attribute RXVCO_CTRL_ENABLE on GT11 instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", RXVCO_CTRL_ENABLE); + $finish; + end + endcase + + case (VCO_CTRL_ENABLE) + "FALSE" : VCO_CTRL_ENABLE_BINARY <= 0; + "TRUE" : VCO_CTRL_ENABLE_BINARY <= 1; + default : begin + $display("Attribute Syntax Error : The Attribute VCO_CTRL_ENABLE on GT11 instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", VCO_CTRL_ENABLE); + $finish; + end + endcase + + case (RXCRCCLOCKDOUBLE) + "FALSE" : RXCRCCLOCKDOUBLE_BINARY <= 0; + "TRUE" : RXCRCCLOCKDOUBLE_BINARY <= 1; + default : begin + $display("Attribute Syntax Error : The Attribute RXCRCCLOCKDOUBLE on GT11 instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", RXCRCCLOCKDOUBLE); + $finish; + end + endcase + + case (RXCRCINVERTGEN) + "FALSE" : RXCRCINVERTGEN_BINARY <= 0; + "TRUE" : RXCRCINVERTGEN_BINARY <= 1; + default : begin + $display("Attribute Syntax Error : The Attribute RXCRCINVERTGEN on GT11 instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", RXCRCINVERTGEN); + $finish; + end + endcase + + case (RXCRCSAMECLOCK) + "FALSE" : RXCRCSAMECLOCK_BINARY <= 0; + "TRUE" : RXCRCSAMECLOCK_BINARY <= 1; + default : begin + $display("Attribute Syntax Error : The Attribute RXCRCSAMECLOCK on GT11 instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", RXCRCSAMECLOCK); + $finish; + end + endcase + + case (RXCRCENABLE) + "FALSE" : RXCRCENABLE_BINARY <= 0; + "TRUE" : RXCRCENABLE_BINARY <= 1; + default : begin + $display("Attribute Syntax Error : The Attribute RXCRCENABLE on GT11 instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", RXCRCENABLE); + $finish; + end + endcase + + case (TXCRCCLOCKDOUBLE) + "FALSE" : TXCRCCLOCKDOUBLE_BINARY <= 0; + "TRUE" : TXCRCCLOCKDOUBLE_BINARY <= 1; + default : begin + $display("Attribute Syntax Error : The Attribute TXCRCCLOCKDOUBLE on GT11 instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", TXCRCCLOCKDOUBLE); + $finish; + end + endcase + + case (TXCRCINVERTGEN) + "FALSE" : TXCRCINVERTGEN_BINARY <= 0; + "TRUE" : TXCRCINVERTGEN_BINARY <= 1; + default : begin + $display("Attribute Syntax Error : The Attribute TXCRCINVERTGEN on GT11 instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", TXCRCINVERTGEN); + $finish; + end + endcase + + case (TXCRCSAMECLOCK) + "FALSE" : TXCRCSAMECLOCK_BINARY <= 0; + "TRUE" : TXCRCSAMECLOCK_BINARY <= 1; + default : begin + $display("Attribute Syntax Error : The Attribute TXCRCSAMECLOCK on GT11 instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", TXCRCSAMECLOCK); + $finish; + end + endcase + + case (TXCRCENABLE) + "FALSE" : TXCRCENABLE_BINARY <= 0; + "TRUE" : TXCRCENABLE_BINARY <= 1; + default : begin + $display("Attribute Syntax Error : The Attribute TXCRCENABLE on GT11 instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", TXCRCENABLE); + $finish; + end + endcase + + case (RXCLK0_FORCE_PMACLK) + "FALSE" : RXCLK0_FORCE_PMACLK_BINARY <= 0; + "TRUE" : RXCLK0_FORCE_PMACLK_BINARY <= 1; + default : begin + $display("Attribute Syntax Error : The Attribute RXCLK0_FORCE_PMACLK on GT11 instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", RXCLK0_FORCE_PMACLK); + $finish; + end + endcase + + case (TXCLK0_FORCE_PMACLK) + "FALSE" : TXCLK0_FORCE_PMACLK_BINARY <= 0; + "TRUE" : TXCLK0_FORCE_PMACLK_BINARY <= 1; + default : begin + $display("Attribute Syntax Error : The Attribute TXCLK0_FORCE_PMACLK on GT11 instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", TXCLK0_FORCE_PMACLK); + $finish; + end + endcase + + case (TXOUTCLK1_USE_SYNC) + "FALSE" : TXOUTCLK1_USE_SYNC_BINARY <= 0; + "TRUE" : TXOUTCLK1_USE_SYNC_BINARY <= 1; + default : begin + $display("Attribute Syntax Error : The Attribute TXOUTCLK1_USE_SYNC on GT11 instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", TXOUTCLK1_USE_SYNC); + $finish; + end + endcase + + case (RXRECCLK1_USE_SYNC) + "FALSE" : RXRECCLK1_USE_SYNC_BINARY <= 0; + "TRUE" : RXRECCLK1_USE_SYNC_BINARY <= 1; + default : begin + $display("Attribute Syntax Error : The Attribute RXRECCLK1_USE_SYNC on GT11 instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", RXRECCLK1_USE_SYNC); + $finish; + end + endcase + + case (RXPMACLKSEL) + "REFCLK1" : RXPMACLKSEL_BINARY <= 2'b00; + "REFCLK2" : RXPMACLKSEL_BINARY <= 2'b01; + "GREFCLK" : RXPMACLKSEL_BINARY <= 2'b10; + default : begin + $display("Attribute Syntax Error : The Attribute RXPMACLKSEL on GT11 instance %m is set to %s. Legal values for this attribute are REFCLK1, REFCLK2 or GREFCLK.", RXPMACLKSEL); + $finish; + end + endcase + + case (TXABPMACLKSEL) + "REFCLK1" : TXABPMACLKSEL_BINARY <= 2'b00; + "REFCLK2" : TXABPMACLKSEL_BINARY <= 2'b01; + "GREFCLK" : TXABPMACLKSEL_BINARY <= 2'b10; + default : begin + $display("Attribute Syntax Error : The Attribute TXABPMACLKSEL on GT11 instance %m is set to %s. Legal values for this attribute are REFCLK1, REFCLK2 or GREFCLK.", TXABPMACLKSEL); + $finish; + end + endcase + + case (BANDGAPSEL) + "FALSE" : BANDGAPSEL_BINARY <= 0; + "TRUE" : BANDGAPSEL_BINARY <= 1; + default : begin + $display("Attribute Syntax Error : The Attribute BANDGAPSEL on GT11 instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", BANDGAPSEL); + $finish; + end + endcase + + case (BIASRESSEL) + "FALSE" : BIASRESSEL_BINARY <= 0; + "TRUE" : BIASRESSEL_BINARY <= 1; + default : begin + $display("Attribute Syntax Error : The Attribute BIASRESSEL on GT11 instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", BIASRESSEL); + $finish; + end + endcase + + case (TXPHASESEL) + "FALSE" : TXPHASESEL_BINARY <= 0; + "TRUE" : TXPHASESEL_BINARY <= 1; + default : begin + $display("Attribute Syntax Error : The Attribute TXPHASESEL on GT11 instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", TXPHASESEL); + $finish; + end + endcase + + case (PMACLKENABLE) + "FALSE" : PMACLKENABLE_BINARY <= 0; + "TRUE" : PMACLKENABLE_BINARY <= 1; + default : begin + $display("Attribute Syntax Error : The Attribute PMACLKENABLE on GT11 instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", PMACLKENABLE); + $finish; + end + endcase + + case (PMACOREPWRENABLE) + "FALSE" : PMACOREPWRENABLE_BINARY <= 0; + "TRUE" : PMACOREPWRENABLE_BINARY <= 1; + default : begin + $display("Attribute Syntax Error : The Attribute PMACOREPWRENABLE on GT11 instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", PMACOREPWRENABLE); + $finish; + end + endcase + + case (PMA_BIT_SLIP) + "FALSE" : PMA_BIT_SLIP_BINARY <= 0; + "TRUE" : PMA_BIT_SLIP_BINARY <= 1; + default : begin + $display("Attribute Syntax Error : The Attribute PMA_BIT_SLIP on GT11 instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", PMA_BIT_SLIP); + $finish; + end + endcase + + case (RXLB) + "FALSE" : RXLB_BINARY <= 0; + "TRUE" : RXLB_BINARY <= 1; + default : begin + $display("Attribute Syntax Error : The Attribute RXLB on GT11 instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", RXLB); + $finish; + end + endcase + + case (RXDCCOUPLE) + "FALSE" : RXDCCOUPLE_BINARY <= 0; + "TRUE" : RXDCCOUPLE_BINARY <= 1; + default : begin + $display("Attribute Syntax Error : The Attribute RXDCCOUPLE on GT11 instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", RXDCCOUPLE); + $finish; + end + endcase + + case (RXDIGRESET) + "FALSE" : RXDIGRESET_BINARY <= 0; + "TRUE" : RXDIGRESET_BINARY <= 1; + default : begin + $display("Attribute Syntax Error : The Attribute RXDIGRESET on GT11 instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", RXDIGRESET); + $finish; + end + endcase + + case (RXCPTST) + "FALSE" : RXCPTST_BINARY <= 0; + "TRUE" : RXCPTST_BINARY <= 1; + default : begin + $display("Attribute Syntax Error : The Attribute RXCPTST on GT11 instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", RXCPTST); + $finish; + end + endcase + + case (RXPDDTST) + "FALSE" : RXPDDTST_BINARY <= 0; + "TRUE" : RXPDDTST_BINARY <= 1; + default : begin + $display("Attribute Syntax Error : The Attribute RXPDDTST on GT11 instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", RXPDDTST); + $finish; + end + endcase + + case (RXACTST) + "FALSE" : RXACTST_BINARY <= 0; + "TRUE" : RXACTST_BINARY <= 1; + default : begin + $display("Attribute Syntax Error : The Attribute RXACTST on GT11 instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", RXACTST); + $finish; + end + endcase + + case (RXAFETST) + "FALSE" : RXAFETST_BINARY <= 0; + "TRUE" : RXAFETST_BINARY <= 1; + default : begin + $display("Attribute Syntax Error : The Attribute RXAFETST on GT11 instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", RXAFETST); + $finish; + end + endcase + + case (RXLKAPD) + "FALSE" : RXLKAPD_BINARY <= 0; + "TRUE" : RXLKAPD_BINARY <= 1; + default : begin + $display("Attribute Syntax Error : The Attribute RXLKAPD on GT11 instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", RXLKAPD); + $finish; + end + endcase + + case (RXRSDPD) + "FALSE" : RXRSDPD_BINARY <= 0; + "TRUE" : RXRSDPD_BINARY <= 1; + default : begin + $display("Attribute Syntax Error : The Attribute RXRSDPD on GT11 instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", RXRSDPD); + $finish; + end + endcase + + case (RXRCPPD) + "FALSE" : RXRCPPD_BINARY <= 0; + "TRUE" : RXRCPPD_BINARY <= 1; + default : begin + $display("Attribute Syntax Error : The Attribute RXRCPPD on GT11 instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", RXRCPPD); + $finish; + end + endcase + + case (RXRPDPD) + "FALSE" : RXRPDPD_BINARY <= 0; + "TRUE" : RXRPDPD_BINARY <= 1; + default : begin + $display("Attribute Syntax Error : The Attribute RXRPDPD on GT11 instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", RXRPDPD); + $finish; + end + endcase + + case (RXAFEPD) + "FALSE" : RXAFEPD_BINARY <= 0; + "TRUE" : RXAFEPD_BINARY <= 1; + default : begin + $display("Attribute Syntax Error : The Attribute RXAFEPD on GT11 instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", RXAFEPD); + $finish; + end + endcase + + case (RXPD) + "FALSE" : RXPD_BINARY <= 0; + "TRUE" : RXPD_BINARY <= 1; + default : begin + $display("Attribute Syntax Error : The Attribute RXPD on GT11 instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", RXPD); + $finish; + end + endcase + + case (TXOUTDIV2SEL) + 1 : TXOUTDIV2SEL_BINARY <= 4'b0001; + 2 : TXOUTDIV2SEL_BINARY <= 4'b0010; + 4 : TXOUTDIV2SEL_BINARY <= 4'b0011; + 8 : TXOUTDIV2SEL_BINARY <= 4'b0100; + 16 : TXOUTDIV2SEL_BINARY <= 4'b0101; + 32 : TXOUTDIV2SEL_BINARY <= 4'b0110; + default : begin + $display("Attribute Syntax Error : The Attribute TXOUTDIV2SEL on GT11 instance %m is set to %d. Legal values for this attribute are 1, 2, 4, 8, 16 or 32.", TXOUTDIV2SEL); + $finish; + end + endcase + + case (TXPLLNDIVSEL) + 8 : TXPLLNDIVSEL_BINARY <= 4'b0000; + 10 : TXPLLNDIVSEL_BINARY <= 4'b0010; + 16 : TXPLLNDIVSEL_BINARY <= 4'b0100; + 20 : TXPLLNDIVSEL_BINARY <= 4'b0110; + 32 : TXPLLNDIVSEL_BINARY <= 4'b1000; + 40 : TXPLLNDIVSEL_BINARY <= 4'b1010; + default : begin + $display("Attribute Syntax Error : The Attribute TXPLLNDIVSEL on GT11 instance %m is set to %d. Legal values for this attribute are 8, 10, 16, 20, 32 or 40.", TXPLLNDIVSEL); + $finish; + end + endcase + + case (TXCPSEL) + "FALSE" : TXCPSEL_BINARY <= 0; + "TRUE" : TXCPSEL_BINARY <= 1; + default : begin + $display("Attribute Syntax Error : The Attribute TXCPSEL on GT11 instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", TXCPSEL); + $finish; + end + endcase + + case (TXAPD) + "FALSE" : TXAPD_BINARY <= 0; + "TRUE" : TXAPD_BINARY <= 1; + default : begin + $display("Attribute Syntax Error : The Attribute TXAPD on GT11 instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", TXAPD); + $finish; + end + endcase + + case (TXLVLSHFTPD) + "FALSE" : TXLVLSHFTPD_BINARY <= 0; + "TRUE" : TXLVLSHFTPD_BINARY <= 1; + default : begin + $display("Attribute Syntax Error : The Attribute TXLVLSHFTPD on GT11 instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", TXLVLSHFTPD); + $finish; + end + endcase + + case (TXPRE_TAP_PD) + "FALSE" : TXPRE_TAP_PD_BINARY <= 0; + "TRUE" : TXPRE_TAP_PD_BINARY <= 1; + default : begin + $display("Attribute Syntax Error : The Attribute TXPRE_TAP_PD on GT11 instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", TXPRE_TAP_PD); + $finish; + end + endcase + + case (TXDIGPD) + "FALSE" : TXDIGPD_BINARY <= 0; + "TRUE" : TXDIGPD_BINARY <= 1; + default : begin + $display("Attribute Syntax Error : The Attribute TXDIGPD on GT11 instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", TXDIGPD); + $finish; + end + endcase + + case (TXHIGHSIGNALEN) + "FALSE" : TXHIGHSIGNALEN_BINARY <= 0; + "TRUE" : TXHIGHSIGNALEN_BINARY <= 1; + default : begin + $display("Attribute Syntax Error : The Attribute TXHIGHSIGNALEN on GT11 instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", TXHIGHSIGNALEN); + $finish; + end + endcase + + case (TXAREFBIASSEL) + "FALSE" : TXAREFBIASSEL_BINARY <= 0; + "TRUE" : TXAREFBIASSEL_BINARY <= 1; + default : begin + $display("Attribute Syntax Error : The Attribute TXAREFBIASSEL on GT11 instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", TXAREFBIASSEL); + $finish; + end + endcase + + case (TXSLEWRATE) + "FALSE" : TXSLEWRATE_BINARY <= 0; + "TRUE" : TXSLEWRATE_BINARY <= 1; + default : begin + $display("Attribute Syntax Error : The Attribute TXSLEWRATE on GT11 instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", TXSLEWRATE); + $finish; + end + endcase + + case (TXPOST_TAP_PD) + "FALSE" : TXPOST_TAP_PD_BINARY <= 0; + "TRUE" : TXPOST_TAP_PD_BINARY <= 1; + default : begin + $display("Attribute Syntax Error : The Attribute TXPOST_TAP_PD on GT11 instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", TXPOST_TAP_PD); + $finish; + end + endcase + + case (TXPD) + "FALSE" : TXPD_BINARY <= 0; + "TRUE" : TXPD_BINARY <= 1; + default : begin + $display("Attribute Syntax Error : The Attribute TXPD on GT11 instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", TXPD); + $finish; + end + endcase + + case (RXOUTDIV2SEL) + 1 : RXOUTDIV2SEL_BINARY <= 8'b00010001; + 2 : RXOUTDIV2SEL_BINARY <= 8'b00100010; + 4 : RXOUTDIV2SEL_BINARY <= 8'b00110011; + 8 : RXOUTDIV2SEL_BINARY <= 8'b01000100; + 16 : RXOUTDIV2SEL_BINARY <= 8'b01010101; + 32 : RXOUTDIV2SEL_BINARY <= 8'b01100110; + default : begin + $display("Attribute Syntax Error : The Attribute RXOUTDIV2SEL on GT11 instance %m is set to %d. Legal values for this attribute are 1, 2, 4, 8, 16 or 32.", RXOUTDIV2SEL); + $finish; + end + endcase + + case (RXPLLNDIVSEL) + 8 : RXPLLNDIVSEL_BINARY <= 4'b0000; + 10 : RXPLLNDIVSEL_BINARY <= 4'b0010; + 16 : RXPLLNDIVSEL_BINARY <= 4'b0100; + 20 : RXPLLNDIVSEL_BINARY <= 4'b0110; + 32 : RXPLLNDIVSEL_BINARY <= 4'b1000; + 40 : RXPLLNDIVSEL_BINARY <= 4'b1010; + default : begin + $display("Attribute Syntax Error : The Attribute RXPLLNDIVSEL on GT11 instance %m is set to %d. Legal values for this attribute are 8, 10, 16, 20, 32 or 40.", RXPLLNDIVSEL); + $finish; + end + endcase + + case (RXDIGRX) + "FALSE" : RXDIGRX_BINARY <= 0; + "TRUE" : RXDIGRX_BINARY <= 1; + default : begin + $display("Attribute Syntax Error : The Attribute RXDIGRX on GT11 instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", RXDIGRX); + $finish; + end + endcase + + case (RXCPSEL) + "FALSE" : RXCPSEL_BINARY <= 0; + "TRUE" : RXCPSEL_BINARY <= 1; + default : begin + $display("Attribute Syntax Error : The Attribute RXCPSEL on GT11 instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", RXCPSEL); + $finish; + end + endcase + + case (RXAPD) + "FALSE" : RXAPD_BINARY <= 0; + "TRUE" : RXAPD_BINARY <= 1; + default : begin + $display("Attribute Syntax Error : The Attribute RXAPD on GT11 instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", RXAPD); + $finish; + end + endcase + +end + +wire [63:0] synDigCfgChnBnd1; +wire [63:0] synDigCfgChnBnd2; +wire [63:0] synDigCfgClkCor1; +wire [63:0] synDigCfgClkCor2; +wire [63:0] synDigCfgMisc; +wire [63:0] synDigCfgComma1; +wire [63:0] synDigCfgComma2; +wire [63:0] synDigCfgSynPmaFD; +wire [63:0] synDigCfgCrc; +wire [63:0] PMACFG; +wire [63:0] PMACFG2; +wire [63:0] RXAFECFG; +wire [63:0] RXAEQCFG; +wire [63:0] TXCLCFG; +wire [63:0] TXACFG; +wire [63:0] RXACLCFG; + +assign synDigCfgChnBnd1 = { + 1'b0, // RESERVED_CB1_BINARY, // .synDigCfgChnBnd1 63 FALSE + TX_BUFFER_USE_BINARY, // .synDigCfgChnBnd1 62 TRUE + RX_BUFFER_USE_BINARY, // .synDigCfgChnBnd1 61 TRUE + CHAN_BOND_SEQ_LEN_BINARY, // .synDigCfgChnBnd1 60:58 1 + CHAN_BOND_SEQ_2_USE_BINARY, // .synDigCfgChnBnd1 57 FALSE + CHAN_BOND_ONE_SHOT_BINARY, // .synDigCfgChnBnd1 56 FALSE + CHAN_BOND_MODE_BINARY, // .synDigCfgChnBnd1 55:54 OFF + CHAN_BOND_LIMIT_BINARY, // .synDigCfgChnBnd1 53:48 16 + CHAN_BOND_SEQ_1_MASK, // .synDigCfgChnBnd1 47:44 4'b0000 + CHAN_BOND_SEQ_1_4, // .synDigCfgChnBnd1 43:33 11'b00000000000 + CHAN_BOND_SEQ_1_3, // .synDigCfgChnBnd1 32:22 11'b00000000000 + CHAN_BOND_SEQ_1_2, // .synDigCfgChnBnd1 21:11 11'b00000000000 + CHAN_BOND_SEQ_1_1 // .synDigCfgChnBnd1 10:0 11'b00000000000 +}; + +assign synDigCfgChnBnd2 = { + 8'b0, // CHAN_BOND_TUNE, // .synDigCfgChnBnd2 63:56 8'b00000000 + 1'b0, //UNUSED BINARY // .synDigCfgChnBnd2 55 + 1'b0, //UNUSED_BINARY // .synDigCfgChnBnd2 54 + CCCB_ARBITRATOR_DISABLE_BINARY, // .synDigCfgChnBnd2 53 FALSE + OPPOSITE_SELECT_BINARY, // .synDigCfgChnBnd2 52 FALSE + POWER_ENABLE_BINARY, // .synDigCfgChnBnd2 51 TRUE + 3'b0, // TEST_MODE_BINARY, // .synDigCfgChnBnd2 50:48 3'b000 + CHAN_BOND_SEQ_2_MASK, // .synDigCfgChnBnd2 47:44 4'b0000 + CHAN_BOND_SEQ_2_4, // .synDigCfgChnBnd2 43:33 11'b00000000000 + CHAN_BOND_SEQ_2_3, // .synDigCfgChnBnd2 32:22 11'b00000000000 + CHAN_BOND_SEQ_2_2, // .synDigCfgChnBnd2 21:11 11'b00000000000 + CHAN_BOND_SEQ_2_1 // .synDigCfgChnBnd2 10:0 11'b00000000000 +}; + +assign synDigCfgClkCor1 = { + RXDATA_SEL, // .synDigCfgClkCor1 63:62 2'b00 + TXDATA_SEL, // .synDigCfgClkCor1 61:60 2'b00 + 1'b0, // RESERVED_CCB // .synDigCfgClkCor1 59 1'b0 + CLK_COR_MIN_LAT_BINARY, // .synDigCfgClkCor1 58:53 28 + 1'b0, // RESERVED_CCA // .synDigCfgClkCor1 52 1'b0 + PCS_BIT_SLIP_BINARY, // .synDigCfgClkCor1 51 1'b0 + DIGRX_SYNC_MODE_BINARY, // .synDigCfgClkCor1 50 1'b0 + DIGRX_FWDCLK, // .synDigCfgClkCor1 49:48 2'b0 + CLK_COR_SEQ_1_MASK, // .synDigCfgClkCor1 47:44 4'b0000 + CLK_COR_SEQ_1_4, // .synDigCfgClkCor1 43:33 11'b00000000000 + CLK_COR_SEQ_1_3, // .synDigCfgClkCor1 32:22 11'b00000000000 + CLK_COR_SEQ_1_2, // .synDigCfgClkCor1 21:11 11'b00000000000 + CLK_COR_SEQ_1_1 // .synDigCfgClkCor1 10:0 11'b00000000000 +}; + +assign synDigCfgClkCor2 = { + 8'b0, // RX_LOS_THRESHOLD_BINARY, // .synDigCfgClkCor2 63:56 4 + 8'b0, // RX_LOS_INVALID_INCR_BINARY, // .synDigCfgClkCor2 55:48 1 + CLK_COR_SEQ_2_MASK, // .synDigCfgClkCor2 47:44 4'b0000 + CLK_COR_SEQ_2_4, // .synDigCfgClkCor2 43:33 11'b00000000000 + CLK_COR_SEQ_2_3, // .synDigCfgClkCor2 32:22 11'b00000000000 + CLK_COR_SEQ_2_2, // .synDigCfgClkCor2 21:11 11'b00000000000 + CLK_COR_SEQ_2_1 // .synDigCfgClkCor2 10:0 11'b00000000000 +}; + +assign synDigCfgMisc = { + RXRECCLK1_USE_SYNC_BINARY, // .synDigCfgMisc 63 FALSE + TXOUTCLK1_USE_SYNC_BINARY, // .synDigCfgMisc 62 FALSE + TXCLK0_FORCE_PMACLK_BINARY, // .synDigCfgMisc 61 1'b0 + RXCLK0_FORCE_PMACLK_BINARY, // .synDigCfgMisc 60 1'b0 + TX_CLOCK_DIVIDER, // .synDigCfgMisc 59:58 2'b00 + RX_CLOCK_DIVIDER, // .synDigCfgMisc 57:56 2'b00 + TXCRCENABLE_BINARY, // .synDigCfgMisc 55 FALSE + TXCRCSAMECLOCK_BINARY, // .synDigCfgMisc 54 FALSE + TXCRCINVERTGEN_BINARY, // .synDigCfgMisc 53 FALSE + TXCRCCLOCKDOUBLE_BINARY, // .synDigCfgMisc 52 FALSE + RXCRCENABLE_BINARY, // .synDigCfgMisc 51 FALSE + RXCRCSAMECLOCK_BINARY, // .synDigCfgMisc 50 FALSE + RXCRCINVERTGEN_BINARY, // .synDigCfgMisc 49 FALSE + RXCRCCLOCKDOUBLE_BINARY, // .synDigCfgMisc 48 FALSE + RXFDCAL_CLOCK_DIVIDE_BINARY, // .synDigCfgMisc 47:46 2'b00 + TXFDCAL_CLOCK_DIVIDE_BINARY, // .synDigCfgMisc 45:44 2'b00 + RXBY_32_BINARY, // .synDigCfgMisc 43 FALSE + REPEATER_BINARY, // .synDigCfgMisc 42 FALSE + ENABLE_DCDR_BINARY, // .synDigCfgMisc 41 FALSE + SAMPLE_8X_BINARY, // .synDigCfgMisc 40 FALSE + DCDR_FILTER, // .synDigCfgMisc 39:37 3'b110 + RXUSRDIVISOR_BINARY, // .synDigCfgMisc 36:32 1 + SH_INVALID_CNT_MAX_BINARY, // .synDigCfgMisc 31:24 16 + SH_CNT_MAX_BINARY, // .synDigCfgMisc 23:16 64 + 1'b0, // RESERVED_M2, // .synDigCfgMisc 15 1'b0 + CLK_COR_8B10B_DE_BINARY, // .synDigCfgMisc 14 FALSE + CLK_CORRECT_USE_BINARY, // .synDigCfgMisc 13 TRUE + CLK_COR_SEQ_LEN_BINARY, // .synDigCfgMisc 12:10 1 + CLK_COR_SEQ_DROP_BINARY, // .synDigCfgMisc 9 FALSE + CLK_COR_SEQ_2_USE_BINARY, // .synDigCfgMisc 8 FALSE + 1'b0, // TXCLK0_INVERT_PMALEAF_BINARY, // .synDigCfgMisc 7 FALSE + 1'b0, // RXCLK0_INVERT_PMALEAF_BINARY_BINARY, // .synDigCfgMisc 6 FALSE + CLK_COR_MAX_LAT_BINARY // .synDigCfgMisc 5:0 36 +}; + +assign synDigCfgComma1 = { + 22'h0, // RESERVED_CM2, // .synDigCfgComma1 63:42 22'h000000 + COMMA_10B_MASK[9:0], // .synDigCfgComma1 41:32 10'h007 + 24'h0, // RESERVED_CM, // .synDigCfgComma1 31:8 24'h000000 + COMMA32_BINARY, // .synDigCfgComma1 7 FALSE + PCOMMA_DETECT_BINARY, // .synDigCfgComma1 6 TRUE + MCOMMA_DETECT_BINARY, // .synDigCfgComma1 5 TRUE + DEC_VALID_COMMA_ONLY_BINARY, // .synDigCfgComma1 4 TRUE + DEC_PCOMMA_DETECT_BINARY, // .synDigCfgComma1 3 TRUE + DEC_MCOMMA_DETECT_BINARY, // .synDigCfgComma1 2 TRUE + ALIGN_COMMA_WORD_BINARY // .synDigCfgComma1 1:0 1 +}; + +assign synDigCfgComma2 = { + PCOMMA_32B_VALUE, // .synDigCfgComma2 63:32 PCOMMA_10B_VALUE = 32'Ha1a1a2a2/10'b17c + MCOMMA_32B_VALUE // .synDigCfgComma2 31:0 MCOMMA_10B_VALUE = 32'Ha1a1a2a2/10'b283 +}; + +assign synDigCfgSynPmaFD = { + 1'b1, // AUTO_CAL_BINARY, // .synDigCfgSynPmaFD 63 TRUE + VCODAC_INIT, // .synDigCfgSynPmaFD 62:53 10'b1010000000 + 2'b00, // SLOWDOWN_CAL, //.synDigCfgSynPmaFD 52:51 2'b00 + 1'b0, // BYPASS_FDET_BINARY, // .synDigCfgSynPmaFD 50 FALSE + LOOPCAL_WAIT, // .synDigCfgSynPmaFD 49:48 2'b00 + 1'b0, // BYPASS_CAL_BINARY, // .synDigCfgSynPmaFD 47 FALSE + FDET_HYS_CAL, // .synDigCfgSynPmaFD 46:44 3'b000 + FDET_LCK_CAL, // .synDigCfgSynPmaFD 43:41 3'b000 + FDET_HYS_SEL, // .synDigCfgSynPmaFD 40:38 3'b000 + FDET_LCK_SEL, // .synDigCfgSynPmaFD 37:35 3'b000 + VCO_CTRL_ENABLE_BINARY, // .synDigCfgSynPmaFD 34 FALSE + CYCLE_LIMIT_SEL, // .synDigCfgSynPmaFD 33:32 2'b00 + 1'b1, // RXAUTO_CAL_BINARY, // .synDigCfgSynPmaFD 31 TRUE + RXVCODAC_INIT, // .synDigCfgSynPmaFD 30:21 10'b1010000000 + RXSLOWDOWN_CAL, // .synDigCfgSynPmaFD 20:19 2'b00 + 1'b0, // RXBYPASS_FDET_BINARY, // .synDigCfgSynPmaFD 18 FALSE + RXLOOPCAL_WAIT, // .synDigCfgSynPmaFD 17:16 2'b00 + 1'b0, // RXBYPASS_CAL_BINARY, // .synDigCfgSynPmaFD 15 FALSE + RXFDET_HYS_CAL, // .synDigCfgSynPmaFD 14:12 3'b000 + RXFDET_LCK_CAL, // .synDigCfgSynPmaFD 11:9 3'b000 + RXFDET_HYS_SEL, // .synDigCfgSynPmaFD 8:6 3'b000 + RXFDET_LCK_SEL, // .synDigCfgSynPmaFD 5:3 3'b000 + RXVCO_CTRL_ENABLE_BINARY, // .synDigCfgSynPmaFD 2 FALSE + RXCYCLE_LIMIT_SEL // .synDigCfgSynPmaFD 1:0 2'b00 +}; + +assign synDigCfgCrc = { + TXCRCINITVAL, // .synDigCfgCrc 63:32 32'h00000000 + RXCRCINITVAL // .synDigCfgCrc 31:0 32'h00000000 +}; + +assign PMACFG = { + 2'b0, // UNUSED_BINARY.PMACFG 63:62 + RXPMACLKSEL_BINARY, // .PMACFG 61:60 2'b00 + RXPMACLKSEL_BINARY, // .PMACFG 59:58 + TXABPMACLKSEL_BINARY, // .PMACFG 57:56 2'b00 + 8'b0, // UNUSED_BINARY, // .PMACFG 55:48 + 1'b0, // PMATUNE_BINARY, // .PMACFG 47 FALSE + 5'b0, // TXREGCTRL_BINARY, // .PMACFG 46:42 5'b00000 + RXAREGCTRL, // .PMACFG 41:37 5'b00000 + PMAVBGCTRL, // .PMACFG 36:32 5'b00000 + BANDGAPSEL_BINARY, // .PMACFG 31 FALSE + PMAIREFTRIM, // .PMACFG 30:27 4'b0000 + IREFBIASMODE, // .PMACFG 26:25 2'b00 + BIASRESSEL_BINARY, // .PMACFG 24 FALSE + PMAVREFTRIM, // .PMACFG 23:20 =4'b0000 + 1'b0, // VREFSELECT_BINARY, // .PMACFG 19 FALSE + VREFBIASMODE, // .PMACFG 18:17 2'b00 + 1'b0, // PMABIASPD_BINARY, // .PMACFG 16 FALSE + 2'b0, // UNUSED_BINARY, // .PMACFG 15:14 + 1'b0, // ATBENABLE_BINARY, // .PMACFG 13 FALSE + 1'b0, // ATBBUMPEN_BINARY, // .PMACFG 12 FALSE + 1'b0, // NATBENABLE_BINARY, // .PMACFG 11 FALSE + 6'b0, // UNUSED_BINARY, // .PMACFG 10:5 + TXPHASESEL_BINARY, // .PMACFG 4 FALSE + 1'b0, // UNUSED_BINARY, // .PMACFG 3 1'0 + 1'b0, // PMACTRL_BINARY, // .PMACFG 2 1'0 + PMACLKENABLE_BINARY, // .PMACFG 1 TRUE + PMACOREPWRENABLE_BINARY // .PMACFG 0 TRUE +}; + +assign PMACFG2 = { + 46'b0, // UNUSED_BINARY, // .PMACFG2 63:18 + 18'b0 // ATBSEL_BINARY // .PMACFG2 17:0 18'h00000 +}; + +assign RXAFECFG = { + RXMODE, // .RXAFECFG 63:58 6'h00 + PMA_BIT_SLIP_BINARY, // // .RXAFECFG 57 FALSE + RXASYNCDIVIDE, // // .RXAFECFG 56:55 2'b00 + RXCLKMODE, // .RXAFECFG 54:49 6'b110000 + RXLB_BINARY, // .RXAFECFG 48 FALSE + RXFETUNE, // .RXAFECFG 47:46 2'b01 + RXRCPADJ, // .RXAFECFG 45:43 3'b000 + RXRIBADJ, // .RXAFECFG 42:41 2'b00 + RXAFEEQ, // .RXAFECFG 40:32 9'h000 + RXCMADJ, // .RXAFECFG 31:30 2'b00 + RXCDRLOS, // .RXAFECFG 29:24 6'b000000 + 1'b0, // UNUSED_BINARY, //.RXAFECFG 23 1'b0 + RXDCCOUPLE_BINARY, // .RXAFECFG 22 FALSE + 1'b0, // UNUSED_BINARY, // .RXAFECFG 21 + RXLKADJ, // .RXAFECFG 20:16 5'b00000 + RXDIGRESET_BINARY, // .RXAFECFG 15 FALSE + RXFECONTROL2, // .RXAFECFG 14:12 + RXCPTST_BINARY, // .RXAFECFG 11 FALSE + RXPDDTST_BINARY, // .RXAFECFG 10 FALSE + RXACTST_BINARY, // .RXAFECFG 9 FALSE + RXAFETST_BINARY, // .RXAFECFG 8 FALSE + RXFECONTROL1, // .RXAFECFG 7:6 + RXLKAPD_BINARY, // .RXAFECFG 5 FALSE + RXRSDPD_BINARY, // .RXAFECFG 4 FALSE + RXRCPPD_BINARY, // .RXAFECFG 3 FALSE + RXRPDPD_BINARY, // .RXAFECFG 2 FALSE + RXAFEPD_BINARY, // .RXAFECFG 1 FALSE + RXPD_BINARY // .RXAFECFG 0 FALSE +}; + +assign RXAEQCFG = { + RXEQ // .RXAEQCFG 63:0 64'h0000000000000000 +}; + +assign TXCLCFG = { + TXOUTDIV2SEL_BINARY, // .TXCLCFG 63:60 + TXPLLNDIVSEL_BINARY, // .TXCLCFG 59:56 4'b0000 + TXCLMODE, // .TXCLCFG 55:54 2'b00 + TXLOOPFILT, // .TXCLCFG 53:50 4'b0000 + 1'b0, // UNUSED_BINARY, // .TXCLCFG 49 + 1'b0, // UNUSED_BINARY, // .TXCLCFG 48 + TXTUNE[12:0], // .TXCLCFG 47:35 + 1'b0, // UNUSED_BINARY, // .TXCLCFG 34 + 1'b0, // UNUSED_BINARY, // .TXCLCFG 33 + TXCPSEL_BINARY, // .TXCLCFG 32 FALSE + 1'b0, // TXDACTST_BINARY, // .TXCLCFG 31 FALSE + TXOUTDIV2SEL_BINARY, // .TXCLCFG 30:27 4'b0000 + TXCTRL1[9:0], // UNUSED_BINARY, // .TXCLCFG 26:17 + 1'b0, // TXQPPD_BINARY, // .TXCLCFG 16 FALSE + 1'b0, // TXCMFPD_BINARY, // .TXCLCFG 15 FALSE + 1'b0, // TXVCOPD_BINARY, // .TXCLCFG 14 FALSE + 1'b0, // TXADCADJPD_BINARY, // .TXCLCFG 13 FALSE + 1'b0, // TXDIVPD_BINARY, // .TXCLCFG 12 FALSE + 1'b0, // TXBIASPD_BINARY, // .TXCLCFG 11 FALSE + 1'b0, // TXVCOBUFPD_BINARY, // .TXCLCFG 10 FALSE + 1'b0, // TXDIVBUFPD_BINARY, // .TXCLCFG 9 FALSE + TXAPD_BINARY, // .TXCLCFG 8 FALSE + 1'b0, // TXAPTST_BINARY, // .TXCLCFG 7 FALSE + 1'b0, // TXCMFTST_BINARY, // .TXCLCFG 6 FALSE + 1'b0, // TXFILTTST_BINARY, // .TXCLCFG 5 FALSE + 1'b0, // TXDIVTST_BINARY, // .TXCLCFG 4 FALSE + 1'b0, // TXPFDTST_BINARY, // .TXCLCFG 3 FALSE + 1'b0, // TXVCOBUFTST_BINARY, // .TXCLCFG 2 FALSE + 1'b0, // TXDIVBUFTST_BINARY, // .TXCLCFG 1 FALSE + 1'b0 // TXVCOTST_BINARY // .TXCLCFG 0 FALSE +}; + +assign TXACFG = { + 4'b0, // TXLNDR_TST1_BINARY, // .TXACFG 63:60 4'b0000 + TXLVLSHFTPD_BINARY, // .TXACFG 59 FALSE + TXPRE_PRDRV_DAC, // .TXACFG 58:56 3'b000 + TXPRE_TAP_PD_BINARY, // .TXACFG 55 FALSE + TXPRE_TAP_DAC[4:3], // .TXACFG 54:53 5'b00000 + TXDIGPD_BINARY, // .TXACFG 52 FALSE + TXCLKMODE, // .TXACFG 51:48 4'b1100 + TXPRE_TAP_DAC[2:0], // .TXACFG 47:45 5'b00000 + 1'b0, // TXCFGENABLE_BINARY, // .TXACFG 44 FALSE + TXHIGHSIGNALEN_BINARY, // .TXACFG 43 TRUE + TXAREFBIASSEL_BINARY, // .TXACFG 42 FALSE + TXTERMTRIM, // .TXACFG 41:38 4'b0000 + TXASYNCDIVIDE[1], // .TXACFG 37 FALSE + TXSLEWRATE_BINARY, // .TXACFG 36 FALSE + TXPOST_PRDRV_DAC, // .TXACFG 35:33 3'b000 + TXDAT_PRDRV_DAC, // .TXACFG 32:30 3'b000 + TXASYNCDIVIDE[0], // .TXACFG 29 + TXPOST_TAP_PD_BINARY, // .TXACFG 28 TRUE + TXPOST_TAP_DAC, // .TXACFG 27:23 5'b00000 + 2'b0, // TXLNDR_TST2_BINARY, // .TXACFG 22:21 2'b00 + TXDAT_TAP_DAC, // .TXACFG 20:16 5'b00000 + 15'b0, // UNUSED_BINARY, // .TXACFG 15:1 + TXPD_BINARY // .TXACFG 0 FALSE +}; + +assign RXACLCFG = { + RXOUTDIV2SEL_BINARY[7:4], // .RXACLCFG 63:60 4'b0000 + RXPLLNDIVSEL_BINARY, // .RXACLCFG 59:56 4'b0000 + RXCLMODE, // .RXACLCFG 55:54 2'b00 + RXLOOPFILT, // .RXACLCFG 53:50 4'b0000 + RXDIGRX_BINARY, // .RXACLCFG 49 FALSE + 1'b0, // UNUSED_BINARY, // .RXACLCFG 48 FALSE + RXTUNE[12:0], // .RXACLCFG 47:35 + 1'b0, // UNUSED_BINARY, // .RXACLCFG 34 FALSE + 1'b0, // UNUSED_BINARY, // .RXACLCFG 33 FALSE + RXCPSEL_BINARY, // .RXACLCFG 32 FALSE + 1'b0, // RXDACTST_BINARY, // .RXACLCFG 31 FALSE + RXOUTDIV2SEL_BINARY[3:0], // .RXACLCFG 30:27 + RXCTRL1[9:0], // .RXACLCFG 26:17 + 1'b0, // RXQPPD_BINARY, // .RXACLCFG 16 FALSE + 1'b1, // RXCMFPD_BINARY, // .RXACLCFG 15 TRUE + 1'b0, // RXVCOPD_BINARY, // .RXACLCFG 14 FALSE + 1'b0, // RXADCADJPD_BINARY, // .RXACLCFG 13 FALSE + 1'b0, // RXDIVPD_BINARY, // .RXACLCFG 12 FALSE + 1'b0, // RXBIASPD_BINARY, // .RXACLCFG 11 FALSE + 1'b0, // RXVCOBUFPD_BINARY, // .RXACLCFG 10 FALSE + 1'b0, // RXDIVBUFPD_BINARY, // .RXACLCFG 9 FALSE + RXAPD_BINARY, // .RXACLCFG 8 FALSE + 1'b0, // RXAPTST_BINARY, // .RXACLCFG 7 FALSE + 1'b0, // RXCMFTST_BINARY, // .RXACLCFG 6 FALSE + 1'b0, // RXFILTTST_BINARY, // .RXACLCFG 5 FALSE + 1'b0, // RXDIVTST_BINARY, // .RXACLCFG 4 FALSE + 1'b0, // RXPFDTST_BINARY, // .RXACLCFG 3 FALSE + 1'b0, // RXVCOBUFTST_BINARY, // .RXACLCFG 2 FALSE + 1'b0, // RXDIVBUFTST_BINARY, // .RXACLCFG 1 FALSE + 1'b0 // RXVCOTST_BINARY // .RXACLCFG 0 FALSE +}; + + +GT11_SWIFT gt11_swift_1 ( + .GSR (GSR), + + .GT11_MODE(GT11_MODE_BINARY), + + .synDigCfgChnBnd1 (synDigCfgChnBnd1), + .synDigCfgChnBnd2 (synDigCfgChnBnd2), + .synDigCfgClkCor1 (synDigCfgClkCor1), + .synDigCfgClkCor2 (synDigCfgClkCor2), + .synDigCfgMisc (synDigCfgMisc), + .synDigCfgComma1 (synDigCfgComma1), + .synDigCfgComma2 (synDigCfgComma2), + .synDigCfgSynPmaFD (synDigCfgSynPmaFD), + .synDigCfgCrc (synDigCfgCrc), + .PMACFG (PMACFG), + .PMACFG2 (PMACFG2), + .RXAFECFG (RXAFECFG), + .RXAEQCFG (RXAEQCFG), + .TXCLCFG (TXCLCFG), + .TXACFG (TXACFG), + .RXACLCFG (RXACLCFG), + + .CHBONDO(CHBONDO), + .COMBUSOUT(COMBUSOUT), + .DO(DO), + .DRDY(DRDY), + .RXBUFERR(RXBUFERR), + .RXCALFAIL(RXCALFAIL), + .RXCHARISCOMMA(RXCHARISCOMMA), + .RXCHARISK(RXCHARISK), + .RXCOMMADET(RXCOMMADET), + .RXCRCOUT(RXCRCOUT), + .RXCYCLELIMIT(RXCYCLELIMIT), + .RXDATA(RXDATA), + .RXDISPERR(RXDISPERR), + .RXLOCK(RXLOCK), + .RXLOSSOFSYNC(RXLOSSOFSYNC), + .RXMCLK(RXMCLK), + .RXNOTINTABLE(RXNOTINTABLE), + .RXPCSHCLKOUT(RXPCSHCLKOUT), + .RXREALIGN(RXREALIGN), + .RXRECCLK1(RXRECCLK1), + .RXRECCLK2(RXRECCLK2), + .RXRUNDISP(RXRUNDISP), + .RXSIGDET(RXSIGDET), + .RXSTATUS(RXSTATUS), + .TX1N(TX1N), + .TX1P(TX1P), + .TXBUFERR(TXBUFERR), + .TXCALFAIL(TXCALFAIL), + .TXCRCOUT(TXCRCOUT), + .TXCYCLELIMIT(TXCYCLELIMIT), + .TXKERR(TXKERR), + .TXLOCK(TXLOCK), + .TXOUTCLK1(TXOUTCLK1), + .TXOUTCLK2(TXOUTCLK2), + .TXPCSHCLKOUT(TXPCSHCLKOUT), + .TXRUNDISP(TXRUNDISP), + .CHBONDI(CHBONDI), + .COMBUSIN(COMBUSIN), + .DADDR(DADDR), + .DCLK(DCLK), + .DEN(DEN), + .DI(DI), + .DWE(DWE), + .ENCHANSYNC(ENCHANSYNC), + .ENMCOMMAALIGN(ENMCOMMAALIGN), + .ENPCOMMAALIGN(ENPCOMMAALIGN), + .GREFCLK(GREFCLK), + .LOOPBACK(LOOPBACK), + .POWERDOWN(POWERDOWN), + .REFCLK1(REFCLK1), + .REFCLK2(REFCLK2), + .RX1N(RX1N), + .RX1P(RX1P), + .RXBLOCKSYNC64B66BUSE(RXBLOCKSYNC64B66BUSE), + .RXCLKSTABLE(RXCLKSTABLE), + .RXCOMMADETUSE(RXCOMMADETUSE), + .RXCRCCLK(RXCRCCLK), + .RXCRCDATAVALID(RXCRCDATAVALID), + .RXCRCDATAWIDTH(RXCRCDATAWIDTH), + .RXCRCIN(RXCRCIN), + .RXCRCINIT(RXCRCINIT), + .RXCRCINTCLK(RXCRCINTCLK), + .RXCRCPD(RXCRCPD), + .RXCRCRESET(RXCRCRESET), + .RXDATAWIDTH(RXDATAWIDTH), + .RXDEC64B66BUSE(RXDEC64B66BUSE), + .RXDEC8B10BUSE(RXDEC8B10BUSE), + .RXDESCRAM64B66BUSE(RXDESCRAM64B66BUSE), + .RXIGNOREBTF(RXIGNOREBTF), + .RXINTDATAWIDTH(RXINTDATAWIDTH), + .RXPMARESET(RXPMARESET), + .RXPOLARITY(RXPOLARITY), + .RXRESET(RXRESET), + .RXSLIDE(RXSLIDE), + .RXSYNC(RXSYNC), + .RXUSRCLK(RXUSRCLK), + .RXUSRCLK2(RXUSRCLK2), + .TXBYPASS8B10B(TXBYPASS8B10B), + .TXCHARDISPMODE(TXCHARDISPMODE), + .TXCHARDISPVAL(TXCHARDISPVAL), + .TXCHARISK(TXCHARISK), + .TXCLKSTABLE(TXCLKSTABLE), + .TXCRCCLK(TXCRCCLK), + .TXCRCDATAVALID(TXCRCDATAVALID), + .TXCRCDATAWIDTH(TXCRCDATAWIDTH), + .TXCRCIN(TXCRCIN), + .TXCRCINIT(TXCRCINIT), + .TXCRCINTCLK(TXCRCINTCLK), + .TXCRCPD(TXCRCPD), + .TXCRCRESET(TXCRCRESET), + .TXDATA(TXDATA), + .TXDATAWIDTH(TXDATAWIDTH), + .TXENC64B66BUSE(TXENC64B66BUSE), + .TXENC8B10BUSE(TXENC8B10BUSE), + .TXENOOB(TXENOOB), + .TXGEARBOX64B66BUSE(TXGEARBOX64B66BUSE), + .TXINHIBIT(TXINHIBIT), + .TXINTDATAWIDTH(TXINTDATAWIDTH), + .TXPMARESET(TXPMARESET), + .TXPOLARITY(TXPOLARITY), + .TXRESET(TXRESET), + .TXSCRAM64B66BUSE(TXSCRAM64B66BUSE), + .TXSYNC(TXSYNC), + .TXUSRCLK(TXUSRCLK), + .TXUSRCLK2(TXUSRCLK2) +); + +specify + (DCLK => DO) = (100, 100); + (DCLK => DRDY) = (100, 100); + (RXCRCINTCLK => RXCRCOUT) = (100, 100); + (RXUSRCLK => CHBONDO) = (100, 100); + (RXUSRCLK2 => RXBUFERR) = (100, 100); + (RXUSRCLK2 => RXCHARISCOMMA) = (100, 100); + (RXUSRCLK2 => RXCHARISK) = (100, 100); + (RXUSRCLK2 => RXCOMMADET) = (100, 100); + (RXUSRCLK2 => RXCYCLELIMIT) = (100, 100); + (RXUSRCLK2 => RXDATA) = (100, 100); + (RXUSRCLK2 => RXDISPERR) = (100, 100); + (RXUSRCLK2 => RXLOCK) = (100, 100); + (RXUSRCLK2 => RXLOSSOFSYNC) = (100, 100); + (RXUSRCLK2 => RXNOTINTABLE) = (100, 100); + (RXUSRCLK2 => RXREALIGN) = (100, 100); + (RXUSRCLK2 => RXRUNDISP) = (100, 100); + (RXUSRCLK2 => RXSIGDET) = (100, 100); + (RXUSRCLK2 => RXSTATUS) = (100, 100); + (TXCRCINTCLK => TXCRCOUT) = (100, 100); + (TXUSRCLK2 => RXCALFAIL) = (100, 100); + (TXUSRCLK2 => TXBUFERR) = (100, 100); + (TXUSRCLK2 => TXCALFAIL) = (100, 100); + (TXUSRCLK2 => TXCYCLELIMIT) = (100, 100); + (TXUSRCLK2 => TXKERR) = (100, 100); + (TXUSRCLK2 => TXLOCK) = (100, 100); + (TXUSRCLK2 => TXRUNDISP) = (100, 100); + specparam PATHPULSE$ = 0; +endspecify +endmodule diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/GT11CLK.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/GT11CLK.v new file mode 100644 index 0000000..2295040 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/GT11CLK.v @@ -0,0 +1,126 @@ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / 11-Gigabit Transceiver MUX +// /___/ /\ Filename : GT11CLK.v +// \ \ / \ Timestamp : Fri Jun 18 10:57:01 PDT 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. + + +`timescale 1 ps / 1 ps + +module GT11CLK ( + SYNCLK1OUT, + SYNCLK2OUT, + MGTCLKN, + MGTCLKP, + REFCLK, + RXBCLK, + SYNCLK1IN, + SYNCLK2IN +); + +parameter REFCLKSEL = "MGTCLK"; +parameter SYNCLK1OUTEN = "ENABLE"; +parameter SYNCLK2OUTEN = "DISABLE"; + + +output SYNCLK1OUT; +output SYNCLK2OUT; + +input MGTCLKN; +input MGTCLKP; +input REFCLK; +input RXBCLK; +input SYNCLK1IN; +input SYNCLK2IN; + +reg [0:0] SYNCLK1OUTEN_BINARY; +reg [0:0] SYNCLK2OUTEN_BINARY; +reg [3:0] REFCLKSEL_BINARY; + +reg notifier; + +reg mgtclk_out; +reg mux_out; + + +initial begin + case (REFCLKSEL) + "MGTCLK" : REFCLKSEL_BINARY <= 4'b1111; + "SYNCLK1IN" : REFCLKSEL_BINARY <= 4'b0010; + "SYNCLK2IN" : REFCLKSEL_BINARY <= 4'b0100; + "REFCLK" : REFCLKSEL_BINARY <= 4'b0110; + "RXBCLK" : REFCLKSEL_BINARY <= 4'b0000; + default : begin + $display("Attribute Syntax Error : The Attribute REFCLKSEL on GT11CLK instance %m is set to %s. Legal values for this attribute are MGTCLK, SYNCLK1IN, SYNCLK2IN, REFCLK or RXBCLK.", REFCLKSEL); + $finish; + end + endcase + + case (SYNCLK1OUTEN) + "ENABLE" : SYNCLK1OUTEN_BINARY <= 1'b1; + "DISABLE" : SYNCLK1OUTEN_BINARY <= 1'b0; + default : begin + $display("Attribute Syntax Error : The Attribute SYNCLK1OUTEN on GT11CLK instance %m is set to %s. Legal values for this attribute are ENABLE or DISABLE.", SYNCLK1OUTEN); + $finish; + end + endcase + + case (SYNCLK2OUTEN) + "ENABLE" : SYNCLK2OUTEN_BINARY <= 1'b1; + "DISABLE" : SYNCLK2OUTEN_BINARY <= 1'b0; + default : begin + $display("Attribute Syntax Error : The Attribute SYNCLK2OUTEN on GT11CLK instance %m is set to %s. Legal values for this attribute are ENABLE or DISABLE.", SYNCLK2OUTEN); + $finish; + end + endcase + +end + + always @(MGTCLKN or MGTCLKP) begin + if (MGTCLKP == 1'b1 && MGTCLKN == 1'b0) + mgtclk_out <= MGTCLKP; + else if (MGTCLKP == 1'b0 && MGTCLKN == 1'b1) + mgtclk_out <= MGTCLKP; + end + + always @(REFCLK) begin + if (REFCLKSEL == "REFCLK") + mux_out <= REFCLK; + end + + always @(mgtclk_out) begin + if (REFCLKSEL == "MGTCLK") + mux_out <= mgtclk_out; + end + + always @(RXBCLK) begin + if (REFCLKSEL == "RXBCLK") + mux_out <= RXBCLK; + end + + always @(SYNCLK1IN) begin + if (REFCLKSEL == "SYNCLK1IN") + mux_out <= SYNCLK1IN; + end + + always @(SYNCLK2IN) begin + if (REFCLKSEL == "SYNCLK2IN") + mux_out <= SYNCLK2IN; + end + + + bufif1 (SYNCLK1OUT, mux_out, SYNCLK1OUTEN_BINARY); + bufif1 (SYNCLK2OUT, mux_out, SYNCLK2OUTEN_BINARY); + +endmodule diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/GT11CLK_MGT.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/GT11CLK_MGT.v new file mode 100644 index 0000000..909551f --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/GT11CLK_MGT.v @@ -0,0 +1,73 @@ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / 11-Gigabit Transceiver MUX +// /___/ /\ Filename : GT11CLK_MGT.v +// \ \ / \ Timestamp : Fri Jun 18 10:57:01 PDT 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. + +`timescale 1 ps / 1 ps + +module GT11CLK_MGT ( + SYNCLK1OUT, + SYNCLK2OUT, + MGTCLKN, + MGTCLKP +); + +parameter SYNCLK1OUTEN = "ENABLE"; +parameter SYNCLK2OUTEN = "DISABLE"; + + +output SYNCLK1OUT; +output SYNCLK2OUT; + +input MGTCLKN; +input MGTCLKP; + +reg [0:0] SYNCLK1OUTEN_BINARY; +reg [0:0] SYNCLK2OUTEN_BINARY; + +reg mgtclk_out; + +initial begin + case (SYNCLK1OUTEN) + "ENABLE" : SYNCLK1OUTEN_BINARY <= 1'b1; + "DISABLE" : SYNCLK1OUTEN_BINARY <= 1'b0; + default : begin + $display("Attribute Syntax Error : The Attribute SYNCLK1OUTEN on GT11CLK_MGT instance %m is set to %s. Legal values for this attribute are ENABLE or DISABLE.", SYNCLK1OUTEN); + $finish; + end + endcase + + case (SYNCLK2OUTEN) + "ENABLE" : SYNCLK2OUTEN_BINARY <= 1'b1; + "DISABLE" : SYNCLK2OUTEN_BINARY <= 1'b0; + default : begin + $display("Attribute Syntax Error : The Attribute SYNCLK2OUTEN on GT11CLK_MGT instance %m is set to %s. Legal values for this attribute are ENABLE or DISABLE.", SYNCLK2OUTEN); + $finish; + end + endcase + +end + + always @(MGTCLKN or MGTCLKP) begin + if (MGTCLKP == 1'b1 && MGTCLKN == 1'b0) + mgtclk_out <= MGTCLKP; + else if (MGTCLKP == 1'b0 && MGTCLKN == 1'b1) + mgtclk_out <= MGTCLKP; + end + + bufif1 (SYNCLK1OUT, mgtclk_out, SYNCLK1OUTEN_BINARY); + bufif1 (SYNCLK2OUT, mgtclk_out, SYNCLK2OUTEN_BINARY); +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/GT11_CUSTOM.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/GT11_CUSTOM.v new file mode 100644 index 0000000..5f77195 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/GT11_CUSTOM.v @@ -0,0 +1,690 @@ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / 11-Gigabit Transceiver for High-Speed I/O CUSTOM Simulation Model +// /___/ /\ Filename : GT11_CUSTOM.v +// \ \ / \ Timestamp : Fri Jun 18 10:57:01 PDT 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/16/05 - Changed default values for some parameters and removed two parameters. Fixed CR#207101. +// 08/08/05 - Changed default parameter values for some parameters. Added POWER_ENABLE parameter. (CR 214282). +// 02/22/06 - CR#226003 - Added integer, real parameter type +// 02/28/06 - CR#226322 - Addition of new parameters and change of default values for some parameters. +// End Revision + +`timescale 1 ps / 1 ps + +module GT11_CUSTOM ( + CHBONDO, + DO, + DRDY, + RXBUFERR, + RXCALFAIL, + RXCHARISCOMMA, + RXCHARISK, + RXCOMMADET, + RXCRCOUT, + RXCYCLELIMIT, + RXDATA, + RXDISPERR, + RXLOCK, + RXLOSSOFSYNC, + RXMCLK, + RXNOTINTABLE, + RXPCSHCLKOUT, + RXREALIGN, + RXRECCLK1, + RXRECCLK2, + RXRUNDISP, + RXSIGDET, + RXSTATUS, + TX1N, + TX1P, + TXBUFERR, + TXCALFAIL, + TXCRCOUT, + TXCYCLELIMIT, + TXKERR, + TXLOCK, + TXOUTCLK1, + TXOUTCLK2, + TXPCSHCLKOUT, + TXRUNDISP, + CHBONDI, + DADDR, + DCLK, + DEN, + DI, + DWE, + ENCHANSYNC, + ENMCOMMAALIGN, + ENPCOMMAALIGN, + GREFCLK, + LOOPBACK, + POWERDOWN, + REFCLK1, + REFCLK2, + RX1N, + RX1P, + RXBLOCKSYNC64B66BUSE, + RXCLKSTABLE, + RXCOMMADETUSE, + RXCRCCLK, + RXCRCDATAVALID, + RXCRCDATAWIDTH, + RXCRCIN, + RXCRCINIT, + RXCRCINTCLK, + RXCRCPD, + RXCRCRESET, + RXDATAWIDTH, + RXDEC64B66BUSE, + RXDEC8B10BUSE, + RXDESCRAM64B66BUSE, + RXIGNOREBTF, + RXINTDATAWIDTH, + RXPMARESET, + RXPOLARITY, + RXRESET, + RXSLIDE, + RXSYNC, + RXUSRCLK, + RXUSRCLK2, + TXBYPASS8B10B, + TXCHARDISPMODE, + TXCHARDISPVAL, + TXCHARISK, + TXCLKSTABLE, + TXCRCCLK, + TXCRCDATAVALID, + TXCRCDATAWIDTH, + TXCRCIN, + TXCRCINIT, + TXCRCINTCLK, + TXCRCPD, + TXCRCRESET, + TXDATA, + TXDATAWIDTH, + TXENC64B66BUSE, + TXENC8B10BUSE, + TXENOOB, + TXGEARBOX64B66BUSE, + TXINHIBIT, + TXINTDATAWIDTH, + TXPMARESET, + TXPOLARITY, + TXRESET, + TXSCRAM64B66BUSE, + TXSYNC, + TXUSRCLK, + TXUSRCLK2 +); + +parameter BANDGAPSEL = "FALSE"; +parameter BIASRESSEL = "FALSE"; +parameter CCCB_ARBITRATOR_DISABLE = "FALSE"; +parameter CHAN_BOND_MODE = "NONE"; +parameter CHAN_BOND_ONE_SHOT = "FALSE"; +parameter CHAN_BOND_SEQ_1_1 = 11'b00000000000; +parameter CHAN_BOND_SEQ_1_2 = 11'b00000000000; +parameter CHAN_BOND_SEQ_1_3 = 11'b00000000000; +parameter CHAN_BOND_SEQ_1_4 = 11'b00000000000; +parameter CHAN_BOND_SEQ_1_MASK = 4'b1110; +parameter CHAN_BOND_SEQ_2_1 = 11'b00000000000; +parameter CHAN_BOND_SEQ_2_2 = 11'b00000000000; +parameter CHAN_BOND_SEQ_2_3 = 11'b00000000000; +parameter CHAN_BOND_SEQ_2_4 = 11'b00000000000; +parameter CHAN_BOND_SEQ_2_MASK = 4'b1110; +parameter CHAN_BOND_SEQ_2_USE = "FALSE"; +parameter CLK_CORRECT_USE = "FALSE"; +parameter CLK_COR_8B10B_DE = "FALSE"; +parameter CLK_COR_SEQ_1_1 = 11'b00000000000; +parameter CLK_COR_SEQ_1_2 = 11'b00000000000; +parameter CLK_COR_SEQ_1_3 = 11'b00000000000; +parameter CLK_COR_SEQ_1_4 = 11'b00000000000; +parameter CLK_COR_SEQ_1_MASK = 4'b1110; +parameter CLK_COR_SEQ_2_1 = 11'b00000000000; +parameter CLK_COR_SEQ_2_2 = 11'b00000000000; +parameter CLK_COR_SEQ_2_3 = 11'b00000000000; +parameter CLK_COR_SEQ_2_4 = 11'b00000000000; +parameter CLK_COR_SEQ_2_MASK = 4'b1110; +parameter CLK_COR_SEQ_2_USE = "FALSE"; +parameter CLK_COR_SEQ_DROP = "FALSE"; +parameter COMMA32 = "FALSE"; +parameter COMMA_10B_MASK = 10'h3FF; +parameter CYCLE_LIMIT_SEL = 2'b00; +parameter DCDR_FILTER = 3'b010; +parameter DEC_MCOMMA_DETECT = "TRUE"; +parameter DEC_PCOMMA_DETECT = "TRUE"; +parameter DEC_VALID_COMMA_ONLY = "TRUE"; +parameter DIGRX_FWDCLK = 2'b00; +parameter DIGRX_SYNC_MODE = "FALSE"; +parameter ENABLE_DCDR = "FALSE"; +parameter FDET_HYS_CAL = 3'b010; +parameter FDET_HYS_SEL = 3'b100; +parameter FDET_LCK_CAL = 3'b100; +parameter FDET_LCK_SEL = 3'b001; +parameter IREFBIASMODE = 2'b11; +parameter LOOPCAL_WAIT = 2'b00; +parameter MCOMMA_32B_VALUE = 32'h00000000; +parameter MCOMMA_DETECT = "TRUE"; +parameter OPPOSITE_SELECT = "FALSE"; +parameter PCOMMA_32B_VALUE = 32'h00000000; +parameter PCOMMA_DETECT = "TRUE"; +parameter PCS_BIT_SLIP = "FALSE"; +parameter PMACLKENABLE = "TRUE"; +parameter PMACOREPWRENABLE = "TRUE"; +parameter PMAIREFTRIM = 4'b0111; +parameter PMAVBGCTRL = 5'b00000; +parameter PMAVREFTRIM = 4'b0111; +parameter PMA_BIT_SLIP = "FALSE"; +parameter POWER_ENABLE = "TRUE"; +parameter REPEATER = "FALSE"; +parameter RXACTST = "FALSE"; +parameter RXAFEEQ = 9'b000000000; +parameter RXAFEPD = "FALSE"; +parameter RXAFETST = "FALSE"; +parameter RXAPD = "FALSE"; +parameter RXAREGCTRL = 5'b00000; +parameter RXASYNCDIVIDE = 2'b11; +parameter RXBY_32 = "FALSE"; +parameter RXCDRLOS = 6'b000000; +parameter RXCLK0_FORCE_PMACLK = "FALSE"; +parameter RXCLKMODE = 6'b110001; +parameter RXCLMODE = 2'b00; +parameter RXCMADJ = 2'b01; +parameter RXCPSEL = "TRUE"; +parameter RXCPTST = "FALSE"; +parameter RXCRCCLOCKDOUBLE = "FALSE"; +parameter RXCRCENABLE = "FALSE"; +parameter RXCRCINITVAL = 32'h00000000; +parameter RXCRCINVERTGEN = "FALSE"; +parameter RXCRCSAMECLOCK = "FALSE"; +parameter RXCTRL1 = 10'h200; +parameter RXCYCLE_LIMIT_SEL = 2'b00; +parameter RXDATA_SEL = 2'b00; +parameter RXDCCOUPLE = "FALSE"; +parameter RXDIGRESET = "FALSE"; +parameter RXDIGRX = "FALSE"; +parameter RXEQ = 64'h4000000000000000; +parameter RXFDCAL_CLOCK_DIVIDE = "NONE"; +parameter RXFDET_HYS_CAL = 3'b010; +parameter RXFDET_HYS_SEL = 3'b100; +parameter RXFDET_LCK_CAL = 3'b100; +parameter RXFDET_LCK_SEL = 3'b001; +parameter RXFECONTROL1 = 2'b00; +parameter RXFECONTROL2 = 3'b000; +parameter RXFETUNE = 2'b01; +parameter RXLB = "FALSE"; +parameter RXLKADJ = 5'b00000; +parameter RXLKAPD = "FALSE"; +parameter RXLOOPCAL_WAIT = 2'b00; +parameter RXLOOPFILT = 4'b0111; +parameter RXMODE = 6'b000000; +parameter RXPD = "FALSE"; +parameter RXPDDTST = "TRUE"; +parameter RXPMACLKSEL = "REFCLK1"; +parameter RXRCPADJ = 3'b011; +parameter RXRCPPD = "FALSE"; +parameter RXRECCLK1_USE_SYNC = "FALSE"; +parameter RXRIBADJ = 2'b11; +parameter RXRPDPD = "FALSE"; +parameter RXRSDPD = "FALSE"; +parameter RXSLOWDOWN_CAL = 2'b00; +parameter RXTUNE = 13'h0000; +parameter RXVCODAC_INIT = 10'b1010000000; +parameter RXVCO_CTRL_ENABLE = "FALSE"; +parameter RX_BUFFER_USE = "TRUE"; +parameter RX_CLOCK_DIVIDER = 2'b00; +parameter SAMPLE_8X = "FALSE"; +parameter SLOWDOWN_CAL = 2'b00; +parameter TXABPMACLKSEL = "REFCLK1"; +parameter TXAPD = "FALSE"; +parameter TXAREFBIASSEL = "TRUE"; +parameter TXASYNCDIVIDE = 2'b11; +parameter TXCLK0_FORCE_PMACLK = "FALSE"; +parameter TXCLKMODE = 4'b1001; +parameter TXCLMODE = 2'b00; +parameter TXCPSEL = "TRUE"; +parameter TXCRCCLOCKDOUBLE = "FALSE"; +parameter TXCRCENABLE = "FALSE"; +parameter TXCRCINITVAL = 32'h00000000; +parameter TXCRCINVERTGEN = "FALSE"; +parameter TXCRCSAMECLOCK = "FALSE"; +parameter TXCTRL1 = 10'h200; +parameter TXDATA_SEL = 2'b00; +parameter TXDAT_PRDRV_DAC = 3'b111; +parameter TXDAT_TAP_DAC = 5'b10110; +parameter TXDIGPD = "FALSE"; +parameter TXFDCAL_CLOCK_DIVIDE = "NONE"; +parameter TXHIGHSIGNALEN = "TRUE"; +parameter TXLOOPFILT = 4'b0111; +parameter TXLVLSHFTPD = "FALSE"; +parameter TXOUTCLK1_USE_SYNC = "FALSE"; +parameter TXPD = "FALSE"; +parameter TXPHASESEL = "FALSE"; +parameter TXPOST_PRDRV_DAC = 3'b111; +parameter TXPOST_TAP_DAC = 5'b01110; +parameter TXPOST_TAP_PD = "TRUE"; +parameter TXPRE_PRDRV_DAC = 3'b111; +parameter TXPRE_TAP_DAC = 5'b00000; +parameter TXPRE_TAP_PD = "TRUE"; +parameter TXSLEWRATE = "FALSE"; +parameter TXTERMTRIM = 4'b1100; +parameter TXTUNE = 13'h0000; +parameter TX_BUFFER_USE = "TRUE"; +parameter TX_CLOCK_DIVIDER = 2'b00; +parameter VCODAC_INIT = 10'b1010000000; +parameter VCO_CTRL_ENABLE = "FALSE"; +parameter VREFBIASMODE = 2'b11; +parameter integer ALIGN_COMMA_WORD = 4; +parameter integer CHAN_BOND_LIMIT = 16; +parameter integer CHAN_BOND_SEQ_LEN = 1; +parameter integer CLK_COR_MAX_LAT = 48; +parameter integer CLK_COR_MIN_LAT = 36; +parameter integer CLK_COR_SEQ_LEN = 1; +parameter integer RXOUTDIV2SEL = 1; +parameter integer RXPLLNDIVSEL = 8; +parameter integer RXUSRDIVISOR = 1; +parameter integer SH_CNT_MAX = 64; +parameter integer SH_INVALID_CNT_MAX = 16; +parameter integer TXOUTDIV2SEL = 1; +parameter integer TXPLLNDIVSEL = 8; + + +output DRDY; +output RXBUFERR; +output RXCALFAIL; +output RXCOMMADET; +output RXCYCLELIMIT; +output RXLOCK; +output RXMCLK; +output RXPCSHCLKOUT; +output RXREALIGN; +output RXRECCLK1; +output RXRECCLK2; +output RXSIGDET; +output TX1N; +output TX1P; +output TXBUFERR; +output TXCALFAIL; +output TXCYCLELIMIT; +output TXLOCK; +output TXOUTCLK1; +output TXOUTCLK2; +output TXPCSHCLKOUT; +output [15:0] DO; +output [1:0] RXLOSSOFSYNC; +output [31:0] RXCRCOUT; +output [31:0] TXCRCOUT; +output [4:0] CHBONDO; +output [5:0] RXSTATUS; +output [63:0] RXDATA; +output [7:0] RXCHARISCOMMA; +output [7:0] RXCHARISK; +output [7:0] RXDISPERR; +output [7:0] RXNOTINTABLE; +output [7:0] RXRUNDISP; +output [7:0] TXKERR; +output [7:0] TXRUNDISP; + +input DCLK; +input DEN; +input DWE; +input ENCHANSYNC; +input ENMCOMMAALIGN; +input ENPCOMMAALIGN; +input GREFCLK; +input POWERDOWN; +input REFCLK1; +input REFCLK2; +input RX1N; +input RX1P; +input RXBLOCKSYNC64B66BUSE; +input RXCLKSTABLE; +input RXCOMMADETUSE; +input RXCRCCLK; +input RXCRCDATAVALID; +input RXCRCINIT; +input RXCRCINTCLK; +input RXCRCPD; +input RXCRCRESET; +input RXDEC64B66BUSE; +input RXDEC8B10BUSE; +input RXDESCRAM64B66BUSE; +input RXIGNOREBTF; +input RXPMARESET; +input RXPOLARITY; +input RXRESET; +input RXSLIDE; +input RXSYNC; +input RXUSRCLK2; +input RXUSRCLK; +input TXCLKSTABLE; +input TXCRCCLK; +input TXCRCDATAVALID; +input TXCRCINIT; +input TXCRCINTCLK; +input TXCRCPD; +input TXCRCRESET; +input TXENC64B66BUSE; +input TXENC8B10BUSE; +input TXENOOB; +input TXGEARBOX64B66BUSE; +input TXINHIBIT; +input TXPMARESET; +input TXPOLARITY; +input TXRESET; +input TXSCRAM64B66BUSE; +input TXSYNC; +input TXUSRCLK2; +input TXUSRCLK; +input [15:0] DI; +input [1:0] LOOPBACK; +input [1:0] RXDATAWIDTH; +input [1:0] RXINTDATAWIDTH; +input [1:0] TXDATAWIDTH; +input [1:0] TXINTDATAWIDTH; +input [2:0] RXCRCDATAWIDTH; +input [2:0] TXCRCDATAWIDTH; +input [4:0] CHBONDI; +input [63:0] RXCRCIN; +input [63:0] TXCRCIN; +input [63:0] TXDATA; +input [7:0] DADDR; +input [7:0] TXBYPASS8B10B; +input [7:0] TXCHARDISPMODE; +input [7:0] TXCHARDISPVAL; +input [7:0] TXCHARISK; + +wire [15:0] OPEN_COMBUSOUT; + +GT11 gt11_1 ( + .CHBONDI (CHBONDI), + .CHBONDO (CHBONDO), + .COMBUSIN (16'b0), + .COMBUSOUT (OPEN_COMBUSOUT), + .DADDR (DADDR), + .DCLK (DCLK), + .DEN (DEN), + .DI (DI), + .DO (DO), + .DRDY (DRDY), + .DWE (DWE), + .ENCHANSYNC (ENCHANSYNC), + .ENMCOMMAALIGN (ENMCOMMAALIGN), + .ENPCOMMAALIGN (ENPCOMMAALIGN), + .GREFCLK (GREFCLK), + .LOOPBACK (LOOPBACK), + .POWERDOWN (POWERDOWN), + .REFCLK1 (REFCLK1), + .REFCLK2 (REFCLK2), + .RX1N (RX1N), + .RX1P (RX1P), + .RXBLOCKSYNC64B66BUSE (RXBLOCKSYNC64B66BUSE), + .RXBUFERR (RXBUFERR), + .RXCALFAIL (RXCALFAIL), + .RXCHARISCOMMA (RXCHARISCOMMA), + .RXCHARISK (RXCHARISK), + .RXCLKSTABLE (RXCLKSTABLE), + .RXCOMMADET (RXCOMMADET), + .RXCOMMADETUSE (RXCOMMADETUSE), + .RXCRCCLK (RXCRCCLK), + .RXCRCDATAVALID (RXCRCDATAVALID), + .RXCRCDATAWIDTH (RXCRCDATAWIDTH), + .RXCRCIN (RXCRCIN), + .RXCRCINIT (RXCRCINIT), + .RXCRCINTCLK (RXCRCINTCLK), + .RXCRCOUT (RXCRCOUT), + .RXCRCPD (RXCRCPD), + .RXCRCRESET (RXCRCRESET), + .RXCYCLELIMIT (RXCYCLELIMIT), + .RXDATA (RXDATA), + .RXDATAWIDTH (RXDATAWIDTH), + .RXDEC64B66BUSE (RXDEC64B66BUSE), + .RXDEC8B10BUSE (RXDEC8B10BUSE), + .RXDESCRAM64B66BUSE (RXDESCRAM64B66BUSE), + .RXDISPERR (RXDISPERR), + .RXIGNOREBTF (RXIGNOREBTF), + .RXINTDATAWIDTH (RXINTDATAWIDTH), + .RXLOCK (RXLOCK), + .RXLOSSOFSYNC (RXLOSSOFSYNC), + .RXMCLK (RXMCLK), + .RXNOTINTABLE (RXNOTINTABLE), + .RXPCSHCLKOUT (RXPCSHCLKOUT), + .RXPMARESET (RXPMARESET), + .RXPOLARITY (RXPOLARITY), + .RXREALIGN (RXREALIGN), + .RXRECCLK1 (RXRECCLK1), + .RXRECCLK2 (RXRECCLK2), + .RXRESET (RXRESET), + .RXRUNDISP (RXRUNDISP), + .RXSIGDET (RXSIGDET), + .RXSLIDE (RXSLIDE), + .RXSTATUS (RXSTATUS), + .RXSYNC (RXSYNC), + .RXUSRCLK (RXUSRCLK), + .RXUSRCLK2 (RXUSRCLK2), + .TX1N (TX1N), + .TX1P (TX1P), + .TXBUFERR (TXBUFERR), + .TXBYPASS8B10B (TXBYPASS8B10B), + .TXCALFAIL (TXCALFAIL), + .TXCHARDISPMODE (TXCHARDISPMODE), + .TXCHARDISPVAL (TXCHARDISPVAL), + .TXCHARISK (TXCHARISK), + .TXCLKSTABLE (TXCLKSTABLE), + .TXCRCCLK (TXCRCCLK), + .TXCRCDATAVALID (TXCRCDATAVALID), + .TXCRCDATAWIDTH (TXCRCDATAWIDTH), + .TXCRCIN (TXCRCIN), + .TXCRCINIT (TXCRCINIT), + .TXCRCINTCLK (TXCRCINTCLK), + .TXCRCOUT (TXCRCOUT), + .TXCRCPD (TXCRCPD), + .TXCRCRESET (TXCRCRESET), + .TXCYCLELIMIT (TXCYCLELIMIT), + .TXDATA (TXDATA), + .TXDATAWIDTH (TXDATAWIDTH), + .TXENC64B66BUSE (TXENC64B66BUSE), + .TXENC8B10BUSE (TXENC8B10BUSE), + .TXENOOB (TXENOOB), + .TXGEARBOX64B66BUSE (TXGEARBOX64B66BUSE), + .TXINHIBIT (TXINHIBIT), + .TXINTDATAWIDTH (TXINTDATAWIDTH), + .TXKERR (TXKERR), + .TXLOCK (TXLOCK), + .TXOUTCLK1 (TXOUTCLK1), + .TXOUTCLK2 (TXOUTCLK2), + .TXPCSHCLKOUT (TXPCSHCLKOUT), + .TXPMARESET (TXPMARESET), + .TXPOLARITY (TXPOLARITY), + .TXRESET (TXRESET), + .TXRUNDISP (TXRUNDISP), + .TXSCRAM64B66BUSE (TXSCRAM64B66BUSE), + .TXSYNC (TXSYNC), + .TXUSRCLK (TXUSRCLK), + .TXUSRCLK2 (TXUSRCLK2) +); + +defparam gt11_1.ALIGN_COMMA_WORD = ALIGN_COMMA_WORD; +defparam gt11_1.BANDGAPSEL = BANDGAPSEL; +defparam gt11_1.BIASRESSEL = BIASRESSEL; +defparam gt11_1.CCCB_ARBITRATOR_DISABLE = CCCB_ARBITRATOR_DISABLE; +defparam gt11_1.CHAN_BOND_LIMIT = CHAN_BOND_LIMIT; +defparam gt11_1.CHAN_BOND_MODE = CHAN_BOND_MODE; +defparam gt11_1.CHAN_BOND_ONE_SHOT = CHAN_BOND_ONE_SHOT; +defparam gt11_1.CHAN_BOND_SEQ_1_1 = CHAN_BOND_SEQ_1_1; +defparam gt11_1.CHAN_BOND_SEQ_1_2 = CHAN_BOND_SEQ_1_2; +defparam gt11_1.CHAN_BOND_SEQ_1_3 = CHAN_BOND_SEQ_1_3; +defparam gt11_1.CHAN_BOND_SEQ_1_4 = CHAN_BOND_SEQ_1_4; +defparam gt11_1.CHAN_BOND_SEQ_1_MASK = CHAN_BOND_SEQ_1_MASK; +defparam gt11_1.CHAN_BOND_SEQ_2_1 = CHAN_BOND_SEQ_2_1; +defparam gt11_1.CHAN_BOND_SEQ_2_2 = CHAN_BOND_SEQ_2_2; +defparam gt11_1.CHAN_BOND_SEQ_2_3 = CHAN_BOND_SEQ_2_3; +defparam gt11_1.CHAN_BOND_SEQ_2_4 = CHAN_BOND_SEQ_2_4; +defparam gt11_1.CHAN_BOND_SEQ_2_MASK = CHAN_BOND_SEQ_2_MASK; +defparam gt11_1.CHAN_BOND_SEQ_2_USE = CHAN_BOND_SEQ_2_USE; +defparam gt11_1.CHAN_BOND_SEQ_LEN = CHAN_BOND_SEQ_LEN; +defparam gt11_1.CLK_CORRECT_USE = CLK_CORRECT_USE; +defparam gt11_1.CLK_COR_8B10B_DE = CLK_COR_8B10B_DE; +defparam gt11_1.CLK_COR_MAX_LAT = CLK_COR_MAX_LAT; +defparam gt11_1.CLK_COR_MIN_LAT = CLK_COR_MIN_LAT; +defparam gt11_1.CLK_COR_SEQ_1_1 = CLK_COR_SEQ_1_1; +defparam gt11_1.CLK_COR_SEQ_1_2 = CLK_COR_SEQ_1_2; +defparam gt11_1.CLK_COR_SEQ_1_3 = CLK_COR_SEQ_1_3; +defparam gt11_1.CLK_COR_SEQ_1_4 = CLK_COR_SEQ_1_4; +defparam gt11_1.CLK_COR_SEQ_1_MASK = CLK_COR_SEQ_1_MASK; +defparam gt11_1.CLK_COR_SEQ_2_1 = CLK_COR_SEQ_2_1; +defparam gt11_1.CLK_COR_SEQ_2_2 = CLK_COR_SEQ_2_2; +defparam gt11_1.CLK_COR_SEQ_2_3 = CLK_COR_SEQ_2_3; +defparam gt11_1.CLK_COR_SEQ_2_4 = CLK_COR_SEQ_2_4; +defparam gt11_1.CLK_COR_SEQ_2_MASK = CLK_COR_SEQ_2_MASK; +defparam gt11_1.CLK_COR_SEQ_2_USE = CLK_COR_SEQ_2_USE; +defparam gt11_1.CLK_COR_SEQ_DROP = CLK_COR_SEQ_DROP; +defparam gt11_1.CLK_COR_SEQ_LEN = CLK_COR_SEQ_LEN; +defparam gt11_1.COMMA32 = COMMA32; +defparam gt11_1.COMMA_10B_MASK = COMMA_10B_MASK; +defparam gt11_1.CYCLE_LIMIT_SEL = CYCLE_LIMIT_SEL; +defparam gt11_1.DCDR_FILTER = DCDR_FILTER; +defparam gt11_1.DEC_MCOMMA_DETECT = DEC_MCOMMA_DETECT; +defparam gt11_1.DEC_PCOMMA_DETECT = DEC_PCOMMA_DETECT; +defparam gt11_1.DEC_VALID_COMMA_ONLY = DEC_VALID_COMMA_ONLY; +defparam gt11_1.DIGRX_FWDCLK = DIGRX_FWDCLK; +defparam gt11_1.DIGRX_SYNC_MODE = DIGRX_SYNC_MODE; +defparam gt11_1.ENABLE_DCDR = ENABLE_DCDR; +defparam gt11_1.FDET_HYS_CAL = FDET_HYS_CAL; +defparam gt11_1.FDET_HYS_SEL = FDET_HYS_SEL; +defparam gt11_1.FDET_LCK_CAL = FDET_LCK_CAL; +defparam gt11_1.FDET_LCK_SEL = FDET_LCK_SEL; +defparam gt11_1.GT11_MODE = "SINGLE"; +defparam gt11_1.IREFBIASMODE = IREFBIASMODE; +defparam gt11_1.LOOPCAL_WAIT = LOOPCAL_WAIT; +defparam gt11_1.MCOMMA_32B_VALUE = MCOMMA_32B_VALUE; +defparam gt11_1.MCOMMA_DETECT = MCOMMA_DETECT; +defparam gt11_1.OPPOSITE_SELECT = OPPOSITE_SELECT; +defparam gt11_1.PCOMMA_32B_VALUE = PCOMMA_32B_VALUE; +defparam gt11_1.PCOMMA_DETECT = PCOMMA_DETECT; +defparam gt11_1.PCS_BIT_SLIP = PCS_BIT_SLIP; +defparam gt11_1.PMACLKENABLE = PMACLKENABLE; +defparam gt11_1.PMACOREPWRENABLE = PMACOREPWRENABLE; +defparam gt11_1.PMAIREFTRIM = PMAIREFTRIM; +defparam gt11_1.PMAVBGCTRL = PMAVBGCTRL; +defparam gt11_1.PMAVREFTRIM = PMAVREFTRIM; +defparam gt11_1.PMA_BIT_SLIP = PMA_BIT_SLIP; +defparam gt11_1.POWER_ENABLE = POWER_ENABLE; +defparam gt11_1.REPEATER = REPEATER; +defparam gt11_1.RXACTST = RXACTST; +defparam gt11_1.RXAFEEQ = RXAFEEQ; +defparam gt11_1.RXAFEPD = RXAFEPD; +defparam gt11_1.RXAFETST = RXAFETST; +defparam gt11_1.RXAPD = RXAPD; +defparam gt11_1.RXAREGCTRL = RXAREGCTRL; +defparam gt11_1.RXASYNCDIVIDE = RXASYNCDIVIDE; +defparam gt11_1.RXBY_32 = RXBY_32; +defparam gt11_1.RXCDRLOS = RXCDRLOS; +defparam gt11_1.RXCLK0_FORCE_PMACLK = RXCLK0_FORCE_PMACLK; +defparam gt11_1.RXCLKMODE = RXCLKMODE; +defparam gt11_1.RXCLMODE = RXCLMODE; +defparam gt11_1.RXCMADJ = RXCMADJ; +defparam gt11_1.RXCPSEL = RXCPSEL; +defparam gt11_1.RXCPTST = RXCPTST; +defparam gt11_1.RXCRCCLOCKDOUBLE = RXCRCCLOCKDOUBLE; +defparam gt11_1.RXCRCENABLE = RXCRCENABLE; +defparam gt11_1.RXCRCINITVAL = RXCRCINITVAL; +defparam gt11_1.RXCRCINVERTGEN = RXCRCINVERTGEN; +defparam gt11_1.RXCRCSAMECLOCK = RXCRCSAMECLOCK; +defparam gt11_1.RXCTRL1 = RXCTRL1; +defparam gt11_1.RXCYCLE_LIMIT_SEL = RXCYCLE_LIMIT_SEL; +defparam gt11_1.RXDATA_SEL = RXDATA_SEL; +defparam gt11_1.RXDCCOUPLE = RXDCCOUPLE; +defparam gt11_1.RXDIGRESET = RXDIGRESET; +defparam gt11_1.RXDIGRX = RXDIGRX; +defparam gt11_1.RXEQ = RXEQ; +defparam gt11_1.RXFDCAL_CLOCK_DIVIDE = RXFDCAL_CLOCK_DIVIDE; +defparam gt11_1.RXFDET_HYS_CAL = RXFDET_HYS_CAL; +defparam gt11_1.RXFDET_HYS_SEL = RXFDET_HYS_SEL; +defparam gt11_1.RXFDET_LCK_CAL = RXFDET_LCK_CAL; +defparam gt11_1.RXFDET_LCK_SEL = RXFDET_LCK_SEL; +defparam gt11_1.RXFECONTROL1 = RXFECONTROL1; +defparam gt11_1.RXFECONTROL2 = RXFECONTROL2; +defparam gt11_1.RXFETUNE = RXFETUNE; +defparam gt11_1.RXLB = RXLB; +defparam gt11_1.RXLKADJ = RXLKADJ; +defparam gt11_1.RXLKAPD = RXLKAPD; +defparam gt11_1.RXLOOPCAL_WAIT = RXLOOPCAL_WAIT; +defparam gt11_1.RXLOOPFILT = RXLOOPFILT; +defparam gt11_1.RXMODE = RXMODE; +defparam gt11_1.RXOUTDIV2SEL = RXOUTDIV2SEL; +defparam gt11_1.RXPD = RXPD; +defparam gt11_1.RXPDDTST = RXPDDTST; +defparam gt11_1.RXPLLNDIVSEL = RXPLLNDIVSEL; +defparam gt11_1.RXPMACLKSEL = RXPMACLKSEL; +defparam gt11_1.RXRCPADJ = RXRCPADJ; +defparam gt11_1.RXRCPPD = RXRCPPD; +defparam gt11_1.RXRECCLK1_USE_SYNC = RXRECCLK1_USE_SYNC; +defparam gt11_1.RXRIBADJ = RXRIBADJ; +defparam gt11_1.RXRPDPD = RXRPDPD; +defparam gt11_1.RXRSDPD = RXRSDPD; +defparam gt11_1.RXSLOWDOWN_CAL = RXSLOWDOWN_CAL; +defparam gt11_1.RXTUNE = RXTUNE; +defparam gt11_1.RXUSRDIVISOR = RXUSRDIVISOR; +defparam gt11_1.RXVCODAC_INIT = RXVCODAC_INIT; +defparam gt11_1.RXVCO_CTRL_ENABLE = RXVCO_CTRL_ENABLE; +defparam gt11_1.RX_BUFFER_USE = RX_BUFFER_USE; +defparam gt11_1.RX_CLOCK_DIVIDER = RX_CLOCK_DIVIDER; +defparam gt11_1.SAMPLE_8X = SAMPLE_8X; +defparam gt11_1.SH_CNT_MAX = SH_CNT_MAX; +defparam gt11_1.SH_INVALID_CNT_MAX = SH_INVALID_CNT_MAX; +defparam gt11_1.SLOWDOWN_CAL = SLOWDOWN_CAL; +defparam gt11_1.TXABPMACLKSEL = TXABPMACLKSEL; +defparam gt11_1.TXAPD = TXAPD; +defparam gt11_1.TXAREFBIASSEL = TXAREFBIASSEL; +defparam gt11_1.TXASYNCDIVIDE = TXASYNCDIVIDE; +defparam gt11_1.TXCLK0_FORCE_PMACLK = TXCLK0_FORCE_PMACLK; +defparam gt11_1.TXCLKMODE = TXCLKMODE; +defparam gt11_1.TXCLMODE = TXCLMODE; +defparam gt11_1.TXCPSEL = TXCPSEL; +defparam gt11_1.TXCRCCLOCKDOUBLE = TXCRCCLOCKDOUBLE; +defparam gt11_1.TXCRCENABLE = TXCRCENABLE; +defparam gt11_1.TXCRCINITVAL = TXCRCINITVAL; +defparam gt11_1.TXCRCINVERTGEN = TXCRCINVERTGEN; +defparam gt11_1.TXCRCSAMECLOCK = TXCRCSAMECLOCK; +defparam gt11_1.TXCTRL1 = TXCTRL1; +defparam gt11_1.TXDATA_SEL = TXDATA_SEL; +defparam gt11_1.TXDAT_PRDRV_DAC = TXDAT_PRDRV_DAC; +defparam gt11_1.TXDAT_TAP_DAC = TXDAT_TAP_DAC; +defparam gt11_1.TXDIGPD = TXDIGPD; +defparam gt11_1.TXFDCAL_CLOCK_DIVIDE = TXFDCAL_CLOCK_DIVIDE; +defparam gt11_1.TXHIGHSIGNALEN = TXHIGHSIGNALEN; +defparam gt11_1.TXLOOPFILT = TXLOOPFILT; +defparam gt11_1.TXLVLSHFTPD = TXLVLSHFTPD; +defparam gt11_1.TXOUTCLK1_USE_SYNC = TXOUTCLK1_USE_SYNC; +defparam gt11_1.TXOUTDIV2SEL = TXOUTDIV2SEL; +defparam gt11_1.TXPD = TXPD; +defparam gt11_1.TXPHASESEL = TXPHASESEL; +defparam gt11_1.TXPLLNDIVSEL = TXPLLNDIVSEL; +defparam gt11_1.TXPOST_PRDRV_DAC = TXPOST_PRDRV_DAC; +defparam gt11_1.TXPOST_TAP_DAC = TXPOST_TAP_DAC; +defparam gt11_1.TXPOST_TAP_PD = TXPOST_TAP_PD; +defparam gt11_1.TXPRE_PRDRV_DAC = TXPRE_PRDRV_DAC; +defparam gt11_1.TXPRE_TAP_DAC = TXPRE_TAP_DAC; +defparam gt11_1.TXPRE_TAP_PD = TXPRE_TAP_PD; +defparam gt11_1.TXSLEWRATE = TXSLEWRATE; +defparam gt11_1.TXTERMTRIM = TXTERMTRIM; +defparam gt11_1.TXTUNE = TXTUNE; +defparam gt11_1.TX_BUFFER_USE = TX_BUFFER_USE; +defparam gt11_1.TX_CLOCK_DIVIDER = TX_CLOCK_DIVIDER; +defparam gt11_1.VCODAC_INIT = VCODAC_INIT; +defparam gt11_1.VCO_CTRL_ENABLE = VCO_CTRL_ENABLE; +defparam gt11_1.VREFBIASMODE = VREFBIASMODE; + +endmodule diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/GT11_DUAL.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/GT11_DUAL.v new file mode 100644 index 0000000..4152f2e --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/GT11_DUAL.v @@ -0,0 +1,1349 @@ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / 11-Gigabit Transceiver for High-Speed I/O DUAL Simulation Model +// /___/ /\ Filename : GT11_DUAL.v +// \ \ / \ Timestamp : Fri Jun 18 10:57:01 PDT 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/16/05 - Changed default values for some parameters and removed two parameters. Fixed CR#207101. +// 09/06/05 - Fixed CR#215006. Attribute default values update. +// 02/22/06 - CR#226003 - Added integer, real parameter type +// 02/28/06 - CR#226322 - Addition of new parameters and change of default values for some parameters. +// End Revision + +`timescale 1 ps / 1 ps + +module GT11_DUAL ( + CHBONDOA, + CHBONDOB, + DOA, + DOB, + DRDYA, + DRDYB, + RXBUFERRA, + RXBUFERRB, + RXCALFAILA, + RXCALFAILB, + RXCHARISCOMMAA, + RXCHARISCOMMAB, + RXCHARISKA, + RXCHARISKB, + RXCOMMADETA, + RXCOMMADETB, + RXCRCOUTA, + RXCRCOUTB, + RXCYCLELIMITA, + RXCYCLELIMITB, + RXDATAA, + RXDATAB, + RXDISPERRA, + RXDISPERRB, + RXLOCKA, + RXLOCKB, + RXLOSSOFSYNCA, + RXLOSSOFSYNCB, + RXMCLKA, + RXMCLKB, + RXNOTINTABLEA, + RXNOTINTABLEB, + RXPCSHCLKOUTA, + RXPCSHCLKOUTB, + RXREALIGNA, + RXREALIGNB, + RXRECCLK1A, + RXRECCLK1B, + RXRECCLK2A, + RXRECCLK2B, + RXRUNDISPA, + RXRUNDISPB, + RXSIGDETA, + RXSIGDETB, + RXSTATUSA, + RXSTATUSB, + TX1NA, + TX1NB, + TX1PA, + TX1PB, + TXBUFERRA, + TXBUFERRB, + TXCALFAILA, + TXCALFAILB, + TXCRCOUTA, + TXCRCOUTB, + TXCYCLELIMITA, + TXCYCLELIMITB, + TXKERRA, + TXKERRB, + TXLOCKA, + TXLOCKB, + TXOUTCLK1A, + TXOUTCLK1B, + TXOUTCLK2A, + TXOUTCLK2B, + TXPCSHCLKOUTA, + TXPCSHCLKOUTB, + TXRUNDISPA, + TXRUNDISPB, + CHBONDIA, + CHBONDIB, + DADDRA, + DADDRB, + DCLKA, + DCLKB, + DENA, + DENB, + DIA, + DIB, + DWEA, + DWEB, + ENCHANSYNCA, + ENCHANSYNCB, + ENMCOMMAALIGNA, + ENMCOMMAALIGNB, + ENPCOMMAALIGNA, + ENPCOMMAALIGNB, + GREFCLKA, + GREFCLKB, + LOOPBACKA, + LOOPBACKB, + POWERDOWNA, + POWERDOWNB, + REFCLK1A, + REFCLK1B, + REFCLK2A, + REFCLK2B, + RX1NA, + RX1NB, + RX1PA, + RX1PB, + RXBLOCKSYNC64B66BUSEA, + RXBLOCKSYNC64B66BUSEB, + RXCLKSTABLEA, + RXCLKSTABLEB, + RXCOMMADETUSEA, + RXCOMMADETUSEB, + RXCRCCLKA, + RXCRCCLKB, + RXCRCDATAVALIDA, + RXCRCDATAVALIDB, + RXCRCDATAWIDTHA, + RXCRCDATAWIDTHB, + RXCRCINA, + RXCRCINB, + RXCRCINITA, + RXCRCINITB, + RXCRCINTCLKA, + RXCRCINTCLKB, + RXCRCPDA, + RXCRCPDB, + RXCRCRESETA, + RXCRCRESETB, + RXDATAWIDTHA, + RXDATAWIDTHB, + RXDEC64B66BUSEA, + RXDEC64B66BUSEB, + RXDEC8B10BUSEA, + RXDEC8B10BUSEB, + RXDESCRAM64B66BUSEA, + RXDESCRAM64B66BUSEB, + RXIGNOREBTFA, + RXIGNOREBTFB, + RXINTDATAWIDTHA, + RXINTDATAWIDTHB, + RXPMARESETA, + RXPMARESETB, + RXPOLARITYA, + RXPOLARITYB, + RXRESETA, + RXRESETB, + RXSLIDEA, + RXSLIDEB, + RXSYNCA, + RXSYNCB, + RXUSRCLK2A, + RXUSRCLK2B, + RXUSRCLKA, + RXUSRCLKB, + TXBYPASS8B10BA, + TXBYPASS8B10BB, + TXCHARDISPMODEA, + TXCHARDISPMODEB, + TXCHARDISPVALA, + TXCHARDISPVALB, + TXCHARISKA, + TXCHARISKB, + TXCLKSTABLEA, + TXCLKSTABLEB, + TXCRCCLKA, + TXCRCCLKB, + TXCRCDATAVALIDA, + TXCRCDATAVALIDB, + TXCRCDATAWIDTHA, + TXCRCDATAWIDTHB, + TXCRCINA, + TXCRCINB, + TXCRCINITA, + TXCRCINITB, + TXCRCINTCLKA, + TXCRCINTCLKB, + TXCRCPDA, + TXCRCPDB, + TXCRCRESETA, + TXCRCRESETB, + TXDATAA, + TXDATAB, + TXDATAWIDTHA, + TXDATAWIDTHB, + TXENC64B66BUSEA, + TXENC64B66BUSEB, + TXENC8B10BUSEA, + TXENC8B10BUSEB, + TXENOOBA, + TXENOOBB, + TXGEARBOX64B66BUSEA, + TXGEARBOX64B66BUSEB, + TXINHIBITA, + TXINHIBITB, + TXINTDATAWIDTHA, + TXINTDATAWIDTHB, + TXPMARESETA, + TXPMARESETB, + TXPOLARITYA, + TXPOLARITYB, + TXRESETA, + TXRESETB, + TXSCRAM64B66BUSEA, + TXSCRAM64B66BUSEB, + TXSYNCA, + TXSYNCB, + TXUSRCLK2A, + TXUSRCLK2B, + TXUSRCLKA, + TXUSRCLKB +); + +parameter BANDGAPSEL_A = "FALSE"; +parameter BANDGAPSEL_B = "FALSE"; +parameter BIASRESSEL_A = "FALSE"; +parameter BIASRESSEL_B = "FALSE"; +parameter CCCB_ARBITRATOR_DISABLE_A = "FALSE"; +parameter CCCB_ARBITRATOR_DISABLE_B = "FALSE"; +parameter CHAN_BOND_MODE_A = "NONE"; +parameter CHAN_BOND_MODE_B = "NONE"; +parameter CHAN_BOND_ONE_SHOT_A = "FALSE"; +parameter CHAN_BOND_ONE_SHOT_B = "FALSE"; +parameter CHAN_BOND_SEQ_1_1_A = 11'b00000000000; +parameter CHAN_BOND_SEQ_1_1_B = 11'b00000000000; +parameter CHAN_BOND_SEQ_1_2_A = 11'b00000000000; +parameter CHAN_BOND_SEQ_1_2_B = 11'b00000000000; +parameter CHAN_BOND_SEQ_1_3_A = 11'b00000000000; +parameter CHAN_BOND_SEQ_1_3_B = 11'b00000000000; +parameter CHAN_BOND_SEQ_1_4_A = 11'b00000000000; +parameter CHAN_BOND_SEQ_1_4_B = 11'b00000000000; +parameter CHAN_BOND_SEQ_1_MASK_A = 4'b1110; +parameter CHAN_BOND_SEQ_1_MASK_B = 4'b1110; +parameter CHAN_BOND_SEQ_2_1_A = 11'b00000000000; +parameter CHAN_BOND_SEQ_2_1_B = 11'b00000000000; +parameter CHAN_BOND_SEQ_2_2_A = 11'b00000000000; +parameter CHAN_BOND_SEQ_2_2_B = 11'b00000000000; +parameter CHAN_BOND_SEQ_2_3_A = 11'b00000000000; +parameter CHAN_BOND_SEQ_2_3_B = 11'b00000000000; +parameter CHAN_BOND_SEQ_2_4_A = 11'b00000000000; +parameter CHAN_BOND_SEQ_2_4_B = 11'b00000000000; +parameter CHAN_BOND_SEQ_2_MASK_A = 4'b1110; +parameter CHAN_BOND_SEQ_2_MASK_B = 4'b1110; +parameter CHAN_BOND_SEQ_2_USE_A = "FALSE"; +parameter CHAN_BOND_SEQ_2_USE_B = "FALSE"; +parameter CLK_CORRECT_USE_A = "FALSE"; +parameter CLK_CORRECT_USE_B = "FALSE"; +parameter CLK_COR_8B10B_DE_A = "FALSE"; +parameter CLK_COR_8B10B_DE_B = "FALSE"; +parameter CLK_COR_SEQ_1_1_A = 11'b00000000000; +parameter CLK_COR_SEQ_1_1_B = 11'b00000000000; +parameter CLK_COR_SEQ_1_2_A = 11'b00000000000; +parameter CLK_COR_SEQ_1_2_B = 11'b00000000000; +parameter CLK_COR_SEQ_1_3_A = 11'b00000000000; +parameter CLK_COR_SEQ_1_3_B = 11'b00000000000; +parameter CLK_COR_SEQ_1_4_A = 11'b00000000000; +parameter CLK_COR_SEQ_1_4_B = 11'b00000000000; +parameter CLK_COR_SEQ_1_MASK_A = 4'b1110; +parameter CLK_COR_SEQ_1_MASK_B = 4'b1110; +parameter CLK_COR_SEQ_2_1_A = 11'b00000000000; +parameter CLK_COR_SEQ_2_1_B = 11'b00000000000; +parameter CLK_COR_SEQ_2_2_A = 11'b00000000000; +parameter CLK_COR_SEQ_2_2_B = 11'b00000000000; +parameter CLK_COR_SEQ_2_3_A = 11'b00000000000; +parameter CLK_COR_SEQ_2_3_B = 11'b00000000000; +parameter CLK_COR_SEQ_2_4_A = 11'b00000000000; +parameter CLK_COR_SEQ_2_4_B = 11'b00000000000; +parameter CLK_COR_SEQ_2_MASK_A = 4'b1110; +parameter CLK_COR_SEQ_2_MASK_B = 4'b1110; +parameter CLK_COR_SEQ_2_USE_A = "FALSE"; +parameter CLK_COR_SEQ_2_USE_B = "FALSE"; +parameter CLK_COR_SEQ_DROP_A = "FALSE"; +parameter CLK_COR_SEQ_DROP_B = "FALSE"; +parameter COMMA32_A = "FALSE"; +parameter COMMA32_B = "FALSE"; +parameter COMMA_10B_MASK_A = 10'h3FF; +parameter COMMA_10B_MASK_B = 10'h3FF; +parameter CYCLE_LIMIT_SEL_A = 2'b00; +parameter CYCLE_LIMIT_SEL_B = 2'b00; +parameter DCDR_FILTER_A = 3'b010; +parameter DCDR_FILTER_B = 3'b010; +parameter DEC_MCOMMA_DETECT_A = "TRUE"; +parameter DEC_MCOMMA_DETECT_B = "TRUE"; +parameter DEC_PCOMMA_DETECT_A = "TRUE"; +parameter DEC_PCOMMA_DETECT_B = "TRUE"; +parameter DEC_VALID_COMMA_ONLY_A = "TRUE"; +parameter DEC_VALID_COMMA_ONLY_B = "TRUE"; +parameter DIGRX_FWDCLK_A = 2'b00; +parameter DIGRX_FWDCLK_B = 2'b00; +parameter DIGRX_SYNC_MODE_A = "FALSE"; +parameter DIGRX_SYNC_MODE_B = "FALSE"; +parameter ENABLE_DCDR_A = "FALSE"; +parameter ENABLE_DCDR_B = "FALSE"; +parameter FDET_HYS_CAL_A = 3'b010; +parameter FDET_HYS_CAL_B = 3'b010; +parameter FDET_HYS_SEL_A = 3'b100; +parameter FDET_HYS_SEL_B = 3'b100; +parameter FDET_LCK_CAL_A = 3'b100; +parameter FDET_LCK_CAL_B = 3'b100; +parameter FDET_LCK_SEL_A = 3'b001; +parameter FDET_LCK_SEL_B = 3'b001; +parameter IREFBIASMODE_A = 2'b11; +parameter IREFBIASMODE_B = 2'b11; +parameter LOOPCAL_WAIT_A = 2'b00; +parameter LOOPCAL_WAIT_B = 2'b00; +parameter MCOMMA_32B_VALUE_A = 32'h00000000; +parameter MCOMMA_32B_VALUE_B = 32'h00000000; +parameter MCOMMA_DETECT_A = "TRUE"; +parameter MCOMMA_DETECT_B = "TRUE"; +parameter OPPOSITE_SELECT_A = "FALSE"; +parameter OPPOSITE_SELECT_B = "FALSE"; +parameter PCOMMA_32B_VALUE_A = 32'h00000000; +parameter PCOMMA_32B_VALUE_B = 32'h00000000; +parameter PCOMMA_DETECT_A = "TRUE"; +parameter PCOMMA_DETECT_B = "TRUE"; +parameter PCS_BIT_SLIP_A = "FALSE"; +parameter PCS_BIT_SLIP_B = "FALSE"; +parameter PMACLKENABLE_A = "TRUE"; +parameter PMACLKENABLE_B = "TRUE"; +parameter PMACOREPWRENABLE_A = "TRUE"; +parameter PMACOREPWRENABLE_B = "TRUE"; +parameter PMAIREFTRIM_A = 4'b0111; +parameter PMAIREFTRIM_B = 4'b0111; +parameter PMAVBGCTRL_A = 5'b00000; +parameter PMAVBGCTRL_B = 5'b00000; +parameter PMAVREFTRIM_A = 4'b0111; +parameter PMAVREFTRIM_B = 4'b0111; +parameter PMA_BIT_SLIP_A = "FALSE"; +parameter PMA_BIT_SLIP_B = "FALSE"; +parameter POWER_ENABLE_A = "TRUE"; +parameter POWER_ENABLE_B = "TRUE"; +parameter REPEATER_A = "FALSE"; +parameter REPEATER_B = "FALSE"; +parameter RXACTST_A = "FALSE"; +parameter RXACTST_B = "FALSE"; +parameter RXAFEEQ_A = 9'b000000000; +parameter RXAFEEQ_B = 9'b000000000; +parameter RXAFEPD_A = "FALSE"; +parameter RXAFEPD_B = "FALSE"; +parameter RXAFETST_A = "FALSE"; +parameter RXAFETST_B = "FALSE"; +parameter RXAPD_A = "FALSE"; +parameter RXAPD_B = "FALSE"; +parameter RXAREGCTRL_A = 5'b00000; +parameter RXAREGCTRL_B = 5'b00000; +parameter RXASYNCDIVIDE_A = 2'b11; +parameter RXASYNCDIVIDE_B = 2'b11; +parameter RXBY_32_A = "FALSE"; +parameter RXBY_32_B = "FALSE"; +parameter RXCDRLOS_A = 6'b000000; +parameter RXCDRLOS_B = 6'b000000; +parameter RXCLK0_FORCE_PMACLK_A = "FALSE"; +parameter RXCLK0_FORCE_PMACLK_B = "FALSE"; +parameter RXCLKMODE_A = 6'b110001; +parameter RXCLKMODE_B = 6'b110001; +parameter RXCLMODE_A = 2'b00; +parameter RXCLMODE_B = 2'b00; +parameter RXCMADJ_A = 2'b01; +parameter RXCMADJ_B = 2'b01; +parameter RXCPSEL_A = "TRUE"; +parameter RXCPSEL_B = "TRUE"; +parameter RXCPTST_A = "FALSE"; +parameter RXCPTST_B = "FALSE"; +parameter RXCRCCLOCKDOUBLE_A = "FALSE"; +parameter RXCRCCLOCKDOUBLE_B = "FALSE"; +parameter RXCRCENABLE_A = "FALSE"; +parameter RXCRCENABLE_B = "FALSE"; +parameter RXCRCINITVAL_A = 32'h00000000; +parameter RXCRCINITVAL_B = 32'h00000000; +parameter RXCRCINVERTGEN_A = "FALSE"; +parameter RXCRCINVERTGEN_B = "FALSE"; +parameter RXCRCSAMECLOCK_A = "FALSE"; +parameter RXCRCSAMECLOCK_B = "FALSE"; +parameter RXCTRL1_A = 10'h200; +parameter RXCTRL1_B = 10'h200; +parameter RXCYCLE_LIMIT_SEL_A = 2'b00; +parameter RXCYCLE_LIMIT_SEL_B = 2'b00; +parameter RXDATA_SEL_A = 2'b00; +parameter RXDATA_SEL_B = 2'b00; +parameter RXDCCOUPLE_A = "FALSE"; +parameter RXDCCOUPLE_B = "FALSE"; +parameter RXDIGRESET_A = "FALSE"; +parameter RXDIGRESET_B = "FALSE"; +parameter RXDIGRX_A = "FALSE"; +parameter RXDIGRX_B = "FALSE"; +parameter RXEQ_A = 64'h4000000000000000; +parameter RXEQ_B = 64'h4000000000000000; +parameter RXFDCAL_CLOCK_DIVIDE_A = "NONE"; +parameter RXFDCAL_CLOCK_DIVIDE_B = "NONE"; +parameter RXFDET_HYS_CAL_A = 3'b010; +parameter RXFDET_HYS_CAL_B = 3'b010; +parameter RXFDET_HYS_SEL_A = 3'b100; +parameter RXFDET_HYS_SEL_B = 3'b100; +parameter RXFDET_LCK_CAL_A = 3'b100; +parameter RXFDET_LCK_CAL_B = 3'b100; +parameter RXFDET_LCK_SEL_A = 3'b001; +parameter RXFDET_LCK_SEL_B = 3'b001; +parameter RXFECONTROL1_A = 2'b00; +parameter RXFECONTROL1_B = 2'b00; +parameter RXFECONTROL2_A = 3'b000; +parameter RXFECONTROL2_B = 3'b000; +parameter RXFETUNE_A = 2'b01; +parameter RXFETUNE_B = 2'b01; +parameter RXLB_A = "FALSE"; +parameter RXLB_B = "FALSE"; +parameter RXLKADJ_A = 5'b00000; +parameter RXLKADJ_B = 5'b00000; +parameter RXLKAPD_A = "FALSE"; +parameter RXLKAPD_B = "FALSE"; +parameter RXLOOPCAL_WAIT_A = 2'b00; +parameter RXLOOPCAL_WAIT_B = 2'b00; +parameter RXLOOPFILT_A = 4'b0111; +parameter RXLOOPFILT_B = 4'b0111; +parameter RXMODE_A = 6'b000000; +parameter RXMODE_B = 6'b000000; +parameter RXPDDTST_A = "TRUE"; +parameter RXPDDTST_B = "TRUE"; +parameter RXPD_A = "FALSE"; +parameter RXPD_B = "FALSE"; +parameter RXPMACLKSEL_A = "REFCLK1"; +parameter RXPMACLKSEL_B = "REFCLK1"; +parameter RXRCPADJ_A = 3'b011; +parameter RXRCPADJ_B = 3'b011; +parameter RXRCPPD_A = "FALSE"; +parameter RXRCPPD_B = "FALSE"; +parameter RXRECCLK1_USE_SYNC_A = "FALSE"; +parameter RXRECCLK1_USE_SYNC_B = "FALSE"; +parameter RXRIBADJ_A = 2'b11; +parameter RXRIBADJ_B = 2'b11; +parameter RXRPDPD_A = "FALSE"; +parameter RXRPDPD_B = "FALSE"; +parameter RXRSDPD_A = "FALSE"; +parameter RXRSDPD_B = "FALSE"; +parameter RXSLOWDOWN_CAL_A = 2'b00; +parameter RXSLOWDOWN_CAL_B = 2'b00; +parameter RXTUNE_A = 13'h0000; +parameter RXTUNE_B = 13'h0000; +parameter RXVCODAC_INIT_A = 10'b1010000000; +parameter RXVCODAC_INIT_B = 10'b1010000000; +parameter RXVCO_CTRL_ENABLE_A = "FALSE"; +parameter RXVCO_CTRL_ENABLE_B = "FALSE"; +parameter RX_BUFFER_USE_A = "TRUE"; +parameter RX_BUFFER_USE_B = "TRUE"; +parameter RX_CLOCK_DIVIDER_A = 2'b00; +parameter RX_CLOCK_DIVIDER_B = 2'b00; +parameter SAMPLE_8X_A = "FALSE"; +parameter SAMPLE_8X_B = "FALSE"; +parameter SLOWDOWN_CAL_A = 2'b00; +parameter SLOWDOWN_CAL_B = 2'b00; +parameter TXABPMACLKSEL_A = "REFCLK1"; +parameter TXABPMACLKSEL_B = "REFCLK1"; +parameter TXAPD_A = "FALSE"; +parameter TXAPD_B = "FALSE"; +parameter TXAREFBIASSEL_A = "TRUE"; +parameter TXAREFBIASSEL_B = "TRUE"; +parameter TXASYNCDIVIDE_A = 2'b11; +parameter TXASYNCDIVIDE_B = 2'b11; +parameter TXCLK0_FORCE_PMACLK_A = "FALSE"; +parameter TXCLK0_FORCE_PMACLK_B = "FALSE"; +parameter TXCLKMODE_A = 4'b1001; +parameter TXCLKMODE_B = 4'b1001; +parameter TXCLMODE_A = 2'b00; +parameter TXCLMODE_B = 2'b00; +parameter TXCPSEL_A = "TRUE"; +parameter TXCPSEL_B = "TRUE"; +parameter TXCRCCLOCKDOUBLE_A = "FALSE"; +parameter TXCRCCLOCKDOUBLE_B = "FALSE"; +parameter TXCRCENABLE_A = "FALSE"; +parameter TXCRCENABLE_B = "FALSE"; +parameter TXCRCINITVAL_A = 32'h00000000; +parameter TXCRCINITVAL_B = 32'h00000000; +parameter TXCRCINVERTGEN_A = "FALSE"; +parameter TXCRCINVERTGEN_B = "FALSE"; +parameter TXCRCSAMECLOCK_A = "FALSE"; +parameter TXCRCSAMECLOCK_B = "FALSE"; +parameter TXCTRL1_A = 10'h200; +parameter TXCTRL1_B = 10'h200; +parameter TXDATA_SEL_A = 2'b00; +parameter TXDATA_SEL_B = 2'b00; +parameter TXDAT_PRDRV_DAC_A = 3'b111; +parameter TXDAT_PRDRV_DAC_B = 3'b111; +parameter TXDAT_TAP_DAC_A = 5'b10110; +parameter TXDAT_TAP_DAC_B = 5'b10110; +parameter TXDIGPD_A = "FALSE"; +parameter TXDIGPD_B = "FALSE"; +parameter TXFDCAL_CLOCK_DIVIDE_A = "NONE"; +parameter TXFDCAL_CLOCK_DIVIDE_B = "NONE"; +parameter TXHIGHSIGNALEN_A = "TRUE"; +parameter TXHIGHSIGNALEN_B = "TRUE"; +parameter TXLOOPFILT_A = 4'b0111; +parameter TXLOOPFILT_B = 4'b0111; +parameter TXLVLSHFTPD_A = "FALSE"; +parameter TXLVLSHFTPD_B = "FALSE"; +parameter TXOUTCLK1_USE_SYNC_A = "FALSE"; +parameter TXOUTCLK1_USE_SYNC_B = "FALSE"; +parameter TXPD_A = "FALSE"; +parameter TXPD_B = "FALSE"; +parameter TXPHASESEL_A = "FALSE"; +parameter TXPHASESEL_B = "FALSE"; +parameter TXPOST_PRDRV_DAC_A = 3'b111; +parameter TXPOST_PRDRV_DAC_B = 3'b111; +parameter TXPOST_TAP_DAC_A = 5'b01110; +parameter TXPOST_TAP_DAC_B = 5'b01110; +parameter TXPOST_TAP_PD_A = "TRUE"; +parameter TXPOST_TAP_PD_B = "TRUE"; +parameter TXPRE_PRDRV_DAC_A = 3'b111; +parameter TXPRE_PRDRV_DAC_B = 3'b111; +parameter TXPRE_TAP_DAC_A = 5'b00000; +parameter TXPRE_TAP_DAC_B = 5'b00000; +parameter TXPRE_TAP_PD_A = "TRUE"; +parameter TXPRE_TAP_PD_B = "TRUE"; +parameter TXSLEWRATE_A = "FALSE"; +parameter TXSLEWRATE_B = "FALSE"; +parameter TXTERMTRIM_A = 4'b1100; +parameter TXTERMTRIM_B = 4'b1100; +parameter TXTUNE_A = 13'h0000; +parameter TXTUNE_B = 13'h0000; +parameter TX_BUFFER_USE_A = "TRUE"; +parameter TX_BUFFER_USE_B = "TRUE"; +parameter TX_CLOCK_DIVIDER_A = 2'b00; +parameter TX_CLOCK_DIVIDER_B = 2'b00; +parameter VCODAC_INIT_A = 10'b1010000000; +parameter VCODAC_INIT_B = 10'b1010000000; +parameter VCO_CTRL_ENABLE_A = "FALSE"; +parameter VCO_CTRL_ENABLE_B = "FALSE"; +parameter VREFBIASMODE_A = 2'b11; +parameter VREFBIASMODE_B = 2'b11; +parameter integer ALIGN_COMMA_WORD_A = 4; +parameter integer ALIGN_COMMA_WORD_B = 4; +parameter integer CHAN_BOND_LIMIT_A = 16; +parameter integer CHAN_BOND_LIMIT_B = 16; +parameter integer CHAN_BOND_SEQ_LEN_A = 1; +parameter integer CHAN_BOND_SEQ_LEN_B = 1; +parameter integer CLK_COR_MAX_LAT_A = 48; +parameter integer CLK_COR_MAX_LAT_B = 48; +parameter integer CLK_COR_MIN_LAT_A = 36; +parameter integer CLK_COR_MIN_LAT_B = 36; +parameter integer CLK_COR_SEQ_LEN_A = 1; +parameter integer CLK_COR_SEQ_LEN_B = 1; +parameter integer RXOUTDIV2SEL_A = 1; +parameter integer RXOUTDIV2SEL_B = 1; +parameter integer RXPLLNDIVSEL_A = 8; +parameter integer RXPLLNDIVSEL_B = 8; +parameter integer RXUSRDIVISOR_A = 1; +parameter integer RXUSRDIVISOR_B = 1; +parameter integer SH_CNT_MAX_A = 64; +parameter integer SH_CNT_MAX_B = 64; +parameter integer SH_INVALID_CNT_MAX_A = 16; +parameter integer SH_INVALID_CNT_MAX_B = 16; +parameter integer TXOUTDIV2SEL_A = 1; +parameter integer TXOUTDIV2SEL_B = 1; +parameter integer TXPLLNDIVSEL_A = 8; +parameter integer TXPLLNDIVSEL_B = 8; + + +output DRDYA; +output DRDYB; +output RXBUFERRA; +output RXBUFERRB; +output RXCALFAILA; +output RXCALFAILB; +output RXCOMMADETA; +output RXCOMMADETB; +output RXCYCLELIMITA; +output RXCYCLELIMITB; +output RXLOCKA; +output RXLOCKB; +output RXMCLKA; +output RXMCLKB; +output RXPCSHCLKOUTA; +output RXPCSHCLKOUTB; +output RXREALIGNA; +output RXREALIGNB; +output RXRECCLK1A; +output RXRECCLK1B; +output RXRECCLK2A; +output RXRECCLK2B; +output RXSIGDETA; +output RXSIGDETB; +output TX1NA; +output TX1NB; +output TX1PA; +output TX1PB; +output TXBUFERRA; +output TXBUFERRB; +output TXCALFAILA; +output TXCALFAILB; +output TXCYCLELIMITA; +output TXCYCLELIMITB; +output TXLOCKA; +output TXLOCKB; +output TXOUTCLK1A; +output TXOUTCLK1B; +output TXOUTCLK2A; +output TXOUTCLK2B; +output TXPCSHCLKOUTA; +output TXPCSHCLKOUTB; +output [15:0] DOA; +output [15:0] DOB; +output [1:0] RXLOSSOFSYNCA; +output [1:0] RXLOSSOFSYNCB; +output [31:0] RXCRCOUTA; +output [31:0] RXCRCOUTB; +output [31:0] TXCRCOUTA; +output [31:0] TXCRCOUTB; +output [4:0] CHBONDOA; +output [4:0] CHBONDOB; +output [5:0] RXSTATUSA; +output [5:0] RXSTATUSB; +output [63:0] RXDATAA; +output [63:0] RXDATAB; +output [7:0] RXCHARISCOMMAA; +output [7:0] RXCHARISCOMMAB; +output [7:0] RXCHARISKA; +output [7:0] RXCHARISKB; +output [7:0] RXDISPERRA; +output [7:0] RXDISPERRB; +output [7:0] RXNOTINTABLEA; +output [7:0] RXNOTINTABLEB; +output [7:0] RXRUNDISPA; +output [7:0] RXRUNDISPB; +output [7:0] TXKERRA; +output [7:0] TXKERRB; +output [7:0] TXRUNDISPA; +output [7:0] TXRUNDISPB; + +input DCLKA; +input DCLKB; +input DENA; +input DENB; +input DWEA; +input DWEB; +input ENCHANSYNCA; +input ENCHANSYNCB; +input ENMCOMMAALIGNA; +input ENMCOMMAALIGNB; +input ENPCOMMAALIGNA; +input ENPCOMMAALIGNB; +input GREFCLKA; +input GREFCLKB; +input POWERDOWNA; +input POWERDOWNB; +input REFCLK1A; +input REFCLK1B; +input REFCLK2A; +input REFCLK2B; +input RX1NA; +input RX1NB; +input RX1PA; +input RX1PB; +input RXBLOCKSYNC64B66BUSEA; +input RXBLOCKSYNC64B66BUSEB; +input RXCLKSTABLEA; +input RXCLKSTABLEB; +input RXCOMMADETUSEA; +input RXCOMMADETUSEB; +input RXCRCCLKA; +input RXCRCCLKB; +input RXCRCDATAVALIDA; +input RXCRCDATAVALIDB; +input RXCRCINITA; +input RXCRCINITB; +input RXCRCINTCLKA; +input RXCRCINTCLKB; +input RXCRCPDA; +input RXCRCPDB; +input RXCRCRESETA; +input RXCRCRESETB; +input RXDEC64B66BUSEA; +input RXDEC64B66BUSEB; +input RXDEC8B10BUSEA; +input RXDEC8B10BUSEB; +input RXDESCRAM64B66BUSEA; +input RXDESCRAM64B66BUSEB; +input RXIGNOREBTFA; +input RXIGNOREBTFB; +input RXPMARESETA; +input RXPMARESETB; +input RXPOLARITYA; +input RXPOLARITYB; +input RXRESETA; +input RXRESETB; +input RXSLIDEA; +input RXSLIDEB; +input RXSYNCA; +input RXSYNCB; +input RXUSRCLK2A; +input RXUSRCLK2B; +input RXUSRCLKA; +input RXUSRCLKB; +input TXCLKSTABLEA; +input TXCLKSTABLEB; +input TXCRCCLKA; +input TXCRCCLKB; +input TXCRCDATAVALIDA; +input TXCRCDATAVALIDB; +input TXCRCINITA; +input TXCRCINITB; +input TXCRCINTCLKA; +input TXCRCINTCLKB; +input TXCRCPDA; +input TXCRCPDB; +input TXCRCRESETA; +input TXCRCRESETB; +input TXENC64B66BUSEA; +input TXENC64B66BUSEB; +input TXENC8B10BUSEA; +input TXENC8B10BUSEB; +input TXENOOBA; +input TXENOOBB; +input TXGEARBOX64B66BUSEA; +input TXGEARBOX64B66BUSEB; +input TXINHIBITA; +input TXINHIBITB; +input TXPMARESETA; +input TXPMARESETB; +input TXPOLARITYA; +input TXPOLARITYB; +input TXRESETA; +input TXRESETB; +input TXSCRAM64B66BUSEA; +input TXSCRAM64B66BUSEB; +input TXSYNCA; +input TXSYNCB; +input TXUSRCLK2A; +input TXUSRCLK2B; +input TXUSRCLKA; +input TXUSRCLKB; +input [15:0] DIA; +input [15:0] DIB; +input [1:0] LOOPBACKA; +input [1:0] LOOPBACKB; +input [1:0] RXDATAWIDTHA; +input [1:0] RXDATAWIDTHB; +input [1:0] RXINTDATAWIDTHA; +input [1:0] RXINTDATAWIDTHB; +input [1:0] TXDATAWIDTHA; +input [1:0] TXDATAWIDTHB; +input [1:0] TXINTDATAWIDTHA; +input [1:0] TXINTDATAWIDTHB; +input [2:0] RXCRCDATAWIDTHA; +input [2:0] RXCRCDATAWIDTHB; +input [2:0] TXCRCDATAWIDTHA; +input [2:0] TXCRCDATAWIDTHB; +input [4:0] CHBONDIA; +input [4:0] CHBONDIB; +input [63:0] RXCRCINA; +input [63:0] RXCRCINB; +input [63:0] TXCRCINA; +input [63:0] TXCRCINB; +input [63:0] TXDATAA; +input [63:0] TXDATAB; +input [7:0] DADDRA; +input [7:0] DADDRB; +input [7:0] TXBYPASS8B10BA; +input [7:0] TXBYPASS8B10BB; +input [7:0] TXCHARDISPMODEA; +input [7:0] TXCHARDISPMODEB; +input [7:0] TXCHARDISPVALA; +input [7:0] TXCHARDISPVALB; +input [7:0] TXCHARISKA; +input [7:0] TXCHARISKB; + +wire [15:0] COMBUSINB; +wire [15:0] COMBUSINA; + +GT11 gt11_a ( + .CHBONDO(CHBONDOA), + .COMBUSOUT(COMBUSINB), + .DO(DOA), + .DRDY(DRDYA), + .RXBUFERR(RXBUFERRA), + .RXCALFAIL(RXCALFAILA), + .RXCHARISCOMMA(RXCHARISCOMMAA), + .RXCHARISK(RXCHARISKA), + .RXCOMMADET(RXCOMMADETA), + .RXCRCOUT(RXCRCOUTA), + .RXCYCLELIMIT(RXCYCLELIMITA), + .RXDATA(RXDATAA), + .RXDISPERR(RXDISPERRA), + .RXLOCK(RXLOCKA), + .RXLOSSOFSYNC(RXLOSSOFSYNCA), + .RXMCLK(RXMCLKA), + .RXNOTINTABLE(RXNOTINTABLEA), + .RXPCSHCLKOUT(RXPCSHCLKOUTA), + .RXREALIGN(RXREALIGNA), + .RXRECCLK1(RXRECCLK1A), + .RXRECCLK2(RXRECCLK2A), + .RXRUNDISP(RXRUNDISPA), + .RXSIGDET(RXSIGDETA), + .RXSTATUS(RXSTATUSA), + .TX1N(TX1NA), + .TX1P(TX1PA), + .TXBUFERR(TXBUFERRA), + .TXCALFAIL(TXCALFAILA), + .TXCRCOUT(TXCRCOUTA), + .TXCYCLELIMIT(TXCYCLELIMITA), + .TXKERR(TXKERRA), + .TXLOCK(TXLOCKA), + .TXOUTCLK1(TXOUTCLK1A), + .TXOUTCLK2(TXOUTCLK2A), + .TXPCSHCLKOUT(TXPCSHCLKOUTA), + .TXRUNDISP(TXRUNDISPA), + .CHBONDI(CHBONDIA), + .COMBUSIN(COMBUSINA), + .DADDR(DADDRA), + .DCLK(DCLKA), + .DEN(DENA), + .DI(DIA), + .DWE(DWEA), + .ENCHANSYNC(ENCHANSYNCA), + .ENMCOMMAALIGN(ENMCOMMAALIGNA), + .ENPCOMMAALIGN(ENPCOMMAALIGNA), + .GREFCLK(GREFCLKA), + .LOOPBACK(LOOPBACKA), + .POWERDOWN(POWERDOWNA), + .REFCLK1(REFCLK1A), + .REFCLK2(REFCLK2A), + .RX1N(RX1NA), + .RX1P(RX1PA), + .RXBLOCKSYNC64B66BUSE(RXBLOCKSYNC64B66BUSEA), + .RXCLKSTABLE(RXCLKSTABLEA), + .RXCOMMADETUSE(RXCOMMADETUSEA), + .RXCRCCLK(RXCRCCLKA), + .RXCRCDATAVALID(RXCRCDATAVALIDA), + .RXCRCDATAWIDTH(RXCRCDATAWIDTHA), + .RXCRCIN(RXCRCINA), + .RXCRCINIT(RXCRCINITA), + .RXCRCINTCLK(RXCRCINTCLKA), + .RXCRCPD(RXCRCPDA), + .RXCRCRESET(RXCRCRESETA), + .RXDATAWIDTH(RXDATAWIDTHA), + .RXDEC64B66BUSE(RXDEC64B66BUSEA), + .RXDEC8B10BUSE(RXDEC8B10BUSEA), + .RXDESCRAM64B66BUSE(RXDESCRAM64B66BUSEA), + .RXIGNOREBTF(RXIGNOREBTFA), + .RXINTDATAWIDTH(RXINTDATAWIDTHA), + .RXPMARESET(RXPMARESETA), + .RXPOLARITY(RXPOLARITYA), + .RXRESET(RXRESETA), + .RXSLIDE(RXSLIDEA), + .RXSYNC(RXSYNCA), + .RXUSRCLK(RXUSRCLKA), + .RXUSRCLK2(RXUSRCLK2A), + .TXBYPASS8B10B(TXBYPASS8B10BA), + .TXCHARDISPMODE(TXCHARDISPMODEA), + .TXCHARDISPVAL(TXCHARDISPVALA), + .TXCHARISK(TXCHARISKA), + .TXCLKSTABLE(TXCLKSTABLEA), + .TXCRCCLK(TXCRCCLKA), + .TXCRCDATAVALID(TXCRCDATAVALIDA), + .TXCRCDATAWIDTH(TXCRCDATAWIDTHA), + .TXCRCIN(TXCRCINA), + .TXCRCINIT(TXCRCINITA), + .TXCRCINTCLK(TXCRCINTCLKA), + .TXCRCPD(TXCRCPDA), + .TXCRCRESET(TXCRCRESETA), + .TXDATA(TXDATAA), + .TXDATAWIDTH(TXDATAWIDTHA), + .TXENC64B66BUSE(TXENC64B66BUSEA), + .TXENC8B10BUSE(TXENC8B10BUSEA), + .TXENOOB(TXENOOBA), + .TXGEARBOX64B66BUSE(TXGEARBOX64B66BUSEA), + .TXINHIBIT(TXINHIBITA), + .TXINTDATAWIDTH(TXINTDATAWIDTHA), + .TXPMARESET(TXPMARESETA), + .TXPOLARITY(TXPOLARITYA), + .TXRESET(TXRESETA), + .TXSCRAM64B66BUSE(TXSCRAM64B66BUSEA), + .TXSYNC(TXSYNCA), + .TXUSRCLK(TXUSRCLKA), + .TXUSRCLK2(TXUSRCLK2A) +); + +GT11 gt11_b ( + .CHBONDO(CHBONDOB), + .COMBUSOUT(COMBUSINA), + .DO(DOB), + .DRDY(DRDYB), + .RXBUFERR(RXBUFERRB), + .RXCALFAIL(RXCALFAILB), + .RXCHARISCOMMA(RXCHARISCOMMAB), + .RXCHARISK(RXCHARISKB), + .RXCOMMADET(RXCOMMADETB), + .RXCRCOUT(RXCRCOUTB), + .RXCYCLELIMIT(RXCYCLELIMITB), + .RXDATA(RXDATAB), + .RXDISPERR(RXDISPERRB), + .RXLOCK(RXLOCKB), + .RXLOSSOFSYNC(RXLOSSOFSYNCB), + .RXMCLK(RXMCLKB), + .RXNOTINTABLE(RXNOTINTABLEB), + .RXPCSHCLKOUT(RXPCSHCLKOUTB), + .RXREALIGN(RXREALIGNB), + .RXRECCLK1(RXRECCLK1B), + .RXRECCLK2(RXRECCLK2B), + .RXRUNDISP(RXRUNDISPB), + .RXSIGDET(RXSIGDETB), + .RXSTATUS(RXSTATUSB), + .TX1N(TX1NB), + .TX1P(TX1PB), + .TXBUFERR(TXBUFERRB), + .TXCALFAIL(TXCALFAILB), + .TXCRCOUT(TXCRCOUTB), + .TXCYCLELIMIT(TXCYCLELIMITB), + .TXKERR(TXKERRB), + .TXLOCK(TXLOCKB), + .TXOUTCLK1(TXOUTCLK1B), + .TXOUTCLK2(TXOUTCLK2B), + .TXPCSHCLKOUT(TXPCSHCLKOUTB), + .TXRUNDISP(TXRUNDISPB), + .CHBONDI(CHBONDIB), + .COMBUSIN(COMBUSINB), + .DADDR(DADDRB), + .DCLK(DCLKB), + .DEN(DENB), + .DI(DIB), + .DWE(DWEB), + .ENCHANSYNC(ENCHANSYNCB), + .ENMCOMMAALIGN(ENMCOMMAALIGNB), + .ENPCOMMAALIGN(ENPCOMMAALIGNB), + .GREFCLK(GREFCLKB), + .LOOPBACK(LOOPBACKB), + .POWERDOWN(POWERDOWNB), + .REFCLK1(REFCLK1B), + .REFCLK2(REFCLK2B), + .RX1N(RX1NB), + .RX1P(RX1PB), + .RXBLOCKSYNC64B66BUSE(RXBLOCKSYNC64B66BUSEB), + .RXCLKSTABLE(RXCLKSTABLEB), + .RXCOMMADETUSE(RXCOMMADETUSEB), + .RXCRCCLK(RXCRCCLKB), + .RXCRCDATAVALID(RXCRCDATAVALIDB), + .RXCRCDATAWIDTH(RXCRCDATAWIDTHB), + .RXCRCIN(RXCRCINB), + .RXCRCINIT(RXCRCINITB), + .RXCRCINTCLK(RXCRCINTCLKB), + .RXCRCPD(RXCRCPDB), + .RXCRCRESET(RXCRCRESETB), + .RXDATAWIDTH(RXDATAWIDTHB), + .RXDEC64B66BUSE(RXDEC64B66BUSEB), + .RXDEC8B10BUSE(RXDEC8B10BUSEB), + .RXDESCRAM64B66BUSE(RXDESCRAM64B66BUSEB), + .RXIGNOREBTF(RXIGNOREBTFB), + .RXINTDATAWIDTH(RXINTDATAWIDTHB), + .RXPMARESET(RXPMARESETB), + .RXPOLARITY(RXPOLARITYB), + .RXRESET(RXRESETB), + .RXSLIDE(RXSLIDEB), + .RXSYNC(RXSYNCB), + .RXUSRCLK(RXUSRCLKB), + .RXUSRCLK2(RXUSRCLK2B), + .TXBYPASS8B10B(TXBYPASS8B10BB), + .TXCHARDISPMODE(TXCHARDISPMODEB), + .TXCHARDISPVAL(TXCHARDISPVALB), + .TXCHARISK(TXCHARISKB), + .TXCLKSTABLE(TXCLKSTABLEB), + .TXCRCCLK(TXCRCCLKB), + .TXCRCDATAVALID(TXCRCDATAVALIDB), + .TXCRCDATAWIDTH(TXCRCDATAWIDTHB), + .TXCRCIN(TXCRCINB), + .TXCRCINIT(TXCRCINITB), + .TXCRCINTCLK(TXCRCINTCLKB), + .TXCRCPD(TXCRCPDB), + .TXCRCRESET(TXCRCRESETB), + .TXDATA(TXDATAB), + .TXDATAWIDTH(TXDATAWIDTHB), + .TXENC64B66BUSE(TXENC64B66BUSEB), + .TXENC8B10BUSE(TXENC8B10BUSEB), + .TXENOOB(TXENOOBB), + .TXGEARBOX64B66BUSE(TXGEARBOX64B66BUSEB), + .TXINHIBIT(TXINHIBITB), + .TXINTDATAWIDTH(TXINTDATAWIDTHB), + .TXPMARESET(TXPMARESETB), + .TXPOLARITY(TXPOLARITYB), + .TXRESET(TXRESETB), + .TXSCRAM64B66BUSE(TXSCRAM64B66BUSEB), + .TXSYNC(TXSYNCB), + .TXUSRCLK(TXUSRCLKB), + .TXUSRCLK2(TXUSRCLK2B) + +); + +defparam gt11_a.ALIGN_COMMA_WORD = ALIGN_COMMA_WORD_A; +defparam gt11_a.BANDGAPSEL = BANDGAPSEL_A; +defparam gt11_a.BIASRESSEL = BIASRESSEL_A; +defparam gt11_a.CCCB_ARBITRATOR_DISABLE = CCCB_ARBITRATOR_DISABLE_A; +defparam gt11_a.CHAN_BOND_LIMIT = CHAN_BOND_LIMIT_A; +defparam gt11_a.CHAN_BOND_MODE = CHAN_BOND_MODE_A; +defparam gt11_a.CHAN_BOND_ONE_SHOT = CHAN_BOND_ONE_SHOT_A; +defparam gt11_a.CHAN_BOND_SEQ_1_1 = CHAN_BOND_SEQ_1_1_A; +defparam gt11_a.CHAN_BOND_SEQ_1_2 = CHAN_BOND_SEQ_1_2_A; +defparam gt11_a.CHAN_BOND_SEQ_1_3 = CHAN_BOND_SEQ_1_3_A; +defparam gt11_a.CHAN_BOND_SEQ_1_4 = CHAN_BOND_SEQ_1_4_A; +defparam gt11_a.CHAN_BOND_SEQ_1_MASK = CHAN_BOND_SEQ_1_MASK_A; +defparam gt11_a.CHAN_BOND_SEQ_2_1 = CHAN_BOND_SEQ_2_1_A; +defparam gt11_a.CHAN_BOND_SEQ_2_2 = CHAN_BOND_SEQ_2_2_A; +defparam gt11_a.CHAN_BOND_SEQ_2_3 = CHAN_BOND_SEQ_2_3_A; +defparam gt11_a.CHAN_BOND_SEQ_2_4 = CHAN_BOND_SEQ_2_4_A; +defparam gt11_a.CHAN_BOND_SEQ_2_MASK = CHAN_BOND_SEQ_2_MASK_A; +defparam gt11_a.CHAN_BOND_SEQ_2_USE = CHAN_BOND_SEQ_2_USE_A; +defparam gt11_a.CHAN_BOND_SEQ_LEN = CHAN_BOND_SEQ_LEN_A; +defparam gt11_a.CLK_CORRECT_USE = CLK_CORRECT_USE_A; +defparam gt11_a.CLK_COR_8B10B_DE = CLK_COR_8B10B_DE_A; +defparam gt11_a.CLK_COR_MAX_LAT = CLK_COR_MAX_LAT_A; +defparam gt11_a.CLK_COR_MIN_LAT = CLK_COR_MIN_LAT_A; +defparam gt11_a.CLK_COR_SEQ_1_1 = CLK_COR_SEQ_1_1_A; +defparam gt11_a.CLK_COR_SEQ_1_2 = CLK_COR_SEQ_1_2_A; +defparam gt11_a.CLK_COR_SEQ_1_3 = CLK_COR_SEQ_1_3_A; +defparam gt11_a.CLK_COR_SEQ_1_4 = CLK_COR_SEQ_1_4_A; +defparam gt11_a.CLK_COR_SEQ_1_MASK = CLK_COR_SEQ_1_MASK_A; +defparam gt11_a.CLK_COR_SEQ_2_1 = CLK_COR_SEQ_2_1_A; +defparam gt11_a.CLK_COR_SEQ_2_2 = CLK_COR_SEQ_2_2_A; +defparam gt11_a.CLK_COR_SEQ_2_3 = CLK_COR_SEQ_2_3_A; +defparam gt11_a.CLK_COR_SEQ_2_4 = CLK_COR_SEQ_2_4_A; +defparam gt11_a.CLK_COR_SEQ_2_MASK = CLK_COR_SEQ_2_MASK_A; +defparam gt11_a.CLK_COR_SEQ_2_USE = CLK_COR_SEQ_2_USE_A; +defparam gt11_a.CLK_COR_SEQ_DROP = CLK_COR_SEQ_DROP_A; +defparam gt11_a.CLK_COR_SEQ_LEN = CLK_COR_SEQ_LEN_A; +defparam gt11_a.COMMA32 = COMMA32_A; +defparam gt11_a.COMMA_10B_MASK = COMMA_10B_MASK_A; +defparam gt11_a.CYCLE_LIMIT_SEL = CYCLE_LIMIT_SEL_A; +defparam gt11_a.DCDR_FILTER = DCDR_FILTER_A; +defparam gt11_a.DEC_MCOMMA_DETECT = DEC_MCOMMA_DETECT_A; +defparam gt11_a.DEC_PCOMMA_DETECT = DEC_PCOMMA_DETECT_A; +defparam gt11_a.DEC_VALID_COMMA_ONLY = DEC_VALID_COMMA_ONLY_A; +defparam gt11_a.DIGRX_FWDCLK = DIGRX_FWDCLK_A; +defparam gt11_a.DIGRX_SYNC_MODE = DIGRX_SYNC_MODE_A; +defparam gt11_a.ENABLE_DCDR = ENABLE_DCDR_A; +defparam gt11_a.FDET_HYS_CAL = FDET_HYS_CAL_A; +defparam gt11_a.FDET_HYS_SEL = FDET_HYS_SEL_A; +defparam gt11_a.FDET_LCK_CAL = FDET_LCK_CAL_A; +defparam gt11_a.FDET_LCK_SEL = FDET_LCK_SEL_A; +defparam gt11_a.GT11_MODE = "A"; +defparam gt11_a.IREFBIASMODE = IREFBIASMODE_A; +defparam gt11_a.LOOPCAL_WAIT = LOOPCAL_WAIT_A; +defparam gt11_a.MCOMMA_32B_VALUE = MCOMMA_32B_VALUE_A; +defparam gt11_a.MCOMMA_DETECT = MCOMMA_DETECT_A; +defparam gt11_a.OPPOSITE_SELECT = OPPOSITE_SELECT_A; +defparam gt11_a.PCOMMA_32B_VALUE = PCOMMA_32B_VALUE_A; +defparam gt11_a.PCOMMA_DETECT = PCOMMA_DETECT_A; +defparam gt11_a.PCS_BIT_SLIP = PCS_BIT_SLIP_A; +defparam gt11_a.PMACLKENABLE = PMACLKENABLE_A; +defparam gt11_a.PMACOREPWRENABLE = PMACOREPWRENABLE_A; +defparam gt11_a.PMAIREFTRIM = PMAIREFTRIM_A; +defparam gt11_a.PMAVBGCTRL = PMAVBGCTRL_A; +defparam gt11_a.PMAVREFTRIM = PMAVREFTRIM_A; +defparam gt11_a.PMA_BIT_SLIP = PMA_BIT_SLIP_A; +defparam gt11_a.POWER_ENABLE = POWER_ENABLE_A; +defparam gt11_a.REPEATER = REPEATER_A; +defparam gt11_a.RXACTST = RXACTST_A; +defparam gt11_a.RXAFEEQ = RXAFEEQ_A; +defparam gt11_a.RXAFEPD = RXAFEPD_A; +defparam gt11_a.RXAFETST = RXAFETST_A; +defparam gt11_a.RXAPD = RXAPD_A; +defparam gt11_a.RXAREGCTRL = RXAREGCTRL_A; +defparam gt11_a.RXASYNCDIVIDE = RXASYNCDIVIDE_A; +defparam gt11_a.RXBY_32 = RXBY_32_A; +defparam gt11_a.RXCDRLOS = RXCDRLOS_A; +defparam gt11_a.RXCLK0_FORCE_PMACLK = RXCLK0_FORCE_PMACLK_A; +defparam gt11_a.RXCLKMODE = RXCLKMODE_A; +defparam gt11_a.RXCLMODE = RXCLMODE_A; +defparam gt11_a.RXCMADJ = RXCMADJ_A; +defparam gt11_a.RXCPSEL = RXCPSEL_A; +defparam gt11_a.RXCPTST = RXCPTST_A; +defparam gt11_a.RXCRCCLOCKDOUBLE = RXCRCCLOCKDOUBLE_A; +defparam gt11_a.RXCRCENABLE = RXCRCENABLE_A; +defparam gt11_a.RXCRCINITVAL = RXCRCINITVAL_A; +defparam gt11_a.RXCRCINVERTGEN = RXCRCINVERTGEN_A; +defparam gt11_a.RXCRCSAMECLOCK = RXCRCSAMECLOCK_A; +defparam gt11_a.RXCTRL1 = RXCTRL1_A; +defparam gt11_a.RXCYCLE_LIMIT_SEL = RXCYCLE_LIMIT_SEL_A; +defparam gt11_a.RXDATA_SEL = RXDATA_SEL_A; +defparam gt11_a.RXDCCOUPLE = RXDCCOUPLE_A; +defparam gt11_a.RXDIGRESET = RXDIGRESET_A; +defparam gt11_a.RXDIGRX = RXDIGRX_A; +defparam gt11_a.RXEQ = RXEQ_A; +defparam gt11_a.RXFDCAL_CLOCK_DIVIDE = RXFDCAL_CLOCK_DIVIDE_A; +defparam gt11_a.RXFDET_HYS_CAL = RXFDET_HYS_CAL_A; +defparam gt11_a.RXFDET_HYS_SEL = RXFDET_HYS_SEL_A; +defparam gt11_a.RXFDET_LCK_CAL = RXFDET_LCK_CAL_A; +defparam gt11_a.RXFDET_LCK_SEL = RXFDET_LCK_SEL_A; +defparam gt11_a.RXFECONTROL1 = RXFECONTROL1_A; +defparam gt11_a.RXFECONTROL2 = RXFECONTROL2_A; +defparam gt11_a.RXFETUNE = RXFETUNE_A; +defparam gt11_a.RXLB = RXLB_A; +defparam gt11_a.RXLKADJ = RXLKADJ_A; +defparam gt11_a.RXLKAPD = RXLKAPD_A; +defparam gt11_a.RXLOOPCAL_WAIT = RXLOOPCAL_WAIT_A; +defparam gt11_a.RXLOOPFILT = RXLOOPFILT_A; +defparam gt11_a.RXMODE = RXMODE_A; +defparam gt11_a.RXOUTDIV2SEL = RXOUTDIV2SEL_A; +defparam gt11_a.RXPD = RXPD_A; +defparam gt11_a.RXPDDTST = RXPDDTST_A; +defparam gt11_a.RXPLLNDIVSEL = RXPLLNDIVSEL_A; +defparam gt11_a.RXPMACLKSEL = RXPMACLKSEL_A; +defparam gt11_a.RXRCPADJ = RXRCPADJ_A; +defparam gt11_a.RXRCPPD = RXRCPPD_A; +defparam gt11_a.RXRECCLK1_USE_SYNC = RXRECCLK1_USE_SYNC_A; +defparam gt11_a.RXRIBADJ = RXRIBADJ_A; +defparam gt11_a.RXRPDPD = RXRPDPD_A; +defparam gt11_a.RXRSDPD = RXRSDPD_A; +defparam gt11_a.RXSLOWDOWN_CAL = RXSLOWDOWN_CAL_A; +defparam gt11_a.RXTUNE = RXTUNE_A; +defparam gt11_a.RXUSRDIVISOR = RXUSRDIVISOR_A; +defparam gt11_a.RXVCODAC_INIT = RXVCODAC_INIT_A; +defparam gt11_a.RXVCO_CTRL_ENABLE = RXVCO_CTRL_ENABLE_A; +defparam gt11_a.RX_BUFFER_USE = RX_BUFFER_USE_A; +defparam gt11_a.RX_CLOCK_DIVIDER = RX_CLOCK_DIVIDER_A; +defparam gt11_a.SAMPLE_8X = SAMPLE_8X_A; +defparam gt11_a.SH_CNT_MAX = SH_CNT_MAX_A; +defparam gt11_a.SH_INVALID_CNT_MAX = SH_INVALID_CNT_MAX_A; +defparam gt11_a.SLOWDOWN_CAL = SLOWDOWN_CAL_A; +defparam gt11_a.TXABPMACLKSEL = TXABPMACLKSEL_A; +defparam gt11_a.TXAPD = TXAPD_A; +defparam gt11_a.TXAREFBIASSEL = TXAREFBIASSEL_A; +defparam gt11_a.TXASYNCDIVIDE = TXASYNCDIVIDE_A; +defparam gt11_a.TXCLK0_FORCE_PMACLK = TXCLK0_FORCE_PMACLK_A; +defparam gt11_a.TXCLKMODE = TXCLKMODE_A; +defparam gt11_a.TXCLMODE = TXCLMODE_A; +defparam gt11_a.TXCPSEL = TXCPSEL_A; +defparam gt11_a.TXCRCCLOCKDOUBLE = TXCRCCLOCKDOUBLE_A; +defparam gt11_a.TXCRCENABLE = TXCRCENABLE_A; +defparam gt11_a.TXCRCINITVAL = TXCRCINITVAL_A; +defparam gt11_a.TXCRCINVERTGEN = TXCRCINVERTGEN_A; +defparam gt11_a.TXCRCSAMECLOCK = TXCRCSAMECLOCK_A; +defparam gt11_a.TXCTRL1 = TXCTRL1_A; +defparam gt11_a.TXDATA_SEL = TXDATA_SEL_A; +defparam gt11_a.TXDAT_PRDRV_DAC = TXDAT_PRDRV_DAC_A; +defparam gt11_a.TXDAT_TAP_DAC = TXDAT_TAP_DAC_A; +defparam gt11_a.TXDIGPD = TXDIGPD_A; +defparam gt11_a.TXFDCAL_CLOCK_DIVIDE = TXFDCAL_CLOCK_DIVIDE_A; +defparam gt11_a.TXHIGHSIGNALEN = TXHIGHSIGNALEN_A; +defparam gt11_a.TXLOOPFILT = TXLOOPFILT_A; +defparam gt11_a.TXLVLSHFTPD = TXLVLSHFTPD_A; +defparam gt11_a.TXOUTCLK1_USE_SYNC = TXOUTCLK1_USE_SYNC_A; +defparam gt11_a.TXOUTDIV2SEL = TXOUTDIV2SEL_A; +defparam gt11_a.TXPD = TXPD_A; +defparam gt11_a.TXPHASESEL = TXPHASESEL_A; +defparam gt11_a.TXPLLNDIVSEL = TXPLLNDIVSEL_A; +defparam gt11_a.TXPOST_PRDRV_DAC = TXPOST_PRDRV_DAC_A; +defparam gt11_a.TXPOST_TAP_DAC = TXPOST_TAP_DAC_A; +defparam gt11_a.TXPOST_TAP_PD = TXPOST_TAP_PD_A; +defparam gt11_a.TXPRE_PRDRV_DAC = TXPRE_PRDRV_DAC_A; +defparam gt11_a.TXPRE_TAP_DAC = TXPRE_TAP_DAC_A; +defparam gt11_a.TXPRE_TAP_PD = TXPRE_TAP_PD_A; +defparam gt11_a.TXSLEWRATE = TXSLEWRATE_A; +defparam gt11_a.TXTERMTRIM = TXTERMTRIM_A; +defparam gt11_a.TXTUNE = TXTUNE_A; +defparam gt11_a.TX_BUFFER_USE = TX_BUFFER_USE_A; +defparam gt11_a.TX_CLOCK_DIVIDER = TX_CLOCK_DIVIDER_A; +defparam gt11_a.VCODAC_INIT = VCODAC_INIT_A; +defparam gt11_a.VCO_CTRL_ENABLE = VCO_CTRL_ENABLE_A; +defparam gt11_a.VREFBIASMODE = VREFBIASMODE_A; + +defparam gt11_b.ALIGN_COMMA_WORD = ALIGN_COMMA_WORD_B; +defparam gt11_b.BANDGAPSEL = BANDGAPSEL_B; +defparam gt11_b.BIASRESSEL = BIASRESSEL_B; +defparam gt11_b.CCCB_ARBITRATOR_DISABLE = CCCB_ARBITRATOR_DISABLE_B; +defparam gt11_b.CHAN_BOND_LIMIT = CHAN_BOND_LIMIT_B; +defparam gt11_b.CHAN_BOND_MODE = CHAN_BOND_MODE_B; +defparam gt11_b.CHAN_BOND_ONE_SHOT = CHAN_BOND_ONE_SHOT_B; +defparam gt11_b.CHAN_BOND_SEQ_1_1 = CHAN_BOND_SEQ_1_1_B; +defparam gt11_b.CHAN_BOND_SEQ_1_2 = CHAN_BOND_SEQ_1_2_B; +defparam gt11_b.CHAN_BOND_SEQ_1_3 = CHAN_BOND_SEQ_1_3_B; +defparam gt11_b.CHAN_BOND_SEQ_1_4 = CHAN_BOND_SEQ_1_4_B; +defparam gt11_b.CHAN_BOND_SEQ_1_MASK = CHAN_BOND_SEQ_1_MASK_B; +defparam gt11_b.CHAN_BOND_SEQ_2_1 = CHAN_BOND_SEQ_2_1_B; +defparam gt11_b.CHAN_BOND_SEQ_2_2 = CHAN_BOND_SEQ_2_2_B; +defparam gt11_b.CHAN_BOND_SEQ_2_3 = CHAN_BOND_SEQ_2_3_B; +defparam gt11_b.CHAN_BOND_SEQ_2_4 = CHAN_BOND_SEQ_2_4_B; +defparam gt11_b.CHAN_BOND_SEQ_2_MASK = CHAN_BOND_SEQ_2_MASK_B; +defparam gt11_b.CHAN_BOND_SEQ_2_USE = CHAN_BOND_SEQ_2_USE_B; +defparam gt11_b.CHAN_BOND_SEQ_LEN = CHAN_BOND_SEQ_LEN_B; +defparam gt11_b.CLK_CORRECT_USE = CLK_CORRECT_USE_B; +defparam gt11_b.CLK_COR_8B10B_DE = CLK_COR_8B10B_DE_B; +defparam gt11_b.CLK_COR_MAX_LAT = CLK_COR_MAX_LAT_B; +defparam gt11_b.CLK_COR_MIN_LAT = CLK_COR_MIN_LAT_B; +defparam gt11_b.CLK_COR_SEQ_1_1 = CLK_COR_SEQ_1_1_B; +defparam gt11_b.CLK_COR_SEQ_1_2 = CLK_COR_SEQ_1_2_B; +defparam gt11_b.CLK_COR_SEQ_1_3 = CLK_COR_SEQ_1_3_B; +defparam gt11_b.CLK_COR_SEQ_1_4 = CLK_COR_SEQ_1_4_B; +defparam gt11_b.CLK_COR_SEQ_1_MASK = CLK_COR_SEQ_1_MASK_B; +defparam gt11_b.CLK_COR_SEQ_2_1 = CLK_COR_SEQ_2_1_B; +defparam gt11_b.CLK_COR_SEQ_2_2 = CLK_COR_SEQ_2_2_B; +defparam gt11_b.CLK_COR_SEQ_2_3 = CLK_COR_SEQ_2_3_B; +defparam gt11_b.CLK_COR_SEQ_2_4 = CLK_COR_SEQ_2_4_B; +defparam gt11_b.CLK_COR_SEQ_2_MASK = CLK_COR_SEQ_2_MASK_B; +defparam gt11_b.CLK_COR_SEQ_2_USE = CLK_COR_SEQ_2_USE_B; +defparam gt11_b.CLK_COR_SEQ_DROP = CLK_COR_SEQ_DROP_B; +defparam gt11_b.CLK_COR_SEQ_LEN = CLK_COR_SEQ_LEN_B; +defparam gt11_b.COMMA32 = COMMA32_B; +defparam gt11_b.COMMA_10B_MASK = COMMA_10B_MASK_B; +defparam gt11_b.CYCLE_LIMIT_SEL = CYCLE_LIMIT_SEL_B; +defparam gt11_b.DCDR_FILTER = DCDR_FILTER_B; +defparam gt11_b.DEC_MCOMMA_DETECT = DEC_MCOMMA_DETECT_B; +defparam gt11_b.DEC_PCOMMA_DETECT = DEC_PCOMMA_DETECT_B; +defparam gt11_b.DEC_VALID_COMMA_ONLY = DEC_VALID_COMMA_ONLY_B; +defparam gt11_b.DIGRX_FWDCLK = DIGRX_FWDCLK_B; +defparam gt11_b.DIGRX_SYNC_MODE = DIGRX_SYNC_MODE_B; +defparam gt11_b.ENABLE_DCDR = ENABLE_DCDR_B; +defparam gt11_b.FDET_HYS_CAL = FDET_HYS_CAL_B; +defparam gt11_b.FDET_HYS_SEL = FDET_HYS_SEL_B; +defparam gt11_b.FDET_LCK_CAL = FDET_LCK_CAL_B; +defparam gt11_b.FDET_LCK_SEL = FDET_LCK_SEL_B; +defparam gt11_b.GT11_MODE = "B"; +defparam gt11_b.IREFBIASMODE = IREFBIASMODE_B; +defparam gt11_b.LOOPCAL_WAIT = LOOPCAL_WAIT_B; +defparam gt11_b.MCOMMA_32B_VALUE = MCOMMA_32B_VALUE_B; +defparam gt11_b.MCOMMA_DETECT = MCOMMA_DETECT_B; +defparam gt11_b.OPPOSITE_SELECT = OPPOSITE_SELECT_B; +defparam gt11_b.PCOMMA_32B_VALUE = PCOMMA_32B_VALUE_B; +defparam gt11_b.PCOMMA_DETECT = PCOMMA_DETECT_B; +defparam gt11_b.PCS_BIT_SLIP = PCS_BIT_SLIP_B; +defparam gt11_b.PMACLKENABLE = PMACLKENABLE_B; +defparam gt11_b.PMACOREPWRENABLE = PMACOREPWRENABLE_B; +defparam gt11_b.PMAIREFTRIM = PMAIREFTRIM_B; +defparam gt11_b.PMAVBGCTRL = PMAVBGCTRL_B; +defparam gt11_b.PMAVREFTRIM = PMAVREFTRIM_B; +defparam gt11_b.PMA_BIT_SLIP = PMA_BIT_SLIP_B; +defparam gt11_b.POWER_ENABLE = POWER_ENABLE_B; +defparam gt11_b.REPEATER = REPEATER_B; +defparam gt11_b.RXACTST = RXACTST_B; +defparam gt11_b.RXAFEEQ = RXAFEEQ_B; +defparam gt11_b.RXAFEPD = RXAFEPD_B; +defparam gt11_b.RXAFETST = RXAFETST_B; +defparam gt11_b.RXAPD = RXAPD_B; +defparam gt11_a.RXAREGCTRL = RXAREGCTRL_B; +defparam gt11_b.RXASYNCDIVIDE = RXASYNCDIVIDE_B; +defparam gt11_b.RXBY_32 = RXBY_32_B; +defparam gt11_b.RXCDRLOS = RXCDRLOS_B; +defparam gt11_b.RXCLK0_FORCE_PMACLK = RXCLK0_FORCE_PMACLK_B; +defparam gt11_b.RXCLKMODE = RXCLKMODE_B; +defparam gt11_a.RXCLMODE = RXCLMODE_B; +defparam gt11_b.RXCMADJ = RXCMADJ_B; +defparam gt11_b.RXCPSEL = RXCPSEL_B; +defparam gt11_b.RXCPTST = RXCPTST_B; +defparam gt11_b.RXCRCCLOCKDOUBLE = RXCRCCLOCKDOUBLE_B; +defparam gt11_b.RXCRCENABLE = RXCRCENABLE_B; +defparam gt11_b.RXCRCINITVAL = RXCRCINITVAL_B; +defparam gt11_b.RXCRCINVERTGEN = RXCRCINVERTGEN_B; +defparam gt11_b.RXCRCSAMECLOCK = RXCRCSAMECLOCK_B; +defparam gt11_b.RXCTRL1 = RXCTRL1_B; +defparam gt11_b.RXCYCLE_LIMIT_SEL = RXCYCLE_LIMIT_SEL_B; +defparam gt11_b.RXDATA_SEL = RXDATA_SEL_B; +defparam gt11_b.RXDCCOUPLE = RXDCCOUPLE_B; +defparam gt11_b.RXDIGRESET = RXDIGRESET_B; +defparam gt11_b.RXDIGRX = RXDIGRX_B; +defparam gt11_b.RXEQ = RXEQ_B; +defparam gt11_b.RXFDCAL_CLOCK_DIVIDE = RXFDCAL_CLOCK_DIVIDE_B; +defparam gt11_b.RXFDET_HYS_CAL = RXFDET_HYS_CAL_B; +defparam gt11_b.RXFDET_HYS_SEL = RXFDET_HYS_SEL_B; +defparam gt11_b.RXFDET_LCK_CAL = RXFDET_LCK_CAL_B; +defparam gt11_b.RXFDET_LCK_SEL = RXFDET_LCK_SEL_B; +defparam gt11_b.RXFECONTROL1 = RXFECONTROL1_B; +defparam gt11_b.RXFECONTROL2 = RXFECONTROL2_B; +defparam gt11_b.RXFETUNE = RXFETUNE_B; +defparam gt11_b.RXLB = RXLB_B; +defparam gt11_b.RXLKADJ = RXLKADJ_B; +defparam gt11_b.RXLKAPD = RXLKAPD_B; +defparam gt11_b.RXLOOPCAL_WAIT = RXLOOPCAL_WAIT_B; +defparam gt11_b.RXLOOPFILT = RXLOOPFILT_B; +defparam gt11_a.RXMODE = RXMODE_B; +defparam gt11_b.RXOUTDIV2SEL = RXOUTDIV2SEL_B; +defparam gt11_b.RXPD = RXPD_B; +defparam gt11_b.RXPDDTST = RXPDDTST_B; +defparam gt11_b.RXPLLNDIVSEL = RXPLLNDIVSEL_B; +defparam gt11_b.RXPMACLKSEL = RXPMACLKSEL_B; +defparam gt11_b.RXRCPADJ = RXRCPADJ_B; +defparam gt11_b.RXRCPPD = RXRCPPD_B; +defparam gt11_b.RXRECCLK1_USE_SYNC = RXRECCLK1_USE_SYNC_B; +defparam gt11_b.RXRIBADJ = RXRIBADJ_B; +defparam gt11_b.RXRPDPD = RXRPDPD_B; +defparam gt11_b.RXRSDPD = RXRSDPD_B; +defparam gt11_b.RXSLOWDOWN_CAL = RXSLOWDOWN_CAL_B; +defparam gt11_a.RXTUNE = RXTUNE_B; +defparam gt11_b.RXUSRDIVISOR = RXUSRDIVISOR_B; +defparam gt11_b.RXVCODAC_INIT = RXVCODAC_INIT_B; +defparam gt11_b.RXVCO_CTRL_ENABLE = RXVCO_CTRL_ENABLE_B; +defparam gt11_b.RX_BUFFER_USE = RX_BUFFER_USE_B; +defparam gt11_b.RX_CLOCK_DIVIDER = RX_CLOCK_DIVIDER_B; +defparam gt11_b.SAMPLE_8X = SAMPLE_8X_B; +defparam gt11_b.SH_CNT_MAX = SH_CNT_MAX_B; +defparam gt11_b.SH_INVALID_CNT_MAX = SH_INVALID_CNT_MAX_B; +defparam gt11_b.SLOWDOWN_CAL = SLOWDOWN_CAL_B; +defparam gt11_b.TXABPMACLKSEL = TXABPMACLKSEL_B; +defparam gt11_b.TXAPD = TXAPD_B; +defparam gt11_b.TXAREFBIASSEL = TXAREFBIASSEL_B; +defparam gt11_b.TXASYNCDIVIDE = TXASYNCDIVIDE_B; +defparam gt11_b.TXCLK0_FORCE_PMACLK = TXCLK0_FORCE_PMACLK_B; +defparam gt11_b.TXCLKMODE = TXCLKMODE_B; +defparam gt11_a.TXCLMODE = TXCLMODE_B; +defparam gt11_b.TXCPSEL = TXCPSEL_B; +defparam gt11_b.TXCRCCLOCKDOUBLE = TXCRCCLOCKDOUBLE_B; +defparam gt11_b.TXCRCENABLE = TXCRCENABLE_B; +defparam gt11_b.TXCRCINITVAL = TXCRCINITVAL_B; +defparam gt11_b.TXCRCINVERTGEN = TXCRCINVERTGEN_B; +defparam gt11_b.TXCRCSAMECLOCK = TXCRCSAMECLOCK_B; +defparam gt11_b.TXCTRL1 = TXCTRL1_B; +defparam gt11_b.TXDATA_SEL = TXDATA_SEL_B; +defparam gt11_b.TXDAT_PRDRV_DAC = TXDAT_PRDRV_DAC_B; +defparam gt11_b.TXDAT_TAP_DAC = TXDAT_TAP_DAC_B; +defparam gt11_b.TXDIGPD = TXDIGPD_B; +defparam gt11_b.TXFDCAL_CLOCK_DIVIDE = TXFDCAL_CLOCK_DIVIDE_B; +defparam gt11_b.TXHIGHSIGNALEN = TXHIGHSIGNALEN_B; +defparam gt11_b.TXLOOPFILT = TXLOOPFILT_B; +defparam gt11_b.TXLVLSHFTPD = TXLVLSHFTPD_B; +defparam gt11_b.TXOUTCLK1_USE_SYNC = TXOUTCLK1_USE_SYNC_B; +defparam gt11_b.TXOUTDIV2SEL = TXOUTDIV2SEL_B; +defparam gt11_b.TXPD = TXPD_B; +defparam gt11_b.TXPHASESEL = TXPHASESEL_B; +defparam gt11_b.TXPLLNDIVSEL = TXPLLNDIVSEL_B; +defparam gt11_b.TXPOST_PRDRV_DAC = TXPOST_PRDRV_DAC_B; +defparam gt11_b.TXPOST_TAP_DAC = TXPOST_TAP_DAC_B; +defparam gt11_b.TXPOST_TAP_PD = TXPOST_TAP_PD_B; +defparam gt11_b.TXPRE_PRDRV_DAC = TXPRE_PRDRV_DAC_B; +defparam gt11_b.TXPRE_TAP_DAC = TXPRE_TAP_DAC_B; +defparam gt11_b.TXPRE_TAP_PD = TXPRE_TAP_PD_B; +defparam gt11_b.TXSLEWRATE = TXSLEWRATE_B; +defparam gt11_b.TXTERMTRIM = TXTERMTRIM_B; +defparam gt11_a.TXTUNE = TXTUNE_B; +defparam gt11_b.TX_BUFFER_USE = TX_BUFFER_USE_B; +defparam gt11_b.TX_CLOCK_DIVIDER = TX_CLOCK_DIVIDER_B; +defparam gt11_b.VCODAC_INIT = VCODAC_INIT_B; +defparam gt11_b.VCO_CTRL_ENABLE = VCO_CTRL_ENABLE_B; +defparam gt11_b.VREFBIASMODE = VREFBIASMODE_B; + + +endmodule diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/GTHE1_QUAD.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/GTHE1_QUAD.v new file mode 100644 index 0000000..5b2bfa9 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/GTHE1_QUAD.v @@ -0,0 +1,2266 @@ +/////////////////////////////////////////////////////// +// Copyright (c) 2010 Xilinx Inc. +// All Right Reserved. +/////////////////////////////////////////////////////// +// +// ____ ___ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Gigabit Transceiver +// /__/ /\ Filename : GTHE1_QUAD.v +// \ \ / \ +// \__\/\__ \ +// +// Revision: 1.0 +// 05/29/09 - CR523112 - Initial version +// 06/16/09 - CR523112 - Parameter update in YML +// 06/24/09 - CR523112 - YML update +// 07/07/09 - CR526271 - secureip publish +// 07/14/09 - CR527136 - specify block update +// 10/01/09 - CR534680 - YML Attribute updates +// 01/26/10 - CR546178 - YML new output pins & parameter default update +// 02/10/10 - CR543263 - Add new output pin connections in B_GTHE1_QUAD_INST +// 03/22/10 - CR552516 - DRC checks added +///////////////////////////////////////////////////////// + +`timescale 1 ps / 1 ps + +module GTHE1_QUAD ( + DRDY, + DRPDO, + GTHINITDONE, + MGMTPCSRDACK, + MGMTPCSRDDATA, + RXCODEERR0, + RXCODEERR1, + RXCODEERR2, + RXCODEERR3, + RXCTRL0, + RXCTRL1, + RXCTRL2, + RXCTRL3, + RXCTRLACK0, + RXCTRLACK1, + RXCTRLACK2, + RXCTRLACK3, + RXDATA0, + RXDATA1, + RXDATA2, + RXDATA3, + RXDATATAP0, + RXDATATAP1, + RXDATATAP2, + RXDATATAP3, + RXDISPERR0, + RXDISPERR1, + RXDISPERR2, + RXDISPERR3, + RXPCSCLKSMPL0, + RXPCSCLKSMPL1, + RXPCSCLKSMPL2, + RXPCSCLKSMPL3, + RXUSERCLKOUT0, + RXUSERCLKOUT1, + RXUSERCLKOUT2, + RXUSERCLKOUT3, + RXVALID0, + RXVALID1, + RXVALID2, + RXVALID3, + TSTPATH, + TSTREFCLKFAB, + TSTREFCLKOUT, + TXCTRLACK0, + TXCTRLACK1, + TXCTRLACK2, + TXCTRLACK3, + TXDATATAP10, + TXDATATAP11, + TXDATATAP12, + TXDATATAP13, + TXDATATAP20, + TXDATATAP21, + TXDATATAP22, + TXDATATAP23, + TXN0, + TXN1, + TXN2, + TXN3, + TXP0, + TXP1, + TXP2, + TXP3, + TXPCSCLKSMPL0, + TXPCSCLKSMPL1, + TXPCSCLKSMPL2, + TXPCSCLKSMPL3, + TXUSERCLKOUT0, + TXUSERCLKOUT1, + TXUSERCLKOUT2, + TXUSERCLKOUT3, + DADDR, + DCLK, + DEN, + DFETRAINCTRL0, + DFETRAINCTRL1, + DFETRAINCTRL2, + DFETRAINCTRL3, + DI, + DISABLEDRP, + DWE, + GTHINIT, + GTHRESET, + GTHX2LANE01, + GTHX2LANE23, + GTHX4LANE, + MGMTPCSLANESEL, + MGMTPCSMMDADDR, + MGMTPCSREGADDR, + MGMTPCSREGRD, + MGMTPCSREGWR, + MGMTPCSWRDATA, + PLLPCSCLKDIV, + PLLREFCLKSEL, + POWERDOWN0, + POWERDOWN1, + POWERDOWN2, + POWERDOWN3, + REFCLK, + RXBUFRESET0, + RXBUFRESET1, + RXBUFRESET2, + RXBUFRESET3, + RXENCOMMADET0, + RXENCOMMADET1, + RXENCOMMADET2, + RXENCOMMADET3, + RXN0, + RXN1, + RXN2, + RXN3, + RXP0, + RXP1, + RXP2, + RXP3, + RXPOLARITY0, + RXPOLARITY1, + RXPOLARITY2, + RXPOLARITY3, + RXPOWERDOWN0, + RXPOWERDOWN1, + RXPOWERDOWN2, + RXPOWERDOWN3, + RXRATE0, + RXRATE1, + RXRATE2, + RXRATE3, + RXSLIP0, + RXSLIP1, + RXSLIP2, + RXSLIP3, + RXUSERCLKIN0, + RXUSERCLKIN1, + RXUSERCLKIN2, + RXUSERCLKIN3, + SAMPLERATE0, + SAMPLERATE1, + SAMPLERATE2, + SAMPLERATE3, + TXBUFRESET0, + TXBUFRESET1, + TXBUFRESET2, + TXBUFRESET3, + TXCTRL0, + TXCTRL1, + TXCTRL2, + TXCTRL3, + TXDATA0, + TXDATA1, + TXDATA2, + TXDATA3, + TXDATAMSB0, + TXDATAMSB1, + TXDATAMSB2, + TXDATAMSB3, + TXDEEMPH0, + TXDEEMPH1, + TXDEEMPH2, + TXDEEMPH3, + TXMARGIN0, + TXMARGIN1, + TXMARGIN2, + TXMARGIN3, + TXPOWERDOWN0, + TXPOWERDOWN1, + TXPOWERDOWN2, + TXPOWERDOWN3, + TXRATE0, + TXRATE1, + TXRATE2, + TXRATE3, + TXUSERCLKIN0, + TXUSERCLKIN1, + TXUSERCLKIN2, + TXUSERCLKIN3 +); + + parameter [15:0] BER_CONST_PTRN0 = 16'h0000; + parameter [15:0] BER_CONST_PTRN1 = 16'h0000; + parameter [15:0] BUFFER_CONFIG_LANE0 = 16'h4004; + parameter [15:0] BUFFER_CONFIG_LANE1 = 16'h4004; + parameter [15:0] BUFFER_CONFIG_LANE2 = 16'h4004; + parameter [15:0] BUFFER_CONFIG_LANE3 = 16'h4004; + parameter [15:0] DFE_TRAIN_CTRL_LANE0 = 16'h0000; + parameter [15:0] DFE_TRAIN_CTRL_LANE1 = 16'h0000; + parameter [15:0] DFE_TRAIN_CTRL_LANE2 = 16'h0000; + parameter [15:0] DFE_TRAIN_CTRL_LANE3 = 16'h0000; + parameter [15:0] DLL_CFG0 = 16'h4201; + parameter [15:0] DLL_CFG1 = 16'h0000; + parameter [15:0] E10GBASEKR_LD_COEFF_UPD_LANE0 = 16'h0000; + parameter [15:0] E10GBASEKR_LD_COEFF_UPD_LANE1 = 16'h0000; + parameter [15:0] E10GBASEKR_LD_COEFF_UPD_LANE2 = 16'h0000; + parameter [15:0] E10GBASEKR_LD_COEFF_UPD_LANE3 = 16'h0000; + parameter [15:0] E10GBASEKR_LP_COEFF_UPD_LANE0 = 16'h0000; + parameter [15:0] E10GBASEKR_LP_COEFF_UPD_LANE1 = 16'h0000; + parameter [15:0] E10GBASEKR_LP_COEFF_UPD_LANE2 = 16'h0000; + parameter [15:0] E10GBASEKR_LP_COEFF_UPD_LANE3 = 16'h0000; + parameter [15:0] E10GBASEKR_PMA_CTRL_LANE0 = 16'h0002; + parameter [15:0] E10GBASEKR_PMA_CTRL_LANE1 = 16'h0002; + parameter [15:0] E10GBASEKR_PMA_CTRL_LANE2 = 16'h0002; + parameter [15:0] E10GBASEKR_PMA_CTRL_LANE3 = 16'h0002; + parameter [15:0] E10GBASEKX_CTRL_LANE0 = 16'h0000; + parameter [15:0] E10GBASEKX_CTRL_LANE1 = 16'h0000; + parameter [15:0] E10GBASEKX_CTRL_LANE2 = 16'h0000; + parameter [15:0] E10GBASEKX_CTRL_LANE3 = 16'h0000; + parameter [15:0] E10GBASER_PCS_CFG_LANE0 = 16'h070C; + parameter [15:0] E10GBASER_PCS_CFG_LANE1 = 16'h070C; + parameter [15:0] E10GBASER_PCS_CFG_LANE2 = 16'h070C; + parameter [15:0] E10GBASER_PCS_CFG_LANE3 = 16'h070C; + parameter [15:0] E10GBASER_PCS_SEEDA0_LANE0 = 16'h0001; + parameter [15:0] E10GBASER_PCS_SEEDA0_LANE1 = 16'h0001; + parameter [15:0] E10GBASER_PCS_SEEDA0_LANE2 = 16'h0001; + parameter [15:0] E10GBASER_PCS_SEEDA0_LANE3 = 16'h0001; + parameter [15:0] E10GBASER_PCS_SEEDA1_LANE0 = 16'h0000; + parameter [15:0] E10GBASER_PCS_SEEDA1_LANE1 = 16'h0000; + parameter [15:0] E10GBASER_PCS_SEEDA1_LANE2 = 16'h0000; + parameter [15:0] E10GBASER_PCS_SEEDA1_LANE3 = 16'h0000; + parameter [15:0] E10GBASER_PCS_SEEDA2_LANE0 = 16'h0000; + parameter [15:0] E10GBASER_PCS_SEEDA2_LANE1 = 16'h0000; + parameter [15:0] E10GBASER_PCS_SEEDA2_LANE2 = 16'h0000; + parameter [15:0] E10GBASER_PCS_SEEDA2_LANE3 = 16'h0000; + parameter [15:0] E10GBASER_PCS_SEEDA3_LANE0 = 16'h0000; + parameter [15:0] E10GBASER_PCS_SEEDA3_LANE1 = 16'h0000; + parameter [15:0] E10GBASER_PCS_SEEDA3_LANE2 = 16'h0000; + parameter [15:0] E10GBASER_PCS_SEEDA3_LANE3 = 16'h0000; + parameter [15:0] E10GBASER_PCS_SEEDB0_LANE0 = 16'h0001; + parameter [15:0] E10GBASER_PCS_SEEDB0_LANE1 = 16'h0001; + parameter [15:0] E10GBASER_PCS_SEEDB0_LANE2 = 16'h0001; + parameter [15:0] E10GBASER_PCS_SEEDB0_LANE3 = 16'h0001; + parameter [15:0] E10GBASER_PCS_SEEDB1_LANE0 = 16'h0000; + parameter [15:0] E10GBASER_PCS_SEEDB1_LANE1 = 16'h0000; + parameter [15:0] E10GBASER_PCS_SEEDB1_LANE2 = 16'h0000; + parameter [15:0] E10GBASER_PCS_SEEDB1_LANE3 = 16'h0000; + parameter [15:0] E10GBASER_PCS_SEEDB2_LANE0 = 16'h0000; + parameter [15:0] E10GBASER_PCS_SEEDB2_LANE1 = 16'h0000; + parameter [15:0] E10GBASER_PCS_SEEDB2_LANE2 = 16'h0000; + parameter [15:0] E10GBASER_PCS_SEEDB2_LANE3 = 16'h0000; + parameter [15:0] E10GBASER_PCS_SEEDB3_LANE0 = 16'h0000; + parameter [15:0] E10GBASER_PCS_SEEDB3_LANE1 = 16'h0000; + parameter [15:0] E10GBASER_PCS_SEEDB3_LANE2 = 16'h0000; + parameter [15:0] E10GBASER_PCS_SEEDB3_LANE3 = 16'h0000; + parameter [15:0] E10GBASER_PCS_TEST_CTRL_LANE0 = 16'h0000; + parameter [15:0] E10GBASER_PCS_TEST_CTRL_LANE1 = 16'h0000; + parameter [15:0] E10GBASER_PCS_TEST_CTRL_LANE2 = 16'h0000; + parameter [15:0] E10GBASER_PCS_TEST_CTRL_LANE3 = 16'h0000; + parameter [15:0] E10GBASEX_PCS_TSTCTRL_LANE0 = 16'h0000; + parameter [15:0] E10GBASEX_PCS_TSTCTRL_LANE1 = 16'h0000; + parameter [15:0] E10GBASEX_PCS_TSTCTRL_LANE2 = 16'h0000; + parameter [15:0] E10GBASEX_PCS_TSTCTRL_LANE3 = 16'h0000; + parameter [15:0] GLBL0_NOISE_CTRL = 16'hF0B8; + parameter [15:0] GLBL_AMON_SEL = 16'h0000; + parameter [15:0] GLBL_DMON_SEL = 16'h0200; + parameter [15:0] GLBL_PWR_CTRL = 16'h0000; + parameter [0:0] GTH_CFG_PWRUP_LANE0 = 1'b1; + parameter [0:0] GTH_CFG_PWRUP_LANE1 = 1'b1; + parameter [0:0] GTH_CFG_PWRUP_LANE2 = 1'b1; + parameter [0:0] GTH_CFG_PWRUP_LANE3 = 1'b1; + parameter [15:0] LANE_AMON_SEL = 16'h00F0; + parameter [15:0] LANE_DMON_SEL = 16'h0000; + parameter [15:0] LANE_LNK_CFGOVRD = 16'h0000; + parameter [15:0] LANE_PWR_CTRL_LANE0 = 16'h0400; + parameter [15:0] LANE_PWR_CTRL_LANE1 = 16'h0400; + parameter [15:0] LANE_PWR_CTRL_LANE2 = 16'h0400; + parameter [15:0] LANE_PWR_CTRL_LANE3 = 16'h0400; + parameter [15:0] LNK_TRN_CFG_LANE0 = 16'h0000; + parameter [15:0] LNK_TRN_CFG_LANE1 = 16'h0000; + parameter [15:0] LNK_TRN_CFG_LANE2 = 16'h0000; + parameter [15:0] LNK_TRN_CFG_LANE3 = 16'h0000; + parameter [15:0] LNK_TRN_COEFF_REQ_LANE0 = 16'h0000; + parameter [15:0] LNK_TRN_COEFF_REQ_LANE1 = 16'h0000; + parameter [15:0] LNK_TRN_COEFF_REQ_LANE2 = 16'h0000; + parameter [15:0] LNK_TRN_COEFF_REQ_LANE3 = 16'h0000; + parameter [15:0] MISC_CFG = 16'h0004; + parameter [15:0] MODE_CFG1 = 16'h0000; + parameter [15:0] MODE_CFG2 = 16'h0000; + parameter [15:0] MODE_CFG3 = 16'h0000; + parameter [15:0] MODE_CFG4 = 16'h0000; + parameter [15:0] MODE_CFG5 = 16'h0000; + parameter [15:0] MODE_CFG6 = 16'h0000; + parameter [15:0] MODE_CFG7 = 16'h0000; + parameter [15:0] PCS_ABILITY_LANE0 = 16'h0010; + parameter [15:0] PCS_ABILITY_LANE1 = 16'h0010; + parameter [15:0] PCS_ABILITY_LANE2 = 16'h0010; + parameter [15:0] PCS_ABILITY_LANE3 = 16'h0010; + parameter [15:0] PCS_CTRL1_LANE0 = 16'h2040; + parameter [15:0] PCS_CTRL1_LANE1 = 16'h2040; + parameter [15:0] PCS_CTRL1_LANE2 = 16'h2040; + parameter [15:0] PCS_CTRL1_LANE3 = 16'h2040; + parameter [15:0] PCS_CTRL2_LANE0 = 16'h0000; + parameter [15:0] PCS_CTRL2_LANE1 = 16'h0000; + parameter [15:0] PCS_CTRL2_LANE2 = 16'h0000; + parameter [15:0] PCS_CTRL2_LANE3 = 16'h0000; + parameter [15:0] PCS_MISC_CFG_0_LANE0 = 16'h1117; + parameter [15:0] PCS_MISC_CFG_0_LANE1 = 16'h1117; + parameter [15:0] PCS_MISC_CFG_0_LANE2 = 16'h1117; + parameter [15:0] PCS_MISC_CFG_0_LANE3 = 16'h1117; + parameter [15:0] PCS_MISC_CFG_1_LANE0 = 16'h0000; + parameter [15:0] PCS_MISC_CFG_1_LANE1 = 16'h0000; + parameter [15:0] PCS_MISC_CFG_1_LANE2 = 16'h0000; + parameter [15:0] PCS_MISC_CFG_1_LANE3 = 16'h0000; + parameter [15:0] PCS_MODE_LANE0 = 16'h0000; + parameter [15:0] PCS_MODE_LANE1 = 16'h0000; + parameter [15:0] PCS_MODE_LANE2 = 16'h0000; + parameter [15:0] PCS_MODE_LANE3 = 16'h0000; + parameter [15:0] PCS_RESET_1_LANE0 = 16'h0002; + parameter [15:0] PCS_RESET_1_LANE1 = 16'h0002; + parameter [15:0] PCS_RESET_1_LANE2 = 16'h0002; + parameter [15:0] PCS_RESET_1_LANE3 = 16'h0002; + parameter [15:0] PCS_RESET_LANE0 = 16'h0000; + parameter [15:0] PCS_RESET_LANE1 = 16'h0000; + parameter [15:0] PCS_RESET_LANE2 = 16'h0000; + parameter [15:0] PCS_RESET_LANE3 = 16'h0000; + parameter [15:0] PCS_TYPE_LANE0 = 16'h002C; + parameter [15:0] PCS_TYPE_LANE1 = 16'h002C; + parameter [15:0] PCS_TYPE_LANE2 = 16'h002C; + parameter [15:0] PCS_TYPE_LANE3 = 16'h002C; + parameter [15:0] PLL_CFG0 = 16'h58C0; + parameter [15:0] PLL_CFG1 = 16'h8440; + parameter [15:0] PLL_CFG2 = 16'h0424; + parameter [15:0] PMA_CTRL1_LANE0 = 16'h0000; + parameter [15:0] PMA_CTRL1_LANE1 = 16'h0000; + parameter [15:0] PMA_CTRL1_LANE2 = 16'h0000; + parameter [15:0] PMA_CTRL1_LANE3 = 16'h0000; + parameter [15:0] PMA_CTRL2_LANE0 = 16'h000B; + parameter [15:0] PMA_CTRL2_LANE1 = 16'h000B; + parameter [15:0] PMA_CTRL2_LANE2 = 16'h000B; + parameter [15:0] PMA_CTRL2_LANE3 = 16'h000B; + parameter [15:0] PMA_LPBK_CTRL_LANE0 = 16'h0004; + parameter [15:0] PMA_LPBK_CTRL_LANE1 = 16'h0004; + parameter [15:0] PMA_LPBK_CTRL_LANE2 = 16'h0004; + parameter [15:0] PMA_LPBK_CTRL_LANE3 = 16'h0004; + parameter [15:0] PRBS_BER_CFG0_LANE0 = 16'h0000; + parameter [15:0] PRBS_BER_CFG0_LANE1 = 16'h0000; + parameter [15:0] PRBS_BER_CFG0_LANE2 = 16'h0000; + parameter [15:0] PRBS_BER_CFG0_LANE3 = 16'h0000; + parameter [15:0] PRBS_BER_CFG1_LANE0 = 16'h0000; + parameter [15:0] PRBS_BER_CFG1_LANE1 = 16'h0000; + parameter [15:0] PRBS_BER_CFG1_LANE2 = 16'h0000; + parameter [15:0] PRBS_BER_CFG1_LANE3 = 16'h0000; + parameter [15:0] PRBS_CFG_LANE0 = 16'h000A; + parameter [15:0] PRBS_CFG_LANE1 = 16'h000A; + parameter [15:0] PRBS_CFG_LANE2 = 16'h000A; + parameter [15:0] PRBS_CFG_LANE3 = 16'h000A; + parameter [15:0] PTRN_CFG0_LSB = 16'h5555; + parameter [15:0] PTRN_CFG0_MSB = 16'h5555; + parameter [15:0] PTRN_LEN_CFG = 16'h001F; + parameter [15:0] PWRUP_DLY = 16'h0000; + parameter [15:0] RX_AEQ_VAL0_LANE0 = 16'h0100; + parameter [15:0] RX_AEQ_VAL0_LANE1 = 16'h0100; + parameter [15:0] RX_AEQ_VAL0_LANE2 = 16'h0100; + parameter [15:0] RX_AEQ_VAL0_LANE3 = 16'h0100; + parameter [15:0] RX_AEQ_VAL1_LANE0 = 16'h0000; + parameter [15:0] RX_AEQ_VAL1_LANE1 = 16'h0000; + parameter [15:0] RX_AEQ_VAL1_LANE2 = 16'h0000; + parameter [15:0] RX_AEQ_VAL1_LANE3 = 16'h0000; + parameter [15:0] RX_AGC_CTRL_LANE0 = 16'h0000; + parameter [15:0] RX_AGC_CTRL_LANE1 = 16'h0000; + parameter [15:0] RX_AGC_CTRL_LANE2 = 16'h0000; + parameter [15:0] RX_AGC_CTRL_LANE3 = 16'h0000; + parameter [15:0] RX_CDR_CTRL0_LANE0 = 16'h0005; + parameter [15:0] RX_CDR_CTRL0_LANE1 = 16'h0005; + parameter [15:0] RX_CDR_CTRL0_LANE2 = 16'h0005; + parameter [15:0] RX_CDR_CTRL0_LANE3 = 16'h0005; + parameter [15:0] RX_CDR_CTRL1_LANE0 = 16'h4300; + parameter [15:0] RX_CDR_CTRL1_LANE1 = 16'h4300; + parameter [15:0] RX_CDR_CTRL1_LANE2 = 16'h4300; + parameter [15:0] RX_CDR_CTRL1_LANE3 = 16'h4300; + parameter [15:0] RX_CDR_CTRL2_LANE0 = 16'h2000; + parameter [15:0] RX_CDR_CTRL2_LANE1 = 16'h2000; + parameter [15:0] RX_CDR_CTRL2_LANE2 = 16'h2000; + parameter [15:0] RX_CDR_CTRL2_LANE3 = 16'h2000; + parameter [15:0] RX_CFG0_LANE0 = 16'h0B06; + parameter [15:0] RX_CFG0_LANE1 = 16'h0B06; + parameter [15:0] RX_CFG0_LANE2 = 16'h0B06; + parameter [15:0] RX_CFG0_LANE3 = 16'h0B06; + parameter [15:0] RX_CFG1_LANE0 = 16'h817F; + parameter [15:0] RX_CFG1_LANE1 = 16'h817F; + parameter [15:0] RX_CFG1_LANE2 = 16'h817F; + parameter [15:0] RX_CFG1_LANE3 = 16'h817F; + parameter [15:0] RX_CFG2_LANE0 = 16'h1000; + parameter [15:0] RX_CFG2_LANE1 = 16'h1000; + parameter [15:0] RX_CFG2_LANE2 = 16'h1000; + parameter [15:0] RX_CFG2_LANE3 = 16'h1000; + parameter [15:0] RX_CTLE_CTRL_LANE0 = 16'h007F; + parameter [15:0] RX_CTLE_CTRL_LANE1 = 16'h007F; + parameter [15:0] RX_CTLE_CTRL_LANE2 = 16'h007F; + parameter [15:0] RX_CTLE_CTRL_LANE3 = 16'h007F; + parameter [15:0] RX_CTRL_OVRD_LANE0 = 16'h000C; + parameter [15:0] RX_CTRL_OVRD_LANE1 = 16'h000C; + parameter [15:0] RX_CTRL_OVRD_LANE2 = 16'h000C; + parameter [15:0] RX_CTRL_OVRD_LANE3 = 16'h000C; + parameter integer RX_FABRIC_WIDTH0 = 6466; + parameter integer RX_FABRIC_WIDTH1 = 6466; + parameter integer RX_FABRIC_WIDTH2 = 6466; + parameter integer RX_FABRIC_WIDTH3 = 6466; + parameter [15:0] RX_LOOP_CTRL_LANE0 = 16'h0070; + parameter [15:0] RX_LOOP_CTRL_LANE1 = 16'h0070; + parameter [15:0] RX_LOOP_CTRL_LANE2 = 16'h0070; + parameter [15:0] RX_LOOP_CTRL_LANE3 = 16'h0070; + parameter [15:0] RX_MVAL0_LANE0 = 16'h0000; + parameter [15:0] RX_MVAL0_LANE1 = 16'h0000; + parameter [15:0] RX_MVAL0_LANE2 = 16'h0000; + parameter [15:0] RX_MVAL0_LANE3 = 16'h0000; + parameter [15:0] RX_MVAL1_LANE0 = 16'h0000; + parameter [15:0] RX_MVAL1_LANE1 = 16'h0000; + parameter [15:0] RX_MVAL1_LANE2 = 16'h0000; + parameter [15:0] RX_MVAL1_LANE3 = 16'h0000; + parameter [15:0] RX_P0S_CTRL = 16'h1206; + parameter [15:0] RX_P0_CTRL = 16'h11F0; + parameter [15:0] RX_P1_CTRL = 16'h120F; + parameter [15:0] RX_P2_CTRL = 16'h0E0F; + parameter [15:0] RX_PI_CTRL0 = 16'hB2F2; + parameter [15:0] RX_PI_CTRL1 = 16'h0080; + parameter integer SIM_GTHRESET_SPEEDUP = 1; + parameter SIM_VERSION = "1.0"; + parameter [15:0] SLICE_CFG = 16'h0000; + parameter [15:0] SLICE_NOISE_CTRL_0_LANE01 = 16'h0000; + parameter [15:0] SLICE_NOISE_CTRL_0_LANE23 = 16'h0000; + parameter [15:0] SLICE_NOISE_CTRL_1_LANE01 = 16'h0000; + parameter [15:0] SLICE_NOISE_CTRL_1_LANE23 = 16'h0000; + parameter [15:0] SLICE_NOISE_CTRL_2_LANE01 = 16'hEFFF; + parameter [15:0] SLICE_NOISE_CTRL_2_LANE23 = 16'hEFFF; + parameter [15:0] SLICE_TX_RESET_LANE01 = 16'h0000; + parameter [15:0] SLICE_TX_RESET_LANE23 = 16'h0000; + parameter [15:0] TERM_CTRL_LANE0 = 16'h0000; + parameter [15:0] TERM_CTRL_LANE1 = 16'h0000; + parameter [15:0] TERM_CTRL_LANE2 = 16'h0000; + parameter [15:0] TERM_CTRL_LANE3 = 16'h0000; + parameter [15:0] TX_CFG0_LANE0 = 16'h203D; + parameter [15:0] TX_CFG0_LANE1 = 16'h203D; + parameter [15:0] TX_CFG0_LANE2 = 16'h203D; + parameter [15:0] TX_CFG0_LANE3 = 16'h203D; + parameter [15:0] TX_CFG1_LANE0 = 16'h0C83; + parameter [15:0] TX_CFG1_LANE1 = 16'h0C83; + parameter [15:0] TX_CFG1_LANE2 = 16'h0C83; + parameter [15:0] TX_CFG1_LANE3 = 16'h0C83; + parameter [15:0] TX_CFG2_LANE0 = 16'h0001; + parameter [15:0] TX_CFG2_LANE1 = 16'h0001; + parameter [15:0] TX_CFG2_LANE2 = 16'h0001; + parameter [15:0] TX_CFG2_LANE3 = 16'h0001; + parameter [15:0] TX_CLK_SEL0_LANE0 = 16'h2F2F; + parameter [15:0] TX_CLK_SEL0_LANE1 = 16'h2F2F; + parameter [15:0] TX_CLK_SEL0_LANE2 = 16'h2F2F; + parameter [15:0] TX_CLK_SEL0_LANE3 = 16'h2F2F; + parameter [15:0] TX_CLK_SEL1_LANE0 = 16'h2F2F; + parameter [15:0] TX_CLK_SEL1_LANE1 = 16'h2F2F; + parameter [15:0] TX_CLK_SEL1_LANE2 = 16'h2F2F; + parameter [15:0] TX_CLK_SEL1_LANE3 = 16'h2F2F; + parameter [15:0] TX_DISABLE_LANE0 = 16'h0000; + parameter [15:0] TX_DISABLE_LANE1 = 16'h0000; + parameter [15:0] TX_DISABLE_LANE2 = 16'h0000; + parameter [15:0] TX_DISABLE_LANE3 = 16'h0000; + parameter integer TX_FABRIC_WIDTH0 = 6466; + parameter integer TX_FABRIC_WIDTH1 = 6466; + parameter integer TX_FABRIC_WIDTH2 = 6466; + parameter integer TX_FABRIC_WIDTH3 = 6466; + parameter [15:0] TX_P0P0S_CTRL = 16'h060C; + parameter [15:0] TX_P1P2_CTRL = 16'h0C39; + parameter [15:0] TX_PREEMPH_LANE0 = 16'hA0F0; + parameter [15:0] TX_PREEMPH_LANE1 = 16'hA0F0; + parameter [15:0] TX_PREEMPH_LANE2 = 16'hA0F0; + parameter [15:0] TX_PREEMPH_LANE3 = 16'hA0F0; + parameter [15:0] TX_PWR_RATE_OVRD_LANE0 = 16'h0060; + parameter [15:0] TX_PWR_RATE_OVRD_LANE1 = 16'h0060; + parameter [15:0] TX_PWR_RATE_OVRD_LANE2 = 16'h0060; + parameter [15:0] TX_PWR_RATE_OVRD_LANE3 = 16'h0060; + + localparam in_delay = 0; + localparam out_delay = 0; + localparam INCLK_DELAY = 0; + localparam OUTCLK_DELAY = 0; + + output DRDY; + output GTHINITDONE; + output MGMTPCSRDACK; + output RXCTRLACK0; + output RXCTRLACK1; + output RXCTRLACK2; + output RXCTRLACK3; + output RXDATATAP0; + output RXDATATAP1; + output RXDATATAP2; + output RXDATATAP3; + output RXPCSCLKSMPL0; + output RXPCSCLKSMPL1; + output RXPCSCLKSMPL2; + output RXPCSCLKSMPL3; + output RXUSERCLKOUT0; + output RXUSERCLKOUT1; + output RXUSERCLKOUT2; + output RXUSERCLKOUT3; + output TSTPATH; + output TSTREFCLKFAB; + output TSTREFCLKOUT; + output TXCTRLACK0; + output TXCTRLACK1; + output TXCTRLACK2; + output TXCTRLACK3; + output TXDATATAP10; + output TXDATATAP11; + output TXDATATAP12; + output TXDATATAP13; + output TXDATATAP20; + output TXDATATAP21; + output TXDATATAP22; + output TXDATATAP23; + output TXN0; + output TXN1; + output TXN2; + output TXN3; + output TXP0; + output TXP1; + output TXP2; + output TXP3; + output TXPCSCLKSMPL0; + output TXPCSCLKSMPL1; + output TXPCSCLKSMPL2; + output TXPCSCLKSMPL3; + output TXUSERCLKOUT0; + output TXUSERCLKOUT1; + output TXUSERCLKOUT2; + output TXUSERCLKOUT3; + output [15:0] DRPDO; + output [15:0] MGMTPCSRDDATA; + output [63:0] RXDATA0; + output [63:0] RXDATA1; + output [63:0] RXDATA2; + output [63:0] RXDATA3; + output [7:0] RXCODEERR0; + output [7:0] RXCODEERR1; + output [7:0] RXCODEERR2; + output [7:0] RXCODEERR3; + output [7:0] RXCTRL0; + output [7:0] RXCTRL1; + output [7:0] RXCTRL2; + output [7:0] RXCTRL3; + output [7:0] RXDISPERR0; + output [7:0] RXDISPERR1; + output [7:0] RXDISPERR2; + output [7:0] RXDISPERR3; + output [7:0] RXVALID0; + output [7:0] RXVALID1; + output [7:0] RXVALID2; + output [7:0] RXVALID3; + + input DCLK; + input DEN; + input DFETRAINCTRL0; + input DFETRAINCTRL1; + input DFETRAINCTRL2; + input DFETRAINCTRL3; + input DISABLEDRP; + input DWE; + input GTHINIT; + input GTHRESET; + input GTHX2LANE01; + input GTHX2LANE23; + input GTHX4LANE; + input MGMTPCSREGRD; + input MGMTPCSREGWR; + input POWERDOWN0; + input POWERDOWN1; + input POWERDOWN2; + input POWERDOWN3; + input REFCLK; + input RXBUFRESET0; + input RXBUFRESET1; + input RXBUFRESET2; + input RXBUFRESET3; + input RXENCOMMADET0; + input RXENCOMMADET1; + input RXENCOMMADET2; + input RXENCOMMADET3; + input RXN0; + input RXN1; + input RXN2; + input RXN3; + input RXP0; + input RXP1; + input RXP2; + input RXP3; + input RXPOLARITY0; + input RXPOLARITY1; + input RXPOLARITY2; + input RXPOLARITY3; + input RXSLIP0; + input RXSLIP1; + input RXSLIP2; + input RXSLIP3; + input RXUSERCLKIN0; + input RXUSERCLKIN1; + input RXUSERCLKIN2; + input RXUSERCLKIN3; + input TXBUFRESET0; + input TXBUFRESET1; + input TXBUFRESET2; + input TXBUFRESET3; + input TXDEEMPH0; + input TXDEEMPH1; + input TXDEEMPH2; + input TXDEEMPH3; + input TXUSERCLKIN0; + input TXUSERCLKIN1; + input TXUSERCLKIN2; + input TXUSERCLKIN3; + input [15:0] DADDR; + input [15:0] DI; + input [15:0] MGMTPCSREGADDR; + input [15:0] MGMTPCSWRDATA; + input [1:0] RXPOWERDOWN0; + input [1:0] RXPOWERDOWN1; + input [1:0] RXPOWERDOWN2; + input [1:0] RXPOWERDOWN3; + input [1:0] RXRATE0; + input [1:0] RXRATE1; + input [1:0] RXRATE2; + input [1:0] RXRATE3; + input [1:0] TXPOWERDOWN0; + input [1:0] TXPOWERDOWN1; + input [1:0] TXPOWERDOWN2; + input [1:0] TXPOWERDOWN3; + input [1:0] TXRATE0; + input [1:0] TXRATE1; + input [1:0] TXRATE2; + input [1:0] TXRATE3; + input [2:0] PLLREFCLKSEL; + input [2:0] SAMPLERATE0; + input [2:0] SAMPLERATE1; + input [2:0] SAMPLERATE2; + input [2:0] SAMPLERATE3; + input [2:0] TXMARGIN0; + input [2:0] TXMARGIN1; + input [2:0] TXMARGIN2; + input [2:0] TXMARGIN3; + input [3:0] MGMTPCSLANESEL; + input [4:0] MGMTPCSMMDADDR; + input [5:0] PLLPCSCLKDIV; + input [63:0] TXDATA0; + input [63:0] TXDATA1; + input [63:0] TXDATA2; + input [63:0] TXDATA3; + input [7:0] TXCTRL0; + input [7:0] TXCTRL1; + input [7:0] TXCTRL2; + input [7:0] TXCTRL3; + input [7:0] TXDATAMSB0; + input [7:0] TXDATAMSB1; + input [7:0] TXDATAMSB2; + input [7:0] TXDATAMSB3; + + reg GTH_CFG_PWRUP_LANE0_BINARY; + reg GTH_CFG_PWRUP_LANE1_BINARY; + reg GTH_CFG_PWRUP_LANE2_BINARY; + reg GTH_CFG_PWRUP_LANE3_BINARY; + reg SIM_GTHRESET_SPEEDUP_BINARY; + reg SIM_VERSION_BINARY; + reg [2:0] RX_FABRIC_WIDTH0_BINARY; + reg [2:0] RX_FABRIC_WIDTH1_BINARY; + reg [2:0] RX_FABRIC_WIDTH2_BINARY; + reg [2:0] RX_FABRIC_WIDTH3_BINARY; + reg [2:0] TX_FABRIC_WIDTH0_BINARY; + reg [2:0] TX_FABRIC_WIDTH1_BINARY; + reg [2:0] TX_FABRIC_WIDTH2_BINARY; + reg [2:0] TX_FABRIC_WIDTH3_BINARY; + + tri0 GSR = glbl.GSR; + + // Start DRC checks + + always @(PLLPCSCLKDIV) begin + + // DRC Checks SET 1 - DRC Error for PLLPCSCLKDIV = 6'b32 + + if (((PLLPCSCLKDIV == 6'd32) || (PLLPCSCLKDIV == 6'b100000)) && ((PCS_MODE_LANE0[7:4] != 4'b0001) || (RX_FABRIC_WIDTH0 != 6466))) begin + $display("DRC Error: When PLLPCSCLKDIV is set to 6'b32, PCS_MODE_LANE0[7:4] %b or RX_FABRIC_WIDTH0 %d is not valid for instance %m of GTHE1_QUAD.", PCS_MODE_LANE0[7:4], RX_FABRIC_WIDTH0); + $finish; + end + if (((PLLPCSCLKDIV == 6'd32) || (PLLPCSCLKDIV == 6'b100000)) && ((PCS_MODE_LANE0[3:0] != 4'b0001) || (TX_FABRIC_WIDTH0 != 6466))) begin + $display("DRC Error : When PLLPCSCLKDIV is set to 6'b32, PCS_MODE_LANE0[3:0] %b or TX_FABRIC_WIDTH0 %d is not valid for instance %m of GTHE1_QUAD.", PCS_MODE_LANE0[3:0], TX_FABRIC_WIDTH0); + $finish; + end + if (((PLLPCSCLKDIV == 6'd32) || (PLLPCSCLKDIV == 6'b100000)) && ((PCS_MODE_LANE1[7:4] != 4'b0001) || (RX_FABRIC_WIDTH1 != 6466))) begin + $display("DRC Error : When PLLPCSCLKDIV is set to 6'b32, PCS_MODE_LANE1[7:4] %b or RX_FABRIC_WIDTH1 %d is not valid for instance %m of GTHE1_QUAD.", PCS_MODE_LANE1[7:4], RX_FABRIC_WIDTH1); + $finish; + end + if (((PLLPCSCLKDIV == 6'd32) || (PLLPCSCLKDIV == 6'b100000)) && ((PCS_MODE_LANE1[3:0] != 4'b0001) || (TX_FABRIC_WIDTH1 != 6466))) begin + $display("DRC Error : When PLLPCSCLKDIV is set to 6'b32, PCS_MODE_LANE1[3:0] %b or TX_FABRIC_WIDTH1 %d is not valid for instance %m of GTHE1_QUAD.", PCS_MODE_LANE1[3:0], TX_FABRIC_WIDTH1); + $finish; + end + if (((PLLPCSCLKDIV == 6'd32) || (PLLPCSCLKDIV == 6'b100000)) && ((PCS_MODE_LANE2[7:4] != 4'b0001) || (RX_FABRIC_WIDTH2 != 6466))) begin + $display("DRC Error : When PLLPCSCLKDIV is set to 6'b32, PCS_MODE_LANE2[7:4] %b or RX_FABRIC_WIDTH2 %d is not valid for instance %m of GTHE1_QUAD.", PCS_MODE_LANE2[7:4], RX_FABRIC_WIDTH2); + $finish; + end + if (((PLLPCSCLKDIV == 6'd32) || (PLLPCSCLKDIV == 6'b100000)) && ((PCS_MODE_LANE2[3:0] != 4'b0001) || (TX_FABRIC_WIDTH2 != 6466))) begin + $display("DRC Error : When PLLPCSCLKDIV is set to 6'b32, PCS_MODE_LANE2[3:0] %b or TX_FABRIC_WIDTH2 %d is not valid for instance %m of GTHE1_QUAD.", PCS_MODE_LANE2[3:0], TX_FABRIC_WIDTH2); + $finish; + end + if (((PLLPCSCLKDIV == 6'd32) || (PLLPCSCLKDIV == 6'b100000)) && ((PCS_MODE_LANE3[7:4] != 4'b0001) || (RX_FABRIC_WIDTH3 != 6466))) begin + $display("DRC Error : When PLLPCSCLKDIV is set to 6'b32, PCS_MODE_LANE3[7:4] %b or RX_FABRIC_WIDTH3 %d is not valid for instance %m of GTHE1_QUAD.", PCS_MODE_LANE3[7:4], RX_FABRIC_WIDTH3); + $finish; + end + if (((PLLPCSCLKDIV == 6'd32) || (PLLPCSCLKDIV == 6'b100000)) && ((PCS_MODE_LANE3[3:0] != 4'b0001) || (TX_FABRIC_WIDTH3 != 6466))) begin + $display("DRC Error : When PLLPCSCLKDIV is set to 6'b32, PCS_MODE_LANE3[3:0] %b or TX_FABRIC_WIDTH3 %d is not valid for instance %m of GTHE1_QUAD.", PCS_MODE_LANE3[3:0], TX_FABRIC_WIDTH3); + $finish; + end + + // DRC Checks SET 2 - DRC Error for PLLPCSCLKDIV = 6'b7 + + if (((PLLPCSCLKDIV == 6'd7) || (PLLPCSCLKDIV == 6'b000111)) && !((PCS_MODE_LANE0[7:4] == 4'b1100) ||((PCS_MODE_LANE0[7:4] == 4'b1000) && (RX_FABRIC_WIDTH0 == 8 ||RX_FABRIC_WIDTH0 ==16 ||RX_FABRIC_WIDTH0==32 || RX_FABRIC_WIDTH0 ==64)) || ((PCS_MODE_LANE0[7:4] == 4'b1010) && (RX_FABRIC_WIDTH0 ==16 ||RX_FABRIC_WIDTH0==32 ||RX_FABRIC_WIDTH0 ==64 )))) begin + $display("DRC Error : When PLLPCSCLKDIV is set to 6'b7, PCS_MODE_LANE0[7:4] %b and RX_FABRIC_WIDTH0 %d is not valid for instance %m of GTHE1_QUAD.", PCS_MODE_LANE0[7:4], RX_FABRIC_WIDTH0); + $finish; + end + + if (((PLLPCSCLKDIV == 6'd7) || (PLLPCSCLKDIV == 6'b000111)) && !((PCS_MODE_LANE0[3:0] == 4'b1100) ||((PCS_MODE_LANE0[3:0] == 4'b1000) && (TX_FABRIC_WIDTH0 == 8 ||TX_FABRIC_WIDTH0 ==16 ||TX_FABRIC_WIDTH0==32 || TX_FABRIC_WIDTH0 ==64)) || ((PCS_MODE_LANE0[3:0] == 4'b1010) && (TX_FABRIC_WIDTH0 ==16 ||TX_FABRIC_WIDTH0==32 ||TX_FABRIC_WIDTH0 ==64 )))) begin + $display("DRC Error : When PLLPCSCLKDIV is set to 6'b7, PCS_MODE_LANE0[3:0] %b and TX_FABRIC_WIDTH0 %d is not valid for instance %m of GTHE1_QUAD.", PCS_MODE_LANE0[3:0], TX_FABRIC_WIDTH0); + $finish; + end + + if (((PLLPCSCLKDIV == 6'd7) || (PLLPCSCLKDIV == 6'b000111)) && !((PCS_MODE_LANE1[7:4] == 4'b1100) ||((PCS_MODE_LANE1[7:4] == 4'b1000) && (RX_FABRIC_WIDTH1 == 8 ||RX_FABRIC_WIDTH1 ==16 ||RX_FABRIC_WIDTH1==32 || RX_FABRIC_WIDTH1 ==64)) || ((PCS_MODE_LANE1[7:4] == 4'b1010) && (RX_FABRIC_WIDTH1 ==16 ||RX_FABRIC_WIDTH1==32 ||RX_FABRIC_WIDTH1 ==64 )))) begin + $display("DRC Error : When PLLPCSCLKDIV is set to 6'b7, PCS_MODE_LANE1[7:4] %b and RX_FABRIC_WIDTH1 %d is not valid for instance %m of GTHE1_QUAD.", PCS_MODE_LANE1[7:4], RX_FABRIC_WIDTH1); + $finish; + end + + if (((PLLPCSCLKDIV == 6'd7) || (PLLPCSCLKDIV == 6'b000111)) && !((PCS_MODE_LANE1[3:0] == 4'b1100) ||((PCS_MODE_LANE1[3:0] == 4'b1000) && (TX_FABRIC_WIDTH1 == 8 ||TX_FABRIC_WIDTH1 ==16 ||TX_FABRIC_WIDTH1==32 || TX_FABRIC_WIDTH1 ==64)) || ((PCS_MODE_LANE1[3:0] == 4'b1010) && (TX_FABRIC_WIDTH1 ==16 ||TX_FABRIC_WIDTH1==32 ||TX_FABRIC_WIDTH1 ==64 )))) begin + $display("DRC Error : When PLLPCSCLKDIV is set to 6'b7, PCS_MODE_LANE1[3:0] %b and TX_FABRIC_WIDTH1 %d is not valid for instance %m of GTHE1_QUAD.", PCS_MODE_LANE1[3:0], TX_FABRIC_WIDTH1); + $finish; + end + + if (((PLLPCSCLKDIV == 6'd7) || (PLLPCSCLKDIV == 6'b000111)) && !((PCS_MODE_LANE2[7:4] == 4'b1100) ||((PCS_MODE_LANE2[7:4] == 4'b1000) && (RX_FABRIC_WIDTH2 == 8 ||RX_FABRIC_WIDTH2 ==16 ||RX_FABRIC_WIDTH2==32 || RX_FABRIC_WIDTH2 ==64)) || ((PCS_MODE_LANE2[7:4] == 4'b1010) && (RX_FABRIC_WIDTH2 ==16 ||RX_FABRIC_WIDTH2==32 ||RX_FABRIC_WIDTH2 ==64 )))) begin + $display("DRC Error : When PLLPCSCLKDIV is set to 6'b7, PCS_MODE_LANE2[7:4] %b and RX_FABRIC_WIDTH2 %d is not valid for instance %m of GTHE1_QUAD.", PCS_MODE_LANE2[7:4], RX_FABRIC_WIDTH2); + $finish; + end + + if (((PLLPCSCLKDIV == 6'd7) || (PLLPCSCLKDIV == 6'b000111)) && !((PCS_MODE_LANE2[3:0] == 4'b1100) ||((PCS_MODE_LANE2[3:0] == 4'b1000) && (TX_FABRIC_WIDTH2 == 8 ||TX_FABRIC_WIDTH2 ==16 ||TX_FABRIC_WIDTH2==32 || TX_FABRIC_WIDTH2 ==64)) || ((PCS_MODE_LANE2[3:0] == 4'b1010) && (TX_FABRIC_WIDTH2 ==16 ||TX_FABRIC_WIDTH2==32 ||TX_FABRIC_WIDTH2 ==64 )))) begin + $display("DRC Error : When PLLPCSCLKDIV is set to 6'b7, PCS_MODE_LANE2[3:0] %b and TX_FABRIC_WIDTH2 %d is not valid for instance %m of GTHE1_QUAD.", PCS_MODE_LANE2[3:0], TX_FABRIC_WIDTH2); + $finish; + end + + if (((PLLPCSCLKDIV == 6'd7) || (PLLPCSCLKDIV == 6'b000111)) && !((PCS_MODE_LANE3[7:4] == 4'b1100) ||((PCS_MODE_LANE3[7:4] == 4'b1000) && (RX_FABRIC_WIDTH3 == 8 ||RX_FABRIC_WIDTH3 ==16 ||RX_FABRIC_WIDTH3==32 || RX_FABRIC_WIDTH3 ==64)) || ((PCS_MODE_LANE3[7:4] == 4'b1010) && (RX_FABRIC_WIDTH3 ==16 ||RX_FABRIC_WIDTH3==32 ||RX_FABRIC_WIDTH3 ==64 )))) begin + $display("DRC Error : When PLLPCSCLKDIV is set to 6'b7, PCS_MODE_LANE3[7:4] %b and RX_FABRIC_WIDTH3 %d is not valid for instance %m of GTHE1_QUAD.", PCS_MODE_LANE3[7:4], RX_FABRIC_WIDTH3); + $finish; + end + + if (((PLLPCSCLKDIV == 6'd7) || (PLLPCSCLKDIV == 6'b000111)) && !((PCS_MODE_LANE3[3:0] == 4'b1100) ||((PCS_MODE_LANE3[3:0] == 4'b1000) && (TX_FABRIC_WIDTH3 == 8 ||TX_FABRIC_WIDTH3 ==16 ||TX_FABRIC_WIDTH3==32 || TX_FABRIC_WIDTH3 ==64)) || ((PCS_MODE_LANE3[3:0] == 4'b1010) && (TX_FABRIC_WIDTH3 ==16 ||TX_FABRIC_WIDTH3==32 ||TX_FABRIC_WIDTH3 ==64 )))) begin + $display("DRC Error : When PLLPCSCLKDIV is set to 6'b7, PCS_MODE_LANE3[3:0] %b and TX_FABRIC_WIDTH3 %d is not valid for instance %m of GTHE1_QUAD.", PCS_MODE_LANE3[3:0], TX_FABRIC_WIDTH3); + $finish; + end + + //DRC Checks Set 3 - DRC Error for PLLPCSCLKDIV = 6'b9 + + if (((PLLPCSCLKDIV == 6'd9) || (PLLPCSCLKDIV == 6'b001001)) && !((((PCS_MODE_LANE0[7:4] == 4'b1011) && (RX_FABRIC_WIDTH0==20 || RX_FABRIC_WIDTH0 ==40 || RX_FABRIC_WIDTH0 ==80)) || ((PCS_MODE_LANE0[7:4] == 4'b0111) && (RX_FABRIC_WIDTH0 ==16 ||RX_FABRIC_WIDTH0==32 ||RX_FABRIC_WIDTH0 ==64 ))))) begin + $display("DRC Error : When PLLPCSCLKDIV is set to 6'b9, PCS_MODE_LANE0[7:4] %b and RX_FABRIC_WIDTH0 %d is not valid for instance %m of GTHE1_QUAD.", PCS_MODE_LANE0[7:4], RX_FABRIC_WIDTH0); + $finish; + end + + if (((PLLPCSCLKDIV == 6'd9) || (PLLPCSCLKDIV == 6'b001001)) && !((((PCS_MODE_LANE0[3:0] == 4'b1011) && (TX_FABRIC_WIDTH0==20 || TX_FABRIC_WIDTH0 ==40 || TX_FABRIC_WIDTH0 ==80)) || ((PCS_MODE_LANE0[3:0] == 4'b0111) && (TX_FABRIC_WIDTH0 ==16 ||TX_FABRIC_WIDTH0==32 ||TX_FABRIC_WIDTH0 ==64 ))))) begin + $display("DRC Error : When PLLPCSCLKDIV is set to 6'b9, PCS_MODE_LANE0[3:0] %b and TX_FABRIC_WIDTH0 %d is not valid for instance %m of GTHE1_QUAD.", PCS_MODE_LANE0[3:0], TX_FABRIC_WIDTH0); + $finish; + end + + if (((PLLPCSCLKDIV == 6'd9) || (PLLPCSCLKDIV == 6'b001001)) && !((((PCS_MODE_LANE1[7:4] == 4'b1011) && (RX_FABRIC_WIDTH1==20 || RX_FABRIC_WIDTH1 ==40 || RX_FABRIC_WIDTH1 ==80)) || ((PCS_MODE_LANE1[7:4] == 4'b0111) && (RX_FABRIC_WIDTH1 ==16 ||RX_FABRIC_WIDTH1==32 ||RX_FABRIC_WIDTH1 ==64 ))))) begin + $display("DRC Error : When PLLPCSCLKDIV is set to 6'b9, PCS_MODE_LANE1[7:4] %b and RX_FABRIC_WIDTH1 %d is not valid for instance %m of GTHE1_QUAD.", PCS_MODE_LANE1[7:4], RX_FABRIC_WIDTH1); + $finish; + end + + if (((PLLPCSCLKDIV == 6'd9) || (PLLPCSCLKDIV == 6'b001001)) && !((((PCS_MODE_LANE1[3:0] == 4'b1011) && (TX_FABRIC_WIDTH1==20 || TX_FABRIC_WIDTH1 ==40 || TX_FABRIC_WIDTH1 ==80)) || ((PCS_MODE_LANE1[3:0] == 4'b0111) && (TX_FABRIC_WIDTH1 ==16 ||TX_FABRIC_WIDTH1==32 ||TX_FABRIC_WIDTH1 ==64 ))))) begin + $display("DRC Error : When PLLPCSCLKDIV is set to 6'b9, PCS_MODE_LANE1[3:0] %b and TX_FABRIC_WIDTH1 %d is not valid for instance %m of GTHE1_QUAD.", PCS_MODE_LANE1[3:0], TX_FABRIC_WIDTH1); + $finish; + end + + if (((PLLPCSCLKDIV == 6'd9) || (PLLPCSCLKDIV == 6'b001001)) && !((((PCS_MODE_LANE2[7:4] == 4'b1011) && (RX_FABRIC_WIDTH2==20 || RX_FABRIC_WIDTH2 ==40 || RX_FABRIC_WIDTH2 ==80)) || ((PCS_MODE_LANE2[7:4] == 4'b0111) && (RX_FABRIC_WIDTH2 ==16 ||RX_FABRIC_WIDTH2==32 ||RX_FABRIC_WIDTH2 ==64 ))))) begin + $display("DRC Error : When PLLPCSCLKDIV is set to 6'b9, PCS_MODE_LANE2[7:4] %b and RX_FABRIC_WIDTH2 %d is not valid for instance %m of GTHE1_QUAD.", PCS_MODE_LANE2[7:4], RX_FABRIC_WIDTH2); + $finish; + end + + if (((PLLPCSCLKDIV == 6'd9) || (PLLPCSCLKDIV == 6'b001001)) && !((((PCS_MODE_LANE2[3:0] == 4'b1011) && (TX_FABRIC_WIDTH2==20 || TX_FABRIC_WIDTH2 ==40 || TX_FABRIC_WIDTH2 ==80)) || ((PCS_MODE_LANE2[3:0] == 4'b0111) && (TX_FABRIC_WIDTH2 ==16 ||TX_FABRIC_WIDTH2==32 ||TX_FABRIC_WIDTH2 ==64 ))))) begin + $display("DRC Error : When PLLPCSCLKDIV is set to 6'b9, PCS_MODE_LANE2[3:0] %b and TX_FABRIC_WIDTH2 %d is not valid for instance %m of GTHE1_QUAD.", PCS_MODE_LANE2[3:0], TX_FABRIC_WIDTH2); + $finish; + end + + if (((PLLPCSCLKDIV == 6'd9) || (PLLPCSCLKDIV == 6'b001001)) && !((((PCS_MODE_LANE3[7:4] == 4'b1011) && (RX_FABRIC_WIDTH3==20 || RX_FABRIC_WIDTH3 ==40 || RX_FABRIC_WIDTH3 ==80)) || ((PCS_MODE_LANE3[7:4] == 4'b0111) && (RX_FABRIC_WIDTH3 ==16 ||RX_FABRIC_WIDTH3==32 ||RX_FABRIC_WIDTH3 ==64 ))))) begin + $display("DRC Error : When PLLPCSCLKDIV is set to 6'b9, PCS_MODE_LANE3[7:4] %b and RX_FABRIC_WIDTH3 %d is not valid for instance %m of GTHE1_QUAD.", PCS_MODE_LANE3[7:4], RX_FABRIC_WIDTH3); + $finish; + end + + if (((PLLPCSCLKDIV == 6'd9) || (PLLPCSCLKDIV == 6'b001001)) && !((((PCS_MODE_LANE3[3:0] == 4'b1011) && (TX_FABRIC_WIDTH3==20 || TX_FABRIC_WIDTH3 ==40 || TX_FABRIC_WIDTH3 ==80)) || ((PCS_MODE_LANE3[3:0] == 4'b0111) && (TX_FABRIC_WIDTH3 ==16 ||TX_FABRIC_WIDTH3==32 ||TX_FABRIC_WIDTH3 ==64 ))))) begin + $display("DRC Error : When PLLPCSCLKDIV is set to 6'b9, PCS_MODE_LANE3[3:0] %b and TX_FABRIC_WIDTH3 %d is not valid for instance %m of GTHE1_QUAD.", PCS_MODE_LANE3[3:0], TX_FABRIC_WIDTH3); + $finish; + end + + end // always @ (PLLPCSCLKDIV) + + // End DRC checks + + initial begin + + case (RX_FABRIC_WIDTH0) + 6466 : RX_FABRIC_WIDTH0_BINARY = 3'b111; + 8 : RX_FABRIC_WIDTH0_BINARY = 3'b000; + 10 : RX_FABRIC_WIDTH0_BINARY = 3'b000; + 16 : RX_FABRIC_WIDTH0_BINARY = 3'b000; + 20 : RX_FABRIC_WIDTH0_BINARY = 3'b000; + 32 : RX_FABRIC_WIDTH0_BINARY = 3'b011; + 40 : RX_FABRIC_WIDTH0_BINARY = 3'b101; + 64 : RX_FABRIC_WIDTH0_BINARY = 3'b010; + 80 : RX_FABRIC_WIDTH0_BINARY = 3'b110; + default : begin + $display("Attribute Syntax Error : The Attribute RX_FABRIC_WIDTH0 on GTHE1_QUAD instance %m is set to %d. Legal values for this attribute are 8 to 6466.", RX_FABRIC_WIDTH0, 6466); + $finish; + end + endcase + + case (RX_FABRIC_WIDTH1) + 6466 : RX_FABRIC_WIDTH1_BINARY = 3'b111; + 8 : RX_FABRIC_WIDTH1_BINARY = 3'b000; + 10 : RX_FABRIC_WIDTH1_BINARY = 3'b000; + 16 : RX_FABRIC_WIDTH1_BINARY = 3'b000; + 20 : RX_FABRIC_WIDTH1_BINARY = 3'b000; + 32 : RX_FABRIC_WIDTH1_BINARY = 3'b011; + 40 : RX_FABRIC_WIDTH1_BINARY = 3'b101; + 64 : RX_FABRIC_WIDTH1_BINARY = 3'b010; + 80 : RX_FABRIC_WIDTH1_BINARY = 3'b110; + default : begin + $display("Attribute Syntax Error : The Attribute RX_FABRIC_WIDTH1 on GTHE1_QUAD instance %m is set to %d. Legal values for this attribute are 8 to 6466.", RX_FABRIC_WIDTH1, 6466); + $finish; + end + endcase + + case (RX_FABRIC_WIDTH2) + 6466 : RX_FABRIC_WIDTH2_BINARY = 3'b111; + 8 : RX_FABRIC_WIDTH2_BINARY = 3'b000; + 10 : RX_FABRIC_WIDTH2_BINARY = 3'b000; + 16 : RX_FABRIC_WIDTH2_BINARY = 3'b000; + 20 : RX_FABRIC_WIDTH2_BINARY = 3'b000; + 32 : RX_FABRIC_WIDTH2_BINARY = 3'b011; + 40 : RX_FABRIC_WIDTH2_BINARY = 3'b101; + 64 : RX_FABRIC_WIDTH2_BINARY = 3'b010; + 80 : RX_FABRIC_WIDTH2_BINARY = 3'b110; + default : begin + $display("Attribute Syntax Error : The Attribute RX_FABRIC_WIDTH2 on GTHE1_QUAD instance %m is set to %d. Legal values for this attribute are 8 to 6466.", RX_FABRIC_WIDTH2, 6466); + $finish; + end + endcase + + case (RX_FABRIC_WIDTH3) + 6466 : RX_FABRIC_WIDTH3_BINARY = 3'b111; + 8 : RX_FABRIC_WIDTH3_BINARY = 3'b000; + 10 : RX_FABRIC_WIDTH3_BINARY = 3'b000; + 16 : RX_FABRIC_WIDTH3_BINARY = 3'b000; + 20 : RX_FABRIC_WIDTH3_BINARY = 3'b000; + 32 : RX_FABRIC_WIDTH3_BINARY = 3'b011; + 40 : RX_FABRIC_WIDTH3_BINARY = 3'b101; + 64 : RX_FABRIC_WIDTH3_BINARY = 3'b010; + 80 : RX_FABRIC_WIDTH3_BINARY = 3'b110; + default : begin + $display("Attribute Syntax Error : The Attribute RX_FABRIC_WIDTH3 on GTHE1_QUAD instance %m is set to %d. Legal values for this attribute are 8 to 6466.", RX_FABRIC_WIDTH3, 6466); + $finish; + end + endcase + + case (SIM_GTHRESET_SPEEDUP) + 1 : SIM_GTHRESET_SPEEDUP_BINARY = 1; + 0 : SIM_GTHRESET_SPEEDUP_BINARY = 0; + default : begin + $display("Attribute Syntax Error : The Attribute SIM_GTHRESET_SPEEDUP on GTHE1_QUAD instance %m is set to %d. Legal values for this attribute are 0 to 1.", SIM_GTHRESET_SPEEDUP, 1); + $finish; + end + endcase + + case (SIM_VERSION) + "1.0" : SIM_VERSION_BINARY = 0; + "0.0" : SIM_VERSION_BINARY = 0; + "2.0" : SIM_VERSION_BINARY = 0; + default : begin + $display("Attribute Syntax Error : The Attribute SIM_VERSION on GTHE1_QUAD instance %m is set to %s. Legal values for this attribute are 1.0, 0.0, or 2.0.", SIM_VERSION); + $finish; + end + endcase + case (TX_FABRIC_WIDTH0) + 6466 : TX_FABRIC_WIDTH0_BINARY = 3'b111; + 8 : TX_FABRIC_WIDTH0_BINARY = 3'b000; + 10 : TX_FABRIC_WIDTH0_BINARY = 3'b000; + 16 : TX_FABRIC_WIDTH0_BINARY = 3'b000; + 20 : TX_FABRIC_WIDTH0_BINARY = 3'b000; + 32 : TX_FABRIC_WIDTH0_BINARY = 3'b011; + 40 : TX_FABRIC_WIDTH0_BINARY = 3'b101; + 64 : TX_FABRIC_WIDTH0_BINARY = 3'b010; + 80 : TX_FABRIC_WIDTH0_BINARY = 3'b110; + default : begin + $display("Attribute Syntax Error : The Attribute TX_FABRIC_WIDTH0 on GTHE1_QUAD instance %m is set to %d. Legal values for this attribute are 8 to 6466.", TX_FABRIC_WIDTH0, 6466); + $finish; + end + endcase + + case (TX_FABRIC_WIDTH1) + 6466 : TX_FABRIC_WIDTH1_BINARY = 3'b111; + 8 : TX_FABRIC_WIDTH1_BINARY = 3'b000; + 10 : TX_FABRIC_WIDTH1_BINARY = 3'b000; + 16 : TX_FABRIC_WIDTH1_BINARY = 3'b000; + 20 : TX_FABRIC_WIDTH1_BINARY = 3'b000; + 32 : TX_FABRIC_WIDTH1_BINARY = 3'b011; + 40 : TX_FABRIC_WIDTH1_BINARY = 3'b101; + 64 : TX_FABRIC_WIDTH1_BINARY = 3'b010; + 80 : TX_FABRIC_WIDTH1_BINARY = 3'b110; + default : begin + $display("Attribute Syntax Error : The Attribute TX_FABRIC_WIDTH1 on GTHE1_QUAD instance %m is set to %d. Legal values for this attribute are 8 to 6466.", TX_FABRIC_WIDTH1, 6466); + $finish; + end + endcase + + case (TX_FABRIC_WIDTH2) + 6466 : TX_FABRIC_WIDTH2_BINARY = 3'b111; + 8 : TX_FABRIC_WIDTH2_BINARY = 3'b000; + 10 : TX_FABRIC_WIDTH2_BINARY = 3'b000; + 16 : TX_FABRIC_WIDTH2_BINARY = 3'b000; + 20 : TX_FABRIC_WIDTH2_BINARY = 3'b000; + 32 : TX_FABRIC_WIDTH2_BINARY = 3'b011; + 40 : TX_FABRIC_WIDTH2_BINARY = 3'b101; + 64 : TX_FABRIC_WIDTH2_BINARY = 3'b010; + 80 : TX_FABRIC_WIDTH2_BINARY = 3'b110; + default : begin + $display("Attribute Syntax Error : The Attribute TX_FABRIC_WIDTH2 on GTHE1_QUAD instance %m is set to %d. Legal values for this attribute are 8 to 6466.", TX_FABRIC_WIDTH2, 6466); + $finish; + end + endcase + + case (TX_FABRIC_WIDTH3) + 6466 : TX_FABRIC_WIDTH3_BINARY = 3'b111; + 8 : TX_FABRIC_WIDTH3_BINARY = 3'b000; + 10 : TX_FABRIC_WIDTH3_BINARY = 3'b000; + 16 : TX_FABRIC_WIDTH3_BINARY = 3'b000; + 20 : TX_FABRIC_WIDTH3_BINARY = 3'b000; + 32 : TX_FABRIC_WIDTH3_BINARY = 3'b011; + 40 : TX_FABRIC_WIDTH3_BINARY = 3'b101; + 64 : TX_FABRIC_WIDTH3_BINARY = 3'b010; + 80 : TX_FABRIC_WIDTH3_BINARY = 3'b110; + default : begin + $display("Attribute Syntax Error : The Attribute TX_FABRIC_WIDTH3 on GTHE1_QUAD instance %m is set to %d. Legal values for this attribute are 8 to 6466.", TX_FABRIC_WIDTH3, 6466); + $finish; + end + endcase + + if ((GTH_CFG_PWRUP_LANE0 >= 0) && (GTH_CFG_PWRUP_LANE0 <= 1)) + GTH_CFG_PWRUP_LANE0_BINARY = GTH_CFG_PWRUP_LANE0; + else begin + $display("Attribute Syntax Error : The Attribute GTH_CFG_PWRUP_LANE0 on GTHE1_QUAD instance %m is set to %d. Legal values for this attribute are 0 to 1.", GTH_CFG_PWRUP_LANE0); + $finish; + end + + if ((GTH_CFG_PWRUP_LANE1 >= 0) && (GTH_CFG_PWRUP_LANE1 <= 1)) + GTH_CFG_PWRUP_LANE1_BINARY = GTH_CFG_PWRUP_LANE1; + else begin + $display("Attribute Syntax Error : The Attribute GTH_CFG_PWRUP_LANE1 on GTHE1_QUAD instance %m is set to %d. Legal values for this attribute are 0 to 1.", GTH_CFG_PWRUP_LANE1); + $finish; + end + + if ((GTH_CFG_PWRUP_LANE2 >= 0) && (GTH_CFG_PWRUP_LANE2 <= 1)) + GTH_CFG_PWRUP_LANE2_BINARY = GTH_CFG_PWRUP_LANE2; + else begin + $display("Attribute Syntax Error : The Attribute GTH_CFG_PWRUP_LANE2 on GTHE1_QUAD instance %m is set to %d. Legal values for this attribute are 0 to 1.", GTH_CFG_PWRUP_LANE2); + $finish; + end + + if ((GTH_CFG_PWRUP_LANE3 >= 0) && (GTH_CFG_PWRUP_LANE3 <= 1)) + GTH_CFG_PWRUP_LANE3_BINARY = GTH_CFG_PWRUP_LANE3; + else begin + $display("Attribute Syntax Error : The Attribute GTH_CFG_PWRUP_LANE3 on GTHE1_QUAD instance %m is set to %d. Legal values for this attribute are 0 to 1.", GTH_CFG_PWRUP_LANE3); + $finish; + end + + end + + wire [15:0] delay_DRPDO; + wire [15:0] delay_MGMTPCSRDDATA; + wire [63:0] delay_RXDATA0; + wire [63:0] delay_RXDATA1; + wire [63:0] delay_RXDATA2; + wire [63:0] delay_RXDATA3; + wire [7:0] delay_RXCODEERR0; + wire [7:0] delay_RXCODEERR1; + wire [7:0] delay_RXCODEERR2; + wire [7:0] delay_RXCODEERR3; + wire [7:0] delay_RXCTRL0; + wire [7:0] delay_RXCTRL1; + wire [7:0] delay_RXCTRL2; + wire [7:0] delay_RXCTRL3; + wire [7:0] delay_RXDISPERR0; + wire [7:0] delay_RXDISPERR1; + wire [7:0] delay_RXDISPERR2; + wire [7:0] delay_RXDISPERR3; + wire [7:0] delay_RXVALID0; + wire [7:0] delay_RXVALID1; + wire [7:0] delay_RXVALID2; + wire [7:0] delay_RXVALID3; + wire delay_DRDY; + wire delay_GTHINITDONE; + wire delay_MGMTPCSRDACK; + wire delay_RXCTRLACK0; + wire delay_RXCTRLACK1; + wire delay_RXCTRLACK2; + wire delay_RXCTRLACK3; + wire delay_RXDATATAP0; + wire delay_RXDATATAP1; + wire delay_RXDATATAP2; + wire delay_RXDATATAP3; + wire delay_RXPCSCLKSMPL0; + wire delay_RXPCSCLKSMPL1; + wire delay_RXPCSCLKSMPL2; + wire delay_RXPCSCLKSMPL3; + wire delay_RXUSERCLKOUT0; + wire delay_RXUSERCLKOUT1; + wire delay_RXUSERCLKOUT2; + wire delay_RXUSERCLKOUT3; + wire delay_TSTPATH; + wire delay_TSTREFCLKFAB; + wire delay_TSTREFCLKOUT; + wire delay_TXCTRLACK0; + wire delay_TXCTRLACK1; + wire delay_TXCTRLACK2; + wire delay_TXCTRLACK3; + wire delay_TXDATATAP10; + wire delay_TXDATATAP11; + wire delay_TXDATATAP12; + wire delay_TXDATATAP13; + wire delay_TXDATATAP20; + wire delay_TXDATATAP21; + wire delay_TXDATATAP22; + wire delay_TXDATATAP23; + wire delay_TXN0; + wire delay_TXN1; + wire delay_TXN2; + wire delay_TXN3; + wire delay_TXP0; + wire delay_TXP1; + wire delay_TXP2; + wire delay_TXP3; + wire delay_TXPCSCLKSMPL0; + wire delay_TXPCSCLKSMPL1; + wire delay_TXPCSCLKSMPL2; + wire delay_TXPCSCLKSMPL3; + wire delay_TXUSERCLKOUT0; + wire delay_TXUSERCLKOUT1; + wire delay_TXUSERCLKOUT2; + wire delay_TXUSERCLKOUT3; + + wire [15:0] delay_DADDR; + wire [15:0] delay_DI; + wire [15:0] delay_MGMTPCSREGADDR; + wire [15:0] delay_MGMTPCSWRDATA; + wire [1:0] delay_RXPOWERDOWN0; + wire [1:0] delay_RXPOWERDOWN1; + wire [1:0] delay_RXPOWERDOWN2; + wire [1:0] delay_RXPOWERDOWN3; + wire [1:0] delay_RXRATE0; + wire [1:0] delay_RXRATE1; + wire [1:0] delay_RXRATE2; + wire [1:0] delay_RXRATE3; + wire [1:0] delay_TXPOWERDOWN0; + wire [1:0] delay_TXPOWERDOWN1; + wire [1:0] delay_TXPOWERDOWN2; + wire [1:0] delay_TXPOWERDOWN3; + wire [1:0] delay_TXRATE0; + wire [1:0] delay_TXRATE1; + wire [1:0] delay_TXRATE2; + wire [1:0] delay_TXRATE3; + wire [2:0] delay_PLLREFCLKSEL; + wire [2:0] delay_SAMPLERATE0; + wire [2:0] delay_SAMPLERATE1; + wire [2:0] delay_SAMPLERATE2; + wire [2:0] delay_SAMPLERATE3; + wire [2:0] delay_TXMARGIN0; + wire [2:0] delay_TXMARGIN1; + wire [2:0] delay_TXMARGIN2; + wire [2:0] delay_TXMARGIN3; + wire [3:0] delay_MGMTPCSLANESEL; + wire [4:0] delay_MGMTPCSMMDADDR; + wire [5:0] delay_PLLPCSCLKDIV; + wire [63:0] delay_TXDATA0; + wire [63:0] delay_TXDATA1; + wire [63:0] delay_TXDATA2; + wire [63:0] delay_TXDATA3; + wire [7:0] delay_TXCTRL0; + wire [7:0] delay_TXCTRL1; + wire [7:0] delay_TXCTRL2; + wire [7:0] delay_TXCTRL3; + wire [7:0] delay_TXDATAMSB0; + wire [7:0] delay_TXDATAMSB1; + wire [7:0] delay_TXDATAMSB2; + wire [7:0] delay_TXDATAMSB3; + wire delay_DCLK; + wire delay_DEN; + wire delay_DFETRAINCTRL0; + wire delay_DFETRAINCTRL1; + wire delay_DFETRAINCTRL2; + wire delay_DFETRAINCTRL3; + wire delay_DISABLEDRP; + wire delay_DWE; + wire delay_GTHINIT; + wire delay_GTHRESET; + wire delay_GTHX2LANE01; + wire delay_GTHX2LANE23; + wire delay_GTHX4LANE; + wire delay_MGMTPCSREGRD; + wire delay_MGMTPCSREGWR; + wire delay_POWERDOWN0; + wire delay_POWERDOWN1; + wire delay_POWERDOWN2; + wire delay_POWERDOWN3; + wire delay_REFCLK; + wire delay_RXBUFRESET0; + wire delay_RXBUFRESET1; + wire delay_RXBUFRESET2; + wire delay_RXBUFRESET3; + wire delay_RXENCOMMADET0; + wire delay_RXENCOMMADET1; + wire delay_RXENCOMMADET2; + wire delay_RXENCOMMADET3; + wire delay_RXN0; + wire delay_RXN1; + wire delay_RXN2; + wire delay_RXN3; + wire delay_RXP0; + wire delay_RXP1; + wire delay_RXP2; + wire delay_RXP3; + wire delay_RXPOLARITY0; + wire delay_RXPOLARITY1; + wire delay_RXPOLARITY2; + wire delay_RXPOLARITY3; + wire delay_RXSLIP0; + wire delay_RXSLIP1; + wire delay_RXSLIP2; + wire delay_RXSLIP3; + wire delay_RXUSERCLKIN0; + wire delay_RXUSERCLKIN1; + wire delay_RXUSERCLKIN2; + wire delay_RXUSERCLKIN3; + wire delay_TXBUFRESET0; + wire delay_TXBUFRESET1; + wire delay_TXBUFRESET2; + wire delay_TXBUFRESET3; + wire delay_TXDEEMPH0; + wire delay_TXDEEMPH1; + wire delay_TXDEEMPH2; + wire delay_TXDEEMPH3; + wire delay_TXUSERCLKIN0; + wire delay_TXUSERCLKIN1; + wire delay_TXUSERCLKIN2; + wire delay_TXUSERCLKIN3; + + assign #(OUTCLK_DELAY) RXUSERCLKOUT0 = delay_RXUSERCLKOUT0; + assign #(OUTCLK_DELAY) RXUSERCLKOUT1 = delay_RXUSERCLKOUT1; + assign #(OUTCLK_DELAY) RXUSERCLKOUT2 = delay_RXUSERCLKOUT2; + assign #(OUTCLK_DELAY) RXUSERCLKOUT3 = delay_RXUSERCLKOUT3; + assign #(OUTCLK_DELAY) TSTPATH = delay_TSTPATH; + assign #(OUTCLK_DELAY) TSTREFCLKFAB = delay_TSTREFCLKFAB; + assign #(OUTCLK_DELAY) TSTREFCLKOUT = delay_TSTREFCLKOUT; + assign #(OUTCLK_DELAY) TXUSERCLKOUT0 = delay_TXUSERCLKOUT0; + assign #(OUTCLK_DELAY) TXUSERCLKOUT1 = delay_TXUSERCLKOUT1; + assign #(OUTCLK_DELAY) TXUSERCLKOUT2 = delay_TXUSERCLKOUT2; + assign #(OUTCLK_DELAY) TXUSERCLKOUT3 = delay_TXUSERCLKOUT3; + + assign #(out_delay) DRDY = delay_DRDY; + assign #(out_delay) DRPDO = delay_DRPDO; + assign #(out_delay) GTHINITDONE = delay_GTHINITDONE; + assign #(out_delay) MGMTPCSRDACK = delay_MGMTPCSRDACK; + assign #(out_delay) MGMTPCSRDDATA = delay_MGMTPCSRDDATA; + assign #(out_delay) RXCODEERR0 = delay_RXCODEERR0; + assign #(out_delay) RXCODEERR1 = delay_RXCODEERR1; + assign #(out_delay) RXCODEERR2 = delay_RXCODEERR2; + assign #(out_delay) RXCODEERR3 = delay_RXCODEERR3; + assign #(out_delay) RXCTRL0 = delay_RXCTRL0; + assign #(out_delay) RXCTRL1 = delay_RXCTRL1; + assign #(out_delay) RXCTRL2 = delay_RXCTRL2; + assign #(out_delay) RXCTRL3 = delay_RXCTRL3; + assign #(out_delay) RXCTRLACK0 = delay_RXCTRLACK0; + assign #(out_delay) RXCTRLACK1 = delay_RXCTRLACK1; + assign #(out_delay) RXCTRLACK2 = delay_RXCTRLACK2; + assign #(out_delay) RXCTRLACK3 = delay_RXCTRLACK3; + assign #(out_delay) RXDATA0 = delay_RXDATA0; + assign #(out_delay) RXDATA1 = delay_RXDATA1; + assign #(out_delay) RXDATA2 = delay_RXDATA2; + assign #(out_delay) RXDATA3 = delay_RXDATA3; + assign #(out_delay) RXDATATAP0 = delay_RXDATATAP0; + assign #(out_delay) RXDATATAP1 = delay_RXDATATAP1; + assign #(out_delay) RXDATATAP2 = delay_RXDATATAP2; + assign #(out_delay) RXDATATAP3 = delay_RXDATATAP3; + assign #(out_delay) RXDISPERR0 = delay_RXDISPERR0; + assign #(out_delay) RXDISPERR1 = delay_RXDISPERR1; + assign #(out_delay) RXDISPERR2 = delay_RXDISPERR2; + assign #(out_delay) RXDISPERR3 = delay_RXDISPERR3; + assign #(out_delay) RXPCSCLKSMPL0 = delay_RXPCSCLKSMPL0; + assign #(out_delay) RXPCSCLKSMPL1 = delay_RXPCSCLKSMPL1; + assign #(out_delay) RXPCSCLKSMPL2 = delay_RXPCSCLKSMPL2; + assign #(out_delay) RXPCSCLKSMPL3 = delay_RXPCSCLKSMPL3; + assign #(out_delay) RXVALID0 = delay_RXVALID0; + assign #(out_delay) RXVALID1 = delay_RXVALID1; + assign #(out_delay) RXVALID2 = delay_RXVALID2; + assign #(out_delay) RXVALID3 = delay_RXVALID3; + assign #(out_delay) TXCTRLACK0 = delay_TXCTRLACK0; + assign #(out_delay) TXCTRLACK1 = delay_TXCTRLACK1; + assign #(out_delay) TXCTRLACK2 = delay_TXCTRLACK2; + assign #(out_delay) TXCTRLACK3 = delay_TXCTRLACK3; + assign #(out_delay) TXDATATAP10 = delay_TXDATATAP10; + assign #(out_delay) TXDATATAP11 = delay_TXDATATAP11; + assign #(out_delay) TXDATATAP12 = delay_TXDATATAP12; + assign #(out_delay) TXDATATAP13 = delay_TXDATATAP13; + assign #(out_delay) TXDATATAP20 = delay_TXDATATAP20; + assign #(out_delay) TXDATATAP21 = delay_TXDATATAP21; + assign #(out_delay) TXDATATAP22 = delay_TXDATATAP22; + assign #(out_delay) TXDATATAP23 = delay_TXDATATAP23; + assign #(out_delay) TXN0 = delay_TXN0; + assign #(out_delay) TXN1 = delay_TXN1; + assign #(out_delay) TXN2 = delay_TXN2; + assign #(out_delay) TXN3 = delay_TXN3; + assign #(out_delay) TXP0 = delay_TXP0; + assign #(out_delay) TXP1 = delay_TXP1; + assign #(out_delay) TXP2 = delay_TXP2; + assign #(out_delay) TXP3 = delay_TXP3; + assign #(out_delay) TXPCSCLKSMPL0 = delay_TXPCSCLKSMPL0; + assign #(out_delay) TXPCSCLKSMPL1 = delay_TXPCSCLKSMPL1; + assign #(out_delay) TXPCSCLKSMPL2 = delay_TXPCSCLKSMPL2; + assign #(out_delay) TXPCSCLKSMPL3 = delay_TXPCSCLKSMPL3; + + assign #(INCLK_DELAY) delay_DCLK = DCLK; + assign #(INCLK_DELAY) delay_REFCLK = REFCLK; + assign #(INCLK_DELAY) delay_RXUSERCLKIN0 = RXUSERCLKIN0; + assign #(INCLK_DELAY) delay_RXUSERCLKIN1 = RXUSERCLKIN1; + assign #(INCLK_DELAY) delay_RXUSERCLKIN2 = RXUSERCLKIN2; + assign #(INCLK_DELAY) delay_RXUSERCLKIN3 = RXUSERCLKIN3; + assign #(INCLK_DELAY) delay_TXUSERCLKIN0 = TXUSERCLKIN0; + assign #(INCLK_DELAY) delay_TXUSERCLKIN1 = TXUSERCLKIN1; + assign #(INCLK_DELAY) delay_TXUSERCLKIN2 = TXUSERCLKIN2; + assign #(INCLK_DELAY) delay_TXUSERCLKIN3 = TXUSERCLKIN3; + + assign #(in_delay) delay_DADDR = DADDR; + assign #(in_delay) delay_DEN = DEN; + assign #(in_delay) delay_DFETRAINCTRL0 = DFETRAINCTRL0; + assign #(in_delay) delay_DFETRAINCTRL1 = DFETRAINCTRL1; + assign #(in_delay) delay_DFETRAINCTRL2 = DFETRAINCTRL2; + assign #(in_delay) delay_DFETRAINCTRL3 = DFETRAINCTRL3; + assign #(in_delay) delay_DI = DI; + assign #(in_delay) delay_DISABLEDRP = DISABLEDRP; + assign #(in_delay) delay_DWE = DWE; + assign #(in_delay) delay_GTHINIT = GTHINIT; + assign #(in_delay) delay_GTHRESET = GTHRESET; + assign #(in_delay) delay_GTHX2LANE01 = GTHX2LANE01; + assign #(in_delay) delay_GTHX2LANE23 = GTHX2LANE23; + assign #(in_delay) delay_GTHX4LANE = GTHX4LANE; + assign #(in_delay) delay_MGMTPCSLANESEL = MGMTPCSLANESEL; + assign #(in_delay) delay_MGMTPCSMMDADDR = MGMTPCSMMDADDR; + assign #(in_delay) delay_MGMTPCSREGADDR = MGMTPCSREGADDR; + assign #(in_delay) delay_MGMTPCSREGRD = MGMTPCSREGRD; + assign #(in_delay) delay_MGMTPCSREGWR = MGMTPCSREGWR; + assign #(in_delay) delay_MGMTPCSWRDATA = MGMTPCSWRDATA; + assign #(in_delay) delay_PLLPCSCLKDIV = PLLPCSCLKDIV; + assign #(in_delay) delay_PLLREFCLKSEL = PLLREFCLKSEL; + assign #(in_delay) delay_POWERDOWN0 = POWERDOWN0; + assign #(in_delay) delay_POWERDOWN1 = POWERDOWN1; + assign #(in_delay) delay_POWERDOWN2 = POWERDOWN2; + assign #(in_delay) delay_POWERDOWN3 = POWERDOWN3; + assign #(in_delay) delay_RXBUFRESET0 = RXBUFRESET0; + assign #(in_delay) delay_RXBUFRESET1 = RXBUFRESET1; + assign #(in_delay) delay_RXBUFRESET2 = RXBUFRESET2; + assign #(in_delay) delay_RXBUFRESET3 = RXBUFRESET3; + assign #(in_delay) delay_RXENCOMMADET0 = RXENCOMMADET0; + assign #(in_delay) delay_RXENCOMMADET1 = RXENCOMMADET1; + assign #(in_delay) delay_RXENCOMMADET2 = RXENCOMMADET2; + assign #(in_delay) delay_RXENCOMMADET3 = RXENCOMMADET3; + assign #(in_delay) delay_RXN0 = RXN0; + assign #(in_delay) delay_RXN1 = RXN1; + assign #(in_delay) delay_RXN2 = RXN2; + assign #(in_delay) delay_RXN3 = RXN3; + assign #(in_delay) delay_RXP0 = RXP0; + assign #(in_delay) delay_RXP1 = RXP1; + assign #(in_delay) delay_RXP2 = RXP2; + assign #(in_delay) delay_RXP3 = RXP3; + assign #(in_delay) delay_RXPOLARITY0 = RXPOLARITY0; + assign #(in_delay) delay_RXPOLARITY1 = RXPOLARITY1; + assign #(in_delay) delay_RXPOLARITY2 = RXPOLARITY2; + assign #(in_delay) delay_RXPOLARITY3 = RXPOLARITY3; + assign #(in_delay) delay_RXPOWERDOWN0 = RXPOWERDOWN0; + assign #(in_delay) delay_RXPOWERDOWN1 = RXPOWERDOWN1; + assign #(in_delay) delay_RXPOWERDOWN2 = RXPOWERDOWN2; + assign #(in_delay) delay_RXPOWERDOWN3 = RXPOWERDOWN3; + assign #(in_delay) delay_RXRATE0 = RXRATE0; + assign #(in_delay) delay_RXRATE1 = RXRATE1; + assign #(in_delay) delay_RXRATE2 = RXRATE2; + assign #(in_delay) delay_RXRATE3 = RXRATE3; + assign #(in_delay) delay_RXSLIP0 = RXSLIP0; + assign #(in_delay) delay_RXSLIP1 = RXSLIP1; + assign #(in_delay) delay_RXSLIP2 = RXSLIP2; + assign #(in_delay) delay_RXSLIP3 = RXSLIP3; + assign #(in_delay) delay_SAMPLERATE0 = SAMPLERATE0; + assign #(in_delay) delay_SAMPLERATE1 = SAMPLERATE1; + assign #(in_delay) delay_SAMPLERATE2 = SAMPLERATE2; + assign #(in_delay) delay_SAMPLERATE3 = SAMPLERATE3; + assign #(in_delay) delay_TXBUFRESET0 = TXBUFRESET0; + assign #(in_delay) delay_TXBUFRESET1 = TXBUFRESET1; + assign #(in_delay) delay_TXBUFRESET2 = TXBUFRESET2; + assign #(in_delay) delay_TXBUFRESET3 = TXBUFRESET3; + assign #(in_delay) delay_TXCTRL0 = TXCTRL0; + assign #(in_delay) delay_TXCTRL1 = TXCTRL1; + assign #(in_delay) delay_TXCTRL2 = TXCTRL2; + assign #(in_delay) delay_TXCTRL3 = TXCTRL3; + assign #(in_delay) delay_TXDATA0 = TXDATA0; + assign #(in_delay) delay_TXDATA1 = TXDATA1; + assign #(in_delay) delay_TXDATA2 = TXDATA2; + assign #(in_delay) delay_TXDATA3 = TXDATA3; + assign #(in_delay) delay_TXDATAMSB0 = TXDATAMSB0; + assign #(in_delay) delay_TXDATAMSB1 = TXDATAMSB1; + assign #(in_delay) delay_TXDATAMSB2 = TXDATAMSB2; + assign #(in_delay) delay_TXDATAMSB3 = TXDATAMSB3; + assign #(in_delay) delay_TXDEEMPH0 = TXDEEMPH0; + assign #(in_delay) delay_TXDEEMPH1 = TXDEEMPH1; + assign #(in_delay) delay_TXDEEMPH2 = TXDEEMPH2; + assign #(in_delay) delay_TXDEEMPH3 = TXDEEMPH3; + assign #(in_delay) delay_TXMARGIN0 = TXMARGIN0; + assign #(in_delay) delay_TXMARGIN1 = TXMARGIN1; + assign #(in_delay) delay_TXMARGIN2 = TXMARGIN2; + assign #(in_delay) delay_TXMARGIN3 = TXMARGIN3; + assign #(in_delay) delay_TXPOWERDOWN0 = TXPOWERDOWN0; + assign #(in_delay) delay_TXPOWERDOWN1 = TXPOWERDOWN1; + assign #(in_delay) delay_TXPOWERDOWN2 = TXPOWERDOWN2; + assign #(in_delay) delay_TXPOWERDOWN3 = TXPOWERDOWN3; + assign #(in_delay) delay_TXRATE0 = TXRATE0; + assign #(in_delay) delay_TXRATE1 = TXRATE1; + assign #(in_delay) delay_TXRATE2 = TXRATE2; + assign #(in_delay) delay_TXRATE3 = TXRATE3; + + B_GTHE1_QUAD #( + .BER_CONST_PTRN0 (BER_CONST_PTRN0), + .BER_CONST_PTRN1 (BER_CONST_PTRN1), + .BUFFER_CONFIG_LANE0 (BUFFER_CONFIG_LANE0), + .BUFFER_CONFIG_LANE1 (BUFFER_CONFIG_LANE1), + .BUFFER_CONFIG_LANE2 (BUFFER_CONFIG_LANE2), + .BUFFER_CONFIG_LANE3 (BUFFER_CONFIG_LANE3), + .DFE_TRAIN_CTRL_LANE0 (DFE_TRAIN_CTRL_LANE0), + .DFE_TRAIN_CTRL_LANE1 (DFE_TRAIN_CTRL_LANE1), + .DFE_TRAIN_CTRL_LANE2 (DFE_TRAIN_CTRL_LANE2), + .DFE_TRAIN_CTRL_LANE3 (DFE_TRAIN_CTRL_LANE3), + .DLL_CFG0 (DLL_CFG0), + .DLL_CFG1 (DLL_CFG1), + .E10GBASEKR_LD_COEFF_UPD_LANE0 (E10GBASEKR_LD_COEFF_UPD_LANE0), + .E10GBASEKR_LD_COEFF_UPD_LANE1 (E10GBASEKR_LD_COEFF_UPD_LANE1), + .E10GBASEKR_LD_COEFF_UPD_LANE2 (E10GBASEKR_LD_COEFF_UPD_LANE2), + .E10GBASEKR_LD_COEFF_UPD_LANE3 (E10GBASEKR_LD_COEFF_UPD_LANE3), + .E10GBASEKR_LP_COEFF_UPD_LANE0 (E10GBASEKR_LP_COEFF_UPD_LANE0), + .E10GBASEKR_LP_COEFF_UPD_LANE1 (E10GBASEKR_LP_COEFF_UPD_LANE1), + .E10GBASEKR_LP_COEFF_UPD_LANE2 (E10GBASEKR_LP_COEFF_UPD_LANE2), + .E10GBASEKR_LP_COEFF_UPD_LANE3 (E10GBASEKR_LP_COEFF_UPD_LANE3), + .E10GBASEKR_PMA_CTRL_LANE0 (E10GBASEKR_PMA_CTRL_LANE0), + .E10GBASEKR_PMA_CTRL_LANE1 (E10GBASEKR_PMA_CTRL_LANE1), + .E10GBASEKR_PMA_CTRL_LANE2 (E10GBASEKR_PMA_CTRL_LANE2), + .E10GBASEKR_PMA_CTRL_LANE3 (E10GBASEKR_PMA_CTRL_LANE3), + .E10GBASEKX_CTRL_LANE0 (E10GBASEKX_CTRL_LANE0), + .E10GBASEKX_CTRL_LANE1 (E10GBASEKX_CTRL_LANE1), + .E10GBASEKX_CTRL_LANE2 (E10GBASEKX_CTRL_LANE2), + .E10GBASEKX_CTRL_LANE3 (E10GBASEKX_CTRL_LANE3), + .E10GBASER_PCS_CFG_LANE0 (E10GBASER_PCS_CFG_LANE0), + .E10GBASER_PCS_CFG_LANE1 (E10GBASER_PCS_CFG_LANE1), + .E10GBASER_PCS_CFG_LANE2 (E10GBASER_PCS_CFG_LANE2), + .E10GBASER_PCS_CFG_LANE3 (E10GBASER_PCS_CFG_LANE3), + .E10GBASER_PCS_SEEDA0_LANE0 (E10GBASER_PCS_SEEDA0_LANE0), + .E10GBASER_PCS_SEEDA0_LANE1 (E10GBASER_PCS_SEEDA0_LANE1), + .E10GBASER_PCS_SEEDA0_LANE2 (E10GBASER_PCS_SEEDA0_LANE2), + .E10GBASER_PCS_SEEDA0_LANE3 (E10GBASER_PCS_SEEDA0_LANE3), + .E10GBASER_PCS_SEEDA1_LANE0 (E10GBASER_PCS_SEEDA1_LANE0), + .E10GBASER_PCS_SEEDA1_LANE1 (E10GBASER_PCS_SEEDA1_LANE1), + .E10GBASER_PCS_SEEDA1_LANE2 (E10GBASER_PCS_SEEDA1_LANE2), + .E10GBASER_PCS_SEEDA1_LANE3 (E10GBASER_PCS_SEEDA1_LANE3), + .E10GBASER_PCS_SEEDA2_LANE0 (E10GBASER_PCS_SEEDA2_LANE0), + .E10GBASER_PCS_SEEDA2_LANE1 (E10GBASER_PCS_SEEDA2_LANE1), + .E10GBASER_PCS_SEEDA2_LANE2 (E10GBASER_PCS_SEEDA2_LANE2), + .E10GBASER_PCS_SEEDA2_LANE3 (E10GBASER_PCS_SEEDA2_LANE3), + .E10GBASER_PCS_SEEDA3_LANE0 (E10GBASER_PCS_SEEDA3_LANE0), + .E10GBASER_PCS_SEEDA3_LANE1 (E10GBASER_PCS_SEEDA3_LANE1), + .E10GBASER_PCS_SEEDA3_LANE2 (E10GBASER_PCS_SEEDA3_LANE2), + .E10GBASER_PCS_SEEDA3_LANE3 (E10GBASER_PCS_SEEDA3_LANE3), + .E10GBASER_PCS_SEEDB0_LANE0 (E10GBASER_PCS_SEEDB0_LANE0), + .E10GBASER_PCS_SEEDB0_LANE1 (E10GBASER_PCS_SEEDB0_LANE1), + .E10GBASER_PCS_SEEDB0_LANE2 (E10GBASER_PCS_SEEDB0_LANE2), + .E10GBASER_PCS_SEEDB0_LANE3 (E10GBASER_PCS_SEEDB0_LANE3), + .E10GBASER_PCS_SEEDB1_LANE0 (E10GBASER_PCS_SEEDB1_LANE0), + .E10GBASER_PCS_SEEDB1_LANE1 (E10GBASER_PCS_SEEDB1_LANE1), + .E10GBASER_PCS_SEEDB1_LANE2 (E10GBASER_PCS_SEEDB1_LANE2), + .E10GBASER_PCS_SEEDB1_LANE3 (E10GBASER_PCS_SEEDB1_LANE3), + .E10GBASER_PCS_SEEDB2_LANE0 (E10GBASER_PCS_SEEDB2_LANE0), + .E10GBASER_PCS_SEEDB2_LANE1 (E10GBASER_PCS_SEEDB2_LANE1), + .E10GBASER_PCS_SEEDB2_LANE2 (E10GBASER_PCS_SEEDB2_LANE2), + .E10GBASER_PCS_SEEDB2_LANE3 (E10GBASER_PCS_SEEDB2_LANE3), + .E10GBASER_PCS_SEEDB3_LANE0 (E10GBASER_PCS_SEEDB3_LANE0), + .E10GBASER_PCS_SEEDB3_LANE1 (E10GBASER_PCS_SEEDB3_LANE1), + .E10GBASER_PCS_SEEDB3_LANE2 (E10GBASER_PCS_SEEDB3_LANE2), + .E10GBASER_PCS_SEEDB3_LANE3 (E10GBASER_PCS_SEEDB3_LANE3), + .E10GBASER_PCS_TEST_CTRL_LANE0 (E10GBASER_PCS_TEST_CTRL_LANE0), + .E10GBASER_PCS_TEST_CTRL_LANE1 (E10GBASER_PCS_TEST_CTRL_LANE1), + .E10GBASER_PCS_TEST_CTRL_LANE2 (E10GBASER_PCS_TEST_CTRL_LANE2), + .E10GBASER_PCS_TEST_CTRL_LANE3 (E10GBASER_PCS_TEST_CTRL_LANE3), + .E10GBASEX_PCS_TSTCTRL_LANE0 (E10GBASEX_PCS_TSTCTRL_LANE0), + .E10GBASEX_PCS_TSTCTRL_LANE1 (E10GBASEX_PCS_TSTCTRL_LANE1), + .E10GBASEX_PCS_TSTCTRL_LANE2 (E10GBASEX_PCS_TSTCTRL_LANE2), + .E10GBASEX_PCS_TSTCTRL_LANE3 (E10GBASEX_PCS_TSTCTRL_LANE3), + .GLBL0_NOISE_CTRL (GLBL0_NOISE_CTRL), + .GLBL_AMON_SEL (GLBL_AMON_SEL), + .GLBL_DMON_SEL (GLBL_DMON_SEL), + .GLBL_PWR_CTRL (GLBL_PWR_CTRL), + .GTH_CFG_PWRUP_LANE0 (GTH_CFG_PWRUP_LANE0), + .GTH_CFG_PWRUP_LANE1 (GTH_CFG_PWRUP_LANE1), + .GTH_CFG_PWRUP_LANE2 (GTH_CFG_PWRUP_LANE2), + .GTH_CFG_PWRUP_LANE3 (GTH_CFG_PWRUP_LANE3), + .LANE_AMON_SEL (LANE_AMON_SEL), + .LANE_DMON_SEL (LANE_DMON_SEL), + .LANE_LNK_CFGOVRD (LANE_LNK_CFGOVRD), + .LANE_PWR_CTRL_LANE0 (LANE_PWR_CTRL_LANE0), + .LANE_PWR_CTRL_LANE1 (LANE_PWR_CTRL_LANE1), + .LANE_PWR_CTRL_LANE2 (LANE_PWR_CTRL_LANE2), + .LANE_PWR_CTRL_LANE3 (LANE_PWR_CTRL_LANE3), + .LNK_TRN_CFG_LANE0 (LNK_TRN_CFG_LANE0), + .LNK_TRN_CFG_LANE1 (LNK_TRN_CFG_LANE1), + .LNK_TRN_CFG_LANE2 (LNK_TRN_CFG_LANE2), + .LNK_TRN_CFG_LANE3 (LNK_TRN_CFG_LANE3), + .LNK_TRN_COEFF_REQ_LANE0 (LNK_TRN_COEFF_REQ_LANE0), + .LNK_TRN_COEFF_REQ_LANE1 (LNK_TRN_COEFF_REQ_LANE1), + .LNK_TRN_COEFF_REQ_LANE2 (LNK_TRN_COEFF_REQ_LANE2), + .LNK_TRN_COEFF_REQ_LANE3 (LNK_TRN_COEFF_REQ_LANE3), + .MISC_CFG (MISC_CFG), + .MODE_CFG1 (MODE_CFG1), + .MODE_CFG2 (MODE_CFG2), + .MODE_CFG3 (MODE_CFG3), + .MODE_CFG4 (MODE_CFG4), + .MODE_CFG5 (MODE_CFG5), + .MODE_CFG6 (MODE_CFG6), + .MODE_CFG7 (MODE_CFG7), + .PCS_ABILITY_LANE0 (PCS_ABILITY_LANE0), + .PCS_ABILITY_LANE1 (PCS_ABILITY_LANE1), + .PCS_ABILITY_LANE2 (PCS_ABILITY_LANE2), + .PCS_ABILITY_LANE3 (PCS_ABILITY_LANE3), + .PCS_CTRL1_LANE0 (PCS_CTRL1_LANE0), + .PCS_CTRL1_LANE1 (PCS_CTRL1_LANE1), + .PCS_CTRL1_LANE2 (PCS_CTRL1_LANE2), + .PCS_CTRL1_LANE3 (PCS_CTRL1_LANE3), + .PCS_CTRL2_LANE0 (PCS_CTRL2_LANE0), + .PCS_CTRL2_LANE1 (PCS_CTRL2_LANE1), + .PCS_CTRL2_LANE2 (PCS_CTRL2_LANE2), + .PCS_CTRL2_LANE3 (PCS_CTRL2_LANE3), + .PCS_MISC_CFG_0_LANE0 (PCS_MISC_CFG_0_LANE0), + .PCS_MISC_CFG_0_LANE1 (PCS_MISC_CFG_0_LANE1), + .PCS_MISC_CFG_0_LANE2 (PCS_MISC_CFG_0_LANE2), + .PCS_MISC_CFG_0_LANE3 (PCS_MISC_CFG_0_LANE3), + .PCS_MISC_CFG_1_LANE0 (PCS_MISC_CFG_1_LANE0), + .PCS_MISC_CFG_1_LANE1 (PCS_MISC_CFG_1_LANE1), + .PCS_MISC_CFG_1_LANE2 (PCS_MISC_CFG_1_LANE2), + .PCS_MISC_CFG_1_LANE3 (PCS_MISC_CFG_1_LANE3), + .PCS_MODE_LANE0 (PCS_MODE_LANE0), + .PCS_MODE_LANE1 (PCS_MODE_LANE1), + .PCS_MODE_LANE2 (PCS_MODE_LANE2), + .PCS_MODE_LANE3 (PCS_MODE_LANE3), + .PCS_RESET_1_LANE0 (PCS_RESET_1_LANE0), + .PCS_RESET_1_LANE1 (PCS_RESET_1_LANE1), + .PCS_RESET_1_LANE2 (PCS_RESET_1_LANE2), + .PCS_RESET_1_LANE3 (PCS_RESET_1_LANE3), + .PCS_RESET_LANE0 (PCS_RESET_LANE0), + .PCS_RESET_LANE1 (PCS_RESET_LANE1), + .PCS_RESET_LANE2 (PCS_RESET_LANE2), + .PCS_RESET_LANE3 (PCS_RESET_LANE3), + .PCS_TYPE_LANE0 (PCS_TYPE_LANE0), + .PCS_TYPE_LANE1 (PCS_TYPE_LANE1), + .PCS_TYPE_LANE2 (PCS_TYPE_LANE2), + .PCS_TYPE_LANE3 (PCS_TYPE_LANE3), + .PLL_CFG0 (PLL_CFG0), + .PLL_CFG1 (PLL_CFG1), + .PLL_CFG2 (PLL_CFG2), + .PMA_CTRL1_LANE0 (PMA_CTRL1_LANE0), + .PMA_CTRL1_LANE1 (PMA_CTRL1_LANE1), + .PMA_CTRL1_LANE2 (PMA_CTRL1_LANE2), + .PMA_CTRL1_LANE3 (PMA_CTRL1_LANE3), + .PMA_CTRL2_LANE0 (PMA_CTRL2_LANE0), + .PMA_CTRL2_LANE1 (PMA_CTRL2_LANE1), + .PMA_CTRL2_LANE2 (PMA_CTRL2_LANE2), + .PMA_CTRL2_LANE3 (PMA_CTRL2_LANE3), + .PMA_LPBK_CTRL_LANE0 (PMA_LPBK_CTRL_LANE0), + .PMA_LPBK_CTRL_LANE1 (PMA_LPBK_CTRL_LANE1), + .PMA_LPBK_CTRL_LANE2 (PMA_LPBK_CTRL_LANE2), + .PMA_LPBK_CTRL_LANE3 (PMA_LPBK_CTRL_LANE3), + .PRBS_BER_CFG0_LANE0 (PRBS_BER_CFG0_LANE0), + .PRBS_BER_CFG0_LANE1 (PRBS_BER_CFG0_LANE1), + .PRBS_BER_CFG0_LANE2 (PRBS_BER_CFG0_LANE2), + .PRBS_BER_CFG0_LANE3 (PRBS_BER_CFG0_LANE3), + .PRBS_BER_CFG1_LANE0 (PRBS_BER_CFG1_LANE0), + .PRBS_BER_CFG1_LANE1 (PRBS_BER_CFG1_LANE1), + .PRBS_BER_CFG1_LANE2 (PRBS_BER_CFG1_LANE2), + .PRBS_BER_CFG1_LANE3 (PRBS_BER_CFG1_LANE3), + .PRBS_CFG_LANE0 (PRBS_CFG_LANE0), + .PRBS_CFG_LANE1 (PRBS_CFG_LANE1), + .PRBS_CFG_LANE2 (PRBS_CFG_LANE2), + .PRBS_CFG_LANE3 (PRBS_CFG_LANE3), + .PTRN_CFG0_LSB (PTRN_CFG0_LSB), + .PTRN_CFG0_MSB (PTRN_CFG0_MSB), + .PTRN_LEN_CFG (PTRN_LEN_CFG), + .PWRUP_DLY (PWRUP_DLY), + .RX_AEQ_VAL0_LANE0 (RX_AEQ_VAL0_LANE0), + .RX_AEQ_VAL0_LANE1 (RX_AEQ_VAL0_LANE1), + .RX_AEQ_VAL0_LANE2 (RX_AEQ_VAL0_LANE2), + .RX_AEQ_VAL0_LANE3 (RX_AEQ_VAL0_LANE3), + .RX_AEQ_VAL1_LANE0 (RX_AEQ_VAL1_LANE0), + .RX_AEQ_VAL1_LANE1 (RX_AEQ_VAL1_LANE1), + .RX_AEQ_VAL1_LANE2 (RX_AEQ_VAL1_LANE2), + .RX_AEQ_VAL1_LANE3 (RX_AEQ_VAL1_LANE3), + .RX_AGC_CTRL_LANE0 (RX_AGC_CTRL_LANE0), + .RX_AGC_CTRL_LANE1 (RX_AGC_CTRL_LANE1), + .RX_AGC_CTRL_LANE2 (RX_AGC_CTRL_LANE2), + .RX_AGC_CTRL_LANE3 (RX_AGC_CTRL_LANE3), + .RX_CDR_CTRL0_LANE0 (RX_CDR_CTRL0_LANE0), + .RX_CDR_CTRL0_LANE1 (RX_CDR_CTRL0_LANE1), + .RX_CDR_CTRL0_LANE2 (RX_CDR_CTRL0_LANE2), + .RX_CDR_CTRL0_LANE3 (RX_CDR_CTRL0_LANE3), + .RX_CDR_CTRL1_LANE0 (RX_CDR_CTRL1_LANE0), + .RX_CDR_CTRL1_LANE1 (RX_CDR_CTRL1_LANE1), + .RX_CDR_CTRL1_LANE2 (RX_CDR_CTRL1_LANE2), + .RX_CDR_CTRL1_LANE3 (RX_CDR_CTRL1_LANE3), + .RX_CDR_CTRL2_LANE0 (RX_CDR_CTRL2_LANE0), + .RX_CDR_CTRL2_LANE1 (RX_CDR_CTRL2_LANE1), + .RX_CDR_CTRL2_LANE2 (RX_CDR_CTRL2_LANE2), + .RX_CDR_CTRL2_LANE3 (RX_CDR_CTRL2_LANE3), + .RX_CFG0_LANE0 (RX_CFG0_LANE0), + .RX_CFG0_LANE1 (RX_CFG0_LANE1), + .RX_CFG0_LANE2 (RX_CFG0_LANE2), + .RX_CFG0_LANE3 (RX_CFG0_LANE3), + .RX_CFG1_LANE0 (RX_CFG1_LANE0), + .RX_CFG1_LANE1 (RX_CFG1_LANE1), + .RX_CFG1_LANE2 (RX_CFG1_LANE2), + .RX_CFG1_LANE3 (RX_CFG1_LANE3), + .RX_CFG2_LANE0 (RX_CFG2_LANE0), + .RX_CFG2_LANE1 (RX_CFG2_LANE1), + .RX_CFG2_LANE2 (RX_CFG2_LANE2), + .RX_CFG2_LANE3 (RX_CFG2_LANE3), + .RX_CTLE_CTRL_LANE0 (RX_CTLE_CTRL_LANE0), + .RX_CTLE_CTRL_LANE1 (RX_CTLE_CTRL_LANE1), + .RX_CTLE_CTRL_LANE2 (RX_CTLE_CTRL_LANE2), + .RX_CTLE_CTRL_LANE3 (RX_CTLE_CTRL_LANE3), + .RX_CTRL_OVRD_LANE0 (RX_CTRL_OVRD_LANE0), + .RX_CTRL_OVRD_LANE1 (RX_CTRL_OVRD_LANE1), + .RX_CTRL_OVRD_LANE2 (RX_CTRL_OVRD_LANE2), + .RX_CTRL_OVRD_LANE3 (RX_CTRL_OVRD_LANE3), + .RX_FABRIC_WIDTH0 (RX_FABRIC_WIDTH0), + .RX_FABRIC_WIDTH1 (RX_FABRIC_WIDTH1), + .RX_FABRIC_WIDTH2 (RX_FABRIC_WIDTH2), + .RX_FABRIC_WIDTH3 (RX_FABRIC_WIDTH3), + .RX_LOOP_CTRL_LANE0 (RX_LOOP_CTRL_LANE0), + .RX_LOOP_CTRL_LANE1 (RX_LOOP_CTRL_LANE1), + .RX_LOOP_CTRL_LANE2 (RX_LOOP_CTRL_LANE2), + .RX_LOOP_CTRL_LANE3 (RX_LOOP_CTRL_LANE3), + .RX_MVAL0_LANE0 (RX_MVAL0_LANE0), + .RX_MVAL0_LANE1 (RX_MVAL0_LANE1), + .RX_MVAL0_LANE2 (RX_MVAL0_LANE2), + .RX_MVAL0_LANE3 (RX_MVAL0_LANE3), + .RX_MVAL1_LANE0 (RX_MVAL1_LANE0), + .RX_MVAL1_LANE1 (RX_MVAL1_LANE1), + .RX_MVAL1_LANE2 (RX_MVAL1_LANE2), + .RX_MVAL1_LANE3 (RX_MVAL1_LANE3), + .RX_P0S_CTRL (RX_P0S_CTRL), + .RX_P0_CTRL (RX_P0_CTRL), + .RX_P1_CTRL (RX_P1_CTRL), + .RX_P2_CTRL (RX_P2_CTRL), + .RX_PI_CTRL0 (RX_PI_CTRL0), + .RX_PI_CTRL1 (RX_PI_CTRL1), + .SIM_GTHRESET_SPEEDUP (SIM_GTHRESET_SPEEDUP), + .SIM_VERSION (SIM_VERSION), + .SLICE_CFG (SLICE_CFG), + .SLICE_NOISE_CTRL_0_LANE01 (SLICE_NOISE_CTRL_0_LANE01), + .SLICE_NOISE_CTRL_0_LANE23 (SLICE_NOISE_CTRL_0_LANE23), + .SLICE_NOISE_CTRL_1_LANE01 (SLICE_NOISE_CTRL_1_LANE01), + .SLICE_NOISE_CTRL_1_LANE23 (SLICE_NOISE_CTRL_1_LANE23), + .SLICE_NOISE_CTRL_2_LANE01 (SLICE_NOISE_CTRL_2_LANE01), + .SLICE_NOISE_CTRL_2_LANE23 (SLICE_NOISE_CTRL_2_LANE23), + .SLICE_TX_RESET_LANE01 (SLICE_TX_RESET_LANE01), + .SLICE_TX_RESET_LANE23 (SLICE_TX_RESET_LANE23), + .TERM_CTRL_LANE0 (TERM_CTRL_LANE0), + .TERM_CTRL_LANE1 (TERM_CTRL_LANE1), + .TERM_CTRL_LANE2 (TERM_CTRL_LANE2), + .TERM_CTRL_LANE3 (TERM_CTRL_LANE3), + .TX_CFG0_LANE0 (TX_CFG0_LANE0), + .TX_CFG0_LANE1 (TX_CFG0_LANE1), + .TX_CFG0_LANE2 (TX_CFG0_LANE2), + .TX_CFG0_LANE3 (TX_CFG0_LANE3), + .TX_CFG1_LANE0 (TX_CFG1_LANE0), + .TX_CFG1_LANE1 (TX_CFG1_LANE1), + .TX_CFG1_LANE2 (TX_CFG1_LANE2), + .TX_CFG1_LANE3 (TX_CFG1_LANE3), + .TX_CFG2_LANE0 (TX_CFG2_LANE0), + .TX_CFG2_LANE1 (TX_CFG2_LANE1), + .TX_CFG2_LANE2 (TX_CFG2_LANE2), + .TX_CFG2_LANE3 (TX_CFG2_LANE3), + .TX_CLK_SEL0_LANE0 (TX_CLK_SEL0_LANE0), + .TX_CLK_SEL0_LANE1 (TX_CLK_SEL0_LANE1), + .TX_CLK_SEL0_LANE2 (TX_CLK_SEL0_LANE2), + .TX_CLK_SEL0_LANE3 (TX_CLK_SEL0_LANE3), + .TX_CLK_SEL1_LANE0 (TX_CLK_SEL1_LANE0), + .TX_CLK_SEL1_LANE1 (TX_CLK_SEL1_LANE1), + .TX_CLK_SEL1_LANE2 (TX_CLK_SEL1_LANE2), + .TX_CLK_SEL1_LANE3 (TX_CLK_SEL1_LANE3), + .TX_DISABLE_LANE0 (TX_DISABLE_LANE0), + .TX_DISABLE_LANE1 (TX_DISABLE_LANE1), + .TX_DISABLE_LANE2 (TX_DISABLE_LANE2), + .TX_DISABLE_LANE3 (TX_DISABLE_LANE3), + .TX_FABRIC_WIDTH0 (TX_FABRIC_WIDTH0), + .TX_FABRIC_WIDTH1 (TX_FABRIC_WIDTH1), + .TX_FABRIC_WIDTH2 (TX_FABRIC_WIDTH2), + .TX_FABRIC_WIDTH3 (TX_FABRIC_WIDTH3), + .TX_P0P0S_CTRL (TX_P0P0S_CTRL), + .TX_P1P2_CTRL (TX_P1P2_CTRL), + .TX_PREEMPH_LANE0 (TX_PREEMPH_LANE0), + .TX_PREEMPH_LANE1 (TX_PREEMPH_LANE1), + .TX_PREEMPH_LANE2 (TX_PREEMPH_LANE2), + .TX_PREEMPH_LANE3 (TX_PREEMPH_LANE3), + .TX_PWR_RATE_OVRD_LANE0 (TX_PWR_RATE_OVRD_LANE0), + .TX_PWR_RATE_OVRD_LANE1 (TX_PWR_RATE_OVRD_LANE1), + .TX_PWR_RATE_OVRD_LANE2 (TX_PWR_RATE_OVRD_LANE2), + .TX_PWR_RATE_OVRD_LANE3 (TX_PWR_RATE_OVRD_LANE3)) + + B_GTHE1_QUAD_INST ( + .DRDY (delay_DRDY), + .DRPDO (delay_DRPDO), + .GTHINITDONE (delay_GTHINITDONE), + .MGMTPCSRDACK (delay_MGMTPCSRDACK), + .MGMTPCSRDDATA (delay_MGMTPCSRDDATA), + .RXCODEERR0 (delay_RXCODEERR0), + .RXCODEERR1 (delay_RXCODEERR1), + .RXCODEERR2 (delay_RXCODEERR2), + .RXCODEERR3 (delay_RXCODEERR3), + .RXCTRL0 (delay_RXCTRL0), + .RXCTRL1 (delay_RXCTRL1), + .RXCTRL2 (delay_RXCTRL2), + .RXCTRL3 (delay_RXCTRL3), + .RXCTRLACK0 (delay_RXCTRLACK0), + .RXCTRLACK1 (delay_RXCTRLACK1), + .RXCTRLACK2 (delay_RXCTRLACK2), + .RXCTRLACK3 (delay_RXCTRLACK3), + .RXDATA0 (delay_RXDATA0), + .RXDATA1 (delay_RXDATA1), + .RXDATA2 (delay_RXDATA2), + .RXDATA3 (delay_RXDATA3), + .RXDATATAP0 (delay_RXDATATAP0), + .RXDATATAP1 (delay_RXDATATAP1), + .RXDATATAP2 (delay_RXDATATAP2), + .RXDATATAP3 (delay_RXDATATAP3), + .RXDISPERR0 (delay_RXDISPERR0), + .RXDISPERR1 (delay_RXDISPERR1), + .RXDISPERR2 (delay_RXDISPERR2), + .RXDISPERR3 (delay_RXDISPERR3), + .RXPCSCLKSMPL0 (delay_RXPCSCLKSMPL0), + .RXPCSCLKSMPL1 (delay_RXPCSCLKSMPL1), + .RXPCSCLKSMPL2 (delay_RXPCSCLKSMPL2), + .RXPCSCLKSMPL3 (delay_RXPCSCLKSMPL3), + .RXUSERCLKOUT0 (delay_RXUSERCLKOUT0), + .RXUSERCLKOUT1 (delay_RXUSERCLKOUT1), + .RXUSERCLKOUT2 (delay_RXUSERCLKOUT2), + .RXUSERCLKOUT3 (delay_RXUSERCLKOUT3), + .RXVALID0 (delay_RXVALID0), + .RXVALID1 (delay_RXVALID1), + .RXVALID2 (delay_RXVALID2), + .RXVALID3 (delay_RXVALID3), + .TSTPATH (delay_TSTPATH), + .TSTREFCLKFAB (delay_TSTREFCLKFAB), + .TSTREFCLKOUT (delay_TSTREFCLKOUT), + .TXCTRLACK0 (delay_TXCTRLACK0), + .TXCTRLACK1 (delay_TXCTRLACK1), + .TXCTRLACK2 (delay_TXCTRLACK2), + .TXCTRLACK3 (delay_TXCTRLACK3), + .TXDATATAP10 (delay_TXDATATAP10), + .TXDATATAP11 (delay_TXDATATAP11), + .TXDATATAP12 (delay_TXDATATAP12), + .TXDATATAP13 (delay_TXDATATAP13), + .TXDATATAP20 (delay_TXDATATAP20), + .TXDATATAP21 (delay_TXDATATAP21), + .TXDATATAP22 (delay_TXDATATAP22), + .TXDATATAP23 (delay_TXDATATAP23), + .TXN0 (delay_TXN0), + .TXN1 (delay_TXN1), + .TXN2 (delay_TXN2), + .TXN3 (delay_TXN3), + .TXP0 (delay_TXP0), + .TXP1 (delay_TXP1), + .TXP2 (delay_TXP2), + .TXP3 (delay_TXP3), + .TXPCSCLKSMPL0 (delay_TXPCSCLKSMPL0), + .TXPCSCLKSMPL1 (delay_TXPCSCLKSMPL1), + .TXPCSCLKSMPL2 (delay_TXPCSCLKSMPL2), + .TXPCSCLKSMPL3 (delay_TXPCSCLKSMPL3), + .TXUSERCLKOUT0 (delay_TXUSERCLKOUT0), + .TXUSERCLKOUT1 (delay_TXUSERCLKOUT1), + .TXUSERCLKOUT2 (delay_TXUSERCLKOUT2), + .TXUSERCLKOUT3 (delay_TXUSERCLKOUT3), + .DADDR (delay_DADDR), + .DCLK (delay_DCLK), + .DEN (delay_DEN), + .DFETRAINCTRL0 (delay_DFETRAINCTRL0), + .DFETRAINCTRL1 (delay_DFETRAINCTRL1), + .DFETRAINCTRL2 (delay_DFETRAINCTRL2), + .DFETRAINCTRL3 (delay_DFETRAINCTRL3), + .DI (delay_DI), + .DISABLEDRP (delay_DISABLEDRP), + .DWE (delay_DWE), + .GTHINIT (delay_GTHINIT), + .GTHRESET (delay_GTHRESET), + .GTHX2LANE01 (delay_GTHX2LANE01), + .GTHX2LANE23 (delay_GTHX2LANE23), + .GTHX4LANE (delay_GTHX4LANE), + .MGMTPCSLANESEL (delay_MGMTPCSLANESEL), + .MGMTPCSMMDADDR (delay_MGMTPCSMMDADDR), + .MGMTPCSREGADDR (delay_MGMTPCSREGADDR), + .MGMTPCSREGRD (delay_MGMTPCSREGRD), + .MGMTPCSREGWR (delay_MGMTPCSREGWR), + .MGMTPCSWRDATA (delay_MGMTPCSWRDATA), + .PLLPCSCLKDIV (delay_PLLPCSCLKDIV), + .PLLREFCLKSEL (delay_PLLREFCLKSEL), + .POWERDOWN0 (delay_POWERDOWN0), + .POWERDOWN1 (delay_POWERDOWN1), + .POWERDOWN2 (delay_POWERDOWN2), + .POWERDOWN3 (delay_POWERDOWN3), + .REFCLK (delay_REFCLK), + .RXBUFRESET0 (delay_RXBUFRESET0), + .RXBUFRESET1 (delay_RXBUFRESET1), + .RXBUFRESET2 (delay_RXBUFRESET2), + .RXBUFRESET3 (delay_RXBUFRESET3), + .RXENCOMMADET0 (delay_RXENCOMMADET0), + .RXENCOMMADET1 (delay_RXENCOMMADET1), + .RXENCOMMADET2 (delay_RXENCOMMADET2), + .RXENCOMMADET3 (delay_RXENCOMMADET3), + .RXN0 (delay_RXN0), + .RXN1 (delay_RXN1), + .RXN2 (delay_RXN2), + .RXN3 (delay_RXN3), + .RXP0 (delay_RXP0), + .RXP1 (delay_RXP1), + .RXP2 (delay_RXP2), + .RXP3 (delay_RXP3), + .RXPOLARITY0 (delay_RXPOLARITY0), + .RXPOLARITY1 (delay_RXPOLARITY1), + .RXPOLARITY2 (delay_RXPOLARITY2), + .RXPOLARITY3 (delay_RXPOLARITY3), + .RXPOWERDOWN0 (delay_RXPOWERDOWN0), + .RXPOWERDOWN1 (delay_RXPOWERDOWN1), + .RXPOWERDOWN2 (delay_RXPOWERDOWN2), + .RXPOWERDOWN3 (delay_RXPOWERDOWN3), + .RXRATE0 (delay_RXRATE0), + .RXRATE1 (delay_RXRATE1), + .RXRATE2 (delay_RXRATE2), + .RXRATE3 (delay_RXRATE3), + .RXSLIP0 (delay_RXSLIP0), + .RXSLIP1 (delay_RXSLIP1), + .RXSLIP2 (delay_RXSLIP2), + .RXSLIP3 (delay_RXSLIP3), + .RXUSERCLKIN0 (delay_RXUSERCLKIN0), + .RXUSERCLKIN1 (delay_RXUSERCLKIN1), + .RXUSERCLKIN2 (delay_RXUSERCLKIN2), + .RXUSERCLKIN3 (delay_RXUSERCLKIN3), + .SAMPLERATE0 (delay_SAMPLERATE0), + .SAMPLERATE1 (delay_SAMPLERATE1), + .SAMPLERATE2 (delay_SAMPLERATE2), + .SAMPLERATE3 (delay_SAMPLERATE3), + .TXBUFRESET0 (delay_TXBUFRESET0), + .TXBUFRESET1 (delay_TXBUFRESET1), + .TXBUFRESET2 (delay_TXBUFRESET2), + .TXBUFRESET3 (delay_TXBUFRESET3), + .TXCTRL0 (delay_TXCTRL0), + .TXCTRL1 (delay_TXCTRL1), + .TXCTRL2 (delay_TXCTRL2), + .TXCTRL3 (delay_TXCTRL3), + .TXDATA0 (delay_TXDATA0), + .TXDATA1 (delay_TXDATA1), + .TXDATA2 (delay_TXDATA2), + .TXDATA3 (delay_TXDATA3), + .TXDATAMSB0 (delay_TXDATAMSB0), + .TXDATAMSB1 (delay_TXDATAMSB1), + .TXDATAMSB2 (delay_TXDATAMSB2), + .TXDATAMSB3 (delay_TXDATAMSB3), + .TXDEEMPH0 (delay_TXDEEMPH0), + .TXDEEMPH1 (delay_TXDEEMPH1), + .TXDEEMPH2 (delay_TXDEEMPH2), + .TXDEEMPH3 (delay_TXDEEMPH3), + .TXMARGIN0 (delay_TXMARGIN0), + .TXMARGIN1 (delay_TXMARGIN1), + .TXMARGIN2 (delay_TXMARGIN2), + .TXMARGIN3 (delay_TXMARGIN3), + .TXPOWERDOWN0 (delay_TXPOWERDOWN0), + .TXPOWERDOWN1 (delay_TXPOWERDOWN1), + .TXPOWERDOWN2 (delay_TXPOWERDOWN2), + .TXPOWERDOWN3 (delay_TXPOWERDOWN3), + .TXRATE0 (delay_TXRATE0), + .TXRATE1 (delay_TXRATE1), + .TXRATE2 (delay_TXRATE2), + .TXRATE3 (delay_TXRATE3), + .TXUSERCLKIN0 (delay_TXUSERCLKIN0), + .TXUSERCLKIN1 (delay_TXUSERCLKIN1), + .TXUSERCLKIN2 (delay_TXUSERCLKIN2), + .TXUSERCLKIN3 (delay_TXUSERCLKIN3), + .GSR(GSR) + ); + + specify + ( DCLK => DRDY) = (100, 100); + ( DCLK => DRPDO[0]) = (100, 100); + ( DCLK => DRPDO[10]) = (100, 100); + ( DCLK => DRPDO[11]) = (100, 100); + ( DCLK => DRPDO[12]) = (100, 100); + ( DCLK => DRPDO[13]) = (100, 100); + ( DCLK => DRPDO[14]) = (100, 100); + ( DCLK => DRPDO[15]) = (100, 100); + ( DCLK => DRPDO[1]) = (100, 100); + ( DCLK => DRPDO[2]) = (100, 100); + ( DCLK => DRPDO[3]) = (100, 100); + ( DCLK => DRPDO[4]) = (100, 100); + ( DCLK => DRPDO[5]) = (100, 100); + ( DCLK => DRPDO[6]) = (100, 100); + ( DCLK => DRPDO[7]) = (100, 100); + ( DCLK => DRPDO[8]) = (100, 100); + ( DCLK => DRPDO[9]) = (100, 100); + ( DCLK => GTHINITDONE) = (100, 100); + ( DCLK => MGMTPCSRDACK) = (100, 100); + ( DCLK => MGMTPCSRDDATA[0]) = (100, 100); + ( DCLK => MGMTPCSRDDATA[10]) = (100, 100); + ( DCLK => MGMTPCSRDDATA[11]) = (100, 100); + ( DCLK => MGMTPCSRDDATA[12]) = (100, 100); + ( DCLK => MGMTPCSRDDATA[13]) = (100, 100); + ( DCLK => MGMTPCSRDDATA[14]) = (100, 100); + ( DCLK => MGMTPCSRDDATA[15]) = (100, 100); + ( DCLK => MGMTPCSRDDATA[1]) = (100, 100); + ( DCLK => MGMTPCSRDDATA[2]) = (100, 100); + ( DCLK => MGMTPCSRDDATA[3]) = (100, 100); + ( DCLK => MGMTPCSRDDATA[4]) = (100, 100); + ( DCLK => MGMTPCSRDDATA[5]) = (100, 100); + ( DCLK => MGMTPCSRDDATA[6]) = (100, 100); + ( DCLK => MGMTPCSRDDATA[7]) = (100, 100); + ( DCLK => MGMTPCSRDDATA[8]) = (100, 100); + ( DCLK => MGMTPCSRDDATA[9]) = (100, 100); + ( REFCLK => TSTREFCLKFAB) = (100, 100); + ( REFCLK => TSTREFCLKOUT) = (100, 100); + ( RXUSERCLKIN0 => RXCODEERR0[0]) = (100, 100); + ( RXUSERCLKIN0 => RXCODEERR0[1]) = (100, 100); + ( RXUSERCLKIN0 => RXCODEERR0[2]) = (100, 100); + ( RXUSERCLKIN0 => RXCODEERR0[3]) = (100, 100); + ( RXUSERCLKIN0 => RXCODEERR0[4]) = (100, 100); + ( RXUSERCLKIN0 => RXCODEERR0[5]) = (100, 100); + ( RXUSERCLKIN0 => RXCODEERR0[6]) = (100, 100); + ( RXUSERCLKIN0 => RXCODEERR0[7]) = (100, 100); + ( RXUSERCLKIN0 => RXCTRL0[0]) = (100, 100); + ( RXUSERCLKIN0 => RXCTRL0[1]) = (100, 100); + ( RXUSERCLKIN0 => RXCTRL0[2]) = (100, 100); + ( RXUSERCLKIN0 => RXCTRL0[3]) = (100, 100); + ( RXUSERCLKIN0 => RXCTRL0[4]) = (100, 100); + ( RXUSERCLKIN0 => RXCTRL0[5]) = (100, 100); + ( RXUSERCLKIN0 => RXCTRL0[6]) = (100, 100); + ( RXUSERCLKIN0 => RXCTRL0[7]) = (100, 100); + ( RXUSERCLKIN0 => RXDATA0[0]) = (100, 100); + ( RXUSERCLKIN0 => RXDATA0[10]) = (100, 100); + ( RXUSERCLKIN0 => RXDATA0[11]) = (100, 100); + ( RXUSERCLKIN0 => RXDATA0[12]) = (100, 100); + ( RXUSERCLKIN0 => RXDATA0[13]) = (100, 100); + ( RXUSERCLKIN0 => RXDATA0[14]) = (100, 100); + ( RXUSERCLKIN0 => RXDATA0[15]) = (100, 100); + ( RXUSERCLKIN0 => RXDATA0[16]) = (100, 100); + ( RXUSERCLKIN0 => RXDATA0[17]) = (100, 100); + ( RXUSERCLKIN0 => RXDATA0[18]) = (100, 100); + ( RXUSERCLKIN0 => RXDATA0[19]) = (100, 100); + ( RXUSERCLKIN0 => RXDATA0[1]) = (100, 100); + ( RXUSERCLKIN0 => RXDATA0[20]) = (100, 100); + ( RXUSERCLKIN0 => RXDATA0[21]) = (100, 100); + ( RXUSERCLKIN0 => RXDATA0[22]) = (100, 100); + ( RXUSERCLKIN0 => RXDATA0[23]) = (100, 100); + ( RXUSERCLKIN0 => RXDATA0[24]) = (100, 100); + ( RXUSERCLKIN0 => RXDATA0[25]) = (100, 100); + ( RXUSERCLKIN0 => RXDATA0[26]) = (100, 100); + ( RXUSERCLKIN0 => RXDATA0[27]) = (100, 100); + ( RXUSERCLKIN0 => RXDATA0[28]) = (100, 100); + ( RXUSERCLKIN0 => RXDATA0[29]) = (100, 100); + ( RXUSERCLKIN0 => RXDATA0[2]) = (100, 100); + ( RXUSERCLKIN0 => RXDATA0[30]) = (100, 100); + ( RXUSERCLKIN0 => RXDATA0[31]) = (100, 100); + ( RXUSERCLKIN0 => RXDATA0[32]) = (100, 100); + ( RXUSERCLKIN0 => RXDATA0[33]) = (100, 100); + ( RXUSERCLKIN0 => RXDATA0[34]) = (100, 100); + ( RXUSERCLKIN0 => RXDATA0[35]) = (100, 100); + ( RXUSERCLKIN0 => RXDATA0[36]) = (100, 100); + ( RXUSERCLKIN0 => RXDATA0[37]) = (100, 100); + ( RXUSERCLKIN0 => RXDATA0[38]) = (100, 100); + ( RXUSERCLKIN0 => RXDATA0[39]) = (100, 100); + ( RXUSERCLKIN0 => RXDATA0[3]) = (100, 100); + ( RXUSERCLKIN0 => RXDATA0[40]) = (100, 100); + ( RXUSERCLKIN0 => RXDATA0[41]) = (100, 100); + ( RXUSERCLKIN0 => RXDATA0[42]) = (100, 100); + ( RXUSERCLKIN0 => RXDATA0[43]) = (100, 100); + ( RXUSERCLKIN0 => RXDATA0[44]) = (100, 100); + ( RXUSERCLKIN0 => RXDATA0[45]) = (100, 100); + ( RXUSERCLKIN0 => RXDATA0[46]) = (100, 100); + ( RXUSERCLKIN0 => RXDATA0[47]) = (100, 100); + ( RXUSERCLKIN0 => RXDATA0[48]) = (100, 100); + ( RXUSERCLKIN0 => RXDATA0[49]) = (100, 100); + ( RXUSERCLKIN0 => RXDATA0[4]) = (100, 100); + ( RXUSERCLKIN0 => RXDATA0[50]) = (100, 100); + ( RXUSERCLKIN0 => RXDATA0[51]) = (100, 100); + ( RXUSERCLKIN0 => RXDATA0[52]) = (100, 100); + ( RXUSERCLKIN0 => RXDATA0[53]) = (100, 100); + ( RXUSERCLKIN0 => RXDATA0[54]) = (100, 100); + ( RXUSERCLKIN0 => RXDATA0[55]) = (100, 100); + ( RXUSERCLKIN0 => RXDATA0[56]) = (100, 100); + ( RXUSERCLKIN0 => RXDATA0[57]) = (100, 100); + ( RXUSERCLKIN0 => RXDATA0[58]) = (100, 100); + ( RXUSERCLKIN0 => RXDATA0[59]) = (100, 100); + ( RXUSERCLKIN0 => RXDATA0[5]) = (100, 100); + ( RXUSERCLKIN0 => RXDATA0[60]) = (100, 100); + ( RXUSERCLKIN0 => RXDATA0[61]) = (100, 100); + ( RXUSERCLKIN0 => RXDATA0[62]) = (100, 100); + ( RXUSERCLKIN0 => RXDATA0[63]) = (100, 100); + ( RXUSERCLKIN0 => RXDATA0[6]) = (100, 100); + ( RXUSERCLKIN0 => RXDATA0[7]) = (100, 100); + ( RXUSERCLKIN0 => RXDATA0[8]) = (100, 100); + ( RXUSERCLKIN0 => RXDATA0[9]) = (100, 100); + ( RXUSERCLKIN0 => RXDISPERR0[0]) = (100, 100); + ( RXUSERCLKIN0 => RXDISPERR0[1]) = (100, 100); + ( RXUSERCLKIN0 => RXDISPERR0[2]) = (100, 100); + ( RXUSERCLKIN0 => RXDISPERR0[3]) = (100, 100); + ( RXUSERCLKIN0 => RXDISPERR0[4]) = (100, 100); + ( RXUSERCLKIN0 => RXDISPERR0[5]) = (100, 100); + ( RXUSERCLKIN0 => RXDISPERR0[6]) = (100, 100); + ( RXUSERCLKIN0 => RXDISPERR0[7]) = (100, 100); + ( RXUSERCLKIN0 => RXVALID0[0]) = (100, 100); + ( RXUSERCLKIN0 => RXVALID0[1]) = (100, 100); + ( RXUSERCLKIN0 => RXVALID0[2]) = (100, 100); + ( RXUSERCLKIN0 => RXVALID0[3]) = (100, 100); + ( RXUSERCLKIN0 => RXVALID0[4]) = (100, 100); + ( RXUSERCLKIN0 => RXVALID0[5]) = (100, 100); + ( RXUSERCLKIN0 => RXVALID0[6]) = (100, 100); + ( RXUSERCLKIN0 => RXVALID0[7]) = (100, 100); + ( RXUSERCLKIN1 => RXCODEERR1[0]) = (100, 100); + ( RXUSERCLKIN1 => RXCODEERR1[1]) = (100, 100); + ( RXUSERCLKIN1 => RXCODEERR1[2]) = (100, 100); + ( RXUSERCLKIN1 => RXCODEERR1[3]) = (100, 100); + ( RXUSERCLKIN1 => RXCODEERR1[4]) = (100, 100); + ( RXUSERCLKIN1 => RXCODEERR1[5]) = (100, 100); + ( RXUSERCLKIN1 => RXCODEERR1[6]) = (100, 100); + ( RXUSERCLKIN1 => RXCODEERR1[7]) = (100, 100); + ( RXUSERCLKIN1 => RXCTRL1[0]) = (100, 100); + ( RXUSERCLKIN1 => RXCTRL1[1]) = (100, 100); + ( RXUSERCLKIN1 => RXCTRL1[2]) = (100, 100); + ( RXUSERCLKIN1 => RXCTRL1[3]) = (100, 100); + ( RXUSERCLKIN1 => RXCTRL1[4]) = (100, 100); + ( RXUSERCLKIN1 => RXCTRL1[5]) = (100, 100); + ( RXUSERCLKIN1 => RXCTRL1[6]) = (100, 100); + ( RXUSERCLKIN1 => RXCTRL1[7]) = (100, 100); + ( RXUSERCLKIN1 => RXDATA1[0]) = (100, 100); + ( RXUSERCLKIN1 => RXDATA1[10]) = (100, 100); + ( RXUSERCLKIN1 => RXDATA1[11]) = (100, 100); + ( RXUSERCLKIN1 => RXDATA1[12]) = (100, 100); + ( RXUSERCLKIN1 => RXDATA1[13]) = (100, 100); + ( RXUSERCLKIN1 => RXDATA1[14]) = (100, 100); + ( RXUSERCLKIN1 => RXDATA1[15]) = (100, 100); + ( RXUSERCLKIN1 => RXDATA1[16]) = (100, 100); + ( RXUSERCLKIN1 => RXDATA1[17]) = (100, 100); + ( RXUSERCLKIN1 => RXDATA1[18]) = (100, 100); + ( RXUSERCLKIN1 => RXDATA1[19]) = (100, 100); + ( RXUSERCLKIN1 => RXDATA1[1]) = (100, 100); + ( RXUSERCLKIN1 => RXDATA1[20]) = (100, 100); + ( RXUSERCLKIN1 => RXDATA1[21]) = (100, 100); + ( RXUSERCLKIN1 => RXDATA1[22]) = (100, 100); + ( RXUSERCLKIN1 => RXDATA1[23]) = (100, 100); + ( RXUSERCLKIN1 => RXDATA1[24]) = (100, 100); + ( RXUSERCLKIN1 => RXDATA1[25]) = (100, 100); + ( RXUSERCLKIN1 => RXDATA1[26]) = (100, 100); + ( RXUSERCLKIN1 => RXDATA1[27]) = (100, 100); + ( RXUSERCLKIN1 => RXDATA1[28]) = (100, 100); + ( RXUSERCLKIN1 => RXDATA1[29]) = (100, 100); + ( RXUSERCLKIN1 => RXDATA1[2]) = (100, 100); + ( RXUSERCLKIN1 => RXDATA1[30]) = (100, 100); + ( RXUSERCLKIN1 => RXDATA1[31]) = (100, 100); + ( RXUSERCLKIN1 => RXDATA1[32]) = (100, 100); + ( RXUSERCLKIN1 => RXDATA1[33]) = (100, 100); + ( RXUSERCLKIN1 => RXDATA1[34]) = (100, 100); + ( RXUSERCLKIN1 => RXDATA1[35]) = (100, 100); + ( RXUSERCLKIN1 => RXDATA1[36]) = (100, 100); + ( RXUSERCLKIN1 => RXDATA1[37]) = (100, 100); + ( RXUSERCLKIN1 => RXDATA1[38]) = (100, 100); + ( RXUSERCLKIN1 => RXDATA1[39]) = (100, 100); + ( RXUSERCLKIN1 => RXDATA1[3]) = (100, 100); + ( RXUSERCLKIN1 => RXDATA1[40]) = (100, 100); + ( RXUSERCLKIN1 => RXDATA1[41]) = (100, 100); + ( RXUSERCLKIN1 => RXDATA1[42]) = (100, 100); + ( RXUSERCLKIN1 => RXDATA1[43]) = (100, 100); + ( RXUSERCLKIN1 => RXDATA1[44]) = (100, 100); + ( RXUSERCLKIN1 => RXDATA1[45]) = (100, 100); + ( RXUSERCLKIN1 => RXDATA1[46]) = (100, 100); + ( RXUSERCLKIN1 => RXDATA1[47]) = (100, 100); + ( RXUSERCLKIN1 => RXDATA1[48]) = (100, 100); + ( RXUSERCLKIN1 => RXDATA1[49]) = (100, 100); + ( RXUSERCLKIN1 => RXDATA1[4]) = (100, 100); + ( RXUSERCLKIN1 => RXDATA1[50]) = (100, 100); + ( RXUSERCLKIN1 => RXDATA1[51]) = (100, 100); + ( RXUSERCLKIN1 => RXDATA1[52]) = (100, 100); + ( RXUSERCLKIN1 => RXDATA1[53]) = (100, 100); + ( RXUSERCLKIN1 => RXDATA1[54]) = (100, 100); + ( RXUSERCLKIN1 => RXDATA1[55]) = (100, 100); + ( RXUSERCLKIN1 => RXDATA1[56]) = (100, 100); + ( RXUSERCLKIN1 => RXDATA1[57]) = (100, 100); + ( RXUSERCLKIN1 => RXDATA1[58]) = (100, 100); + ( RXUSERCLKIN1 => RXDATA1[59]) = (100, 100); + ( RXUSERCLKIN1 => RXDATA1[5]) = (100, 100); + ( RXUSERCLKIN1 => RXDATA1[60]) = (100, 100); + ( RXUSERCLKIN1 => RXDATA1[61]) = (100, 100); + ( RXUSERCLKIN1 => RXDATA1[62]) = (100, 100); + ( RXUSERCLKIN1 => RXDATA1[63]) = (100, 100); + ( RXUSERCLKIN1 => RXDATA1[6]) = (100, 100); + ( RXUSERCLKIN1 => RXDATA1[7]) = (100, 100); + ( RXUSERCLKIN1 => RXDATA1[8]) = (100, 100); + ( RXUSERCLKIN1 => RXDATA1[9]) = (100, 100); + ( RXUSERCLKIN1 => RXDISPERR1[0]) = (100, 100); + ( RXUSERCLKIN1 => RXDISPERR1[1]) = (100, 100); + ( RXUSERCLKIN1 => RXDISPERR1[2]) = (100, 100); + ( RXUSERCLKIN1 => RXDISPERR1[3]) = (100, 100); + ( RXUSERCLKIN1 => RXDISPERR1[4]) = (100, 100); + ( RXUSERCLKIN1 => RXDISPERR1[5]) = (100, 100); + ( RXUSERCLKIN1 => RXDISPERR1[6]) = (100, 100); + ( RXUSERCLKIN1 => RXDISPERR1[7]) = (100, 100); + ( RXUSERCLKIN1 => RXVALID1[0]) = (100, 100); + ( RXUSERCLKIN1 => RXVALID1[1]) = (100, 100); + ( RXUSERCLKIN1 => RXVALID1[2]) = (100, 100); + ( RXUSERCLKIN1 => RXVALID1[3]) = (100, 100); + ( RXUSERCLKIN1 => RXVALID1[4]) = (100, 100); + ( RXUSERCLKIN1 => RXVALID1[5]) = (100, 100); + ( RXUSERCLKIN1 => RXVALID1[6]) = (100, 100); + ( RXUSERCLKIN1 => RXVALID1[7]) = (100, 100); + ( RXUSERCLKIN2 => RXCODEERR2[0]) = (100, 100); + ( RXUSERCLKIN2 => RXCODEERR2[1]) = (100, 100); + ( RXUSERCLKIN2 => RXCODEERR2[2]) = (100, 100); + ( RXUSERCLKIN2 => RXCODEERR2[3]) = (100, 100); + ( RXUSERCLKIN2 => RXCODEERR2[4]) = (100, 100); + ( RXUSERCLKIN2 => RXCODEERR2[5]) = (100, 100); + ( RXUSERCLKIN2 => RXCODEERR2[6]) = (100, 100); + ( RXUSERCLKIN2 => RXCODEERR2[7]) = (100, 100); + ( RXUSERCLKIN2 => RXCTRL2[0]) = (100, 100); + ( RXUSERCLKIN2 => RXCTRL2[1]) = (100, 100); + ( RXUSERCLKIN2 => RXCTRL2[2]) = (100, 100); + ( RXUSERCLKIN2 => RXCTRL2[3]) = (100, 100); + ( RXUSERCLKIN2 => RXCTRL2[4]) = (100, 100); + ( RXUSERCLKIN2 => RXCTRL2[5]) = (100, 100); + ( RXUSERCLKIN2 => RXCTRL2[6]) = (100, 100); + ( RXUSERCLKIN2 => RXCTRL2[7]) = (100, 100); + ( RXUSERCLKIN2 => RXDATA2[0]) = (100, 100); + ( RXUSERCLKIN2 => RXDATA2[10]) = (100, 100); + ( RXUSERCLKIN2 => RXDATA2[11]) = (100, 100); + ( RXUSERCLKIN2 => RXDATA2[12]) = (100, 100); + ( RXUSERCLKIN2 => RXDATA2[13]) = (100, 100); + ( RXUSERCLKIN2 => RXDATA2[14]) = (100, 100); + ( RXUSERCLKIN2 => RXDATA2[15]) = (100, 100); + ( RXUSERCLKIN2 => RXDATA2[16]) = (100, 100); + ( RXUSERCLKIN2 => RXDATA2[17]) = (100, 100); + ( RXUSERCLKIN2 => RXDATA2[18]) = (100, 100); + ( RXUSERCLKIN2 => RXDATA2[19]) = (100, 100); + ( RXUSERCLKIN2 => RXDATA2[1]) = (100, 100); + ( RXUSERCLKIN2 => RXDATA2[20]) = (100, 100); + ( RXUSERCLKIN2 => RXDATA2[21]) = (100, 100); + ( RXUSERCLKIN2 => RXDATA2[22]) = (100, 100); + ( RXUSERCLKIN2 => RXDATA2[23]) = (100, 100); + ( RXUSERCLKIN2 => RXDATA2[24]) = (100, 100); + ( RXUSERCLKIN2 => RXDATA2[25]) = (100, 100); + ( RXUSERCLKIN2 => RXDATA2[26]) = (100, 100); + ( RXUSERCLKIN2 => RXDATA2[27]) = (100, 100); + ( RXUSERCLKIN2 => RXDATA2[28]) = (100, 100); + ( RXUSERCLKIN2 => RXDATA2[29]) = (100, 100); + ( RXUSERCLKIN2 => RXDATA2[2]) = (100, 100); + ( RXUSERCLKIN2 => RXDATA2[30]) = (100, 100); + ( RXUSERCLKIN2 => RXDATA2[31]) = (100, 100); + ( RXUSERCLKIN2 => RXDATA2[32]) = (100, 100); + ( RXUSERCLKIN2 => RXDATA2[33]) = (100, 100); + ( RXUSERCLKIN2 => RXDATA2[34]) = (100, 100); + ( RXUSERCLKIN2 => RXDATA2[35]) = (100, 100); + ( RXUSERCLKIN2 => RXDATA2[36]) = (100, 100); + ( RXUSERCLKIN2 => RXDATA2[37]) = (100, 100); + ( RXUSERCLKIN2 => RXDATA2[38]) = (100, 100); + ( RXUSERCLKIN2 => RXDATA2[39]) = (100, 100); + ( RXUSERCLKIN2 => RXDATA2[3]) = (100, 100); + ( RXUSERCLKIN2 => RXDATA2[40]) = (100, 100); + ( RXUSERCLKIN2 => RXDATA2[41]) = (100, 100); + ( RXUSERCLKIN2 => RXDATA2[42]) = (100, 100); + ( RXUSERCLKIN2 => RXDATA2[43]) = (100, 100); + ( RXUSERCLKIN2 => RXDATA2[44]) = (100, 100); + ( RXUSERCLKIN2 => RXDATA2[45]) = (100, 100); + ( RXUSERCLKIN2 => RXDATA2[46]) = (100, 100); + ( RXUSERCLKIN2 => RXDATA2[47]) = (100, 100); + ( RXUSERCLKIN2 => RXDATA2[48]) = (100, 100); + ( RXUSERCLKIN2 => RXDATA2[49]) = (100, 100); + ( RXUSERCLKIN2 => RXDATA2[4]) = (100, 100); + ( RXUSERCLKIN2 => RXDATA2[50]) = (100, 100); + ( RXUSERCLKIN2 => RXDATA2[51]) = (100, 100); + ( RXUSERCLKIN2 => RXDATA2[52]) = (100, 100); + ( RXUSERCLKIN2 => RXDATA2[53]) = (100, 100); + ( RXUSERCLKIN2 => RXDATA2[54]) = (100, 100); + ( RXUSERCLKIN2 => RXDATA2[55]) = (100, 100); + ( RXUSERCLKIN2 => RXDATA2[56]) = (100, 100); + ( RXUSERCLKIN2 => RXDATA2[57]) = (100, 100); + ( RXUSERCLKIN2 => RXDATA2[58]) = (100, 100); + ( RXUSERCLKIN2 => RXDATA2[59]) = (100, 100); + ( RXUSERCLKIN2 => RXDATA2[5]) = (100, 100); + ( RXUSERCLKIN2 => RXDATA2[60]) = (100, 100); + ( RXUSERCLKIN2 => RXDATA2[61]) = (100, 100); + ( RXUSERCLKIN2 => RXDATA2[62]) = (100, 100); + ( RXUSERCLKIN2 => RXDATA2[63]) = (100, 100); + ( RXUSERCLKIN2 => RXDATA2[6]) = (100, 100); + ( RXUSERCLKIN2 => RXDATA2[7]) = (100, 100); + ( RXUSERCLKIN2 => RXDATA2[8]) = (100, 100); + ( RXUSERCLKIN2 => RXDATA2[9]) = (100, 100); + ( RXUSERCLKIN2 => RXDISPERR2[0]) = (100, 100); + ( RXUSERCLKIN2 => RXDISPERR2[1]) = (100, 100); + ( RXUSERCLKIN2 => RXDISPERR2[2]) = (100, 100); + ( RXUSERCLKIN2 => RXDISPERR2[3]) = (100, 100); + ( RXUSERCLKIN2 => RXDISPERR2[4]) = (100, 100); + ( RXUSERCLKIN2 => RXDISPERR2[5]) = (100, 100); + ( RXUSERCLKIN2 => RXDISPERR2[6]) = (100, 100); + ( RXUSERCLKIN2 => RXDISPERR2[7]) = (100, 100); + ( RXUSERCLKIN2 => RXVALID2[0]) = (100, 100); + ( RXUSERCLKIN2 => RXVALID2[1]) = (100, 100); + ( RXUSERCLKIN2 => RXVALID2[2]) = (100, 100); + ( RXUSERCLKIN2 => RXVALID2[3]) = (100, 100); + ( RXUSERCLKIN2 => RXVALID2[4]) = (100, 100); + ( RXUSERCLKIN2 => RXVALID2[5]) = (100, 100); + ( RXUSERCLKIN2 => RXVALID2[6]) = (100, 100); + ( RXUSERCLKIN2 => RXVALID2[7]) = (100, 100); + ( RXUSERCLKIN3 => RXCODEERR3[0]) = (100, 100); + ( RXUSERCLKIN3 => RXCODEERR3[1]) = (100, 100); + ( RXUSERCLKIN3 => RXCODEERR3[2]) = (100, 100); + ( RXUSERCLKIN3 => RXCODEERR3[3]) = (100, 100); + ( RXUSERCLKIN3 => RXCODEERR3[4]) = (100, 100); + ( RXUSERCLKIN3 => RXCODEERR3[5]) = (100, 100); + ( RXUSERCLKIN3 => RXCODEERR3[6]) = (100, 100); + ( RXUSERCLKIN3 => RXCODEERR3[7]) = (100, 100); + ( RXUSERCLKIN3 => RXCTRL3[0]) = (100, 100); + ( RXUSERCLKIN3 => RXCTRL3[1]) = (100, 100); + ( RXUSERCLKIN3 => RXCTRL3[2]) = (100, 100); + ( RXUSERCLKIN3 => RXCTRL3[3]) = (100, 100); + ( RXUSERCLKIN3 => RXCTRL3[4]) = (100, 100); + ( RXUSERCLKIN3 => RXCTRL3[5]) = (100, 100); + ( RXUSERCLKIN3 => RXCTRL3[6]) = (100, 100); + ( RXUSERCLKIN3 => RXCTRL3[7]) = (100, 100); + ( RXUSERCLKIN3 => RXDATA3[0]) = (100, 100); + ( RXUSERCLKIN3 => RXDATA3[10]) = (100, 100); + ( RXUSERCLKIN3 => RXDATA3[11]) = (100, 100); + ( RXUSERCLKIN3 => RXDATA3[12]) = (100, 100); + ( RXUSERCLKIN3 => RXDATA3[13]) = (100, 100); + ( RXUSERCLKIN3 => RXDATA3[14]) = (100, 100); + ( RXUSERCLKIN3 => RXDATA3[15]) = (100, 100); + ( RXUSERCLKIN3 => RXDATA3[16]) = (100, 100); + ( RXUSERCLKIN3 => RXDATA3[17]) = (100, 100); + ( RXUSERCLKIN3 => RXDATA3[18]) = (100, 100); + ( RXUSERCLKIN3 => RXDATA3[19]) = (100, 100); + ( RXUSERCLKIN3 => RXDATA3[1]) = (100, 100); + ( RXUSERCLKIN3 => RXDATA3[20]) = (100, 100); + ( RXUSERCLKIN3 => RXDATA3[21]) = (100, 100); + ( RXUSERCLKIN3 => RXDATA3[22]) = (100, 100); + ( RXUSERCLKIN3 => RXDATA3[23]) = (100, 100); + ( RXUSERCLKIN3 => RXDATA3[24]) = (100, 100); + ( RXUSERCLKIN3 => RXDATA3[25]) = (100, 100); + ( RXUSERCLKIN3 => RXDATA3[26]) = (100, 100); + ( RXUSERCLKIN3 => RXDATA3[27]) = (100, 100); + ( RXUSERCLKIN3 => RXDATA3[28]) = (100, 100); + ( RXUSERCLKIN3 => RXDATA3[29]) = (100, 100); + ( RXUSERCLKIN3 => RXDATA3[2]) = (100, 100); + ( RXUSERCLKIN3 => RXDATA3[30]) = (100, 100); + ( RXUSERCLKIN3 => RXDATA3[31]) = (100, 100); + ( RXUSERCLKIN3 => RXDATA3[32]) = (100, 100); + ( RXUSERCLKIN3 => RXDATA3[33]) = (100, 100); + ( RXUSERCLKIN3 => RXDATA3[34]) = (100, 100); + ( RXUSERCLKIN3 => RXDATA3[35]) = (100, 100); + ( RXUSERCLKIN3 => RXDATA3[36]) = (100, 100); + ( RXUSERCLKIN3 => RXDATA3[37]) = (100, 100); + ( RXUSERCLKIN3 => RXDATA3[38]) = (100, 100); + ( RXUSERCLKIN3 => RXDATA3[39]) = (100, 100); + ( RXUSERCLKIN3 => RXDATA3[3]) = (100, 100); + ( RXUSERCLKIN3 => RXDATA3[40]) = (100, 100); + ( RXUSERCLKIN3 => RXDATA3[41]) = (100, 100); + ( RXUSERCLKIN3 => RXDATA3[42]) = (100, 100); + ( RXUSERCLKIN3 => RXDATA3[43]) = (100, 100); + ( RXUSERCLKIN3 => RXDATA3[44]) = (100, 100); + ( RXUSERCLKIN3 => RXDATA3[45]) = (100, 100); + ( RXUSERCLKIN3 => RXDATA3[46]) = (100, 100); + ( RXUSERCLKIN3 => RXDATA3[47]) = (100, 100); + ( RXUSERCLKIN3 => RXDATA3[48]) = (100, 100); + ( RXUSERCLKIN3 => RXDATA3[49]) = (100, 100); + ( RXUSERCLKIN3 => RXDATA3[4]) = (100, 100); + ( RXUSERCLKIN3 => RXDATA3[50]) = (100, 100); + ( RXUSERCLKIN3 => RXDATA3[51]) = (100, 100); + ( RXUSERCLKIN3 => RXDATA3[52]) = (100, 100); + ( RXUSERCLKIN3 => RXDATA3[53]) = (100, 100); + ( RXUSERCLKIN3 => RXDATA3[54]) = (100, 100); + ( RXUSERCLKIN3 => RXDATA3[55]) = (100, 100); + ( RXUSERCLKIN3 => RXDATA3[56]) = (100, 100); + ( RXUSERCLKIN3 => RXDATA3[57]) = (100, 100); + ( RXUSERCLKIN3 => RXDATA3[58]) = (100, 100); + ( RXUSERCLKIN3 => RXDATA3[59]) = (100, 100); + ( RXUSERCLKIN3 => RXDATA3[5]) = (100, 100); + ( RXUSERCLKIN3 => RXDATA3[60]) = (100, 100); + ( RXUSERCLKIN3 => RXDATA3[61]) = (100, 100); + ( RXUSERCLKIN3 => RXDATA3[62]) = (100, 100); + ( RXUSERCLKIN3 => RXDATA3[63]) = (100, 100); + ( RXUSERCLKIN3 => RXDATA3[6]) = (100, 100); + ( RXUSERCLKIN3 => RXDATA3[7]) = (100, 100); + ( RXUSERCLKIN3 => RXDATA3[8]) = (100, 100); + ( RXUSERCLKIN3 => RXDATA3[9]) = (100, 100); + ( RXUSERCLKIN3 => RXDISPERR3[0]) = (100, 100); + ( RXUSERCLKIN3 => RXDISPERR3[1]) = (100, 100); + ( RXUSERCLKIN3 => RXDISPERR3[2]) = (100, 100); + ( RXUSERCLKIN3 => RXDISPERR3[3]) = (100, 100); + ( RXUSERCLKIN3 => RXDISPERR3[4]) = (100, 100); + ( RXUSERCLKIN3 => RXDISPERR3[5]) = (100, 100); + ( RXUSERCLKIN3 => RXDISPERR3[6]) = (100, 100); + ( RXUSERCLKIN3 => RXDISPERR3[7]) = (100, 100); + ( RXUSERCLKIN3 => RXVALID3[0]) = (100, 100); + ( RXUSERCLKIN3 => RXVALID3[1]) = (100, 100); + ( RXUSERCLKIN3 => RXVALID3[2]) = (100, 100); + ( RXUSERCLKIN3 => RXVALID3[3]) = (100, 100); + ( RXUSERCLKIN3 => RXVALID3[4]) = (100, 100); + ( RXUSERCLKIN3 => RXVALID3[5]) = (100, 100); + ( RXUSERCLKIN3 => RXVALID3[6]) = (100, 100); + ( RXUSERCLKIN3 => RXVALID3[7]) = (100, 100); + ( TXUSERCLKIN0 => RXCTRLACK0) = (100, 100); + ( TXUSERCLKIN0 => TXCTRLACK0) = (100, 100); + ( TXUSERCLKIN1 => RXCTRLACK1) = (100, 100); + ( TXUSERCLKIN1 => TXCTRLACK1) = (100, 100); + ( TXUSERCLKIN2 => RXCTRLACK2) = (100, 100); + ( TXUSERCLKIN2 => TXCTRLACK2) = (100, 100); + ( TXUSERCLKIN3 => RXCTRLACK3) = (100, 100); + ( TXUSERCLKIN3 => TXCTRLACK3) = (100, 100); + + specparam PATHPULSE$ = 0; + endspecify +endmodule diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/GTPA1_DUAL.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/GTPA1_DUAL.v new file mode 100644 index 0000000..bedbf18 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/GTPA1_DUAL.v @@ -0,0 +1,4037 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/stan/GTPA1_DUAL.v,v 1.16.50.1 2010/06/07 18:24:46 robh Exp $ +/////////////////////////////////////////////////////// +// Copyright (c) 2009 Xilinx Inc. +// All Right Reserved. +/////////////////////////////////////////////////////// +// +// ____ ___ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Multi-Gigabit Tranceiver Port Secure IP +// /__/ /\ Filename : GTPA1_DUAL.v +// \ \ / \ +// \__\/\__ \ +// +// Revision: Date: Comment +// 1.0: 08/15/08: Initial version. +// 1.1 01/22/09: updates for VCS, NCSIM +// 1.2: 01/29/09: CR503397 remove NCELAB work arounds +// 1.3: 03/12/09: CR511750 - upper case attribute defaults +// 1.4: 04/09/09: CR516873 - yml, rtl update +// 1.5: 09/02/09: CR532550 - yml update +// 1.6: 10/01/09: CR533370 - yml update +// 1.7: 06/07/10: CR563488 - yml update + +// End Revision +/////////////////////////////////////////////////////// + +`timescale 1 ps / 1 ps + +module GTPA1_DUAL ( + DRDY, + DRPDO, + GTPCLKFBEAST, + GTPCLKFBWEST, + GTPCLKOUT0, + GTPCLKOUT1, + PHYSTATUS0, + PHYSTATUS1, + PLLLKDET0, + PLLLKDET1, + RCALOUTEAST, + RCALOUTWEST, + REFCLKOUT0, + REFCLKOUT1, + REFCLKPLL0, + REFCLKPLL1, + RESETDONE0, + RESETDONE1, + RXBUFSTATUS0, + RXBUFSTATUS1, + RXBYTEISALIGNED0, + RXBYTEISALIGNED1, + RXBYTEREALIGN0, + RXBYTEREALIGN1, + RXCHANBONDSEQ0, + RXCHANBONDSEQ1, + RXCHANISALIGNED0, + RXCHANISALIGNED1, + RXCHANREALIGN0, + RXCHANREALIGN1, + RXCHARISCOMMA0, + RXCHARISCOMMA1, + RXCHARISK0, + RXCHARISK1, + RXCHBONDO, + RXCLKCORCNT0, + RXCLKCORCNT1, + RXCOMMADET0, + RXCOMMADET1, + RXDATA0, + RXDATA1, + RXDISPERR0, + RXDISPERR1, + RXELECIDLE0, + RXELECIDLE1, + RXLOSSOFSYNC0, + RXLOSSOFSYNC1, + RXNOTINTABLE0, + RXNOTINTABLE1, + RXPRBSERR0, + RXPRBSERR1, + RXRECCLK0, + RXRECCLK1, + RXRUNDISP0, + RXRUNDISP1, + RXSTATUS0, + RXSTATUS1, + RXVALID0, + RXVALID1, + TSTOUT0, + TSTOUT1, + TXBUFSTATUS0, + TXBUFSTATUS1, + TXKERR0, + TXKERR1, + TXN0, + TXN1, + TXOUTCLK0, + TXOUTCLK1, + TXP0, + TXP1, + TXRUNDISP0, + TXRUNDISP1, + CLK00, + CLK01, + CLK10, + CLK11, + CLKINEAST0, + CLKINEAST1, + CLKINWEST0, + CLKINWEST1, + DADDR, + DCLK, + DEN, + DI, + DWE, + GATERXELECIDLE0, + GATERXELECIDLE1, + GCLK00, + GCLK01, + GCLK10, + GCLK11, + GTPCLKFBSEL0EAST, + GTPCLKFBSEL0WEST, + GTPCLKFBSEL1EAST, + GTPCLKFBSEL1WEST, + GTPRESET0, + GTPRESET1, + GTPTEST0, + GTPTEST1, + IGNORESIGDET0, + IGNORESIGDET1, + INTDATAWIDTH0, + INTDATAWIDTH1, + LOOPBACK0, + LOOPBACK1, + PLLCLK00, + PLLCLK01, + PLLCLK10, + PLLCLK11, + PLLLKDETEN0, + PLLLKDETEN1, + PLLPOWERDOWN0, + PLLPOWERDOWN1, + PRBSCNTRESET0, + PRBSCNTRESET1, + RCALINEAST, + RCALINWEST, + REFCLKPWRDNB0, + REFCLKPWRDNB1, + REFSELDYPLL0, + REFSELDYPLL1, + RXBUFRESET0, + RXBUFRESET1, + RXCDRRESET0, + RXCDRRESET1, + RXCHBONDI, + RXCHBONDMASTER0, + RXCHBONDMASTER1, + RXCHBONDSLAVE0, + RXCHBONDSLAVE1, + RXCOMMADETUSE0, + RXCOMMADETUSE1, + RXDATAWIDTH0, + RXDATAWIDTH1, + RXDEC8B10BUSE0, + RXDEC8B10BUSE1, + RXENCHANSYNC0, + RXENCHANSYNC1, + RXENMCOMMAALIGN0, + RXENMCOMMAALIGN1, + RXENPCOMMAALIGN0, + RXENPCOMMAALIGN1, + RXENPMAPHASEALIGN0, + RXENPMAPHASEALIGN1, + RXENPRBSTST0, + RXENPRBSTST1, + RXEQMIX0, + RXEQMIX1, + RXN0, + RXN1, + RXP0, + RXP1, + RXPMASETPHASE0, + RXPMASETPHASE1, + RXPOLARITY0, + RXPOLARITY1, + RXPOWERDOWN0, + RXPOWERDOWN1, + RXRESET0, + RXRESET1, + RXSLIDE0, + RXSLIDE1, + RXUSRCLK0, + RXUSRCLK1, + RXUSRCLK20, + RXUSRCLK21, + TSTCLK0, + TSTCLK1, + TSTIN0, + TSTIN1, + TXBUFDIFFCTRL0, + TXBUFDIFFCTRL1, + TXBYPASS8B10B0, + TXBYPASS8B10B1, + TXCHARDISPMODE0, + TXCHARDISPMODE1, + TXCHARDISPVAL0, + TXCHARDISPVAL1, + TXCHARISK0, + TXCHARISK1, + TXCOMSTART0, + TXCOMSTART1, + TXCOMTYPE0, + TXCOMTYPE1, + TXDATA0, + TXDATA1, + TXDATAWIDTH0, + TXDATAWIDTH1, + TXDETECTRX0, + TXDETECTRX1, + TXDIFFCTRL0, + TXDIFFCTRL1, + TXELECIDLE0, + TXELECIDLE1, + TXENC8B10BUSE0, + TXENC8B10BUSE1, + TXENPMAPHASEALIGN0, + TXENPMAPHASEALIGN1, + TXENPRBSTST0, + TXENPRBSTST1, + TXINHIBIT0, + TXINHIBIT1, + TXPDOWNASYNCH0, + TXPDOWNASYNCH1, + TXPMASETPHASE0, + TXPMASETPHASE1, + TXPOLARITY0, + TXPOLARITY1, + TXPOWERDOWN0, + TXPOWERDOWN1, + TXPRBSFORCEERR0, + TXPRBSFORCEERR1, + TXPREEMPHASIS0, + TXPREEMPHASIS1, + TXRESET0, + TXRESET1, + TXUSRCLK0, + TXUSRCLK1, + TXUSRCLK20, + TXUSRCLK21, + USRCODEERR0, + USRCODEERR1 +); + + parameter AC_CAP_DIS_0 = "TRUE"; + parameter AC_CAP_DIS_1 = "TRUE"; + parameter integer ALIGN_COMMA_WORD_0 = 1; + parameter integer ALIGN_COMMA_WORD_1 = 1; + parameter integer CB2_INH_CC_PERIOD_0 = 8; + parameter integer CB2_INH_CC_PERIOD_1 = 8; + parameter [4:0] CDR_PH_ADJ_TIME_0 = 5'b01010; + parameter [4:0] CDR_PH_ADJ_TIME_1 = 5'b01010; + parameter integer CHAN_BOND_1_MAX_SKEW_0 = 7; + parameter integer CHAN_BOND_1_MAX_SKEW_1 = 7; + parameter integer CHAN_BOND_2_MAX_SKEW_0 = 1; + parameter integer CHAN_BOND_2_MAX_SKEW_1 = 1; + parameter CHAN_BOND_KEEP_ALIGN_0 = "FALSE"; + parameter CHAN_BOND_KEEP_ALIGN_1 = "FALSE"; + parameter [9:0] CHAN_BOND_SEQ_1_1_0 = 10'b0101111100; + parameter [9:0] CHAN_BOND_SEQ_1_1_1 = 10'b0101111100; + parameter [9:0] CHAN_BOND_SEQ_1_2_0 = 10'b0001001010; + parameter [9:0] CHAN_BOND_SEQ_1_2_1 = 10'b0001001010; + parameter [9:0] CHAN_BOND_SEQ_1_3_0 = 10'b0001001010; + parameter [9:0] CHAN_BOND_SEQ_1_3_1 = 10'b0001001010; + parameter [9:0] CHAN_BOND_SEQ_1_4_0 = 10'b0110111100; + parameter [9:0] CHAN_BOND_SEQ_1_4_1 = 10'b0110111100; + parameter [3:0] CHAN_BOND_SEQ_1_ENABLE_0 = 4'b1111; + parameter [3:0] CHAN_BOND_SEQ_1_ENABLE_1 = 4'b1111; + parameter [9:0] CHAN_BOND_SEQ_2_1_0 = 10'b0110111100; + parameter [9:0] CHAN_BOND_SEQ_2_1_1 = 10'b0110111100; + parameter [9:0] CHAN_BOND_SEQ_2_2_0 = 10'b0100111100; + parameter [9:0] CHAN_BOND_SEQ_2_2_1 = 10'b0100111100; + parameter [9:0] CHAN_BOND_SEQ_2_3_0 = 10'b0100111100; + parameter [9:0] CHAN_BOND_SEQ_2_3_1 = 10'b0100111100; + parameter [9:0] CHAN_BOND_SEQ_2_4_0 = 10'b0100111100; + parameter [9:0] CHAN_BOND_SEQ_2_4_1 = 10'b0100111100; + parameter [3:0] CHAN_BOND_SEQ_2_ENABLE_0 = 4'b1111; + parameter [3:0] CHAN_BOND_SEQ_2_ENABLE_1 = 4'b1111; + parameter CHAN_BOND_SEQ_2_USE_0 = "FALSE"; + parameter CHAN_BOND_SEQ_2_USE_1 = "FALSE"; + parameter integer CHAN_BOND_SEQ_LEN_0 = 1; + parameter integer CHAN_BOND_SEQ_LEN_1 = 1; + parameter integer CLK25_DIVIDER_0 = 4; + parameter integer CLK25_DIVIDER_1 = 4; + parameter CLKINDC_B_0 = "TRUE"; + parameter CLKINDC_B_1 = "TRUE"; + parameter CLKRCV_TRST_0 = "TRUE"; + parameter CLKRCV_TRST_1 = "TRUE"; + parameter CLK_CORRECT_USE_0 = "TRUE"; + parameter CLK_CORRECT_USE_1 = "TRUE"; + parameter integer CLK_COR_ADJ_LEN_0 = 1; + parameter integer CLK_COR_ADJ_LEN_1 = 1; + parameter integer CLK_COR_DET_LEN_0 = 1; + parameter integer CLK_COR_DET_LEN_1 = 1; + parameter CLK_COR_INSERT_IDLE_FLAG_0 = "FALSE"; + parameter CLK_COR_INSERT_IDLE_FLAG_1 = "FALSE"; + parameter CLK_COR_KEEP_IDLE_0 = "FALSE"; + parameter CLK_COR_KEEP_IDLE_1 = "FALSE"; + parameter integer CLK_COR_MAX_LAT_0 = 20; + parameter integer CLK_COR_MAX_LAT_1 = 20; + parameter integer CLK_COR_MIN_LAT_0 = 18; + parameter integer CLK_COR_MIN_LAT_1 = 18; + parameter CLK_COR_PRECEDENCE_0 = "TRUE"; + parameter CLK_COR_PRECEDENCE_1 = "TRUE"; + parameter integer CLK_COR_REPEAT_WAIT_0 = 0; + parameter integer CLK_COR_REPEAT_WAIT_1 = 0; + parameter [9:0] CLK_COR_SEQ_1_1_0 = 10'b0100011100; + parameter [9:0] CLK_COR_SEQ_1_1_1 = 10'b0100011100; + parameter [9:0] CLK_COR_SEQ_1_2_0 = 10'b0000000000; + parameter [9:0] CLK_COR_SEQ_1_2_1 = 10'b0000000000; + parameter [9:0] CLK_COR_SEQ_1_3_0 = 10'b0000000000; + parameter [9:0] CLK_COR_SEQ_1_3_1 = 10'b0000000000; + parameter [9:0] CLK_COR_SEQ_1_4_0 = 10'b0000000000; + parameter [9:0] CLK_COR_SEQ_1_4_1 = 10'b0000000000; + parameter [3:0] CLK_COR_SEQ_1_ENABLE_0 = 4'b1111; + parameter [3:0] CLK_COR_SEQ_1_ENABLE_1 = 4'b1111; + parameter [9:0] CLK_COR_SEQ_2_1_0 = 10'b0000000000; + parameter [9:0] CLK_COR_SEQ_2_1_1 = 10'b0000000000; + parameter [9:0] CLK_COR_SEQ_2_2_0 = 10'b0000000000; + parameter [9:0] CLK_COR_SEQ_2_2_1 = 10'b0000000000; + parameter [9:0] CLK_COR_SEQ_2_3_0 = 10'b0000000000; + parameter [9:0] CLK_COR_SEQ_2_3_1 = 10'b0000000000; + parameter [9:0] CLK_COR_SEQ_2_4_0 = 10'b0000000000; + parameter [9:0] CLK_COR_SEQ_2_4_1 = 10'b0000000000; + parameter [3:0] CLK_COR_SEQ_2_ENABLE_0 = 4'b1111; + parameter [3:0] CLK_COR_SEQ_2_ENABLE_1 = 4'b1111; + parameter CLK_COR_SEQ_2_USE_0 = "FALSE"; + parameter CLK_COR_SEQ_2_USE_1 = "FALSE"; + parameter CLK_OUT_GTP_SEL_0 = "REFCLKPLL0"; + parameter CLK_OUT_GTP_SEL_1 = "REFCLKPLL1"; + parameter [1:0] CM_TRIM_0 = 2'b00; + parameter [1:0] CM_TRIM_1 = 2'b00; + parameter [9:0] COMMA_10B_ENABLE_0 = 10'b1111111111; + parameter [9:0] COMMA_10B_ENABLE_1 = 10'b1111111111; + parameter [3:0] COM_BURST_VAL_0 = 4'b1111; + parameter [3:0] COM_BURST_VAL_1 = 4'b1111; + parameter DEC_MCOMMA_DETECT_0 = "TRUE"; + parameter DEC_MCOMMA_DETECT_1 = "TRUE"; + parameter DEC_PCOMMA_DETECT_0 = "TRUE"; + parameter DEC_PCOMMA_DETECT_1 = "TRUE"; + parameter DEC_VALID_COMMA_ONLY_0 = "TRUE"; + parameter DEC_VALID_COMMA_ONLY_1 = "TRUE"; + parameter GTP_CFG_PWRUP_0 = "TRUE"; + parameter GTP_CFG_PWRUP_1 = "TRUE"; + parameter [9:0] MCOMMA_10B_VALUE_0 = 10'b1010000011; + parameter [9:0] MCOMMA_10B_VALUE_1 = 10'b1010000011; + parameter MCOMMA_DETECT_0 = "TRUE"; + parameter MCOMMA_DETECT_1 = "TRUE"; + parameter [2:0] OOBDETECT_THRESHOLD_0 = 3'b110; + parameter [2:0] OOBDETECT_THRESHOLD_1 = 3'b110; + parameter integer OOB_CLK_DIVIDER_0 = 4; + parameter integer OOB_CLK_DIVIDER_1 = 4; + parameter PCI_EXPRESS_MODE_0 = "FALSE"; + parameter PCI_EXPRESS_MODE_1 = "FALSE"; + parameter [9:0] PCOMMA_10B_VALUE_0 = 10'b0101111100; + parameter [9:0] PCOMMA_10B_VALUE_1 = 10'b0101111100; + parameter PCOMMA_DETECT_0 = "TRUE"; + parameter PCOMMA_DETECT_1 = "TRUE"; + parameter [2:0] PLLLKDET_CFG_0 = 3'b101; + parameter [2:0] PLLLKDET_CFG_1 = 3'b101; + parameter [23:0] PLL_COM_CFG_0 = 24'h21680A; + parameter [23:0] PLL_COM_CFG_1 = 24'h21680A; + parameter [7:0] PLL_CP_CFG_0 = 8'h00; + parameter [7:0] PLL_CP_CFG_1 = 8'h00; + parameter integer PLL_DIVSEL_FB_0 = 5; + parameter integer PLL_DIVSEL_FB_1 = 5; + parameter integer PLL_DIVSEL_REF_0 = 2; + parameter integer PLL_DIVSEL_REF_1 = 2; + parameter integer PLL_RXDIVSEL_OUT_0 = 1; + parameter integer PLL_RXDIVSEL_OUT_1 = 1; + parameter PLL_SATA_0 = "FALSE"; + parameter PLL_SATA_1 = "FALSE"; + parameter PLL_SOURCE_0 = "PLL0"; + parameter PLL_SOURCE_1 = "PLL0"; + parameter integer PLL_TXDIVSEL_OUT_0 = 1; + parameter integer PLL_TXDIVSEL_OUT_1 = 1; + parameter [26:0] PMA_CDR_SCAN_0 = 27'h6404040; + parameter [26:0] PMA_CDR_SCAN_1 = 27'h6404040; + parameter [35:0] PMA_COM_CFG_EAST = 36'h000008000; + parameter [35:0] PMA_COM_CFG_WEST = 36'h00000A000; + parameter [6:0] PMA_RXSYNC_CFG_0 = 7'h00; + parameter [6:0] PMA_RXSYNC_CFG_1 = 7'h00; + parameter [24:0] PMA_RX_CFG_0 = 25'h05CE048; + parameter [24:0] PMA_RX_CFG_1 = 25'h05CE048; + parameter [19:0] PMA_TX_CFG_0 = 20'h00082; + parameter [19:0] PMA_TX_CFG_1 = 20'h00082; + parameter RCV_TERM_GND_0 = "FALSE"; + parameter RCV_TERM_GND_1 = "FALSE"; + parameter RCV_TERM_VTTRX_0 = "TRUE"; + parameter RCV_TERM_VTTRX_1 = "TRUE"; + parameter [7:0] RXEQ_CFG_0 = 8'b01111011; + parameter [7:0] RXEQ_CFG_1 = 8'b01111011; + parameter [0:0] RXPRBSERR_LOOPBACK_0 = 1'b0; + parameter [0:0] RXPRBSERR_LOOPBACK_1 = 1'b0; + parameter RX_BUFFER_USE_0 = "TRUE"; + parameter RX_BUFFER_USE_1 = "TRUE"; + parameter RX_DECODE_SEQ_MATCH_0 = "TRUE"; + parameter RX_DECODE_SEQ_MATCH_1 = "TRUE"; + parameter RX_EN_IDLE_HOLD_CDR_0 = "FALSE"; + parameter RX_EN_IDLE_HOLD_CDR_1 = "FALSE"; + parameter RX_EN_IDLE_RESET_BUF_0 = "TRUE"; + parameter RX_EN_IDLE_RESET_BUF_1 = "TRUE"; + parameter RX_EN_IDLE_RESET_FR_0 = "TRUE"; + parameter RX_EN_IDLE_RESET_FR_1 = "TRUE"; + parameter RX_EN_IDLE_RESET_PH_0 = "TRUE"; + parameter RX_EN_IDLE_RESET_PH_1 = "TRUE"; + parameter RX_EN_MODE_RESET_BUF_0 = "TRUE"; + parameter RX_EN_MODE_RESET_BUF_1 = "TRUE"; + parameter [3:0] RX_IDLE_HI_CNT_0 = 4'b1000; + parameter [3:0] RX_IDLE_HI_CNT_1 = 4'b1000; + parameter [3:0] RX_IDLE_LO_CNT_0 = 4'b0000; + parameter [3:0] RX_IDLE_LO_CNT_1 = 4'b0000; + parameter RX_LOSS_OF_SYNC_FSM_0 = "FALSE"; + parameter RX_LOSS_OF_SYNC_FSM_1 = "FALSE"; + parameter integer RX_LOS_INVALID_INCR_0 = 1; + parameter integer RX_LOS_INVALID_INCR_1 = 1; + parameter integer RX_LOS_THRESHOLD_0 = 4; + parameter integer RX_LOS_THRESHOLD_1 = 4; + parameter RX_SLIDE_MODE_0 = "PCS"; + parameter RX_SLIDE_MODE_1 = "PCS"; + parameter RX_STATUS_FMT_0 = "PCIE"; + parameter RX_STATUS_FMT_1 = "PCIE"; + parameter RX_XCLK_SEL_0 = "RXREC"; + parameter RX_XCLK_SEL_1 = "RXREC"; + parameter [2:0] SATA_BURST_VAL_0 = 3'b100; + parameter [2:0] SATA_BURST_VAL_1 = 3'b100; + parameter [2:0] SATA_IDLE_VAL_0 = 3'b011; + parameter [2:0] SATA_IDLE_VAL_1 = 3'b011; + parameter integer SATA_MAX_BURST_0 = 7; + parameter integer SATA_MAX_BURST_1 = 7; + parameter integer SATA_MAX_INIT_0 = 22; + parameter integer SATA_MAX_INIT_1 = 22; + parameter integer SATA_MAX_WAKE_0 = 7; + parameter integer SATA_MAX_WAKE_1 = 7; + parameter integer SATA_MIN_BURST_0 = 4; + parameter integer SATA_MIN_BURST_1 = 4; + parameter integer SATA_MIN_INIT_0 = 12; + parameter integer SATA_MIN_INIT_1 = 12; + parameter integer SATA_MIN_WAKE_0 = 4; + parameter integer SATA_MIN_WAKE_1 = 4; + parameter integer SIM_GTPRESET_SPEEDUP = 0; + parameter SIM_RECEIVER_DETECT_PASS = "FALSE"; + parameter [2:0] SIM_REFCLK0_SOURCE = 3'b000; + parameter [2:0] SIM_REFCLK1_SOURCE = 3'b000; + parameter SIM_TX_ELEC_IDLE_LEVEL = "X"; + parameter SIM_VERSION = "2.0"; + parameter [4:0] TERMINATION_CTRL_0 = 5'b10100; + parameter [4:0] TERMINATION_CTRL_1 = 5'b10100; + parameter TERMINATION_OVRD_0 = "FALSE"; + parameter TERMINATION_OVRD_1 = "FALSE"; + parameter [11:0] TRANS_TIME_FROM_P2_0 = 12'h03C; + parameter [11:0] TRANS_TIME_FROM_P2_1 = 12'h03C; + parameter [7:0] TRANS_TIME_NON_P2_0 = 8'h19; + parameter [7:0] TRANS_TIME_NON_P2_1 = 8'h19; + parameter [9:0] TRANS_TIME_TO_P2_0 = 10'h064; + parameter [9:0] TRANS_TIME_TO_P2_1 = 10'h064; + parameter [31:0] TST_ATTR_0 = 32'h00000000; + parameter [31:0] TST_ATTR_1 = 32'h00000000; + parameter [2:0] TXRX_INVERT_0 = 3'b011; + parameter [2:0] TXRX_INVERT_1 = 3'b011; + parameter TX_BUFFER_USE_0 = "FALSE"; + parameter TX_BUFFER_USE_1 = "FALSE"; + parameter [13:0] TX_DETECT_RX_CFG_0 = 14'h1832; + parameter [13:0] TX_DETECT_RX_CFG_1 = 14'h1832; + parameter [2:0] TX_IDLE_DELAY_0 = 3'b011; + parameter [2:0] TX_IDLE_DELAY_1 = 3'b011; + parameter [1:0] TX_TDCC_CFG_0 = 2'b00; + parameter [1:0] TX_TDCC_CFG_1 = 2'b00; + parameter TX_XCLK_SEL_0 = "TXUSR"; + parameter TX_XCLK_SEL_1 = "TXUSR"; + + localparam in_delay = 0; + localparam out_delay = 0; + localparam INCLK_DELAY = 0; + localparam OUTCLK_DELAY = 0; + localparam MODULE_NAME = "GTPA1_DUAL"; + + + output DRDY; + output PHYSTATUS0; + output PHYSTATUS1; + output PLLLKDET0; + output PLLLKDET1; + output REFCLKOUT0; + output REFCLKOUT1; + output REFCLKPLL0; + output REFCLKPLL1; + output RESETDONE0; + output RESETDONE1; + output RXBYTEISALIGNED0; + output RXBYTEISALIGNED1; + output RXBYTEREALIGN0; + output RXBYTEREALIGN1; + output RXCHANBONDSEQ0; + output RXCHANBONDSEQ1; + output RXCHANISALIGNED0; + output RXCHANISALIGNED1; + output RXCHANREALIGN0; + output RXCHANREALIGN1; + output RXCOMMADET0; + output RXCOMMADET1; + output RXELECIDLE0; + output RXELECIDLE1; + output RXPRBSERR0; + output RXPRBSERR1; + output RXRECCLK0; + output RXRECCLK1; + output RXVALID0; + output RXVALID1; + output TXN0; + output TXN1; + output TXOUTCLK0; + output TXOUTCLK1; + output TXP0; + output TXP1; + output [15:0] DRPDO; + output [1:0] GTPCLKFBEAST; + output [1:0] GTPCLKFBWEST; + output [1:0] GTPCLKOUT0; + output [1:0] GTPCLKOUT1; + output [1:0] RXLOSSOFSYNC0; + output [1:0] RXLOSSOFSYNC1; + output [1:0] TXBUFSTATUS0; + output [1:0] TXBUFSTATUS1; + output [2:0] RXBUFSTATUS0; + output [2:0] RXBUFSTATUS1; + output [2:0] RXCHBONDO; + output [2:0] RXCLKCORCNT0; + output [2:0] RXCLKCORCNT1; + output [2:0] RXSTATUS0; + output [2:0] RXSTATUS1; + output [31:0] RXDATA0; + output [31:0] RXDATA1; + output [3:0] RXCHARISCOMMA0; + output [3:0] RXCHARISCOMMA1; + output [3:0] RXCHARISK0; + output [3:0] RXCHARISK1; + output [3:0] RXDISPERR0; + output [3:0] RXDISPERR1; + output [3:0] RXNOTINTABLE0; + output [3:0] RXNOTINTABLE1; + output [3:0] RXRUNDISP0; + output [3:0] RXRUNDISP1; + output [3:0] TXKERR0; + output [3:0] TXKERR1; + output [3:0] TXRUNDISP0; + output [3:0] TXRUNDISP1; + output [4:0] RCALOUTEAST; + output [4:0] RCALOUTWEST; + output [4:0] TSTOUT0; + output [4:0] TSTOUT1; + + input CLK00; + input CLK01; + input CLK10; + input CLK11; + input CLKINEAST0; + input CLKINEAST1; + input CLKINWEST0; + input CLKINWEST1; + input DCLK; + input DEN; + input DWE; + input GATERXELECIDLE0; + input GATERXELECIDLE1; + input GCLK00; + input GCLK01; + input GCLK10; + input GCLK11; + input GTPRESET0; + input GTPRESET1; + input IGNORESIGDET0; + input IGNORESIGDET1; + input INTDATAWIDTH0; + input INTDATAWIDTH1; + input PLLCLK00; + input PLLCLK01; + input PLLCLK10; + input PLLCLK11; + input PLLLKDETEN0; + input PLLLKDETEN1; + input PLLPOWERDOWN0; + input PLLPOWERDOWN1; + input PRBSCNTRESET0; + input PRBSCNTRESET1; + input REFCLKPWRDNB0; + input REFCLKPWRDNB1; + input RXBUFRESET0; + input RXBUFRESET1; + input RXCDRRESET0; + input RXCDRRESET1; + input RXCHBONDMASTER0; + input RXCHBONDMASTER1; + input RXCHBONDSLAVE0; + input RXCHBONDSLAVE1; + input RXCOMMADETUSE0; + input RXCOMMADETUSE1; + input RXDEC8B10BUSE0; + input RXDEC8B10BUSE1; + input RXENCHANSYNC0; + input RXENCHANSYNC1; + input RXENMCOMMAALIGN0; + input RXENMCOMMAALIGN1; + input RXENPCOMMAALIGN0; + input RXENPCOMMAALIGN1; + input RXENPMAPHASEALIGN0; + input RXENPMAPHASEALIGN1; + input RXN0; + input RXN1; + input RXP0; + input RXP1; + input RXPMASETPHASE0; + input RXPMASETPHASE1; + input RXPOLARITY0; + input RXPOLARITY1; + input RXRESET0; + input RXRESET1; + input RXSLIDE0; + input RXSLIDE1; + input RXUSRCLK0; + input RXUSRCLK1; + input RXUSRCLK20; + input RXUSRCLK21; + input TSTCLK0; + input TSTCLK1; + input TXCOMSTART0; + input TXCOMSTART1; + input TXCOMTYPE0; + input TXCOMTYPE1; + input TXDETECTRX0; + input TXDETECTRX1; + input TXELECIDLE0; + input TXELECIDLE1; + input TXENC8B10BUSE0; + input TXENC8B10BUSE1; + input TXENPMAPHASEALIGN0; + input TXENPMAPHASEALIGN1; + input TXINHIBIT0; + input TXINHIBIT1; + input TXPDOWNASYNCH0; + input TXPDOWNASYNCH1; + input TXPMASETPHASE0; + input TXPMASETPHASE1; + input TXPOLARITY0; + input TXPOLARITY1; + input TXPRBSFORCEERR0; + input TXPRBSFORCEERR1; + input TXRESET0; + input TXRESET1; + input TXUSRCLK0; + input TXUSRCLK1; + input TXUSRCLK20; + input TXUSRCLK21; + input USRCODEERR0; + input USRCODEERR1; + input [11:0] TSTIN0; + input [11:0] TSTIN1; + input [15:0] DI; + input [1:0] GTPCLKFBSEL0EAST; + input [1:0] GTPCLKFBSEL0WEST; + input [1:0] GTPCLKFBSEL1EAST; + input [1:0] GTPCLKFBSEL1WEST; + input [1:0] RXDATAWIDTH0; + input [1:0] RXDATAWIDTH1; + input [1:0] RXEQMIX0; + input [1:0] RXEQMIX1; + input [1:0] RXPOWERDOWN0; + input [1:0] RXPOWERDOWN1; + input [1:0] TXDATAWIDTH0; + input [1:0] TXDATAWIDTH1; + input [1:0] TXPOWERDOWN0; + input [1:0] TXPOWERDOWN1; + input [2:0] LOOPBACK0; + input [2:0] LOOPBACK1; + input [2:0] REFSELDYPLL0; + input [2:0] REFSELDYPLL1; + input [2:0] RXCHBONDI; + input [2:0] RXENPRBSTST0; + input [2:0] RXENPRBSTST1; + input [2:0] TXBUFDIFFCTRL0; + input [2:0] TXBUFDIFFCTRL1; + input [2:0] TXENPRBSTST0; + input [2:0] TXENPRBSTST1; + input [2:0] TXPREEMPHASIS0; + input [2:0] TXPREEMPHASIS1; + input [31:0] TXDATA0; + input [31:0] TXDATA1; + input [3:0] TXBYPASS8B10B0; + input [3:0] TXBYPASS8B10B1; + input [3:0] TXCHARDISPMODE0; + input [3:0] TXCHARDISPMODE1; + input [3:0] TXCHARDISPVAL0; + input [3:0] TXCHARDISPVAL1; + input [3:0] TXCHARISK0; + input [3:0] TXCHARISK1; + input [3:0] TXDIFFCTRL0; + input [3:0] TXDIFFCTRL1; + input [4:0] RCALINEAST; + input [4:0] RCALINWEST; + input [7:0] DADDR; + input [7:0] GTPTEST0; + input [7:0] GTPTEST1; + + reg SIM_GTPRESET_SPEEDUP_BINARY; + reg SIM_RECEIVER_DETECT_PASS_BINARY; + reg SIM_TX_ELEC_IDLE_LEVEL_BINARY; + reg SIM_VERSION_BINARY; + reg [0:0] AC_CAP_DIS_0_BINARY; + reg [0:0] AC_CAP_DIS_1_BINARY; + reg [0:0] ALIGN_COMMA_WORD_0_BINARY; + reg [0:0] ALIGN_COMMA_WORD_1_BINARY; + reg [0:0] CHAN_BOND_KEEP_ALIGN_0_BINARY; + reg [0:0] CHAN_BOND_KEEP_ALIGN_1_BINARY; + reg [0:0] CHAN_BOND_SEQ_2_USE_0_BINARY; + reg [0:0] CHAN_BOND_SEQ_2_USE_1_BINARY; + reg [0:0] CLKINDC_B_0_BINARY; + reg [0:0] CLKINDC_B_1_BINARY; + reg [0:0] CLKRCV_TRST_0_BINARY; + reg [0:0] CLKRCV_TRST_1_BINARY; + reg [0:0] CLK_CORRECT_USE_0_BINARY; + reg [0:0] CLK_CORRECT_USE_1_BINARY; + reg [0:0] CLK_COR_INSERT_IDLE_FLAG_0_BINARY; + reg [0:0] CLK_COR_INSERT_IDLE_FLAG_1_BINARY; + reg [0:0] CLK_COR_KEEP_IDLE_0_BINARY; + reg [0:0] CLK_COR_KEEP_IDLE_1_BINARY; + reg [0:0] CLK_COR_PRECEDENCE_0_BINARY; + reg [0:0] CLK_COR_PRECEDENCE_1_BINARY; + reg [0:0] CLK_COR_SEQ_2_USE_0_BINARY; + reg [0:0] CLK_COR_SEQ_2_USE_1_BINARY; + reg [0:0] CLK_OUT_GTP_SEL_0_BINARY; + reg [0:0] CLK_OUT_GTP_SEL_1_BINARY; + reg [0:0] DEC_MCOMMA_DETECT_0_BINARY; + reg [0:0] DEC_MCOMMA_DETECT_1_BINARY; + reg [0:0] DEC_PCOMMA_DETECT_0_BINARY; + reg [0:0] DEC_PCOMMA_DETECT_1_BINARY; + reg [0:0] DEC_VALID_COMMA_ONLY_0_BINARY; + reg [0:0] DEC_VALID_COMMA_ONLY_1_BINARY; + reg [0:0] GTP_CFG_PWRUP_0_BINARY; + reg [0:0] GTP_CFG_PWRUP_1_BINARY; + reg [0:0] MCOMMA_DETECT_0_BINARY; + reg [0:0] MCOMMA_DETECT_1_BINARY; + reg [0:0] PCI_EXPRESS_MODE_0_BINARY; + reg [0:0] PCI_EXPRESS_MODE_1_BINARY; + reg [0:0] PCOMMA_DETECT_0_BINARY; + reg [0:0] PCOMMA_DETECT_1_BINARY; + reg [0:0] PLL_SATA_0_BINARY; + reg [0:0] PLL_SATA_1_BINARY; + reg [0:0] PLL_SOURCE_0_BINARY; + reg [0:0] PLL_SOURCE_1_BINARY; + reg [0:0] RCV_TERM_GND_0_BINARY; + reg [0:0] RCV_TERM_GND_1_BINARY; + reg [0:0] RCV_TERM_VTTRX_0_BINARY; + reg [0:0] RCV_TERM_VTTRX_1_BINARY; + reg [0:0] RXPRBSERR_LOOPBACK_0_BINARY; + reg [0:0] RXPRBSERR_LOOPBACK_1_BINARY; + reg [0:0] RX_BUFFER_USE_0_BINARY; + reg [0:0] RX_BUFFER_USE_1_BINARY; + reg [0:0] RX_DECODE_SEQ_MATCH_0_BINARY; + reg [0:0] RX_DECODE_SEQ_MATCH_1_BINARY; + reg [0:0] RX_EN_IDLE_HOLD_CDR_0_BINARY; + reg [0:0] RX_EN_IDLE_HOLD_CDR_1_BINARY; + reg [0:0] RX_EN_IDLE_RESET_BUF_0_BINARY; + reg [0:0] RX_EN_IDLE_RESET_BUF_1_BINARY; + reg [0:0] RX_EN_IDLE_RESET_FR_0_BINARY; + reg [0:0] RX_EN_IDLE_RESET_FR_1_BINARY; + reg [0:0] RX_EN_IDLE_RESET_PH_0_BINARY; + reg [0:0] RX_EN_IDLE_RESET_PH_1_BINARY; + reg [0:0] RX_EN_MODE_RESET_BUF_0_BINARY; + reg [0:0] RX_EN_MODE_RESET_BUF_1_BINARY; + reg [0:0] RX_LOSS_OF_SYNC_FSM_0_BINARY; + reg [0:0] RX_LOSS_OF_SYNC_FSM_1_BINARY; + reg [0:0] RX_SLIDE_MODE_0_BINARY; + reg [0:0] RX_SLIDE_MODE_1_BINARY; + reg [0:0] RX_STATUS_FMT_0_BINARY; + reg [0:0] RX_STATUS_FMT_1_BINARY; + reg [0:0] RX_XCLK_SEL_0_BINARY; + reg [0:0] RX_XCLK_SEL_1_BINARY; + reg [0:0] TERMINATION_OVRD_0_BINARY; + reg [0:0] TERMINATION_OVRD_1_BINARY; + reg [0:0] TX_BUFFER_USE_0_BINARY; + reg [0:0] TX_BUFFER_USE_1_BINARY; + reg [0:0] TX_XCLK_SEL_0_BINARY; + reg [0:0] TX_XCLK_SEL_1_BINARY; + reg [1:0] CHAN_BOND_SEQ_LEN_0_BINARY; + reg [1:0] CHAN_BOND_SEQ_LEN_1_BINARY; + reg [1:0] CLK_COR_ADJ_LEN_0_BINARY; + reg [1:0] CLK_COR_ADJ_LEN_1_BINARY; + reg [1:0] CLK_COR_DET_LEN_0_BINARY; + reg [1:0] CLK_COR_DET_LEN_1_BINARY; + reg [1:0] CM_TRIM_0_BINARY; + reg [1:0] CM_TRIM_1_BINARY; + reg [1:0] PLL_RXDIVSEL_OUT_0_BINARY; + reg [1:0] PLL_RXDIVSEL_OUT_1_BINARY; + reg [1:0] PLL_TXDIVSEL_OUT_0_BINARY; + reg [1:0] PLL_TXDIVSEL_OUT_1_BINARY; + reg [1:0] TX_TDCC_CFG_0_BINARY; + reg [1:0] TX_TDCC_CFG_1_BINARY; + reg [2:0] CLK25_DIVIDER_0_BINARY; + reg [2:0] CLK25_DIVIDER_1_BINARY; + reg [2:0] OOBDETECT_THRESHOLD_0_BINARY; + reg [2:0] OOBDETECT_THRESHOLD_1_BINARY; + reg [2:0] OOB_CLK_DIVIDER_0_BINARY; + reg [2:0] OOB_CLK_DIVIDER_1_BINARY; + reg [2:0] PLLLKDET_CFG_0_BINARY; + reg [2:0] PLLLKDET_CFG_1_BINARY; + reg [2:0] RX_LOS_INVALID_INCR_0_BINARY; + reg [2:0] RX_LOS_INVALID_INCR_1_BINARY; + reg [2:0] RX_LOS_THRESHOLD_0_BINARY; + reg [2:0] RX_LOS_THRESHOLD_1_BINARY; + reg [2:0] SATA_BURST_VAL_0_BINARY; + reg [2:0] SATA_BURST_VAL_1_BINARY; + reg [2:0] SATA_IDLE_VAL_0_BINARY; + reg [2:0] SATA_IDLE_VAL_1_BINARY; + reg [2:0] SIM_REFCLK0_SOURCE_BINARY; + reg [2:0] SIM_REFCLK1_SOURCE_BINARY; + reg [2:0] TXRX_INVERT_0_BINARY; + reg [2:0] TXRX_INVERT_1_BINARY; + reg [2:0] TX_IDLE_DELAY_0_BINARY; + reg [2:0] TX_IDLE_DELAY_1_BINARY; + reg [3:0] CB2_INH_CC_PERIOD_0_BINARY; + reg [3:0] CB2_INH_CC_PERIOD_1_BINARY; + reg [3:0] CHAN_BOND_1_MAX_SKEW_0_BINARY; + reg [3:0] CHAN_BOND_1_MAX_SKEW_1_BINARY; + reg [3:0] CHAN_BOND_2_MAX_SKEW_0_BINARY; + reg [3:0] CHAN_BOND_2_MAX_SKEW_1_BINARY; + reg [3:0] CHAN_BOND_SEQ_1_ENABLE_0_BINARY; + reg [3:0] CHAN_BOND_SEQ_1_ENABLE_1_BINARY; + reg [3:0] CHAN_BOND_SEQ_2_ENABLE_0_BINARY; + reg [3:0] CHAN_BOND_SEQ_2_ENABLE_1_BINARY; + reg [3:0] CLK_COR_SEQ_1_ENABLE_0_BINARY; + reg [3:0] CLK_COR_SEQ_1_ENABLE_1_BINARY; + reg [3:0] CLK_COR_SEQ_2_ENABLE_0_BINARY; + reg [3:0] CLK_COR_SEQ_2_ENABLE_1_BINARY; + reg [3:0] COM_BURST_VAL_0_BINARY; + reg [3:0] COM_BURST_VAL_1_BINARY; + reg [3:0] RX_IDLE_HI_CNT_0_BINARY; + reg [3:0] RX_IDLE_HI_CNT_1_BINARY; + reg [3:0] RX_IDLE_LO_CNT_0_BINARY; + reg [3:0] RX_IDLE_LO_CNT_1_BINARY; + reg [4:0] CDR_PH_ADJ_TIME_0_BINARY; + reg [4:0] CDR_PH_ADJ_TIME_1_BINARY; + reg [4:0] CLK_COR_REPEAT_WAIT_0_BINARY; + reg [4:0] CLK_COR_REPEAT_WAIT_1_BINARY; + reg [4:0] PLL_DIVSEL_FB_0_BINARY; + reg [4:0] PLL_DIVSEL_FB_1_BINARY; + reg [4:0] TERMINATION_CTRL_0_BINARY; + reg [4:0] TERMINATION_CTRL_1_BINARY; + reg [5:0] CLK_COR_MAX_LAT_0_BINARY; + reg [5:0] CLK_COR_MAX_LAT_1_BINARY; + reg [5:0] CLK_COR_MIN_LAT_0_BINARY; + reg [5:0] CLK_COR_MIN_LAT_1_BINARY; + reg [5:0] PLL_DIVSEL_REF_0_BINARY; + reg [5:0] PLL_DIVSEL_REF_1_BINARY; + reg [5:0] SATA_MAX_BURST_0_BINARY; + reg [5:0] SATA_MAX_BURST_1_BINARY; + reg [5:0] SATA_MAX_INIT_0_BINARY; + reg [5:0] SATA_MAX_INIT_1_BINARY; + reg [5:0] SATA_MAX_WAKE_0_BINARY; + reg [5:0] SATA_MAX_WAKE_1_BINARY; + reg [5:0] SATA_MIN_BURST_0_BINARY; + reg [5:0] SATA_MIN_BURST_1_BINARY; + reg [5:0] SATA_MIN_INIT_0_BINARY; + reg [5:0] SATA_MIN_INIT_1_BINARY; + reg [5:0] SATA_MIN_WAKE_0_BINARY; + reg [5:0] SATA_MIN_WAKE_1_BINARY; + reg [7:0] RXEQ_CFG_0_BINARY; + reg [7:0] RXEQ_CFG_1_BINARY; + reg [9:0] CHAN_BOND_SEQ_1_1_0_BINARY; + reg [9:0] CHAN_BOND_SEQ_1_1_1_BINARY; + reg [9:0] CHAN_BOND_SEQ_1_2_0_BINARY; + reg [9:0] CHAN_BOND_SEQ_1_2_1_BINARY; + reg [9:0] CHAN_BOND_SEQ_1_3_0_BINARY; + reg [9:0] CHAN_BOND_SEQ_1_3_1_BINARY; + reg [9:0] CHAN_BOND_SEQ_1_4_0_BINARY; + reg [9:0] CHAN_BOND_SEQ_1_4_1_BINARY; + reg [9:0] CHAN_BOND_SEQ_2_1_0_BINARY; + reg [9:0] CHAN_BOND_SEQ_2_1_1_BINARY; + reg [9:0] CHAN_BOND_SEQ_2_2_0_BINARY; + reg [9:0] CHAN_BOND_SEQ_2_2_1_BINARY; + reg [9:0] CHAN_BOND_SEQ_2_3_0_BINARY; + reg [9:0] CHAN_BOND_SEQ_2_3_1_BINARY; + reg [9:0] CHAN_BOND_SEQ_2_4_0_BINARY; + reg [9:0] CHAN_BOND_SEQ_2_4_1_BINARY; + reg [9:0] CLK_COR_SEQ_1_1_0_BINARY; + reg [9:0] CLK_COR_SEQ_1_1_1_BINARY; + reg [9:0] CLK_COR_SEQ_1_2_0_BINARY; + reg [9:0] CLK_COR_SEQ_1_2_1_BINARY; + reg [9:0] CLK_COR_SEQ_1_3_0_BINARY; + reg [9:0] CLK_COR_SEQ_1_3_1_BINARY; + reg [9:0] CLK_COR_SEQ_1_4_0_BINARY; + reg [9:0] CLK_COR_SEQ_1_4_1_BINARY; + reg [9:0] CLK_COR_SEQ_2_1_0_BINARY; + reg [9:0] CLK_COR_SEQ_2_1_1_BINARY; + reg [9:0] CLK_COR_SEQ_2_2_0_BINARY; + reg [9:0] CLK_COR_SEQ_2_2_1_BINARY; + reg [9:0] CLK_COR_SEQ_2_3_0_BINARY; + reg [9:0] CLK_COR_SEQ_2_3_1_BINARY; + reg [9:0] CLK_COR_SEQ_2_4_0_BINARY; + reg [9:0] CLK_COR_SEQ_2_4_1_BINARY; + reg [9:0] COMMA_10B_ENABLE_0_BINARY; + reg [9:0] COMMA_10B_ENABLE_1_BINARY; + reg [9:0] MCOMMA_10B_VALUE_0_BINARY; + reg [9:0] MCOMMA_10B_VALUE_1_BINARY; + reg [9:0] PCOMMA_10B_VALUE_0_BINARY; + reg [9:0] PCOMMA_10B_VALUE_1_BINARY; + + tri0 GSR = glbl.GSR; + wire DRDY_OUT; + wire PHYSTATUS0_OUT; + wire PHYSTATUS1_OUT; + wire PLLLKDET0_OUT; + wire PLLLKDET1_OUT; + wire REFCLKOUT0_OUT; + wire REFCLKOUT1_OUT; + wire REFCLKPLL0_OUT; + wire REFCLKPLL1_OUT; + wire RESETDONE0_OUT; + wire RESETDONE1_OUT; + wire RXBYTEISALIGNED0_OUT; + wire RXBYTEISALIGNED1_OUT; + wire RXBYTEREALIGN0_OUT; + wire RXBYTEREALIGN1_OUT; + wire RXCHANBONDSEQ0_OUT; + wire RXCHANBONDSEQ1_OUT; + wire RXCHANISALIGNED0_OUT; + wire RXCHANISALIGNED1_OUT; + wire RXCHANREALIGN0_OUT; + wire RXCHANREALIGN1_OUT; + wire RXCOMMADET0_OUT; + wire RXCOMMADET1_OUT; + wire RXELECIDLE0_OUT; + wire RXELECIDLE1_OUT; + wire RXPRBSERR0_OUT; + wire RXPRBSERR1_OUT; + wire RXRECCLK0_OUT; + wire RXRECCLK1_OUT; + wire RXVALID0_OUT; + wire RXVALID1_OUT; + wire TXN0_OUT; + wire TXN1_OUT; + wire TXOUTCLK0_OUT; + wire TXOUTCLK1_OUT; + wire TXP0_OUT; + wire TXP1_OUT; + wire [15:0] DRPDO_OUT; + wire [1:0] GTPCLKFBEAST_OUT; + wire [1:0] GTPCLKFBWEST_OUT; + wire [1:0] GTPCLKOUT0_OUT; + wire [1:0] GTPCLKOUT1_OUT; + wire [1:0] RXLOSSOFSYNC0_OUT; + wire [1:0] RXLOSSOFSYNC1_OUT; + wire [1:0] TXBUFSTATUS0_OUT; + wire [1:0] TXBUFSTATUS1_OUT; + wire [2:0] RXBUFSTATUS0_OUT; + wire [2:0] RXBUFSTATUS1_OUT; + wire [2:0] RXCHBONDO_OUT; + wire [2:0] RXCLKCORCNT0_OUT; + wire [2:0] RXCLKCORCNT1_OUT; + wire [2:0] RXSTATUS0_OUT; + wire [2:0] RXSTATUS1_OUT; + wire [31:0] RXDATA0_OUT; + wire [31:0] RXDATA1_OUT; + wire [3:0] RXCHARISCOMMA0_OUT; + wire [3:0] RXCHARISCOMMA1_OUT; + wire [3:0] RXCHARISK0_OUT; + wire [3:0] RXCHARISK1_OUT; + wire [3:0] RXDISPERR0_OUT; + wire [3:0] RXDISPERR1_OUT; + wire [3:0] RXNOTINTABLE0_OUT; + wire [3:0] RXNOTINTABLE1_OUT; + wire [3:0] RXRUNDISP0_OUT; + wire [3:0] RXRUNDISP1_OUT; + wire [3:0] TXKERR0_OUT; + wire [3:0] TXKERR1_OUT; + wire [3:0] TXRUNDISP0_OUT; + wire [3:0] TXRUNDISP1_OUT; + wire [4:0] RCALOUTEAST_OUT; + wire [4:0] RCALOUTWEST_OUT; + wire [4:0] TSTOUT0_OUT; + wire [4:0] TSTOUT1_OUT; + + wire delay_DRDY; + wire delay_PHYSTATUS0; + wire delay_PHYSTATUS1; + wire delay_PLLLKDET0; + wire delay_PLLLKDET1; + wire delay_REFCLKOUT0; + wire delay_REFCLKOUT1; + wire delay_REFCLKPLL0; + wire delay_REFCLKPLL1; + wire delay_RESETDONE0; + wire delay_RESETDONE1; + wire delay_RXBYTEISALIGNED0; + wire delay_RXBYTEISALIGNED1; + wire delay_RXBYTEREALIGN0; + wire delay_RXBYTEREALIGN1; + wire delay_RXCHANBONDSEQ0; + wire delay_RXCHANBONDSEQ1; + wire delay_RXCHANISALIGNED0; + wire delay_RXCHANISALIGNED1; + wire delay_RXCHANREALIGN0; + wire delay_RXCHANREALIGN1; + wire delay_RXCOMMADET0; + wire delay_RXCOMMADET1; + wire delay_RXELECIDLE0; + wire delay_RXELECIDLE1; + wire delay_RXPRBSERR0; + wire delay_RXPRBSERR1; + wire delay_RXRECCLK0; + wire delay_RXRECCLK1; + wire delay_RXVALID0; + wire delay_RXVALID1; + wire delay_TXN0; + wire delay_TXN1; + wire delay_TXOUTCLK0; + wire delay_TXOUTCLK1; + wire delay_TXP0; + wire delay_TXP1; + wire [15:0] delay_DRPDO; + wire [1:0] delay_GTPCLKFBEAST; + wire [1:0] delay_GTPCLKFBWEST; + wire [1:0] delay_GTPCLKOUT0; + wire [1:0] delay_GTPCLKOUT1; + wire [1:0] delay_RXLOSSOFSYNC0; + wire [1:0] delay_RXLOSSOFSYNC1; + wire [1:0] delay_TXBUFSTATUS0; + wire [1:0] delay_TXBUFSTATUS1; + wire [2:0] delay_RXBUFSTATUS0; + wire [2:0] delay_RXBUFSTATUS1; + wire [2:0] delay_RXCHBONDO; + wire [2:0] delay_RXCLKCORCNT0; + wire [2:0] delay_RXCLKCORCNT1; + wire [2:0] delay_RXSTATUS0; + wire [2:0] delay_RXSTATUS1; + wire [31:0] delay_RXDATA0; + wire [31:0] delay_RXDATA1; + wire [3:0] delay_RXCHARISCOMMA0; + wire [3:0] delay_RXCHARISCOMMA1; + wire [3:0] delay_RXCHARISK0; + wire [3:0] delay_RXCHARISK1; + wire [3:0] delay_RXDISPERR0; + wire [3:0] delay_RXDISPERR1; + wire [3:0] delay_RXNOTINTABLE0; + wire [3:0] delay_RXNOTINTABLE1; + wire [3:0] delay_RXRUNDISP0; + wire [3:0] delay_RXRUNDISP1; + wire [3:0] delay_TXKERR0; + wire [3:0] delay_TXKERR1; + wire [3:0] delay_TXRUNDISP0; + wire [3:0] delay_TXRUNDISP1; + wire [4:0] delay_RCALOUTEAST; + wire [4:0] delay_RCALOUTWEST; + wire [4:0] delay_TSTOUT0; + wire [4:0] delay_TSTOUT1; + + wire CLK00_IN; + wire CLK01_IN; + wire CLK10_IN; + wire CLK11_IN; + wire CLKINEAST0_IN; + wire CLKINEAST1_IN; + wire CLKINWEST0_IN; + wire CLKINWEST1_IN; + wire DCLK_IN; + wire DEN_IN; + wire DWE_IN; + wire GATERXELECIDLE0_IN; + wire GATERXELECIDLE1_IN; + wire GCLK00_IN; + wire GCLK01_IN; + wire GCLK10_IN; + wire GCLK11_IN; + wire GTPRESET0_IN; + wire GTPRESET1_IN; + wire IGNORESIGDET0_IN; + wire IGNORESIGDET1_IN; + wire INTDATAWIDTH0_IN; + wire INTDATAWIDTH1_IN; + wire PLLCLK00_IN; + wire PLLCLK01_IN; + wire PLLCLK10_IN; + wire PLLCLK11_IN; + wire PLLLKDETEN0_IN; + wire PLLLKDETEN1_IN; + wire PLLPOWERDOWN0_IN; + wire PLLPOWERDOWN1_IN; + wire PRBSCNTRESET0_IN; + wire PRBSCNTRESET1_IN; + wire REFCLKPWRDNB0_IN; + wire REFCLKPWRDNB1_IN; + wire RXBUFRESET0_IN; + wire RXBUFRESET1_IN; + wire RXCDRRESET0_IN; + wire RXCDRRESET1_IN; + wire RXCHBONDMASTER0_IN; + wire RXCHBONDMASTER1_IN; + wire RXCHBONDSLAVE0_IN; + wire RXCHBONDSLAVE1_IN; + wire RXCOMMADETUSE0_IN; + wire RXCOMMADETUSE1_IN; + wire RXDEC8B10BUSE0_IN; + wire RXDEC8B10BUSE1_IN; + wire RXENCHANSYNC0_IN; + wire RXENCHANSYNC1_IN; + wire RXENMCOMMAALIGN0_IN; + wire RXENMCOMMAALIGN1_IN; + wire RXENPCOMMAALIGN0_IN; + wire RXENPCOMMAALIGN1_IN; + wire RXENPMAPHASEALIGN0_IN; + wire RXENPMAPHASEALIGN1_IN; + wire RXN0_IN; + wire RXN1_IN; + wire RXP0_IN; + wire RXP1_IN; + wire RXPMASETPHASE0_IN; + wire RXPMASETPHASE1_IN; + wire RXPOLARITY0_IN; + wire RXPOLARITY1_IN; + wire RXRESET0_IN; + wire RXRESET1_IN; + wire RXSLIDE0_IN; + wire RXSLIDE1_IN; + wire RXUSRCLK0_IN; + wire RXUSRCLK1_IN; + wire RXUSRCLK20_IN; + wire RXUSRCLK21_IN; + wire TSTCLK0_IN; + wire TSTCLK1_IN; + wire TXCOMSTART0_IN; + wire TXCOMSTART1_IN; + wire TXCOMTYPE0_IN; + wire TXCOMTYPE1_IN; + wire TXDETECTRX0_IN; + wire TXDETECTRX1_IN; + wire TXELECIDLE0_IN; + wire TXELECIDLE1_IN; + wire TXENC8B10BUSE0_IN; + wire TXENC8B10BUSE1_IN; + wire TXENPMAPHASEALIGN0_IN; + wire TXENPMAPHASEALIGN1_IN; + wire TXINHIBIT0_IN; + wire TXINHIBIT1_IN; + wire TXPDOWNASYNCH0_IN; + wire TXPDOWNASYNCH1_IN; + wire TXPMASETPHASE0_IN; + wire TXPMASETPHASE1_IN; + wire TXPOLARITY0_IN; + wire TXPOLARITY1_IN; + wire TXPRBSFORCEERR0_IN; + wire TXPRBSFORCEERR1_IN; + wire TXRESET0_IN; + wire TXRESET1_IN; + wire TXUSRCLK0_IN; + wire TXUSRCLK1_IN; + wire TXUSRCLK20_IN; + wire TXUSRCLK21_IN; + wire USRCODEERR0_IN; + wire USRCODEERR1_IN; + wire [11:0] TSTIN0_IN; + wire [11:0] TSTIN1_IN; + wire [15:0] DI_IN; + wire [1:0] GTPCLKFBSEL0EAST_IN; + wire [1:0] GTPCLKFBSEL0WEST_IN; + wire [1:0] GTPCLKFBSEL1EAST_IN; + wire [1:0] GTPCLKFBSEL1WEST_IN; + wire [1:0] RXDATAWIDTH0_IN; + wire [1:0] RXDATAWIDTH1_IN; + wire [1:0] RXEQMIX0_IN; + wire [1:0] RXEQMIX1_IN; + wire [1:0] RXPOWERDOWN0_IN; + wire [1:0] RXPOWERDOWN1_IN; + wire [1:0] TXDATAWIDTH0_IN; + wire [1:0] TXDATAWIDTH1_IN; + wire [1:0] TXPOWERDOWN0_IN; + wire [1:0] TXPOWERDOWN1_IN; + wire [2:0] LOOPBACK0_IN; + wire [2:0] LOOPBACK1_IN; + wire [2:0] REFSELDYPLL0_IN; + wire [2:0] REFSELDYPLL1_IN; + wire [2:0] RXCHBONDI_IN; + wire [2:0] RXENPRBSTST0_IN; + wire [2:0] RXENPRBSTST1_IN; + wire [2:0] TXBUFDIFFCTRL0_IN; + wire [2:0] TXBUFDIFFCTRL1_IN; + wire [2:0] TXENPRBSTST0_IN; + wire [2:0] TXENPRBSTST1_IN; + wire [2:0] TXPREEMPHASIS0_IN; + wire [2:0] TXPREEMPHASIS1_IN; + wire [31:0] TXDATA0_IN; + wire [31:0] TXDATA1_IN; + wire [3:0] TXBYPASS8B10B0_IN; + wire [3:0] TXBYPASS8B10B1_IN; + wire [3:0] TXCHARDISPMODE0_IN; + wire [3:0] TXCHARDISPMODE1_IN; + wire [3:0] TXCHARDISPVAL0_IN; + wire [3:0] TXCHARDISPVAL1_IN; + wire [3:0] TXCHARISK0_IN; + wire [3:0] TXCHARISK1_IN; + wire [3:0] TXDIFFCTRL0_IN; + wire [3:0] TXDIFFCTRL1_IN; + wire [4:0] RCALINEAST_IN; + wire [4:0] RCALINWEST_IN; + wire [7:0] DADDR_IN; + wire [7:0] GTPTEST0_IN; + wire [7:0] GTPTEST1_IN; + wire delay_CLK00; + wire delay_CLK01; + wire delay_CLK10; + wire delay_CLK11; + wire delay_CLKINEAST0; + wire delay_CLKINEAST1; + wire delay_CLKINWEST0; + wire delay_CLKINWEST1; + wire delay_DCLK; + wire delay_DEN; + wire delay_DWE; + wire delay_GATERXELECIDLE0; + wire delay_GATERXELECIDLE1; + wire delay_GCLK00; + wire delay_GCLK01; + wire delay_GCLK10; + wire delay_GCLK11; + wire delay_GTPRESET0; + wire delay_GTPRESET1; + wire delay_IGNORESIGDET0; + wire delay_IGNORESIGDET1; + wire delay_INTDATAWIDTH0; + wire delay_INTDATAWIDTH1; + wire delay_PLLCLK00; + wire delay_PLLCLK01; + wire delay_PLLCLK10; + wire delay_PLLCLK11; + wire delay_PLLLKDETEN0; + wire delay_PLLLKDETEN1; + wire delay_PLLPOWERDOWN0; + wire delay_PLLPOWERDOWN1; + wire delay_PRBSCNTRESET0; + wire delay_PRBSCNTRESET1; + wire delay_REFCLKPWRDNB0; + wire delay_REFCLKPWRDNB1; + wire delay_RXBUFRESET0; + wire delay_RXBUFRESET1; + wire delay_RXCDRRESET0; + wire delay_RXCDRRESET1; + wire delay_RXCHBONDMASTER0; + wire delay_RXCHBONDMASTER1; + wire delay_RXCHBONDSLAVE0; + wire delay_RXCHBONDSLAVE1; + wire delay_RXCOMMADETUSE0; + wire delay_RXCOMMADETUSE1; + wire delay_RXDEC8B10BUSE0; + wire delay_RXDEC8B10BUSE1; + wire delay_RXENCHANSYNC0; + wire delay_RXENCHANSYNC1; + wire delay_RXENMCOMMAALIGN0; + wire delay_RXENMCOMMAALIGN1; + wire delay_RXENPCOMMAALIGN0; + wire delay_RXENPCOMMAALIGN1; + wire delay_RXENPMAPHASEALIGN0; + wire delay_RXENPMAPHASEALIGN1; + wire delay_RXN0; + wire delay_RXN1; + wire delay_RXP0; + wire delay_RXP1; + wire delay_RXPMASETPHASE0; + wire delay_RXPMASETPHASE1; + wire delay_RXPOLARITY0; + wire delay_RXPOLARITY1; + wire delay_RXRESET0; + wire delay_RXRESET1; + wire delay_RXSLIDE0; + wire delay_RXSLIDE1; + wire delay_RXUSRCLK0; + wire delay_RXUSRCLK1; + wire delay_RXUSRCLK20; + wire delay_RXUSRCLK21; + wire delay_TSTCLK0; + wire delay_TSTCLK1; + wire delay_TXCOMSTART0; + wire delay_TXCOMSTART1; + wire delay_TXCOMTYPE0; + wire delay_TXCOMTYPE1; + wire delay_TXDETECTRX0; + wire delay_TXDETECTRX1; + wire delay_TXELECIDLE0; + wire delay_TXELECIDLE1; + wire delay_TXENC8B10BUSE0; + wire delay_TXENC8B10BUSE1; + wire delay_TXENPMAPHASEALIGN0; + wire delay_TXENPMAPHASEALIGN1; + wire delay_TXINHIBIT0; + wire delay_TXINHIBIT1; + wire delay_TXPDOWNASYNCH0; + wire delay_TXPDOWNASYNCH1; + wire delay_TXPMASETPHASE0; + wire delay_TXPMASETPHASE1; + wire delay_TXPOLARITY0; + wire delay_TXPOLARITY1; + wire delay_TXPRBSFORCEERR0; + wire delay_TXPRBSFORCEERR1; + wire delay_TXRESET0; + wire delay_TXRESET1; + wire delay_TXUSRCLK0; + wire delay_TXUSRCLK1; + wire delay_TXUSRCLK20; + wire delay_TXUSRCLK21; + wire delay_USRCODEERR0; + wire delay_USRCODEERR1; + wire [11:0] delay_TSTIN0; + wire [11:0] delay_TSTIN1; + wire [15:0] delay_DI; + wire [1:0] delay_GTPCLKFBSEL0EAST; + wire [1:0] delay_GTPCLKFBSEL0WEST; + wire [1:0] delay_GTPCLKFBSEL1EAST; + wire [1:0] delay_GTPCLKFBSEL1WEST; + wire [1:0] delay_RXDATAWIDTH0; + wire [1:0] delay_RXDATAWIDTH1; + wire [1:0] delay_RXEQMIX0; + wire [1:0] delay_RXEQMIX1; + wire [1:0] delay_RXPOWERDOWN0; + wire [1:0] delay_RXPOWERDOWN1; + wire [1:0] delay_TXDATAWIDTH0; + wire [1:0] delay_TXDATAWIDTH1; + wire [1:0] delay_TXPOWERDOWN0; + wire [1:0] delay_TXPOWERDOWN1; + wire [2:0] delay_LOOPBACK0; + wire [2:0] delay_LOOPBACK1; + wire [2:0] delay_REFSELDYPLL0; + wire [2:0] delay_REFSELDYPLL1; + wire [2:0] delay_RXCHBONDI; + wire [2:0] delay_RXENPRBSTST0; + wire [2:0] delay_RXENPRBSTST1; + wire [2:0] delay_TXBUFDIFFCTRL0; + wire [2:0] delay_TXBUFDIFFCTRL1; + wire [2:0] delay_TXENPRBSTST0; + wire [2:0] delay_TXENPRBSTST1; + wire [2:0] delay_TXPREEMPHASIS0; + wire [2:0] delay_TXPREEMPHASIS1; + wire [31:0] delay_TXDATA0; + wire [31:0] delay_TXDATA1; + wire [3:0] delay_TXBYPASS8B10B0; + wire [3:0] delay_TXBYPASS8B10B1; + wire [3:0] delay_TXCHARDISPMODE0; + wire [3:0] delay_TXCHARDISPMODE1; + wire [3:0] delay_TXCHARDISPVAL0; + wire [3:0] delay_TXCHARDISPVAL1; + wire [3:0] delay_TXCHARISK0; + wire [3:0] delay_TXCHARISK1; + wire [3:0] delay_TXDIFFCTRL0; + wire [3:0] delay_TXDIFFCTRL1; + wire [4:0] delay_RCALINEAST; + wire [4:0] delay_RCALINWEST; + wire [7:0] delay_DADDR; + wire [7:0] delay_GTPTEST0; + wire [7:0] delay_GTPTEST1; + + initial begin + case (AC_CAP_DIS_0[31:0]) + "ALSE" : AC_CAP_DIS_0_BINARY <= 1'b0; + "TRUE" : AC_CAP_DIS_0_BINARY <= 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute AC_CAP_DIS_0 on %s instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", MODULE_NAME, AC_CAP_DIS_0); + $finish; + end + endcase + + case (AC_CAP_DIS_1[31:0]) + "ALSE" : AC_CAP_DIS_1_BINARY <= 1'b0; + "TRUE" : AC_CAP_DIS_1_BINARY <= 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute AC_CAP_DIS_1 on %s instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", MODULE_NAME, AC_CAP_DIS_1); + $finish; + end + endcase + + case (ALIGN_COMMA_WORD_0) + 1 : ALIGN_COMMA_WORD_0_BINARY <= 1'b0; + 2 : ALIGN_COMMA_WORD_0_BINARY <= 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute ALIGN_COMMA_WORD_0 on %s instance %m is set to %d. Legal values for this attribute are 1 to 2.", MODULE_NAME, ALIGN_COMMA_WORD_0); + $finish; + end + endcase + + case (ALIGN_COMMA_WORD_1) + 1 : ALIGN_COMMA_WORD_1_BINARY <= 1'b0; + 2 : ALIGN_COMMA_WORD_1_BINARY <= 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute ALIGN_COMMA_WORD_1 on %s instance %m is set to %d. Legal values for this attribute are 1 to 2.", MODULE_NAME, ALIGN_COMMA_WORD_1); + $finish; + end + endcase + + case (CHAN_BOND_KEEP_ALIGN_0[31:0]) + "ALSE" : CHAN_BOND_KEEP_ALIGN_0_BINARY <= 1'b0; + "TRUE" : CHAN_BOND_KEEP_ALIGN_0_BINARY <= 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute CHAN_BOND_KEEP_ALIGN_0 on %s instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", MODULE_NAME, CHAN_BOND_KEEP_ALIGN_0); + $finish; + end + endcase + + case (CHAN_BOND_KEEP_ALIGN_1[31:0]) + "ALSE" : CHAN_BOND_KEEP_ALIGN_1_BINARY <= 1'b0; + "TRUE" : CHAN_BOND_KEEP_ALIGN_1_BINARY <= 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute CHAN_BOND_KEEP_ALIGN_1 on %s instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", MODULE_NAME, CHAN_BOND_KEEP_ALIGN_1); + $finish; + end + endcase + + case (CHAN_BOND_SEQ_2_USE_0[31:0]) + "ALSE" : CHAN_BOND_SEQ_2_USE_0_BINARY <= 1'b0; + "TRUE" : CHAN_BOND_SEQ_2_USE_0_BINARY <= 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute CHAN_BOND_SEQ_2_USE_0 on %s instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", MODULE_NAME, CHAN_BOND_SEQ_2_USE_0); + $finish; + end + endcase + + case (CHAN_BOND_SEQ_2_USE_1[31:0]) + "ALSE" : CHAN_BOND_SEQ_2_USE_1_BINARY <= 1'b0; + "TRUE" : CHAN_BOND_SEQ_2_USE_1_BINARY <= 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute CHAN_BOND_SEQ_2_USE_1 on %s instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", MODULE_NAME, CHAN_BOND_SEQ_2_USE_1); + $finish; + end + endcase + + case (CHAN_BOND_SEQ_LEN_0) + 1 : CHAN_BOND_SEQ_LEN_0_BINARY <= 2'b00; + 2 : CHAN_BOND_SEQ_LEN_0_BINARY <= 2'b01; + 4 : CHAN_BOND_SEQ_LEN_0_BINARY <= 2'b11; + default : begin + $display("Attribute Syntax Error : The Attribute CHAN_BOND_SEQ_LEN_0 on %s instance %m is set to %d. Legal values for this attribute are 1, 2 or 4.", MODULE_NAME, CHAN_BOND_SEQ_LEN_0); + $finish; + end + endcase + + case (CHAN_BOND_SEQ_LEN_1) + 1 : CHAN_BOND_SEQ_LEN_1_BINARY <= 2'b00; + 2 : CHAN_BOND_SEQ_LEN_1_BINARY <= 2'b01; + 4 : CHAN_BOND_SEQ_LEN_1_BINARY <= 2'b11; + default : begin + $display("Attribute Syntax Error : The Attribute CHAN_BOND_SEQ_LEN_1 on %s instance %m is set to %d. Legal values for this attribute are 1, 2 or 4.", MODULE_NAME, CHAN_BOND_SEQ_LEN_1); + $finish; + end + endcase + + case (CLK25_DIVIDER_0) + 4 : CLK25_DIVIDER_0_BINARY <= 3'b011; + 1 : CLK25_DIVIDER_0_BINARY <= 3'b000; + 2 : CLK25_DIVIDER_0_BINARY <= 3'b001; + 3 : CLK25_DIVIDER_0_BINARY <= 3'b010; + 5 : CLK25_DIVIDER_0_BINARY <= 3'b100; + 6 : CLK25_DIVIDER_0_BINARY <= 3'b101; + 10 : CLK25_DIVIDER_0_BINARY <= 3'b110; + 12 : CLK25_DIVIDER_0_BINARY <= 3'b111; + default : begin + $display("Attribute Syntax Error : The Attribute CLK25_DIVIDER_0 on %s instance %m is set to %d. Legal values for this attribute are 1 to 6, 10 and 12.", MODULE_NAME, CLK25_DIVIDER_0); + $finish; + end + endcase + + case (CLK25_DIVIDER_1) + 4 : CLK25_DIVIDER_1_BINARY <= 3'b011; + 1 : CLK25_DIVIDER_1_BINARY <= 3'b000; + 2 : CLK25_DIVIDER_1_BINARY <= 3'b001; + 3 : CLK25_DIVIDER_1_BINARY <= 3'b010; + 5 : CLK25_DIVIDER_1_BINARY <= 3'b100; + 6 : CLK25_DIVIDER_1_BINARY <= 3'b101; + 10 : CLK25_DIVIDER_1_BINARY <= 3'b110; + 12 : CLK25_DIVIDER_1_BINARY <= 3'b111; + default : begin + $display("Attribute Syntax Error : The Attribute CLK25_DIVIDER_1 on %s instance %m is set to %d. Legal values for this attribute are 1 to 6, 10 and 12.", MODULE_NAME, CLK25_DIVIDER_1); + $finish; + end + endcase + + case (CLKINDC_B_0[31:0]) + "ALSE" : CLKINDC_B_0_BINARY <= 1'b0; + "TRUE" : CLKINDC_B_0_BINARY <= 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute CLKINDC_B_0 on %s instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", MODULE_NAME, CLKINDC_B_0); + $finish; + end + endcase + + case (CLKINDC_B_1[31:0]) + "ALSE" : CLKINDC_B_1_BINARY <= 1'b0; + "TRUE" : CLKINDC_B_1_BINARY <= 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute CLKINDC_B_1 on %s instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", MODULE_NAME, CLKINDC_B_1); + $finish; + end + endcase + + case (CLKRCV_TRST_0[31:0]) + "ALSE" : CLKRCV_TRST_0_BINARY <= 1'b0; + "TRUE" : CLKRCV_TRST_0_BINARY <= 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute CLKRCV_TRST_0 on %s instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", MODULE_NAME, CLKRCV_TRST_0); + $finish; + end + endcase + + case (CLKRCV_TRST_1[31:0]) + "ALSE" : CLKRCV_TRST_1_BINARY <= 1'b0; + "TRUE" : CLKRCV_TRST_1_BINARY <= 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute CLKRCV_TRST_1 on %s instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", MODULE_NAME, CLKRCV_TRST_1); + $finish; + end + endcase + + case (CLK_CORRECT_USE_0[31:0]) + "ALSE" : CLK_CORRECT_USE_0_BINARY <= 1'b0; + "TRUE" : CLK_CORRECT_USE_0_BINARY <= 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute CLK_CORRECT_USE_0 on %s instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", MODULE_NAME, CLK_CORRECT_USE_0); + $finish; + end + endcase + + case (CLK_CORRECT_USE_1[31:0]) + "ALSE" : CLK_CORRECT_USE_1_BINARY <= 1'b0; + "TRUE" : CLK_CORRECT_USE_1_BINARY <= 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute CLK_CORRECT_USE_1 on %s instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", MODULE_NAME, CLK_CORRECT_USE_1); + $finish; + end + endcase + + case (CLK_COR_ADJ_LEN_0) + 1 : CLK_COR_ADJ_LEN_0_BINARY <= 2'b00; + 2 : CLK_COR_ADJ_LEN_0_BINARY <= 2'b01; + 4 : CLK_COR_ADJ_LEN_0_BINARY <= 2'b11; + default : begin + $display("Attribute Syntax Error : The Attribute CLK_COR_ADJ_LEN_0 on %s instance %m is set to %d. Legal values for this attribute are 1, 2 or 4.", MODULE_NAME, CLK_COR_ADJ_LEN_0); + $finish; + end + endcase + + case (CLK_COR_ADJ_LEN_1) + 1 : CLK_COR_ADJ_LEN_1_BINARY <= 2'b00; + 2 : CLK_COR_ADJ_LEN_1_BINARY <= 2'b01; + 4 : CLK_COR_ADJ_LEN_1_BINARY <= 2'b11; + default : begin + $display("Attribute Syntax Error : The Attribute CLK_COR_ADJ_LEN_1 on %s instance %m is set to %d. Legal values for this attribute are 1, 2 or 4.", MODULE_NAME, CLK_COR_ADJ_LEN_1); + $finish; + end + endcase + + case (CLK_COR_DET_LEN_0) + 1 : CLK_COR_DET_LEN_0_BINARY <= 2'b00; + 2 : CLK_COR_DET_LEN_0_BINARY <= 2'b01; + 4 : CLK_COR_DET_LEN_0_BINARY <= 2'b11; + default : begin + $display("Attribute Syntax Error : The Attribute CLK_COR_DET_LEN_0 on %s instance %m is set to %d. Legal values for this attribute are 1, 2 or 4.", MODULE_NAME, CLK_COR_DET_LEN_0); + $finish; + end + endcase + + case (CLK_COR_DET_LEN_1) + 1 : CLK_COR_DET_LEN_1_BINARY <= 2'b00; + 2 : CLK_COR_DET_LEN_1_BINARY <= 2'b01; + 4 : CLK_COR_DET_LEN_1_BINARY <= 2'b11; + default : begin + $display("Attribute Syntax Error : The Attribute CLK_COR_DET_LEN_1 on %s instance %m is set to %d. Legal values for this attribute are 1, 2 or 4.", MODULE_NAME, CLK_COR_DET_LEN_1); + $finish; + end + endcase + + case (CLK_COR_INSERT_IDLE_FLAG_0[31:0]) + "ALSE" : CLK_COR_INSERT_IDLE_FLAG_0_BINARY <= 1'b0; + "TRUE" : CLK_COR_INSERT_IDLE_FLAG_0_BINARY <= 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute CLK_COR_INSERT_IDLE_FLAG_0 on %s instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", MODULE_NAME, CLK_COR_INSERT_IDLE_FLAG_0); + $finish; + end + endcase + + case (CLK_COR_INSERT_IDLE_FLAG_1[31:0]) + "ALSE" : CLK_COR_INSERT_IDLE_FLAG_1_BINARY <= 1'b0; + "TRUE" : CLK_COR_INSERT_IDLE_FLAG_1_BINARY <= 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute CLK_COR_INSERT_IDLE_FLAG_1 on %s instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", MODULE_NAME, CLK_COR_INSERT_IDLE_FLAG_1); + $finish; + end + endcase + + case (CLK_COR_KEEP_IDLE_0[31:0]) + "ALSE" : CLK_COR_KEEP_IDLE_0_BINARY <= 1'b0; + "TRUE" : CLK_COR_KEEP_IDLE_0_BINARY <= 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute CLK_COR_KEEP_IDLE_0 on %s instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", MODULE_NAME, CLK_COR_KEEP_IDLE_0); + $finish; + end + endcase + + case (CLK_COR_KEEP_IDLE_1[31:0]) + "ALSE" : CLK_COR_KEEP_IDLE_1_BINARY <= 1'b0; + "TRUE" : CLK_COR_KEEP_IDLE_1_BINARY <= 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute CLK_COR_KEEP_IDLE_1 on %s instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", MODULE_NAME, CLK_COR_KEEP_IDLE_1); + $finish; + end + endcase + + case (CLK_COR_PRECEDENCE_0[31:0]) + "ALSE" : CLK_COR_PRECEDENCE_0_BINARY <= 1'b0; + "TRUE" : CLK_COR_PRECEDENCE_0_BINARY <= 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute CLK_COR_PRECEDENCE_0 on %s instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", MODULE_NAME, CLK_COR_PRECEDENCE_0); + $finish; + end + endcase + + case (CLK_COR_PRECEDENCE_1[31:0]) + "ALSE" : CLK_COR_PRECEDENCE_1_BINARY <= 1'b0; + "TRUE" : CLK_COR_PRECEDENCE_1_BINARY <= 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute CLK_COR_PRECEDENCE_1 on %s instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", MODULE_NAME, CLK_COR_PRECEDENCE_1); + $finish; + end + endcase + + case (CLK_COR_SEQ_2_USE_0[31:0]) + "ALSE" : CLK_COR_SEQ_2_USE_0_BINARY <= 1'b0; + "TRUE" : CLK_COR_SEQ_2_USE_0_BINARY <= 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute CLK_COR_SEQ_2_USE_0 on %s instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", MODULE_NAME, CLK_COR_SEQ_2_USE_0); + $finish; + end + endcase + + case (CLK_COR_SEQ_2_USE_1[31:0]) + "ALSE" : CLK_COR_SEQ_2_USE_1_BINARY <= 1'b0; + "TRUE" : CLK_COR_SEQ_2_USE_1_BINARY <= 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute CLK_COR_SEQ_2_USE_1 on %s instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", MODULE_NAME, CLK_COR_SEQ_2_USE_1); + $finish; + end + endcase + + case (CLK_OUT_GTP_SEL_0[71:0]) + "EFCLKPLL0" : CLK_OUT_GTP_SEL_0_BINARY <= 1'b1; + "TXOUTCLK0" : CLK_OUT_GTP_SEL_0_BINARY <= 1'b0; + default : begin + $display("Attribute Syntax Error : The Attribute CLK_OUT_GTP_SEL_0 on %s instance %m is set to %s. Legal values for this attribute are TXOUTCLK0, or REFCLKPLL0.", MODULE_NAME, CLK_OUT_GTP_SEL_0); + $finish; + end + endcase + + case (CLK_OUT_GTP_SEL_1[71:0]) + "EFCLKPLL1" : CLK_OUT_GTP_SEL_1_BINARY <= 1'b1; + "TXOUTCLK1" : CLK_OUT_GTP_SEL_1_BINARY <= 1'b0; + default : begin + $display("Attribute Syntax Error : The Attribute CLK_OUT_GTP_SEL_1 on %s instance %m is set to %s. Legal values for this attribute are TXOUTCLK1, or REFCLKPLL1.", MODULE_NAME, CLK_OUT_GTP_SEL_1); + $finish; + end + endcase + + case (DEC_MCOMMA_DETECT_0[31:0]) + "ALSE" : DEC_MCOMMA_DETECT_0_BINARY <= 1'b0; + "TRUE" : DEC_MCOMMA_DETECT_0_BINARY <= 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute DEC_MCOMMA_DETECT_0 on %s instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", MODULE_NAME, DEC_MCOMMA_DETECT_0); + $finish; + end + endcase + + case (DEC_MCOMMA_DETECT_1[31:0]) + "ALSE" : DEC_MCOMMA_DETECT_1_BINARY <= 1'b0; + "TRUE" : DEC_MCOMMA_DETECT_1_BINARY <= 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute DEC_MCOMMA_DETECT_1 on %s instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", MODULE_NAME, DEC_MCOMMA_DETECT_1); + $finish; + end + endcase + + case (DEC_PCOMMA_DETECT_0[31:0]) + "ALSE" : DEC_PCOMMA_DETECT_0_BINARY <= 1'b0; + "TRUE" : DEC_PCOMMA_DETECT_0_BINARY <= 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute DEC_PCOMMA_DETECT_0 on %s instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", MODULE_NAME, DEC_PCOMMA_DETECT_0); + $finish; + end + endcase + + case (DEC_PCOMMA_DETECT_1[31:0]) + "ALSE" : DEC_PCOMMA_DETECT_1_BINARY <= 1'b0; + "TRUE" : DEC_PCOMMA_DETECT_1_BINARY <= 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute DEC_PCOMMA_DETECT_1 on %s instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", MODULE_NAME, DEC_PCOMMA_DETECT_1); + $finish; + end + endcase + + case (DEC_VALID_COMMA_ONLY_0[31:0]) + "ALSE" : DEC_VALID_COMMA_ONLY_0_BINARY <= 1'b0; + "TRUE" : DEC_VALID_COMMA_ONLY_0_BINARY <= 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute DEC_VALID_COMMA_ONLY_0 on %s instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", MODULE_NAME, DEC_VALID_COMMA_ONLY_0); + $finish; + end + endcase + + case (DEC_VALID_COMMA_ONLY_1[31:0]) + "ALSE" : DEC_VALID_COMMA_ONLY_1_BINARY <= 1'b0; + "TRUE" : DEC_VALID_COMMA_ONLY_1_BINARY <= 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute DEC_VALID_COMMA_ONLY_1 on %s instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", MODULE_NAME, DEC_VALID_COMMA_ONLY_1); + $finish; + end + endcase + + case (GTP_CFG_PWRUP_0[31:0]) + "ALSE" : GTP_CFG_PWRUP_0_BINARY <= 1'b0; + "TRUE" : GTP_CFG_PWRUP_0_BINARY <= 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute GTP_CFG_PWRUP_0 on %s instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", MODULE_NAME, GTP_CFG_PWRUP_0); + $finish; + end + endcase + + case (GTP_CFG_PWRUP_1[31:0]) + "ALSE" : GTP_CFG_PWRUP_1_BINARY <= 1'b0; + "TRUE" : GTP_CFG_PWRUP_1_BINARY <= 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute GTP_CFG_PWRUP_1 on %s instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", MODULE_NAME, GTP_CFG_PWRUP_1); + $finish; + end + endcase + + case (MCOMMA_DETECT_0[31:0]) + "ALSE" : MCOMMA_DETECT_0_BINARY <= 1'b0; + "TRUE" : MCOMMA_DETECT_0_BINARY <= 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute MCOMMA_DETECT_0 on %s instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", MODULE_NAME, MCOMMA_DETECT_0); + $finish; + end + endcase + + case (MCOMMA_DETECT_1[31:0]) + "ALSE" : MCOMMA_DETECT_1_BINARY <= 1'b0; + "TRUE" : MCOMMA_DETECT_1_BINARY <= 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute MCOMMA_DETECT_1 on %s instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", MODULE_NAME, MCOMMA_DETECT_1); + $finish; + end + endcase + + case (OOB_CLK_DIVIDER_0) + 4 : OOB_CLK_DIVIDER_0_BINARY <= 3'b010; + 1 : OOB_CLK_DIVIDER_0_BINARY <= 3'b000; + 2 : OOB_CLK_DIVIDER_0_BINARY <= 3'b001; + 6 : OOB_CLK_DIVIDER_0_BINARY <= 3'b011; + 8 : OOB_CLK_DIVIDER_0_BINARY <= 3'b100; + 10 : OOB_CLK_DIVIDER_0_BINARY <= 3'b101; + 12 : OOB_CLK_DIVIDER_0_BINARY <= 3'b110; + 14 : OOB_CLK_DIVIDER_0_BINARY <= 3'b111; + default : begin + $display("Attribute Syntax Error : The Attribute OOB_CLK_DIVIDER_0 on %s instance %m is set to %d. Legal values for this attribute are 1, 2, 4, 6, 8, 10, 12 and 14.", MODULE_NAME, OOB_CLK_DIVIDER_0); + $finish; + end + endcase + + case (OOB_CLK_DIVIDER_1) + 4 : OOB_CLK_DIVIDER_1_BINARY <= 3'b010; + 1 : OOB_CLK_DIVIDER_1_BINARY <= 3'b000; + 2 : OOB_CLK_DIVIDER_1_BINARY <= 3'b001; + 6 : OOB_CLK_DIVIDER_1_BINARY <= 3'b011; + 8 : OOB_CLK_DIVIDER_1_BINARY <= 3'b100; + 10 : OOB_CLK_DIVIDER_1_BINARY <= 3'b101; + 12 : OOB_CLK_DIVIDER_1_BINARY <= 3'b110; + 14 : OOB_CLK_DIVIDER_1_BINARY <= 3'b111; + default : begin + $display("Attribute Syntax Error : The Attribute OOB_CLK_DIVIDER_1 on %s instance %m is set to %d. Legal values for this attribute are 1, 2, 4, 6, 8, 10, 12 and 14.", MODULE_NAME, OOB_CLK_DIVIDER_1); + $finish; + end + endcase + + case (PCI_EXPRESS_MODE_0[31:0]) + "ALSE" : PCI_EXPRESS_MODE_0_BINARY <= 1'b0; + "TRUE" : PCI_EXPRESS_MODE_0_BINARY <= 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute PCI_EXPRESS_MODE_0 on %s instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", MODULE_NAME, PCI_EXPRESS_MODE_0); + $finish; + end + endcase + + case (PCI_EXPRESS_MODE_1[31:0]) + "ALSE" : PCI_EXPRESS_MODE_1_BINARY <= 1'b0; + "TRUE" : PCI_EXPRESS_MODE_1_BINARY <= 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute PCI_EXPRESS_MODE_1 on %s instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", MODULE_NAME, PCI_EXPRESS_MODE_1); + $finish; + end + endcase + + case (PCOMMA_DETECT_0[31:0]) + "ALSE" : PCOMMA_DETECT_0_BINARY <= 1'b0; + "TRUE" : PCOMMA_DETECT_0_BINARY <= 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute PCOMMA_DETECT_0 on %s instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", MODULE_NAME, PCOMMA_DETECT_0); + $finish; + end + endcase + + case (PCOMMA_DETECT_1[31:0]) + "ALSE" : PCOMMA_DETECT_1_BINARY <= 1'b0; + "TRUE" : PCOMMA_DETECT_1_BINARY <= 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute PCOMMA_DETECT_1 on %s instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", MODULE_NAME, PCOMMA_DETECT_1); + $finish; + end + endcase + + case (PLL_DIVSEL_FB_0) + 5 : PLL_DIVSEL_FB_0_BINARY <= 5'b00011; + 1 : PLL_DIVSEL_FB_0_BINARY <= 5'b10000; + 2 : PLL_DIVSEL_FB_0_BINARY <= 5'b00000; + 3 : PLL_DIVSEL_FB_0_BINARY <= 5'b00001; + 4 : PLL_DIVSEL_FB_0_BINARY <= 5'b00010; + 8 : PLL_DIVSEL_FB_0_BINARY <= 5'b00110; + 10 : PLL_DIVSEL_FB_0_BINARY <= 5'b00111; + default : begin + $display("Attribute Syntax Error : The Attribute PLL_DIVSEL_FB_0 on %s instance %m is set to %d. Legal values for this attribute are 1 to 5, 8 and 10.", MODULE_NAME, PLL_DIVSEL_FB_0); + $finish; + end + endcase + + case (PLL_DIVSEL_FB_1) + 5 : PLL_DIVSEL_FB_1_BINARY <= 5'b00011; + 1 : PLL_DIVSEL_FB_1_BINARY <= 5'b10000; + 2 : PLL_DIVSEL_FB_1_BINARY <= 5'b00000; + 3 : PLL_DIVSEL_FB_1_BINARY <= 5'b00001; + 4 : PLL_DIVSEL_FB_1_BINARY <= 5'b00010; + 8 : PLL_DIVSEL_FB_1_BINARY <= 5'b00110; + 10 : PLL_DIVSEL_FB_1_BINARY <= 5'b00111; + default : begin + $display("Attribute Syntax Error : The Attribute PLL_DIVSEL_FB_1 on %s instance %m is set to %d. Legal values for this attribute are 1 to 5, 8 and 10.", MODULE_NAME, PLL_DIVSEL_FB_1); + $finish; + end + endcase + + case (PLL_DIVSEL_REF_0) + 2 : PLL_DIVSEL_REF_0_BINARY <= 6'b000000; + 1 : PLL_DIVSEL_REF_0_BINARY <= 6'b010000; + 3 : PLL_DIVSEL_REF_0_BINARY <= 6'b000001; + 4 : PLL_DIVSEL_REF_0_BINARY <= 6'b000010; + 5 : PLL_DIVSEL_REF_0_BINARY <= 6'b000011; + 6 : PLL_DIVSEL_REF_0_BINARY <= 6'b000101; + 8 : PLL_DIVSEL_REF_0_BINARY <= 6'b000110; + 10 : PLL_DIVSEL_REF_0_BINARY <= 6'b000111; + 12 : PLL_DIVSEL_REF_0_BINARY <= 6'b001101; + 16 : PLL_DIVSEL_REF_0_BINARY <= 6'b001110; + 20 : PLL_DIVSEL_REF_0_BINARY <= 6'b001111; + default : begin + $display("Attribute Syntax Error : The Attribute PLL_DIVSEL_REF_0 on %s instance %m is set to %d. Legal values for this attribute are 1 to 6, 8, 10, 12, 16 and 20.", MODULE_NAME, PLL_DIVSEL_REF_0); + $finish; + end + endcase + + case (PLL_DIVSEL_REF_1) + 2 : PLL_DIVSEL_REF_1_BINARY <= 6'b000000; + 1 : PLL_DIVSEL_REF_1_BINARY <= 6'b010000; + 3 : PLL_DIVSEL_REF_1_BINARY <= 6'b000001; + 4 : PLL_DIVSEL_REF_1_BINARY <= 6'b000010; + 5 : PLL_DIVSEL_REF_1_BINARY <= 6'b000011; + 6 : PLL_DIVSEL_REF_1_BINARY <= 6'b000101; + 8 : PLL_DIVSEL_REF_1_BINARY <= 6'b000110; + 10 : PLL_DIVSEL_REF_1_BINARY <= 6'b000111; + 12 : PLL_DIVSEL_REF_1_BINARY <= 6'b001101; + 16 : PLL_DIVSEL_REF_1_BINARY <= 6'b001110; + 20 : PLL_DIVSEL_REF_1_BINARY <= 6'b001111; + default : begin + $display("Attribute Syntax Error : The Attribute PLL_DIVSEL_REF_1 on %s instance %m is set to %d. Legal values for this attribute are 1 to 6, 8, 10, 12, 16 and 20.", MODULE_NAME, PLL_DIVSEL_REF_1); + $finish; + end + endcase + + case (PLL_RXDIVSEL_OUT_0) + 1 : PLL_RXDIVSEL_OUT_0_BINARY <= 2'b00; + 2 : PLL_RXDIVSEL_OUT_0_BINARY <= 2'b01; + 4 : PLL_RXDIVSEL_OUT_0_BINARY <= 2'b10; + default : begin + $display("Attribute Syntax Error : The Attribute PLL_RXDIVSEL_OUT_0 on %s instance %m is set to %d. Legal values for this attribute are 1, 2 and 4.", MODULE_NAME, PLL_RXDIVSEL_OUT_0); + $finish; + end + endcase + + case (PLL_RXDIVSEL_OUT_1) + 1 : PLL_RXDIVSEL_OUT_1_BINARY <= 2'b00; + 2 : PLL_RXDIVSEL_OUT_1_BINARY <= 2'b01; + 4 : PLL_RXDIVSEL_OUT_1_BINARY <= 2'b10; + default : begin + $display("Attribute Syntax Error : The Attribute PLL_RXDIVSEL_OUT_1 on %s instance %m is set to %d. Legal values for this attribute are 1, 2 and 4.", MODULE_NAME, PLL_RXDIVSEL_OUT_1); + $finish; + end + endcase + + case (PLL_SATA_0[31:0]) + "ALSE" : PLL_SATA_0_BINARY <= 1'b0; + "TRUE" : PLL_SATA_0_BINARY <= 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute PLL_SATA_0 on %s instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", MODULE_NAME, PLL_SATA_0); + $finish; + end + endcase + + case (PLL_SATA_1[31:0]) + "ALSE" : PLL_SATA_1_BINARY <= 1'b0; + "TRUE" : PLL_SATA_1_BINARY <= 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute PLL_SATA_1 on %s instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", MODULE_NAME, PLL_SATA_1); + $finish; + end + endcase + + case (PLL_SOURCE_0) + "PLL0" : PLL_SOURCE_0_BINARY <= 1'b0; + "PLL1" : PLL_SOURCE_0_BINARY <= 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute PLL_SOURCE_0 on %s instance %m is set to %s. Legal values for this attribute are PLL0, or PLL1.", MODULE_NAME, PLL_SOURCE_0); + $finish; + end + endcase + + case (PLL_SOURCE_1) + "PLL0" : PLL_SOURCE_1_BINARY <= 1'b0; + "PLL1" : PLL_SOURCE_1_BINARY <= 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute PLL_SOURCE_1 on %s instance %m is set to %s. Legal values for this attribute are PLL0, or PLL1.", MODULE_NAME, PLL_SOURCE_1); + $finish; + end + endcase + + case (PLL_TXDIVSEL_OUT_0) + 1 : PLL_TXDIVSEL_OUT_0_BINARY <= 2'b00; + 2 : PLL_TXDIVSEL_OUT_0_BINARY <= 2'b01; + 4 : PLL_TXDIVSEL_OUT_0_BINARY <= 2'b10; + default : begin + $display("Attribute Syntax Error : The Attribute PLL_TXDIVSEL_OUT_0 on %s instance %m is set to %d. Legal values for this attribute are 1, 2 and 4.", MODULE_NAME, PLL_TXDIVSEL_OUT_0); + $finish; + end + endcase + + case (PLL_TXDIVSEL_OUT_1) + 1 : PLL_TXDIVSEL_OUT_1_BINARY <= 2'b00; + 2 : PLL_TXDIVSEL_OUT_1_BINARY <= 2'b01; + 4 : PLL_TXDIVSEL_OUT_1_BINARY <= 2'b10; + default : begin + $display("Attribute Syntax Error : The Attribute PLL_TXDIVSEL_OUT_1 on %s instance %m is set to %d. Legal values for this attribute are 1, 2 and 4.", MODULE_NAME, PLL_TXDIVSEL_OUT_1); + $finish; + end + endcase + + case (RCV_TERM_GND_0[31:0]) + "ALSE" : RCV_TERM_GND_0_BINARY <= 1'b0; + "TRUE" : RCV_TERM_GND_0_BINARY <= 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute RCV_TERM_GND_0 on %s instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", MODULE_NAME, RCV_TERM_GND_0); + $finish; + end + endcase + + case (RCV_TERM_GND_1[31:0]) + "ALSE" : RCV_TERM_GND_1_BINARY <= 1'b0; + "TRUE" : RCV_TERM_GND_1_BINARY <= 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute RCV_TERM_GND_1 on %s instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", MODULE_NAME, RCV_TERM_GND_1); + $finish; + end + endcase + + case (RCV_TERM_VTTRX_0[31:0]) + "ALSE" : RCV_TERM_VTTRX_0_BINARY <= 1'b0; + "TRUE" : RCV_TERM_VTTRX_0_BINARY <= 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute RCV_TERM_VTTRX_0 on %s instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", MODULE_NAME, RCV_TERM_VTTRX_0); + $finish; + end + endcase + + case (RCV_TERM_VTTRX_1[31:0]) + "ALSE" : RCV_TERM_VTTRX_1_BINARY <= 1'b0; + "TRUE" : RCV_TERM_VTTRX_1_BINARY <= 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute RCV_TERM_VTTRX_1 on %s instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", MODULE_NAME, RCV_TERM_VTTRX_1); + $finish; + end + endcase + + case (RX_BUFFER_USE_0[31:0]) + "ALSE" : RX_BUFFER_USE_0_BINARY <= 1'b0; + "TRUE" : RX_BUFFER_USE_0_BINARY <= 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute RX_BUFFER_USE_0 on %s instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", MODULE_NAME, RX_BUFFER_USE_0); + $finish; + end + endcase + + case (RX_BUFFER_USE_1[31:0]) + "ALSE" : RX_BUFFER_USE_1_BINARY <= 1'b0; + "TRUE" : RX_BUFFER_USE_1_BINARY <= 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute RX_BUFFER_USE_1 on %s instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", MODULE_NAME, RX_BUFFER_USE_1); + $finish; + end + endcase + + case (RX_DECODE_SEQ_MATCH_0[31:0]) + "ALSE" : RX_DECODE_SEQ_MATCH_0_BINARY <= 1'b0; + "TRUE" : RX_DECODE_SEQ_MATCH_0_BINARY <= 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute RX_DECODE_SEQ_MATCH_0 on %s instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", MODULE_NAME, RX_DECODE_SEQ_MATCH_0); + $finish; + end + endcase + + case (RX_DECODE_SEQ_MATCH_1[31:0]) + "ALSE" : RX_DECODE_SEQ_MATCH_1_BINARY <= 1'b0; + "TRUE" : RX_DECODE_SEQ_MATCH_1_BINARY <= 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute RX_DECODE_SEQ_MATCH_1 on %s instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", MODULE_NAME, RX_DECODE_SEQ_MATCH_1); + $finish; + end + endcase + + case (RX_EN_IDLE_HOLD_CDR_0[31:0]) + "ALSE" : RX_EN_IDLE_HOLD_CDR_0_BINARY <= 1'b0; + "TRUE" : RX_EN_IDLE_HOLD_CDR_0_BINARY <= 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute RX_EN_IDLE_HOLD_CDR_0 on %s instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", MODULE_NAME, RX_EN_IDLE_HOLD_CDR_0); + $finish; + end + endcase + + case (RX_EN_IDLE_HOLD_CDR_1[31:0]) + "ALSE" : RX_EN_IDLE_HOLD_CDR_1_BINARY <= 1'b0; + "TRUE" : RX_EN_IDLE_HOLD_CDR_1_BINARY <= 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute RX_EN_IDLE_HOLD_CDR_1 on %s instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", MODULE_NAME, RX_EN_IDLE_HOLD_CDR_1); + $finish; + end + endcase + + case (RX_EN_IDLE_RESET_BUF_0[31:0]) + "ALSE" : RX_EN_IDLE_RESET_BUF_0_BINARY <= 1'b0; + "TRUE" : RX_EN_IDLE_RESET_BUF_0_BINARY <= 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute RX_EN_IDLE_RESET_BUF_0 on %s instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", MODULE_NAME, RX_EN_IDLE_RESET_BUF_0); + $finish; + end + endcase + + case (RX_EN_IDLE_RESET_BUF_1[31:0]) + "ALSE" : RX_EN_IDLE_RESET_BUF_1_BINARY <= 1'b0; + "TRUE" : RX_EN_IDLE_RESET_BUF_1_BINARY <= 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute RX_EN_IDLE_RESET_BUF_1 on %s instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", MODULE_NAME, RX_EN_IDLE_RESET_BUF_1); + $finish; + end + endcase + + case (RX_EN_IDLE_RESET_FR_0[31:0]) + "ALSE" : RX_EN_IDLE_RESET_FR_0_BINARY <= 1'b0; + "TRUE" : RX_EN_IDLE_RESET_FR_0_BINARY <= 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute RX_EN_IDLE_RESET_FR_0 on %s instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", MODULE_NAME, RX_EN_IDLE_RESET_FR_0); + $finish; + end + endcase + + case (RX_EN_IDLE_RESET_FR_1[31:0]) + "ALSE" : RX_EN_IDLE_RESET_FR_1_BINARY <= 1'b0; + "TRUE" : RX_EN_IDLE_RESET_FR_1_BINARY <= 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute RX_EN_IDLE_RESET_FR_1 on %s instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", MODULE_NAME, RX_EN_IDLE_RESET_FR_1); + $finish; + end + endcase + + case (RX_EN_IDLE_RESET_PH_0[31:0]) + "ALSE" : RX_EN_IDLE_RESET_PH_0_BINARY <= 1'b0; + "TRUE" : RX_EN_IDLE_RESET_PH_0_BINARY <= 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute RX_EN_IDLE_RESET_PH_0 on %s instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", MODULE_NAME, RX_EN_IDLE_RESET_PH_0); + $finish; + end + endcase + + case (RX_EN_IDLE_RESET_PH_1[31:0]) + "ALSE" : RX_EN_IDLE_RESET_PH_1_BINARY <= 1'b0; + "TRUE" : RX_EN_IDLE_RESET_PH_1_BINARY <= 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute RX_EN_IDLE_RESET_PH_1 on %s instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", MODULE_NAME, RX_EN_IDLE_RESET_PH_1); + $finish; + end + endcase + + case (RX_EN_MODE_RESET_BUF_0[31:0]) + "ALSE" : RX_EN_MODE_RESET_BUF_0_BINARY <= 1'b0; + "TRUE" : RX_EN_MODE_RESET_BUF_0_BINARY <= 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute RX_EN_MODE_RESET_BUF_0 on %s instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", MODULE_NAME, RX_EN_MODE_RESET_BUF_0); + $finish; + end + endcase + + case (RX_EN_MODE_RESET_BUF_1[31:0]) + "ALSE" : RX_EN_MODE_RESET_BUF_1_BINARY <= 1'b0; + "TRUE" : RX_EN_MODE_RESET_BUF_1_BINARY <= 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute RX_EN_MODE_RESET_BUF_1 on %s instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", MODULE_NAME, RX_EN_MODE_RESET_BUF_1); + $finish; + end + endcase + + case (RX_LOSS_OF_SYNC_FSM_0[31:0]) + "ALSE" : RX_LOSS_OF_SYNC_FSM_0_BINARY <= 1'b0; + "TRUE" : RX_LOSS_OF_SYNC_FSM_0_BINARY <= 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute RX_LOSS_OF_SYNC_FSM_0 on %s instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", MODULE_NAME, RX_LOSS_OF_SYNC_FSM_0); + $finish; + end + endcase + + case (RX_LOSS_OF_SYNC_FSM_1[31:0]) + "ALSE" : RX_LOSS_OF_SYNC_FSM_1_BINARY <= 1'b0; + "TRUE" : RX_LOSS_OF_SYNC_FSM_1_BINARY <= 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute RX_LOSS_OF_SYNC_FSM_1 on %s instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", MODULE_NAME, RX_LOSS_OF_SYNC_FSM_1); + $finish; + end + endcase + + case (RX_LOS_INVALID_INCR_0) + 1 : RX_LOS_INVALID_INCR_0_BINARY <= 3'b000; + 2 : RX_LOS_INVALID_INCR_0_BINARY <= 3'b001; + 4 : RX_LOS_INVALID_INCR_0_BINARY <= 3'b010; + 8 : RX_LOS_INVALID_INCR_0_BINARY <= 3'b011; + 16 : RX_LOS_INVALID_INCR_0_BINARY <= 3'b100; + 32 : RX_LOS_INVALID_INCR_0_BINARY <= 3'b101; + 64 : RX_LOS_INVALID_INCR_0_BINARY <= 3'b110; + 128 : RX_LOS_INVALID_INCR_0_BINARY <= 3'b111; + default : begin + $display("Attribute Syntax Error : The Attribute RX_LOS_INVALID_INCR_0 on %s instance %m is set to %d. Legal values for this attribute are 1, 2, 4, 8, 16, 32, 64 and 128.", MODULE_NAME, RX_LOS_INVALID_INCR_0); + $finish; + end + endcase + + case (RX_LOS_INVALID_INCR_1) + 1 : RX_LOS_INVALID_INCR_1_BINARY <= 3'b000; + 2 : RX_LOS_INVALID_INCR_1_BINARY <= 3'b001; + 4 : RX_LOS_INVALID_INCR_1_BINARY <= 3'b010; + 8 : RX_LOS_INVALID_INCR_1_BINARY <= 3'b011; + 16 : RX_LOS_INVALID_INCR_1_BINARY <= 3'b100; + 32 : RX_LOS_INVALID_INCR_1_BINARY <= 3'b101; + 64 : RX_LOS_INVALID_INCR_1_BINARY <= 3'b110; + 128 : RX_LOS_INVALID_INCR_1_BINARY <= 3'b111; + default : begin + $display("Attribute Syntax Error : The Attribute RX_LOS_INVALID_INCR_1 on %s instance %m is set to %d. Legal values for this attribute are 1, 2, 4, 8, 16, 32, 64 and 128.", MODULE_NAME, RX_LOS_INVALID_INCR_1); + $finish; + end + endcase + + case (RX_LOS_THRESHOLD_0) + 4 : RX_LOS_THRESHOLD_0_BINARY <= 3'b000; + 8 : RX_LOS_THRESHOLD_0_BINARY <= 3'b001; + 16 : RX_LOS_THRESHOLD_0_BINARY <= 3'b010; + 32 : RX_LOS_THRESHOLD_0_BINARY <= 3'b011; + 64 : RX_LOS_THRESHOLD_0_BINARY <= 3'b100; + 128 : RX_LOS_THRESHOLD_0_BINARY <= 3'b101; + 256 : RX_LOS_THRESHOLD_0_BINARY <= 3'b110; + 512 : RX_LOS_THRESHOLD_0_BINARY <= 3'b111; + default : begin + $display("Attribute Syntax Error : The Attribute RX_LOS_THRESHOLD_0 on %s instance %m is set to %d. Legal values for this attribute are 4, 8, 16, 32, 64, 128, 256 and 512.", MODULE_NAME, RX_LOS_THRESHOLD_0); + $finish; + end + endcase + + case (RX_LOS_THRESHOLD_1) + 4 : RX_LOS_THRESHOLD_1_BINARY <= 3'b000; + 8 : RX_LOS_THRESHOLD_1_BINARY <= 3'b001; + 16 : RX_LOS_THRESHOLD_1_BINARY <= 3'b010; + 32 : RX_LOS_THRESHOLD_1_BINARY <= 3'b011; + 64 : RX_LOS_THRESHOLD_1_BINARY <= 3'b100; + 128 : RX_LOS_THRESHOLD_1_BINARY <= 3'b101; + 256 : RX_LOS_THRESHOLD_1_BINARY <= 3'b110; + 512 : RX_LOS_THRESHOLD_1_BINARY <= 3'b111; + default : begin + $display("Attribute Syntax Error : The Attribute RX_LOS_THRESHOLD_1 on %s instance %m is set to %d. Legal values for this attribute are 4, 8, 16, 32, 64, 128, 256 and 512.", MODULE_NAME, RX_LOS_THRESHOLD_1); + $finish; + end + endcase + + case (RX_SLIDE_MODE_0) + "PCS" : RX_SLIDE_MODE_0_BINARY <= 1'b0; + "PMA" : RX_SLIDE_MODE_0_BINARY <= 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute RX_SLIDE_MODE_0 on %s instance %m is set to %s. Legal values for this attribute are PCS, or PMA.", MODULE_NAME, RX_SLIDE_MODE_0); + $finish; + end + endcase + + case (RX_SLIDE_MODE_1) + "PCS" : RX_SLIDE_MODE_1_BINARY <= 1'b0; + "PMA" : RX_SLIDE_MODE_1_BINARY <= 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute RX_SLIDE_MODE_1 on %s instance %m is set to %s. Legal values for this attribute are PCS, or PMA.", MODULE_NAME, RX_SLIDE_MODE_1); + $finish; + end + endcase + + case (RX_STATUS_FMT_0) + "PCIE" : RX_STATUS_FMT_0_BINARY <= 1'b0; + "SATA" : RX_STATUS_FMT_0_BINARY <= 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute RX_STATUS_FMT_0 on %s instance %m is set to %s. Legal values for this attribute are PCIE, or SATA.", MODULE_NAME, RX_STATUS_FMT_0); + $finish; + end + endcase + + case (RX_STATUS_FMT_1) + "PCIE" : RX_STATUS_FMT_1_BINARY <= 1'b0; + "SATA" : RX_STATUS_FMT_1_BINARY <= 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute RX_STATUS_FMT_1 on %s instance %m is set to %s. Legal values for this attribute are PCIE, or SATA.", MODULE_NAME, RX_STATUS_FMT_1); + $finish; + end + endcase + + case (RX_XCLK_SEL_0) + "RXREC" : RX_XCLK_SEL_0_BINARY <= 1'b0; + "RXUSR" : RX_XCLK_SEL_0_BINARY <= 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute RX_XCLK_SEL_0 on %s instance %m is set to %s. Legal values for this attribute are RXREC, or RXUSR.", MODULE_NAME, RX_XCLK_SEL_0); + $finish; + end + endcase + + case (RX_XCLK_SEL_1) + "RXREC" : RX_XCLK_SEL_1_BINARY <= 1'b0; + "RXUSR" : RX_XCLK_SEL_1_BINARY <= 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute RX_XCLK_SEL_1 on %s instance %m is set to %s. Legal values for this attribute are RXREC, or RXUSR.", MODULE_NAME, RX_XCLK_SEL_1); + $finish; + end + endcase + + case (SIM_GTPRESET_SPEEDUP) + 0 : SIM_GTPRESET_SPEEDUP_BINARY <= 1'b0; + 1 : SIM_GTPRESET_SPEEDUP_BINARY <= 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute SIM_GTPRESET_SPEEDUP on %s instance %m is set to %d. Legal values for this attribute are 0 to 1.", MODULE_NAME, SIM_GTPRESET_SPEEDUP, 0); + $finish; + end + endcase + + case (SIM_RECEIVER_DETECT_PASS[31:0]) + "ALSE" : SIM_RECEIVER_DETECT_PASS_BINARY <= 1'b0; + "TRUE" : SIM_RECEIVER_DETECT_PASS_BINARY <= 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute SIM_RECEIVER_DETECT_PASS on %s instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", MODULE_NAME, SIM_RECEIVER_DETECT_PASS); + $finish; + end + endcase + + case (SIM_TX_ELEC_IDLE_LEVEL) + "X" : SIM_TX_ELEC_IDLE_LEVEL_BINARY <= 0; + "0" : SIM_TX_ELEC_IDLE_LEVEL_BINARY <= 0; + "1" : SIM_TX_ELEC_IDLE_LEVEL_BINARY <= 0; + "Z" : SIM_TX_ELEC_IDLE_LEVEL_BINARY <= 0; + default : begin + $display("Attribute Syntax Error : The Attribute SIM_TX_ELEC_IDLE_LEVEL on %s instance %m is set to %s. Legal values for this attribute are X, 0, 1, or Z.", MODULE_NAME, SIM_TX_ELEC_IDLE_LEVEL); + $finish; + end + endcase + + case (SIM_VERSION) + "2.0" : SIM_VERSION_BINARY <= 0; + "1.0" : SIM_VERSION_BINARY <= 0; + default : begin + $display("Attribute Syntax Error : The Attribute SIM_VERSION on %s instance %m is set to %s. Legal values for this attribute are 0.0, 1.0 or 2.0.", MODULE_NAME, SIM_VERSION); + $finish; + end + endcase + + case (TERMINATION_OVRD_0[31:0]) + "ALSE" : TERMINATION_OVRD_0_BINARY <= 1'b0; + "TRUE" : TERMINATION_OVRD_0_BINARY <= 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute TERMINATION_OVRD_0 on %s instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", MODULE_NAME, TERMINATION_OVRD_0); + $finish; + end + endcase + + case (TERMINATION_OVRD_1[31:0]) + "ALSE" : TERMINATION_OVRD_1_BINARY <= 1'b0; + "TRUE" : TERMINATION_OVRD_1_BINARY <= 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute TERMINATION_OVRD_1 on %s instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", MODULE_NAME, TERMINATION_OVRD_1); + $finish; + end + endcase + + case (TX_BUFFER_USE_0[31:0]) + "ALSE" : TX_BUFFER_USE_0_BINARY <= 1'b0; + "TRUE" : TX_BUFFER_USE_0_BINARY <= 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute TX_BUFFER_USE_0 on %s instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", MODULE_NAME, TX_BUFFER_USE_0); + $finish; + end + endcase + + case (TX_BUFFER_USE_1[31:0]) + "ALSE" : TX_BUFFER_USE_1_BINARY <= 1'b0; + "TRUE" : TX_BUFFER_USE_1_BINARY <= 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute TX_BUFFER_USE_1 on %s instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", MODULE_NAME, TX_BUFFER_USE_1); + $finish; + end + endcase + + case (TX_XCLK_SEL_0) + "TXUSR" : TX_XCLK_SEL_0_BINARY <= 1'b1; + "TXOUT" : TX_XCLK_SEL_0_BINARY <= 1'b0; + default : begin + $display("Attribute Syntax Error : The Attribute TX_XCLK_SEL_0 on %s instance %m is set to %s. Legal values for this attribute are TXUSR, or TXOUT.", MODULE_NAME, TX_XCLK_SEL_0); + $finish; + end + endcase + + case (TX_XCLK_SEL_1) + "TXUSR" : TX_XCLK_SEL_1_BINARY <= 1'b1; + "TXOUT" : TX_XCLK_SEL_1_BINARY <= 1'b0; + default : begin + $display("Attribute Syntax Error : The Attribute TX_XCLK_SEL_1 on %s instance %m is set to %s. Legal values for this attribute are TXUSR, or TXOUT.", MODULE_NAME, TX_XCLK_SEL_1); + $finish; + end + endcase + + if ((CB2_INH_CC_PERIOD_0 >= 0) && (CB2_INH_CC_PERIOD_0 <= 15)) + CB2_INH_CC_PERIOD_0_BINARY <= CB2_INH_CC_PERIOD_0; + else begin + $display("Attribute Syntax Error : The Attribute CB2_INH_CC_PERIOD_0 on %s instance %m is set to %d. Legal values for this attribute are 0 to 15.", MODULE_NAME, CB2_INH_CC_PERIOD_0); + $finish; + end + + if ((CB2_INH_CC_PERIOD_1 >= 0) && (CB2_INH_CC_PERIOD_1 <= 15)) + CB2_INH_CC_PERIOD_1_BINARY <= CB2_INH_CC_PERIOD_1; + else begin + $display("Attribute Syntax Error : The Attribute CB2_INH_CC_PERIOD_1 on %s instance %m is set to %d. Legal values for this attribute are 0 to 15.", MODULE_NAME, CB2_INH_CC_PERIOD_1); + $finish; + end + + if ((CDR_PH_ADJ_TIME_0 >= 0) && (CDR_PH_ADJ_TIME_0 <= 31)) + CDR_PH_ADJ_TIME_0_BINARY <= CDR_PH_ADJ_TIME_0; + else begin + $display("Attribute Syntax Error : The Attribute CDR_PH_ADJ_TIME_0 on %s instance %m is set to %d. Legal values for this attribute are 0 to 31.", MODULE_NAME, CDR_PH_ADJ_TIME_0); + $finish; + end + + if ((CDR_PH_ADJ_TIME_1 >= 0) && (CDR_PH_ADJ_TIME_1 <= 31)) + CDR_PH_ADJ_TIME_1_BINARY <= CDR_PH_ADJ_TIME_1; + else begin + $display("Attribute Syntax Error : The Attribute CDR_PH_ADJ_TIME_1 on %s instance %m is set to %d. Legal values for this attribute are 0 to 31.", MODULE_NAME, CDR_PH_ADJ_TIME_1); + $finish; + end + + if ((CHAN_BOND_1_MAX_SKEW_0 >= 1) && (CHAN_BOND_1_MAX_SKEW_0 <= 14)) + CHAN_BOND_1_MAX_SKEW_0_BINARY <= CHAN_BOND_1_MAX_SKEW_0; + else begin + $display("Attribute Syntax Error : The Attribute CHAN_BOND_1_MAX_SKEW_0 on %s instance %m is set to %d. Legal values for this attribute are 1 to 14.", MODULE_NAME, CHAN_BOND_1_MAX_SKEW_0); + $finish; + end + + if ((CHAN_BOND_1_MAX_SKEW_1 >= 1) && (CHAN_BOND_1_MAX_SKEW_1 <= 14)) + CHAN_BOND_1_MAX_SKEW_1_BINARY <= CHAN_BOND_1_MAX_SKEW_1; + else begin + $display("Attribute Syntax Error : The Attribute CHAN_BOND_1_MAX_SKEW_1 on %s instance %m is set to %d. Legal values for this attribute are 1 to 14.", MODULE_NAME, CHAN_BOND_1_MAX_SKEW_1); + $finish; + end + + if ((CHAN_BOND_2_MAX_SKEW_0 >= 1) && (CHAN_BOND_2_MAX_SKEW_0 <= 14)) + CHAN_BOND_2_MAX_SKEW_0_BINARY <= CHAN_BOND_2_MAX_SKEW_0; + else begin + $display("Attribute Syntax Error : The Attribute CHAN_BOND_2_MAX_SKEW_0 on %s instance %m is set to %d. Legal values for this attribute are 1 to 14.", MODULE_NAME, CHAN_BOND_2_MAX_SKEW_0); + $finish; + end + + if ((CHAN_BOND_2_MAX_SKEW_1 >= 1) && (CHAN_BOND_2_MAX_SKEW_1 <= 14)) + CHAN_BOND_2_MAX_SKEW_1_BINARY <= CHAN_BOND_2_MAX_SKEW_1; + else begin + $display("Attribute Syntax Error : The Attribute CHAN_BOND_2_MAX_SKEW_1 on %s instance %m is set to %d. Legal values for this attribute are 1 to 14.", MODULE_NAME, CHAN_BOND_2_MAX_SKEW_1); + $finish; + end + + if (CHAN_BOND_2_MAX_SKEW_0 > CHAN_BOND_1_MAX_SKEW_0) begin + $display("DRC Error : The value of CHAN_BOND_2_MAX_SKEW_0 is set to %d. This value must be less than or equal to the value of CHAN_BOND_1_MAX_SKEW_0 %d for instance %m of %s.", MODULE_NAME,CHAN_BOND_2_MAX_SKEW_0, CHAN_BOND_1_MAX_SKEW_0); + $finish; + end + + if (CHAN_BOND_2_MAX_SKEW_1 > CHAN_BOND_1_MAX_SKEW_1) begin + $display("DRC Error : The value of CHAN_BOND_2_MAX_SKEW_1 is set to %d. This value must be less than or equal to the value of CHAN_BOND_1_MAX_SKEW_1 %d for instance %m of %s.", MODULE_NAME,CHAN_BOND_2_MAX_SKEW_1, CHAN_BOND_1_MAX_SKEW_1); + $finish; + end + + if ((CHAN_BOND_SEQ_1_1_0 >= 0) && (CHAN_BOND_SEQ_1_1_0 <= 1023)) + CHAN_BOND_SEQ_1_1_0_BINARY <= CHAN_BOND_SEQ_1_1_0; + else begin + $display("Attribute Syntax Error : The Attribute CHAN_BOND_SEQ_1_1_0 on %s instance %m is set to %d. Legal values for this attribute are 0 to 1023.", MODULE_NAME, CHAN_BOND_SEQ_1_1_0); + $finish; + end + + if ((CHAN_BOND_SEQ_1_1_1 >= 0) && (CHAN_BOND_SEQ_1_1_1 <= 1023)) + CHAN_BOND_SEQ_1_1_1_BINARY <= CHAN_BOND_SEQ_1_1_1; + else begin + $display("Attribute Syntax Error : The Attribute CHAN_BOND_SEQ_1_1_1 on %s instance %m is set to %d. Legal values for this attribute are 0 to 1023.", MODULE_NAME, CHAN_BOND_SEQ_1_1_1); + $finish; + end + + if ((CHAN_BOND_SEQ_1_2_0 >= 0) && (CHAN_BOND_SEQ_1_2_0 <= 1023)) + CHAN_BOND_SEQ_1_2_0_BINARY <= CHAN_BOND_SEQ_1_2_0; + else begin + $display("Attribute Syntax Error : The Attribute CHAN_BOND_SEQ_1_2_0 on %s instance %m is set to %d. Legal values for this attribute are 0 to 1023.", MODULE_NAME, CHAN_BOND_SEQ_1_2_0); + $finish; + end + + if ((CHAN_BOND_SEQ_1_2_1 >= 0) && (CHAN_BOND_SEQ_1_2_1 <= 1023)) + CHAN_BOND_SEQ_1_2_1_BINARY <= CHAN_BOND_SEQ_1_2_1; + else begin + $display("Attribute Syntax Error : The Attribute CHAN_BOND_SEQ_1_2_1 on %s instance %m is set to %d. Legal values for this attribute are 0 to 1023.", MODULE_NAME, CHAN_BOND_SEQ_1_2_1); + $finish; + end + + if ((CHAN_BOND_SEQ_1_3_0 >= 0) && (CHAN_BOND_SEQ_1_3_0 <= 1023)) + CHAN_BOND_SEQ_1_3_0_BINARY <= CHAN_BOND_SEQ_1_3_0; + else begin + $display("Attribute Syntax Error : The Attribute CHAN_BOND_SEQ_1_3_0 on %s instance %m is set to %d. Legal values for this attribute are 0 to 1023.", MODULE_NAME, CHAN_BOND_SEQ_1_3_0); + $finish; + end + + if ((CHAN_BOND_SEQ_1_3_1 >= 0) && (CHAN_BOND_SEQ_1_3_1 <= 1023)) + CHAN_BOND_SEQ_1_3_1_BINARY <= CHAN_BOND_SEQ_1_3_1; + else begin + $display("Attribute Syntax Error : The Attribute CHAN_BOND_SEQ_1_3_1 on %s instance %m is set to %d. Legal values for this attribute are 0 to 1023.", MODULE_NAME, CHAN_BOND_SEQ_1_3_1); + $finish; + end + + if ((CHAN_BOND_SEQ_1_4_0 >= 0) && (CHAN_BOND_SEQ_1_4_0 <= 1023)) + CHAN_BOND_SEQ_1_4_0_BINARY <= CHAN_BOND_SEQ_1_4_0; + else begin + $display("Attribute Syntax Error : The Attribute CHAN_BOND_SEQ_1_4_0 on %s instance %m is set to %d. Legal values for this attribute are 0 to 1023.", MODULE_NAME, CHAN_BOND_SEQ_1_4_0); + $finish; + end + + if ((CHAN_BOND_SEQ_1_4_1 >= 0) && (CHAN_BOND_SEQ_1_4_1 <= 1023)) + CHAN_BOND_SEQ_1_4_1_BINARY <= CHAN_BOND_SEQ_1_4_1; + else begin + $display("Attribute Syntax Error : The Attribute CHAN_BOND_SEQ_1_4_1 on %s instance %m is set to %d. Legal values for this attribute are 0 to 1023.", MODULE_NAME, CHAN_BOND_SEQ_1_4_1); + $finish; + end + + if ((CHAN_BOND_SEQ_1_ENABLE_0 >= 0) && (CHAN_BOND_SEQ_1_ENABLE_0 <= 15)) + CHAN_BOND_SEQ_1_ENABLE_0_BINARY <= CHAN_BOND_SEQ_1_ENABLE_0; + else begin + $display("Attribute Syntax Error : The Attribute CHAN_BOND_SEQ_1_ENABLE_0 on %s instance %m is set to %d. Legal values for this attribute are 0 to 15.", MODULE_NAME, CHAN_BOND_SEQ_1_ENABLE_0); + $finish; + end + + if ((CHAN_BOND_SEQ_1_ENABLE_1 >= 0) && (CHAN_BOND_SEQ_1_ENABLE_1 <= 15)) + CHAN_BOND_SEQ_1_ENABLE_1_BINARY <= CHAN_BOND_SEQ_1_ENABLE_1; + else begin + $display("Attribute Syntax Error : The Attribute CHAN_BOND_SEQ_1_ENABLE_1 on %s instance %m is set to %d. Legal values for this attribute are 0 to 15.", MODULE_NAME, CHAN_BOND_SEQ_1_ENABLE_1); + $finish; + end + + if ((CHAN_BOND_SEQ_2_1_0 >= 0) && (CHAN_BOND_SEQ_2_1_0 <= 1023)) + CHAN_BOND_SEQ_2_1_0_BINARY <= CHAN_BOND_SEQ_2_1_0; + else begin + $display("Attribute Syntax Error : The Attribute CHAN_BOND_SEQ_2_1_0 on %s instance %m is set to %d. Legal values for this attribute are 0 to 1023.", MODULE_NAME, CHAN_BOND_SEQ_2_1_0); + $finish; + end + + if ((CHAN_BOND_SEQ_2_1_1 >= 0) && (CHAN_BOND_SEQ_2_1_1 <= 1023)) + CHAN_BOND_SEQ_2_1_1_BINARY <= CHAN_BOND_SEQ_2_1_1; + else begin + $display("Attribute Syntax Error : The Attribute CHAN_BOND_SEQ_2_1_1 on %s instance %m is set to %d. Legal values for this attribute are 0 to 1023.", MODULE_NAME, CHAN_BOND_SEQ_2_1_1); + $finish; + end + + if ((CHAN_BOND_SEQ_2_2_0 >= 0) && (CHAN_BOND_SEQ_2_2_0 <= 1023)) + CHAN_BOND_SEQ_2_2_0_BINARY <= CHAN_BOND_SEQ_2_2_0; + else begin + $display("Attribute Syntax Error : The Attribute CHAN_BOND_SEQ_2_2_0 on %s instance %m is set to %d. Legal values for this attribute are 0 to 1023.", MODULE_NAME, CHAN_BOND_SEQ_2_2_0); + $finish; + end + + if ((CHAN_BOND_SEQ_2_2_1 >= 0) && (CHAN_BOND_SEQ_2_2_1 <= 1023)) + CHAN_BOND_SEQ_2_2_1_BINARY <= CHAN_BOND_SEQ_2_2_1; + else begin + $display("Attribute Syntax Error : The Attribute CHAN_BOND_SEQ_2_2_1 on %s instance %m is set to %d. Legal values for this attribute are 0 to 1023.", MODULE_NAME, CHAN_BOND_SEQ_2_2_1); + $finish; + end + + if ((CHAN_BOND_SEQ_2_3_0 >= 0) && (CHAN_BOND_SEQ_2_3_0 <= 1023)) + CHAN_BOND_SEQ_2_3_0_BINARY <= CHAN_BOND_SEQ_2_3_0; + else begin + $display("Attribute Syntax Error : The Attribute CHAN_BOND_SEQ_2_3_0 on %s instance %m is set to %d. Legal values for this attribute are 0 to 1023.", MODULE_NAME, CHAN_BOND_SEQ_2_3_0); + $finish; + end + + if ((CHAN_BOND_SEQ_2_3_1 >= 0) && (CHAN_BOND_SEQ_2_3_1 <= 1023)) + CHAN_BOND_SEQ_2_3_1_BINARY <= CHAN_BOND_SEQ_2_3_1; + else begin + $display("Attribute Syntax Error : The Attribute CHAN_BOND_SEQ_2_3_1 on %s instance %m is set to %d. Legal values for this attribute are 0 to 1023.", MODULE_NAME, CHAN_BOND_SEQ_2_3_1); + $finish; + end + + if ((CHAN_BOND_SEQ_2_4_0 >= 0) && (CHAN_BOND_SEQ_2_4_0 <= 1023)) + CHAN_BOND_SEQ_2_4_0_BINARY <= CHAN_BOND_SEQ_2_4_0; + else begin + $display("Attribute Syntax Error : The Attribute CHAN_BOND_SEQ_2_4_0 on %s instance %m is set to %d. Legal values for this attribute are 0 to 1023.", MODULE_NAME, CHAN_BOND_SEQ_2_4_0); + $finish; + end + + if ((CHAN_BOND_SEQ_2_4_1 >= 0) && (CHAN_BOND_SEQ_2_4_1 <= 1023)) + CHAN_BOND_SEQ_2_4_1_BINARY <= CHAN_BOND_SEQ_2_4_1; + else begin + $display("Attribute Syntax Error : The Attribute CHAN_BOND_SEQ_2_4_1 on %s instance %m is set to %d. Legal values for this attribute are 0 to 1023.", MODULE_NAME, CHAN_BOND_SEQ_2_4_1); + $finish; + end + + if ((CHAN_BOND_SEQ_2_ENABLE_0 >= 0) && (CHAN_BOND_SEQ_2_ENABLE_0 <= 15)) + CHAN_BOND_SEQ_2_ENABLE_0_BINARY <= CHAN_BOND_SEQ_2_ENABLE_0; + else begin + $display("Attribute Syntax Error : The Attribute CHAN_BOND_SEQ_2_ENABLE_0 on %s instance %m is set to %d. Legal values for this attribute are 0 to 15.", MODULE_NAME, CHAN_BOND_SEQ_2_ENABLE_0); + $finish; + end + + if ((CHAN_BOND_SEQ_2_ENABLE_1 >= 0) && (CHAN_BOND_SEQ_2_ENABLE_1 <= 15)) + CHAN_BOND_SEQ_2_ENABLE_1_BINARY <= CHAN_BOND_SEQ_2_ENABLE_1; + else begin + $display("Attribute Syntax Error : The Attribute CHAN_BOND_SEQ_2_ENABLE_1 on %s instance %m is set to %d. Legal values for this attribute are 0 to 15.", MODULE_NAME, CHAN_BOND_SEQ_2_ENABLE_1); + $finish; + end + + if ((CLK_COR_MAX_LAT_0 >= 3) && (CLK_COR_MAX_LAT_0 <= 48)) + CLK_COR_MAX_LAT_0_BINARY <= CLK_COR_MAX_LAT_0; + else begin + $display("Attribute Syntax Error : The Attribute CLK_COR_MAX_LAT_0 on %s instance %m is set to %d. Legal values for this attribute are 3 to 48.", MODULE_NAME, CLK_COR_MAX_LAT_0); + $finish; + end + + if ((CLK_COR_MAX_LAT_1 >= 3) && (CLK_COR_MAX_LAT_1 <= 48)) + CLK_COR_MAX_LAT_1_BINARY <= CLK_COR_MAX_LAT_1; + else begin + $display("Attribute Syntax Error : The Attribute CLK_COR_MAX_LAT_1 on %s instance %m is set to %d. Legal values for this attribute are 3 to 48.", MODULE_NAME, CLK_COR_MAX_LAT_1); + $finish; + end + + if (CLK_COR_MIN_LAT_0 > CLK_COR_MAX_LAT_0) begin + $display("DRC Error : The value of CLK_COR_MIN_LAT_0 is set to %d. This value must be less than or equal to the value of CLK_COR_MAX_LAT_0 %d for instance %m of %s.", MODULE_NAME,CLK_COR_MIN_LAT_0, CLK_COR_MAX_LAT_0); + $finish; + end + + if (CLK_COR_MIN_LAT_1 > CLK_COR_MAX_LAT_1) begin + $display("DRC Error : The value of CLK_COR_MIN_LAT_1 is set to %d. This value must be less than or equal to the value of CLK_COR_MAX_LAT_1 %d for instance %m of %s.", MODULE_NAME,CLK_COR_MIN_LAT_1, CLK_COR_MAX_LAT_1); + $finish; + end + + if ((CLK_COR_MIN_LAT_0 >= 3) && (CLK_COR_MIN_LAT_0 <= 48)) + CLK_COR_MIN_LAT_0_BINARY <= CLK_COR_MIN_LAT_0; + else begin + $display("Attribute Syntax Error : The Attribute CLK_COR_MIN_LAT_0 on %s instance %m is set to %d. Legal values for this attribute are 3 to 48.", MODULE_NAME, CLK_COR_MIN_LAT_0); + $finish; + end + + if ((CLK_COR_MIN_LAT_1 >= 3) && (CLK_COR_MIN_LAT_1 <= 48)) + CLK_COR_MIN_LAT_1_BINARY <= CLK_COR_MIN_LAT_1; + else begin + $display("Attribute Syntax Error : The Attribute CLK_COR_MIN_LAT_1 on %s instance %m is set to %d. Legal values for this attribute are 3 to 48.", MODULE_NAME, CLK_COR_MIN_LAT_1); + $finish; + end + + if ((CLK_COR_REPEAT_WAIT_0 >= 0) && (CLK_COR_REPEAT_WAIT_0 <= 31)) + CLK_COR_REPEAT_WAIT_0_BINARY <= CLK_COR_REPEAT_WAIT_0; + else begin + $display("Attribute Syntax Error : The Attribute CLK_COR_REPEAT_WAIT_0 on %s instance %m is set to %d. Legal values for this attribute are 0 to 31.", MODULE_NAME, CLK_COR_REPEAT_WAIT_0); + $finish; + end + + if ((CLK_COR_REPEAT_WAIT_1 >= 0) && (CLK_COR_REPEAT_WAIT_1 <= 31)) + CLK_COR_REPEAT_WAIT_1_BINARY <= CLK_COR_REPEAT_WAIT_1; + else begin + $display("Attribute Syntax Error : The Attribute CLK_COR_REPEAT_WAIT_1 on %s instance %m is set to %d. Legal values for this attribute are 0 to 31.", MODULE_NAME, CLK_COR_REPEAT_WAIT_1); + $finish; + end + + if ((CLK_COR_SEQ_1_1_0 >= 0) && (CLK_COR_SEQ_1_1_0 <= 1023)) + CLK_COR_SEQ_1_1_0_BINARY <= CLK_COR_SEQ_1_1_0; + else begin + $display("Attribute Syntax Error : The Attribute CLK_COR_SEQ_1_1_0 on %s instance %m is set to %d. Legal values for this attribute are 0 to 1023.", MODULE_NAME, CLK_COR_SEQ_1_1_0); + $finish; + end + + if ((CLK_COR_SEQ_1_1_1 >= 0) && (CLK_COR_SEQ_1_1_1 <= 1023)) + CLK_COR_SEQ_1_1_1_BINARY <= CLK_COR_SEQ_1_1_1; + else begin + $display("Attribute Syntax Error : The Attribute CLK_COR_SEQ_1_1_1 on %s instance %m is set to %d. Legal values for this attribute are 0 to 1023.", MODULE_NAME, CLK_COR_SEQ_1_1_1); + $finish; + end + + if ((CLK_COR_SEQ_1_2_0 >= 0) && (CLK_COR_SEQ_1_2_0 <= 1023)) + CLK_COR_SEQ_1_2_0_BINARY <= CLK_COR_SEQ_1_2_0; + else begin + $display("Attribute Syntax Error : The Attribute CLK_COR_SEQ_1_2_0 on %s instance %m is set to %d. Legal values for this attribute are 0 to 1023.", MODULE_NAME, CLK_COR_SEQ_1_2_0); + $finish; + end + + if ((CLK_COR_SEQ_1_2_1 >= 0) && (CLK_COR_SEQ_1_2_1 <= 1023)) + CLK_COR_SEQ_1_2_1_BINARY <= CLK_COR_SEQ_1_2_1; + else begin + $display("Attribute Syntax Error : The Attribute CLK_COR_SEQ_1_2_1 on %s instance %m is set to %d. Legal values for this attribute are 0 to 1023.", MODULE_NAME, CLK_COR_SEQ_1_2_1); + $finish; + end + + if ((CLK_COR_SEQ_1_3_0 >= 0) && (CLK_COR_SEQ_1_3_0 <= 1023)) + CLK_COR_SEQ_1_3_0_BINARY <= CLK_COR_SEQ_1_3_0; + else begin + $display("Attribute Syntax Error : The Attribute CLK_COR_SEQ_1_3_0 on %s instance %m is set to %d. Legal values for this attribute are 0 to 1023.", MODULE_NAME, CLK_COR_SEQ_1_3_0); + $finish; + end + + if ((CLK_COR_SEQ_1_3_1 >= 0) && (CLK_COR_SEQ_1_3_1 <= 1023)) + CLK_COR_SEQ_1_3_1_BINARY <= CLK_COR_SEQ_1_3_1; + else begin + $display("Attribute Syntax Error : The Attribute CLK_COR_SEQ_1_3_1 on %s instance %m is set to %d. Legal values for this attribute are 0 to 1023.", MODULE_NAME, CLK_COR_SEQ_1_3_1); + $finish; + end + + if ((CLK_COR_SEQ_1_4_0 >= 0) && (CLK_COR_SEQ_1_4_0 <= 1023)) + CLK_COR_SEQ_1_4_0_BINARY <= CLK_COR_SEQ_1_4_0; + else begin + $display("Attribute Syntax Error : The Attribute CLK_COR_SEQ_1_4_0 on %s instance %m is set to %d. Legal values for this attribute are 0 to 1023.", MODULE_NAME, CLK_COR_SEQ_1_4_0); + $finish; + end + + if ((CLK_COR_SEQ_1_4_1 >= 0) && (CLK_COR_SEQ_1_4_1 <= 1023)) + CLK_COR_SEQ_1_4_1_BINARY <= CLK_COR_SEQ_1_4_1; + else begin + $display("Attribute Syntax Error : The Attribute CLK_COR_SEQ_1_4_1 on %s instance %m is set to %d. Legal values for this attribute are 0 to 1023.", MODULE_NAME, CLK_COR_SEQ_1_4_1); + $finish; + end + + if ((CLK_COR_SEQ_1_ENABLE_0 >= 0) && (CLK_COR_SEQ_1_ENABLE_0 <= 15)) + CLK_COR_SEQ_1_ENABLE_0_BINARY <= CLK_COR_SEQ_1_ENABLE_0; + else begin + $display("Attribute Syntax Error : The Attribute CLK_COR_SEQ_1_ENABLE_0 on %s instance %m is set to %d. Legal values for this attribute are 0 to 15.", MODULE_NAME, CLK_COR_SEQ_1_ENABLE_0); + $finish; + end + + if ((CLK_COR_SEQ_1_ENABLE_1 >= 0) && (CLK_COR_SEQ_1_ENABLE_1 <= 15)) + CLK_COR_SEQ_1_ENABLE_1_BINARY <= CLK_COR_SEQ_1_ENABLE_1; + else begin + $display("Attribute Syntax Error : The Attribute CLK_COR_SEQ_1_ENABLE_1 on %s instance %m is set to %d. Legal values for this attribute are 0 to 15.", MODULE_NAME, CLK_COR_SEQ_1_ENABLE_1); + $finish; + end + + if ((CLK_COR_SEQ_2_1_0 >= 0) && (CLK_COR_SEQ_2_1_0 <= 1023)) + CLK_COR_SEQ_2_1_0_BINARY <= CLK_COR_SEQ_2_1_0; + else begin + $display("Attribute Syntax Error : The Attribute CLK_COR_SEQ_2_1_0 on %s instance %m is set to %d. Legal values for this attribute are 0 to 1023.", MODULE_NAME, CLK_COR_SEQ_2_1_0); + $finish; + end + + if ((CLK_COR_SEQ_2_1_1 >= 0) && (CLK_COR_SEQ_2_1_1 <= 1023)) + CLK_COR_SEQ_2_1_1_BINARY <= CLK_COR_SEQ_2_1_1; + else begin + $display("Attribute Syntax Error : The Attribute CLK_COR_SEQ_2_1_1 on %s instance %m is set to %d. Legal values for this attribute are 0 to 1023.", MODULE_NAME, CLK_COR_SEQ_2_1_1); + $finish; + end + + if ((CLK_COR_SEQ_2_2_0 >= 0) && (CLK_COR_SEQ_2_2_0 <= 1023)) + CLK_COR_SEQ_2_2_0_BINARY <= CLK_COR_SEQ_2_2_0; + else begin + $display("Attribute Syntax Error : The Attribute CLK_COR_SEQ_2_2_0 on %s instance %m is set to %d. Legal values for this attribute are 0 to 1023.", MODULE_NAME, CLK_COR_SEQ_2_2_0); + $finish; + end + + if ((CLK_COR_SEQ_2_2_1 >= 0) && (CLK_COR_SEQ_2_2_1 <= 1023)) + CLK_COR_SEQ_2_2_1_BINARY <= CLK_COR_SEQ_2_2_1; + else begin + $display("Attribute Syntax Error : The Attribute CLK_COR_SEQ_2_2_1 on %s instance %m is set to %d. Legal values for this attribute are 0 to 1023.", MODULE_NAME, CLK_COR_SEQ_2_2_1); + $finish; + end + + if ((CLK_COR_SEQ_2_3_0 >= 0) && (CLK_COR_SEQ_2_3_0 <= 1023)) + CLK_COR_SEQ_2_3_0_BINARY <= CLK_COR_SEQ_2_3_0; + else begin + $display("Attribute Syntax Error : The Attribute CLK_COR_SEQ_2_3_0 on %s instance %m is set to %d. Legal values for this attribute are 0 to 1023.", MODULE_NAME, CLK_COR_SEQ_2_3_0); + $finish; + end + + if ((CLK_COR_SEQ_2_3_1 >= 0) && (CLK_COR_SEQ_2_3_1 <= 1023)) + CLK_COR_SEQ_2_3_1_BINARY <= CLK_COR_SEQ_2_3_1; + else begin + $display("Attribute Syntax Error : The Attribute CLK_COR_SEQ_2_3_1 on %s instance %m is set to %d. Legal values for this attribute are 0 to 1023.", MODULE_NAME, CLK_COR_SEQ_2_3_1); + $finish; + end + + if ((CLK_COR_SEQ_2_4_0 >= 0) && (CLK_COR_SEQ_2_4_0 <= 1023)) + CLK_COR_SEQ_2_4_0_BINARY <= CLK_COR_SEQ_2_4_0; + else begin + $display("Attribute Syntax Error : The Attribute CLK_COR_SEQ_2_4_0 on %s instance %m is set to %d. Legal values for this attribute are 0 to 1023.", MODULE_NAME, CLK_COR_SEQ_2_4_0); + $finish; + end + + if ((CLK_COR_SEQ_2_4_1 >= 0) && (CLK_COR_SEQ_2_4_1 <= 1023)) + CLK_COR_SEQ_2_4_1_BINARY <= CLK_COR_SEQ_2_4_1; + else begin + $display("Attribute Syntax Error : The Attribute CLK_COR_SEQ_2_4_1 on %s instance %m is set to %d. Legal values for this attribute are 0 to 1023.", MODULE_NAME, CLK_COR_SEQ_2_4_1); + $finish; + end + + if ((CLK_COR_SEQ_2_ENABLE_0 >= 0) && (CLK_COR_SEQ_2_ENABLE_0 <= 15)) + CLK_COR_SEQ_2_ENABLE_0_BINARY <= CLK_COR_SEQ_2_ENABLE_0; + else begin + $display("Attribute Syntax Error : The Attribute CLK_COR_SEQ_2_ENABLE_0 on %s instance %m is set to %d. Legal values for this attribute are 0 to 15.", MODULE_NAME, CLK_COR_SEQ_2_ENABLE_0); + $finish; + end + + if ((CLK_COR_SEQ_2_ENABLE_1 >= 0) && (CLK_COR_SEQ_2_ENABLE_1 <= 15)) + CLK_COR_SEQ_2_ENABLE_1_BINARY <= CLK_COR_SEQ_2_ENABLE_1; + else begin + $display("Attribute Syntax Error : The Attribute CLK_COR_SEQ_2_ENABLE_1 on %s instance %m is set to %d. Legal values for this attribute are 0 to 15.", MODULE_NAME, CLK_COR_SEQ_2_ENABLE_1); + $finish; + end + + if ((CM_TRIM_0 >= 0) && (CM_TRIM_0 <= 3)) + CM_TRIM_0_BINARY <= CM_TRIM_0; + else begin + $display("Attribute Syntax Error : The Attribute CM_TRIM_0 on %s instance %m is set to %d. Legal values for this attribute are 0 to 3.", MODULE_NAME, CM_TRIM_0); + $finish; + end + + if ((CM_TRIM_1 >= 0) && (CM_TRIM_1 <= 3)) + CM_TRIM_1_BINARY <= CM_TRIM_1; + else begin + $display("Attribute Syntax Error : The Attribute CM_TRIM_1 on %s instance %m is set to %d. Legal values for this attribute are 0 to 3.", MODULE_NAME, CM_TRIM_1); + $finish; + end + + if ((COMMA_10B_ENABLE_0 >= 0) && (COMMA_10B_ENABLE_0 <= 1023)) + COMMA_10B_ENABLE_0_BINARY <= COMMA_10B_ENABLE_0; + else begin + $display("Attribute Syntax Error : The Attribute COMMA_10B_ENABLE_0 on %s instance %m is set to %d. Legal values for this attribute are 0 to 1023.", MODULE_NAME, COMMA_10B_ENABLE_0); + $finish; + end + + if ((COMMA_10B_ENABLE_1 >= 0) && (COMMA_10B_ENABLE_1 <= 1023)) + COMMA_10B_ENABLE_1_BINARY <= COMMA_10B_ENABLE_1; + else begin + $display("Attribute Syntax Error : The Attribute COMMA_10B_ENABLE_1 on %s instance %m is set to %d. Legal values for this attribute are 0 to 1023.", MODULE_NAME, COMMA_10B_ENABLE_1); + $finish; + end + + if ((COM_BURST_VAL_0 >= 0) && (COM_BURST_VAL_0 <= 15)) + COM_BURST_VAL_0_BINARY <= COM_BURST_VAL_0; + else begin + $display("Attribute Syntax Error : The Attribute COM_BURST_VAL_0 on %s instance %m is set to %d. Legal values for this attribute are 0 to 15.", MODULE_NAME, COM_BURST_VAL_0); + $finish; + end + + if ((COM_BURST_VAL_1 >= 0) && (COM_BURST_VAL_1 <= 15)) + COM_BURST_VAL_1_BINARY <= COM_BURST_VAL_1; + else begin + $display("Attribute Syntax Error : The Attribute COM_BURST_VAL_1 on %s instance %m is set to %d. Legal values for this attribute are 0 to 15.", MODULE_NAME, COM_BURST_VAL_1); + $finish; + end + + if ((MCOMMA_10B_VALUE_0 >= 0) && (MCOMMA_10B_VALUE_0 <= 1023)) + MCOMMA_10B_VALUE_0_BINARY <= MCOMMA_10B_VALUE_0; + else begin + $display("Attribute Syntax Error : The Attribute MCOMMA_10B_VALUE_0 on %s instance %m is set to %d. Legal values for this attribute are 0 to 1023.", MODULE_NAME, MCOMMA_10B_VALUE_0); + $finish; + end + + if ((MCOMMA_10B_VALUE_1 >= 0) && (MCOMMA_10B_VALUE_1 <= 1023)) + MCOMMA_10B_VALUE_1_BINARY <= MCOMMA_10B_VALUE_1; + else begin + $display("Attribute Syntax Error : The Attribute MCOMMA_10B_VALUE_1 on %s instance %m is set to %d. Legal values for this attribute are 0 to 1023.", MODULE_NAME, MCOMMA_10B_VALUE_1); + $finish; + end + + if ((OOBDETECT_THRESHOLD_0 >= 0) && (OOBDETECT_THRESHOLD_0 <= 7)) + OOBDETECT_THRESHOLD_0_BINARY <= OOBDETECT_THRESHOLD_0; + else begin + $display("Attribute Syntax Error : The Attribute OOBDETECT_THRESHOLD_0 on %s instance %m is set to %d. Legal values for this attribute are 0 to 7.", MODULE_NAME, OOBDETECT_THRESHOLD_0); + $finish; + end + + if ((OOBDETECT_THRESHOLD_1 >= 0) && (OOBDETECT_THRESHOLD_1 <= 7)) + OOBDETECT_THRESHOLD_1_BINARY <= OOBDETECT_THRESHOLD_1; + else begin + $display("Attribute Syntax Error : The Attribute OOBDETECT_THRESHOLD_1 on %s instance %m is set to %d. Legal values for this attribute are 0 to 7.", MODULE_NAME, OOBDETECT_THRESHOLD_1); + $finish; + end + + if ((PCOMMA_10B_VALUE_0 >= 0) && (PCOMMA_10B_VALUE_0 <= 1023)) + PCOMMA_10B_VALUE_0_BINARY <= PCOMMA_10B_VALUE_0; + else begin + $display("Attribute Syntax Error : The Attribute PCOMMA_10B_VALUE_0 on %s instance %m is set to %d. Legal values for this attribute are 0 to 1023.", MODULE_NAME, PCOMMA_10B_VALUE_0); + $finish; + end + + if ((PCOMMA_10B_VALUE_1 >= 0) && (PCOMMA_10B_VALUE_1 <= 1023)) + PCOMMA_10B_VALUE_1_BINARY <= PCOMMA_10B_VALUE_1; + else begin + $display("Attribute Syntax Error : The Attribute PCOMMA_10B_VALUE_1 on %s instance %m is set to %d. Legal values for this attribute are 0 to 1023.", MODULE_NAME, PCOMMA_10B_VALUE_1); + $finish; + end + + if ((PLLLKDET_CFG_0 >= 0) && (PLLLKDET_CFG_0 <= 7)) + PLLLKDET_CFG_0_BINARY <= PLLLKDET_CFG_0; + else begin + $display("Attribute Syntax Error : The Attribute PLLLKDET_CFG_0 on %s instance %m is set to %d. Legal values for this attribute are 0 to 7.", MODULE_NAME, PLLLKDET_CFG_0); + $finish; + end + + if ((PLLLKDET_CFG_1 >= 0) && (PLLLKDET_CFG_1 <= 7)) + PLLLKDET_CFG_1_BINARY <= PLLLKDET_CFG_1; + else begin + $display("Attribute Syntax Error : The Attribute PLLLKDET_CFG_1 on %s instance %m is set to %d. Legal values for this attribute are 0 to 7.", MODULE_NAME, PLLLKDET_CFG_1); + $finish; + end + + if ((RXEQ_CFG_0 >= 0) && (RXEQ_CFG_0 <= 255)) + RXEQ_CFG_0_BINARY <= RXEQ_CFG_0; + else begin + $display("Attribute Syntax Error : The Attribute RXEQ_CFG_0 on %s instance %m is set to %d. Legal values for this attribute are 0 to 255.", MODULE_NAME, RXEQ_CFG_0); + $finish; + end + + if ((RXEQ_CFG_1 >= 0) && (RXEQ_CFG_1 <= 255)) + RXEQ_CFG_1_BINARY <= RXEQ_CFG_1; + else begin + $display("Attribute Syntax Error : The Attribute RXEQ_CFG_1 on %s instance %m is set to %d. Legal values for this attribute are 0 to 255.", MODULE_NAME, RXEQ_CFG_1); + $finish; + end + + if ((RXPRBSERR_LOOPBACK_0 >= 0) && (RXPRBSERR_LOOPBACK_0 <= 1)) + RXPRBSERR_LOOPBACK_0_BINARY <= RXPRBSERR_LOOPBACK_0; + else begin + $display("Attribute Syntax Error : The Attribute RXPRBSERR_LOOPBACK_0 on %s instance %m is set to %d. Legal values for this attribute are 0 to 1.", MODULE_NAME, RXPRBSERR_LOOPBACK_0); + $finish; + end + + if ((RXPRBSERR_LOOPBACK_1 >= 0) && (RXPRBSERR_LOOPBACK_1 <= 1)) + RXPRBSERR_LOOPBACK_1_BINARY <= RXPRBSERR_LOOPBACK_1; + else begin + $display("Attribute Syntax Error : The Attribute RXPRBSERR_LOOPBACK_1 on %s instance %m is set to %d. Legal values for this attribute are 0 to 1.", MODULE_NAME, RXPRBSERR_LOOPBACK_1); + $finish; + end + + if ((RX_IDLE_HI_CNT_0 >= 0) && (RX_IDLE_HI_CNT_0 <= 15)) + RX_IDLE_HI_CNT_0_BINARY <= RX_IDLE_HI_CNT_0; + else begin + $display("Attribute Syntax Error : The Attribute RX_IDLE_HI_CNT_0 on %s instance %m is set to %d. Legal values for this attribute are 0 to 15.", MODULE_NAME, RX_IDLE_HI_CNT_0); + $finish; + end + + if ((RX_IDLE_HI_CNT_1 >= 0) && (RX_IDLE_HI_CNT_1 <= 15)) + RX_IDLE_HI_CNT_1_BINARY <= RX_IDLE_HI_CNT_1; + else begin + $display("Attribute Syntax Error : The Attribute RX_IDLE_HI_CNT_1 on %s instance %m is set to %d. Legal values for this attribute are 0 to 15.", MODULE_NAME, RX_IDLE_HI_CNT_1); + $finish; + end + + if ((RX_IDLE_LO_CNT_0 >= 0) && (RX_IDLE_LO_CNT_0 <= 15)) + RX_IDLE_LO_CNT_0_BINARY <= RX_IDLE_LO_CNT_0; + else begin + $display("Attribute Syntax Error : The Attribute RX_IDLE_LO_CNT_0 on %s instance %m is set to %d. Legal values for this attribute are 0 to 15.", MODULE_NAME, RX_IDLE_LO_CNT_0); + $finish; + end + + if ((RX_IDLE_LO_CNT_1 >= 0) && (RX_IDLE_LO_CNT_1 <= 15)) + RX_IDLE_LO_CNT_1_BINARY <= RX_IDLE_LO_CNT_1; + else begin + $display("Attribute Syntax Error : The Attribute RX_IDLE_LO_CNT_1 on %s instance %m is set to %d. Legal values for this attribute are 0 to 15.", MODULE_NAME, RX_IDLE_LO_CNT_1); + $finish; + end + + if ((SATA_BURST_VAL_0 >= 0) && (SATA_BURST_VAL_0 <= 7)) + SATA_BURST_VAL_0_BINARY <= SATA_BURST_VAL_0; + else begin + $display("Attribute Syntax Error : The Attribute SATA_BURST_VAL_0 on %s instance %m is set to %d. Legal values for this attribute are 0 to 7.", MODULE_NAME, SATA_BURST_VAL_0); + $finish; + end + + if ((SATA_BURST_VAL_1 >= 0) && (SATA_BURST_VAL_1 <= 7)) + SATA_BURST_VAL_1_BINARY <= SATA_BURST_VAL_1; + else begin + $display("Attribute Syntax Error : The Attribute SATA_BURST_VAL_1 on %s instance %m is set to %d. Legal values for this attribute are 0 to 7.", MODULE_NAME, SATA_BURST_VAL_1); + $finish; + end + + if ((SATA_IDLE_VAL_0 >= 0) && (SATA_IDLE_VAL_0 <= 7)) + SATA_IDLE_VAL_0_BINARY <= SATA_IDLE_VAL_0; + else begin + $display("Attribute Syntax Error : The Attribute SATA_IDLE_VAL_0 on %s instance %m is set to %d. Legal values for this attribute are 0 to 7.", MODULE_NAME, SATA_IDLE_VAL_0); + $finish; + end + + if ((SATA_IDLE_VAL_1 >= 0) && (SATA_IDLE_VAL_1 <= 7)) + SATA_IDLE_VAL_1_BINARY <= SATA_IDLE_VAL_1; + else begin + $display("Attribute Syntax Error : The Attribute SATA_IDLE_VAL_1 on %s instance %m is set to %d. Legal values for this attribute are 0 to 7.", MODULE_NAME, SATA_IDLE_VAL_1); + $finish; + end + + if ((SATA_MAX_BURST_0 >= 1) && (SATA_MAX_BURST_0 <= 61)) + SATA_MAX_BURST_0_BINARY <= SATA_MAX_BURST_0; + else begin + $display("Attribute Syntax Error : The Attribute SATA_MAX_BURST_0 on %s instance %m is set to %d. Legal values for this attribute are 1 to 61.", MODULE_NAME, SATA_MAX_BURST_0); + $finish; + end + + if ((SATA_MAX_BURST_1 >= 1) && (SATA_MAX_BURST_1 <= 61)) + SATA_MAX_BURST_1_BINARY <= SATA_MAX_BURST_1; + else begin + $display("Attribute Syntax Error : The Attribute SATA_MAX_BURST_1 on %s instance %m is set to %d. Legal values for this attribute are 1 to 61.", MODULE_NAME, SATA_MAX_BURST_1); + $finish; + end + + if ((SATA_MAX_INIT_0 >= 1) && (SATA_MAX_INIT_0 <= 61)) + SATA_MAX_INIT_0_BINARY <= SATA_MAX_INIT_0; + else begin + $display("Attribute Syntax Error : The Attribute SATA_MAX_INIT_0 on %s instance %m is set to %d. Legal values for this attribute are 1 to 61.", MODULE_NAME, SATA_MAX_INIT_0); + $finish; + end + + if ((SATA_MAX_INIT_1 >= 1) && (SATA_MAX_INIT_1 <= 61)) + SATA_MAX_INIT_1_BINARY <= SATA_MAX_INIT_1; + else begin + $display("Attribute Syntax Error : The Attribute SATA_MAX_INIT_1 on %s instance %m is set to %d. Legal values for this attribute are 1 to 61.", MODULE_NAME, SATA_MAX_INIT_1); + $finish; + end + + if ((SATA_MAX_WAKE_0 >= 1) && (SATA_MAX_WAKE_0 <= 61)) + SATA_MAX_WAKE_0_BINARY <= SATA_MAX_WAKE_0; + else begin + $display("Attribute Syntax Error : The Attribute SATA_MAX_WAKE_0 on %s instance %m is set to %d. Legal values for this attribute are 1 to 61.", MODULE_NAME, SATA_MAX_WAKE_0); + $finish; + end + + if ((SATA_MAX_WAKE_1 >= 1) && (SATA_MAX_WAKE_1 <= 61)) + SATA_MAX_WAKE_1_BINARY <= SATA_MAX_WAKE_1; + else begin + $display("Attribute Syntax Error : The Attribute SATA_MAX_WAKE_1 on %s instance %m is set to %d. Legal values for this attribute are 1 to 61.", MODULE_NAME, SATA_MAX_WAKE_1); + $finish; + end + + if ((SATA_MIN_BURST_0 >= 1) && (SATA_MIN_BURST_0 <= 61)) + SATA_MIN_BURST_0_BINARY <= SATA_MIN_BURST_0; + else begin + $display("Attribute Syntax Error : The Attribute SATA_MIN_BURST_0 on %s instance %m is set to %d. Legal values for this attribute are 1 to 61.", MODULE_NAME, SATA_MIN_BURST_0); + $finish; + end + + if ((SATA_MIN_BURST_1 >= 1) && (SATA_MIN_BURST_1 <= 61)) + SATA_MIN_BURST_1_BINARY <= SATA_MIN_BURST_1; + else begin + $display("Attribute Syntax Error : The Attribute SATA_MIN_BURST_1 on %s instance %m is set to %d. Legal values for this attribute are 1 to 61.", MODULE_NAME, SATA_MIN_BURST_1); + $finish; + end + + if ((SATA_MIN_INIT_0 >= 1) && (SATA_MIN_INIT_0 <= 61)) + SATA_MIN_INIT_0_BINARY <= SATA_MIN_INIT_0; + else begin + $display("Attribute Syntax Error : The Attribute SATA_MIN_INIT_0 on %s instance %m is set to %d. Legal values for this attribute are 1 to 61.", MODULE_NAME, SATA_MIN_INIT_0); + $finish; + end + + if ((SATA_MIN_INIT_1 >= 1) && (SATA_MIN_INIT_1 <= 61)) + SATA_MIN_INIT_1_BINARY <= SATA_MIN_INIT_1; + else begin + $display("Attribute Syntax Error : The Attribute SATA_MIN_INIT_1 on %s instance %m is set to %d. Legal values for this attribute are 1 to 61.", MODULE_NAME, SATA_MIN_INIT_1); + $finish; + end + + if ((SATA_MIN_WAKE_0 >= 1) && (SATA_MIN_WAKE_0 <= 61)) + SATA_MIN_WAKE_0_BINARY <= SATA_MIN_WAKE_0; + else begin + $display("Attribute Syntax Error : The Attribute SATA_MIN_WAKE_0 on %s instance %m is set to %d. Legal values for this attribute are 1 to 61.", MODULE_NAME, SATA_MIN_WAKE_0); + $finish; + end + + if ((SATA_MIN_WAKE_1 >= 1) && (SATA_MIN_WAKE_1 <= 61)) + SATA_MIN_WAKE_1_BINARY <= SATA_MIN_WAKE_1; + else begin + $display("Attribute Syntax Error : The Attribute SATA_MIN_WAKE_1 on %s instance %m is set to %d. Legal values for this attribute are 1 to 61.", MODULE_NAME, SATA_MIN_WAKE_1); + $finish; + end + + if (SATA_MIN_BURST_0 > SATA_MAX_BURST_0) begin + $display("DRC Error : The value of SATA_MIN_BURST_0 is set to %d. This value must be less than or equal to the value of SATA_MAX_BURST_0 %d for instance %m of %s.", MODULE_NAME,SATA_MIN_BURST_0, SATA_MAX_BURST_0); + $finish; + end + + if (SATA_MIN_BURST_1 > SATA_MAX_BURST_1) begin + $display("DRC Error : The value of SATA_MIN_BURST_1 is set to %d. This value must be less than or equal to the value of SATA_MAX_BURST_1 %d for instance %m of %s.", MODULE_NAME,SATA_MIN_BURST_1, SATA_MAX_BURST_1); + $finish; + end + + if (SATA_MIN_INIT_0 > SATA_MAX_INIT_0) begin + $display("DRC Error : The value of SATA_MIN_INIT_0 is set to %d. This value must be less than or equal to the value of SATA_MAX_INIT_0 %d for instance %m of %s.", MODULE_NAME,SATA_MIN_INIT_0, SATA_MAX_INIT_0); + $finish; + end + + if (SATA_MIN_INIT_1 > SATA_MAX_INIT_1) begin + $display("DRC Error : The value of SATA_MIN_INIT_1 is set to %d. This value must be less than or equal to the value of SATA_MAX_INIT_1 %d for instance %m of %s.", MODULE_NAME,SATA_MIN_INIT_1, SATA_MAX_INIT_1); + $finish; + end + + if (SATA_MIN_WAKE_0 > SATA_MAX_WAKE_0) begin + $display("DRC Error : The value of SATA_MIN_WAKE_0 is set to %d. This value must be less than or equal to the value of SATA_MAX_WAKE_0 %d for instance %m of %s.", MODULE_NAME,SATA_MIN_WAKE_0, SATA_MAX_WAKE_0); + $finish; + end + + if (SATA_MIN_WAKE_1 > SATA_MAX_WAKE_1) begin + $display("DRC Error : The value of SATA_MIN_WAKE_1 is set to %d. This value must be less than or equal to the value of SATA_MAX_WAKE_1 %d for instance %m of %s.", MODULE_NAME,SATA_MIN_WAKE_1, SATA_MAX_WAKE_1); + $finish; + end + + if ((SIM_REFCLK0_SOURCE >= 0) && (SIM_REFCLK0_SOURCE <= 7)) + SIM_REFCLK0_SOURCE_BINARY <= SIM_REFCLK0_SOURCE; + else begin + $display("Attribute Syntax Error : The Attribute SIM_REFCLK0_SOURCE on %s instance %m is set to %d. Legal values for this attribute are 0 to 7.", MODULE_NAME, SIM_REFCLK0_SOURCE); + $finish; + end + + if ((SIM_REFCLK1_SOURCE >= 0) && (SIM_REFCLK1_SOURCE <= 7)) + SIM_REFCLK1_SOURCE_BINARY <= SIM_REFCLK1_SOURCE; + else begin + $display("Attribute Syntax Error : The Attribute SIM_REFCLK1_SOURCE on %s instance %m is set to %d. Legal values for this attribute are 0 to 7.", MODULE_NAME, SIM_REFCLK1_SOURCE); + $finish; + end + + if ((TERMINATION_CTRL_0 >= 0) && (TERMINATION_CTRL_0 <= 31)) + TERMINATION_CTRL_0_BINARY <= TERMINATION_CTRL_0; + else begin + $display("Attribute Syntax Error : The Attribute TERMINATION_CTRL_0 on %s instance %m is set to %d. Legal values for this attribute are 0 to 31.", MODULE_NAME, TERMINATION_CTRL_0); + $finish; + end + + if ((TERMINATION_CTRL_1 >= 0) && (TERMINATION_CTRL_1 <= 31)) + TERMINATION_CTRL_1_BINARY <= TERMINATION_CTRL_1; + else begin + $display("Attribute Syntax Error : The Attribute TERMINATION_CTRL_1 on %s instance %m is set to %d. Legal values for this attribute are 0 to 31.", MODULE_NAME, TERMINATION_CTRL_1); + $finish; + end + + if ((TXRX_INVERT_0 >= 0) && (TXRX_INVERT_0 <= 7)) + TXRX_INVERT_0_BINARY <= TXRX_INVERT_0; + else begin + $display("Attribute Syntax Error : The Attribute TXRX_INVERT_0 on %s instance %m is set to %d. Legal values for this attribute are 0 to 7.", MODULE_NAME, TXRX_INVERT_0); + $finish; + end + + if ((TXRX_INVERT_1 >= 0) && (TXRX_INVERT_1 <= 7)) + TXRX_INVERT_1_BINARY <= TXRX_INVERT_1; + else begin + $display("Attribute Syntax Error : The Attribute TXRX_INVERT_1 on %s instance %m is set to %d. Legal values for this attribute are 0 to 7.", MODULE_NAME, TXRX_INVERT_1); + $finish; + end + + if ((TX_IDLE_DELAY_0 >= 0) && (TX_IDLE_DELAY_0 <= 7)) + TX_IDLE_DELAY_0_BINARY <= TX_IDLE_DELAY_0; + else begin + $display("Attribute Syntax Error : The Attribute TX_IDLE_DELAY_0 on %s instance %m is set to %d. Legal values for this attribute are 0 to 7.", MODULE_NAME, TX_IDLE_DELAY_0); + $finish; + end + + if ((TX_IDLE_DELAY_1 >= 0) && (TX_IDLE_DELAY_1 <= 7)) + TX_IDLE_DELAY_1_BINARY <= TX_IDLE_DELAY_1; + else begin + $display("Attribute Syntax Error : The Attribute TX_IDLE_DELAY_1 on %s instance %m is set to %d. Legal values for this attribute are 0 to 7.", MODULE_NAME, TX_IDLE_DELAY_1); + $finish; + end + + if ((TX_TDCC_CFG_0 >= 0) && (TX_TDCC_CFG_0 <= 3)) + TX_TDCC_CFG_0_BINARY <= TX_TDCC_CFG_0; + else begin + $display("Attribute Syntax Error : The Attribute TX_TDCC_CFG_0 on %s instance %m is set to %d. Legal values for this attribute are 0 to 3.", MODULE_NAME, TX_TDCC_CFG_0); + $finish; + end + + if ((TX_TDCC_CFG_1 >= 0) && (TX_TDCC_CFG_1 <= 3)) + TX_TDCC_CFG_1_BINARY <= TX_TDCC_CFG_1; + else begin + $display("Attribute Syntax Error : The Attribute TX_TDCC_CFG_1 on %s instance %m is set to %d. Legal values for this attribute are 0 to 3.", MODULE_NAME, TX_TDCC_CFG_1); + $finish; + end + + end + +//---------------------------------------------------------------------- +//------------------------ Output Ports ------------------------------ +//---------------------------------------------------------------------- + assign #(OUTCLK_DELAY) GTPCLKOUT0 = GTPCLKOUT0_OUT; + assign #(OUTCLK_DELAY) GTPCLKOUT1 = GTPCLKOUT1_OUT; + assign #(OUTCLK_DELAY) REFCLKPLL0 = REFCLKPLL0_OUT; + assign #(OUTCLK_DELAY) REFCLKPLL1 = REFCLKPLL1_OUT; + + assign #(out_delay) DRDY = DRDY_OUT; + assign #(out_delay) DRPDO = DRPDO_OUT; + assign #(out_delay) GTPCLKFBEAST = GTPCLKFBEAST_OUT; + assign #(out_delay) GTPCLKFBWEST = GTPCLKFBWEST_OUT; + assign #(out_delay) PHYSTATUS0 = PHYSTATUS0_OUT; + assign #(out_delay) PHYSTATUS1 = PHYSTATUS1_OUT; + assign #(out_delay) PLLLKDET0 = PLLLKDET0_OUT; + assign #(out_delay) PLLLKDET1 = PLLLKDET1_OUT; + assign #(out_delay) RCALOUTEAST = RCALOUTEAST_OUT; + assign #(out_delay) RCALOUTWEST = RCALOUTWEST_OUT; + assign #(out_delay) REFCLKOUT0 = REFCLKOUT0_OUT; + assign #(out_delay) REFCLKOUT1 = REFCLKOUT1_OUT; + assign #(out_delay) RESETDONE0 = RESETDONE0_OUT; + assign #(out_delay) RESETDONE1 = RESETDONE1_OUT; + assign #(out_delay) RXBUFSTATUS0 = RXBUFSTATUS0_OUT; + assign #(out_delay) RXBUFSTATUS1 = RXBUFSTATUS1_OUT; + assign #(out_delay) RXBYTEISALIGNED0 = RXBYTEISALIGNED0_OUT; + assign #(out_delay) RXBYTEISALIGNED1 = RXBYTEISALIGNED1_OUT; + assign #(out_delay) RXBYTEREALIGN0 = RXBYTEREALIGN0_OUT; + assign #(out_delay) RXBYTEREALIGN1 = RXBYTEREALIGN1_OUT; + assign #(out_delay) RXCHANBONDSEQ0 = RXCHANBONDSEQ0_OUT; + assign #(out_delay) RXCHANBONDSEQ1 = RXCHANBONDSEQ1_OUT; + assign #(out_delay) RXCHANISALIGNED0 = RXCHANISALIGNED0_OUT; + assign #(out_delay) RXCHANISALIGNED1 = RXCHANISALIGNED1_OUT; + assign #(out_delay) RXCHANREALIGN0 = RXCHANREALIGN0_OUT; + assign #(out_delay) RXCHANREALIGN1 = RXCHANREALIGN1_OUT; + assign #(out_delay) RXCHARISCOMMA0 = RXCHARISCOMMA0_OUT; + assign #(out_delay) RXCHARISCOMMA1 = RXCHARISCOMMA1_OUT; + assign #(out_delay) RXCHARISK0 = RXCHARISK0_OUT; + assign #(out_delay) RXCHARISK1 = RXCHARISK1_OUT; + assign #(out_delay) RXCHBONDO = RXCHBONDO_OUT; + assign #(out_delay) RXCLKCORCNT0 = RXCLKCORCNT0_OUT; + assign #(out_delay) RXCLKCORCNT1 = RXCLKCORCNT1_OUT; + assign #(out_delay) RXCOMMADET0 = RXCOMMADET0_OUT; + assign #(out_delay) RXCOMMADET1 = RXCOMMADET1_OUT; + assign #(out_delay) RXDATA0 = RXDATA0_OUT; + assign #(out_delay) RXDATA1 = RXDATA1_OUT; + assign #(out_delay) RXDISPERR0 = RXDISPERR0_OUT; + assign #(out_delay) RXDISPERR1 = RXDISPERR1_OUT; + assign #(out_delay) RXELECIDLE0 = RXELECIDLE0_OUT; + assign #(out_delay) RXELECIDLE1 = RXELECIDLE1_OUT; + assign #(out_delay) RXLOSSOFSYNC0 = RXLOSSOFSYNC0_OUT; + assign #(out_delay) RXLOSSOFSYNC1 = RXLOSSOFSYNC1_OUT; + assign #(out_delay) RXNOTINTABLE0 = RXNOTINTABLE0_OUT; + assign #(out_delay) RXNOTINTABLE1 = RXNOTINTABLE1_OUT; + assign #(out_delay) RXPRBSERR0 = RXPRBSERR0_OUT; + assign #(out_delay) RXPRBSERR1 = RXPRBSERR1_OUT; + assign #(out_delay) RXRECCLK0 = RXRECCLK0_OUT; + assign #(out_delay) RXRECCLK1 = RXRECCLK1_OUT; + assign #(out_delay) RXRUNDISP0 = RXRUNDISP0_OUT; + assign #(out_delay) RXRUNDISP1 = RXRUNDISP1_OUT; + assign #(out_delay) RXSTATUS0 = RXSTATUS0_OUT; + assign #(out_delay) RXSTATUS1 = RXSTATUS1_OUT; + assign #(out_delay) RXVALID0 = RXVALID0_OUT; + assign #(out_delay) RXVALID1 = RXVALID1_OUT; + assign #(out_delay) TSTOUT0 = TSTOUT0_OUT; + assign #(out_delay) TSTOUT1 = TSTOUT1_OUT; + assign #(out_delay) TXBUFSTATUS0 = TXBUFSTATUS0_OUT; + assign #(out_delay) TXBUFSTATUS1 = TXBUFSTATUS1_OUT; + assign #(out_delay) TXKERR0 = TXKERR0_OUT; + assign #(out_delay) TXKERR1 = TXKERR1_OUT; + assign #(out_delay) TXN0 = TXN0_OUT; + assign #(out_delay) TXN1 = TXN1_OUT; + assign #(out_delay) TXOUTCLK0 = TXOUTCLK0_OUT; + assign #(out_delay) TXOUTCLK1 = TXOUTCLK1_OUT; + assign #(out_delay) TXP0 = TXP0_OUT; + assign #(out_delay) TXP1 = TXP1_OUT; + assign #(out_delay) TXRUNDISP0 = TXRUNDISP0_OUT; + assign #(out_delay) TXRUNDISP1 = TXRUNDISP1_OUT; + + assign #(INCLK_DELAY) CLK00_IN = CLK00; + assign #(INCLK_DELAY) CLK01_IN = CLK01; + assign #(INCLK_DELAY) CLK10_IN = CLK10; + assign #(INCLK_DELAY) CLK11_IN = CLK11; + assign #(INCLK_DELAY) CLKINEAST0_IN = CLKINEAST0; + assign #(INCLK_DELAY) CLKINEAST1_IN = CLKINEAST1; + assign #(INCLK_DELAY) CLKINWEST0_IN = CLKINWEST0; + assign #(INCLK_DELAY) CLKINWEST1_IN = CLKINWEST1; + assign #(INCLK_DELAY) DCLK_IN = DCLK; + assign #(INCLK_DELAY) GCLK00_IN = GCLK00; + assign #(INCLK_DELAY) GCLK01_IN = GCLK01; + assign #(INCLK_DELAY) GCLK10_IN = GCLK10; + assign #(INCLK_DELAY) GCLK11_IN = GCLK11; + assign #(INCLK_DELAY) PLLCLK00_IN = PLLCLK00; + assign #(INCLK_DELAY) PLLCLK01_IN = PLLCLK01; + assign #(INCLK_DELAY) PLLCLK10_IN = PLLCLK10; + assign #(INCLK_DELAY) PLLCLK11_IN = PLLCLK11; + assign #(INCLK_DELAY) RXUSRCLK0_IN = RXUSRCLK0; + assign #(INCLK_DELAY) RXUSRCLK1_IN = RXUSRCLK1; + assign #(INCLK_DELAY) RXUSRCLK20_IN = RXUSRCLK20; + assign #(INCLK_DELAY) RXUSRCLK21_IN = RXUSRCLK21; + assign #(INCLK_DELAY) TSTCLK0_IN = TSTCLK0; + assign #(INCLK_DELAY) TSTCLK1_IN = TSTCLK1; + assign #(INCLK_DELAY) TXUSRCLK0_IN = TXUSRCLK0; + assign #(INCLK_DELAY) TXUSRCLK1_IN = TXUSRCLK1; + assign #(INCLK_DELAY) TXUSRCLK20_IN = TXUSRCLK20; + assign #(INCLK_DELAY) TXUSRCLK21_IN = TXUSRCLK21; + + assign #(in_delay) DADDR_IN = DADDR; + assign #(in_delay) DEN_IN = DEN; + assign #(in_delay) DI_IN = DI; + assign #(in_delay) DWE_IN = DWE; + assign #(in_delay) GATERXELECIDLE0_IN = GATERXELECIDLE0; + assign #(in_delay) GATERXELECIDLE1_IN = GATERXELECIDLE1; + assign #(in_delay) GTPCLKFBSEL0EAST_IN = GTPCLKFBSEL0EAST; + assign #(in_delay) GTPCLKFBSEL0WEST_IN = GTPCLKFBSEL0WEST; + assign #(in_delay) GTPCLKFBSEL1EAST_IN = GTPCLKFBSEL1EAST; + assign #(in_delay) GTPCLKFBSEL1WEST_IN = GTPCLKFBSEL1WEST; + assign #(in_delay) GTPRESET0_IN = GTPRESET0; + assign #(in_delay) GTPRESET1_IN = GTPRESET1; + assign #(in_delay) GTPTEST0_IN = GTPTEST0; + assign #(in_delay) GTPTEST1_IN = GTPTEST1; + assign #(in_delay) IGNORESIGDET0_IN = IGNORESIGDET0; + assign #(in_delay) IGNORESIGDET1_IN = IGNORESIGDET1; + assign #(in_delay) INTDATAWIDTH0_IN = INTDATAWIDTH0; + assign #(in_delay) INTDATAWIDTH1_IN = INTDATAWIDTH1; + assign #(in_delay) LOOPBACK0_IN = LOOPBACK0; + assign #(in_delay) LOOPBACK1_IN = LOOPBACK1; + assign #(in_delay) PLLLKDETEN0_IN = PLLLKDETEN0; + assign #(in_delay) PLLLKDETEN1_IN = PLLLKDETEN1; + assign #(in_delay) PLLPOWERDOWN0_IN = PLLPOWERDOWN0; + assign #(in_delay) PLLPOWERDOWN1_IN = PLLPOWERDOWN1; + assign #(in_delay) PRBSCNTRESET0_IN = PRBSCNTRESET0; + assign #(in_delay) PRBSCNTRESET1_IN = PRBSCNTRESET1; + assign #(in_delay) RCALINEAST_IN = RCALINEAST; + assign #(in_delay) RCALINWEST_IN = RCALINWEST; + assign #(in_delay) REFCLKPWRDNB0_IN = REFCLKPWRDNB0; + assign #(in_delay) REFCLKPWRDNB1_IN = REFCLKPWRDNB1; + assign #(in_delay) REFSELDYPLL0_IN = REFSELDYPLL0; + assign #(in_delay) REFSELDYPLL1_IN = REFSELDYPLL1; + assign #(in_delay) RXBUFRESET0_IN = RXBUFRESET0; + assign #(in_delay) RXBUFRESET1_IN = RXBUFRESET1; + assign #(in_delay) RXCDRRESET0_IN = RXCDRRESET0; + assign #(in_delay) RXCDRRESET1_IN = RXCDRRESET1; + assign #(in_delay) RXCHBONDI_IN = RXCHBONDI; + assign #(in_delay) RXCHBONDMASTER0_IN = RXCHBONDMASTER0; + assign #(in_delay) RXCHBONDMASTER1_IN = RXCHBONDMASTER1; + assign #(in_delay) RXCHBONDSLAVE0_IN = RXCHBONDSLAVE0; + assign #(in_delay) RXCHBONDSLAVE1_IN = RXCHBONDSLAVE1; + assign #(in_delay) RXCOMMADETUSE0_IN = RXCOMMADETUSE0; + assign #(in_delay) RXCOMMADETUSE1_IN = RXCOMMADETUSE1; + assign #(in_delay) RXDATAWIDTH0_IN = RXDATAWIDTH0; + assign #(in_delay) RXDATAWIDTH1_IN = RXDATAWIDTH1; + assign #(in_delay) RXDEC8B10BUSE0_IN = RXDEC8B10BUSE0; + assign #(in_delay) RXDEC8B10BUSE1_IN = RXDEC8B10BUSE1; + assign #(in_delay) RXENCHANSYNC0_IN = RXENCHANSYNC0; + assign #(in_delay) RXENCHANSYNC1_IN = RXENCHANSYNC1; + assign #(in_delay) RXENMCOMMAALIGN0_IN = RXENMCOMMAALIGN0; + assign #(in_delay) RXENMCOMMAALIGN1_IN = RXENMCOMMAALIGN1; + assign #(in_delay) RXENPCOMMAALIGN0_IN = RXENPCOMMAALIGN0; + assign #(in_delay) RXENPCOMMAALIGN1_IN = RXENPCOMMAALIGN1; + assign #(in_delay) RXENPMAPHASEALIGN0_IN = RXENPMAPHASEALIGN0; + assign #(in_delay) RXENPMAPHASEALIGN1_IN = RXENPMAPHASEALIGN1; + assign #(in_delay) RXENPRBSTST0_IN = RXENPRBSTST0; + assign #(in_delay) RXENPRBSTST1_IN = RXENPRBSTST1; + assign #(in_delay) RXEQMIX0_IN = RXEQMIX0; + assign #(in_delay) RXEQMIX1_IN = RXEQMIX1; + assign #(in_delay) RXN0_IN = RXN0; + assign #(in_delay) RXN1_IN = RXN1; + assign #(in_delay) RXP0_IN = RXP0; + assign #(in_delay) RXP1_IN = RXP1; + assign #(in_delay) RXPMASETPHASE0_IN = RXPMASETPHASE0; + assign #(in_delay) RXPMASETPHASE1_IN = RXPMASETPHASE1; + assign #(in_delay) RXPOLARITY0_IN = RXPOLARITY0; + assign #(in_delay) RXPOLARITY1_IN = RXPOLARITY1; + assign #(in_delay) RXPOWERDOWN0_IN = RXPOWERDOWN0; + assign #(in_delay) RXPOWERDOWN1_IN = RXPOWERDOWN1; + assign #(in_delay) RXRESET0_IN = RXRESET0; + assign #(in_delay) RXRESET1_IN = RXRESET1; + assign #(in_delay) RXSLIDE0_IN = RXSLIDE0; + assign #(in_delay) RXSLIDE1_IN = RXSLIDE1; + assign #(in_delay) TSTIN0_IN = TSTIN0; + assign #(in_delay) TSTIN1_IN = TSTIN1; + assign #(in_delay) TXBUFDIFFCTRL0_IN = TXBUFDIFFCTRL0; + assign #(in_delay) TXBUFDIFFCTRL1_IN = TXBUFDIFFCTRL1; + assign #(in_delay) TXBYPASS8B10B0_IN = TXBYPASS8B10B0; + assign #(in_delay) TXBYPASS8B10B1_IN = TXBYPASS8B10B1; + assign #(in_delay) TXCHARDISPMODE0_IN = TXCHARDISPMODE0; + assign #(in_delay) TXCHARDISPMODE1_IN = TXCHARDISPMODE1; + assign #(in_delay) TXCHARDISPVAL0_IN = TXCHARDISPVAL0; + assign #(in_delay) TXCHARDISPVAL1_IN = TXCHARDISPVAL1; + assign #(in_delay) TXCHARISK0_IN = TXCHARISK0; + assign #(in_delay) TXCHARISK1_IN = TXCHARISK1; + assign #(in_delay) TXCOMSTART0_IN = TXCOMSTART0; + assign #(in_delay) TXCOMSTART1_IN = TXCOMSTART1; + assign #(in_delay) TXCOMTYPE0_IN = TXCOMTYPE0; + assign #(in_delay) TXCOMTYPE1_IN = TXCOMTYPE1; + assign #(in_delay) TXDATA0_IN = TXDATA0; + assign #(in_delay) TXDATA1_IN = TXDATA1; + assign #(in_delay) TXDATAWIDTH0_IN = TXDATAWIDTH0; + assign #(in_delay) TXDATAWIDTH1_IN = TXDATAWIDTH1; + assign #(in_delay) TXDETECTRX0_IN = TXDETECTRX0; + assign #(in_delay) TXDETECTRX1_IN = TXDETECTRX1; + assign #(in_delay) TXDIFFCTRL0_IN = TXDIFFCTRL0; + assign #(in_delay) TXDIFFCTRL1_IN = TXDIFFCTRL1; + assign #(in_delay) TXELECIDLE0_IN = TXELECIDLE0; + assign #(in_delay) TXELECIDLE1_IN = TXELECIDLE1; + assign #(in_delay) TXENC8B10BUSE0_IN = TXENC8B10BUSE0; + assign #(in_delay) TXENC8B10BUSE1_IN = TXENC8B10BUSE1; + assign #(in_delay) TXENPMAPHASEALIGN0_IN = TXENPMAPHASEALIGN0; + assign #(in_delay) TXENPMAPHASEALIGN1_IN = TXENPMAPHASEALIGN1; + assign #(in_delay) TXENPRBSTST0_IN = TXENPRBSTST0; + assign #(in_delay) TXENPRBSTST1_IN = TXENPRBSTST1; + assign #(in_delay) TXINHIBIT0_IN = TXINHIBIT0; + assign #(in_delay) TXINHIBIT1_IN = TXINHIBIT1; + assign #(in_delay) TXPDOWNASYNCH0_IN = TXPDOWNASYNCH0; + assign #(in_delay) TXPDOWNASYNCH1_IN = TXPDOWNASYNCH1; + assign #(in_delay) TXPMASETPHASE0_IN = TXPMASETPHASE0; + assign #(in_delay) TXPMASETPHASE1_IN = TXPMASETPHASE1; + assign #(in_delay) TXPOLARITY0_IN = TXPOLARITY0; + assign #(in_delay) TXPOLARITY1_IN = TXPOLARITY1; + assign #(in_delay) TXPOWERDOWN0_IN = TXPOWERDOWN0; + assign #(in_delay) TXPOWERDOWN1_IN = TXPOWERDOWN1; + assign #(in_delay) TXPRBSFORCEERR0_IN = TXPRBSFORCEERR0; + assign #(in_delay) TXPRBSFORCEERR1_IN = TXPRBSFORCEERR1; + assign #(in_delay) TXPREEMPHASIS0_IN = TXPREEMPHASIS0; + assign #(in_delay) TXPREEMPHASIS1_IN = TXPREEMPHASIS1; + assign #(in_delay) TXRESET0_IN = TXRESET0; + assign #(in_delay) TXRESET1_IN = TXRESET1; + assign #(in_delay) USRCODEERR0_IN = USRCODEERR0; + assign #(in_delay) USRCODEERR1_IN = USRCODEERR1; + assign GTPCLKOUT0_OUT = delay_GTPCLKOUT0; + assign GTPCLKOUT1_OUT = delay_GTPCLKOUT1; + assign REFCLKPLL0_OUT = delay_REFCLKPLL0; + assign REFCLKPLL1_OUT = delay_REFCLKPLL1; + + assign DRDY_OUT = delay_DRDY; + assign DRPDO_OUT = delay_DRPDO; + assign GTPCLKFBEAST_OUT = delay_GTPCLKFBEAST; + assign GTPCLKFBWEST_OUT = delay_GTPCLKFBWEST; + assign PHYSTATUS0_OUT = delay_PHYSTATUS0; + assign PHYSTATUS1_OUT = delay_PHYSTATUS1; + assign PLLLKDET0_OUT = delay_PLLLKDET0; + assign PLLLKDET1_OUT = delay_PLLLKDET1; + assign RCALOUTEAST_OUT = delay_RCALOUTEAST; + assign RCALOUTWEST_OUT = delay_RCALOUTWEST; + assign REFCLKOUT0_OUT = delay_REFCLKOUT0; + assign REFCLKOUT1_OUT = delay_REFCLKOUT1; + assign RESETDONE0_OUT = delay_RESETDONE0; + assign RESETDONE1_OUT = delay_RESETDONE1; + assign RXBUFSTATUS0_OUT = delay_RXBUFSTATUS0; + assign RXBUFSTATUS1_OUT = delay_RXBUFSTATUS1; + assign RXBYTEISALIGNED0_OUT = delay_RXBYTEISALIGNED0; + assign RXBYTEISALIGNED1_OUT = delay_RXBYTEISALIGNED1; + assign RXBYTEREALIGN0_OUT = delay_RXBYTEREALIGN0; + assign RXBYTEREALIGN1_OUT = delay_RXBYTEREALIGN1; + assign RXCHANBONDSEQ0_OUT = delay_RXCHANBONDSEQ0; + assign RXCHANBONDSEQ1_OUT = delay_RXCHANBONDSEQ1; + assign RXCHANISALIGNED0_OUT = delay_RXCHANISALIGNED0; + assign RXCHANISALIGNED1_OUT = delay_RXCHANISALIGNED1; + assign RXCHANREALIGN0_OUT = delay_RXCHANREALIGN0; + assign RXCHANREALIGN1_OUT = delay_RXCHANREALIGN1; + assign RXCHARISCOMMA0_OUT = delay_RXCHARISCOMMA0; + assign RXCHARISCOMMA1_OUT = delay_RXCHARISCOMMA1; + assign RXCHARISK0_OUT = delay_RXCHARISK0; + assign RXCHARISK1_OUT = delay_RXCHARISK1; + assign RXCHBONDO_OUT = delay_RXCHBONDO; + assign RXCLKCORCNT0_OUT = delay_RXCLKCORCNT0; + assign RXCLKCORCNT1_OUT = delay_RXCLKCORCNT1; + assign RXCOMMADET0_OUT = delay_RXCOMMADET0; + assign RXCOMMADET1_OUT = delay_RXCOMMADET1; + assign RXDATA0_OUT = delay_RXDATA0; + assign RXDATA1_OUT = delay_RXDATA1; + assign RXDISPERR0_OUT = delay_RXDISPERR0; + assign RXDISPERR1_OUT = delay_RXDISPERR1; + assign RXELECIDLE0_OUT = delay_RXELECIDLE0; + assign RXELECIDLE1_OUT = delay_RXELECIDLE1; + assign RXLOSSOFSYNC0_OUT = delay_RXLOSSOFSYNC0; + assign RXLOSSOFSYNC1_OUT = delay_RXLOSSOFSYNC1; + assign RXNOTINTABLE0_OUT = delay_RXNOTINTABLE0; + assign RXNOTINTABLE1_OUT = delay_RXNOTINTABLE1; + assign RXPRBSERR0_OUT = delay_RXPRBSERR0; + assign RXPRBSERR1_OUT = delay_RXPRBSERR1; + assign RXRECCLK0_OUT = delay_RXRECCLK0; + assign RXRECCLK1_OUT = delay_RXRECCLK1; + assign RXRUNDISP0_OUT = delay_RXRUNDISP0; + assign RXRUNDISP1_OUT = delay_RXRUNDISP1; + assign RXSTATUS0_OUT = delay_RXSTATUS0; + assign RXSTATUS1_OUT = delay_RXSTATUS1; + assign RXVALID0_OUT = delay_RXVALID0; + assign RXVALID1_OUT = delay_RXVALID1; + assign TSTOUT0_OUT = delay_TSTOUT0; + assign TSTOUT1_OUT = delay_TSTOUT1; + assign TXBUFSTATUS0_OUT = delay_TXBUFSTATUS0; + assign TXBUFSTATUS1_OUT = delay_TXBUFSTATUS1; + assign TXKERR0_OUT = delay_TXKERR0; + assign TXKERR1_OUT = delay_TXKERR1; + assign TXN0_OUT = delay_TXN0; + assign TXN1_OUT = delay_TXN1; + assign TXOUTCLK0_OUT = delay_TXOUTCLK0; + assign TXOUTCLK1_OUT = delay_TXOUTCLK1; + assign TXP0_OUT = delay_TXP0; + assign TXP1_OUT = delay_TXP1; + assign TXRUNDISP0_OUT = delay_TXRUNDISP0; + assign TXRUNDISP1_OUT = delay_TXRUNDISP1; + + assign delay_CLK00 = CLK00_IN; + assign delay_CLK01 = CLK01_IN; + assign delay_CLK10 = CLK10_IN; + assign delay_CLK11 = CLK11_IN; + assign delay_CLKINEAST0 = CLKINEAST0_IN; + assign delay_CLKINEAST1 = CLKINEAST1_IN; + assign delay_CLKINWEST0 = CLKINWEST0_IN; + assign delay_CLKINWEST1 = CLKINWEST1_IN; + assign delay_DCLK = DCLK_IN; + assign delay_GCLK00 = GCLK00_IN; + assign delay_GCLK01 = GCLK01_IN; + assign delay_GCLK10 = GCLK10_IN; + assign delay_GCLK11 = GCLK11_IN; + assign delay_PLLCLK00 = PLLCLK00_IN; + assign delay_PLLCLK01 = PLLCLK01_IN; + assign delay_PLLCLK10 = PLLCLK10_IN; + assign delay_PLLCLK11 = PLLCLK11_IN; + assign delay_RXUSRCLK0 = RXUSRCLK0_IN; + assign delay_RXUSRCLK1 = RXUSRCLK1_IN; + assign delay_RXUSRCLK20 = RXUSRCLK20_IN; + assign delay_RXUSRCLK21 = RXUSRCLK21_IN; + assign delay_TSTCLK0 = TSTCLK0_IN; + assign delay_TSTCLK1 = TSTCLK1_IN; + assign delay_TXUSRCLK0 = TXUSRCLK0_IN; + assign delay_TXUSRCLK1 = TXUSRCLK1_IN; + assign delay_TXUSRCLK20 = TXUSRCLK20_IN; + assign delay_TXUSRCLK21 = TXUSRCLK21_IN; + + assign delay_DADDR = DADDR_IN; + assign delay_DEN = DEN_IN; + assign delay_DI = DI_IN; + assign delay_DWE = DWE_IN; + assign delay_GATERXELECIDLE0 = GATERXELECIDLE0_IN; + assign delay_GATERXELECIDLE1 = GATERXELECIDLE1_IN; + assign delay_GTPCLKFBSEL0EAST = GTPCLKFBSEL0EAST_IN; + assign delay_GTPCLKFBSEL0WEST = GTPCLKFBSEL0WEST_IN; + assign delay_GTPCLKFBSEL1EAST = GTPCLKFBSEL1EAST_IN; + assign delay_GTPCLKFBSEL1WEST = GTPCLKFBSEL1WEST_IN; + assign delay_GTPRESET0 = GTPRESET0_IN; + assign delay_GTPRESET1 = GTPRESET1_IN; + assign delay_GTPTEST0 = GTPTEST0_IN; + assign delay_GTPTEST1 = GTPTEST1_IN; + assign delay_IGNORESIGDET0 = IGNORESIGDET0_IN; + assign delay_IGNORESIGDET1 = IGNORESIGDET1_IN; + assign delay_INTDATAWIDTH0 = INTDATAWIDTH0_IN; + assign delay_INTDATAWIDTH1 = INTDATAWIDTH1_IN; + assign delay_LOOPBACK0 = LOOPBACK0_IN; + assign delay_LOOPBACK1 = LOOPBACK1_IN; + assign delay_PLLLKDETEN0 = PLLLKDETEN0_IN; + assign delay_PLLLKDETEN1 = PLLLKDETEN1_IN; + assign delay_PLLPOWERDOWN0 = PLLPOWERDOWN0_IN; + assign delay_PLLPOWERDOWN1 = PLLPOWERDOWN1_IN; + assign delay_PRBSCNTRESET0 = PRBSCNTRESET0_IN; + assign delay_PRBSCNTRESET1 = PRBSCNTRESET1_IN; + assign delay_RCALINEAST = RCALINEAST_IN; + assign delay_RCALINWEST = RCALINWEST_IN; + assign delay_REFCLKPWRDNB0 = REFCLKPWRDNB0_IN; + assign delay_REFCLKPWRDNB1 = REFCLKPWRDNB1_IN; + assign delay_REFSELDYPLL0 = REFSELDYPLL0_IN; + assign delay_REFSELDYPLL1 = REFSELDYPLL1_IN; + assign delay_RXBUFRESET0 = RXBUFRESET0_IN; + assign delay_RXBUFRESET1 = RXBUFRESET1_IN; + assign delay_RXCDRRESET0 = RXCDRRESET0_IN; + assign delay_RXCDRRESET1 = RXCDRRESET1_IN; + assign delay_RXCHBONDI = RXCHBONDI_IN; + assign delay_RXCHBONDMASTER0 = RXCHBONDMASTER0_IN; + assign delay_RXCHBONDMASTER1 = RXCHBONDMASTER1_IN; + assign delay_RXCHBONDSLAVE0 = RXCHBONDSLAVE0_IN; + assign delay_RXCHBONDSLAVE1 = RXCHBONDSLAVE1_IN; + assign delay_RXCOMMADETUSE0 = RXCOMMADETUSE0_IN; + assign delay_RXCOMMADETUSE1 = RXCOMMADETUSE1_IN; + assign delay_RXDATAWIDTH0 = RXDATAWIDTH0_IN; + assign delay_RXDATAWIDTH1 = RXDATAWIDTH1_IN; + assign delay_RXDEC8B10BUSE0 = RXDEC8B10BUSE0_IN; + assign delay_RXDEC8B10BUSE1 = RXDEC8B10BUSE1_IN; + assign delay_RXENCHANSYNC0 = RXENCHANSYNC0_IN; + assign delay_RXENCHANSYNC1 = RXENCHANSYNC1_IN; + assign delay_RXENMCOMMAALIGN0 = RXENMCOMMAALIGN0_IN; + assign delay_RXENMCOMMAALIGN1 = RXENMCOMMAALIGN1_IN; + assign delay_RXENPCOMMAALIGN0 = RXENPCOMMAALIGN0_IN; + assign delay_RXENPCOMMAALIGN1 = RXENPCOMMAALIGN1_IN; + assign delay_RXENPMAPHASEALIGN0 = RXENPMAPHASEALIGN0_IN; + assign delay_RXENPMAPHASEALIGN1 = RXENPMAPHASEALIGN1_IN; + assign delay_RXENPRBSTST0 = RXENPRBSTST0_IN; + assign delay_RXENPRBSTST1 = RXENPRBSTST1_IN; + assign delay_RXEQMIX0 = RXEQMIX0_IN; + assign delay_RXEQMIX1 = RXEQMIX1_IN; + assign delay_RXN0 = RXN0_IN; + assign delay_RXN1 = RXN1_IN; + assign delay_RXP0 = RXP0_IN; + assign delay_RXP1 = RXP1_IN; + assign delay_RXPMASETPHASE0 = RXPMASETPHASE0_IN; + assign delay_RXPMASETPHASE1 = RXPMASETPHASE1_IN; + assign delay_RXPOLARITY0 = RXPOLARITY0_IN; + assign delay_RXPOLARITY1 = RXPOLARITY1_IN; + assign delay_RXPOWERDOWN0 = RXPOWERDOWN0_IN; + assign delay_RXPOWERDOWN1 = RXPOWERDOWN1_IN; + assign delay_RXRESET0 = RXRESET0_IN; + assign delay_RXRESET1 = RXRESET1_IN; + assign delay_RXSLIDE0 = RXSLIDE0_IN; + assign delay_RXSLIDE1 = RXSLIDE1_IN; + assign delay_TSTIN0 = TSTIN0_IN; + assign delay_TSTIN1 = TSTIN1_IN; + assign delay_TXBUFDIFFCTRL0 = TXBUFDIFFCTRL0_IN; + assign delay_TXBUFDIFFCTRL1 = TXBUFDIFFCTRL1_IN; + assign delay_TXBYPASS8B10B0 = TXBYPASS8B10B0_IN; + assign delay_TXBYPASS8B10B1 = TXBYPASS8B10B1_IN; + assign delay_TXCHARDISPMODE0 = TXCHARDISPMODE0_IN; + assign delay_TXCHARDISPMODE1 = TXCHARDISPMODE1_IN; + assign delay_TXCHARDISPVAL0 = TXCHARDISPVAL0_IN; + assign delay_TXCHARDISPVAL1 = TXCHARDISPVAL1_IN; + assign delay_TXCHARISK0 = TXCHARISK0_IN; + assign delay_TXCHARISK1 = TXCHARISK1_IN; + assign delay_TXCOMSTART0 = TXCOMSTART0_IN; + assign delay_TXCOMSTART1 = TXCOMSTART1_IN; + assign delay_TXCOMTYPE0 = TXCOMTYPE0_IN; + assign delay_TXCOMTYPE1 = TXCOMTYPE1_IN; + assign delay_TXDATA0 = TXDATA0_IN; + assign delay_TXDATA1 = TXDATA1_IN; + assign delay_TXDATAWIDTH0 = TXDATAWIDTH0_IN; + assign delay_TXDATAWIDTH1 = TXDATAWIDTH1_IN; + assign delay_TXDETECTRX0 = TXDETECTRX0_IN; + assign delay_TXDETECTRX1 = TXDETECTRX1_IN; + assign delay_TXDIFFCTRL0 = TXDIFFCTRL0_IN; + assign delay_TXDIFFCTRL1 = TXDIFFCTRL1_IN; + assign delay_TXELECIDLE0 = TXELECIDLE0_IN; + assign delay_TXELECIDLE1 = TXELECIDLE1_IN; + assign delay_TXENC8B10BUSE0 = TXENC8B10BUSE0_IN; + assign delay_TXENC8B10BUSE1 = TXENC8B10BUSE1_IN; + assign delay_TXENPMAPHASEALIGN0 = TXENPMAPHASEALIGN0_IN; + assign delay_TXENPMAPHASEALIGN1 = TXENPMAPHASEALIGN1_IN; + assign delay_TXENPRBSTST0 = TXENPRBSTST0_IN; + assign delay_TXENPRBSTST1 = TXENPRBSTST1_IN; + assign delay_TXINHIBIT0 = TXINHIBIT0_IN; + assign delay_TXINHIBIT1 = TXINHIBIT1_IN; + assign delay_TXPDOWNASYNCH0 = TXPDOWNASYNCH0_IN; + assign delay_TXPDOWNASYNCH1 = TXPDOWNASYNCH1_IN; + assign delay_TXPMASETPHASE0 = TXPMASETPHASE0_IN; + assign delay_TXPMASETPHASE1 = TXPMASETPHASE1_IN; + assign delay_TXPOLARITY0 = TXPOLARITY0_IN; + assign delay_TXPOLARITY1 = TXPOLARITY1_IN; + assign delay_TXPOWERDOWN0 = TXPOWERDOWN0_IN; + assign delay_TXPOWERDOWN1 = TXPOWERDOWN1_IN; + assign delay_TXPRBSFORCEERR0 = TXPRBSFORCEERR0_IN; + assign delay_TXPRBSFORCEERR1 = TXPRBSFORCEERR1_IN; + assign delay_TXPREEMPHASIS0 = TXPREEMPHASIS0_IN; + assign delay_TXPREEMPHASIS1 = TXPREEMPHASIS1_IN; + assign delay_TXRESET0 = TXRESET0_IN; + assign delay_TXRESET1 = TXRESET1_IN; + assign delay_USRCODEERR0 = USRCODEERR0_IN; + assign delay_USRCODEERR1 = USRCODEERR1_IN; + + + B_GTPA1_DUAL #( + .AC_CAP_DIS_0 (AC_CAP_DIS_0), + .AC_CAP_DIS_1 (AC_CAP_DIS_1), + .ALIGN_COMMA_WORD_0 (ALIGN_COMMA_WORD_0), + .ALIGN_COMMA_WORD_1 (ALIGN_COMMA_WORD_1), + .CB2_INH_CC_PERIOD_0 (CB2_INH_CC_PERIOD_0), + .CB2_INH_CC_PERIOD_1 (CB2_INH_CC_PERIOD_1), + .CDR_PH_ADJ_TIME_0 (CDR_PH_ADJ_TIME_0), + .CDR_PH_ADJ_TIME_1 (CDR_PH_ADJ_TIME_1), + .CHAN_BOND_1_MAX_SKEW_0 (CHAN_BOND_1_MAX_SKEW_0), + .CHAN_BOND_1_MAX_SKEW_1 (CHAN_BOND_1_MAX_SKEW_1), + .CHAN_BOND_2_MAX_SKEW_0 (CHAN_BOND_2_MAX_SKEW_0), + .CHAN_BOND_2_MAX_SKEW_1 (CHAN_BOND_2_MAX_SKEW_1), + .CHAN_BOND_KEEP_ALIGN_0 (CHAN_BOND_KEEP_ALIGN_0), + .CHAN_BOND_KEEP_ALIGN_1 (CHAN_BOND_KEEP_ALIGN_1), + .CHAN_BOND_SEQ_1_1_0 (CHAN_BOND_SEQ_1_1_0), + .CHAN_BOND_SEQ_1_1_1 (CHAN_BOND_SEQ_1_1_1), + .CHAN_BOND_SEQ_1_2_0 (CHAN_BOND_SEQ_1_2_0), + .CHAN_BOND_SEQ_1_2_1 (CHAN_BOND_SEQ_1_2_1), + .CHAN_BOND_SEQ_1_3_0 (CHAN_BOND_SEQ_1_3_0), + .CHAN_BOND_SEQ_1_3_1 (CHAN_BOND_SEQ_1_3_1), + .CHAN_BOND_SEQ_1_4_0 (CHAN_BOND_SEQ_1_4_0), + .CHAN_BOND_SEQ_1_4_1 (CHAN_BOND_SEQ_1_4_1), + .CHAN_BOND_SEQ_1_ENABLE_0 (CHAN_BOND_SEQ_1_ENABLE_0), + .CHAN_BOND_SEQ_1_ENABLE_1 (CHAN_BOND_SEQ_1_ENABLE_1), + .CHAN_BOND_SEQ_2_1_0 (CHAN_BOND_SEQ_2_1_0), + .CHAN_BOND_SEQ_2_1_1 (CHAN_BOND_SEQ_2_1_1), + .CHAN_BOND_SEQ_2_2_0 (CHAN_BOND_SEQ_2_2_0), + .CHAN_BOND_SEQ_2_2_1 (CHAN_BOND_SEQ_2_2_1), + .CHAN_BOND_SEQ_2_3_0 (CHAN_BOND_SEQ_2_3_0), + .CHAN_BOND_SEQ_2_3_1 (CHAN_BOND_SEQ_2_3_1), + .CHAN_BOND_SEQ_2_4_0 (CHAN_BOND_SEQ_2_4_0), + .CHAN_BOND_SEQ_2_4_1 (CHAN_BOND_SEQ_2_4_1), + .CHAN_BOND_SEQ_2_ENABLE_0 (CHAN_BOND_SEQ_2_ENABLE_0), + .CHAN_BOND_SEQ_2_ENABLE_1 (CHAN_BOND_SEQ_2_ENABLE_1), + .CHAN_BOND_SEQ_2_USE_0 (CHAN_BOND_SEQ_2_USE_0), + .CHAN_BOND_SEQ_2_USE_1 (CHAN_BOND_SEQ_2_USE_1), + .CHAN_BOND_SEQ_LEN_0 (CHAN_BOND_SEQ_LEN_0), + .CHAN_BOND_SEQ_LEN_1 (CHAN_BOND_SEQ_LEN_1), + .CLK25_DIVIDER_0 (CLK25_DIVIDER_0), + .CLK25_DIVIDER_1 (CLK25_DIVIDER_1), + .CLKINDC_B_0 (CLKINDC_B_0), + .CLKINDC_B_1 (CLKINDC_B_1), + .CLKRCV_TRST_0 (CLKRCV_TRST_0), + .CLKRCV_TRST_1 (CLKRCV_TRST_1), + .CLK_CORRECT_USE_0 (CLK_CORRECT_USE_0), + .CLK_CORRECT_USE_1 (CLK_CORRECT_USE_1), + .CLK_COR_ADJ_LEN_0 (CLK_COR_ADJ_LEN_0), + .CLK_COR_ADJ_LEN_1 (CLK_COR_ADJ_LEN_1), + .CLK_COR_DET_LEN_0 (CLK_COR_DET_LEN_0), + .CLK_COR_DET_LEN_1 (CLK_COR_DET_LEN_1), + .CLK_COR_INSERT_IDLE_FLAG_0 (CLK_COR_INSERT_IDLE_FLAG_0), + .CLK_COR_INSERT_IDLE_FLAG_1 (CLK_COR_INSERT_IDLE_FLAG_1), + .CLK_COR_KEEP_IDLE_0 (CLK_COR_KEEP_IDLE_0), + .CLK_COR_KEEP_IDLE_1 (CLK_COR_KEEP_IDLE_1), + .CLK_COR_MAX_LAT_0 (CLK_COR_MAX_LAT_0), + .CLK_COR_MAX_LAT_1 (CLK_COR_MAX_LAT_1), + .CLK_COR_MIN_LAT_0 (CLK_COR_MIN_LAT_0), + .CLK_COR_MIN_LAT_1 (CLK_COR_MIN_LAT_1), + .CLK_COR_PRECEDENCE_0 (CLK_COR_PRECEDENCE_0), + .CLK_COR_PRECEDENCE_1 (CLK_COR_PRECEDENCE_1), + .CLK_COR_REPEAT_WAIT_0 (CLK_COR_REPEAT_WAIT_0), + .CLK_COR_REPEAT_WAIT_1 (CLK_COR_REPEAT_WAIT_1), + .CLK_COR_SEQ_1_1_0 (CLK_COR_SEQ_1_1_0), + .CLK_COR_SEQ_1_1_1 (CLK_COR_SEQ_1_1_1), + .CLK_COR_SEQ_1_2_0 (CLK_COR_SEQ_1_2_0), + .CLK_COR_SEQ_1_2_1 (CLK_COR_SEQ_1_2_1), + .CLK_COR_SEQ_1_3_0 (CLK_COR_SEQ_1_3_0), + .CLK_COR_SEQ_1_3_1 (CLK_COR_SEQ_1_3_1), + .CLK_COR_SEQ_1_4_0 (CLK_COR_SEQ_1_4_0), + .CLK_COR_SEQ_1_4_1 (CLK_COR_SEQ_1_4_1), + .CLK_COR_SEQ_1_ENABLE_0 (CLK_COR_SEQ_1_ENABLE_0), + .CLK_COR_SEQ_1_ENABLE_1 (CLK_COR_SEQ_1_ENABLE_1), + .CLK_COR_SEQ_2_1_0 (CLK_COR_SEQ_2_1_0), + .CLK_COR_SEQ_2_1_1 (CLK_COR_SEQ_2_1_1), + .CLK_COR_SEQ_2_2_0 (CLK_COR_SEQ_2_2_0), + .CLK_COR_SEQ_2_2_1 (CLK_COR_SEQ_2_2_1), + .CLK_COR_SEQ_2_3_0 (CLK_COR_SEQ_2_3_0), + .CLK_COR_SEQ_2_3_1 (CLK_COR_SEQ_2_3_1), + .CLK_COR_SEQ_2_4_0 (CLK_COR_SEQ_2_4_0), + .CLK_COR_SEQ_2_4_1 (CLK_COR_SEQ_2_4_1), + .CLK_COR_SEQ_2_ENABLE_0 (CLK_COR_SEQ_2_ENABLE_0), + .CLK_COR_SEQ_2_ENABLE_1 (CLK_COR_SEQ_2_ENABLE_1), + .CLK_COR_SEQ_2_USE_0 (CLK_COR_SEQ_2_USE_0), + .CLK_COR_SEQ_2_USE_1 (CLK_COR_SEQ_2_USE_1), + .CLK_OUT_GTP_SEL_0 (CLK_OUT_GTP_SEL_0), + .CLK_OUT_GTP_SEL_1 (CLK_OUT_GTP_SEL_1), + .CM_TRIM_0 (CM_TRIM_0), + .CM_TRIM_1 (CM_TRIM_1), + .COMMA_10B_ENABLE_0 (COMMA_10B_ENABLE_0), + .COMMA_10B_ENABLE_1 (COMMA_10B_ENABLE_1), + .COM_BURST_VAL_0 (COM_BURST_VAL_0), + .COM_BURST_VAL_1 (COM_BURST_VAL_1), + .DEC_MCOMMA_DETECT_0 (DEC_MCOMMA_DETECT_0), + .DEC_MCOMMA_DETECT_1 (DEC_MCOMMA_DETECT_1), + .DEC_PCOMMA_DETECT_0 (DEC_PCOMMA_DETECT_0), + .DEC_PCOMMA_DETECT_1 (DEC_PCOMMA_DETECT_1), + .DEC_VALID_COMMA_ONLY_0 (DEC_VALID_COMMA_ONLY_0), + .DEC_VALID_COMMA_ONLY_1 (DEC_VALID_COMMA_ONLY_1), + .GTP_CFG_PWRUP_0 (GTP_CFG_PWRUP_0), + .GTP_CFG_PWRUP_1 (GTP_CFG_PWRUP_1), + .MCOMMA_10B_VALUE_0 (MCOMMA_10B_VALUE_0), + .MCOMMA_10B_VALUE_1 (MCOMMA_10B_VALUE_1), + .MCOMMA_DETECT_0 (MCOMMA_DETECT_0), + .MCOMMA_DETECT_1 (MCOMMA_DETECT_1), + .OOBDETECT_THRESHOLD_0 (OOBDETECT_THRESHOLD_0), + .OOBDETECT_THRESHOLD_1 (OOBDETECT_THRESHOLD_1), + .OOB_CLK_DIVIDER_0 (OOB_CLK_DIVIDER_0), + .OOB_CLK_DIVIDER_1 (OOB_CLK_DIVIDER_1), + .PCI_EXPRESS_MODE_0 (PCI_EXPRESS_MODE_0), + .PCI_EXPRESS_MODE_1 (PCI_EXPRESS_MODE_1), + .PCOMMA_10B_VALUE_0 (PCOMMA_10B_VALUE_0), + .PCOMMA_10B_VALUE_1 (PCOMMA_10B_VALUE_1), + .PCOMMA_DETECT_0 (PCOMMA_DETECT_0), + .PCOMMA_DETECT_1 (PCOMMA_DETECT_1), + .PLLLKDET_CFG_0 (PLLLKDET_CFG_0), + .PLLLKDET_CFG_1 (PLLLKDET_CFG_1), + .PLL_COM_CFG_0 (PLL_COM_CFG_0), + .PLL_COM_CFG_1 (PLL_COM_CFG_1), + .PLL_CP_CFG_0 (PLL_CP_CFG_0), + .PLL_CP_CFG_1 (PLL_CP_CFG_1), + .PLL_DIVSEL_FB_0 (PLL_DIVSEL_FB_0), + .PLL_DIVSEL_FB_1 (PLL_DIVSEL_FB_1), + .PLL_DIVSEL_REF_0 (PLL_DIVSEL_REF_0), + .PLL_DIVSEL_REF_1 (PLL_DIVSEL_REF_1), + .PLL_RXDIVSEL_OUT_0 (PLL_RXDIVSEL_OUT_0), + .PLL_RXDIVSEL_OUT_1 (PLL_RXDIVSEL_OUT_1), + .PLL_SATA_0 (PLL_SATA_0), + .PLL_SATA_1 (PLL_SATA_1), + .PLL_SOURCE_0 (PLL_SOURCE_0), + .PLL_SOURCE_1 (PLL_SOURCE_1), + .PLL_TXDIVSEL_OUT_0 (PLL_TXDIVSEL_OUT_0), + .PLL_TXDIVSEL_OUT_1 (PLL_TXDIVSEL_OUT_1), + .PMA_CDR_SCAN_0 (PMA_CDR_SCAN_0), + .PMA_CDR_SCAN_1 (PMA_CDR_SCAN_1), + .PMA_COM_CFG_EAST (PMA_COM_CFG_EAST), + .PMA_COM_CFG_WEST (PMA_COM_CFG_WEST), + .PMA_RXSYNC_CFG_0 (PMA_RXSYNC_CFG_0), + .PMA_RXSYNC_CFG_1 (PMA_RXSYNC_CFG_1), + .PMA_RX_CFG_0 (PMA_RX_CFG_0), + .PMA_RX_CFG_1 (PMA_RX_CFG_1), + .PMA_TX_CFG_0 (PMA_TX_CFG_0), + .PMA_TX_CFG_1 (PMA_TX_CFG_1), + .RCV_TERM_GND_0 (RCV_TERM_GND_0), + .RCV_TERM_GND_1 (RCV_TERM_GND_1), + .RCV_TERM_VTTRX_0 (RCV_TERM_VTTRX_0), + .RCV_TERM_VTTRX_1 (RCV_TERM_VTTRX_1), + .RXEQ_CFG_0 (RXEQ_CFG_0), + .RXEQ_CFG_1 (RXEQ_CFG_1), + .RXPRBSERR_LOOPBACK_0 (RXPRBSERR_LOOPBACK_0), + .RXPRBSERR_LOOPBACK_1 (RXPRBSERR_LOOPBACK_1), + .RX_BUFFER_USE_0 (RX_BUFFER_USE_0), + .RX_BUFFER_USE_1 (RX_BUFFER_USE_1), + .RX_DECODE_SEQ_MATCH_0 (RX_DECODE_SEQ_MATCH_0), + .RX_DECODE_SEQ_MATCH_1 (RX_DECODE_SEQ_MATCH_1), + .RX_EN_IDLE_HOLD_CDR_0 (RX_EN_IDLE_HOLD_CDR_0), + .RX_EN_IDLE_HOLD_CDR_1 (RX_EN_IDLE_HOLD_CDR_1), + .RX_EN_IDLE_RESET_BUF_0 (RX_EN_IDLE_RESET_BUF_0), + .RX_EN_IDLE_RESET_BUF_1 (RX_EN_IDLE_RESET_BUF_1), + .RX_EN_IDLE_RESET_FR_0 (RX_EN_IDLE_RESET_FR_0), + .RX_EN_IDLE_RESET_FR_1 (RX_EN_IDLE_RESET_FR_1), + .RX_EN_IDLE_RESET_PH_0 (RX_EN_IDLE_RESET_PH_0), + .RX_EN_IDLE_RESET_PH_1 (RX_EN_IDLE_RESET_PH_1), + .RX_EN_MODE_RESET_BUF_0 (RX_EN_MODE_RESET_BUF_0), + .RX_EN_MODE_RESET_BUF_1 (RX_EN_MODE_RESET_BUF_1), + .RX_IDLE_HI_CNT_0 (RX_IDLE_HI_CNT_0), + .RX_IDLE_HI_CNT_1 (RX_IDLE_HI_CNT_1), + .RX_IDLE_LO_CNT_0 (RX_IDLE_LO_CNT_0), + .RX_IDLE_LO_CNT_1 (RX_IDLE_LO_CNT_1), + .RX_LOSS_OF_SYNC_FSM_0 (RX_LOSS_OF_SYNC_FSM_0), + .RX_LOSS_OF_SYNC_FSM_1 (RX_LOSS_OF_SYNC_FSM_1), + .RX_LOS_INVALID_INCR_0 (RX_LOS_INVALID_INCR_0), + .RX_LOS_INVALID_INCR_1 (RX_LOS_INVALID_INCR_1), + .RX_LOS_THRESHOLD_0 (RX_LOS_THRESHOLD_0), + .RX_LOS_THRESHOLD_1 (RX_LOS_THRESHOLD_1), + .RX_SLIDE_MODE_0 (RX_SLIDE_MODE_0), + .RX_SLIDE_MODE_1 (RX_SLIDE_MODE_1), + .RX_STATUS_FMT_0 (RX_STATUS_FMT_0), + .RX_STATUS_FMT_1 (RX_STATUS_FMT_1), + .RX_XCLK_SEL_0 (RX_XCLK_SEL_0), + .RX_XCLK_SEL_1 (RX_XCLK_SEL_1), + .SATA_BURST_VAL_0 (SATA_BURST_VAL_0), + .SATA_BURST_VAL_1 (SATA_BURST_VAL_1), + .SATA_IDLE_VAL_0 (SATA_IDLE_VAL_0), + .SATA_IDLE_VAL_1 (SATA_IDLE_VAL_1), + .SATA_MAX_BURST_0 (SATA_MAX_BURST_0), + .SATA_MAX_BURST_1 (SATA_MAX_BURST_1), + .SATA_MAX_INIT_0 (SATA_MAX_INIT_0), + .SATA_MAX_INIT_1 (SATA_MAX_INIT_1), + .SATA_MAX_WAKE_0 (SATA_MAX_WAKE_0), + .SATA_MAX_WAKE_1 (SATA_MAX_WAKE_1), + .SATA_MIN_BURST_0 (SATA_MIN_BURST_0), + .SATA_MIN_BURST_1 (SATA_MIN_BURST_1), + .SATA_MIN_INIT_0 (SATA_MIN_INIT_0), + .SATA_MIN_INIT_1 (SATA_MIN_INIT_1), + .SATA_MIN_WAKE_0 (SATA_MIN_WAKE_0), + .SATA_MIN_WAKE_1 (SATA_MIN_WAKE_1), + .SIM_GTPRESET_SPEEDUP (SIM_GTPRESET_SPEEDUP), + .SIM_RECEIVER_DETECT_PASS (SIM_RECEIVER_DETECT_PASS), + .SIM_REFCLK0_SOURCE (SIM_REFCLK0_SOURCE), + .SIM_REFCLK1_SOURCE (SIM_REFCLK1_SOURCE), + .SIM_TX_ELEC_IDLE_LEVEL (SIM_TX_ELEC_IDLE_LEVEL), + .SIM_VERSION (SIM_VERSION), + .TERMINATION_CTRL_0 (TERMINATION_CTRL_0), + .TERMINATION_CTRL_1 (TERMINATION_CTRL_1), + .TERMINATION_OVRD_0 (TERMINATION_OVRD_0), + .TERMINATION_OVRD_1 (TERMINATION_OVRD_1), + .TRANS_TIME_FROM_P2_0 (TRANS_TIME_FROM_P2_0), + .TRANS_TIME_FROM_P2_1 (TRANS_TIME_FROM_P2_1), + .TRANS_TIME_NON_P2_0 (TRANS_TIME_NON_P2_0), + .TRANS_TIME_NON_P2_1 (TRANS_TIME_NON_P2_1), + .TRANS_TIME_TO_P2_0 (TRANS_TIME_TO_P2_0), + .TRANS_TIME_TO_P2_1 (TRANS_TIME_TO_P2_1), + .TST_ATTR_0 (TST_ATTR_0), + .TST_ATTR_1 (TST_ATTR_1), + .TXRX_INVERT_0 (TXRX_INVERT_0), + .TXRX_INVERT_1 (TXRX_INVERT_1), + .TX_BUFFER_USE_0 (TX_BUFFER_USE_0), + .TX_BUFFER_USE_1 (TX_BUFFER_USE_1), + .TX_DETECT_RX_CFG_0 (TX_DETECT_RX_CFG_0), + .TX_DETECT_RX_CFG_1 (TX_DETECT_RX_CFG_1), + .TX_IDLE_DELAY_0 (TX_IDLE_DELAY_0), + .TX_IDLE_DELAY_1 (TX_IDLE_DELAY_1), + .TX_TDCC_CFG_0 (TX_TDCC_CFG_0), + .TX_TDCC_CFG_1 (TX_TDCC_CFG_1), + .TX_XCLK_SEL_0 (TX_XCLK_SEL_0), + .TX_XCLK_SEL_1 (TX_XCLK_SEL_1)) + + B_GTPA1_DUAL_INST ( + .DRDY (delay_DRDY), + .DRPDO (delay_DRPDO), + .GTPCLKFBEAST (delay_GTPCLKFBEAST), + .GTPCLKFBWEST (delay_GTPCLKFBWEST), + .GTPCLKOUT0 (delay_GTPCLKOUT0), + .GTPCLKOUT1 (delay_GTPCLKOUT1), + .PHYSTATUS0 (delay_PHYSTATUS0), + .PHYSTATUS1 (delay_PHYSTATUS1), + .PLLLKDET0 (delay_PLLLKDET0), + .PLLLKDET1 (delay_PLLLKDET1), + .RCALOUTEAST (delay_RCALOUTEAST), + .RCALOUTWEST (delay_RCALOUTWEST), + .REFCLKOUT0 (delay_REFCLKOUT0), + .REFCLKOUT1 (delay_REFCLKOUT1), + .REFCLKPLL0 (delay_REFCLKPLL0), + .REFCLKPLL1 (delay_REFCLKPLL1), + .RESETDONE0 (delay_RESETDONE0), + .RESETDONE1 (delay_RESETDONE1), + .RXBUFSTATUS0 (delay_RXBUFSTATUS0), + .RXBUFSTATUS1 (delay_RXBUFSTATUS1), + .RXBYTEISALIGNED0 (delay_RXBYTEISALIGNED0), + .RXBYTEISALIGNED1 (delay_RXBYTEISALIGNED1), + .RXBYTEREALIGN0 (delay_RXBYTEREALIGN0), + .RXBYTEREALIGN1 (delay_RXBYTEREALIGN1), + .RXCHANBONDSEQ0 (delay_RXCHANBONDSEQ0), + .RXCHANBONDSEQ1 (delay_RXCHANBONDSEQ1), + .RXCHANISALIGNED0 (delay_RXCHANISALIGNED0), + .RXCHANISALIGNED1 (delay_RXCHANISALIGNED1), + .RXCHANREALIGN0 (delay_RXCHANREALIGN0), + .RXCHANREALIGN1 (delay_RXCHANREALIGN1), + .RXCHARISCOMMA0 (delay_RXCHARISCOMMA0), + .RXCHARISCOMMA1 (delay_RXCHARISCOMMA1), + .RXCHARISK0 (delay_RXCHARISK0), + .RXCHARISK1 (delay_RXCHARISK1), + .RXCHBONDO (delay_RXCHBONDO), + .RXCLKCORCNT0 (delay_RXCLKCORCNT0), + .RXCLKCORCNT1 (delay_RXCLKCORCNT1), + .RXCOMMADET0 (delay_RXCOMMADET0), + .RXCOMMADET1 (delay_RXCOMMADET1), + .RXDATA0 (delay_RXDATA0), + .RXDATA1 (delay_RXDATA1), + .RXDISPERR0 (delay_RXDISPERR0), + .RXDISPERR1 (delay_RXDISPERR1), + .RXELECIDLE0 (delay_RXELECIDLE0), + .RXELECIDLE1 (delay_RXELECIDLE1), + .RXLOSSOFSYNC0 (delay_RXLOSSOFSYNC0), + .RXLOSSOFSYNC1 (delay_RXLOSSOFSYNC1), + .RXNOTINTABLE0 (delay_RXNOTINTABLE0), + .RXNOTINTABLE1 (delay_RXNOTINTABLE1), + .RXPRBSERR0 (delay_RXPRBSERR0), + .RXPRBSERR1 (delay_RXPRBSERR1), + .RXRECCLK0 (delay_RXRECCLK0), + .RXRECCLK1 (delay_RXRECCLK1), + .RXRUNDISP0 (delay_RXRUNDISP0), + .RXRUNDISP1 (delay_RXRUNDISP1), + .RXSTATUS0 (delay_RXSTATUS0), + .RXSTATUS1 (delay_RXSTATUS1), + .RXVALID0 (delay_RXVALID0), + .RXVALID1 (delay_RXVALID1), + .TSTOUT0 (delay_TSTOUT0), + .TSTOUT1 (delay_TSTOUT1), + .TXBUFSTATUS0 (delay_TXBUFSTATUS0), + .TXBUFSTATUS1 (delay_TXBUFSTATUS1), + .TXKERR0 (delay_TXKERR0), + .TXKERR1 (delay_TXKERR1), + .TXN0 (delay_TXN0), + .TXN1 (delay_TXN1), + .TXOUTCLK0 (delay_TXOUTCLK0), + .TXOUTCLK1 (delay_TXOUTCLK1), + .TXP0 (delay_TXP0), + .TXP1 (delay_TXP1), + .TXRUNDISP0 (delay_TXRUNDISP0), + .TXRUNDISP1 (delay_TXRUNDISP1), + .CLK00 (delay_CLK00), + .CLK01 (delay_CLK01), + .CLK10 (delay_CLK10), + .CLK11 (delay_CLK11), + .CLKINEAST0 (delay_CLKINEAST0), + .CLKINEAST1 (delay_CLKINEAST1), + .CLKINWEST0 (delay_CLKINWEST0), + .CLKINWEST1 (delay_CLKINWEST1), + .DADDR (delay_DADDR), + .DCLK (delay_DCLK), + .DEN (delay_DEN), + .DI (delay_DI), + .DWE (delay_DWE), + .GATERXELECIDLE0 (delay_GATERXELECIDLE0), + .GATERXELECIDLE1 (delay_GATERXELECIDLE1), + .GCLK00 (delay_GCLK00), + .GCLK01 (delay_GCLK01), + .GCLK10 (delay_GCLK10), + .GCLK11 (delay_GCLK11), + .GTPCLKFBSEL0EAST (delay_GTPCLKFBSEL0EAST), + .GTPCLKFBSEL0WEST (delay_GTPCLKFBSEL0WEST), + .GTPCLKFBSEL1EAST (delay_GTPCLKFBSEL1EAST), + .GTPCLKFBSEL1WEST (delay_GTPCLKFBSEL1WEST), + .GTPRESET0 (delay_GTPRESET0), + .GTPRESET1 (delay_GTPRESET1), + .GTPTEST0 (delay_GTPTEST0), + .GTPTEST1 (delay_GTPTEST1), + .IGNORESIGDET0 (delay_IGNORESIGDET0), + .IGNORESIGDET1 (delay_IGNORESIGDET1), + .INTDATAWIDTH0 (delay_INTDATAWIDTH0), + .INTDATAWIDTH1 (delay_INTDATAWIDTH1), + .LOOPBACK0 (delay_LOOPBACK0), + .LOOPBACK1 (delay_LOOPBACK1), + .PLLCLK00 (delay_PLLCLK00), + .PLLCLK01 (delay_PLLCLK01), + .PLLCLK10 (delay_PLLCLK10), + .PLLCLK11 (delay_PLLCLK11), + .PLLLKDETEN0 (delay_PLLLKDETEN0), + .PLLLKDETEN1 (delay_PLLLKDETEN1), + .PLLPOWERDOWN0 (delay_PLLPOWERDOWN0), + .PLLPOWERDOWN1 (delay_PLLPOWERDOWN1), + .PRBSCNTRESET0 (delay_PRBSCNTRESET0), + .PRBSCNTRESET1 (delay_PRBSCNTRESET1), + .RCALINEAST (delay_RCALINEAST), + .RCALINWEST (delay_RCALINWEST), + .REFCLKPWRDNB0 (delay_REFCLKPWRDNB0), + .REFCLKPWRDNB1 (delay_REFCLKPWRDNB1), + .REFSELDYPLL0 (delay_REFSELDYPLL0), + .REFSELDYPLL1 (delay_REFSELDYPLL1), + .RXBUFRESET0 (delay_RXBUFRESET0), + .RXBUFRESET1 (delay_RXBUFRESET1), + .RXCDRRESET0 (delay_RXCDRRESET0), + .RXCDRRESET1 (delay_RXCDRRESET1), + .RXCHBONDI (delay_RXCHBONDI), + .RXCHBONDMASTER0 (delay_RXCHBONDMASTER0), + .RXCHBONDMASTER1 (delay_RXCHBONDMASTER1), + .RXCHBONDSLAVE0 (delay_RXCHBONDSLAVE0), + .RXCHBONDSLAVE1 (delay_RXCHBONDSLAVE1), + .RXCOMMADETUSE0 (delay_RXCOMMADETUSE0), + .RXCOMMADETUSE1 (delay_RXCOMMADETUSE1), + .RXDATAWIDTH0 (delay_RXDATAWIDTH0), + .RXDATAWIDTH1 (delay_RXDATAWIDTH1), + .RXDEC8B10BUSE0 (delay_RXDEC8B10BUSE0), + .RXDEC8B10BUSE1 (delay_RXDEC8B10BUSE1), + .RXENCHANSYNC0 (delay_RXENCHANSYNC0), + .RXENCHANSYNC1 (delay_RXENCHANSYNC1), + .RXENMCOMMAALIGN0 (delay_RXENMCOMMAALIGN0), + .RXENMCOMMAALIGN1 (delay_RXENMCOMMAALIGN1), + .RXENPCOMMAALIGN0 (delay_RXENPCOMMAALIGN0), + .RXENPCOMMAALIGN1 (delay_RXENPCOMMAALIGN1), + .RXENPMAPHASEALIGN0 (delay_RXENPMAPHASEALIGN0), + .RXENPMAPHASEALIGN1 (delay_RXENPMAPHASEALIGN1), + .RXENPRBSTST0 (delay_RXENPRBSTST0), + .RXENPRBSTST1 (delay_RXENPRBSTST1), + .RXEQMIX0 (delay_RXEQMIX0), + .RXEQMIX1 (delay_RXEQMIX1), + .RXN0 (delay_RXN0), + .RXN1 (delay_RXN1), + .RXP0 (delay_RXP0), + .RXP1 (delay_RXP1), + .RXPMASETPHASE0 (delay_RXPMASETPHASE0), + .RXPMASETPHASE1 (delay_RXPMASETPHASE1), + .RXPOLARITY0 (delay_RXPOLARITY0), + .RXPOLARITY1 (delay_RXPOLARITY1), + .RXPOWERDOWN0 (delay_RXPOWERDOWN0), + .RXPOWERDOWN1 (delay_RXPOWERDOWN1), + .RXRESET0 (delay_RXRESET0), + .RXRESET1 (delay_RXRESET1), + .RXSLIDE0 (delay_RXSLIDE0), + .RXSLIDE1 (delay_RXSLIDE1), + .RXUSRCLK0 (delay_RXUSRCLK0), + .RXUSRCLK1 (delay_RXUSRCLK1), + .RXUSRCLK20 (delay_RXUSRCLK20), + .RXUSRCLK21 (delay_RXUSRCLK21), + .TSTCLK0 (delay_TSTCLK0), + .TSTCLK1 (delay_TSTCLK1), + .TSTIN0 (delay_TSTIN0), + .TSTIN1 (delay_TSTIN1), + .TXBUFDIFFCTRL0 (delay_TXBUFDIFFCTRL0), + .TXBUFDIFFCTRL1 (delay_TXBUFDIFFCTRL1), + .TXBYPASS8B10B0 (delay_TXBYPASS8B10B0), + .TXBYPASS8B10B1 (delay_TXBYPASS8B10B1), + .TXCHARDISPMODE0 (delay_TXCHARDISPMODE0), + .TXCHARDISPMODE1 (delay_TXCHARDISPMODE1), + .TXCHARDISPVAL0 (delay_TXCHARDISPVAL0), + .TXCHARDISPVAL1 (delay_TXCHARDISPVAL1), + .TXCHARISK0 (delay_TXCHARISK0), + .TXCHARISK1 (delay_TXCHARISK1), + .TXCOMSTART0 (delay_TXCOMSTART0), + .TXCOMSTART1 (delay_TXCOMSTART1), + .TXCOMTYPE0 (delay_TXCOMTYPE0), + .TXCOMTYPE1 (delay_TXCOMTYPE1), + .TXDATA0 (delay_TXDATA0), + .TXDATA1 (delay_TXDATA1), + .TXDATAWIDTH0 (delay_TXDATAWIDTH0), + .TXDATAWIDTH1 (delay_TXDATAWIDTH1), + .TXDETECTRX0 (delay_TXDETECTRX0), + .TXDETECTRX1 (delay_TXDETECTRX1), + .TXDIFFCTRL0 (delay_TXDIFFCTRL0), + .TXDIFFCTRL1 (delay_TXDIFFCTRL1), + .TXELECIDLE0 (delay_TXELECIDLE0), + .TXELECIDLE1 (delay_TXELECIDLE1), + .TXENC8B10BUSE0 (delay_TXENC8B10BUSE0), + .TXENC8B10BUSE1 (delay_TXENC8B10BUSE1), + .TXENPMAPHASEALIGN0 (delay_TXENPMAPHASEALIGN0), + .TXENPMAPHASEALIGN1 (delay_TXENPMAPHASEALIGN1), + .TXENPRBSTST0 (delay_TXENPRBSTST0), + .TXENPRBSTST1 (delay_TXENPRBSTST1), + .TXINHIBIT0 (delay_TXINHIBIT0), + .TXINHIBIT1 (delay_TXINHIBIT1), + .TXPDOWNASYNCH0 (delay_TXPDOWNASYNCH0), + .TXPDOWNASYNCH1 (delay_TXPDOWNASYNCH1), + .TXPMASETPHASE0 (delay_TXPMASETPHASE0), + .TXPMASETPHASE1 (delay_TXPMASETPHASE1), + .TXPOLARITY0 (delay_TXPOLARITY0), + .TXPOLARITY1 (delay_TXPOLARITY1), + .TXPOWERDOWN0 (delay_TXPOWERDOWN0), + .TXPOWERDOWN1 (delay_TXPOWERDOWN1), + .TXPRBSFORCEERR0 (delay_TXPRBSFORCEERR0), + .TXPRBSFORCEERR1 (delay_TXPRBSFORCEERR1), + .TXPREEMPHASIS0 (delay_TXPREEMPHASIS0), + .TXPREEMPHASIS1 (delay_TXPREEMPHASIS1), + .TXRESET0 (delay_TXRESET0), + .TXRESET1 (delay_TXRESET1), + .TXUSRCLK0 (delay_TXUSRCLK0), + .TXUSRCLK1 (delay_TXUSRCLK1), + .TXUSRCLK20 (delay_TXUSRCLK20), + .TXUSRCLK21 (delay_TXUSRCLK21), + .USRCODEERR0 (delay_USRCODEERR0), + .USRCODEERR1 (delay_USRCODEERR1), + .GSR(GSR) + ); + +endmodule // GTPA1_DUAL diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/GTP_DUAL.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/GTP_DUAL.v new file mode 100644 index 0000000..3ec678b --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/GTP_DUAL.v @@ -0,0 +1,3548 @@ +/////////////////////////////////////////////////////////// +// Copyright (c) 1995/2006 Xilinx Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////// +// +// ____ ___ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Multi-Gigabit Transceiver +// /__/ /\ Filename : GTP_DUAL.v +// \ \ / \ Timestamp : Fri Mar 24 2006 +// \__\/\__ \ +// +// Revision: +// 12/08/05 - Initial version. +// 01/09/06 - Added case statement, specify block +// 01/27/06 - Updated ONE_UI[10:0] to ONE_UI[31:0] +// 02/23/06 - CR#226003 - Added integer, real parameter type +// - Updated Header +// 03/24/06 - CR#225541 - Updated GTP_DUAL smartmodel version to 0.006 for following updates +// - GTP_DUAL smartmodel not generating DO output on the DRP port properly +// - Renamed some of the ports. +// - Removed some of the attributes. +// - Renamed some of the attributes. +// 04/24/06 - CR#230306 - CLKIN => REFCLKOUT delay added +// 04/27/06 - CR#230642 - Spreadsheet updates for I.31 +// 05/22/06 - CR#231412 - SIM_RECEIVER_DETECT_PASS0/1 attributes added +// 05/23/06 - CR#231962 - Add buffers for connectivity +// 06/22/06 - CR#233879 - Add parameter bus range +// 08/02/06 - CR#235013 - Missing GSR added in SWIFT instantiation +// 10/26/06 - - replaced zero_delay with CLK_DELAY to be consistent with writers (PPC440 update) +// 05/18/07 - CR#439780 - Default attribute value change - PMA_CDR_SCAN0/1, PMA_RX_CFG_0/1, TX_DIFF_BOOST_0/1 +// - PCS_COM_CFG is a user visible attribute +// 05/18/07 - CR#440008 - Specify block timing update - RXCHBONDO0/1 synchronous to RXUSRCLK0, RXCHBONDI0/1 synchronous to RXUSRCLK1 +// 02/19/08 - CR#467686 - Add SIM_MODE attribute with values LEGACY & FAST model +// 05/19/08 - CR#472395 - Remove GTX_DUAL LEGACY model +// 05/27/08 - CR#472395 - Set SIM_MODE to FAST, Add DRC checks +// 07/20/09 - CR#524927 - Adding RXUSRCLK20_PHYSTATUS0 path +// 06/04/10 - CR#563818 - Adding RXUSRCLK21_PHYSTATUS1 path +// End Revision +/////////////////////////////////////////////////////////// + +`timescale 1 ps / 1 ps + +module GTP_DUAL ( + DO, + DRDY, + PHYSTATUS0, + PHYSTATUS1, + PLLLKDET, + REFCLKOUT, + RESETDONE0, + RESETDONE1, + RXBUFSTATUS0, + RXBUFSTATUS1, + RXBYTEISALIGNED0, + RXBYTEISALIGNED1, + RXBYTEREALIGN0, + RXBYTEREALIGN1, + RXCHANBONDSEQ0, + RXCHANBONDSEQ1, + RXCHANISALIGNED0, + RXCHANISALIGNED1, + RXCHANREALIGN0, + RXCHANREALIGN1, + RXCHARISCOMMA0, + RXCHARISCOMMA1, + RXCHARISK0, + RXCHARISK1, + RXCHBONDO0, + RXCHBONDO1, + RXCLKCORCNT0, + RXCLKCORCNT1, + RXCOMMADET0, + RXCOMMADET1, + RXDATA0, + RXDATA1, + RXDISPERR0, + RXDISPERR1, + RXELECIDLE0, + RXELECIDLE1, + RXLOSSOFSYNC0, + RXLOSSOFSYNC1, + RXNOTINTABLE0, + RXNOTINTABLE1, + RXOVERSAMPLEERR0, + RXOVERSAMPLEERR1, + RXPRBSERR0, + RXPRBSERR1, + RXRECCLK0, + RXRECCLK1, + RXRUNDISP0, + RXRUNDISP1, + RXSTATUS0, + RXSTATUS1, + RXVALID0, + RXVALID1, + TXBUFSTATUS0, + TXBUFSTATUS1, + TXKERR0, + TXKERR1, + TXN0, + TXN1, + TXOUTCLK0, + TXOUTCLK1, + TXP0, + TXP1, + TXRUNDISP0, + TXRUNDISP1, + + CLKIN, + DADDR, + DCLK, + DEN, + DI, + DWE, + GTPRESET, + GTPTEST, + INTDATAWIDTH, + LOOPBACK0, + LOOPBACK1, + PLLLKDETEN, + PLLPOWERDOWN, + PRBSCNTRESET0, + PRBSCNTRESET1, + REFCLKPWRDNB, + RXBUFRESET0, + RXBUFRESET1, + RXCDRRESET0, + RXCDRRESET1, + RXCHBONDI0, + RXCHBONDI1, + RXCOMMADETUSE0, + RXCOMMADETUSE1, + RXDATAWIDTH0, + RXDATAWIDTH1, + RXDEC8B10BUSE0, + RXDEC8B10BUSE1, + RXELECIDLERESET0, + RXELECIDLERESET1, + RXENCHANSYNC0, + RXENCHANSYNC1, + RXENELECIDLERESETB, + RXENEQB0, + RXENEQB1, + RXENMCOMMAALIGN0, + RXENMCOMMAALIGN1, + RXENPCOMMAALIGN0, + RXENPCOMMAALIGN1, + RXENPRBSTST0, + RXENPRBSTST1, + RXENSAMPLEALIGN0, + RXENSAMPLEALIGN1, + RXEQMIX0, + RXEQMIX1, + RXEQPOLE0, + RXEQPOLE1, + RXN0, + RXN1, + RXP0, + RXP1, + RXPMASETPHASE0, + RXPMASETPHASE1, + RXPOLARITY0, + RXPOLARITY1, + RXPOWERDOWN0, + RXPOWERDOWN1, + RXRESET0, + RXRESET1, + RXSLIDE0, + RXSLIDE1, + RXUSRCLK0, + RXUSRCLK1, + RXUSRCLK20, + RXUSRCLK21, + TXBUFDIFFCTRL0, + TXBUFDIFFCTRL1, + TXBYPASS8B10B0, + TXBYPASS8B10B1, + TXCHARDISPMODE0, + TXCHARDISPMODE1, + TXCHARDISPVAL0, + TXCHARDISPVAL1, + TXCHARISK0, + TXCHARISK1, + TXCOMSTART0, + TXCOMSTART1, + TXCOMTYPE0, + TXCOMTYPE1, + TXDATA0, + TXDATA1, + TXDATAWIDTH0, + TXDATAWIDTH1, + TXDETECTRX0, + TXDETECTRX1, + TXDIFFCTRL0, + TXDIFFCTRL1, + TXELECIDLE0, + TXELECIDLE1, + TXENC8B10BUSE0, + TXENC8B10BUSE1, + TXENPMAPHASEALIGN, + TXENPRBSTST0, + TXENPRBSTST1, + TXINHIBIT0, + TXINHIBIT1, + TXPMASETPHASE, + TXPOLARITY0, + TXPOLARITY1, + TXPOWERDOWN0, + TXPOWERDOWN1, + TXPREEMPHASIS0, + TXPREEMPHASIS1, + TXRESET0, + TXRESET1, + TXUSRCLK0, + TXUSRCLK1, + TXUSRCLK20, + TXUSRCLK21 + +); + +parameter AC_CAP_DIS_0 = "TRUE"; +parameter AC_CAP_DIS_1 = "TRUE"; +parameter CHAN_BOND_MODE_0 = "OFF"; +parameter CHAN_BOND_MODE_1 = "OFF"; +parameter CHAN_BOND_SEQ_2_USE_0 = "TRUE"; +parameter CHAN_BOND_SEQ_2_USE_1 = "TRUE"; +parameter CLKINDC_B = "TRUE"; +parameter CLK_CORRECT_USE_0 = "TRUE"; +parameter CLK_CORRECT_USE_1 = "TRUE"; +parameter CLK_COR_INSERT_IDLE_FLAG_0 = "FALSE"; +parameter CLK_COR_INSERT_IDLE_FLAG_1 = "FALSE"; +parameter CLK_COR_KEEP_IDLE_0 = "FALSE"; +parameter CLK_COR_KEEP_IDLE_1 = "FALSE"; +parameter CLK_COR_PRECEDENCE_0 = "TRUE"; +parameter CLK_COR_PRECEDENCE_1 = "TRUE"; +parameter CLK_COR_SEQ_2_USE_0 = "FALSE"; +parameter CLK_COR_SEQ_2_USE_1 = "FALSE"; +parameter COMMA_DOUBLE_0 = "FALSE"; +parameter COMMA_DOUBLE_1 = "FALSE"; +parameter DEC_MCOMMA_DETECT_0 = "TRUE"; +parameter DEC_MCOMMA_DETECT_1 = "TRUE"; +parameter DEC_PCOMMA_DETECT_0 = "TRUE"; +parameter DEC_PCOMMA_DETECT_1 = "TRUE"; +parameter DEC_VALID_COMMA_ONLY_0 = "TRUE"; +parameter DEC_VALID_COMMA_ONLY_1 = "TRUE"; +parameter MCOMMA_DETECT_0 = "TRUE"; +parameter MCOMMA_DETECT_1 = "TRUE"; +parameter OVERSAMPLE_MODE = "FALSE"; +parameter PCI_EXPRESS_MODE_0 = "TRUE"; +parameter PCI_EXPRESS_MODE_1 = "TRUE"; +parameter PCOMMA_DETECT_0 = "TRUE"; +parameter PCOMMA_DETECT_1 = "TRUE"; +parameter PLL_SATA_0 = "FALSE"; +parameter PLL_SATA_1 = "FALSE"; +parameter RCV_TERM_GND_0 = "TRUE"; +parameter RCV_TERM_GND_1 = "TRUE"; +parameter RCV_TERM_MID_0 = "FALSE"; +parameter RCV_TERM_MID_1 = "FALSE"; +parameter RCV_TERM_VTTRX_0 = "FALSE"; +parameter RCV_TERM_VTTRX_1 = "FALSE"; +parameter RX_BUFFER_USE_0 = "TRUE"; +parameter RX_BUFFER_USE_1 = "TRUE"; +parameter RX_DECODE_SEQ_MATCH_0 = "TRUE"; +parameter RX_DECODE_SEQ_MATCH_1 = "TRUE"; +parameter RX_LOSS_OF_SYNC_FSM_0 = "FALSE"; +parameter RX_LOSS_OF_SYNC_FSM_1 = "FALSE"; +parameter RX_SLIDE_MODE_0 = "PCS"; +parameter RX_SLIDE_MODE_1 = "PCS"; +parameter RX_STATUS_FMT_0 = "PCIE"; +parameter RX_STATUS_FMT_1 = "PCIE"; +parameter RX_XCLK_SEL_0 = "RXREC"; +parameter RX_XCLK_SEL_1 = "RXREC"; +parameter SIM_MODE = "FAST"; +parameter SIM_PLL_PERDIV2 = 9'h190; +parameter SIM_RECEIVER_DETECT_PASS0 = "FALSE"; +parameter SIM_RECEIVER_DETECT_PASS1 = "FALSE"; +parameter TERMINATION_OVRD = "FALSE"; +parameter TX_BUFFER_USE_0 = "TRUE"; +parameter TX_BUFFER_USE_1 = "TRUE"; +parameter TX_DIFF_BOOST_0 = "TRUE"; +parameter TX_DIFF_BOOST_1 = "TRUE"; +parameter TX_XCLK_SEL_0 = "TXUSR"; +parameter TX_XCLK_SEL_1 = "TXUSR"; +parameter [15:0] TRANS_TIME_FROM_P2_0 = 16'h003c; +parameter [15:0] TRANS_TIME_FROM_P2_1 = 16'h003c; +parameter [15:0] TRANS_TIME_NON_P2_0 = 16'h0019; +parameter [15:0] TRANS_TIME_NON_P2_1 = 16'h0019; +parameter [15:0] TRANS_TIME_TO_P2_0 = 16'h0064; +parameter [15:0] TRANS_TIME_TO_P2_1 = 16'h0064; +parameter [24:0] PMA_RX_CFG_0 = 25'h09f0089; +parameter [24:0] PMA_RX_CFG_1 = 25'h09f0089; +parameter [26:0] PMA_CDR_SCAN_0 = 27'h6c07640; +parameter [26:0] PMA_CDR_SCAN_1 = 27'h6c07640; +parameter [27:0] PCS_COM_CFG = 28'h1680a0e; +parameter [2:0] OOBDETECT_THRESHOLD_0 = 3'b001; +parameter [2:0] OOBDETECT_THRESHOLD_1 = 3'b001; +parameter [2:0] SATA_BURST_VAL_0 = 3'b100; +parameter [2:0] SATA_BURST_VAL_1 = 3'b100; +parameter [2:0] SATA_IDLE_VAL_0 = 3'b011; +parameter [2:0] SATA_IDLE_VAL_1 = 3'b011; +parameter [31:0] PRBS_ERR_THRESHOLD_0 = 32'h1; +parameter [31:0] PRBS_ERR_THRESHOLD_1 = 32'h1; +parameter [3:0] CHAN_BOND_SEQ_1_ENABLE_0 = 4'b1111; +parameter [3:0] CHAN_BOND_SEQ_1_ENABLE_1 = 4'b1111; +parameter [3:0] CHAN_BOND_SEQ_2_ENABLE_0 = 4'b1111; +parameter [3:0] CHAN_BOND_SEQ_2_ENABLE_1 = 4'b1111; +parameter [3:0] CLK_COR_SEQ_1_ENABLE_0 = 4'b1111; +parameter [3:0] CLK_COR_SEQ_1_ENABLE_1 = 4'b1111; +parameter [3:0] CLK_COR_SEQ_2_ENABLE_0 = 4'b1111; +parameter [3:0] CLK_COR_SEQ_2_ENABLE_1 = 4'b1111; +parameter [3:0] COM_BURST_VAL_0 = 4'b1111; +parameter [3:0] COM_BURST_VAL_1 = 4'b1111; +parameter [4:0] TERMINATION_CTRL = 5'b10100; +parameter [4:0] TXRX_INVERT_0 = 5'b00000; +parameter [4:0] TXRX_INVERT_1 = 5'b00000; +parameter [9:0] CHAN_BOND_SEQ_1_1_0 = 10'b0001001010; +parameter [9:0] CHAN_BOND_SEQ_1_1_1 = 10'b0001001010; +parameter [9:0] CHAN_BOND_SEQ_1_2_0 = 10'b0001001010; +parameter [9:0] CHAN_BOND_SEQ_1_2_1 = 10'b0001001010; +parameter [9:0] CHAN_BOND_SEQ_1_3_0 = 10'b0001001010; +parameter [9:0] CHAN_BOND_SEQ_1_3_1 = 10'b0001001010; +parameter [9:0] CHAN_BOND_SEQ_1_4_0 = 10'b0110111100; +parameter [9:0] CHAN_BOND_SEQ_1_4_1 = 10'b0110111100; +parameter [9:0] CHAN_BOND_SEQ_2_1_0 = 10'b0110111100; +parameter [9:0] CHAN_BOND_SEQ_2_1_1 = 10'b0110111100; +parameter [9:0] CHAN_BOND_SEQ_2_2_0 = 10'b0100111100; +parameter [9:0] CHAN_BOND_SEQ_2_2_1 = 10'b0100111100; +parameter [9:0] CHAN_BOND_SEQ_2_3_0 = 10'b0100111100; +parameter [9:0] CHAN_BOND_SEQ_2_3_1 = 10'b0100111100; +parameter [9:0] CHAN_BOND_SEQ_2_4_0 = 10'b0100111100; +parameter [9:0] CHAN_BOND_SEQ_2_4_1 = 10'b0100111100; +parameter [9:0] CLK_COR_SEQ_1_1_0 = 10'b0100011100; +parameter [9:0] CLK_COR_SEQ_1_1_1 = 10'b0100011100; +parameter [9:0] CLK_COR_SEQ_1_2_0 = 10'b0; +parameter [9:0] CLK_COR_SEQ_1_2_1 = 10'b0; +parameter [9:0] CLK_COR_SEQ_1_3_0 = 10'b0; +parameter [9:0] CLK_COR_SEQ_1_3_1 = 10'b0; +parameter [9:0] CLK_COR_SEQ_1_4_0 = 10'b0; +parameter [9:0] CLK_COR_SEQ_1_4_1 = 10'b0; +parameter [9:0] CLK_COR_SEQ_2_1_0 = 10'b0; +parameter [9:0] CLK_COR_SEQ_2_1_1 = 10'b0; +parameter [9:0] CLK_COR_SEQ_2_2_0 = 10'b0; +parameter [9:0] CLK_COR_SEQ_2_2_1 = 10'b0; +parameter [9:0] CLK_COR_SEQ_2_3_0 = 10'b0; +parameter [9:0] CLK_COR_SEQ_2_3_1 = 10'b0; +parameter [9:0] CLK_COR_SEQ_2_4_0 = 10'b0; +parameter [9:0] CLK_COR_SEQ_2_4_1 = 10'b0; +parameter [9:0] COMMA_10B_ENABLE_0 = 10'b1111111111; +parameter [9:0] COMMA_10B_ENABLE_1 = 10'b1111111111; +parameter [9:0] MCOMMA_10B_VALUE_0 = 10'b1010000011; +parameter [9:0] MCOMMA_10B_VALUE_1 = 10'b1010000011; +parameter [9:0] PCOMMA_10B_VALUE_0 = 10'b0101111100; +parameter [9:0] PCOMMA_10B_VALUE_1 = 10'b0101111100; +parameter integer ALIGN_COMMA_WORD_0 = 1; +parameter integer ALIGN_COMMA_WORD_1 = 1; +parameter integer CHAN_BOND_1_MAX_SKEW_0 = 7; +parameter integer CHAN_BOND_1_MAX_SKEW_1 = 7; +parameter integer CHAN_BOND_2_MAX_SKEW_0 = 1; +parameter integer CHAN_BOND_2_MAX_SKEW_1 = 1; +parameter integer CHAN_BOND_LEVEL_0 = 0; +parameter integer CHAN_BOND_LEVEL_1 = 0; +parameter integer CHAN_BOND_SEQ_LEN_0 = 4; +parameter integer CHAN_BOND_SEQ_LEN_1 = 4; +parameter integer CLK25_DIVIDER = 4; +parameter integer CLK_COR_ADJ_LEN_0 = 1; +parameter integer CLK_COR_ADJ_LEN_1 = 1; +parameter integer CLK_COR_DET_LEN_0 = 1; +parameter integer CLK_COR_DET_LEN_1 = 1; +parameter integer CLK_COR_MAX_LAT_0 = 18; +parameter integer CLK_COR_MAX_LAT_1 = 18; +parameter integer CLK_COR_MIN_LAT_0 = 16; +parameter integer CLK_COR_MIN_LAT_1 = 16; +parameter integer CLK_COR_REPEAT_WAIT_0 = 5; +parameter integer CLK_COR_REPEAT_WAIT_1 = 5; +parameter integer OOB_CLK_DIVIDER = 4; +parameter integer PLL_DIVSEL_FB = 5; +parameter integer PLL_DIVSEL_REF = 2; +parameter integer PLL_RXDIVSEL_OUT_0 = 1; +parameter integer PLL_RXDIVSEL_OUT_1 = 1; +parameter integer PLL_TXDIVSEL_COMM_OUT = 1; +parameter integer PLL_TXDIVSEL_OUT_0 = 1; +parameter integer PLL_TXDIVSEL_OUT_1 = 1; +parameter integer RX_LOS_INVALID_INCR_0 = 8; +parameter integer RX_LOS_INVALID_INCR_1 = 8; +parameter integer RX_LOS_THRESHOLD_0 = 128; +parameter integer RX_LOS_THRESHOLD_1 = 128; +parameter integer SATA_MAX_BURST_0 = 7; +parameter integer SATA_MAX_BURST_1 = 7; +parameter integer SATA_MAX_INIT_0 = 22; +parameter integer SATA_MAX_INIT_1 = 22; +parameter integer SATA_MAX_WAKE_0 = 7; +parameter integer SATA_MAX_WAKE_1 = 7; +parameter integer SATA_MIN_BURST_0 = 4; +parameter integer SATA_MIN_BURST_1 = 4; +parameter integer SATA_MIN_INIT_0 = 12; +parameter integer SATA_MIN_INIT_1 = 12; +parameter integer SATA_MIN_WAKE_0 = 4; +parameter integer SATA_MIN_WAKE_1 = 4; +parameter integer SIM_GTPRESET_SPEEDUP = 0; +parameter integer TERMINATION_IMP_0 = 50; +parameter integer TERMINATION_IMP_1 = 50; +parameter integer TX_SYNC_FILTERB = 1; + +localparam in_delay = 0; +localparam out_delay = 0; +localparam CLK_DELAY = 0; + +output DRDY; +output PHYSTATUS0; +output PHYSTATUS1; +output PLLLKDET; +output REFCLKOUT; +output RESETDONE0; +output RESETDONE1; +output RXBYTEISALIGNED0; +output RXBYTEISALIGNED1; +output RXBYTEREALIGN0; +output RXBYTEREALIGN1; +output RXCHANBONDSEQ0; +output RXCHANBONDSEQ1; +output RXCHANISALIGNED0; +output RXCHANISALIGNED1; +output RXCHANREALIGN0; +output RXCHANREALIGN1; +output RXCOMMADET0; +output RXCOMMADET1; +output RXELECIDLE0; +output RXELECIDLE1; +output RXOVERSAMPLEERR0; +output RXOVERSAMPLEERR1; +output RXPRBSERR0; +output RXPRBSERR1; +output RXRECCLK0; +output RXRECCLK1; +output RXVALID0; +output RXVALID1; +output TXN0; +output TXN1; +output TXOUTCLK0; +output TXOUTCLK1; +output TXP0; +output TXP1; +output [15:0] DO; +output [15:0] RXDATA0; +output [15:0] RXDATA1; +output [1:0] RXCHARISCOMMA0; +output [1:0] RXCHARISCOMMA1; +output [1:0] RXCHARISK0; +output [1:0] RXCHARISK1; +output [1:0] RXDISPERR0; +output [1:0] RXDISPERR1; +output [1:0] RXLOSSOFSYNC0; +output [1:0] RXLOSSOFSYNC1; +output [1:0] RXNOTINTABLE0; +output [1:0] RXNOTINTABLE1; +output [1:0] RXRUNDISP0; +output [1:0] RXRUNDISP1; +output [1:0] TXBUFSTATUS0; +output [1:0] TXBUFSTATUS1; +output [1:0] TXKERR0; +output [1:0] TXKERR1; +output [1:0] TXRUNDISP0; +output [1:0] TXRUNDISP1; +output [2:0] RXBUFSTATUS0; +output [2:0] RXBUFSTATUS1; +output [2:0] RXCHBONDO0; +output [2:0] RXCHBONDO1; +output [2:0] RXCLKCORCNT0; +output [2:0] RXCLKCORCNT1; +output [2:0] RXSTATUS0; +output [2:0] RXSTATUS1; + +input CLKIN; +input DCLK; +input DEN; +input DWE; +input GTPRESET; +input INTDATAWIDTH; +input PLLLKDETEN; +input PLLPOWERDOWN; +input PRBSCNTRESET0; +input PRBSCNTRESET1; +input REFCLKPWRDNB; +input RXBUFRESET0; +input RXBUFRESET1; +input RXCDRRESET0; +input RXCDRRESET1; +input RXCOMMADETUSE0; +input RXCOMMADETUSE1; +input RXDATAWIDTH0; +input RXDATAWIDTH1; +input RXDEC8B10BUSE0; +input RXDEC8B10BUSE1; +input RXELECIDLERESET0; +input RXELECIDLERESET1; +input RXENCHANSYNC0; +input RXENCHANSYNC1; +input RXENELECIDLERESETB; +input RXENEQB0; +input RXENEQB1; +input RXENMCOMMAALIGN0; +input RXENMCOMMAALIGN1; +input RXENPCOMMAALIGN0; +input RXENPCOMMAALIGN1; +input RXENSAMPLEALIGN0; +input RXENSAMPLEALIGN1; +input RXN0; +input RXN1; +input RXP0; +input RXP1; +input RXPMASETPHASE0; +input RXPMASETPHASE1; +input RXPOLARITY0; +input RXPOLARITY1; +input RXRESET0; +input RXRESET1; +input RXSLIDE0; +input RXSLIDE1; +input RXUSRCLK0; +input RXUSRCLK1; +input RXUSRCLK20; +input RXUSRCLK21; +input TXCOMSTART0; +input TXCOMSTART1; +input TXCOMTYPE0; +input TXCOMTYPE1; +input TXDATAWIDTH0; +input TXDATAWIDTH1; +input TXDETECTRX0; +input TXDETECTRX1; +input TXELECIDLE0; +input TXELECIDLE1; +input TXENC8B10BUSE0; +input TXENC8B10BUSE1; +input TXENPMAPHASEALIGN; +input TXINHIBIT0; +input TXINHIBIT1; +input TXPMASETPHASE; +input TXPOLARITY0; +input TXPOLARITY1; +input TXRESET0; +input TXRESET1; +input TXUSRCLK0; +input TXUSRCLK1; +input TXUSRCLK20; +input TXUSRCLK21; +input [15:0] DI; +input [15:0] TXDATA0; +input [15:0] TXDATA1; +input [1:0] RXENPRBSTST0; +input [1:0] RXENPRBSTST1; +input [1:0] RXEQMIX0; +input [1:0] RXEQMIX1; +input [1:0] RXPOWERDOWN0; +input [1:0] RXPOWERDOWN1; +input [1:0] TXBYPASS8B10B0; +input [1:0] TXBYPASS8B10B1; +input [1:0] TXCHARDISPMODE0; +input [1:0] TXCHARDISPMODE1; +input [1:0] TXCHARDISPVAL0; +input [1:0] TXCHARDISPVAL1; +input [1:0] TXCHARISK0; +input [1:0] TXCHARISK1; +input [1:0] TXENPRBSTST0; +input [1:0] TXENPRBSTST1; +input [1:0] TXPOWERDOWN0; +input [1:0] TXPOWERDOWN1; +input [2:0] LOOPBACK0; +input [2:0] LOOPBACK1; +input [2:0] RXCHBONDI0; +input [2:0] RXCHBONDI1; +input [2:0] TXBUFDIFFCTRL0; +input [2:0] TXBUFDIFFCTRL1; +input [2:0] TXDIFFCTRL0; +input [2:0] TXDIFFCTRL1; +input [2:0] TXPREEMPHASIS0; +input [2:0] TXPREEMPHASIS1; +input [3:0] GTPTEST; +input [3:0] RXEQPOLE0; +input [3:0] RXEQPOLE1; +input [6:0] DADDR; + +reg AC_CAP_DIS_0_BINARY; +reg AC_CAP_DIS_1_BINARY; +reg ALIGN_COMMA_WORD_0_BINARY; +reg ALIGN_COMMA_WORD_1_BINARY; +reg [1:0] CHAN_BOND_MODE_0_BINARY; +reg [1:0] CHAN_BOND_MODE_1_BINARY; +reg CHAN_BOND_SEQ_2_USE_0_BINARY; +reg CHAN_BOND_SEQ_2_USE_1_BINARY; +reg CLKINDC_B_BINARY; +reg CLK_CORRECT_USE_0_BINARY; +reg CLK_CORRECT_USE_1_BINARY; +reg CLK_COR_INSERT_IDLE_FLAG_0_BINARY; +reg CLK_COR_INSERT_IDLE_FLAG_1_BINARY; +reg CLK_COR_KEEP_IDLE_0_BINARY; +reg CLK_COR_KEEP_IDLE_1_BINARY; +reg CLK_COR_PRECEDENCE_0_BINARY; +reg CLK_COR_PRECEDENCE_1_BINARY; +reg CLK_COR_SEQ_2_USE_0_BINARY; +reg CLK_COR_SEQ_2_USE_1_BINARY; +reg COMMA_DOUBLE_0_BINARY; +reg COMMA_DOUBLE_1_BINARY; +reg DEC_MCOMMA_DETECT_0_BINARY; +reg DEC_MCOMMA_DETECT_1_BINARY; +reg DEC_PCOMMA_DETECT_0_BINARY; +reg DEC_PCOMMA_DETECT_1_BINARY; +reg DEC_VALID_COMMA_ONLY_0_BINARY; +reg DEC_VALID_COMMA_ONLY_1_BINARY; +reg MCOMMA_DETECT_0_BINARY; +reg MCOMMA_DETECT_1_BINARY; +reg OVERSAMPLE_MODE_BINARY; +reg PCI_EXPRESS_MODE_0_BINARY; +reg PCI_EXPRESS_MODE_1_BINARY; +reg PCOMMA_DETECT_0_BINARY; +reg PCOMMA_DETECT_1_BINARY; +reg PLL_SATA_0_BINARY; +reg PLL_SATA_1_BINARY; +reg RCV_TERM_GND_0_BINARY; +reg RCV_TERM_GND_1_BINARY; +reg RCV_TERM_MID_0_BINARY; +reg RCV_TERM_MID_1_BINARY; +reg RCV_TERM_VTTRX_0_BINARY; +reg RCV_TERM_VTTRX_1_BINARY; +reg RX_BUFFER_USE_0_BINARY; +reg RX_BUFFER_USE_1_BINARY; +reg RX_DECODE_SEQ_MATCH_0_BINARY; +reg RX_DECODE_SEQ_MATCH_1_BINARY; +reg RX_LOSS_OF_SYNC_FSM_0_BINARY; +reg RX_LOSS_OF_SYNC_FSM_1_BINARY; +reg RX_SLIDE_MODE_0_BINARY; +reg RX_SLIDE_MODE_1_BINARY; +reg RX_STATUS_FMT_0_BINARY; +reg RX_STATUS_FMT_1_BINARY; +reg RX_XCLK_SEL_0_BINARY; +reg RX_XCLK_SEL_1_BINARY; +reg SIM_GTPRESET_SPEEDUP_BINARY; +reg SIM_MODE_BINARY; +reg SIM_RECEIVER_DETECT_PASS0_BINARY; +reg SIM_RECEIVER_DETECT_PASS1_BINARY; +reg TERMINATION_IMP_0_BINARY; +reg TERMINATION_IMP_1_BINARY; +reg TERMINATION_OVRD_BINARY; +reg TX_BUFFER_USE_0_BINARY; +reg TX_BUFFER_USE_1_BINARY; +reg TX_DIFF_BOOST_0_BINARY; +reg TX_DIFF_BOOST_1_BINARY; +reg TX_SYNC_FILTERB_BINARY; +reg TX_XCLK_SEL_0_BINARY; +reg TX_XCLK_SEL_1_BINARY; +reg [1:0] CHAN_BOND_SEQ_LEN_0_BINARY; +reg [1:0] CHAN_BOND_SEQ_LEN_1_BINARY; +reg [1:0] CLK_COR_ADJ_LEN_0_BINARY; +reg [1:0] CLK_COR_ADJ_LEN_1_BINARY; +reg [1:0] CLK_COR_DET_LEN_0_BINARY; +reg [1:0] CLK_COR_DET_LEN_1_BINARY; +reg [1:0] PLL_RXDIVSEL_OUT_0_BINARY; +reg [1:0] PLL_RXDIVSEL_OUT_1_BINARY; +reg [1:0] PLL_TXDIVSEL_COMM_OUT_BINARY; +reg [1:0] PLL_TXDIVSEL_OUT_0_BINARY; +reg [1:0] PLL_TXDIVSEL_OUT_1_BINARY; +reg [2:0] CHAN_BOND_LEVEL_0_BINARY; +reg [2:0] CHAN_BOND_LEVEL_1_BINARY; +reg [2:0] CLK25_DIVIDER_BINARY; +reg [2:0] OOB_CLK_DIVIDER_BINARY; +reg [2:0] RX_LOS_INVALID_INCR_0_BINARY; +reg [2:0] RX_LOS_INVALID_INCR_1_BINARY; +reg [2:0] RX_LOS_THRESHOLD_0_BINARY; +reg [2:0] RX_LOS_THRESHOLD_1_BINARY; +reg [3:0] CHAN_BOND_1_MAX_SKEW_0_BINARY; +reg [3:0] CHAN_BOND_1_MAX_SKEW_1_BINARY; +reg [3:0] CHAN_BOND_2_MAX_SKEW_0_BINARY; +reg [3:0] CHAN_BOND_2_MAX_SKEW_1_BINARY; +reg [4:0] CLK_COR_REPEAT_WAIT_0_BINARY; +reg [4:0] CLK_COR_REPEAT_WAIT_1_BINARY; +reg [4:0] PLL_DIVSEL_FB_BINARY; +reg [5:0] CLK_COR_MAX_LAT_0_BINARY; +reg [5:0] CLK_COR_MAX_LAT_1_BINARY; +reg [5:0] CLK_COR_MIN_LAT_0_BINARY; +reg [5:0] CLK_COR_MIN_LAT_1_BINARY; +reg [5:0] PLL_DIVSEL_REF_BINARY; +reg [5:0] SATA_MAX_BURST_0_BINARY; +reg [5:0] SATA_MAX_BURST_1_BINARY; +reg [5:0] SATA_MAX_INIT_0_BINARY; +reg [5:0] SATA_MAX_INIT_1_BINARY; +reg [5:0] SATA_MAX_WAKE_0_BINARY; +reg [5:0] SATA_MAX_WAKE_1_BINARY; +reg [5:0] SATA_MIN_BURST_0_BINARY; +reg [5:0] SATA_MIN_BURST_1_BINARY; +reg [5:0] SATA_MIN_INIT_0_BINARY; +reg [5:0] SATA_MIN_INIT_1_BINARY; +reg [5:0] SATA_MIN_WAKE_0_BINARY; +reg [5:0] SATA_MIN_WAKE_1_BINARY; + +tri0 GSR = glbl.GSR; + +initial begin + case (PLL_TXDIVSEL_OUT_0) + 1 : PLL_TXDIVSEL_OUT_0_BINARY = 2'b00; + 2 : PLL_TXDIVSEL_OUT_0_BINARY = 2'b01; + 4 : PLL_TXDIVSEL_OUT_0_BINARY = 2'b10; + default : begin + $display("Attribute Syntax Error : The Attribute PLL_TXDIVSEL_OUT_0 on GTP_DUAL instance %m is set to %d. Legal values for this attribute are 1, 2 or 4.", PLL_TXDIVSEL_OUT_0); + $finish; + end + endcase + + case (PLL_RXDIVSEL_OUT_0) + 1 : PLL_RXDIVSEL_OUT_0_BINARY = 2'b00; + 2 : PLL_RXDIVSEL_OUT_0_BINARY = 2'b01; + 4 : PLL_RXDIVSEL_OUT_0_BINARY = 2'b10; + default : begin + $display("Attribute Syntax Error : The Attribute PLL_RXDIVSEL_OUT_0 on GTP_DUAL instance %m is set to %d. Legal values for this attribute are 1, 2 or 4.", PLL_RXDIVSEL_OUT_0); + $finish; + end + endcase + + case (PLL_TXDIVSEL_OUT_1) + 1 : PLL_TXDIVSEL_OUT_1_BINARY = 2'b00; + 2 : PLL_TXDIVSEL_OUT_1_BINARY = 2'b01; + 4 : PLL_TXDIVSEL_OUT_1_BINARY = 2'b10; + default : begin + $display("Attribute Syntax Error : The Attribute PLL_TXDIVSEL_OUT_1 on GTP_DUAL instance %m is set to %d. Legal values for this attribute are 1, 2 or 4.", PLL_TXDIVSEL_OUT_1); + $finish; + end + endcase + + case (PLL_RXDIVSEL_OUT_1) + 1 : PLL_RXDIVSEL_OUT_1_BINARY = 2'b00; + 2 : PLL_RXDIVSEL_OUT_1_BINARY = 2'b01; + 4 : PLL_RXDIVSEL_OUT_1_BINARY = 2'b10; + default : begin + $display("Attribute Syntax Error : The Attribute PLL_RXDIVSEL_OUT_1 on GTP_DUAL instance %m is set to %d. Legal values for this attribute are 1, 2 or 4.", PLL_RXDIVSEL_OUT_1); + $finish; + end + endcase + + case (PLL_DIVSEL_FB) + 1 : PLL_DIVSEL_FB_BINARY = 5'b10000; + 2 : PLL_DIVSEL_FB_BINARY = 5'b00000; + 3 : PLL_DIVSEL_FB_BINARY = 5'b00001; + 4 : PLL_DIVSEL_FB_BINARY = 5'b00010; + 5 : PLL_DIVSEL_FB_BINARY = 5'b00011; + 8 : PLL_DIVSEL_FB_BINARY = 5'b00110; + 10 : PLL_DIVSEL_FB_BINARY = 5'b00111; + default : begin + $display("Attribute Syntax Error : The Attribute PLL_DIVSEL_FB on GTP_DUAL instance %m is set to %d. Legal values for this attribute are 1, 2, 3, 4, 5, 8 or 10.", PLL_DIVSEL_FB); + $finish; + end + endcase + + case (PLL_DIVSEL_REF) + 1 : PLL_DIVSEL_REF_BINARY = 6'b010000; + 2 : PLL_DIVSEL_REF_BINARY = 6'b000000; + 3 : PLL_DIVSEL_REF_BINARY = 6'b000001; + 4 : PLL_DIVSEL_REF_BINARY = 6'b000010; + 5 : PLL_DIVSEL_REF_BINARY = 6'b000011; + 6 : PLL_DIVSEL_REF_BINARY = 6'b000101; + 8 : PLL_DIVSEL_REF_BINARY = 6'b000110; + 10 : PLL_DIVSEL_REF_BINARY = 6'b000111; + 12 : PLL_DIVSEL_REF_BINARY = 6'b001101; + 16 : PLL_DIVSEL_REF_BINARY = 6'b001110; + 20 : PLL_DIVSEL_REF_BINARY = 6'b001111; + default : begin + $display("Attribute Syntax Error : The Attribute PLL_DIVSEL_REF on GTP_DUAL instance %m is set to %d. Legal values for this attribute are 1, 2, 3, 4, 5, 6, 8, 10, 12, 16 or 20.", PLL_DIVSEL_REF); + $finish; + end + endcase + + case (PLL_TXDIVSEL_COMM_OUT) + 1 : PLL_TXDIVSEL_COMM_OUT_BINARY = 2'b00; + 2 : PLL_TXDIVSEL_COMM_OUT_BINARY = 2'b01; + 4 : PLL_TXDIVSEL_COMM_OUT_BINARY = 2'b10; + default : begin + $display("Attribute Syntax Error : The Attribute PLL_TXDIVSEL_COMM_OUT on GTP_DUAL instance %m is set to %d. Legal values for this attribute are 1, 2 or 4.", PLL_TXDIVSEL_COMM_OUT); + $finish; + end + endcase + + case (PLL_SATA_0) + "FALSE" : PLL_SATA_0_BINARY = 1'b0; + "TRUE" : PLL_SATA_0_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute PLL_SATA_0 on GTP_DUAL instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", PLL_SATA_0); + $finish; + end + endcase + + case (PLL_SATA_1) + "FALSE" : PLL_SATA_1_BINARY = 1'b0; + "TRUE" : PLL_SATA_1_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute PLL_SATA_1 on GTP_DUAL instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", PLL_SATA_1); + $finish; + end + endcase + + case (TX_DIFF_BOOST_0) + "FALSE" : TX_DIFF_BOOST_0_BINARY = 1'b0; + "TRUE" : TX_DIFF_BOOST_0_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute TX_DIFF_BOOST_0 on GTP_DUAL instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", TX_DIFF_BOOST_0); + $finish; + end + endcase + + case (TX_DIFF_BOOST_1) + "FALSE" : TX_DIFF_BOOST_1_BINARY = 1'b0; + "TRUE" : TX_DIFF_BOOST_1_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute TX_DIFF_BOOST_1 on GTP_DUAL instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", TX_DIFF_BOOST_1); + $finish; + end + endcase + + case (OOB_CLK_DIVIDER) + 1 : OOB_CLK_DIVIDER_BINARY = 3'b000; + 2 : OOB_CLK_DIVIDER_BINARY = 3'b001; + 4 : OOB_CLK_DIVIDER_BINARY = 3'b010; + 6 : OOB_CLK_DIVIDER_BINARY = 3'b011; + 8 : OOB_CLK_DIVIDER_BINARY = 3'b100; + 10 : OOB_CLK_DIVIDER_BINARY = 3'b101; + 12 : OOB_CLK_DIVIDER_BINARY = 3'b110; + 14 : OOB_CLK_DIVIDER_BINARY = 3'b111; + default : begin + $display("Attribute Syntax Error : The Attribute OOB_CLK_DIVIDER on GTP_DUAL instance %m is set to %d. Legal values for this attribute are 1, 2, 4, 6, 8, 10, 12 or 14.", OOB_CLK_DIVIDER); + $finish; + end + endcase + + case (TX_SYNC_FILTERB) + 0 : TX_SYNC_FILTERB_BINARY = 1'b0; + 1 : TX_SYNC_FILTERB_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute TX_SYNC_FILTERB on GTP_DUAL instance %m is set to %d. Legal values for this attribute are 0 or 1.", TX_SYNC_FILTERB); + $finish; + end + endcase + + case (AC_CAP_DIS_0) + "FALSE" : AC_CAP_DIS_0_BINARY = 1'b0; + "TRUE" : AC_CAP_DIS_0_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute AC_CAP_DIS_0 on GTP_DUAL instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", AC_CAP_DIS_0); + $finish; + end + endcase + + case (AC_CAP_DIS_1) + "FALSE" : AC_CAP_DIS_1_BINARY = 1'b0; + "TRUE" : AC_CAP_DIS_1_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute AC_CAP_DIS_1 on GTP_DUAL instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", AC_CAP_DIS_1); + $finish; + end + endcase + + case (RCV_TERM_GND_0) + "FALSE" : RCV_TERM_GND_0_BINARY = 1'b0; + "TRUE" : RCV_TERM_GND_0_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute RCV_TERM_GND_0 on GTP_DUAL instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", RCV_TERM_GND_0); + $finish; + end + endcase + + case (RCV_TERM_GND_1) + "FALSE" : RCV_TERM_GND_1_BINARY = 1'b0; + "TRUE" : RCV_TERM_GND_1_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute RCV_TERM_GND_1 on GTP_DUAL instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", RCV_TERM_GND_1); + $finish; + end + endcase + + case (RCV_TERM_MID_0) + "FALSE" : RCV_TERM_MID_0_BINARY = 1'b0; + "TRUE" : RCV_TERM_MID_0_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute RCV_TERM_MID_0 on GTP_DUAL instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", RCV_TERM_MID_0); + $finish; + end + endcase + + case (RCV_TERM_MID_1) + "FALSE" : RCV_TERM_MID_1_BINARY = 1'b0; + "TRUE" : RCV_TERM_MID_1_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute RCV_TERM_MID_1 on GTP_DUAL instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", RCV_TERM_MID_1); + $finish; + end + endcase + + case (TERMINATION_IMP_0) + 50 : TERMINATION_IMP_0_BINARY = 1'b0; + 75 : TERMINATION_IMP_0_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute TERMINATION_IMP_0 on GTP_DUAL instance %m is set to %d. Legal values for this attribute are 50 or 75.", TERMINATION_IMP_0); + $finish; + end + endcase + + case (TERMINATION_IMP_1) + 50 : TERMINATION_IMP_1_BINARY = 1'b0; + 75 : TERMINATION_IMP_1_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute TERMINATION_IMP_1 on GTP_DUAL instance %m is set to %d. Legal values for this attribute are 50 or 75.", TERMINATION_IMP_1); + $finish; + end + endcase + + case (TERMINATION_OVRD) + "FALSE" : TERMINATION_OVRD_BINARY = 1'b0; + "TRUE" : TERMINATION_OVRD_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute TERMINATION_OVRD on GTP_DUAL instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", TERMINATION_OVRD); + $finish; + end + endcase + + case (RCV_TERM_VTTRX_0) + "FALSE" : RCV_TERM_VTTRX_0_BINARY = 1'b0; + "TRUE" : RCV_TERM_VTTRX_0_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute RCV_TERM_VTTRX_0 on GTP_DUAL instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", RCV_TERM_VTTRX_0); + $finish; + end + endcase + + case (RCV_TERM_VTTRX_1) + "FALSE" : RCV_TERM_VTTRX_1_BINARY = 1'b0; + "TRUE" : RCV_TERM_VTTRX_1_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute RCV_TERM_VTTRX_1 on GTP_DUAL instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", RCV_TERM_VTTRX_1); + $finish; + end + endcase + + case (CLKINDC_B) + "FALSE" : CLKINDC_B_BINARY = 1'b0; + "TRUE" : CLKINDC_B_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute CLKINDC_B on GTP_DUAL instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", CLKINDC_B); + $finish; + end + endcase + + case (PCOMMA_DETECT_0) + "FALSE" : PCOMMA_DETECT_0_BINARY = 1'b0; + "TRUE" : PCOMMA_DETECT_0_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute PCOMMA_DETECT_0 on GTP_DUAL instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", PCOMMA_DETECT_0); + $finish; + end + endcase + + case (MCOMMA_DETECT_0) + "FALSE" : MCOMMA_DETECT_0_BINARY = 1'b0; + "TRUE" : MCOMMA_DETECT_0_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute MCOMMA_DETECT_0 on GTP_DUAL instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", MCOMMA_DETECT_0); + $finish; + end + endcase + + case (COMMA_DOUBLE_0) + "FALSE" : COMMA_DOUBLE_0_BINARY = 1'b0; + "TRUE" : COMMA_DOUBLE_0_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute COMMA_DOUBLE_0 on GTP_DUAL instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", COMMA_DOUBLE_0); + $finish; + end + endcase + + case (ALIGN_COMMA_WORD_0) + 1 : ALIGN_COMMA_WORD_0_BINARY = 1'b0; + 2 : ALIGN_COMMA_WORD_0_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute ALIGN_COMMA_WORD_0 on GTP_DUAL instance %m is set to %d. Legal values for this attribute are 1 or 2.", ALIGN_COMMA_WORD_0); + $finish; + end + endcase + + case (DEC_PCOMMA_DETECT_0) + "FALSE" : DEC_PCOMMA_DETECT_0_BINARY = 1'b0; + "TRUE" : DEC_PCOMMA_DETECT_0_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute DEC_PCOMMA_DETECT_0 on GTP_DUAL instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", DEC_PCOMMA_DETECT_0); + $finish; + end + endcase + + case (DEC_MCOMMA_DETECT_0) + "FALSE" : DEC_MCOMMA_DETECT_0_BINARY = 1'b0; + "TRUE" : DEC_MCOMMA_DETECT_0_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute DEC_MCOMMA_DETECT_0 on GTP_DUAL instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", DEC_MCOMMA_DETECT_0); + $finish; + end + endcase + + case (DEC_VALID_COMMA_ONLY_0) + "FALSE" : DEC_VALID_COMMA_ONLY_0_BINARY = 1'b0; + "TRUE" : DEC_VALID_COMMA_ONLY_0_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute DEC_VALID_COMMA_ONLY_0 on GTP_DUAL instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", DEC_VALID_COMMA_ONLY_0); + $finish; + end + endcase + + case (PCOMMA_DETECT_1) + "FALSE" : PCOMMA_DETECT_1_BINARY = 1'b0; + "TRUE" : PCOMMA_DETECT_1_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute PCOMMA_DETECT_1 on GTP_DUAL instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", PCOMMA_DETECT_1); + $finish; + end + endcase + + case (MCOMMA_DETECT_1) + "FALSE" : MCOMMA_DETECT_1_BINARY = 1'b0; + "TRUE" : MCOMMA_DETECT_1_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute MCOMMA_DETECT_1 on GTP_DUAL instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", MCOMMA_DETECT_1); + $finish; + end + endcase + + case (COMMA_DOUBLE_1) + "FALSE" : COMMA_DOUBLE_1_BINARY = 1'b0; + "TRUE" : COMMA_DOUBLE_1_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute COMMA_DOUBLE_1 on GTP_DUAL instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", COMMA_DOUBLE_1); + $finish; + end + endcase + + case (ALIGN_COMMA_WORD_1) + 1 : ALIGN_COMMA_WORD_1_BINARY = 1'b0; + 2 : ALIGN_COMMA_WORD_1_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute ALIGN_COMMA_WORD_1 on GTP_DUAL instance %m is set to %d. Legal values for this attribute are 1 or 2.", ALIGN_COMMA_WORD_1); + $finish; + end + endcase + + case (DEC_PCOMMA_DETECT_1) + "FALSE" : DEC_PCOMMA_DETECT_1_BINARY = 1'b0; + "TRUE" : DEC_PCOMMA_DETECT_1_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute DEC_PCOMMA_DETECT_1 on GTP_DUAL instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", DEC_PCOMMA_DETECT_1); + $finish; + end + endcase + + case (DEC_MCOMMA_DETECT_1) + "FALSE" : DEC_MCOMMA_DETECT_1_BINARY = 1'b0; + "TRUE" : DEC_MCOMMA_DETECT_1_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute DEC_MCOMMA_DETECT_1 on GTP_DUAL instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", DEC_MCOMMA_DETECT_1); + $finish; + end + endcase + + case (DEC_VALID_COMMA_ONLY_1) + "FALSE" : DEC_VALID_COMMA_ONLY_1_BINARY = 1'b0; + "TRUE" : DEC_VALID_COMMA_ONLY_1_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute DEC_VALID_COMMA_ONLY_1 on GTP_DUAL instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", DEC_VALID_COMMA_ONLY_1); + $finish; + end + endcase + + case (RX_LOSS_OF_SYNC_FSM_0) + "FALSE" : RX_LOSS_OF_SYNC_FSM_0_BINARY = 1'b0; + "TRUE" : RX_LOSS_OF_SYNC_FSM_0_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute RX_LOSS_OF_SYNC_FSM_0 on GTP_DUAL instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", RX_LOSS_OF_SYNC_FSM_0); + $finish; + end + endcase + + case (RX_LOS_INVALID_INCR_0) + 1 : RX_LOS_INVALID_INCR_0_BINARY = 3'b000; + 2 : RX_LOS_INVALID_INCR_0_BINARY = 3'b001; + 4 : RX_LOS_INVALID_INCR_0_BINARY = 3'b010; + 8 : RX_LOS_INVALID_INCR_0_BINARY = 3'b011; + 16 : RX_LOS_INVALID_INCR_0_BINARY = 3'b100; + 32 : RX_LOS_INVALID_INCR_0_BINARY = 3'b101; + 64 : RX_LOS_INVALID_INCR_0_BINARY = 3'b110; + 128 : RX_LOS_INVALID_INCR_0_BINARY = 3'b111; + default : begin + $display("Attribute Syntax Error : The Attribute RX_LOS_INVALID_INCR_0 on GTP_DUAL instance %m is set to %d. Legal values for this attribute are 1, 2, 4, 8, 16, 32, 64 or 128.", RX_LOS_INVALID_INCR_0); + $finish; + end + endcase + + case (RX_LOS_THRESHOLD_0) + 4 : RX_LOS_THRESHOLD_0_BINARY = 3'b000; + 8 : RX_LOS_THRESHOLD_0_BINARY = 3'b001; + 16 : RX_LOS_THRESHOLD_0_BINARY = 3'b010; + 32 : RX_LOS_THRESHOLD_0_BINARY = 3'b011; + 64 : RX_LOS_THRESHOLD_0_BINARY = 3'b100; + 128 : RX_LOS_THRESHOLD_0_BINARY = 3'b101; + 256 : RX_LOS_THRESHOLD_0_BINARY = 3'b110; + 512 : RX_LOS_THRESHOLD_0_BINARY = 3'b111; + default : begin + $display("Attribute Syntax Error : The Attribute RX_LOS_THRESHOLD_0 on GTP_DUAL instance %m is set to %d. Legal values for this attribute are 4, 8, 16, 32, 64, 128, 256 or 512.", RX_LOS_THRESHOLD_0); + $finish; + end + endcase + + case (RX_LOSS_OF_SYNC_FSM_1) + "FALSE" : RX_LOSS_OF_SYNC_FSM_1_BINARY = 1'b0; + "TRUE" : RX_LOSS_OF_SYNC_FSM_1_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute RX_LOSS_OF_SYNC_FSM_1 on GTP_DUAL instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", RX_LOSS_OF_SYNC_FSM_1); + $finish; + end + endcase + + case (RX_LOS_INVALID_INCR_1) + 1 : RX_LOS_INVALID_INCR_1_BINARY = 3'b000; + 2 : RX_LOS_INVALID_INCR_1_BINARY = 3'b001; + 4 : RX_LOS_INVALID_INCR_1_BINARY = 3'b010; + 8 : RX_LOS_INVALID_INCR_1_BINARY = 3'b011; + 16 : RX_LOS_INVALID_INCR_1_BINARY = 3'b100; + 32 : RX_LOS_INVALID_INCR_1_BINARY = 3'b101; + 64 : RX_LOS_INVALID_INCR_1_BINARY = 3'b110; + 128 : RX_LOS_INVALID_INCR_1_BINARY = 3'b111; + default : begin + $display("Attribute Syntax Error : The Attribute RX_LOS_INVALID_INCR_1 on GTP_DUAL instance %m is set to %d. Legal values for this attribute are 1, 2, 4, 8, 16, 32, 64 or 128.", RX_LOS_INVALID_INCR_1); + $finish; + end + endcase + + case (RX_LOS_THRESHOLD_1) + 4 : RX_LOS_THRESHOLD_1_BINARY = 3'b000; + 8 : RX_LOS_THRESHOLD_1_BINARY = 3'b001; + 16 : RX_LOS_THRESHOLD_1_BINARY = 3'b010; + 32 : RX_LOS_THRESHOLD_1_BINARY = 3'b011; + 64 : RX_LOS_THRESHOLD_1_BINARY = 3'b100; + 128 : RX_LOS_THRESHOLD_1_BINARY = 3'b101; + 256 : RX_LOS_THRESHOLD_1_BINARY = 3'b110; + 512 : RX_LOS_THRESHOLD_1_BINARY = 3'b111; + default : begin + $display("Attribute Syntax Error : The Attribute RX_LOS_THRESHOLD_1 on GTP_DUAL instance %m is set to %d. Legal values for this attribute are 4, 8, 16, 32, 64, 128, 256 or 512.", RX_LOS_THRESHOLD_1); + $finish; + end + endcase + + case (RX_BUFFER_USE_0) + "FALSE" : RX_BUFFER_USE_0_BINARY = 1'b0; + "TRUE" : RX_BUFFER_USE_0_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute RX_BUFFER_USE_0 on GTP_DUAL instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", RX_BUFFER_USE_0); + $finish; + end + endcase + + case (RX_DECODE_SEQ_MATCH_0) + "FALSE" : RX_DECODE_SEQ_MATCH_0_BINARY = 1'b0; + "TRUE" : RX_DECODE_SEQ_MATCH_0_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute RX_DECODE_SEQ_MATCH_0 on GTP_DUAL instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", RX_DECODE_SEQ_MATCH_0); + $finish; + end + endcase + + case (RX_BUFFER_USE_1) + "FALSE" : RX_BUFFER_USE_1_BINARY = 1'b0; + "TRUE" : RX_BUFFER_USE_1_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute RX_BUFFER_USE_1 on GTP_DUAL instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", RX_BUFFER_USE_1); + $finish; + end + endcase + + case (RX_DECODE_SEQ_MATCH_1) + "FALSE" : RX_DECODE_SEQ_MATCH_1_BINARY = 1'b0; + "TRUE" : RX_DECODE_SEQ_MATCH_1_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute RX_DECODE_SEQ_MATCH_1 on GTP_DUAL instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", RX_DECODE_SEQ_MATCH_1); + $finish; + end + endcase + + case (CLK_COR_MIN_LAT_0) + 3 : CLK_COR_MIN_LAT_0_BINARY = 6'b000011; + 4 : CLK_COR_MIN_LAT_0_BINARY = 6'b000100; + 5 : CLK_COR_MIN_LAT_0_BINARY = 6'b000101; + 6 : CLK_COR_MIN_LAT_0_BINARY = 6'b000110; + 7 : CLK_COR_MIN_LAT_0_BINARY = 6'b000111; + 8 : CLK_COR_MIN_LAT_0_BINARY = 6'b001000; + 9 : CLK_COR_MIN_LAT_0_BINARY = 6'b001001; + 10 : CLK_COR_MIN_LAT_0_BINARY = 6'b001010; + 11 : CLK_COR_MIN_LAT_0_BINARY = 6'b001011; + 12 : CLK_COR_MIN_LAT_0_BINARY = 6'b001100; + 13 : CLK_COR_MIN_LAT_0_BINARY = 6'b001101; + 14 : CLK_COR_MIN_LAT_0_BINARY = 6'b001110; + 15 : CLK_COR_MIN_LAT_0_BINARY = 6'b001111; + 16 : CLK_COR_MIN_LAT_0_BINARY = 6'b010000; + 17 : CLK_COR_MIN_LAT_0_BINARY = 6'b010001; + 18 : CLK_COR_MIN_LAT_0_BINARY = 6'b010010; + 19 : CLK_COR_MIN_LAT_0_BINARY = 6'b010011; + 20 : CLK_COR_MIN_LAT_0_BINARY = 6'b010100; + 21 : CLK_COR_MIN_LAT_0_BINARY = 6'b010101; + 22 : CLK_COR_MIN_LAT_0_BINARY = 6'b010110; + 23 : CLK_COR_MIN_LAT_0_BINARY = 6'b010111; + 24 : CLK_COR_MIN_LAT_0_BINARY = 6'b011000; + 25 : CLK_COR_MIN_LAT_0_BINARY = 6'b011001; + 26 : CLK_COR_MIN_LAT_0_BINARY = 6'b011010; + 27 : CLK_COR_MIN_LAT_0_BINARY = 6'b011011; + 28 : CLK_COR_MIN_LAT_0_BINARY = 6'b011100; + 29 : CLK_COR_MIN_LAT_0_BINARY = 6'b011101; + 30 : CLK_COR_MIN_LAT_0_BINARY = 6'b011110; + 31 : CLK_COR_MIN_LAT_0_BINARY = 6'b011111; + 32 : CLK_COR_MIN_LAT_0_BINARY = 6'b100000; + 33 : CLK_COR_MIN_LAT_0_BINARY = 6'b100001; + 34 : CLK_COR_MIN_LAT_0_BINARY = 6'b100010; + 35 : CLK_COR_MIN_LAT_0_BINARY = 6'b100011; + 36 : CLK_COR_MIN_LAT_0_BINARY = 6'b100100; + 37 : CLK_COR_MIN_LAT_0_BINARY = 6'b100101; + 38 : CLK_COR_MIN_LAT_0_BINARY = 6'b100110; + 39 : CLK_COR_MIN_LAT_0_BINARY = 6'b100111; + 40 : CLK_COR_MIN_LAT_0_BINARY = 6'b101000; + 41 : CLK_COR_MIN_LAT_0_BINARY = 6'b101001; + 42 : CLK_COR_MIN_LAT_0_BINARY = 6'b101010; + 43 : CLK_COR_MIN_LAT_0_BINARY = 6'b101011; + 44 : CLK_COR_MIN_LAT_0_BINARY = 6'b101100; + 45 : CLK_COR_MIN_LAT_0_BINARY = 6'b101101; + 46 : CLK_COR_MIN_LAT_0_BINARY = 6'b101110; + 47 : CLK_COR_MIN_LAT_0_BINARY = 6'b101111; + 48 : CLK_COR_MIN_LAT_0_BINARY = 6'b110000; + default : begin + $display("Attribute Syntax Error : The Attribute CLK_COR_MIN_LAT_0 on GTP_DUAL instance %m is set to %d. Legal values for this attribute are 3 to 48.", CLK_COR_MIN_LAT_0); + $finish; + end + endcase + + case (CLK_COR_MAX_LAT_0) + 3 : CLK_COR_MAX_LAT_0_BINARY = 6'b000011; + 4 : CLK_COR_MAX_LAT_0_BINARY = 6'b000100; + 5 : CLK_COR_MAX_LAT_0_BINARY = 6'b000101; + 6 : CLK_COR_MAX_LAT_0_BINARY = 6'b000110; + 7 : CLK_COR_MAX_LAT_0_BINARY = 6'b000111; + 8 : CLK_COR_MAX_LAT_0_BINARY = 6'b001000; + 9 : CLK_COR_MAX_LAT_0_BINARY = 6'b001001; + 10 : CLK_COR_MAX_LAT_0_BINARY = 6'b001010; + 11 : CLK_COR_MAX_LAT_0_BINARY = 6'b001011; + 12 : CLK_COR_MAX_LAT_0_BINARY = 6'b001100; + 13 : CLK_COR_MAX_LAT_0_BINARY = 6'b001101; + 14 : CLK_COR_MAX_LAT_0_BINARY = 6'b001110; + 15 : CLK_COR_MAX_LAT_0_BINARY = 6'b001111; + 16 : CLK_COR_MAX_LAT_0_BINARY = 6'b010000; + 17 : CLK_COR_MAX_LAT_0_BINARY = 6'b010001; + 18 : CLK_COR_MAX_LAT_0_BINARY = 6'b010010; + 19 : CLK_COR_MAX_LAT_0_BINARY = 6'b010011; + 20 : CLK_COR_MAX_LAT_0_BINARY = 6'b010100; + 21 : CLK_COR_MAX_LAT_0_BINARY = 6'b010101; + 22 : CLK_COR_MAX_LAT_0_BINARY = 6'b010110; + 23 : CLK_COR_MAX_LAT_0_BINARY = 6'b010111; + 24 : CLK_COR_MAX_LAT_0_BINARY = 6'b011000; + 25 : CLK_COR_MAX_LAT_0_BINARY = 6'b011001; + 26 : CLK_COR_MAX_LAT_0_BINARY = 6'b011010; + 27 : CLK_COR_MAX_LAT_0_BINARY = 6'b011011; + 28 : CLK_COR_MAX_LAT_0_BINARY = 6'b011100; + 29 : CLK_COR_MAX_LAT_0_BINARY = 6'b011101; + 30 : CLK_COR_MAX_LAT_0_BINARY = 6'b011110; + 31 : CLK_COR_MAX_LAT_0_BINARY = 6'b011111; + 32 : CLK_COR_MAX_LAT_0_BINARY = 6'b100000; + 33 : CLK_COR_MAX_LAT_0_BINARY = 6'b100001; + 34 : CLK_COR_MAX_LAT_0_BINARY = 6'b100010; + 35 : CLK_COR_MAX_LAT_0_BINARY = 6'b100011; + 36 : CLK_COR_MAX_LAT_0_BINARY = 6'b100100; + 37 : CLK_COR_MAX_LAT_0_BINARY = 6'b100101; + 38 : CLK_COR_MAX_LAT_0_BINARY = 6'b100110; + 39 : CLK_COR_MAX_LAT_0_BINARY = 6'b100111; + 40 : CLK_COR_MAX_LAT_0_BINARY = 6'b101000; + 41 : CLK_COR_MAX_LAT_0_BINARY = 6'b101001; + 42 : CLK_COR_MAX_LAT_0_BINARY = 6'b101010; + 43 : CLK_COR_MAX_LAT_0_BINARY = 6'b101011; + 44 : CLK_COR_MAX_LAT_0_BINARY = 6'b101100; + 45 : CLK_COR_MAX_LAT_0_BINARY = 6'b101101; + 46 : CLK_COR_MAX_LAT_0_BINARY = 6'b101110; + 47 : CLK_COR_MAX_LAT_0_BINARY = 6'b101111; + 48 : CLK_COR_MAX_LAT_0_BINARY = 6'b110000; + default : begin + $display("Attribute Syntax Error : The Attribute CLK_COR_MAX_LAT_0 on GTP_DUAL instance %m is set to %d. Legal values for this attribute are 3 to 48.", CLK_COR_MAX_LAT_0); + $finish; + end + endcase + + case (CLK_CORRECT_USE_0) + "FALSE" : CLK_CORRECT_USE_0_BINARY = 1'b0; + "TRUE" : CLK_CORRECT_USE_0_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute CLK_CORRECT_USE_0 on GTP_DUAL instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", CLK_CORRECT_USE_0); + $finish; + end + endcase + + case (CLK_COR_PRECEDENCE_0) + "FALSE" : CLK_COR_PRECEDENCE_0_BINARY = 1'b0; + "TRUE" : CLK_COR_PRECEDENCE_0_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute CLK_COR_PRECEDENCE_0 on GTP_DUAL instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", CLK_COR_PRECEDENCE_0); + $finish; + end + endcase + + case (CLK_COR_DET_LEN_0) + 1 : CLK_COR_DET_LEN_0_BINARY = 2'b00; + 2 : CLK_COR_DET_LEN_0_BINARY = 2'b01; + 3 : CLK_COR_DET_LEN_0_BINARY = 2'b10; + 4 : CLK_COR_DET_LEN_0_BINARY = 2'b11; + default : begin + $display("Attribute Syntax Error : The Attribute CLK_COR_DET_LEN_0 on GTP_DUAL instance %m is set to %d. Legal values for this attribute are 1, 2, 3 or 4.", CLK_COR_DET_LEN_0); + $finish; + end + endcase + + case (CLK_COR_ADJ_LEN_0) + 1 : CLK_COR_ADJ_LEN_0_BINARY = 2'b00; + 2 : CLK_COR_ADJ_LEN_0_BINARY = 2'b01; + 3 : CLK_COR_ADJ_LEN_0_BINARY = 2'b10; + 4 : CLK_COR_ADJ_LEN_0_BINARY = 2'b11; + default : begin + $display("Attribute Syntax Error : The Attribute CLK_COR_ADJ_LEN_0 on GTP_DUAL instance %m is set to %d. Legal values for this attribute are 1, 2, 3 or 4.", CLK_COR_ADJ_LEN_0); + $finish; + end + endcase + + case (CLK_COR_KEEP_IDLE_0) + "FALSE" : CLK_COR_KEEP_IDLE_0_BINARY = 1'b0; + "TRUE" : CLK_COR_KEEP_IDLE_0_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute CLK_COR_KEEP_IDLE_0 on GTP_DUAL instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", CLK_COR_KEEP_IDLE_0); + $finish; + end + endcase + + case (CLK_COR_INSERT_IDLE_FLAG_0) + "FALSE" : CLK_COR_INSERT_IDLE_FLAG_0_BINARY = 1'b0; + "TRUE" : CLK_COR_INSERT_IDLE_FLAG_0_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute CLK_COR_INSERT_IDLE_FLAG_0 on GTP_DUAL instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", CLK_COR_INSERT_IDLE_FLAG_0); + $finish; + end + endcase + + case (CLK_COR_REPEAT_WAIT_0) + 0 : CLK_COR_REPEAT_WAIT_0_BINARY = 5'b00000; + 1 : CLK_COR_REPEAT_WAIT_0_BINARY = 5'b00001; + 2 : CLK_COR_REPEAT_WAIT_0_BINARY = 5'b00010; + 3 : CLK_COR_REPEAT_WAIT_0_BINARY = 5'b00011; + 4 : CLK_COR_REPEAT_WAIT_0_BINARY = 5'b00100; + 5 : CLK_COR_REPEAT_WAIT_0_BINARY = 5'b00101; + 6 : CLK_COR_REPEAT_WAIT_0_BINARY = 5'b00110; + 7 : CLK_COR_REPEAT_WAIT_0_BINARY = 5'b00111; + 8 : CLK_COR_REPEAT_WAIT_0_BINARY = 5'b01000; + 9 : CLK_COR_REPEAT_WAIT_0_BINARY = 5'b01001; + 10 : CLK_COR_REPEAT_WAIT_0_BINARY = 5'b01010; + 11 : CLK_COR_REPEAT_WAIT_0_BINARY = 5'b01011; + 12 : CLK_COR_REPEAT_WAIT_0_BINARY = 5'b01100; + 13 : CLK_COR_REPEAT_WAIT_0_BINARY = 5'b01101; + 14 : CLK_COR_REPEAT_WAIT_0_BINARY = 5'b01110; + 15 : CLK_COR_REPEAT_WAIT_0_BINARY = 5'b01111; + 16 : CLK_COR_REPEAT_WAIT_0_BINARY = 5'b10000; + 17 : CLK_COR_REPEAT_WAIT_0_BINARY = 5'b10001; + 18 : CLK_COR_REPEAT_WAIT_0_BINARY = 5'b10010; + 19 : CLK_COR_REPEAT_WAIT_0_BINARY = 5'b10011; + 20 : CLK_COR_REPEAT_WAIT_0_BINARY = 5'b10100; + 21 : CLK_COR_REPEAT_WAIT_0_BINARY = 5'b10101; + 22 : CLK_COR_REPEAT_WAIT_0_BINARY = 5'b10110; + 23 : CLK_COR_REPEAT_WAIT_0_BINARY = 5'b10111; + 24 : CLK_COR_REPEAT_WAIT_0_BINARY = 5'b11000; + 25 : CLK_COR_REPEAT_WAIT_0_BINARY = 5'b11001; + 26 : CLK_COR_REPEAT_WAIT_0_BINARY = 5'b11010; + 27 : CLK_COR_REPEAT_WAIT_0_BINARY = 5'b11011; + 28 : CLK_COR_REPEAT_WAIT_0_BINARY = 5'b11100; + 29 : CLK_COR_REPEAT_WAIT_0_BINARY = 5'b11101; + 30 : CLK_COR_REPEAT_WAIT_0_BINARY = 5'b11110; + 31 : CLK_COR_REPEAT_WAIT_0_BINARY = 5'b11111; + default : begin + $display("Attribute Syntax Error : The Attribute CLK_COR_REPEAT_WAIT_0 on GTP_DUAL instance %m is set to %d. Legal values for this attribute are 0 to 31.", CLK_COR_REPEAT_WAIT_0); + $finish; + end + endcase + + case (CLK_COR_SEQ_2_USE_0) + "FALSE" : CLK_COR_SEQ_2_USE_0_BINARY = 1'b0; + "TRUE" : CLK_COR_SEQ_2_USE_0_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute CLK_COR_SEQ_2_USE_0 on GTP_DUAL instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", CLK_COR_SEQ_2_USE_0); + $finish; + end + endcase + + case (CLK_COR_MIN_LAT_1) + 3 : CLK_COR_MIN_LAT_1_BINARY = 6'b000011; + 4 : CLK_COR_MIN_LAT_1_BINARY = 6'b000100; + 5 : CLK_COR_MIN_LAT_1_BINARY = 6'b000101; + 6 : CLK_COR_MIN_LAT_1_BINARY = 6'b000110; + 7 : CLK_COR_MIN_LAT_1_BINARY = 6'b000111; + 8 : CLK_COR_MIN_LAT_1_BINARY = 6'b001000; + 9 : CLK_COR_MIN_LAT_1_BINARY = 6'b001001; + 10 : CLK_COR_MIN_LAT_1_BINARY = 6'b001010; + 11 : CLK_COR_MIN_LAT_1_BINARY = 6'b001011; + 12 : CLK_COR_MIN_LAT_1_BINARY = 6'b001100; + 13 : CLK_COR_MIN_LAT_1_BINARY = 6'b001101; + 14 : CLK_COR_MIN_LAT_1_BINARY = 6'b001110; + 15 : CLK_COR_MIN_LAT_1_BINARY = 6'b001111; + 16 : CLK_COR_MIN_LAT_1_BINARY = 6'b010000; + 17 : CLK_COR_MIN_LAT_1_BINARY = 6'b010001; + 18 : CLK_COR_MIN_LAT_1_BINARY = 6'b010010; + 19 : CLK_COR_MIN_LAT_1_BINARY = 6'b010011; + 20 : CLK_COR_MIN_LAT_1_BINARY = 6'b010100; + 21 : CLK_COR_MIN_LAT_1_BINARY = 6'b010101; + 22 : CLK_COR_MIN_LAT_1_BINARY = 6'b010110; + 23 : CLK_COR_MIN_LAT_1_BINARY = 6'b010111; + 24 : CLK_COR_MIN_LAT_1_BINARY = 6'b011000; + 25 : CLK_COR_MIN_LAT_1_BINARY = 6'b011001; + 26 : CLK_COR_MIN_LAT_1_BINARY = 6'b011010; + 27 : CLK_COR_MIN_LAT_1_BINARY = 6'b011011; + 28 : CLK_COR_MIN_LAT_1_BINARY = 6'b011100; + 29 : CLK_COR_MIN_LAT_1_BINARY = 6'b011101; + 30 : CLK_COR_MIN_LAT_1_BINARY = 6'b011110; + 31 : CLK_COR_MIN_LAT_1_BINARY = 6'b011111; + 32 : CLK_COR_MIN_LAT_1_BINARY = 6'b100000; + 33 : CLK_COR_MIN_LAT_1_BINARY = 6'b100001; + 34 : CLK_COR_MIN_LAT_1_BINARY = 6'b100010; + 35 : CLK_COR_MIN_LAT_1_BINARY = 6'b100011; + 36 : CLK_COR_MIN_LAT_1_BINARY = 6'b100100; + 37 : CLK_COR_MIN_LAT_1_BINARY = 6'b100101; + 38 : CLK_COR_MIN_LAT_1_BINARY = 6'b100110; + 39 : CLK_COR_MIN_LAT_1_BINARY = 6'b100111; + 40 : CLK_COR_MIN_LAT_1_BINARY = 6'b101000; + 41 : CLK_COR_MIN_LAT_1_BINARY = 6'b101001; + 42 : CLK_COR_MIN_LAT_1_BINARY = 6'b101010; + 43 : CLK_COR_MIN_LAT_1_BINARY = 6'b101011; + 44 : CLK_COR_MIN_LAT_1_BINARY = 6'b101100; + 45 : CLK_COR_MIN_LAT_1_BINARY = 6'b101101; + 46 : CLK_COR_MIN_LAT_1_BINARY = 6'b101110; + 47 : CLK_COR_MIN_LAT_1_BINARY = 6'b101111; + 48 : CLK_COR_MIN_LAT_1_BINARY = 6'b110000; + default : begin + $display("Attribute Syntax Error : The Attribute CLK_COR_MIN_LAT_1 on GTP_DUAL instance %m is set to %d. Legal values for this attribute are 3 to 48.", CLK_COR_MIN_LAT_1); + $finish; + end + endcase + + case (CLK_COR_MAX_LAT_1) + 3 : CLK_COR_MAX_LAT_1_BINARY = 6'b000011; + 4 : CLK_COR_MAX_LAT_1_BINARY = 6'b000100; + 5 : CLK_COR_MAX_LAT_1_BINARY = 6'b000101; + 6 : CLK_COR_MAX_LAT_1_BINARY = 6'b000110; + 7 : CLK_COR_MAX_LAT_1_BINARY = 6'b000111; + 8 : CLK_COR_MAX_LAT_1_BINARY = 6'b001000; + 9 : CLK_COR_MAX_LAT_1_BINARY = 6'b001001; + 10 : CLK_COR_MAX_LAT_1_BINARY = 6'b001010; + 11 : CLK_COR_MAX_LAT_1_BINARY = 6'b001011; + 12 : CLK_COR_MAX_LAT_1_BINARY = 6'b001100; + 13 : CLK_COR_MAX_LAT_1_BINARY = 6'b001101; + 14 : CLK_COR_MAX_LAT_1_BINARY = 6'b001110; + 15 : CLK_COR_MAX_LAT_1_BINARY = 6'b001111; + 16 : CLK_COR_MAX_LAT_1_BINARY = 6'b010000; + 17 : CLK_COR_MAX_LAT_1_BINARY = 6'b010001; + 18 : CLK_COR_MAX_LAT_1_BINARY = 6'b010010; + 19 : CLK_COR_MAX_LAT_1_BINARY = 6'b010011; + 20 : CLK_COR_MAX_LAT_1_BINARY = 6'b010100; + 21 : CLK_COR_MAX_LAT_1_BINARY = 6'b010101; + 22 : CLK_COR_MAX_LAT_1_BINARY = 6'b010110; + 23 : CLK_COR_MAX_LAT_1_BINARY = 6'b010111; + 24 : CLK_COR_MAX_LAT_1_BINARY = 6'b011000; + 25 : CLK_COR_MAX_LAT_1_BINARY = 6'b011001; + 26 : CLK_COR_MAX_LAT_1_BINARY = 6'b011010; + 27 : CLK_COR_MAX_LAT_1_BINARY = 6'b011011; + 28 : CLK_COR_MAX_LAT_1_BINARY = 6'b011100; + 29 : CLK_COR_MAX_LAT_1_BINARY = 6'b011101; + 30 : CLK_COR_MAX_LAT_1_BINARY = 6'b011110; + 31 : CLK_COR_MAX_LAT_1_BINARY = 6'b011111; + 32 : CLK_COR_MAX_LAT_1_BINARY = 6'b100000; + 33 : CLK_COR_MAX_LAT_1_BINARY = 6'b100001; + 34 : CLK_COR_MAX_LAT_1_BINARY = 6'b100010; + 35 : CLK_COR_MAX_LAT_1_BINARY = 6'b100011; + 36 : CLK_COR_MAX_LAT_1_BINARY = 6'b100100; + 37 : CLK_COR_MAX_LAT_1_BINARY = 6'b100101; + 38 : CLK_COR_MAX_LAT_1_BINARY = 6'b100110; + 39 : CLK_COR_MAX_LAT_1_BINARY = 6'b100111; + 40 : CLK_COR_MAX_LAT_1_BINARY = 6'b101000; + 41 : CLK_COR_MAX_LAT_1_BINARY = 6'b101001; + 42 : CLK_COR_MAX_LAT_1_BINARY = 6'b101010; + 43 : CLK_COR_MAX_LAT_1_BINARY = 6'b101011; + 44 : CLK_COR_MAX_LAT_1_BINARY = 6'b101100; + 45 : CLK_COR_MAX_LAT_1_BINARY = 6'b101101; + 46 : CLK_COR_MAX_LAT_1_BINARY = 6'b101110; + 47 : CLK_COR_MAX_LAT_1_BINARY = 6'b101111; + 48 : CLK_COR_MAX_LAT_1_BINARY = 6'b110000; + default : begin + $display("Attribute Syntax Error : The Attribute CLK_COR_MAX_LAT_1 on GTP_DUAL instance %m is set to %d. Legal values for this attribute are 3 to 48.", CLK_COR_MAX_LAT_1); + $finish; + end + endcase + + case (CLK_CORRECT_USE_1) + "FALSE" : CLK_CORRECT_USE_1_BINARY = 1'b0; + "TRUE" : CLK_CORRECT_USE_1_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute CLK_CORRECT_USE_1 on GTP_DUAL instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", CLK_CORRECT_USE_1); + $finish; + end + endcase + + case (CLK_COR_PRECEDENCE_1) + "FALSE" : CLK_COR_PRECEDENCE_1_BINARY = 1'b0; + "TRUE" : CLK_COR_PRECEDENCE_1_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute CLK_COR_PRECEDENCE_1 on GTP_DUAL instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", CLK_COR_PRECEDENCE_1); + $finish; + end + endcase + + case (CLK_COR_DET_LEN_1) + 1 : CLK_COR_DET_LEN_1_BINARY = 2'b00; + 2 : CLK_COR_DET_LEN_1_BINARY = 2'b01; + 3 : CLK_COR_DET_LEN_1_BINARY = 2'b10; + 4 : CLK_COR_DET_LEN_1_BINARY = 2'b11; + default : begin + $display("Attribute Syntax Error : The Attribute CLK_COR_DET_LEN_1 on GTP_DUAL instance %m is set to %d. Legal values for this attribute are 1, 2, 3 or 4.", CLK_COR_DET_LEN_1); + $finish; + end + endcase + + case (CLK_COR_ADJ_LEN_1) + 1 : CLK_COR_ADJ_LEN_1_BINARY = 2'b00; + 2 : CLK_COR_ADJ_LEN_1_BINARY = 2'b01; + 3 : CLK_COR_ADJ_LEN_1_BINARY = 2'b10; + 4 : CLK_COR_ADJ_LEN_1_BINARY = 2'b11; + default : begin + $display("Attribute Syntax Error : The Attribute CLK_COR_ADJ_LEN_1 on GTP_DUAL instance %m is set to %d. Legal values for this attribute are 1, 2, 3 or 4.", CLK_COR_ADJ_LEN_1); + $finish; + end + endcase + + case (CLK_COR_KEEP_IDLE_1) + "FALSE" : CLK_COR_KEEP_IDLE_1_BINARY = 1'b0; + "TRUE" : CLK_COR_KEEP_IDLE_1_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute CLK_COR_KEEP_IDLE_1 on GTP_DUAL instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", CLK_COR_KEEP_IDLE_1); + $finish; + end + endcase + + case (CLK_COR_INSERT_IDLE_FLAG_1) + "FALSE" : CLK_COR_INSERT_IDLE_FLAG_1_BINARY = 1'b0; + "TRUE" : CLK_COR_INSERT_IDLE_FLAG_1_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute CLK_COR_INSERT_IDLE_FLAG_1 on GTP_DUAL instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", CLK_COR_INSERT_IDLE_FLAG_1); + $finish; + end + endcase + + case (CLK_COR_REPEAT_WAIT_1) + 0 : CLK_COR_REPEAT_WAIT_1_BINARY = 5'b00000; + 1 : CLK_COR_REPEAT_WAIT_1_BINARY = 5'b00001; + 2 : CLK_COR_REPEAT_WAIT_1_BINARY = 5'b00010; + 3 : CLK_COR_REPEAT_WAIT_1_BINARY = 5'b00011; + 4 : CLK_COR_REPEAT_WAIT_1_BINARY = 5'b00100; + 5 : CLK_COR_REPEAT_WAIT_1_BINARY = 5'b00101; + 6 : CLK_COR_REPEAT_WAIT_1_BINARY = 5'b00110; + 7 : CLK_COR_REPEAT_WAIT_1_BINARY = 5'b00111; + 8 : CLK_COR_REPEAT_WAIT_1_BINARY = 5'b01000; + 9 : CLK_COR_REPEAT_WAIT_1_BINARY = 5'b01001; + 10 : CLK_COR_REPEAT_WAIT_1_BINARY = 5'b01010; + 11 : CLK_COR_REPEAT_WAIT_1_BINARY = 5'b01011; + 12 : CLK_COR_REPEAT_WAIT_1_BINARY = 5'b01100; + 13 : CLK_COR_REPEAT_WAIT_1_BINARY = 5'b01101; + 14 : CLK_COR_REPEAT_WAIT_1_BINARY = 5'b01110; + 15 : CLK_COR_REPEAT_WAIT_1_BINARY = 5'b01111; + 16 : CLK_COR_REPEAT_WAIT_1_BINARY = 5'b10000; + 17 : CLK_COR_REPEAT_WAIT_1_BINARY = 5'b10001; + 18 : CLK_COR_REPEAT_WAIT_1_BINARY = 5'b10010; + 19 : CLK_COR_REPEAT_WAIT_1_BINARY = 5'b10011; + 20 : CLK_COR_REPEAT_WAIT_1_BINARY = 5'b10100; + 21 : CLK_COR_REPEAT_WAIT_1_BINARY = 5'b10101; + 22 : CLK_COR_REPEAT_WAIT_1_BINARY = 5'b10110; + 23 : CLK_COR_REPEAT_WAIT_1_BINARY = 5'b10111; + 24 : CLK_COR_REPEAT_WAIT_1_BINARY = 5'b11000; + 25 : CLK_COR_REPEAT_WAIT_1_BINARY = 5'b11001; + 26 : CLK_COR_REPEAT_WAIT_1_BINARY = 5'b11010; + 27 : CLK_COR_REPEAT_WAIT_1_BINARY = 5'b11011; + 28 : CLK_COR_REPEAT_WAIT_1_BINARY = 5'b11100; + 29 : CLK_COR_REPEAT_WAIT_1_BINARY = 5'b11101; + 30 : CLK_COR_REPEAT_WAIT_1_BINARY = 5'b11110; + 31 : CLK_COR_REPEAT_WAIT_1_BINARY = 5'b11111; + default : begin + $display("Attribute Syntax Error : The Attribute CLK_COR_REPEAT_WAIT_1 on GTP_DUAL instance %m is set to %d. Legal values for this attribute are 0 to 31.", CLK_COR_REPEAT_WAIT_1); + $finish; + end + endcase + + case (CLK_COR_SEQ_2_USE_1) + "FALSE" : CLK_COR_SEQ_2_USE_1_BINARY = 1'b0; + "TRUE" : CLK_COR_SEQ_2_USE_1_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute CLK_COR_SEQ_2_USE_1 on GTP_DUAL instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", CLK_COR_SEQ_2_USE_1); + $finish; + end + endcase + + case (CHAN_BOND_MODE_0) + "OFF" : CHAN_BOND_MODE_0_BINARY = 2'b00; + "MASTER" : CHAN_BOND_MODE_0_BINARY = 2'b01; + "SLAVE" : CHAN_BOND_MODE_0_BINARY = 2'b10; + default : begin + $display("Attribute Syntax Error : The Attribute CHAN_BOND_MODE_0 on GTP_DUAL instance %m is set to %s. Legal values for this attribute are OFF, MASTER or SLAVE.", CHAN_BOND_MODE_0); + $finish; + end + endcase + + case (CHAN_BOND_LEVEL_0) + 0 : CHAN_BOND_LEVEL_0_BINARY = 3'b000; + 1 : CHAN_BOND_LEVEL_0_BINARY = 3'b001; + 2 : CHAN_BOND_LEVEL_0_BINARY = 3'b010; + 3 : CHAN_BOND_LEVEL_0_BINARY = 3'b011; + 4 : CHAN_BOND_LEVEL_0_BINARY = 3'b100; + 5 : CHAN_BOND_LEVEL_0_BINARY = 3'b101; + 6 : CHAN_BOND_LEVEL_0_BINARY = 3'b110; + 7 : CHAN_BOND_LEVEL_0_BINARY = 3'b111; + default : begin + $display("Attribute Syntax Error : The Attribute CHAN_BOND_LEVEL_0 on GTP_DUAL instance %m is set to %d. Legal values for this attribute are 0 to 7.", CHAN_BOND_LEVEL_0); + $finish; + end + endcase + + case (CHAN_BOND_SEQ_LEN_0) + 1 : CHAN_BOND_SEQ_LEN_0_BINARY = 2'b00; + 2 : CHAN_BOND_SEQ_LEN_0_BINARY = 2'b01; + 3 : CHAN_BOND_SEQ_LEN_0_BINARY = 2'b10; + 4 : CHAN_BOND_SEQ_LEN_0_BINARY = 2'b11; + default : begin + $display("Attribute Syntax Error : The Attribute CHAN_BOND_SEQ_LEN_0 on GTP_DUAL instance %m is set to %d. Legal values for this attribute are 1, 2, 3 or 4.", CHAN_BOND_SEQ_LEN_0); + $finish; + end + endcase + + case (CHAN_BOND_SEQ_2_USE_0) + "FALSE" : CHAN_BOND_SEQ_2_USE_0_BINARY = 1'b0; + "TRUE" : CHAN_BOND_SEQ_2_USE_0_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute CHAN_BOND_SEQ_2_USE_0 on GTP_DUAL instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", CHAN_BOND_SEQ_2_USE_0); + $finish; + end + endcase + + case (CHAN_BOND_1_MAX_SKEW_0) + 1 : CHAN_BOND_1_MAX_SKEW_0_BINARY = 4'b0001; + 2 : CHAN_BOND_1_MAX_SKEW_0_BINARY = 4'b0010; + 3 : CHAN_BOND_1_MAX_SKEW_0_BINARY = 4'b0011; + 4 : CHAN_BOND_1_MAX_SKEW_0_BINARY = 4'b0100; + 5 : CHAN_BOND_1_MAX_SKEW_0_BINARY = 4'b0101; + 6 : CHAN_BOND_1_MAX_SKEW_0_BINARY = 4'b0110; + 7 : CHAN_BOND_1_MAX_SKEW_0_BINARY = 4'b0111; + 8 : CHAN_BOND_1_MAX_SKEW_0_BINARY = 4'b1000; + 9 : CHAN_BOND_1_MAX_SKEW_0_BINARY = 4'b1001; + 10 : CHAN_BOND_1_MAX_SKEW_0_BINARY = 4'b1010; + 11 : CHAN_BOND_1_MAX_SKEW_0_BINARY = 4'b1011; + 12 : CHAN_BOND_1_MAX_SKEW_0_BINARY = 4'b1100; + 13 : CHAN_BOND_1_MAX_SKEW_0_BINARY = 4'b1101; + 14 : CHAN_BOND_1_MAX_SKEW_0_BINARY = 4'b1110; + default : begin + $display("Attribute Syntax Error : The Attribute CHAN_BOND_1_MAX_SKEW_0 on GTP_DUAL instance %m is set to %d. Legal values for this attribute are 1 to 14.", CHAN_BOND_1_MAX_SKEW_0); + $finish; + end + endcase + + case (CHAN_BOND_2_MAX_SKEW_0) + 1 : CHAN_BOND_2_MAX_SKEW_0_BINARY = 4'b0001; + 2 : CHAN_BOND_2_MAX_SKEW_0_BINARY = 4'b0010; + 3 : CHAN_BOND_2_MAX_SKEW_0_BINARY = 4'b0011; + 4 : CHAN_BOND_2_MAX_SKEW_0_BINARY = 4'b0100; + 5 : CHAN_BOND_2_MAX_SKEW_0_BINARY = 4'b0101; + 6 : CHAN_BOND_2_MAX_SKEW_0_BINARY = 4'b0110; + 7 : CHAN_BOND_2_MAX_SKEW_0_BINARY = 4'b0111; + 8 : CHAN_BOND_2_MAX_SKEW_0_BINARY = 4'b1000; + 9 : CHAN_BOND_2_MAX_SKEW_0_BINARY = 4'b1001; + 10 : CHAN_BOND_2_MAX_SKEW_0_BINARY = 4'b1010; + 11 : CHAN_BOND_2_MAX_SKEW_0_BINARY = 4'b1011; + 12 : CHAN_BOND_2_MAX_SKEW_0_BINARY = 4'b1100; + 13 : CHAN_BOND_2_MAX_SKEW_0_BINARY = 4'b1101; + 14 : CHAN_BOND_2_MAX_SKEW_0_BINARY = 4'b1110; + default : begin + $display("Attribute Syntax Error : The Attribute CHAN_BOND_2_MAX_SKEW_0 on GTP_DUAL instance %m is set to %d. Legal values for this attribute are 1 to 14.", CHAN_BOND_2_MAX_SKEW_0); + $finish; + end + endcase + + case (CHAN_BOND_MODE_1) + "OFF" : CHAN_BOND_MODE_1_BINARY = 2'b00; + "MASTER" : CHAN_BOND_MODE_1_BINARY = 2'b01; + "SLAVE" : CHAN_BOND_MODE_1_BINARY = 2'b10; + default : begin + $display("Attribute Syntax Error : The Attribute CHAN_BOND_MODE_1 on GTP_DUAL instance %m is set to %s. Legal values for this attribute are OFF, MASTER or SLAVE.", CHAN_BOND_MODE_1); + $finish; + end + endcase + + case (CHAN_BOND_LEVEL_1) + 0 : CHAN_BOND_LEVEL_1_BINARY = 3'b000; + 1 : CHAN_BOND_LEVEL_1_BINARY = 3'b001; + 2 : CHAN_BOND_LEVEL_1_BINARY = 3'b010; + 3 : CHAN_BOND_LEVEL_1_BINARY = 3'b011; + 4 : CHAN_BOND_LEVEL_1_BINARY = 3'b100; + 5 : CHAN_BOND_LEVEL_1_BINARY = 3'b101; + 6 : CHAN_BOND_LEVEL_1_BINARY = 3'b110; + 7 : CHAN_BOND_LEVEL_1_BINARY = 3'b111; + default : begin + $display("Attribute Syntax Error : The Attribute CHAN_BOND_LEVEL_1 on GTP_DUAL instance %m is set to %d. Legal values for this attribute are 0 to 7.", CHAN_BOND_LEVEL_1); + $finish; + end + endcase + + case (CHAN_BOND_SEQ_LEN_1) + 1 : CHAN_BOND_SEQ_LEN_1_BINARY = 2'b00; + 2 : CHAN_BOND_SEQ_LEN_1_BINARY = 2'b01; + 3 : CHAN_BOND_SEQ_LEN_1_BINARY = 2'b10; + 4 : CHAN_BOND_SEQ_LEN_1_BINARY = 2'b11; + default : begin + $display("Attribute Syntax Error : The Attribute CHAN_BOND_SEQ_LEN_1 on GTP_DUAL instance %m is set to %d. Legal values for this attribute are 1, 2, 3 or 4.", CHAN_BOND_SEQ_LEN_1); + $finish; + end + endcase + + case (CHAN_BOND_SEQ_2_USE_1) + "FALSE" : CHAN_BOND_SEQ_2_USE_1_BINARY = 1'b0; + "TRUE" : CHAN_BOND_SEQ_2_USE_1_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute CHAN_BOND_SEQ_2_USE_1 on GTP_DUAL instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", CHAN_BOND_SEQ_2_USE_1); + $finish; + end + endcase + + case (CHAN_BOND_1_MAX_SKEW_1) + 1 : CHAN_BOND_1_MAX_SKEW_1_BINARY = 4'b0001; + 2 : CHAN_BOND_1_MAX_SKEW_1_BINARY = 4'b0010; + 3 : CHAN_BOND_1_MAX_SKEW_1_BINARY = 4'b0011; + 4 : CHAN_BOND_1_MAX_SKEW_1_BINARY = 4'b0100; + 5 : CHAN_BOND_1_MAX_SKEW_1_BINARY = 4'b0101; + 6 : CHAN_BOND_1_MAX_SKEW_1_BINARY = 4'b0110; + 7 : CHAN_BOND_1_MAX_SKEW_1_BINARY = 4'b0111; + 8 : CHAN_BOND_1_MAX_SKEW_1_BINARY = 4'b1000; + 9 : CHAN_BOND_1_MAX_SKEW_1_BINARY = 4'b1001; + 10 : CHAN_BOND_1_MAX_SKEW_1_BINARY = 4'b1010; + 11 : CHAN_BOND_1_MAX_SKEW_1_BINARY = 4'b1011; + 12 : CHAN_BOND_1_MAX_SKEW_1_BINARY = 4'b1100; + 13 : CHAN_BOND_1_MAX_SKEW_1_BINARY = 4'b1101; + 14 : CHAN_BOND_1_MAX_SKEW_1_BINARY = 4'b1110; + default : begin + $display("Attribute Syntax Error : The Attribute CHAN_BOND_1_MAX_SKEW_1 on GTP_DUAL instance %m is set to %d. Legal values for this attribute are 1 to 14.", CHAN_BOND_1_MAX_SKEW_1); + $finish; + end + endcase + + case (CHAN_BOND_2_MAX_SKEW_1) + 1 : CHAN_BOND_2_MAX_SKEW_1_BINARY = 4'b0001; + 2 : CHAN_BOND_2_MAX_SKEW_1_BINARY = 4'b0010; + 3 : CHAN_BOND_2_MAX_SKEW_1_BINARY = 4'b0011; + 4 : CHAN_BOND_2_MAX_SKEW_1_BINARY = 4'b0100; + 5 : CHAN_BOND_2_MAX_SKEW_1_BINARY = 4'b0101; + 6 : CHAN_BOND_2_MAX_SKEW_1_BINARY = 4'b0110; + 7 : CHAN_BOND_2_MAX_SKEW_1_BINARY = 4'b0111; + 8 : CHAN_BOND_2_MAX_SKEW_1_BINARY = 4'b1000; + 9 : CHAN_BOND_2_MAX_SKEW_1_BINARY = 4'b1001; + 10 : CHAN_BOND_2_MAX_SKEW_1_BINARY = 4'b1010; + 11 : CHAN_BOND_2_MAX_SKEW_1_BINARY = 4'b1011; + 12 : CHAN_BOND_2_MAX_SKEW_1_BINARY = 4'b1100; + 13 : CHAN_BOND_2_MAX_SKEW_1_BINARY = 4'b1101; + 14 : CHAN_BOND_2_MAX_SKEW_1_BINARY = 4'b1110; + default : begin + $display("Attribute Syntax Error : The Attribute CHAN_BOND_2_MAX_SKEW_1 on GTP_DUAL instance %m is set to %d. Legal values for this attribute are 1 to 14.", CHAN_BOND_2_MAX_SKEW_1); + $finish; + end + endcase + + case (PCI_EXPRESS_MODE_0) + "FALSE" : PCI_EXPRESS_MODE_0_BINARY = 1'b0; + "TRUE" : PCI_EXPRESS_MODE_0_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute PCI_EXPRESS_MODE_0 on GTP_DUAL instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", PCI_EXPRESS_MODE_0); + $finish; + end + endcase + + case (PCI_EXPRESS_MODE_1) + "FALSE" : PCI_EXPRESS_MODE_1_BINARY = 1'b0; + "TRUE" : PCI_EXPRESS_MODE_1_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute PCI_EXPRESS_MODE_1 on GTP_DUAL instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", PCI_EXPRESS_MODE_1); + $finish; + end + endcase + + case (RX_STATUS_FMT_0) + "PCIE" : RX_STATUS_FMT_0_BINARY = 1'b0; + "SATA" : RX_STATUS_FMT_0_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute RX_STATUS_FMT_0 on GTP_DUAL instance %m is set to %s. Legal values for this attribute are PCIE or SATA.", RX_STATUS_FMT_0); + $finish; + end + endcase + + case (TX_BUFFER_USE_0) + "FALSE" : TX_BUFFER_USE_0_BINARY = 1'b0; + "TRUE" : TX_BUFFER_USE_0_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute TX_BUFFER_USE_0 on GTP_DUAL instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", TX_BUFFER_USE_0); + $finish; + end + endcase + + case (TX_XCLK_SEL_0) + "TXUSR" : TX_XCLK_SEL_0_BINARY = 1'b1; + "TXOUT" : TX_XCLK_SEL_0_BINARY = 1'b0; + default : begin + $display("Attribute Syntax Error : The Attribute TX_XCLK_SEL_0 on GTP_DUAL instance %m is set to %s. Legal values for this attribute are TXUSR or TXOUT.", TX_XCLK_SEL_0); + $finish; + end + endcase + + case (RX_XCLK_SEL_0) + "RXREC" : RX_XCLK_SEL_0_BINARY = 1'b0; + "RXUSR" : RX_XCLK_SEL_0_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute RX_XCLK_SEL_0 on GTP_DUAL instance %m is set to %s. Legal values for this attribute are RXREC or RXUSR.", RX_XCLK_SEL_0); + $finish; + end + endcase + + case (RX_STATUS_FMT_1) + "PCIE" : RX_STATUS_FMT_1_BINARY = 1'b0; + "SATA" : RX_STATUS_FMT_1_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute RX_STATUS_FMT_1 on GTP_DUAL instance %m is set to %s. Legal values for this attribute are PCIE or SATA.", RX_STATUS_FMT_1); + $finish; + end + endcase + + case (TX_BUFFER_USE_1) + "FALSE" : TX_BUFFER_USE_1_BINARY = 1'b0; + "TRUE" : TX_BUFFER_USE_1_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute TX_BUFFER_USE_1 on GTP_DUAL instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", TX_BUFFER_USE_1); + $finish; + end + endcase + + case (TX_XCLK_SEL_1) + "TXUSR" : TX_XCLK_SEL_1_BINARY = 1'b1; + "TXOUT" : TX_XCLK_SEL_1_BINARY = 1'b0; + default : begin + $display("Attribute Syntax Error : The Attribute TX_XCLK_SEL_1 on GTP_DUAL instance %m is set to %s. Legal values for this attribute are TXUSR or TXOUT.", TX_XCLK_SEL_1); + $finish; + end + endcase + + case (RX_XCLK_SEL_1) + "RXREC" : RX_XCLK_SEL_1_BINARY = 1'b0; + "RXUSR" : RX_XCLK_SEL_1_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute RX_XCLK_SEL_1 on GTP_DUAL instance %m is set to %s. Legal values for this attribute are RXREC or RXUSR.", RX_XCLK_SEL_1); + $finish; + end + endcase + + case (RX_SLIDE_MODE_0) + "PCS" : RX_SLIDE_MODE_0_BINARY = 1'b0; + "PMA" : RX_SLIDE_MODE_0_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute RX_SLIDE_MODE_0 on GTP_DUAL instance %m is set to %s. Legal values for this attribute are PCS or PMA.", RX_SLIDE_MODE_0); + $finish; + end + endcase + + case (RX_SLIDE_MODE_1) + "PCS" : RX_SLIDE_MODE_1_BINARY = 1'b0; + "PMA" : RX_SLIDE_MODE_1_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute RX_SLIDE_MODE_1 on GTP_DUAL instance %m is set to %s. Legal values for this attribute are PCS or PMA.", RX_SLIDE_MODE_1); + $finish; + end + endcase + + case (SATA_MIN_BURST_0) + 1 : SATA_MIN_BURST_0_BINARY = 6'b000001; + 2 : SATA_MIN_BURST_0_BINARY = 6'b000010; + 3 : SATA_MIN_BURST_0_BINARY = 6'b000011; + 4 : SATA_MIN_BURST_0_BINARY = 6'b000100; + 5 : SATA_MIN_BURST_0_BINARY = 6'b000101; + 6 : SATA_MIN_BURST_0_BINARY = 6'b000110; + 7 : SATA_MIN_BURST_0_BINARY = 6'b000111; + 8 : SATA_MIN_BURST_0_BINARY = 6'b001000; + 9 : SATA_MIN_BURST_0_BINARY = 6'b001001; + 10 : SATA_MIN_BURST_0_BINARY = 6'b001010; + 11 : SATA_MIN_BURST_0_BINARY = 6'b001011; + 12 : SATA_MIN_BURST_0_BINARY = 6'b001100; + 13 : SATA_MIN_BURST_0_BINARY = 6'b001101; + 14 : SATA_MIN_BURST_0_BINARY = 6'b001110; + 15 : SATA_MIN_BURST_0_BINARY = 6'b001111; + 16 : SATA_MIN_BURST_0_BINARY = 6'b010000; + 17 : SATA_MIN_BURST_0_BINARY = 6'b010001; + 18 : SATA_MIN_BURST_0_BINARY = 6'b010010; + 19 : SATA_MIN_BURST_0_BINARY = 6'b010011; + 20 : SATA_MIN_BURST_0_BINARY = 6'b010100; + 21 : SATA_MIN_BURST_0_BINARY = 6'b010101; + 22 : SATA_MIN_BURST_0_BINARY = 6'b010110; + 23 : SATA_MIN_BURST_0_BINARY = 6'b010111; + 24 : SATA_MIN_BURST_0_BINARY = 6'b011000; + 25 : SATA_MIN_BURST_0_BINARY = 6'b011001; + 26 : SATA_MIN_BURST_0_BINARY = 6'b011010; + 27 : SATA_MIN_BURST_0_BINARY = 6'b011011; + 28 : SATA_MIN_BURST_0_BINARY = 6'b011100; + 29 : SATA_MIN_BURST_0_BINARY = 6'b011101; + 30 : SATA_MIN_BURST_0_BINARY = 6'b011110; + 31 : SATA_MIN_BURST_0_BINARY = 6'b011111; + 32 : SATA_MIN_BURST_0_BINARY = 6'b100000; + 33 : SATA_MIN_BURST_0_BINARY = 6'b100001; + 34 : SATA_MIN_BURST_0_BINARY = 6'b100010; + 35 : SATA_MIN_BURST_0_BINARY = 6'b100011; + 36 : SATA_MIN_BURST_0_BINARY = 6'b100100; + 37 : SATA_MIN_BURST_0_BINARY = 6'b100101; + 38 : SATA_MIN_BURST_0_BINARY = 6'b100110; + 39 : SATA_MIN_BURST_0_BINARY = 6'b100111; + 40 : SATA_MIN_BURST_0_BINARY = 6'b101000; + 41 : SATA_MIN_BURST_0_BINARY = 6'b101001; + 42 : SATA_MIN_BURST_0_BINARY = 6'b101010; + 43 : SATA_MIN_BURST_0_BINARY = 6'b101011; + 44 : SATA_MIN_BURST_0_BINARY = 6'b101100; + 45 : SATA_MIN_BURST_0_BINARY = 6'b101101; + 46 : SATA_MIN_BURST_0_BINARY = 6'b101110; + 47 : SATA_MIN_BURST_0_BINARY = 6'b101111; + 48 : SATA_MIN_BURST_0_BINARY = 6'b110000; + 49 : SATA_MIN_BURST_0_BINARY = 6'b110001; + 50 : SATA_MIN_BURST_0_BINARY = 6'b110010; + 51 : SATA_MIN_BURST_0_BINARY = 6'b110011; + 52 : SATA_MIN_BURST_0_BINARY = 6'b110100; + 53 : SATA_MIN_BURST_0_BINARY = 6'b110101; + 54 : SATA_MIN_BURST_0_BINARY = 6'b110110; + 55 : SATA_MIN_BURST_0_BINARY = 6'b110111; + 56 : SATA_MIN_BURST_0_BINARY = 6'b111000; + 57 : SATA_MIN_BURST_0_BINARY = 6'b111001; + 58 : SATA_MIN_BURST_0_BINARY = 6'b111010; + 59 : SATA_MIN_BURST_0_BINARY = 6'b111011; + 60 : SATA_MIN_BURST_0_BINARY = 6'b111100; + 61 : SATA_MIN_BURST_0_BINARY = 6'b111101; + default : begin + $display("Attribute Syntax Error : The Attribute SATA_MIN_BURST_0 on GTP_DUAL instance %m is set to %d. Legal values for this attribute are 1 to 61.", SATA_MIN_BURST_0); + $finish; + end + endcase + + case (SATA_MAX_BURST_0) + 1 : SATA_MAX_BURST_0_BINARY = 6'b000001; + 2 : SATA_MAX_BURST_0_BINARY = 6'b000010; + 3 : SATA_MAX_BURST_0_BINARY = 6'b000011; + 4 : SATA_MAX_BURST_0_BINARY = 6'b000100; + 5 : SATA_MAX_BURST_0_BINARY = 6'b000101; + 6 : SATA_MAX_BURST_0_BINARY = 6'b000110; + 7 : SATA_MAX_BURST_0_BINARY = 6'b000111; + 8 : SATA_MAX_BURST_0_BINARY = 6'b001000; + 9 : SATA_MAX_BURST_0_BINARY = 6'b001001; + 10 : SATA_MAX_BURST_0_BINARY = 6'b001010; + 11 : SATA_MAX_BURST_0_BINARY = 6'b001011; + 12 : SATA_MAX_BURST_0_BINARY = 6'b001100; + 13 : SATA_MAX_BURST_0_BINARY = 6'b001101; + 14 : SATA_MAX_BURST_0_BINARY = 6'b001110; + 15 : SATA_MAX_BURST_0_BINARY = 6'b001111; + 16 : SATA_MAX_BURST_0_BINARY = 6'b010000; + 17 : SATA_MAX_BURST_0_BINARY = 6'b010001; + 18 : SATA_MAX_BURST_0_BINARY = 6'b010010; + 19 : SATA_MAX_BURST_0_BINARY = 6'b010011; + 20 : SATA_MAX_BURST_0_BINARY = 6'b010100; + 21 : SATA_MAX_BURST_0_BINARY = 6'b010101; + 22 : SATA_MAX_BURST_0_BINARY = 6'b010110; + 23 : SATA_MAX_BURST_0_BINARY = 6'b010111; + 24 : SATA_MAX_BURST_0_BINARY = 6'b011000; + 25 : SATA_MAX_BURST_0_BINARY = 6'b011001; + 26 : SATA_MAX_BURST_0_BINARY = 6'b011010; + 27 : SATA_MAX_BURST_0_BINARY = 6'b011011; + 28 : SATA_MAX_BURST_0_BINARY = 6'b011100; + 29 : SATA_MAX_BURST_0_BINARY = 6'b011101; + 30 : SATA_MAX_BURST_0_BINARY = 6'b011110; + 31 : SATA_MAX_BURST_0_BINARY = 6'b011111; + 32 : SATA_MAX_BURST_0_BINARY = 6'b100000; + 33 : SATA_MAX_BURST_0_BINARY = 6'b100001; + 34 : SATA_MAX_BURST_0_BINARY = 6'b100010; + 35 : SATA_MAX_BURST_0_BINARY = 6'b100011; + 36 : SATA_MAX_BURST_0_BINARY = 6'b100100; + 37 : SATA_MAX_BURST_0_BINARY = 6'b100101; + 38 : SATA_MAX_BURST_0_BINARY = 6'b100110; + 39 : SATA_MAX_BURST_0_BINARY = 6'b100111; + 40 : SATA_MAX_BURST_0_BINARY = 6'b101000; + 41 : SATA_MAX_BURST_0_BINARY = 6'b101001; + 42 : SATA_MAX_BURST_0_BINARY = 6'b101010; + 43 : SATA_MAX_BURST_0_BINARY = 6'b101011; + 44 : SATA_MAX_BURST_0_BINARY = 6'b101100; + 45 : SATA_MAX_BURST_0_BINARY = 6'b101101; + 46 : SATA_MAX_BURST_0_BINARY = 6'b101110; + 47 : SATA_MAX_BURST_0_BINARY = 6'b101111; + 48 : SATA_MAX_BURST_0_BINARY = 6'b110000; + 49 : SATA_MAX_BURST_0_BINARY = 6'b110001; + 50 : SATA_MAX_BURST_0_BINARY = 6'b110010; + 51 : SATA_MAX_BURST_0_BINARY = 6'b110011; + 52 : SATA_MAX_BURST_0_BINARY = 6'b110100; + 53 : SATA_MAX_BURST_0_BINARY = 6'b110101; + 54 : SATA_MAX_BURST_0_BINARY = 6'b110110; + 55 : SATA_MAX_BURST_0_BINARY = 6'b110111; + 56 : SATA_MAX_BURST_0_BINARY = 6'b111000; + 57 : SATA_MAX_BURST_0_BINARY = 6'b111001; + 58 : SATA_MAX_BURST_0_BINARY = 6'b111010; + 59 : SATA_MAX_BURST_0_BINARY = 6'b111011; + 60 : SATA_MAX_BURST_0_BINARY = 6'b111100; + 61 : SATA_MAX_BURST_0_BINARY = 6'b111101; + default : begin + $display("Attribute Syntax Error : The Attribute SATA_MAX_BURST_0 on GTP_DUAL instance %m is set to %d. Legal values for this attribute are 1 to 61.", SATA_MAX_BURST_0); + $finish; + end + endcase + + case (SATA_MIN_INIT_0) + 1 : SATA_MIN_INIT_0_BINARY = 6'b000001; + 2 : SATA_MIN_INIT_0_BINARY = 6'b000010; + 3 : SATA_MIN_INIT_0_BINARY = 6'b000011; + 4 : SATA_MIN_INIT_0_BINARY = 6'b000100; + 5 : SATA_MIN_INIT_0_BINARY = 6'b000101; + 6 : SATA_MIN_INIT_0_BINARY = 6'b000110; + 7 : SATA_MIN_INIT_0_BINARY = 6'b000111; + 8 : SATA_MIN_INIT_0_BINARY = 6'b001000; + 9 : SATA_MIN_INIT_0_BINARY = 6'b001001; + 10 : SATA_MIN_INIT_0_BINARY = 6'b001010; + 11 : SATA_MIN_INIT_0_BINARY = 6'b001011; + 12 : SATA_MIN_INIT_0_BINARY = 6'b001100; + 13 : SATA_MIN_INIT_0_BINARY = 6'b001101; + 14 : SATA_MIN_INIT_0_BINARY = 6'b001110; + 15 : SATA_MIN_INIT_0_BINARY = 6'b001111; + 16 : SATA_MIN_INIT_0_BINARY = 6'b010000; + 17 : SATA_MIN_INIT_0_BINARY = 6'b010001; + 18 : SATA_MIN_INIT_0_BINARY = 6'b010010; + 19 : SATA_MIN_INIT_0_BINARY = 6'b010011; + 20 : SATA_MIN_INIT_0_BINARY = 6'b010100; + 21 : SATA_MIN_INIT_0_BINARY = 6'b010101; + 22 : SATA_MIN_INIT_0_BINARY = 6'b010110; + 23 : SATA_MIN_INIT_0_BINARY = 6'b010111; + 24 : SATA_MIN_INIT_0_BINARY = 6'b011000; + 25 : SATA_MIN_INIT_0_BINARY = 6'b011001; + 26 : SATA_MIN_INIT_0_BINARY = 6'b011010; + 27 : SATA_MIN_INIT_0_BINARY = 6'b011011; + 28 : SATA_MIN_INIT_0_BINARY = 6'b011100; + 29 : SATA_MIN_INIT_0_BINARY = 6'b011101; + 30 : SATA_MIN_INIT_0_BINARY = 6'b011110; + 31 : SATA_MIN_INIT_0_BINARY = 6'b011111; + 32 : SATA_MIN_INIT_0_BINARY = 6'b100000; + 33 : SATA_MIN_INIT_0_BINARY = 6'b100001; + 34 : SATA_MIN_INIT_0_BINARY = 6'b100010; + 35 : SATA_MIN_INIT_0_BINARY = 6'b100011; + 36 : SATA_MIN_INIT_0_BINARY = 6'b100100; + 37 : SATA_MIN_INIT_0_BINARY = 6'b100101; + 38 : SATA_MIN_INIT_0_BINARY = 6'b100110; + 39 : SATA_MIN_INIT_0_BINARY = 6'b100111; + 40 : SATA_MIN_INIT_0_BINARY = 6'b101000; + 41 : SATA_MIN_INIT_0_BINARY = 6'b101001; + 42 : SATA_MIN_INIT_0_BINARY = 6'b101010; + 43 : SATA_MIN_INIT_0_BINARY = 6'b101011; + 44 : SATA_MIN_INIT_0_BINARY = 6'b101100; + 45 : SATA_MIN_INIT_0_BINARY = 6'b101101; + 46 : SATA_MIN_INIT_0_BINARY = 6'b101110; + 47 : SATA_MIN_INIT_0_BINARY = 6'b101111; + 48 : SATA_MIN_INIT_0_BINARY = 6'b110000; + 49 : SATA_MIN_INIT_0_BINARY = 6'b110001; + 50 : SATA_MIN_INIT_0_BINARY = 6'b110010; + 51 : SATA_MIN_INIT_0_BINARY = 6'b110011; + 52 : SATA_MIN_INIT_0_BINARY = 6'b110100; + 53 : SATA_MIN_INIT_0_BINARY = 6'b110101; + 54 : SATA_MIN_INIT_0_BINARY = 6'b110110; + 55 : SATA_MIN_INIT_0_BINARY = 6'b110111; + 56 : SATA_MIN_INIT_0_BINARY = 6'b111000; + 57 : SATA_MIN_INIT_0_BINARY = 6'b111001; + 58 : SATA_MIN_INIT_0_BINARY = 6'b111010; + 59 : SATA_MIN_INIT_0_BINARY = 6'b111011; + 60 : SATA_MIN_INIT_0_BINARY = 6'b111100; + 61 : SATA_MIN_INIT_0_BINARY = 6'b111101; + default : begin + $display("Attribute Syntax Error : The Attribute SATA_MIN_INIT_0 on GTP_DUAL instance %m is set to %d. Legal values for this attribute are 1 to 61.", SATA_MIN_INIT_0); + $finish; + end + endcase + + case (SATA_MAX_INIT_0) + 1 : SATA_MAX_INIT_0_BINARY = 6'b000001; + 2 : SATA_MAX_INIT_0_BINARY = 6'b000010; + 3 : SATA_MAX_INIT_0_BINARY = 6'b000011; + 4 : SATA_MAX_INIT_0_BINARY = 6'b000100; + 5 : SATA_MAX_INIT_0_BINARY = 6'b000101; + 6 : SATA_MAX_INIT_0_BINARY = 6'b000110; + 7 : SATA_MAX_INIT_0_BINARY = 6'b000111; + 8 : SATA_MAX_INIT_0_BINARY = 6'b001000; + 9 : SATA_MAX_INIT_0_BINARY = 6'b001001; + 10 : SATA_MAX_INIT_0_BINARY = 6'b001010; + 11 : SATA_MAX_INIT_0_BINARY = 6'b001011; + 12 : SATA_MAX_INIT_0_BINARY = 6'b001100; + 13 : SATA_MAX_INIT_0_BINARY = 6'b001101; + 14 : SATA_MAX_INIT_0_BINARY = 6'b001110; + 15 : SATA_MAX_INIT_0_BINARY = 6'b001111; + 16 : SATA_MAX_INIT_0_BINARY = 6'b010000; + 17 : SATA_MAX_INIT_0_BINARY = 6'b010001; + 18 : SATA_MAX_INIT_0_BINARY = 6'b010010; + 19 : SATA_MAX_INIT_0_BINARY = 6'b010011; + 20 : SATA_MAX_INIT_0_BINARY = 6'b010100; + 21 : SATA_MAX_INIT_0_BINARY = 6'b010101; + 22 : SATA_MAX_INIT_0_BINARY = 6'b010110; + 23 : SATA_MAX_INIT_0_BINARY = 6'b010111; + 24 : SATA_MAX_INIT_0_BINARY = 6'b011000; + 25 : SATA_MAX_INIT_0_BINARY = 6'b011001; + 26 : SATA_MAX_INIT_0_BINARY = 6'b011010; + 27 : SATA_MAX_INIT_0_BINARY = 6'b011011; + 28 : SATA_MAX_INIT_0_BINARY = 6'b011100; + 29 : SATA_MAX_INIT_0_BINARY = 6'b011101; + 30 : SATA_MAX_INIT_0_BINARY = 6'b011110; + 31 : SATA_MAX_INIT_0_BINARY = 6'b011111; + 32 : SATA_MAX_INIT_0_BINARY = 6'b100000; + 33 : SATA_MAX_INIT_0_BINARY = 6'b100001; + 34 : SATA_MAX_INIT_0_BINARY = 6'b100010; + 35 : SATA_MAX_INIT_0_BINARY = 6'b100011; + 36 : SATA_MAX_INIT_0_BINARY = 6'b100100; + 37 : SATA_MAX_INIT_0_BINARY = 6'b100101; + 38 : SATA_MAX_INIT_0_BINARY = 6'b100110; + 39 : SATA_MAX_INIT_0_BINARY = 6'b100111; + 40 : SATA_MAX_INIT_0_BINARY = 6'b101000; + 41 : SATA_MAX_INIT_0_BINARY = 6'b101001; + 42 : SATA_MAX_INIT_0_BINARY = 6'b101010; + 43 : SATA_MAX_INIT_0_BINARY = 6'b101011; + 44 : SATA_MAX_INIT_0_BINARY = 6'b101100; + 45 : SATA_MAX_INIT_0_BINARY = 6'b101101; + 46 : SATA_MAX_INIT_0_BINARY = 6'b101110; + 47 : SATA_MAX_INIT_0_BINARY = 6'b101111; + 48 : SATA_MAX_INIT_0_BINARY = 6'b110000; + 49 : SATA_MAX_INIT_0_BINARY = 6'b110001; + 50 : SATA_MAX_INIT_0_BINARY = 6'b110010; + 51 : SATA_MAX_INIT_0_BINARY = 6'b110011; + 52 : SATA_MAX_INIT_0_BINARY = 6'b110100; + 53 : SATA_MAX_INIT_0_BINARY = 6'b110101; + 54 : SATA_MAX_INIT_0_BINARY = 6'b110110; + 55 : SATA_MAX_INIT_0_BINARY = 6'b110111; + 56 : SATA_MAX_INIT_0_BINARY = 6'b111000; + 57 : SATA_MAX_INIT_0_BINARY = 6'b111001; + 58 : SATA_MAX_INIT_0_BINARY = 6'b111010; + 59 : SATA_MAX_INIT_0_BINARY = 6'b111011; + 60 : SATA_MAX_INIT_0_BINARY = 6'b111100; + 61 : SATA_MAX_INIT_0_BINARY = 6'b111101; + default : begin + $display("Attribute Syntax Error : The Attribute SATA_MAX_INIT_0 on GTP_DUAL instance %m is set to %d. Legal values for this attribute are 1 to 61.", SATA_MAX_INIT_0); + $finish; + end + endcase + + case (SATA_MIN_WAKE_0) + 1 : SATA_MIN_WAKE_0_BINARY = 6'b000001; + 2 : SATA_MIN_WAKE_0_BINARY = 6'b000010; + 3 : SATA_MIN_WAKE_0_BINARY = 6'b000011; + 4 : SATA_MIN_WAKE_0_BINARY = 6'b000100; + 5 : SATA_MIN_WAKE_0_BINARY = 6'b000101; + 6 : SATA_MIN_WAKE_0_BINARY = 6'b000110; + 7 : SATA_MIN_WAKE_0_BINARY = 6'b000111; + 8 : SATA_MIN_WAKE_0_BINARY = 6'b001000; + 9 : SATA_MIN_WAKE_0_BINARY = 6'b001001; + 10 : SATA_MIN_WAKE_0_BINARY = 6'b001010; + 11 : SATA_MIN_WAKE_0_BINARY = 6'b001011; + 12 : SATA_MIN_WAKE_0_BINARY = 6'b001100; + 13 : SATA_MIN_WAKE_0_BINARY = 6'b001101; + 14 : SATA_MIN_WAKE_0_BINARY = 6'b001110; + 15 : SATA_MIN_WAKE_0_BINARY = 6'b001111; + 16 : SATA_MIN_WAKE_0_BINARY = 6'b010000; + 17 : SATA_MIN_WAKE_0_BINARY = 6'b010001; + 18 : SATA_MIN_WAKE_0_BINARY = 6'b010010; + 19 : SATA_MIN_WAKE_0_BINARY = 6'b010011; + 20 : SATA_MIN_WAKE_0_BINARY = 6'b010100; + 21 : SATA_MIN_WAKE_0_BINARY = 6'b010101; + 22 : SATA_MIN_WAKE_0_BINARY = 6'b010110; + 23 : SATA_MIN_WAKE_0_BINARY = 6'b010111; + 24 : SATA_MIN_WAKE_0_BINARY = 6'b011000; + 25 : SATA_MIN_WAKE_0_BINARY = 6'b011001; + 26 : SATA_MIN_WAKE_0_BINARY = 6'b011010; + 27 : SATA_MIN_WAKE_0_BINARY = 6'b011011; + 28 : SATA_MIN_WAKE_0_BINARY = 6'b011100; + 29 : SATA_MIN_WAKE_0_BINARY = 6'b011101; + 30 : SATA_MIN_WAKE_0_BINARY = 6'b011110; + 31 : SATA_MIN_WAKE_0_BINARY = 6'b011111; + 32 : SATA_MIN_WAKE_0_BINARY = 6'b100000; + 33 : SATA_MIN_WAKE_0_BINARY = 6'b100001; + 34 : SATA_MIN_WAKE_0_BINARY = 6'b100010; + 35 : SATA_MIN_WAKE_0_BINARY = 6'b100011; + 36 : SATA_MIN_WAKE_0_BINARY = 6'b100100; + 37 : SATA_MIN_WAKE_0_BINARY = 6'b100101; + 38 : SATA_MIN_WAKE_0_BINARY = 6'b100110; + 39 : SATA_MIN_WAKE_0_BINARY = 6'b100111; + 40 : SATA_MIN_WAKE_0_BINARY = 6'b101000; + 41 : SATA_MIN_WAKE_0_BINARY = 6'b101001; + 42 : SATA_MIN_WAKE_0_BINARY = 6'b101010; + 43 : SATA_MIN_WAKE_0_BINARY = 6'b101011; + 44 : SATA_MIN_WAKE_0_BINARY = 6'b101100; + 45 : SATA_MIN_WAKE_0_BINARY = 6'b101101; + 46 : SATA_MIN_WAKE_0_BINARY = 6'b101110; + 47 : SATA_MIN_WAKE_0_BINARY = 6'b101111; + 48 : SATA_MIN_WAKE_0_BINARY = 6'b110000; + 49 : SATA_MIN_WAKE_0_BINARY = 6'b110001; + 50 : SATA_MIN_WAKE_0_BINARY = 6'b110010; + 51 : SATA_MIN_WAKE_0_BINARY = 6'b110011; + 52 : SATA_MIN_WAKE_0_BINARY = 6'b110100; + 53 : SATA_MIN_WAKE_0_BINARY = 6'b110101; + 54 : SATA_MIN_WAKE_0_BINARY = 6'b110110; + 55 : SATA_MIN_WAKE_0_BINARY = 6'b110111; + 56 : SATA_MIN_WAKE_0_BINARY = 6'b111000; + 57 : SATA_MIN_WAKE_0_BINARY = 6'b111001; + 58 : SATA_MIN_WAKE_0_BINARY = 6'b111010; + 59 : SATA_MIN_WAKE_0_BINARY = 6'b111011; + 60 : SATA_MIN_WAKE_0_BINARY = 6'b111100; + 61 : SATA_MIN_WAKE_0_BINARY = 6'b111101; + default : begin + $display("Attribute Syntax Error : The Attribute SATA_MIN_WAKE_0 on GTP_DUAL instance %m is set to %d. Legal values for this attribute are 1 to 61.", SATA_MIN_WAKE_0); + $finish; + end + endcase + + case (SATA_MAX_WAKE_0) + 1 : SATA_MAX_WAKE_0_BINARY = 6'b000001; + 2 : SATA_MAX_WAKE_0_BINARY = 6'b000010; + 3 : SATA_MAX_WAKE_0_BINARY = 6'b000011; + 4 : SATA_MAX_WAKE_0_BINARY = 6'b000100; + 5 : SATA_MAX_WAKE_0_BINARY = 6'b000101; + 6 : SATA_MAX_WAKE_0_BINARY = 6'b000110; + 7 : SATA_MAX_WAKE_0_BINARY = 6'b000111; + 8 : SATA_MAX_WAKE_0_BINARY = 6'b001000; + 9 : SATA_MAX_WAKE_0_BINARY = 6'b001001; + 10 : SATA_MAX_WAKE_0_BINARY = 6'b001010; + 11 : SATA_MAX_WAKE_0_BINARY = 6'b001011; + 12 : SATA_MAX_WAKE_0_BINARY = 6'b001100; + 13 : SATA_MAX_WAKE_0_BINARY = 6'b001101; + 14 : SATA_MAX_WAKE_0_BINARY = 6'b001110; + 15 : SATA_MAX_WAKE_0_BINARY = 6'b001111; + 16 : SATA_MAX_WAKE_0_BINARY = 6'b010000; + 17 : SATA_MAX_WAKE_0_BINARY = 6'b010001; + 18 : SATA_MAX_WAKE_0_BINARY = 6'b010010; + 19 : SATA_MAX_WAKE_0_BINARY = 6'b010011; + 20 : SATA_MAX_WAKE_0_BINARY = 6'b010100; + 21 : SATA_MAX_WAKE_0_BINARY = 6'b010101; + 22 : SATA_MAX_WAKE_0_BINARY = 6'b010110; + 23 : SATA_MAX_WAKE_0_BINARY = 6'b010111; + 24 : SATA_MAX_WAKE_0_BINARY = 6'b011000; + 25 : SATA_MAX_WAKE_0_BINARY = 6'b011001; + 26 : SATA_MAX_WAKE_0_BINARY = 6'b011010; + 27 : SATA_MAX_WAKE_0_BINARY = 6'b011011; + 28 : SATA_MAX_WAKE_0_BINARY = 6'b011100; + 29 : SATA_MAX_WAKE_0_BINARY = 6'b011101; + 30 : SATA_MAX_WAKE_0_BINARY = 6'b011110; + 31 : SATA_MAX_WAKE_0_BINARY = 6'b011111; + 32 : SATA_MAX_WAKE_0_BINARY = 6'b100000; + 33 : SATA_MAX_WAKE_0_BINARY = 6'b100001; + 34 : SATA_MAX_WAKE_0_BINARY = 6'b100010; + 35 : SATA_MAX_WAKE_0_BINARY = 6'b100011; + 36 : SATA_MAX_WAKE_0_BINARY = 6'b100100; + 37 : SATA_MAX_WAKE_0_BINARY = 6'b100101; + 38 : SATA_MAX_WAKE_0_BINARY = 6'b100110; + 39 : SATA_MAX_WAKE_0_BINARY = 6'b100111; + 40 : SATA_MAX_WAKE_0_BINARY = 6'b101000; + 41 : SATA_MAX_WAKE_0_BINARY = 6'b101001; + 42 : SATA_MAX_WAKE_0_BINARY = 6'b101010; + 43 : SATA_MAX_WAKE_0_BINARY = 6'b101011; + 44 : SATA_MAX_WAKE_0_BINARY = 6'b101100; + 45 : SATA_MAX_WAKE_0_BINARY = 6'b101101; + 46 : SATA_MAX_WAKE_0_BINARY = 6'b101110; + 47 : SATA_MAX_WAKE_0_BINARY = 6'b101111; + 48 : SATA_MAX_WAKE_0_BINARY = 6'b110000; + 49 : SATA_MAX_WAKE_0_BINARY = 6'b110001; + 50 : SATA_MAX_WAKE_0_BINARY = 6'b110010; + 51 : SATA_MAX_WAKE_0_BINARY = 6'b110011; + 52 : SATA_MAX_WAKE_0_BINARY = 6'b110100; + 53 : SATA_MAX_WAKE_0_BINARY = 6'b110101; + 54 : SATA_MAX_WAKE_0_BINARY = 6'b110110; + 55 : SATA_MAX_WAKE_0_BINARY = 6'b110111; + 56 : SATA_MAX_WAKE_0_BINARY = 6'b111000; + 57 : SATA_MAX_WAKE_0_BINARY = 6'b111001; + 58 : SATA_MAX_WAKE_0_BINARY = 6'b111010; + 59 : SATA_MAX_WAKE_0_BINARY = 6'b111011; + 60 : SATA_MAX_WAKE_0_BINARY = 6'b111100; + 61 : SATA_MAX_WAKE_0_BINARY = 6'b111101; + default : begin + $display("Attribute Syntax Error : The Attribute SATA_MAX_WAKE_0 on GTP_DUAL instance %m is set to %d. Legal values for this attribute are 1 to 61.", SATA_MAX_WAKE_0); + $finish; + end + endcase + + case (SATA_MIN_BURST_1) + 1 : SATA_MIN_BURST_1_BINARY = 6'b000001; + 2 : SATA_MIN_BURST_1_BINARY = 6'b000010; + 3 : SATA_MIN_BURST_1_BINARY = 6'b000011; + 4 : SATA_MIN_BURST_1_BINARY = 6'b000100; + 5 : SATA_MIN_BURST_1_BINARY = 6'b000101; + 6 : SATA_MIN_BURST_1_BINARY = 6'b000110; + 7 : SATA_MIN_BURST_1_BINARY = 6'b000111; + 8 : SATA_MIN_BURST_1_BINARY = 6'b001000; + 9 : SATA_MIN_BURST_1_BINARY = 6'b001001; + 10 : SATA_MIN_BURST_1_BINARY = 6'b001010; + 11 : SATA_MIN_BURST_1_BINARY = 6'b001011; + 12 : SATA_MIN_BURST_1_BINARY = 6'b001100; + 13 : SATA_MIN_BURST_1_BINARY = 6'b001101; + 14 : SATA_MIN_BURST_1_BINARY = 6'b001110; + 15 : SATA_MIN_BURST_1_BINARY = 6'b001111; + 16 : SATA_MIN_BURST_1_BINARY = 6'b010000; + 17 : SATA_MIN_BURST_1_BINARY = 6'b010001; + 18 : SATA_MIN_BURST_1_BINARY = 6'b010010; + 19 : SATA_MIN_BURST_1_BINARY = 6'b010011; + 20 : SATA_MIN_BURST_1_BINARY = 6'b010100; + 21 : SATA_MIN_BURST_1_BINARY = 6'b010101; + 22 : SATA_MIN_BURST_1_BINARY = 6'b010110; + 23 : SATA_MIN_BURST_1_BINARY = 6'b010111; + 24 : SATA_MIN_BURST_1_BINARY = 6'b011000; + 25 : SATA_MIN_BURST_1_BINARY = 6'b011001; + 26 : SATA_MIN_BURST_1_BINARY = 6'b011010; + 27 : SATA_MIN_BURST_1_BINARY = 6'b011011; + 28 : SATA_MIN_BURST_1_BINARY = 6'b011100; + 29 : SATA_MIN_BURST_1_BINARY = 6'b011101; + 30 : SATA_MIN_BURST_1_BINARY = 6'b011110; + 31 : SATA_MIN_BURST_1_BINARY = 6'b011111; + 32 : SATA_MIN_BURST_1_BINARY = 6'b100000; + 33 : SATA_MIN_BURST_1_BINARY = 6'b100001; + 34 : SATA_MIN_BURST_1_BINARY = 6'b100010; + 35 : SATA_MIN_BURST_1_BINARY = 6'b100011; + 36 : SATA_MIN_BURST_1_BINARY = 6'b100100; + 37 : SATA_MIN_BURST_1_BINARY = 6'b100101; + 38 : SATA_MIN_BURST_1_BINARY = 6'b100110; + 39 : SATA_MIN_BURST_1_BINARY = 6'b100111; + 40 : SATA_MIN_BURST_1_BINARY = 6'b101000; + 41 : SATA_MIN_BURST_1_BINARY = 6'b101001; + 42 : SATA_MIN_BURST_1_BINARY = 6'b101010; + 43 : SATA_MIN_BURST_1_BINARY = 6'b101011; + 44 : SATA_MIN_BURST_1_BINARY = 6'b101100; + 45 : SATA_MIN_BURST_1_BINARY = 6'b101101; + 46 : SATA_MIN_BURST_1_BINARY = 6'b101110; + 47 : SATA_MIN_BURST_1_BINARY = 6'b101111; + 48 : SATA_MIN_BURST_1_BINARY = 6'b110000; + 49 : SATA_MIN_BURST_1_BINARY = 6'b110001; + 50 : SATA_MIN_BURST_1_BINARY = 6'b110010; + 51 : SATA_MIN_BURST_1_BINARY = 6'b110011; + 52 : SATA_MIN_BURST_1_BINARY = 6'b110100; + 53 : SATA_MIN_BURST_1_BINARY = 6'b110101; + 54 : SATA_MIN_BURST_1_BINARY = 6'b110110; + 55 : SATA_MIN_BURST_1_BINARY = 6'b110111; + 56 : SATA_MIN_BURST_1_BINARY = 6'b111000; + 57 : SATA_MIN_BURST_1_BINARY = 6'b111001; + 58 : SATA_MIN_BURST_1_BINARY = 6'b111010; + 59 : SATA_MIN_BURST_1_BINARY = 6'b111011; + 60 : SATA_MIN_BURST_1_BINARY = 6'b111100; + 61 : SATA_MIN_BURST_1_BINARY = 6'b111101; + default : begin + $display("Attribute Syntax Error : The Attribute SATA_MIN_BURST_1 on GTP_DUAL instance %m is set to %d. Legal values for this attribute are 1 to 61.", SATA_MIN_BURST_1); + $finish; + end + endcase + + case (SATA_MAX_BURST_1) + 1 : SATA_MAX_BURST_1_BINARY = 6'b000001; + 2 : SATA_MAX_BURST_1_BINARY = 6'b000010; + 3 : SATA_MAX_BURST_1_BINARY = 6'b000011; + 4 : SATA_MAX_BURST_1_BINARY = 6'b000100; + 5 : SATA_MAX_BURST_1_BINARY = 6'b000101; + 6 : SATA_MAX_BURST_1_BINARY = 6'b000110; + 7 : SATA_MAX_BURST_1_BINARY = 6'b000111; + 8 : SATA_MAX_BURST_1_BINARY = 6'b001000; + 9 : SATA_MAX_BURST_1_BINARY = 6'b001001; + 10 : SATA_MAX_BURST_1_BINARY = 6'b001010; + 11 : SATA_MAX_BURST_1_BINARY = 6'b001011; + 12 : SATA_MAX_BURST_1_BINARY = 6'b001100; + 13 : SATA_MAX_BURST_1_BINARY = 6'b001101; + 14 : SATA_MAX_BURST_1_BINARY = 6'b001110; + 15 : SATA_MAX_BURST_1_BINARY = 6'b001111; + 16 : SATA_MAX_BURST_1_BINARY = 6'b010000; + 17 : SATA_MAX_BURST_1_BINARY = 6'b010001; + 18 : SATA_MAX_BURST_1_BINARY = 6'b010010; + 19 : SATA_MAX_BURST_1_BINARY = 6'b010011; + 20 : SATA_MAX_BURST_1_BINARY = 6'b010100; + 21 : SATA_MAX_BURST_1_BINARY = 6'b010101; + 22 : SATA_MAX_BURST_1_BINARY = 6'b010110; + 23 : SATA_MAX_BURST_1_BINARY = 6'b010111; + 24 : SATA_MAX_BURST_1_BINARY = 6'b011000; + 25 : SATA_MAX_BURST_1_BINARY = 6'b011001; + 26 : SATA_MAX_BURST_1_BINARY = 6'b011010; + 27 : SATA_MAX_BURST_1_BINARY = 6'b011011; + 28 : SATA_MAX_BURST_1_BINARY = 6'b011100; + 29 : SATA_MAX_BURST_1_BINARY = 6'b011101; + 30 : SATA_MAX_BURST_1_BINARY = 6'b011110; + 31 : SATA_MAX_BURST_1_BINARY = 6'b011111; + 32 : SATA_MAX_BURST_1_BINARY = 6'b100000; + 33 : SATA_MAX_BURST_1_BINARY = 6'b100001; + 34 : SATA_MAX_BURST_1_BINARY = 6'b100010; + 35 : SATA_MAX_BURST_1_BINARY = 6'b100011; + 36 : SATA_MAX_BURST_1_BINARY = 6'b100100; + 37 : SATA_MAX_BURST_1_BINARY = 6'b100101; + 38 : SATA_MAX_BURST_1_BINARY = 6'b100110; + 39 : SATA_MAX_BURST_1_BINARY = 6'b100111; + 40 : SATA_MAX_BURST_1_BINARY = 6'b101000; + 41 : SATA_MAX_BURST_1_BINARY = 6'b101001; + 42 : SATA_MAX_BURST_1_BINARY = 6'b101010; + 43 : SATA_MAX_BURST_1_BINARY = 6'b101011; + 44 : SATA_MAX_BURST_1_BINARY = 6'b101100; + 45 : SATA_MAX_BURST_1_BINARY = 6'b101101; + 46 : SATA_MAX_BURST_1_BINARY = 6'b101110; + 47 : SATA_MAX_BURST_1_BINARY = 6'b101111; + 48 : SATA_MAX_BURST_1_BINARY = 6'b110000; + 49 : SATA_MAX_BURST_1_BINARY = 6'b110001; + 50 : SATA_MAX_BURST_1_BINARY = 6'b110010; + 51 : SATA_MAX_BURST_1_BINARY = 6'b110011; + 52 : SATA_MAX_BURST_1_BINARY = 6'b110100; + 53 : SATA_MAX_BURST_1_BINARY = 6'b110101; + 54 : SATA_MAX_BURST_1_BINARY = 6'b110110; + 55 : SATA_MAX_BURST_1_BINARY = 6'b110111; + 56 : SATA_MAX_BURST_1_BINARY = 6'b111000; + 57 : SATA_MAX_BURST_1_BINARY = 6'b111001; + 58 : SATA_MAX_BURST_1_BINARY = 6'b111010; + 59 : SATA_MAX_BURST_1_BINARY = 6'b111011; + 60 : SATA_MAX_BURST_1_BINARY = 6'b111100; + 61 : SATA_MAX_BURST_1_BINARY = 6'b111101; + default : begin + $display("Attribute Syntax Error : The Attribute SATA_MAX_BURST_1 on GTP_DUAL instance %m is set to %d. Legal values for this attribute are 1 to 61.", SATA_MAX_BURST_1); + $finish; + end + endcase + + case (SATA_MIN_INIT_1) + 1 : SATA_MIN_INIT_1_BINARY = 6'b000001; + 2 : SATA_MIN_INIT_1_BINARY = 6'b000010; + 3 : SATA_MIN_INIT_1_BINARY = 6'b000011; + 4 : SATA_MIN_INIT_1_BINARY = 6'b000100; + 5 : SATA_MIN_INIT_1_BINARY = 6'b000101; + 6 : SATA_MIN_INIT_1_BINARY = 6'b000110; + 7 : SATA_MIN_INIT_1_BINARY = 6'b000111; + 8 : SATA_MIN_INIT_1_BINARY = 6'b001000; + 9 : SATA_MIN_INIT_1_BINARY = 6'b001001; + 10 : SATA_MIN_INIT_1_BINARY = 6'b001010; + 11 : SATA_MIN_INIT_1_BINARY = 6'b001011; + 12 : SATA_MIN_INIT_1_BINARY = 6'b001100; + 13 : SATA_MIN_INIT_1_BINARY = 6'b001101; + 14 : SATA_MIN_INIT_1_BINARY = 6'b001110; + 15 : SATA_MIN_INIT_1_BINARY = 6'b001111; + 16 : SATA_MIN_INIT_1_BINARY = 6'b010000; + 17 : SATA_MIN_INIT_1_BINARY = 6'b010001; + 18 : SATA_MIN_INIT_1_BINARY = 6'b010010; + 19 : SATA_MIN_INIT_1_BINARY = 6'b010011; + 20 : SATA_MIN_INIT_1_BINARY = 6'b010100; + 21 : SATA_MIN_INIT_1_BINARY = 6'b010101; + 22 : SATA_MIN_INIT_1_BINARY = 6'b010110; + 23 : SATA_MIN_INIT_1_BINARY = 6'b010111; + 24 : SATA_MIN_INIT_1_BINARY = 6'b011000; + 25 : SATA_MIN_INIT_1_BINARY = 6'b011001; + 26 : SATA_MIN_INIT_1_BINARY = 6'b011010; + 27 : SATA_MIN_INIT_1_BINARY = 6'b011011; + 28 : SATA_MIN_INIT_1_BINARY = 6'b011100; + 29 : SATA_MIN_INIT_1_BINARY = 6'b011101; + 30 : SATA_MIN_INIT_1_BINARY = 6'b011110; + 31 : SATA_MIN_INIT_1_BINARY = 6'b011111; + 32 : SATA_MIN_INIT_1_BINARY = 6'b100000; + 33 : SATA_MIN_INIT_1_BINARY = 6'b100001; + 34 : SATA_MIN_INIT_1_BINARY = 6'b100010; + 35 : SATA_MIN_INIT_1_BINARY = 6'b100011; + 36 : SATA_MIN_INIT_1_BINARY = 6'b100100; + 37 : SATA_MIN_INIT_1_BINARY = 6'b100101; + 38 : SATA_MIN_INIT_1_BINARY = 6'b100110; + 39 : SATA_MIN_INIT_1_BINARY = 6'b100111; + 40 : SATA_MIN_INIT_1_BINARY = 6'b101000; + 41 : SATA_MIN_INIT_1_BINARY = 6'b101001; + 42 : SATA_MIN_INIT_1_BINARY = 6'b101010; + 43 : SATA_MIN_INIT_1_BINARY = 6'b101011; + 44 : SATA_MIN_INIT_1_BINARY = 6'b101100; + 45 : SATA_MIN_INIT_1_BINARY = 6'b101101; + 46 : SATA_MIN_INIT_1_BINARY = 6'b101110; + 47 : SATA_MIN_INIT_1_BINARY = 6'b101111; + 48 : SATA_MIN_INIT_1_BINARY = 6'b110000; + 49 : SATA_MIN_INIT_1_BINARY = 6'b110001; + 50 : SATA_MIN_INIT_1_BINARY = 6'b110010; + 51 : SATA_MIN_INIT_1_BINARY = 6'b110011; + 52 : SATA_MIN_INIT_1_BINARY = 6'b110100; + 53 : SATA_MIN_INIT_1_BINARY = 6'b110101; + 54 : SATA_MIN_INIT_1_BINARY = 6'b110110; + 55 : SATA_MIN_INIT_1_BINARY = 6'b110111; + 56 : SATA_MIN_INIT_1_BINARY = 6'b111000; + 57 : SATA_MIN_INIT_1_BINARY = 6'b111001; + 58 : SATA_MIN_INIT_1_BINARY = 6'b111010; + 59 : SATA_MIN_INIT_1_BINARY = 6'b111011; + 60 : SATA_MIN_INIT_1_BINARY = 6'b111100; + 61 : SATA_MIN_INIT_1_BINARY = 6'b111101; + default : begin + $display("Attribute Syntax Error : The Attribute SATA_MIN_INIT_1 on GTP_DUAL instance %m is set to %d. Legal values for this attribute are 1 to 61.", SATA_MIN_INIT_1); + $finish; + end + endcase + + case (SATA_MAX_INIT_1) + 1 : SATA_MAX_INIT_1_BINARY = 6'b000001; + 2 : SATA_MAX_INIT_1_BINARY = 6'b000010; + 3 : SATA_MAX_INIT_1_BINARY = 6'b000011; + 4 : SATA_MAX_INIT_1_BINARY = 6'b000100; + 5 : SATA_MAX_INIT_1_BINARY = 6'b000101; + 6 : SATA_MAX_INIT_1_BINARY = 6'b000110; + 7 : SATA_MAX_INIT_1_BINARY = 6'b000111; + 8 : SATA_MAX_INIT_1_BINARY = 6'b001000; + 9 : SATA_MAX_INIT_1_BINARY = 6'b001001; + 10 : SATA_MAX_INIT_1_BINARY = 6'b001010; + 11 : SATA_MAX_INIT_1_BINARY = 6'b001011; + 12 : SATA_MAX_INIT_1_BINARY = 6'b001100; + 13 : SATA_MAX_INIT_1_BINARY = 6'b001101; + 14 : SATA_MAX_INIT_1_BINARY = 6'b001110; + 15 : SATA_MAX_INIT_1_BINARY = 6'b001111; + 16 : SATA_MAX_INIT_1_BINARY = 6'b010000; + 17 : SATA_MAX_INIT_1_BINARY = 6'b010001; + 18 : SATA_MAX_INIT_1_BINARY = 6'b010010; + 19 : SATA_MAX_INIT_1_BINARY = 6'b010011; + 20 : SATA_MAX_INIT_1_BINARY = 6'b010100; + 21 : SATA_MAX_INIT_1_BINARY = 6'b010101; + 22 : SATA_MAX_INIT_1_BINARY = 6'b010110; + 23 : SATA_MAX_INIT_1_BINARY = 6'b010111; + 24 : SATA_MAX_INIT_1_BINARY = 6'b011000; + 25 : SATA_MAX_INIT_1_BINARY = 6'b011001; + 26 : SATA_MAX_INIT_1_BINARY = 6'b011010; + 27 : SATA_MAX_INIT_1_BINARY = 6'b011011; + 28 : SATA_MAX_INIT_1_BINARY = 6'b011100; + 29 : SATA_MAX_INIT_1_BINARY = 6'b011101; + 30 : SATA_MAX_INIT_1_BINARY = 6'b011110; + 31 : SATA_MAX_INIT_1_BINARY = 6'b011111; + 32 : SATA_MAX_INIT_1_BINARY = 6'b100000; + 33 : SATA_MAX_INIT_1_BINARY = 6'b100001; + 34 : SATA_MAX_INIT_1_BINARY = 6'b100010; + 35 : SATA_MAX_INIT_1_BINARY = 6'b100011; + 36 : SATA_MAX_INIT_1_BINARY = 6'b100100; + 37 : SATA_MAX_INIT_1_BINARY = 6'b100101; + 38 : SATA_MAX_INIT_1_BINARY = 6'b100110; + 39 : SATA_MAX_INIT_1_BINARY = 6'b100111; + 40 : SATA_MAX_INIT_1_BINARY = 6'b101000; + 41 : SATA_MAX_INIT_1_BINARY = 6'b101001; + 42 : SATA_MAX_INIT_1_BINARY = 6'b101010; + 43 : SATA_MAX_INIT_1_BINARY = 6'b101011; + 44 : SATA_MAX_INIT_1_BINARY = 6'b101100; + 45 : SATA_MAX_INIT_1_BINARY = 6'b101101; + 46 : SATA_MAX_INIT_1_BINARY = 6'b101110; + 47 : SATA_MAX_INIT_1_BINARY = 6'b101111; + 48 : SATA_MAX_INIT_1_BINARY = 6'b110000; + 49 : SATA_MAX_INIT_1_BINARY = 6'b110001; + 50 : SATA_MAX_INIT_1_BINARY = 6'b110010; + 51 : SATA_MAX_INIT_1_BINARY = 6'b110011; + 52 : SATA_MAX_INIT_1_BINARY = 6'b110100; + 53 : SATA_MAX_INIT_1_BINARY = 6'b110101; + 54 : SATA_MAX_INIT_1_BINARY = 6'b110110; + 55 : SATA_MAX_INIT_1_BINARY = 6'b110111; + 56 : SATA_MAX_INIT_1_BINARY = 6'b111000; + 57 : SATA_MAX_INIT_1_BINARY = 6'b111001; + 58 : SATA_MAX_INIT_1_BINARY = 6'b111010; + 59 : SATA_MAX_INIT_1_BINARY = 6'b111011; + 60 : SATA_MAX_INIT_1_BINARY = 6'b111100; + 61 : SATA_MAX_INIT_1_BINARY = 6'b111101; + default : begin + $display("Attribute Syntax Error : The Attribute SATA_MAX_INIT_1 on GTP_DUAL instance %m is set to %d. Legal values for this attribute are 1 to 61.", SATA_MAX_INIT_1); + $finish; + end + endcase + + case (SATA_MIN_WAKE_1) + 1 : SATA_MIN_WAKE_1_BINARY = 6'b000001; + 2 : SATA_MIN_WAKE_1_BINARY = 6'b000010; + 3 : SATA_MIN_WAKE_1_BINARY = 6'b000011; + 4 : SATA_MIN_WAKE_1_BINARY = 6'b000100; + 5 : SATA_MIN_WAKE_1_BINARY = 6'b000101; + 6 : SATA_MIN_WAKE_1_BINARY = 6'b000110; + 7 : SATA_MIN_WAKE_1_BINARY = 6'b000111; + 8 : SATA_MIN_WAKE_1_BINARY = 6'b001000; + 9 : SATA_MIN_WAKE_1_BINARY = 6'b001001; + 10 : SATA_MIN_WAKE_1_BINARY = 6'b001010; + 11 : SATA_MIN_WAKE_1_BINARY = 6'b001011; + 12 : SATA_MIN_WAKE_1_BINARY = 6'b001100; + 13 : SATA_MIN_WAKE_1_BINARY = 6'b001101; + 14 : SATA_MIN_WAKE_1_BINARY = 6'b001110; + 15 : SATA_MIN_WAKE_1_BINARY = 6'b001111; + 16 : SATA_MIN_WAKE_1_BINARY = 6'b010000; + 17 : SATA_MIN_WAKE_1_BINARY = 6'b010001; + 18 : SATA_MIN_WAKE_1_BINARY = 6'b010010; + 19 : SATA_MIN_WAKE_1_BINARY = 6'b010011; + 20 : SATA_MIN_WAKE_1_BINARY = 6'b010100; + 21 : SATA_MIN_WAKE_1_BINARY = 6'b010101; + 22 : SATA_MIN_WAKE_1_BINARY = 6'b010110; + 23 : SATA_MIN_WAKE_1_BINARY = 6'b010111; + 24 : SATA_MIN_WAKE_1_BINARY = 6'b011000; + 25 : SATA_MIN_WAKE_1_BINARY = 6'b011001; + 26 : SATA_MIN_WAKE_1_BINARY = 6'b011010; + 27 : SATA_MIN_WAKE_1_BINARY = 6'b011011; + 28 : SATA_MIN_WAKE_1_BINARY = 6'b011100; + 29 : SATA_MIN_WAKE_1_BINARY = 6'b011101; + 30 : SATA_MIN_WAKE_1_BINARY = 6'b011110; + 31 : SATA_MIN_WAKE_1_BINARY = 6'b011111; + 32 : SATA_MIN_WAKE_1_BINARY = 6'b100000; + 33 : SATA_MIN_WAKE_1_BINARY = 6'b100001; + 34 : SATA_MIN_WAKE_1_BINARY = 6'b100010; + 35 : SATA_MIN_WAKE_1_BINARY = 6'b100011; + 36 : SATA_MIN_WAKE_1_BINARY = 6'b100100; + 37 : SATA_MIN_WAKE_1_BINARY = 6'b100101; + 38 : SATA_MIN_WAKE_1_BINARY = 6'b100110; + 39 : SATA_MIN_WAKE_1_BINARY = 6'b100111; + 40 : SATA_MIN_WAKE_1_BINARY = 6'b101000; + 41 : SATA_MIN_WAKE_1_BINARY = 6'b101001; + 42 : SATA_MIN_WAKE_1_BINARY = 6'b101010; + 43 : SATA_MIN_WAKE_1_BINARY = 6'b101011; + 44 : SATA_MIN_WAKE_1_BINARY = 6'b101100; + 45 : SATA_MIN_WAKE_1_BINARY = 6'b101101; + 46 : SATA_MIN_WAKE_1_BINARY = 6'b101110; + 47 : SATA_MIN_WAKE_1_BINARY = 6'b101111; + 48 : SATA_MIN_WAKE_1_BINARY = 6'b110000; + 49 : SATA_MIN_WAKE_1_BINARY = 6'b110001; + 50 : SATA_MIN_WAKE_1_BINARY = 6'b110010; + 51 : SATA_MIN_WAKE_1_BINARY = 6'b110011; + 52 : SATA_MIN_WAKE_1_BINARY = 6'b110100; + 53 : SATA_MIN_WAKE_1_BINARY = 6'b110101; + 54 : SATA_MIN_WAKE_1_BINARY = 6'b110110; + 55 : SATA_MIN_WAKE_1_BINARY = 6'b110111; + 56 : SATA_MIN_WAKE_1_BINARY = 6'b111000; + 57 : SATA_MIN_WAKE_1_BINARY = 6'b111001; + 58 : SATA_MIN_WAKE_1_BINARY = 6'b111010; + 59 : SATA_MIN_WAKE_1_BINARY = 6'b111011; + 60 : SATA_MIN_WAKE_1_BINARY = 6'b111100; + 61 : SATA_MIN_WAKE_1_BINARY = 6'b111101; + default : begin + $display("Attribute Syntax Error : The Attribute SATA_MIN_WAKE_1 on GTP_DUAL instance %m is set to %d. Legal values for this attribute are 1 to 61.", SATA_MIN_WAKE_1); + $finish; + end + endcase + + case (SATA_MAX_WAKE_1) + 1 : SATA_MAX_WAKE_1_BINARY = 6'b000001; + 2 : SATA_MAX_WAKE_1_BINARY = 6'b000010; + 3 : SATA_MAX_WAKE_1_BINARY = 6'b000011; + 4 : SATA_MAX_WAKE_1_BINARY = 6'b000100; + 5 : SATA_MAX_WAKE_1_BINARY = 6'b000101; + 6 : SATA_MAX_WAKE_1_BINARY = 6'b000110; + 7 : SATA_MAX_WAKE_1_BINARY = 6'b000111; + 8 : SATA_MAX_WAKE_1_BINARY = 6'b001000; + 9 : SATA_MAX_WAKE_1_BINARY = 6'b001001; + 10 : SATA_MAX_WAKE_1_BINARY = 6'b001010; + 11 : SATA_MAX_WAKE_1_BINARY = 6'b001011; + 12 : SATA_MAX_WAKE_1_BINARY = 6'b001100; + 13 : SATA_MAX_WAKE_1_BINARY = 6'b001101; + 14 : SATA_MAX_WAKE_1_BINARY = 6'b001110; + 15 : SATA_MAX_WAKE_1_BINARY = 6'b001111; + 16 : SATA_MAX_WAKE_1_BINARY = 6'b010000; + 17 : SATA_MAX_WAKE_1_BINARY = 6'b010001; + 18 : SATA_MAX_WAKE_1_BINARY = 6'b010010; + 19 : SATA_MAX_WAKE_1_BINARY = 6'b010011; + 20 : SATA_MAX_WAKE_1_BINARY = 6'b010100; + 21 : SATA_MAX_WAKE_1_BINARY = 6'b010101; + 22 : SATA_MAX_WAKE_1_BINARY = 6'b010110; + 23 : SATA_MAX_WAKE_1_BINARY = 6'b010111; + 24 : SATA_MAX_WAKE_1_BINARY = 6'b011000; + 25 : SATA_MAX_WAKE_1_BINARY = 6'b011001; + 26 : SATA_MAX_WAKE_1_BINARY = 6'b011010; + 27 : SATA_MAX_WAKE_1_BINARY = 6'b011011; + 28 : SATA_MAX_WAKE_1_BINARY = 6'b011100; + 29 : SATA_MAX_WAKE_1_BINARY = 6'b011101; + 30 : SATA_MAX_WAKE_1_BINARY = 6'b011110; + 31 : SATA_MAX_WAKE_1_BINARY = 6'b011111; + 32 : SATA_MAX_WAKE_1_BINARY = 6'b100000; + 33 : SATA_MAX_WAKE_1_BINARY = 6'b100001; + 34 : SATA_MAX_WAKE_1_BINARY = 6'b100010; + 35 : SATA_MAX_WAKE_1_BINARY = 6'b100011; + 36 : SATA_MAX_WAKE_1_BINARY = 6'b100100; + 37 : SATA_MAX_WAKE_1_BINARY = 6'b100101; + 38 : SATA_MAX_WAKE_1_BINARY = 6'b100110; + 39 : SATA_MAX_WAKE_1_BINARY = 6'b100111; + 40 : SATA_MAX_WAKE_1_BINARY = 6'b101000; + 41 : SATA_MAX_WAKE_1_BINARY = 6'b101001; + 42 : SATA_MAX_WAKE_1_BINARY = 6'b101010; + 43 : SATA_MAX_WAKE_1_BINARY = 6'b101011; + 44 : SATA_MAX_WAKE_1_BINARY = 6'b101100; + 45 : SATA_MAX_WAKE_1_BINARY = 6'b101101; + 46 : SATA_MAX_WAKE_1_BINARY = 6'b101110; + 47 : SATA_MAX_WAKE_1_BINARY = 6'b101111; + 48 : SATA_MAX_WAKE_1_BINARY = 6'b110000; + 49 : SATA_MAX_WAKE_1_BINARY = 6'b110001; + 50 : SATA_MAX_WAKE_1_BINARY = 6'b110010; + 51 : SATA_MAX_WAKE_1_BINARY = 6'b110011; + 52 : SATA_MAX_WAKE_1_BINARY = 6'b110100; + 53 : SATA_MAX_WAKE_1_BINARY = 6'b110101; + 54 : SATA_MAX_WAKE_1_BINARY = 6'b110110; + 55 : SATA_MAX_WAKE_1_BINARY = 6'b110111; + 56 : SATA_MAX_WAKE_1_BINARY = 6'b111000; + 57 : SATA_MAX_WAKE_1_BINARY = 6'b111001; + 58 : SATA_MAX_WAKE_1_BINARY = 6'b111010; + 59 : SATA_MAX_WAKE_1_BINARY = 6'b111011; + 60 : SATA_MAX_WAKE_1_BINARY = 6'b111100; + 61 : SATA_MAX_WAKE_1_BINARY = 6'b111101; + default : begin + $display("Attribute Syntax Error : The Attribute SATA_MAX_WAKE_1 on GTP_DUAL instance %m is set to %d. Legal values for this attribute are 1 to 61.", SATA_MAX_WAKE_1); + $finish; + end + endcase + + case (CLK25_DIVIDER) + 1 : CLK25_DIVIDER_BINARY = 3'b000; + 2 : CLK25_DIVIDER_BINARY = 3'b001; + 3 : CLK25_DIVIDER_BINARY = 3'b010; + 4 : CLK25_DIVIDER_BINARY = 3'b011; + 5 : CLK25_DIVIDER_BINARY = 3'b100; + 6 : CLK25_DIVIDER_BINARY = 3'b101; + 10 : CLK25_DIVIDER_BINARY = 3'b110; + 12 : CLK25_DIVIDER_BINARY = 3'b111; + default : begin + $display("Attribute Syntax Error : The Attribute CLK25_DIVIDER on GTP_DUAL instance %m is set to %d. Legal values for this attribute are 1, 2, 3, 4, 5, 6, 10 or 12.", CLK25_DIVIDER); + $finish; + end + endcase + + case (OVERSAMPLE_MODE) + "FALSE" : OVERSAMPLE_MODE_BINARY = 1'b0; + "TRUE" : OVERSAMPLE_MODE_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute OVERSAMPLE_MODE on GTP_DUAL instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", OVERSAMPLE_MODE); + $finish; + end + endcase + + case (SIM_GTPRESET_SPEEDUP) + 0 : SIM_GTPRESET_SPEEDUP_BINARY = 0; + 1 : SIM_GTPRESET_SPEEDUP_BINARY = 1; + default : begin + $display("Attribute Syntax Error : The Attribute SIM_GTPRESET_SPEEDUP on GTP_DUAL instance %m is set to %d. Legal values for this attribute are 0 or 1.", SIM_GTPRESET_SPEEDUP); + $finish; + end + endcase + + case (SIM_MODE) + "FAST" : SIM_MODE_BINARY = 1'b1; + "LEGACY" : begin + $display("Attribute Syntax Warning : The Attribute SIM_MODE on GTX_DUAL instance %m is set to %s. The Legacy model is not supported from ISE 11.1 onwards. GTX_DUAL defaults to FAST model. There are no functionality differences between GTX_DUAL LEGACY and GTX_DUAL FAST simulation models. Although, if you want to use the GTX_DUAL LEGACY model, please use an earlier ISE build", SIM_MODE); + //$finish; + end + default : begin + $display("Attribute Syntax Warning : The Attribute SIM_MODE on GTP_DUAL instance %m is set to %s. Legal value for this attribute is FAST.", SIM_MODE); + //$finish; + end + endcase + + case (SIM_RECEIVER_DETECT_PASS0) + "FALSE" : SIM_RECEIVER_DETECT_PASS0_BINARY = 1'b0; + "TRUE" : SIM_RECEIVER_DETECT_PASS0_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute SIM_RECEIVER_DETECT_PASS0 on GTP_DUAL instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", SIM_RECEIVER_DETECT_PASS0); + $finish; + end + endcase + + case (SIM_RECEIVER_DETECT_PASS1) + "FALSE" : SIM_RECEIVER_DETECT_PASS1_BINARY = 1'b0; + "TRUE" : SIM_RECEIVER_DETECT_PASS1_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute SIM_RECEIVER_DETECT_PASS1 on GTP_DUAL instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", SIM_RECEIVER_DETECT_PASS1); + $finish; + end + endcase + +end + +wire DRDY_delay; +wire PHYSTATUS0_delay; +wire PHYSTATUS1_delay; +wire PLLLKDET_delay; +wire REFCLKOUT_delay; +wire RESETDONE0_delay; +wire RESETDONE1_delay; +wire RXBYTEISALIGNED0_delay; +wire RXBYTEISALIGNED1_delay; +wire RXBYTEREALIGN0_delay; +wire RXBYTEREALIGN1_delay; +wire RXCHANBONDSEQ0_delay; +wire RXCHANBONDSEQ1_delay; +wire RXCHANISALIGNED0_delay; +wire RXCHANISALIGNED1_delay; +wire RXCHANREALIGN0_delay; +wire RXCHANREALIGN1_delay; +wire RXCOMMADET0_delay; +wire RXCOMMADET1_delay; +wire RXELECIDLE0_delay; +wire RXELECIDLE1_delay; +wire RXOVERSAMPLEERR0_delay; +wire RXOVERSAMPLEERR1_delay; +wire RXPRBSERR0_delay; +wire RXPRBSERR1_delay; +wire RXRECCLK0_delay; +wire RXRECCLK1_delay; +wire RXVALID0_delay; +wire RXVALID1_delay; +wire TXN0_delay; +wire TXN1_delay; +wire TXOUTCLK0_delay; +wire TXOUTCLK1_delay; +wire TXP0_delay; +wire TXP1_delay; +wire [15:0] DO_delay; +wire [15:0] RXDATA0_delay; +wire [15:0] RXDATA1_delay; +wire [1:0] RXCHARISCOMMA0_delay; +wire [1:0] RXCHARISCOMMA1_delay; +wire [1:0] RXCHARISK0_delay; +wire [1:0] RXCHARISK1_delay; +wire [1:0] RXDISPERR0_delay; +wire [1:0] RXDISPERR1_delay; +wire [1:0] RXLOSSOFSYNC0_delay; +wire [1:0] RXLOSSOFSYNC1_delay; +wire [1:0] RXNOTINTABLE0_delay; +wire [1:0] RXNOTINTABLE1_delay; +wire [1:0] RXRUNDISP0_delay; +wire [1:0] RXRUNDISP1_delay; +wire [1:0] TXBUFSTATUS0_delay; +wire [1:0] TXBUFSTATUS1_delay; +wire [1:0] TXKERR0_delay; +wire [1:0] TXKERR1_delay; +wire [1:0] TXRUNDISP0_delay; +wire [1:0] TXRUNDISP1_delay; +wire [2:0] RXBUFSTATUS0_delay; +wire [2:0] RXBUFSTATUS1_delay; +wire [2:0] RXCHBONDO0_delay; +wire [2:0] RXCHBONDO1_delay; +wire [2:0] RXCLKCORCNT0_delay; +wire [2:0] RXCLKCORCNT1_delay; +wire [2:0] RXSTATUS0_delay; +wire [2:0] RXSTATUS1_delay; + +wire CLKIN_delay; +wire DCLK_delay; +wire DEN_delay; +wire DWE_delay; +wire GTPRESET_delay; +wire INTDATAWIDTH_delay; +wire PLLLKDETEN_delay; +wire PLLPOWERDOWN_delay; +wire PRBSCNTRESET0_delay; +wire PRBSCNTRESET1_delay; +wire REFCLKPWRDNB_delay; +wire RXBUFRESET0_delay; +wire RXBUFRESET1_delay; +wire RXCDRRESET0_delay; +wire RXCDRRESET1_delay; +wire RXCOMMADETUSE0_delay; +wire RXCOMMADETUSE1_delay; +wire RXDATAWIDTH0_delay; +wire RXDATAWIDTH1_delay; +wire RXDEC8B10BUSE0_delay; +wire RXDEC8B10BUSE1_delay; +wire RXELECIDLERESET0_delay; +wire RXELECIDLERESET1_delay; +wire RXENCHANSYNC0_delay; +wire RXENCHANSYNC1_delay; +wire RXENELECIDLERESETB_delay; +wire RXENEQB0_delay; +wire RXENEQB1_delay; +wire RXENMCOMMAALIGN0_delay; +wire RXENMCOMMAALIGN1_delay; +wire RXENPCOMMAALIGN0_delay; +wire RXENPCOMMAALIGN1_delay; +wire RXENSAMPLEALIGN0_delay; +wire RXENSAMPLEALIGN1_delay; +wire RXN0_delay; +wire RXN1_delay; +wire RXP0_delay; +wire RXP1_delay; +wire RXPMASETPHASE0_delay; +wire RXPMASETPHASE1_delay; +wire RXPOLARITY0_delay; +wire RXPOLARITY1_delay; +wire RXRESET0_delay; +wire RXRESET1_delay; +wire RXSLIDE0_delay; +wire RXSLIDE1_delay; +wire RXUSRCLK0_delay; +wire RXUSRCLK1_delay; +wire RXUSRCLK20_delay; +wire RXUSRCLK21_delay; +wire TXCOMSTART0_delay; +wire TXCOMSTART1_delay; +wire TXCOMTYPE0_delay; +wire TXCOMTYPE1_delay; +wire TXDATAWIDTH0_delay; +wire TXDATAWIDTH1_delay; +wire TXDETECTRX0_delay; +wire TXDETECTRX1_delay; +wire TXELECIDLE0_delay; +wire TXELECIDLE1_delay; +wire TXENC8B10BUSE0_delay; +wire TXENC8B10BUSE1_delay; +wire TXENPMAPHASEALIGN_delay; +wire TXINHIBIT0_delay; +wire TXINHIBIT1_delay; +wire TXPMASETPHASE_delay; +wire TXPOLARITY0_delay; +wire TXPOLARITY1_delay; +wire TXRESET0_delay; +wire TXRESET1_delay; +wire TXUSRCLK0_delay; +wire TXUSRCLK1_delay; +wire TXUSRCLK20_delay; +wire TXUSRCLK21_delay; +wire [15:0] DI_delay; +wire [15:0] TXDATA0_delay; +wire [15:0] TXDATA1_delay; +wire [1:0] RXENPRBSTST0_delay; +wire [1:0] RXENPRBSTST1_delay; +wire [1:0] RXEQMIX0_delay; +wire [1:0] RXEQMIX1_delay; +wire [1:0] RXPOWERDOWN0_delay; +wire [1:0] RXPOWERDOWN1_delay; +wire [1:0] TXBYPASS8B10B0_delay; +wire [1:0] TXBYPASS8B10B1_delay; +wire [1:0] TXCHARDISPMODE0_delay; +wire [1:0] TXCHARDISPMODE1_delay; +wire [1:0] TXCHARDISPVAL0_delay; +wire [1:0] TXCHARDISPVAL1_delay; +wire [1:0] TXCHARISK0_delay; +wire [1:0] TXCHARISK1_delay; +wire [1:0] TXENPRBSTST0_delay; +wire [1:0] TXENPRBSTST1_delay; +wire [1:0] TXPOWERDOWN0_delay; +wire [1:0] TXPOWERDOWN1_delay; +wire [2:0] LOOPBACK0_delay; +wire [2:0] LOOPBACK1_delay; +wire [2:0] RXCHBONDI0_delay; +wire [2:0] RXCHBONDI1_delay; +wire [2:0] TXBUFDIFFCTRL0_delay; +wire [2:0] TXBUFDIFFCTRL1_delay; +wire [2:0] TXDIFFCTRL0_delay; +wire [2:0] TXDIFFCTRL1_delay; +wire [2:0] TXPREEMPHASIS0_delay; +wire [2:0] TXPREEMPHASIS1_delay; +wire [3:0] GTPTEST_delay; +wire [3:0] RXEQPOLE0_delay; +wire [3:0] RXEQPOLE1_delay; +wire [6:0] DADDR_delay; + +assign #(CLK_DELAY) REFCLKOUT = REFCLKOUT_delay; +assign #(CLK_DELAY) RXCLKCORCNT0 = RXCLKCORCNT0_delay; +assign #(CLK_DELAY) RXCLKCORCNT1 = RXCLKCORCNT1_delay; +assign #(CLK_DELAY) RXRECCLK0 = RXRECCLK0_delay; +assign #(CLK_DELAY) RXRECCLK1 = RXRECCLK1_delay; +assign #(CLK_DELAY) TXOUTCLK0 = TXOUTCLK0_delay; +assign #(CLK_DELAY) TXOUTCLK1 = TXOUTCLK1_delay; + +assign #(out_delay) DO = DO_delay; +assign #(out_delay) DRDY = DRDY_delay; +assign #(out_delay) PHYSTATUS0 = PHYSTATUS0_delay; +assign #(out_delay) PHYSTATUS1 = PHYSTATUS1_delay; +assign #(out_delay) PLLLKDET = PLLLKDET_delay; +assign #(out_delay) RESETDONE0 = RESETDONE0_delay; +assign #(out_delay) RESETDONE1 = RESETDONE1_delay; +assign #(out_delay) RXBUFSTATUS0 = RXBUFSTATUS0_delay; +assign #(out_delay) RXBUFSTATUS1 = RXBUFSTATUS1_delay; +assign #(out_delay) RXBYTEISALIGNED0 = RXBYTEISALIGNED0_delay; +assign #(out_delay) RXBYTEISALIGNED1 = RXBYTEISALIGNED1_delay; +assign #(out_delay) RXBYTEREALIGN0 = RXBYTEREALIGN0_delay; +assign #(out_delay) RXBYTEREALIGN1 = RXBYTEREALIGN1_delay; +assign #(out_delay) RXCHANBONDSEQ0 = RXCHANBONDSEQ0_delay; +assign #(out_delay) RXCHANBONDSEQ1 = RXCHANBONDSEQ1_delay; +assign #(out_delay) RXCHANISALIGNED0 = RXCHANISALIGNED0_delay; +assign #(out_delay) RXCHANISALIGNED1 = RXCHANISALIGNED1_delay; +assign #(out_delay) RXCHANREALIGN0 = RXCHANREALIGN0_delay; +assign #(out_delay) RXCHANREALIGN1 = RXCHANREALIGN1_delay; +assign #(out_delay) RXCHARISCOMMA0 = RXCHARISCOMMA0_delay; +assign #(out_delay) RXCHARISCOMMA1 = RXCHARISCOMMA1_delay; +assign #(out_delay) RXCHARISK0 = RXCHARISK0_delay; +assign #(out_delay) RXCHARISK1 = RXCHARISK1_delay; +assign #(out_delay) RXCHBONDO0 = RXCHBONDO0_delay; +assign #(out_delay) RXCHBONDO1 = RXCHBONDO1_delay; +assign #(out_delay) RXCOMMADET0 = RXCOMMADET0_delay; +assign #(out_delay) RXCOMMADET1 = RXCOMMADET1_delay; +assign #(out_delay) RXDATA0 = RXDATA0_delay; +assign #(out_delay) RXDATA1 = RXDATA1_delay; +assign #(out_delay) RXDISPERR0 = RXDISPERR0_delay; +assign #(out_delay) RXDISPERR1 = RXDISPERR1_delay; +assign #(out_delay) RXELECIDLE0 = RXELECIDLE0_delay; +assign #(out_delay) RXELECIDLE1 = RXELECIDLE1_delay; +assign #(out_delay) RXLOSSOFSYNC0 = RXLOSSOFSYNC0_delay; +assign #(out_delay) RXLOSSOFSYNC1 = RXLOSSOFSYNC1_delay; +assign #(out_delay) RXNOTINTABLE0 = RXNOTINTABLE0_delay; +assign #(out_delay) RXNOTINTABLE1 = RXNOTINTABLE1_delay; +assign #(out_delay) RXOVERSAMPLEERR0 = RXOVERSAMPLEERR0_delay; +assign #(out_delay) RXOVERSAMPLEERR1 = RXOVERSAMPLEERR1_delay; +assign #(out_delay) RXPRBSERR0 = RXPRBSERR0_delay; +assign #(out_delay) RXPRBSERR1 = RXPRBSERR1_delay; +assign #(out_delay) RXRUNDISP0 = RXRUNDISP0_delay; +assign #(out_delay) RXRUNDISP1 = RXRUNDISP1_delay; +assign #(out_delay) RXSTATUS0 = RXSTATUS0_delay; +assign #(out_delay) RXSTATUS1 = RXSTATUS1_delay; +assign #(out_delay) RXVALID0 = RXVALID0_delay; +assign #(out_delay) RXVALID1 = RXVALID1_delay; +assign #(out_delay) TXBUFSTATUS0 = TXBUFSTATUS0_delay; +assign #(out_delay) TXBUFSTATUS1 = TXBUFSTATUS1_delay; +assign #(out_delay) TXKERR0 = TXKERR0_delay; +assign #(out_delay) TXKERR1 = TXKERR1_delay; +assign #(out_delay) TXN0 = TXN0_delay; +assign #(out_delay) TXN1 = TXN1_delay; +assign #(out_delay) TXP0 = TXP0_delay; +assign #(out_delay) TXP1 = TXP1_delay; +assign #(out_delay) TXRUNDISP0 = TXRUNDISP0_delay; +assign #(out_delay) TXRUNDISP1 = TXRUNDISP1_delay; + +assign #(CLK_DELAY) CLKIN_delay = CLKIN; +assign #(CLK_DELAY) DCLK_delay = DCLK; +assign #(CLK_DELAY) RXUSRCLK0_delay = RXUSRCLK0; +assign #(CLK_DELAY) RXUSRCLK1_delay = RXUSRCLK1; +assign #(CLK_DELAY) RXUSRCLK20_delay = RXUSRCLK20; +assign #(CLK_DELAY) RXUSRCLK21_delay = RXUSRCLK21; +assign #(CLK_DELAY) TXUSRCLK0_delay = TXUSRCLK0; +assign #(CLK_DELAY) TXUSRCLK1_delay = TXUSRCLK1; +assign #(CLK_DELAY) TXUSRCLK20_delay = TXUSRCLK20; +assign #(CLK_DELAY) TXUSRCLK21_delay = TXUSRCLK21; + +assign #(in_delay) DADDR_delay = DADDR; +assign #(in_delay) DEN_delay = DEN; +assign #(in_delay) DI_delay = DI; +assign #(in_delay) DWE_delay = DWE; +assign #(in_delay) GTPRESET_delay = GTPRESET; +assign #(in_delay) GTPTEST_delay = GTPTEST; +assign #(in_delay) INTDATAWIDTH_delay = INTDATAWIDTH; +assign #(in_delay) LOOPBACK0_delay = LOOPBACK0; +assign #(in_delay) LOOPBACK1_delay = LOOPBACK1; +assign #(in_delay) PLLLKDETEN_delay = PLLLKDETEN; +assign #(in_delay) PLLPOWERDOWN_delay = PLLPOWERDOWN; +assign #(in_delay) PRBSCNTRESET0_delay = PRBSCNTRESET0; +assign #(in_delay) PRBSCNTRESET1_delay = PRBSCNTRESET1; +assign #(in_delay) REFCLKPWRDNB_delay = REFCLKPWRDNB; +assign #(in_delay) RXBUFRESET0_delay = RXBUFRESET0; +assign #(in_delay) RXBUFRESET1_delay = RXBUFRESET1; +assign #(in_delay) RXCDRRESET0_delay = RXCDRRESET0; +assign #(in_delay) RXCDRRESET1_delay = RXCDRRESET1; +assign #(in_delay) RXCHBONDI0_delay = RXCHBONDI0; +assign #(in_delay) RXCHBONDI1_delay = RXCHBONDI1; +assign #(in_delay) RXCOMMADETUSE0_delay = RXCOMMADETUSE0; +assign #(in_delay) RXCOMMADETUSE1_delay = RXCOMMADETUSE1; +assign #(in_delay) RXDATAWIDTH0_delay = RXDATAWIDTH0; +assign #(in_delay) RXDATAWIDTH1_delay = RXDATAWIDTH1; +assign #(in_delay) RXDEC8B10BUSE0_delay = RXDEC8B10BUSE0; +assign #(in_delay) RXDEC8B10BUSE1_delay = RXDEC8B10BUSE1; +assign #(in_delay) RXELECIDLERESET0_delay = RXELECIDLERESET0; +assign #(in_delay) RXELECIDLERESET1_delay = RXELECIDLERESET1; +assign #(in_delay) RXENCHANSYNC0_delay = RXENCHANSYNC0; +assign #(in_delay) RXENCHANSYNC1_delay = RXENCHANSYNC1; +assign #(in_delay) RXENELECIDLERESETB_delay = RXENELECIDLERESETB; +assign #(in_delay) RXENEQB0_delay = RXENEQB0; +assign #(in_delay) RXENEQB1_delay = RXENEQB1; +assign #(in_delay) RXENMCOMMAALIGN0_delay = RXENMCOMMAALIGN0; +assign #(in_delay) RXENMCOMMAALIGN1_delay = RXENMCOMMAALIGN1; +assign #(in_delay) RXENPCOMMAALIGN0_delay = RXENPCOMMAALIGN0; +assign #(in_delay) RXENPCOMMAALIGN1_delay = RXENPCOMMAALIGN1; +assign #(in_delay) RXENPRBSTST0_delay = RXENPRBSTST0; +assign #(in_delay) RXENPRBSTST1_delay = RXENPRBSTST1; +assign #(in_delay) RXENSAMPLEALIGN0_delay = RXENSAMPLEALIGN0; +assign #(in_delay) RXENSAMPLEALIGN1_delay = RXENSAMPLEALIGN1; +assign #(in_delay) RXEQMIX0_delay = RXEQMIX0; +assign #(in_delay) RXEQMIX1_delay = RXEQMIX1; +assign #(in_delay) RXEQPOLE0_delay = RXEQPOLE0; +assign #(in_delay) RXEQPOLE1_delay = RXEQPOLE1; +assign #(in_delay) RXN0_delay = RXN0; +assign #(in_delay) RXN1_delay = RXN1; +assign #(in_delay) RXP0_delay = RXP0; +assign #(in_delay) RXP1_delay = RXP1; +assign #(in_delay) RXPMASETPHASE0_delay = RXPMASETPHASE0; +assign #(in_delay) RXPMASETPHASE1_delay = RXPMASETPHASE1; +assign #(in_delay) RXPOLARITY0_delay = RXPOLARITY0; +assign #(in_delay) RXPOLARITY1_delay = RXPOLARITY1; +assign #(in_delay) RXPOWERDOWN0_delay = RXPOWERDOWN0; +assign #(in_delay) RXPOWERDOWN1_delay = RXPOWERDOWN1; +assign #(in_delay) RXRESET0_delay = RXRESET0; +assign #(in_delay) RXRESET1_delay = RXRESET1; +assign #(in_delay) RXSLIDE0_delay = RXSLIDE0; +assign #(in_delay) RXSLIDE1_delay = RXSLIDE1; +assign #(in_delay) TXBUFDIFFCTRL0_delay = TXBUFDIFFCTRL0; +assign #(in_delay) TXBUFDIFFCTRL1_delay = TXBUFDIFFCTRL1; +assign #(in_delay) TXBYPASS8B10B0_delay = TXBYPASS8B10B0; +assign #(in_delay) TXBYPASS8B10B1_delay = TXBYPASS8B10B1; +assign #(in_delay) TXCHARDISPMODE0_delay = TXCHARDISPMODE0; +assign #(in_delay) TXCHARDISPMODE1_delay = TXCHARDISPMODE1; +assign #(in_delay) TXCHARDISPVAL0_delay = TXCHARDISPVAL0; +assign #(in_delay) TXCHARDISPVAL1_delay = TXCHARDISPVAL1; +assign #(in_delay) TXCHARISK0_delay = TXCHARISK0; +assign #(in_delay) TXCHARISK1_delay = TXCHARISK1; +assign #(in_delay) TXCOMSTART0_delay = TXCOMSTART0; +assign #(in_delay) TXCOMSTART1_delay = TXCOMSTART1; +assign #(in_delay) TXCOMTYPE0_delay = TXCOMTYPE0; +assign #(in_delay) TXCOMTYPE1_delay = TXCOMTYPE1; +assign #(in_delay) TXDATA0_delay = TXDATA0; +assign #(in_delay) TXDATA1_delay = TXDATA1; +assign #(in_delay) TXDATAWIDTH0_delay = TXDATAWIDTH0; +assign #(in_delay) TXDATAWIDTH1_delay = TXDATAWIDTH1; +assign #(in_delay) TXDETECTRX0_delay = TXDETECTRX0; +assign #(in_delay) TXDETECTRX1_delay = TXDETECTRX1; +assign #(in_delay) TXDIFFCTRL0_delay = TXDIFFCTRL0; +assign #(in_delay) TXDIFFCTRL1_delay = TXDIFFCTRL1; +assign #(in_delay) TXELECIDLE0_delay = TXELECIDLE0; +assign #(in_delay) TXELECIDLE1_delay = TXELECIDLE1; +assign #(in_delay) TXENC8B10BUSE0_delay = TXENC8B10BUSE0; +assign #(in_delay) TXENC8B10BUSE1_delay = TXENC8B10BUSE1; +assign #(in_delay) TXENPMAPHASEALIGN_delay = TXENPMAPHASEALIGN; +assign #(in_delay) TXENPRBSTST0_delay = TXENPRBSTST0; +assign #(in_delay) TXENPRBSTST1_delay = TXENPRBSTST1; +assign #(in_delay) TXINHIBIT0_delay = TXINHIBIT0; +assign #(in_delay) TXINHIBIT1_delay = TXINHIBIT1; +assign #(in_delay) TXPMASETPHASE_delay = TXPMASETPHASE; +assign #(in_delay) TXPOLARITY0_delay = TXPOLARITY0; +assign #(in_delay) TXPOLARITY1_delay = TXPOLARITY1; +assign #(in_delay) TXPOWERDOWN0_delay = TXPOWERDOWN0; +assign #(in_delay) TXPOWERDOWN1_delay = TXPOWERDOWN1; +assign #(in_delay) TXPREEMPHASIS0_delay = TXPREEMPHASIS0; +assign #(in_delay) TXPREEMPHASIS1_delay = TXPREEMPHASIS1; +assign #(in_delay) TXRESET0_delay = TXRESET0; +assign #(in_delay) TXRESET1_delay = TXRESET1; + + GTP_DUAL_FAST gtp_dual_fast_1 ( + .AC_CAP_DIS_0 (AC_CAP_DIS_0_BINARY), + .AC_CAP_DIS_1 (AC_CAP_DIS_1_BINARY), + .ALIGN_COMMA_WORD_0 (ALIGN_COMMA_WORD_0_BINARY), + .ALIGN_COMMA_WORD_1 (ALIGN_COMMA_WORD_1_BINARY), + .CHAN_BOND_1_MAX_SKEW_0 (CHAN_BOND_1_MAX_SKEW_0_BINARY), + .CHAN_BOND_1_MAX_SKEW_1 (CHAN_BOND_1_MAX_SKEW_1_BINARY), + .CHAN_BOND_2_MAX_SKEW_0 (CHAN_BOND_2_MAX_SKEW_0_BINARY), + .CHAN_BOND_2_MAX_SKEW_1 (CHAN_BOND_2_MAX_SKEW_1_BINARY), + .CHAN_BOND_LEVEL_0 (CHAN_BOND_LEVEL_0_BINARY), + .CHAN_BOND_LEVEL_1 (CHAN_BOND_LEVEL_1_BINARY), + .CHAN_BOND_MODE_0 (CHAN_BOND_MODE_0_BINARY), + .CHAN_BOND_MODE_1 (CHAN_BOND_MODE_1_BINARY), + .CHAN_BOND_SEQ_1_1_0 (CHAN_BOND_SEQ_1_1_0), + .CHAN_BOND_SEQ_1_1_1 (CHAN_BOND_SEQ_1_1_1), + .CHAN_BOND_SEQ_1_2_0 (CHAN_BOND_SEQ_1_2_0), + .CHAN_BOND_SEQ_1_2_1 (CHAN_BOND_SEQ_1_2_1), + .CHAN_BOND_SEQ_1_3_0 (CHAN_BOND_SEQ_1_3_0), + .CHAN_BOND_SEQ_1_3_1 (CHAN_BOND_SEQ_1_3_1), + .CHAN_BOND_SEQ_1_4_0 (CHAN_BOND_SEQ_1_4_0), + .CHAN_BOND_SEQ_1_4_1 (CHAN_BOND_SEQ_1_4_1), + .CHAN_BOND_SEQ_1_ENABLE_0 (CHAN_BOND_SEQ_1_ENABLE_0), + .CHAN_BOND_SEQ_1_ENABLE_1 (CHAN_BOND_SEQ_1_ENABLE_1), + .CHAN_BOND_SEQ_2_1_0 (CHAN_BOND_SEQ_2_1_0), + .CHAN_BOND_SEQ_2_1_1 (CHAN_BOND_SEQ_2_1_1), + .CHAN_BOND_SEQ_2_2_0 (CHAN_BOND_SEQ_2_2_0), + .CHAN_BOND_SEQ_2_2_1 (CHAN_BOND_SEQ_2_2_1), + .CHAN_BOND_SEQ_2_3_0 (CHAN_BOND_SEQ_2_3_0), + .CHAN_BOND_SEQ_2_3_1 (CHAN_BOND_SEQ_2_3_1), + .CHAN_BOND_SEQ_2_4_0 (CHAN_BOND_SEQ_2_4_0), + .CHAN_BOND_SEQ_2_4_1 (CHAN_BOND_SEQ_2_4_1), + .CHAN_BOND_SEQ_2_ENABLE_0 (CHAN_BOND_SEQ_2_ENABLE_0), + .CHAN_BOND_SEQ_2_ENABLE_1 (CHAN_BOND_SEQ_2_ENABLE_1), + .CHAN_BOND_SEQ_2_USE_0 (CHAN_BOND_SEQ_2_USE_0_BINARY), + .CHAN_BOND_SEQ_2_USE_1 (CHAN_BOND_SEQ_2_USE_1_BINARY), + .CHAN_BOND_SEQ_LEN_0 (CHAN_BOND_SEQ_LEN_0_BINARY), + .CHAN_BOND_SEQ_LEN_1 (CHAN_BOND_SEQ_LEN_1_BINARY), + .CLK25_DIVIDER (CLK25_DIVIDER_BINARY), + .CLKINDC_B (CLKINDC_B_BINARY), + .CLK_CORRECT_USE_0 (CLK_CORRECT_USE_0_BINARY), + .CLK_CORRECT_USE_1 (CLK_CORRECT_USE_1_BINARY), + .CLK_COR_ADJ_LEN_0 (CLK_COR_ADJ_LEN_0_BINARY), + .CLK_COR_ADJ_LEN_1 (CLK_COR_ADJ_LEN_1_BINARY), + .CLK_COR_DET_LEN_0 (CLK_COR_DET_LEN_0_BINARY), + .CLK_COR_DET_LEN_1 (CLK_COR_DET_LEN_1_BINARY), + .CLK_COR_INSERT_IDLE_FLAG_0 (CLK_COR_INSERT_IDLE_FLAG_0_BINARY), + .CLK_COR_INSERT_IDLE_FLAG_1 (CLK_COR_INSERT_IDLE_FLAG_1_BINARY), + .CLK_COR_KEEP_IDLE_0 (CLK_COR_KEEP_IDLE_0_BINARY), + .CLK_COR_KEEP_IDLE_1 (CLK_COR_KEEP_IDLE_1_BINARY), + .CLK_COR_MAX_LAT_0 (CLK_COR_MAX_LAT_0_BINARY), + .CLK_COR_MAX_LAT_1 (CLK_COR_MAX_LAT_1_BINARY), + .CLK_COR_MIN_LAT_0 (CLK_COR_MIN_LAT_0_BINARY), + .CLK_COR_MIN_LAT_1 (CLK_COR_MIN_LAT_1_BINARY), + .CLK_COR_PRECEDENCE_0 (CLK_COR_PRECEDENCE_0_BINARY), + .CLK_COR_PRECEDENCE_1 (CLK_COR_PRECEDENCE_1_BINARY), + .CLK_COR_REPEAT_WAIT_0 (CLK_COR_REPEAT_WAIT_0_BINARY), + .CLK_COR_REPEAT_WAIT_1 (CLK_COR_REPEAT_WAIT_1_BINARY), + .CLK_COR_SEQ_1_1_0 (CLK_COR_SEQ_1_1_0), + .CLK_COR_SEQ_1_1_1 (CLK_COR_SEQ_1_1_1), + .CLK_COR_SEQ_1_2_0 (CLK_COR_SEQ_1_2_0), + .CLK_COR_SEQ_1_2_1 (CLK_COR_SEQ_1_2_1), + .CLK_COR_SEQ_1_3_0 (CLK_COR_SEQ_1_3_0), + .CLK_COR_SEQ_1_3_1 (CLK_COR_SEQ_1_3_1), + .CLK_COR_SEQ_1_4_0 (CLK_COR_SEQ_1_4_0), + .CLK_COR_SEQ_1_4_1 (CLK_COR_SEQ_1_4_1), + .CLK_COR_SEQ_1_ENABLE_0 (CLK_COR_SEQ_1_ENABLE_0), + .CLK_COR_SEQ_1_ENABLE_1 (CLK_COR_SEQ_1_ENABLE_1), + .CLK_COR_SEQ_2_1_0 (CLK_COR_SEQ_2_1_0), + .CLK_COR_SEQ_2_1_1 (CLK_COR_SEQ_2_1_1), + .CLK_COR_SEQ_2_2_0 (CLK_COR_SEQ_2_2_0), + .CLK_COR_SEQ_2_2_1 (CLK_COR_SEQ_2_2_1), + .CLK_COR_SEQ_2_3_0 (CLK_COR_SEQ_2_3_0), + .CLK_COR_SEQ_2_3_1 (CLK_COR_SEQ_2_3_1), + .CLK_COR_SEQ_2_4_0 (CLK_COR_SEQ_2_4_0), + .CLK_COR_SEQ_2_4_1 (CLK_COR_SEQ_2_4_1), + .CLK_COR_SEQ_2_ENABLE_0 (CLK_COR_SEQ_2_ENABLE_0), + .CLK_COR_SEQ_2_ENABLE_1 (CLK_COR_SEQ_2_ENABLE_1), + .CLK_COR_SEQ_2_USE_0 (CLK_COR_SEQ_2_USE_0_BINARY), + .CLK_COR_SEQ_2_USE_1 (CLK_COR_SEQ_2_USE_1_BINARY), + .COMMA_10B_ENABLE_0 (COMMA_10B_ENABLE_0), + .COMMA_10B_ENABLE_1 (COMMA_10B_ENABLE_1), + .COMMA_DOUBLE_0 (COMMA_DOUBLE_0_BINARY), + .COMMA_DOUBLE_1 (COMMA_DOUBLE_1_BINARY), + .COM_BURST_VAL_0 (COM_BURST_VAL_0), + .COM_BURST_VAL_1 (COM_BURST_VAL_1), + .DEC_MCOMMA_DETECT_0 (DEC_MCOMMA_DETECT_0_BINARY), + .DEC_MCOMMA_DETECT_1 (DEC_MCOMMA_DETECT_1_BINARY), + .DEC_PCOMMA_DETECT_0 (DEC_PCOMMA_DETECT_0_BINARY), + .DEC_PCOMMA_DETECT_1 (DEC_PCOMMA_DETECT_1_BINARY), + .DEC_VALID_COMMA_ONLY_0 (DEC_VALID_COMMA_ONLY_0_BINARY), + .DEC_VALID_COMMA_ONLY_1 (DEC_VALID_COMMA_ONLY_1_BINARY), + .MCOMMA_10B_VALUE_0 (MCOMMA_10B_VALUE_0), + .MCOMMA_10B_VALUE_1 (MCOMMA_10B_VALUE_1), + .MCOMMA_DETECT_0 (MCOMMA_DETECT_0_BINARY), + .MCOMMA_DETECT_1 (MCOMMA_DETECT_1_BINARY), + .OOBDETECT_THRESHOLD_0 (OOBDETECT_THRESHOLD_0), + .OOBDETECT_THRESHOLD_1 (OOBDETECT_THRESHOLD_1), + .OOB_CLK_DIVIDER (OOB_CLK_DIVIDER_BINARY), + .OVERSAMPLE_MODE (OVERSAMPLE_MODE_BINARY), + .PCI_EXPRESS_MODE_0 (PCI_EXPRESS_MODE_0_BINARY), + .PCI_EXPRESS_MODE_1 (PCI_EXPRESS_MODE_1_BINARY), + .PCOMMA_10B_VALUE_0 (PCOMMA_10B_VALUE_0), + .PCOMMA_10B_VALUE_1 (PCOMMA_10B_VALUE_1), + .PCOMMA_DETECT_0 (PCOMMA_DETECT_0_BINARY), + .PCOMMA_DETECT_1 (PCOMMA_DETECT_1_BINARY), + .PCS_COM_CFG (PCS_COM_CFG), + .PLL_DIVSEL_FB (PLL_DIVSEL_FB_BINARY), + .PLL_DIVSEL_REF (PLL_DIVSEL_REF_BINARY), + .PLL_RXDIVSEL_OUT_0 (PLL_RXDIVSEL_OUT_0_BINARY), + .PLL_RXDIVSEL_OUT_1 (PLL_RXDIVSEL_OUT_1_BINARY), + .PLL_SATA_0 (PLL_SATA_0_BINARY), + .PLL_SATA_1 (PLL_SATA_1_BINARY), + .PLL_TXDIVSEL_COMM_OUT (PLL_TXDIVSEL_COMM_OUT_BINARY), + .PLL_TXDIVSEL_OUT_0 (PLL_TXDIVSEL_OUT_0_BINARY), + .PLL_TXDIVSEL_OUT_1 (PLL_TXDIVSEL_OUT_1_BINARY), + .PMA_CDR_SCAN_0 (PMA_CDR_SCAN_0), + .PMA_CDR_SCAN_1 (PMA_CDR_SCAN_1), + .PMA_RX_CFG_0 (PMA_RX_CFG_0), + .PMA_RX_CFG_1 (PMA_RX_CFG_1), + .PRBS_ERR_THRESHOLD_0 (PRBS_ERR_THRESHOLD_0), + .PRBS_ERR_THRESHOLD_1 (PRBS_ERR_THRESHOLD_1), + .RCV_TERM_GND_0 (RCV_TERM_GND_0_BINARY), + .RCV_TERM_GND_1 (RCV_TERM_GND_1_BINARY), + .RCV_TERM_MID_0 (RCV_TERM_MID_0_BINARY), + .RCV_TERM_MID_1 (RCV_TERM_MID_1_BINARY), + .RCV_TERM_VTTRX_0 (RCV_TERM_VTTRX_0_BINARY), + .RCV_TERM_VTTRX_1 (RCV_TERM_VTTRX_1_BINARY), + .RX_BUFFER_USE_0 (RX_BUFFER_USE_0_BINARY), + .RX_BUFFER_USE_1 (RX_BUFFER_USE_1_BINARY), + .RX_DECODE_SEQ_MATCH_0 (RX_DECODE_SEQ_MATCH_0_BINARY), + .RX_DECODE_SEQ_MATCH_1 (RX_DECODE_SEQ_MATCH_1_BINARY), + .RX_LOSS_OF_SYNC_FSM_0 (RX_LOSS_OF_SYNC_FSM_0_BINARY), + .RX_LOSS_OF_SYNC_FSM_1 (RX_LOSS_OF_SYNC_FSM_1_BINARY), + .RX_LOS_INVALID_INCR_0 (RX_LOS_INVALID_INCR_0_BINARY), + .RX_LOS_INVALID_INCR_1 (RX_LOS_INVALID_INCR_1_BINARY), + .RX_LOS_THRESHOLD_0 (RX_LOS_THRESHOLD_0_BINARY), + .RX_LOS_THRESHOLD_1 (RX_LOS_THRESHOLD_1_BINARY), + .RX_SLIDE_MODE_0 (RX_SLIDE_MODE_0_BINARY), + .RX_SLIDE_MODE_1 (RX_SLIDE_MODE_1_BINARY), + .RX_STATUS_FMT_0 (RX_STATUS_FMT_0_BINARY), + .RX_STATUS_FMT_1 (RX_STATUS_FMT_1_BINARY), + .RX_XCLK_SEL_0 (RX_XCLK_SEL_0_BINARY), + .RX_XCLK_SEL_1 (RX_XCLK_SEL_1_BINARY), + .SATA_BURST_VAL_0 (SATA_BURST_VAL_0), + .SATA_BURST_VAL_1 (SATA_BURST_VAL_1), + .SATA_IDLE_VAL_0 (SATA_IDLE_VAL_0), + .SATA_IDLE_VAL_1 (SATA_IDLE_VAL_1), + .SATA_MAX_BURST_0 (SATA_MAX_BURST_0_BINARY), + .SATA_MAX_BURST_1 (SATA_MAX_BURST_1_BINARY), + .SATA_MAX_INIT_0 (SATA_MAX_INIT_0_BINARY), + .SATA_MAX_INIT_1 (SATA_MAX_INIT_1_BINARY), + .SATA_MAX_WAKE_0 (SATA_MAX_WAKE_0_BINARY), + .SATA_MAX_WAKE_1 (SATA_MAX_WAKE_1_BINARY), + .SATA_MIN_BURST_0 (SATA_MIN_BURST_0_BINARY), + .SATA_MIN_BURST_1 (SATA_MIN_BURST_1_BINARY), + .SATA_MIN_INIT_0 (SATA_MIN_INIT_0_BINARY), + .SATA_MIN_INIT_1 (SATA_MIN_INIT_1_BINARY), + .SATA_MIN_WAKE_0 (SATA_MIN_WAKE_0_BINARY), + .SATA_MIN_WAKE_1 (SATA_MIN_WAKE_1_BINARY), + .SIM_GTPRESET_SPEEDUP (SIM_GTPRESET_SPEEDUP_BINARY), + .SIM_PLL_PERDIV2 (SIM_PLL_PERDIV2), + .SIM_RECEIVER_DETECT_PASS0 (SIM_RECEIVER_DETECT_PASS0_BINARY), + .SIM_RECEIVER_DETECT_PASS1 (SIM_RECEIVER_DETECT_PASS1_BINARY), + .TERMINATION_CTRL (TERMINATION_CTRL), + .TERMINATION_IMP_0 (TERMINATION_IMP_0_BINARY), + .TERMINATION_IMP_1 (TERMINATION_IMP_1_BINARY), + .TERMINATION_OVRD (TERMINATION_OVRD_BINARY), + .TRANS_TIME_FROM_P2_0 (TRANS_TIME_FROM_P2_0), + .TRANS_TIME_FROM_P2_1 (TRANS_TIME_FROM_P2_1), + .TRANS_TIME_NON_P2_0 (TRANS_TIME_NON_P2_0), + .TRANS_TIME_NON_P2_1 (TRANS_TIME_NON_P2_1), + .TRANS_TIME_TO_P2_0 (TRANS_TIME_TO_P2_0), + .TRANS_TIME_TO_P2_1 (TRANS_TIME_TO_P2_1), + .TXRX_INVERT_0 (TXRX_INVERT_0), + .TXRX_INVERT_1 (TXRX_INVERT_1), + .TX_BUFFER_USE_0 (TX_BUFFER_USE_0_BINARY), + .TX_BUFFER_USE_1 (TX_BUFFER_USE_1_BINARY), + .TX_DIFF_BOOST_0 (TX_DIFF_BOOST_0_BINARY), + .TX_DIFF_BOOST_1 (TX_DIFF_BOOST_1_BINARY), + .TX_SYNC_FILTERB (TX_SYNC_FILTERB_BINARY), + .TX_XCLK_SEL_0 (TX_XCLK_SEL_0_BINARY), + .TX_XCLK_SEL_1 (TX_XCLK_SEL_1_BINARY), + + .DO (DO_delay), + .DRDY (DRDY_delay), + .PHYSTATUS0 (PHYSTATUS0_delay), + .PHYSTATUS1 (PHYSTATUS1_delay), + .PLLLKDET (PLLLKDET_delay), + .REFCLKOUT (REFCLKOUT_delay), + .RESETDONE0 (RESETDONE0_delay), + .RESETDONE1 (RESETDONE1_delay), + .RXBUFSTATUS0 (RXBUFSTATUS0_delay), + .RXBUFSTATUS1 (RXBUFSTATUS1_delay), + .RXBYTEISALIGNED0 (RXBYTEISALIGNED0_delay), + .RXBYTEISALIGNED1 (RXBYTEISALIGNED1_delay), + .RXBYTEREALIGN0 (RXBYTEREALIGN0_delay), + .RXBYTEREALIGN1 (RXBYTEREALIGN1_delay), + .RXCHANBONDSEQ0 (RXCHANBONDSEQ0_delay), + .RXCHANBONDSEQ1 (RXCHANBONDSEQ1_delay), + .RXCHANISALIGNED0 (RXCHANISALIGNED0_delay), + .RXCHANISALIGNED1 (RXCHANISALIGNED1_delay), + .RXCHANREALIGN0 (RXCHANREALIGN0_delay), + .RXCHANREALIGN1 (RXCHANREALIGN1_delay), + .RXCHARISCOMMA0 (RXCHARISCOMMA0_delay), + .RXCHARISCOMMA1 (RXCHARISCOMMA1_delay), + .RXCHARISK0 (RXCHARISK0_delay), + .RXCHARISK1 (RXCHARISK1_delay), + .RXCHBONDO0 (RXCHBONDO0_delay), + .RXCHBONDO1 (RXCHBONDO1_delay), + .RXCLKCORCNT0 (RXCLKCORCNT0_delay), + .RXCLKCORCNT1 (RXCLKCORCNT1_delay), + .RXCOMMADET0 (RXCOMMADET0_delay), + .RXCOMMADET1 (RXCOMMADET1_delay), + .RXDATA0 (RXDATA0_delay), + .RXDATA1 (RXDATA1_delay), + .RXDISPERR0 (RXDISPERR0_delay), + .RXDISPERR1 (RXDISPERR1_delay), + .RXELECIDLE0 (RXELECIDLE0_delay), + .RXELECIDLE1 (RXELECIDLE1_delay), + .RXLOSSOFSYNC0 (RXLOSSOFSYNC0_delay), + .RXLOSSOFSYNC1 (RXLOSSOFSYNC1_delay), + .RXNOTINTABLE0 (RXNOTINTABLE0_delay), + .RXNOTINTABLE1 (RXNOTINTABLE1_delay), + .RXOVERSAMPLEERR0 (RXOVERSAMPLEERR0_delay), + .RXOVERSAMPLEERR1 (RXOVERSAMPLEERR1_delay), + .RXPRBSERR0 (RXPRBSERR0_delay), + .RXPRBSERR1 (RXPRBSERR1_delay), + .RXRECCLK0 (RXRECCLK0_delay), + .RXRECCLK1 (RXRECCLK1_delay), + .RXRUNDISP0 (RXRUNDISP0_delay), + .RXRUNDISP1 (RXRUNDISP1_delay), + .RXSTATUS0 (RXSTATUS0_delay), + .RXSTATUS1 (RXSTATUS1_delay), + .RXVALID0 (RXVALID0_delay), + .RXVALID1 (RXVALID1_delay), + .TXBUFSTATUS0 (TXBUFSTATUS0_delay), + .TXBUFSTATUS1 (TXBUFSTATUS1_delay), + .TXKERR0 (TXKERR0_delay), + .TXKERR1 (TXKERR1_delay), + .TXN0 (TXN0_delay), + .TXN1 (TXN1_delay), + .TXOUTCLK0 (TXOUTCLK0_delay), + .TXOUTCLK1 (TXOUTCLK1_delay), + .TXP0 (TXP0_delay), + .TXP1 (TXP1_delay), + .TXRUNDISP0 (TXRUNDISP0_delay), + .TXRUNDISP1 (TXRUNDISP1_delay), + + .CLKIN (CLKIN_delay), + .DADDR (DADDR_delay), + .DCLK (DCLK_delay), + .DEN (DEN_delay), + .DI (DI_delay), + .DWE (DWE_delay), + .GTPRESET (GTPRESET_delay), + .GTPTEST (GTPTEST_delay), + .INTDATAWIDTH (INTDATAWIDTH_delay), + .LOOPBACK0 (LOOPBACK0_delay), + .LOOPBACK1 (LOOPBACK1_delay), + .PLLLKDETEN (PLLLKDETEN_delay), + .PLLPOWERDOWN (PLLPOWERDOWN_delay), + .PRBSCNTRESET0 (PRBSCNTRESET0_delay), + .PRBSCNTRESET1 (PRBSCNTRESET1_delay), + .REFCLKPWRDNB (REFCLKPWRDNB_delay), + .RXBUFRESET0 (RXBUFRESET0_delay), + .RXBUFRESET1 (RXBUFRESET1_delay), + .RXCDRRESET0 (RXCDRRESET0_delay), + .RXCDRRESET1 (RXCDRRESET1_delay), + .RXCHBONDI0 (RXCHBONDI0_delay), + .RXCHBONDI1 (RXCHBONDI1_delay), + .RXCOMMADETUSE0 (RXCOMMADETUSE0_delay), + .RXCOMMADETUSE1 (RXCOMMADETUSE1_delay), + .RXDATAWIDTH0 (RXDATAWIDTH0_delay), + .RXDATAWIDTH1 (RXDATAWIDTH1_delay), + .RXDEC8B10BUSE0 (RXDEC8B10BUSE0_delay), + .RXDEC8B10BUSE1 (RXDEC8B10BUSE1_delay), + .RXELECIDLERESET0 (RXELECIDLERESET0_delay), + .RXELECIDLERESET1 (RXELECIDLERESET1_delay), + .RXENCHANSYNC0 (RXENCHANSYNC0_delay), + .RXENCHANSYNC1 (RXENCHANSYNC1_delay), + .RXENELECIDLERESETB (RXENELECIDLERESETB_delay), + .RXENEQB0 (RXENEQB0_delay), + .RXENEQB1 (RXENEQB1_delay), + .RXENMCOMMAALIGN0 (RXENMCOMMAALIGN0_delay), + .RXENMCOMMAALIGN1 (RXENMCOMMAALIGN1_delay), + .RXENPCOMMAALIGN0 (RXENPCOMMAALIGN0_delay), + .RXENPCOMMAALIGN1 (RXENPCOMMAALIGN1_delay), + .RXENPRBSTST0 (RXENPRBSTST0_delay), + .RXENPRBSTST1 (RXENPRBSTST1_delay), + .RXENSAMPLEALIGN0 (RXENSAMPLEALIGN0_delay), + .RXENSAMPLEALIGN1 (RXENSAMPLEALIGN1_delay), + .RXEQMIX0 (RXEQMIX0_delay), + .RXEQMIX1 (RXEQMIX1_delay), + .RXEQPOLE0 (RXEQPOLE0_delay), + .RXEQPOLE1 (RXEQPOLE1_delay), + .RXN0 (RXN0_delay), + .RXN1 (RXN1_delay), + .RXP0 (RXP0_delay), + .RXP1 (RXP1_delay), + .RXPMASETPHASE0 (RXPMASETPHASE0_delay), + .RXPMASETPHASE1 (RXPMASETPHASE1_delay), + .RXPOLARITY0 (RXPOLARITY0_delay), + .RXPOLARITY1 (RXPOLARITY1_delay), + .RXPOWERDOWN0 (RXPOWERDOWN0_delay), + .RXPOWERDOWN1 (RXPOWERDOWN1_delay), + .RXRESET0 (RXRESET0_delay), + .RXRESET1 (RXRESET1_delay), + .RXSLIDE0 (RXSLIDE0_delay), + .RXSLIDE1 (RXSLIDE1_delay), + .RXUSRCLK0 (RXUSRCLK0_delay), + .RXUSRCLK1 (RXUSRCLK1_delay), + .RXUSRCLK20 (RXUSRCLK20_delay), + .RXUSRCLK21 (RXUSRCLK21_delay), + .TXBUFDIFFCTRL0 (TXBUFDIFFCTRL0_delay), + .TXBUFDIFFCTRL1 (TXBUFDIFFCTRL1_delay), + .TXBYPASS8B10B0 (TXBYPASS8B10B0_delay), + .TXBYPASS8B10B1 (TXBYPASS8B10B1_delay), + .TXCHARDISPMODE0 (TXCHARDISPMODE0_delay), + .TXCHARDISPMODE1 (TXCHARDISPMODE1_delay), + .TXCHARDISPVAL0 (TXCHARDISPVAL0_delay), + .TXCHARDISPVAL1 (TXCHARDISPVAL1_delay), + .TXCHARISK0 (TXCHARISK0_delay), + .TXCHARISK1 (TXCHARISK1_delay), + .TXCOMSTART0 (TXCOMSTART0_delay), + .TXCOMSTART1 (TXCOMSTART1_delay), + .TXCOMTYPE0 (TXCOMTYPE0_delay), + .TXCOMTYPE1 (TXCOMTYPE1_delay), + .TXDATA0 (TXDATA0_delay), + .TXDATA1 (TXDATA1_delay), + .TXDATAWIDTH0 (TXDATAWIDTH0_delay), + .TXDATAWIDTH1 (TXDATAWIDTH1_delay), + .TXDETECTRX0 (TXDETECTRX0_delay), + .TXDETECTRX1 (TXDETECTRX1_delay), + .TXDIFFCTRL0 (TXDIFFCTRL0_delay), + .TXDIFFCTRL1 (TXDIFFCTRL1_delay), + .TXELECIDLE0 (TXELECIDLE0_delay), + .TXELECIDLE1 (TXELECIDLE1_delay), + .TXENC8B10BUSE0 (TXENC8B10BUSE0_delay), + .TXENC8B10BUSE1 (TXENC8B10BUSE1_delay), + .TXENPMAPHASEALIGN (TXENPMAPHASEALIGN_delay), + .TXENPRBSTST0 (TXENPRBSTST0_delay), + .TXENPRBSTST1 (TXENPRBSTST1_delay), + .TXINHIBIT0 (TXINHIBIT0_delay), + .TXINHIBIT1 (TXINHIBIT1_delay), + .TXPMASETPHASE (TXPMASETPHASE_delay), + .TXPOLARITY0 (TXPOLARITY0_delay), + .TXPOLARITY1 (TXPOLARITY1_delay), + .TXPOWERDOWN0 (TXPOWERDOWN0_delay), + .TXPOWERDOWN1 (TXPOWERDOWN1_delay), + .TXPREEMPHASIS0 (TXPREEMPHASIS0_delay), + .TXPREEMPHASIS1 (TXPREEMPHASIS1_delay), + .TXRESET0 (TXRESET0_delay), + .TXRESET1 (TXRESET1_delay), + .TXUSRCLK0 (TXUSRCLK0_delay), + .TXUSRCLK1 (TXUSRCLK1_delay), + .TXUSRCLK20 (TXUSRCLK20_delay), + .TXUSRCLK21 (TXUSRCLK21_delay), + + .GSR(GSR) +); + + + +specify + (CLKIN => REFCLKOUT) = (100, 100); + (DCLK => DO) = (100, 100); + (DCLK => DRDY) = (100, 100); + (RXUSRCLK0 => RXCHBONDO0) = (100, 100); + (RXUSRCLK1 => RXCHBONDO1) = (100, 100); + (RXUSRCLK20 => PHYSTATUS0) = (100,100); + (RXUSRCLK20 => RXBUFSTATUS0) = (100, 100); + (RXUSRCLK20 => RXBYTEISALIGNED0) = (100, 100); + (RXUSRCLK20 => RXBYTEREALIGN0) = (100, 100); + (RXUSRCLK20 => RXCHANBONDSEQ0) = (100, 100); + (RXUSRCLK20 => RXCHANISALIGNED0) = (100, 100); + (RXUSRCLK20 => RXCHANREALIGN0) = (100, 100); + (RXUSRCLK20 => RXCHARISCOMMA0) = (100, 100); + (RXUSRCLK20 => RXCHARISK0) = (100, 100); + (RXUSRCLK20 => RXCLKCORCNT0) = (100, 100); + (RXUSRCLK20 => RXCOMMADET0) = (100, 100); + (RXUSRCLK20 => RXDATA0) = (100, 100); + (RXUSRCLK20 => RXDISPERR0) = (100, 100); + (RXUSRCLK20 => RXLOSSOFSYNC0) = (100, 100); + (RXUSRCLK20 => RXNOTINTABLE0) = (100, 100); + (RXUSRCLK20 => RXPRBSERR0) = (100, 100); + (RXUSRCLK20 => RXRUNDISP0) = (100, 100); + (RXUSRCLK20 => RXSTATUS0) = (100, 100); + (RXUSRCLK20 => RXVALID0) = (100, 100); + (RXUSRCLK21 => PHYSTATUS1) = (100,100); + (RXUSRCLK21 => RXBUFSTATUS1) = (100, 100); + (RXUSRCLK21 => RXBYTEISALIGNED1) = (100, 100); + (RXUSRCLK21 => RXBYTEREALIGN1) = (100, 100); + (RXUSRCLK21 => RXCHANBONDSEQ1) = (100, 100); + (RXUSRCLK21 => RXCHANISALIGNED1) = (100, 100); + (RXUSRCLK21 => RXCHANREALIGN1) = (100, 100); + (RXUSRCLK21 => RXCHARISCOMMA1) = (100, 100); + (RXUSRCLK21 => RXCHARISK1) = (100, 100); + (RXUSRCLK21 => RXCLKCORCNT1) = (100, 100); + (RXUSRCLK21 => RXCOMMADET1) = (100, 100); + (RXUSRCLK21 => RXDATA1) = (100, 100); + (RXUSRCLK21 => RXDISPERR1) = (100, 100); + (RXUSRCLK21 => RXLOSSOFSYNC1) = (100, 100); + (RXUSRCLK21 => RXNOTINTABLE1) = (100, 100); + (RXUSRCLK21 => RXPRBSERR1) = (100, 100); + (RXUSRCLK21 => RXRUNDISP1) = (100, 100); + (RXUSRCLK21 => RXSTATUS1) = (100, 100); + (RXUSRCLK21 => RXVALID1) = (100, 100); + (TXUSRCLK20 => RXOVERSAMPLEERR0) = (100, 100); + (TXUSRCLK20 => TXBUFSTATUS0) = (100, 100); + (TXUSRCLK20 => TXKERR0) = (100, 100); + (TXUSRCLK20 => TXRUNDISP0) = (100, 100); + (TXUSRCLK21 => RXOVERSAMPLEERR1) = (100, 100); + (TXUSRCLK21 => TXBUFSTATUS1) = (100, 100); + (TXUSRCLK21 => TXKERR1) = (100, 100); + (TXUSRCLK21 => TXRUNDISP1) = (100, 100); + specparam PATHPULSE$ = 0; +endspecify +endmodule diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/GTXE1.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/GTXE1.v new file mode 100644 index 0000000..967a5db --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/GTXE1.v @@ -0,0 +1,3101 @@ +////////////////////////////////////////////////////// +// Copyright (c) 2010 Xilinx Inc. +// All Right Reserved. +/////////////////////////////////////////////////////// +// +// ____ ___ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / : Gigabit Transceiver +// /__/ /\ Filename : GTXE1.v +// \ \ / \ +// \__\/\__ \ +// +// Revision: 1.0 +// 10/24/08 - CR495047 - Initial version +// 11/04/08 - CR495046 - replace case with if for parameter type integer - writer enhancement +// 11/05/08 - CR494078 - SIM_VERSION real to string +// 11/05/08 - CR495047 - Add DRC checks to unisim wrapper +// 11/19/08 - CR497301 - YML update for parameter default value +// 01/27/09 - CR505569 - parameter checks if to case statement - writer bug +// 02/11/09 - CR507680 - GTXE1 Attribute default changes +// 03/11/09 - CR511750 - Update attribute value to upper case +// 03/24/09 - CR514739 - PMA attribute default update +// 05/05/09 - CR520565 - Update specify block from 100ps to 0ps +// 05/13/09 - CR521563 - Attribute POWER_SAVE default change +// 07/28/09 - CR528324 - Default Attribute YML updates +// 09/21/09 - CR532191 - YML update to add RXPRBSERR_LOOPBACK, SIM_VERSION updated to "2.0", add input RXDLYALIGNMONENB/TXDLYALIGNMONENB +// 03/04/10 - CR552249 - Attribute updates - YML & RTL updated +// 03/16/10 - CR552250 - Additional DRC checks added +// 05/11/10 - CR552250 - DRC check bug fixed +///////////////////////////////////////////////////////// + +`timescale 1 ps / 1 ps + +module GTXE1 ( + COMFINISH, + COMINITDET, + COMSASDET, + COMWAKEDET, + DFECLKDLYADJMON, + DFEEYEDACMON, + DFESENSCAL, + DFETAP1MONITOR, + DFETAP2MONITOR, + DFETAP3MONITOR, + DFETAP4MONITOR, + DRDY, + DRPDO, + MGTREFCLKFAB, + PHYSTATUS, + RXBUFSTATUS, + RXBYTEISALIGNED, + RXBYTEREALIGN, + RXCHANBONDSEQ, + RXCHANISALIGNED, + RXCHANREALIGN, + RXCHARISCOMMA, + RXCHARISK, + RXCHBONDO, + RXCLKCORCNT, + RXCOMMADET, + RXDATA, + RXDATAVALID, + RXDISPERR, + RXDLYALIGNMONITOR, + RXELECIDLE, + RXHEADER, + RXHEADERVALID, + RXLOSSOFSYNC, + RXNOTINTABLE, + RXOVERSAMPLEERR, + RXPLLLKDET, + RXPRBSERR, + RXRATEDONE, + RXRECCLK, + RXRECCLKPCS, + RXRESETDONE, + RXRUNDISP, + RXSTARTOFSEQ, + RXSTATUS, + RXVALID, + TSTOUT, + TXBUFSTATUS, + TXDLYALIGNMONITOR, + TXGEARBOXREADY, + TXKERR, + TXN, + TXOUTCLK, + TXOUTCLKPCS, + TXP, + TXPLLLKDET, + TXRATEDONE, + TXRESETDONE, + TXRUNDISP, + DADDR, + DCLK, + DEN, + DFECLKDLYADJ, + DFEDLYOVRD, + DFETAP1, + DFETAP2, + DFETAP3, + DFETAP4, + DFETAPOVRD, + DI, + DWE, + GATERXELECIDLE, + GREFCLKRX, + GREFCLKTX, + GTXRXRESET, + GTXTEST, + GTXTXRESET, + IGNORESIGDET, + LOOPBACK, + MGTREFCLKRX, + MGTREFCLKTX, + NORTHREFCLKRX, + NORTHREFCLKTX, + PERFCLKRX, + PERFCLKTX, + PLLRXRESET, + PLLTXRESET, + PRBSCNTRESET, + RXBUFRESET, + RXCDRRESET, + RXCHBONDI, + RXCHBONDLEVEL, + RXCHBONDMASTER, + RXCHBONDSLAVE, + RXCOMMADETUSE, + RXDEC8B10BUSE, + RXDLYALIGNDISABLE, + RXDLYALIGNMONENB, + RXDLYALIGNOVERRIDE, + RXDLYALIGNRESET, + RXDLYALIGNSWPPRECURB, + RXDLYALIGNUPDSW, + RXENCHANSYNC, + RXENMCOMMAALIGN, + RXENPCOMMAALIGN, + RXENPMAPHASEALIGN, + RXENPRBSTST, + RXENSAMPLEALIGN, + RXEQMIX, + RXGEARBOXSLIP, + RXN, + RXP, + RXPLLLKDETEN, + RXPLLPOWERDOWN, + RXPLLREFSELDY, + RXPMASETPHASE, + RXPOLARITY, + RXPOWERDOWN, + RXRATE, + RXRESET, + RXSLIDE, + RXUSRCLK, + RXUSRCLK2, + SOUTHREFCLKRX, + SOUTHREFCLKTX, + TSTCLK0, + TSTCLK1, + TSTIN, + TXBUFDIFFCTRL, + TXBYPASS8B10B, + TXCHARDISPMODE, + TXCHARDISPVAL, + TXCHARISK, + TXCOMINIT, + TXCOMSAS, + TXCOMWAKE, + TXDATA, + TXDEEMPH, + TXDETECTRX, + TXDIFFCTRL, + TXDLYALIGNDISABLE, + TXDLYALIGNMONENB, + TXDLYALIGNOVERRIDE, + TXDLYALIGNRESET, + TXDLYALIGNUPDSW, + TXELECIDLE, + TXENC8B10BUSE, + TXENPMAPHASEALIGN, + TXENPRBSTST, + TXHEADER, + TXINHIBIT, + TXMARGIN, + TXPDOWNASYNCH, + TXPLLLKDETEN, + TXPLLPOWERDOWN, + TXPLLREFSELDY, + TXPMASETPHASE, + TXPOLARITY, + TXPOSTEMPHASIS, + TXPOWERDOWN, + TXPRBSFORCEERR, + TXPREEMPHASIS, + TXRATE, + TXRESET, + TXSEQUENCE, + TXSTARTSEQ, + TXSWING, + TXUSRCLK, + TXUSRCLK2, + USRCODEERR +); + + parameter AC_CAP_DIS = "TRUE"; + parameter integer ALIGN_COMMA_WORD = 1; + parameter [1:0] BGTEST_CFG = 2'b00; + parameter [16:0] BIAS_CFG = 17'h00000; + parameter [4:0] CDR_PH_ADJ_TIME = 5'b10100; + parameter integer CHAN_BOND_1_MAX_SKEW = 7; + parameter integer CHAN_BOND_2_MAX_SKEW = 1; + parameter CHAN_BOND_KEEP_ALIGN = "FALSE"; + parameter [9:0] CHAN_BOND_SEQ_1_1 = 10'b0101111100; + parameter [9:0] CHAN_BOND_SEQ_1_2 = 10'b0001001010; + parameter [9:0] CHAN_BOND_SEQ_1_3 = 10'b0001001010; + parameter [9:0] CHAN_BOND_SEQ_1_4 = 10'b0110111100; + parameter [3:0] CHAN_BOND_SEQ_1_ENABLE = 4'b1111; + parameter [9:0] CHAN_BOND_SEQ_2_1 = 10'b0100111100; + parameter [9:0] CHAN_BOND_SEQ_2_2 = 10'b0100111100; + parameter [9:0] CHAN_BOND_SEQ_2_3 = 10'b0110111100; + parameter [9:0] CHAN_BOND_SEQ_2_4 = 10'b0100111100; + parameter [4:0] CHAN_BOND_SEQ_2_CFG = 5'b00000; + parameter [3:0] CHAN_BOND_SEQ_2_ENABLE = 4'b1111; + parameter CHAN_BOND_SEQ_2_USE = "FALSE"; + parameter integer CHAN_BOND_SEQ_LEN = 1; + parameter CLK_CORRECT_USE = "TRUE"; + parameter integer CLK_COR_ADJ_LEN = 1; + parameter integer CLK_COR_DET_LEN = 1; + parameter CLK_COR_INSERT_IDLE_FLAG = "FALSE"; + parameter CLK_COR_KEEP_IDLE = "FALSE"; + parameter integer CLK_COR_MAX_LAT = 20; + parameter integer CLK_COR_MIN_LAT = 18; + parameter CLK_COR_PRECEDENCE = "TRUE"; + parameter integer CLK_COR_REPEAT_WAIT = 0; + parameter [9:0] CLK_COR_SEQ_1_1 = 10'b0100011100; + parameter [9:0] CLK_COR_SEQ_1_2 = 10'b0000000000; + parameter [9:0] CLK_COR_SEQ_1_3 = 10'b0000000000; + parameter [9:0] CLK_COR_SEQ_1_4 = 10'b0000000000; + parameter [3:0] CLK_COR_SEQ_1_ENABLE = 4'b1111; + parameter [9:0] CLK_COR_SEQ_2_1 = 10'b0000000000; + parameter [9:0] CLK_COR_SEQ_2_2 = 10'b0000000000; + parameter [9:0] CLK_COR_SEQ_2_3 = 10'b0000000000; + parameter [9:0] CLK_COR_SEQ_2_4 = 10'b0000000000; + parameter [3:0] CLK_COR_SEQ_2_ENABLE = 4'b1111; + parameter CLK_COR_SEQ_2_USE = "FALSE"; + parameter [1:0] CM_TRIM = 2'b01; + parameter [9:0] COMMA_10B_ENABLE = 10'b1111111111; + parameter COMMA_DOUBLE = "FALSE"; + parameter [3:0] COM_BURST_VAL = 4'b1111; + parameter DEC_MCOMMA_DETECT = "TRUE"; + parameter DEC_PCOMMA_DETECT = "TRUE"; + parameter DEC_VALID_COMMA_ONLY = "TRUE"; + parameter [4:0] DFE_CAL_TIME = 5'b01100; + parameter [7:0] DFE_CFG = 8'b00011011; + parameter [2:0] GEARBOX_ENDEC = 3'b000; + parameter GEN_RXUSRCLK = "TRUE"; + parameter GEN_TXUSRCLK = "TRUE"; + parameter GTX_CFG_PWRUP = "TRUE"; + parameter [9:0] MCOMMA_10B_VALUE = 10'b1010000011; + parameter MCOMMA_DETECT = "TRUE"; + parameter [2:0] OOBDETECT_THRESHOLD = 3'b011; + parameter PCI_EXPRESS_MODE = "FALSE"; + parameter [9:0] PCOMMA_10B_VALUE = 10'b0101111100; + parameter PCOMMA_DETECT = "TRUE"; + parameter PMA_CAS_CLK_EN = "FALSE"; + parameter [26:0] PMA_CDR_SCAN = 27'h640404C; + parameter [75:0] PMA_CFG = 76'h0040000040000000003; + parameter [6:0] PMA_RXSYNC_CFG = 7'h00; + parameter [24:0] PMA_RX_CFG = 25'h05CE048; + parameter [19:0] PMA_TX_CFG = 20'h00082; + parameter [9:0] POWER_SAVE = 10'b0000110100; + parameter RCV_TERM_GND = "FALSE"; + parameter RCV_TERM_VTTRX = "TRUE"; + parameter RXGEARBOX_USE = "FALSE"; + parameter [23:0] RXPLL_COM_CFG = 24'h21680A; + parameter [7:0] RXPLL_CP_CFG = 8'h00; + parameter integer RXPLL_DIVSEL45_FB = 5; + parameter integer RXPLL_DIVSEL_FB = 2; + parameter integer RXPLL_DIVSEL_OUT = 1; + parameter integer RXPLL_DIVSEL_REF = 1; + parameter [2:0] RXPLL_LKDET_CFG = 3'b111; + parameter [0:0] RXPRBSERR_LOOPBACK = 1'b0; + parameter RXRECCLK_CTRL = "RXRECCLKPCS"; + parameter [9:0] RXRECCLK_DLY = 10'b0000000000; + parameter [15:0] RXUSRCLK_DLY = 16'h0000; + parameter RX_BUFFER_USE = "TRUE"; + parameter integer RX_CLK25_DIVIDER = 6; + parameter integer RX_DATA_WIDTH = 20; + parameter RX_DECODE_SEQ_MATCH = "TRUE"; + parameter [3:0] RX_DLYALIGN_CTRINC = 4'b0100; + parameter [4:0] RX_DLYALIGN_EDGESET = 5'b00110; + parameter [3:0] RX_DLYALIGN_LPFINC = 4'b0111; + parameter [2:0] RX_DLYALIGN_MONSEL = 3'b000; + parameter [7:0] RX_DLYALIGN_OVRDSETTING = 8'b00000000; + parameter RX_EN_IDLE_HOLD_CDR = "FALSE"; + parameter RX_EN_IDLE_HOLD_DFE = "TRUE"; + parameter RX_EN_IDLE_RESET_BUF = "TRUE"; + parameter RX_EN_IDLE_RESET_FR = "TRUE"; + parameter RX_EN_IDLE_RESET_PH = "TRUE"; + parameter RX_EN_MODE_RESET_BUF = "TRUE"; + parameter RX_EN_RATE_RESET_BUF = "TRUE"; + parameter RX_EN_REALIGN_RESET_BUF = "FALSE"; + parameter RX_EN_REALIGN_RESET_BUF2 = "FALSE"; + parameter [7:0] RX_EYE_OFFSET = 8'h4C; + parameter [1:0] RX_EYE_SCANMODE = 2'b00; + parameter RX_FIFO_ADDR_MODE = "FULL"; + parameter [3:0] RX_IDLE_HI_CNT = 4'b1000; + parameter [3:0] RX_IDLE_LO_CNT = 4'b0000; + parameter RX_LOSS_OF_SYNC_FSM = "FALSE"; + parameter integer RX_LOS_INVALID_INCR = 1; + parameter integer RX_LOS_THRESHOLD = 4; + parameter RX_OVERSAMPLE_MODE = "FALSE"; + parameter integer RX_SLIDE_AUTO_WAIT = 5; + parameter RX_SLIDE_MODE = "OFF"; + parameter RX_XCLK_SEL = "RXREC"; + parameter integer SAS_MAX_COMSAS = 52; + parameter integer SAS_MIN_COMSAS = 40; + parameter [2:0] SATA_BURST_VAL = 3'b100; + parameter [2:0] SATA_IDLE_VAL = 3'b100; + parameter integer SATA_MAX_BURST = 7; + parameter integer SATA_MAX_INIT = 22; + parameter integer SATA_MAX_WAKE = 7; + parameter integer SATA_MIN_BURST = 4; + parameter integer SATA_MIN_INIT = 12; + parameter integer SATA_MIN_WAKE = 4; + parameter SHOW_REALIGN_COMMA = "TRUE"; + parameter integer SIM_GTXRESET_SPEEDUP = 1; + parameter SIM_RECEIVER_DETECT_PASS = "TRUE"; + parameter [2:0] SIM_RXREFCLK_SOURCE = 3'b000; + parameter [2:0] SIM_TXREFCLK_SOURCE = 3'b000; + parameter SIM_TX_ELEC_IDLE_LEVEL = "X"; + parameter SIM_VERSION = "2.0"; + parameter [4:0] TERMINATION_CTRL = 5'b10100; + parameter TERMINATION_OVRD = "FALSE"; + parameter [11:0] TRANS_TIME_FROM_P2 = 12'h03C; + parameter [7:0] TRANS_TIME_NON_P2 = 8'h19; + parameter [7:0] TRANS_TIME_RATE = 8'h0E; + parameter [9:0] TRANS_TIME_TO_P2 = 10'h064; + parameter [31:0] TST_ATTR = 32'h00000000; + parameter TXDRIVE_LOOPBACK_HIZ = "FALSE"; + parameter TXDRIVE_LOOPBACK_PD = "FALSE"; + parameter TXGEARBOX_USE = "FALSE"; + parameter TXOUTCLK_CTRL = "TXOUTCLKPCS"; + parameter [9:0] TXOUTCLK_DLY = 10'b0000000000; + parameter [23:0] TXPLL_COM_CFG = 24'h21680A; + parameter [7:0] TXPLL_CP_CFG = 8'h00; + parameter integer TXPLL_DIVSEL45_FB = 5; + parameter integer TXPLL_DIVSEL_FB = 2; + parameter integer TXPLL_DIVSEL_OUT = 1; + parameter integer TXPLL_DIVSEL_REF = 1; + parameter [2:0] TXPLL_LKDET_CFG = 3'b111; + parameter [1:0] TXPLL_SATA = 2'b00; + parameter TX_BUFFER_USE = "TRUE"; + parameter [5:0] TX_BYTECLK_CFG = 6'h00; + parameter integer TX_CLK25_DIVIDER = 6; + parameter TX_CLK_SOURCE = "RXPLL"; + parameter integer TX_DATA_WIDTH = 20; + parameter [4:0] TX_DEEMPH_0 = 5'b11010; + parameter [4:0] TX_DEEMPH_1 = 5'b10000; + parameter [13:0] TX_DETECT_RX_CFG = 14'h1832; + parameter [3:0] TX_DLYALIGN_CTRINC = 4'b0100; + parameter [3:0] TX_DLYALIGN_LPFINC = 4'b0110; + parameter [2:0] TX_DLYALIGN_MONSEL = 3'b000; + parameter [7:0] TX_DLYALIGN_OVRDSETTING = 8'b10000000; + parameter TX_DRIVE_MODE = "DIRECT"; + parameter TX_EN_RATE_RESET_BUF = "TRUE"; + parameter [2:0] TX_IDLE_ASSERT_DELAY = 3'b100; + parameter [2:0] TX_IDLE_DEASSERT_DELAY = 3'b010; + parameter [6:0] TX_MARGIN_FULL_0 = 7'b1001110; + parameter [6:0] TX_MARGIN_FULL_1 = 7'b1001001; + parameter [6:0] TX_MARGIN_FULL_2 = 7'b1000101; + parameter [6:0] TX_MARGIN_FULL_3 = 7'b1000010; + parameter [6:0] TX_MARGIN_FULL_4 = 7'b1000000; + parameter [6:0] TX_MARGIN_LOW_0 = 7'b1000110; + parameter [6:0] TX_MARGIN_LOW_1 = 7'b1000100; + parameter [6:0] TX_MARGIN_LOW_2 = 7'b1000010; + parameter [6:0] TX_MARGIN_LOW_3 = 7'b1000000; + parameter [6:0] TX_MARGIN_LOW_4 = 7'b1000000; + parameter TX_OVERSAMPLE_MODE = "FALSE"; + parameter [0:0] TX_PMADATA_OPT = 1'b0; + parameter [1:0] TX_TDCC_CFG = 2'b11; + parameter [5:0] TX_USRCLK_CFG = 6'h00; + parameter TX_XCLK_SEL = "TXUSR"; + + localparam in_delay = 0; + localparam out_delay = 0; + localparam INCLK_DELAY = 0; + localparam OUTCLK_DELAY = 0; + + output COMFINISH; + output COMINITDET; + output COMSASDET; + output COMWAKEDET; + output DRDY; + output PHYSTATUS; + output RXBYTEISALIGNED; + output RXBYTEREALIGN; + output RXCHANBONDSEQ; + output RXCHANISALIGNED; + output RXCHANREALIGN; + output RXCOMMADET; + output RXDATAVALID; + output RXELECIDLE; + output RXHEADERVALID; + output RXOVERSAMPLEERR; + output RXPLLLKDET; + output RXPRBSERR; + output RXRATEDONE; + output RXRECCLK; + output RXRECCLKPCS; + output RXRESETDONE; + output RXSTARTOFSEQ; + output RXVALID; + output TXGEARBOXREADY; + output TXN; + output TXOUTCLK; + output TXOUTCLKPCS; + output TXP; + output TXPLLLKDET; + output TXRATEDONE; + output TXRESETDONE; + output [15:0] DRPDO; + output [1:0] MGTREFCLKFAB; + output [1:0] RXLOSSOFSYNC; + output [1:0] TXBUFSTATUS; + output [2:0] DFESENSCAL; + output [2:0] RXBUFSTATUS; + output [2:0] RXCLKCORCNT; + output [2:0] RXHEADER; + output [2:0] RXSTATUS; + output [31:0] RXDATA; + output [3:0] DFETAP3MONITOR; + output [3:0] DFETAP4MONITOR; + output [3:0] RXCHARISCOMMA; + output [3:0] RXCHARISK; + output [3:0] RXCHBONDO; + output [3:0] RXDISPERR; + output [3:0] RXNOTINTABLE; + output [3:0] RXRUNDISP; + output [3:0] TXKERR; + output [3:0] TXRUNDISP; + output [4:0] DFEEYEDACMON; + output [4:0] DFETAP1MONITOR; + output [4:0] DFETAP2MONITOR; + output [5:0] DFECLKDLYADJMON; + output [7:0] RXDLYALIGNMONITOR; + output [7:0] TXDLYALIGNMONITOR; + output [9:0] TSTOUT; + + input DCLK; + input DEN; + input DFEDLYOVRD; + input DFETAPOVRD; + input DWE; + input GATERXELECIDLE; + input GREFCLKRX; + input GREFCLKTX; + input GTXRXRESET; + input GTXTXRESET; + input IGNORESIGDET; + input PERFCLKRX; + input PERFCLKTX; + input PLLRXRESET; + input PLLTXRESET; + input PRBSCNTRESET; + input RXBUFRESET; + input RXCDRRESET; + input RXCHBONDMASTER; + input RXCHBONDSLAVE; + input RXCOMMADETUSE; + input RXDEC8B10BUSE; + input RXDLYALIGNDISABLE; + input RXDLYALIGNMONENB; + input RXDLYALIGNOVERRIDE; + input RXDLYALIGNRESET; + input RXDLYALIGNSWPPRECURB; + input RXDLYALIGNUPDSW; + input RXENCHANSYNC; + input RXENMCOMMAALIGN; + input RXENPCOMMAALIGN; + input RXENPMAPHASEALIGN; + input RXENSAMPLEALIGN; + input RXGEARBOXSLIP; + input RXN; + input RXP; + input RXPLLLKDETEN; + input RXPLLPOWERDOWN; + input RXPMASETPHASE; + input RXPOLARITY; + input RXRESET; + input RXSLIDE; + input RXUSRCLK2; + input RXUSRCLK; + input TSTCLK0; + input TSTCLK1; + input TXCOMINIT; + input TXCOMSAS; + input TXCOMWAKE; + input TXDEEMPH; + input TXDETECTRX; + input TXDLYALIGNDISABLE; + input TXDLYALIGNMONENB; + input TXDLYALIGNOVERRIDE; + input TXDLYALIGNRESET; + input TXDLYALIGNUPDSW; + input TXELECIDLE; + input TXENC8B10BUSE; + input TXENPMAPHASEALIGN; + input TXINHIBIT; + input TXPDOWNASYNCH; + input TXPLLLKDETEN; + input TXPLLPOWERDOWN; + input TXPMASETPHASE; + input TXPOLARITY; + input TXPRBSFORCEERR; + input TXRESET; + input TXSTARTSEQ; + input TXSWING; + input TXUSRCLK2; + input TXUSRCLK; + input USRCODEERR; + input [12:0] GTXTEST; + input [15:0] DI; + input [19:0] TSTIN; + input [1:0] MGTREFCLKRX; + input [1:0] MGTREFCLKTX; + input [1:0] NORTHREFCLKRX; + input [1:0] NORTHREFCLKTX; + input [1:0] RXPOWERDOWN; + input [1:0] RXRATE; + input [1:0] SOUTHREFCLKRX; + input [1:0] SOUTHREFCLKTX; + input [1:0] TXPOWERDOWN; + input [1:0] TXRATE; + input [2:0] LOOPBACK; + input [2:0] RXCHBONDLEVEL; + input [2:0] RXENPRBSTST; + input [2:0] RXPLLREFSELDY; + input [2:0] TXBUFDIFFCTRL; + input [2:0] TXENPRBSTST; + input [2:0] TXHEADER; + input [2:0] TXMARGIN; + input [2:0] TXPLLREFSELDY; + input [31:0] TXDATA; + input [3:0] DFETAP3; + input [3:0] DFETAP4; + input [3:0] RXCHBONDI; + input [3:0] TXBYPASS8B10B; + input [3:0] TXCHARDISPMODE; + input [3:0] TXCHARDISPVAL; + input [3:0] TXCHARISK; + input [3:0] TXDIFFCTRL; + input [3:0] TXPREEMPHASIS; + input [4:0] DFETAP1; + input [4:0] DFETAP2; + input [4:0] TXPOSTEMPHASIS; + input [5:0] DFECLKDLYADJ; + input [6:0] TXSEQUENCE; + input [7:0] DADDR; + input [9:0] RXEQMIX; + + reg AC_CAP_DIS_BINARY; + reg ALIGN_COMMA_WORD_BINARY; + reg CHAN_BOND_KEEP_ALIGN_BINARY; + reg CHAN_BOND_SEQ_2_USE_BINARY; + reg CLK_CORRECT_USE_BINARY; + reg CLK_COR_INSERT_IDLE_FLAG_BINARY; + reg CLK_COR_KEEP_IDLE_BINARY; + reg CLK_COR_PRECEDENCE_BINARY; + reg CLK_COR_SEQ_2_USE_BINARY; + reg COMMA_DOUBLE_BINARY; + reg DEC_MCOMMA_DETECT_BINARY; + reg DEC_PCOMMA_DETECT_BINARY; + reg DEC_VALID_COMMA_ONLY_BINARY; + reg GEN_RXUSRCLK_BINARY; + reg GEN_TXUSRCLK_BINARY; + reg GTX_CFG_PWRUP_BINARY; + reg MCOMMA_DETECT_BINARY; + reg PCI_EXPRESS_MODE_BINARY; + reg PCOMMA_DETECT_BINARY; + reg PMA_CAS_CLK_EN_BINARY; + reg RCV_TERM_GND_BINARY; + reg RCV_TERM_VTTRX_BINARY; + reg RXGEARBOX_USE_BINARY; + reg RXPLL_DIVSEL45_FB_BINARY; + reg RXPRBSERR_LOOPBACK_BINARY; + reg RX_BUFFER_USE_BINARY; + reg RX_DECODE_SEQ_MATCH_BINARY; + reg RX_EN_IDLE_HOLD_CDR_BINARY; + reg RX_EN_IDLE_HOLD_DFE_BINARY; + reg RX_EN_IDLE_RESET_BUF_BINARY; + reg RX_EN_IDLE_RESET_FR_BINARY; + reg RX_EN_IDLE_RESET_PH_BINARY; + reg RX_EN_MODE_RESET_BUF_BINARY; + reg RX_EN_RATE_RESET_BUF_BINARY; + reg RX_EN_REALIGN_RESET_BUF2_BINARY; + reg RX_EN_REALIGN_RESET_BUF_BINARY; + reg RX_FIFO_ADDR_MODE_BINARY; + reg RX_LOSS_OF_SYNC_FSM_BINARY; + reg RX_OVERSAMPLE_MODE_BINARY; + reg RX_XCLK_SEL_BINARY; + reg SHOW_REALIGN_COMMA_BINARY; + reg SIM_GTXRESET_SPEEDUP_BINARY; + reg SIM_RECEIVER_DETECT_PASS_BINARY; + reg SIM_TX_ELEC_IDLE_LEVEL_BINARY; + reg SIM_VERSION_BINARY; + reg TERMINATION_OVRD_BINARY; + reg TXDRIVE_LOOPBACK_HIZ_BINARY; + reg TXDRIVE_LOOPBACK_PD_BINARY; + reg TXGEARBOX_USE_BINARY; + reg TXPLL_DIVSEL45_FB_BINARY; + reg TX_BUFFER_USE_BINARY; + reg TX_CLK_SOURCE_BINARY; + reg TX_DRIVE_MODE_BINARY; + reg TX_EN_RATE_RESET_BUF_BINARY; + reg TX_OVERSAMPLE_MODE_BINARY; + reg TX_PMADATA_OPT_BINARY; + reg TX_XCLK_SEL_BINARY; + reg [1:0] BGTEST_CFG_BINARY; + reg [1:0] CHAN_BOND_SEQ_LEN_BINARY; + reg [1:0] CLK_COR_ADJ_LEN_BINARY; + reg [1:0] CLK_COR_DET_LEN_BINARY; + reg [1:0] CM_TRIM_BINARY; + reg [1:0] RXPLL_DIVSEL_OUT_BINARY; + reg [1:0] RX_EYE_SCANMODE_BINARY; + reg [1:0] RX_SLIDE_MODE_BINARY; + reg [1:0] TXPLL_DIVSEL_OUT_BINARY; + reg [1:0] TXPLL_SATA_BINARY; + reg [1:0] TX_TDCC_CFG_BINARY; + reg [2:0] GEARBOX_ENDEC_BINARY; + reg [2:0] OOBDETECT_THRESHOLD_BINARY; + reg [2:0] RXPLL_LKDET_CFG_BINARY; + reg [2:0] RXRECCLK_CTRL_BINARY; + reg [2:0] RX_DATA_WIDTH_BINARY; + reg [2:0] RX_DLYALIGN_MONSEL_BINARY; + reg [2:0] RX_LOS_INVALID_INCR_BINARY; + reg [2:0] RX_LOS_THRESHOLD_BINARY; + reg [2:0] SATA_BURST_VAL_BINARY; + reg [2:0] SATA_IDLE_VAL_BINARY; + reg [2:0] SIM_RXREFCLK_SOURCE_BINARY; + reg [2:0] SIM_TXREFCLK_SOURCE_BINARY; + reg [2:0] TXOUTCLK_CTRL_BINARY; + reg [2:0] TXPLL_LKDET_CFG_BINARY; + reg [2:0] TX_DATA_WIDTH_BINARY; + reg [2:0] TX_DLYALIGN_MONSEL_BINARY; + reg [2:0] TX_IDLE_ASSERT_DELAY_BINARY; + reg [2:0] TX_IDLE_DEASSERT_DELAY_BINARY; + reg [3:0] CHAN_BOND_1_MAX_SKEW_BINARY; + reg [3:0] CHAN_BOND_2_MAX_SKEW_BINARY; + reg [3:0] CHAN_BOND_SEQ_1_ENABLE_BINARY; + reg [3:0] CHAN_BOND_SEQ_2_ENABLE_BINARY; + reg [3:0] CLK_COR_SEQ_1_ENABLE_BINARY; + reg [3:0] CLK_COR_SEQ_2_ENABLE_BINARY; + reg [3:0] COM_BURST_VAL_BINARY; + reg [3:0] RX_DLYALIGN_CTRINC_BINARY; + reg [3:0] RX_DLYALIGN_LPFINC_BINARY; + reg [3:0] RX_IDLE_HI_CNT_BINARY; + reg [3:0] RX_IDLE_LO_CNT_BINARY; + reg [3:0] RX_SLIDE_AUTO_WAIT_BINARY; + reg [3:0] TX_DLYALIGN_CTRINC_BINARY; + reg [3:0] TX_DLYALIGN_LPFINC_BINARY; + reg [4:0] CDR_PH_ADJ_TIME_BINARY; + reg [4:0] CHAN_BOND_SEQ_2_CFG_BINARY; + reg [4:0] CLK_COR_REPEAT_WAIT_BINARY; + reg [4:0] DFE_CAL_TIME_BINARY; + reg [4:0] RXPLL_DIVSEL_FB_BINARY; + reg [4:0] RXPLL_DIVSEL_REF_BINARY; + reg [4:0] RX_CLK25_DIVIDER_BINARY; + reg [4:0] RX_DLYALIGN_EDGESET_BINARY; + reg [4:0] TERMINATION_CTRL_BINARY; + reg [4:0] TXPLL_DIVSEL_FB_BINARY; + reg [4:0] TXPLL_DIVSEL_REF_BINARY; + reg [4:0] TX_CLK25_DIVIDER_BINARY; + reg [4:0] TX_DEEMPH_0_BINARY; + reg [4:0] TX_DEEMPH_1_BINARY; + reg [5:0] CLK_COR_MAX_LAT_BINARY; + reg [5:0] CLK_COR_MIN_LAT_BINARY; + reg [5:0] SAS_MAX_COMSAS_BINARY; + reg [5:0] SAS_MIN_COMSAS_BINARY; + reg [5:0] SATA_MAX_BURST_BINARY; + reg [5:0] SATA_MAX_INIT_BINARY; + reg [5:0] SATA_MAX_WAKE_BINARY; + reg [5:0] SATA_MIN_BURST_BINARY; + reg [5:0] SATA_MIN_INIT_BINARY; + reg [5:0] SATA_MIN_WAKE_BINARY; + reg [6:0] TX_MARGIN_FULL_0_BINARY; + reg [6:0] TX_MARGIN_FULL_1_BINARY; + reg [6:0] TX_MARGIN_FULL_2_BINARY; + reg [6:0] TX_MARGIN_FULL_3_BINARY; + reg [6:0] TX_MARGIN_FULL_4_BINARY; + reg [6:0] TX_MARGIN_LOW_0_BINARY; + reg [6:0] TX_MARGIN_LOW_1_BINARY; + reg [6:0] TX_MARGIN_LOW_2_BINARY; + reg [6:0] TX_MARGIN_LOW_3_BINARY; + reg [6:0] TX_MARGIN_LOW_4_BINARY; + reg [7:0] DFE_CFG_BINARY; + reg [7:0] RX_DLYALIGN_OVRDSETTING_BINARY; + reg [7:0] TX_DLYALIGN_OVRDSETTING_BINARY; + reg [9:0] CHAN_BOND_SEQ_1_1_BINARY; + reg [9:0] CHAN_BOND_SEQ_1_2_BINARY; + reg [9:0] CHAN_BOND_SEQ_1_3_BINARY; + reg [9:0] CHAN_BOND_SEQ_1_4_BINARY; + reg [9:0] CHAN_BOND_SEQ_2_1_BINARY; + reg [9:0] CHAN_BOND_SEQ_2_2_BINARY; + reg [9:0] CHAN_BOND_SEQ_2_3_BINARY; + reg [9:0] CHAN_BOND_SEQ_2_4_BINARY; + reg [9:0] CLK_COR_SEQ_1_1_BINARY; + reg [9:0] CLK_COR_SEQ_1_2_BINARY; + reg [9:0] CLK_COR_SEQ_1_3_BINARY; + reg [9:0] CLK_COR_SEQ_1_4_BINARY; + reg [9:0] CLK_COR_SEQ_2_1_BINARY; + reg [9:0] CLK_COR_SEQ_2_2_BINARY; + reg [9:0] CLK_COR_SEQ_2_3_BINARY; + reg [9:0] CLK_COR_SEQ_2_4_BINARY; + reg [9:0] COMMA_10B_ENABLE_BINARY; + reg [9:0] MCOMMA_10B_VALUE_BINARY; + reg [9:0] PCOMMA_10B_VALUE_BINARY; + reg [9:0] POWER_SAVE_BINARY; + reg [9:0] RXRECCLK_DLY_BINARY; + reg [9:0] TXOUTCLK_DLY_BINARY; + + tri0 GSR = glbl.GSR; + + initial begin + + // Start DRC checks + + if (CHAN_BOND_2_MAX_SKEW > CHAN_BOND_1_MAX_SKEW) begin + $display("DRC Error : The value of CHAN_BOND_2_MAX_SKEW is set to %d. This value must be less than or equal to the value of CHAN_BOND_1_MAX_SKEW %d for instance %m of GTXE1.",CHAN_BOND_2_MAX_SKEW, CHAN_BOND_1_MAX_SKEW); + $finish; + end + + if (CLK_COR_MIN_LAT > CLK_COR_MAX_LAT) begin + $display("DRC Error : The value of CLK_COR_MIN_LAT is set to %d. This value must be less than or equal to the value of CLK_COR_MAX_LAT %d for instance %m of GTXE1.",CLK_COR_MIN_LAT, CLK_COR_MAX_LAT); + $finish; + end + + if (SATA_MIN_BURST > SATA_MAX_BURST) begin + $display("DRC Error : The value of SATA_MIN_BURST is set to %d. This value must be less than or equal to the value of SATA_MAX_BURST %d for instance %m of GTXE1.",SATA_MIN_BURST, SATA_MAX_BURST); + $finish; + end + + if (SATA_MIN_INIT > SATA_MAX_INIT) begin + $display("DRC Error : The value of SATA_MIN_INIT is set to %d. This value must be less than or equal to the value of SATA_MAX_INIT %d for instance %m of GTXE1.",SATA_MIN_INIT, SATA_MAX_INIT); + $finish; + end + + if (SATA_MIN_WAKE > SATA_MAX_WAKE) begin + $display("DRC Error : The value of SATA_MIN_WAKE is set to %d. This value must be less than or equal to the value of SATA_MAX_WAKE %d for instance %m of GTXE1.",SATA_MIN_WAKE, SATA_MAX_WAKE); + $finish; + end + + if (SAS_MIN_COMSAS > SAS_MAX_COMSAS) begin + $display("DRC Error : The value of SAS_MIN_COMSAS is set to %d. This value must be less than or equal to the value of SAS_MAX_COMSAS %d for instance %m of GTXE1.",SAS_MIN_COMSAS, SAS_MAX_COMSAS); + $finish; + end + + if ((RX_DATA_WIDTH == 16 && GEN_RXUSRCLK == "FALSE") || (RX_DATA_WIDTH == 20 && GEN_RXUSRCLK == "FALSE")) begin + $display("DRC Error : The following attribute condition must be satisfied for instance %m of GTXE1 : If RX_DATA_WIDTH is 8 or 10 (and channel bonding is not used) or if RX_DATA_WIDTH is 16 or 20 then set GEN_RXUSRCLK to TRUE."); + $finish; + end + + if ((RX_DATA_WIDTH == 32 && GEN_RXUSRCLK == "TRUE") || (RX_DATA_WIDTH == 40 && GEN_RXUSRCLK == "TRUE")) begin + $display("DRC Error : The following attribute condition must be satisfied for instance %m of GTXE1 : If RX_DATA_WIDTH is 32 or 40 then set GEN_RXUSRCLK to FALSE."); + $finish; + end + + if ((TX_DATA_WIDTH == 16 && GEN_TXUSRCLK == "FALSE") || (TX_DATA_WIDTH == 20 && GEN_TXUSRCLK == "FALSE")) begin + $display("DRC Error : The following attribute condition must be satisfied for instance %m of GTXE1 : If TX_DATA_WIDTH is 8 or 10 (and channel bonding is not used) or if TX_DATA_WIDTH is 16 or 20 then set GEN_TXUSRCLK to TRUE."); + $finish; + end + + if ((TX_DATA_WIDTH == 32 && GEN_TXUSRCLK == "TRUE") || (TX_DATA_WIDTH == 40 && GEN_TXUSRCLK == "TRUE")) begin + $display("DRC Error : The following attribute condition must be satisfied for instance %m of GTXE1 : If TX_DATA_WIDTH is 32 or 40 then set GEN_TXUSRCLK to FALSE."); + $finish; + end + + if (CLK_CORRECT_USE == "TRUE" && RX_FIFO_ADDR_MODE == "FAST") begin + $display("DRC Error : The following attribute condition must be satisfied for instance %m of GTXE1 : If CLK_CORRECT_USE is TRUE then set RX_FIFO_ADDR_MODE to FULL."); + $finish; + end + + if ((RX_SLIDE_MODE == "PMA" && SHOW_REALIGN_COMMA == "TRUE") || (RX_SLIDE_MODE == "AUTO" && SHOW_REALIGN_COMMA == "TRUE")) begin + $display("DRC Error : The following attribute condition must be satisfied for instance %m of GTXE1 : If RX_SLIDE_MODE is PMA or AUTO then set SHOW_REALIGN_COMMA to FALSE."); + $finish; + end + + if (TXOUTCLK_CTRL == "CLKTESTSIG0") begin + $display("DRC Error : TXOUTCLK_CTRL cannot be set to %s for instance %m of GTXE1.", TXOUTCLK_CTRL); + $finish; + end + + if (RXRECCLK_CTRL == "CLKTESTSIG1") begin + $display("DRC Error :RXRECCLK_CTRL cannot be set to %s for instance %m of GTXE1.", RXRECCLK_CTRL); + $finish; + end + + if (TXOUTCLK_CTRL == "OFF_LOW") begin + $display("DRC Error : TXOUTCLK_CTRL cannot be set to %s for instance %m of GTXE1.", TXOUTCLK_CTRL); + $finish; + end + + if (RXRECCLK_CTRL == "OFF_LOW") begin + $display("DRC Error :RXRECCLK_CTRL cannot be set to %s for instance %m of GTXE1.", RXRECCLK_CTRL); + $finish; + end + + if (TXOUTCLK_CTRL == "OFF_HIGH") begin + $display("DRC Error : TXOUTCLK_CTRL cannot be set to %s for instance %m of GTXE1.", TXOUTCLK_CTRL); + $finish; + end + + if (RXRECCLK_CTRL == "OFF_HIGH") begin + $display("DRC Error :RXRECCLK_CTRL cannot be set to %s for instance %m of GTXE1.", RXRECCLK_CTRL); + $finish; + end + + if ((TX_BUFFER_USE == "TRUE") && (POWER_SAVE[4] != 1)) begin + $display("DRC Error : If value of TX_BUFFER_USE is set to %s then value of POWER_SAVE[4] has to be set to 1 for instance %m of GTXE1.", TX_BUFFER_USE, POWER_SAVE); + $finish; + end + + if ((TX_BUFFER_USE == "FALSE") && (POWER_SAVE[4] != 0)) begin + $display("DRC Error : If value of TX_BUFFER_USE is set to %s then value of POWER_SAVE[4] has to be set to 0 for instance %m of GTXE1.", TX_BUFFER_USE, POWER_SAVE); + $finish; + end + + if ((RX_BUFFER_USE == "TRUE") && (POWER_SAVE[5] != 1)) begin + $display("DRC Error : If value of RX_BUFFER_USE is set to %s then value of POWER_SAVE[5] has to be set to 1 for instance %m of GTXE1.", RX_BUFFER_USE, POWER_SAVE); + $finish; + end + + if ((RX_BUFFER_USE == "FALSE") && (POWER_SAVE[5] != 0)) begin + $display("DRC Error : If value of RX_BUFFER_USE is set to %s then value of POWER_SAVE[5] has to be set to 0 for instance %m of GTXE1.", RX_BUFFER_USE, POWER_SAVE); + $finish; + end + + // End DRC checks + + case (AC_CAP_DIS) + "FALSE" : AC_CAP_DIS_BINARY = 1'b0; + "TRUE" : AC_CAP_DIS_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute AC_CAP_DIS on GTXE1 instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", AC_CAP_DIS); + $finish; + end + endcase + + case (ALIGN_COMMA_WORD) + 1 : ALIGN_COMMA_WORD_BINARY = 1'b0; + 2 : ALIGN_COMMA_WORD_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute ALIGN_COMMA_WORD on GTXE1 instance %m is set to %d. Legal values for this attribute are 1 to 2.", ALIGN_COMMA_WORD, 1); + $finish; + end + endcase + + case (CHAN_BOND_KEEP_ALIGN) + "FALSE" : CHAN_BOND_KEEP_ALIGN_BINARY = 1'b0; + "TRUE" : CHAN_BOND_KEEP_ALIGN_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute CHAN_BOND_KEEP_ALIGN on GTXE1 instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", CHAN_BOND_KEEP_ALIGN); + $finish; + end + endcase + + case (CHAN_BOND_SEQ_2_USE) + "FALSE" : CHAN_BOND_SEQ_2_USE_BINARY = 1'b0; + "TRUE" : CHAN_BOND_SEQ_2_USE_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute CHAN_BOND_SEQ_2_USE on GTXE1 instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", CHAN_BOND_SEQ_2_USE); + $finish; + end + endcase + + case (CHAN_BOND_SEQ_LEN) + 1 : CHAN_BOND_SEQ_LEN_BINARY = 2'b00; + 2 : CHAN_BOND_SEQ_LEN_BINARY = 2'b01; + 4 : CHAN_BOND_SEQ_LEN_BINARY = 2'b11; + default : begin + $display("Attribute Syntax Error : The Attribute CHAN_BOND_SEQ_LEN on GTXE1 instance %m is set to %d. Legal values for this attribute are 1 to 4.", CHAN_BOND_SEQ_LEN, 1); + $finish; + end + endcase + + case (CLK_CORRECT_USE) + "FALSE" : CLK_CORRECT_USE_BINARY = 1'b0; + "TRUE" : CLK_CORRECT_USE_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute CLK_CORRECT_USE on GTXE1 instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", CLK_CORRECT_USE); + $finish; + end + endcase + + case (CLK_COR_ADJ_LEN) + 1 : CLK_COR_ADJ_LEN_BINARY = 2'b00; + 2 : CLK_COR_ADJ_LEN_BINARY = 2'b01; + 4 : CLK_COR_ADJ_LEN_BINARY = 2'b11; + default : begin + $display("Attribute Syntax Error : The Attribute CLK_COR_ADJ_LEN on GTXE1 instance %m is set to %d. Legal values for this attribute are 1 to 4.", CLK_COR_ADJ_LEN, 1); + $finish; + end + endcase + + case (CLK_COR_DET_LEN) + 1 : CLK_COR_DET_LEN_BINARY = 2'b00; + 2 : CLK_COR_DET_LEN_BINARY = 2'b01; + 4 : CLK_COR_DET_LEN_BINARY = 2'b11; + default : begin + $display("Attribute Syntax Error : The Attribute CLK_COR_DET_LEN on GTXE1 instance %m is set to %d. Legal values for this attribute are 1 to 4.", CLK_COR_DET_LEN, 1); + $finish; + end + endcase + + case (CLK_COR_INSERT_IDLE_FLAG) + "FALSE" : CLK_COR_INSERT_IDLE_FLAG_BINARY = 1'b0; + "TRUE" : CLK_COR_INSERT_IDLE_FLAG_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute CLK_COR_INSERT_IDLE_FLAG on GTXE1 instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", CLK_COR_INSERT_IDLE_FLAG); + $finish; + end + endcase + + case (CLK_COR_KEEP_IDLE) + "FALSE" : CLK_COR_KEEP_IDLE_BINARY = 1'b0; + "TRUE" : CLK_COR_KEEP_IDLE_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute CLK_COR_KEEP_IDLE on GTXE1 instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", CLK_COR_KEEP_IDLE); + $finish; + end + endcase + + case (CLK_COR_PRECEDENCE) + "FALSE" : CLK_COR_PRECEDENCE_BINARY = 1'b0; + "TRUE" : CLK_COR_PRECEDENCE_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute CLK_COR_PRECEDENCE on GTXE1 instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", CLK_COR_PRECEDENCE); + $finish; + end + endcase + + case (CLK_COR_SEQ_2_USE) + "FALSE" : CLK_COR_SEQ_2_USE_BINARY = 1'b0; + "TRUE" : CLK_COR_SEQ_2_USE_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute CLK_COR_SEQ_2_USE on GTXE1 instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", CLK_COR_SEQ_2_USE); + $finish; + end + endcase + + case (COMMA_DOUBLE) + "FALSE" : COMMA_DOUBLE_BINARY = 1'b0; + "TRUE" : COMMA_DOUBLE_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute COMMA_DOUBLE on GTXE1 instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", COMMA_DOUBLE); + $finish; + end + endcase + + case (DEC_MCOMMA_DETECT) + "FALSE" : DEC_MCOMMA_DETECT_BINARY = 1'b0; + "TRUE" : DEC_MCOMMA_DETECT_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute DEC_MCOMMA_DETECT on GTXE1 instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", DEC_MCOMMA_DETECT); + $finish; + end + endcase + + case (DEC_PCOMMA_DETECT) + "FALSE" : DEC_PCOMMA_DETECT_BINARY = 1'b0; + "TRUE" : DEC_PCOMMA_DETECT_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute DEC_PCOMMA_DETECT on GTXE1 instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", DEC_PCOMMA_DETECT); + $finish; + end + endcase + + case (DEC_VALID_COMMA_ONLY) + "FALSE" : DEC_VALID_COMMA_ONLY_BINARY = 1'b0; + "TRUE" : DEC_VALID_COMMA_ONLY_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute DEC_VALID_COMMA_ONLY on GTXE1 instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", DEC_VALID_COMMA_ONLY); + $finish; + end + endcase + + case (GEN_RXUSRCLK) + "FALSE" : GEN_RXUSRCLK_BINARY = 1'b0; + "TRUE" : GEN_RXUSRCLK_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute GEN_RXUSRCLK on GTXE1 instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", GEN_RXUSRCLK); + $finish; + end + endcase + + case (GEN_TXUSRCLK) + "FALSE" : GEN_TXUSRCLK_BINARY = 1'b0; + "TRUE" : GEN_TXUSRCLK_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute GEN_TXUSRCLK on GTXE1 instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", GEN_TXUSRCLK); + $finish; + end + endcase + + case (GTX_CFG_PWRUP) + "FALSE" : GTX_CFG_PWRUP_BINARY = 1'b0; + "TRUE" : GTX_CFG_PWRUP_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute GTX_CFG_PWRUP on GTXE1 instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", GTX_CFG_PWRUP); + $finish; + end + endcase + + case (MCOMMA_DETECT) + "FALSE" : MCOMMA_DETECT_BINARY = 1'b0; + "TRUE" : MCOMMA_DETECT_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute MCOMMA_DETECT on GTXE1 instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", MCOMMA_DETECT); + $finish; + end + endcase + + case (PCI_EXPRESS_MODE) + "FALSE" : PCI_EXPRESS_MODE_BINARY = 1'b0; + "TRUE" : PCI_EXPRESS_MODE_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute PCI_EXPRESS_MODE on GTXE1 instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", PCI_EXPRESS_MODE); + $finish; + end + endcase + + case (PCOMMA_DETECT) + "FALSE" : PCOMMA_DETECT_BINARY = 1'b0; + "TRUE" : PCOMMA_DETECT_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute PCOMMA_DETECT on GTXE1 instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", PCOMMA_DETECT); + $finish; + end + endcase + + case (PMA_CAS_CLK_EN) + "FALSE" : PMA_CAS_CLK_EN_BINARY = 1'b0; + "TRUE" : PMA_CAS_CLK_EN_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute PMA_CAS_CLK_EN on GTXE1 instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", PMA_CAS_CLK_EN); + $finish; + end + endcase + + case (RCV_TERM_GND) + "FALSE" : RCV_TERM_GND_BINARY = 1'b0; + "TRUE" : RCV_TERM_GND_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute RCV_TERM_GND on GTXE1 instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", RCV_TERM_GND); + $finish; + end + endcase + + case (RCV_TERM_VTTRX) + "FALSE" : RCV_TERM_VTTRX_BINARY = 1'b0; + "TRUE" : RCV_TERM_VTTRX_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute RCV_TERM_VTTRX on GTXE1 instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", RCV_TERM_VTTRX); + $finish; + end + endcase + + case (RXGEARBOX_USE) + "FALSE" : RXGEARBOX_USE_BINARY = 1'b0; + "TRUE" : RXGEARBOX_USE_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute RXGEARBOX_USE on GTXE1 instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", RXGEARBOX_USE); + $finish; + end + endcase + + case (RXPLL_DIVSEL45_FB) + 5 : RXPLL_DIVSEL45_FB_BINARY = 1'b1; + 4 : RXPLL_DIVSEL45_FB_BINARY = 1'b0; + default : begin + $display("Attribute Syntax Error : The Attribute RXPLL_DIVSEL45_FB on GTXE1 instance %m is set to %d. Legal values for this attribute are 4 to 5.", RXPLL_DIVSEL45_FB, 5); + $finish; + end + endcase + + case (RXPLL_DIVSEL_FB) + 2 : RXPLL_DIVSEL_FB_BINARY = 5'b00000; + 1 : RXPLL_DIVSEL_FB_BINARY = 5'b10000; + 3 : RXPLL_DIVSEL_FB_BINARY = 5'b00001; + 4 : RXPLL_DIVSEL_FB_BINARY = 5'b00010; + 5 : RXPLL_DIVSEL_FB_BINARY = 5'b00011; + 6 : RXPLL_DIVSEL_FB_BINARY = 5'b00101; + 8 : RXPLL_DIVSEL_FB_BINARY = 5'b00110; + 10 : RXPLL_DIVSEL_FB_BINARY = 5'b00111; + 12 : RXPLL_DIVSEL_FB_BINARY = 5'b01101; + 16 : RXPLL_DIVSEL_FB_BINARY = 5'b01110; + 20 : RXPLL_DIVSEL_FB_BINARY = 5'b01111; + default : begin + $display("Attribute Syntax Error : The Attribute RXPLL_DIVSEL_FB on GTXE1 instance %m is set to %d. Legal values for this attribute are 1 to 20.", RXPLL_DIVSEL_FB, 2); + $finish; + end + endcase + + case (RXPLL_DIVSEL_OUT) + 1 : RXPLL_DIVSEL_OUT_BINARY = 2'b00; + 2 : RXPLL_DIVSEL_OUT_BINARY = 2'b01; + 4 : RXPLL_DIVSEL_OUT_BINARY = 2'b10; + default : begin + $display("Attribute Syntax Error : The Attribute RXPLL_DIVSEL_OUT on GTXE1 instance %m is set to %d. Legal values for this attribute are 1 to 4.", RXPLL_DIVSEL_OUT, 1); + $finish; + end + endcase + + case (RXPLL_DIVSEL_REF) + 1 : RXPLL_DIVSEL_REF_BINARY = 5'b10000; + 2 : RXPLL_DIVSEL_REF_BINARY = 5'b00000; + 3 : RXPLL_DIVSEL_REF_BINARY = 5'b00001; + 4 : RXPLL_DIVSEL_REF_BINARY = 5'b00010; + 5 : RXPLL_DIVSEL_REF_BINARY = 5'b00011; + 6 : RXPLL_DIVSEL_REF_BINARY = 5'b00101; + 8 : RXPLL_DIVSEL_REF_BINARY = 5'b00110; + 10 : RXPLL_DIVSEL_REF_BINARY = 5'b00111; + 12 : RXPLL_DIVSEL_REF_BINARY = 5'b01101; + 16 : RXPLL_DIVSEL_REF_BINARY = 5'b01110; + 20 : RXPLL_DIVSEL_REF_BINARY = 5'b01111; + default : begin + $display("Attribute Syntax Error : The Attribute RXPLL_DIVSEL_REF on GTXE1 instance %m is set to %d. Legal values for this attribute are 1 to 20.", RXPLL_DIVSEL_REF, 1); + $finish; + end + endcase + + case (RXRECCLK_CTRL) + "RXRECCLKPCS" : RXRECCLK_CTRL_BINARY = 3'b000; + "RXPLLREFCLK_DIV1" : RXRECCLK_CTRL_BINARY = 3'b011; + "RXPLLREFCLK_DIV2" : RXRECCLK_CTRL_BINARY = 3'b100; + "RXRECCLKPMA_DIV1" : RXRECCLK_CTRL_BINARY = 3'b001; + "RXRECCLKPMA_DIV2" : RXRECCLK_CTRL_BINARY = 3'b010; + default : begin + $display("Attribute Syntax Error : The Attribute RXRECCLK_CTRL on GTXE1 instance %m is set to %s. Legal values for this attribute are RXRECCLKPCS, RXPLLREFCLK_DIV1, RXPLLREFCLK_DIV2, RXRECCLKPMA_DIV1, or RXRECCLKPMA_DIV2.", RXRECCLK_CTRL); + $finish; + end + endcase + + case (RX_BUFFER_USE) + "FALSE" : RX_BUFFER_USE_BINARY = 1'b0; + "TRUE" : RX_BUFFER_USE_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute RX_BUFFER_USE on GTXE1 instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", RX_BUFFER_USE); + $finish; + end + endcase + + case (RX_CLK25_DIVIDER) + 6 : RX_CLK25_DIVIDER_BINARY = 5'b00101; + 1 : RX_CLK25_DIVIDER_BINARY = 5'b00000; + 2 : RX_CLK25_DIVIDER_BINARY = 5'b00001; + 3 : RX_CLK25_DIVIDER_BINARY = 5'b00010; + 4 : RX_CLK25_DIVIDER_BINARY = 5'b00011; + 5 : RX_CLK25_DIVIDER_BINARY = 5'b00100; + 7 : RX_CLK25_DIVIDER_BINARY = 5'b00110; + 8 : RX_CLK25_DIVIDER_BINARY = 5'b00111; + 9 : RX_CLK25_DIVIDER_BINARY = 5'b01000; + 10 : RX_CLK25_DIVIDER_BINARY = 5'b01001; + 11 : RX_CLK25_DIVIDER_BINARY = 5'b01010; + 12 : RX_CLK25_DIVIDER_BINARY = 5'b01011; + 13 : RX_CLK25_DIVIDER_BINARY = 5'b01100; + 14 : RX_CLK25_DIVIDER_BINARY = 5'b01101; + 15 : RX_CLK25_DIVIDER_BINARY = 5'b01110; + 16 : RX_CLK25_DIVIDER_BINARY = 5'b01111; + 17 : RX_CLK25_DIVIDER_BINARY = 5'b10000; + 18 : RX_CLK25_DIVIDER_BINARY = 5'b10001; + 19 : RX_CLK25_DIVIDER_BINARY = 5'b10010; + 20 : RX_CLK25_DIVIDER_BINARY = 5'b10011; + 21 : RX_CLK25_DIVIDER_BINARY = 5'b10100; + 22 : RX_CLK25_DIVIDER_BINARY = 5'b10101; + 23 : RX_CLK25_DIVIDER_BINARY = 5'b10110; + 24 : RX_CLK25_DIVIDER_BINARY = 5'b10111; + 25 : RX_CLK25_DIVIDER_BINARY = 5'b11000; + 26 : RX_CLK25_DIVIDER_BINARY = 5'b11001; + 27 : RX_CLK25_DIVIDER_BINARY = 5'b11010; + 28 : RX_CLK25_DIVIDER_BINARY = 5'b11011; + 29 : RX_CLK25_DIVIDER_BINARY = 5'b11100; + 30 : RX_CLK25_DIVIDER_BINARY = 5'b11101; + 31 : RX_CLK25_DIVIDER_BINARY = 5'b11110; + 32 : RX_CLK25_DIVIDER_BINARY = 5'b11111; + default : begin + $display("Attribute Syntax Error : The Attribute RX_CLK25_DIVIDER on GTXE1 instance %m is set to %d. Legal values for this attribute are 1 to 32.", RX_CLK25_DIVIDER, 6); + $finish; + end + endcase + + case (RX_DATA_WIDTH) + 20 : RX_DATA_WIDTH_BINARY = 3'b011; + 8 : RX_DATA_WIDTH_BINARY = 3'b000; + 10 : RX_DATA_WIDTH_BINARY = 3'b001; + 16 : RX_DATA_WIDTH_BINARY = 3'b010; + 32 : RX_DATA_WIDTH_BINARY = 3'b100; + 40 : RX_DATA_WIDTH_BINARY = 3'b101; + default : begin + $display("Attribute Syntax Error : The Attribute RX_DATA_WIDTH on GTXE1 instance %m is set to %d. Legal values for this attribute are 8 to 40.", RX_DATA_WIDTH, 20); + $finish; + end + endcase + + case (RX_DECODE_SEQ_MATCH) + "FALSE" : RX_DECODE_SEQ_MATCH_BINARY = 1'b0; + "TRUE" : RX_DECODE_SEQ_MATCH_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute RX_DECODE_SEQ_MATCH on GTXE1 instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", RX_DECODE_SEQ_MATCH); + $finish; + end + endcase + + case (RX_EN_IDLE_HOLD_CDR) + "FALSE" : RX_EN_IDLE_HOLD_CDR_BINARY = 1'b0; + "TRUE" : RX_EN_IDLE_HOLD_CDR_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute RX_EN_IDLE_HOLD_CDR on GTXE1 instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", RX_EN_IDLE_HOLD_CDR); + $finish; + end + endcase + + case (RX_EN_IDLE_HOLD_DFE) + "FALSE" : RX_EN_IDLE_HOLD_DFE_BINARY = 1'b0; + "TRUE" : RX_EN_IDLE_HOLD_DFE_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute RX_EN_IDLE_HOLD_DFE on GTXE1 instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", RX_EN_IDLE_HOLD_DFE); + $finish; + end + endcase + + case (RX_EN_IDLE_RESET_BUF) + "FALSE" : RX_EN_IDLE_RESET_BUF_BINARY = 1'b0; + "TRUE" : RX_EN_IDLE_RESET_BUF_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute RX_EN_IDLE_RESET_BUF on GTXE1 instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", RX_EN_IDLE_RESET_BUF); + $finish; + end + endcase + + case (RX_EN_IDLE_RESET_FR) + "FALSE" : RX_EN_IDLE_RESET_FR_BINARY = 1'b0; + "TRUE" : RX_EN_IDLE_RESET_FR_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute RX_EN_IDLE_RESET_FR on GTXE1 instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", RX_EN_IDLE_RESET_FR); + $finish; + end + endcase + + case (RX_EN_IDLE_RESET_PH) + "FALSE" : RX_EN_IDLE_RESET_PH_BINARY = 1'b0; + "TRUE" : RX_EN_IDLE_RESET_PH_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute RX_EN_IDLE_RESET_PH on GTXE1 instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", RX_EN_IDLE_RESET_PH); + $finish; + end + endcase + + case (RX_EN_MODE_RESET_BUF) + "FALSE" : RX_EN_MODE_RESET_BUF_BINARY = 1'b0; + "TRUE" : RX_EN_MODE_RESET_BUF_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute RX_EN_MODE_RESET_BUF on GTXE1 instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", RX_EN_MODE_RESET_BUF); + $finish; + end + endcase + + case (RX_EN_RATE_RESET_BUF) + "FALSE" : RX_EN_RATE_RESET_BUF_BINARY = 1'b0; + "TRUE" : RX_EN_RATE_RESET_BUF_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute RX_EN_RATE_RESET_BUF on GTXE1 instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", RX_EN_RATE_RESET_BUF); + $finish; + end + endcase + + case (RX_EN_REALIGN_RESET_BUF) + "FALSE" : RX_EN_REALIGN_RESET_BUF_BINARY = 1'b0; + "TRUE" : RX_EN_REALIGN_RESET_BUF_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute RX_EN_REALIGN_RESET_BUF on GTXE1 instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", RX_EN_REALIGN_RESET_BUF); + $finish; + end + endcase + + case (RX_EN_REALIGN_RESET_BUF2) + "FALSE" : RX_EN_REALIGN_RESET_BUF2_BINARY = 1'b0; + "TRUE" : RX_EN_REALIGN_RESET_BUF2_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute RX_EN_REALIGN_RESET_BUF2 on GTXE1 instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", RX_EN_REALIGN_RESET_BUF2); + $finish; + end + endcase + + case (RX_FIFO_ADDR_MODE) + "FULL" : RX_FIFO_ADDR_MODE_BINARY = 1'b0; + "FAST" : RX_FIFO_ADDR_MODE_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute RX_FIFO_ADDR_MODE on GTXE1 instance %m is set to %s. Legal values for this attribute are FULL, or FAST.", RX_FIFO_ADDR_MODE); + $finish; + end + endcase + + case (RX_LOSS_OF_SYNC_FSM) + "FALSE" : RX_LOSS_OF_SYNC_FSM_BINARY = 1'b0; + "TRUE" : RX_LOSS_OF_SYNC_FSM_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute RX_LOSS_OF_SYNC_FSM on GTXE1 instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", RX_LOSS_OF_SYNC_FSM); + $finish; + end + endcase + + case (RX_LOS_INVALID_INCR) + 1 : RX_LOS_INVALID_INCR_BINARY = 3'b000; + 2 : RX_LOS_INVALID_INCR_BINARY = 3'b001; + 4 : RX_LOS_INVALID_INCR_BINARY = 3'b010; + 8 : RX_LOS_INVALID_INCR_BINARY = 3'b011; + 16 : RX_LOS_INVALID_INCR_BINARY = 3'b100; + 32 : RX_LOS_INVALID_INCR_BINARY = 3'b101; + 64 : RX_LOS_INVALID_INCR_BINARY = 3'b110; + 128 : RX_LOS_INVALID_INCR_BINARY = 3'b111; + default : begin + $display("Attribute Syntax Error : The Attribute RX_LOS_INVALID_INCR on GTXE1 instance %m is set to %d. Legal values for this attribute are 1 to 128.", RX_LOS_INVALID_INCR, 1); + $finish; + end + endcase + + case (RX_LOS_THRESHOLD) + 4 : RX_LOS_THRESHOLD_BINARY = 3'b000; + 8 : RX_LOS_THRESHOLD_BINARY = 3'b001; + 16 : RX_LOS_THRESHOLD_BINARY = 3'b010; + 32 : RX_LOS_THRESHOLD_BINARY = 3'b011; + 64 : RX_LOS_THRESHOLD_BINARY = 3'b100; + 128 : RX_LOS_THRESHOLD_BINARY = 3'b101; + 256 : RX_LOS_THRESHOLD_BINARY = 3'b110; + 512 : RX_LOS_THRESHOLD_BINARY = 3'b111; + default : begin + $display("Attribute Syntax Error : The Attribute RX_LOS_THRESHOLD on GTXE1 instance %m is set to %d. Legal values for this attribute are 4 to 512.", RX_LOS_THRESHOLD, 4); + $finish; + end + endcase + + case (RX_OVERSAMPLE_MODE) + "FALSE" : RX_OVERSAMPLE_MODE_BINARY = 1'b0; + "TRUE" : RX_OVERSAMPLE_MODE_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute RX_OVERSAMPLE_MODE on GTXE1 instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", RX_OVERSAMPLE_MODE); + $finish; + end + endcase + + case (RX_SLIDE_MODE) + "OFF" : RX_SLIDE_MODE_BINARY = 2'b00; + "AUTO" : RX_SLIDE_MODE_BINARY = 2'b01; + "PCS" : RX_SLIDE_MODE_BINARY = 2'b10; + "PMA" : RX_SLIDE_MODE_BINARY = 2'b11; + default : begin + $display("Attribute Syntax Error : The Attribute RX_SLIDE_MODE on GTXE1 instance %m is set to %s. Legal values for this attribute are OFF, AUTO, PCS, or PMA.", RX_SLIDE_MODE); + $finish; + end + endcase + + case (RX_XCLK_SEL) + "RXREC" : RX_XCLK_SEL_BINARY = 1'b0; + "RXUSR" : RX_XCLK_SEL_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute RX_XCLK_SEL on GTXE1 instance %m is set to %s. Legal values for this attribute are RXREC, or RXUSR.", RX_XCLK_SEL); + $finish; + end + endcase + + case (SHOW_REALIGN_COMMA) + "FALSE" : SHOW_REALIGN_COMMA_BINARY = 1'b0; + "TRUE" : SHOW_REALIGN_COMMA_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute SHOW_REALIGN_COMMA on GTXE1 instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", SHOW_REALIGN_COMMA); + $finish; + end + endcase + + case (SIM_GTXRESET_SPEEDUP) + 1 : SIM_GTXRESET_SPEEDUP_BINARY = 1; + 0 : SIM_GTXRESET_SPEEDUP_BINARY = 0; + default : begin + $display("Attribute Syntax Error : The Attribute SIM_GTXRESET_SPEEDUP on GTXE1 instance %m is set to %d. Legal values for this attribute are 0 to 1.", SIM_GTXRESET_SPEEDUP, 1); + $finish; + end + endcase + + case (SIM_RECEIVER_DETECT_PASS) + "FALSE" : SIM_RECEIVER_DETECT_PASS_BINARY = 1'b0; + "TRUE" : SIM_RECEIVER_DETECT_PASS_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute SIM_RECEIVER_DETECT_PASS on GTXE1 instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", SIM_RECEIVER_DETECT_PASS); + $finish; + end + endcase + + case (TERMINATION_OVRD) + "FALSE" : TERMINATION_OVRD_BINARY = 1'b0; + "TRUE" : TERMINATION_OVRD_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute TERMINATION_OVRD on GTXE1 instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", TERMINATION_OVRD); + $finish; + end + endcase + + case (TXDRIVE_LOOPBACK_HIZ) + "FALSE" : TXDRIVE_LOOPBACK_HIZ_BINARY = 1'b0; + "TRUE" : TXDRIVE_LOOPBACK_HIZ_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute TXDRIVE_LOOPBACK_HIZ on GTXE1 instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", TXDRIVE_LOOPBACK_HIZ); + $finish; + end + endcase + + case (TXDRIVE_LOOPBACK_PD) + "FALSE" : TXDRIVE_LOOPBACK_PD_BINARY = 1'b0; + "TRUE" : TXDRIVE_LOOPBACK_PD_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute TXDRIVE_LOOPBACK_PD on GTXE1 instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", TXDRIVE_LOOPBACK_PD); + $finish; + end + endcase + + case (TXGEARBOX_USE) + "FALSE" : TXGEARBOX_USE_BINARY = 1'b0; + "TRUE" : TXGEARBOX_USE_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute TXGEARBOX_USE on GTXE1 instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", TXGEARBOX_USE); + $finish; + end + endcase + + case (TXOUTCLK_CTRL) + "TXOUTCLKPCS" : TXOUTCLK_CTRL_BINARY = 3'b000; + "TXOUTCLKPMA_DIV1" : TXOUTCLK_CTRL_BINARY = 3'b001; + "TXOUTCLKPMA_DIV2" : TXOUTCLK_CTRL_BINARY = 3'b010; + "TXPLLREFCLK_DIV1" : TXOUTCLK_CTRL_BINARY = 3'b011; + "TXPLLREFCLK_DIV2" : TXOUTCLK_CTRL_BINARY = 3'b100; + default : begin + $display("Attribute Syntax Error : The Attribute TXOUTCLK_CTRL on GTXE1 instance %m is set to %s. Legal values for this attribute are TXOUTCLKPCS, TXOUTCLKPMA_DIV1, TXOUTCLKPMA_DIV2, TXPLLREFCLK_DIV1, or TXPLLREFCLK_DIV2.", TXOUTCLK_CTRL); + $finish; + end + endcase + + case (TXPLL_DIVSEL45_FB) + 5 : TXPLL_DIVSEL45_FB_BINARY = 1'b1; + 4 : TXPLL_DIVSEL45_FB_BINARY = 1'b0; + default : begin + $display("Attribute Syntax Error : The Attribute TXPLL_DIVSEL45_FB on GTXE1 instance %m is set to %d. Legal values for this attribute are 4 to 5.", TXPLL_DIVSEL45_FB, 5); + $finish; + end + endcase + + case (TXPLL_DIVSEL_FB) + 2 : TXPLL_DIVSEL_FB_BINARY = 5'b00000; + 1 : TXPLL_DIVSEL_FB_BINARY = 5'b10000; + 3 : TXPLL_DIVSEL_FB_BINARY = 5'b00001; + 4 : TXPLL_DIVSEL_FB_BINARY = 5'b00010; + 5 : TXPLL_DIVSEL_FB_BINARY = 5'b00011; + 6 : TXPLL_DIVSEL_FB_BINARY = 5'b00101; + 8 : TXPLL_DIVSEL_FB_BINARY = 5'b00110; + 10 : TXPLL_DIVSEL_FB_BINARY = 5'b00111; + 12 : TXPLL_DIVSEL_FB_BINARY = 5'b01101; + 16 : TXPLL_DIVSEL_FB_BINARY = 5'b01110; + 20 : TXPLL_DIVSEL_FB_BINARY = 5'b01111; + default : begin + $display("Attribute Syntax Error : The Attribute TXPLL_DIVSEL_FB on GTXE1 instance %m is set to %d. Legal values for this attribute are 1 to 20.", TXPLL_DIVSEL_FB, 2); + $finish; + end + endcase + + case (TXPLL_DIVSEL_OUT) + 1 : TXPLL_DIVSEL_OUT_BINARY = 2'b00; + 2 : TXPLL_DIVSEL_OUT_BINARY = 2'b01; + 4 : TXPLL_DIVSEL_OUT_BINARY = 2'b10; + default : begin + $display("Attribute Syntax Error : The Attribute TXPLL_DIVSEL_OUT on GTXE1 instance %m is set to %d. Legal values for this attribute are 1 to 4.", TXPLL_DIVSEL_OUT, 1); + $finish; + end + endcase + + case (TXPLL_DIVSEL_REF) + 1 : TXPLL_DIVSEL_REF_BINARY = 5'b10000; + 2 : TXPLL_DIVSEL_REF_BINARY = 5'b00000; + 3 : TXPLL_DIVSEL_REF_BINARY = 5'b00001; + 4 : TXPLL_DIVSEL_REF_BINARY = 5'b00010; + 5 : TXPLL_DIVSEL_REF_BINARY = 5'b00011; + 6 : TXPLL_DIVSEL_REF_BINARY = 5'b00101; + 8 : TXPLL_DIVSEL_REF_BINARY = 5'b00110; + 10 : TXPLL_DIVSEL_REF_BINARY = 5'b00111; + 12 : TXPLL_DIVSEL_REF_BINARY = 5'b01101; + 16 : TXPLL_DIVSEL_REF_BINARY = 5'b01110; + 20 : TXPLL_DIVSEL_REF_BINARY = 5'b01111; + default : begin + $display("Attribute Syntax Error : The Attribute TXPLL_DIVSEL_REF on GTXE1 instance %m is set to %d. Legal values for this attribute are 1 to 20.", TXPLL_DIVSEL_REF, 1); + $finish; + end + endcase + + case (TX_BUFFER_USE) + "FALSE" : TX_BUFFER_USE_BINARY = 1'b0; + "TRUE" : TX_BUFFER_USE_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute TX_BUFFER_USE on GTXE1 instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", TX_BUFFER_USE); + $finish; + end + endcase + + case (TX_CLK25_DIVIDER) + 6 : TX_CLK25_DIVIDER_BINARY = 5'b00101; + 1 : TX_CLK25_DIVIDER_BINARY = 5'b00000; + 2 : TX_CLK25_DIVIDER_BINARY = 5'b00001; + 3 : TX_CLK25_DIVIDER_BINARY = 5'b00010; + 4 : TX_CLK25_DIVIDER_BINARY = 5'b00011; + 5 : TX_CLK25_DIVIDER_BINARY = 5'b00100; + 7 : TX_CLK25_DIVIDER_BINARY = 5'b00110; + 8 : TX_CLK25_DIVIDER_BINARY = 5'b00111; + 9 : TX_CLK25_DIVIDER_BINARY = 5'b01000; + 10 : TX_CLK25_DIVIDER_BINARY = 5'b01001; + 11 : TX_CLK25_DIVIDER_BINARY = 5'b01010; + 12 : TX_CLK25_DIVIDER_BINARY = 5'b01011; + 13 : TX_CLK25_DIVIDER_BINARY = 5'b01100; + 14 : TX_CLK25_DIVIDER_BINARY = 5'b01101; + 15 : TX_CLK25_DIVIDER_BINARY = 5'b01110; + 16 : TX_CLK25_DIVIDER_BINARY = 5'b01111; + 17 : TX_CLK25_DIVIDER_BINARY = 5'b10000; + 18 : TX_CLK25_DIVIDER_BINARY = 5'b10001; + 19 : TX_CLK25_DIVIDER_BINARY = 5'b10010; + 20 : TX_CLK25_DIVIDER_BINARY = 5'b10011; + 21 : TX_CLK25_DIVIDER_BINARY = 5'b10100; + 22 : TX_CLK25_DIVIDER_BINARY = 5'b10101; + 23 : TX_CLK25_DIVIDER_BINARY = 5'b10110; + 24 : TX_CLK25_DIVIDER_BINARY = 5'b10111; + 25 : TX_CLK25_DIVIDER_BINARY = 5'b11000; + 26 : TX_CLK25_DIVIDER_BINARY = 5'b11001; + 27 : TX_CLK25_DIVIDER_BINARY = 5'b11010; + 28 : TX_CLK25_DIVIDER_BINARY = 5'b11011; + 29 : TX_CLK25_DIVIDER_BINARY = 5'b11100; + 30 : TX_CLK25_DIVIDER_BINARY = 5'b11101; + 31 : TX_CLK25_DIVIDER_BINARY = 5'b11110; + 32 : TX_CLK25_DIVIDER_BINARY = 5'b11111; + default : begin + $display("Attribute Syntax Error : The Attribute TX_CLK25_DIVIDER on GTXE1 instance %m is set to %d. Legal values for this attribute are 1 to 32.", TX_CLK25_DIVIDER, 6); + $finish; + end + endcase + + case (TX_CLK_SOURCE) + "RXPLL" : TX_CLK_SOURCE_BINARY = 1'b1; + "TXPLL" : TX_CLK_SOURCE_BINARY = 1'b0; + default : begin + $display("Attribute Syntax Error : The Attribute TX_CLK_SOURCE on GTXE1 instance %m is set to %s. Legal values for this attribute are RXPLL, or TXPLL.", TX_CLK_SOURCE); + $finish; + end + endcase + + case (TX_DATA_WIDTH) + 20 : TX_DATA_WIDTH_BINARY = 3'b011; + 8 : TX_DATA_WIDTH_BINARY = 3'b000; + 10 : TX_DATA_WIDTH_BINARY = 3'b001; + 16 : TX_DATA_WIDTH_BINARY = 3'b010; + 32 : TX_DATA_WIDTH_BINARY = 3'b100; + 40 : TX_DATA_WIDTH_BINARY = 3'b101; + default : begin + $display("Attribute Syntax Error : The Attribute TX_DATA_WIDTH on GTXE1 instance %m is set to %d. Legal values for this attribute are 8 to 40.", TX_DATA_WIDTH, 20); + $finish; + end + endcase + + case (TX_DRIVE_MODE) + "DIRECT" : TX_DRIVE_MODE_BINARY = 1'b0; + "PIPE" : TX_DRIVE_MODE_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute TX_DRIVE_MODE on GTXE1 instance %m is set to %s. Legal values for this attribute are DIRECT, or PIPE.", TX_DRIVE_MODE); + $finish; + end + endcase + + case (TX_EN_RATE_RESET_BUF) + "FALSE" : TX_EN_RATE_RESET_BUF_BINARY = 1'b0; + "TRUE" : TX_EN_RATE_RESET_BUF_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute TX_EN_RATE_RESET_BUF on GTXE1 instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", TX_EN_RATE_RESET_BUF); + $finish; + end + endcase + + case (TX_OVERSAMPLE_MODE) + "FALSE" : TX_OVERSAMPLE_MODE_BINARY = 1'b0; + "TRUE" : TX_OVERSAMPLE_MODE_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute TX_OVERSAMPLE_MODE on GTXE1 instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", TX_OVERSAMPLE_MODE); + $finish; + end + endcase + + case (TX_XCLK_SEL) + "TXUSR" : TX_XCLK_SEL_BINARY = 1'b1; + "TXOUT" : TX_XCLK_SEL_BINARY = 1'b0; + default : begin + $display("Attribute Syntax Error : The Attribute TX_XCLK_SEL on GTXE1 instance %m is set to %s. Legal values for this attribute are TXUSR, or TXOUT.", TX_XCLK_SEL); + $finish; + end + endcase + + if ((BGTEST_CFG >= 0) && (BGTEST_CFG <= 3)) + BGTEST_CFG_BINARY = BGTEST_CFG; + else begin + $display("Attribute Syntax Error : The Attribute BGTEST_CFG on GTXE1 instance %m is set to %d. Legal values for this attribute are 0 to 3.", BGTEST_CFG); + $finish; + end + + if ((CDR_PH_ADJ_TIME >= 0) && (CDR_PH_ADJ_TIME <= 31)) + CDR_PH_ADJ_TIME_BINARY = CDR_PH_ADJ_TIME; + else begin + $display("Attribute Syntax Error : The Attribute CDR_PH_ADJ_TIME on GTXE1 instance %m is set to %d. Legal values for this attribute are 0 to 31.", CDR_PH_ADJ_TIME); + $finish; + end + + if ((CHAN_BOND_1_MAX_SKEW >= 1) && (CHAN_BOND_1_MAX_SKEW <= 14)) + CHAN_BOND_1_MAX_SKEW_BINARY = CHAN_BOND_1_MAX_SKEW; + else begin + $display("Attribute Syntax Error : The Attribute CHAN_BOND_1_MAX_SKEW on GTXE1 instance %m is set to %d. Legal values for this attribute are 1 to 14.", CHAN_BOND_1_MAX_SKEW); + $finish; + end + + if ((CHAN_BOND_2_MAX_SKEW >= 1) && (CHAN_BOND_2_MAX_SKEW <= 14)) + CHAN_BOND_2_MAX_SKEW_BINARY = CHAN_BOND_2_MAX_SKEW; + else begin + $display("Attribute Syntax Error : The Attribute CHAN_BOND_2_MAX_SKEW on GTXE1 instance %m is set to %d. Legal values for this attribute are 1 to 14.", CHAN_BOND_2_MAX_SKEW); + $finish; + end + + if ((CHAN_BOND_SEQ_1_1 >= 0) && (CHAN_BOND_SEQ_1_1 <= 1023)) + CHAN_BOND_SEQ_1_1_BINARY = CHAN_BOND_SEQ_1_1; + else begin + $display("Attribute Syntax Error : The Attribute CHAN_BOND_SEQ_1_1 on GTXE1 instance %m is set to %d. Legal values for this attribute are 0 to 1023.", CHAN_BOND_SEQ_1_1); + $finish; + end + + if ((CHAN_BOND_SEQ_1_2 >= 0) && (CHAN_BOND_SEQ_1_2 <= 1023)) + CHAN_BOND_SEQ_1_2_BINARY = CHAN_BOND_SEQ_1_2; + else begin + $display("Attribute Syntax Error : The Attribute CHAN_BOND_SEQ_1_2 on GTXE1 instance %m is set to %d. Legal values for this attribute are 0 to 1023.", CHAN_BOND_SEQ_1_2); + $finish; + end + + if ((CHAN_BOND_SEQ_1_3 >= 0) && (CHAN_BOND_SEQ_1_3 <= 1023)) + CHAN_BOND_SEQ_1_3_BINARY = CHAN_BOND_SEQ_1_3; + else begin + $display("Attribute Syntax Error : The Attribute CHAN_BOND_SEQ_1_3 on GTXE1 instance %m is set to %d. Legal values for this attribute are 0 to 1023.", CHAN_BOND_SEQ_1_3); + $finish; + end + + if ((CHAN_BOND_SEQ_1_4 >= 0) && (CHAN_BOND_SEQ_1_4 <= 1023)) + CHAN_BOND_SEQ_1_4_BINARY = CHAN_BOND_SEQ_1_4; + else begin + $display("Attribute Syntax Error : The Attribute CHAN_BOND_SEQ_1_4 on GTXE1 instance %m is set to %d. Legal values for this attribute are 0 to 1023.", CHAN_BOND_SEQ_1_4); + $finish; + end + + if ((CHAN_BOND_SEQ_1_ENABLE >= 0) && (CHAN_BOND_SEQ_1_ENABLE <= 15)) + CHAN_BOND_SEQ_1_ENABLE_BINARY = CHAN_BOND_SEQ_1_ENABLE; + else begin + $display("Attribute Syntax Error : The Attribute CHAN_BOND_SEQ_1_ENABLE on GTXE1 instance %m is set to %d. Legal values for this attribute are 0 to 15.", CHAN_BOND_SEQ_1_ENABLE); + $finish; + end + + if ((CHAN_BOND_SEQ_2_1 >= 0) && (CHAN_BOND_SEQ_2_1 <= 1023)) + CHAN_BOND_SEQ_2_1_BINARY = CHAN_BOND_SEQ_2_1; + else begin + $display("Attribute Syntax Error : The Attribute CHAN_BOND_SEQ_2_1 on GTXE1 instance %m is set to %d. Legal values for this attribute are 0 to 1023.", CHAN_BOND_SEQ_2_1); + $finish; + end + + if ((CHAN_BOND_SEQ_2_2 >= 0) && (CHAN_BOND_SEQ_2_2 <= 1023)) + CHAN_BOND_SEQ_2_2_BINARY = CHAN_BOND_SEQ_2_2; + else begin + $display("Attribute Syntax Error : The Attribute CHAN_BOND_SEQ_2_2 on GTXE1 instance %m is set to %d. Legal values for this attribute are 0 to 1023.", CHAN_BOND_SEQ_2_2); + $finish; + end + + if ((CHAN_BOND_SEQ_2_3 >= 0) && (CHAN_BOND_SEQ_2_3 <= 1023)) + CHAN_BOND_SEQ_2_3_BINARY = CHAN_BOND_SEQ_2_3; + else begin + $display("Attribute Syntax Error : The Attribute CHAN_BOND_SEQ_2_3 on GTXE1 instance %m is set to %d. Legal values for this attribute are 0 to 1023.", CHAN_BOND_SEQ_2_3); + $finish; + end + + if ((CHAN_BOND_SEQ_2_4 >= 0) && (CHAN_BOND_SEQ_2_4 <= 1023)) + CHAN_BOND_SEQ_2_4_BINARY = CHAN_BOND_SEQ_2_4; + else begin + $display("Attribute Syntax Error : The Attribute CHAN_BOND_SEQ_2_4 on GTXE1 instance %m is set to %d. Legal values for this attribute are 0 to 1023.", CHAN_BOND_SEQ_2_4); + $finish; + end + + if ((CHAN_BOND_SEQ_2_CFG >= 0) && (CHAN_BOND_SEQ_2_CFG <= 31)) + CHAN_BOND_SEQ_2_CFG_BINARY = CHAN_BOND_SEQ_2_CFG; + else begin + $display("Attribute Syntax Error : The Attribute CHAN_BOND_SEQ_2_CFG on GTXE1 instance %m is set to %d. Legal values for this attribute are 0 to 31.", CHAN_BOND_SEQ_2_CFG); + $finish; + end + + if ((CHAN_BOND_SEQ_2_ENABLE >= 0) && (CHAN_BOND_SEQ_2_ENABLE <= 15)) + CHAN_BOND_SEQ_2_ENABLE_BINARY = CHAN_BOND_SEQ_2_ENABLE; + else begin + $display("Attribute Syntax Error : The Attribute CHAN_BOND_SEQ_2_ENABLE on GTXE1 instance %m is set to %d. Legal values for this attribute are 0 to 15.", CHAN_BOND_SEQ_2_ENABLE); + $finish; + end + + if ((CLK_COR_MAX_LAT >= 3) && (CLK_COR_MAX_LAT <= 48)) + CLK_COR_MAX_LAT_BINARY = CLK_COR_MAX_LAT; + else begin + $display("Attribute Syntax Error : The Attribute CLK_COR_MAX_LAT on GTXE1 instance %m is set to %d. Legal values for this attribute are 3 to 48.", CLK_COR_MAX_LAT); + $finish; + end + + if ((CLK_COR_MIN_LAT >= 3) && (CLK_COR_MIN_LAT <= 48)) + CLK_COR_MIN_LAT_BINARY = CLK_COR_MIN_LAT; + else begin + $display("Attribute Syntax Error : The Attribute CLK_COR_MIN_LAT on GTXE1 instance %m is set to %d. Legal values for this attribute are 3 to 48.", CLK_COR_MIN_LAT); + $finish; + end + + if ((CLK_COR_REPEAT_WAIT >= 0) && (CLK_COR_REPEAT_WAIT <= 31)) + CLK_COR_REPEAT_WAIT_BINARY = CLK_COR_REPEAT_WAIT; + else begin + $display("Attribute Syntax Error : The Attribute CLK_COR_REPEAT_WAIT on GTXE1 instance %m is set to %d. Legal values for this attribute are 0 to 31.", CLK_COR_REPEAT_WAIT); + $finish; + end + + if ((CLK_COR_SEQ_1_1 >= 0) && (CLK_COR_SEQ_1_1 <= 1023)) + CLK_COR_SEQ_1_1_BINARY = CLK_COR_SEQ_1_1; + else begin + $display("Attribute Syntax Error : The Attribute CLK_COR_SEQ_1_1 on GTXE1 instance %m is set to %d. Legal values for this attribute are 0 to 1023.", CLK_COR_SEQ_1_1); + $finish; + end + + if ((CLK_COR_SEQ_1_2 >= 0) && (CLK_COR_SEQ_1_2 <= 1023)) + CLK_COR_SEQ_1_2_BINARY = CLK_COR_SEQ_1_2; + else begin + $display("Attribute Syntax Error : The Attribute CLK_COR_SEQ_1_2 on GTXE1 instance %m is set to %d. Legal values for this attribute are 0 to 1023.", CLK_COR_SEQ_1_2); + $finish; + end + + if ((CLK_COR_SEQ_1_3 >= 0) && (CLK_COR_SEQ_1_3 <= 1023)) + CLK_COR_SEQ_1_3_BINARY = CLK_COR_SEQ_1_3; + else begin + $display("Attribute Syntax Error : The Attribute CLK_COR_SEQ_1_3 on GTXE1 instance %m is set to %d. Legal values for this attribute are 0 to 1023.", CLK_COR_SEQ_1_3); + $finish; + end + + if ((CLK_COR_SEQ_1_4 >= 0) && (CLK_COR_SEQ_1_4 <= 1023)) + CLK_COR_SEQ_1_4_BINARY = CLK_COR_SEQ_1_4; + else begin + $display("Attribute Syntax Error : The Attribute CLK_COR_SEQ_1_4 on GTXE1 instance %m is set to %d. Legal values for this attribute are 0 to 1023.", CLK_COR_SEQ_1_4); + $finish; + end + + if ((CLK_COR_SEQ_1_ENABLE >= 0) && (CLK_COR_SEQ_1_ENABLE <= 15)) + CLK_COR_SEQ_1_ENABLE_BINARY = CLK_COR_SEQ_1_ENABLE; + else begin + $display("Attribute Syntax Error : The Attribute CLK_COR_SEQ_1_ENABLE on GTXE1 instance %m is set to %d. Legal values for this attribute are 0 to 15.", CLK_COR_SEQ_1_ENABLE); + $finish; + end + + if ((CLK_COR_SEQ_2_1 >= 0) && (CLK_COR_SEQ_2_1 <= 1023)) + CLK_COR_SEQ_2_1_BINARY = CLK_COR_SEQ_2_1; + else begin + $display("Attribute Syntax Error : The Attribute CLK_COR_SEQ_2_1 on GTXE1 instance %m is set to %d. Legal values for this attribute are 0 to 1023.", CLK_COR_SEQ_2_1); + $finish; + end + + if ((CLK_COR_SEQ_2_2 >= 0) && (CLK_COR_SEQ_2_2 <= 1023)) + CLK_COR_SEQ_2_2_BINARY = CLK_COR_SEQ_2_2; + else begin + $display("Attribute Syntax Error : The Attribute CLK_COR_SEQ_2_2 on GTXE1 instance %m is set to %d. Legal values for this attribute are 0 to 1023.", CLK_COR_SEQ_2_2); + $finish; + end + + if ((CLK_COR_SEQ_2_3 >= 0) && (CLK_COR_SEQ_2_3 <= 1023)) + CLK_COR_SEQ_2_3_BINARY = CLK_COR_SEQ_2_3; + else begin + $display("Attribute Syntax Error : The Attribute CLK_COR_SEQ_2_3 on GTXE1 instance %m is set to %d. Legal values for this attribute are 0 to 1023.", CLK_COR_SEQ_2_3); + $finish; + end + + if ((CLK_COR_SEQ_2_4 >= 0) && (CLK_COR_SEQ_2_4 <= 1023)) + CLK_COR_SEQ_2_4_BINARY = CLK_COR_SEQ_2_4; + else begin + $display("Attribute Syntax Error : The Attribute CLK_COR_SEQ_2_4 on GTXE1 instance %m is set to %d. Legal values for this attribute are 0 to 1023.", CLK_COR_SEQ_2_4); + $finish; + end + + if ((CLK_COR_SEQ_2_ENABLE >= 0) && (CLK_COR_SEQ_2_ENABLE <= 15)) + CLK_COR_SEQ_2_ENABLE_BINARY = CLK_COR_SEQ_2_ENABLE; + else begin + $display("Attribute Syntax Error : The Attribute CLK_COR_SEQ_2_ENABLE on GTXE1 instance %m is set to %d. Legal values for this attribute are 0 to 15.", CLK_COR_SEQ_2_ENABLE); + $finish; + end + + if ((CM_TRIM >= 0) && (CM_TRIM <= 3)) + CM_TRIM_BINARY = CM_TRIM; + else begin + $display("Attribute Syntax Error : The Attribute CM_TRIM on GTXE1 instance %m is set to %d. Legal values for this attribute are 0 to 3.", CM_TRIM); + $finish; + end + + if ((COMMA_10B_ENABLE >= 0) && (COMMA_10B_ENABLE <= 1023)) + COMMA_10B_ENABLE_BINARY = COMMA_10B_ENABLE; + else begin + $display("Attribute Syntax Error : The Attribute COMMA_10B_ENABLE on GTXE1 instance %m is set to %d. Legal values for this attribute are 0 to 1023.", COMMA_10B_ENABLE); + $finish; + end + + if ((COM_BURST_VAL >= 0) && (COM_BURST_VAL <= 15)) + COM_BURST_VAL_BINARY = COM_BURST_VAL; + else begin + $display("Attribute Syntax Error : The Attribute COM_BURST_VAL on GTXE1 instance %m is set to %d. Legal values for this attribute are 0 to 15.", COM_BURST_VAL); + $finish; + end + + if ((DFE_CAL_TIME >= 0) && (DFE_CAL_TIME <= 31)) + DFE_CAL_TIME_BINARY = DFE_CAL_TIME; + else begin + $display("Attribute Syntax Error : The Attribute DFE_CAL_TIME on GTXE1 instance %m is set to %d. Legal values for this attribute are 0 to 31.", DFE_CAL_TIME); + $finish; + end + + if ((DFE_CFG >= 0) && (DFE_CFG <= 255)) + DFE_CFG_BINARY = DFE_CFG; + else begin + $display("Attribute Syntax Error : The Attribute DFE_CFG on GTXE1 instance %m is set to %d. Legal values for this attribute are 0 to 255.", DFE_CFG); + $finish; + end + + if ((GEARBOX_ENDEC >= 0) && (GEARBOX_ENDEC <= 7)) + GEARBOX_ENDEC_BINARY = GEARBOX_ENDEC; + else begin + $display("Attribute Syntax Error : The Attribute GEARBOX_ENDEC on GTXE1 instance %m is set to %d. Legal values for this attribute are 0 to 7.", GEARBOX_ENDEC); + $finish; + end + + if ((MCOMMA_10B_VALUE >= 0) && (MCOMMA_10B_VALUE <= 1023)) + MCOMMA_10B_VALUE_BINARY = MCOMMA_10B_VALUE; + else begin + $display("Attribute Syntax Error : The Attribute MCOMMA_10B_VALUE on GTXE1 instance %m is set to %d. Legal values for this attribute are 0 to 1023.", MCOMMA_10B_VALUE); + $finish; + end + + if ((OOBDETECT_THRESHOLD >= 0) && (OOBDETECT_THRESHOLD <= 7)) + OOBDETECT_THRESHOLD_BINARY = OOBDETECT_THRESHOLD; + else begin + $display("Attribute Syntax Error : The Attribute OOBDETECT_THRESHOLD on GTXE1 instance %m is set to %d. Legal values for this attribute are 0 to 7.", OOBDETECT_THRESHOLD); + $finish; + end + + if ((PCOMMA_10B_VALUE >= 0) && (PCOMMA_10B_VALUE <= 1023)) + PCOMMA_10B_VALUE_BINARY = PCOMMA_10B_VALUE; + else begin + $display("Attribute Syntax Error : The Attribute PCOMMA_10B_VALUE on GTXE1 instance %m is set to %d. Legal values for this attribute are 0 to 1023.", PCOMMA_10B_VALUE); + $finish; + end + + if ((POWER_SAVE >= 0) && (POWER_SAVE <= 1023)) + POWER_SAVE_BINARY = POWER_SAVE; + else begin + $display("Attribute Syntax Error : The Attribute POWER_SAVE on GTXE1 instance %m is set to %d. Legal values for this attribute are 0 to 1023.", POWER_SAVE); + $finish; + end + + if ((RXPLL_LKDET_CFG >= 0) && (RXPLL_LKDET_CFG <= 7)) + RXPLL_LKDET_CFG_BINARY = RXPLL_LKDET_CFG; + else begin + $display("Attribute Syntax Error : The Attribute RXPLL_LKDET_CFG on GTXE1 instance %m is set to %d. Legal values for this attribute are 0 to 7.", RXPLL_LKDET_CFG); + $finish; + end + + if ((RXPRBSERR_LOOPBACK >= 0) && (RXPRBSERR_LOOPBACK <= 1)) + RXPRBSERR_LOOPBACK_BINARY = RXPRBSERR_LOOPBACK; + else begin + $display("Attribute Syntax Error : The Attribute RXPRBSERR_LOOPBACK on GTXE1 instance %m is set to %d. Legal values for this attribute are 0 to 1.", RXPRBSERR_LOOPBACK); + $finish; + end + + if ((RXRECCLK_DLY >= 0) && (RXRECCLK_DLY <= 1023)) + RXRECCLK_DLY_BINARY = RXRECCLK_DLY; + else begin + $display("Attribute Syntax Error : The Attribute RXRECCLK_DLY on GTXE1 instance %m is set to %d. Legal values for this attribute are 0 to 1023.", RXRECCLK_DLY); + $finish; + end + + if ((RX_DLYALIGN_CTRINC >= 0) && (RX_DLYALIGN_CTRINC <= 15)) + RX_DLYALIGN_CTRINC_BINARY = RX_DLYALIGN_CTRINC; + else begin + $display("Attribute Syntax Error : The Attribute RX_DLYALIGN_CTRINC on GTXE1 instance %m is set to %d. Legal values for this attribute are 0 to 15.", RX_DLYALIGN_CTRINC); + $finish; + end + + if ((RX_DLYALIGN_EDGESET >= 0) && (RX_DLYALIGN_EDGESET <= 31)) + RX_DLYALIGN_EDGESET_BINARY = RX_DLYALIGN_EDGESET; + else begin + $display("Attribute Syntax Error : The Attribute RX_DLYALIGN_EDGESET on GTXE1 instance %m is set to %d. Legal values for this attribute are 0 to 31.", RX_DLYALIGN_EDGESET); + $finish; + end + + if ((RX_DLYALIGN_LPFINC >= 0) && (RX_DLYALIGN_LPFINC <= 15)) + RX_DLYALIGN_LPFINC_BINARY = RX_DLYALIGN_LPFINC; + else begin + $display("Attribute Syntax Error : The Attribute RX_DLYALIGN_LPFINC on GTXE1 instance %m is set to %d. Legal values for this attribute are 0 to 15.", RX_DLYALIGN_LPFINC); + $finish; + end + + if ((RX_DLYALIGN_MONSEL >= 0) && (RX_DLYALIGN_MONSEL <= 7)) + RX_DLYALIGN_MONSEL_BINARY = RX_DLYALIGN_MONSEL; + else begin + $display("Attribute Syntax Error : The Attribute RX_DLYALIGN_MONSEL on GTXE1 instance %m is set to %d. Legal values for this attribute are 0 to 7.", RX_DLYALIGN_MONSEL); + $finish; + end + + if ((RX_DLYALIGN_OVRDSETTING >= 0) && (RX_DLYALIGN_OVRDSETTING <= 255)) + RX_DLYALIGN_OVRDSETTING_BINARY = RX_DLYALIGN_OVRDSETTING; + else begin + $display("Attribute Syntax Error : The Attribute RX_DLYALIGN_OVRDSETTING on GTXE1 instance %m is set to %d. Legal values for this attribute are 0 to 255.", RX_DLYALIGN_OVRDSETTING); + $finish; + end + + if ((RX_EYE_SCANMODE >= 0) && (RX_EYE_SCANMODE <= 3)) + RX_EYE_SCANMODE_BINARY = RX_EYE_SCANMODE; + else begin + $display("Attribute Syntax Error : The Attribute RX_EYE_SCANMODE on GTXE1 instance %m is set to %d. Legal values for this attribute are 0 to 3.", RX_EYE_SCANMODE); + $finish; + end + + if ((RX_IDLE_HI_CNT >= 0) && (RX_IDLE_HI_CNT <= 15)) + RX_IDLE_HI_CNT_BINARY = RX_IDLE_HI_CNT; + else begin + $display("Attribute Syntax Error : The Attribute RX_IDLE_HI_CNT on GTXE1 instance %m is set to %d. Legal values for this attribute are 0 to 15.", RX_IDLE_HI_CNT); + $finish; + end + + if ((RX_IDLE_LO_CNT >= 0) && (RX_IDLE_LO_CNT <= 15)) + RX_IDLE_LO_CNT_BINARY = RX_IDLE_LO_CNT; + else begin + $display("Attribute Syntax Error : The Attribute RX_IDLE_LO_CNT on GTXE1 instance %m is set to %d. Legal values for this attribute are 0 to 15.", RX_IDLE_LO_CNT); + $finish; + end + + if ((RX_SLIDE_AUTO_WAIT >= 0) && (RX_SLIDE_AUTO_WAIT <= 15)) + RX_SLIDE_AUTO_WAIT_BINARY = RX_SLIDE_AUTO_WAIT; + else begin + $display("Attribute Syntax Error : The Attribute RX_SLIDE_AUTO_WAIT on GTXE1 instance %m is set to %d. Legal values for this attribute are 0 to 15.", RX_SLIDE_AUTO_WAIT); + $finish; + end + + if ((SAS_MAX_COMSAS >= 1) && (SAS_MAX_COMSAS <= 61)) + SAS_MAX_COMSAS_BINARY = SAS_MAX_COMSAS; + else begin + $display("Attribute Syntax Error : The Attribute SAS_MAX_COMSAS on GTXE1 instance %m is set to %d. Legal values for this attribute are 1 to 61.", SAS_MAX_COMSAS); + $finish; + end + + if ((SAS_MIN_COMSAS >= 1) && (SAS_MIN_COMSAS <= 61)) + SAS_MIN_COMSAS_BINARY = SAS_MIN_COMSAS; + else begin + $display("Attribute Syntax Error : The Attribute SAS_MIN_COMSAS on GTXE1 instance %m is set to %d. Legal values for this attribute are 1 to 61.", SAS_MIN_COMSAS); + $finish; + end + + if ((SATA_BURST_VAL >= 0) && (SATA_BURST_VAL <= 7)) + SATA_BURST_VAL_BINARY = SATA_BURST_VAL; + else begin + $display("Attribute Syntax Error : The Attribute SATA_BURST_VAL on GTXE1 instance %m is set to %d. Legal values for this attribute are 0 to 7.", SATA_BURST_VAL); + $finish; + end + + if ((SATA_IDLE_VAL >= 0) && (SATA_IDLE_VAL <= 7)) + SATA_IDLE_VAL_BINARY = SATA_IDLE_VAL; + else begin + $display("Attribute Syntax Error : The Attribute SATA_IDLE_VAL on GTXE1 instance %m is set to %d. Legal values for this attribute are 0 to 7.", SATA_IDLE_VAL); + $finish; + end + + if ((SATA_MAX_BURST >= 1) && (SATA_MAX_BURST <= 61)) + SATA_MAX_BURST_BINARY = SATA_MAX_BURST; + else begin + $display("Attribute Syntax Error : The Attribute SATA_MAX_BURST on GTXE1 instance %m is set to %d. Legal values for this attribute are 1 to 61.", SATA_MAX_BURST); + $finish; + end + + if ((SATA_MAX_INIT >= 1) && (SATA_MAX_INIT <= 61)) + SATA_MAX_INIT_BINARY = SATA_MAX_INIT; + else begin + $display("Attribute Syntax Error : The Attribute SATA_MAX_INIT on GTXE1 instance %m is set to %d. Legal values for this attribute are 1 to 61.", SATA_MAX_INIT); + $finish; + end + + if ((SATA_MAX_WAKE >= 1) && (SATA_MAX_WAKE <= 61)) + SATA_MAX_WAKE_BINARY = SATA_MAX_WAKE; + else begin + $display("Attribute Syntax Error : The Attribute SATA_MAX_WAKE on GTXE1 instance %m is set to %d. Legal values for this attribute are 1 to 61.", SATA_MAX_WAKE); + $finish; + end + + if ((SATA_MIN_BURST >= 1) && (SATA_MIN_BURST <= 61)) + SATA_MIN_BURST_BINARY = SATA_MIN_BURST; + else begin + $display("Attribute Syntax Error : The Attribute SATA_MIN_BURST on GTXE1 instance %m is set to %d. Legal values for this attribute are 1 to 61.", SATA_MIN_BURST); + $finish; + end + + if ((SATA_MIN_INIT >= 1) && (SATA_MIN_INIT <= 61)) + SATA_MIN_INIT_BINARY = SATA_MIN_INIT; + else begin + $display("Attribute Syntax Error : The Attribute SATA_MIN_INIT on GTXE1 instance %m is set to %d. Legal values for this attribute are 1 to 61.", SATA_MIN_INIT); + $finish; + end + + if ((SATA_MIN_WAKE >= 1) && (SATA_MIN_WAKE <= 61)) + SATA_MIN_WAKE_BINARY = SATA_MIN_WAKE; + else begin + $display("Attribute Syntax Error : The Attribute SATA_MIN_WAKE on GTXE1 instance %m is set to %d. Legal values for this attribute are 1 to 61.", SATA_MIN_WAKE); + $finish; + end + + if ((SIM_RXREFCLK_SOURCE >= 0) && (SIM_RXREFCLK_SOURCE <= 7)) + SIM_RXREFCLK_SOURCE_BINARY = SIM_RXREFCLK_SOURCE; + else begin + $display("Attribute Syntax Error : The Attribute SIM_RXREFCLK_SOURCE on GTXE1 instance %m is set to %d. Legal values for this attribute are 0 to 7.", SIM_RXREFCLK_SOURCE); + $finish; + end + + if ((SIM_TXREFCLK_SOURCE >= 0) && (SIM_TXREFCLK_SOURCE <= 7)) + SIM_TXREFCLK_SOURCE_BINARY = SIM_TXREFCLK_SOURCE; + else begin + $display("Attribute Syntax Error : The Attribute SIM_TXREFCLK_SOURCE on GTXE1 instance %m is set to %d. Legal values for this attribute are 0 to 7.", SIM_TXREFCLK_SOURCE); + $finish; + end + + if ((TERMINATION_CTRL >= 0) && (TERMINATION_CTRL <= 31)) + TERMINATION_CTRL_BINARY = TERMINATION_CTRL; + else begin + $display("Attribute Syntax Error : The Attribute TERMINATION_CTRL on GTXE1 instance %m is set to %d. Legal values for this attribute are 0 to 31.", TERMINATION_CTRL); + $finish; + end + + if ((TXOUTCLK_DLY >= 0) && (TXOUTCLK_DLY <= 1023)) + TXOUTCLK_DLY_BINARY = TXOUTCLK_DLY; + else begin + $display("Attribute Syntax Error : The Attribute TXOUTCLK_DLY on GTXE1 instance %m is set to %d. Legal values for this attribute are 0 to 1023.", TXOUTCLK_DLY); + $finish; + end + + if ((TXPLL_LKDET_CFG >= 0) && (TXPLL_LKDET_CFG <= 7)) + TXPLL_LKDET_CFG_BINARY = TXPLL_LKDET_CFG; + else begin + $display("Attribute Syntax Error : The Attribute TXPLL_LKDET_CFG on GTXE1 instance %m is set to %d. Legal values for this attribute are 0 to 7.", TXPLL_LKDET_CFG); + $finish; + end + + if ((TXPLL_SATA >= 0) && (TXPLL_SATA <= 3)) + TXPLL_SATA_BINARY = TXPLL_SATA; + else begin + $display("Attribute Syntax Error : The Attribute TXPLL_SATA on GTXE1 instance %m is set to %d. Legal values for this attribute are 0 to 3.", TXPLL_SATA); + $finish; + end + + if ((TX_DEEMPH_0 >= 0) && (TX_DEEMPH_0 <= 31)) + TX_DEEMPH_0_BINARY = TX_DEEMPH_0; + else begin + $display("Attribute Syntax Error : The Attribute TX_DEEMPH_0 on GTXE1 instance %m is set to %d. Legal values for this attribute are 0 to 31.", TX_DEEMPH_0); + $finish; + end + + if ((TX_DEEMPH_1 >= 0) && (TX_DEEMPH_1 <= 31)) + TX_DEEMPH_1_BINARY = TX_DEEMPH_1; + else begin + $display("Attribute Syntax Error : The Attribute TX_DEEMPH_1 on GTXE1 instance %m is set to %d. Legal values for this attribute are 0 to 31.", TX_DEEMPH_1); + $finish; + end + + if ((TX_DLYALIGN_CTRINC >= 0) && (TX_DLYALIGN_CTRINC <= 15)) + TX_DLYALIGN_CTRINC_BINARY = TX_DLYALIGN_CTRINC; + else begin + $display("Attribute Syntax Error : The Attribute TX_DLYALIGN_CTRINC on GTXE1 instance %m is set to %d. Legal values for this attribute are 0 to 15.", TX_DLYALIGN_CTRINC); + $finish; + end + + if ((TX_DLYALIGN_LPFINC >= 0) && (TX_DLYALIGN_LPFINC <= 15)) + TX_DLYALIGN_LPFINC_BINARY = TX_DLYALIGN_LPFINC; + else begin + $display("Attribute Syntax Error : The Attribute TX_DLYALIGN_LPFINC on GTXE1 instance %m is set to %d. Legal values for this attribute are 0 to 15.", TX_DLYALIGN_LPFINC); + $finish; + end + + if ((TX_DLYALIGN_MONSEL >= 0) && (TX_DLYALIGN_MONSEL <= 7)) + TX_DLYALIGN_MONSEL_BINARY = TX_DLYALIGN_MONSEL; + else begin + $display("Attribute Syntax Error : The Attribute TX_DLYALIGN_MONSEL on GTXE1 instance %m is set to %d. Legal values for this attribute are 0 to 7.", TX_DLYALIGN_MONSEL); + $finish; + end + + if ((TX_DLYALIGN_OVRDSETTING >= 0) && (TX_DLYALIGN_OVRDSETTING <= 255)) + TX_DLYALIGN_OVRDSETTING_BINARY = TX_DLYALIGN_OVRDSETTING; + else begin + $display("Attribute Syntax Error : The Attribute TX_DLYALIGN_OVRDSETTING on GTXE1 instance %m is set to %d. Legal values for this attribute are 0 to 255.", TX_DLYALIGN_OVRDSETTING); + $finish; + end + + if ((TX_IDLE_ASSERT_DELAY >= 0) && (TX_IDLE_ASSERT_DELAY <= 7)) + TX_IDLE_ASSERT_DELAY_BINARY = TX_IDLE_ASSERT_DELAY; + else begin + $display("Attribute Syntax Error : The Attribute TX_IDLE_ASSERT_DELAY on GTXE1 instance %m is set to %d. Legal values for this attribute are 0 to 7.", TX_IDLE_ASSERT_DELAY); + $finish; + end + + if ((TX_IDLE_DEASSERT_DELAY >= 0) && (TX_IDLE_DEASSERT_DELAY <= 7)) + TX_IDLE_DEASSERT_DELAY_BINARY = TX_IDLE_DEASSERT_DELAY; + else begin + $display("Attribute Syntax Error : The Attribute TX_IDLE_DEASSERT_DELAY on GTXE1 instance %m is set to %d. Legal values for this attribute are 0 to 7.", TX_IDLE_DEASSERT_DELAY); + $finish; + end + + if ((TX_MARGIN_FULL_0 >= 0) && (TX_MARGIN_FULL_0 <= 127)) + TX_MARGIN_FULL_0_BINARY = TX_MARGIN_FULL_0; + else begin + $display("Attribute Syntax Error : The Attribute TX_MARGIN_FULL_0 on GTXE1 instance %m is set to %d. Legal values for this attribute are 0 to 127.", TX_MARGIN_FULL_0); + $finish; + end + + if ((TX_MARGIN_FULL_1 >= 0) && (TX_MARGIN_FULL_1 <= 127)) + TX_MARGIN_FULL_1_BINARY = TX_MARGIN_FULL_1; + else begin + $display("Attribute Syntax Error : The Attribute TX_MARGIN_FULL_1 on GTXE1 instance %m is set to %d. Legal values for this attribute are 0 to 127.", TX_MARGIN_FULL_1); + $finish; + end + + if ((TX_MARGIN_FULL_2 >= 0) && (TX_MARGIN_FULL_2 <= 127)) + TX_MARGIN_FULL_2_BINARY = TX_MARGIN_FULL_2; + else begin + $display("Attribute Syntax Error : The Attribute TX_MARGIN_FULL_2 on GTXE1 instance %m is set to %d. Legal values for this attribute are 0 to 127.", TX_MARGIN_FULL_2); + $finish; + end + + if ((TX_MARGIN_FULL_3 >= 0) && (TX_MARGIN_FULL_3 <= 127)) + TX_MARGIN_FULL_3_BINARY = TX_MARGIN_FULL_3; + else begin + $display("Attribute Syntax Error : The Attribute TX_MARGIN_FULL_3 on GTXE1 instance %m is set to %d. Legal values for this attribute are 0 to 127.", TX_MARGIN_FULL_3); + $finish; + end + + if ((TX_MARGIN_FULL_4 >= 0) && (TX_MARGIN_FULL_4 <= 127)) + TX_MARGIN_FULL_4_BINARY = TX_MARGIN_FULL_4; + else begin + $display("Attribute Syntax Error : The Attribute TX_MARGIN_FULL_4 on GTXE1 instance %m is set to %d. Legal values for this attribute are 0 to 127.", TX_MARGIN_FULL_4); + $finish; + end + + if ((TX_MARGIN_LOW_0 >= 0) && (TX_MARGIN_LOW_0 <= 127)) + TX_MARGIN_LOW_0_BINARY = TX_MARGIN_LOW_0; + else begin + $display("Attribute Syntax Error : The Attribute TX_MARGIN_LOW_0 on GTXE1 instance %m is set to %d. Legal values for this attribute are 0 to 127.", TX_MARGIN_LOW_0); + $finish; + end + + if ((TX_MARGIN_LOW_1 >= 0) && (TX_MARGIN_LOW_1 <= 127)) + TX_MARGIN_LOW_1_BINARY = TX_MARGIN_LOW_1; + else begin + $display("Attribute Syntax Error : The Attribute TX_MARGIN_LOW_1 on GTXE1 instance %m is set to %d. Legal values for this attribute are 0 to 127.", TX_MARGIN_LOW_1); + $finish; + end + + if ((TX_MARGIN_LOW_2 >= 0) && (TX_MARGIN_LOW_2 <= 127)) + TX_MARGIN_LOW_2_BINARY = TX_MARGIN_LOW_2; + else begin + $display("Attribute Syntax Error : The Attribute TX_MARGIN_LOW_2 on GTXE1 instance %m is set to %d. Legal values for this attribute are 0 to 127.", TX_MARGIN_LOW_2); + $finish; + end + + if ((TX_MARGIN_LOW_3 >= 0) && (TX_MARGIN_LOW_3 <= 127)) + TX_MARGIN_LOW_3_BINARY = TX_MARGIN_LOW_3; + else begin + $display("Attribute Syntax Error : The Attribute TX_MARGIN_LOW_3 on GTXE1 instance %m is set to %d. Legal values for this attribute are 0 to 127.", TX_MARGIN_LOW_3); + $finish; + end + + if ((TX_MARGIN_LOW_4 >= 0) && (TX_MARGIN_LOW_4 <= 127)) + TX_MARGIN_LOW_4_BINARY = TX_MARGIN_LOW_4; + else begin + $display("Attribute Syntax Error : The Attribute TX_MARGIN_LOW_4 on GTXE1 instance %m is set to %d. Legal values for this attribute are 0 to 127.", TX_MARGIN_LOW_4); + $finish; + end + + if ((TX_PMADATA_OPT >= 0) && (TX_PMADATA_OPT <= 1)) + TX_PMADATA_OPT_BINARY = TX_PMADATA_OPT; + else begin + $display("Attribute Syntax Error : The Attribute TX_PMADATA_OPT on GTXE1 instance %m is set to %d. Legal values for this attribute are 0 to 1.", TX_PMADATA_OPT); + $finish; + end + + if ((TX_TDCC_CFG >= 0) && (TX_TDCC_CFG <= 3)) + TX_TDCC_CFG_BINARY = TX_TDCC_CFG; + else begin + $display("Attribute Syntax Error : The Attribute TX_TDCC_CFG on GTXE1 instance %m is set to %d. Legal values for this attribute are 0 to 3.", TX_TDCC_CFG); + $finish; + end + + end + + wire [15:0] delay_DRPDO; + wire [1:0] delay_MGTREFCLKFAB; + wire [1:0] delay_RXLOSSOFSYNC; + wire [1:0] delay_TXBUFSTATUS; + wire [2:0] delay_DFESENSCAL; + wire [2:0] delay_RXBUFSTATUS; + wire [2:0] delay_RXCLKCORCNT; + wire [2:0] delay_RXHEADER; + wire [2:0] delay_RXSTATUS; + wire [31:0] delay_RXDATA; + wire [3:0] delay_DFETAP3MONITOR; + wire [3:0] delay_DFETAP4MONITOR; + wire [3:0] delay_RXCHARISCOMMA; + wire [3:0] delay_RXCHARISK; + wire [3:0] delay_RXCHBONDO; + wire [3:0] delay_RXDISPERR; + wire [3:0] delay_RXNOTINTABLE; + wire [3:0] delay_RXRUNDISP; + wire [3:0] delay_TXKERR; + wire [3:0] delay_TXRUNDISP; + wire [4:0] delay_DFEEYEDACMON; + wire [4:0] delay_DFETAP1MONITOR; + wire [4:0] delay_DFETAP2MONITOR; + wire [5:0] delay_DFECLKDLYADJMON; + wire [7:0] delay_RXDLYALIGNMONITOR; + wire [7:0] delay_TXDLYALIGNMONITOR; + wire [9:0] delay_TSTOUT; + wire delay_COMFINISH; + wire delay_COMINITDET; + wire delay_COMSASDET; + wire delay_COMWAKEDET; + wire delay_DRDY; + wire delay_PHYSTATUS; + wire delay_RXBYTEISALIGNED; + wire delay_RXBYTEREALIGN; + wire delay_RXCHANBONDSEQ; + wire delay_RXCHANISALIGNED; + wire delay_RXCHANREALIGN; + wire delay_RXCOMMADET; + wire delay_RXDATAVALID; + wire delay_RXELECIDLE; + wire delay_RXHEADERVALID; + wire delay_RXOVERSAMPLEERR; + wire delay_RXPLLLKDET; + wire delay_RXPRBSERR; + wire delay_RXRATEDONE; + wire delay_RXRECCLK; + wire delay_RXRECCLKPCS; + wire delay_RXRESETDONE; + wire delay_RXSTARTOFSEQ; + wire delay_RXVALID; + wire delay_TXGEARBOXREADY; + wire delay_TXN; + wire delay_TXOUTCLK; + wire delay_TXOUTCLKPCS; + wire delay_TXP; + wire delay_TXPLLLKDET; + wire delay_TXRATEDONE; + wire delay_TXRESETDONE; + + wire [12:0] delay_GTXTEST; + wire [15:0] delay_DI; + wire [19:0] delay_TSTIN; + wire [1:0] delay_MGTREFCLKRX; + wire [1:0] delay_MGTREFCLKTX; + wire [1:0] delay_NORTHREFCLKRX; + wire [1:0] delay_NORTHREFCLKTX; + wire [1:0] delay_RXPOWERDOWN; + wire [1:0] delay_RXRATE; + wire [1:0] delay_SOUTHREFCLKRX; + wire [1:0] delay_SOUTHREFCLKTX; + wire [1:0] delay_TXPOWERDOWN; + wire [1:0] delay_TXRATE; + wire [2:0] delay_LOOPBACK; + wire [2:0] delay_RXCHBONDLEVEL; + wire [2:0] delay_RXENPRBSTST; + wire [2:0] delay_RXPLLREFSELDY; + wire [2:0] delay_TXBUFDIFFCTRL; + wire [2:0] delay_TXENPRBSTST; + wire [2:0] delay_TXHEADER; + wire [2:0] delay_TXMARGIN; + wire [2:0] delay_TXPLLREFSELDY; + wire [31:0] delay_TXDATA; + wire [3:0] delay_DFETAP3; + wire [3:0] delay_DFETAP4; + wire [3:0] delay_RXCHBONDI; + wire [3:0] delay_TXBYPASS8B10B; + wire [3:0] delay_TXCHARDISPMODE; + wire [3:0] delay_TXCHARDISPVAL; + wire [3:0] delay_TXCHARISK; + wire [3:0] delay_TXDIFFCTRL; + wire [3:0] delay_TXPREEMPHASIS; + wire [4:0] delay_DFETAP1; + wire [4:0] delay_DFETAP2; + wire [4:0] delay_TXPOSTEMPHASIS; + wire [5:0] delay_DFECLKDLYADJ; + wire [6:0] delay_TXSEQUENCE; + wire [7:0] delay_DADDR; + wire [9:0] delay_RXEQMIX; + wire delay_DCLK; + wire delay_DEN; + wire delay_DFEDLYOVRD; + wire delay_DFETAPOVRD; + wire delay_DWE; + wire delay_GATERXELECIDLE; + wire delay_GREFCLKRX; + wire delay_GREFCLKTX; + wire delay_GTXRXRESET; + wire delay_GTXTXRESET; + wire delay_IGNORESIGDET; + wire delay_PERFCLKRX; + wire delay_PERFCLKTX; + wire delay_PLLRXRESET; + wire delay_PLLTXRESET; + wire delay_PRBSCNTRESET; + wire delay_RXBUFRESET; + wire delay_RXCDRRESET; + wire delay_RXCHBONDMASTER; + wire delay_RXCHBONDSLAVE; + wire delay_RXCOMMADETUSE; + wire delay_RXDEC8B10BUSE; + wire delay_RXDLYALIGNDISABLE; + wire delay_RXDLYALIGNMONENB; + wire delay_RXDLYALIGNOVERRIDE; + wire delay_RXDLYALIGNRESET; + wire delay_RXDLYALIGNSWPPRECURB; + wire delay_RXDLYALIGNUPDSW; + wire delay_RXENCHANSYNC; + wire delay_RXENMCOMMAALIGN; + wire delay_RXENPCOMMAALIGN; + wire delay_RXENPMAPHASEALIGN; + wire delay_RXENSAMPLEALIGN; + wire delay_RXGEARBOXSLIP; + wire delay_RXN; + wire delay_RXP; + wire delay_RXPLLLKDETEN; + wire delay_RXPLLPOWERDOWN; + wire delay_RXPMASETPHASE; + wire delay_RXPOLARITY; + wire delay_RXRESET; + wire delay_RXSLIDE; + wire delay_RXUSRCLK2; + wire delay_RXUSRCLK; + wire delay_TSTCLK0; + wire delay_TSTCLK1; + wire delay_TXCOMINIT; + wire delay_TXCOMSAS; + wire delay_TXCOMWAKE; + wire delay_TXDEEMPH; + wire delay_TXDETECTRX; + wire delay_TXDLYALIGNDISABLE; + wire delay_TXDLYALIGNMONENB; + wire delay_TXDLYALIGNOVERRIDE; + wire delay_TXDLYALIGNRESET; + wire delay_TXDLYALIGNUPDSW; + wire delay_TXELECIDLE; + wire delay_TXENC8B10BUSE; + wire delay_TXENPMAPHASEALIGN; + wire delay_TXINHIBIT; + wire delay_TXPDOWNASYNCH; + wire delay_TXPLLLKDETEN; + wire delay_TXPLLPOWERDOWN; + wire delay_TXPMASETPHASE; + wire delay_TXPOLARITY; + wire delay_TXPRBSFORCEERR; + wire delay_TXRESET; + wire delay_TXSTARTSEQ; + wire delay_TXSWING; + wire delay_TXUSRCLK2; + wire delay_TXUSRCLK; + wire delay_USRCODEERR; + + assign #(OUTCLK_DELAY) MGTREFCLKFAB = delay_MGTREFCLKFAB; + assign #(OUTCLK_DELAY) RXRECCLK = delay_RXRECCLK; + assign #(OUTCLK_DELAY) RXRECCLKPCS = delay_RXRECCLKPCS; + assign #(OUTCLK_DELAY) TXOUTCLK = delay_TXOUTCLK; + assign #(OUTCLK_DELAY) TXOUTCLKPCS = delay_TXOUTCLKPCS; + + assign #(out_delay) COMFINISH = delay_COMFINISH; + assign #(out_delay) COMINITDET = delay_COMINITDET; + assign #(out_delay) COMSASDET = delay_COMSASDET; + assign #(out_delay) COMWAKEDET = delay_COMWAKEDET; + assign #(out_delay) DFECLKDLYADJMON = delay_DFECLKDLYADJMON; + assign #(out_delay) DFEEYEDACMON = delay_DFEEYEDACMON; + assign #(out_delay) DFESENSCAL = delay_DFESENSCAL; + assign #(out_delay) DFETAP1MONITOR = delay_DFETAP1MONITOR; + assign #(out_delay) DFETAP2MONITOR = delay_DFETAP2MONITOR; + assign #(out_delay) DFETAP3MONITOR = delay_DFETAP3MONITOR; + assign #(out_delay) DFETAP4MONITOR = delay_DFETAP4MONITOR; + assign #(out_delay) DRDY = delay_DRDY; + assign #(out_delay) DRPDO = delay_DRPDO; + assign #(out_delay) PHYSTATUS = delay_PHYSTATUS; + assign #(out_delay) RXBUFSTATUS = delay_RXBUFSTATUS; + assign #(out_delay) RXBYTEISALIGNED = delay_RXBYTEISALIGNED; + assign #(out_delay) RXBYTEREALIGN = delay_RXBYTEREALIGN; + assign #(out_delay) RXCHANBONDSEQ = delay_RXCHANBONDSEQ; + assign #(out_delay) RXCHANISALIGNED = delay_RXCHANISALIGNED; + assign #(out_delay) RXCHANREALIGN = delay_RXCHANREALIGN; + assign #(out_delay) RXCHARISCOMMA = delay_RXCHARISCOMMA; + assign #(out_delay) RXCHARISK = delay_RXCHARISK; + assign #(out_delay) RXCHBONDO = delay_RXCHBONDO; + assign #(out_delay) RXCLKCORCNT = delay_RXCLKCORCNT; + assign #(out_delay) RXCOMMADET = delay_RXCOMMADET; + assign #(out_delay) RXDATA = delay_RXDATA; + assign #(out_delay) RXDATAVALID = delay_RXDATAVALID; + assign #(out_delay) RXDISPERR = delay_RXDISPERR; + assign #(out_delay) RXDLYALIGNMONITOR = delay_RXDLYALIGNMONITOR; + assign #(out_delay) RXELECIDLE = delay_RXELECIDLE; + assign #(out_delay) RXHEADER = delay_RXHEADER; + assign #(out_delay) RXHEADERVALID = delay_RXHEADERVALID; + assign #(out_delay) RXLOSSOFSYNC = delay_RXLOSSOFSYNC; + assign #(out_delay) RXNOTINTABLE = delay_RXNOTINTABLE; + assign #(out_delay) RXOVERSAMPLEERR = delay_RXOVERSAMPLEERR; + assign #(out_delay) RXPLLLKDET = delay_RXPLLLKDET; + assign #(out_delay) RXPRBSERR = delay_RXPRBSERR; + assign #(out_delay) RXRATEDONE = delay_RXRATEDONE; + assign #(out_delay) RXRESETDONE = delay_RXRESETDONE; + assign #(out_delay) RXRUNDISP = delay_RXRUNDISP; + assign #(out_delay) RXSTARTOFSEQ = delay_RXSTARTOFSEQ; + assign #(out_delay) RXSTATUS = delay_RXSTATUS; + assign #(out_delay) RXVALID = delay_RXVALID; + assign #(out_delay) TSTOUT = delay_TSTOUT; + assign #(out_delay) TXBUFSTATUS = delay_TXBUFSTATUS; + assign #(out_delay) TXDLYALIGNMONITOR = delay_TXDLYALIGNMONITOR; + assign #(out_delay) TXGEARBOXREADY = delay_TXGEARBOXREADY; + assign #(out_delay) TXKERR = delay_TXKERR; + assign #(out_delay) TXN = delay_TXN; + assign #(out_delay) TXP = delay_TXP; + assign #(out_delay) TXPLLLKDET = delay_TXPLLLKDET; + assign #(out_delay) TXRATEDONE = delay_TXRATEDONE; + assign #(out_delay) TXRESETDONE = delay_TXRESETDONE; + assign #(out_delay) TXRUNDISP = delay_TXRUNDISP; + + assign #(INCLK_DELAY) delay_DCLK = DCLK; + assign #(INCLK_DELAY) delay_GREFCLKRX = GREFCLKRX; + assign #(INCLK_DELAY) delay_GREFCLKTX = GREFCLKTX; + assign #(INCLK_DELAY) delay_MGTREFCLKRX = MGTREFCLKRX; + assign #(INCLK_DELAY) delay_MGTREFCLKTX = MGTREFCLKTX; + assign #(INCLK_DELAY) delay_NORTHREFCLKRX = NORTHREFCLKRX; + assign #(INCLK_DELAY) delay_NORTHREFCLKTX = NORTHREFCLKTX; + assign #(INCLK_DELAY) delay_PERFCLKRX = PERFCLKRX; + assign #(INCLK_DELAY) delay_PERFCLKTX = PERFCLKTX; + assign #(INCLK_DELAY) delay_RXUSRCLK = RXUSRCLK; + assign #(INCLK_DELAY) delay_RXUSRCLK2 = RXUSRCLK2; + assign #(INCLK_DELAY) delay_SOUTHREFCLKRX = SOUTHREFCLKRX; + assign #(INCLK_DELAY) delay_SOUTHREFCLKTX = SOUTHREFCLKTX; + assign #(INCLK_DELAY) delay_TSTCLK0 = TSTCLK0; + assign #(INCLK_DELAY) delay_TSTCLK1 = TSTCLK1; + assign #(INCLK_DELAY) delay_TXUSRCLK = TXUSRCLK; + assign #(INCLK_DELAY) delay_TXUSRCLK2 = TXUSRCLK2; + + assign #(in_delay) delay_DADDR = DADDR; + assign #(in_delay) delay_DEN = DEN; + assign #(in_delay) delay_DFECLKDLYADJ = DFECLKDLYADJ; + assign #(in_delay) delay_DFEDLYOVRD = DFEDLYOVRD; + assign #(in_delay) delay_DFETAP1 = DFETAP1; + assign #(in_delay) delay_DFETAP2 = DFETAP2; + assign #(in_delay) delay_DFETAP3 = DFETAP3; + assign #(in_delay) delay_DFETAP4 = DFETAP4; + assign #(in_delay) delay_DFETAPOVRD = DFETAPOVRD; + assign #(in_delay) delay_DI = DI; + assign #(in_delay) delay_DWE = DWE; + assign #(in_delay) delay_GATERXELECIDLE = GATERXELECIDLE; + assign #(in_delay) delay_GTXRXRESET = GTXRXRESET; + assign #(in_delay) delay_GTXTEST = GTXTEST; + assign #(in_delay) delay_GTXTXRESET = GTXTXRESET; + assign #(in_delay) delay_IGNORESIGDET = IGNORESIGDET; + assign #(in_delay) delay_LOOPBACK = LOOPBACK; + assign #(in_delay) delay_PLLRXRESET = PLLRXRESET; + assign #(in_delay) delay_PLLTXRESET = PLLTXRESET; + assign #(in_delay) delay_PRBSCNTRESET = PRBSCNTRESET; + assign #(in_delay) delay_RXBUFRESET = RXBUFRESET; + assign #(in_delay) delay_RXCDRRESET = RXCDRRESET; + assign #(in_delay) delay_RXCHBONDI = RXCHBONDI; + assign #(in_delay) delay_RXCHBONDLEVEL = RXCHBONDLEVEL; + assign #(in_delay) delay_RXCHBONDMASTER = RXCHBONDMASTER; + assign #(in_delay) delay_RXCHBONDSLAVE = RXCHBONDSLAVE; + assign #(in_delay) delay_RXCOMMADETUSE = RXCOMMADETUSE; + assign #(in_delay) delay_RXDEC8B10BUSE = RXDEC8B10BUSE; + assign #(in_delay) delay_RXDLYALIGNDISABLE = RXDLYALIGNDISABLE; + assign #(in_delay) delay_RXDLYALIGNMONENB = RXDLYALIGNMONENB; + assign #(in_delay) delay_RXDLYALIGNOVERRIDE = RXDLYALIGNOVERRIDE; + assign #(in_delay) delay_RXDLYALIGNRESET = RXDLYALIGNRESET; + assign #(in_delay) delay_RXDLYALIGNSWPPRECURB = RXDLYALIGNSWPPRECURB; + assign #(in_delay) delay_RXDLYALIGNUPDSW = RXDLYALIGNUPDSW; + assign #(in_delay) delay_RXENCHANSYNC = RXENCHANSYNC; + assign #(in_delay) delay_RXENMCOMMAALIGN = RXENMCOMMAALIGN; + assign #(in_delay) delay_RXENPCOMMAALIGN = RXENPCOMMAALIGN; + assign #(in_delay) delay_RXENPMAPHASEALIGN = RXENPMAPHASEALIGN; + assign #(in_delay) delay_RXENPRBSTST = RXENPRBSTST; + assign #(in_delay) delay_RXENSAMPLEALIGN = RXENSAMPLEALIGN; + assign #(in_delay) delay_RXEQMIX = RXEQMIX; + assign #(in_delay) delay_RXGEARBOXSLIP = RXGEARBOXSLIP; + assign #(in_delay) delay_RXN = RXN; + assign #(in_delay) delay_RXP = RXP; + assign #(in_delay) delay_RXPLLLKDETEN = RXPLLLKDETEN; + assign #(in_delay) delay_RXPLLPOWERDOWN = RXPLLPOWERDOWN; + assign #(in_delay) delay_RXPLLREFSELDY = RXPLLREFSELDY; + assign #(in_delay) delay_RXPMASETPHASE = RXPMASETPHASE; + assign #(in_delay) delay_RXPOLARITY = RXPOLARITY; + assign #(in_delay) delay_RXPOWERDOWN = RXPOWERDOWN; + assign #(in_delay) delay_RXRATE = RXRATE; + assign #(in_delay) delay_RXRESET = RXRESET; + assign #(in_delay) delay_RXSLIDE = RXSLIDE; + assign #(in_delay) delay_TSTIN = TSTIN; + assign #(in_delay) delay_TXBUFDIFFCTRL = TXBUFDIFFCTRL; + assign #(in_delay) delay_TXBYPASS8B10B = TXBYPASS8B10B; + assign #(in_delay) delay_TXCHARDISPMODE = TXCHARDISPMODE; + assign #(in_delay) delay_TXCHARDISPVAL = TXCHARDISPVAL; + assign #(in_delay) delay_TXCHARISK = TXCHARISK; + assign #(in_delay) delay_TXCOMINIT = TXCOMINIT; + assign #(in_delay) delay_TXCOMSAS = TXCOMSAS; + assign #(in_delay) delay_TXCOMWAKE = TXCOMWAKE; + assign #(in_delay) delay_TXDATA = TXDATA; + assign #(in_delay) delay_TXDEEMPH = TXDEEMPH; + assign #(in_delay) delay_TXDETECTRX = TXDETECTRX; + assign #(in_delay) delay_TXDIFFCTRL = TXDIFFCTRL; + assign #(in_delay) delay_TXDLYALIGNDISABLE = TXDLYALIGNDISABLE; + assign #(in_delay) delay_TXDLYALIGNMONENB = TXDLYALIGNMONENB; + assign #(in_delay) delay_TXDLYALIGNOVERRIDE = TXDLYALIGNOVERRIDE; + assign #(in_delay) delay_TXDLYALIGNRESET = TXDLYALIGNRESET; + assign #(in_delay) delay_TXDLYALIGNUPDSW = TXDLYALIGNUPDSW; + assign #(in_delay) delay_TXELECIDLE = TXELECIDLE; + assign #(in_delay) delay_TXENC8B10BUSE = TXENC8B10BUSE; + assign #(in_delay) delay_TXENPMAPHASEALIGN = TXENPMAPHASEALIGN; + assign #(in_delay) delay_TXENPRBSTST = TXENPRBSTST; + assign #(in_delay) delay_TXHEADER = TXHEADER; + assign #(in_delay) delay_TXINHIBIT = TXINHIBIT; + assign #(in_delay) delay_TXMARGIN = TXMARGIN; + assign #(in_delay) delay_TXPDOWNASYNCH = TXPDOWNASYNCH; + assign #(in_delay) delay_TXPLLLKDETEN = TXPLLLKDETEN; + assign #(in_delay) delay_TXPLLPOWERDOWN = TXPLLPOWERDOWN; + assign #(in_delay) delay_TXPLLREFSELDY = TXPLLREFSELDY; + assign #(in_delay) delay_TXPMASETPHASE = TXPMASETPHASE; + assign #(in_delay) delay_TXPOLARITY = TXPOLARITY; + assign #(in_delay) delay_TXPOSTEMPHASIS = TXPOSTEMPHASIS; + assign #(in_delay) delay_TXPOWERDOWN = TXPOWERDOWN; + assign #(in_delay) delay_TXPRBSFORCEERR = TXPRBSFORCEERR; + assign #(in_delay) delay_TXPREEMPHASIS = TXPREEMPHASIS; + assign #(in_delay) delay_TXRATE = TXRATE; + assign #(in_delay) delay_TXRESET = TXRESET; + assign #(in_delay) delay_TXSEQUENCE = TXSEQUENCE; + assign #(in_delay) delay_TXSTARTSEQ = TXSTARTSEQ; + assign #(in_delay) delay_TXSWING = TXSWING; + assign #(in_delay) delay_USRCODEERR = USRCODEERR; + + B_GTXE1 #( + .AC_CAP_DIS (AC_CAP_DIS), + .ALIGN_COMMA_WORD (ALIGN_COMMA_WORD), + .BGTEST_CFG (BGTEST_CFG), + .BIAS_CFG (BIAS_CFG), + .CDR_PH_ADJ_TIME (CDR_PH_ADJ_TIME), + .CHAN_BOND_1_MAX_SKEW (CHAN_BOND_1_MAX_SKEW), + .CHAN_BOND_2_MAX_SKEW (CHAN_BOND_2_MAX_SKEW), + .CHAN_BOND_KEEP_ALIGN (CHAN_BOND_KEEP_ALIGN), + .CHAN_BOND_SEQ_1_1 (CHAN_BOND_SEQ_1_1), + .CHAN_BOND_SEQ_1_2 (CHAN_BOND_SEQ_1_2), + .CHAN_BOND_SEQ_1_3 (CHAN_BOND_SEQ_1_3), + .CHAN_BOND_SEQ_1_4 (CHAN_BOND_SEQ_1_4), + .CHAN_BOND_SEQ_1_ENABLE (CHAN_BOND_SEQ_1_ENABLE), + .CHAN_BOND_SEQ_2_1 (CHAN_BOND_SEQ_2_1), + .CHAN_BOND_SEQ_2_2 (CHAN_BOND_SEQ_2_2), + .CHAN_BOND_SEQ_2_3 (CHAN_BOND_SEQ_2_3), + .CHAN_BOND_SEQ_2_4 (CHAN_BOND_SEQ_2_4), + .CHAN_BOND_SEQ_2_CFG (CHAN_BOND_SEQ_2_CFG), + .CHAN_BOND_SEQ_2_ENABLE (CHAN_BOND_SEQ_2_ENABLE), + .CHAN_BOND_SEQ_2_USE (CHAN_BOND_SEQ_2_USE), + .CHAN_BOND_SEQ_LEN (CHAN_BOND_SEQ_LEN), + .CLK_CORRECT_USE (CLK_CORRECT_USE), + .CLK_COR_ADJ_LEN (CLK_COR_ADJ_LEN), + .CLK_COR_DET_LEN (CLK_COR_DET_LEN), + .CLK_COR_INSERT_IDLE_FLAG (CLK_COR_INSERT_IDLE_FLAG), + .CLK_COR_KEEP_IDLE (CLK_COR_KEEP_IDLE), + .CLK_COR_MAX_LAT (CLK_COR_MAX_LAT), + .CLK_COR_MIN_LAT (CLK_COR_MIN_LAT), + .CLK_COR_PRECEDENCE (CLK_COR_PRECEDENCE), + .CLK_COR_REPEAT_WAIT (CLK_COR_REPEAT_WAIT), + .CLK_COR_SEQ_1_1 (CLK_COR_SEQ_1_1), + .CLK_COR_SEQ_1_2 (CLK_COR_SEQ_1_2), + .CLK_COR_SEQ_1_3 (CLK_COR_SEQ_1_3), + .CLK_COR_SEQ_1_4 (CLK_COR_SEQ_1_4), + .CLK_COR_SEQ_1_ENABLE (CLK_COR_SEQ_1_ENABLE), + .CLK_COR_SEQ_2_1 (CLK_COR_SEQ_2_1), + .CLK_COR_SEQ_2_2 (CLK_COR_SEQ_2_2), + .CLK_COR_SEQ_2_3 (CLK_COR_SEQ_2_3), + .CLK_COR_SEQ_2_4 (CLK_COR_SEQ_2_4), + .CLK_COR_SEQ_2_ENABLE (CLK_COR_SEQ_2_ENABLE), + .CLK_COR_SEQ_2_USE (CLK_COR_SEQ_2_USE), + .CM_TRIM (CM_TRIM), + .COMMA_10B_ENABLE (COMMA_10B_ENABLE), + .COMMA_DOUBLE (COMMA_DOUBLE), + .COM_BURST_VAL (COM_BURST_VAL), + .DEC_MCOMMA_DETECT (DEC_MCOMMA_DETECT), + .DEC_PCOMMA_DETECT (DEC_PCOMMA_DETECT), + .DEC_VALID_COMMA_ONLY (DEC_VALID_COMMA_ONLY), + .DFE_CAL_TIME (DFE_CAL_TIME), + .DFE_CFG (DFE_CFG), + .GEARBOX_ENDEC (GEARBOX_ENDEC), + .GEN_RXUSRCLK (GEN_RXUSRCLK), + .GEN_TXUSRCLK (GEN_TXUSRCLK), + .GTX_CFG_PWRUP (GTX_CFG_PWRUP), + .MCOMMA_10B_VALUE (MCOMMA_10B_VALUE), + .MCOMMA_DETECT (MCOMMA_DETECT), + .OOBDETECT_THRESHOLD (OOBDETECT_THRESHOLD), + .PCI_EXPRESS_MODE (PCI_EXPRESS_MODE), + .PCOMMA_10B_VALUE (PCOMMA_10B_VALUE), + .PCOMMA_DETECT (PCOMMA_DETECT), + .PMA_CAS_CLK_EN (PMA_CAS_CLK_EN), + .PMA_CDR_SCAN (PMA_CDR_SCAN), + .PMA_CFG (PMA_CFG), + .PMA_RXSYNC_CFG (PMA_RXSYNC_CFG), + .PMA_RX_CFG (PMA_RX_CFG), + .PMA_TX_CFG (PMA_TX_CFG), + .POWER_SAVE (POWER_SAVE), + .RCV_TERM_GND (RCV_TERM_GND), + .RCV_TERM_VTTRX (RCV_TERM_VTTRX), + .RXGEARBOX_USE (RXGEARBOX_USE), + .RXPLL_COM_CFG (RXPLL_COM_CFG), + .RXPLL_CP_CFG (RXPLL_CP_CFG), + .RXPLL_DIVSEL45_FB (RXPLL_DIVSEL45_FB), + .RXPLL_DIVSEL_FB (RXPLL_DIVSEL_FB), + .RXPLL_DIVSEL_OUT (RXPLL_DIVSEL_OUT), + .RXPLL_DIVSEL_REF (RXPLL_DIVSEL_REF), + .RXPLL_LKDET_CFG (RXPLL_LKDET_CFG), + .RXPRBSERR_LOOPBACK (RXPRBSERR_LOOPBACK), + .RXRECCLK_CTRL (RXRECCLK_CTRL), + .RXRECCLK_DLY (RXRECCLK_DLY), + .RXUSRCLK_DLY (RXUSRCLK_DLY), + .RX_BUFFER_USE (RX_BUFFER_USE), + .RX_CLK25_DIVIDER (RX_CLK25_DIVIDER), + .RX_DATA_WIDTH (RX_DATA_WIDTH), + .RX_DECODE_SEQ_MATCH (RX_DECODE_SEQ_MATCH), + .RX_DLYALIGN_CTRINC (RX_DLYALIGN_CTRINC), + .RX_DLYALIGN_EDGESET (RX_DLYALIGN_EDGESET), + .RX_DLYALIGN_LPFINC (RX_DLYALIGN_LPFINC), + .RX_DLYALIGN_MONSEL (RX_DLYALIGN_MONSEL), + .RX_DLYALIGN_OVRDSETTING (RX_DLYALIGN_OVRDSETTING), + .RX_EN_IDLE_HOLD_CDR (RX_EN_IDLE_HOLD_CDR), + .RX_EN_IDLE_HOLD_DFE (RX_EN_IDLE_HOLD_DFE), + .RX_EN_IDLE_RESET_BUF (RX_EN_IDLE_RESET_BUF), + .RX_EN_IDLE_RESET_FR (RX_EN_IDLE_RESET_FR), + .RX_EN_IDLE_RESET_PH (RX_EN_IDLE_RESET_PH), + .RX_EN_MODE_RESET_BUF (RX_EN_MODE_RESET_BUF), + .RX_EN_RATE_RESET_BUF (RX_EN_RATE_RESET_BUF), + .RX_EN_REALIGN_RESET_BUF (RX_EN_REALIGN_RESET_BUF), + .RX_EN_REALIGN_RESET_BUF2 (RX_EN_REALIGN_RESET_BUF2), + .RX_EYE_OFFSET (RX_EYE_OFFSET), + .RX_EYE_SCANMODE (RX_EYE_SCANMODE), + .RX_FIFO_ADDR_MODE (RX_FIFO_ADDR_MODE), + .RX_IDLE_HI_CNT (RX_IDLE_HI_CNT), + .RX_IDLE_LO_CNT (RX_IDLE_LO_CNT), + .RX_LOSS_OF_SYNC_FSM (RX_LOSS_OF_SYNC_FSM), + .RX_LOS_INVALID_INCR (RX_LOS_INVALID_INCR), + .RX_LOS_THRESHOLD (RX_LOS_THRESHOLD), + .RX_OVERSAMPLE_MODE (RX_OVERSAMPLE_MODE), + .RX_SLIDE_AUTO_WAIT (RX_SLIDE_AUTO_WAIT), + .RX_SLIDE_MODE (RX_SLIDE_MODE), + .RX_XCLK_SEL (RX_XCLK_SEL), + .SAS_MAX_COMSAS (SAS_MAX_COMSAS), + .SAS_MIN_COMSAS (SAS_MIN_COMSAS), + .SATA_BURST_VAL (SATA_BURST_VAL), + .SATA_IDLE_VAL (SATA_IDLE_VAL), + .SATA_MAX_BURST (SATA_MAX_BURST), + .SATA_MAX_INIT (SATA_MAX_INIT), + .SATA_MAX_WAKE (SATA_MAX_WAKE), + .SATA_MIN_BURST (SATA_MIN_BURST), + .SATA_MIN_INIT (SATA_MIN_INIT), + .SATA_MIN_WAKE (SATA_MIN_WAKE), + .SHOW_REALIGN_COMMA (SHOW_REALIGN_COMMA), + .SIM_GTXRESET_SPEEDUP (SIM_GTXRESET_SPEEDUP), + .SIM_RECEIVER_DETECT_PASS (SIM_RECEIVER_DETECT_PASS), + .SIM_RXREFCLK_SOURCE (SIM_RXREFCLK_SOURCE), + .SIM_TXREFCLK_SOURCE (SIM_TXREFCLK_SOURCE), + .SIM_TX_ELEC_IDLE_LEVEL (SIM_TX_ELEC_IDLE_LEVEL), + .SIM_VERSION (SIM_VERSION), + .TERMINATION_CTRL (TERMINATION_CTRL), + .TERMINATION_OVRD (TERMINATION_OVRD), + .TRANS_TIME_FROM_P2 (TRANS_TIME_FROM_P2), + .TRANS_TIME_NON_P2 (TRANS_TIME_NON_P2), + .TRANS_TIME_RATE (TRANS_TIME_RATE), + .TRANS_TIME_TO_P2 (TRANS_TIME_TO_P2), + .TST_ATTR (TST_ATTR), + .TXDRIVE_LOOPBACK_HIZ (TXDRIVE_LOOPBACK_HIZ), + .TXDRIVE_LOOPBACK_PD (TXDRIVE_LOOPBACK_PD), + .TXGEARBOX_USE (TXGEARBOX_USE), + .TXOUTCLK_CTRL (TXOUTCLK_CTRL), + .TXOUTCLK_DLY (TXOUTCLK_DLY), + .TXPLL_COM_CFG (TXPLL_COM_CFG), + .TXPLL_CP_CFG (TXPLL_CP_CFG), + .TXPLL_DIVSEL45_FB (TXPLL_DIVSEL45_FB), + .TXPLL_DIVSEL_FB (TXPLL_DIVSEL_FB), + .TXPLL_DIVSEL_OUT (TXPLL_DIVSEL_OUT), + .TXPLL_DIVSEL_REF (TXPLL_DIVSEL_REF), + .TXPLL_LKDET_CFG (TXPLL_LKDET_CFG), + .TXPLL_SATA (TXPLL_SATA), + .TX_BUFFER_USE (TX_BUFFER_USE), + .TX_BYTECLK_CFG (TX_BYTECLK_CFG), + .TX_CLK25_DIVIDER (TX_CLK25_DIVIDER), + .TX_CLK_SOURCE (TX_CLK_SOURCE), + .TX_DATA_WIDTH (TX_DATA_WIDTH), + .TX_DEEMPH_0 (TX_DEEMPH_0), + .TX_DEEMPH_1 (TX_DEEMPH_1), + .TX_DETECT_RX_CFG (TX_DETECT_RX_CFG), + .TX_DLYALIGN_CTRINC (TX_DLYALIGN_CTRINC), + .TX_DLYALIGN_LPFINC (TX_DLYALIGN_LPFINC), + .TX_DLYALIGN_MONSEL (TX_DLYALIGN_MONSEL), + .TX_DLYALIGN_OVRDSETTING (TX_DLYALIGN_OVRDSETTING), + .TX_DRIVE_MODE (TX_DRIVE_MODE), + .TX_EN_RATE_RESET_BUF (TX_EN_RATE_RESET_BUF), + .TX_IDLE_ASSERT_DELAY (TX_IDLE_ASSERT_DELAY), + .TX_IDLE_DEASSERT_DELAY (TX_IDLE_DEASSERT_DELAY), + .TX_MARGIN_FULL_0 (TX_MARGIN_FULL_0), + .TX_MARGIN_FULL_1 (TX_MARGIN_FULL_1), + .TX_MARGIN_FULL_2 (TX_MARGIN_FULL_2), + .TX_MARGIN_FULL_3 (TX_MARGIN_FULL_3), + .TX_MARGIN_FULL_4 (TX_MARGIN_FULL_4), + .TX_MARGIN_LOW_0 (TX_MARGIN_LOW_0), + .TX_MARGIN_LOW_1 (TX_MARGIN_LOW_1), + .TX_MARGIN_LOW_2 (TX_MARGIN_LOW_2), + .TX_MARGIN_LOW_3 (TX_MARGIN_LOW_3), + .TX_MARGIN_LOW_4 (TX_MARGIN_LOW_4), + .TX_OVERSAMPLE_MODE (TX_OVERSAMPLE_MODE), + .TX_PMADATA_OPT (TX_PMADATA_OPT), + .TX_TDCC_CFG (TX_TDCC_CFG), + .TX_USRCLK_CFG (TX_USRCLK_CFG), + .TX_XCLK_SEL (TX_XCLK_SEL)) + + B_GTXE1_INST( + .COMFINISH (delay_COMFINISH), + .COMINITDET (delay_COMINITDET), + .COMSASDET (delay_COMSASDET), + .COMWAKEDET (delay_COMWAKEDET), + .DFECLKDLYADJMON (delay_DFECLKDLYADJMON), + .DFEEYEDACMON (delay_DFEEYEDACMON), + .DFESENSCAL (delay_DFESENSCAL), + .DFETAP1MONITOR (delay_DFETAP1MONITOR), + .DFETAP2MONITOR (delay_DFETAP2MONITOR), + .DFETAP3MONITOR (delay_DFETAP3MONITOR), + .DFETAP4MONITOR (delay_DFETAP4MONITOR), + .DRDY (delay_DRDY), + .DRPDO (delay_DRPDO), + .MGTREFCLKFAB (delay_MGTREFCLKFAB), + .PHYSTATUS (delay_PHYSTATUS), + .RXBUFSTATUS (delay_RXBUFSTATUS), + .RXBYTEISALIGNED (delay_RXBYTEISALIGNED), + .RXBYTEREALIGN (delay_RXBYTEREALIGN), + .RXCHANBONDSEQ (delay_RXCHANBONDSEQ), + .RXCHANISALIGNED (delay_RXCHANISALIGNED), + .RXCHANREALIGN (delay_RXCHANREALIGN), + .RXCHARISCOMMA (delay_RXCHARISCOMMA), + .RXCHARISK (delay_RXCHARISK), + .RXCHBONDO (delay_RXCHBONDO), + .RXCLKCORCNT (delay_RXCLKCORCNT), + .RXCOMMADET (delay_RXCOMMADET), + .RXDATA (delay_RXDATA), + .RXDATAVALID (delay_RXDATAVALID), + .RXDISPERR (delay_RXDISPERR), + .RXDLYALIGNMONITOR (delay_RXDLYALIGNMONITOR), + .RXELECIDLE (delay_RXELECIDLE), + .RXHEADER (delay_RXHEADER), + .RXHEADERVALID (delay_RXHEADERVALID), + .RXLOSSOFSYNC (delay_RXLOSSOFSYNC), + .RXNOTINTABLE (delay_RXNOTINTABLE), + .RXOVERSAMPLEERR (delay_RXOVERSAMPLEERR), + .RXPLLLKDET (delay_RXPLLLKDET), + .RXPRBSERR (delay_RXPRBSERR), + .RXRATEDONE (delay_RXRATEDONE), + .RXRECCLK (delay_RXRECCLK), + .RXRECCLKPCS (delay_RXRECCLKPCS), + .RXRESETDONE (delay_RXRESETDONE), + .RXRUNDISP (delay_RXRUNDISP), + .RXSTARTOFSEQ (delay_RXSTARTOFSEQ), + .RXSTATUS (delay_RXSTATUS), + .RXVALID (delay_RXVALID), + .TSTOUT (delay_TSTOUT), + .TXBUFSTATUS (delay_TXBUFSTATUS), + .TXDLYALIGNMONITOR (delay_TXDLYALIGNMONITOR), + .TXGEARBOXREADY (delay_TXGEARBOXREADY), + .TXKERR (delay_TXKERR), + .TXN (delay_TXN), + .TXOUTCLK (delay_TXOUTCLK), + .TXOUTCLKPCS (delay_TXOUTCLKPCS), + .TXP (delay_TXP), + .TXPLLLKDET (delay_TXPLLLKDET), + .TXRATEDONE (delay_TXRATEDONE), + .TXRESETDONE (delay_TXRESETDONE), + .TXRUNDISP (delay_TXRUNDISP), + .DADDR (delay_DADDR), + .DCLK (delay_DCLK), + .DEN (delay_DEN), + .DFECLKDLYADJ (delay_DFECLKDLYADJ), + .DFEDLYOVRD (delay_DFEDLYOVRD), + .DFETAP1 (delay_DFETAP1), + .DFETAP2 (delay_DFETAP2), + .DFETAP3 (delay_DFETAP3), + .DFETAP4 (delay_DFETAP4), + .DFETAPOVRD (delay_DFETAPOVRD), + .DI (delay_DI), + .DWE (delay_DWE), + .GATERXELECIDLE (delay_GATERXELECIDLE), + .GREFCLKRX (delay_GREFCLKRX), + .GREFCLKTX (delay_GREFCLKTX), + .GTXRXRESET (delay_GTXRXRESET), + .GTXTEST (delay_GTXTEST), + .GTXTXRESET (delay_GTXTXRESET), + .IGNORESIGDET (delay_IGNORESIGDET), + .LOOPBACK (delay_LOOPBACK), + .MGTREFCLKRX (delay_MGTREFCLKRX), + .MGTREFCLKTX (delay_MGTREFCLKTX), + .NORTHREFCLKRX (delay_NORTHREFCLKRX), + .NORTHREFCLKTX (delay_NORTHREFCLKTX), + .PERFCLKRX (delay_PERFCLKRX), + .PERFCLKTX (delay_PERFCLKTX), + .PLLRXRESET (delay_PLLRXRESET), + .PLLTXRESET (delay_PLLTXRESET), + .PRBSCNTRESET (delay_PRBSCNTRESET), + .RXBUFRESET (delay_RXBUFRESET), + .RXCDRRESET (delay_RXCDRRESET), + .RXCHBONDI (delay_RXCHBONDI), + .RXCHBONDLEVEL (delay_RXCHBONDLEVEL), + .RXCHBONDMASTER (delay_RXCHBONDMASTER), + .RXCHBONDSLAVE (delay_RXCHBONDSLAVE), + .RXCOMMADETUSE (delay_RXCOMMADETUSE), + .RXDEC8B10BUSE (delay_RXDEC8B10BUSE), + .RXDLYALIGNDISABLE (delay_RXDLYALIGNDISABLE), + .RXDLYALIGNMONENB (delay_RXDLYALIGNMONENB), + .RXDLYALIGNOVERRIDE (delay_RXDLYALIGNOVERRIDE), + .RXDLYALIGNRESET (delay_RXDLYALIGNRESET), + .RXDLYALIGNSWPPRECURB (delay_RXDLYALIGNSWPPRECURB), + .RXDLYALIGNUPDSW (delay_RXDLYALIGNUPDSW), + .RXENCHANSYNC (delay_RXENCHANSYNC), + .RXENMCOMMAALIGN (delay_RXENMCOMMAALIGN), + .RXENPCOMMAALIGN (delay_RXENPCOMMAALIGN), + .RXENPMAPHASEALIGN (delay_RXENPMAPHASEALIGN), + .RXENPRBSTST (delay_RXENPRBSTST), + .RXENSAMPLEALIGN (delay_RXENSAMPLEALIGN), + .RXEQMIX (delay_RXEQMIX), + .RXGEARBOXSLIP (delay_RXGEARBOXSLIP), + .RXN (delay_RXN), + .RXP (delay_RXP), + .RXPLLLKDETEN (delay_RXPLLLKDETEN), + .RXPLLPOWERDOWN (delay_RXPLLPOWERDOWN), + .RXPLLREFSELDY (delay_RXPLLREFSELDY), + .RXPMASETPHASE (delay_RXPMASETPHASE), + .RXPOLARITY (delay_RXPOLARITY), + .RXPOWERDOWN (delay_RXPOWERDOWN), + .RXRATE (delay_RXRATE), + .RXRESET (delay_RXRESET), + .RXSLIDE (delay_RXSLIDE), + .RXUSRCLK (delay_RXUSRCLK), + .RXUSRCLK2 (delay_RXUSRCLK2), + .SOUTHREFCLKRX (delay_SOUTHREFCLKRX), + .SOUTHREFCLKTX (delay_SOUTHREFCLKTX), + .TSTCLK0 (delay_TSTCLK0), + .TSTCLK1 (delay_TSTCLK1), + .TSTIN (delay_TSTIN), + .TXBUFDIFFCTRL (delay_TXBUFDIFFCTRL), + .TXBYPASS8B10B (delay_TXBYPASS8B10B), + .TXCHARDISPMODE (delay_TXCHARDISPMODE), + .TXCHARDISPVAL (delay_TXCHARDISPVAL), + .TXCHARISK (delay_TXCHARISK), + .TXCOMINIT (delay_TXCOMINIT), + .TXCOMSAS (delay_TXCOMSAS), + .TXCOMWAKE (delay_TXCOMWAKE), + .TXDATA (delay_TXDATA), + .TXDEEMPH (delay_TXDEEMPH), + .TXDETECTRX (delay_TXDETECTRX), + .TXDIFFCTRL (delay_TXDIFFCTRL), + .TXDLYALIGNDISABLE (delay_TXDLYALIGNDISABLE), + .TXDLYALIGNMONENB (delay_TXDLYALIGNMONENB), + .TXDLYALIGNOVERRIDE (delay_TXDLYALIGNOVERRIDE), + .TXDLYALIGNRESET (delay_TXDLYALIGNRESET), + .TXDLYALIGNUPDSW (delay_TXDLYALIGNUPDSW), + .TXELECIDLE (delay_TXELECIDLE), + .TXENC8B10BUSE (delay_TXENC8B10BUSE), + .TXENPMAPHASEALIGN (delay_TXENPMAPHASEALIGN), + .TXENPRBSTST (delay_TXENPRBSTST), + .TXHEADER (delay_TXHEADER), + .TXINHIBIT (delay_TXINHIBIT), + .TXMARGIN (delay_TXMARGIN), + .TXPDOWNASYNCH (delay_TXPDOWNASYNCH), + .TXPLLLKDETEN (delay_TXPLLLKDETEN), + .TXPLLPOWERDOWN (delay_TXPLLPOWERDOWN), + .TXPLLREFSELDY (delay_TXPLLREFSELDY), + .TXPMASETPHASE (delay_TXPMASETPHASE), + .TXPOLARITY (delay_TXPOLARITY), + .TXPOSTEMPHASIS (delay_TXPOSTEMPHASIS), + .TXPOWERDOWN (delay_TXPOWERDOWN), + .TXPRBSFORCEERR (delay_TXPRBSFORCEERR), + .TXPREEMPHASIS (delay_TXPREEMPHASIS), + .TXRATE (delay_TXRATE), + .TXRESET (delay_TXRESET), + .TXSEQUENCE (delay_TXSEQUENCE), + .TXSTARTSEQ (delay_TXSTARTSEQ), + .TXSWING (delay_TXSWING), + .TXUSRCLK (delay_TXUSRCLK), + .TXUSRCLK2 (delay_TXUSRCLK2), + .USRCODEERR (delay_USRCODEERR), + .GSR(GSR) + ); + + specify + ( DCLK => DRDY) = (0, 0); + ( DCLK => DRPDO[0]) = (0, 0); + ( DCLK => DRPDO[10]) = (0, 0); + ( DCLK => DRPDO[11]) = (0, 0); + ( DCLK => DRPDO[12]) = (0, 0); + ( DCLK => DRPDO[13]) = (0, 0); + ( DCLK => DRPDO[14]) = (0, 0); + ( DCLK => DRPDO[15]) = (0, 0); + ( DCLK => DRPDO[1]) = (0, 0); + ( DCLK => DRPDO[2]) = (0, 0); + ( DCLK => DRPDO[3]) = (0, 0); + ( DCLK => DRPDO[4]) = (0, 0); + ( DCLK => DRPDO[5]) = (0, 0); + ( DCLK => DRPDO[6]) = (0, 0); + ( DCLK => DRPDO[7]) = (0, 0); + ( DCLK => DRPDO[8]) = (0, 0); + ( DCLK => DRPDO[9]) = (0, 0); + ( MGTREFCLKRX[0] => MGTREFCLKFAB[0]) = (0, 0); + ( MGTREFCLKRX[0] => MGTREFCLKFAB[1]) = (0, 0); + ( MGTREFCLKRX[1] => MGTREFCLKFAB[0]) = (0, 0); + ( MGTREFCLKRX[1] => MGTREFCLKFAB[1]) = (0, 0); + ( MGTREFCLKTX[0] => MGTREFCLKFAB[0]) = (0, 0); + ( MGTREFCLKTX[0] => MGTREFCLKFAB[1]) = (0, 0); + ( MGTREFCLKTX[1] => MGTREFCLKFAB[0]) = (0, 0); + ( MGTREFCLKTX[1] => MGTREFCLKFAB[1]) = (0, 0); + ( NORTHREFCLKRX[0] => MGTREFCLKFAB[0]) = (0, 0); + ( NORTHREFCLKRX[0] => MGTREFCLKFAB[1]) = (0, 0); + ( NORTHREFCLKRX[1] => MGTREFCLKFAB[0]) = (0, 0); + ( NORTHREFCLKRX[1] => MGTREFCLKFAB[1]) = (0, 0); + ( NORTHREFCLKTX[0] => MGTREFCLKFAB[0]) = (0, 0); + ( NORTHREFCLKTX[0] => MGTREFCLKFAB[1]) = (0, 0); + ( NORTHREFCLKTX[1] => MGTREFCLKFAB[0]) = (0, 0); + ( NORTHREFCLKTX[1] => MGTREFCLKFAB[1]) = (0, 0); + ( RXUSRCLK => RXCHBONDO[0]) = (0, 0); + ( RXUSRCLK => RXCHBONDO[1]) = (0, 0); + ( RXUSRCLK => RXCHBONDO[2]) = (0, 0); + ( RXUSRCLK => RXCHBONDO[3]) = (0, 0); + ( RXUSRCLK2 => COMINITDET) = (0, 0); + ( RXUSRCLK2 => COMSASDET) = (0, 0); + ( RXUSRCLK2 => COMWAKEDET) = (0, 0); + ( RXUSRCLK2 => DFECLKDLYADJMON[0]) = (0, 0); + ( RXUSRCLK2 => DFECLKDLYADJMON[1]) = (0, 0); + ( RXUSRCLK2 => DFECLKDLYADJMON[2]) = (0, 0); + ( RXUSRCLK2 => DFECLKDLYADJMON[3]) = (0, 0); + ( RXUSRCLK2 => DFECLKDLYADJMON[4]) = (0, 0); + ( RXUSRCLK2 => DFECLKDLYADJMON[5]) = (0, 0); + ( RXUSRCLK2 => DFEEYEDACMON[0]) = (0, 0); + ( RXUSRCLK2 => DFEEYEDACMON[1]) = (0, 0); + ( RXUSRCLK2 => DFEEYEDACMON[2]) = (0, 0); + ( RXUSRCLK2 => DFEEYEDACMON[3]) = (0, 0); + ( RXUSRCLK2 => DFEEYEDACMON[4]) = (0, 0); + ( RXUSRCLK2 => DFESENSCAL[0]) = (0, 0); + ( RXUSRCLK2 => DFESENSCAL[1]) = (0, 0); + ( RXUSRCLK2 => DFESENSCAL[2]) = (0, 0); + ( RXUSRCLK2 => DFETAP1MONITOR[0]) = (0, 0); + ( RXUSRCLK2 => DFETAP1MONITOR[1]) = (0, 0); + ( RXUSRCLK2 => DFETAP1MONITOR[2]) = (0, 0); + ( RXUSRCLK2 => DFETAP1MONITOR[3]) = (0, 0); + ( RXUSRCLK2 => DFETAP1MONITOR[4]) = (0, 0); + ( RXUSRCLK2 => DFETAP2MONITOR[0]) = (0, 0); + ( RXUSRCLK2 => DFETAP2MONITOR[1]) = (0, 0); + ( RXUSRCLK2 => DFETAP2MONITOR[2]) = (0, 0); + ( RXUSRCLK2 => DFETAP2MONITOR[3]) = (0, 0); + ( RXUSRCLK2 => DFETAP2MONITOR[4]) = (0, 0); + ( RXUSRCLK2 => DFETAP3MONITOR[0]) = (0, 0); + ( RXUSRCLK2 => DFETAP3MONITOR[1]) = (0, 0); + ( RXUSRCLK2 => DFETAP3MONITOR[2]) = (0, 0); + ( RXUSRCLK2 => DFETAP3MONITOR[3]) = (0, 0); + ( RXUSRCLK2 => DFETAP4MONITOR[0]) = (0, 0); + ( RXUSRCLK2 => DFETAP4MONITOR[1]) = (0, 0); + ( RXUSRCLK2 => DFETAP4MONITOR[2]) = (0, 0); + ( RXUSRCLK2 => DFETAP4MONITOR[3]) = (0, 0); + ( RXUSRCLK2 => PHYSTATUS) = (0, 0); + ( RXUSRCLK2 => RXBUFSTATUS[0]) = (0, 0); + ( RXUSRCLK2 => RXBUFSTATUS[1]) = (0, 0); + ( RXUSRCLK2 => RXBUFSTATUS[2]) = (0, 0); + ( RXUSRCLK2 => RXBYTEISALIGNED) = (0, 0); + ( RXUSRCLK2 => RXBYTEREALIGN) = (0, 0); + ( RXUSRCLK2 => RXCHANBONDSEQ) = (0, 0); + ( RXUSRCLK2 => RXCHANISALIGNED) = (0, 0); + ( RXUSRCLK2 => RXCHANREALIGN) = (0, 0); + ( RXUSRCLK2 => RXCHARISCOMMA[0]) = (0, 0); + ( RXUSRCLK2 => RXCHARISCOMMA[1]) = (0, 0); + ( RXUSRCLK2 => RXCHARISCOMMA[2]) = (0, 0); + ( RXUSRCLK2 => RXCHARISCOMMA[3]) = (0, 0); + ( RXUSRCLK2 => RXCHARISK[0]) = (0, 0); + ( RXUSRCLK2 => RXCHARISK[1]) = (0, 0); + ( RXUSRCLK2 => RXCHARISK[2]) = (0, 0); + ( RXUSRCLK2 => RXCHARISK[3]) = (0, 0); + ( RXUSRCLK2 => RXCHBONDO[0]) = (0, 0); + ( RXUSRCLK2 => RXCHBONDO[1]) = (0, 0); + ( RXUSRCLK2 => RXCHBONDO[2]) = (0, 0); + ( RXUSRCLK2 => RXCHBONDO[3]) = (0, 0); + ( RXUSRCLK2 => RXCLKCORCNT[0]) = (0, 0); + ( RXUSRCLK2 => RXCLKCORCNT[1]) = (0, 0); + ( RXUSRCLK2 => RXCLKCORCNT[2]) = (0, 0); + ( RXUSRCLK2 => RXCOMMADET) = (0, 0); + ( RXUSRCLK2 => RXDATAVALID) = (0, 0); + ( RXUSRCLK2 => RXDATA[0]) = (0, 0); + ( RXUSRCLK2 => RXDATA[10]) = (0, 0); + ( RXUSRCLK2 => RXDATA[11]) = (0, 0); + ( RXUSRCLK2 => RXDATA[12]) = (0, 0); + ( RXUSRCLK2 => RXDATA[13]) = (0, 0); + ( RXUSRCLK2 => RXDATA[14]) = (0, 0); + ( RXUSRCLK2 => RXDATA[15]) = (0, 0); + ( RXUSRCLK2 => RXDATA[16]) = (0, 0); + ( RXUSRCLK2 => RXDATA[17]) = (0, 0); + ( RXUSRCLK2 => RXDATA[18]) = (0, 0); + ( RXUSRCLK2 => RXDATA[19]) = (0, 0); + ( RXUSRCLK2 => RXDATA[1]) = (0, 0); + ( RXUSRCLK2 => RXDATA[20]) = (0, 0); + ( RXUSRCLK2 => RXDATA[21]) = (0, 0); + ( RXUSRCLK2 => RXDATA[22]) = (0, 0); + ( RXUSRCLK2 => RXDATA[23]) = (0, 0); + ( RXUSRCLK2 => RXDATA[24]) = (0, 0); + ( RXUSRCLK2 => RXDATA[25]) = (0, 0); + ( RXUSRCLK2 => RXDATA[26]) = (0, 0); + ( RXUSRCLK2 => RXDATA[27]) = (0, 0); + ( RXUSRCLK2 => RXDATA[28]) = (0, 0); + ( RXUSRCLK2 => RXDATA[29]) = (0, 0); + ( RXUSRCLK2 => RXDATA[2]) = (0, 0); + ( RXUSRCLK2 => RXDATA[30]) = (0, 0); + ( RXUSRCLK2 => RXDATA[31]) = (0, 0); + ( RXUSRCLK2 => RXDATA[3]) = (0, 0); + ( RXUSRCLK2 => RXDATA[4]) = (0, 0); + ( RXUSRCLK2 => RXDATA[5]) = (0, 0); + ( RXUSRCLK2 => RXDATA[6]) = (0, 0); + ( RXUSRCLK2 => RXDATA[7]) = (0, 0); + ( RXUSRCLK2 => RXDATA[8]) = (0, 0); + ( RXUSRCLK2 => RXDATA[9]) = (0, 0); + ( RXUSRCLK2 => RXDISPERR[0]) = (0, 0); + ( RXUSRCLK2 => RXDISPERR[1]) = (0, 0); + ( RXUSRCLK2 => RXDISPERR[2]) = (0, 0); + ( RXUSRCLK2 => RXDISPERR[3]) = (0, 0); + ( RXUSRCLK2 => RXHEADERVALID) = (0, 0); + ( RXUSRCLK2 => RXHEADER[0]) = (0, 0); + ( RXUSRCLK2 => RXHEADER[1]) = (0, 0); + ( RXUSRCLK2 => RXHEADER[2]) = (0, 0); + ( RXUSRCLK2 => RXLOSSOFSYNC[0]) = (0, 0); + ( RXUSRCLK2 => RXLOSSOFSYNC[1]) = (0, 0); + ( RXUSRCLK2 => RXNOTINTABLE[0]) = (0, 0); + ( RXUSRCLK2 => RXNOTINTABLE[1]) = (0, 0); + ( RXUSRCLK2 => RXNOTINTABLE[2]) = (0, 0); + ( RXUSRCLK2 => RXNOTINTABLE[3]) = (0, 0); + ( RXUSRCLK2 => RXOVERSAMPLEERR) = (0, 0); + ( RXUSRCLK2 => RXPRBSERR) = (0, 0); + ( RXUSRCLK2 => RXRATEDONE) = (0, 0); + ( RXUSRCLK2 => RXRESETDONE) = (0, 0); + ( RXUSRCLK2 => RXRUNDISP[0]) = (0, 0); + ( RXUSRCLK2 => RXRUNDISP[1]) = (0, 0); + ( RXUSRCLK2 => RXRUNDISP[2]) = (0, 0); + ( RXUSRCLK2 => RXRUNDISP[3]) = (0, 0); + ( RXUSRCLK2 => RXSTARTOFSEQ) = (0, 0); + ( RXUSRCLK2 => RXSTATUS[0]) = (0, 0); + ( RXUSRCLK2 => RXSTATUS[1]) = (0, 0); + ( RXUSRCLK2 => RXSTATUS[2]) = (0, 0); + ( RXUSRCLK2 => RXVALID) = (0, 0); + ( SOUTHREFCLKRX[0] => MGTREFCLKFAB[0]) = (0, 0); + ( SOUTHREFCLKRX[0] => MGTREFCLKFAB[1]) = (0, 0); + ( SOUTHREFCLKRX[1] => MGTREFCLKFAB[0]) = (0, 0); + ( SOUTHREFCLKRX[1] => MGTREFCLKFAB[1]) = (0, 0); + ( SOUTHREFCLKTX[0] => MGTREFCLKFAB[0]) = (0, 0); + ( SOUTHREFCLKTX[0] => MGTREFCLKFAB[1]) = (0, 0); + ( SOUTHREFCLKTX[1] => MGTREFCLKFAB[0]) = (0, 0); + ( SOUTHREFCLKTX[1] => MGTREFCLKFAB[1]) = (0, 0); + ( TXUSRCLK2 => COMFINISH) = (0, 0); + ( TXUSRCLK2 => TXBUFSTATUS[0]) = (0, 0); + ( TXUSRCLK2 => TXBUFSTATUS[1]) = (0, 0); + ( TXUSRCLK2 => TXGEARBOXREADY) = (0, 0); + ( TXUSRCLK2 => TXKERR[0]) = (0, 0); + ( TXUSRCLK2 => TXKERR[1]) = (0, 0); + ( TXUSRCLK2 => TXKERR[2]) = (0, 0); + ( TXUSRCLK2 => TXKERR[3]) = (0, 0); + ( TXUSRCLK2 => TXRATEDONE) = (0, 0); + ( TXUSRCLK2 => TXRESETDONE) = (0, 0); + ( TXUSRCLK2 => TXRUNDISP[0]) = (0, 0); + ( TXUSRCLK2 => TXRUNDISP[1]) = (0, 0); + ( TXUSRCLK2 => TXRUNDISP[2]) = (0, 0); + ( TXUSRCLK2 => TXRUNDISP[3]) = (0, 0); + + specparam PATHPULSE$ = 0; + endspecify +endmodule diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/GTX_DUAL.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/GTX_DUAL.v new file mode 100644 index 0000000..4a80b0b --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/GTX_DUAL.v @@ -0,0 +1,4005 @@ +/////////////////////////////////////////////////////////// +// Copyright (c) 1995/2006 Xilinx Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////// +// +// ____ ___ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : +// / / +// /__/ /\ Filename : GTX_DUAL.v +// \ \ / \ Timestamp : Tue Jan 9 10:05:14 2007 +// \__\/\__ \ +// +// Revision: +// 09/12/06 - CR#423671 - Initial version. +// 12/05/06 - CR#426138 - J.31 spreadsheet update +// 01/23/07 - CR#430426 - J.32 pinTime added +// 02/20/07 - CR#434096 - Parameter default value update PLL_RXDIVSEL_OUT_0/1 +// 06/18/07 - CR#441601 - BT1445 - Test attributes made visible +// 06/18/07 - CR#441576 - BT1488 - Add STEPPING attribute +// 10/05/07 - CR#451343 - BT1514 - Add ES1 (ES1 mapped to 0) as STEPPING value +// 11/05/07 - CR#452590 - BT1514 - Remove STEPPING attribute from unisim/simprim wrapper +// 02/05/08 - CR#459742 - Attribute default changes +// 03/14/08 - CR#468285 - Updated timing checks +// 03/17/08 - CR#467692 - Add SIM_MODE attribute with values LEGACY & FAST model +// 04/24/08 - CR#472011 - OOBDETECT_THRESHOLD_0/1 default from 001 to 110, range changes from 000-111 to 110-111 +// 05/13/08 - CR#472931 - OOBDETECT_THRESHOLD_0/1 case statement updates +// 05/19/08 - CR#472395 - Remove GTX_DUAL LEGACY model +// 05/27/08 - CR#472395 - Set SIM_MODE to FAST, Add DRC checks +///////////////////////////////////////////////////////////// + +`timescale 1 ps / 1 ps + +module GTX_DUAL ( + DFECLKDLYADJMONITOR0, + DFECLKDLYADJMONITOR1, + DFEEYEDACMONITOR0, + DFEEYEDACMONITOR1, + DFESENSCAL0, + DFESENSCAL1, + DFETAP1MONITOR0, + DFETAP1MONITOR1, + DFETAP2MONITOR0, + DFETAP2MONITOR1, + DFETAP3MONITOR0, + DFETAP3MONITOR1, + DFETAP4MONITOR0, + DFETAP4MONITOR1, + DO, + DRDY, + PHYSTATUS0, + PHYSTATUS1, + PLLLKDET, + REFCLKOUT, + RESETDONE0, + RESETDONE1, + RXBUFSTATUS0, + RXBUFSTATUS1, + RXBYTEISALIGNED0, + RXBYTEISALIGNED1, + RXBYTEREALIGN0, + RXBYTEREALIGN1, + RXCHANBONDSEQ0, + RXCHANBONDSEQ1, + RXCHANISALIGNED0, + RXCHANISALIGNED1, + RXCHANREALIGN0, + RXCHANREALIGN1, + RXCHARISCOMMA0, + RXCHARISCOMMA1, + RXCHARISK0, + RXCHARISK1, + RXCHBONDO0, + RXCHBONDO1, + RXCLKCORCNT0, + RXCLKCORCNT1, + RXCOMMADET0, + RXCOMMADET1, + RXDATA0, + RXDATA1, + RXDATAVALID0, + RXDATAVALID1, + RXDISPERR0, + RXDISPERR1, + RXELECIDLE0, + RXELECIDLE1, + RXHEADER0, + RXHEADER1, + RXHEADERVALID0, + RXHEADERVALID1, + RXLOSSOFSYNC0, + RXLOSSOFSYNC1, + RXNOTINTABLE0, + RXNOTINTABLE1, + RXOVERSAMPLEERR0, + RXOVERSAMPLEERR1, + RXPRBSERR0, + RXPRBSERR1, + RXRECCLK0, + RXRECCLK1, + RXRUNDISP0, + RXRUNDISP1, + RXSTARTOFSEQ0, + RXSTARTOFSEQ1, + RXSTATUS0, + RXSTATUS1, + RXVALID0, + RXVALID1, + TXBUFSTATUS0, + TXBUFSTATUS1, + TXGEARBOXREADY0, + TXGEARBOXREADY1, + TXKERR0, + TXKERR1, + TXN0, + TXN1, + TXOUTCLK0, + TXOUTCLK1, + TXP0, + TXP1, + TXRUNDISP0, + TXRUNDISP1, + + CLKIN, + DADDR, + DCLK, + DEN, + DFECLKDLYADJ0, + DFECLKDLYADJ1, + DFETAP10, + DFETAP11, + DFETAP20, + DFETAP21, + DFETAP30, + DFETAP31, + DFETAP40, + DFETAP41, + DI, + DWE, + GTXRESET, + GTXTEST, + INTDATAWIDTH, + LOOPBACK0, + LOOPBACK1, + PLLLKDETEN, + PLLPOWERDOWN, + PRBSCNTRESET0, + PRBSCNTRESET1, + REFCLKPWRDNB, + RXBUFRESET0, + RXBUFRESET1, + RXCDRRESET0, + RXCDRRESET1, + RXCHBONDI0, + RXCHBONDI1, + RXCOMMADETUSE0, + RXCOMMADETUSE1, + RXDATAWIDTH0, + RXDATAWIDTH1, + RXDEC8B10BUSE0, + RXDEC8B10BUSE1, + RXENCHANSYNC0, + RXENCHANSYNC1, + RXENEQB0, + RXENEQB1, + RXENMCOMMAALIGN0, + RXENMCOMMAALIGN1, + RXENPCOMMAALIGN0, + RXENPCOMMAALIGN1, + RXENPMAPHASEALIGN0, + RXENPMAPHASEALIGN1, + RXENPRBSTST0, + RXENPRBSTST1, + RXENSAMPLEALIGN0, + RXENSAMPLEALIGN1, + RXEQMIX0, + RXEQMIX1, + RXEQPOLE0, + RXEQPOLE1, + RXGEARBOXSLIP0, + RXGEARBOXSLIP1, + RXN0, + RXN1, + RXP0, + RXP1, + RXPMASETPHASE0, + RXPMASETPHASE1, + RXPOLARITY0, + RXPOLARITY1, + RXPOWERDOWN0, + RXPOWERDOWN1, + RXRESET0, + RXRESET1, + RXSLIDE0, + RXSLIDE1, + RXUSRCLK0, + RXUSRCLK1, + RXUSRCLK20, + RXUSRCLK21, + TXBUFDIFFCTRL0, + TXBUFDIFFCTRL1, + TXBYPASS8B10B0, + TXBYPASS8B10B1, + TXCHARDISPMODE0, + TXCHARDISPMODE1, + TXCHARDISPVAL0, + TXCHARDISPVAL1, + TXCHARISK0, + TXCHARISK1, + TXCOMSTART0, + TXCOMSTART1, + TXCOMTYPE0, + TXCOMTYPE1, + TXDATA0, + TXDATA1, + TXDATAWIDTH0, + TXDATAWIDTH1, + TXDETECTRX0, + TXDETECTRX1, + TXDIFFCTRL0, + TXDIFFCTRL1, + TXELECIDLE0, + TXELECIDLE1, + TXENC8B10BUSE0, + TXENC8B10BUSE1, + TXENPMAPHASEALIGN0, + TXENPMAPHASEALIGN1, + TXENPRBSTST0, + TXENPRBSTST1, + TXHEADER0, + TXHEADER1, + TXINHIBIT0, + TXINHIBIT1, + TXPMASETPHASE0, + TXPMASETPHASE1, + TXPOLARITY0, + TXPOLARITY1, + TXPOWERDOWN0, + TXPOWERDOWN1, + TXPREEMPHASIS0, + TXPREEMPHASIS1, + TXRESET0, + TXRESET1, + TXSEQUENCE0, + TXSEQUENCE1, + TXSTARTSEQ0, + TXSTARTSEQ1, + TXUSRCLK0, + TXUSRCLK1, + TXUSRCLK20, + TXUSRCLK21 + +); + +parameter AC_CAP_DIS_0 = "TRUE"; +parameter AC_CAP_DIS_1 = "TRUE"; +parameter CHAN_BOND_KEEP_ALIGN_0 = "FALSE"; +parameter CHAN_BOND_KEEP_ALIGN_1 = "FALSE"; +parameter CHAN_BOND_MODE_0 = "OFF"; +parameter CHAN_BOND_MODE_1 = "OFF"; +parameter CHAN_BOND_SEQ_2_USE_0 = "FALSE"; +parameter CHAN_BOND_SEQ_2_USE_1 = "FALSE"; +parameter CLKINDC_B = "TRUE"; +parameter CLKRCV_TRST = "TRUE"; +parameter CLK_CORRECT_USE_0 = "TRUE"; +parameter CLK_CORRECT_USE_1 = "TRUE"; +parameter CLK_COR_INSERT_IDLE_FLAG_0 = "FALSE"; +parameter CLK_COR_INSERT_IDLE_FLAG_1 = "FALSE"; +parameter CLK_COR_KEEP_IDLE_0 = "FALSE"; +parameter CLK_COR_KEEP_IDLE_1 = "FALSE"; +parameter CLK_COR_PRECEDENCE_0 = "TRUE"; +parameter CLK_COR_PRECEDENCE_1 = "TRUE"; +parameter CLK_COR_SEQ_2_USE_0 = "FALSE"; +parameter CLK_COR_SEQ_2_USE_1 = "FALSE"; +parameter COMMA_DOUBLE_0 = "FALSE"; +parameter COMMA_DOUBLE_1 = "FALSE"; +parameter DEC_MCOMMA_DETECT_0 = "TRUE"; +parameter DEC_MCOMMA_DETECT_1 = "TRUE"; +parameter DEC_PCOMMA_DETECT_0 = "TRUE"; +parameter DEC_PCOMMA_DETECT_1 = "TRUE"; +parameter DEC_VALID_COMMA_ONLY_0 = "TRUE"; +parameter DEC_VALID_COMMA_ONLY_1 = "TRUE"; +parameter MCOMMA_DETECT_0 = "TRUE"; +parameter MCOMMA_DETECT_1 = "TRUE"; +parameter OVERSAMPLE_MODE = "FALSE"; +parameter PCI_EXPRESS_MODE_0 = "FALSE"; +parameter PCI_EXPRESS_MODE_1 = "FALSE"; +parameter PCOMMA_DETECT_0 = "TRUE"; +parameter PCOMMA_DETECT_1 = "TRUE"; +parameter PLL_FB_DCCEN = "FALSE"; +parameter PLL_SATA_0 = "FALSE"; +parameter PLL_SATA_1 = "FALSE"; +parameter RCV_TERM_GND_0 = "FALSE"; +parameter RCV_TERM_GND_1 = "FALSE"; +parameter RCV_TERM_VTTRX_0 = "FALSE"; +parameter RCV_TERM_VTTRX_1 = "FALSE"; +parameter RXGEARBOX_USE_0 = "FALSE"; +parameter RXGEARBOX_USE_1 = "FALSE"; +parameter RX_BUFFER_USE_0 = "TRUE"; +parameter RX_BUFFER_USE_1 = "TRUE"; +parameter RX_DECODE_SEQ_MATCH_0 = "TRUE"; +parameter RX_DECODE_SEQ_MATCH_1 = "TRUE"; +parameter RX_EN_IDLE_HOLD_CDR = "FALSE"; +parameter RX_EN_IDLE_HOLD_DFE_0 = "TRUE"; +parameter RX_EN_IDLE_HOLD_DFE_1 = "TRUE"; +parameter RX_EN_IDLE_RESET_BUF_0 = "TRUE"; +parameter RX_EN_IDLE_RESET_BUF_1 = "TRUE"; +parameter RX_EN_IDLE_RESET_FR = "TRUE"; +parameter RX_EN_IDLE_RESET_PH = "TRUE"; +parameter RX_LOSS_OF_SYNC_FSM_0 = "FALSE"; +parameter RX_LOSS_OF_SYNC_FSM_1 = "FALSE"; +parameter RX_SLIDE_MODE_0 = "PCS"; +parameter RX_SLIDE_MODE_1 = "PCS"; +parameter RX_STATUS_FMT_0 = "PCIE"; +parameter RX_STATUS_FMT_1 = "PCIE"; +parameter RX_XCLK_SEL_0 = "RXREC"; +parameter RX_XCLK_SEL_1 = "RXREC"; +parameter SIM_MODE = "FAST"; +parameter SIM_PLL_PERDIV2 = 9'h140; +parameter SIM_RECEIVER_DETECT_PASS_0 = "TRUE"; +parameter SIM_RECEIVER_DETECT_PASS_1 = "TRUE"; +parameter TERMINATION_OVRD = "FALSE"; +parameter TXGEARBOX_USE_0 = "FALSE"; +parameter TXGEARBOX_USE_1 = "FALSE"; +parameter TX_BUFFER_USE_0 = "TRUE"; +parameter TX_BUFFER_USE_1 = "TRUE"; +parameter TX_XCLK_SEL_0 = "TXOUT"; +parameter TX_XCLK_SEL_1 = "TXOUT"; +parameter [11:0] TRANS_TIME_FROM_P2_0 = 12'h03c; +parameter [11:0] TRANS_TIME_FROM_P2_1 = 12'h03c; +parameter [13:0] TX_DETECT_RX_CFG_0 = 14'h1832; +parameter [13:0] TX_DETECT_RX_CFG_1 = 14'h1832; +parameter [19:0] PMA_TX_CFG_0 = 20'h80082; +parameter [19:0] PMA_TX_CFG_1 = 20'h80082; +parameter [1:0] CM_TRIM_0 = 2'b10; +parameter [1:0] CM_TRIM_1 = 2'b10; +parameter [23:0] PLL_COM_CFG = 24'h21680a; +parameter [24:0] PMA_RX_CFG_0 = 25'h0f44089; +parameter [24:0] PMA_RX_CFG_1 = 25'h0f44089; +parameter [26:0] PMA_CDR_SCAN_0 = 27'h6404035; +parameter [26:0] PMA_CDR_SCAN_1 = 27'h6404035; +parameter [2:0] GEARBOX_ENDEC_0 = 3'b000; +parameter [2:0] GEARBOX_ENDEC_1 = 3'b000; +parameter [2:0] OOBDETECT_THRESHOLD_0 = 3'b110; +parameter [2:0] OOBDETECT_THRESHOLD_1 = 3'b110; +parameter [2:0] PLL_LKDET_CFG = 3'b101; +parameter [2:0] PLL_TDCC_CFG = 3'b000; +parameter [2:0] SATA_BURST_VAL_0 = 3'b100; +parameter [2:0] SATA_BURST_VAL_1 = 3'b100; +parameter [2:0] SATA_IDLE_VAL_0 = 3'b100; +parameter [2:0] SATA_IDLE_VAL_1 = 3'b100; +parameter [2:0] TXRX_INVERT_0 = 3'b011; +parameter [2:0] TXRX_INVERT_1 = 3'b011; +parameter [2:0] TX_IDLE_DELAY_0 = 3'b010; +parameter [2:0] TX_IDLE_DELAY_1 = 3'b010; +parameter [31:0] PRBS_ERR_THRESHOLD_0 = 32'h00000001; +parameter [31:0] PRBS_ERR_THRESHOLD_1 = 32'h00000001; +parameter [3:0] CHAN_BOND_SEQ_1_ENABLE_0 = 4'b0001; +parameter [3:0] CHAN_BOND_SEQ_1_ENABLE_1 = 4'b0001; +parameter [3:0] CHAN_BOND_SEQ_2_ENABLE_0 = 4'b0000; +parameter [3:0] CHAN_BOND_SEQ_2_ENABLE_1 = 4'b0000; +parameter [3:0] CLK_COR_SEQ_1_ENABLE_0 = 4'b0001; +parameter [3:0] CLK_COR_SEQ_1_ENABLE_1 = 4'b0001; +parameter [3:0] CLK_COR_SEQ_2_ENABLE_0 = 4'b0000; +parameter [3:0] CLK_COR_SEQ_2_ENABLE_1 = 4'b0000; +parameter [3:0] COM_BURST_VAL_0 = 4'b1111; +parameter [3:0] COM_BURST_VAL_1 = 4'b1111; +parameter [3:0] RX_IDLE_HI_CNT_0 = 4'b1000; +parameter [3:0] RX_IDLE_HI_CNT_1 = 4'b1000; +parameter [3:0] RX_IDLE_LO_CNT_0 = 4'b0000; +parameter [3:0] RX_IDLE_LO_CNT_1 = 4'b0000; +parameter [4:0] CDR_PH_ADJ_TIME = 5'b01010; +parameter [4:0] DFE_CAL_TIME = 5'b00110; +parameter [4:0] TERMINATION_CTRL = 5'b10100; +parameter [68:0] PMA_COM_CFG = 69'h0; +parameter [6:0] PMA_RXSYNC_CFG_0 = 7'h0; +parameter [6:0] PMA_RXSYNC_CFG_1 = 7'h0; +parameter [7:0] PLL_CP_CFG = 8'h00; +parameter [7:0] TRANS_TIME_NON_P2_0 = 8'h19; +parameter [7:0] TRANS_TIME_NON_P2_1 = 8'h19; +parameter [9:0] CHAN_BOND_SEQ_1_1_0 = 10'b0101111100; +parameter [9:0] CHAN_BOND_SEQ_1_1_1 = 10'b0101111100; +parameter [9:0] CHAN_BOND_SEQ_1_2_0 = 10'b0000000000; +parameter [9:0] CHAN_BOND_SEQ_1_2_1 = 10'b0000000000; +parameter [9:0] CHAN_BOND_SEQ_1_3_0 = 10'b0000000000; +parameter [9:0] CHAN_BOND_SEQ_1_3_1 = 10'b0000000000; +parameter [9:0] CHAN_BOND_SEQ_1_4_0 = 10'b0000000000; +parameter [9:0] CHAN_BOND_SEQ_1_4_1 = 10'b0000000000; +parameter [9:0] CHAN_BOND_SEQ_2_1_0 = 10'b0000000000; +parameter [9:0] CHAN_BOND_SEQ_2_1_1 = 10'b0000000000; +parameter [9:0] CHAN_BOND_SEQ_2_2_0 = 10'b0000000000; +parameter [9:0] CHAN_BOND_SEQ_2_2_1 = 10'b0000000000; +parameter [9:0] CHAN_BOND_SEQ_2_3_0 = 10'b0000000000; +parameter [9:0] CHAN_BOND_SEQ_2_3_1 = 10'b0000000000; +parameter [9:0] CHAN_BOND_SEQ_2_4_0 = 10'b0000000000; +parameter [9:0] CHAN_BOND_SEQ_2_4_1 = 10'b0000000000; +parameter [9:0] CLK_COR_SEQ_1_1_0 = 10'b0100011100; +parameter [9:0] CLK_COR_SEQ_1_1_1 = 10'b0100011100; +parameter [9:0] CLK_COR_SEQ_1_2_0 = 10'b0000000000; +parameter [9:0] CLK_COR_SEQ_1_2_1 = 10'b0000000000; +parameter [9:0] CLK_COR_SEQ_1_3_0 = 10'b0000000000; +parameter [9:0] CLK_COR_SEQ_1_3_1 = 10'b0000000000; +parameter [9:0] CLK_COR_SEQ_1_4_0 = 10'b0000000000; +parameter [9:0] CLK_COR_SEQ_1_4_1 = 10'b0000000000; +parameter [9:0] CLK_COR_SEQ_2_1_0 = 10'b0000000000; +parameter [9:0] CLK_COR_SEQ_2_1_1 = 10'b0000000000; +parameter [9:0] CLK_COR_SEQ_2_2_0 = 10'b0000000000; +parameter [9:0] CLK_COR_SEQ_2_2_1 = 10'b0000000000; +parameter [9:0] CLK_COR_SEQ_2_3_0 = 10'b0000000000; +parameter [9:0] CLK_COR_SEQ_2_3_1 = 10'b0000000000; +parameter [9:0] CLK_COR_SEQ_2_4_0 = 10'b0000000000; +parameter [9:0] CLK_COR_SEQ_2_4_1 = 10'b0000000000; +parameter [9:0] COMMA_10B_ENABLE_0 = 10'b0001111111; +parameter [9:0] COMMA_10B_ENABLE_1 = 10'b0001111111; +parameter [9:0] DFE_CFG_0 = 10'b1101111011; +parameter [9:0] DFE_CFG_1 = 10'b1101111011; +parameter [9:0] MCOMMA_10B_VALUE_0 = 10'b1010000011; +parameter [9:0] MCOMMA_10B_VALUE_1 = 10'b1010000011; +parameter [9:0] PCOMMA_10B_VALUE_0 = 10'b0101111100; +parameter [9:0] PCOMMA_10B_VALUE_1 = 10'b0101111100; +parameter [9:0] TRANS_TIME_TO_P2_0 = 10'h064; +parameter [9:0] TRANS_TIME_TO_P2_1 = 10'h064; +parameter integer ALIGN_COMMA_WORD_0 = 1; +parameter integer ALIGN_COMMA_WORD_1 = 1; +parameter integer CB2_INH_CC_PERIOD_0 = 8; +parameter integer CB2_INH_CC_PERIOD_1 = 8; +parameter integer CHAN_BOND_1_MAX_SKEW_0 = 7; +parameter integer CHAN_BOND_1_MAX_SKEW_1 = 7; +parameter integer CHAN_BOND_2_MAX_SKEW_0 = 7; +parameter integer CHAN_BOND_2_MAX_SKEW_1 = 7; +parameter integer CHAN_BOND_LEVEL_0 = 0; +parameter integer CHAN_BOND_LEVEL_1 = 0; +parameter integer CHAN_BOND_SEQ_LEN_0 = 1; +parameter integer CHAN_BOND_SEQ_LEN_1 = 1; +parameter integer CLK25_DIVIDER = 10; +parameter integer CLK_COR_ADJ_LEN_0 = 1; +parameter integer CLK_COR_ADJ_LEN_1 = 1; +parameter integer CLK_COR_DET_LEN_0 = 1; +parameter integer CLK_COR_DET_LEN_1 = 1; +parameter integer CLK_COR_MAX_LAT_0 = 20; +parameter integer CLK_COR_MAX_LAT_1 = 20; +parameter integer CLK_COR_MIN_LAT_0 = 18; +parameter integer CLK_COR_MIN_LAT_1 = 18; +parameter integer CLK_COR_REPEAT_WAIT_0 = 0; +parameter integer CLK_COR_REPEAT_WAIT_1 = 0; +parameter integer OOB_CLK_DIVIDER = 6; +parameter integer PLL_DIVSEL_FB = 2; +parameter integer PLL_DIVSEL_REF = 1; +parameter integer PLL_RXDIVSEL_OUT_0 = 1; +parameter integer PLL_RXDIVSEL_OUT_1 = 1; +parameter integer PLL_TXDIVSEL_OUT_0 = 1; +parameter integer PLL_TXDIVSEL_OUT_1 = 1; +parameter integer RX_LOS_INVALID_INCR_0 = 1; +parameter integer RX_LOS_INVALID_INCR_1 = 1; +parameter integer RX_LOS_THRESHOLD_0 = 4; +parameter integer RX_LOS_THRESHOLD_1 = 4; +parameter integer SATA_MAX_BURST_0 = 7; +parameter integer SATA_MAX_BURST_1 = 7; +parameter integer SATA_MAX_INIT_0 = 22; +parameter integer SATA_MAX_INIT_1 = 22; +parameter integer SATA_MAX_WAKE_0 = 7; +parameter integer SATA_MAX_WAKE_1 = 7; +parameter integer SATA_MIN_BURST_0 = 4; +parameter integer SATA_MIN_BURST_1 = 4; +parameter integer SATA_MIN_INIT_0 = 12; +parameter integer SATA_MIN_INIT_1 = 12; +parameter integer SATA_MIN_WAKE_0 = 4; +parameter integer SATA_MIN_WAKE_1 = 4; +parameter integer SIM_GTXRESET_SPEEDUP = 1; +parameter integer TERMINATION_IMP_0 = 50; +parameter integer TERMINATION_IMP_1 = 50; + + +localparam in_delay = 0; +localparam out_delay = 0; +localparam CLK_DELAY = 0; + +output DRDY; +output PHYSTATUS0; +output PHYSTATUS1; +output PLLLKDET; +output REFCLKOUT; +output RESETDONE0; +output RESETDONE1; +output RXBYTEISALIGNED0; +output RXBYTEISALIGNED1; +output RXBYTEREALIGN0; +output RXBYTEREALIGN1; +output RXCHANBONDSEQ0; +output RXCHANBONDSEQ1; +output RXCHANISALIGNED0; +output RXCHANISALIGNED1; +output RXCHANREALIGN0; +output RXCHANREALIGN1; +output RXCOMMADET0; +output RXCOMMADET1; +output RXDATAVALID0; +output RXDATAVALID1; +output RXELECIDLE0; +output RXELECIDLE1; +output RXHEADERVALID0; +output RXHEADERVALID1; +output RXOVERSAMPLEERR0; +output RXOVERSAMPLEERR1; +output RXPRBSERR0; +output RXPRBSERR1; +output RXRECCLK0; +output RXRECCLK1; +output RXSTARTOFSEQ0; +output RXSTARTOFSEQ1; +output RXVALID0; +output RXVALID1; +output TXGEARBOXREADY0; +output TXGEARBOXREADY1; +output TXN0; +output TXN1; +output TXOUTCLK0; +output TXOUTCLK1; +output TXP0; +output TXP1; +output [15:0] DO; +output [1:0] RXLOSSOFSYNC0; +output [1:0] RXLOSSOFSYNC1; +output [1:0] TXBUFSTATUS0; +output [1:0] TXBUFSTATUS1; +output [2:0] DFESENSCAL0; +output [2:0] DFESENSCAL1; +output [2:0] RXBUFSTATUS0; +output [2:0] RXBUFSTATUS1; +output [2:0] RXCLKCORCNT0; +output [2:0] RXCLKCORCNT1; +output [2:0] RXHEADER0; +output [2:0] RXHEADER1; +output [2:0] RXSTATUS0; +output [2:0] RXSTATUS1; +output [31:0] RXDATA0; +output [31:0] RXDATA1; +output [3:0] DFETAP3MONITOR0; +output [3:0] DFETAP3MONITOR1; +output [3:0] DFETAP4MONITOR0; +output [3:0] DFETAP4MONITOR1; +output [3:0] RXCHARISCOMMA0; +output [3:0] RXCHARISCOMMA1; +output [3:0] RXCHARISK0; +output [3:0] RXCHARISK1; +output [3:0] RXCHBONDO0; +output [3:0] RXCHBONDO1; +output [3:0] RXDISPERR0; +output [3:0] RXDISPERR1; +output [3:0] RXNOTINTABLE0; +output [3:0] RXNOTINTABLE1; +output [3:0] RXRUNDISP0; +output [3:0] RXRUNDISP1; +output [3:0] TXKERR0; +output [3:0] TXKERR1; +output [3:0] TXRUNDISP0; +output [3:0] TXRUNDISP1; +output [4:0] DFEEYEDACMONITOR0; +output [4:0] DFEEYEDACMONITOR1; +output [4:0] DFETAP1MONITOR0; +output [4:0] DFETAP1MONITOR1; +output [4:0] DFETAP2MONITOR0; +output [4:0] DFETAP2MONITOR1; +output [5:0] DFECLKDLYADJMONITOR0; +output [5:0] DFECLKDLYADJMONITOR1; + +input CLKIN; +input DCLK; +input DEN; +input DWE; +input GTXRESET; +input INTDATAWIDTH; +input PLLLKDETEN; +input PLLPOWERDOWN; +input PRBSCNTRESET0; +input PRBSCNTRESET1; +input REFCLKPWRDNB; +input RXBUFRESET0; +input RXBUFRESET1; +input RXCDRRESET0; +input RXCDRRESET1; +input RXCOMMADETUSE0; +input RXCOMMADETUSE1; +input RXDEC8B10BUSE0; +input RXDEC8B10BUSE1; +input RXENCHANSYNC0; +input RXENCHANSYNC1; +input RXENEQB0; +input RXENEQB1; +input RXENMCOMMAALIGN0; +input RXENMCOMMAALIGN1; +input RXENPCOMMAALIGN0; +input RXENPCOMMAALIGN1; +input RXENPMAPHASEALIGN0; +input RXENPMAPHASEALIGN1; +input RXENSAMPLEALIGN0; +input RXENSAMPLEALIGN1; +input RXGEARBOXSLIP0; +input RXGEARBOXSLIP1; +input RXN0; +input RXN1; +input RXP0; +input RXP1; +input RXPMASETPHASE0; +input RXPMASETPHASE1; +input RXPOLARITY0; +input RXPOLARITY1; +input RXRESET0; +input RXRESET1; +input RXSLIDE0; +input RXSLIDE1; +input RXUSRCLK0; +input RXUSRCLK1; +input RXUSRCLK20; +input RXUSRCLK21; +input TXCOMSTART0; +input TXCOMSTART1; +input TXCOMTYPE0; +input TXCOMTYPE1; +input TXDETECTRX0; +input TXDETECTRX1; +input TXELECIDLE0; +input TXELECIDLE1; +input TXENC8B10BUSE0; +input TXENC8B10BUSE1; +input TXENPMAPHASEALIGN0; +input TXENPMAPHASEALIGN1; +input TXINHIBIT0; +input TXINHIBIT1; +input TXPMASETPHASE0; +input TXPMASETPHASE1; +input TXPOLARITY0; +input TXPOLARITY1; +input TXRESET0; +input TXRESET1; +input TXSTARTSEQ0; +input TXSTARTSEQ1; +input TXUSRCLK0; +input TXUSRCLK1; +input TXUSRCLK20; +input TXUSRCLK21; +input [13:0] GTXTEST; +input [15:0] DI; +input [1:0] RXDATAWIDTH0; +input [1:0] RXDATAWIDTH1; +input [1:0] RXENPRBSTST0; +input [1:0] RXENPRBSTST1; +input [1:0] RXEQMIX0; +input [1:0] RXEQMIX1; +input [1:0] RXPOWERDOWN0; +input [1:0] RXPOWERDOWN1; +input [1:0] TXDATAWIDTH0; +input [1:0] TXDATAWIDTH1; +input [1:0] TXENPRBSTST0; +input [1:0] TXENPRBSTST1; +input [1:0] TXPOWERDOWN0; +input [1:0] TXPOWERDOWN1; +input [2:0] LOOPBACK0; +input [2:0] LOOPBACK1; +input [2:0] TXBUFDIFFCTRL0; +input [2:0] TXBUFDIFFCTRL1; +input [2:0] TXDIFFCTRL0; +input [2:0] TXDIFFCTRL1; +input [2:0] TXHEADER0; +input [2:0] TXHEADER1; +input [31:0] TXDATA0; +input [31:0] TXDATA1; +input [3:0] DFETAP30; +input [3:0] DFETAP31; +input [3:0] DFETAP40; +input [3:0] DFETAP41; +input [3:0] RXCHBONDI0; +input [3:0] RXCHBONDI1; +input [3:0] RXEQPOLE0; +input [3:0] RXEQPOLE1; +input [3:0] TXBYPASS8B10B0; +input [3:0] TXBYPASS8B10B1; +input [3:0] TXCHARDISPMODE0; +input [3:0] TXCHARDISPMODE1; +input [3:0] TXCHARDISPVAL0; +input [3:0] TXCHARDISPVAL1; +input [3:0] TXCHARISK0; +input [3:0] TXCHARISK1; +input [3:0] TXPREEMPHASIS0; +input [3:0] TXPREEMPHASIS1; +input [4:0] DFETAP10; +input [4:0] DFETAP11; +input [4:0] DFETAP20; +input [4:0] DFETAP21; +input [5:0] DFECLKDLYADJ0; +input [5:0] DFECLKDLYADJ1; +input [6:0] DADDR; +input [6:0] TXSEQUENCE0; +input [6:0] TXSEQUENCE1; + +reg AC_CAP_DIS_0_BINARY; +reg AC_CAP_DIS_1_BINARY; +reg ALIGN_COMMA_WORD_0_BINARY; +reg ALIGN_COMMA_WORD_1_BINARY; +reg CHAN_BOND_KEEP_ALIGN_0_BINARY; +reg CHAN_BOND_KEEP_ALIGN_1_BINARY; +reg [1:0] CHAN_BOND_MODE_0_BINARY; +reg [1:0] CHAN_BOND_MODE_1_BINARY; +reg CHAN_BOND_SEQ_2_USE_0_BINARY; +reg CHAN_BOND_SEQ_2_USE_1_BINARY; +reg CLKINDC_B_BINARY; +reg CLKRCV_TRST_BINARY; +reg CLK_CORRECT_USE_0_BINARY; +reg CLK_CORRECT_USE_1_BINARY; +reg CLK_COR_INSERT_IDLE_FLAG_0_BINARY; +reg CLK_COR_INSERT_IDLE_FLAG_1_BINARY; +reg CLK_COR_KEEP_IDLE_0_BINARY; +reg CLK_COR_KEEP_IDLE_1_BINARY; +reg CLK_COR_PRECEDENCE_0_BINARY; +reg CLK_COR_PRECEDENCE_1_BINARY; +reg CLK_COR_SEQ_2_USE_0_BINARY; +reg CLK_COR_SEQ_2_USE_1_BINARY; +reg COMMA_DOUBLE_0_BINARY; +reg COMMA_DOUBLE_1_BINARY; +reg DEC_MCOMMA_DETECT_0_BINARY; +reg DEC_MCOMMA_DETECT_1_BINARY; +reg DEC_PCOMMA_DETECT_0_BINARY; +reg DEC_PCOMMA_DETECT_1_BINARY; +reg DEC_VALID_COMMA_ONLY_0_BINARY; +reg DEC_VALID_COMMA_ONLY_1_BINARY; +reg MCOMMA_DETECT_0_BINARY; +reg MCOMMA_DETECT_1_BINARY; +reg OVERSAMPLE_MODE_BINARY; +reg PCI_EXPRESS_MODE_0_BINARY; +reg PCI_EXPRESS_MODE_1_BINARY; +reg PCOMMA_DETECT_0_BINARY; +reg PCOMMA_DETECT_1_BINARY; +reg PLL_FB_DCCEN_BINARY; +reg PLL_SATA_0_BINARY; +reg PLL_SATA_1_BINARY; +reg RCV_TERM_GND_0_BINARY; +reg RCV_TERM_GND_1_BINARY; +reg RCV_TERM_VTTRX_0_BINARY; +reg RCV_TERM_VTTRX_1_BINARY; +reg RXGEARBOX_USE_0_BINARY; +reg RXGEARBOX_USE_1_BINARY; +reg RX_BUFFER_USE_0_BINARY; +reg RX_BUFFER_USE_1_BINARY; +reg RX_DECODE_SEQ_MATCH_0_BINARY; +reg RX_DECODE_SEQ_MATCH_1_BINARY; +reg RX_EN_IDLE_HOLD_CDR_BINARY; +reg RX_EN_IDLE_HOLD_DFE_0_BINARY; +reg RX_EN_IDLE_HOLD_DFE_1_BINARY; +reg RX_EN_IDLE_RESET_BUF_0_BINARY; +reg RX_EN_IDLE_RESET_BUF_1_BINARY; +reg RX_EN_IDLE_RESET_FR_BINARY; +reg RX_EN_IDLE_RESET_PH_BINARY; +reg RX_LOSS_OF_SYNC_FSM_0_BINARY; +reg RX_LOSS_OF_SYNC_FSM_1_BINARY; +reg RX_SLIDE_MODE_0_BINARY; +reg RX_SLIDE_MODE_1_BINARY; +reg RX_STATUS_FMT_0_BINARY; +reg RX_STATUS_FMT_1_BINARY; +reg RX_XCLK_SEL_0_BINARY; +reg RX_XCLK_SEL_1_BINARY; +reg SIM_GTXRESET_SPEEDUP_BINARY; +reg SIM_MODE_BINARY; +reg SIM_RECEIVER_DETECT_PASS_0_BINARY; +reg SIM_RECEIVER_DETECT_PASS_1_BINARY; +reg TERMINATION_IMP_0_BINARY; +reg TERMINATION_IMP_1_BINARY; +reg TERMINATION_OVRD_BINARY; +reg TXGEARBOX_USE_0_BINARY; +reg TXGEARBOX_USE_1_BINARY; +reg TX_BUFFER_USE_0_BINARY; +reg TX_BUFFER_USE_1_BINARY; +reg TX_XCLK_SEL_0_BINARY; +reg TX_XCLK_SEL_1_BINARY; +reg [1:0] CHAN_BOND_SEQ_LEN_0_BINARY; +reg [1:0] CHAN_BOND_SEQ_LEN_1_BINARY; +reg [1:0] CLK_COR_ADJ_LEN_0_BINARY; +reg [1:0] CLK_COR_ADJ_LEN_1_BINARY; +reg [1:0] CLK_COR_DET_LEN_0_BINARY; +reg [1:0] CLK_COR_DET_LEN_1_BINARY; +reg [1:0] PLL_RXDIVSEL_OUT_0_BINARY; +reg [1:0] PLL_RXDIVSEL_OUT_1_BINARY; +reg [1:0] PLL_TXDIVSEL_OUT_0_BINARY; +reg [1:0] PLL_TXDIVSEL_OUT_1_BINARY; +reg [2:0] CHAN_BOND_LEVEL_0_BINARY; +reg [2:0] CHAN_BOND_LEVEL_1_BINARY; +reg [2:0] CLK25_DIVIDER_BINARY; +reg [2:0] OOB_CLK_DIVIDER_BINARY; +reg [2:0] OOBDETECT_THRESHOLD_0_BINARY; +reg [2:0] OOBDETECT_THRESHOLD_1_BINARY; +reg [2:0] RX_LOS_INVALID_INCR_0_BINARY; +reg [2:0] RX_LOS_INVALID_INCR_1_BINARY; +reg [2:0] RX_LOS_THRESHOLD_0_BINARY; +reg [2:0] RX_LOS_THRESHOLD_1_BINARY; +reg [3:0] CB2_INH_CC_PERIOD_0_BINARY; +reg [3:0] CB2_INH_CC_PERIOD_1_BINARY; +reg [3:0] CHAN_BOND_1_MAX_SKEW_0_BINARY; +reg [3:0] CHAN_BOND_1_MAX_SKEW_1_BINARY; +reg [3:0] CHAN_BOND_2_MAX_SKEW_0_BINARY; +reg [3:0] CHAN_BOND_2_MAX_SKEW_1_BINARY; +reg [4:0] CLK_COR_REPEAT_WAIT_0_BINARY; +reg [4:0] CLK_COR_REPEAT_WAIT_1_BINARY; +reg [4:0] PLL_DIVSEL_FB_BINARY; +reg [5:0] CLK_COR_MAX_LAT_0_BINARY; +reg [5:0] CLK_COR_MAX_LAT_1_BINARY; +reg [5:0] CLK_COR_MIN_LAT_0_BINARY; +reg [5:0] CLK_COR_MIN_LAT_1_BINARY; +reg [5:0] PLL_DIVSEL_REF_BINARY; +reg [5:0] SATA_MAX_BURST_0_BINARY; +reg [5:0] SATA_MAX_BURST_1_BINARY; +reg [5:0] SATA_MAX_INIT_0_BINARY; +reg [5:0] SATA_MAX_INIT_1_BINARY; +reg [5:0] SATA_MAX_WAKE_0_BINARY; +reg [5:0] SATA_MAX_WAKE_1_BINARY; +reg [5:0] SATA_MIN_BURST_0_BINARY; +reg [5:0] SATA_MIN_BURST_1_BINARY; +reg [5:0] SATA_MIN_INIT_0_BINARY; +reg [5:0] SATA_MIN_INIT_1_BINARY; +reg [5:0] SATA_MIN_WAKE_0_BINARY; +reg [5:0] SATA_MIN_WAKE_1_BINARY; + +tri0 GSR = glbl.GSR; + + +initial begin + + case (PLL_TXDIVSEL_OUT_0) + 1 : PLL_TXDIVSEL_OUT_0_BINARY = 2'b00; + 2 : PLL_TXDIVSEL_OUT_0_BINARY = 2'b01; + 4 : PLL_TXDIVSEL_OUT_0_BINARY = 2'b10; + default : begin + $display("Attribute Syntax Error : The Attribute PLL_TXDIVSEL_OUT_0 on GTX_DUAL instance %m is set to %d. Legal values for this attribute are 1, 2 or 4.", PLL_TXDIVSEL_OUT_0); + $finish; + end + endcase + + case (PLL_RXDIVSEL_OUT_0) + 1 : PLL_RXDIVSEL_OUT_0_BINARY = 2'b00; + 2 : PLL_RXDIVSEL_OUT_0_BINARY = 2'b01; + 4 : PLL_RXDIVSEL_OUT_0_BINARY = 2'b10; + default : begin + $display("Attribute Syntax Error : The Attribute PLL_RXDIVSEL_OUT_0 on GTX_DUAL instance %m is set to %d. Legal values for this attribute are 1, 2 or 4.", PLL_RXDIVSEL_OUT_0); + $finish; + end + endcase + + case (PLL_TXDIVSEL_OUT_1) + 1 : PLL_TXDIVSEL_OUT_1_BINARY = 2'b00; + 2 : PLL_TXDIVSEL_OUT_1_BINARY = 2'b01; + 4 : PLL_TXDIVSEL_OUT_1_BINARY = 2'b10; + default : begin + $display("Attribute Syntax Error : The Attribute PLL_TXDIVSEL_OUT_1 on GTX_DUAL instance %m is set to %d. Legal values for this attribute are 1, 2 or 4.", PLL_TXDIVSEL_OUT_1); + $finish; + end + endcase + + case (PLL_RXDIVSEL_OUT_1) + 1 : PLL_RXDIVSEL_OUT_1_BINARY = 2'b00; + 2 : PLL_RXDIVSEL_OUT_1_BINARY = 2'b01; + 4 : PLL_RXDIVSEL_OUT_1_BINARY = 2'b10; + default : begin + $display("Attribute Syntax Error : The Attribute PLL_RXDIVSEL_OUT_1 on GTX_DUAL instance %m is set to %d. Legal values for this attribute are 1, 2 or 4.", PLL_RXDIVSEL_OUT_1); + $finish; + end + endcase + + case (PLL_DIVSEL_FB) + 1 : PLL_DIVSEL_FB_BINARY = 5'b10000; + 2 : PLL_DIVSEL_FB_BINARY = 5'b00000; + 3 : PLL_DIVSEL_FB_BINARY = 5'b00001; + 4 : PLL_DIVSEL_FB_BINARY = 5'b00010; + 5 : PLL_DIVSEL_FB_BINARY = 5'b00011; + 8 : PLL_DIVSEL_FB_BINARY = 5'b00110; + 10 : PLL_DIVSEL_FB_BINARY = 5'b00111; + default : begin + $display("Attribute Syntax Error : The Attribute PLL_DIVSEL_FB on GTX_DUAL instance %m is set to %d. Legal values for this attribute are 1, 2, 3, 4, 5, 8 or 10.", PLL_DIVSEL_FB); + $finish; + end + endcase + + case (PLL_DIVSEL_REF) + 1 : PLL_DIVSEL_REF_BINARY = 6'b010000; + 2 : PLL_DIVSEL_REF_BINARY = 6'b000000; + 3 : PLL_DIVSEL_REF_BINARY = 6'b000001; + 4 : PLL_DIVSEL_REF_BINARY = 6'b000010; + 5 : PLL_DIVSEL_REF_BINARY = 6'b000011; + 6 : PLL_DIVSEL_REF_BINARY = 6'b000101; + 8 : PLL_DIVSEL_REF_BINARY = 6'b000110; + 10 : PLL_DIVSEL_REF_BINARY = 6'b000111; + 12 : PLL_DIVSEL_REF_BINARY = 6'b001101; + 16 : PLL_DIVSEL_REF_BINARY = 6'b001110; + 20 : PLL_DIVSEL_REF_BINARY = 6'b001111; + default : begin + $display("Attribute Syntax Error : The Attribute PLL_DIVSEL_REF on GTX_DUAL instance %m is set to %d. Legal values for this attribute are 1, 2, 3, 4, 5, 6, 8, 10, 12, 16 or 20.", PLL_DIVSEL_REF); + $finish; + end + endcase + + case (PLL_SATA_0) + "FALSE" : PLL_SATA_0_BINARY = 1'b0; + "TRUE" : PLL_SATA_0_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute PLL_SATA_0 on GTX_DUAL instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", PLL_SATA_0); + $finish; + end + endcase + + case (PLL_SATA_1) + "FALSE" : PLL_SATA_1_BINARY = 1'b0; + "TRUE" : PLL_SATA_1_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute PLL_SATA_1 on GTX_DUAL instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", PLL_SATA_1); + $finish; + end + endcase + + case (OOB_CLK_DIVIDER) + 1 : OOB_CLK_DIVIDER_BINARY = 3'b000; + 2 : OOB_CLK_DIVIDER_BINARY = 3'b001; + 4 : OOB_CLK_DIVIDER_BINARY = 3'b010; + 6 : OOB_CLK_DIVIDER_BINARY = 3'b011; + 8 : OOB_CLK_DIVIDER_BINARY = 3'b100; + 10 : OOB_CLK_DIVIDER_BINARY = 3'b101; + 12 : OOB_CLK_DIVIDER_BINARY = 3'b110; + 14 : OOB_CLK_DIVIDER_BINARY = 3'b111; + default : begin + $display("Attribute Syntax Error : The Attribute OOB_CLK_DIVIDER on GTX_DUAL instance %m is set to %b. Legal values for this attribute are 1, 2, 4, 6, 8, 10, 12 or 14.", OOB_CLK_DIVIDER); + $finish; + end + endcase + + case (OOBDETECT_THRESHOLD_0) + 3'b110 : OOBDETECT_THRESHOLD_0_BINARY = 3'b110; + 3'b111 : OOBDETECT_THRESHOLD_0_BINARY = 3'b111; + default : begin + $display("Attribute Syntax Warning : The Attribute OOBDETECT_THRESHOLD_0 on GTX_DUAL instance %m is set to %b. Legal values for this attribute are 110 or 111.", OOBDETECT_THRESHOLD_0); + //$finish; + end + endcase + + case (OOBDETECT_THRESHOLD_1) + 3'b110 : OOBDETECT_THRESHOLD_1_BINARY = 3'b110; + 3'b111 : OOBDETECT_THRESHOLD_1_BINARY = 3'b111; + default : begin + $display("Attribute Syntax Warning : The Attribute OOBDETECT_THRESHOLD_1 on GTX_DUAL instance %m is set to %b. Legal values for this attribute are 110 or 111.", OOBDETECT_THRESHOLD_1); + //$finish; + end + endcase + + case (AC_CAP_DIS_0) + "FALSE" : AC_CAP_DIS_0_BINARY = 1'b0; + "TRUE" : AC_CAP_DIS_0_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute AC_CAP_DIS_0 on GTX_DUAL instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", AC_CAP_DIS_0); + $finish; + end + endcase + + case (AC_CAP_DIS_1) + "FALSE" : AC_CAP_DIS_1_BINARY = 1'b0; + "TRUE" : AC_CAP_DIS_1_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute AC_CAP_DIS_1 on GTX_DUAL instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", AC_CAP_DIS_1); + $finish; + end + endcase + + case (RCV_TERM_GND_0) + "FALSE" : RCV_TERM_GND_0_BINARY = 1'b0; + "TRUE" : RCV_TERM_GND_0_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute RCV_TERM_GND_0 on GTX_DUAL instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", RCV_TERM_GND_0); + $finish; + end + endcase + + case (RCV_TERM_GND_1) + "FALSE" : RCV_TERM_GND_1_BINARY = 1'b0; + "TRUE" : RCV_TERM_GND_1_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute RCV_TERM_GND_1 on GTX_DUAL instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", RCV_TERM_GND_1); + $finish; + end + endcase + + case (TERMINATION_IMP_0) + 50 : TERMINATION_IMP_0_BINARY = 1'b0; + 75 : TERMINATION_IMP_0_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute TERMINATION_IMP_0 on GTX_DUAL instance %m is set to %d. Legal values for this attribute are 50 or 75.", TERMINATION_IMP_0); + $finish; + end + endcase + + case (TERMINATION_IMP_1) + 50 : TERMINATION_IMP_1_BINARY = 1'b0; + 75 : TERMINATION_IMP_1_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute TERMINATION_IMP_1 on GTX_DUAL instance %m is set to %d. Legal values for this attribute are 50 or 75.", TERMINATION_IMP_1); + $finish; + end + endcase + + case (TERMINATION_OVRD) + "FALSE" : TERMINATION_OVRD_BINARY = 1'b0; + "TRUE" : TERMINATION_OVRD_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute TERMINATION_OVRD on GTX_DUAL instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", TERMINATION_OVRD); + $finish; + end + endcase + + case (RCV_TERM_VTTRX_0) + "FALSE" : RCV_TERM_VTTRX_0_BINARY = 1'b0; + "TRUE" : RCV_TERM_VTTRX_0_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute RCV_TERM_VTTRX_0 on GTX_DUAL instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", RCV_TERM_VTTRX_0); + $finish; + end + endcase + + case (RCV_TERM_VTTRX_1) + "FALSE" : RCV_TERM_VTTRX_1_BINARY = 1'b0; + "TRUE" : RCV_TERM_VTTRX_1_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute RCV_TERM_VTTRX_1 on GTX_DUAL instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", RCV_TERM_VTTRX_1); + $finish; + end + endcase + + case (CLKINDC_B) + "FALSE" : CLKINDC_B_BINARY = 1'b0; + "TRUE" : CLKINDC_B_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute CLKINDC_B on GTX_DUAL instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", CLKINDC_B); + $finish; + end + endcase + + case (PCOMMA_DETECT_0) + "FALSE" : PCOMMA_DETECT_0_BINARY = 1'b0; + "TRUE" : PCOMMA_DETECT_0_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute PCOMMA_DETECT_0 on GTX_DUAL instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", PCOMMA_DETECT_0); + $finish; + end + endcase + + case (MCOMMA_DETECT_0) + "FALSE" : MCOMMA_DETECT_0_BINARY = 1'b0; + "TRUE" : MCOMMA_DETECT_0_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute MCOMMA_DETECT_0 on GTX_DUAL instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", MCOMMA_DETECT_0); + $finish; + end + endcase + + case (COMMA_DOUBLE_0) + "FALSE" : COMMA_DOUBLE_0_BINARY = 1'b0; + "TRUE" : COMMA_DOUBLE_0_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute COMMA_DOUBLE_0 on GTX_DUAL instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", COMMA_DOUBLE_0); + $finish; + end + endcase + + case (ALIGN_COMMA_WORD_0) + 1 : ALIGN_COMMA_WORD_0_BINARY = 1'b0; + 2 : ALIGN_COMMA_WORD_0_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute ALIGN_COMMA_WORD_0 on GTX_DUAL instance %m is set to %d. Legal values for this attribute are 1 or 2.", ALIGN_COMMA_WORD_0); + $finish; + end + endcase + + case (DEC_PCOMMA_DETECT_0) + "FALSE" : DEC_PCOMMA_DETECT_0_BINARY = 1'b0; + "TRUE" : DEC_PCOMMA_DETECT_0_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute DEC_PCOMMA_DETECT_0 on GTX_DUAL instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", DEC_PCOMMA_DETECT_0); + $finish; + end + endcase + + case (DEC_MCOMMA_DETECT_0) + "FALSE" : DEC_MCOMMA_DETECT_0_BINARY = 1'b0; + "TRUE" : DEC_MCOMMA_DETECT_0_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute DEC_MCOMMA_DETECT_0 on GTX_DUAL instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", DEC_MCOMMA_DETECT_0); + $finish; + end + endcase + + case (DEC_VALID_COMMA_ONLY_0) + "FALSE" : DEC_VALID_COMMA_ONLY_0_BINARY = 1'b0; + "TRUE" : DEC_VALID_COMMA_ONLY_0_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute DEC_VALID_COMMA_ONLY_0 on GTX_DUAL instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", DEC_VALID_COMMA_ONLY_0); + $finish; + end + endcase + + case (PCOMMA_DETECT_1) + "FALSE" : PCOMMA_DETECT_1_BINARY = 1'b0; + "TRUE" : PCOMMA_DETECT_1_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute PCOMMA_DETECT_1 on GTX_DUAL instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", PCOMMA_DETECT_1); + $finish; + end + endcase + + case (MCOMMA_DETECT_1) + "FALSE" : MCOMMA_DETECT_1_BINARY = 1'b0; + "TRUE" : MCOMMA_DETECT_1_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute MCOMMA_DETECT_1 on GTX_DUAL instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", MCOMMA_DETECT_1); + $finish; + end + endcase + + case (COMMA_DOUBLE_1) + "FALSE" : COMMA_DOUBLE_1_BINARY = 1'b0; + "TRUE" : COMMA_DOUBLE_1_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute COMMA_DOUBLE_1 on GTX_DUAL instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", COMMA_DOUBLE_1); + $finish; + end + endcase + + case (ALIGN_COMMA_WORD_1) + 1 : ALIGN_COMMA_WORD_1_BINARY = 1'b0; + 2 : ALIGN_COMMA_WORD_1_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute ALIGN_COMMA_WORD_1 on GTX_DUAL instance %m is set to %d. Legal values for this attribute are 1 or 2.", ALIGN_COMMA_WORD_1); + $finish; + end + endcase + + case (DEC_PCOMMA_DETECT_1) + "FALSE" : DEC_PCOMMA_DETECT_1_BINARY = 1'b0; + "TRUE" : DEC_PCOMMA_DETECT_1_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute DEC_PCOMMA_DETECT_1 on GTX_DUAL instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", DEC_PCOMMA_DETECT_1); + $finish; + end + endcase + + case (DEC_MCOMMA_DETECT_1) + "FALSE" : DEC_MCOMMA_DETECT_1_BINARY = 1'b0; + "TRUE" : DEC_MCOMMA_DETECT_1_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute DEC_MCOMMA_DETECT_1 on GTX_DUAL instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", DEC_MCOMMA_DETECT_1); + $finish; + end + endcase + + case (DEC_VALID_COMMA_ONLY_1) + "FALSE" : DEC_VALID_COMMA_ONLY_1_BINARY = 1'b0; + "TRUE" : DEC_VALID_COMMA_ONLY_1_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute DEC_VALID_COMMA_ONLY_1 on GTX_DUAL instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", DEC_VALID_COMMA_ONLY_1); + $finish; + end + endcase + + case (RX_LOSS_OF_SYNC_FSM_0) + "FALSE" : RX_LOSS_OF_SYNC_FSM_0_BINARY = 1'b0; + "TRUE" : RX_LOSS_OF_SYNC_FSM_0_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute RX_LOSS_OF_SYNC_FSM_0 on GTX_DUAL instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", RX_LOSS_OF_SYNC_FSM_0); + $finish; + end + endcase + + case (RX_LOS_INVALID_INCR_0) + 1 : RX_LOS_INVALID_INCR_0_BINARY = 3'b000; + 2 : RX_LOS_INVALID_INCR_0_BINARY = 3'b001; + 4 : RX_LOS_INVALID_INCR_0_BINARY = 3'b010; + 8 : RX_LOS_INVALID_INCR_0_BINARY = 3'b011; + 16 : RX_LOS_INVALID_INCR_0_BINARY = 3'b100; + 32 : RX_LOS_INVALID_INCR_0_BINARY = 3'b101; + 64 : RX_LOS_INVALID_INCR_0_BINARY = 3'b110; + 128 : RX_LOS_INVALID_INCR_0_BINARY = 3'b111; + default : begin + $display("Attribute Syntax Error : The Attribute RX_LOS_INVALID_INCR_0 on GTX_DUAL instance %m is set to %d. Legal values for this attribute are 1, 2, 4, 8, 16, 32, 64 or 128.", RX_LOS_INVALID_INCR_0); + $finish; + end + endcase + + case (RX_LOS_THRESHOLD_0) + 4 : RX_LOS_THRESHOLD_0_BINARY = 3'b000; + 8 : RX_LOS_THRESHOLD_0_BINARY = 3'b001; + 16 : RX_LOS_THRESHOLD_0_BINARY = 3'b010; + 32 : RX_LOS_THRESHOLD_0_BINARY = 3'b011; + 64 : RX_LOS_THRESHOLD_0_BINARY = 3'b100; + 128 : RX_LOS_THRESHOLD_0_BINARY = 3'b101; + 256 : RX_LOS_THRESHOLD_0_BINARY = 3'b110; + 512 : RX_LOS_THRESHOLD_0_BINARY = 3'b111; + default : begin + $display("Attribute Syntax Error : The Attribute RX_LOS_THRESHOLD_0 on GTX_DUAL instance %m is set to %d. Legal values for this attribute are 4, 8, 16, 32, 64, 128, 256 or 512.", RX_LOS_THRESHOLD_0); + $finish; + end + endcase + + case (RX_LOSS_OF_SYNC_FSM_1) + "FALSE" : RX_LOSS_OF_SYNC_FSM_1_BINARY = 1'b0; + "TRUE" : RX_LOSS_OF_SYNC_FSM_1_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute RX_LOSS_OF_SYNC_FSM_1 on GTX_DUAL instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", RX_LOSS_OF_SYNC_FSM_1); + $finish; + end + endcase + + case (RX_LOS_INVALID_INCR_1) + 1 : RX_LOS_INVALID_INCR_1_BINARY = 3'b000; + 2 : RX_LOS_INVALID_INCR_1_BINARY = 3'b001; + 4 : RX_LOS_INVALID_INCR_1_BINARY = 3'b010; + 8 : RX_LOS_INVALID_INCR_1_BINARY = 3'b011; + 16 : RX_LOS_INVALID_INCR_1_BINARY = 3'b100; + 32 : RX_LOS_INVALID_INCR_1_BINARY = 3'b101; + 64 : RX_LOS_INVALID_INCR_1_BINARY = 3'b110; + 128 : RX_LOS_INVALID_INCR_1_BINARY = 3'b111; + default : begin + $display("Attribute Syntax Error : The Attribute RX_LOS_INVALID_INCR_1 on GTX_DUAL instance %m is set to %d. Legal values for this attribute are 1, 2, 4, 8, 16, 32, 64 or 128.", RX_LOS_INVALID_INCR_1); + $finish; + end + endcase + + case (RX_LOS_THRESHOLD_1) + 4 : RX_LOS_THRESHOLD_1_BINARY = 3'b000; + 8 : RX_LOS_THRESHOLD_1_BINARY = 3'b001; + 16 : RX_LOS_THRESHOLD_1_BINARY = 3'b010; + 32 : RX_LOS_THRESHOLD_1_BINARY = 3'b011; + 64 : RX_LOS_THRESHOLD_1_BINARY = 3'b100; + 128 : RX_LOS_THRESHOLD_1_BINARY = 3'b101; + 256 : RX_LOS_THRESHOLD_1_BINARY = 3'b110; + 512 : RX_LOS_THRESHOLD_1_BINARY = 3'b111; + default : begin + $display("Attribute Syntax Error : The Attribute RX_LOS_THRESHOLD_1 on GTX_DUAL instance %m is set to %d. Legal values for this attribute are 4, 8, 16, 32, 64, 128, 256 or 512.", RX_LOS_THRESHOLD_1); + $finish; + end + endcase + + case (RX_BUFFER_USE_0) + "FALSE" : RX_BUFFER_USE_0_BINARY = 1'b0; + "TRUE" : RX_BUFFER_USE_0_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute RX_BUFFER_USE_0 on GTX_DUAL instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", RX_BUFFER_USE_0); + $finish; + end + endcase + + case (RX_DECODE_SEQ_MATCH_0) + "FALSE" : RX_DECODE_SEQ_MATCH_0_BINARY = 1'b0; + "TRUE" : RX_DECODE_SEQ_MATCH_0_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute RX_DECODE_SEQ_MATCH_0 on GTX_DUAL instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", RX_DECODE_SEQ_MATCH_0); + $finish; + end + endcase + + case (RX_BUFFER_USE_1) + "FALSE" : RX_BUFFER_USE_1_BINARY = 1'b0; + "TRUE" : RX_BUFFER_USE_1_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute RX_BUFFER_USE_1 on GTX_DUAL instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", RX_BUFFER_USE_1); + $finish; + end + endcase + + case (RX_DECODE_SEQ_MATCH_1) + "FALSE" : RX_DECODE_SEQ_MATCH_1_BINARY = 1'b0; + "TRUE" : RX_DECODE_SEQ_MATCH_1_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute RX_DECODE_SEQ_MATCH_1 on GTX_DUAL instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", RX_DECODE_SEQ_MATCH_1); + $finish; + end + endcase + + case (CLK_COR_MIN_LAT_0) + 3 : CLK_COR_MIN_LAT_0_BINARY = 6'b000011; + 4 : CLK_COR_MIN_LAT_0_BINARY = 6'b000100; + 5 : CLK_COR_MIN_LAT_0_BINARY = 6'b000101; + 6 : CLK_COR_MIN_LAT_0_BINARY = 6'b000110; + 7 : CLK_COR_MIN_LAT_0_BINARY = 6'b000111; + 8 : CLK_COR_MIN_LAT_0_BINARY = 6'b001000; + 9 : CLK_COR_MIN_LAT_0_BINARY = 6'b001001; + 10 : CLK_COR_MIN_LAT_0_BINARY = 6'b001010; + 11 : CLK_COR_MIN_LAT_0_BINARY = 6'b001011; + 12 : CLK_COR_MIN_LAT_0_BINARY = 6'b001100; + 13 : CLK_COR_MIN_LAT_0_BINARY = 6'b001101; + 14 : CLK_COR_MIN_LAT_0_BINARY = 6'b001110; + 15 : CLK_COR_MIN_LAT_0_BINARY = 6'b001111; + 16 : CLK_COR_MIN_LAT_0_BINARY = 6'b010000; + 17 : CLK_COR_MIN_LAT_0_BINARY = 6'b010001; + 18 : CLK_COR_MIN_LAT_0_BINARY = 6'b010010; + 19 : CLK_COR_MIN_LAT_0_BINARY = 6'b010011; + 20 : CLK_COR_MIN_LAT_0_BINARY = 6'b010100; + 21 : CLK_COR_MIN_LAT_0_BINARY = 6'b010101; + 22 : CLK_COR_MIN_LAT_0_BINARY = 6'b010110; + 23 : CLK_COR_MIN_LAT_0_BINARY = 6'b010111; + 24 : CLK_COR_MIN_LAT_0_BINARY = 6'b011000; + 25 : CLK_COR_MIN_LAT_0_BINARY = 6'b011001; + 26 : CLK_COR_MIN_LAT_0_BINARY = 6'b011010; + 27 : CLK_COR_MIN_LAT_0_BINARY = 6'b011011; + 28 : CLK_COR_MIN_LAT_0_BINARY = 6'b011100; + 29 : CLK_COR_MIN_LAT_0_BINARY = 6'b011101; + 30 : CLK_COR_MIN_LAT_0_BINARY = 6'b011110; + 31 : CLK_COR_MIN_LAT_0_BINARY = 6'b011111; + 32 : CLK_COR_MIN_LAT_0_BINARY = 6'b100000; + 33 : CLK_COR_MIN_LAT_0_BINARY = 6'b100001; + 34 : CLK_COR_MIN_LAT_0_BINARY = 6'b100010; + 35 : CLK_COR_MIN_LAT_0_BINARY = 6'b100011; + 36 : CLK_COR_MIN_LAT_0_BINARY = 6'b100100; + 37 : CLK_COR_MIN_LAT_0_BINARY = 6'b100101; + 38 : CLK_COR_MIN_LAT_0_BINARY = 6'b100110; + 39 : CLK_COR_MIN_LAT_0_BINARY = 6'b100111; + 40 : CLK_COR_MIN_LAT_0_BINARY = 6'b101000; + 41 : CLK_COR_MIN_LAT_0_BINARY = 6'b101001; + 42 : CLK_COR_MIN_LAT_0_BINARY = 6'b101010; + 43 : CLK_COR_MIN_LAT_0_BINARY = 6'b101011; + 44 : CLK_COR_MIN_LAT_0_BINARY = 6'b101100; + 45 : CLK_COR_MIN_LAT_0_BINARY = 6'b101101; + 46 : CLK_COR_MIN_LAT_0_BINARY = 6'b101110; + 47 : CLK_COR_MIN_LAT_0_BINARY = 6'b101111; + 48 : CLK_COR_MIN_LAT_0_BINARY = 6'b110000; + default : begin + $display("Attribute Syntax Error : The Attribute CLK_COR_MIN_LAT_0 on GTX_DUAL instance %m is set to %d. Legal values for this attribute are 3 to 48.", CLK_COR_MIN_LAT_0); + $finish; + end + endcase + + case (CLK_COR_MAX_LAT_0) + 3 : CLK_COR_MAX_LAT_0_BINARY = 6'b000011; + 4 : CLK_COR_MAX_LAT_0_BINARY = 6'b000100; + 5 : CLK_COR_MAX_LAT_0_BINARY = 6'b000101; + 6 : CLK_COR_MAX_LAT_0_BINARY = 6'b000110; + 7 : CLK_COR_MAX_LAT_0_BINARY = 6'b000111; + 8 : CLK_COR_MAX_LAT_0_BINARY = 6'b001000; + 9 : CLK_COR_MAX_LAT_0_BINARY = 6'b001001; + 10 : CLK_COR_MAX_LAT_0_BINARY = 6'b001010; + 11 : CLK_COR_MAX_LAT_0_BINARY = 6'b001011; + 12 : CLK_COR_MAX_LAT_0_BINARY = 6'b001100; + 13 : CLK_COR_MAX_LAT_0_BINARY = 6'b001101; + 14 : CLK_COR_MAX_LAT_0_BINARY = 6'b001110; + 15 : CLK_COR_MAX_LAT_0_BINARY = 6'b001111; + 16 : CLK_COR_MAX_LAT_0_BINARY = 6'b010000; + 17 : CLK_COR_MAX_LAT_0_BINARY = 6'b010001; + 18 : CLK_COR_MAX_LAT_0_BINARY = 6'b010010; + 19 : CLK_COR_MAX_LAT_0_BINARY = 6'b010011; + 20 : CLK_COR_MAX_LAT_0_BINARY = 6'b010100; + 21 : CLK_COR_MAX_LAT_0_BINARY = 6'b010101; + 22 : CLK_COR_MAX_LAT_0_BINARY = 6'b010110; + 23 : CLK_COR_MAX_LAT_0_BINARY = 6'b010111; + 24 : CLK_COR_MAX_LAT_0_BINARY = 6'b011000; + 25 : CLK_COR_MAX_LAT_0_BINARY = 6'b011001; + 26 : CLK_COR_MAX_LAT_0_BINARY = 6'b011010; + 27 : CLK_COR_MAX_LAT_0_BINARY = 6'b011011; + 28 : CLK_COR_MAX_LAT_0_BINARY = 6'b011100; + 29 : CLK_COR_MAX_LAT_0_BINARY = 6'b011101; + 30 : CLK_COR_MAX_LAT_0_BINARY = 6'b011110; + 31 : CLK_COR_MAX_LAT_0_BINARY = 6'b011111; + 32 : CLK_COR_MAX_LAT_0_BINARY = 6'b100000; + 33 : CLK_COR_MAX_LAT_0_BINARY = 6'b100001; + 34 : CLK_COR_MAX_LAT_0_BINARY = 6'b100010; + 35 : CLK_COR_MAX_LAT_0_BINARY = 6'b100011; + 36 : CLK_COR_MAX_LAT_0_BINARY = 6'b100100; + 37 : CLK_COR_MAX_LAT_0_BINARY = 6'b100101; + 38 : CLK_COR_MAX_LAT_0_BINARY = 6'b100110; + 39 : CLK_COR_MAX_LAT_0_BINARY = 6'b100111; + 40 : CLK_COR_MAX_LAT_0_BINARY = 6'b101000; + 41 : CLK_COR_MAX_LAT_0_BINARY = 6'b101001; + 42 : CLK_COR_MAX_LAT_0_BINARY = 6'b101010; + 43 : CLK_COR_MAX_LAT_0_BINARY = 6'b101011; + 44 : CLK_COR_MAX_LAT_0_BINARY = 6'b101100; + 45 : CLK_COR_MAX_LAT_0_BINARY = 6'b101101; + 46 : CLK_COR_MAX_LAT_0_BINARY = 6'b101110; + 47 : CLK_COR_MAX_LAT_0_BINARY = 6'b101111; + 48 : CLK_COR_MAX_LAT_0_BINARY = 6'b110000; + default : begin + $display("Attribute Syntax Error : The Attribute CLK_COR_MAX_LAT_0 on GTX_DUAL instance %m is set to %d. Legal values for this attribute are 3 to 48.", CLK_COR_MAX_LAT_0); + $finish; + end + endcase + + case (CLK_CORRECT_USE_0) + "FALSE" : CLK_CORRECT_USE_0_BINARY = 1'b0; + "TRUE" : CLK_CORRECT_USE_0_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute CLK_CORRECT_USE_0 on GTX_DUAL instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", CLK_CORRECT_USE_0); + $finish; + end + endcase + + case (CLK_COR_PRECEDENCE_0) + "FALSE" : CLK_COR_PRECEDENCE_0_BINARY = 1'b0; + "TRUE" : CLK_COR_PRECEDENCE_0_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute CLK_COR_PRECEDENCE_0 on GTX_DUAL instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", CLK_COR_PRECEDENCE_0); + $finish; + end + endcase + + case (CLK_COR_DET_LEN_0) + 1 : CLK_COR_DET_LEN_0_BINARY = 2'b00; + 2 : CLK_COR_DET_LEN_0_BINARY = 2'b01; + 3 : CLK_COR_DET_LEN_0_BINARY = 2'b10; + 4 : CLK_COR_DET_LEN_0_BINARY = 2'b11; + default : begin + $display("Attribute Syntax Error : The Attribute CLK_COR_DET_LEN_0 on GTX_DUAL instance %m is set to %d. Legal values for this attribute are 1, 2, 3 or 4.", CLK_COR_DET_LEN_0); + $finish; + end + endcase + + case (CLK_COR_ADJ_LEN_0) + 1 : CLK_COR_ADJ_LEN_0_BINARY = 2'b00; + 2 : CLK_COR_ADJ_LEN_0_BINARY = 2'b01; + 3 : CLK_COR_ADJ_LEN_0_BINARY = 2'b10; + 4 : CLK_COR_ADJ_LEN_0_BINARY = 2'b11; + default : begin + $display("Attribute Syntax Error : The Attribute CLK_COR_ADJ_LEN_0 on GTX_DUAL instance %m is set to %d. Legal values for this attribute are 1, 2, 3 or 4.", CLK_COR_ADJ_LEN_0); + $finish; + end + endcase + + case (CLK_COR_KEEP_IDLE_0) + "FALSE" : CLK_COR_KEEP_IDLE_0_BINARY = 1'b0; + "TRUE" : CLK_COR_KEEP_IDLE_0_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute CLK_COR_KEEP_IDLE_0 on GTX_DUAL instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", CLK_COR_KEEP_IDLE_0); + $finish; + end + endcase + + case (CLK_COR_INSERT_IDLE_FLAG_0) + "FALSE" : CLK_COR_INSERT_IDLE_FLAG_0_BINARY = 1'b0; + "TRUE" : CLK_COR_INSERT_IDLE_FLAG_0_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute CLK_COR_INSERT_IDLE_FLAG_0 on GTX_DUAL instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", CLK_COR_INSERT_IDLE_FLAG_0); + $finish; + end + endcase + + case (CLK_COR_REPEAT_WAIT_0) + 0 : CLK_COR_REPEAT_WAIT_0_BINARY = 5'b00000; + 1 : CLK_COR_REPEAT_WAIT_0_BINARY = 5'b00001; + 2 : CLK_COR_REPEAT_WAIT_0_BINARY = 5'b00010; + 3 : CLK_COR_REPEAT_WAIT_0_BINARY = 5'b00011; + 4 : CLK_COR_REPEAT_WAIT_0_BINARY = 5'b00100; + 5 : CLK_COR_REPEAT_WAIT_0_BINARY = 5'b00101; + 6 : CLK_COR_REPEAT_WAIT_0_BINARY = 5'b00110; + 7 : CLK_COR_REPEAT_WAIT_0_BINARY = 5'b00111; + 8 : CLK_COR_REPEAT_WAIT_0_BINARY = 5'b01000; + 9 : CLK_COR_REPEAT_WAIT_0_BINARY = 5'b01001; + 10 : CLK_COR_REPEAT_WAIT_0_BINARY = 5'b01010; + 11 : CLK_COR_REPEAT_WAIT_0_BINARY = 5'b01011; + 12 : CLK_COR_REPEAT_WAIT_0_BINARY = 5'b01100; + 13 : CLK_COR_REPEAT_WAIT_0_BINARY = 5'b01101; + 14 : CLK_COR_REPEAT_WAIT_0_BINARY = 5'b01110; + 15 : CLK_COR_REPEAT_WAIT_0_BINARY = 5'b01111; + 16 : CLK_COR_REPEAT_WAIT_0_BINARY = 5'b10000; + 17 : CLK_COR_REPEAT_WAIT_0_BINARY = 5'b10001; + 18 : CLK_COR_REPEAT_WAIT_0_BINARY = 5'b10010; + 19 : CLK_COR_REPEAT_WAIT_0_BINARY = 5'b10011; + 20 : CLK_COR_REPEAT_WAIT_0_BINARY = 5'b10100; + 21 : CLK_COR_REPEAT_WAIT_0_BINARY = 5'b10101; + 22 : CLK_COR_REPEAT_WAIT_0_BINARY = 5'b10110; + 23 : CLK_COR_REPEAT_WAIT_0_BINARY = 5'b10111; + 24 : CLK_COR_REPEAT_WAIT_0_BINARY = 5'b11000; + 25 : CLK_COR_REPEAT_WAIT_0_BINARY = 5'b11001; + 26 : CLK_COR_REPEAT_WAIT_0_BINARY = 5'b11010; + 27 : CLK_COR_REPEAT_WAIT_0_BINARY = 5'b11011; + 28 : CLK_COR_REPEAT_WAIT_0_BINARY = 5'b11100; + 29 : CLK_COR_REPEAT_WAIT_0_BINARY = 5'b11101; + 30 : CLK_COR_REPEAT_WAIT_0_BINARY = 5'b11110; + 31 : CLK_COR_REPEAT_WAIT_0_BINARY = 5'b11111; + default : begin + $display("Attribute Syntax Error : The Attribute CLK_COR_REPEAT_WAIT_0 on GTX_DUAL instance %m is set to %d. Legal values for this attribute are 0 to 31.", CLK_COR_REPEAT_WAIT_0); + $finish; + end + endcase + + case (CLK_COR_SEQ_2_USE_0) + "FALSE" : CLK_COR_SEQ_2_USE_0_BINARY = 1'b0; + "TRUE" : CLK_COR_SEQ_2_USE_0_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute CLK_COR_SEQ_2_USE_0 on GTX_DUAL instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", CLK_COR_SEQ_2_USE_0); + $finish; + end + endcase + + case (CLK_COR_MIN_LAT_1) + 3 : CLK_COR_MIN_LAT_1_BINARY = 6'b000011; + 4 : CLK_COR_MIN_LAT_1_BINARY = 6'b000100; + 5 : CLK_COR_MIN_LAT_1_BINARY = 6'b000101; + 6 : CLK_COR_MIN_LAT_1_BINARY = 6'b000110; + 7 : CLK_COR_MIN_LAT_1_BINARY = 6'b000111; + 8 : CLK_COR_MIN_LAT_1_BINARY = 6'b001000; + 9 : CLK_COR_MIN_LAT_1_BINARY = 6'b001001; + 10 : CLK_COR_MIN_LAT_1_BINARY = 6'b001010; + 11 : CLK_COR_MIN_LAT_1_BINARY = 6'b001011; + 12 : CLK_COR_MIN_LAT_1_BINARY = 6'b001100; + 13 : CLK_COR_MIN_LAT_1_BINARY = 6'b001101; + 14 : CLK_COR_MIN_LAT_1_BINARY = 6'b001110; + 15 : CLK_COR_MIN_LAT_1_BINARY = 6'b001111; + 16 : CLK_COR_MIN_LAT_1_BINARY = 6'b010000; + 17 : CLK_COR_MIN_LAT_1_BINARY = 6'b010001; + 18 : CLK_COR_MIN_LAT_1_BINARY = 6'b010010; + 19 : CLK_COR_MIN_LAT_1_BINARY = 6'b010011; + 20 : CLK_COR_MIN_LAT_1_BINARY = 6'b010100; + 21 : CLK_COR_MIN_LAT_1_BINARY = 6'b010101; + 22 : CLK_COR_MIN_LAT_1_BINARY = 6'b010110; + 23 : CLK_COR_MIN_LAT_1_BINARY = 6'b010111; + 24 : CLK_COR_MIN_LAT_1_BINARY = 6'b011000; + 25 : CLK_COR_MIN_LAT_1_BINARY = 6'b011001; + 26 : CLK_COR_MIN_LAT_1_BINARY = 6'b011010; + 27 : CLK_COR_MIN_LAT_1_BINARY = 6'b011011; + 28 : CLK_COR_MIN_LAT_1_BINARY = 6'b011100; + 29 : CLK_COR_MIN_LAT_1_BINARY = 6'b011101; + 30 : CLK_COR_MIN_LAT_1_BINARY = 6'b011110; + 31 : CLK_COR_MIN_LAT_1_BINARY = 6'b011111; + 32 : CLK_COR_MIN_LAT_1_BINARY = 6'b100000; + 33 : CLK_COR_MIN_LAT_1_BINARY = 6'b100001; + 34 : CLK_COR_MIN_LAT_1_BINARY = 6'b100010; + 35 : CLK_COR_MIN_LAT_1_BINARY = 6'b100011; + 36 : CLK_COR_MIN_LAT_1_BINARY = 6'b100100; + 37 : CLK_COR_MIN_LAT_1_BINARY = 6'b100101; + 38 : CLK_COR_MIN_LAT_1_BINARY = 6'b100110; + 39 : CLK_COR_MIN_LAT_1_BINARY = 6'b100111; + 40 : CLK_COR_MIN_LAT_1_BINARY = 6'b101000; + 41 : CLK_COR_MIN_LAT_1_BINARY = 6'b101001; + 42 : CLK_COR_MIN_LAT_1_BINARY = 6'b101010; + 43 : CLK_COR_MIN_LAT_1_BINARY = 6'b101011; + 44 : CLK_COR_MIN_LAT_1_BINARY = 6'b101100; + 45 : CLK_COR_MIN_LAT_1_BINARY = 6'b101101; + 46 : CLK_COR_MIN_LAT_1_BINARY = 6'b101110; + 47 : CLK_COR_MIN_LAT_1_BINARY = 6'b101111; + 48 : CLK_COR_MIN_LAT_1_BINARY = 6'b110000; + default : begin + $display("Attribute Syntax Error : The Attribute CLK_COR_MIN_LAT_1 on GTX_DUAL instance %m is set to %d. Legal values for this attribute are 3 to 48.", CLK_COR_MIN_LAT_1); + $finish; + end + endcase + + case (CLK_COR_MAX_LAT_1) + 3 : CLK_COR_MAX_LAT_1_BINARY = 6'b000011; + 4 : CLK_COR_MAX_LAT_1_BINARY = 6'b000100; + 5 : CLK_COR_MAX_LAT_1_BINARY = 6'b000101; + 6 : CLK_COR_MAX_LAT_1_BINARY = 6'b000110; + 7 : CLK_COR_MAX_LAT_1_BINARY = 6'b000111; + 8 : CLK_COR_MAX_LAT_1_BINARY = 6'b001000; + 9 : CLK_COR_MAX_LAT_1_BINARY = 6'b001001; + 10 : CLK_COR_MAX_LAT_1_BINARY = 6'b001010; + 11 : CLK_COR_MAX_LAT_1_BINARY = 6'b001011; + 12 : CLK_COR_MAX_LAT_1_BINARY = 6'b001100; + 13 : CLK_COR_MAX_LAT_1_BINARY = 6'b001101; + 14 : CLK_COR_MAX_LAT_1_BINARY = 6'b001110; + 15 : CLK_COR_MAX_LAT_1_BINARY = 6'b001111; + 16 : CLK_COR_MAX_LAT_1_BINARY = 6'b010000; + 17 : CLK_COR_MAX_LAT_1_BINARY = 6'b010001; + 18 : CLK_COR_MAX_LAT_1_BINARY = 6'b010010; + 19 : CLK_COR_MAX_LAT_1_BINARY = 6'b010011; + 20 : CLK_COR_MAX_LAT_1_BINARY = 6'b010100; + 21 : CLK_COR_MAX_LAT_1_BINARY = 6'b010101; + 22 : CLK_COR_MAX_LAT_1_BINARY = 6'b010110; + 23 : CLK_COR_MAX_LAT_1_BINARY = 6'b010111; + 24 : CLK_COR_MAX_LAT_1_BINARY = 6'b011000; + 25 : CLK_COR_MAX_LAT_1_BINARY = 6'b011001; + 26 : CLK_COR_MAX_LAT_1_BINARY = 6'b011010; + 27 : CLK_COR_MAX_LAT_1_BINARY = 6'b011011; + 28 : CLK_COR_MAX_LAT_1_BINARY = 6'b011100; + 29 : CLK_COR_MAX_LAT_1_BINARY = 6'b011101; + 30 : CLK_COR_MAX_LAT_1_BINARY = 6'b011110; + 31 : CLK_COR_MAX_LAT_1_BINARY = 6'b011111; + 32 : CLK_COR_MAX_LAT_1_BINARY = 6'b100000; + 33 : CLK_COR_MAX_LAT_1_BINARY = 6'b100001; + 34 : CLK_COR_MAX_LAT_1_BINARY = 6'b100010; + 35 : CLK_COR_MAX_LAT_1_BINARY = 6'b100011; + 36 : CLK_COR_MAX_LAT_1_BINARY = 6'b100100; + 37 : CLK_COR_MAX_LAT_1_BINARY = 6'b100101; + 38 : CLK_COR_MAX_LAT_1_BINARY = 6'b100110; + 39 : CLK_COR_MAX_LAT_1_BINARY = 6'b100111; + 40 : CLK_COR_MAX_LAT_1_BINARY = 6'b101000; + 41 : CLK_COR_MAX_LAT_1_BINARY = 6'b101001; + 42 : CLK_COR_MAX_LAT_1_BINARY = 6'b101010; + 43 : CLK_COR_MAX_LAT_1_BINARY = 6'b101011; + 44 : CLK_COR_MAX_LAT_1_BINARY = 6'b101100; + 45 : CLK_COR_MAX_LAT_1_BINARY = 6'b101101; + 46 : CLK_COR_MAX_LAT_1_BINARY = 6'b101110; + 47 : CLK_COR_MAX_LAT_1_BINARY = 6'b101111; + 48 : CLK_COR_MAX_LAT_1_BINARY = 6'b110000; + default : begin + $display("Attribute Syntax Error : The Attribute CLK_COR_MAX_LAT_1 on GTX_DUAL instance %m is set to %d. Legal values for this attribute are 3 to 48.", CLK_COR_MAX_LAT_1); + $finish; + end + endcase + + case (CLK_CORRECT_USE_1) + "FALSE" : CLK_CORRECT_USE_1_BINARY = 1'b0; + "TRUE" : CLK_CORRECT_USE_1_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute CLK_CORRECT_USE_1 on GTX_DUAL instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", CLK_CORRECT_USE_1); + $finish; + end + endcase + + case (CLK_COR_PRECEDENCE_1) + "FALSE" : CLK_COR_PRECEDENCE_1_BINARY = 1'b0; + "TRUE" : CLK_COR_PRECEDENCE_1_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute CLK_COR_PRECEDENCE_1 on GTX_DUAL instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", CLK_COR_PRECEDENCE_1); + $finish; + end + endcase + + case (CLK_COR_DET_LEN_1) + 1 : CLK_COR_DET_LEN_1_BINARY = 2'b00; + 2 : CLK_COR_DET_LEN_1_BINARY = 2'b01; + 3 : CLK_COR_DET_LEN_1_BINARY = 2'b10; + 4 : CLK_COR_DET_LEN_1_BINARY = 2'b11; + default : begin + $display("Attribute Syntax Error : The Attribute CLK_COR_DET_LEN_1 on GTX_DUAL instance %m is set to %d. Legal values for this attribute are 1, 2, 3 or 4.", CLK_COR_DET_LEN_1); + $finish; + end + endcase + + case (CLK_COR_ADJ_LEN_1) + 1 : CLK_COR_ADJ_LEN_1_BINARY = 2'b00; + 2 : CLK_COR_ADJ_LEN_1_BINARY = 2'b01; + 3 : CLK_COR_ADJ_LEN_1_BINARY = 2'b10; + 4 : CLK_COR_ADJ_LEN_1_BINARY = 2'b11; + default : begin + $display("Attribute Syntax Error : The Attribute CLK_COR_ADJ_LEN_1 on GTX_DUAL instance %m is set to %d. Legal values for this attribute are 1, 2, 3 or 4.", CLK_COR_ADJ_LEN_1); + $finish; + end + endcase + + case (CLK_COR_KEEP_IDLE_1) + "FALSE" : CLK_COR_KEEP_IDLE_1_BINARY = 1'b0; + "TRUE" : CLK_COR_KEEP_IDLE_1_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute CLK_COR_KEEP_IDLE_1 on GTX_DUAL instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", CLK_COR_KEEP_IDLE_1); + $finish; + end + endcase + + case (CLK_COR_INSERT_IDLE_FLAG_1) + "FALSE" : CLK_COR_INSERT_IDLE_FLAG_1_BINARY = 1'b0; + "TRUE" : CLK_COR_INSERT_IDLE_FLAG_1_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute CLK_COR_INSERT_IDLE_FLAG_1 on GTX_DUAL instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", CLK_COR_INSERT_IDLE_FLAG_1); + $finish; + end + endcase + + case (CLK_COR_REPEAT_WAIT_1) + 0 : CLK_COR_REPEAT_WAIT_1_BINARY = 5'b00000; + 1 : CLK_COR_REPEAT_WAIT_1_BINARY = 5'b00001; + 2 : CLK_COR_REPEAT_WAIT_1_BINARY = 5'b00010; + 3 : CLK_COR_REPEAT_WAIT_1_BINARY = 5'b00011; + 4 : CLK_COR_REPEAT_WAIT_1_BINARY = 5'b00100; + 5 : CLK_COR_REPEAT_WAIT_1_BINARY = 5'b00101; + 6 : CLK_COR_REPEAT_WAIT_1_BINARY = 5'b00110; + 7 : CLK_COR_REPEAT_WAIT_1_BINARY = 5'b00111; + 8 : CLK_COR_REPEAT_WAIT_1_BINARY = 5'b01000; + 9 : CLK_COR_REPEAT_WAIT_1_BINARY = 5'b01001; + 10 : CLK_COR_REPEAT_WAIT_1_BINARY = 5'b01010; + 11 : CLK_COR_REPEAT_WAIT_1_BINARY = 5'b01011; + 12 : CLK_COR_REPEAT_WAIT_1_BINARY = 5'b01100; + 13 : CLK_COR_REPEAT_WAIT_1_BINARY = 5'b01101; + 14 : CLK_COR_REPEAT_WAIT_1_BINARY = 5'b01110; + 15 : CLK_COR_REPEAT_WAIT_1_BINARY = 5'b01111; + 16 : CLK_COR_REPEAT_WAIT_1_BINARY = 5'b10000; + 17 : CLK_COR_REPEAT_WAIT_1_BINARY = 5'b10001; + 18 : CLK_COR_REPEAT_WAIT_1_BINARY = 5'b10010; + 19 : CLK_COR_REPEAT_WAIT_1_BINARY = 5'b10011; + 20 : CLK_COR_REPEAT_WAIT_1_BINARY = 5'b10100; + 21 : CLK_COR_REPEAT_WAIT_1_BINARY = 5'b10101; + 22 : CLK_COR_REPEAT_WAIT_1_BINARY = 5'b10110; + 23 : CLK_COR_REPEAT_WAIT_1_BINARY = 5'b10111; + 24 : CLK_COR_REPEAT_WAIT_1_BINARY = 5'b11000; + 25 : CLK_COR_REPEAT_WAIT_1_BINARY = 5'b11001; + 26 : CLK_COR_REPEAT_WAIT_1_BINARY = 5'b11010; + 27 : CLK_COR_REPEAT_WAIT_1_BINARY = 5'b11011; + 28 : CLK_COR_REPEAT_WAIT_1_BINARY = 5'b11100; + 29 : CLK_COR_REPEAT_WAIT_1_BINARY = 5'b11101; + 30 : CLK_COR_REPEAT_WAIT_1_BINARY = 5'b11110; + 31 : CLK_COR_REPEAT_WAIT_1_BINARY = 5'b11111; + default : begin + $display("Attribute Syntax Error : The Attribute CLK_COR_REPEAT_WAIT_1 on GTX_DUAL instance %m is set to %d. Legal values for this attribute are 0 to 31.", CLK_COR_REPEAT_WAIT_1); + $finish; + end + endcase + + case (CLK_COR_SEQ_2_USE_1) + "FALSE" : CLK_COR_SEQ_2_USE_1_BINARY = 1'b0; + "TRUE" : CLK_COR_SEQ_2_USE_1_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute CLK_COR_SEQ_2_USE_1 on GTX_DUAL instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", CLK_COR_SEQ_2_USE_1); + $finish; + end + endcase + + case (CHAN_BOND_MODE_0) + "OFF" : CHAN_BOND_MODE_0_BINARY = 2'b00; + "MASTER" : CHAN_BOND_MODE_0_BINARY = 2'b01; + "SLAVE" : CHAN_BOND_MODE_0_BINARY = 2'b10; + default : begin + $display("Attribute Syntax Error : The Attribute CHAN_BOND_MODE_0 on GTX_DUAL instance %m is set to %s. Legal values for this attribute are OFF, MASTER or SLAVE.", CHAN_BOND_MODE_0); + $finish; + end + endcase + + case (CHAN_BOND_LEVEL_0) + 0 : CHAN_BOND_LEVEL_0_BINARY = 3'b000; + 1 : CHAN_BOND_LEVEL_0_BINARY = 3'b001; + 2 : CHAN_BOND_LEVEL_0_BINARY = 3'b010; + 3 : CHAN_BOND_LEVEL_0_BINARY = 3'b011; + 4 : CHAN_BOND_LEVEL_0_BINARY = 3'b100; + 5 : CHAN_BOND_LEVEL_0_BINARY = 3'b101; + 6 : CHAN_BOND_LEVEL_0_BINARY = 3'b110; + 7 : CHAN_BOND_LEVEL_0_BINARY = 3'b111; + default : begin + $display("Attribute Syntax Error : The Attribute CHAN_BOND_LEVEL_0 on GTX_DUAL instance %m is set to %d. Legal values for this attribute are 0 to 7.", CHAN_BOND_LEVEL_0); + $finish; + end + endcase + + case (CHAN_BOND_SEQ_LEN_0) + 1 : CHAN_BOND_SEQ_LEN_0_BINARY = 2'b00; + 2 : CHAN_BOND_SEQ_LEN_0_BINARY = 2'b01; + 3 : CHAN_BOND_SEQ_LEN_0_BINARY = 2'b10; + 4 : CHAN_BOND_SEQ_LEN_0_BINARY = 2'b11; + default : begin + $display("Attribute Syntax Error : The Attribute CHAN_BOND_SEQ_LEN_0 on GTX_DUAL instance %m is set to %d. Legal values for this attribute are 1, 2, 3 or 4.", CHAN_BOND_SEQ_LEN_0); + $finish; + end + endcase + + case (CHAN_BOND_SEQ_2_USE_0) + "FALSE" : CHAN_BOND_SEQ_2_USE_0_BINARY = 1'b0; + "TRUE" : CHAN_BOND_SEQ_2_USE_0_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute CHAN_BOND_SEQ_2_USE_0 on GTX_DUAL instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", CHAN_BOND_SEQ_2_USE_0); + $finish; + end + endcase + + case (CHAN_BOND_1_MAX_SKEW_0) + 1 : CHAN_BOND_1_MAX_SKEW_0_BINARY = 4'b0001; + 2 : CHAN_BOND_1_MAX_SKEW_0_BINARY = 4'b0010; + 3 : CHAN_BOND_1_MAX_SKEW_0_BINARY = 4'b0011; + 4 : CHAN_BOND_1_MAX_SKEW_0_BINARY = 4'b0100; + 5 : CHAN_BOND_1_MAX_SKEW_0_BINARY = 4'b0101; + 6 : CHAN_BOND_1_MAX_SKEW_0_BINARY = 4'b0110; + 7 : CHAN_BOND_1_MAX_SKEW_0_BINARY = 4'b0111; + 8 : CHAN_BOND_1_MAX_SKEW_0_BINARY = 4'b1000; + 9 : CHAN_BOND_1_MAX_SKEW_0_BINARY = 4'b1001; + 10 : CHAN_BOND_1_MAX_SKEW_0_BINARY = 4'b1010; + 11 : CHAN_BOND_1_MAX_SKEW_0_BINARY = 4'b1011; + 12 : CHAN_BOND_1_MAX_SKEW_0_BINARY = 4'b1100; + 13 : CHAN_BOND_1_MAX_SKEW_0_BINARY = 4'b1101; + 14 : CHAN_BOND_1_MAX_SKEW_0_BINARY = 4'b1110; + default : begin + $display("Attribute Syntax Error : The Attribute CHAN_BOND_1_MAX_SKEW_0 on GTX_DUAL instance %m is set to %d. Legal values for this attribute are 1 to 14.", CHAN_BOND_1_MAX_SKEW_0); + $finish; + end + endcase + + case (CHAN_BOND_2_MAX_SKEW_0) + 1 : CHAN_BOND_2_MAX_SKEW_0_BINARY = 4'b0001; + 2 : CHAN_BOND_2_MAX_SKEW_0_BINARY = 4'b0010; + 3 : CHAN_BOND_2_MAX_SKEW_0_BINARY = 4'b0011; + 4 : CHAN_BOND_2_MAX_SKEW_0_BINARY = 4'b0100; + 5 : CHAN_BOND_2_MAX_SKEW_0_BINARY = 4'b0101; + 6 : CHAN_BOND_2_MAX_SKEW_0_BINARY = 4'b0110; + 7 : CHAN_BOND_2_MAX_SKEW_0_BINARY = 4'b0111; + 8 : CHAN_BOND_2_MAX_SKEW_0_BINARY = 4'b1000; + 9 : CHAN_BOND_2_MAX_SKEW_0_BINARY = 4'b1001; + 10 : CHAN_BOND_2_MAX_SKEW_0_BINARY = 4'b1010; + 11 : CHAN_BOND_2_MAX_SKEW_0_BINARY = 4'b1011; + 12 : CHAN_BOND_2_MAX_SKEW_0_BINARY = 4'b1100; + 13 : CHAN_BOND_2_MAX_SKEW_0_BINARY = 4'b1101; + 14 : CHAN_BOND_2_MAX_SKEW_0_BINARY = 4'b1110; + default : begin + $display("Attribute Syntax Error : The Attribute CHAN_BOND_2_MAX_SKEW_0 on GTX_DUAL instance %m is set to %d. Legal values for this attribute are 1 to 14.", CHAN_BOND_2_MAX_SKEW_0); + $finish; + end + endcase + + case (CHAN_BOND_KEEP_ALIGN_0) + "FALSE" : CHAN_BOND_KEEP_ALIGN_0_BINARY = 1'b0; + "TRUE" : CHAN_BOND_KEEP_ALIGN_0_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute CHAN_BOND_KEEP_ALIGN_0 on GTX_DUAL instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", CHAN_BOND_KEEP_ALIGN_0); + $finish; + end + endcase + + case (CB2_INH_CC_PERIOD_0) + 0 : CB2_INH_CC_PERIOD_0_BINARY = 4'b0000; + 1 : CB2_INH_CC_PERIOD_0_BINARY = 4'b0001; + 2 : CB2_INH_CC_PERIOD_0_BINARY = 4'b0010; + 3 : CB2_INH_CC_PERIOD_0_BINARY = 4'b0011; + 4 : CB2_INH_CC_PERIOD_0_BINARY = 4'b0100; + 5 : CB2_INH_CC_PERIOD_0_BINARY = 4'b0101; + 6 : CB2_INH_CC_PERIOD_0_BINARY = 4'b0110; + 7 : CB2_INH_CC_PERIOD_0_BINARY = 4'b0111; + 8 : CB2_INH_CC_PERIOD_0_BINARY = 4'b1000; + 9 : CB2_INH_CC_PERIOD_0_BINARY = 4'b1001; + 10 : CB2_INH_CC_PERIOD_0_BINARY = 4'b1010; + 11 : CB2_INH_CC_PERIOD_0_BINARY = 4'b1011; + 12 : CB2_INH_CC_PERIOD_0_BINARY = 4'b1100; + 13 : CB2_INH_CC_PERIOD_0_BINARY = 4'b1101; + 14 : CB2_INH_CC_PERIOD_0_BINARY = 4'b1110; + 15 : CB2_INH_CC_PERIOD_0_BINARY = 4'b1111; + default : begin + $display("Attribute Syntax Error : The Attribute CB2_INH_CC_PERIOD_0 on GTX_DUAL instance %m is set to %d. Legal values for this attribute are 0 to 15.", CB2_INH_CC_PERIOD_0); + $finish; + end + endcase + + case (CHAN_BOND_MODE_1) + "OFF" : CHAN_BOND_MODE_1_BINARY = 2'b00; + "MASTER" : CHAN_BOND_MODE_1_BINARY = 2'b01; + "SLAVE" : CHAN_BOND_MODE_1_BINARY = 2'b10; + default : begin + $display("Attribute Syntax Error : The Attribute CHAN_BOND_MODE_1 on GTX_DUAL instance %m is set to %s. Legal values for this attribute are OFF, MASTER or SLAVE.", CHAN_BOND_MODE_1); + $finish; + end + endcase + + case (CHAN_BOND_LEVEL_1) + 0 : CHAN_BOND_LEVEL_1_BINARY = 3'b000; + 1 : CHAN_BOND_LEVEL_1_BINARY = 3'b001; + 2 : CHAN_BOND_LEVEL_1_BINARY = 3'b010; + 3 : CHAN_BOND_LEVEL_1_BINARY = 3'b011; + 4 : CHAN_BOND_LEVEL_1_BINARY = 3'b100; + 5 : CHAN_BOND_LEVEL_1_BINARY = 3'b101; + 6 : CHAN_BOND_LEVEL_1_BINARY = 3'b110; + 7 : CHAN_BOND_LEVEL_1_BINARY = 3'b111; + default : begin + $display("Attribute Syntax Error : The Attribute CHAN_BOND_LEVEL_1 on GTX_DUAL instance %m is set to %d. Legal values for this attribute are 0 to 7.", CHAN_BOND_LEVEL_1); + $finish; + end + endcase + + case (CHAN_BOND_SEQ_LEN_1) + 1 : CHAN_BOND_SEQ_LEN_1_BINARY = 2'b00; + 2 : CHAN_BOND_SEQ_LEN_1_BINARY = 2'b01; + 3 : CHAN_BOND_SEQ_LEN_1_BINARY = 2'b10; + 4 : CHAN_BOND_SEQ_LEN_1_BINARY = 2'b11; + default : begin + $display("Attribute Syntax Error : The Attribute CHAN_BOND_SEQ_LEN_1 on GTX_DUAL instance %m is set to %d. Legal values for this attribute are 1, 2, 3 or 4.", CHAN_BOND_SEQ_LEN_1); + $finish; + end + endcase + + case (CHAN_BOND_SEQ_2_USE_1) + "FALSE" : CHAN_BOND_SEQ_2_USE_1_BINARY = 1'b0; + "TRUE" : CHAN_BOND_SEQ_2_USE_1_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute CHAN_BOND_SEQ_2_USE_1 on GTX_DUAL instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", CHAN_BOND_SEQ_2_USE_1); + $finish; + end + endcase + + case (CHAN_BOND_1_MAX_SKEW_1) + 1 : CHAN_BOND_1_MAX_SKEW_1_BINARY = 4'b0001; + 2 : CHAN_BOND_1_MAX_SKEW_1_BINARY = 4'b0010; + 3 : CHAN_BOND_1_MAX_SKEW_1_BINARY = 4'b0011; + 4 : CHAN_BOND_1_MAX_SKEW_1_BINARY = 4'b0100; + 5 : CHAN_BOND_1_MAX_SKEW_1_BINARY = 4'b0101; + 6 : CHAN_BOND_1_MAX_SKEW_1_BINARY = 4'b0110; + 7 : CHAN_BOND_1_MAX_SKEW_1_BINARY = 4'b0111; + 8 : CHAN_BOND_1_MAX_SKEW_1_BINARY = 4'b1000; + 9 : CHAN_BOND_1_MAX_SKEW_1_BINARY = 4'b1001; + 10 : CHAN_BOND_1_MAX_SKEW_1_BINARY = 4'b1010; + 11 : CHAN_BOND_1_MAX_SKEW_1_BINARY = 4'b1011; + 12 : CHAN_BOND_1_MAX_SKEW_1_BINARY = 4'b1100; + 13 : CHAN_BOND_1_MAX_SKEW_1_BINARY = 4'b1101; + 14 : CHAN_BOND_1_MAX_SKEW_1_BINARY = 4'b1110; + default : begin + $display("Attribute Syntax Error : The Attribute CHAN_BOND_1_MAX_SKEW_1 on GTX_DUAL instance %m is set to %d. Legal values for this attribute are 1 to 14.", CHAN_BOND_1_MAX_SKEW_1); + $finish; + end + endcase + + case (CHAN_BOND_2_MAX_SKEW_1) + 1 : CHAN_BOND_2_MAX_SKEW_1_BINARY = 4'b0001; + 2 : CHAN_BOND_2_MAX_SKEW_1_BINARY = 4'b0010; + 3 : CHAN_BOND_2_MAX_SKEW_1_BINARY = 4'b0011; + 4 : CHAN_BOND_2_MAX_SKEW_1_BINARY = 4'b0100; + 5 : CHAN_BOND_2_MAX_SKEW_1_BINARY = 4'b0101; + 6 : CHAN_BOND_2_MAX_SKEW_1_BINARY = 4'b0110; + 7 : CHAN_BOND_2_MAX_SKEW_1_BINARY = 4'b0111; + 8 : CHAN_BOND_2_MAX_SKEW_1_BINARY = 4'b1000; + 9 : CHAN_BOND_2_MAX_SKEW_1_BINARY = 4'b1001; + 10 : CHAN_BOND_2_MAX_SKEW_1_BINARY = 4'b1010; + 11 : CHAN_BOND_2_MAX_SKEW_1_BINARY = 4'b1011; + 12 : CHAN_BOND_2_MAX_SKEW_1_BINARY = 4'b1100; + 13 : CHAN_BOND_2_MAX_SKEW_1_BINARY = 4'b1101; + 14 : CHAN_BOND_2_MAX_SKEW_1_BINARY = 4'b1110; + default : begin + $display("Attribute Syntax Error : The Attribute CHAN_BOND_2_MAX_SKEW_1 on GTX_DUAL instance %m is set to %d. Legal values for this attribute are 1 to 14.", CHAN_BOND_2_MAX_SKEW_1); + $finish; + end + endcase + + case (CHAN_BOND_KEEP_ALIGN_1) + "FALSE" : CHAN_BOND_KEEP_ALIGN_1_BINARY = 1'b0; + "TRUE" : CHAN_BOND_KEEP_ALIGN_1_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute CHAN_BOND_KEEP_ALIGN_1 on GTX_DUAL instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", CHAN_BOND_KEEP_ALIGN_1); + $finish; + end + endcase + + case (CB2_INH_CC_PERIOD_1) + 0 : CB2_INH_CC_PERIOD_1_BINARY = 4'b0000; + 1 : CB2_INH_CC_PERIOD_1_BINARY = 4'b0001; + 2 : CB2_INH_CC_PERIOD_1_BINARY = 4'b0010; + 3 : CB2_INH_CC_PERIOD_1_BINARY = 4'b0011; + 4 : CB2_INH_CC_PERIOD_1_BINARY = 4'b0100; + 5 : CB2_INH_CC_PERIOD_1_BINARY = 4'b0101; + 6 : CB2_INH_CC_PERIOD_1_BINARY = 4'b0110; + 7 : CB2_INH_CC_PERIOD_1_BINARY = 4'b0111; + 8 : CB2_INH_CC_PERIOD_1_BINARY = 4'b1000; + 9 : CB2_INH_CC_PERIOD_1_BINARY = 4'b1001; + 10 : CB2_INH_CC_PERIOD_1_BINARY = 4'b1010; + 11 : CB2_INH_CC_PERIOD_1_BINARY = 4'b1011; + 12 : CB2_INH_CC_PERIOD_1_BINARY = 4'b1100; + 13 : CB2_INH_CC_PERIOD_1_BINARY = 4'b1101; + 14 : CB2_INH_CC_PERIOD_1_BINARY = 4'b1110; + 15 : CB2_INH_CC_PERIOD_1_BINARY = 4'b1111; + default : begin + $display("Attribute Syntax Error : The Attribute CB2_INH_CC_PERIOD_1 on GTX_DUAL instance %m is set to %d. Legal values for this attribute are 0 to 15.", CB2_INH_CC_PERIOD_1); + $finish; + end + endcase + + case (PCI_EXPRESS_MODE_0) + "FALSE" : PCI_EXPRESS_MODE_0_BINARY = 1'b0; + "TRUE" : PCI_EXPRESS_MODE_0_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute PCI_EXPRESS_MODE_0 on GTX_DUAL instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", PCI_EXPRESS_MODE_0); + $finish; + end + endcase + + case (PCI_EXPRESS_MODE_1) + "FALSE" : PCI_EXPRESS_MODE_1_BINARY = 1'b0; + "TRUE" : PCI_EXPRESS_MODE_1_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute PCI_EXPRESS_MODE_1 on GTX_DUAL instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", PCI_EXPRESS_MODE_1); + $finish; + end + endcase + + case (RX_STATUS_FMT_0) + "PCIE" : RX_STATUS_FMT_0_BINARY = 1'b0; + "SATA" : RX_STATUS_FMT_0_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute RX_STATUS_FMT_0 on GTX_DUAL instance %m is set to %s. Legal values for this attribute are PCIE or SATA.", RX_STATUS_FMT_0); + $finish; + end + endcase + + case (TX_BUFFER_USE_0) + "FALSE" : TX_BUFFER_USE_0_BINARY = 1'b0; + "TRUE" : TX_BUFFER_USE_0_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute TX_BUFFER_USE_0 on GTX_DUAL instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", TX_BUFFER_USE_0); + $finish; + end + endcase + + case (TX_XCLK_SEL_0) + "TXUSR" : TX_XCLK_SEL_0_BINARY = 1'b1; + "TXOUT" : TX_XCLK_SEL_0_BINARY = 1'b0; + default : begin + $display("Attribute Syntax Error : The Attribute TX_XCLK_SEL_0 on GTX_DUAL instance %m is set to %s. Legal values for this attribute are TXUSR or TXOUT.", TX_XCLK_SEL_0); + $finish; + end + endcase + + case (RX_XCLK_SEL_0) + "RXREC" : RX_XCLK_SEL_0_BINARY = 1'b0; + "RXUSR" : RX_XCLK_SEL_0_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute RX_XCLK_SEL_0 on GTX_DUAL instance %m is set to %s. Legal values for this attribute are RXREC or RXUSR.", RX_XCLK_SEL_0); + $finish; + end + endcase + + case (RX_STATUS_FMT_1) + "PCIE" : RX_STATUS_FMT_1_BINARY = 1'b0; + "SATA" : RX_STATUS_FMT_1_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute RX_STATUS_FMT_1 on GTX_DUAL instance %m is set to %s. Legal values for this attribute are PCIE or SATA.", RX_STATUS_FMT_1); + $finish; + end + endcase + + case (TX_BUFFER_USE_1) + "FALSE" : TX_BUFFER_USE_1_BINARY = 1'b0; + "TRUE" : TX_BUFFER_USE_1_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute TX_BUFFER_USE_1 on GTX_DUAL instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", TX_BUFFER_USE_1); + $finish; + end + endcase + + case (TX_XCLK_SEL_1) + "TXUSR" : TX_XCLK_SEL_1_BINARY = 1'b1; + "TXOUT" : TX_XCLK_SEL_1_BINARY = 1'b0; + default : begin + $display("Attribute Syntax Error : The Attribute TX_XCLK_SEL_1 on GTX_DUAL instance %m is set to %s. Legal values for this attribute are TXUSR or TXOUT.", TX_XCLK_SEL_1); + $finish; + end + endcase + + case (RX_XCLK_SEL_1) + "RXREC" : RX_XCLK_SEL_1_BINARY = 1'b0; + "RXUSR" : RX_XCLK_SEL_1_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute RX_XCLK_SEL_1 on GTX_DUAL instance %m is set to %s. Legal values for this attribute are RXREC or RXUSR.", RX_XCLK_SEL_1); + $finish; + end + endcase + + case (RX_SLIDE_MODE_0) + "PCS" : RX_SLIDE_MODE_0_BINARY = 1'b0; + "PMA" : RX_SLIDE_MODE_0_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute RX_SLIDE_MODE_0 on GTX_DUAL instance %m is set to %s. Legal values for this attribute are PCS or PMA.", RX_SLIDE_MODE_0); + $finish; + end + endcase + + case (RX_SLIDE_MODE_1) + "PCS" : RX_SLIDE_MODE_1_BINARY = 1'b0; + "PMA" : RX_SLIDE_MODE_1_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute RX_SLIDE_MODE_1 on GTX_DUAL instance %m is set to %s. Legal values for this attribute are PCS or PMA.", RX_SLIDE_MODE_1); + $finish; + end + endcase + + case (SATA_MIN_BURST_0) + 1 : SATA_MIN_BURST_0_BINARY = 6'b000001; + 2 : SATA_MIN_BURST_0_BINARY = 6'b000010; + 3 : SATA_MIN_BURST_0_BINARY = 6'b000011; + 4 : SATA_MIN_BURST_0_BINARY = 6'b000100; + 5 : SATA_MIN_BURST_0_BINARY = 6'b000101; + 6 : SATA_MIN_BURST_0_BINARY = 6'b000110; + 7 : SATA_MIN_BURST_0_BINARY = 6'b000111; + 8 : SATA_MIN_BURST_0_BINARY = 6'b001000; + 9 : SATA_MIN_BURST_0_BINARY = 6'b001001; + 10 : SATA_MIN_BURST_0_BINARY = 6'b001010; + 11 : SATA_MIN_BURST_0_BINARY = 6'b001011; + 12 : SATA_MIN_BURST_0_BINARY = 6'b001100; + 13 : SATA_MIN_BURST_0_BINARY = 6'b001101; + 14 : SATA_MIN_BURST_0_BINARY = 6'b001110; + 15 : SATA_MIN_BURST_0_BINARY = 6'b001111; + 16 : SATA_MIN_BURST_0_BINARY = 6'b010000; + 17 : SATA_MIN_BURST_0_BINARY = 6'b010001; + 18 : SATA_MIN_BURST_0_BINARY = 6'b010010; + 19 : SATA_MIN_BURST_0_BINARY = 6'b010011; + 20 : SATA_MIN_BURST_0_BINARY = 6'b010100; + 21 : SATA_MIN_BURST_0_BINARY = 6'b010101; + 22 : SATA_MIN_BURST_0_BINARY = 6'b010110; + 23 : SATA_MIN_BURST_0_BINARY = 6'b010111; + 24 : SATA_MIN_BURST_0_BINARY = 6'b011000; + 25 : SATA_MIN_BURST_0_BINARY = 6'b011001; + 26 : SATA_MIN_BURST_0_BINARY = 6'b011010; + 27 : SATA_MIN_BURST_0_BINARY = 6'b011011; + 28 : SATA_MIN_BURST_0_BINARY = 6'b011100; + 29 : SATA_MIN_BURST_0_BINARY = 6'b011101; + 30 : SATA_MIN_BURST_0_BINARY = 6'b011110; + 31 : SATA_MIN_BURST_0_BINARY = 6'b011111; + 32 : SATA_MIN_BURST_0_BINARY = 6'b100000; + 33 : SATA_MIN_BURST_0_BINARY = 6'b100001; + 34 : SATA_MIN_BURST_0_BINARY = 6'b100010; + 35 : SATA_MIN_BURST_0_BINARY = 6'b100011; + 36 : SATA_MIN_BURST_0_BINARY = 6'b100100; + 37 : SATA_MIN_BURST_0_BINARY = 6'b100101; + 38 : SATA_MIN_BURST_0_BINARY = 6'b100110; + 39 : SATA_MIN_BURST_0_BINARY = 6'b100111; + 40 : SATA_MIN_BURST_0_BINARY = 6'b101000; + 41 : SATA_MIN_BURST_0_BINARY = 6'b101001; + 42 : SATA_MIN_BURST_0_BINARY = 6'b101010; + 43 : SATA_MIN_BURST_0_BINARY = 6'b101011; + 44 : SATA_MIN_BURST_0_BINARY = 6'b101100; + 45 : SATA_MIN_BURST_0_BINARY = 6'b101101; + 46 : SATA_MIN_BURST_0_BINARY = 6'b101110; + 47 : SATA_MIN_BURST_0_BINARY = 6'b101111; + 48 : SATA_MIN_BURST_0_BINARY = 6'b110000; + 49 : SATA_MIN_BURST_0_BINARY = 6'b110001; + 50 : SATA_MIN_BURST_0_BINARY = 6'b110010; + 51 : SATA_MIN_BURST_0_BINARY = 6'b110011; + 52 : SATA_MIN_BURST_0_BINARY = 6'b110100; + 53 : SATA_MIN_BURST_0_BINARY = 6'b110101; + 54 : SATA_MIN_BURST_0_BINARY = 6'b110110; + 55 : SATA_MIN_BURST_0_BINARY = 6'b110111; + 56 : SATA_MIN_BURST_0_BINARY = 6'b111000; + 57 : SATA_MIN_BURST_0_BINARY = 6'b111001; + 58 : SATA_MIN_BURST_0_BINARY = 6'b111010; + 59 : SATA_MIN_BURST_0_BINARY = 6'b111011; + 60 : SATA_MIN_BURST_0_BINARY = 6'b111100; + 61 : SATA_MIN_BURST_0_BINARY = 6'b111101; + default : begin + $display("Attribute Syntax Error : The Attribute SATA_MIN_BURST_0 on GTX_DUAL instance %m is set to %d. Legal values for this attribute are 1 to 61.", SATA_MIN_BURST_0); + $finish; + end + endcase + + case (SATA_MAX_BURST_0) + 1 : SATA_MAX_BURST_0_BINARY = 6'b000001; + 2 : SATA_MAX_BURST_0_BINARY = 6'b000010; + 3 : SATA_MAX_BURST_0_BINARY = 6'b000011; + 4 : SATA_MAX_BURST_0_BINARY = 6'b000100; + 5 : SATA_MAX_BURST_0_BINARY = 6'b000101; + 6 : SATA_MAX_BURST_0_BINARY = 6'b000110; + 7 : SATA_MAX_BURST_0_BINARY = 6'b000111; + 8 : SATA_MAX_BURST_0_BINARY = 6'b001000; + 9 : SATA_MAX_BURST_0_BINARY = 6'b001001; + 10 : SATA_MAX_BURST_0_BINARY = 6'b001010; + 11 : SATA_MAX_BURST_0_BINARY = 6'b001011; + 12 : SATA_MAX_BURST_0_BINARY = 6'b001100; + 13 : SATA_MAX_BURST_0_BINARY = 6'b001101; + 14 : SATA_MAX_BURST_0_BINARY = 6'b001110; + 15 : SATA_MAX_BURST_0_BINARY = 6'b001111; + 16 : SATA_MAX_BURST_0_BINARY = 6'b010000; + 17 : SATA_MAX_BURST_0_BINARY = 6'b010001; + 18 : SATA_MAX_BURST_0_BINARY = 6'b010010; + 19 : SATA_MAX_BURST_0_BINARY = 6'b010011; + 20 : SATA_MAX_BURST_0_BINARY = 6'b010100; + 21 : SATA_MAX_BURST_0_BINARY = 6'b010101; + 22 : SATA_MAX_BURST_0_BINARY = 6'b010110; + 23 : SATA_MAX_BURST_0_BINARY = 6'b010111; + 24 : SATA_MAX_BURST_0_BINARY = 6'b011000; + 25 : SATA_MAX_BURST_0_BINARY = 6'b011001; + 26 : SATA_MAX_BURST_0_BINARY = 6'b011010; + 27 : SATA_MAX_BURST_0_BINARY = 6'b011011; + 28 : SATA_MAX_BURST_0_BINARY = 6'b011100; + 29 : SATA_MAX_BURST_0_BINARY = 6'b011101; + 30 : SATA_MAX_BURST_0_BINARY = 6'b011110; + 31 : SATA_MAX_BURST_0_BINARY = 6'b011111; + 32 : SATA_MAX_BURST_0_BINARY = 6'b100000; + 33 : SATA_MAX_BURST_0_BINARY = 6'b100001; + 34 : SATA_MAX_BURST_0_BINARY = 6'b100010; + 35 : SATA_MAX_BURST_0_BINARY = 6'b100011; + 36 : SATA_MAX_BURST_0_BINARY = 6'b100100; + 37 : SATA_MAX_BURST_0_BINARY = 6'b100101; + 38 : SATA_MAX_BURST_0_BINARY = 6'b100110; + 39 : SATA_MAX_BURST_0_BINARY = 6'b100111; + 40 : SATA_MAX_BURST_0_BINARY = 6'b101000; + 41 : SATA_MAX_BURST_0_BINARY = 6'b101001; + 42 : SATA_MAX_BURST_0_BINARY = 6'b101010; + 43 : SATA_MAX_BURST_0_BINARY = 6'b101011; + 44 : SATA_MAX_BURST_0_BINARY = 6'b101100; + 45 : SATA_MAX_BURST_0_BINARY = 6'b101101; + 46 : SATA_MAX_BURST_0_BINARY = 6'b101110; + 47 : SATA_MAX_BURST_0_BINARY = 6'b101111; + 48 : SATA_MAX_BURST_0_BINARY = 6'b110000; + 49 : SATA_MAX_BURST_0_BINARY = 6'b110001; + 50 : SATA_MAX_BURST_0_BINARY = 6'b110010; + 51 : SATA_MAX_BURST_0_BINARY = 6'b110011; + 52 : SATA_MAX_BURST_0_BINARY = 6'b110100; + 53 : SATA_MAX_BURST_0_BINARY = 6'b110101; + 54 : SATA_MAX_BURST_0_BINARY = 6'b110110; + 55 : SATA_MAX_BURST_0_BINARY = 6'b110111; + 56 : SATA_MAX_BURST_0_BINARY = 6'b111000; + 57 : SATA_MAX_BURST_0_BINARY = 6'b111001; + 58 : SATA_MAX_BURST_0_BINARY = 6'b111010; + 59 : SATA_MAX_BURST_0_BINARY = 6'b111011; + 60 : SATA_MAX_BURST_0_BINARY = 6'b111100; + 61 : SATA_MAX_BURST_0_BINARY = 6'b111101; + default : begin + $display("Attribute Syntax Error : The Attribute SATA_MAX_BURST_0 on GTX_DUAL instance %m is set to %d. Legal values for this attribute are 1 to 61.", SATA_MAX_BURST_0); + $finish; + end + endcase + + case (SATA_MIN_INIT_0) + 1 : SATA_MIN_INIT_0_BINARY = 6'b000001; + 2 : SATA_MIN_INIT_0_BINARY = 6'b000010; + 3 : SATA_MIN_INIT_0_BINARY = 6'b000011; + 4 : SATA_MIN_INIT_0_BINARY = 6'b000100; + 5 : SATA_MIN_INIT_0_BINARY = 6'b000101; + 6 : SATA_MIN_INIT_0_BINARY = 6'b000110; + 7 : SATA_MIN_INIT_0_BINARY = 6'b000111; + 8 : SATA_MIN_INIT_0_BINARY = 6'b001000; + 9 : SATA_MIN_INIT_0_BINARY = 6'b001001; + 10 : SATA_MIN_INIT_0_BINARY = 6'b001010; + 11 : SATA_MIN_INIT_0_BINARY = 6'b001011; + 12 : SATA_MIN_INIT_0_BINARY = 6'b001100; + 13 : SATA_MIN_INIT_0_BINARY = 6'b001101; + 14 : SATA_MIN_INIT_0_BINARY = 6'b001110; + 15 : SATA_MIN_INIT_0_BINARY = 6'b001111; + 16 : SATA_MIN_INIT_0_BINARY = 6'b010000; + 17 : SATA_MIN_INIT_0_BINARY = 6'b010001; + 18 : SATA_MIN_INIT_0_BINARY = 6'b010010; + 19 : SATA_MIN_INIT_0_BINARY = 6'b010011; + 20 : SATA_MIN_INIT_0_BINARY = 6'b010100; + 21 : SATA_MIN_INIT_0_BINARY = 6'b010101; + 22 : SATA_MIN_INIT_0_BINARY = 6'b010110; + 23 : SATA_MIN_INIT_0_BINARY = 6'b010111; + 24 : SATA_MIN_INIT_0_BINARY = 6'b011000; + 25 : SATA_MIN_INIT_0_BINARY = 6'b011001; + 26 : SATA_MIN_INIT_0_BINARY = 6'b011010; + 27 : SATA_MIN_INIT_0_BINARY = 6'b011011; + 28 : SATA_MIN_INIT_0_BINARY = 6'b011100; + 29 : SATA_MIN_INIT_0_BINARY = 6'b011101; + 30 : SATA_MIN_INIT_0_BINARY = 6'b011110; + 31 : SATA_MIN_INIT_0_BINARY = 6'b011111; + 32 : SATA_MIN_INIT_0_BINARY = 6'b100000; + 33 : SATA_MIN_INIT_0_BINARY = 6'b100001; + 34 : SATA_MIN_INIT_0_BINARY = 6'b100010; + 35 : SATA_MIN_INIT_0_BINARY = 6'b100011; + 36 : SATA_MIN_INIT_0_BINARY = 6'b100100; + 37 : SATA_MIN_INIT_0_BINARY = 6'b100101; + 38 : SATA_MIN_INIT_0_BINARY = 6'b100110; + 39 : SATA_MIN_INIT_0_BINARY = 6'b100111; + 40 : SATA_MIN_INIT_0_BINARY = 6'b101000; + 41 : SATA_MIN_INIT_0_BINARY = 6'b101001; + 42 : SATA_MIN_INIT_0_BINARY = 6'b101010; + 43 : SATA_MIN_INIT_0_BINARY = 6'b101011; + 44 : SATA_MIN_INIT_0_BINARY = 6'b101100; + 45 : SATA_MIN_INIT_0_BINARY = 6'b101101; + 46 : SATA_MIN_INIT_0_BINARY = 6'b101110; + 47 : SATA_MIN_INIT_0_BINARY = 6'b101111; + 48 : SATA_MIN_INIT_0_BINARY = 6'b110000; + 49 : SATA_MIN_INIT_0_BINARY = 6'b110001; + 50 : SATA_MIN_INIT_0_BINARY = 6'b110010; + 51 : SATA_MIN_INIT_0_BINARY = 6'b110011; + 52 : SATA_MIN_INIT_0_BINARY = 6'b110100; + 53 : SATA_MIN_INIT_0_BINARY = 6'b110101; + 54 : SATA_MIN_INIT_0_BINARY = 6'b110110; + 55 : SATA_MIN_INIT_0_BINARY = 6'b110111; + 56 : SATA_MIN_INIT_0_BINARY = 6'b111000; + 57 : SATA_MIN_INIT_0_BINARY = 6'b111001; + 58 : SATA_MIN_INIT_0_BINARY = 6'b111010; + 59 : SATA_MIN_INIT_0_BINARY = 6'b111011; + 60 : SATA_MIN_INIT_0_BINARY = 6'b111100; + 61 : SATA_MIN_INIT_0_BINARY = 6'b111101; + default : begin + $display("Attribute Syntax Error : The Attribute SATA_MIN_INIT_0 on GTX_DUAL instance %m is set to %d. Legal values for this attribute are 1 to 61.", SATA_MIN_INIT_0); + $finish; + end + endcase + + case (SATA_MAX_INIT_0) + 1 : SATA_MAX_INIT_0_BINARY = 6'b000001; + 2 : SATA_MAX_INIT_0_BINARY = 6'b000010; + 3 : SATA_MAX_INIT_0_BINARY = 6'b000011; + 4 : SATA_MAX_INIT_0_BINARY = 6'b000100; + 5 : SATA_MAX_INIT_0_BINARY = 6'b000101; + 6 : SATA_MAX_INIT_0_BINARY = 6'b000110; + 7 : SATA_MAX_INIT_0_BINARY = 6'b000111; + 8 : SATA_MAX_INIT_0_BINARY = 6'b001000; + 9 : SATA_MAX_INIT_0_BINARY = 6'b001001; + 10 : SATA_MAX_INIT_0_BINARY = 6'b001010; + 11 : SATA_MAX_INIT_0_BINARY = 6'b001011; + 12 : SATA_MAX_INIT_0_BINARY = 6'b001100; + 13 : SATA_MAX_INIT_0_BINARY = 6'b001101; + 14 : SATA_MAX_INIT_0_BINARY = 6'b001110; + 15 : SATA_MAX_INIT_0_BINARY = 6'b001111; + 16 : SATA_MAX_INIT_0_BINARY = 6'b010000; + 17 : SATA_MAX_INIT_0_BINARY = 6'b010001; + 18 : SATA_MAX_INIT_0_BINARY = 6'b010010; + 19 : SATA_MAX_INIT_0_BINARY = 6'b010011; + 20 : SATA_MAX_INIT_0_BINARY = 6'b010100; + 21 : SATA_MAX_INIT_0_BINARY = 6'b010101; + 22 : SATA_MAX_INIT_0_BINARY = 6'b010110; + 23 : SATA_MAX_INIT_0_BINARY = 6'b010111; + 24 : SATA_MAX_INIT_0_BINARY = 6'b011000; + 25 : SATA_MAX_INIT_0_BINARY = 6'b011001; + 26 : SATA_MAX_INIT_0_BINARY = 6'b011010; + 27 : SATA_MAX_INIT_0_BINARY = 6'b011011; + 28 : SATA_MAX_INIT_0_BINARY = 6'b011100; + 29 : SATA_MAX_INIT_0_BINARY = 6'b011101; + 30 : SATA_MAX_INIT_0_BINARY = 6'b011110; + 31 : SATA_MAX_INIT_0_BINARY = 6'b011111; + 32 : SATA_MAX_INIT_0_BINARY = 6'b100000; + 33 : SATA_MAX_INIT_0_BINARY = 6'b100001; + 34 : SATA_MAX_INIT_0_BINARY = 6'b100010; + 35 : SATA_MAX_INIT_0_BINARY = 6'b100011; + 36 : SATA_MAX_INIT_0_BINARY = 6'b100100; + 37 : SATA_MAX_INIT_0_BINARY = 6'b100101; + 38 : SATA_MAX_INIT_0_BINARY = 6'b100110; + 39 : SATA_MAX_INIT_0_BINARY = 6'b100111; + 40 : SATA_MAX_INIT_0_BINARY = 6'b101000; + 41 : SATA_MAX_INIT_0_BINARY = 6'b101001; + 42 : SATA_MAX_INIT_0_BINARY = 6'b101010; + 43 : SATA_MAX_INIT_0_BINARY = 6'b101011; + 44 : SATA_MAX_INIT_0_BINARY = 6'b101100; + 45 : SATA_MAX_INIT_0_BINARY = 6'b101101; + 46 : SATA_MAX_INIT_0_BINARY = 6'b101110; + 47 : SATA_MAX_INIT_0_BINARY = 6'b101111; + 48 : SATA_MAX_INIT_0_BINARY = 6'b110000; + 49 : SATA_MAX_INIT_0_BINARY = 6'b110001; + 50 : SATA_MAX_INIT_0_BINARY = 6'b110010; + 51 : SATA_MAX_INIT_0_BINARY = 6'b110011; + 52 : SATA_MAX_INIT_0_BINARY = 6'b110100; + 53 : SATA_MAX_INIT_0_BINARY = 6'b110101; + 54 : SATA_MAX_INIT_0_BINARY = 6'b110110; + 55 : SATA_MAX_INIT_0_BINARY = 6'b110111; + 56 : SATA_MAX_INIT_0_BINARY = 6'b111000; + 57 : SATA_MAX_INIT_0_BINARY = 6'b111001; + 58 : SATA_MAX_INIT_0_BINARY = 6'b111010; + 59 : SATA_MAX_INIT_0_BINARY = 6'b111011; + 60 : SATA_MAX_INIT_0_BINARY = 6'b111100; + 61 : SATA_MAX_INIT_0_BINARY = 6'b111101; + default : begin + $display("Attribute Syntax Error : The Attribute SATA_MAX_INIT_0 on GTX_DUAL instance %m is set to %d. Legal values for this attribute are 1 to 61.", SATA_MAX_INIT_0); + $finish; + end + endcase + + case (SATA_MIN_WAKE_0) + 1 : SATA_MIN_WAKE_0_BINARY = 6'b000001; + 2 : SATA_MIN_WAKE_0_BINARY = 6'b000010; + 3 : SATA_MIN_WAKE_0_BINARY = 6'b000011; + 4 : SATA_MIN_WAKE_0_BINARY = 6'b000100; + 5 : SATA_MIN_WAKE_0_BINARY = 6'b000101; + 6 : SATA_MIN_WAKE_0_BINARY = 6'b000110; + 7 : SATA_MIN_WAKE_0_BINARY = 6'b000111; + 8 : SATA_MIN_WAKE_0_BINARY = 6'b001000; + 9 : SATA_MIN_WAKE_0_BINARY = 6'b001001; + 10 : SATA_MIN_WAKE_0_BINARY = 6'b001010; + 11 : SATA_MIN_WAKE_0_BINARY = 6'b001011; + 12 : SATA_MIN_WAKE_0_BINARY = 6'b001100; + 13 : SATA_MIN_WAKE_0_BINARY = 6'b001101; + 14 : SATA_MIN_WAKE_0_BINARY = 6'b001110; + 15 : SATA_MIN_WAKE_0_BINARY = 6'b001111; + 16 : SATA_MIN_WAKE_0_BINARY = 6'b010000; + 17 : SATA_MIN_WAKE_0_BINARY = 6'b010001; + 18 : SATA_MIN_WAKE_0_BINARY = 6'b010010; + 19 : SATA_MIN_WAKE_0_BINARY = 6'b010011; + 20 : SATA_MIN_WAKE_0_BINARY = 6'b010100; + 21 : SATA_MIN_WAKE_0_BINARY = 6'b010101; + 22 : SATA_MIN_WAKE_0_BINARY = 6'b010110; + 23 : SATA_MIN_WAKE_0_BINARY = 6'b010111; + 24 : SATA_MIN_WAKE_0_BINARY = 6'b011000; + 25 : SATA_MIN_WAKE_0_BINARY = 6'b011001; + 26 : SATA_MIN_WAKE_0_BINARY = 6'b011010; + 27 : SATA_MIN_WAKE_0_BINARY = 6'b011011; + 28 : SATA_MIN_WAKE_0_BINARY = 6'b011100; + 29 : SATA_MIN_WAKE_0_BINARY = 6'b011101; + 30 : SATA_MIN_WAKE_0_BINARY = 6'b011110; + 31 : SATA_MIN_WAKE_0_BINARY = 6'b011111; + 32 : SATA_MIN_WAKE_0_BINARY = 6'b100000; + 33 : SATA_MIN_WAKE_0_BINARY = 6'b100001; + 34 : SATA_MIN_WAKE_0_BINARY = 6'b100010; + 35 : SATA_MIN_WAKE_0_BINARY = 6'b100011; + 36 : SATA_MIN_WAKE_0_BINARY = 6'b100100; + 37 : SATA_MIN_WAKE_0_BINARY = 6'b100101; + 38 : SATA_MIN_WAKE_0_BINARY = 6'b100110; + 39 : SATA_MIN_WAKE_0_BINARY = 6'b100111; + 40 : SATA_MIN_WAKE_0_BINARY = 6'b101000; + 41 : SATA_MIN_WAKE_0_BINARY = 6'b101001; + 42 : SATA_MIN_WAKE_0_BINARY = 6'b101010; + 43 : SATA_MIN_WAKE_0_BINARY = 6'b101011; + 44 : SATA_MIN_WAKE_0_BINARY = 6'b101100; + 45 : SATA_MIN_WAKE_0_BINARY = 6'b101101; + 46 : SATA_MIN_WAKE_0_BINARY = 6'b101110; + 47 : SATA_MIN_WAKE_0_BINARY = 6'b101111; + 48 : SATA_MIN_WAKE_0_BINARY = 6'b110000; + 49 : SATA_MIN_WAKE_0_BINARY = 6'b110001; + 50 : SATA_MIN_WAKE_0_BINARY = 6'b110010; + 51 : SATA_MIN_WAKE_0_BINARY = 6'b110011; + 52 : SATA_MIN_WAKE_0_BINARY = 6'b110100; + 53 : SATA_MIN_WAKE_0_BINARY = 6'b110101; + 54 : SATA_MIN_WAKE_0_BINARY = 6'b110110; + 55 : SATA_MIN_WAKE_0_BINARY = 6'b110111; + 56 : SATA_MIN_WAKE_0_BINARY = 6'b111000; + 57 : SATA_MIN_WAKE_0_BINARY = 6'b111001; + 58 : SATA_MIN_WAKE_0_BINARY = 6'b111010; + 59 : SATA_MIN_WAKE_0_BINARY = 6'b111011; + 60 : SATA_MIN_WAKE_0_BINARY = 6'b111100; + 61 : SATA_MIN_WAKE_0_BINARY = 6'b111101; + default : begin + $display("Attribute Syntax Error : The Attribute SATA_MIN_WAKE_0 on GTX_DUAL instance %m is set to %d. Legal values for this attribute are 1 to 61.", SATA_MIN_WAKE_0); + $finish; + end + endcase + + case (SATA_MAX_WAKE_0) + 1 : SATA_MAX_WAKE_0_BINARY = 6'b000001; + 2 : SATA_MAX_WAKE_0_BINARY = 6'b000010; + 3 : SATA_MAX_WAKE_0_BINARY = 6'b000011; + 4 : SATA_MAX_WAKE_0_BINARY = 6'b000100; + 5 : SATA_MAX_WAKE_0_BINARY = 6'b000101; + 6 : SATA_MAX_WAKE_0_BINARY = 6'b000110; + 7 : SATA_MAX_WAKE_0_BINARY = 6'b000111; + 8 : SATA_MAX_WAKE_0_BINARY = 6'b001000; + 9 : SATA_MAX_WAKE_0_BINARY = 6'b001001; + 10 : SATA_MAX_WAKE_0_BINARY = 6'b001010; + 11 : SATA_MAX_WAKE_0_BINARY = 6'b001011; + 12 : SATA_MAX_WAKE_0_BINARY = 6'b001100; + 13 : SATA_MAX_WAKE_0_BINARY = 6'b001101; + 14 : SATA_MAX_WAKE_0_BINARY = 6'b001110; + 15 : SATA_MAX_WAKE_0_BINARY = 6'b001111; + 16 : SATA_MAX_WAKE_0_BINARY = 6'b010000; + 17 : SATA_MAX_WAKE_0_BINARY = 6'b010001; + 18 : SATA_MAX_WAKE_0_BINARY = 6'b010010; + 19 : SATA_MAX_WAKE_0_BINARY = 6'b010011; + 20 : SATA_MAX_WAKE_0_BINARY = 6'b010100; + 21 : SATA_MAX_WAKE_0_BINARY = 6'b010101; + 22 : SATA_MAX_WAKE_0_BINARY = 6'b010110; + 23 : SATA_MAX_WAKE_0_BINARY = 6'b010111; + 24 : SATA_MAX_WAKE_0_BINARY = 6'b011000; + 25 : SATA_MAX_WAKE_0_BINARY = 6'b011001; + 26 : SATA_MAX_WAKE_0_BINARY = 6'b011010; + 27 : SATA_MAX_WAKE_0_BINARY = 6'b011011; + 28 : SATA_MAX_WAKE_0_BINARY = 6'b011100; + 29 : SATA_MAX_WAKE_0_BINARY = 6'b011101; + 30 : SATA_MAX_WAKE_0_BINARY = 6'b011110; + 31 : SATA_MAX_WAKE_0_BINARY = 6'b011111; + 32 : SATA_MAX_WAKE_0_BINARY = 6'b100000; + 33 : SATA_MAX_WAKE_0_BINARY = 6'b100001; + 34 : SATA_MAX_WAKE_0_BINARY = 6'b100010; + 35 : SATA_MAX_WAKE_0_BINARY = 6'b100011; + 36 : SATA_MAX_WAKE_0_BINARY = 6'b100100; + 37 : SATA_MAX_WAKE_0_BINARY = 6'b100101; + 38 : SATA_MAX_WAKE_0_BINARY = 6'b100110; + 39 : SATA_MAX_WAKE_0_BINARY = 6'b100111; + 40 : SATA_MAX_WAKE_0_BINARY = 6'b101000; + 41 : SATA_MAX_WAKE_0_BINARY = 6'b101001; + 42 : SATA_MAX_WAKE_0_BINARY = 6'b101010; + 43 : SATA_MAX_WAKE_0_BINARY = 6'b101011; + 44 : SATA_MAX_WAKE_0_BINARY = 6'b101100; + 45 : SATA_MAX_WAKE_0_BINARY = 6'b101101; + 46 : SATA_MAX_WAKE_0_BINARY = 6'b101110; + 47 : SATA_MAX_WAKE_0_BINARY = 6'b101111; + 48 : SATA_MAX_WAKE_0_BINARY = 6'b110000; + 49 : SATA_MAX_WAKE_0_BINARY = 6'b110001; + 50 : SATA_MAX_WAKE_0_BINARY = 6'b110010; + 51 : SATA_MAX_WAKE_0_BINARY = 6'b110011; + 52 : SATA_MAX_WAKE_0_BINARY = 6'b110100; + 53 : SATA_MAX_WAKE_0_BINARY = 6'b110101; + 54 : SATA_MAX_WAKE_0_BINARY = 6'b110110; + 55 : SATA_MAX_WAKE_0_BINARY = 6'b110111; + 56 : SATA_MAX_WAKE_0_BINARY = 6'b111000; + 57 : SATA_MAX_WAKE_0_BINARY = 6'b111001; + 58 : SATA_MAX_WAKE_0_BINARY = 6'b111010; + 59 : SATA_MAX_WAKE_0_BINARY = 6'b111011; + 60 : SATA_MAX_WAKE_0_BINARY = 6'b111100; + 61 : SATA_MAX_WAKE_0_BINARY = 6'b111101; + default : begin + $display("Attribute Syntax Error : The Attribute SATA_MAX_WAKE_0 on GTX_DUAL instance %m is set to %d. Legal values for this attribute are 1 to 61.", SATA_MAX_WAKE_0); + $finish; + end + endcase + + case (SATA_MIN_BURST_1) + 1 : SATA_MIN_BURST_1_BINARY = 6'b000001; + 2 : SATA_MIN_BURST_1_BINARY = 6'b000010; + 3 : SATA_MIN_BURST_1_BINARY = 6'b000011; + 4 : SATA_MIN_BURST_1_BINARY = 6'b000100; + 5 : SATA_MIN_BURST_1_BINARY = 6'b000101; + 6 : SATA_MIN_BURST_1_BINARY = 6'b000110; + 7 : SATA_MIN_BURST_1_BINARY = 6'b000111; + 8 : SATA_MIN_BURST_1_BINARY = 6'b001000; + 9 : SATA_MIN_BURST_1_BINARY = 6'b001001; + 10 : SATA_MIN_BURST_1_BINARY = 6'b001010; + 11 : SATA_MIN_BURST_1_BINARY = 6'b001011; + 12 : SATA_MIN_BURST_1_BINARY = 6'b001100; + 13 : SATA_MIN_BURST_1_BINARY = 6'b001101; + 14 : SATA_MIN_BURST_1_BINARY = 6'b001110; + 15 : SATA_MIN_BURST_1_BINARY = 6'b001111; + 16 : SATA_MIN_BURST_1_BINARY = 6'b010000; + 17 : SATA_MIN_BURST_1_BINARY = 6'b010001; + 18 : SATA_MIN_BURST_1_BINARY = 6'b010010; + 19 : SATA_MIN_BURST_1_BINARY = 6'b010011; + 20 : SATA_MIN_BURST_1_BINARY = 6'b010100; + 21 : SATA_MIN_BURST_1_BINARY = 6'b010101; + 22 : SATA_MIN_BURST_1_BINARY = 6'b010110; + 23 : SATA_MIN_BURST_1_BINARY = 6'b010111; + 24 : SATA_MIN_BURST_1_BINARY = 6'b011000; + 25 : SATA_MIN_BURST_1_BINARY = 6'b011001; + 26 : SATA_MIN_BURST_1_BINARY = 6'b011010; + 27 : SATA_MIN_BURST_1_BINARY = 6'b011011; + 28 : SATA_MIN_BURST_1_BINARY = 6'b011100; + 29 : SATA_MIN_BURST_1_BINARY = 6'b011101; + 30 : SATA_MIN_BURST_1_BINARY = 6'b011110; + 31 : SATA_MIN_BURST_1_BINARY = 6'b011111; + 32 : SATA_MIN_BURST_1_BINARY = 6'b100000; + 33 : SATA_MIN_BURST_1_BINARY = 6'b100001; + 34 : SATA_MIN_BURST_1_BINARY = 6'b100010; + 35 : SATA_MIN_BURST_1_BINARY = 6'b100011; + 36 : SATA_MIN_BURST_1_BINARY = 6'b100100; + 37 : SATA_MIN_BURST_1_BINARY = 6'b100101; + 38 : SATA_MIN_BURST_1_BINARY = 6'b100110; + 39 : SATA_MIN_BURST_1_BINARY = 6'b100111; + 40 : SATA_MIN_BURST_1_BINARY = 6'b101000; + 41 : SATA_MIN_BURST_1_BINARY = 6'b101001; + 42 : SATA_MIN_BURST_1_BINARY = 6'b101010; + 43 : SATA_MIN_BURST_1_BINARY = 6'b101011; + 44 : SATA_MIN_BURST_1_BINARY = 6'b101100; + 45 : SATA_MIN_BURST_1_BINARY = 6'b101101; + 46 : SATA_MIN_BURST_1_BINARY = 6'b101110; + 47 : SATA_MIN_BURST_1_BINARY = 6'b101111; + 48 : SATA_MIN_BURST_1_BINARY = 6'b110000; + 49 : SATA_MIN_BURST_1_BINARY = 6'b110001; + 50 : SATA_MIN_BURST_1_BINARY = 6'b110010; + 51 : SATA_MIN_BURST_1_BINARY = 6'b110011; + 52 : SATA_MIN_BURST_1_BINARY = 6'b110100; + 53 : SATA_MIN_BURST_1_BINARY = 6'b110101; + 54 : SATA_MIN_BURST_1_BINARY = 6'b110110; + 55 : SATA_MIN_BURST_1_BINARY = 6'b110111; + 56 : SATA_MIN_BURST_1_BINARY = 6'b111000; + 57 : SATA_MIN_BURST_1_BINARY = 6'b111001; + 58 : SATA_MIN_BURST_1_BINARY = 6'b111010; + 59 : SATA_MIN_BURST_1_BINARY = 6'b111011; + 60 : SATA_MIN_BURST_1_BINARY = 6'b111100; + 61 : SATA_MIN_BURST_1_BINARY = 6'b111101; + default : begin + $display("Attribute Syntax Error : The Attribute SATA_MIN_BURST_1 on GTX_DUAL instance %m is set to %d. Legal values for this attribute are 1 to 61.", SATA_MIN_BURST_1); + $finish; + end + endcase + + case (SATA_MAX_BURST_1) + 1 : SATA_MAX_BURST_1_BINARY = 6'b000001; + 2 : SATA_MAX_BURST_1_BINARY = 6'b000010; + 3 : SATA_MAX_BURST_1_BINARY = 6'b000011; + 4 : SATA_MAX_BURST_1_BINARY = 6'b000100; + 5 : SATA_MAX_BURST_1_BINARY = 6'b000101; + 6 : SATA_MAX_BURST_1_BINARY = 6'b000110; + 7 : SATA_MAX_BURST_1_BINARY = 6'b000111; + 8 : SATA_MAX_BURST_1_BINARY = 6'b001000; + 9 : SATA_MAX_BURST_1_BINARY = 6'b001001; + 10 : SATA_MAX_BURST_1_BINARY = 6'b001010; + 11 : SATA_MAX_BURST_1_BINARY = 6'b001011; + 12 : SATA_MAX_BURST_1_BINARY = 6'b001100; + 13 : SATA_MAX_BURST_1_BINARY = 6'b001101; + 14 : SATA_MAX_BURST_1_BINARY = 6'b001110; + 15 : SATA_MAX_BURST_1_BINARY = 6'b001111; + 16 : SATA_MAX_BURST_1_BINARY = 6'b010000; + 17 : SATA_MAX_BURST_1_BINARY = 6'b010001; + 18 : SATA_MAX_BURST_1_BINARY = 6'b010010; + 19 : SATA_MAX_BURST_1_BINARY = 6'b010011; + 20 : SATA_MAX_BURST_1_BINARY = 6'b010100; + 21 : SATA_MAX_BURST_1_BINARY = 6'b010101; + 22 : SATA_MAX_BURST_1_BINARY = 6'b010110; + 23 : SATA_MAX_BURST_1_BINARY = 6'b010111; + 24 : SATA_MAX_BURST_1_BINARY = 6'b011000; + 25 : SATA_MAX_BURST_1_BINARY = 6'b011001; + 26 : SATA_MAX_BURST_1_BINARY = 6'b011010; + 27 : SATA_MAX_BURST_1_BINARY = 6'b011011; + 28 : SATA_MAX_BURST_1_BINARY = 6'b011100; + 29 : SATA_MAX_BURST_1_BINARY = 6'b011101; + 30 : SATA_MAX_BURST_1_BINARY = 6'b011110; + 31 : SATA_MAX_BURST_1_BINARY = 6'b011111; + 32 : SATA_MAX_BURST_1_BINARY = 6'b100000; + 33 : SATA_MAX_BURST_1_BINARY = 6'b100001; + 34 : SATA_MAX_BURST_1_BINARY = 6'b100010; + 35 : SATA_MAX_BURST_1_BINARY = 6'b100011; + 36 : SATA_MAX_BURST_1_BINARY = 6'b100100; + 37 : SATA_MAX_BURST_1_BINARY = 6'b100101; + 38 : SATA_MAX_BURST_1_BINARY = 6'b100110; + 39 : SATA_MAX_BURST_1_BINARY = 6'b100111; + 40 : SATA_MAX_BURST_1_BINARY = 6'b101000; + 41 : SATA_MAX_BURST_1_BINARY = 6'b101001; + 42 : SATA_MAX_BURST_1_BINARY = 6'b101010; + 43 : SATA_MAX_BURST_1_BINARY = 6'b101011; + 44 : SATA_MAX_BURST_1_BINARY = 6'b101100; + 45 : SATA_MAX_BURST_1_BINARY = 6'b101101; + 46 : SATA_MAX_BURST_1_BINARY = 6'b101110; + 47 : SATA_MAX_BURST_1_BINARY = 6'b101111; + 48 : SATA_MAX_BURST_1_BINARY = 6'b110000; + 49 : SATA_MAX_BURST_1_BINARY = 6'b110001; + 50 : SATA_MAX_BURST_1_BINARY = 6'b110010; + 51 : SATA_MAX_BURST_1_BINARY = 6'b110011; + 52 : SATA_MAX_BURST_1_BINARY = 6'b110100; + 53 : SATA_MAX_BURST_1_BINARY = 6'b110101; + 54 : SATA_MAX_BURST_1_BINARY = 6'b110110; + 55 : SATA_MAX_BURST_1_BINARY = 6'b110111; + 56 : SATA_MAX_BURST_1_BINARY = 6'b111000; + 57 : SATA_MAX_BURST_1_BINARY = 6'b111001; + 58 : SATA_MAX_BURST_1_BINARY = 6'b111010; + 59 : SATA_MAX_BURST_1_BINARY = 6'b111011; + 60 : SATA_MAX_BURST_1_BINARY = 6'b111100; + 61 : SATA_MAX_BURST_1_BINARY = 6'b111101; + default : begin + $display("Attribute Syntax Error : The Attribute SATA_MAX_BURST_1 on GTX_DUAL instance %m is set to %d. Legal values for this attribute are 1 to 61.", SATA_MAX_BURST_1); + $finish; + end + endcase + + case (SATA_MIN_INIT_1) + 1 : SATA_MIN_INIT_1_BINARY = 6'b000001; + 2 : SATA_MIN_INIT_1_BINARY = 6'b000010; + 3 : SATA_MIN_INIT_1_BINARY = 6'b000011; + 4 : SATA_MIN_INIT_1_BINARY = 6'b000100; + 5 : SATA_MIN_INIT_1_BINARY = 6'b000101; + 6 : SATA_MIN_INIT_1_BINARY = 6'b000110; + 7 : SATA_MIN_INIT_1_BINARY = 6'b000111; + 8 : SATA_MIN_INIT_1_BINARY = 6'b001000; + 9 : SATA_MIN_INIT_1_BINARY = 6'b001001; + 10 : SATA_MIN_INIT_1_BINARY = 6'b001010; + 11 : SATA_MIN_INIT_1_BINARY = 6'b001011; + 12 : SATA_MIN_INIT_1_BINARY = 6'b001100; + 13 : SATA_MIN_INIT_1_BINARY = 6'b001101; + 14 : SATA_MIN_INIT_1_BINARY = 6'b001110; + 15 : SATA_MIN_INIT_1_BINARY = 6'b001111; + 16 : SATA_MIN_INIT_1_BINARY = 6'b010000; + 17 : SATA_MIN_INIT_1_BINARY = 6'b010001; + 18 : SATA_MIN_INIT_1_BINARY = 6'b010010; + 19 : SATA_MIN_INIT_1_BINARY = 6'b010011; + 20 : SATA_MIN_INIT_1_BINARY = 6'b010100; + 21 : SATA_MIN_INIT_1_BINARY = 6'b010101; + 22 : SATA_MIN_INIT_1_BINARY = 6'b010110; + 23 : SATA_MIN_INIT_1_BINARY = 6'b010111; + 24 : SATA_MIN_INIT_1_BINARY = 6'b011000; + 25 : SATA_MIN_INIT_1_BINARY = 6'b011001; + 26 : SATA_MIN_INIT_1_BINARY = 6'b011010; + 27 : SATA_MIN_INIT_1_BINARY = 6'b011011; + 28 : SATA_MIN_INIT_1_BINARY = 6'b011100; + 29 : SATA_MIN_INIT_1_BINARY = 6'b011101; + 30 : SATA_MIN_INIT_1_BINARY = 6'b011110; + 31 : SATA_MIN_INIT_1_BINARY = 6'b011111; + 32 : SATA_MIN_INIT_1_BINARY = 6'b100000; + 33 : SATA_MIN_INIT_1_BINARY = 6'b100001; + 34 : SATA_MIN_INIT_1_BINARY = 6'b100010; + 35 : SATA_MIN_INIT_1_BINARY = 6'b100011; + 36 : SATA_MIN_INIT_1_BINARY = 6'b100100; + 37 : SATA_MIN_INIT_1_BINARY = 6'b100101; + 38 : SATA_MIN_INIT_1_BINARY = 6'b100110; + 39 : SATA_MIN_INIT_1_BINARY = 6'b100111; + 40 : SATA_MIN_INIT_1_BINARY = 6'b101000; + 41 : SATA_MIN_INIT_1_BINARY = 6'b101001; + 42 : SATA_MIN_INIT_1_BINARY = 6'b101010; + 43 : SATA_MIN_INIT_1_BINARY = 6'b101011; + 44 : SATA_MIN_INIT_1_BINARY = 6'b101100; + 45 : SATA_MIN_INIT_1_BINARY = 6'b101101; + 46 : SATA_MIN_INIT_1_BINARY = 6'b101110; + 47 : SATA_MIN_INIT_1_BINARY = 6'b101111; + 48 : SATA_MIN_INIT_1_BINARY = 6'b110000; + 49 : SATA_MIN_INIT_1_BINARY = 6'b110001; + 50 : SATA_MIN_INIT_1_BINARY = 6'b110010; + 51 : SATA_MIN_INIT_1_BINARY = 6'b110011; + 52 : SATA_MIN_INIT_1_BINARY = 6'b110100; + 53 : SATA_MIN_INIT_1_BINARY = 6'b110101; + 54 : SATA_MIN_INIT_1_BINARY = 6'b110110; + 55 : SATA_MIN_INIT_1_BINARY = 6'b110111; + 56 : SATA_MIN_INIT_1_BINARY = 6'b111000; + 57 : SATA_MIN_INIT_1_BINARY = 6'b111001; + 58 : SATA_MIN_INIT_1_BINARY = 6'b111010; + 59 : SATA_MIN_INIT_1_BINARY = 6'b111011; + 60 : SATA_MIN_INIT_1_BINARY = 6'b111100; + 61 : SATA_MIN_INIT_1_BINARY = 6'b111101; + default : begin + $display("Attribute Syntax Error : The Attribute SATA_MIN_INIT_1 on GTX_DUAL instance %m is set to %d. Legal values for this attribute are 1 to 61.", SATA_MIN_INIT_1); + $finish; + end + endcase + + case (SATA_MAX_INIT_1) + 1 : SATA_MAX_INIT_1_BINARY = 6'b000001; + 2 : SATA_MAX_INIT_1_BINARY = 6'b000010; + 3 : SATA_MAX_INIT_1_BINARY = 6'b000011; + 4 : SATA_MAX_INIT_1_BINARY = 6'b000100; + 5 : SATA_MAX_INIT_1_BINARY = 6'b000101; + 6 : SATA_MAX_INIT_1_BINARY = 6'b000110; + 7 : SATA_MAX_INIT_1_BINARY = 6'b000111; + 8 : SATA_MAX_INIT_1_BINARY = 6'b001000; + 9 : SATA_MAX_INIT_1_BINARY = 6'b001001; + 10 : SATA_MAX_INIT_1_BINARY = 6'b001010; + 11 : SATA_MAX_INIT_1_BINARY = 6'b001011; + 12 : SATA_MAX_INIT_1_BINARY = 6'b001100; + 13 : SATA_MAX_INIT_1_BINARY = 6'b001101; + 14 : SATA_MAX_INIT_1_BINARY = 6'b001110; + 15 : SATA_MAX_INIT_1_BINARY = 6'b001111; + 16 : SATA_MAX_INIT_1_BINARY = 6'b010000; + 17 : SATA_MAX_INIT_1_BINARY = 6'b010001; + 18 : SATA_MAX_INIT_1_BINARY = 6'b010010; + 19 : SATA_MAX_INIT_1_BINARY = 6'b010011; + 20 : SATA_MAX_INIT_1_BINARY = 6'b010100; + 21 : SATA_MAX_INIT_1_BINARY = 6'b010101; + 22 : SATA_MAX_INIT_1_BINARY = 6'b010110; + 23 : SATA_MAX_INIT_1_BINARY = 6'b010111; + 24 : SATA_MAX_INIT_1_BINARY = 6'b011000; + 25 : SATA_MAX_INIT_1_BINARY = 6'b011001; + 26 : SATA_MAX_INIT_1_BINARY = 6'b011010; + 27 : SATA_MAX_INIT_1_BINARY = 6'b011011; + 28 : SATA_MAX_INIT_1_BINARY = 6'b011100; + 29 : SATA_MAX_INIT_1_BINARY = 6'b011101; + 30 : SATA_MAX_INIT_1_BINARY = 6'b011110; + 31 : SATA_MAX_INIT_1_BINARY = 6'b011111; + 32 : SATA_MAX_INIT_1_BINARY = 6'b100000; + 33 : SATA_MAX_INIT_1_BINARY = 6'b100001; + 34 : SATA_MAX_INIT_1_BINARY = 6'b100010; + 35 : SATA_MAX_INIT_1_BINARY = 6'b100011; + 36 : SATA_MAX_INIT_1_BINARY = 6'b100100; + 37 : SATA_MAX_INIT_1_BINARY = 6'b100101; + 38 : SATA_MAX_INIT_1_BINARY = 6'b100110; + 39 : SATA_MAX_INIT_1_BINARY = 6'b100111; + 40 : SATA_MAX_INIT_1_BINARY = 6'b101000; + 41 : SATA_MAX_INIT_1_BINARY = 6'b101001; + 42 : SATA_MAX_INIT_1_BINARY = 6'b101010; + 43 : SATA_MAX_INIT_1_BINARY = 6'b101011; + 44 : SATA_MAX_INIT_1_BINARY = 6'b101100; + 45 : SATA_MAX_INIT_1_BINARY = 6'b101101; + 46 : SATA_MAX_INIT_1_BINARY = 6'b101110; + 47 : SATA_MAX_INIT_1_BINARY = 6'b101111; + 48 : SATA_MAX_INIT_1_BINARY = 6'b110000; + 49 : SATA_MAX_INIT_1_BINARY = 6'b110001; + 50 : SATA_MAX_INIT_1_BINARY = 6'b110010; + 51 : SATA_MAX_INIT_1_BINARY = 6'b110011; + 52 : SATA_MAX_INIT_1_BINARY = 6'b110100; + 53 : SATA_MAX_INIT_1_BINARY = 6'b110101; + 54 : SATA_MAX_INIT_1_BINARY = 6'b110110; + 55 : SATA_MAX_INIT_1_BINARY = 6'b110111; + 56 : SATA_MAX_INIT_1_BINARY = 6'b111000; + 57 : SATA_MAX_INIT_1_BINARY = 6'b111001; + 58 : SATA_MAX_INIT_1_BINARY = 6'b111010; + 59 : SATA_MAX_INIT_1_BINARY = 6'b111011; + 60 : SATA_MAX_INIT_1_BINARY = 6'b111100; + 61 : SATA_MAX_INIT_1_BINARY = 6'b111101; + default : begin + $display("Attribute Syntax Error : The Attribute SATA_MAX_INIT_1 on GTX_DUAL instance %m is set to %d. Legal values for this attribute are 1 to 61.", SATA_MAX_INIT_1); + $finish; + end + endcase + + case (SATA_MIN_WAKE_1) + 1 : SATA_MIN_WAKE_1_BINARY = 6'b000001; + 2 : SATA_MIN_WAKE_1_BINARY = 6'b000010; + 3 : SATA_MIN_WAKE_1_BINARY = 6'b000011; + 4 : SATA_MIN_WAKE_1_BINARY = 6'b000100; + 5 : SATA_MIN_WAKE_1_BINARY = 6'b000101; + 6 : SATA_MIN_WAKE_1_BINARY = 6'b000110; + 7 : SATA_MIN_WAKE_1_BINARY = 6'b000111; + 8 : SATA_MIN_WAKE_1_BINARY = 6'b001000; + 9 : SATA_MIN_WAKE_1_BINARY = 6'b001001; + 10 : SATA_MIN_WAKE_1_BINARY = 6'b001010; + 11 : SATA_MIN_WAKE_1_BINARY = 6'b001011; + 12 : SATA_MIN_WAKE_1_BINARY = 6'b001100; + 13 : SATA_MIN_WAKE_1_BINARY = 6'b001101; + 14 : SATA_MIN_WAKE_1_BINARY = 6'b001110; + 15 : SATA_MIN_WAKE_1_BINARY = 6'b001111; + 16 : SATA_MIN_WAKE_1_BINARY = 6'b010000; + 17 : SATA_MIN_WAKE_1_BINARY = 6'b010001; + 18 : SATA_MIN_WAKE_1_BINARY = 6'b010010; + 19 : SATA_MIN_WAKE_1_BINARY = 6'b010011; + 20 : SATA_MIN_WAKE_1_BINARY = 6'b010100; + 21 : SATA_MIN_WAKE_1_BINARY = 6'b010101; + 22 : SATA_MIN_WAKE_1_BINARY = 6'b010110; + 23 : SATA_MIN_WAKE_1_BINARY = 6'b010111; + 24 : SATA_MIN_WAKE_1_BINARY = 6'b011000; + 25 : SATA_MIN_WAKE_1_BINARY = 6'b011001; + 26 : SATA_MIN_WAKE_1_BINARY = 6'b011010; + 27 : SATA_MIN_WAKE_1_BINARY = 6'b011011; + 28 : SATA_MIN_WAKE_1_BINARY = 6'b011100; + 29 : SATA_MIN_WAKE_1_BINARY = 6'b011101; + 30 : SATA_MIN_WAKE_1_BINARY = 6'b011110; + 31 : SATA_MIN_WAKE_1_BINARY = 6'b011111; + 32 : SATA_MIN_WAKE_1_BINARY = 6'b100000; + 33 : SATA_MIN_WAKE_1_BINARY = 6'b100001; + 34 : SATA_MIN_WAKE_1_BINARY = 6'b100010; + 35 : SATA_MIN_WAKE_1_BINARY = 6'b100011; + 36 : SATA_MIN_WAKE_1_BINARY = 6'b100100; + 37 : SATA_MIN_WAKE_1_BINARY = 6'b100101; + 38 : SATA_MIN_WAKE_1_BINARY = 6'b100110; + 39 : SATA_MIN_WAKE_1_BINARY = 6'b100111; + 40 : SATA_MIN_WAKE_1_BINARY = 6'b101000; + 41 : SATA_MIN_WAKE_1_BINARY = 6'b101001; + 42 : SATA_MIN_WAKE_1_BINARY = 6'b101010; + 43 : SATA_MIN_WAKE_1_BINARY = 6'b101011; + 44 : SATA_MIN_WAKE_1_BINARY = 6'b101100; + 45 : SATA_MIN_WAKE_1_BINARY = 6'b101101; + 46 : SATA_MIN_WAKE_1_BINARY = 6'b101110; + 47 : SATA_MIN_WAKE_1_BINARY = 6'b101111; + 48 : SATA_MIN_WAKE_1_BINARY = 6'b110000; + 49 : SATA_MIN_WAKE_1_BINARY = 6'b110001; + 50 : SATA_MIN_WAKE_1_BINARY = 6'b110010; + 51 : SATA_MIN_WAKE_1_BINARY = 6'b110011; + 52 : SATA_MIN_WAKE_1_BINARY = 6'b110100; + 53 : SATA_MIN_WAKE_1_BINARY = 6'b110101; + 54 : SATA_MIN_WAKE_1_BINARY = 6'b110110; + 55 : SATA_MIN_WAKE_1_BINARY = 6'b110111; + 56 : SATA_MIN_WAKE_1_BINARY = 6'b111000; + 57 : SATA_MIN_WAKE_1_BINARY = 6'b111001; + 58 : SATA_MIN_WAKE_1_BINARY = 6'b111010; + 59 : SATA_MIN_WAKE_1_BINARY = 6'b111011; + 60 : SATA_MIN_WAKE_1_BINARY = 6'b111100; + 61 : SATA_MIN_WAKE_1_BINARY = 6'b111101; + default : begin + $display("Attribute Syntax Error : The Attribute SATA_MIN_WAKE_1 on GTX_DUAL instance %m is set to %d. Legal values for this attribute are 1 to 61.", SATA_MIN_WAKE_1); + $finish; + end + endcase + + case (SATA_MAX_WAKE_1) + 1 : SATA_MAX_WAKE_1_BINARY = 6'b000001; + 2 : SATA_MAX_WAKE_1_BINARY = 6'b000010; + 3 : SATA_MAX_WAKE_1_BINARY = 6'b000011; + 4 : SATA_MAX_WAKE_1_BINARY = 6'b000100; + 5 : SATA_MAX_WAKE_1_BINARY = 6'b000101; + 6 : SATA_MAX_WAKE_1_BINARY = 6'b000110; + 7 : SATA_MAX_WAKE_1_BINARY = 6'b000111; + 8 : SATA_MAX_WAKE_1_BINARY = 6'b001000; + 9 : SATA_MAX_WAKE_1_BINARY = 6'b001001; + 10 : SATA_MAX_WAKE_1_BINARY = 6'b001010; + 11 : SATA_MAX_WAKE_1_BINARY = 6'b001011; + 12 : SATA_MAX_WAKE_1_BINARY = 6'b001100; + 13 : SATA_MAX_WAKE_1_BINARY = 6'b001101; + 14 : SATA_MAX_WAKE_1_BINARY = 6'b001110; + 15 : SATA_MAX_WAKE_1_BINARY = 6'b001111; + 16 : SATA_MAX_WAKE_1_BINARY = 6'b010000; + 17 : SATA_MAX_WAKE_1_BINARY = 6'b010001; + 18 : SATA_MAX_WAKE_1_BINARY = 6'b010010; + 19 : SATA_MAX_WAKE_1_BINARY = 6'b010011; + 20 : SATA_MAX_WAKE_1_BINARY = 6'b010100; + 21 : SATA_MAX_WAKE_1_BINARY = 6'b010101; + 22 : SATA_MAX_WAKE_1_BINARY = 6'b010110; + 23 : SATA_MAX_WAKE_1_BINARY = 6'b010111; + 24 : SATA_MAX_WAKE_1_BINARY = 6'b011000; + 25 : SATA_MAX_WAKE_1_BINARY = 6'b011001; + 26 : SATA_MAX_WAKE_1_BINARY = 6'b011010; + 27 : SATA_MAX_WAKE_1_BINARY = 6'b011011; + 28 : SATA_MAX_WAKE_1_BINARY = 6'b011100; + 29 : SATA_MAX_WAKE_1_BINARY = 6'b011101; + 30 : SATA_MAX_WAKE_1_BINARY = 6'b011110; + 31 : SATA_MAX_WAKE_1_BINARY = 6'b011111; + 32 : SATA_MAX_WAKE_1_BINARY = 6'b100000; + 33 : SATA_MAX_WAKE_1_BINARY = 6'b100001; + 34 : SATA_MAX_WAKE_1_BINARY = 6'b100010; + 35 : SATA_MAX_WAKE_1_BINARY = 6'b100011; + 36 : SATA_MAX_WAKE_1_BINARY = 6'b100100; + 37 : SATA_MAX_WAKE_1_BINARY = 6'b100101; + 38 : SATA_MAX_WAKE_1_BINARY = 6'b100110; + 39 : SATA_MAX_WAKE_1_BINARY = 6'b100111; + 40 : SATA_MAX_WAKE_1_BINARY = 6'b101000; + 41 : SATA_MAX_WAKE_1_BINARY = 6'b101001; + 42 : SATA_MAX_WAKE_1_BINARY = 6'b101010; + 43 : SATA_MAX_WAKE_1_BINARY = 6'b101011; + 44 : SATA_MAX_WAKE_1_BINARY = 6'b101100; + 45 : SATA_MAX_WAKE_1_BINARY = 6'b101101; + 46 : SATA_MAX_WAKE_1_BINARY = 6'b101110; + 47 : SATA_MAX_WAKE_1_BINARY = 6'b101111; + 48 : SATA_MAX_WAKE_1_BINARY = 6'b110000; + 49 : SATA_MAX_WAKE_1_BINARY = 6'b110001; + 50 : SATA_MAX_WAKE_1_BINARY = 6'b110010; + 51 : SATA_MAX_WAKE_1_BINARY = 6'b110011; + 52 : SATA_MAX_WAKE_1_BINARY = 6'b110100; + 53 : SATA_MAX_WAKE_1_BINARY = 6'b110101; + 54 : SATA_MAX_WAKE_1_BINARY = 6'b110110; + 55 : SATA_MAX_WAKE_1_BINARY = 6'b110111; + 56 : SATA_MAX_WAKE_1_BINARY = 6'b111000; + 57 : SATA_MAX_WAKE_1_BINARY = 6'b111001; + 58 : SATA_MAX_WAKE_1_BINARY = 6'b111010; + 59 : SATA_MAX_WAKE_1_BINARY = 6'b111011; + 60 : SATA_MAX_WAKE_1_BINARY = 6'b111100; + 61 : SATA_MAX_WAKE_1_BINARY = 6'b111101; + default : begin + $display("Attribute Syntax Error : The Attribute SATA_MAX_WAKE_1 on GTX_DUAL instance %m is set to %d. Legal values for this attribute are 1 to 61.", SATA_MAX_WAKE_1); + $finish; + end + endcase + + case (CLK25_DIVIDER) + 1 : CLK25_DIVIDER_BINARY = 3'b000; + 2 : CLK25_DIVIDER_BINARY = 3'b001; + 3 : CLK25_DIVIDER_BINARY = 3'b010; + 4 : CLK25_DIVIDER_BINARY = 3'b011; + 5 : CLK25_DIVIDER_BINARY = 3'b100; + 6 : CLK25_DIVIDER_BINARY = 3'b101; + 10 : CLK25_DIVIDER_BINARY = 3'b110; + 12 : CLK25_DIVIDER_BINARY = 3'b111; + default : begin + $display("Attribute Syntax Error : The Attribute CLK25_DIVIDER on GTX_DUAL instance %m is set to %d. Legal values for this attribute are 1, 2, 3, 4, 5, 6, 10 or 12.", CLK25_DIVIDER); + $finish; + end + endcase + + case (OVERSAMPLE_MODE) + "FALSE" : OVERSAMPLE_MODE_BINARY = 1'b0; + "TRUE" : OVERSAMPLE_MODE_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute OVERSAMPLE_MODE on GTX_DUAL instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", OVERSAMPLE_MODE); + $finish; + end + endcase + + case (TXGEARBOX_USE_0) + "FALSE" : TXGEARBOX_USE_0_BINARY = 1'b0; + "TRUE" : TXGEARBOX_USE_0_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute TXGEARBOX_USE_0 on GTX_DUAL instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", TXGEARBOX_USE_0); + $finish; + end + endcase + + case (RXGEARBOX_USE_0) + "FALSE" : RXGEARBOX_USE_0_BINARY = 1'b0; + "TRUE" : RXGEARBOX_USE_0_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute RXGEARBOX_USE_0 on GTX_DUAL instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", RXGEARBOX_USE_0); + $finish; + end + endcase + + case (TXGEARBOX_USE_1) + "FALSE" : TXGEARBOX_USE_1_BINARY = 1'b0; + "TRUE" : TXGEARBOX_USE_1_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute TXGEARBOX_USE_1 on GTX_DUAL instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", TXGEARBOX_USE_1); + $finish; + end + endcase + + case (RXGEARBOX_USE_1) + "FALSE" : RXGEARBOX_USE_1_BINARY = 1'b0; + "TRUE" : RXGEARBOX_USE_1_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute RXGEARBOX_USE_1 on GTX_DUAL instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", RXGEARBOX_USE_1); + $finish; + end + endcase + + case (PLL_FB_DCCEN) + "FALSE" : PLL_FB_DCCEN_BINARY = 1'b0; + "TRUE" : PLL_FB_DCCEN_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute PLL_FB_DCCEN on GTX_DUAL instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", PLL_FB_DCCEN); + $finish; + end + endcase + + case (CLKRCV_TRST) + "FALSE" : CLKRCV_TRST_BINARY = 1'b0; + "TRUE" : CLKRCV_TRST_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute CLKRCV_TRST on GTX_DUAL instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", CLKRCV_TRST); + $finish; + end + endcase + + case (RX_EN_IDLE_HOLD_DFE_0) + "FALSE" : RX_EN_IDLE_HOLD_DFE_0_BINARY = 1'b0; + "TRUE" : RX_EN_IDLE_HOLD_DFE_0_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute RX_EN_IDLE_HOLD_DFE_0 on GTX_DUAL instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", RX_EN_IDLE_HOLD_DFE_0); + $finish; + end + endcase + + case (RX_EN_IDLE_RESET_BUF_0) + "FALSE" : RX_EN_IDLE_RESET_BUF_0_BINARY = 1'b0; + "TRUE" : RX_EN_IDLE_RESET_BUF_0_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute RX_EN_IDLE_RESET_BUF_0 on GTX_DUAL instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", RX_EN_IDLE_RESET_BUF_0); + $finish; + end + endcase + + case (RX_EN_IDLE_HOLD_DFE_1) + "FALSE" : RX_EN_IDLE_HOLD_DFE_1_BINARY = 1'b0; + "TRUE" : RX_EN_IDLE_HOLD_DFE_1_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute RX_EN_IDLE_HOLD_DFE_1 on GTX_DUAL instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", RX_EN_IDLE_HOLD_DFE_1); + $finish; + end + endcase + + case (RX_EN_IDLE_RESET_BUF_1) + "FALSE" : RX_EN_IDLE_RESET_BUF_1_BINARY = 1'b0; + "TRUE" : RX_EN_IDLE_RESET_BUF_1_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute RX_EN_IDLE_RESET_BUF_1 on GTX_DUAL instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", RX_EN_IDLE_RESET_BUF_1); + $finish; + end + endcase + + case (RX_EN_IDLE_HOLD_CDR) + "FALSE" : RX_EN_IDLE_HOLD_CDR_BINARY = 1'b0; + "TRUE" : RX_EN_IDLE_HOLD_CDR_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute RX_EN_IDLE_HOLD_CDR on GTX_DUAL instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", RX_EN_IDLE_HOLD_CDR); + $finish; + end + endcase + + case (RX_EN_IDLE_RESET_PH) + "FALSE" : RX_EN_IDLE_RESET_PH_BINARY = 1'b0; + "TRUE" : RX_EN_IDLE_RESET_PH_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute RX_EN_IDLE_RESET_PH on GTX_DUAL instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", RX_EN_IDLE_RESET_PH); + $finish; + end + endcase + + case (RX_EN_IDLE_RESET_FR) + "FALSE" : RX_EN_IDLE_RESET_FR_BINARY = 1'b0; + "TRUE" : RX_EN_IDLE_RESET_FR_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute RX_EN_IDLE_RESET_FR on GTX_DUAL instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", RX_EN_IDLE_RESET_FR); + $finish; + end + endcase + + case (SIM_GTXRESET_SPEEDUP) + 0 : SIM_GTXRESET_SPEEDUP_BINARY = 0; + 1 : SIM_GTXRESET_SPEEDUP_BINARY = 1; + default : begin + $display("Attribute Syntax Error : The Attribute SIM_GTXRESET_SPEEDUP on GTX_DUAL instance %m is set to %d. Legal values for this attribute are 0 or 1.", SIM_GTXRESET_SPEEDUP); + $finish; + end + endcase + + case (SIM_MODE) + "FAST" : SIM_MODE_BINARY = 1'b1; + "LEGACY" : begin + $display("Attribute Syntax Warning : The Attribute SIM_MODE on GTX_DUAL instance %m is set to %s. The Legacy model is not supported from ISE 11.1 onwards. GTX_DUAL defaults to FAST model. There are no functionality differences between GTX_DUAL LEGACY and GTX_DUAL FAST simulation models. Although, if you want to use the GTX_DUAL LEGACY model, please use an earlier ISE build", SIM_MODE); + //$finish; + end + default : begin + $display("Attribute Syntax Warning : The Attribute SIM_MODE on GTX_DUAL instance %m is set to %s. Legal value for this attribute is FAST.", SIM_MODE); + //$finish; + end + endcase + + case (SIM_RECEIVER_DETECT_PASS_0) + "FALSE" : SIM_RECEIVER_DETECT_PASS_0_BINARY = 1'b0; + "TRUE" : SIM_RECEIVER_DETECT_PASS_0_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute SIM_RECEIVER_DETECT_PASS_0 on GTX_DUAL instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", SIM_RECEIVER_DETECT_PASS_0); + $finish; + end + endcase + + case (SIM_RECEIVER_DETECT_PASS_1) + "FALSE" : SIM_RECEIVER_DETECT_PASS_1_BINARY = 1'b0; + "TRUE" : SIM_RECEIVER_DETECT_PASS_1_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute SIM_RECEIVER_DETECT_PASS_1 on GTX_DUAL instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", SIM_RECEIVER_DETECT_PASS_1); + $finish; + end + endcase + +end + +wire DRDY_delay; +wire PHYSTATUS0_delay; +wire PHYSTATUS1_delay; +wire PLLLKDET_delay; +wire REFCLKOUT_delay; +wire RESETDONE0_delay; +wire RESETDONE1_delay; +wire RXBYTEISALIGNED0_delay; +wire RXBYTEISALIGNED1_delay; +wire RXBYTEREALIGN0_delay; +wire RXBYTEREALIGN1_delay; +wire RXCHANBONDSEQ0_delay; +wire RXCHANBONDSEQ1_delay; +wire RXCHANISALIGNED0_delay; +wire RXCHANISALIGNED1_delay; +wire RXCHANREALIGN0_delay; +wire RXCHANREALIGN1_delay; +wire RXCOMMADET0_delay; +wire RXCOMMADET1_delay; +wire RXDATAVALID0_delay; +wire RXDATAVALID1_delay; +wire RXELECIDLE0_delay; +wire RXELECIDLE1_delay; +wire RXHEADERVALID0_delay; +wire RXHEADERVALID1_delay; +wire RXOVERSAMPLEERR0_delay; +wire RXOVERSAMPLEERR1_delay; +wire RXPRBSERR0_delay; +wire RXPRBSERR1_delay; +wire RXRECCLK0_delay; +wire RXRECCLK1_delay; +wire RXSTARTOFSEQ0_delay; +wire RXSTARTOFSEQ1_delay; +wire RXVALID0_delay; +wire RXVALID1_delay; +wire TXGEARBOXREADY0_delay; +wire TXGEARBOXREADY1_delay; +wire TXN0_delay; +wire TXN1_delay; +wire TXOUTCLK0_delay; +wire TXOUTCLK1_delay; +wire TXP0_delay; +wire TXP1_delay; +wire [15:0] DO_delay; +wire [1:0] RXLOSSOFSYNC0_delay; +wire [1:0] RXLOSSOFSYNC1_delay; +wire [1:0] TXBUFSTATUS0_delay; +wire [1:0] TXBUFSTATUS1_delay; +wire [2:0] DFESENSCAL0_delay; +wire [2:0] DFESENSCAL1_delay; +wire [2:0] RXBUFSTATUS0_delay; +wire [2:0] RXBUFSTATUS1_delay; +wire [2:0] RXCLKCORCNT0_delay; +wire [2:0] RXCLKCORCNT1_delay; +wire [2:0] RXHEADER0_delay; +wire [2:0] RXHEADER1_delay; +wire [2:0] RXSTATUS0_delay; +wire [2:0] RXSTATUS1_delay; +wire [31:0] RXDATA0_delay; +wire [31:0] RXDATA1_delay; +wire [3:0] DFETAP3MONITOR0_delay; +wire [3:0] DFETAP3MONITOR1_delay; +wire [3:0] DFETAP4MONITOR0_delay; +wire [3:0] DFETAP4MONITOR1_delay; +wire [3:0] RXCHARISCOMMA0_delay; +wire [3:0] RXCHARISCOMMA1_delay; +wire [3:0] RXCHARISK0_delay; +wire [3:0] RXCHARISK1_delay; +wire [3:0] RXCHBONDO0_delay; +wire [3:0] RXCHBONDO1_delay; +wire [3:0] RXDISPERR0_delay; +wire [3:0] RXDISPERR1_delay; +wire [3:0] RXNOTINTABLE0_delay; +wire [3:0] RXNOTINTABLE1_delay; +wire [3:0] RXRUNDISP0_delay; +wire [3:0] RXRUNDISP1_delay; +wire [3:0] TXKERR0_delay; +wire [3:0] TXKERR1_delay; +wire [3:0] TXRUNDISP0_delay; +wire [3:0] TXRUNDISP1_delay; +wire [4:0] DFEEYEDACMONITOR0_delay; +wire [4:0] DFEEYEDACMONITOR1_delay; +wire [4:0] DFETAP1MONITOR0_delay; +wire [4:0] DFETAP1MONITOR1_delay; +wire [4:0] DFETAP2MONITOR0_delay; +wire [4:0] DFETAP2MONITOR1_delay; +wire [5:0] DFECLKDLYADJMONITOR0_delay; +wire [5:0] DFECLKDLYADJMONITOR1_delay; + +wire CLKIN_delay; +wire DCLK_delay; +wire DEN_delay; +wire DWE_delay; +wire GTXRESET_delay; +wire INTDATAWIDTH_delay; +wire PLLLKDETEN_delay; +wire PLLPOWERDOWN_delay; +wire PRBSCNTRESET0_delay; +wire PRBSCNTRESET1_delay; +wire REFCLKPWRDNB_delay; +wire RXBUFRESET0_delay; +wire RXBUFRESET1_delay; +wire RXCDRRESET0_delay; +wire RXCDRRESET1_delay; +wire RXCOMMADETUSE0_delay; +wire RXCOMMADETUSE1_delay; +wire RXDEC8B10BUSE0_delay; +wire RXDEC8B10BUSE1_delay; +wire RXENCHANSYNC0_delay; +wire RXENCHANSYNC1_delay; +wire RXENEQB0_delay; +wire RXENEQB1_delay; +wire RXENMCOMMAALIGN0_delay; +wire RXENMCOMMAALIGN1_delay; +wire RXENPCOMMAALIGN0_delay; +wire RXENPCOMMAALIGN1_delay; +wire RXENPMAPHASEALIGN0_delay; +wire RXENPMAPHASEALIGN1_delay; +wire RXENSAMPLEALIGN0_delay; +wire RXENSAMPLEALIGN1_delay; +wire RXGEARBOXSLIP0_delay; +wire RXGEARBOXSLIP1_delay; +wire RXN0_delay; +wire RXN1_delay; +wire RXP0_delay; +wire RXP1_delay; +wire RXPMASETPHASE0_delay; +wire RXPMASETPHASE1_delay; +wire RXPOLARITY0_delay; +wire RXPOLARITY1_delay; +wire RXRESET0_delay; +wire RXRESET1_delay; +wire RXSLIDE0_delay; +wire RXSLIDE1_delay; +wire RXUSRCLK0_delay; +wire RXUSRCLK1_delay; +wire RXUSRCLK20_delay; +wire RXUSRCLK21_delay; +wire TXCOMSTART0_delay; +wire TXCOMSTART1_delay; +wire TXCOMTYPE0_delay; +wire TXCOMTYPE1_delay; +wire TXDETECTRX0_delay; +wire TXDETECTRX1_delay; +wire TXELECIDLE0_delay; +wire TXELECIDLE1_delay; +wire TXENC8B10BUSE0_delay; +wire TXENC8B10BUSE1_delay; +wire TXENPMAPHASEALIGN0_delay; +wire TXENPMAPHASEALIGN1_delay; +wire TXINHIBIT0_delay; +wire TXINHIBIT1_delay; +wire TXPMASETPHASE0_delay; +wire TXPMASETPHASE1_delay; +wire TXPOLARITY0_delay; +wire TXPOLARITY1_delay; +wire TXRESET0_delay; +wire TXRESET1_delay; +wire TXSTARTSEQ0_delay; +wire TXSTARTSEQ1_delay; +wire TXUSRCLK0_delay; +wire TXUSRCLK1_delay; +wire TXUSRCLK20_delay; +wire TXUSRCLK21_delay; +wire [13:0] GTXTEST_delay; +wire [15:0] DI_delay; +wire [1:0] RXDATAWIDTH0_delay; +wire [1:0] RXDATAWIDTH1_delay; +wire [1:0] RXENPRBSTST0_delay; +wire [1:0] RXENPRBSTST1_delay; +wire [1:0] RXEQMIX0_delay; +wire [1:0] RXEQMIX1_delay; +wire [1:0] RXPOWERDOWN0_delay; +wire [1:0] RXPOWERDOWN1_delay; +wire [1:0] TXDATAWIDTH0_delay; +wire [1:0] TXDATAWIDTH1_delay; +wire [1:0] TXENPRBSTST0_delay; +wire [1:0] TXENPRBSTST1_delay; +wire [1:0] TXPOWERDOWN0_delay; +wire [1:0] TXPOWERDOWN1_delay; +wire [2:0] LOOPBACK0_delay; +wire [2:0] LOOPBACK1_delay; +wire [2:0] TXBUFDIFFCTRL0_delay; +wire [2:0] TXBUFDIFFCTRL1_delay; +wire [2:0] TXDIFFCTRL0_delay; +wire [2:0] TXDIFFCTRL1_delay; +wire [2:0] TXHEADER0_delay; +wire [2:0] TXHEADER1_delay; +wire [31:0] TXDATA0_delay; +wire [31:0] TXDATA1_delay; +wire [3:0] DFETAP30_delay; +wire [3:0] DFETAP31_delay; +wire [3:0] DFETAP40_delay; +wire [3:0] DFETAP41_delay; +wire [3:0] RXCHBONDI0_delay; +wire [3:0] RXCHBONDI1_delay; +wire [3:0] RXEQPOLE0_delay; +wire [3:0] RXEQPOLE1_delay; +wire [3:0] TXBYPASS8B10B0_delay; +wire [3:0] TXBYPASS8B10B1_delay; +wire [3:0] TXCHARDISPMODE0_delay; +wire [3:0] TXCHARDISPMODE1_delay; +wire [3:0] TXCHARDISPVAL0_delay; +wire [3:0] TXCHARDISPVAL1_delay; +wire [3:0] TXCHARISK0_delay; +wire [3:0] TXCHARISK1_delay; +wire [3:0] TXPREEMPHASIS0_delay; +wire [3:0] TXPREEMPHASIS1_delay; +wire [4:0] DFETAP10_delay; +wire [4:0] DFETAP11_delay; +wire [4:0] DFETAP20_delay; +wire [4:0] DFETAP21_delay; +wire [5:0] DFECLKDLYADJ0_delay; +wire [5:0] DFECLKDLYADJ1_delay; +wire [6:0] DADDR_delay; +wire [6:0] TXSEQUENCE0_delay; +wire [6:0] TXSEQUENCE1_delay; + +assign #(CLK_DELAY) DFECLKDLYADJMONITOR0 = DFECLKDLYADJMONITOR0_delay; +assign #(CLK_DELAY) DFECLKDLYADJMONITOR1 = DFECLKDLYADJMONITOR1_delay; +assign #(CLK_DELAY) REFCLKOUT = REFCLKOUT_delay; +assign #(CLK_DELAY) RXCLKCORCNT0 = RXCLKCORCNT0_delay; +assign #(CLK_DELAY) RXCLKCORCNT1 = RXCLKCORCNT1_delay; +assign #(CLK_DELAY) RXRECCLK0 = RXRECCLK0_delay; +assign #(CLK_DELAY) RXRECCLK1 = RXRECCLK1_delay; +assign #(CLK_DELAY) TXOUTCLK0 = TXOUTCLK0_delay; +assign #(CLK_DELAY) TXOUTCLK1 = TXOUTCLK1_delay; + +assign #(out_delay) DFEEYEDACMONITOR0 = DFEEYEDACMONITOR0_delay; +assign #(out_delay) DFEEYEDACMONITOR1 = DFEEYEDACMONITOR1_delay; +assign #(out_delay) DFESENSCAL0 = DFESENSCAL0_delay; +assign #(out_delay) DFESENSCAL1 = DFESENSCAL1_delay; +assign #(out_delay) DFETAP1MONITOR0 = DFETAP1MONITOR0_delay; +assign #(out_delay) DFETAP1MONITOR1 = DFETAP1MONITOR1_delay; +assign #(out_delay) DFETAP2MONITOR0 = DFETAP2MONITOR0_delay; +assign #(out_delay) DFETAP2MONITOR1 = DFETAP2MONITOR1_delay; +assign #(out_delay) DFETAP3MONITOR0 = DFETAP3MONITOR0_delay; +assign #(out_delay) DFETAP3MONITOR1 = DFETAP3MONITOR1_delay; +assign #(out_delay) DFETAP4MONITOR0 = DFETAP4MONITOR0_delay; +assign #(out_delay) DFETAP4MONITOR1 = DFETAP4MONITOR1_delay; +assign #(out_delay) DO = DO_delay; +assign #(out_delay) DRDY = DRDY_delay; +assign #(out_delay) PHYSTATUS0 = PHYSTATUS0_delay; +assign #(out_delay) PHYSTATUS1 = PHYSTATUS1_delay; +assign #(out_delay) PLLLKDET = PLLLKDET_delay; +assign #(out_delay) RESETDONE0 = RESETDONE0_delay; +assign #(out_delay) RESETDONE1 = RESETDONE1_delay; +assign #(out_delay) RXBUFSTATUS0 = RXBUFSTATUS0_delay; +assign #(out_delay) RXBUFSTATUS1 = RXBUFSTATUS1_delay; +assign #(out_delay) RXBYTEISALIGNED0 = RXBYTEISALIGNED0_delay; +assign #(out_delay) RXBYTEISALIGNED1 = RXBYTEISALIGNED1_delay; +assign #(out_delay) RXBYTEREALIGN0 = RXBYTEREALIGN0_delay; +assign #(out_delay) RXBYTEREALIGN1 = RXBYTEREALIGN1_delay; +assign #(out_delay) RXCHANBONDSEQ0 = RXCHANBONDSEQ0_delay; +assign #(out_delay) RXCHANBONDSEQ1 = RXCHANBONDSEQ1_delay; +assign #(out_delay) RXCHANISALIGNED0 = RXCHANISALIGNED0_delay; +assign #(out_delay) RXCHANISALIGNED1 = RXCHANISALIGNED1_delay; +assign #(out_delay) RXCHANREALIGN0 = RXCHANREALIGN0_delay; +assign #(out_delay) RXCHANREALIGN1 = RXCHANREALIGN1_delay; +assign #(out_delay) RXCHARISCOMMA0 = RXCHARISCOMMA0_delay; +assign #(out_delay) RXCHARISCOMMA1 = RXCHARISCOMMA1_delay; +assign #(out_delay) RXCHARISK0 = RXCHARISK0_delay; +assign #(out_delay) RXCHARISK1 = RXCHARISK1_delay; +assign #(out_delay) RXCHBONDO0 = RXCHBONDO0_delay; +assign #(out_delay) RXCHBONDO1 = RXCHBONDO1_delay; +assign #(out_delay) RXCOMMADET0 = RXCOMMADET0_delay; +assign #(out_delay) RXCOMMADET1 = RXCOMMADET1_delay; +assign #(out_delay) RXDATA0 = RXDATA0_delay; +assign #(out_delay) RXDATA1 = RXDATA1_delay; +assign #(out_delay) RXDATAVALID0 = RXDATAVALID0_delay; +assign #(out_delay) RXDATAVALID1 = RXDATAVALID1_delay; +assign #(out_delay) RXDISPERR0 = RXDISPERR0_delay; +assign #(out_delay) RXDISPERR1 = RXDISPERR1_delay; +assign #(out_delay) RXELECIDLE0 = RXELECIDLE0_delay; +assign #(out_delay) RXELECIDLE1 = RXELECIDLE1_delay; +assign #(out_delay) RXHEADER0 = RXHEADER0_delay; +assign #(out_delay) RXHEADER1 = RXHEADER1_delay; +assign #(out_delay) RXHEADERVALID0 = RXHEADERVALID0_delay; +assign #(out_delay) RXHEADERVALID1 = RXHEADERVALID1_delay; +assign #(out_delay) RXLOSSOFSYNC0 = RXLOSSOFSYNC0_delay; +assign #(out_delay) RXLOSSOFSYNC1 = RXLOSSOFSYNC1_delay; +assign #(out_delay) RXNOTINTABLE0 = RXNOTINTABLE0_delay; +assign #(out_delay) RXNOTINTABLE1 = RXNOTINTABLE1_delay; +assign #(out_delay) RXOVERSAMPLEERR0 = RXOVERSAMPLEERR0_delay; +assign #(out_delay) RXOVERSAMPLEERR1 = RXOVERSAMPLEERR1_delay; +assign #(out_delay) RXPRBSERR0 = RXPRBSERR0_delay; +assign #(out_delay) RXPRBSERR1 = RXPRBSERR1_delay; +assign #(out_delay) RXRUNDISP0 = RXRUNDISP0_delay; +assign #(out_delay) RXRUNDISP1 = RXRUNDISP1_delay; +assign #(out_delay) RXSTARTOFSEQ0 = RXSTARTOFSEQ0_delay; +assign #(out_delay) RXSTARTOFSEQ1 = RXSTARTOFSEQ1_delay; +assign #(out_delay) RXSTATUS0 = RXSTATUS0_delay; +assign #(out_delay) RXSTATUS1 = RXSTATUS1_delay; +assign #(out_delay) RXVALID0 = RXVALID0_delay; +assign #(out_delay) RXVALID1 = RXVALID1_delay; +assign #(out_delay) TXBUFSTATUS0 = TXBUFSTATUS0_delay; +assign #(out_delay) TXBUFSTATUS1 = TXBUFSTATUS1_delay; +assign #(out_delay) TXGEARBOXREADY0 = TXGEARBOXREADY0_delay; +assign #(out_delay) TXGEARBOXREADY1 = TXGEARBOXREADY1_delay; +assign #(out_delay) TXKERR0 = TXKERR0_delay; +assign #(out_delay) TXKERR1 = TXKERR1_delay; +assign #(out_delay) TXN0 = TXN0_delay; +assign #(out_delay) TXN1 = TXN1_delay; +assign #(out_delay) TXP0 = TXP0_delay; +assign #(out_delay) TXP1 = TXP1_delay; +assign #(out_delay) TXRUNDISP0 = TXRUNDISP0_delay; +assign #(out_delay) TXRUNDISP1 = TXRUNDISP1_delay; + +assign #(CLK_DELAY) DCLK_delay = DCLK; +assign #(CLK_DELAY) RXUSRCLK0_delay = RXUSRCLK0; +assign #(CLK_DELAY) RXUSRCLK1_delay = RXUSRCLK1; +assign #(CLK_DELAY) RXUSRCLK20_delay = RXUSRCLK20; +assign #(CLK_DELAY) RXUSRCLK21_delay = RXUSRCLK21; +assign #(CLK_DELAY) TXUSRCLK0_delay = TXUSRCLK0; +assign #(CLK_DELAY) TXUSRCLK1_delay = TXUSRCLK1; +assign #(CLK_DELAY) TXUSRCLK20_delay = TXUSRCLK20; +assign #(CLK_DELAY) TXUSRCLK21_delay = TXUSRCLK21; + +assign #(in_delay) CLKIN_delay = CLKIN; +assign #(in_delay) DADDR_delay = DADDR; +assign #(in_delay) DEN_delay = DEN; +assign #(in_delay) DFECLKDLYADJ0_delay = DFECLKDLYADJ0; +assign #(in_delay) DFECLKDLYADJ1_delay = DFECLKDLYADJ1; +assign #(in_delay) DFETAP10_delay = DFETAP10; +assign #(in_delay) DFETAP11_delay = DFETAP11; +assign #(in_delay) DFETAP20_delay = DFETAP20; +assign #(in_delay) DFETAP21_delay = DFETAP21; +assign #(in_delay) DFETAP30_delay = DFETAP30; +assign #(in_delay) DFETAP31_delay = DFETAP31; +assign #(in_delay) DFETAP40_delay = DFETAP40; +assign #(in_delay) DFETAP41_delay = DFETAP41; +assign #(in_delay) DI_delay = DI; +assign #(in_delay) DWE_delay = DWE; +assign #(in_delay) GTXRESET_delay = GTXRESET; +assign #(in_delay) GTXTEST_delay = GTXTEST; +assign #(in_delay) INTDATAWIDTH_delay = INTDATAWIDTH; +assign #(in_delay) LOOPBACK0_delay = LOOPBACK0; +assign #(in_delay) LOOPBACK1_delay = LOOPBACK1; +assign #(in_delay) PLLLKDETEN_delay = PLLLKDETEN; +assign #(in_delay) PLLPOWERDOWN_delay = PLLPOWERDOWN; +assign #(in_delay) PRBSCNTRESET0_delay = PRBSCNTRESET0; +assign #(in_delay) PRBSCNTRESET1_delay = PRBSCNTRESET1; +assign #(in_delay) REFCLKPWRDNB_delay = REFCLKPWRDNB; +assign #(in_delay) RXBUFRESET0_delay = RXBUFRESET0; +assign #(in_delay) RXBUFRESET1_delay = RXBUFRESET1; +assign #(in_delay) RXCDRRESET0_delay = RXCDRRESET0; +assign #(in_delay) RXCDRRESET1_delay = RXCDRRESET1; +assign #(in_delay) RXCHBONDI0_delay = RXCHBONDI0; +assign #(in_delay) RXCHBONDI1_delay = RXCHBONDI1; +assign #(in_delay) RXCOMMADETUSE0_delay = RXCOMMADETUSE0; +assign #(in_delay) RXCOMMADETUSE1_delay = RXCOMMADETUSE1; +assign #(in_delay) RXDATAWIDTH0_delay = RXDATAWIDTH0; +assign #(in_delay) RXDATAWIDTH1_delay = RXDATAWIDTH1; +assign #(in_delay) RXDEC8B10BUSE0_delay = RXDEC8B10BUSE0; +assign #(in_delay) RXDEC8B10BUSE1_delay = RXDEC8B10BUSE1; +assign #(in_delay) RXENCHANSYNC0_delay = RXENCHANSYNC0; +assign #(in_delay) RXENCHANSYNC1_delay = RXENCHANSYNC1; +assign #(in_delay) RXENEQB0_delay = RXENEQB0; +assign #(in_delay) RXENEQB1_delay = RXENEQB1; +assign #(in_delay) RXENMCOMMAALIGN0_delay = RXENMCOMMAALIGN0; +assign #(in_delay) RXENMCOMMAALIGN1_delay = RXENMCOMMAALIGN1; +assign #(in_delay) RXENPCOMMAALIGN0_delay = RXENPCOMMAALIGN0; +assign #(in_delay) RXENPCOMMAALIGN1_delay = RXENPCOMMAALIGN1; +assign #(in_delay) RXENPMAPHASEALIGN0_delay = RXENPMAPHASEALIGN0; +assign #(in_delay) RXENPMAPHASEALIGN1_delay = RXENPMAPHASEALIGN1; +assign #(in_delay) RXENPRBSTST0_delay = RXENPRBSTST0; +assign #(in_delay) RXENPRBSTST1_delay = RXENPRBSTST1; +assign #(in_delay) RXENSAMPLEALIGN0_delay = RXENSAMPLEALIGN0; +assign #(in_delay) RXENSAMPLEALIGN1_delay = RXENSAMPLEALIGN1; +assign #(in_delay) RXEQMIX0_delay = RXEQMIX0; +assign #(in_delay) RXEQMIX1_delay = RXEQMIX1; +assign #(in_delay) RXEQPOLE0_delay = RXEQPOLE0; +assign #(in_delay) RXEQPOLE1_delay = RXEQPOLE1; +assign #(in_delay) RXGEARBOXSLIP0_delay = RXGEARBOXSLIP0; +assign #(in_delay) RXGEARBOXSLIP1_delay = RXGEARBOXSLIP1; +assign #(in_delay) RXN0_delay = RXN0; +assign #(in_delay) RXN1_delay = RXN1; +assign #(in_delay) RXP0_delay = RXP0; +assign #(in_delay) RXP1_delay = RXP1; +assign #(in_delay) RXPMASETPHASE0_delay = RXPMASETPHASE0; +assign #(in_delay) RXPMASETPHASE1_delay = RXPMASETPHASE1; +assign #(in_delay) RXPOLARITY0_delay = RXPOLARITY0; +assign #(in_delay) RXPOLARITY1_delay = RXPOLARITY1; +assign #(in_delay) RXPOWERDOWN0_delay = RXPOWERDOWN0; +assign #(in_delay) RXPOWERDOWN1_delay = RXPOWERDOWN1; +assign #(in_delay) RXRESET0_delay = RXRESET0; +assign #(in_delay) RXRESET1_delay = RXRESET1; +assign #(in_delay) RXSLIDE0_delay = RXSLIDE0; +assign #(in_delay) RXSLIDE1_delay = RXSLIDE1; +assign #(in_delay) TXBUFDIFFCTRL0_delay = TXBUFDIFFCTRL0; +assign #(in_delay) TXBUFDIFFCTRL1_delay = TXBUFDIFFCTRL1; +assign #(in_delay) TXBYPASS8B10B0_delay = TXBYPASS8B10B0; +assign #(in_delay) TXBYPASS8B10B1_delay = TXBYPASS8B10B1; +assign #(in_delay) TXCHARDISPMODE0_delay = TXCHARDISPMODE0; +assign #(in_delay) TXCHARDISPMODE1_delay = TXCHARDISPMODE1; +assign #(in_delay) TXCHARDISPVAL0_delay = TXCHARDISPVAL0; +assign #(in_delay) TXCHARDISPVAL1_delay = TXCHARDISPVAL1; +assign #(in_delay) TXCHARISK0_delay = TXCHARISK0; +assign #(in_delay) TXCHARISK1_delay = TXCHARISK1; +assign #(in_delay) TXCOMSTART0_delay = TXCOMSTART0; +assign #(in_delay) TXCOMSTART1_delay = TXCOMSTART1; +assign #(in_delay) TXCOMTYPE0_delay = TXCOMTYPE0; +assign #(in_delay) TXCOMTYPE1_delay = TXCOMTYPE1; +assign #(in_delay) TXDATA0_delay = TXDATA0; +assign #(in_delay) TXDATA1_delay = TXDATA1; +assign #(in_delay) TXDATAWIDTH0_delay = TXDATAWIDTH0; +assign #(in_delay) TXDATAWIDTH1_delay = TXDATAWIDTH1; +assign #(in_delay) TXDETECTRX0_delay = TXDETECTRX0; +assign #(in_delay) TXDETECTRX1_delay = TXDETECTRX1; +assign #(in_delay) TXDIFFCTRL0_delay = TXDIFFCTRL0; +assign #(in_delay) TXDIFFCTRL1_delay = TXDIFFCTRL1; +assign #(in_delay) TXELECIDLE0_delay = TXELECIDLE0; +assign #(in_delay) TXELECIDLE1_delay = TXELECIDLE1; +assign #(in_delay) TXENC8B10BUSE0_delay = TXENC8B10BUSE0; +assign #(in_delay) TXENC8B10BUSE1_delay = TXENC8B10BUSE1; +assign #(in_delay) TXENPMAPHASEALIGN0_delay = TXENPMAPHASEALIGN0; +assign #(in_delay) TXENPMAPHASEALIGN1_delay = TXENPMAPHASEALIGN1; +assign #(in_delay) TXENPRBSTST0_delay = TXENPRBSTST0; +assign #(in_delay) TXENPRBSTST1_delay = TXENPRBSTST1; +assign #(in_delay) TXHEADER0_delay = TXHEADER0; +assign #(in_delay) TXHEADER1_delay = TXHEADER1; +assign #(in_delay) TXINHIBIT0_delay = TXINHIBIT0; +assign #(in_delay) TXINHIBIT1_delay = TXINHIBIT1; +assign #(in_delay) TXPMASETPHASE0_delay = TXPMASETPHASE0; +assign #(in_delay) TXPMASETPHASE1_delay = TXPMASETPHASE1; +assign #(in_delay) TXPOLARITY0_delay = TXPOLARITY0; +assign #(in_delay) TXPOLARITY1_delay = TXPOLARITY1; +assign #(in_delay) TXPOWERDOWN0_delay = TXPOWERDOWN0; +assign #(in_delay) TXPOWERDOWN1_delay = TXPOWERDOWN1; +assign #(in_delay) TXPREEMPHASIS0_delay = TXPREEMPHASIS0; +assign #(in_delay) TXPREEMPHASIS1_delay = TXPREEMPHASIS1; +assign #(in_delay) TXRESET0_delay = TXRESET0; +assign #(in_delay) TXRESET1_delay = TXRESET1; +assign #(in_delay) TXSEQUENCE0_delay = TXSEQUENCE0; +assign #(in_delay) TXSEQUENCE1_delay = TXSEQUENCE1; +assign #(in_delay) TXSTARTSEQ0_delay = TXSTARTSEQ0; +assign #(in_delay) TXSTARTSEQ1_delay = TXSTARTSEQ1; + + GTX_DUAL_FAST gtx_dual_fast_1 ( + .AC_CAP_DIS_0 (AC_CAP_DIS_0_BINARY), + .AC_CAP_DIS_1 (AC_CAP_DIS_1_BINARY), + .ALIGN_COMMA_WORD_0 (ALIGN_COMMA_WORD_0_BINARY), + .ALIGN_COMMA_WORD_1 (ALIGN_COMMA_WORD_1_BINARY), + .CB2_INH_CC_PERIOD_0 (CB2_INH_CC_PERIOD_0_BINARY), + .CB2_INH_CC_PERIOD_1 (CB2_INH_CC_PERIOD_1_BINARY), + .CDR_PH_ADJ_TIME (CDR_PH_ADJ_TIME), + .CHAN_BOND_1_MAX_SKEW_0 (CHAN_BOND_1_MAX_SKEW_0_BINARY), + .CHAN_BOND_1_MAX_SKEW_1 (CHAN_BOND_1_MAX_SKEW_1_BINARY), + .CHAN_BOND_2_MAX_SKEW_0 (CHAN_BOND_2_MAX_SKEW_0_BINARY), + .CHAN_BOND_2_MAX_SKEW_1 (CHAN_BOND_2_MAX_SKEW_1_BINARY), + .CHAN_BOND_KEEP_ALIGN_0 (CHAN_BOND_KEEP_ALIGN_0_BINARY), + .CHAN_BOND_KEEP_ALIGN_1 (CHAN_BOND_KEEP_ALIGN_1_BINARY), + .CHAN_BOND_LEVEL_0 (CHAN_BOND_LEVEL_0_BINARY), + .CHAN_BOND_LEVEL_1 (CHAN_BOND_LEVEL_1_BINARY), + .CHAN_BOND_MODE_0 (CHAN_BOND_MODE_0_BINARY), + .CHAN_BOND_MODE_1 (CHAN_BOND_MODE_1_BINARY), + .CHAN_BOND_SEQ_1_1_0 (CHAN_BOND_SEQ_1_1_0), + .CHAN_BOND_SEQ_1_1_1 (CHAN_BOND_SEQ_1_1_1), + .CHAN_BOND_SEQ_1_2_0 (CHAN_BOND_SEQ_1_2_0), + .CHAN_BOND_SEQ_1_2_1 (CHAN_BOND_SEQ_1_2_1), + .CHAN_BOND_SEQ_1_3_0 (CHAN_BOND_SEQ_1_3_0), + .CHAN_BOND_SEQ_1_3_1 (CHAN_BOND_SEQ_1_3_1), + .CHAN_BOND_SEQ_1_4_0 (CHAN_BOND_SEQ_1_4_0), + .CHAN_BOND_SEQ_1_4_1 (CHAN_BOND_SEQ_1_4_1), + .CHAN_BOND_SEQ_1_ENABLE_0 (CHAN_BOND_SEQ_1_ENABLE_0), + .CHAN_BOND_SEQ_1_ENABLE_1 (CHAN_BOND_SEQ_1_ENABLE_1), + .CHAN_BOND_SEQ_2_1_0 (CHAN_BOND_SEQ_2_1_0), + .CHAN_BOND_SEQ_2_1_1 (CHAN_BOND_SEQ_2_1_1), + .CHAN_BOND_SEQ_2_2_0 (CHAN_BOND_SEQ_2_2_0), + .CHAN_BOND_SEQ_2_2_1 (CHAN_BOND_SEQ_2_2_1), + .CHAN_BOND_SEQ_2_3_0 (CHAN_BOND_SEQ_2_3_0), + .CHAN_BOND_SEQ_2_3_1 (CHAN_BOND_SEQ_2_3_1), + .CHAN_BOND_SEQ_2_4_0 (CHAN_BOND_SEQ_2_4_0), + .CHAN_BOND_SEQ_2_4_1 (CHAN_BOND_SEQ_2_4_1), + .CHAN_BOND_SEQ_2_ENABLE_0 (CHAN_BOND_SEQ_2_ENABLE_0), + .CHAN_BOND_SEQ_2_ENABLE_1 (CHAN_BOND_SEQ_2_ENABLE_1), + .CHAN_BOND_SEQ_2_USE_0 (CHAN_BOND_SEQ_2_USE_0_BINARY), + .CHAN_BOND_SEQ_2_USE_1 (CHAN_BOND_SEQ_2_USE_1_BINARY), + .CHAN_BOND_SEQ_LEN_0 (CHAN_BOND_SEQ_LEN_0_BINARY), + .CHAN_BOND_SEQ_LEN_1 (CHAN_BOND_SEQ_LEN_1_BINARY), + .CLK25_DIVIDER (CLK25_DIVIDER_BINARY), + .CLKINDC_B (CLKINDC_B_BINARY), + .CLKRCV_TRST (CLKRCV_TRST_BINARY), + .CLK_CORRECT_USE_0 (CLK_CORRECT_USE_0_BINARY), + .CLK_CORRECT_USE_1 (CLK_CORRECT_USE_1_BINARY), + .CLK_COR_ADJ_LEN_0 (CLK_COR_ADJ_LEN_0_BINARY), + .CLK_COR_ADJ_LEN_1 (CLK_COR_ADJ_LEN_1_BINARY), + .CLK_COR_DET_LEN_0 (CLK_COR_DET_LEN_0_BINARY), + .CLK_COR_DET_LEN_1 (CLK_COR_DET_LEN_1_BINARY), + .CLK_COR_INSERT_IDLE_FLAG_0 (CLK_COR_INSERT_IDLE_FLAG_0_BINARY), + .CLK_COR_INSERT_IDLE_FLAG_1 (CLK_COR_INSERT_IDLE_FLAG_1_BINARY), + .CLK_COR_KEEP_IDLE_0 (CLK_COR_KEEP_IDLE_0_BINARY), + .CLK_COR_KEEP_IDLE_1 (CLK_COR_KEEP_IDLE_1_BINARY), + .CLK_COR_MAX_LAT_0 (CLK_COR_MAX_LAT_0_BINARY), + .CLK_COR_MAX_LAT_1 (CLK_COR_MAX_LAT_1_BINARY), + .CLK_COR_MIN_LAT_0 (CLK_COR_MIN_LAT_0_BINARY), + .CLK_COR_MIN_LAT_1 (CLK_COR_MIN_LAT_1_BINARY), + .CLK_COR_PRECEDENCE_0 (CLK_COR_PRECEDENCE_0_BINARY), + .CLK_COR_PRECEDENCE_1 (CLK_COR_PRECEDENCE_1_BINARY), + .CLK_COR_REPEAT_WAIT_0 (CLK_COR_REPEAT_WAIT_0_BINARY), + .CLK_COR_REPEAT_WAIT_1 (CLK_COR_REPEAT_WAIT_1_BINARY), + .CLK_COR_SEQ_1_1_0 (CLK_COR_SEQ_1_1_0), + .CLK_COR_SEQ_1_1_1 (CLK_COR_SEQ_1_1_1), + .CLK_COR_SEQ_1_2_0 (CLK_COR_SEQ_1_2_0), + .CLK_COR_SEQ_1_2_1 (CLK_COR_SEQ_1_2_1), + .CLK_COR_SEQ_1_3_0 (CLK_COR_SEQ_1_3_0), + .CLK_COR_SEQ_1_3_1 (CLK_COR_SEQ_1_3_1), + .CLK_COR_SEQ_1_4_0 (CLK_COR_SEQ_1_4_0), + .CLK_COR_SEQ_1_4_1 (CLK_COR_SEQ_1_4_1), + .CLK_COR_SEQ_1_ENABLE_0 (CLK_COR_SEQ_1_ENABLE_0), + .CLK_COR_SEQ_1_ENABLE_1 (CLK_COR_SEQ_1_ENABLE_1), + .CLK_COR_SEQ_2_1_0 (CLK_COR_SEQ_2_1_0), + .CLK_COR_SEQ_2_1_1 (CLK_COR_SEQ_2_1_1), + .CLK_COR_SEQ_2_2_0 (CLK_COR_SEQ_2_2_0), + .CLK_COR_SEQ_2_2_1 (CLK_COR_SEQ_2_2_1), + .CLK_COR_SEQ_2_3_0 (CLK_COR_SEQ_2_3_0), + .CLK_COR_SEQ_2_3_1 (CLK_COR_SEQ_2_3_1), + .CLK_COR_SEQ_2_4_0 (CLK_COR_SEQ_2_4_0), + .CLK_COR_SEQ_2_4_1 (CLK_COR_SEQ_2_4_1), + .CLK_COR_SEQ_2_ENABLE_0 (CLK_COR_SEQ_2_ENABLE_0), + .CLK_COR_SEQ_2_ENABLE_1 (CLK_COR_SEQ_2_ENABLE_1), + .CLK_COR_SEQ_2_USE_0 (CLK_COR_SEQ_2_USE_0_BINARY), + .CLK_COR_SEQ_2_USE_1 (CLK_COR_SEQ_2_USE_1_BINARY), + .CM_TRIM_0 (CM_TRIM_0), + .CM_TRIM_1 (CM_TRIM_1), + .COMMA_10B_ENABLE_0 (COMMA_10B_ENABLE_0), + .COMMA_10B_ENABLE_1 (COMMA_10B_ENABLE_1), + .COMMA_DOUBLE_0 (COMMA_DOUBLE_0_BINARY), + .COMMA_DOUBLE_1 (COMMA_DOUBLE_1_BINARY), + .COM_BURST_VAL_0 (COM_BURST_VAL_0), + .COM_BURST_VAL_1 (COM_BURST_VAL_1), + .DEC_MCOMMA_DETECT_0 (DEC_MCOMMA_DETECT_0_BINARY), + .DEC_MCOMMA_DETECT_1 (DEC_MCOMMA_DETECT_1_BINARY), + .DEC_PCOMMA_DETECT_0 (DEC_PCOMMA_DETECT_0_BINARY), + .DEC_PCOMMA_DETECT_1 (DEC_PCOMMA_DETECT_1_BINARY), + .DEC_VALID_COMMA_ONLY_0 (DEC_VALID_COMMA_ONLY_0_BINARY), + .DEC_VALID_COMMA_ONLY_1 (DEC_VALID_COMMA_ONLY_1_BINARY), + .DFE_CAL_TIME (DFE_CAL_TIME), + .DFE_CFG_0 (DFE_CFG_0), + .DFE_CFG_1 (DFE_CFG_1), + .GEARBOX_ENDEC_0 (GEARBOX_ENDEC_0), + .GEARBOX_ENDEC_1 (GEARBOX_ENDEC_1), + .MCOMMA_10B_VALUE_0 (MCOMMA_10B_VALUE_0), + .MCOMMA_10B_VALUE_1 (MCOMMA_10B_VALUE_1), + .MCOMMA_DETECT_0 (MCOMMA_DETECT_0_BINARY), + .MCOMMA_DETECT_1 (MCOMMA_DETECT_1_BINARY), + .OOBDETECT_THRESHOLD_0 (OOBDETECT_THRESHOLD_0_BINARY), + .OOBDETECT_THRESHOLD_1 (OOBDETECT_THRESHOLD_1_BINARY), + .OOB_CLK_DIVIDER (OOB_CLK_DIVIDER_BINARY), + .OVERSAMPLE_MODE (OVERSAMPLE_MODE_BINARY), + .PCI_EXPRESS_MODE_0 (PCI_EXPRESS_MODE_0_BINARY), + .PCI_EXPRESS_MODE_1 (PCI_EXPRESS_MODE_1_BINARY), + .PCOMMA_10B_VALUE_0 (PCOMMA_10B_VALUE_0), + .PCOMMA_10B_VALUE_1 (PCOMMA_10B_VALUE_1), + .PCOMMA_DETECT_0 (PCOMMA_DETECT_0_BINARY), + .PCOMMA_DETECT_1 (PCOMMA_DETECT_1_BINARY), + .PLL_COM_CFG (PLL_COM_CFG), + .PLL_CP_CFG (PLL_CP_CFG), + .PLL_DIVSEL_FB (PLL_DIVSEL_FB_BINARY), + .PLL_DIVSEL_REF (PLL_DIVSEL_REF_BINARY), + .PLL_FB_DCCEN (PLL_FB_DCCEN_BINARY), + .PLL_LKDET_CFG (PLL_LKDET_CFG), + .PLL_RXDIVSEL_OUT_0 (PLL_RXDIVSEL_OUT_0_BINARY), + .PLL_RXDIVSEL_OUT_1 (PLL_RXDIVSEL_OUT_1_BINARY), + .PLL_SATA_0 (PLL_SATA_0_BINARY), + .PLL_SATA_1 (PLL_SATA_1_BINARY), + .PLL_TDCC_CFG (PLL_TDCC_CFG), + .PLL_TXDIVSEL_OUT_0 (PLL_TXDIVSEL_OUT_0_BINARY), + .PLL_TXDIVSEL_OUT_1 (PLL_TXDIVSEL_OUT_1_BINARY), + .PMA_CDR_SCAN_0 (PMA_CDR_SCAN_0), + .PMA_CDR_SCAN_1 (PMA_CDR_SCAN_1), + .PMA_COM_CFG (PMA_COM_CFG), + .PMA_RXSYNC_CFG_0 (PMA_RXSYNC_CFG_0), + .PMA_RXSYNC_CFG_1 (PMA_RXSYNC_CFG_1), + .PMA_RX_CFG_0 (PMA_RX_CFG_0), + .PMA_RX_CFG_1 (PMA_RX_CFG_1), + .PMA_TX_CFG_0 (PMA_TX_CFG_0), + .PMA_TX_CFG_1 (PMA_TX_CFG_1), + .PRBS_ERR_THRESHOLD_0 (PRBS_ERR_THRESHOLD_0), + .PRBS_ERR_THRESHOLD_1 (PRBS_ERR_THRESHOLD_1), + .RCV_TERM_GND_0 (RCV_TERM_GND_0_BINARY), + .RCV_TERM_GND_1 (RCV_TERM_GND_1_BINARY), + .RCV_TERM_VTTRX_0 (RCV_TERM_VTTRX_0_BINARY), + .RCV_TERM_VTTRX_1 (RCV_TERM_VTTRX_1_BINARY), + .RXGEARBOX_USE_0 (RXGEARBOX_USE_0_BINARY), + .RXGEARBOX_USE_1 (RXGEARBOX_USE_1_BINARY), + .RX_BUFFER_USE_0 (RX_BUFFER_USE_0_BINARY), + .RX_BUFFER_USE_1 (RX_BUFFER_USE_1_BINARY), + .RX_DECODE_SEQ_MATCH_0 (RX_DECODE_SEQ_MATCH_0_BINARY), + .RX_DECODE_SEQ_MATCH_1 (RX_DECODE_SEQ_MATCH_1_BINARY), + .RX_EN_IDLE_HOLD_CDR (RX_EN_IDLE_HOLD_CDR_BINARY), + .RX_EN_IDLE_HOLD_DFE_0 (RX_EN_IDLE_HOLD_DFE_0_BINARY), + .RX_EN_IDLE_HOLD_DFE_1 (RX_EN_IDLE_HOLD_DFE_1_BINARY), + .RX_EN_IDLE_RESET_BUF_0 (RX_EN_IDLE_RESET_BUF_0_BINARY), + .RX_EN_IDLE_RESET_BUF_1 (RX_EN_IDLE_RESET_BUF_1_BINARY), + .RX_EN_IDLE_RESET_FR (RX_EN_IDLE_RESET_FR_BINARY), + .RX_EN_IDLE_RESET_PH (RX_EN_IDLE_RESET_PH_BINARY), + .RX_IDLE_HI_CNT_0 (RX_IDLE_HI_CNT_0), + .RX_IDLE_HI_CNT_1 (RX_IDLE_HI_CNT_1), + .RX_IDLE_LO_CNT_0 (RX_IDLE_LO_CNT_0), + .RX_IDLE_LO_CNT_1 (RX_IDLE_LO_CNT_1), + .RX_LOSS_OF_SYNC_FSM_0 (RX_LOSS_OF_SYNC_FSM_0_BINARY), + .RX_LOSS_OF_SYNC_FSM_1 (RX_LOSS_OF_SYNC_FSM_1_BINARY), + .RX_LOS_INVALID_INCR_0 (RX_LOS_INVALID_INCR_0_BINARY), + .RX_LOS_INVALID_INCR_1 (RX_LOS_INVALID_INCR_1_BINARY), + .RX_LOS_THRESHOLD_0 (RX_LOS_THRESHOLD_0_BINARY), + .RX_LOS_THRESHOLD_1 (RX_LOS_THRESHOLD_1_BINARY), + .RX_SLIDE_MODE_0 (RX_SLIDE_MODE_0_BINARY), + .RX_SLIDE_MODE_1 (RX_SLIDE_MODE_1_BINARY), + .RX_STATUS_FMT_0 (RX_STATUS_FMT_0_BINARY), + .RX_STATUS_FMT_1 (RX_STATUS_FMT_1_BINARY), + .RX_XCLK_SEL_0 (RX_XCLK_SEL_0_BINARY), + .RX_XCLK_SEL_1 (RX_XCLK_SEL_1_BINARY), + .SATA_BURST_VAL_0 (SATA_BURST_VAL_0), + .SATA_BURST_VAL_1 (SATA_BURST_VAL_1), + .SATA_IDLE_VAL_0 (SATA_IDLE_VAL_0), + .SATA_IDLE_VAL_1 (SATA_IDLE_VAL_1), + .SATA_MAX_BURST_0 (SATA_MAX_BURST_0_BINARY), + .SATA_MAX_BURST_1 (SATA_MAX_BURST_1_BINARY), + .SATA_MAX_INIT_0 (SATA_MAX_INIT_0_BINARY), + .SATA_MAX_INIT_1 (SATA_MAX_INIT_1_BINARY), + .SATA_MAX_WAKE_0 (SATA_MAX_WAKE_0_BINARY), + .SATA_MAX_WAKE_1 (SATA_MAX_WAKE_1_BINARY), + .SATA_MIN_BURST_0 (SATA_MIN_BURST_0_BINARY), + .SATA_MIN_BURST_1 (SATA_MIN_BURST_1_BINARY), + .SATA_MIN_INIT_0 (SATA_MIN_INIT_0_BINARY), + .SATA_MIN_INIT_1 (SATA_MIN_INIT_1_BINARY), + .SATA_MIN_WAKE_0 (SATA_MIN_WAKE_0_BINARY), + .SATA_MIN_WAKE_1 (SATA_MIN_WAKE_1_BINARY), + .SIM_GTXRESET_SPEEDUP (SIM_GTXRESET_SPEEDUP_BINARY), + .SIM_PLL_PERDIV2 (SIM_PLL_PERDIV2), + .SIM_RECEIVER_DETECT_PASS_0 (SIM_RECEIVER_DETECT_PASS_0_BINARY), + .SIM_RECEIVER_DETECT_PASS_1 (SIM_RECEIVER_DETECT_PASS_1_BINARY), + .STEPPING (1'b0), + .TERMINATION_CTRL (TERMINATION_CTRL), + .TERMINATION_IMP_0 (TERMINATION_IMP_0_BINARY), + .TERMINATION_IMP_1 (TERMINATION_IMP_1_BINARY), + .TERMINATION_OVRD (TERMINATION_OVRD_BINARY), + .TRANS_TIME_FROM_P2_0 (TRANS_TIME_FROM_P2_0), + .TRANS_TIME_FROM_P2_1 (TRANS_TIME_FROM_P2_1), + .TRANS_TIME_NON_P2_0 (TRANS_TIME_NON_P2_0), + .TRANS_TIME_NON_P2_1 (TRANS_TIME_NON_P2_1), + .TRANS_TIME_TO_P2_0 (TRANS_TIME_TO_P2_0), + .TRANS_TIME_TO_P2_1 (TRANS_TIME_TO_P2_1), + .TXGEARBOX_USE_0 (TXGEARBOX_USE_0_BINARY), + .TXGEARBOX_USE_1 (TXGEARBOX_USE_1_BINARY), + .TXRX_INVERT_0 (TXRX_INVERT_0), + .TXRX_INVERT_1 (TXRX_INVERT_1), + .TX_BUFFER_USE_0 (TX_BUFFER_USE_0_BINARY), + .TX_BUFFER_USE_1 (TX_BUFFER_USE_1_BINARY), + .TX_DETECT_RX_CFG_0 (TX_DETECT_RX_CFG_0), + .TX_DETECT_RX_CFG_1 (TX_DETECT_RX_CFG_1), + .TX_IDLE_DELAY_0 (TX_IDLE_DELAY_0), + .TX_IDLE_DELAY_1 (TX_IDLE_DELAY_1), + .TX_XCLK_SEL_0 (TX_XCLK_SEL_0_BINARY), + .TX_XCLK_SEL_1 (TX_XCLK_SEL_1_BINARY), + + .DFECLKDLYADJMONITOR0 (DFECLKDLYADJMONITOR0_delay), + .DFECLKDLYADJMONITOR1 (DFECLKDLYADJMONITOR1_delay), + .DFEEYEDACMONITOR0 (DFEEYEDACMONITOR0_delay), + .DFEEYEDACMONITOR1 (DFEEYEDACMONITOR1_delay), + .DFESENSCAL0 (DFESENSCAL0_delay), + .DFESENSCAL1 (DFESENSCAL1_delay), + .DFETAP1MONITOR0 (DFETAP1MONITOR0_delay), + .DFETAP1MONITOR1 (DFETAP1MONITOR1_delay), + .DFETAP2MONITOR0 (DFETAP2MONITOR0_delay), + .DFETAP2MONITOR1 (DFETAP2MONITOR1_delay), + .DFETAP3MONITOR0 (DFETAP3MONITOR0_delay), + .DFETAP3MONITOR1 (DFETAP3MONITOR1_delay), + .DFETAP4MONITOR0 (DFETAP4MONITOR0_delay), + .DFETAP4MONITOR1 (DFETAP4MONITOR1_delay), + .DO (DO_delay), + .DRDY (DRDY_delay), + .PHYSTATUS0 (PHYSTATUS0_delay), + .PHYSTATUS1 (PHYSTATUS1_delay), + .PLLLKDET (PLLLKDET_delay), + .REFCLKOUT (REFCLKOUT_delay), + .RESETDONE0 (RESETDONE0_delay), + .RESETDONE1 (RESETDONE1_delay), + .RXBUFSTATUS0 (RXBUFSTATUS0_delay), + .RXBUFSTATUS1 (RXBUFSTATUS1_delay), + .RXBYTEISALIGNED0 (RXBYTEISALIGNED0_delay), + .RXBYTEISALIGNED1 (RXBYTEISALIGNED1_delay), + .RXBYTEREALIGN0 (RXBYTEREALIGN0_delay), + .RXBYTEREALIGN1 (RXBYTEREALIGN1_delay), + .RXCHANBONDSEQ0 (RXCHANBONDSEQ0_delay), + .RXCHANBONDSEQ1 (RXCHANBONDSEQ1_delay), + .RXCHANISALIGNED0 (RXCHANISALIGNED0_delay), + .RXCHANISALIGNED1 (RXCHANISALIGNED1_delay), + .RXCHANREALIGN0 (RXCHANREALIGN0_delay), + .RXCHANREALIGN1 (RXCHANREALIGN1_delay), + .RXCHARISCOMMA0 (RXCHARISCOMMA0_delay), + .RXCHARISCOMMA1 (RXCHARISCOMMA1_delay), + .RXCHARISK0 (RXCHARISK0_delay), + .RXCHARISK1 (RXCHARISK1_delay), + .RXCHBONDO0 (RXCHBONDO0_delay), + .RXCHBONDO1 (RXCHBONDO1_delay), + .RXCLKCORCNT0 (RXCLKCORCNT0_delay), + .RXCLKCORCNT1 (RXCLKCORCNT1_delay), + .RXCOMMADET0 (RXCOMMADET0_delay), + .RXCOMMADET1 (RXCOMMADET1_delay), + .RXDATA0 (RXDATA0_delay), + .RXDATA1 (RXDATA1_delay), + .RXDATAVALID0 (RXDATAVALID0_delay), + .RXDATAVALID1 (RXDATAVALID1_delay), + .RXDISPERR0 (RXDISPERR0_delay), + .RXDISPERR1 (RXDISPERR1_delay), + .RXELECIDLE0 (RXELECIDLE0_delay), + .RXELECIDLE1 (RXELECIDLE1_delay), + .RXHEADER0 (RXHEADER0_delay), + .RXHEADER1 (RXHEADER1_delay), + .RXHEADERVALID0 (RXHEADERVALID0_delay), + .RXHEADERVALID1 (RXHEADERVALID1_delay), + .RXLOSSOFSYNC0 (RXLOSSOFSYNC0_delay), + .RXLOSSOFSYNC1 (RXLOSSOFSYNC1_delay), + .RXNOTINTABLE0 (RXNOTINTABLE0_delay), + .RXNOTINTABLE1 (RXNOTINTABLE1_delay), + .RXOVERSAMPLEERR0 (RXOVERSAMPLEERR0_delay), + .RXOVERSAMPLEERR1 (RXOVERSAMPLEERR1_delay), + .RXPRBSERR0 (RXPRBSERR0_delay), + .RXPRBSERR1 (RXPRBSERR1_delay), + .RXRECCLK0 (RXRECCLK0_delay), + .RXRECCLK1 (RXRECCLK1_delay), + .RXRUNDISP0 (RXRUNDISP0_delay), + .RXRUNDISP1 (RXRUNDISP1_delay), + .RXSTARTOFSEQ0 (RXSTARTOFSEQ0_delay), + .RXSTARTOFSEQ1 (RXSTARTOFSEQ1_delay), + .RXSTATUS0 (RXSTATUS0_delay), + .RXSTATUS1 (RXSTATUS1_delay), + .RXVALID0 (RXVALID0_delay), + .RXVALID1 (RXVALID1_delay), + .TXBUFSTATUS0 (TXBUFSTATUS0_delay), + .TXBUFSTATUS1 (TXBUFSTATUS1_delay), + .TXGEARBOXREADY0 (TXGEARBOXREADY0_delay), + .TXGEARBOXREADY1 (TXGEARBOXREADY1_delay), + .TXKERR0 (TXKERR0_delay), + .TXKERR1 (TXKERR1_delay), + .TXN0 (TXN0_delay), + .TXN1 (TXN1_delay), + .TXOUTCLK0 (TXOUTCLK0_delay), + .TXOUTCLK1 (TXOUTCLK1_delay), + .TXP0 (TXP0_delay), + .TXP1 (TXP1_delay), + .TXRUNDISP0 (TXRUNDISP0_delay), + .TXRUNDISP1 (TXRUNDISP1_delay), + + .CLKIN (CLKIN_delay), + .DADDR (DADDR_delay), + .DCLK (DCLK_delay), + .DEN (DEN_delay), + .DFECLKDLYADJ0 (DFECLKDLYADJ0_delay), + .DFECLKDLYADJ1 (DFECLKDLYADJ1_delay), + .DFETAP10 (DFETAP10_delay), + .DFETAP11 (DFETAP11_delay), + .DFETAP20 (DFETAP20_delay), + .DFETAP21 (DFETAP21_delay), + .DFETAP30 (DFETAP30_delay), + .DFETAP31 (DFETAP31_delay), + .DFETAP40 (DFETAP40_delay), + .DFETAP41 (DFETAP41_delay), + .DI (DI_delay), + .DWE (DWE_delay), + .GTXRESET (GTXRESET_delay), + .GTXTEST (GTXTEST_delay), + .INTDATAWIDTH (INTDATAWIDTH_delay), + .LOOPBACK0 (LOOPBACK0_delay), + .LOOPBACK1 (LOOPBACK1_delay), + .PLLLKDETEN (PLLLKDETEN_delay), + .PLLPOWERDOWN (PLLPOWERDOWN_delay), + .PRBSCNTRESET0 (PRBSCNTRESET0_delay), + .PRBSCNTRESET1 (PRBSCNTRESET1_delay), + .REFCLKPWRDNB (REFCLKPWRDNB_delay), + .RXBUFRESET0 (RXBUFRESET0_delay), + .RXBUFRESET1 (RXBUFRESET1_delay), + .RXCDRRESET0 (RXCDRRESET0_delay), + .RXCDRRESET1 (RXCDRRESET1_delay), + .RXCHBONDI0 (RXCHBONDI0_delay), + .RXCHBONDI1 (RXCHBONDI1_delay), + .RXCOMMADETUSE0 (RXCOMMADETUSE0_delay), + .RXCOMMADETUSE1 (RXCOMMADETUSE1_delay), + .RXDATAWIDTH0 (RXDATAWIDTH0_delay), + .RXDATAWIDTH1 (RXDATAWIDTH1_delay), + .RXDEC8B10BUSE0 (RXDEC8B10BUSE0_delay), + .RXDEC8B10BUSE1 (RXDEC8B10BUSE1_delay), + .RXENCHANSYNC0 (RXENCHANSYNC0_delay), + .RXENCHANSYNC1 (RXENCHANSYNC1_delay), + .RXENEQB0 (RXENEQB0_delay), + .RXENEQB1 (RXENEQB1_delay), + .RXENMCOMMAALIGN0 (RXENMCOMMAALIGN0_delay), + .RXENMCOMMAALIGN1 (RXENMCOMMAALIGN1_delay), + .RXENPCOMMAALIGN0 (RXENPCOMMAALIGN0_delay), + .RXENPCOMMAALIGN1 (RXENPCOMMAALIGN1_delay), + .RXENPMAPHASEALIGN0 (RXENPMAPHASEALIGN0_delay), + .RXENPMAPHASEALIGN1 (RXENPMAPHASEALIGN1_delay), + .RXENPRBSTST0 (RXENPRBSTST0_delay), + .RXENPRBSTST1 (RXENPRBSTST1_delay), + .RXENSAMPLEALIGN0 (RXENSAMPLEALIGN0_delay), + .RXENSAMPLEALIGN1 (RXENSAMPLEALIGN1_delay), + .RXEQMIX0 (RXEQMIX0_delay), + .RXEQMIX1 (RXEQMIX1_delay), + .RXEQPOLE0 (RXEQPOLE0_delay), + .RXEQPOLE1 (RXEQPOLE1_delay), + .RXGEARBOXSLIP0 (RXGEARBOXSLIP0_delay), + .RXGEARBOXSLIP1 (RXGEARBOXSLIP1_delay), + .RXN0 (RXN0_delay), + .RXN1 (RXN1_delay), + .RXP0 (RXP0_delay), + .RXP1 (RXP1_delay), + .RXPMASETPHASE0 (RXPMASETPHASE0_delay), + .RXPMASETPHASE1 (RXPMASETPHASE1_delay), + .RXPOLARITY0 (RXPOLARITY0_delay), + .RXPOLARITY1 (RXPOLARITY1_delay), + .RXPOWERDOWN0 (RXPOWERDOWN0_delay), + .RXPOWERDOWN1 (RXPOWERDOWN1_delay), + .RXRESET0 (RXRESET0_delay), + .RXRESET1 (RXRESET1_delay), + .RXSLIDE0 (RXSLIDE0_delay), + .RXSLIDE1 (RXSLIDE1_delay), + .RXUSRCLK0 (RXUSRCLK0_delay), + .RXUSRCLK1 (RXUSRCLK1_delay), + .RXUSRCLK20 (RXUSRCLK20_delay), + .RXUSRCLK21 (RXUSRCLK21_delay), + .TXBUFDIFFCTRL0 (TXBUFDIFFCTRL0_delay), + .TXBUFDIFFCTRL1 (TXBUFDIFFCTRL1_delay), + .TXBYPASS8B10B0 (TXBYPASS8B10B0_delay), + .TXBYPASS8B10B1 (TXBYPASS8B10B1_delay), + .TXCHARDISPMODE0 (TXCHARDISPMODE0_delay), + .TXCHARDISPMODE1 (TXCHARDISPMODE1_delay), + .TXCHARDISPVAL0 (TXCHARDISPVAL0_delay), + .TXCHARDISPVAL1 (TXCHARDISPVAL1_delay), + .TXCHARISK0 (TXCHARISK0_delay), + .TXCHARISK1 (TXCHARISK1_delay), + .TXCOMSTART0 (TXCOMSTART0_delay), + .TXCOMSTART1 (TXCOMSTART1_delay), + .TXCOMTYPE0 (TXCOMTYPE0_delay), + .TXCOMTYPE1 (TXCOMTYPE1_delay), + .TXDATA0 (TXDATA0_delay), + .TXDATA1 (TXDATA1_delay), + .TXDATAWIDTH0 (TXDATAWIDTH0_delay), + .TXDATAWIDTH1 (TXDATAWIDTH1_delay), + .TXDETECTRX0 (TXDETECTRX0_delay), + .TXDETECTRX1 (TXDETECTRX1_delay), + .TXDIFFCTRL0 (TXDIFFCTRL0_delay), + .TXDIFFCTRL1 (TXDIFFCTRL1_delay), + .TXELECIDLE0 (TXELECIDLE0_delay), + .TXELECIDLE1 (TXELECIDLE1_delay), + .TXENC8B10BUSE0 (TXENC8B10BUSE0_delay), + .TXENC8B10BUSE1 (TXENC8B10BUSE1_delay), + .TXENPMAPHASEALIGN0 (TXENPMAPHASEALIGN0_delay), + .TXENPMAPHASEALIGN1 (TXENPMAPHASEALIGN1_delay), + .TXENPRBSTST0 (TXENPRBSTST0_delay), + .TXENPRBSTST1 (TXENPRBSTST1_delay), + .TXHEADER0 (TXHEADER0_delay), + .TXHEADER1 (TXHEADER1_delay), + .TXINHIBIT0 (TXINHIBIT0_delay), + .TXINHIBIT1 (TXINHIBIT1_delay), + .TXPMASETPHASE0 (TXPMASETPHASE0_delay), + .TXPMASETPHASE1 (TXPMASETPHASE1_delay), + .TXPOLARITY0 (TXPOLARITY0_delay), + .TXPOLARITY1 (TXPOLARITY1_delay), + .TXPOWERDOWN0 (TXPOWERDOWN0_delay), + .TXPOWERDOWN1 (TXPOWERDOWN1_delay), + .TXPREEMPHASIS0 (TXPREEMPHASIS0_delay), + .TXPREEMPHASIS1 (TXPREEMPHASIS1_delay), + .TXRESET0 (TXRESET0_delay), + .TXRESET1 (TXRESET1_delay), + .TXSEQUENCE0 (TXSEQUENCE0_delay), + .TXSEQUENCE1 (TXSEQUENCE1_delay), + .TXSTARTSEQ0 (TXSTARTSEQ0_delay), + .TXSTARTSEQ1 (TXSTARTSEQ1_delay), + .TXUSRCLK0 (TXUSRCLK0_delay), + .TXUSRCLK1 (TXUSRCLK1_delay), + .TXUSRCLK20 (TXUSRCLK20_delay), + .TXUSRCLK21 (TXUSRCLK21_delay), + .GSR(GSR) + ); + +specify + (CLKIN => REFCLKOUT) = (100, 100); + (DCLK => DO) = (100, 100); + (DCLK => DRDY) = (100, 100); + (RXUSRCLK0 => RXCHBONDO0) = (100, 100); + (RXUSRCLK1 => RXCHBONDO1) = (100, 100); + (RXUSRCLK20 => DFECLKDLYADJMONITOR0) = (100, 100); + (RXUSRCLK20 => DFEEYEDACMONITOR0) = (100, 100); + (RXUSRCLK20 => DFESENSCAL0) = (100, 100); + (RXUSRCLK20 => DFETAP1MONITOR0) = (100, 100); + (RXUSRCLK20 => DFETAP2MONITOR0) = (100, 100); + (RXUSRCLK20 => DFETAP3MONITOR0) = (100, 100); + (RXUSRCLK20 => DFETAP4MONITOR0) = (100, 100); + (RXUSRCLK20 => PHYSTATUS0) = (100, 100); + (RXUSRCLK20 => RXBUFSTATUS0) = (100, 100); + (RXUSRCLK20 => RXBYTEISALIGNED0) = (100, 100); + (RXUSRCLK20 => RXBYTEREALIGN0) = (100, 100); + (RXUSRCLK20 => RXCHANBONDSEQ0) = (100, 100); + (RXUSRCLK20 => RXCHANISALIGNED0) = (100, 100); + (RXUSRCLK20 => RXCHANREALIGN0) = (100, 100); + (RXUSRCLK20 => RXCHARISCOMMA0) = (100, 100); + (RXUSRCLK20 => RXCHARISK0) = (100, 100); + (RXUSRCLK20 => RXCLKCORCNT0) = (100, 100); + (RXUSRCLK20 => RXCOMMADET0) = (100, 100); + (RXUSRCLK20 => RXDATA0) = (100, 100); + (RXUSRCLK20 => RXDATAVALID0) = (100, 100); + (RXUSRCLK20 => RXDISPERR0) = (100, 100); + (RXUSRCLK20 => RXHEADER0) = (100, 100); + (RXUSRCLK20 => RXHEADERVALID0) = (100, 100); + (RXUSRCLK20 => RXLOSSOFSYNC0) = (100, 100); + (RXUSRCLK20 => RXNOTINTABLE0) = (100, 100); + (RXUSRCLK20 => RXOVERSAMPLEERR0) = (100, 100); + (RXUSRCLK20 => RXPRBSERR0) = (100, 100); + (RXUSRCLK20 => RXRUNDISP0) = (100, 100); + (RXUSRCLK20 => RXSTARTOFSEQ0) = (100, 100); + (RXUSRCLK20 => RXSTATUS0) = (100, 100); + (RXUSRCLK20 => RXVALID0) = (100, 100); + (RXUSRCLK21 => DFECLKDLYADJMONITOR1) = (100, 100); + (RXUSRCLK21 => DFEEYEDACMONITOR1) = (100, 100); + (RXUSRCLK21 => DFESENSCAL1) = (100, 100); + (RXUSRCLK21 => DFETAP1MONITOR1) = (100, 100); + (RXUSRCLK21 => DFETAP2MONITOR1) = (100, 100); + (RXUSRCLK21 => DFETAP3MONITOR1) = (100, 100); + (RXUSRCLK21 => DFETAP4MONITOR1) = (100, 100); + (RXUSRCLK21 => PHYSTATUS1) = (100, 100); + (RXUSRCLK21 => RXBUFSTATUS1) = (100, 100); + (RXUSRCLK21 => RXBYTEISALIGNED1) = (100, 100); + (RXUSRCLK21 => RXBYTEREALIGN1) = (100, 100); + (RXUSRCLK21 => RXCHANBONDSEQ1) = (100, 100); + (RXUSRCLK21 => RXCHANISALIGNED1) = (100, 100); + (RXUSRCLK21 => RXCHANREALIGN1) = (100, 100); + (RXUSRCLK21 => RXCHARISCOMMA1) = (100, 100); + (RXUSRCLK21 => RXCHARISK1) = (100, 100); + (RXUSRCLK21 => RXCLKCORCNT1) = (100, 100); + (RXUSRCLK21 => RXCOMMADET1) = (100, 100); + (RXUSRCLK21 => RXDATA1) = (100, 100); + (RXUSRCLK21 => RXDATAVALID1) = (100, 100); + (RXUSRCLK21 => RXDISPERR1) = (100, 100); + (RXUSRCLK21 => RXHEADER1) = (100, 100); + (RXUSRCLK21 => RXHEADERVALID1) = (100, 100); + (RXUSRCLK21 => RXLOSSOFSYNC1) = (100, 100); + (RXUSRCLK21 => RXNOTINTABLE1) = (100, 100); + (RXUSRCLK21 => RXOVERSAMPLEERR1) = (100, 100); + (RXUSRCLK21 => RXPRBSERR1) = (100, 100); + (RXUSRCLK21 => RXRUNDISP1) = (100, 100); + (RXUSRCLK21 => RXSTARTOFSEQ1) = (100, 100); + (RXUSRCLK21 => RXSTATUS1) = (100, 100); + (RXUSRCLK21 => RXVALID1) = (100, 100); + (TXUSRCLK20 => TXBUFSTATUS0) = (100, 100); + (TXUSRCLK20 => TXGEARBOXREADY0) = (100, 100); + (TXUSRCLK20 => TXKERR0) = (100, 100); + (TXUSRCLK20 => TXRUNDISP0) = (100, 100); + (TXUSRCLK21 => TXBUFSTATUS1) = (100, 100); + (TXUSRCLK21 => TXGEARBOXREADY1) = (100, 100); + (TXUSRCLK21 => TXKERR1) = (100, 100); + (TXUSRCLK21 => TXRUNDISP1) = (100, 100); + specparam PATHPULSE$ = 0; +endspecify +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IBUF.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IBUF.v new file mode 100644 index 0000000..ee84324 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IBUF.v @@ -0,0 +1,87 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/IBUF.v,v 1.9 2009/08/21 23:55:43 harikr Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Input Buffer +// /___/ /\ Filename : IBUF.v +// \ \ / \ Timestamp : Thu Mar 25 16:42:23 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. +// 07/16/08 - Added IBUF_LOW_PWR attribute. +// 04/22/09 - CR 519127 - Changed IBUF_LOW_PWR default to TRUE. +// End Revision + +`timescale 1 ps / 1 ps + + +module IBUF (O, I); + + parameter CAPACITANCE = "DONT_CARE"; + parameter IBUF_DELAY_VALUE = "0"; + parameter IBUF_LOW_PWR = "TRUE"; + parameter IFD_DELAY_VALUE = "AUTO"; + parameter IOSTANDARD = "DEFAULT"; + + output O; + input I; + + buf B1 (O, I); + + + initial begin + + case (CAPACITANCE) + + "LOW", "NORMAL", "DONT_CARE" : ; + default : begin + $display("Attribute Syntax Error : The attribute CAPACITANCE on IBUF instance %m is set to %s. Legal values for this attribute are DONT_CARE, LOW or NORMAL.", CAPACITANCE); + $finish; + end + + endcase + + + case (IBUF_DELAY_VALUE) + + "0", "1", "2", "3", "4", "5", "6", "7", "8", "9", "10", "11", "12", "13", "14", "15", "16" : ; + default : begin + $display("Attribute Syntax Error : The attribute IBUF_DELAY_VALUE on IBUF instance %m is set to %s. Legal values for this attribute are 0, 1, 2, ... or 16.", IBUF_DELAY_VALUE); + $finish; + end + + endcase + + case (IBUF_LOW_PWR) + + "FALSE", "TRUE" : ; + default : begin + $display("Attribute Syntax Error : The attribute IBUF_LOW_PWR on IBUF instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", IBUF_LOW_PWR); + $finish; + end + + endcase + + + case (IFD_DELAY_VALUE) + + "AUTO", "0", "1", "2", "3", "4", "5", "6", "7", "8" : ; + default : begin + $display("Attribute Syntax Error : The attribute IFD_DELAY_VALUE on IBUF instance %m is set to %s. Legal values for this attribute are AUTO, 0, 1, 2, ... or 8.", IFD_DELAY_VALUE); + $finish; + end + + endcase + + end + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IBUFDS.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IBUFDS.v new file mode 100644 index 0000000..034685e --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IBUFDS.v @@ -0,0 +1,108 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/IBUFDS.v,v 1.10 2009/08/21 23:55:43 harikr Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Differential Signaling Input Buffer +// /___/ /\ Filename : IBUFDS.v +// \ \ / \ Timestamp : Thu Mar 25 16:42:23 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 07/19/06 - Add else to handle x case for o_out (CR 234718). +// 05/23/07 - Changed timescale to 1 ps / 1 ps. +// 07/16/08 - Added IBUF_LOW_PWR attribute. +// 03/19/09 - CR 511590 - Added Z condition handling +// 04/22/09 - CR 519127 - Changed IBUF_LOW_PWR default to TRUE. +// End Revision + +`timescale 1 ps / 1 ps + + +module IBUFDS (O, I, IB); + + parameter CAPACITANCE = "DONT_CARE"; + parameter DIFF_TERM = "FALSE"; + parameter IBUF_DELAY_VALUE = "0"; + parameter IBUF_LOW_PWR = "TRUE"; + parameter IFD_DELAY_VALUE = "AUTO"; + parameter IOSTANDARD = "DEFAULT"; + + output O; + input I, IB; + + reg o_out; + + buf b_0 (O, o_out); + + initial begin + + case (CAPACITANCE) + + "LOW", "NORMAL", "DONT_CARE" : ; + default : begin + $display("Attribute Syntax Error : The attribute CAPACITANCE on IBUFDS instance %m is set to %s. Legal values for this attribute are DONT_CARE, LOW or NORMAL.", CAPACITANCE); + $finish; + end + + endcase + + case (DIFF_TERM) + + "TRUE", "FALSE" : ; + default : begin + $display("Attribute Syntax Error : The attribute DIFF_TERM on IBUFDS instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", DIFF_TERM); + $finish; + end + + endcase // case(DIFF_TERM) + + + case (IBUF_DELAY_VALUE) + + "0", "1", "2", "3", "4", "5", "6", "7", "8", "9", "10", "11", "12", "13", "14", "15", "16" : ; + default : begin + $display("Attribute Syntax Error : The attribute IBUF_DELAY_VALUE on IBUFDS instance %m is set to %s. Legal values for this attribute are 0, 1, 2, ... or 16.", IBUF_DELAY_VALUE); + $finish; + end + + endcase + + case (IBUF_LOW_PWR) + + "FALSE", "TRUE" : ; + default : begin + $display("Attribute Syntax Error : The attribute IBUF_LOW_PWR on IBUF instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", IBUF_LOW_PWR); + $finish; + end + + endcase + + case (IFD_DELAY_VALUE) + + "AUTO", "0", "1", "2", "3", "4", "5", "6", "7", "8" : ; + default : begin + $display("Attribute Syntax Error : The attribute IFD_DELAY_VALUE on IBUFDS instance %m is set to %s. Legal values for this attribute are AUTO, 0, 1, 2, ... or 8.", IFD_DELAY_VALUE); + $finish; + end + + endcase + + end + + always @(I or IB) + if (I == 1'b1 && IB == 1'b0) + o_out = I; + else if (I == 1'b0 && IB == 1'b1) + o_out = I; + else if (I == 1'bx || I == 1'bz || IB == 1'bx || IB == 1'bz) + o_out = 1'bx; + + +endmodule diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IBUFDS_BLVDS_25.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IBUFDS_BLVDS_25.v new file mode 100644 index 0000000..5366d0e --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IBUFDS_BLVDS_25.v @@ -0,0 +1,46 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/IBUFDS_BLVDS_25.v,v 1.7 2008/05/15 21:26:52 fphillip Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Differential Signaling Input Buffer with BLVDS_25 I/O Standard +// /___/ /\ Filename : IBUFDS_BLVDS_25.v +// \ \ / \ Timestamp : Thu Mar 25 16:42:23 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. +// 05/13/08 - CR 458290 -- Added else condition to handle x case. +// End Revision + +`timescale 1 ps / 1 ps + + +module IBUFDS_BLVDS_25 (O, I, IB); + + output O; + + input I, IB; + + reg o_out; + + buf b_0 (O, o_out); + + always @(I or IB) begin + if (I == 1'b1 && IB == 1'b0) + o_out <= I; + else if (I == 1'b0 && IB == 1'b1) + o_out <= I; + else if (I == 1'bx || IB == 1'bx) + o_out <= 1'bx; + + end + + +endmodule diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IBUFDS_DIFF_OUT.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IBUFDS_DIFF_OUT.v new file mode 100644 index 0000000..33f9df7 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IBUFDS_DIFF_OUT.v @@ -0,0 +1,76 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/IBUFDS_DIFF_OUT.v,v 1.9 2009/08/21 23:55:43 harikr Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Differential Signaling Input Buffer with Differential Outputs +// /___/ /\ Filename : IBUFDS_DIFF_OUT.v +// \ \ / \ Timestamp : Thu Mar 25 16:42:23 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. +// 05/13/08 - CR 458290 -- Added else condition to handle x case. +// 02/10/09 - CR 430124 -- Added attribute DIFF_TERM. +// 06/02/09 - CR 523083 -- Added attribute IBUF_LOW_PWR. +// End Revision + +`timescale 1 ps / 1 ps + + +module IBUFDS_DIFF_OUT (O, OB, I, IB); + + parameter DIFF_TERM = "FALSE"; + parameter IBUF_LOW_PWR = "TRUE"; + parameter IOSTANDARD = "LVDS_25"; + + output O, OB; + + input I, IB; + + reg o_out; + + buf B0 (O, o_out); + not B1 (OB, o_out); + + initial begin + case (DIFF_TERM) + + "TRUE", "FALSE" : ; + default : begin + $display("Attribute Syntax Error : The attribute DIFF_TERM on IBUFDS_DIFF_OUT instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", DIFF_TERM); + $finish; + end + + endcase // case(DIFF_TERM) + + case (IBUF_LOW_PWR) + + "FALSE", "TRUE" : ; + default : begin + $display("Attribute Syntax Error : The attribute IBUF_LOW_PWR on IBUFDS_DIFF_OUT instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", IBUF_LOW_PWR); + $finish; + end + + endcase + + end + + + always @(I or IB) begin + if (I == 1'b1 && IB == 1'b0) + o_out <= I; + else if (I == 1'b0 && IB == 1'b1) + o_out <= I; + else if (I == 1'bx || IB == 1'bx) + o_out <= 1'bx; + end + + +endmodule diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IBUFDS_DLY_ADJ.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IBUFDS_DLY_ADJ.v new file mode 100644 index 0000000..ec6deb8 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IBUFDS_DLY_ADJ.v @@ -0,0 +1,148 @@ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Dynamically Adjustable Differential Input Delay Buffer +// /___/ /\ Filename : IBUFDS_DLY_ADJ.v +// \ \ / \ Timestamp : Fri Jun 3 16:44:07 PST 2005 +// \___\/\___\ +// +// Revision: +// 06/03/05 - Initial version. +// 05/29/07 - Added wire declaration for internal signals +// 08/08/07 - CR 439320 -- Simprim fix -- Added attributes SIM_DELAY0, ... SIM_DELAY16 to fix timing issues +// 09/11/07 - CR 447604 -- When S[2:0]=0, it should correlate to 1 tap +// 03/28/08 - CR 469907 -- Corrected bus path of S[2:0] in the specify block elaboration +// End Revision + +`timescale 1 ps / 1 ps + +module IBUFDS_DLY_ADJ (O, I, IB, S); + + output O; + + input I, IB; + input [2:0] S; + + parameter DELAY_OFFSET = "OFF"; + parameter DIFF_TERM = "FALSE"; + parameter IOSTANDARD = "DEFAULT"; + +// xilinx_internal_parameter on + // WARNING !!!: This model may not work properly if the + // following parameter is changed. + localparam SIM_TAPDELAY_VALUE = 200; + localparam SPECTRUM_OFFSET_DELAY = 1600; + +// xilinx_internal_parameter off + + + reg o_out; + + reg i_int; + + wire [2:0] s_in; + wire i_in; + wire ib_in; + + integer delay_count; + + wire delay_chain_0, delay_chain_1, delay_chain_2, delay_chain_3, + delay_chain_4, delay_chain_5, delay_chain_6, delay_chain_7; + + buf buf_o (O, o_out); + + buf buf_i (i_in, I); + buf buf_ib (ib_in, IB); + buf buf_s[2:0] (s_in, S); + + time INITIAL_DELAY = 0; + time FINAL_DELAY = 0; + + + initial begin + case (DIFF_TERM) + + "TRUE", "FALSE" : ; + default : begin + $display("Attribute Syntax Error : The attribute DIFF_TERM on IBUFDS instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", DIFF_TERM); + $finish; + end + endcase // case(DIFF_TERM) + + if (DELAY_OFFSET != "ON" && DELAY_OFFSET != "OFF") begin + + $display("Attribute Syntax Error : The attribute DELAY_OFFSET on IBUFDS_DLY_ADJ instance %m is set to %s. Legal values for this attribute are ON or OFF", DELAY_OFFSET); + $finish; + + end + + if(DELAY_OFFSET == "ON") +// CR 447604 +// INITIAL_DELAY = SPECTRUM_OFFSET_DELAY; + INITIAL_DELAY = SPECTRUM_OFFSET_DELAY + SIM_TAPDELAY_VALUE; + else +// INITIAL_DELAY = 0; + INITIAL_DELAY = SIM_TAPDELAY_VALUE; + + end // initial begin + + +//------------------------------------------------------------ +//---------------------- delay the chain -------------------- +//------------------------------------------------------------ + always @(i_in or ib_in) begin + if (i_in == 1'b1 && ib_in == 1'b0) + i_int <= i_in; + else if (i_in == 1'b0 && ib_in == 1'b1) + i_int <= i_in; + end + +//------------------------------------------------------------ +//----------------------- S input ---------------------------- +//------------------------------------------------------------ + always@s_in +// #FINAL_DELAY = s_in * SIM_TAP_DELAY_VALUE + INITIAL_DELAY; + delay_count = s_in; + +//------------------------------------------------------------ +//---------------------- delay the chain -------------------- +//------------------------------------------------------------ + assign #INITIAL_DELAY delay_chain_0 = i_int; + assign #SIM_TAPDELAY_VALUE delay_chain_1 = delay_chain_0; + assign #SIM_TAPDELAY_VALUE delay_chain_2 = delay_chain_1; + assign #SIM_TAPDELAY_VALUE delay_chain_3 = delay_chain_2; + assign #SIM_TAPDELAY_VALUE delay_chain_4 = delay_chain_3; + assign #SIM_TAPDELAY_VALUE delay_chain_5 = delay_chain_4; + assign #SIM_TAPDELAY_VALUE delay_chain_6 = delay_chain_5; + assign #SIM_TAPDELAY_VALUE delay_chain_7 = delay_chain_6; + +//------------------------------------------------------------ +//---------------------- Assign to output ------------------- +//------------------------------------------------------------ + always @(delay_count) begin + + case (delay_count) + 0: assign o_out = delay_chain_0; + 1: assign o_out = delay_chain_1; + 2: assign o_out = delay_chain_2; + 3: assign o_out = delay_chain_3; + 4: assign o_out = delay_chain_4; + 5: assign o_out = delay_chain_5; + 6: assign o_out = delay_chain_6; + 7: assign o_out = delay_chain_7; + default: + assign o_out = delay_chain_0; + + endcase + end // always @ (s_in) + + + +endmodule // IBUFDS_DLY_ADJ + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IBUFDS_GTHE1.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IBUFDS_GTHE1.v new file mode 100644 index 0000000..579b4c9 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IBUFDS_GTHE1.v @@ -0,0 +1,54 @@ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2007 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Differential Signaling Input Buffer for GTs +// /___/ /\ Filename : IBUFDS_GTHE1.v +// \ \ / \ Timestamp : Tue Jun 2 10:50:23 PDT 2009 +// \___\/\___\ +// +// Revision: +// 06/02/09 - Initial version. +// End Revision + +`timescale 1 ps / 1 ps + +module IBUFDS_GTHE1 (O, I, IB); + + + + output O; + + input I; + input IB; + +// Output signals + reg o_out; + + + + tri0 GSR = glbl.GSR; + + always @(I or IB) + if (I == 1'b1 && IB == 1'b0) + o_out = I; + else if (I == 1'b0 && IB == 1'b1) + o_out = I; + else if (I == 1'bx || I == 1'bz || IB == 1'bx || IB == 1'bz) + o_out = 1'bx; + + + + + assign O = o_out; + + specify + specparam PATHPULSE$ = 0; + endspecify + +endmodule // IBUFDS_GTHE1 diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IBUFDS_GTXE1.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IBUFDS_GTXE1.v new file mode 100644 index 0000000..8ba7b44 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IBUFDS_GTXE1.v @@ -0,0 +1,136 @@ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2007 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Differential Signaling Input Buffer for GTs +// /___/ /\ Filename : IBUFDS_GTXE1.v +// \ \ / \ Timestamp : Wed Sep 3 23:37:39 PDT 2008 +// \___\/\___\ +// +// Revision: +// 09/03/08 - Initial version. +// End Revision + +`timescale 1 ps / 1 ps + +module IBUFDS_GTXE1 (O, ODIV2, CEB, I, IB); + + + parameter CLKCM_CFG = "TRUE"; + parameter CLKRCV_TRST = "TRUE"; + parameter [9:0] REFCLKOUT_DLY = 10'b0000000000; + + output O; + output ODIV2; + + input CEB; + input I; + input IB; + +// Output signals + reg O_out=0, ODIV2_out=0; + + +// Counters and Flags + reg [2:0] ce_count = 1; + reg [2:0] edge_count = 0; + + reg allEqual; + +// Attribute settings + +// Other signals + reg clkcm_cfg_int = 0; + reg clkrcv_trst_int = 0; + + reg attr_err_flag = 0; + tri0 GSR = glbl.GSR; + + + initial begin + allEqual = 0; + +//------------------------------------------------- +//----- CLKCM_CFG check +//------------------------------------------------- + case (CLKCM_CFG) + + "FALSE" : clkcm_cfg_int <= 1'b0; + "TRUE" : clkcm_cfg_int <= 1'b1; + default : begin + $display("Attribute Syntax Error : The attribute CLKCM_CFG on IBUFDS_GTXE1 instance %m is set to %s. Legal values for this attribute are FALSE or TRUE", CLKCM_CFG); + $finish; + end + + endcase // case(CLKCM_CFG) + +//------------------------------------------------- +//----- CLKRCV_TRST check +//------------------------------------------------- + case (CLKRCV_TRST) + + "FALSE" : clkrcv_trst_int <= 1'b0; + "TRUE" : clkrcv_trst_int <= 1'b1; + default : begin + $display("Attribute Syntax Error : The attribute CLKRCV_TRST on IBUFDS_GTXE1 instance %m is set to %s. Legal values for this attribute are FALSE or TRUE", CLKRCV_TRST); + $finish; + end + + endcase // case(CLKRCV_TRST) + + end // initial begin + + +//----------------------------------------------------------------------------------- +// ===================== +// Count the rising edges of the clk +// ===================== + always @(posedge I) begin + if(allEqual) + edge_count <= 3'b000; + else + if (CEB == 1'b0) + edge_count <= edge_count + 1; + end + +// Generate synchronous reset after DIVIDE number of counts + always @(edge_count) + if (edge_count == ce_count) + allEqual = 1; + else + allEqual = 0; + +// ===================== +// Generate ODIV2 +// ===================== + always @(posedge I) + ODIV2_out <= allEqual; + +// ===================== +// Generate O +// ===================== + always @(I) + O_out <= I & ~CEB; + + + + + assign O = O_out; + assign ODIV2 = ODIV2_out; + + specify + ( I => O) = (100, 100); + ( I => ODIV2) = (100, 100); + ( IB => O) = (100, 100); + ( IB => ODIV2) = (100, 100); + + specparam PATHPULSE$ = 0; + endspecify + +endmodule // IBUFDS_GTXE1 + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IBUFDS_LDT_25.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IBUFDS_LDT_25.v new file mode 100644 index 0000000..6060cc8 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IBUFDS_LDT_25.v @@ -0,0 +1,48 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/IBUFDS_LDT_25.v,v 1.7 2008/05/15 21:26:52 fphillip Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Differential Signaling Input Buffer with LDT_25 I/O Standard +// /___/ /\ Filename : IBUFDS_LDT_25.v +// \ \ / \ Timestamp : Thu Mar 25 16:42:23 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. +// 05/13/08 - CR 458290 -- Added else condition to handle x case. +// End Revision + + +`timescale 1 ps / 1 ps + + +module IBUFDS_LDT_25 (O, I, IB); + + output O; + + input I, IB; + + reg o_out; + + buf b_0 (O, o_out); + + always @(I or IB) begin + if (I == 1'b1 && IB == 1'b0) + o_out <= I; + else if (I == 1'b0 && IB == 1'b1) + o_out <= I; + else if (I == 1'bx || IB == 1'bx) + o_out <= 1'bx; + end + + +endmodule + + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IBUFDS_LVDSEXT_25.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IBUFDS_LVDSEXT_25.v new file mode 100644 index 0000000..6aae71f --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IBUFDS_LVDSEXT_25.v @@ -0,0 +1,45 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/IBUFDS_LVDSEXT_25.v,v 1.7 2008/05/15 21:26:52 fphillip Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Differential Signaling Input Buffer with LVDSEXT_25 I/O Standard +// /___/ /\ Filename : IBUFDS_LVDSEXT_25.v +// \ \ / \ Timestamp : Thu Mar 25 16:42:23 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. +// 05/13/08 - CR 458290 -- Added else condition to handle x case. +// End Revision + +`timescale 1 ps / 1 ps + + +module IBUFDS_LVDSEXT_25 (O, I, IB); + + output O; + + input I, IB; + + reg o_out; + + buf b_0 (O, o_out); + + always @(I or IB) begin + if (I == 1'b1 && IB == 1'b0) + o_out <= I; + else if (I == 1'b0 && IB == 1'b1) + o_out <= I; + else if (I == 1'bx || IB == 1'bx) + o_out <= 1'bx; + end + + +endmodule diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IBUFDS_LVDSEXT_25_DCI.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IBUFDS_LVDSEXT_25_DCI.v new file mode 100644 index 0000000..44e3608 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IBUFDS_LVDSEXT_25_DCI.v @@ -0,0 +1,45 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/IBUFDS_LVDSEXT_25_DCI.v,v 1.7 2008/05/15 21:26:52 fphillip Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Differential Signaling Input Buffer with LVDSEXT_25_DCI I/O Standard +// /___/ /\ Filename : IBUFDS_LVDSEXT_25_DCI.v +// \ \ / \ Timestamp : Thu Mar 25 16:42:23 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. +// 05/13/08 - CR 458290 -- Added else condition to handle x case. +// End Revision + +`timescale 1 ps / 1 ps + + +module IBUFDS_LVDSEXT_25_DCI (O, I, IB); + + output O; + + input I, IB; + + reg o_out; + + buf b_0 (O, o_out); + + always @(I or IB) begin + if (I == 1'b1 && IB == 1'b0) + o_out <= I; + else if (I == 1'b0 && IB == 1'b1) + o_out <= I; + else if (I == 1'bx || IB == 1'bx) + o_out <= 1'bx; + end + + +endmodule diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IBUFDS_LVDSEXT_33.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IBUFDS_LVDSEXT_33.v new file mode 100644 index 0000000..e5b1151 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IBUFDS_LVDSEXT_33.v @@ -0,0 +1,45 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/IBUFDS_LVDSEXT_33.v,v 1.7 2008/05/15 21:26:52 fphillip Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Differential Signaling Input Buffer with LVDSEXT_33 I/O Standard +// /___/ /\ Filename : IBUFDS_LVDSEXT_33.v +// \ \ / \ Timestamp : Thu Mar 25 16:42:24 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. +// 05/13/08 - CR 458290 -- Added else condition to handle x case. +// End Revision + +`timescale 1 ps / 1 ps + + +module IBUFDS_LVDSEXT_33 (O, I, IB); + + output O; + + input I, IB; + + reg o_out; + + buf b_0 (O, o_out); + + always @(I or IB) begin + if (I == 1'b1 && IB == 1'b0) + o_out <= I; + else if (I == 1'b0 && IB == 1'b1) + o_out <= I; + else if (I == 1'bx || IB == 1'bx) + o_out <= 1'bx; + end + + +endmodule diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IBUFDS_LVDSEXT_33_DCI.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IBUFDS_LVDSEXT_33_DCI.v new file mode 100644 index 0000000..5a81160 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IBUFDS_LVDSEXT_33_DCI.v @@ -0,0 +1,45 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/IBUFDS_LVDSEXT_33_DCI.v,v 1.7 2008/05/15 21:26:52 fphillip Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Differential Signaling Input Buffer with LVDSEXT_33_DCI I/O Standard +// /___/ /\ Filename : IBUFDS_LVDSEXT_33_DCI.v +// \ \ / \ Timestamp : Thu Mar 25 16:42:24 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. +// 05/13/08 - CR 458290 -- Added else condition to handle x case. +// End Revision + +`timescale 1 ps / 1 ps + + +module IBUFDS_LVDSEXT_33_DCI (O, I, IB); + + output O; + + input I, IB; + + reg o_out; + + buf b_0 (O, o_out); + + always @(I or IB) begin + if (I == 1'b1 && IB == 1'b0) + o_out <= I; + else if (I == 1'b0 && IB == 1'b1) + o_out <= I; + else if (I == 1'bx || IB == 1'bx) + o_out <= 1'bx; + end + + +endmodule diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IBUFDS_LVDS_25.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IBUFDS_LVDS_25.v new file mode 100644 index 0000000..9516f6d --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IBUFDS_LVDS_25.v @@ -0,0 +1,45 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/IBUFDS_LVDS_25.v,v 1.7 2008/05/15 21:26:52 fphillip Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Differential Signaling Input Buffer with LVDS_25 I/O Standard +// /___/ /\ Filename : IBUFDS_LVDS_25.v +// \ \ / \ Timestamp : Thu Mar 25 16:42:24 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. +// 05/13/08 - CR 458290 -- Added else condition to handle x case. +// End Revision + +`timescale 1 ps / 1 ps + + +module IBUFDS_LVDS_25 (O, I, IB); + + output O; + + input I, IB; + + reg o_out; + + buf b_0 (O, o_out); + + always @(I or IB) begin + if (I == 1'b1 && IB == 1'b0) + o_out <= I; + else if (I == 1'b0 && IB == 1'b1) + o_out <= I; + else if (I == 1'bx || IB == 1'bx) + o_out <= 1'bx; + end + + +endmodule diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IBUFDS_LVDS_25_DCI.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IBUFDS_LVDS_25_DCI.v new file mode 100644 index 0000000..2cc5846 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IBUFDS_LVDS_25_DCI.v @@ -0,0 +1,47 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/IBUFDS_LVDS_25_DCI.v,v 1.7 2008/05/15 21:26:52 fphillip Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Differential Signaling Input Buffer with LVDS_25_DCI I/O Standard +// /___/ /\ Filename : IBUFDS_LVDS_25_DCI.v +// \ \ / \ Timestamp : Thu Mar 25 16:42:24 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. +// 05/13/08 - CR 458290 -- Added else condition to handle x case. +// End Revision + +`timescale 1 ps / 1 ps + + +module IBUFDS_LVDS_25_DCI (O, I, IB); + + output O; + + input I, IB; + + reg o_out; + + buf b_0 (O, o_out); + + always @(I or IB) begin + if (I == 1'b1 && IB == 1'b0) + o_out <= I; + else if (I == 1'b0 && IB == 1'b1) + o_out <= I; + else if (I == 1'bx || IB == 1'bx) + o_out <= 1'bx; + end + + +endmodule + + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IBUFDS_LVDS_33.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IBUFDS_LVDS_33.v new file mode 100644 index 0000000..6077a2f --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IBUFDS_LVDS_33.v @@ -0,0 +1,45 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/IBUFDS_LVDS_33.v,v 1.7 2008/05/15 21:26:52 fphillip Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Differential Signaling Input Buffer with LVDS_33 I/O Standard +// /___/ /\ Filename : IBUFDS_LVDS_33.v +// \ \ / \ Timestamp : Thu Mar 25 16:42:24 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. +// 05/13/08 - CR 458290 -- Added else condition to handle x case. +// End Revision + +`timescale 1 ps / 1 ps + + +module IBUFDS_LVDS_33 (O, I, IB); + + output O; + + input I, IB; + + reg o_out; + + buf b_0 (O, o_out); + + always @(I or IB) begin + if (I == 1'b1 && IB == 1'b0) + o_out <= I; + else if (I == 1'b0 && IB == 1'b1) + o_out <= I; + else if (I == 1'bx || IB == 1'bx) + o_out <= 1'bx; + end + + +endmodule diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IBUFDS_LVDS_33_DCI.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IBUFDS_LVDS_33_DCI.v new file mode 100644 index 0000000..0d1d441 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IBUFDS_LVDS_33_DCI.v @@ -0,0 +1,45 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/IBUFDS_LVDS_33_DCI.v,v 1.7 2008/05/15 21:26:52 fphillip Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Differential Signaling Input Buffer with LVDS_33_DCI I/O Standard +// /___/ /\ Filename : IBUFDS_LVDS_33_DCI.v +// \ \ / \ Timestamp : Thu Mar 25 16:42:24 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. +// 05/13/08 - CR 458290 -- Added else condition to handle x case. +// End Revision + +`timescale 1 ps / 1 ps + + +module IBUFDS_LVDS_33_DCI (O, I, IB); + + output O; + + input I, IB; + + reg o_out; + + buf b_0 (O, o_out); + + always @(I or IB) begin + if (I == 1'b1 && IB == 1'b0) + o_out <= I; + else if (I == 1'b0 && IB == 1'b1) + o_out <= I; + else if (I == 1'bx || IB == 1'bx) + o_out <= 1'bx; + end + + +endmodule diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IBUFDS_LVPECL_25.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IBUFDS_LVPECL_25.v new file mode 100644 index 0000000..4025daf --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IBUFDS_LVPECL_25.v @@ -0,0 +1,45 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/IBUFDS_LVPECL_25.v,v 1.7 2008/05/15 21:26:52 fphillip Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Differential Signaling Input Buffer with LVPECL_25 I/O Standard +// /___/ /\ Filename : IBUFDS_LVPECL_25.v +// \ \ / \ Timestamp : Thu Mar 25 16:42:24 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. +// 05/13/08 - CR 458290 -- Added else condition to handle x case. +// End Revision + +`timescale 1 ps / 1 ps + + +module IBUFDS_LVPECL_25 (O, I, IB); + + output O; + + input I, IB; + + reg o_out; + + buf b_0 (O, o_out); + + always @(I or IB) begin + if (I == 1'b1 && IB == 1'b0) + o_out <= I; + else if (I == 1'b0 && IB == 1'b1) + o_out <= I; + else if (I == 1'bx || IB == 1'bx) + o_out <= 1'bx; + end + + +endmodule diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IBUFDS_LVPECL_33.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IBUFDS_LVPECL_33.v new file mode 100644 index 0000000..85a1c88 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IBUFDS_LVPECL_33.v @@ -0,0 +1,47 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/IBUFDS_LVPECL_33.v,v 1.7 2008/05/15 21:26:52 fphillip Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Differential Signaling Input Buffer with LVPECL_33 I/O Standard +// /___/ /\ Filename : IBUFDS_LVPECL_33.v +// \ \ / \ Timestamp : Thu Mar 25 16:42:24 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. +// 05/13/08 - CR 458290 -- Added else condition to handle x case. +// End Revision + +`timescale 1 ps / 1 ps + + +module IBUFDS_LVPECL_33 (O, I, IB); + + output O; + + input I, IB; + + reg o_out; + + buf b_0 (O, o_out); + + always @(I or IB) begin + if (I == 1'b1 && IB == 1'b0) + o_out <= I; + else if (I == 1'b0 && IB == 1'b1) + o_out <= I; + else if (I == 1'bx || IB == 1'bx) + o_out <= 1'bx; + end + + +endmodule + + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IBUFDS_ULVDS_25.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IBUFDS_ULVDS_25.v new file mode 100644 index 0000000..7404cef --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IBUFDS_ULVDS_25.v @@ -0,0 +1,45 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/IBUFDS_ULVDS_25.v,v 1.7 2008/05/15 21:26:52 fphillip Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Differential Signaling Input Buffer with ULVDS_25 I/O Standard +// /___/ /\ Filename : IBUFDS_ULVDS_25.v +// \ \ / \ Timestamp : Thu Mar 25 16:42:24 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. +// 05/13/08 - CR 458290 -- Added else condition to handle x case. +// End Revision + +`timescale 1 ps / 1 ps + + +module IBUFDS_ULVDS_25 (O, I, IB); + + output O; + + input I, IB; + + reg o_out; + + buf b_0 (O, o_out); + + always @(I or IB) begin + if (I == 1'b1 && IB == 1'b0) + o_out <= I; + else if (I == 1'b0 && IB == 1'b1) + o_out <= I; + else if (I == 1'bx || IB == 1'bx) + o_out <= 1'bx; + end + + +endmodule diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IBUFG.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IBUFG.v new file mode 100644 index 0000000..0ad8fb0 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IBUFG.v @@ -0,0 +1,75 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/IBUFG.v,v 1.9 2009/08/21 23:55:43 harikr Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Input Clock Buffer +// /___/ /\ Filename : IBUFG.v +// \ \ / \ Timestamp : Thu Mar 25 16:42:24 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. +// 07/16/08 - Added IBUF_LOW_PWR attribute. +// 04/22/09 - CR 519127 - Changed IBUF_LOW_PWR default to TRUE. +// End Revision + + +`timescale 1 ps / 1 ps + + +module IBUFG (O, I); + + parameter CAPACITANCE = "DONT_CARE"; + parameter IBUF_DELAY_VALUE = "0"; + parameter IBUF_LOW_PWR = "TRUE"; + parameter IOSTANDARD = "DEFAULT"; + + output O; + input I; + + buf B1 (O, I); + + initial begin + + case (CAPACITANCE) + + "LOW", "NORMAL", "DONT_CARE" : ; + default : begin + $display("Attribute Syntax Error : The attribute CAPACITANCE on IBUFG instance %m is set to %s. Legal values for this attribute are DONT_CARE, LOW or NORMAL.", CAPACITANCE); + $finish; + end + + endcase + + + case (IBUF_DELAY_VALUE) + + "0", "1", "2", "3", "4", "5", "6", "7", "8", "9", "10", "11", "12", "13", "14", "15", "16" : ; + default : begin + $display("Attribute Syntax Error : The attribute IBUF_DELAY_VALUE on IBUFG instance %m is set to %s. Legal values for this attribute are 0, 1, 2, ... or 16.", IBUF_DELAY_VALUE); + $finish; + end + + endcase + + case (IBUF_LOW_PWR) + + "FALSE", "TRUE" : ; + default : begin + $display("Attribute Syntax Error : The attribute IBUF_LOW_PWR on IBUF instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", IBUF_LOW_PWR); + $finish; + end + + endcase + + + end // initial begin + +endmodule diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IBUFGDS.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IBUFGDS.v new file mode 100644 index 0000000..fca7fe4 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IBUFGDS.v @@ -0,0 +1,100 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/IBUFGDS.v,v 1.10 2009/08/21 23:55:43 harikr Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Differential Signaling Input Clock Buffer +// /___/ /\ Filename : IBUFGDS.v +// \ \ / \ Timestamp : Thu Mar 25 16:42:24 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. +// 07/26/07 - Add else to handle x case for o_out (CR 424214). +// 07/16/08 - Added IBUF_LOW_PWR attribute. +// 03/19/09 - CR 511590 - Added Z condition handling. +// 04/22/09 - CR 519127 - Changed IBUF_LOW_PWR default to TRUE. +// End Revision + + +`timescale 1 ps / 1 ps + + +module IBUFGDS (O, I, IB); + + parameter CAPACITANCE = "DONT_CARE"; + parameter DIFF_TERM = "FALSE"; + parameter IBUF_DELAY_VALUE = "0"; + parameter IBUF_LOW_PWR = "TRUE"; + parameter IOSTANDARD = "DEFAULT"; + + output O; + input I, IB; + + reg o_out; + + buf b_0 (O, o_out); + + initial begin + + case (CAPACITANCE) + + "LOW", "NORMAL", "DONT_CARE" : ; + default : begin + $display("Attribute Syntax Error : The attribute CAPACITANCE on IBUFGDS instance %m is set to %s. Legal values for this attribute are DONT_CARE, LOW or NORMAL.", CAPACITANCE); + $finish; + end + + endcase + + + case (DIFF_TERM) + + "TRUE", "FALSE" : ; + default : begin + $display("Attribute Syntax Error : The attribute DIFF_TERM on IBUFGDS instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", DIFF_TERM); + $finish; + end + + endcase + + + case (IBUF_DELAY_VALUE) + + "0", "1", "2", "3", "4", "5", "6", "7", "8", "9", "10", "11", "12", "13", "14", "15", "16" : ; + default : begin + $display("Attribute Syntax Error : The attribute IBUF_DELAY_VALUE on IBUFGDS instance %m is set to %s. Legal values for this attribute are 0, 1, 2, ... or 16.", IBUF_DELAY_VALUE); + $finish; + end + + endcase + + case (IBUF_LOW_PWR) + + "FALSE", "TRUE" : ; + default : begin + $display("Attribute Syntax Error : The attribute IBUF_LOW_PWR on IBUF instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", IBUF_LOW_PWR); + $finish; + end + + endcase + + + end + + always @(I or IB) begin + if (I == 1'b1 && IB == 1'b0) + o_out <= I; + else if (I == 1'b0 && IB == 1'b1) + o_out <= I; + else if (I == 1'bx || I == 1'bz || IB == 1'bx || IB == 1'bz) + o_out <= 1'bx; + end + +endmodule diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IBUFGDS_BLVDS_25.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IBUFGDS_BLVDS_25.v new file mode 100644 index 0000000..5bb92b1 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IBUFGDS_BLVDS_25.v @@ -0,0 +1,43 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/IBUFGDS_BLVDS_25.v,v 1.6 2007/05/23 21:43:34 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Differential Signaling Input Clock Buffer with BLVDS_25 I/O Standard +// /___/ /\ Filename : IBUFGDS_BLVDS_25.v +// \ \ / \ Timestamp : Thu Mar 25 16:42:25 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. + +`timescale 1 ps / 1 ps + + +module IBUFGDS_BLVDS_25 (O, I, IB); + + output O; + + input I, IB; + + reg o_out; + + buf b_0 (O, o_out); + + always @(I or IB) begin + if (I == 1'b1 && IB == 1'b0) + o_out <= I; + else if (I == 1'b0 && IB == 1'b1) + o_out <= I; + end + + +endmodule + + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IBUFGDS_DIFF_OUT.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IBUFGDS_DIFF_OUT.v new file mode 100644 index 0000000..4468ee4 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IBUFGDS_DIFF_OUT.v @@ -0,0 +1,73 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/IBUFGDS_DIFF_OUT.v,v 1.8 2009/08/21 23:55:43 harikr Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Differential Signaling Input Clock Buffer with Differential Outputs +// /___/ /\ Filename : IBUFGDS_DIFF_OUT.v +// \ \ / \ Timestamp : Thu Mar 25 16:42:25 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. +// 02/10/09 - CR 430124 -- Added attribute DIFF_TERM. +// 06/02/09 - CR 523083 -- Added attribute IBUF_LOW_PWR. +// End Revision + + +`timescale 1 ps / 1 ps + + +module IBUFGDS_DIFF_OUT (O, OB, I, IB); + + parameter DIFF_TERM = "FALSE"; + parameter IBUF_LOW_PWR = "TRUE"; + parameter IOSTANDARD = "LVDS_25"; + + output O, OB; + + input I, IB; + + reg o_out; + + buf B0 (O, o_out); + not B1 (OB, o_out); + + initial begin + case (DIFF_TERM) + + "TRUE", "FALSE" : ; + default : begin + $display("Attribute Syntax Error : The attribute DIFF_TERM on IBUFGDS_DIFF_OUT instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", DIFF_TERM); + $finish; + end + + endcase // case(DIFF_TERM) + + case (IBUF_LOW_PWR) + + "FALSE", "TRUE" : ; + default : begin + $display("Attribute Syntax Error : The attribute IBUF_LOW_PWR on IBUFGDS_DIFF_OUT instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", IBUF_LOW_PWR); + $finish; + end + + endcase + + end + + always @(I or IB) begin + if (I == 1'b1 && IB == 1'b0) + o_out <= I; + else if (I == 1'b0 && IB == 1'b1) + o_out <= I; + end + + +endmodule diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IBUFGDS_LDT_25.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IBUFGDS_LDT_25.v new file mode 100644 index 0000000..ec30f2a --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IBUFGDS_LDT_25.v @@ -0,0 +1,43 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/IBUFGDS_LDT_25.v,v 1.6 2007/05/23 21:43:34 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Differential Signaling Input Clock Buffer with LDT_25 I/O Standard +// /___/ /\ Filename : IBUFGDS_LDT_25.v +// \ \ / \ Timestamp : Thu Mar 25 16:42:25 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. + +`timescale 1 ps / 1 ps + + +module IBUFGDS_LDT_25 (O, I, IB); + + output O; + + input I, IB; + + reg o_out; + + buf b_0 (O, o_out); + + always @(I or IB) begin + if (I == 1'b1 && IB == 1'b0) + o_out <= I; + else if (I == 1'b0 && IB == 1'b1) + o_out <= I; + end + + +endmodule + + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IBUFGDS_LVDSEXT_25.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IBUFGDS_LVDSEXT_25.v new file mode 100644 index 0000000..0c4711f --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IBUFGDS_LVDSEXT_25.v @@ -0,0 +1,43 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/IBUFGDS_LVDSEXT_25.v,v 1.6 2007/05/23 21:43:34 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Differential Signaling Input Clock Buffer with LVDSEXT_25 I/O Standard +// /___/ /\ Filename : IBUFGDS_LVDSEXT_25.v +// \ \ / \ Timestamp : Thu Mar 25 16:42:25 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. + +`timescale 1 ps / 1 ps + + +module IBUFGDS_LVDSEXT_25 (O, I, IB); + + output O; + + input I, IB; + + reg o_out; + + buf b_0 (O, o_out); + + always @(I or IB) begin + if (I == 1'b1 && IB == 1'b0) + o_out <= I; + else if (I == 1'b0 && IB == 1'b1) + o_out <= I; + end + + +endmodule + + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IBUFGDS_LVDSEXT_25_DCI.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IBUFGDS_LVDSEXT_25_DCI.v new file mode 100644 index 0000000..eeb1f30 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IBUFGDS_LVDSEXT_25_DCI.v @@ -0,0 +1,43 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/IBUFGDS_LVDSEXT_25_DCI.v,v 1.6 2007/05/23 21:43:34 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Differential Signaling Input Clock Buffer with LVDSEXT_25_DCI I/O Standard +// /___/ /\ Filename : IBUFGDS_LVDSEXT_25_DCI.v +// \ \ / \ Timestamp : Thu Mar 25 16:42:25 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. + +`timescale 1 ps / 1 ps + + +module IBUFGDS_LVDSEXT_25_DCI (O, I, IB); + + output O; + + input I, IB; + + reg o_out; + + buf b_0 (O, o_out); + + always @(I or IB) begin + if (I == 1'b1 && IB == 1'b0) + o_out <= I; + else if (I == 1'b0 && IB == 1'b1) + o_out <= I; + end + + +endmodule + + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IBUFGDS_LVDSEXT_33.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IBUFGDS_LVDSEXT_33.v new file mode 100644 index 0000000..8dc918a --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IBUFGDS_LVDSEXT_33.v @@ -0,0 +1,43 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/IBUFGDS_LVDSEXT_33.v,v 1.6 2007/05/23 21:43:34 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Differential Signaling Input Clock Buffer with LVDSEXT_33 I/O Standard +// /___/ /\ Filename : IBUFGDS_LVDSEXT_33.v +// \ \ / \ Timestamp : Thu Mar 25 16:42:25 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. + +`timescale 1 ps / 1 ps + + +module IBUFGDS_LVDSEXT_33 (O, I, IB); + + output O; + + input I, IB; + + reg o_out; + + buf b_0 (O, o_out); + + always @(I or IB) begin + if (I == 1'b1 && IB == 1'b0) + o_out <= I; + else if (I == 1'b0 && IB == 1'b1) + o_out <= I; + end + + +endmodule + + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IBUFGDS_LVDSEXT_33_DCI.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IBUFGDS_LVDSEXT_33_DCI.v new file mode 100644 index 0000000..4786029 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IBUFGDS_LVDSEXT_33_DCI.v @@ -0,0 +1,43 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/IBUFGDS_LVDSEXT_33_DCI.v,v 1.6 2007/05/23 21:43:34 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Differential Signaling Input Clock Buffer with LVDSEXT_33_DCI I/O Standard +// /___/ /\ Filename : IBUFGDS_LVDSEXT_33_DCI.v +// \ \ / \ Timestamp : Thu Mar 25 16:42:25 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. + +`timescale 1 ps / 1 ps + + +module IBUFGDS_LVDSEXT_33_DCI (O, I, IB); + + output O; + + input I, IB; + + reg o_out; + + buf b_0 (O, o_out); + + always @(I or IB) begin + if (I == 1'b1 && IB == 1'b0) + o_out <= I; + else if (I == 1'b0 && IB == 1'b1) + o_out <= I; + end + + +endmodule + + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IBUFGDS_LVDS_25.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IBUFGDS_LVDS_25.v new file mode 100644 index 0000000..28b7354 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IBUFGDS_LVDS_25.v @@ -0,0 +1,43 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/IBUFGDS_LVDS_25.v,v 1.6 2007/05/23 21:43:34 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Differential Signaling Input Clock Buffer with LVDS_25 I/O Standard +// /___/ /\ Filename : IBUFGDS_LVDS_25.v +// \ \ / \ Timestamp : Thu Mar 25 16:42:25 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. + +`timescale 1 ps / 1 ps + + +module IBUFGDS_LVDS_25 (O, I, IB); + + output O; + + input I, IB; + + reg o_out; + + buf b_0 (O, o_out); + + always @(I or IB) begin + if (I == 1'b1 && IB == 1'b0) + o_out <= I; + else if (I == 1'b0 && IB == 1'b1) + o_out <= I; + end + + +endmodule + + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IBUFGDS_LVDS_25_DCI.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IBUFGDS_LVDS_25_DCI.v new file mode 100644 index 0000000..5db9abe --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IBUFGDS_LVDS_25_DCI.v @@ -0,0 +1,43 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/IBUFGDS_LVDS_25_DCI.v,v 1.6 2007/05/23 21:43:34 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Differential Signaling Input Clock Buffer with LVDS_25_DCI I/O Standard +// /___/ /\ Filename : IBUFGDS_LVDS_25_DCI.v +// \ \ / \ Timestamp : Thu Mar 25 16:42:25 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. + +`timescale 1 ps / 1 ps + + +module IBUFGDS_LVDS_25_DCI (O, I, IB); + + output O; + + input I, IB; + + reg o_out; + + buf b_0 (O, o_out); + + always @(I or IB) begin + if (I == 1'b1 && IB == 1'b0) + o_out <= I; + else if (I == 1'b0 && IB == 1'b1) + o_out <= I; + end + + +endmodule + + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IBUFGDS_LVDS_33.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IBUFGDS_LVDS_33.v new file mode 100644 index 0000000..8b8c771 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IBUFGDS_LVDS_33.v @@ -0,0 +1,43 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/IBUFGDS_LVDS_33.v,v 1.6 2007/05/23 21:43:34 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Differential Signaling Input Clock Buffer with LVDS_33 I/O Standard +// /___/ /\ Filename : IBUFGDS_LVDS_33.v +// \ \ / \ Timestamp : Thu Mar 25 16:42:25 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. + +`timescale 1 ps / 1 ps + + +module IBUFGDS_LVDS_33 (O, I, IB); + + output O; + + input I, IB; + + reg o_out; + + buf b_0 (O, o_out); + + always @(I or IB) begin + if (I == 1'b1 && IB == 1'b0) + o_out <= I; + else if (I == 1'b0 && IB == 1'b1) + o_out <= I; + end + + +endmodule + + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IBUFGDS_LVDS_33_DCI.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IBUFGDS_LVDS_33_DCI.v new file mode 100644 index 0000000..d24b816 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IBUFGDS_LVDS_33_DCI.v @@ -0,0 +1,43 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/IBUFGDS_LVDS_33_DCI.v,v 1.6 2007/05/23 21:43:34 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Differential Signaling Input Clock Buffer with LVDS_33_DCI I/O Standard +// /___/ /\ Filename : IBUFGDS_LVDS_33_DCI.v +// \ \ / \ Timestamp : Thu Mar 25 16:42:26 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. + +`timescale 1 ps / 1 ps + + +module IBUFGDS_LVDS_33_DCI (O, I, IB); + + output O; + + input I, IB; + + reg o_out; + + buf b_0 (O, o_out); + + always @(I or IB) begin + if (I == 1'b1 && IB == 1'b0) + o_out <= I; + else if (I == 1'b0 && IB == 1'b1) + o_out <= I; + end + + +endmodule + + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IBUFGDS_LVPECL_25.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IBUFGDS_LVPECL_25.v new file mode 100644 index 0000000..5a78c00 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IBUFGDS_LVPECL_25.v @@ -0,0 +1,43 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/IBUFGDS_LVPECL_25.v,v 1.6 2007/05/23 21:43:34 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Differential Signaling Input Clock Buffer with LVPECL_25 I/O Standard +// /___/ /\ Filename : IBUFGDS_LVPECL_25.v +// \ \ / \ Timestamp : Thu Mar 25 16:42:26 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. + +`timescale 1 ps / 1 ps + + +module IBUFGDS_LVPECL_25 (O, I, IB); + + output O; + + input I, IB; + + reg o_out; + + buf b_0 (O, o_out); + + always @(I or IB) begin + if (I == 1'b1 && IB == 1'b0) + o_out <= I; + else if (I == 1'b0 && IB == 1'b1) + o_out <= I; + end + + +endmodule + + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IBUFGDS_LVPECL_33.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IBUFGDS_LVPECL_33.v new file mode 100644 index 0000000..7441d84 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IBUFGDS_LVPECL_33.v @@ -0,0 +1,43 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/IBUFGDS_LVPECL_33.v,v 1.6 2007/05/23 21:43:34 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Differential Signaling Input Clock Buffer with LVPECL_33 I/O Standard +// /___/ /\ Filename : IBUFGDS_LVPECL_33.v +// \ \ / \ Timestamp : Thu Mar 25 16:42:26 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. + +`timescale 1 ps / 1 ps + + +module IBUFGDS_LVPECL_33 (O, I, IB); + + output O; + + input I, IB; + + reg o_out; + + buf b_0 (O, o_out); + + always @(I or IB) begin + if (I == 1'b1 && IB == 1'b0) + o_out <= I; + else if (I == 1'b0 && IB == 1'b1) + o_out <= I; + end + + +endmodule + + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IBUFGDS_ULVDS_25.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IBUFGDS_ULVDS_25.v new file mode 100644 index 0000000..38bd2ee --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IBUFGDS_ULVDS_25.v @@ -0,0 +1,43 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/IBUFGDS_ULVDS_25.v,v 1.6 2007/05/23 21:43:34 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Differential Signaling Input Clock Buffer with ULVDS_25 I/O Standard +// /___/ /\ Filename : IBUFGDS_ULVDS_25.v +// \ \ / \ Timestamp : Thu Mar 25 16:42:26 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. + +`timescale 1 ps / 1 ps + + +module IBUFGDS_ULVDS_25 (O, I, IB); + + output O; + + input I, IB; + + reg o_out; + + buf b_0 (O, o_out); + + always @(I or IB) begin + if (I == 1'b1 && IB == 1'b0) + o_out <= I; + else if (I == 1'b0 && IB == 1'b1) + o_out <= I; + end + + +endmodule + + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IBUFG_AGP.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IBUFG_AGP.v new file mode 100644 index 0000000..03fb596 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IBUFG_AGP.v @@ -0,0 +1,33 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/IBUFG_AGP.v,v 1.6 2007/05/23 21:43:33 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Input Clock Buffer with AGP I/O Standard +// /___/ /\ Filename : IBUFG_AGP.v +// \ \ / \ Timestamp : Thu Mar 25 16:42:26 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. + +`timescale 1 ps / 1 ps + + +module IBUFG_AGP (O, I); + + output O; + + input I; + + buf B1 (O, I); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IBUFG_CTT.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IBUFG_CTT.v new file mode 100644 index 0000000..ea6ca75 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IBUFG_CTT.v @@ -0,0 +1,33 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/IBUFG_CTT.v,v 1.6 2007/05/23 21:43:33 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Input Clock Buffer with CTT I/O Standard +// /___/ /\ Filename : IBUFG_CTT.v +// \ \ / \ Timestamp : Thu Mar 25 16:42:26 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. + +`timescale 1 ps / 1 ps + + +module IBUFG_CTT (O, I); + + output O; + + input I; + + buf B1 (O, I); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IBUFG_GTL.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IBUFG_GTL.v new file mode 100644 index 0000000..7c4ed5a --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IBUFG_GTL.v @@ -0,0 +1,33 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/IBUFG_GTL.v,v 1.6 2007/05/23 21:43:34 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Input Clock Buffer with GTL I/O Standard +// /___/ /\ Filename : IBUFG_GTL.v +// \ \ / \ Timestamp : Thu Mar 25 16:42:26 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. + +`timescale 1 ps / 1 ps + + +module IBUFG_GTL (O, I); + + output O; + + input I; + + buf B1 (O, I); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IBUFG_GTLP.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IBUFG_GTLP.v new file mode 100644 index 0000000..6a0f604 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IBUFG_GTLP.v @@ -0,0 +1,33 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/IBUFG_GTLP.v,v 1.6 2007/05/23 21:43:34 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Input Clock Buffer with GTLP I/O Standard +// /___/ /\ Filename : IBUFG_GTLP.v +// \ \ / \ Timestamp : Thu Mar 25 16:42:26 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. + +`timescale 1 ps / 1 ps + + +module IBUFG_GTLP (O, I); + + output O; + + input I; + + buf B1 (O, I); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IBUFG_GTLP_DCI.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IBUFG_GTLP_DCI.v new file mode 100644 index 0000000..348bff0 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IBUFG_GTLP_DCI.v @@ -0,0 +1,33 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/IBUFG_GTLP_DCI.v,v 1.6 2007/05/23 21:43:34 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Input Clock Buffer with GTLP_DCI I/O Standard +// /___/ /\ Filename : IBUFG_GTLP_DCI.v +// \ \ / \ Timestamp : Thu Mar 25 16:42:26 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. + +`timescale 1 ps / 1 ps + + +module IBUFG_GTLP_DCI (O, I); + + output O; + + input I; + + buf B1 (O, I); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IBUFG_GTL_DCI.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IBUFG_GTL_DCI.v new file mode 100644 index 0000000..3e9d75d --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IBUFG_GTL_DCI.v @@ -0,0 +1,33 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/IBUFG_GTL_DCI.v,v 1.6 2007/05/23 21:43:34 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Input Clock Buffer with GTL_DCI I/O Standard +// /___/ /\ Filename : IBUFG_GTL_DCI.v +// \ \ / \ Timestamp : Thu Mar 25 16:42:26 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. + +`timescale 1 ps / 1 ps + + +module IBUFG_GTL_DCI (O, I); + + output O; + + input I; + + buf B1 (O, I); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IBUFG_HSTL_I.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IBUFG_HSTL_I.v new file mode 100644 index 0000000..8dccd56 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IBUFG_HSTL_I.v @@ -0,0 +1,33 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/IBUFG_HSTL_I.v,v 1.6 2007/05/23 21:43:34 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Input Clock Buffer with HSTL_I I/O Standard +// /___/ /\ Filename : IBUFG_HSTL_I.v +// \ \ / \ Timestamp : Thu Mar 25 16:42:27 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. + +`timescale 1 ps / 1 ps + + +module IBUFG_HSTL_I (O, I); + + output O; + + input I; + + buf B1 (O, I); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IBUFG_HSTL_II.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IBUFG_HSTL_II.v new file mode 100644 index 0000000..1c01a78 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IBUFG_HSTL_II.v @@ -0,0 +1,33 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/IBUFG_HSTL_II.v,v 1.6 2007/05/23 21:43:34 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Input Clock Buffer with HSTL_II I/O Standard +// /___/ /\ Filename : IBUFG_HSTL_II.v +// \ \ / \ Timestamp : Thu Mar 25 16:42:27 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. + +`timescale 1 ps / 1 ps + + +module IBUFG_HSTL_II (O, I); + + output O; + + input I; + + buf B1 (O, I); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IBUFG_HSTL_III.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IBUFG_HSTL_III.v new file mode 100644 index 0000000..d0010e3 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IBUFG_HSTL_III.v @@ -0,0 +1,33 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/IBUFG_HSTL_III.v,v 1.6 2007/05/23 21:43:34 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Input Clock Buffer with HSTL_III I/O Standard +// /___/ /\ Filename : IBUFG_HSTL_III.v +// \ \ / \ Timestamp : Thu Mar 25 16:42:27 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. + +`timescale 1 ps / 1 ps + + +module IBUFG_HSTL_III (O, I); + + output O; + + input I; + + buf B1 (O, I); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IBUFG_HSTL_III_18.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IBUFG_HSTL_III_18.v new file mode 100644 index 0000000..182db99 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IBUFG_HSTL_III_18.v @@ -0,0 +1,33 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/IBUFG_HSTL_III_18.v,v 1.6 2007/05/23 21:43:34 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Input Clock Buffer with HSTL_III_18 I/O Standard +// /___/ /\ Filename : IBUFG_HSTL_III_18.v +// \ \ / \ Timestamp : Thu Mar 25 16:42:27 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. + +`timescale 1 ps / 1 ps + + +module IBUFG_HSTL_III_18 (O, I); + + output O; + + input I; + + buf B1 (O, I); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IBUFG_HSTL_III_DCI.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IBUFG_HSTL_III_DCI.v new file mode 100644 index 0000000..74f68ad --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IBUFG_HSTL_III_DCI.v @@ -0,0 +1,33 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/IBUFG_HSTL_III_DCI.v,v 1.6 2007/05/23 21:43:34 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Input Clock Buffer with HSTL_III_DCI I/O Standard +// /___/ /\ Filename : IBUFG_HSTL_III_DCI.v +// \ \ / \ Timestamp : Thu Mar 25 16:42:27 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. + +`timescale 1 ps / 1 ps + + +module IBUFG_HSTL_III_DCI (O, I); + + output O; + + input I; + + buf B1 (O, I); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IBUFG_HSTL_III_DCI_18.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IBUFG_HSTL_III_DCI_18.v new file mode 100644 index 0000000..797c212 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IBUFG_HSTL_III_DCI_18.v @@ -0,0 +1,33 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/IBUFG_HSTL_III_DCI_18.v,v 1.6 2007/05/23 21:43:34 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Input Clock Buffer with HSTL_III_DCI_18 I/O Standard +// /___/ /\ Filename : IBUFG_HSTL_III_DCI_18.v +// \ \ / \ Timestamp : Thu Mar 25 16:42:27 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. + +`timescale 1 ps / 1 ps + + +module IBUFG_HSTL_III_DCI_18 (O, I); + + output O; + + input I; + + buf B1 (O, I); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IBUFG_HSTL_II_18.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IBUFG_HSTL_II_18.v new file mode 100644 index 0000000..cb053c1 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IBUFG_HSTL_II_18.v @@ -0,0 +1,33 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/IBUFG_HSTL_II_18.v,v 1.6 2007/05/23 21:43:34 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Input Clock Buffer with HSTL_II_18 I/O Standard +// /___/ /\ Filename : IBUFG_HSTL_II_18.v +// \ \ / \ Timestamp : Thu Mar 25 16:42:27 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. + +`timescale 1 ps / 1 ps + + +module IBUFG_HSTL_II_18 (O, I); + + output O; + + input I; + + buf B1 (O, I); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IBUFG_HSTL_II_DCI.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IBUFG_HSTL_II_DCI.v new file mode 100644 index 0000000..17658d7 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IBUFG_HSTL_II_DCI.v @@ -0,0 +1,33 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/IBUFG_HSTL_II_DCI.v,v 1.6 2007/05/23 21:43:34 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Input Clock Buffer with HSTL_II_DCI I/O Standard +// /___/ /\ Filename : IBUFG_HSTL_II_DCI.v +// \ \ / \ Timestamp : Thu Mar 25 16:42:27 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. + +`timescale 1 ps / 1 ps + + +module IBUFG_HSTL_II_DCI (O, I); + + output O; + + input I; + + buf B1 (O, I); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IBUFG_HSTL_II_DCI_18.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IBUFG_HSTL_II_DCI_18.v new file mode 100644 index 0000000..3a694ac --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IBUFG_HSTL_II_DCI_18.v @@ -0,0 +1,33 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/IBUFG_HSTL_II_DCI_18.v,v 1.6 2007/05/23 21:43:34 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Input Clock Buffer with HSTL_II_DCI_18 I/O Standard +// /___/ /\ Filename : IBUFG_HSTL_II_DCI_18.v +// \ \ / \ Timestamp : Thu Mar 25 16:42:27 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. + +`timescale 1 ps / 1 ps + + +module IBUFG_HSTL_II_DCI_18 (O, I); + + output O; + + input I; + + buf B1 (O, I); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IBUFG_HSTL_IV.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IBUFG_HSTL_IV.v new file mode 100644 index 0000000..61c9746 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IBUFG_HSTL_IV.v @@ -0,0 +1,33 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/IBUFG_HSTL_IV.v,v 1.6 2007/05/23 21:43:34 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Input Clock Buffer with HSTL_IV I/O Standard +// /___/ /\ Filename : IBUFG_HSTL_IV.v +// \ \ / \ Timestamp : Thu Mar 25 16:42:27 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. + +`timescale 1 ps / 1 ps + + +module IBUFG_HSTL_IV (O, I); + + output O; + + input I; + + buf B1 (O, I); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IBUFG_HSTL_IV_18.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IBUFG_HSTL_IV_18.v new file mode 100644 index 0000000..80d0fea --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IBUFG_HSTL_IV_18.v @@ -0,0 +1,33 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/IBUFG_HSTL_IV_18.v,v 1.6 2007/05/23 21:43:34 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Input Clock Buffer with HSTL_IV_18 I/O Standard +// /___/ /\ Filename : IBUFG_HSTL_IV_18.v +// \ \ / \ Timestamp : Thu Mar 25 16:42:27 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. + +`timescale 1 ps / 1 ps + + +module IBUFG_HSTL_IV_18 (O, I); + + output O; + + input I; + + buf B1 (O, I); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IBUFG_HSTL_IV_DCI.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IBUFG_HSTL_IV_DCI.v new file mode 100644 index 0000000..c72dfb5 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IBUFG_HSTL_IV_DCI.v @@ -0,0 +1,33 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/IBUFG_HSTL_IV_DCI.v,v 1.6 2007/05/23 21:43:34 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Input Clock Buffer with HSTL_IV_DCI I/O Standard +// /___/ /\ Filename : IBUFG_HSTL_IV_DCI.v +// \ \ / \ Timestamp : Thu Mar 25 16:42:28 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. + +`timescale 1 ps / 1 ps + + +module IBUFG_HSTL_IV_DCI (O, I); + + output O; + + input I; + + buf B1 (O, I); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IBUFG_HSTL_IV_DCI_18.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IBUFG_HSTL_IV_DCI_18.v new file mode 100644 index 0000000..ae45875 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IBUFG_HSTL_IV_DCI_18.v @@ -0,0 +1,33 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/IBUFG_HSTL_IV_DCI_18.v,v 1.6 2007/05/23 21:43:34 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Input Clock Buffer with HSTL_IV_DCI_18 I/O Standard +// /___/ /\ Filename : IBUFG_HSTL_IV_DCI_18.v +// \ \ / \ Timestamp : Thu Mar 25 16:42:28 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. + +`timescale 1 ps / 1 ps + + +module IBUFG_HSTL_IV_DCI_18 (O, I); + + output O; + + input I; + + buf B1 (O, I); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IBUFG_HSTL_I_18.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IBUFG_HSTL_I_18.v new file mode 100644 index 0000000..75b55f2 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IBUFG_HSTL_I_18.v @@ -0,0 +1,33 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/IBUFG_HSTL_I_18.v,v 1.6 2007/05/23 21:43:34 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Input Clock Buffer with HSTL_I_18 I/O Standard +// /___/ /\ Filename : IBUFG_HSTL_I_18.v +// \ \ / \ Timestamp : Thu Mar 25 16:42:28 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. + +`timescale 1 ps / 1 ps + + +module IBUFG_HSTL_I_18 (O, I); + + output O; + + input I; + + buf B1 (O, I); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IBUFG_HSTL_I_DCI.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IBUFG_HSTL_I_DCI.v new file mode 100644 index 0000000..174f055 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IBUFG_HSTL_I_DCI.v @@ -0,0 +1,33 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/IBUFG_HSTL_I_DCI.v,v 1.6 2007/05/23 21:43:34 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Input Clock Buffer with HSTL_I_DCI I/O Standard +// /___/ /\ Filename : IBUFG_HSTL_I_DCI.v +// \ \ / \ Timestamp : Thu Mar 25 16:42:28 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. + +`timescale 1 ps / 1 ps + + +module IBUFG_HSTL_I_DCI (O, I); + + output O; + + input I; + + buf B1 (O, I); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IBUFG_HSTL_I_DCI_18.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IBUFG_HSTL_I_DCI_18.v new file mode 100644 index 0000000..95b3292 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IBUFG_HSTL_I_DCI_18.v @@ -0,0 +1,33 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/IBUFG_HSTL_I_DCI_18.v,v 1.6 2007/05/23 21:43:34 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Input Clock Buffer with HSTL_I_DCI_18 I/O Standard +// /___/ /\ Filename : IBUFG_HSTL_I_DCI_18.v +// \ \ / \ Timestamp : Thu Mar 25 16:42:28 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. + +`timescale 1 ps / 1 ps + + +module IBUFG_HSTL_I_DCI_18 (O, I); + + output O; + + input I; + + buf B1 (O, I); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IBUFG_LVCMOS12.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IBUFG_LVCMOS12.v new file mode 100644 index 0000000..b6cc781 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IBUFG_LVCMOS12.v @@ -0,0 +1,33 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/IBUFG_LVCMOS12.v,v 1.6 2007/05/23 21:43:34 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Input Clock Buffer with LVCMOS12 I/O Standard +// /___/ /\ Filename : IBUFG_LVCMOS12.v +// \ \ / \ Timestamp : Thu Mar 25 16:42:28 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. + +`timescale 1 ps / 1 ps + + +module IBUFG_LVCMOS12 (O, I); + + output O; + + input I; + + buf B1 (O, I); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IBUFG_LVCMOS15.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IBUFG_LVCMOS15.v new file mode 100644 index 0000000..6caa5bf --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IBUFG_LVCMOS15.v @@ -0,0 +1,33 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/IBUFG_LVCMOS15.v,v 1.6 2007/05/23 21:43:34 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Input Clock Buffer with LVCMOS15 I/O Standard +// /___/ /\ Filename : IBUFG_LVCMOS15.v +// \ \ / \ Timestamp : Thu Mar 25 16:42:28 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. + +`timescale 1 ps / 1 ps + + +module IBUFG_LVCMOS15 (O, I); + + output O; + + input I; + + buf B1 (O, I); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IBUFG_LVCMOS18.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IBUFG_LVCMOS18.v new file mode 100644 index 0000000..dba00e2 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IBUFG_LVCMOS18.v @@ -0,0 +1,33 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/IBUFG_LVCMOS18.v,v 1.6 2007/05/23 21:43:34 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Input Clock Buffer with LVCMOS18 I/O Standard +// /___/ /\ Filename : IBUFG_LVCMOS18.v +// \ \ / \ Timestamp : Thu Mar 25 16:42:28 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. + +`timescale 1 ps / 1 ps + + +module IBUFG_LVCMOS18 (O, I); + + output O; + + input I; + + buf B1 (O, I); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IBUFG_LVCMOS2.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IBUFG_LVCMOS2.v new file mode 100644 index 0000000..a546ffe --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IBUFG_LVCMOS2.v @@ -0,0 +1,33 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/IBUFG_LVCMOS2.v,v 1.6 2007/05/23 21:43:34 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Input Clock Buffer with LVCMOS2 I/O Standard +// /___/ /\ Filename : IBUFG_LVCMOS2.v +// \ \ / \ Timestamp : Thu Mar 25 16:42:28 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. + +`timescale 1 ps / 1 ps + + +module IBUFG_LVCMOS2 (O, I); + + output O; + + input I; + + buf B1 (O, I); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IBUFG_LVCMOS25.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IBUFG_LVCMOS25.v new file mode 100644 index 0000000..821a2cc --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IBUFG_LVCMOS25.v @@ -0,0 +1,33 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/IBUFG_LVCMOS25.v,v 1.6 2007/05/23 21:43:34 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Input Clock Buffer with LVCMOS25 I/O Standard +// /___/ /\ Filename : IBUFG_LVCMOS25.v +// \ \ / \ Timestamp : Thu Mar 25 16:42:28 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. + +`timescale 1 ps / 1 ps + + +module IBUFG_LVCMOS25 (O, I); + + output O; + + input I; + + buf B1 (O, I); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IBUFG_LVCMOS33.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IBUFG_LVCMOS33.v new file mode 100644 index 0000000..130d36a --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IBUFG_LVCMOS33.v @@ -0,0 +1,33 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/IBUFG_LVCMOS33.v,v 1.6 2007/05/23 21:43:34 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Input Clock Buffer with LVCMOS33 I/O Standard +// /___/ /\ Filename : IBUFG_LVCMOS33.v +// \ \ / \ Timestamp : Thu Mar 25 16:42:29 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. + +`timescale 1 ps / 1 ps + + +module IBUFG_LVCMOS33 (O, I); + + output O; + + input I; + + buf B1 (O, I); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IBUFG_LVDCI_15.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IBUFG_LVDCI_15.v new file mode 100644 index 0000000..87d8430 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IBUFG_LVDCI_15.v @@ -0,0 +1,33 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/IBUFG_LVDCI_15.v,v 1.6 2007/05/23 21:43:34 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Input Clock Buffer with LVDCI_15 I/O Standard +// /___/ /\ Filename : IBUFG_LVDCI_15.v +// \ \ / \ Timestamp : Thu Mar 25 16:42:29 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. + +`timescale 1 ps / 1 ps + + +module IBUFG_LVDCI_15 (O, I); + + output O; + + input I; + + buf B1 (O, I); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IBUFG_LVDCI_18.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IBUFG_LVDCI_18.v new file mode 100644 index 0000000..d50d2a9 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IBUFG_LVDCI_18.v @@ -0,0 +1,33 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/IBUFG_LVDCI_18.v,v 1.6 2007/05/23 21:43:34 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Input Clock Buffer with LVDCI_18 I/O Standard +// /___/ /\ Filename : IBUFG_LVDCI_18.v +// \ \ / \ Timestamp : Thu Mar 25 16:42:29 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. + +`timescale 1 ps / 1 ps + + +module IBUFG_LVDCI_18 (O, I); + + output O; + + input I; + + buf B1 (O, I); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IBUFG_LVDCI_25.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IBUFG_LVDCI_25.v new file mode 100644 index 0000000..b8b5398 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IBUFG_LVDCI_25.v @@ -0,0 +1,33 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/IBUFG_LVDCI_25.v,v 1.6 2007/05/23 21:43:34 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Input Clock Buffer with LVDCI_25 I/O Standard +// /___/ /\ Filename : IBUFG_LVDCI_25.v +// \ \ / \ Timestamp : Thu Mar 25 16:42:29 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. + +`timescale 1 ps / 1 ps + + +module IBUFG_LVDCI_25 (O, I); + + output O; + + input I; + + buf B1 (O, I); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IBUFG_LVDCI_33.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IBUFG_LVDCI_33.v new file mode 100644 index 0000000..50a13fa --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IBUFG_LVDCI_33.v @@ -0,0 +1,33 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/IBUFG_LVDCI_33.v,v 1.6 2007/05/23 21:43:34 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Input Clock Buffer with LVDCI_33 I/O Standard +// /___/ /\ Filename : IBUFG_LVDCI_33.v +// \ \ / \ Timestamp : Thu Mar 25 16:42:29 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. + +`timescale 1 ps / 1 ps + + +module IBUFG_LVDCI_33 (O, I); + + output O; + + input I; + + buf B1 (O, I); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IBUFG_LVDCI_DV2_15.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IBUFG_LVDCI_DV2_15.v new file mode 100644 index 0000000..bdd3c3d --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IBUFG_LVDCI_DV2_15.v @@ -0,0 +1,33 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/IBUFG_LVDCI_DV2_15.v,v 1.6 2007/05/23 21:43:34 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Input Clock Buffer with LVDCI_DV2_15 I/O Standard +// /___/ /\ Filename : IBUFG_LVDCI_DV2_15.v +// \ \ / \ Timestamp : Thu Mar 25 16:42:29 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. + +`timescale 1 ps / 1 ps + + +module IBUFG_LVDCI_DV2_15 (O, I); + + output O; + + input I; + + buf B1 (O, I); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IBUFG_LVDCI_DV2_18.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IBUFG_LVDCI_DV2_18.v new file mode 100644 index 0000000..bf0e805 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IBUFG_LVDCI_DV2_18.v @@ -0,0 +1,33 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/IBUFG_LVDCI_DV2_18.v,v 1.6 2007/05/23 21:43:34 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Input Clock Buffer with LVDCI_DV2_18 I/O Standard +// /___/ /\ Filename : IBUFG_LVDCI_DV2_18.v +// \ \ / \ Timestamp : Thu Mar 25 16:42:29 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. + +`timescale 1 ps / 1 ps + + +module IBUFG_LVDCI_DV2_18 (O, I); + + output O; + + input I; + + buf B1 (O, I); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IBUFG_LVDCI_DV2_25.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IBUFG_LVDCI_DV2_25.v new file mode 100644 index 0000000..862bb51 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IBUFG_LVDCI_DV2_25.v @@ -0,0 +1,33 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/IBUFG_LVDCI_DV2_25.v,v 1.6 2007/05/23 21:43:34 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Input Clock Buffer with LVDCI_DV2_25 I/O Standard +// /___/ /\ Filename : IBUFG_LVDCI_DV2_25.v +// \ \ / \ Timestamp : Thu Mar 25 16:42:29 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. + +`timescale 1 ps / 1 ps + + +module IBUFG_LVDCI_DV2_25 (O, I); + + output O; + + input I; + + buf B1 (O, I); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IBUFG_LVDCI_DV2_33.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IBUFG_LVDCI_DV2_33.v new file mode 100644 index 0000000..e497264 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IBUFG_LVDCI_DV2_33.v @@ -0,0 +1,33 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/IBUFG_LVDCI_DV2_33.v,v 1.6 2007/05/23 21:43:34 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Input Clock Buffer with LVDCI_DV2_33 I/O Standard +// /___/ /\ Filename : IBUFG_LVDCI_DV2_33.v +// \ \ / \ Timestamp : Thu Mar 25 16:42:29 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. + +`timescale 1 ps / 1 ps + + +module IBUFG_LVDCI_DV2_33 (O, I); + + output O; + + input I; + + buf B1 (O, I); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IBUFG_LVDS.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IBUFG_LVDS.v new file mode 100644 index 0000000..a6203a9 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IBUFG_LVDS.v @@ -0,0 +1,33 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/IBUFG_LVDS.v,v 1.6 2007/05/23 21:43:34 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Input Clock Buffer with LVDS I/O Standard +// /___/ /\ Filename : IBUFG_LVDS.v +// \ \ / \ Timestamp : Thu Mar 25 16:42:29 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. + +`timescale 1 ps / 1 ps + + +module IBUFG_LVDS (O, I); + + output O; + + input I; + + buf B1 (O, I); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IBUFG_LVPECL.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IBUFG_LVPECL.v new file mode 100644 index 0000000..d5220f4 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IBUFG_LVPECL.v @@ -0,0 +1,33 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/IBUFG_LVPECL.v,v 1.6 2007/05/23 21:43:34 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Input Clock Buffer with LVPECL I/O Standard +// /___/ /\ Filename : IBUFG_LVPECL.v +// \ \ / \ Timestamp : Thu Mar 25 16:42:29 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. + +`timescale 1 ps / 1 ps + + +module IBUFG_LVPECL (O, I); + + output O; + + input I; + + buf B1 (O, I); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IBUFG_LVTTL.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IBUFG_LVTTL.v new file mode 100644 index 0000000..c3db451 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IBUFG_LVTTL.v @@ -0,0 +1,33 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/IBUFG_LVTTL.v,v 1.6 2007/05/23 21:43:34 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Input Clock Buffer with LVTTL I/O Standard +// /___/ /\ Filename : IBUFG_LVTTL.v +// \ \ / \ Timestamp : Thu Mar 25 16:42:30 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. + +`timescale 1 ps / 1 ps + + +module IBUFG_LVTTL (O, I); + + output O; + + input I; + + buf B1 (O, I); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IBUFG_PCI33_3.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IBUFG_PCI33_3.v new file mode 100644 index 0000000..f379ffe --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IBUFG_PCI33_3.v @@ -0,0 +1,33 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/IBUFG_PCI33_3.v,v 1.6 2007/05/23 21:43:34 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Input Clock Buffer with PCI33_3 I/O Standard +// /___/ /\ Filename : IBUFG_PCI33_3.v +// \ \ / \ Timestamp : Thu Mar 25 16:42:30 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. + +`timescale 1 ps / 1 ps + + +module IBUFG_PCI33_3 (O, I); + + output O; + + input I; + + buf B1 (O, I); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IBUFG_PCI33_5.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IBUFG_PCI33_5.v new file mode 100644 index 0000000..e50c3ed --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IBUFG_PCI33_5.v @@ -0,0 +1,33 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/IBUFG_PCI33_5.v,v 1.6 2007/05/23 21:43:34 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Input Clock Buffer with PCI33_5 I/O Standard +// /___/ /\ Filename : IBUFG_PCI33_5.v +// \ \ / \ Timestamp : Thu Mar 25 16:42:30 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. + +`timescale 1 ps / 1 ps + + +module IBUFG_PCI33_5 (O, I); + + output O; + + input I; + + buf B1 (O, I); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IBUFG_PCI66_3.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IBUFG_PCI66_3.v new file mode 100644 index 0000000..71e1a6f --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IBUFG_PCI66_3.v @@ -0,0 +1,33 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/IBUFG_PCI66_3.v,v 1.6 2007/05/23 21:43:34 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Input Clock Buffer with PCI66_3 I/O Standard +// /___/ /\ Filename : IBUFG_PCI66_3.v +// \ \ / \ Timestamp : Thu Mar 25 16:42:30 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. + +`timescale 1 ps / 1 ps + + +module IBUFG_PCI66_3 (O, I); + + output O; + + input I; + + buf B1 (O, I); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IBUFG_PCIX.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IBUFG_PCIX.v new file mode 100644 index 0000000..eaf5449 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IBUFG_PCIX.v @@ -0,0 +1,33 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/IBUFG_PCIX.v,v 1.6 2007/05/23 21:43:34 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Input Clock Buffer with PCIX I/O Standard +// /___/ /\ Filename : IBUFG_PCIX.v +// \ \ / \ Timestamp : Thu Mar 25 16:42:30 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. + +`timescale 1 ps / 1 ps + + +module IBUFG_PCIX (O, I); + + output O; + + input I; + + buf B1 (O, I); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IBUFG_PCIX66_3.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IBUFG_PCIX66_3.v new file mode 100644 index 0000000..947418e --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IBUFG_PCIX66_3.v @@ -0,0 +1,33 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/IBUFG_PCIX66_3.v,v 1.6 2007/05/23 21:43:34 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Input Clock Buffer with PCIX66_3 I/O Standard +// /___/ /\ Filename : IBUFG_PCIX66_3.v +// \ \ / \ Timestamp : Thu Mar 25 16:42:30 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. + +`timescale 1 ps / 1 ps + + +module IBUFG_PCIX66_3 (O, I); + + output O; + + input I; + + buf B1 (O, I); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IBUFG_SSTL18_I.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IBUFG_SSTL18_I.v new file mode 100644 index 0000000..07d9f12 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IBUFG_SSTL18_I.v @@ -0,0 +1,33 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/IBUFG_SSTL18_I.v,v 1.6 2007/05/23 21:43:34 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Input Clock Buffer with SSTL18_I I/O Standard +// /___/ /\ Filename : IBUFG_SSTL18_I.v +// \ \ / \ Timestamp : Thu Mar 25 16:42:30 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. + +`timescale 1 ps / 1 ps + + +module IBUFG_SSTL18_I (O, I); + + output O; + + input I; + + buf B1 (O, I); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IBUFG_SSTL18_II.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IBUFG_SSTL18_II.v new file mode 100644 index 0000000..b7d5473 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IBUFG_SSTL18_II.v @@ -0,0 +1,33 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/IBUFG_SSTL18_II.v,v 1.6 2007/05/23 21:43:34 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Input Clock Buffer with SSTL18_II I/O Standard +// /___/ /\ Filename : IBUFG_SSTL18_II.v +// \ \ / \ Timestamp : Thu Mar 25 16:42:30 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. + +`timescale 1 ps / 1 ps + + +module IBUFG_SSTL18_II (O, I); + + output O; + + input I; + + buf B1 (O, I); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IBUFG_SSTL18_II_DCI.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IBUFG_SSTL18_II_DCI.v new file mode 100644 index 0000000..3a34ae5 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IBUFG_SSTL18_II_DCI.v @@ -0,0 +1,33 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/IBUFG_SSTL18_II_DCI.v,v 1.6 2007/05/23 21:43:34 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Input Clock Buffer with SSTL18_II_DCI I/O Standard +// /___/ /\ Filename : IBUFG_SSTL18_II_DCI.v +// \ \ / \ Timestamp : Thu Mar 25 16:42:30 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. + +`timescale 1 ps / 1 ps + + +module IBUFG_SSTL18_II_DCI (O, I); + + output O; + + input I; + + buf B1 (O, I); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IBUFG_SSTL18_I_DCI.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IBUFG_SSTL18_I_DCI.v new file mode 100644 index 0000000..5229673 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IBUFG_SSTL18_I_DCI.v @@ -0,0 +1,33 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/IBUFG_SSTL18_I_DCI.v,v 1.6 2007/05/23 21:43:34 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Input Clock Buffer with SSTL18_I_DCI I/O Standard +// /___/ /\ Filename : IBUFG_SSTL18_I_DCI.v +// \ \ / \ Timestamp : Thu Mar 25 16:42:31 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. + +`timescale 1 ps / 1 ps + + +module IBUFG_SSTL18_I_DCI (O, I); + + output O; + + input I; + + buf B1 (O, I); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IBUFG_SSTL2_I.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IBUFG_SSTL2_I.v new file mode 100644 index 0000000..b6c4063 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IBUFG_SSTL2_I.v @@ -0,0 +1,33 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/IBUFG_SSTL2_I.v,v 1.6 2007/05/23 21:43:34 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Input Clock Buffer with SSTL2_I I/O Standard +// /___/ /\ Filename : IBUFG_SSTL2_I.v +// \ \ / \ Timestamp : Thu Mar 25 16:42:31 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. + +`timescale 1 ps / 1 ps + + +module IBUFG_SSTL2_I (O, I); + + output O; + + input I; + + buf B1 (O, I); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IBUFG_SSTL2_II.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IBUFG_SSTL2_II.v new file mode 100644 index 0000000..4813600 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IBUFG_SSTL2_II.v @@ -0,0 +1,33 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/IBUFG_SSTL2_II.v,v 1.6 2007/05/23 21:43:34 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Input Clock Buffer with SSTL2_II I/O Standard +// /___/ /\ Filename : IBUFG_SSTL2_II.v +// \ \ / \ Timestamp : Thu Mar 25 16:42:31 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. + +`timescale 1 ps / 1 ps + + +module IBUFG_SSTL2_II (O, I); + + output O; + + input I; + + buf B1 (O, I); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IBUFG_SSTL2_II_DCI.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IBUFG_SSTL2_II_DCI.v new file mode 100644 index 0000000..c9658a6 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IBUFG_SSTL2_II_DCI.v @@ -0,0 +1,33 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/IBUFG_SSTL2_II_DCI.v,v 1.6 2007/05/23 21:43:34 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Input Clock Buffer with SSTL2_II_DCI I/O Standard +// /___/ /\ Filename : IBUFG_SSTL2_II_DCI.v +// \ \ / \ Timestamp : Thu Mar 25 16:42:31 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. + +`timescale 1 ps / 1 ps + + +module IBUFG_SSTL2_II_DCI (O, I); + + output O; + + input I; + + buf B1 (O, I); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IBUFG_SSTL2_I_DCI.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IBUFG_SSTL2_I_DCI.v new file mode 100644 index 0000000..59a3305 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IBUFG_SSTL2_I_DCI.v @@ -0,0 +1,33 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/IBUFG_SSTL2_I_DCI.v,v 1.6 2007/05/23 21:43:34 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Input Clock Buffer with SSTL2_I_DCI I/O Standard +// /___/ /\ Filename : IBUFG_SSTL2_I_DCI.v +// \ \ / \ Timestamp : Thu Mar 25 16:42:31 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. + +`timescale 1 ps / 1 ps + + +module IBUFG_SSTL2_I_DCI (O, I); + + output O; + + input I; + + buf B1 (O, I); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IBUFG_SSTL3_I.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IBUFG_SSTL3_I.v new file mode 100644 index 0000000..8245a34 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IBUFG_SSTL3_I.v @@ -0,0 +1,33 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/IBUFG_SSTL3_I.v,v 1.6 2007/05/23 21:43:34 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Input Clock Buffer with SSTL3_I I/O Standard +// /___/ /\ Filename : IBUFG_SSTL3_I.v +// \ \ / \ Timestamp : Thu Mar 25 16:42:31 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. + +`timescale 1 ps / 1 ps + + +module IBUFG_SSTL3_I (O, I); + + output O; + + input I; + + buf B1 (O, I); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IBUFG_SSTL3_II.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IBUFG_SSTL3_II.v new file mode 100644 index 0000000..8ceeecf --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IBUFG_SSTL3_II.v @@ -0,0 +1,33 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/IBUFG_SSTL3_II.v,v 1.6 2007/05/23 21:43:34 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Input Clock Buffer with SSTL3_II I/O Standard +// /___/ /\ Filename : IBUFG_SSTL3_II.v +// \ \ / \ Timestamp : Thu Mar 25 16:42:31 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. + +`timescale 1 ps / 1 ps + + +module IBUFG_SSTL3_II (O, I); + + output O; + + input I; + + buf B1 (O, I); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IBUFG_SSTL3_II_DCI.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IBUFG_SSTL3_II_DCI.v new file mode 100644 index 0000000..cc93720 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IBUFG_SSTL3_II_DCI.v @@ -0,0 +1,33 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/IBUFG_SSTL3_II_DCI.v,v 1.6 2007/05/23 21:43:34 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Input Clock Buffer with SSTL3_II_DCI I/O Standard +// /___/ /\ Filename : IBUFG_SSTL3_II_DCI.v +// \ \ / \ Timestamp : Thu Mar 25 16:42:31 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. + +`timescale 1 ps / 1 ps + + +module IBUFG_SSTL3_II_DCI (O, I); + + output O; + + input I; + + buf B1 (O, I); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IBUFG_SSTL3_I_DCI.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IBUFG_SSTL3_I_DCI.v new file mode 100644 index 0000000..86087dc --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IBUFG_SSTL3_I_DCI.v @@ -0,0 +1,33 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/IBUFG_SSTL3_I_DCI.v,v 1.6 2007/05/23 21:43:34 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Input Clock Buffer with SSTL3_I_DCI I/O Standard +// /___/ /\ Filename : IBUFG_SSTL3_I_DCI.v +// \ \ / \ Timestamp : Thu Mar 25 16:42:31 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. + +`timescale 1 ps / 1 ps + + +module IBUFG_SSTL3_I_DCI (O, I); + + output O; + + input I; + + buf B1 (O, I); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IBUF_AGP.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IBUF_AGP.v new file mode 100644 index 0000000..740d9d8 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IBUF_AGP.v @@ -0,0 +1,33 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/IBUF_AGP.v,v 1.6 2007/05/23 21:43:33 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Input Buffer with AGP I/O Standard +// /___/ /\ Filename : IBUF_AGP.v +// \ \ / \ Timestamp : Thu Mar 25 16:42:31 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. + +`timescale 1 ps / 1 ps + + +module IBUF_AGP (O, I); + + output O; + + input I; + + buf B1 (O, I); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IBUF_CTT.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IBUF_CTT.v new file mode 100644 index 0000000..e5b88e6 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IBUF_CTT.v @@ -0,0 +1,33 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/IBUF_CTT.v,v 1.6 2007/05/23 21:43:33 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Input Buffer with CTT I/O Standard +// /___/ /\ Filename : IBUF_CTT.v +// \ \ / \ Timestamp : Thu Mar 25 16:42:31 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. + +`timescale 1 ps / 1 ps + + +module IBUF_CTT (O, I); + + output O; + + input I; + + buf B1 (O, I); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IBUF_DLY_ADJ.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IBUF_DLY_ADJ.v new file mode 100644 index 0000000..0f85a8f --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IBUF_DLY_ADJ.v @@ -0,0 +1,138 @@ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Dynamically Adjustable Input Delay Buffer +// /___/ /\ Filename : IBUF_DLY_ADJ.v +// \ \ / \ Timestamp : Thu Feb 17 16:44:07 PST 2005 +// \___\/\___\ +// +// Revision: +// 03/23/05 - Initial version. +// 05/29/07 - Added wire declaration for internal signals +// 08/08/07 - CR 439320 -- Simprim fix -- Added attributes SIM_DELAY0, ... SIM_DELAY16 to fix timing issues +// 09/11/07 - CR 447604 -- When S[2:0]=0, it should correlate to 1 tap +// 03/28/08 - CR 469907 -- Corrected bus path of S[2:0] in the specify block elaboration +// End Revision + +`timescale 1 ps / 1 ps + +module IBUF_DLY_ADJ (O, I, S); + + output O; + + input I; + input [2:0] S; + + + parameter DELAY_OFFSET = "OFF"; + parameter IOSTANDARD = "DEFAULT"; + +// xilinx_internal_parameter on + // WARNING !!!: This model may not work properly if the + // following parameter is changed. + localparam SIM_TAPDELAY_VALUE = 200; + localparam SPECTRUM_OFFSET_DELAY = 1600; + +// xilinx_internal_parameter off + + + reg o_out; + + wire [2:0] s_in; + integer delay_count; + + wire delay_chain_0, delay_chain_1, delay_chain_2, delay_chain_3, + delay_chain_4, delay_chain_5, delay_chain_6, delay_chain_7; + + wire i_in; + + buf buf_o (O, o_out); + + buf buf_i (i_in, I); + buf buf_s[2:0] (s_in, S); + +// buf buf_gsr (gsr_in, GSR); + + time INITIAL_DELAY = 0; + time FINAL_DELAY = 0; + + + + initial begin + if (DELAY_OFFSET != "ON" && DELAY_OFFSET != "OFF") begin + + $display("Attribute Syntax Error : The attribute DELAY_OFFSET on IBUF_DLY_ADJ instance %m is set to %s. Legal values for this attribute are ON or OFF", DELAY_OFFSET); + $finish; + + end + + if(DELAY_OFFSET == "ON") +// CR 447604 +// INITIAL_DELAY = SPECTRUM_OFFSET_DELAY; + INITIAL_DELAY = SPECTRUM_OFFSET_DELAY + SIM_TAPDELAY_VALUE; + else +// INITIAL_DELAY = 0; + INITIAL_DELAY = SIM_TAPDELAY_VALUE; + + end // initial begin + + +//------------------------------------------------------------ +//--------------------------- GSR ---------------------------- +//------------------------------------------------------------ +// always @(gsr_in) +// if (gsr_in == 1'b1) +// assign delay_count = 0; +// else if (gsr_in == 1'b0) +// deassign delay_count; + +//------------------------------------------------------------ +//----------------------- S input ---------------------------- +//------------------------------------------------------------ + always@s_in +// #FINAL_DELAY = s_in * SIM_TAP_DELAY_VALUE + INITIAL_DELAY; + delay_count = s_in; + + +//------------------------------------------------------------ +//---------------------- delay the chain -------------------- +//------------------------------------------------------------ + assign #INITIAL_DELAY delay_chain_0 = i_in; + assign #SIM_TAPDELAY_VALUE delay_chain_1 = delay_chain_0; + assign #SIM_TAPDELAY_VALUE delay_chain_2 = delay_chain_1; + assign #SIM_TAPDELAY_VALUE delay_chain_3 = delay_chain_2; + assign #SIM_TAPDELAY_VALUE delay_chain_4 = delay_chain_3; + assign #SIM_TAPDELAY_VALUE delay_chain_5 = delay_chain_4; + assign #SIM_TAPDELAY_VALUE delay_chain_6 = delay_chain_5; + assign #SIM_TAPDELAY_VALUE delay_chain_7 = delay_chain_6; + +//------------------------------------------------------------ +//---------------------- Assign to output ------------------- +//------------------------------------------------------------ + always @(delay_count) begin + + case (delay_count) + 0: assign o_out = delay_chain_0; + 1: assign o_out = delay_chain_1; + 2: assign o_out = delay_chain_2; + 3: assign o_out = delay_chain_3; + 4: assign o_out = delay_chain_4; + 5: assign o_out = delay_chain_5; + 6: assign o_out = delay_chain_6; + 7: assign o_out = delay_chain_7; + default: + assign o_out = delay_chain_0; + + endcase + end // always @ (s_in) + + + +endmodule // IBUF_DLY_ADJ + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IBUF_GTL.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IBUF_GTL.v new file mode 100644 index 0000000..1bcf643 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IBUF_GTL.v @@ -0,0 +1,33 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/IBUF_GTL.v,v 1.6 2007/05/23 21:43:34 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Input Buffer with GTL I/O Standard +// /___/ /\ Filename : IBUF_GTL.v +// \ \ / \ Timestamp : Thu Mar 25 16:42:32 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. + +`timescale 1 ps / 1 ps + + +module IBUF_GTL (O, I); + + output O; + + input I; + + buf B1 (O, I); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IBUF_GTLP.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IBUF_GTLP.v new file mode 100644 index 0000000..064b367 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IBUF_GTLP.v @@ -0,0 +1,33 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/IBUF_GTLP.v,v 1.6 2007/05/23 21:43:34 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Input Buffer with GTLP I/O Standard +// /___/ /\ Filename : IBUF_GTLP.v +// \ \ / \ Timestamp : Thu Mar 25 16:42:32 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. + +`timescale 1 ps / 1 ps + + +module IBUF_GTLP (O, I); + + output O; + + input I; + + buf B1 (O, I); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IBUF_GTLP_DCI.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IBUF_GTLP_DCI.v new file mode 100644 index 0000000..b0d00b4 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IBUF_GTLP_DCI.v @@ -0,0 +1,33 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/IBUF_GTLP_DCI.v,v 1.6 2007/05/23 21:43:34 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Input Buffer with GTLP_DCI I/O Standard +// /___/ /\ Filename : IBUF_GTLP_DCI.v +// \ \ / \ Timestamp : Thu Mar 25 16:42:32 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. + +`timescale 1 ps / 1 ps + + +module IBUF_GTLP_DCI (O, I); + + output O; + + input I; + + buf B1 (O, I); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IBUF_GTL_DCI.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IBUF_GTL_DCI.v new file mode 100644 index 0000000..ead5602 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IBUF_GTL_DCI.v @@ -0,0 +1,33 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/IBUF_GTL_DCI.v,v 1.6 2007/05/23 21:43:34 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Input Buffer with GTL_DCI I/O Standard +// /___/ /\ Filename : IBUF_GTL_DCI.v +// \ \ / \ Timestamp : Thu Mar 25 16:42:32 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. + +`timescale 1 ps / 1 ps + + +module IBUF_GTL_DCI (O, I); + + output O; + + input I; + + buf B1 (O, I); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IBUF_HSTL_I.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IBUF_HSTL_I.v new file mode 100644 index 0000000..7ad18bb --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IBUF_HSTL_I.v @@ -0,0 +1,33 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/IBUF_HSTL_I.v,v 1.6 2007/05/23 21:43:34 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Input Buffer with HSTL_I I/O Standard +// /___/ /\ Filename : IBUF_HSTL_I.v +// \ \ / \ Timestamp : Thu Mar 25 16:42:32 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. + +`timescale 1 ps / 1 ps + + +module IBUF_HSTL_I (O, I); + + output O; + + input I; + + buf B1 (O, I); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IBUF_HSTL_II.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IBUF_HSTL_II.v new file mode 100644 index 0000000..d38cbb2 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IBUF_HSTL_II.v @@ -0,0 +1,33 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/IBUF_HSTL_II.v,v 1.6 2007/05/23 21:43:34 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Input Buffer with HSTL_II I/O Standard +// /___/ /\ Filename : IBUF_HSTL_II.v +// \ \ / \ Timestamp : Thu Mar 25 16:42:32 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. + +`timescale 1 ps / 1 ps + + +module IBUF_HSTL_II (O, I); + + output O; + + input I; + + buf B1 (O, I); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IBUF_HSTL_III.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IBUF_HSTL_III.v new file mode 100644 index 0000000..9ea82d7 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IBUF_HSTL_III.v @@ -0,0 +1,33 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/IBUF_HSTL_III.v,v 1.6 2007/05/23 21:43:34 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Input Buffer with HSTL_III I/O Standard +// /___/ /\ Filename : IBUF_HSTL_III.v +// \ \ / \ Timestamp : Thu Mar 25 16:42:32 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. + +`timescale 1 ps / 1 ps + + +module IBUF_HSTL_III (O, I); + + output O; + + input I; + + buf B1 (O, I); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IBUF_HSTL_III_18.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IBUF_HSTL_III_18.v new file mode 100644 index 0000000..eeee43d --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IBUF_HSTL_III_18.v @@ -0,0 +1,33 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/IBUF_HSTL_III_18.v,v 1.6 2007/05/23 21:43:34 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Input Buffer with HSTL_III_18 I/O Standard +// /___/ /\ Filename : IBUF_HSTL_III_18.v +// \ \ / \ Timestamp : Thu Mar 25 16:42:32 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. + +`timescale 1 ps / 1 ps + + +module IBUF_HSTL_III_18 (O, I); + + output O; + + input I; + + buf B1 (O, I); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IBUF_HSTL_III_DCI.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IBUF_HSTL_III_DCI.v new file mode 100644 index 0000000..648b3a4 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IBUF_HSTL_III_DCI.v @@ -0,0 +1,33 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/IBUF_HSTL_III_DCI.v,v 1.6 2007/05/23 21:43:34 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Input Buffer with HSTL_III_DCI I/O Standard +// /___/ /\ Filename : IBUF_HSTL_III_DCI.v +// \ \ / \ Timestamp : Thu Mar 25 16:42:32 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. + +`timescale 1 ps / 1 ps + + +module IBUF_HSTL_III_DCI (O, I); + + output O; + + input I; + + buf B1 (O, I); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IBUF_HSTL_III_DCI_18.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IBUF_HSTL_III_DCI_18.v new file mode 100644 index 0000000..db9ffec --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IBUF_HSTL_III_DCI_18.v @@ -0,0 +1,33 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/IBUF_HSTL_III_DCI_18.v,v 1.6 2007/05/23 21:43:34 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Input Buffer with HSTL_III_DCI_18 I/O Standard +// /___/ /\ Filename : IBUF_HSTL_III_DCI_18.v +// \ \ / \ Timestamp : Thu Mar 25 16:42:32 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. + +`timescale 1 ps / 1 ps + + +module IBUF_HSTL_III_DCI_18 (O, I); + + output O; + + input I; + + buf B1 (O, I); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IBUF_HSTL_II_18.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IBUF_HSTL_II_18.v new file mode 100644 index 0000000..253f480 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IBUF_HSTL_II_18.v @@ -0,0 +1,33 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/IBUF_HSTL_II_18.v,v 1.6 2007/05/23 21:43:34 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Input Buffer with HSTL_II_18 I/O Standard +// /___/ /\ Filename : IBUF_HSTL_II_18.v +// \ \ / \ Timestamp : Thu Mar 25 16:42:33 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. + +`timescale 1 ps / 1 ps + + +module IBUF_HSTL_II_18 (O, I); + + output O; + + input I; + + buf B1 (O, I); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IBUF_HSTL_II_DCI.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IBUF_HSTL_II_DCI.v new file mode 100644 index 0000000..f0e55b9 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IBUF_HSTL_II_DCI.v @@ -0,0 +1,33 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/IBUF_HSTL_II_DCI.v,v 1.6 2007/05/23 21:43:34 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Input Buffer with HSTL_II_DCI I/O Standard +// /___/ /\ Filename : IBUF_HSTL_II_DCI.v +// \ \ / \ Timestamp : Thu Mar 25 16:42:33 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. + +`timescale 1 ps / 1 ps + + +module IBUF_HSTL_II_DCI (O, I); + + output O; + + input I; + + buf B1 (O, I); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IBUF_HSTL_II_DCI_18.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IBUF_HSTL_II_DCI_18.v new file mode 100644 index 0000000..192c15b --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IBUF_HSTL_II_DCI_18.v @@ -0,0 +1,33 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/IBUF_HSTL_II_DCI_18.v,v 1.6 2007/05/23 21:43:34 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Input Buffer with HSTL_II_DCI_18 I/O Standard +// /___/ /\ Filename : IBUF_HSTL_II_DCI_18.v +// \ \ / \ Timestamp : Thu Mar 25 16:42:33 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. + +`timescale 1 ps / 1 ps + + +module IBUF_HSTL_II_DCI_18 (O, I); + + output O; + + input I; + + buf B1 (O, I); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IBUF_HSTL_IV.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IBUF_HSTL_IV.v new file mode 100644 index 0000000..6618091 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IBUF_HSTL_IV.v @@ -0,0 +1,33 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/IBUF_HSTL_IV.v,v 1.6 2007/05/23 21:43:35 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Input Buffer with HSTL_IV I/O Standard +// /___/ /\ Filename : IBUF_HSTL_IV.v +// \ \ / \ Timestamp : Thu Mar 25 16:42:33 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. + +`timescale 1 ps / 1 ps + + +module IBUF_HSTL_IV (O, I); + + output O; + + input I; + + buf B1 (O, I); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IBUF_HSTL_IV_18.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IBUF_HSTL_IV_18.v new file mode 100644 index 0000000..1d99415 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IBUF_HSTL_IV_18.v @@ -0,0 +1,33 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/IBUF_HSTL_IV_18.v,v 1.6 2007/05/23 21:43:35 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Input Buffer with HSTL_IV_18 I/O Standard +// /___/ /\ Filename : IBUF_HSTL_IV_18.v +// \ \ / \ Timestamp : Thu Mar 25 16:42:33 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. + +`timescale 1 ps / 1 ps + + +module IBUF_HSTL_IV_18 (O, I); + + output O; + + input I; + + buf B1 (O, I); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IBUF_HSTL_IV_DCI.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IBUF_HSTL_IV_DCI.v new file mode 100644 index 0000000..a0a2dc0 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IBUF_HSTL_IV_DCI.v @@ -0,0 +1,33 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/IBUF_HSTL_IV_DCI.v,v 1.6 2007/05/23 21:43:35 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Input Buffer with HSTL_IV_DCI I/O Standard +// /___/ /\ Filename : IBUF_HSTL_IV_DCI.v +// \ \ / \ Timestamp : Thu Mar 25 16:42:33 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. + +`timescale 1 ps / 1 ps + + +module IBUF_HSTL_IV_DCI (O, I); + + output O; + + input I; + + buf B1 (O, I); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IBUF_HSTL_IV_DCI_18.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IBUF_HSTL_IV_DCI_18.v new file mode 100644 index 0000000..c0aaa6f --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IBUF_HSTL_IV_DCI_18.v @@ -0,0 +1,33 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/IBUF_HSTL_IV_DCI_18.v,v 1.6 2007/05/23 21:43:35 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Input Buffer with HSTL_IV_DCI_18 I/O Standard +// /___/ /\ Filename : IBUF_HSTL_IV_DCI_18.v +// \ \ / \ Timestamp : Thu Mar 25 16:42:33 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. + +`timescale 1 ps / 1 ps + + +module IBUF_HSTL_IV_DCI_18 (O, I); + + output O; + + input I; + + buf B1 (O, I); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IBUF_HSTL_I_18.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IBUF_HSTL_I_18.v new file mode 100644 index 0000000..1b51d96 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IBUF_HSTL_I_18.v @@ -0,0 +1,33 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/IBUF_HSTL_I_18.v,v 1.6 2007/05/23 21:43:34 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Input Buffer with HSTL_I_18 I/O Standard +// /___/ /\ Filename : IBUF_HSTL_I_18.v +// \ \ / \ Timestamp : Thu Mar 25 16:42:33 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. + +`timescale 1 ps / 1 ps + + +module IBUF_HSTL_I_18 (O, I); + + output O; + + input I; + + buf B1 (O, I); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IBUF_HSTL_I_DCI.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IBUF_HSTL_I_DCI.v new file mode 100644 index 0000000..0a267b3 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IBUF_HSTL_I_DCI.v @@ -0,0 +1,33 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/IBUF_HSTL_I_DCI.v,v 1.6 2007/05/23 21:43:34 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Input Buffer with HSTL_I_DCI I/O Standard +// /___/ /\ Filename : IBUF_HSTL_I_DCI.v +// \ \ / \ Timestamp : Thu Mar 25 16:42:33 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. + +`timescale 1 ps / 1 ps + + +module IBUF_HSTL_I_DCI (O, I); + + output O; + + input I; + + buf B1 (O, I); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IBUF_HSTL_I_DCI_18.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IBUF_HSTL_I_DCI_18.v new file mode 100644 index 0000000..f946154 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IBUF_HSTL_I_DCI_18.v @@ -0,0 +1,33 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/IBUF_HSTL_I_DCI_18.v,v 1.6 2007/05/23 21:43:34 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Input Buffer with HSTL_I_DCI_18 I/O Standard +// /___/ /\ Filename : IBUF_HSTL_I_DCI_18.v +// \ \ / \ Timestamp : Thu Mar 25 16:42:33 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. + +`timescale 1 ps / 1 ps + + +module IBUF_HSTL_I_DCI_18 (O, I); + + output O; + + input I; + + buf B1 (O, I); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IBUF_LVCMOS12.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IBUF_LVCMOS12.v new file mode 100644 index 0000000..1c437b7 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IBUF_LVCMOS12.v @@ -0,0 +1,33 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/IBUF_LVCMOS12.v,v 1.6 2007/05/23 21:43:35 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Input Buffer with LVCMOS12 I/O Standard +// /___/ /\ Filename : IBUF_LVCMOS12.v +// \ \ / \ Timestamp : Thu Mar 25 16:42:33 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. + +`timescale 1 ps / 1 ps + + +module IBUF_LVCMOS12 (O, I); + + output O; + + input I; + + buf B1 (O, I); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IBUF_LVCMOS15.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IBUF_LVCMOS15.v new file mode 100644 index 0000000..1e41402 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IBUF_LVCMOS15.v @@ -0,0 +1,33 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/IBUF_LVCMOS15.v,v 1.6 2007/05/23 21:43:35 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Input Buffer with LVCMOS15 I/O Standard +// /___/ /\ Filename : IBUF_LVCMOS15.v +// \ \ / \ Timestamp : Thu Mar 25 16:42:34 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. + +`timescale 1 ps / 1 ps + + +module IBUF_LVCMOS15 (O, I); + + output O; + + input I; + + buf B1 (O, I); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IBUF_LVCMOS18.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IBUF_LVCMOS18.v new file mode 100644 index 0000000..57f5c15 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IBUF_LVCMOS18.v @@ -0,0 +1,33 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/IBUF_LVCMOS18.v,v 1.6 2007/05/23 21:43:35 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Input Buffer with LVCMOS18 I/O Standard +// /___/ /\ Filename : IBUF_LVCMOS18.v +// \ \ / \ Timestamp : Thu Mar 25 16:42:34 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. + +`timescale 1 ps / 1 ps + + +module IBUF_LVCMOS18 (O, I); + + output O; + + input I; + + buf B1 (O, I); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IBUF_LVCMOS2.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IBUF_LVCMOS2.v new file mode 100644 index 0000000..454c64b --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IBUF_LVCMOS2.v @@ -0,0 +1,33 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/IBUF_LVCMOS2.v,v 1.6 2007/05/23 21:43:35 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Input Buffer with LVCMOS2 I/O Standard +// /___/ /\ Filename : IBUF_LVCMOS2.v +// \ \ / \ Timestamp : Thu Mar 25 16:42:34 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. + +`timescale 1 ps / 1 ps + + +module IBUF_LVCMOS2 (O, I); + + output O; + + input I; + + buf B1 (O, I); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IBUF_LVCMOS25.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IBUF_LVCMOS25.v new file mode 100644 index 0000000..2474bd1 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IBUF_LVCMOS25.v @@ -0,0 +1,33 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/IBUF_LVCMOS25.v,v 1.6 2007/05/23 21:43:35 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Input Buffer with LVCMOS25 I/O Standard +// /___/ /\ Filename : IBUF_LVCMOS25.v +// \ \ / \ Timestamp : Thu Mar 25 16:42:34 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. + +`timescale 1 ps / 1 ps + + +module IBUF_LVCMOS25 (O, I); + + output O; + + input I; + + buf B1 (O, I); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IBUF_LVCMOS33.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IBUF_LVCMOS33.v new file mode 100644 index 0000000..8c16f24 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IBUF_LVCMOS33.v @@ -0,0 +1,33 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/IBUF_LVCMOS33.v,v 1.6 2007/05/23 21:43:35 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Input Buffer with LVCMOS33 I/O Standard +// /___/ /\ Filename : IBUF_LVCMOS33.v +// \ \ / \ Timestamp : Thu Mar 25 16:42:34 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. + +`timescale 1 ps / 1 ps + + +module IBUF_LVCMOS33 (O, I); + + output O; + + input I; + + buf B1 (O, I); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IBUF_LVDCI_15.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IBUF_LVDCI_15.v new file mode 100644 index 0000000..d320f97 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IBUF_LVDCI_15.v @@ -0,0 +1,33 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/IBUF_LVDCI_15.v,v 1.6 2007/05/23 21:43:35 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Input Buffer with LVDCI_15 I/O Standard +// /___/ /\ Filename : IBUF_LVDCI_15.v +// \ \ / \ Timestamp : Thu Mar 25 16:42:34 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. + +`timescale 1 ps / 1 ps + + +module IBUF_LVDCI_15 (O, I); + + output O; + + input I; + + buf B1 (O, I); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IBUF_LVDCI_18.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IBUF_LVDCI_18.v new file mode 100644 index 0000000..cc8a8b3 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IBUF_LVDCI_18.v @@ -0,0 +1,33 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/IBUF_LVDCI_18.v,v 1.6 2007/05/23 21:43:35 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Input Buffer with LVDCI_18 I/O Standard +// /___/ /\ Filename : IBUF_LVDCI_18.v +// \ \ / \ Timestamp : Thu Mar 25 16:42:34 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. + +`timescale 1 ps / 1 ps + + +module IBUF_LVDCI_18 (O, I); + + output O; + + input I; + + buf B1 (O, I); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IBUF_LVDCI_25.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IBUF_LVDCI_25.v new file mode 100644 index 0000000..4d6cb8b --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IBUF_LVDCI_25.v @@ -0,0 +1,33 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/IBUF_LVDCI_25.v,v 1.6 2007/05/23 21:43:35 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Input Buffer with LVDCI_25 I/O Standard +// /___/ /\ Filename : IBUF_LVDCI_25.v +// \ \ / \ Timestamp : Thu Mar 25 16:42:34 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. + +`timescale 1 ps / 1 ps + + +module IBUF_LVDCI_25 (O, I); + + output O; + + input I; + + buf B1 (O, I); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IBUF_LVDCI_33.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IBUF_LVDCI_33.v new file mode 100644 index 0000000..4adf3cb --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IBUF_LVDCI_33.v @@ -0,0 +1,33 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/IBUF_LVDCI_33.v,v 1.6 2007/05/23 21:43:35 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Input Buffer with LVDCI_33 I/O Standard +// /___/ /\ Filename : IBUF_LVDCI_33.v +// \ \ / \ Timestamp : Thu Mar 25 16:42:34 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. + +`timescale 1 ps / 1 ps + + +module IBUF_LVDCI_33 (O, I); + + output O; + + input I; + + buf B1 (O, I); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IBUF_LVDCI_DV2_15.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IBUF_LVDCI_DV2_15.v new file mode 100644 index 0000000..ffd944b --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IBUF_LVDCI_DV2_15.v @@ -0,0 +1,33 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/IBUF_LVDCI_DV2_15.v,v 1.6 2007/05/23 21:43:35 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Input Buffer with LVDCI_DV2_15 I/O Standard +// /___/ /\ Filename : IBUF_LVDCI_DV2_15.v +// \ \ / \ Timestamp : Thu Mar 25 16:42:34 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. + +`timescale 1 ps / 1 ps + + +module IBUF_LVDCI_DV2_15 (O, I); + + output O; + + input I; + + buf B1 (O, I); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IBUF_LVDCI_DV2_18.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IBUF_LVDCI_DV2_18.v new file mode 100644 index 0000000..fe2d53f --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IBUF_LVDCI_DV2_18.v @@ -0,0 +1,33 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/IBUF_LVDCI_DV2_18.v,v 1.6 2007/05/23 21:43:35 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Input Buffer with LVDCI_DV2_18 I/O Standard +// /___/ /\ Filename : IBUF_LVDCI_DV2_18.v +// \ \ / \ Timestamp : Thu Mar 25 16:42:35 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. + +`timescale 1 ps / 1 ps + + +module IBUF_LVDCI_DV2_18 (O, I); + + output O; + + input I; + + buf B1 (O, I); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IBUF_LVDCI_DV2_25.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IBUF_LVDCI_DV2_25.v new file mode 100644 index 0000000..1f6aea3 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IBUF_LVDCI_DV2_25.v @@ -0,0 +1,33 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/IBUF_LVDCI_DV2_25.v,v 1.6 2007/05/23 21:43:35 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Input Buffer with LVDCI_DV2_25 I/O Standard +// /___/ /\ Filename : IBUF_LVDCI_DV2_25.v +// \ \ / \ Timestamp : Thu Mar 25 16:42:35 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. + +`timescale 1 ps / 1 ps + + +module IBUF_LVDCI_DV2_25 (O, I); + + output O; + + input I; + + buf B1 (O, I); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IBUF_LVDCI_DV2_33.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IBUF_LVDCI_DV2_33.v new file mode 100644 index 0000000..200c551 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IBUF_LVDCI_DV2_33.v @@ -0,0 +1,33 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/IBUF_LVDCI_DV2_33.v,v 1.6 2007/05/23 21:43:35 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Input Buffer with LVDCI_DV2_33 I/O Standard +// /___/ /\ Filename : IBUF_LVDCI_DV2_33.v +// \ \ / \ Timestamp : Thu Mar 25 16:42:35 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. + +`timescale 1 ps / 1 ps + + +module IBUF_LVDCI_DV2_33 (O, I); + + output O; + + input I; + + buf B1 (O, I); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IBUF_LVDS.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IBUF_LVDS.v new file mode 100644 index 0000000..6014e23 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IBUF_LVDS.v @@ -0,0 +1,33 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/IBUF_LVDS.v,v 1.6 2007/05/23 21:43:35 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Input Buffer with LVDS I/O Standard +// /___/ /\ Filename : IBUF_LVDS.v +// \ \ / \ Timestamp : Thu Mar 25 16:42:35 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. + +`timescale 1 ps / 1 ps + + +module IBUF_LVDS (O, I); + + output O; + + input I; + + buf B1 (O, I); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IBUF_LVPECL.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IBUF_LVPECL.v new file mode 100644 index 0000000..a67338f --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IBUF_LVPECL.v @@ -0,0 +1,33 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/IBUF_LVPECL.v,v 1.6 2007/05/23 21:43:35 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Input Buffer with LVPECL I/O Standard +// /___/ /\ Filename : IBUF_LVPECL.v +// \ \ / \ Timestamp : Thu Mar 25 16:42:35 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. + +`timescale 1 ps / 1 ps + + +module IBUF_LVPECL (O, I); + + output O; + + input I; + + buf B1 (O, I); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IBUF_LVTTL.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IBUF_LVTTL.v new file mode 100644 index 0000000..b204c2b --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IBUF_LVTTL.v @@ -0,0 +1,33 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/IBUF_LVTTL.v,v 1.6 2007/05/23 21:43:35 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Input Buffer with LVTTL I/O Standard +// /___/ /\ Filename : IBUF_LVTTL.v +// \ \ / \ Timestamp : Thu Mar 25 16:42:35 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. + +`timescale 1 ps / 1 ps + + +module IBUF_LVTTL (O, I); + + output O; + + input I; + + buf B1 (O, I); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IBUF_PCI33_3.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IBUF_PCI33_3.v new file mode 100644 index 0000000..89ee151 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IBUF_PCI33_3.v @@ -0,0 +1,33 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/IBUF_PCI33_3.v,v 1.6 2007/05/23 21:43:35 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Input Buffer with PCI33_3 I/O Standard +// /___/ /\ Filename : IBUF_PCI33_3.v +// \ \ / \ Timestamp : Thu Mar 25 16:42:35 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. + +`timescale 1 ps / 1 ps + + +module IBUF_PCI33_3 (O, I); + + output O; + + input I; + + buf B1 (O, I); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IBUF_PCI33_5.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IBUF_PCI33_5.v new file mode 100644 index 0000000..7aa14bc --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IBUF_PCI33_5.v @@ -0,0 +1,33 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/IBUF_PCI33_5.v,v 1.6 2007/05/23 21:43:35 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Input Buffer with PCI33_5 I/O Standard +// /___/ /\ Filename : IBUF_PCI33_5.v +// \ \ / \ Timestamp : Thu Mar 25 16:42:35 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. + +`timescale 1 ps / 1 ps + + +module IBUF_PCI33_5 (O, I); + + output O; + + input I; + + buf B1 (O, I); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IBUF_PCI66_3.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IBUF_PCI66_3.v new file mode 100644 index 0000000..80d2ba4 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IBUF_PCI66_3.v @@ -0,0 +1,33 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/IBUF_PCI66_3.v,v 1.6 2007/05/23 21:43:35 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Input Buffer with PCI66_3 I/O Standard +// /___/ /\ Filename : IBUF_PCI66_3.v +// \ \ / \ Timestamp : Thu Mar 25 16:42:35 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. + +`timescale 1 ps / 1 ps + + +module IBUF_PCI66_3 (O, I); + + output O; + + input I; + + buf B1 (O, I); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IBUF_PCIX.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IBUF_PCIX.v new file mode 100644 index 0000000..4c087e8 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IBUF_PCIX.v @@ -0,0 +1,33 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/IBUF_PCIX.v,v 1.6 2007/05/23 21:43:35 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Input Buffer with PCIX I/O Standard +// /___/ /\ Filename : IBUF_PCIX.v +// \ \ / \ Timestamp : Thu Mar 25 16:42:35 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. + +`timescale 1 ps / 1 ps + + +module IBUF_PCIX (O, I); + + output O; + + input I; + + buf B1 (O, I); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IBUF_PCIX66_3.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IBUF_PCIX66_3.v new file mode 100644 index 0000000..71e7dff --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IBUF_PCIX66_3.v @@ -0,0 +1,33 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/IBUF_PCIX66_3.v,v 1.6 2007/05/23 21:43:35 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Input Buffer with PCIX66_3 I/O Standard +// /___/ /\ Filename : IBUF_PCIX66_3.v +// \ \ / \ Timestamp : Thu Mar 25 16:42:35 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. + +`timescale 1 ps / 1 ps + + +module IBUF_PCIX66_3 (O, I); + + output O; + + input I; + + buf B1 (O, I); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IBUF_SSTL18_I.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IBUF_SSTL18_I.v new file mode 100644 index 0000000..c927479 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IBUF_SSTL18_I.v @@ -0,0 +1,33 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/IBUF_SSTL18_I.v,v 1.6 2007/05/23 21:43:36 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Input Buffer with SSTL18_I I/O Standard +// /___/ /\ Filename : IBUF_SSTL18_I.v +// \ \ / \ Timestamp : Thu Mar 25 16:42:36 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. + +`timescale 1 ps / 1 ps + + +module IBUF_SSTL18_I (O, I); + + output O; + + input I; + + buf B1 (O, I); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IBUF_SSTL18_II.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IBUF_SSTL18_II.v new file mode 100644 index 0000000..8eb9cd9 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IBUF_SSTL18_II.v @@ -0,0 +1,33 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/IBUF_SSTL18_II.v,v 1.6 2007/05/23 21:43:35 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Input Buffer with SSTL18_II I/O Standard +// /___/ /\ Filename : IBUF_SSTL18_II.v +// \ \ / \ Timestamp : Thu Mar 25 16:42:36 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. + +`timescale 1 ps / 1 ps + + +module IBUF_SSTL18_II (O, I); + + output O; + + input I; + + buf B1 (O, I); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IBUF_SSTL18_II_DCI.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IBUF_SSTL18_II_DCI.v new file mode 100644 index 0000000..a8eee61 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IBUF_SSTL18_II_DCI.v @@ -0,0 +1,33 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/IBUF_SSTL18_II_DCI.v,v 1.6 2007/05/23 21:43:35 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Input Buffer with SSTL18_II_DCI I/O Standard +// /___/ /\ Filename : IBUF_SSTL18_II_DCI.v +// \ \ / \ Timestamp : Thu Mar 25 16:42:36 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. + +`timescale 1 ps / 1 ps + + +module IBUF_SSTL18_II_DCI (O, I); + + output O; + + input I; + + buf B1 (O, I); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IBUF_SSTL18_I_DCI.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IBUF_SSTL18_I_DCI.v new file mode 100644 index 0000000..c7a9dd9 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IBUF_SSTL18_I_DCI.v @@ -0,0 +1,33 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/IBUF_SSTL18_I_DCI.v,v 1.6 2007/05/23 21:43:35 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Input Buffer with SSTL18_I_DCI I/O Standard +// /___/ /\ Filename : IBUF_SSTL18_I_DCI.v +// \ \ / \ Timestamp : Thu Mar 25 16:42:36 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. + +`timescale 1 ps / 1 ps + + +module IBUF_SSTL18_I_DCI (O, I); + + output O; + + input I; + + buf B1 (O, I); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IBUF_SSTL2_I.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IBUF_SSTL2_I.v new file mode 100644 index 0000000..4a29712 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IBUF_SSTL2_I.v @@ -0,0 +1,33 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/IBUF_SSTL2_I.v,v 1.6 2007/05/23 21:43:36 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Input Buffer with SSTL2_I I/O Standard +// /___/ /\ Filename : IBUF_SSTL2_I.v +// \ \ / \ Timestamp : Thu Mar 25 16:42:36 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. + +`timescale 1 ps / 1 ps + + +module IBUF_SSTL2_I (O, I); + + output O; + + input I; + + buf B1 (O, I); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IBUF_SSTL2_II.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IBUF_SSTL2_II.v new file mode 100644 index 0000000..5f018bf --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IBUF_SSTL2_II.v @@ -0,0 +1,33 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/IBUF_SSTL2_II.v,v 1.6 2007/05/23 21:43:36 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Input Buffer with SSTL2_II I/O Standard +// /___/ /\ Filename : IBUF_SSTL2_II.v +// \ \ / \ Timestamp : Thu Mar 25 16:42:36 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. + +`timescale 1 ps / 1 ps + + +module IBUF_SSTL2_II (O, I); + + output O; + + input I; + + buf B1 (O, I); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IBUF_SSTL2_II_DCI.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IBUF_SSTL2_II_DCI.v new file mode 100644 index 0000000..c2cbeb4 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IBUF_SSTL2_II_DCI.v @@ -0,0 +1,33 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/IBUF_SSTL2_II_DCI.v,v 1.6 2007/05/23 21:43:36 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Input Buffer with SSTL2_II_DCI I/O Standard +// /___/ /\ Filename : IBUF_SSTL2_II_DCI.v +// \ \ / \ Timestamp : Thu Mar 25 16:42:36 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. + +`timescale 1 ps / 1 ps + + +module IBUF_SSTL2_II_DCI (O, I); + + output O; + + input I; + + buf B1 (O, I); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IBUF_SSTL2_I_DCI.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IBUF_SSTL2_I_DCI.v new file mode 100644 index 0000000..135928f --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IBUF_SSTL2_I_DCI.v @@ -0,0 +1,33 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/IBUF_SSTL2_I_DCI.v,v 1.6 2007/05/23 21:43:36 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Input Buffer with SSTL2_I_DCI I/O Standard +// /___/ /\ Filename : IBUF_SSTL2_I_DCI.v +// \ \ / \ Timestamp : Thu Mar 25 16:42:36 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. + +`timescale 1 ps / 1 ps + + +module IBUF_SSTL2_I_DCI (O, I); + + output O; + + input I; + + buf B1 (O, I); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IBUF_SSTL3_I.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IBUF_SSTL3_I.v new file mode 100644 index 0000000..f94a999 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IBUF_SSTL3_I.v @@ -0,0 +1,33 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/IBUF_SSTL3_I.v,v 1.6 2007/05/23 21:43:36 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Input Buffer with SSTL3_I I/O Standard +// /___/ /\ Filename : IBUF_SSTL3_I.v +// \ \ / \ Timestamp : Thu Mar 25 16:42:36 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. + +`timescale 1 ps / 1 ps + + +module IBUF_SSTL3_I (O, I); + + output O; + + input I; + + buf B1 (O, I); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IBUF_SSTL3_II.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IBUF_SSTL3_II.v new file mode 100644 index 0000000..baabcd3 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IBUF_SSTL3_II.v @@ -0,0 +1,33 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/IBUF_SSTL3_II.v,v 1.6 2007/05/23 21:43:36 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Input Buffer with SSTL3_II I/O Standard +// /___/ /\ Filename : IBUF_SSTL3_II.v +// \ \ / \ Timestamp : Thu Mar 25 16:42:36 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. + +`timescale 1 ps / 1 ps + + +module IBUF_SSTL3_II (O, I); + + output O; + + input I; + + buf B1 (O, I); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IBUF_SSTL3_II_DCI.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IBUF_SSTL3_II_DCI.v new file mode 100644 index 0000000..ad7d1fa --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IBUF_SSTL3_II_DCI.v @@ -0,0 +1,33 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/IBUF_SSTL3_II_DCI.v,v 1.6 2007/05/23 21:43:36 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Input Buffer with SSTL3_II_DCI I/O Standard +// /___/ /\ Filename : IBUF_SSTL3_II_DCI.v +// \ \ / \ Timestamp : Thu Mar 25 16:42:37 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. + +`timescale 1 ps / 1 ps + + +module IBUF_SSTL3_II_DCI (O, I); + + output O; + + input I; + + buf B1 (O, I); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IBUF_SSTL3_I_DCI.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IBUF_SSTL3_I_DCI.v new file mode 100644 index 0000000..d023620 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IBUF_SSTL3_I_DCI.v @@ -0,0 +1,33 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/IBUF_SSTL3_I_DCI.v,v 1.6 2007/05/23 21:43:36 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Input Buffer with SSTL3_I_DCI I/O Standard +// /___/ /\ Filename : IBUF_SSTL3_I_DCI.v +// \ \ / \ Timestamp : Thu Mar 25 16:42:37 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. + +`timescale 1 ps / 1 ps + + +module IBUF_SSTL3_I_DCI (O, I); + + output O; + + input I; + + buf B1 (O, I); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/ICAP_SPARTAN3A.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/ICAP_SPARTAN3A.v new file mode 100644 index 0000000..af76d50 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/ICAP_SPARTAN3A.v @@ -0,0 +1,30 @@ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Internal Configuration Access Port for Spartan3a +// /___/ /\ Filename : ICAP_SPARTAN3A.v +// \ \ / \ Timestamp : Wed Jul 6 18:29:19 PDT 2005 +// \___\/\___\ +// +// Revision: +// 07/06/05 - Initial version. + +`timescale 1 ps / 1 ps + + +module ICAP_SPARTAN3A (BUSY, O, CE, CLK, I, WRITE); + + output BUSY; + output [7:0] O; + + input CE, CLK, WRITE; + input [7:0] I; + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/ICAP_SPARTAN6.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/ICAP_SPARTAN6.v new file mode 100644 index 0000000..94c4ac2 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/ICAP_SPARTAN6.v @@ -0,0 +1,226 @@ +/////////////////////////////////////////////////////// +// Copyright (c) 1995/2006 Xilinx Inc. +// All Right Reserved. +/////////////////////////////////////////////////////// +// +// ____ ___ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : +// / / +// /__/ /\ Filename : ICAP_SPARTAN6.v +// \ \ / \ +// \__\/\__ \ +// +// Revision: 1.0 +// 07/08/09 - Set BUSY to 1 during icap initial (CR525847) +// 09/17/09 - Remove DCMLOCK pin for SIM_CONFIG (CR530867) +// 10/09/09 - Add initialzion message and check (CR525847) +// 12/17/09 - Allow ICAP use without RBT file (CR537437) +// 03/02/10 - Support desync when icap initial done (CR551856) +// 03/17/10 - Create internal clock for icap initializtion to +// reduce initializtion time (CR554252) +/////////////////////////////////////////////////////// + +`timescale 1 ps / 1 ps + +module ICAP_SPARTAN6 ( + BUSY, + O, + CE, + CLK, + I, + WRITE +); + parameter DEVICE_ID = 32'h02000093; + + parameter SIM_CFG_FILE_NAME = "NONE"; + + output BUSY; + output [15:0] O; + + input CLK; + input CE; + input WRITE; + input [15:0] I; + + wire cso_b; + reg prog_b; + reg init_b; + wire busy_out; + reg cs_bi = 0; + reg rdwr_bi = 0; + wire cs_b_t; + wire clk_in; + wire rdwr_b_t; + wire [15:0] dix; + reg [7:0] tmp_byte0; + reg [7:0] tmp_byte1; + reg [15:0] di; + reg [15:0] data_rbt; + reg [800:0] data_rbt_s; + reg icap_idone = 0; + reg clk_osc = 0; + reg sim_file_flag; + wire csi_b_in; + integer icap_fd; + reg lcnt; + reg notifier; + wire CLK; + wire WRITE; + wire CE; + + tri1 p_up; + tri (weak1, strong0) done_o = p_up; + tri (pull1, supply0) [15:0] di_t = (icap_idone == 1 && WRITE == 1)? 16'bz : dix; + + assign csi_b_in = CE; + assign dix = (icap_idone == 1) ? I : di; + assign BUSY = (icap_idone == 1) ? busy_out : 1; + assign cs_b_t = (icap_idone == 1) ? csi_b_in : cs_bi; + assign clk_in = (icap_idone == 1) ? CLK : clk_osc; + assign rdwr_b_t = (icap_idone == 1) ? WRITE : rdwr_bi; + assign O = (icap_idone == 1 && WRITE == 1) ? di_t : 16'b0; + + always +// if (icap_idone == 0) + #1000 clk_osc <= ~clk_osc; + + always @(CE or WRITE) + if ($time > 1 && icap_idone == 0) begin + $display (" Warning : ICAP_SPARTAN6 on instance %m at time %t has not finished initialization. A message will be printed after the initialization. User need start read/write operation after that.", $time); + end + + SIM_CONFIG_S6 #( + .DEVICE_ID(DEVICE_ID), + .ICAP_SUPPORT("TRUE") + ) + SIM_CONFIG_S6_INST ( + .BUSY(busy_out), + .CSOB(cso_b), + .DONE(done_o), + .CCLK(clk_in), + .CSIB(cs_b_t), + .D(di_t), + .INITB(init_tri), + .M(2'b10), + .PROGB(prog_b), + .RDWRB(rdwr_b_t) + ); + + initial begin + icap_idone = 0; + sim_file_flag = 0; + if (SIM_CFG_FILE_NAME == "NONE") begin + // $display(" Error: The configure rbt data file for ICAP_SPARTAN6 instance %m was not found. Use the SIM_CFG_FILE_NAME parameter to pass the file name.\n"); + sim_file_flag = 1; + end + else begin + icap_fd = $fopen(SIM_CFG_FILE_NAME, "r"); + if (icap_fd == 0) + begin + $display(" Error: The configure rbt data file %s for ICAP_SPARTAN6 instance %m was not found. Use the SIM_CFG_FILE_NAME parameter to pass the file name.\n", SIM_CFG_FILE_NAME); + sim_file_flag = 1; + end + end + + init_b = 1; + prog_b = 1; + rdwr_bi = 0; + cs_bi = 1; + #600000; + @(posedge clk_in) + prog_b = 0; + @(negedge clk_in) + init_b = 0; + #600000; + @(posedge clk_in) + prog_b = 1; + @(negedge clk_in) begin + init_b = 1; + cs_bi = 0; + end + if (sim_file_flag == 0) begin +// lcnt = $fgets(data_rbt_s, icap_fd); +// lcnt = $fgets(data_rbt_s, icap_fd); +// lcnt = $fgets(data_rbt_s, icap_fd); +// lcnt = $fgets(data_rbt_s, icap_fd); +// lcnt = $fgets(data_rbt_s, icap_fd); +// lcnt = $fgets(data_rbt_s, icap_fd); +// lcnt = $fgets(data_rbt_s, icap_fd); + while ($fscanf(icap_fd, "%b", data_rbt) != -1) begin + if (done_o == 0) begin + tmp_byte1 = bit_revers8(data_rbt[15:8]); + tmp_byte0 = bit_revers8(data_rbt[7:0]); + @(negedge clk_in) + di = {tmp_byte1, tmp_byte0}; + end + else begin + @(negedge clk_in); + di = 16'hFFFF; + @(negedge clk_in); + @(negedge clk_in); + @(negedge clk_in); + @(negedge clk_in); + @(negedge clk_in); + if (icap_idone == 0) begin + $display (" Message: ICAP_SPARTAN6 on instance %m at time %t has finished initialization. User can start read/write operation.", $time); + icap_idone = 1; + end + end + end + $fclose(icap_fd); + #1000; + end + else begin + @(negedge clk_in) + di = 16'hFFFF; + @(negedge clk_in) + di = 16'hFFFF; + @(negedge clk_in) + di = 16'hFFFF; + @(negedge clk_in) + di = 16'hFFFF; + @(negedge clk_in) + di = 16'h5599; // AA99 + @(negedge clk_in) + di = 16'hAA66; // 5566 + @(negedge clk_in) + di = 16'hFFFF; + @(negedge clk_in) + di = 16'hFFFF; + @(negedge clk_in) + di = 16'h0C85; + @(negedge clk_in) + di = 16'h00A0; + @(negedge clk_in); + @(negedge clk_in); + @(negedge clk_in); + @(negedge clk_in); + @(negedge clk_in); + @(negedge clk_in); + if (icap_idone == 0) begin + $display (" Message: ICAP_SPARTAN6 on instance %m at time %t has finished initialization. User can start read/write operation.", $time); + icap_idone = 1; + end + #1000; + end + end + + function [7:0] bit_revers8; + input [7:0] din8; + begin + bit_revers8[0] = din8[7]; + bit_revers8[1] = din8[6]; + bit_revers8[2] = din8[5]; + bit_revers8[3] = din8[4]; + bit_revers8[4] = din8[3]; + bit_revers8[5] = din8[2]; + bit_revers8[6] = din8[1]; + bit_revers8[7] = din8[0]; + end + endfunction + + +endmodule diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/ICAP_VIRTEX4.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/ICAP_VIRTEX4.v new file mode 100644 index 0000000..2626d81 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/ICAP_VIRTEX4.v @@ -0,0 +1,36 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/virtex4/ICAP_VIRTEX4.v,v 1.4 2007/06/06 22:14:07 fphillip Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Internal Configuration Access Port for Virtex4 +// /___/ /\ Filename : ICAP_VIRTEX4.v +// \ \ / \ Timestamp : Thu Mar 25 16:43:51 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 06/06/07 - Fixed timescale values +// End Revision + + +`timescale 1 ps / 1 ps + + +module ICAP_VIRTEX4 (BUSY, O, CE, CLK, I, WRITE); + + output BUSY; + output [31:0] O; + + input CE, CLK, WRITE; + input [31:0] I; + + parameter ICAP_WIDTH = "X8"; + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/ICAP_VIRTEX5.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/ICAP_VIRTEX5.v new file mode 100644 index 0000000..a38fecf --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/ICAP_VIRTEX5.v @@ -0,0 +1,57 @@ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Internal Configuration Access Port for Virtex5 +// /___/ /\ Filename : ICAP_VIRTEX5.v +// \ \ / \ Timestamp : Thu Jul 21 13:42:30 PDT 2005 +// \___\/\___\ +// +// Revision: +// 07/21/05 - Initial version. +// End Revision + +`timescale 1 ps / 1 ps + +module ICAP_VIRTEX5 ( + BUSY, + O, + CE, + CLK, + I, + WRITE +); + +output BUSY; +output [31:0] O; + +input CE; +input CLK; +input WRITE; +input [31:0] I; + +parameter ICAP_WIDTH = "X8"; + +initial begin + case (ICAP_WIDTH) + "X8" , "X16", "X32" : ; + default : begin + $display("Attribute Syntax Error : The Attribute ICAP_WIDTH on ICAP_VIRTEX5 instance %m is set to %s. Legal values for this attribute are X8, X16 or X32.", ICAP_WIDTH); + $finish; + end + endcase + +end + + + +specify + specparam PATHPULSE$ = 0; +endspecify + +endmodule diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/ICAP_VIRTEX6.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/ICAP_VIRTEX6.v new file mode 100644 index 0000000..afb9c43 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/ICAP_VIRTEX6.v @@ -0,0 +1,299 @@ +/////////////////////////////////////////////////////// +// Copyright (c) 1995/2006 Xilinx Inc. +// All Right Reserved. +/////////////////////////////////////////////////////// +// +// ____ ___ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : +// / / +// /__/ /\ Filename : ICAP_VIRTEX6.v +// \ \ / \ +// \__\/\__ \ +// +// Revision: +// 04/22/09 - Initial version. +// 07/08/09 - Set BUSY to 1 during icap initial (CR525847) +// 09/17/09 - Remove DCMLOCK pin for SIM_CONFIG (CR530867) +// 10/09/09 - Add initialzion message and check (CR525847) +// 12/17/09 - Allow ICAP use without RBT file (CR537437) +// 03/02/10 - Support desync when icap initial done (CR551856) +// 03/17/10 - Create internal clock for icap initializtion to +// reduce initializtion time (CR554252) +/////////////////////////////////////////////////////// + +`timescale 1 ps / 1 ps + +module ICAP_VIRTEX6 ( + BUSY, + O, + CLK, + CSB, + I, + RDWRB +); + parameter [31:0] DEVICE_ID = 32'h04244093; + + parameter ICAP_WIDTH = "X8"; + parameter SIM_CFG_FILE_NAME = "NONE"; + + output BUSY; + output [31:0] O; + + input CLK; + input CSB; + input RDWRB; + input [31:0] I; + + wire cso_b; + reg prog_b; + reg init_b; + reg [3:0] bw = 4'b0000; + wire busy_out; + reg cs_bi = 0, rdwr_bi = 0; + wire cs_b_t; + wire clk_in; + wire rdwr_b_t; + wire [31:0] dix; + reg [31:0] di; + reg [31:0] data_rbt; + reg [7:0] tmp_byte0; + reg [7:0] tmp_byte1; + reg [7:0] tmp_byte2; + reg [7:0] tmp_byte3; + reg icap_idone = 0; + reg clk_osc = 0; + reg sim_file_flag; + integer icap_fd; + reg notifier; + wire CLK; + wire CSB; + wire RDWRB; + + tri1 p_up; + tri init_tri = (icap_idone == 0) ? init_b : p_up; + tri (weak1, strong0) done_o = p_up; + tri (pull1, supply0) [31:0] di_t = (icap_idone == 1 && RDWRB == 1)? 32'bz : dix; + + assign dix = (icap_idone == 1) ? I : di; + assign BUSY = (icap_idone == 1) ? busy_out : 1; + assign cs_b_t = (icap_idone == 1) ? CSB : cs_bi; + assign clk_in = (icap_idone == 1) ? CLK : clk_osc; + assign rdwr_b_t = (icap_idone == 1) ? RDWRB : rdwr_bi; + assign O = (icap_idone == 1 && RDWRB == 1) ? di_t : 32'b0; + + always +// if (icap_idone == 0) + #1000 clk_osc <= ~clk_osc; + + always @(CSB or RDWRB) + if ($time > 1 && icap_idone == 0) begin + $display (" Warning : ICAP_VIRTEX6 on instance %m at time %t has not finished initialization. A message will be printed after the initialization. User need start read/write operation after that.", $time); + end + + + SIM_CONFIG_V6 #( + .DEVICE_ID(DEVICE_ID), + .ICAP_SUPPORT("TRUE"), + .ICAP_WIDTH(ICAP_WIDTH) + ) + SIM_CONFIG_V6_INST ( + .BUSY(busy_out), + .CSOB(cso_b), + .DONE(done_o), + .CCLK(clk_in), + .CSB(cs_b_t), + .D(di_t), + .INITB(init_tri), + .M(3'b110), + .PROGB(prog_b), + .RDWRB(rdwr_b_t) + ); + + + initial begin + + case (ICAP_WIDTH) + "X8" : bw = 4'b0000; + "X16" : bw = 4'b0010; + "X32" : bw = 4'b0011; + default : begin + $display("Attribute Syntax Error : The Attribute ICAP_WIDTH on ICAP_VIRTEX6 instance %m is set to %s. Legal values for this attribute are X8, X16 or X32.", ICAP_WIDTH); + end + endcase + + icap_idone = 0; + sim_file_flag = 0; + if (SIM_CFG_FILE_NAME == "NONE") begin +// $display(" Error: The configure rbt data file for ICAP_VIRTEX6 instance %m was not found. Use the SIM_CFG_FILE_NAME parameter to pass the file name.\n"); + sim_file_flag = 1; + end + else begin + icap_fd = $fopen(SIM_CFG_FILE_NAME, "r"); + if (icap_fd == 0) + begin + $display(" Error: The configure rbt data file %s for ICAP_VIRTEX6 instance %m was not found. Use the SIM_CFG_FILE_NAME parameter to pass the file name.\n", SIM_CFG_FILE_NAME); + sim_file_flag = 1; + end + end + + init_b = 1; + prog_b = 1; + rdwr_bi = 0; + cs_bi = 1; + #600000; + @(posedge clk_in) + prog_b = 0; + @(negedge clk_in) + init_b = 0; + #600000; + @(posedge clk_in) + prog_b = 1; + @(negedge clk_in) begin + init_b = 1; + cs_bi = 0; + end + if (sim_file_flag == 0) begin + while ($fscanf(icap_fd, "%b", data_rbt) != -1) begin + if (done_o == 0) begin + tmp_byte3 = bit_revers8(data_rbt[31:24]); + tmp_byte2 = bit_revers8(data_rbt[23:16]); + tmp_byte1 = bit_revers8(data_rbt[15:8]); + tmp_byte0 = bit_revers8(data_rbt[7:0]); + if (bw == 4'b0000) begin + @(negedge clk_in) + di = {24'b0, tmp_byte3}; + @(negedge clk_in) + di = {24'b0, tmp_byte2}; + @(negedge clk_in) + di = {24'b0, tmp_byte1}; + @(negedge clk_in) + di = {24'b0, tmp_byte0}; + end + else if (bw == 4'b0010) begin + @(negedge clk_in) + di = {16'b0, tmp_byte3, tmp_byte2}; + @(negedge clk_in) + di = {16'b0, tmp_byte1, tmp_byte0}; + end + else if (bw == 4'b0011) begin + @(negedge clk_in) + di = {tmp_byte3, tmp_byte2, tmp_byte1, tmp_byte0}; + end + end + else begin + @(negedge clk_in); + di = 32'hFFFFFFFF; + @(negedge clk_in); + @(negedge clk_in); + @(negedge clk_in); + if (icap_idone == 0) begin + $display (" Message: ICAP_VIRTEX6 on instance %m at time %t has finished initialization. User can start read/write operation.", $time); + icap_idone = 1; + end + end + end + $fclose(icap_fd); + #1000; + end + else begin + @(negedge clk_in) + di = 32'hFFFFFFFF; + @(negedge clk_in) + di = 32'hFFFFFFFF; + @(negedge clk_in) + di = 32'hFFFFFFFF; + @(negedge clk_in) + di = 32'hFFFFFFFF; + @(negedge clk_in) + di = 32'hFFFFFFFF; + @(negedge clk_in) + di = 32'hFFFFFFFF; + @(negedge clk_in) + di = 32'hFFFFFFFF; + @(negedge clk_in) + di = 32'hFFFFFFFF; + @(negedge clk_in) + di = 32'hFFFFFFFF; + @(negedge clk_in) + di = 32'h000000DD; + @(negedge clk_in) begin + if (bw == 4'b0000) + di = 32'h00000088; + else if (bw == 4'b0010) + di = 32'h00000044; + else if (bw == 4'b0011) + di = 32'h00000022; + end + rbt_data_wr(32'hFFFFFFFF); + rbt_data_wr(32'hFFFFFFFF); + rbt_data_wr(32'hAA995566); + rbt_data_wr(32'h30008001); + rbt_data_wr(32'h00000005); + @(negedge clk_in); + @(negedge clk_in); + @(negedge clk_in); + @(negedge clk_in); + @(negedge clk_in); + @(negedge clk_in); + if (icap_idone == 0) begin + $display (" Message: ICAP_VIRTEX6 on instance %m at time %t has finished initialization. User can start read/write operation.", $time); + icap_idone = 1; + end + #1000; + end + end + + + task rbt_data_wr; + input [31:0] dat_rbt; + reg [7:0] tp_byte3; + reg [7:0] tp_byte2; + reg [7:0] tp_byte1; + reg [7:0] tp_byte0; + begin + tp_byte3 = bit_revers8(dat_rbt[31:24]); + tp_byte2 = bit_revers8(dat_rbt[23:16]); + tp_byte1 = bit_revers8(dat_rbt[15:8]); + tp_byte0 = bit_revers8(dat_rbt[7:0]); + if (bw == 4'b0000) begin + @(negedge clk_in) + di = {24'b0, tp_byte3}; + @(negedge clk_in) + di = {24'b0, tp_byte2}; + @(negedge clk_in) + di = {24'b0, tp_byte1}; + @(negedge clk_in) + di = {24'b0, tp_byte0}; + end + else if (bw == 4'b0010) begin + @(negedge clk_in) + di = {16'b0, tp_byte3, tp_byte2}; + @(negedge clk_in) + di = {16'b0, tp_byte1, tp_byte0}; + end + else if (bw == 4'b0011) begin + @(negedge clk_in) + di = {tp_byte3, tp_byte2, tp_byte1, tp_byte0}; + end + end + endtask + + function [7:0] bit_revers8; + input [7:0] din8; + begin + bit_revers8[0] = din8[7]; + bit_revers8[1] = din8[6]; + bit_revers8[2] = din8[5]; + bit_revers8[3] = din8[4]; + bit_revers8[4] = din8[3]; + bit_revers8[5] = din8[2]; + bit_revers8[6] = din8[1]; + bit_revers8[7] = din8[0]; + end + endfunction + + +endmodule diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IDDR.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IDDR.v new file mode 100644 index 0000000..ed6cb4a --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IDDR.v @@ -0,0 +1,188 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/virtex4/IDDR.v,v 1.9 2008/12/03 23:49:31 fphillip Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2005 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Dual Data Rate Input D Flip-Flop +// /___/ /\ Filename : IDDR.v +// \ \ / \ Timestamp : Thu Mar 11 16:43:51 PST 2005 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 03/11/05 - Initialized outpus. +// 04/28/06 - Added c_in into the sensitivity list (CR 219840). +// 05/29/07 - Added wire declaration for internal signals +// 12/03/08 - CR 498674 added pulldown on R/S. +// End Revision + +`timescale 1 ps / 1 ps + +module IDDR (Q1, Q2, C, CE, D, R, S); + + output Q1; + output Q2; + + input C; + input CE; + input D; + tri0 GSR = glbl.GSR; + input R; + input S; + + parameter DDR_CLK_EDGE = "OPPOSITE_EDGE"; + parameter INIT_Q1 = 1'b0; + parameter INIT_Q2 = 1'b0; + parameter SRTYPE = "SYNC"; + + pulldown P1 (R); + pulldown P2 (S); + + reg q1_out = INIT_Q1, q2_out = INIT_Q2; + reg q1_out_int, q2_out_int; + reg q1_out_pipelined, q2_out_same_edge_int; + + + wire c_in; + wire ce_in; + wire d_in; + wire gsr_in; + wire r_in; + wire s_in; + + buf buf_c (c_in, C); + buf buf_ce (ce_in, CE); + buf buf_d (d_in, D); + buf buf_gsr (gsr_in, GSR); + buf buf_q1 (Q1, q1_out); + buf buf_q2 (Q2, q2_out); + buf buf_r (r_in, R); + buf buf_s (s_in, S); + + initial begin + + if ((INIT_Q1 != 0) && (INIT_Q1 != 1)) begin + $display("Attribute Syntax Error : The attribute INIT_Q1 on IDDR instance %m is set to %d. Legal values for this attribute are 0 or 1.", INIT_Q1); + $finish; + end + + if ((INIT_Q2 != 0) && (INIT_Q2 != 1)) begin + $display("Attribute Syntax Error : The attribute INIT_Q1 on IDDR instance %m is set to %d. Legal values for this attribute are 0 or 1.", INIT_Q2); + $finish; + end + + if ((DDR_CLK_EDGE != "OPPOSITE_EDGE") && (DDR_CLK_EDGE != "SAME_EDGE") && (DDR_CLK_EDGE != "SAME_EDGE_PIPELINED")) begin + $display("Attribute Syntax Error : The attribute DDR_CLK_EDGE on IDDR instance %m is set to %s. Legal values for this attribute are OPPOSITE_EDGE, SAME_EDGE or SAME_EDGE_PIPELINED.", DDR_CLK_EDGE); + $finish; + end + + if ((SRTYPE != "ASYNC") && (SRTYPE != "SYNC")) begin + $display("Attribute Syntax Error : The attribute SRTYPE on IDDR instance %m is set to %s. Legal values for this attribute are ASYNC or SYNC.", SRTYPE); + $finish; + end + + end // initial begin + + + always @(gsr_in or r_in or s_in) begin + if (gsr_in == 1'b1) begin + assign q1_out_int = INIT_Q1; + assign q1_out_pipelined = INIT_Q1; + assign q2_out_same_edge_int = INIT_Q2; + assign q2_out_int = INIT_Q2; + end + else if (gsr_in == 1'b0) begin + if (r_in == 1'b1 && SRTYPE == "ASYNC") begin + assign q1_out_int = 1'b0; + assign q1_out_pipelined = 1'b0; + assign q2_out_same_edge_int = 1'b0; + assign q2_out_int = 1'b0; + end + else if (r_in == 1'b0 && s_in == 1'b1 && SRTYPE == "ASYNC") begin + assign q1_out_int = 1'b1; + assign q1_out_pipelined = 1'b1; + assign q2_out_same_edge_int = 1'b1; + assign q2_out_int = 1'b1; + end + else if ((r_in == 1'b1 || s_in == 1'b1) && SRTYPE == "SYNC") begin + deassign q1_out_int; + deassign q1_out_pipelined; + deassign q2_out_same_edge_int; + deassign q2_out_int; + end + else if (r_in == 1'b0 && s_in == 1'b0) begin + deassign q1_out_int; + deassign q1_out_pipelined; + deassign q2_out_same_edge_int; + deassign q2_out_int; + end + end // if (gsr_in == 1'b0) + end // always @ (gsr_in or r_in or s_in) + + + always @(posedge c_in) begin + if (r_in == 1'b1) begin + q1_out_int <= 1'b0; + q1_out_pipelined <= 1'b0; + q2_out_same_edge_int <= 1'b0; + end + else if (r_in == 1'b0 && s_in == 1'b1) begin + q1_out_int <= 1'b1; + q1_out_pipelined <= 1'b1; + q2_out_same_edge_int <= 1'b1; + end + else if (ce_in == 1'b1 && r_in == 1'b0 && s_in == 1'b0) begin + q1_out_int <= d_in; + q1_out_pipelined <= q1_out_int; + q2_out_same_edge_int <= q2_out_int; + end + end // always @ (posedge c_in) + + + always @(negedge c_in) begin + if (r_in == 1'b1) + q2_out_int <= 1'b0; + else if (r_in == 1'b0 && s_in == 1'b1) + q2_out_int <= 1'b1; + else if (ce_in == 1'b1 && r_in == 1'b0 && s_in == 1'b0) + q2_out_int <= d_in; + end + + + always @(c_in or q1_out_int or q2_out_int or q2_out_same_edge_int or q1_out_pipelined) begin + case (DDR_CLK_EDGE) + "OPPOSITE_EDGE" : begin + q1_out <= q1_out_int; + q2_out <= q2_out_int; + end + "SAME_EDGE" : begin + q1_out <= q1_out_int; + q2_out <= q2_out_same_edge_int; + end + "SAME_EDGE_PIPELINED" : begin + q1_out <= q1_out_pipelined; + q2_out <= q2_out_same_edge_int; + end + default : begin + $display("Attribute Syntax Error : The attribute DDR_CLK_EDGE on IDDR instance %m is set to %s. Legal values for this attribute are OPPOSITE_EDGE, SAME_EDGE or SAME_EDGE_PIPELINED.", DDR_CLK_EDGE); + $finish; + end + endcase // case(DDR_CLK_EDGE) + end // always @ (q1_out_int or q2_out_int or q2_out_same_edge_int or q1_out_pipelined or q2_out_pipelined) + + + specify + + (C => Q1) = (100, 100); + (C => Q2) = (100, 100); + specparam PATHPULSE$ = 0; + + endspecify + +endmodule // IDDR + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IDDR2.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IDDR2.v new file mode 100644 index 0000000..f1a0b0e --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IDDR2.v @@ -0,0 +1,181 @@ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Dual Data Rate Input D Flip-Flop +// /___/ /\ Filename : IDDR2.v +// \ \ / \ Timestamp : Thu Mar 25 16:43:51 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 08/20/08 - CR 478850 added pulldown on R/S and pullup on CE. +// 04/08/09 - CR 517973 Reworked to matched Holistic tests +// 01/12/10 - CR 538181 Fixed R/S to take INIT values +// 05/04/10 - CR 558177 revert the above CR. Holistic tests are failing +// End Revision + + +`timescale 1 ps / 1 ps + +module IDDR2 (Q0, Q1, C0, C1, CE, D, R, S); + + output Q0; + output Q1; + + input C0; + input C1; + input CE; + input D; + tri0 GSR = glbl.GSR; + input R; + input S; + + parameter DDR_ALIGNMENT = "NONE"; + parameter INIT_Q0 = 1'b0; + parameter INIT_Q1 = 1'b0; + parameter SRTYPE = "SYNC"; + + pullup P1 (CE); + pulldown P2 (R); + pulldown P3 (S); + + reg q0_out, q1_out; + reg q0_out_int, q1_out_int; + reg q0_c0_out_int, q1_c0_out_int; + + wire PC0, PC1; + + buf buf_q0 (Q0, q0_out); + buf buf_q1 (Q1, q1_out); + + + initial begin + + if ((INIT_Q0 != 1'b0) && (INIT_Q0 != 1'b1)) begin + $display("Attribute Syntax Error : The attribute INIT_Q0 on IDDR2 instance %m is set to %d. Legal values for this attribute are 0 or 1.", INIT_Q0); + $finish; + end + + if ((INIT_Q1 != 1'b0) && (INIT_Q1 != 1'b1)) begin + $display("Attribute Syntax Error : The attribute INIT_Q0 on IDDR2 instance %m is set to %d. Legal values for this attribute are 0 or 1.", INIT_Q1); + $finish; + end + + if ((DDR_ALIGNMENT != "C1") && (DDR_ALIGNMENT != "C0") && (DDR_ALIGNMENT != "NONE")) begin + $display("Attribute Syntax Error : The attribute DDR_ALIGNMENT on IDDR2 instance %m is set to %s. Legal values for this attribute are C0, C1 or NONE.", DDR_ALIGNMENT); + $finish; + end + + if ((SRTYPE != "ASYNC") && (SRTYPE != "SYNC")) begin + $display("Attribute Syntax Error : The attribute SRTYPE on IDDR2 instance %m is set to %s. Legal values for this attribute are ASYNC or SYNC.", SRTYPE); + $finish; + end + + end // initial begin + + assign PC0 = ((DDR_ALIGNMENT== "C0") || (DDR_ALIGNMENT== "NONE"))? C0 : C1; + assign PC1 = ((DDR_ALIGNMENT== "C0") || (DDR_ALIGNMENT== "NONE"))? C1 : C0; + + always @(GSR or R or S) begin + + if (GSR == 1) begin + + assign q0_out_int = INIT_Q0; + assign q1_out_int = INIT_Q1; + assign q0_c0_out_int = INIT_Q0; + assign q1_c0_out_int = INIT_Q1; + + end + else begin + + deassign q0_out_int; + deassign q1_out_int; + deassign q0_c0_out_int; + deassign q1_c0_out_int; + + if (SRTYPE == "ASYNC") begin + if (R == 1) begin + assign q0_out_int = 0; + assign q1_out_int = 0; + assign q0_c0_out_int = 0; + assign q1_c0_out_int = 0; + end + else if (R == 0 && S == 1) begin + assign q0_out_int = 1; + assign q1_out_int = 1; + end + end // if (SRTYPE == "ASYNC") + + end // if (GSR == 1'b0) + + end // always @ (GSR or R or S) + + + always @(posedge PC0) begin + if (R == 1 && SRTYPE == "SYNC") begin + q0_out_int <= 0; + q0_c0_out_int <= 0; + q1_c0_out_int <= 0; + end + else if (R == 0 && S == 1 && SRTYPE == "SYNC") begin + q0_out_int <= 1; + end + else if (CE == 1 && R == 0 && S == 0) begin + q0_out_int <= D; + q0_c0_out_int <= q0_out_int; + q1_c0_out_int <= q1_out_int; + end + end // always @ (posedge PC0) + + + always @(posedge PC1) begin + if (R == 1 && SRTYPE == "SYNC") begin + q1_out_int <= 0; + end + else if (R == 0 && S == 1 && SRTYPE == "SYNC") begin + q1_out_int <= 1; + end + else if (CE == 1 && R == 0 && S == 0) begin + q1_out_int <= D; + end + end // always @ (posedge PC1) + + + always @(q0_out_int or q1_out_int or q1_c0_out_int or q0_c0_out_int) begin + + case (DDR_ALIGNMENT) + "NONE" : begin + q0_out <= q0_out_int; + q1_out <= q1_out_int; + end + "C0" : begin + q0_out <= q0_out_int; + q1_out <= q1_c0_out_int; + end + "C1" : begin + q0_out <= q0_out_int; + q1_out <= q1_c0_out_int; + end + endcase // case(DDR_ALIGNMENT) + + end // always @ (q0_out_int or q1_out_int or q1_c0_out_int or q0_c0_out_int) + + + specify + + if (C0) (C0 => Q0) = (100, 100); + if (C0) (C0 => Q1) = (100, 100); + if (C1) (C1 => Q1) = (100, 100); + if (C1) (C1 => Q0) = (100, 100); + specparam PATHPULSE$ = 0; + + endspecify + +endmodule // IDDR2 + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IDDR_2CLK.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IDDR_2CLK.v new file mode 100644 index 0000000..10baede --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IDDR_2CLK.v @@ -0,0 +1,188 @@ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2006 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Input Dual Data-Rate Register with Dual Clock inputs +// /___/ /\ Filename : IDDR_2CLK.v +// \ \ / \ Timestamp : Mon Jun 26 16:44:06 PST 2006 +// \___\/\___\ +// +// Revision: +// 06/26/06 - Initial version. +// 05/29/07 - Added wire declaration for internal signals +// 04/15/08 - CR 468871 Negative SetupHold fix +// 02/17/10 - CR 548313 VCS Negative Setup check hangs when input buffers are present +// End Revision + +`timescale 1 ps / 1 ps + +module IDDR_2CLK (Q1, Q2, C, CB, CE, D, R, S); + + parameter DDR_CLK_EDGE = "OPPOSITE_EDGE"; + parameter INIT_Q1 = 1'b0; + parameter INIT_Q2 = 1'b0; + parameter SRTYPE = "SYNC"; + + output Q1; + output Q2; + + input C; + input CB; + input CE; + input D; + input R; + input S; + + reg q1_out = INIT_Q1, q2_out = INIT_Q2; + reg q1_out_int, q2_out_int; + reg q1_out_pipelined, q2_out_same_edge_int; + reg notifier, notifier1, notifier2; + + wire c_in; + wire cb_in; + wire ce_in; + wire d_in; + wire gsr_in; + wire r_in; + wire s_in; + + tri0 GSR = glbl.GSR; + + buf buf_q1 (Q1, q1_out); + buf buf_q2 (Q2, q2_out); + + assign c_in = C; + assign cb_in = CB; + assign ce_in = CE; + assign d_in = D; + assign gsr_in = GSR; + assign r_in = R; + assign s_in = S; + + initial begin + + if ((INIT_Q1 != 0) && (INIT_Q1 != 1)) begin + $display("Attribute Syntax Error : The attribute INIT_Q1 on IDDR_2CLK instance %m is set to %d. Legal values for this attribute are 0 or 1.", INIT_Q1); + $finish; + end + + if ((INIT_Q2 != 0) && (INIT_Q2 != 1)) begin + $display("Attribute Syntax Error : The attribute INIT_Q1 on IDDR_2CLK instance %m is set to %d. Legal values for this attribute are 0 or 1.", INIT_Q2); + $finish; + end + + if ((DDR_CLK_EDGE != "OPPOSITE_EDGE") && (DDR_CLK_EDGE != "SAME_EDGE") && (DDR_CLK_EDGE != "SAME_EDGE_PIPELINED")) begin + $display("Attribute Syntax Error : The attribute DDR_CLK_EDGE on IDDR_2CLK instance %m is set to %s. Legal values for this attribute are OPPOSITE_EDGE, SAME_EDGE or SAME_EDGE_PIPELINED.", DDR_CLK_EDGE); + $finish; + end + + if ((SRTYPE != "ASYNC") && (SRTYPE != "SYNC")) begin + $display("Attribute Syntax Error : The attribute SRTYPE on IDDR_2CLK instance %m is set to %s. Legal values for this attribute are ASYNC or SYNC.", SRTYPE); + $finish; + end + + end // initial begin + + + always @(gsr_in or r_in or s_in) begin + if (gsr_in == 1'b1) begin + assign q1_out_int = INIT_Q1; + assign q1_out_pipelined = INIT_Q1; + assign q2_out_same_edge_int = INIT_Q2; + assign q2_out_int = INIT_Q2; + end + else if (gsr_in == 1'b0) begin + if (r_in == 1'b1 && SRTYPE == "ASYNC") begin + assign q1_out_int = 1'b0; + assign q1_out_pipelined = 1'b0; + assign q2_out_same_edge_int = 1'b0; + assign q2_out_int = 1'b0; + end + else if (r_in == 1'b0 && s_in == 1'b1 && SRTYPE == "ASYNC") begin + assign q1_out_int = 1'b1; + assign q1_out_pipelined = 1'b1; + assign q2_out_same_edge_int = 1'b1; + assign q2_out_int = 1'b1; + end + else if ((r_in == 1'b1 || s_in == 1'b1) && SRTYPE == "SYNC") begin + deassign q1_out_int; + deassign q1_out_pipelined; + deassign q2_out_same_edge_int; + deassign q2_out_int; + end + else if (r_in == 1'b0 && s_in == 1'b0) begin + deassign q1_out_int; + deassign q1_out_pipelined; + deassign q2_out_same_edge_int; + deassign q2_out_int; + end + end // if (gsr_in == 1'b0) + end // always @ (gsr_in or r_in or s_in) + + + always @(posedge c_in) begin + if (r_in == 1'b1) begin + q1_out_int <= 1'b0; + q1_out_pipelined <= 1'b0; + q2_out_same_edge_int <= 1'b0; + end + else if (r_in == 1'b0 && s_in == 1'b1) begin + q1_out_int <= 1'b1; + q1_out_pipelined <= 1'b1; + q2_out_same_edge_int <= 1'b1; + end + else if (ce_in == 1'b1 && r_in == 1'b0 && s_in == 1'b0) begin + q1_out_int <= d_in; + q1_out_pipelined <= q1_out_int; + q2_out_same_edge_int <= q2_out_int; + end + end // always @ (posedge c_in) + + + always @(posedge cb_in) begin + if (r_in == 1'b1) + q2_out_int <= 1'b0; + else if (r_in == 1'b0 && s_in == 1'b1) + q2_out_int <= 1'b1; + else if (ce_in == 1'b1 && r_in == 1'b0 && s_in == 1'b0) + q2_out_int <= d_in; + end // always @ (posedge cb_in) + + + always @(posedge c_in or posedge cb_in, q1_out_int or q2_out_int or q2_out_same_edge_int or q1_out_pipelined) begin + case (DDR_CLK_EDGE) + "OPPOSITE_EDGE" : begin + q1_out <= q1_out_int; + q2_out <= q2_out_int; + end + "SAME_EDGE" : begin + q1_out <= q1_out_int; + q2_out <= q2_out_same_edge_int; + end + "SAME_EDGE_PIPELINED" : begin + q1_out <= q1_out_pipelined; + q2_out <= q2_out_same_edge_int; + end + default : begin + $display("Attribute Syntax Error : The attribute DDR_CLK_EDGE on IDDR_2CLK instance %m is set to %s. Legal values for this attribute are OPPOSITE_EDGE, SAME_EDGE or SAME_EDGE_PIPELINED.", DDR_CLK_EDGE); + $finish; + end + endcase // case(DDR_CLK_EDGE) + end // always @ (q1_out_int or q2_out_int or q2_out_same_edge_int or q1_out_pipelined or q2_out_pipelined) + + specify + + (C => Q1) = (100, 100); + (C => Q2) = (100, 100); + (CB => Q1) = (100, 100); + (CB => Q2) = (100, 100); + specparam PATHPULSE$ = 0; + + endspecify + +endmodule // IDDR_2CLK diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IDELAY.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IDELAY.v new file mode 100644 index 0000000..4e547c8 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IDELAY.v @@ -0,0 +1,303 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/virtex4/IDELAY.v,v 1.10 2007/06/08 01:59:04 fphillip Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2005 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Input Delay Line +// /___/ /\ Filename : IDELAY.v +// \ \ / \ Timestamp : Thu Mar 11 16:43:51 PST 2005 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 03/11/05 - Initialized outpus. +// 03/18/05 - Changed SIM_TAPDELAY_VALUE to 75 from 78. +// 05/29/07 - Added wire declaration for internal signals +// End Revision + +`timescale 1 ps / 1 ps + +module IDELAY (O, C, CE, I, INC, RST); + + output O; + + input C; + input CE; + tri0 GSR = glbl.GSR; + input I; + input INC; + input RST; + + parameter IOBDELAY_TYPE = "DEFAULT"; + parameter integer IOBDELAY_VALUE = 0; + + reg o_out = 0; + integer delay_count; + + wire delay_chain_0, delay_chain_1, delay_chain_2, delay_chain_3, + delay_chain_4, delay_chain_5, delay_chain_6, delay_chain_7, + delay_chain_8, delay_chain_9, delay_chain_10, delay_chain_11, + delay_chain_12, delay_chain_13, delay_chain_14, delay_chain_15, + delay_chain_16, delay_chain_17, delay_chain_18, delay_chain_19, + delay_chain_20, delay_chain_21, delay_chain_22, delay_chain_23, + delay_chain_24, delay_chain_25, delay_chain_26, delay_chain_27, + delay_chain_28, delay_chain_29, delay_chain_30, delay_chain_31, + delay_chain_32, delay_chain_33, delay_chain_34, delay_chain_35, + delay_chain_36, delay_chain_37, delay_chain_38, delay_chain_39, + delay_chain_40, delay_chain_41, delay_chain_42, delay_chain_43, + delay_chain_44, delay_chain_45, delay_chain_46, delay_chain_47, + delay_chain_48, delay_chain_49, delay_chain_50, delay_chain_51, + delay_chain_52, delay_chain_53, delay_chain_54, delay_chain_55, + delay_chain_56, delay_chain_57, delay_chain_58, delay_chain_59, + delay_chain_60, delay_chain_61, delay_chain_62, delay_chain_63; + + wire c_in; + wire ce_in; + wire gsr_in; + wire i_in; + wire inc_in; + wire rst_in; + + buf buf_c (c_in, C); + buf buf_ce (ce_in, CE); + buf buf_gsr (gsr_in, GSR); + buf buf_i (i_in, I); + buf buf_inc (inc_in, INC); + buf buf_rst (rst_in, RST); + buf buf_o (O, o_out); + + localparam SIM_TAPDELAY_VALUE = 75; + +// GSR + always @(gsr_in) + + if (gsr_in == 1'b1) begin + + if (IOBDELAY_TYPE == "DEFAULT") + + assign delay_count = 0; + + else + + assign delay_count = IOBDELAY_VALUE; + + end + else if (gsr_in == 1'b0) begin + + deassign delay_count; + + end + + + + initial begin + + if (IOBDELAY_VALUE < 0 || IOBDELAY_VALUE > 63) begin + + $display("Attribute Syntax Error : The attribute IOBDELAY_VALUE on IDELAY instance %m is set to %d. Legal values for this attribute are 0, 1, 2, 3, .... or 63", IOBDELAY_VALUE); + $finish; + + end + + + if (IOBDELAY_TYPE != "DEFAULT" && IOBDELAY_TYPE != "FIXED" && IOBDELAY_TYPE != "VARIABLE") begin + + $display("Attribute Syntax Error : The attribute IOBDELAY_TYPE on IDELAY instance %m is set to %s. Legal values for this attribute are DEFAULT, FIXED or VARIABLE", IOBDELAY_TYPE); + $finish; + + end + + end // initial begin + + + + always @(posedge c_in) begin + + if (IOBDELAY_TYPE == "VARIABLE") begin + + if (rst_in == 1'b1) + delay_count = IOBDELAY_VALUE; + + else if (rst_in == 1'b0 && ce_in == 1'b1) begin + + if (inc_in == 1'b1) begin + + if (delay_count < 63) + + delay_count = delay_count + 1; + + else if (delay_count == 63) + + delay_count = 0; + + end + else if (inc_in == 1'b0) begin + + if (delay_count > 0) + + delay_count = delay_count - 1; + + else if (delay_count == 0) + + delay_count = 63; + end + + end + + end // if (IOBDELAY_TYPE == "VARIABLE") + + end // always @ (posedge clkdiv_in) + + +// delay chain + assign delay_chain_0 = i_in; + assign #SIM_TAPDELAY_VALUE delay_chain_1 = delay_chain_0; + assign #SIM_TAPDELAY_VALUE delay_chain_2 = delay_chain_1; + assign #SIM_TAPDELAY_VALUE delay_chain_3 = delay_chain_2; + assign #SIM_TAPDELAY_VALUE delay_chain_4 = delay_chain_3; + assign #SIM_TAPDELAY_VALUE delay_chain_5 = delay_chain_4; + assign #SIM_TAPDELAY_VALUE delay_chain_6 = delay_chain_5; + assign #SIM_TAPDELAY_VALUE delay_chain_7 = delay_chain_6; + assign #SIM_TAPDELAY_VALUE delay_chain_8 = delay_chain_7; + assign #SIM_TAPDELAY_VALUE delay_chain_9 = delay_chain_8; + assign #SIM_TAPDELAY_VALUE delay_chain_10 = delay_chain_9; + assign #SIM_TAPDELAY_VALUE delay_chain_11 = delay_chain_10; + assign #SIM_TAPDELAY_VALUE delay_chain_12 = delay_chain_11; + assign #SIM_TAPDELAY_VALUE delay_chain_13 = delay_chain_12; + assign #SIM_TAPDELAY_VALUE delay_chain_14 = delay_chain_13; + assign #SIM_TAPDELAY_VALUE delay_chain_15 = delay_chain_14; + assign #SIM_TAPDELAY_VALUE delay_chain_16 = delay_chain_15; + assign #SIM_TAPDELAY_VALUE delay_chain_17 = delay_chain_16; + assign #SIM_TAPDELAY_VALUE delay_chain_18 = delay_chain_17; + assign #SIM_TAPDELAY_VALUE delay_chain_19 = delay_chain_18; + assign #SIM_TAPDELAY_VALUE delay_chain_20 = delay_chain_19; + assign #SIM_TAPDELAY_VALUE delay_chain_21 = delay_chain_20; + assign #SIM_TAPDELAY_VALUE delay_chain_22 = delay_chain_21; + assign #SIM_TAPDELAY_VALUE delay_chain_23 = delay_chain_22; + assign #SIM_TAPDELAY_VALUE delay_chain_24 = delay_chain_23; + assign #SIM_TAPDELAY_VALUE delay_chain_25 = delay_chain_24; + assign #SIM_TAPDELAY_VALUE delay_chain_26 = delay_chain_25; + assign #SIM_TAPDELAY_VALUE delay_chain_27 = delay_chain_26; + assign #SIM_TAPDELAY_VALUE delay_chain_28 = delay_chain_27; + assign #SIM_TAPDELAY_VALUE delay_chain_29 = delay_chain_28; + assign #SIM_TAPDELAY_VALUE delay_chain_30 = delay_chain_29; + assign #SIM_TAPDELAY_VALUE delay_chain_31 = delay_chain_30; + assign #SIM_TAPDELAY_VALUE delay_chain_32 = delay_chain_31; + assign #SIM_TAPDELAY_VALUE delay_chain_33 = delay_chain_32; + assign #SIM_TAPDELAY_VALUE delay_chain_34 = delay_chain_33; + assign #SIM_TAPDELAY_VALUE delay_chain_35 = delay_chain_34; + assign #SIM_TAPDELAY_VALUE delay_chain_36 = delay_chain_35; + assign #SIM_TAPDELAY_VALUE delay_chain_37 = delay_chain_36; + assign #SIM_TAPDELAY_VALUE delay_chain_38 = delay_chain_37; + assign #SIM_TAPDELAY_VALUE delay_chain_39 = delay_chain_38; + assign #SIM_TAPDELAY_VALUE delay_chain_40 = delay_chain_39; + assign #SIM_TAPDELAY_VALUE delay_chain_41 = delay_chain_40; + assign #SIM_TAPDELAY_VALUE delay_chain_42 = delay_chain_41; + assign #SIM_TAPDELAY_VALUE delay_chain_43 = delay_chain_42; + assign #SIM_TAPDELAY_VALUE delay_chain_44 = delay_chain_43; + assign #SIM_TAPDELAY_VALUE delay_chain_45 = delay_chain_44; + assign #SIM_TAPDELAY_VALUE delay_chain_46 = delay_chain_45; + assign #SIM_TAPDELAY_VALUE delay_chain_47 = delay_chain_46; + assign #SIM_TAPDELAY_VALUE delay_chain_48 = delay_chain_47; + assign #SIM_TAPDELAY_VALUE delay_chain_49 = delay_chain_48; + assign #SIM_TAPDELAY_VALUE delay_chain_50 = delay_chain_49; + assign #SIM_TAPDELAY_VALUE delay_chain_51 = delay_chain_50; + assign #SIM_TAPDELAY_VALUE delay_chain_52 = delay_chain_51; + assign #SIM_TAPDELAY_VALUE delay_chain_53 = delay_chain_52; + assign #SIM_TAPDELAY_VALUE delay_chain_54 = delay_chain_53; + assign #SIM_TAPDELAY_VALUE delay_chain_55 = delay_chain_54; + assign #SIM_TAPDELAY_VALUE delay_chain_56 = delay_chain_55; + assign #SIM_TAPDELAY_VALUE delay_chain_57 = delay_chain_56; + assign #SIM_TAPDELAY_VALUE delay_chain_58 = delay_chain_57; + assign #SIM_TAPDELAY_VALUE delay_chain_59 = delay_chain_58; + assign #SIM_TAPDELAY_VALUE delay_chain_60 = delay_chain_59; + assign #SIM_TAPDELAY_VALUE delay_chain_61 = delay_chain_60; + assign #SIM_TAPDELAY_VALUE delay_chain_62 = delay_chain_61; + assign #SIM_TAPDELAY_VALUE delay_chain_63 = delay_chain_62; + + +// assign delay + always @(delay_count) begin + + case (delay_count) + 0: assign o_out = delay_chain_0; + 1: assign o_out = delay_chain_1; + 2: assign o_out = delay_chain_2; + 3: assign o_out = delay_chain_3; + 4: assign o_out = delay_chain_4; + 5: assign o_out = delay_chain_5; + 6: assign o_out = delay_chain_6; + 7: assign o_out = delay_chain_7; + 8: assign o_out = delay_chain_8; + 9: assign o_out = delay_chain_9; + 10: assign o_out = delay_chain_10; + 11: assign o_out = delay_chain_11; + 12: assign o_out = delay_chain_12; + 13: assign o_out = delay_chain_13; + 14: assign o_out = delay_chain_14; + 15: assign o_out = delay_chain_15; + 16: assign o_out = delay_chain_16; + 17: assign o_out = delay_chain_17; + 18: assign o_out = delay_chain_18; + 19: assign o_out = delay_chain_19; + 20: assign o_out = delay_chain_20; + 21: assign o_out = delay_chain_21; + 22: assign o_out = delay_chain_22; + 23: assign o_out = delay_chain_23; + 24: assign o_out = delay_chain_24; + 25: assign o_out = delay_chain_25; + 26: assign o_out = delay_chain_26; + 27: assign o_out = delay_chain_27; + 28: assign o_out = delay_chain_28; + 29: assign o_out = delay_chain_29; + 30: assign o_out = delay_chain_30; + 31: assign o_out = delay_chain_31; + 32: assign o_out = delay_chain_32; + 33: assign o_out = delay_chain_33; + 34: assign o_out = delay_chain_34; + 35: assign o_out = delay_chain_35; + 36: assign o_out = delay_chain_36; + 37: assign o_out = delay_chain_37; + 38: assign o_out = delay_chain_38; + 39: assign o_out = delay_chain_39; + 40: assign o_out = delay_chain_40; + 41: assign o_out = delay_chain_41; + 42: assign o_out = delay_chain_42; + 43: assign o_out = delay_chain_43; + 44: assign o_out = delay_chain_44; + 45: assign o_out = delay_chain_45; + 46: assign o_out = delay_chain_46; + 47: assign o_out = delay_chain_47; + 48: assign o_out = delay_chain_48; + 49: assign o_out = delay_chain_49; + 50: assign o_out = delay_chain_50; + 51: assign o_out = delay_chain_51; + 52: assign o_out = delay_chain_52; + 53: assign o_out = delay_chain_53; + 54: assign o_out = delay_chain_54; + 55: assign o_out = delay_chain_55; + 56: assign o_out = delay_chain_56; + 57: assign o_out = delay_chain_57; + 58: assign o_out = delay_chain_58; + 59: assign o_out = delay_chain_59; + 60: assign o_out = delay_chain_60; + 61: assign o_out = delay_chain_61; + 62: assign o_out = delay_chain_62; + 63: assign o_out = delay_chain_63; + default: + assign o_out = delay_chain_0; + + endcase + end // always @ (delay_count) + + + +endmodule // IDELAY + + + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IDELAYCTRL.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IDELAYCTRL.v new file mode 100644 index 0000000..676bebd --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IDELAYCTRL.v @@ -0,0 +1,125 @@ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2005 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Input Delay Controller +// /___/ /\ Filename : IDELAYCTRL.v +// \ \ / \ Timestamp : Thu Mar 11 16:43:51 PST 2005 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 03/11/05 - Initialized outpus. +// 07/23/07 - Initialized outpus. +// 04/10/07 - CR 436682 fix, disable activity when rst is high + +// End Revision + +`timescale 1 ps / 1 ps + +module IDELAYCTRL (RDY, REFCLK, RST); + + output RDY; + + input REFCLK; + input RST; + + wire refclk_in; + wire rst_in; + + time clock_edge; + reg [63:0] period; + reg clock_low, clock_high; + reg clock_posedge, clock_negedge; + reg lost, rdy_out = 0; + + buf b_rdy (RDY, rdy_out); + buf b_refclk (refclk_in, REFCLK); + buf b_rst (rst_in, RST); + + + always @(rst_in, lost) begin + + if ((rst_in == 1'b1) || (lost == 1)) + + rdy_out <= 1'b0; + + else if (rst_in == 1'b0 && lost == 0) + + rdy_out <= 1'b1; + + end + + +/* + always @(posedge lost) begin + + rdy_out <= 1'b0; + + end +*/ + + initial begin + clock_edge <= 0; + clock_high <= 0; + clock_low <= 0; + lost <= 1; + period <= 0; + end + + + always @(posedge refclk_in) begin + if(rst_in == 1'b0) begin + clock_edge <= $time; + if (period != 0 && (($time - clock_edge) <= (1.5 * period))) + period <= $time - clock_edge; + else if (period != 0 && (($time - clock_edge) > (1.5 * period))) + period <= 0; + else if ((period == 0) && (clock_edge != 0)) + period <= $time - clock_edge; + end + end + + always @(posedge refclk_in) begin + clock_low <= 1'b0; + clock_high <= 1'b1; + if (period != 0) + lost <= 1'b0; + clock_posedge <= 1'b0; + #((period * 9.1) / 10) + if ((clock_low != 1'b1) && (clock_posedge != 1'b1)) + lost <= 1; + end + + always @(posedge refclk_in) begin + clock_negedge <= 1'b1; + end + + always @(negedge refclk_in) begin + clock_posedge <= 1'b1; + end + + always @(negedge refclk_in) begin + clock_high <= 1'b0; + clock_low <= 1'b1; + if (period != 0) + lost <= 1'b0; + clock_negedge <= 1'b0; + #((period * 9.1) / 10) + if ((clock_high != 1'b1) && (clock_negedge != 1'b1)) + lost <= 1; + end + + specify + + (REFCLK => RDY) = (100, 100); + specparam PATHPULSE$ = 0; + + endspecify + +endmodule // IDELAYCTRL diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IFDDRCPE.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IFDDRCPE.v new file mode 100644 index 0000000..89a1fe1 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IFDDRCPE.v @@ -0,0 +1,49 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/IFDDRCPE.v,v 1.4 2005/03/14 22:32:53 yanx Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Dual Data Rate Input D Flip-Flop with Asynchronous Clear and Preset and Clock Enable +// /___/ /\ Filename : IFDDRCPE.v +// \ \ / \ Timestamp : Thu Mar 25 16:42:37 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// End Revision + +`timescale 1 ps / 1 ps + +module IFDDRCPE (Q0, Q1, C0, C1, CE, CLR, D, PRE); + + output Q0, Q1; + + input C0, C1, CE, CLR, D, PRE; + + wire d_in; + + IBUF I1 (.I(D), + .O(d_in)); + + FDCPE F0 (.C(C0), + .CE(CE), + .CLR(CLR), + .D(d_in), + .PRE(PRE), + .Q(Q0)); + defparam F0.INIT = 1'b0; + + FDCPE F1 (.C(C1), + .CE(CE), + .CLR(CLR), + .D(d_in), + .PRE(PRE), + .Q(Q1)); + defparam F1.INIT = 1'b0; + +endmodule diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IFDDRRSE.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IFDDRRSE.v new file mode 100644 index 0000000..9020cc8 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IFDDRRSE.v @@ -0,0 +1,49 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/IFDDRRSE.v,v 1.4 2005/03/14 22:32:53 yanx Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Dual Data Rate Input D Flip-Flop with Synchronous Reset and SET and Clock Enable +// /___/ /\ Filename : IFDDRRSE.v +// \ \ / \ Timestamp : Thu Mar 25 16:42:37 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// End Revision + +`timescale 1 ps / 1 ps + +module IFDDRRSE (Q0, Q1, C0, C1, CE, D, R, S); + + output Q0, Q1; + + input C0, C1, CE, D, R, S; + + wire d_in; + + IBUF I1 (.I(D), + .O(d_in)); + + FDRSE F0 (.C(C0), + .CE(CE), + .R(R), + .D(d_in), + .S(S), + .Q(Q0)); + defparam F0.INIT = 1'b0; + + FDRSE F1 (.C(C1), + .CE(CE), + .R(R), + .D(d_in), + .S(S), + .Q(Q1)); + defparam F1.INIT = "0"; + +endmodule diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/INV.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/INV.v new file mode 100644 index 0000000..9d3a5ee --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/INV.v @@ -0,0 +1,32 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/INV.v,v 1.6 2007/05/23 21:43:36 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Inverter +// /___/ /\ Filename : INV.v +// \ \ / \ Timestamp : Thu Mar 25 16:42:37 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. + +`timescale 1 ps / 1 ps + + +module INV (O, I); + + output O; + + input I; + + not N1 (O, I); + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IOBUF.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IOBUF.v new file mode 100644 index 0000000..51f92e8 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IOBUF.v @@ -0,0 +1,96 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/IOBUF.v,v 1.11 2009/08/21 23:55:43 harikr Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Bi-Directional Buffer +// /___/ /\ Filename : IOBUF.v +// \ \ / \ Timestamp : Thu Mar 25 16:42:37 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 02/22/06 - CR#226003 - Added integer, real parameter type +// 05/23/07 - Changed timescale to 1 ps / 1 ps. +// 05/23/07 - Added wire declaration for internal signals. +// 07/16/08 - Added IBUF_LOW_PWR attribute. +// 04/22/09 - CR 519127 - Changed IBUF_LOW_PWR default to TRUE. +// End Revision + +`timescale 1 ps / 1 ps + + +module IOBUF (O, IO, I, T); + + parameter CAPACITANCE = "DONT_CARE"; + parameter integer DRIVE = 12; + parameter IBUF_DELAY_VALUE = "0"; + parameter IBUF_LOW_PWR = "TRUE"; + parameter IFD_DELAY_VALUE = "AUTO"; + parameter IOSTANDARD = "DEFAULT"; + parameter SLEW = "SLOW"; + + output O; + inout IO; + input I, T; + + wire ts; + + tri0 GTS = glbl.GTS; + + or O1 (ts, GTS, T); + bufif0 T1 (IO, I, ts); + + buf B1 (O, IO); + + initial begin + + case (CAPACITANCE) + + "LOW", "NORMAL", "DONT_CARE" : ; + default : begin + $display("Attribute Syntax Error : The attribute CAPACITANCE on IOBUF instance %m is set to %s. Legal values for this attribute are DONT_CARE, LOW or NORMAL.", CAPACITANCE); + $finish; + end + + endcase + + case (IBUF_DELAY_VALUE) + + "0", "1", "2", "3", "4", "5", "6", "7", "8", "9", "10", "11", "12", "13", "14", "15", "16" : ; + default : begin + $display("Attribute Syntax Error : The attribute IBUF_DELAY_VALUE on IOBUF instance %m is set to %s. Legal values for this attribute are 0, 1, 2, ... or 16.", IBUF_DELAY_VALUE); + $finish; + end + + endcase + + case (IBUF_LOW_PWR) + + "FALSE", "TRUE" : ; + default : begin + $display("Attribute Syntax Error : The attribute IBUF_LOW_PWR on IBUF instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", IBUF_LOW_PWR); + $finish; + end + + endcase + + case (IFD_DELAY_VALUE) + + "AUTO", "0", "1", "2", "3", "4", "5", "6", "7", "8" : ; + default : begin + $display("Attribute Syntax Error : The attribute IFD_DELAY_VALUE on IOBUF instance %m is set to %s. Legal values for this attribute are AUTO, 0, 1, 2, ... or 8.", IFD_DELAY_VALUE); + $finish; + end + + endcase + + end // initial begin + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IOBUFDS.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IOBUFDS.v new file mode 100644 index 0000000..94edb25 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IOBUFDS.v @@ -0,0 +1,125 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/IOBUFDS.v,v 1.13.46.1 2010/05/12 23:22:19 fphillip Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / 3-State Diffential Signaling I/O Buffer +// /___/ /\ Filename : IOBUFDS.v +// \ \ / \ Timestamp : Thu Mar 25 16:42:37 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. +// 05/23/07 - Added wire declaration for internal signals. +// 07/26/07 - Add else to handle x case for o_out (CR 424214). +// 07/16/08 - Added IBUF_LOW_PWR attribute. +// 03/19/09 - CR 511590 - Added Z condition handling +// 04/22/09 - CR 519127 - Changed IBUF_LOW_PWR default to TRUE. +// 10/14/09 - CR 535630 - Added DIFF_TERM attribute. +// 05/12/10 - CR 559468 - Added DRC warnings for LVDS_25 bus architectures. +// End Revision + +`timescale 1 ps / 1 ps + + +module IOBUFDS (O, IO, IOB, I, T); + + parameter CAPACITANCE = "DONT_CARE"; + parameter DIFF_TERM = "FALSE"; + parameter IBUF_DELAY_VALUE = "0"; + parameter IBUF_LOW_PWR = "TRUE"; + parameter IFD_DELAY_VALUE = "AUTO"; + parameter IOSTANDARD = "DEFAULT"; + + output O; + inout IO, IOB; + input I, T; + + wire ts; + + tri0 GTS = glbl.GTS; + + reg O; + + or O1 (ts, GTS, T); + bufif0 B1 (IO, I, ts); + notif0 N1 (IOB, I, ts); + + + initial begin + + case (DIFF_TERM) + + "TRUE", "FALSE" : ; + default : begin + $display("Attribute Syntax Error : The attribute DIFF_TERM on IOBUFDS instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", DIFF_TERM); + $finish; + end + + endcase // case(DIFF_TERM) + + + case (CAPACITANCE) + + "LOW", "NORMAL", "DONT_CARE" : ; + default : begin + $display("Attribute Syntax Error : The attribute CAPACITANCE on IOBUFDS instance %m is set to %s. Legal values for this attribute are DONT_CARE, LOW or NORMAL.", CAPACITANCE); + $finish; + end + + endcase + + + case (IBUF_DELAY_VALUE) + + "0", "1", "2", "3", "4", "5", "6", "7", "8", "9", "10", "11", "12", "13", "14", "15", "16" : ; + default : begin + $display("Attribute Syntax Error : The attribute IBUF_DELAY_VALUE on IOBUFDS instance %m is set to %s. Legal values for this attribute are 0, 1, 2, ... or 16.", IBUF_DELAY_VALUE); + $finish; + end + + endcase + + case (IBUF_LOW_PWR) + + "FALSE", "TRUE" : ; + default : begin + $display("Attribute Syntax Error : The attribute IBUF_LOW_PWR on IBUF instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", IBUF_LOW_PWR); + $finish; + end + + endcase + + case (IFD_DELAY_VALUE) + + "AUTO", "0", "1", "2", "3", "4", "5", "6", "7", "8" : ; + default : begin + $display("Attribute Syntax Error : The attribute IFD_DELAY_VALUE on IOBUFDS instance %m is set to %s. Legal values for this attribute are AUTO, 0, 1, 2, ... or 8.", IFD_DELAY_VALUE); + $finish; + end + + endcase + + if((IOSTANDARD == "LVDS_25") || (IOSTANDARD == "LVDSEXT_25")) begin + $display("DRC Warning : The IOSTANDARD attribute on IOBUFDS instance %m is set to %s. LVDS_25 is a fixed impedance structure optimized to 100ohm differential. If the intended usage is a bus architecture, please use BLVDS. This is only intended to be used in point to point transmissions that do not have turn around timing requirements", IOSTANDARD); + end + + end + + + always @(IO or IOB) begin + if (IO == 1'b1 && IOB == 1'b0) + O <= IO; + else if (IO == 1'b0 && IOB == 1'b1) + O <= IO; + else if (IO == 1'bx || IO == 1'bz || IOB == 1'bx || IOB == 1'bz) + O = 1'bx; + end + +endmodule diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IOBUFDS_BLVDS_25.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IOBUFDS_BLVDS_25.v new file mode 100644 index 0000000..0464831 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IOBUFDS_BLVDS_25.v @@ -0,0 +1,53 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/IOBUFDS_BLVDS_25.v,v 1.8 2008/05/15 21:26:52 fphillip Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / 3-State Differential Signaling I/O Buffer with BLVDS_25 I/O Standard +// /___/ /\ Filename : IOBUFDS_BLVDS_25.v +// \ \ / \ Timestamp : Thu Mar 25 16:42:37 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. +// 05/23/07 - Added wire declaration for internal signals. +// 05/13/08 - CR 458290 -- Added else condition to handle x case. +// End Revision + + +`timescale 1 ps / 1 ps + + +module IOBUFDS_BLVDS_25 (O, IO, IOB, I, T); + + output O; + inout IO, IOB; + input I, T; + + wire ts; + + tri0 GTS = glbl.GTS; + + reg O; + + or O1 (ts, GTS, T); + bufif0 B1 (IO, I, ts); + notif0 N1 (IOB, I, ts); + + always @(IO or IOB) begin + if (IO == 1'b1 && IOB == 1'b0) + O <= IO; + else if (IO == 1'b0 && IOB == 1'b1) + O <= IO; + else if (IO == 1'bx || IOB == 1'bx) + O <= 1'bx; + + end + +endmodule diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IOBUFDS_DIFF_OUT.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IOBUFDS_DIFF_OUT.v new file mode 100644 index 0000000..57ac96d --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IOBUFDS_DIFF_OUT.v @@ -0,0 +1,89 @@ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / 3-State Diffential Signaling I/O Buffer +// /___/ /\ Filename : IOBUFDS_DIFF_OUT.v +// \ \ / \ Timestamp : Mon Jan 19 10:23:13 PST 2009 +// \___\/\___\ +// +// Revision: +// 01/19/09 - Initial version. +// 01/28/09 - Reflected RC's feedback. +// 06/02/09 - CR 523083 -- Added attribute IBUF_LOW_PWR. +// End Revision + +`timescale 1 ps / 1 ps + + +module IOBUFDS_DIFF_OUT (O, OB, IO, IOB, I, TM, TS); + + parameter DIFF_TERM = "FALSE"; + parameter IBUF_LOW_PWR = "TRUE"; + parameter IOSTANDARD = "DEFAULT"; + + output O; + output OB; + inout IO; + inout IOB; + input I; + input TM; + input TS; + + wire t1, t2; + + tri0 GTS = glbl.GTS; + + reg O, OB; + + or O1 (t1, GTS, TM); + bufif0 B1 (IO, I, t1); + + or O2 (t2, GTS, TS); + notif0 N2 (IOB, I, t2); + + initial begin + + case (DIFF_TERM) + + "TRUE", "FALSE" : ; + default : begin + $display("Attribute Syntax Error : The attribute DIFF_TERM on IOBUFDS_DIFF_OUT instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", DIFF_TERM); + $finish; + end + + endcase // case(DIFF_TERM) + case (IBUF_LOW_PWR) + + "FALSE", "TRUE" : ; + default : begin + $display("Attribute Syntax Error : The attribute IBUF_LOW_PWR on IOBUFDS_DIFF_OUT instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", IBUF_LOW_PWR); + $finish; + end + + endcase + + end + + + always @(IO or IOB) begin + if (IO == 1'b1 && IOB == 1'b0) begin + O = IO; + OB = ~IO; + end + else if (IO == 1'b0 && IOB == 1'b1) begin + O = IO; + OB = ~IO; + end + else begin + O = 1'bx; + OB = 1'bx; + end + end + +endmodule diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IOBUF_AGP.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IOBUF_AGP.v new file mode 100644 index 0000000..4d205db --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IOBUF_AGP.v @@ -0,0 +1,43 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/IOBUF_AGP.v,v 1.6 2007/05/23 21:43:36 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Bi-Directional Buffer with AGP I/O Standard +// /___/ /\ Filename : IOBUF_AGP.v +// \ \ / \ Timestamp : Thu Mar 25 16:42:38 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. +// 05/23/07 - Added wire declaration for internal signals. + +`timescale 1 ps / 1 ps + + +module IOBUF_AGP (O, IO, I, T); + + output O; + + inout IO; + + input I, T; + + wire ts; + + tri0 GTS = glbl.GTS; + + or O1 (ts, GTS, T); + bufif0 T1 (IO, I, ts); + + buf B1 (O, IO); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IOBUF_CTT.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IOBUF_CTT.v new file mode 100644 index 0000000..1eca803 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IOBUF_CTT.v @@ -0,0 +1,43 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/IOBUF_CTT.v,v 1.6 2007/05/23 21:43:36 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Bi-Directional Buffer with CTT I/O Standard +// /___/ /\ Filename : IOBUF_CTT.v +// \ \ / \ Timestamp : Thu Mar 25 16:42:38 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. +// 05/23/07 - Added wire declaration for internal signals. + +`timescale 1 ps / 1 ps + + +module IOBUF_CTT (O, IO, I, T); + + output O; + + inout IO; + + input I, T; + + wire ts; + + tri0 GTS = glbl.GTS; + + or O1 (ts, GTS, T); + bufif0 T1 (IO, I, ts); + + buf B1 (O, IO); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IOBUF_F_12.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IOBUF_F_12.v new file mode 100644 index 0000000..e5e54bd --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IOBUF_F_12.v @@ -0,0 +1,43 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/IOBUF_F_12.v,v 1.6 2007/05/23 21:43:36 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Bi-Directional Buffer with Fast Slew 12 mA Drive +// /___/ /\ Filename : IOBUF_F_12.v +// \ \ / \ Timestamp : Thu Mar 25 16:42:38 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. +// 05/23/07 - Added wire declaration for internal signals. + +`timescale 1 ps / 1 ps + + +module IOBUF_F_12 (O, IO, I, T); + + output O; + + inout IO; + + input I, T; + + wire ts; + + tri0 GTS = glbl.GTS; + + or O1 (ts, GTS, T); + bufif0 T1 (IO, I, ts); + + buf B1 (O, IO); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IOBUF_F_16.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IOBUF_F_16.v new file mode 100644 index 0000000..1119ee5 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IOBUF_F_16.v @@ -0,0 +1,43 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/IOBUF_F_16.v,v 1.6 2007/05/23 21:43:36 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Bi-Directional Buffer with Fast Slew 16 mA Drive +// /___/ /\ Filename : IOBUF_F_16.v +// \ \ / \ Timestamp : Thu Mar 25 16:42:38 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. +// 05/23/07 - Added wire declaration for internal signals. + +`timescale 1 ps / 1 ps + + +module IOBUF_F_16 (O, IO, I, T); + + output O; + + inout IO; + + input I, T; + + wire ts; + + tri0 GTS = glbl.GTS; + + or O1 (ts, GTS, T); + bufif0 T1 (IO, I, ts); + + buf B1 (O, IO); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IOBUF_F_2.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IOBUF_F_2.v new file mode 100644 index 0000000..abffa43 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IOBUF_F_2.v @@ -0,0 +1,43 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/IOBUF_F_2.v,v 1.6 2007/05/23 21:43:36 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Bi-Directional Buffer with Fast Slew 2 mA Drive +// /___/ /\ Filename : IOBUF_F_2.v +// \ \ / \ Timestamp : Thu Mar 25 16:42:38 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. +// 05/23/07 - Added wire declaration for internal signals. + +`timescale 1 ps / 1 ps + + +module IOBUF_F_2 (O, IO, I, T); + + output O; + + inout IO; + + input I, T; + + wire ts; + + tri0 GTS = glbl.GTS; + + or O1 (ts, GTS, T); + bufif0 T1 (IO, I, ts); + + buf B1 (O, IO); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IOBUF_F_24.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IOBUF_F_24.v new file mode 100644 index 0000000..a82fb4a --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IOBUF_F_24.v @@ -0,0 +1,43 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/IOBUF_F_24.v,v 1.6 2007/05/23 21:43:36 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Bi-Directional Buffer with Fast Slew 24 mA Drive +// /___/ /\ Filename : IOBUF_F_24.v +// \ \ / \ Timestamp : Thu Mar 25 16:42:38 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. +// 05/23/07 - Added wire declaration for internal signals. + +`timescale 1 ps / 1 ps + + +module IOBUF_F_24 (O, IO, I, T); + + output O; + + inout IO; + + input I, T; + + wire ts; + + tri0 GTS = glbl.GTS; + + or O1 (ts, GTS, T); + bufif0 T1 (IO, I, ts); + + buf B1 (O, IO); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IOBUF_F_4.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IOBUF_F_4.v new file mode 100644 index 0000000..0ddab3c --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IOBUF_F_4.v @@ -0,0 +1,43 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/IOBUF_F_4.v,v 1.6 2007/05/23 21:43:36 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Bi-Directional Buffer with Fast Slew 4 mA Drive +// /___/ /\ Filename : IOBUF_F_4.v +// \ \ / \ Timestamp : Thu Mar 25 16:42:38 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. +// 05/23/07 - Added wire declaration for internal signals. + +`timescale 1 ps / 1 ps + + +module IOBUF_F_4 (O, IO, I, T); + + output O; + + inout IO; + + input I, T; + + wire ts; + + tri0 GTS = glbl.GTS; + + or O1 (ts, GTS, T); + bufif0 T1 (IO, I, ts); + + buf B1 (O, IO); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IOBUF_F_6.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IOBUF_F_6.v new file mode 100644 index 0000000..4de63af --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IOBUF_F_6.v @@ -0,0 +1,43 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/IOBUF_F_6.v,v 1.6 2007/05/23 21:43:36 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Bi-Directional Buffer with Fast Slew 6 mA Drive +// /___/ /\ Filename : IOBUF_F_6.v +// \ \ / \ Timestamp : Thu Mar 25 16:42:38 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. +// 05/23/07 - Added wire declaration for internal signals. + +`timescale 1 ps / 1 ps + + +module IOBUF_F_6 (O, IO, I, T); + + output O; + + inout IO; + + input I, T; + + wire ts; + + tri0 GTS = glbl.GTS; + + or O1 (ts, GTS, T); + bufif0 T1 (IO, I, ts); + + buf B1 (O, IO); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IOBUF_F_8.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IOBUF_F_8.v new file mode 100644 index 0000000..e7c9eef --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IOBUF_F_8.v @@ -0,0 +1,43 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/IOBUF_F_8.v,v 1.6 2007/05/23 21:43:36 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Bi-Directional Buffer with Fast Slew 8 mA Drive +// /___/ /\ Filename : IOBUF_F_8.v +// \ \ / \ Timestamp : Thu Mar 25 16:42:38 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. +// 05/23/07 - Added wire declaration for internal signals. + +`timescale 1 ps / 1 ps + + +module IOBUF_F_8 (O, IO, I, T); + + output O; + + inout IO; + + input I, T; + + wire ts; + + tri0 GTS = glbl.GTS; + + or O1 (ts, GTS, T); + bufif0 T1 (IO, I, ts); + + buf B1 (O, IO); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IOBUF_GTL.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IOBUF_GTL.v new file mode 100644 index 0000000..304cec1 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IOBUF_GTL.v @@ -0,0 +1,43 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/IOBUF_GTL.v,v 1.6 2007/05/23 21:43:36 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Bi-Directional Buffer with GTL I/O Standard +// /___/ /\ Filename : IOBUF_GTL.v +// \ \ / \ Timestamp : Thu Mar 25 16:42:38 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. +// 05/23/07 - Added wire declaration for internal signals. + +`timescale 1 ps / 1 ps + + +module IOBUF_GTL (O, IO, I, T); + + output O; + + inout IO; + + input I, T; + + wire ts; + + tri0 GTS = glbl.GTS; + + or O1 (ts, GTS, T); + bufif0 T1 (IO, I, ts); + + buf B1 (O, IO); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IOBUF_GTLP.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IOBUF_GTLP.v new file mode 100644 index 0000000..3f8c7ac --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IOBUF_GTLP.v @@ -0,0 +1,43 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/IOBUF_GTLP.v,v 1.6 2007/05/23 21:43:36 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Bi-Directional Buffer with GTLP I/O Standard +// /___/ /\ Filename : IOBUF_GTLP.v +// \ \ / \ Timestamp : Thu Mar 25 16:42:39 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. +// 05/23/07 - Added wire declaration for internal signals. + +`timescale 1 ps / 1 ps + + +module IOBUF_GTLP (O, IO, I, T); + + output O; + + inout IO; + + input I, T; + + wire ts; + + tri0 GTS = glbl.GTS; + + or O1 (ts, GTS, T); + bufif0 T1 (IO, I, ts); + + buf B1 (O, IO); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IOBUF_GTLP_DCI.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IOBUF_GTLP_DCI.v new file mode 100644 index 0000000..8c80942 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IOBUF_GTLP_DCI.v @@ -0,0 +1,43 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/IOBUF_GTLP_DCI.v,v 1.6 2007/05/23 21:43:36 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Bi-Directional Buffer with GTLP_DCI I/O Standard +// /___/ /\ Filename : IOBUF_GTLP_DCI.v +// \ \ / \ Timestamp : Thu Mar 25 16:42:39 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. +// 05/23/07 - Added wire declaration for internal signals. + +`timescale 1 ps / 1 ps + + +module IOBUF_GTLP_DCI (O, IO, I, T); + + output O; + + inout IO; + + input I, T; + + wire ts; + + tri0 GTS = glbl.GTS; + + or O1 (ts, GTS, T); + bufif0 T1 (IO, I, ts); + + buf B1 (O, IO); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IOBUF_GTL_DCI.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IOBUF_GTL_DCI.v new file mode 100644 index 0000000..cd1f861 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IOBUF_GTL_DCI.v @@ -0,0 +1,43 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/IOBUF_GTL_DCI.v,v 1.6 2007/05/23 21:43:36 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Bi-Directional Buffer with GTL_DCI I/O Standard +// /___/ /\ Filename : IOBUF_GTL_DCI.v +// \ \ / \ Timestamp : Thu Mar 25 16:42:39 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. +// 05/23/07 - Added wire declaration for internal signals. + +`timescale 1 ps / 1 ps + + +module IOBUF_GTL_DCI (O, IO, I, T); + + output O; + + inout IO; + + input I, T; + + wire ts; + + tri0 GTS = glbl.GTS; + + or O1 (ts, GTS, T); + bufif0 T1 (IO, I, ts); + + buf B1 (O, IO); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IOBUF_HSTL_I.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IOBUF_HSTL_I.v new file mode 100644 index 0000000..4342582 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IOBUF_HSTL_I.v @@ -0,0 +1,43 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/IOBUF_HSTL_I.v,v 1.6 2007/05/23 21:43:37 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Bi-Directional Buffer with HSTL_I I/O Standard +// /___/ /\ Filename : IOBUF_HSTL_I.v +// \ \ / \ Timestamp : Thu Mar 25 16:42:39 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. +// 05/23/07 - Added wire declaration for internal signals. + +`timescale 1 ps / 1 ps + + +module IOBUF_HSTL_I (O, IO, I, T); + + output O; + + inout IO; + + input I, T; + + wire ts; + + tri0 GTS = glbl.GTS; + + or O1 (ts, GTS, T); + bufif0 T1 (IO, I, ts); + + buf B1 (O, IO); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IOBUF_HSTL_II.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IOBUF_HSTL_II.v new file mode 100644 index 0000000..ef17543 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IOBUF_HSTL_II.v @@ -0,0 +1,43 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/IOBUF_HSTL_II.v,v 1.6 2007/05/23 21:43:37 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Bi-Directional Buffer with HSTL_II I/O Standard +// /___/ /\ Filename : IOBUF_HSTL_II.v +// \ \ / \ Timestamp : Thu Mar 25 16:42:39 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. +// 05/23/07 - Added wire declaration for internal signals. + +`timescale 1 ps / 1 ps + + +module IOBUF_HSTL_II (O, IO, I, T); + + output O; + + inout IO; + + input I, T; + + wire ts; + + tri0 GTS = glbl.GTS; + + or O1 (ts, GTS, T); + bufif0 T1 (IO, I, ts); + + buf B1 (O, IO); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IOBUF_HSTL_III.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IOBUF_HSTL_III.v new file mode 100644 index 0000000..d4a604e --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IOBUF_HSTL_III.v @@ -0,0 +1,43 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/IOBUF_HSTL_III.v,v 1.6 2007/05/23 21:43:37 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Bi-Directional Buffer with HSTL_III I/O Standard +// /___/ /\ Filename : IOBUF_HSTL_III.v +// \ \ / \ Timestamp : Thu Mar 25 16:42:39 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. +// 05/23/07 - Added wire declaration for internal signals. + +`timescale 1 ps / 1 ps + + +module IOBUF_HSTL_III (O, IO, I, T); + + output O; + + inout IO; + + input I, T; + + wire ts; + + tri0 GTS = glbl.GTS; + + or O1 (ts, GTS, T); + bufif0 T1 (IO, I, ts); + + buf B1 (O, IO); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IOBUF_HSTL_III_18.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IOBUF_HSTL_III_18.v new file mode 100644 index 0000000..54cace5 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IOBUF_HSTL_III_18.v @@ -0,0 +1,43 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/IOBUF_HSTL_III_18.v,v 1.6 2007/05/23 21:43:37 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Bi-Directional Buffer with HSTL_III_18 I/O Standard +// /___/ /\ Filename : IOBUF_HSTL_III_18.v +// \ \ / \ Timestamp : Thu Mar 25 16:42:39 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. +// 05/23/07 - Added wire declaration for internal signals. + +`timescale 1 ps / 1 ps + + +module IOBUF_HSTL_III_18 (O, IO, I, T); + + output O; + + inout IO; + + input I, T; + + wire ts; + + tri0 GTS = glbl.GTS; + + or O1 (ts, GTS, T); + bufif0 T1 (IO, I, ts); + + buf B1 (O, IO); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IOBUF_HSTL_II_18.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IOBUF_HSTL_II_18.v new file mode 100644 index 0000000..3a43953 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IOBUF_HSTL_II_18.v @@ -0,0 +1,43 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/IOBUF_HSTL_II_18.v,v 1.6 2007/05/23 21:43:36 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Bi-Directional Buffer with HSTL_II_18 I/O Standard +// /___/ /\ Filename : IOBUF_HSTL_II_18.v +// \ \ / \ Timestamp : Thu Mar 25 16:42:39 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. +// 05/23/07 - Added wire declaration for internal signals. + +`timescale 1 ps / 1 ps + + +module IOBUF_HSTL_II_18 (O, IO, I, T); + + output O; + + inout IO; + + input I, T; + + wire ts; + + tri0 GTS = glbl.GTS; + + or O1 (ts, GTS, T); + bufif0 T1 (IO, I, ts); + + buf B1 (O, IO); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IOBUF_HSTL_II_DCI.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IOBUF_HSTL_II_DCI.v new file mode 100644 index 0000000..7e07f4f --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IOBUF_HSTL_II_DCI.v @@ -0,0 +1,43 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/IOBUF_HSTL_II_DCI.v,v 1.6 2007/05/23 21:43:37 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Bi-Directional Buffer with HSTL_II_DCI I/O Standard +// /___/ /\ Filename : IOBUF_HSTL_II_DCI.v +// \ \ / \ Timestamp : Thu Mar 25 16:42:39 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. +// 05/23/07 - Added wire declaration for internal signals. + +`timescale 1 ps / 1 ps + + +module IOBUF_HSTL_II_DCI (O, IO, I, T); + + output O; + + inout IO; + + input I, T; + + wire ts; + + tri0 GTS = glbl.GTS; + + or O1 (ts, GTS, T); + bufif0 T1 (IO, I, ts); + + buf B1 (O, IO); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IOBUF_HSTL_II_DCI_18.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IOBUF_HSTL_II_DCI_18.v new file mode 100644 index 0000000..1bf50d7 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IOBUF_HSTL_II_DCI_18.v @@ -0,0 +1,43 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/IOBUF_HSTL_II_DCI_18.v,v 1.6 2007/05/23 21:43:36 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Bi-Directional Buffer with HSTL_II_DCI_18 I/O Standard +// /___/ /\ Filename : IOBUF_HSTL_II_DCI_18.v +// \ \ / \ Timestamp : Thu Mar 25 16:42:39 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. +// 05/23/07 - Added wire declaration for internal signals. + +`timescale 1 ps / 1 ps + + +module IOBUF_HSTL_II_DCI_18 (O, IO, I, T); + + output O; + + inout IO; + + input I, T; + + wire ts; + + tri0 GTS = glbl.GTS; + + or O1 (ts, GTS, T); + bufif0 T1 (IO, I, ts); + + buf B1 (O, IO); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IOBUF_HSTL_IV.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IOBUF_HSTL_IV.v new file mode 100644 index 0000000..5bf9b43 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IOBUF_HSTL_IV.v @@ -0,0 +1,43 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/IOBUF_HSTL_IV.v,v 1.6 2007/05/23 21:43:37 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Bi-Directional Buffer with HSTL_IV I/O Standard +// /___/ /\ Filename : IOBUF_HSTL_IV.v +// \ \ / \ Timestamp : Thu Mar 25 16:42:40 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. +// 05/23/07 - Added wire declaration for internal signals. + +`timescale 1 ps / 1 ps + + +module IOBUF_HSTL_IV (O, IO, I, T); + + output O; + + inout IO; + + input I, T; + + wire ts; + + tri0 GTS = glbl.GTS; + + or O1 (ts, GTS, T); + bufif0 T1 (IO, I, ts); + + buf B1 (O, IO); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IOBUF_HSTL_IV_18.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IOBUF_HSTL_IV_18.v new file mode 100644 index 0000000..ac02150 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IOBUF_HSTL_IV_18.v @@ -0,0 +1,43 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/IOBUF_HSTL_IV_18.v,v 1.6 2007/05/23 21:43:37 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Bi-Directional Buffer with HSTL_IV_18 I/O Standard +// /___/ /\ Filename : IOBUF_HSTL_IV_18.v +// \ \ / \ Timestamp : Thu Mar 25 16:42:40 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. +// 05/23/07 - Added wire declaration for internal signals. + +`timescale 1 ps / 1 ps + + +module IOBUF_HSTL_IV_18 (O, IO, I, T); + + output O; + + inout IO; + + input I, T; + + wire ts; + + tri0 GTS = glbl.GTS; + + or O1 (ts, GTS, T); + bufif0 T1 (IO, I, ts); + + buf B1 (O, IO); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IOBUF_HSTL_IV_DCI.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IOBUF_HSTL_IV_DCI.v new file mode 100644 index 0000000..3b8623e --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IOBUF_HSTL_IV_DCI.v @@ -0,0 +1,43 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/IOBUF_HSTL_IV_DCI.v,v 1.6 2007/05/23 21:43:37 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Bi-Directional Buffer with HSTL_IV_DCI I/O Standard +// /___/ /\ Filename : IOBUF_HSTL_IV_DCI.v +// \ \ / \ Timestamp : Thu Mar 25 16:42:40 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. +// 05/23/07 - Added wire declaration for internal signals. + +`timescale 1 ps / 1 ps + + +module IOBUF_HSTL_IV_DCI (O, IO, I, T); + + output O; + + inout IO; + + input I, T; + + wire ts; + + tri0 GTS = glbl.GTS; + + or O1 (ts, GTS, T); + bufif0 T1 (IO, I, ts); + + buf B1 (O, IO); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IOBUF_HSTL_IV_DCI_18.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IOBUF_HSTL_IV_DCI_18.v new file mode 100644 index 0000000..2caad23 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IOBUF_HSTL_IV_DCI_18.v @@ -0,0 +1,43 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/IOBUF_HSTL_IV_DCI_18.v,v 1.6 2007/05/23 21:43:37 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Bi-Directional Buffer with HSTL_IV_DCI_18 I/O Standard +// /___/ /\ Filename : IOBUF_HSTL_IV_DCI_18.v +// \ \ / \ Timestamp : Thu Mar 25 16:42:40 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. +// 05/23/07 - Added wire declaration for internal signals. + +`timescale 1 ps / 1 ps + + +module IOBUF_HSTL_IV_DCI_18 (O, IO, I, T); + + output O; + + inout IO; + + input I, T; + + wire ts; + + tri0 GTS = glbl.GTS; + + or O1 (ts, GTS, T); + bufif0 T1 (IO, I, ts); + + buf B1 (O, IO); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IOBUF_HSTL_I_18.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IOBUF_HSTL_I_18.v new file mode 100644 index 0000000..4f54d4c --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IOBUF_HSTL_I_18.v @@ -0,0 +1,43 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/IOBUF_HSTL_I_18.v,v 1.6 2007/05/23 21:43:36 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Bi-Directional Buffer with HSTL_I_18 I/O Standard +// /___/ /\ Filename : IOBUF_HSTL_I_18.v +// \ \ / \ Timestamp : Thu Mar 25 16:42:40 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. +// 05/23/07 - Added wire declaration for internal signals. + +`timescale 1 ps / 1 ps + + +module IOBUF_HSTL_I_18 (O, IO, I, T); + + output O; + + inout IO; + + input I, T; + + wire ts; + + tri0 GTS = glbl.GTS; + + or O1 (ts, GTS, T); + bufif0 T1 (IO, I, ts); + + buf B1 (O, IO); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IOBUF_LVCMOS12.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IOBUF_LVCMOS12.v new file mode 100644 index 0000000..91ec948 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IOBUF_LVCMOS12.v @@ -0,0 +1,43 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/IOBUF_LVCMOS12.v,v 1.6 2007/05/23 21:43:37 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Bi-Directional Buffer with LVCMOS12 I/O Standard +// /___/ /\ Filename : IOBUF_LVCMOS12.v +// \ \ / \ Timestamp : Thu Mar 25 16:42:40 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. +// 05/23/07 - Added wire declaration for internal signals. + +`timescale 1 ps / 1 ps + + +module IOBUF_LVCMOS12 (O, IO, I, T); + + output O; + + inout IO; + + input I, T; + + wire ts; + + tri0 GTS = glbl.GTS; + + or O1 (ts, GTS, T); + bufif0 T1 (IO, I, ts); + + buf B1 (O, IO); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IOBUF_LVCMOS12_F_2.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IOBUF_LVCMOS12_F_2.v new file mode 100644 index 0000000..bbe0b4b --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IOBUF_LVCMOS12_F_2.v @@ -0,0 +1,43 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/IOBUF_LVCMOS12_F_2.v,v 1.6 2007/05/23 21:43:37 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Bi-Directional Buffer with LVCMOS12 I/O Standard Fast Slew 2 mA Drive +// /___/ /\ Filename : IOBUF_LVCMOS12_F_2.v +// \ \ / \ Timestamp : Thu Mar 25 16:42:40 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. +// 05/23/07 - Added wire declaration for internal signals. + +`timescale 1 ps / 1 ps + + +module IOBUF_LVCMOS12_F_2 (O, IO, I, T); + + output O; + + inout IO; + + input I, T; + + wire ts; + + tri0 GTS = glbl.GTS; + + or O1 (ts, GTS, T); + bufif0 T1 (IO, I, ts); + + buf B1 (O, IO); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IOBUF_LVCMOS12_F_4.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IOBUF_LVCMOS12_F_4.v new file mode 100644 index 0000000..faf51ed --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IOBUF_LVCMOS12_F_4.v @@ -0,0 +1,43 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/IOBUF_LVCMOS12_F_4.v,v 1.6 2007/05/23 21:43:37 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Bi-Directional Buffer with LVCMOS12 I/O Standard Fast Slew 4 mA Drive +// /___/ /\ Filename : IOBUF_LVCMOS12_F_4.v +// \ \ / \ Timestamp : Thu Mar 25 16:42:40 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. +// 05/23/07 - Added wire declaration for internal signals. + +`timescale 1 ps / 1 ps + + +module IOBUF_LVCMOS12_F_4 (O, IO, I, T); + + output O; + + inout IO; + + input I, T; + + wire ts; + + tri0 GTS = glbl.GTS; + + or O1 (ts, GTS, T); + bufif0 T1 (IO, I, ts); + + buf B1 (O, IO); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IOBUF_LVCMOS12_F_6.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IOBUF_LVCMOS12_F_6.v new file mode 100644 index 0000000..2ff5086 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IOBUF_LVCMOS12_F_6.v @@ -0,0 +1,43 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/IOBUF_LVCMOS12_F_6.v,v 1.6 2007/05/23 21:43:37 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Bi-Directional Buffer with LVCMOS12 I/O Standard Fast Slew 6 mA Drive +// /___/ /\ Filename : IOBUF_LVCMOS12_F_6.v +// \ \ / \ Timestamp : Thu Mar 25 16:42:40 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. +// 05/23/07 - Added wire declaration for internal signals. + +`timescale 1 ps / 1 ps + + +module IOBUF_LVCMOS12_F_6 (O, IO, I, T); + + output O; + + inout IO; + + input I, T; + + wire ts; + + tri0 GTS = glbl.GTS; + + or O1 (ts, GTS, T); + bufif0 T1 (IO, I, ts); + + buf B1 (O, IO); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IOBUF_LVCMOS12_F_8.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IOBUF_LVCMOS12_F_8.v new file mode 100644 index 0000000..dcbb2f2 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IOBUF_LVCMOS12_F_8.v @@ -0,0 +1,43 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/IOBUF_LVCMOS12_F_8.v,v 1.6 2007/05/23 21:43:37 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Bi-Directional Buffer with LVCMOS12 I/O Standard Fast Slew 8 mA Drive +// /___/ /\ Filename : IOBUF_LVCMOS12_F_8.v +// \ \ / \ Timestamp : Thu Mar 25 16:42:40 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. +// 05/23/07 - Added wire declaration for internal signals. + +`timescale 1 ps / 1 ps + + +module IOBUF_LVCMOS12_F_8 (O, IO, I, T); + + output O; + + inout IO; + + input I, T; + + wire ts; + + tri0 GTS = glbl.GTS; + + or O1 (ts, GTS, T); + bufif0 T1 (IO, I, ts); + + buf B1 (O, IO); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IOBUF_LVCMOS12_S_2.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IOBUF_LVCMOS12_S_2.v new file mode 100644 index 0000000..61aec22 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IOBUF_LVCMOS12_S_2.v @@ -0,0 +1,43 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/IOBUF_LVCMOS12_S_2.v,v 1.6 2007/05/23 21:43:37 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Bi-Directional Buffer with LVCMOS12 I/O Standard Slow Slew 2 mA Drive +// /___/ /\ Filename : IOBUF_LVCMOS12_S_2.v +// \ \ / \ Timestamp : Thu Mar 25 16:42:41 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. +// 05/23/07 - Added wire declaration for internal signals. + +`timescale 1 ps / 1 ps + + +module IOBUF_LVCMOS12_S_2 (O, IO, I, T); + + output O; + + inout IO; + + input I, T; + + wire ts; + + tri0 GTS = glbl.GTS; + + or O1 (ts, GTS, T); + bufif0 T1 (IO, I, ts); + + buf B1 (O, IO); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IOBUF_LVCMOS12_S_4.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IOBUF_LVCMOS12_S_4.v new file mode 100644 index 0000000..8314289 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IOBUF_LVCMOS12_S_4.v @@ -0,0 +1,43 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/IOBUF_LVCMOS12_S_4.v,v 1.6 2007/05/23 21:43:37 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Bi-Directional Buffer with LVCMOS12 I/O Standard Slow Slew 4 mA Drive +// /___/ /\ Filename : IOBUF_LVCMOS12_S_4.v +// \ \ / \ Timestamp : Thu Mar 25 16:42:41 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. +// 05/23/07 - Added wire declaration for internal signals. + +`timescale 1 ps / 1 ps + + +module IOBUF_LVCMOS12_S_4 (O, IO, I, T); + + output O; + + inout IO; + + input I, T; + + wire ts; + + tri0 GTS = glbl.GTS; + + or O1 (ts, GTS, T); + bufif0 T1 (IO, I, ts); + + buf B1 (O, IO); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IOBUF_LVCMOS12_S_6.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IOBUF_LVCMOS12_S_6.v new file mode 100644 index 0000000..235ab63 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IOBUF_LVCMOS12_S_6.v @@ -0,0 +1,43 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/IOBUF_LVCMOS12_S_6.v,v 1.6 2007/05/23 21:43:37 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Bi-Directional Buffer with LVCMOS12 I/O Standard Slow Slew 6 mA Drive +// /___/ /\ Filename : IOBUF_LVCMOS12_S_6.v +// \ \ / \ Timestamp : Thu Mar 25 16:42:41 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. +// 05/23/07 - Added wire declaration for internal signals. + +`timescale 1 ps / 1 ps + + +module IOBUF_LVCMOS12_S_6 (O, IO, I, T); + + output O; + + inout IO; + + input I, T; + + wire ts; + + tri0 GTS = glbl.GTS; + + or O1 (ts, GTS, T); + bufif0 T1 (IO, I, ts); + + buf B1 (O, IO); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IOBUF_LVCMOS12_S_8.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IOBUF_LVCMOS12_S_8.v new file mode 100644 index 0000000..c8f18e3 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IOBUF_LVCMOS12_S_8.v @@ -0,0 +1,43 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/IOBUF_LVCMOS12_S_8.v,v 1.6 2007/05/23 21:43:37 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Bi-Directional Buffer with LVCMOS12 I/O Standard Slow Slew 8 mA Drive +// /___/ /\ Filename : IOBUF_LVCMOS12_S_8.v +// \ \ / \ Timestamp : Thu Mar 25 16:42:41 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. +// 05/23/07 - Added wire declaration for internal signals. + +`timescale 1 ps / 1 ps + + +module IOBUF_LVCMOS12_S_8 (O, IO, I, T); + + output O; + + inout IO; + + input I, T; + + wire ts; + + tri0 GTS = glbl.GTS; + + or O1 (ts, GTS, T); + bufif0 T1 (IO, I, ts); + + buf B1 (O, IO); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IOBUF_LVCMOS15.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IOBUF_LVCMOS15.v new file mode 100644 index 0000000..d54d0b5 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IOBUF_LVCMOS15.v @@ -0,0 +1,43 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/IOBUF_LVCMOS15.v,v 1.6 2007/05/23 21:43:37 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Bi-Directional Buffer with LVCMOS15 I/O Standard +// /___/ /\ Filename : IOBUF_LVCMOS15.v +// \ \ / \ Timestamp : Thu Mar 25 16:42:41 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. +// 05/23/07 - Added wire declaration for internal signals. + +`timescale 1 ps / 1 ps + + +module IOBUF_LVCMOS15 (O, IO, I, T); + + output O; + + inout IO; + + input I, T; + + wire ts; + + tri0 GTS = glbl.GTS; + + or O1 (ts, GTS, T); + bufif0 T1 (IO, I, ts); + + buf B1 (O, IO); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IOBUF_LVCMOS15_F_12.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IOBUF_LVCMOS15_F_12.v new file mode 100644 index 0000000..03b3537 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IOBUF_LVCMOS15_F_12.v @@ -0,0 +1,43 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/IOBUF_LVCMOS15_F_12.v,v 1.6 2007/05/23 21:43:37 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Bi-Directional Buffer with LVCMOS15 I/O Standard Fast Slew 12 mA Drive +// /___/ /\ Filename : IOBUF_LVCMOS15_F_12.v +// \ \ / \ Timestamp : Thu Mar 25 16:42:41 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. +// 05/23/07 - Added wire declaration for internal signals. + +`timescale 1 ps / 1 ps + + +module IOBUF_LVCMOS15_F_12 (O, IO, I, T); + + output O; + + inout IO; + + input I, T; + + wire ts; + + tri0 GTS = glbl.GTS; + + or O1 (ts, GTS, T); + bufif0 T1 (IO, I, ts); + + buf B1 (O, IO); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IOBUF_LVCMOS15_F_16.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IOBUF_LVCMOS15_F_16.v new file mode 100644 index 0000000..ff0cf63 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IOBUF_LVCMOS15_F_16.v @@ -0,0 +1,43 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/IOBUF_LVCMOS15_F_16.v,v 1.6 2007/05/23 21:43:37 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Bi-Directional Buffer with LVCMOS15 I/O Standard Fast Slew 16 mA Drive +// /___/ /\ Filename : IOBUF_LVCMOS15_F_16.v +// \ \ / \ Timestamp : Thu Mar 25 16:42:41 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. +// 05/23/07 - Added wire declaration for internal signals. + +`timescale 1 ps / 1 ps + + +module IOBUF_LVCMOS15_F_16 (O, IO, I, T); + + output O; + + inout IO; + + input I, T; + + wire ts; + + tri0 GTS = glbl.GTS; + + or O1 (ts, GTS, T); + bufif0 T1 (IO, I, ts); + + buf B1 (O, IO); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IOBUF_LVCMOS15_F_2.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IOBUF_LVCMOS15_F_2.v new file mode 100644 index 0000000..74a41ff --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IOBUF_LVCMOS15_F_2.v @@ -0,0 +1,43 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/IOBUF_LVCMOS15_F_2.v,v 1.6 2007/05/23 21:43:37 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Bi-Directional Buffer with LVCMOS15 I/O Standard Fast Slew 2 mA Drive +// /___/ /\ Filename : IOBUF_LVCMOS15_F_2.v +// \ \ / \ Timestamp : Thu Mar 25 16:42:41 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. +// 05/23/07 - Added wire declaration for internal signals. + +`timescale 1 ps / 1 ps + + +module IOBUF_LVCMOS15_F_2 (O, IO, I, T); + + output O; + + inout IO; + + input I, T; + + wire ts; + + tri0 GTS = glbl.GTS; + + or O1 (ts, GTS, T); + bufif0 T1 (IO, I, ts); + + buf B1 (O, IO); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IOBUF_LVCMOS15_F_4.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IOBUF_LVCMOS15_F_4.v new file mode 100644 index 0000000..47c9fdd --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IOBUF_LVCMOS15_F_4.v @@ -0,0 +1,43 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/IOBUF_LVCMOS15_F_4.v,v 1.6 2007/05/23 21:43:37 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Bi-Directional Buffer with LVCMOS15 I/O Standard Fast Slew 4 mA Drive +// /___/ /\ Filename : IOBUF_LVCMOS15_F_4.v +// \ \ / \ Timestamp : Thu Mar 25 16:42:41 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. +// 05/23/07 - Added wire declaration for internal signals. + +`timescale 1 ps / 1 ps + + +module IOBUF_LVCMOS15_F_4 (O, IO, I, T); + + output O; + + inout IO; + + input I, T; + + wire ts; + + tri0 GTS = glbl.GTS; + + or O1 (ts, GTS, T); + bufif0 T1 (IO, I, ts); + + buf B1 (O, IO); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IOBUF_LVCMOS15_F_6.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IOBUF_LVCMOS15_F_6.v new file mode 100644 index 0000000..f05884a --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IOBUF_LVCMOS15_F_6.v @@ -0,0 +1,43 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/IOBUF_LVCMOS15_F_6.v,v 1.6 2007/05/23 21:43:37 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Bi-Directional Buffer with LVCMOS15 I/O Standard Fast Slew 6 mA Drive +// /___/ /\ Filename : IOBUF_LVCMOS15_F_6.v +// \ \ / \ Timestamp : Thu Mar 25 16:42:41 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. +// 05/23/07 - Added wire declaration for internal signals. + +`timescale 1 ps / 1 ps + + +module IOBUF_LVCMOS15_F_6 (O, IO, I, T); + + output O; + + inout IO; + + input I, T; + + wire ts; + + tri0 GTS = glbl.GTS; + + or O1 (ts, GTS, T); + bufif0 T1 (IO, I, ts); + + buf B1 (O, IO); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IOBUF_LVCMOS15_F_8.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IOBUF_LVCMOS15_F_8.v new file mode 100644 index 0000000..9257640 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IOBUF_LVCMOS15_F_8.v @@ -0,0 +1,43 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/IOBUF_LVCMOS15_F_8.v,v 1.6 2007/05/23 21:43:37 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Bi-Directional Buffer with LVCMOS15 I/O Standard Fast Slew 8 mA Drive +// /___/ /\ Filename : IOBUF_LVCMOS15_F_8.v +// \ \ / \ Timestamp : Thu Mar 25 16:42:42 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. +// 05/23/07 - Added wire declaration for internal signals. + +`timescale 1 ps / 1 ps + + +module IOBUF_LVCMOS15_F_8 (O, IO, I, T); + + output O; + + inout IO; + + input I, T; + + wire ts; + + tri0 GTS = glbl.GTS; + + or O1 (ts, GTS, T); + bufif0 T1 (IO, I, ts); + + buf B1 (O, IO); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IOBUF_LVCMOS15_S_12.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IOBUF_LVCMOS15_S_12.v new file mode 100644 index 0000000..84fba6b --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IOBUF_LVCMOS15_S_12.v @@ -0,0 +1,43 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/IOBUF_LVCMOS15_S_12.v,v 1.6 2007/05/23 21:43:37 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Bi-Directional Buffer with LVCMOS15 I/O Standard Slow Slew 12 mA Drive +// /___/ /\ Filename : IOBUF_LVCMOS15_S_12.v +// \ \ / \ Timestamp : Thu Mar 25 16:42:42 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. +// 05/23/07 - Added wire declaration for internal signals. + +`timescale 1 ps / 1 ps + + +module IOBUF_LVCMOS15_S_12 (O, IO, I, T); + + output O; + + inout IO; + + input I, T; + + wire ts; + + tri0 GTS = glbl.GTS; + + or O1 (ts, GTS, T); + bufif0 T1 (IO, I, ts); + + buf B1 (O, IO); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IOBUF_LVCMOS15_S_16.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IOBUF_LVCMOS15_S_16.v new file mode 100644 index 0000000..f4a524c --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IOBUF_LVCMOS15_S_16.v @@ -0,0 +1,43 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/IOBUF_LVCMOS15_S_16.v,v 1.6 2007/05/23 21:43:37 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Bi-Directional Buffer with LVCMOS15 I/O Standard Slow Slew 16 mA Drive +// /___/ /\ Filename : IOBUF_LVCMOS15_S_16.v +// \ \ / \ Timestamp : Thu Mar 25 16:42:42 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. +// 05/23/07 - Added wire declaration for internal signals. + +`timescale 1 ps / 1 ps + + +module IOBUF_LVCMOS15_S_16 (O, IO, I, T); + + output O; + + inout IO; + + input I, T; + + wire ts; + + tri0 GTS = glbl.GTS; + + or O1 (ts, GTS, T); + bufif0 T1 (IO, I, ts); + + buf B1 (O, IO); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IOBUF_LVCMOS15_S_2.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IOBUF_LVCMOS15_S_2.v new file mode 100644 index 0000000..9a8d84a --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IOBUF_LVCMOS15_S_2.v @@ -0,0 +1,43 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/IOBUF_LVCMOS15_S_2.v,v 1.6 2007/05/23 21:43:37 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Bi-Directional Buffer with LVCMOS15 I/O Standard Slow Slew 2 mA Drive +// /___/ /\ Filename : IOBUF_LVCMOS15_S_2.v +// \ \ / \ Timestamp : Thu Mar 25 16:42:42 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. +// 05/23/07 - Added wire declaration for internal signals. + +`timescale 1 ps / 1 ps + + +module IOBUF_LVCMOS15_S_2 (O, IO, I, T); + + output O; + + inout IO; + + input I, T; + + wire ts; + + tri0 GTS = glbl.GTS; + + or O1 (ts, GTS, T); + bufif0 T1 (IO, I, ts); + + buf B1 (O, IO); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IOBUF_LVCMOS15_S_4.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IOBUF_LVCMOS15_S_4.v new file mode 100644 index 0000000..cda427b --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IOBUF_LVCMOS15_S_4.v @@ -0,0 +1,43 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/IOBUF_LVCMOS15_S_4.v,v 1.6 2007/05/23 21:43:37 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Bi-Directional Buffer with LVCMOS15 I/O Standard Slow Slew 4 mA Drive +// /___/ /\ Filename : IOBUF_LVCMOS15_S_4.v +// \ \ / \ Timestamp : Thu Mar 25 16:42:42 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. +// 05/23/07 - Added wire declaration for internal signals. + +`timescale 1 ps / 1 ps + + +module IOBUF_LVCMOS15_S_4 (O, IO, I, T); + + output O; + + inout IO; + + input I, T; + + wire ts; + + tri0 GTS = glbl.GTS; + + or O1 (ts, GTS, T); + bufif0 T1 (IO, I, ts); + + buf B1 (O, IO); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IOBUF_LVCMOS15_S_6.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IOBUF_LVCMOS15_S_6.v new file mode 100644 index 0000000..c38daeb --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IOBUF_LVCMOS15_S_6.v @@ -0,0 +1,43 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/IOBUF_LVCMOS15_S_6.v,v 1.6 2007/05/23 21:43:37 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Bi-Directional Buffer with LVCMOS15 I/O Standard Slow Slew 6 mA Drive +// /___/ /\ Filename : IOBUF_LVCMOS15_S_6.v +// \ \ / \ Timestamp : Thu Mar 25 16:42:42 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. +// 05/23/07 - Added wire declaration for internal signals. + +`timescale 1 ps / 1 ps + + +module IOBUF_LVCMOS15_S_6 (O, IO, I, T); + + output O; + + inout IO; + + input I, T; + + wire ts; + + tri0 GTS = glbl.GTS; + + or O1 (ts, GTS, T); + bufif0 T1 (IO, I, ts); + + buf B1 (O, IO); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IOBUF_LVCMOS15_S_8.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IOBUF_LVCMOS15_S_8.v new file mode 100644 index 0000000..e195763 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IOBUF_LVCMOS15_S_8.v @@ -0,0 +1,43 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/IOBUF_LVCMOS15_S_8.v,v 1.6 2007/05/23 21:43:37 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Bi-Directional Buffer with LVCMOS15 I/O Standard Slow Slew 8 mA Drive +// /___/ /\ Filename : IOBUF_LVCMOS15_S_8.v +// \ \ / \ Timestamp : Thu Mar 25 16:42:42 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. +// 05/23/07 - Added wire declaration for internal signals. + +`timescale 1 ps / 1 ps + + +module IOBUF_LVCMOS15_S_8 (O, IO, I, T); + + output O; + + inout IO; + + input I, T; + + wire ts; + + tri0 GTS = glbl.GTS; + + or O1 (ts, GTS, T); + bufif0 T1 (IO, I, ts); + + buf B1 (O, IO); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IOBUF_LVCMOS18.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IOBUF_LVCMOS18.v new file mode 100644 index 0000000..173f3a4 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IOBUF_LVCMOS18.v @@ -0,0 +1,43 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/IOBUF_LVCMOS18.v,v 1.6 2007/05/23 21:43:37 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Bi-Directional Buffer with LVCMOS18 I/O Standard +// /___/ /\ Filename : IOBUF_LVCMOS18.v +// \ \ / \ Timestamp : Thu Mar 25 16:42:42 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. +// 05/23/07 - Added wire declaration for internal signals. + +`timescale 1 ps / 1 ps + + +module IOBUF_LVCMOS18 (O, IO, I, T); + + output O; + + inout IO; + + input I, T; + + wire ts; + + tri0 GTS = glbl.GTS; + + or O1 (ts, GTS, T); + bufif0 T1 (IO, I, ts); + + buf B1 (O, IO); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IOBUF_LVCMOS18_F_12.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IOBUF_LVCMOS18_F_12.v new file mode 100644 index 0000000..71b2c87 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IOBUF_LVCMOS18_F_12.v @@ -0,0 +1,43 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/IOBUF_LVCMOS18_F_12.v,v 1.6 2007/05/23 21:43:37 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Bi-Directional Buffer with LVCMOS18 I/O Standard Fast Slew 12 mA Drive +// /___/ /\ Filename : IOBUF_LVCMOS18_F_12.v +// \ \ / \ Timestamp : Thu Mar 25 16:42:42 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. +// 05/23/07 - Added wire declaration for internal signals. + +`timescale 1 ps / 1 ps + + +module IOBUF_LVCMOS18_F_12 (O, IO, I, T); + + output O; + + inout IO; + + input I, T; + + wire ts; + + tri0 GTS = glbl.GTS; + + or O1 (ts, GTS, T); + bufif0 T1 (IO, I, ts); + + buf B1 (O, IO); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IOBUF_LVCMOS18_F_16.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IOBUF_LVCMOS18_F_16.v new file mode 100644 index 0000000..445f272 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IOBUF_LVCMOS18_F_16.v @@ -0,0 +1,43 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/IOBUF_LVCMOS18_F_16.v,v 1.6 2007/05/23 21:43:37 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Bi-Directional Buffer with LVCMOS18 I/O Standard Fast Slew 16 mA Drive +// /___/ /\ Filename : IOBUF_LVCMOS18_F_16.v +// \ \ / \ Timestamp : Thu Mar 25 16:42:42 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. +// 05/23/07 - Added wire declaration for internal signals. + +`timescale 1 ps / 1 ps + + +module IOBUF_LVCMOS18_F_16 (O, IO, I, T); + + output O; + + inout IO; + + input I, T; + + wire ts; + + tri0 GTS = glbl.GTS; + + or O1 (ts, GTS, T); + bufif0 T1 (IO, I, ts); + + buf B1 (O, IO); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IOBUF_LVCMOS18_F_2.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IOBUF_LVCMOS18_F_2.v new file mode 100644 index 0000000..b8df154 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IOBUF_LVCMOS18_F_2.v @@ -0,0 +1,43 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/IOBUF_LVCMOS18_F_2.v,v 1.6 2007/05/23 21:43:37 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Bi-Directional Buffer with LVCMOS18 I/O Standard Fast Slew 2 mA Drive +// /___/ /\ Filename : IOBUF_LVCMOS18_F_2.v +// \ \ / \ Timestamp : Thu Mar 25 16:42:43 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. +// 05/23/07 - Added wire declaration for internal signals. + +`timescale 1 ps / 1 ps + + +module IOBUF_LVCMOS18_F_2 (O, IO, I, T); + + output O; + + inout IO; + + input I, T; + + wire ts; + + tri0 GTS = glbl.GTS; + + or O1 (ts, GTS, T); + bufif0 T1 (IO, I, ts); + + buf B1 (O, IO); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IOBUF_LVCMOS18_F_4.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IOBUF_LVCMOS18_F_4.v new file mode 100644 index 0000000..9c4af55 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IOBUF_LVCMOS18_F_4.v @@ -0,0 +1,43 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/IOBUF_LVCMOS18_F_4.v,v 1.6 2007/05/23 21:43:37 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Bi-Directional Buffer with LVCMOS18 I/O Standard Fast Slew 4 mA Drive +// /___/ /\ Filename : IOBUF_LVCMOS18_F_4.v +// \ \ / \ Timestamp : Thu Mar 25 16:42:43 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. +// 05/23/07 - Added wire declaration for internal signals. + +`timescale 1 ps / 1 ps + + +module IOBUF_LVCMOS18_F_4 (O, IO, I, T); + + output O; + + inout IO; + + input I, T; + + wire ts; + + tri0 GTS = glbl.GTS; + + or O1 (ts, GTS, T); + bufif0 T1 (IO, I, ts); + + buf B1 (O, IO); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IOBUF_LVCMOS18_F_6.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IOBUF_LVCMOS18_F_6.v new file mode 100644 index 0000000..0105957 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IOBUF_LVCMOS18_F_6.v @@ -0,0 +1,43 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/IOBUF_LVCMOS18_F_6.v,v 1.6 2007/05/23 21:43:37 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Bi-Directional Buffer with LVCMOS18 I/O Standard Fast Slew 6 mA Drive +// /___/ /\ Filename : IOBUF_LVCMOS18_F_6.v +// \ \ / \ Timestamp : Thu Mar 25 16:42:43 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. +// 05/23/07 - Added wire declaration for internal signals. + +`timescale 1 ps / 1 ps + + +module IOBUF_LVCMOS18_F_6 (O, IO, I, T); + + output O; + + inout IO; + + input I, T; + + wire ts; + + tri0 GTS = glbl.GTS; + + or O1 (ts, GTS, T); + bufif0 T1 (IO, I, ts); + + buf B1 (O, IO); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IOBUF_LVCMOS18_F_8.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IOBUF_LVCMOS18_F_8.v new file mode 100644 index 0000000..4f05f64 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IOBUF_LVCMOS18_F_8.v @@ -0,0 +1,43 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/IOBUF_LVCMOS18_F_8.v,v 1.6 2007/05/23 21:43:37 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Bi-Directional Buffer with LVCMOS18 I/O Standard Fast Slew 8 mA Drive +// /___/ /\ Filename : IOBUF_LVCMOS18_F_8.v +// \ \ / \ Timestamp : Thu Mar 25 16:42:43 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. +// 05/23/07 - Added wire declaration for internal signals. + +`timescale 1 ps / 1 ps + + +module IOBUF_LVCMOS18_F_8 (O, IO, I, T); + + output O; + + inout IO; + + input I, T; + + wire ts; + + tri0 GTS = glbl.GTS; + + or O1 (ts, GTS, T); + bufif0 T1 (IO, I, ts); + + buf B1 (O, IO); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IOBUF_LVCMOS18_S_12.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IOBUF_LVCMOS18_S_12.v new file mode 100644 index 0000000..24d1c07 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IOBUF_LVCMOS18_S_12.v @@ -0,0 +1,43 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/IOBUF_LVCMOS18_S_12.v,v 1.6 2007/05/23 21:43:37 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Bi-Directional Buffer with LVCMOS18 I/O Standard Slow Slew 12 mA Drive +// /___/ /\ Filename : IOBUF_LVCMOS18_S_12.v +// \ \ / \ Timestamp : Thu Mar 25 16:42:43 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. +// 05/23/07 - Added wire declaration for internal signals. + +`timescale 1 ps / 1 ps + + +module IOBUF_LVCMOS18_S_12 (O, IO, I, T); + + output O; + + inout IO; + + input I, T; + + wire ts; + + tri0 GTS = glbl.GTS; + + or O1 (ts, GTS, T); + bufif0 T1 (IO, I, ts); + + buf B1 (O, IO); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IOBUF_LVCMOS18_S_16.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IOBUF_LVCMOS18_S_16.v new file mode 100644 index 0000000..76dd708 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IOBUF_LVCMOS18_S_16.v @@ -0,0 +1,43 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/IOBUF_LVCMOS18_S_16.v,v 1.6 2007/05/23 21:43:37 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Bi-Directional Buffer with LVCMOS18 I/O Standard Slow Slew 16 mA Drive +// /___/ /\ Filename : IOBUF_LVCMOS18_S_16.v +// \ \ / \ Timestamp : Thu Mar 25 16:42:43 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. +// 05/23/07 - Added wire declaration for internal signals. + +`timescale 1 ps / 1 ps + + +module IOBUF_LVCMOS18_S_16 (O, IO, I, T); + + output O; + + inout IO; + + input I, T; + + wire ts; + + tri0 GTS = glbl.GTS; + + or O1 (ts, GTS, T); + bufif0 T1 (IO, I, ts); + + buf B1 (O, IO); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IOBUF_LVCMOS18_S_2.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IOBUF_LVCMOS18_S_2.v new file mode 100644 index 0000000..3f0f30a --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IOBUF_LVCMOS18_S_2.v @@ -0,0 +1,43 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/IOBUF_LVCMOS18_S_2.v,v 1.6 2007/05/23 21:43:37 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Bi-Directional Buffer with LVCMOS18 I/O Standard Slow Slew 2 mA Drive +// /___/ /\ Filename : IOBUF_LVCMOS18_S_2.v +// \ \ / \ Timestamp : Thu Mar 25 16:42:43 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. +// 05/23/07 - Added wire declaration for internal signals. + +`timescale 1 ps / 1 ps + + +module IOBUF_LVCMOS18_S_2 (O, IO, I, T); + + output O; + + inout IO; + + input I, T; + + wire ts; + + tri0 GTS = glbl.GTS; + + or O1 (ts, GTS, T); + bufif0 T1 (IO, I, ts); + + buf B1 (O, IO); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IOBUF_LVCMOS18_S_4.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IOBUF_LVCMOS18_S_4.v new file mode 100644 index 0000000..28ad1f7 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IOBUF_LVCMOS18_S_4.v @@ -0,0 +1,43 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/IOBUF_LVCMOS18_S_4.v,v 1.6 2007/05/23 21:43:37 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Bi-Directional Buffer with LVCMOS18 I/O Standard Slow Slew 4 mA Drive +// /___/ /\ Filename : IOBUF_LVCMOS18_S_4.v +// \ \ / \ Timestamp : Thu Mar 25 16:42:43 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. +// 05/23/07 - Added wire declaration for internal signals. + +`timescale 1 ps / 1 ps + + +module IOBUF_LVCMOS18_S_4 (O, IO, I, T); + + output O; + + inout IO; + + input I, T; + + wire ts; + + tri0 GTS = glbl.GTS; + + or O1 (ts, GTS, T); + bufif0 T1 (IO, I, ts); + + buf B1 (O, IO); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IOBUF_LVCMOS18_S_6.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IOBUF_LVCMOS18_S_6.v new file mode 100644 index 0000000..14b480e --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IOBUF_LVCMOS18_S_6.v @@ -0,0 +1,43 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/IOBUF_LVCMOS18_S_6.v,v 1.6 2007/05/23 21:43:37 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Bi-Directional Buffer with LVCMOS18 I/O Standard Slow Slew 6 mA Drive +// /___/ /\ Filename : IOBUF_LVCMOS18_S_6.v +// \ \ / \ Timestamp : Thu Mar 25 16:42:43 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. +// 05/23/07 - Added wire declaration for internal signals. + +`timescale 1 ps / 1 ps + + +module IOBUF_LVCMOS18_S_6 (O, IO, I, T); + + output O; + + inout IO; + + input I, T; + + wire ts; + + tri0 GTS = glbl.GTS; + + or O1 (ts, GTS, T); + bufif0 T1 (IO, I, ts); + + buf B1 (O, IO); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IOBUF_LVCMOS18_S_8.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IOBUF_LVCMOS18_S_8.v new file mode 100644 index 0000000..463e42a --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IOBUF_LVCMOS18_S_8.v @@ -0,0 +1,43 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/IOBUF_LVCMOS18_S_8.v,v 1.6 2007/05/23 21:43:37 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Bi-Directional Buffer with LVCMOS18 I/O Standard Slow Slew 8 mA Drive +// /___/ /\ Filename : IOBUF_LVCMOS18_S_8.v +// \ \ / \ Timestamp : Thu Mar 25 16:42:43 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. +// 05/23/07 - Added wire declaration for internal signals. + +`timescale 1 ps / 1 ps + + +module IOBUF_LVCMOS18_S_8 (O, IO, I, T); + + output O; + + inout IO; + + input I, T; + + wire ts; + + tri0 GTS = glbl.GTS; + + or O1 (ts, GTS, T); + bufif0 T1 (IO, I, ts); + + buf B1 (O, IO); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IOBUF_LVCMOS2.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IOBUF_LVCMOS2.v new file mode 100644 index 0000000..426525a --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IOBUF_LVCMOS2.v @@ -0,0 +1,43 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/IOBUF_LVCMOS2.v,v 1.6 2007/05/23 21:43:38 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Bi-Directional Buffer with LVCMOS2 I/O Standard +// /___/ /\ Filename : IOBUF_LVCMOS2.v +// \ \ / \ Timestamp : Thu Mar 25 16:42:43 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. +// 05/23/07 - Added wire declaration for internal signals. + +`timescale 1 ps / 1 ps + + +module IOBUF_LVCMOS2 (O, IO, I, T); + + output O; + + inout IO; + + input I, T; + + wire ts; + + tri0 GTS = glbl.GTS; + + or O1 (ts, GTS, T); + bufif0 T1 (IO, I, ts); + + buf B1 (O, IO); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IOBUF_LVCMOS25.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IOBUF_LVCMOS25.v new file mode 100644 index 0000000..00189b2 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IOBUF_LVCMOS25.v @@ -0,0 +1,43 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/IOBUF_LVCMOS25.v,v 1.6 2007/05/23 21:43:38 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Bi-Directional Buffer with LVCMOS25 I/O Standard +// /___/ /\ Filename : IOBUF_LVCMOS25.v +// \ \ / \ Timestamp : Thu Mar 25 16:42:44 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. +// 05/23/07 - Added wire declaration for internal signals. + +`timescale 1 ps / 1 ps + + +module IOBUF_LVCMOS25 (O, IO, I, T); + + output O; + + inout IO; + + input I, T; + + wire ts; + + tri0 GTS = glbl.GTS; + + or O1 (ts, GTS, T); + bufif0 T1 (IO, I, ts); + + buf B1 (O, IO); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IOBUF_LVCMOS25_F_12.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IOBUF_LVCMOS25_F_12.v new file mode 100644 index 0000000..008143e --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IOBUF_LVCMOS25_F_12.v @@ -0,0 +1,43 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/IOBUF_LVCMOS25_F_12.v,v 1.6 2007/05/23 21:43:37 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Bi-Directional Buffer with LVCMOS25 I/O Standard Fast Slew 12 mA Drive +// /___/ /\ Filename : IOBUF_LVCMOS25_F_12.v +// \ \ / \ Timestamp : Thu Mar 25 16:42:44 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. +// 05/23/07 - Added wire declaration for internal signals. + +`timescale 1 ps / 1 ps + + +module IOBUF_LVCMOS25_F_12 (O, IO, I, T); + + output O; + + inout IO; + + input I, T; + + wire ts; + + tri0 GTS = glbl.GTS; + + or O1 (ts, GTS, T); + bufif0 T1 (IO, I, ts); + + buf B1 (O, IO); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IOBUF_LVCMOS25_F_16.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IOBUF_LVCMOS25_F_16.v new file mode 100644 index 0000000..20340f8 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IOBUF_LVCMOS25_F_16.v @@ -0,0 +1,43 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/IOBUF_LVCMOS25_F_16.v,v 1.6 2007/05/23 21:43:37 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Bi-Directional Buffer with LVCMOS25 I/O Standard Fast Slew 16 mA Drive +// /___/ /\ Filename : IOBUF_LVCMOS25_F_16.v +// \ \ / \ Timestamp : Thu Mar 25 16:42:44 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. +// 05/23/07 - Added wire declaration for internal signals. + +`timescale 1 ps / 1 ps + + +module IOBUF_LVCMOS25_F_16 (O, IO, I, T); + + output O; + + inout IO; + + input I, T; + + wire ts; + + tri0 GTS = glbl.GTS; + + or O1 (ts, GTS, T); + bufif0 T1 (IO, I, ts); + + buf B1 (O, IO); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IOBUF_LVCMOS25_F_2.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IOBUF_LVCMOS25_F_2.v new file mode 100644 index 0000000..5a2020f --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IOBUF_LVCMOS25_F_2.v @@ -0,0 +1,43 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/IOBUF_LVCMOS25_F_2.v,v 1.6 2007/05/23 21:43:37 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Bi-Directional Buffer with LVCMOS25 I/O Standard Fast Slew 2 mA Drive +// /___/ /\ Filename : IOBUF_LVCMOS25_F_2.v +// \ \ / \ Timestamp : Thu Mar 25 16:42:44 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. +// 05/23/07 - Added wire declaration for internal signals. + +`timescale 1 ps / 1 ps + + +module IOBUF_LVCMOS25_F_2 (O, IO, I, T); + + output O; + + inout IO; + + input I, T; + + wire ts; + + tri0 GTS = glbl.GTS; + + or O1 (ts, GTS, T); + bufif0 T1 (IO, I, ts); + + buf B1 (O, IO); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IOBUF_LVCMOS25_F_24.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IOBUF_LVCMOS25_F_24.v new file mode 100644 index 0000000..8319fe4 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IOBUF_LVCMOS25_F_24.v @@ -0,0 +1,43 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/IOBUF_LVCMOS25_F_24.v,v 1.6 2007/05/23 21:43:37 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Bi-Directional Buffer with LVCMOS25 I/O Standard Fast Slew 24 mA Drive +// /___/ /\ Filename : IOBUF_LVCMOS25_F_24.v +// \ \ / \ Timestamp : Thu Mar 25 16:42:44 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. +// 05/23/07 - Added wire declaration for internal signals. + +`timescale 1 ps / 1 ps + + +module IOBUF_LVCMOS25_F_24 (O, IO, I, T); + + output O; + + inout IO; + + input I, T; + + wire ts; + + tri0 GTS = glbl.GTS; + + or O1 (ts, GTS, T); + bufif0 T1 (IO, I, ts); + + buf B1 (O, IO); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IOBUF_LVCMOS25_F_4.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IOBUF_LVCMOS25_F_4.v new file mode 100644 index 0000000..bee3ec1 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IOBUF_LVCMOS25_F_4.v @@ -0,0 +1,43 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/IOBUF_LVCMOS25_F_4.v,v 1.6 2007/05/23 21:43:37 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Bi-Directional Buffer with LVCMOS25 I/O Standard Fast Slew 4 mA Drive +// /___/ /\ Filename : IOBUF_LVCMOS25_F_4.v +// \ \ / \ Timestamp : Thu Mar 25 16:42:44 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. +// 05/23/07 - Added wire declaration for internal signals. + +`timescale 1 ps / 1 ps + + +module IOBUF_LVCMOS25_F_4 (O, IO, I, T); + + output O; + + inout IO; + + input I, T; + + wire ts; + + tri0 GTS = glbl.GTS; + + or O1 (ts, GTS, T); + bufif0 T1 (IO, I, ts); + + buf B1 (O, IO); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IOBUF_LVCMOS25_F_6.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IOBUF_LVCMOS25_F_6.v new file mode 100644 index 0000000..f0de644 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IOBUF_LVCMOS25_F_6.v @@ -0,0 +1,43 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/IOBUF_LVCMOS25_F_6.v,v 1.6 2007/05/23 21:43:37 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Bi-Directional Buffer with LVCMOS25 I/O Standard Fast Slew 6 mA Drive +// /___/ /\ Filename : IOBUF_LVCMOS25_F_6.v +// \ \ / \ Timestamp : Thu Mar 25 16:42:44 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. +// 05/23/07 - Added wire declaration for internal signals. + +`timescale 1 ps / 1 ps + + +module IOBUF_LVCMOS25_F_6 (O, IO, I, T); + + output O; + + inout IO; + + input I, T; + + wire ts; + + tri0 GTS = glbl.GTS; + + or O1 (ts, GTS, T); + bufif0 T1 (IO, I, ts); + + buf B1 (O, IO); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IOBUF_LVCMOS25_F_8.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IOBUF_LVCMOS25_F_8.v new file mode 100644 index 0000000..765395e --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IOBUF_LVCMOS25_F_8.v @@ -0,0 +1,43 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/IOBUF_LVCMOS25_F_8.v,v 1.6 2007/05/23 21:43:37 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Bi-Directional Buffer with LVCMOS25 I/O Standard Fast Slew 8 mA Drive +// /___/ /\ Filename : IOBUF_LVCMOS25_F_8.v +// \ \ / \ Timestamp : Thu Mar 25 16:42:44 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. +// 05/23/07 - Added wire declaration for internal signals. + +`timescale 1 ps / 1 ps + + +module IOBUF_LVCMOS25_F_8 (O, IO, I, T); + + output O; + + inout IO; + + input I, T; + + wire ts; + + tri0 GTS = glbl.GTS; + + or O1 (ts, GTS, T); + bufif0 T1 (IO, I, ts); + + buf B1 (O, IO); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IOBUF_LVCMOS25_S_12.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IOBUF_LVCMOS25_S_12.v new file mode 100644 index 0000000..09716c1 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IOBUF_LVCMOS25_S_12.v @@ -0,0 +1,43 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/IOBUF_LVCMOS25_S_12.v,v 1.6 2007/05/23 21:43:37 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Bi-Directional Buffer with LVCMOS25 I/O Standard Slow Slew 12 mA Drive +// /___/ /\ Filename : IOBUF_LVCMOS25_S_12.v +// \ \ / \ Timestamp : Thu Mar 25 16:42:44 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. +// 05/23/07 - Added wire declaration for internal signals. + +`timescale 1 ps / 1 ps + + +module IOBUF_LVCMOS25_S_12 (O, IO, I, T); + + output O; + + inout IO; + + input I, T; + + wire ts; + + tri0 GTS = glbl.GTS; + + or O1 (ts, GTS, T); + bufif0 T1 (IO, I, ts); + + buf B1 (O, IO); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IOBUF_LVCMOS25_S_16.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IOBUF_LVCMOS25_S_16.v new file mode 100644 index 0000000..a0798e7 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IOBUF_LVCMOS25_S_16.v @@ -0,0 +1,43 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/IOBUF_LVCMOS25_S_16.v,v 1.6 2007/05/23 21:43:37 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Bi-Directional Buffer with LVCMOS25 I/O Standard Slow Slew 16 mA Drive +// /___/ /\ Filename : IOBUF_LVCMOS25_S_16.v +// \ \ / \ Timestamp : Thu Mar 25 16:42:44 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. +// 05/23/07 - Added wire declaration for internal signals. + +`timescale 1 ps / 1 ps + + +module IOBUF_LVCMOS25_S_16 (O, IO, I, T); + + output O; + + inout IO; + + input I, T; + + wire ts; + + tri0 GTS = glbl.GTS; + + or O1 (ts, GTS, T); + bufif0 T1 (IO, I, ts); + + buf B1 (O, IO); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IOBUF_LVCMOS25_S_2.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IOBUF_LVCMOS25_S_2.v new file mode 100644 index 0000000..1d3945a --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IOBUF_LVCMOS25_S_2.v @@ -0,0 +1,43 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/IOBUF_LVCMOS25_S_2.v,v 1.6 2007/05/23 21:43:38 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Bi-Directional Buffer with LVCMOS25 I/O Standard Slow Slew 2 mA Drive +// /___/ /\ Filename : IOBUF_LVCMOS25_S_2.v +// \ \ / \ Timestamp : Thu Mar 25 16:42:45 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. +// 05/23/07 - Added wire declaration for internal signals. + +`timescale 1 ps / 1 ps + + +module IOBUF_LVCMOS25_S_2 (O, IO, I, T); + + output O; + + inout IO; + + input I, T; + + wire ts; + + tri0 GTS = glbl.GTS; + + or O1 (ts, GTS, T); + bufif0 T1 (IO, I, ts); + + buf B1 (O, IO); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IOBUF_LVCMOS25_S_24.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IOBUF_LVCMOS25_S_24.v new file mode 100644 index 0000000..714e6d4 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IOBUF_LVCMOS25_S_24.v @@ -0,0 +1,43 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/IOBUF_LVCMOS25_S_24.v,v 1.6 2007/05/23 21:43:37 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Bi-Directional Buffer with LVCMOS25 I/O Standard Slow Slew 24 mA Drive +// /___/ /\ Filename : IOBUF_LVCMOS25_S_24.v +// \ \ / \ Timestamp : Thu Mar 25 16:42:45 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. +// 05/23/07 - Added wire declaration for internal signals. + +`timescale 1 ps / 1 ps + + +module IOBUF_LVCMOS25_S_24 (O, IO, I, T); + + output O; + + inout IO; + + input I, T; + + wire ts; + + tri0 GTS = glbl.GTS; + + or O1 (ts, GTS, T); + bufif0 T1 (IO, I, ts); + + buf B1 (O, IO); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IOBUF_LVCMOS25_S_4.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IOBUF_LVCMOS25_S_4.v new file mode 100644 index 0000000..6cfaa39 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IOBUF_LVCMOS25_S_4.v @@ -0,0 +1,43 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/IOBUF_LVCMOS25_S_4.v,v 1.6 2007/05/23 21:43:38 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Bi-Directional Buffer with LVCMOS25 I/O Standard Slow Slew 4 mA Drive +// /___/ /\ Filename : IOBUF_LVCMOS25_S_4.v +// \ \ / \ Timestamp : Thu Mar 25 16:42:45 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. +// 05/23/07 - Added wire declaration for internal signals. + +`timescale 1 ps / 1 ps + + +module IOBUF_LVCMOS25_S_4 (O, IO, I, T); + + output O; + + inout IO; + + input I, T; + + wire ts; + + tri0 GTS = glbl.GTS; + + or O1 (ts, GTS, T); + bufif0 T1 (IO, I, ts); + + buf B1 (O, IO); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IOBUF_LVCMOS25_S_6.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IOBUF_LVCMOS25_S_6.v new file mode 100644 index 0000000..efad910 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IOBUF_LVCMOS25_S_6.v @@ -0,0 +1,43 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/IOBUF_LVCMOS25_S_6.v,v 1.6 2007/05/23 21:43:38 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Bi-Directional Buffer with LVCMOS25 I/O Standard Slow Slew 6 mA Drive +// /___/ /\ Filename : IOBUF_LVCMOS25_S_6.v +// \ \ / \ Timestamp : Thu Mar 25 16:42:45 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. +// 05/23/07 - Added wire declaration for internal signals. + +`timescale 1 ps / 1 ps + + +module IOBUF_LVCMOS25_S_6 (O, IO, I, T); + + output O; + + inout IO; + + input I, T; + + wire ts; + + tri0 GTS = glbl.GTS; + + or O1 (ts, GTS, T); + bufif0 T1 (IO, I, ts); + + buf B1 (O, IO); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IOBUF_LVCMOS25_S_8.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IOBUF_LVCMOS25_S_8.v new file mode 100644 index 0000000..05b6625 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IOBUF_LVCMOS25_S_8.v @@ -0,0 +1,43 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/IOBUF_LVCMOS25_S_8.v,v 1.6 2007/05/23 21:43:38 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Bi-Directional Buffer with LVCMOS25 I/O Standard Slow Slew 8 mA Drive +// /___/ /\ Filename : IOBUF_LVCMOS25_S_8.v +// \ \ / \ Timestamp : Thu Mar 25 16:42:45 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. +// 05/23/07 - Added wire declaration for internal signals. + +`timescale 1 ps / 1 ps + + +module IOBUF_LVCMOS25_S_8 (O, IO, I, T); + + output O; + + inout IO; + + input I, T; + + wire ts; + + tri0 GTS = glbl.GTS; + + or O1 (ts, GTS, T); + bufif0 T1 (IO, I, ts); + + buf B1 (O, IO); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IOBUF_LVCMOS33.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IOBUF_LVCMOS33.v new file mode 100644 index 0000000..4b6ce0a --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IOBUF_LVCMOS33.v @@ -0,0 +1,43 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/IOBUF_LVCMOS33.v,v 1.6 2007/05/23 21:43:38 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Bi-Directional Buffer with LVCMOS33 I/O Standard +// /___/ /\ Filename : IOBUF_LVCMOS33.v +// \ \ / \ Timestamp : Thu Mar 25 16:42:45 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. +// 05/23/07 - Added wire declaration for internal signals. + +`timescale 1 ps / 1 ps + + +module IOBUF_LVCMOS33 (O, IO, I, T); + + output O; + + inout IO; + + input I, T; + + wire ts; + + tri0 GTS = glbl.GTS; + + or O1 (ts, GTS, T); + bufif0 T1 (IO, I, ts); + + buf B1 (O, IO); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IOBUF_LVCMOS33_F_12.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IOBUF_LVCMOS33_F_12.v new file mode 100644 index 0000000..8dac0da --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IOBUF_LVCMOS33_F_12.v @@ -0,0 +1,43 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/IOBUF_LVCMOS33_F_12.v,v 1.6 2007/05/23 21:43:38 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Bi-Directional Buffer with LVCMOS33 I/O Standard Fast Slew 12 mA Drive +// /___/ /\ Filename : IOBUF_LVCMOS33_F_12.v +// \ \ / \ Timestamp : Thu Mar 25 16:42:45 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. +// 05/23/07 - Added wire declaration for internal signals. + +`timescale 1 ps / 1 ps + + +module IOBUF_LVCMOS33_F_12 (O, IO, I, T); + + output O; + + inout IO; + + input I, T; + + wire ts; + + tri0 GTS = glbl.GTS; + + or O1 (ts, GTS, T); + bufif0 T1 (IO, I, ts); + + buf B1 (O, IO); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IOBUF_LVCMOS33_F_16.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IOBUF_LVCMOS33_F_16.v new file mode 100644 index 0000000..65dc5c6 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IOBUF_LVCMOS33_F_16.v @@ -0,0 +1,43 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/IOBUF_LVCMOS33_F_16.v,v 1.6 2007/05/23 21:43:38 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Bi-Directional Buffer with LVCMOS33 I/O Standard Fast Slew 16 mA Drive +// /___/ /\ Filename : IOBUF_LVCMOS33_F_16.v +// \ \ / \ Timestamp : Thu Mar 25 16:42:45 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. +// 05/23/07 - Added wire declaration for internal signals. + +`timescale 1 ps / 1 ps + + +module IOBUF_LVCMOS33_F_16 (O, IO, I, T); + + output O; + + inout IO; + + input I, T; + + wire ts; + + tri0 GTS = glbl.GTS; + + or O1 (ts, GTS, T); + bufif0 T1 (IO, I, ts); + + buf B1 (O, IO); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IOBUF_LVCMOS33_F_2.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IOBUF_LVCMOS33_F_2.v new file mode 100644 index 0000000..f986b8b --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IOBUF_LVCMOS33_F_2.v @@ -0,0 +1,43 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/IOBUF_LVCMOS33_F_2.v,v 1.6 2007/05/23 21:43:38 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Bi-Directional Buffer with LVCMOS33 I/O Standard Fast Slew 2 mA Drive +// /___/ /\ Filename : IOBUF_LVCMOS33_F_2.v +// \ \ / \ Timestamp : Thu Mar 25 16:42:45 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. +// 05/23/07 - Added wire declaration for internal signals. + +`timescale 1 ps / 1 ps + + +module IOBUF_LVCMOS33_F_2 (O, IO, I, T); + + output O; + + inout IO; + + input I, T; + + wire ts; + + tri0 GTS = glbl.GTS; + + or O1 (ts, GTS, T); + bufif0 T1 (IO, I, ts); + + buf B1 (O, IO); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IOBUF_LVCMOS33_F_24.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IOBUF_LVCMOS33_F_24.v new file mode 100644 index 0000000..8e43aef --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IOBUF_LVCMOS33_F_24.v @@ -0,0 +1,43 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/IOBUF_LVCMOS33_F_24.v,v 1.6 2007/05/23 21:43:38 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Bi-Directional Buffer with LVCMOS33 I/O Standard Fast Slew 24 mA Drive +// /___/ /\ Filename : IOBUF_LVCMOS33_F_24.v +// \ \ / \ Timestamp : Thu Mar 25 16:42:45 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. +// 05/23/07 - Added wire declaration for internal signals. + +`timescale 1 ps / 1 ps + + +module IOBUF_LVCMOS33_F_24 (O, IO, I, T); + + output O; + + inout IO; + + input I, T; + + wire ts; + + tri0 GTS = glbl.GTS; + + or O1 (ts, GTS, T); + bufif0 T1 (IO, I, ts); + + buf B1 (O, IO); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IOBUF_LVCMOS33_F_4.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IOBUF_LVCMOS33_F_4.v new file mode 100644 index 0000000..427f934 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IOBUF_LVCMOS33_F_4.v @@ -0,0 +1,43 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/IOBUF_LVCMOS33_F_4.v,v 1.6 2007/05/23 21:43:38 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Bi-Directional Buffer with LVCMOS33 I/O Standard Fast Slew 4 mA Drive +// /___/ /\ Filename : IOBUF_LVCMOS33_F_4.v +// \ \ / \ Timestamp : Thu Mar 25 16:42:46 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. +// 05/23/07 - Added wire declaration for internal signals. + +`timescale 1 ps / 1 ps + + +module IOBUF_LVCMOS33_F_4 (O, IO, I, T); + + output O; + + inout IO; + + input I, T; + + wire ts; + + tri0 GTS = glbl.GTS; + + or O1 (ts, GTS, T); + bufif0 T1 (IO, I, ts); + + buf B1 (O, IO); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IOBUF_LVCMOS33_F_6.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IOBUF_LVCMOS33_F_6.v new file mode 100644 index 0000000..e25f60d --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IOBUF_LVCMOS33_F_6.v @@ -0,0 +1,43 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/IOBUF_LVCMOS33_F_6.v,v 1.6 2007/05/23 21:43:38 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Bi-Directional Buffer with LVCMOS33 I/O Standard Fast Slew 6 mA Drive +// /___/ /\ Filename : IOBUF_LVCMOS33_F_6.v +// \ \ / \ Timestamp : Thu Mar 25 16:42:46 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. +// 05/23/07 - Added wire declaration for internal signals. + +`timescale 1 ps / 1 ps + + +module IOBUF_LVCMOS33_F_6 (O, IO, I, T); + + output O; + + inout IO; + + input I, T; + + wire ts; + + tri0 GTS = glbl.GTS; + + or O1 (ts, GTS, T); + bufif0 T1 (IO, I, ts); + + buf B1 (O, IO); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IOBUF_LVCMOS33_F_8.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IOBUF_LVCMOS33_F_8.v new file mode 100644 index 0000000..0515cb6 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IOBUF_LVCMOS33_F_8.v @@ -0,0 +1,43 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/IOBUF_LVCMOS33_F_8.v,v 1.6 2007/05/23 21:43:38 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Bi-Directional Buffer with LVCMOS33 I/O Standard Fast Slew 8 mA Drive +// /___/ /\ Filename : IOBUF_LVCMOS33_F_8.v +// \ \ / \ Timestamp : Thu Mar 25 16:42:46 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. +// 05/23/07 - Added wire declaration for internal signals. + +`timescale 1 ps / 1 ps + + +module IOBUF_LVCMOS33_F_8 (O, IO, I, T); + + output O; + + inout IO; + + input I, T; + + wire ts; + + tri0 GTS = glbl.GTS; + + or O1 (ts, GTS, T); + bufif0 T1 (IO, I, ts); + + buf B1 (O, IO); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IOBUF_LVCMOS33_S_12.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IOBUF_LVCMOS33_S_12.v new file mode 100644 index 0000000..e6e4850 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IOBUF_LVCMOS33_S_12.v @@ -0,0 +1,43 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/IOBUF_LVCMOS33_S_12.v,v 1.6 2007/05/23 21:43:38 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Bi-Directional Buffer with LVCMOS33 I/O Standard Slow Slew 12 mA Drive +// /___/ /\ Filename : IOBUF_LVCMOS33_S_12.v +// \ \ / \ Timestamp : Thu Mar 25 16:42:46 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. +// 05/23/07 - Added wire declaration for internal signals. + +`timescale 1 ps / 1 ps + + +module IOBUF_LVCMOS33_S_12 (O, IO, I, T); + + output O; + + inout IO; + + input I, T; + + wire ts; + + tri0 GTS = glbl.GTS; + + or O1 (ts, GTS, T); + bufif0 T1 (IO, I, ts); + + buf B1 (O, IO); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IOBUF_LVCMOS33_S_16.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IOBUF_LVCMOS33_S_16.v new file mode 100644 index 0000000..13309a7 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IOBUF_LVCMOS33_S_16.v @@ -0,0 +1,43 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/IOBUF_LVCMOS33_S_16.v,v 1.6 2007/05/23 21:43:38 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Bi-Directional Buffer with LVCMOS33 I/O Standard Slow Slew 16 mA Drive +// /___/ /\ Filename : IOBUF_LVCMOS33_S_16.v +// \ \ / \ Timestamp : Thu Mar 25 16:42:46 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. +// 05/23/07 - Added wire declaration for internal signals. + +`timescale 1 ps / 1 ps + + +module IOBUF_LVCMOS33_S_16 (O, IO, I, T); + + output O; + + inout IO; + + input I, T; + + wire ts; + + tri0 GTS = glbl.GTS; + + or O1 (ts, GTS, T); + bufif0 T1 (IO, I, ts); + + buf B1 (O, IO); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IOBUF_LVCMOS33_S_2.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IOBUF_LVCMOS33_S_2.v new file mode 100644 index 0000000..08e6bc0 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IOBUF_LVCMOS33_S_2.v @@ -0,0 +1,43 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/IOBUF_LVCMOS33_S_2.v,v 1.6 2007/05/23 21:43:38 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Bi-Directional Buffer with LVCMOS33 I/O Standard Slow Slew 2 mA Drive +// /___/ /\ Filename : IOBUF_LVCMOS33_S_2.v +// \ \ / \ Timestamp : Thu Mar 25 16:42:46 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. +// 05/23/07 - Added wire declaration for internal signals. + +`timescale 1 ps / 1 ps + + +module IOBUF_LVCMOS33_S_2 (O, IO, I, T); + + output O; + + inout IO; + + input I, T; + + wire ts; + + tri0 GTS = glbl.GTS; + + or O1 (ts, GTS, T); + bufif0 T1 (IO, I, ts); + + buf B1 (O, IO); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IOBUF_LVCMOS33_S_24.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IOBUF_LVCMOS33_S_24.v new file mode 100644 index 0000000..245e8a6 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IOBUF_LVCMOS33_S_24.v @@ -0,0 +1,43 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/IOBUF_LVCMOS33_S_24.v,v 1.6 2007/05/23 21:43:38 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Bi-Directional Buffer with LVCMOS33 I/O Standard Slow Slew 24 mA Drive +// /___/ /\ Filename : IOBUF_LVCMOS33_S_24.v +// \ \ / \ Timestamp : Thu Mar 25 16:42:46 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. +// 05/23/07 - Added wire declaration for internal signals. + +`timescale 1 ps / 1 ps + + +module IOBUF_LVCMOS33_S_24 (O, IO, I, T); + + output O; + + inout IO; + + input I, T; + + wire ts; + + tri0 GTS = glbl.GTS; + + or O1 (ts, GTS, T); + bufif0 T1 (IO, I, ts); + + buf B1 (O, IO); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IOBUF_LVCMOS33_S_4.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IOBUF_LVCMOS33_S_4.v new file mode 100644 index 0000000..ef42b47 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IOBUF_LVCMOS33_S_4.v @@ -0,0 +1,43 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/IOBUF_LVCMOS33_S_4.v,v 1.6 2007/05/23 21:43:38 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Bi-Directional Buffer with LVCMOS33 I/O Standard Slow Slew 4 mA Drive +// /___/ /\ Filename : IOBUF_LVCMOS33_S_4.v +// \ \ / \ Timestamp : Thu Mar 25 16:42:46 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. +// 05/23/07 - Added wire declaration for internal signals. + +`timescale 1 ps / 1 ps + + +module IOBUF_LVCMOS33_S_4 (O, IO, I, T); + + output O; + + inout IO; + + input I, T; + + wire ts; + + tri0 GTS = glbl.GTS; + + or O1 (ts, GTS, T); + bufif0 T1 (IO, I, ts); + + buf B1 (O, IO); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IOBUF_LVCMOS33_S_6.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IOBUF_LVCMOS33_S_6.v new file mode 100644 index 0000000..43e6960 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IOBUF_LVCMOS33_S_6.v @@ -0,0 +1,43 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/IOBUF_LVCMOS33_S_6.v,v 1.6 2007/05/23 21:43:38 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Bi-Directional Buffer with LVCMOS33 I/O Standard Slow Slew 6 mA Drive +// /___/ /\ Filename : IOBUF_LVCMOS33_S_6.v +// \ \ / \ Timestamp : Thu Mar 25 16:42:46 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. +// 05/23/07 - Added wire declaration for internal signals. + +`timescale 1 ps / 1 ps + + +module IOBUF_LVCMOS33_S_6 (O, IO, I, T); + + output O; + + inout IO; + + input I, T; + + wire ts; + + tri0 GTS = glbl.GTS; + + or O1 (ts, GTS, T); + bufif0 T1 (IO, I, ts); + + buf B1 (O, IO); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IOBUF_LVCMOS33_S_8.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IOBUF_LVCMOS33_S_8.v new file mode 100644 index 0000000..1a4c265 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IOBUF_LVCMOS33_S_8.v @@ -0,0 +1,43 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/IOBUF_LVCMOS33_S_8.v,v 1.6 2007/05/23 21:43:38 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Bi-Directional Buffer with LVCMOS33 I/O Standard Slow Slew 8 mA Drive +// /___/ /\ Filename : IOBUF_LVCMOS33_S_8.v +// \ \ / \ Timestamp : Thu Mar 25 16:42:46 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. +// 05/23/07 - Added wire declaration for internal signals. + +`timescale 1 ps / 1 ps + + +module IOBUF_LVCMOS33_S_8 (O, IO, I, T); + + output O; + + inout IO; + + input I, T; + + wire ts; + + tri0 GTS = glbl.GTS; + + or O1 (ts, GTS, T); + bufif0 T1 (IO, I, ts); + + buf B1 (O, IO); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IOBUF_LVDCI_15.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IOBUF_LVDCI_15.v new file mode 100644 index 0000000..36aee69 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IOBUF_LVDCI_15.v @@ -0,0 +1,43 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/IOBUF_LVDCI_15.v,v 1.6 2007/05/23 21:43:38 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Bi-Directional Buffer with LVDCI_15 I/O Standard +// /___/ /\ Filename : IOBUF_LVDCI_15.v +// \ \ / \ Timestamp : Thu Mar 25 16:42:46 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. +// 05/23/07 - Added wire declaration for internal signals. + +`timescale 1 ps / 1 ps + + +module IOBUF_LVDCI_15 (O, IO, I, T); + + output O; + + inout IO; + + input I, T; + + wire ts; + + tri0 GTS = glbl.GTS; + + or O1 (ts, GTS, T); + bufif0 T1 (IO, I, ts); + + buf B1 (O, IO); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IOBUF_LVDCI_18.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IOBUF_LVDCI_18.v new file mode 100644 index 0000000..ec3bb3b --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IOBUF_LVDCI_18.v @@ -0,0 +1,43 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/IOBUF_LVDCI_18.v,v 1.6 2007/05/23 21:43:38 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Bi-Directional Buffer with LVDCI_18 I/O Standard +// /___/ /\ Filename : IOBUF_LVDCI_18.v +// \ \ / \ Timestamp : Thu Mar 25 16:42:47 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. +// 05/23/07 - Added wire declaration for internal signals. + +`timescale 1 ps / 1 ps + + +module IOBUF_LVDCI_18 (O, IO, I, T); + + output O; + + inout IO; + + input I, T; + + wire ts; + + tri0 GTS = glbl.GTS; + + or O1 (ts, GTS, T); + bufif0 T1 (IO, I, ts); + + buf B1 (O, IO); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IOBUF_LVDCI_25.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IOBUF_LVDCI_25.v new file mode 100644 index 0000000..a8d7b58 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IOBUF_LVDCI_25.v @@ -0,0 +1,43 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/IOBUF_LVDCI_25.v,v 1.6 2007/05/23 21:43:38 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Bi-Directional Buffer with LVDCI_25 I/O Standard +// /___/ /\ Filename : IOBUF_LVDCI_25.v +// \ \ / \ Timestamp : Thu Mar 25 16:42:47 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. +// 05/23/07 - Added wire declaration for internal signals. + +`timescale 1 ps / 1 ps + + +module IOBUF_LVDCI_25 (O, IO, I, T); + + output O; + + inout IO; + + input I, T; + + wire ts; + + tri0 GTS = glbl.GTS; + + or O1 (ts, GTS, T); + bufif0 T1 (IO, I, ts); + + buf B1 (O, IO); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IOBUF_LVDCI_33.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IOBUF_LVDCI_33.v new file mode 100644 index 0000000..0ccacb7 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IOBUF_LVDCI_33.v @@ -0,0 +1,43 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/IOBUF_LVDCI_33.v,v 1.6 2007/05/23 21:43:38 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Bi-Directional Buffer with LVDCI_33 I/O Standard +// /___/ /\ Filename : IOBUF_LVDCI_33.v +// \ \ / \ Timestamp : Thu Mar 25 16:42:47 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. +// 05/23/07 - Added wire declaration for internal signals. + +`timescale 1 ps / 1 ps + + +module IOBUF_LVDCI_33 (O, IO, I, T); + + output O; + + inout IO; + + input I, T; + + wire ts; + + tri0 GTS = glbl.GTS; + + or O1 (ts, GTS, T); + bufif0 T1 (IO, I, ts); + + buf B1 (O, IO); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IOBUF_LVDCI_DV2_15.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IOBUF_LVDCI_DV2_15.v new file mode 100644 index 0000000..428b9f2 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IOBUF_LVDCI_DV2_15.v @@ -0,0 +1,43 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/IOBUF_LVDCI_DV2_15.v,v 1.6 2007/05/23 21:43:38 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Bi-Directional Buffer with LVDCI_DV2_15 I/O Standard +// /___/ /\ Filename : IOBUF_LVDCI_DV2_15.v +// \ \ / \ Timestamp : Thu Mar 25 16:42:47 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. +// 05/23/07 - Added wire declaration for internal signals. + +`timescale 1 ps / 1 ps + + +module IOBUF_LVDCI_DV2_15 (O, IO, I, T); + + output O; + + inout IO; + + input I, T; + + wire ts; + + tri0 GTS = glbl.GTS; + + or O1 (ts, GTS, T); + bufif0 T1 (IO, I, ts); + + buf B1 (O, IO); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IOBUF_LVDCI_DV2_18.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IOBUF_LVDCI_DV2_18.v new file mode 100644 index 0000000..6900abc --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IOBUF_LVDCI_DV2_18.v @@ -0,0 +1,43 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/IOBUF_LVDCI_DV2_18.v,v 1.6 2007/05/23 21:43:38 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Bi-Directional Buffer with LVDCI_DV2_18 I/O Standard +// /___/ /\ Filename : IOBUF_LVDCI_DV2_18.v +// \ \ / \ Timestamp : Thu Mar 25 16:42:47 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. +// 05/23/07 - Added wire declaration for internal signals. + +`timescale 1 ps / 1 ps + + +module IOBUF_LVDCI_DV2_18 (O, IO, I, T); + + output O; + + inout IO; + + input I, T; + + wire ts; + + tri0 GTS = glbl.GTS; + + or O1 (ts, GTS, T); + bufif0 T1 (IO, I, ts); + + buf B1 (O, IO); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IOBUF_LVDCI_DV2_25.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IOBUF_LVDCI_DV2_25.v new file mode 100644 index 0000000..58a1580 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IOBUF_LVDCI_DV2_25.v @@ -0,0 +1,43 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/IOBUF_LVDCI_DV2_25.v,v 1.6 2007/05/23 21:43:38 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Bi-Directional Buffer with LVDCI_DV2_25 I/O Standard +// /___/ /\ Filename : IOBUF_LVDCI_DV2_25.v +// \ \ / \ Timestamp : Thu Mar 25 16:42:47 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. +// 05/23/07 - Added wire declaration for internal signals. + +`timescale 1 ps / 1 ps + + +module IOBUF_LVDCI_DV2_25 (O, IO, I, T); + + output O; + + inout IO; + + input I, T; + + wire ts; + + tri0 GTS = glbl.GTS; + + or O1 (ts, GTS, T); + bufif0 T1 (IO, I, ts); + + buf B1 (O, IO); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IOBUF_LVDCI_DV2_33.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IOBUF_LVDCI_DV2_33.v new file mode 100644 index 0000000..cf678d8 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IOBUF_LVDCI_DV2_33.v @@ -0,0 +1,43 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/IOBUF_LVDCI_DV2_33.v,v 1.6 2007/05/23 21:43:38 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Bi-Directional Buffer with LVDCI_DV2_33 I/O Standard +// /___/ /\ Filename : IOBUF_LVDCI_DV2_33.v +// \ \ / \ Timestamp : Thu Mar 25 16:42:47 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. +// 05/23/07 - Added wire declaration for internal signals. + +`timescale 1 ps / 1 ps + + +module IOBUF_LVDCI_DV2_33 (O, IO, I, T); + + output O; + + inout IO; + + input I, T; + + wire ts; + + tri0 GTS = glbl.GTS; + + or O1 (ts, GTS, T); + bufif0 T1 (IO, I, ts); + + buf B1 (O, IO); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IOBUF_LVDS.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IOBUF_LVDS.v new file mode 100644 index 0000000..643a52c --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IOBUF_LVDS.v @@ -0,0 +1,43 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/IOBUF_LVDS.v,v 1.6 2007/05/23 21:43:38 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Bi-Directional Buffer with LVDS I/O Standard +// /___/ /\ Filename : IOBUF_LVDS.v +// \ \ / \ Timestamp : Thu Mar 25 16:42:47 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. +// 05/23/07 - Added wire declaration for internal signals. + +`timescale 1 ps / 1 ps + + +module IOBUF_LVDS (O, IO, I, T); + + output O; + + inout IO; + + input I, T; + + wire ts; + + tri0 GTS = glbl.GTS; + + or O1 (ts, GTS, T); + bufif0 T1 (IO, I, ts); + + buf B1 (O, IO); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IOBUF_LVPECL.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IOBUF_LVPECL.v new file mode 100644 index 0000000..19462fe --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IOBUF_LVPECL.v @@ -0,0 +1,43 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/IOBUF_LVPECL.v,v 1.6 2007/05/23 21:43:38 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Bi-Directional Buffer with LVPECL I/O Standard +// /___/ /\ Filename : IOBUF_LVPECL.v +// \ \ / \ Timestamp : Thu Mar 25 16:42:47 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. +// 05/23/07 - Added wire declaration for internal signals. + +`timescale 1 ps / 1 ps + + +module IOBUF_LVPECL (O, IO, I, T); + + output O; + + inout IO; + + input I, T; + + wire ts; + + tri0 GTS = glbl.GTS; + + or O1 (ts, GTS, T); + bufif0 T1 (IO, I, ts); + + buf B1 (O, IO); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IOBUF_LVTTL.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IOBUF_LVTTL.v new file mode 100644 index 0000000..a6bca1e --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IOBUF_LVTTL.v @@ -0,0 +1,43 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/IOBUF_LVTTL.v,v 1.6 2007/05/23 21:43:38 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Bi-Directional Buffer with LVTTL I/O Standard +// /___/ /\ Filename : IOBUF_LVTTL.v +// \ \ / \ Timestamp : Thu Mar 25 16:42:47 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. +// 05/23/07 - Added wire declaration for internal signals. + +`timescale 1 ps / 1 ps + + +module IOBUF_LVTTL (O, IO, I, T); + + output O; + + inout IO; + + input I, T; + + wire ts; + + tri0 GTS = glbl.GTS; + + or O1 (ts, GTS, T); + bufif0 T1 (IO, I, ts); + + buf B1 (O, IO); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IOBUF_LVTTL_F_12.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IOBUF_LVTTL_F_12.v new file mode 100644 index 0000000..94a50a5 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IOBUF_LVTTL_F_12.v @@ -0,0 +1,43 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/IOBUF_LVTTL_F_12.v,v 1.6 2007/05/23 21:43:38 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Bi-Directional Buffer with LVTTL I/O Standard Fast Slew 12 mA Drive +// /___/ /\ Filename : IOBUF_LVTTL_F_12.v +// \ \ / \ Timestamp : Thu Mar 25 16:42:48 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. +// 05/23/07 - Added wire declaration for internal signals. + +`timescale 1 ps / 1 ps + + +module IOBUF_LVTTL_F_12 (O, IO, I, T); + + output O; + + inout IO; + + input I, T; + + wire ts; + + tri0 GTS = glbl.GTS; + + or O1 (ts, GTS, T); + bufif0 T1 (IO, I, ts); + + buf B1 (O, IO); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IOBUF_LVTTL_F_16.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IOBUF_LVTTL_F_16.v new file mode 100644 index 0000000..26f5a32 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IOBUF_LVTTL_F_16.v @@ -0,0 +1,43 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/IOBUF_LVTTL_F_16.v,v 1.6 2007/05/23 21:43:38 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Bi-Directional Buffer with LVTTL I/O Standard Fast Slew 16 mA Drive +// /___/ /\ Filename : IOBUF_LVTTL_F_16.v +// \ \ / \ Timestamp : Thu Mar 25 16:42:48 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. +// 05/23/07 - Added wire declaration for internal signals. + +`timescale 1 ps / 1 ps + + +module IOBUF_LVTTL_F_16 (O, IO, I, T); + + output O; + + inout IO; + + input I, T; + + wire ts; + + tri0 GTS = glbl.GTS; + + or O1 (ts, GTS, T); + bufif0 T1 (IO, I, ts); + + buf B1 (O, IO); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IOBUF_LVTTL_F_2.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IOBUF_LVTTL_F_2.v new file mode 100644 index 0000000..b6d7d16 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IOBUF_LVTTL_F_2.v @@ -0,0 +1,43 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/IOBUF_LVTTL_F_2.v,v 1.6 2007/05/23 21:43:38 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Bi-Directional Buffer with LVTTL I/O Standard Fast Slew 2 mA Drive +// /___/ /\ Filename : IOBUF_LVTTL_F_2.v +// \ \ / \ Timestamp : Thu Mar 25 16:42:48 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. +// 05/23/07 - Added wire declaration for internal signals. + +`timescale 1 ps / 1 ps + + +module IOBUF_LVTTL_F_2 (O, IO, I, T); + + output O; + + inout IO; + + input I, T; + + wire ts; + + tri0 GTS = glbl.GTS; + + or O1 (ts, GTS, T); + bufif0 T1 (IO, I, ts); + + buf B1 (O, IO); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IOBUF_LVTTL_F_24.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IOBUF_LVTTL_F_24.v new file mode 100644 index 0000000..171df09 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IOBUF_LVTTL_F_24.v @@ -0,0 +1,43 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/IOBUF_LVTTL_F_24.v,v 1.6 2007/05/23 21:43:38 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Bi-Directional Buffer with LVTTL I/O Standard Fast Slew 24 mA Drive +// /___/ /\ Filename : IOBUF_LVTTL_F_24.v +// \ \ / \ Timestamp : Thu Mar 25 16:42:48 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. +// 05/23/07 - Added wire declaration for internal signals. + +`timescale 1 ps / 1 ps + + +module IOBUF_LVTTL_F_24 (O, IO, I, T); + + output O; + + inout IO; + + input I, T; + + wire ts; + + tri0 GTS = glbl.GTS; + + or O1 (ts, GTS, T); + bufif0 T1 (IO, I, ts); + + buf B1 (O, IO); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IOBUF_LVTTL_F_4.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IOBUF_LVTTL_F_4.v new file mode 100644 index 0000000..1a98dc7 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IOBUF_LVTTL_F_4.v @@ -0,0 +1,43 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/IOBUF_LVTTL_F_4.v,v 1.6 2007/05/23 21:43:38 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Bi-Directional Buffer with LVTTL I/O Standard Fast Slew 4 mA Drive +// /___/ /\ Filename : IOBUF_LVTTL_F_4.v +// \ \ / \ Timestamp : Thu Mar 25 16:42:48 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. +// 05/23/07 - Added wire declaration for internal signals. + +`timescale 1 ps / 1 ps + + +module IOBUF_LVTTL_F_4 (O, IO, I, T); + + output O; + + inout IO; + + input I, T; + + wire ts; + + tri0 GTS = glbl.GTS; + + or O1 (ts, GTS, T); + bufif0 T1 (IO, I, ts); + + buf B1 (O, IO); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IOBUF_LVTTL_F_6.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IOBUF_LVTTL_F_6.v new file mode 100644 index 0000000..2a831ab --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IOBUF_LVTTL_F_6.v @@ -0,0 +1,43 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/IOBUF_LVTTL_F_6.v,v 1.6 2007/05/23 21:43:38 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Bi-Directional Buffer with LVTTL I/O Standard Fast Slew 6 mA Drive +// /___/ /\ Filename : IOBUF_LVTTL_F_6.v +// \ \ / \ Timestamp : Thu Mar 25 16:42:48 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. +// 05/23/07 - Added wire declaration for internal signals. + +`timescale 1 ps / 1 ps + + +module IOBUF_LVTTL_F_6 (O, IO, I, T); + + output O; + + inout IO; + + input I, T; + + wire ts; + + tri0 GTS = glbl.GTS; + + or O1 (ts, GTS, T); + bufif0 T1 (IO, I, ts); + + buf B1 (O, IO); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IOBUF_LVTTL_F_8.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IOBUF_LVTTL_F_8.v new file mode 100644 index 0000000..82ca029 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IOBUF_LVTTL_F_8.v @@ -0,0 +1,43 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/IOBUF_LVTTL_F_8.v,v 1.6 2007/05/23 21:43:38 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Bi-Directional Buffer with LVTTL I/O Standard Fast Slew 8 mA Drive +// /___/ /\ Filename : IOBUF_LVTTL_F_8.v +// \ \ / \ Timestamp : Thu Mar 25 16:42:48 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. +// 05/23/07 - Added wire declaration for internal signals. + +`timescale 1 ps / 1 ps + + +module IOBUF_LVTTL_F_8 (O, IO, I, T); + + output O; + + inout IO; + + input I, T; + + wire ts; + + tri0 GTS = glbl.GTS; + + or O1 (ts, GTS, T); + bufif0 T1 (IO, I, ts); + + buf B1 (O, IO); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IOBUF_LVTTL_S_12.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IOBUF_LVTTL_S_12.v new file mode 100644 index 0000000..ede1078 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IOBUF_LVTTL_S_12.v @@ -0,0 +1,43 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/IOBUF_LVTTL_S_12.v,v 1.6 2007/05/23 21:43:38 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Bi-Directional Buffer with LVTTL I/O Standard Slow Slew 12 mA Drive +// /___/ /\ Filename : IOBUF_LVTTL_S_12.v +// \ \ / \ Timestamp : Thu Mar 25 16:42:48 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. +// 05/23/07 - Added wire declaration for internal signals. + +`timescale 1 ps / 1 ps + + +module IOBUF_LVTTL_S_12 (O, IO, I, T); + + output O; + + inout IO; + + input I, T; + + wire ts; + + tri0 GTS = glbl.GTS; + + or O1 (ts, GTS, T); + bufif0 T1 (IO, I, ts); + + buf B1 (O, IO); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IOBUF_LVTTL_S_16.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IOBUF_LVTTL_S_16.v new file mode 100644 index 0000000..9ff9ae2 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IOBUF_LVTTL_S_16.v @@ -0,0 +1,43 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/IOBUF_LVTTL_S_16.v,v 1.6 2007/05/23 21:43:38 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Bi-Directional Buffer with LVTTL I/O Standard Slow Slew 16 mA Drive +// /___/ /\ Filename : IOBUF_LVTTL_S_16.v +// \ \ / \ Timestamp : Thu Mar 25 16:42:48 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. +// 05/23/07 - Added wire declaration for internal signals. + +`timescale 1 ps / 1 ps + + +module IOBUF_LVTTL_S_16 (O, IO, I, T); + + output O; + + inout IO; + + input I, T; + + wire ts; + + tri0 GTS = glbl.GTS; + + or O1 (ts, GTS, T); + bufif0 T1 (IO, I, ts); + + buf B1 (O, IO); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IOBUF_LVTTL_S_2.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IOBUF_LVTTL_S_2.v new file mode 100644 index 0000000..aa42610 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IOBUF_LVTTL_S_2.v @@ -0,0 +1,43 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/IOBUF_LVTTL_S_2.v,v 1.6 2007/05/23 21:43:38 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Bi-Directional Buffer with LVTTL I/O Standard Slow Slew 2 mA Drive +// /___/ /\ Filename : IOBUF_LVTTL_S_2.v +// \ \ / \ Timestamp : Thu Mar 25 16:42:48 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. +// 05/23/07 - Added wire declaration for internal signals. + +`timescale 1 ps / 1 ps + + +module IOBUF_LVTTL_S_2 (O, IO, I, T); + + output O; + + inout IO; + + input I, T; + + wire ts; + + tri0 GTS = glbl.GTS; + + or O1 (ts, GTS, T); + bufif0 T1 (IO, I, ts); + + buf B1 (O, IO); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IOBUF_LVTTL_S_24.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IOBUF_LVTTL_S_24.v new file mode 100644 index 0000000..b396eb9 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IOBUF_LVTTL_S_24.v @@ -0,0 +1,43 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/IOBUF_LVTTL_S_24.v,v 1.6 2007/05/23 21:43:38 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Bi-Directional Buffer with LVTTL I/O Standard Slow Slew 24 mA Drive +// /___/ /\ Filename : IOBUF_LVTTL_S_24.v +// \ \ / \ Timestamp : Thu Mar 25 16:42:49 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. +// 05/23/07 - Added wire declaration for internal signals. + +`timescale 1 ps / 1 ps + + +module IOBUF_LVTTL_S_24 (O, IO, I, T); + + output O; + + inout IO; + + input I, T; + + wire ts; + + tri0 GTS = glbl.GTS; + + or O1 (ts, GTS, T); + bufif0 T1 (IO, I, ts); + + buf B1 (O, IO); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IOBUF_LVTTL_S_4.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IOBUF_LVTTL_S_4.v new file mode 100644 index 0000000..4b2af9b --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IOBUF_LVTTL_S_4.v @@ -0,0 +1,43 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/IOBUF_LVTTL_S_4.v,v 1.6 2007/05/23 21:43:38 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Bi-Directional Buffer with LVTTL I/O Standard Slow Slew 4 mA Drive +// /___/ /\ Filename : IOBUF_LVTTL_S_4.v +// \ \ / \ Timestamp : Thu Mar 25 16:42:49 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. +// 05/23/07 - Added wire declaration for internal signals. + +`timescale 1 ps / 1 ps + + +module IOBUF_LVTTL_S_4 (O, IO, I, T); + + output O; + + inout IO; + + input I, T; + + wire ts; + + tri0 GTS = glbl.GTS; + + or O1 (ts, GTS, T); + bufif0 T1 (IO, I, ts); + + buf B1 (O, IO); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IOBUF_LVTTL_S_6.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IOBUF_LVTTL_S_6.v new file mode 100644 index 0000000..1c31483 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IOBUF_LVTTL_S_6.v @@ -0,0 +1,43 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/IOBUF_LVTTL_S_6.v,v 1.6 2007/05/23 21:43:38 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Bi-Directional Buffer with LVTTL I/O Standard Slow Slew 6 mA Drive +// /___/ /\ Filename : IOBUF_LVTTL_S_6.v +// \ \ / \ Timestamp : Thu Mar 25 16:42:49 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. +// 05/23/07 - Added wire declaration for internal signals. + +`timescale 1 ps / 1 ps + + +module IOBUF_LVTTL_S_6 (O, IO, I, T); + + output O; + + inout IO; + + input I, T; + + wire ts; + + tri0 GTS = glbl.GTS; + + or O1 (ts, GTS, T); + bufif0 T1 (IO, I, ts); + + buf B1 (O, IO); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IOBUF_LVTTL_S_8.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IOBUF_LVTTL_S_8.v new file mode 100644 index 0000000..acd4b0e --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IOBUF_LVTTL_S_8.v @@ -0,0 +1,43 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/IOBUF_LVTTL_S_8.v,v 1.6 2007/05/23 21:43:38 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Bi-Directional Buffer with LVTTL I/O Standard Slow Slew 8 mA Drive +// /___/ /\ Filename : IOBUF_LVTTL_S_8.v +// \ \ / \ Timestamp : Thu Mar 25 16:42:49 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. +// 05/23/07 - Added wire declaration for internal signals. + +`timescale 1 ps / 1 ps + + +module IOBUF_LVTTL_S_8 (O, IO, I, T); + + output O; + + inout IO; + + input I, T; + + wire ts; + + tri0 GTS = glbl.GTS; + + or O1 (ts, GTS, T); + bufif0 T1 (IO, I, ts); + + buf B1 (O, IO); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IOBUF_PCI33_3.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IOBUF_PCI33_3.v new file mode 100644 index 0000000..16066c7 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IOBUF_PCI33_3.v @@ -0,0 +1,43 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/IOBUF_PCI33_3.v,v 1.6 2007/05/23 21:43:38 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Bi-Directional Buffer with PCI33_3 I/O Standard +// /___/ /\ Filename : IOBUF_PCI33_3.v +// \ \ / \ Timestamp : Thu Mar 25 16:42:49 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. +// 05/23/07 - Added wire declaration for internal signals. + +`timescale 1 ps / 1 ps + + +module IOBUF_PCI33_3 (O, IO, I, T); + + output O; + + inout IO; + + input I, T; + + wire ts; + + tri0 GTS = glbl.GTS; + + or O1 (ts, GTS, T); + bufif0 T1 (IO, I, ts); + + buf B1 (O, IO); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IOBUF_PCI33_5.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IOBUF_PCI33_5.v new file mode 100644 index 0000000..edb7a3f --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IOBUF_PCI33_5.v @@ -0,0 +1,43 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/IOBUF_PCI33_5.v,v 1.6 2007/05/23 21:43:38 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Bi-Directional Buffer with PCI33_5 I/O Standard +// /___/ /\ Filename : IOBUF_PCI33_5.v +// \ \ / \ Timestamp : Thu Mar 25 16:42:49 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. +// 05/23/07 - Added wire declaration for internal signals. + +`timescale 1 ps / 1 ps + + +module IOBUF_PCI33_5 (O, IO, I, T); + + output O; + + inout IO; + + input I, T; + + wire ts; + + tri0 GTS = glbl.GTS; + + or O1 (ts, GTS, T); + bufif0 T1 (IO, I, ts); + + buf B1 (O, IO); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IOBUF_PCI66_3.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IOBUF_PCI66_3.v new file mode 100644 index 0000000..f3ccf70 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IOBUF_PCI66_3.v @@ -0,0 +1,43 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/IOBUF_PCI66_3.v,v 1.6 2007/05/23 21:43:38 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Bi-Directional Buffer with PCI66_3 I/O Standard +// /___/ /\ Filename : IOBUF_PCI66_3.v +// \ \ / \ Timestamp : Thu Mar 25 16:42:49 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. +// 05/23/07 - Added wire declaration for internal signals. + +`timescale 1 ps / 1 ps + + +module IOBUF_PCI66_3 (O, IO, I, T); + + output O; + + inout IO; + + input I, T; + + wire ts; + + tri0 GTS = glbl.GTS; + + or O1 (ts, GTS, T); + bufif0 T1 (IO, I, ts); + + buf B1 (O, IO); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IOBUF_PCIX.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IOBUF_PCIX.v new file mode 100644 index 0000000..17f4281 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IOBUF_PCIX.v @@ -0,0 +1,43 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/IOBUF_PCIX.v,v 1.6 2007/05/23 21:43:38 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Bi-Directional Buffer with PCIX I/O Standard +// /___/ /\ Filename : IOBUF_PCIX.v +// \ \ / \ Timestamp : Thu Mar 25 16:42:49 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. +// 05/23/07 - Added wire declaration for internal signals. + +`timescale 1 ps / 1 ps + + +module IOBUF_PCIX (O, IO, I, T); + + output O; + + inout IO; + + input I, T; + + wire ts; + + tri0 GTS = glbl.GTS; + + or O1 (ts, GTS, T); + bufif0 T1 (IO, I, ts); + + buf B1 (O, IO); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IOBUF_PCIX66_3.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IOBUF_PCIX66_3.v new file mode 100644 index 0000000..f7a55f3 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IOBUF_PCIX66_3.v @@ -0,0 +1,43 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/IOBUF_PCIX66_3.v,v 1.6 2007/05/23 21:43:38 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Bi-Directional Buffer with PCIX66_3 I/O Standard +// /___/ /\ Filename : IOBUF_PCIX66_3.v +// \ \ / \ Timestamp : Thu Mar 25 16:42:49 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. +// 05/23/07 - Added wire declaration for internal signals. + +`timescale 1 ps / 1 ps + + +module IOBUF_PCIX66_3 (O, IO, I, T); + + output O; + + inout IO; + + input I, T; + + wire ts; + + tri0 GTS = glbl.GTS; + + or O1 (ts, GTS, T); + bufif0 T1 (IO, I, ts); + + buf B1 (O, IO); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IOBUF_SSTL18_I.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IOBUF_SSTL18_I.v new file mode 100644 index 0000000..9c017d9 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IOBUF_SSTL18_I.v @@ -0,0 +1,43 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/IOBUF_SSTL18_I.v,v 1.6 2007/05/23 21:43:39 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Bi-Directional Buffer with SSTL18_I I/O Standard +// /___/ /\ Filename : IOBUF_SSTL18_I.v +// \ \ / \ Timestamp : Thu Mar 25 16:42:49 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. +// 05/23/07 - Added wire declaration for internal signals. + +`timescale 1 ps / 1 ps + + +module IOBUF_SSTL18_I (O, IO, I, T); + + output O; + + inout IO; + + input I, T; + + wire ts; + + tri0 GTS = glbl.GTS; + + or O1 (ts, GTS, T); + bufif0 T1 (IO, I, ts); + + buf B1 (O, IO); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IOBUF_SSTL18_II.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IOBUF_SSTL18_II.v new file mode 100644 index 0000000..233aa64 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IOBUF_SSTL18_II.v @@ -0,0 +1,43 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/IOBUF_SSTL18_II.v,v 1.6 2007/05/23 21:43:39 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Bi-Directional Buffer with SSTL18_II I/O Standard +// /___/ /\ Filename : IOBUF_SSTL18_II.v +// \ \ / \ Timestamp : Thu Mar 25 16:42:50 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. +// 05/23/07 - Added wire declaration for internal signals. + +`timescale 1 ps / 1 ps + + +module IOBUF_SSTL18_II (O, IO, I, T); + + output O; + + inout IO; + + input I, T; + + wire ts; + + tri0 GTS = glbl.GTS; + + or O1 (ts, GTS, T); + bufif0 T1 (IO, I, ts); + + buf B1 (O, IO); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IOBUF_SSTL18_II_DCI.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IOBUF_SSTL18_II_DCI.v new file mode 100644 index 0000000..563ae84 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IOBUF_SSTL18_II_DCI.v @@ -0,0 +1,43 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/IOBUF_SSTL18_II_DCI.v,v 1.6 2007/05/23 21:43:39 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Bi-Directional Buffer with SSTL18_II_DCI I/O Standard +// /___/ /\ Filename : IOBUF_SSTL18_II_DCI.v +// \ \ / \ Timestamp : Thu Mar 25 16:42:50 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. +// 05/23/07 - Added wire declaration for internal signals. + +`timescale 1 ps / 1 ps + + +module IOBUF_SSTL18_II_DCI (O, IO, I, T); + + output O; + + inout IO; + + input I, T; + + wire ts; + + tri0 GTS = glbl.GTS; + + or O1 (ts, GTS, T); + bufif0 T1 (IO, I, ts); + + buf B1 (O, IO); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IOBUF_SSTL2_I.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IOBUF_SSTL2_I.v new file mode 100644 index 0000000..6dcea8f --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IOBUF_SSTL2_I.v @@ -0,0 +1,43 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/IOBUF_SSTL2_I.v,v 1.6 2007/05/23 21:43:39 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Bi-Directional Buffer with SSTL2_I I/O Standard +// /___/ /\ Filename : IOBUF_SSTL2_I.v +// \ \ / \ Timestamp : Thu Mar 25 16:42:50 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. +// 05/23/07 - Added wire declaration for internal signals. + +`timescale 1 ps / 1 ps + + +module IOBUF_SSTL2_I (O, IO, I, T); + + output O; + + inout IO; + + input I, T; + + wire ts; + + tri0 GTS = glbl.GTS; + + or O1 (ts, GTS, T); + bufif0 T1 (IO, I, ts); + + buf B1 (O, IO); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IOBUF_SSTL2_II.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IOBUF_SSTL2_II.v new file mode 100644 index 0000000..adf6202 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IOBUF_SSTL2_II.v @@ -0,0 +1,43 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/IOBUF_SSTL2_II.v,v 1.6 2007/05/23 21:43:39 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Bi-Directional Buffer with SSTL2_II I/O Standard +// /___/ /\ Filename : IOBUF_SSTL2_II.v +// \ \ / \ Timestamp : Thu Mar 25 16:42:50 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. +// 05/23/07 - Added wire declaration for internal signals. + +`timescale 1 ps / 1 ps + + +module IOBUF_SSTL2_II (O, IO, I, T); + + output O; + + inout IO; + + input I, T; + + wire ts; + + tri0 GTS = glbl.GTS; + + or O1 (ts, GTS, T); + bufif0 T1 (IO, I, ts); + + buf B1 (O, IO); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IOBUF_SSTL2_II_DCI.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IOBUF_SSTL2_II_DCI.v new file mode 100644 index 0000000..1681eb8 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IOBUF_SSTL2_II_DCI.v @@ -0,0 +1,43 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/IOBUF_SSTL2_II_DCI.v,v 1.6 2007/05/23 21:43:39 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Bi-Directional Buffer with SSTL2_II_DCI I/O Standard +// /___/ /\ Filename : IOBUF_SSTL2_II_DCI.v +// \ \ / \ Timestamp : Thu Mar 25 16:42:50 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. +// 05/23/07 - Added wire declaration for internal signals. + +`timescale 1 ps / 1 ps + + +module IOBUF_SSTL2_II_DCI (O, IO, I, T); + + output O; + + inout IO; + + input I, T; + + wire ts; + + tri0 GTS = glbl.GTS; + + or O1 (ts, GTS, T); + bufif0 T1 (IO, I, ts); + + buf B1 (O, IO); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IOBUF_SSTL3_I.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IOBUF_SSTL3_I.v new file mode 100644 index 0000000..98e7b3c --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IOBUF_SSTL3_I.v @@ -0,0 +1,43 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/IOBUF_SSTL3_I.v,v 1.6 2007/05/23 21:43:39 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Bi-Directional Buffer with SSTL3_I I/O Standard +// /___/ /\ Filename : IOBUF_SSTL3_I.v +// \ \ / \ Timestamp : Thu Mar 25 16:42:50 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. +// 05/23/07 - Added wire declaration for internal signals. + +`timescale 1 ps / 1 ps + + +module IOBUF_SSTL3_I (O, IO, I, T); + + output O; + + inout IO; + + input I, T; + + wire ts; + + tri0 GTS = glbl.GTS; + + or O1 (ts, GTS, T); + bufif0 T1 (IO, I, ts); + + buf B1 (O, IO); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IOBUF_SSTL3_II.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IOBUF_SSTL3_II.v new file mode 100644 index 0000000..b7f63a4 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IOBUF_SSTL3_II.v @@ -0,0 +1,43 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/IOBUF_SSTL3_II.v,v 1.6 2007/05/23 21:43:39 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Bi-Directional Buffer with SSTL3_II I/O Standard +// /___/ /\ Filename : IOBUF_SSTL3_II.v +// \ \ / \ Timestamp : Thu Mar 25 16:42:50 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. +// 05/23/07 - Added wire declaration for internal signals. + +`timescale 1 ps / 1 ps + + +module IOBUF_SSTL3_II (O, IO, I, T); + + output O; + + inout IO; + + input I, T; + + wire ts; + + tri0 GTS = glbl.GTS; + + or O1 (ts, GTS, T); + bufif0 T1 (IO, I, ts); + + buf B1 (O, IO); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IOBUF_SSTL3_II_DCI.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IOBUF_SSTL3_II_DCI.v new file mode 100644 index 0000000..36eff9a --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IOBUF_SSTL3_II_DCI.v @@ -0,0 +1,43 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/IOBUF_SSTL3_II_DCI.v,v 1.6 2007/05/23 21:43:39 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Bi-Directional Buffer with SSTL3_II_DCI I/O Standard +// /___/ /\ Filename : IOBUF_SSTL3_II_DCI.v +// \ \ / \ Timestamp : Thu Mar 25 16:42:50 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. +// 05/23/07 - Added wire declaration for internal signals. + +`timescale 1 ps / 1 ps + + +module IOBUF_SSTL3_II_DCI (O, IO, I, T); + + output O; + + inout IO; + + input I, T; + + wire ts; + + tri0 GTS = glbl.GTS; + + or O1 (ts, GTS, T); + bufif0 T1 (IO, I, ts); + + buf B1 (O, IO); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IOBUF_S_12.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IOBUF_S_12.v new file mode 100644 index 0000000..bc9c40b --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IOBUF_S_12.v @@ -0,0 +1,43 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/IOBUF_S_12.v,v 1.6 2007/05/23 21:43:38 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Bi-Directional Buffer with Slow Slew 12 mA Drive +// /___/ /\ Filename : IOBUF_S_12.v +// \ \ / \ Timestamp : Thu Mar 25 16:42:51 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. +// 05/23/07 - Added wire declaration for internal signals. + +`timescale 1 ps / 1 ps + + +module IOBUF_S_12 (O, IO, I, T); + + output O; + + inout IO; + + input I, T; + + wire ts; + + tri0 GTS = glbl.GTS; + + or O1 (ts, GTS, T); + bufif0 T1 (IO, I, ts); + + buf B1 (O, IO); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IOBUF_S_16.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IOBUF_S_16.v new file mode 100644 index 0000000..7a55283 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IOBUF_S_16.v @@ -0,0 +1,43 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/IOBUF_S_16.v,v 1.6 2007/05/23 21:43:38 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Bi-Directional Buffer with Slow Slew 16 mA Drive +// /___/ /\ Filename : IOBUF_S_16.v +// \ \ / \ Timestamp : Thu Mar 25 16:42:51 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. +// 05/23/07 - Added wire declaration for internal signals. + +`timescale 1 ps / 1 ps + + +module IOBUF_S_16 (O, IO, I, T); + + output O; + + inout IO; + + input I, T; + + wire ts; + + tri0 GTS = glbl.GTS; + + or O1 (ts, GTS, T); + bufif0 T1 (IO, I, ts); + + buf B1 (O, IO); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IOBUF_S_2.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IOBUF_S_2.v new file mode 100644 index 0000000..c2107e9 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IOBUF_S_2.v @@ -0,0 +1,43 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/IOBUF_S_2.v,v 1.6 2007/05/23 21:43:38 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Bi-Directional Buffer with Slow Slew 2 mA Drive +// /___/ /\ Filename : IOBUF_S_2.v +// \ \ / \ Timestamp : Thu Mar 25 16:42:51 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. +// 05/23/07 - Added wire declaration for internal signals. + +`timescale 1 ps / 1 ps + + +module IOBUF_S_2 (O, IO, I, T); + + output O; + + inout IO; + + input I, T; + + wire ts; + + tri0 GTS = glbl.GTS; + + or O1 (ts, GTS, T); + bufif0 T1 (IO, I, ts); + + buf B1 (O, IO); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IOBUF_S_24.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IOBUF_S_24.v new file mode 100644 index 0000000..470e56f --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IOBUF_S_24.v @@ -0,0 +1,43 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/IOBUF_S_24.v,v 1.6 2007/05/23 21:43:38 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Bi-Directional Buffer with Slow Slew 24 mA Drive +// /___/ /\ Filename : IOBUF_S_24.v +// \ \ / \ Timestamp : Thu Mar 25 16:42:51 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. +// 05/23/07 - Added wire declaration for internal signals. + +`timescale 1 ps / 1 ps + + +module IOBUF_S_24 (O, IO, I, T); + + output O; + + inout IO; + + input I, T; + + wire ts; + + tri0 GTS = glbl.GTS; + + or O1 (ts, GTS, T); + bufif0 T1 (IO, I, ts); + + buf B1 (O, IO); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IOBUF_S_4.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IOBUF_S_4.v new file mode 100644 index 0000000..4b21de2 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IOBUF_S_4.v @@ -0,0 +1,43 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/IOBUF_S_4.v,v 1.6 2007/05/23 21:43:39 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Bi-Directional Buffer with Slow Slew 4 mA Drive +// /___/ /\ Filename : IOBUF_S_4.v +// \ \ / \ Timestamp : Thu Mar 25 16:42:51 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. +// 05/23/07 - Added wire declaration for internal signals. + +`timescale 1 ps / 1 ps + + +module IOBUF_S_4 (O, IO, I, T); + + output O; + + inout IO; + + input I, T; + + wire ts; + + tri0 GTS = glbl.GTS; + + or O1 (ts, GTS, T); + bufif0 T1 (IO, I, ts); + + buf B1 (O, IO); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IOBUF_S_6.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IOBUF_S_6.v new file mode 100644 index 0000000..0d8bebb --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IOBUF_S_6.v @@ -0,0 +1,43 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/IOBUF_S_6.v,v 1.6 2007/05/23 21:43:39 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Bi-Directional Buffer with Slow Slew 6 mA Drive +// /___/ /\ Filename : IOBUF_S_6.v +// \ \ / \ Timestamp : Thu Mar 25 16:42:51 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. +// 05/23/07 - Added wire declaration for internal signals. + +`timescale 1 ps / 1 ps + + +module IOBUF_S_6 (O, IO, I, T); + + output O; + + inout IO; + + input I, T; + + wire ts; + + tri0 GTS = glbl.GTS; + + or O1 (ts, GTS, T); + bufif0 T1 (IO, I, ts); + + buf B1 (O, IO); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IOBUF_S_8.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IOBUF_S_8.v new file mode 100644 index 0000000..7b51411 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IOBUF_S_8.v @@ -0,0 +1,43 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/IOBUF_S_8.v,v 1.6 2007/05/23 21:43:39 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Bi-Directional Buffer with Slow Slew 8 mA Drive +// /___/ /\ Filename : IOBUF_S_8.v +// \ \ / \ Timestamp : Thu Mar 25 16:42:51 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. +// 05/23/07 - Added wire declaration for internal signals. + +`timescale 1 ps / 1 ps + + +module IOBUF_S_8 (O, IO, I, T); + + output O; + + inout IO; + + input I, T; + + wire ts; + + tri0 GTS = glbl.GTS; + + or O1 (ts, GTS, T); + bufif0 T1 (IO, I, ts); + + buf B1 (O, IO); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IODELAY.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IODELAY.v new file mode 100644 index 0000000..9d19e30 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IODELAY.v @@ -0,0 +1,631 @@ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Input and/or Output Fixed or Variable Delay Element. +// /___/ /\ Filename : IODELAY.v +// \ \ / \ Timestamp : Thu Jul 28 15:58:12 PDT 2005 +// \___\/\___\ +// +// Revision: +// 07/28/05 - Initial version. +// 01/11/06 - Changed Equation for CALC_TAPDELAY --FP +// 02/28/06 - CR 226003 -- Added Parameter Types (integer/real) --FP +// 03/10/06 - CR 227041 -- Added path delays --FP +// 06/04/06 - Made the model independent of T pin (except in DELAY_SRC=IO mode) --FP +// 07/21/06 - CR 234556 fix. Added SIM_DELAY_D to Simprims --FP +// 01/03/07 - For simprims, the fixed Delay value is taken from the sdf. +// 03/26/07 - CR 436199 , changed default value of HIGH_PERFORMANCE_MODE -- FP +// 03/26/07 - CR 436765 -- FP +// 05/03/07 - CR 438921 SIGNAL_PATTERN -- FP +// 07/07/07 - Added wire declarations +// 08/29/07 - CR 445561 -- Replaced D_IOBDELAY_OFFSET with D_IODELAY_OFFSET +// End Revision + +`timescale 1 ps / 1 ps + +module IODELAY (DATAOUT, C, CE, DATAIN, IDATAIN, INC, ODATAIN, RST, T); + + parameter DELAY_SRC = "I"; + parameter HIGH_PERFORMANCE_MODE = "TRUE"; + parameter IDELAY_TYPE = "DEFAULT"; + parameter integer IDELAY_VALUE = 0; + parameter integer ODELAY_VALUE = 0; + parameter real REFCLK_FREQUENCY = 200.0; + parameter SIGNAL_PATTERN = "DATA"; + + output DATAOUT; + + input C; + input CE; + input DATAIN; + input IDATAIN; + input INC; + input ODATAIN; + input RST; + input T ; + + + localparam ILEAK_ADJUST = 1.0; + localparam D_IODELAY_OFFSET = 0.0; + + tri0 GSR = glbl.GSR; + +//------------------- constants ------------------------------------ + + localparam MAX_IDELAY_COUNT = 63; + localparam MIN_IDELAY_COUNT = 0; + localparam MAX_ODELAY_COUNT = 63; + localparam MIN_ODELAY_COUNT = 0; + + localparam MAX_REFCLK_FREQUENCY = 225.0; + localparam MIN_REFCLK_FREQUENCY = 175.0; + +//------------------- variable declaration ------------------------- + + integer idelay_count, odelay_count; + + + + reg data_mux = 0; + reg tap_out = 0; + + wire delay_chain_0, delay_chain_1, delay_chain_2, delay_chain_3, + delay_chain_4, delay_chain_5, delay_chain_6, delay_chain_7, + delay_chain_8, delay_chain_9, delay_chain_10, delay_chain_11, + delay_chain_12, delay_chain_13, delay_chain_14, delay_chain_15, + delay_chain_16, delay_chain_17, delay_chain_18, delay_chain_19, + delay_chain_20, delay_chain_21, delay_chain_22, delay_chain_23, + delay_chain_24, delay_chain_25, delay_chain_26, delay_chain_27, + delay_chain_28, delay_chain_29, delay_chain_30, delay_chain_31, + delay_chain_32, delay_chain_33, delay_chain_34, delay_chain_35, + delay_chain_36, delay_chain_37, delay_chain_38, delay_chain_39, + delay_chain_40, delay_chain_41, delay_chain_42, delay_chain_43, + delay_chain_44, delay_chain_45, delay_chain_46, delay_chain_47, + delay_chain_48, delay_chain_49, delay_chain_50, delay_chain_51, + delay_chain_52, delay_chain_53, delay_chain_54, delay_chain_55, + delay_chain_56, delay_chain_57, delay_chain_58, delay_chain_59, + delay_chain_60, delay_chain_61, delay_chain_62, delay_chain_63; + + wire c_in; + wire ce_in; + wire datain_in; + wire gsr_in; + wire idatain_in; + wire inc_in; + wire odatain_in; + wire rst_in; + wire t_in; + + real CALC_TAPDELAY = 0.0; +//---------------------------------------------------------------------- +//------------------------ Output buffering ------------------------------ +//---------------------------------------------------------------------- + buf buf_odataout (DATAOUT, tap_out); + +//----------------------------------------------------- +//----------- Input buffering -------------------------------- +//----------------------------------------------------- + + buf buf_c (c_in, C); + buf buf_ce (ce_in, CE); + buf buf_ (datain_in, DATAIN); + buf buf_gsr (gsr_in, GSR); + buf buf_i (idatain_in, IDATAIN); + buf buf_inc (inc_in, INC); + buf buf_o (odatain_in, ODATAIN); + buf buf_rst (rst_in, RST); + buf buf_t (t_in, T); + + +//*** GLOBAL hidden GSR pin + always @(gsr_in) begin + if (gsr_in == 1'b1) begin + + assign odelay_count = ODELAY_VALUE; + + if (IDELAY_TYPE == "DEFAULT") + assign idelay_count = 0; + else + assign idelay_count = IDELAY_VALUE; + end + else if (gsr_in == 1'b0) begin + deassign idelay_count; + deassign odelay_count; + end + end + + + initial begin + + //-------- SIGNAL_PATTERN check + + case (SIGNAL_PATTERN) + "CLOCK", "DATA" : ; + default : begin + $display("Attribute Syntax Error : The attribute SIGNAL_PATTERN on IODELAY instance %m is set to %s. Legal values for this attribute are DATA or CLOCK.", SIGNAL_PATTERN); + $finish; + end + endcase + + //-------- HIGH_PERFORMANCE_MODE check + + case (HIGH_PERFORMANCE_MODE) + "TRUE", "FALSE" : ; + default : begin + $display("Attribute Syntax Error : The attribute HIGH_PERFORMANCE_MODE on IODELAY instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", HIGH_PERFORMANCE_MODE); + $finish; + end + endcase + + + //-------- IDELAY_TYPE check + + if (IDELAY_TYPE != "DEFAULT" && IDELAY_TYPE != "FIXED" && IDELAY_TYPE != "VARIABLE") begin + + $display("Attribute Syntax Error : The attribute IDELAY_TYPE on IODELAY instance %m is set to %s. Legal values for this attribute are DEFAULT, FIXED or VARIABLE", IDELAY_TYPE); + $finish; + + end + + + //-------- IDELAY_VALUE check + + if (IDELAY_VALUE < MIN_IDELAY_COUNT || IDELAY_VALUE > MAX_IDELAY_COUNT) begin + $display("Attribute Syntax Error : The attribute IDELAY_VALUE on IODELAY instance %m is set to %d. Legal values for this attribute are 0, 1, 2, 3, .... or 63", IDELAY_VALUE); + $finish; + + end + + + //-------- ODELAY_VALUE check + + if (ODELAY_VALUE < MIN_ODELAY_COUNT || ODELAY_VALUE > MAX_ODELAY_COUNT) begin + $display("Attribute Syntax Error : The attribute ODELAY_VALUE on IODELAY instance %m is set to %d. Legal values for this attribute are 0, 1, 2, 3, .... or 63", ODELAY_VALUE); + $finish; + + end + + //-------- REFCLK_FREQUENCY check + + if (REFCLK_FREQUENCY < MIN_REFCLK_FREQUENCY || REFCLK_FREQUENCY > MAX_REFCLK_FREQUENCY) begin + $display("Attribute Syntax Error : The attribute REFCLK_FREQUENCY on IODELAY instance %m is set to %f. Legal values for this attribute are 175.0 to 225.0", REFCLK_FREQUENCY); + $finish; + + end + + //-------- CALC_TAPDELAY check + + CALC_TAPDELAY = ((1.0/REFCLK_FREQUENCY) * (1.0/64) * ILEAK_ADJUST * 1000000) + D_IODELAY_OFFSET ; + + end // initial begin + +//********************************************************* +//*** IDELAY_COUNT +//********************************************************* + + always @(posedge c_in) begin + + if (IDELAY_TYPE == "VARIABLE") begin + if (rst_in == 1'b1) + idelay_count = IDELAY_VALUE; + else if (rst_in == 1'b0 && ce_in == 1'b1) begin + if (inc_in == 1'b1) begin + if (idelay_count < MAX_IDELAY_COUNT) + idelay_count = idelay_count + 1; + else if (idelay_count == MAX_IDELAY_COUNT) + idelay_count = MIN_IDELAY_COUNT; + end + else if (inc_in == 1'b0) begin + if (idelay_count > MIN_IDELAY_COUNT) + idelay_count = idelay_count - 1; + else if (idelay_count == MIN_IDELAY_COUNT) + idelay_count = MAX_IDELAY_COUNT; + end + end + end // if (IDELAY_TYPE == "VARIABLE") + + end // always @ (posedge c_in) + +//********************************************************* +//*** ODELAY_COUNT +//********************************************************* +// is FIXED + +//********************************************************* +//*** SELECT IDATA signal +//********************************************************* + + always @(datain_in or idatain_in, odatain_in, t_in ) begin + + case (DELAY_SRC) + + "I" : begin + data_mux <= idatain_in; + end + "O" : begin + data_mux <= odatain_in; + end + "IO" : begin + data_mux <= ((idatain_in) & t_in ) | ((odatain_in) & ~t_in); + end + "DATAIN" : begin + data_mux <= datain_in; + end + default : begin + $display("Attribute Syntax Error : The attribute DELAY_SRC on IODELAY instance %m is set to %s. Legal values for this attribute are I, O, IO or DATAIN", DELAY_SRC); + $finish; + end + + endcase // case(DELAY_SRC) + + end // always @ (data_in or idatain_in or odatain_in or t_in) + + +//********************************************************* +//*** DELAY IDATA signal +//********************************************************* + assign delay_chain_0 = data_mux; + assign #CALC_TAPDELAY delay_chain_1 = delay_chain_0; + assign #CALC_TAPDELAY delay_chain_2 = delay_chain_1; + assign #CALC_TAPDELAY delay_chain_3 = delay_chain_2; + assign #CALC_TAPDELAY delay_chain_4 = delay_chain_3; + assign #CALC_TAPDELAY delay_chain_5 = delay_chain_4; + assign #CALC_TAPDELAY delay_chain_6 = delay_chain_5; + assign #CALC_TAPDELAY delay_chain_7 = delay_chain_6; + assign #CALC_TAPDELAY delay_chain_8 = delay_chain_7; + assign #CALC_TAPDELAY delay_chain_9 = delay_chain_8; + assign #CALC_TAPDELAY delay_chain_10 = delay_chain_9; + assign #CALC_TAPDELAY delay_chain_11 = delay_chain_10; + assign #CALC_TAPDELAY delay_chain_12 = delay_chain_11; + assign #CALC_TAPDELAY delay_chain_13 = delay_chain_12; + assign #CALC_TAPDELAY delay_chain_14 = delay_chain_13; + assign #CALC_TAPDELAY delay_chain_15 = delay_chain_14; + assign #CALC_TAPDELAY delay_chain_16 = delay_chain_15; + assign #CALC_TAPDELAY delay_chain_17 = delay_chain_16; + assign #CALC_TAPDELAY delay_chain_18 = delay_chain_17; + assign #CALC_TAPDELAY delay_chain_19 = delay_chain_18; + assign #CALC_TAPDELAY delay_chain_20 = delay_chain_19; + assign #CALC_TAPDELAY delay_chain_21 = delay_chain_20; + assign #CALC_TAPDELAY delay_chain_22 = delay_chain_21; + assign #CALC_TAPDELAY delay_chain_23 = delay_chain_22; + assign #CALC_TAPDELAY delay_chain_24 = delay_chain_23; + assign #CALC_TAPDELAY delay_chain_25 = delay_chain_24; + assign #CALC_TAPDELAY delay_chain_26 = delay_chain_25; + assign #CALC_TAPDELAY delay_chain_27 = delay_chain_26; + assign #CALC_TAPDELAY delay_chain_28 = delay_chain_27; + assign #CALC_TAPDELAY delay_chain_29 = delay_chain_28; + assign #CALC_TAPDELAY delay_chain_30 = delay_chain_29; + assign #CALC_TAPDELAY delay_chain_31 = delay_chain_30; + assign #CALC_TAPDELAY delay_chain_32 = delay_chain_31; + assign #CALC_TAPDELAY delay_chain_33 = delay_chain_32; + assign #CALC_TAPDELAY delay_chain_34 = delay_chain_33; + assign #CALC_TAPDELAY delay_chain_35 = delay_chain_34; + assign #CALC_TAPDELAY delay_chain_36 = delay_chain_35; + assign #CALC_TAPDELAY delay_chain_37 = delay_chain_36; + assign #CALC_TAPDELAY delay_chain_38 = delay_chain_37; + assign #CALC_TAPDELAY delay_chain_39 = delay_chain_38; + assign #CALC_TAPDELAY delay_chain_40 = delay_chain_39; + assign #CALC_TAPDELAY delay_chain_41 = delay_chain_40; + assign #CALC_TAPDELAY delay_chain_42 = delay_chain_41; + assign #CALC_TAPDELAY delay_chain_43 = delay_chain_42; + assign #CALC_TAPDELAY delay_chain_44 = delay_chain_43; + assign #CALC_TAPDELAY delay_chain_45 = delay_chain_44; + assign #CALC_TAPDELAY delay_chain_46 = delay_chain_45; + assign #CALC_TAPDELAY delay_chain_47 = delay_chain_46; + assign #CALC_TAPDELAY delay_chain_48 = delay_chain_47; + assign #CALC_TAPDELAY delay_chain_49 = delay_chain_48; + assign #CALC_TAPDELAY delay_chain_50 = delay_chain_49; + assign #CALC_TAPDELAY delay_chain_51 = delay_chain_50; + assign #CALC_TAPDELAY delay_chain_52 = delay_chain_51; + assign #CALC_TAPDELAY delay_chain_53 = delay_chain_52; + assign #CALC_TAPDELAY delay_chain_54 = delay_chain_53; + assign #CALC_TAPDELAY delay_chain_55 = delay_chain_54; + assign #CALC_TAPDELAY delay_chain_56 = delay_chain_55; + assign #CALC_TAPDELAY delay_chain_57 = delay_chain_56; + assign #CALC_TAPDELAY delay_chain_58 = delay_chain_57; + assign #CALC_TAPDELAY delay_chain_59 = delay_chain_58; + assign #CALC_TAPDELAY delay_chain_60 = delay_chain_59; + assign #CALC_TAPDELAY delay_chain_61 = delay_chain_60; + assign #CALC_TAPDELAY delay_chain_62 = delay_chain_61; + assign #CALC_TAPDELAY delay_chain_63 = delay_chain_62; + +//********************************************************* +//*** assign delay +//********************************************************* + always @(idelay_count, odelay_count, t_in) begin + if(DELAY_SRC == "IO") begin + if (t_in == 1'b1) + case (idelay_count) + 0: assign tap_out = delay_chain_0; + 1: assign tap_out = delay_chain_1; + 2: assign tap_out = delay_chain_2; + 3: assign tap_out = delay_chain_3; + 4: assign tap_out = delay_chain_4; + 5: assign tap_out = delay_chain_5; + 6: assign tap_out = delay_chain_6; + 7: assign tap_out = delay_chain_7; + 8: assign tap_out = delay_chain_8; + 9: assign tap_out = delay_chain_9; + 10: assign tap_out = delay_chain_10; + 11: assign tap_out = delay_chain_11; + 12: assign tap_out = delay_chain_12; + 13: assign tap_out = delay_chain_13; + 14: assign tap_out = delay_chain_14; + 15: assign tap_out = delay_chain_15; + 16: assign tap_out = delay_chain_16; + 17: assign tap_out = delay_chain_17; + 18: assign tap_out = delay_chain_18; + 19: assign tap_out = delay_chain_19; + 20: assign tap_out = delay_chain_20; + 21: assign tap_out = delay_chain_21; + 22: assign tap_out = delay_chain_22; + 23: assign tap_out = delay_chain_23; + 24: assign tap_out = delay_chain_24; + 25: assign tap_out = delay_chain_25; + 26: assign tap_out = delay_chain_26; + 27: assign tap_out = delay_chain_27; + 28: assign tap_out = delay_chain_28; + 29: assign tap_out = delay_chain_29; + 30: assign tap_out = delay_chain_30; + 31: assign tap_out = delay_chain_31; + 32: assign tap_out = delay_chain_32; + 33: assign tap_out = delay_chain_33; + 34: assign tap_out = delay_chain_34; + 35: assign tap_out = delay_chain_35; + 36: assign tap_out = delay_chain_36; + 37: assign tap_out = delay_chain_37; + 38: assign tap_out = delay_chain_38; + 39: assign tap_out = delay_chain_39; + 40: assign tap_out = delay_chain_40; + 41: assign tap_out = delay_chain_41; + 42: assign tap_out = delay_chain_42; + 43: assign tap_out = delay_chain_43; + 44: assign tap_out = delay_chain_44; + 45: assign tap_out = delay_chain_45; + 46: assign tap_out = delay_chain_46; + 47: assign tap_out = delay_chain_47; + 48: assign tap_out = delay_chain_48; + 49: assign tap_out = delay_chain_49; + 50: assign tap_out = delay_chain_50; + 51: assign tap_out = delay_chain_51; + 52: assign tap_out = delay_chain_52; + 53: assign tap_out = delay_chain_53; + 54: assign tap_out = delay_chain_54; + 55: assign tap_out = delay_chain_55; + 56: assign tap_out = delay_chain_56; + 57: assign tap_out = delay_chain_57; + 58: assign tap_out = delay_chain_58; + 59: assign tap_out = delay_chain_59; + 60: assign tap_out = delay_chain_60; + 61: assign tap_out = delay_chain_61; + 62: assign tap_out = delay_chain_62; + 63: assign tap_out = delay_chain_63; + default: + assign tap_out = delay_chain_0; + endcase + else if (t_in == 1'b0) + case (odelay_count) + 0: assign tap_out = delay_chain_0; + 1: assign tap_out = delay_chain_1; + 2: assign tap_out = delay_chain_2; + 3: assign tap_out = delay_chain_3; + 4: assign tap_out = delay_chain_4; + 5: assign tap_out = delay_chain_5; + 6: assign tap_out = delay_chain_6; + 7: assign tap_out = delay_chain_7; + 8: assign tap_out = delay_chain_8; + 9: assign tap_out = delay_chain_9; + 10: assign tap_out = delay_chain_10; + 11: assign tap_out = delay_chain_11; + 12: assign tap_out = delay_chain_12; + 13: assign tap_out = delay_chain_13; + 14: assign tap_out = delay_chain_14; + 15: assign tap_out = delay_chain_15; + 16: assign tap_out = delay_chain_16; + 17: assign tap_out = delay_chain_17; + 18: assign tap_out = delay_chain_18; + 19: assign tap_out = delay_chain_19; + 20: assign tap_out = delay_chain_20; + 21: assign tap_out = delay_chain_21; + 22: assign tap_out = delay_chain_22; + 23: assign tap_out = delay_chain_23; + 24: assign tap_out = delay_chain_24; + 25: assign tap_out = delay_chain_25; + 26: assign tap_out = delay_chain_26; + 27: assign tap_out = delay_chain_27; + 28: assign tap_out = delay_chain_28; + 29: assign tap_out = delay_chain_29; + 30: assign tap_out = delay_chain_30; + 31: assign tap_out = delay_chain_31; + 32: assign tap_out = delay_chain_32; + 33: assign tap_out = delay_chain_33; + 34: assign tap_out = delay_chain_34; + 35: assign tap_out = delay_chain_35; + 36: assign tap_out = delay_chain_36; + 37: assign tap_out = delay_chain_37; + 38: assign tap_out = delay_chain_38; + 39: assign tap_out = delay_chain_39; + 40: assign tap_out = delay_chain_40; + 41: assign tap_out = delay_chain_41; + 42: assign tap_out = delay_chain_42; + 43: assign tap_out = delay_chain_43; + 44: assign tap_out = delay_chain_44; + 45: assign tap_out = delay_chain_45; + 46: assign tap_out = delay_chain_46; + 47: assign tap_out = delay_chain_47; + 48: assign tap_out = delay_chain_48; + 49: assign tap_out = delay_chain_49; + 50: assign tap_out = delay_chain_50; + 51: assign tap_out = delay_chain_51; + 52: assign tap_out = delay_chain_52; + 53: assign tap_out = delay_chain_53; + 54: assign tap_out = delay_chain_54; + 55: assign tap_out = delay_chain_55; + 56: assign tap_out = delay_chain_56; + 57: assign tap_out = delay_chain_57; + 58: assign tap_out = delay_chain_58; + 59: assign tap_out = delay_chain_59; + 60: assign tap_out = delay_chain_60; + 61: assign tap_out = delay_chain_61; + 62: assign tap_out = delay_chain_62; + 63: assign tap_out = delay_chain_63; + default: + assign tap_out = delay_chain_0; + endcase + end // DELAY_SRC == "IO" + else if(DELAY_SRC == "O") begin + case (odelay_count) + 0: assign tap_out = delay_chain_0; + 1: assign tap_out = delay_chain_1; + 2: assign tap_out = delay_chain_2; + 3: assign tap_out = delay_chain_3; + 4: assign tap_out = delay_chain_4; + 5: assign tap_out = delay_chain_5; + 6: assign tap_out = delay_chain_6; + 7: assign tap_out = delay_chain_7; + 8: assign tap_out = delay_chain_8; + 9: assign tap_out = delay_chain_9; + 10: assign tap_out = delay_chain_10; + 11: assign tap_out = delay_chain_11; + 12: assign tap_out = delay_chain_12; + 13: assign tap_out = delay_chain_13; + 14: assign tap_out = delay_chain_14; + 15: assign tap_out = delay_chain_15; + 16: assign tap_out = delay_chain_16; + 17: assign tap_out = delay_chain_17; + 18: assign tap_out = delay_chain_18; + 19: assign tap_out = delay_chain_19; + 20: assign tap_out = delay_chain_20; + 21: assign tap_out = delay_chain_21; + 22: assign tap_out = delay_chain_22; + 23: assign tap_out = delay_chain_23; + 24: assign tap_out = delay_chain_24; + 25: assign tap_out = delay_chain_25; + 26: assign tap_out = delay_chain_26; + 27: assign tap_out = delay_chain_27; + 28: assign tap_out = delay_chain_28; + 29: assign tap_out = delay_chain_29; + 30: assign tap_out = delay_chain_30; + 31: assign tap_out = delay_chain_31; + 32: assign tap_out = delay_chain_32; + 33: assign tap_out = delay_chain_33; + 34: assign tap_out = delay_chain_34; + 35: assign tap_out = delay_chain_35; + 36: assign tap_out = delay_chain_36; + 37: assign tap_out = delay_chain_37; + 38: assign tap_out = delay_chain_38; + 39: assign tap_out = delay_chain_39; + 40: assign tap_out = delay_chain_40; + 41: assign tap_out = delay_chain_41; + 42: assign tap_out = delay_chain_42; + 43: assign tap_out = delay_chain_43; + 44: assign tap_out = delay_chain_44; + 45: assign tap_out = delay_chain_45; + 46: assign tap_out = delay_chain_46; + 47: assign tap_out = delay_chain_47; + 48: assign tap_out = delay_chain_48; + 49: assign tap_out = delay_chain_49; + 50: assign tap_out = delay_chain_50; + 51: assign tap_out = delay_chain_51; + 52: assign tap_out = delay_chain_52; + 53: assign tap_out = delay_chain_53; + 54: assign tap_out = delay_chain_54; + 55: assign tap_out = delay_chain_55; + 56: assign tap_out = delay_chain_56; + 57: assign tap_out = delay_chain_57; + 58: assign tap_out = delay_chain_58; + 59: assign tap_out = delay_chain_59; + 60: assign tap_out = delay_chain_60; + 61: assign tap_out = delay_chain_61; + 62: assign tap_out = delay_chain_62; + 63: assign tap_out = delay_chain_63; + default: + assign tap_out = delay_chain_0; + endcase + end // DELAY_SRC == "O" + else begin + case (idelay_count) + 0: assign tap_out = delay_chain_0; + 1: assign tap_out = delay_chain_1; + 2: assign tap_out = delay_chain_2; + 3: assign tap_out = delay_chain_3; + 4: assign tap_out = delay_chain_4; + 5: assign tap_out = delay_chain_5; + 6: assign tap_out = delay_chain_6; + 7: assign tap_out = delay_chain_7; + 8: assign tap_out = delay_chain_8; + 9: assign tap_out = delay_chain_9; + 10: assign tap_out = delay_chain_10; + 11: assign tap_out = delay_chain_11; + 12: assign tap_out = delay_chain_12; + 13: assign tap_out = delay_chain_13; + 14: assign tap_out = delay_chain_14; + 15: assign tap_out = delay_chain_15; + 16: assign tap_out = delay_chain_16; + 17: assign tap_out = delay_chain_17; + 18: assign tap_out = delay_chain_18; + 19: assign tap_out = delay_chain_19; + 20: assign tap_out = delay_chain_20; + 21: assign tap_out = delay_chain_21; + 22: assign tap_out = delay_chain_22; + 23: assign tap_out = delay_chain_23; + 24: assign tap_out = delay_chain_24; + 25: assign tap_out = delay_chain_25; + 26: assign tap_out = delay_chain_26; + 27: assign tap_out = delay_chain_27; + 28: assign tap_out = delay_chain_28; + 29: assign tap_out = delay_chain_29; + 30: assign tap_out = delay_chain_30; + 31: assign tap_out = delay_chain_31; + 32: assign tap_out = delay_chain_32; + 33: assign tap_out = delay_chain_33; + 34: assign tap_out = delay_chain_34; + 35: assign tap_out = delay_chain_35; + 36: assign tap_out = delay_chain_36; + 37: assign tap_out = delay_chain_37; + 38: assign tap_out = delay_chain_38; + 39: assign tap_out = delay_chain_39; + 40: assign tap_out = delay_chain_40; + 41: assign tap_out = delay_chain_41; + 42: assign tap_out = delay_chain_42; + 43: assign tap_out = delay_chain_43; + 44: assign tap_out = delay_chain_44; + 45: assign tap_out = delay_chain_45; + 46: assign tap_out = delay_chain_46; + 47: assign tap_out = delay_chain_47; + 48: assign tap_out = delay_chain_48; + 49: assign tap_out = delay_chain_49; + 50: assign tap_out = delay_chain_50; + 51: assign tap_out = delay_chain_51; + 52: assign tap_out = delay_chain_52; + 53: assign tap_out = delay_chain_53; + 54: assign tap_out = delay_chain_54; + 55: assign tap_out = delay_chain_55; + 56: assign tap_out = delay_chain_56; + 57: assign tap_out = delay_chain_57; + 58: assign tap_out = delay_chain_58; + 59: assign tap_out = delay_chain_59; + 60: assign tap_out = delay_chain_60; + 61: assign tap_out = delay_chain_61; + 62: assign tap_out = delay_chain_62; + 63: assign tap_out = delay_chain_63; + default: + assign tap_out = delay_chain_0; + endcase + end // DELAY_SRC = REST + end // always @ (idelay_count, odelay_count, t_in) + + specify + + specparam PATHPULSE$ = 0; + + endspecify + +endmodule // IODELAY + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IODELAY2.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IODELAY2.v new file mode 100644 index 0000000..c36f103 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IODELAY2.v @@ -0,0 +1,1104 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/stan/IODELAY2.v,v 1.25 2010/01/28 19:46:31 robh Exp $ +/////////////////////////////////////////////////////// +// Copyright (c) 2008 Xilinx Inc. +// All Right Reserved. +/////////////////////////////////////////////////////// +// +// ____ ___ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Input and/or Output Fixed or Variable Delay Element. +// /__/ /\ Filename : IODELAY2.v +// \ \ / \ +// \__\/\__ \ +// +// Revision: Date: Comment +// 1.0: 01/16/08: Initial version. +// 1.1: 08/21/08: CR479980 fix T polarity. +// 1.2: 09/05/08: CR480001 fix calibration. +// 1.3: 09/19/08: CR480004 fix phase detector mode. +// 1.4: 09/30/08: Add DATA_RATE attribute +// Add clock doubler +// Change RDY to BUSY +// 1.5 11/05/2008 I/O, structure change +// 1.6 11/19/2008 Change SIM_TAP_DELAY to SIM_TAPDELAY_VALUE +// 1.7 01/29/2009 IR504942, 504805, 504692 sync to data +// 1.8 02/04/2009 CR480001 Diff phase detector changes +// 02/04/2009 CR506027 sync_to_data off +// 1.9 02/12/2009 CR1016 update DOUT to match HW +// 1.10 03/05/2009 CR511015 VHDL - VER sync +// CR511054 Output at time 0 fix +// 1.11: 04/09/2009 CR480001 fix calibration. +// 1.12: 04/22/2009 CR518721 ODELAY value fix at time 0 +// 1.13: 05/19/2009 CR522171 Missing else in if-else-else. delay values +// 1.14: 07/23/2009 CR527208 Race condition in cal sig +// 1.15: 08/07/2009 CR511054 Time 0 output initialization +// CR529368 Input bypass ouput when delay line idle +// 1.16: 09/01/2009 CR531995 sync_to_data on +// 1.17: 11/04/2009 CR538116 fix calibrate_done when cal_delay saturates +// 1.18: 11/30/2009 CR538638 add parameter SIM_IDATAIN_INDELAY and SIM_ODATAIN_INDELAY +// 1.19: 01/28/2010 CR544661 transport (always@) SIM_*_INDELAY in case delay > period +// End Revision +/////////////////////////////////////////////////////// + +`timescale 1 ps / 1 ps + +module IODELAY2 ( + BUSY, + DATAOUT, + DATAOUT2, + DOUT, + TOUT, + CAL, + CE, + CLK, + IDATAIN, + INC, + IOCLK0, + IOCLK1, + ODATAIN, + RST, + T +); + + parameter COUNTER_WRAPAROUND = "WRAPAROUND"; // "WRAPAROUND", "STAY_AT_LIMIT" + parameter DATA_RATE = "SDR"; // "SDR", "DDR" + parameter DELAY_SRC = "IO"; // "IO", "IDATAIN", "ODATAIN" + parameter integer IDELAY2_VALUE = 0; // 0 to 255 inclusive + parameter IDELAY_MODE = "NORMAL"; // "NORMAL", "PCI" + parameter IDELAY_TYPE = "DEFAULT"; // "DEFAULT", "DIFF_PHASE_DETECTOR", "FIXED", "VARIABLE_FROM_HALF_MAX", "VARIABLE_FROM_ZERO" + parameter integer IDELAY_VALUE = 0; // 0 to 255 inclusive + parameter integer ODELAY_VALUE = 0; // 0 to 255 inclusive + parameter SERDES_MODE = "NONE"; // "NONE", "MASTER", "SLAVE" + parameter integer SIM_TAPDELAY_VALUE = 75; // 10 to 90 inclusive + + localparam integer SIM_IDATAIN_INDELAY = 110; + localparam integer SIM_ODATAIN_INDELAY = 110; + localparam WRAPAROUND = 1'b0; + localparam STAY_AT_LIMIT = 1'b1; + localparam SDR = 1'b1; + localparam DDR = 1'b0; + localparam IO = 2'b00; + localparam I = 2'b01; + localparam O = 2'b11; + localparam PCI = 1'b0; + localparam NORMAL = 1'b1; + localparam DEFAULT = 4'b1001; + localparam FIXED = 4'b1000; + localparam VAR = 4'b1100; + localparam DIFF_PHASE_DETECTOR = 4'b1111; + localparam NONE = 1'b1; + localparam MASTER = 1'b1; + localparam SLAVE = 1'b0; + + output BUSY; + output DATAOUT2; + output DATAOUT; + output DOUT; + output TOUT; + + input CAL; + input CE; + input CLK; + input IDATAIN; + input INC; + input IOCLK0; + input IOCLK1; + input ODATAIN; + input RST; + input T; + + + reg COUNTER_WRAPAROUND_BINARY = WRAPAROUND; + reg DATA_RATE_BINARY = SDR; + reg [1:0] DELAY_SRC_BINARY = IO; + reg [7:0] IDELAY2_VALUE_BINARY = 0; + reg IDELAY_MODE_BINARY = NORMAL; + reg [3:0] IDELAY_TYPE_BINARY = DEFAULT; + reg SERDES_MODE_BINARY = NONE; + reg [6:0] SIM_TAPDELAY_VALUE_BINARY = 75; + reg [7:0] IDELAY_VALUE_BINARY = 0; + reg [7:0] ODELAY_VALUE_BINARY = 0; + + tri0 GSR = glbl.GSR; + + wire BUSY_OUT; + wire DATAOUT2_OUT; + wire DATAOUT_OUT; + wire DOUT_OUT; + wire TOUT_OUT; + wire BUSY_OUTDELAY; + wire DATAOUT2_OUTDELAY; + wire DATAOUT_OUTDELAY; + wire DOUT_OUTDELAY; + wire TOUT_OUTDELAY; + + wire CAL_IN; + wire CE_IN; + wire CLK_IN; + wire IDATAIN_IN; + wire INC_IN; + wire IOCLK0_IN; + wire IOCLK1_IN; + wire ODATAIN_IN; + wire RST_IN; + wire T_IN; + wire GSR_IN; + wire CAL_INDELAY; + wire CE_INDELAY; + wire CLK_INDELAY; + reg IDATAIN_INDELAY; + wire INC_INDELAY; + wire IOCLK0_INDELAY; + wire IOCLK1_INDELAY; + reg ODATAIN_INDELAY; + wire RST_INDELAY; + wire T_INDELAY; + wire GSR_INDELAY; +//----------------------------------------------------------------------------- +//------------------- constants ----------------------------------------------- +//----------------------------------------------------------------------------- + localparam in_delay = 110; + localparam out_delay = 0; + localparam clk_delay = 1; + localparam MODULE_NAME = "IODELAY2"; + + wire output_delay_off; + wire input_delay_off; + wire [7:0] idelay_val_pe_reg; + reg [7:0] idelay_val_pe_m_reg = 0; + reg [7:0] idelay_val_pe_s_reg = 0; + wire [7:0] idelay_val_ne_reg; + reg [7:0] idelay_val_ne_m_reg = 0; + reg [7:0] idelay_val_ne_s_reg = 0; + reg sat_at_max_reg = WRAPAROUND; + reg rst_to_half_reg = 0; + reg ignore_rst = 0; + reg force_rx_reg = 0; + reg force_dly_dir_reg = 0; + reg [7:0] default_value = 8'ha5; + + wire rst_sig; + wire ce_sig; + wire inc_sig; + wire cal_sig; + reg ioclk0_int = 0; + reg ioclk1_int = 0; + wire ioclk_int; + reg first_edge = 0; + wire delay1_out_sig; + reg delay1_out = 0; + reg delay2_out = 0; + reg delay1_out_dly = 0; + reg tout_out_int = 0; + reg busy_out_int = 1; + reg busy_out_dly = 1; + reg busy_out_dly1 = 1; + +// Error flags + reg counter_wraparound_err_flag = 0; + reg data_rate_err_flag = 0; + reg serdes_mode_err_flag = 0; + reg odelay_value_err_flag = 0; + reg idelay_value_err_flag = 0; + reg sim_tap_delay_err_flag = 0; + reg idelay_type_err_flag = 0; + reg idelay_mode_err_flag = 0; + reg delay_src_err_flag = 0; + reg idelay2_value_err_flag = 0; + reg attr_err_flag = 0; +// internal logic + reg [4:0] cal_count = 5'b10010; + reg [7:0] cal_delay = 8'h00; + reg [7:0] max_delay = 8'h00; + reg [7:0] half_max = 8'h00; + reg [7:0] delay_val_pe_1 = 0; + reg [7:0] delay_val_ne_1 = 0; + wire delay_val_pe_clk; + wire delay_val_ne_clk; + wire delay1_reached; + reg delay1_reached_1 = 0; + reg delay1_reached_2 = 0; + wire delay1_working; + reg delay1_working_1 = 0; + reg delay1_working_2 = 0; + reg delay1_ignore = 0; + reg [7:0] delay_val_pe_2 = 0; + reg [7:0] delay_val_ne_2 = 0; + reg [7:0] odelay_val_pe_reg = 0; + reg [7:0] odelay_val_ne_reg = 0; + wire delay2_reached; + reg delay2_reached_1 = 0; + reg delay2_reached_2 = 0; + wire delay2_working; + reg delay2_working_1 = 0; + reg delay2_working_2 = 0; + reg delay2_ignore = 0; + reg delay1_in = 0; + reg delay2_in = 0; + reg calibrate = 0; + reg calibrate_done = 0; + reg sync_to_data_reg = 1; + reg pci_ce_reg = 0; + +//----------------------------------------------------------------------------- +//----------------- tasks / function ------------------------------------- +//----------------------------------------------------------------------------- +task inc_dec; +begin + if (GSR_INDELAY) begin + idelay_val_pe_m_reg <= IDELAY_VALUE_BINARY; + idelay_val_pe_s_reg <= IDELAY_VALUE_BINARY; + if (pci_ce_reg == 1) begin // PCI + idelay_val_ne_m_reg <= IDELAY2_VALUE_BINARY; + idelay_val_ne_s_reg <= IDELAY2_VALUE_BINARY; + end + else begin + idelay_val_ne_m_reg <= IDELAY_VALUE_BINARY; + idelay_val_ne_s_reg <= IDELAY_VALUE_BINARY; + end + end + else if (rst_sig) begin + if (rst_to_half_reg == 1'b1) begin + // rst to half + if (SERDES_MODE_BINARY == SLAVE) begin + if ((ignore_rst == 1'b0) && (IDELAY_TYPE_BINARY != DIFF_PHASE_DETECTOR)) begin + // all non diff phase detector slave rst + idelay_val_pe_s_reg <= half_max; + idelay_val_ne_s_reg <= half_max; + end + else if (ignore_rst == 1'b0) begin + // slave phase detector first rst + idelay_val_pe_m_reg <= half_max; + idelay_val_ne_m_reg <= half_max; + idelay_val_pe_s_reg <= half_max << 1; + idelay_val_ne_s_reg <= half_max << 1; + ignore_rst <= 1'b1; + end + else begin + // slave phase det second or more rst + if ((idelay_val_pe_m_reg + half_max) > max_delay) begin + idelay_val_pe_s_reg <= idelay_val_pe_m_reg + half_max - max_delay - 1; + idelay_val_ne_s_reg <= idelay_val_ne_m_reg + half_max - max_delay - 1; + end + else begin + idelay_val_pe_s_reg <= idelay_val_pe_m_reg + half_max; + idelay_val_ne_s_reg <= idelay_val_ne_m_reg + half_max; + end + end + end + else if ((ignore_rst == 1'b0) || (IDELAY_TYPE_BINARY != DIFF_PHASE_DETECTOR)) begin + // master or none, first diff phase rst or all others + idelay_val_pe_m_reg <= half_max; + idelay_val_ne_m_reg <= half_max; + ignore_rst <= 1'b1; + end + end + else begin + // rst to 0 + idelay_val_pe_m_reg <= 0; + idelay_val_ne_m_reg <= 0; + idelay_val_pe_s_reg <= 0; + idelay_val_ne_s_reg <= 0; + end + end + else if ( ~busy_out_int && ce_sig && ~rst_sig && + ((IDELAY_TYPE_BINARY == VAR) || + (IDELAY_TYPE_BINARY == DIFF_PHASE_DETECTOR)) ) begin //variable + if (inc_sig) begin // inc + // MASTER or NONE + // (lt max_delay inc m) + if (idelay_val_pe_m_reg < max_delay) begin + idelay_val_pe_m_reg <= idelay_val_pe_m_reg + 1; + end + // wrap to 0 wrap (gte max_delay and wrap to 0) + else if (sat_at_max_reg == WRAPAROUND) begin + idelay_val_pe_m_reg <= 8'h00; + end + // stay at max (gte max_delay and stay at max) + else begin + idelay_val_pe_m_reg <= max_delay; + end + // SLAVE + // (lt max_delay inc s) + if (idelay_val_pe_s_reg < max_delay) begin + idelay_val_pe_s_reg <= idelay_val_pe_s_reg + 1; + end + // wrap to 0 wrap (gte max_delay and wrap to 0) + else if (sat_at_max_reg == WRAPAROUND) begin + idelay_val_pe_s_reg <= 8'h00; + end + // stay at max (gte max_delay and stay at max) + else begin + idelay_val_pe_s_reg <= max_delay; + end + // MASTER or NONE + // (lt max_delay inc) + if (idelay_val_ne_m_reg < max_delay) begin + idelay_val_ne_m_reg <= idelay_val_ne_m_reg + 1; + end + // wrap to 0 wrap (gte max_delay and wrap to 0) + else if (sat_at_max_reg == WRAPAROUND) begin + idelay_val_ne_m_reg <= 8'h00; + end + // stay at max (gte max_delay and stay at max) + else begin + idelay_val_ne_m_reg <= max_delay; + end + // SLAVE + // (lt max_delay inc) + if (idelay_val_ne_s_reg < max_delay) begin + idelay_val_ne_s_reg <= idelay_val_ne_s_reg + 1; + end + // wrap to 0 wrap (gte max_delay and wrap to 0) + else if (sat_at_max_reg == WRAPAROUND) begin + idelay_val_ne_s_reg <= 8'h00; + end + // stay at max (gte max_delay and stay at max) + else begin + idelay_val_ne_s_reg <= max_delay; + end + end + else begin // dec + // MASTER or NONE + // (between 0 and max_delay dec) + if ((idelay_val_pe_m_reg > 8'h00) && + (idelay_val_pe_m_reg <= max_delay)) begin + idelay_val_pe_m_reg <= idelay_val_pe_m_reg - 1; + end + // stay at max (0) (eq 0 and stay at max/min) + else if ((sat_at_max_reg == STAY_AT_LIMIT) && (idelay_val_pe_m_reg == 0)) begin + idelay_val_pe_m_reg <= 8'h00; + end + // wrap to 0 wrap (gte max_delay or (eq 0 and wrap to max)) + else begin + idelay_val_pe_m_reg <= max_delay; + end + // SLAVE + // (between 0 and max_delay dec) + if ((idelay_val_pe_s_reg > 8'h00) && + (idelay_val_pe_s_reg <= max_delay)) begin + idelay_val_pe_s_reg <= idelay_val_pe_s_reg - 1; + end + // stay at max (0) (eq 0 and stay at max/min) + else if ((sat_at_max_reg == STAY_AT_LIMIT) && (idelay_val_pe_s_reg == 0)) begin + idelay_val_pe_s_reg <= 8'h00; + end + // wrap to 0 wrap (gte max_delay or (eq 0 and wrap to max)) + else begin + idelay_val_pe_s_reg <= max_delay; + end + // MASTER or NONE + // (between 0 and max_delay dec) + if ((idelay_val_ne_m_reg > 8'h00) && + (idelay_val_ne_m_reg <= max_delay)) begin + idelay_val_ne_m_reg <= idelay_val_ne_m_reg - 1; + end + // stay at max (0) (eq 0 and stay at max/min) + else if ((sat_at_max_reg == STAY_AT_LIMIT) && (idelay_val_ne_m_reg == 0)) begin + idelay_val_ne_m_reg <= 8'h00; + end + // wrap to 0 wrap (gte max_delay or (eq 0 and wrap to max)) + else begin + idelay_val_ne_m_reg <= max_delay; + end + // SLAVE + // (between 0 and max_delay dec) + if ((idelay_val_ne_s_reg > 8'h00) && + (idelay_val_ne_s_reg <= max_delay)) begin + idelay_val_ne_s_reg <= idelay_val_ne_s_reg - 1; + end + // stay at max (0) (eq 0 and stay at max/min) + else if ((sat_at_max_reg == STAY_AT_LIMIT) && (idelay_val_ne_s_reg == 0)) begin + idelay_val_ne_s_reg <= 8'h00; + end + // wrap to 0 wrap (gte max_delay or (eq 0 and wrap to max)) + else begin + idelay_val_ne_s_reg <= max_delay; + end + end + end + end +endtask + assign BUSY_OUT = busy_out_dly; + assign rst_sig = RST_INDELAY; + assign ce_sig = CE_INDELAY; + assign inc_sig = INC_INDELAY; + assign cal_sig = CAL_INDELAY; + assign output_delay_off = force_dly_dir_reg && force_rx_reg; + assign input_delay_off = force_dly_dir_reg && ~force_rx_reg; + assign idelay_val_pe_reg = (SERDES_MODE_BINARY == SLAVE) ? idelay_val_pe_s_reg : idelay_val_pe_m_reg; + assign idelay_val_ne_reg = (SERDES_MODE_BINARY == SLAVE) ? idelay_val_ne_s_reg : idelay_val_ne_m_reg; + assign delay1_reached = delay1_reached_1 || delay1_reached_2; + assign delay2_reached = delay2_reached_1 || delay2_reached_2; + assign delay1_working = delay1_working_1 || delay1_working_2; + assign delay2_working = delay2_working_1 || delay2_working_2; + + initial begin +//----------------------------------------------------------------------------- +//----------------- COUNTER_WRAPAROUND Check ---------------------------------- +//----------------------------------------------------------------------------- + if (COUNTER_WRAPAROUND == "WRAPAROUND") begin + COUNTER_WRAPAROUND_BINARY = WRAPAROUND; + sat_at_max_reg = WRAPAROUND; // wrap to 0 + end + else if (COUNTER_WRAPAROUND == "STAY_AT_LIMIT") begin + COUNTER_WRAPAROUND_BINARY = STAY_AT_LIMIT; + sat_at_max_reg = STAY_AT_LIMIT; // stay at max + end + else begin + #1; + $display("Attribute Syntax Error : The Attribute COUNTER_WRAPAROUND on %s instance %m is set to %s. Legal values for this attribute are WRAPAROUND or STAY_AT_LIMIT.\n", MODULE_NAME, COUNTER_WRAPAROUND); + counter_wraparound_err_flag = 1; + end + +//----------------------------------------------------------------------------- +//----------------- DATA_RATE Check ------------------------------------------ +//----------------------------------------------------------------------------- + if (DATA_RATE == "SDR") DATA_RATE_BINARY <= SDR; + else if (DATA_RATE == "DDR") DATA_RATE_BINARY <= DDR; + else begin + #1; + $display("Attribute Syntax Error : The attribute DATA_RATE on %s instance %m is set to %s. Legal values for this attribute are SDR or DDR\n", MODULE_NAME, DATA_RATE); + data_rate_err_flag = 1; + end + +//----------------------------------------------------------------------------- +//----------------- DELAY_SRC Check ------------------------------------------ +//----------------------------------------------------------------------------- + if (DELAY_SRC == "IO") begin + DELAY_SRC_BINARY = IO; + force_rx_reg = 0; + force_dly_dir_reg = 0; + end + else if (DELAY_SRC == "IDATAIN") begin + DELAY_SRC_BINARY = I; + force_rx_reg = 1; + force_dly_dir_reg = 1; + end + else if (DELAY_SRC == "ODATAIN") begin + DELAY_SRC_BINARY = O; + force_rx_reg = 0; + force_dly_dir_reg = 1; + end + else begin + #1; + $display("Attribute Syntax Error : The Attribute DELAY_SRC on %s instance %m is set to %s. Legal values for this attribute are IO, IDATAIN or ODATAIN.\n", MODULE_NAME, DELAY_SRC); + delay_src_err_flag = 1; + end + +//----------------------------------------------------------------------------- +//----------------- IDELAY2_VALUE Check --------------------------------------- +//----------------------------------------------------------------------------- + if ((IDELAY2_VALUE >= 0) && (IDELAY2_VALUE <= 255)) begin + IDELAY2_VALUE_BINARY = IDELAY2_VALUE; + if (IDELAY_MODE == "PCI") begin + idelay_val_ne_m_reg = IDELAY2_VALUE; + idelay_val_ne_s_reg = IDELAY2_VALUE; + end + end + else begin + #1; + $display("Attribute Syntax Error : The Attribute IDELAY2_VALUE on %s instance %m is set to %d. Legal values for this attribute are 0, 1, 2, ... 253, 254, 255.\n", MODULE_NAME, IDELAY2_VALUE); + idelay2_value_err_flag = 1; + end + +//----------------------------------------------------------------------------- +//----------------- IDELAY_MODE Check ----------------------------------------- +//----------------------------------------------------------------------------- + if (IDELAY_MODE == "NORMAL") begin + IDELAY_MODE_BINARY = NORMAL; + pci_ce_reg = 0; + end + else if (IDELAY_MODE == "PCI") begin + IDELAY_MODE_BINARY = PCI; + pci_ce_reg = 1; + end + else begin + #1; + $display("Attribute Syntax Error : The Attribute IDELAY_MODE on %s instance %m is set to %s. Legal values for this attribute are NORMAL or PCI.\n", MODULE_NAME, IDELAY_MODE); + idelay_mode_err_flag = 1; + end + +//----------------------------------------------------------------------------- +//----------------- IDELAY_TYPE Check ----------------------------------------- +//----------------------------------------------------------------------------- + if (IDELAY_TYPE == "DEFAULT") begin + IDELAY_TYPE_BINARY = DEFAULT; + end + else if (IDELAY_TYPE == "DIFF_PHASE_DETECTOR") begin + IDELAY_TYPE_BINARY = DIFF_PHASE_DETECTOR; + sat_at_max_reg = WRAPAROUND; + rst_to_half_reg = 1; + if (DELAY_SRC != "IDATAIN") begin + #1; + $display("Attribute Syntax Error : The Attribute IDELAY_TYPE on %s instance %m is set to %s and the attribute DELAY_SRC is set to %s. DELAY_SRC must be set to IDATAIN when IDELAY_TYPE is set to %s.\n", MODULE_NAME, IDELAY_TYPE, DELAY_SRC, IDELAY_TYPE); + idelay_type_err_flag = 1; + end + if (IDELAY_MODE != "NORMAL") begin + #1; + $display("Attribute Syntax Error : The Attribute IDELAY_TYPE on %s instance %m is set to %s and the attribute IDELAY_MODE is set to %s. IDELAY_MODE must be set to NORMAL when IDELAY_TYPE is set to %s.\n", MODULE_NAME, IDELAY_TYPE, IDELAY_MODE, IDELAY_TYPE); + idelay_type_err_flag = 1; + end + if ((SERDES_MODE != "MASTER") && (SERDES_MODE != "SLAVE")) begin + #1; + $display("Attribute Syntax Error : The Attribute IDELAY_TYPE on %s instance %m is set to %s and the attribute SERDES_MODE is set to %s. SERDES_MODE must be set to MASTER or SLAVE when IDELAY_TYPE is set to %s.\n", MODULE_NAME, IDELAY_TYPE, SERDES_MODE, IDELAY_TYPE); + idelay_type_err_flag = 1; + end + if (COUNTER_WRAPAROUND != "WRAPAROUND") begin + #1; + $display("Attribute Syntax Error : The Attribute IDELAY_TYPE on %s instance %m is set to %s and the attribute COUNTER_WRAPAROUND is set to %s. COUNTER_WRAPAROUND must be set to WRAPAROUND when IDELAY_TYPE is set to %s.\n", MODULE_NAME, IDELAY_TYPE, COUNTER_WRAPAROUND, IDELAY_TYPE); + idelay_type_err_flag = 1; + end + end + else if (IDELAY_TYPE == "FIXED") begin + IDELAY_TYPE_BINARY = FIXED; + end + else if (IDELAY_TYPE == "VARIABLE_FROM_HALF_MAX") begin + IDELAY_TYPE_BINARY = VAR; + rst_to_half_reg = 1; // variable from half max + end + else if (IDELAY_TYPE == "VARIABLE_FROM_ZERO") begin + IDELAY_TYPE_BINARY = VAR; + rst_to_half_reg = 0; // variable from zero + end + else begin + #1; + $display("Attribute Syntax Error : The Attribute IDELAY_TYPE on %s instance %m is set to %s. Legal values for this attribute are DEFAULT, DIFF_PHASE_DETECTOR, FIXED, VARIABLE_FROM_HALF_MAX, or VARIABLE_FROM_ZERO.\n", MODULE_NAME, IDELAY_TYPE); + idelay_type_err_flag = 1; + end + +//----------------------------------------------------------------------------- +//----------------- IDELAY_VALUE Check ---------------------------------------- +//----------------------------------------------------------------------------- + if ((IDELAY_VALUE >= 0) && (IDELAY_VALUE <= 255)) begin + IDELAY_VALUE_BINARY = IDELAY_VALUE; + idelay_val_pe_m_reg = IDELAY_VALUE; + idelay_val_pe_s_reg = IDELAY_VALUE; + if (IDELAY_MODE != "PCI") begin + idelay_val_ne_m_reg = IDELAY_VALUE; + idelay_val_ne_s_reg = IDELAY_VALUE; + end + end + else begin + #1; + $display("Attribute Syntax Error : The Attribute IDELAY_VALUE on %s instance %m is set to %d. Legal values for this attribute are 0, 1, 2, ... 253, 254, 255.\n", MODULE_NAME, IDELAY_VALUE); + idelay_value_err_flag = 1; + end + +//----------------------------------------------------------------------------- +//----------------- ODELAY_VALUE Check ---------------------------------------- +//----------------------------------------------------------------------------- + if ((ODELAY_VALUE >= 0) && (ODELAY_VALUE <= 255)) begin + ODELAY_VALUE_BINARY = ODELAY_VALUE; + odelay_val_pe_reg = ODELAY_VALUE; + odelay_val_ne_reg = ODELAY_VALUE; + end + else begin + #1; + $display("Attribute Syntax Error : The Attribute ODELAY_VALUE on %s instance %m is set to %d. Legal values for this attribute are 0, 1, 2, ... 253, 254, 255.\n", MODULE_NAME, ODELAY_VALUE); + odelay_value_err_flag = 1; + end + +//----------------------------------------------------------------------------- +//----------------- SERDES_MODE Check ----------------------------------------- +//----------------------------------------------------------------------------- + if (SERDES_MODE == "NONE") begin + SERDES_MODE_BINARY = NONE; + end + else if (SERDES_MODE == "MASTER") begin + SERDES_MODE_BINARY = MASTER; + end + else if (SERDES_MODE == "SLAVE") begin + SERDES_MODE_BINARY = SLAVE; + end + else begin + #1; + $display("Attribute Syntax Error : The Attribute SERDES_MODE on %s instance %m is set to %s. Legal values for this attribute are NONE, MASTER, or SLAVE.\n", MODULE_NAME, SERDES_MODE); + serdes_mode_err_flag = 1; + end +//----------------------------------------------------------------------------- +//----------------- SIM_TAPDELAY_VALUE Check ---------------------------------- +//----------------------------------------------------------------------------- + if ((SIM_TAPDELAY_VALUE >= 10) && (SIM_TAPDELAY_VALUE <= 90)) begin + SIM_TAPDELAY_VALUE_BINARY = SIM_TAPDELAY_VALUE; + end + else begin + #1; + $display("Attribute Syntax Error : The Attribute SIM_TAPDELAY_VALUE on %s instance %m is set to %d. Legal values for this attribute are between 10 and 90 ps inclusive.\n", MODULE_NAME, SIM_TAPDELAY_VALUE); + sim_tap_delay_err_flag = 1; + end + + if ( counter_wraparound_err_flag || serdes_mode_err_flag || + odelay_value_err_flag || idelay_value_err_flag || + idelay_type_err_flag || idelay_mode_err_flag || + delay_src_err_flag || idelay2_value_err_flag || + sim_tap_delay_err_flag || data_rate_err_flag) begin + attr_err_flag = 1; + #1; + $display("Attribute Errors detected in %s instance %m: Simulation cannot continue. Exiting. \n", MODULE_NAME); + $finish; + end + + end //initial begin parameter check + +//----------------------------------------------------------------------------- +//-------------------- Input / Output ----------------------------------------- +//----------------------------------------------------------------------------- + assign #(out_delay) BUSY_OUTDELAY = BUSY_OUT; + assign #(out_delay) DATAOUT_OUTDELAY = DATAOUT_OUT; + assign #(out_delay) DATAOUT2_OUTDELAY = DATAOUT2_OUT; + assign #(out_delay) DOUT_OUTDELAY = DOUT_OUT; + assign #(out_delay) TOUT_OUTDELAY = TOUT_OUT; + + assign #(in_delay) CAL_INDELAY = CAL_IN; + assign #(in_delay) CE_INDELAY = CE_IN; + assign #(clk_delay) CLK_INDELAY = CLK_IN; + assign #(in_delay) INC_INDELAY = INC_IN; + assign #(clk_delay) IOCLK0_INDELAY = IOCLK0_IN; + assign #(clk_delay) IOCLK1_INDELAY = IOCLK1_IN; + assign #(in_delay) RST_INDELAY = RST_IN; + assign #(in_delay) T_INDELAY = T_IN; + assign #(in_delay) GSR_INDELAY = GSR_IN; + +//----------------------------------------------------------------------------- +//----------------- I/O Assignments / Mux ------------------------------------- +//----------------------------------------------------------------------------- + // input delay paths + assign DATAOUT_OUT = delay1_out_sig; + assign DATAOUT2_OUT = (pci_ce_reg == 0) ? delay1_out_sig : delay2_out; + assign TOUT_OUT = (~output_delay_off && (~T_INDELAY || input_delay_off)) ? + tout_out_int : T_INDELAY; + + assign delay1_out_sig = ((IDELAY_TYPE_BINARY == DIFF_PHASE_DETECTOR) && + (SERDES_MODE_BINARY == SLAVE) && + (delay_val_pe_1 < half_max) ) ? + delay1_out_dly : delay1_out; +// output delay paths + assign DOUT_OUT = (~output_delay_off && (~T_INDELAY || input_delay_off)) ? delay1_out : 1'b0; + initial begin + first_edge <= #150 1; + wait (GSR_INDELAY === 1'b0); + end //initial begin other initializations + +//----------------------------------------------------------------------------- +//----------------- GLOBAL hidden GSR pin ------------------------------------- +//----------------------------------------------------------------------------- + + +//----------------------------------------------------------------------------- +//----------------- Bulk Input/Output Delay ----------------------------------- +//----------------------------------------------------------------------------- + always @(IDATAIN_IN) IDATAIN_INDELAY <= #(SIM_IDATAIN_INDELAY) IDATAIN_IN; + always @(ODATAIN_IN) ODATAIN_INDELAY <= #(SIM_ODATAIN_INDELAY) ODATAIN_IN; + +//----------------------------------------------------------------------------- +//----------------- DDR Doubler ----------------------------------------- +//----------------------------------------------------------------------------- + always @(posedge IOCLK0_INDELAY) begin + if (first_edge == 1) begin + ioclk0_int <= 1; + ioclk0_int <= #100 0; + end + end + + generate if(DATA_RATE == "DDR") + always @(posedge IOCLK1_INDELAY) begin + if (first_edge== 1) begin + ioclk1_int <= 1; + ioclk1_int <= #100 0; + end + end + endgenerate + + assign ioclk_int = ioclk0_int | ioclk1_int; + +//----------------------------------------------------------------------------- +//----------------- Delay Line Inputs ----------------------------------------- +//----------------------------------------------------------------------------- + always @(posedge ioclk_int) begin + delay1_out_dly <= delay1_out; + end + +// delay line 1 input + always @(IDATAIN_INDELAY or DATAOUT_OUT or T_INDELAY or ODATAIN_INDELAY or GSR_INDELAY) begin + if ((T_INDELAY || output_delay_off) && ~input_delay_off) begin // input delay + if (pci_ce_reg == 0 ) delay1_in <= IDATAIN_INDELAY; // NORMAL + else delay1_in <= IDATAIN_INDELAY ^ DATAOUT_OUT; // PCI + end + else begin // output delay + if (output_delay_off) delay1_in <= 0; + else delay1_in <= ODATAIN_INDELAY; + end + end + +// delay line 2 input + always @(IDATAIN_INDELAY or DATAOUT2_OUT or T_INDELAY or ODATAIN_INDELAY or GSR_INDELAY) begin + if ((T_INDELAY || output_delay_off) && ~input_delay_off) begin // input delay + if (pci_ce_reg == 0 ) delay2_in <= ~IDATAIN_INDELAY; // NORMAL + else delay2_in <= IDATAIN_INDELAY ^ DATAOUT2_OUT; // PCI + end + else begin // output delay + if (output_delay_off) delay2_in <= 0; + else delay2_in <= ~ODATAIN_INDELAY; + end + end + +//----------------------------------------------------------------------------- +//----------------- Delay Lines ----------------------------------------------- +//----------------------------------------------------------------------------- + always @(delay1_in or GSR_INDELAY) begin + if (GSR_INDELAY) begin + delay1_reached_1 <= 1'b0; + delay1_reached_2 <= 1'b0; + delay1_working_1 <= 1'b0; + delay1_working_2 <= 1'b0; + delay1_ignore <= delay1_in; + end + else if (delay1_in) begin + if (~delay1_working || delay1_reached) begin + if (delay1_working_1 == 1'b0) delay1_working_1 <= 1'b1; + else delay1_working_2 <= 1'b1; + if ((T_INDELAY || output_delay_off) && ~input_delay_off) begin // input delay + if (IDATAIN_INDELAY) begin // positive edge + if (delay1_reached_1 == 1'b0) + delay1_reached_1 <= #(SIM_TAPDELAY_VALUE*delay_val_pe_1) 1'b1; + else + delay1_reached_2 <= #(SIM_TAPDELAY_VALUE*delay_val_pe_1) 1'b1; + end + else begin // negative edge + if (delay1_reached_1 == 1'b0) + delay1_reached_1 <= #(SIM_TAPDELAY_VALUE*delay_val_ne_1) 1'b1; + else + delay1_reached_2 <= #(SIM_TAPDELAY_VALUE*delay_val_ne_1) 1'b1; + end + end + else begin // output delay + if (ODATAIN_INDELAY) begin // positive edge + if (delay1_reached_1 == 1'b0) + delay1_reached_1 <= #(SIM_TAPDELAY_VALUE*delay_val_pe_1) 1'b1; + else + delay1_reached_2 <= #(SIM_TAPDELAY_VALUE*delay_val_pe_1) 1'b1; + end + else begin // negative edge + if (delay1_reached_1 == 1'b0) + delay1_reached_1 <= #(SIM_TAPDELAY_VALUE*delay_val_ne_1) 1'b1; + else + delay1_reached_2 <= #(SIM_TAPDELAY_VALUE*delay_val_ne_1) 1'b1; + end + end + end + else begin + delay1_ignore <= 1'b1; + end + end + end + + always @(delay2_in or GSR_INDELAY) begin + if (GSR_INDELAY) begin + delay2_reached_1 <= 1'b0; + delay2_reached_2 <= 1'b0; + delay2_working_1 <= 1'b0; + delay2_working_2 <= 1'b0; + delay2_ignore <= delay2_in; + end + else if (delay2_in) begin + if (~delay2_working || delay2_reached) begin + if (delay2_working_1 == 1'b0) delay2_working_1 <= 1'b1; + else delay2_working_2 <= 1'b1; + if ((T_INDELAY || output_delay_off) && ~input_delay_off) begin // input delay + if (IDATAIN_INDELAY) begin // positive edge + if (delay2_reached_1 == 1'b0) + delay2_reached_1 <= #(SIM_TAPDELAY_VALUE*delay_val_pe_2) 1'b1; + else + delay2_reached_2 <= #(SIM_TAPDELAY_VALUE*delay_val_pe_2) 1'b1; + end + else begin // negative edge + if (delay2_reached_1 == 1'b0) + delay2_reached_1 <= #(SIM_TAPDELAY_VALUE*delay_val_ne_2) 1'b1; + else + delay2_reached_2 <= #(SIM_TAPDELAY_VALUE*delay_val_ne_2) 1'b1; + end + end + else begin // output delay + if (ODATAIN_INDELAY) begin // positive edge + if (delay2_reached_1 == 1'b0) + delay2_reached_1 <= #(SIM_TAPDELAY_VALUE*delay_val_pe_2) 1'b1; + else + delay2_reached_2 <= #(SIM_TAPDELAY_VALUE*delay_val_pe_2) 1'b1; + end + else begin // negative edge + if (delay2_reached_1 == 1'b0) + delay2_reached_1 <= #(SIM_TAPDELAY_VALUE*delay_val_ne_2) 1'b1; + else + delay2_reached_2 <= #(SIM_TAPDELAY_VALUE*delay_val_ne_2) 1'b1; + end + end + end + else begin + delay2_ignore <= 1'b1; + end + end + end + + always @(posedge delay1_reached) begin + delay1_ignore <= #1 1'b0; + end + + always @(posedge delay1_reached_1) begin + delay1_working_1 <= #1 1'b0; + delay1_reached_1 <= #1 1'b0; + end + + always @(posedge delay1_reached_2) begin + delay1_working_2 <= #1 1'b0; + delay1_reached_2 <= #1 1'b0; + end + + always @(posedge delay2_reached) begin + delay2_ignore <= #1 1'b0; + end + + always @(posedge delay2_reached_1) begin + delay2_working_1 <= #1 1'b0; + delay2_reached_1 <= #1 1'b0; + end + + always @(posedge delay2_reached_2) begin + delay2_working_2 <= #1 1'b0; + delay2_reached_2 <= #1 1'b0; + end + +//----------------------------------------------------------------------------- +//----------------- Output FF ------------------------------------------------- +//----------------------------------------------------------------------------- + always @(posedge delay1_reached or posedge delay2_reached or delay1_working or delay2_working or posedge delay1_ignore or posedge delay2_ignore or T_INDELAY or GSR_INDELAY) begin + if ((pci_ce_reg == 0) || (~T_INDELAY && ~output_delay_off) || + input_delay_off) begin //NORMAL in or output + if (GSR_INDELAY || ~first_edge || (~delay1_working && ~delay2_working)) begin + delay1_out <= delay1_in; + end + else if ( (delay1_reached && ~delay1_ignore) || + (delay1_ignore && ~delay1_out) ) begin + delay1_out <= 1'b1; + end + else if ( (delay2_reached && ~delay2_ignore) || + (delay2_ignore && delay1_out) ) begin + delay1_out <= 1'b0; + end + delay2_out <= 1'b0; + end + else begin // PCI in + if (GSR_INDELAY || delay1_reached) begin + delay1_out <= IDATAIN_INDELAY; + end + if (GSR_INDELAY || delay2_reached) begin + delay2_out <= IDATAIN_INDELAY; + end + end + end +//----------------------------------------------------------------------------- +//----------------- TOUT delay ------------------------------------------------ +//----------------------------------------------------------------------------- + always @(T_INDELAY) begin + #(SIM_TAPDELAY_VALUE); + tout_out_int <= T_INDELAY; + end + +//----------------------------------------------------------------------------- +//----------------- Delay Preset Values --------------------------------------- +//----------------------------------------------------------------------------- + assign delay_val_pe_clk = sync_to_data_reg ? delay1_in : ioclk_int; + assign delay_val_ne_clk = sync_to_data_reg ? delay2_in : ioclk_int; + + always @(posedge delay_val_pe_clk or posedge rst_sig or posedge busy_out_int) begin + if ((rst_sig == 1'b1) || (busy_out_int == 1'b1)) begin + busy_out_dly <= 1'b1; + busy_out_dly1 <= 1'b1; + end + else begin + busy_out_dly <= busy_out_dly1; + busy_out_dly1 <= busy_out_int; + end + end + + + always @(posedge delay_val_pe_clk or rst_sig) begin + if ((~T_INDELAY && ~output_delay_off) || input_delay_off) begin // output + delay_val_pe_1 <= odelay_val_pe_reg; + delay_val_pe_2 <= odelay_val_pe_reg; + end + // input delays + else if (IDELAY_TYPE_BINARY == DEFAULT) begin + delay_val_pe_1 <= default_value; + delay_val_pe_2 <= default_value; + end + else if (IDELAY_TYPE_BINARY == FIXED) begin + if (pci_ce_reg == 1) begin // PCI + delay_val_pe_1 <= IDELAY_VALUE_BINARY[7:0]; + delay_val_pe_2 <= IDELAY2_VALUE_BINARY[7:0]; + end + else begin // normal + delay_val_pe_1 <= IDELAY_VALUE_BINARY[7:0]; + delay_val_pe_2 <= IDELAY_VALUE_BINARY[7:0]; + end + end + else if (IDELAY_TYPE_BINARY == VAR) begin + if (pci_ce_reg == 1) begin // PCI + delay_val_pe_1 <= idelay_val_pe_reg; + delay_val_pe_2 <= idelay_val_ne_reg; + end + else begin // normal + delay_val_pe_1 <= idelay_val_pe_reg; + delay_val_pe_2 <= idelay_val_ne_reg; + end + end + else if (IDELAY_TYPE_BINARY == DIFF_PHASE_DETECTOR) begin + delay_val_pe_1 <= idelay_val_pe_reg; + delay_val_pe_2 <= idelay_val_ne_reg; + end + else begin // default + delay_val_pe_1 <= default_value; + delay_val_pe_2 <= default_value; + end + end + + always @(posedge delay_val_ne_clk or rst_sig) begin + if ((~T_INDELAY && ~output_delay_off) || input_delay_off) begin // output + delay_val_ne_1 <= odelay_val_ne_reg; + delay_val_ne_2 <= odelay_val_ne_reg; + end + //input delays + else if (IDELAY_TYPE_BINARY == DEFAULT) begin + delay_val_ne_1 <= default_value; + delay_val_ne_2 <= default_value; + end + else if (IDELAY_TYPE_BINARY == FIXED) begin + if (pci_ce_reg == 1) begin // PCI + delay_val_ne_1 <= IDELAY_VALUE_BINARY[7:0]; + delay_val_ne_2 <= IDELAY2_VALUE_BINARY[7:0]; + end + else begin // normal + delay_val_ne_1 <= IDELAY_VALUE_BINARY[7:0]; + delay_val_ne_2 <= IDELAY_VALUE_BINARY[7:0]; + end + end + else if (IDELAY_TYPE_BINARY == VAR) begin + if (pci_ce_reg == 1) begin // PCI + delay_val_ne_1 <= idelay_val_pe_reg; + delay_val_ne_2 <= idelay_val_ne_reg; + end + else begin // normal + delay_val_ne_1 <= idelay_val_pe_reg; + delay_val_ne_2 <= idelay_val_ne_reg; + end + end + else if (IDELAY_TYPE_BINARY == DIFF_PHASE_DETECTOR) begin + delay_val_ne_1 <= idelay_val_pe_reg; + delay_val_ne_2 <= idelay_val_ne_reg; + end + else begin // default + delay_val_ne_1 <= default_value; + delay_val_ne_2 <= default_value; + end + end + +//----------------------------------------------------------------------------- +//----------------- Max Count CAL --------------------------------------------- +//----------------------------------------------------------------------------- + + always @(posedge CLK_INDELAY or posedge GSR_INDELAY) begin + if (GSR_INDELAY) begin + cal_count <= 5'b10010; + busy_out_int <= 1'b1; // reset + end + else if (cal_sig && ~busy_out_int) begin + cal_count <= 5'b00000; + busy_out_int <= 1'b1; // begin cal + end + else if (ce_sig && ~busy_out_int) begin + cal_count <= 5'b10010; + busy_out_int <= 1'b1; // inc (busy high 2 clocks) + end + else if (busy_out_int && (cal_count < 5'b10011) ) begin + cal_count <= cal_count + 1; + busy_out_int <= 1'b1; // continue + end + else begin + busy_out_int <= 1'b0; // done + end + end + + always @(posedge ioclk_int) begin + if (~calibrate & ~calibrate_done && busy_out_int && (cal_count == 5'b01000) ) + calibrate <= 1'b1; + else + calibrate <= 1'b0; + end + + always @(cal_delay or calibrate or GSR_INDELAY or cal_sig or busy_out_int) begin + if ((GSR_INDELAY) || (cal_sig && ~busy_out_int)) begin + cal_delay <= 8'h00; + calibrate_done <= 1'b0; + end + else if (calibrate && (cal_delay !== 8'hff)) begin + #(SIM_TAPDELAY_VALUE); + if (calibrate) begin + cal_delay <= cal_delay + 1; + end + else begin + if ((pci_ce_reg == 1) && (DATA_RATE_BINARY == SDR)) begin + cal_delay <= cal_delay >> 1; + end + calibrate_done <= 1'b1; + end + end + else if (calibrate && (cal_delay == 8'hff)) begin + calibrate_done <= 1'b1; + end + else begin + #(SIM_TAPDELAY_VALUE); + calibrate_done <= 1'b0; + end + end + +//----------------------------------------------------------------------------- +//----------------- Delay Value Registers (INC/DEC) --------------------------- +//----------------------------------------------------------------------------- + always @(posedge CLK_INDELAY or rst_sig or GSR_INDELAY) begin + inc_dec; + end + + always @(calibrate_done) begin + if (calibrate_done) begin + max_delay <= cal_delay; + half_max <= cal_delay >> 1; + end + end + + assign BUSY = BUSY_OUTDELAY; + assign DATAOUT = DATAOUT_OUTDELAY; + assign DATAOUT2 = DATAOUT2_OUTDELAY; + assign DOUT = DOUT_OUTDELAY; + assign TOUT = TOUT_OUTDELAY; + + assign CAL_IN = CAL; + assign CE_IN = CE; + assign CLK_IN = CLK; + assign IDATAIN_IN = IDATAIN; + assign INC_IN = INC; + assign IOCLK0_IN = IOCLK0; + assign IOCLK1_IN = IOCLK1; + assign ODATAIN_IN = ODATAIN; + assign RST_IN = RST; + assign T_IN = T; + assign GSR_IN = GSR; + specify + ( CLK => BUSY) = (100, 100); + ( T => TOUT) = (0, 0); + + specparam PATHPULSE$ = 0; + endspecify +endmodule // IODELAY2 diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IODELAYE1.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IODELAYE1.v new file mode 100644 index 0000000..c787593 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IODELAYE1.v @@ -0,0 +1,677 @@ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Input and/or Output Fixed or Variable Delay Element. +// /___/ /\ Filename : IODELAYE1.v +// \ \ / \ Timestamp : Sat Sep 6 14:21:08 PDT 2008 +// \___\/\___\ +// +// Revision: +// 09/06/08 - Initial version. +// 02/02/09 - Fixed CNTVALUEOUT for when in DEFAULT/FIXED mode. +// 02/11/09 - IR 507221 CNTVALUEOUT fix -- Removed T dependency for I and O. +// 04/22/09 - CR 519123 -- Changed HIGH_PERFORMANCE_MODE default to FALSE. +// End Revision + +`timescale 1 ps / 1 ps + +module IODELAYE1 (CNTVALUEOUT, DATAOUT, C, CE, CINVCTRL, CLKIN, CNTVALUEIN, DATAIN, IDATAIN, INC, ODATAIN, RST, T); + + parameter CINVCTRL_SEL = "FALSE"; + parameter DELAY_SRC = "I"; + parameter HIGH_PERFORMANCE_MODE = "FALSE"; + parameter IDELAY_TYPE = "DEFAULT"; + parameter integer IDELAY_VALUE = 0; + parameter ODELAY_TYPE = "FIXED"; + parameter integer ODELAY_VALUE = 0; + parameter real REFCLK_FREQUENCY = 200.0; + parameter SIGNAL_PATTERN = "DATA"; + + output [4:0] CNTVALUEOUT; + output DATAOUT; + + input C; + input CE; + input CINVCTRL; + input CLKIN; + input [4:0] CNTVALUEIN; + input DATAIN; + input IDATAIN; + input INC; + input ODATAIN; + input RST; + input T ; + + + localparam ILEAK_ADJUST = 1.0; + localparam D_IOBDELAY_OFFSET = 0.0; + + tri0 GSR = glbl.GSR; + real CALC_TAPDELAY ; + real INIT_DELAY; + +//------------------- constants ------------------------------------ + + localparam MAX_DELAY_COUNT = 31; + localparam MIN_DELAY_COUNT = 0; + + localparam MAX_REFCLK_FREQUENCYL = 210.0; + localparam MIN_REFCLK_FREQUENCYL = 190.0; + + localparam MAX_REFCLK_FREQUENCYH = 310.0; + localparam MIN_REFCLK_FREQUENCYH = 290.0; + + +//------------------- variable declaration ------------------------- + + integer idelay_count, odelay_count; + integer CNTVALUEIN_INTEGER; + reg [4:0] cntvalueout_pre; + + + + reg data_mux = 0; + reg tap_out = 0; + + wire delay_chain_0, delay_chain_1, delay_chain_2, delay_chain_3, + delay_chain_4, delay_chain_5, delay_chain_6, delay_chain_7, + delay_chain_8, delay_chain_9, delay_chain_10, delay_chain_11, + delay_chain_12, delay_chain_13, delay_chain_14, delay_chain_15, + delay_chain_16, delay_chain_17, delay_chain_18, delay_chain_19, + delay_chain_20, delay_chain_21, delay_chain_22, delay_chain_23, + delay_chain_24, delay_chain_25, delay_chain_26, delay_chain_27, + delay_chain_28, delay_chain_29, delay_chain_30, delay_chain_31; + + reg c_in; + wire ce_in; + wire clkin_in; + wire [4:0] cntvaluein_in; + wire datain_in; + wire gsr_in; + wire idatain_in; + wire inc_in; + wire odatain_in; + wire rst_in; + wire t_in; + + wire c_in_pre; + + +//---------------------------------------------------------------------- +//------------------------------- Output ------------------------------ +//---------------------------------------------------------------------- + assign #INIT_DELAY DATAOUT = tap_out; + assign CNTVALUEOUT = cntvalueout_pre; + +//---------------------------------------------------------------------- +//------------------------------- Input ------------------------------- +//---------------------------------------------------------------------- + assign c_in_pre = C; + assign ce_in = CE; + assign cinvctrl_in = CINVCTRL; + assign clkin_in = CLKIN; + assign cntvaluein_in = CNTVALUEIN; + assign datain_in = DATAIN; + assign gsr_in = GSR; + assign idatain_in = IDATAIN; + assign inc_in = INC; + assign odatain_in = ODATAIN; + assign rst_in = RST; + assign t_in = T; + +//*** GLOBAL hidden GSR pin + always @(gsr_in) begin + if (gsr_in == 1'b1) begin + case (IDELAY_TYPE) + "DEFAULT" : begin + assign idelay_count = 0; + end + "VAR_LOADABLE": assign idelay_count = 0; + "FIXED" : assign idelay_count = IDELAY_VALUE; + "VARIABLE": assign idelay_count = IDELAY_VALUE; + endcase + case (ODELAY_TYPE) + "VAR_LOADABLE": assign odelay_count = 0; + "FIXED" : assign odelay_count = ODELAY_VALUE; + "VARIABLE": assign odelay_count = ODELAY_VALUE; + endcase + end + else if (gsr_in == 1'b0) begin + deassign idelay_count; + deassign odelay_count; + end + end + +//---------------------------------------------------------------------- +//------------------------ Dynamic clock inversion --------------------- +//---------------------------------------------------------------------- + + always @(c_in_pre or cinvctrl_in) begin + case (CINVCTRL_SEL) + "TRUE" : c_in = (cinvctrl_in ? ~c_in_pre : c_in_pre); + "FALSE" : c_in = c_in_pre; + endcase + end + +//---------------------------------------------------------------------- +//------------------------ CNTVALUEOUT --------------------- +//---------------------------------------------------------------------- + generate + case(DELAY_SRC) + "IO" : + + always @(idelay_count or odelay_count or t_in) begin + if (t_in == 1) begin +// 02/02/09 - Fixed CNTVALUEOUT for when in DEFAULT/FIXED mode. + if((IDELAY_TYPE != "DEFAULT") && (IDELAY_TYPE != "FIXED")) + assign cntvalueout_pre = idelay_count; + else + assign cntvalueout_pre = IDELAY_VALUE; + end + else if(t_in == 0) begin + if(ODELAY_TYPE != "FIXED") + assign cntvalueout_pre = odelay_count; + else + assign cntvalueout_pre = ODELAY_VALUE; + end + end + "O" : + always @(odelay_count) begin +// 02/02/09 - Fixed CNTVALUEOUT for when in DEFAULT/FIXED mode -- because of simprim. + if(ODELAY_TYPE != "FIXED") + assign cntvalueout_pre = odelay_count; + else + assign cntvalueout_pre = ODELAY_VALUE; + end + default : + always @(idelay_count) begin +// 02/02/09 - Fixed CNTVALUEOUT for when in DEFAULT/FIXED mode because of simprim. + if((IDELAY_TYPE != "DEFAULT") && (IDELAY_TYPE != "FIXED")) + assign cntvalueout_pre = idelay_count; + else + assign cntvalueout_pre = IDELAY_VALUE; + end + endcase + endgenerate + + + initial begin + + //-------- SIGNAL_PATTERN check + + case (SIGNAL_PATTERN) + "CLOCK", "DATA" : ; + default : begin + $display("Attribute Syntax Error : The attribute SIGNAL_PATTERN on IODELAYE1 instance %m is set to %s. Legal values for this attribute are DATA or CLOCK.", SIGNAL_PATTERN); + $finish; + end + endcase + + //-------- HIGH_PERFORMANCE_MODE check + + case (HIGH_PERFORMANCE_MODE) + "TRUE", "FALSE" : ; + default : begin + $display("Attribute Syntax Error : The attribute HIGH_PERFORMANCE_MODE on IODELAYE1 instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", HIGH_PERFORMANCE_MODE); + $finish; + end + endcase + + + //-------- IDELAY_TYPE check + + if (IDELAY_TYPE != "DEFAULT" && IDELAY_TYPE != "FIXED" && IDELAY_TYPE != "VARIABLE" && IDELAY_TYPE != "VAR_LOADABLE") begin + + $display("Attribute Syntax Error : The attribute IDELAY_TYPE on IODELAYE1 instance %m is set to %s. Legal values for this attribute are DEFAULT, FIXED, VARIABLE or VAR_LOADABLE", IDELAY_TYPE); + $finish; + + end + + //-------- ODELAY_TYPE check + + if (ODELAY_TYPE != "FIXED" && ODELAY_TYPE != "VARIABLE" && ODELAY_TYPE != "VAR_LOADABLE") begin + + $display("Attribute Syntax Error : The attribute ODELAY_TYPE on IODELAY instance is set to %s. Legal values for this attribute are FIXED, VARIABLE, VAR_LOADABLE", ODELAY_TYPE); + $finish; + + end + + //--------Bidirectional valid cases check + + if (DELAY_SRC == "IO") begin + if ((IDELAY_TYPE == "FIXED" && ODELAY_TYPE == "FIXED") | (IDELAY_TYPE == "FIXED" && ODELAY_TYPE == "VARIABLE") | (IDELAY_TYPE == "VARIABLE" && ODELAY_TYPE == "FIXED") | (IDELAY_TYPE == "VAR_LOADABLE" && ODELAY_TYPE == "VAR_LOADABLE")) begin + end + else begin + $display("Attribute Syntax Error : The attribute IDELAY_TYPE and ODELAY_TYPE during DELAY_SRC = \"IO\" on IODELAY instance is set to %s and %s respectively. Legal values for these attributes are FIXED-FIXED, VARIABLE-FIXED, FIXED-VARIABLE, VAR_LOADABLE-VAR_LOADABLE", IDELAY_TYPE, ODELAY_TYPE); + $finish; + + end + end + + //-------- IDELAY_VALUE check + + if (IDELAY_VALUE < MIN_DELAY_COUNT || IDELAY_VALUE > MAX_DELAY_COUNT) begin + $display("Attribute Syntax Error : The attribute IDELAY_VALUE on IODELAYE1 instance %m is set to %d. Legal values for this attribute are 0, 1, 2, 3, .... or 31", IDELAY_VALUE); + $finish; + + end + + + //-------- ODELAY_VALUE check + + if (ODELAY_VALUE < MIN_DELAY_COUNT || ODELAY_VALUE > MAX_DELAY_COUNT) begin + $display("Attribute Syntax Error : The attribute ODELAY_VALUE on IODELAYE1 instance %m is set to %d. Legal values for this attribute are 0, 1, 2, 3, .... or 31", ODELAY_VALUE); + $finish; + + end + + //-------- REFCLK_FREQUENCY check + + if (REFCLK_FREQUENCY < MIN_REFCLK_FREQUENCYL || REFCLK_FREQUENCY > MAX_REFCLK_FREQUENCYH) begin + $display("Attribute Syntax Error : The attribute REFCLK_FREQUENCY on IODELAYE1 instance %m is set to %f. Legal values for this attribute are 175.0 to 225.0", REFCLK_FREQUENCY); + $finish; + + end + + //-------- CALC_TAPDELAY check + + //CALC_TAPDELAY = ((1.0/REFCLK_FREQUENCY) * (1.0/64) * ILEAK_ADJUST * 1000000) + D_IOBDELAY_OFFSET ; + INIT_DELAY = 144; + + end // initial begin + + // CALC_TAPDELAY value + initial begin + if ((REFCLK_FREQUENCY <= MAX_REFCLK_FREQUENCYH) && (REFCLK_FREQUENCY >= MIN_REFCLK_FREQUENCYH)) + begin + CALC_TAPDELAY = 52; + end + else + begin + CALC_TAPDELAY = 78; + end + end + +//********************************************************* +//*** IDELAY_COUNT and ODELAY_COUNT +//********************************************************* + always @(posedge c_in) begin + + if (IDELAY_TYPE == "VARIABLE" | IDELAY_TYPE == "VAR_LOADABLE" |ODELAY_TYPE == "VARIABLE" | ODELAY_TYPE == "VAR_LOADABLE") begin + if (rst_in == 1'b1) begin + case (ODELAY_TYPE) + "VARIABLE" : odelay_count = ODELAY_VALUE; + "VAR_LOADABLE" : odelay_count = CNTVALUEIN_INTEGER; + endcase + case (IDELAY_TYPE) + "VARIABLE" : idelay_count = IDELAY_VALUE; + "VAR_LOADABLE" : idelay_count = CNTVALUEIN_INTEGER; + endcase + end + else if (rst_in == 1'b0 && ce_in == 1'b1) begin + if (inc_in == 1'b1) begin + case (IDELAY_TYPE) + "VARIABLE" : begin + if (idelay_count < MAX_DELAY_COUNT) + idelay_count = idelay_count + 1; + else if (idelay_count == MAX_DELAY_COUNT) + idelay_count = MIN_DELAY_COUNT; + end + "VAR_LOADABLE" : begin + if (idelay_count < MAX_DELAY_COUNT) + idelay_count = idelay_count + 1; + else if (idelay_count == MAX_DELAY_COUNT) + idelay_count = MIN_DELAY_COUNT; + end + endcase + case (ODELAY_TYPE) + "VARIABLE" : begin + if (odelay_count < MAX_DELAY_COUNT) + odelay_count = odelay_count + 1; + else if (odelay_count == MAX_DELAY_COUNT) + odelay_count = MIN_DELAY_COUNT; + end + "VAR_LOADABLE" : begin + if (odelay_count < MAX_DELAY_COUNT) + odelay_count = odelay_count + 1; + else if (odelay_count == MAX_DELAY_COUNT) + odelay_count = MIN_DELAY_COUNT; + end + endcase + end + else if (inc_in == 1'b0) begin + case (IDELAY_TYPE) + "VARIABLE" : begin + if (idelay_count > MIN_DELAY_COUNT) + idelay_count = idelay_count - 1; + else if (idelay_count == MIN_DELAY_COUNT) + idelay_count = MAX_DELAY_COUNT; + end + "VAR_LOADABLE" : begin + if (idelay_count > MIN_DELAY_COUNT) + idelay_count = idelay_count - 1; + else if (idelay_count == MIN_DELAY_COUNT) + idelay_count = MAX_DELAY_COUNT; + end + endcase + case (ODELAY_TYPE) + "VARIABLE" : begin + if (odelay_count > MIN_DELAY_COUNT) + odelay_count = odelay_count - 1; + else if (odelay_count == MIN_DELAY_COUNT) + odelay_count = MAX_DELAY_COUNT; + end + "VAR_LOADABLE" : begin + if (odelay_count > MIN_DELAY_COUNT) + odelay_count = odelay_count - 1; + else if (odelay_count == MIN_DELAY_COUNT) + odelay_count = MAX_DELAY_COUNT; + end + endcase + end + end + end // + end // always @ (posedge c_in) + + always @(cntvaluein_in or gsr_in) begin + case (cntvaluein_in) + 5'b00000 : assign CNTVALUEIN_INTEGER = 0; + 5'b00001 : assign CNTVALUEIN_INTEGER = 1; + 5'b00010 : assign CNTVALUEIN_INTEGER = 2; + 5'b00011 : assign CNTVALUEIN_INTEGER = 3; + 5'b00100 : assign CNTVALUEIN_INTEGER = 4; + 5'b00101 : assign CNTVALUEIN_INTEGER = 5; + 5'b00110 : assign CNTVALUEIN_INTEGER = 6; + 5'b00111 : assign CNTVALUEIN_INTEGER = 7; + 5'b01000 : assign CNTVALUEIN_INTEGER = 8; + 5'b01001 : assign CNTVALUEIN_INTEGER = 9; + 5'b01010 : assign CNTVALUEIN_INTEGER = 10; + 5'b01011 : assign CNTVALUEIN_INTEGER = 11; + 5'b01100 : assign CNTVALUEIN_INTEGER = 12; + 5'b01101 : assign CNTVALUEIN_INTEGER = 13; + 5'b01110 : assign CNTVALUEIN_INTEGER = 14; + 5'b01111 : assign CNTVALUEIN_INTEGER = 15; + 5'b10000 : assign CNTVALUEIN_INTEGER = 16; + 5'b10001 : assign CNTVALUEIN_INTEGER = 17; + 5'b10010 : assign CNTVALUEIN_INTEGER = 18; + 5'b10011 : assign CNTVALUEIN_INTEGER = 19; + 5'b10100 : assign CNTVALUEIN_INTEGER = 20; + 5'b10101 : assign CNTVALUEIN_INTEGER = 21; + 5'b10110 : assign CNTVALUEIN_INTEGER = 22; + 5'b10111 : assign CNTVALUEIN_INTEGER = 23; + 5'b11000 : assign CNTVALUEIN_INTEGER = 24; + 5'b11001 : assign CNTVALUEIN_INTEGER = 25; + 5'b11010 : assign CNTVALUEIN_INTEGER = 26; + 5'b11011 : assign CNTVALUEIN_INTEGER = 27; + 5'b11100 : assign CNTVALUEIN_INTEGER = 28; + 5'b11101 : assign CNTVALUEIN_INTEGER = 29; + 5'b11110 : assign CNTVALUEIN_INTEGER = 30; + 5'b11111 : assign CNTVALUEIN_INTEGER = 31; + endcase + end + + +//********************************************************* +//*** SELECT IDATA signal +//********************************************************* + + always @(datain_in or idatain_in, odatain_in, t_in, clkin_in ) begin + + case (DELAY_SRC) + + "I" : begin + data_mux <= idatain_in; + end + "O" : begin + data_mux <= odatain_in; + end + "IO" : begin + data_mux <= ((idatain_in) & t_in ) | ((odatain_in) & ~t_in); + end + "DATAIN" : begin + data_mux <= datain_in; + end + "CLKIN" : begin + data_mux <= clkin_in; + end + default : begin + $display("Attribute Syntax Error : The attribute DELAY_SRC on IODELAYE1 instance %m is set to %s. Legal values for this attribute are I, O, CLKIN, IO or DATAIN", DELAY_SRC); + $finish; + end + + endcase // case(DELAY_SRC) + + end // always @ (data_in or idatain_in or odatain_in or t_in, clkin_in) + + +//********************************************************* +//*** DELAY IDATA signal +//********************************************************* +// assign #(DELAY_D + INIT_DELAY) delay_chain_0 = data_mux; + assign delay_chain_0 = data_mux; + assign #CALC_TAPDELAY delay_chain_1 = delay_chain_0; + assign #CALC_TAPDELAY delay_chain_2 = delay_chain_1; + assign #CALC_TAPDELAY delay_chain_3 = delay_chain_2; + assign #CALC_TAPDELAY delay_chain_4 = delay_chain_3; + assign #CALC_TAPDELAY delay_chain_5 = delay_chain_4; + assign #CALC_TAPDELAY delay_chain_6 = delay_chain_5; + assign #CALC_TAPDELAY delay_chain_7 = delay_chain_6; + assign #CALC_TAPDELAY delay_chain_8 = delay_chain_7; + assign #CALC_TAPDELAY delay_chain_9 = delay_chain_8; + assign #CALC_TAPDELAY delay_chain_10 = delay_chain_9; + assign #CALC_TAPDELAY delay_chain_11 = delay_chain_10; + assign #CALC_TAPDELAY delay_chain_12 = delay_chain_11; + assign #CALC_TAPDELAY delay_chain_13 = delay_chain_12; + assign #CALC_TAPDELAY delay_chain_14 = delay_chain_13; + assign #CALC_TAPDELAY delay_chain_15 = delay_chain_14; + assign #CALC_TAPDELAY delay_chain_16 = delay_chain_15; + assign #CALC_TAPDELAY delay_chain_17 = delay_chain_16; + assign #CALC_TAPDELAY delay_chain_18 = delay_chain_17; + assign #CALC_TAPDELAY delay_chain_19 = delay_chain_18; + assign #CALC_TAPDELAY delay_chain_20 = delay_chain_19; + assign #CALC_TAPDELAY delay_chain_21 = delay_chain_20; + assign #CALC_TAPDELAY delay_chain_22 = delay_chain_21; + assign #CALC_TAPDELAY delay_chain_23 = delay_chain_22; + assign #CALC_TAPDELAY delay_chain_24 = delay_chain_23; + assign #CALC_TAPDELAY delay_chain_25 = delay_chain_24; + assign #CALC_TAPDELAY delay_chain_26 = delay_chain_25; + assign #CALC_TAPDELAY delay_chain_27 = delay_chain_26; + assign #CALC_TAPDELAY delay_chain_28 = delay_chain_27; + assign #CALC_TAPDELAY delay_chain_29 = delay_chain_28; + assign #CALC_TAPDELAY delay_chain_30 = delay_chain_29; + assign #CALC_TAPDELAY delay_chain_31 = delay_chain_30; + +//********************************************************* +//*** assign delay +//********************************************************* + always @(idelay_count, odelay_count, t_in) begin + if(DELAY_SRC == "IO") begin + if (t_in == 1'b1) + case (idelay_count) + 0: assign tap_out = delay_chain_0; + 1: assign tap_out = delay_chain_1; + 2: assign tap_out = delay_chain_2; + 3: assign tap_out = delay_chain_3; + 4: assign tap_out = delay_chain_4; + 5: assign tap_out = delay_chain_5; + 6: assign tap_out = delay_chain_6; + 7: assign tap_out = delay_chain_7; + 8: assign tap_out = delay_chain_8; + 9: assign tap_out = delay_chain_9; + 10: assign tap_out = delay_chain_10; + 11: assign tap_out = delay_chain_11; + 12: assign tap_out = delay_chain_12; + 13: assign tap_out = delay_chain_13; + 14: assign tap_out = delay_chain_14; + 15: assign tap_out = delay_chain_15; + 16: assign tap_out = delay_chain_16; + 17: assign tap_out = delay_chain_17; + 18: assign tap_out = delay_chain_18; + 19: assign tap_out = delay_chain_19; + 20: assign tap_out = delay_chain_20; + 21: assign tap_out = delay_chain_21; + 22: assign tap_out = delay_chain_22; + 23: assign tap_out = delay_chain_23; + 24: assign tap_out = delay_chain_24; + 25: assign tap_out = delay_chain_25; + 26: assign tap_out = delay_chain_26; + 27: assign tap_out = delay_chain_27; + 28: assign tap_out = delay_chain_28; + 29: assign tap_out = delay_chain_29; + 30: assign tap_out = delay_chain_30; + 31: assign tap_out = delay_chain_31; + default: + assign tap_out = delay_chain_0; + endcase + else if (t_in == 1'b0) + case (odelay_count) + 0: assign tap_out = delay_chain_0; + 1: assign tap_out = delay_chain_1; + 2: assign tap_out = delay_chain_2; + 3: assign tap_out = delay_chain_3; + 4: assign tap_out = delay_chain_4; + 5: assign tap_out = delay_chain_5; + 6: assign tap_out = delay_chain_6; + 7: assign tap_out = delay_chain_7; + 8: assign tap_out = delay_chain_8; + 9: assign tap_out = delay_chain_9; + 10: assign tap_out = delay_chain_10; + 11: assign tap_out = delay_chain_11; + 12: assign tap_out = delay_chain_12; + 13: assign tap_out = delay_chain_13; + 14: assign tap_out = delay_chain_14; + 15: assign tap_out = delay_chain_15; + 16: assign tap_out = delay_chain_16; + 17: assign tap_out = delay_chain_17; + 18: assign tap_out = delay_chain_18; + 19: assign tap_out = delay_chain_19; + 20: assign tap_out = delay_chain_20; + 21: assign tap_out = delay_chain_21; + 22: assign tap_out = delay_chain_22; + 23: assign tap_out = delay_chain_23; + 24: assign tap_out = delay_chain_24; + 25: assign tap_out = delay_chain_25; + 26: assign tap_out = delay_chain_26; + 27: assign tap_out = delay_chain_27; + 28: assign tap_out = delay_chain_28; + 29: assign tap_out = delay_chain_29; + 30: assign tap_out = delay_chain_30; + 31: assign tap_out = delay_chain_31; + default: + assign tap_out = delay_chain_0; + endcase + end // DELAY_SRC == "IO" + else if(DELAY_SRC == "O") begin + case (odelay_count) + 0: assign tap_out = delay_chain_0; + 1: assign tap_out = delay_chain_1; + 2: assign tap_out = delay_chain_2; + 3: assign tap_out = delay_chain_3; + 4: assign tap_out = delay_chain_4; + 5: assign tap_out = delay_chain_5; + 6: assign tap_out = delay_chain_6; + 7: assign tap_out = delay_chain_7; + 8: assign tap_out = delay_chain_8; + 9: assign tap_out = delay_chain_9; + 10: assign tap_out = delay_chain_10; + 11: assign tap_out = delay_chain_11; + 12: assign tap_out = delay_chain_12; + 13: assign tap_out = delay_chain_13; + 14: assign tap_out = delay_chain_14; + 15: assign tap_out = delay_chain_15; + 16: assign tap_out = delay_chain_16; + 17: assign tap_out = delay_chain_17; + 18: assign tap_out = delay_chain_18; + 19: assign tap_out = delay_chain_19; + 20: assign tap_out = delay_chain_20; + 21: assign tap_out = delay_chain_21; + 22: assign tap_out = delay_chain_22; + 23: assign tap_out = delay_chain_23; + 24: assign tap_out = delay_chain_24; + 25: assign tap_out = delay_chain_25; + 26: assign tap_out = delay_chain_26; + 27: assign tap_out = delay_chain_27; + 28: assign tap_out = delay_chain_28; + 29: assign tap_out = delay_chain_29; + 30: assign tap_out = delay_chain_30; + 31: assign tap_out = delay_chain_31; + default: + assign tap_out = delay_chain_0; + endcase + end // DELAY_SRC == "O" + else begin + case (idelay_count) + 0: assign tap_out = delay_chain_0; + 1: assign tap_out = delay_chain_1; + 2: assign tap_out = delay_chain_2; + 3: assign tap_out = delay_chain_3; + 4: assign tap_out = delay_chain_4; + 5: assign tap_out = delay_chain_5; + 6: assign tap_out = delay_chain_6; + 7: assign tap_out = delay_chain_7; + 8: assign tap_out = delay_chain_8; + 9: assign tap_out = delay_chain_9; + 10: assign tap_out = delay_chain_10; + 11: assign tap_out = delay_chain_11; + 12: assign tap_out = delay_chain_12; + 13: assign tap_out = delay_chain_13; + 14: assign tap_out = delay_chain_14; + 15: assign tap_out = delay_chain_15; + 16: assign tap_out = delay_chain_16; + 17: assign tap_out = delay_chain_17; + 18: assign tap_out = delay_chain_18; + 19: assign tap_out = delay_chain_19; + 20: assign tap_out = delay_chain_20; + 21: assign tap_out = delay_chain_21; + 22: assign tap_out = delay_chain_22; + 23: assign tap_out = delay_chain_23; + 24: assign tap_out = delay_chain_24; + 25: assign tap_out = delay_chain_25; + 26: assign tap_out = delay_chain_26; + 27: assign tap_out = delay_chain_27; + 28: assign tap_out = delay_chain_28; + 29: assign tap_out = delay_chain_29; + 30: assign tap_out = delay_chain_30; + 31: assign tap_out = delay_chain_31; + default: + assign tap_out = delay_chain_0; + endcase + end // DELAY_SRC = REST + end // always @ (idelay_count, odelay_count, t_in) + + + specify + ( C => CNTVALUEOUT[0]) = (100, 100); + ( C => CNTVALUEOUT[1]) = (100, 100); + ( C => CNTVALUEOUT[2]) = (100, 100); + ( C => CNTVALUEOUT[3]) = (100, 100); + ( C => CNTVALUEOUT[4]) = (100, 100); + ( C => DATAOUT) = (0, 0); + ( CINVCTRL => CNTVALUEOUT[0]) = (0, 0); + ( CINVCTRL => CNTVALUEOUT[1]) = (0, 0); + ( CINVCTRL => CNTVALUEOUT[2]) = (0, 0); + ( CINVCTRL => CNTVALUEOUT[3]) = (0, 0); + ( CINVCTRL => CNTVALUEOUT[4]) = (0, 0); + ( CINVCTRL => DATAOUT) = (0, 0); + ( CLKIN => DATAOUT) = (0, 0); + ( DATAIN => DATAOUT) = (0, 0); + ( IDATAIN => DATAOUT) = (0, 0); + ( ODATAIN => DATAOUT) = (0, 0); + ( T => CNTVALUEOUT[0]) = (0, 0); + ( T => CNTVALUEOUT[1]) = (0, 0); + ( T => CNTVALUEOUT[2]) = (0, 0); + ( T => CNTVALUEOUT[3]) = (0, 0); + ( T => CNTVALUEOUT[4]) = (0, 0); + ( T => DATAOUT) = (0, 0); + + specparam PATHPULSE$ = 1; + endspecify + +endmodule // IODELAYE1 + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IODRP2.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IODRP2.v new file mode 100644 index 0000000..f0ada7f --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IODRP2.v @@ -0,0 +1,1147 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/stan/IODRP2.v,v 1.16 2009/11/05 16:59:02 robh Exp $ +/////////////////////////////////////////////////////// +// Copyright (c) 2008 Xilinx Inc. +// All Right Reserved. +/////////////////////////////////////////////////////// +// +// ____ ___ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / IODELAY2 Dynamic Reconfiguration Port +// /__/ /\ Filename : IODRP2.v +// \ \ / \ +// \__\/\__ \ +// +// Revision: Date: Comment +// 1.0: 04/16/08: Initial version. +// 1.1: 08/15/08: Change BSKT to BKST per yml +// Remove parameters and checking per yml +// 1.2: 08/21/08: CR479980 fix T polarity. +// Add SIM_TAP_DELAY attribute +// 1.3: 09/05/08: CR480001 fix calibration. +// 1.4 09/30/08: Add DATA_RATA attribute +// Add clock doubler +// 1.5 11/05/2008 I/O, structure change +// 1.6 11/19/2008 Change SIM_TAP_DELAY to SIM_TAPDELAY_VALUE +// 1.7 01/29/2009 IR504942, 504805, 504692 sync to data +// 1.8 02/04/2009 CR506027 IODRP state machine, sync_to_data off +// 02/04/2009 CR502236 lumped delay reg +// 1.9 02/12/2009 CR1016 update DOUT to match HW +// 1.10 03/05/2009 CR511015 VHDL - VER sync +// CR511054 Output at time 0 fix +// 1.11: 04/09/2009 CR480001 fix calibration. +// 1.12: 04/22/2009 CR518721 ODELAY value fix at time 0 +// 1.13: 05/19/2009 CR522171 Missing else in if-else-else. delay values +// 1.14: 07/23/2009 CR527208 Race condition in cal sig +// 1.15: 08/07/2009 CR511054 Time 0 output initialization +// CR529368 Input bypass ouput when delay line idle +// 1.16: 09/01/2009 CR531995 sync_to_data on +// remove pci_ce_reg, byp_ts_ff_reg, byp_op_ff_reg from addr6 +// 1.17: 11/04/2009 CR538116 fix calibrate_done when cal_delay saturates +// End Revision +/////////////////////////////////////////////////////// + +`timescale 1 ps / 1 ps + +module IODRP2 ( + DATAOUT, + DATAOUT2, + DOUT, + SDO, + TOUT, + ADD, + BKST, + CLK, + CS, + IDATAIN, + IOCLK0, + IOCLK1, + ODATAIN, + SDI, + T +); + + parameter DATA_RATE = "SDR"; // "SDR", "DDR" + parameter integer SIM_TAPDELAY_VALUE = 75; // 10 to 90 inclusive + + localparam IDELAY_MODE = "NORMAL"; // "NORMAL", "PCI" + localparam WRAPAROUND = 1'b0; + localparam STAY_AT_LIMIT = 1'b1; + localparam SDR = 1'b1; + localparam DDR = 1'b0; + localparam IO = 2'b00; + localparam I = 2'b01; + localparam O = 2'b11; + localparam PCI = 1'b0; + localparam NORMAL = 1'b1; + localparam DEFAULT = 4'b1001; + localparam FIXED = 4'b1000; + localparam VAR = 4'b1100; + localparam DIFF_PHASE_DETECTOR = 4'b1111; + localparam NONE = 1'b1; + localparam MASTER = 1'b1; + localparam SLAVE = 1'b0; + + output DATAOUT2; + output DATAOUT; + output DOUT; + output SDO; + output TOUT; + + input ADD; + input BKST; + input CLK; + input CS; + input IDATAIN; + input IOCLK0; + input IOCLK1; + input ODATAIN; + input SDI; + input T; + + + reg COUNTER_WRAPAROUND_BINARY = WRAPAROUND; + reg DATA_RATE_BINARY = SDR; + reg [7:0] IDELAY2_VALUE_BINARY = 0; + reg IDELAY_MODE_BINARY = NORMAL; + reg [3:0] IDELAY_TYPE_BINARY = VAR; + reg SERDES_MODE_BINARY = NONE; + reg [6:0] SIM_TAPDELAY_VALUE_BINARY = 75; + reg [7:0] IDELAY_VALUE_BINARY = 0; + reg [7:0] ODELAY_VALUE_BINARY = 0; + + tri0 GSR = glbl.GSR; + + wire DATAOUT2_OUT; + wire DATAOUT_OUT; + wire DOUT_OUT; + wire SDO_OUT; + wire TOUT_OUT; + wire DATAOUT2_OUTDELAY; + wire DATAOUT_OUTDELAY; + wire DOUT_OUTDELAY; + wire SDO_OUTDELAY; + wire TOUT_OUTDELAY; + + wire ADD_IN; + wire BKST_IN; + wire CLK_IN; + wire CS_IN; + wire IDATAIN_IN; + wire IOCLK0_IN; + wire IOCLK1_IN; + wire ODATAIN_IN; + wire SDI_IN; + wire T_IN; + wire GSR_IN; + wire ADD_INDELAY; + wire BKST_INDELAY; + wire CLK_INDELAY; + wire CS_INDELAY; + wire IDATAIN_INDELAY; + wire IOCLK0_INDELAY; + wire IOCLK1_INDELAY; + wire MEMUPDATE_INDELAY; + wire ODATAIN_INDELAY; + wire SDI_INDELAY; + wire T_INDELAY; + wire GSR_INDELAY; +//----------------------------------------------------------------------------- +//------------------- constants ----------------------------------------------- +//----------------------------------------------------------------------------- + localparam in_delay = 110; + localparam out_delay = 0; + localparam clk_delay = 1; + localparam MODULE_NAME = "IODRP2"; + localparam IDLE = 0, + ADDR_ACTIVE = 1, + DATA_ACTIVE = 2; + + wire output_delay_off; + wire input_delay_off; + wire [7:0] idelay_val_pe_reg; + reg [7:0] idelay_val_pe_m_reg = 0; + reg [7:0] idelay_val_pe_s_reg = 0; + wire [7:0] idelay_val_ne_reg; + reg [7:0] idelay_val_ne_m_reg = 0; + reg [7:0] idelay_val_ne_s_reg = 0; + reg sat_at_max_reg = WRAPAROUND; + reg rst_to_half_reg = 0; + reg ignore_rst = 0; + reg force_rx_reg = 0; + reg force_dly_dir_reg = 0; + reg [7:0] default_value = 8'ha5; + + wire rst_sig; + wire ce_sig; + wire inc_sig; + wire cal_sig; + reg ioclk0_int = 0; + reg ioclk1_int = 0; + wire ioclk_int; + reg first_edge = 0; + wire cs_sig; + wire snapback_sig; + wire half_sig; + wire delay1_out_sig; + reg delay1_out = 0; + reg delay2_out = 0; + reg delay1_out_dly = 0; + reg tout_out_int = 0; + reg busy_out_int = 1; + reg busy_out_dly = 1; + reg busy_out_dly1 = 1; + +// Error flags + reg counter_wraparound_err_flag = 0; + reg data_rate_err_flag = 0; + reg serdes_mode_err_flag = 0; + reg odelay_value_err_flag = 0; + reg idelay_value_err_flag = 0; + reg sim_tap_delay_err_flag = 0; + reg idelay_type_err_flag = 0; + reg idelay_mode_err_flag = 0; + reg delay_src_err_flag = 0; + reg idelay2_value_err_flag = 0; + reg attr_err_flag = 0; +// internal logic + reg [4:0] cal_count = 5'b10010; + reg [7:0] cal_delay = 8'h00; + reg [7:0] max_delay = 8'h00; + reg [7:0] half_max = 8'h00; + reg [7:0] delay_val_pe_1 = 0; + reg [7:0] delay_val_ne_1 = 0; + wire delay_val_pe_clk; + wire delay_val_ne_clk; + wire delay1_reached; + reg delay1_reached_1 = 0; + reg delay1_reached_2 = 0; + wire delay1_working; + reg delay1_working_1 = 0; + reg delay1_working_2 = 0; + reg delay1_ignore = 0; + reg [7:0] delay_val_pe_2 = 0; + reg [7:0] delay_val_ne_2 = 0; + reg [7:0] odelay_val_pe_reg = 0; + reg [7:0] odelay_val_ne_reg = 0; + wire delay2_reached; + reg delay2_reached_1 = 0; + reg delay2_reached_2 = 0; + wire delay2_working; + reg delay2_working_1 = 0; + reg delay2_working_2 = 0; + reg delay2_ignore = 0; + reg delay1_in = 0; + reg delay2_in = 0; + reg calibrate = 0; + reg calibrate_done = 0; + reg sync_to_data_reg = 1; + reg pci_ce_reg = 0; + + reg [7:0] data_reg = 8'h00; + reg [7:0] addr_reg = 8'h80; + reg mem_updated = 1'b1; + reg [7:0] shift_out = 8'h00; + reg [7:0] mask = 8'h00; + reg [7:0] mc_iob [0:8]; + reg [7:0] mc_iob_mask [0:8]; + reg [2:0] if_state = IDLE; + reg cal_reg = 0; + reg snapback_reg = 0; + reg half_reg = 0; + reg inc_reg = 0; + reg ce_reg = 0; + reg rst_reg = 0; + reg direct_in_reg = 0; + reg [1:0] event_sel_m_reg = 2'b0; + reg plus1_s_reg = 1'b0; + reg [3:0] lumped_delay_select_reg = 4'h0; + reg lumped_delay_reg = 0; + +//----------------------------------------------------------------------------- +//----------------- tasks / function ------------------------------------- +//----------------------------------------------------------------------------- +task inc_dec; +begin + if (GSR_INDELAY) begin + idelay_val_pe_m_reg <= IDELAY_VALUE_BINARY; + idelay_val_pe_s_reg <= IDELAY_VALUE_BINARY; + if (pci_ce_reg == 1) begin // PCI + idelay_val_ne_m_reg <= IDELAY2_VALUE_BINARY; + idelay_val_ne_s_reg <= IDELAY2_VALUE_BINARY; + end + else begin + idelay_val_ne_m_reg <= IDELAY_VALUE_BINARY; + idelay_val_ne_s_reg <= IDELAY_VALUE_BINARY; + end + end + else if (rst_sig) begin + if (rst_to_half_reg == 1'b1) begin + // rst to half + if (SERDES_MODE_BINARY == SLAVE) begin + if ((ignore_rst == 1'b0) && (IDELAY_TYPE_BINARY != DIFF_PHASE_DETECTOR)) begin + // all non diff phase detector slave rst + idelay_val_pe_s_reg <= half_max; + idelay_val_ne_s_reg <= half_max; + end + else if (ignore_rst == 1'b0) begin + // slave phase detector first rst + idelay_val_pe_m_reg <= half_max; + idelay_val_ne_m_reg <= half_max; + idelay_val_pe_s_reg <= half_max << 1; + idelay_val_ne_s_reg <= half_max << 1; + ignore_rst <= 1'b1; + end + else begin + // slave phase det second or more rst + if ((idelay_val_pe_m_reg + half_max) > max_delay) begin + idelay_val_pe_s_reg <= idelay_val_pe_m_reg + half_max - max_delay - 1; + idelay_val_ne_s_reg <= idelay_val_ne_m_reg + half_max - max_delay - 1; + end + else begin + idelay_val_pe_s_reg <= idelay_val_pe_m_reg + half_max; + idelay_val_ne_s_reg <= idelay_val_ne_m_reg + half_max; + end + end + end + else if ((ignore_rst == 1'b0) || (IDELAY_TYPE_BINARY != DIFF_PHASE_DETECTOR)) begin + // master or none, first diff phase rst or all others + idelay_val_pe_m_reg <= half_max; + idelay_val_ne_m_reg <= half_max; + ignore_rst <= 1'b1; + end + end + else begin + // rst to 0 + idelay_val_pe_m_reg <= 0; + idelay_val_ne_m_reg <= 0; + idelay_val_pe_s_reg <= 0; + idelay_val_ne_s_reg <= 0; + end + end + else if ( ~busy_out_int && ce_sig && ~rst_sig && + ((IDELAY_TYPE_BINARY == VAR) || + (IDELAY_TYPE_BINARY == DIFF_PHASE_DETECTOR)) ) begin //variable + if (inc_sig) begin // inc + // MASTER or NONE + // (lt max_delay inc m) + if (idelay_val_pe_m_reg < max_delay) begin + idelay_val_pe_m_reg <= idelay_val_pe_m_reg + 1; + end + // wrap to 0 wrap (gte max_delay and wrap to 0) + else if (sat_at_max_reg == WRAPAROUND) begin + idelay_val_pe_m_reg <= 8'h00; + end + // stay at max (gte max_delay and stay at max) + else begin + idelay_val_pe_m_reg <= max_delay; + end + // SLAVE + // (lt max_delay inc s) + if (idelay_val_pe_s_reg < max_delay) begin + idelay_val_pe_s_reg <= idelay_val_pe_s_reg + 1; + end + // wrap to 0 wrap (gte max_delay and wrap to 0) + else if (sat_at_max_reg == WRAPAROUND) begin + idelay_val_pe_s_reg <= 8'h00; + end + // stay at max (gte max_delay and stay at max) + else begin + idelay_val_pe_s_reg <= max_delay; + end + // MASTER or NONE + // (lt max_delay inc) + if (idelay_val_ne_m_reg < max_delay) begin + idelay_val_ne_m_reg <= idelay_val_ne_m_reg + 1; + end + // wrap to 0 wrap (gte max_delay and wrap to 0) + else if (sat_at_max_reg == WRAPAROUND) begin + idelay_val_ne_m_reg <= 8'h00; + end + // stay at max (gte max_delay and stay at max) + else begin + idelay_val_ne_m_reg <= max_delay; + end + // SLAVE + // (lt max_delay inc) + if (idelay_val_ne_s_reg < max_delay) begin + idelay_val_ne_s_reg <= idelay_val_ne_s_reg + 1; + end + // wrap to 0 wrap (gte max_delay and wrap to 0) + else if (sat_at_max_reg == WRAPAROUND) begin + idelay_val_ne_s_reg <= 8'h00; + end + // stay at max (gte max_delay and stay at max) + else begin + idelay_val_ne_s_reg <= max_delay; + end + end + else begin // dec + // MASTER or NONE + // (between 0 and max_delay dec) + if ((idelay_val_pe_m_reg > 8'h00) && + (idelay_val_pe_m_reg <= max_delay)) begin + idelay_val_pe_m_reg <= idelay_val_pe_m_reg - 1; + end + // stay at max (0) (eq 0 and stay at max/min) + else if ((sat_at_max_reg == STAY_AT_LIMIT) && (idelay_val_pe_m_reg == 0)) begin + idelay_val_pe_m_reg <= 8'h00; + end + // wrap to 0 wrap (gte max_delay or (eq 0 and wrap to max)) + else begin + idelay_val_pe_m_reg <= max_delay; + end + // SLAVE + // (between 0 and max_delay dec) + if ((idelay_val_pe_s_reg > 8'h00) && + (idelay_val_pe_s_reg <= max_delay)) begin + idelay_val_pe_s_reg <= idelay_val_pe_s_reg - 1; + end + // stay at max (0) (eq 0 and stay at max/min) + else if ((sat_at_max_reg == STAY_AT_LIMIT) && (idelay_val_pe_s_reg == 0)) begin + idelay_val_pe_s_reg <= 8'h00; + end + // wrap to 0 wrap (gte max_delay or (eq 0 and wrap to max)) + else begin + idelay_val_pe_s_reg <= max_delay; + end + // MASTER or NONE + // (between 0 and max_delay dec) + if ((idelay_val_ne_m_reg > 8'h00) && + (idelay_val_ne_m_reg <= max_delay)) begin + idelay_val_ne_m_reg <= idelay_val_ne_m_reg - 1; + end + // stay at max (0) (eq 0 and stay at max/min) + else if ((sat_at_max_reg == STAY_AT_LIMIT) && (idelay_val_ne_m_reg == 0)) begin + idelay_val_ne_m_reg <= 8'h00; + end + // wrap to 0 wrap (gte max_delay or (eq 0 and wrap to max)) + else begin + idelay_val_ne_m_reg <= max_delay; + end + // SLAVE + // (between 0 and max_delay dec) + if ((idelay_val_ne_s_reg > 8'h00) && + (idelay_val_ne_s_reg <= max_delay)) begin + idelay_val_ne_s_reg <= idelay_val_ne_s_reg - 1; + end + // stay at max (0) (eq 0 and stay at max/min) + else if ((sat_at_max_reg == STAY_AT_LIMIT) && (idelay_val_ne_s_reg == 0)) begin + idelay_val_ne_s_reg <= 8'h00; + end + // wrap to 0 wrap (gte max_delay or (eq 0 and wrap to max)) + else begin + idelay_val_ne_s_reg <= max_delay; + end + end + end + end +endtask +task write_to_ioi; +begin + case (addr_reg[6:0]) + 7'h01: begin + {cal_reg, snapback_reg, half_reg, inc_reg, ce_reg, rst_reg} <= data_reg[5:0]; + shift_out <= 8'h0; + end + 7'h02: begin + idelay_val_pe_m_reg <= data_reg; + idelay_val_pe_s_reg <= data_reg; + shift_out <= data_reg; + end + 7'h03: begin + idelay_val_ne_m_reg <= data_reg; + idelay_val_ne_s_reg <= data_reg; + shift_out <= data_reg; + end + 7'h04: begin + odelay_val_pe_reg <= data_reg; + shift_out <= data_reg; + end + 7'h05: begin + odelay_val_ne_reg <= data_reg; + shift_out <= data_reg; + end + 7'h06: begin + if (SERDES_MODE_BINARY == SLAVE) begin + {direct_in_reg, force_rx_reg, force_dly_dir_reg} <= data_reg[4:2]; + plus1_s_reg <= data_reg[0]; + shift_out <= {3'b0, data_reg[4:2], 1'b0, data_reg[0]}; + end + else begin + {direct_in_reg, force_rx_reg, force_dly_dir_reg, event_sel_m_reg} <= data_reg[4:0]; + shift_out <= {3'b0, data_reg[4:0]}; + end + end + 7'h07: begin + {lumped_delay_select_reg, lumped_delay_reg, sync_to_data_reg, sat_at_max_reg, rst_to_half_reg} <= data_reg; + shift_out <= data_reg; + end + 7'h08: begin + max_delay <= data_reg; + half_max <= data_reg >> 1; + shift_out <= data_reg; + end + default: ; + endcase + end +endtask + +task read_from_ioi; +begin + case (addr_reg[6:0]) + 7'h00: shift_out <= 8'h0; + 7'h01: shift_out <= 8'h0; // w/o {2'b0, cal_reg, snapback_reg, half_reg, inc_reg, ce_reg, rst_reg}; + 7'h02: begin + if (SERDES_MODE_BINARY == SLAVE) + shift_out <= idelay_val_pe_s_reg; + else + shift_out <= idelay_val_pe_m_reg; + end + 7'h03: begin + if (SERDES_MODE_BINARY == SLAVE) + shift_out <= idelay_val_ne_s_reg; + else + shift_out <= idelay_val_ne_m_reg; + end + 7'h04: shift_out <= odelay_val_pe_reg; + 7'h05: shift_out <= odelay_val_ne_reg; + 7'h06: begin + if (SERDES_MODE_BINARY == MASTER) + shift_out <= {3'b0, direct_in_reg, force_rx_reg, force_dly_dir_reg, event_sel_m_reg}; + else + shift_out <= {3'b0, direct_in_reg, force_rx_reg, force_dly_dir_reg, 1'b0, plus1_s_reg}; + end + 7'h07: shift_out <= {lumped_delay_select_reg, lumped_delay_reg, sync_to_data_reg, sat_at_max_reg, rst_to_half_reg}; + 7'h08: shift_out <= max_delay; + default: shift_out <= 8'h0; + endcase + end +endtask + + assign rst_sig = rst_reg; + assign cal_sig = cal_reg; + assign inc_sig = inc_reg; + assign ce_sig = ce_reg; + assign snapback_sig = snapback_reg; + assign half_sig = half_reg; + assign output_delay_off = force_dly_dir_reg && force_rx_reg; + assign input_delay_off = force_dly_dir_reg && ~force_rx_reg; + assign idelay_val_pe_reg = (SERDES_MODE_BINARY == SLAVE) ? idelay_val_pe_s_reg : idelay_val_pe_m_reg; + assign idelay_val_ne_reg = (SERDES_MODE_BINARY == SLAVE) ? idelay_val_ne_s_reg : idelay_val_ne_m_reg; + assign delay1_reached = delay1_reached_1 || delay1_reached_2; + assign delay2_reached = delay2_reached_1 || delay2_reached_2; + assign delay1_working = delay1_working_1 || delay1_working_2; + assign delay2_working = delay2_working_1 || delay2_working_2; + + initial begin +//----------------------------------------------------------------------------- +//----------------- DATA_RATE Check ------------------------------------------ +//----------------------------------------------------------------------------- + if (DATA_RATE == "SDR") DATA_RATE_BINARY <= SDR; + else if (DATA_RATE == "DDR") DATA_RATE_BINARY <= DDR; + else begin + #1; + $display("Attribute Syntax Error : The attribute DATA_RATE on %s instance %m is set to %s. Legal values for this attribute are SDR or DDR\n", MODULE_NAME, DATA_RATE); + data_rate_err_flag = 1; + end + +//----------------------------------------------------------------------------- +//----------------- SIM_TAPDELAY_VALUE Check ---------------------------------- +//----------------------------------------------------------------------------- + if ((SIM_TAPDELAY_VALUE >= 10) && (SIM_TAPDELAY_VALUE <= 90)) begin + SIM_TAPDELAY_VALUE_BINARY = SIM_TAPDELAY_VALUE; + end + else begin + #1; + $display("Attribute Syntax Error : The Attribute SIM_TAPDELAY_VALUE on %s instance %m is set to %d. Legal values for this attribute are between 10 and 90 ps inclusive.\n", MODULE_NAME, SIM_TAPDELAY_VALUE); + sim_tap_delay_err_flag = 1; + end + + if (sim_tap_delay_err_flag) begin + attr_err_flag = 1; + #1; + $display("Attribute Errors detected in %s instance %m: Simulation cannot continue. Exiting. \n", MODULE_NAME); + $finish; + end + + end //initial begin parameter check + +//----------------------------------------------------------------------------- +//-------------------- Input / Output ----------------------------------------- +//----------------------------------------------------------------------------- + assign #(out_delay) DATAOUT_OUTDELAY = DATAOUT_OUT; + assign #(out_delay) DATAOUT2_OUTDELAY = DATAOUT2_OUT; + assign #(out_delay) DOUT_OUTDELAY = DOUT_OUT; + assign #(out_delay) SDO_OUTDELAY = SDO_OUT; + assign #(out_delay) TOUT_OUTDELAY = TOUT_OUT; + + assign #(in_delay) ADD_INDELAY = ADD_IN; + assign #(in_delay) BKST_INDELAY = BKST_IN; + assign #(clk_delay) CLK_INDELAY = CLK_IN; + assign #(in_delay) CS_INDELAY = CS_IN; + assign #(in_delay) IDATAIN_INDELAY = IDATAIN_IN; + assign #(clk_delay) IOCLK0_INDELAY = IOCLK0_IN; + assign #(clk_delay) IOCLK1_INDELAY = IOCLK1_IN; + assign MEMUPDATE_INDELAY = 1'b1; + assign #(in_delay) ODATAIN_INDELAY = ODATAIN_IN; + assign #(in_delay) SDI_INDELAY = SDI_IN; + assign #(in_delay) T_INDELAY = T_IN; + assign #(in_delay) GSR_INDELAY = GSR_IN; + +//----------------------------------------------------------------------------- +//----------------- I/O Assignments / Mux ------------------------------------- +//----------------------------------------------------------------------------- + // input delay paths + assign DATAOUT_OUT = delay1_out_sig; + assign DATAOUT2_OUT = (pci_ce_reg == 0) ? delay1_out_sig : delay2_out; + assign TOUT_OUT = (~output_delay_off && (~T_INDELAY || input_delay_off)) ? + tout_out_int : T_INDELAY; + + assign delay1_out_sig = ((IDELAY_TYPE_BINARY == DIFF_PHASE_DETECTOR) && + (SERDES_MODE_BINARY == SLAVE) && + (delay_val_pe_1 < half_max) ) ? + delay1_out_dly : delay1_out; +// output delay paths + assign #(SIM_TAPDELAY_VALUE) DOUT_OUT = (~output_delay_off && (~T_INDELAY || input_delay_off)) ? delay1_in : 1'b0; + assign cs_sig = CS_INDELAY; + assign SDO_OUT = cs_sig ? shift_out[0] : 1'b0 ; + + initial begin + first_edge <= #150 1; + wait (GSR_INDELAY === 1'b0); + mc_iob_mask [0] = 8'h3f; + mc_iob_mask [1] = 8'hbf; + mc_iob_mask [2] = 8'h7f; + mc_iob_mask [3] = 8'hff; + mc_iob_mask [4] = 8'hff; + mc_iob_mask [5] = 8'hff; + mc_iob_mask [6] = 8'hff; + mc_iob_mask [7] = 8'hff; + mc_iob_mask [8] = 8'h7f; + mc_iob [0] = 8'h00; + mc_iob [1] = 8'h00; + mc_iob [2] = 8'h00; + mc_iob [3] = 8'h00; + mc_iob [4] = 8'h00; + mc_iob [5] = 8'h00; + mc_iob [6] = 8'h00; + mc_iob [7] = 8'h00; + mc_iob [8] = 8'h00; + end //initial begin other initializations + +//----------------------------------------------------------------------------- +//----------------- GLOBAL hidden GSR pin ------------------------------------- +//----------------------------------------------------------------------------- + + +//----------------------------------------------------------------------------- +//----------------- DDR Doubler ----------------------------------------- +//----------------------------------------------------------------------------- + always @(posedge IOCLK0_INDELAY) begin + if (first_edge == 1) begin + ioclk0_int <= 1; + ioclk0_int <= #100 0; + end + end + + generate if(DATA_RATE == "DDR") + always @(posedge IOCLK1_INDELAY) begin + if (first_edge== 1) begin + ioclk1_int <= 1; + ioclk1_int <= #100 0; + end + end + endgenerate + + assign ioclk_int = ioclk0_int | ioclk1_int; + +//----------------------------------------------------------------------------- +//----------------- Delay Line Inputs ----------------------------------------- +//----------------------------------------------------------------------------- + always @(posedge ioclk_int) begin + delay1_out_dly <= delay1_out; + end + +// delay line 1 input + always @(IDATAIN_INDELAY or DATAOUT_OUT or T_INDELAY or ODATAIN_INDELAY or GSR_INDELAY) begin + if ((T_INDELAY || output_delay_off) && ~input_delay_off) begin // input delay + if (pci_ce_reg == 0 ) delay1_in <= IDATAIN_INDELAY; // NORMAL + else delay1_in <= IDATAIN_INDELAY ^ DATAOUT_OUT; // PCI + end + else begin // output delay + if (output_delay_off) delay1_in <= 0; + else delay1_in <= ODATAIN_INDELAY; + end + end + +// delay line 2 input + always @(IDATAIN_INDELAY or DATAOUT2_OUT or T_INDELAY or ODATAIN_INDELAY or GSR_INDELAY) begin + if ((T_INDELAY || output_delay_off) && ~input_delay_off) begin // input delay + if (pci_ce_reg == 0 ) delay2_in <= ~IDATAIN_INDELAY; // NORMAL + else delay2_in <= IDATAIN_INDELAY ^ DATAOUT2_OUT; // PCI + end + else begin // output delay + if (output_delay_off) delay2_in <= 0; + else delay2_in <= ~ODATAIN_INDELAY; + end + end + +//----------------------------------------------------------------------------- +//----------------- Delay Lines ----------------------------------------------- +//----------------------------------------------------------------------------- + always @(delay1_in or GSR_INDELAY) begin + if (GSR_INDELAY) begin + delay1_reached_1 <= 1'b0; + delay1_reached_2 <= 1'b0; + delay1_working_1 <= 1'b0; + delay1_working_2 <= 1'b0; + delay1_ignore <= delay1_in; + end + else if (delay1_in) begin + if (~delay1_working || delay1_reached) begin + if (delay1_working_1 == 1'b0) delay1_working_1 <= 1'b1; + else delay1_working_2 <= 1'b1; + if ((T_INDELAY || output_delay_off) && ~input_delay_off) begin // input delay + if (IDATAIN_INDELAY) begin // positive edge + if (delay1_reached_1 == 1'b0) + delay1_reached_1 <= #(SIM_TAPDELAY_VALUE*delay_val_pe_1) 1'b1; + else + delay1_reached_2 <= #(SIM_TAPDELAY_VALUE*delay_val_pe_1) 1'b1; + end + else begin // negative edge + if (delay1_reached_1 == 1'b0) + delay1_reached_1 <= #(SIM_TAPDELAY_VALUE*delay_val_ne_1) 1'b1; + else + delay1_reached_2 <= #(SIM_TAPDELAY_VALUE*delay_val_ne_1) 1'b1; + end + end + else begin // output delay + if (ODATAIN_INDELAY) begin // positive edge + if (delay1_reached_1 == 1'b0) + delay1_reached_1 <= #(SIM_TAPDELAY_VALUE*delay_val_pe_1) 1'b1; + else + delay1_reached_2 <= #(SIM_TAPDELAY_VALUE*delay_val_pe_1) 1'b1; + end + else begin // negative edge + if (delay1_reached_1 == 1'b0) + delay1_reached_1 <= #(SIM_TAPDELAY_VALUE*delay_val_ne_1) 1'b1; + else + delay1_reached_2 <= #(SIM_TAPDELAY_VALUE*delay_val_ne_1) 1'b1; + end + end + end + else begin + delay1_ignore <= 1'b1; + end + end + end + + always @(delay2_in or GSR_INDELAY) begin + if (GSR_INDELAY) begin + delay2_reached_1 <= 1'b0; + delay2_reached_2 <= 1'b0; + delay2_working_1 <= 1'b0; + delay2_working_2 <= 1'b0; + delay2_ignore <= delay2_in; + end + else if (delay2_in) begin + if (~delay2_working || delay2_reached) begin + if (delay2_working_1 == 1'b0) delay2_working_1 <= 1'b1; + else delay2_working_2 <= 1'b1; + if ((T_INDELAY || output_delay_off) && ~input_delay_off) begin // input delay + if (IDATAIN_INDELAY) begin // positive edge + if (delay2_reached_1 == 1'b0) + delay2_reached_1 <= #(SIM_TAPDELAY_VALUE*delay_val_pe_2) 1'b1; + else + delay2_reached_2 <= #(SIM_TAPDELAY_VALUE*delay_val_pe_2) 1'b1; + end + else begin // negative edge + if (delay2_reached_1 == 1'b0) + delay2_reached_1 <= #(SIM_TAPDELAY_VALUE*delay_val_ne_2) 1'b1; + else + delay2_reached_2 <= #(SIM_TAPDELAY_VALUE*delay_val_ne_2) 1'b1; + end + end + else begin // output delay + if (ODATAIN_INDELAY) begin // positive edge + if (delay2_reached_1 == 1'b0) + delay2_reached_1 <= #(SIM_TAPDELAY_VALUE*delay_val_pe_2) 1'b1; + else + delay2_reached_2 <= #(SIM_TAPDELAY_VALUE*delay_val_pe_2) 1'b1; + end + else begin // negative edge + if (delay2_reached_1 == 1'b0) + delay2_reached_1 <= #(SIM_TAPDELAY_VALUE*delay_val_ne_2) 1'b1; + else + delay2_reached_2 <= #(SIM_TAPDELAY_VALUE*delay_val_ne_2) 1'b1; + end + end + end + else begin + delay2_ignore <= 1'b1; + end + end + end + + always @(posedge delay1_reached) begin + delay1_ignore <= #1 1'b0; + end + + always @(posedge delay1_reached_1) begin + delay1_working_1 <= #1 1'b0; + delay1_reached_1 <= #1 1'b0; + end + + always @(posedge delay1_reached_2) begin + delay1_working_2 <= #1 1'b0; + delay1_reached_2 <= #1 1'b0; + end + + always @(posedge delay2_reached) begin + delay2_ignore <= #1 1'b0; + end + + always @(posedge delay2_reached_1) begin + delay2_working_1 <= #1 1'b0; + delay2_reached_1 <= #1 1'b0; + end + + always @(posedge delay2_reached_2) begin + delay2_working_2 <= #1 1'b0; + delay2_reached_2 <= #1 1'b0; + end + +//----------------------------------------------------------------------------- +//----------------- Output FF ------------------------------------------------- +//----------------------------------------------------------------------------- + always @(posedge delay1_reached or posedge delay2_reached or delay1_working or delay2_working or posedge delay1_ignore or posedge delay2_ignore or T_INDELAY or GSR_INDELAY) begin + if ((pci_ce_reg == 0) || (~T_INDELAY && ~output_delay_off) || + input_delay_off) begin //NORMAL in or output + if (GSR_INDELAY || ~first_edge || (~delay1_working && ~delay2_working)) begin + delay1_out <= delay1_in; + end + else if ( (delay1_reached && ~delay1_ignore) || + (delay1_ignore && ~delay1_out) ) begin + delay1_out <= 1'b1; + end + else if ( (delay2_reached && ~delay2_ignore) || + (delay2_ignore && delay1_out) ) begin + delay1_out <= 1'b0; + end + delay2_out <= 1'b0; + end + else begin // PCI in + if (GSR_INDELAY || delay1_reached) begin + delay1_out <= IDATAIN_INDELAY; + end + if (GSR_INDELAY || delay2_reached) begin + delay2_out <= IDATAIN_INDELAY; + end + end + end +//----------------------------------------------------------------------------- +//----------------- TOUT delay ------------------------------------------------ +//----------------------------------------------------------------------------- + always @(T_INDELAY) begin + #(SIM_TAPDELAY_VALUE); + tout_out_int <= T_INDELAY; + end + +//----------------------------------------------------------------------------- +//----------------- Delay Preset Values --------------------------------------- +//----------------------------------------------------------------------------- + assign delay_val_pe_clk = sync_to_data_reg ? delay1_in : ioclk_int; + assign delay_val_ne_clk = sync_to_data_reg ? delay2_in : ioclk_int; + + always @(posedge delay_val_pe_clk or posedge rst_sig or posedge busy_out_int) begin + if ((rst_sig == 1'b1) || (busy_out_int == 1'b1)) begin + busy_out_dly <= 1'b1; + busy_out_dly1 <= 1'b1; + end + else begin + busy_out_dly <= busy_out_dly1; + busy_out_dly1 <= busy_out_int; + end + end + + + always @(posedge delay_val_pe_clk or rst_sig) begin + if ((~T_INDELAY && ~output_delay_off) || input_delay_off) begin // output + delay_val_pe_1 <= odelay_val_pe_reg; + delay_val_pe_2 <= odelay_val_pe_reg; + end + // input delays + else if (IDELAY_TYPE_BINARY == DEFAULT) begin + delay_val_pe_1 <= default_value; + delay_val_pe_2 <= default_value; + end + else if (IDELAY_TYPE_BINARY == FIXED) begin + if (pci_ce_reg == 1) begin // PCI + delay_val_pe_1 <= IDELAY_VALUE_BINARY[7:0]; + delay_val_pe_2 <= IDELAY2_VALUE_BINARY[7:0]; + end + else begin // normal + delay_val_pe_1 <= IDELAY_VALUE_BINARY[7:0]; + delay_val_pe_2 <= IDELAY_VALUE_BINARY[7:0]; + end + end + else if (IDELAY_TYPE_BINARY == VAR) begin + if (pci_ce_reg == 1) begin // PCI + delay_val_pe_1 <= idelay_val_pe_reg; + delay_val_pe_2 <= idelay_val_ne_reg; + end + else begin // normal + delay_val_pe_1 <= idelay_val_pe_reg; + delay_val_pe_2 <= idelay_val_ne_reg; + end + end + else if (IDELAY_TYPE_BINARY == DIFF_PHASE_DETECTOR) begin + delay_val_pe_1 <= idelay_val_pe_reg; + delay_val_pe_2 <= idelay_val_ne_reg; + end + else begin // default + delay_val_pe_1 <= default_value; + delay_val_pe_2 <= default_value; + end + end + + always @(posedge delay_val_ne_clk or rst_sig) begin + if ((~T_INDELAY && ~output_delay_off) || input_delay_off) begin // output + delay_val_ne_1 <= odelay_val_ne_reg; + delay_val_ne_2 <= odelay_val_ne_reg; + end + //input delays + else if (IDELAY_TYPE_BINARY == DEFAULT) begin + delay_val_ne_1 <= default_value; + delay_val_ne_2 <= default_value; + end + else if (IDELAY_TYPE_BINARY == FIXED) begin + if (pci_ce_reg == 1) begin // PCI + delay_val_ne_1 <= IDELAY_VALUE_BINARY[7:0]; + delay_val_ne_2 <= IDELAY2_VALUE_BINARY[7:0]; + end + else begin // normal + delay_val_ne_1 <= IDELAY_VALUE_BINARY[7:0]; + delay_val_ne_2 <= IDELAY_VALUE_BINARY[7:0]; + end + end + else if (IDELAY_TYPE_BINARY == VAR) begin + if (pci_ce_reg == 1) begin // PCI + delay_val_ne_1 <= idelay_val_pe_reg; + delay_val_ne_2 <= idelay_val_ne_reg; + end + else begin // normal + delay_val_ne_1 <= idelay_val_pe_reg; + delay_val_ne_2 <= idelay_val_ne_reg; + end + end + else if (IDELAY_TYPE_BINARY == DIFF_PHASE_DETECTOR) begin + delay_val_ne_1 <= idelay_val_pe_reg; + delay_val_ne_2 <= idelay_val_ne_reg; + end + else begin // default + delay_val_ne_1 <= default_value; + delay_val_ne_2 <= default_value; + end + end + +//----------------------------------------------------------------------------- +//----------------- Max Count CAL --------------------------------------------- +//----------------------------------------------------------------------------- + + always @(posedge CLK_INDELAY or posedge GSR_INDELAY) begin + if (GSR_INDELAY) begin + cal_count <= 5'b10010; + busy_out_int <= 1'b1; // reset + end + else if (cal_sig && ~busy_out_int) begin + cal_count <= 5'b00000; + busy_out_int <= 1'b1; // begin cal + end + else if (ce_sig && ~busy_out_int) begin + cal_count <= 5'b10010; + busy_out_int <= 1'b1; // inc (busy high 2 clocks) + end + else if (busy_out_int && (cal_count < 5'b10011) ) begin + cal_count <= cal_count + 1; + busy_out_int <= 1'b1; // continue + end + else begin + busy_out_int <= 1'b0; // done + end + end + + always @(posedge ioclk_int) begin + if (~calibrate & ~calibrate_done && busy_out_int && (cal_count == 5'b01000) ) + calibrate <= 1'b1; + else + calibrate <= 1'b0; + end + + always @(cal_delay or calibrate or GSR_INDELAY or cal_sig or busy_out_int) begin + if ((GSR_INDELAY) || (cal_sig && ~busy_out_int)) begin + cal_delay <= 8'h00; + calibrate_done <= 1'b0; + end + else if (calibrate && (cal_delay !== 8'hff)) begin + #(SIM_TAPDELAY_VALUE); + if (calibrate) begin + cal_delay <= cal_delay + 1; + end + else begin + if ((pci_ce_reg == 1) && (DATA_RATE_BINARY == SDR)) begin + cal_delay <= cal_delay >> 1; + end + calibrate_done <= 1'b1; + end + end + else if (calibrate && (cal_delay == 8'hff)) begin + calibrate_done <= 1'b1; + end + else begin + #(SIM_TAPDELAY_VALUE); + calibrate_done <= 1'b0; + end + end + +//----------------------------------------------------------------------------- +//----------------- Interface State Machine------------------------------------ +//----------------------------------------------------------------------------- + always @(posedge CLK_INDELAY) begin + if (GSR_INDELAY || rst_sig) begin + if_state <= IDLE; + shift_out <= 8'h00; + addr_reg <= 8'h80; + data_reg <= 8'h00; + mem_updated <= 1'b1; + cal_reg <= 0; + snapback_reg <= 0; + half_reg <= 0; + inc_reg <= 0; + ce_reg <= 0; + rst_reg <= 0; + end + else begin + if (cal_reg == 1) cal_reg <= 0; + if (snapback_reg == 1) snapback_reg <= 0; + if (half_reg == 1) half_reg <= 0; + if (inc_reg == 1) inc_reg <= 0; + if (ce_reg == 1) ce_reg <= 0; + case (if_state) + IDLE: begin + if (cs_sig && ADD_INDELAY) begin + if_state <= ADDR_ACTIVE; + addr_reg <= {SDI_INDELAY, addr_reg[7:1]}; + shift_out <= {1'b0, shift_out[7:1]}; + end + else if (cs_sig && ~ADD_INDELAY ) begin + if_state <= DATA_ACTIVE; + data_reg <= {SDI_INDELAY, data_reg[7:1]}; + shift_out <= {1'b0, shift_out[7:1]}; + end + else begin + if_state <= IDLE; + if (~addr_reg[7]) read_from_ioi; + else shift_out <= mc_iob[addr_reg[3:0]]; + end + end + ADDR_ACTIVE: begin + if (cs_sig && ADD_INDELAY) begin + if_state <= ADDR_ACTIVE; + addr_reg <= {SDI_INDELAY, addr_reg[7:1]}; + shift_out <= {1'b0, shift_out[7:1]}; + end + else if (~cs_sig && ~ADD_INDELAY) begin + if_state <= IDLE; + if (~addr_reg[7]) read_from_ioi; + else shift_out <= mc_iob[addr_reg[3:0]]; + end + else begin + if_state <= IDLE; + $display("Illegal interface state transition on %s instance %m at time %t: ADDR_ACTIVE state - ADD [%d] and CS [%d] must both be low for one clk to advance.\n", MODULE_NAME, $time, ADD_INDELAY, cs_sig); + end + end + DATA_ACTIVE: begin + if (cs_sig && ~ADD_INDELAY) begin + if_state <= DATA_ACTIVE; + data_reg <= {SDI_INDELAY, data_reg[7:1]}; + shift_out <= {1'b0, shift_out[7:1]}; + end + else if (~cs_sig && ~ADD_INDELAY ) begin + if_state <= IDLE; + if (addr_reg[7] == 1'b0) begin + if (MEMUPDATE_INDELAY == 1'b1) write_to_ioi; + else mem_updated <= 1'b0; + end + else begin + if (MEMUPDATE_INDELAY == 1'b1) begin + mc_iob[addr_reg[3:0]] <= data_reg & mc_iob_mask[addr_reg[3:0]]; + shift_out <= data_reg & mc_iob_mask[addr_reg[3:0]]; + end + else begin + mem_updated <= 1'b0; + end + end + end + else begin + if_state <= IDLE; + $display("Illegal interface state transition on %s instance %m at time %t: DATA_ACTIVE state - ADD [%d] must stay low\n", MODULE_NAME, $time, ADD_INDELAY); + end + end + default: begin + if_state <= IDLE; + $display("Illegal state entered on %s instance %m at time %t: state %3b\n", MODULE_NAME, $time, if_state); + end + endcase + end + + if ((mem_updated == 1'b0) && (MEMUPDATE_INDELAY == 1'b1)) begin + if (addr_reg[7] == 1'b0) begin + write_to_ioi; + mem_updated <= 1'b1; + end + else begin + mc_iob[addr_reg[3:0]] <= data_reg & mc_iob_mask[addr_reg[3:0]]; + mem_updated <= 1'b1; + end + end + + inc_dec; + + if (calibrate_done) begin + max_delay <= cal_delay; + half_max <= cal_delay >> 1; + end + + end + + assign DATAOUT = DATAOUT_OUTDELAY; + assign DATAOUT2 = DATAOUT2_OUTDELAY; + assign DOUT = DOUT_OUTDELAY; + assign SDO = SDO_OUTDELAY; + assign TOUT = TOUT_OUTDELAY; + + assign ADD_IN = ADD; + assign BKST_IN = BKST; + assign CLK_IN = CLK; + assign CS_IN = CS; + assign IDATAIN_IN = IDATAIN; + assign IOCLK0_IN = IOCLK0; + assign IOCLK1_IN = IOCLK1; + assign ODATAIN_IN = ODATAIN; + assign SDI_IN = SDI; + assign T_IN = T; + assign GSR_IN = GSR; + specify + ( CLK => SDO) = (0, 0); + ( IDATAIN => DATAOUT) = (0, 0); + ( IDATAIN => DATAOUT2) = (0, 0); + ( ODATAIN => DOUT) = (0, 0); + ( T => TOUT) = (0, 0); + + specparam PATHPULSE$ = 0; + endspecify +endmodule // IODRP2 diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IODRP2_MCB.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IODRP2_MCB.v new file mode 100644 index 0000000..a3ea141 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/IODRP2_MCB.v @@ -0,0 +1,1251 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/stan/IODRP2_MCB.v,v 1.14 2009/11/05 16:59:56 robh Exp $ +/////////////////////////////////////////////////////// +// Copyright (c) 2008 Xilinx Inc. +// All Right Reserved. +/////////////////////////////////////////////////////// +// +// ____ ___ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / IODELAY2 Dynamic Reconfiguration Port for MCB +// /__/ /\ Filename : IODRP2_MCB.v +// \ \ / \ +// \__\/\__ \ +// +// Revision: Date: Comment +// 1.0: 09/30/08: Initial version. From IODELAY2/IODRP2 +// 1.1 11/05/2008 I/O, structure change +// Correct BKST functionality +// 1.2 11/19/2008 Change SIM_TAP_DELAY to SIM_TAPDELAY_VALUE +// 1.3 11/21/2008 Change AUX_SDO_OUTDELAY to AUXSDO_OUTDELAY +// 1.4 01/29/2009 IR504942, 504805, 504692 sync to data +// IR506027 DQSOUT's +// 1.5 02/04/2009 CR506027 IODRP state machine, sync_to_data off +// 02/04/2009 CR502236 lumped delay reg +// 1.6 02/12/2009 CR1016 update DOUT to match HW +// 1.7 03/05/2009 CR511015 VHDL - VER sync +// CR511054 Output at time 0 fix +// 1.8 : 04/09/2009 CR480001 fix calibration. +// 1.9 : 04/22/2009 CR518721 ODELAY value fix at time 0 +// 1.10: 05/08/2009 CR521007 missing assign SDO_OUT to SDO +// 1.11: 05/19/2009 CR522171 Missing else in if-else-else. delay values +// 1.12: 07/23/2009 CR527208 Race condition in cal sig +// 1.13: 08/07/2009 CR511054 Time 0 output initialization +// CR529368 Input bypass ouput when delay line idle +// 1.14: 09/01/2009 CR531995 remove pci_ce_reg, byp_ts_ff_reg, byp_op_ff_reg from addr6 +// 1.15: 11/04/2009 CR538116 fix calibrate_done when cal_delay saturates +// End Revision +/////////////////////////////////////////////////////// + +`timescale 1 ps / 1 ps + +module IODRP2_MCB ( + AUXSDO, + DATAOUT, + DATAOUT2, + DOUT, + DQSOUTN, + DQSOUTP, + SDO, + TOUT, + ADD, + AUXADDR, + AUXSDOIN, + BKST, + CLK, + CS, + IDATAIN, + IOCLK0, + IOCLK1, + MEMUPDATE, + ODATAIN, + SDI, + T +); + + parameter DATA_RATE = "SDR"; // "SDR", "DDR" + parameter integer IDELAY_VALUE = 0; // 0 to 255 inclusive + parameter integer MCB_ADDRESS = 0; // 0 to 15 + parameter integer ODELAY_VALUE = 0; // 0 to 255 inclusive + parameter SERDES_MODE = "NONE"; // "NONE", "MASTER", "SLAVE" + parameter integer SIM_TAPDELAY_VALUE = 75; // 10 to 90 inclusive + + localparam IDELAY_MODE = "NORMAL"; // "NORMAL", "PCI" + localparam WRAPAROUND = 1'b0; + localparam STAY_AT_LIMIT = 1'b1; + localparam SDR = 1'b1; + localparam DDR = 1'b0; + localparam IO = 2'b00; + localparam I = 2'b01; + localparam O = 2'b11; + localparam PCI = 1'b0; + localparam NORMAL = 1'b1; + localparam DEFAULT = 4'b1001; + localparam FIXED = 4'b1000; + localparam VAR = 4'b1100; + localparam DIFF_PHASE_DETECTOR = 4'b1111; + localparam NONE = 1'b1; + localparam MASTER = 1'b1; + localparam SLAVE = 1'b0; + + output AUXSDO; + output DATAOUT2; + output DATAOUT; + output DOUT; + output DQSOUTN; + output DQSOUTP; + output SDO; + output TOUT; + + input ADD; + input AUXSDOIN; + input BKST; + input CLK; + input CS; + input IDATAIN; + input IOCLK0; + input IOCLK1; + input MEMUPDATE; + input ODATAIN; + input SDI; + input T; + input [4:0] AUXADDR; + + + + + reg COUNTER_WRAPAROUND_BINARY = WRAPAROUND; + reg DATA_RATE_BINARY = SDR; + reg [7:0] IDELAY2_VALUE_BINARY = 0; + reg IDELAY_MODE_BINARY = NORMAL; + reg [3:0] IDELAY_TYPE_BINARY = VAR; + reg SERDES_MODE_BINARY = NONE; + reg [3:0] MCB_ADDRESS_BINARY = 4'b0; + reg [6:0] SIM_TAPDELAY_VALUE_BINARY = 75; + reg [7:0] IDELAY_VALUE_BINARY = 0; + reg [7:0] ODELAY_VALUE_BINARY = 0; + + tri0 GSR = glbl.GSR; + + wire AUXSDO_OUT; + wire DATAOUT2_OUT; + wire DATAOUT_OUT; + wire DOUT_OUT; + wire DQSOUTN_OUT; + wire DQSOUTP_OUT; + wire SDO_OUT; + wire TOUT_OUT; + wire AUXSDO_OUTDELAY; + wire DATAOUT2_OUTDELAY; + wire DATAOUT_OUTDELAY; + wire DOUT_OUTDELAY; + wire DQSOUTN_OUTDELAY; + wire DQSOUTP_OUTDELAY; + wire SDO_OUTDELAY; + wire TOUT_OUTDELAY; + + wire ADD_IN; + wire AUXSDOIN_IN; + wire BKST_IN; + wire CLK_IN; + wire CS_IN; + wire IDATAIN_IN; + wire IOCLK0_IN; + wire IOCLK1_IN; + wire MEMUPDATE_IN; + wire ODATAIN_IN; + wire SDI_IN; + wire T_IN; + wire [4:0] AUXADDR_IN; + wire GSR_IN; + wire ADD_INDELAY; + wire AUXSDOIN_INDELAY; + wire BKST_INDELAY; + wire CLK_INDELAY; + wire CS_INDELAY; + wire IDATAIN_INDELAY; + wire IOCLK0_INDELAY; + wire IOCLK1_INDELAY; + wire MEMUPDATE_INDELAY; + wire ODATAIN_INDELAY; + wire SDI_INDELAY; + wire T_INDELAY; + wire [4:0] AUXADDR_INDELAY; + wire GSR_INDELAY; +//----------------------------------------------------------------------------- +//------------------- constants ----------------------------------------------- +//----------------------------------------------------------------------------- + localparam in_delay = 110; + localparam out_delay = 0; + localparam clk_delay = 1; + localparam MODULE_NAME = "IODRP2_MCB"; + localparam IDLE = 0, + ADDR_ACTIVE = 1, + DATA_ACTIVE = 2; + + wire output_delay_off; + wire input_delay_off; + wire [7:0] idelay_val_pe_reg; + reg [7:0] idelay_val_pe_m_reg = 0; + reg [7:0] idelay_val_pe_s_reg = 0; + wire [7:0] idelay_val_ne_reg; + reg [7:0] idelay_val_ne_m_reg = 0; + reg [7:0] idelay_val_ne_s_reg = 0; + reg sat_at_max_reg = WRAPAROUND; + reg rst_to_half_reg = 0; + reg ignore_rst = 0; + reg force_rx_reg = 0; + reg force_dly_dir_reg = 0; + reg [7:0] default_value = 8'ha5; + + wire rst_sig; + wire ce_sig; + wire inc_sig; + wire cal_sig; + reg ioclk0_int = 0; + reg ioclk1_int = 0; + wire ioclk_int; + reg first_edge = 0; + wire cs_sig; + wire snapback_sig; + wire half_sig; + wire delay1_out_sig; + reg delay1_out = 0; + reg delay2_out = 0; + reg delay1_out_dly = 0; + reg tout_out_int = 0; + reg busy_out_int = 1; + reg busy_out_dly = 1; + reg busy_out_dly1 = 1; + +// Error flags + reg counter_wraparound_err_flag = 0; + reg data_rate_err_flag = 0; + reg serdes_mode_err_flag = 0; + reg odelay_value_err_flag = 0; + reg idelay_value_err_flag = 0; + reg sim_tap_delay_err_flag = 0; + reg idelay_type_err_flag = 0; + reg idelay_mode_err_flag = 0; + reg delay_src_err_flag = 0; + reg idelay2_value_err_flag = 0; + reg mcb_address_err_flag = 0; + reg attr_err_flag = 0; +// internal logic + reg [4:0] cal_count = 5'b10010; + reg [7:0] cal_delay = 8'h00; + reg [7:0] max_delay = 8'h00; + reg [7:0] half_max = 8'h00; + reg [7:0] delay_val_pe_1 = 0; + reg [7:0] delay_val_ne_1 = 0; + wire delay_val_pe_clk; + wire delay_val_ne_clk; + wire delay1_reached; + reg delay1_reached_1 = 0; + reg delay1_reached_2 = 0; + wire delay1_working; + reg delay1_working_1 = 0; + reg delay1_working_2 = 0; + reg delay1_ignore = 0; + reg [7:0] delay_val_pe_2 = 0; + reg [7:0] delay_val_ne_2 = 0; + reg [7:0] odelay_val_pe_reg = 0; + reg [7:0] odelay_val_ne_reg = 0; + wire delay2_reached; + reg delay2_reached_1 = 0; + reg delay2_reached_2 = 0; + wire delay2_working; + reg delay2_working_1 = 0; + reg delay2_working_2 = 0; + reg delay2_ignore = 0; + reg delay1_in = 0; + reg delay2_in = 0; + reg calibrate = 0; + reg calibrate_done = 0; + reg sync_to_data_reg = 0; + reg pci_ce_reg = 0; + + reg [7:0] data_reg = 8'h00; + reg [7:0] addr_reg = 8'h80; + reg mem_updated = 1'b1; + reg [7:0] shift_out = 8'h00; + reg [7:0] mask = 8'h00; + reg [7:0] mc_iob [0:8]; + reg [7:0] mc_iob_mask [0:8]; + reg [2:0] if_state = IDLE; + reg cal_reg = 0; + reg snapback_reg = 0; + reg half_reg = 0; + reg inc_reg = 0; + reg ce_reg = 0; + reg rst_reg = 0; + reg direct_in_reg = 0; + reg [1:0] event_sel_m_reg = 2'b0; + reg plus1_s_reg = 1'b0; + reg [3:0] lumped_delay_select_reg = 4'h0; + reg lumped_delay_reg = 0; + + +//----------------------------------------------------------------------------- +//----------------- tasks / function ------------------------------------- +//----------------------------------------------------------------------------- +task inc_dec; +begin + if (GSR_INDELAY) begin + idelay_val_pe_m_reg <= IDELAY_VALUE_BINARY; + idelay_val_pe_s_reg <= IDELAY_VALUE_BINARY; + if (pci_ce_reg == 1) begin // PCI + idelay_val_ne_m_reg <= IDELAY2_VALUE_BINARY; + idelay_val_ne_s_reg <= IDELAY2_VALUE_BINARY; + end + else begin + idelay_val_ne_m_reg <= IDELAY_VALUE_BINARY; + idelay_val_ne_s_reg <= IDELAY_VALUE_BINARY; + end + end + else if (rst_sig) begin + if (rst_to_half_reg == 1'b1) begin + // rst to half + if (SERDES_MODE_BINARY == SLAVE) begin + if ((ignore_rst == 1'b0) && (IDELAY_TYPE_BINARY != DIFF_PHASE_DETECTOR)) begin + // all non diff phase detector slave rst + idelay_val_pe_s_reg <= half_max; + idelay_val_ne_s_reg <= half_max; + end + else if (ignore_rst == 1'b0) begin + // slave phase detector first rst + idelay_val_pe_m_reg <= half_max; + idelay_val_ne_m_reg <= half_max; + idelay_val_pe_s_reg <= half_max << 1; + idelay_val_ne_s_reg <= half_max << 1; + ignore_rst <= 1'b1; + end + else begin + // slave phase det second or more rst + if ((idelay_val_pe_m_reg + half_max) > max_delay) begin + idelay_val_pe_s_reg <= idelay_val_pe_m_reg + half_max - max_delay - 1; + idelay_val_ne_s_reg <= idelay_val_ne_m_reg + half_max - max_delay - 1; + end + else begin + idelay_val_pe_s_reg <= idelay_val_pe_m_reg + half_max; + idelay_val_ne_s_reg <= idelay_val_ne_m_reg + half_max; + end + end + end + else if ((ignore_rst == 1'b0) || (IDELAY_TYPE_BINARY != DIFF_PHASE_DETECTOR)) begin + // master or none, first diff phase rst or all others + idelay_val_pe_m_reg <= half_max; + idelay_val_ne_m_reg <= half_max; + ignore_rst <= 1'b1; + end + end + else begin + // rst to 0 + idelay_val_pe_m_reg <= 0; + idelay_val_ne_m_reg <= 0; + idelay_val_pe_s_reg <= 0; + idelay_val_ne_s_reg <= 0; + end + end + else if ( ~busy_out_int && ce_sig && ~rst_sig && + ((IDELAY_TYPE_BINARY == VAR) || + (IDELAY_TYPE_BINARY == DIFF_PHASE_DETECTOR)) ) begin //variable + if (inc_sig) begin // inc + // MASTER or NONE + // (lt max_delay inc m) + if (idelay_val_pe_m_reg < max_delay) begin + idelay_val_pe_m_reg <= idelay_val_pe_m_reg + 1; + end + // wrap to 0 wrap (gte max_delay and wrap to 0) + else if (sat_at_max_reg == WRAPAROUND) begin + idelay_val_pe_m_reg <= 8'h00; + end + // stay at max (gte max_delay and stay at max) + else begin + idelay_val_pe_m_reg <= max_delay; + end + // SLAVE + // (lt max_delay inc s) + if (idelay_val_pe_s_reg < max_delay) begin + idelay_val_pe_s_reg <= idelay_val_pe_s_reg + 1; + end + // wrap to 0 wrap (gte max_delay and wrap to 0) + else if (sat_at_max_reg == WRAPAROUND) begin + idelay_val_pe_s_reg <= 8'h00; + end + // stay at max (gte max_delay and stay at max) + else begin + idelay_val_pe_s_reg <= max_delay; + end + // MASTER or NONE + // (lt max_delay inc) + if (idelay_val_ne_m_reg < max_delay) begin + idelay_val_ne_m_reg <= idelay_val_ne_m_reg + 1; + end + // wrap to 0 wrap (gte max_delay and wrap to 0) + else if (sat_at_max_reg == WRAPAROUND) begin + idelay_val_ne_m_reg <= 8'h00; + end + // stay at max (gte max_delay and stay at max) + else begin + idelay_val_ne_m_reg <= max_delay; + end + // SLAVE + // (lt max_delay inc) + if (idelay_val_ne_s_reg < max_delay) begin + idelay_val_ne_s_reg <= idelay_val_ne_s_reg + 1; + end + // wrap to 0 wrap (gte max_delay and wrap to 0) + else if (sat_at_max_reg == WRAPAROUND) begin + idelay_val_ne_s_reg <= 8'h00; + end + // stay at max (gte max_delay and stay at max) + else begin + idelay_val_ne_s_reg <= max_delay; + end + end + else begin // dec + // MASTER or NONE + // (between 0 and max_delay dec) + if ((idelay_val_pe_m_reg > 8'h00) && + (idelay_val_pe_m_reg <= max_delay)) begin + idelay_val_pe_m_reg <= idelay_val_pe_m_reg - 1; + end + // stay at max (0) (eq 0 and stay at max/min) + else if ((sat_at_max_reg == STAY_AT_LIMIT) && (idelay_val_pe_m_reg == 0)) begin + idelay_val_pe_m_reg <= 8'h00; + end + // wrap to 0 wrap (gte max_delay or (eq 0 and wrap to max)) + else begin + idelay_val_pe_m_reg <= max_delay; + end + // SLAVE + // (between 0 and max_delay dec) + if ((idelay_val_pe_s_reg > 8'h00) && + (idelay_val_pe_s_reg <= max_delay)) begin + idelay_val_pe_s_reg <= idelay_val_pe_s_reg - 1; + end + // stay at max (0) (eq 0 and stay at max/min) + else if ((sat_at_max_reg == STAY_AT_LIMIT) && (idelay_val_pe_s_reg == 0)) begin + idelay_val_pe_s_reg <= 8'h00; + end + // wrap to 0 wrap (gte max_delay or (eq 0 and wrap to max)) + else begin + idelay_val_pe_s_reg <= max_delay; + end + // MASTER or NONE + // (between 0 and max_delay dec) + if ((idelay_val_ne_m_reg > 8'h00) && + (idelay_val_ne_m_reg <= max_delay)) begin + idelay_val_ne_m_reg <= idelay_val_ne_m_reg - 1; + end + // stay at max (0) (eq 0 and stay at max/min) + else if ((sat_at_max_reg == STAY_AT_LIMIT) && (idelay_val_ne_m_reg == 0)) begin + idelay_val_ne_m_reg <= 8'h00; + end + // wrap to 0 wrap (gte max_delay or (eq 0 and wrap to max)) + else begin + idelay_val_ne_m_reg <= max_delay; + end + // SLAVE + // (between 0 and max_delay dec) + if ((idelay_val_ne_s_reg > 8'h00) && + (idelay_val_ne_s_reg <= max_delay)) begin + idelay_val_ne_s_reg <= idelay_val_ne_s_reg - 1; + end + // stay at max (0) (eq 0 and stay at max/min) + else if ((sat_at_max_reg == STAY_AT_LIMIT) && (idelay_val_ne_s_reg == 0)) begin + idelay_val_ne_s_reg <= 8'h00; + end + // wrap to 0 wrap (gte max_delay or (eq 0 and wrap to max)) + else begin + idelay_val_ne_s_reg <= max_delay; + end + end + end + end +endtask +task write_to_ioi; +begin + case (addr_reg[6:0]) + 7'h01: begin + {cal_reg, snapback_reg, half_reg, inc_reg, ce_reg, rst_reg} <= data_reg[5:0]; + shift_out <= 8'h0; + end + 7'h02: begin + idelay_val_pe_m_reg <= data_reg; + idelay_val_pe_s_reg <= data_reg; + shift_out <= data_reg; + end + 7'h03: begin + idelay_val_ne_m_reg <= data_reg; + idelay_val_ne_s_reg <= data_reg; + shift_out <= data_reg; + end + 7'h04: begin + odelay_val_pe_reg <= data_reg; + shift_out <= data_reg; + end + 7'h05: begin + odelay_val_ne_reg <= data_reg; + shift_out <= data_reg; + end + 7'h06: begin + if (SERDES_MODE_BINARY == SLAVE) begin + {direct_in_reg, force_rx_reg, force_dly_dir_reg} <= data_reg[4:2]; + plus1_s_reg <= data_reg[0]; + shift_out <= {3'b0, data_reg[4:2], 1'b0, data_reg[0]}; + end + else begin + {direct_in_reg, force_rx_reg, force_dly_dir_reg, event_sel_m_reg} <= data_reg[4:0]; + shift_out <= {3'b0, data_reg[4:0]}; + end + end + 7'h07: begin + {lumped_delay_select_reg, lumped_delay_reg, sync_to_data_reg, sat_at_max_reg, rst_to_half_reg} <= data_reg; + shift_out <= data_reg; + end + 7'h08: begin + max_delay <= data_reg; + half_max <= data_reg >> 1; + shift_out <= data_reg; + end + default: ; + endcase + end +endtask + +task read_from_ioi; +begin + case (addr_reg[6:0]) + 7'h00: shift_out <= 8'h0; + 7'h01: shift_out <= 8'h0; // w/o {2'b0, cal_reg, snapback_reg, half_reg, inc_reg, ce_reg, rst_reg}; + 7'h02: begin + if (SERDES_MODE_BINARY == SLAVE) + shift_out <= idelay_val_pe_s_reg; + else + shift_out <= idelay_val_pe_m_reg; + end + 7'h03: begin + if (SERDES_MODE_BINARY == SLAVE) + shift_out <= idelay_val_ne_s_reg; + else + shift_out <= idelay_val_ne_m_reg; + end + 7'h04: shift_out <= odelay_val_pe_reg; + 7'h05: shift_out <= odelay_val_ne_reg; + 7'h06: begin + if (SERDES_MODE_BINARY == MASTER) + shift_out <= {3'b0, direct_in_reg, force_rx_reg, force_dly_dir_reg, event_sel_m_reg}; + else + shift_out <= {3'b0, direct_in_reg, force_rx_reg, force_dly_dir_reg, 1'b0, plus1_s_reg}; + end + 7'h07: shift_out <= {lumped_delay_select_reg, lumped_delay_reg, sync_to_data_reg, sat_at_max_reg, rst_to_half_reg}; + 7'h08: shift_out <= max_delay; + default: shift_out <= 8'h0; + endcase + end +endtask + + assign rst_sig = rst_reg; + assign cal_sig = cal_reg; + assign inc_sig = inc_reg; + assign ce_sig = ce_reg; + assign snapback_sig = snapback_reg; + assign half_sig = half_reg; + assign output_delay_off = force_dly_dir_reg && force_rx_reg; + assign input_delay_off = force_dly_dir_reg && ~force_rx_reg; + assign idelay_val_pe_reg = (SERDES_MODE_BINARY == SLAVE) ? idelay_val_pe_s_reg : idelay_val_pe_m_reg; + assign idelay_val_ne_reg = (SERDES_MODE_BINARY == SLAVE) ? idelay_val_ne_s_reg : idelay_val_ne_m_reg; + assign delay1_reached = delay1_reached_1 || delay1_reached_2; + assign delay2_reached = delay2_reached_1 || delay2_reached_2; + assign delay1_working = delay1_working_1 || delay1_working_2; + assign delay2_working = delay2_working_1 || delay2_working_2; + + initial begin +//----------------------------------------------------------------------------- +//----------------- DATA_RATE Check ------------------------------------------ +//----------------------------------------------------------------------------- + if (DATA_RATE == "SDR") DATA_RATE_BINARY <= SDR; + else if (DATA_RATE == "DDR") DATA_RATE_BINARY <= DDR; + else begin + #1; + $display("Attribute Syntax Error : The attribute DATA_RATE on %s instance %m is set to %s. Legal values for this attribute are SDR or DDR\n", MODULE_NAME, DATA_RATE); + data_rate_err_flag = 1; + end + +//----------------------------------------------------------------------------- +//----------------- IDELAY_VALUE Check ---------------------------------------- +//----------------------------------------------------------------------------- + if ((IDELAY_VALUE >= 0) && (IDELAY_VALUE <= 255)) begin + IDELAY_VALUE_BINARY = IDELAY_VALUE; + idelay_val_pe_m_reg = IDELAY_VALUE; + idelay_val_pe_s_reg = IDELAY_VALUE; + if (IDELAY_MODE != "PCI") begin + idelay_val_ne_m_reg = IDELAY_VALUE; + idelay_val_ne_s_reg = IDELAY_VALUE; + end + end + else begin + #1; + $display("Attribute Syntax Error : The Attribute IDELAY_VALUE on %s instance %m is set to %d. Legal values for this attribute are 0, 1, 2, ... 253, 254, 255.\n", MODULE_NAME, IDELAY_VALUE); + idelay_value_err_flag = 1; + end + +//----------------------------------------------------------------------------- +//----------------- MCB_ADDRESS Check ---------------------------------------- +//----------------------------------------------------------------------------- + if ((MCB_ADDRESS >= 0) && (MCB_ADDRESS <= 15)) begin + MCB_ADDRESS_BINARY = MCB_ADDRESS; + end + else begin + #1; + $display("Attribute Syntax Error : The Attribute MCB_ADDRESS on %s instance %m is set to %d. Legal values for this attribute are 0, 1, 2, ... 13, 14, 15.\n", MODULE_NAME, MCB_ADDRESS); + mcb_address_err_flag = 1; + end + +//----------------------------------------------------------------------------- +//----------------- ODELAY_VALUE Check ---------------------------------------- +//----------------------------------------------------------------------------- + if ((ODELAY_VALUE >= 0) && (ODELAY_VALUE <= 255)) begin + ODELAY_VALUE_BINARY = ODELAY_VALUE; + odelay_val_pe_reg = ODELAY_VALUE; + odelay_val_ne_reg = ODELAY_VALUE; + end + else begin + #1; + $display("Attribute Syntax Error : The Attribute ODELAY_VALUE on %s instance %m is set to %d. Legal values for this attribute are 0, 1, 2, ... 253, 254, 255.\n", MODULE_NAME, ODELAY_VALUE); + odelay_value_err_flag = 1; + end + +//----------------------------------------------------------------------------- +//----------------- SERDES_MODE Check ----------------------------------------- +//----------------------------------------------------------------------------- + if (SERDES_MODE == "NONE") begin + SERDES_MODE_BINARY = NONE; + end + else if (SERDES_MODE == "MASTER") begin + SERDES_MODE_BINARY = MASTER; + end + else if (SERDES_MODE == "SLAVE") begin + SERDES_MODE_BINARY = SLAVE; + end + else begin + #1; + $display("Attribute Syntax Error : The Attribute SERDES_MODE on %s instance %m is set to %s. Legal values for this attribute are NONE, MASTER, or SLAVE.\n", MODULE_NAME, SERDES_MODE); + serdes_mode_err_flag = 1; + end +//----------------------------------------------------------------------------- +//----------------- SIM_TAPDELAY_VALUE Check ---------------------------------- +//----------------------------------------------------------------------------- + if ((SIM_TAPDELAY_VALUE >= 10) && (SIM_TAPDELAY_VALUE <= 90)) begin + SIM_TAPDELAY_VALUE_BINARY = SIM_TAPDELAY_VALUE; + end + else begin + #1; + $display("Attribute Syntax Error : The Attribute SIM_TAPDELAY_VALUE on %s instance %m is set to %d. Legal values for this attribute are between 10 and 90 ps inclusive.\n", MODULE_NAME, SIM_TAPDELAY_VALUE); + sim_tap_delay_err_flag = 1; + end + + if ( serdes_mode_err_flag || odelay_value_err_flag || + idelay_value_err_flag || sim_tap_delay_err_flag) begin + attr_err_flag = 1; + #1; + $display("Attribute Errors detected in %s instance %m: Simulation cannot continue. Exiting. \n", MODULE_NAME); + $finish; + end + + end //initial begin parameter check + +//----------------------------------------------------------------------------- +//-------------------- Input / Output ----------------------------------------- +//----------------------------------------------------------------------------- + assign #(out_delay) AUXSDO_OUTDELAY = AUXSDO_OUT; + assign #(out_delay) DATAOUT_OUTDELAY = DATAOUT_OUT; + assign #(out_delay) DATAOUT2_OUTDELAY = DATAOUT2_OUT; + assign #(out_delay) DOUT_OUTDELAY = DOUT_OUT; + assign #(out_delay) DQSOUTN_OUTDELAY = DQSOUTN_OUT; + assign #(out_delay) DQSOUTP_OUTDELAY = DQSOUTP_OUT; + assign #(out_delay) SDO_OUTDELAY = SDO_OUT; + assign #(out_delay) TOUT_OUTDELAY = TOUT_OUT; + + assign #(in_delay) ADD_INDELAY = ADD_IN; + assign #(in_delay) AUXADDR_INDELAY = AUXADDR_IN; + assign #(in_delay) AUXSDOIN_INDELAY = AUXSDOIN_IN; + assign #(in_delay) BKST_INDELAY = BKST_IN; + assign #(clk_delay) CLK_INDELAY = CLK_IN; + assign #(in_delay) CS_INDELAY = CS_IN; + assign #(in_delay) IDATAIN_INDELAY = IDATAIN_IN; + assign #(clk_delay) IOCLK0_INDELAY = IOCLK0_IN; + assign #(clk_delay) IOCLK1_INDELAY = IOCLK1_IN; + assign #(in_delay) MEMUPDATE_INDELAY = MEMUPDATE_IN; + assign #(in_delay) ODATAIN_INDELAY = ODATAIN_IN; + assign #(in_delay) SDI_INDELAY = SDI_IN; + assign #(in_delay) T_INDELAY = T_IN; + assign #(in_delay) GSR_INDELAY = GSR_IN; + +//----------------------------------------------------------------------------- +//----------------- I/O Assignments / Mux ------------------------------------- +//----------------------------------------------------------------------------- + // input delay paths + assign DATAOUT_OUT = delay1_out_sig; + assign DATAOUT2_OUT = (pci_ce_reg == 0) ? delay1_out_sig : delay2_out; + assign TOUT_OUT = (~output_delay_off && (~T_INDELAY || input_delay_off)) ? + tout_out_int : T_INDELAY; + + assign delay1_out_sig = ((IDELAY_TYPE_BINARY == DIFF_PHASE_DETECTOR) && + (SERDES_MODE_BINARY == SLAVE) && + (delay_val_pe_1 < half_max) ) ? + delay1_out_dly : delay1_out; +// output delay paths + assign #(SIM_TAPDELAY_VALUE) DOUT_OUT = (~output_delay_off && (~T_INDELAY || input_delay_off)) ? delay1_in : 1'b0; + assign DQSOUTN_OUT = ~delay1_out_sig; + assign DQSOUTP_OUT = delay1_out_sig; + assign cs_sig = ((CS_INDELAY === 1'b1) && ((AUXADDR_INDELAY === {MCB_ADDRESS_BINARY,SERDES_MODE_BINARY}) || (BKST_INDELAY === 1'b1))) ? 1'b1 : 1'b0; + assign AUXSDO_OUT = cs_sig ? shift_out[0] : AUXSDOIN_INDELAY; + assign SDO_OUT = shift_out[0]; + + initial begin + first_edge <= #150 1; + wait (GSR_INDELAY === 1'b0); + mc_iob_mask [0] = 8'h3f; + mc_iob_mask [1] = 8'hbf; + mc_iob_mask [2] = 8'h7f; + mc_iob_mask [3] = 8'hff; + mc_iob_mask [4] = 8'hff; + mc_iob_mask [5] = 8'hff; + mc_iob_mask [6] = 8'hff; + mc_iob_mask [7] = 8'hff; + mc_iob_mask [8] = 8'h7f; + mc_iob [0] = 8'h00; + mc_iob [1] = 8'h00; + mc_iob [2] = 8'h00; + mc_iob [3] = 8'h00; + mc_iob [4] = 8'h00; + mc_iob [5] = 8'h00; + mc_iob [6] = 8'h00; + mc_iob [7] = 8'h00; + mc_iob [8] = 8'h00; + end //initial begin other initializations + +//----------------------------------------------------------------------------- +//----------------- GLOBAL hidden GSR pin ------------------------------------- +//----------------------------------------------------------------------------- + + +//----------------------------------------------------------------------------- +//----------------- DDR Doubler ----------------------------------------- +//----------------------------------------------------------------------------- + always @(posedge IOCLK0_INDELAY) begin + if (first_edge == 1) begin + ioclk0_int <= 1; + ioclk0_int <= #100 0; + end + end + + generate if(DATA_RATE == "DDR") + always @(posedge IOCLK1_INDELAY) begin + if (first_edge== 1) begin + ioclk1_int <= 1; + ioclk1_int <= #100 0; + end + end + endgenerate + + assign ioclk_int = ioclk0_int | ioclk1_int; + +//----------------------------------------------------------------------------- +//----------------- Delay Line Inputs ----------------------------------------- +//----------------------------------------------------------------------------- + always @(posedge ioclk_int) begin + delay1_out_dly <= delay1_out; + end + +// delay line 1 input + always @(IDATAIN_INDELAY or DATAOUT_OUT or T_INDELAY or ODATAIN_INDELAY or GSR_INDELAY) begin + if ((T_INDELAY || output_delay_off) && ~input_delay_off) begin // input delay + if (pci_ce_reg == 0 ) delay1_in <= IDATAIN_INDELAY; // NORMAL + else delay1_in <= IDATAIN_INDELAY ^ DATAOUT_OUT; // PCI + end + else begin // output delay + if (output_delay_off) delay1_in <= 0; + else delay1_in <= ODATAIN_INDELAY; + end + end + +// delay line 2 input + always @(IDATAIN_INDELAY or DATAOUT2_OUT or T_INDELAY or ODATAIN_INDELAY or GSR_INDELAY) begin + if ((T_INDELAY || output_delay_off) && ~input_delay_off) begin // input delay + if (pci_ce_reg == 0 ) delay2_in <= ~IDATAIN_INDELAY; // NORMAL + else delay2_in <= IDATAIN_INDELAY ^ DATAOUT2_OUT; // PCI + end + else begin // output delay + if (output_delay_off) delay2_in <= 0; + else delay2_in <= ~ODATAIN_INDELAY; + end + end + +//----------------------------------------------------------------------------- +//----------------- Delay Lines ----------------------------------------------- +//----------------------------------------------------------------------------- + always @(delay1_in or GSR_INDELAY) begin + if (GSR_INDELAY) begin + delay1_reached_1 <= 1'b0; + delay1_reached_2 <= 1'b0; + delay1_working_1 <= 1'b0; + delay1_working_2 <= 1'b0; + delay1_ignore <= delay1_in; + end + else if (delay1_in) begin + if (~delay1_working || delay1_reached) begin + if (delay1_working_1 == 1'b0) delay1_working_1 <= 1'b1; + else delay1_working_2 <= 1'b1; + if ((T_INDELAY || output_delay_off) && ~input_delay_off) begin // input delay + if (IDATAIN_INDELAY) begin // positive edge + if (delay1_reached_1 == 1'b0) + delay1_reached_1 <= #(SIM_TAPDELAY_VALUE*delay_val_pe_1) 1'b1; + else + delay1_reached_2 <= #(SIM_TAPDELAY_VALUE*delay_val_pe_1) 1'b1; + end + else begin // negative edge + if (delay1_reached_1 == 1'b0) + delay1_reached_1 <= #(SIM_TAPDELAY_VALUE*delay_val_ne_1) 1'b1; + else + delay1_reached_2 <= #(SIM_TAPDELAY_VALUE*delay_val_ne_1) 1'b1; + end + end + else begin // output delay + if (ODATAIN_INDELAY) begin // positive edge + if (delay1_reached_1 == 1'b0) + delay1_reached_1 <= #(SIM_TAPDELAY_VALUE*delay_val_pe_1) 1'b1; + else + delay1_reached_2 <= #(SIM_TAPDELAY_VALUE*delay_val_pe_1) 1'b1; + end + else begin // negative edge + if (delay1_reached_1 == 1'b0) + delay1_reached_1 <= #(SIM_TAPDELAY_VALUE*delay_val_ne_1) 1'b1; + else + delay1_reached_2 <= #(SIM_TAPDELAY_VALUE*delay_val_ne_1) 1'b1; + end + end + end + else begin + delay1_ignore <= 1'b1; + end + end + end + + always @(delay2_in or GSR_INDELAY) begin + if (GSR_INDELAY) begin + delay2_reached_1 <= 1'b0; + delay2_reached_2 <= 1'b0; + delay2_working_1 <= 1'b0; + delay2_working_2 <= 1'b0; + delay2_ignore <= delay2_in; + end + else if (delay2_in) begin + if (~delay2_working || delay2_reached) begin + if (delay2_working_1 == 1'b0) delay2_working_1 <= 1'b1; + else delay2_working_2 <= 1'b1; + if ((T_INDELAY || output_delay_off) && ~input_delay_off) begin // input delay + if (IDATAIN_INDELAY) begin // positive edge + if (delay2_reached_1 == 1'b0) + delay2_reached_1 <= #(SIM_TAPDELAY_VALUE*delay_val_pe_2) 1'b1; + else + delay2_reached_2 <= #(SIM_TAPDELAY_VALUE*delay_val_pe_2) 1'b1; + end + else begin // negative edge + if (delay2_reached_1 == 1'b0) + delay2_reached_1 <= #(SIM_TAPDELAY_VALUE*delay_val_ne_2) 1'b1; + else + delay2_reached_2 <= #(SIM_TAPDELAY_VALUE*delay_val_ne_2) 1'b1; + end + end + else begin // output delay + if (ODATAIN_INDELAY) begin // positive edge + if (delay2_reached_1 == 1'b0) + delay2_reached_1 <= #(SIM_TAPDELAY_VALUE*delay_val_pe_2) 1'b1; + else + delay2_reached_2 <= #(SIM_TAPDELAY_VALUE*delay_val_pe_2) 1'b1; + end + else begin // negative edge + if (delay2_reached_1 == 1'b0) + delay2_reached_1 <= #(SIM_TAPDELAY_VALUE*delay_val_ne_2) 1'b1; + else + delay2_reached_2 <= #(SIM_TAPDELAY_VALUE*delay_val_ne_2) 1'b1; + end + end + end + else begin + delay2_ignore <= 1'b1; + end + end + end + + always @(posedge delay1_reached) begin + delay1_ignore <= #1 1'b0; + end + + always @(posedge delay1_reached_1) begin + delay1_working_1 <= #1 1'b0; + delay1_reached_1 <= #1 1'b0; + end + + always @(posedge delay1_reached_2) begin + delay1_working_2 <= #1 1'b0; + delay1_reached_2 <= #1 1'b0; + end + + always @(posedge delay2_reached) begin + delay2_ignore <= #1 1'b0; + end + + always @(posedge delay2_reached_1) begin + delay2_working_1 <= #1 1'b0; + delay2_reached_1 <= #1 1'b0; + end + + always @(posedge delay2_reached_2) begin + delay2_working_2 <= #1 1'b0; + delay2_reached_2 <= #1 1'b0; + end + +//----------------------------------------------------------------------------- +//----------------- Output FF ------------------------------------------------- +//----------------------------------------------------------------------------- + always @(posedge delay1_reached or posedge delay2_reached or delay1_working or delay2_working or posedge delay1_ignore or posedge delay2_ignore or T_INDELAY or GSR_INDELAY) begin + if ((pci_ce_reg == 0) || (~T_INDELAY && ~output_delay_off) || + input_delay_off) begin //NORMAL in or output + if (GSR_INDELAY || ~first_edge || (~delay1_working && ~delay2_working)) begin + delay1_out <= delay1_in; + end + else if ( (delay1_reached && ~delay1_ignore) || + (delay1_ignore && ~delay1_out) ) begin + delay1_out <= 1'b1; + end + else if ( (delay2_reached && ~delay2_ignore) || + (delay2_ignore && delay1_out) ) begin + delay1_out <= 1'b0; + end + delay2_out <= 1'b0; + end + else begin // PCI in + if (GSR_INDELAY || delay1_reached) begin + delay1_out <= IDATAIN_INDELAY; + end + if (GSR_INDELAY || delay2_reached) begin + delay2_out <= IDATAIN_INDELAY; + end + end + end +//----------------------------------------------------------------------------- +//----------------- TOUT delay ------------------------------------------------ +//----------------------------------------------------------------------------- + always @(T_INDELAY) begin + #(SIM_TAPDELAY_VALUE); + tout_out_int <= T_INDELAY; + end + +//----------------------------------------------------------------------------- +//----------------- Delay Preset Values --------------------------------------- +//----------------------------------------------------------------------------- + assign delay_val_pe_clk = sync_to_data_reg ? delay1_in : ioclk_int; + assign delay_val_ne_clk = sync_to_data_reg ? delay2_in : ioclk_int; + + always @(posedge delay_val_pe_clk or posedge rst_sig or posedge busy_out_int) begin + if ((rst_sig == 1'b1) || (busy_out_int == 1'b1)) begin + busy_out_dly <= 1'b1; + busy_out_dly1 <= 1'b1; + end + else begin + busy_out_dly <= busy_out_dly1; + busy_out_dly1 <= busy_out_int; + end + end + + + always @(posedge delay_val_pe_clk or rst_sig) begin + if ((~T_INDELAY && ~output_delay_off) || input_delay_off) begin // output + delay_val_pe_1 <= odelay_val_pe_reg; + delay_val_pe_2 <= odelay_val_pe_reg; + end + // input delays + else if (IDELAY_TYPE_BINARY == DEFAULT) begin + delay_val_pe_1 <= default_value; + delay_val_pe_2 <= default_value; + end + else if (IDELAY_TYPE_BINARY == FIXED) begin + if (pci_ce_reg == 1) begin // PCI + delay_val_pe_1 <= IDELAY_VALUE_BINARY[7:0]; + delay_val_pe_2 <= IDELAY2_VALUE_BINARY[7:0]; + end + else begin // normal + delay_val_pe_1 <= IDELAY_VALUE_BINARY[7:0]; + delay_val_pe_2 <= IDELAY_VALUE_BINARY[7:0]; + end + end + else if (IDELAY_TYPE_BINARY == VAR) begin + if (pci_ce_reg == 1) begin // PCI + delay_val_pe_1 <= idelay_val_pe_reg; + delay_val_pe_2 <= idelay_val_ne_reg; + end + else begin // normal + delay_val_pe_1 <= idelay_val_pe_reg; + delay_val_pe_2 <= idelay_val_ne_reg; + end + end + else if (IDELAY_TYPE_BINARY == DIFF_PHASE_DETECTOR) begin + delay_val_pe_1 <= idelay_val_pe_reg; + delay_val_pe_2 <= idelay_val_ne_reg; + end + else begin // default + delay_val_pe_1 <= default_value; + delay_val_pe_2 <= default_value; + end + end + + always @(posedge delay_val_ne_clk or rst_sig) begin + if ((~T_INDELAY && ~output_delay_off) || input_delay_off) begin // output + delay_val_ne_1 <= odelay_val_ne_reg; + delay_val_ne_2 <= odelay_val_ne_reg; + end + //input delays + else if (IDELAY_TYPE_BINARY == DEFAULT) begin + delay_val_ne_1 <= default_value; + delay_val_ne_2 <= default_value; + end + else if (IDELAY_TYPE_BINARY == FIXED) begin + if (pci_ce_reg == 1) begin // PCI + delay_val_ne_1 <= IDELAY_VALUE_BINARY[7:0]; + delay_val_ne_2 <= IDELAY2_VALUE_BINARY[7:0]; + end + else begin // normal + delay_val_ne_1 <= IDELAY_VALUE_BINARY[7:0]; + delay_val_ne_2 <= IDELAY_VALUE_BINARY[7:0]; + end + end + else if (IDELAY_TYPE_BINARY == VAR) begin + if (pci_ce_reg == 1) begin // PCI + delay_val_ne_1 <= idelay_val_pe_reg; + delay_val_ne_2 <= idelay_val_ne_reg; + end + else begin // normal + delay_val_ne_1 <= idelay_val_pe_reg; + delay_val_ne_2 <= idelay_val_ne_reg; + end + end + else if (IDELAY_TYPE_BINARY == DIFF_PHASE_DETECTOR) begin + delay_val_ne_1 <= idelay_val_pe_reg; + delay_val_ne_2 <= idelay_val_ne_reg; + end + else begin // default + delay_val_ne_1 <= default_value; + delay_val_ne_2 <= default_value; + end + end + +//----------------------------------------------------------------------------- +//----------------- Max Count CAL --------------------------------------------- +//----------------------------------------------------------------------------- + + always @(posedge CLK_INDELAY or posedge GSR_INDELAY) begin + if (GSR_INDELAY) begin + cal_count <= 5'b10010; + busy_out_int <= 1'b1; // reset + end + else if (cal_sig && ~busy_out_int) begin + cal_count <= 5'b00000; + busy_out_int <= 1'b1; // begin cal + end + else if (ce_sig && ~busy_out_int) begin + cal_count <= 5'b10010; + busy_out_int <= 1'b1; // inc (busy high 2 clocks) + end + else if (busy_out_int && (cal_count < 5'b10011) ) begin + cal_count <= cal_count + 1; + busy_out_int <= 1'b1; // continue + end + else begin + busy_out_int <= 1'b0; // done + end + end + + always @(posedge ioclk_int) begin + if (~calibrate & ~calibrate_done && busy_out_int && (cal_count == 5'b01000) ) + calibrate <= 1'b1; + else + calibrate <= 1'b0; + end + + always @(cal_delay or calibrate or GSR_INDELAY or cal_sig or busy_out_int) begin + if ((GSR_INDELAY) || (cal_sig && ~busy_out_int)) begin + cal_delay <= 8'h00; + calibrate_done <= 1'b0; + end + else if (calibrate && (cal_delay !== 8'hff)) begin + #(SIM_TAPDELAY_VALUE); + if (calibrate) begin + cal_delay <= cal_delay + 1; + end + else begin + if ((pci_ce_reg == 1) && (DATA_RATE_BINARY == SDR)) begin + cal_delay <= cal_delay >> 1; + end + calibrate_done <= 1'b1; + end + end + else if (calibrate && (cal_delay == 8'hff)) begin + calibrate_done <= 1'b1; + end + else begin + #(SIM_TAPDELAY_VALUE); + calibrate_done <= 1'b0; + end + end + +//----------------------------------------------------------------------------- +//----------------- Interface State Machine------------------------------------ +//----------------------------------------------------------------------------- + always @(posedge CLK_INDELAY) begin + if (GSR_INDELAY || rst_sig) begin + if_state <= IDLE; + shift_out <= 8'h00; + addr_reg <= 8'h80; + data_reg <= 8'h00; + mem_updated <= 1'b1; + cal_reg <= 0; + snapback_reg <= 0; + half_reg <= 0; + inc_reg <= 0; + ce_reg <= 0; + rst_reg <= 0; + end + else begin + if (cal_reg == 1) cal_reg <= 0; + if (snapback_reg == 1) snapback_reg <= 0; + if (half_reg == 1) half_reg <= 0; + if (inc_reg == 1) inc_reg <= 0; + if (ce_reg == 1) ce_reg <= 0; + case (if_state) + IDLE: begin + if (cs_sig && ADD_INDELAY) begin + if_state <= ADDR_ACTIVE; + addr_reg <= {SDI_INDELAY, addr_reg[7:1]}; + shift_out <= {1'b0, shift_out[7:1]}; + end + else if (cs_sig && ~ADD_INDELAY ) begin + if_state <= DATA_ACTIVE; + data_reg <= {SDI_INDELAY, data_reg[7:1]}; + shift_out <= {1'b0, shift_out[7:1]}; + end + else begin + if_state <= IDLE; + if (~addr_reg[7]) read_from_ioi; + else shift_out <= mc_iob[addr_reg[3:0]]; + end + end + ADDR_ACTIVE: begin + if (cs_sig && ADD_INDELAY) begin + if_state <= ADDR_ACTIVE; + addr_reg <= {SDI_INDELAY, addr_reg[7:1]}; + shift_out <= {1'b0, shift_out[7:1]}; + end + else if (~cs_sig && ~ADD_INDELAY) begin + if_state <= IDLE; + if (~addr_reg[7]) read_from_ioi; + else shift_out <= mc_iob[addr_reg[3:0]]; + end + else begin + if_state <= IDLE; + $display("Illegal interface state transition on %s instance %m at time %t: ADDR_ACTIVE state - ADD [%d] and CS [%d] must both be low for one clk to advance.\n", MODULE_NAME, $time, ADD_INDELAY, cs_sig); + end + end + DATA_ACTIVE: begin + if (cs_sig && ~ADD_INDELAY) begin + if_state <= DATA_ACTIVE; + data_reg <= {SDI_INDELAY, data_reg[7:1]}; + shift_out <= {1'b0, shift_out[7:1]}; + end + else if (~cs_sig && ~ADD_INDELAY ) begin + if_state <= IDLE; + if (addr_reg[7] == 1'b0) begin + if (MEMUPDATE_INDELAY == 1'b1) write_to_ioi; + else mem_updated <= 1'b0; + end + else begin + if (MEMUPDATE_INDELAY == 1'b1) begin + mc_iob[addr_reg[3:0]] <= data_reg & mc_iob_mask[addr_reg[3:0]]; + shift_out <= data_reg & mc_iob_mask[addr_reg[3:0]]; + end + else begin + mem_updated <= 1'b0; + end + end + end + else begin + if_state <= IDLE; + $display("Illegal interface state transition on %s instance %m at time %t: DATA_ACTIVE state - ADD [%d] must stay low\n", MODULE_NAME, $time, ADD_INDELAY); + end + end + default: begin + if_state <= IDLE; + $display("Illegal state entered on %s instance %m at time %t: state %3b\n", MODULE_NAME, $time, if_state); + end + endcase + end + + if ((mem_updated == 1'b0) && (MEMUPDATE_INDELAY == 1'b1)) begin + if (addr_reg[7] == 1'b0) begin + write_to_ioi; + mem_updated <= 1'b1; + end + else begin + mc_iob[addr_reg[3:0]] <= data_reg & mc_iob_mask[addr_reg[3:0]]; + mem_updated <= 1'b1; + end + end + + inc_dec; + + if (calibrate_done) begin + max_delay <= cal_delay; + half_max <= cal_delay >> 1; + end + + end + + assign AUXSDO = AUXSDO_OUTDELAY; + assign DATAOUT = DATAOUT_OUTDELAY; + assign DATAOUT2 = DATAOUT2_OUTDELAY; + assign DOUT = DOUT_OUTDELAY; + assign DQSOUTN = DQSOUTN_OUTDELAY; + assign DQSOUTP = DQSOUTP_OUTDELAY; + assign SDO = SDO_OUTDELAY; + assign TOUT = TOUT_OUTDELAY; + + assign ADD_IN = ADD; + assign AUXADDR_IN = AUXADDR; + assign AUXSDOIN_IN = AUXSDOIN; + assign BKST_IN = BKST; + assign CLK_IN = CLK; + assign CS_IN = CS; + assign IDATAIN_IN = IDATAIN; + assign IOCLK0_IN = IOCLK0; + assign IOCLK1_IN = IOCLK1; + assign MEMUPDATE_IN = MEMUPDATE; + assign ODATAIN_IN = ODATAIN; + assign SDI_IN = SDI; + assign T_IN = T; + assign GSR_IN = GSR; + specify + ( CLK => SDO) = (0, 0); + ( IDATAIN => DATAOUT) = (0, 0); + ( IDATAIN => DATAOUT2) = (0, 0); + ( ODATAIN => DOUT) = (0, 0); + ( T => TOUT) = (0, 0); + + specparam PATHPULSE$ = 0; + endspecify +endmodule // IODRP2_MCB diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/ISERDES.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/ISERDES.v new file mode 100644 index 0000000..cba9389 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/ISERDES.v @@ -0,0 +1,1329 @@ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2005 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Source Synchronous Input Deserializer +// /___/ /\ Filename : ISERDES.v +// \ \ / \ Timestamp : Thu Mar 11 16:43:51 PST 2005 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 03/11/05 - Initialized outpus. +// 03/18/05 - Changed SIM_TAPDELAY_VALUE to 75 from 78. +// 10/13/06 - Fixed CR 426606 +// 06/06/07 - Added wire declaration for internal signals +// 09/10/07 - CR 447760 Added Strict DRC for BITSLIP and INTERFACE_TYPE combinations +// 01/27/09 - CR 504307 removed glitches from the tap +// End Revision + +`timescale 1 ps / 1 ps + +module ISERDES (O, Q1, Q2, Q3, Q4, Q5, Q6, SHIFTOUT1, SHIFTOUT2, + BITSLIP, CE1, CE2, CLK, CLKDIV, D, DLYCE, DLYINC, DLYRST, OCLK, REV, SHIFTIN1, SHIFTIN2, SR); + output O; + output Q1; + output Q2; + output Q3; + output Q4; + output Q5; + output Q6; + output SHIFTOUT1; + output SHIFTOUT2; + + input BITSLIP; + input CE1; + input CE2; + input CLK; + input CLKDIV; + input D; + input DLYCE; + input DLYINC; + input DLYRST; + tri0 GSR = glbl.GSR; + input OCLK; + input REV; + input SHIFTIN1; + input SHIFTIN2; + input SR; + + parameter BITSLIP_ENABLE = "FALSE"; + parameter DATA_RATE = "DDR"; + parameter integer DATA_WIDTH = 4; + parameter INIT_Q1 = 1'b0; + parameter INIT_Q2 = 1'b0; + parameter INIT_Q3 = 1'b0; + parameter INIT_Q4 = 1'b0; + parameter INTERFACE_TYPE = "MEMORY"; + parameter IOBDELAY = "NONE"; + parameter IOBDELAY_TYPE = "DEFAULT"; + parameter integer IOBDELAY_VALUE = 0; + parameter integer NUM_CE = 2; + parameter SERDES_MODE = "MASTER"; + parameter SRVAL_Q1 = 1'b0; + parameter SRVAL_Q2 = 1'b0; + parameter SRVAL_Q3 = 1'b0; + parameter SRVAL_Q4 = 1'b0; + + integer delay_count, delay_count_int; + + reg [1:0] sel; + reg [3:0] data_width_int; + reg bts_q1, bts_q2, bts_q3; + reg c23, c45, c67; + reg ce1r, ce2r; + reg dataq1rnk2, dataq2rnk2, dataq3rnk2; + reg dataq3rnk1, dataq4rnk1, dataq5rnk1, dataq6rnk1; + reg dataq4rnk2, dataq5rnk2, dataq6rnk2; + reg ice, memmux, q2pmux; + reg mux, mux1, muxc; + reg clkdiv_int, clkdivmux; + reg o_out = 0, q1_out = 0, q2_out = 0, q3_out = 0, q4_out = 0, q5_out = 0, q6_out = 0; + reg q1rnk2, q2rnk2, q3rnk2, q4rnk2, q5rnk2, q6rnk2; + reg q1rnk3, q2rnk3, q3rnk3, q4rnk3, q5rnk3, q6rnk3; + reg q4rnk1, q5rnk1, q6rnk1, q6prnk1; + reg num_ce_int; + reg qr1, qr2, qhc1, qhc2, qlc1, qlc2; + reg shiftn2_in, shiftn1_in; + reg q1rnk1, q2nrnk1, q1prnk1, q2prnk1, q3rnk1; + reg serdes_mode_int, data_rate_int, bitslip_enable_int; + reg d_delay, o_delay; + + wire shiftout1_out, shiftout2_out; + wire [1:0] sel1; + wire [2:0] bsmux; + wire [3:0] selrnk3; + wire delay_chain_0, delay_chain_1, delay_chain_2, delay_chain_3, + delay_chain_4, delay_chain_5, delay_chain_6, delay_chain_7, + delay_chain_8, delay_chain_9, delay_chain_10, delay_chain_11, + delay_chain_12, delay_chain_13, delay_chain_14, delay_chain_15, + delay_chain_16, delay_chain_17, delay_chain_18, delay_chain_19, + delay_chain_20, delay_chain_21, delay_chain_22, delay_chain_23, + delay_chain_24, delay_chain_25, delay_chain_26, delay_chain_27, + delay_chain_28, delay_chain_29, delay_chain_30, delay_chain_31, + delay_chain_32, delay_chain_33, delay_chain_34, delay_chain_35, + delay_chain_36, delay_chain_37, delay_chain_38, delay_chain_39, + delay_chain_40, delay_chain_41, delay_chain_42, delay_chain_43, + delay_chain_44, delay_chain_45, delay_chain_46, delay_chain_47, + delay_chain_48, delay_chain_49, delay_chain_50, delay_chain_51, + delay_chain_52, delay_chain_53, delay_chain_54, delay_chain_55, + delay_chain_56, delay_chain_57, delay_chain_58, delay_chain_59, + delay_chain_60, delay_chain_61, delay_chain_62, delay_chain_63; + + wire bitslip_in; + wire ce1_in; + wire ce2_in; + wire clk_in; + wire clkdiv_in; + wire d_in; + wire dlyce_in; + wire dlyinc_in; + wire dlyrst_in; + wire gsr_in; + wire oclk_in; + wire rev_in; + wire sr_in; + wire shiftin1_in; + wire shiftin2_in; + + buf b_o (O, o_out); + buf b_q1 (Q1, q1_out); + buf b_q2 (Q2, q2_out); + buf b_q3 (Q3, q3_out); + buf b_q4 (Q4, q4_out); + buf b_q5 (Q5, q5_out); + buf b_q6 (Q6, q6_out); + buf b_shiftout1 (SHIFTOUT1, shiftout1_out); + buf b_shiftout2 (SHIFTOUT2, shiftout2_out); + + buf b_bitslip (bitslip_in, BITSLIP); + buf b_ce1 (ce1_in, CE1); + buf b_ce2 (ce2_in, CE2); + buf b_clk (clk_in, CLK); + buf b_clkdiv (clkdiv_in, CLKDIV); + buf b_d (d_in, D); + buf b_dlyce (dlyce_in, DLYCE); + buf b_dlyinc (dlyinc_in, DLYINC); + buf b_dlyrst (dlyrst_in, DLYRST); + buf b_gsr (gsr_in, GSR); + buf b_oclk (oclk_in, OCLK); + buf b_rev (rev_in, REV); + buf b_sr (sr_in, SR); + buf b_shiftin1 (shiftin1_in, SHIFTIN1); + buf b_shiftin2 (shiftin2_in, SHIFTIN2); + + // workaround for XSIM + wire rev_in_AND_NOT_sr_in = rev_in & !sr_in; + wire NOT_rev_in_AND_sr_in = !rev_in & sr_in; + + localparam SIM_TAPDELAY_VALUE = 75; + +// Parameter declarations for delays + localparam ffinp = 300; + localparam mxinp1 = 60; + localparam mxinp2 = 120; + +// Delay parameters + + localparam ffice = 300; + localparam mxice = 60; + +// Delay parameter assignment + + localparam ffbsc = 300; + localparam mxbsc = 60; + + localparam mxinp1_my = 0; + + + initial begin + +// --------CR 447760 DRC -- BITSLIP - INTERFACE_TYPE combination ------------------ + + if((INTERFACE_TYPE == "MEMORY") && (BITSLIP_ENABLE == "TRUE")) begin + $display("Attribute Syntax Error: BITSLIP_ENABLE is currently set to TRUE when INTERFACE_TYPE is set to MEMORY. This is an invalid configuration."); + $finish; + end + else if((INTERFACE_TYPE == "NETWORKING") && (BITSLIP_ENABLE == "FALSE")) begin + $display ("Attribute Syntax Error: BITSLIP_ENABLE is currently set to FALSE when INTERFACE_TYPE is set to NETWORKING. If BITSLIP is not intended to be used, please set BITSLIP_ENABLE to TRUE and tie the BITSLIP port to ground."); + $finish; + end + +// --------------------------------------------------------------------------------- + + if (IOBDELAY_VALUE < 0 || IOBDELAY_VALUE > 63) begin + + $display("Attribute Syntax Error : The attribute IOBDELAY_VALUE on ISERDES instance %m is set to %d. Legal values for this attribute are 0, 1, 2, 3, .... or 63", IOBDELAY_VALUE); + $finish; + + end + + + if (IOBDELAY_TYPE != "DEFAULT" && IOBDELAY_TYPE != "FIXED" && IOBDELAY_TYPE != "VARIABLE") begin + + $display("Attribute Syntax Error : The attribute IOBDELAY_TYPE on ISERDES instance %m is set to %s. Legal values for this attribute are DEFAULT, FIXED or VARIABLE", IOBDELAY_TYPE); + $finish; + + end + + case (SERDES_MODE) + "MASTER" : serdes_mode_int <= 1'b0; + "SLAVE" : serdes_mode_int <= 1'b1; + default : begin + $display("Attribute Syntax Error : The attribute SERDES_MODE on ISERDES instance %m is set to %s. Legal values for this attribute are MASTER or SLAVE", SERDES_MODE); + $finish; + end + endcase // case(SERDES_MODE) + + + case (DATA_RATE) + "SDR" : data_rate_int <= 1'b1; + "DDR" : data_rate_int <= 1'b0; + default : begin + $display("Attribute Syntax Error : The attribute DATA_RATE on ISERDES instance %m is set to %s. Legal values for this attribute are SDR or DDR", DATA_RATE); + $finish; + end + endcase // case(DATA_RATE) + + + case (BITSLIP_ENABLE) + + "FALSE" : bitslip_enable_int <= 1'b0; + "TRUE" : bitslip_enable_int <= 1'b1; + default : begin + $display("Attribute Syntax Error : The attribute BITSLIP_ENABLE on ISERDES instance %m is set to %s. Legal values for this attribute are FALSE or TRUE", BITSLIP_ENABLE); + $finish; + end + + endcase // case(BITSLIP_ENABLE) + + + case (DATA_WIDTH) + + 2, 3, 4, 5, 6, 7, 8, 10 : data_width_int = DATA_WIDTH[3:0]; + default : begin + $display("Attribute Syntax Error : The attribute DATA_WIDTH on ISERDES instance %m is set to %d. Legal values for this attribute are 2, 3, 4, 5, 6, 7, 8, or 10", DATA_WIDTH); + $finish; + end + endcase // case(DATA_WIDTH) + + + case (NUM_CE) + + 1 : num_ce_int <= 1'b0; + 2 : num_ce_int <= 1'b1; + default : begin + $display("Attribute Syntax Error : The attribute NUM_CE on ISERDES instance %m is set to %d. Legal values for this attribute are 1 or 2", NUM_CE); + $finish; + end + + endcase // case(NUM_CE) + + end // initial begin + + + assign sel1 = {serdes_mode_int, data_rate_int}; + + assign selrnk3 = {1'b1, bitslip_enable_int, 2'b00}; + + assign bsmux = {bitslip_enable_int, data_rate_int, muxc}; + + + +// GSR + always @(gsr_in) begin + + if (gsr_in == 1'b1) begin + + if (IOBDELAY_TYPE == "DEFAULT") + + assign delay_count = 0; + + else + + assign delay_count = IOBDELAY_VALUE; + + assign bts_q3 = 1'b0; + assign bts_q2 = 1'b0; + assign bts_q1 = 1'b0; + assign clkdiv_int = 1'b0; + + assign ce1r = 1'b0; + assign ce2r = 1'b0; + + assign q1rnk1 = INIT_Q1; + assign q2nrnk1 = INIT_Q2; + assign q1prnk1 = INIT_Q3; + assign q2prnk1 = INIT_Q4; + + assign q3rnk1 = 1'b0; + assign q4rnk1 = 1'b0; + assign q5rnk1 = 1'b0; + assign q6rnk1 = 1'b0; + assign q6prnk1 = 1'b0; + + assign q6rnk2 = 1'b0; + assign q5rnk2 = 1'b0; + assign q4rnk2 = 1'b0; + assign q3rnk2 = 1'b0; + assign q2rnk2 = 1'b0; + assign q1rnk2 = 1'b0; + + assign q6rnk3 = 1'b0; + assign q5rnk3 = 1'b0; + assign q4rnk3 = 1'b0; + assign q3rnk3 = 1'b0; + assign q2rnk3 = 1'b0; + assign q1rnk3 = 1'b0; + + end + else if (gsr_in == 1'b0) begin + + deassign delay_count; + + deassign bts_q3; + deassign bts_q2; + deassign bts_q1; + deassign clkdiv_int; + + deassign ce1r; + deassign ce2r; + + deassign q1rnk1; + deassign q2nrnk1; + deassign q1prnk1; + deassign q2prnk1; + + deassign q3rnk1; + deassign q4rnk1; + deassign q5rnk1; + deassign q6rnk1; + deassign q6prnk1; + + deassign q6rnk2; + deassign q5rnk2; + deassign q4rnk2; + deassign q3rnk2; + deassign q2rnk2; + deassign q1rnk2; + + deassign q6rnk3; + deassign q5rnk3; + deassign q4rnk3; + deassign q3rnk3; + deassign q2rnk3; + deassign q1rnk3; + + end // if (gsr_in == 1'b0) + end // always @ (gsr_in) + + + +// IDELAY + always @(posedge clkdiv_in) begin + + if (IOBDELAY_TYPE == "VARIABLE") begin + + if (dlyrst_in == 1'b1) begin + + delay_count = IOBDELAY_VALUE; + + end + else if (dlyrst_in == 1'b0 && dlyce_in == 1'b1) begin + + if (dlyinc_in == 1'b1) begin + + if (delay_count < 63) + + delay_count = delay_count + 1; + + else if (delay_count == 63) + + delay_count = 0; + + end + else if (dlyinc_in == 1'b0) begin + + if (delay_count > 0) + + delay_count = delay_count - 1; + + else if (delay_count == 0) + + delay_count = 63; + end + + end + + end // if (IOBDELAY_TYPE == "VARIABLE") + + end // always @ (posedge clkdiv_in) + + +// delay chain + assign delay_chain_0 = d_in; + assign #SIM_TAPDELAY_VALUE delay_chain_1 = delay_chain_0; + assign #SIM_TAPDELAY_VALUE delay_chain_2 = delay_chain_1; + assign #SIM_TAPDELAY_VALUE delay_chain_3 = delay_chain_2; + assign #SIM_TAPDELAY_VALUE delay_chain_4 = delay_chain_3; + assign #SIM_TAPDELAY_VALUE delay_chain_5 = delay_chain_4; + assign #SIM_TAPDELAY_VALUE delay_chain_6 = delay_chain_5; + assign #SIM_TAPDELAY_VALUE delay_chain_7 = delay_chain_6; + assign #SIM_TAPDELAY_VALUE delay_chain_8 = delay_chain_7; + assign #SIM_TAPDELAY_VALUE delay_chain_9 = delay_chain_8; + assign #SIM_TAPDELAY_VALUE delay_chain_10 = delay_chain_9; + assign #SIM_TAPDELAY_VALUE delay_chain_11 = delay_chain_10; + assign #SIM_TAPDELAY_VALUE delay_chain_12 = delay_chain_11; + assign #SIM_TAPDELAY_VALUE delay_chain_13 = delay_chain_12; + assign #SIM_TAPDELAY_VALUE delay_chain_14 = delay_chain_13; + assign #SIM_TAPDELAY_VALUE delay_chain_15 = delay_chain_14; + assign #SIM_TAPDELAY_VALUE delay_chain_16 = delay_chain_15; + assign #SIM_TAPDELAY_VALUE delay_chain_17 = delay_chain_16; + assign #SIM_TAPDELAY_VALUE delay_chain_18 = delay_chain_17; + assign #SIM_TAPDELAY_VALUE delay_chain_19 = delay_chain_18; + assign #SIM_TAPDELAY_VALUE delay_chain_20 = delay_chain_19; + assign #SIM_TAPDELAY_VALUE delay_chain_21 = delay_chain_20; + assign #SIM_TAPDELAY_VALUE delay_chain_22 = delay_chain_21; + assign #SIM_TAPDELAY_VALUE delay_chain_23 = delay_chain_22; + assign #SIM_TAPDELAY_VALUE delay_chain_24 = delay_chain_23; + assign #SIM_TAPDELAY_VALUE delay_chain_25 = delay_chain_24; + assign #SIM_TAPDELAY_VALUE delay_chain_26 = delay_chain_25; + assign #SIM_TAPDELAY_VALUE delay_chain_27 = delay_chain_26; + assign #SIM_TAPDELAY_VALUE delay_chain_28 = delay_chain_27; + assign #SIM_TAPDELAY_VALUE delay_chain_29 = delay_chain_28; + assign #SIM_TAPDELAY_VALUE delay_chain_30 = delay_chain_29; + assign #SIM_TAPDELAY_VALUE delay_chain_31 = delay_chain_30; + assign #SIM_TAPDELAY_VALUE delay_chain_32 = delay_chain_31; + assign #SIM_TAPDELAY_VALUE delay_chain_33 = delay_chain_32; + assign #SIM_TAPDELAY_VALUE delay_chain_34 = delay_chain_33; + assign #SIM_TAPDELAY_VALUE delay_chain_35 = delay_chain_34; + assign #SIM_TAPDELAY_VALUE delay_chain_36 = delay_chain_35; + assign #SIM_TAPDELAY_VALUE delay_chain_37 = delay_chain_36; + assign #SIM_TAPDELAY_VALUE delay_chain_38 = delay_chain_37; + assign #SIM_TAPDELAY_VALUE delay_chain_39 = delay_chain_38; + assign #SIM_TAPDELAY_VALUE delay_chain_40 = delay_chain_39; + assign #SIM_TAPDELAY_VALUE delay_chain_41 = delay_chain_40; + assign #SIM_TAPDELAY_VALUE delay_chain_42 = delay_chain_41; + assign #SIM_TAPDELAY_VALUE delay_chain_43 = delay_chain_42; + assign #SIM_TAPDELAY_VALUE delay_chain_44 = delay_chain_43; + assign #SIM_TAPDELAY_VALUE delay_chain_45 = delay_chain_44; + assign #SIM_TAPDELAY_VALUE delay_chain_46 = delay_chain_45; + assign #SIM_TAPDELAY_VALUE delay_chain_47 = delay_chain_46; + assign #SIM_TAPDELAY_VALUE delay_chain_48 = delay_chain_47; + assign #SIM_TAPDELAY_VALUE delay_chain_49 = delay_chain_48; + assign #SIM_TAPDELAY_VALUE delay_chain_50 = delay_chain_49; + assign #SIM_TAPDELAY_VALUE delay_chain_51 = delay_chain_50; + assign #SIM_TAPDELAY_VALUE delay_chain_52 = delay_chain_51; + assign #SIM_TAPDELAY_VALUE delay_chain_53 = delay_chain_52; + assign #SIM_TAPDELAY_VALUE delay_chain_54 = delay_chain_53; + assign #SIM_TAPDELAY_VALUE delay_chain_55 = delay_chain_54; + assign #SIM_TAPDELAY_VALUE delay_chain_56 = delay_chain_55; + assign #SIM_TAPDELAY_VALUE delay_chain_57 = delay_chain_56; + assign #SIM_TAPDELAY_VALUE delay_chain_58 = delay_chain_57; + assign #SIM_TAPDELAY_VALUE delay_chain_59 = delay_chain_58; + assign #SIM_TAPDELAY_VALUE delay_chain_60 = delay_chain_59; + assign #SIM_TAPDELAY_VALUE delay_chain_61 = delay_chain_60; + assign #SIM_TAPDELAY_VALUE delay_chain_62 = delay_chain_61; + assign #SIM_TAPDELAY_VALUE delay_chain_63 = delay_chain_62; + + +// assign delay + always @(delay_count_int) begin + + case (delay_count_int) + 0: assign d_delay = delay_chain_0; + 1: assign d_delay = delay_chain_1; + 2: assign d_delay = delay_chain_2; + 3: assign d_delay = delay_chain_3; + 4: assign d_delay = delay_chain_4; + 5: assign d_delay = delay_chain_5; + 6: assign d_delay = delay_chain_6; + 7: assign d_delay = delay_chain_7; + 8: assign d_delay = delay_chain_8; + 9: assign d_delay = delay_chain_9; + 10: assign d_delay = delay_chain_10; + 11: assign d_delay = delay_chain_11; + 12: assign d_delay = delay_chain_12; + 13: assign d_delay = delay_chain_13; + 14: assign d_delay = delay_chain_14; + 15: assign d_delay = delay_chain_15; + 16: assign d_delay = delay_chain_16; + 17: assign d_delay = delay_chain_17; + 18: assign d_delay = delay_chain_18; + 19: assign d_delay = delay_chain_19; + 20: assign d_delay = delay_chain_20; + 21: assign d_delay = delay_chain_21; + 22: assign d_delay = delay_chain_22; + 23: assign d_delay = delay_chain_23; + 24: assign d_delay = delay_chain_24; + 25: assign d_delay = delay_chain_25; + 26: assign d_delay = delay_chain_26; + 27: assign d_delay = delay_chain_27; + 28: assign d_delay = delay_chain_28; + 29: assign d_delay = delay_chain_29; + 30: assign d_delay = delay_chain_30; + 31: assign d_delay = delay_chain_31; + 32: assign d_delay = delay_chain_32; + 33: assign d_delay = delay_chain_33; + 34: assign d_delay = delay_chain_34; + 35: assign d_delay = delay_chain_35; + 36: assign d_delay = delay_chain_36; + 37: assign d_delay = delay_chain_37; + 38: assign d_delay = delay_chain_38; + 39: assign d_delay = delay_chain_39; + 40: assign d_delay = delay_chain_40; + 41: assign d_delay = delay_chain_41; + 42: assign d_delay = delay_chain_42; + 43: assign d_delay = delay_chain_43; + 44: assign d_delay = delay_chain_44; + 45: assign d_delay = delay_chain_45; + 46: assign d_delay = delay_chain_46; + 47: assign d_delay = delay_chain_47; + 48: assign d_delay = delay_chain_48; + 49: assign d_delay = delay_chain_49; + 50: assign d_delay = delay_chain_50; + 51: assign d_delay = delay_chain_51; + 52: assign d_delay = delay_chain_52; + 53: assign d_delay = delay_chain_53; + 54: assign d_delay = delay_chain_54; + 55: assign d_delay = delay_chain_55; + 56: assign d_delay = delay_chain_56; + 57: assign d_delay = delay_chain_57; + 58: assign d_delay = delay_chain_58; + 59: assign d_delay = delay_chain_59; + 60: assign d_delay = delay_chain_60; + 61: assign d_delay = delay_chain_61; + 62: assign d_delay = delay_chain_62; + 63: assign d_delay = delay_chain_63; + default: + assign d_delay = delay_chain_0; + + endcase + end // always @ (delay_count_int) + + +// to workaround the glitches generated by mux of assign delay above + always @(delay_count) +// CR 504307 delay_count_int <= #0 delay_count; + delay_count_int <= #SIM_TAPDELAY_VALUE delay_count; + + +// Mux to O and o_delay + always @(d_in or d_delay) begin + + case (IOBDELAY) + + "NONE" : begin + o_delay <= d_in; + o_out <= d_in; + end + "IBUF" : begin + o_delay <= d_in; + o_out <= d_delay; + end + "IFD" : begin + o_delay <= d_delay; + o_out <= d_in; + end + "BOTH" : begin + o_delay <= d_delay; + o_out <= d_delay; + end + default : begin + $display("Attribute Syntax Error : The attribute IOBDELAY on ISERDES instance %m is set to %s. Legal values for this attribute are NONE, IBUF, IFD or BOTH", IOBDELAY); + $finish; + end + + endcase // case(IOBDELAY) + + end // always @ (d_in or d_delay) + + +// 1st rank of registers + +// Asynchronous Operation + always @(posedge clk_in or posedge rev_in or posedge sr_in or posedge rev_in_AND_NOT_sr_in or posedge NOT_rev_in_AND_sr_in) begin +// 1st flop in rank 1 that is full featured + + if (sr_in == 1'b1 & !(rev_in == 1'b1 & SRVAL_Q1 == 1'b1)) + + q1rnk1 <= # ffinp SRVAL_Q1; + + else if (rev_in == 1'b1) + + q1rnk1 <= # ffinp !SRVAL_Q1; + + else if (ice == 1'b1) + + q1rnk1 <= # ffinp o_delay; + + end // always @ (posedge clk_in or posedge rev_in or posedge sr_in or posedge rev_in_AND_NOT_sr_in or posedge NOT_rev_in_AND_sr_in) + + + always @(posedge clk_in or posedge sr_in) begin +// rest of flops which are not full featured and don't have clock options + + if (sr_in == 1'b1) begin + + q5rnk1 <= # ffinp 1'b0; + q6rnk1 <= # ffinp 1'b0; + q6prnk1 <= # ffinp 1'b0; + + end + else begin + + q5rnk1 <= # ffinp dataq5rnk1; + q6rnk1 <= # ffinp dataq6rnk1; + q6prnk1 <= # ffinp q6rnk1; + + end + + end // always @ (posedge clk_in or sr_in) + + +// 2nd flop in rank 1 + +// Asynchronous Operation + always @(negedge clk_in or posedge sr_in or posedge rev_in or posedge rev_in_AND_NOT_sr_in or posedge NOT_rev_in_AND_sr_in) begin + + if (sr_in == 1'b1 & !(rev_in == 1'b1 & SRVAL_Q2 == 1'b1)) + + q2nrnk1 <= # ffinp SRVAL_Q2; + + else if (rev_in == 1'b1) + + q2nrnk1 <= # ffinp !SRVAL_Q2; + + else if (ice == 1'b1) + + q2nrnk1 <= # ffinp o_delay; + + end // always @ (negedge clk_in or posedge sr_in or posedge rev_in or posedge rev_in_AND_NOT_sr_in or posedge NOT_rev_in_AND_sr_in) + + +// 4th flop in rank 1 operating on the posedge for networking +// Asynchronous Operation + always @(posedge q2pmux or posedge sr_in or posedge rev_in or posedge rev_in_AND_NOT_sr_in or posedge NOT_rev_in_AND_sr_in) begin + + if (sr_in == 1'b1 & !(rev_in == 1'b1 & SRVAL_Q4 == 1'b1)) + + q2prnk1 <= # ffinp SRVAL_Q4; + + else if (rev_in == 1'b1) + + q2prnk1 <= # ffinp !SRVAL_Q4; + + else if (ice == 1'b1) + + q2prnk1 <= # ffinp q2nrnk1; + + end // always @ (posedge q2pmux or posedge sr_in or posedge rev_in or posedge rev_in_AND_NOT_sr_in or posedge NOT_rev_in_AND_sr_in) + + +// 3rd flop in 2nd rank which is full featured and has +// a choice of being clocked by oclk or clk + +// Asynchronous Operation + always @(posedge memmux or posedge sr_in or posedge rev_in or posedge rev_in_AND_NOT_sr_in or posedge NOT_rev_in_AND_sr_in) begin + + if (sr_in == 1'b1 & !(rev_in == 1'b1 & SRVAL_Q3 == 1'b1)) + + q1prnk1 <= # ffinp SRVAL_Q3; + + else if (rev_in == 1'b1) + + q1prnk1 <= # ffinp !SRVAL_Q3; + + else if (ice == 1'b1) + + q1prnk1 <= # ffinp q1rnk1; + + end // always @ (posedge memmux or posedge sr_in or posedge rev_in or posedge rev_in_AND_NOT_sr_in or posedge NOT_rev_in_AND_sr_in) + + +// 5th and 6th flops in rank 1 which are not full featured but can be clocked +// by either clk or oclk + always @(posedge memmux or posedge sr_in) begin + + if (sr_in == 1'b1) begin + + q3rnk1 <= # ffinp 1'b0; + q4rnk1 <= # ffinp 1'b0; + + end + else begin + + q3rnk1 <= # ffinp dataq3rnk1; + q4rnk1 <= # ffinp dataq4rnk1; + + end + + end // always @ (posedge memmux or posedge sr_in) + + +////////////////////////////////////////// +// Mux elements for the 1st rank +//////////////////////////////////////// + +// Optional inverter for q2p (4th flop in rank1) + always @ (memmux) begin + + case (INTERFACE_TYPE) + + "MEMORY" : q2pmux <= # mxinp1 !memmux; + "NETWORKING" : q2pmux <= # mxinp1 memmux; + default: q2pmux <= # mxinp1 !memmux; + + endcase + + end // always @ (memmux) + + +// 4 clock muxs in first rank + always @(clk_in or oclk_in) begin + + case (INTERFACE_TYPE) + + "MEMORY" : memmux <= # mxinp1 oclk_in; + "NETWORKING" : memmux <= # mxinp1 clk_in; + default : begin + $display("Attribute Syntax Error : The attribute INTERFACE_TYPE on ISERDES instance %m is set to %s. Legal values for this attribute are MEMORY or NETWORKING", INTERFACE_TYPE); + $finish; + end + + endcase // case(INTERFACE_TYPE) + + end // always @(clk_in or oclk_in) + + + + +// data input mux for q3, q4, q5 and q6 + always @(sel1 or q1prnk1 or shiftin1_in or shiftin2_in) begin + + case (sel1) + + 2'b00 : dataq3rnk1 <= # mxinp1 q1prnk1; + 2'b01 : dataq3rnk1 <= # mxinp1 q1prnk1; + 2'b10 : dataq3rnk1 <= # mxinp1 shiftin2_in; + 2'b11 : dataq3rnk1 <= # mxinp1 shiftin1_in; + default : dataq3rnk1 <= # mxinp1 q1prnk1; + + endcase // case(sel1) + + end // always @(sel1 or q1prnk1 or SHIFTIN1 or SHIFTIN2) + + + always @(sel1 or q2prnk1 or q3rnk1 or shiftin1_in) begin + + case (sel1) + + 2'b00 : dataq4rnk1 <= # mxinp1 q2prnk1; + 2'b01 : dataq4rnk1 <= # mxinp1 q3rnk1; + 2'b10 : dataq4rnk1 <= # mxinp1 shiftin1_in; + 2'b11 : dataq4rnk1 <= # mxinp1 q3rnk1; + default : dataq4rnk1 <= # mxinp1 q2prnk1; + + endcase // case(sel1) + + end // always @(sel1 or q2prnk1 or q3rnk1 or SHIFTIN1) + + + always @(data_rate_int or q3rnk1 or q4rnk1) begin + + case (data_rate_int) + + 1'b0 : dataq5rnk1 <= # mxinp1 q3rnk1; + 1'b1 : dataq5rnk1 <= # mxinp1 q4rnk1; + default : dataq5rnk1 <= # mxinp1 q4rnk1; + + endcase // case(DATA_RATE) + + end + + + always @(data_rate_int or q4rnk1 or q5rnk1) begin + + case (data_rate_int) + + 1'b0 : dataq6rnk1 <= # mxinp1 q4rnk1; + 1'b1 : dataq6rnk1 <= # mxinp1 q5rnk1; + default : dataq6rnk1 <= # mxinp1 q5rnk1; + + endcase // case(DATA_RATE) + + end + + +// 2nd rank of registers + +// clkdivmux to pass clkdiv_int or CLKDIV to rank 2 + always @(bitslip_enable_int or clkdiv_int or clkdiv_in) begin + + case (bitslip_enable_int) + + 1'b0 : clkdivmux <= # mxinp1 clkdiv_in; + 1'b1 : clkdivmux <= # mxinp1 clkdiv_int; + default : clkdivmux <= # mxinp1 clkdiv_in; + + endcase // case(BITSLIP_ENABLE) + + end // always @(clkdiv_int or clkdiv_in) + + + +// Asynchronous Operation + always @(posedge clkdivmux or posedge sr_in) begin + + if (sr_in == 1'b1) begin + + q1rnk2 <= # ffinp 1'b0; + q2rnk2 <= # ffinp 1'b0; + q3rnk2 <= # ffinp 1'b0; + q4rnk2 <= # ffinp 1'b0; + q5rnk2 <= # ffinp 1'b0; + q6rnk2 <= # ffinp 1'b0; + + end + else begin + + q1rnk2 <= # ffinp dataq1rnk2; + q2rnk2 <= # ffinp dataq2rnk2; + q3rnk2 <= # ffinp dataq3rnk2; + q4rnk2 <= # ffinp dataq4rnk2; + q5rnk2 <= # ffinp dataq5rnk2; + q6rnk2 <= # ffinp dataq6rnk2; + + end + + end // always @ (posedge clkdivmux or sr_in) + + +// Data mux for 2nd rank of flops +// Delay for mux set to 120 + always @(bsmux or q1rnk1 or q1prnk1 or q2prnk1) begin + + casex (bsmux) + + 3'b00X : dataq1rnk2 <= # mxinp2 q2prnk1; + 3'b100 : dataq1rnk2 <= # mxinp2 q2prnk1; + 3'b101 : dataq1rnk2 <= # mxinp2 q1prnk1; + 3'bX1X : dataq1rnk2 <= # mxinp2 q1rnk1; + default : dataq1rnk2 <= # mxinp2 q2prnk1; + + endcase // casex(bsmux) + + end // always @(bsmux or q1rnk1 or q1prnk1 or q2prnk1) + + + always @(bsmux or q1prnk1 or q4rnk1) begin + + casex (bsmux) + + 3'b00X : dataq2rnk2 <= # mxinp2 q1prnk1; + 3'b100 : dataq2rnk2 <= # mxinp2 q1prnk1; + 3'b101 : dataq2rnk2 <= # mxinp2 q4rnk1; + 3'bX1X : dataq2rnk2 <= # mxinp2 q1prnk1; + default : dataq2rnk2 <= # mxinp2 q1prnk1; + + endcase // casex(bsmux) + + end // always @(bsmux or q1prnk1 or q4rnk1) + + + always @(bsmux or q3rnk1 or q4rnk1) begin + + casex (bsmux) + + 3'b00X : dataq3rnk2 <= # mxinp2 q4rnk1; + 3'b100 : dataq3rnk2 <= # mxinp2 q4rnk1; + 3'b101 : dataq3rnk2 <= # mxinp2 q3rnk1; + 3'bX1X : dataq3rnk2 <= # mxinp2 q3rnk1; + default : dataq3rnk2 <= # mxinp2 q4rnk1; + + endcase // casex(bsmux) + + end // always @(bsmux or q3rnk1 or q4rnk1) + + + always @(bsmux or q3rnk1 or q4rnk1 or q6rnk1) begin + + casex (bsmux) + + 3'b00X : dataq4rnk2 <= # mxinp2 q3rnk1; + 3'b100 : dataq4rnk2 <= # mxinp2 q3rnk1; + 3'b101 : dataq4rnk2 <= # mxinp2 q6rnk1; + 3'bX1X : dataq4rnk2 <= # mxinp2 q4rnk1; + default : dataq4rnk2 <= # mxinp2 q3rnk1; + + endcase // casex(bsmux) + + end // always @(bsmux or q3rnk1 or q4rnk1 or q6rnk1) + + + always @(bsmux or q5rnk1 or q6rnk1) begin + + casex (bsmux) + + 3'b00X : dataq5rnk2 <= # mxinp2 q6rnk1; + 3'b100 : dataq5rnk2 <= # mxinp2 q6rnk1; + 3'b101 : dataq5rnk2 <= # mxinp2 q5rnk1; + 3'bX1X : dataq5rnk2 <= # mxinp2 q5rnk1; + default : dataq5rnk2 <= # mxinp2 q6rnk1; + + endcase // casex(bsmux) + + end // always @(bsmux or q5rnk1 or q6rnk1) + + + always @(bsmux or q5rnk1 or q6rnk1 or q6prnk1) begin + + casex (bsmux) + + 3'b00X : dataq6rnk2 <= # mxinp2 q5rnk1; + 3'b100 : dataq6rnk2 <= # mxinp2 q5rnk1; + 3'b101 : dataq6rnk2 <= # mxinp2 q6prnk1; + 3'bX1X : dataq6rnk2 <= # mxinp2 q6rnk1; + default : dataq6rnk2 <= # mxinp2 q5rnk1; + + endcase // casex(bsmux) + + end // always @(bsmux or q5rnk1 or q6rnk1 or q6prnk1) + + + +// 3rd rank of registers + +// Asynchronous Operation + always @(posedge clkdiv_in or posedge sr_in) begin + + if (sr_in == 1'b1) begin + + q1rnk3 <= # ffinp 1'b0; + q2rnk3 <= # ffinp 1'b0; + q3rnk3 <= # ffinp 1'b0; + q4rnk3 <= # ffinp 1'b0; + q5rnk3 <= # ffinp 1'b0; + q6rnk3 <= # ffinp 1'b0; + + end + else begin + + q1rnk3 <= # ffinp q1rnk2; + q2rnk3 <= # ffinp q2rnk2; + q3rnk3 <= # ffinp q3rnk2; + q4rnk3 <= # ffinp q4rnk2; + q5rnk3 <= # ffinp q5rnk2; + q6rnk3 <= # ffinp q6rnk2; + + end + + end // always @ (posedge clkdiv_in or posedge sr_in) + + +// Outputs + + assign shiftout2_out = q5rnk1; + + assign shiftout1_out = q6rnk1; + + + always @(selrnk3 or q1rnk1 or q1prnk1 or q1rnk2 or q1rnk3) begin + + casex (selrnk3) + + 4'b0X00 : q1_out <= # mxinp1_my q1prnk1; + 4'b0X01 : q1_out <= # mxinp1_my q1rnk1; + 4'b0X10 : q1_out <= # mxinp1_my q1rnk1; + 4'b10XX : q1_out <= # mxinp1_my q1rnk2; + 4'b11XX : q1_out <= # mxinp1_my q1rnk3; + default : q1_out <= # mxinp1_my q1rnk2; + + endcase // casex(selrnk3) + + end // always @(selrnk3 or q1rnk1 or q1prnk1 or q1rnk2 or q1rnk3) + + + always @(selrnk3 or q2nrnk1 or q2prnk1 or q2rnk2 or q2rnk3) begin + + casex (selrnk3) + + 4'b0X00 : q2_out <= # mxinp1_my q2prnk1; + 4'b0X01 : q2_out <= # mxinp1_my q2prnk1; + 4'b0X10 : q2_out <= # mxinp1_my q2nrnk1; + 4'b10XX : q2_out <= # mxinp1_my q2rnk2; + 4'b11XX : q2_out <= # mxinp1_my q2rnk3; + default : q2_out <= # mxinp1_my q2rnk2; + + endcase // casex(selrnk3) + + end // always @(selrnk3 or q2nrnk1 or q2prnk1 or q2rnk2 or q2rnk3) + + + always @(bitslip_enable_int or q3rnk2 or q3rnk3) begin + + case (bitslip_enable_int) + + 1'b0 : q3_out <= # mxinp1_my q3rnk2; + 1'b1 : q3_out <= # mxinp1_my q3rnk3; + + endcase // case(BITSLIP_ENABLE) + + end // always @ (q3rnk2 or q3rnk3) + + + + + always @(bitslip_enable_int or q4rnk2 or q4rnk3) begin + + casex (bitslip_enable_int) + + 1'b0 : q4_out <= # mxinp1_my q4rnk2; + 1'b1 : q4_out <= # mxinp1_my q4rnk3; + + endcase // casex(BITSLIP_ENABLE) + + end // always @ (q4rnk2 or q4rnk3) + + + always @(bitslip_enable_int or q5rnk2 or q5rnk3) begin + + casex (bitslip_enable_int) + + 1'b0 : q5_out <= # mxinp1_my q5rnk2; + 1'b1 : q5_out <= # mxinp1_my q5rnk3; + + endcase // casex(BITSLIP_ENABLE) + + end // always @ (q5rnk2 or q5rnk3) + + + always @(bitslip_enable_int or q6rnk2 or q6rnk3) begin + + casex (bitslip_enable_int) + + 1'b0 : q6_out <= # mxinp1_my q6rnk2; + 1'b1 : q6_out <= # mxinp1_my q6rnk3; + + endcase // casex(BITSLIP_ENABLE) + + end // always @ (q6rnk2 or q6rnk3) + + + + + +// Set value of counter in bitslip controller + always @(data_rate_int or data_width_int) begin + + casex ({data_rate_int, data_width_int}) + + 5'b00100 : begin c23=1'b0; c45=1'b0; c67=1'b0; sel=2'b00; end + 5'b00110 : begin c23=1'b1; c45=1'b0; c67=1'b0; sel=2'b00; end + 5'b01000 : begin c23=1'b0; c45=1'b0; c67=1'b0; sel=2'b01; end + 5'b01010 : begin c23=1'b0; c45=1'b1; c67=1'b0; sel=2'b01; end + 5'b10010 : begin c23=1'b0; c45=1'b0; c67=1'b0; sel=2'b00; end + 5'b10011 : begin c23=1'b1; c45=1'b0; c67=1'b0; sel=2'b00; end + 5'b10100 : begin c23=1'b0; c45=1'b0; c67=1'b0; sel=2'b01; end + 5'b10101 : begin c23=1'b0; c45=1'b1; c67=1'b0; sel=2'b01; end + 5'b10110 : begin c23=1'b0; c45=1'b0; c67=1'b0; sel=2'b10; end + 5'b10111 : begin c23=1'b0; c45=1'b0; c67=1'b1; sel=2'b10; end + 5'b11000 : begin c23=1'b0; c45=1'b0; c67=1'b0; sel=2'b11; end + default : begin + $display("DATA_WIDTH %d and DATA_RATE %s at %t is an illegal value", DATA_WIDTH, DATA_RATE, $time); + $finish; + end + + endcase + + end // always @ (data_rate_int or data_width_int) + + + + + +/////////////////////////////////////////// +// Bit slip controler +/////////////////////////////////////////// + + +// Divide by 2 - 8 counter + +// Asynchronous Operation + always @ (posedge qr2 or negedge clk_in) begin + + if (qr2 == 1'b1) begin + + clkdiv_int <= # ffbsc 1'b0; + bts_q1 <= # ffbsc 1'b0; + bts_q2 <= # ffbsc 1'b0; + bts_q3 <= # ffbsc 1'b0; + + end + else if (qhc1 == 1'b0) begin + + bts_q3 <= # ffbsc bts_q2; + bts_q2 <= # ffbsc (!(!clkdiv_int & !bts_q2) & bts_q1); + bts_q1 <= # ffbsc clkdiv_int; + clkdiv_int <= # ffbsc mux; + + end + + end // always @ (posedge qr2 or negedge clk_in) + + +// Synchronous Operation + always @ (negedge clk_in) begin + + if (qr2 == 1'b1) begin + + clkdiv_int <= # ffbsc 1'b0; + bts_q1 <= # ffbsc 1'b0; + bts_q2 <= # ffbsc 1'b0; + bts_q3 <= # ffbsc 1'b0; + + end + else if (qhc1 == 1'b1) begin + + clkdiv_int <= # ffbsc clkdiv_int; + bts_q1 <= # ffbsc bts_q1; + bts_q2 <= # ffbsc bts_q2; + bts_q3 <= # ffbsc bts_q3; + + end + else begin + + bts_q3 <= # ffbsc bts_q2; + bts_q2 <= # ffbsc (!(!clkdiv_int & !bts_q2) & bts_q1); + bts_q1 <= # ffbsc clkdiv_int; + clkdiv_int <= # ffbsc mux; + + end + + end // always @ (negedge clk_in) + + +// 4:1 selector mux and divider selections + always @ (sel or c23 or c45 or c67 or clkdiv_int or bts_q1 or bts_q2 or bts_q3) begin + + case (sel) + + 2'b00 : mux <= # mxbsc !(clkdiv_int | (c23 & bts_q1)); + 2'b01 : mux <= # mxbsc !(bts_q1 | (c45 & bts_q2)); + 2'b10 : mux <= # mxbsc !(bts_q2 | (c67 & bts_q3)); + 2'b11 : mux <= # mxbsc !bts_q3; + default : mux <= # mxbsc !(clkdiv_int | (c23 & bts_q1)); + + endcase + + end // always @ (sel or c23 or c45 or c67 or clkdiv_int or bts_q1 or bts_q2 or bts_q3) + + + +// Bitslip control logic +// Low speed control flop + +// Asynchronous Operation + always @ (posedge qr1 or posedge clkdiv_in) begin + + if (qr1 == 1'b1) begin + + qlc1 <= # ffbsc 1'b0; + qlc2 <= # ffbsc 1'b0; + + end + else if (bitslip_in == 1'b0) begin + + qlc1 <= # ffbsc qlc1; + qlc2 <= # ffbsc 1'b0; + + end + else begin + + qlc1 <= # ffbsc !qlc1; + qlc2 <= # ffbsc (bitslip_in & mux1); + + end + + end // always @ (posedge qr1 or posedge clkdiv_in) + + +// Mux to select between sdr "1" and ddr "0" + + always @ (data_rate_int or qlc1) begin + + case (data_rate_int) + + 1'b0 : mux1 <= # mxbsc qlc1; + 1'b1 : mux1 <= # mxbsc 1'b1; + + endcase + + end + + + +// High speed control flop + +// Asynchronous Operation + always @ (posedge qr2 or negedge clk_in) begin + + if (qr2 == 1'b1) begin + + qhc1 <= # ffbsc 1'b0; + qhc2 <= # ffbsc 1'b0; + + end + else begin + + qhc1 <= # ffbsc (qlc2 & !qhc2); + qhc2 <= # ffbsc qlc2; + + end + + end // always @ (posedge qr2 or negedge clk_in) + + +// Mux that drives control line of mux in front +// of 2nd rank of flops + + always @ (data_rate_int or mux1) begin + + case (data_rate_int) + + 1'b0 : muxc <= # mxbsc mux1; + 1'b1 : muxc <= # mxbsc 1'b0; + + endcase + + end + + +// Asynchronous set flops + +// Low speed reset flop + +// Asynchronous Operation + always @ (posedge sr_in or posedge clkdiv_in) begin + + if (sr_in == 1'b1) + + qr1 <= # ffbsc 1'b1; + + else + + qr1 <= # ffbsc 1'b0; + + end // always @ (posedge sr_in or posedge clkdiv_in) + + +// High speed reset flop + +// Asynchronous Operation + always @ (posedge sr_in or negedge clk_in) begin + + if (sr_in == 1'b1) + + qr2 <= # ffbsc 1'b1; + + else + + qr2 <= # ffbsc qr1; + + end // always @ (posedge sr_in or negedge clk_in) + + +///////////////////////////////////////////// +// ICE +/////////////////////////////////////////// + + +// Asynchronous Operation + always @ (posedge clkdiv_in or posedge sr_in) begin + + if (sr_in == 1'b1) begin + + ce1r <= # ffice 1'b0; + ce2r <= # ffice 1'b0; + + end + else begin + + ce1r <= # ffice ce1_in; + ce2r <= # ffice ce2_in; + + end + + end // always @ (posedge clkdiv_in or posedge sr_in) + + + // Output mux ice + always @ (num_ce_int or clkdiv_in or ce1_in or ce1r or ce2r) begin + case ({num_ce_int, clkdiv_in}) + 2'b00 : ice <= # mxice ce1_in; + 2'b01 : ice <= # mxice ce1_in; +// 426606 + 2'b10 : ice <= # mxice ce2r; + 2'b11 : ice <= # mxice ce1r; + default : ice <= # mxice ce1_in; + endcase + end + + specify + + (CLKDIV => Q1) = (100, 100); + (CLKDIV => Q2) = (100, 100); + (CLKDIV => Q3) = (100, 100); + (CLKDIV => Q4) = (100, 100); + (CLKDIV => Q5) = (100, 100); + (CLKDIV => Q6) = (100, 100); + specparam PATHPULSE$ = 0; + + endspecify + +endmodule // ISERDES diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/ISERDES2.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/ISERDES2.v new file mode 100644 index 0000000..b214f8a --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/ISERDES2.v @@ -0,0 +1,626 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/stan/ISERDES2.v,v 1.25 2009/11/19 20:04:35 robh Exp $ +////////////////////////////////////////////////////// +// Copyright (c) 2008 Xilinx Inc. +// All Right Reserved. +////////////////////////////////////////////////////// +// +// ____ ___ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Source Synchronous Input Deserializer for the Spartan Series +// /__/ /\ Filename : ISERDES2.v +// \ \ / \ +// \__\/\__ \ +// +// Revision: Date: Comment +// 1.0: 10/10/07: Initial version. +// 1.1: 02/29/08: Changed name to ISERDES2 +// removed mc_ from signal names +// 1.2: 08/15/08: remove DQIP, DQIN per yml +// IR478802 force unused outputs 0 based on DATA_WIDTH +// IR478802 force outputs X for 1 clk after BITSLIP +// 1.3: 08/22/08: IR480003 Changed serialized input to DDLY by default +// add param to select D if desired +// 1.4: 08/27/08: Remove DDLY, DDLY2, use D input per IO SOLN TEAM +// IR481178 - phase detector moved to master +// 1.5: 09/19/08: Fix up Phase Detector +// 1.6: 09/30/08: IR489891 Change ci_int reset +// 1.7: 10/13/08: IR492154 Add CE0 as enable on FFs +// 1.8: 11/05/08: add CE0 as enable on bitslip_counter +// fixup input/output delays +// 1.9: 11/13/08: update specify block +// 1.10: 11/20/08: Connect CFB0, CFB1, DFB +// 1.11: 12/11/08: delay internal ioce by 1 ioclk +// 1.12: 01/06/09: CR502438 sync bitslip couter to clk_int +// 1.13: 02/12/09: CR507431 Input shift reg and bitslip changes to match HW +// 1.14: 02/26/09: CR510115 Changes for verilog vhdl sim differences +// 1.15: 04/22/09: CR519002 change to match HW phase detector function +// CR519029 change to match HW bitslip function +// 1.16: 06/03/09: CR523941 update phase detector logic +// CR523212 simprim IO update and match unisim +// 1.17: 07/08/09: CR524403 Add NONE to valid serdes_mode values +// 1.18: 11/16/09: CR539199 Reset logic on bitslip counter. GSR vs RST. +// End Revision +/////////////////////////////////////////////////////// + +`timescale 1 ps / 1 ps + +module ISERDES2 ( + CFB0, + CFB1, + DFB, + FABRICOUT, + INCDEC, + Q1, + Q2, + Q3, + Q4, + SHIFTOUT, + VALID, + BITSLIP, + CE0, + CLK0, + CLK1, + CLKDIV, + D, + IOCE, + RST, + SHIFTIN +); + + parameter BITSLIP_ENABLE = "FALSE"; // TRUE, FALSE + parameter DATA_RATE = "SDR"; // SDR, DDR + parameter integer DATA_WIDTH = 1; // {1..8} + parameter INTERFACE_TYPE = "NETWORKING"; // NETWORKING, NETWORKING_PIPELINED, RETIMED + parameter SERDES_MODE = "NONE"; // NONE, MASTER, SLAVE + localparam in_delay = 1; + localparam out_delay = 100; + localparam clk_delay = 0; + localparam MODULE_NAME = "ISERDES2"; + + output CFB0; + output CFB1; + output DFB; + output FABRICOUT; + output INCDEC; + output Q1; + output Q2; + output Q3; + output Q4; + output SHIFTOUT; + output VALID; + + input BITSLIP; + input CE0; + input CLK0; + input CLK1; + input CLKDIV; + input D; + input IOCE; + input RST; + input SHIFTIN; + + pulldown( BITSLIP ); + pulldown( RST ); + pullup( CE0 ); + pullup( IOCE ); + + reg BITSLIP_ENABLE_BINARY = 1'b0; + reg DATA_RATE_BINARY = 1'b0; + reg INTERFACE_TYPE_BINARY = 1'b0; + reg SERDES_MODE_BINARY = 1'b0; + reg [7:0] DATA_WIDTH_BINARY = 8'h00; + + tri0 GSR = glbl.GSR; + + reg [3:0] qout_en = 4'b0; + +// FF outputs + reg [3:0] qs, qc, qt, qg; + +// CE signals + wire ci_int; + reg ci_int_m=0; + reg ci_int_s=0; + reg ci_int_m_sync=0; + reg ci_int_s_sync=0; + reg ioce_int=0; + reg [6:0] io_ce_dly = 7'b0; + reg [2:0] bitslip_counter = 8 - DATA_WIDTH + 1; + +// Phase detector signals; + reg sample = 0; + reg E3 = 0; + reg event_occured = 0, incdec_reg = 0, valid_capture = 0, incdec_capture = 0; + reg[3:0] edge_counter = 4'h0; + reg [1:0] drp_event = 2'b10; // input from DRP + reg plus1 = 1'b0; // input from DRP + reg gvalid = 1'b1; // input from DRP + reg pre_event; + reg en_lower_baud = 1'b0; // where ever this is coming from + reg e3_f; + reg incr_d; + reg incdec_latch; // it is a full reg, just the same name as schematic + + +// Attribute settings + reg cascade_in_int = 0; + reg [1:0] qmuxSel_int = 0; + +// Internal Clock + reg clk0_int = 0; + reg clk1_int = 0; + wire clk_int; + +// Other signals + reg attr_err_flag = 0; + reg SERDES_MODE_err_flag = 0; + reg DATA_WIDTH_err_flag = 0; + reg DATA_RATE_err_flag = 0; + reg BITSLIP_ENABLE_err_flag = 0; + reg INTERFACE_TYPE_err_flag = 0; + + wire CFB0_OUTDELAY; + wire CFB1_OUTDELAY; + wire DFB_OUTDELAY; + wire FABRICOUT_OUTDELAY; + wire INCDEC_OUTDELAY; + wire Q1_OUTDELAY; + wire Q2_OUTDELAY; + wire Q3_OUTDELAY; + wire Q4_OUTDELAY; + wire SHIFTOUT_OUTDELAY; + wire VALID_OUTDELAY; + + wire BITSLIP_INDELAY; + wire CE0_INDELAY; + wire CLK0_INDELAY; + wire CLK1_INDELAY; + wire CLKDIV_INDELAY; + wire D_INDELAY; + wire GSR_INDELAY; + wire IOCE_INDELAY; + wire RST_INDELAY; + wire SHIFTIN_INDELAY; + + wire CFB0_OUT; + wire CFB1_OUT; + wire DFB_OUT; + reg FABRICOUT_OUT=0; + reg INCDEC_OUT=0; + reg Q1_OUT=0; + reg Q2_OUT=0; + reg Q3_OUT=0; + reg Q4_OUT=0; + reg SHIFTOUT_OUT=0; + reg VALID_OUT=0; + + wire BITSLIP_IN; + wire CE0_IN; + wire CLK0_IN; + wire CLK1_IN; + wire CLKDIV_IN; + wire D_IN; + wire GSR_IN; + wire IOCE_IN; + wire RST_IN; + wire SHIFTIN_IN; + +//---------------------------------------------------------------------- +//------------------------ Output Ports ------------------------------ +//---------------------------------------------------------------------- + assign #(out_delay) CFB0_OUTDELAY = CFB0_OUT; + assign #(out_delay) CFB1_OUTDELAY = CFB1_OUT; + assign #(out_delay) DFB_OUTDELAY = DFB_OUT; + assign #(out_delay) FABRICOUT_OUTDELAY = FABRICOUT_OUT; + assign #(out_delay) INCDEC_OUTDELAY = INCDEC_OUT; + assign #(out_delay) Q1_OUTDELAY = Q1_OUT; + assign #(out_delay) Q2_OUTDELAY = Q2_OUT; + assign #(out_delay) Q3_OUTDELAY = Q3_OUT; + assign #(out_delay) Q4_OUTDELAY = Q4_OUT; + assign #(out_delay) SHIFTOUT_OUTDELAY = SHIFTOUT_OUT; + assign #(out_delay) VALID_OUTDELAY = VALID_OUT; + assign CFB0 = CFB0_OUTDELAY; + assign CFB1 = CFB1_OUTDELAY; + assign DFB = DFB_OUTDELAY; + assign FABRICOUT = FABRICOUT_OUTDELAY; + assign INCDEC = INCDEC_OUTDELAY; + assign Q1 = Q1_OUTDELAY; + assign Q2 = Q2_OUTDELAY; + assign Q3 = Q3_OUTDELAY; + assign Q4 = Q4_OUTDELAY; + assign SHIFTOUT = SHIFTOUT_OUTDELAY; + assign VALID = VALID_OUTDELAY; +//---------------------------------------------------------------------- +//------------------------ Input Ports ------------------------------ +//---------------------------------------------------------------------- + assign #(clk_delay) CLK0_INDELAY = CLK0_IN; + assign #(clk_delay) CLK1_INDELAY = CLK1_IN; + assign #(clk_delay) CLKDIV_INDELAY = CLKDIV_IN; + assign #(in_delay) BITSLIP_INDELAY = BITSLIP_IN; + assign #(in_delay) CE0_INDELAY = CE0_IN; + assign #(in_delay) D_INDELAY = D_IN; + assign #(in_delay) IOCE_INDELAY = IOCE_IN; + assign #(in_delay) RST_INDELAY = RST_IN; + assign #(in_delay) GSR_INDELAY = GSR_IN; + assign #(in_delay) SHIFTIN_INDELAY = SHIFTIN_IN; + assign CLK0_IN = CLK0; + assign CLK1_IN = CLK1; + assign CLKDIV_IN = CLKDIV; + assign BITSLIP_IN = BITSLIP; + assign CE0_IN = CE0; + assign D_IN = D; + assign IOCE_IN = IOCE; + assign RST_IN = RST; + assign GSR_IN = GSR; + assign SHIFTIN_IN = SHIFTIN; + + initial begin +//------------------------------------------------- +//------ INTERFACE_TYPE Check +//------------------------------------------------- + if (INTERFACE_TYPE == "NETWORKING") qmuxSel_int <= 2'b01; + else if (INTERFACE_TYPE == "NETWORKING_PIPELINED") qmuxSel_int <= 2'b10; + else if (INTERFACE_TYPE == "RETIMED") qmuxSel_int <= 2'b11; + else begin + #1; + $display("Attribute Syntax Error : The attribute INTERFACE_TYPE on %s instance %m is set to %s. Legal values for this attribute are NETWORKING, NETWORKING_PIPELINED or RETIMED", MODULE_NAME, INTERFACE_TYPE); + INTERFACE_TYPE_err_flag = 1; + end + +//------------------------------------------------- +//------ BITSLIP_ENABLE Check +//------------------------------------------------- + if (BITSLIP_ENABLE == "TRUE") BITSLIP_ENABLE_BINARY <= 1'b1; + else if (BITSLIP_ENABLE == "FALSE") BITSLIP_ENABLE_BINARY <= 1'b0; + else begin + #1; + $display("Attribute Syntax Error : The attribute BITSLIP_ENABLE on %s instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", MODULE_NAME, BITSLIP_ENABLE); + BITSLIP_ENABLE_err_flag = 1; + end + +//------------------------------------------------- +//----- DATA_RATE Check +//------------------------------------------------- + if (DATA_RATE == "SDR") DATA_RATE_BINARY <= 1'b1; + else if (DATA_RATE == "DDR") DATA_RATE_BINARY <= 1'b0; + else begin + #1; + $display("Attribute Syntax Error : The attribute DATA_RATE on %s instance %m is set to %s. Legal values for this attribute are SDR or DDR", MODULE_NAME, DATA_RATE); + DATA_RATE_err_flag = 1; + end + +//------------------------------------------------- +//----- DATA_WIDTH check +//------------------------------------------------- + if (DATA_WIDTH == 1) DATA_WIDTH_BINARY = 8'b10000000; + else if (DATA_WIDTH == 2) DATA_WIDTH_BINARY = 8'b11000000; + else if (DATA_WIDTH == 3) DATA_WIDTH_BINARY = 8'b11100000; + else if (DATA_WIDTH == 4) DATA_WIDTH_BINARY = 8'b11110000; + else if (DATA_WIDTH == 5) DATA_WIDTH_BINARY = 8'b11111000; + else if (DATA_WIDTH == 6) DATA_WIDTH_BINARY = 8'b11111100; + else if (DATA_WIDTH == 7) DATA_WIDTH_BINARY = 8'b11111110; + else if (DATA_WIDTH == 8) DATA_WIDTH_BINARY = 8'b11111111; + else begin + #1; + $display("Attribute Syntax Error : The attribute DATA_WIDTH on %s instance %m is set to %d. Legal values for this attribute are 1, 2, 3, 4, 5, 6, 7 or 8.", MODULE_NAME, DATA_WIDTH); + DATA_WIDTH_err_flag = 1; + end + +//------------------------------------------------- +//------ SERDES_MODE Check +//------------------------------------------------- + if (SERDES_MODE == "NONE") SERDES_MODE_BINARY <= 1'b0; + else if (SERDES_MODE == "MASTER") SERDES_MODE_BINARY <= 1'b0; + else if (SERDES_MODE == "SLAVE") SERDES_MODE_BINARY <= 1'b1; + else begin + #1; + $display("Attribute Syntax Error : The attribute SERDES_MODE on %s instance %m is set to %s. Legal values for this attribute are NONE, MASTER or SLAVE", MODULE_NAME, SERDES_MODE); + SERDES_MODE_err_flag = 1; + end + +//------------------------------------------------- +//------ Other Initializations -------- +//------------------------------------------------- + if (DATA_WIDTH > 4 && SERDES_MODE == "SLAVE") + cascade_in_int <= 1; + else + cascade_in_int <= 0; + + if (SERDES_MODE == "SLAVE") + qout_en = DATA_WIDTH_BINARY[3:0]; + else + qout_en = DATA_WIDTH_BINARY[7:4]; + + if ( SERDES_MODE_err_flag || DATA_WIDTH_err_flag || + DATA_RATE_err_flag || BITSLIP_ENABLE_err_flag || + INTERFACE_TYPE_err_flag) + begin + attr_err_flag = 1; + #1; + $display("Attribute Errors detected : Simulation cannot continue. Exiting. \n"); + $finish; + end + + end // initial begin + +//----------------------------------------------------------------------------------- +//*** GLOBAL hidden GSR pin + always @(GSR_INDELAY or RST_INDELAY) begin + if ((GSR_INDELAY == 1'b1) || (RST_INDELAY == 1'b1)) begin + assign qs = 4'b0; + assign qc = 4'b0; + assign qt = 4'b0; + assign qg = 4'b0; + end + else if ((GSR_INDELAY == 1'b0) && (RST_INDELAY == 1'b0)) begin + deassign qs; + deassign qc; + deassign qt; + deassign qg; + end + end +// ===================== +// DDR doubler +// ===================== + always @(posedge CLK0_INDELAY) begin + clk0_int = 1; + #10 clk0_int = 0; + end + + generate if(DATA_RATE == "DDR") + always @(posedge CLK1_INDELAY) begin + clk1_int = 1; + #10 clk1_int = 0; + end + endgenerate + + assign clk_int = clk0_int | clk1_int; + + assign CFB0_OUT = CLK0_INDELAY; + assign CFB1_OUT = CLK1_INDELAY; + assign DFB_OUT = D_INDELAY; + +// ===================== +// IOCE sample +// ===================== + always @(posedge clk_int) begin + ioce_int <= IOCE_INDELAY; + end + +// ====================== +// Input Shift Register +// ====================== + + always @(posedge clk_int) begin + if (CE0_INDELAY) begin + if (cascade_in_int == 1'b1) qs[3] <= SHIFTIN_INDELAY; + else qs[3] <= D_INDELAY; + end + qs[2:0] <= qs[3:1]; + end + +/* + Output Input sample if this is the Slave (used by the Phase Detector in Master) + Output S0 if this is the Master (used to cascade shift register in Slave) +*/ + generate + case (SERDES_MODE) + "NONE" : always @(qs[0]) SHIFTOUT_OUT = qs[0]; + "MASTER" : always @(qs[0]) SHIFTOUT_OUT = qs[0]; + "SLAVE" : begin + always @(posedge clk_int or posedge RST_INDELAY) begin + if(RST) + sample = 0; + else if (CE0_INDELAY) + sample = #10 D_INDELAY; + end + + always @(sample) SHIFTOUT_OUT = sample; + end + endcase + endgenerate + +// ====================== +// Capture-In Registers +// ====================== + always @(posedge clk_int) begin + if(ci_int && CE0_INDELAY) begin + qc <= qs; + end + end + +// ===--=================== +// Transfer Out Registers +// ====--================== + always @(posedge clk_int) begin + if(ioce_int && CE0_INDELAY) begin + qt <= qc; + end + end + +// ====================== +// GCLK Registers +// ====================== + always @(posedge CLKDIV_INDELAY) begin + if(CE0_INDELAY) begin + qg <= qt; + end + end +// ================================================================== +// BITSLIP Function +// ================================================================== + always @(posedge clk_int) begin + if (GSR_INDELAY) + io_ce_dly <= 7'h00; + else + io_ce_dly <= {ioce_int, io_ce_dly[6:1]}; + end + + always @(posedge CLKDIV_INDELAY or posedge RST_INDELAY) begin + if (GSR_INDELAY || RST_INDELAY) + bitslip_counter <= 8 - DATA_WIDTH + 1; + else if(BITSLIP_ENABLE_BINARY && BITSLIP_INDELAY) begin + if(bitslip_counter == 3'b111) + bitslip_counter <= ~DATA_WIDTH + 1; + else + bitslip_counter <= bitslip_counter + 1; + end + end +// ================================================================== +// Generate CaptureIn (CI) signal +// ================================================================== + assign ci_int = bitslip_counter[2] ? ci_int_m_sync : ci_int_s_sync; + always @(ioce_int or io_ce_dly or bitslip_counter) + case(bitslip_counter[1:0]) + 2'b00: #0.5 ci_int_m = io_ce_dly[4]; + 2'b01: #0.5 ci_int_m = io_ce_dly[5]; + 2'b10: #0.5 ci_int_m = io_ce_dly[6]; + 2'b11: #0.5 ci_int_m = ioce_int; + endcase + + always @(io_ce_dly or bitslip_counter) + case(bitslip_counter[1:0]) + 2'b00: #0.5 ci_int_s = io_ce_dly[0]; + 2'b01: #0.5 ci_int_s = io_ce_dly[1]; + 2'b10: #0.5 ci_int_s = io_ce_dly[2]; + 2'b11: #0.5 ci_int_s = io_ce_dly[3]; + endcase + + always @(posedge clk_int) begin + ci_int_m_sync <= ci_int_m; + ci_int_s_sync <= ci_int_s; + end + + +// ================================================================== +// Phase Detector Function +// ================================================================== + + generate if ((SERDES_MODE == "MASTER") || (SERDES_MODE == "NONE")) + always @(SHIFTIN_INDELAY) E3 = SHIFTIN_INDELAY; + + always @(posedge clk_int or posedge RST_INDELAY) begin + if(RST_INDELAY) begin + event_occured <= 0; + incdec_reg <= 0; + edge_counter <= 4'h0; + valid_capture <= 0; + incdec_capture <= 0; + pre_event <= 1'b0; + e3_f <= 1'b0; + incr_d <= 1'b0; + incdec_latch <= 1'b0; + end + else if (CE0_INDELAY) begin + e3_f <= E3; + pre_event <= drp_event[1] ? (qs[3] ^ qs[2]) : (drp_event[0] ? (!qs[3] & qs[2]) : (qs[3] & !qs[2])); + event_occured <= pre_event & !((qs[3] ^ qs[2]) & en_lower_baud); + + incr_d <= qs[3] ~^ (plus1 ? e3_f : E3); + incdec_reg <= incr_d; + incdec_latch <= ioce_int ? (event_occured & incdec_reg) : + ((event_occured & !edge_counter[0]) ? incdec_reg : incdec_latch); + edge_counter <= ioce_int ? {3'h0,event_occured} : + (event_occured ? + (!(edge_counter[0] & (incdec_reg ^ incdec_latch)) ? {edge_counter[2:0],1'b1} : {1'b0,edge_counter[3:1]}) + : edge_counter); + if(ioce_int) begin + valid_capture <= #100 edge_counter[0]; + incdec_capture <= #100 incdec_latch; + end + end + end + +// +// Re-time signals into GCLK domain +// + + always @(posedge CLKDIV_INDELAY or posedge RST_INDELAY) begin + if(RST_INDELAY) begin + VALID_OUT = 0; + INCDEC_OUT = 0; + end + else if (CE0_INDELAY) begin + if (gvalid) VALID_OUT = valid_capture; + INCDEC_OUT = incdec_capture; + end + end + endgenerate + +// ============== +// Output MUXES +// ============== + always @(qs[3] or qc[3] or qt[3] or qg[3]) + if (qout_en[3] == 1'b0) Q4_OUT = 1'b0; + else + case(qmuxSel_int) + 2'b00: Q4_OUT = qs[3]; + 2'b01: Q4_OUT = qc[3]; + 2'b10: Q4_OUT = qt[3]; + 2'b11: Q4_OUT = qg[3]; + default Q4_OUT = qs[3]; + endcase + + always @(qs[2] or qc[2] or qt[2] or qg[2]) + if (qout_en[2] == 1'b0) Q3_OUT = 1'b0; + else + case(qmuxSel_int) + 2'b00: Q3_OUT = qs[2]; + 2'b01: Q3_OUT = qc[2]; + 2'b10: Q3_OUT = qt[2]; + 2'b11: Q3_OUT = qg[2]; + default Q3_OUT = qs[2]; + endcase + + always @(qs[1] or qc[1] or qt[1] or qg[1]) + if (qout_en[1] == 1'b0) Q2_OUT = 1'b0; + else + case(qmuxSel_int) + 2'b00: Q2_OUT = qs[1]; + 2'b01: Q2_OUT = qc[1]; + 2'b10: Q2_OUT = qt[1]; + 2'b11: Q2_OUT = qg[1]; + default Q2_OUT = qs[1]; + endcase + + always @(qs[0] or qc[0] or qt[0] or qg[0]) + if (qout_en[0] == 1'b0) Q1_OUT = 1'b0; + else + case(qmuxSel_int) + 2'b00: Q1_OUT = qs[0]; + 2'b01: Q1_OUT = qc[0]; + 2'b10: Q1_OUT = qt[0]; + 2'b11: Q1_OUT = qg[0]; + default Q1_OUT = qs[0]; + endcase + + specify + ( CLK0 => CFB0) = (0, 0); + ( CLK0 => Q1) = (0, 0); + ( CLK0 => Q2) = (0, 0); + ( CLK0 => Q3) = (0, 0); + ( CLK0 => Q4) = (0, 0); + ( CLK1 => CFB1) = (0, 0); + ( CLK1 => Q1) = (0, 0); + ( CLK1 => Q2) = (0, 0); + ( CLK1 => Q3) = (0, 0); + ( CLK1 => Q4) = (0, 0); + ( CLKDIV => INCDEC) = (0, 0); + ( CLKDIV => Q1) = (0, 0); + ( CLKDIV => Q2) = (0, 0); + ( CLKDIV => Q3) = (0, 0); + ( CLKDIV => Q4) = (0, 0); + ( CLKDIV => VALID) = (0, 0); + ( D => DFB) = (0, 0); + ( D => FABRICOUT) = (0, 0); + ( RST => Q1) = (0, 0); + ( RST => Q2) = (0, 0); + ( RST => Q3) = (0, 0); + ( RST => Q4) = (0, 0); + + specparam PATHPULSE$ = 0; + endspecify +endmodule // ISERDES2 diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/ISERDESE1.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/ISERDESE1.v new file mode 100644 index 0000000..4bf4ea4 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/ISERDESE1.v @@ -0,0 +1,1638 @@ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2007 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Source Synchronous Input Deserializer for Virtex6 +// /___/ /\ Filename : ISERDESE1.v +// \ \ / \ Timestamp : Tue Aug 19 13:56:05 PDT 2008 +// \___\/\___\ +// +// Revision: +// 08/19/08 - Initial version. +// 02/06/09 - CR 507371 removed OCLKB +// 02/18/09 - CR 509177 DYNCLKSEL inverts the clock when it is low +// 04/15/09 - CR 518368 Removed DYNOCLKSEL pin and DYN_OCLK_INV_EN attribute +// 04/27/09 - CR 519644 Removed DYN_OCLK_INV_EN attribute +// 06/04/09 - CR 523086 When ((DYN_CLK_INV_EN = TRUE) and (DYNCLKSEL = '0')), swap CLK and CLKB signals +// 10/09/09 - CR 535789 incorrect assignment to O port +// 12/15/09 - CR 541284/541285 Enabled OverSampling +// 01/18/10 - CR 545277 Updated CLK to Q timing due OverSampling +// 02/23/10 - CR 550912 Fixed OVERSAMPLE issues +// End Revision + +`timescale 1 ps / 1 ps + +module ISERDESE1 (O, Q1, Q2, Q3, Q4, Q5, Q6, SHIFTOUT1, SHIFTOUT2, + BITSLIP, CE1, CE2, CLK, CLKB, CLKDIV, D, DDLY, DYNCLKDIVSEL, DYNCLKSEL, OCLK, OFB, RST, SHIFTIN1, SHIFTIN2); + + + + + parameter DATA_RATE = "DDR"; + parameter integer DATA_WIDTH = 4; + parameter DYN_CLKDIV_INV_EN = "FALSE"; + parameter DYN_CLK_INV_EN = "FALSE"; + parameter INIT_Q1 = 1'b0; + parameter INIT_Q2 = 1'b0; + parameter INIT_Q3 = 1'b0; + parameter INIT_Q4 = 1'b0; + parameter INTERFACE_TYPE = "MEMORY"; + parameter integer NUM_CE = 2; + parameter IOBDELAY = "NONE"; + parameter OFB_USED = "FALSE"; + parameter SERDES_MODE = "MASTER"; + parameter SRVAL_Q1 = 1'b0; + parameter SRVAL_Q2 = 1'b0; + parameter SRVAL_Q3 = 1'b0; + parameter SRVAL_Q4 = 1'b0; + + +//------------------------------------------------------------- +// Outputs: +//------------------------------------------------------------- +// Q1: q1 output +// Q2: q2 output +// Q3: q3 output +// Q4: q4 output +// Q5: q5 output +// Q6: q6 output +// SHIFTOUT1: carry out data +// SHIFTOUT2: carry out data +// +//------------------------------------------------------------- +// Inputs: +//------------------------------------------------------------- +// D: Input from pad +// CE1: main clock enable input +// CE2: 2nd clock enable input for serdes +// BITSLIP: Manage bitslip controller +// SHIFTIN1: Carry in data +// SHIFTIN2: Carry in data +// CLK: High speed clock or strobe +// CLKB: High speed inverted clock or strobe +// Primary use is QDR +// CLKDIV: Divided clock from H clock row or OCLKDIV for memory applications +// OCLK: High speed output clock +// OCLKB: High speed inverted output clock +// Primary use is oversampling +// RST: Set/Reset control. +// CLKDIV: Low speed clock to drive counter for delay element +// +// DYNCLKSEL: Dynamically change polarity of CLK +// DYNCLKDIVSEL: Dynamically change polarity of CLKDIV +// DYNOCLKSEL: Dynamically change polarity of OCLK +// OFB: Feedback input from the OQ portion of the output +// + output O; + output Q1; + output Q2; + output Q3; + output Q4; + output Q5; + output Q6; + output SHIFTOUT1; + output SHIFTOUT2; + + input BITSLIP; + input CE1; + input CE2; + input CLK; + input CLKB; + input CLKDIV; + input D; + input DDLY; + input DYNCLKDIVSEL; + input DYNCLKSEL; + input OCLK; + input OFB; + input RST; + input SHIFTIN1; + input SHIFTIN2; + + +// + wire [1:0] SRTYPE, DDR_CLK_EDGE; + wire SERDES; + wire TFB; +// CR 541284 wire OVERSAMPLE, RANK12_DLY, RANK23_DLY; + wire RANK12_DLY, RANK23_DLY; + wire D_EMU; + assign SRTYPE = 2'b00; + assign SERDES = 1'b1; + assign DDR_CLK_EDGE = 2'b11; + assign TFB = 1'b0; +// CR 541284 assign OVERSAMPLE = 1'b0; + reg OVERSAMPLE = 1'b0; + assign RANK12_DLY = 1'b0; + assign RANK23_DLY = 1'b0; + assign D_EMU = 1'b0; + +// Output signals + reg o_out = 0, q1_out = 0, q2_out = 0, q3_out = 0, q4_out = 0, q5_out = 0, q6_out = 0; + wire shiftout1_out, shiftout2_out; + + reg q1rnk1, q2nrnk1, q1prnk1, q2prnk1, q3rnk1; + reg q4rnk1, q5rnk1, q6rnk1, q6prnk1; + reg q1rnk2, q2rnk2, q3rnk2, q4rnk2, q5rnk2, q6rnk2; + reg q1rnk3, q2rnk3, q3rnk3, q4rnk3, q5rnk3, q6rnk3; + + reg dataq3rnk1, dataq4rnk1, dataq5rnk1, dataq6rnk1; + reg dataq1rnk2, dataq2rnk2, dataq3rnk2; + reg dataq4rnk2, dataq5rnk2, dataq6rnk2; + + reg memmux, q2pmux; + + reg clkmux1, clkmux2, clkmux3, clkmux4; + + reg clkoimux, oclkoimux, clkdivoimux; + reg clkboimux, oclkboimux = 0, clkdivboimux; + + + reg clkdivmux1, clkdivmux2; + + reg ddr3clkmux; + + reg rank3clkmux; + + reg c23, c45, c67; + + reg [1:0] sel; + + wire [3:0] selrnk3; + + wire [4:0] cntr; + + wire [1:0] sel1; + + wire [3:0] bsmux; + + wire ice; + + wire muxc; + + wire clkdiv_int; + + wire [1:0] clkdivsel; + + wire bitslip_en; + + wire int_typ; + + wire [1:0] os_en; + + wire [2:0] rank2_cksel; + + reg data_in; + reg o_out_pre_fb = 0, o_delay_pre_fb = 0; + + + reg data_rate_int; + reg [3:0] data_width_int; + reg dyn_clkdiv_inv_int, dyn_clk_inv_int, dyn_oclk_inv_int; + reg ofb_used_int, num_ce_int, serdes_mode_int; + reg [1:0] interface_type_int; + + + +// Other signals + tri0 GSR = glbl.GSR; + + assign bitslip_in = BITSLIP; + assign ce1_in = CE1; + assign ce2_in = CE2; + assign clk_in = CLK; + assign clkb_in = CLKB; + assign clkdiv_in = CLKDIV; + assign d_in = D; + assign ddly_in = DDLY; + assign dynclkdivsel_in = DYNCLKDIVSEL; + assign dynclksel_in = DYNCLKSEL; +// CR 518368 +// assign dynoclksel_in = DYNOCLKSEL; + assign oclk_in = OCLK; +// CR 507371 +// assign oclkb_in = OCLKB; + assign ofb_in = OFB; + assign rst_in = RST; + assign shiftin1_in = SHIFTIN1; + assign shiftin2_in = SHIFTIN2; + + + task INTERFACE_TYPE_msg; + begin + $display("DRC Warning : The combination of INTERFACE_TYPE, DATA_RATE and DATA_WIDTH values on instance %m is not recommended.\n"); + $display("The current settings are : INTERFACE_TYPE = %s, DATA_RATE = %s and DATA_WIDTH = %d\n", INTERFACE_TYPE, DATA_RATE, DATA_WIDTH); + $display("The recommended combinations of values are :\n"); + $display("NETWORKING SDR 2, 3, 4, 5, 6, 7, 8\n"); + $display("NETWORKING DDR 4, 6, 8, 10\n"); + $display("MEMORY SDR None\n"); + $display("MEMORY DDR 4\n"); + end + endtask // INTERFACE_TYPE_msg + +// CR 541284 + task OVERSAMPLE_DDR_SDR_msg; + begin + $display("DRC Warning : The combination of INTERFACE_TYPE, DATA_RATE and DATA_WIDTH values on instance %m is not recommended.\n"); + $display("The current settings are : INTERFACE_TYPE = %s, DATA_RATE = %s and DATA_WIDTH = %d\n", INTERFACE_TYPE, DATA_RATE, DATA_WIDTH); + $display("The recommended combinations of values are :\n"); + $display("OVERSAMPLE DDR 4\n"); + end + endtask // OVERSAMPLE_DDR_SDR_msg + + initial begin +//------------------------------------------------- +//----- DATA_RATE check +//------------------------------------------------- + case (DATA_RATE) + "SDR" : data_rate_int <= 1'b1; + "DDR" : data_rate_int <= 1'b0; + default : begin + $display("Attribute Syntax Error : The attribute DATA_RATE on ISERDESE1 instance %m is set to %s. Legal values for this attribute are SDR or DDR", DATA_RATE); + $finish; + end + endcase // case(DATA_RATE) + +//------------------------------------------------- +//----- DATA_WIDTH check +//------------------------------------------------- + case (DATA_WIDTH) + + 2, 3, 4, 5, 6, 7, 8, 10 : data_width_int = DATA_WIDTH[3:0]; + default : begin + $display("Attribute Syntax Error : The attribute DATA_WIDTH on ISERDESE1 instance %m is set to %d. Legal values for this attribute are 2, 3, 4, 5, 6, 7, 8, or 10", DATA_WIDTH); + $finish; + end + endcase // case(DATA_WIDTH) + + +//------------------------------------------------- +//----- DYN_CLKDIV_INV_EN check +//------------------------------------------------- + case (DYN_CLKDIV_INV_EN) + + "FALSE" : dyn_clkdiv_inv_int <= 1'b0; + "TRUE" : dyn_clkdiv_inv_int <= 1'b1; + default : begin + $display("Attribute Syntax Error : The attribute DYN_CLKDIV_INV_EN on ISERDESE1 instance %m is set to %s. Legal values for this attribute are FALSE or TRUE", DYN_CLKDIV_INV_EN); + $finish; + end + + endcase // case(DYN_CLKDIV_INV_EN) + +//------------------------------------------------- +//----- DYN_CLK_INV_EN check +//------------------------------------------------- + case (DYN_CLK_INV_EN) + + "FALSE" : dyn_clk_inv_int <= 1'b0; + "TRUE" : dyn_clk_inv_int <= 1'b1; + default : begin + $display("Attribute Syntax Error : The attribute DYN_CLK_INV_EN on ISERDESE1 instance %m is set to %s. Legal values for this attribute are FALSE or TRUE", DYN_CLK_INV_EN); + $finish; + end + + endcase // case(DYN_CLK_INV_EN) + +//------------------------------------------------- +//----- OFB_USED check +//------------------------------------------------- + case (OFB_USED) + + "FALSE" : ofb_used_int <= 1'b0; + "TRUE" : ofb_used_int <= 1'b1; + default : begin + $display("Attribute Syntax Error : The attribute OFB_USED on ISERDESE1 instance %m is set to %s. Legal values for this attribute are FALSE or TRUE", OFB_USED); + $finish; + end + + endcase // case(OFB_USED) +//------------------------------------------------- +//----- NUM_CE check +//------------------------------------------------- + case (NUM_CE) + + 1 : num_ce_int <= 1'b0; + 2 : num_ce_int <= 1'b1; + default : begin + $display("Attribute Syntax Error : The attribute NUM_CE on ISERDESE1 instance %m is set to %d. Legal values for this attribute are 1 or 2", NUM_CE); + $finish; + end + + endcase // case(NUM_CE) + + +//------------------------------------------------- +//----- INTERFACE_TYPE check +//------------------------------------------------- + case (INTERFACE_TYPE) + "MEMORY" : begin + interface_type_int <= 2'b00; + case(DATA_RATE) + "DDR" : + case(DATA_WIDTH) + 4 : ; + default : INTERFACE_TYPE_msg; + endcase // DATA_WIDTH + default : INTERFACE_TYPE_msg; + endcase // DATA_RATE + end + "NETWORKING" : begin + interface_type_int <= 2'b01; + case(DATA_RATE) + "SDR" : + case(DATA_WIDTH) + 2, 3, 4, 5, 6, 7, 8 : ; + default : INTERFACE_TYPE_msg; + endcase // DATA_WIDTH + "DDR" : + case(DATA_WIDTH) + 4, 6, 8, 10 : ; + default : INTERFACE_TYPE_msg; + endcase // DATA_WIDTH + default : ; + endcase // DATA_RATE + end + "MEMORY_QDR" : + interface_type_int <= 2'b10; + "MEMORY_DDR3" : + interface_type_int <= 2'b11; +// CR 541284 + "OVERSAMPLE" : begin + OVERSAMPLE <= 1'b1; + interface_type_int <= 2'b01; + case(DATA_RATE) + "SDR" : OVERSAMPLE_DDR_SDR_msg; + "DDR" : + case(DATA_WIDTH) + 4 : ; + default : OVERSAMPLE_DDR_SDR_msg; + endcase // DATA_WIDTH + default : ; + endcase // DATA_RATE + end + + default : begin + $display("Attribute Syntax Error : The attribute INTERFACE_TYPE on ISERDESE1 instance %m is set to %s. Legal values for this attribute are MEMORY, NETWORKING, MEMORY_QDR, MEMORY_DDR3 or OVERSAMPLE", INTERFACE_TYPE); + $finish; + end + endcase // INTERFACE_TYPE + +//------------------------------------------------- +//----- SERDES_MODE check +//------------------------------------------------- + case (SERDES_MODE) + "MASTER" : serdes_mode_int <= 1'b0; + "SLAVE" : serdes_mode_int <= 1'b1; + default : begin + $display("Attribute Syntax Error : The attribute SERDES_MODE on ISERDESE1 instance %m is set to %s. Legal values for this attribute are MASTER or SLAVE", SERDES_MODE); + $finish; + end + endcase // case(SERDES_MODE) + +//------------------------------------------------- + end // initial begin + +//------------------------------------------------- +assign int_typ = interface_type_int[1] | interface_type_int[0]; + +assign bitslip_en = interface_type_int[0]; + +// CR 541284 +assign os_en = {int_typ, OVERSAMPLE}; // {int_typ, OVERSAMPLE}; + +assign sel1 = {serdes_mode_int, data_rate_int}; // {SERDES_MODE,DATA_RATE}; + +// CR 541284 +assign rank2_cksel = {interface_type_int, OVERSAMPLE}; // {interface_type_int, OVERSAMPLE}; + +assign selrnk3 = {1'b1, bitslip_en, 2'b11}; // {SERDES,bitslip_en, DDR_CLK_EDGE}; + +// CR 541284 +assign bsmux = {bitslip_en, data_rate_int, muxc, OVERSAMPLE}; // {bitslip_en,DATA_RATE,muxc, OVERSAMPLE}; + +assign cntr = {data_rate_int, data_width_int}; // {DATA_RATE,DATA_WIDTH}; + +// Parameter declarations for delays + + localparam ffinp = 300; + localparam mxinp1 = 60; + localparam mxinp2 = 120; + +// Delay parameters + localparam ht0 = 800; + localparam fftco = 300; + localparam mxdly = 60; + localparam cnstdly = 80; + + +// GSR + + always @(GSR) begin + if (GSR == 1'b1) begin + assign q1rnk1 = INIT_Q1; + assign q2nrnk1 = INIT_Q2; + assign q1prnk1 = INIT_Q3; + assign q2prnk1 = INIT_Q4; + + assign q3rnk1 = 1'b0; + assign q4rnk1 = 1'b0; + assign q5rnk1 = 1'b0; + assign q6rnk1 = 1'b0; + assign q6prnk1 = 1'b0; + + assign q6rnk2 = 1'b0; + assign q5rnk2 = 1'b0; + assign q4rnk2 = 1'b0; + assign q3rnk2 = 1'b0; + assign q2rnk2 = 1'b0; + assign q1rnk2 = 1'b0; + + assign q6rnk3 = 1'b0; + assign q5rnk3 = 1'b0; + assign q4rnk3 = 1'b0; + assign q3rnk3 = 1'b0; + assign q2rnk3 = 1'b0; + assign q1rnk3 = 1'b0; + assign ddr3clkmux = 1'b1; + end + else if (GSR == 1'b0) begin + + deassign q1rnk1; + deassign q2nrnk1; + deassign q1prnk1; + deassign q2prnk1; + + deassign q3rnk1; + deassign q4rnk1; + deassign q5rnk1; + deassign q6rnk1; + deassign q6prnk1; + + deassign q6rnk2; + deassign q5rnk2; + deassign q4rnk2; + deassign q3rnk2; + deassign q2rnk2; + deassign q1rnk2; + + deassign q6rnk3; + deassign q5rnk3; + deassign q4rnk3; + deassign q3rnk3; + deassign q2rnk3; + deassign q1rnk3; + deassign ddr3clkmux; + + end // if (GSR == 1'b0) + end // always @ (GSR) + +//------------------------------------------------- +// Input to ISERDES +//------------------------------------------------- + + always @(d_in or ddly_in) begin + + case (IOBDELAY) + + "NONE" : begin + o_out_pre_fb <= d_in; + o_delay_pre_fb <= d_in; + + end + "IBUF" : begin + o_out_pre_fb <= ddly_in; + o_delay_pre_fb <= d_in; + end + "IFD" : begin + o_out_pre_fb <= d_in; + o_delay_pre_fb <= ddly_in; + end + "BOTH" : begin + o_out_pre_fb <= ddly_in; + o_delay_pre_fb <= ddly_in; + end + default : begin + $display("Attribute Syntax Error : The attribute IOBDELAY on ISERDESE1 instance %m is set to %s. Legal values for this attribute are NONE, IBUF, IFD or BOTH", IOBDELAY); + $finish; + end + + endcase // case(IOBDELAY) + + end // always @ (d_in or ddly_in) + + generate + case (OFB_USED) + "TRUE" : always @(ofb_in) + begin + o_out <= ofb_in; + data_in <= ofb_in; + end + "FALSE" : begin + always @(o_out_pre_fb) o_out <= o_out_pre_fb; + always @(o_delay_pre_fb) data_in <= o_delay_pre_fb; + end + endcase + endgenerate + +//------------------------------------------------------ +// High Speed Clock Generation and Polarity Control +//------------------------------------------------------ + +// Optional inverter for clk + generate + case (DYN_CLK_INV_EN) + "FALSE" : always @(clk_in) clkoimux <= clk_in; + "TRUE" : +// CR 523086 + always @ (dynclksel_in or clk_in or clkb_in) begin + case (dynclksel_in) + 1'b0: clkoimux <= clkb_in; + 1'b1: clkoimux <= clk_in; + endcase + end + endcase + endgenerate + +// Optional inverter for clkb + generate + case (DYN_CLK_INV_EN) + "FALSE" : always @(clkb_in) clkboimux <= clkb_in; + "TRUE" : +// CR 523086 + always @ (dynclksel_in or clkb_in or clk_in) begin + case (dynclksel_in) + 1'b0: clkboimux <= clk_in; + 1'b1: clkboimux <= clkb_in; + endcase + end + endcase + endgenerate + +// CR 518368 +// Optional inverter for oclk +/* + generate + case (DYN_OCLK_INV_EN) + "FALSE" : always @(oclk_in) oclkoimux <= oclk_in; + "TRUE" : + always @ (dynoclksel_in or oclk_in) begin + case (dynoclksel_in) + 1'b0: oclkoimux <= oclk_in; + 1'b1: oclkoimux <= ~oclk_in; + endcase + end + endcase + endgenerate +*/ + + always @(oclk_in) oclkoimux <= oclk_in; + +//CR 507371 +// Optional inverter for oclkb +/* + generate + case (DYN_OCLK_INV_EN) + "FALSE" : always @(oclkb_in) oclkboimux <= oclkb_in; + "TRUE" : + always @ (dynoclksel_in or oclkb_in) begin + case (dynoclksel_in) + 1'b0: oclkboimux <= oclkb_in; + 1'b1: oclkboimux <= ~oclkb_in; + endcase + end + endcase + endgenerate +*/ + +// Optional inverter for clkdiv + generate + case (DYN_CLKDIV_INV_EN) + "FALSE" : always @(clkdiv_in) clkdivoimux <= clkdiv_in; + "TRUE" : + always @ (dynclkdivsel_in or clkdiv_in) begin + case (dynclkdivsel_in) + 1'b0: clkdivoimux <= clkdiv_in; + 1'b1: clkdivoimux <= ~clkdiv_in; + endcase + end + endcase + endgenerate + +// clkmux for 2nd flop in rank1 + generate + case (INTERFACE_TYPE) + "MEMORY" : always @(clkboimux) clkmux2 <= clkboimux; + "NETWORKING" : always @(clkboimux) clkmux2 <= clkboimux; + "MEMORY_QDR" : always @(clkboimux) clkmux2 <= clkboimux; + "MEMORY_DDR3" : always @(clkboimux) clkmux2 <= clkboimux; + "OVERSAMPLE" : always @(clkboimux) clkmux2 <= clkboimux; // need for OVERSAMPLE CR fix 02/23/10 + endcase + endgenerate + +// clkmux for 3rd flop in rank1 + always @ (os_en or oclkoimux or clkoimux) begin + case (os_en) + 2'b00: clkmux3 <= oclkoimux; + 2'b01: clkmux3 <= oclkoimux; + 2'b10: clkmux3 <= clkoimux; + 2'b11: clkmux3 <= oclkoimux; + endcase + end + +//clkmux for 4th flop in rank1 + always @ (os_en or oclkoimux or clkoimux or oclkboimux) begin + case(os_en) + 2'b00: clkmux4 <= ~oclkoimux; + 2'b01: clkmux4 <= ~oclkoimux; + 2'b10: clkmux4 <= clkoimux; + 2'b11: clkmux4 <= ~oclkoimux; // changed from grounded oclkboimux to ~oclkoimux -- need for OVERSAMPLE CR fix 02/23/10 + default: clkmux4 <= ~oclkoimux; + endcase + end + +// Rest of clock muxs in first rank + always @ (int_typ or oclkoimux or clkoimux) begin + case (int_typ) + 1'b0: memmux <= # mxinp1 oclkoimux; + 1'b1: memmux <= # mxinp1 clkoimux; + default: memmux <= # mxinp1 oclkoimux; + endcase + end + +//------------------------------------------------- +// 1st rank of registers -- Synchronous Operation +//------------------------------------------------- +// Uses the positive edge of CLK +// This includes the 1st, 6th, 7th and 8th flops in rank 1 +// These flops are designated as q1rnk1, q5rnk1, q6rnk1 +// and q6prnk1. q1rnk1 is full featured. +// q5rnk1, q6rnk1 and q6prnk1 are not. + + always @ (posedge clkoimux) begin + if(rst_in == 1'b1) begin + q1rnk1 <= # ffinp SRVAL_Q1; + end + else if (ice == 1'b1) begin + q1rnk1 <= # ffinp data_in; + end + + if(rst_in == 1'b1) begin + q5rnk1 <= # ffinp 1'b0; + q6rnk1 <= # ffinp 1'b0; + q6prnk1 <= # ffinp 1'b0; + end + else begin + q5rnk1 <= # ffinp dataq5rnk1; + q6rnk1 <= # ffinp dataq6rnk1; + q6prnk1 <= # ffinp q6rnk1; + end + end // always @ (posedge clkoimux) + +// 2nd flop in rank 1, designated q2nrnk1, that is full featured +// and operates only on the negative edge of CLK or positive +// edge of CLKB + + always @ (posedge clkmux2) begin + if(rst_in == 1'b1) + q2nrnk1 <= # ffinp SRVAL_Q2; + else if (ice == 1'b1) + q2nrnk1 <= # ffinp data_in; + end // always @ (posedge clkmux2) + +// 3rd, 4th, 5th and 6th flops in rank1 +// The 3rd and 4th flops are full featured while +// The 5th and 6th flops only have reset. The flops are +// designated as q1prnk1, q2prnk1, q3rnk1 and q4rnk1. +// These 4 flops can be driven from CLK or OCLK. This +// function is implemented by the clk mux called +// "memmux". Flops q1prnk1, q3rnk1 and q4rnk1 are +// driven of the positive edge of memmux. Flop q2prnk1 +// is further driven by the optional inverter mux named +// "q2pmux" that allows it to be driven off either the +// positive or negative edge of memmux. +// + + always @ (posedge clkmux3) begin + if(rst_in == 1'b1) + q1prnk1 <= # ffinp SRVAL_Q3; + else if (ice == 1'b1) +// q1prnk1 <= # ffinp q1rnk1; + q1prnk1 <= # ffinp (OVERSAMPLE? data_in : q1rnk1); + end // always @ (posedge clkmux3) + +// 5th and 6th flops in rank 1 which are not full featured but can be clocked +// by either clk or oclk + + always @ (posedge memmux) begin + if(rst_in == 1'b1) begin + q3rnk1 <= # ffinp 1'b0; + q4rnk1 <= # ffinp 1'b0; + end + else begin + q3rnk1 <= # ffinp dataq3rnk1; + q4rnk1 <= # ffinp dataq4rnk1; + end + end // always @ (posedge clkmux2) + +// 4th flop in rank 1 (q2prnk1). This is a full featured flop +// that for memory is clocked on the negative edge of OCLK +// and for networking is clocked on the positive edge of CLK + + + always @ (posedge clkmux4) begin + if(rst_in == 1'b1) + q2prnk1 <= # ffinp SRVAL_Q4; + else if (ice == 1'b1) +// q2prnk1 <= # ffinp q2nrnk1; + q2prnk1 <= # ffinp (OVERSAMPLE? data_in : q2nrnk1); + end // always @ (posedge clkmux4) + +//------------------------------------------------- +// Mux elements for the 1st rank +//------------------------------------------------- + +// data input mux for q3, q4, q5 and q6 + + always @ (sel1 or q1prnk1 or shiftin1_in or shiftin2_in) begin + case (sel1) + 2'b00: dataq3rnk1 <= # mxinp1 q1prnk1; + 2'b01: dataq3rnk1 <= # mxinp1 q1prnk1; + 2'b10: dataq3rnk1 <= # mxinp1 shiftin2_in; + 2'b11: dataq3rnk1 <= # mxinp1 shiftin1_in; + default: dataq3rnk1 <= # mxinp1 q1prnk1; + endcase // case(sel1) + end // always @ (sel1 or q1prnk1 or shiftin1_in or shiftin2_in) + + always @ (sel1 or q2prnk1 or q3rnk1 or shiftin1_in) begin + case (sel1) + 2'b00: dataq4rnk1 <= # mxinp1 q2prnk1; + 2'b01: dataq4rnk1 <= # mxinp1 q3rnk1; + 2'b10: dataq4rnk1 <= # mxinp1 shiftin1_in; + 2'b11: dataq4rnk1 <= # mxinp1 q3rnk1; + default: dataq4rnk1 <= # mxinp1 q2prnk1; + endcase // case(sel1) + end // always @ (sel1 or q2prnk1 or q3rnk1 or shiftin1_in) + + always @ (data_rate_int or q3rnk1 or q4rnk1) begin + case (data_rate_int) + 1'b0: dataq5rnk1 <= # mxinp1 q3rnk1; + 1'b1: dataq5rnk1 <= # mxinp1 q4rnk1; + default: dataq5rnk1 <= # mxinp1 q4rnk1; + endcase // case(data_rate_int) + end // always @ (data_rate_int or q3rnk1 or q4rnk1) + + always @ (data_rate_int or q4rnk1 or q5rnk1) begin + case (data_rate_int) + 1'b0: dataq6rnk1 <= # mxinp1 q4rnk1; + 1'b1: dataq6rnk1 <= # mxinp1 q5rnk1; + default: dataq6rnk1 <= # mxinp1 q5rnk1; + endcase // case(data_rate_int) + end // always @ (data_rate_int or q4rnk1 or q5rnk1) + +//------------------------------------------------- +// 2nd rank of registers -- Synchronous Operation +//------------------------------------------------- + + +// DDR3 Divide By 2 CKT + + always @ (negedge clkoimux) begin + if(rst_in) + ddr3clkmux <= 1'b0; + else if (INTERFACE_TYPE == "MEMORY_DDR3") + ddr3clkmux <= ~ddr3clkmux; + else + ddr3clkmux <= ddr3clkmux; + end // always @ (negedge clkoimux) + +// clkdivmuxs to pass clkdiv_int or CLKDIV to rank 2 + always @ (rank2_cksel or clkdiv_int or clkdivoimux or clkoimux or cntr) begin + case (rank2_cksel) + 3'b000: clkdivmux1 <= # mxinp1 clkdivoimux; + 3'b010: begin + case (cntr) + 5'b00100: clkdivmux1 <= # mxinp1 ~clkdiv_int; + 5'b10010: clkdivmux1 <= # mxinp1 ~clkdiv_int; + default: clkdivmux1 <= # mxinp1 clkdiv_int; + endcase + end + 3'b100: clkdivmux1 <= # mxinp1 clkdivoimux; + 3'b110: #1 clkdivmux1 <= # mxinp1 ddr3clkmux; + 3'b011: clkdivmux1 <= # mxinp1 clkoimux; +// default: $display("INTERFACE_TYPE %b and OVERSAMPLE %b at %t is an illegal value", INTERFACE_TYPE, OVERSAMPLE, $time); + endcase // case (rank2_cksel) + end // always @ (rank2_cksel or clkdiv_int or clkdivoimux or clkoimux or cntr) + + +// clkdivmuxs to pass clkdiv_int or CLKDIV to rank 2 + always @ (rank2_cksel or clkdiv_int or clkdivoimux or clkoimux or oclkoimux or cntr) begin + case (rank2_cksel) + 3'b000: clkdivmux2 <= # mxinp1 clkdivoimux; + 3'b010: begin + case (cntr) + 5'b00100: clkdivmux2 <= # mxinp1 ~clkdiv_int; + 5'b10010: clkdivmux2 <= # mxinp1 ~clkdiv_int; + default: clkdivmux2 <= # mxinp1 clkdiv_int; + endcase + end + 3'b100: clkdivmux2 <= # mxinp1 clkdivoimux; + 3'b110: #1 clkdivmux2 <= #mxinp1 ddr3clkmux; + 3'b011: clkdivmux2 <= # mxinp1 oclkoimux; +// default: $display("INTERFACE_TYPE %b and OVERSAMPLE %b at %t is an illegal value", INTERFACE_TYPE, OVERSAMPLE, $time); + endcase // case (rank2_cksel) + end // always @ (rank2_cksel or clkdiv_int or clkdivoimux or clkoimux) + +// Synchronous Operation + always @ (posedge clkdivmux1) begin + if(rst_in == 1'b1) begin + q1rnk2 <= # ffinp 1'b0; + q3rnk2 <= # ffinp 1'b0; + q5rnk2 <= # ffinp 1'b0; + q6rnk2 <= # ffinp 1'b0; + end + else begin + q1rnk2 <= # ffinp dataq1rnk2; + q3rnk2 <= # ffinp dataq3rnk2; + q5rnk2 <= # ffinp dataq5rnk2; + q6rnk2 <= # ffinp dataq6rnk2; + end + end // always @ (posedge clkdivmux1) + + + always @ (posedge clkdivmux2) begin + if(rst_in == 1'b1) begin + q2rnk2 <= # ffinp 1'b0; + q4rnk2 <= # ffinp 1'b0; + end + else begin + q2rnk2 <= # ffinp dataq2rnk2; + q4rnk2 <= # ffinp dataq4rnk2; + end + end // always @ (posedge clkdivmux2) + + +// Data mux for 2nd rank of flops +// Delay for mux set to 120 + + always @ (bsmux or q1rnk1 or q1prnk1 or q2prnk1) begin + casex (bsmux) + 4'b00X0: dataq1rnk2 <= # mxinp2 q2prnk1; + 4'b1000: dataq1rnk2 <= # mxinp2 q2prnk1; + 4'b1010: dataq1rnk2 <= # mxinp2 q1prnk1; + 4'bX1X0: dataq1rnk2 <= # mxinp2 q1rnk1; + 4'bXXX1: dataq1rnk2 <= # mxinp2 q1rnk1; + default: dataq1rnk2 <= # mxinp2 q2prnk1; + endcase // casex (bsmux) + end // always @ (bsmux or q1rnk1 or q1prnk1 or q2prnk1) + + always @ (bsmux or q1prnk1 or q4rnk1 or q2nrnk1) begin + casex (bsmux) + 4'b00X0: dataq2rnk2 <= # mxinp2 q1prnk1; + 4'b1000: dataq2rnk2 <= # mxinp2 q1prnk1; + 4'b1010: dataq2rnk2 <= # mxinp2 q4rnk1; + 4'bX1X0: dataq2rnk2 <= # mxinp2 q1prnk1; + 4'bXXX1: dataq2rnk2 <= # mxinp2 q2nrnk1; + default: dataq2rnk2 <= # mxinp2 q1prnk1; + endcase // casex (bsmux) + end // always @ (bsmux or q1prnk1 or q4rnk1 or q2nrnk1) + + always @ (bsmux or q3rnk1 or q4rnk1 or q1prnk1) begin + casex (bsmux) + 4'b00X0: dataq3rnk2 <= # mxinp2 q4rnk1; + 4'b1000: dataq3rnk2 <= # mxinp2 q4rnk1; + 4'b1010: dataq3rnk2 <= # mxinp2 q3rnk1; + 4'bX1X0: dataq3rnk2 <= # mxinp2 q3rnk1; + 4'bXXX1: dataq3rnk2 <= # mxinp2 q1prnk1; + default: dataq3rnk2 <= # mxinp2 q4rnk1; + endcase // casex (bsmux) + end // always @ (bsmux or q3rnk1 or q4rnk1 or q1prnk1) + + always @ (bsmux or q3rnk1 or q4rnk1 or q6rnk1 or q2prnk1) begin + casex (bsmux) + 4'b00X0: dataq4rnk2 <= # mxinp2 q3rnk1; + 4'b1000: dataq4rnk2 <= # mxinp2 q3rnk1; + 4'b1010: dataq4rnk2 <= # mxinp2 q6rnk1; + 4'bX1X0: dataq4rnk2 <= # mxinp2 q4rnk1; + 4'bXXX1: dataq4rnk2 <= # mxinp2 q2prnk1; + default: dataq4rnk2 <= # mxinp2 q3rnk1; + endcase // casex (bsmux) + end // always @ (bsmux or q3rnk1 or q4rnk1 or q6rnk1 or q2prnk1) + + always @ (bsmux or q5rnk1 or q6rnk1) begin + casex (bsmux) + 4'b00X0: dataq5rnk2 <= # mxinp2 q6rnk1; + 4'b1000: dataq5rnk2 <= # mxinp2 q6rnk1; + 4'b1010: dataq5rnk2 <= # mxinp2 q5rnk1; + 4'bX1X0: dataq5rnk2 <= # mxinp2 q5rnk1; + default: dataq5rnk2 <= # mxinp2 q6rnk1; + endcase // casex (bsmux) + end // always @ (bsmux or q5rnk1 or q6rnk1) + + always @ (bsmux or q5rnk1 or q6rnk1 or q6prnk1) begin + casex (bsmux) + 4'b00X0: dataq6rnk2 <= # mxinp2 q5rnk1; + 4'b1000: dataq6rnk2 <= # mxinp2 q5rnk1; + 4'b1010: dataq6rnk2 <= # mxinp2 q6prnk1; + 4'bX1X0: dataq6rnk2 <= # mxinp2 q6rnk1; + default: dataq6rnk2 <= # mxinp2 q5rnk1; + endcase // casex (bsmux) + end // always @ (bsmux or q5rnk1 or q6rnk1 or q6prnk1) + + + +//------------------------------------------------- +// 3rd rank of registers -- Synchronous Operation +//------------------------------------------------- + + +// clkdivmuxs to pass CLK or CLKDIV to rank 3 + always @ (OVERSAMPLE or clkdivoimux or clkoimux) begin + case (OVERSAMPLE) + 1'b0: rank3clkmux <= # mxinp1 clkdivoimux; + 1'b1: rank3clkmux <= # mxinp1 clkoimux; + default: rank3clkmux <= # mxinp1 clkdivoimux; + endcase // case (OVERSAMPLE) + end // always @ (OVERSAMPLE or clkdivoimux or clkoimux) + +// Synchronous Operation + + always @ (posedge rank3clkmux) begin + if(rst_in == 1'b1) begin + q1rnk3 <= # ffinp 1'b0; + q2rnk3 <= # ffinp 1'b0; + q3rnk3 <= # ffinp 1'b0; + q4rnk3 <= # ffinp 1'b0; + q5rnk3 <= # ffinp 1'b0; + q6rnk3 <= # ffinp 1'b0; + end + else begin + q1rnk3 <= # ffinp q1rnk2; + q2rnk3 <= # ffinp q2rnk2; + q3rnk3 <= # ffinp q3rnk2; + q4rnk3 <= # ffinp q4rnk2; + q5rnk3 <= # ffinp q5rnk2; + q6rnk3 <= # ffinp q6rnk2; + end + end // always @ (posedge rank3clkmux) + +//------------------------------------------------- +// Outputs +//------------------------------------------------- + + assign shiftout1_out = q6rnk1; + assign shiftout2_out = q5rnk1; + + always @ (selrnk3 or q1rnk1 or q1prnk1 or q1rnk2 or q1rnk3) begin + casex (selrnk3) + 4'b0X00: q1_out <= # mxinp1 q1prnk1; + 4'b0X01: q1_out <= # mxinp1 q1rnk1; + 4'b0X10: q1_out <= # mxinp1 q1rnk1; + 4'b10XX: q1_out <= # mxinp1 q1rnk2; + 4'b11XX: q1_out <= # mxinp1 q1rnk3; + default: q1_out <= # mxinp1 q1rnk2; + endcase + end + + always @ (selrnk3 or q2nrnk1 or q2prnk1 or q2rnk2 or q2rnk3) begin + casex (selrnk3) + 4'b0X00: q2_out <= # mxinp1 q2prnk1; + 4'b0X01: q2_out <= # mxinp1 q2prnk1; + 4'b0X10: q2_out <= # mxinp1 q2nrnk1; + 4'b10XX: q2_out <= # mxinp1 q2rnk2; + 4'b11XX: q2_out <= # mxinp1 q2rnk3; + default: q2_out <= # mxinp1 q2rnk2; + endcase + end + + always @ (bitslip_en or q3rnk2 or q3rnk3) begin + case (bitslip_en) + 1'b0: q3_out <= # mxinp1 q3rnk2; + 1'b1: q3_out <= # mxinp1 q3rnk3; + default: q3_out <= # mxinp1 q3rnk2; + endcase + end + + always @ (bitslip_en or q4rnk2 or q4rnk3) begin + casex (bitslip_en) + 1'b0: q4_out <= # mxinp1 q4rnk2; + 1'b1: q4_out <= # mxinp1 q4rnk3; + default: q4_out <= # mxinp1 q4rnk2; + endcase + end + + always @ (bitslip_en or q5rnk2 or q5rnk3) begin + casex (bitslip_en) + 1'b0: q5_out <= # mxinp1 q5rnk2; + 1'b1: q5_out <= # mxinp1 q5rnk3; + default: q5_out <= # mxinp1 q5rnk2; + endcase + end + + always @ (bitslip_en or q6rnk2 or q6rnk3) begin + casex (bitslip_en) + 1'b0: q6_out <= # mxinp1 q6rnk2; + 1'b1: q6_out <= # mxinp1 q6rnk3; + default: q6_out <= # mxinp1 q6rnk2; + endcase + end + +// Instantiate Bitslip controller +bscntrl_iserdese1_vlog bsc (.c23(c23), .c45(c45), .c67(c67), .sel(sel), + .DATA_RATE(data_rate_int), .bitslip(bitslip_in), + .clk(!clkoimux), .clkdiv(clkdivoimux), .r(rst_in), + .clkdiv_int(clkdiv_int), .muxc(muxc) + ); + +// Set value of counter in bitslip controller +always @ (cntr or c23 or c45 or c67 or sel) +begin + casex (cntr) + 5'b00100: begin c23=1'b0; c45=1'b0; c67=1'b0; sel=2'b00; end + 5'b00110: begin c23=1'b1; c45=1'b0; c67=1'b0; sel=2'b00; end + 5'b01000: begin c23=1'b0; c45=1'b0; c67=1'b0; sel=2'b01; end + 5'b01010: begin c23=1'b0; c45=1'b1; c67=1'b0; sel=2'b01; end + 5'b10010: begin c23=1'b0; c45=1'b0; c67=1'b0; sel=2'b00; end + 5'b10011: begin c23=1'b1; c45=1'b0; c67=1'b0; sel=2'b00; end + 5'b10100: begin c23=1'b0; c45=1'b0; c67=1'b0; sel=2'b01; end + 5'b10101: begin c23=1'b0; c45=1'b1; c67=1'b0; sel=2'b01; end + 5'b10110: begin c23=1'b0; c45=1'b0; c67=1'b0; sel=2'b10; end + 5'b10111: begin c23=1'b0; c45=1'b0; c67=1'b1; sel=2'b10; end + 5'b11000: begin c23=1'b0; c45=1'b0; c67=1'b0; sel=2'b11; end + default: $display("DATA_WIDTH %b and DATA_RATE %b at %t is an illegal value", DATA_WIDTH, DATA_RATE, $time); + endcase + +end + + +// Instantiate clock enable circuit +ice_iserdese1_vlog cec (.ce1(ce1_in), .ce2(ce2_in), .NUM_CE(num_ce_int), + .clkdiv(rank3clkmux), .r(rst_in), .ice(ice) + ); + + assign O = o_out; + assign Q1 = q1_out; + assign Q2 = q2_out; + assign Q3 = q3_out; + assign Q4 = q4_out; + assign Q5 = q5_out; + assign Q6 = q6_out; + assign SHIFTOUT1 = shiftout1_out; + assign SHIFTOUT2 = shiftout2_out; + + specify + + (CLK => Q1) = (100:100:100, 100:100:100); + (CLK => Q2) = (100:100:100, 100:100:100); + (CLK => Q3) = (100:100:100, 100:100:100); + (CLK => Q4) = (100:100:100, 100:100:100); + (CLK => Q5) = (100:100:100, 100:100:100); + (CLK => Q6) = (100:100:100, 100:100:100); + + (CLKDIV => Q1) = (100:100:100, 100:100:100); + (CLKDIV => Q2) = (100:100:100, 100:100:100); + (CLKDIV => Q3) = (100:100:100, 100:100:100); + (CLKDIV => Q4) = (100:100:100, 100:100:100); + (CLKDIV => Q5) = (100:100:100, 100:100:100); + (CLKDIV => Q6) = (100:100:100, 100:100:100); + (D => O) = (0, 0); + (DDLY => O) = (0, 0); + (OFB => O) = (0, 0); + + + specparam PATHPULSE$ = 0; + + endspecify + +endmodule // ISERDESE1 + +`timescale 1ps/1ps +/////////////////////////////////////////////////////// +// +// Bit slip controller +// +// +//////////////////////////////////////////////////////// +// +// +// +///////////////////////////////////////////////////////// +// +// Inputs: +// bitslip: Activates bitslip controller +// clk: High speed forwarded clock +// clkdiv: Low speed from clock divider in H clock row +// r: Generates resest for flops +// +// +// Outputs: +// clkdiv_int: Generates clock same frequency as clkdiv +// muxc: Controls mux in 2nd rank for DDR bitslip +// +// +// Programmable options +// +// DATA_RATE: Selects between sdr "1" and ddr "0" operation +// c23: Selector between divide by 2 and divide by 3 +// c45: Selector between divide by 4 and divide by 5 +// c67: Selector between divide by 6 and divide by 7 +// sel: Mux selector with following table: +// 00: Divide by 2 or 3 +// 01: Divide by 4 or 5 +// 10: Divide by 6 or 7 +// 11: Divide by 8 +// +//////////////////////////////////////////////////////////////////////////////// +// + +module bscntrl_iserdese1_vlog (c23, c45, c67, sel, DATA_RATE, + bitslip, + clk, clkdiv, r, + clkdiv_int,muxc + ); + +// programmable points +input c23, c45, c67, DATA_RATE; + +input [1:0] sel; + +// regular inputs + +input clk, r, clkdiv; + +input bitslip; + +// Programmable Test Attributes +wire SRTYPE; +assign SRTYPE = 1'b0; + +// outputs +output clkdiv_int, muxc; + + +reg clkdiv_int; + +reg q1, q2, q3; + +reg mux; + +reg qhc1, qhc2, qlc1, qlc2; + +reg qr1, qr2; + +reg mux1, muxc; + + +////////////////////////////////////////////////// +// +// Delay parameter assignment +// +///////////////////////////////////////////////// + +localparam ffbsc = 300; +localparam mxbsc = 60; + + +//////////////////////////////////////////////////// +// +// Initialization of flops through GSR +// +/////////////////////////////////////////////////// + +`ifdef SW_NO_ISERDES_TEST +`else +tri0 GSR = glbl.GSR; + +always @(GSR) +begin + if (GSR) + begin + assign q3 = 1'b0; + assign q2 = 1'b0; + assign q1 = 1'b0; + assign clkdiv_int = 1'b0; + end + else + begin + deassign q3; + deassign q2; + deassign q1; + deassign clkdiv_int; + end +end +`endif +////////////////////////////////////////////////////////////////// +///////////////////////////////////////////////////////////////// + + +/////////////////////////////// +// +// Divide by 2 - 8 counter +// +//////////////////////////////// + +// Asynchronous Operation +always @ (posedge qr2 or posedge clk) +begin + if (qr2 & SRTYPE) + begin + clkdiv_int <= # ffbsc 1'b0; + q1 <= # ffbsc 1'b0; + q2 <= # ffbsc 1'b0; + q3 <= # ffbsc 1'b0; + end + else if (qhc1 & SRTYPE) + begin + clkdiv_int <= # ffbsc clkdiv_int; + q1 <= # ffbsc q1; + q2 <= # ffbsc q2; + q3 <= # ffbsc q3; + end + else if (SRTYPE) + begin + q3 <= # ffbsc q2; + q2 <= # ffbsc (!(!clkdiv_int & !q2) & q1); + q1 <= # ffbsc clkdiv_int; + clkdiv_int <= # ffbsc mux; + end +end +// Synchronous Operation +always @ (posedge clk) +begin + if (qr2 & !SRTYPE) + begin + clkdiv_int <= # ffbsc 1'b0; + q1 <= # ffbsc 1'b0; + q2 <= # ffbsc 1'b0; + q3 <= # ffbsc 1'b0; + end + else if (qhc1 & !SRTYPE) + begin + clkdiv_int <= # ffbsc clkdiv_int; + q1 <= # ffbsc q1; + q2 <= # ffbsc q2; + q3 <= # ffbsc q3; + end + else if (!SRTYPE) + begin + q3 <= # ffbsc q2; + q2 <= # ffbsc (!(!clkdiv_int & !q2) & q1); + q1 <= # ffbsc clkdiv_int; + clkdiv_int <= # ffbsc mux; + end +end + + + +////////////////////////////////////////// +// 4:1 selector mux and divider selections +////////////////////////////////////////// +always @ (sel or c23 or c45 or c67 or clkdiv_int or q1 or q2 or q3) + begin + case (sel) + 2'b00: mux <= # mxbsc !(clkdiv_int | (c23 & q1)); + 2'b01: mux <= # mxbsc !(q1 | (c45 & q2)); + 2'b10: mux <= # mxbsc !(q2 | (c67 & q3)); + 2'b11: mux <= # mxbsc !q3; + default: mux <= # mxbsc !(clkdiv_int | (c23 & q1)); + endcase + end + +/////////////////////////////////// +// +// Bitslip control logic +// +/////////////////////////////////// + + +///////////////////// +// Low speed control flop +/////////////////////// + +// Asynchronous Operation +always @ (posedge qr1 or posedge clkdiv) +begin + begin + if (qr1 & SRTYPE) + begin + qlc1 <= # ffbsc 1'b0; + qlc2 <= # ffbsc 1'b0; + end + else if (!bitslip & SRTYPE) + begin + qlc1 <= # ffbsc qlc1; + qlc2 <= # ffbsc 1'b0; + end + else if (SRTYPE) + begin + qlc1 <= # ffbsc !qlc1; + qlc2 <= # ffbsc (bitslip & mux1); + end + end +end +// Synchronous Operation +always @ (posedge clkdiv) +begin + begin + if (qr1 & !SRTYPE) + begin + qlc1 <= # ffbsc 1'b0; + qlc2 <= # ffbsc 1'b0; + end + else if (!bitslip & !SRTYPE) + begin + qlc1 <= # ffbsc qlc1; + qlc2 <= # ffbsc 1'b0; + end + else if (!SRTYPE) + begin + qlc1 <= # ffbsc !qlc1; + qlc2 <= # ffbsc (bitslip & mux1); + end + end +end + + +///////////////////////////////////////////// +// Mux to select between sdr "1" and ddr "0" +///////////////////////////////////////////// +always @ (qlc1 or DATA_RATE) + begin + case (DATA_RATE) + 1'b0: mux1 <= # mxbsc qlc1; + 1'b1: mux1 <= # mxbsc 1'b1; + + endcase + end + +///////////////////////// +// High speed control flop +///////////////////////// + +// Asynchronous Operation +always @ (posedge qr2 or posedge clk) +begin + begin + if (qr2 & SRTYPE) + begin + qhc1 <= # ffbsc 1'b0; + qhc2 <= # ffbsc 1'b0; + end + else if (SRTYPE) + begin + qhc1 <= # ffbsc (qlc2 & !qhc2); + qhc2 <= # ffbsc qlc2; + end + end +end +// Synchronous Operation +always @ (posedge clk) +begin + begin + if (qr2 & !SRTYPE) + begin + qhc1 <= # ffbsc 1'b0; + qhc2 <= # ffbsc 1'b0; + end + else if (!SRTYPE) + begin + qhc1 <= # ffbsc (qlc2 & !qhc2); + qhc2 <= # ffbsc qlc2; + end + end +end + + + +///////////////////////////////////////////// +// Mux that drives control line of mux in front +// of 2nd rank of flops +////////////////////////////////////////// +always @ (mux1 or DATA_RATE) +begin + case (DATA_RATE) + 1'b0 : muxc <= # mxbsc mux1; + 1'b1 : muxc <= # mxbsc 1'b0; + endcase +end + +///////////////////////////// +// Asynchronous set flops +///////////////////////////// + +///////////////////// +// Low speed reset flop +/////////////////////// + +// Asynchronous Operation +always @ (posedge r or posedge clkdiv) + begin + if (r & SRTYPE) + begin + qr1 <= # ffbsc 1'b1; + end + else if (SRTYPE) + begin + qr1 <= # ffbsc 1'b0; + end + end +// Synchronous Operation +always @ (posedge clkdiv) + begin + if (r & !SRTYPE) + begin + qr1 <= # ffbsc 1'b1; + end + else if (!SRTYPE) + begin + qr1 <= # ffbsc 1'b0; + end + end + +///////////////////// +// High speed reset flop +/////////////////////// +// Asynchronous Operation +always @ (posedge r or posedge clk) + begin + if (r & SRTYPE) + begin + qr2 <= # ffbsc 1'b1; + end + else if (SRTYPE) + begin + qr2 <= # ffbsc qr1; + end + end +// Synchronous Operation +always @ (posedge clk) + begin + if (r & !SRTYPE) + begin + qr2 <= # ffbsc 1'b1; + end + else if (!SRTYPE) + begin + qr2 <= # ffbsc qr1; + end + end + + +/////////////////////// + +endmodule + + + +`timescale 1ps/1ps +// +/////////////////////////////////////////////////////// +// +// Input Clock Enable Circuit +// +// +//////////////////////////////////////////////////////// +// +// +// +///////////////////////////////////////////////////////// +// +// Inputs: ce1: 1st and default clock enable +// ce2: 2nd clock enable used for serdes memory cases +// r: Synchronous reset +// clkdiv: Low speed output clock generated off the DCM +// +// +// +// Outputs: intce: Clock enable +// +// +// Programmable options +// +// NUM_CE: 0: ce1 only, 1: ce1 and ce2 +// +// +// +//////////////////////////////////////////////////////////////////////////////// +// + +module ice_iserdese1_vlog (ce1, ce2, NUM_CE, + clkdiv, r, + ice + ); + + +// regular inputs + +input ce1, ce2; + +input clkdiv, r; + +// programmable points +input NUM_CE; + + +// programmable test points +// Synchronus RST +wire SRTYPE; +assign SRTYPE = 1'b0; + +// output +output ice; + + +reg ce1r, ce2r, ice; + +wire [1:0] cesel; + +assign cesel = {NUM_CE,clkdiv}; + + + +////////////////////////////////////////////////// +// +// Delay parameters +// +///////////////////// + +localparam ffice = 300; +localparam mxice = 60; + + +//////////////////////////////////////////////////// +// +// Initialization of flops through GSR +// +/////////////////////////////////////////////////// + +tri0 GSR = glbl.GSR; + +always @(GSR) +begin + if (GSR) + begin + assign ce1r = 1'b0; + assign ce2r = 1'b0; + end + else + begin + deassign ce1r; + deassign ce2r; + end +end +////////////////////////////////////////////////////////////////// +///////////////////////////////////////////////////////////////// + + + + +// Asynchronous Operation +always @ (posedge clkdiv or posedge r) + begin + if (r & SRTYPE) + begin + ce1r <= # ffice 1'b0; + ce2r <= # ffice 1'b0; + end + else if (SRTYPE) + begin + ce1r <= # ffice ce1; + ce2r <= # ffice ce2; + end + end +// Synchronous Operation +always @ (posedge clkdiv) + begin + if (r & !SRTYPE) + begin + ce1r <= # ffice 1'b0; + ce2r <= # ffice 1'b0; + end + else if (!SRTYPE) + begin + ce1r <= # ffice ce1; + ce2r <= # ffice ce2; + end + end + +// Output mux +always @ (cesel or ce1 or ce1r or ce2r) + begin + case (cesel) + 2'b00: ice <= # mxice ce1; + 2'b01: ice <= # mxice ce1; + 2'b10: ice <= # mxice ce2r; + 2'b11: ice <= # mxice ce1r; + default: ice <= # mxice ce1; + endcase + end + +/////////////////////// + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/ISERDES_NODELAY.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/ISERDES_NODELAY.v new file mode 100644 index 0000000..fc9ae2c --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/ISERDES_NODELAY.v @@ -0,0 +1,1118 @@ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2005 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Source Synchronous Input Deserializer without delay element +// /___/ /\ Filename : ISERDES_NODELAY.v +// \ \ / \ Timestamp : Fri Oct 21 10:31:45 PDT 2005 +// \___\/\___\ +// +// Revision: +// 10/21/05 - Initial version. +// 02/28/06 - CR 226003 -- Added Parameter Types (integer/real) +// 06/16/06 - Added new port CLKB +// 10/13/06 - Fixed CR 426606 +// 07/07/07 - Added wire declaration for internal signals +// 09/10/07 - CR 447760 Added Strict DRC for BITSLIP and INTERFACE_TYPE combinations +// 12/03/07 - CR 454107 Added DRC warnings for INTERFACE_TYPE, DATA_RATE and DATA_WIDTH combinations +// End Revision + +`timescale 1 ps / 1 ps + +module ISERDES_NODELAY (Q1, Q2, Q3, Q4, Q5, Q6, SHIFTOUT1, SHIFTOUT2, + BITSLIP, CE1, CE2, CLK, CLKB, CLKDIV, D, OCLK, RST, SHIFTIN1, SHIFTIN2); + + parameter BITSLIP_ENABLE = "FALSE"; + parameter DATA_RATE = "DDR"; + parameter integer DATA_WIDTH = 4; + parameter INIT_Q1 = 1'b0; + parameter INIT_Q2 = 1'b0; + parameter INIT_Q3 = 1'b0; + parameter INIT_Q4 = 1'b0; + parameter INTERFACE_TYPE = "MEMORY"; + parameter integer NUM_CE = 2; + parameter SERDES_MODE = "MASTER"; + + output Q1; + output Q2; + output Q3; + output Q4; + output Q5; + output Q6; + output SHIFTOUT1; + output SHIFTOUT2; + + input BITSLIP; + input CE1; + input CE2; + input CLK; + input CLKB; + input CLKDIV; + input D; + input OCLK; + input RST; + input SHIFTIN1; + input SHIFTIN2; + + localparam SRVAL_Q1 = 1'b0; + localparam SRVAL_Q2 = 1'b0; + localparam SRVAL_Q3 = 1'b0; + localparam SRVAL_Q4 = 1'b0; + + tri0 GSR = glbl.GSR; + + reg [1:0] sel; + reg [3:0] data_width_int; + reg bts_q1, bts_q2, bts_q3; + reg c23, c45, c67; + reg ce1r, ce2r; + reg dataq1rnk2, dataq2rnk2, dataq3rnk2; + reg dataq3rnk1, dataq4rnk1, dataq5rnk1, dataq6rnk1; + reg dataq4rnk2, dataq5rnk2, dataq6rnk2; + reg ice, memmux, q2pmux; + reg mux, mux1, muxc; + reg notifier; + reg clkdiv_int, clkdivmux; + reg o_out = 0, q1_out = 0, q2_out = 0, q3_out = 0, q4_out = 0, q5_out = 0, q6_out = 0; + reg q1rnk2, q2rnk2, q3rnk2, q4rnk2, q5rnk2, q6rnk2; + reg q1rnk3, q2rnk3, q3rnk3, q4rnk3, q5rnk3, q6rnk3; + reg q4rnk1, q5rnk1, q6rnk1, q6prnk1; + reg num_ce_int; + reg qr1, qr2, qhc1, qhc2, qlc1, qlc2; + reg shiftn2_in, shiftn1_in; + reg q1rnk1, q2nrnk1, q1prnk1, q2prnk1, q3rnk1; + reg serdes_mode_int, data_rate_int, bitslip_enable_int; + + wire o_delay; + + reg rev_in = 0; + + wire shiftout1_out, shiftout2_out; + wire [1:0] sel1; + wire [2:0] bsmux; + wire [3:0] selrnk3; + + wire bitslip_in; + wire ce1_in; + wire ce2_in; + wire clk_in; + wire clkb_in; + wire clkdiv_in; + wire d_in; + wire dlyce_in; + wire dlyinc_in; + wire dlyrst_in; + wire gsr_in; + wire oclk_in; + wire sr_in; + wire shiftin1_in; + wire shiftin2_in; + + buf b_q1 (Q1, q1_out); + buf b_q2 (Q2, q2_out); + buf b_q3 (Q3, q3_out); + buf b_q4 (Q4, q4_out); + buf b_q5 (Q5, q5_out); + buf b_q6 (Q6, q6_out); + buf b_shiftout1 (SHIFTOUT1, shiftout1_out); + buf b_shiftout2 (SHIFTOUT2, shiftout2_out); + + buf b_bitslip (bitslip_in, BITSLIP); + buf b_ce1 (ce1_in, CE1); + buf b_ce2 (ce2_in, CE2); + buf b_clk (clk_in, CLK); + buf b_clkb (clkb_in, CLKB); + buf b_clkdiv (clkdiv_in, CLKDIV); + buf b_d (d_in, D); + buf b_gsr (gsr_in, GSR); + buf b_oclk (oclk_in, OCLK); + buf b_sr (sr_in, RST); + buf b_shiftin1 (shiftin1_in, SHIFTIN1); + buf b_shiftin2 (shiftin2_in, SHIFTIN2); + + // workaround for XSIM + wire rev_in_AND_NOT_sr_in = rev_in & !sr_in; + wire NOT_rev_in_AND_sr_in = !rev_in & sr_in; + +// WARNING !!!: This model may not work properly if the +// following parameters are changed. + +// xilinx_internal_parameter on + + +// Parameter declarations for delays + parameter ffinp = 300; + parameter mxinp1 = 60; + parameter mxinp2 = 120; + +// Delay parameters + + parameter ffice = 300; + parameter mxice = 60; + +// Delay parameter assignment + + parameter ffbsc = 300; + parameter mxbsc = 60; + + parameter mxinp1_my = 0; + +// xilinx_internal_parameter off + +// --------CR 454107 DRC Warning -- INTERFACE_TYPE / DATA_RATE / DATA_WIDTH combinations ------------------ + task CR454107_msg; + begin + $display("DRC Warning : The combination of INTERFACE_TYPE, DATA_RATE and DATA_WIDTH values on instance %m is not recommended.\n"); + $display("The current settings are : INTERFACE_TYPE = %s, DATA_RATE = %s and DATA_WIDTH = %d\n", INTERFACE_TYPE, DATA_RATE, DATA_WIDTH); + $display("The recommended combinations of values are :\n"); + $display("NETWORKING SDR 2, 3, 4, 5, 6, 7, 8\n"); + $display("NETWORKING DDR 4, 6, 8, 10\n"); + $display("MEMORY SDR None\n"); + $display("MEMORY DDR 4\n"); + end + endtask // CR454107_msg + + initial begin + +// --------CR 454107 DRC Warning -- INTERFACE_TYPE / DATA_RATE / DATA_WIDTH combinations ------------------ + case (INTERFACE_TYPE) + "NETWORKING" : + case(DATA_RATE) + "SDR" : + case(DATA_WIDTH) + 2, 3, 4, 5, 6, 7, 8 : ; + default : CR454107_msg; + endcase // DATA_WIDTH + "DDR" : + case(DATA_WIDTH) + 4, 6, 8, 10 : ; + default : CR454107_msg; + endcase // DATA_WIDTH + default : ; + endcase // DATA_RATE + "MEMORY" : + case(DATA_RATE) + "DDR" : + case(DATA_WIDTH) + 4 : ; + default : CR454107_msg; + endcase // DATA_WIDTH + default : CR454107_msg; + endcase // DATA_RATE + default : ; + endcase // INTERFACE_TYPE + +// --------CR 447760 DRC -- BITSLIP - INTERFACE_TYPE combination ------------------ + + if((INTERFACE_TYPE == "MEMORY") && (BITSLIP_ENABLE == "TRUE")) begin + $display("Attribute Syntax Error: BITSLIP_ENABLE is currently set to TRUE when INTERFACE_TYPE is set to MEMORY. This is an invalid configuration."); + $finish; + end + else if((INTERFACE_TYPE == "NETWORKING") && (BITSLIP_ENABLE == "FALSE")) begin + $display ("Attribute Syntax Error: BITSLIP_ENABLE is currently set to FALSE when INTERFACE_TYPE is set to NETWORKING. If BITSLIP is not intended to be used, please set BITSLIP_ENABLE to TRUE and tie the BITSLIP port to ground."); + $finish; + end + +//------------------------------------------------------------------------------------ + + case (SERDES_MODE) + "MASTER" : serdes_mode_int <= 1'b0; + "SLAVE" : serdes_mode_int <= 1'b1; + default : begin + $display("Attribute Syntax Error : The attribute SERDES_MODE on ISERDES_NODELAY instance %m is set to %s. Legal values for this attribute are MASTER or SLAVE", SERDES_MODE); + $finish; + end + endcase // case(SERDES_MODE) + + + case (DATA_RATE) + "SDR" : data_rate_int <= 1'b1; + "DDR" : data_rate_int <= 1'b0; + default : begin + $display("Attribute Syntax Error : The attribute DATA_RATE on ISERDES_NODELAY instance %m is set to %s. Legal values for this attribute are SDR or DDR", DATA_RATE); + $finish; + end + endcase // case(DATA_RATE) + + + case (BITSLIP_ENABLE) + + "FALSE" : bitslip_enable_int <= 1'b0; + "TRUE" : bitslip_enable_int <= 1'b1; + default : begin + $display("Attribute Syntax Error : The attribute BITSLIP_ENABLE on ISERDES_NODELAY instance %m is set to %s. Legal values for this attribute are FALSE or TRUE", BITSLIP_ENABLE); + $finish; + end + + endcase // case(BITSLIP_ENABLE) + + + case (DATA_WIDTH) + + 2, 3, 4, 5, 6, 7, 8, 10 : data_width_int = DATA_WIDTH[3:0]; + default : begin + $display("Attribute Syntax Error : The attribute DATA_WIDTH on ISERDES_NODELAY instance %m is set to %d. Legal values for this attribute are 2, 3, 4, 5, 6, 7, 8, or 10", DATA_WIDTH); + $finish; + end + endcase // case(DATA_WIDTH) + + + case (NUM_CE) + + 1 : num_ce_int <= 1'b0; + 2 : num_ce_int <= 1'b1; + default : begin + $display("Attribute Syntax Error : The attribute NUM_CE on ISERDES_NODELAY instance %m is set to %d. Legal values for this attribute are 1 or 2", NUM_CE); + $finish; + end + + endcase // case(NUM_CE) + + end // initial begin + + + assign sel1 = {serdes_mode_int, data_rate_int}; + + assign selrnk3 = {1'b1, bitslip_enable_int, 2'b00}; + + assign bsmux = {bitslip_enable_int, data_rate_int, muxc}; + + + +// GSR + always @(gsr_in) begin + + if (gsr_in == 1'b1) begin + + assign bts_q3 = 1'b0; + assign bts_q2 = 1'b0; + assign bts_q1 = 1'b0; + assign clkdiv_int = 1'b0; + + assign ce1r = 1'b0; + assign ce2r = 1'b0; + + assign q1rnk1 = INIT_Q1; + assign q2nrnk1 = INIT_Q2; + assign q1prnk1 = INIT_Q3; + assign q2prnk1 = INIT_Q4; + + assign q3rnk1 = 1'b0; + assign q4rnk1 = 1'b0; + assign q5rnk1 = 1'b0; + assign q6rnk1 = 1'b0; + assign q6prnk1 = 1'b0; + + assign q6rnk2 = 1'b0; + assign q5rnk2 = 1'b0; + assign q4rnk2 = 1'b0; + assign q3rnk2 = 1'b0; + assign q2rnk2 = 1'b0; + assign q1rnk2 = 1'b0; + + assign q6rnk3 = 1'b0; + assign q5rnk3 = 1'b0; + assign q4rnk3 = 1'b0; + assign q3rnk3 = 1'b0; + assign q2rnk3 = 1'b0; + assign q1rnk3 = 1'b0; + + end + else if (gsr_in == 1'b0) begin + + + deassign bts_q3; + deassign bts_q2; + deassign bts_q1; + deassign clkdiv_int; + + deassign ce1r; + deassign ce2r; + + deassign q1rnk1; + deassign q2nrnk1; + deassign q1prnk1; + deassign q2prnk1; + + deassign q3rnk1; + deassign q4rnk1; + deassign q5rnk1; + deassign q6rnk1; + deassign q6prnk1; + + deassign q6rnk2; + deassign q5rnk2; + deassign q4rnk2; + deassign q3rnk2; + deassign q2rnk2; + deassign q1rnk2; + + deassign q6rnk3; + deassign q5rnk3; + deassign q4rnk3; + deassign q3rnk3; + deassign q2rnk3; + deassign q1rnk3; + + end // if (gsr_in == 1'b0) + end // always @ (gsr_in) + + + +// to workaround the glitches generated by mux of assign delay above +// always @(delay_count) +// delay_count_int <= #0 delay_count; + + assign o_delay = d_in; + +// 1st rank of registers + +// Asynchronous Operation + always @(posedge clk_in or posedge rev_in or posedge sr_in or posedge rev_in_AND_NOT_sr_in or posedge NOT_rev_in_AND_sr_in) begin +// 1st flop in rank 1 that is full featured + + if (sr_in == 1'b1 & !(rev_in == 1'b1 & SRVAL_Q1 == 1'b1)) + + q1rnk1 <= # ffinp SRVAL_Q1; + + else if (rev_in == 1'b1) + + q1rnk1 <= # ffinp !SRVAL_Q1; + + else if (ice == 1'b1) + + q1rnk1 <= # ffinp o_delay; + + end // always @ (posedge clk_in or posedge rev_in or posedge sr_in or posedge rev_in_AND_NOT_sr_in or posedge NOT_rev_in_AND_sr_in) + + + always @(posedge clk_in or posedge sr_in) begin +// rest of flops which are not full featured and don't have clock options + + if (sr_in == 1'b1) begin + + q5rnk1 <= # ffinp 1'b0; + q6rnk1 <= # ffinp 1'b0; + q6prnk1 <= # ffinp 1'b0; + + end + else begin + + q5rnk1 <= # ffinp dataq5rnk1; + q6rnk1 <= # ffinp dataq6rnk1; + q6prnk1 <= # ffinp q6rnk1; + + end + + end // always @ (posedge clk_in or sr_in) + + +// 2nd flop in rank 1 + +// Asynchronous Operation + always @(posedge clkb_in or posedge sr_in or posedge rev_in or posedge rev_in_AND_NOT_sr_in or posedge NOT_rev_in_AND_sr_in) begin + + if (sr_in == 1'b1 & !(rev_in == 1'b1 & SRVAL_Q2 == 1'b1)) + + q2nrnk1 <= # ffinp SRVAL_Q2; + + else if (rev_in == 1'b1) + + q2nrnk1 <= # ffinp !SRVAL_Q2; + + else if (ice == 1'b1) + + q2nrnk1 <= # ffinp o_delay; + + end // always @ (posedge clkb_in or posedge sr_in or posedge rev_in or posedge rev_in_AND_NOT_sr_in or posedge NOT_rev_in_AND_sr_in) + + +// 4th flop in rank 1 operating on the posedge for networking +// Asynchronous Operation + always @(posedge q2pmux or posedge sr_in or posedge rev_in or posedge rev_in_AND_NOT_sr_in or posedge NOT_rev_in_AND_sr_in) begin + + if (sr_in == 1'b1 & !(rev_in == 1'b1 & SRVAL_Q4 == 1'b1)) + + q2prnk1 <= # ffinp SRVAL_Q4; + + else if (rev_in == 1'b1) + + q2prnk1 <= # ffinp !SRVAL_Q4; + + else if (ice == 1'b1) + + q2prnk1 <= # ffinp q2nrnk1; + + end // always @ (posedge q2pmux or posedge sr_in or posedge rev_in or posedge rev_in_AND_NOT_sr_in or posedge NOT_rev_in_AND_sr_in) + + +// 3rd flop in 2nd rank which is full featured and has +// a choice of being clocked by oclk or clk + +// Asynchronous Operation + always @(posedge memmux or posedge sr_in or posedge rev_in or posedge rev_in_AND_NOT_sr_in or posedge NOT_rev_in_AND_sr_in) begin + + if (sr_in == 1'b1 & !(rev_in == 1'b1 & SRVAL_Q3 == 1'b1)) + + q1prnk1 <= # ffinp SRVAL_Q3; + + else if (rev_in == 1'b1) + + q1prnk1 <= # ffinp !SRVAL_Q3; + + else if (ice == 1'b1) + + q1prnk1 <= # ffinp q1rnk1; + + end // always @ (posedge memmux or posedge sr_in or posedge rev_in or posedge rev_in_AND_NOT_sr_in or posedge NOT_rev_in_AND_sr_in) + + +// 5th and 6th flops in rank 1 which are not full featured but can be clocked +// by either clk or oclk + always @(posedge memmux or posedge sr_in) begin + + if (sr_in == 1'b1) begin + + q3rnk1 <= # ffinp 1'b0; + q4rnk1 <= # ffinp 1'b0; + + end + else begin + + q3rnk1 <= # ffinp dataq3rnk1; + q4rnk1 <= # ffinp dataq4rnk1; + + end + + end // always @ (posedge memmux or posedge sr_in) + + +////////////////////////////////////////// +// Mux elements for the 1st rank +//////////////////////////////////////// + +// Optional inverter for q2p (4th flop in rank1) + always @ (memmux) begin + + case (INTERFACE_TYPE) + + "MEMORY" : q2pmux <= # mxinp1 !memmux; + "NETWORKING" : q2pmux <= # mxinp1 memmux; + default: q2pmux <= # mxinp1 !memmux; + + endcase + + end // always @ (memmux) + + +// 4 clock muxs in first rank + always @(clk_in or oclk_in) begin + + case (INTERFACE_TYPE) + + "MEMORY" : memmux <= # mxinp1 oclk_in; + "NETWORKING" : memmux <= # mxinp1 clk_in; + default : begin + $display("Attribute Syntax Error : The attribute INTERFACE_TYPE on ISERDES_NODELAY instance %m is set to %s. Legal values for this attribute are MEMORY or NETWORKING", INTERFACE_TYPE); + $finish; + end + + endcase // case(INTERFACE_TYPE) + + end // always @(clk_in or oclk_in) + + + + +// data input mux for q3, q4, q5 and q6 + always @(sel1 or q1prnk1 or shiftin1_in or shiftin2_in) begin + + case (sel1) + + 2'b00 : dataq3rnk1 <= # mxinp1 q1prnk1; + 2'b01 : dataq3rnk1 <= # mxinp1 q1prnk1; + 2'b10 : dataq3rnk1 <= # mxinp1 shiftin2_in; + 2'b11 : dataq3rnk1 <= # mxinp1 shiftin1_in; + default : dataq3rnk1 <= # mxinp1 q1prnk1; + + endcase // case(sel1) + + end // always @(sel1 or q1prnk1 or SHIFTIN1 or SHIFTIN2) + + + always @(sel1 or q2prnk1 or q3rnk1 or shiftin1_in) begin + + case (sel1) + + 2'b00 : dataq4rnk1 <= # mxinp1 q2prnk1; + 2'b01 : dataq4rnk1 <= # mxinp1 q3rnk1; + 2'b10 : dataq4rnk1 <= # mxinp1 shiftin1_in; + 2'b11 : dataq4rnk1 <= # mxinp1 q3rnk1; + default : dataq4rnk1 <= # mxinp1 q2prnk1; + + endcase // case(sel1) + + end // always @(sel1 or q2prnk1 or q3rnk1 or SHIFTIN1) + + + always @(data_rate_int or q3rnk1 or q4rnk1) begin + + case (data_rate_int) + + 1'b0 : dataq5rnk1 <= # mxinp1 q3rnk1; + 1'b1 : dataq5rnk1 <= # mxinp1 q4rnk1; + default : dataq5rnk1 <= # mxinp1 q4rnk1; + + endcase // case(DATA_RATE) + + end + + + always @(data_rate_int or q4rnk1 or q5rnk1) begin + + case (data_rate_int) + + 1'b0 : dataq6rnk1 <= # mxinp1 q4rnk1; + 1'b1 : dataq6rnk1 <= # mxinp1 q5rnk1; + default : dataq6rnk1 <= # mxinp1 q5rnk1; + + endcase // case(DATA_RATE) + + end + + +// 2nd rank of registers + +// clkdivmux to pass clkdiv_int or CLKDIV to rank 2 + always @(bitslip_enable_int or clkdiv_int or clkdiv_in) begin + + case (bitslip_enable_int) + + 1'b0 : clkdivmux <= # mxinp1 clkdiv_in; + 1'b1 : clkdivmux <= # mxinp1 clkdiv_int; + default : clkdivmux <= # mxinp1 clkdiv_in; + + endcase // case(BITSLIP_ENABLE) + + end // always @(clkdiv_int or clkdiv_in) + + + +// Asynchronous Operation + always @(posedge clkdivmux or posedge sr_in) begin + + if (sr_in == 1'b1) begin + + q1rnk2 <= # ffinp 1'b0; + q2rnk2 <= # ffinp 1'b0; + q3rnk2 <= # ffinp 1'b0; + q4rnk2 <= # ffinp 1'b0; + q5rnk2 <= # ffinp 1'b0; + q6rnk2 <= # ffinp 1'b0; + + end + else begin + + q1rnk2 <= # ffinp dataq1rnk2; + q2rnk2 <= # ffinp dataq2rnk2; + q3rnk2 <= # ffinp dataq3rnk2; + q4rnk2 <= # ffinp dataq4rnk2; + q5rnk2 <= # ffinp dataq5rnk2; + q6rnk2 <= # ffinp dataq6rnk2; + + end + + end // always @ (posedge clkdivmux or sr_in) + + +// Data mux for 2nd rank of flops +// Delay for mux set to 120 + always @(bsmux or q1rnk1 or q1prnk1 or q2prnk1) begin + + casex (bsmux) + + 3'b00X : dataq1rnk2 <= # mxinp2 q2prnk1; + 3'b100 : dataq1rnk2 <= # mxinp2 q2prnk1; + 3'b101 : dataq1rnk2 <= # mxinp2 q1prnk1; + 3'bX1X : dataq1rnk2 <= # mxinp2 q1rnk1; + default : dataq1rnk2 <= # mxinp2 q2prnk1; + + endcase // casex(bsmux) + + end // always @(bsmux or q1rnk1 or q1prnk1 or q2prnk1) + + + always @(bsmux or q1prnk1 or q4rnk1) begin + + casex (bsmux) + + 3'b00X : dataq2rnk2 <= # mxinp2 q1prnk1; + 3'b100 : dataq2rnk2 <= # mxinp2 q1prnk1; + 3'b101 : dataq2rnk2 <= # mxinp2 q4rnk1; + 3'bX1X : dataq2rnk2 <= # mxinp2 q1prnk1; + default : dataq2rnk2 <= # mxinp2 q1prnk1; + + endcase // casex(bsmux) + + end // always @(bsmux or q1prnk1 or q4rnk1) + + + always @(bsmux or q3rnk1 or q4rnk1) begin + + casex (bsmux) + + 3'b00X : dataq3rnk2 <= # mxinp2 q4rnk1; + 3'b100 : dataq3rnk2 <= # mxinp2 q4rnk1; + 3'b101 : dataq3rnk2 <= # mxinp2 q3rnk1; + 3'bX1X : dataq3rnk2 <= # mxinp2 q3rnk1; + default : dataq3rnk2 <= # mxinp2 q4rnk1; + + endcase // casex(bsmux) + + end // always @(bsmux or q3rnk1 or q4rnk1) + + + always @(bsmux or q3rnk1 or q4rnk1 or q6rnk1) begin + + casex (bsmux) + + 3'b00X : dataq4rnk2 <= # mxinp2 q3rnk1; + 3'b100 : dataq4rnk2 <= # mxinp2 q3rnk1; + 3'b101 : dataq4rnk2 <= # mxinp2 q6rnk1; + 3'bX1X : dataq4rnk2 <= # mxinp2 q4rnk1; + default : dataq4rnk2 <= # mxinp2 q3rnk1; + + endcase // casex(bsmux) + + end // always @(bsmux or q3rnk1 or q4rnk1 or q6rnk1) + + + always @(bsmux or q5rnk1 or q6rnk1) begin + + casex (bsmux) + + 3'b00X : dataq5rnk2 <= # mxinp2 q6rnk1; + 3'b100 : dataq5rnk2 <= # mxinp2 q6rnk1; + 3'b101 : dataq5rnk2 <= # mxinp2 q5rnk1; + 3'bX1X : dataq5rnk2 <= # mxinp2 q5rnk1; + default : dataq5rnk2 <= # mxinp2 q6rnk1; + + endcase // casex(bsmux) + + end // always @(bsmux or q5rnk1 or q6rnk1) + + + always @(bsmux or q5rnk1 or q6rnk1 or q6prnk1) begin + + casex (bsmux) + + 3'b00X : dataq6rnk2 <= # mxinp2 q5rnk1; + 3'b100 : dataq6rnk2 <= # mxinp2 q5rnk1; + 3'b101 : dataq6rnk2 <= # mxinp2 q6prnk1; + 3'bX1X : dataq6rnk2 <= # mxinp2 q6rnk1; + default : dataq6rnk2 <= # mxinp2 q5rnk1; + + endcase // casex(bsmux) + + end // always @(bsmux or q5rnk1 or q6rnk1 or q6prnk1) + + + +// 3rd rank of registers + +// Asynchronous Operation + always @(posedge clkdiv_in or posedge sr_in) begin + + if (sr_in == 1'b1) begin + + q1rnk3 <= # ffinp 1'b0; + q2rnk3 <= # ffinp 1'b0; + q3rnk3 <= # ffinp 1'b0; + q4rnk3 <= # ffinp 1'b0; + q5rnk3 <= # ffinp 1'b0; + q6rnk3 <= # ffinp 1'b0; + + end + else begin + + q1rnk3 <= # ffinp q1rnk2; + q2rnk3 <= # ffinp q2rnk2; + q3rnk3 <= # ffinp q3rnk2; + q4rnk3 <= # ffinp q4rnk2; + q5rnk3 <= # ffinp q5rnk2; + q6rnk3 <= # ffinp q6rnk2; + + end + + end // always @ (posedge clkdiv_in or posedge sr_in) + + +// Outputs + + assign shiftout2_out = q5rnk1; + + assign shiftout1_out = q6rnk1; + + + always @(selrnk3 or q1rnk1 or q1prnk1 or q1rnk2 or q1rnk3) begin + + casex (selrnk3) + + 4'b0X00 : q1_out <= # mxinp1_my q1prnk1; + 4'b0X01 : q1_out <= # mxinp1_my q1rnk1; + 4'b0X10 : q1_out <= # mxinp1_my q1rnk1; + 4'b10XX : q1_out <= # mxinp1_my q1rnk2; + 4'b11XX : q1_out <= # mxinp1_my q1rnk3; + default : q1_out <= # mxinp1_my q1rnk2; + + endcase // casex(selrnk3) + + end // always @(selrnk3 or q1rnk1 or q1prnk1 or q1rnk2 or q1rnk3) + + + always @(selrnk3 or q2nrnk1 or q2prnk1 or q2rnk2 or q2rnk3) begin + + casex (selrnk3) + + 4'b0X00 : q2_out <= # mxinp1_my q2prnk1; + 4'b0X01 : q2_out <= # mxinp1_my q2prnk1; + 4'b0X10 : q2_out <= # mxinp1_my q2nrnk1; + 4'b10XX : q2_out <= # mxinp1_my q2rnk2; + 4'b11XX : q2_out <= # mxinp1_my q2rnk3; + default : q2_out <= # mxinp1_my q2rnk2; + + endcase // casex(selrnk3) + + end // always @(selrnk3 or q2nrnk1 or q2prnk1 or q2rnk2 or q2rnk3) + + + always @(bitslip_enable_int or q3rnk2 or q3rnk3) begin + + case (bitslip_enable_int) + + 1'b0 : q3_out <= # mxinp1_my q3rnk2; + 1'b1 : q3_out <= # mxinp1_my q3rnk3; + + endcase // case(BITSLIP_ENABLE) + + end // always @ (q3rnk2 or q3rnk3) + + + + + always @(bitslip_enable_int or q4rnk2 or q4rnk3) begin + + casex (bitslip_enable_int) + + 1'b0 : q4_out <= # mxinp1_my q4rnk2; + 1'b1 : q4_out <= # mxinp1_my q4rnk3; + + endcase // casex(BITSLIP_ENABLE) + + end // always @ (q4rnk2 or q4rnk3) + + + always @(bitslip_enable_int or q5rnk2 or q5rnk3) begin + + casex (bitslip_enable_int) + + 1'b0 : q5_out <= # mxinp1_my q5rnk2; + 1'b1 : q5_out <= # mxinp1_my q5rnk3; + + endcase // casex(BITSLIP_ENABLE) + + end // always @ (q5rnk2 or q5rnk3) + + + always @(bitslip_enable_int or q6rnk2 or q6rnk3) begin + + casex (bitslip_enable_int) + + 1'b0 : q6_out <= # mxinp1_my q6rnk2; + 1'b1 : q6_out <= # mxinp1_my q6rnk3; + + endcase // casex(BITSLIP_ENABLE) + + end // always @ (q6rnk2 or q6rnk3) + + + + + +// Set value of counter in bitslip controller + always @(data_rate_int or data_width_int) begin + + casex ({data_rate_int, data_width_int}) + + 5'b00100 : begin c23=1'b0; c45=1'b0; c67=1'b0; sel=2'b00; end + 5'b00110 : begin c23=1'b1; c45=1'b0; c67=1'b0; sel=2'b00; end + 5'b01000 : begin c23=1'b0; c45=1'b0; c67=1'b0; sel=2'b01; end + 5'b01010 : begin c23=1'b0; c45=1'b1; c67=1'b0; sel=2'b01; end + 5'b10010 : begin c23=1'b0; c45=1'b0; c67=1'b0; sel=2'b00; end + 5'b10011 : begin c23=1'b1; c45=1'b0; c67=1'b0; sel=2'b00; end + 5'b10100 : begin c23=1'b0; c45=1'b0; c67=1'b0; sel=2'b01; end + 5'b10101 : begin c23=1'b0; c45=1'b1; c67=1'b0; sel=2'b01; end + 5'b10110 : begin c23=1'b0; c45=1'b0; c67=1'b0; sel=2'b10; end + 5'b10111 : begin c23=1'b0; c45=1'b0; c67=1'b1; sel=2'b10; end + 5'b11000 : begin c23=1'b0; c45=1'b0; c67=1'b0; sel=2'b11; end + default : begin + $display("DATA_WIDTH %d and DATA_RATE %s at %t is an illegal value", DATA_WIDTH, DATA_RATE, $time); + $finish; + end + + endcase + + end // always @ (data_rate_int or data_width_int) + + + + + +/////////////////////////////////////////// +// Bit slip controler +/////////////////////////////////////////// + + +// Divide by 2 - 8 counter + +// Asynchronous Operation + always @ (posedge qr2 or negedge clk_in) begin + + if (qr2 == 1'b1) begin + + clkdiv_int <= # ffbsc 1'b0; + bts_q1 <= # ffbsc 1'b0; + bts_q2 <= # ffbsc 1'b0; + bts_q3 <= # ffbsc 1'b0; + + end + else if (qhc1 == 1'b0) begin + + bts_q3 <= # ffbsc bts_q2; + bts_q2 <= # ffbsc (!(!clkdiv_int & !bts_q2) & bts_q1); + bts_q1 <= # ffbsc clkdiv_int; + clkdiv_int <= # ffbsc mux; + + end + + end // always @ (posedge qr2 or negedge clk_in) + + +// Synchronous Operation + always @ (negedge clk_in) begin + + if (qr2 == 1'b1) begin + + clkdiv_int <= # ffbsc 1'b0; + bts_q1 <= # ffbsc 1'b0; + bts_q2 <= # ffbsc 1'b0; + bts_q3 <= # ffbsc 1'b0; + + end + else if (qhc1 == 1'b1) begin + + clkdiv_int <= # ffbsc clkdiv_int; + bts_q1 <= # ffbsc bts_q1; + bts_q2 <= # ffbsc bts_q2; + bts_q3 <= # ffbsc bts_q3; + + end + else begin + + bts_q3 <= # ffbsc bts_q2; + bts_q2 <= # ffbsc (!(!clkdiv_int & !bts_q2) & bts_q1); + bts_q1 <= # ffbsc clkdiv_int; + clkdiv_int <= # ffbsc mux; + + end + + end // always @ (negedge clk_in) + + +// 4:1 selector mux and divider selections + always @ (sel or c23 or c45 or c67 or clkdiv_int or bts_q1 or bts_q2 or bts_q3) begin + + case (sel) + + 2'b00 : mux <= # mxbsc !(clkdiv_int | (c23 & bts_q1)); + 2'b01 : mux <= # mxbsc !(bts_q1 | (c45 & bts_q2)); + 2'b10 : mux <= # mxbsc !(bts_q2 | (c67 & bts_q3)); + 2'b11 : mux <= # mxbsc !bts_q3; + default : mux <= # mxbsc !(clkdiv_int | (c23 & bts_q1)); + + endcase + + end // always @ (sel or c23 or c45 or c67 or clkdiv_int or bts_q1 or bts_q2 or bts_q3) + + + +// Bitslip control logic +// Low speed control flop + +// Asynchronous Operation + always @ (posedge qr1 or posedge clkdiv_in) begin + + if (qr1 == 1'b1) begin + + qlc1 <= # ffbsc 1'b0; + qlc2 <= # ffbsc 1'b0; + + end + else if (bitslip_in == 1'b0) begin + + qlc1 <= # ffbsc qlc1; + qlc2 <= # ffbsc 1'b0; + + end + else begin + + qlc1 <= # ffbsc !qlc1; + qlc2 <= # ffbsc (bitslip_in & mux1); + + end + + end // always @ (posedge qr1 or posedge clkdiv_in) + + +// Mux to select between sdr "1" and ddr "0" + + always @ (data_rate_int or qlc1) begin + + case (data_rate_int) + + 1'b0 : mux1 <= # mxbsc qlc1; + 1'b1 : mux1 <= # mxbsc 1'b1; + + endcase + + end + + + +// High speed control flop + +// Asynchronous Operation + always @ (posedge qr2 or negedge clk_in) begin + + if (qr2 == 1'b1) begin + + qhc1 <= # ffbsc 1'b0; + qhc2 <= # ffbsc 1'b0; + + end + else begin + + qhc1 <= # ffbsc (qlc2 & !qhc2); + qhc2 <= # ffbsc qlc2; + + end + + end // always @ (posedge qr2 or negedge clk_in) + + +// Mux that drives control line of mux in front +// of 2nd rank of flops + + always @ (data_rate_int or mux1) begin + + case (data_rate_int) + + 1'b0 : muxc <= # mxbsc mux1; + 1'b1 : muxc <= # mxbsc 1'b0; + + endcase + + end + + +// Asynchronous set flops + +// Low speed reset flop + +// Asynchronous Operation + always @ (posedge sr_in or posedge clkdiv_in) begin + + if (sr_in == 1'b1) + + qr1 <= # ffbsc 1'b1; + + else + + qr1 <= # ffbsc 1'b0; + + end // always @ (posedge sr_in or posedge clkdiv_in) + + +// High speed reset flop + +// Asynchronous Operation + always @ (posedge sr_in or negedge clk_in) begin + + if (sr_in == 1'b1) + + qr2 <= # ffbsc 1'b1; + + else + + qr2 <= # ffbsc qr1; + + end // always @ (posedge sr_in or negedge clk_in) + + +///////////////////////////////////////////// +// ICE +/////////////////////////////////////////// + + +// Asynchronous Operation + always @ (posedge clkdiv_in or posedge sr_in) begin + + if (sr_in == 1'b1) begin + + ce1r <= # ffice 1'b0; + ce2r <= # ffice 1'b0; + + end + else begin + + ce1r <= # ffice ce1_in; + ce2r <= # ffice ce2_in; + + end + + end // always @ (posedge clkdiv_in or posedge sr_in) + + + // Output mux ice + always @ (num_ce_int or clkdiv_in or ce1_in or ce1r or ce2r) begin + case ({num_ce_int, clkdiv_in}) + 2'b00 : ice <= # mxice ce1_in; + 2'b01 : ice <= # mxice ce1_in; +// 426606 + 2'b10 : ice <= # mxice ce2r; + 2'b11 : ice <= # mxice ce1r; + default : ice <= # mxice ce1_in; + endcase + end + +//*** Timing Checks Start here + + specify + + (CLKDIV => Q1) = (100:100:100, 100:100:100); + (CLKDIV => Q2) = (100:100:100, 100:100:100); + (CLKDIV => Q3) = (100:100:100, 100:100:100); + (CLKDIV => Q4) = (100:100:100, 100:100:100); + (CLKDIV => Q5) = (100:100:100, 100:100:100); + (CLKDIV => Q6) = (100:100:100, 100:100:100); + + specparam PATHPULSE$ = 0; + + endspecify + +endmodule // ISERDES_NODELAY diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/JTAGPPC.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/JTAGPPC.v new file mode 100644 index 0000000..d4ba637 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/JTAGPPC.v @@ -0,0 +1,34 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/JTAGPPC.v,v 1.6 2007/05/23 21:43:39 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / +// /___/ /\ Filename : JTAGPPC.v +// \ \ / \ Timestamp : Thu Jun 24 16:42:51 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. + +`timescale 1 ps / 1 ps + +module JTAGPPC (TCK, TDIPPC, TMS, TDOPPC, TDOTSPPC); + +output TCK; +output TDIPPC; +output TMS; + +input TDOPPC; +input TDOTSPPC; + + assign TCK = 1'b1; + assign TDIPPC = 1'b1; + assign TMS = 1'b1; +endmodule diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/JTAGPPC440.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/JTAGPPC440.v new file mode 100644 index 0000000..702d115 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/JTAGPPC440.v @@ -0,0 +1,38 @@ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / +// /___/ /\ Filename : JTAGPPC440.v +// \ \ / \ Timestamp : Wed Aug 17 16:23:43 PDT 2005 +// \___\/\___\ +// +// Revision: +// 08/17/05 - Initial version. +// End Revision + +`timescale 1 ps / 1 ps + +module JTAGPPC440 ( + TCK, + TDIPPC, + TMS, + TDOPPC +); + +output TCK; +output TDIPPC; +output TMS; + +input TDOPPC; + +specify + specparam PATHPULSE$ = 0; +endspecify + +endmodule diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/JTAG_SIM_SPARTAN3A.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/JTAG_SIM_SPARTAN3A.v new file mode 100644 index 0000000..ee2132e --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/JTAG_SIM_SPARTAN3A.v @@ -0,0 +1,676 @@ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Simulation Library Component +// / / Jtag TAP Controler +// /___/ /\ Filename : JTAG_SIM_SPARTAN3A.v +// \ \ / \ Timestamp : Fri Jul 1 16:18:11 PDT 2005 +// \___\/\___\ +// +// Revision: +// 07/01/05 - Initial version. +// 07/09/05 - CR 211337 -- made RESET be active on the "+" edge of TCK +// 09/14/08 - CR 481520 -- added global TMS +// 03/04/09 - CR 508358 -- Added XCS3AN and XCS3D device support +// End Revision + +`timescale 1 ps/1 ps + +module JTAG_SIM_SPARTAN3A( TDO, TCK, TDI, TMS ); + + + output TDO; + + input TCK, TDI, TMS; + + reg TDO; + reg notifier; + + parameter PART_NAME = "3S200A"; + + localparam tpd_TCK_TDO = 6000, + tsetup_TDI_TCK = 1000, + thold_TDI_TCK = 2000, + tsetup_TMS_TCK = 1000, + thold_TMS_TCK = 2000; + + localparam TestLogicReset = 4'h0, + RunTestIdle = 4'h1, + SelectDRScan = 4'h2, + CaptureDR = 4'h3, + ShiftDR = 4'h4, + Exit1DR = 4'h5, + PauseDR = 4'h6, + Exit2DR = 4'h7, + UpdateDR = 4'h8, + SelectIRScan = 4'h9, + CaptureIR = 4'ha, + ShiftIR = 4'hb, + Exit1IR = 4'hc, + PauseIR = 4'hd, + Exit2IR = 4'he, + UpdateIR = 4'hf; + + localparam DELAY_SIG = 1; + + reg TRST = 0; + + reg [3:0] CurrentState = TestLogicReset; + reg [14*8:0] jtag_state_name = "TestLogicReset"; + reg [14*8:0] jtag_instruction_name = "IDCODE"; + + +//----------------- Virtex4 Specific Constants --------- + localparam IRLength = 6; + localparam IDLength = 32; + + reg [IRLength-1:0] IR_CAPTURE_VAL = 6'b010001, + BYPASS_INSTR = 6'b111111, + IDCODE_INSTR = 6'b001001, + USER1_INSTR = 6'b000010, + USER2_INSTR = 6'b000011, + USER3_INSTR = 6'bxxxxxx, + USER4_INSTR = 6'bxxxxxx; + +//----------------- local reg ------------------------------- + reg CaptureDR_sig = 0, RESET_sig = 0, ShiftDR_sig = 0, UpdateDR_sig = 0; + + reg ClkIR_active = 0, ClkIR_sig = 0, ClkID_sig = 0; + + reg ShiftIR_sig, UpdateIR_sig, ClkUpdateIR_sig; + + reg [IRLength-1:0] IRcontent_sig; + + reg [IDLength-1:0] IDCODEval_sig; + + reg BypassReg = 0, BYPASS_sig = 0, IDCODE_sig = 0, + USER1_sig = 0, USER2_sig = 0, + USER3_sig = 0, USER4_sig = 0; + + reg TDO_latch; + + reg Tlrst_sig = 1; + reg TlrstN_sig = 1; + + reg IRegLastBit_sig = 0, IDregLastBit_sig = 0; + + //------------------------------------------------------------- + reg [IRLength-1:0] NextIRreg; + reg [IRLength-1:0] ir_int; + reg [IDLength-1:0] IDreg; + +//#################################################################### +//##### Initialize ##### +//#################################################################### + initial begin + case (PART_NAME) + "3S1400A", "3s1400a" : IDCODEval_sig <= 32'h02230093; + "3S1400AN", "3s1400an" : IDCODEval_sig <= 32'h02630093; + "3S200A", "3s200a" : IDCODEval_sig <= 32'h02218093; + "3S200AN", "3s200an" : IDCODEval_sig <= 32'h02618093; + "3S400A", "3s400a" : IDCODEval_sig <= 32'h02220093; + "3S400AN", "3s400an" : IDCODEval_sig <= 32'h02620093; + "3S50A", "3s50a" : IDCODEval_sig <= 32'h02210093; + "3S50AN", "3s50an" : IDCODEval_sig <= 32'h02610093; + "3S700A", "3s700a" : IDCODEval_sig <= 32'h02228093; + "3S700AN", "3s700an" : IDCODEval_sig <= 32'h02628093; + "3SD1800A", "3sd1800a" : IDCODEval_sig <= 32'h03840093; + "3SD3400A", "3sd3400a" : IDCODEval_sig <= 32'h0384e093; + + default : begin + $display("Attribute Syntax Error : attribute PART_NAME on JTAG_SIM_SPARTAN3A instance %m is set to %s. The legal values for this attribute are 3S1400A or 3S1400AN or 3S200A or 3S200AN or 3S400A or 3S400AN or 3S50A or 3S50AN or 3S700A or 3S700AN or 3SD1800A or 3SD3400A", PART_NAME); + end + endcase // case(PART_NAME) + + ir_int <= IR_CAPTURE_VAL[IRLength-1:0]; + + end // initial begin +//#################################################################### +//##### JtagTapSM ##### +//#################################################################### + always@(posedge TCK or posedge TRST) + begin + if(TRST) begin + CurrentState = TestLogicReset; + end + else begin + case(CurrentState) + + TestLogicReset: + begin + if(TMS == 0) begin + CurrentState = RunTestIdle; + jtag_state_name = "RunTestIdle"; + end + end + + RunTestIdle: + begin + if(TMS == 1) begin + CurrentState = SelectDRScan; + jtag_state_name = "SelectDRScan"; + end + end + //------------------------------- + // ------ DR path --------------- + // ------------------------------- + SelectDRScan: + begin + if(TMS == 0) begin + CurrentState = CaptureDR; + jtag_state_name = "CaptureDR"; + end + else if(TMS == 1) begin + CurrentState = SelectIRScan; + jtag_state_name = "SelectIRScan"; + end + end + + CaptureDR: + begin + if(TMS == 0) begin + CurrentState = ShiftDR; + jtag_state_name = "ShiftDR"; + end + else if(TMS == 1) begin + CurrentState = Exit1DR; + jtag_state_name = "Exit1DR"; + end + end + + ShiftDR: + begin + if(IRcontent_sig == BYPASS_INSTR) + BypassReg = TDI; + + if(TMS == 1) begin + CurrentState = Exit1DR; + jtag_state_name = "Exit1DR"; + end + end + + Exit1DR: + begin + if(TMS == 0) begin + CurrentState = PauseDR; + jtag_state_name = "PauseDR"; + end + else if(TMS == 1) begin + CurrentState = UpdateDR; + jtag_state_name = "UpdateDR"; + end + end + + PauseDR: + begin + if(TMS == 1) begin + CurrentState = Exit2DR; + jtag_state_name = "Exit2DR"; + end + end + + Exit2DR: + begin + if(TMS == 0) begin + CurrentState = ShiftDR; + jtag_state_name = "ShiftDR"; + end + else if(TMS == 1) begin + CurrentState = UpdateDR; + jtag_state_name = "UpdateDR"; + end + end + + UpdateDR: + begin + if(TMS == 0) begin + CurrentState = RunTestIdle; + jtag_state_name = "RunTestIdle"; + end + else if(TMS == 1) begin + CurrentState = SelectDRScan; + jtag_state_name = "SelectDRScan"; + end + end + //------------------------------- + // ------ IR path --------------- + // ------------------------------- + SelectIRScan: + begin + if(TMS == 0) begin + CurrentState = CaptureIR; + jtag_state_name = "CaptureIR"; + end + else if(TMS == 1) begin + CurrentState = TestLogicReset; + jtag_state_name = "TestLogicReset"; + end + end + + CaptureIR: + begin + if(TMS == 0) begin + CurrentState = ShiftIR; + jtag_state_name = "ShiftIR"; + end + else if(TMS == 1) begin + CurrentState = Exit1IR; + jtag_state_name = "Exit1IR"; + end + end + + ShiftIR: + begin + + if(TMS == 1) begin + CurrentState = Exit1IR; + jtag_state_name = "Exit1IR"; + end + end + + Exit1IR: + begin + if(TMS == 0) begin + CurrentState = PauseIR; + jtag_state_name = "PauseIR"; + end + else if(TMS == 1) begin + CurrentState = UpdateIR; + jtag_state_name = "UpdateIR"; + end + end + + PauseIR: + begin + if(TMS == 1) begin + CurrentState = Exit2IR; + jtag_state_name = "Exit2IR"; + end + end + + Exit2IR: + begin + if(TMS == 0) begin + CurrentState = ShiftIR; + jtag_state_name = "ShiftIR"; + end + else if(TMS == 1) begin + CurrentState = UpdateIR; + jtag_state_name = "UpdateIR"; + end + end + + UpdateIR: + begin + + if(TMS == 0) begin + CurrentState = RunTestIdle; + jtag_state_name = "RunTestIdle"; + end + else if(TMS == 1) begin + CurrentState = SelectDRScan; + jtag_state_name = "SelectDRScan"; + end + end + endcase // case(CurrentState) + end // else + + end // always + +//-------------------------------------------------------- + always@(CurrentState, TCK, TRST) + begin + ClkIR_sig = 1; + + if(TRST == 1 ) begin + Tlrst_sig = #DELAY_SIG 1; + CaptureDR_sig = #DELAY_SIG 0; + ShiftDR_sig = #DELAY_SIG 0; + UpdateDR_sig = #DELAY_SIG 0; + ShiftIR_sig = #DELAY_SIG 0; + UpdateIR_sig = #DELAY_SIG 0; + end + else if(TRST == 0) begin + + case (CurrentState) + TestLogicReset: begin + Tlrst_sig = #DELAY_SIG 1; + CaptureDR_sig = #DELAY_SIG 0; + ShiftDR_sig = #DELAY_SIG 0; + UpdateDR_sig = #DELAY_SIG 0; + ShiftIR_sig = #DELAY_SIG 0; + UpdateIR_sig = #DELAY_SIG 0; + end + CaptureDR: begin + Tlrst_sig = #DELAY_SIG 0; + CaptureDR_sig = #DELAY_SIG 1; + ShiftDR_sig = #DELAY_SIG 0; + UpdateDR_sig = #DELAY_SIG 0; + ShiftIR_sig = #DELAY_SIG 0; + UpdateIR_sig = #DELAY_SIG 0; + end + ShiftDR: begin + Tlrst_sig = #DELAY_SIG 0; + CaptureDR_sig = #DELAY_SIG 0; + ShiftDR_sig = #DELAY_SIG 1; + UpdateDR_sig = #DELAY_SIG 0; + ShiftIR_sig = #DELAY_SIG 0; + UpdateIR_sig = #DELAY_SIG 0; + end + UpdateDR: begin + Tlrst_sig = #DELAY_SIG 0; + CaptureDR_sig = #DELAY_SIG 0; + ShiftDR_sig = #DELAY_SIG 0; + UpdateDR_sig = #DELAY_SIG 1; + ShiftIR_sig = #DELAY_SIG 0; + UpdateIR_sig = #DELAY_SIG 0; + end + CaptureIR: begin + Tlrst_sig = #DELAY_SIG 0; + CaptureDR_sig = #DELAY_SIG 0; + ShiftDR_sig = #DELAY_SIG 0; + UpdateDR_sig = #DELAY_SIG 0; + ShiftIR_sig = #DELAY_SIG 0; + UpdateIR_sig = #DELAY_SIG 0; + ClkIR_sig = TCK; + end + ShiftIR: begin + Tlrst_sig = #DELAY_SIG 0; + CaptureDR_sig = #DELAY_SIG 0; + ShiftDR_sig = #DELAY_SIG 0; + UpdateDR_sig = #DELAY_SIG 0; + ShiftIR_sig = #DELAY_SIG 1; + UpdateIR_sig = #DELAY_SIG 0; + ClkIR_sig = TCK; + end + UpdateIR: begin + Tlrst_sig = #DELAY_SIG 0; + CaptureDR_sig = #DELAY_SIG 0; + ShiftDR_sig = #DELAY_SIG 0; + UpdateDR_sig = #DELAY_SIG 0; + ShiftIR_sig = #DELAY_SIG 0; + UpdateIR_sig = #DELAY_SIG 1; + end + default: begin + Tlrst_sig = #DELAY_SIG 0; + CaptureDR_sig = #DELAY_SIG 0; + ShiftDR_sig = #DELAY_SIG 0; + UpdateDR_sig = #DELAY_SIG 0; + ShiftIR_sig = #DELAY_SIG 0; + UpdateIR_sig = #DELAY_SIG 0; + end + endcase + + end + + end // always(CurrentState) +//----------------------------------------------------- + always@(TCK) + begin + ClkUpdateIR_sig = UpdateIR_sig & ~TCK; + end // always + + always@(TCK) + begin + ClkID_sig = IDCODE_sig & TCK; + end // always + +// CR 211377 Reset should go high in State Tlrst + always@(Tlrst_sig) + begin + glbl.JTAG_RESET_GLBL <= Tlrst_sig; + end + + +//-------------- TCK NEGATIVE EDGE activities ---------- + always@(negedge TCK, negedge UpdateDR_sig) + begin + if(TCK == 0) begin + glbl.JTAG_CAPTURE_GLBL <= CaptureDR_sig; + // CR 211377 Reset should go high in State Tlrst + // glbl.JTAG_RESET_GLBL <= Tlrst_sig; + glbl.JTAG_SHIFT_GLBL <= ShiftDR_sig; + TlrstN_sig <= Tlrst_sig; + end + + glbl.JTAG_UPDATE_GLBL <= UpdateDR_sig; + + end // always + +//--#################################################################### +//--##### JtagIR ##### +//--#################################################################### + always@(posedge ClkIR_sig) begin + NextIRreg = {TDI, ir_int[IRLength-1:1]}; + + if ((TRST== 0) && (TlrstN_sig == 0)) begin + if(ShiftIR_sig == 1) begin + ir_int = NextIRreg; + IRegLastBit_sig = ir_int[0]; + end + else begin + ir_int = IR_CAPTURE_VAL; + IRegLastBit_sig = ir_int[0]; + end + end + end //always +//-------------------------------------------------------- + always@(posedge ClkUpdateIR_sig or posedge TlrstN_sig or + posedge TRST) begin + if ((TRST== 1) || (TlrstN_sig == 1)) begin + IRcontent_sig = IDCODE_INSTR; // IDCODE instr is loaded.. + IRegLastBit_sig = ir_int[0]; + end + else if( (TRST == 0) && (TlrstN_sig == 0)) begin + IRcontent_sig = ir_int; + end + end //always +//--#################################################################### +//--##### JtagDecodeIR ##### +//--#################################################################### + always@(IRcontent_sig) begin + + case(IRcontent_sig) + + BYPASS_INSTR : begin + jtag_instruction_name = "BYPASS"; + // if BYPASS instruction, set BYPASS signal to 1 + BYPASS_sig <= 1; + IDCODE_sig <= 0; + USER1_sig <= 0; + USER2_sig <= 0; + USER3_sig <= 0; + USER4_sig <= 0; + end + + IDCODE_INSTR : begin + jtag_instruction_name = "IDCODE"; + // if IDCODE instruction, set IDCODE signal to 1 + BYPASS_sig <= 0; + IDCODE_sig <= 1; + USER1_sig <= 0; + USER2_sig <= 0; + USER3_sig <= 0; + USER4_sig <= 0; + end + + USER1_INSTR : begin + jtag_instruction_name = "USER1"; + // if USER1 instruction, set USER1 signal to 1 + BYPASS_sig <= 0; + IDCODE_sig <= 0; + USER1_sig <= 1; + USER2_sig <= 0; + USER3_sig <= 0; + USER4_sig <= 0; + end + + USER2_INSTR : begin + jtag_instruction_name = "USER2"; + // if USER2 instruction, set USER2 signal to 1 + BYPASS_sig <= 0; + IDCODE_sig <= 0; + USER1_sig <= 0; + USER2_sig <= 1; + USER3_sig <= 0; + USER4_sig <= 0; + end + + USER3_INSTR : begin + jtag_instruction_name = "USER3"; + // if USER3 instruction, set USER3 signal to 1 + BYPASS_sig <= 0; + USER1_sig <= 0; + USER2_sig <= 0; + IDCODE_sig <= 0; + USER3_sig <= 1; + USER4_sig <= 0; + end + + USER4_INSTR : begin + jtag_instruction_name = "USER4"; + // if USER4 instruction, set USER4 signal to 1 + BYPASS_sig <= 0; + IDCODE_sig <= 0; + USER1_sig <= 0; + USER2_sig <= 0; + USER3_sig <= 0; + USER4_sig <= 1; + end + + endcase + end //always +//--#################################################################### +//--##### JtagIDCODE ##### +//--#################################################################### + always@(posedge ClkID_sig) begin + if(ShiftDR_sig == 1) begin + IDreg = IDreg >> 1; + IDreg[IDLength -1] = TDI; + end + else + IDreg = IDCODEval_sig; + + IDregLastBit_sig = IDreg[0]; + end // always + +//--#################################################################### +//--##### JtagSetGlobalSignals ##### +//--#################################################################### + always@(ClkUpdateIR_sig, Tlrst_sig, USER1_sig, USER2_sig, USER3_sig, USER4_sig) begin + + if(Tlrst_sig == 1) begin + glbl.JTAG_SEL1_GLBL <= 0; + glbl.JTAG_SEL2_GLBL <= 0; + glbl.JTAG_SEL3_GLBL <= 0; + glbl.JTAG_SEL4_GLBL <= 0; + end + else if(Tlrst_sig == 0) begin + if(USER1_sig == 1) begin + glbl.JTAG_SEL1_GLBL <= USER1_sig; + glbl.JTAG_SEL2_GLBL <= 0; + glbl.JTAG_SEL3_GLBL <= 0; + glbl.JTAG_SEL4_GLBL <= 0; + end + else if(USER2_sig == 1) begin + glbl.JTAG_SEL1_GLBL <= 0; + glbl.JTAG_SEL2_GLBL <= 1; + glbl.JTAG_SEL3_GLBL <= 0; + glbl.JTAG_SEL4_GLBL <= 0; + end + else if(USER3_sig == 1) begin + glbl.JTAG_SEL1_GLBL <= 0; + glbl.JTAG_SEL2_GLBL <= 0; + glbl.JTAG_SEL3_GLBL <= 1; + glbl.JTAG_SEL4_GLBL <= 0; + end + else if(USER4_sig == 1) begin + glbl.JTAG_SEL1_GLBL <= 0; + glbl.JTAG_SEL2_GLBL <= 0; + glbl.JTAG_SEL3_GLBL <= 0; + glbl.JTAG_SEL4_GLBL <= 1; + end + else if(ClkUpdateIR_sig == 1) begin + glbl.JTAG_SEL1_GLBL <= 0; + glbl.JTAG_SEL2_GLBL <= 0; + glbl.JTAG_SEL3_GLBL <= 0; + glbl.JTAG_SEL4_GLBL <= 0; + end + + end + + end //always + +//--#################################################################### +//--##### OUTPUT ##### +//--#################################################################### + assign glbl.JTAG_TDI_GLBL = TDI; + assign glbl.JTAG_TCK_GLBL = TCK; + assign glbl.JTAG_TMS_GLBL = TMS; + + always@(CurrentState, IRcontent_sig, BypassReg, + IRegLastBit_sig, IDregLastBit_sig, glbl.JTAG_USER_TDO1_GLBL, + glbl.JTAG_USER_TDO2_GLBL, glbl.JTAG_USER_TDO3_GLBL, + glbl.JTAG_USER_TDO4_GLBL) + begin + case (CurrentState) + ShiftIR: begin + TDO_latch <= IRegLastBit_sig; + end + ShiftDR: begin + if(IRcontent_sig == IDCODE_INSTR) + TDO_latch <= IDregLastBit_sig; + else if(IRcontent_sig == BYPASS_INSTR) + TDO_latch <= BypassReg; + else if(IRcontent_sig == USER1_INSTR) + TDO_latch <= glbl.JTAG_USER_TDO1_GLBL; + else if(IRcontent_sig == USER2_INSTR) + TDO_latch <= glbl.JTAG_USER_TDO2_GLBL; + else if(IRcontent_sig == USER3_INSTR) + TDO_latch <= glbl.JTAG_USER_TDO3_GLBL; + else if(IRcontent_sig == USER4_INSTR) + TDO_latch <= glbl.JTAG_USER_TDO4_GLBL; + else + TDO_latch <= 1'bz; + end + default : begin + TDO_latch <= 1'bz; + end + endcase // case(PART_NAME) + end // always + + always@(negedge TCK) + begin +// TDO <= #tpd_TCK_TDO TDO_latch; + TDO <= # 6000 TDO_latch; + end // always + +//--#################################################################### +//--##### Timing ##### +//--#################################################################### + + specify + +// (TCK => TDO) = (tpd_TCK_TDO, tpd_TCK_TDO); + +// $setuphold (posedge TCK, posedge TDI , tsetup_TDI_TCK, tsetup_TDI_TCK, notifier); +// $setuphold (posedge TCK, negedge TDI , thold_TDI_TCK, thold_TDI_TCK, notifier); + +// $setuphold (posedge TCK, posedge TMS , tsetup_TMS_TCK, tsetup_TMS_TCK, notifier); +// $setuphold (posedge TCK, negedge TMS , thold_TMS_TCK, thold_TMS_TCK, notifier); + + $setuphold (posedge TCK, posedge TDI , 1000:1000:1000, 2000:2000:2000, notifier); + $setuphold (posedge TCK, negedge TDI , 1000:1000:1000, 2000:2000:2000, notifier); + + $setuphold (posedge TCK, posedge TMS , 1000:1000:1000, 2000:2000:2000, notifier); + $setuphold (posedge TCK, negedge TMS , 1000:1000:1000, 2000:2000:2000, notifier); + + endspecify + + +endmodule // JTAG_SIM_SPARTAN3A diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/JTAG_SIM_SPARTAN6.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/JTAG_SIM_SPARTAN6.v new file mode 100644 index 0000000..90a4ffa --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/JTAG_SIM_SPARTAN6.v @@ -0,0 +1,705 @@ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2005 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Timing Simulation Library Component +// / / Jtag TAP Controler for Spartan6 +// /___/ /\ Filename : JTAG_SIM_SPARTAN6.v +// \ \ / \ Timestamp : Fri Jan 16 14:13:44 PST 2009 +// \___\/\___\ +// +// Revision: +// 01/16/09 - Initial version. +// 04/08/09 - CR 528894 -- PART_NAME default value fix for gencomp +// 08/26/09 - CR 530869 -- PART_NAME values updated and default value changed +// End Revision + +`timescale 1 ps/1 ps + +module JTAG_SIM_SPARTAN6( TDO, TCK, TDI, TMS); + + + output TDO; + + input TCK, TDI, TMS; + + reg TDO; + reg notifier; + + + parameter PART_NAME = "LX4"; + + localparam TestLogicReset = 4'h0, + RunTestIdle = 4'h1, + SelectDRScan = 4'h2, + CaptureDR = 4'h3, + ShiftDR = 4'h4, + Exit1DR = 4'h5, + PauseDR = 4'h6, + Exit2DR = 4'h7, + UpdateDR = 4'h8, + SelectIRScan = 4'h9, + CaptureIR = 4'ha, + ShiftIR = 4'hb, + Exit1IR = 4'hc, + PauseIR = 4'hd, + Exit2IR = 4'he, + UpdateIR = 4'hf; + + localparam DELAY_SIG = 1; + + reg TRST = 0; + + reg [3:0] CurrentState = TestLogicReset; + reg [14*8:0] jtag_state_name = "TestLogicReset"; + reg [14*8:0] jtag_instruction_name = "IDCODE"; + + +//----------------- Virtex4 Specific Constants --------- + localparam IRLengthMax = 6; + localparam IDLength = 32; + + reg [IRLengthMax-1:0] IR_CAPTURE_VAL = 6'b010001, + BYPASS_INSTR = 6'b111111, + IDCODE_INSTR = 6'b001001, + USER1_INSTR = 6'b000010, + USER2_INSTR = 6'b000011, + USER3_INSTR = 6'b011010, + USER4_INSTR = 6'b011011; + + localparam IRLength = 6; + +//----------------- local reg ------------------------------- + reg CaptureDR_sig = 0, RESET_sig = 0, ShiftDR_sig = 0, UpdateDR_sig = 0; + + reg ClkIR_active = 0, ClkIR_sig = 0, ClkID_sig = 0; + + reg ShiftIR_sig, UpdateIR_sig, ClkUpdateIR_sig; + + reg [IRLength-1:0] IRcontent_sig; + + reg [IDLength-1:0] IDCODEval_sig; + + reg BypassReg = 0, BYPASS_sig = 0, IDCODE_sig = 0, + USER1_sig = 0, USER2_sig = 0, + USER3_sig = 0, USER4_sig = 0; + + reg TDO_latch; + + reg Tlrst_sig = 1; + reg TlrstN_sig = 1; + + reg IRegLastBit_sig = 0, IDregLastBit_sig = 0; + + reg Rti_sig = 0; + //------------------------------------------------------------- + reg [IRLength-1:0] NextIRreg; + reg [IRLength-1:0] ir_int; // = IR_CAPTURE_VAL[IRLength-1:0] ; + reg [IDLength-1:0] IDreg; + +//#################################################################### +//##### Initialize ##### +//#################################################################### + initial begin + case (PART_NAME) + "LX4", "lx4" : IDCODEval_sig <= 32'h04000093; + "LX9", "lx9" : IDCODEval_sig <= 32'h04001093; + "LX16", "lx16" : IDCODEval_sig <= 32'h04002093; + "LX25", "lx25" : IDCODEval_sig <= 32'h04004093; + "LX25T", "lx25t" : IDCODEval_sig <= 32'h04024093; + "LX45", "lx45" : IDCODEval_sig <= 32'h04008093; + "LX45T", "lx45t" : IDCODEval_sig <= 32'h04028093; + "LX75", "lx75" : IDCODEval_sig <= 32'h0400e093; + "LX75T", "lx75t" : IDCODEval_sig <= 32'h0402e093; + "LX100", "lx100" : IDCODEval_sig <= 32'h04011093; + "LX100T", "lx100t" : IDCODEval_sig <= 32'h04031093; + "LX150", "lx150" : IDCODEval_sig <= 32'h0401d093; + "LX150T", "lx150t" : IDCODEval_sig <= 32'h0403d093; + + default : begin + $display("Attribute Syntax Error : The attribute PART_NAME on JTAG_SIM_SPARTAN6 instance %m is set to %s. The legal values for this attributes are LX4 or LX9 or LX16 or LX25 or LX25T or LX45 or LX45T or LX75 or LX75T or LX100 or LX100T or LX150 or LX150T", PART_NAME); + + end + endcase // case(PART_NAME) + + ir_int <= IR_CAPTURE_VAL[IRLength-1:0]; + + end // initial begin +//#################################################################### +//##### JtagTapSM ##### +//#################################################################### + always@(posedge TCK or posedge TRST) + begin + if(TRST) begin + CurrentState = TestLogicReset; + end + else begin + case(CurrentState) + + TestLogicReset: + begin + if(TMS == 0) begin + CurrentState = RunTestIdle; + jtag_state_name = "RunTestIdle"; + end + end + + RunTestIdle: + begin + if(TMS == 1) begin + CurrentState = SelectDRScan; + jtag_state_name = "SelectDRScan"; + end + end + //------------------------------- + // ------ DR path --------------- + // ------------------------------- + SelectDRScan: + begin + if(TMS == 0) begin + CurrentState = CaptureDR; + jtag_state_name = "CaptureDR"; + end + else if(TMS == 1) begin + CurrentState = SelectIRScan; + jtag_state_name = "SelectIRScan"; + end + end + + CaptureDR: + begin + if(TMS == 0) begin + CurrentState = ShiftDR; + jtag_state_name = "ShiftDR"; + end + else if(TMS == 1) begin + CurrentState = Exit1DR; + jtag_state_name = "Exit1DR"; + end + end + + ShiftDR: + begin + if(IRcontent_sig == BYPASS_INSTR[(IRLength - 1): 0]) + BypassReg = TDI; + + if(TMS == 1) begin + CurrentState = Exit1DR; + jtag_state_name = "Exit1DR"; + end + end + + Exit1DR: + begin + if(TMS == 0) begin + CurrentState = PauseDR; + jtag_state_name = "PauseDR"; + end + else if(TMS == 1) begin + CurrentState = UpdateDR; + jtag_state_name = "UpdateDR"; + end + end + + PauseDR: + begin + if(TMS == 1) begin + CurrentState = Exit2DR; + jtag_state_name = "Exit2DR"; + end + end + + Exit2DR: + begin + if(TMS == 0) begin + CurrentState = ShiftDR; + jtag_state_name = "ShiftDR"; + end + else if(TMS == 1) begin + CurrentState = UpdateDR; + jtag_state_name = "UpdateDR"; + end + end + + UpdateDR: + begin + if(TMS == 0) begin + CurrentState = RunTestIdle; + jtag_state_name = "RunTestIdle"; + end + else if(TMS == 1) begin + CurrentState = SelectDRScan; + jtag_state_name = "SelectDRScan"; + end + end + //------------------------------- + // ------ IR path --------------- + // ------------------------------- + SelectIRScan: + begin + if(TMS == 0) begin + CurrentState = CaptureIR; + jtag_state_name = "CaptureIR"; + end + else if(TMS == 1) begin + CurrentState = TestLogicReset; + jtag_state_name = "TestLogicReset"; + end + end + + CaptureIR: + begin + if(TMS == 0) begin + CurrentState = ShiftIR; + jtag_state_name = "ShiftIR"; + end + else if(TMS == 1) begin + CurrentState = Exit1IR; + jtag_state_name = "Exit1IR"; + end + end + + ShiftIR: + begin +// ClkIR_sig = 1; + + if(TMS == 1) begin + CurrentState = Exit1IR; + jtag_state_name = "Exit1IR"; + end + end + + Exit1IR: + begin + if(TMS == 0) begin + CurrentState = PauseIR; + jtag_state_name = "PauseIR"; + end + else if(TMS == 1) begin + CurrentState = UpdateIR; + jtag_state_name = "UpdateIR"; + end + end + + PauseIR: + begin + if(TMS == 1) begin + CurrentState = Exit2IR; + jtag_state_name = "Exit2IR"; + end + end + + Exit2IR: + begin + if(TMS == 0) begin + CurrentState = ShiftIR; + jtag_state_name = "ShiftIR"; + end + else if(TMS == 1) begin + CurrentState = UpdateIR; + jtag_state_name = "UpdateIR"; + end + end + + UpdateIR: + begin + //-- FP +// ClkIR_sig = 1; + + if(TMS == 0) begin + CurrentState = RunTestIdle; + jtag_state_name = "RunTestIdle"; + end + else if(TMS == 1) begin + CurrentState = SelectDRScan; + jtag_state_name = "SelectDRScan"; + end + end + endcase // case(CurrentState) + end // else + + end // always + +//-------------------------------------------------------- + always@(CurrentState, TCK, TRST) + begin + ClkIR_sig = 1; + + if(TRST == 1 ) begin + Tlrst_sig = #DELAY_SIG 1; + CaptureDR_sig = #DELAY_SIG 0; + ShiftDR_sig = #DELAY_SIG 0; + UpdateDR_sig = #DELAY_SIG 0; + ShiftIR_sig = #DELAY_SIG 0; + UpdateIR_sig = #DELAY_SIG 0; + end + else if(TRST == 0) begin + + case (CurrentState) + TestLogicReset: begin + Tlrst_sig = #DELAY_SIG 1; + Rti_sig = #DELAY_SIG 0; + CaptureDR_sig = #DELAY_SIG 0; + ShiftDR_sig = #DELAY_SIG 0; + UpdateDR_sig = #DELAY_SIG 0; + ShiftIR_sig = #DELAY_SIG 0; + UpdateIR_sig = #DELAY_SIG 0; + end + RunTestIdle: begin + Tlrst_sig = #DELAY_SIG 0; + Rti_sig = #DELAY_SIG 1; + CaptureDR_sig = #DELAY_SIG 0; + ShiftDR_sig = #DELAY_SIG 0; + UpdateDR_sig = #DELAY_SIG 0; + ShiftIR_sig = #DELAY_SIG 0; + UpdateIR_sig = #DELAY_SIG 0; + end + CaptureDR: begin + Tlrst_sig = #DELAY_SIG 0; + Rti_sig = #DELAY_SIG 0; + CaptureDR_sig = #DELAY_SIG 1; + ShiftDR_sig = #DELAY_SIG 0; + UpdateDR_sig = #DELAY_SIG 0; + ShiftIR_sig = #DELAY_SIG 0; + UpdateIR_sig = #DELAY_SIG 0; + end + ShiftDR: begin + Tlrst_sig = #DELAY_SIG 0; + Rti_sig = #DELAY_SIG 0; + CaptureDR_sig = #DELAY_SIG 0; + ShiftDR_sig = #DELAY_SIG 1; + UpdateDR_sig = #DELAY_SIG 0; + ShiftIR_sig = #DELAY_SIG 0; + UpdateIR_sig = #DELAY_SIG 0; + end + UpdateDR: begin + Tlrst_sig = #DELAY_SIG 0; + Rti_sig = #DELAY_SIG 0; + CaptureDR_sig = #DELAY_SIG 0; + ShiftDR_sig = #DELAY_SIG 0; + UpdateDR_sig = #DELAY_SIG 1; + ShiftIR_sig = #DELAY_SIG 0; + UpdateIR_sig = #DELAY_SIG 0; + end + CaptureIR: begin + Tlrst_sig = #DELAY_SIG 0; + Rti_sig = #DELAY_SIG 0; + CaptureDR_sig = #DELAY_SIG 0; + ShiftDR_sig = #DELAY_SIG 0; + UpdateDR_sig = #DELAY_SIG 0; + ShiftIR_sig = #DELAY_SIG 0; + UpdateIR_sig = #DELAY_SIG 0; + ClkIR_sig = TCK; + end + ShiftIR: begin + Tlrst_sig = #DELAY_SIG 0; + Rti_sig = #DELAY_SIG 0; + CaptureDR_sig = #DELAY_SIG 0; + ShiftDR_sig = #DELAY_SIG 0; + UpdateDR_sig = #DELAY_SIG 0; + ShiftIR_sig = #DELAY_SIG 1; + UpdateIR_sig = #DELAY_SIG 0; + ClkIR_sig = TCK; + end + UpdateIR: begin + Tlrst_sig = #DELAY_SIG 0; + Rti_sig = #DELAY_SIG 0; + CaptureDR_sig = #DELAY_SIG 0; + ShiftDR_sig = #DELAY_SIG 0; + UpdateDR_sig = #DELAY_SIG 0; + ShiftIR_sig = #DELAY_SIG 0; + UpdateIR_sig = #DELAY_SIG 1; + end + default: begin + Tlrst_sig = #DELAY_SIG 0; + Rti_sig = #DELAY_SIG 0; + CaptureDR_sig = #DELAY_SIG 0; + ShiftDR_sig = #DELAY_SIG 0; + UpdateDR_sig = #DELAY_SIG 0; + ShiftIR_sig = #DELAY_SIG 0; + UpdateIR_sig = #DELAY_SIG 0; + end + endcase + + end + + end // always(CurrentState) +//----------------------------------------------------- + always@(TCK) + begin +// ClkIR_sig = ShiftIR_sig & TCK; + ClkUpdateIR_sig = UpdateIR_sig & ~TCK; + end // always + + always@(TCK) + begin + ClkID_sig = IDCODE_sig & TCK; + end // always + +// RESET + always@(Tlrst_sig) + begin + glbl.JTAG_RESET_GLBL <= Tlrst_sig; + end + +// RUNTEST + always@(Rti_sig) + begin + glbl.JTAG_RUNTEST_GLBL <= Rti_sig; + end +//-------------- TCK NEGATIVE EDGE activities ---------- + always@(negedge TCK, negedge UpdateDR_sig) + begin + if(TCK == 0) begin + glbl.JTAG_CAPTURE_GLBL <= CaptureDR_sig; + glbl.JTAG_SHIFT_GLBL <= ShiftDR_sig; + TlrstN_sig <= Tlrst_sig; + end + + glbl.JTAG_UPDATE_GLBL <= UpdateDR_sig; + + end // always + +//--#################################################################### +//--##### JtagIR ##### +//--#################################################################### + always@(posedge ClkIR_sig) begin + NextIRreg = {TDI, ir_int[IRLength-1:1]}; + + if ((TRST== 0) && (TlrstN_sig == 0)) begin + if(ShiftIR_sig == 1) begin + ir_int = NextIRreg; + IRegLastBit_sig = ir_int[0]; + end + else begin + ir_int = IR_CAPTURE_VAL; + IRegLastBit_sig = ir_int[0]; + end + end + end //always +//-------------------------------------------------------- + always@(posedge ClkUpdateIR_sig or posedge TlrstN_sig or + posedge TRST) begin + if ((TRST== 1) || (TlrstN_sig == 1)) begin + IRcontent_sig = IDCODE_INSTR[(IRLength - 1): 0]; // IDCODE instr is loaded.. must verify-- FP. + IRegLastBit_sig = ir_int[0]; + end + else if( (TRST == 0) && (TlrstN_sig == 0)) begin + IRcontent_sig = ir_int; + end + end //always +//--#################################################################### +//--##### JtagDecodeIR ##### +//--#################################################################### + always@(IRcontent_sig) begin + + case(IRcontent_sig) + +// IR_CAPTURE_VAL : begin +// ; +// jtag_instruction_name = "IR_CAPTURE"; +// end + + BYPASS_INSTR[(IRLength - 1): 0] : begin + jtag_instruction_name = "BYPASS"; + // if BYPASS instruction, set BYPASS signal to 1 + BYPASS_sig <= 1; + IDCODE_sig <= 0; + USER1_sig <= 0; + USER2_sig <= 0; + USER3_sig <= 0; + USER4_sig <= 0; + end + + IDCODE_INSTR[(IRLength - 1): 0] : begin + jtag_instruction_name = "IDCODE"; + // if IDCODE instruction, set IDCODE signal to 1 + BYPASS_sig <= 0; + IDCODE_sig <= 1; + USER1_sig <= 0; + USER2_sig <= 0; + USER3_sig <= 0; + USER4_sig <= 0; + end + + USER1_INSTR[(IRLength - 1): 0] : begin + jtag_instruction_name = "USER1"; + // if USER1 instruction, set USER1 signal to 1 + BYPASS_sig <= 0; + IDCODE_sig <= 0; + USER1_sig <= 1; + USER2_sig <= 0; + USER3_sig <= 0; + USER4_sig <= 0; + end + + USER2_INSTR[(IRLength - 1): 0] : begin + jtag_instruction_name = "USER2"; + // if USER2 instruction, set USER2 signal to 1 + BYPASS_sig <= 0; + IDCODE_sig <= 0; + USER1_sig <= 0; + USER2_sig <= 1; + USER3_sig <= 0; + USER4_sig <= 0; + end + + USER3_INSTR[(IRLength - 1): 0] : begin + jtag_instruction_name = "USER3"; + // if USER3 instruction, set USER3 signal to 1 + BYPASS_sig <= 0; + USER1_sig <= 0; + USER2_sig <= 0; + IDCODE_sig <= 0; + USER3_sig <= 1; + USER4_sig <= 0; + end + + USER4_INSTR[(IRLength - 1): 0] : begin + jtag_instruction_name = "USER4"; + // if USER4 instruction, set USER4 signal to 1 + BYPASS_sig <= 0; + IDCODE_sig <= 0; + USER1_sig <= 0; + USER2_sig <= 0; + USER3_sig <= 0; + USER4_sig <= 1; + end + default : begin + jtag_instruction_name = "UNKNOWN"; + // if UNKNOWN instruction, set all signals to 0 + BYPASS_sig <= 0; + IDCODE_sig <= 0; + USER1_sig <= 0; + USER2_sig <= 0; + USER3_sig <= 0; + USER4_sig <= 0; + end + + endcase + end //always +//--#################################################################### +//--##### JtagIDCODE ##### +//--#################################################################### + always@(posedge ClkID_sig) begin +// reg [(IDLength -1) : 0] IDreg; + if(ShiftDR_sig == 1) begin + IDreg = IDreg >> 1; + IDreg[IDLength -1] = TDI; + end + else + IDreg = IDCODEval_sig; + + IDregLastBit_sig = IDreg[0]; + end // always + +//--#################################################################### +//--##### JtagSetGlobalSignals ##### +//--#################################################################### + always@(ClkUpdateIR_sig, Tlrst_sig, USER1_sig, USER2_sig, USER3_sig, USER4_sig) begin + if(Tlrst_sig == 1) begin + glbl.JTAG_SEL1_GLBL <= 0; + glbl.JTAG_SEL2_GLBL <= 0; + glbl.JTAG_SEL3_GLBL <= 0; + glbl.JTAG_SEL4_GLBL <= 0; + end + else if(Tlrst_sig == 0) begin + if(USER1_sig == 1) begin + glbl.JTAG_SEL1_GLBL <= USER1_sig; + glbl.JTAG_SEL2_GLBL <= 0; + glbl.JTAG_SEL3_GLBL <= 0; + glbl.JTAG_SEL4_GLBL <= 0; + end + else if(USER2_sig == 1) begin + glbl.JTAG_SEL1_GLBL <= 0; + glbl.JTAG_SEL2_GLBL <= 1; + glbl.JTAG_SEL3_GLBL <= 0; + glbl.JTAG_SEL4_GLBL <= 0; + end + else if(USER3_sig == 1) begin + glbl.JTAG_SEL1_GLBL <= 0; + glbl.JTAG_SEL2_GLBL <= 0; + glbl.JTAG_SEL3_GLBL <= 1; + glbl.JTAG_SEL4_GLBL <= 0; + end + else if(USER4_sig == 1) begin + glbl.JTAG_SEL1_GLBL <= 0; + glbl.JTAG_SEL2_GLBL <= 0; + glbl.JTAG_SEL3_GLBL <= 0; + glbl.JTAG_SEL4_GLBL <= 1; + end + else if(ClkUpdateIR_sig == 1) begin + glbl.JTAG_SEL1_GLBL <= 0; + glbl.JTAG_SEL2_GLBL <= 0; + glbl.JTAG_SEL3_GLBL <= 0; + glbl.JTAG_SEL4_GLBL <= 0; + end + + end + + end //always + +//--#################################################################### +//--##### OUTPUT ##### +//--#################################################################### + assign glbl.JTAG_TDI_GLBL = TDI; + assign glbl.JTAG_TCK_GLBL = TCK; + assign glbl.JTAG_TMS_GLBL = TMS; + + always@(CurrentState, IRcontent_sig, BypassReg, + IRegLastBit_sig, IDregLastBit_sig, glbl.JTAG_USER_TDO1_GLBL, + glbl.JTAG_USER_TDO2_GLBL, glbl.JTAG_USER_TDO3_GLBL, + glbl.JTAG_USER_TDO4_GLBL) + begin + case (CurrentState) + ShiftIR: begin + TDO_latch <= IRegLastBit_sig; + end + ShiftDR: begin + if(IRcontent_sig == IDCODE_INSTR[(IRLength - 1): 0]) + TDO_latch <= IDregLastBit_sig; + else if(IRcontent_sig == BYPASS_INSTR[(IRLength - 1): 0]) + TDO_latch <= BypassReg; + else if(IRcontent_sig == USER1_INSTR[(IRLength - 1): 0]) + TDO_latch <= glbl.JTAG_USER_TDO1_GLBL; + else if(IRcontent_sig == USER2_INSTR[(IRLength - 1): 0]) + TDO_latch <= glbl.JTAG_USER_TDO2_GLBL; + else if(IRcontent_sig == USER3_INSTR[(IRLength - 1): 0]) + TDO_latch <= glbl.JTAG_USER_TDO3_GLBL; + else if(IRcontent_sig == USER4_INSTR[(IRLength - 1): 0]) + TDO_latch <= glbl.JTAG_USER_TDO4_GLBL; + else + TDO_latch <= 1'bz; + end + default : begin + TDO_latch <= 1'bz; + end + endcase // case(PART_NAME) + end // always + + always@(negedge TCK) + begin +// 213980 NCsim compile error fix + TDO <= # 6000 TDO_latch; + end // always + +//--#################################################################### +//--##### Timing ##### +//--#################################################################### + + specify +// 213980 NCsim compile error fix +// (TCK => TDO) = (6000:6000:6000, 6000:6000:6000); + + $setuphold (posedge TCK, posedge TDI , 1000:1000:1000, 2000:2000:2000, notifier); + $setuphold (posedge TCK, negedge TDI , 1000:1000:1000, 2000:2000:2000, notifier); + + $setuphold (posedge TCK, posedge TMS , 1000:1000:1000, 2000:2000:2000, notifier); + $setuphold (posedge TCK, negedge TMS , 1000:1000:1000, 2000:2000:2000, notifier); + endspecify + +endmodule // JTAG_SIM_SPARTAN6 diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/JTAG_SIM_VIRTEX4.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/JTAG_SIM_VIRTEX4.v new file mode 100644 index 0000000..7047a17 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/JTAG_SIM_VIRTEX4.v @@ -0,0 +1,703 @@ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Timing Simulation Library Component +// / / Jtag TAP Controler +// /___/ /\ Filename : JTAG_SIM_VIRTEX4.v +// \ \ / \ Timestamp : Thu Jul 25 16:43:55 PST 2004 +// \___\/\___\ +// +// Revision: +// 07/25/04 - Initial version. +// 07/09/05 - CR 211337 -- made RESET be active on the "+" edge of TCK +// 07/20/05 - CR 212040 Added Timing +// 08/04/05 - CR 213890 NCsim compile error fix for TCK => TDO timing construct +// i.e TDO being a reg. +// 09/14/08 - CR 481520 -- added global TMS +// 03/11/09 - CR 508358 -- removed fx200 support +// End Revision + +`timescale 1 ps/1 ps + +module JTAG_SIM_VIRTEX4( TDO, TCK, TDI, TMS ); + + + output TDO; + + input TCK, TDI, TMS; + + reg TDO; + reg notifier; + + + parameter PART_NAME = "LX15"; + + localparam TestLogicReset = 4'h0, + RunTestIdle = 4'h1, + SelectDRScan = 4'h2, + CaptureDR = 4'h3, + ShiftDR = 4'h4, + Exit1DR = 4'h5, + PauseDR = 4'h6, + Exit2DR = 4'h7, + UpdateDR = 4'h8, + SelectIRScan = 4'h9, + CaptureIR = 4'ha, + ShiftIR = 4'hb, + Exit1IR = 4'hc, + PauseIR = 4'hd, + Exit2IR = 4'he, + UpdateIR = 4'hf; + + localparam DELAY_SIG = 1; + + reg TRST = 0; + + reg [3:0] CurrentState = TestLogicReset; + reg [14*8:0] jtag_state_name = "TestLogicReset"; + reg [14*8:0] jtag_instruction_name = "IDCODE"; + + +//----------------- Virtex4 Specific Constants --------- + localparam IRLengthMax = 14; + localparam IDLength = 32; + + reg [IRLengthMax-1:0] IR_CAPTURE_VAL = 14'b11111111010001, + BYPASS_INSTR = 14'b11111111111111, + IDCODE_INSTR = 14'b11111111001001, + USER1_INSTR = 14'b11111111000010, + USER2_INSTR = 14'b11111111000011, + USER3_INSTR = 14'b11111111100010, + USER4_INSTR = 14'b11111111100011; + + localparam IRLength = ((PART_NAME == "LX15") || (PART_NAME == "lx15") || + (PART_NAME == "LX25") || (PART_NAME == "lx25") || + (PART_NAME == "LX40") || (PART_NAME == "lx40") || + (PART_NAME == "LX60") || (PART_NAME == "lx40") || + (PART_NAME == "LX80") || (PART_NAME == "lx80") || + (PART_NAME == "LX100") || (PART_NAME == "lx100") || + (PART_NAME == "LX160") || (PART_NAME == "lx160") || + (PART_NAME == "LX200") || (PART_NAME == "lx200") || + (PART_NAME == "SX25") || (PART_NAME == "sx25") || + (PART_NAME == "SX35") || (PART_NAME == "sx35") || + (PART_NAME == "SX55") || (PART_NAME == "sx55") || + (PART_NAME == "FX12") || (PART_NAME == "fx12") || + (PART_NAME == "FX20") || (PART_NAME == "fx20")) ? 10 : 14; +//----------------- local reg ------------------------------- + reg CaptureDR_sig = 0, RESET_sig = 0, ShiftDR_sig = 0, UpdateDR_sig = 0; + + reg ClkIR_active = 0, ClkIR_sig = 0, ClkID_sig = 0; + + reg ShiftIR_sig, UpdateIR_sig, ClkUpdateIR_sig; + + reg [IRLength-1:0] IRcontent_sig; + + reg [IDLength-1:0] IDCODEval_sig; + + reg BypassReg = 0, BYPASS_sig = 0, IDCODE_sig = 0, + USER1_sig = 0, USER2_sig = 0, + USER3_sig = 0, USER4_sig = 0; + + reg TDO_latch; + + reg Tlrst_sig = 1; + reg TlrstN_sig = 1; + + reg IRegLastBit_sig = 0, IDregLastBit_sig = 0; + + //------------------------------------------------------------- + reg [IRLength-1:0] NextIRreg; + reg [IRLength-1:0] ir_int; // = IR_CAPTURE_VAL[IRLength-1:0] ; + reg [IDLength-1:0] IDreg; + +//#################################################################### +//##### Initialize ##### +//#################################################################### + initial begin + case (PART_NAME) + "LX15", "lx15" : IDCODEval_sig <= 32'hx1658093; + "LX25", "lx25" : IDCODEval_sig <= 32'hx167C093; + "LX40", "lx40" : IDCODEval_sig <= 32'hx16A4093; + "LX60", "lx60" : IDCODEval_sig <= 32'hx16B4093; + "LX80", "lx80" : IDCODEval_sig <= 32'hx16D8093; + "LX100", "lx100" : IDCODEval_sig <= 32'hx1700093; + "LX160", "lx160" : IDCODEval_sig <= 32'hx1718093; + "LX200", "lx200" : IDCODEval_sig <= 32'hx1734093; + "SX25", "sx25" : IDCODEval_sig <= 32'hx2068093; + "SX35", "sx35" : IDCODEval_sig <= 32'hx2088093; + "SX55", "sx55" : IDCODEval_sig <= 32'hx20B0093; + "FX12", "fx12" : IDCODEval_sig <= 32'hx1E58093; + "FX20", "fx20" : IDCODEval_sig <= 32'hx1E64093; + "FX40", "fx40" : IDCODEval_sig <= 32'hx1E8C093; + "FX60", "fx60" : IDCODEval_sig <= 32'hx1EB4093; + "FX100", "fx100" : IDCODEval_sig <= 32'hx1EE4093; + "FX140", "fx140" : IDCODEval_sig <= 32'hx1F14093; + default : begin + $display("Attribute Syntax Error : The attribute PART_NAME on JTAG_SIM_VIRTEX4 instance %m is set to %s. The legal values for this attributes are LX15, LX25, LX40, LX60, LX80, LX100, LX160, LX200, SX25, SX35, SX55, FX12, FX20, FX40, FX60, FX100 or FX140" , PART_NAME); + end + endcase // case(PART_NAME) + + ir_int <= IR_CAPTURE_VAL[IRLength-1:0]; + + end // initial begin +//#################################################################### +//##### JtagTapSM ##### +//#################################################################### + always@(posedge TCK or posedge TRST) + begin + if(TRST) begin + CurrentState = TestLogicReset; + end + else begin + case(CurrentState) + + TestLogicReset: + begin + if(TMS == 0) begin + CurrentState = RunTestIdle; + jtag_state_name = "RunTestIdle"; + end + end + + RunTestIdle: + begin + if(TMS == 1) begin + CurrentState = SelectDRScan; + jtag_state_name = "SelectDRScan"; + end + end + //------------------------------- + // ------ DR path --------------- + // ------------------------------- + SelectDRScan: + begin + if(TMS == 0) begin + CurrentState = CaptureDR; + jtag_state_name = "CaptureDR"; + end + else if(TMS == 1) begin + CurrentState = SelectIRScan; + jtag_state_name = "SelectIRScan"; + end + end + + CaptureDR: + begin + if(TMS == 0) begin + CurrentState = ShiftDR; + jtag_state_name = "ShiftDR"; + end + else if(TMS == 1) begin + CurrentState = Exit1DR; + jtag_state_name = "Exit1DR"; + end + end + + ShiftDR: + begin + if(IRcontent_sig == BYPASS_INSTR[(IRLength - 1): 0]) + BypassReg = TDI; + + if(TMS == 1) begin + CurrentState = Exit1DR; + jtag_state_name = "Exit1DR"; + end + end + + Exit1DR: + begin + if(TMS == 0) begin + CurrentState = PauseDR; + jtag_state_name = "PauseDR"; + end + else if(TMS == 1) begin + CurrentState = UpdateDR; + jtag_state_name = "UpdateDR"; + end + end + + PauseDR: + begin + if(TMS == 1) begin + CurrentState = Exit2DR; + jtag_state_name = "Exit2DR"; + end + end + + Exit2DR: + begin + if(TMS == 0) begin + CurrentState = ShiftDR; + jtag_state_name = "ShiftDR"; + end + else if(TMS == 1) begin + CurrentState = UpdateDR; + jtag_state_name = "UpdateDR"; + end + end + + UpdateDR: + begin + if(TMS == 0) begin + CurrentState = RunTestIdle; + jtag_state_name = "RunTestIdle"; + end + else if(TMS == 1) begin + CurrentState = SelectDRScan; + jtag_state_name = "SelectDRScan"; + end + end + //------------------------------- + // ------ IR path --------------- + // ------------------------------- + SelectIRScan: + begin + if(TMS == 0) begin + CurrentState = CaptureIR; + jtag_state_name = "CaptureIR"; + end + else if(TMS == 1) begin + CurrentState = TestLogicReset; + jtag_state_name = "TestLogicReset"; + end + end + + CaptureIR: + begin + if(TMS == 0) begin + CurrentState = ShiftIR; + jtag_state_name = "ShiftIR"; + end + else if(TMS == 1) begin + CurrentState = Exit1IR; + jtag_state_name = "Exit1IR"; + end + end + + ShiftIR: + begin +// ClkIR_sig = 1; + + if(TMS == 1) begin + CurrentState = Exit1IR; + jtag_state_name = "Exit1IR"; + end + end + + Exit1IR: + begin + if(TMS == 0) begin + CurrentState = PauseIR; + jtag_state_name = "PauseIR"; + end + else if(TMS == 1) begin + CurrentState = UpdateIR; + jtag_state_name = "UpdateIR"; + end + end + + PauseIR: + begin + if(TMS == 1) begin + CurrentState = Exit2IR; + jtag_state_name = "Exit2IR"; + end + end + + Exit2IR: + begin + if(TMS == 0) begin + CurrentState = ShiftIR; + jtag_state_name = "ShiftIR"; + end + else if(TMS == 1) begin + CurrentState = UpdateIR; + jtag_state_name = "UpdateIR"; + end + end + + UpdateIR: + begin + //-- FP +// ClkIR_sig = 1; + + if(TMS == 0) begin + CurrentState = RunTestIdle; + jtag_state_name = "RunTestIdle"; + end + else if(TMS == 1) begin + CurrentState = SelectDRScan; + jtag_state_name = "SelectDRScan"; + end + end + endcase // case(CurrentState) + end // else + + end // always + +//-------------------------------------------------------- + always@(CurrentState, TCK, TRST) + begin + ClkIR_sig = 1; + + if(TRST == 1 ) begin + Tlrst_sig = #DELAY_SIG 1; + CaptureDR_sig = #DELAY_SIG 0; + ShiftDR_sig = #DELAY_SIG 0; + UpdateDR_sig = #DELAY_SIG 0; + ShiftIR_sig = #DELAY_SIG 0; + UpdateIR_sig = #DELAY_SIG 0; + end + else if(TRST == 0) begin + + case (CurrentState) + TestLogicReset: begin + Tlrst_sig = #DELAY_SIG 1; + CaptureDR_sig = #DELAY_SIG 0; + ShiftDR_sig = #DELAY_SIG 0; + UpdateDR_sig = #DELAY_SIG 0; + ShiftIR_sig = #DELAY_SIG 0; + UpdateIR_sig = #DELAY_SIG 0; + end + CaptureDR: begin + Tlrst_sig = #DELAY_SIG 0; + CaptureDR_sig = #DELAY_SIG 1; + ShiftDR_sig = #DELAY_SIG 0; + UpdateDR_sig = #DELAY_SIG 0; + ShiftIR_sig = #DELAY_SIG 0; + UpdateIR_sig = #DELAY_SIG 0; + end + ShiftDR: begin + Tlrst_sig = #DELAY_SIG 0; + CaptureDR_sig = #DELAY_SIG 0; + ShiftDR_sig = #DELAY_SIG 1; + UpdateDR_sig = #DELAY_SIG 0; + ShiftIR_sig = #DELAY_SIG 0; + UpdateIR_sig = #DELAY_SIG 0; + end + UpdateDR: begin + Tlrst_sig = #DELAY_SIG 0; + CaptureDR_sig = #DELAY_SIG 0; + ShiftDR_sig = #DELAY_SIG 0; + UpdateDR_sig = #DELAY_SIG 1; + ShiftIR_sig = #DELAY_SIG 0; + UpdateIR_sig = #DELAY_SIG 0; + end + CaptureIR: begin + Tlrst_sig = #DELAY_SIG 0; + CaptureDR_sig = #DELAY_SIG 0; + ShiftDR_sig = #DELAY_SIG 0; + UpdateDR_sig = #DELAY_SIG 0; + ShiftIR_sig = #DELAY_SIG 0; + UpdateIR_sig = #DELAY_SIG 0; + ClkIR_sig = TCK; + end + ShiftIR: begin + Tlrst_sig = #DELAY_SIG 0; + CaptureDR_sig = #DELAY_SIG 0; + ShiftDR_sig = #DELAY_SIG 0; + UpdateDR_sig = #DELAY_SIG 0; + ShiftIR_sig = #DELAY_SIG 1; + UpdateIR_sig = #DELAY_SIG 0; + ClkIR_sig = TCK; + end + UpdateIR: begin + Tlrst_sig = #DELAY_SIG 0; + CaptureDR_sig = #DELAY_SIG 0; + ShiftDR_sig = #DELAY_SIG 0; + UpdateDR_sig = #DELAY_SIG 0; + ShiftIR_sig = #DELAY_SIG 0; + UpdateIR_sig = #DELAY_SIG 1; + end + default: begin + Tlrst_sig = #DELAY_SIG 0; + CaptureDR_sig = #DELAY_SIG 0; + ShiftDR_sig = #DELAY_SIG 0; + UpdateDR_sig = #DELAY_SIG 0; + ShiftIR_sig = #DELAY_SIG 0; + UpdateIR_sig = #DELAY_SIG 0; + end + endcase + + end + + end // always(CurrentState) +//----------------------------------------------------- + always@(TCK) + begin +// ClkIR_sig = ShiftIR_sig & TCK; + ClkUpdateIR_sig = UpdateIR_sig & ~TCK; + end // always + + always@(TCK) + begin + ClkID_sig = IDCODE_sig & TCK; + end // always + + +// CR 211377 Reset should go high in State Tlrst + always@(Tlrst_sig) + begin + glbl.JTAG_RESET_GLBL <= Tlrst_sig; + end + +//-------------- TCK NEGATIVE EDGE activities ---------- + always@(negedge TCK, negedge UpdateDR_sig) + begin + if(TCK == 0) begin + glbl.JTAG_CAPTURE_GLBL <= CaptureDR_sig; + // CR 211377 Reset should go high in State Tlrst + // glbl.JTAG_RESET_GLBL <= Tlrst_sig; + glbl.JTAG_SHIFT_GLBL <= ShiftDR_sig; + TlrstN_sig <= Tlrst_sig; + end + + glbl.JTAG_UPDATE_GLBL <= UpdateDR_sig; + + end // always + +//--#################################################################### +//--##### JtagIR ##### +//--#################################################################### + always@(posedge ClkIR_sig) begin + NextIRreg = {TDI, ir_int[IRLength-1:1]}; + + if ((TRST== 0) && (TlrstN_sig == 0)) begin + if(ShiftIR_sig == 1) begin + ir_int = NextIRreg; + IRegLastBit_sig = ir_int[0]; + end + else begin + ir_int = IR_CAPTURE_VAL; + IRegLastBit_sig = ir_int[0]; + end + end + end //always +//-------------------------------------------------------- + always@(posedge ClkUpdateIR_sig or posedge TlrstN_sig or + posedge TRST) begin + if ((TRST== 1) || (TlrstN_sig == 1)) begin + IRcontent_sig = IDCODE_INSTR[(IRLength - 1): 0]; // IDCODE instr is loaded.. must verify-- FP. + IRegLastBit_sig = ir_int[0]; + end + else if( (TRST == 0) && (TlrstN_sig == 0)) begin + IRcontent_sig = ir_int; + end + end //always +//--#################################################################### +//--##### JtagDecodeIR ##### +//--#################################################################### + always@(IRcontent_sig) begin + + case(IRcontent_sig) + +// IR_CAPTURE_VAL : begin +// ; +// jtag_instruction_name = "IR_CAPTURE"; +// end + + BYPASS_INSTR[(IRLength - 1): 0] : begin + jtag_instruction_name = "BYPASS"; + // if BYPASS instruction, set BYPASS signal to 1 + BYPASS_sig <= 1; + IDCODE_sig <= 0; + USER1_sig <= 0; + USER2_sig <= 0; + USER3_sig <= 0; + USER4_sig <= 0; + end + + IDCODE_INSTR[(IRLength - 1): 0] : begin + jtag_instruction_name = "IDCODE"; + // if IDCODE instruction, set IDCODE signal to 1 + BYPASS_sig <= 0; + IDCODE_sig <= 1; + USER1_sig <= 0; + USER2_sig <= 0; + USER3_sig <= 0; + USER4_sig <= 0; + end + + USER1_INSTR[(IRLength - 1): 0] : begin + jtag_instruction_name = "USER1"; + // if USER1 instruction, set USER1 signal to 1 + BYPASS_sig <= 0; + IDCODE_sig <= 0; + USER1_sig <= 1; + USER2_sig <= 0; + USER3_sig <= 0; + USER4_sig <= 0; + end + + USER2_INSTR[(IRLength - 1): 0] : begin + jtag_instruction_name = "USER2"; + // if USER2 instruction, set USER2 signal to 1 + BYPASS_sig <= 0; + IDCODE_sig <= 0; + USER1_sig <= 0; + USER2_sig <= 1; + USER3_sig <= 0; + USER4_sig <= 0; + end + + USER3_INSTR[(IRLength - 1): 0] : begin + jtag_instruction_name = "USER3"; + // if USER3 instruction, set USER3 signal to 1 + BYPASS_sig <= 0; + USER1_sig <= 0; + USER2_sig <= 0; + IDCODE_sig <= 0; + USER3_sig <= 1; + USER4_sig <= 0; + end + + USER4_INSTR[(IRLength - 1): 0] : begin + jtag_instruction_name = "USER4"; + // if USER4 instruction, set USER4 signal to 1 + BYPASS_sig <= 0; + IDCODE_sig <= 0; + USER1_sig <= 0; + USER2_sig <= 0; + USER3_sig <= 0; + USER4_sig <= 1; + end + default : begin + jtag_instruction_name = "UNKNOWN"; + // if UNKNOWN instruction, set all signals to 0 + BYPASS_sig <= 0; + IDCODE_sig <= 0; + USER1_sig <= 0; + USER2_sig <= 0; + USER3_sig <= 0; + USER4_sig <= 0; + end + + endcase + end //always +//--#################################################################### +//--##### JtagIDCODE ##### +//--#################################################################### + always@(posedge ClkID_sig) begin +// reg [(IDLength -1) : 0] IDreg; + if(ShiftDR_sig == 1) begin + IDreg = IDreg >> 1; + IDreg[IDLength -1] = TDI; + end + else + IDreg = IDCODEval_sig; + + IDregLastBit_sig = IDreg[0]; + end // always + +//--#################################################################### +//--##### JtagSetGlobalSignals ##### +//--#################################################################### + always@(ClkUpdateIR_sig, Tlrst_sig, USER1_sig, USER2_sig, USER3_sig, USER4_sig) begin + if(Tlrst_sig == 1) begin + glbl.JTAG_SEL1_GLBL <= 0; + glbl.JTAG_SEL2_GLBL <= 0; + glbl.JTAG_SEL3_GLBL <= 0; + glbl.JTAG_SEL4_GLBL <= 0; + end + else if(Tlrst_sig == 0) begin + if(USER1_sig == 1) begin + glbl.JTAG_SEL1_GLBL <= USER1_sig; + glbl.JTAG_SEL2_GLBL <= 0; + glbl.JTAG_SEL3_GLBL <= 0; + glbl.JTAG_SEL4_GLBL <= 0; + end + else if(USER2_sig == 1) begin + glbl.JTAG_SEL1_GLBL <= 0; + glbl.JTAG_SEL2_GLBL <= 1; + glbl.JTAG_SEL3_GLBL <= 0; + glbl.JTAG_SEL4_GLBL <= 0; + end + else if(USER3_sig == 1) begin + glbl.JTAG_SEL1_GLBL <= 0; + glbl.JTAG_SEL2_GLBL <= 0; + glbl.JTAG_SEL3_GLBL <= 1; + glbl.JTAG_SEL4_GLBL <= 0; + end + else if(USER4_sig == 1) begin + glbl.JTAG_SEL1_GLBL <= 0; + glbl.JTAG_SEL2_GLBL <= 0; + glbl.JTAG_SEL3_GLBL <= 0; + glbl.JTAG_SEL4_GLBL <= 1; + end + else if(ClkUpdateIR_sig == 1) begin + glbl.JTAG_SEL1_GLBL <= 0; + glbl.JTAG_SEL2_GLBL <= 0; + glbl.JTAG_SEL3_GLBL <= 0; + glbl.JTAG_SEL4_GLBL <= 0; + end + + end + + end //always + +//--#################################################################### +//--##### OUTPUT ##### +//--#################################################################### + assign glbl.JTAG_TDI_GLBL = TDI; + assign glbl.JTAG_TCK_GLBL = TCK; + assign glbl.JTAG_TMS_GLBL = TMS; + + always@(CurrentState, IRcontent_sig, BypassReg, + IRegLastBit_sig, IDregLastBit_sig, glbl.JTAG_USER_TDO1_GLBL, + glbl.JTAG_USER_TDO2_GLBL, glbl.JTAG_USER_TDO3_GLBL, + glbl.JTAG_USER_TDO4_GLBL) + begin + case (CurrentState) + ShiftIR: begin + TDO_latch <= IRegLastBit_sig; + end + ShiftDR: begin + if(IRcontent_sig == IDCODE_INSTR[(IRLength - 1): 0]) + TDO_latch <= IDregLastBit_sig; + else if(IRcontent_sig == BYPASS_INSTR[(IRLength - 1): 0]) + TDO_latch <= BypassReg; + else if(IRcontent_sig == USER1_INSTR[(IRLength - 1): 0]) + TDO_latch <= glbl.JTAG_USER_TDO1_GLBL; + else if(IRcontent_sig == USER2_INSTR[(IRLength - 1): 0]) + TDO_latch <= glbl.JTAG_USER_TDO2_GLBL; + else if(IRcontent_sig == USER3_INSTR[(IRLength - 1): 0]) + TDO_latch <= glbl.JTAG_USER_TDO3_GLBL; + else if(IRcontent_sig == USER4_INSTR[(IRLength - 1): 0]) + TDO_latch <= glbl.JTAG_USER_TDO4_GLBL; + else + TDO_latch <= 1'bz; + end + default : begin + TDO_latch <= 1'bz; + end + endcase // case(PART_NAME) + end // always + + always@(negedge TCK) + begin +// 213980 NCsim compile error fix + TDO <= # 6000 TDO_latch; + end // always + +//--#################################################################### +//--##### Timing ##### +//--#################################################################### + + specify +// +// 213980 NCsim compile error fix +// (TCK => TDO) = (6000:6000:6000, 6000:6000:6000); + + $setuphold (posedge TCK, posedge TDI , 1000:1000:1000, 2000:2000:2000, notifier); + $setuphold (posedge TCK, negedge TDI , 1000:1000:1000, 2000:2000:2000, notifier); + + $setuphold (posedge TCK, posedge TMS , 1000:1000:1000, 2000:2000:2000, notifier); + $setuphold (posedge TCK, negedge TMS , 1000:1000:1000, 2000:2000:2000, notifier); + endspecify + +endmodule // JTAG_SIM_VIRTEX4 diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/JTAG_SIM_VIRTEX5.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/JTAG_SIM_VIRTEX5.v new file mode 100644 index 0000000..58ef9ca --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/JTAG_SIM_VIRTEX5.v @@ -0,0 +1,733 @@ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2005 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Timing Simulation Library Component +// / / Jtag TAP Controler +// /___/ /\ Filename : JTAG_SIM_VIRTEX5.v +// \ \ / \ Timestamp : Tue Nov 1 14:38:19 PST 2005 +// \___\/\___\ +// +// Revision: +// 11/01/05 - Initial version. +// 06/04/08 - CR 473578 fix. Made PartNames consistent by removing "5V" from the prefix. +// 09/14/08 - CR 481520 -- added global TMS +// 02/17/09 - CR 508358 -- Added support for SXT, FXT and TXT devices +// End Revision + +`timescale 1 ps/1 ps + +module JTAG_SIM_VIRTEX5( TDO, TCK, TDI, TMS ); + + + output TDO; + + input TCK, TDI, TMS; + + reg TDO; + reg notifier; + + + parameter PART_NAME = "LX30"; + + localparam TestLogicReset = 4'h0, + RunTestIdle = 4'h1, + SelectDRScan = 4'h2, + CaptureDR = 4'h3, + ShiftDR = 4'h4, + Exit1DR = 4'h5, + PauseDR = 4'h6, + Exit2DR = 4'h7, + UpdateDR = 4'h8, + SelectIRScan = 4'h9, + CaptureIR = 4'ha, + ShiftIR = 4'hb, + Exit1IR = 4'hc, + PauseIR = 4'hd, + Exit2IR = 4'he, + UpdateIR = 4'hf; + + localparam DELAY_SIG = 1; + + reg TRST = 0; + + reg [3:0] CurrentState = TestLogicReset; + reg [14*8:0] jtag_state_name = "TestLogicReset"; + reg [14*8:0] jtag_instruction_name = "IDCODE"; + + +//----------------- Virtex4 Specific Constants --------- + localparam IRLengthMax = 14; + localparam IDLength = 32; + + reg [IRLengthMax-1:0] IR_CAPTURE_VAL = 14'b11111111010001, + BYPASS_INSTR = 14'b11111111111111, + IDCODE_INSTR = 14'b11111111001001, + USER1_INSTR = 14'b11111111000010, + USER2_INSTR = 14'b11111111000011, + USER3_INSTR = 14'b11111111100010, + USER4_INSTR = 14'b11111111100011; +/* + localparam IRLength = ((PART_NAME == "LX30") || (PART_NAME == "lx30") || + (PART_NAME == "LX50") || (PART_NAME == "lx50") || + (PART_NAME == "LX85") || (PART_NAME == "lx85") || + (PART_NAME == "LX110") || (PART_NAME == "lx110") || + (PART_NAME == "LX220") || (PART_NAME == "lx220") || + (PART_NAME == "LX330") || (PART_NAME == "lx330") || + (PART_NAME == "LX30T") || (PART_NAME == "lx30t") || + (PART_NAME == "LX50T") || (PART_NAME == "lx50t") || + (PART_NAME == "LX85T") || (PART_NAME == "lx85t") || + (PART_NAME == "LX110T") || (PART_NAME == "lx110t") || + (PART_NAME == "LX220T") || (PART_NAME == "lx220t") || + (PART_NAME == "LX330T") || (PART_NAME == "lx330t")) ? 10 : 14; +*/ + localparam IRLength = ( + (PART_NAME == "FX30T") || (PART_NAME == "fx30t") || + (PART_NAME == "FX70T") || (PART_NAME == "fx70t") || + (PART_NAME == "LX110") || (PART_NAME == "lx110") || + (PART_NAME == "LX110T") || (PART_NAME == "lx110t") || + (PART_NAME == "LX155") || (PART_NAME == "lx155") || + (PART_NAME == "LX155T") || (PART_NAME == "lx155t") || + (PART_NAME == "LX20T") || (PART_NAME == "lx20t") || + (PART_NAME == "LX220") || (PART_NAME == "lx220") || + (PART_NAME == "LX220T") || (PART_NAME == "lx220t") || + (PART_NAME == "LX30") || (PART_NAME == "lx30") || + (PART_NAME == "LX30T") || (PART_NAME == "lx30t") || + (PART_NAME == "LX330") || (PART_NAME == "lx330") || + (PART_NAME == "LX330T") || (PART_NAME == "lx330t") || + (PART_NAME == "LX50") || (PART_NAME == "lx50") || + (PART_NAME == "LX50T") || (PART_NAME == "lx50t") || + (PART_NAME == "LX85") || (PART_NAME == "lx85") || + (PART_NAME == "LX85T") || (PART_NAME == "lx85t") || + (PART_NAME == "SX240T") || (PART_NAME == "sx240t") || + (PART_NAME == "SX35T") || (PART_NAME == "sx35t") || + (PART_NAME == "SX50T") || (PART_NAME == "sx50t") || + (PART_NAME == "SX95T") || (PART_NAME == "sx95t") || + (PART_NAME == "TX150T") || (PART_NAME == "tx150t") || + (PART_NAME == "TX240T") || (PART_NAME == "tx240t")) ? 10 : 14; + +//----------------- local reg ------------------------------- + reg CaptureDR_sig = 0, RESET_sig = 0, ShiftDR_sig = 0, UpdateDR_sig = 0; + + reg ClkIR_active = 0, ClkIR_sig = 0, ClkID_sig = 0; + + reg ShiftIR_sig, UpdateIR_sig, ClkUpdateIR_sig; + + reg [IRLength-1:0] IRcontent_sig; + + reg [IDLength-1:0] IDCODEval_sig; + + reg BypassReg = 0, BYPASS_sig = 0, IDCODE_sig = 0, + USER1_sig = 0, USER2_sig = 0, + USER3_sig = 0, USER4_sig = 0; + + reg TDO_latch; + + reg Tlrst_sig = 1; + reg TlrstN_sig = 1; + + reg IRegLastBit_sig = 0, IDregLastBit_sig = 0; + + //------------------------------------------------------------- + reg [IRLength-1:0] NextIRreg; + reg [IRLength-1:0] ir_int; // = IR_CAPTURE_VAL[IRLength-1:0] ; + reg [IDLength-1:0] IDreg; + +//#################################################################### +//##### Initialize ##### +//#################################################################### + initial begin + case (PART_NAME) + "FX100T", "fx100t" : IDCODEval_sig <= 32'h032d8093; + "FX130T", "fx130t" : IDCODEval_sig <= 32'h03300093; + "FX200T", "fx200t" : IDCODEval_sig <= 32'h03334093; + "FX30T", "fx30t" : IDCODEval_sig <= 32'h03276093; + "FX70T", "fx70t" : IDCODEval_sig <= 32'h032c6093; + "LX110", "lx110" : IDCODEval_sig <= 32'h028d6093; + "LX110T", "lx110t" : IDCODEval_sig <= 32'h02ad6093; + "LX155", "lx155" : IDCODEval_sig <= 32'h028ec093; + "LX155T", "lx155t" : IDCODEval_sig <= 32'h02aec093; + "LX20T", "lx20t" : IDCODEval_sig <= 32'h02a56093; + "LX220", "lx220" : IDCODEval_sig <= 32'h0290c093; + "LX220T", "lx220t" : IDCODEval_sig <= 32'h02b0c093; + "LX30", "lx30" : IDCODEval_sig <= 32'h0286e093; + "LX30T", "lx30t" : IDCODEval_sig <= 32'h02a6e093; + "LX330", "lx330" : IDCODEval_sig <= 32'h0295c093; + "LX330T", "lx330t" : IDCODEval_sig <= 32'h02b5c093; + "LX50", "lx50" : IDCODEval_sig <= 32'h02896093; + "LX50T", "lx50t" : IDCODEval_sig <= 32'h02a96093; + "LX85", "lx85" : IDCODEval_sig <= 32'h028ae093; + "LX85T", "lx85t" : IDCODEval_sig <= 32'h02aae093; + "SX240T", "sx240t" : IDCODEval_sig <= 32'h02f3e093; + "SX35T", "sx35t" : IDCODEval_sig <= 32'h02e72093; + "SX50T", "sx50t" : IDCODEval_sig <= 32'h02e9a093; + "SX95T", "sx95t" : IDCODEval_sig <= 32'h02ece093; + "TX150T", "tx150t" : IDCODEval_sig <= 32'h04502093; + "TX240T", "tx240t" : IDCODEval_sig <= 32'h0453e093; + default : begin + $display("Attribute Syntax Error : The attribute PART_NAME on JTAG_SIM_VIRTEX5 instance %m is set to %s. The legal values for this attributes are FX100T or FX130T or FX200T or FX30T or FX70T or LX110 or LX110T or LX155 or LX155T or LX20T or LX220 or LX220T or LX30 or LX30T or LX330 or LX330T or LX50 or LX50T or LX85 or LX85T or SX240T or SX35T or SX50T or SX95T or TX150T or TX240TT", PART_NAME); + end + endcase // case(PART_NAME) + + ir_int <= IR_CAPTURE_VAL[IRLength-1:0]; + + end // initial begin +//#################################################################### +//##### JtagTapSM ##### +//#################################################################### + always@(posedge TCK or posedge TRST) + begin + if(TRST) begin + CurrentState = TestLogicReset; + end + else begin + case(CurrentState) + + TestLogicReset: + begin + if(TMS == 0) begin + CurrentState = RunTestIdle; + jtag_state_name = "RunTestIdle"; + end + end + + RunTestIdle: + begin + if(TMS == 1) begin + CurrentState = SelectDRScan; + jtag_state_name = "SelectDRScan"; + end + end + //------------------------------- + // ------ DR path --------------- + // ------------------------------- + SelectDRScan: + begin + if(TMS == 0) begin + CurrentState = CaptureDR; + jtag_state_name = "CaptureDR"; + end + else if(TMS == 1) begin + CurrentState = SelectIRScan; + jtag_state_name = "SelectIRScan"; + end + end + + CaptureDR: + begin + if(TMS == 0) begin + CurrentState = ShiftDR; + jtag_state_name = "ShiftDR"; + end + else if(TMS == 1) begin + CurrentState = Exit1DR; + jtag_state_name = "Exit1DR"; + end + end + + ShiftDR: + begin + if(IRcontent_sig == BYPASS_INSTR[(IRLength - 1): 0]) + BypassReg = TDI; + + if(TMS == 1) begin + CurrentState = Exit1DR; + jtag_state_name = "Exit1DR"; + end + end + + Exit1DR: + begin + if(TMS == 0) begin + CurrentState = PauseDR; + jtag_state_name = "PauseDR"; + end + else if(TMS == 1) begin + CurrentState = UpdateDR; + jtag_state_name = "UpdateDR"; + end + end + + PauseDR: + begin + if(TMS == 1) begin + CurrentState = Exit2DR; + jtag_state_name = "Exit2DR"; + end + end + + Exit2DR: + begin + if(TMS == 0) begin + CurrentState = ShiftDR; + jtag_state_name = "ShiftDR"; + end + else if(TMS == 1) begin + CurrentState = UpdateDR; + jtag_state_name = "UpdateDR"; + end + end + + UpdateDR: + begin + if(TMS == 0) begin + CurrentState = RunTestIdle; + jtag_state_name = "RunTestIdle"; + end + else if(TMS == 1) begin + CurrentState = SelectDRScan; + jtag_state_name = "SelectDRScan"; + end + end + //------------------------------- + // ------ IR path --------------- + // ------------------------------- + SelectIRScan: + begin + if(TMS == 0) begin + CurrentState = CaptureIR; + jtag_state_name = "CaptureIR"; + end + else if(TMS == 1) begin + CurrentState = TestLogicReset; + jtag_state_name = "TestLogicReset"; + end + end + + CaptureIR: + begin + if(TMS == 0) begin + CurrentState = ShiftIR; + jtag_state_name = "ShiftIR"; + end + else if(TMS == 1) begin + CurrentState = Exit1IR; + jtag_state_name = "Exit1IR"; + end + end + + ShiftIR: + begin +// ClkIR_sig = 1; + + if(TMS == 1) begin + CurrentState = Exit1IR; + jtag_state_name = "Exit1IR"; + end + end + + Exit1IR: + begin + if(TMS == 0) begin + CurrentState = PauseIR; + jtag_state_name = "PauseIR"; + end + else if(TMS == 1) begin + CurrentState = UpdateIR; + jtag_state_name = "UpdateIR"; + end + end + + PauseIR: + begin + if(TMS == 1) begin + CurrentState = Exit2IR; + jtag_state_name = "Exit2IR"; + end + end + + Exit2IR: + begin + if(TMS == 0) begin + CurrentState = ShiftIR; + jtag_state_name = "ShiftIR"; + end + else if(TMS == 1) begin + CurrentState = UpdateIR; + jtag_state_name = "UpdateIR"; + end + end + + UpdateIR: + begin + //-- FP +// ClkIR_sig = 1; + + if(TMS == 0) begin + CurrentState = RunTestIdle; + jtag_state_name = "RunTestIdle"; + end + else if(TMS == 1) begin + CurrentState = SelectDRScan; + jtag_state_name = "SelectDRScan"; + end + end + endcase // case(CurrentState) + end // else + + end // always + +//-------------------------------------------------------- + always@(CurrentState, TCK, TRST) + begin + ClkIR_sig = 1; + + if(TRST == 1 ) begin + Tlrst_sig = #DELAY_SIG 1; + CaptureDR_sig = #DELAY_SIG 0; + ShiftDR_sig = #DELAY_SIG 0; + UpdateDR_sig = #DELAY_SIG 0; + ShiftIR_sig = #DELAY_SIG 0; + UpdateIR_sig = #DELAY_SIG 0; + end + else if(TRST == 0) begin + + case (CurrentState) + TestLogicReset: begin + Tlrst_sig = #DELAY_SIG 1; + CaptureDR_sig = #DELAY_SIG 0; + ShiftDR_sig = #DELAY_SIG 0; + UpdateDR_sig = #DELAY_SIG 0; + ShiftIR_sig = #DELAY_SIG 0; + UpdateIR_sig = #DELAY_SIG 0; + end + CaptureDR: begin + Tlrst_sig = #DELAY_SIG 0; + CaptureDR_sig = #DELAY_SIG 1; + ShiftDR_sig = #DELAY_SIG 0; + UpdateDR_sig = #DELAY_SIG 0; + ShiftIR_sig = #DELAY_SIG 0; + UpdateIR_sig = #DELAY_SIG 0; + end + ShiftDR: begin + Tlrst_sig = #DELAY_SIG 0; + CaptureDR_sig = #DELAY_SIG 0; + ShiftDR_sig = #DELAY_SIG 1; + UpdateDR_sig = #DELAY_SIG 0; + ShiftIR_sig = #DELAY_SIG 0; + UpdateIR_sig = #DELAY_SIG 0; + end + UpdateDR: begin + Tlrst_sig = #DELAY_SIG 0; + CaptureDR_sig = #DELAY_SIG 0; + ShiftDR_sig = #DELAY_SIG 0; + UpdateDR_sig = #DELAY_SIG 1; + ShiftIR_sig = #DELAY_SIG 0; + UpdateIR_sig = #DELAY_SIG 0; + end + CaptureIR: begin + Tlrst_sig = #DELAY_SIG 0; + CaptureDR_sig = #DELAY_SIG 0; + ShiftDR_sig = #DELAY_SIG 0; + UpdateDR_sig = #DELAY_SIG 0; + ShiftIR_sig = #DELAY_SIG 0; + UpdateIR_sig = #DELAY_SIG 0; + ClkIR_sig = TCK; + end + ShiftIR: begin + Tlrst_sig = #DELAY_SIG 0; + CaptureDR_sig = #DELAY_SIG 0; + ShiftDR_sig = #DELAY_SIG 0; + UpdateDR_sig = #DELAY_SIG 0; + ShiftIR_sig = #DELAY_SIG 1; + UpdateIR_sig = #DELAY_SIG 0; + ClkIR_sig = TCK; + end + UpdateIR: begin + Tlrst_sig = #DELAY_SIG 0; + CaptureDR_sig = #DELAY_SIG 0; + ShiftDR_sig = #DELAY_SIG 0; + UpdateDR_sig = #DELAY_SIG 0; + ShiftIR_sig = #DELAY_SIG 0; + UpdateIR_sig = #DELAY_SIG 1; + end + default: begin + Tlrst_sig = #DELAY_SIG 0; + CaptureDR_sig = #DELAY_SIG 0; + ShiftDR_sig = #DELAY_SIG 0; + UpdateDR_sig = #DELAY_SIG 0; + ShiftIR_sig = #DELAY_SIG 0; + UpdateIR_sig = #DELAY_SIG 0; + end + endcase + + end + + end // always(CurrentState) +//----------------------------------------------------- + always@(TCK) + begin +// ClkIR_sig = ShiftIR_sig & TCK; + ClkUpdateIR_sig = UpdateIR_sig & ~TCK; + end // always + + always@(TCK) + begin + ClkID_sig = IDCODE_sig & TCK; + end // always + + +// CR 211377 Reset should go high in State Tlrst + always@(Tlrst_sig) + begin + glbl.JTAG_RESET_GLBL <= Tlrst_sig; + end + +//-------------- TCK NEGATIVE EDGE activities ---------- + always@(negedge TCK, negedge UpdateDR_sig) + begin + if(TCK == 0) begin + glbl.JTAG_CAPTURE_GLBL <= CaptureDR_sig; + // CR 211377 Reset should go high in State Tlrst + // glbl.JTAG_RESET_GLBL <= Tlrst_sig; + glbl.JTAG_SHIFT_GLBL <= ShiftDR_sig; + TlrstN_sig <= Tlrst_sig; + end + + glbl.JTAG_UPDATE_GLBL <= UpdateDR_sig; + + end // always + +//--#################################################################### +//--##### JtagIR ##### +//--#################################################################### + always@(posedge ClkIR_sig) begin + NextIRreg = {TDI, ir_int[IRLength-1:1]}; + + if ((TRST== 0) && (TlrstN_sig == 0)) begin + if(ShiftIR_sig == 1) begin + ir_int = NextIRreg; + IRegLastBit_sig = ir_int[0]; + end + else begin + ir_int = IR_CAPTURE_VAL; + IRegLastBit_sig = ir_int[0]; + end + end + end //always +//-------------------------------------------------------- + always@(posedge ClkUpdateIR_sig or posedge TlrstN_sig or + posedge TRST) begin + if ((TRST== 1) || (TlrstN_sig == 1)) begin + IRcontent_sig = IDCODE_INSTR[(IRLength - 1): 0]; // IDCODE instr is loaded.. must verify-- FP. + IRegLastBit_sig = ir_int[0]; + end + else if( (TRST == 0) && (TlrstN_sig == 0)) begin + IRcontent_sig = ir_int; + end + end //always +//--#################################################################### +//--##### JtagDecodeIR ##### +//--#################################################################### + always@(IRcontent_sig) begin + + case(IRcontent_sig) + +// IR_CAPTURE_VAL : begin +// ; +// jtag_instruction_name = "IR_CAPTURE"; +// end + + BYPASS_INSTR[(IRLength - 1): 0] : begin + jtag_instruction_name = "BYPASS"; + // if BYPASS instruction, set BYPASS signal to 1 + BYPASS_sig <= 1; + IDCODE_sig <= 0; + USER1_sig <= 0; + USER2_sig <= 0; + USER3_sig <= 0; + USER4_sig <= 0; + end + + IDCODE_INSTR[(IRLength - 1): 0] : begin + jtag_instruction_name = "IDCODE"; + // if IDCODE instruction, set IDCODE signal to 1 + BYPASS_sig <= 0; + IDCODE_sig <= 1; + USER1_sig <= 0; + USER2_sig <= 0; + USER3_sig <= 0; + USER4_sig <= 0; + end + + USER1_INSTR[(IRLength - 1): 0] : begin + jtag_instruction_name = "USER1"; + // if USER1 instruction, set USER1 signal to 1 + BYPASS_sig <= 0; + IDCODE_sig <= 0; + USER1_sig <= 1; + USER2_sig <= 0; + USER3_sig <= 0; + USER4_sig <= 0; + end + + USER2_INSTR[(IRLength - 1): 0] : begin + jtag_instruction_name = "USER2"; + // if USER2 instruction, set USER2 signal to 1 + BYPASS_sig <= 0; + IDCODE_sig <= 0; + USER1_sig <= 0; + USER2_sig <= 1; + USER3_sig <= 0; + USER4_sig <= 0; + end + + USER3_INSTR[(IRLength - 1): 0] : begin + jtag_instruction_name = "USER3"; + // if USER3 instruction, set USER3 signal to 1 + BYPASS_sig <= 0; + USER1_sig <= 0; + USER2_sig <= 0; + IDCODE_sig <= 0; + USER3_sig <= 1; + USER4_sig <= 0; + end + + USER4_INSTR[(IRLength - 1): 0] : begin + jtag_instruction_name = "USER4"; + // if USER4 instruction, set USER4 signal to 1 + BYPASS_sig <= 0; + IDCODE_sig <= 0; + USER1_sig <= 0; + USER2_sig <= 0; + USER3_sig <= 0; + USER4_sig <= 1; + end + default : begin + jtag_instruction_name = "UNKNOWN"; + // if UNKNOWN instruction, set all signals to 0 + BYPASS_sig <= 0; + IDCODE_sig <= 0; + USER1_sig <= 0; + USER2_sig <= 0; + USER3_sig <= 0; + USER4_sig <= 0; + end + + endcase + end //always +//--#################################################################### +//--##### JtagIDCODE ##### +//--#################################################################### + always@(posedge ClkID_sig) begin +// reg [(IDLength -1) : 0] IDreg; + if(ShiftDR_sig == 1) begin + IDreg = IDreg >> 1; + IDreg[IDLength -1] = TDI; + end + else + IDreg = IDCODEval_sig; + + IDregLastBit_sig = IDreg[0]; + end // always + +//--#################################################################### +//--##### JtagSetGlobalSignals ##### +//--#################################################################### + always@(ClkUpdateIR_sig, Tlrst_sig, USER1_sig, USER2_sig, USER3_sig, USER4_sig) begin + if(Tlrst_sig == 1) begin + glbl.JTAG_SEL1_GLBL <= 0; + glbl.JTAG_SEL2_GLBL <= 0; + glbl.JTAG_SEL3_GLBL <= 0; + glbl.JTAG_SEL4_GLBL <= 0; + end + else if(Tlrst_sig == 0) begin + if(USER1_sig == 1) begin + glbl.JTAG_SEL1_GLBL <= USER1_sig; + glbl.JTAG_SEL2_GLBL <= 0; + glbl.JTAG_SEL3_GLBL <= 0; + glbl.JTAG_SEL4_GLBL <= 0; + end + else if(USER2_sig == 1) begin + glbl.JTAG_SEL1_GLBL <= 0; + glbl.JTAG_SEL2_GLBL <= 1; + glbl.JTAG_SEL3_GLBL <= 0; + glbl.JTAG_SEL4_GLBL <= 0; + end + else if(USER3_sig == 1) begin + glbl.JTAG_SEL1_GLBL <= 0; + glbl.JTAG_SEL2_GLBL <= 0; + glbl.JTAG_SEL3_GLBL <= 1; + glbl.JTAG_SEL4_GLBL <= 0; + end + else if(USER4_sig == 1) begin + glbl.JTAG_SEL1_GLBL <= 0; + glbl.JTAG_SEL2_GLBL <= 0; + glbl.JTAG_SEL3_GLBL <= 0; + glbl.JTAG_SEL4_GLBL <= 1; + end + else if(ClkUpdateIR_sig == 1) begin + glbl.JTAG_SEL1_GLBL <= 0; + glbl.JTAG_SEL2_GLBL <= 0; + glbl.JTAG_SEL3_GLBL <= 0; + glbl.JTAG_SEL4_GLBL <= 0; + end + + end + + end //always + +//--#################################################################### +//--##### OUTPUT ##### +//--#################################################################### + assign glbl.JTAG_TDI_GLBL = TDI; + assign glbl.JTAG_TCK_GLBL = TCK; + assign glbl.JTAG_TMS_GLBL = TMS; + + always@(CurrentState, IRcontent_sig, BypassReg, + IRegLastBit_sig, IDregLastBit_sig, glbl.JTAG_USER_TDO1_GLBL, + glbl.JTAG_USER_TDO2_GLBL, glbl.JTAG_USER_TDO3_GLBL, + glbl.JTAG_USER_TDO4_GLBL) + begin + case (CurrentState) + ShiftIR: begin + TDO_latch <= IRegLastBit_sig; + end + ShiftDR: begin + if(IRcontent_sig == IDCODE_INSTR[(IRLength - 1): 0]) + TDO_latch <= IDregLastBit_sig; + else if(IRcontent_sig == BYPASS_INSTR[(IRLength - 1): 0]) + TDO_latch <= BypassReg; + else if(IRcontent_sig == USER1_INSTR[(IRLength - 1): 0]) + TDO_latch <= glbl.JTAG_USER_TDO1_GLBL; + else if(IRcontent_sig == USER2_INSTR[(IRLength - 1): 0]) + TDO_latch <= glbl.JTAG_USER_TDO2_GLBL; + else if(IRcontent_sig == USER3_INSTR[(IRLength - 1): 0]) + TDO_latch <= glbl.JTAG_USER_TDO3_GLBL; + else if(IRcontent_sig == USER4_INSTR[(IRLength - 1): 0]) + TDO_latch <= glbl.JTAG_USER_TDO4_GLBL; + else + TDO_latch <= 1'bz; + end + default : begin + TDO_latch <= 1'bz; + end + endcase // case(PART_NAME) + end // always + + always@(negedge TCK) + begin +// 213980 NCsim compile error fix + TDO <= # 6000 TDO_latch; + end // always + +//--#################################################################### +//--##### Timing ##### +//--#################################################################### + + specify +// 213980 NCsim compile error fix +// (TCK => TDO) = (6000:6000:6000, 6000:6000:6000); + + $setuphold (posedge TCK, posedge TDI , 1000:1000:1000, 2000:2000:2000, notifier); + $setuphold (posedge TCK, negedge TDI , 1000:1000:1000, 2000:2000:2000, notifier); + + $setuphold (posedge TCK, posedge TMS , 1000:1000:1000, 2000:2000:2000, notifier); + $setuphold (posedge TCK, negedge TMS , 1000:1000:1000, 2000:2000:2000, notifier); + endspecify + +endmodule // JTAG_SIM_VIRTEX5 diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/JTAG_SIM_VIRTEX6.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/JTAG_SIM_VIRTEX6.v new file mode 100644 index 0000000..545cc1a --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/JTAG_SIM_VIRTEX6.v @@ -0,0 +1,709 @@ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2005 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Timing Simulation Library Component +// / / Jtag TAP Controler for SPARTAN6 +// /___/ /\ Filename : JTAG_SIM_VIRTEX6.v +// \ \ / \ Timestamp : Thu Jan 29 16:26:40 PST 2009 +// \___\/\___\ +// +// Revision: +// 01/29/09 - Initial version. +// 04/08/09 - CR 528894 -- PART_NAME default value fix for gencomp +// 08/26/09 - CR 530869 -- PART_NAME values updated and default value changed +// End Revision + +`timescale 1 ps/1 ps + +module JTAG_SIM_VIRTEX6( TDO, TCK, TDI, TMS); + + + output TDO; + + input TCK, TDI, TMS; + + reg TDO; + reg notifier; + + + parameter PART_NAME = "LX75T"; + + localparam TestLogicReset = 4'h0, + RunTestIdle = 4'h1, + SelectDRScan = 4'h2, + CaptureDR = 4'h3, + ShiftDR = 4'h4, + Exit1DR = 4'h5, + PauseDR = 4'h6, + Exit2DR = 4'h7, + UpdateDR = 4'h8, + SelectIRScan = 4'h9, + CaptureIR = 4'ha, + ShiftIR = 4'hb, + Exit1IR = 4'hc, + PauseIR = 4'hd, + Exit2IR = 4'he, + UpdateIR = 4'hf; + + localparam DELAY_SIG = 1; + + reg TRST = 0; + + reg [3:0] CurrentState = TestLogicReset; + reg [14*8:0] jtag_state_name = "TestLogicReset"; + reg [14*8:0] jtag_instruction_name = "IDCODE"; + + +//----------------- Virtex4 Specific Constants --------- + localparam IRLengthMax = 10; + localparam IDLength = 32; + + reg [IRLengthMax-1:0] IR_CAPTURE_VAL = 10'b1111010001, + BYPASS_INSTR = 10'b1111111111, + IDCODE_INSTR = 10'b1111001001, + USER1_INSTR = 10'b1111000010, + USER2_INSTR = 10'b1111000011, + USER3_INSTR = 10'b1111100010, + USER4_INSTR = 10'b1111100011; + + localparam IRLength = 10; + +//----------------- local reg ------------------------------- + reg CaptureDR_sig = 0, RESET_sig = 0, ShiftDR_sig = 0, UpdateDR_sig = 0; + + reg ClkIR_active = 0, ClkIR_sig = 0, ClkID_sig = 0; + + reg ShiftIR_sig, UpdateIR_sig, ClkUpdateIR_sig; + + reg [IRLength-1:0] IRcontent_sig; + + reg [IDLength-1:0] IDCODEval_sig; + + reg BypassReg = 0, BYPASS_sig = 0, IDCODE_sig = 0, + USER1_sig = 0, USER2_sig = 0, + USER3_sig = 0, USER4_sig = 0; + + reg TDO_latch; + + reg Tlrst_sig = 1; + reg TlrstN_sig = 1; + + reg IRegLastBit_sig = 0, IDregLastBit_sig = 0; + + reg Rti_sig = 0; + //------------------------------------------------------------- + reg [IRLength-1:0] NextIRreg; + reg [IRLength-1:0] ir_int; // = IR_CAPTURE_VAL[IRLength-1:0] ; + reg [IDLength-1:0] IDreg; + +//#################################################################### +//##### Initialize ##### +//#################################################################### + initial begin + case (PART_NAME) + "CX75T", "cx75t" : IDCODEval_sig <= 32'h042c4093; + "LX75T", "lx75t" : IDCODEval_sig <= 32'h04244093; + "CX130T", "cx130t" : IDCODEval_sig <= 32'h042ca093; + "LX130T", "lx130t" : IDCODEval_sig <= 32'h0424a093; + "CX195T", "cx195t" : IDCODEval_sig <= 32'h042cc093; + "LX195T", "lx195t" : IDCODEval_sig <= 32'h0424c093; + "CX240T", "cx240t" : IDCODEval_sig <= 32'h042d0093; + "LX240T", "lx240t" : IDCODEval_sig <= 32'h04250093; + "HX250T", "hx250t" : IDCODEval_sig <= 32'h042a2093; + "HX255T", "hx255t" : IDCODEval_sig <= 32'h042a4093; + "SX315T", "sx315t" : IDCODEval_sig <= 32'h04286093; + "LX365T", "lx365t" : IDCODEval_sig <= 32'h04252093; + "HX380T", "hx380t" : IDCODEval_sig <= 32'h042a8093; + "SX475T", "sx475t" : IDCODEval_sig <= 32'h04288093; + "LX550T", "lx550t" : IDCODEval_sig <= 32'h04256093; + "HX565T", "hx565t" : IDCODEval_sig <= 32'h042ac093; + "LX760", "lx760" : IDCODEval_sig <= 32'h0423a093; + + default : begin + + $display("Attribute Syntax Error : The attribute PART_NAME on JTAG_SIM_VIRTEX6 instance %m is set to %s. The legal values for this attributes are CX75T or LX75T or CX130T or LX130T or CX195T or LX195T or CX240T or LX240T or HX250T or HX255T or SX315T or LX365T or HX380T or SX475T or LX550T or HX565T or LX760", PART_NAME); + end + endcase // case(PART_NAME) + + ir_int <= IR_CAPTURE_VAL[IRLength-1:0]; + + end // initial begin +//#################################################################### +//##### JtagTapSM ##### +//#################################################################### + always@(posedge TCK or posedge TRST) + begin + if(TRST) begin + CurrentState = TestLogicReset; + end + else begin + case(CurrentState) + + TestLogicReset: + begin + if(TMS == 0) begin + CurrentState = RunTestIdle; + jtag_state_name = "RunTestIdle"; + end + end + + RunTestIdle: + begin + if(TMS == 1) begin + CurrentState = SelectDRScan; + jtag_state_name = "SelectDRScan"; + end + end + //------------------------------- + // ------ DR path --------------- + // ------------------------------- + SelectDRScan: + begin + if(TMS == 0) begin + CurrentState = CaptureDR; + jtag_state_name = "CaptureDR"; + end + else if(TMS == 1) begin + CurrentState = SelectIRScan; + jtag_state_name = "SelectIRScan"; + end + end + + CaptureDR: + begin + if(TMS == 0) begin + CurrentState = ShiftDR; + jtag_state_name = "ShiftDR"; + end + else if(TMS == 1) begin + CurrentState = Exit1DR; + jtag_state_name = "Exit1DR"; + end + end + + ShiftDR: + begin + if(IRcontent_sig == BYPASS_INSTR[(IRLength - 1): 0]) + BypassReg = TDI; + + if(TMS == 1) begin + CurrentState = Exit1DR; + jtag_state_name = "Exit1DR"; + end + end + + Exit1DR: + begin + if(TMS == 0) begin + CurrentState = PauseDR; + jtag_state_name = "PauseDR"; + end + else if(TMS == 1) begin + CurrentState = UpdateDR; + jtag_state_name = "UpdateDR"; + end + end + + PauseDR: + begin + if(TMS == 1) begin + CurrentState = Exit2DR; + jtag_state_name = "Exit2DR"; + end + end + + Exit2DR: + begin + if(TMS == 0) begin + CurrentState = ShiftDR; + jtag_state_name = "ShiftDR"; + end + else if(TMS == 1) begin + CurrentState = UpdateDR; + jtag_state_name = "UpdateDR"; + end + end + + UpdateDR: + begin + if(TMS == 0) begin + CurrentState = RunTestIdle; + jtag_state_name = "RunTestIdle"; + end + else if(TMS == 1) begin + CurrentState = SelectDRScan; + jtag_state_name = "SelectDRScan"; + end + end + //------------------------------- + // ------ IR path --------------- + // ------------------------------- + SelectIRScan: + begin + if(TMS == 0) begin + CurrentState = CaptureIR; + jtag_state_name = "CaptureIR"; + end + else if(TMS == 1) begin + CurrentState = TestLogicReset; + jtag_state_name = "TestLogicReset"; + end + end + + CaptureIR: + begin + if(TMS == 0) begin + CurrentState = ShiftIR; + jtag_state_name = "ShiftIR"; + end + else if(TMS == 1) begin + CurrentState = Exit1IR; + jtag_state_name = "Exit1IR"; + end + end + + ShiftIR: + begin +// ClkIR_sig = 1; + + if(TMS == 1) begin + CurrentState = Exit1IR; + jtag_state_name = "Exit1IR"; + end + end + + Exit1IR: + begin + if(TMS == 0) begin + CurrentState = PauseIR; + jtag_state_name = "PauseIR"; + end + else if(TMS == 1) begin + CurrentState = UpdateIR; + jtag_state_name = "UpdateIR"; + end + end + + PauseIR: + begin + if(TMS == 1) begin + CurrentState = Exit2IR; + jtag_state_name = "Exit2IR"; + end + end + + Exit2IR: + begin + if(TMS == 0) begin + CurrentState = ShiftIR; + jtag_state_name = "ShiftIR"; + end + else if(TMS == 1) begin + CurrentState = UpdateIR; + jtag_state_name = "UpdateIR"; + end + end + + UpdateIR: + begin + //-- FP +// ClkIR_sig = 1; + + if(TMS == 0) begin + CurrentState = RunTestIdle; + jtag_state_name = "RunTestIdle"; + end + else if(TMS == 1) begin + CurrentState = SelectDRScan; + jtag_state_name = "SelectDRScan"; + end + end + endcase // case(CurrentState) + end // else + + end // always + +//-------------------------------------------------------- + always@(CurrentState, TCK, TRST) + begin + ClkIR_sig = 1; + + if(TRST == 1 ) begin + Tlrst_sig = #DELAY_SIG 1; + CaptureDR_sig = #DELAY_SIG 0; + ShiftDR_sig = #DELAY_SIG 0; + UpdateDR_sig = #DELAY_SIG 0; + ShiftIR_sig = #DELAY_SIG 0; + UpdateIR_sig = #DELAY_SIG 0; + end + else if(TRST == 0) begin + + case (CurrentState) + TestLogicReset: begin + Tlrst_sig = #DELAY_SIG 1; + Rti_sig = #DELAY_SIG 0; + CaptureDR_sig = #DELAY_SIG 0; + ShiftDR_sig = #DELAY_SIG 0; + UpdateDR_sig = #DELAY_SIG 0; + ShiftIR_sig = #DELAY_SIG 0; + UpdateIR_sig = #DELAY_SIG 0; + end + RunTestIdle: begin + Tlrst_sig = #DELAY_SIG 0; + Rti_sig = #DELAY_SIG 1; + CaptureDR_sig = #DELAY_SIG 0; + ShiftDR_sig = #DELAY_SIG 0; + UpdateDR_sig = #DELAY_SIG 0; + ShiftIR_sig = #DELAY_SIG 0; + UpdateIR_sig = #DELAY_SIG 0; + end + CaptureDR: begin + Tlrst_sig = #DELAY_SIG 0; + Rti_sig = #DELAY_SIG 0; + CaptureDR_sig = #DELAY_SIG 1; + ShiftDR_sig = #DELAY_SIG 0; + UpdateDR_sig = #DELAY_SIG 0; + ShiftIR_sig = #DELAY_SIG 0; + UpdateIR_sig = #DELAY_SIG 0; + end + ShiftDR: begin + Tlrst_sig = #DELAY_SIG 0; + Rti_sig = #DELAY_SIG 0; + CaptureDR_sig = #DELAY_SIG 0; + ShiftDR_sig = #DELAY_SIG 1; + UpdateDR_sig = #DELAY_SIG 0; + ShiftIR_sig = #DELAY_SIG 0; + UpdateIR_sig = #DELAY_SIG 0; + end + UpdateDR: begin + Tlrst_sig = #DELAY_SIG 0; + Rti_sig = #DELAY_SIG 0; + CaptureDR_sig = #DELAY_SIG 0; + ShiftDR_sig = #DELAY_SIG 0; + UpdateDR_sig = #DELAY_SIG 1; + ShiftIR_sig = #DELAY_SIG 0; + UpdateIR_sig = #DELAY_SIG 0; + end + CaptureIR: begin + Tlrst_sig = #DELAY_SIG 0; + Rti_sig = #DELAY_SIG 0; + CaptureDR_sig = #DELAY_SIG 0; + ShiftDR_sig = #DELAY_SIG 0; + UpdateDR_sig = #DELAY_SIG 0; + ShiftIR_sig = #DELAY_SIG 0; + UpdateIR_sig = #DELAY_SIG 0; + ClkIR_sig = TCK; + end + ShiftIR: begin + Tlrst_sig = #DELAY_SIG 0; + Rti_sig = #DELAY_SIG 0; + CaptureDR_sig = #DELAY_SIG 0; + ShiftDR_sig = #DELAY_SIG 0; + UpdateDR_sig = #DELAY_SIG 0; + ShiftIR_sig = #DELAY_SIG 1; + UpdateIR_sig = #DELAY_SIG 0; + ClkIR_sig = TCK; + end + UpdateIR: begin + Tlrst_sig = #DELAY_SIG 0; + Rti_sig = #DELAY_SIG 0; + CaptureDR_sig = #DELAY_SIG 0; + ShiftDR_sig = #DELAY_SIG 0; + UpdateDR_sig = #DELAY_SIG 0; + ShiftIR_sig = #DELAY_SIG 0; + UpdateIR_sig = #DELAY_SIG 1; + end + default: begin + Tlrst_sig = #DELAY_SIG 0; + Rti_sig = #DELAY_SIG 0; + CaptureDR_sig = #DELAY_SIG 0; + ShiftDR_sig = #DELAY_SIG 0; + UpdateDR_sig = #DELAY_SIG 0; + ShiftIR_sig = #DELAY_SIG 0; + UpdateIR_sig = #DELAY_SIG 0; + end + endcase + + end + + end // always(CurrentState) +//----------------------------------------------------- + always@(TCK) + begin +// ClkIR_sig = ShiftIR_sig & TCK; + ClkUpdateIR_sig = UpdateIR_sig & ~TCK; + end // always + + always@(TCK) + begin + ClkID_sig = IDCODE_sig & TCK; + end // always + +// RESET + always@(Tlrst_sig) + begin + glbl.JTAG_RESET_GLBL <= Tlrst_sig; + end + +// RUNTEST + always@(Rti_sig) + begin + glbl.JTAG_RUNTEST_GLBL <= Rti_sig; + end +//-------------- TCK NEGATIVE EDGE activities ---------- + always@(negedge TCK, negedge UpdateDR_sig) + begin + if(TCK == 0) begin + glbl.JTAG_CAPTURE_GLBL <= CaptureDR_sig; + glbl.JTAG_SHIFT_GLBL <= ShiftDR_sig; + TlrstN_sig <= Tlrst_sig; + end + + glbl.JTAG_UPDATE_GLBL <= UpdateDR_sig; + + end // always + +//--#################################################################### +//--##### JtagIR ##### +//--#################################################################### + always@(posedge ClkIR_sig) begin + NextIRreg = {TDI, ir_int[IRLength-1:1]}; + + if ((TRST== 0) && (TlrstN_sig == 0)) begin + if(ShiftIR_sig == 1) begin + ir_int = NextIRreg; + IRegLastBit_sig = ir_int[0]; + end + else begin + ir_int = IR_CAPTURE_VAL; + IRegLastBit_sig = ir_int[0]; + end + end + end //always +//-------------------------------------------------------- + always@(posedge ClkUpdateIR_sig or posedge TlrstN_sig or + posedge TRST) begin + if ((TRST== 1) || (TlrstN_sig == 1)) begin + IRcontent_sig = IDCODE_INSTR[(IRLength - 1): 0]; // IDCODE instr is loaded.. must verify-- FP. + IRegLastBit_sig = ir_int[0]; + end + else if( (TRST == 0) && (TlrstN_sig == 0)) begin + IRcontent_sig = ir_int; + end + end //always +//--#################################################################### +//--##### JtagDecodeIR ##### +//--#################################################################### + always@(IRcontent_sig) begin + + case(IRcontent_sig) + +// IR_CAPTURE_VAL : begin +// ; +// jtag_instruction_name = "IR_CAPTURE"; +// end + + BYPASS_INSTR[(IRLength - 1): 0] : begin + jtag_instruction_name = "BYPASS"; + // if BYPASS instruction, set BYPASS signal to 1 + BYPASS_sig <= 1; + IDCODE_sig <= 0; + USER1_sig <= 0; + USER2_sig <= 0; + USER3_sig <= 0; + USER4_sig <= 0; + end + + IDCODE_INSTR[(IRLength - 1): 0] : begin + jtag_instruction_name = "IDCODE"; + // if IDCODE instruction, set IDCODE signal to 1 + BYPASS_sig <= 0; + IDCODE_sig <= 1; + USER1_sig <= 0; + USER2_sig <= 0; + USER3_sig <= 0; + USER4_sig <= 0; + end + + USER1_INSTR[(IRLength - 1): 0] : begin + jtag_instruction_name = "USER1"; + // if USER1 instruction, set USER1 signal to 1 + BYPASS_sig <= 0; + IDCODE_sig <= 0; + USER1_sig <= 1; + USER2_sig <= 0; + USER3_sig <= 0; + USER4_sig <= 0; + end + + USER2_INSTR[(IRLength - 1): 0] : begin + jtag_instruction_name = "USER2"; + // if USER2 instruction, set USER2 signal to 1 + BYPASS_sig <= 0; + IDCODE_sig <= 0; + USER1_sig <= 0; + USER2_sig <= 1; + USER3_sig <= 0; + USER4_sig <= 0; + end + + USER3_INSTR[(IRLength - 1): 0] : begin + jtag_instruction_name = "USER3"; + // if USER3 instruction, set USER3 signal to 1 + BYPASS_sig <= 0; + USER1_sig <= 0; + USER2_sig <= 0; + IDCODE_sig <= 0; + USER3_sig <= 1; + USER4_sig <= 0; + end + + USER4_INSTR[(IRLength - 1): 0] : begin + jtag_instruction_name = "USER4"; + // if USER4 instruction, set USER4 signal to 1 + BYPASS_sig <= 0; + IDCODE_sig <= 0; + USER1_sig <= 0; + USER2_sig <= 0; + USER3_sig <= 0; + USER4_sig <= 1; + end + default : begin + jtag_instruction_name = "UNKNOWN"; + // if UNKNOWN instruction, set all signals to 0 + BYPASS_sig <= 0; + IDCODE_sig <= 0; + USER1_sig <= 0; + USER2_sig <= 0; + USER3_sig <= 0; + USER4_sig <= 0; + end + + endcase + end //always +//--#################################################################### +//--##### JtagIDCODE ##### +//--#################################################################### + always@(posedge ClkID_sig) begin +// reg [(IDLength -1) : 0] IDreg; + if(ShiftDR_sig == 1) begin + IDreg = IDreg >> 1; + IDreg[IDLength -1] = TDI; + end + else + IDreg = IDCODEval_sig; + + IDregLastBit_sig = IDreg[0]; + end // always + +//--#################################################################### +//--##### JtagSetGlobalSignals ##### +//--#################################################################### + always@(ClkUpdateIR_sig, Tlrst_sig, USER1_sig, USER2_sig, USER3_sig, USER4_sig) begin + if(Tlrst_sig == 1) begin + glbl.JTAG_SEL1_GLBL <= 0; + glbl.JTAG_SEL2_GLBL <= 0; + glbl.JTAG_SEL3_GLBL <= 0; + glbl.JTAG_SEL4_GLBL <= 0; + end + else if(Tlrst_sig == 0) begin + if(USER1_sig == 1) begin + glbl.JTAG_SEL1_GLBL <= USER1_sig; + glbl.JTAG_SEL2_GLBL <= 0; + glbl.JTAG_SEL3_GLBL <= 0; + glbl.JTAG_SEL4_GLBL <= 0; + end + else if(USER2_sig == 1) begin + glbl.JTAG_SEL1_GLBL <= 0; + glbl.JTAG_SEL2_GLBL <= 1; + glbl.JTAG_SEL3_GLBL <= 0; + glbl.JTAG_SEL4_GLBL <= 0; + end + else if(USER3_sig == 1) begin + glbl.JTAG_SEL1_GLBL <= 0; + glbl.JTAG_SEL2_GLBL <= 0; + glbl.JTAG_SEL3_GLBL <= 1; + glbl.JTAG_SEL4_GLBL <= 0; + end + else if(USER4_sig == 1) begin + glbl.JTAG_SEL1_GLBL <= 0; + glbl.JTAG_SEL2_GLBL <= 0; + glbl.JTAG_SEL3_GLBL <= 0; + glbl.JTAG_SEL4_GLBL <= 1; + end + else if(ClkUpdateIR_sig == 1) begin + glbl.JTAG_SEL1_GLBL <= 0; + glbl.JTAG_SEL2_GLBL <= 0; + glbl.JTAG_SEL3_GLBL <= 0; + glbl.JTAG_SEL4_GLBL <= 0; + end + + end + + end //always + +//--#################################################################### +//--##### OUTPUT ##### +//--#################################################################### + assign glbl.JTAG_TDI_GLBL = TDI; + assign glbl.JTAG_TCK_GLBL = TCK; + assign glbl.JTAG_TMS_GLBL = TMS; + + always@(CurrentState, IRcontent_sig, BypassReg, + IRegLastBit_sig, IDregLastBit_sig, glbl.JTAG_USER_TDO1_GLBL, + glbl.JTAG_USER_TDO2_GLBL, glbl.JTAG_USER_TDO3_GLBL, + glbl.JTAG_USER_TDO4_GLBL) + begin + case (CurrentState) + ShiftIR: begin + TDO_latch <= IRegLastBit_sig; + end + ShiftDR: begin + if(IRcontent_sig == IDCODE_INSTR[(IRLength - 1): 0]) + TDO_latch <= IDregLastBit_sig; + else if(IRcontent_sig == BYPASS_INSTR[(IRLength - 1): 0]) + TDO_latch <= BypassReg; + else if(IRcontent_sig == USER1_INSTR[(IRLength - 1): 0]) + TDO_latch <= glbl.JTAG_USER_TDO1_GLBL; + else if(IRcontent_sig == USER2_INSTR[(IRLength - 1): 0]) + TDO_latch <= glbl.JTAG_USER_TDO2_GLBL; + else if(IRcontent_sig == USER3_INSTR[(IRLength - 1): 0]) + TDO_latch <= glbl.JTAG_USER_TDO3_GLBL; + else if(IRcontent_sig == USER4_INSTR[(IRLength - 1): 0]) + TDO_latch <= glbl.JTAG_USER_TDO4_GLBL; + else + TDO_latch <= 1'bz; + end + default : begin + TDO_latch <= 1'bz; + end + endcase // case(PART_NAME) + end // always + + always@(negedge TCK) + begin +// 213980 NCsim compile error fix + TDO <= # 6000 TDO_latch; + end // always + +//--#################################################################### +//--##### Timing ##### +//--#################################################################### + + specify +// 213980 NCsim compile error fix +// (TCK => TDO) = (6000:6000:6000, 6000:6000:6000); + + $setuphold (posedge TCK, posedge TDI , 1000:1000:1000, 2000:2000:2000, notifier); + $setuphold (posedge TCK, negedge TDI , 1000:1000:1000, 2000:2000:2000, notifier); + + $setuphold (posedge TCK, posedge TMS , 1000:1000:1000, 2000:2000:2000, notifier); + $setuphold (posedge TCK, negedge TMS , 1000:1000:1000, 2000:2000:2000, notifier); + endspecify + +endmodule // JTAG_SIM_VIRTEX6 diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/KEEPER.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/KEEPER.v new file mode 100644 index 0000000..6a545fa --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/KEEPER.v @@ -0,0 +1,35 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/KEEPER.v,v 1.5 2007/05/23 21:43:39 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Weak Keeper +// /___/ /\ Filename : KEEPER.v +// \ \ / \ Timestamp : Thu Mar 25 16:42:51 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. + +`timescale 1 ps / 1 ps + +module KEEPER (O); + + inout O; + reg in; + + always @(O) + if (O) + in <= 1; + else + in <= 0; + + buf (pull1, pull0) B1 (O, in); + +endmodule diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/KEY_CLEAR.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/KEY_CLEAR.v new file mode 100644 index 0000000..a89a561 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/KEY_CLEAR.v @@ -0,0 +1,31 @@ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / +// /___/ /\ Filename : KEY_CLEAR.v +// \ \ / \ Timestamp : Wed Aug 17 16:23:43 PDT 2005 +// \___\/\___\ +// +// Revision: +// 08/17/05 - Initial version. +// End Revision + +`timescale 1 ps / 1 ps + +module KEY_CLEAR ( + KEYCLEARB +); + +input KEYCLEARB; + +specify + specparam PATHPULSE$ = 0; +endspecify + +endmodule diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/LD.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/LD.v new file mode 100644 index 0000000..1da8c76 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/LD.v @@ -0,0 +1,55 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/LD.v,v 1.12 2006/04/10 20:46:00 yanx Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Transparent Data Latch +// /___/ /\ Filename : LD.v +// \ \ / \ Timestamp : Thu Mar 25 16:42:51 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 02/04/05 - Rev 0.0.1 Remove input/output bufs; Seperate GSR from clock block. +// 08/09/05 - Add GSR to main block (CR 215196). +// 03/31/06 - Add specify block for 100ps delay. (CR 228298) +// End Revision + +`timescale 1 ps / 1 ps + +module LD (Q, D, G); + + parameter INIT = 1'b0; + + output Q; + wire Q; + + input D, G; + + tri0 GSR = glbl.GSR; + + + reg q_out; + + initial q_out = INIT; + + assign Q = q_out; + + always @(D or G or GSR) + if (GSR) + q_out <= INIT; + else + if (G) + q_out <= D; + + specify + if (G) + (D +=> Q) = (100, 100); + (posedge G => (Q +: D)) = (100, 100); + endspecify +endmodule diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/LDC.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/LDC.v new file mode 100644 index 0000000..e30d1e4 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/LDC.v @@ -0,0 +1,60 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/LDC.v,v 1.12 2006/04/10 20:46:00 yanx Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Transparent Data Latch with Asynchronous Clear +// /___/ /\ Filename : LDC.v +// \ \ / \ Timestamp : Thu Mar 25 16:42:52 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 02/04/05 - Rev 0.0.1 Remove input/output bufs; Seperate GSR from clock block. +// 08/09/05 - Add GSR to main block (CR 215196). +// 03/31/06 - Add specify block for 100ps delay. (CR 228298) +// End Revision + +`timescale 1 ps / 1 ps + + +module LDC (Q, CLR, D, G); + + parameter INIT = 1'b0; + + output Q; + wire Q; + + input CLR, D, G; + + tri0 GSR = glbl.GSR; + + + reg q_out; + + initial q_out = INIT; + + assign Q = q_out; + + always @(CLR or D or G or GSR) + if (GSR) + q_out <= INIT; + else + if (CLR) + q_out <= 0; + else if (G) + q_out <= D; + + specify + if (!CLR && G) + (D +=> Q) = (100, 100); + if (!CLR) + (posedge G => (Q +: D)) = (100, 100); + (posedge CLR => (Q +: 1'b0)) = (0, 0); + endspecify +endmodule diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/LDCE.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/LDCE.v new file mode 100644 index 0000000..c3b02fe --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/LDCE.v @@ -0,0 +1,64 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/LDCE.v,v 1.12 2006/04/10 20:46:00 yanx Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Transparent Data Latch with Asynchronous Clear and Gate Enable +// /___/ /\ Filename : LDCE.v +// \ \ / \ Timestamp : Thu Mar 25 16:42:52 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 02/04/05 - Rev 0.0.1 Remove input/output bufs; Seperate GSR from clock block. +// 08/09/05 - Add GSR to main block (CR 215196). +// 03/31/06 - Add specify block for 100ps delay. (CR 228298) +// End Revision + +`timescale 1 ps / 1 ps + + +module LDCE (Q, CLR, D, G, GE); + + parameter INIT = 1'b0; + + output Q; + wire Q; + + input CLR, D, G, GE; + + tri0 GSR = glbl.GSR; + + + reg q_out; + + initial q_out = INIT; + + assign Q = q_out; + + always @(CLR or D or G or GE or GSR) + if (GSR) + q_out <= INIT; + else + if (CLR) + q_out <= 0; + else if (G && GE) + q_out <= D; + + + + specify + if (!CLR && G && GE) + (D +=> Q) = (100, 100); + if (!CLR && GE) + (posedge G => (Q +: D)) = (100, 100); + if (!CLR && G) + (posedge GE => (Q +: D)) = (100, 100); + (posedge CLR => (Q +: 1'b0)) = (0, 0); + endspecify +endmodule diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/LDCE_1.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/LDCE_1.v new file mode 100644 index 0000000..f978777 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/LDCE_1.v @@ -0,0 +1,64 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/LDCE_1.v,v 1.12 2006/04/10 20:46:00 yanx Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Transparent Data Latch with Asynchronous Clear, Gate Enable and Inverted Gate +// /___/ /\ Filename : LDCE_1.v +// \ \ / \ Timestamp : Thu Mar 25 16:42:52 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 02/04/05 - Rev 0.0.1 Remove input/output bufs; Seperate GSR from clock block. +// 08/09/05 - Add GSR to main block (CR 215196). +// 03/31/06 - Add specify block for 100ps delay. (CR 228298) +// End Revision + +`timescale 1 ps / 1 ps + + +module LDCE_1 (Q, CLR, D, G, GE); + + parameter INIT = 1'b0; + + output Q; + wire Q; + + input CLR, D, G, GE; + + tri0 GSR = glbl.GSR; + + + reg q_out; + + initial q_out = INIT; + + assign Q = q_out; + + always @(CLR or D or G or GE or GSR) + if (GSR) + q_out <= INIT; + else + if (CLR) + q_out <= 0; + else if (!G && GE) + q_out <= D; + + + + specify + if (!CLR && !G && GE) + (D +=> Q) = (100, 100); + if (!CLR && GE) + (negedge G => (Q +: D)) = (100, 100); + if (!CLR && !G) + (posedge GE => (Q +: D)) = (100, 100); + (posedge CLR => (Q +: 1'b0)) = (0, 0); + endspecify +endmodule diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/LDCP.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/LDCP.v new file mode 100644 index 0000000..479b8a3 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/LDCP.v @@ -0,0 +1,66 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/LDCP.v,v 1.12 2006/04/10 20:46:00 yanx Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Transparent Data Latch with Asynchronous Clear and Preset +// /___/ /\ Filename : LDCP.v +// \ \ / \ Timestamp : Thu Mar 25 16:42:52 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 02/04/05 - Rev 0.0.1 Remove input/output bufs; Seperate GSR from clock block. +// 08/09/05 - Add GSR to main block (CR 215196). +// 03/31/06 - Add specify block for 100ps delay. (CR 228298) +// End Revision + +`timescale 1 ps / 1 ps + + +module LDCP (Q, CLR, D, G, PRE); + + parameter INIT = 1'b0; + + output Q; + wire Q; + + input CLR, D, G, PRE; + + tri0 GSR = glbl.GSR; + + + reg q_out; + + initial q_out = INIT; + + assign Q = q_out; + + always @(CLR or PRE or D or G or GSR) + if (GSR) + q_out <= INIT; + else + if (CLR) + q_out <= 0; + else if (PRE) + q_out <= 1; + else if (G) + q_out <= D; + + + + specify + if (!CLR && !PRE && G) + (D +=> Q) = (100, 100); + if (!CLR && !PRE) + (posedge G => (Q +: D)) = (100, 100); + if (!CLR) + (posedge PRE => (Q +: 1'b1)) = (0, 0); + (posedge CLR => (Q +: 1'b0)) = (0, 0); + endspecify +endmodule diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/LDCPE.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/LDCPE.v new file mode 100644 index 0000000..8888cab --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/LDCPE.v @@ -0,0 +1,66 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/LDCPE.v,v 1.12 2006/04/10 20:46:00 yanx Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Transparent Data Latch with Asynchronous Clear and Preset and Gate Enable +// /___/ /\ Filename : LDCPE.v +// \ \ / \ Timestamp : Thu Mar 25 16:42:52 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 02/04/05 - Rev 0.0.1 Remove input/output bufs; Seperate GSR from clock block. +// 08/09/05 - Add GSR to main block (CR 215196). +// 03/31/06 - Add specify block for 100ps delay. (CR 228298) +// End Revision + +`timescale 1 ps / 1 ps + + +module LDCPE (Q, CLR, D, G, GE, PRE); + + parameter INIT = 1'b0; + + output Q; + wire Q; + + input CLR, D, G, GE, PRE; + + tri0 GSR = glbl.GSR; + + + reg q_out; + + initial q_out = INIT; + + assign Q = q_out; + + always @(CLR or PRE or D or G or GE or GSR) + if (GSR) + q_out <= INIT; + else + if (CLR) + q_out <= 0; + else if (PRE) + q_out <= 1; + else if (G && GE) + q_out <= D; + + specify + if (!CLR && !PRE && G && GE) + (D +=> Q) = (100, 100); + if (!CLR && !PRE && GE) + (posedge G => (Q +: D)) = (100, 100); + if (!CLR && !PRE && G) + (posedge GE => (Q +: D)) = (100, 100); + if (!CLR) + (posedge PRE => (Q +: 1'b1)) = (0, 0); + (posedge CLR => (Q +: 1'b0)) = (0, 0); + endspecify +endmodule diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/LDCPE_1.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/LDCPE_1.v new file mode 100644 index 0000000..f30d85d --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/LDCPE_1.v @@ -0,0 +1,66 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/LDCPE_1.v,v 1.12 2006/04/10 20:46:00 yanx Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Transparent Data Latch with Asynchronous Clear and Preset, Gate Enable and Inverted Gate +// /___/ /\ Filename : LDCPE_1.v +// \ \ / \ Timestamp : Thu Mar 25 16:42:52 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 02/04/05 - Rev 0.0.1 Remove input/output bufs; Seperate GSR from clock block. +// 08/09/05 - Add GSR to main block (CR 215196). +// 03/31/06 - Add specify block for 100ps delay. (CR 228298) +// End Revision + +`timescale 1 ps / 1 ps + + +module LDCPE_1 (Q, CLR, D, G, GE, PRE); + + parameter INIT = 1'b0; + + output Q; + wire Q; + + input CLR, D, G, GE, PRE; + + tri0 GSR = glbl.GSR; + + + reg q_out; + + initial q_out = INIT; + + assign Q = q_out; + + always @(CLR or PRE or D or G or GE or GSR) + if (GSR) + q_out <= INIT; + else + if (CLR) + q_out <= 0; + else if (PRE) + q_out <= 1; + else if (!G && GE) + q_out <= D; + + specify + if (!CLR && !PRE && !G && GE) + (D +=> Q) = (100, 100); + if (!CLR && !PRE && GE) + (negedge G => (Q +: D)) = (100, 100); + if (!CLR && !PRE && !G) + (posedge GE => (Q +: D)) = (100, 100); + if (!CLR) + (posedge PRE => (Q +: 1'b1)) = (0, 0); + (posedge CLR => (Q +: 1'b0)) = (0, 0); + endspecify +endmodule diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/LDCP_1.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/LDCP_1.v new file mode 100644 index 0000000..4215aa6 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/LDCP_1.v @@ -0,0 +1,64 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/LDCP_1.v,v 1.12 2006/04/10 20:46:00 yanx Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Transparent Data Latch with Asynchronous Clear and Preset and Inverted Gate +// /___/ /\ Filename : LDCP_1.v +// \ \ / \ Timestamp : Thu Mar 25 16:42:52 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 02/04/05 - Rev 0.0.1 Remove input/output bufs; Seperate GSR from clock block. +// 08/09/05 - Add GSR to main block (CR 215196). +// 03/31/06 - Add specify block for 100ps delay. (CR 228298) +// End Revision + +`timescale 1 ps / 1 ps + + +module LDCP_1 (Q, CLR, D, G, PRE); + + parameter INIT = 1'b0; + + output Q; + wire Q; + + input CLR, D, G, PRE; + + tri0 GSR = glbl.GSR; + + + reg q_out; + + initial q_out = INIT; + + assign Q = q_out; + + always @(CLR or PRE or D or G or GSR) + if (GSR) + q_out <= INIT; + else + if (CLR) + q_out <= 0; + else if (PRE) + q_out <= 1; + else if (!G) + q_out <= D; + + specify + if (!CLR && !PRE && !G) + (D +=> Q) = (100, 100); + if (!CLR && !PRE) + (negedge G => (Q +: D)) = (100, 100); + if (!CLR) + (posedge PRE => (Q +: 1'b1)) = (0, 0); + (posedge CLR => (Q +: 1'b0)) = (0, 0); + endspecify +endmodule diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/LDC_1.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/LDC_1.v new file mode 100644 index 0000000..4bb3052 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/LDC_1.v @@ -0,0 +1,62 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/LDC_1.v,v 1.12 2006/04/10 20:46:00 yanx Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Transparent Data Latch with Asynchronous Clear and Inverted Gate +// /___/ /\ Filename : LDC_1.v +// \ \ / \ Timestamp : Thu Mar 25 16:42:52 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 02/04/05 - Rev 0.0.1 Remove input/output bufs; Seperate GSR from clock block. +// 08/09/05 - Add GSR to main block (CR 215196). +// 03/31/06 - Add specify block for 100ps delay. (CR 228298) +// End Revision + +`timescale 1 ps / 1 ps + + +module LDC_1 (Q, CLR, D, G); + + parameter INIT = 1'b0; + + output Q; + wire Q; + + input CLR, D, G; + + tri0 GSR = glbl.GSR; + + + reg q_out; + + initial q_out = INIT; + + assign Q = q_out; + + always @(CLR or D or G or GSR) + if (GSR) + q_out <= INIT; + else + if (CLR) + q_out <= 0; + else if (!G) + q_out <= D; + + + + specify + if (!CLR && !G) + (D +=> Q) = (100, 100); + if (!CLR) + (negedge G => (Q +: D)) = (100, 100); + (posedge CLR => (Q +: 1'b0)) = (0, 0); + endspecify +endmodule diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/LDE.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/LDE.v new file mode 100644 index 0000000..70b0305 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/LDE.v @@ -0,0 +1,61 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/LDE.v,v 1.12 2006/04/10 20:46:00 yanx Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Transparent Data Latch with Gate Enable +// /___/ /\ Filename : LDE.v +// \ \ / \ Timestamp : Thu Mar 25 16:42:52 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 02/04/05 - Rev 0.0.1 Remove input/output bufs; Seperate GSR from clock block. +// 08/09/05 - Add GSR to main block (CR 215196). +// 03/31/06 - Add specify block for 100ps delay. (CR 228298) +// End Revision + +`timescale 1 ps / 1 ps + + +module LDE (Q, D, G, GE); + + parameter INIT = 1'b0; + + output Q; + wire Q; + + input D, G, GE; + + tri0 GSR = glbl.GSR; + + + reg q_out; + + initial q_out = INIT; + + assign Q = q_out; + + always @(D or G or GE or GSR) + if (GSR) + q_out <= INIT; + else + if (G && GE) + q_out <= D; + + + + specify + if (G && GE) + (D +=> Q) = (100, 100); + if (GE) + (posedge G => (Q +: D)) = (100, 100); + if (G) + (posedge GE => (Q +: D)) = (100, 100); + endspecify +endmodule diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/LDE_1.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/LDE_1.v new file mode 100644 index 0000000..759333b --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/LDE_1.v @@ -0,0 +1,59 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/LDE_1.v,v 1.12 2006/04/10 20:46:00 yanx Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Transparent Data Latch with Gate Enable and Inverted Gate +// /___/ /\ Filename : LDE_1.v +// \ \ / \ Timestamp : Thu Mar 25 16:42:52 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 02/04/05 - Rev 0.0.1 Remove input/output bufs; Seperate GSR from clock block. +// 08/09/05 - Add GSR to main block (CR 215196). +// 03/31/06 - Add specify block for 100ps delay. (CR 228298) +// End Revision + +`timescale 1 ps / 1 ps + + +module LDE_1 (Q, D, G, GE); + + parameter INIT = 1'b0; + + output Q; + wire Q; + + input D, G, GE; + + tri0 GSR = glbl.GSR; + + + reg q_out; + + initial q_out = INIT; + + assign Q = q_out; + + always @(D or G or GE or GSR) + if (GSR) + q_out <= INIT; + else + if (!G && GE) + q_out <= D; + + specify + if (!G && GE) + (D +=> Q) = (100, 100); + if (GE) + (negedge G => (Q +: D)) = (100, 100); + if (!G) + (posedge GE => (Q +: D)) = (100, 100); + endspecify +endmodule diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/LDP.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/LDP.v new file mode 100644 index 0000000..10106be --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/LDP.v @@ -0,0 +1,60 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/LDP.v,v 1.12 2006/04/10 20:46:00 yanx Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Transparent Data Latch with Asynchronous Preset +// /___/ /\ Filename : LDP.v +// \ \ / \ Timestamp : Thu Mar 25 16:42:53 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 02/04/05 - Rev 0.0.1 Remove input/output bufs; Seperate GSR from clock block. +// 08/09/05 - Add GSR to main block (CR 215196). +// 03/31/06 - Add specify block for 100ps delay. (CR 228298) +// End Revision + +`timescale 1 ps / 1 ps + + +module LDP (Q, D, G, PRE); + + parameter INIT = 1'b1; + + output Q; + wire Q; + + input D, G, PRE; + + tri0 GSR = glbl.GSR; + + + reg q_out; + + initial q_out = INIT; + + assign Q = q_out; + + always @(PRE or D or G or GSR) + if (GSR ) + q_out <= INIT; + else + if (PRE) + q_out <= 1; + else if (G) + q_out <= D; + + specify + if (!PRE && G) + (D +=> Q) = (100, 100); + if (!PRE) + (posedge G => (Q +: D)) = (100, 100); + (posedge PRE => (Q +: 1'b1)) = (0, 0); + endspecify +endmodule diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/LDPE.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/LDPE.v new file mode 100644 index 0000000..3fd2b48 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/LDPE.v @@ -0,0 +1,61 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/LDPE.v,v 1.12 2006/04/10 20:46:01 yanx Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Transparent Data Latch with Asynchronous Preset and Gate Enable +// /___/ /\ Filename : LDPE.v +// \ \ / \ Timestamp : Thu Mar 25 16:42:53 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 02/04/05 - Rev 0.0.1 Remove input/output bufs; Seperate GSR from clock block. +// 08/09/05 - Add GSR to main block (CR 215196). +// 03/31/06 - Add specify block for 100ps delay. (CR 228298) +// End Revision + +`timescale 1 ps / 1 ps + +module LDPE (Q, D, G, GE, PRE); + + parameter INIT = 1'b1; + + output Q; + wire Q; + + input D, G, GE, PRE; + + tri0 GSR = glbl.GSR; + + + reg q_out; + + initial q_out = INIT; + + assign Q = q_out; + + always @(PRE or D or G or GE or GSR) + if (GSR) + q_out <= INIT; + else + if (PRE) + q_out <= 1; + else if (G && GE) + q_out <= D; + + specify + if (!PRE && G && GE) + (D +=> Q) = (100, 100); + if (!PRE && GE) + (posedge G => (Q +: D)) = (100, 100); + if (!PRE && G) + (posedge GE => (Q +: D)) = (100, 100); + (posedge PRE => (Q +: 1'b1)) = (0, 0); + endspecify +endmodule diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/LDPE_1.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/LDPE_1.v new file mode 100644 index 0000000..4b4b9e8 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/LDPE_1.v @@ -0,0 +1,61 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/LDPE_1.v,v 1.12 2006/04/10 20:46:01 yanx Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Transparent Data Latch with Asynchronous Preset, Gate Enable and Inverted Gate +// /___/ /\ Filename : LDPE_1.v +// \ \ / \ Timestamp : Thu Mar 25 16:42:53 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 02/04/05 - Rev 0.0.1 Remove input/output bufs; Seperate GSR from clock block. +// 08/09/05 - Add GSR to main block (CR 215196). +// 03/31/06 - Add specify block for 100ps delay. (CR 228298) +// End Revision + +`timescale 1 ps / 1 ps + +module LDPE_1 (Q, D, G, GE, PRE); + + parameter INIT = 1'b1; + + output Q; + wire Q; + + input D, G, GE, PRE; + + tri0 GSR = glbl.GSR; + + + reg q_out; + + initial q_out = INIT; + + assign Q = q_out; + + always @(PRE or D or G or GE or GSR) + if (GSR) + q_out <= INIT; + else + if (PRE) + q_out <= 1; + else if (!G && GE) + q_out <= D; + + specify + if (!PRE && !G && GE) + (D +=> Q) = (100, 100); + if (!PRE && GE) + (negedge G => (Q +: D)) = (100, 100); + if (!PRE && !G) + (posedge GE => (Q +: D)) = (100, 100); + (posedge PRE => (Q +: 1'b1)) = (0, 0); + endspecify +endmodule diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/LDP_1.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/LDP_1.v new file mode 100644 index 0000000..091b16e --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/LDP_1.v @@ -0,0 +1,59 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/LDP_1.v,v 1.12 2006/04/10 20:46:01 yanx Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Transparent Data Latch with Asynchronous Preset and Inverted Gate +// /___/ /\ Filename : LDP_1.v +// \ \ / \ Timestamp : Thu Mar 25 16:42:53 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 02/04/05 - Rev 0.0.1 Remove input/output bufs; Seperate GSR from clock block. +// 08/09/05 - Add GSR to main block (CR 215196). +// 03/31/06 - Add specify block for 100ps delay. (CR 228298) +// End Revision + +`timescale 1 ps / 1 ps + +module LDP_1 (Q, D, G, PRE); + + parameter INIT = 1'b1; + + output Q; + wire Q; + + input D, G, PRE; + + tri0 GSR = glbl.GSR; + + + reg q_out; + + initial q_out = INIT; + + assign Q = q_out; + + always @(PRE or D or G or GSR) + if (GSR) + q_out <= INIT; + else + if (PRE) + q_out <= 1; + else if (!G) + q_out <= D; + + specify + if (!PRE && !G) + (D +=> Q) = (100, 100); + if (!PRE) + (negedge G => (Q +: D)) = (100, 100); + (posedge PRE => (Q +: 1'b1)) = (0, 0); + endspecify +endmodule diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/LD_1.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/LD_1.v new file mode 100644 index 0000000..2a38493 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/LD_1.v @@ -0,0 +1,55 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/LD_1.v,v 1.12 2006/04/10 20:46:01 yanx Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Transparent Data Latch with Inverted Gate +// /___/ /\ Filename : LD_1.v +// \ \ / \ Timestamp : Thu Mar 25 16:42:53 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 02/04/05 - Rev 0.0.1 Remove input/output bufs; Seperate GSR from clock block. +// 08/09/05 - Add GSR to main block (CR 215196). +// 03/31/06 - Add specify block for 100ps delay. (CR 228298) +// End Revision + +`timescale 1 ps / 1 ps + +module LD_1 (Q, D, G); + + parameter INIT = 1'b0; + + output Q; + wire Q; + + input D, G; + + tri0 GSR = glbl.GSR; + + + reg q_out; + + initial q_out = INIT; + + assign Q = q_out; + + always @(D or G or GSR) + if (GSR) + q_out <= INIT; + else + if (!G) + q_out <= D; + + specify + if (!G) + (D +=> Q) = (100, 100); + (negedge G => (Q +: D)) = (100, 100); + endspecify +endmodule diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/LUT1.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/LUT1.v new file mode 100644 index 0000000..4e68925 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/LUT1.v @@ -0,0 +1,36 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/LUT1.v,v 1.7 2007/05/23 21:43:39 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / 1-input Look-Up-Table with General Output +// /___/ /\ Filename : LUT1.v +// \ \ / \ Timestamp : Thu Mar 25 16:42:53 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 02/04/05 - Rev 0.0.1 Replace premitive with function; Remove buf. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. + +`timescale 1 ps / 1 ps + + +module LUT1 (O, I0); + + parameter INIT = 2'h0; + + input I0; + + output O; + + wire O; + + assign O = (INIT[0] == INIT[1]) ? INIT[0] : INIT[I0]; + +endmodule diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/LUT1_D.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/LUT1_D.v new file mode 100644 index 0000000..98bc834 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/LUT1_D.v @@ -0,0 +1,37 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/LUT1_D.v,v 1.7 2007/05/23 21:43:39 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / 1-input Look-Up-Table with Dual Output +// /___/ /\ Filename : LUT1_D.v +// \ \ / \ Timestamp : Thu Mar 25 16:42:53 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 02/04/05 - Rev 0.0.1 Replace premitive with function; Remove buf. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. + +`timescale 1 ps / 1 ps + + +module LUT1_D (LO, O, I0); + + parameter INIT = 2'h0; + + input I0; + + output LO, O; + + wire LO, O; + + assign O = (INIT[0] == INIT[1]) ? INIT[0] : INIT[I0]; + assign LO = O; + +endmodule diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/LUT1_L.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/LUT1_L.v new file mode 100644 index 0000000..4e2911a --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/LUT1_L.v @@ -0,0 +1,36 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/LUT1_L.v,v 1.7 2007/05/23 21:43:39 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / 1-input Look-Up-Table with Local Output +// /___/ /\ Filename : LUT1_L.v +// \ \ / \ Timestamp : Thu Mar 25 16:42:53 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 02/04/05 - Rev 0.0.1 Replace premitive with function; Remove buf. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. + +`timescale 1 ps / 1 ps + + +module LUT1_L (LO, I0); + + parameter INIT = 2'h0; + + input I0; + + output LO; + + wire LO; + + assign LO = (INIT[0] == INIT[1]) ? INIT[0] : INIT[I0]; + +endmodule diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/LUT2.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/LUT2.v new file mode 100644 index 0000000..53a9bbd --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/LUT2.v @@ -0,0 +1,52 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/LUT2.v,v 1.7 2007/05/23 21:43:39 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / 2-input Look-Up-Table with General Output +// /___/ /\ Filename : LUT2.v +// \ \ / \ Timestamp : Thu Mar 25 16:42:53 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 02/04/05 - Rev 0.0.1 Replace premitive with function; Remove buf. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. + +`timescale 1 ps / 1 ps + + +module LUT2 (O, I0, I1); + + parameter INIT = 4'h0; + + input I0, I1; + + output O; + + reg O; + wire [1:0] s; + + assign s = {I1, I0}; + + always @(s) + if ((s[1]^s[0] ==1) || (s[1]^s[0] ==0)) + O = INIT[s]; + else if ((INIT[0] == INIT[1]) && (INIT[2] == INIT[3]) && (INIT[0] == INIT[2])) + O = INIT[0]; + else if ((s[1] == 0) && (INIT[0] == INIT[1])) + O = INIT[0]; + else if ((s[1] == 1) && (INIT[2] == INIT[3])) + O = INIT[2]; + else if ((s[0] == 0) && (INIT[0] == INIT[2])) + O = INIT[0]; + else if ((s[0] == 1) && (INIT[1] == INIT[3])) + O = INIT[1]; + else + O = 1'bx; +endmodule diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/LUT2_D.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/LUT2_D.v new file mode 100644 index 0000000..62e7295 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/LUT2_D.v @@ -0,0 +1,54 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/LUT2_D.v,v 1.7 2007/05/23 21:43:39 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / 2-input Look-Up-Table with Dual Output +// /___/ /\ Filename : LUT2_D.v +// \ \ / \ Timestamp : Thu Mar 25 16:42:53 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 02/04/05 - Rev 0.0.1 Replace premitive with function; Remove buf. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. + +`timescale 1 ps / 1 ps + + +module LUT2_D (LO, O, I0, I1); + + parameter INIT = 4'h0; + + input I0, I1; + + output LO, O; + + reg O; + wire LO; + wire [1:0] s; + + assign s = {I1, I0}; + assign LO = O; + + always @(s) + if ((s[1]^s[0] ==1) || (s[1]^s[0] ==0)) + O = INIT[s]; + else if ((INIT[0] == INIT[1]) && (INIT[2] == INIT[3]) && (INIT[0] == INIT[2])) + O = INIT[0]; + else if ((s[1] == 0) && (INIT[0] == INIT[1])) + O = INIT[0]; + else if ((s[1] == 1) && (INIT[2] == INIT[3])) + O = INIT[2]; + else if ((s[0] == 0) && (INIT[0] == INIT[2])) + O = INIT[0]; + else if ((s[0] == 1) && (INIT[1] == INIT[3])) + O = INIT[1]; + else + O = 1'bx; +endmodule diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/LUT2_L.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/LUT2_L.v new file mode 100644 index 0000000..8d27d0c --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/LUT2_L.v @@ -0,0 +1,53 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/LUT2_L.v,v 1.7 2007/05/23 21:43:39 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / 2-input Look-Up-Table with Local Output +// /___/ /\ Filename : LUT2_L.v +// \ \ / \ Timestamp : Thu Mar 25 16:42:54 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 02/04/05 - Rev 0.0.1 Replace premitive with function; Remove buf. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. + +`timescale 1 ps / 1 ps + + +module LUT2_L (LO, I0, I1); + + parameter INIT = 4'h0; + + input I0, I1; + + output LO; + + reg LO; + wire [1:0] s; + + assign s = {I1, I0}; + + always @(s) + if ((s[1]^s[0] ==1) || (s[1]^s[0] ==0)) + LO = INIT[s]; + else if ((INIT[0] == INIT[1]) && (INIT[2] == INIT[3]) && (INIT[0] == INIT[2])) + LO = INIT[0]; + else if ((s[1] == 0) && (INIT[0] == INIT[1])) + LO = INIT[0]; + else if ((s[1] == 1) && (INIT[2] == INIT[3])) + LO = INIT[2]; + else if ((s[0] == 0) && (INIT[0] == INIT[2])) + LO = INIT[0]; + else if ((s[0] == 1) && (INIT[1] == INIT[3])) + LO = INIT[1]; + else + LO = 1'bx; + +endmodule diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/LUT3.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/LUT3.v new file mode 100644 index 0000000..15775e1 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/LUT3.v @@ -0,0 +1,68 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/LUT3.v,v 1.7 2007/05/23 21:43:39 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / 3-input Look-Up-Table with General Output +// /___/ /\ Filename : LUT3.v +// \ \ / \ Timestamp : Thu Mar 25 16:42:54 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 02/04/05 - Rev 0.0.1 Replace premitive with function; Remove buf. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. + +`timescale 1 ps / 1 ps + + +module LUT3 (O, I0, I1, I2); + + parameter INIT = 8'h00; + + input I0, I1, I2; + + output O; + + reg O; + reg tmp; + + always @( I2 or I1 or I0 ) begin + tmp = I0 ^ I1 ^ I2; + if ( tmp == 0 || tmp == 1) + O = INIT[{I2, I1, I0}]; + else + O = lut3_mux4 ( {1'b0, 1'b0, lut3_mux4 (INIT[7:4], {I1, I0}), + lut3_mux4 (INIT[3:0], {I1, I0}) }, {1'b0, I2}); + end + + function lut3_mux4; + input [3:0] d; + input [1:0] s; + + begin + if ((s[1]^s[0] ==1) || (s[1]^s[0] ==0)) + lut3_mux4 = d[s]; + else if ((d[0] === d[1]) && (d[2] === d[3]) && (d[0] === d[2])) + lut3_mux4 = d[0]; + else if ((s[1] == 0) && (d[0] === d[1])) + lut3_mux4 = d[0]; + else if ((s[1] == 1) && (d[2] === d[3])) + lut3_mux4 = d[2]; + else if ((s[0] == 0) && (d[0] === d[2])) + lut3_mux4 = d[0]; + else if ((s[0] == 1) && (d[1] === d[3])) + lut3_mux4 = d[1]; + else + lut3_mux4 = 1'bx; + end + endfunction + +endmodule + + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/LUT3_D.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/LUT3_D.v new file mode 100644 index 0000000..36b792e --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/LUT3_D.v @@ -0,0 +1,69 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/LUT3_D.v,v 1.7 2007/05/23 21:43:39 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / 3-input Look-Up-Table with Dual Output +// /___/ /\ Filename : LUT3_D.v +// \ \ / \ Timestamp : Thu Mar 25 16:42:54 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 02/04/05 - Rev 0.0.1 Replace premitive with function; Remove buf. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. + +`timescale 1 ps / 1 ps + + +module LUT3_D (LO, O, I0, I1, I2); + + parameter INIT = 8'h00; + + input I0, I1, I2; + + output LO, O; + + reg O; + reg tmp; + + assign LO = O; + + always @( I2 or I1 or I0 ) begin + tmp = I0 ^ I1 ^ I2; + if ( tmp == 0 || tmp == 1) + O = INIT[{I2, I1, I0}]; + else + O = lut3_mux4 ( {1'b0, 1'b0, lut3_mux4 (INIT[7:4], {I1, I0}), + lut3_mux4 (INIT[3:0], {I1, I0}) }, {1'b0, I2}); + end + + function lut3_mux4; + input [3:0] d; + input [1:0] s; + + begin + if ((s[1]^s[0] ==1) || (s[1]^s[0] ==0)) + lut3_mux4 = d[s]; + else if ((d[0] === d[1]) && (d[2] === d[3]) && (d[0] === d[2])) + lut3_mux4 = d[0]; + else if ((s[1] == 0) && (d[0] === d[1])) + lut3_mux4 = d[0]; + else if ((s[1] == 1) && (d[2] === d[3])) + lut3_mux4 = d[2]; + else if ((s[0] == 0) && (d[0] === d[2])) + lut3_mux4 = d[0]; + else if ((s[0] == 1) && (d[1] === d[3])) + lut3_mux4 = d[1]; + else + lut3_mux4 = 1'bx; + end + endfunction + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/LUT3_L.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/LUT3_L.v new file mode 100644 index 0000000..29583ca --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/LUT3_L.v @@ -0,0 +1,66 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/LUT3_L.v,v 1.7 2007/05/23 21:43:39 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / 3-input Look-Up-Table with Local Output +// /___/ /\ Filename : LUT3_L.v +// \ \ / \ Timestamp : Thu Mar 25 16:42:54 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 02/04/05 - Rev 0.0.1 Replace premitive with function; Remove buf. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. + +`timescale 1 ps / 1 ps + + +module LUT3_L (LO, I0, I1, I2); + + parameter INIT = 8'h00; + + input I0, I1, I2; + + output LO; + reg LO; + reg tmp; + + always @( I2 or I1 or I0 ) begin + tmp = I0 ^ I1 ^ I2; + if ( tmp == 0 || tmp == 1) + LO = INIT[{I2, I1, I0}]; + else + LO = lut3_mux4 ( {1'b0, 1'b0, lut3_mux4 (INIT[7:4], {I1, I0}), + lut3_mux4 (INIT[3:0], {I1, I0}) }, {1'b0, I2}); + end + + function lut3_mux4; + input [3:0] d; + input [1:0] s; + + begin + if ((s[1]^s[0] ==1) || (s[1]^s[0] ==0)) + lut3_mux4 = d[s]; + else if ((d[0] === d[1]) && (d[2] === d[3]) && (d[0] === d[2])) + lut3_mux4 = d[0]; + else if ((s[1] == 0) && (d[0] === d[1])) + lut3_mux4 = d[0]; + else if ((s[1] == 1) && (d[2] === d[3])) + lut3_mux4 = d[2]; + else if ((s[0] == 0) && (d[0] === d[2])) + lut3_mux4 = d[0]; + else if ((s[0] == 1) && (d[1] === d[3])) + lut3_mux4 = d[1]; + else + lut3_mux4 = 1'bx; + end + endfunction + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/LUT4.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/LUT4.v new file mode 100644 index 0000000..cc0f4c8 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/LUT4.v @@ -0,0 +1,76 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/LUT4.v,v 1.7 2007/05/23 21:43:39 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / 4-input Look-Up-Table with General Output +// /___/ /\ Filename : LUT4.v +// \ \ / \ Timestamp : Thu Mar 25 16:42:54 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 02/04/05 - Rev 0.0.1 Replace premitive with function; Remove buf. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. + +`timescale 1 ps / 1 ps + + +module LUT4 (O, I0, I1, I2, I3); + + parameter INIT = 16'h0000; + + input I0, I1, I2, I3; + + output O; + + reg O; + reg tmp; + + always @( I3 or I2 or I1 or I0 ) begin + + tmp = I0 ^ I1 ^ I2 ^ I3; + + if ( tmp == 0 || tmp == 1) + + O = INIT[{I3, I2, I1, I0}]; + + else + + O = lut4_mux4 ( {lut4_mux4 ( INIT[15:12], {I1, I0}), + lut4_mux4 ( INIT[11:8], {I1, I0}), + lut4_mux4 ( INIT[7:4], {I1, I0}), + lut4_mux4 ( INIT[3:0], {I1, I0}) }, {I3, I2}); + end + + function lut4_mux4; + input [3:0] d; + input [1:0] s; + + begin + + if ((s[1]^s[0] ==1) || (s[1]^s[0] ==0)) + + lut4_mux4 = d[s]; + + else if ((d[0] === d[1]) && (d[2] === d[3]) && (d[0] === d[2])) + lut4_mux4 = d[0]; + else if ((s[1] == 0) && (d[0] === d[1])) + lut4_mux4 = d[0]; + else if ((s[1] == 1) && (d[2] === d[3])) + lut4_mux4 = d[2]; + else if ((s[0] == 0) && (d[0] === d[2])) + lut4_mux4 = d[0]; + else if ((s[0] == 1) && (d[1] === d[3])) + lut4_mux4 = d[1]; + else + lut4_mux4 = 1'bx; + end + endfunction + +endmodule diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/LUT4_D.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/LUT4_D.v new file mode 100644 index 0000000..825db12 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/LUT4_D.v @@ -0,0 +1,79 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/LUT4_D.v,v 1.7 2007/05/23 21:43:39 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / 4-input Look-Up-Table with Dual Output +// /___/ /\ Filename : LUT4_D.v +// \ \ / \ Timestamp : Thu Mar 25 16:42:54 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 02/04/05 - Rev 0.0.1 Replace premitive with function; Remove buf. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. + +`timescale 1 ps / 1 ps + + +module LUT4_D (LO, O, I0, I1, I2, I3); + + parameter INIT = 16'h0000; + + input I0, I1, I2, I3; + + output O, LO; + + reg O; + reg tmp; + wire LO; + + assign LO = O; + + always @( I3 or I2 or I1 or I0 ) begin + + tmp = I0 ^ I1 ^ I2 ^ I3; + + if ( tmp == 0 || tmp == 1) + + O = INIT[{I3, I2, I1, I0}]; + + else + + O = lut4_mux4 ( {lut4_mux4 ( INIT[15:12], {I1, I0}), + lut4_mux4 ( INIT[11:8], {I1, I0}), + lut4_mux4 ( INIT[7:4], {I1, I0}), + lut4_mux4 ( INIT[3:0], {I1, I0}) }, {I3, I2}); + end + + function lut4_mux4; + input [3:0] d; + input [1:0] s; + + begin + + if ((s[1]^s[0] ==1) || (s[1]^s[0] ==0)) + + lut4_mux4 = d[s]; + + else if ((d[0] === d[1]) && (d[2] === d[3]) && (d[0] === d[2])) + lut4_mux4 = d[0]; + else if ((s[1] == 0) && (d[0] === d[1])) + lut4_mux4 = d[0]; + else if ((s[1] == 1) && (d[2] === d[3])) + lut4_mux4 = d[2]; + else if ((s[0] == 0) && (d[0] === d[2])) + lut4_mux4 = d[0]; + else if ((s[0] == 1) && (d[1] === d[3])) + lut4_mux4 = d[1]; + else + lut4_mux4 = 1'bx; + end + endfunction + +endmodule diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/LUT4_L.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/LUT4_L.v new file mode 100644 index 0000000..8250158 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/LUT4_L.v @@ -0,0 +1,76 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/LUT4_L.v,v 1.7 2007/05/23 21:43:39 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / 4-input Look-Up-Table with Local Output +// /___/ /\ Filename : LUT4_L.v +// \ \ / \ Timestamp : Thu Mar 25 16:42:54 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 02/04/05 - Rev 0.0.1 Replace premitive with function; Remove buf. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. + +`timescale 1 ps / 1 ps + + +module LUT4_L (LO, I0, I1, I2, I3); + + parameter INIT = 16'h0000; + + input I0, I1, I2, I3; + + output LO; + + reg LO; + reg tmp; + + always @( I3 or I2 or I1 or I0 ) begin + + tmp = I0 ^ I1 ^ I2 ^ I3; + + if ( tmp == 0 || tmp == 1) + + LO = INIT[{I3, I2, I1, I0}]; + + else + + LO = lut4_mux4 ( {lut4_mux4 ( INIT[15:12], {I1, I0}), + lut4_mux4 ( INIT[11:8], {I1, I0}), + lut4_mux4 ( INIT[7:4], {I1, I0}), + lut4_mux4 ( INIT[3:0], {I1, I0}) }, {I3, I2}); + end + + function lut4_mux4; + input [3:0] d; + input [1:0] s; + + begin + + if ((s[1]^s[0] ==1) || (s[1]^s[0] ==0)) + + lut4_mux4 = d[s]; + + else if ((d[0] === d[1]) && (d[2] === d[3]) && (d[0] === d[2])) + lut4_mux4 = d[0]; + else if ((s[1] == 0) && (d[0] === d[1])) + lut4_mux4 = d[0]; + else if ((s[1] == 1) && (d[2] === d[3])) + lut4_mux4 = d[2]; + else if ((s[0] == 0) && (d[0] === d[2])) + lut4_mux4 = d[0]; + else if ((s[0] == 1) && (d[1] === d[3])) + lut4_mux4 = d[1]; + else + lut4_mux4 = 1'bx; + end + endfunction + +endmodule diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/LUT5.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/LUT5.v new file mode 100644 index 0000000..ab12dbb --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/LUT5.v @@ -0,0 +1,115 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/rainier/LUT5.v,v 1.6 2007/06/01 00:22:57 yanx Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / 5-input Look-Up-Table with General Output +// /___/ /\ Filename : LUT5.v +// \ \ / \ Timestamp : Thu Mar 25 16:42:54 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 02/04/05 - Replace premitive with function; Remove buf. +// 05/30/07 - Change timescale to 1 ps / 1ps. +// End Revision + +`timescale 1 ps / 1 ps + + +module LUT5 (O, I0, I1, I2, I3, I4); + + parameter INIT = 32'h00000000; + + input I0, I1, I2, I3, I4; + + output O; + + reg O; + reg tmp; + + always @( I4 or I3 or I2 or I1 or I0 ) begin + + tmp = I0 ^ I1 ^ I2 ^ I3 ^ I4; + + if ( tmp == 0 || tmp == 1) + + O = INIT[{I4, I3, I2, I1, I0}]; + + else + + O = lut4_mux4 ( + { lut6_mux8 ( INIT[31:24], {I2, I1, I0}), + lut6_mux8 ( INIT[23:16], {I2, I1, I0}), + lut6_mux8 ( INIT[15:8], {I2, I1, I0}), + lut6_mux8 ( INIT[7:0], {I2, I1, I0}) }, { I4, I3}); + end + + function lut6_mux8; + input [7:0] d; + input [2:0] s; + + begin + + if ((s[2]^s[1]^s[0] ==1) || (s[2]^s[1]^s[0] ==0)) + + lut6_mux8 = d[s]; + + else + if ( ~(|d)) + lut6_mux8 = 1'b0; + else if ((&d)) + lut6_mux8 = 1'b1; + else if (((s[1]^s[0] ==1'b1) || (s[1]^s[0] ==1'b0)) && (d[{1'b0,s[1:0]}]===d[{1'b1,s[1:0]}])) + lut6_mux8 = d[{1'b0,s[1:0]}]; + else if (((s[2]^s[0] ==1) || (s[2]^s[0] ==0)) && (d[{s[2],1'b0,s[0]}]===d[{s[2],1'b1,s[0]}])) + lut6_mux8 = d[{s[2],1'b0,s[0]}]; + else if (((s[2]^s[1] ==1) || (s[2]^s[1] ==0)) && (d[{s[2],s[1],1'b0}]===d[{s[2],s[1],1'b1}])) + lut6_mux8 = d[{s[2],s[1],1'b0}]; + else if (((s[0] ==1) || (s[0] ==0)) && (d[{1'b0,1'b0,s[0]}]===d[{1'b0,1'b1,s[0]}]) && + (d[{1'b0,1'b0,s[0]}]===d[{1'b1,1'b0,s[0]}]) && (d[{1'b0,1'b0,s[0]}]===d[{1'b1,1'b1,s[0]}])) + lut6_mux8 = d[{1'b0,1'b0,s[0]}]; + else if (((s[1] ==1) || (s[1] ==0)) && (d[{1'b0,s[1],1'b0}]===d[{1'b0,s[1],1'b1}]) && + (d[{1'b0,s[1],1'b0}]===d[{1'b1,s[1],1'b0}]) && (d[{1'b0,s[1],1'b0}]===d[{1'b1,s[1],1'b1}])) + lut6_mux8 = d[{1'b0,s[1],1'b0}]; + else if (((s[2] ==1) || (s[2] ==0)) && (d[{s[2],1'b0,1'b0}]===d[{s[2],1'b0,1'b1}]) && + (d[{s[2],1'b0,1'b0}]===d[{s[2],1'b1,1'b0}]) && (d[{s[2],1'b0,1'b0}]===d[{s[2],1'b1,1'b1}])) + lut6_mux8 = d[{s[2],1'b0,1'b0}]; + else + lut6_mux8 = 1'bx; + end + endfunction + + + function lut4_mux4; + input [3:0] d; + input [1:0] s; + + begin + + if ((s[1]^s[0] ==1) || (s[1]^s[0] ==0)) + + lut4_mux4 = d[s]; + + else if ((d[0] === d[1]) && (d[2] === d[3]) && (d[0] === d[2]) ) + lut4_mux4 = d[0]; + else if ((s[1] == 0) && (d[0] === d[1])) + lut4_mux4 = d[0]; + else if ((s[1] == 1) && (d[2] === d[3])) + lut4_mux4 = d[2]; + else if ((s[0] == 0) && (d[0] === d[2])) + lut4_mux4 = d[0]; + else if ((s[0] == 1) && (d[1] === d[3])) + lut4_mux4 = d[1]; + else + lut4_mux4 = 1'bx; + + end + endfunction + +endmodule diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/LUT5_D.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/LUT5_D.v new file mode 100644 index 0000000..f3ed0af --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/LUT5_D.v @@ -0,0 +1,118 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/rainier/LUT5_D.v,v 1.3 2007/06/01 00:22:57 yanx Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / 5-input Look-Up-Table with Dual Output +// /___/ /\ Filename : LUT5_D.v +// \ \ / \ Timestamp : Thu Mar 25 16:42:54 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 02/04/05 - Replace premitive with function; Remove buf. +// 05/30/07 - Change timescale to 1 ps / 1ps. +// End Revision + +`timescale 1 ps / 1 ps + + +module LUT5_D (LO, O, I0, I1, I2, I3, I4); + + parameter INIT = 32'h00000000; + + input I0, I1, I2, I3, I4; + + output LO, O; + + reg O; + reg tmp; + wire LO; + + assign LO = O; + + always @( I4 or I3 or I2 or I1 or I0 ) begin + + tmp = I0 ^ I1 ^ I2 ^ I3 ^ I4; + + if ( tmp == 0 || tmp == 1) + + O = INIT[{I4, I3, I2, I1, I0}]; + + else + + O = lut4_mux4 ( + { lut6_mux8 ( INIT[31:24], {I2, I1, I0}), + lut6_mux8 ( INIT[23:16], {I2, I1, I0}), + lut6_mux8 ( INIT[15:8], {I2, I1, I0}), + lut6_mux8 ( INIT[7:0], {I2, I1, I0}) }, { I4, I3}); + end + + function lut6_mux8; + input [7:0] d; + input [2:0] s; + + begin + + if ((s[2]^s[1]^s[0] ==1) || (s[2]^s[1]^s[0] ==0)) + + lut6_mux8 = d[s]; + + else + if ( ~(|d)) + lut6_mux8 = 1'b0; + else if ((&d)) + lut6_mux8 = 1'b1; + else if (((s[1]^s[0] ==1'b1) || (s[1]^s[0] ==1'b0)) && (d[{1'b0,s[1:0]}]===d[{1'b1,s[1:0]}])) + lut6_mux8 = d[{1'b0,s[1:0]}]; + else if (((s[2]^s[0] ==1) || (s[2]^s[0] ==0)) && (d[{s[2],1'b0,s[0]}]===d[{s[2],1'b1,s[0]}])) + lut6_mux8 = d[{s[2],1'b0,s[0]}]; + else if (((s[2]^s[1] ==1) || (s[2]^s[1] ==0)) && (d[{s[2],s[1],1'b0}]===d[{s[2],s[1],1'b1}])) + lut6_mux8 = d[{s[2],s[1],1'b0}]; + else if (((s[0] ==1) || (s[0] ==0)) && (d[{1'b0,1'b0,s[0]}]===d[{1'b0,1'b1,s[0]}]) && + (d[{1'b0,1'b0,s[0]}]===d[{1'b1,1'b0,s[0]}]) && (d[{1'b0,1'b0,s[0]}]===d[{1'b1,1'b1,s[0]}])) + lut6_mux8 = d[{1'b0,1'b0,s[0]}]; + else if (((s[1] ==1) || (s[1] ==0)) && (d[{1'b0,s[1],1'b0}]===d[{1'b0,s[1],1'b1}]) && + (d[{1'b0,s[1],1'b0}]===d[{1'b1,s[1],1'b0}]) && (d[{1'b0,s[1],1'b0}]===d[{1'b1,s[1],1'b1}])) + lut6_mux8 = d[{1'b0,s[1],1'b0}]; + else if (((s[2] ==1) || (s[2] ==0)) && (d[{s[2],1'b0,1'b0}]===d[{s[2],1'b0,1'b1}]) && + (d[{s[2],1'b0,1'b0}]===d[{s[2],1'b1,1'b0}]) && (d[{s[2],1'b0,1'b0}]===d[{s[2],1'b1,1'b1}])) + lut6_mux8 = d[{s[2],1'b0,1'b0}]; + else + lut6_mux8 = 1'bx; + end + endfunction + + + function lut4_mux4; + input [3:0] d; + input [1:0] s; + + begin + + if ((s[1]^s[0] ==1) || (s[1]^s[0] ==0)) + + lut4_mux4 = d[s]; + + else if ((d[0] === d[1]) && (d[2] === d[3]) && (d[0] === d[2]) ) + lut4_mux4 = d[0]; + else if ((s[1] == 0) && (d[0] === d[1])) + lut4_mux4 = d[0]; + else if ((s[1] == 1) && (d[2] === d[3])) + lut4_mux4 = d[2]; + else if ((s[0] == 0) && (d[0] === d[2])) + lut4_mux4 = d[0]; + else if ((s[0] == 1) && (d[1] === d[3])) + lut4_mux4 = d[1]; + else + lut4_mux4 = 1'bx; + + end + endfunction + +endmodule diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/LUT5_L.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/LUT5_L.v new file mode 100644 index 0000000..13896aa --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/LUT5_L.v @@ -0,0 +1,115 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/rainier/LUT5_L.v,v 1.3 2007/06/01 00:22:57 yanx Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / 5-input Look-Up-Table with Local Output +// /___/ /\ Filename : LUT5_L.v +// \ \ / \ Timestamp : Thu Mar 25 16:42:54 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 02/04/05 - Replace premitive with function; Remove buf. +// 05/30/07 - Change timescale to 1 ps / 1ps. +// End Revision + +`timescale 1 ps / 1 ps + + +module LUT5_L (LO, I0, I1, I2, I3, I4); + + parameter INIT = 32'h00000000; + + input I0, I1, I2, I3, I4; + + output LO; + + reg LO; + reg tmp; + + always @( I4 or I3 or I2 or I1 or I0 ) begin + + tmp = I0 ^ I1 ^ I2 ^ I3 ^ I4; + + if ( tmp == 0 || tmp == 1) + + LO = INIT[{I4, I3, I2, I1, I0}]; + + else + + LO = lut4_mux4 ( + { lut6_mux8 ( INIT[31:24], {I2, I1, I0}), + lut6_mux8 ( INIT[23:16], {I2, I1, I0}), + lut6_mux8 ( INIT[15:8], {I2, I1, I0}), + lut6_mux8 ( INIT[7:0], {I2, I1, I0}) }, { I4, I3}); + end + + function lut6_mux8; + input [7:0] d; + input [2:0] s; + + begin + + if ((s[2]^s[1]^s[0] ==1) || (s[2]^s[1]^s[0] ==0)) + + lut6_mux8 = d[s]; + + else + if ( ~(|d)) + lut6_mux8 = 1'b0; + else if ((&d)) + lut6_mux8 = 1'b1; + else if (((s[1]^s[0] ==1'b1) || (s[1]^s[0] ==1'b0)) && (d[{1'b0,s[1:0]}]===d[{1'b1,s[1:0]}])) + lut6_mux8 = d[{1'b0,s[1:0]}]; + else if (((s[2]^s[0] ==1) || (s[2]^s[0] ==0)) && (d[{s[2],1'b0,s[0]}]===d[{s[2],1'b1,s[0]}])) + lut6_mux8 = d[{s[2],1'b0,s[0]}]; + else if (((s[2]^s[1] ==1) || (s[2]^s[1] ==0)) && (d[{s[2],s[1],1'b0}]===d[{s[2],s[1],1'b1}])) + lut6_mux8 = d[{s[2],s[1],1'b0}]; + else if (((s[0] ==1) || (s[0] ==0)) && (d[{1'b0,1'b0,s[0]}]===d[{1'b0,1'b1,s[0]}]) && + (d[{1'b0,1'b0,s[0]}]===d[{1'b1,1'b0,s[0]}]) && (d[{1'b0,1'b0,s[0]}]===d[{1'b1,1'b1,s[0]}])) + lut6_mux8 = d[{1'b0,1'b0,s[0]}]; + else if (((s[1] ==1) || (s[1] ==0)) && (d[{1'b0,s[1],1'b0}]===d[{1'b0,s[1],1'b1}]) && + (d[{1'b0,s[1],1'b0}]===d[{1'b1,s[1],1'b0}]) && (d[{1'b0,s[1],1'b0}]===d[{1'b1,s[1],1'b1}])) + lut6_mux8 = d[{1'b0,s[1],1'b0}]; + else if (((s[2] ==1) || (s[2] ==0)) && (d[{s[2],1'b0,1'b0}]===d[{s[2],1'b0,1'b1}]) && + (d[{s[2],1'b0,1'b0}]===d[{s[2],1'b1,1'b0}]) && (d[{s[2],1'b0,1'b0}]===d[{s[2],1'b1,1'b1}])) + lut6_mux8 = d[{s[2],1'b0,1'b0}]; + else + lut6_mux8 = 1'bx; + end + endfunction + + + function lut4_mux4; + input [3:0] d; + input [1:0] s; + + begin + + if ((s[1]^s[0] ==1) || (s[1]^s[0] ==0)) + + lut4_mux4 = d[s]; + + else if ((d[0] === d[1]) && (d[2] === d[3]) && (d[0] === d[2]) ) + lut4_mux4 = d[0]; + else if ((s[1] == 0) && (d[0] === d[1])) + lut4_mux4 = d[0]; + else if ((s[1] == 1) && (d[2] === d[3])) + lut4_mux4 = d[2]; + else if ((s[0] == 0) && (d[0] === d[2])) + lut4_mux4 = d[0]; + else if ((s[0] == 1) && (d[1] === d[3])) + lut4_mux4 = d[1]; + else + lut4_mux4 = 1'bx; + + end + endfunction + +endmodule diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/LUT6.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/LUT6.v new file mode 100644 index 0000000..e9581fa --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/LUT6.v @@ -0,0 +1,91 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/rainier/LUT6.v,v 1.6 2007/06/01 00:22:57 yanx Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / 6-input Look-Up-Table with General Output +// /___/ /\ Filename : LUT6.v +// \ \ / \ Timestamp : Thu Mar 25 16:42:54 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 02/04/05 - Replace premitive with function; Remove buf. +// 05/30/07 - Change timescale to 1 ps / 1ps. +// End Revision + +`timescale 1 ps / 1 ps + + +module LUT6 (O, I0, I1, I2, I3, I4, I5); + + parameter INIT = 64'h0000000000000000; + + input I0, I1, I2, I3, I4, I5; + + output O; + + reg O; + reg tmp; + + always @( I5 or I4 or I3 or I2 or I1 or I0 ) begin + + tmp = I0 ^ I1 ^ I2 ^ I3 ^ I4 ^ I5; + + if ( tmp == 0 || tmp == 1) + + O = INIT[{I5, I4, I3, I2, I1, I0}]; + + else + + O = lut6_mux8 ( {lut6_mux8 ( INIT[63:56], {I2, I1, I0}), + lut6_mux8 ( INIT[55:48], {I2, I1, I0}), + lut6_mux8 ( INIT[47:40], {I2, I1, I0}), + lut6_mux8 ( INIT[39:32], {I2, I1, I0}), + lut6_mux8 ( INIT[31:24], {I2, I1, I0}), + lut6_mux8 ( INIT[23:16], {I2, I1, I0}), + lut6_mux8 ( INIT[15:8], {I2, I1, I0}), + lut6_mux8 ( INIT[7:0], {I2, I1, I0}) }, {I5, I4, I3}); + end + + function lut6_mux8; + input [7:0] d; + input [2:0] s; + + begin + + if ((s[2]^s[1]^s[0] ==1) || (s[2]^s[1]^s[0] ==0)) + + lut6_mux8 = d[s]; + + else + if ( ~(|d)) + lut6_mux8 = 1'b0; + else if ((&d)) + lut6_mux8 = 1'b1; + else if (((s[1]^s[0] ==1'b1) || (s[1]^s[0] ==1'b0)) && (d[{1'b0,s[1:0]}]==d[{1'b1,s[1:0]}])) + lut6_mux8 = d[{1'b0,s[1:0]}]; + else if (((s[2]^s[0] ==1) || (s[2]^s[0] ==0)) && (d[{s[2],1'b0,s[0]}]==d[{s[2],1'b1,s[0]}])) + lut6_mux8 = d[{s[2],1'b0,s[0]}]; + else if (((s[2]^s[1] ==1) || (s[2]^s[1] ==0)) && (d[{s[2],s[1],1'b0}]==d[{s[2],s[1],1'b1}])) + lut6_mux8 = d[{s[2],s[1],1'b0}]; + else if (((s[0] ==1) || (s[0] ==0)) && (d[{1'b0,1'b0,s[0]}]==d[{1'b0,1'b1,s[0]}]) && + (d[{1'b0,1'b0,s[0]}]==d[{1'b1,1'b0,s[0]}]) && (d[{1'b0,1'b0,s[0]}]==d[{1'b1,1'b1,s[0]}])) + lut6_mux8 = d[{1'b0,1'b0,s[0]}]; + else if (((s[1] ==1) || (s[1] ==0)) && (d[{1'b0,s[1],1'b0}]==d[{1'b0,s[1],1'b1}]) && + (d[{1'b0,s[1],1'b0}]==d[{1'b1,s[1],1'b0}]) && (d[{1'b0,s[1],1'b0}]==d[{1'b1,s[1],1'b1}])) + lut6_mux8 = d[{1'b0,s[1],1'b0}]; + else if (((s[2] ==1) || (s[2] ==0)) && (d[{s[2],1'b0,1'b0}]==d[{s[2],1'b0,1'b1}]) && + (d[{s[2],1'b0,1'b0}]==d[{s[2],1'b1,1'b0}]) && (d[{s[2],1'b0,1'b0}]==d[{s[2],1'b1,1'b1}])) + lut6_mux8 = d[{s[2],1'b0,1'b0}]; + else + lut6_mux8 = 1'bx; + end + endfunction + +endmodule diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/LUT6_2.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/LUT6_2.v new file mode 100644 index 0000000..b88fb77 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/LUT6_2.v @@ -0,0 +1,141 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/rainier/LUT6_2.v,v 1.2 2007/06/01 00:22:57 yanx Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / 6-input Look-Up-Table with Two General Outputs +// /___/ /\ Filename : LUT6_2.v +// \ \ / \ Timestamp : +// \___\/\___\ +// +// Revision: +// 08/08/64 - Initial version. +// 05/30/07 - Change timescale to 1 ps / 1ps. +// End Revision + +`timescale 1 ps / 1 ps + + +module LUT6_2 (O5, O6, I0, I1, I2, I3, I4, I5); + + parameter INIT = 64'h0000000000000000; + + input I0, I1, I2, I3, I4, I5; + + output O5, O6; + + reg [63:0] init_reg = INIT; + reg [31:0] init_l, init_h; + reg O_l, O_h, tmp; + reg O5, O6; + + initial begin + init_l = init_reg[31:0]; + init_h = init_reg[63:32]; + end + + always @(I5 or O_l or O_h) begin + O5 = O_l; + if (I5 == 1) + O6 = O_h; + else if (I5 == 0) + O6 = O_l; + else begin + if (O_h == 0 && O_l == 0) + O6 = 1'b0; + else if (O_h == 1 && O_l == 1) + O6 = 1'b1; + else + O6 = 1'bx; + end + end + + + always @( I4 or I3 or I2 or I1 or I0 ) begin + tmp = I0 ^ I1 ^ I2 ^ I3 ^ I4; + if ( tmp == 0 || tmp == 1) begin + O_l = init_l[{I4, I3, I2, I1, I0}]; + O_h = init_h[{I4, I3, I2, I1, I0}]; + end + else begin + O_l = lut4_mux4 ( + { lut6_mux8 ( init_l[31:24], {I2, I1, I0}), + lut6_mux8 ( init_l[23:16], {I2, I1, I0}), + lut6_mux8 ( init_l[15:8], {I2, I1, I0}), + lut6_mux8 ( init_l[7:0], {I2, I1, I0}) }, { I4, I3}); + O_h = lut4_mux4 ( + { lut6_mux8 ( init_h[31:24], {I2, I1, I0}), + lut6_mux8 ( init_h[23:16], {I2, I1, I0}), + lut6_mux8 ( init_h[15:8], {I2, I1, I0}), + lut6_mux8 ( init_h[7:0], {I2, I1, I0}) }, { I4, I3}); + end + end + + function lut6_mux8; + input [7:0] d; + input [2:0] s; + + begin + + if ((s[2]^s[1]^s[0] ==1) || (s[2]^s[1]^s[0] ==0)) + + lut6_mux8 = d[s]; + + else + if ( ~(|d)) + lut6_mux8 = 1'b0; + else if ((&d)) + lut6_mux8 = 1'b1; + else if (((s[1]^s[0] ==1'b1) || (s[1]^s[0] ==1'b0)) && (d[{1'b0,s[1:0]}]===d[{1'b1,s[1:0]}])) + lut6_mux8 = d[{1'b0,s[1:0]}]; + else if (((s[2]^s[0] ==1) || (s[2]^s[0] ==0)) && (d[{s[2],1'b0,s[0]}]===d[{s[2],1'b1,s[0]}])) + lut6_mux8 = d[{s[2],1'b0,s[0]}]; + else if (((s[2]^s[1] ==1) || (s[2]^s[1] ==0)) && (d[{s[2],s[1],1'b0}]===d[{s[2],s[1],1'b1}])) + lut6_mux8 = d[{s[2],s[1],1'b0}]; + else if (((s[0] ==1) || (s[0] ==0)) && (d[{1'b0,1'b0,s[0]}]===d[{1'b0,1'b1,s[0]}]) && + (d[{1'b0,1'b0,s[0]}]===d[{1'b1,1'b0,s[0]}]) && (d[{1'b0,1'b0,s[0]}]===d[{1'b1,1'b1,s[0]}])) + lut6_mux8 = d[{1'b0,1'b0,s[0]}]; + else if (((s[1] ==1) || (s[1] ==0)) && (d[{1'b0,s[1],1'b0}]===d[{1'b0,s[1],1'b1}]) && + (d[{1'b0,s[1],1'b0}]===d[{1'b1,s[1],1'b0}]) && (d[{1'b0,s[1],1'b0}]===d[{1'b1,s[1],1'b1}])) + lut6_mux8 = d[{1'b0,s[1],1'b0}]; + else if (((s[2] ==1) || (s[2] ==0)) && (d[{s[2],1'b0,1'b0}]===d[{s[2],1'b0,1'b1}]) && + (d[{s[2],1'b0,1'b0}]===d[{s[2],1'b1,1'b0}]) && (d[{s[2],1'b0,1'b0}]===d[{s[2],1'b1,1'b1}])) + lut6_mux8 = d[{s[2],1'b0,1'b0}]; + else + lut6_mux8 = 1'bx; + end + endfunction + + + function lut4_mux4; + input [3:0] d; + input [1:0] s; + + begin + + if ((s[1]^s[0] ==1) || (s[1]^s[0] ==0)) + + lut4_mux4 = d[s]; + + else if ((d[0] === d[1]) && (d[2] === d[3]) && (d[0] === d[2]) ) + lut4_mux4 = d[0]; + else if ((s[1] == 0) && (d[0] === d[1])) + lut4_mux4 = d[0]; + else if ((s[1] == 1) && (d[2] === d[3])) + lut4_mux4 = d[2]; + else if ((s[0] == 0) && (d[0] === d[2])) + lut4_mux4 = d[0]; + else if ((s[0] == 1) && (d[1] === d[3])) + lut4_mux4 = d[1]; + else + lut4_mux4 = 1'bx; + + end + endfunction + +endmodule diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/LUT6_D.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/LUT6_D.v new file mode 100644 index 0000000..893b794 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/LUT6_D.v @@ -0,0 +1,94 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/rainier/LUT6_D.v,v 1.3 2007/06/01 00:22:57 yanx Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / 6-input Look-Up-Table with Dual Output +// /___/ /\ Filename : LUT6_D.v +// \ \ / \ Timestamp : Thu Mar 25 16:42:54 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 02/04/05 - Replace premitive with function; Remove buf. +// 05/30/07 - Change timescale to 1 ps / 1ps. +// End Revision + +`timescale 1 ps / 1 ps + + +module LUT6_D (LO, O, I0, I1, I2, I3, I4, I5); + + parameter INIT = 64'h0000000000000000; + + input I0, I1, I2, I3, I4, I5; + + output LO, O; + + reg O; + reg tmp; + wire LO; + + assign LO = O; + + always @( I5 or I4 or I3 or I2 or I1 or I0 ) begin + + tmp = I0 ^ I1 ^ I2 ^ I3 ^ I4 ^ I5; + + if ( tmp == 0 || tmp == 1) + + O = INIT[{I5, I4, I3, I2, I1, I0}]; + + else + + O = lut6_mux8 ( {lut6_mux8 ( INIT[63:56], {I2, I1, I0}), + lut6_mux8 ( INIT[55:48], {I2, I1, I0}), + lut6_mux8 ( INIT[47:40], {I2, I1, I0}), + lut6_mux8 ( INIT[39:32], {I2, I1, I0}), + lut6_mux8 ( INIT[31:24], {I2, I1, I0}), + lut6_mux8 ( INIT[23:16], {I2, I1, I0}), + lut6_mux8 ( INIT[15:8], {I2, I1, I0}), + lut6_mux8 ( INIT[7:0], {I2, I1, I0}) }, {I5, I4, I3}); + end + + function lut6_mux8; + input [7:0] d; + input [2:0] s; + + begin + + if ((s[2]^s[1]^s[0] ==1) || (s[2]^s[1]^s[0] ==0)) + + lut6_mux8 = d[s]; + + else + if ( ~(|d)) + lut6_mux8 = 1'b0; + else if ((&d)) + lut6_mux8 = 1'b1; + else if (((s[1]^s[0] ==1'b1) || (s[1]^s[0] ==1'b0)) && (d[{1'b0,s[1:0]}]==d[{1'b1,s[1:0]}])) + lut6_mux8 = d[{1'b0,s[1:0]}]; + else if (((s[2]^s[0] ==1) || (s[2]^s[0] ==0)) && (d[{s[2],1'b0,s[0]}]==d[{s[2],1'b1,s[0]}])) + lut6_mux8 = d[{s[2],1'b0,s[0]}]; + else if (((s[2]^s[1] ==1) || (s[2]^s[1] ==0)) && (d[{s[2],s[1],1'b0}]==d[{s[2],s[1],1'b1}])) + lut6_mux8 = d[{s[2],s[1],1'b0}]; + else if (((s[0] ==1) || (s[0] ==0)) && (d[{1'b0,1'b0,s[0]}]==d[{1'b0,1'b1,s[0]}]) && + (d[{1'b0,1'b0,s[0]}]==d[{1'b1,1'b0,s[0]}]) && (d[{1'b0,1'b0,s[0]}]==d[{1'b1,1'b1,s[0]}])) + lut6_mux8 = d[{1'b0,1'b0,s[0]}]; + else if (((s[1] ==1) || (s[1] ==0)) && (d[{1'b0,s[1],1'b0}]==d[{1'b0,s[1],1'b1}]) && + (d[{1'b0,s[1],1'b0}]==d[{1'b1,s[1],1'b0}]) && (d[{1'b0,s[1],1'b0}]==d[{1'b1,s[1],1'b1}])) + lut6_mux8 = d[{1'b0,s[1],1'b0}]; + else if (((s[2] ==1) || (s[2] ==0)) && (d[{s[2],1'b0,1'b0}]==d[{s[2],1'b0,1'b1}]) && + (d[{s[2],1'b0,1'b0}]==d[{s[2],1'b1,1'b0}]) && (d[{s[2],1'b0,1'b0}]==d[{s[2],1'b1,1'b1}])) + lut6_mux8 = d[{s[2],1'b0,1'b0}]; + else + lut6_mux8 = 1'bx; + end + endfunction + +endmodule diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/LUT6_L.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/LUT6_L.v new file mode 100644 index 0000000..3a8ab52 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/LUT6_L.v @@ -0,0 +1,91 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/rainier/LUT6_L.v,v 1.3 2007/06/01 00:22:57 yanx Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / 6-input Look-Up-Table with Local Output +// /___/ /\ Filename : LUT6_L.v +// \ \ / \ Timestamp : Thu Mar 25 16:42:54 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 02/04/05 - Replace premitive with function; Remove buf. +// 05/30/07 - Change timescale to 1 ps / 1ps. +// End Revision + +`timescale 1 ps / 1 ps + + +module LUT6_L (LO, I0, I1, I2, I3, I4, I5); + + parameter INIT = 64'h0000000000000000; + + input I0, I1, I2, I3, I4, I5; + + output LO; + + reg LO; + reg tmp; + + always @( I5 or I4 or I3 or I2 or I1 or I0 ) begin + + tmp = I0 ^ I1 ^ I2 ^ I3 ^ I4 ^ I5; + + if ( tmp == 0 || tmp == 1) + + LO = INIT[{I5, I4, I3, I2, I1, I0}]; + + else + + LO = lut6_mux8 ( {lut6_mux8 ( INIT[63:56], {I2, I1, I0}), + lut6_mux8 ( INIT[55:48], {I2, I1, I0}), + lut6_mux8 ( INIT[47:40], {I2, I1, I0}), + lut6_mux8 ( INIT[39:32], {I2, I1, I0}), + lut6_mux8 ( INIT[31:24], {I2, I1, I0}), + lut6_mux8 ( INIT[23:16], {I2, I1, I0}), + lut6_mux8 ( INIT[15:8], {I2, I1, I0}), + lut6_mux8 ( INIT[7:0], {I2, I1, I0}) }, {I5, I4, I3}); + end + + function lut6_mux8; + input [7:0] d; + input [2:0] s; + + begin + + if ((s[2]^s[1]^s[0] ==1) || (s[2]^s[1]^s[0] ==0)) + + lut6_mux8 = d[s]; + + else + if ( ~(|d)) + lut6_mux8 = 1'b0; + else if ((&d)) + lut6_mux8 = 1'b1; + else if (((s[1]^s[0] ==1'b1) || (s[1]^s[0] ==1'b0)) && (d[{1'b0,s[1:0]}]==d[{1'b1,s[1:0]}])) + lut6_mux8 = d[{1'b0,s[1:0]}]; + else if (((s[2]^s[0] ==1) || (s[2]^s[0] ==0)) && (d[{s[2],1'b0,s[0]}]==d[{s[2],1'b1,s[0]}])) + lut6_mux8 = d[{s[2],1'b0,s[0]}]; + else if (((s[2]^s[1] ==1) || (s[2]^s[1] ==0)) && (d[{s[2],s[1],1'b0}]==d[{s[2],s[1],1'b1}])) + lut6_mux8 = d[{s[2],s[1],1'b0}]; + else if (((s[0] ==1) || (s[0] ==0)) && (d[{1'b0,1'b0,s[0]}]==d[{1'b0,1'b1,s[0]}]) && + (d[{1'b0,1'b0,s[0]}]==d[{1'b1,1'b0,s[0]}]) && (d[{1'b0,1'b0,s[0]}]==d[{1'b1,1'b1,s[0]}])) + lut6_mux8 = d[{1'b0,1'b0,s[0]}]; + else if (((s[1] ==1) || (s[1] ==0)) && (d[{1'b0,s[1],1'b0}]==d[{1'b0,s[1],1'b1}]) && + (d[{1'b0,s[1],1'b0}]==d[{1'b1,s[1],1'b0}]) && (d[{1'b0,s[1],1'b0}]==d[{1'b1,s[1],1'b1}])) + lut6_mux8 = d[{1'b0,s[1],1'b0}]; + else if (((s[2] ==1) || (s[2] ==0)) && (d[{s[2],1'b0,1'b0}]==d[{s[2],1'b0,1'b1}]) && + (d[{s[2],1'b0,1'b0}]==d[{s[2],1'b1,1'b0}]) && (d[{s[2],1'b0,1'b0}]==d[{s[2],1'b1,1'b1}])) + lut6_mux8 = d[{s[2],1'b0,1'b0}]; + else + lut6_mux8 = 1'bx; + end + endfunction + +endmodule diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/MCB.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/MCB.v new file mode 100644 index 0000000..e58646f --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/MCB.v @@ -0,0 +1,1977 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/stan/MCB.v,v 1.12.10.1 2010/05/27 17:36:50 vandanad Exp $ +/////////////////////////////////////////////////////// +// Copyright (c) 2008 Xilinx Inc. +// All Right Reserved. +/////////////////////////////////////////////////////// +// +// ____ ___ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : +// / / +// /__/ /\ Filename : MCB.v +// \ \ / \ +// \__\/\__ \ +// +// Generated by : /home/chen/xfoundry/HEAD/env/Databases/CAEInterfaces/LibraryWriters/bin/write_verilog.pl +// Revision: 1.0 +// 1016 - Added memory type based parameter checks and set uiclk-ioidrpclk path delay to 0. +// 520730 - Remove UICLK-> IOIDRPTRAIN path from specify block. +// 532287 - Change default value of parameter CAL_CALIBRATION_MODE. +// 545576 - MEM_MDDR_ODS attribute update. +// 561882 - MCB yml update. +/////////////////////////////////////////////////////// + +`timescale 1 ps / 1 ps + +module MCB ( + ADDR, + BA, + CAS, + CKE, + DQIOWEN0, + DQON, + DQOP, + DQSIOWEN90N, + DQSIOWEN90P, + IOIDRPADD, + IOIDRPADDR, + IOIDRPBROADCAST, + IOIDRPCLK, + IOIDRPCS, + IOIDRPSDO, + IOIDRPTRAIN, + IOIDRPUPDATE, + LDMN, + LDMP, + ODT, + P0CMDEMPTY, + P0CMDFULL, + P0RDCOUNT, + P0RDDATA, + P0RDEMPTY, + P0RDERROR, + P0RDFULL, + P0RDOVERFLOW, + P0WRCOUNT, + P0WREMPTY, + P0WRERROR, + P0WRFULL, + P0WRUNDERRUN, + P1CMDEMPTY, + P1CMDFULL, + P1RDCOUNT, + P1RDDATA, + P1RDEMPTY, + P1RDERROR, + P1RDFULL, + P1RDOVERFLOW, + P1WRCOUNT, + P1WREMPTY, + P1WRERROR, + P1WRFULL, + P1WRUNDERRUN, + P2CMDEMPTY, + P2CMDFULL, + P2COUNT, + P2EMPTY, + P2ERROR, + P2FULL, + P2RDDATA, + P2RDOVERFLOW, + P2WRUNDERRUN, + P3CMDEMPTY, + P3CMDFULL, + P3COUNT, + P3EMPTY, + P3ERROR, + P3FULL, + P3RDDATA, + P3RDOVERFLOW, + P3WRUNDERRUN, + P4CMDEMPTY, + P4CMDFULL, + P4COUNT, + P4EMPTY, + P4ERROR, + P4FULL, + P4RDDATA, + P4RDOVERFLOW, + P4WRUNDERRUN, + P5CMDEMPTY, + P5CMDFULL, + P5COUNT, + P5EMPTY, + P5ERROR, + P5FULL, + P5RDDATA, + P5RDOVERFLOW, + P5WRUNDERRUN, + RAS, + RST, + SELFREFRESHMODE, + STATUS, + UDMN, + UDMP, + UOCALSTART, + UOCMDREADYIN, + UODATA, + UODATAVALID, + UODONECAL, + UOREFRSHFLAG, + UOSDO, + WE, + DQI, + DQSIOIN, + DQSIOIP, + IOIDRPSDI, + P0ARBEN, + P0CMDBA, + P0CMDBL, + P0CMDCA, + P0CMDCLK, + P0CMDEN, + P0CMDINSTR, + P0CMDRA, + P0RDCLK, + P0RDEN, + P0RWRMASK, + P0WRCLK, + P0WRDATA, + P0WREN, + P1ARBEN, + P1CMDBA, + P1CMDBL, + P1CMDCA, + P1CMDCLK, + P1CMDEN, + P1CMDINSTR, + P1CMDRA, + P1RDCLK, + P1RDEN, + P1RWRMASK, + P1WRCLK, + P1WRDATA, + P1WREN, + P2ARBEN, + P2CLK, + P2CMDBA, + P2CMDBL, + P2CMDCA, + P2CMDCLK, + P2CMDEN, + P2CMDINSTR, + P2CMDRA, + P2EN, + P2WRDATA, + P2WRMASK, + P3ARBEN, + P3CLK, + P3CMDBA, + P3CMDBL, + P3CMDCA, + P3CMDCLK, + P3CMDEN, + P3CMDINSTR, + P3CMDRA, + P3EN, + P3WRDATA, + P3WRMASK, + P4ARBEN, + P4CLK, + P4CMDBA, + P4CMDBL, + P4CMDCA, + P4CMDCLK, + P4CMDEN, + P4CMDINSTR, + P4CMDRA, + P4EN, + P4WRDATA, + P4WRMASK, + P5ARBEN, + P5CLK, + P5CMDBA, + P5CMDBL, + P5CMDCA, + P5CMDCLK, + P5CMDEN, + P5CMDINSTR, + P5CMDRA, + P5EN, + P5WRDATA, + P5WRMASK, + PLLCE, + PLLCLK, + PLLLOCK, + RECAL, + SELFREFRESHENTER, + SYSRST, + UDQSIOIN, + UDQSIOIP, + UIADD, + UIADDR, + UIBROADCAST, + UICLK, + UICMD, + UICMDEN, + UICMDIN, + UICS, + UIDONECAL, + UIDQCOUNT, + UIDQLOWERDEC, + UIDQLOWERINC, + UIDQUPPERDEC, + UIDQUPPERINC, + UIDRPUPDATE, + UILDQSDEC, + UILDQSINC, + UIREAD, + UISDI, + UIUDQSDEC, + UIUDQSINC +); + + parameter integer ARB_NUM_TIME_SLOTS = 12; + parameter [17:0] ARB_TIME_SLOT_0 = 18'b111111111111111111; + parameter [17:0] ARB_TIME_SLOT_1 = 18'b111111111111111111; + parameter [17:0] ARB_TIME_SLOT_10 = 18'b111111111111111111; + parameter [17:0] ARB_TIME_SLOT_11 = 18'b111111111111111111; + parameter [17:0] ARB_TIME_SLOT_2 = 18'b111111111111111111; + parameter [17:0] ARB_TIME_SLOT_3 = 18'b111111111111111111; + parameter [17:0] ARB_TIME_SLOT_4 = 18'b111111111111111111; + parameter [17:0] ARB_TIME_SLOT_5 = 18'b111111111111111111; + parameter [17:0] ARB_TIME_SLOT_6 = 18'b111111111111111111; + parameter [17:0] ARB_TIME_SLOT_7 = 18'b111111111111111111; + parameter [17:0] ARB_TIME_SLOT_8 = 18'b111111111111111111; + parameter [17:0] ARB_TIME_SLOT_9 = 18'b111111111111111111; + parameter [2:0] CAL_BA = 3'h0; + parameter CAL_BYPASS = "YES"; + parameter [11:0] CAL_CA = 12'h000; + parameter CAL_CALIBRATION_MODE = "NOCALIBRATION"; + parameter integer CAL_CLK_DIV = 1; + parameter CAL_DELAY = "QUARTER"; + parameter [14:0] CAL_RA = 15'h0000; + parameter MEM_ADDR_ORDER = "BANK_ROW_COLUMN"; + parameter integer MEM_BA_SIZE = 3; + parameter integer MEM_BURST_LEN = 8; + parameter integer MEM_CAS_LATENCY = 4; + parameter integer MEM_CA_SIZE = 11; + parameter MEM_DDR1_2_ODS = "FULL"; + parameter MEM_DDR2_3_HIGH_TEMP_SR = "NORMAL"; + parameter MEM_DDR2_3_PA_SR = "FULL"; + parameter integer MEM_DDR2_ADD_LATENCY = 0; + parameter MEM_DDR2_DIFF_DQS_EN = "YES"; + parameter MEM_DDR2_RTT = "50OHMS"; + parameter integer MEM_DDR2_WRT_RECOVERY = 4; + parameter MEM_DDR3_ADD_LATENCY = "OFF"; + parameter MEM_DDR3_AUTO_SR = "ENABLED"; + parameter integer MEM_DDR3_CAS_LATENCY = 7; + parameter integer MEM_DDR3_CAS_WR_LATENCY = 5; + parameter MEM_DDR3_DYN_WRT_ODT = "OFF"; + parameter MEM_DDR3_ODS = "DIV7"; + parameter MEM_DDR3_RTT = "DIV2"; + parameter integer MEM_DDR3_WRT_RECOVERY = 7; + parameter MEM_MDDR_ODS = "FULL"; + parameter MEM_MOBILE_PA_SR = "FULL"; + parameter integer MEM_MOBILE_TC_SR = 0; + parameter integer MEM_RAS_VAL = 0; + parameter integer MEM_RA_SIZE = 13; + parameter integer MEM_RCD_VAL = 1; + parameter integer MEM_REFI_VAL = 0; + parameter integer MEM_RFC_VAL = 0; + parameter integer MEM_RP_VAL = 0; + parameter integer MEM_RTP_VAL = 0; + parameter MEM_TYPE = "DDR3"; + parameter integer MEM_WIDTH = 4; + parameter integer MEM_WR_VAL = 0; + parameter integer MEM_WTR_VAL = 3; + parameter PORT_CONFIG = "B32_B32_B32_B32"; + + localparam in_delay = 0; + localparam out_delay = 0; + localparam INCLK_DELAY = 0; + localparam OUTCLK_DELAY = 0; + + output CAS; + output CKE; + output DQIOWEN0; + output DQSIOWEN90N; + output DQSIOWEN90P; + output IOIDRPADD; + output IOIDRPBROADCAST; + output IOIDRPCLK; + output IOIDRPCS; + output IOIDRPSDO; + output IOIDRPTRAIN; + output IOIDRPUPDATE; + output LDMN; + output LDMP; + output ODT; + output P0CMDEMPTY; + output P0CMDFULL; + output P0RDEMPTY; + output P0RDERROR; + output P0RDFULL; + output P0RDOVERFLOW; + output P0WREMPTY; + output P0WRERROR; + output P0WRFULL; + output P0WRUNDERRUN; + output P1CMDEMPTY; + output P1CMDFULL; + output P1RDEMPTY; + output P1RDERROR; + output P1RDFULL; + output P1RDOVERFLOW; + output P1WREMPTY; + output P1WRERROR; + output P1WRFULL; + output P1WRUNDERRUN; + output P2CMDEMPTY; + output P2CMDFULL; + output P2EMPTY; + output P2ERROR; + output P2FULL; + output P2RDOVERFLOW; + output P2WRUNDERRUN; + output P3CMDEMPTY; + output P3CMDFULL; + output P3EMPTY; + output P3ERROR; + output P3FULL; + output P3RDOVERFLOW; + output P3WRUNDERRUN; + output P4CMDEMPTY; + output P4CMDFULL; + output P4EMPTY; + output P4ERROR; + output P4FULL; + output P4RDOVERFLOW; + output P4WRUNDERRUN; + output P5CMDEMPTY; + output P5CMDFULL; + output P5EMPTY; + output P5ERROR; + output P5FULL; + output P5RDOVERFLOW; + output P5WRUNDERRUN; + output RAS; + output RST; + output SELFREFRESHMODE; + output UDMN; + output UDMP; + output UOCALSTART; + output UOCMDREADYIN; + output UODATAVALID; + output UODONECAL; + output UOREFRSHFLAG; + output UOSDO; + output WE; + output [14:0] ADDR; + output [15:0] DQON; + output [15:0] DQOP; + output [2:0] BA; + output [31:0] P0RDDATA; + output [31:0] P1RDDATA; + output [31:0] P2RDDATA; + output [31:0] P3RDDATA; + output [31:0] P4RDDATA; + output [31:0] P5RDDATA; + output [31:0] STATUS; + output [4:0] IOIDRPADDR; + output [6:0] P0RDCOUNT; + output [6:0] P0WRCOUNT; + output [6:0] P1RDCOUNT; + output [6:0] P1WRCOUNT; + output [6:0] P2COUNT; + output [6:0] P3COUNT; + output [6:0] P4COUNT; + output [6:0] P5COUNT; + output [7:0] UODATA; + + input DQSIOIN; + input DQSIOIP; + input IOIDRPSDI; + input P0ARBEN; + input P0CMDCLK; + input P0CMDEN; + input P0RDCLK; + input P0RDEN; + input P0WRCLK; + input P0WREN; + input P1ARBEN; + input P1CMDCLK; + input P1CMDEN; + input P1RDCLK; + input P1RDEN; + input P1WRCLK; + input P1WREN; + input P2ARBEN; + input P2CLK; + input P2CMDCLK; + input P2CMDEN; + input P2EN; + input P3ARBEN; + input P3CLK; + input P3CMDCLK; + input P3CMDEN; + input P3EN; + input P4ARBEN; + input P4CLK; + input P4CMDCLK; + input P4CMDEN; + input P4EN; + input P5ARBEN; + input P5CLK; + input P5CMDCLK; + input P5CMDEN; + input P5EN; + input PLLLOCK; + input RECAL; + input SELFREFRESHENTER; + input SYSRST; + input UDQSIOIN; + input UDQSIOIP; + input UIADD; + input UIBROADCAST; + input UICLK; + input UICMD; + input UICMDEN; + input UICMDIN; + input UICS; + input UIDONECAL; + input UIDQLOWERDEC; + input UIDQLOWERINC; + input UIDQUPPERDEC; + input UIDQUPPERINC; + input UIDRPUPDATE; + input UILDQSDEC; + input UILDQSINC; + input UIREAD; + input UISDI; + input UIUDQSDEC; + input UIUDQSINC; + input [11:0] P0CMDCA; + input [11:0] P1CMDCA; + input [11:0] P2CMDCA; + input [11:0] P3CMDCA; + input [11:0] P4CMDCA; + input [11:0] P5CMDCA; + input [14:0] P0CMDRA; + input [14:0] P1CMDRA; + input [14:0] P2CMDRA; + input [14:0] P3CMDRA; + input [14:0] P4CMDRA; + input [14:0] P5CMDRA; + input [15:0] DQI; + input [1:0] PLLCE; + input [1:0] PLLCLK; + input [2:0] P0CMDBA; + input [2:0] P0CMDINSTR; + input [2:0] P1CMDBA; + input [2:0] P1CMDINSTR; + input [2:0] P2CMDBA; + input [2:0] P2CMDINSTR; + input [2:0] P3CMDBA; + input [2:0] P3CMDINSTR; + input [2:0] P4CMDBA; + input [2:0] P4CMDINSTR; + input [2:0] P5CMDBA; + input [2:0] P5CMDINSTR; + input [31:0] P0WRDATA; + input [31:0] P1WRDATA; + input [31:0] P2WRDATA; + input [31:0] P3WRDATA; + input [31:0] P4WRDATA; + input [31:0] P5WRDATA; + input [3:0] P0RWRMASK; + input [3:0] P1RWRMASK; + input [3:0] P2WRMASK; + input [3:0] P3WRMASK; + input [3:0] P4WRMASK; + input [3:0] P5WRMASK; + input [3:0] UIDQCOUNT; + input [4:0] UIADDR; + input [5:0] P0CMDBL; + input [5:0] P1CMDBL; + input [5:0] P2CMDBL; + input [5:0] P3CMDBL; + input [5:0] P4CMDBL; + input [5:0] P5CMDBL; + + reg ARB_NUM_TIME_SLOTS_BINARY; + reg CAL_BYPASS_BINARY; + reg CAL_CALIBRATION_MODE_BINARY; + reg MEM_ADDR_ORDER_BINARY; + reg MEM_BA_SIZE_BINARY; + reg MEM_BURST_LEN_BINARY; + reg MEM_DDR1_2_ODS_BINARY; + reg MEM_DDR2_3_HIGH_TEMP_SR_BINARY; + reg MEM_DDR2_DIFF_DQS_EN_BINARY; + reg MEM_DDR3_AUTO_SR_BINARY; + reg [2:0] PORT_CONFIG_BINARY; + reg [11:0] MEM_REFI_VAL_BINARY; + reg [17:0] ARB_TIME_SLOT_0_BINARY; + reg [17:0] ARB_TIME_SLOT_10_BINARY; + reg [17:0] ARB_TIME_SLOT_11_BINARY; + reg [17:0] ARB_TIME_SLOT_1_BINARY; + reg [17:0] ARB_TIME_SLOT_2_BINARY; + reg [17:0] ARB_TIME_SLOT_3_BINARY; + reg [17:0] ARB_TIME_SLOT_4_BINARY; + reg [17:0] ARB_TIME_SLOT_5_BINARY; + reg [17:0] ARB_TIME_SLOT_6_BINARY; + reg [17:0] ARB_TIME_SLOT_7_BINARY; + reg [17:0] ARB_TIME_SLOT_8_BINARY; + reg [17:0] ARB_TIME_SLOT_9_BINARY; + reg [1:0] CAL_DELAY_BINARY; + reg [1:0] MEM_CA_SIZE_BINARY; + reg [1:0] MEM_DDR2_RTT_BINARY; + reg [1:0] MEM_DDR3_ADD_LATENCY_BINARY; + reg [1:0] MEM_DDR3_DYN_WRT_ODT_BINARY; + reg [1:0] MEM_DDR3_ODS_BINARY; + reg [1:0] MEM_MOBILE_TC_SR_BINARY; + reg [1:0] MEM_RA_SIZE_BINARY; + reg [1:0] MEM_WIDTH_BINARY; + reg [2:0] CAL_CLK_DIV_BINARY; + reg [2:0] MEM_CAS_LATENCY_BINARY; + reg [2:0] MEM_DDR2_3_PA_SR_BINARY; + reg [2:0] MEM_DDR2_ADD_LATENCY_BINARY; + reg [2:0] MEM_DDR2_WRT_RECOVERY_BINARY; + reg [2:0] MEM_DDR3_CAS_WR_LATENCY_BINARY; + reg [2:0] MEM_DDR3_RTT_BINARY; + reg [2:0] MEM_DDR3_WRT_RECOVERY_BINARY; + reg [2:0] MEM_MDDR_ODS_BINARY; + reg [2:0] MEM_MOBILE_PA_SR_BINARY; + reg [2:0] MEM_RCD_VAL_BINARY; + reg [2:0] MEM_RTP_VAL_BINARY; + reg [2:0] MEM_TYPE_BINARY; + reg [2:0] MEM_WR_VAL_BINARY; + reg [2:0] MEM_WTR_VAL_BINARY; + reg [3:0] MEM_DDR3_CAS_LATENCY_BINARY; + reg [3:0] MEM_RP_VAL_BINARY; + reg [4:0] MEM_RAS_VAL_BINARY; + reg [7:0] MEM_RFC_VAL_BINARY; + + tri0 GSR = glbl.GSR; + + initial begin + case (ARB_NUM_TIME_SLOTS) + 12 : ARB_NUM_TIME_SLOTS_BINARY = 1'b1; + 10 : ARB_NUM_TIME_SLOTS_BINARY = 1'b0; + default : begin + $display("Attribute Syntax Error : The Attribute ARB_NUM_TIME_SLOTS on MCB instance %m is set to %d. Legal values for this attribute are 12 or 10.", ARB_NUM_TIME_SLOTS); + $finish; + end + endcase + + case (CAL_BYPASS) + "YES" : CAL_BYPASS_BINARY = 1'b1; + "NO" : CAL_BYPASS_BINARY = 1'b0; + default : begin + $display("Attribute Syntax Error : The Attribute CAL_BYPASS on MCB instance %m is set to %s. Legal values for this attribute are YES, or NO.", CAL_BYPASS); + $finish; + end + endcase + + case (CAL_CALIBRATION_MODE) + "CALIBRATION" : CAL_CALIBRATION_MODE_BINARY = 1'b0; + "NOCALIBRATION" : CAL_CALIBRATION_MODE_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute CAL_CALIBRATION_MODE on MCB instance %m is set to %s. Legal values for this attribute are CALIBRATION, or NOCALIBRATION.", CAL_CALIBRATION_MODE); + $finish; + end + endcase + + case (CAL_CLK_DIV) + 1 : CAL_CLK_DIV_BINARY = 3'b000; + 2 : CAL_CLK_DIV_BINARY = 3'b001; + 4 : CAL_CLK_DIV_BINARY = 3'b010; + 8 : CAL_CLK_DIV_BINARY = 3'b011; + default : begin + $display("Attribute Syntax Error : The Attribute CAL_CLK_DIV on MCB instance %m is set to %d. Legal values for this attribute are 1, 2, 4 or 8.", CAL_CLK_DIV); + $finish; + end + endcase + + case (CAL_DELAY) + "QUARTER" : CAL_DELAY_BINARY = 2'b00; + "FULL" : CAL_DELAY_BINARY = 2'b11; + "HALF" : CAL_DELAY_BINARY = 2'b01; + "THREEQUARTER" : CAL_DELAY_BINARY = 2'b10; + default : begin + $display("Attribute Syntax Error : The Attribute CAL_DELAY on MCB instance %m is set to %s. Legal values for this attribute are QUARTER, FULL, HALF, or THREEQUARTER.", CAL_DELAY); + $finish; + end + endcase + + case (MEM_ADDR_ORDER) + "BANK_ROW_COLUMN" : MEM_ADDR_ORDER_BINARY = 1'b0; + "ROW_BANK_COLUMN" : MEM_ADDR_ORDER_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute MEM_ADDR_ORDER on MCB instance %m is set to %s. Legal values for this attribute are BANK_ROW_COLUMN, or ROW_BANK_COLUMN.", MEM_ADDR_ORDER); + $finish; + end + endcase + + case (MEM_BA_SIZE) + 3 : MEM_BA_SIZE_BINARY = 1'b1; + 2 : MEM_BA_SIZE_BINARY = 1'b0; + default : begin + $display("Attribute Syntax Error : The Attribute MEM_BA_SIZE on MCB instance %m is set to %d. Legal values for this attribute are 2 to 3 .", MEM_BA_SIZE); + $finish; + end + endcase + + case (MEM_CA_SIZE) + 11 : MEM_CA_SIZE_BINARY = 2'b10; + 9 : MEM_CA_SIZE_BINARY = 2'b00; + 10 : MEM_CA_SIZE_BINARY = 2'b01; + 12 : MEM_CA_SIZE_BINARY = 2'b11; + default : begin + $display("Attribute Syntax Error : The Attribute MEM_CA_SIZE on MCB instance %m is set to %d. Legal values for this attribute are 9 to 12.", MEM_CA_SIZE); + $finish; + end + endcase + case (MEM_TYPE) + "DDR3" : MEM_TYPE_BINARY = 3'b000; + "DDR" : MEM_TYPE_BINARY = 3'b010; + "DDR2" : MEM_TYPE_BINARY = 3'b001; + "MDDR" : MEM_TYPE_BINARY = 3'b011; + default : begin + $display("Attribute Syntax Error : The Attribute MEM_TYPE on MCB instance %m is set to %s. Legal values for this attribute are DDR3, DDR, DDR2, or MDDR.", MEM_TYPE); + $finish; + end + endcase + + case (MEM_WIDTH) + 4 : MEM_WIDTH_BINARY = 2'b01; + 8 : MEM_WIDTH_BINARY = 2'b10; + 16 : MEM_WIDTH_BINARY = 2'b11; + default : begin + $display("Attribute Syntax Error : The Attribute MEM_WIDTH on MCB instance %m is set to %d. Legal values for this attribute are 4, 8 or 16.", MEM_WIDTH); + $finish; + end + endcase + + case(MEM_BURST_LEN) + 4 : if(MEM_TYPE == "DDR3") begin + $display("Attribute Syntax Error : The Attribute MEM_BURST_LEN on MEMC instance %m is set to %s. This parameter cannot be set to 4 for MEM_TYPE DDR3.", MEM_BURST_LEN); + $finish; + end + else + MEM_BURST_LEN_BINARY = 3'b010; + 8 : MEM_BURST_LEN_BINARY = 3'b011; + default : begin + $display("Attribute Syntax Error : The Attribute MEM_BURST_LEN on MEMC instance %m is set to %s. Legal values for this attribute are 2, 4 and 8.", MEM_BURST_LEN); + $finish; + end + endcase + + if((MEM_TYPE == "DDR2") || (MEM_TYPE == "DDR")) begin + case (MEM_DDR1_2_ODS) + "FULL" : MEM_DDR1_2_ODS_BINARY = 1'b0; + "REDUCED" : MEM_DDR1_2_ODS_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute MEM_DDR1_2_ODS on MCB instance %m is set to %s. Legal values for this attribute are FULL, or REDUCED.", MEM_DDR1_2_ODS); + $finish; + end + endcase + end + + if((MEM_TYPE == "DDR2") || (MEM_TYPE == "DDR3")) begin + case (MEM_DDR2_3_HIGH_TEMP_SR) + "NORMAL" : MEM_DDR2_3_HIGH_TEMP_SR_BINARY = 1'b0; + "EXTENDED" : MEM_DDR2_3_HIGH_TEMP_SR_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute MEM_DDR2_3_HIGH_TEMP_SR on MCB instance %m is set to %s. Legal values for this attribute are NORMAL, or EXTENDED.", MEM_DDR2_3_HIGH_TEMP_SR); + $finish; + end + endcase + + case (MEM_DDR2_3_PA_SR) + "FULL" : MEM_DDR2_3_PA_SR_BINARY = 3'b000; + "EIGHTH1" : MEM_DDR2_3_PA_SR_BINARY = 3'b011; + "EIGHTH2" : MEM_DDR2_3_PA_SR_BINARY = 3'b111; + "HALF1" : MEM_DDR2_3_PA_SR_BINARY = 3'b001; + "HALF2" : MEM_DDR2_3_PA_SR_BINARY = 3'b101; + "QUARTER1" : MEM_DDR2_3_PA_SR_BINARY = 3'b010; + "QUARTER2" : MEM_DDR2_3_PA_SR_BINARY = 3'b110; + "THREEQUARTER" : MEM_DDR2_3_PA_SR_BINARY = 3'b100; + default : begin + $display("Attribute Syntax Error : The Attribute MEM_DDR2_3_PA_SR on MCB instance %m is set to %s. Legal values for this attribute are FULL, EIGHTH1, EIGHTH2, HALF1, HALF2, QUARTER1, QUARTER2, or THREEQUARTER.", MEM_DDR2_3_PA_SR); + $finish; + end + endcase + end + + if (MEM_TYPE == "DDR2") begin + case (MEM_DDR2_DIFF_DQS_EN) + "YES" : MEM_DDR2_DIFF_DQS_EN_BINARY = 1'b0; + "NO" : MEM_DDR2_DIFF_DQS_EN_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute MEM_DDR2_DIFF_DQS_EN on MCB instance %m is set to %s. Legal values for this attribute are YES, or NO.", MEM_DDR2_DIFF_DQS_EN); + $finish; + end + endcase + + case (MEM_DDR2_RTT) + "50OHMS" : MEM_DDR2_RTT_BINARY = 2'b11; + "75OHMS" : MEM_DDR2_RTT_BINARY = 2'b01; + "150OHMS" : MEM_DDR2_RTT_BINARY = 2'b10; + "OFF" : MEM_DDR2_RTT_BINARY = 2'b00; + default : begin + $display("Attribute Syntax Error : The Attribute MEM_DDR2_RTT on MCB instance %m is set to %s. Legal values for this attribute are 50OHMS, 75OHMS, 150OHMS, or OFF.", MEM_DDR2_RTT); + $finish; + end + endcase + + case (MEM_DDR2_WRT_RECOVERY) + 4 : MEM_DDR2_WRT_RECOVERY_BINARY = 3'b011; + 2 : MEM_DDR2_WRT_RECOVERY_BINARY = 3'b001; + 3 : MEM_DDR2_WRT_RECOVERY_BINARY = 3'b010; + 5 : MEM_DDR2_WRT_RECOVERY_BINARY = 3'b100; + 6 : MEM_DDR2_WRT_RECOVERY_BINARY = 3'b101; + default : begin + $display("Attribute Syntax Error : The Attribute MEM_DDR2_WRT_RECOVERY on MCB instance %m is set to %d. Legal values for this attribute are 2 to 6.", MEM_DDR2_WRT_RECOVERY); + $finish; + end + endcase + if ((MEM_DDR2_ADD_LATENCY >= 0) && (MEM_DDR2_ADD_LATENCY <= 5)) + MEM_DDR2_ADD_LATENCY_BINARY = MEM_DDR2_ADD_LATENCY; + else begin + $display("Attribute Syntax Error : The Attribute MEM_DDR2_ADD_LATENCY on MCB instance %m is set to %d. Legal values for this attribute are 0 to 5.", MEM_DDR2_ADD_LATENCY); + $finish; + end + end + + if (MEM_TYPE == "DDR3") begin + case (MEM_DDR3_ADD_LATENCY) + "OFF" : MEM_DDR3_ADD_LATENCY_BINARY = 2'b00; + "CL1" : MEM_DDR3_ADD_LATENCY_BINARY = 2'b01; + "CL2" : MEM_DDR3_ADD_LATENCY_BINARY = 2'b10; + default : begin + $display("Attribute Syntax Error : The Attribute MEM_DDR3_ADD_LATENCY on MCB instance %m is set to %s. Legal values for this attribute are OFF, CL1, or CL2.", MEM_DDR3_ADD_LATENCY); + $finish; + end + endcase + + case (MEM_DDR3_AUTO_SR) + "ENABLED" : MEM_DDR3_AUTO_SR_BINARY = 1'b1; + "MANUAL" : MEM_DDR3_AUTO_SR_BINARY = 1'b0; + default : begin + $display("Attribute Syntax Error : The Attribute MEM_DDR3_AUTO_SR on MCB instance %m is set to %s. Legal values for this attribute are ENABLED, or MANUAL.", MEM_DDR3_AUTO_SR); + $finish; + end + endcase + + case (MEM_DDR3_CAS_LATENCY) + 7 : MEM_DDR3_CAS_LATENCY_BINARY = 4'b0110; + 5 : MEM_DDR3_CAS_LATENCY_BINARY = 4'b0010; + 6 : MEM_DDR3_CAS_LATENCY_BINARY = 4'b0100; + 8 : MEM_DDR3_CAS_LATENCY_BINARY = 4'b1000; + 9 : MEM_DDR3_CAS_LATENCY_BINARY = 4'b1010; + 10 : MEM_DDR3_CAS_LATENCY_BINARY = 4'b1100; + default : begin + $display("Attribute Syntax Error : The Attribute MEM_DDR3_CAS_LATENCY on MCB instance %m is set to %d. Legal values for this attribute are 5 to 10.", MEM_DDR3_CAS_LATENCY); + $finish; + end + endcase + + case (MEM_DDR3_CAS_WR_LATENCY) + 5 : MEM_DDR3_CAS_WR_LATENCY_BINARY = 3'b000; + 6 : MEM_DDR3_CAS_WR_LATENCY_BINARY = 3'b001; + 7 : MEM_DDR3_CAS_WR_LATENCY_BINARY = 3'b010; + 8 : MEM_DDR3_CAS_WR_LATENCY_BINARY = 3'b011; + default : begin + $display("Attribute Syntax Error : The Attribute MEM_DDR3_CAS_WR_LATENCY on MCB instance %m is set to %d. Legal values for this attribute are 5 to 8.", MEM_DDR3_CAS_WR_LATENCY); + $finish; + end + endcase + + case (MEM_DDR3_DYN_WRT_ODT) + "OFF" : MEM_DDR3_DYN_WRT_ODT_BINARY = 2'b00; + "DIV2" : MEM_DDR3_DYN_WRT_ODT_BINARY = 2'b01; + "DIV4" : MEM_DDR3_DYN_WRT_ODT_BINARY = 2'b10; + default : begin + $display("Attribute Syntax Error : The Attribute MEM_DDR3_DYN_WRT_ODT on MCB instance %m is set to %s. Legal values for this attribute are OFF, DIV2, or DIV4.", MEM_DDR3_DYN_WRT_ODT); + $finish; + end + endcase + + case (MEM_DDR3_ODS) + "DIV7" : MEM_DDR3_ODS_BINARY = 2'b01; + "DIV6" : MEM_DDR3_ODS_BINARY = 2'b00; + default : begin + $display("Attribute Syntax Error : The Attribute MEM_DDR3_ODS on MCB instance %m is set to %s. Legal values for this attribute are DIV7, or DIV6.", MEM_DDR3_ODS); + $finish; + end + endcase + + case (MEM_DDR3_RTT) + "DIV2" : MEM_DDR3_RTT_BINARY = 3'b010; + "DIV4" : MEM_DDR3_RTT_BINARY = 3'b001; + "DIV6" : MEM_DDR3_RTT_BINARY = 3'b011; + "DIV8" : MEM_DDR3_RTT_BINARY = 3'b100; + "DIV12" : MEM_DDR3_RTT_BINARY = 3'b101; + "OFF" : MEM_DDR3_RTT_BINARY = 3'b000; + default : begin + $display("Attribute Syntax Error : The Attribute MEM_DDR3_RTT on MCB instance %m is set to %s. Legal values for this attribute are DIV2, DIV4, DIV6, DIV8, DIV12, or OFF.", MEM_DDR3_RTT); + $finish; + end + endcase + + case (MEM_DDR3_WRT_RECOVERY) + 7 : MEM_DDR3_WRT_RECOVERY_BINARY = 3'b011; + 5 : MEM_DDR3_WRT_RECOVERY_BINARY = 3'b001; + 6 : MEM_DDR3_WRT_RECOVERY_BINARY = 3'b010; + 8 : MEM_DDR3_WRT_RECOVERY_BINARY = 3'b100; + 10 : MEM_DDR3_WRT_RECOVERY_BINARY = 3'b101; + 12 : MEM_DDR3_WRT_RECOVERY_BINARY = 3'b110; + default : begin + $display("Attribute Syntax Error : The Attribute MEM_DDR3_WRT_RECOVERY on MCB instance %m is set to %d. Legal values for this attribute are 5, 6, 7, 8, 10 or 12.", MEM_DDR3_WRT_RECOVERY); + $finish; + end + endcase + end + + if(MEM_TYPE == "MDDR") begin + case (MEM_MDDR_ODS) + "FULL" : MEM_MDDR_ODS_BINARY = 3'b000; + "HALF" : MEM_MDDR_ODS_BINARY = 3'b001; + "QUARTER" : MEM_MDDR_ODS_BINARY = 3'b010; + "THREEQUARTERS" : MEM_MDDR_ODS_BINARY = 3'b100; + default : begin + $display("Attribute Syntax Error : The Attribute MEM_MDDR_ODS on MCB instance %m is set to %s. Legal values for this attribute are FULL, HALF, QUARTER, or THREEQUARTERS.", MEM_MDDR_ODS); + $finish; + end + endcase + + case (MEM_MOBILE_PA_SR) + "FULL" : MEM_MOBILE_PA_SR_BINARY = 3'b000; + "HALF" : MEM_MOBILE_PA_SR_BINARY = 3'b001; + default : begin + $display("Attribute Syntax Error : The Attribute MEM_MOBILE_PA_SR on MCB instance %m is set to %s. Legal values for this attribute are FULL, or HALF.", MEM_MOBILE_PA_SR); + $finish; + end + endcase + if ((MEM_MOBILE_TC_SR >= 0) && (MEM_MOBILE_TC_SR <= 3)) + MEM_MOBILE_TC_SR_BINARY = MEM_MOBILE_TC_SR; + else begin + $display("Attribute Syntax Error : The Attribute MEM_MOBILE_TC_SR on MCB instance %m is set to %d. Legal values for this attribute are 0 to 3.", MEM_MOBILE_TC_SR); + $finish; + end + end + + case (MEM_RA_SIZE) + 13 : MEM_RA_SIZE_BINARY = 2'b01; + 12 : MEM_RA_SIZE_BINARY = 2'b00; + 14 : MEM_RA_SIZE_BINARY = 2'b10; + 15 : MEM_RA_SIZE_BINARY = 2'b11; + default : begin + $display("Attribute Syntax Error : The Attribute MEM_RA_SIZE on MCB instance %m is set to %d. Legal values for this attribute are 12 to 15.", MEM_RA_SIZE); + $finish; + end + endcase + + if ((MEM_CAS_LATENCY >= 1) && (MEM_CAS_LATENCY <= 6)) + MEM_CAS_LATENCY_BINARY = MEM_CAS_LATENCY; + else begin + $display("Attribute Syntax Error : The Attribute MEM_CAS_LATENCY on MCB instance %m is set to %d. Legal values for this attribute are 1 to 6.", MEM_CAS_LATENCY); + $finish; + end + + if ((MEM_RAS_VAL >= 0) && (MEM_RAS_VAL <= 31)) + MEM_RAS_VAL_BINARY = MEM_RAS_VAL; + else begin + $display("Attribute Syntax Error : The Attribute MEM_RAS_VAL on MCB instance %m is set to %d. Legal values for this attribute are 0 to 31.", MEM_RAS_VAL); + $finish; + end + + if ((MEM_RCD_VAL >= 0) && (MEM_RCD_VAL <= 7)) + MEM_RCD_VAL_BINARY = MEM_RCD_VAL; + else begin + $display("Attribute Syntax Error : The Attribute MEM_RCD_VAL on MCB instance %m is set to %d. Legal values for this attribute are 0 to 7.", MEM_RCD_VAL); + $finish; + end + + if ((MEM_REFI_VAL >= 0) && (MEM_REFI_VAL <= 4095)) + MEM_REFI_VAL_BINARY = MEM_REFI_VAL; + else begin + $display("Attribute Syntax Error : The Attribute MEM_REFI_VAL on MCB instance %m is set to %d. Legal values for this attribute are 0 to 4095.", MEM_REFI_VAL); + $finish; + end + + if ((MEM_RFC_VAL >= 0) && (MEM_RFC_VAL <= 255)) + MEM_RFC_VAL_BINARY = MEM_RFC_VAL; + else begin + $display("Attribute Syntax Error : The Attribute MEM_RFC_VAL on MCB instance %m is set to %d. Legal values for this attribute are 0 to 255.", MEM_RFC_VAL); + $finish; + end + + if ((MEM_RP_VAL >= 0) && (MEM_RP_VAL <= 15)) + MEM_RP_VAL_BINARY = MEM_RP_VAL; + else begin + $display("Attribute Syntax Error : The Attribute MEM_RP_VAL on MCB instance %m is set to %d. Legal values for this attribute are 0 to 15.", MEM_RP_VAL); + $finish; + end + + if ((MEM_RTP_VAL >= 0) && (MEM_RTP_VAL <= 7)) + MEM_RTP_VAL_BINARY = MEM_RTP_VAL; + else begin + $display("Attribute Syntax Error : The Attribute MEM_RTP_VAL on MCB instance %m is set to %d. Legal values for this attribute are 0 to 7.", MEM_RTP_VAL); + $finish; + end + + if ((MEM_WR_VAL >= 0) && (MEM_WR_VAL <= 7)) + MEM_WR_VAL_BINARY = MEM_WR_VAL; + else begin + $display("Attribute Syntax Error : The Attribute MEM_WR_VAL on MCB instance %m is set to %d. Legal values for this attribute are 0 to 7.", MEM_WR_VAL); + $finish; + end + + if ((MEM_WTR_VAL >= 0) && (MEM_WTR_VAL <= 7)) + MEM_WTR_VAL_BINARY = MEM_WTR_VAL; + else begin + $display("Attribute Syntax Error : The Attribute MEM_WTR_VAL on MCB instance %m is set to %d. Legal values for this attribute are 0 to 7.", MEM_WTR_VAL); + $finish; + end + case (PORT_CONFIG) + "B32_B32_B32_B32" : PORT_CONFIG_BINARY = 3'b001; + "B32_B32_R32_R32_R32_R32" : PORT_CONFIG_BINARY = 3'b000; + "B32_B32_R32_R32_R32_W32" : PORT_CONFIG_BINARY = 3'b000; + "B32_B32_R32_R32_W32_R32" : PORT_CONFIG_BINARY = 3'b000; + "B32_B32_R32_R32_W32_W32" : PORT_CONFIG_BINARY = 3'b000; + "B32_B32_R32_W32_R32_R32" : PORT_CONFIG_BINARY = 3'b000; + "B32_B32_R32_W32_R32_W32" : PORT_CONFIG_BINARY = 3'b000; + "B32_B32_R32_W32_W32_R32" : PORT_CONFIG_BINARY = 3'b000; + "B32_B32_R32_W32_W32_W32" : PORT_CONFIG_BINARY = 3'b000; + "B32_B32_W32_R32_R32_R32" : PORT_CONFIG_BINARY = 3'b000; + "B32_B32_W32_R32_R32_W32" : PORT_CONFIG_BINARY = 3'b000; + "B32_B32_W32_R32_W32_R32" : PORT_CONFIG_BINARY = 3'b000; + "B32_B32_W32_R32_W32_W32" : PORT_CONFIG_BINARY = 3'b000; + "B32_B32_W32_W32_R32_R32" : PORT_CONFIG_BINARY = 3'b000; + "B32_B32_W32_W32_R32_W32" : PORT_CONFIG_BINARY = 3'b000; + "B32_B32_W32_W32_W32_R32" : PORT_CONFIG_BINARY = 3'b000; + "B32_B32_W32_W32_W32_W32" : PORT_CONFIG_BINARY = 3'b000; + "B64_B32_B32" : PORT_CONFIG_BINARY = 3'b010; + "B64_B64" : PORT_CONFIG_BINARY = 3'b011; + "B128" : PORT_CONFIG_BINARY = 3'b100; + default : begin + $display("Attribute Syntax Error : The Attribute PORT_CONFIG on MCB instance %m is set to %s. Legal values for this attribute are B32_B32_B32_B32, B32_B32_R32_R32_R32_R32, B32_B32_R32_R32_R32_W32, B32_B32_R32_R32_W32_R32, B32_B32_R32_R32_W32_W32, B32_B32_R32_W32_R32_R32, B32_B32_R32_W32_R32_W32, B32_B32_R32_W32_W32_R32, B32_B32_R32_W32_W32_W32, B32_B32_W32_R32_R32_R32, B32_B32_W32_R32_R32_W32, B32_B32_W32_R32_W32_R32, B32_B32_W32_R32_W32_W32, B32_B32_W32_W32_R32_R32, B32_B32_W32_W32_R32_W32, B32_B32_W32_W32_W32_R32, B32_B32_W32_W32_W32_W32, B64_B32_B32, B64_B64, or B128.", PORT_CONFIG); + $finish; + end + endcase + end + + wire [14:0] delay_ADDR; + wire [15:0] delay_DQON; + wire [15:0] delay_DQOP; + wire [2:0] delay_BA; + wire [31:0] delay_P0RDDATA; + wire [31:0] delay_P1RDDATA; + wire [31:0] delay_P2RDDATA; + wire [31:0] delay_P3RDDATA; + wire [31:0] delay_P4RDDATA; + wire [31:0] delay_P5RDDATA; + wire [31:0] delay_STATUS; + wire [4:0] delay_IOIDRPADDR; + wire [6:0] delay_P0RDCOUNT; + wire [6:0] delay_P0WRCOUNT; + wire [6:0] delay_P1RDCOUNT; + wire [6:0] delay_P1WRCOUNT; + wire [6:0] delay_P2COUNT; + wire [6:0] delay_P3COUNT; + wire [6:0] delay_P4COUNT; + wire [6:0] delay_P5COUNT; + wire [7:0] delay_UODATA; + wire delay_CAS; + wire delay_CKE; + wire delay_DQIOWEN0; + wire delay_DQSIOWEN90N; + wire delay_DQSIOWEN90P; + wire delay_IOIDRPADD; + wire delay_IOIDRPBROADCAST; + wire delay_IOIDRPCLK; + wire delay_IOIDRPCS; + wire delay_IOIDRPSDO; + wire delay_IOIDRPTRAIN; + wire delay_IOIDRPUPDATE; + wire delay_LDMN; + wire delay_LDMP; + wire delay_ODT; + wire delay_P0CMDEMPTY; + wire delay_P0CMDFULL; + wire delay_P0RDEMPTY; + wire delay_P0RDERROR; + wire delay_P0RDFULL; + wire delay_P0RDOVERFLOW; + wire delay_P0WREMPTY; + wire delay_P0WRERROR; + wire delay_P0WRFULL; + wire delay_P0WRUNDERRUN; + wire delay_P1CMDEMPTY; + wire delay_P1CMDFULL; + wire delay_P1RDEMPTY; + wire delay_P1RDERROR; + wire delay_P1RDFULL; + wire delay_P1RDOVERFLOW; + wire delay_P1WREMPTY; + wire delay_P1WRERROR; + wire delay_P1WRFULL; + wire delay_P1WRUNDERRUN; + wire delay_P2CMDEMPTY; + wire delay_P2CMDFULL; + wire delay_P2EMPTY; + wire delay_P2ERROR; + wire delay_P2FULL; + wire delay_P2RDOVERFLOW; + wire delay_P2WRUNDERRUN; + wire delay_P3CMDEMPTY; + wire delay_P3CMDFULL; + wire delay_P3EMPTY; + wire delay_P3ERROR; + wire delay_P3FULL; + wire delay_P3RDOVERFLOW; + wire delay_P3WRUNDERRUN; + wire delay_P4CMDEMPTY; + wire delay_P4CMDFULL; + wire delay_P4EMPTY; + wire delay_P4ERROR; + wire delay_P4FULL; + wire delay_P4RDOVERFLOW; + wire delay_P4WRUNDERRUN; + wire delay_P5CMDEMPTY; + wire delay_P5CMDFULL; + wire delay_P5EMPTY; + wire delay_P5ERROR; + wire delay_P5FULL; + wire delay_P5RDOVERFLOW; + wire delay_P5WRUNDERRUN; + wire delay_RAS; + wire delay_RST; + wire delay_SELFREFRESHMODE; + wire delay_UDMN; + wire delay_UDMP; + wire delay_UOCALSTART; + wire delay_UOCMDREADYIN; + wire delay_UODATAVALID; + wire delay_UODONECAL; + wire delay_UOREFRSHFLAG; + wire delay_UOSDO; + wire delay_WE; + + wire [11:0] delay_P0CMDCA; + wire [11:0] delay_P1CMDCA; + wire [11:0] delay_P2CMDCA; + wire [11:0] delay_P3CMDCA; + wire [11:0] delay_P4CMDCA; + wire [11:0] delay_P5CMDCA; + wire [14:0] delay_P0CMDRA; + wire [14:0] delay_P1CMDRA; + wire [14:0] delay_P2CMDRA; + wire [14:0] delay_P3CMDRA; + wire [14:0] delay_P4CMDRA; + wire [14:0] delay_P5CMDRA; + wire [15:0] delay_DQI; + wire [1:0] delay_PLLCE; + wire [1:0] delay_PLLCLK; + wire [2:0] delay_P0CMDBA; + wire [2:0] delay_P0CMDINSTR; + wire [2:0] delay_P1CMDBA; + wire [2:0] delay_P1CMDINSTR; + wire [2:0] delay_P2CMDBA; + wire [2:0] delay_P2CMDINSTR; + wire [2:0] delay_P3CMDBA; + wire [2:0] delay_P3CMDINSTR; + wire [2:0] delay_P4CMDBA; + wire [2:0] delay_P4CMDINSTR; + wire [2:0] delay_P5CMDBA; + wire [2:0] delay_P5CMDINSTR; + wire [31:0] delay_P0WRDATA; + wire [31:0] delay_P1WRDATA; + wire [31:0] delay_P2WRDATA; + wire [31:0] delay_P3WRDATA; + wire [31:0] delay_P4WRDATA; + wire [31:0] delay_P5WRDATA; + wire [3:0] delay_P0RWRMASK; + wire [3:0] delay_P1RWRMASK; + wire [3:0] delay_P2WRMASK; + wire [3:0] delay_P3WRMASK; + wire [3:0] delay_P4WRMASK; + wire [3:0] delay_P5WRMASK; + wire [3:0] delay_UIDQCOUNT; + wire [4:0] delay_UIADDR; + wire [5:0] delay_P0CMDBL; + wire [5:0] delay_P1CMDBL; + wire [5:0] delay_P2CMDBL; + wire [5:0] delay_P3CMDBL; + wire [5:0] delay_P4CMDBL; + wire [5:0] delay_P5CMDBL; + wire delay_DQSIOIN; + wire delay_DQSIOIP; + wire delay_IOIDRPSDI; + wire delay_P0ARBEN; + wire delay_P0CMDCLK; + wire delay_P0CMDEN; + wire delay_P0RDCLK; + wire delay_P0RDEN; + wire delay_P0WRCLK; + wire delay_P0WREN; + wire delay_P1ARBEN; + wire delay_P1CMDCLK; + wire delay_P1CMDEN; + wire delay_P1RDCLK; + wire delay_P1RDEN; + wire delay_P1WRCLK; + wire delay_P1WREN; + wire delay_P2ARBEN; + wire delay_P2CLK; + wire delay_P2CMDCLK; + wire delay_P2CMDEN; + wire delay_P2EN; + wire delay_P3ARBEN; + wire delay_P3CLK; + wire delay_P3CMDCLK; + wire delay_P3CMDEN; + wire delay_P3EN; + wire delay_P4ARBEN; + wire delay_P4CLK; + wire delay_P4CMDCLK; + wire delay_P4CMDEN; + wire delay_P4EN; + wire delay_P5ARBEN; + wire delay_P5CLK; + wire delay_P5CMDCLK; + wire delay_P5CMDEN; + wire delay_P5EN; + wire delay_PLLLOCK; + wire delay_RECAL; + wire delay_SELFREFRESHENTER; + wire delay_SYSRST; + wire delay_UDQSIOIN; + wire delay_UDQSIOIP; + wire delay_UIADD; + wire delay_UIBROADCAST; + wire delay_UICLK; + wire delay_UICMD; + wire delay_UICMDEN; + wire delay_UICMDIN; + wire delay_UICS; + wire delay_UIDONECAL; + wire delay_UIDQLOWERDEC; + wire delay_UIDQLOWERINC; + wire delay_UIDQUPPERDEC; + wire delay_UIDQUPPERINC; + wire delay_UIDRPUPDATE; + wire delay_UILDQSDEC; + wire delay_UILDQSINC; + wire delay_UIREAD; + wire delay_UISDI; + wire delay_UIUDQSDEC; + wire delay_UIUDQSINC; + + + assign #(out_delay) ADDR = delay_ADDR; + assign #(out_delay) BA = delay_BA; + assign #(out_delay) CAS = delay_CAS; + assign #(out_delay) CKE = delay_CKE; + assign #(out_delay) DQIOWEN0 = delay_DQIOWEN0; + assign #(out_delay) DQON = delay_DQON; + assign #(out_delay) DQOP = delay_DQOP; + assign #(out_delay) DQSIOWEN90N = delay_DQSIOWEN90N; + assign #(out_delay) DQSIOWEN90P = delay_DQSIOWEN90P; + assign #(out_delay) IOIDRPADD = delay_IOIDRPADD; + assign #(out_delay) IOIDRPADDR = delay_IOIDRPADDR; + assign #(out_delay) IOIDRPBROADCAST = delay_IOIDRPBROADCAST; + assign #(out_delay) IOIDRPCLK = delay_IOIDRPCLK; + assign #(out_delay) IOIDRPCS = delay_IOIDRPCS; + assign #(out_delay) IOIDRPSDO = delay_IOIDRPSDO; + assign #(out_delay) IOIDRPTRAIN = delay_IOIDRPTRAIN; + assign #(out_delay) IOIDRPUPDATE = delay_IOIDRPUPDATE; + assign #(out_delay) LDMN = delay_LDMN; + assign #(out_delay) LDMP = delay_LDMP; + assign #(out_delay) ODT = delay_ODT; + assign #(out_delay) P0CMDEMPTY = delay_P0CMDEMPTY; + assign #(out_delay) P0CMDFULL = delay_P0CMDFULL; + assign #(out_delay) P0RDCOUNT = delay_P0RDCOUNT; + assign #(out_delay) P0RDDATA = delay_P0RDDATA; + assign #(out_delay) P0RDEMPTY = delay_P0RDEMPTY; + assign #(out_delay) P0RDERROR = delay_P0RDERROR; + assign #(out_delay) P0RDFULL = delay_P0RDFULL; + assign #(out_delay) P0RDOVERFLOW = delay_P0RDOVERFLOW; + assign #(out_delay) P0WRCOUNT = delay_P0WRCOUNT; + assign #(out_delay) P0WREMPTY = delay_P0WREMPTY; + assign #(out_delay) P0WRERROR = delay_P0WRERROR; + assign #(out_delay) P0WRFULL = delay_P0WRFULL; + assign #(out_delay) P0WRUNDERRUN = delay_P0WRUNDERRUN; + assign #(out_delay) P1CMDEMPTY = delay_P1CMDEMPTY; + assign #(out_delay) P1CMDFULL = delay_P1CMDFULL; + assign #(out_delay) P1RDCOUNT = delay_P1RDCOUNT; + assign #(out_delay) P1RDDATA = delay_P1RDDATA; + assign #(out_delay) P1RDEMPTY = delay_P1RDEMPTY; + assign #(out_delay) P1RDERROR = delay_P1RDERROR; + assign #(out_delay) P1RDFULL = delay_P1RDFULL; + assign #(out_delay) P1RDOVERFLOW = delay_P1RDOVERFLOW; + assign #(out_delay) P1WRCOUNT = delay_P1WRCOUNT; + assign #(out_delay) P1WREMPTY = delay_P1WREMPTY; + assign #(out_delay) P1WRERROR = delay_P1WRERROR; + assign #(out_delay) P1WRFULL = delay_P1WRFULL; + assign #(out_delay) P1WRUNDERRUN = delay_P1WRUNDERRUN; + assign #(out_delay) P2CMDEMPTY = delay_P2CMDEMPTY; + assign #(out_delay) P2CMDFULL = delay_P2CMDFULL; + assign #(out_delay) P2COUNT = delay_P2COUNT; + assign #(out_delay) P2EMPTY = delay_P2EMPTY; + assign #(out_delay) P2ERROR = delay_P2ERROR; + assign #(out_delay) P2FULL = delay_P2FULL; + assign #(out_delay) P2RDDATA = delay_P2RDDATA; + assign #(out_delay) P2RDOVERFLOW = delay_P2RDOVERFLOW; + assign #(out_delay) P2WRUNDERRUN = delay_P2WRUNDERRUN; + assign #(out_delay) P3CMDEMPTY = delay_P3CMDEMPTY; + assign #(out_delay) P3CMDFULL = delay_P3CMDFULL; + assign #(out_delay) P3COUNT = delay_P3COUNT; + assign #(out_delay) P3EMPTY = delay_P3EMPTY; + assign #(out_delay) P3ERROR = delay_P3ERROR; + assign #(out_delay) P3FULL = delay_P3FULL; + assign #(out_delay) P3RDDATA = delay_P3RDDATA; + assign #(out_delay) P3RDOVERFLOW = delay_P3RDOVERFLOW; + assign #(out_delay) P3WRUNDERRUN = delay_P3WRUNDERRUN; + assign #(out_delay) P4CMDEMPTY = delay_P4CMDEMPTY; + assign #(out_delay) P4CMDFULL = delay_P4CMDFULL; + assign #(out_delay) P4COUNT = delay_P4COUNT; + assign #(out_delay) P4EMPTY = delay_P4EMPTY; + assign #(out_delay) P4ERROR = delay_P4ERROR; + assign #(out_delay) P4FULL = delay_P4FULL; + assign #(out_delay) P4RDDATA = delay_P4RDDATA; + assign #(out_delay) P4RDOVERFLOW = delay_P4RDOVERFLOW; + assign #(out_delay) P4WRUNDERRUN = delay_P4WRUNDERRUN; + assign #(out_delay) P5CMDEMPTY = delay_P5CMDEMPTY; + assign #(out_delay) P5CMDFULL = delay_P5CMDFULL; + assign #(out_delay) P5COUNT = delay_P5COUNT; + assign #(out_delay) P5EMPTY = delay_P5EMPTY; + assign #(out_delay) P5ERROR = delay_P5ERROR; + assign #(out_delay) P5FULL = delay_P5FULL; + assign #(out_delay) P5RDDATA = delay_P5RDDATA; + assign #(out_delay) P5RDOVERFLOW = delay_P5RDOVERFLOW; + assign #(out_delay) P5WRUNDERRUN = delay_P5WRUNDERRUN; + assign #(out_delay) RAS = delay_RAS; + assign #(out_delay) RST = delay_RST; + assign #(out_delay) SELFREFRESHMODE = delay_SELFREFRESHMODE; + assign #(out_delay) STATUS = delay_STATUS; + assign #(out_delay) UDMN = delay_UDMN; + assign #(out_delay) UDMP = delay_UDMP; + assign #(out_delay) UOCALSTART = delay_UOCALSTART; + assign #(out_delay) UOCMDREADYIN = delay_UOCMDREADYIN; + assign #(out_delay) UODATA = delay_UODATA; + assign #(out_delay) UODATAVALID = delay_UODATAVALID; + assign #(out_delay) UODONECAL = delay_UODONECAL; + assign #(out_delay) UOREFRSHFLAG = delay_UOREFRSHFLAG; + assign #(out_delay) UOSDO = delay_UOSDO; + assign #(out_delay) WE = delay_WE; + + assign #(INCLK_DELAY) delay_DQSIOIN = DQSIOIN; + assign #(INCLK_DELAY) delay_DQSIOIP = DQSIOIP; + assign #(INCLK_DELAY) delay_P0CMDCLK = P0CMDCLK; + assign #(INCLK_DELAY) delay_P0RDCLK = P0RDCLK; + assign #(INCLK_DELAY) delay_P0WRCLK = P0WRCLK; + assign #(INCLK_DELAY) delay_P1CMDCLK = P1CMDCLK; + assign #(INCLK_DELAY) delay_P1RDCLK = P1RDCLK; + assign #(INCLK_DELAY) delay_P1WRCLK = P1WRCLK; + assign #(INCLK_DELAY) delay_P2CLK = P2CLK; + assign #(INCLK_DELAY) delay_P2CMDCLK = P2CMDCLK; + assign #(INCLK_DELAY) delay_P3CLK = P3CLK; + assign #(INCLK_DELAY) delay_P3CMDCLK = P3CMDCLK; + assign #(INCLK_DELAY) delay_P4CLK = P4CLK; + assign #(INCLK_DELAY) delay_P4CMDCLK = P4CMDCLK; + assign #(INCLK_DELAY) delay_P5CLK = P5CLK; + assign #(INCLK_DELAY) delay_P5CMDCLK = P5CMDCLK; + assign #(INCLK_DELAY) delay_PLLCLK = PLLCLK; + assign #(INCLK_DELAY) delay_UDQSIOIN = UDQSIOIN; + assign #(INCLK_DELAY) delay_UDQSIOIP = UDQSIOIP; + assign #(INCLK_DELAY) delay_UICLK = UICLK; + + assign #(in_delay) delay_DQI = DQI; + assign #(in_delay) delay_IOIDRPSDI = IOIDRPSDI; + assign #(in_delay) delay_P0ARBEN = P0ARBEN; + assign #(in_delay) delay_P0CMDBA = P0CMDBA; + assign #(in_delay) delay_P0CMDBL = P0CMDBL; + assign #(in_delay) delay_P0CMDCA = P0CMDCA; + assign #(in_delay) delay_P0CMDEN = P0CMDEN; + assign #(in_delay) delay_P0CMDINSTR = P0CMDINSTR; + assign #(in_delay) delay_P0CMDRA = P0CMDRA; + assign #(in_delay) delay_P0RDEN = P0RDEN; + assign #(in_delay) delay_P0RWRMASK = P0RWRMASK; + assign #(in_delay) delay_P0WRDATA = P0WRDATA; + assign #(in_delay) delay_P0WREN = P0WREN; + assign #(in_delay) delay_P1ARBEN = P1ARBEN; + assign #(in_delay) delay_P1CMDBA = P1CMDBA; + assign #(in_delay) delay_P1CMDBL = P1CMDBL; + assign #(in_delay) delay_P1CMDCA = P1CMDCA; + assign #(in_delay) delay_P1CMDEN = P1CMDEN; + assign #(in_delay) delay_P1CMDINSTR = P1CMDINSTR; + assign #(in_delay) delay_P1CMDRA = P1CMDRA; + assign #(in_delay) delay_P1RDEN = P1RDEN; + assign #(in_delay) delay_P1RWRMASK = P1RWRMASK; + assign #(in_delay) delay_P1WRDATA = P1WRDATA; + assign #(in_delay) delay_P1WREN = P1WREN; + assign #(in_delay) delay_P2ARBEN = P2ARBEN; + assign #(in_delay) delay_P2CMDBA = P2CMDBA; + assign #(in_delay) delay_P2CMDBL = P2CMDBL; + assign #(in_delay) delay_P2CMDCA = P2CMDCA; + assign #(in_delay) delay_P2CMDEN = P2CMDEN; + assign #(in_delay) delay_P2CMDINSTR = P2CMDINSTR; + assign #(in_delay) delay_P2CMDRA = P2CMDRA; + assign #(in_delay) delay_P2EN = P2EN; + assign #(in_delay) delay_P2WRDATA = P2WRDATA; + assign #(in_delay) delay_P2WRMASK = P2WRMASK; + assign #(in_delay) delay_P3ARBEN = P3ARBEN; + assign #(in_delay) delay_P3CMDBA = P3CMDBA; + assign #(in_delay) delay_P3CMDBL = P3CMDBL; + assign #(in_delay) delay_P3CMDCA = P3CMDCA; + assign #(in_delay) delay_P3CMDEN = P3CMDEN; + assign #(in_delay) delay_P3CMDINSTR = P3CMDINSTR; + assign #(in_delay) delay_P3CMDRA = P3CMDRA; + assign #(in_delay) delay_P3EN = P3EN; + assign #(in_delay) delay_P3WRDATA = P3WRDATA; + assign #(in_delay) delay_P3WRMASK = P3WRMASK; + assign #(in_delay) delay_P4ARBEN = P4ARBEN; + assign #(in_delay) delay_P4CMDBA = P4CMDBA; + assign #(in_delay) delay_P4CMDBL = P4CMDBL; + assign #(in_delay) delay_P4CMDCA = P4CMDCA; + assign #(in_delay) delay_P4CMDEN = P4CMDEN; + assign #(in_delay) delay_P4CMDINSTR = P4CMDINSTR; + assign #(in_delay) delay_P4CMDRA = P4CMDRA; + assign #(in_delay) delay_P4EN = P4EN; + assign #(in_delay) delay_P4WRDATA = P4WRDATA; + assign #(in_delay) delay_P4WRMASK = P4WRMASK; + assign #(in_delay) delay_P5ARBEN = P5ARBEN; + assign #(in_delay) delay_P5CMDBA = P5CMDBA; + assign #(in_delay) delay_P5CMDBL = P5CMDBL; + assign #(in_delay) delay_P5CMDCA = P5CMDCA; + assign #(in_delay) delay_P5CMDEN = P5CMDEN; + assign #(in_delay) delay_P5CMDINSTR = P5CMDINSTR; + assign #(in_delay) delay_P5CMDRA = P5CMDRA; + assign #(in_delay) delay_P5EN = P5EN; + assign #(in_delay) delay_P5WRDATA = P5WRDATA; + assign #(in_delay) delay_P5WRMASK = P5WRMASK; + assign #(in_delay) delay_PLLCE = PLLCE; + assign #(in_delay) delay_PLLLOCK = PLLLOCK; + assign #(in_delay) delay_RECAL = RECAL; + assign #(in_delay) delay_SELFREFRESHENTER = SELFREFRESHENTER; + assign #(in_delay) delay_SYSRST = SYSRST; + assign #(in_delay) delay_UIADD = UIADD; + assign #(in_delay) delay_UIADDR = UIADDR; + assign #(in_delay) delay_UIBROADCAST = UIBROADCAST; + assign #(in_delay) delay_UICMD = UICMD; + assign #(in_delay) delay_UICMDEN = UICMDEN; + assign #(in_delay) delay_UICMDIN = UICMDIN; + assign #(in_delay) delay_UICS = UICS; + assign #(in_delay) delay_UIDONECAL = UIDONECAL; + assign #(in_delay) delay_UIDQCOUNT = UIDQCOUNT; + assign #(in_delay) delay_UIDQLOWERDEC = UIDQLOWERDEC; + assign #(in_delay) delay_UIDQLOWERINC = UIDQLOWERINC; + assign #(in_delay) delay_UIDQUPPERDEC = UIDQUPPERDEC; + assign #(in_delay) delay_UIDQUPPERINC = UIDQUPPERINC; + assign #(in_delay) delay_UIDRPUPDATE = UIDRPUPDATE; + assign #(in_delay) delay_UILDQSDEC = UILDQSDEC; + assign #(in_delay) delay_UILDQSINC = UILDQSINC; + assign #(in_delay) delay_UIREAD = UIREAD; + assign #(in_delay) delay_UISDI = UISDI; + assign #(in_delay) delay_UIUDQSDEC = UIUDQSDEC; + assign #(in_delay) delay_UIUDQSINC = UIUDQSINC; + + B_MCB #( + .ARB_NUM_TIME_SLOTS (ARB_NUM_TIME_SLOTS), + .ARB_TIME_SLOT_0 (ARB_TIME_SLOT_0), + .ARB_TIME_SLOT_1 (ARB_TIME_SLOT_1), + .ARB_TIME_SLOT_10 (ARB_TIME_SLOT_10), + .ARB_TIME_SLOT_11 (ARB_TIME_SLOT_11), + .ARB_TIME_SLOT_2 (ARB_TIME_SLOT_2), + .ARB_TIME_SLOT_3 (ARB_TIME_SLOT_3), + .ARB_TIME_SLOT_4 (ARB_TIME_SLOT_4), + .ARB_TIME_SLOT_5 (ARB_TIME_SLOT_5), + .ARB_TIME_SLOT_6 (ARB_TIME_SLOT_6), + .ARB_TIME_SLOT_7 (ARB_TIME_SLOT_7), + .ARB_TIME_SLOT_8 (ARB_TIME_SLOT_8), + .ARB_TIME_SLOT_9 (ARB_TIME_SLOT_9), + .CAL_BA (CAL_BA), + .CAL_BYPASS (CAL_BYPASS), + .CAL_CA (CAL_CA), + .CAL_CALIBRATION_MODE (CAL_CALIBRATION_MODE), + .CAL_CLK_DIV (CAL_CLK_DIV), + .CAL_DELAY (CAL_DELAY), + .CAL_RA (CAL_RA), + .MEM_ADDR_ORDER (MEM_ADDR_ORDER), + .MEM_BA_SIZE (MEM_BA_SIZE), + .MEM_BURST_LEN (MEM_BURST_LEN), + .MEM_CAS_LATENCY (MEM_CAS_LATENCY), + .MEM_CA_SIZE (MEM_CA_SIZE), + .MEM_DDR1_2_ODS (MEM_DDR1_2_ODS), + .MEM_DDR2_3_HIGH_TEMP_SR (MEM_DDR2_3_HIGH_TEMP_SR), + .MEM_DDR2_3_PA_SR (MEM_DDR2_3_PA_SR), + .MEM_DDR2_ADD_LATENCY (MEM_DDR2_ADD_LATENCY), + .MEM_DDR2_DIFF_DQS_EN (MEM_DDR2_DIFF_DQS_EN), + .MEM_DDR2_RTT (MEM_DDR2_RTT), + .MEM_DDR2_WRT_RECOVERY (MEM_DDR2_WRT_RECOVERY), + .MEM_DDR3_ADD_LATENCY (MEM_DDR3_ADD_LATENCY), + .MEM_DDR3_AUTO_SR (MEM_DDR3_AUTO_SR), + .MEM_DDR3_CAS_LATENCY (MEM_DDR3_CAS_LATENCY), + .MEM_DDR3_CAS_WR_LATENCY (MEM_DDR3_CAS_WR_LATENCY), + .MEM_DDR3_DYN_WRT_ODT (MEM_DDR3_DYN_WRT_ODT), + .MEM_DDR3_ODS (MEM_DDR3_ODS), + .MEM_DDR3_RTT (MEM_DDR3_RTT), + .MEM_DDR3_WRT_RECOVERY (MEM_DDR3_WRT_RECOVERY), + .MEM_MDDR_ODS (MEM_MDDR_ODS), + .MEM_MOBILE_PA_SR (MEM_MOBILE_PA_SR), + .MEM_MOBILE_TC_SR (MEM_MOBILE_TC_SR), + .MEM_RAS_VAL (MEM_RAS_VAL), + .MEM_RA_SIZE (MEM_RA_SIZE), + .MEM_RCD_VAL (MEM_RCD_VAL), + .MEM_REFI_VAL (MEM_REFI_VAL), + .MEM_RFC_VAL (MEM_RFC_VAL), + .MEM_RP_VAL (MEM_RP_VAL), + .MEM_RTP_VAL (MEM_RTP_VAL), + .MEM_TYPE (MEM_TYPE), + .MEM_WIDTH (MEM_WIDTH), + .MEM_WR_VAL (MEM_WR_VAL), + .MEM_WTR_VAL (MEM_WTR_VAL), + .PORT_CONFIG (PORT_CONFIG)) + + B_MCB_INST ( + .ADDR (delay_ADDR), + .BA (delay_BA), + .CAS (delay_CAS), + .CKE (delay_CKE), + .DQIOWEN0 (delay_DQIOWEN0), + .DQON (delay_DQON), + .DQOP (delay_DQOP), + .DQSIOWEN90N (delay_DQSIOWEN90N), + .DQSIOWEN90P (delay_DQSIOWEN90P), + .IOIDRPADD (delay_IOIDRPADD), + .IOIDRPADDR (delay_IOIDRPADDR), + .IOIDRPBROADCAST (delay_IOIDRPBROADCAST), + .IOIDRPCLK (delay_IOIDRPCLK), + .IOIDRPCS (delay_IOIDRPCS), + .IOIDRPSDO (delay_IOIDRPSDO), + .IOIDRPTRAIN (delay_IOIDRPTRAIN), + .IOIDRPUPDATE (delay_IOIDRPUPDATE), + .LDMN (delay_LDMN), + .LDMP (delay_LDMP), + .ODT (delay_ODT), + .P0CMDEMPTY (delay_P0CMDEMPTY), + .P0CMDFULL (delay_P0CMDFULL), + .P0RDCOUNT (delay_P0RDCOUNT), + .P0RDDATA (delay_P0RDDATA), + .P0RDEMPTY (delay_P0RDEMPTY), + .P0RDERROR (delay_P0RDERROR), + .P0RDFULL (delay_P0RDFULL), + .P0RDOVERFLOW (delay_P0RDOVERFLOW), + .P0WRCOUNT (delay_P0WRCOUNT), + .P0WREMPTY (delay_P0WREMPTY), + .P0WRERROR (delay_P0WRERROR), + .P0WRFULL (delay_P0WRFULL), + .P0WRUNDERRUN (delay_P0WRUNDERRUN), + .P1CMDEMPTY (delay_P1CMDEMPTY), + .P1CMDFULL (delay_P1CMDFULL), + .P1RDCOUNT (delay_P1RDCOUNT), + .P1RDDATA (delay_P1RDDATA), + .P1RDEMPTY (delay_P1RDEMPTY), + .P1RDERROR (delay_P1RDERROR), + .P1RDFULL (delay_P1RDFULL), + .P1RDOVERFLOW (delay_P1RDOVERFLOW), + .P1WRCOUNT (delay_P1WRCOUNT), + .P1WREMPTY (delay_P1WREMPTY), + .P1WRERROR (delay_P1WRERROR), + .P1WRFULL (delay_P1WRFULL), + .P1WRUNDERRUN (delay_P1WRUNDERRUN), + .P2CMDEMPTY (delay_P2CMDEMPTY), + .P2CMDFULL (delay_P2CMDFULL), + .P2COUNT (delay_P2COUNT), + .P2EMPTY (delay_P2EMPTY), + .P2ERROR (delay_P2ERROR), + .P2FULL (delay_P2FULL), + .P2RDDATA (delay_P2RDDATA), + .P2RDOVERFLOW (delay_P2RDOVERFLOW), + .P2WRUNDERRUN (delay_P2WRUNDERRUN), + .P3CMDEMPTY (delay_P3CMDEMPTY), + .P3CMDFULL (delay_P3CMDFULL), + .P3COUNT (delay_P3COUNT), + .P3EMPTY (delay_P3EMPTY), + .P3ERROR (delay_P3ERROR), + .P3FULL (delay_P3FULL), + .P3RDDATA (delay_P3RDDATA), + .P3RDOVERFLOW (delay_P3RDOVERFLOW), + .P3WRUNDERRUN (delay_P3WRUNDERRUN), + .P4CMDEMPTY (delay_P4CMDEMPTY), + .P4CMDFULL (delay_P4CMDFULL), + .P4COUNT (delay_P4COUNT), + .P4EMPTY (delay_P4EMPTY), + .P4ERROR (delay_P4ERROR), + .P4FULL (delay_P4FULL), + .P4RDDATA (delay_P4RDDATA), + .P4RDOVERFLOW (delay_P4RDOVERFLOW), + .P4WRUNDERRUN (delay_P4WRUNDERRUN), + .P5CMDEMPTY (delay_P5CMDEMPTY), + .P5CMDFULL (delay_P5CMDFULL), + .P5COUNT (delay_P5COUNT), + .P5EMPTY (delay_P5EMPTY), + .P5ERROR (delay_P5ERROR), + .P5FULL (delay_P5FULL), + .P5RDDATA (delay_P5RDDATA), + .P5RDOVERFLOW (delay_P5RDOVERFLOW), + .P5WRUNDERRUN (delay_P5WRUNDERRUN), + .RAS (delay_RAS), + .RST (delay_RST), + .SELFREFRESHMODE (delay_SELFREFRESHMODE), + .STATUS (delay_STATUS), + .UDMN (delay_UDMN), + .UDMP (delay_UDMP), + .UOCALSTART (delay_UOCALSTART), + .UOCMDREADYIN (delay_UOCMDREADYIN), + .UODATA (delay_UODATA), + .UODATAVALID (delay_UODATAVALID), + .UODONECAL (delay_UODONECAL), + .UOREFRSHFLAG (delay_UOREFRSHFLAG), + .UOSDO (delay_UOSDO), + .WE (delay_WE), + .DQI (delay_DQI), + .DQSIOIN (delay_DQSIOIN), + .DQSIOIP (delay_DQSIOIP), + .IOIDRPSDI (delay_IOIDRPSDI), + .P0ARBEN (delay_P0ARBEN), + .P0CMDBA (delay_P0CMDBA), + .P0CMDBL (delay_P0CMDBL), + .P0CMDCA (delay_P0CMDCA), + .P0CMDCLK (delay_P0CMDCLK), + .P0CMDEN (delay_P0CMDEN), + .P0CMDINSTR (delay_P0CMDINSTR), + .P0CMDRA (delay_P0CMDRA), + .P0RDCLK (delay_P0RDCLK), + .P0RDEN (delay_P0RDEN), + .P0RWRMASK (delay_P0RWRMASK), + .P0WRCLK (delay_P0WRCLK), + .P0WRDATA (delay_P0WRDATA), + .P0WREN (delay_P0WREN), + .P1ARBEN (delay_P1ARBEN), + .P1CMDBA (delay_P1CMDBA), + .P1CMDBL (delay_P1CMDBL), + .P1CMDCA (delay_P1CMDCA), + .P1CMDCLK (delay_P1CMDCLK), + .P1CMDEN (delay_P1CMDEN), + .P1CMDINSTR (delay_P1CMDINSTR), + .P1CMDRA (delay_P1CMDRA), + .P1RDCLK (delay_P1RDCLK), + .P1RDEN (delay_P1RDEN), + .P1RWRMASK (delay_P1RWRMASK), + .P1WRCLK (delay_P1WRCLK), + .P1WRDATA (delay_P1WRDATA), + .P1WREN (delay_P1WREN), + .P2ARBEN (delay_P2ARBEN), + .P2CLK (delay_P2CLK), + .P2CMDBA (delay_P2CMDBA), + .P2CMDBL (delay_P2CMDBL), + .P2CMDCA (delay_P2CMDCA), + .P2CMDCLK (delay_P2CMDCLK), + .P2CMDEN (delay_P2CMDEN), + .P2CMDINSTR (delay_P2CMDINSTR), + .P2CMDRA (delay_P2CMDRA), + .P2EN (delay_P2EN), + .P2WRDATA (delay_P2WRDATA), + .P2WRMASK (delay_P2WRMASK), + .P3ARBEN (delay_P3ARBEN), + .P3CLK (delay_P3CLK), + .P3CMDBA (delay_P3CMDBA), + .P3CMDBL (delay_P3CMDBL), + .P3CMDCA (delay_P3CMDCA), + .P3CMDCLK (delay_P3CMDCLK), + .P3CMDEN (delay_P3CMDEN), + .P3CMDINSTR (delay_P3CMDINSTR), + .P3CMDRA (delay_P3CMDRA), + .P3EN (delay_P3EN), + .P3WRDATA (delay_P3WRDATA), + .P3WRMASK (delay_P3WRMASK), + .P4ARBEN (delay_P4ARBEN), + .P4CLK (delay_P4CLK), + .P4CMDBA (delay_P4CMDBA), + .P4CMDBL (delay_P4CMDBL), + .P4CMDCA (delay_P4CMDCA), + .P4CMDCLK (delay_P4CMDCLK), + .P4CMDEN (delay_P4CMDEN), + .P4CMDINSTR (delay_P4CMDINSTR), + .P4CMDRA (delay_P4CMDRA), + .P4EN (delay_P4EN), + .P4WRDATA (delay_P4WRDATA), + .P4WRMASK (delay_P4WRMASK), + .P5ARBEN (delay_P5ARBEN), + .P5CLK (delay_P5CLK), + .P5CMDBA (delay_P5CMDBA), + .P5CMDBL (delay_P5CMDBL), + .P5CMDCA (delay_P5CMDCA), + .P5CMDCLK (delay_P5CMDCLK), + .P5CMDEN (delay_P5CMDEN), + .P5CMDINSTR (delay_P5CMDINSTR), + .P5CMDRA (delay_P5CMDRA), + .P5EN (delay_P5EN), + .P5WRDATA (delay_P5WRDATA), + .P5WRMASK (delay_P5WRMASK), + .PLLCE (delay_PLLCE), + .PLLCLK (delay_PLLCLK), + .PLLLOCK (delay_PLLLOCK), + .RECAL (delay_RECAL), + .SELFREFRESHENTER (delay_SELFREFRESHENTER), + .SYSRST (delay_SYSRST), + .UDQSIOIN (delay_UDQSIOIN), + .UDQSIOIP (delay_UDQSIOIP), + .UIADD (delay_UIADD), + .UIADDR (delay_UIADDR), + .UIBROADCAST (delay_UIBROADCAST), + .UICLK (delay_UICLK), + .UICMD (delay_UICMD), + .UICMDEN (delay_UICMDEN), + .UICMDIN (delay_UICMDIN), + .UICS (delay_UICS), + .UIDONECAL (delay_UIDONECAL), + .UIDQCOUNT (delay_UIDQCOUNT), + .UIDQLOWERDEC (delay_UIDQLOWERDEC), + .UIDQLOWERINC (delay_UIDQLOWERINC), + .UIDQUPPERDEC (delay_UIDQUPPERDEC), + .UIDQUPPERINC (delay_UIDQUPPERINC), + .UIDRPUPDATE (delay_UIDRPUPDATE), + .UILDQSDEC (delay_UILDQSDEC), + .UILDQSINC (delay_UILDQSINC), + .UIREAD (delay_UIREAD), + .UISDI (delay_UISDI), + .UIUDQSDEC (delay_UIUDQSDEC), + .UIUDQSINC (delay_UIUDQSINC), + .GSR (GSR) + ); + + specify + ( P0CMDCLK => P0CMDEMPTY) = (100, 100); + ( P0CMDCLK => P0CMDFULL) = (100, 100); + ( P0RDCLK => P0RDCOUNT[0]) = (100, 100); + ( P0RDCLK => P0RDCOUNT[1]) = (100, 100); + ( P0RDCLK => P0RDCOUNT[2]) = (100, 100); + ( P0RDCLK => P0RDCOUNT[3]) = (100, 100); + ( P0RDCLK => P0RDCOUNT[4]) = (100, 100); + ( P0RDCLK => P0RDCOUNT[5]) = (100, 100); + ( P0RDCLK => P0RDCOUNT[6]) = (100, 100); + ( P0RDCLK => P0RDDATA[0]) = (100, 100); + ( P0RDCLK => P0RDDATA[10]) = (100, 100); + ( P0RDCLK => P0RDDATA[11]) = (100, 100); + ( P0RDCLK => P0RDDATA[12]) = (100, 100); + ( P0RDCLK => P0RDDATA[13]) = (100, 100); + ( P0RDCLK => P0RDDATA[14]) = (100, 100); + ( P0RDCLK => P0RDDATA[15]) = (100, 100); + ( P0RDCLK => P0RDDATA[16]) = (100, 100); + ( P0RDCLK => P0RDDATA[17]) = (100, 100); + ( P0RDCLK => P0RDDATA[18]) = (100, 100); + ( P0RDCLK => P0RDDATA[19]) = (100, 100); + ( P0RDCLK => P0RDDATA[1]) = (100, 100); + ( P0RDCLK => P0RDDATA[20]) = (100, 100); + ( P0RDCLK => P0RDDATA[21]) = (100, 100); + ( P0RDCLK => P0RDDATA[22]) = (100, 100); + ( P0RDCLK => P0RDDATA[23]) = (100, 100); + ( P0RDCLK => P0RDDATA[24]) = (100, 100); + ( P0RDCLK => P0RDDATA[25]) = (100, 100); + ( P0RDCLK => P0RDDATA[26]) = (100, 100); + ( P0RDCLK => P0RDDATA[27]) = (100, 100); + ( P0RDCLK => P0RDDATA[28]) = (100, 100); + ( P0RDCLK => P0RDDATA[29]) = (100, 100); + ( P0RDCLK => P0RDDATA[2]) = (100, 100); + ( P0RDCLK => P0RDDATA[30]) = (100, 100); + ( P0RDCLK => P0RDDATA[31]) = (100, 100); + ( P0RDCLK => P0RDDATA[3]) = (100, 100); + ( P0RDCLK => P0RDDATA[4]) = (100, 100); + ( P0RDCLK => P0RDDATA[5]) = (100, 100); + ( P0RDCLK => P0RDDATA[6]) = (100, 100); + ( P0RDCLK => P0RDDATA[7]) = (100, 100); + ( P0RDCLK => P0RDDATA[8]) = (100, 100); + ( P0RDCLK => P0RDDATA[9]) = (100, 100); + ( P0RDCLK => P0RDEMPTY) = (100, 100); + ( P0RDCLK => P0RDERROR) = (100, 100); + ( P0RDCLK => P0RDFULL) = (100, 100); + ( P0RDCLK => P0RDOVERFLOW) = (100, 100); + ( P0WRCLK => P0WRCOUNT[0]) = (100, 100); + ( P0WRCLK => P0WRCOUNT[1]) = (100, 100); + ( P0WRCLK => P0WRCOUNT[2]) = (100, 100); + ( P0WRCLK => P0WRCOUNT[3]) = (100, 100); + ( P0WRCLK => P0WRCOUNT[4]) = (100, 100); + ( P0WRCLK => P0WRCOUNT[5]) = (100, 100); + ( P0WRCLK => P0WRCOUNT[6]) = (100, 100); + ( P0WRCLK => P0WREMPTY) = (100, 100); + ( P0WRCLK => P0WRERROR) = (100, 100); + ( P0WRCLK => P0WRFULL) = (100, 100); + ( P0WRCLK => P0WRUNDERRUN) = (100, 100); + ( P1CMDCLK => P1CMDEMPTY) = (100, 100); + ( P1CMDCLK => P1CMDFULL) = (100, 100); + ( P1RDCLK => P1RDCOUNT[0]) = (100, 100); + ( P1RDCLK => P1RDCOUNT[1]) = (100, 100); + ( P1RDCLK => P1RDCOUNT[2]) = (100, 100); + ( P1RDCLK => P1RDCOUNT[3]) = (100, 100); + ( P1RDCLK => P1RDCOUNT[4]) = (100, 100); + ( P1RDCLK => P1RDCOUNT[5]) = (100, 100); + ( P1RDCLK => P1RDCOUNT[6]) = (100, 100); + ( P1RDCLK => P1RDDATA[0]) = (100, 100); + ( P1RDCLK => P1RDDATA[10]) = (100, 100); + ( P1RDCLK => P1RDDATA[11]) = (100, 100); + ( P1RDCLK => P1RDDATA[12]) = (100, 100); + ( P1RDCLK => P1RDDATA[13]) = (100, 100); + ( P1RDCLK => P1RDDATA[14]) = (100, 100); + ( P1RDCLK => P1RDDATA[15]) = (100, 100); + ( P1RDCLK => P1RDDATA[16]) = (100, 100); + ( P1RDCLK => P1RDDATA[17]) = (100, 100); + ( P1RDCLK => P1RDDATA[18]) = (100, 100); + ( P1RDCLK => P1RDDATA[19]) = (100, 100); + ( P1RDCLK => P1RDDATA[1]) = (100, 100); + ( P1RDCLK => P1RDDATA[20]) = (100, 100); + ( P1RDCLK => P1RDDATA[21]) = (100, 100); + ( P1RDCLK => P1RDDATA[22]) = (100, 100); + ( P1RDCLK => P1RDDATA[23]) = (100, 100); + ( P1RDCLK => P1RDDATA[24]) = (100, 100); + ( P1RDCLK => P1RDDATA[25]) = (100, 100); + ( P1RDCLK => P1RDDATA[26]) = (100, 100); + ( P1RDCLK => P1RDDATA[27]) = (100, 100); + ( P1RDCLK => P1RDDATA[28]) = (100, 100); + ( P1RDCLK => P1RDDATA[29]) = (100, 100); + ( P1RDCLK => P1RDDATA[2]) = (100, 100); + ( P1RDCLK => P1RDDATA[30]) = (100, 100); + ( P1RDCLK => P1RDDATA[31]) = (100, 100); + ( P1RDCLK => P1RDDATA[3]) = (100, 100); + ( P1RDCLK => P1RDDATA[4]) = (100, 100); + ( P1RDCLK => P1RDDATA[5]) = (100, 100); + ( P1RDCLK => P1RDDATA[6]) = (100, 100); + ( P1RDCLK => P1RDDATA[7]) = (100, 100); + ( P1RDCLK => P1RDDATA[8]) = (100, 100); + ( P1RDCLK => P1RDDATA[9]) = (100, 100); + ( P1RDCLK => P1RDEMPTY) = (100, 100); + ( P1RDCLK => P1RDERROR) = (100, 100); + ( P1RDCLK => P1RDFULL) = (100, 100); + ( P1RDCLK => P1RDOVERFLOW) = (100, 100); + ( P1WRCLK => P1WRCOUNT[0]) = (100, 100); + ( P1WRCLK => P1WRCOUNT[1]) = (100, 100); + ( P1WRCLK => P1WRCOUNT[2]) = (100, 100); + ( P1WRCLK => P1WRCOUNT[3]) = (100, 100); + ( P1WRCLK => P1WRCOUNT[4]) = (100, 100); + ( P1WRCLK => P1WRCOUNT[5]) = (100, 100); + ( P1WRCLK => P1WRCOUNT[6]) = (100, 100); + ( P1WRCLK => P1WREMPTY) = (100, 100); + ( P1WRCLK => P1WRERROR) = (100, 100); + ( P1WRCLK => P1WRFULL) = (100, 100); + ( P1WRCLK => P1WRUNDERRUN) = (100, 100); + ( P2CLK => P2COUNT[0]) = (100, 100); + ( P2CLK => P2COUNT[1]) = (100, 100); + ( P2CLK => P2COUNT[2]) = (100, 100); + ( P2CLK => P2COUNT[3]) = (100, 100); + ( P2CLK => P2COUNT[4]) = (100, 100); + ( P2CLK => P2COUNT[5]) = (100, 100); + ( P2CLK => P2COUNT[6]) = (100, 100); + ( P2CLK => P2EMPTY) = (100, 100); + ( P2CLK => P2ERROR) = (100, 100); + ( P2CLK => P2FULL) = (100, 100); + ( P2CLK => P2RDDATA[0]) = (100, 100); + ( P2CLK => P2RDDATA[10]) = (100, 100); + ( P2CLK => P2RDDATA[11]) = (100, 100); + ( P2CLK => P2RDDATA[12]) = (100, 100); + ( P2CLK => P2RDDATA[13]) = (100, 100); + ( P2CLK => P2RDDATA[14]) = (100, 100); + ( P2CLK => P2RDDATA[15]) = (100, 100); + ( P2CLK => P2RDDATA[16]) = (100, 100); + ( P2CLK => P2RDDATA[17]) = (100, 100); + ( P2CLK => P2RDDATA[18]) = (100, 100); + ( P2CLK => P2RDDATA[19]) = (100, 100); + ( P2CLK => P2RDDATA[1]) = (100, 100); + ( P2CLK => P2RDDATA[20]) = (100, 100); + ( P2CLK => P2RDDATA[21]) = (100, 100); + ( P2CLK => P2RDDATA[22]) = (100, 100); + ( P2CLK => P2RDDATA[23]) = (100, 100); + ( P2CLK => P2RDDATA[24]) = (100, 100); + ( P2CLK => P2RDDATA[25]) = (100, 100); + ( P2CLK => P2RDDATA[26]) = (100, 100); + ( P2CLK => P2RDDATA[27]) = (100, 100); + ( P2CLK => P2RDDATA[28]) = (100, 100); + ( P2CLK => P2RDDATA[29]) = (100, 100); + ( P2CLK => P2RDDATA[2]) = (100, 100); + ( P2CLK => P2RDDATA[30]) = (100, 100); + ( P2CLK => P2RDDATA[31]) = (100, 100); + ( P2CLK => P2RDDATA[3]) = (100, 100); + ( P2CLK => P2RDDATA[4]) = (100, 100); + ( P2CLK => P2RDDATA[5]) = (100, 100); + ( P2CLK => P2RDDATA[6]) = (100, 100); + ( P2CLK => P2RDDATA[7]) = (100, 100); + ( P2CLK => P2RDDATA[8]) = (100, 100); + ( P2CLK => P2RDDATA[9]) = (100, 100); + ( P2CLK => P2RDOVERFLOW) = (100, 100); + ( P2CLK => P2WRUNDERRUN) = (100, 100); + ( P2CMDCLK => P2CMDEMPTY) = (100, 100); + ( P2CMDCLK => P2CMDFULL) = (100, 100); + ( P3CLK => P3COUNT[0]) = (100, 100); + ( P3CLK => P3COUNT[1]) = (100, 100); + ( P3CLK => P3COUNT[2]) = (100, 100); + ( P3CLK => P3COUNT[3]) = (100, 100); + ( P3CLK => P3COUNT[4]) = (100, 100); + ( P3CLK => P3COUNT[5]) = (100, 100); + ( P3CLK => P3COUNT[6]) = (100, 100); + ( P3CLK => P3EMPTY) = (100, 100); + ( P3CLK => P3ERROR) = (100, 100); + ( P3CLK => P3FULL) = (100, 100); + ( P3CLK => P3RDDATA[0]) = (100, 100); + ( P3CLK => P3RDDATA[10]) = (100, 100); + ( P3CLK => P3RDDATA[11]) = (100, 100); + ( P3CLK => P3RDDATA[12]) = (100, 100); + ( P3CLK => P3RDDATA[13]) = (100, 100); + ( P3CLK => P3RDDATA[14]) = (100, 100); + ( P3CLK => P3RDDATA[15]) = (100, 100); + ( P3CLK => P3RDDATA[16]) = (100, 100); + ( P3CLK => P3RDDATA[17]) = (100, 100); + ( P3CLK => P3RDDATA[18]) = (100, 100); + ( P3CLK => P3RDDATA[19]) = (100, 100); + ( P3CLK => P3RDDATA[1]) = (100, 100); + ( P3CLK => P3RDDATA[20]) = (100, 100); + ( P3CLK => P3RDDATA[21]) = (100, 100); + ( P3CLK => P3RDDATA[22]) = (100, 100); + ( P3CLK => P3RDDATA[23]) = (100, 100); + ( P3CLK => P3RDDATA[24]) = (100, 100); + ( P3CLK => P3RDDATA[25]) = (100, 100); + ( P3CLK => P3RDDATA[26]) = (100, 100); + ( P3CLK => P3RDDATA[27]) = (100, 100); + ( P3CLK => P3RDDATA[28]) = (100, 100); + ( P3CLK => P3RDDATA[29]) = (100, 100); + ( P3CLK => P3RDDATA[2]) = (100, 100); + ( P3CLK => P3RDDATA[30]) = (100, 100); + ( P3CLK => P3RDDATA[31]) = (100, 100); + ( P3CLK => P3RDDATA[3]) = (100, 100); + ( P3CLK => P3RDDATA[4]) = (100, 100); + ( P3CLK => P3RDDATA[5]) = (100, 100); + ( P3CLK => P3RDDATA[6]) = (100, 100); + ( P3CLK => P3RDDATA[7]) = (100, 100); + ( P3CLK => P3RDDATA[8]) = (100, 100); + ( P3CLK => P3RDDATA[9]) = (100, 100); + ( P3CLK => P3RDOVERFLOW) = (100, 100); + ( P3CLK => P3WRUNDERRUN) = (100, 100); + ( P3CMDCLK => P3CMDEMPTY) = (100, 100); + ( P3CMDCLK => P3CMDFULL) = (100, 100); + ( P4CLK => P4COUNT[0]) = (100, 100); + ( P4CLK => P4COUNT[1]) = (100, 100); + ( P4CLK => P4COUNT[2]) = (100, 100); + ( P4CLK => P4COUNT[3]) = (100, 100); + ( P4CLK => P4COUNT[4]) = (100, 100); + ( P4CLK => P4COUNT[5]) = (100, 100); + ( P4CLK => P4COUNT[6]) = (100, 100); + ( P4CLK => P4EMPTY) = (100, 100); + ( P4CLK => P4ERROR) = (100, 100); + ( P4CLK => P4FULL) = (100, 100); + ( P4CLK => P4RDDATA[0]) = (100, 100); + ( P4CLK => P4RDDATA[10]) = (100, 100); + ( P4CLK => P4RDDATA[11]) = (100, 100); + ( P4CLK => P4RDDATA[12]) = (100, 100); + ( P4CLK => P4RDDATA[13]) = (100, 100); + ( P4CLK => P4RDDATA[14]) = (100, 100); + ( P4CLK => P4RDDATA[15]) = (100, 100); + ( P4CLK => P4RDDATA[16]) = (100, 100); + ( P4CLK => P4RDDATA[17]) = (100, 100); + ( P4CLK => P4RDDATA[18]) = (100, 100); + ( P4CLK => P4RDDATA[19]) = (100, 100); + ( P4CLK => P4RDDATA[1]) = (100, 100); + ( P4CLK => P4RDDATA[20]) = (100, 100); + ( P4CLK => P4RDDATA[21]) = (100, 100); + ( P4CLK => P4RDDATA[22]) = (100, 100); + ( P4CLK => P4RDDATA[23]) = (100, 100); + ( P4CLK => P4RDDATA[24]) = (100, 100); + ( P4CLK => P4RDDATA[25]) = (100, 100); + ( P4CLK => P4RDDATA[26]) = (100, 100); + ( P4CLK => P4RDDATA[27]) = (100, 100); + ( P4CLK => P4RDDATA[28]) = (100, 100); + ( P4CLK => P4RDDATA[29]) = (100, 100); + ( P4CLK => P4RDDATA[2]) = (100, 100); + ( P4CLK => P4RDDATA[30]) = (100, 100); + ( P4CLK => P4RDDATA[31]) = (100, 100); + ( P4CLK => P4RDDATA[3]) = (100, 100); + ( P4CLK => P4RDDATA[4]) = (100, 100); + ( P4CLK => P4RDDATA[5]) = (100, 100); + ( P4CLK => P4RDDATA[6]) = (100, 100); + ( P4CLK => P4RDDATA[7]) = (100, 100); + ( P4CLK => P4RDDATA[8]) = (100, 100); + ( P4CLK => P4RDDATA[9]) = (100, 100); + ( P4CLK => P4RDOVERFLOW) = (100, 100); + ( P4CLK => P4WRUNDERRUN) = (100, 100); + ( P4CMDCLK => P4CMDEMPTY) = (100, 100); + ( P4CMDCLK => P4CMDFULL) = (100, 100); + ( P5CLK => P5COUNT[0]) = (100, 100); + ( P5CLK => P5COUNT[1]) = (100, 100); + ( P5CLK => P5COUNT[2]) = (100, 100); + ( P5CLK => P5COUNT[3]) = (100, 100); + ( P5CLK => P5COUNT[4]) = (100, 100); + ( P5CLK => P5COUNT[5]) = (100, 100); + ( P5CLK => P5COUNT[6]) = (100, 100); + ( P5CLK => P5EMPTY) = (100, 100); + ( P5CLK => P5ERROR) = (100, 100); + ( P5CLK => P5FULL) = (100, 100); + ( P5CLK => P5RDDATA[0]) = (100, 100); + ( P5CLK => P5RDDATA[10]) = (100, 100); + ( P5CLK => P5RDDATA[11]) = (100, 100); + ( P5CLK => P5RDDATA[12]) = (100, 100); + ( P5CLK => P5RDDATA[13]) = (100, 100); + ( P5CLK => P5RDDATA[14]) = (100, 100); + ( P5CLK => P5RDDATA[15]) = (100, 100); + ( P5CLK => P5RDDATA[16]) = (100, 100); + ( P5CLK => P5RDDATA[17]) = (100, 100); + ( P5CLK => P5RDDATA[18]) = (100, 100); + ( P5CLK => P5RDDATA[19]) = (100, 100); + ( P5CLK => P5RDDATA[1]) = (100, 100); + ( P5CLK => P5RDDATA[20]) = (100, 100); + ( P5CLK => P5RDDATA[21]) = (100, 100); + ( P5CLK => P5RDDATA[22]) = (100, 100); + ( P5CLK => P5RDDATA[23]) = (100, 100); + ( P5CLK => P5RDDATA[24]) = (100, 100); + ( P5CLK => P5RDDATA[25]) = (100, 100); + ( P5CLK => P5RDDATA[26]) = (100, 100); + ( P5CLK => P5RDDATA[27]) = (100, 100); + ( P5CLK => P5RDDATA[28]) = (100, 100); + ( P5CLK => P5RDDATA[29]) = (100, 100); + ( P5CLK => P5RDDATA[2]) = (100, 100); + ( P5CLK => P5RDDATA[30]) = (100, 100); + ( P5CLK => P5RDDATA[31]) = (100, 100); + ( P5CLK => P5RDDATA[3]) = (100, 100); + ( P5CLK => P5RDDATA[4]) = (100, 100); + ( P5CLK => P5RDDATA[5]) = (100, 100); + ( P5CLK => P5RDDATA[6]) = (100, 100); + ( P5CLK => P5RDDATA[7]) = (100, 100); + ( P5CLK => P5RDDATA[8]) = (100, 100); + ( P5CLK => P5RDDATA[9]) = (100, 100); + ( P5CLK => P5RDOVERFLOW) = (100, 100); + ( P5CLK => P5WRUNDERRUN) = (100, 100); + ( P5CMDCLK => P5CMDEMPTY) = (100, 100); + ( P5CMDCLK => P5CMDFULL) = (100, 100); + ( PLLCLK[1] => SELFREFRESHMODE) = (100, 100); + ( UICLK => IOIDRPADD) = (100, 100); + ( UICLK => IOIDRPADDR[0]) = (100, 100); + ( UICLK => IOIDRPADDR[1]) = (100, 100); + ( UICLK => IOIDRPADDR[2]) = (100, 100); + ( UICLK => IOIDRPADDR[3]) = (100, 100); + ( UICLK => IOIDRPADDR[4]) = (100, 100); + ( UICLK => IOIDRPBROADCAST) = (100, 100); + ( UICLK => IOIDRPCLK) = (0, 0); + ( UICLK => IOIDRPCS) = (100, 100); + ( UICLK => IOIDRPSDO) = (100, 100); + ( UICLK => IOIDRPUPDATE) = (100, 100); + ( UICLK => UOCALSTART) = (100, 100); + ( UICLK => UOCMDREADYIN) = (100, 100); + ( UICLK => UODATAVALID) = (100, 100); + ( UICLK => UODATA[0]) = (100, 100); + ( UICLK => UODATA[1]) = (100, 100); + ( UICLK => UODATA[2]) = (100, 100); + ( UICLK => UODATA[3]) = (100, 100); + ( UICLK => UODATA[4]) = (100, 100); + ( UICLK => UODATA[5]) = (100, 100); + ( UICLK => UODATA[6]) = (100, 100); + ( UICLK => UODATA[7]) = (100, 100); + ( UICLK => UODONECAL) = (100, 100); + ( UICLK => UOREFRSHFLAG) = (100, 100); + ( UICLK => UOSDO) = (100, 100); + + specparam PATHPULSE$ = 0; + endspecify + +endmodule diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/MMCM_ADV.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/MMCM_ADV.v new file mode 100644 index 0000000..a5e0d4d --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/MMCM_ADV.v @@ -0,0 +1,3331 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/blanc/MMCM_ADV.v,v 1.45.2.3 2010/05/20 20:41:23 yanx Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2010 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Function Simulation Library Component +// / / Phase Lock Loop Clock +// /___/ /\ Filename : MMCM_ADV.v +// \ \ / \ Timestamp : +// \___\/\___\ +// +// Revision: +// 07/07/08 - Initial version. +// 09/19/08 - Change CLKFBOUT_MULT to CLKFBOUT_MULT_F +// CLKOUT0_DIVIDE to CLKOUT0_DIVIDE_F +// 10/03/08 - Initial all signals. +// 10/30/08 - Clock source switching without reset (CR492263). +// 11/18/08 - Add timing check for DADDR[6:5]. +// 12/02/08 - Fix bug of Duty cycle calculation (CR498696) +// 12/05/08 - change pll_res according to hardware spreadsheet (CR496137) +// 12/09/08 - Enable output at CLKFBOUT_MULT_F*8 for fraction mode (CR499322) +// 01/08/09 - Add phase and duty cycle checks for fraction divide (CR501181) +// 01/09/09 - make pll_res same for BANDWIDTH=HIGH and OPTIMIZED (CR496137) +// 01/14/09 - Fine phase shift wrap around to 0 after 56 times; +// - PSEN to PSDONE change to 12 PSCLK; RST minpusle to 5ns; +// - add pulldown to PWRDWN pin. (CR503425) +// 01/14/09 - increase clkout_en_time for fraction mode (CR499322) +// 01/21/09 - align CLKFBOUT to CLKIN for fraction mode (CR504602) +// 01/27/09 - update DRP register address (CR505271) +// 01/28/09 - assign clkout_en0 and clkout_en1 to 0 when RST=1 (CR505767) +// 02/03/09 - Fix bug in clkfb fine phase shift. +// - Add delay to clkout_en0_tmp (CR506530). +// 02/05/09 - Add ps_in_ps calculation to clkvco_delay when clkfb_fps_en=1. +// - round clk_ht clk_lt for duty_cycle (CR506531) +// 02/11/09 - Change VCO_FREQ_MAX and MIN to 1601 and 399 to cover the rounded +// error (CR507969) +// 02/25/09 - round clk_ht clk_lt for duty_cycle (509386) +// 02/26/09 - Fix for clkin and clkfbin stop case (CR503425) +// 03/04/09 - Fix for CLOCK_HOLD (CR510820). +// 03/27/09 - set default 1 to CLKINSEL pin (CR516951) +// 04/13/09 - Check vco reange when CLKINSEL not connected (CR516951) +// 04/22/09 - Add reset to clkinstopped related signals (CR519102) +// 04/27/09 - Make duty cycle of fraction mode 50/50 (CR519505) +// 05/13/09 - Use period_avg for clkvco_delay calculation (CR521120) +// 07/23/09 - fix bug in clkout0_dly (CR527643) +// 07/27/09 - Do divide when period_avg > 0 (CR528090) +// - Change DIVCLK_DIVIDE to 80 (CR525904) +// - Add initial lock setting (CR524523) +// - Update RES CP setting (CR524522) +// 07/31/09 - Add if else to handle the fracion and nonfraction for clkout_en. +// 08/10/09 - Calculate clkin_lost_val after lock_period=1 (CR528520). +// 08/15/09 - Update LFHF (CR524522) +// 08/19/09 - Set clkfb_lost_val initial value (CR531354) +// 08/28/09 - add clkin_period_tmp_t to handle period_avg calculation +// when clkin has jitter (CR528520) +// 09/11/09 - Change CLKIN_FREQ_MIN to 10 Mhz (CR532774) +// 10/01/09 - Change CLKIN_FREQ_MAX to 800Mhz (CR535076) +// Add reset check for clock switchover (CR534900) +// 10/08/09 - Change CLKIN_FREQ MAX & MIN, CLKPFD_FREQ +// MAX & MIN to parameter (CR535828) +// 10/14/09 - Add clkin_chk_t1 and clkin_chk_t2 to handle check (CR535662) +// 10/22/09 - Add period_vco_mf for clkvco_delay calculation (CR536951) +// Add cmpvco to compensate period_vco rounded error (CR537073) +// 12/02/09 - not stop clkvco_lk when jitter (CR538717) +// 01/08/10 - Change minimum RST pulse width from 5 ns to 1.5 ns +// Add 1 ns delay to locked_out_tmp when RST=1 (CR543857) +// 01/19/10 - make change to clkvoc_lk_tmp to handle M=1 case (CR544970) +// 02/09/10 - Add global PLL_LOCKG (CR547918) +// 02/23/10 - Not use edge for locked_out_tmp (CR549667) +// 03/04/10 - Change CLKFBOUT_MULT_F range to 5-64 (CR551618) +// 03/22/10 - Change CLKFBOUT_MULT_F default to 5 (554618) +// 03/24/10 - Add SIM_DEVICE attribute +// 04/07/10 - Generate clkvco_ps_tmp2_en correctly when ps_lock_dly rising +// and clkout_ps=1 case; increase lock_period time to 10 (CR556468) +// 05/07/10 - Use period_vco_half_rm1 to reduce jitter (CR558966) +// End Revision + + +`timescale 1 ps / 1 ps + + +module MMCM_ADV ( + CLKFBOUT, + CLKFBOUTB, + CLKFBSTOPPED, + CLKINSTOPPED, + CLKOUT0, + CLKOUT0B, + CLKOUT1, + CLKOUT1B, + CLKOUT2, + CLKOUT2B, + CLKOUT3, + CLKOUT3B, + CLKOUT4, + CLKOUT5, + CLKOUT6, + DO, + DRDY, + LOCKED, + PSDONE, + CLKFBIN, + CLKIN1, + CLKIN2, + CLKINSEL, + DADDR, + DCLK, + DEN, + DI, + DWE, + PSCLK, + PSEN, + PSINCDEC, + PWRDWN, + RST +); + parameter BANDWIDTH = "OPTIMIZED"; + parameter CLKFBOUT_USE_FINE_PS = "FALSE"; + parameter CLKOUT0_USE_FINE_PS = "FALSE"; + parameter CLKOUT1_USE_FINE_PS = "FALSE"; + parameter CLKOUT2_USE_FINE_PS = "FALSE"; + parameter CLKOUT3_USE_FINE_PS = "FALSE"; + parameter CLKOUT4_CASCADE = "FALSE"; + parameter CLKOUT4_USE_FINE_PS = "FALSE"; + parameter CLKOUT5_USE_FINE_PS = "FALSE"; + parameter CLKOUT6_USE_FINE_PS = "FALSE"; + parameter CLOCK_HOLD = "FALSE"; + parameter COMPENSATION = "ZHOLD"; + parameter SIM_DEVICE = "VIRTEX6"; + parameter STARTUP_WAIT = "FALSE"; + parameter integer CLKOUT1_DIVIDE = 1; + parameter integer CLKOUT2_DIVIDE = 1; + parameter integer CLKOUT3_DIVIDE = 1; + parameter integer CLKOUT4_DIVIDE = 1; + parameter integer CLKOUT5_DIVIDE = 1; + parameter integer CLKOUT6_DIVIDE = 1; + parameter integer DIVCLK_DIVIDE = 1; + parameter real CLKFBOUT_MULT_F = 5.000; + parameter real CLKFBOUT_PHASE = 0.000; + parameter real CLKIN1_PERIOD = 0.000; + parameter real CLKIN2_PERIOD = 0.000; + parameter real CLKOUT0_DIVIDE_F = 1.000; + parameter real CLKOUT0_DUTY_CYCLE = 0.500; + parameter real CLKOUT0_PHASE = 0.000; + parameter real CLKOUT1_DUTY_CYCLE = 0.500; + parameter real CLKOUT1_PHASE = 0.000; + parameter real CLKOUT2_DUTY_CYCLE = 0.500; + parameter real CLKOUT2_PHASE = 0.000; + parameter real CLKOUT3_DUTY_CYCLE = 0.500; + parameter real CLKOUT3_PHASE = 0.000; + parameter real CLKOUT4_DUTY_CYCLE = 0.500; + parameter real CLKOUT4_PHASE = 0.000; + parameter real CLKOUT5_DUTY_CYCLE = 0.500; + parameter real CLKOUT5_PHASE = 0.000; + parameter real CLKOUT6_DUTY_CYCLE = 0.500; + parameter real CLKOUT6_PHASE = 0.000; + parameter real REF_JITTER1 = 0.010; + parameter real REF_JITTER2 = 0.010; + parameter real VCOCLK_FREQ_MAX = 1600.0; + parameter real VCOCLK_FREQ_MIN = 600.0; + parameter real CLKIN_FREQ_MAX = 800.0; + parameter real CLKIN_FREQ_MIN = 10.0; + parameter real CLKPFD_FREQ_MAX = 550.0; + parameter real CLKPFD_FREQ_MIN = 10.0; + + + + output CLKFBOUT; + output CLKFBOUTB; + output CLKFBSTOPPED; + output CLKINSTOPPED; + output CLKOUT0; + output CLKOUT0B; + output CLKOUT1; + output CLKOUT1B; + output CLKOUT2; + output CLKOUT2B; + output CLKOUT3; + output CLKOUT3B; + output CLKOUT4; + output CLKOUT5; + output CLKOUT6; + output DRDY; + output LOCKED; + output PSDONE; + output [15:0] DO; + + input CLKFBIN; + input CLKIN1; + input CLKIN2; + input CLKINSEL; + input DCLK; + input DEN; + input DWE; + input PSCLK; + input PSEN; + input PSINCDEC; + input PWRDWN; + input RST; + input [15:0] DI; + input [6:0] DADDR; + + localparam VCOCLK_FREQ_TARGET = 800; + localparam M_MIN = 5.000; + localparam M_MAX = 64.000; + localparam D_MIN = 1; + localparam D_MAX = 80; + localparam O_MIN = 1; + localparam O_MAX = 128; + localparam O_MAX_HT_LT = 64; + localparam REF_CLK_JITTER_MAX = 1000; + localparam REF_CLK_JITTER_SCALE = 0.1; + localparam MAX_FEEDBACK_DELAY = 10.0; + localparam MAX_FEEDBACK_DELAY_SCALE = 1.0; + localparam ps_max = 55; + localparam OSC_P2 = 250; + + tri0 GSR = glbl.GSR; + tri1 p_up; + wire glock; + + integer clkfb_div_frac_int, clk0_div_frac_int, clkfb_div_fint, clk0_div_fint; + integer clkfb_div_fint_tmp1, clkfb_div_fint_odd; + integer clk0_div_fint_tmp1, clk0_div_fint_odd; + real clkfb_div_frac, clk0_div_frac; + reg clk0_frac_out, clkfbm1_frac_out; + reg clk0_nf_out, clkfbm1_nf_out; + integer clk0_frac_en; + integer clkfb_frac_en; + integer ps_in_init; + reg psdone_out, psdone_out1; + integer clk0_fps_en, clk1_fps_en, clk2_fps_en, clk3_fps_en, clk4_fps_en; + integer clk5_fps_en, clk6_fps_en, clkfb_fps_en, fps_en; + reg clkinstopped_out, clkin_hold_f; + reg clkinstopped_out_dly = 0; + reg clkinstopped_out1 = 0; + reg clkfbstopped_out1 = 0; + reg clkfb_stop_tmp, clkfbstopped_out, clkin_stop_tmp; + reg rst_clkinstopped = 0, rst_clkfbstopped = 0, rst_clkinstopped_tm = 0; + reg rst_clkinstopped_rc = 0; + reg rst_clkinstopped_lk, rst_clkfbstopped_lk; + integer clkin_lost_cnt, clkfb_lost_cnt; + wire clkinstopped_hold; + integer ps_in_ps, ps_cnt; + integer ps_in_ps_neg, ps_cnt_neg; + reg clkout_ps, clkout_ps_tmp1, clkout_ps_tmp2; + time clkout_ps_eg = 0; + time clkout_ps_peg = 0; + time clkout_ps_w = 0; + reg clkvco_ps_tmp1, clkvco_ps_tmp2; + reg clkvco_ps_tmp2_en; + integer clkout4_cascade_int; + reg [6:0] daddr_lat; + reg valid_daddr; + reg drdy_out, drdy_out1; + reg drp_lock, drp_lock1; + reg [15:0] dr_sram [127:0]; + reg [160:0] tmp_string; + reg rst_in; + reg pwron_int; + wire orig_rst_in,rst_in_o; + wire locked_out; + reg locked_out1; + reg locked_out_tmp; + wire clk0_out, clkfbm1_out; + reg clk1_out, clk2_out, clk3_out, clk4_out, clk5_out; + reg clkfb_out; + reg clkout_en, clkout_en1, clkout_en0, clkout_en0_tmp, clkout_en0_tmp1; + integer clkout_en_val, clkout_en_t; + integer clkin_lock_cnt; + integer clkout_en_time, locked_en_time, lock_cnt_max; + integer pll_lock_time, lock_period_time; + reg clkvco_lk_osc, clkvco, clkvco_lk_tmp, clkvco_lk_tmp_en; + reg clkvco_ps_tmp2_pg; + reg clkvco_lk_dly_tmp; + reg clkvco_lk_en; + reg clkvco_lk; + reg fbclk_tmp; + reg clk_osc, clkin_p, clkfb_p; + reg clkinstopped_vco_f; + time rst_edge, rst_ht; + reg fb_delay_found, fb_delay_found_tmp; + reg clkfb_tst; + real fb_delay_max; + time fb_delay, clkvco_delay, val_tmp, dly_tmp, fbm1_comp_delay, fbm1_comp_delay_tmp; + time dly_tmp1, tmp_ps_val2; + integer dly_tmp_int, tmp_ps_val1; + time clkin_edge, delay_edge; + real period_clkin, clkin_period_tmp; + integer clkin_period_tmp_t; + integer clkin_period [4:0]; + integer period_vco, period_vco_half, period_vco_half1, period_vco_half_rm; + integer period_vco_half_rm1, period_vco_half_rm2; + real cmpvco = 0.0; + real clkvco_pdrm; + integer period_vco_mf; + integer period_vco_tmp; + integer period_vco_rm, period_vco_cmp_cnt, clkvco_rm_cnt; + integer period_vco_cmp_flag; + integer period_vco_max, period_vco_min; + integer period_vco1, period_vco2, period_vco3, period_vco4; + integer period_vco5, period_vco6, period_vco7; + integer period_vco_target, period_vco_target_half; + integer period_fb, period_avg; + integer clk0_frac_lt, clk0_frac_ht; + integer clkfb_frac_lt, clkfb_frac_ht; + integer period_ps, period_ps_old; + reg ps_lock, ps_lock_dly; + real clkvco_freq_init_chk, clkfbm1pm_rl; + real tmp_real; + integer ik0, ik1, ik2, ik3, ik4, ib, i, j; + integer md_product, m_product, m_product2, clkin_stop_max, clkfb_stop_max; + integer mf_product, clk0f_product; + integer clkin_lost_val, clkfb_lost_val, clkin_lost_val_lk; + time pll_locked_delay, clkin_dly_t, clkfb_dly_t; + wire pll_unlock, pll_unlock1; + reg pll_locked_tmp1, pll_locked_tmp2; + reg lock_period; + reg pll_locked_tm, unlock_recover; + reg clkpll_jitter_unlock; + integer clkin_jit, REF_CLK_JITTER_MAX_tmp; + wire init_trig, clkpll_r, clk0in, clk1in, clk2in, clk3in, clk4in, clk5in, clk6in; + reg clkpll_tmp1, clkpll; + wire clkfbm1in, clkfbm1ps_en; + reg chk_ok; + wire clk0ps_en, clk1ps_en, clk2ps_en, clk3ps_en, clk4ps_en, clk5ps_en, clk6ps_en; + reg [7:0] clkout_mux, clkout_ps_mux; + reg [2:0] clk0pm_sel, clk1pm_sel, clk2pm_sel, clk3pm_sel, clk4pm_sel, clk5pm_sel; + wire [2:0] clk0pm_sel1, clk5pm_sel1, clk6pm_sel1, clkfbm1pm_sel1; + reg [2:0] clk6pm_sel, clkfbm1pm_sel; + integer clk0pm_sel_int, clkfbm1pm_sel_int; + reg clk0_edge, clk1_edge, clk2_edge, clk3_edge, clk4_edge, clk5_edge, clk6_edge; + reg clkfbm1_edge, clkfbm2_edge, clkind_edge; + reg clk0_nocnt, clk1_nocnt, clk2_nocnt, clk3_nocnt, clk4_nocnt, clk5_nocnt; + reg clk6_nocnt, clkfbm1_nocnt, clkfbm2_nocnt, clkind_nocnt; + reg clkfbtmp_nocnti; + reg clkind_edgei, clkind_nocnti; + reg [5:0] clk0_dly_cnt, clkout0_dly; + reg [5:0] clk1_dly_cnt, clkout1_dly; + reg [5:0] clk2_dly_cnt, clkout2_dly; + reg [5:0] clk3_dly_cnt, clkout3_dly; + reg [5:0] clk4_dly_cnt, clkout4_dly; + reg [5:0] clk5_dly_cnt, clkout5_dly; + reg [5:0] clk6_dly_cnt, clkout6_dly; + reg [6:0] clk0_ht, clk0_lt; + reg [6:0] clk1_ht, clk1_lt; + reg [6:0] clk2_ht, clk2_lt; + reg [6:0] clk3_ht, clk3_lt; + reg [6:0] clk4_ht, clk4_lt; + reg [6:0] clk5_ht, clk5_lt; + reg [6:0] clk6_ht, clk6_lt; + reg [5:0] clkfbm1_dly_cnt, clkfbm1_dly; + reg [6:0] clkfbm1_ht, clkfbm1_lt; + reg [6:0] clkfbm2_ht, clkfbm2_lt; + reg [7:0] clkind_ht, clkind_lt; + reg [7:0] clkind_hti, clkind_lti; + reg [7:0] clk0_ht1, clk0_cnt, clk0_div, clk0_div1; + reg [7:0] clk1_ht1, clk1_cnt, clk1_div, clk1_div1; + reg [7:0] clk2_ht1, clk2_cnt, clk2_div, clk2_div1; + reg [7:0] clk3_ht1, clk3_cnt, clk3_div, clk3_div1; + reg [7:0] clk4_ht1, clk4_cnt, clk4_div, clk4_div1; + reg [7:0] clk5_ht1, clk5_cnt, clk5_div, clk5_div1; + reg [7:0] clk6_ht1, clk6_cnt, clk6_div, clk6_div1; + reg [7:0] clkfbm1_ht1, clkfbm1_cnt, clkfbm1_div, clkfbm1_div1; + real clkfbm1_f_div, clkfbm1_div_t; + integer clkfbm1_div_t_int; + reg [7:0] clkfbtmp_divi, clkfbtmp_hti, clkfbtmp_lti; + reg [7:0] clkfbm2_ht1, clkfbm2_cnt, clkfbm2_div, clkfbm2_div1; + reg [7:0] clkind_div, clkind_divi, clkind_div1, clkind_cnt, clkind_ht1; + reg clkind_out, clkind_out_tmp; + reg [3:0] pll_cp, pll_res; + reg [1:0] pll_lfhf; + reg [1:0] pll_cpres = 2'b01; + reg [4:0] drp_lock_ref_dly; + reg [4:0] drp_lock_fb_dly; + reg [9:0] drp_lock_cnt; + reg [9:0] drp_unlock_cnt; + reg [9:0] drp_lock_sat_high; + wire clkinsel_tmp; + real clkin_chk_t1, clkin_chk_t2; + reg init_chk; + reg rst_clkinsel_flag = 0; + reg clkout0_out, clkout1_out, clkout2_out, clkout3_out, clkout4_out; + reg clkout5_out, clkout6_out; + reg clkfbm2_out, clkfbm2_out_tmp, clk6_out; + reg notifier; + wire [15:0] do_out, di_in; + reg [15:0] do_out1; + wire clkin1_in, clkin2_in, clkfb_in, clkinsel_in, dwe_in, den_in, dclk_in; + wire clkinsel_in1; + wire psen_in, psclk_in, psincdec_in, pwrdwn_in; + wire pwrdwn_in1; + reg pwrdwn_in1_h = 0; + reg rst_input_r_h = 0; + reg pchk_clr = 0; + reg psincdec_chg = 0; + reg psincdec_chg_tmp = 0; + wire [6:0] daddr_in; + wire rst_input; + wire rst_input_r; + reg startup_wait_sig; + wire delay_PSINCDEC, delay_PSEN, delay_PSCLK, delay_DCLK, delay_DWE; + wire delay_DEN; + wire [15:0] delay_DI; + wire [6:0] delay_DADDR; + + + assign CLKINSTOPPED = clkinstopped_out1; + assign CLKFBSTOPPED = clkfbstopped_out1; + assign clkin1_in = CLKIN1; + assign clkin2_in = CLKIN2; + assign clkfb_in = CLKFBIN; + assign clkinsel_in = (CLKINSEL === 0) ? 0 : 1; + assign rst_input_r = RST; + assign daddr_in = DADDR; + assign di_in = DI; + assign dwe_in = DWE; + assign den_in = DEN; + assign dclk_in = DCLK; + assign psclk_in = PSCLK; + assign psen_in = PSEN; + assign psincdec_in = PSINCDEC; + assign pwrdwn_in = PWRDWN; + assign LOCKED = locked_out1; + assign DRDY = drdy_out1; + assign DO = do_out1; + assign PSDONE = psdone_out1; + + always @(locked_out_tmp) + locked_out1 = #100 locked_out_tmp; + always @(drdy_out) + drdy_out1 = #100 drdy_out; + always @(do_out) + do_out1 = #100 do_out; + always @(psdone_out) + psdone_out1 = #100 psdone_out; + + initial begin + #1; + if ($realtime == 0) begin + $display ("Simulator Resolution Error : Simulator resolution is set to a value greater than 1 ps."); + $display ("In order to simulate the MMCM_ADV, the simulator resolution must be set to 1ps or smaller."); + $finish; + end + end + + initial begin + case (STARTUP_WAIT) + "FALSE" : startup_wait_sig = 0; + "TRUE" : startup_wait_sig = 1; + default : begin + $display("Attribute Syntax Error : The Attribute STARTUP_WAIT on MMCM_ADV instance %m is set to %s. Legal values for this attribute are FALSE or TRUE.", STARTUP_WAIT); + $finish; + end + endcase + + case (BANDWIDTH) + "OPTIMIZED" : ; + "HIGH" : ; + "LOW" : ; + default : begin + $display("Attribute Syntax Error : The Attribute BANDWIDTH on MMCM_ADV instance %m is set to %s. Legal values for this attribute are OPTIMIZED, HIGH, or LOW.", BANDWIDTH); + $finish; + end + endcase + + case (CLKFBOUT_USE_FINE_PS) + "FALSE" : ; + "TRUE" : ; + default : begin + $display("Attribute Syntax Error : The Attribute CLKFBOUT_USE_FINE_PS on MMCM_ADV instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", CLKFBOUT_USE_FINE_PS); + $finish; + end + endcase + + case (CLKOUT0_USE_FINE_PS) + "FALSE" : ; + "TRUE" : ; + default : begin + $display("Attribute Syntax Error : The Attribute CLKOUT0_USE_FINE_PS on MMCM_ADV instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", CLKOUT0_USE_FINE_PS); + $finish; + end + endcase + + case (CLKOUT1_USE_FINE_PS) + "FALSE" : ; + "TRUE" : ; + default : begin + $display("Attribute Syntax Error : The Attribute CLKOUT1_USE_FINE_PS on MMCM_ADV instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", CLKOUT1_USE_FINE_PS); + $finish; + end + endcase + + case (CLKOUT2_USE_FINE_PS) + "FALSE" : ; + "TRUE" : ; + default : begin + $display("Attribute Syntax Error : The Attribute CLKOUT2_USE_FINE_PS on MMCM_ADV instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", CLKOUT2_USE_FINE_PS); + $finish; + end + endcase + + case (CLKOUT3_USE_FINE_PS) + "FALSE" : ; + "TRUE" : ; + default : begin + $display("Attribute Syntax Error : The Attribute CLKOUT3_USE_FINE_PS on MMCM_ADV instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", CLKOUT3_USE_FINE_PS); + $finish; + end + endcase + + case (CLKOUT4_USE_FINE_PS) + "FALSE" : ; + "TRUE" : ; + default : begin + $display("Attribute Syntax Error : The Attribute CLKOUT4_USE_FINE_PS on MMCM_ADV instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", CLKOUT4_USE_FINE_PS); + $finish; + end + endcase + + case (CLKOUT5_USE_FINE_PS) + "FALSE" : ; + "TRUE" : ; + default : begin + $display("Attribute Syntax Error : The Attribute CLKOUT5_USE_FINE_PS on MMCM_ADV instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", CLKOUT5_USE_FINE_PS); + $finish; + end + endcase + + case (CLKOUT6_USE_FINE_PS) + "FALSE" : ; + "TRUE" : ; + default : begin + $display("Attribute Syntax Error : The Attribute CLKOUT6_USE_FINE_PS on MMCM_ADV instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", CLKOUT6_USE_FINE_PS); + $finish; + end + endcase + + case (CLOCK_HOLD) + "FALSE" : clkin_hold_f = 0; + "TRUE" : clkin_hold_f = 1; + default : begin + $display("Attribute Syntax Error : The Attribute CLOCK_HOLD on MMCM_ADV instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", CLOCK_HOLD); + $finish; + end + endcase + + case (CLKOUT4_CASCADE) + "FALSE" : clkout4_cascade_int = 0; + "TRUE" : clkout4_cascade_int = 1; + default : begin + $display("Attribute Syntax Error : The Attribute CLKOUT4_CASCADE on MMCM_ADV instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", CLKOUT4_CASCADE); + $finish; + end + endcase + + case (COMPENSATION) + "ZHOLD" : ; + "BUF_IN" : ; + "CASCADE" : ; + "EXTERNAL" : ; + "INTERNAL" : ; + default : begin + $display("Attribute Syntax Error : The Attribute COMPENSATION on MMCM_ADV instance %m is set to %s. Legal values for this attribute are ZHOLD, BUF_IN, CASCADE, EXTERNAL, or INTERNAL.", COMPENSATION); + $finish; + end + endcase + + clkfbm1_f_div = CLKFBOUT_MULT_F; + clkfb_div_fint = $rtoi(CLKFBOUT_MULT_F); + clkfb_div_frac = CLKFBOUT_MULT_F - clkfb_div_fint; + if (clkfb_div_frac > 0.000) begin + clkfb_frac_en = 1; + clkfb_div_frac_int = $rtoi(clkfb_div_frac * 8); + clkfb_div_fint_tmp1 = clkfb_div_fint / 2; + clkfb_div_fint_odd = clkfb_div_fint - clkfb_div_fint_tmp1 -clkfb_div_fint_tmp1; + end + else begin + clkfb_frac_en = 0; + clkfb_div_frac_int = 0; + end +// mf_product = clkfb_div_fint * 8 + clkfb_div_frac_int; + clk0_div_fint = $rtoi(CLKOUT0_DIVIDE_F); + clk0_div_frac = CLKOUT0_DIVIDE_F - clk0_div_fint; + if (clk0_div_frac > 0.000) begin + clk0_frac_en = 1; + clk0_div_frac_int = $rtoi(clk0_div_frac * 8); + clk0_div_fint_tmp1 = clk0_div_fint / 2; + clk0_div_fint_odd = clk0_div_fint - clk0_div_fint_tmp1 -clk0_div_fint_tmp1; + end + else begin + clk0_frac_en = 0; + clk0_div_frac_int = 0; + end + ps_in_init = 0; + ps_in_ps = ps_in_init; + ps_cnt = 0; + + if (CLKFBOUT_USE_FINE_PS == "TRUE") begin + if (clkfb_frac_en == 1) begin + $display("Attribute Syntax Error : The Attribute CLKFBOUT_USE_FINE_PS on MMCM_ADV instance %m is set to %s. This attribute should be set to FALSE when CLKFBOUT_MULT_F has fraction part.", CLKFBOUT_USE_FINE_PS); + $finish; + end + else + clkfb_fps_en = 1; + end + else + clkfb_fps_en = 0; + + if (CLKOUT0_USE_FINE_PS == "TRUE") begin + if (clk0_frac_en == 1) begin + $display("Attribute Syntax Error : The Attribute CLKOUT0_USE_FINE_PS on MMCM_ADV instance %m is set to %s. This attribute should be set to FALSE when CLKOUT0_DIVIDE has fraction part.", CLKOUT0_USE_FINE_PS); + $finish; + end + else + clk0_fps_en = 1; + end + else + clk0_fps_en = 0; + + if (CLKOUT1_USE_FINE_PS == "TRUE") + clk1_fps_en = 1; + else + clk1_fps_en = 0; + + if (CLKOUT2_USE_FINE_PS == "TRUE") + clk2_fps_en = 1; + else + clk2_fps_en = 0; + + if (CLKOUT3_USE_FINE_PS == "TRUE") + clk3_fps_en = 1; + else + clk3_fps_en = 0; + + if (CLKOUT4_USE_FINE_PS == "TRUE") + clk4_fps_en = 1; + else + clk4_fps_en = 0; + + if (CLKOUT5_USE_FINE_PS == "TRUE") + clk5_fps_en = 1; + else + clk5_fps_en = 0; + + if (CLKOUT6_USE_FINE_PS == "TRUE") + clk6_fps_en = 1; + else + clk6_fps_en = 0; + + + fps_en = clk0_fps_en || clk1_fps_en || clk2_fps_en || clk3_fps_en + || clk4_fps_en || clk5_fps_en || clk6_fps_en || clkfb_fps_en; + + tmp_string = "CLKOUT0_DIVIDE_F"; + chk_ok = para_real_range_chk(CLKOUT0_DIVIDE_F, tmp_string, 1.000, 128.000); + tmp_string = "CLKOUT0_PHASE"; + if (clk0_frac_en == 0) + chk_ok = para_real_range_chk(CLKOUT0_PHASE, tmp_string, -360.0, 360.0); + else + if (CLKOUT0_PHASE != 0.0) begin + $display("Attribute Syntax Error : The Attribute CLKOUT0_PHASE on MMCM_ADV instance %m is set to %f. This attribute should be set to 0.0 when CLKOUT0_DIVIDE_F has fraction part.", CLKOUT0_PHASE); + $finish; + end + tmp_string = "CLKOUT0_DUTY_CYCLE"; + if (clk0_frac_en == 0) + chk_ok = para_real_range_chk(CLKOUT0_DUTY_CYCLE, tmp_string, 0.001, 0.999); + else + if (CLKOUT0_DUTY_CYCLE != 0.5) begin + $display("Attribute Syntax Error : The Attribute CLKOUT0_DUTY_CYCLE on MMCM_ADV instance %m is set to %f. This attribute should be set to 0.5 when CLKOUT0_DIVIDE_F has fraction part.", CLKOUT0_DUTY_CYCLE); + $finish; + end + tmp_string = "CLKOUT1_DIVIDE"; + chk_ok = para_int_range_chk(CLKOUT1_DIVIDE, tmp_string, 1, 128); + tmp_string = "CLKOUT1_PHASE"; + chk_ok = para_real_range_chk(CLKOUT1_PHASE, tmp_string, -360.0, 360.0); + tmp_string = "CLKOUT1_DUTY_CYCLE"; + chk_ok = para_real_range_chk(CLKOUT1_DUTY_CYCLE, tmp_string, 0.001, 0.999); + tmp_string = "CLKOUT2_DIVIDE"; + chk_ok = para_int_range_chk(CLKOUT2_DIVIDE, tmp_string, 1, 128); + tmp_string = "CLKOUT2_PHASE"; + chk_ok = para_real_range_chk(CLKOUT2_PHASE, tmp_string, -360.0, 360.0); + tmp_string = "CLKOUT2_DUTY_CYCLE"; + chk_ok = para_real_range_chk(CLKOUT2_DUTY_CYCLE, tmp_string, 0.001, 0.999); + tmp_string = "CLKOUT3_DIVIDE"; + chk_ok = para_int_range_chk(CLKOUT3_DIVIDE, tmp_string, 1, 128); + tmp_string = "CLKOUT3_PHASE"; + chk_ok = para_real_range_chk(CLKOUT3_PHASE, tmp_string, -360.0, 360.0); + tmp_string = "CLKOUT3_DUTY_CYCLE"; + chk_ok = para_real_range_chk(CLKOUT3_DUTY_CYCLE, tmp_string, 0.001, 0.999); + tmp_string = "CLKOUT4_DIVIDE"; + chk_ok = para_int_range_chk(CLKOUT4_DIVIDE, tmp_string, 1, 128); + tmp_string = "CLKOUT4_PHASE"; + chk_ok = para_real_range_chk(CLKOUT4_PHASE, tmp_string, -360.0, 360.0); + tmp_string = "CLKOUT4_DUTY_CYCLE"; + chk_ok = para_real_range_chk(CLKOUT4_DUTY_CYCLE, tmp_string, 0.001, 0.999); + if (clk0_frac_en == 0) begin + tmp_string = "CLKOUT5_DIVIDE"; + chk_ok = para_int_range_chk (CLKOUT5_DIVIDE, tmp_string, 1, 128); + tmp_string = "CLKOUT5_PHASE"; + chk_ok = para_real_range_chk(CLKOUT5_PHASE, tmp_string, -360.0, 360.0); + tmp_string = "CLKOUT5_DUTY_CYCLE"; + chk_ok = para_real_range_chk (CLKOUT5_DUTY_CYCLE, tmp_string, 0.001, 0.999); + end + if (clkfb_frac_en == 0) begin + tmp_string = "CLKOUT6_DIVIDE"; + chk_ok = para_int_range_chk (CLKOUT6_DIVIDE, tmp_string, 1, 128); + tmp_string = "CLKOUT6_PHASE"; + chk_ok = para_real_range_chk(CLKOUT6_PHASE, tmp_string, -360.0, 360.0); + tmp_string = "CLKOUT6_DUTY_CYCLE"; + chk_ok = para_real_range_chk (CLKOUT6_DUTY_CYCLE, tmp_string, 0.001, 0.999); + end + tmp_string = "CLKFBOUT_MULT_F"; +// chk_ok = para_real_range_chk(CLKFBOUT_MULT_F, tmp_string, 1.000, 64.000); + if (SIM_DEVICE == "VIRTEX6") + chk_ok = para_real_range_chk(CLKFBOUT_MULT_F, tmp_string, 5.000, 64.000); + else + chk_ok = para_real_range_chk(CLKFBOUT_MULT_F, tmp_string, 2.000, 64.000); + tmp_string = "CLKFBOUT_PHASE"; + if (clkfb_frac_en == 0) + chk_ok = para_real_range_chk(CLKFBOUT_PHASE, tmp_string, -360.0, 360.0); + else + if (CLKFBOUT_PHASE != 0.0) begin + $display("Attribute Syntax Error : The Attribute CLKFBOUT_PHASE on MMCM_ADV instance %m is set to %f. This attribute should be set to 0.0 when CLKFBOUT_MULT_F has fraction part.", CLKFBOUT_PHASE); + $finish; + end + tmp_string = "DIVCLK_DIVIDE"; + chk_ok = para_int_range_chk (DIVCLK_DIVIDE, tmp_string, 1, D_MAX); + tmp_string = "REF_JITTER1"; + chk_ok = para_real_range_chk (REF_JITTER1, tmp_string, 0.000, 0.999); + tmp_string = "REF_JITTER2"; + chk_ok = para_real_range_chk (REF_JITTER2, tmp_string, 0.000, 0.999); + + if (BANDWIDTH === "LOW") + pll_lfhf = 2'b11; + else + pll_lfhf = 2'b00; + + if (BANDWIDTH === "LOW") + case (clkfb_div_fint) + 1 : begin pll_cp = 4'b0001; pll_res = 4'b0111; end + 2 : begin pll_cp = 4'b0001; pll_res = 4'b0101; end + 3 : begin pll_cp = 4'b0001; pll_res = 4'b1110; end + 4 : begin pll_cp = 4'b0001; pll_res = 4'b0110; end + 5 : begin pll_cp = 4'b0001; pll_res = 4'b1010; end + 6 : begin pll_cp = 4'b0001; pll_res = 4'b1100; end + 7 : begin pll_cp = 4'b0001; pll_res = 4'b1100; end + 8 : begin pll_cp = 4'b0001; pll_res = 4'b1100; end + 9 : begin pll_cp = 4'b0001; pll_res = 4'b1100; end + 10 : begin pll_cp = 4'b0001; pll_res = 4'b0010; end + 11 : begin pll_cp = 4'b0001; pll_res = 4'b0010; end + 12 : begin pll_cp = 4'b0001; pll_res = 4'b0010; end + 13 : begin pll_cp = 4'b0010; pll_res = 4'b1100; end + 14 : begin pll_cp = 4'b0001; pll_res = 4'b0100; end + 15 : begin pll_cp = 4'b0001; pll_res = 4'b0100; end + 16 : begin pll_cp = 4'b0001; pll_res = 4'b0100; end + 17 : begin pll_cp = 4'b0001; pll_res = 4'b0100; end + 18 : begin pll_cp = 4'b0001; pll_res = 4'b0100; end + 19 : begin pll_cp = 4'b0001; pll_res = 4'b0100; end + 20 : begin pll_cp = 4'b0001; pll_res = 4'b0100; end + 21 : begin pll_cp = 4'b0001; pll_res = 4'b0100; end + 22 : begin pll_cp = 4'b0001; pll_res = 4'b0100; end + 23 : begin pll_cp = 4'b0001; pll_res = 4'b0100; end + 24 : begin pll_cp = 4'b0001; pll_res = 4'b1000; end + 25 : begin pll_cp = 4'b0001; pll_res = 4'b1000; end + 26 : begin pll_cp = 4'b0001; pll_res = 4'b1000; end + 27 : begin pll_cp = 4'b0001; pll_res = 4'b1000; end + 28 : begin pll_cp = 4'b0001; pll_res = 4'b1000; end + 29 : begin pll_cp = 4'b0001; pll_res = 4'b1000; end + 30 : begin pll_cp = 4'b0001; pll_res = 4'b1000; end + 31 : begin pll_cp = 4'b0001; pll_res = 4'b1000; end + 32 : begin pll_cp = 4'b0001; pll_res = 4'b1000; end + 33 : begin pll_cp = 4'b0001; pll_res = 4'b1000; end + 34 : begin pll_cp = 4'b0001; pll_res = 4'b1000; end + 35 : begin pll_cp = 4'b0001; pll_res = 4'b1000; end + 36 : begin pll_cp = 4'b0001; pll_res = 4'b1000; end + 37 : begin pll_cp = 4'b0001; pll_res = 4'b1000; end + 38 : begin pll_cp = 4'b0010; pll_res = 4'b0100; end + 39 : begin pll_cp = 4'b0010; pll_res = 4'b0100; end + 40 : begin pll_cp = 4'b0010; pll_res = 4'b0100; end + 41 : begin pll_cp = 4'b0010; pll_res = 4'b0100; end + 42 : begin pll_cp = 4'b0010; pll_res = 4'b0100; end + 43 : begin pll_cp = 4'b0010; pll_res = 4'b0100; end + 44 : begin pll_cp = 4'b0010; pll_res = 4'b0100; end + 45 : begin pll_cp = 4'b0010; pll_res = 4'b0100; end + 46 : begin pll_cp = 4'b0010; pll_res = 4'b0100; end + 47 : begin pll_cp = 4'b0010; pll_res = 4'b0100; end + 48 : begin pll_cp = 4'b0010; pll_res = 4'b1000; end + 49 : begin pll_cp = 4'b0010; pll_res = 4'b1000; end + 50 : begin pll_cp = 4'b0010; pll_res = 4'b1000; end + 51 : begin pll_cp = 4'b0010; pll_res = 4'b1000; end + 52 : begin pll_cp = 4'b0010; pll_res = 4'b1000; end + 53 : begin pll_cp = 4'b0010; pll_res = 4'b1000; end + 54 : begin pll_cp = 4'b0010; pll_res = 4'b1000; end + 55 : begin pll_cp = 4'b0010; pll_res = 4'b1000; end + 56 : begin pll_cp = 4'b0010; pll_res = 4'b1000; end + 57 : begin pll_cp = 4'b0010; pll_res = 4'b1000; end + 58 : begin pll_cp = 4'b0010; pll_res = 4'b1000; end + 59 : begin pll_cp = 4'b0010; pll_res = 4'b1000; end + 60 : begin pll_cp = 4'b0010; pll_res = 4'b1000; end + 61 : begin pll_cp = 4'b0010; pll_res = 4'b1000; end + 62 : begin pll_cp = 4'b0010; pll_res = 4'b1000; end + 63 : begin pll_cp = 4'b0010; pll_res = 4'b1000; end + 64 : begin pll_cp = 4'b0010; pll_res = 4'b1000; end + endcase + else if (BANDWIDTH === "HIGH") + case (clkfb_div_fint) + 1 : begin pll_cp = 4'b0101; pll_res = 4'b1111; end + 2 : begin pll_cp = 4'b1111; pll_res = 4'b1111; end + 3 : begin pll_cp = 4'b1111; pll_res = 4'b1101; end + 4 : begin pll_cp = 4'b1111; pll_res = 4'b1001; end + 5 : begin pll_cp = 4'b1111; pll_res = 4'b1110; end + 6 : begin pll_cp = 4'b1111; pll_res = 4'b0001; end + 7 : begin pll_cp = 4'b1111; pll_res = 4'b0001; end + 8 : begin pll_cp = 4'b1111; pll_res = 4'b0110; end + 9 : begin pll_cp = 4'b1111; pll_res = 4'b1010; end + 10 : begin pll_cp = 4'b1111; pll_res = 4'b1010; end + 11 : begin pll_cp = 4'b1111; pll_res = 4'b1010; end + 12 : begin pll_cp = 4'b1110; pll_res = 4'b1100; end + 13 : begin pll_cp = 4'b1111; pll_res = 4'b1100; end + 14 : begin pll_cp = 4'b1111; pll_res = 4'b1100; end + 15 : begin pll_cp = 4'b1111; pll_res = 4'b1100; end + 16 : begin pll_cp = 4'b1111; pll_res = 4'b1100; end + 17 : begin pll_cp = 4'b1111; pll_res = 4'b1100; end + 18 : begin pll_cp = 4'b1111; pll_res = 4'b1100; end + 19 : begin pll_cp = 4'b1111; pll_res = 4'b1100; end + 20 : begin pll_cp = 4'b1111; pll_res = 4'b1100; end + 21 : begin pll_cp = 4'b1110; pll_res = 4'b1100; end + 22 : begin pll_cp = 4'b1110; pll_res = 4'b1100; end + 23 : begin pll_cp = 4'b1110; pll_res = 4'b1100; end + 24 : begin pll_cp = 4'b1111; pll_res = 4'b1010; end + 25 : begin pll_cp = 4'b1101; pll_res = 4'b1100; end + 26 : begin pll_cp = 4'b1100; pll_res = 4'b0010; end + 27 : begin pll_cp = 4'b1101; pll_res = 4'b1100; end + 28 : begin pll_cp = 4'b1101; pll_res = 4'b1100; end + 29 : begin pll_cp = 4'b1111; pll_res = 4'b1010; end + 30 : begin pll_cp = 4'b1111; pll_res = 4'b1010; end + 31 : begin pll_cp = 4'b1111; pll_res = 4'b1010; end + 32 : begin pll_cp = 4'b0111; pll_res = 4'b0010; end + 33 : begin pll_cp = 4'b1100; pll_res = 4'b1100; end + 34 : begin pll_cp = 4'b1100; pll_res = 4'b1100; end + 35 : begin pll_cp = 4'b1110; pll_res = 4'b1010; end + 36 : begin pll_cp = 4'b0110; pll_res = 4'b0010; end + 37 : begin pll_cp = 4'b0110; pll_res = 4'b0010; end + 38 : begin pll_cp = 4'b0110; pll_res = 4'b0010; end + 39 : begin pll_cp = 4'b0111; pll_res = 4'b1100; end + 40 : begin pll_cp = 4'b0110; pll_res = 4'b0010; end + 41 : begin pll_cp = 4'b0100; pll_res = 4'b0100; end + 42 : begin pll_cp = 4'b0100; pll_res = 4'b0100; end + 43 : begin pll_cp = 4'b0100; pll_res = 4'b0100; end + 44 : begin pll_cp = 4'b0100; pll_res = 4'b0100; end + 45 : begin pll_cp = 4'b0100; pll_res = 4'b0100; end + 46 : begin pll_cp = 4'b0100; pll_res = 4'b0100; end + 47 : begin pll_cp = 4'b0011; pll_res = 4'b1000; end + 48 : begin pll_cp = 4'b0011; pll_res = 4'b1000; end + 49 : begin pll_cp = 4'b0011; pll_res = 4'b1000; end + 50 : begin pll_cp = 4'b0011; pll_res = 4'b1000; end + 51 : begin pll_cp = 4'b0011; pll_res = 4'b1000; end + 52 : begin pll_cp = 4'b0011; pll_res = 4'b1000; end + 53 : begin pll_cp = 4'b0011; pll_res = 4'b1000; end + 54 : begin pll_cp = 4'b0011; pll_res = 4'b1000; end + 55 : begin pll_cp = 4'b0011; pll_res = 4'b1000; end + 56 : begin pll_cp = 4'b0011; pll_res = 4'b1000; end + 57 : begin pll_cp = 4'b0011; pll_res = 4'b1000; end + 58 : begin pll_cp = 4'b0011; pll_res = 4'b1000; end + 59 : begin pll_cp = 4'b0011; pll_res = 4'b1000; end + 60 : begin pll_cp = 4'b0011; pll_res = 4'b1000; end + 61 : begin pll_cp = 4'b0011; pll_res = 4'b1000; end + 62 : begin pll_cp = 4'b0011; pll_res = 4'b1000; end + 63 : begin pll_cp = 4'b0011; pll_res = 4'b1000; end + 64 : begin pll_cp = 4'b0011; pll_res = 4'b1000; end + endcase + else if (BANDWIDTH === "OPTIMIZED") + case (clkfb_div_fint) + 1 : begin pll_cp = 4'b0101; pll_res = 4'b1111; end + 2 : begin pll_cp = 4'b1111; pll_res = 4'b1111; end + 3 : begin pll_cp = 4'b1111; pll_res = 4'b1101; end + 4 : begin pll_cp = 4'b1111; pll_res = 4'b1001; end + 5 : begin pll_cp = 4'b1111; pll_res = 4'b1110; end + 6 : begin pll_cp = 4'b1111; pll_res = 4'b0001; end + 7 : begin pll_cp = 4'b1111; pll_res = 4'b0001; end + 8 : begin pll_cp = 4'b1111; pll_res = 4'b0110; end + 9 : begin pll_cp = 4'b1111; pll_res = 4'b1010; end + 10 : begin pll_cp = 4'b1111; pll_res = 4'b1010; end + 11 : begin pll_cp = 4'b1111; pll_res = 4'b1010; end + 12 : begin pll_cp = 4'b1110; pll_res = 4'b1100; end + 13 : begin pll_cp = 4'b1111; pll_res = 4'b1100; end + 14 : begin pll_cp = 4'b1111; pll_res = 4'b1100; end + 15 : begin pll_cp = 4'b1111; pll_res = 4'b1100; end + 16 : begin pll_cp = 4'b1111; pll_res = 4'b1100; end + 17 : begin pll_cp = 4'b1111; pll_res = 4'b1100; end + 18 : begin pll_cp = 4'b1111; pll_res = 4'b1100; end + 19 : begin pll_cp = 4'b1111; pll_res = 4'b1100; end + 20 : begin pll_cp = 4'b1111; pll_res = 4'b1100; end + 21 : begin pll_cp = 4'b1110; pll_res = 4'b1100; end + 22 : begin pll_cp = 4'b1110; pll_res = 4'b1100; end + 23 : begin pll_cp = 4'b1110; pll_res = 4'b1100; end + 24 : begin pll_cp = 4'b1111; pll_res = 4'b1010; end + 25 : begin pll_cp = 4'b1101; pll_res = 4'b1100; end + 26 : begin pll_cp = 4'b1100; pll_res = 4'b0010; end + 27 : begin pll_cp = 4'b1101; pll_res = 4'b1100; end + 28 : begin pll_cp = 4'b1101; pll_res = 4'b1100; end + 29 : begin pll_cp = 4'b1111; pll_res = 4'b1010; end + 30 : begin pll_cp = 4'b1111; pll_res = 4'b1010; end + 31 : begin pll_cp = 4'b1111; pll_res = 4'b1010; end + 32 : begin pll_cp = 4'b0111; pll_res = 4'b0010; end + 33 : begin pll_cp = 4'b1100; pll_res = 4'b1100; end + 34 : begin pll_cp = 4'b1100; pll_res = 4'b1100; end + 35 : begin pll_cp = 4'b1110; pll_res = 4'b1010; end + 36 : begin pll_cp = 4'b0110; pll_res = 4'b0010; end + 37 : begin pll_cp = 4'b0110; pll_res = 4'b0010; end + 38 : begin pll_cp = 4'b0110; pll_res = 4'b0010; end + 39 : begin pll_cp = 4'b0111; pll_res = 4'b1100; end + 40 : begin pll_cp = 4'b0110; pll_res = 4'b0010; end + 41 : begin pll_cp = 4'b0100; pll_res = 4'b0100; end + 42 : begin pll_cp = 4'b0100; pll_res = 4'b0100; end + 43 : begin pll_cp = 4'b0100; pll_res = 4'b0100; end + 44 : begin pll_cp = 4'b0100; pll_res = 4'b0100; end + 45 : begin pll_cp = 4'b0100; pll_res = 4'b0100; end + 46 : begin pll_cp = 4'b0100; pll_res = 4'b0100; end + 47 : begin pll_cp = 4'b0011; pll_res = 4'b1000; end + 48 : begin pll_cp = 4'b0011; pll_res = 4'b1000; end + 49 : begin pll_cp = 4'b0011; pll_res = 4'b1000; end + 50 : begin pll_cp = 4'b0011; pll_res = 4'b1000; end + 51 : begin pll_cp = 4'b0011; pll_res = 4'b1000; end + 52 : begin pll_cp = 4'b0011; pll_res = 4'b1000; end + 53 : begin pll_cp = 4'b0011; pll_res = 4'b1000; end + 54 : begin pll_cp = 4'b0011; pll_res = 4'b1000; end + 55 : begin pll_cp = 4'b0011; pll_res = 4'b1000; end + 56 : begin pll_cp = 4'b0011; pll_res = 4'b1000; end + 57 : begin pll_cp = 4'b0011; pll_res = 4'b1000; end + 58 : begin pll_cp = 4'b0011; pll_res = 4'b1000; end + 59 : begin pll_cp = 4'b0011; pll_res = 4'b1000; end + 60 : begin pll_cp = 4'b0011; pll_res = 4'b1000; end + 61 : begin pll_cp = 4'b0011; pll_res = 4'b1000; end + 62 : begin pll_cp = 4'b0011; pll_res = 4'b1000; end + 63 : begin pll_cp = 4'b0011; pll_res = 4'b1000; end + 64 : begin pll_cp = 4'b0011; pll_res = 4'b1000; end + endcase +/* + case (clkfb_div_fint) +1 : if (BANDWIDTH === "HIGH" || BANDWIDTH === "OPTIMIZED") begin pll_cp = 4'b0010; pll_res = 4'b1011; end + else if (BANDWIDTH === "LOW") begin pll_cp = 4'b0001; pll_res = 4'b1101; end +2 : if (BANDWIDTH === "HIGH" || BANDWIDTH === "OPTIMIZED") begin pll_cp = 4'b0101; pll_res = 4'b1111; end + else if (BANDWIDTH === "LOW") begin pll_cp = 4'b0001; pll_res = 4'b1110; end +3 : if (BANDWIDTH === "HIGH" || BANDWIDTH === "OPTIMIZED") begin pll_cp = 4'b1100; pll_res = 4'b1111; end + else if (BANDWIDTH === "LOW") begin pll_cp = 4'b0001; pll_res = 4'b0110; end +4 : if (BANDWIDTH === "HIGH" || BANDWIDTH === "OPTIMIZED") begin pll_cp = 4'b1111; pll_res = 4'b1111; end + else if (BANDWIDTH === "LOW") begin pll_cp = 4'b0001; pll_res = 4'b1010; end +5 : if (BANDWIDTH === "HIGH" || BANDWIDTH === "OPTIMIZED") begin pll_cp = 4'b1111; pll_res = 4'b0111; end + else if (BANDWIDTH === "LOW") begin pll_cp = 4'b0001; pll_res = 4'b1100; end +6 : if (BANDWIDTH === "HIGH" || BANDWIDTH === "OPTIMIZED") begin pll_cp = 4'b1111; pll_res = 4'b1101; end + else if (BANDWIDTH === "LOW") begin pll_cp = 4'b0001; pll_res = 4'b1100; end +7 : if (BANDWIDTH === "HIGH" || BANDWIDTH === "OPTIMIZED") begin pll_cp = 4'b1111; pll_res = 4'b0011; end + else if (BANDWIDTH === "LOW") begin pll_cp = 4'b0001; pll_res = 4'b1100; end +8 : if (BANDWIDTH === "HIGH" || BANDWIDTH === "OPTIMIZED") begin pll_cp = 4'b1111; pll_res = 4'b0101; end + else if (BANDWIDTH === "LOW") begin pll_cp = 4'b0001; pll_res = 4'b0010; end +9 : if (BANDWIDTH === "HIGH" || BANDWIDTH === "OPTIMIZED") begin pll_cp = 4'b1111; pll_res = 4'b1001; end + else if (BANDWIDTH === "LOW") begin pll_cp = 4'b0001; pll_res = 4'b0010; end +10 : if (BANDWIDTH === "HIGH" || BANDWIDTH === "OPTIMIZED") begin pll_cp = 4'b1110; pll_res = 4'b1110; end + else if (BANDWIDTH === "LOW") begin pll_cp = 4'b0001; pll_res = 4'b0100; end +11 : if (BANDWIDTH === "HIGH" || BANDWIDTH === "OPTIMIZED") begin pll_cp = 4'b1111; pll_res = 4'b1110; end + else if (BANDWIDTH === "LOW") begin pll_cp = 4'b0001; pll_res = 4'b0100; end +12 : if (BANDWIDTH === "HIGH" || BANDWIDTH === "OPTIMIZED") begin pll_cp = 4'b1111; pll_res = 4'b1110; end + else if (BANDWIDTH === "LOW") begin pll_cp = 4'b0001; pll_res = 4'b0100; end +13 : if (BANDWIDTH === "HIGH" || BANDWIDTH === "OPTIMIZED") begin pll_cp = 4'b1111; pll_res = 4'b0001; end + else if (BANDWIDTH === "LOW") begin pll_cp = 4'b0001; pll_res = 4'b0100; end +14 : if (BANDWIDTH === "HIGH" || BANDWIDTH === "OPTIMIZED") begin pll_cp = 4'b1111; pll_res = 4'b0001; end + else if (BANDWIDTH === "LOW") begin pll_cp = 4'b0001; pll_res = 4'b0100; end +15 : if (BANDWIDTH === "HIGH" || BANDWIDTH === "OPTIMIZED") begin pll_cp = 4'b1111; pll_res = 4'b0001; end + else if (BANDWIDTH === "LOW") begin pll_cp = 4'b0001; pll_res = 4'b0100; end +16 : if (BANDWIDTH === "HIGH" || BANDWIDTH === "OPTIMIZED") begin pll_cp = 4'b1110; pll_res = 4'b0110; end + else if (BANDWIDTH === "LOW") begin pll_cp = 4'b0001; pll_res = 4'b0100; end +17 : if (BANDWIDTH === "HIGH" || BANDWIDTH === "OPTIMIZED") begin pll_cp = 4'b1110; pll_res = 4'b0110; end + else if (BANDWIDTH === "LOW") begin pll_cp = 4'b0001; pll_res = 4'b0100; end +18 : if (BANDWIDTH === "HIGH" || BANDWIDTH === "OPTIMIZED") begin pll_cp = 4'b1111; pll_res = 4'b0110; end + else if (BANDWIDTH === "LOW") begin pll_cp = 4'b0001; pll_res = 4'b0100; end +19 : if (BANDWIDTH === "HIGH" || BANDWIDTH === "OPTIMIZED") begin pll_cp = 4'b1110; pll_res = 4'b1010; end + else if (BANDWIDTH === "LOW") begin pll_cp = 4'b0001; pll_res = 4'b1000; end +20 : if (BANDWIDTH === "HIGH" || BANDWIDTH === "OPTIMIZED") begin pll_cp = 4'b1110; pll_res = 4'b1010; end + else if (BANDWIDTH === "LOW") begin pll_cp = 4'b0001; pll_res = 4'b1000; end +21 : if (BANDWIDTH === "HIGH" || BANDWIDTH === "OPTIMIZED") begin pll_cp = 4'b1111; pll_res = 4'b1010; end + else if (BANDWIDTH === "LOW") begin pll_cp = 4'b0001; pll_res = 4'b1000; end +22 : if (BANDWIDTH === "HIGH" || BANDWIDTH === "OPTIMIZED") begin pll_cp = 4'b1111; pll_res = 4'b1010; end + else if (BANDWIDTH === "LOW") begin pll_cp = 4'b0001; pll_res = 4'b1000; end +23 : if (BANDWIDTH === "HIGH" || BANDWIDTH === "OPTIMIZED") begin pll_cp = 4'b1111; pll_res = 4'b1010; end + else if (BANDWIDTH === "LOW") begin pll_cp = 4'b0001; pll_res = 4'b1000; end +24 : if (BANDWIDTH === "HIGH" || BANDWIDTH === "OPTIMIZED") begin pll_cp = 4'b1111; pll_res = 4'b1010; end + else if (BANDWIDTH === "LOW") begin pll_cp = 4'b0001; pll_res = 4'b1000; end +25 : if (BANDWIDTH === "HIGH" || BANDWIDTH === "OPTIMIZED") begin pll_cp = 4'b1111; pll_res = 4'b1010; end + else if (BANDWIDTH === "LOW") begin pll_cp = 4'b0001; pll_res = 4'b1000; end +26 : if (BANDWIDTH === "HIGH" || BANDWIDTH === "OPTIMIZED") begin pll_cp = 4'b1111; pll_res = 4'b1010; end + else if (BANDWIDTH === "LOW") begin pll_cp = 4'b0001; pll_res = 4'b1000; end +27 : if (BANDWIDTH === "HIGH" || BANDWIDTH === "OPTIMIZED") begin pll_cp = 4'b1101; pll_res = 4'b1100; end + else if (BANDWIDTH === "LOW") begin pll_cp = 4'b0001; pll_res = 4'b1000; end +28 : if (BANDWIDTH === "HIGH" || BANDWIDTH === "OPTIMIZED") begin pll_cp = 4'b1101; pll_res = 4'b1100; end + else if (BANDWIDTH === "LOW") begin pll_cp = 4'b0001; pll_res = 4'b1000; end +29 : if (BANDWIDTH === "HIGH" || BANDWIDTH === "OPTIMIZED") begin pll_cp = 4'b1101; pll_res = 4'b1100; end + else if (BANDWIDTH === "LOW") begin pll_cp = 4'b0001; pll_res = 4'b1000; end +30 : if (BANDWIDTH === "HIGH" || BANDWIDTH === "OPTIMIZED") begin pll_cp = 4'b1110; pll_res = 4'b1100; end + else if (BANDWIDTH === "LOW") begin pll_cp = 4'b0001; pll_res = 4'b1000; end +31 : if (BANDWIDTH === "HIGH" || BANDWIDTH === "OPTIMIZED") begin pll_cp = 4'b1101; pll_res = 4'b1100; end + else if (BANDWIDTH === "LOW") begin pll_cp = 4'b0010; pll_res = 4'b0100; end +32 : if (BANDWIDTH === "HIGH" || BANDWIDTH === "OPTIMIZED") begin pll_cp = 4'b1100; pll_res = 4'b0010; end + else if (BANDWIDTH === "LOW") begin pll_cp = 4'b0010; pll_res = 4'b0100; end +33 : if (BANDWIDTH === "HIGH" || BANDWIDTH === "OPTIMIZED") begin pll_cp = 4'b1111; pll_res = 4'b1010; end + else if (BANDWIDTH === "LOW") begin pll_cp = 4'b0010; pll_res = 4'b0100; end +34 : if (BANDWIDTH === "HIGH" || BANDWIDTH === "OPTIMIZED") begin pll_cp = 4'b0111; pll_res = 4'b0010; end + else if (BANDWIDTH === "LOW") begin pll_cp = 4'b0010; pll_res = 4'b0100; end +35 : if (BANDWIDTH === "HIGH" || BANDWIDTH === "OPTIMIZED") begin pll_cp = 4'b0111; pll_res = 4'b0010; end + else if (BANDWIDTH === "LOW") begin pll_cp = 4'b0010; pll_res = 4'b0100; end +36 : if (BANDWIDTH === "HIGH" || BANDWIDTH === "OPTIMIZED") begin pll_cp = 4'b0111; pll_res = 4'b0010; end + else if (BANDWIDTH === "LOW") begin pll_cp = 4'b0010; pll_res = 4'b0100; end +37 : if (BANDWIDTH === "HIGH" || BANDWIDTH === "OPTIMIZED") begin pll_cp = 4'b0110; pll_res = 4'b0010; end + else if (BANDWIDTH === "LOW") begin pll_cp = 4'b0010; pll_res = 4'b0100; end +38 : if (BANDWIDTH === "HIGH" || BANDWIDTH === "OPTIMIZED") begin pll_cp = 4'b0110; pll_res = 4'b0010; end + else if (BANDWIDTH === "LOW") begin pll_cp = 4'b0010; pll_res = 4'b1000; end +39 : if (BANDWIDTH === "HIGH" || BANDWIDTH === "OPTIMIZED") begin pll_cp = 4'b0110; pll_res = 4'b0010; end + else if (BANDWIDTH === "LOW") begin pll_cp = 4'b0010; pll_res = 4'b1000; end +40 : if (BANDWIDTH === "HIGH" || BANDWIDTH === "OPTIMIZED") begin pll_cp = 4'b0110; pll_res = 4'b0010; end + else if (BANDWIDTH === "LOW") begin pll_cp = 4'b0010; pll_res = 4'b1000; end +41 : if (BANDWIDTH === "HIGH" || BANDWIDTH === "OPTIMIZED") begin pll_cp = 4'b0110; pll_res = 4'b0010; end + else if (BANDWIDTH === "LOW") begin pll_cp = 4'b0010; pll_res = 4'b1000; end +42 : if (BANDWIDTH === "HIGH" || BANDWIDTH === "OPTIMIZED") begin pll_cp = 4'b0100; pll_res = 4'b0100; end + else if (BANDWIDTH === "LOW") begin pll_cp = 4'b0010; pll_res = 4'b1000; end +43 : if (BANDWIDTH === "HIGH" || BANDWIDTH === "OPTIMIZED") begin pll_cp = 4'b0100; pll_res = 4'b0100; end + else if (BANDWIDTH === "LOW") begin pll_cp = 4'b0010; pll_res = 4'b1000; end +44 : if (BANDWIDTH === "HIGH" || BANDWIDTH === "OPTIMIZED") begin pll_cp = 4'b0100; pll_res = 4'b0100; end + else if (BANDWIDTH === "LOW") begin pll_cp = 4'b0010; pll_res = 4'b1000; end +45 : if (BANDWIDTH === "HIGH" || BANDWIDTH === "OPTIMIZED") begin pll_cp = 4'b0011; pll_res = 4'b1000; end + else if (BANDWIDTH === "LOW") begin pll_cp = 4'b0010; pll_res = 4'b1000; end +46 : if (BANDWIDTH === "HIGH" || BANDWIDTH === "OPTIMIZED") begin pll_cp = 4'b0011; pll_res = 4'b1000; end + else if (BANDWIDTH === "LOW") begin pll_cp = 4'b0010; pll_res = 4'b1000; end +47 : if (BANDWIDTH === "HIGH" || BANDWIDTH === "OPTIMIZED") begin pll_cp = 4'b0011; pll_res = 4'b0100; end + else if (BANDWIDTH === "LOW") begin pll_cp = 4'b0010; pll_res = 4'b1000; end +48 : if (BANDWIDTH === "HIGH" || BANDWIDTH === "OPTIMIZED") begin pll_cp = 4'b0011; pll_res = 4'b0100; end + else if (BANDWIDTH === "LOW") begin pll_cp = 4'b0010; pll_res = 4'b1000; end +49 : if (BANDWIDTH === "HIGH" || BANDWIDTH === "OPTIMIZED") begin pll_cp = 4'b0011; pll_res = 4'b0100; end + else if (BANDWIDTH === "LOW") begin pll_cp = 4'b0010; pll_res = 4'b1000; end +50 : if (BANDWIDTH === "HIGH" || BANDWIDTH === "OPTIMIZED") begin pll_cp = 4'b0011; pll_res = 4'b0100; end + else if (BANDWIDTH === "LOW") begin pll_cp = 4'b0010; pll_res = 4'b1000; end +51 : if (BANDWIDTH === "HIGH" || BANDWIDTH === "OPTIMIZED") begin pll_cp = 4'b0011; pll_res = 4'b0100; end + else if (BANDWIDTH === "LOW") begin pll_cp = 4'b0010; pll_res = 4'b1000; end +52 : if (BANDWIDTH === "HIGH" || BANDWIDTH === "OPTIMIZED") begin pll_cp = 4'b0011; pll_res = 4'b0100; end + else if (BANDWIDTH === "LOW") begin pll_cp = 4'b0010; pll_res = 4'b1000; end +53 : if (BANDWIDTH === "HIGH" || BANDWIDTH === "OPTIMIZED") begin pll_cp = 4'b0011; pll_res = 4'b0100; end + else if (BANDWIDTH === "LOW") begin pll_cp = 4'b0010; pll_res = 4'b1000; end +54 : if (BANDWIDTH === "HIGH" || BANDWIDTH === "OPTIMIZED") begin pll_cp = 4'b0011; pll_res = 4'b0100; end + else if (BANDWIDTH === "LOW") begin pll_cp = 4'b0010; pll_res = 4'b1000; end +55 : if (BANDWIDTH === "HIGH" || BANDWIDTH === "OPTIMIZED") begin pll_cp = 4'b0011; pll_res = 4'b0100; end + else if (BANDWIDTH === "LOW") begin pll_cp = 4'b0010; pll_res = 4'b1000; end +56 : if (BANDWIDTH === "HIGH" || BANDWIDTH === "OPTIMIZED") begin pll_cp = 4'b0011; pll_res = 4'b0100; end + else if (BANDWIDTH === "LOW") begin pll_cp = 4'b0010; pll_res = 4'b1000; end +57 : if (BANDWIDTH === "HIGH" || BANDWIDTH === "OPTIMIZED") begin pll_cp = 4'b0010; pll_res = 4'b1000; end + else if (BANDWIDTH === "LOW") begin pll_cp = 4'b0010; pll_res = 4'b1000; end +58 : if (BANDWIDTH === "HIGH" || BANDWIDTH === "OPTIMIZED") begin pll_cp = 4'b0010; pll_res = 4'b1000; end + else if (BANDWIDTH === "LOW") begin pll_cp = 4'b0010; pll_res = 4'b1000; end +59 : if (BANDWIDTH === "HIGH" || BANDWIDTH === "OPTIMIZED") begin pll_cp = 4'b0010; pll_res = 4'b1000; end + else if (BANDWIDTH === "LOW") begin pll_cp = 4'b0010; pll_res = 4'b1000; end +60 : if (BANDWIDTH === "HIGH" || BANDWIDTH === "OPTIMIZED") begin pll_cp = 4'b0010; pll_res = 4'b1000; end + else if (BANDWIDTH === "LOW") begin pll_cp = 4'b0010; pll_res = 4'b1000; end +61 : if (BANDWIDTH === "HIGH" || BANDWIDTH === "OPTIMIZED") begin pll_cp = 4'b0010; pll_res = 4'b1000; end + else if (BANDWIDTH === "LOW") begin pll_cp = 4'b0010; pll_res = 4'b1000; end +62 : if (BANDWIDTH === "HIGH" || BANDWIDTH === "OPTIMIZED") begin pll_cp = 4'b0010; pll_res = 4'b1000; end + else if (BANDWIDTH === "LOW") begin pll_cp = 4'b0010; pll_res = 4'b1000; end +63 : if (BANDWIDTH === "HIGH" || BANDWIDTH === "OPTIMIZED") begin pll_cp = 4'b0010; pll_res = 4'b1000; end + else if (BANDWIDTH === "LOW") begin pll_cp = 4'b0010; pll_res = 4'b1000; end +64 : if (BANDWIDTH === "HIGH" || BANDWIDTH === "OPTIMIZED") begin pll_cp = 4'b0010; pll_res = 4'b1000; end + else if (BANDWIDTH === "LOW") begin pll_cp = 4'b0010; pll_res = 4'b1000; end + endcase +*/ + + case (clkfb_div_fint) + 1 : begin drp_lock_ref_dly = 5'b00110; + drp_lock_fb_dly = 5'b00110; + drp_lock_cnt = 10'b1111101000; + drp_lock_sat_high = 10'b1111101001; + drp_unlock_cnt = 10'b0000000001; end + 2 : begin drp_lock_ref_dly = 5'b00110; + drp_lock_fb_dly = 5'b00110; + drp_lock_cnt = 10'b1111101000; + drp_lock_sat_high = 10'b1111101001; + drp_unlock_cnt = 10'b0000000001; end + 3 : begin drp_lock_ref_dly = 5'b01000; + drp_lock_fb_dly = 5'b01000; + drp_lock_cnt = 10'b1111101000; + drp_lock_sat_high = 10'b1111101001; + drp_unlock_cnt = 10'b0000000001; end + 4 : begin drp_lock_ref_dly = 5'b01011; + drp_lock_fb_dly = 5'b01011; + drp_lock_cnt = 10'b1111101000; + drp_lock_sat_high = 10'b1111101001; + drp_unlock_cnt = 10'b0000000001; end + 5 : begin drp_lock_ref_dly = 5'b01110; + drp_lock_fb_dly = 5'b01110; + drp_lock_cnt = 10'b1111101000; + drp_lock_sat_high = 10'b1111101001; + drp_unlock_cnt = 10'b0000000001; end + 6 : begin drp_lock_ref_dly = 5'b10001; + drp_lock_fb_dly = 5'b10001; + drp_lock_cnt = 10'b1111101000; + drp_lock_sat_high = 10'b1111101001; + drp_unlock_cnt = 10'b0000000001; end + 7 : begin drp_lock_ref_dly = 5'b10011; + drp_lock_fb_dly = 5'b10011; + drp_lock_cnt = 10'b1111101000; + drp_lock_sat_high = 10'b1111101001; + drp_unlock_cnt = 10'b0000000001; end + 8 : begin drp_lock_ref_dly = 5'b10110; + drp_lock_fb_dly = 5'b10110; + drp_lock_cnt = 10'b1111101000; + drp_lock_sat_high = 10'b1111101001; + drp_unlock_cnt = 10'b0000000001; end + 9 : begin drp_lock_ref_dly = 5'b11001; + drp_lock_fb_dly = 5'b11001; + drp_lock_cnt = 10'b1111101000; + drp_lock_sat_high = 10'b1111101001; + drp_unlock_cnt = 10'b0000000001; end + 10 : begin drp_lock_ref_dly = 5'b11100; + drp_lock_fb_dly = 5'b11100; + drp_lock_cnt = 10'b1111101000; + drp_lock_sat_high = 10'b1111101001; + drp_unlock_cnt = 10'b0000000001; end + 11 : begin drp_lock_ref_dly = 5'b11111; + drp_lock_fb_dly = 5'b11111; + drp_lock_cnt = 10'b1110000100; + drp_lock_sat_high = 10'b1111101001; + drp_unlock_cnt = 10'b0000000001; end + 12 : begin drp_lock_ref_dly = 5'b11111; + drp_lock_fb_dly = 5'b11111; + drp_lock_cnt = 10'b1100111001; + drp_lock_sat_high = 10'b1111101001; + drp_unlock_cnt = 10'b0000000001; end + 13 : begin drp_lock_ref_dly = 5'b11111; + drp_lock_fb_dly = 5'b11111; + drp_lock_cnt = 10'b1011101110; + drp_lock_sat_high = 10'b1111101001; + drp_unlock_cnt = 10'b0000000001; end + 14 : begin drp_lock_ref_dly = 5'b11111; + drp_lock_fb_dly = 5'b11111; + drp_lock_cnt = 10'b1010111100; + drp_lock_sat_high = 10'b1111101001; + drp_unlock_cnt = 10'b0000000001; end + 15 : begin drp_lock_ref_dly = 5'b11111; + drp_lock_fb_dly = 5'b11111; + drp_lock_cnt = 10'b1010001010; + drp_lock_sat_high = 10'b1111101001; + drp_unlock_cnt = 10'b0000000001; end + 16 : begin drp_lock_ref_dly = 5'b11111; + drp_lock_fb_dly = 5'b11111; + drp_lock_cnt = 10'b1001110001; + drp_lock_sat_high = 10'b1111101001; + drp_unlock_cnt = 10'b0000000001; end + 17 : begin drp_lock_ref_dly = 5'b11111; + drp_lock_fb_dly = 5'b11111; + drp_lock_cnt = 10'b1000111111; + drp_lock_sat_high = 10'b1111101001; + drp_unlock_cnt = 10'b0000000001; end + 18 : begin drp_lock_ref_dly = 5'b11111; + drp_lock_fb_dly = 5'b11111; + drp_lock_cnt = 10'b1000100110; + drp_lock_sat_high = 10'b1111101001; + drp_unlock_cnt = 10'b0000000001; end + 19 : begin drp_lock_ref_dly = 5'b11111; + drp_lock_fb_dly = 5'b11111; + drp_lock_cnt = 10'b1000001101; + drp_lock_sat_high = 10'b1111101001; + drp_unlock_cnt = 10'b0000000001; end + 20 : begin drp_lock_ref_dly = 5'b11111; + drp_lock_fb_dly = 5'b11111; + drp_lock_cnt = 10'b0111110100; + drp_lock_sat_high = 10'b1111101001; + drp_unlock_cnt = 10'b0000000001; end + 21 : begin drp_lock_ref_dly = 5'b11111; + drp_lock_fb_dly = 5'b11111; + drp_lock_cnt = 10'b0111011011; + drp_lock_sat_high = 10'b1111101001; + drp_unlock_cnt = 10'b0000000001; end + 22 : begin drp_lock_ref_dly = 5'b11111; + drp_lock_fb_dly = 5'b11111; + drp_lock_cnt = 10'b0111000010; + drp_lock_sat_high = 10'b1111101001; + drp_unlock_cnt = 10'b0000000001; end + 23 : begin drp_lock_ref_dly = 5'b11111; + drp_lock_fb_dly = 5'b11111; + drp_lock_cnt = 10'b0110101001; + drp_lock_sat_high = 10'b1111101001; + drp_unlock_cnt = 10'b0000000001; end + 24 : begin drp_lock_ref_dly = 5'b11111; + drp_lock_fb_dly = 5'b11111; + drp_lock_cnt = 10'b0110010000; + drp_lock_sat_high = 10'b1111101001; + drp_unlock_cnt = 10'b0000000001; end + 25 : begin drp_lock_ref_dly = 5'b11111; + drp_lock_fb_dly = 5'b11111; + drp_lock_cnt = 10'b0110010000; + drp_lock_sat_high = 10'b1111101001; + drp_unlock_cnt = 10'b0000000001; end + 26 : begin drp_lock_ref_dly = 5'b11111; + drp_lock_fb_dly = 5'b11111; + drp_lock_cnt = 10'b0101110111; + drp_lock_sat_high = 10'b1111101001; + drp_unlock_cnt = 10'b0000000001; end + 27 : begin drp_lock_ref_dly = 5'b11111; + drp_lock_fb_dly = 5'b11111; + drp_lock_cnt = 10'b0101011110; + drp_lock_sat_high = 10'b1111101001; + drp_unlock_cnt = 10'b0000000001; end + 28 : begin drp_lock_ref_dly = 5'b11111; + drp_lock_fb_dly = 5'b11111; + drp_lock_cnt = 10'b0101011110; + drp_lock_sat_high = 10'b1111101001; + drp_unlock_cnt = 10'b0000000001; end + 29 : begin drp_lock_ref_dly = 5'b11111; + drp_lock_fb_dly = 5'b11111; + drp_lock_cnt = 10'b0101000101; + drp_lock_sat_high = 10'b1111101001; + drp_unlock_cnt = 10'b0000000001; end + 30 : begin drp_lock_ref_dly = 5'b11111; + drp_lock_fb_dly = 5'b11111; + drp_lock_cnt = 10'b0101000101; + drp_lock_sat_high = 10'b1111101001; + drp_unlock_cnt = 10'b0000000001; end + 31 : begin drp_lock_ref_dly = 5'b11111; + drp_lock_fb_dly = 5'b11111; + drp_lock_cnt = 10'b0100101100; + drp_lock_sat_high = 10'b1111101001; + drp_unlock_cnt = 10'b0000000001; end + 32 : begin drp_lock_ref_dly = 5'b11111; + drp_lock_fb_dly = 5'b11111; + drp_lock_cnt = 10'b0100101100; + drp_lock_sat_high = 10'b1111101001; + drp_unlock_cnt = 10'b0000000001; end + 33 : begin drp_lock_ref_dly = 5'b11111; + drp_lock_fb_dly = 5'b11111; + drp_lock_cnt = 10'b0100101100; + drp_lock_sat_high = 10'b1111101001; + drp_unlock_cnt = 10'b0000000001; end + 34 : begin drp_lock_ref_dly = 5'b11111; + drp_lock_fb_dly = 5'b11111; + drp_lock_cnt = 10'b0100010011; + drp_lock_sat_high = 10'b1111101001; + drp_unlock_cnt = 10'b0000000001; end + 35 : begin drp_lock_ref_dly = 5'b11111; + drp_lock_fb_dly = 5'b11111; + drp_lock_cnt = 10'b0100010011; + drp_lock_sat_high = 10'b1111101001; + drp_unlock_cnt = 10'b0000000001; end + 36 : begin drp_lock_ref_dly = 5'b11111; + drp_lock_fb_dly = 5'b11111; + drp_lock_cnt = 10'b0100010011; + drp_lock_sat_high = 10'b1111101001; + drp_unlock_cnt = 10'b0000000001; end + 37 : begin drp_lock_ref_dly = 5'b11111; + drp_lock_fb_dly = 5'b11111; + drp_lock_cnt = 10'b0011111010; + drp_lock_sat_high = 10'b1111101001; + drp_unlock_cnt = 10'b0000000001; end + 38 : begin drp_lock_ref_dly = 5'b11111; + drp_lock_fb_dly = 5'b11111; + drp_lock_cnt = 10'b0011111010; + drp_lock_sat_high = 10'b1111101001; + drp_unlock_cnt = 10'b0000000001; end + 39 : begin drp_lock_ref_dly = 5'b11111; + drp_lock_fb_dly = 5'b11111; + drp_lock_cnt = 10'b0011111010; + drp_lock_sat_high = 10'b1111101001; + drp_unlock_cnt = 10'b0000000001; end + 40 : begin drp_lock_ref_dly = 5'b11111; + drp_lock_fb_dly = 5'b11111; + drp_lock_cnt = 10'b0011111010; + drp_lock_sat_high = 10'b1111101001; + drp_unlock_cnt = 10'b0000000001; end + 41 : begin drp_lock_ref_dly = 5'b11111; + drp_lock_fb_dly = 5'b11111; + drp_lock_cnt = 10'b0011111010; + drp_lock_sat_high = 10'b1111101001; + drp_unlock_cnt = 10'b0000000001; end + 42 : begin drp_lock_ref_dly = 5'b11111; + drp_lock_fb_dly = 5'b11111; + drp_lock_cnt = 10'b0011111010; + drp_lock_sat_high = 10'b1111101001; + drp_unlock_cnt = 10'b0000000001; end + 43 : begin drp_lock_ref_dly = 5'b11111; + drp_lock_fb_dly = 5'b11111; + drp_lock_cnt = 10'b0011111010; + drp_lock_sat_high = 10'b1111101001; + drp_unlock_cnt = 10'b0000000001; end + 44 : begin drp_lock_ref_dly = 5'b11111; + drp_lock_fb_dly = 5'b11111; + drp_lock_cnt = 10'b0011111010; + drp_lock_sat_high = 10'b1111101001; + drp_unlock_cnt = 10'b0000000001; end + 45 : begin drp_lock_ref_dly = 5'b11111; + drp_lock_fb_dly = 5'b11111; + drp_lock_cnt = 10'b0011111010; + drp_lock_sat_high = 10'b1111101001; + drp_unlock_cnt = 10'b0000000001; end + 46 : begin drp_lock_ref_dly = 5'b11111; + drp_lock_fb_dly = 5'b11111; + drp_lock_cnt = 10'b0011111010; + drp_lock_sat_high = 10'b1111101001; + drp_unlock_cnt = 10'b0000000001; end + 47 : begin drp_lock_ref_dly = 5'b11111; + drp_lock_fb_dly = 5'b11111; + drp_lock_cnt = 10'b0011111010; + drp_lock_sat_high = 10'b1111101001; + drp_unlock_cnt = 10'b0000000001; end + 48 : begin drp_lock_ref_dly = 5'b11111; + drp_lock_fb_dly = 5'b11111; + drp_lock_cnt = 10'b0011111010; + drp_lock_sat_high = 10'b1111101001; + drp_unlock_cnt = 10'b0000000001; end + 49 : begin drp_lock_ref_dly = 5'b11111; + drp_lock_fb_dly = 5'b11111; + drp_lock_cnt = 10'b0011111010; + drp_lock_sat_high = 10'b1111101001; + drp_unlock_cnt = 10'b0000000001; end + 50 : begin drp_lock_ref_dly = 5'b11111; + drp_lock_fb_dly = 5'b11111; + drp_lock_cnt = 10'b0011111010; + drp_lock_sat_high = 10'b1111101001; + drp_unlock_cnt = 10'b0000000001; end + 51 : begin drp_lock_ref_dly = 5'b11111; + drp_lock_fb_dly = 5'b11111; + drp_lock_cnt = 10'b0011111010; + drp_lock_sat_high = 10'b1111101001; + drp_unlock_cnt = 10'b0000000001; end + 52 : begin drp_lock_ref_dly = 5'b11111; + drp_lock_fb_dly = 5'b11111; + drp_lock_cnt = 10'b0011111010; + drp_lock_sat_high = 10'b1111101001; + drp_unlock_cnt = 10'b0000000001; end + 53 : begin drp_lock_ref_dly = 5'b11111; + drp_lock_fb_dly = 5'b11111; + drp_lock_cnt = 10'b0011111010; + drp_lock_sat_high = 10'b1111101001; + drp_unlock_cnt = 10'b0000000001; end + 54 : begin drp_lock_ref_dly = 5'b11111; + drp_lock_fb_dly = 5'b11111; + drp_lock_cnt = 10'b0011111010; + drp_lock_sat_high = 10'b1111101001; + drp_unlock_cnt = 10'b0000000001; end + 55 : begin drp_lock_ref_dly = 5'b11111; + drp_lock_fb_dly = 5'b11111; + drp_lock_cnt = 10'b0011111010; + drp_lock_sat_high = 10'b1111101001; + drp_unlock_cnt = 10'b0000000001; end + 56 : begin drp_lock_ref_dly = 5'b11111; + drp_lock_fb_dly = 5'b11111; + drp_lock_cnt = 10'b0011111010; + drp_lock_sat_high = 10'b1111101001; + drp_unlock_cnt = 10'b0000000001; end + 57 : begin drp_lock_ref_dly = 5'b11111; + drp_lock_fb_dly = 5'b11111; + drp_lock_cnt = 10'b0011111010; + drp_lock_sat_high = 10'b1111101001; + drp_unlock_cnt = 10'b0000000001; end + 58 : begin drp_lock_ref_dly = 5'b11111; + drp_lock_fb_dly = 5'b11111; + drp_lock_cnt = 10'b0011111010; + drp_lock_sat_high = 10'b1111101001; + drp_unlock_cnt = 10'b0000000001; end + 59 : begin drp_lock_ref_dly = 5'b11111; + drp_lock_fb_dly = 5'b11111; + drp_lock_cnt = 10'b0011111010; + drp_lock_sat_high = 10'b1111101001; + drp_unlock_cnt = 10'b0000000001; end + 60 : begin drp_lock_ref_dly = 5'b11111; + drp_lock_fb_dly = 5'b11111; + drp_lock_cnt = 10'b0011111010; + drp_lock_sat_high = 10'b1111101001; + drp_unlock_cnt = 10'b0000000001; end + 61 : begin drp_lock_ref_dly = 5'b11111; + drp_lock_fb_dly = 5'b11111; + drp_lock_cnt = 10'b0011111010; + drp_lock_sat_high = 10'b1111101001; + drp_unlock_cnt = 10'b0000000001; end + 62 : begin drp_lock_ref_dly = 5'b11111; + drp_lock_fb_dly = 5'b11111; + drp_lock_cnt = 10'b0011111010; + drp_lock_sat_high = 10'b1111101001; + drp_unlock_cnt = 10'b0000000001; end + 63 : begin drp_lock_ref_dly = 5'b11111; + drp_lock_fb_dly = 5'b11111; + drp_lock_cnt = 10'b0011111010; + drp_lock_sat_high = 10'b1111101001; + drp_unlock_cnt = 10'b0000000001; end + 64 : begin drp_lock_ref_dly = 5'b11111; + drp_lock_fb_dly = 5'b11111; + drp_lock_cnt = 10'b0011111010; + drp_lock_sat_high = 10'b1111101001; + drp_unlock_cnt = 10'b0000000001; end + endcase + + tmp_string = "DIVCLK_DIVIDE"; + chk_ok = para_int_range_chk (DIVCLK_DIVIDE, tmp_string, D_MIN, D_MAX); + if(clkfb_frac_en == 0) begin + tmp_string = "CLKFBOUT_MULT_F"; + chk_ok = para_real_range_chk (CLKFBOUT_MULT_F, tmp_string, M_MIN, M_MAX); + tmp_string = "CLKOUT6_DUTY_CYCLE"; + chk_ok = clkout_duty_chk (CLKOUT6_DIVIDE, CLKOUT6_DUTY_CYCLE, tmp_string); + end + if(clk0_frac_en == 0) begin + tmp_string = "CLKOUT0_DUTY_CYCLE"; + chk_ok = clkout_duty_chk (CLKOUT0_DIVIDE_F, CLKOUT0_DUTY_CYCLE, tmp_string); + tmp_string = "CLKOUT5_DUTY_CYCLE"; + chk_ok = clkout_duty_chk (CLKOUT5_DIVIDE, CLKOUT5_DUTY_CYCLE, tmp_string); + end + tmp_string = "CLKOUT1_DUTY_CYCLE"; + chk_ok = clkout_duty_chk (CLKOUT1_DIVIDE, CLKOUT1_DUTY_CYCLE, tmp_string); + tmp_string = "CLKOUT2_DUTY_CYCLE"; + chk_ok = clkout_duty_chk (CLKOUT2_DIVIDE, CLKOUT2_DUTY_CYCLE, tmp_string); + tmp_string = "CLKOUT3_DUTY_CYCLE"; + chk_ok = clkout_duty_chk (CLKOUT3_DIVIDE, CLKOUT3_DUTY_CYCLE, tmp_string); + tmp_string = "CLKOUT4_DUTY_CYCLE"; + chk_ok = clkout_duty_chk (CLKOUT4_DIVIDE, CLKOUT4_DUTY_CYCLE, tmp_string); + period_vco_max = 1000000 / VCOCLK_FREQ_MIN; + period_vco_min = 1000000 / VCOCLK_FREQ_MAX; + period_vco_target = 1000000 / VCOCLK_FREQ_TARGET; + period_vco_target_half = period_vco_target / 2; + fb_delay_max = MAX_FEEDBACK_DELAY * MAX_FEEDBACK_DELAY_SCALE; + clk0f_product = CLKOUT0_DIVIDE_F * 8; + pll_lock_time = 12; + lock_period_time = 10; + if (clkfb_frac_en == 1) begin + md_product = clkfb_div_fint * DIVCLK_DIVIDE; + m_product = clkfb_div_fint; + mf_product = CLKFBOUT_MULT_F * 8; + clkout_en_val = mf_product - 2; + m_product2 = clkfb_div_fint / 2; + clkout_en_time = mf_product + 4 + pll_lock_time; + locked_en_time = md_product + clkout_en_time + 2; + lock_cnt_max = locked_en_time + 16; + end + else begin + md_product = clkfb_div_fint * DIVCLK_DIVIDE; + m_product = clkfb_div_fint; + mf_product = CLKFBOUT_MULT_F * 8; + m_product2 = clkfb_div_fint / 2; + clkout_en_val = m_product; + clkout_en_time = md_product + pll_lock_time; + locked_en_time = md_product + clkout_en_time + 2; + lock_cnt_max = locked_en_time + 16; + end + clkfb_stop_max = 3; + clkin_stop_max = DIVCLK_DIVIDE + 1; + REF_CLK_JITTER_MAX_tmp = REF_CLK_JITTER_MAX; + clk_out_para_cal (clk1_ht, clk1_lt, clk1_nocnt, clk1_edge, CLKOUT1_DIVIDE, CLKOUT1_DUTY_CYCLE); + clk_out_para_cal (clk2_ht, clk2_lt, clk2_nocnt, clk2_edge, CLKOUT2_DIVIDE, CLKOUT2_DUTY_CYCLE); + clk_out_para_cal (clk3_ht, clk3_lt, clk3_nocnt, clk3_edge, CLKOUT3_DIVIDE, CLKOUT3_DUTY_CYCLE); + clk_out_para_cal (clk4_ht, clk4_lt, clk4_nocnt, clk4_edge, CLKOUT4_DIVIDE, CLKOUT4_DUTY_CYCLE); + clk_out_para_cal (clkind_ht, clkind_lt, clkind_nocnt, clkind_edge, DIVCLK_DIVIDE, 0.50); + tmp_string = "CLKOUT1_PHASE"; + clkout_dly_cal (clkout1_dly, clk1pm_sel, CLKOUT1_DIVIDE, CLKOUT1_PHASE, tmp_string); + tmp_string = "CLKOUT2_PHASE"; + clkout_dly_cal (clkout2_dly, clk2pm_sel, CLKOUT2_DIVIDE, CLKOUT2_PHASE, tmp_string); + tmp_string = "CLKOUT3_PHASE"; + clkout_dly_cal (clkout3_dly, clk3pm_sel, CLKOUT3_DIVIDE, CLKOUT3_PHASE, tmp_string); + tmp_string = "CLKOUT4_PHASE"; + clkout_dly_cal (clkout4_dly, clk4pm_sel, CLKOUT4_DIVIDE, CLKOUT4_PHASE, tmp_string); + if (clkfb_frac_en == 1) begin + clkfbm1_dly = clkfb_div_fint /2; + clkout6_dly = clkfb_div_fint /2; + if (clkfb_div_fint_odd > 0) begin + clk6pm_sel = (8 + clkfb_div_frac_int) / 2; + clkfbm1pm_sel = 8 + clkfb_div_frac_int - (8 + clkfb_div_frac_int) / 2 ; + clkfbm1pm_sel_int = 8 + clkfb_div_frac_int - (8 + clkfb_div_frac_int) / 2 ; + end + else begin + clkfbm1pm_sel = clkfb_div_frac_int - clkfb_div_frac_int / 2; + clkfbm1pm_sel_int = clkfb_div_frac_int - clkfb_div_frac_int / 2; + clk6pm_sel = clkfb_div_frac_int / 2; + end + end + else begin + tmp_string = "CLKOUT6_PHASE"; + clkout_dly_cal (clkout6_dly, clk6pm_sel, CLKOUT6_DIVIDE, CLKOUT6_PHASE, tmp_string); + tmp_string = "CLKFBOUT_PHASE"; + clkout_dly_cal (clkfbm1_dly, clkfbm1pm_sel, clkfb_div_fint, CLKFBOUT_PHASE, tmp_string); + end + if (clk0_frac_en == 1) begin + clkout0_dly = clk0_div_fint /2; + clkout5_dly = clk0_div_fint /2; + if (clk0_div_fint_odd > 0) begin + clk5pm_sel = (8 + clk0_div_frac_int) / 2; + clk0pm_sel = 8 + clk0_div_frac_int - (8 + clk0_div_frac_int) / 2; + clk0pm_sel_int = 8 + clk0_div_frac_int - (8 + clk0_div_frac_int) / 2; + end + else begin + clk0pm_sel = clk0_div_frac_int - clk0_div_frac_int / 2; + clk0pm_sel_int = clk0_div_frac_int - clk0_div_frac_int / 2; + clk5pm_sel = clk0_div_frac_int / 2; + end + end + else begin + tmp_string = "CLKOUT0_PHASE"; + clkout_dly_cal (clkout0_dly, clk0pm_sel, clk0_div_fint, CLKOUT0_PHASE, tmp_string); + tmp_string = "CLKOUT5_PHASE"; + clkout_dly_cal (clkout5_dly, clk5pm_sel, CLKOUT5_DIVIDE, CLKOUT5_PHASE, tmp_string); + end + if (clk0_frac_en == 1) begin + end + else begin + clk_out_para_cal (clk0_ht, clk0_lt, clk0_nocnt, clk0_edge, clk0_div_fint, CLKOUT0_DUTY_CYCLE); + clk_out_para_cal (clk5_ht, clk5_lt, clk5_nocnt, clk5_edge, CLKOUT5_DIVIDE, CLKOUT5_DUTY_CYCLE); + end + if (clkfb_frac_en == 1) begin + end + else begin + clk_out_para_cal (clkfbm1_ht, clkfbm1_lt, clkfbm1_nocnt, clkfbm1_edge, clkfb_div_fint, 0.50); + clk_out_para_cal (clk6_ht, clk6_lt, clk6_nocnt, clk6_edge, CLKOUT6_DIVIDE, CLKOUT6_DUTY_CYCLE); + end + clk_out_para_cal (clkfbm2_ht, clkfbm2_lt, clkfbm2_nocnt, clkfbm2_edge, 1, 0.50); + clkind_div = DIVCLK_DIVIDE; + + dr_sram[6] = {clk5pm_sel[2:0], 1'b1, clk5_ht[5:0], clk5_lt[5:0]}; + dr_sram[7] = {5'bx, 3'b0, clk5_edge, clk5_nocnt, clkout5_dly[5:0]}; + dr_sram[8] = {clk0pm_sel[2:0], 1'b1, clk0_ht[5:0], clk0_lt[5:0]}; + dr_sram[9] = {8'b0, clk0_edge, clk0_nocnt, clkout0_dly[5:0]}; + dr_sram[10] = {clk1pm_sel[2:0], 1'b1, clk1_ht[5:0], clk1_lt[5:0]}; + dr_sram[11] = {6'bx, 2'b0, clk1_edge, clk1_nocnt, clkout1_dly[5:0]}; + dr_sram[12] = {clk2pm_sel[2:0], 1'b1, clk2_ht[5:0], clk2_lt[5:0]}; + dr_sram[13] = {6'bx, 2'b0, clk2_edge, clk2_nocnt, clkout2_dly[5:0]}; + dr_sram[14] = {clk3pm_sel[2:0], 1'b1, clk3_ht[5:0], clk3_lt[5:0]}; + dr_sram[15] = {6'bx, 2'b0, clk3_edge, clk3_nocnt, clkout3_dly[5:0]}; + dr_sram[16] = {clk4pm_sel[2:0], 1'b1, clk4_ht[5:0], clk4_lt[5:0]}; + dr_sram[17] = {5'bx, 3'b0, clk4_edge, clk4_nocnt, clkout4_dly[5:0]}; + dr_sram[18] = {clk6pm_sel[2:0], 1'b1, clk6_ht[5:0], clk6_lt[5:0]}; + dr_sram[19] = {6'bx, 2'b0, clk6_edge, clk6_nocnt, clkout6_dly[5:0]}; + dr_sram[20] = {clkfbm1pm_sel[2:0], 1'b1, clkfbm1_ht[5:0], clkfbm1_lt[5:0]}; + dr_sram[21] = {1'bx, 7'b0, clkfbm1_edge, clkfbm1_nocnt, clkfbm1_dly[5:0]}; + dr_sram[22] = {2'bx, clkind_edge, clkind_nocnt, clkind_ht[5:0], clkind_lt[5:0]}; + dr_sram[24] = {6'bx, drp_lock_cnt}; + dr_sram[25] = {1'bx, drp_lock_fb_dly, drp_unlock_cnt}; + dr_sram[26] = {1'bx, drp_lock_ref_dly, drp_lock_sat_high}; + dr_sram[40] = {1'b1, 2'bx, 2'b11, 2'bx, 2'b11, 2'bx, 2'b11, 2'bx, 1'b1}; + dr_sram[78] = {pll_cp[3], 2'bx, pll_cp[2:1], 2'bx, pll_cp[0], 1'b0, 2'bx, pll_cpres, 3'bx}; + dr_sram[79] = {pll_res[3], 2'bx, pll_res[2:1], 2'bx, pll_res[0], pll_lfhf[1], 2'bx, pll_lfhf[0], 4'bx}; + dr_sram[116] = {5'bx, 6'b0, 5'b00001}; + end + + initial begin + clkpll_jitter_unlock = 0; + clkinstopped_vco_f = 0; + rst_clkfbstopped = 0; + rst_clkinstopped = 0; + rst_clkfbstopped_lk = 0; + rst_clkinstopped_lk = 0; + clkfb_stop_tmp = 0; + clkin_stop_tmp = 0; + clkout_ps = 0; + clkout_ps_tmp1 = 0; + clkout_ps_tmp2 = 0; + clkvco_ps_tmp1 = 0; + clkvco_ps_tmp2 = 0; + clkvco_ps_tmp2_en = 0; + clkvco_lk_osc = 0; + clkvco_lk_en = 0; + clkvco_lk_tmp = 0; + clkvco_lk_dly_tmp = 0; + clk_osc = 0; + clkin_p = 0; + clkfb_p = 0; + clkind_edgei = 0; + clkind_nocnti = 0; + clkind_hti = 0; + clkind_lti = 0; + clkind_divi = 1; + drp_lock1 = 0; + ps_lock = 0; + ps_lock_dly = 0; + psdone_out = 0; + psdone_out1 = 0; + rst_in = 0; + clkinstopped_out = 0; + clkfbstopped_out = 0; + clkin_period[0] = 0; + clkin_period[1] = 0; + clkin_period[2] = 0; + clkin_period[3] = 0; + clkin_period[4] = 0; + clkin_period_tmp_t = 0; + period_avg = 0; + period_fb = 0; + clkin_lost_val = 500; + clkfb_lost_val = 500; + clkin_lost_val_lk = 500; + fb_delay = 0; + clkfbm1_div = 1; + clkfbm2_div = 1; + clkfbm1_div1 = 0; + clkfbm2_div1 = 0; + clkvco_delay = 0; + val_tmp = 0; + dly_tmp = 0; + fbm1_comp_delay = 0; + clkfbm1pm_rl = 0; + period_vco = 0; + period_vco1 = 0; + period_vco2 = 0; + period_vco3 = 0; + period_vco4 = 0; + period_vco5 = 0; + period_vco6 = 0; + period_vco7 = 0; + period_vco_half = 0; + period_vco_half1 = 0; + period_vco_half_rm = 0; + period_vco_half_rm1 = 0; + period_vco_half_rm2 = 0; + period_vco_rm = 0; + period_vco_cmp_cnt = 0; + period_vco_cmp_flag = 0; + period_ps = 0; + period_ps_old = 0; + clkfb_frac_ht = 0; + clkfb_frac_lt = 0; + clk0_frac_ht = 0; + clk0_frac_lt = 0; + clkvco_rm_cnt = 0; + fb_delay_found = 0; + fb_delay_found_tmp = 0; + clkin_edge = 0; + delay_edge = 0; + fbclk_tmp = 0; + clkfb_tst = 0; + clkout_en = 0; + clkout_en0 = 0; + clkout_en_t = 0; + clkout_en0_tmp = 0; + clkout_en1 = 0; + pll_locked_tmp1 = 0; + pll_locked_tmp2 = 0; + pll_locked_tm = 0; + pll_locked_delay = 0; + clkout_mux = 8'b0; + clkout_ps_mux = 8'b0; + unlock_recover = 0; + clkin_jit = 0; + clkin_lock_cnt = 0; + lock_period = 0; + rst_edge = 0; + rst_ht = 0; + drdy_out = 0; + drdy_out1 = 0; + locked_out1 = 0; + locked_out_tmp = 0; + do_out1 = 16'b0; + drp_lock = 0; + clkout0_out = 0; + clk0_dly_cnt = 6'b0; + clk1_dly_cnt = 6'b0; + clk2_dly_cnt = 6'b0; + clk3_dly_cnt = 6'b0; + clk4_dly_cnt = 6'b0; + clk5_dly_cnt = 6'b0; + clk6_dly_cnt = 6'b0; + clkfbm1_dly_cnt = 6'b0; + clk0_cnt = 8'b0; + clk1_cnt = 8'b0; + clk2_cnt = 8'b0; + clk3_cnt = 8'b0; + clk4_cnt = 8'b0; + clk5_cnt = 8'b0; + clk6_cnt = 8'b0; + clkfbm1_cnt = 8'b0; + clkfbm2_cnt = 8'b0; + clkind_cnt = 8'b0; + clkout0_out = 0; + clkout1_out = 0; + clkout2_out = 0; + clkout3_out = 0; + clkout4_out = 0; + clkout5_out = 0; + clkout6_out = 0; + clk0_nf_out = 0; + clk0_frac_out = 0; + clk1_out = 0; + clk2_out = 0; + clk3_out = 0; + clk4_out = 0; + clk5_out = 0; + clk6_out = 0; + clkfb_out = 0; + clkfbm1_nf_out = 0; + clkfbm1_frac_out = 0; + clkfbm2_out = 0; + clkfbm2_out_tmp = 0; + clkind_out = 0; + clkind_out_tmp = 0; + clk_osc = 0; + clkin_p = 0; + clkfb_p = 0; + pwron_int = 1; + #100000 pwron_int = 0; + end + + assign CLKOUT6 = clkout6_out; + assign CLKOUT5 = clkout5_out; + assign CLKOUT4 = clkout4_out; + assign CLKOUT3 = clkout3_out; + assign CLKOUT2 = clkout2_out; + assign CLKOUT1 = clkout1_out; + assign CLKOUT0 = clkout0_out; + assign CLKFBOUT = clkfb_out; + assign CLKOUT3B = ~clkout3_out; + assign CLKOUT2B = ~clkout2_out; + assign CLKOUT1B = ~clkout1_out; + assign CLKOUT0B = ~clkout0_out; + assign CLKFBOUTB = ~clkfb_out; + + assign #1 clkinsel_tmp = clkinsel_in; + + assign glock = (startup_wait_sig) ? locked_out_tmp : 1; + assign (weak1, strong0) glbl.PLL_LOCKG = (glock == 0) ? 0 : p_up; + + initial begin + init_chk = 0; + #1; + init_chk = 1; + end + + always @(clkinsel_in or posedge init_chk ) begin + if ($time > 1 && rst_in === 0 && (clkinsel_tmp === 0 || clkinsel_tmp === 1)) begin + $display("Input Error : Input clock can only be switched when RST=1. CLKINSEL on MMCM_ADV instance %m at time %t changed when RST low, which should change at RST high.", $time); + $finish; + end + if (SIM_DEVICE == "VIRTEX6") begin + clkin_chk_t1 = 1000.0 / CLKIN_FREQ_MIN; + clkin_chk_t2 = 1000.0 / CLKIN_FREQ_MAX; + end + else begin + clkin_chk_t1 = 100.0; + clkin_chk_t2 = 0.938; + end + + if (clkinsel_in === 1 && $time > 1 || clkinsel_in !== 0 && init_chk == 1) begin + if (CLKIN1_PERIOD > clkin_chk_t1 || CLKIN1_PERIOD < clkin_chk_t2) begin + $display (" Attribute Syntax Error : The attribute CLKIN1_PERIOD is set to %f ns and out the allowed range %f ns to %f ns.", CLKIN1_PERIOD, clkin_chk_t2, clkin_chk_t1); + + $finish; + end + end + else if (clkinsel_in ===0 && $time > 1 || init_chk == 1 && clkinsel_tmp === 0 ) begin + if (CLKIN2_PERIOD > clkin_chk_t1 || CLKIN2_PERIOD < clkin_chk_t2) begin + $display (" Attribute Syntax Error : The attribute CLKIN2_PERIOD is set to %f ns and out the allowed range %f ns to %f ns.", CLKIN2_PERIOD, clkin_chk_t2, clkin_chk_t1); + $finish; + end + end + period_clkin = (clkinsel_in === 0) ? CLKIN2_PERIOD : CLKIN1_PERIOD; + clkvco_freq_init_chk = (1000.0 * CLKFBOUT_MULT_F) / (period_clkin * DIVCLK_DIVIDE); + if (clkvco_freq_init_chk > VCOCLK_FREQ_MAX || clkvco_freq_init_chk < VCOCLK_FREQ_MIN) begin + if (clkinsel_tmp === 0 && $time > 1 || clkinsel_tmp === 0 && init_chk === 1) begin + $display (" Attribute Syntax Error : The calculation of VCO frequency=%f Mhz. This exceeds the permitted VCO frequency range of %f Mhz to %f Mhz. The VCO frequency is calculated with formula: VCO frequency = CLKFBOUT_MULT_F / (DIVCLK_DIVIDE * CLKIN2_PERIOD). Please adjust the attributes to the permitted VCO frequency range.", clkvco_freq_init_chk, VCOCLK_FREQ_MIN, VCOCLK_FREQ_MAX); + $finish; + end + else if (clkinsel_tmp === 1 && $time > 1 || clkinsel_tmp !== 0 && init_chk === 1) begin + $display (" Attribute Syntax Error : The calculation of VCO frequency=%f Mhz. This exceeds the permitted VCO frequency range of %f Mhz to %f Mhz. The VCO frequency is calculated with formula: VCO frequency = CLKFBOUT_MULT_F / (DIVCLK_DIVIDE * CLKIN1_PERIOD). Please adjust the attributes to the permitted VCO frequency range.", clkvco_freq_init_chk, VCOCLK_FREQ_MIN, VCOCLK_FREQ_MAX); + $finish; + end + end + end + + assign init_trig = 1; + assign clkpll_r = (clkinsel_in) ? clkin1_in : clkin2_in; + assign pwrdwn_in1 = (pwrdwn_in === 1) ? 1 : 0; + assign rst_input = rst_input_r | pwrdwn_in1; + + always @(posedge clkpll_r or posedge rst_input) + if (rst_input) + rst_in <= 1; + else + rst_in <= rst_input ; + + assign rst_in_o = (rst_in || rst_clkfbstopped || rst_clkinstopped); + + + // + // DRP port read and write + // + + assign do_out = dr_sram[daddr_lat]; + + always @(posedge dclk_in or posedge GSR) + if (GSR == 1) begin + drp_lock <= 0; + end + else begin + if (den_in == 1) begin + valid_daddr = addr_is_valid(daddr_in); + if (drp_lock == 1) begin + $display(" Warning : DEN is high at MMCM_ADV instance %m at time %t. Need wait for DRDY signal before next read/write operation through DRP. ", $time); + end + else begin + drp_lock <= 1; + daddr_lat <= daddr_in; + end + if (valid_daddr && ( daddr_in == 7'b1110100 || daddr_in == 7'b1001111 || + daddr_in == 7'b1001110 || daddr_in == 7'b0101000 || + (daddr_in >= 7'b0011000 && daddr_in <= 7'b0011010) || + (daddr_in >= 7'b0000110 && daddr_in <= 7'b0010110))) begin + end + else begin + $display(" Warning : Address DADDR=%b is unsupported at MMCM_ADV instance %m at time %t. ", DADDR, $time); + end + + if (dwe_in == 1) begin // write process + if (rst_input == 1) begin + if (valid_daddr && ( daddr_in == 7'b1110100 || daddr_in == 7'b1001111 || + daddr_in == 7'b1001110 || daddr_in == 7'b0101000 || + (daddr_in >= 7'b0011000 && daddr_in <= 7'b0011010) || + (daddr_in >= 7'b0000110 && daddr_in <= 7'b0010110))) begin + dr_sram[daddr_in] <= di_in; + end + if (daddr_in == 7'b0001001) + clkout_delay_para_drp (clkout0_dly, clk0_nocnt, clk0_edge, di_in, daddr_in); + if (daddr_in == 7'b0001000) + clkout_hl_para_drp (clk0_lt, clk0_ht, clk0pm_sel, di_in, daddr_in); + if (daddr_in == 7'b0001011) + clkout_delay_para_drp (clkout1_dly, clk1_nocnt, clk1_edge, di_in, daddr_in); + if (daddr_in == 7'b0001010) + clkout_hl_para_drp (clk1_lt, clk1_ht, clk1pm_sel, di_in, daddr_in); + if (daddr_in == 7'b0001101) + clkout_delay_para_drp (clkout2_dly, clk2_nocnt, clk2_edge, di_in, daddr_in); + if (daddr_in == 7'b0001100) + clkout_hl_para_drp (clk2_lt, clk2_ht, clk2pm_sel, di_in, daddr_in); + if (daddr_in == 7'b0001111) + clkout_delay_para_drp (clkout3_dly, clk3_nocnt, clk3_edge, di_in, daddr_in); + if (daddr_in == 7'b0001110) + clkout_hl_para_drp (clk3_lt, clk3_ht, clk3pm_sel, di_in, daddr_in); + if (daddr_in == 7'b0010001) + clkout_delay_para_drp (clkout4_dly, clk4_nocnt, clk4_edge, di_in, daddr_in); + if (daddr_in == 7'b0010000) + clkout_hl_para_drp (clk4_lt, clk4_ht, clk4pm_sel, di_in, daddr_in); + if (daddr_in == 7'b0010011) + clkout_delay_para_drp (clkout6_dly, clk6_nocnt, clk6_edge, di_in, daddr_in); + if (daddr_in == 7'b0010010) + clkout_hl_para_drp (clk6_lt, clk6_ht, clk6pm_sel, di_in, daddr_in); + if (daddr_in == 7'b0000111) + clkout_delay_para_drp (clkout5_dly, clk5_nocnt, clk5_edge, di_in, daddr_in); + if (daddr_in == 7'b0000110) + clkout_hl_para_drp (clk5_lt, clk5_ht, clk5pm_sel, di_in, daddr_in); + if (daddr_in == 7'b0010101) begin + clkout_delay_para_drp (clkfbm1_dly, clkfbm1_nocnt, clkfbm1_edge, di_in, daddr_in); + clkfbtmp_nocnti = di_in[12]; + end + if (daddr_in == 7'b0010100) begin + clkout_hl_para_drp (clkfbm1_lt, clkfbm1_ht, clkfbm1pm_sel, di_in, daddr_in); + clkfbtmp_lti = {2'b00, di_in[5:0]}; + clkfbtmp_hti = {2'b00, di_in[11:6]}; + if (clkfbtmp_nocnti == 1) + clkfbtmp_divi = 8'b00000001; + else if (di_in[5:0] == 6'b0 && di_in[11:6] == 6'b0) + clkfbtmp_divi = 8'b10000000; + else if (di_in[5:0] == 6'b0) + clkfbtmp_divi = 64 + clkfbtmp_hti; + else if (di_in[11:6] == 6'b0) + clkfbtmp_divi = 64 + clkfbtmp_lti; + else + clkfbtmp_divi = clkfbtmp_hti + clkfbtmp_lti; + if (SIM_DEVICE == "VIRTEX6") begin + if (clkfbtmp_divi > 64 || (clkfbtmp_divi < 5)) + $display(" Input Error : DI at Address DADDR=%b is %h at MMCM_ADV instance %m at time %t. The sum of DI[11:6] and DI[5:0] is %b and over the range of %d to %d.", daddr_in, di_in, clkfbtmp_divi, $time, 5, 64); + end + else begin + if (clkfbtmp_divi > 64 || (clkfbtmp_divi < 2)) + $display(" Input Error : DI at Address DADDR=%b is %h at MMCM_ADV instance %m at time %t. The sum of DI[11:6] and DI[5:0] is %d and over the range of %d to %d.", daddr_in, di_in, clkfbtmp_divi, $time, 2, 64); + end + end + + if (daddr_in == 7'b0010110) begin + clkind_lti = {2'b00, di_in[5:0]}; + clkind_hti = {2'b00, di_in[11:6]}; + clkind_lt <= clkind_lti; + clkind_ht <= clkind_hti; + clkind_nocnt <= di_in[12]; + clkind_nocnti = di_in[12]; + clkind_edgei = di_in[13]; + clkind_edge <= di_in[13]; + if (di_in[12] == 1) + clkind_divi = 8'b00000001; + else if (di_in[5:0] == 6'b0 && di_in[11:6] == 6'b0) + clkind_divi = 8'b10000000; + else if (di_in[5:0] == 6'b0) + clkind_divi = 64 + clkind_hti; + else if (di_in[11:6] == 6'b0) + clkind_divi = 64 + clkind_lti; + else + clkind_divi = clkind_hti + clkind_lti; + + clkind_div <= clkind_divi; + if (clkind_divi > D_MAX || (clkind_divi < 1 && clkind_nocnti == 0)) + $display(" Input Error : DI at Address DADDR=%b is %h at MMCM_ADV instance %m at time %t. The sum of DI[11:6] and DI[5:0] is %d and over the range of 1 to %d.", daddr_in, di_in, clkind_divi, $time, D_MAX); + end + end + else begin + $display(" Error : RST is low at MMCM_ADV instance %m at time %t. RST need to be high when change MMCM_ADV paramters through DRP. ", $time); + end + end //DWE + end //DEN + if ( drp_lock == 1) begin + drp_lock <= 0; + drp_lock1 <= 1; + end + if (drp_lock1 == 1) begin + drp_lock1 <= 0; + drdy_out <= 1; + end + if (drdy_out == 1) + drdy_out <= 0; + end + + function addr_is_valid; + input [6:0] daddr_funcin; + begin + addr_is_valid = 1; + for (i=0; i<=6; i=i+1) + if ( daddr_funcin[i] != 0 && daddr_funcin[i] != 1) + addr_is_valid = 0; + end + endfunction + + // end process drp; + + // + // determine clock period + // + + always @(posedge clkpll_r or posedge rst_in or posedge rst_clkinsel_flag) + if (rst_in || rst_clkinsel_flag) + begin + clkin_period[0] <= period_vco_target; + clkin_period[1] <= period_vco_target; + clkin_period[2] <= period_vco_target; + clkin_period[3] <= period_vco_target; + clkin_period[4] <= period_vco_target; + clkin_jit <= 0; + clkin_lock_cnt <= 0; + pll_locked_tm <= 0; + lock_period <= 0; + pll_locked_tmp1 <= 0; + clkout_en0_tmp <= 0; + unlock_recover <= 0; + clkin_edge <= 0; + end + else begin + clkin_edge <= $time; + clkin_period[4] <= clkin_period[3]; + clkin_period[3] <= clkin_period[2]; + clkin_period[2] <= clkin_period[1]; + clkin_period[1] <= clkin_period[0]; + if (clkin_edge != 0 && clkinstopped_out == 0 && rst_clkinsel_flag == 0) begin + clkin_period[0] <= $time - clkin_edge; + end + + if (pll_unlock == 0) + clkin_jit <= $time - clkin_edge - clkin_period[0]; + else + clkin_jit <= 0; + if ( (clkin_lock_cnt < lock_cnt_max) && fb_delay_found && pll_unlock1 == 0) + clkin_lock_cnt <= clkin_lock_cnt + 1; + else if (pll_unlock1 == 1 && pll_locked_tmp1 ==1 ) begin + clkin_lock_cnt <= lock_cnt_max - 6; + unlock_recover <= 1; + end + if ( clkin_lock_cnt >= pll_lock_time && pll_unlock1 == 0) + pll_locked_tm <= 1; + if ( clkin_lock_cnt == lock_period_time ) + lock_period <= 1; + if (clkin_lock_cnt >= clkout_en_time && pll_locked_tm == 1) begin + clkout_en0_tmp <= 1; + end + if (clkin_lock_cnt >= locked_en_time && clkout_en == 1) + pll_locked_tmp1 <= 1; + if (unlock_recover ==1 && clkin_lock_cnt >= lock_cnt_max) + unlock_recover <= 0; + end + + always @(m_product or mf_product or clkfb_frac_en) + if (clkfb_frac_en == 0) + clkout_en_val = m_product; + else + clkout_en_val = mf_product - 2; + + always @(clkout_en0_tmp) + clkout_en0_tmp1 <= #1 clkout_en0_tmp; + + always @(clkout_en0_tmp1 or clkout_en_t or clkout_en0_tmp ) + if (clkout_en0_tmp==0 ) + clkout_en0 = 0; + else begin + if (clkfb_frac_en == 1) begin + if (clkout_en_t > clkout_en_val && clkout_en0_tmp1 == 1) + clkout_en0 <= #period_vco6 clkout_en0_tmp1; + end + else begin + if (clkout_en_t == clkout_en_val && clkout_en0_tmp1 == 1) + clkout_en0 <= #period_vco6 clkout_en0_tmp1; + end + end + + always @(clkout_en0 ) + clkout_en1 <= #(clkvco_delay) clkout_en0; + + always @(clkout_en1 or rst_in_o ) + if (rst_in_o) + clkout_en = 0; + else + clkout_en = clkout_en1; + + always @(pll_locked_tmp1 ) + if (pll_locked_tmp1==0) + pll_locked_tmp2 = pll_locked_tmp1; + else begin + pll_locked_tmp2 <= #pll_locked_delay pll_locked_tmp1; + end + + always @(rst_in) + if (rst_in) begin + assign pll_locked_tmp2 = 0; + assign clkout_en0 = 0; + assign clkout_en1 = 0; + end + else begin + deassign pll_locked_tmp2; + deassign clkout_en0; + deassign clkout_en1; + end + + assign locked_out = (pll_locked_tm && pll_locked_tmp2 && ~pll_unlock && !unlock_recover) ? 1 : 0; + + always @(rst_in or locked_out) + if (rst_in == 1) + locked_out_tmp <= 0; + else + locked_out_tmp <= locked_out; + + always @(clkin_period[0] or clkin_period[1] or clkin_period[2] or + clkin_period[3] or clkin_period[4] or period_avg ) begin + if (clkin_period[0] > clkin_period[1]) + clkin_period_tmp_t = clkin_period[0] - clkin_period[1]; + else + clkin_period_tmp_t = clkin_period[1] - clkin_period[0]; + + if ( (clkin_period[0] != period_avg) && (clkin_period[0] < 1.5 * period_avg || clkin_period_tmp_t <= 300) ) + period_avg = (clkin_period[0] + clkin_period[1] + clkin_period[2] + + clkin_period[3] + clkin_period[4])/5; + end + + assign clkinstopped_hold = (clkin_hold_f == 1) ? clkinstopped_out : 0; + + always @(period_avg or lock_period or clkind_div) + if (period_avg > 500 && lock_period == 1) begin + clkin_lost_val = ((period_avg * 1.5) / 500) - 1; + clkfb_lost_val = ((period_avg * 1.5 * clkind_div) / 500) - 1; + end + + always @(clkfb_frac_en or clkfbm1_f_div or clkfbm1_div) + if (clkfb_frac_en) + clkfbm1_div_t = clkfbm1_f_div; + else + clkfbm1_div_t = clkfbm1_div; + + always @(period_avg or clkind_div or clkfbm1_div_t or clkinstopped_hold or posedge rst_clkinstopped_rc) + if (period_avg > 0 ) begin + md_product = clkind_div * clkfbm1_div_t; + m_product = clkfbm1_div_t; + m_product2 = clkfbm1_div_t / 2; + period_fb = period_avg * clkind_div; + period_vco_tmp = period_fb / clkfbm1_div_t; + clkvco_pdrm = (period_avg * clkind_div / clkfbm1_div_t) - period_vco_tmp; + period_vco_mf = period_avg * 8; + if (clkinstopped_hold == 1) + period_vco = (20000 * period_vco_tmp) / (20000 - period_vco_tmp); + else + period_vco = period_vco_tmp; + clkfbm1_div_t_int = $rtoi(clkfbm1_div_t); + period_vco_rm = period_fb % clkfbm1_div_t_int; + if (period_vco_rm > 1) begin + if (period_vco_rm > m_product2) begin + period_vco_cmp_cnt = m_product / (m_product - period_vco_rm) - 1; + period_vco_cmp_flag = 2; + end + else begin + period_vco_cmp_cnt = (m_product / period_vco_rm) - 1; + period_vco_cmp_flag = 1; + end + end + else begin + period_vco_cmp_cnt = 0; + period_vco_cmp_flag = 0; + end + period_vco_half = period_vco /2; + period_vco_half_rm = period_vco - period_vco_half; + period_vco_half_rm1 = period_vco_half_rm + 1; + period_vco_half_rm2 = period_vco_half_rm - 1; + period_vco_half1 = period_vco - period_vco_half + 1; + pll_locked_delay = period_fb * clkfbm1_div_t; + clkin_dly_t = period_avg * (clkind_div + 1.25); + clkfb_dly_t = period_fb * 2.25 ; + period_vco1 = period_vco / 8; + period_vco2 = period_vco / 4; + period_vco3 = period_vco * 3/ 8; + period_vco4 = period_vco / 2; + period_vco5 = period_vco * 5 / 8; + period_vco6 = period_vco *3 / 4; + period_vco7 = period_vco * 7 / 8; + clk0_frac_ht = period_vco * clkout0_dly + (period_vco * clk0pm_sel_int) / 8; + clk0_frac_lt = period_vco * clkout5_dly + (period_vco * clk5pm_sel) / 8; + clkfb_frac_ht = period_vco * clkfbm1_dly + (period_vco * clkfbm1pm_sel_int) / 8; + clkfb_frac_lt = period_vco * clkout6_dly + (period_vco * clk6pm_sel) / 8; + end + + always @(period_vco or ps_in_ps) + if (fps_en == 1) begin + period_ps_old = period_ps; + if (ps_in_ps < 0) + period_ps = period_vco + ps_in_ps * period_vco / 56.0; + else if ((ps_in_ps == 0) && psincdec_in == 0) + period_ps = period_vco; + else + period_ps = ps_in_ps * period_vco / 56.0; + end + + + always @( clkpll_r ) + clkpll_tmp1 <= #(period_avg) clkpll_r; + + always @(clkpll_tmp1) + clkpll <= #(period_avg) clkpll_tmp1; + + always @(posedge clkinstopped_out ) begin + clkinstopped_vco_f <= 1; + @(posedge clkpll); + @(posedge clkpll) + clkinstopped_vco_f <= 0; + end + + always @(posedge clkinstopped_out or posedge rst_in) + if (rst_in) + clkinstopped_out1 <= 0; + else begin + clkinstopped_out1 <= 1; + @(posedge locked_out or posedge rst_in) + clkinstopped_out1 <= 0; + end + + always @(posedge clkfbstopped_out) begin + clkfbstopped_out1 <= 1; + @(posedge locked_out) + clkfbstopped_out1 <= 0; + end + + always @(clkout_en_t) + if (clkout_en_t >= clkout_en_val -3 && clkout_en_t < clkout_en_val) + rst_clkinstopped_tm = 1; + else + rst_clkinstopped_tm = 0; + + always @(negedge clkinstopped_out or posedge rst_in) + if (rst_in) + rst_clkinstopped <= 0; + else + if (rst_clkinstopped_lk == 0) begin + @(posedge rst_clkinstopped_tm) + rst_clkinstopped <= #period_vco3 1; + @(negedge rst_clkinstopped_tm ) begin + rst_clkinstopped <= #period_vco5 0; + rst_clkinstopped_rc <= #period_vco6 1; + rst_clkinstopped_rc <= #period_vco7 0; + end + end + + always @(posedge clkinstopped_out or posedge rst_in) + if (rst_in) + clkinstopped_out_dly <= 0; + else begin + clkinstopped_out_dly <= 1; + @(negedge rst_clkinstopped_rc or posedge rst_in) + clkinstopped_out_dly <= 0; + end + + always @(negedge rst_clkinstopped) begin + rst_clkinstopped_lk <= 1; + @(posedge locked_out) + rst_clkinstopped_lk <= 0; + end + + + always @(clkinstopped_vco_f or clkvco_lk or clkvco_lk_tmp or rst_in) + if (rst_in) + clkvco_lk = 0; + else begin + if (clkinstopped_vco_f == 1 && period_vco_half > 0) + clkvco_lk <= #(period_vco_half) !clkvco_lk; + else + clkvco_lk = clkvco_lk_tmp; + end + + always @(posedge clkpll) + if (clkfb_frac_en == 1) begin + if (pll_locked_tm ==1 ) begin + clkvco_lk_tmp <= 1; + cmpvco = 0.0; + for (ik1=1; ik1 < mf_product; ik1=ik1+1) begin + #(period_vco_half) clkvco_lk_tmp <= 0; + if ( cmpvco >= 1.0 ) begin + #(period_vco_half_rm1) clkvco_lk_tmp <= 1; + cmpvco <= cmpvco - 1.0 + clkvco_pdrm; + end + else if ( cmpvco <= -1.0 ) begin + #(period_vco_half_rm2) clkvco_lk_tmp <= 1; + cmpvco <= cmpvco + 1.0 + clkvco_pdrm; + end + else begin + #(period_vco_half_rm) clkvco_lk_tmp <= 1; + cmpvco <= cmpvco + clkvco_pdrm; + end + clkout_en_t <= ik1; + end + clkout_en_t <= ik1; + #(period_vco_half) clkvco_lk_tmp <= 0; + end + end + else begin + if (pll_locked_tm ==1) begin + clkvco_lk_tmp <= 1; + clkvco_rm_cnt = 0; + clkout_en_t <= 0; + if ( period_vco_cmp_flag == 1) begin + for (ik2=1; ik2 < m_product; ik2=ik2+1) begin + clkout_en_t <= ik2; + #(period_vco_half) clkvco_lk_tmp <= 0; + if ( clkvco_rm_cnt == 1) +// #(period_vco_half1) clkvco_lk_tmp <= 1; + #(period_vco_half_rm1) clkvco_lk_tmp <= 1; + else + #(period_vco_half_rm) clkvco_lk_tmp <= 1; + + if ( clkvco_rm_cnt == period_vco_cmp_cnt) + clkvco_rm_cnt <= 0; + else + clkvco_rm_cnt <= clkvco_rm_cnt + 1; + end + clkout_en_t <= ik2; + end + else if ( period_vco_cmp_flag == 2 ) begin + for (ik3=1; ik3 < m_product; ik3=ik3+1) begin + clkout_en_t <= ik3; + #(period_vco_half) clkvco_lk_tmp <= 0; + if ( clkvco_rm_cnt == 1) + #(period_vco_half_rm) clkvco_lk_tmp <= 1; + else + #(period_vco_half_rm1) clkvco_lk_tmp <= 1; + + if ( clkvco_rm_cnt == period_vco_cmp_cnt) + clkvco_rm_cnt <= 0; + else + clkvco_rm_cnt <= clkvco_rm_cnt + 1; + end + clkout_en_t <= ik3; + end + else begin + for (ik4=1; ik4 < m_product; ik4=ik4+1) begin + clkout_en_t <= ik4; + #(period_vco_half) clkvco_lk_tmp <= 0; + #(period_vco_half_rm) clkvco_lk_tmp <= 1; + end + clkout_en_t <= ik4; + end + + #(period_vco_half) clkvco_lk_tmp <= 0; + +// if (clkpll == 1) begin + if (clkpll == 1 && m_product > 1) begin + for (ik4=1; ik4 < m_product; ik4=ik4+1) begin + clkout_en_t <= ik4; + #(period_vco_half) clkvco_lk_tmp <= 0; + #(period_vco_half_rm) clkvco_lk_tmp <= 1; + end + clkout_en_t <= ik4; + #(period_vco_half) clkvco_lk_tmp <= 0; + end + + end + end + + always @(fb_delay or period_vco or period_vco_mf or clkfbm1_dly or clkfbm1pm_rl + or lock_period or ps_in_ps ) + if (lock_period == 1) begin + if (clkfb_frac_en == 1) begin + fbm1_comp_delay = 0; +// val_tmp = period_vco * mf_product ; + val_tmp = period_vco_mf; + end + else begin + val_tmp = period_avg * DIVCLK_DIVIDE; + fbm1_comp_delay = period_vco * (clkfbm1_dly + clkfbm1pm_rl); + end + dly_tmp1 = fb_delay + fbm1_comp_delay; + dly_tmp_int = 1; + if (clkfb_fps_en == 1) begin + if (ps_in_ps < 0) begin + tmp_ps_val1 = -1 * ps_in_ps; + tmp_ps_val2 = tmp_ps_val1 * period_vco / 56.0; + if (tmp_ps_val2 > dly_tmp1 ) begin + dly_tmp_int = -1; + dly_tmp = tmp_ps_val2 - dly_tmp1; + end + else if (tmp_ps_val2 == dly_tmp1 ) begin + dly_tmp_int = 0; + dly_tmp = 0; + end + else begin + dly_tmp_int = 1; + dly_tmp = dly_tmp1 - tmp_ps_val2; + end + end + else + dly_tmp = dly_tmp1 + ps_in_ps * period_vco / 56.0; + end + else + dly_tmp = dly_tmp1; + + if (dly_tmp_int < 0) + clkvco_delay = dly_tmp; + else begin + if (clkfb_frac_en == 1 && dly_tmp == 0) + clkvco_delay = 0; + else if ( dly_tmp < val_tmp) + clkvco_delay = val_tmp - dly_tmp; + else + clkvco_delay = val_tmp - dly_tmp % val_tmp ; + end + end + + always @(period_vco or ps_in_ps ) + if (fps_en == 1) begin + if (ps_in_ps < 0) + period_ps = period_vco + ps_in_ps * period_vco / 56.0; + else if ((ps_in_ps == 0) && psincdec_in == 0) + period_ps = period_vco; + else + period_ps = ps_in_ps * period_vco / 56.0; + end + + always @(clkfbm1pm_sel) + case (clkfbm1pm_sel) + 3'b000 : clkfbm1pm_rl = 0.0; + 3'b001 : clkfbm1pm_rl = 0.125; + 3'b010 : clkfbm1pm_rl = 0.25; + 3'b011 : clkfbm1pm_rl = 0.375; + 3'b100 : clkfbm1pm_rl = 0.50; + 3'b101 : clkfbm1pm_rl = 0.625; + 3'b110 : clkfbm1pm_rl = 0.75; + 3'b111 : clkfbm1pm_rl = 0.875; + endcase + + + always @(clkvco_lk) + clkvco_lk_dly_tmp <= #clkvco_delay clkvco_lk; + + always @(clkvco_lk_dly_tmp or clkvco_lk or pll_locked_tm) + if ( pll_locked_tm) begin + if (dly_tmp == 0) + clkvco = clkvco_lk; + else + clkvco = clkvco_lk_dly_tmp; + end + else + clkvco = 0; + + always @(clk0_ht or clk0_lt or clk0_nocnt or init_trig or clk0_edge) + clkout_pm_cal(clk0_ht1, clk0_div, clk0_div1, clk0_ht, clk0_lt, clk0_nocnt, clk0_edge); + always @(clk1_ht or clk1_lt or clk1_nocnt or init_trig or clk1_edge) + clkout_pm_cal(clk1_ht1, clk1_div, clk1_div1, clk1_ht, clk1_lt, clk1_nocnt, clk1_edge); + always @(clk2_ht or clk2_lt or clk2_nocnt or init_trig or clk2_edge) + clkout_pm_cal(clk2_ht1, clk2_div, clk2_div1, clk2_ht, clk2_lt, clk2_nocnt, clk2_edge); + always @(clk3_ht or clk3_lt or clk3_nocnt or init_trig or clk3_edge) + clkout_pm_cal(clk3_ht1, clk3_div, clk3_div1, clk3_ht, clk3_lt, clk3_nocnt, clk3_edge); + always @(clk4_ht or clk4_lt or clk4_nocnt or init_trig or clk4_edge) + clkout_pm_cal(clk4_ht1, clk4_div, clk4_div1, clk4_ht, clk4_lt, clk4_nocnt, clk4_edge); + always @(clk5_ht or clk5_lt or clk5_nocnt or init_trig or clk5_edge) + clkout_pm_cal(clk5_ht1, clk5_div, clk5_div1, clk5_ht, clk5_lt, clk5_nocnt, clk5_edge); + always @(clk6_ht or clk6_lt or clk6_nocnt or init_trig or clk6_edge) + clkout_pm_cal(clk6_ht1, clk6_div, clk6_div1, clk6_ht, clk6_lt, clk6_nocnt, clk6_edge); + always @(clkfbm1_ht or clkfbm1_lt or clkfbm1_nocnt or init_trig or clkfbm1_edge) + if (clkfb_frac_en) begin + clkfbm1_div = CLKFBOUT_MULT_F; + end + else + clkout_pm_cal(clkfbm1_ht1, clkfbm1_div, clkfbm1_div1, clkfbm1_ht, clkfbm1_lt, clkfbm1_nocnt, clkfbm1_edge); + always @(clkfbm2_ht or clkfbm2_lt or clkfbm2_nocnt or init_trig or clkfbm2_edge) + clkout_pm_cal(clkfbm2_ht1, clkfbm2_div, clkfbm2_div1, clkfbm2_ht, clkfbm2_lt, clkfbm2_nocnt, clkfbm2_edge); + always @(clkind_ht or clkind_lt or clkind_nocnt or init_trig or clkind_edge) + clkout_pm_cal(clkind_ht1, clkind_div, clkind_div1, clkind_ht, clkind_lt, clkind_nocnt, clkind_edge); + + always @(posedge psclk_in or posedge rst_in) + if (rst_in) begin + ps_in_ps <= ps_in_init; + ps_cnt <= 0; + end + else if (fps_en == 1) begin + if (psen_in) begin + if (ps_lock == 1) + $display(" Warning : Please wait for PSDONE signal before adjusting the Phase Shift."); + else if (psincdec_in == 1) begin + if (ps_cnt < ps_max) + ps_cnt <= ps_cnt + 1; + else + ps_cnt <= 0; + + if (ps_in_ps < ps_max) + ps_in_ps <= ps_in_ps + 1; + else + ps_in_ps <= 0; + + ps_lock <= 1; + end + else if (psincdec_in == 0) begin + ps_cnt_neg = (-1) * ps_cnt; + ps_in_ps_neg = (-1) * ps_in_ps; + if (ps_cnt_neg < ps_max) + ps_cnt <= ps_cnt - 1; + else + ps_cnt <= 0; + + if (ps_in_ps_neg < ps_max) + ps_in_ps <= ps_in_ps - 1; + else + ps_in_ps <= 0; + + ps_lock <= 1; + end + end + if ( psdone_out == 1) + ps_lock <= 0; + end + + always @(posedge ps_lock ) + if (fps_en == 1) begin + @(posedge psclk_in) + @(posedge psclk_in) + @(posedge psclk_in) + @(posedge psclk_in) + @(posedge psclk_in) + @(posedge psclk_in) + @(posedge psclk_in) + @(posedge psclk_in) + @(posedge psclk_in) + @(posedge psclk_in) + @(posedge psclk_in) + begin + psdone_out = 1; + @(posedge psclk_in); + psdone_out = 0; + end + end + + always @(rst_in_o) + if (rst_in_o) begin + assign clkout_mux = 8'b0; + assign clkout_ps_mux = 8'b0; + assign clkout_ps = 0; + assign clkout_ps_tmp1 = 0; + assign clkout_ps_tmp2 = 0; + assign clk0_frac_out = 0; + assign clkfbm1_frac_out = 0; + end + else begin + deassign clkout_mux; + deassign clkout_ps_mux; + deassign clkout_ps; + deassign clkout_ps_tmp1; + deassign clkout_ps_tmp2; + deassign clk0_frac_out; + deassign clkfbm1_frac_out; + end + + always @(rst_clkinstopped) + if (rst_clkinstopped) begin + assign clkfb_frac_ht = 50; + assign clkfb_frac_lt = 50; + end + else begin + deassign clkfb_frac_ht; + deassign clkfb_frac_lt; + end + + always @(clkvco or clkout_en ) + if (clkout_en) begin + clkout_mux[0] = clkvco; + clkout_mux[1] <= #(period_vco1) clkvco; + clkout_mux[2] <= #(period_vco2) clkvco; + clkout_mux[3] <= #(period_vco3) clkvco; + clkout_mux[4] <= #(period_vco4) clkvco; + clkout_mux[5] <= #(period_vco5) clkvco; + clkout_mux[6] <= #(period_vco6) clkvco; + clkout_mux[7] <= #(period_vco7) clkvco; + end + + always @(clkout_ps or clkout_en ) + if (clkout_en) begin + clkout_ps_mux[0] = clkout_ps; + clkout_ps_mux[1] <= #(period_vco1) clkout_ps; + clkout_ps_mux[2] <= #(period_vco2) clkout_ps; + clkout_ps_mux[3] <= #(period_vco3) clkout_ps; + clkout_ps_mux[4] <= #(period_vco4) clkout_ps; + clkout_ps_mux[5] <= #(period_vco5) clkout_ps; + clkout_ps_mux[6] <= #(period_vco6) clkout_ps; + clkout_ps_mux[7] <= #(period_vco7) clkout_ps; + end + + always @(clkvco or clkout_en ) + if ( fps_en == 1) begin + clkvco_ps_tmp1 <= #(period_ps) clkvco; + clkvco_ps_tmp2 <= #(period_ps_old) clkvco; + end + + always @(negedge clkout_ps) + clkout_ps_eg <= $time; + + always @(posedge clkout_ps) + clkout_ps_peg <= $time; + + always @(ps_lock) + ps_lock_dly <= #1 ps_lock; + + always @(posedge ps_lock_dly) + if ((period_ps - period_ps_old) > period_vco_half ) begin + if (clkout_ps == 0) begin + if (clkvco_ps_tmp2 == 1) begin + clkout_ps_w = $time - clkout_ps_eg; + if (clkout_ps_w > period_vco3) + clkvco_ps_tmp2_en <= 1; + else begin + @(negedge clkvco_ps_tmp2) + clkvco_ps_tmp2_en <= 1; + end + end + else + clkvco_ps_tmp2_en <= 1; + end + else begin + if (clkvco_ps_tmp2 == 0) begin + clkout_ps_w = $time - clkout_ps_peg; + if (clkout_ps_w > period_vco3) + clkvco_ps_tmp2_en <= 1; + else begin + @(posedge clkvco_ps_tmp2) + clkvco_ps_tmp2_en <= 1; + end + end + else + clkvco_ps_tmp2_en <= 1; + end + @(posedge clkvco_ps_tmp2); + @(negedge clkvco_ps_tmp2) + if (clkvco_ps_tmp1 == 0) + clkvco_ps_tmp2_en <= 0; + else + @(negedge clkvco_ps_tmp1) + clkvco_ps_tmp2_en <= 0; + end + + + always @(clkvco or clkvco_ps_tmp1 or clkvco_ps_tmp2 or clkvco_ps_tmp2_en ) + if (fps_en == 1) begin + if (ps_in_ps == 0 ) + clkout_ps = clkvco; + else if (clkvco_ps_tmp2_en == 1) + clkout_ps = clkvco_ps_tmp2; + else + clkout_ps = clkvco_ps_tmp1; + end + + + assign clk0in = (clk0_fps_en == 1) ? clkout_ps_mux[clk0pm_sel] : clkout_mux[clk0pm_sel1]; + assign clk1in = (clk1_fps_en == 1) ? clkout_ps_mux[clk1pm_sel] : clkout_mux[clk1pm_sel]; + assign clk2in = (clk2_fps_en == 1) ? clkout_ps_mux[clk2pm_sel] : clkout_mux[clk2pm_sel]; + assign clk3in = (clk3_fps_en == 1) ? clkout_ps_mux[clk3pm_sel] : clkout_mux[clk3pm_sel]; + assign clk4in = (clk4_fps_en == 1) ? clkout_ps_mux[clk4pm_sel] : ((clkout4_cascade_int == 1) ? clk6_out : clkout_mux[clk4pm_sel]); + assign clk5in = (clk5_fps_en == 1) ? clkout_ps_mux[clk5pm_sel] : clkout_mux[clk5pm_sel1]; + assign clk6in = (clk6_fps_en == 1) ? clkout_ps_mux[clk6pm_sel] : clkout_mux[clk6pm_sel1]; + assign clkfbm1in = (clkfb_fps_en == 1) ? clkout_ps_mux[clkfbm1pm_sel] : clkout_mux[clkfbm1pm_sel1]; + + assign clkfbm1pm_sel1 = (clkfb_frac_en) ? 3'b0 : clkfbm1pm_sel; + assign clk6pm_sel1 = (clkfb_frac_en) ? 3'b0 : clk6pm_sel; + assign clk0pm_sel1 = (clk0_frac_en) ? 3'b0 : clk0pm_sel; + assign clk5pm_sel1 = (clk0_frac_en) ? 3'b0 : clk5pm_sel; + + assign clk0ps_en = (clk0_dly_cnt == clkout0_dly) ? clkout_en : 0; + assign clk1ps_en = (clk1_dly_cnt == clkout1_dly) ? clkout_en : 0; + assign clk2ps_en = (clk2_dly_cnt == clkout2_dly) ? clkout_en : 0; + assign clk3ps_en = (clk3_dly_cnt == clkout3_dly) ? clkout_en : 0; + assign clk4ps_en = (clk4_dly_cnt == clkout4_dly) ? clkout_en : 0; + assign clk5ps_en = (clk5_dly_cnt == clkout5_dly) ? clkout_en : 0; + assign clk6ps_en = (clk6_dly_cnt == clkout6_dly) ? clkout_en : 0; + assign clkfbm1ps_en = (clkfbm1_dly_cnt == clkfbm1_dly) ? clkout_en : 0; + + always @(posedge clk0in) + if (clkout_en && clk0_frac_en) begin + clk0_frac_out <= 1; + for (ik0=1; ik0 < 8; ik0=ik0+1) begin + #(clk0_frac_ht) clk0_frac_out <= 0; + #(clk0_frac_lt) clk0_frac_out <= 1; + end + #(clk0_frac_ht) clk0_frac_out <= 0; +// #(clk0_frac_lt - 50); + #(clk0_frac_lt - period_vco1); + end + + always @(posedge clkfbm1in) + if (clkout_en && clkfb_frac_en) begin + clkfbm1_frac_out <= 1; + for (ib=1; ib < 8; ib=ib+1) begin + #(clkfb_frac_ht) clkfbm1_frac_out <= 0; + #(clkfb_frac_lt) clkfbm1_frac_out <= 1; + end + #(clkfb_frac_ht) clkfbm1_frac_out <= 0; + #(clkfb_frac_lt - period_vco1); + end + else + clkfbm1_frac_out <= 0; + + always @(negedge clk0in or posedge rst_in_o) + if (rst_in_o) + clk0_dly_cnt <= 6'b0; + else if (clkout_en == 1 && clk0_frac_en == 0) begin + if (clk0_dly_cnt < clkout0_dly) + clk0_dly_cnt <= clk0_dly_cnt + 1; + end + + always @(negedge clk1in or posedge rst_in_o) + if (rst_in_o) + clk1_dly_cnt <= 6'b0; + else + if (clk1_dly_cnt < clkout1_dly && clkout_en ==1) + clk1_dly_cnt <= clk1_dly_cnt + 1; + + always @(negedge clk2in or posedge rst_in_o) + if (rst_in_o) + clk2_dly_cnt <= 6'b0; + else + if (clk2_dly_cnt < clkout2_dly && clkout_en ==1) + clk2_dly_cnt <= clk2_dly_cnt + 1; + + always @(negedge clk3in or posedge rst_in_o) + if (rst_in_o) + clk3_dly_cnt <= 6'b0; + else + if (clk3_dly_cnt < clkout3_dly && clkout_en ==1) + clk3_dly_cnt <= clk3_dly_cnt + 1; + + always @(negedge clk4in or posedge rst_in_o) + if (rst_in_o) + clk4_dly_cnt <= 6'b0; + else + if (clk4_dly_cnt < clkout4_dly && clkout_en ==1) + clk4_dly_cnt <= clk4_dly_cnt + 1; + + always @(negedge clk5in or posedge rst_in_o) + if (rst_in_o) + clk5_dly_cnt <= 6'b0; + else if (clkout_en == 1 && clk0_frac_en == 0) begin + if (clk5_dly_cnt < clkout5_dly) + clk5_dly_cnt <= clk5_dly_cnt + 1; + end + + always @(negedge clk6in or posedge rst_in_o) + if (rst_in_o) + clk6_dly_cnt <= 6'b0; + else if (clkout_en == 1 && clkfb_frac_en == 0) begin + if (clk6_dly_cnt < clkout6_dly) + clk6_dly_cnt <= clk6_dly_cnt + 1; + end + + always @(negedge clkfbm1in or posedge rst_in_o) + if (rst_in_o) + clkfbm1_dly_cnt <= 6'b0; + else if (clkout_en == 1 && clkfb_frac_en == 0) begin + if (clkfbm1_dly_cnt < clkfbm1_dly) + clkfbm1_dly_cnt <= clkfbm1_dly_cnt + 1; + end + + always @(posedge clk0in or negedge clk0in or posedge rst_in_o) + if (rst_in_o) begin + clk0_cnt <= 8'b0; + clk0_nf_out <= 0; + end + else if (clk0ps_en && clk0_frac_en == 0) begin + if (clk0_cnt < clk0_div1) + clk0_cnt <= clk0_cnt + 1; + else + clk0_cnt <= 8'b0; + if (clk0_cnt < clk0_ht1) + clk0_nf_out <= 1; + else + clk0_nf_out <= 0; + end + else begin + clk0_cnt <= 8'b0; + clk0_nf_out <= 0; + end + + assign clk0_out = (clk0_frac_en) ? clk0_frac_out : clk0_nf_out; + + always @(posedge clk1in or negedge clk1in or posedge rst_in_o) + if (rst_in_o) begin + clk1_cnt <= 8'b0; + clk1_out <= 0; + end + else if (clk1ps_en) begin + if (clk1_cnt < clk1_div1) + clk1_cnt <= clk1_cnt + 1; + else + clk1_cnt <= 8'b0; + if (clk1_cnt < clk1_ht1) + clk1_out <= 1; + else + clk1_out <= 0; + end + else begin + clk1_cnt <= 8'b0; + clk1_out <= 0; + end + + always @(posedge clk2in or negedge clk2in or posedge rst_in_o) + if (rst_in_o) begin + clk2_cnt <= 8'b0; + clk2_out <= 0; + end + else if (clk2ps_en) begin + if (clk2_cnt < clk2_div1) + clk2_cnt <= clk2_cnt + 1; + else + clk2_cnt <= 8'b0; + if (clk2_cnt < clk2_ht1) + clk2_out <= 1; + else + clk2_out <= 0; + end + else begin + clk2_cnt <= 8'b0; + clk2_out <= 0; + end + + always @(posedge clk3in or negedge clk3in or posedge rst_in_o) + if (rst_in_o) begin + clk3_cnt <= 8'b0; + clk3_out <= 0; + end + else if (clk3ps_en) begin + if (clk3_cnt < clk3_div1) + clk3_cnt <= clk3_cnt + 1; + else + clk3_cnt <= 8'b0; + if (clk3_cnt < clk3_ht1) + clk3_out <= 1; + else + clk3_out <= 0; + end + else begin + clk3_cnt <= 8'b0; + clk3_out <= 0; + end + + + always @(posedge clk4in or negedge clk4in or posedge rst_in_o) + if (rst_in_o) begin + clk4_cnt <= 8'b0; + clk4_out <= 0; + end + else if (clk4ps_en) begin + if (clk4_cnt < clk4_div1) + clk4_cnt <= clk4_cnt + 1; + else + clk4_cnt <= 8'b0; + if (clk4_cnt < clk4_ht1) + clk4_out <= 1; + else + clk4_out <= 0; + end + else begin + clk4_cnt <= 8'b0; + clk4_out <= 0; + end + + always @(posedge clk5in or negedge clk5in or posedge rst_in_o) + if (rst_in_o) begin + clk5_cnt <= 8'b0; + clk5_out <= 0; + end + else if (clk5ps_en && clk0_frac_en == 0) begin + if (clk5_cnt < clk5_div1) + clk5_cnt <= clk5_cnt + 1; + else + clk5_cnt <= 8'b0; + if (clk5_cnt < clk5_ht1) + clk5_out <= 1; + else + clk5_out <= 0; + end + else begin + clk5_cnt <= 8'b0; + clk5_out <= 0; + end + + always @(posedge clk6in or negedge clk6in or posedge rst_in_o) + if (rst_in_o) begin + clk6_cnt <= 8'b0; + clk6_out <= 0; + end + else if (clk6ps_en && clkfb_frac_en == 0) begin + if (clk6_cnt < clk6_div1) + clk6_cnt <= clk6_cnt + 1; + else + clk6_cnt <= 8'b0; + if (clk6_cnt < clk6_ht1) + clk6_out <= 1; + else + clk6_out <= 0; + end + else begin + clk6_cnt <= 8'b0; + clk6_out <= 0; + end + + always @(posedge clkfbm1in or negedge clkfbm1in or posedge rst_in_o) + if (rst_in_o) begin + clkfbm1_cnt <= 8'b0; + clkfbm1_nf_out <= 0; + end + else if (clkfbm1ps_en && clkfb_frac_en == 0) begin + if (clkfbm1_cnt < clkfbm1_div1) + clkfbm1_cnt <= clkfbm1_cnt + 1; + else + clkfbm1_cnt <= 8'b0; + if (clkfbm1_cnt < clkfbm1_ht1) + clkfbm1_nf_out <= 1; + else + clkfbm1_nf_out <= 0; + end + else begin + clkfbm1_cnt <= 8'b0; + clkfbm1_nf_out <= 0; + end + + assign clkfbm1_out = (clkfb_frac_en) ? clkfbm1_frac_out : clkfbm1_nf_out; + + always @(posedge clkfb_in or negedge clkfb_in or posedge rst_in) + if (rst_in) begin + clkfbm2_cnt <= 8'b0; + clkfbm2_out <= 0; + end + else if (clkout_en) begin + if (clkfbm2_cnt < clkfbm2_div1) + clkfbm2_cnt <= clkfbm2_cnt + 1; + else + clkfbm2_cnt <= 8'b0; + if (clkfbm2_cnt < clkfbm2_ht1) + clkfbm2_out <= 1; + else + clkfbm2_out <= 0; + end + else begin + clkfbm2_cnt <= 8'b0; + clkfbm2_out <= 0; + end + + always @(posedge clkpll_r or negedge clkpll_r or posedge rst_in) + if (rst_in) begin + clkind_cnt <= 8'b0; + clkind_out <= 0; + end + else if (clkout_en) begin + if (clkind_cnt < clkind_div1) + clkind_cnt <= clkind_cnt + 1; + else + clkind_cnt <= 8'b0; + if (clkind_cnt < clkind_ht1) + clkind_out <= 1; + else + clkind_out <= 0; + end + else begin + clkind_cnt <= 8'b0; + clkind_out <= 0; + end + + always @(clk0_out or clkfb_tst or fb_delay_found) + if (fb_delay_found == 1) + clkout0_out = clk0_out; + else + clkout0_out = clkfb_tst; + + always @(clk1_out or clkfb_tst or fb_delay_found) + if (fb_delay_found == 1) + clkout1_out = clk1_out; + else + clkout1_out = clkfb_tst; + + always @(clk2_out or clkfb_tst or fb_delay_found) + if (fb_delay_found == 1) + clkout2_out = clk2_out; + else + clkout2_out = clkfb_tst; + + always @(clk3_out or clkfb_tst or fb_delay_found) + if (fb_delay_found == 1) + clkout3_out = clk3_out; + else + clkout3_out = clkfb_tst; + + always @(clk4_out or clkfb_tst or fb_delay_found) + if (fb_delay_found == 1) + clkout4_out = clk4_out; + else + clkout4_out = clkfb_tst; + + always @(clk5_out or clkfb_tst or fb_delay_found) + if (fb_delay_found == 1) + clkout5_out = clk5_out; + else + clkout5_out = clkfb_tst; + + always @(clk6_out or clkfb_tst or fb_delay_found) + if (fb_delay_found == 1) + clkout6_out = clk6_out; + else + clkout6_out = clkfb_tst; + + always @(clkfbm1_out or clkfb_tst or fb_delay_found) + if (fb_delay_found == 1) + clkfb_out = clkfbm1_out; + else + clkfb_out = clkfb_tst; + + // + // determine feedback delay + // + +// always @(rst_in) +// if (rst_in) +// assign clkfb_tst = 0; +// else +// deassign clkfb_tst; + + always @(posedge clkpll_r ) + if (fb_delay_found_tmp == 0 && pwron_int == 0 && rst_in == 0) begin + clkfb_tst <= 1'b1; + end + else + clkfb_tst <= 1'b0; + + always @( posedge clkfb_tst or posedge rst_in ) + if (rst_in) + delay_edge <= 0; + else + delay_edge <= $time; + + always @(posedge clkfb_in or posedge rst_in ) + if (rst_in) begin + fb_delay <= 0; + fb_delay_found_tmp <= 0; + end + else + if (fb_delay_found_tmp ==0 ) begin + if ( delay_edge != 0) + fb_delay <= ($time - delay_edge); + else + fb_delay <= 0; + fb_delay_found_tmp <= 1; + end + + always @(rst_in) + if (rst_in) + assign fb_delay_found = 0; + else + deassign fb_delay_found; + + always @(fb_delay_found_tmp or clkvco_delay ) + if (clkvco_delay == 0) + fb_delay_found <= #1000 fb_delay_found_tmp; + else + fb_delay_found <= #(clkvco_delay) fb_delay_found_tmp; + + always @(fb_delay) + if (rst_in==0 && (fb_delay/1000.0 > fb_delay_max)) begin + $display("Warning : The feedback delay on MMCM_ADV instance %m at time %t is %f ns. It is over the maximun value %f ns.", $time, fb_delay / 1000.0, fb_delay_max); + end + + // + // generate unlock signal + // + + always @(clk_osc or rst_in) + if (rst_in) + clk_osc <= 0; + else + clk_osc <= #OSC_P2 ~clk_osc; + + always @(posedge clkpll_r or negedge clkpll_r) begin + clkin_p <= 1; + clkin_p <= #100 0; + end + + always @(posedge clkfb_in or negedge clkfb_in) begin + clkfb_p <= 1; + clkfb_p <= #100 0; + end + + + always @(posedge clk_osc or posedge rst_in or posedge clkin_p) + if (rst_in == 1 || clkin_p == 1) begin + clkinstopped_out <= 0; + clkin_lost_cnt <= 0; + end + else if (lock_period) begin + if (clkin_lost_cnt < clkin_lost_val) begin + clkin_lost_cnt <= clkin_lost_cnt + 1; + clkinstopped_out <= 0; + end + else + clkinstopped_out <= 1; + end + + always @(posedge clk_osc or posedge rst_in or posedge clkfb_p) + if (rst_in == 1 || clkfb_p == 1) begin + clkfbstopped_out <= 0; + clkfb_lost_cnt <= 0; + end + else if (clkout_en) begin + if (clkfb_lost_cnt < clkfb_lost_val) begin + clkfb_lost_cnt <= clkfb_lost_cnt + 1; + clkfbstopped_out <= 0; + end + else + clkfbstopped_out <= 1; + end + + + always @(clkin_jit or rst_in ) + if (rst_in) + clkpll_jitter_unlock = 0; + else + if (pll_locked_tmp2 && clkfbstopped_out == 0 && clkinstopped_out == 0) begin + if ((clkin_jit > REF_CLK_JITTER_MAX_tmp && clkin_jit < period_avg) || + (clkin_jit < -REF_CLK_JITTER_MAX_tmp && clkin_jit > -period_avg )) + clkpll_jitter_unlock = 1; + else + clkpll_jitter_unlock = 0; + end + else + clkpll_jitter_unlock = 0; + + assign pll_unlock1 = (clkinstopped_out_dly ==1 || clkfbstopped_out==1 || clkpll_jitter_unlock == 1) ? 1 : 0; + assign pll_unlock = (clkinstopped_out_dly ==1 || clkfbstopped_out==1 || clkpll_jitter_unlock == 1 || unlock_recover == 1) ? 1 : 0; + + // tasks + + task clkout_dly_cal; + output [5:0] clkout_dly; + output [2:0] clkpm_sel; + input clkdiv; + input clk_ps; + input reg [160:0] clk_ps_name; + integer clkdiv; + real clk_ps; + real clk_ps_rl; + real clk_dly_rl, clk_dly_rem; + integer clkout_dly_tmp; + begin + if (clk_ps < 0.0) + clk_dly_rl = (360.0 + clk_ps) * clkdiv / 360.0; + else + clk_dly_rl = clk_ps * clkdiv / 360.0; + + clkout_dly_tmp = $rtoi(clk_dly_rl); + + if (clkout_dly_tmp > 63) begin + $display(" Warning : Attribute %s of MMCM_ADV on instance %m is set to %f. Required phase shifting can not be reached since it is over the maximum phase shifting ability of MMCM_ADV", clk_ps_name, clk_ps); + clkout_dly = 6'b111111; + end + else + clkout_dly = clkout_dly_tmp; + + clk_dly_rem = clk_dly_rl - clkout_dly; + + if (clk_dly_rem < 0.125) + clkpm_sel = 0; + else if (clk_dly_rem >= 0.125 && clk_dly_rem < 0.25) + clkpm_sel = 1; + else if (clk_dly_rem >= 0.25 && clk_dly_rem < 0.375) + clkpm_sel = 2; + else if (clk_dly_rem >= 0.375 && clk_dly_rem < 0.5) + clkpm_sel = 3; + else if (clk_dly_rem >= 0.5 && clk_dly_rem < 0.625) + clkpm_sel = 4; + else if (clk_dly_rem >= 0.625 && clk_dly_rem < 0.75) + clkpm_sel = 5; + else if (clk_dly_rem >= 0.75 && clk_dly_rem < 0.875) + clkpm_sel = 6; + else if (clk_dly_rem >= 0.875 ) + clkpm_sel = 7; + + if (clk_ps < 0.0) + clk_ps_rl = (clkout_dly + 0.125 * clkpm_sel)* 360.0 / clkdiv - 360.0; + else + clk_ps_rl = (clkout_dly + 0.125 * clkpm_sel) * 360.0 / clkdiv; + + if (((clk_ps_rl- clk_ps) > 0.001) || ((clk_ps_rl- clk_ps) < -0.001)) + $display(" Warning : Attribute %s of MMCM_ADV on instance %m is set to %f. Real phase shifting is %f. Required phase shifting can not be reached.", clk_ps_name, clk_ps, clk_ps_rl); + + end + endtask + + task clk_out_para_cal; + output [6:0] clk_ht; + output [6:0] clk_lt; + output clk_nocnt; + output clk_edge; + input CLKOUT_DIVIDE; + input CLKOUT_DUTY_CYCLE; + integer CLKOUT_DIVIDE; + real CLKOUT_DUTY_CYCLE; + real tmp_value, tmp_value0, tmp_value_rm; + integer tmp_value1, tmp_value_r; + real tmp_value2; + real tmp_value_rm1, tmp_value_r1; + integer tmp_value_r2; + begin + + tmp_value0 = CLKOUT_DIVIDE * CLKOUT_DUTY_CYCLE; + tmp_value_r = $rtoi(tmp_value0); + tmp_value_rm = tmp_value0 - tmp_value_r; + if (tmp_value_rm < 0.1) + tmp_value = tmp_value_r * 1.0; + else if (tmp_value_rm > 0.9) + tmp_value = 1.0 * tmp_value_r + 1.0; + else begin + tmp_value_r1 = tmp_value0 * 2.0; + tmp_value_r2 = $rtoi(tmp_value_r1); + tmp_value_rm1 = tmp_value_r1 - tmp_value_r2; + if (tmp_value_rm1 > 0.995) + tmp_value = tmp_value0 + 0.002; + else + tmp_value = tmp_value0; + end + tmp_value1 = $rtoi(tmp_value * 2.0) % 2; + tmp_value2 = CLKOUT_DIVIDE - tmp_value; + + + if ((tmp_value2) >= O_MAX_HT_LT) begin + clk_lt = 7'b1000000; + end + else begin + if (tmp_value2 < 1.0) + clk_lt = 1; + else + if ( tmp_value1 != 0) + clk_lt = $rtoi(tmp_value2) + 1; + else + clk_lt = $rtoi(tmp_value2); + end + + if ( (CLKOUT_DIVIDE - clk_lt) >= O_MAX_HT_LT) + clk_ht = 7'b1000000; + else + clk_ht = CLKOUT_DIVIDE - clk_lt; + + clk_nocnt = (CLKOUT_DIVIDE ==1) ? 1 : 0; + if ( tmp_value < 1.0) + clk_edge = 1; + else if (tmp_value1 != 0) + clk_edge = 1; + else + clk_edge = 0; + end + endtask + + function clkout_duty_chk; + input CLKOUT_DIVIDE; + input CLKOUT_DUTY_CYCLE; + input reg [160:0] CLKOUT_DUTY_CYCLE_N; + integer CLKOUT_DIVIDE, step_tmp; + real CLKOUT_DUTY_CYCLE; + real CLK_DUTY_CYCLE_MIN, CLK_DUTY_CYCLE_MAX, CLK_DUTY_CYCLE_STEP; + real CLK_DUTY_CYCLE_MIN_rnd; + reg clk_duty_tmp_int; + begin + if (CLKOUT_DIVIDE > O_MAX_HT_LT) begin + CLK_DUTY_CYCLE_MIN = (CLKOUT_DIVIDE - O_MAX_HT_LT)/CLKOUT_DIVIDE; + CLK_DUTY_CYCLE_MAX = (O_MAX_HT_LT + 0.5)/CLKOUT_DIVIDE; + CLK_DUTY_CYCLE_MIN_rnd = CLK_DUTY_CYCLE_MIN; + end + else begin + if (CLKOUT_DIVIDE == 1) begin + CLK_DUTY_CYCLE_MIN = 0.0; + CLK_DUTY_CYCLE_MIN_rnd = 0.0; + end + else begin + step_tmp = 1000 / CLKOUT_DIVIDE; + CLK_DUTY_CYCLE_MIN_rnd = step_tmp / 1000.0; + CLK_DUTY_CYCLE_MIN = 1.0 /CLKOUT_DIVIDE; + end + CLK_DUTY_CYCLE_MAX = 1.0; + end + + if (CLKOUT_DUTY_CYCLE > CLK_DUTY_CYCLE_MAX || CLKOUT_DUTY_CYCLE < CLK_DUTY_CYCLE_MIN_rnd) begin + $display(" Attribute Syntax Warning : %s is set to %f on instance %m and is not in the allowed range %f to %f.", CLKOUT_DUTY_CYCLE_N, CLKOUT_DUTY_CYCLE, CLK_DUTY_CYCLE_MIN, CLK_DUTY_CYCLE_MAX ); + end + + clk_duty_tmp_int = 0; + CLK_DUTY_CYCLE_STEP = 0.5 / CLKOUT_DIVIDE; + for (j = 0; j < (2 * CLKOUT_DIVIDE - CLK_DUTY_CYCLE_MIN/CLK_DUTY_CYCLE_STEP); j = j + 1) + if (((CLK_DUTY_CYCLE_MIN + CLK_DUTY_CYCLE_STEP * j) - CLKOUT_DUTY_CYCLE) > -0.001 && + ((CLK_DUTY_CYCLE_MIN + CLK_DUTY_CYCLE_STEP * j) - CLKOUT_DUTY_CYCLE) < 0.001) + clk_duty_tmp_int = 1; + + if ( clk_duty_tmp_int != 1) begin + $display(" Attribute Syntax Warning : %s is set to %f on instance %m and is not an allowed value. Allowed values are:", CLKOUT_DUTY_CYCLE_N, CLKOUT_DUTY_CYCLE); + for (j = 0; j < (2 * CLKOUT_DIVIDE - CLK_DUTY_CYCLE_MIN/CLK_DUTY_CYCLE_STEP); j = j + 1) + $display("%f", CLK_DUTY_CYCLE_MIN + CLK_DUTY_CYCLE_STEP * j); + end + + clkout_duty_chk = 1'b1; + end + endfunction + + function para_int_range_chk; + input para_in; + input reg [160:0] para_name; + input range_low; + input range_high; + integer para_in; + integer range_low; + integer range_high; + begin + if ( para_in < range_low || para_in > range_high) begin + $display("Attribute Syntax Error : The Attribute %s on MMCM_ADV instance %m is set to %d. Legal values for this attribute are %d to %d.", para_name, para_in, range_low, range_high); + $finish; + end + para_int_range_chk = 1'b1; + end + endfunction + + function para_real_range_chk; + input para_in; + input reg [160:0] para_name; + input range_low; + input range_high; + real para_in; + real range_low; + real range_high; + begin + if ( para_in < range_low || para_in > range_high) begin + $display("Attribute Syntax Error : The Attribute %s on MMCM_ADV instance %m is set to %f. Legal values for this attribute are %f to %f.", para_name, para_in, range_low, range_high); + $finish; + end + para_real_range_chk = 1'b0; + end + endfunction + + task clkout_pm_cal; + output [7:0] clk_ht1; + output [7:0] clk_div; + output [7:0] clk_div1; + input [6:0] clk_ht; + input [6:0] clk_lt; + input clk_nocnt; + input clk_edge; + begin + if (clk_nocnt ==1) begin + clk_div = 8'b00000001; + clk_div1 = 8'b00000001; + clk_ht1 = 8'b00000001; + end + else begin + if ( clk_edge == 1) + clk_ht1 = 2 * clk_ht + 1; + else + clk_ht1 = 2 * clk_ht; + clk_div = clk_ht + clk_lt ; + clk_div1 = 2 * clk_div -1; + end + end + endtask + + task clkout_delay_para_drp; + output [5:0] clkout_dly; + output clk_nocnt; + output clk_edge; + input [15:0] di_in; + input [6:0] daddr_in; + begin + clkout_dly = di_in[5:0]; + clk_nocnt = di_in[6]; + clk_edge = di_in[7]; + end + endtask + + task clkout_hl_para_drp; + output [6:0] clk_lt; + output [6:0] clk_ht; + output [2:0] clkpm_sel; + input [15:0] di_in_tmp; + input [6:0] daddr_in_tmp; + begin + if (di_in_tmp[12] != 1) begin + $display(" Error : MMCM_ADV on instance %m input DI is %h at address DADDR=%b at time %t. The bit 12 need to be set to 1 .", di_in_tmp, daddr_in_tmp, $time); + end + if ( di_in_tmp[5:0] == 6'b0) + clk_lt = 7'b1000000; + else + clk_lt = { 1'b0, di_in_tmp[5:0]}; + if (di_in_tmp[11:6] == 6'b0) + clk_ht = 7'b1000000; + else + clk_ht = { 1'b0, di_in_tmp[11:6]}; + clkpm_sel = di_in_tmp[15:13]; + end + endtask + + +endmodule diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/MMCM_BASE.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/MMCM_BASE.v new file mode 100644 index 0000000..08626ac --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/MMCM_BASE.v @@ -0,0 +1,171 @@ +/////////////////////////////////////////////////////// +// Copyright (c) 2008 Xilinx Inc. +// All Right Reserved. +/////////////////////////////////////////////////////// +// +// ____ ___ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : +// / / +// /__/ /\ Filename : MMCM_BASE.v +// \ \ / \ +// \__\/\__ \ +// +// Revision: 1.0 +// 01/06/09 Change CLKIN to CLKIN1 (CR502299) +// 09/02/09 - update REF_JITTER1 value to 0.010. +// 03/22/10 - Change CLKFBOUT_MULT_F default to 5 (554618) +/////////////////////////////////////////////////////// + +`timescale 1 ps / 1 ps + +module MMCM_BASE ( + CLKFBOUT, + CLKFBOUTB, + CLKOUT0, + CLKOUT0B, + CLKOUT1, + CLKOUT1B, + CLKOUT2, + CLKOUT2B, + CLKOUT3, + CLKOUT3B, + CLKOUT4, + CLKOUT5, + CLKOUT6, + LOCKED, + CLKFBIN, + CLKIN1, + PWRDWN, + RST +); + + parameter BANDWIDTH = "OPTIMIZED"; + parameter real CLKFBOUT_MULT_F = 5.000; + parameter real CLKFBOUT_PHASE = 0.000; + parameter real CLKIN1_PERIOD = 0.000; + parameter real CLKOUT0_DIVIDE_F = 1.000; + parameter real CLKOUT0_DUTY_CYCLE = 0.500; + parameter real CLKOUT0_PHASE = 0.000; + parameter integer CLKOUT1_DIVIDE = 1; + parameter real CLKOUT1_DUTY_CYCLE = 0.500; + parameter real CLKOUT1_PHASE = 0.000; + parameter integer CLKOUT2_DIVIDE = 1; + parameter real CLKOUT2_DUTY_CYCLE = 0.500; + parameter real CLKOUT2_PHASE = 0.000; + parameter integer CLKOUT3_DIVIDE = 1; + parameter real CLKOUT3_DUTY_CYCLE = 0.500; + parameter real CLKOUT3_PHASE = 0.000; + parameter CLKOUT4_CASCADE = "FALSE"; + parameter integer CLKOUT4_DIVIDE = 1; + parameter real CLKOUT4_DUTY_CYCLE = 0.500; + parameter real CLKOUT4_PHASE = 0.000; + parameter integer CLKOUT5_DIVIDE = 1; + parameter real CLKOUT5_DUTY_CYCLE = 0.500; + parameter real CLKOUT5_PHASE = 0.000; + parameter integer CLKOUT6_DIVIDE = 1; + parameter real CLKOUT6_DUTY_CYCLE = 0.500; + parameter real CLKOUT6_PHASE = 0.000; + parameter CLOCK_HOLD = "FALSE"; + parameter integer DIVCLK_DIVIDE = 1; + parameter real REF_JITTER1 = 0.010; + parameter STARTUP_WAIT = "FALSE"; + + output CLKFBOUT; + output CLKFBOUTB; + output CLKOUT0; + output CLKOUT0B; + output CLKOUT1; + output CLKOUT1B; + output CLKOUT2; + output CLKOUT2B; + output CLKOUT3; + output CLKOUT3B; + output CLKOUT4; + output CLKOUT5; + output CLKOUT6; + output LOCKED; + + input CLKFBIN; + input CLKIN1; + input PWRDWN; + input RST; + + wire OPEN_DRDY; + wire OPEN_PSDONE; + wire OPEN_FBS; + wire OPEN_INS; + wire [15:0] OPEN_DO; + + MMCM_ADV #( + .BANDWIDTH(BANDWIDTH), + .CLKOUT4_CASCADE(CLKOUT4_CASCADE), + .CLOCK_HOLD(CLOCK_HOLD), + .STARTUP_WAIT(STARTUP_WAIT), + .CLKOUT1_DIVIDE(CLKOUT1_DIVIDE), + .CLKOUT2_DIVIDE(CLKOUT2_DIVIDE), + .CLKOUT3_DIVIDE(CLKOUT3_DIVIDE), + .CLKOUT4_DIVIDE(CLKOUT4_DIVIDE), + .CLKOUT5_DIVIDE(CLKOUT5_DIVIDE), + .CLKOUT6_DIVIDE(CLKOUT6_DIVIDE), + .DIVCLK_DIVIDE(DIVCLK_DIVIDE), + .CLKFBOUT_MULT_F(CLKFBOUT_MULT_F), + .CLKFBOUT_PHASE(CLKFBOUT_PHASE), + .CLKIN1_PERIOD(CLKIN1_PERIOD), + .CLKIN2_PERIOD(10), + .CLKOUT0_DIVIDE_F(CLKOUT0_DIVIDE_F), + .CLKOUT0_DUTY_CYCLE(CLKOUT0_DUTY_CYCLE), + .CLKOUT0_PHASE(CLKOUT0_PHASE), + .CLKOUT1_DUTY_CYCLE(CLKOUT1_DUTY_CYCLE), + .CLKOUT1_PHASE(CLKOUT1_PHASE), + .CLKOUT2_DUTY_CYCLE(CLKOUT2_DUTY_CYCLE), + .CLKOUT2_PHASE(CLKOUT2_PHASE), + .CLKOUT3_DUTY_CYCLE(CLKOUT3_DUTY_CYCLE), + .CLKOUT3_PHASE(CLKOUT3_PHASE), + .CLKOUT4_DUTY_CYCLE(CLKOUT4_DUTY_CYCLE), + .CLKOUT4_PHASE(CLKOUT4_PHASE), + .CLKOUT5_DUTY_CYCLE(CLKOUT5_DUTY_CYCLE), + .CLKOUT5_PHASE(CLKOUT5_PHASE), + .CLKOUT6_DUTY_CYCLE(CLKOUT6_DUTY_CYCLE), + .CLKOUT6_PHASE(CLKOUT6_PHASE), + .REF_JITTER1(REF_JITTER1) + ) + mmcm_adv_1 ( + .CLKFBIN (CLKFBIN), + .CLKFBOUT (CLKFBOUT), + .CLKFBOUTB (CLKFBOUTB), + .CLKIN1 (CLKIN1), + .CLKIN2 (1'b0), + .CLKOUT0 (CLKOUT0), + .CLKOUT0B (CLKOUT0B), + .CLKOUT1 (CLKOUT1), + .CLKOUT1B (CLKOUT1B), + .CLKOUT2 (CLKOUT2), + .CLKOUT2B (CLKOUT2B), + .CLKOUT3 (CLKOUT3), + .CLKOUT3B (CLKOUT3B), + .CLKOUT4 (CLKOUT4), + .CLKOUT5 (CLKOUT5), + .CLKOUT6 (CLKOUT6), + .DADDR (7'b0), + .DCLK (1'b0), + .DEN (1'b0), + .DI (16'b0), + .DO (OPEN_DO), + .DRDY (OPEN_DRDY), + .DWE (1'b0), + .LOCKED (LOCKED), + .CLKINSEL(1'b1), + .CLKFBSTOPPED(OPEN_FBS), + .CLKINSTOPPED(OPEN_INS), + .PSDONE(OPEN_PSDONE), + .PSCLK(1'b0), + .PSEN(1'b0), + .PSINCDEC(1'b0), + .PWRDWN(PWRDWN), + .RST (RST) + ); + +endmodule diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/MULT18X18.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/MULT18X18.v new file mode 100644 index 0000000..231fcda --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/MULT18X18.v @@ -0,0 +1,145 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/MULT18X18.v,v 1.9 2006/02/08 23:28:02 fphillip Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / 18X18 Signed Multiplier +// /___/ /\ Filename : MULT18X18.v +// \ \ / \ Timestamp : Thu Mar 25 16:42:54 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 02/08/06 - Reversed from I.26 to H.42 model -- CR 224617 +// End Revision + +`timescale 1 ps / 1 ps + +module MULT18X18 (P, A, B); + + output [35:0] P; + + input [17:0] A; + input [17:0] B; + + wire [35:0] a_in, b_in; + reg [35:0] p_out; + wire p0_out, p1_out, p2_out, p3_out, p4_out, p5_out, p6_out, p7_out, p8_out, p9_out, p10_out, p11_out, p12_out, p13_out, p14_out, p15_out, p16_out, p17_out, p18_out, p19_out, p20_out, p21_out, p22_out, p23_out, p24_out, p25_out, p26_out, p27_out, p28_out, p29_out, p30_out, p31_out, p32_out, p33_out, p34_out, p35_out; + + buf A0 (a_in[0], A[0]); + buf A1 (a_in[1], A[1]); + buf A2 (a_in[2], A[2]); + buf A3 (a_in[3], A[3]); + buf A4 (a_in[4], A[4]); + buf A5 (a_in[5], A[5]); + buf A6 (a_in[6], A[6]); + buf A7 (a_in[7], A[7]); + buf A8 (a_in[8], A[8]); + buf A9 (a_in[9], A[9]); + buf A10 (a_in[10], A[10]); + buf A11 (a_in[11], A[11]); + buf A12 (a_in[12], A[12]); + buf A13 (a_in[13], A[13]); + buf A14 (a_in[14], A[14]); + buf A15 (a_in[15], A[15]); + buf A16 (a_in[16], A[16]); + buf A17 (a_in[17], A[17]); + buf A18 (a_in[18], A[17]); + buf A19 (a_in[19], A[17]); + buf A20 (a_in[20], A[17]); + buf A21 (a_in[21], A[17]); + buf A22 (a_in[22], A[17]); + buf A23 (a_in[23], A[17]); + buf A24 (a_in[24], A[17]); + buf A25 (a_in[25], A[17]); + buf A26 (a_in[26], A[17]); + buf A27 (a_in[27], A[17]); + buf A28 (a_in[28], A[17]); + buf A29 (a_in[29], A[17]); + buf A30 (a_in[30], A[17]); + buf A31 (a_in[31], A[17]); + buf A32 (a_in[32], A[17]); + buf A33 (a_in[33], A[17]); + buf A34 (a_in[34], A[17]); + buf A35 (a_in[35], A[17]); + buf B0 (b_in[0], B[0]); + buf B1 (b_in[1], B[1]); + buf B2 (b_in[2], B[2]); + buf B3 (b_in[3], B[3]); + buf B4 (b_in[4], B[4]); + buf B5 (b_in[5], B[5]); + buf B6 (b_in[6], B[6]); + buf B7 (b_in[7], B[7]); + buf B8 (b_in[8], B[8]); + buf B9 (b_in[9], B[9]); + buf B10 (b_in[10], B[10]); + buf B11 (b_in[11], B[11]); + buf B12 (b_in[12], B[12]); + buf B13 (b_in[13], B[13]); + buf B14 (b_in[14], B[14]); + buf B15 (b_in[15], B[15]); + buf B16 (b_in[16], B[16]); + buf B17 (b_in[17], B[17]); + buf B18 (b_in[18], B[17]); + buf B19 (b_in[19], B[17]); + buf B20 (b_in[20], B[17]); + buf B21 (b_in[21], B[17]); + buf B22 (b_in[22], B[17]); + buf B23 (b_in[23], B[17]); + buf B24 (b_in[24], B[17]); + buf B25 (b_in[25], B[17]); + buf B26 (b_in[26], B[17]); + buf B27 (b_in[27], B[17]); + buf B28 (b_in[28], B[17]); + buf B29 (b_in[29], B[17]); + buf B30 (b_in[30], B[17]); + buf B31 (b_in[31], B[17]); + buf B32 (b_in[32], B[17]); + buf B33 (b_in[33], B[17]); + buf B34 (b_in[34], B[17]); + buf B35 (b_in[35], B[17]); + buf P0 (P[0], p0_out); + buf P1 (P[1], p1_out); + buf P2 (P[2], p2_out); + buf P3 (P[3], p3_out); + buf P4 (P[4], p4_out); + buf P5 (P[5], p5_out); + buf P6 (P[6], p6_out); + buf P7 (P[7], p7_out); + buf P8 (P[8], p8_out); + buf P9 (P[9], p9_out); + buf P10 (P[10], p10_out); + buf P11 (P[11], p11_out); + buf P12 (P[12], p12_out); + buf P13 (P[13], p13_out); + buf P14 (P[14], p14_out); + buf P15 (P[15], p15_out); + buf P16 (P[16], p16_out); + buf P17 (P[17], p17_out); + buf P18 (P[18], p18_out); + buf P19 (P[19], p19_out); + buf P20 (P[20], p20_out); + buf P21 (P[21], p21_out); + buf P22 (P[22], p22_out); + buf P23 (P[23], p23_out); + buf P24 (P[24], p24_out); + buf P25 (P[25], p25_out); + buf P26 (P[26], p26_out); + buf P27 (P[27], p27_out); + buf P28 (P[28], p28_out); + buf P29 (P[29], p29_out); + buf P30 (P[30], p30_out); + buf P31 (P[31], p31_out); + buf P32 (P[32], p32_out); + buf P33 (P[33], p33_out); + buf P34 (P[34], p34_out); + buf P35 (P[35], p35_out); + + assign {p35_out, p34_out, p33_out, p32_out, p31_out, p30_out, p29_out, p28_out, p27_out, p26_out, p25_out, p24_out, p23_out, p22_out, p21_out, p20_out, p19_out, p18_out, p17_out, p16_out, p15_out, p14_out, p13_out, p12_out, p11_out, p10_out, p9_out, p8_out, p7_out, p6_out, p5_out, p4_out, p3_out, p2_out, p1_out, p0_out} = a_in * b_in; + +endmodule diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/MULT18X18S.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/MULT18X18S.v new file mode 100644 index 0000000..a5db11d --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/MULT18X18S.v @@ -0,0 +1,164 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/MULT18X18S.v,v 1.10 2006/01/11 08:27:07 fphillip Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / 18X18 Signed Registered Multiplier +// /___/ /\ Filename : MULT18X18S.v +// \ \ / \ Timestamp : Thu Mar 25 16:42:54 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 01/10/06 - Reversed from I.25 to H.42 model -- CR 223831 +// End Revision + +`timescale 1 ps / 1 ps + + +module MULT18X18S (P, A, B, C, CE, R); + + output [35:0] P; + + input [17:0] A; + input [17:0] B; + input C, CE, R; + + wire [35:0] a_in, b_in; + wire [35:0] p_in; + reg [35:0] p_out; + + wire p0_out, p1_out, p2_out, p3_out, p4_out, p5_out, p6_out, p7_out, p8_out, p9_out, p10_out, p11_out, p12_out, p13_out, p14_out, p15_out, p16_out, p17_out, p18_out, p19_out, p20_out, p21_out, p22_out, p23_out, p24_out, p25_out, p26_out, p27_out, p28_out, p29_out, p30_out, p31_out, p32_out, p33_out, p34_out, p35_out; + + tri0 GSR = glbl.GSR; + + buf A0 (a_in[0], A[0]); + buf A1 (a_in[1], A[1]); + buf A2 (a_in[2], A[2]); + buf A3 (a_in[3], A[3]); + buf A4 (a_in[4], A[4]); + buf A5 (a_in[5], A[5]); + buf A6 (a_in[6], A[6]); + buf A7 (a_in[7], A[7]); + buf A8 (a_in[8], A[8]); + buf A9 (a_in[9], A[9]); + buf A10 (a_in[10], A[10]); + buf A11 (a_in[11], A[11]); + buf A12 (a_in[12], A[12]); + buf A13 (a_in[13], A[13]); + buf A14 (a_in[14], A[14]); + buf A15 (a_in[15], A[15]); + buf A16 (a_in[16], A[16]); + buf A17 (a_in[17], A[17]); + buf A18 (a_in[18], A[17]); + buf A19 (a_in[19], A[17]); + buf A20 (a_in[20], A[17]); + buf A21 (a_in[21], A[17]); + buf A22 (a_in[22], A[17]); + buf A23 (a_in[23], A[17]); + buf A24 (a_in[24], A[17]); + buf A25 (a_in[25], A[17]); + buf A26 (a_in[26], A[17]); + buf A27 (a_in[27], A[17]); + buf A28 (a_in[28], A[17]); + buf A29 (a_in[29], A[17]); + buf A30 (a_in[30], A[17]); + buf A31 (a_in[31], A[17]); + buf A32 (a_in[32], A[17]); + buf A33 (a_in[33], A[17]); + buf A34 (a_in[34], A[17]); + buf A35 (a_in[35], A[17]); + buf B0 (b_in[0], B[0]); + buf B1 (b_in[1], B[1]); + buf B2 (b_in[2], B[2]); + buf B3 (b_in[3], B[3]); + buf B4 (b_in[4], B[4]); + buf B5 (b_in[5], B[5]); + buf B6 (b_in[6], B[6]); + buf B7 (b_in[7], B[7]); + buf B8 (b_in[8], B[8]); + buf B9 (b_in[9], B[9]); + buf B10 (b_in[10], B[10]); + buf B11 (b_in[11], B[11]); + buf B12 (b_in[12], B[12]); + buf B13 (b_in[13], B[13]); + buf B14 (b_in[14], B[14]); + buf B15 (b_in[15], B[15]); + buf B16 (b_in[16], B[16]); + buf B17 (b_in[17], B[17]); + buf B18 (b_in[18], B[17]); + buf B19 (b_in[19], B[17]); + buf B20 (b_in[20], B[17]); + buf B21 (b_in[21], B[17]); + buf B22 (b_in[22], B[17]); + buf B23 (b_in[23], B[17]); + buf B24 (b_in[24], B[17]); + buf B25 (b_in[25], B[17]); + buf B26 (b_in[26], B[17]); + buf B27 (b_in[27], B[17]); + buf B28 (b_in[28], B[17]); + buf B29 (b_in[29], B[17]); + buf B30 (b_in[30], B[17]); + buf B31 (b_in[31], B[17]); + buf B32 (b_in[32], B[17]); + buf B33 (b_in[33], B[17]); + buf B34 (b_in[34], B[17]); + buf B35 (b_in[35], B[17]); + + buf P0 (P[0], p0_out); + buf P1 (P[1], p1_out); + buf P2 (P[2], p2_out); + buf P3 (P[3], p3_out); + buf P4 (P[4], p4_out); + buf P5 (P[5], p5_out); + buf P6 (P[6], p6_out); + buf P7 (P[7], p7_out); + buf P8 (P[8], p8_out); + buf P9 (P[9], p9_out); + buf P10 (P[10], p10_out); + buf P11 (P[11], p11_out); + buf P12 (P[12], p12_out); + buf P13 (P[13], p13_out); + buf P14 (P[14], p14_out); + buf P15 (P[15], p15_out); + buf P16 (P[16], p16_out); + buf P17 (P[17], p17_out); + buf P18 (P[18], p18_out); + buf P19 (P[19], p19_out); + buf P20 (P[20], p20_out); + buf P21 (P[21], p21_out); + buf P22 (P[22], p22_out); + buf P23 (P[23], p23_out); + buf P24 (P[24], p24_out); + buf P25 (P[25], p25_out); + buf P26 (P[26], p26_out); + buf P27 (P[27], p27_out); + buf P28 (P[28], p28_out); + buf P29 (P[29], p29_out); + buf P30 (P[30], p30_out); + buf P31 (P[31], p31_out); + buf P32 (P[32], p32_out); + buf P33 (P[33], p33_out); + buf P34 (P[34], p34_out); + buf P35 (P[35], p35_out); + + assign p_in = a_in * b_in; + assign {p35_out, p34_out, p33_out, p32_out, p31_out, p30_out, p29_out, p28_out, p27_out, p26_out, p25_out, p24_out, p23_out, p22_out, p21_out, p20_out, p19_out, p18_out, p17_out, p16_out, p15_out, p14_out, p13_out, p12_out, p11_out, p10_out, p9_out, p8_out, p7_out, p6_out, p5_out, p4_out, p3_out, p2_out, p1_out, p0_out} = p_out; + + + always @(posedge C or posedge GSR) + if (GSR) + p_out = 36'b0; + else + if (R) + p_out <= 36'b0; + else if (CE) + p_out <= #100 p_in; + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/MULT18X18SIO.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/MULT18X18SIO.v new file mode 100644 index 0000000..6f8a033 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/MULT18X18SIO.v @@ -0,0 +1,257 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/spartan4/MULT18X18SIO.v,v 1.6 2007/06/08 02:19:53 fphillip Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / 18X18 Signed Registered Multiplier +// /___/ /\ Filename : MULT18X18SIO.v +// \ \ / \ Timestamp : Thu Mar 25 16:43:52 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 03/08/06 - CR 226003 -- Added Parameter Types (integer/real) +// 05/29/07 - Added wire declaration for internal signals +// End Revision + +`timescale 1 ps / 1 ps + +module MULT18X18SIO (BCOUT, P, A, B, BCIN, CEA, CEB, CEP, CLK, RSTA, RSTB, RSTP); + + output [17:0] BCOUT; + output [35:0] P; + + input [17:0] A; + input [17:0] B; + input [17:0] BCIN; + input CEA; + input CEB; + input CEP; + input CLK; + tri0 GSR = glbl.GSR; + input RSTA; + input RSTB; + input RSTP; + + parameter integer AREG = 1; + parameter integer BREG = 1; + parameter B_INPUT = "DIRECT"; + parameter integer PREG = 1; + + reg [17:0] b_o_mux, qb_o_mux, qb_o_reg1; + reg [17:0] qa_o_mux, qa_o_reg1; + reg [35:0] qp_o_mux, qp_o_reg1; + + wire [17:0] bcin_in, a_in, b_in; + wire [35:0] mult_o; + + wire cep_in; + wire cea_in; + wire ceb_in; + wire clk_in; + wire gsr_in; + wire rstp_in; + wire rsta_in; + wire rstb_in; + + buf b_p_o[35:0] (P, qp_o_mux); + buf b_bcout[17:0] (BCOUT, qb_o_mux); + + buf b_bcin[17:0] (bcin_in, BCIN); + buf b_a[17:0] (a_in, A); + buf b_b[17:0] (b_in, B); + + buf b_cep (cep_in, CEP); + buf b_cea (cea_in, CEA); + buf b_ceb (ceb_in, CEB); + buf b_clk (clk_in, CLK); + buf b_gsr (gsr_in, GSR); + buf b_rstp (rstp_in, RSTP); + buf b_rsta (rsta_in, RSTA); + buf b_rstb (rstb_in, RSTB); + + +//*** GSR pin + always @(gsr_in) begin + + if (gsr_in) begin + + assign qa_o_reg1 = 18'b0; + assign qb_o_reg1 = 18'b0; + assign qp_o_reg1 = 36'b0; + + end + else begin + + deassign qa_o_reg1; + deassign qb_o_reg1; + deassign qp_o_reg1; + + end + end + + +//*** Input register B + + always @(bcin_in or b_in) begin + + case (B_INPUT) + + "DIRECT" : b_o_mux <= b_in; + "CASCADE" : b_o_mux <= bcin_in; + default : begin + + $display("Attribute Syntax Error : The attribute B_INPUT on MULT18X18SIO instance %m is set to %s. Legal values for this attribute are DIRECT or CASCADE.", B_INPUT); + $finish; + + end + + endcase + end + + always @(posedge clk_in) begin + + if (rstb_in) + qb_o_reg1 <= 18'b0; + + else if (ceb_in) + qb_o_reg1 <= b_o_mux; + + end + + always @(b_o_mux or qb_o_reg1) begin + + case (BREG) + + 0 : qb_o_mux <= b_o_mux; + 1 : qb_o_mux <= qb_o_reg1; + default : begin + $display("Attribute Syntax Error : The attribute BREG on MULT18X18SIO instance %m is set to %d. Legal values for this attribute are 0 or 1.", BREG); + $finish; + end + + endcase + end + + +//*** Input register A + always @(posedge clk_in) begin + + if (rsta_in) + qa_o_reg1 <= 18'b0; + + else if (cea_in) + qa_o_reg1 <= a_in; + + end + + always @(a_in or qa_o_reg1) begin + + case (AREG) + + 0 : qa_o_mux <= a_in; + 1 : qa_o_mux <= qa_o_reg1; + default : begin + $display("Attribute Syntax Error : The attribute AREG on MULT18X18SIO instance %m is set to %d. Legal values for this attribute are 0 or 1.", AREG); + $finish; + end + endcase + end + + +//*** 18x18 Multiplier +// assign mult_o = qa_o_mux * qb_o_mux; + assign mult_o = {{18{qa_o_mux[17]}}, qa_o_mux} * {{18{qb_o_mux[17]}}, qb_o_mux}; + +//*** Output register P + always @(posedge clk_in) begin + + if (rstp_in) + qp_o_reg1 <= 36'b0; + + else if (cep_in) + qp_o_reg1 <= mult_o; + + end + + always @(qp_o_reg1 or mult_o) begin + + case (PREG) + + 0 : qp_o_mux <= mult_o; + 1 : qp_o_mux <= qp_o_reg1; + default : begin + $display("Attribute Syntax Error : The attribute PREG on MULT18X18SIO instance %m is set to %d. Legal values for this attribute are 0 or 1.", PREG); + $finish; + end + + endcase + end + + + specify + + (CLK => P[0]) = (100, 100); + (CLK => P[1]) = (100, 100); + (CLK => P[2]) = (100, 100); + (CLK => P[3]) = (100, 100); + (CLK => P[4]) = (100, 100); + (CLK => P[5]) = (100, 100); + (CLK => P[6]) = (100, 100); + (CLK => P[7]) = (100, 100); + (CLK => P[8]) = (100, 100); + (CLK => P[9]) = (100, 100); + (CLK => P[10]) = (100, 100); + (CLK => P[11]) = (100, 100); + (CLK => P[12]) = (100, 100); + (CLK => P[13]) = (100, 100); + (CLK => P[14]) = (100, 100); + (CLK => P[15]) = (100, 100); + (CLK => P[16]) = (100, 100); + (CLK => P[17]) = (100, 100); + (CLK => P[18]) = (100, 100); + (CLK => P[19]) = (100, 100); + (CLK => P[20]) = (100, 100); + (CLK => P[21]) = (100, 100); + (CLK => P[22]) = (100, 100); + (CLK => P[23]) = (100, 100); + (CLK => P[24]) = (100, 100); + (CLK => P[25]) = (100, 100); + (CLK => P[26]) = (100, 100); + (CLK => P[27]) = (100, 100); + (CLK => P[28]) = (100, 100); + (CLK => P[29]) = (100, 100); + (CLK => P[30]) = (100, 100); + (CLK => P[31]) = (100, 100); + (CLK => P[32]) = (100, 100); + (CLK => P[33]) = (100, 100); + (CLK => P[34]) = (100, 100); + (CLK => P[35]) = (100, 100); + (CLK => BCOUT[0]) = (100, 100); + (CLK => BCOUT[1]) = (100, 100); + (CLK => BCOUT[2]) = (100, 100); + (CLK => BCOUT[3]) = (100, 100); + (CLK => BCOUT[4]) = (100, 100); + (CLK => BCOUT[5]) = (100, 100); + (CLK => BCOUT[6]) = (100, 100); + (CLK => BCOUT[7]) = (100, 100); + (CLK => BCOUT[8]) = (100, 100); + (CLK => BCOUT[9]) = (100, 100); + (CLK => BCOUT[10]) = (100, 100); + (CLK => BCOUT[11]) = (100, 100); + (CLK => BCOUT[12]) = (100, 100); + (CLK => BCOUT[13]) = (100, 100); + (CLK => BCOUT[14]) = (100, 100); + (CLK => BCOUT[15]) = (100, 100); + (CLK => BCOUT[16]) = (100, 100); + (CLK => BCOUT[17]) = (100, 100); + specparam PATHPULSE$ = 0; + + endspecify + +endmodule // MULT18X18SIO diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/MULT_AND.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/MULT_AND.v new file mode 100644 index 0000000..b4c3222 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/MULT_AND.v @@ -0,0 +1,37 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/MULT_AND.v,v 1.5 2007/05/23 21:43:39 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Fast Multiplier AND +// /___/ /\ Filename : MULT_AND.v +// \ \ / \ Timestamp : Thu Mar 25 16:42:54 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. + +`timescale 1 ps / 1 ps + + +module MULT_AND (LO, I0, I1); + + output LO; + + input I0, I1; + + and A1 (LO, I0, I1); + + specify + (I0 *> LO) = (0, 0); + (I1 *> LO) = (0, 0); + endspecify + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/MUXCY.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/MUXCY.v new file mode 100644 index 0000000..a8d6506 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/MUXCY.v @@ -0,0 +1,40 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/MUXCY.v,v 1.11 2007/08/23 23:00:26 yanx Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / 2-to-1 Multiplexer for Carry Logic with General Output +// /___/ /\ Filename : MUXCY.v +// \ \ / \ Timestamp : Thu Mar 25 16:42:55 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 02/04/05 - Rev 0.0.1 Remove input/output bufs; Remove unnessasary begin/end; +// 05/10/07 - When input same, output same for any sel value. (CR434611). +// 08/23/07 - User block statement (CR446704). +// End Revision + +`timescale 1 ps / 1 ps + + +module MUXCY (O, CI, DI, S); + + output O; + reg O; + + input CI, DI, S; + + always @(CI or DI or S) + if (S) + O = CI; + else + O = DI; + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/MUXCY_D.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/MUXCY_D.v new file mode 100644 index 0000000..2c83555 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/MUXCY_D.v @@ -0,0 +1,44 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/MUXCY_D.v,v 1.11 2007/08/23 23:00:26 yanx Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / 2-to-1 Multiplexer for Carry Logic with Dual Output +// /___/ /\ Filename : MUXCY_D.v +// \ \ / \ Timestamp : Thu Mar 25 16:42:55 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 02/04/05 - Rev 0.0.1 Remove input/output bufs; Remove unnessasary begin/end; +// 05/10/07 - When input same, output same for any sel value. (CR434611). +// 08/23/07 - User block statement (CR446704). +// End Revision + +`timescale 1 ps / 1 ps + + +module MUXCY_D (LO, O, CI, DI, S); + + output LO, O; + reg O, LO; + + input CI, DI, S; + + always @(CI or DI or S) + if (S) begin + O = CI; + LO = CI; + end + else begin + O = DI; + LO = DI; + end + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/MUXCY_L.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/MUXCY_L.v new file mode 100644 index 0000000..1f6e936 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/MUXCY_L.v @@ -0,0 +1,38 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/MUXCY_L.v,v 1.11 2007/08/23 23:00:26 yanx Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / 2-to-1 Multiplexer for Carry Logic with Local Output +// /___/ /\ Filename : MUXCY_L.v +// \ \ / \ Timestamp : Thu Mar 25 16:42:55 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 02/04/05 - Rev 0.0.1 Remove input/output bufs; Remove unnessasary begin/end; +// 05/10/07 - When input same, output same for any sel value. (CR434611). +// 08/23/07 - User block statement (CR446704). +// End Revision + +`timescale 1 ps / 1 ps + +module MUXCY_L (LO, CI, DI, S); + + output LO; + reg LO; + + input CI, DI, S; + + always @(CI or DI or S) + if (S) + LO = CI; + else + LO = DI; +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/MUXF5.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/MUXF5.v new file mode 100644 index 0000000..631e89d --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/MUXF5.v @@ -0,0 +1,37 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/MUXF5.v,v 1.11 2007/08/23 23:00:26 yanx Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / 2-to-1 Lookup Table Multiplexer with General Output +// /___/ /\ Filename : MUXF5.v +// \ \ / \ Timestamp : Thu Mar 25 16:42:55 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 02/04/05 - Rev 0.0.1 Remove input/output bufs; Remove unnessasary begin/end; +// 02/10/07 - When input same, output same for any sel value. (CR433761). +// 05/23/07 - Changed timescale to 1 ps / 1 ps. + +`timescale 1 ps / 1 ps + +module MUXF5 (O, I0, I1, S); + + output O; + reg O; + + input I0, I1, S; + + always @(I0 or I1 or S) + if (S) + O = I1; + else + O = I0; +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/MUXF5_D.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/MUXF5_D.v new file mode 100644 index 0000000..145c082 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/MUXF5_D.v @@ -0,0 +1,43 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/MUXF5_D.v,v 1.11 2007/08/23 23:00:26 yanx Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / 2-to-1 Lookup Table Multiplexer with Dual Output +// /___/ /\ Filename : MUXF5_D.v +// \ \ / \ Timestamp : Thu Mar 25 16:42:55 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 02/04/05 - Rev 0.0.1 Remove input/output bufs; Remove unnessasary begin/end; +// 05/10/07 - When input same, output same for any sel value. (CR434611). +// 08/23/07 - User block statement (CR446704). +// End Revision + +`timescale 1 ps / 1 ps + + +module MUXF5_D (LO, O, I0, I1, S); + + output LO, O; + reg O, LO; + + input I0, I1, S; + + always @(I0 or I1 or S) + if (S) begin + O = I1; + LO = I1; + end + else begin + O = I0; + LO = I0; + end +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/MUXF5_L.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/MUXF5_L.v new file mode 100644 index 0000000..d11fcf9 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/MUXF5_L.v @@ -0,0 +1,38 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/MUXF5_L.v,v 1.11 2007/08/23 23:00:26 yanx Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / 2-to-1 Lookup Table Multiplexer with Local Output +// /___/ /\ Filename : MUXF5_L.v +// \ \ / \ Timestamp : Thu Mar 25 16:42:55 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 02/04/05 - Rev 0.0.1 Remove input/output bufs; Remove unnessasary begin/end; +// 05/10/07 - When input same, output same for any sel value. (CR434611). +// 08/23/07 - User block statement (CR446704). +// End Revision + +`timescale 1 ps / 1 ps + +module MUXF5_L (LO, I0, I1, S); + + output LO; + reg LO; + + input I0, I1, S; + + always @(I0 or I1 or S) + if (S) + LO = I1; + else + LO = I0; +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/MUXF6.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/MUXF6.v new file mode 100644 index 0000000..aee6d0a --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/MUXF6.v @@ -0,0 +1,39 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/MUXF6.v,v 1.11 2007/08/23 23:00:26 yanx Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / 2-to-1 Lookup Table Multiplexer with General Output +// /___/ /\ Filename : MUXF6.v +// \ \ / \ Timestamp : Thu Mar 25 16:42:55 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 02/04/05 - Rev 0.0.1 Remove input/output bufs; Remove unnessasary begin/end; +// 05/10/07 - When input same, output same for any sel value. (CR434611). +// 08/23/07 - User block statement (CR446704). +// End Revision + +`timescale 1 ps / 1 ps + + +module MUXF6 (O, I0, I1, S); + + output O; + reg O; + + input I0, I1, S; + + always @(I0 or I1 or S) + if (S) + O = I1; + else + O = I0; +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/MUXF6_D.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/MUXF6_D.v new file mode 100644 index 0000000..6475d5e --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/MUXF6_D.v @@ -0,0 +1,43 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/MUXF6_D.v,v 1.11 2007/08/23 23:00:26 yanx Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / 2-to-1 Lookup Table Multiplexer with Dual Output +// /___/ /\ Filename : MUXF6_D.v +// \ \ / \ Timestamp : Thu Mar 25 16:42:55 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 02/04/05 - Rev 0.0.1 Remove input/output bufs; Remove unnessasary begin/end; +// 05/10/07 - When input same, output same for any sel value. (CR434611). +// 08/23/07 - User block statement (CR446704). +// End Revision + +`timescale 1 ps / 1 ps + + +module MUXF6_D (LO, O, I0, I1, S); + + output LO, O; + reg O, LO; + + input I0, I1, S; + + always @(I0 or I1 or S) + if (S) begin + O = I1; + LO = I1; + end + else begin + O = I0; + LO = I0; + end +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/MUXF6_L.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/MUXF6_L.v new file mode 100644 index 0000000..db14db1 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/MUXF6_L.v @@ -0,0 +1,39 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/MUXF6_L.v,v 1.11 2007/08/23 23:00:26 yanx Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / 2-to-1 Lookup Table Multiplexer with Local Output +// /___/ /\ Filename : MUXF6_L.v +// \ \ / \ Timestamp : Thu Mar 25 16:42:55 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 02/04/05 - Rev 0.0.1 Remove input/output bufs; Remove unnessasary begin/end; +// 05/10/07 - When input same, output same for any sel value. (CR434611). +// 08/23/07 - User block statement (CR446704). +// End Revision + +`timescale 1 ps / 1 ps + + +module MUXF6_L (LO, I0, I1, S); + + output LO; + reg LO; + + input I0, I1, S; + + always @(I0 or I1 or S) + if (S) + LO = I1; + else + LO = I0; +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/MUXF7.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/MUXF7.v new file mode 100644 index 0000000..720e792 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/MUXF7.v @@ -0,0 +1,38 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/MUXF7.v,v 1.11 2007/08/23 23:00:26 yanx Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / 2-to-1 Lookup Table Multiplexer with General Output +// /___/ /\ Filename : MUXF7.v +// \ \ / \ Timestamp : Thu Mar 25 16:42:55 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 02/04/05 - Rev 0.0.1 Remove input/output bufs; Remove unnessasary begin/end; +// 05/10/07 - When input same, output same for any sel value. (CR434611). +// 08/23/07 - User block statement (CR446704). +// End Revision + +`timescale 1 ps / 1 ps + +module MUXF7 (O, I0, I1, S); + + output O; + reg O; + + input I0, I1, S; + + always @(I0 or I1 or S) + if (S) + O = I1; + else + O = I0; +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/MUXF7_D.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/MUXF7_D.v new file mode 100644 index 0000000..a28f614 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/MUXF7_D.v @@ -0,0 +1,43 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/MUXF7_D.v,v 1.11 2007/08/23 23:00:26 yanx Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / 2-to-1 Lookup Table Multiplexer with Dual Output +// /___/ /\ Filename : MUXF7_D.v +// \ \ / \ Timestamp : Thu Mar 25 16:42:56 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 02/04/05 - Rev 0.0.1 Remove input/output bufs; Remove unnessasary begin/end; +// 05/10/07 - When input same, output same for any sel value. (CR434611). +// 08/23/07 - User block statement (CR446704). +// End Revision + +`timescale 1 ps / 1 ps + + +module MUXF7_D (LO, O, I0, I1, S); + + output LO, O; + reg O, LO; + + input I0, I1, S; + + always @(I0 or I1 or S) + if (S) begin + O = I1; + LO = I1; + end + else begin + O = I0; + LO = I0; + end +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/MUXF7_L.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/MUXF7_L.v new file mode 100644 index 0000000..b7609f2 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/MUXF7_L.v @@ -0,0 +1,38 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/MUXF7_L.v,v 1.11 2007/08/23 23:00:26 yanx Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / 2-to-1 Lookup Table Multiplexer with Local Output +// /___/ /\ Filename : MUXF7_L.v +// \ \ / \ Timestamp : Thu Mar 25 16:42:56 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 02/04/05 - Rev 0.0.1 Remove input/output bufs; Remove unnessasary begin/end; +// 05/10/07 - When input same, output same for any sel value. (CR434611). +// 08/23/07 - User block statement (CR446704). +// End Revision + +`timescale 1 ps / 1 ps + +module MUXF7_L (LO, I0, I1, S); + + output LO; + reg LO; + + input I0, I1, S; + + always @(I0 or I1 or S) + if (S) + LO = I1; + else + LO = I0; +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/MUXF8.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/MUXF8.v new file mode 100644 index 0000000..dc0e413 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/MUXF8.v @@ -0,0 +1,39 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/MUXF8.v,v 1.11 2007/08/23 23:00:26 yanx Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / 2-to-1 Lookup Table Multiplexer with General Output +// /___/ /\ Filename : MUXF8.v +// \ \ / \ Timestamp : Thu Mar 25 16:42:56 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 02/04/05 - Rev 0.0.1 Remove input/output bufs; Remove unnessasary begin/end; +// 05/10/07 - When input same, output same for any sel value. (CR434611). +// 08/23/07 - User block statement (CR446704). +// End Revision + +`timescale 1 ps / 1 ps + + +module MUXF8 (O, I0, I1, S); + + output O; + reg O; + + input I0, I1, S; + + always @(I0 or I1 or S) + if (S) + O = I1; + else + O = I0; +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/MUXF8_D.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/MUXF8_D.v new file mode 100644 index 0000000..907ed0f --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/MUXF8_D.v @@ -0,0 +1,43 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/MUXF8_D.v,v 1.11 2007/08/23 23:00:26 yanx Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / 2-to-1 Lookup Table Multiplexer with Dual Output +// /___/ /\ Filename : MUXF8_D.v +// \ \ / \ Timestamp : Thu Mar 25 16:42:56 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 02/04/05 - Rev 0.0.1 Remove input/output bufs; Remove unnessasary begin/end; +// 05/10/07 - When input same, output same for any sel value. (CR434611). +// 08/23/07 - User block statement (CR446704). +// End Revision + +`timescale 1 ps / 1 ps + + +module MUXF8_D (LO, O, I0, I1, S); + + output LO, O; + reg O, LO; + + input I0, I1, S; + + always @(I0 or I1 or S) + if (S) begin + O = I1; + LO = I1; + end + else begin + O = I0; + LO = I0; + end +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/MUXF8_L.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/MUXF8_L.v new file mode 100644 index 0000000..1bc3c89 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/MUXF8_L.v @@ -0,0 +1,39 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/MUXF8_L.v,v 1.11 2007/08/23 23:00:26 yanx Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / 2-to-1 Lookup Table Multiplexer with Local Output +// /___/ /\ Filename : MUXF8_L.v +// \ \ / \ Timestamp : Thu Mar 25 16:42:56 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 02/04/05 - Rev 0.0.1 Remove input/output bufs; Remove unnessasary begin/end; +// 05/10/07 - When input same, output same for any sel value. (CR434611). +// 08/23/07 - User block statement (CR446704). +// End Revision + +`timescale 1 ps / 1 ps + + +module MUXF8_L (LO, I0, I1, S); + + output LO; + reg LO; + + input I0, I1, S; + + always @(I0 or I1 or S) + if (S) + LO = I1; + else + LO = I0; +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/NAND2.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/NAND2.v new file mode 100644 index 0000000..ed7c2f0 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/NAND2.v @@ -0,0 +1,33 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/NAND2.v,v 1.6 2007/05/23 21:43:39 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / 2-input NAND Gate +// /___/ /\ Filename : NAND2.v +// \ \ / \ Timestamp : Thu Mar 25 16:42:56 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. + +`timescale 1 ps / 1 ps + + +module NAND2 (O, I0, I1); + + output O; + + input I0, I1; + + nand A1 (O, I0, I1); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/NAND2B1.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/NAND2B1.v new file mode 100644 index 0000000..1c72c53 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/NAND2B1.v @@ -0,0 +1,37 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/NAND2B1.v,v 1.6 2007/05/23 21:43:39 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / 2-input NAND Gate +// /___/ /\ Filename : NAND2B1.v +// \ \ / \ Timestamp : Thu Mar 25 16:42:56 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. +// 05/23/07 - Added wire declaration for internal signals. + +`timescale 1 ps / 1 ps + + +module NAND2B1 (O, I0, I1); + + output O; + + input I0, I1; + + wire i0_inv; + + not N0 (i0_inv, I0); + nand A1 (O, i0_inv, I1); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/NAND2B2.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/NAND2B2.v new file mode 100644 index 0000000..8fda549 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/NAND2B2.v @@ -0,0 +1,39 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/NAND2B2.v,v 1.6 2007/05/23 21:43:39 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / 2-input NAND Gate +// /___/ /\ Filename : NAND2B2.v +// \ \ / \ Timestamp : Thu Mar 25 16:42:56 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. +// 05/23/07 - Added wire declaration for internal signals. + +`timescale 1 ps / 1 ps + + +module NAND2B2 (O, I0, I1); + + output O; + + input I0, I1; + + wire i0_inv; + wire i1_inv; + + not N1 (i1_inv, I1); + not N0 (i0_inv, I0); + nand A1 (O, i0_inv, i1_inv); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/NAND3.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/NAND3.v new file mode 100644 index 0000000..1ea46aa --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/NAND3.v @@ -0,0 +1,33 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/NAND3.v,v 1.6 2007/05/23 21:43:39 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / 3-input NAND Gate +// /___/ /\ Filename : NAND3.v +// \ \ / \ Timestamp : Thu Mar 25 16:42:56 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. + +`timescale 1 ps / 1 ps + + +module NAND3 (O, I0, I1, I2); + + output O; + + input I0, I1, I2; + + nand A1 (O, I0, I1, I2); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/NAND3B1.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/NAND3B1.v new file mode 100644 index 0000000..4e9402d --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/NAND3B1.v @@ -0,0 +1,37 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/NAND3B1.v,v 1.6 2007/05/23 21:43:39 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / 3-input NAND Gate +// /___/ /\ Filename : NAND3B1.v +// \ \ / \ Timestamp : Thu Mar 25 16:42:56 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. +// 05/23/07 - Added wire declaration for internal signals. + +`timescale 1 ps / 1 ps + + +module NAND3B1 (O, I0, I1, I2); + + output O; + + input I0, I1, I2; + + wire i0_inv; + + not N0 (i0_inv, I0); + nand A1 (O, i0_inv, I1, I2); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/NAND3B2.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/NAND3B2.v new file mode 100644 index 0000000..b1bf5b1 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/NAND3B2.v @@ -0,0 +1,39 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/NAND3B2.v,v 1.6 2007/05/23 21:43:39 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / 3-input NAND Gate +// /___/ /\ Filename : NAND3B2.v +// \ \ / \ Timestamp : Thu Mar 25 16:42:56 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. +// 05/23/07 - Added wire declaration for internal signals. + +`timescale 1 ps / 1 ps + + +module NAND3B2 (O, I0, I1, I2); + + output O; + + input I0, I1, I2; + + wire i0_inv; + wire i1_inv; + + not N1 (i1_inv, I1); + not N0 (i0_inv, I0); + nand A1 (O, i0_inv, i1_inv, I2); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/NAND3B3.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/NAND3B3.v new file mode 100644 index 0000000..970918d --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/NAND3B3.v @@ -0,0 +1,41 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/NAND3B3.v,v 1.6 2007/05/23 21:43:39 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / 3-input NAND Gate +// /___/ /\ Filename : NAND3B3.v +// \ \ / \ Timestamp : Thu Mar 25 16:42:57 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. +// 05/23/07 - Added wire declaration for internal signals. + +`timescale 1 ps / 1 ps + + +module NAND3B3 (O, I0, I1, I2); + + output O; + + input I0, I1, I2; + + wire i0_inv; + wire i1_inv; + wire i2_inv; + + not N2 (i2_inv, I2); + not N1 (i1_inv, I1); + not N0 (i0_inv, I0); + nand A1 (O, i0_inv, i1_inv, i2_inv); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/NAND4.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/NAND4.v new file mode 100644 index 0000000..23fbc90 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/NAND4.v @@ -0,0 +1,33 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/NAND4.v,v 1.6 2007/05/23 21:43:39 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / 4-input NAND Gate +// /___/ /\ Filename : NAND4.v +// \ \ / \ Timestamp : Thu Mar 25 16:42:57 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. + +`timescale 1 ps / 1 ps + + +module NAND4 (O, I0, I1, I2, I3); + + output O; + + input I0, I1, I2, I3; + + nand A1 (O, I0, I1, I2, I3); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/NAND4B1.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/NAND4B1.v new file mode 100644 index 0000000..c851182 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/NAND4B1.v @@ -0,0 +1,37 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/NAND4B1.v,v 1.6 2007/05/23 21:43:39 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / 4-input NAND Gate +// /___/ /\ Filename : NAND4B1.v +// \ \ / \ Timestamp : Thu Mar 25 16:42:57 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. +// 05/23/07 - Added wire declaration for internal signals. + +`timescale 1 ps / 1 ps + + +module NAND4B1 (O, I0, I1, I2, I3); + + output O; + + input I0, I1, I2, I3; + + wire i0_inv; + + not N0 (i0_inv, I0); + nand A1 (O, i0_inv, I1, I2, I3); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/NAND4B2.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/NAND4B2.v new file mode 100644 index 0000000..85b095c --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/NAND4B2.v @@ -0,0 +1,39 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/NAND4B2.v,v 1.6 2007/05/23 21:43:39 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / 4-input NAND Gate +// /___/ /\ Filename : NAND4B2.v +// \ \ / \ Timestamp : Thu Mar 25 16:42:57 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. +// 05/23/07 - Added wire declaration for internal signals. + +`timescale 1 ps / 1 ps + + +module NAND4B2 (O, I0, I1, I2, I3); + + output O; + + input I0, I1, I2, I3; + + wire i0_inv; + wire i1_inv; + + not N1 (i1_inv, I1); + not N0 (i0_inv, I0); + nand A1 (O, i0_inv, i1_inv, I2, I3); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/NAND4B3.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/NAND4B3.v new file mode 100644 index 0000000..89a5a76 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/NAND4B3.v @@ -0,0 +1,41 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/NAND4B3.v,v 1.6 2007/05/23 21:43:39 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / 4-input NAND Gate +// /___/ /\ Filename : NAND4B3.v +// \ \ / \ Timestamp : Thu Mar 25 16:42:57 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. +// 05/23/07 - Added wire declaration for internal signals. + +`timescale 1 ps / 1 ps + + +module NAND4B3 (O, I0, I1, I2, I3); + + output O; + + input I0, I1, I2, I3; + + wire i0_inv; + wire i1_inv; + wire i2_inv; + + not N2 (i2_inv, I2); + not N1 (i1_inv, I1); + not N0 (i0_inv, I0); + nand A1 (O, i0_inv, i1_inv, i2_inv, I3); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/NAND4B4.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/NAND4B4.v new file mode 100644 index 0000000..6e692fe --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/NAND4B4.v @@ -0,0 +1,43 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/NAND4B4.v,v 1.6 2007/05/23 21:43:39 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / 4-input NAND Gate +// /___/ /\ Filename : NAND4B4.v +// \ \ / \ Timestamp : Thu Mar 25 16:42:57 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. +// 05/23/07 - Added wire declaration for internal signals. + +`timescale 1 ps / 1 ps + + +module NAND4B4 (O, I0, I1, I2, I3); + + output O; + + input I0, I1, I2, I3; + + wire i0_inv; + wire i1_inv; + wire i2_inv; + wire i3_inv; + + not N3 (i3_inv, I3); + not N2 (i2_inv, I2); + not N1 (i1_inv, I1); + not N0 (i0_inv, I0); + nand A1 (O, i0_inv, i1_inv, i2_inv, i3_inv); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/NAND5.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/NAND5.v new file mode 100644 index 0000000..0ff84ec --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/NAND5.v @@ -0,0 +1,33 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/NAND5.v,v 1.6 2007/05/23 21:43:39 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / 5-input NAND Gate +// /___/ /\ Filename : NAND5.v +// \ \ / \ Timestamp : Thu Mar 25 16:42:57 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. + +`timescale 1 ps / 1 ps + + +module NAND5 (O, I0, I1, I2, I3, I4); + + output O; + + input I0, I1, I2, I3, I4; + + nand A1 (O, I0, I1, I2, I3, I4); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/NAND5B1.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/NAND5B1.v new file mode 100644 index 0000000..697f146 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/NAND5B1.v @@ -0,0 +1,37 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/NAND5B1.v,v 1.6 2007/05/23 21:43:39 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / 5-input NAND Gate +// /___/ /\ Filename : NAND5B1.v +// \ \ / \ Timestamp : Thu Mar 25 16:42:57 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. +// 05/23/07 - Added wire declaration for internal signals. + +`timescale 1 ps / 1 ps + + +module NAND5B1 (O, I0, I1, I2, I3, I4); + + output O; + + input I0, I1, I2, I3, I4; + + wire i0_inv; + + not N0 (i0_inv, I0); + nand A1 (O, i0_inv, I1, I2, I3, I4); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/NAND5B2.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/NAND5B2.v new file mode 100644 index 0000000..7705d68 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/NAND5B2.v @@ -0,0 +1,39 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/NAND5B2.v,v 1.6 2007/05/23 21:43:39 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / 5-input NAND Gate +// /___/ /\ Filename : NAND5B2.v +// \ \ / \ Timestamp : Thu Mar 25 16:42:57 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. +// 05/23/07 - Added wire declaration for internal signals. + +`timescale 1 ps / 1 ps + + +module NAND5B2 (O, I0, I1, I2, I3, I4); + + output O; + + input I0, I1, I2, I3, I4; + + wire i0_inv; + wire i1_inv; + + not N1 (i1_inv, I1); + not N0 (i0_inv, I0); + nand A1 (O, i0_inv, i1_inv, I2, I3, I4); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/NAND5B3.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/NAND5B3.v new file mode 100644 index 0000000..2eccec5 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/NAND5B3.v @@ -0,0 +1,41 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/NAND5B3.v,v 1.6 2007/05/23 21:43:39 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / 5-input NAND Gate +// /___/ /\ Filename : NAND5B3.v +// \ \ / \ Timestamp : Thu Mar 25 16:42:57 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. +// 05/23/07 - Added wire declaration for internal signals. + +`timescale 1 ps / 1 ps + + +module NAND5B3 (O, I0, I1, I2, I3, I4); + + output O; + + input I0, I1, I2, I3, I4; + + wire i0_inv; + wire i1_inv; + wire i2_inv; + + not N2 (i2_inv, I2); + not N1 (i1_inv, I1); + not N0 (i0_inv, I0); + nand A1 (O, i0_inv, i1_inv, i2_inv, I3, I4); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/NAND5B4.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/NAND5B4.v new file mode 100644 index 0000000..1042fc7 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/NAND5B4.v @@ -0,0 +1,43 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/NAND5B4.v,v 1.6 2007/05/23 21:43:39 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / 5-input NAND Gate +// /___/ /\ Filename : NAND5B4.v +// \ \ / \ Timestamp : Thu Mar 25 16:42:57 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. +// 05/23/07 - Added wire declaration for internal signals. + +`timescale 1 ps / 1 ps + + +module NAND5B4 (O, I0, I1, I2, I3, I4); + + output O; + + input I0, I1, I2, I3, I4; + + wire i0_inv; + wire i1_inv; + wire i2_inv; + wire i3_inv; + + not N3 (i3_inv, I3); + not N2 (i2_inv, I2); + not N1 (i1_inv, I1); + not N0 (i0_inv, I0); + nand A1 (O, i0_inv, i1_inv, i2_inv, i3_inv, I4); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/NAND5B5.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/NAND5B5.v new file mode 100644 index 0000000..213d165 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/NAND5B5.v @@ -0,0 +1,45 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/NAND5B5.v,v 1.6 2007/05/23 21:43:39 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / 5-input NAND Gate +// /___/ /\ Filename : NAND5B5.v +// \ \ / \ Timestamp : Thu Mar 25 16:42:58 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. +// 05/23/07 - Added wire declaration for internal signals. + +`timescale 1 ps / 1 ps + + +module NAND5B5 (O, I0, I1, I2, I3, I4); + + output O; + + input I0, I1, I2, I3, I4; + + wire i0_inv; + wire i1_inv; + wire i2_inv; + wire i3_inv; + wire i4_inv; + + not N4 (i4_inv, I4); + not N3 (i3_inv, I3); + not N2 (i2_inv, I2); + not N1 (i1_inv, I1); + not N0 (i0_inv, I0); + nand A1 (O, i0_inv, i1_inv, i2_inv, i3_inv, i4_inv); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/NOR2.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/NOR2.v new file mode 100644 index 0000000..8ff48e6 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/NOR2.v @@ -0,0 +1,33 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/NOR2.v,v 1.6 2007/05/23 21:43:39 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / 2-input NOR Gate +// /___/ /\ Filename : NOR2.v +// \ \ / \ Timestamp : Thu Mar 25 16:42:58 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. + +`timescale 1 ps / 1 ps + + +module NOR2 (O, I0, I1); + + output O; + + input I0, I1; + + nor O1 (O, I0, I1); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/NOR2B1.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/NOR2B1.v new file mode 100644 index 0000000..635f315 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/NOR2B1.v @@ -0,0 +1,37 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/NOR2B1.v,v 1.6 2007/05/23 21:43:39 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / 2-input NOR Gate +// /___/ /\ Filename : NOR2B1.v +// \ \ / \ Timestamp : Thu Mar 25 16:42:58 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. +// 05/23/07 - Added wire declaration for internal signals. + +`timescale 1 ps / 1 ps + + +module NOR2B1 (O, I0, I1); + + output O; + + input I0, I1; + + wire i0_inv; + + not N0 (i0_inv, I0); + nor O1 (O, i0_inv, I1); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/NOR2B2.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/NOR2B2.v new file mode 100644 index 0000000..a8fc3ef --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/NOR2B2.v @@ -0,0 +1,39 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/NOR2B2.v,v 1.6 2007/05/23 21:43:39 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / 2-input NOR Gate +// /___/ /\ Filename : NOR2B2.v +// \ \ / \ Timestamp : Thu Mar 25 16:42:58 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. +// 05/23/07 - Added wire declaration for internal signals. + +`timescale 1 ps / 1 ps + + +module NOR2B2 (O, I0, I1); + + output O; + + input I0, I1; + + wire i0_inv; + wire i1_inv; + + not N1 (i1_inv, I1); + not N0 (i0_inv, I0); + nor O1 (O, i0_inv, i1_inv); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/NOR3.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/NOR3.v new file mode 100644 index 0000000..45f400d --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/NOR3.v @@ -0,0 +1,33 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/NOR3.v,v 1.6 2007/05/23 21:43:39 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / 3-input NOR Gate +// /___/ /\ Filename : NOR3.v +// \ \ / \ Timestamp : Thu Mar 25 16:42:58 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. + +`timescale 1 ps / 1 ps + + +module NOR3 (O, I0, I1, I2); + + output O; + + input I0, I1, I2; + + nor O1 (O, I0, I1, I2); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/NOR3B1.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/NOR3B1.v new file mode 100644 index 0000000..f05493b --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/NOR3B1.v @@ -0,0 +1,37 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/NOR3B1.v,v 1.6 2007/05/23 21:43:39 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / 3-input NOR Gate +// /___/ /\ Filename : NOR3B1.v +// \ \ / \ Timestamp : Thu Mar 25 16:42:58 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. +// 05/23/07 - Added wire declaration for internal signals. + +`timescale 1 ps / 1 ps + + +module NOR3B1 (O, I0, I1, I2); + + output O; + + input I0, I1, I2; + + wire i0_inv; + + not N0 (i0_inv, I0); + nor O1 (O, i0_inv, I1, I2); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/NOR3B2.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/NOR3B2.v new file mode 100644 index 0000000..77a7182 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/NOR3B2.v @@ -0,0 +1,39 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/NOR3B2.v,v 1.6 2007/05/23 21:43:39 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / 3-input NOR Gate +// /___/ /\ Filename : NOR3B2.v +// \ \ / \ Timestamp : Thu Mar 25 16:42:58 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. +// 05/23/07 - Added wire declaration for internal signals. + +`timescale 1 ps / 1 ps + + +module NOR3B2 (O, I0, I1, I2); + + output O; + + input I0, I1, I2; + + wire i0_inv; + wire i1_inv; + + not N1 (i1_inv, I1); + not N0 (i0_inv, I0); + nor O1 (O, i0_inv, i1_inv, I2); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/NOR3B3.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/NOR3B3.v new file mode 100644 index 0000000..807bff0 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/NOR3B3.v @@ -0,0 +1,41 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/NOR3B3.v,v 1.6 2007/05/23 21:43:39 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / 3-input NOR Gate +// /___/ /\ Filename : NOR3B3.v +// \ \ / \ Timestamp : Thu Mar 25 16:42:58 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. +// 05/23/07 - Added wire declaration for internal signals. + +`timescale 1 ps / 1 ps + + +module NOR3B3 (O, I0, I1, I2); + + output O; + + input I0, I1, I2; + + wire i0_inv; + wire i1_inv; + wire i2_inv; + + not N2 (i2_inv, I2); + not N1 (i1_inv, I1); + not N0 (i0_inv, I0); + nor O1 (O, i0_inv, i1_inv, i2_inv); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/NOR4.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/NOR4.v new file mode 100644 index 0000000..5ef4558 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/NOR4.v @@ -0,0 +1,33 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/NOR4.v,v 1.6 2007/05/23 21:43:39 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / 4-input NOR Gate +// /___/ /\ Filename : NOR4.v +// \ \ / \ Timestamp : Thu Mar 25 16:42:58 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. + +`timescale 1 ps / 1 ps + + +module NOR4 (O, I0, I1, I2, I3); + + output O; + + input I0, I1, I2, I3; + + nor O1 (O, I0, I1, I2, I3); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/NOR4B1.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/NOR4B1.v new file mode 100644 index 0000000..5eae06c --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/NOR4B1.v @@ -0,0 +1,37 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/NOR4B1.v,v 1.6 2007/05/23 21:43:39 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / 4-input NOR Gate +// /___/ /\ Filename : NOR4B1.v +// \ \ / \ Timestamp : Thu Mar 25 16:42:58 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. +// 05/23/07 - Added wire declaration for internal signals. + +`timescale 1 ps / 1 ps + + +module NOR4B1 (O, I0, I1, I2, I3); + + output O; + + input I0, I1, I2, I3; + + wire i0_inv; + + not N0 (i0_inv, I0); + nor O1 (O, i0_inv, I1, I2, I3); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/NOR4B2.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/NOR4B2.v new file mode 100644 index 0000000..ebdb949 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/NOR4B2.v @@ -0,0 +1,39 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/NOR4B2.v,v 1.6 2007/05/23 21:43:39 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / 4-input NOR Gate +// /___/ /\ Filename : NOR4B2.v +// \ \ / \ Timestamp : Thu Mar 25 16:42:59 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. +// 05/23/07 - Added wire declaration for internal signals. + +`timescale 1 ps / 1 ps + + +module NOR4B2 (O, I0, I1, I2, I3); + + output O; + + input I0, I1, I2, I3; + + wire i0_inv; + wire i1_inv; + + not N1 (i1_inv, I1); + not N0 (i0_inv, I0); + nor O1 (O, i0_inv, i1_inv, I2, I3); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/NOR4B3.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/NOR4B3.v new file mode 100644 index 0000000..e8f63a4 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/NOR4B3.v @@ -0,0 +1,41 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/NOR4B3.v,v 1.6 2007/05/23 21:43:39 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / 4-input NOR Gate +// /___/ /\ Filename : NOR4B3.v +// \ \ / \ Timestamp : Thu Mar 25 16:42:59 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. +// 05/23/07 - Added wire declaration for internal signals. + +`timescale 1 ps / 1 ps + + +module NOR4B3 (O, I0, I1, I2, I3); + + output O; + + input I0, I1, I2, I3; + + wire i0_inv; + wire i1_inv; + wire i2_inv; + + not N2 (i2_inv, I2); + not N1 (i1_inv, I1); + not N0 (i0_inv, I0); + nor O1 (O, i0_inv, i1_inv, i2_inv, I3); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/NOR4B4.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/NOR4B4.v new file mode 100644 index 0000000..09fea67 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/NOR4B4.v @@ -0,0 +1,43 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/NOR4B4.v,v 1.6 2007/05/23 21:43:39 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / 4-input NOR Gate +// /___/ /\ Filename : NOR4B4.v +// \ \ / \ Timestamp : Thu Mar 25 16:42:59 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. +// 05/23/07 - Added wire declaration for internal signals. + +`timescale 1 ps / 1 ps + + +module NOR4B4 (O, I0, I1, I2, I3); + + output O; + + input I0, I1, I2, I3; + + wire i0_inv; + wire i1_inv; + wire i2_inv; + wire i3_inv; + + not N3 (i3_inv, I3); + not N2 (i2_inv, I2); + not N1 (i1_inv, I1); + not N0 (i0_inv, I0); + nor O1 (O, i0_inv, i1_inv, i2_inv, i3_inv); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/NOR5.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/NOR5.v new file mode 100644 index 0000000..9a4a57a --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/NOR5.v @@ -0,0 +1,33 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/NOR5.v,v 1.6 2007/05/23 21:43:40 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / 5-input NOR Gate +// /___/ /\ Filename : NOR5.v +// \ \ / \ Timestamp : Thu Mar 25 16:42:59 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. + +`timescale 1 ps / 1 ps + + +module NOR5 (O, I0, I1, I2, I3, I4); + + output O; + + input I0, I1, I2, I3, I4; + + nor O1 (O, I0, I1, I2, I3, I4); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/NOR5B1.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/NOR5B1.v new file mode 100644 index 0000000..d115cdf --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/NOR5B1.v @@ -0,0 +1,37 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/NOR5B1.v,v 1.6 2007/05/23 21:43:39 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / 5-input NOR Gate +// /___/ /\ Filename : NOR5B1.v +// \ \ / \ Timestamp : Thu Mar 25 16:42:59 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. +// 05/23/07 - Added wire declaration for internal signals. + +`timescale 1 ps / 1 ps + + +module NOR5B1 (O, I0, I1, I2, I3, I4); + + output O; + + input I0, I1, I2, I3, I4; + + wire i0_inv; + + not N0 (i0_inv, I0); + nor O1 (O, i0_inv, I1, I2, I3, I4); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/NOR5B2.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/NOR5B2.v new file mode 100644 index 0000000..1cc5920 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/NOR5B2.v @@ -0,0 +1,39 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/NOR5B2.v,v 1.6 2007/05/23 21:43:39 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / 5-input NOR Gate +// /___/ /\ Filename : NOR5B2.v +// \ \ / \ Timestamp : Thu Mar 25 16:42:59 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. +// 05/23/07 - Added wire declaration for internal signals. + +`timescale 1 ps / 1 ps + + +module NOR5B2 (O, I0, I1, I2, I3, I4); + + output O; + + input I0, I1, I2, I3, I4; + + wire i0_inv; + wire i1_inv; + + not N1 (i1_inv, I1); + not N0 (i0_inv, I0); + nor O1 (O, i0_inv, i1_inv, I2, I3, I4); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/NOR5B3.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/NOR5B3.v new file mode 100644 index 0000000..15e0df0 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/NOR5B3.v @@ -0,0 +1,41 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/NOR5B3.v,v 1.6 2007/05/23 21:43:39 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / 5-input NOR Gate +// /___/ /\ Filename : NOR5B3.v +// \ \ / \ Timestamp : Thu Mar 25 16:42:59 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. +// 05/23/07 - Added wire declaration for internal signals. + +`timescale 1 ps / 1 ps + + +module NOR5B3 (O, I0, I1, I2, I3, I4); + + output O; + + input I0, I1, I2, I3, I4; + + wire i0_inv; + wire i1_inv; + wire i2_inv; + + not N2 (i2_inv, I2); + not N1 (i1_inv, I1); + not N0 (i0_inv, I0); + nor O1 (O, i0_inv, i1_inv, i2_inv, I3, I4); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/NOR5B4.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/NOR5B4.v new file mode 100644 index 0000000..9fa632a --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/NOR5B4.v @@ -0,0 +1,43 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/NOR5B4.v,v 1.6 2007/05/23 21:43:40 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / 5-input NOR Gate +// /___/ /\ Filename : NOR5B4.v +// \ \ / \ Timestamp : Thu Mar 25 16:42:59 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. +// 05/23/07 - Added wire declaration for internal signals. + +`timescale 1 ps / 1 ps + + +module NOR5B4 (O, I0, I1, I2, I3, I4); + + output O; + + input I0, I1, I2, I3, I4; + + wire i0_inv; + wire i1_inv; + wire i2_inv; + wire i3_inv; + + not N3 (i3_inv, I3); + not N2 (i2_inv, I2); + not N1 (i1_inv, I1); + not N0 (i0_inv, I0); + nor O1 (O, i0_inv, i1_inv, i2_inv, i3_inv, I4); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/NOR5B5.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/NOR5B5.v new file mode 100644 index 0000000..e0518d2 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/NOR5B5.v @@ -0,0 +1,45 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/NOR5B5.v,v 1.6 2007/05/23 21:43:40 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / 5-input NOR Gate +// /___/ /\ Filename : NOR5B5.v +// \ \ / \ Timestamp : Thu Mar 25 16:42:59 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. +// 05/23/07 - Added wire declaration for internal signals. + +`timescale 1 ps / 1 ps + + +module NOR5B5 (O, I0, I1, I2, I3, I4); + + output O; + + input I0, I1, I2, I3, I4; + + wire i0_inv; + wire i1_inv; + wire i2_inv; + wire i3_inv; + wire i4_inv; + + not N4 (i4_inv, I4); + not N3 (i3_inv, I3); + not N2 (i2_inv, I2); + not N1 (i1_inv, I1); + not N0 (i0_inv, I0); + nor O1 (O, i0_inv, i1_inv, i2_inv, i3_inv, i4_inv); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUF.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUF.v new file mode 100644 index 0000000..7de5055 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUF.v @@ -0,0 +1,57 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/OBUF.v,v 1.10 2009/08/21 23:55:43 harikr Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Output Buffer +// /___/ /\ Filename : OBUF.v +// \ \ / \ Timestamp : Thu Mar 25 16:42:59 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 02/22/06 - CR#226003 - Added integer, real parameter type +// 05/23/07 - Changed timescale to 1 ps / 1 ps. + +`timescale 1 ps / 1 ps + + +module OBUF (O, I); + + parameter CAPACITANCE = "DONT_CARE"; + parameter integer DRIVE = 12; + parameter IOSTANDARD = "DEFAULT"; + parameter SLEW = "SLOW"; + + output O; + + input I; + + tri0 GTS = glbl.GTS; + + bufif0 B1 (O, I, GTS); + + initial begin + + case (CAPACITANCE) + + "LOW", "NORMAL", "DONT_CARE" : ; + default : begin + $display("Attribute Syntax Error : The attribute CAPACITANCE on OBUF instance %m is set to %s. Legal values for this attribute are DONT_CARE, LOW or NORMAL.", CAPACITANCE); + $finish; + end + + endcase + + end + +endmodule + + + + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUFDS.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUFDS.v new file mode 100644 index 0000000..dfdd9fa --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUFDS.v @@ -0,0 +1,53 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/OBUFDS.v,v 1.8 2009/08/21 23:55:43 harikr Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Differential Signaling Output Buffer +// /___/ /\ Filename : OBUFDS.v +// \ \ / \ Timestamp : Thu Mar 25 16:43:00 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. + +`timescale 1 ps / 1 ps + + +module OBUFDS (O, OB, I); + + parameter CAPACITANCE = "DONT_CARE"; + parameter IOSTANDARD = "DEFAULT"; + + output O, OB; + input I; + + tri0 GTS = glbl.GTS; + + bufif0 B1 (O, I, GTS); + notif0 N1 (OB, I, GTS); + + initial begin + + case (CAPACITANCE) + + "LOW", "NORMAL", "DONT_CARE" : ; + default : begin + $display("Attribute Syntax Error : The attribute CAPACITANCE on OBUFDS instance %m is set to %s. Legal values for this attribute are DONT_CARE, LOW or NORMAL.", CAPACITANCE); + $finish; + end + + endcase + + end + +endmodule + + + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUFDS_BLVDS_25.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUFDS_BLVDS_25.v new file mode 100644 index 0000000..4b89026 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUFDS_BLVDS_25.v @@ -0,0 +1,37 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/OBUFDS_BLVDS_25.v,v 1.6 2007/05/23 21:43:40 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Differential Signaling Output Buffer with BLVDS_25 I/O Standard +// /___/ /\ Filename : OBUFDS_BLVDS_25.v +// \ \ / \ Timestamp : Thu Mar 25 16:43:00 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. + +`timescale 1 ps / 1 ps + + +module OBUFDS_BLVDS_25 (O, OB, I); + + output O, OB; + + input I; + + tri0 GTS = glbl.GTS; + + bufif0 B1 (O, I, GTS); + notif0 N1 (OB, I, GTS); + + +endmodule + + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUFDS_LDT_25.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUFDS_LDT_25.v new file mode 100644 index 0000000..5ea0fc7 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUFDS_LDT_25.v @@ -0,0 +1,37 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/OBUFDS_LDT_25.v,v 1.6 2007/05/23 21:43:40 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Differential Signaling Output Buffer with LDT_25 I/O Standard +// /___/ /\ Filename : OBUFDS_LDT_25.v +// \ \ / \ Timestamp : Thu Mar 25 16:43:00 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. + +`timescale 1 ps / 1 ps + + +module OBUFDS_LDT_25 (O, OB, I); + + output O, OB; + + input I; + + tri0 GTS = glbl.GTS; + + bufif0 B1 (O, I, GTS); + notif0 N1 (OB, I, GTS); + + +endmodule + + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUFDS_LVDSEXT_25.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUFDS_LVDSEXT_25.v new file mode 100644 index 0000000..272904f --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUFDS_LVDSEXT_25.v @@ -0,0 +1,37 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/OBUFDS_LVDSEXT_25.v,v 1.6 2007/05/23 21:43:40 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Differential Signaling Output Buffer with LVDSEXT_25 I/O Standard +// /___/ /\ Filename : OBUFDS_LVDSEXT_25.v +// \ \ / \ Timestamp : Thu Mar 25 16:43:00 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. + +`timescale 1 ps / 1 ps + + +module OBUFDS_LVDSEXT_25 (O, OB, I); + + output O, OB; + + input I; + + tri0 GTS = glbl.GTS; + + bufif0 B1 (O, I, GTS); + notif0 N1 (OB, I, GTS); + + +endmodule + + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUFDS_LVDSEXT_33.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUFDS_LVDSEXT_33.v new file mode 100644 index 0000000..5df5ef5 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUFDS_LVDSEXT_33.v @@ -0,0 +1,37 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/OBUFDS_LVDSEXT_33.v,v 1.6 2007/05/23 21:43:40 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Differential Signaling Output Buffer with LVDSEXT_33 I/O Standard +// /___/ /\ Filename : OBUFDS_LVDSEXT_33.v +// \ \ / \ Timestamp : Thu Mar 25 16:43:00 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. + +`timescale 1 ps / 1 ps + + +module OBUFDS_LVDSEXT_33 (O, OB, I); + + output O, OB; + + input I; + + tri0 GTS = glbl.GTS; + + bufif0 B1 (O, I, GTS); + notif0 N1 (OB, I, GTS); + + +endmodule + + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUFDS_LVDS_25.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUFDS_LVDS_25.v new file mode 100644 index 0000000..2b250e1 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUFDS_LVDS_25.v @@ -0,0 +1,37 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/OBUFDS_LVDS_25.v,v 1.6 2007/05/23 21:43:40 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Differential Signaling Output Buffer with LVDS_25 I/O Standard +// /___/ /\ Filename : OBUFDS_LVDS_25.v +// \ \ / \ Timestamp : Thu Mar 25 16:43:00 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. + +`timescale 1 ps / 1 ps + + +module OBUFDS_LVDS_25 (O, OB, I); + + output O, OB; + + input I; + + tri0 GTS = glbl.GTS; + + bufif0 B1 (O, I, GTS); + notif0 N1 (OB, I, GTS); + + +endmodule + + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUFDS_LVDS_33.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUFDS_LVDS_33.v new file mode 100644 index 0000000..6802f14 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUFDS_LVDS_33.v @@ -0,0 +1,37 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/OBUFDS_LVDS_33.v,v 1.6 2007/05/23 21:43:40 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Differential Signaling Output Buffer with LVDS_33 I/O Standard +// /___/ /\ Filename : OBUFDS_LVDS_33.v +// \ \ / \ Timestamp : Thu Mar 25 16:43:00 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. + +`timescale 1 ps / 1 ps + + +module OBUFDS_LVDS_33 (O, OB, I); + + output O, OB; + + input I; + + tri0 GTS = glbl.GTS; + + bufif0 B1 (O, I, GTS); + notif0 N1 (OB, I, GTS); + + +endmodule + + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUFDS_LVPECL_25.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUFDS_LVPECL_25.v new file mode 100644 index 0000000..df842fd --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUFDS_LVPECL_25.v @@ -0,0 +1,37 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/OBUFDS_LVPECL_25.v,v 1.6 2007/05/23 21:43:40 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Differential Signaling Output Buffer with LVPECL_25 I/O Standard +// /___/ /\ Filename : OBUFDS_LVPECL_25.v +// \ \ / \ Timestamp : Thu Mar 25 16:43:00 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. + +`timescale 1 ps / 1 ps + + +module OBUFDS_LVPECL_25 (O, OB, I); + + output O, OB; + + input I; + + tri0 GTS = glbl.GTS; + + bufif0 B1 (O, I, GTS); + notif0 N1 (OB, I, GTS); + + +endmodule + + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUFDS_LVPECL_33.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUFDS_LVPECL_33.v new file mode 100644 index 0000000..f8f75af --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUFDS_LVPECL_33.v @@ -0,0 +1,37 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/OBUFDS_LVPECL_33.v,v 1.6 2007/05/23 21:43:40 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Differential Signaling Output Buffer with LVPECL_33 I/O Standard +// /___/ /\ Filename : OBUFDS_LVPECL_33.v +// \ \ / \ Timestamp : Thu Mar 25 16:43:00 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. + +`timescale 1 ps / 1 ps + + +module OBUFDS_LVPECL_33 (O, OB, I); + + output O, OB; + + input I; + + tri0 GTS = glbl.GTS; + + bufif0 B1 (O, I, GTS); + notif0 N1 (OB, I, GTS); + + +endmodule + + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUFDS_ULVDS_25.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUFDS_ULVDS_25.v new file mode 100644 index 0000000..8bfae23 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUFDS_ULVDS_25.v @@ -0,0 +1,37 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/OBUFDS_ULVDS_25.v,v 1.6 2007/05/23 21:43:40 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Differential Signaling Output Buffer with ULVDS_25 I/O Standard +// /___/ /\ Filename : OBUFDS_ULVDS_25.v +// \ \ / \ Timestamp : Thu Mar 25 16:43:00 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. + +`timescale 1 ps / 1 ps + + +module OBUFDS_ULVDS_25 (O, OB, I); + + output O, OB; + + input I; + + tri0 GTS = glbl.GTS; + + bufif0 B1 (O, I, GTS); + notif0 N1 (OB, I, GTS); + + +endmodule + + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUFT.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUFT.v new file mode 100644 index 0000000..d8311ea --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUFT.v @@ -0,0 +1,57 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/OBUFT.v,v 1.10 2009/08/21 23:55:43 harikr Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / 3-State Output Buffer +// /___/ /\ Filename : OBUFT.v +// \ \ / \ Timestamp : Thu Mar 25 16:43:01 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 02/22/06 - CR#226003 - Added integer, real parameter type +// 05/23/07 - Changed timescale to 1 ps / 1 ps. +// 05/23/07 - Added wire declaration for internal signals. + +`timescale 1 ps / 1 ps + + +module OBUFT (O, I, T); + + parameter CAPACITANCE = "DONT_CARE"; + parameter integer DRIVE = 12; + parameter IOSTANDARD = "DEFAULT"; + parameter SLEW = "SLOW"; + + output O; + input I, T; + + wire ts; + + tri0 GTS = glbl.GTS; + + or O1 (ts, GTS, T); + bufif0 T1 (O, I, ts); + + initial begin + + case (CAPACITANCE) + + "LOW", "NORMAL", "DONT_CARE" : ; + default : begin + $display("Attribute Syntax Error : The attribute CAPACITANCE on OBUFT instance %m is set to %s. Legal values for this attribute are DONT_CARE, LOW or NORMAL.", CAPACITANCE); + $finish; + end + + endcase + + end + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUFTDS.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUFTDS.v new file mode 100644 index 0000000..ca1d494 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUFTDS.v @@ -0,0 +1,60 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/OBUFTDS.v,v 1.8.64.1 2010/05/12 23:22:20 fphillip Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / 3-State Differential Signaling Output Buffer +// /___/ /\ Filename : OBUFTDS.v +// \ \ / \ Timestamp : Thu Mar 25 16:43:01 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. +// 05/23/07 - Added wire declaration for internal signals. +// 05/12/10 - CR 559468 - Added DRC warnings for LVDS_25 bus architectures. +// End Revision + +`timescale 1 ps / 1 ps + +module OBUFTDS (O, OB, I, T); + + parameter CAPACITANCE = "DONT_CARE"; + parameter IOSTANDARD = "DEFAULT"; + + output O, OB; + input I, T; + + wire ts; + + tri0 GTS = glbl.GTS; + + or O1 (ts, GTS, T); + bufif0 B1 (O, I, ts); + notif0 N1 (OB, I, ts); + + initial begin + + case (CAPACITANCE) + + "LOW", "NORMAL", "DONT_CARE" : ; + default : begin + $display("Attribute Syntax Error : The attribute CAPACITANCE on OBUFTDS instance %m is set to %s. Legal values for this attribute are DONT_CARE, LOW or NORMAL.", CAPACITANCE); + $finish; + end + + endcase + + if((IOSTANDARD == "LVDS_25") || (IOSTANDARD == "LVDSEXT_25")) begin + $display("DRC Warning : The IOSTANDARD attribute on OBUFTDS instance %m is set to %s. LVDS_25 is a fixed impedance structure optimized to 100ohm differential. If the intended usage is a bus architecture, please use BLVDS. This is only intended to be used in point to point transmissions that do not have turn around timing requirements", IOSTANDARD); + end + + + end + +endmodule diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUFTDS_BLVDS_25.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUFTDS_BLVDS_25.v new file mode 100644 index 0000000..2780873 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUFTDS_BLVDS_25.v @@ -0,0 +1,41 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/OBUFTDS_BLVDS_25.v,v 1.6 2007/05/23 21:43:41 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / 3-State Differential Signaling Output Buffer with BLVDS_25 I/O Standard +// /___/ /\ Filename : OBUFTDS_BLVDS_25.v +// \ \ / \ Timestamp : Thu Mar 25 16:43:01 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. +// 05/23/07 - Added wire declaration for internal signals. + +`timescale 1 ps / 1 ps + + +module OBUFTDS_BLVDS_25 (O, OB, I, T); + + output O, OB; + + input I, T; + + wire ts; + + tri0 GTS = glbl.GTS; + + or O1 (ts, GTS, T); + bufif0 B1 (O, I, ts); + notif0 N1 (OB, I, ts); + + +endmodule + + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUFTDS_LDT_25.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUFTDS_LDT_25.v new file mode 100644 index 0000000..5623e50 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUFTDS_LDT_25.v @@ -0,0 +1,41 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/OBUFTDS_LDT_25.v,v 1.6 2007/05/23 21:43:41 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / 3-State Differential Signaling Output Buffer with LDT_25 I/O Standard +// /___/ /\ Filename : OBUFTDS_LDT_25.v +// \ \ / \ Timestamp : Thu Mar 25 16:43:01 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. +// 05/23/07 - Added wire declaration for internal signals. + +`timescale 1 ps / 1 ps + + +module OBUFTDS_LDT_25 (O, OB, I, T); + + output O, OB; + + input I, T; + + wire ts; + + tri0 GTS = glbl.GTS; + + or O1 (ts, GTS, T); + bufif0 B1 (O, I, ts); + notif0 N1 (OB, I, ts); + + +endmodule + + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUFTDS_LVDSEXT_25.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUFTDS_LVDSEXT_25.v new file mode 100644 index 0000000..7b4ab33 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUFTDS_LVDSEXT_25.v @@ -0,0 +1,41 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/OBUFTDS_LVDSEXT_25.v,v 1.6 2007/05/23 21:43:41 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / 3-State Differential Signaling Output Buffer with LVDSEXT_25 I/O Standard +// /___/ /\ Filename : OBUFTDS_LVDSEXT_25.v +// \ \ / \ Timestamp : Thu Mar 25 16:43:01 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. +// 05/23/07 - Added wire declaration for internal signals. + +`timescale 1 ps / 1 ps + + +module OBUFTDS_LVDSEXT_25 (O, OB, I, T); + + output O, OB; + + input I, T; + + wire ts; + + tri0 GTS = glbl.GTS; + + or O1 (ts, GTS, T); + bufif0 B1 (O, I, ts); + notif0 N1 (OB, I, ts); + + +endmodule + + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUFTDS_LVDSEXT_33.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUFTDS_LVDSEXT_33.v new file mode 100644 index 0000000..e42c147 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUFTDS_LVDSEXT_33.v @@ -0,0 +1,41 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/OBUFTDS_LVDSEXT_33.v,v 1.6 2007/05/23 21:43:41 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / 3-State Differential Signaling Output Buffer with LVDSEXT_33 I/O Standard +// /___/ /\ Filename : OBUFTDS_LVDSEXT_33.v +// \ \ / \ Timestamp : Thu Mar 25 16:43:01 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. +// 05/23/07 - Added wire declaration for internal signals. + +`timescale 1 ps / 1 ps + + +module OBUFTDS_LVDSEXT_33 (O, OB, I, T); + + output O, OB; + + input I, T; + + wire ts; + + tri0 GTS = glbl.GTS; + + or O1 (ts, GTS, T); + bufif0 B1 (O, I, ts); + notif0 N1 (OB, I, ts); + + +endmodule + + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUFTDS_LVDS_25.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUFTDS_LVDS_25.v new file mode 100644 index 0000000..fba1fd8 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUFTDS_LVDS_25.v @@ -0,0 +1,41 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/OBUFTDS_LVDS_25.v,v 1.6 2007/05/23 21:43:41 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / 3-State Differential Signaling Output Buffer with LVDS_25 I/O Standard +// /___/ /\ Filename : OBUFTDS_LVDS_25.v +// \ \ / \ Timestamp : Thu Mar 25 16:43:01 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. +// 05/23/07 - Added wire declaration for internal signals. + +`timescale 1 ps / 1 ps + + +module OBUFTDS_LVDS_25 (O, OB, I, T); + + output O, OB; + + input I, T; + + wire ts; + + tri0 GTS = glbl.GTS; + + or O1 (ts, GTS, T); + bufif0 B1 (O, I, ts); + notif0 N1 (OB, I, ts); + + +endmodule + + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUFTDS_LVDS_33.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUFTDS_LVDS_33.v new file mode 100644 index 0000000..aa98a68 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUFTDS_LVDS_33.v @@ -0,0 +1,41 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/OBUFTDS_LVDS_33.v,v 1.6 2007/05/23 21:43:41 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / 3-State Differential Signaling Output Buffer with LVDS_33 I/O Standard +// /___/ /\ Filename : OBUFTDS_LVDS_33.v +// \ \ / \ Timestamp : Thu Mar 25 16:43:01 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. +// 05/23/07 - Added wire declaration for internal signals. + +`timescale 1 ps / 1 ps + + +module OBUFTDS_LVDS_33 (O, OB, I, T); + + output O, OB; + + input I, T; + + wire ts; + + tri0 GTS = glbl.GTS; + + or O1 (ts, GTS, T); + bufif0 B1 (O, I, ts); + notif0 N1 (OB, I, ts); + + +endmodule + + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUFTDS_LVPECL_25.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUFTDS_LVPECL_25.v new file mode 100644 index 0000000..63bf63a --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUFTDS_LVPECL_25.v @@ -0,0 +1,41 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/OBUFTDS_LVPECL_25.v,v 1.6 2007/05/23 21:43:41 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / 3-State Differential Signaling Output Buffer with LVPECL_25 I/O Standard +// /___/ /\ Filename : OBUFTDS_LVPECL_25.v +// \ \ / \ Timestamp : Thu Mar 25 16:43:01 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. +// 05/23/07 - Added wire declaration for internal signals. + +`timescale 1 ps / 1 ps + + +module OBUFTDS_LVPECL_25 (O, OB, I, T); + + output O, OB; + + input I, T; + + wire ts; + + tri0 GTS = glbl.GTS; + + or O1 (ts, GTS, T); + bufif0 B1 (O, I, ts); + notif0 N1 (OB, I, ts); + + +endmodule + + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUFTDS_LVPECL_33.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUFTDS_LVPECL_33.v new file mode 100644 index 0000000..72f45c5 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUFTDS_LVPECL_33.v @@ -0,0 +1,41 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/OBUFTDS_LVPECL_33.v,v 1.6 2007/05/23 21:43:41 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / 3-State Differential Signaling Output Buffer with LVPECL_33 I/O Standard +// /___/ /\ Filename : OBUFTDS_LVPECL_33.v +// \ \ / \ Timestamp : Thu Mar 25 16:43:02 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. +// 05/23/07 - Added wire declaration for internal signals. + +`timescale 1 ps / 1 ps + + +module OBUFTDS_LVPECL_33 (O, OB, I, T); + + output O, OB; + + input I, T; + + wire ts; + + tri0 GTS = glbl.GTS; + + or O1 (ts, GTS, T); + bufif0 B1 (O, I, ts); + notif0 N1 (OB, I, ts); + + +endmodule + + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUFTDS_ULVDS_25.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUFTDS_ULVDS_25.v new file mode 100644 index 0000000..2cabf9f --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUFTDS_ULVDS_25.v @@ -0,0 +1,41 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/OBUFTDS_ULVDS_25.v,v 1.6 2007/05/23 21:43:41 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / 3-State Differential Signaling Output Buffer with ULVDS_25 I/O Standard +// /___/ /\ Filename : OBUFTDS_ULVDS_25.v +// \ \ / \ Timestamp : Thu Mar 25 16:43:02 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. +// 05/23/07 - Added wire declaration for internal signals. + +`timescale 1 ps / 1 ps + + +module OBUFTDS_ULVDS_25 (O, OB, I, T); + + output O, OB; + + input I, T; + + wire ts; + + tri0 GTS = glbl.GTS; + + or O1 (ts, GTS, T); + bufif0 B1 (O, I, ts); + notif0 N1 (OB, I, ts); + + +endmodule + + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUFT_AGP.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUFT_AGP.v new file mode 100644 index 0000000..8007d16 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUFT_AGP.v @@ -0,0 +1,39 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/OBUFT_AGP.v,v 1.6 2007/05/23 21:43:41 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / 3-State Output Buffer with AGP I/O Standard +// /___/ /\ Filename : OBUFT_AGP.v +// \ \ / \ Timestamp : Thu Mar 25 16:43:02 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. +// 05/23/07 - Added wire declaration for internal signals. + +`timescale 1 ps / 1 ps + + +module OBUFT_AGP (O, I, T); + + output O; + + input I, T; + + wire ts; + + tri0 GTS = glbl.GTS; + + or O1 (ts, GTS, T); + bufif0 T1 (O, I, ts); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUFT_CTT.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUFT_CTT.v new file mode 100644 index 0000000..7e9d5c6 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUFT_CTT.v @@ -0,0 +1,39 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/OBUFT_CTT.v,v 1.6 2007/05/23 21:43:41 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / 3-State Output Buffer with CTT I/O Standard +// /___/ /\ Filename : OBUFT_CTT.v +// \ \ / \ Timestamp : Thu Mar 25 16:43:02 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. +// 05/23/07 - Added wire declaration for internal signals. + +`timescale 1 ps / 1 ps + + +module OBUFT_CTT (O, I, T); + + output O; + + input I, T; + + wire ts; + + tri0 GTS = glbl.GTS; + + or O1 (ts, GTS, T); + bufif0 T1 (O, I, ts); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUFT_F_12.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUFT_F_12.v new file mode 100644 index 0000000..9439b93 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUFT_F_12.v @@ -0,0 +1,39 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/OBUFT_F_12.v,v 1.6 2007/05/23 21:43:41 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / 3-State Output Buffer with Fast Slew 12 mA Drive +// /___/ /\ Filename : OBUFT_F_12.v +// \ \ / \ Timestamp : Thu Mar 25 16:43:02 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. +// 05/23/07 - Added wire declaration for internal signals. + +`timescale 1 ps / 1 ps + + +module OBUFT_F_12 (O, I, T); + + output O; + + input I, T; + + wire ts; + + tri0 GTS = glbl.GTS; + + or O1 (ts, GTS, T); + bufif0 T1 (O, I, ts); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUFT_F_16.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUFT_F_16.v new file mode 100644 index 0000000..8c2e15e --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUFT_F_16.v @@ -0,0 +1,39 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/OBUFT_F_16.v,v 1.6 2007/05/23 21:43:42 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / 3-State Output Buffer with Fast Slew 16 mA Drive +// /___/ /\ Filename : OBUFT_F_16.v +// \ \ / \ Timestamp : Thu Mar 25 16:43:02 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. +// 05/23/07 - Added wire declaration for internal signals. + +`timescale 1 ps / 1 ps + + +module OBUFT_F_16 (O, I, T); + + output O; + + input I, T; + + wire ts; + + tri0 GTS = glbl.GTS; + + or O1 (ts, GTS, T); + bufif0 T1 (O, I, ts); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUFT_F_2.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUFT_F_2.v new file mode 100644 index 0000000..e07a115 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUFT_F_2.v @@ -0,0 +1,39 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/OBUFT_F_2.v,v 1.6 2007/05/23 21:43:42 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / 3-State Output Buffer with Fast Slew 2 mA Drive +// /___/ /\ Filename : OBUFT_F_2.v +// \ \ / \ Timestamp : Thu Mar 25 16:43:02 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. +// 05/23/07 - Added wire declaration for internal signals. + +`timescale 1 ps / 1 ps + + +module OBUFT_F_2 (O, I, T); + + output O; + + input I, T; + + wire ts; + + tri0 GTS = glbl.GTS; + + or O1 (ts, GTS, T); + bufif0 T1 (O, I, ts); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUFT_F_24.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUFT_F_24.v new file mode 100644 index 0000000..78e530a --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUFT_F_24.v @@ -0,0 +1,39 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/OBUFT_F_24.v,v 1.6 2007/05/23 21:43:42 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / 3-State Output Buffer with Fast Slew 24 mA Drive +// /___/ /\ Filename : OBUFT_F_24.v +// \ \ / \ Timestamp : Thu Mar 25 16:43:02 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. +// 05/23/07 - Added wire declaration for internal signals. + +`timescale 1 ps / 1 ps + + +module OBUFT_F_24 (O, I, T); + + output O; + + input I, T; + + wire ts; + + tri0 GTS = glbl.GTS; + + or O1 (ts, GTS, T); + bufif0 T1 (O, I, ts); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUFT_F_4.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUFT_F_4.v new file mode 100644 index 0000000..ec957bf --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUFT_F_4.v @@ -0,0 +1,39 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/OBUFT_F_4.v,v 1.6 2007/05/23 21:43:42 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / 3-State Output Buffer with Fast Slew 4 mA Drive +// /___/ /\ Filename : OBUFT_F_4.v +// \ \ / \ Timestamp : Thu Mar 25 16:43:02 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. +// 05/23/07 - Added wire declaration for internal signals. + +`timescale 1 ps / 1 ps + + +module OBUFT_F_4 (O, I, T); + + output O; + + input I, T; + + wire ts; + + tri0 GTS = glbl.GTS; + + or O1 (ts, GTS, T); + bufif0 T1 (O, I, ts); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUFT_F_6.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUFT_F_6.v new file mode 100644 index 0000000..5964515 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUFT_F_6.v @@ -0,0 +1,39 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/OBUFT_F_6.v,v 1.6 2007/05/23 21:43:42 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / 3-State Output Buffer with Fast Slew 6 mA Drive +// /___/ /\ Filename : OBUFT_F_6.v +// \ \ / \ Timestamp : Thu Mar 25 16:43:02 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. +// 05/23/07 - Added wire declaration for internal signals. + +`timescale 1 ps / 1 ps + + +module OBUFT_F_6 (O, I, T); + + output O; + + input I, T; + + wire ts; + + tri0 GTS = glbl.GTS; + + or O1 (ts, GTS, T); + bufif0 T1 (O, I, ts); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUFT_F_8.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUFT_F_8.v new file mode 100644 index 0000000..a6f2b51 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUFT_F_8.v @@ -0,0 +1,39 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/OBUFT_F_8.v,v 1.6 2007/05/23 21:43:42 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / 3-State Output Buffer with Fast Slew 8 mA Drive +// /___/ /\ Filename : OBUFT_F_8.v +// \ \ / \ Timestamp : Thu Mar 25 16:43:02 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. +// 05/23/07 - Added wire declaration for internal signals. + +`timescale 1 ps / 1 ps + + +module OBUFT_F_8 (O, I, T); + + output O; + + input I, T; + + wire ts; + + tri0 GTS = glbl.GTS; + + or O1 (ts, GTS, T); + bufif0 T1 (O, I, ts); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUFT_GTL.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUFT_GTL.v new file mode 100644 index 0000000..2ab07da --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUFT_GTL.v @@ -0,0 +1,39 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/OBUFT_GTL.v,v 1.6 2007/05/23 21:43:42 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / 3-State Output Buffer with GTL I/O Standard +// /___/ /\ Filename : OBUFT_GTL.v +// \ \ / \ Timestamp : Thu Mar 25 16:43:03 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. +// 05/23/07 - Added wire declaration for internal signals. + +`timescale 1 ps / 1 ps + + +module OBUFT_GTL (O, I, T); + + output O; + + input I, T; + + wire ts; + + tri0 GTS = glbl.GTS; + + or O1 (ts, GTS, T); + bufif0 T1 (O, I, ts); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUFT_GTLP.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUFT_GTLP.v new file mode 100644 index 0000000..e63698f --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUFT_GTLP.v @@ -0,0 +1,39 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/OBUFT_GTLP.v,v 1.6 2007/05/23 21:43:42 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / 3-State Output Buffer with GTLP I/O Standard +// /___/ /\ Filename : OBUFT_GTLP.v +// \ \ / \ Timestamp : Thu Mar 25 16:43:03 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. +// 05/23/07 - Added wire declaration for internal signals. + +`timescale 1 ps / 1 ps + + +module OBUFT_GTLP (O, I, T); + + output O; + + input I, T; + + wire ts; + + tri0 GTS = glbl.GTS; + + or O1 (ts, GTS, T); + bufif0 T1 (O, I, ts); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUFT_GTLP_DCI.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUFT_GTLP_DCI.v new file mode 100644 index 0000000..234c2f2 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUFT_GTLP_DCI.v @@ -0,0 +1,39 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/OBUFT_GTLP_DCI.v,v 1.6 2007/05/23 21:43:42 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / 3-State Output Buffer with GTLP_DCI I/O Standard +// /___/ /\ Filename : OBUFT_GTLP_DCI.v +// \ \ / \ Timestamp : Thu Mar 25 16:43:03 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. +// 05/23/07 - Added wire declaration for internal signals. + +`timescale 1 ps / 1 ps + + +module OBUFT_GTLP_DCI (O, I, T); + + output O; + + input I, T; + + wire ts; + + tri0 GTS = glbl.GTS; + + or O1 (ts, GTS, T); + bufif0 T1 (O, I, ts); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUFT_GTL_DCI.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUFT_GTL_DCI.v new file mode 100644 index 0000000..3af8df7 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUFT_GTL_DCI.v @@ -0,0 +1,39 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/OBUFT_GTL_DCI.v,v 1.6 2007/05/23 21:43:42 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / 3-State Output Buffer with GTL_DCI I/O Standard +// /___/ /\ Filename : OBUFT_GTL_DCI.v +// \ \ / \ Timestamp : Thu Mar 25 16:43:03 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. +// 05/23/07 - Added wire declaration for internal signals. + +`timescale 1 ps / 1 ps + + +module OBUFT_GTL_DCI (O, I, T); + + output O; + + input I, T; + + wire ts; + + tri0 GTS = glbl.GTS; + + or O1 (ts, GTS, T); + bufif0 T1 (O, I, ts); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUFT_HSTL_I.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUFT_HSTL_I.v new file mode 100644 index 0000000..1e4c0dd --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUFT_HSTL_I.v @@ -0,0 +1,39 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/OBUFT_HSTL_I.v,v 1.6 2007/05/23 21:43:42 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / 3-State Output Buffer with HSTL_I I/O Standard +// /___/ /\ Filename : OBUFT_HSTL_I.v +// \ \ / \ Timestamp : Thu Mar 25 16:43:03 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. +// 05/23/07 - Added wire declaration for internal signals. + +`timescale 1 ps / 1 ps + + +module OBUFT_HSTL_I (O, I, T); + + output O; + + input I, T; + + wire ts; + + tri0 GTS = glbl.GTS; + + or O1 (ts, GTS, T); + bufif0 T1 (O, I, ts); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUFT_HSTL_II.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUFT_HSTL_II.v new file mode 100644 index 0000000..eafa777 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUFT_HSTL_II.v @@ -0,0 +1,39 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/OBUFT_HSTL_II.v,v 1.6 2007/05/23 21:43:42 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / 3-State Output Buffer with HSTL_II I/O Standard +// /___/ /\ Filename : OBUFT_HSTL_II.v +// \ \ / \ Timestamp : Thu Mar 25 16:43:03 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. +// 05/23/07 - Added wire declaration for internal signals. + +`timescale 1 ps / 1 ps + + +module OBUFT_HSTL_II (O, I, T); + + output O; + + input I, T; + + wire ts; + + tri0 GTS = glbl.GTS; + + or O1 (ts, GTS, T); + bufif0 T1 (O, I, ts); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUFT_HSTL_III.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUFT_HSTL_III.v new file mode 100644 index 0000000..9664027 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUFT_HSTL_III.v @@ -0,0 +1,39 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/OBUFT_HSTL_III.v,v 1.6 2007/05/23 21:43:42 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / 3-State Output Buffer with HSTL_III I/O Standard +// /___/ /\ Filename : OBUFT_HSTL_III.v +// \ \ / \ Timestamp : Thu Mar 25 16:43:03 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. +// 05/23/07 - Added wire declaration for internal signals. + +`timescale 1 ps / 1 ps + + +module OBUFT_HSTL_III (O, I, T); + + output O; + + input I, T; + + wire ts; + + tri0 GTS = glbl.GTS; + + or O1 (ts, GTS, T); + bufif0 T1 (O, I, ts); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUFT_HSTL_III_18.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUFT_HSTL_III_18.v new file mode 100644 index 0000000..408f842 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUFT_HSTL_III_18.v @@ -0,0 +1,39 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/OBUFT_HSTL_III_18.v,v 1.6 2007/05/23 21:43:42 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / 3-State Output Buffer with HSTL_III_18 I/O Standard +// /___/ /\ Filename : OBUFT_HSTL_III_18.v +// \ \ / \ Timestamp : Thu Mar 25 16:43:03 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. +// 05/23/07 - Added wire declaration for internal signals. + +`timescale 1 ps / 1 ps + + +module OBUFT_HSTL_III_18 (O, I, T); + + output O; + + input I, T; + + wire ts; + + tri0 GTS = glbl.GTS; + + or O1 (ts, GTS, T); + bufif0 T1 (O, I, ts); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUFT_HSTL_III_DCI.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUFT_HSTL_III_DCI.v new file mode 100644 index 0000000..bd6eab1 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUFT_HSTL_III_DCI.v @@ -0,0 +1,39 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/OBUFT_HSTL_III_DCI.v,v 1.6 2007/05/23 21:43:42 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / 3-State Output Buffer with HSTL_III_DCI I/O Standard +// /___/ /\ Filename : OBUFT_HSTL_III_DCI.v +// \ \ / \ Timestamp : Thu Mar 25 16:43:03 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. +// 05/23/07 - Added wire declaration for internal signals. + +`timescale 1 ps / 1 ps + + +module OBUFT_HSTL_III_DCI (O, I, T); + + output O; + + input I, T; + + wire ts; + + tri0 GTS = glbl.GTS; + + or O1 (ts, GTS, T); + bufif0 T1 (O, I, ts); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUFT_HSTL_III_DCI_18.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUFT_HSTL_III_DCI_18.v new file mode 100644 index 0000000..cbbe265 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUFT_HSTL_III_DCI_18.v @@ -0,0 +1,39 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/OBUFT_HSTL_III_DCI_18.v,v 1.6 2007/05/23 21:43:42 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / 3-State Output Buffer with HSTL_III_DCI_18 I/O Standard +// /___/ /\ Filename : OBUFT_HSTL_III_DCI_18.v +// \ \ / \ Timestamp : Thu Mar 25 16:43:03 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. +// 05/23/07 - Added wire declaration for internal signals. + +`timescale 1 ps / 1 ps + + +module OBUFT_HSTL_III_DCI_18 (O, I, T); + + output O; + + input I, T; + + wire ts; + + tri0 GTS = glbl.GTS; + + or O1 (ts, GTS, T); + bufif0 T1 (O, I, ts); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUFT_HSTL_II_18.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUFT_HSTL_II_18.v new file mode 100644 index 0000000..f5c0548 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUFT_HSTL_II_18.v @@ -0,0 +1,39 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/OBUFT_HSTL_II_18.v,v 1.6 2007/05/23 21:43:42 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / 3-State Output Buffer with HSTL_II_18 I/O Standard +// /___/ /\ Filename : OBUFT_HSTL_II_18.v +// \ \ / \ Timestamp : Thu Mar 25 16:43:03 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. +// 05/23/07 - Added wire declaration for internal signals. + +`timescale 1 ps / 1 ps + + +module OBUFT_HSTL_II_18 (O, I, T); + + output O; + + input I, T; + + wire ts; + + tri0 GTS = glbl.GTS; + + or O1 (ts, GTS, T); + bufif0 T1 (O, I, ts); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUFT_HSTL_II_DCI.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUFT_HSTL_II_DCI.v new file mode 100644 index 0000000..bc80273 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUFT_HSTL_II_DCI.v @@ -0,0 +1,39 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/OBUFT_HSTL_II_DCI.v,v 1.6 2007/05/23 21:43:42 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / 3-State Output Buffer with HSTL_II_DCI I/O Standard +// /___/ /\ Filename : OBUFT_HSTL_II_DCI.v +// \ \ / \ Timestamp : Thu Mar 25 16:43:04 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. +// 05/23/07 - Added wire declaration for internal signals. + +`timescale 1 ps / 1 ps + + +module OBUFT_HSTL_II_DCI (O, I, T); + + output O; + + input I, T; + + wire ts; + + tri0 GTS = glbl.GTS; + + or O1 (ts, GTS, T); + bufif0 T1 (O, I, ts); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUFT_HSTL_II_DCI_18.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUFT_HSTL_II_DCI_18.v new file mode 100644 index 0000000..8e2bda9 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUFT_HSTL_II_DCI_18.v @@ -0,0 +1,39 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/OBUFT_HSTL_II_DCI_18.v,v 1.6 2007/05/23 21:43:42 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / 3-State Output Buffer with HSTL_II_DCI_18 I/O Standard +// /___/ /\ Filename : OBUFT_HSTL_II_DCI_18.v +// \ \ / \ Timestamp : Thu Mar 25 16:43:04 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. +// 05/23/07 - Added wire declaration for internal signals. + +`timescale 1 ps / 1 ps + + +module OBUFT_HSTL_II_DCI_18 (O, I, T); + + output O; + + input I, T; + + wire ts; + + tri0 GTS = glbl.GTS; + + or O1 (ts, GTS, T); + bufif0 T1 (O, I, ts); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUFT_HSTL_IV.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUFT_HSTL_IV.v new file mode 100644 index 0000000..a0e539f --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUFT_HSTL_IV.v @@ -0,0 +1,39 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/OBUFT_HSTL_IV.v,v 1.6 2007/05/23 21:43:42 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / 3-State Output Buffer with HSTL_IV I/O Standard +// /___/ /\ Filename : OBUFT_HSTL_IV.v +// \ \ / \ Timestamp : Thu Mar 25 16:43:04 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. +// 05/23/07 - Added wire declaration for internal signals. + +`timescale 1 ps / 1 ps + + +module OBUFT_HSTL_IV (O, I, T); + + output O; + + input I, T; + + wire ts; + + tri0 GTS = glbl.GTS; + + or O1 (ts, GTS, T); + bufif0 T1 (O, I, ts); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUFT_HSTL_IV_18.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUFT_HSTL_IV_18.v new file mode 100644 index 0000000..e43022d --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUFT_HSTL_IV_18.v @@ -0,0 +1,39 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/OBUFT_HSTL_IV_18.v,v 1.6 2007/05/23 21:43:42 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / 3-State Output Buffer with HSTL_IV_18 I/O Standard +// /___/ /\ Filename : OBUFT_HSTL_IV_18.v +// \ \ / \ Timestamp : Thu Mar 25 16:43:04 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. +// 05/23/07 - Added wire declaration for internal signals. + +`timescale 1 ps / 1 ps + + +module OBUFT_HSTL_IV_18 (O, I, T); + + output O; + + input I, T; + + wire ts; + + tri0 GTS = glbl.GTS; + + or O1 (ts, GTS, T); + bufif0 T1 (O, I, ts); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUFT_HSTL_IV_DCI.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUFT_HSTL_IV_DCI.v new file mode 100644 index 0000000..8dbda43 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUFT_HSTL_IV_DCI.v @@ -0,0 +1,39 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/OBUFT_HSTL_IV_DCI.v,v 1.6 2007/05/23 21:43:42 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / 3-State Output Buffer with HSTL_IV_DCI I/O Standard +// /___/ /\ Filename : OBUFT_HSTL_IV_DCI.v +// \ \ / \ Timestamp : Thu Mar 25 16:43:04 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. +// 05/23/07 - Added wire declaration for internal signals. + +`timescale 1 ps / 1 ps + + +module OBUFT_HSTL_IV_DCI (O, I, T); + + output O; + + input I, T; + + wire ts; + + tri0 GTS = glbl.GTS; + + or O1 (ts, GTS, T); + bufif0 T1 (O, I, ts); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUFT_HSTL_IV_DCI_18.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUFT_HSTL_IV_DCI_18.v new file mode 100644 index 0000000..38af4b7 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUFT_HSTL_IV_DCI_18.v @@ -0,0 +1,39 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/OBUFT_HSTL_IV_DCI_18.v,v 1.6 2007/05/23 21:43:42 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / 3-State Output Buffer with HSTL_IV_DCI_18 I/O Standard +// /___/ /\ Filename : OBUFT_HSTL_IV_DCI_18.v +// \ \ / \ Timestamp : Thu Mar 25 16:43:04 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. +// 05/23/07 - Added wire declaration for internal signals. + +`timescale 1 ps / 1 ps + + +module OBUFT_HSTL_IV_DCI_18 (O, I, T); + + output O; + + input I, T; + + wire ts; + + tri0 GTS = glbl.GTS; + + or O1 (ts, GTS, T); + bufif0 T1 (O, I, ts); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUFT_HSTL_I_18.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUFT_HSTL_I_18.v new file mode 100644 index 0000000..5718b29 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUFT_HSTL_I_18.v @@ -0,0 +1,39 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/OBUFT_HSTL_I_18.v,v 1.6 2007/05/23 21:43:42 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / 3-State Output Buffer with HSTL_I_18 I/O Standard +// /___/ /\ Filename : OBUFT_HSTL_I_18.v +// \ \ / \ Timestamp : Thu Mar 25 16:43:04 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. +// 05/23/07 - Added wire declaration for internal signals. + +`timescale 1 ps / 1 ps + + +module OBUFT_HSTL_I_18 (O, I, T); + + output O; + + input I, T; + + wire ts; + + tri0 GTS = glbl.GTS; + + or O1 (ts, GTS, T); + bufif0 T1 (O, I, ts); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUFT_HSTL_I_DCI.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUFT_HSTL_I_DCI.v new file mode 100644 index 0000000..3dd1d1a --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUFT_HSTL_I_DCI.v @@ -0,0 +1,39 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/OBUFT_HSTL_I_DCI.v,v 1.6 2007/05/23 21:43:42 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / 3-State Output Buffer with HSTL_I_DCI I/O Standard +// /___/ /\ Filename : OBUFT_HSTL_I_DCI.v +// \ \ / \ Timestamp : Thu Mar 25 16:43:04 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. +// 05/23/07 - Added wire declaration for internal signals. + +`timescale 1 ps / 1 ps + + +module OBUFT_HSTL_I_DCI (O, I, T); + + output O; + + input I, T; + + wire ts; + + tri0 GTS = glbl.GTS; + + or O1 (ts, GTS, T); + bufif0 T1 (O, I, ts); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUFT_HSTL_I_DCI_18.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUFT_HSTL_I_DCI_18.v new file mode 100644 index 0000000..294c4d9 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUFT_HSTL_I_DCI_18.v @@ -0,0 +1,39 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/OBUFT_HSTL_I_DCI_18.v,v 1.6 2007/05/23 21:43:42 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / 3-State Output Buffer with HSTL_I_DCI_18 I/O Standard +// /___/ /\ Filename : OBUFT_HSTL_I_DCI_18.v +// \ \ / \ Timestamp : Thu Mar 25 16:43:04 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. +// 05/23/07 - Added wire declaration for internal signals. + +`timescale 1 ps / 1 ps + + +module OBUFT_HSTL_I_DCI_18 (O, I, T); + + output O; + + input I, T; + + wire ts; + + tri0 GTS = glbl.GTS; + + or O1 (ts, GTS, T); + bufif0 T1 (O, I, ts); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUFT_LVCMOS12.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUFT_LVCMOS12.v new file mode 100644 index 0000000..a0d0d57 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUFT_LVCMOS12.v @@ -0,0 +1,39 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/OBUFT_LVCMOS12.v,v 1.6 2007/05/23 21:43:42 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / 3-State Output Buffer with LVCMOS12 I/O Standard +// /___/ /\ Filename : OBUFT_LVCMOS12.v +// \ \ / \ Timestamp : Thu Mar 25 16:43:04 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. +// 05/23/07 - Added wire declaration for internal signals. + +`timescale 1 ps / 1 ps + + +module OBUFT_LVCMOS12 (O, I, T); + + output O; + + input I, T; + + wire ts; + + tri0 GTS = glbl.GTS; + + or O1 (ts, GTS, T); + bufif0 T1 (O, I, ts); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUFT_LVCMOS12_F_2.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUFT_LVCMOS12_F_2.v new file mode 100644 index 0000000..ec652b9 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUFT_LVCMOS12_F_2.v @@ -0,0 +1,39 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/OBUFT_LVCMOS12_F_2.v,v 1.6 2007/05/23 21:43:42 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / 3-State Output Buffer with LVCMOS12 I/O Standard Fast Slew 2 mA Drive +// /___/ /\ Filename : OBUFT_LVCMOS12_F_2.v +// \ \ / \ Timestamp : Thu Mar 25 16:43:05 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. +// 05/23/07 - Added wire declaration for internal signals. + +`timescale 1 ps / 1 ps + + +module OBUFT_LVCMOS12_F_2 (O, I, T); + + output O; + + input I, T; + + wire ts; + + tri0 GTS = glbl.GTS; + + or O1 (ts, GTS, T); + bufif0 T1 (O, I, ts); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUFT_LVCMOS12_F_4.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUFT_LVCMOS12_F_4.v new file mode 100644 index 0000000..9477ec6 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUFT_LVCMOS12_F_4.v @@ -0,0 +1,39 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/OBUFT_LVCMOS12_F_4.v,v 1.6 2007/05/23 21:43:42 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / 3-State Output Buffer with LVCMOS12 I/O Standard Fast Slew 4 mA Drive +// /___/ /\ Filename : OBUFT_LVCMOS12_F_4.v +// \ \ / \ Timestamp : Thu Mar 25 16:43:05 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. +// 05/23/07 - Added wire declaration for internal signals. + +`timescale 1 ps / 1 ps + + +module OBUFT_LVCMOS12_F_4 (O, I, T); + + output O; + + input I, T; + + wire ts; + + tri0 GTS = glbl.GTS; + + or O1 (ts, GTS, T); + bufif0 T1 (O, I, ts); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUFT_LVCMOS12_F_6.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUFT_LVCMOS12_F_6.v new file mode 100644 index 0000000..8b006d0 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUFT_LVCMOS12_F_6.v @@ -0,0 +1,39 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/OBUFT_LVCMOS12_F_6.v,v 1.6 2007/05/23 21:43:42 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / 3-State Output Buffer with LVCMOS12 I/O Standard Fast Slew 6 mA Drive +// /___/ /\ Filename : OBUFT_LVCMOS12_F_6.v +// \ \ / \ Timestamp : Thu Mar 25 16:43:05 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. +// 05/23/07 - Added wire declaration for internal signals. + +`timescale 1 ps / 1 ps + + +module OBUFT_LVCMOS12_F_6 (O, I, T); + + output O; + + input I, T; + + wire ts; + + tri0 GTS = glbl.GTS; + + or O1 (ts, GTS, T); + bufif0 T1 (O, I, ts); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUFT_LVCMOS12_F_8.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUFT_LVCMOS12_F_8.v new file mode 100644 index 0000000..eb3c44c --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUFT_LVCMOS12_F_8.v @@ -0,0 +1,39 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/OBUFT_LVCMOS12_F_8.v,v 1.6 2007/05/23 21:43:42 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / 3-State Output Buffer with LVCMOS12 I/O Standard Fast Slew 8 mA Drive +// /___/ /\ Filename : OBUFT_LVCMOS12_F_8.v +// \ \ / \ Timestamp : Thu Mar 25 16:43:05 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. +// 05/23/07 - Added wire declaration for internal signals. + +`timescale 1 ps / 1 ps + + +module OBUFT_LVCMOS12_F_8 (O, I, T); + + output O; + + input I, T; + + wire ts; + + tri0 GTS = glbl.GTS; + + or O1 (ts, GTS, T); + bufif0 T1 (O, I, ts); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUFT_LVCMOS12_S_2.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUFT_LVCMOS12_S_2.v new file mode 100644 index 0000000..1e27475 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUFT_LVCMOS12_S_2.v @@ -0,0 +1,39 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/OBUFT_LVCMOS12_S_2.v,v 1.6 2007/05/23 21:43:42 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / 3-State Output Buffer with LVCMOS12 I/O Standard Slow Slew 2 mA Drive +// /___/ /\ Filename : OBUFT_LVCMOS12_S_2.v +// \ \ / \ Timestamp : Thu Mar 25 16:43:05 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. +// 05/23/07 - Added wire declaration for internal signals. + +`timescale 1 ps / 1 ps + + +module OBUFT_LVCMOS12_S_2 (O, I, T); + + output O; + + input I, T; + + wire ts; + + tri0 GTS = glbl.GTS; + + or O1 (ts, GTS, T); + bufif0 T1 (O, I, ts); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUFT_LVCMOS12_S_4.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUFT_LVCMOS12_S_4.v new file mode 100644 index 0000000..877caea --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUFT_LVCMOS12_S_4.v @@ -0,0 +1,39 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/OBUFT_LVCMOS12_S_4.v,v 1.6 2007/05/23 21:43:42 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / 3-State Output Buffer with LVCMOS12 I/O Standard Slow Slew 4 mA Drive +// /___/ /\ Filename : OBUFT_LVCMOS12_S_4.v +// \ \ / \ Timestamp : Thu Mar 25 16:43:05 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. +// 05/23/07 - Added wire declaration for internal signals. + +`timescale 1 ps / 1 ps + + +module OBUFT_LVCMOS12_S_4 (O, I, T); + + output O; + + input I, T; + + wire ts; + + tri0 GTS = glbl.GTS; + + or O1 (ts, GTS, T); + bufif0 T1 (O, I, ts); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUFT_LVCMOS12_S_6.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUFT_LVCMOS12_S_6.v new file mode 100644 index 0000000..1b65f69 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUFT_LVCMOS12_S_6.v @@ -0,0 +1,39 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/OBUFT_LVCMOS12_S_6.v,v 1.6 2007/05/23 21:43:42 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / 3-State Output Buffer with LVCMOS12 I/O Standard Slow Slew 6 mA Drive +// /___/ /\ Filename : OBUFT_LVCMOS12_S_6.v +// \ \ / \ Timestamp : Thu Mar 25 16:43:05 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. +// 05/23/07 - Added wire declaration for internal signals. + +`timescale 1 ps / 1 ps + + +module OBUFT_LVCMOS12_S_6 (O, I, T); + + output O; + + input I, T; + + wire ts; + + tri0 GTS = glbl.GTS; + + or O1 (ts, GTS, T); + bufif0 T1 (O, I, ts); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUFT_LVCMOS12_S_8.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUFT_LVCMOS12_S_8.v new file mode 100644 index 0000000..b4daf0e --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUFT_LVCMOS12_S_8.v @@ -0,0 +1,39 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/OBUFT_LVCMOS12_S_8.v,v 1.6 2007/05/23 21:43:42 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / 3-State Output Buffer with LVCMOS12 I/O Standard Slow Slew 8 mA Drive +// /___/ /\ Filename : OBUFT_LVCMOS12_S_8.v +// \ \ / \ Timestamp : Thu Mar 25 16:43:05 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. +// 05/23/07 - Added wire declaration for internal signals. + +`timescale 1 ps / 1 ps + + +module OBUFT_LVCMOS12_S_8 (O, I, T); + + output O; + + input I, T; + + wire ts; + + tri0 GTS = glbl.GTS; + + or O1 (ts, GTS, T); + bufif0 T1 (O, I, ts); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUFT_LVCMOS15.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUFT_LVCMOS15.v new file mode 100644 index 0000000..3c25596 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUFT_LVCMOS15.v @@ -0,0 +1,39 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/OBUFT_LVCMOS15.v,v 1.6 2007/05/23 21:43:42 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / 3-State Output Buffer with LVCMOS15 I/O Standard +// /___/ /\ Filename : OBUFT_LVCMOS15.v +// \ \ / \ Timestamp : Thu Mar 25 16:43:05 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. +// 05/23/07 - Added wire declaration for internal signals. + +`timescale 1 ps / 1 ps + + +module OBUFT_LVCMOS15 (O, I, T); + + output O; + + input I, T; + + wire ts; + + tri0 GTS = glbl.GTS; + + or O1 (ts, GTS, T); + bufif0 T1 (O, I, ts); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUFT_LVCMOS15_F_12.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUFT_LVCMOS15_F_12.v new file mode 100644 index 0000000..c098867 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUFT_LVCMOS15_F_12.v @@ -0,0 +1,39 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/OBUFT_LVCMOS15_F_12.v,v 1.6 2007/05/23 21:43:42 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / 3-State Output Buffer with LVCMOS15 I/O Standard Fast Slew 12 mA Drive +// /___/ /\ Filename : OBUFT_LVCMOS15_F_12.v +// \ \ / \ Timestamp : Thu Mar 25 16:43:05 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. +// 05/23/07 - Added wire declaration for internal signals. + +`timescale 1 ps / 1 ps + + +module OBUFT_LVCMOS15_F_12 (O, I, T); + + output O; + + input I, T; + + wire ts; + + tri0 GTS = glbl.GTS; + + or O1 (ts, GTS, T); + bufif0 T1 (O, I, ts); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUFT_LVCMOS15_F_16.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUFT_LVCMOS15_F_16.v new file mode 100644 index 0000000..09ce122 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUFT_LVCMOS15_F_16.v @@ -0,0 +1,39 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/OBUFT_LVCMOS15_F_16.v,v 1.6 2007/05/23 21:43:42 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / 3-State Output Buffer with LVCMOS15 I/O Standard Fast Slew 16 mA Drive +// /___/ /\ Filename : OBUFT_LVCMOS15_F_16.v +// \ \ / \ Timestamp : Thu Mar 25 16:43:06 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. +// 05/23/07 - Added wire declaration for internal signals. + +`timescale 1 ps / 1 ps + + +module OBUFT_LVCMOS15_F_16 (O, I, T); + + output O; + + input I, T; + + wire ts; + + tri0 GTS = glbl.GTS; + + or O1 (ts, GTS, T); + bufif0 T1 (O, I, ts); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUFT_LVCMOS15_F_2.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUFT_LVCMOS15_F_2.v new file mode 100644 index 0000000..2363a14 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUFT_LVCMOS15_F_2.v @@ -0,0 +1,39 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/OBUFT_LVCMOS15_F_2.v,v 1.6 2007/05/23 21:43:42 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / 3-State Output Buffer with LVCMOS15 I/O Standard Fast Slew 2 mA Drive +// /___/ /\ Filename : OBUFT_LVCMOS15_F_2.v +// \ \ / \ Timestamp : Thu Mar 25 16:43:06 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. +// 05/23/07 - Added wire declaration for internal signals. + +`timescale 1 ps / 1 ps + + +module OBUFT_LVCMOS15_F_2 (O, I, T); + + output O; + + input I, T; + + wire ts; + + tri0 GTS = glbl.GTS; + + or O1 (ts, GTS, T); + bufif0 T1 (O, I, ts); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUFT_LVCMOS15_F_4.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUFT_LVCMOS15_F_4.v new file mode 100644 index 0000000..e51a426 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUFT_LVCMOS15_F_4.v @@ -0,0 +1,39 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/OBUFT_LVCMOS15_F_4.v,v 1.6 2007/05/23 21:43:42 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / 3-State Output Buffer with LVCMOS15 I/O Standard Fast Slew 4 mA Drive +// /___/ /\ Filename : OBUFT_LVCMOS15_F_4.v +// \ \ / \ Timestamp : Thu Mar 25 16:43:06 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. +// 05/23/07 - Added wire declaration for internal signals. + +`timescale 1 ps / 1 ps + + +module OBUFT_LVCMOS15_F_4 (O, I, T); + + output O; + + input I, T; + + wire ts; + + tri0 GTS = glbl.GTS; + + or O1 (ts, GTS, T); + bufif0 T1 (O, I, ts); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUFT_LVCMOS15_F_6.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUFT_LVCMOS15_F_6.v new file mode 100644 index 0000000..2f920ba --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUFT_LVCMOS15_F_6.v @@ -0,0 +1,39 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/OBUFT_LVCMOS15_F_6.v,v 1.6 2007/05/23 21:43:42 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / 3-State Output Buffer with LVCMOS15 I/O Standard Fast Slew 6 mA Drive +// /___/ /\ Filename : OBUFT_LVCMOS15_F_6.v +// \ \ / \ Timestamp : Thu Mar 25 16:43:06 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. +// 05/23/07 - Added wire declaration for internal signals. + +`timescale 1 ps / 1 ps + + +module OBUFT_LVCMOS15_F_6 (O, I, T); + + output O; + + input I, T; + + wire ts; + + tri0 GTS = glbl.GTS; + + or O1 (ts, GTS, T); + bufif0 T1 (O, I, ts); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUFT_LVCMOS15_F_8.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUFT_LVCMOS15_F_8.v new file mode 100644 index 0000000..85a6036 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUFT_LVCMOS15_F_8.v @@ -0,0 +1,39 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/OBUFT_LVCMOS15_F_8.v,v 1.6 2007/05/23 21:43:42 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / 3-State Output Buffer with LVCMOS15 I/O Standard Fast Slew 8 mA Drive +// /___/ /\ Filename : OBUFT_LVCMOS15_F_8.v +// \ \ / \ Timestamp : Thu Mar 25 16:43:06 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. +// 05/23/07 - Added wire declaration for internal signals. + +`timescale 1 ps / 1 ps + + +module OBUFT_LVCMOS15_F_8 (O, I, T); + + output O; + + input I, T; + + wire ts; + + tri0 GTS = glbl.GTS; + + or O1 (ts, GTS, T); + bufif0 T1 (O, I, ts); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUFT_LVCMOS15_S_12.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUFT_LVCMOS15_S_12.v new file mode 100644 index 0000000..c165dba --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUFT_LVCMOS15_S_12.v @@ -0,0 +1,39 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/OBUFT_LVCMOS15_S_12.v,v 1.6 2007/05/23 21:43:42 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / 3-State Output Buffer with LVCMOS15 I/O Standard Slow Slew 12 mA Drive +// /___/ /\ Filename : OBUFT_LVCMOS15_S_12.v +// \ \ / \ Timestamp : Thu Mar 25 16:43:06 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. +// 05/23/07 - Added wire declaration for internal signals. + +`timescale 1 ps / 1 ps + + +module OBUFT_LVCMOS15_S_12 (O, I, T); + + output O; + + input I, T; + + wire ts; + + tri0 GTS = glbl.GTS; + + or O1 (ts, GTS, T); + bufif0 T1 (O, I, ts); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUFT_LVCMOS15_S_16.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUFT_LVCMOS15_S_16.v new file mode 100644 index 0000000..75801f4 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUFT_LVCMOS15_S_16.v @@ -0,0 +1,39 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/OBUFT_LVCMOS15_S_16.v,v 1.6 2007/05/23 21:43:42 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / 3-State Output Buffer with LVCMOS15 I/O Standard Slow Slew 16 mA Drive +// /___/ /\ Filename : OBUFT_LVCMOS15_S_16.v +// \ \ / \ Timestamp : Thu Mar 25 16:43:06 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. +// 05/23/07 - Added wire declaration for internal signals. + +`timescale 1 ps / 1 ps + + +module OBUFT_LVCMOS15_S_16 (O, I, T); + + output O; + + input I, T; + + wire ts; + + tri0 GTS = glbl.GTS; + + or O1 (ts, GTS, T); + bufif0 T1 (O, I, ts); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUFT_LVCMOS15_S_2.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUFT_LVCMOS15_S_2.v new file mode 100644 index 0000000..2fa922a --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUFT_LVCMOS15_S_2.v @@ -0,0 +1,39 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/OBUFT_LVCMOS15_S_2.v,v 1.6 2007/05/23 21:43:42 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / 3-State Output Buffer with LVCMOS15 I/O Standard Slow Slew 2 mA Drive +// /___/ /\ Filename : OBUFT_LVCMOS15_S_2.v +// \ \ / \ Timestamp : Thu Mar 25 16:43:06 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. +// 05/23/07 - Added wire declaration for internal signals. + +`timescale 1 ps / 1 ps + + +module OBUFT_LVCMOS15_S_2 (O, I, T); + + output O; + + input I, T; + + wire ts; + + tri0 GTS = glbl.GTS; + + or O1 (ts, GTS, T); + bufif0 T1 (O, I, ts); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUFT_LVCMOS15_S_4.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUFT_LVCMOS15_S_4.v new file mode 100644 index 0000000..e3e2419 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUFT_LVCMOS15_S_4.v @@ -0,0 +1,39 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/OBUFT_LVCMOS15_S_4.v,v 1.6 2007/05/23 21:43:42 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / 3-State Output Buffer with LVCMOS15 I/O Standard Slow Slew 4 mA Drive +// /___/ /\ Filename : OBUFT_LVCMOS15_S_4.v +// \ \ / \ Timestamp : Thu Mar 25 16:43:06 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. +// 05/23/07 - Added wire declaration for internal signals. + +`timescale 1 ps / 1 ps + + +module OBUFT_LVCMOS15_S_4 (O, I, T); + + output O; + + input I, T; + + wire ts; + + tri0 GTS = glbl.GTS; + + or O1 (ts, GTS, T); + bufif0 T1 (O, I, ts); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUFT_LVCMOS15_S_6.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUFT_LVCMOS15_S_6.v new file mode 100644 index 0000000..7fce9f3 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUFT_LVCMOS15_S_6.v @@ -0,0 +1,39 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/OBUFT_LVCMOS15_S_6.v,v 1.6 2007/05/23 21:43:42 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / 3-State Output Buffer with LVCMOS15 I/O Standard Slow Slew 6 mA Drive +// /___/ /\ Filename : OBUFT_LVCMOS15_S_6.v +// \ \ / \ Timestamp : Thu Mar 25 16:43:07 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. +// 05/23/07 - Added wire declaration for internal signals. + +`timescale 1 ps / 1 ps + + +module OBUFT_LVCMOS15_S_6 (O, I, T); + + output O; + + input I, T; + + wire ts; + + tri0 GTS = glbl.GTS; + + or O1 (ts, GTS, T); + bufif0 T1 (O, I, ts); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUFT_LVCMOS15_S_8.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUFT_LVCMOS15_S_8.v new file mode 100644 index 0000000..5b36b34 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUFT_LVCMOS15_S_8.v @@ -0,0 +1,39 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/OBUFT_LVCMOS15_S_8.v,v 1.6 2007/05/23 21:43:42 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / 3-State Output Buffer with LVCMOS15 I/O Standard Slow Slew 8 mA Drive +// /___/ /\ Filename : OBUFT_LVCMOS15_S_8.v +// \ \ / \ Timestamp : Thu Mar 25 16:43:07 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. +// 05/23/07 - Added wire declaration for internal signals. + +`timescale 1 ps / 1 ps + + +module OBUFT_LVCMOS15_S_8 (O, I, T); + + output O; + + input I, T; + + wire ts; + + tri0 GTS = glbl.GTS; + + or O1 (ts, GTS, T); + bufif0 T1 (O, I, ts); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUFT_LVCMOS18.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUFT_LVCMOS18.v new file mode 100644 index 0000000..8dad409 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUFT_LVCMOS18.v @@ -0,0 +1,39 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/OBUFT_LVCMOS18.v,v 1.6 2007/05/23 21:43:43 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / 3-State Output Buffer with LVCMOS18 I/O Standard +// /___/ /\ Filename : OBUFT_LVCMOS18.v +// \ \ / \ Timestamp : Thu Mar 25 16:43:07 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. +// 05/23/07 - Added wire declaration for internal signals. + +`timescale 1 ps / 1 ps + + +module OBUFT_LVCMOS18 (O, I, T); + + output O; + + input I, T; + + wire ts; + + tri0 GTS = glbl.GTS; + + or O1 (ts, GTS, T); + bufif0 T1 (O, I, ts); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUFT_LVCMOS18_F_12.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUFT_LVCMOS18_F_12.v new file mode 100644 index 0000000..4214579 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUFT_LVCMOS18_F_12.v @@ -0,0 +1,39 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/OBUFT_LVCMOS18_F_12.v,v 1.6 2007/05/23 21:43:42 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / 3-State Output Buffer with LVCMOS18 I/O Standard Fast Slew 12 mA Drive +// /___/ /\ Filename : OBUFT_LVCMOS18_F_12.v +// \ \ / \ Timestamp : Thu Mar 25 16:43:07 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. +// 05/23/07 - Added wire declaration for internal signals. + +`timescale 1 ps / 1 ps + + +module OBUFT_LVCMOS18_F_12 (O, I, T); + + output O; + + input I, T; + + wire ts; + + tri0 GTS = glbl.GTS; + + or O1 (ts, GTS, T); + bufif0 T1 (O, I, ts); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUFT_LVCMOS18_F_16.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUFT_LVCMOS18_F_16.v new file mode 100644 index 0000000..d86d95e --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUFT_LVCMOS18_F_16.v @@ -0,0 +1,39 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/OBUFT_LVCMOS18_F_16.v,v 1.6 2007/05/23 21:43:42 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / 3-State Output Buffer with LVCMOS18 I/O Standard Fast Slew 16 mA Drive +// /___/ /\ Filename : OBUFT_LVCMOS18_F_16.v +// \ \ / \ Timestamp : Thu Mar 25 16:43:07 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. +// 05/23/07 - Added wire declaration for internal signals. + +`timescale 1 ps / 1 ps + + +module OBUFT_LVCMOS18_F_16 (O, I, T); + + output O; + + input I, T; + + wire ts; + + tri0 GTS = glbl.GTS; + + or O1 (ts, GTS, T); + bufif0 T1 (O, I, ts); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUFT_LVCMOS18_F_2.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUFT_LVCMOS18_F_2.v new file mode 100644 index 0000000..60a800f --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUFT_LVCMOS18_F_2.v @@ -0,0 +1,39 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/OBUFT_LVCMOS18_F_2.v,v 1.6 2007/05/23 21:43:42 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / 3-State Output Buffer with LVCMOS18 I/O Standard Fast Slew 2 mA Drive +// /___/ /\ Filename : OBUFT_LVCMOS18_F_2.v +// \ \ / \ Timestamp : Thu Mar 25 16:43:07 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. +// 05/23/07 - Added wire declaration for internal signals. + +`timescale 1 ps / 1 ps + + +module OBUFT_LVCMOS18_F_2 (O, I, T); + + output O; + + input I, T; + + wire ts; + + tri0 GTS = glbl.GTS; + + or O1 (ts, GTS, T); + bufif0 T1 (O, I, ts); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUFT_LVCMOS18_F_4.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUFT_LVCMOS18_F_4.v new file mode 100644 index 0000000..24fd214 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUFT_LVCMOS18_F_4.v @@ -0,0 +1,39 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/OBUFT_LVCMOS18_F_4.v,v 1.6 2007/05/23 21:43:42 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / 3-State Output Buffer with LVCMOS18 I/O Standard Fast Slew 4 mA Drive +// /___/ /\ Filename : OBUFT_LVCMOS18_F_4.v +// \ \ / \ Timestamp : Thu Mar 25 16:43:07 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. +// 05/23/07 - Added wire declaration for internal signals. + +`timescale 1 ps / 1 ps + + +module OBUFT_LVCMOS18_F_4 (O, I, T); + + output O; + + input I, T; + + wire ts; + + tri0 GTS = glbl.GTS; + + or O1 (ts, GTS, T); + bufif0 T1 (O, I, ts); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUFT_LVCMOS18_F_6.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUFT_LVCMOS18_F_6.v new file mode 100644 index 0000000..9ddaed9 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUFT_LVCMOS18_F_6.v @@ -0,0 +1,39 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/OBUFT_LVCMOS18_F_6.v,v 1.6 2007/05/23 21:43:42 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / 3-State Output Buffer with LVCMOS18 I/O Standard Fast Slew 6 mA Drive +// /___/ /\ Filename : OBUFT_LVCMOS18_F_6.v +// \ \ / \ Timestamp : Thu Mar 25 16:43:08 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. +// 05/23/07 - Added wire declaration for internal signals. + +`timescale 1 ps / 1 ps + + +module OBUFT_LVCMOS18_F_6 (O, I, T); + + output O; + + input I, T; + + wire ts; + + tri0 GTS = glbl.GTS; + + or O1 (ts, GTS, T); + bufif0 T1 (O, I, ts); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUFT_LVCMOS18_F_8.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUFT_LVCMOS18_F_8.v new file mode 100644 index 0000000..47dedac --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUFT_LVCMOS18_F_8.v @@ -0,0 +1,39 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/OBUFT_LVCMOS18_F_8.v,v 1.6 2007/05/23 21:43:42 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / 3-State Output Buffer with LVCMOS18 I/O Standard Fast Slew 8 mA Drive +// /___/ /\ Filename : OBUFT_LVCMOS18_F_8.v +// \ \ / \ Timestamp : Thu Mar 25 16:43:08 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. +// 05/23/07 - Added wire declaration for internal signals. + +`timescale 1 ps / 1 ps + + +module OBUFT_LVCMOS18_F_8 (O, I, T); + + output O; + + input I, T; + + wire ts; + + tri0 GTS = glbl.GTS; + + or O1 (ts, GTS, T); + bufif0 T1 (O, I, ts); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUFT_LVCMOS18_S_12.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUFT_LVCMOS18_S_12.v new file mode 100644 index 0000000..23cd4a0 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUFT_LVCMOS18_S_12.v @@ -0,0 +1,39 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/OBUFT_LVCMOS18_S_12.v,v 1.6 2007/05/23 21:43:42 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / 3-State Output Buffer with LVCMOS18 I/O Standard Slow Slew 12 mA Drive +// /___/ /\ Filename : OBUFT_LVCMOS18_S_12.v +// \ \ / \ Timestamp : Thu Mar 25 16:43:08 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. +// 05/23/07 - Added wire declaration for internal signals. + +`timescale 1 ps / 1 ps + + +module OBUFT_LVCMOS18_S_12 (O, I, T); + + output O; + + input I, T; + + wire ts; + + tri0 GTS = glbl.GTS; + + or O1 (ts, GTS, T); + bufif0 T1 (O, I, ts); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUFT_LVCMOS18_S_16.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUFT_LVCMOS18_S_16.v new file mode 100644 index 0000000..7b62b97 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUFT_LVCMOS18_S_16.v @@ -0,0 +1,39 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/OBUFT_LVCMOS18_S_16.v,v 1.6 2007/05/23 21:43:42 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / 3-State Output Buffer with LVCMOS18 I/O Standard Slow Slew 16 mA Drive +// /___/ /\ Filename : OBUFT_LVCMOS18_S_16.v +// \ \ / \ Timestamp : Thu Mar 25 16:43:08 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. +// 05/23/07 - Added wire declaration for internal signals. + +`timescale 1 ps / 1 ps + + +module OBUFT_LVCMOS18_S_16 (O, I, T); + + output O; + + input I, T; + + wire ts; + + tri0 GTS = glbl.GTS; + + or O1 (ts, GTS, T); + bufif0 T1 (O, I, ts); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUFT_LVCMOS18_S_2.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUFT_LVCMOS18_S_2.v new file mode 100644 index 0000000..8ac09d0 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUFT_LVCMOS18_S_2.v @@ -0,0 +1,39 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/OBUFT_LVCMOS18_S_2.v,v 1.6 2007/05/23 21:43:42 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / 3-State Output Buffer with LVCMOS18 I/O Standard Slow Slew 2 mA Drive +// /___/ /\ Filename : OBUFT_LVCMOS18_S_2.v +// \ \ / \ Timestamp : Thu Mar 25 16:43:08 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. +// 05/23/07 - Added wire declaration for internal signals. + +`timescale 1 ps / 1 ps + + +module OBUFT_LVCMOS18_S_2 (O, I, T); + + output O; + + input I, T; + + wire ts; + + tri0 GTS = glbl.GTS; + + or O1 (ts, GTS, T); + bufif0 T1 (O, I, ts); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUFT_LVCMOS18_S_4.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUFT_LVCMOS18_S_4.v new file mode 100644 index 0000000..eff2877 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUFT_LVCMOS18_S_4.v @@ -0,0 +1,39 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/OBUFT_LVCMOS18_S_4.v,v 1.6 2007/05/23 21:43:42 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / 3-State Output Buffer with LVCMOS18 I/O Standard Slow Slew 4 mA Drive +// /___/ /\ Filename : OBUFT_LVCMOS18_S_4.v +// \ \ / \ Timestamp : Thu Mar 25 16:43:08 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. +// 05/23/07 - Added wire declaration for internal signals. + +`timescale 1 ps / 1 ps + + +module OBUFT_LVCMOS18_S_4 (O, I, T); + + output O; + + input I, T; + + wire ts; + + tri0 GTS = glbl.GTS; + + or O1 (ts, GTS, T); + bufif0 T1 (O, I, ts); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUFT_LVCMOS18_S_6.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUFT_LVCMOS18_S_6.v new file mode 100644 index 0000000..f3c43fc --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUFT_LVCMOS18_S_6.v @@ -0,0 +1,39 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/OBUFT_LVCMOS18_S_6.v,v 1.6 2007/05/23 21:43:42 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / 3-State Output Buffer with LVCMOS18 I/O Standard Slow Slew 6 mA Drive +// /___/ /\ Filename : OBUFT_LVCMOS18_S_6.v +// \ \ / \ Timestamp : Thu Mar 25 16:43:08 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. +// 05/23/07 - Added wire declaration for internal signals. + +`timescale 1 ps / 1 ps + + +module OBUFT_LVCMOS18_S_6 (O, I, T); + + output O; + + input I, T; + + wire ts; + + tri0 GTS = glbl.GTS; + + or O1 (ts, GTS, T); + bufif0 T1 (O, I, ts); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUFT_LVCMOS18_S_8.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUFT_LVCMOS18_S_8.v new file mode 100644 index 0000000..e80acaf --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUFT_LVCMOS18_S_8.v @@ -0,0 +1,39 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/OBUFT_LVCMOS18_S_8.v,v 1.6 2007/05/23 21:43:42 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / 3-State Output Buffer with LVCMOS18 I/O Standard Slow Slew 8 mA Drive +// /___/ /\ Filename : OBUFT_LVCMOS18_S_8.v +// \ \ / \ Timestamp : Thu Mar 25 16:43:08 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. +// 05/23/07 - Added wire declaration for internal signals. + +`timescale 1 ps / 1 ps + + +module OBUFT_LVCMOS18_S_8 (O, I, T); + + output O; + + input I, T; + + wire ts; + + tri0 GTS = glbl.GTS; + + or O1 (ts, GTS, T); + bufif0 T1 (O, I, ts); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUFT_LVCMOS2.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUFT_LVCMOS2.v new file mode 100644 index 0000000..9e9160b --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUFT_LVCMOS2.v @@ -0,0 +1,39 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/OBUFT_LVCMOS2.v,v 1.6 2007/05/23 21:43:43 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / 3-State Output Buffer with LVCMOS2 I/O Standard +// /___/ /\ Filename : OBUFT_LVCMOS2.v +// \ \ / \ Timestamp : Thu Mar 25 16:43:08 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. +// 05/23/07 - Added wire declaration for internal signals. + +`timescale 1 ps / 1 ps + + +module OBUFT_LVCMOS2 (O, I, T); + + output O; + + input I, T; + + wire ts; + + tri0 GTS = glbl.GTS; + + or O1 (ts, GTS, T); + bufif0 T1 (O, I, ts); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUFT_LVCMOS25.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUFT_LVCMOS25.v new file mode 100644 index 0000000..72186b9 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUFT_LVCMOS25.v @@ -0,0 +1,39 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/OBUFT_LVCMOS25.v,v 1.6 2007/05/23 21:43:43 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / 3-State Output Buffer with LVCMOS25 I/O Standard +// /___/ /\ Filename : OBUFT_LVCMOS25.v +// \ \ / \ Timestamp : Thu Mar 25 16:43:08 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. +// 05/23/07 - Added wire declaration for internal signals. + +`timescale 1 ps / 1 ps + + +module OBUFT_LVCMOS25 (O, I, T); + + output O; + + input I, T; + + wire ts; + + tri0 GTS = glbl.GTS; + + or O1 (ts, GTS, T); + bufif0 T1 (O, I, ts); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUFT_LVCMOS25_F_12.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUFT_LVCMOS25_F_12.v new file mode 100644 index 0000000..fb8d903 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUFT_LVCMOS25_F_12.v @@ -0,0 +1,39 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/OBUFT_LVCMOS25_F_12.v,v 1.6 2007/05/23 21:43:43 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / 3-State Output Buffer with LVCMOS25 I/O Standard Fast Slew 12 mA Drive +// /___/ /\ Filename : OBUFT_LVCMOS25_F_12.v +// \ \ / \ Timestamp : Thu Mar 25 16:43:09 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. +// 05/23/07 - Added wire declaration for internal signals. + +`timescale 1 ps / 1 ps + + +module OBUFT_LVCMOS25_F_12 (O, I, T); + + output O; + + input I, T; + + wire ts; + + tri0 GTS = glbl.GTS; + + or O1 (ts, GTS, T); + bufif0 T1 (O, I, ts); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUFT_LVCMOS25_F_16.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUFT_LVCMOS25_F_16.v new file mode 100644 index 0000000..accee93 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUFT_LVCMOS25_F_16.v @@ -0,0 +1,39 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/OBUFT_LVCMOS25_F_16.v,v 1.6 2007/05/23 21:43:43 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / 3-State Output Buffer with LVCMOS25 I/O Standard Fast Slew 16 mA Drive +// /___/ /\ Filename : OBUFT_LVCMOS25_F_16.v +// \ \ / \ Timestamp : Thu Mar 25 16:43:09 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. +// 05/23/07 - Added wire declaration for internal signals. + +`timescale 1 ps / 1 ps + + +module OBUFT_LVCMOS25_F_16 (O, I, T); + + output O; + + input I, T; + + wire ts; + + tri0 GTS = glbl.GTS; + + or O1 (ts, GTS, T); + bufif0 T1 (O, I, ts); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUFT_LVCMOS25_F_2.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUFT_LVCMOS25_F_2.v new file mode 100644 index 0000000..f7e0dbe --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUFT_LVCMOS25_F_2.v @@ -0,0 +1,39 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/OBUFT_LVCMOS25_F_2.v,v 1.6 2007/05/23 21:43:43 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / 3-State Output Buffer with LVCMOS25 I/O Standard Fast Slew 2 mA Drive +// /___/ /\ Filename : OBUFT_LVCMOS25_F_2.v +// \ \ / \ Timestamp : Thu Mar 25 16:43:09 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. +// 05/23/07 - Added wire declaration for internal signals. + +`timescale 1 ps / 1 ps + + +module OBUFT_LVCMOS25_F_2 (O, I, T); + + output O; + + input I, T; + + wire ts; + + tri0 GTS = glbl.GTS; + + or O1 (ts, GTS, T); + bufif0 T1 (O, I, ts); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUFT_LVCMOS25_F_24.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUFT_LVCMOS25_F_24.v new file mode 100644 index 0000000..741469d --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUFT_LVCMOS25_F_24.v @@ -0,0 +1,39 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/OBUFT_LVCMOS25_F_24.v,v 1.6 2007/05/23 21:43:43 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / 3-State Output Buffer with LVCMOS25 I/O Standard Fast Slew 24 mA Drive +// /___/ /\ Filename : OBUFT_LVCMOS25_F_24.v +// \ \ / \ Timestamp : Thu Mar 25 16:43:09 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. +// 05/23/07 - Added wire declaration for internal signals. + +`timescale 1 ps / 1 ps + + +module OBUFT_LVCMOS25_F_24 (O, I, T); + + output O; + + input I, T; + + wire ts; + + tri0 GTS = glbl.GTS; + + or O1 (ts, GTS, T); + bufif0 T1 (O, I, ts); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUFT_LVCMOS25_F_4.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUFT_LVCMOS25_F_4.v new file mode 100644 index 0000000..7109089 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUFT_LVCMOS25_F_4.v @@ -0,0 +1,39 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/OBUFT_LVCMOS25_F_4.v,v 1.6 2007/05/23 21:43:43 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / 3-State Output Buffer with LVCMOS25 I/O Standard Fast Slew 4 mA Drive +// /___/ /\ Filename : OBUFT_LVCMOS25_F_4.v +// \ \ / \ Timestamp : Thu Mar 25 16:43:09 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. +// 05/23/07 - Added wire declaration for internal signals. + +`timescale 1 ps / 1 ps + + +module OBUFT_LVCMOS25_F_4 (O, I, T); + + output O; + + input I, T; + + wire ts; + + tri0 GTS = glbl.GTS; + + or O1 (ts, GTS, T); + bufif0 T1 (O, I, ts); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUFT_LVCMOS25_F_6.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUFT_LVCMOS25_F_6.v new file mode 100644 index 0000000..a4e85b3 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUFT_LVCMOS25_F_6.v @@ -0,0 +1,39 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/OBUFT_LVCMOS25_F_6.v,v 1.6 2007/05/23 21:43:43 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / 3-State Output Buffer with LVCMOS25 I/O Standard Fast Slew 6 mA Drive +// /___/ /\ Filename : OBUFT_LVCMOS25_F_6.v +// \ \ / \ Timestamp : Thu Mar 25 16:43:09 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. +// 05/23/07 - Added wire declaration for internal signals. + +`timescale 1 ps / 1 ps + + +module OBUFT_LVCMOS25_F_6 (O, I, T); + + output O; + + input I, T; + + wire ts; + + tri0 GTS = glbl.GTS; + + or O1 (ts, GTS, T); + bufif0 T1 (O, I, ts); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUFT_LVCMOS25_F_8.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUFT_LVCMOS25_F_8.v new file mode 100644 index 0000000..624c5b0 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUFT_LVCMOS25_F_8.v @@ -0,0 +1,39 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/OBUFT_LVCMOS25_F_8.v,v 1.6 2007/05/23 21:43:43 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / 3-State Output Buffer with LVCMOS25 I/O Standard Fast Slew 8 mA Drive +// /___/ /\ Filename : OBUFT_LVCMOS25_F_8.v +// \ \ / \ Timestamp : Thu Mar 25 16:43:09 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. +// 05/23/07 - Added wire declaration for internal signals. + +`timescale 1 ps / 1 ps + + +module OBUFT_LVCMOS25_F_8 (O, I, T); + + output O; + + input I, T; + + wire ts; + + tri0 GTS = glbl.GTS; + + or O1 (ts, GTS, T); + bufif0 T1 (O, I, ts); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUFT_LVCMOS25_S_12.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUFT_LVCMOS25_S_12.v new file mode 100644 index 0000000..d1c3722 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUFT_LVCMOS25_S_12.v @@ -0,0 +1,39 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/OBUFT_LVCMOS25_S_12.v,v 1.6 2007/05/23 21:43:43 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / 3-State Output Buffer with LVCMOS25 I/O Standard Slow Slew 12 mA Drive +// /___/ /\ Filename : OBUFT_LVCMOS25_S_12.v +// \ \ / \ Timestamp : Thu Mar 25 16:43:09 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. +// 05/23/07 - Added wire declaration for internal signals. + +`timescale 1 ps / 1 ps + + +module OBUFT_LVCMOS25_S_12 (O, I, T); + + output O; + + input I, T; + + wire ts; + + tri0 GTS = glbl.GTS; + + or O1 (ts, GTS, T); + bufif0 T1 (O, I, ts); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUFT_LVCMOS25_S_16.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUFT_LVCMOS25_S_16.v new file mode 100644 index 0000000..e2256b6 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUFT_LVCMOS25_S_16.v @@ -0,0 +1,39 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/OBUFT_LVCMOS25_S_16.v,v 1.6 2007/05/23 21:43:43 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / 3-State Output Buffer with LVCMOS25 I/O Standard Slow Slew 16 mA Drive +// /___/ /\ Filename : OBUFT_LVCMOS25_S_16.v +// \ \ / \ Timestamp : Thu Mar 25 16:43:09 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. +// 05/23/07 - Added wire declaration for internal signals. + +`timescale 1 ps / 1 ps + + +module OBUFT_LVCMOS25_S_16 (O, I, T); + + output O; + + input I, T; + + wire ts; + + tri0 GTS = glbl.GTS; + + or O1 (ts, GTS, T); + bufif0 T1 (O, I, ts); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUFT_LVCMOS25_S_2.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUFT_LVCMOS25_S_2.v new file mode 100644 index 0000000..fada75c --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUFT_LVCMOS25_S_2.v @@ -0,0 +1,39 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/OBUFT_LVCMOS25_S_2.v,v 1.6 2007/05/23 21:43:43 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / 3-State Output Buffer with LVCMOS25 I/O Standard Slow Slew 2 mA Drive +// /___/ /\ Filename : OBUFT_LVCMOS25_S_2.v +// \ \ / \ Timestamp : Thu Mar 25 16:43:09 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. +// 05/23/07 - Added wire declaration for internal signals. + +`timescale 1 ps / 1 ps + + +module OBUFT_LVCMOS25_S_2 (O, I, T); + + output O; + + input I, T; + + wire ts; + + tri0 GTS = glbl.GTS; + + or O1 (ts, GTS, T); + bufif0 T1 (O, I, ts); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUFT_LVCMOS25_S_24.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUFT_LVCMOS25_S_24.v new file mode 100644 index 0000000..4da0190 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUFT_LVCMOS25_S_24.v @@ -0,0 +1,39 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/OBUFT_LVCMOS25_S_24.v,v 1.6 2007/05/23 21:43:43 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / 3-State Output Buffer with LVCMOS25 I/O Standard Slow Slew 24 mA Drive +// /___/ /\ Filename : OBUFT_LVCMOS25_S_24.v +// \ \ / \ Timestamp : Thu Mar 25 16:43:10 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. +// 05/23/07 - Added wire declaration for internal signals. + +`timescale 1 ps / 1 ps + + +module OBUFT_LVCMOS25_S_24 (O, I, T); + + output O; + + input I, T; + + wire ts; + + tri0 GTS = glbl.GTS; + + or O1 (ts, GTS, T); + bufif0 T1 (O, I, ts); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUFT_LVCMOS25_S_4.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUFT_LVCMOS25_S_4.v new file mode 100644 index 0000000..7410c03 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUFT_LVCMOS25_S_4.v @@ -0,0 +1,39 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/OBUFT_LVCMOS25_S_4.v,v 1.6 2007/05/23 21:43:43 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / 3-State Output Buffer with LVCMOS25 I/O Standard Slow Slew 4 mA Drive +// /___/ /\ Filename : OBUFT_LVCMOS25_S_4.v +// \ \ / \ Timestamp : Thu Mar 25 16:43:10 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. +// 05/23/07 - Added wire declaration for internal signals. + +`timescale 1 ps / 1 ps + + +module OBUFT_LVCMOS25_S_4 (O, I, T); + + output O; + + input I, T; + + wire ts; + + tri0 GTS = glbl.GTS; + + or O1 (ts, GTS, T); + bufif0 T1 (O, I, ts); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUFT_LVCMOS25_S_6.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUFT_LVCMOS25_S_6.v new file mode 100644 index 0000000..ce0089b --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUFT_LVCMOS25_S_6.v @@ -0,0 +1,39 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/OBUFT_LVCMOS25_S_6.v,v 1.6 2007/05/23 21:43:43 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / 3-State Output Buffer with LVCMOS25 I/O Standard Slow Slew 6 mA Drive +// /___/ /\ Filename : OBUFT_LVCMOS25_S_6.v +// \ \ / \ Timestamp : Thu Mar 25 16:43:10 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. +// 05/23/07 - Added wire declaration for internal signals. + +`timescale 1 ps / 1 ps + + +module OBUFT_LVCMOS25_S_6 (O, I, T); + + output O; + + input I, T; + + wire ts; + + tri0 GTS = glbl.GTS; + + or O1 (ts, GTS, T); + bufif0 T1 (O, I, ts); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUFT_LVCMOS25_S_8.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUFT_LVCMOS25_S_8.v new file mode 100644 index 0000000..91ed392 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUFT_LVCMOS25_S_8.v @@ -0,0 +1,39 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/OBUFT_LVCMOS25_S_8.v,v 1.6 2007/05/23 21:43:43 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / 3-State Output Buffer with LVCMOS25 I/O Standard Slow Slew 8 mA Drive +// /___/ /\ Filename : OBUFT_LVCMOS25_S_8.v +// \ \ / \ Timestamp : Thu Mar 25 16:43:10 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. +// 05/23/07 - Added wire declaration for internal signals. + +`timescale 1 ps / 1 ps + + +module OBUFT_LVCMOS25_S_8 (O, I, T); + + output O; + + input I, T; + + wire ts; + + tri0 GTS = glbl.GTS; + + or O1 (ts, GTS, T); + bufif0 T1 (O, I, ts); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUFT_LVCMOS33.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUFT_LVCMOS33.v new file mode 100644 index 0000000..33bdc2e --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUFT_LVCMOS33.v @@ -0,0 +1,39 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/OBUFT_LVCMOS33.v,v 1.6 2007/05/23 21:43:43 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / 3-State Output Buffer with LVCMOS33 I/O Standard +// /___/ /\ Filename : OBUFT_LVCMOS33.v +// \ \ / \ Timestamp : Thu Mar 25 16:43:10 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. +// 05/23/07 - Added wire declaration for internal signals. + +`timescale 1 ps / 1 ps + + +module OBUFT_LVCMOS33 (O, I, T); + + output O; + + input I, T; + + wire ts; + + tri0 GTS = glbl.GTS; + + or O1 (ts, GTS, T); + bufif0 T1 (O, I, ts); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUFT_LVCMOS33_F_12.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUFT_LVCMOS33_F_12.v new file mode 100644 index 0000000..b72fc7b --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUFT_LVCMOS33_F_12.v @@ -0,0 +1,39 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/OBUFT_LVCMOS33_F_12.v,v 1.6 2007/05/23 21:43:43 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / 3-State Output Buffer with LVCMOS33 I/O Standard Fast Slew 12 mA Drive +// /___/ /\ Filename : OBUFT_LVCMOS33_F_12.v +// \ \ / \ Timestamp : Thu Mar 25 16:43:10 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. +// 05/23/07 - Added wire declaration for internal signals. + +`timescale 1 ps / 1 ps + + +module OBUFT_LVCMOS33_F_12 (O, I, T); + + output O; + + input I, T; + + wire ts; + + tri0 GTS = glbl.GTS; + + or O1 (ts, GTS, T); + bufif0 T1 (O, I, ts); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUFT_LVCMOS33_F_16.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUFT_LVCMOS33_F_16.v new file mode 100644 index 0000000..bfe5198 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUFT_LVCMOS33_F_16.v @@ -0,0 +1,39 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/OBUFT_LVCMOS33_F_16.v,v 1.6 2007/05/23 21:43:43 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / 3-State Output Buffer with LVCMOS33 I/O Standard Fast Slew 16 mA Drive +// /___/ /\ Filename : OBUFT_LVCMOS33_F_16.v +// \ \ / \ Timestamp : Thu Mar 25 16:43:10 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. +// 05/23/07 - Added wire declaration for internal signals. + +`timescale 1 ps / 1 ps + + +module OBUFT_LVCMOS33_F_16 (O, I, T); + + output O; + + input I, T; + + wire ts; + + tri0 GTS = glbl.GTS; + + or O1 (ts, GTS, T); + bufif0 T1 (O, I, ts); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUFT_LVCMOS33_F_2.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUFT_LVCMOS33_F_2.v new file mode 100644 index 0000000..dc12075 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUFT_LVCMOS33_F_2.v @@ -0,0 +1,39 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/OBUFT_LVCMOS33_F_2.v,v 1.6 2007/05/23 21:43:43 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / 3-State Output Buffer with LVCMOS33 I/O Standard Fast Slew 2 mA Drive +// /___/ /\ Filename : OBUFT_LVCMOS33_F_2.v +// \ \ / \ Timestamp : Thu Mar 25 16:43:10 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. +// 05/23/07 - Added wire declaration for internal signals. + +`timescale 1 ps / 1 ps + + +module OBUFT_LVCMOS33_F_2 (O, I, T); + + output O; + + input I, T; + + wire ts; + + tri0 GTS = glbl.GTS; + + or O1 (ts, GTS, T); + bufif0 T1 (O, I, ts); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUFT_LVCMOS33_F_24.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUFT_LVCMOS33_F_24.v new file mode 100644 index 0000000..5236fa6 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUFT_LVCMOS33_F_24.v @@ -0,0 +1,39 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/OBUFT_LVCMOS33_F_24.v,v 1.6 2007/05/23 21:43:43 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / 3-State Output Buffer with LVCMOS33 I/O Standard Fast Slew 24 mA Drive +// /___/ /\ Filename : OBUFT_LVCMOS33_F_24.v +// \ \ / \ Timestamp : Thu Mar 25 16:43:10 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. +// 05/23/07 - Added wire declaration for internal signals. + +`timescale 1 ps / 1 ps + + +module OBUFT_LVCMOS33_F_24 (O, I, T); + + output O; + + input I, T; + + wire ts; + + tri0 GTS = glbl.GTS; + + or O1 (ts, GTS, T); + bufif0 T1 (O, I, ts); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUFT_LVCMOS33_F_4.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUFT_LVCMOS33_F_4.v new file mode 100644 index 0000000..fbdd290 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUFT_LVCMOS33_F_4.v @@ -0,0 +1,39 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/OBUFT_LVCMOS33_F_4.v,v 1.6 2007/05/23 21:43:43 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / 3-State Output Buffer with LVCMOS33 I/O Standard Fast Slew 4 mA Drive +// /___/ /\ Filename : OBUFT_LVCMOS33_F_4.v +// \ \ / \ Timestamp : Thu Mar 25 16:43:10 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. +// 05/23/07 - Added wire declaration for internal signals. + +`timescale 1 ps / 1 ps + + +module OBUFT_LVCMOS33_F_4 (O, I, T); + + output O; + + input I, T; + + wire ts; + + tri0 GTS = glbl.GTS; + + or O1 (ts, GTS, T); + bufif0 T1 (O, I, ts); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUFT_LVCMOS33_F_6.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUFT_LVCMOS33_F_6.v new file mode 100644 index 0000000..1c3968e --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUFT_LVCMOS33_F_6.v @@ -0,0 +1,39 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/OBUFT_LVCMOS33_F_6.v,v 1.6 2007/05/23 21:43:43 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / 3-State Output Buffer with LVCMOS33 I/O Standard Fast Slew 6 mA Drive +// /___/ /\ Filename : OBUFT_LVCMOS33_F_6.v +// \ \ / \ Timestamp : Thu Mar 25 16:43:10 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. +// 05/23/07 - Added wire declaration for internal signals. + +`timescale 1 ps / 1 ps + + +module OBUFT_LVCMOS33_F_6 (O, I, T); + + output O; + + input I, T; + + wire ts; + + tri0 GTS = glbl.GTS; + + or O1 (ts, GTS, T); + bufif0 T1 (O, I, ts); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUFT_LVCMOS33_F_8.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUFT_LVCMOS33_F_8.v new file mode 100644 index 0000000..f3245e0 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUFT_LVCMOS33_F_8.v @@ -0,0 +1,39 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/OBUFT_LVCMOS33_F_8.v,v 1.6 2007/05/23 21:43:43 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / 3-State Output Buffer with LVCMOS33 I/O Standard Fast Slew 8 mA Drive +// /___/ /\ Filename : OBUFT_LVCMOS33_F_8.v +// \ \ / \ Timestamp : Thu Mar 25 16:43:11 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. +// 05/23/07 - Added wire declaration for internal signals. + +`timescale 1 ps / 1 ps + + +module OBUFT_LVCMOS33_F_8 (O, I, T); + + output O; + + input I, T; + + wire ts; + + tri0 GTS = glbl.GTS; + + or O1 (ts, GTS, T); + bufif0 T1 (O, I, ts); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUFT_LVCMOS33_S_12.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUFT_LVCMOS33_S_12.v new file mode 100644 index 0000000..c7169c2 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUFT_LVCMOS33_S_12.v @@ -0,0 +1,39 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/OBUFT_LVCMOS33_S_12.v,v 1.6 2007/05/23 21:43:43 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / 3-State Output Buffer with LVCMOS33 I/O Standard Slow Slew 12 mA Drive +// /___/ /\ Filename : OBUFT_LVCMOS33_S_12.v +// \ \ / \ Timestamp : Thu Mar 25 16:43:11 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. +// 05/23/07 - Added wire declaration for internal signals. + +`timescale 1 ps / 1 ps + + +module OBUFT_LVCMOS33_S_12 (O, I, T); + + output O; + + input I, T; + + wire ts; + + tri0 GTS = glbl.GTS; + + or O1 (ts, GTS, T); + bufif0 T1 (O, I, ts); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUFT_LVCMOS33_S_16.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUFT_LVCMOS33_S_16.v new file mode 100644 index 0000000..4416006 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUFT_LVCMOS33_S_16.v @@ -0,0 +1,39 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/OBUFT_LVCMOS33_S_16.v,v 1.6 2007/05/23 21:43:43 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / 3-State Output Buffer with LVCMOS33 I/O Standard Slow Slew 16 mA Drive +// /___/ /\ Filename : OBUFT_LVCMOS33_S_16.v +// \ \ / \ Timestamp : Thu Mar 25 16:43:11 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. +// 05/23/07 - Added wire declaration for internal signals. + +`timescale 1 ps / 1 ps + + +module OBUFT_LVCMOS33_S_16 (O, I, T); + + output O; + + input I, T; + + wire ts; + + tri0 GTS = glbl.GTS; + + or O1 (ts, GTS, T); + bufif0 T1 (O, I, ts); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUFT_LVCMOS33_S_2.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUFT_LVCMOS33_S_2.v new file mode 100644 index 0000000..6fe1389 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUFT_LVCMOS33_S_2.v @@ -0,0 +1,39 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/OBUFT_LVCMOS33_S_2.v,v 1.6 2007/05/23 21:43:43 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / 3-State Output Buffer with LVCMOS33 I/O Standard Slow Slew 2 mA Drive +// /___/ /\ Filename : OBUFT_LVCMOS33_S_2.v +// \ \ / \ Timestamp : Thu Mar 25 16:43:11 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. +// 05/23/07 - Added wire declaration for internal signals. + +`timescale 1 ps / 1 ps + + +module OBUFT_LVCMOS33_S_2 (O, I, T); + + output O; + + input I, T; + + wire ts; + + tri0 GTS = glbl.GTS; + + or O1 (ts, GTS, T); + bufif0 T1 (O, I, ts); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUFT_LVCMOS33_S_24.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUFT_LVCMOS33_S_24.v new file mode 100644 index 0000000..e27377d --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUFT_LVCMOS33_S_24.v @@ -0,0 +1,39 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/OBUFT_LVCMOS33_S_24.v,v 1.6 2007/05/23 21:43:43 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / 3-State Output Buffer with LVCMOS33 I/O Standard Slow Slew 24 mA Drive +// /___/ /\ Filename : OBUFT_LVCMOS33_S_24.v +// \ \ / \ Timestamp : Thu Mar 25 16:43:11 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. +// 05/23/07 - Added wire declaration for internal signals. + +`timescale 1 ps / 1 ps + + +module OBUFT_LVCMOS33_S_24 (O, I, T); + + output O; + + input I, T; + + wire ts; + + tri0 GTS = glbl.GTS; + + or O1 (ts, GTS, T); + bufif0 T1 (O, I, ts); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUFT_LVCMOS33_S_4.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUFT_LVCMOS33_S_4.v new file mode 100644 index 0000000..0e50e55 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUFT_LVCMOS33_S_4.v @@ -0,0 +1,39 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/OBUFT_LVCMOS33_S_4.v,v 1.6 2007/05/23 21:43:43 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / 3-State Output Buffer with LVCMOS33 I/O Standard Slow Slew 4 mA Drive +// /___/ /\ Filename : OBUFT_LVCMOS33_S_4.v +// \ \ / \ Timestamp : Thu Mar 25 16:43:11 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. +// 05/23/07 - Added wire declaration for internal signals. + +`timescale 1 ps / 1 ps + + +module OBUFT_LVCMOS33_S_4 (O, I, T); + + output O; + + input I, T; + + wire ts; + + tri0 GTS = glbl.GTS; + + or O1 (ts, GTS, T); + bufif0 T1 (O, I, ts); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUFT_LVCMOS33_S_6.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUFT_LVCMOS33_S_6.v new file mode 100644 index 0000000..eca2118 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUFT_LVCMOS33_S_6.v @@ -0,0 +1,39 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/OBUFT_LVCMOS33_S_6.v,v 1.6 2007/05/23 21:43:43 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / 3-State Output Buffer with LVCMOS33 I/O Standard Slow Slew 6 mA Drive +// /___/ /\ Filename : OBUFT_LVCMOS33_S_6.v +// \ \ / \ Timestamp : Thu Mar 25 16:43:11 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. +// 05/23/07 - Added wire declaration for internal signals. + +`timescale 1 ps / 1 ps + + +module OBUFT_LVCMOS33_S_6 (O, I, T); + + output O; + + input I, T; + + wire ts; + + tri0 GTS = glbl.GTS; + + or O1 (ts, GTS, T); + bufif0 T1 (O, I, ts); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUFT_LVCMOS33_S_8.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUFT_LVCMOS33_S_8.v new file mode 100644 index 0000000..a9c8a29 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUFT_LVCMOS33_S_8.v @@ -0,0 +1,39 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/OBUFT_LVCMOS33_S_8.v,v 1.6 2007/05/23 21:43:43 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / 3-State Output Buffer with LVCMOS33 I/O Standard Slow Slew 8 mA Drive +// /___/ /\ Filename : OBUFT_LVCMOS33_S_8.v +// \ \ / \ Timestamp : Thu Mar 25 16:43:11 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. +// 05/23/07 - Added wire declaration for internal signals. + +`timescale 1 ps / 1 ps + + +module OBUFT_LVCMOS33_S_8 (O, I, T); + + output O; + + input I, T; + + wire ts; + + tri0 GTS = glbl.GTS; + + or O1 (ts, GTS, T); + bufif0 T1 (O, I, ts); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUFT_LVDCI_15.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUFT_LVDCI_15.v new file mode 100644 index 0000000..5e4449b --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUFT_LVDCI_15.v @@ -0,0 +1,39 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/OBUFT_LVDCI_15.v,v 1.6 2007/05/23 21:43:43 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / 3-State Output Buffer with LVDCI_15 I/O Standard +// /___/ /\ Filename : OBUFT_LVDCI_15.v +// \ \ / \ Timestamp : Thu Mar 25 16:43:11 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. +// 05/23/07 - Added wire declaration for internal signals. + +`timescale 1 ps / 1 ps + + +module OBUFT_LVDCI_15 (O, I, T); + + output O; + + input I, T; + + wire ts; + + tri0 GTS = glbl.GTS; + + or O1 (ts, GTS, T); + bufif0 T1 (O, I, ts); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUFT_LVDCI_18.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUFT_LVDCI_18.v new file mode 100644 index 0000000..5adc725 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUFT_LVDCI_18.v @@ -0,0 +1,39 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/OBUFT_LVDCI_18.v,v 1.6 2007/05/23 21:43:43 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / 3-State Output Buffer with LVDCI_18 I/O Standard +// /___/ /\ Filename : OBUFT_LVDCI_18.v +// \ \ / \ Timestamp : Thu Mar 25 16:43:11 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. +// 05/23/07 - Added wire declaration for internal signals. + +`timescale 1 ps / 1 ps + + +module OBUFT_LVDCI_18 (O, I, T); + + output O; + + input I, T; + + wire ts; + + tri0 GTS = glbl.GTS; + + or O1 (ts, GTS, T); + bufif0 T1 (O, I, ts); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUFT_LVDCI_25.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUFT_LVDCI_25.v new file mode 100644 index 0000000..613a347 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUFT_LVDCI_25.v @@ -0,0 +1,39 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/OBUFT_LVDCI_25.v,v 1.6 2007/05/23 21:43:43 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / 3-State Output Buffer with LVDCI_25 I/O Standard +// /___/ /\ Filename : OBUFT_LVDCI_25.v +// \ \ / \ Timestamp : Thu Mar 25 16:43:12 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. +// 05/23/07 - Added wire declaration for internal signals. + +`timescale 1 ps / 1 ps + + +module OBUFT_LVDCI_25 (O, I, T); + + output O; + + input I, T; + + wire ts; + + tri0 GTS = glbl.GTS; + + or O1 (ts, GTS, T); + bufif0 T1 (O, I, ts); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUFT_LVDCI_33.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUFT_LVDCI_33.v new file mode 100644 index 0000000..eaea11f --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUFT_LVDCI_33.v @@ -0,0 +1,39 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/OBUFT_LVDCI_33.v,v 1.6 2007/05/23 21:43:43 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / 3-State Output Buffer with LVDCI_33 I/O Standard +// /___/ /\ Filename : OBUFT_LVDCI_33.v +// \ \ / \ Timestamp : Thu Mar 25 16:43:12 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. +// 05/23/07 - Added wire declaration for internal signals. + +`timescale 1 ps / 1 ps + + +module OBUFT_LVDCI_33 (O, I, T); + + output O; + + input I, T; + + wire ts; + + tri0 GTS = glbl.GTS; + + or O1 (ts, GTS, T); + bufif0 T1 (O, I, ts); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUFT_LVDCI_DV2_15.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUFT_LVDCI_DV2_15.v new file mode 100644 index 0000000..d92fc61 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUFT_LVDCI_DV2_15.v @@ -0,0 +1,39 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/OBUFT_LVDCI_DV2_15.v,v 1.6 2007/05/23 21:43:43 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / 3-State Output Buffer with LVDCI_DV2_15 I/O Standard +// /___/ /\ Filename : OBUFT_LVDCI_DV2_15.v +// \ \ / \ Timestamp : Thu Mar 25 16:43:12 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. +// 05/23/07 - Added wire declaration for internal signals. + +`timescale 1 ps / 1 ps + + +module OBUFT_LVDCI_DV2_15 (O, I, T); + + output O; + + input I, T; + + wire ts; + + tri0 GTS = glbl.GTS; + + or O1 (ts, GTS, T); + bufif0 T1 (O, I, ts); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUFT_LVDCI_DV2_18.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUFT_LVDCI_DV2_18.v new file mode 100644 index 0000000..81faff3 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUFT_LVDCI_DV2_18.v @@ -0,0 +1,39 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/OBUFT_LVDCI_DV2_18.v,v 1.6 2007/05/23 21:43:43 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / 3-State Output Buffer with LVDCI_DV2_18 I/O Standard +// /___/ /\ Filename : OBUFT_LVDCI_DV2_18.v +// \ \ / \ Timestamp : Thu Mar 25 16:43:12 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. +// 05/23/07 - Added wire declaration for internal signals. + +`timescale 1 ps / 1 ps + + +module OBUFT_LVDCI_DV2_18 (O, I, T); + + output O; + + input I, T; + + wire ts; + + tri0 GTS = glbl.GTS; + + or O1 (ts, GTS, T); + bufif0 T1 (O, I, ts); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUFT_LVDCI_DV2_25.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUFT_LVDCI_DV2_25.v new file mode 100644 index 0000000..0602330 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUFT_LVDCI_DV2_25.v @@ -0,0 +1,39 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/OBUFT_LVDCI_DV2_25.v,v 1.6 2007/05/23 21:43:43 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / 3-State Output Buffer with LVDCI_DV2_25 I/O Standard +// /___/ /\ Filename : OBUFT_LVDCI_DV2_25.v +// \ \ / \ Timestamp : Thu Mar 25 16:43:12 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. +// 05/23/07 - Added wire declaration for internal signals. + +`timescale 1 ps / 1 ps + + +module OBUFT_LVDCI_DV2_25 (O, I, T); + + output O; + + input I, T; + + wire ts; + + tri0 GTS = glbl.GTS; + + or O1 (ts, GTS, T); + bufif0 T1 (O, I, ts); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUFT_LVDCI_DV2_33.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUFT_LVDCI_DV2_33.v new file mode 100644 index 0000000..6b4b8bd --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUFT_LVDCI_DV2_33.v @@ -0,0 +1,39 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/OBUFT_LVDCI_DV2_33.v,v 1.6 2007/05/23 21:43:43 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / 3-State Output Buffer with LVDCI_DV2_33 I/O Standard +// /___/ /\ Filename : OBUFT_LVDCI_DV2_33.v +// \ \ / \ Timestamp : Thu Mar 25 16:43:12 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. +// 05/23/07 - Added wire declaration for internal signals. + +`timescale 1 ps / 1 ps + + +module OBUFT_LVDCI_DV2_33 (O, I, T); + + output O; + + input I, T; + + wire ts; + + tri0 GTS = glbl.GTS; + + or O1 (ts, GTS, T); + bufif0 T1 (O, I, ts); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUFT_LVDS.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUFT_LVDS.v new file mode 100644 index 0000000..1707e30 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUFT_LVDS.v @@ -0,0 +1,39 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/OBUFT_LVDS.v,v 1.6 2007/05/23 21:43:43 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / 3-State Output Buffer with LVDS I/O Standard +// /___/ /\ Filename : OBUFT_LVDS.v +// \ \ / \ Timestamp : Thu Mar 25 16:43:12 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. +// 05/23/07 - Added wire declaration for internal signals. + +`timescale 1 ps / 1 ps + + +module OBUFT_LVDS (O, I, T); + + output O; + + input I, T; + + wire ts; + + tri0 GTS = glbl.GTS; + + or O1 (ts, GTS, T); + bufif0 T1 (O, I, ts); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUFT_LVPECL.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUFT_LVPECL.v new file mode 100644 index 0000000..6669aaf --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUFT_LVPECL.v @@ -0,0 +1,39 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/OBUFT_LVPECL.v,v 1.6 2007/05/23 21:43:43 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / 3-State Output Buffer with LVPECL I/O Standard +// /___/ /\ Filename : OBUFT_LVPECL.v +// \ \ / \ Timestamp : Thu Mar 25 16:43:12 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. +// 05/23/07 - Added wire declaration for internal signals. + +`timescale 1 ps / 1 ps + + +module OBUFT_LVPECL (O, I, T); + + output O; + + input I, T; + + wire ts; + + tri0 GTS = glbl.GTS; + + or O1 (ts, GTS, T); + bufif0 T1 (O, I, ts); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUFT_LVTTL.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUFT_LVTTL.v new file mode 100644 index 0000000..8ca310b --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUFT_LVTTL.v @@ -0,0 +1,39 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/OBUFT_LVTTL.v,v 1.6 2007/05/23 21:43:43 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / 3-State Output Buffer with LVTTL I/O Standard +// /___/ /\ Filename : OBUFT_LVTTL.v +// \ \ / \ Timestamp : Thu Mar 25 16:43:12 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. +// 05/23/07 - Added wire declaration for internal signals. + +`timescale 1 ps / 1 ps + + +module OBUFT_LVTTL (O, I, T); + + output O; + + input I, T; + + wire ts; + + tri0 GTS = glbl.GTS; + + or O1 (ts, GTS, T); + bufif0 T1 (O, I, ts); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUFT_LVTTL_F_12.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUFT_LVTTL_F_12.v new file mode 100644 index 0000000..51d6583 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUFT_LVTTL_F_12.v @@ -0,0 +1,39 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/OBUFT_LVTTL_F_12.v,v 1.6 2007/05/23 21:43:43 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / 3-State Output Buffer with LVTTL I/O Standard Fast Slew 12 mA Drive +// /___/ /\ Filename : OBUFT_LVTTL_F_12.v +// \ \ / \ Timestamp : Thu Mar 25 16:43:12 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. +// 05/23/07 - Added wire declaration for internal signals. + +`timescale 1 ps / 1 ps + + +module OBUFT_LVTTL_F_12 (O, I, T); + + output O; + + input I, T; + + wire ts; + + tri0 GTS = glbl.GTS; + + or O1 (ts, GTS, T); + bufif0 T1 (O, I, ts); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUFT_LVTTL_F_16.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUFT_LVTTL_F_16.v new file mode 100644 index 0000000..f8ca534 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUFT_LVTTL_F_16.v @@ -0,0 +1,39 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/OBUFT_LVTTL_F_16.v,v 1.6 2007/05/23 21:43:43 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / 3-State Output Buffer with LVTTL I/O Standard Fast Slew 16 mA Drive +// /___/ /\ Filename : OBUFT_LVTTL_F_16.v +// \ \ / \ Timestamp : Thu Mar 25 16:43:12 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. +// 05/23/07 - Added wire declaration for internal signals. + +`timescale 1 ps / 1 ps + + +module OBUFT_LVTTL_F_16 (O, I, T); + + output O; + + input I, T; + + wire ts; + + tri0 GTS = glbl.GTS; + + or O1 (ts, GTS, T); + bufif0 T1 (O, I, ts); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUFT_LVTTL_F_2.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUFT_LVTTL_F_2.v new file mode 100644 index 0000000..70b421e --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUFT_LVTTL_F_2.v @@ -0,0 +1,39 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/OBUFT_LVTTL_F_2.v,v 1.6 2007/05/23 21:43:43 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / 3-State Output Buffer with LVTTL I/O Standard Fast Slew 2 mA Drive +// /___/ /\ Filename : OBUFT_LVTTL_F_2.v +// \ \ / \ Timestamp : Thu Mar 25 16:43:13 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. +// 05/23/07 - Added wire declaration for internal signals. + +`timescale 1 ps / 1 ps + + +module OBUFT_LVTTL_F_2 (O, I, T); + + output O; + + input I, T; + + wire ts; + + tri0 GTS = glbl.GTS; + + or O1 (ts, GTS, T); + bufif0 T1 (O, I, ts); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUFT_LVTTL_F_24.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUFT_LVTTL_F_24.v new file mode 100644 index 0000000..7e789d5 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUFT_LVTTL_F_24.v @@ -0,0 +1,39 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/OBUFT_LVTTL_F_24.v,v 1.6 2007/05/23 21:43:43 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / 3-State Output Buffer with LVTTL I/O Standard Fast Slew 24 mA Drive +// /___/ /\ Filename : OBUFT_LVTTL_F_24.v +// \ \ / \ Timestamp : Thu Mar 25 16:43:13 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. +// 05/23/07 - Added wire declaration for internal signals. + +`timescale 1 ps / 1 ps + + +module OBUFT_LVTTL_F_24 (O, I, T); + + output O; + + input I, T; + + wire ts; + + tri0 GTS = glbl.GTS; + + or O1 (ts, GTS, T); + bufif0 T1 (O, I, ts); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUFT_LVTTL_F_4.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUFT_LVTTL_F_4.v new file mode 100644 index 0000000..60f9bbf --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUFT_LVTTL_F_4.v @@ -0,0 +1,39 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/OBUFT_LVTTL_F_4.v,v 1.6 2007/05/23 21:43:43 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / 3-State Output Buffer with LVTTL I/O Standard Fast Slew 4 mA Drive +// /___/ /\ Filename : OBUFT_LVTTL_F_4.v +// \ \ / \ Timestamp : Thu Mar 25 16:43:13 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. +// 05/23/07 - Added wire declaration for internal signals. + +`timescale 1 ps / 1 ps + + +module OBUFT_LVTTL_F_4 (O, I, T); + + output O; + + input I, T; + + wire ts; + + tri0 GTS = glbl.GTS; + + or O1 (ts, GTS, T); + bufif0 T1 (O, I, ts); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUFT_LVTTL_F_6.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUFT_LVTTL_F_6.v new file mode 100644 index 0000000..942a0f0 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUFT_LVTTL_F_6.v @@ -0,0 +1,39 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/OBUFT_LVTTL_F_6.v,v 1.6 2007/05/23 21:43:43 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / 3-State Output Buffer with LVTTL I/O Standard Fast Slew 6 mA Drive +// /___/ /\ Filename : OBUFT_LVTTL_F_6.v +// \ \ / \ Timestamp : Thu Mar 25 16:43:13 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. +// 05/23/07 - Added wire declaration for internal signals. + +`timescale 1 ps / 1 ps + + +module OBUFT_LVTTL_F_6 (O, I, T); + + output O; + + input I, T; + + wire ts; + + tri0 GTS = glbl.GTS; + + or O1 (ts, GTS, T); + bufif0 T1 (O, I, ts); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUFT_LVTTL_F_8.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUFT_LVTTL_F_8.v new file mode 100644 index 0000000..18d602f --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUFT_LVTTL_F_8.v @@ -0,0 +1,39 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/OBUFT_LVTTL_F_8.v,v 1.6 2007/05/23 21:43:43 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / 3-State Output Buffer with LVTTL I/O Standard Fast Slew 8 mA Drive +// /___/ /\ Filename : OBUFT_LVTTL_F_8.v +// \ \ / \ Timestamp : Thu Mar 25 16:43:13 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. +// 05/23/07 - Added wire declaration for internal signals. + +`timescale 1 ps / 1 ps + + +module OBUFT_LVTTL_F_8 (O, I, T); + + output O; + + input I, T; + + wire ts; + + tri0 GTS = glbl.GTS; + + or O1 (ts, GTS, T); + bufif0 T1 (O, I, ts); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUFT_LVTTL_S_12.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUFT_LVTTL_S_12.v new file mode 100644 index 0000000..8ca3e87 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUFT_LVTTL_S_12.v @@ -0,0 +1,39 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/OBUFT_LVTTL_S_12.v,v 1.6 2007/05/23 21:43:43 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / 3-State Output Buffer with LVTTL I/O Standard Slow Slew 12 mA Drive +// /___/ /\ Filename : OBUFT_LVTTL_S_12.v +// \ \ / \ Timestamp : Thu Mar 25 16:43:13 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. +// 05/23/07 - Added wire declaration for internal signals. + +`timescale 1 ps / 1 ps + + +module OBUFT_LVTTL_S_12 (O, I, T); + + output O; + + input I, T; + + wire ts; + + tri0 GTS = glbl.GTS; + + or O1 (ts, GTS, T); + bufif0 T1 (O, I, ts); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUFT_LVTTL_S_16.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUFT_LVTTL_S_16.v new file mode 100644 index 0000000..677d17c --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUFT_LVTTL_S_16.v @@ -0,0 +1,39 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/OBUFT_LVTTL_S_16.v,v 1.6 2007/05/23 21:43:43 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / 3-State Output Buffer with LVTTL I/O Standard Slow Slew 16 mA Drive +// /___/ /\ Filename : OBUFT_LVTTL_S_16.v +// \ \ / \ Timestamp : Thu Mar 25 16:43:13 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. +// 05/23/07 - Added wire declaration for internal signals. + +`timescale 1 ps / 1 ps + + +module OBUFT_LVTTL_S_16 (O, I, T); + + output O; + + input I, T; + + wire ts; + + tri0 GTS = glbl.GTS; + + or O1 (ts, GTS, T); + bufif0 T1 (O, I, ts); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUFT_LVTTL_S_2.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUFT_LVTTL_S_2.v new file mode 100644 index 0000000..7f0ef64 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUFT_LVTTL_S_2.v @@ -0,0 +1,39 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/OBUFT_LVTTL_S_2.v,v 1.6 2007/05/23 21:43:43 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / 3-State Output Buffer with LVTTL I/O Standard Slow Slew 2 mA Drive +// /___/ /\ Filename : OBUFT_LVTTL_S_2.v +// \ \ / \ Timestamp : Thu Mar 25 16:43:13 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. +// 05/23/07 - Added wire declaration for internal signals. + +`timescale 1 ps / 1 ps + + +module OBUFT_LVTTL_S_2 (O, I, T); + + output O; + + input I, T; + + wire ts; + + tri0 GTS = glbl.GTS; + + or O1 (ts, GTS, T); + bufif0 T1 (O, I, ts); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUFT_LVTTL_S_24.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUFT_LVTTL_S_24.v new file mode 100644 index 0000000..8efcb8d --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUFT_LVTTL_S_24.v @@ -0,0 +1,39 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/OBUFT_LVTTL_S_24.v,v 1.6 2007/05/23 21:43:43 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / 3-State Output Buffer with LVTTL I/O Standard Slow Slew 24 mA Drive +// /___/ /\ Filename : OBUFT_LVTTL_S_24.v +// \ \ / \ Timestamp : Thu Mar 25 16:43:13 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. +// 05/23/07 - Added wire declaration for internal signals. + +`timescale 1 ps / 1 ps + + +module OBUFT_LVTTL_S_24 (O, I, T); + + output O; + + input I, T; + + wire ts; + + tri0 GTS = glbl.GTS; + + or O1 (ts, GTS, T); + bufif0 T1 (O, I, ts); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUFT_LVTTL_S_4.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUFT_LVTTL_S_4.v new file mode 100644 index 0000000..b6850bc --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUFT_LVTTL_S_4.v @@ -0,0 +1,39 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/OBUFT_LVTTL_S_4.v,v 1.6 2007/05/23 21:43:43 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / 3-State Output Buffer with LVTTL I/O Standard Slow Slew 4 mA Drive +// /___/ /\ Filename : OBUFT_LVTTL_S_4.v +// \ \ / \ Timestamp : Thu Mar 25 16:43:13 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. +// 05/23/07 - Added wire declaration for internal signals. + +`timescale 1 ps / 1 ps + + +module OBUFT_LVTTL_S_4 (O, I, T); + + output O; + + input I, T; + + wire ts; + + tri0 GTS = glbl.GTS; + + or O1 (ts, GTS, T); + bufif0 T1 (O, I, ts); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUFT_LVTTL_S_6.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUFT_LVTTL_S_6.v new file mode 100644 index 0000000..e7e19bc --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUFT_LVTTL_S_6.v @@ -0,0 +1,39 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/OBUFT_LVTTL_S_6.v,v 1.6 2007/05/23 21:43:43 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / 3-State Output Buffer with LVTTL I/O Standard Slow Slew 6 mA Drive +// /___/ /\ Filename : OBUFT_LVTTL_S_6.v +// \ \ / \ Timestamp : Thu Mar 25 16:43:14 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. +// 05/23/07 - Added wire declaration for internal signals. + +`timescale 1 ps / 1 ps + + +module OBUFT_LVTTL_S_6 (O, I, T); + + output O; + + input I, T; + + wire ts; + + tri0 GTS = glbl.GTS; + + or O1 (ts, GTS, T); + bufif0 T1 (O, I, ts); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUFT_LVTTL_S_8.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUFT_LVTTL_S_8.v new file mode 100644 index 0000000..1e836ee --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUFT_LVTTL_S_8.v @@ -0,0 +1,39 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/OBUFT_LVTTL_S_8.v,v 1.6 2007/05/23 21:43:43 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / 3-State Output Buffer with LVTTL I/O Standard Slow Slew 8 mA Drive +// /___/ /\ Filename : OBUFT_LVTTL_S_8.v +// \ \ / \ Timestamp : Thu Mar 25 16:43:14 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. +// 05/23/07 - Added wire declaration for internal signals. + +`timescale 1 ps / 1 ps + + +module OBUFT_LVTTL_S_8 (O, I, T); + + output O; + + input I, T; + + wire ts; + + tri0 GTS = glbl.GTS; + + or O1 (ts, GTS, T); + bufif0 T1 (O, I, ts); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUFT_PCI33_3.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUFT_PCI33_3.v new file mode 100644 index 0000000..df4ff5b --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUFT_PCI33_3.v @@ -0,0 +1,39 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/OBUFT_PCI33_3.v,v 1.6 2007/05/23 21:43:43 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / 3-State Output Buffer with PCI33_3 I/O Standard +// /___/ /\ Filename : OBUFT_PCI33_3.v +// \ \ / \ Timestamp : Thu Mar 25 16:43:14 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. +// 05/23/07 - Added wire declaration for internal signals. + +`timescale 1 ps / 1 ps + + +module OBUFT_PCI33_3 (O, I, T); + + output O; + + input I, T; + + wire ts; + + tri0 GTS = glbl.GTS; + + or O1 (ts, GTS, T); + bufif0 T1 (O, I, ts); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUFT_PCI33_5.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUFT_PCI33_5.v new file mode 100644 index 0000000..367e49f --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUFT_PCI33_5.v @@ -0,0 +1,39 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/OBUFT_PCI33_5.v,v 1.6 2007/05/23 21:43:43 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / 3-State Output Buffer with PCI33_5 I/O Standard +// /___/ /\ Filename : OBUFT_PCI33_5.v +// \ \ / \ Timestamp : Thu Mar 25 16:43:14 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. +// 05/23/07 - Added wire declaration for internal signals. + +`timescale 1 ps / 1 ps + + +module OBUFT_PCI33_5 (O, I, T); + + output O; + + input I, T; + + wire ts; + + tri0 GTS = glbl.GTS; + + or O1 (ts, GTS, T); + bufif0 T1 (O, I, ts); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUFT_PCI66_3.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUFT_PCI66_3.v new file mode 100644 index 0000000..524d619 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUFT_PCI66_3.v @@ -0,0 +1,39 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/OBUFT_PCI66_3.v,v 1.6 2007/05/23 21:43:43 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / 3-State Output Buffer with PCI66_3 I/O Standard +// /___/ /\ Filename : OBUFT_PCI66_3.v +// \ \ / \ Timestamp : Thu Mar 25 16:43:14 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. +// 05/23/07 - Added wire declaration for internal signals. + +`timescale 1 ps / 1 ps + + +module OBUFT_PCI66_3 (O, I, T); + + output O; + + input I, T; + + wire ts; + + tri0 GTS = glbl.GTS; + + or O1 (ts, GTS, T); + bufif0 T1 (O, I, ts); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUFT_PCIX.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUFT_PCIX.v new file mode 100644 index 0000000..e5d3b6e --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUFT_PCIX.v @@ -0,0 +1,39 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/OBUFT_PCIX.v,v 1.6 2007/05/23 21:43:43 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / 3-State Output Buffer with PCIX I/O Standard +// /___/ /\ Filename : OBUFT_PCIX.v +// \ \ / \ Timestamp : Thu Mar 25 16:43:14 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. +// 05/23/07 - Added wire declaration for internal signals. + +`timescale 1 ps / 1 ps + + +module OBUFT_PCIX (O, I, T); + + output O; + + input I, T; + + wire ts; + + tri0 GTS = glbl.GTS; + + or O1 (ts, GTS, T); + bufif0 T1 (O, I, ts); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUFT_PCIX66_3.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUFT_PCIX66_3.v new file mode 100644 index 0000000..5645044 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUFT_PCIX66_3.v @@ -0,0 +1,39 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/OBUFT_PCIX66_3.v,v 1.6 2007/05/23 21:43:43 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / 3-State Output Buffer with PCIX66_3 I/O Standard +// /___/ /\ Filename : OBUFT_PCIX66_3.v +// \ \ / \ Timestamp : Thu Mar 25 16:43:14 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. +// 05/23/07 - Added wire declaration for internal signals. + +`timescale 1 ps / 1 ps + + +module OBUFT_PCIX66_3 (O, I, T); + + output O; + + input I, T; + + wire ts; + + tri0 GTS = glbl.GTS; + + or O1 (ts, GTS, T); + bufif0 T1 (O, I, ts); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUFT_SSTL18_I.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUFT_SSTL18_I.v new file mode 100644 index 0000000..2b3902d --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUFT_SSTL18_I.v @@ -0,0 +1,39 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/OBUFT_SSTL18_I.v,v 1.6 2007/05/23 21:43:43 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / 3-State Output Buffer with SSTL18_I I/O Standard +// /___/ /\ Filename : OBUFT_SSTL18_I.v +// \ \ / \ Timestamp : Thu Mar 25 16:43:14 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. +// 05/23/07 - Added wire declaration for internal signals. + +`timescale 1 ps / 1 ps + + +module OBUFT_SSTL18_I (O, I, T); + + output O; + + input I, T; + + wire ts; + + tri0 GTS = glbl.GTS; + + or O1 (ts, GTS, T); + bufif0 T1 (O, I, ts); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUFT_SSTL18_II.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUFT_SSTL18_II.v new file mode 100644 index 0000000..ed0ef9a --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUFT_SSTL18_II.v @@ -0,0 +1,39 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/OBUFT_SSTL18_II.v,v 1.6 2007/05/23 21:43:43 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / 3-State Output Buffer with SSTL18_II I/O Standard +// /___/ /\ Filename : OBUFT_SSTL18_II.v +// \ \ / \ Timestamp : Thu Mar 25 16:43:14 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. +// 05/23/07 - Added wire declaration for internal signals. + +`timescale 1 ps / 1 ps + + +module OBUFT_SSTL18_II (O, I, T); + + output O; + + input I, T; + + wire ts; + + tri0 GTS = glbl.GTS; + + or O1 (ts, GTS, T); + bufif0 T1 (O, I, ts); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUFT_SSTL18_II_DCI.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUFT_SSTL18_II_DCI.v new file mode 100644 index 0000000..d53e01b --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUFT_SSTL18_II_DCI.v @@ -0,0 +1,39 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/OBUFT_SSTL18_II_DCI.v,v 1.6 2007/05/23 21:43:43 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / 3-State Output Buffer with SSTL18_II_DCI I/O Standard +// /___/ /\ Filename : OBUFT_SSTL18_II_DCI.v +// \ \ / \ Timestamp : Thu Mar 25 16:43:14 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. +// 05/23/07 - Added wire declaration for internal signals. + +`timescale 1 ps / 1 ps + + +module OBUFT_SSTL18_II_DCI (O, I, T); + + output O; + + input I, T; + + wire ts; + + tri0 GTS = glbl.GTS; + + or O1 (ts, GTS, T); + bufif0 T1 (O, I, ts); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUFT_SSTL18_I_DCI.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUFT_SSTL18_I_DCI.v new file mode 100644 index 0000000..81723cd --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUFT_SSTL18_I_DCI.v @@ -0,0 +1,39 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/OBUFT_SSTL18_I_DCI.v,v 1.6 2007/05/23 21:43:43 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / 3-State Output Buffer with SSTL18_I_DCI I/O Standard +// /___/ /\ Filename : OBUFT_SSTL18_I_DCI.v +// \ \ / \ Timestamp : Thu Mar 25 16:43:14 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. +// 05/23/07 - Added wire declaration for internal signals. + +`timescale 1 ps / 1 ps + + +module OBUFT_SSTL18_I_DCI (O, I, T); + + output O; + + input I, T; + + wire ts; + + tri0 GTS = glbl.GTS; + + or O1 (ts, GTS, T); + bufif0 T1 (O, I, ts); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUFT_SSTL2_I.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUFT_SSTL2_I.v new file mode 100644 index 0000000..ba6ab1f --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUFT_SSTL2_I.v @@ -0,0 +1,39 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/OBUFT_SSTL2_I.v,v 1.6 2007/05/23 21:43:43 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / 3-State Output Buffer with SSTL2_I I/O Standard +// /___/ /\ Filename : OBUFT_SSTL2_I.v +// \ \ / \ Timestamp : Thu Mar 25 16:43:15 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. +// 05/23/07 - Added wire declaration for internal signals. + +`timescale 1 ps / 1 ps + + +module OBUFT_SSTL2_I (O, I, T); + + output O; + + input I, T; + + wire ts; + + tri0 GTS = glbl.GTS; + + or O1 (ts, GTS, T); + bufif0 T1 (O, I, ts); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUFT_SSTL2_II.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUFT_SSTL2_II.v new file mode 100644 index 0000000..5821e3f --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUFT_SSTL2_II.v @@ -0,0 +1,39 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/OBUFT_SSTL2_II.v,v 1.6 2007/05/23 21:43:43 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / 3-State Output Buffer with SSTL2_II I/O Standard +// /___/ /\ Filename : OBUFT_SSTL2_II.v +// \ \ / \ Timestamp : Thu Mar 25 16:43:15 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. +// 05/23/07 - Added wire declaration for internal signals. + +`timescale 1 ps / 1 ps + + +module OBUFT_SSTL2_II (O, I, T); + + output O; + + input I, T; + + wire ts; + + tri0 GTS = glbl.GTS; + + or O1 (ts, GTS, T); + bufif0 T1 (O, I, ts); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUFT_SSTL2_II_DCI.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUFT_SSTL2_II_DCI.v new file mode 100644 index 0000000..35ab5c7 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUFT_SSTL2_II_DCI.v @@ -0,0 +1,39 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/OBUFT_SSTL2_II_DCI.v,v 1.6 2007/05/23 21:43:43 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / 3-State Output Buffer with SSTL2_II_DCI I/O Standard +// /___/ /\ Filename : OBUFT_SSTL2_II_DCI.v +// \ \ / \ Timestamp : Thu Mar 25 16:43:15 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. +// 05/23/07 - Added wire declaration for internal signals. + +`timescale 1 ps / 1 ps + + +module OBUFT_SSTL2_II_DCI (O, I, T); + + output O; + + input I, T; + + wire ts; + + tri0 GTS = glbl.GTS; + + or O1 (ts, GTS, T); + bufif0 T1 (O, I, ts); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUFT_SSTL2_I_DCI.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUFT_SSTL2_I_DCI.v new file mode 100644 index 0000000..59cb4b1 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUFT_SSTL2_I_DCI.v @@ -0,0 +1,39 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/OBUFT_SSTL2_I_DCI.v,v 1.6 2007/05/23 21:43:43 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / 3-State Output Buffer with SSTL2_I_DCI I/O Standard +// /___/ /\ Filename : OBUFT_SSTL2_I_DCI.v +// \ \ / \ Timestamp : Thu Mar 25 16:43:15 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. +// 05/23/07 - Added wire declaration for internal signals. + +`timescale 1 ps / 1 ps + + +module OBUFT_SSTL2_I_DCI (O, I, T); + + output O; + + input I, T; + + wire ts; + + tri0 GTS = glbl.GTS; + + or O1 (ts, GTS, T); + bufif0 T1 (O, I, ts); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUFT_SSTL3_I.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUFT_SSTL3_I.v new file mode 100644 index 0000000..d6eb1ae --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUFT_SSTL3_I.v @@ -0,0 +1,39 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/OBUFT_SSTL3_I.v,v 1.6 2007/05/23 21:43:44 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / 3-State Output Buffer with SSTL3_I I/O Standard +// /___/ /\ Filename : OBUFT_SSTL3_I.v +// \ \ / \ Timestamp : Thu Mar 25 16:43:15 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. +// 05/23/07 - Added wire declaration for internal signals. + +`timescale 1 ps / 1 ps + + +module OBUFT_SSTL3_I (O, I, T); + + output O; + + input I, T; + + wire ts; + + tri0 GTS = glbl.GTS; + + or O1 (ts, GTS, T); + bufif0 T1 (O, I, ts); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUFT_SSTL3_II.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUFT_SSTL3_II.v new file mode 100644 index 0000000..37ba43c --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUFT_SSTL3_II.v @@ -0,0 +1,39 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/OBUFT_SSTL3_II.v,v 1.6 2007/05/23 21:43:44 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / 3-State Output Buffer with SSTL3_II I/O Standard +// /___/ /\ Filename : OBUFT_SSTL3_II.v +// \ \ / \ Timestamp : Thu Mar 25 16:43:15 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. +// 05/23/07 - Added wire declaration for internal signals. + +`timescale 1 ps / 1 ps + + +module OBUFT_SSTL3_II (O, I, T); + + output O; + + input I, T; + + wire ts; + + tri0 GTS = glbl.GTS; + + or O1 (ts, GTS, T); + bufif0 T1 (O, I, ts); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUFT_SSTL3_II_DCI.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUFT_SSTL3_II_DCI.v new file mode 100644 index 0000000..640bf13 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUFT_SSTL3_II_DCI.v @@ -0,0 +1,39 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/OBUFT_SSTL3_II_DCI.v,v 1.6 2007/05/23 21:43:43 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / 3-State Output Buffer with SSTL3_II_DCI I/O Standard +// /___/ /\ Filename : OBUFT_SSTL3_II_DCI.v +// \ \ / \ Timestamp : Thu Mar 25 16:43:15 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. +// 05/23/07 - Added wire declaration for internal signals. + +`timescale 1 ps / 1 ps + + +module OBUFT_SSTL3_II_DCI (O, I, T); + + output O; + + input I, T; + + wire ts; + + tri0 GTS = glbl.GTS; + + or O1 (ts, GTS, T); + bufif0 T1 (O, I, ts); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUFT_SSTL3_I_DCI.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUFT_SSTL3_I_DCI.v new file mode 100644 index 0000000..0ae2057 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUFT_SSTL3_I_DCI.v @@ -0,0 +1,39 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/OBUFT_SSTL3_I_DCI.v,v 1.6 2007/05/23 21:43:43 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / 3-State Output Buffer with SSTL3_I_DCI I/O Standard +// /___/ /\ Filename : OBUFT_SSTL3_I_DCI.v +// \ \ / \ Timestamp : Thu Mar 25 16:43:15 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. +// 05/23/07 - Added wire declaration for internal signals. + +`timescale 1 ps / 1 ps + + +module OBUFT_SSTL3_I_DCI (O, I, T); + + output O; + + input I, T; + + wire ts; + + tri0 GTS = glbl.GTS; + + or O1 (ts, GTS, T); + bufif0 T1 (O, I, ts); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUFT_S_12.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUFT_S_12.v new file mode 100644 index 0000000..d9878a3 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUFT_S_12.v @@ -0,0 +1,39 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/OBUFT_S_12.v,v 1.6 2007/05/23 21:43:43 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / 3-State Output Buffer with Slow Slew 12 mA Drive +// /___/ /\ Filename : OBUFT_S_12.v +// \ \ / \ Timestamp : Thu Mar 25 16:43:15 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. +// 05/23/07 - Added wire declaration for internal signals. + +`timescale 1 ps / 1 ps + + +module OBUFT_S_12 (O, I, T); + + output O; + + input I, T; + + wire ts; + + tri0 GTS = glbl.GTS; + + or O1 (ts, GTS, T); + bufif0 T1 (O, I, ts); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUFT_S_16.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUFT_S_16.v new file mode 100644 index 0000000..c62fb31 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUFT_S_16.v @@ -0,0 +1,39 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/OBUFT_S_16.v,v 1.6 2007/05/23 21:43:43 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / 3-State Output Buffer with Slow Slew 16 mA Drive +// /___/ /\ Filename : OBUFT_S_16.v +// \ \ / \ Timestamp : Thu Mar 25 16:43:15 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. +// 05/23/07 - Added wire declaration for internal signals. + +`timescale 1 ps / 1 ps + + +module OBUFT_S_16 (O, I, T); + + output O; + + input I, T; + + wire ts; + + tri0 GTS = glbl.GTS; + + or O1 (ts, GTS, T); + bufif0 T1 (O, I, ts); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUFT_S_2.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUFT_S_2.v new file mode 100644 index 0000000..60877cb --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUFT_S_2.v @@ -0,0 +1,39 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/OBUFT_S_2.v,v 1.6 2007/05/23 21:43:43 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / 3-State Output Buffer with Slow Slew 2 mA Drive +// /___/ /\ Filename : OBUFT_S_2.v +// \ \ / \ Timestamp : Thu Mar 25 16:43:16 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. +// 05/23/07 - Added wire declaration for internal signals. + +`timescale 1 ps / 1 ps + + +module OBUFT_S_2 (O, I, T); + + output O; + + input I, T; + + wire ts; + + tri0 GTS = glbl.GTS; + + or O1 (ts, GTS, T); + bufif0 T1 (O, I, ts); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUFT_S_24.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUFT_S_24.v new file mode 100644 index 0000000..0ddce2e --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUFT_S_24.v @@ -0,0 +1,39 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/OBUFT_S_24.v,v 1.6 2007/05/23 21:43:43 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / 3-State Output Buffer with Slow Slew 24 mA Drive +// /___/ /\ Filename : OBUFT_S_24.v +// \ \ / \ Timestamp : Thu Mar 25 16:43:16 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. +// 05/23/07 - Added wire declaration for internal signals. + +`timescale 1 ps / 1 ps + + +module OBUFT_S_24 (O, I, T); + + output O; + + input I, T; + + wire ts; + + tri0 GTS = glbl.GTS; + + or O1 (ts, GTS, T); + bufif0 T1 (O, I, ts); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUFT_S_4.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUFT_S_4.v new file mode 100644 index 0000000..ba1dbe7 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUFT_S_4.v @@ -0,0 +1,39 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/OBUFT_S_4.v,v 1.6 2007/05/23 21:43:43 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / 3-State Output Buffer with Slow Slew 4 mA Drive +// /___/ /\ Filename : OBUFT_S_4.v +// \ \ / \ Timestamp : Thu Mar 25 16:43:16 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. +// 05/23/07 - Added wire declaration for internal signals. + +`timescale 1 ps / 1 ps + + +module OBUFT_S_4 (O, I, T); + + output O; + + input I, T; + + wire ts; + + tri0 GTS = glbl.GTS; + + or O1 (ts, GTS, T); + bufif0 T1 (O, I, ts); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUFT_S_6.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUFT_S_6.v new file mode 100644 index 0000000..6fa3561 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUFT_S_6.v @@ -0,0 +1,39 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/OBUFT_S_6.v,v 1.6 2007/05/23 21:43:43 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / 3-State Output Buffer with Slow Slew 6 mA Drive +// /___/ /\ Filename : OBUFT_S_6.v +// \ \ / \ Timestamp : Thu Mar 25 16:43:16 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. +// 05/23/07 - Added wire declaration for internal signals. + +`timescale 1 ps / 1 ps + + +module OBUFT_S_6 (O, I, T); + + output O; + + input I, T; + + wire ts; + + tri0 GTS = glbl.GTS; + + or O1 (ts, GTS, T); + bufif0 T1 (O, I, ts); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUFT_S_8.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUFT_S_8.v new file mode 100644 index 0000000..486c997 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUFT_S_8.v @@ -0,0 +1,39 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/OBUFT_S_8.v,v 1.6 2007/05/23 21:43:43 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / 3-State Output Buffer with Slow Slew 8 mA Drive +// /___/ /\ Filename : OBUFT_S_8.v +// \ \ / \ Timestamp : Thu Mar 25 16:43:16 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. +// 05/23/07 - Added wire declaration for internal signals. + +`timescale 1 ps / 1 ps + + +module OBUFT_S_8 (O, I, T); + + output O; + + input I, T; + + wire ts; + + tri0 GTS = glbl.GTS; + + or O1 (ts, GTS, T); + bufif0 T1 (O, I, ts); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUF_AGP.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUF_AGP.v new file mode 100644 index 0000000..a014d50 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUF_AGP.v @@ -0,0 +1,35 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/OBUF_AGP.v,v 1.6 2007/05/23 21:43:40 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Output Buffer with AGP I/O Standard +// /___/ /\ Filename : OBUF_AGP.v +// \ \ / \ Timestamp : Thu Mar 25 16:43:16 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. + +`timescale 1 ps / 1 ps + + +module OBUF_AGP (O, I); + + output O; + + input I; + + tri0 GTS = glbl.GTS; + + bufif0 B1 (O, I, GTS); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUF_CTT.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUF_CTT.v new file mode 100644 index 0000000..7e376ef --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUF_CTT.v @@ -0,0 +1,35 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/OBUF_CTT.v,v 1.6 2007/05/23 21:43:40 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Output Buffer with CTT I/O Standard +// /___/ /\ Filename : OBUF_CTT.v +// \ \ / \ Timestamp : Thu Mar 25 16:43:16 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. + +`timescale 1 ps / 1 ps + + +module OBUF_CTT (O, I); + + output O; + + input I; + + tri0 GTS = glbl.GTS; + + bufif0 B1 (O, I, GTS); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUF_F_12.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUF_F_12.v new file mode 100644 index 0000000..9ea6f4e --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUF_F_12.v @@ -0,0 +1,35 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/OBUF_F_12.v,v 1.6 2007/05/23 21:43:40 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Output Buffer with Fast Slew 12 mA Drive +// /___/ /\ Filename : OBUF_F_12.v +// \ \ / \ Timestamp : Thu Mar 25 16:43:16 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. + +`timescale 1 ps / 1 ps + + +module OBUF_F_12 (O, I); + + output O; + + input I; + + tri0 GTS = glbl.GTS; + + bufif0 B1 (O, I, GTS); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUF_F_16.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUF_F_16.v new file mode 100644 index 0000000..f0bfdcb --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUF_F_16.v @@ -0,0 +1,35 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/OBUF_F_16.v,v 1.6 2007/05/23 21:43:40 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Output Buffer with Fast Slew 16 mA Drive +// /___/ /\ Filename : OBUF_F_16.v +// \ \ / \ Timestamp : Thu Mar 25 16:43:16 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. + +`timescale 1 ps / 1 ps + + +module OBUF_F_16 (O, I); + + output O; + + input I; + + tri0 GTS = glbl.GTS; + + bufif0 B1 (O, I, GTS); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUF_F_2.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUF_F_2.v new file mode 100644 index 0000000..1aa2e3f --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUF_F_2.v @@ -0,0 +1,35 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/OBUF_F_2.v,v 1.6 2007/05/23 21:43:40 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Output Buffer with Fast Slew 2 mA Drive +// /___/ /\ Filename : OBUF_F_2.v +// \ \ / \ Timestamp : Thu Mar 25 16:43:16 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. + +`timescale 1 ps / 1 ps + + +module OBUF_F_2 (O, I); + + output O; + + input I; + + tri0 GTS = glbl.GTS; + + bufif0 B1 (O, I, GTS); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUF_F_24.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUF_F_24.v new file mode 100644 index 0000000..9c31dc8 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUF_F_24.v @@ -0,0 +1,35 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/OBUF_F_24.v,v 1.6 2007/05/23 21:43:40 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Output Buffer with Fast Slew 24 mA Drive +// /___/ /\ Filename : OBUF_F_24.v +// \ \ / \ Timestamp : Thu Mar 25 16:43:16 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. + +`timescale 1 ps / 1 ps + + +module OBUF_F_24 (O, I); + + output O; + + input I; + + tri0 GTS = glbl.GTS; + + bufif0 B1 (O, I, GTS); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUF_F_4.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUF_F_4.v new file mode 100644 index 0000000..5ee1f8d --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUF_F_4.v @@ -0,0 +1,35 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/OBUF_F_4.v,v 1.6 2007/05/23 21:43:40 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Output Buffer with Fast Slew 4 mA Drive +// /___/ /\ Filename : OBUF_F_4.v +// \ \ / \ Timestamp : Thu Mar 25 16:43:17 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. + +`timescale 1 ps / 1 ps + + +module OBUF_F_4 (O, I); + + output O; + + input I; + + tri0 GTS = glbl.GTS; + + bufif0 B1 (O, I, GTS); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUF_F_6.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUF_F_6.v new file mode 100644 index 0000000..ee84106 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUF_F_6.v @@ -0,0 +1,35 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/OBUF_F_6.v,v 1.6 2007/05/23 21:43:40 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Output Buffer with Fast Slew 6 mA Drive +// /___/ /\ Filename : OBUF_F_6.v +// \ \ / \ Timestamp : Thu Mar 25 16:43:17 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. + +`timescale 1 ps / 1 ps + + +module OBUF_F_6 (O, I); + + output O; + + input I; + + tri0 GTS = glbl.GTS; + + bufif0 B1 (O, I, GTS); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUF_F_8.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUF_F_8.v new file mode 100644 index 0000000..cb36eee --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUF_F_8.v @@ -0,0 +1,35 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/OBUF_F_8.v,v 1.6 2007/05/23 21:43:40 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Output Buffer with Fast Slew 8 mA Drive +// /___/ /\ Filename : OBUF_F_8.v +// \ \ / \ Timestamp : Thu Mar 25 16:43:17 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. + +`timescale 1 ps / 1 ps + + +module OBUF_F_8 (O, I); + + output O; + + input I; + + tri0 GTS = glbl.GTS; + + bufif0 B1 (O, I, GTS); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUF_GTL.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUF_GTL.v new file mode 100644 index 0000000..c8b79b1 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUF_GTL.v @@ -0,0 +1,35 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/OBUF_GTL.v,v 1.6 2007/05/23 21:43:40 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Output Buffer with GTL I/O Standard +// /___/ /\ Filename : OBUF_GTL.v +// \ \ / \ Timestamp : Thu Mar 25 16:43:17 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. + +`timescale 1 ps / 1 ps + + +module OBUF_GTL (O, I); + + output O; + + input I; + + tri0 GTS = glbl.GTS; + + bufif0 B1 (O, I, GTS); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUF_GTLP.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUF_GTLP.v new file mode 100644 index 0000000..eb124b1 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUF_GTLP.v @@ -0,0 +1,35 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/OBUF_GTLP.v,v 1.6 2007/05/23 21:43:40 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Output Buffer with GTLP I/O Standard +// /___/ /\ Filename : OBUF_GTLP.v +// \ \ / \ Timestamp : Thu Mar 25 16:43:17 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. + +`timescale 1 ps / 1 ps + + +module OBUF_GTLP (O, I); + + output O; + + input I; + + tri0 GTS = glbl.GTS; + + bufif0 B1 (O, I, GTS); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUF_GTLP_DCI.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUF_GTLP_DCI.v new file mode 100644 index 0000000..9446d60 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUF_GTLP_DCI.v @@ -0,0 +1,35 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/OBUF_GTLP_DCI.v,v 1.6 2007/05/23 21:43:40 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Output Buffer with GTLP_DCI I/O Standard +// /___/ /\ Filename : OBUF_GTLP_DCI.v +// \ \ / \ Timestamp : Thu Mar 25 16:43:17 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. + +`timescale 1 ps / 1 ps + + +module OBUF_GTLP_DCI (O, I); + + output O; + + input I; + + tri0 GTS = glbl.GTS; + + bufif0 B1 (O, I, GTS); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUF_GTL_DCI.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUF_GTL_DCI.v new file mode 100644 index 0000000..bc486f5 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUF_GTL_DCI.v @@ -0,0 +1,35 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/OBUF_GTL_DCI.v,v 1.6 2007/05/23 21:43:40 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Output Buffer with GTL_DCI I/O Standard +// /___/ /\ Filename : OBUF_GTL_DCI.v +// \ \ / \ Timestamp : Thu Mar 25 16:43:17 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. + +`timescale 1 ps / 1 ps + + +module OBUF_GTL_DCI (O, I); + + output O; + + input I; + + tri0 GTS = glbl.GTS; + + bufif0 B1 (O, I, GTS); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUF_HSTL_I.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUF_HSTL_I.v new file mode 100644 index 0000000..afa1122 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUF_HSTL_I.v @@ -0,0 +1,35 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/OBUF_HSTL_I.v,v 1.6 2007/05/23 21:43:40 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Output Buffer with HSTL_I I/O Standard +// /___/ /\ Filename : OBUF_HSTL_I.v +// \ \ / \ Timestamp : Thu Mar 25 16:43:17 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. + +`timescale 1 ps / 1 ps + + +module OBUF_HSTL_I (O, I); + + output O; + + input I; + + tri0 GTS = glbl.GTS; + + bufif0 B1 (O, I, GTS); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUF_HSTL_II.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUF_HSTL_II.v new file mode 100644 index 0000000..e8ebf26 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUF_HSTL_II.v @@ -0,0 +1,35 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/OBUF_HSTL_II.v,v 1.6 2007/05/23 21:43:40 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Output Buffer with HSTL_II I/O Standard +// /___/ /\ Filename : OBUF_HSTL_II.v +// \ \ / \ Timestamp : Thu Mar 25 16:43:17 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. + +`timescale 1 ps / 1 ps + + +module OBUF_HSTL_II (O, I); + + output O; + + input I; + + tri0 GTS = glbl.GTS; + + bufif0 B1 (O, I, GTS); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUF_HSTL_III.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUF_HSTL_III.v new file mode 100644 index 0000000..8fbb941 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUF_HSTL_III.v @@ -0,0 +1,35 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/OBUF_HSTL_III.v,v 1.6 2007/05/23 21:43:40 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Output Buffer with HSTL_III I/O Standard +// /___/ /\ Filename : OBUF_HSTL_III.v +// \ \ / \ Timestamp : Thu Mar 25 16:43:17 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. + +`timescale 1 ps / 1 ps + + +module OBUF_HSTL_III (O, I); + + output O; + + input I; + + tri0 GTS = glbl.GTS; + + bufif0 B1 (O, I, GTS); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUF_HSTL_III_18.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUF_HSTL_III_18.v new file mode 100644 index 0000000..87e823f --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUF_HSTL_III_18.v @@ -0,0 +1,35 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/OBUF_HSTL_III_18.v,v 1.6 2007/05/23 21:43:40 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Output Buffer with HSTL_III_18 I/O Standard +// /___/ /\ Filename : OBUF_HSTL_III_18.v +// \ \ / \ Timestamp : Thu Mar 25 16:43:18 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. + +`timescale 1 ps / 1 ps + + +module OBUF_HSTL_III_18 (O, I); + + output O; + + input I; + + tri0 GTS = glbl.GTS; + + bufif0 B1 (O, I, GTS); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUF_HSTL_III_DCI.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUF_HSTL_III_DCI.v new file mode 100644 index 0000000..67a0557 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUF_HSTL_III_DCI.v @@ -0,0 +1,35 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/OBUF_HSTL_III_DCI.v,v 1.6 2007/05/23 21:43:40 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Output Buffer with HSTL_III_DCI I/O Standard +// /___/ /\ Filename : OBUF_HSTL_III_DCI.v +// \ \ / \ Timestamp : Thu Mar 25 16:43:18 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. + +`timescale 1 ps / 1 ps + + +module OBUF_HSTL_III_DCI (O, I); + + output O; + + input I; + + tri0 GTS = glbl.GTS; + + bufif0 B1 (O, I, GTS); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUF_HSTL_III_DCI_18.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUF_HSTL_III_DCI_18.v new file mode 100644 index 0000000..b503c21 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUF_HSTL_III_DCI_18.v @@ -0,0 +1,35 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/OBUF_HSTL_III_DCI_18.v,v 1.6 2007/05/23 21:43:40 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Output Buffer with HSTL_III_DCI_18 I/O Standard +// /___/ /\ Filename : OBUF_HSTL_III_DCI_18.v +// \ \ / \ Timestamp : Thu Mar 25 16:43:18 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. + +`timescale 1 ps / 1 ps + + +module OBUF_HSTL_III_DCI_18 (O, I); + + output O; + + input I; + + tri0 GTS = glbl.GTS; + + bufif0 B1 (O, I, GTS); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUF_HSTL_II_18.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUF_HSTL_II_18.v new file mode 100644 index 0000000..0e6482b --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUF_HSTL_II_18.v @@ -0,0 +1,35 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/OBUF_HSTL_II_18.v,v 1.6 2007/05/23 21:43:40 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Output Buffer with HSTL_II_18 I/O Standard +// /___/ /\ Filename : OBUF_HSTL_II_18.v +// \ \ / \ Timestamp : Thu Mar 25 16:43:18 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. + +`timescale 1 ps / 1 ps + + +module OBUF_HSTL_II_18 (O, I); + + output O; + + input I; + + tri0 GTS = glbl.GTS; + + bufif0 B1 (O, I, GTS); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUF_HSTL_II_DCI.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUF_HSTL_II_DCI.v new file mode 100644 index 0000000..ba1d202 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUF_HSTL_II_DCI.v @@ -0,0 +1,35 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/OBUF_HSTL_II_DCI.v,v 1.6 2007/05/23 21:43:40 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Output Buffer with HSTL_II_DCI I/O Standard +// /___/ /\ Filename : OBUF_HSTL_II_DCI.v +// \ \ / \ Timestamp : Thu Mar 25 16:43:18 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. + +`timescale 1 ps / 1 ps + + +module OBUF_HSTL_II_DCI (O, I); + + output O; + + input I; + + tri0 GTS = glbl.GTS; + + bufif0 B1 (O, I, GTS); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUF_HSTL_II_DCI_18.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUF_HSTL_II_DCI_18.v new file mode 100644 index 0000000..6119cd5 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUF_HSTL_II_DCI_18.v @@ -0,0 +1,35 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/OBUF_HSTL_II_DCI_18.v,v 1.6 2007/05/23 21:43:40 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Output Buffer with HSTL_II_DCI_18 I/O Standard +// /___/ /\ Filename : OBUF_HSTL_II_DCI_18.v +// \ \ / \ Timestamp : Thu Mar 25 16:43:18 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. + +`timescale 1 ps / 1 ps + + +module OBUF_HSTL_II_DCI_18 (O, I); + + output O; + + input I; + + tri0 GTS = glbl.GTS; + + bufif0 B1 (O, I, GTS); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUF_HSTL_IV.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUF_HSTL_IV.v new file mode 100644 index 0000000..6b98c95 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUF_HSTL_IV.v @@ -0,0 +1,35 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/OBUF_HSTL_IV.v,v 1.6 2007/05/23 21:43:40 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Output Buffer with HSTL_IV I/O Standard +// /___/ /\ Filename : OBUF_HSTL_IV.v +// \ \ / \ Timestamp : Thu Mar 25 16:43:18 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. + +`timescale 1 ps / 1 ps + + +module OBUF_HSTL_IV (O, I); + + output O; + + input I; + + tri0 GTS = glbl.GTS; + + bufif0 B1 (O, I, GTS); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUF_HSTL_IV_18.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUF_HSTL_IV_18.v new file mode 100644 index 0000000..5b7b1da --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUF_HSTL_IV_18.v @@ -0,0 +1,35 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/OBUF_HSTL_IV_18.v,v 1.6 2007/05/23 21:43:40 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Output Buffer with HSTL_IV_18 I/O Standard +// /___/ /\ Filename : OBUF_HSTL_IV_18.v +// \ \ / \ Timestamp : Thu Mar 25 16:43:18 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. + +`timescale 1 ps / 1 ps + + +module OBUF_HSTL_IV_18 (O, I); + + output O; + + input I; + + tri0 GTS = glbl.GTS; + + bufif0 B1 (O, I, GTS); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUF_HSTL_IV_DCI.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUF_HSTL_IV_DCI.v new file mode 100644 index 0000000..edab195 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUF_HSTL_IV_DCI.v @@ -0,0 +1,35 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/OBUF_HSTL_IV_DCI.v,v 1.6 2007/05/23 21:43:40 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Output Buffer with HSTL_IV_DCI I/O Standard +// /___/ /\ Filename : OBUF_HSTL_IV_DCI.v +// \ \ / \ Timestamp : Thu Mar 25 16:43:18 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. + +`timescale 1 ps / 1 ps + + +module OBUF_HSTL_IV_DCI (O, I); + + output O; + + input I; + + tri0 GTS = glbl.GTS; + + bufif0 B1 (O, I, GTS); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUF_HSTL_IV_DCI_18.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUF_HSTL_IV_DCI_18.v new file mode 100644 index 0000000..2a0ce51 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUF_HSTL_IV_DCI_18.v @@ -0,0 +1,35 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/OBUF_HSTL_IV_DCI_18.v,v 1.6 2007/05/23 21:43:40 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Output Buffer with HSTL_IV_DCI_18 I/O Standard +// /___/ /\ Filename : OBUF_HSTL_IV_DCI_18.v +// \ \ / \ Timestamp : Thu Mar 25 16:43:18 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. + +`timescale 1 ps / 1 ps + + +module OBUF_HSTL_IV_DCI_18 (O, I); + + output O; + + input I; + + tri0 GTS = glbl.GTS; + + bufif0 B1 (O, I, GTS); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUF_HSTL_I_18.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUF_HSTL_I_18.v new file mode 100644 index 0000000..4ce2fe1 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUF_HSTL_I_18.v @@ -0,0 +1,35 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/OBUF_HSTL_I_18.v,v 1.6 2007/05/23 21:43:40 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Output Buffer with HSTL_I_18 I/O Standard +// /___/ /\ Filename : OBUF_HSTL_I_18.v +// \ \ / \ Timestamp : Thu Mar 25 16:43:19 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. + +`timescale 1 ps / 1 ps + + +module OBUF_HSTL_I_18 (O, I); + + output O; + + input I; + + tri0 GTS = glbl.GTS; + + bufif0 B1 (O, I, GTS); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUF_HSTL_I_DCI.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUF_HSTL_I_DCI.v new file mode 100644 index 0000000..99b2c7c --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUF_HSTL_I_DCI.v @@ -0,0 +1,35 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/OBUF_HSTL_I_DCI.v,v 1.6 2007/05/23 21:43:40 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Output Buffer with HSTL_I_DCI I/O Standard +// /___/ /\ Filename : OBUF_HSTL_I_DCI.v +// \ \ / \ Timestamp : Thu Mar 25 16:43:19 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. + +`timescale 1 ps / 1 ps + + +module OBUF_HSTL_I_DCI (O, I); + + output O; + + input I; + + tri0 GTS = glbl.GTS; + + bufif0 B1 (O, I, GTS); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUF_HSTL_I_DCI_18.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUF_HSTL_I_DCI_18.v new file mode 100644 index 0000000..de7e756 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUF_HSTL_I_DCI_18.v @@ -0,0 +1,35 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/OBUF_HSTL_I_DCI_18.v,v 1.6 2007/05/23 21:43:40 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Output Buffer with HSTL_I_DCI_18 I/O Standard +// /___/ /\ Filename : OBUF_HSTL_I_DCI_18.v +// \ \ / \ Timestamp : Thu Mar 25 16:43:19 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. + +`timescale 1 ps / 1 ps + + +module OBUF_HSTL_I_DCI_18 (O, I); + + output O; + + input I; + + tri0 GTS = glbl.GTS; + + bufif0 B1 (O, I, GTS); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUF_LVCMOS12.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUF_LVCMOS12.v new file mode 100644 index 0000000..26f5f87 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUF_LVCMOS12.v @@ -0,0 +1,35 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/OBUF_LVCMOS12.v,v 1.6 2007/05/23 21:43:40 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Output Buffer with LVCMOS12 I/O Standard +// /___/ /\ Filename : OBUF_LVCMOS12.v +// \ \ / \ Timestamp : Thu Mar 25 16:43:19 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. + +`timescale 1 ps / 1 ps + + +module OBUF_LVCMOS12 (O, I); + + output O; + + input I; + + tri0 GTS = glbl.GTS; + + bufif0 B1 (O, I, GTS); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUF_LVCMOS12_F_2.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUF_LVCMOS12_F_2.v new file mode 100644 index 0000000..60fde8a --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUF_LVCMOS12_F_2.v @@ -0,0 +1,35 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/OBUF_LVCMOS12_F_2.v,v 1.6 2007/05/23 21:43:40 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Output Buffer with LVCMOS12 I/O Standard Fast Slew 2 mA Drive +// /___/ /\ Filename : OBUF_LVCMOS12_F_2.v +// \ \ / \ Timestamp : Thu Mar 25 16:43:19 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. + +`timescale 1 ps / 1 ps + + +module OBUF_LVCMOS12_F_2 (O, I); + + output O; + + input I; + + tri0 GTS = glbl.GTS; + + bufif0 B1 (O, I, GTS); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUF_LVCMOS12_F_4.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUF_LVCMOS12_F_4.v new file mode 100644 index 0000000..cd6feb6 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUF_LVCMOS12_F_4.v @@ -0,0 +1,35 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/OBUF_LVCMOS12_F_4.v,v 1.6 2007/05/23 21:43:40 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Output Buffer with LVCMOS12 I/O Standard Fast Slew 4 mA Drive +// /___/ /\ Filename : OBUF_LVCMOS12_F_4.v +// \ \ / \ Timestamp : Thu Mar 25 16:43:19 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. + +`timescale 1 ps / 1 ps + + +module OBUF_LVCMOS12_F_4 (O, I); + + output O; + + input I; + + tri0 GTS = glbl.GTS; + + bufif0 B1 (O, I, GTS); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUF_LVCMOS12_F_6.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUF_LVCMOS12_F_6.v new file mode 100644 index 0000000..f6c0cab --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUF_LVCMOS12_F_6.v @@ -0,0 +1,35 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/OBUF_LVCMOS12_F_6.v,v 1.6 2007/05/23 21:43:40 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Output Buffer with LVCMOS12 I/O Standard Fast Slew 6 mA Drive +// /___/ /\ Filename : OBUF_LVCMOS12_F_6.v +// \ \ / \ Timestamp : Thu Mar 25 16:43:19 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. + +`timescale 1 ps / 1 ps + + +module OBUF_LVCMOS12_F_6 (O, I); + + output O; + + input I; + + tri0 GTS = glbl.GTS; + + bufif0 B1 (O, I, GTS); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUF_LVCMOS12_F_8.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUF_LVCMOS12_F_8.v new file mode 100644 index 0000000..890a3f2 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUF_LVCMOS12_F_8.v @@ -0,0 +1,35 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/OBUF_LVCMOS12_F_8.v,v 1.6 2007/05/23 21:43:40 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Output Buffer with LVCMOS12 I/O Standard Fast Slew 8 mA Drive +// /___/ /\ Filename : OBUF_LVCMOS12_F_8.v +// \ \ / \ Timestamp : Thu Mar 25 16:43:19 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. + +`timescale 1 ps / 1 ps + + +module OBUF_LVCMOS12_F_8 (O, I); + + output O; + + input I; + + tri0 GTS = glbl.GTS; + + bufif0 B1 (O, I, GTS); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUF_LVCMOS12_S_2.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUF_LVCMOS12_S_2.v new file mode 100644 index 0000000..751cedb --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUF_LVCMOS12_S_2.v @@ -0,0 +1,35 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/OBUF_LVCMOS12_S_2.v,v 1.6 2007/05/23 21:43:40 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Output Buffer with LVCMOS12 I/O Standard Slow Slew 2 mA Drive +// /___/ /\ Filename : OBUF_LVCMOS12_S_2.v +// \ \ / \ Timestamp : Thu Mar 25 16:43:19 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. + +`timescale 1 ps / 1 ps + + +module OBUF_LVCMOS12_S_2 (O, I); + + output O; + + input I; + + tri0 GTS = glbl.GTS; + + bufif0 B1 (O, I, GTS); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUF_LVCMOS12_S_4.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUF_LVCMOS12_S_4.v new file mode 100644 index 0000000..85b602e --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUF_LVCMOS12_S_4.v @@ -0,0 +1,35 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/OBUF_LVCMOS12_S_4.v,v 1.6 2007/05/23 21:43:40 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Output Buffer with LVCMOS12 I/O Standard Slow Slew 4 mA Drive +// /___/ /\ Filename : OBUF_LVCMOS12_S_4.v +// \ \ / \ Timestamp : Thu Mar 25 16:43:19 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. + +`timescale 1 ps / 1 ps + + +module OBUF_LVCMOS12_S_4 (O, I); + + output O; + + input I; + + tri0 GTS = glbl.GTS; + + bufif0 B1 (O, I, GTS); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUF_LVCMOS12_S_6.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUF_LVCMOS12_S_6.v new file mode 100644 index 0000000..0232cc1 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUF_LVCMOS12_S_6.v @@ -0,0 +1,35 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/OBUF_LVCMOS12_S_6.v,v 1.6 2007/05/23 21:43:40 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Output Buffer with LVCMOS12 I/O Standard Slow Slew 6 mA Drive +// /___/ /\ Filename : OBUF_LVCMOS12_S_6.v +// \ \ / \ Timestamp : Thu Mar 25 16:43:20 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. + +`timescale 1 ps / 1 ps + + +module OBUF_LVCMOS12_S_6 (O, I); + + output O; + + input I; + + tri0 GTS = glbl.GTS; + + bufif0 B1 (O, I, GTS); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUF_LVCMOS12_S_8.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUF_LVCMOS12_S_8.v new file mode 100644 index 0000000..5d33971 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUF_LVCMOS12_S_8.v @@ -0,0 +1,35 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/OBUF_LVCMOS12_S_8.v,v 1.6 2007/05/23 21:43:40 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Output Buffer with LVCMOS12 I/O Standard Slow Slew 8 mA Drive +// /___/ /\ Filename : OBUF_LVCMOS12_S_8.v +// \ \ / \ Timestamp : Thu Mar 25 16:43:20 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. + +`timescale 1 ps / 1 ps + + +module OBUF_LVCMOS12_S_8 (O, I); + + output O; + + input I; + + tri0 GTS = glbl.GTS; + + bufif0 B1 (O, I, GTS); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUF_LVCMOS15.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUF_LVCMOS15.v new file mode 100644 index 0000000..97169d5 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUF_LVCMOS15.v @@ -0,0 +1,35 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/OBUF_LVCMOS15.v,v 1.6 2007/05/23 21:43:40 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Output Buffer with LVCMOS15 I/O Standard +// /___/ /\ Filename : OBUF_LVCMOS15.v +// \ \ / \ Timestamp : Thu Mar 25 16:43:20 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. + +`timescale 1 ps / 1 ps + + +module OBUF_LVCMOS15 (O, I); + + output O; + + input I; + + tri0 GTS = glbl.GTS; + + bufif0 B1 (O, I, GTS); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUF_LVCMOS15_F_12.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUF_LVCMOS15_F_12.v new file mode 100644 index 0000000..590f249 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUF_LVCMOS15_F_12.v @@ -0,0 +1,35 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/OBUF_LVCMOS15_F_12.v,v 1.6 2007/05/23 21:43:40 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Output Buffer with LVCMOS15 I/O Standard Fast Slew 12 mA Drive +// /___/ /\ Filename : OBUF_LVCMOS15_F_12.v +// \ \ / \ Timestamp : Thu Mar 25 16:43:20 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. + +`timescale 1 ps / 1 ps + + +module OBUF_LVCMOS15_F_12 (O, I); + + output O; + + input I; + + tri0 GTS = glbl.GTS; + + bufif0 B1 (O, I, GTS); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUF_LVCMOS15_F_16.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUF_LVCMOS15_F_16.v new file mode 100644 index 0000000..d560549 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUF_LVCMOS15_F_16.v @@ -0,0 +1,35 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/OBUF_LVCMOS15_F_16.v,v 1.6 2007/05/23 21:43:40 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Output Buffer with LVCMOS15 I/O Standard Fast Slew 16 mA Drive +// /___/ /\ Filename : OBUF_LVCMOS15_F_16.v +// \ \ / \ Timestamp : Thu Mar 25 16:43:20 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. + +`timescale 1 ps / 1 ps + + +module OBUF_LVCMOS15_F_16 (O, I); + + output O; + + input I; + + tri0 GTS = glbl.GTS; + + bufif0 B1 (O, I, GTS); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUF_LVCMOS15_F_2.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUF_LVCMOS15_F_2.v new file mode 100644 index 0000000..282cb4a --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUF_LVCMOS15_F_2.v @@ -0,0 +1,35 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/OBUF_LVCMOS15_F_2.v,v 1.6 2007/05/23 21:43:40 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Output Buffer with LVCMOS15 I/O Standard Fast Slew 2 mA Drive +// /___/ /\ Filename : OBUF_LVCMOS15_F_2.v +// \ \ / \ Timestamp : Thu Mar 25 16:43:20 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. + +`timescale 1 ps / 1 ps + + +module OBUF_LVCMOS15_F_2 (O, I); + + output O; + + input I; + + tri0 GTS = glbl.GTS; + + bufif0 B1 (O, I, GTS); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUF_LVCMOS15_F_4.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUF_LVCMOS15_F_4.v new file mode 100644 index 0000000..fe87b32 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUF_LVCMOS15_F_4.v @@ -0,0 +1,35 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/OBUF_LVCMOS15_F_4.v,v 1.6 2007/05/23 21:43:40 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Output Buffer with LVCMOS15 I/O Standard Fast Slew 4 mA Drive +// /___/ /\ Filename : OBUF_LVCMOS15_F_4.v +// \ \ / \ Timestamp : Thu Mar 25 16:43:20 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. + +`timescale 1 ps / 1 ps + + +module OBUF_LVCMOS15_F_4 (O, I); + + output O; + + input I; + + tri0 GTS = glbl.GTS; + + bufif0 B1 (O, I, GTS); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUF_LVCMOS15_F_6.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUF_LVCMOS15_F_6.v new file mode 100644 index 0000000..0e2634d --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUF_LVCMOS15_F_6.v @@ -0,0 +1,35 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/OBUF_LVCMOS15_F_6.v,v 1.6 2007/05/23 21:43:40 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Output Buffer with LVCMOS15 I/O Standard Fast Slew 6 mA Drive +// /___/ /\ Filename : OBUF_LVCMOS15_F_6.v +// \ \ / \ Timestamp : Thu Mar 25 16:43:20 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. + +`timescale 1 ps / 1 ps + + +module OBUF_LVCMOS15_F_6 (O, I); + + output O; + + input I; + + tri0 GTS = glbl.GTS; + + bufif0 B1 (O, I, GTS); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUF_LVCMOS15_F_8.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUF_LVCMOS15_F_8.v new file mode 100644 index 0000000..4ce7ac8 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUF_LVCMOS15_F_8.v @@ -0,0 +1,35 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/OBUF_LVCMOS15_F_8.v,v 1.6 2007/05/23 21:43:40 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Output Buffer with LVCMOS15 I/O Standard Fast Slew 8 mA Drive +// /___/ /\ Filename : OBUF_LVCMOS15_F_8.v +// \ \ / \ Timestamp : Thu Mar 25 16:43:20 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. + +`timescale 1 ps / 1 ps + + +module OBUF_LVCMOS15_F_8 (O, I); + + output O; + + input I; + + tri0 GTS = glbl.GTS; + + bufif0 B1 (O, I, GTS); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUF_LVCMOS15_S_12.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUF_LVCMOS15_S_12.v new file mode 100644 index 0000000..a4b1f15 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUF_LVCMOS15_S_12.v @@ -0,0 +1,35 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/OBUF_LVCMOS15_S_12.v,v 1.6 2007/05/23 21:43:40 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Output Buffer with LVCMOS15 I/O Standard Slow Slew 12 mA Drive +// /___/ /\ Filename : OBUF_LVCMOS15_S_12.v +// \ \ / \ Timestamp : Thu Mar 25 16:43:20 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. + +`timescale 1 ps / 1 ps + + +module OBUF_LVCMOS15_S_12 (O, I); + + output O; + + input I; + + tri0 GTS = glbl.GTS; + + bufif0 B1 (O, I, GTS); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUF_LVCMOS15_S_16.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUF_LVCMOS15_S_16.v new file mode 100644 index 0000000..18232d8 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUF_LVCMOS15_S_16.v @@ -0,0 +1,35 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/OBUF_LVCMOS15_S_16.v,v 1.6 2007/05/23 21:43:40 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Output Buffer with LVCMOS15 I/O Standard Slow Slew 16 mA Drive +// /___/ /\ Filename : OBUF_LVCMOS15_S_16.v +// \ \ / \ Timestamp : Thu Mar 25 16:43:20 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. + +`timescale 1 ps / 1 ps + + +module OBUF_LVCMOS15_S_16 (O, I); + + output O; + + input I; + + tri0 GTS = glbl.GTS; + + bufif0 B1 (O, I, GTS); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUF_LVCMOS15_S_2.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUF_LVCMOS15_S_2.v new file mode 100644 index 0000000..d5e32c0 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUF_LVCMOS15_S_2.v @@ -0,0 +1,35 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/OBUF_LVCMOS15_S_2.v,v 1.6 2007/05/23 21:43:40 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Output Buffer with LVCMOS15 I/O Standard Slow Slew 2 mA Drive +// /___/ /\ Filename : OBUF_LVCMOS15_S_2.v +// \ \ / \ Timestamp : Thu Mar 25 16:43:21 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. + +`timescale 1 ps / 1 ps + + +module OBUF_LVCMOS15_S_2 (O, I); + + output O; + + input I; + + tri0 GTS = glbl.GTS; + + bufif0 B1 (O, I, GTS); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUF_LVCMOS15_S_4.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUF_LVCMOS15_S_4.v new file mode 100644 index 0000000..b7c9aa3 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUF_LVCMOS15_S_4.v @@ -0,0 +1,35 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/OBUF_LVCMOS15_S_4.v,v 1.6 2007/05/23 21:43:40 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Output Buffer with LVCMOS15 I/O Standard Slow Slew 4 mA Drive +// /___/ /\ Filename : OBUF_LVCMOS15_S_4.v +// \ \ / \ Timestamp : Thu Mar 25 16:43:21 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. + +`timescale 1 ps / 1 ps + + +module OBUF_LVCMOS15_S_4 (O, I); + + output O; + + input I; + + tri0 GTS = glbl.GTS; + + bufif0 B1 (O, I, GTS); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUF_LVCMOS15_S_6.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUF_LVCMOS15_S_6.v new file mode 100644 index 0000000..a4f5f7b --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUF_LVCMOS15_S_6.v @@ -0,0 +1,35 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/OBUF_LVCMOS15_S_6.v,v 1.6 2007/05/23 21:43:40 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Output Buffer with LVCMOS15 I/O Standard Slow Slew 6 mA Drive +// /___/ /\ Filename : OBUF_LVCMOS15_S_6.v +// \ \ / \ Timestamp : Thu Mar 25 16:43:21 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. + +`timescale 1 ps / 1 ps + + +module OBUF_LVCMOS15_S_6 (O, I); + + output O; + + input I; + + tri0 GTS = glbl.GTS; + + bufif0 B1 (O, I, GTS); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUF_LVCMOS15_S_8.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUF_LVCMOS15_S_8.v new file mode 100644 index 0000000..2649732 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUF_LVCMOS15_S_8.v @@ -0,0 +1,35 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/OBUF_LVCMOS15_S_8.v,v 1.6 2007/05/23 21:43:40 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Output Buffer with LVCMOS15 I/O Standard Slow Slew 8 mA Drive +// /___/ /\ Filename : OBUF_LVCMOS15_S_8.v +// \ \ / \ Timestamp : Thu Mar 25 16:43:21 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. + +`timescale 1 ps / 1 ps + + +module OBUF_LVCMOS15_S_8 (O, I); + + output O; + + input I; + + tri0 GTS = glbl.GTS; + + bufif0 B1 (O, I, GTS); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUF_LVCMOS18.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUF_LVCMOS18.v new file mode 100644 index 0000000..33d2b89 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUF_LVCMOS18.v @@ -0,0 +1,35 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/OBUF_LVCMOS18.v,v 1.6 2007/05/23 21:43:40 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Output Buffer with LVCMOS18 I/O Standard +// /___/ /\ Filename : OBUF_LVCMOS18.v +// \ \ / \ Timestamp : Thu Mar 25 16:43:21 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. + +`timescale 1 ps / 1 ps + + +module OBUF_LVCMOS18 (O, I); + + output O; + + input I; + + tri0 GTS = glbl.GTS; + + bufif0 B1 (O, I, GTS); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUF_LVCMOS18_F_12.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUF_LVCMOS18_F_12.v new file mode 100644 index 0000000..4f2878f --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUF_LVCMOS18_F_12.v @@ -0,0 +1,35 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/OBUF_LVCMOS18_F_12.v,v 1.6 2007/05/23 21:43:40 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Output Buffer with LVCMOS18 I/O Standard Fast Slew 12 mA Drive +// /___/ /\ Filename : OBUF_LVCMOS18_F_12.v +// \ \ / \ Timestamp : Thu Mar 25 16:43:21 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. + +`timescale 1 ps / 1 ps + + +module OBUF_LVCMOS18_F_12 (O, I); + + output O; + + input I; + + tri0 GTS = glbl.GTS; + + bufif0 B1 (O, I, GTS); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUF_LVCMOS18_F_16.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUF_LVCMOS18_F_16.v new file mode 100644 index 0000000..a0a19be --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUF_LVCMOS18_F_16.v @@ -0,0 +1,35 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/OBUF_LVCMOS18_F_16.v,v 1.6 2007/05/23 21:43:40 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Output Buffer with LVCMOS18 I/O Standard Fast Slew 16 mA Drive +// /___/ /\ Filename : OBUF_LVCMOS18_F_16.v +// \ \ / \ Timestamp : Thu Mar 25 16:43:21 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. + +`timescale 1 ps / 1 ps + + +module OBUF_LVCMOS18_F_16 (O, I); + + output O; + + input I; + + tri0 GTS = glbl.GTS; + + bufif0 B1 (O, I, GTS); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUF_LVCMOS18_F_2.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUF_LVCMOS18_F_2.v new file mode 100644 index 0000000..a33c672 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUF_LVCMOS18_F_2.v @@ -0,0 +1,35 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/OBUF_LVCMOS18_F_2.v,v 1.6 2007/05/23 21:43:40 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Output Buffer with LVCMOS18 I/O Standard Fast Slew 2 mA Drive +// /___/ /\ Filename : OBUF_LVCMOS18_F_2.v +// \ \ / \ Timestamp : Thu Mar 25 16:43:21 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. + +`timescale 1 ps / 1 ps + + +module OBUF_LVCMOS18_F_2 (O, I); + + output O; + + input I; + + tri0 GTS = glbl.GTS; + + bufif0 B1 (O, I, GTS); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUF_LVCMOS18_F_4.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUF_LVCMOS18_F_4.v new file mode 100644 index 0000000..069650a --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUF_LVCMOS18_F_4.v @@ -0,0 +1,35 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/OBUF_LVCMOS18_F_4.v,v 1.6 2007/05/23 21:43:40 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Output Buffer with LVCMOS18 I/O Standard Fast Slew 4 mA Drive +// /___/ /\ Filename : OBUF_LVCMOS18_F_4.v +// \ \ / \ Timestamp : Thu Mar 25 16:43:21 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. + +`timescale 1 ps / 1 ps + + +module OBUF_LVCMOS18_F_4 (O, I); + + output O; + + input I; + + tri0 GTS = glbl.GTS; + + bufif0 B1 (O, I, GTS); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUF_LVCMOS18_F_6.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUF_LVCMOS18_F_6.v new file mode 100644 index 0000000..771ad4e --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUF_LVCMOS18_F_6.v @@ -0,0 +1,35 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/OBUF_LVCMOS18_F_6.v,v 1.6 2007/05/23 21:43:40 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Output Buffer with LVCMOS18 I/O Standard Fast Slew 6 mA Drive +// /___/ /\ Filename : OBUF_LVCMOS18_F_6.v +// \ \ / \ Timestamp : Thu Mar 25 16:43:21 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. + +`timescale 1 ps / 1 ps + + +module OBUF_LVCMOS18_F_6 (O, I); + + output O; + + input I; + + tri0 GTS = glbl.GTS; + + bufif0 B1 (O, I, GTS); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUF_LVCMOS18_F_8.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUF_LVCMOS18_F_8.v new file mode 100644 index 0000000..e916c98 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUF_LVCMOS18_F_8.v @@ -0,0 +1,35 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/OBUF_LVCMOS18_F_8.v,v 1.6 2007/05/23 21:43:40 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Output Buffer with LVCMOS18 I/O Standard Fast Slew 8 mA Drive +// /___/ /\ Filename : OBUF_LVCMOS18_F_8.v +// \ \ / \ Timestamp : Thu Mar 25 16:43:22 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. + +`timescale 1 ps / 1 ps + + +module OBUF_LVCMOS18_F_8 (O, I); + + output O; + + input I; + + tri0 GTS = glbl.GTS; + + bufif0 B1 (O, I, GTS); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUF_LVCMOS18_S_12.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUF_LVCMOS18_S_12.v new file mode 100644 index 0000000..155b7d5 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUF_LVCMOS18_S_12.v @@ -0,0 +1,35 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/OBUF_LVCMOS18_S_12.v,v 1.6 2007/05/23 21:43:40 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Output Buffer with LVCMOS18 I/O Standard Slow Slew 12 mA Drive +// /___/ /\ Filename : OBUF_LVCMOS18_S_12.v +// \ \ / \ Timestamp : Thu Mar 25 16:43:22 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. + +`timescale 1 ps / 1 ps + + +module OBUF_LVCMOS18_S_12 (O, I); + + output O; + + input I; + + tri0 GTS = glbl.GTS; + + bufif0 B1 (O, I, GTS); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUF_LVCMOS18_S_16.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUF_LVCMOS18_S_16.v new file mode 100644 index 0000000..b539476 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUF_LVCMOS18_S_16.v @@ -0,0 +1,35 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/OBUF_LVCMOS18_S_16.v,v 1.6 2007/05/23 21:43:40 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Output Buffer with LVCMOS18 I/O Standard Slow Slew 16 mA Drive +// /___/ /\ Filename : OBUF_LVCMOS18_S_16.v +// \ \ / \ Timestamp : Thu Mar 25 16:43:22 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. + +`timescale 1 ps / 1 ps + + +module OBUF_LVCMOS18_S_16 (O, I); + + output O; + + input I; + + tri0 GTS = glbl.GTS; + + bufif0 B1 (O, I, GTS); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUF_LVCMOS18_S_2.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUF_LVCMOS18_S_2.v new file mode 100644 index 0000000..344853d --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUF_LVCMOS18_S_2.v @@ -0,0 +1,35 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/OBUF_LVCMOS18_S_2.v,v 1.6 2007/05/23 21:43:40 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Output Buffer with LVCMOS18 I/O Standard Slow Slew 2 mA Drive +// /___/ /\ Filename : OBUF_LVCMOS18_S_2.v +// \ \ / \ Timestamp : Thu Mar 25 16:43:22 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. + +`timescale 1 ps / 1 ps + + +module OBUF_LVCMOS18_S_2 (O, I); + + output O; + + input I; + + tri0 GTS = glbl.GTS; + + bufif0 B1 (O, I, GTS); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUF_LVCMOS18_S_4.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUF_LVCMOS18_S_4.v new file mode 100644 index 0000000..8b8fb8a --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUF_LVCMOS18_S_4.v @@ -0,0 +1,35 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/OBUF_LVCMOS18_S_4.v,v 1.6 2007/05/23 21:43:40 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Output Buffer with LVCMOS18 I/O Standard Slow Slew 4 mA Drive +// /___/ /\ Filename : OBUF_LVCMOS18_S_4.v +// \ \ / \ Timestamp : Thu Mar 25 16:43:22 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. + +`timescale 1 ps / 1 ps + + +module OBUF_LVCMOS18_S_4 (O, I); + + output O; + + input I; + + tri0 GTS = glbl.GTS; + + bufif0 B1 (O, I, GTS); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUF_LVCMOS18_S_6.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUF_LVCMOS18_S_6.v new file mode 100644 index 0000000..7957111 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUF_LVCMOS18_S_6.v @@ -0,0 +1,35 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/OBUF_LVCMOS18_S_6.v,v 1.6 2007/05/23 21:43:40 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Output Buffer with LVCMOS18 I/O Standard Slow Slew 6 mA Drive +// /___/ /\ Filename : OBUF_LVCMOS18_S_6.v +// \ \ / \ Timestamp : Thu Mar 25 16:43:22 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. + +`timescale 1 ps / 1 ps + + +module OBUF_LVCMOS18_S_6 (O, I); + + output O; + + input I; + + tri0 GTS = glbl.GTS; + + bufif0 B1 (O, I, GTS); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUF_LVCMOS18_S_8.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUF_LVCMOS18_S_8.v new file mode 100644 index 0000000..281d4a6 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUF_LVCMOS18_S_8.v @@ -0,0 +1,35 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/OBUF_LVCMOS18_S_8.v,v 1.6 2007/05/23 21:43:40 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Output Buffer with LVCMOS18 I/O Standard Slow Slew 8 mA Drive +// /___/ /\ Filename : OBUF_LVCMOS18_S_8.v +// \ \ / \ Timestamp : Thu Mar 25 16:43:22 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. + +`timescale 1 ps / 1 ps + + +module OBUF_LVCMOS18_S_8 (O, I); + + output O; + + input I; + + tri0 GTS = glbl.GTS; + + bufif0 B1 (O, I, GTS); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUF_LVCMOS2.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUF_LVCMOS2.v new file mode 100644 index 0000000..85667a0 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUF_LVCMOS2.v @@ -0,0 +1,35 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/OBUF_LVCMOS2.v,v 1.6 2007/05/23 21:43:41 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Output Buffer with LVCMOS2 I/O Standard +// /___/ /\ Filename : OBUF_LVCMOS2.v +// \ \ / \ Timestamp : Thu Mar 25 16:43:22 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. + +`timescale 1 ps / 1 ps + + +module OBUF_LVCMOS2 (O, I); + + output O; + + input I; + + tri0 GTS = glbl.GTS; + + bufif0 B1 (O, I, GTS); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUF_LVCMOS25.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUF_LVCMOS25.v new file mode 100644 index 0000000..91f8575 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUF_LVCMOS25.v @@ -0,0 +1,35 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/OBUF_LVCMOS25.v,v 1.6 2007/05/23 21:43:41 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Output Buffer with LVCMOS25 I/O Standard +// /___/ /\ Filename : OBUF_LVCMOS25.v +// \ \ / \ Timestamp : Thu Mar 25 16:43:22 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. + +`timescale 1 ps / 1 ps + + +module OBUF_LVCMOS25 (O, I); + + output O; + + input I; + + tri0 GTS = glbl.GTS; + + bufif0 B1 (O, I, GTS); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUF_LVCMOS25_F_12.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUF_LVCMOS25_F_12.v new file mode 100644 index 0000000..804a6e0 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUF_LVCMOS25_F_12.v @@ -0,0 +1,35 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/OBUF_LVCMOS25_F_12.v,v 1.6 2007/05/23 21:43:41 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Output Buffer with LVCMOS25 I/O Standard Fast Slew 12 mA Drive +// /___/ /\ Filename : OBUF_LVCMOS25_F_12.v +// \ \ / \ Timestamp : Thu Mar 25 16:43:22 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. + +`timescale 1 ps / 1 ps + + +module OBUF_LVCMOS25_F_12 (O, I); + + output O; + + input I; + + tri0 GTS = glbl.GTS; + + bufif0 B1 (O, I, GTS); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUF_LVCMOS25_F_16.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUF_LVCMOS25_F_16.v new file mode 100644 index 0000000..eba30de --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUF_LVCMOS25_F_16.v @@ -0,0 +1,35 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/OBUF_LVCMOS25_F_16.v,v 1.6 2007/05/23 21:43:41 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Output Buffer with LVCMOS25 I/O Standard Fast Slew 16 mA Drive +// /___/ /\ Filename : OBUF_LVCMOS25_F_16.v +// \ \ / \ Timestamp : Thu Mar 25 16:43:22 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. + +`timescale 1 ps / 1 ps + + +module OBUF_LVCMOS25_F_16 (O, I); + + output O; + + input I; + + tri0 GTS = glbl.GTS; + + bufif0 B1 (O, I, GTS); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUF_LVCMOS25_F_2.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUF_LVCMOS25_F_2.v new file mode 100644 index 0000000..3c94f67 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUF_LVCMOS25_F_2.v @@ -0,0 +1,35 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/OBUF_LVCMOS25_F_2.v,v 1.6 2007/05/23 21:43:41 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Output Buffer with LVCMOS25 I/O Standard Fast Slew 2 mA Drive +// /___/ /\ Filename : OBUF_LVCMOS25_F_2.v +// \ \ / \ Timestamp : Thu Mar 25 16:43:23 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. + +`timescale 1 ps / 1 ps + + +module OBUF_LVCMOS25_F_2 (O, I); + + output O; + + input I; + + tri0 GTS = glbl.GTS; + + bufif0 B1 (O, I, GTS); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUF_LVCMOS25_F_24.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUF_LVCMOS25_F_24.v new file mode 100644 index 0000000..3230fb9 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUF_LVCMOS25_F_24.v @@ -0,0 +1,35 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/OBUF_LVCMOS25_F_24.v,v 1.6 2007/05/23 21:43:41 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Output Buffer with LVCMOS25 I/O Standard Fast Slew 24 mA Drive +// /___/ /\ Filename : OBUF_LVCMOS25_F_24.v +// \ \ / \ Timestamp : Thu Mar 25 16:43:23 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. + +`timescale 1 ps / 1 ps + + +module OBUF_LVCMOS25_F_24 (O, I); + + output O; + + input I; + + tri0 GTS = glbl.GTS; + + bufif0 B1 (O, I, GTS); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUF_LVCMOS25_F_4.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUF_LVCMOS25_F_4.v new file mode 100644 index 0000000..d254db0 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUF_LVCMOS25_F_4.v @@ -0,0 +1,35 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/OBUF_LVCMOS25_F_4.v,v 1.6 2007/05/23 21:43:41 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Output Buffer with LVCMOS25 I/O Standard Fast Slew 4 mA Drive +// /___/ /\ Filename : OBUF_LVCMOS25_F_4.v +// \ \ / \ Timestamp : Thu Mar 25 16:43:23 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. + +`timescale 1 ps / 1 ps + + +module OBUF_LVCMOS25_F_4 (O, I); + + output O; + + input I; + + tri0 GTS = glbl.GTS; + + bufif0 B1 (O, I, GTS); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUF_LVCMOS25_F_6.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUF_LVCMOS25_F_6.v new file mode 100644 index 0000000..d1f9211 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUF_LVCMOS25_F_6.v @@ -0,0 +1,35 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/OBUF_LVCMOS25_F_6.v,v 1.6 2007/05/23 21:43:41 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Output Buffer with LVCMOS25 I/O Standard Fast Slew 6 mA Drive +// /___/ /\ Filename : OBUF_LVCMOS25_F_6.v +// \ \ / \ Timestamp : Thu Mar 25 16:43:23 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. + +`timescale 1 ps / 1 ps + + +module OBUF_LVCMOS25_F_6 (O, I); + + output O; + + input I; + + tri0 GTS = glbl.GTS; + + bufif0 B1 (O, I, GTS); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUF_LVCMOS25_F_8.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUF_LVCMOS25_F_8.v new file mode 100644 index 0000000..522731d --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUF_LVCMOS25_F_8.v @@ -0,0 +1,35 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/OBUF_LVCMOS25_F_8.v,v 1.6 2007/05/23 21:43:41 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Output Buffer with LVCMOS25 I/O Standard Fast Slew 8 mA Drive +// /___/ /\ Filename : OBUF_LVCMOS25_F_8.v +// \ \ / \ Timestamp : Thu Mar 25 16:43:23 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. + +`timescale 1 ps / 1 ps + + +module OBUF_LVCMOS25_F_8 (O, I); + + output O; + + input I; + + tri0 GTS = glbl.GTS; + + bufif0 B1 (O, I, GTS); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUF_LVCMOS25_S_12.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUF_LVCMOS25_S_12.v new file mode 100644 index 0000000..73bb15b --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUF_LVCMOS25_S_12.v @@ -0,0 +1,35 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/OBUF_LVCMOS25_S_12.v,v 1.6 2007/05/23 21:43:41 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Output Buffer with LVCMOS25 I/O Standard Slow Slew 12 mA Drive +// /___/ /\ Filename : OBUF_LVCMOS25_S_12.v +// \ \ / \ Timestamp : Thu Mar 25 16:43:23 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. + +`timescale 1 ps / 1 ps + + +module OBUF_LVCMOS25_S_12 (O, I); + + output O; + + input I; + + tri0 GTS = glbl.GTS; + + bufif0 B1 (O, I, GTS); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUF_LVCMOS25_S_16.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUF_LVCMOS25_S_16.v new file mode 100644 index 0000000..344c80e --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUF_LVCMOS25_S_16.v @@ -0,0 +1,35 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/OBUF_LVCMOS25_S_16.v,v 1.6 2007/05/23 21:43:41 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Output Buffer with LVCMOS25 I/O Standard Slow Slew 16 mA Drive +// /___/ /\ Filename : OBUF_LVCMOS25_S_16.v +// \ \ / \ Timestamp : Thu Mar 25 16:43:23 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. + +`timescale 1 ps / 1 ps + + +module OBUF_LVCMOS25_S_16 (O, I); + + output O; + + input I; + + tri0 GTS = glbl.GTS; + + bufif0 B1 (O, I, GTS); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUF_LVCMOS25_S_2.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUF_LVCMOS25_S_2.v new file mode 100644 index 0000000..8e6ef27 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUF_LVCMOS25_S_2.v @@ -0,0 +1,35 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/OBUF_LVCMOS25_S_2.v,v 1.6 2007/05/23 21:43:41 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Output Buffer with LVCMOS25 I/O Standard Slow Slew 2 mA Drive +// /___/ /\ Filename : OBUF_LVCMOS25_S_2.v +// \ \ / \ Timestamp : Thu Mar 25 16:43:23 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. + +`timescale 1 ps / 1 ps + + +module OBUF_LVCMOS25_S_2 (O, I); + + output O; + + input I; + + tri0 GTS = glbl.GTS; + + bufif0 B1 (O, I, GTS); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUF_LVCMOS25_S_24.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUF_LVCMOS25_S_24.v new file mode 100644 index 0000000..c2ec476 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUF_LVCMOS25_S_24.v @@ -0,0 +1,35 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/OBUF_LVCMOS25_S_24.v,v 1.6 2007/05/23 21:43:41 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Output Buffer with LVCMOS25 I/O Standard Slow Slew 24 mA Drive +// /___/ /\ Filename : OBUF_LVCMOS25_S_24.v +// \ \ / \ Timestamp : Thu Mar 25 16:43:23 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. + +`timescale 1 ps / 1 ps + + +module OBUF_LVCMOS25_S_24 (O, I); + + output O; + + input I; + + tri0 GTS = glbl.GTS; + + bufif0 B1 (O, I, GTS); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUF_LVCMOS25_S_4.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUF_LVCMOS25_S_4.v new file mode 100644 index 0000000..43b2b83 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUF_LVCMOS25_S_4.v @@ -0,0 +1,35 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/OBUF_LVCMOS25_S_4.v,v 1.6 2007/05/23 21:43:41 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Output Buffer with LVCMOS25 I/O Standard Slow Slew 4 mA Drive +// /___/ /\ Filename : OBUF_LVCMOS25_S_4.v +// \ \ / \ Timestamp : Thu Mar 25 16:43:23 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. + +`timescale 1 ps / 1 ps + + +module OBUF_LVCMOS25_S_4 (O, I); + + output O; + + input I; + + tri0 GTS = glbl.GTS; + + bufif0 B1 (O, I, GTS); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUF_LVCMOS25_S_6.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUF_LVCMOS25_S_6.v new file mode 100644 index 0000000..3083136 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUF_LVCMOS25_S_6.v @@ -0,0 +1,35 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/OBUF_LVCMOS25_S_6.v,v 1.6 2007/05/23 21:43:41 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Output Buffer with LVCMOS25 I/O Standard Slow Slew 6 mA Drive +// /___/ /\ Filename : OBUF_LVCMOS25_S_6.v +// \ \ / \ Timestamp : Thu Mar 25 16:43:24 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. + +`timescale 1 ps / 1 ps + + +module OBUF_LVCMOS25_S_6 (O, I); + + output O; + + input I; + + tri0 GTS = glbl.GTS; + + bufif0 B1 (O, I, GTS); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUF_LVCMOS25_S_8.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUF_LVCMOS25_S_8.v new file mode 100644 index 0000000..d047cf0 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUF_LVCMOS25_S_8.v @@ -0,0 +1,35 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/OBUF_LVCMOS25_S_8.v,v 1.6 2007/05/23 21:43:41 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Output Buffer with LVCMOS25 I/O Standard Slow Slew 8 mA Drive +// /___/ /\ Filename : OBUF_LVCMOS25_S_8.v +// \ \ / \ Timestamp : Thu Mar 25 16:43:24 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. + +`timescale 1 ps / 1 ps + + +module OBUF_LVCMOS25_S_8 (O, I); + + output O; + + input I; + + tri0 GTS = glbl.GTS; + + bufif0 B1 (O, I, GTS); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUF_LVCMOS33.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUF_LVCMOS33.v new file mode 100644 index 0000000..f8ed7de --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUF_LVCMOS33.v @@ -0,0 +1,35 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/OBUF_LVCMOS33.v,v 1.6 2007/05/23 21:43:41 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Output Buffer with LVCMOS33 I/O Standard +// /___/ /\ Filename : OBUF_LVCMOS33.v +// \ \ / \ Timestamp : Thu Mar 25 16:43:24 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. + +`timescale 1 ps / 1 ps + + +module OBUF_LVCMOS33 (O, I); + + output O; + + input I; + + tri0 GTS = glbl.GTS; + + bufif0 B1 (O, I, GTS); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUF_LVCMOS33_F_12.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUF_LVCMOS33_F_12.v new file mode 100644 index 0000000..3680b3c --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUF_LVCMOS33_F_12.v @@ -0,0 +1,35 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/OBUF_LVCMOS33_F_12.v,v 1.6 2007/05/23 21:43:41 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Output Buffer with LVCMOS33 I/O Standard Fast Slew 12 mA Drive +// /___/ /\ Filename : OBUF_LVCMOS33_F_12.v +// \ \ / \ Timestamp : Thu Mar 25 16:43:24 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. + +`timescale 1 ps / 1 ps + + +module OBUF_LVCMOS33_F_12 (O, I); + + output O; + + input I; + + tri0 GTS = glbl.GTS; + + bufif0 B1 (O, I, GTS); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUF_LVCMOS33_F_16.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUF_LVCMOS33_F_16.v new file mode 100644 index 0000000..e342dba --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUF_LVCMOS33_F_16.v @@ -0,0 +1,35 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/OBUF_LVCMOS33_F_16.v,v 1.6 2007/05/23 21:43:41 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Output Buffer with LVCMOS33 I/O Standard Fast Slew 16 mA Drive +// /___/ /\ Filename : OBUF_LVCMOS33_F_16.v +// \ \ / \ Timestamp : Thu Mar 25 16:43:24 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. + +`timescale 1 ps / 1 ps + + +module OBUF_LVCMOS33_F_16 (O, I); + + output O; + + input I; + + tri0 GTS = glbl.GTS; + + bufif0 B1 (O, I, GTS); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUF_LVCMOS33_F_2.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUF_LVCMOS33_F_2.v new file mode 100644 index 0000000..be8b190 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUF_LVCMOS33_F_2.v @@ -0,0 +1,35 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/OBUF_LVCMOS33_F_2.v,v 1.6 2007/05/23 21:43:41 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Output Buffer with LVCMOS33 I/O Standard Fast Slew 2 mA Drive +// /___/ /\ Filename : OBUF_LVCMOS33_F_2.v +// \ \ / \ Timestamp : Thu Mar 25 16:43:24 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. + +`timescale 1 ps / 1 ps + + +module OBUF_LVCMOS33_F_2 (O, I); + + output O; + + input I; + + tri0 GTS = glbl.GTS; + + bufif0 B1 (O, I, GTS); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUF_LVCMOS33_F_24.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUF_LVCMOS33_F_24.v new file mode 100644 index 0000000..e618cc5 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUF_LVCMOS33_F_24.v @@ -0,0 +1,35 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/OBUF_LVCMOS33_F_24.v,v 1.6 2007/05/23 21:43:41 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Output Buffer with LVCMOS33 I/O Standard Fast Slew 24 mA Drive +// /___/ /\ Filename : OBUF_LVCMOS33_F_24.v +// \ \ / \ Timestamp : Thu Mar 25 16:43:24 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. + +`timescale 1 ps / 1 ps + + +module OBUF_LVCMOS33_F_24 (O, I); + + output O; + + input I; + + tri0 GTS = glbl.GTS; + + bufif0 B1 (O, I, GTS); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUF_LVCMOS33_F_4.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUF_LVCMOS33_F_4.v new file mode 100644 index 0000000..0c6ab78 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUF_LVCMOS33_F_4.v @@ -0,0 +1,35 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/OBUF_LVCMOS33_F_4.v,v 1.6 2007/05/23 21:43:41 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Output Buffer with LVCMOS33 I/O Standard Fast Slew 4 mA Drive +// /___/ /\ Filename : OBUF_LVCMOS33_F_4.v +// \ \ / \ Timestamp : Thu Mar 25 16:43:24 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. + +`timescale 1 ps / 1 ps + + +module OBUF_LVCMOS33_F_4 (O, I); + + output O; + + input I; + + tri0 GTS = glbl.GTS; + + bufif0 B1 (O, I, GTS); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUF_LVCMOS33_F_6.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUF_LVCMOS33_F_6.v new file mode 100644 index 0000000..8fe5ea9 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUF_LVCMOS33_F_6.v @@ -0,0 +1,35 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/OBUF_LVCMOS33_F_6.v,v 1.6 2007/05/23 21:43:41 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Output Buffer with LVCMOS33 I/O Standard Fast Slew 6 mA Drive +// /___/ /\ Filename : OBUF_LVCMOS33_F_6.v +// \ \ / \ Timestamp : Thu Mar 25 16:43:24 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. + +`timescale 1 ps / 1 ps + + +module OBUF_LVCMOS33_F_6 (O, I); + + output O; + + input I; + + tri0 GTS = glbl.GTS; + + bufif0 B1 (O, I, GTS); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUF_LVCMOS33_F_8.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUF_LVCMOS33_F_8.v new file mode 100644 index 0000000..d85ac3b --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUF_LVCMOS33_F_8.v @@ -0,0 +1,35 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/OBUF_LVCMOS33_F_8.v,v 1.6 2007/05/23 21:43:41 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Output Buffer with LVCMOS33 I/O Standard Fast Slew 8 mA Drive +// /___/ /\ Filename : OBUF_LVCMOS33_F_8.v +// \ \ / \ Timestamp : Thu Mar 25 16:43:24 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. + +`timescale 1 ps / 1 ps + + +module OBUF_LVCMOS33_F_8 (O, I); + + output O; + + input I; + + tri0 GTS = glbl.GTS; + + bufif0 B1 (O, I, GTS); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUF_LVCMOS33_S_12.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUF_LVCMOS33_S_12.v new file mode 100644 index 0000000..b47d86d --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUF_LVCMOS33_S_12.v @@ -0,0 +1,35 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/OBUF_LVCMOS33_S_12.v,v 1.6 2007/05/23 21:43:41 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Output Buffer with LVCMOS33 I/O Standard Slow Slew 12 mA Drive +// /___/ /\ Filename : OBUF_LVCMOS33_S_12.v +// \ \ / \ Timestamp : Thu Mar 25 16:43:25 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. + +`timescale 1 ps / 1 ps + + +module OBUF_LVCMOS33_S_12 (O, I); + + output O; + + input I; + + tri0 GTS = glbl.GTS; + + bufif0 B1 (O, I, GTS); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUF_LVCMOS33_S_16.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUF_LVCMOS33_S_16.v new file mode 100644 index 0000000..2b5fc7f --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUF_LVCMOS33_S_16.v @@ -0,0 +1,35 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/OBUF_LVCMOS33_S_16.v,v 1.6 2007/05/23 21:43:41 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Output Buffer with LVCMOS33 I/O Standard Slow Slew 16 mA Drive +// /___/ /\ Filename : OBUF_LVCMOS33_S_16.v +// \ \ / \ Timestamp : Thu Mar 25 16:43:25 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. + +`timescale 1 ps / 1 ps + + +module OBUF_LVCMOS33_S_16 (O, I); + + output O; + + input I; + + tri0 GTS = glbl.GTS; + + bufif0 B1 (O, I, GTS); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUF_LVCMOS33_S_2.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUF_LVCMOS33_S_2.v new file mode 100644 index 0000000..4be9937 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUF_LVCMOS33_S_2.v @@ -0,0 +1,35 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/OBUF_LVCMOS33_S_2.v,v 1.6 2007/05/23 21:43:41 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Output Buffer with LVCMOS33 I/O Standard Slow Slew 2 mA Drive +// /___/ /\ Filename : OBUF_LVCMOS33_S_2.v +// \ \ / \ Timestamp : Thu Mar 25 16:43:25 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. + +`timescale 1 ps / 1 ps + + +module OBUF_LVCMOS33_S_2 (O, I); + + output O; + + input I; + + tri0 GTS = glbl.GTS; + + bufif0 B1 (O, I, GTS); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUF_LVCMOS33_S_24.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUF_LVCMOS33_S_24.v new file mode 100644 index 0000000..be6938a --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUF_LVCMOS33_S_24.v @@ -0,0 +1,35 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/OBUF_LVCMOS33_S_24.v,v 1.6 2007/05/23 21:43:41 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Output Buffer with LVCMOS33 I/O Standard Slow Slew 24 mA Drive +// /___/ /\ Filename : OBUF_LVCMOS33_S_24.v +// \ \ / \ Timestamp : Thu Mar 25 16:43:25 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. + +`timescale 1 ps / 1 ps + + +module OBUF_LVCMOS33_S_24 (O, I); + + output O; + + input I; + + tri0 GTS = glbl.GTS; + + bufif0 B1 (O, I, GTS); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUF_LVCMOS33_S_4.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUF_LVCMOS33_S_4.v new file mode 100644 index 0000000..5dacde3 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUF_LVCMOS33_S_4.v @@ -0,0 +1,35 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/OBUF_LVCMOS33_S_4.v,v 1.6 2007/05/23 21:43:41 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Output Buffer with LVCMOS33 I/O Standard Slow Slew 4 mA Drive +// /___/ /\ Filename : OBUF_LVCMOS33_S_4.v +// \ \ / \ Timestamp : Thu Mar 25 16:43:25 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. + +`timescale 1 ps / 1 ps + + +module OBUF_LVCMOS33_S_4 (O, I); + + output O; + + input I; + + tri0 GTS = glbl.GTS; + + bufif0 B1 (O, I, GTS); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUF_LVCMOS33_S_6.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUF_LVCMOS33_S_6.v new file mode 100644 index 0000000..759cb12 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUF_LVCMOS33_S_6.v @@ -0,0 +1,35 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/OBUF_LVCMOS33_S_6.v,v 1.6 2007/05/23 21:43:41 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Output Buffer with LVCMOS33 I/O Standard Slow Slew 6 mA Drive +// /___/ /\ Filename : OBUF_LVCMOS33_S_6.v +// \ \ / \ Timestamp : Thu Mar 25 16:43:25 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. + +`timescale 1 ps / 1 ps + + +module OBUF_LVCMOS33_S_6 (O, I); + + output O; + + input I; + + tri0 GTS = glbl.GTS; + + bufif0 B1 (O, I, GTS); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUF_LVCMOS33_S_8.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUF_LVCMOS33_S_8.v new file mode 100644 index 0000000..a0e1586 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUF_LVCMOS33_S_8.v @@ -0,0 +1,35 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/OBUF_LVCMOS33_S_8.v,v 1.6 2007/05/23 21:43:41 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Output Buffer with LVCMOS33 I/O Standard Slow Slew 8 mA Drive +// /___/ /\ Filename : OBUF_LVCMOS33_S_8.v +// \ \ / \ Timestamp : Thu Mar 25 16:43:25 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. + +`timescale 1 ps / 1 ps + + +module OBUF_LVCMOS33_S_8 (O, I); + + output O; + + input I; + + tri0 GTS = glbl.GTS; + + bufif0 B1 (O, I, GTS); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUF_LVDCI_15.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUF_LVDCI_15.v new file mode 100644 index 0000000..d7de6af --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUF_LVDCI_15.v @@ -0,0 +1,35 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/OBUF_LVDCI_15.v,v 1.6 2007/05/23 21:43:41 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Output Buffer with LVDCI_15 I/O Standard +// /___/ /\ Filename : OBUF_LVDCI_15.v +// \ \ / \ Timestamp : Thu Mar 25 16:43:25 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. + +`timescale 1 ps / 1 ps + + +module OBUF_LVDCI_15 (O, I); + + output O; + + input I; + + tri0 GTS = glbl.GTS; + + bufif0 B1 (O, I, GTS); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUF_LVDCI_18.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUF_LVDCI_18.v new file mode 100644 index 0000000..9ac6655 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUF_LVDCI_18.v @@ -0,0 +1,35 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/OBUF_LVDCI_18.v,v 1.6 2007/05/23 21:43:41 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Output Buffer with LVDCI_18 I/O Standard +// /___/ /\ Filename : OBUF_LVDCI_18.v +// \ \ / \ Timestamp : Thu Mar 25 16:43:25 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. + +`timescale 1 ps / 1 ps + + +module OBUF_LVDCI_18 (O, I); + + output O; + + input I; + + tri0 GTS = glbl.GTS; + + bufif0 B1 (O, I, GTS); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUF_LVDCI_25.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUF_LVDCI_25.v new file mode 100644 index 0000000..bf02136 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUF_LVDCI_25.v @@ -0,0 +1,35 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/OBUF_LVDCI_25.v,v 1.6 2007/05/23 21:43:41 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Output Buffer with LVDCI_25 I/O Standard +// /___/ /\ Filename : OBUF_LVDCI_25.v +// \ \ / \ Timestamp : Thu Mar 25 16:43:25 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. + +`timescale 1 ps / 1 ps + + +module OBUF_LVDCI_25 (O, I); + + output O; + + input I; + + tri0 GTS = glbl.GTS; + + bufif0 B1 (O, I, GTS); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUF_LVDCI_33.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUF_LVDCI_33.v new file mode 100644 index 0000000..cb50d33 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUF_LVDCI_33.v @@ -0,0 +1,35 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/OBUF_LVDCI_33.v,v 1.6 2007/05/23 21:43:41 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Output Buffer with LVDCI_33 I/O Standard +// /___/ /\ Filename : OBUF_LVDCI_33.v +// \ \ / \ Timestamp : Thu Mar 25 16:43:25 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. + +`timescale 1 ps / 1 ps + + +module OBUF_LVDCI_33 (O, I); + + output O; + + input I; + + tri0 GTS = glbl.GTS; + + bufif0 B1 (O, I, GTS); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUF_LVDCI_DV2_15.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUF_LVDCI_DV2_15.v new file mode 100644 index 0000000..60e65f8 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUF_LVDCI_DV2_15.v @@ -0,0 +1,35 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/OBUF_LVDCI_DV2_15.v,v 1.6 2007/05/23 21:43:41 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Output Buffer with LVDCI_DV2_15 I/O Standard +// /___/ /\ Filename : OBUF_LVDCI_DV2_15.v +// \ \ / \ Timestamp : Thu Mar 25 16:43:26 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. + +`timescale 1 ps / 1 ps + + +module OBUF_LVDCI_DV2_15 (O, I); + + output O; + + input I; + + tri0 GTS = glbl.GTS; + + bufif0 B1 (O, I, GTS); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUF_LVDCI_DV2_18.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUF_LVDCI_DV2_18.v new file mode 100644 index 0000000..b6a0ad6 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUF_LVDCI_DV2_18.v @@ -0,0 +1,35 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/OBUF_LVDCI_DV2_18.v,v 1.6 2007/05/23 21:43:41 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Output Buffer with LVDCI_DV2_18 I/O Standard +// /___/ /\ Filename : OBUF_LVDCI_DV2_18.v +// \ \ / \ Timestamp : Thu Mar 25 16:43:26 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. + +`timescale 1 ps / 1 ps + + +module OBUF_LVDCI_DV2_18 (O, I); + + output O; + + input I; + + tri0 GTS = glbl.GTS; + + bufif0 B1 (O, I, GTS); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUF_LVDCI_DV2_25.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUF_LVDCI_DV2_25.v new file mode 100644 index 0000000..e1b725b --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUF_LVDCI_DV2_25.v @@ -0,0 +1,35 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/OBUF_LVDCI_DV2_25.v,v 1.6 2007/05/23 21:43:41 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Output Buffer with LVDCI_DV2_25 I/O Standard +// /___/ /\ Filename : OBUF_LVDCI_DV2_25.v +// \ \ / \ Timestamp : Thu Mar 25 16:43:26 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. + +`timescale 1 ps / 1 ps + + +module OBUF_LVDCI_DV2_25 (O, I); + + output O; + + input I; + + tri0 GTS = glbl.GTS; + + bufif0 B1 (O, I, GTS); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUF_LVDCI_DV2_33.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUF_LVDCI_DV2_33.v new file mode 100644 index 0000000..75b355a --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUF_LVDCI_DV2_33.v @@ -0,0 +1,35 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/OBUF_LVDCI_DV2_33.v,v 1.6 2007/05/23 21:43:41 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Output Buffer with LVDCI_DV2_33 I/O Standard +// /___/ /\ Filename : OBUF_LVDCI_DV2_33.v +// \ \ / \ Timestamp : Thu Mar 25 16:43:26 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. + +`timescale 1 ps / 1 ps + + +module OBUF_LVDCI_DV2_33 (O, I); + + output O; + + input I; + + tri0 GTS = glbl.GTS; + + bufif0 B1 (O, I, GTS); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUF_LVDS.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUF_LVDS.v new file mode 100644 index 0000000..353560b --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUF_LVDS.v @@ -0,0 +1,35 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/OBUF_LVDS.v,v 1.6 2007/05/23 21:43:41 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Output Buffer with LVDS I/O Standard +// /___/ /\ Filename : OBUF_LVDS.v +// \ \ / \ Timestamp : Thu Mar 25 16:43:26 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. + +`timescale 1 ps / 1 ps + + +module OBUF_LVDS (O, I); + + output O; + + input I; + + tri0 GTS = glbl.GTS; + + bufif0 B1 (O, I, GTS); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUF_LVPECL.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUF_LVPECL.v new file mode 100644 index 0000000..df1c6c2 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUF_LVPECL.v @@ -0,0 +1,35 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/OBUF_LVPECL.v,v 1.6 2007/05/23 21:43:41 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Output Buffer with LVPECL I/O Standard +// /___/ /\ Filename : OBUF_LVPECL.v +// \ \ / \ Timestamp : Thu Mar 25 16:43:26 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. + +`timescale 1 ps / 1 ps + + +module OBUF_LVPECL (O, I); + + output O; + + input I; + + tri0 GTS = glbl.GTS; + + bufif0 B1 (O, I, GTS); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUF_LVTTL.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUF_LVTTL.v new file mode 100644 index 0000000..815fde6 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUF_LVTTL.v @@ -0,0 +1,35 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/OBUF_LVTTL.v,v 1.6 2007/05/23 21:43:41 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Output Buffer with LVTTL I/O Standard +// /___/ /\ Filename : OBUF_LVTTL.v +// \ \ / \ Timestamp : Thu Mar 25 16:43:26 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. + +`timescale 1 ps / 1 ps + + +module OBUF_LVTTL (O, I); + + output O; + + input I; + + tri0 GTS = glbl.GTS; + + bufif0 B1 (O, I, GTS); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUF_LVTTL_F_12.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUF_LVTTL_F_12.v new file mode 100644 index 0000000..62458d2 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUF_LVTTL_F_12.v @@ -0,0 +1,35 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/OBUF_LVTTL_F_12.v,v 1.6 2007/05/23 21:43:41 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Output Buffer with LVTTL I/O Standard Fast Slew 12 mA Drive +// /___/ /\ Filename : OBUF_LVTTL_F_12.v +// \ \ / \ Timestamp : Thu Mar 25 16:43:26 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. + +`timescale 1 ps / 1 ps + + +module OBUF_LVTTL_F_12 (O, I); + + output O; + + input I; + + tri0 GTS = glbl.GTS; + + bufif0 B1 (O, I, GTS); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUF_LVTTL_F_16.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUF_LVTTL_F_16.v new file mode 100644 index 0000000..dc0bcfb --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUF_LVTTL_F_16.v @@ -0,0 +1,35 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/OBUF_LVTTL_F_16.v,v 1.6 2007/05/23 21:43:41 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Output Buffer with LVTTL I/O Standard Fast Slew 16 mA Drive +// /___/ /\ Filename : OBUF_LVTTL_F_16.v +// \ \ / \ Timestamp : Thu Mar 25 16:43:26 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. + +`timescale 1 ps / 1 ps + + +module OBUF_LVTTL_F_16 (O, I); + + output O; + + input I; + + tri0 GTS = glbl.GTS; + + bufif0 B1 (O, I, GTS); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUF_LVTTL_F_2.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUF_LVTTL_F_2.v new file mode 100644 index 0000000..710f2e3 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUF_LVTTL_F_2.v @@ -0,0 +1,35 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/OBUF_LVTTL_F_2.v,v 1.6 2007/05/23 21:43:41 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Output Buffer with LVTTL I/O Standard Fast Slew 2 mA Drive +// /___/ /\ Filename : OBUF_LVTTL_F_2.v +// \ \ / \ Timestamp : Thu Mar 25 16:43:26 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. + +`timescale 1 ps / 1 ps + + +module OBUF_LVTTL_F_2 (O, I); + + output O; + + input I; + + tri0 GTS = glbl.GTS; + + bufif0 B1 (O, I, GTS); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUF_LVTTL_F_24.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUF_LVTTL_F_24.v new file mode 100644 index 0000000..9efb889 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUF_LVTTL_F_24.v @@ -0,0 +1,35 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/OBUF_LVTTL_F_24.v,v 1.6 2007/05/23 21:43:41 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Output Buffer with LVTTL I/O Standard Fast Slew 24 mA Drive +// /___/ /\ Filename : OBUF_LVTTL_F_24.v +// \ \ / \ Timestamp : Thu Mar 25 16:43:27 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. + +`timescale 1 ps / 1 ps + + +module OBUF_LVTTL_F_24 (O, I); + + output O; + + input I; + + tri0 GTS = glbl.GTS; + + bufif0 B1 (O, I, GTS); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUF_LVTTL_F_4.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUF_LVTTL_F_4.v new file mode 100644 index 0000000..11c0466 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUF_LVTTL_F_4.v @@ -0,0 +1,35 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/OBUF_LVTTL_F_4.v,v 1.6 2007/05/23 21:43:41 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Output Buffer with LVTTL I/O Standard Fast Slew 4 mA Drive +// /___/ /\ Filename : OBUF_LVTTL_F_4.v +// \ \ / \ Timestamp : Thu Mar 25 16:43:27 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. + +`timescale 1 ps / 1 ps + + +module OBUF_LVTTL_F_4 (O, I); + + output O; + + input I; + + tri0 GTS = glbl.GTS; + + bufif0 B1 (O, I, GTS); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUF_LVTTL_F_6.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUF_LVTTL_F_6.v new file mode 100644 index 0000000..4187cd0 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUF_LVTTL_F_6.v @@ -0,0 +1,35 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/OBUF_LVTTL_F_6.v,v 1.6 2007/05/23 21:43:41 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Output Buffer with LVTTL I/O Standard Fast Slew 6 mA Drive +// /___/ /\ Filename : OBUF_LVTTL_F_6.v +// \ \ / \ Timestamp : Thu Mar 25 16:43:27 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. + +`timescale 1 ps / 1 ps + + +module OBUF_LVTTL_F_6 (O, I); + + output O; + + input I; + + tri0 GTS = glbl.GTS; + + bufif0 B1 (O, I, GTS); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUF_LVTTL_F_8.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUF_LVTTL_F_8.v new file mode 100644 index 0000000..c6bceac --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUF_LVTTL_F_8.v @@ -0,0 +1,35 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/OBUF_LVTTL_F_8.v,v 1.6 2007/05/23 21:43:41 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Output Buffer with LVTTL I/O Standard Fast Slew 8 mA Drive +// /___/ /\ Filename : OBUF_LVTTL_F_8.v +// \ \ / \ Timestamp : Thu Mar 25 16:43:27 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. + +`timescale 1 ps / 1 ps + + +module OBUF_LVTTL_F_8 (O, I); + + output O; + + input I; + + tri0 GTS = glbl.GTS; + + bufif0 B1 (O, I, GTS); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUF_LVTTL_S_12.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUF_LVTTL_S_12.v new file mode 100644 index 0000000..f1a7214 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUF_LVTTL_S_12.v @@ -0,0 +1,35 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/OBUF_LVTTL_S_12.v,v 1.6 2007/05/23 21:43:41 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Output Buffer with LVTTL I/O Standard Slow Slew 12 mA Drive +// /___/ /\ Filename : OBUF_LVTTL_S_12.v +// \ \ / \ Timestamp : Thu Mar 25 16:43:27 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. + +`timescale 1 ps / 1 ps + + +module OBUF_LVTTL_S_12 (O, I); + + output O; + + input I; + + tri0 GTS = glbl.GTS; + + bufif0 B1 (O, I, GTS); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUF_LVTTL_S_16.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUF_LVTTL_S_16.v new file mode 100644 index 0000000..4a7a0d8 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUF_LVTTL_S_16.v @@ -0,0 +1,35 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/OBUF_LVTTL_S_16.v,v 1.6 2007/05/23 21:43:41 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Output Buffer with LVTTL I/O Standard Slow Slew 16 mA Drive +// /___/ /\ Filename : OBUF_LVTTL_S_16.v +// \ \ / \ Timestamp : Thu Mar 25 16:43:27 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. + +`timescale 1 ps / 1 ps + + +module OBUF_LVTTL_S_16 (O, I); + + output O; + + input I; + + tri0 GTS = glbl.GTS; + + bufif0 B1 (O, I, GTS); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUF_LVTTL_S_2.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUF_LVTTL_S_2.v new file mode 100644 index 0000000..f82b6cc --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUF_LVTTL_S_2.v @@ -0,0 +1,35 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/OBUF_LVTTL_S_2.v,v 1.6 2007/05/23 21:43:41 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Output Buffer with LVTTL I/O Standard Slow Slew 2 mA Drive +// /___/ /\ Filename : OBUF_LVTTL_S_2.v +// \ \ / \ Timestamp : Thu Mar 25 16:43:27 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. + +`timescale 1 ps / 1 ps + + +module OBUF_LVTTL_S_2 (O, I); + + output O; + + input I; + + tri0 GTS = glbl.GTS; + + bufif0 B1 (O, I, GTS); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUF_LVTTL_S_24.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUF_LVTTL_S_24.v new file mode 100644 index 0000000..36f8bc8 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUF_LVTTL_S_24.v @@ -0,0 +1,35 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/OBUF_LVTTL_S_24.v,v 1.6 2007/05/23 21:43:41 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Output Buffer with LVTTL I/O Standard Slow Slew 24 mA Drive +// /___/ /\ Filename : OBUF_LVTTL_S_24.v +// \ \ / \ Timestamp : Thu Mar 25 16:43:27 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. + +`timescale 1 ps / 1 ps + + +module OBUF_LVTTL_S_24 (O, I); + + output O; + + input I; + + tri0 GTS = glbl.GTS; + + bufif0 B1 (O, I, GTS); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUF_LVTTL_S_4.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUF_LVTTL_S_4.v new file mode 100644 index 0000000..e5b970b --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUF_LVTTL_S_4.v @@ -0,0 +1,35 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/OBUF_LVTTL_S_4.v,v 1.6 2007/05/23 21:43:41 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Output Buffer with LVTTL I/O Standard Slow Slew 4 mA Drive +// /___/ /\ Filename : OBUF_LVTTL_S_4.v +// \ \ / \ Timestamp : Thu Mar 25 16:43:27 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. + +`timescale 1 ps / 1 ps + + +module OBUF_LVTTL_S_4 (O, I); + + output O; + + input I; + + tri0 GTS = glbl.GTS; + + bufif0 B1 (O, I, GTS); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUF_LVTTL_S_6.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUF_LVTTL_S_6.v new file mode 100644 index 0000000..acfe23e --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUF_LVTTL_S_6.v @@ -0,0 +1,35 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/OBUF_LVTTL_S_6.v,v 1.6 2007/05/23 21:43:41 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Output Buffer with LVTTL I/O Standard Slow Slew 6 mA Drive +// /___/ /\ Filename : OBUF_LVTTL_S_6.v +// \ \ / \ Timestamp : Thu Mar 25 16:43:27 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. + +`timescale 1 ps / 1 ps + + +module OBUF_LVTTL_S_6 (O, I); + + output O; + + input I; + + tri0 GTS = glbl.GTS; + + bufif0 B1 (O, I, GTS); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUF_LVTTL_S_8.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUF_LVTTL_S_8.v new file mode 100644 index 0000000..f780389 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUF_LVTTL_S_8.v @@ -0,0 +1,35 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/OBUF_LVTTL_S_8.v,v 1.6 2007/05/23 21:43:41 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Output Buffer with LVTTL I/O Standard Slow Slew 8 mA Drive +// /___/ /\ Filename : OBUF_LVTTL_S_8.v +// \ \ / \ Timestamp : Thu Mar 25 16:43:27 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. + +`timescale 1 ps / 1 ps + + +module OBUF_LVTTL_S_8 (O, I); + + output O; + + input I; + + tri0 GTS = glbl.GTS; + + bufif0 B1 (O, I, GTS); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUF_PCI33_3.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUF_PCI33_3.v new file mode 100644 index 0000000..7d0e739 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUF_PCI33_3.v @@ -0,0 +1,35 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/OBUF_PCI33_3.v,v 1.6 2007/05/23 21:43:41 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Output Buffer with PCI33_3 I/O Standard +// /___/ /\ Filename : OBUF_PCI33_3.v +// \ \ / \ Timestamp : Thu Mar 25 16:43:28 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. + +`timescale 1 ps / 1 ps + + +module OBUF_PCI33_3 (O, I); + + output O; + + input I; + + tri0 GTS = glbl.GTS; + + bufif0 B1 (O, I, GTS); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUF_PCI33_5.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUF_PCI33_5.v new file mode 100644 index 0000000..1135718 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUF_PCI33_5.v @@ -0,0 +1,35 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/OBUF_PCI33_5.v,v 1.6 2007/05/23 21:43:41 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Output Buffer with PCI33_5 I/O Standard +// /___/ /\ Filename : OBUF_PCI33_5.v +// \ \ / \ Timestamp : Thu Mar 25 16:43:28 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. + +`timescale 1 ps / 1 ps + + +module OBUF_PCI33_5 (O, I); + + output O; + + input I; + + tri0 GTS = glbl.GTS; + + bufif0 B1 (O, I, GTS); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUF_PCI66_3.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUF_PCI66_3.v new file mode 100644 index 0000000..0ee36fe --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUF_PCI66_3.v @@ -0,0 +1,35 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/OBUF_PCI66_3.v,v 1.6 2007/05/23 21:43:41 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Output Buffer with PCI66_3 I/O Standard +// /___/ /\ Filename : OBUF_PCI66_3.v +// \ \ / \ Timestamp : Thu Mar 25 16:43:28 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. + +`timescale 1 ps / 1 ps + + +module OBUF_PCI66_3 (O, I); + + output O; + + input I; + + tri0 GTS = glbl.GTS; + + bufif0 B1 (O, I, GTS); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUF_PCIX.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUF_PCIX.v new file mode 100644 index 0000000..7759ada --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUF_PCIX.v @@ -0,0 +1,35 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/OBUF_PCIX.v,v 1.6 2007/05/23 21:43:41 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Output Buffer with PCIX I/O Standard +// /___/ /\ Filename : OBUF_PCIX.v +// \ \ / \ Timestamp : Thu Mar 25 16:43:28 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. + +`timescale 1 ps / 1 ps + + +module OBUF_PCIX (O, I); + + output O; + + input I; + + tri0 GTS = glbl.GTS; + + bufif0 B1 (O, I, GTS); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUF_PCIX66_3.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUF_PCIX66_3.v new file mode 100644 index 0000000..59b1ebc --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUF_PCIX66_3.v @@ -0,0 +1,35 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/OBUF_PCIX66_3.v,v 1.6 2007/05/23 21:43:41 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Output Buffer with PCIX66_3 I/O Standard +// /___/ /\ Filename : OBUF_PCIX66_3.v +// \ \ / \ Timestamp : Thu Mar 25 16:43:28 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. + +`timescale 1 ps / 1 ps + + +module OBUF_PCIX66_3 (O, I); + + output O; + + input I; + + tri0 GTS = glbl.GTS; + + bufif0 B1 (O, I, GTS); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUF_SSTL18_I.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUF_SSTL18_I.v new file mode 100644 index 0000000..d010253 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUF_SSTL18_I.v @@ -0,0 +1,35 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/OBUF_SSTL18_I.v,v 1.6 2007/05/23 21:43:41 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Output Buffer with SSTL18_I I/O Standard +// /___/ /\ Filename : OBUF_SSTL18_I.v +// \ \ / \ Timestamp : Thu Mar 25 16:43:28 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. + +`timescale 1 ps / 1 ps + + +module OBUF_SSTL18_I (O, I); + + output O; + + input I; + + tri0 GTS = glbl.GTS; + + bufif0 B1 (O, I, GTS); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUF_SSTL18_II.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUF_SSTL18_II.v new file mode 100644 index 0000000..e4db63a --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUF_SSTL18_II.v @@ -0,0 +1,35 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/OBUF_SSTL18_II.v,v 1.6 2007/05/23 21:43:41 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Output Buffer with SSTL18_II I/O Standard +// /___/ /\ Filename : OBUF_SSTL18_II.v +// \ \ / \ Timestamp : Thu Mar 25 16:43:28 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. + +`timescale 1 ps / 1 ps + + +module OBUF_SSTL18_II (O, I); + + output O; + + input I; + + tri0 GTS = glbl.GTS; + + bufif0 B1 (O, I, GTS); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUF_SSTL18_II_DCI.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUF_SSTL18_II_DCI.v new file mode 100644 index 0000000..f19bcd7 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUF_SSTL18_II_DCI.v @@ -0,0 +1,35 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/OBUF_SSTL18_II_DCI.v,v 1.6 2007/05/23 21:43:41 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Output Buffer with SSTL18_II_DCI I/O Standard +// /___/ /\ Filename : OBUF_SSTL18_II_DCI.v +// \ \ / \ Timestamp : Thu Mar 25 16:43:28 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. + +`timescale 1 ps / 1 ps + + +module OBUF_SSTL18_II_DCI (O, I); + + output O; + + input I; + + tri0 GTS = glbl.GTS; + + bufif0 B1 (O, I, GTS); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUF_SSTL18_I_DCI.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUF_SSTL18_I_DCI.v new file mode 100644 index 0000000..d355900 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUF_SSTL18_I_DCI.v @@ -0,0 +1,35 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/OBUF_SSTL18_I_DCI.v,v 1.6 2007/05/23 21:43:41 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Output Buffer with SSTL18_I_DCI I/O Standard +// /___/ /\ Filename : OBUF_SSTL18_I_DCI.v +// \ \ / \ Timestamp : Thu Mar 25 16:43:28 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. + +`timescale 1 ps / 1 ps + + +module OBUF_SSTL18_I_DCI (O, I); + + output O; + + input I; + + tri0 GTS = glbl.GTS; + + bufif0 B1 (O, I, GTS); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUF_SSTL2_I.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUF_SSTL2_I.v new file mode 100644 index 0000000..a06826f --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUF_SSTL2_I.v @@ -0,0 +1,35 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/OBUF_SSTL2_I.v,v 1.6 2007/05/23 21:43:41 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Output Buffer with SSTL2_I I/O Standard +// /___/ /\ Filename : OBUF_SSTL2_I.v +// \ \ / \ Timestamp : Thu Mar 25 16:43:28 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. + +`timescale 1 ps / 1 ps + + +module OBUF_SSTL2_I (O, I); + + output O; + + input I; + + tri0 GTS = glbl.GTS; + + bufif0 B1 (O, I, GTS); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUF_SSTL2_II.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUF_SSTL2_II.v new file mode 100644 index 0000000..a3f3a5b --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUF_SSTL2_II.v @@ -0,0 +1,35 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/OBUF_SSTL2_II.v,v 1.6 2007/05/23 21:43:41 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Output Buffer with SSTL2_II I/O Standard +// /___/ /\ Filename : OBUF_SSTL2_II.v +// \ \ / \ Timestamp : Thu Mar 25 16:43:28 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. + +`timescale 1 ps / 1 ps + + +module OBUF_SSTL2_II (O, I); + + output O; + + input I; + + tri0 GTS = glbl.GTS; + + bufif0 B1 (O, I, GTS); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUF_SSTL2_II_DCI.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUF_SSTL2_II_DCI.v new file mode 100644 index 0000000..24a33e7 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUF_SSTL2_II_DCI.v @@ -0,0 +1,35 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/OBUF_SSTL2_II_DCI.v,v 1.6 2007/05/23 21:43:41 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Output Buffer with SSTL2_II_DCI I/O Standard +// /___/ /\ Filename : OBUF_SSTL2_II_DCI.v +// \ \ / \ Timestamp : Thu Mar 25 16:43:29 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. + +`timescale 1 ps / 1 ps + + +module OBUF_SSTL2_II_DCI (O, I); + + output O; + + input I; + + tri0 GTS = glbl.GTS; + + bufif0 B1 (O, I, GTS); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUF_SSTL2_I_DCI.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUF_SSTL2_I_DCI.v new file mode 100644 index 0000000..756efbf --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUF_SSTL2_I_DCI.v @@ -0,0 +1,35 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/OBUF_SSTL2_I_DCI.v,v 1.6 2007/05/23 21:43:41 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Output Buffer with SSTL2_I_DCI I/O Standard +// /___/ /\ Filename : OBUF_SSTL2_I_DCI.v +// \ \ / \ Timestamp : Thu Mar 25 16:43:29 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. + +`timescale 1 ps / 1 ps + + +module OBUF_SSTL2_I_DCI (O, I); + + output O; + + input I; + + tri0 GTS = glbl.GTS; + + bufif0 B1 (O, I, GTS); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUF_SSTL3_I.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUF_SSTL3_I.v new file mode 100644 index 0000000..ccd06d4 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUF_SSTL3_I.v @@ -0,0 +1,35 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/OBUF_SSTL3_I.v,v 1.6 2007/05/23 21:43:41 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Output Buffer with SSTL3_I I/O Standard +// /___/ /\ Filename : OBUF_SSTL3_I.v +// \ \ / \ Timestamp : Thu Mar 25 16:43:29 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. + +`timescale 1 ps / 1 ps + + +module OBUF_SSTL3_I (O, I); + + output O; + + input I; + + tri0 GTS = glbl.GTS; + + bufif0 B1 (O, I, GTS); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUF_SSTL3_II.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUF_SSTL3_II.v new file mode 100644 index 0000000..fc7737c --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUF_SSTL3_II.v @@ -0,0 +1,35 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/OBUF_SSTL3_II.v,v 1.6 2007/05/23 21:43:41 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Output Buffer with SSTL3_II I/O Standard +// /___/ /\ Filename : OBUF_SSTL3_II.v +// \ \ / \ Timestamp : Thu Mar 25 16:43:29 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. + +`timescale 1 ps / 1 ps + + +module OBUF_SSTL3_II (O, I); + + output O; + + input I; + + tri0 GTS = glbl.GTS; + + bufif0 B1 (O, I, GTS); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUF_SSTL3_II_DCI.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUF_SSTL3_II_DCI.v new file mode 100644 index 0000000..6fcdcc6 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUF_SSTL3_II_DCI.v @@ -0,0 +1,35 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/OBUF_SSTL3_II_DCI.v,v 1.6 2007/05/23 21:43:41 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Output Buffer with SSTL3_II_DCI I/O Standard +// /___/ /\ Filename : OBUF_SSTL3_II_DCI.v +// \ \ / \ Timestamp : Thu Mar 25 16:43:29 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. + +`timescale 1 ps / 1 ps + + +module OBUF_SSTL3_II_DCI (O, I); + + output O; + + input I; + + tri0 GTS = glbl.GTS; + + bufif0 B1 (O, I, GTS); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUF_SSTL3_I_DCI.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUF_SSTL3_I_DCI.v new file mode 100644 index 0000000..915cc9d --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUF_SSTL3_I_DCI.v @@ -0,0 +1,35 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/OBUF_SSTL3_I_DCI.v,v 1.6 2007/05/23 21:43:41 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Output Buffer with SSTL3_I_DCI I/O Standard +// /___/ /\ Filename : OBUF_SSTL3_I_DCI.v +// \ \ / \ Timestamp : Thu Mar 25 16:43:29 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. + +`timescale 1 ps / 1 ps + + +module OBUF_SSTL3_I_DCI (O, I); + + output O; + + input I; + + tri0 GTS = glbl.GTS; + + bufif0 B1 (O, I, GTS); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUF_S_12.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUF_S_12.v new file mode 100644 index 0000000..527aaf9 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUF_S_12.v @@ -0,0 +1,35 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/OBUF_S_12.v,v 1.6 2007/05/23 21:43:41 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Output Buffer with Slow Slew 12 mA Drive +// /___/ /\ Filename : OBUF_S_12.v +// \ \ / \ Timestamp : Thu Mar 25 16:43:29 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. + +`timescale 1 ps / 1 ps + + +module OBUF_S_12 (O, I); + + output O; + + input I; + + tri0 GTS = glbl.GTS; + + bufif0 B1 (O, I, GTS); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUF_S_16.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUF_S_16.v new file mode 100644 index 0000000..764ca09 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUF_S_16.v @@ -0,0 +1,35 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/OBUF_S_16.v,v 1.6 2007/05/23 21:43:41 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Output Buffer with Slow Slew 16 mA Drive +// /___/ /\ Filename : OBUF_S_16.v +// \ \ / \ Timestamp : Thu Mar 25 16:43:29 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. + +`timescale 1 ps / 1 ps + + +module OBUF_S_16 (O, I); + + output O; + + input I; + + tri0 GTS = glbl.GTS; + + bufif0 B1 (O, I, GTS); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUF_S_2.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUF_S_2.v new file mode 100644 index 0000000..27bb3f3 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUF_S_2.v @@ -0,0 +1,35 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/OBUF_S_2.v,v 1.6 2007/05/23 21:43:41 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Output Buffer with Slow Slew 2 mA Drive +// /___/ /\ Filename : OBUF_S_2.v +// \ \ / \ Timestamp : Thu Mar 25 16:43:29 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. + +`timescale 1 ps / 1 ps + + +module OBUF_S_2 (O, I); + + output O; + + input I; + + tri0 GTS = glbl.GTS; + + bufif0 B1 (O, I, GTS); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUF_S_24.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUF_S_24.v new file mode 100644 index 0000000..b013f30 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUF_S_24.v @@ -0,0 +1,35 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/OBUF_S_24.v,v 1.6 2007/05/23 21:43:41 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Output Buffer with Slow Slew 24 mA Drive +// /___/ /\ Filename : OBUF_S_24.v +// \ \ / \ Timestamp : Thu Mar 25 16:43:29 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. + +`timescale 1 ps / 1 ps + + +module OBUF_S_24 (O, I); + + output O; + + input I; + + tri0 GTS = glbl.GTS; + + bufif0 B1 (O, I, GTS); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUF_S_4.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUF_S_4.v new file mode 100644 index 0000000..6de85cc --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUF_S_4.v @@ -0,0 +1,35 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/OBUF_S_4.v,v 1.6 2007/05/23 21:43:41 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Output Buffer with Slow Slew 4 mA Drive +// /___/ /\ Filename : OBUF_S_4.v +// \ \ / \ Timestamp : Thu Mar 25 16:43:30 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. + +`timescale 1 ps / 1 ps + + +module OBUF_S_4 (O, I); + + output O; + + input I; + + tri0 GTS = glbl.GTS; + + bufif0 B1 (O, I, GTS); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUF_S_6.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUF_S_6.v new file mode 100644 index 0000000..23915bf --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUF_S_6.v @@ -0,0 +1,35 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/OBUF_S_6.v,v 1.6 2007/05/23 21:43:41 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Output Buffer with Slow Slew 6 mA Drive +// /___/ /\ Filename : OBUF_S_6.v +// \ \ / \ Timestamp : Thu Mar 25 16:43:30 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. + +`timescale 1 ps / 1 ps + + +module OBUF_S_6 (O, I); + + output O; + + input I; + + tri0 GTS = glbl.GTS; + + bufif0 B1 (O, I, GTS); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUF_S_8.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUF_S_8.v new file mode 100644 index 0000000..6145409 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OBUF_S_8.v @@ -0,0 +1,35 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/OBUF_S_8.v,v 1.6 2007/05/23 21:43:41 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Output Buffer with Slow Slew 8 mA Drive +// /___/ /\ Filename : OBUF_S_8.v +// \ \ / \ Timestamp : Thu Mar 25 16:43:30 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. + +`timescale 1 ps / 1 ps + + +module OBUF_S_8 (O, I); + + output O; + + input I; + + tri0 GTS = glbl.GTS; + + bufif0 B1 (O, I, GTS); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/ODDR.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/ODDR.v new file mode 100644 index 0000000..9e9d10f --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/ODDR.v @@ -0,0 +1,154 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/virtex4/ODDR.v,v 1.9 2009/08/21 23:55:43 harikr Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2005 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Dual Data Rate Output D Flip-Flop +// /___/ /\ Filename : ODDR.v +// \ \ / \ Timestamp : Thu Mar 11 16:43:52 PST 2005 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 03/11/05 - Initialized outpus. +// 05/29/07 - Added wire declaration for internal signals +// 12/03/08 - CR 498674 added pulldown on R/S. +// 07/28/09 - CR 527698 According to holistic, CE has to be high for both rise/fall CLK +// - If CE is low on the rising edge, it has an effect of no change in the falling CLK. +// End Revision + +`timescale 1 ps / 1 ps + +module ODDR (Q, C, CE, D1, D2, R, S); + + output Q; + + input C; + input CE; + input D1; + input D2; + tri0 GSR = glbl.GSR; + input R; + input S; + + parameter DDR_CLK_EDGE = "OPPOSITE_EDGE"; + parameter INIT = 1'b0; + parameter SRTYPE = "SYNC"; + + pulldown P1 (R); + pulldown P2 (S); + + reg q_out = INIT, qd2_posedge_int; + + wire c_in; + wire ce_in; + wire d1_in; + wire d2_in; + wire gsr_in; + wire r_in; + wire s_in; + + + buf buf_c (c_in, C); + buf buf_ce (ce_in, CE); + buf buf_d1 (d1_in, D1); + buf buf_d2 (d2_in, D2); + buf buf_gsr (gsr_in, GSR); + buf buf_q (Q, q_out); + buf buf_r (r_in, R); + buf buf_s (s_in, S); + + + initial begin + + if ((INIT != 0) && (INIT != 1)) begin + $display("Attribute Syntax Error : The attribute INIT on ODDR instance %m is set to %d. Legal values for this attribute are 0 or 1.", INIT); + $finish; + end + + if ((DDR_CLK_EDGE != "OPPOSITE_EDGE") && (DDR_CLK_EDGE != "SAME_EDGE")) begin + $display("Attribute Syntax Error : The attribute DDR_CLK_EDGE on ODDR instance %m is set to %s. Legal values for this attribute are OPPOSITE_EDGE or SAME_EDGE.", DDR_CLK_EDGE); + $finish; + end + + if ((SRTYPE != "ASYNC") && (SRTYPE != "SYNC")) begin + $display("Attribute Syntax Error : The attribute SRTYPE on ODDR instance %m is set to %s. Legal values for this attribute are ASYNC or SYNC.", SRTYPE); + $finish; + end + + end // initial begin + + + always @(gsr_in or r_in or s_in) begin + if (gsr_in == 1'b1) begin + assign q_out = INIT; + assign qd2_posedge_int = INIT; + end + else if (gsr_in == 1'b0) begin + if (r_in == 1'b1 && SRTYPE == "ASYNC") begin + assign q_out = 1'b0; + assign qd2_posedge_int = 1'b0; + end + else if (r_in == 1'b0 && s_in == 1'b1 && SRTYPE == "ASYNC") begin + assign q_out = 1'b1; + assign qd2_posedge_int = 1'b1; + end + else if ((r_in == 1'b1 || s_in == 1'b1) && SRTYPE == "SYNC") begin + deassign q_out; + deassign qd2_posedge_int; + end + else if (r_in == 1'b0 && s_in == 1'b0) begin + deassign q_out; + deassign qd2_posedge_int; + end + end // if (gsr_in == 1'b0) + end // always @ (gsr_in or r_in or s_in) + + + always @(posedge c_in) begin + if (r_in == 1'b1) begin + q_out <= 1'b0; + qd2_posedge_int <= 1'b0; + end + else if (r_in == 1'b0 && s_in == 1'b1) begin + q_out <= 1'b1; + qd2_posedge_int <= 1'b1; + end + else if (ce_in == 1'b1 && r_in == 1'b0 && s_in == 1'b0) begin + q_out <= d1_in; + qd2_posedge_int <= d2_in; + end +// CR 527698 + else if (ce_in == 1'b0 && r_in == 1'b0 && s_in == 1'b0) begin + qd2_posedge_int <= q_out; + end + end // always @ (posedge c_in) + + + always @(negedge c_in) begin + if (r_in == 1'b1) + q_out <= 1'b0; + else if (r_in == 1'b0 && s_in == 1'b1) + q_out <= 1'b1; + else if (ce_in == 1'b1 && r_in == 1'b0 && s_in == 1'b0) begin + if (DDR_CLK_EDGE == "SAME_EDGE") + q_out <= qd2_posedge_int; + else if (DDR_CLK_EDGE == "OPPOSITE_EDGE") + q_out <= d2_in; + end + end // always @ (negedge c_in) + + + specify + + (C => Q) = (100, 100); + specparam PATHPULSE$ = 0; + + endspecify + +endmodule // ODDR diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/ODDR2.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/ODDR2.v new file mode 100644 index 0000000..8b00d41 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/ODDR2.v @@ -0,0 +1,197 @@ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Dual Data Rate Output D Flip-Flop +// /___/ /\ Filename : ODDR2.v +// \ \ / \ Timestamp : Thu Mar 25 16:43:52 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 08/20/08 - CR 478850 added pulldown on R/S and pullup on CE. +// 01/12/09 - IR 503207 Reworked C0/C1 alignments +// 06/24/09 - CR 525390 Fixed delta cycle race condition using generate statements +// End Revision + +`timescale 1 ps / 1 ps + +module ODDR2 (Q, C0, C1, CE, D0, D1, R, S); + + output Q; + + input C0; + input C1; + input CE; + input D0; + input D1; + tri0 GSR = glbl.GSR; + input R; + input S; + + parameter DDR_ALIGNMENT = "NONE"; + parameter INIT = 1'b0; + parameter SRTYPE = "SYNC"; + + pullup P1 (CE); + pulldown P2 (R); + pulldown P3 (S); + + reg q_out, q_d1_c0_out_int; +// wire PC0, PC1; + + buf buf_q (Q, q_out); + + + initial begin + + if ((INIT != 1'b0) && (INIT != 1'b1)) begin + $display("Attribute Syntax Error : The attribute INIT on ODDR2 instance %m is set to %d. Legal values for this attribute are 0 or 1.", INIT); + $finish; + end + + if ((DDR_ALIGNMENT != "NONE") && (DDR_ALIGNMENT != "C0") && (DDR_ALIGNMENT != "C1")) begin + $display("Attribute Syntax Error : The attribute DDR_ALIGNMENT on ODDR2 instance %m is set to %s. Legal values for this attribute are NONE, C0 or C1.", DDR_ALIGNMENT); + $finish; + end + + if ((SRTYPE != "ASYNC") && (SRTYPE != "SYNC")) begin + $display("Attribute Syntax Error : The attribute SRTYPE on ODDR2 instance %m is set to %s. Legal values for this attribute are ASYNC or SYNC.", SRTYPE); + $finish; + end + + end // initial begin + + + always @(GSR or R or S) begin + + if (GSR == 1) begin + + assign q_out = INIT; + assign q_d1_c0_out_int = INIT; + + end + else begin + + deassign q_out; + deassign q_d1_c0_out_int; + + if (SRTYPE == "ASYNC") begin + if (R == 1) begin + assign q_out = 0; + assign q_d1_c0_out_int = 0; + end + else if (R == 0 && S == 1) begin + assign q_out = 1; + assign q_d1_c0_out_int = 1; + end + end // if (SRTYPE == "ASYNC") + + end // if (GSR == 1'b0) + + end // always @ (GSR or R or S) + +// assign PC0 = ((DDR_ALIGNMENT== "C0") || (DDR_ALIGNMENT== "NONE"))? C0 : C1; +// assign PC1 = ((DDR_ALIGNMENT== "C0") || (DDR_ALIGNMENT== "NONE"))? C1 : C0; + + generate if((DDR_ALIGNMENT== "C0") || (DDR_ALIGNMENT== "NONE")) + begin + + always @(posedge C0) begin + + if (R == 1 && SRTYPE == "SYNC") begin + q_out <= 0; + q_d1_c0_out_int <= 0; + end + else if (R == 0 && S == 1 && SRTYPE == "SYNC") begin + q_out <= 1; + q_d1_c0_out_int <= 1; + end + else if (CE == 1 && R == 0 && S == 0) begin + q_out <= D0; + q_d1_c0_out_int <= D1 ; + end // if (CE == 1 && R == 0 && S == 0) + + end // always @ (posedge C0) + + + always @(posedge C1) begin + + if (R == 1 && SRTYPE == "SYNC") begin + q_out <= 0; + end + else if (R == 0 && S == 1 && SRTYPE == "SYNC") begin + q_out <= 1; + end + else if (CE == 1 && R == 0 && S == 0) begin + + if (DDR_ALIGNMENT == "NONE") + q_out <= D1; + else + q_out <= q_d1_c0_out_int; + + + end // if (CE == 1 && R == 0 && S == 0) + + end // always @ (posedge C1) + end + + + else + begin + + always @(posedge C1) begin + + if (R == 1 && SRTYPE == "SYNC") begin + q_out <= 0; + q_d1_c0_out_int <= 0; + end + else if (R == 0 && S == 1 && SRTYPE == "SYNC") begin + q_out <= 1; + q_d1_c0_out_int <= 1; + end + else if (CE == 1 && R == 0 && S == 0) begin + q_out <= D0; + q_d1_c0_out_int <= D1 ; + end // if (CE == 1 && R == 0 && S == 0) + + end // always @ (posedge C1) + + + always @(posedge C0) begin + + if (R == 1 && SRTYPE == "SYNC") begin + q_out <= 0; + end + else if (R == 0 && S == 1 && SRTYPE == "SYNC") begin + q_out <= 1; + end + else if (CE == 1 && R == 0 && S == 0) begin + + if (DDR_ALIGNMENT == "NONE") + q_out <= D1; + else + q_out <= q_d1_c0_out_int; + + + end // if (CE == 1 && R == 0 && S == 0) + + end // always @ (posedge C0) + end + endgenerate + + specify + + if (C0) (C0 => Q) = (100, 100); + if (C1) (C1 => Q) = (100, 100); + specparam PATHPULSE$ = 0; + + endspecify + +endmodule // ODDR2 + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OFDDRCPE.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OFDDRCPE.v new file mode 100644 index 0000000..871612e --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OFDDRCPE.v @@ -0,0 +1,43 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/OFDDRCPE.v,v 1.4 2005/03/14 22:32:58 yanx Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Dual Data Rate Output D Flip-Flop with Asynchronous Clear and Preset and Clock Enable +// /___/ /\ Filename : OFDDRCPE.v +// \ \ / \ Timestamp : Thu Mar 25 16:43:30 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// End Revision + +`timescale 1 ps / 1 ps + +module OFDDRCPE (Q, C0, C1, CE, CLR, D0, D1, PRE); + + output Q; + + input C0, C1, CE, CLR, D0, D1, PRE; + + wire q_out; + + FDDRCPE F0 (.C0(C0), + .C1(C1), + .CE(CE), + .CLR(CLR), + .D0(D0), + .D1(D1), + .PRE(PRE), + .Q(q_out)); + defparam F0.INIT = 1'b0; + + OBUF O1 (.I(q_out), + .O(Q)); + +endmodule diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OFDDRRSE.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OFDDRRSE.v new file mode 100644 index 0000000..0317613 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OFDDRRSE.v @@ -0,0 +1,43 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/OFDDRRSE.v,v 1.4 2005/03/14 22:32:58 yanx Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Dual Data Rate Output D Flip-Flop with Synchronous Reset and Set and Clock Enable +// /___/ /\ Filename : OFDDRRSE.v +// \ \ / \ Timestamp : Thu Mar 25 16:43:30 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// End Revision + +`timescale 1 ps / 1 ps + +module OFDDRRSE (Q, C0, C1, CE, D0, D1, R, S); + + output Q; + + input C0, C1, CE, D0, D1, R, S; + + wire q_out; + + FDDRRSE F0 (.C0(C0), + .C1(C1), + .CE(CE), + .R(R), + .D0(D0), + .D1(D1), + .S(S), + .Q(q_out)); + defparam F0.INIT = 1'b0; + + OBUF O1 (.I(q_out), + .O(Q)); + +endmodule diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OFDDRTCPE.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OFDDRTCPE.v new file mode 100644 index 0000000..bd69075 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OFDDRTCPE.v @@ -0,0 +1,44 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/OFDDRTCPE.v,v 1.4 2005/03/14 22:32:58 yanx Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Dual Data Rate Output D Flip-Flop with 3-State Output, Asynchronous Clear and Preset and Clock Enable +// /___/ /\ Filename : OFDDRTCPE.v +// \ \ / \ Timestamp : Thu Mar 25 16:43:30 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// End Revision + +`timescale 1 ps / 1 ps + +module OFDDRTCPE (O, C0, C1, CE, CLR, D0, D1, PRE, T); + + output O; + + input C0, C1, CE, CLR, D0, D1, PRE, T; + + wire q_out; + + FDDRCPE F0 (.C0(C0), + .C1(C1), + .CE(CE), + .CLR(CLR), + .D0(D0), + .D1(D1), + .PRE(PRE), + .Q(q_out)); + defparam F0.INIT = 1'b0; + + OBUFT O1 (.I(q_out), + .T(T), + .O(O)); + +endmodule diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OFDDRTRSE.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OFDDRTRSE.v new file mode 100644 index 0000000..7751584 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OFDDRTRSE.v @@ -0,0 +1,44 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/OFDDRTRSE.v,v 1.4 2005/03/14 22:32:58 yanx Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Dual Data Rate Output D Flip-Flop with 3-State Output, Synchronous Reset and Set and Clock Enable +// /___/ /\ Filename : OFDDRTRSE.v +// \ \ / \ Timestamp : Thu Mar 25 16:43:30 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// End Revision + +`timescale 1 ps / 1 ps + +module OFDDRTRSE (O, C0, C1, CE, D0, D1, R, S, T); + + output O; + + input C0, C1, CE, D0, D1, R, S, T; + + wire q_out; + + FDDRRSE F0 (.C0(C0), + .C1(C1), + .CE(CE), + .R(R), + .D0(D0), + .D1(D1), + .S(S), + .Q(q_out)); + defparam F0.INIT = 1'b0; + + OBUFT O1 (.I(q_out), + .T(T), + .O(O)); + +endmodule diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OR2.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OR2.v new file mode 100644 index 0000000..8f237b2 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OR2.v @@ -0,0 +1,33 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/OR2.v,v 1.6 2007/05/23 21:43:44 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / 2-input OR Gate +// /___/ /\ Filename : OR2.v +// \ \ / \ Timestamp : Thu Mar 25 16:43:30 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. + +`timescale 1 ps / 1 ps + + +module OR2 (O, I0, I1); + + output O; + + input I0, I1; + + or O1 (O, I0, I1); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OR2B1.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OR2B1.v new file mode 100644 index 0000000..cfd5e8b --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OR2B1.v @@ -0,0 +1,37 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/OR2B1.v,v 1.6 2007/05/23 21:43:44 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / 2-input OR Gate +// /___/ /\ Filename : OR2B1.v +// \ \ / \ Timestamp : Thu Mar 25 16:43:30 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. +// 05/23/07 - Added wire declaration for internal signals. + +`timescale 1 ps / 1 ps + + +module OR2B1 (O, I0, I1); + + output O; + + input I0, I1; + + wire i0_inv; + + not N0 (i0_inv, I0); + or O1 (O, i0_inv, I1); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OR2B2.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OR2B2.v new file mode 100644 index 0000000..72a2e33 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OR2B2.v @@ -0,0 +1,39 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/OR2B2.v,v 1.6 2007/05/23 21:43:44 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / 2-input OR Gate +// /___/ /\ Filename : OR2B2.v +// \ \ / \ Timestamp : Thu Mar 25 16:43:30 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. +// 05/23/07 - Added wire declaration for internal signals. + +`timescale 1 ps / 1 ps + + +module OR2B2 (O, I0, I1); + + output O; + + input I0, I1; + + wire i0_inv; + wire i1_inv; + + not N1 (i1_inv, I1); + not N0 (i0_inv, I0); + or O1 (O, i0_inv, i1_inv); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OR2L.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OR2L.v new file mode 100644 index 0000000..2aac005 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OR2L.v @@ -0,0 +1,36 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/blanc/OR2L.v,v 1.3 2008/10/08 21:02:10 yanx Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Latch used as 2-input OR Gate +// /___/ /\ Filename : OR2L.v +// \ \ / \ Timestamp : Tue Feb 26 11:11:42 PST 2008 +// \___\/\___\ +// +// Revision: +// 02/26/08 - Initial version. +// 04/01/08 - Add GSR. +// End Revision + +`timescale 1 ps / 1 ps + +module OR2L (O, DI, SRI); + + output O; + + input SRI, DI; + + tri0 GSR = glbl.GSR; + + wire o_out; + + assign O = (GSR) ? 0 : o_out; + or O1 (o_out, SRI, DI); + +endmodule diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OR3.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OR3.v new file mode 100644 index 0000000..d7223c8 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OR3.v @@ -0,0 +1,33 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/OR3.v,v 1.6 2007/05/23 21:43:44 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / 3-input OR Gate +// /___/ /\ Filename : OR3.v +// \ \ / \ Timestamp : Thu Mar 25 16:43:31 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. + +`timescale 1 ps / 1 ps + + +module OR3 (O, I0, I1, I2); + + output O; + + input I0, I1, I2; + + or O1 (O, I0, I1, I2); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OR3B1.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OR3B1.v new file mode 100644 index 0000000..54d8015 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OR3B1.v @@ -0,0 +1,37 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/OR3B1.v,v 1.6 2007/05/23 21:43:44 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / 3-input OR Gate +// /___/ /\ Filename : OR3B1.v +// \ \ / \ Timestamp : Thu Mar 25 16:43:31 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. +// 05/23/07 - Added wire declaration for internal signals. + +`timescale 1 ps / 1 ps + + +module OR3B1 (O, I0, I1, I2); + + output O; + + input I0, I1, I2; + + wire i0_inv; + + not N0 (i0_inv, I0); + or O1 (O, i0_inv, I1, I2); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OR3B2.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OR3B2.v new file mode 100644 index 0000000..eb5a87e --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OR3B2.v @@ -0,0 +1,39 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/OR3B2.v,v 1.6 2007/05/23 21:43:44 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / 3-input OR Gate +// /___/ /\ Filename : OR3B2.v +// \ \ / \ Timestamp : Thu Mar 25 16:43:31 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. +// 05/23/07 - Added wire declaration for internal signals. + +`timescale 1 ps / 1 ps + + +module OR3B2 (O, I0, I1, I2); + + output O; + + input I0, I1, I2; + + wire i0_inv; + wire i1_inv; + + not N1 (i1_inv, I1); + not N0 (i0_inv, I0); + or O1 (O, i0_inv, i1_inv, I2); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OR3B3.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OR3B3.v new file mode 100644 index 0000000..b08079d --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OR3B3.v @@ -0,0 +1,41 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/OR3B3.v,v 1.6 2007/05/23 21:43:44 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / 5-input OR Gate +// /___/ /\ Filename : OR3B3.v +// \ \ / \ Timestamp : Thu Mar 25 16:43:31 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. +// 05/23/07 - Added wire declaration for internal signals. + +`timescale 1 ps / 1 ps + + +module OR3B3 (O, I0, I1, I2); + + output O; + + input I0, I1, I2; + + wire i0_inv; + wire i1_inv; + wire i2_inv; + + not N2 (i2_inv, I2); + not N1 (i1_inv, I1); + not N0 (i0_inv, I0); + or O1 (O, i0_inv, i1_inv, i2_inv); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OR4.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OR4.v new file mode 100644 index 0000000..c755c32 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OR4.v @@ -0,0 +1,33 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/OR4.v,v 1.6 2007/05/23 21:43:44 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / 4-input OR Gate +// /___/ /\ Filename : OR4.v +// \ \ / \ Timestamp : Thu Mar 25 16:43:31 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. + +`timescale 1 ps / 1 ps + + +module OR4 (O, I0, I1, I2, I3); + + output O; + + input I0, I1, I2, I3; + + or O1 (O, I0, I1, I2, I3); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OR4B1.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OR4B1.v new file mode 100644 index 0000000..efebc86 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OR4B1.v @@ -0,0 +1,37 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/OR4B1.v,v 1.6 2007/05/23 21:43:44 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / 4-input OR Gate +// /___/ /\ Filename : OR4B1.v +// \ \ / \ Timestamp : Thu Mar 25 16:43:31 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. +// 05/23/07 - Added wire declaration for internal signals. + +`timescale 1 ps / 1 ps + + +module OR4B1 (O, I0, I1, I2, I3); + + output O; + + input I0, I1, I2, I3; + + wire i0_inv; + + not N0 (i0_inv, I0); + or O1 (O, i0_inv, I1, I2, I3); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OR4B2.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OR4B2.v new file mode 100644 index 0000000..fcb5752 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OR4B2.v @@ -0,0 +1,39 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/OR4B2.v,v 1.6 2007/05/23 21:43:44 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / 4-input OR Gate +// /___/ /\ Filename : OR4B2.v +// \ \ / \ Timestamp : Thu Mar 25 16:43:31 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. +// 05/23/07 - Added wire declaration for internal signals. + +`timescale 1 ps / 1 ps + + +module OR4B2 (O, I0, I1, I2, I3); + + output O; + + input I0, I1, I2, I3; + + wire i0_inv; + wire i1_inv; + + not N1 (i1_inv, I1); + not N0 (i0_inv, I0); + or O1 (O, i0_inv, i1_inv, I2, I3); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OR4B3.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OR4B3.v new file mode 100644 index 0000000..c9a8804 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OR4B3.v @@ -0,0 +1,41 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/OR4B3.v,v 1.6 2007/05/23 21:43:44 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / 4-input OR Gate +// /___/ /\ Filename : OR4B3.v +// \ \ / \ Timestamp : Thu Mar 25 16:43:31 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. +// 05/23/07 - Added wire declaration for internal signals. + +`timescale 1 ps / 1 ps + + +module OR4B3 (O, I0, I1, I2, I3); + + output O; + + input I0, I1, I2, I3; + + wire i0_inv; + wire i1_inv; + wire i2_inv; + + not N2 (i2_inv, I2); + not N1 (i1_inv, I1); + not N0 (i0_inv, I0); + or O1 (O, i0_inv, i1_inv, i2_inv, I3); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OR4B4.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OR4B4.v new file mode 100644 index 0000000..7a60ae6 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OR4B4.v @@ -0,0 +1,43 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/OR4B4.v,v 1.6 2007/05/23 21:43:44 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / 4-input OR Gate +// /___/ /\ Filename : OR4B4.v +// \ \ / \ Timestamp : Thu Mar 25 16:43:31 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. +// 05/23/07 - Added wire declaration for internal signals. + +`timescale 1 ps / 1 ps + + +module OR4B4 (O, I0, I1, I2, I3); + + output O; + + input I0, I1, I2, I3; + + wire i0_inv; + wire i1_inv; + wire i2_inv; + wire i3_inv; + + not N3 (i3_inv, I3); + not N2 (i2_inv, I2); + not N1 (i1_inv, I1); + not N0 (i0_inv, I0); + or O1 (O, i0_inv, i1_inv, i2_inv, i3_inv); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OR5.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OR5.v new file mode 100644 index 0000000..20dbd2b --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OR5.v @@ -0,0 +1,33 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/OR5.v,v 1.6 2007/05/23 21:43:44 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / 5-input OR Gate +// /___/ /\ Filename : OR5.v +// \ \ / \ Timestamp : Thu Mar 25 16:43:31 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. + +`timescale 1 ps / 1 ps + + +module OR5 (O, I0, I1, I2, I3, I4); + + output O; + + input I0, I1, I2, I3, I4; + + or O1 (O, I0, I1, I2, I3, I4); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OR5B1.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OR5B1.v new file mode 100644 index 0000000..c49e3cb --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OR5B1.v @@ -0,0 +1,37 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/OR5B1.v,v 1.6 2007/05/23 21:43:44 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / 5-input OR Gate +// /___/ /\ Filename : OR5B1.v +// \ \ / \ Timestamp : Thu Mar 25 16:43:32 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. +// 05/23/07 - Added wire declaration for internal signals. + +`timescale 1 ps / 1 ps + + +module OR5B1 (O, I0, I1, I2, I3, I4); + + output O; + + input I0, I1, I2, I3, I4; + + wire i0_inv; + + not N0 (i0_inv, I0); + or O1 (O, i0_inv, I1, I2, I3, I4); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OR5B2.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OR5B2.v new file mode 100644 index 0000000..6115209 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OR5B2.v @@ -0,0 +1,39 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/OR5B2.v,v 1.6 2007/05/23 21:43:44 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / 5-input OR Gate +// /___/ /\ Filename : OR5B2.v +// \ \ / \ Timestamp : Thu Mar 25 16:43:32 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. +// 05/23/07 - Added wire declaration for internal signals. + +`timescale 1 ps / 1 ps + + +module OR5B2 (O, I0, I1, I2, I3, I4); + + output O; + + input I0, I1, I2, I3, I4; + + wire i0_inv; + wire i1_inv; + + not N1 (i1_inv, I1); + not N0 (i0_inv, I0); + or O1 (O, i0_inv, i1_inv, I2, I3, I4); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OR5B3.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OR5B3.v new file mode 100644 index 0000000..44f847a --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OR5B3.v @@ -0,0 +1,41 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/OR5B3.v,v 1.6 2007/05/23 21:43:44 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / 5-input OR Gate +// /___/ /\ Filename : OR5B3.v +// \ \ / \ Timestamp : Thu Mar 25 16:43:32 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. +// 05/23/07 - Added wire declaration for internal signals. + +`timescale 1 ps / 1 ps + + +module OR5B3 (O, I0, I1, I2, I3, I4); + + output O; + + input I0, I1, I2, I3, I4; + + wire i0_inv; + wire i1_inv; + wire i2_inv; + + not N2 (i2_inv, I2); + not N1 (i1_inv, I1); + not N0 (i0_inv, I0); + or O1 (O, i0_inv, i1_inv, i2_inv, I3, I4); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OR5B4.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OR5B4.v new file mode 100644 index 0000000..aca892f --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OR5B4.v @@ -0,0 +1,43 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/OR5B4.v,v 1.6 2007/05/23 21:43:44 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / 5-input OR Gate +// /___/ /\ Filename : OR5B4.v +// \ \ / \ Timestamp : Thu Mar 25 16:43:32 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. +// 05/23/07 - Added wire declaration for internal signals. + +`timescale 1 ps / 1 ps + + +module OR5B4 (O, I0, I1, I2, I3, I4); + + output O; + + input I0, I1, I2, I3, I4; + + wire i0_inv; + wire i1_inv; + wire i2_inv; + wire i3_inv; + + not N3 (i3_inv, I3); + not N2 (i2_inv, I2); + not N1 (i1_inv, I1); + not N0 (i0_inv, I0); + or O1 (O, i0_inv, i1_inv, i2_inv, i3_inv, I4); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OR5B5.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OR5B5.v new file mode 100644 index 0000000..9f85007 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OR5B5.v @@ -0,0 +1,45 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/OR5B5.v,v 1.6 2007/05/23 21:43:44 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / 5-input OR Gate +// /___/ /\ Filename : OR5B5.v +// \ \ / \ Timestamp : Thu Mar 25 16:43:32 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. +// 05/23/07 - Added wire declaration for internal signals. + +`timescale 1 ps / 1 ps + + +module OR5B5 (O, I0, I1, I2, I3, I4); + + output O; + + input I0, I1, I2, I3, I4; + + wire i0_inv; + wire i1_inv; + wire i2_inv; + wire i3_inv; + wire i4_inv; + + not N4 (i4_inv, I4); + not N3 (i3_inv, I3); + not N2 (i2_inv, I2); + not N1 (i1_inv, I1); + not N0 (i0_inv, I0); + or O1 (O, i0_inv, i1_inv, i2_inv, i3_inv, i4_inv); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/ORCY.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/ORCY.v new file mode 100644 index 0000000..b45ccb1 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/ORCY.v @@ -0,0 +1,33 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/ORCY.v,v 1.6 2007/05/23 21:43:44 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / OR with Carry Logic +// /___/ /\ Filename : ORCY.v +// \ \ / \ Timestamp : Thu Mar 25 16:43:32 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. + +`timescale 1 ps / 1 ps + + +module ORCY (O, CI, I); + + output O; + + input CI, I; + + or X1 (O, CI, I); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OSERDES.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OSERDES.v new file mode 100644 index 0000000..33ab789 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OSERDES.v @@ -0,0 +1,953 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/virtex4/OSERDES.v,v 1.11 2008/02/09 00:37:36 fphillip Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2005 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Timing Simulation Library Component +// / / Source Synchronous Output Serializer +// /___/ /\ Filename : OSERDES.v +// \ \ / \ Timestamp : Thu Mar 11 16:44:07 PST 2005 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 03/11/05 - Initialized outpus. +// 06/06/07 - Fixed timescale values +// 01/08/08 - CR 458156 -- enabled TRISTATE_WIDTH to be 1 in DDR mode. +// End Revision + +`timescale 1 ps / 1 ps + +module OSERDES (OQ, SHIFTOUT1, SHIFTOUT2, TQ, + CLK, CLKDIV, D1, D2, D3, D4, D5, D6, OCE, REV, SHIFTIN1, SHIFTIN2, SR, T1, T2, T3, T4, TCE); + + parameter DATA_RATE_OQ = "DDR"; + parameter DATA_RATE_TQ = "DDR"; + parameter integer DATA_WIDTH = 4; + parameter INIT_OQ = 1'b0; + parameter INIT_TQ = 1'b0; + parameter SERDES_MODE = "MASTER"; + parameter SRVAL_OQ = 1'b0; + parameter SRVAL_TQ = 1'b0; + parameter integer TRISTATE_WIDTH = 4; + + output OQ; + output SHIFTOUT1; + output SHIFTOUT2; + output TQ; + + input CLK; + input CLKDIV; + input D1; + input D2; + input D3; + input D4; + input D5; + input D6; + tri0 GSR = glbl.GSR; + input OCE; + input REV; + input SHIFTIN1; + input SHIFTIN2; + input SR; + input T1; + input T2; + input T3; + input T4; + input TCE; + + reg c23, c45, c67; + reg t1r, t2r, t3r, t4r; + reg io_sdata_edge, io_odata_edge, io_ddr_data; + reg iot_sdata_edge, iot_odata_edge, iot_ddr_data; + reg data1, data2, data3, data4, data5, data6; + reg serdes_mode_int, serdes_int; + reg data_rate_oq_int, ddr_clk_edge_int; + reg [1:0] data_rate_tq_int, tristate_width_int; + reg [1:0] sel; + reg d1r, d2r, d3r, d4r, d5r, d6r; + reg q0, q1, q2, q3; + reg d1rnk2, d2rnk2, d2nrnk2, d3rnk2, d4rnk2, d5rnk2, d6rnk2; + reg qt1, qt2, qt2n; + reg load, qhr, qlr, mux; + reg data1t, data2t; + reg oq_out = INIT_OQ, tq_out = INIT_TQ; + reg [3:0] data_width_int; + + wire oqsr, oqrev; + wire tqsr, tqrev; + wire c2p, c3; + wire [2:0] sel1_4; + wire [3:0] sel5_6; + wire [4:0] sel_tri; + wire [6:0] seltq; + wire [3:0] seloq; + + wire shiftout1_out; + wire shiftout2_out; + + wire clk_in; + wire clkdiv_in; + wire d1_in; + wire d2_in; + wire d3_in; + wire d4_in; + wire d5_in; + wire d6_in; + wire gsr_in; + wire oce_in; + wire sr_in; + wire rev_in; + wire shiftin1_in; + wire shiftin2_in; + wire t1_in; + wire t2_in; + wire t3_in; + wire t4_in; + wire tce_in; + + buf b_oq (OQ, oq_out); + buf b_shiftout1 (SHIFTOUT1, shiftout1_out); + buf b_shiftout2 (SHIFTOUT2, shiftout2_out); + buf b_tq (TQ, tq_out); + + buf b_clk (clk_in, CLK); + buf b_clkdiv (clkdiv_in, CLKDIV); + buf b_d1 (d1_in, D1); + buf b_d2 (d2_in, D2); + buf b_d3 (d3_in, D3); + buf b_d4 (d4_in, D4); + buf b_d5 (d5_in, D5); + buf b_d6 (d6_in, D6); + buf b_gsr (gsr_in, GSR); + buf b_oce (oce_in, OCE); + buf b_r (sr_in, SR); + buf b_s (rev_in, REV); + buf b_shiftin1 (shiftin1_in, SHIFTIN1); + buf b_shiftin2 (shiftin2_in, SHIFTIN2); + buf b_t1 (t1_in, T1); + buf b_t2 (t2_in, T2); + buf b_t3 (t3_in, T3); + buf b_t4 (t4_in, T4); + buf b_tce (tce_in, TCE); + + // workaround for XSIM + wire rev_in_AND_NOT_sr_in = rev_in & !sr_in; + wire NOT_rev_in_AND_sr_in = !rev_in & sr_in; + +///////////////////////////////////////////////////////// +// +// Delay assignments +// +///////////////////////////////////////////////////////// + +// Data output delays + + localparam io_ffd = 1; // clock to out delay for flip flops driven by clk + localparam io_ffcd = 1; // clock to out delay for flip flops driven by clkdiv + localparam io_mxd = 1; // 60 ps mux delay + localparam io_mxr1 = 1; // mux before 2nd rank of flops + + // Programmable load generator + localparam ffdcnt = 1; + localparam mxdcnt = 1; + localparam ffrst = 145; // clock to out delay for flop in PLSG + + // Tristate output delays + localparam iot_ffd = 1; + localparam iot_mxd = 1; +///////////////////////////////////////////////////////////// + + + always @(gsr_in) + + if (gsr_in) begin + + assign oq_out = INIT_OQ; + assign d1rnk2 = INIT_OQ; + assign d2rnk2 = INIT_OQ; + assign d2nrnk2 = INIT_OQ; + assign d6rnk2 = 1'b0; + assign d5rnk2 = 1'b0; + assign d4rnk2 = 1'b0; + assign d3rnk2 = 1'b0; + + assign d6r = 1'b0; + assign d5r = 1'b0; + assign d4r = 1'b0; + assign d3r = 1'b0; + assign d2r = 1'b0; + assign d1r = 1'b0; + +// PLG + assign q3 = 1'b0; + assign q2 = 1'b0; + assign q1 = 1'b0; + assign q0 = 1'b0; + +// Tristate output + assign tq_out = INIT_TQ; + assign qt1 = INIT_TQ; + assign qt2 = INIT_TQ; + assign qt2n = INIT_TQ; + assign t4r = 1'b0; + assign t3r = 1'b0; + assign t2r = 1'b0; + assign t1r = 1'b0; + + end + else begin + + deassign oq_out; + deassign d1rnk2; + deassign d2rnk2; + deassign d2nrnk2; + deassign d6rnk2; + deassign d5rnk2; + deassign d4rnk2; + deassign d3rnk2; + deassign d6r; + deassign d5r; + deassign d4r; + deassign d3r; + deassign d2r; + deassign d1r; + +// PLG + deassign q3; + deassign q2; + deassign q1; + deassign q0; + +// Tristate output + deassign tq_out; + deassign qt1; + deassign qt2; + deassign qt2n; + deassign t4r; + deassign t3r; + deassign t2r; + deassign t1r; + + end + + + initial begin + + case (SERDES_MODE) + + "MASTER" : serdes_mode_int <= 1'b0; + "SLAVE" : serdes_mode_int <= 1'b1; + default : begin + $display("Attribute Syntax Error : The attribute SERDES_MODE on OSERDES instance %m is set to %s. Legal values for this attribute are MASTER or SLAVE", SERDES_MODE); + $finish; + end + + endcase // case(SERDES_MODE) + + + serdes_int <= 1'b1; // SERDES = TRUE + + ddr_clk_edge_int <= 1'b1; // DDR_CLK_EDGE = SAME_EDGE + + + case (DATA_RATE_OQ) + + "SDR" : data_rate_oq_int <= 1'b1; + "DDR" : data_rate_oq_int <= 1'b0; + default : begin + $display("Attribute Syntax Error : The attribute DATA_RATE_OQ on OSERDES instance %m is set to %s. Legal values for this attribute are SDR or DDR", DATA_RATE_OQ); + $finish; + end + + endcase // case(DATA_RATE_OQ) + + + case (DATA_WIDTH) + + 2, 3, 4, 5, 6, 7, 8, 10 : data_width_int = DATA_WIDTH[3:0]; + default : begin + $display("Attribute Syntax Error : The attribute DATA_WIDTH on OSERDES instance %m is set to %d. Legal values for this attribute are 2, 3, 4, 5, 6, 7, 8, or 10", DATA_WIDTH); + $finish; + end + + endcase // case(DATA_WIDTH) + + + case (DATA_RATE_TQ) + + "BUF" : data_rate_tq_int <= 2'b00; + "SDR" : data_rate_tq_int <= 2'b01; + "DDR" : data_rate_tq_int <= 2'b10; + default : begin + $display("Attribute Syntax Error : The attribute DATA_RATE_TQ on OSERDES instance %m is set to %s. Legal values for this attribute are BUF, SDR or DDR", DATA_RATE_TQ); + $finish; + end + + endcase // case(DATA_RATE_TQ) + + + case (TRISTATE_WIDTH) + + 1 : tristate_width_int <= 2'b00; + 2 : tristate_width_int <= 2'b01; + 4 : tristate_width_int <= 2'b10; + default : begin + $display("Attribute Syntax Error : The attribute TRISTATE_WIDTH on OSERDES instance %m is set to %d. Legal values for this attribute are 1, 2 or 4", TRISTATE_WIDTH); + $finish; + end + + endcase // case(TRISTATE_WIDTH) + + + end // initial begin + + + assign shiftout1_out = d3rnk2 & serdes_mode_int; + + assign shiftout2_out = d4rnk2 & serdes_mode_int; + + assign c2p = (clk_in & ddr_clk_edge_int) | (!clk_in & !ddr_clk_edge_int); + + assign c3 = !c2p; + + assign sel1_4 = {serdes_int, load, data_rate_oq_int}; + + assign sel5_6 = {serdes_int, serdes_mode_int, load, data_rate_oq_int}; + +// Tristate output + assign sel_tri = {load, data_rate_tq_int, tristate_width_int}; + + assign seloq = {oce_in, data_rate_oq_int, oqsr, oqrev}; + + assign seltq = {tce_in, data_rate_tq_int, tristate_width_int, tqsr, tqrev}; + + assign oqsr = (sr_in & !SRVAL_OQ) | (rev_in & SRVAL_OQ); + + assign oqrev = (sr_in & SRVAL_OQ) | (rev_in & !SRVAL_OQ); + + assign tqsr = (sr_in & !SRVAL_TQ) | (rev_in & SRVAL_TQ); + + assign tqrev = (sr_in & SRVAL_TQ) | (rev_in & !SRVAL_TQ); + +// 3 flops to create DDR operations of 4 latches +// asynchronous operation + always @ (posedge clk_in or posedge sr_in or posedge rev_in or posedge rev_in_AND_NOT_sr_in or posedge NOT_rev_in_AND_sr_in) begin + + if (sr_in == 1'b1 & !(rev_in == 1'b1 & SRVAL_OQ == 1'b1)) + + d1rnk2 <= # io_ffd SRVAL_OQ; + + else if (rev_in == 1'b1) + + d1rnk2 <= # io_ffd !SRVAL_OQ; + + else if (oce_in == 1'b1) + + d1rnk2 <= # io_ffd data1; + + else if (oce_in == 1'b0) // to match with HW + + d1rnk2 <= # io_ffd oq_out; + + end // always @ (posedge clk_in or posedge sr_in or posedge rev_in or posedge rev_in_AND_NOT_sr_in or posedge NOT_rev_in_AND_sr_in) + + +// Representation of 2nd latch +// asynchronous operation + always @ (posedge c2p or posedge sr_in or posedge rev_in or posedge rev_in_AND_NOT_sr_in or posedge NOT_rev_in_AND_sr_in) begin + + if (sr_in == 1'b1 & !(rev_in == 1'b1 & SRVAL_OQ == 1'b1)) + + d2rnk2 <= # io_ffd SRVAL_OQ; + + else if (rev_in == 1'b1) + + d2rnk2 <= # io_ffd !SRVAL_OQ; + + else if (oce_in == 1'b1) + + d2rnk2 <= # io_ffd data2; + + else if (oce_in == 1'b0) // to match with HW + + d2rnk2 <= # io_ffd oq_out; + + end // always @ (posedge c2p or posedge sr_in or posedge rev_in or posedge rev_in_AND_NOT_sr_in or posedge NOT_rev_in_AND_sr_in) + + +// Representation of 3rd flop ( latch and output latch) +// asynchronous operation + always @ (posedge c3 or posedge sr_in or posedge rev_in or posedge rev_in_AND_NOT_sr_in or posedge NOT_rev_in_AND_sr_in) begin + + if (sr_in == 1'b1 & !(rev_in == 1'b1 & SRVAL_OQ == 1'b1)) + + d2nrnk2 <= # io_ffd SRVAL_OQ; + + else if (rev_in == 1'b1) + + d2nrnk2 <= # io_ffd !SRVAL_OQ; + + else if (oce_in == 1'b1) + + d2nrnk2 <= # io_ffd d2rnk2; + + else if (oce_in == 1'b0) // to match with HW + + d2nrnk2 <= # io_ffd oq_out; + + end // always @ (posedge c3 or posedge sr_in or posedge rev_in or posedge rev_in_AND_NOT_sr_in or posedge NOT_rev_in_AND_sr_in) + + +// last 4 flops which only have reset and init +// asynchronous operation + always @ (posedge clk_in or posedge sr_in) begin + + if (sr_in == 1'b1) begin + + d3rnk2 <= # io_ffd 1'b0; + d4rnk2 <= # io_ffd 1'b0; + d5rnk2 <= # io_ffd 1'b0; + d6rnk2 <= # io_ffd 1'b0; + + end + else begin + + d3rnk2 <= # io_ffd data3; + d4rnk2 <= # io_ffd data4; + d5rnk2 <= # io_ffd data5; + d6rnk2 <= # io_ffd data6; + + end + + end // always @ (posedge clk_in or posedge sr_in) + + +// First rank of flops for input data +// asynchronous operation + always @ (posedge clkdiv_in or posedge sr_in) begin + + if (sr_in == 1'b1) begin + + d1r <= # io_ffcd 1'b0; + d2r <= # io_ffcd 1'b0; + d3r <= # io_ffcd 1'b0; + d4r <= # io_ffcd 1'b0; + d5r <= # io_ffcd 1'b0; + d6r <= # io_ffcd 1'b0; + + end + else begin + + d1r <= # io_ffcd d1_in; + d2r <= # io_ffcd d2_in; + d3r <= # io_ffcd d3_in; + d4r <= # io_ffcd d4_in; + d5r <= # io_ffcd d5_in; + d6r <= # io_ffcd d6_in; + + end + + end // always @ (posedge clkdiv_in or posedge sr_in) + + +// Muxs for 2nd rank of flops + always @ (sel1_4 or d1r or d2rnk2 or d3rnk2) begin + + casex (sel1_4) + + 3'b100: data1 <= # io_mxr1 d3rnk2; + 3'b110: data1 <= # io_mxr1 d1r; + 3'b101: data1 <= # io_mxr1 d2rnk2; + 3'b111: data1 <= # io_mxr1 d1r; + default: data1 <= # io_mxr1 d3rnk2; + + endcase + + end + + + always @ (sel1_4 or d2r or d3rnk2 or d4rnk2) begin + + casex (sel1_4) + + 3'b100: data2 <= # io_mxr1 d4rnk2; + 3'b110: data2 <= # io_mxr1 d2r; + 3'b101: data2 <= # io_mxr1 d3rnk2; + 3'b111: data2 <= # io_mxr1 d2r; + default: data2 <= # io_mxr1 d4rnk2; + + endcase + + end + + +//Note: To stop data rate of 00 from being illegal, register data is fed to mux + always @ (sel1_4 or d3r or d4rnk2 or d5rnk2) begin + + casex (sel1_4) + + 3'b100: data3 <= # io_mxr1 d5rnk2; + 3'b110: data3 <= # io_mxr1 d3r; + 3'b101: data3 <= # io_mxr1 d4rnk2; + 3'b111: data3 <= # io_mxr1 d3r; + default: data3 <= # io_mxr1 d5rnk2; + + endcase + + end + + + always @ (sel1_4 or d4r or d5rnk2 or d6rnk2) begin + + casex (sel1_4) + + 3'b100: data4 <= # io_mxr1 d6rnk2; + 3'b110: data4 <= # io_mxr1 d4r; + 3'b101: data4 <= # io_mxr1 d5rnk2; + 3'b111: data4 <= # io_mxr1 d4r; + default: data4 <= # io_mxr1 d6rnk2; + + endcase + + end + + + always @ (sel5_6 or d5r or d6rnk2 or shiftin1_in) begin + + casex (sel5_6) + + 4'b1000: data5 <= # io_mxr1 shiftin1_in; + 4'b1010: data5 <= # io_mxr1 d5r; + 4'b1001: data5 <= # io_mxr1 d6rnk2; + 4'b1011: data5 <= # io_mxr1 d5r; + 4'b1100: data5 <= # io_mxr1 1'b0; + 4'b1110: data5 <= # io_mxr1 d5r; + 4'b1101: data5 <= # io_mxr1 d6rnk2; + 4'b1111: data5 <= # io_mxr1 d5r; + default: data5 <= # io_mxr1 shiftin1_in; + + endcase + + end + + + always @ (sel5_6 or D6 or d6r or shiftin1_in or shiftin2_in) begin + + casex (sel5_6) + + 4'b1000: data6 <= # io_mxr1 shiftin2_in; + 4'b1010: data6 <= # io_mxr1 d6r; + 4'b1001: data6 <= # io_mxr1 shiftin1_in; + 4'b1011: data6 <= # io_mxr1 d6r; + 4'b1100: data6 <= # io_mxr1 1'b0; + 4'b1110: data6 <= # io_mxr1 d6r; + 4'b1101: data6 <= # io_mxr1 1'b0; + 4'b1111: data6 <= # io_mxr1 d6r; + default: data6 <= # io_mxr1 shiftin2_in; + + endcase + + end + + +// Logic to generate same edge data from d1rnk2 and d2nrnk2; + always @ (clk_in or c3 or d1rnk2 or d2nrnk2) begin + + io_sdata_edge <= # io_mxd (d1rnk2 & clk_in) | (d2nrnk2 & c3); + + end + +// Mux to create opposite edge DDR data from d1rnk2 and d2rnk2 + always @(clk_in or d1rnk2 or d2rnk2) begin + + case (clk_in) + + 1'b0: io_odata_edge <= # io_mxd d2rnk2; + 1'b1: io_odata_edge <= # io_mxd d1rnk2; + default: io_odata_edge <= # io_mxd d1rnk2; + + endcase + + end + + +// Logic to same edge and opposite data into just ddr data + always @(io_sdata_edge or io_odata_edge or ddr_clk_edge_int) begin + + io_ddr_data <= # io_mxd (io_odata_edge & !ddr_clk_edge_int) | (io_sdata_edge & ddr_clk_edge_int); + + end + + +// Output mux to generate OQ + always @ (seloq or d1rnk2 or io_ddr_data or oq_out) begin + + casex (seloq) + + 4'bXX01: oq_out <= # io_mxd 1'b1; + 4'bXX10: oq_out <= # io_mxd 1'b0; + 4'bXX11: oq_out <= # io_mxd 1'b0; + 4'b0000: oq_out <= # io_mxd oq_out; + 4'b0100: oq_out <= # io_mxd oq_out; + 4'b1000: oq_out <= # io_mxd io_ddr_data; + 4'b1100: oq_out <= # io_mxd d1rnk2; + default: oq_out <= # io_mxd io_ddr_data; + + endcase + + end + + +// Set value of counter in bitslip controller + always @ (data_rate_oq_int or data_width_int) begin + + casex ({data_rate_oq_int, data_width_int}) + + 5'b00100: begin c23 <= 1'b0; c45 <= 1'b0; c67 <= 1'b0; sel <= 2'b00; end + 5'b00110: begin c23 <= 1'b1; c45 <= 1'b0; c67 <= 1'b0; sel <= 2'b00; end + 5'b01000: begin c23 <= 1'b0; c45 <= 1'b0; c67 <= 1'b0; sel <= 2'b01; end + 5'b01010: begin c23 <= 1'b0; c45 <= 1'b1; c67 <= 1'b0; sel <= 2'b01; end + 5'b10010: begin c23 <= 1'b0; c45 <= 1'b0; c67 <= 1'b0; sel <= 2'b00; end + 5'b10011: begin c23 <= 1'b1; c45 <= 1'b0; c67 <= 1'b0; sel <= 2'b00; end + 5'b10100: begin c23 <= 1'b0; c45 <= 1'b0; c67 <= 1'b0; sel <= 2'b01; end + 5'b10101: begin c23 <= 1'b0; c45 <= 1'b1; c67 <= 1'b0; sel <= 2'b01; end + 5'b10110: begin c23 <= 1'b0; c45 <= 1'b0; c67 <= 1'b0; sel <= 2'b10; end + 5'b10111: begin c23 <= 1'b0; c45 <= 1'b0; c67 <= 1'b1; sel <= 2'b10; end + 5'b11000: begin c23 <= 1'b0; c45 <= 1'b0; c67 <= 1'b0; sel <= 2'b11; end + + default: begin + $display("DATA_WIDTH %d and DATA_RATE_OQ %s at time %t ns are illegal.", DATA_WIDTH, DATA_RATE_OQ, $time/1000.0); + $finish; + end + + endcase + + end // always @ (data_rate_oq_int or data_width_int) + + + + +/////////////////////////////////////////////////////////////// +// Programmable Load Generator (PLG) +// Divide by 2-8 counter with load enable output +////////////////////////////////////////////////////////////////// + +// flops for counter +// asynchronous reset + always @ (posedge qhr or posedge clk_in) begin + + if (qhr) begin + + q0 <= # ffdcnt 1'b0; + q1 <= # ffdcnt 1'b0; + q2 <= # ffdcnt 1'b0; + q3 <= # ffdcnt 1'b0; + + end + else begin + + q3 <= # ffdcnt q2; + q2 <= # ffdcnt (!(!q0 & !q2) & q1); + q1 <= # ffdcnt q0; + q0 <= # ffdcnt mux; + + end + + end // always @ (posedge qhr or posedge clk_in) + + +// mux settings for counter + always @ (sel or c23 or c45 or c67 or q0 or q1 or q2 or q3) begin + + case (sel) + + 2'b00: mux <= # mxdcnt (!q0 & !(c23 & q1)); + 2'b01: mux <= # mxdcnt (!q1 & !(c45 & q2)); + 2'b10: mux <= # mxdcnt (!q2 & !(c67 & q3)); + 2'b11: mux <= # mxdcnt !q3; + default: mux <= # mxdcnt 1'b0; + + endcase + + end + + +// mux decoding for load signal + always @ (sel or c23 or c45 or c67 or q0 or q1 or q2 or q3) begin + + case (sel) + + 2'b00: load <= # mxdcnt q0; + 2'b01: load <= # mxdcnt q0 & q1; + 2'b10: load <= # mxdcnt q0 & q2; + 2'b11: load <= # mxdcnt q0 & q3; + default: load <= # mxdcnt 1'b0; + + endcase + + end + + +// flops to reset counter +// Low speed flop +// asynchronous reset + always @ (posedge sr_in or posedge clkdiv_in) begin + + if (sr_in == 1'b1) + + qlr <= # ffrst 1'b1; + + else + + qlr <= # ffrst 1'b0; + + end // always @ (posedge sr_in or posedge clkdiv_in) + + +// High speed flop +// asynchronous reset + always @ (posedge sr_in or posedge clk_in) begin + + if (sr_in == 1'b1) + + qhr <= # ffdcnt 1'b1; + + else + + qhr <= # ffdcnt qlr; + + end // always @ (posedge sr_in or posedge clk_in) + + + +/////////////////////////////////////////////////////// +// +// Tristate Output cell +// +//////////////////////////////////////////////////////// + +// 3 flops to create DDR operations of 4 latches +// Representation of top latch +// asynchronous operation + always @ (posedge clk_in or posedge sr_in or posedge rev_in or posedge rev_in_AND_NOT_sr_in or posedge NOT_rev_in_AND_sr_in) begin + + if (sr_in == 1'b1 & !(rev_in == 1'b1 & SRVAL_TQ == 1'b1)) + + qt1 <= # iot_ffd SRVAL_TQ; + + else if (rev_in == 1'b1) + + qt1 <= # iot_ffd !SRVAL_TQ; + + else if (tce_in == 1'b1) + + qt1 <= # iot_ffd data1t; + + else if (tce_in == 1'b0) + + qt1 <= # iot_ffd tq_out; + + end // always @ (posedge clk_in or posedge sr_in or posedge rev_in or posedge rev_in_AND_NOT_sr_in or posedge NOT_rev_in_AND_sr_in) + + +// Representation of 2nd latch +// asynchronous operation + always @ (posedge c2p or posedge sr_in or posedge rev_in or posedge rev_in_AND_NOT_sr_in or posedge NOT_rev_in_AND_sr_in) begin + + if (sr_in == 1'b1 & !(rev_in == 1'b1 & SRVAL_TQ == 1'b1)) + + qt2 <= # iot_ffd SRVAL_TQ; + + else if (rev_in == 1'b1) + + qt2 <= # iot_ffd !SRVAL_TQ; + + else if (tce_in == 1'b1) + + qt2 <= # iot_ffd data2t; + + else if (tce_in == 1'b0) + + qt2 <= # iot_ffd tq_out; + + end // always @ (posedge c2p or posedge sr_in or posedge rev_in or posedge rev_in_AND_NOT_sr_in or posedge NOT_rev_in_AND_sr_in) + + +// Representation of 3rd flop ( latch and output latch) +// asynchronous operation + always @ (posedge c3 or posedge sr_in or posedge rev_in or posedge rev_in_AND_NOT_sr_in or posedge NOT_rev_in_AND_sr_in) begin + + if (sr_in == 1'b1 & !(rev_in == 1'b1 & SRVAL_TQ == 1'b1)) + + qt2n <= # iot_ffd SRVAL_TQ; + + else if (rev_in == 1'b1) + + qt2n <= # iot_ffd !SRVAL_TQ; + + else if (tce_in == 1'b1) + + qt2n <= # iot_ffd qt2; + + else if (tce_in == 1'b0) + + qt2n <= # iot_ffd tq_out; + + end // always @ (posedge c3 or posedge sr_in or posedge rev_in or posedge rev_in_AND_NOT_sr_in or posedge NOT_rev_in_AND_sr_in) + + +// First rank of flops +// asynchronous reset operation + always @ (posedge clkdiv_in or posedge sr_in) begin + + if (sr_in == 1'b1) begin + + t1r <= # iot_ffd 1'b0; + t2r <= # iot_ffd 1'b0; + t3r <= # iot_ffd 1'b0; + t4r <= # iot_ffd 1'b0; + + end + else begin + + t1r <= # iot_ffd t1_in; + t2r <= # iot_ffd t2_in; + t3r <= # iot_ffd t3_in; + t4r <= # iot_ffd t4_in; + + end + + end // always @ (posedge clkdiv_in or posedge sr_in) + + +// Data Muxs for tristate otuput signals + always @ (sel_tri or t1_in or t1r or t3r) begin + + casex (sel_tri) + + 5'b00000: data1t <= # iot_mxd t1_in; + 5'b10000: data1t <= # iot_mxd t1_in; + 5'bX0000: data1t <= # iot_mxd t1_in; + 5'b00100: data1t <= # iot_mxd t1_in; + 5'b10100: data1t <= # iot_mxd t1_in; + 5'bX0100: data1t <= # iot_mxd t1_in; + 5'b01001: data1t <= # iot_mxd t1_in; + 5'b11001: data1t <= # iot_mxd t1_in; + 5'b01010: data1t <= # iot_mxd t3r; + 5'b11010: data1t <= # iot_mxd t1r; +// CR 458156 -- allow/enabled TRISTATE_WIDTH to be 1 in DDR mode. No func change, but removed warnings + 5'b01000: ; + 5'b11000: ; + 5'bX1000: ; + default: begin + $display("DATA_RATE_TQ %s and/or TRISTATE_WIDTH %d at time %t ns are not supported by OSERDES", DATA_RATE_TQ, TRISTATE_WIDTH, $time/1000.0); + $finish; + end + + endcase + + end + +// For data 2, width of 1 is inserted as acceptable for buf and sdr +// The capability exists in the device if the feature is added + always @ (sel_tri or t2_in or t2r or t4r) begin + + casex (sel_tri) + + 5'b00000: data2t <= # iot_mxd t2_in; + 5'b00100: data2t <= # iot_mxd t2_in; + 5'b10000: data2t <= # iot_mxd t2_in; + 5'b10100: data2t <= # iot_mxd t2_in; + 5'bX0000: data2t <= # iot_mxd t2_in; + 5'bX0100: data2t <= # iot_mxd t2_in; + 5'b00X00: data2t <= # iot_mxd t2_in; + 5'b10X00: data2t <= # iot_mxd t2_in; + 5'bX0X00: data2t <= # iot_mxd t2_in; + 5'b01001: data2t <= # iot_mxd t2_in; + 5'b11001: data2t <= # iot_mxd t2_in; + 5'bX1001: data2t <= # iot_mxd t2_in; + 5'b01010: data2t <= # iot_mxd t4r; + 5'b11010: data2t <= # iot_mxd t2r; +// CR 458156 -- allow/enabled TRISTATE_WIDTH to be 1 in DDR mode. No func change, but removed warnings + 5'b01000: ; + 5'b11000: ; + 5'bX1000: ; + default: begin + $display("DATA_RATE_TQ %s and/or TRISTATE_WIDTH %d at time %t ns are not supported by OSERDES", DATA_RATE_TQ, TRISTATE_WIDTH, $time/1000.0); + $finish; + end + + endcase + + end + + +// Logic to generate same edge data from qt1, qt3; + always @ (clk_in or c3 or qt1 or qt2n) begin + + iot_sdata_edge <= # iot_mxd (qt1 & clk_in) | (qt2n & c3); + + end + + +// Mux to create opposite edge DDR function + always @ (clk_in or qt1 or qt2) begin + + case (clk_in) + + 1'b0: iot_odata_edge <= # iot_mxd qt2; + 1'b1: iot_odata_edge <= # iot_mxd qt1; + default: iot_odata_edge <= 1'b0; + + endcase + + end + + +// Logic to same edge and opposite data into just ddr data + always @ (iot_sdata_edge or iot_odata_edge or ddr_clk_edge_int) begin + + iot_ddr_data <= # iot_mxd (iot_odata_edge & !ddr_clk_edge_int) | (iot_sdata_edge & ddr_clk_edge_int); + + end + +// Output mux to generate TQ +// Note that the TQ mux can also support T2 combinatorial or +// registered outputs. Those modes are not support in this model. + always @ (seltq or data1t or iot_ddr_data or qt1 or tq_out) begin + + casex (seltq) + + 7'bX01XX01: tq_out <= # iot_mxd 1'b1; + 7'bX10XX01: tq_out <= # iot_mxd 1'b1; + 7'bX01XX10: tq_out <= # iot_mxd 1'b0; + 7'bX10XX10: tq_out <= # iot_mxd 1'b0; + 7'bX01XX11: tq_out <= # iot_mxd 1'b0; + 7'bX10XX11: tq_out <= # iot_mxd 1'b0; + 7'bX0000XX: tq_out <= # iot_mxd data1t; + 7'b0010000: tq_out <= # iot_mxd tq_out; + 7'b0100100: tq_out <= # iot_mxd tq_out; + 7'b0101000: tq_out <= # iot_mxd tq_out; + 7'b1010000: tq_out <= # iot_mxd qt1; + 7'b1100100: tq_out <= # iot_mxd iot_ddr_data; + 7'b1101000: tq_out <= # iot_mxd iot_ddr_data; + default: tq_out <= # iot_mxd iot_ddr_data; + + endcase + + end + + specify + + (CLK => OQ) = (100, 100); + (CLK => TQ) = (100, 100); + specparam PATHPULSE$ = 0; + + endspecify + +endmodule // OSERDES diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OSERDES2.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OSERDES2.v new file mode 100644 index 0000000..2e3fa6c --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OSERDES2.v @@ -0,0 +1,609 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/stan/OSERDES2.v,v 1.18 2009/08/21 23:55:41 harikr Exp $ +////////////////////////////////////////////////////// +// Copyright (c) 2008 Xilinx Inc. +// All Right Reserved. +/////////////////////////////////////////////////////// +// +// ____ ___ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Source Synchronous Output Serializer +// /__/ /\ Filename : OSERDES2.v +// \ \ / \ +// \__\/\__ \ +// +// Revision: Date: Comment +// 1.0: 12/12/07: Initial version. +// 1.1: 02/29/08: Changed name to OSERDES2 +// removed mc_ from signal names +// 1.2: 11/13/08: IR495203 Gate behavior with OCE, TCE. +// Fix specify block +// 1.3: 12/11/08: delay internal ioce by 1 ioclk +// 1.4: 01/30/09: CR504529 add BYPASS_GCLK_FF attribute +// 1.5: 02/11/09: CR507848 add missing MODULE_NAME localparam +// 1.6: 03/05/09: CR511015 VHDL - VER sync +// 1.7: 03/19/09: CR513780 x -> 0 rst sensitivity +// 1.8: 04/02/09: CR513901 unisim-simprim mismatch, always -> assign +// 1.9: 07/07/09: CR524403 Add NONE to valid serdes_mode values +// End Revision +/////////////////////////////////////////////////////// + +`timescale 1 ps / 1 ps + +module OSERDES2 ( + OQ, + SHIFTOUT1, + SHIFTOUT2, + SHIFTOUT3, + SHIFTOUT4, + TQ, + CLK0, + CLK1, + CLKDIV, + D1, + D2, + D3, + D4, + IOCE, + OCE, + RST, + SHIFTIN1, + SHIFTIN2, + SHIFTIN3, + SHIFTIN4, + T1, + T2, + T3, + T4, + TCE, + TRAIN +); + + parameter BYPASS_GCLK_FF = "FALSE"; // TRUE, FALSE + parameter DATA_RATE_OQ = "DDR"; // SDR, DDR | Data Rate setting + parameter DATA_RATE_OT = "DDR"; // SDR, DDR, BUF | Tristate Rate setting. + parameter integer DATA_WIDTH = 2; // {1..8} + parameter OUTPUT_MODE = "SINGLE_ENDED"; // SINGLE_ENDED, DIFFERENTIAL + parameter SERDES_MODE = "NONE"; // NONE, MASTER, SLAVE + parameter integer TRAIN_PATTERN = 0; // {0..15} + + localparam in_delay = 1; + localparam out_delay = 1; + localparam inclk_delay = 0; + localparam outclk_delay = 0; + localparam MODULE_NAME = "OSERDES2"; + + + output OQ; + output SHIFTOUT1; + output SHIFTOUT2; + output SHIFTOUT3; + output SHIFTOUT4; + output TQ; + + input CLK0; + input CLK1; + input CLKDIV; + input D1; + input D2; + input D3; + input D4; + input IOCE; + input OCE; + input RST; + input SHIFTIN1; + input SHIFTIN2; + input SHIFTIN3; + input SHIFTIN4; + input T1; + input T2; + input T3; + input T4; + input TCE; + input TRAIN; +// Output signals + wire oq_out, tq_out; + wire shiftout1_out, shiftout2_out, shiftout3_out, shiftout4_out; + + wire oq_outdelay, tq_outdelay; + wire shiftout1_outdelay, shiftout2_outdelay, shiftout3_outdelay, shiftout4_outdelay; + +// FF outputs + reg [3:0] tgff, toff, dgff, doff; + wire [3:0] tdata, ddata; + wire tlsb, dlsb, tpre, dpre; + reg Tff = 1'b0, Dff = 1'b0; + reg Tpf = 1'b0, Dpf = 1'b0; + reg one_shot_TCE = 1'b1, one_shot_OCE = 1'b1; + reg ioce_int = 1'b0; + +// Other nodes + wire tcasc_in, dcasc_in; + reg tinit = 0; + reg [3:0] trainp; + +// Internal Clock + reg clk0_int = 0; + reg clk1_int = 0; + wire clk_int; + +// Attribute settings + reg encasc; // 1 = enable cascade input + reg isslave; // 1 = slave mode + reg endiffop; // 1 = enable pseudo diff output + reg enTCE; // 1 = enable the tristate path + reg bypassTFF; // 1 = direct out + +// Other signals + reg BYPASS_GCLK_FF_err_flag = 0; + reg data_rate_oq_err_flag = 0; + reg data_rate_tq_err_flag = 0; + reg data_width_err_flag = 0; + reg output_mode_err_flag = 0; + reg serdes_mode_err_flag = 0; + reg train_pattern_err_flag = 0; + reg attr_err_flag = 0; + reg BYPASS_GCLK_FF_BINARY = 0; + reg [7:0] DATA_WIDTH_BINARY = 2'h2; + tri0 GSR = glbl.GSR; + + wire OQ; + wire SHIFTOUT1; + wire SHIFTOUT2; + wire SHIFTOUT3; + wire SHIFTOUT4; + wire TQ; + wire CLK0_IN; + wire CLK1_IN; + wire CLKDIV_IN; + wire D1_IN; + wire D2_IN; + wire D3_IN; + wire D4_IN; + wire GSR_IN; + wire IOCE_IN; + wire OCE_IN; + wire SHIFTIN1_IN; + wire SHIFTIN2_IN; + wire SHIFTIN3_IN; + wire SHIFTIN4_IN; + wire RST_IN; + wire T1_IN; + wire T2_IN; + wire T3_IN; + wire T4_IN; + wire TCE_IN; + wire TRAIN_IN; + + wire CLK0_INDELAY; + wire CLK1_INDELAY; + wire CLKDIV_INDELAY; + wire D1_INDELAY; + wire D2_INDELAY; + wire D3_INDELAY; + wire D4_INDELAY; + wire GSR_INDELAY; + wire IOCE_INDELAY; + wire OCE_INDELAY; + wire SHIFTIN1_INDELAY; + wire SHIFTIN2_INDELAY; + wire SHIFTIN3_INDELAY; + wire SHIFTIN4_INDELAY; + wire RST_INDELAY; + wire T1_INDELAY; + wire T2_INDELAY; + wire T3_INDELAY; + wire T4_INDELAY; + wire TCE_INDELAY; + wire TRAIN_INDELAY; + reg notifier=0; + + assign #(inclk_delay) CLK0_INDELAY = CLK0_IN; +// assign #(inclk_delay) CLK1_INDELAY = (DATA_RATE_OQ == "DDR") ? CLK1_IN : 1'b0; + assign #(inclk_delay) CLK1_INDELAY = CLK1_IN; + assign #(inclk_delay) CLKDIV_INDELAY = CLKDIV_IN; + assign #(in_delay) D1_INDELAY = D1_IN; + assign #(in_delay) D2_INDELAY = D2_IN; + assign #(in_delay) D3_INDELAY = D3_IN; + assign #(in_delay) D4_INDELAY = D4_IN; + assign #(in_delay) GSR_INDELAY = GSR_IN; + assign #(in_delay) IOCE_INDELAY = IOCE_IN; + assign #(in_delay) OCE_INDELAY = OCE_IN; + assign #(in_delay) SHIFTIN1_INDELAY = SHIFTIN1_IN; + assign #(in_delay) SHIFTIN2_INDELAY = SHIFTIN2_IN; + assign #(in_delay) SHIFTIN3_INDELAY = SHIFTIN3_IN; + assign #(in_delay) SHIFTIN4_INDELAY = SHIFTIN4_IN; + assign #(in_delay) RST_INDELAY = RST_IN; + assign #(in_delay) T1_INDELAY = T1_IN; + assign #(in_delay) T2_INDELAY = T2_IN; + assign #(in_delay) T3_INDELAY = T3_IN; + assign #(in_delay) T4_INDELAY = T4_IN; + assign #(in_delay) TCE_INDELAY = TCE_IN; + assign #(in_delay) TRAIN_INDELAY = TRAIN_IN; + + assign #(out_delay) oq_outdelay = oq_out; + assign #(out_delay) tq_outdelay = tq_out; + assign #(out_delay) shiftout1_outdelay = shiftout1_out; + assign #(out_delay) shiftout2_outdelay = shiftout2_out; + assign #(out_delay) shiftout3_outdelay = shiftout3_out; + assign #(out_delay) shiftout4_outdelay = shiftout4_out; + +//---------------------------------------------------------------------- +//------------------------ Output Ports ------------------------------ +//---------------------------------------------------------------------- + assign OQ = oq_outdelay; + assign TQ = tq_outdelay; + assign SHIFTOUT1 = shiftout1_outdelay; + assign SHIFTOUT2 = shiftout2_outdelay; + assign SHIFTOUT3 = shiftout3_outdelay; + assign SHIFTOUT4 = shiftout4_outdelay; + +//---------------------------------------------------------------------- +//------------------------ Input Ports ------------------------------ +//---------------------------------------------------------------------- + + assign CLK0_IN = CLK0; + assign CLK1_IN = CLK1; + assign CLKDIV_IN = CLKDIV; + assign D1_IN = D1; + assign D2_IN = D2; + assign D3_IN = D3; + assign D4_IN = D4; + assign GSR_IN = GSR; + assign IOCE_IN = IOCE; + assign OCE_IN = OCE; + assign SHIFTIN1_IN = SHIFTIN1; + assign SHIFTIN2_IN = SHIFTIN2; + assign SHIFTIN3_IN = SHIFTIN3; + assign SHIFTIN4_IN = SHIFTIN4; + assign RST_IN = RST; + assign T1_IN = T1; + assign T2_IN = T2; + assign T3_IN = T3; + assign T4_IN = T4; + assign TCE_IN = TCE; + assign TRAIN_IN = TRAIN; + + +// ======================= +// Top of shift register +// ======================= + assign dcasc_in = encasc & SHIFTIN1_INDELAY; + assign tcasc_in = encasc & SHIFTIN2_INDELAY; + + initial begin +//------------------------------------------------- +//------ BYPASS_GCLK_FF Check +//------------------------------------------------- + if (BYPASS_GCLK_FF == "TRUE") BYPASS_GCLK_FF_BINARY <= 1'b1; + else if (BYPASS_GCLK_FF == "FALSE") BYPASS_GCLK_FF_BINARY <= 1'b0; + else begin + #1; + $display("Attribute Syntax Error : The attribute BYPASS_GCLK_FF on %s instance %m is set to %s. \n Legal values for this attribute are TRUE or FALSE.\n", MODULE_NAME, BYPASS_GCLK_FF); + BYPASS_GCLK_FF_err_flag = 1; + end + + +//------------------------------------------------- +//----- DATA_RATE_OQ Check +//------------------------------------------------- + if ((DATA_RATE_OQ != "SDR") && (DATA_RATE_OQ != "DDR")) begin + #1; + $display("Attribute Syntax Error : The attribute DATA_RATE_OQ on %s instance %m is set to %s. \nLegal values for this attribute are SDR or DDR.\n", MODULE_NAME, DATA_RATE_OQ); + data_rate_oq_err_flag = 1; + end + +//------------------------------------------------- +//----- DATA_RATE_OT Check +//------------------------------------------------- + if (DATA_RATE_OT == "SDR") begin + tinit = 1; + enTCE = 1; + bypassTFF = 0; + if (DATA_RATE_OQ !== "SDR") begin + #1; + $display("Attribute Syntax Error : The attribute DATA_RATE_OT on %s instance %m is set to %s and the attribute DATA_RATE_OQ is set to %s. \nThese two values must match for SDR and DDR.\n", MODULE_NAME, DATA_RATE_OT, DATA_RATE_OQ); + data_rate_tq_err_flag = 1; + end + end + else if (DATA_RATE_OT == "DDR") begin + tinit = 1; + enTCE = 1; + bypassTFF = 0; + if (DATA_RATE_OQ !== "DDR") begin + #1; + $display("Attribute Syntax Error : The attribute DATA_RATE_OT on %s instance %m is set to %s and the attribute DATA_RATE_OQ is set to %s. \nThese two values must match for SDR and DDR.\n", MODULE_NAME, DATA_RATE_OT, DATA_RATE_OQ); + data_rate_tq_err_flag = 1; + end + end + else if (DATA_RATE_OT == "BUF") begin + tinit = 0; + enTCE = 0; + bypassTFF = 1; + end + else begin + #1; + $display("Attribute Syntax Error : The attribute DATA_RATE_OT on %s instance %m is set to %s. \nLegal values for this attribute are SDR, DDR or BUF.\n", MODULE_NAME, DATA_RATE_OT); + data_rate_tq_err_flag = 1; + end + +//------------------------------------------------- +//----- DATA_WIDTH check +//------------------------------------------------- + if ((DATA_WIDTH == 1) || (DATA_WIDTH == 2) || (DATA_WIDTH == 3) || + (DATA_WIDTH == 4) || (DATA_WIDTH == 5) || (DATA_WIDTH == 6) || + (DATA_WIDTH == 7) || (DATA_WIDTH == 8)) begin + DATA_WIDTH_BINARY = DATA_WIDTH; + end + else begin + #1; + $display("Attribute Syntax Error : The attribute DATA_WIDTH on %s instance %m is set to %d. \nLegal values for this attribute are 1, 2, 3, 4, 5, 6, 7 or 8.\n", MODULE_NAME, DATA_WIDTH); + data_width_err_flag = 1; + end + +//------------------------------------------------- +//------ SERDES_MODE Check +//------------------------------------------------- + if (SERDES_MODE == "NONE") begin + isslave = 1'b0; + encasc = 1'b0; + end + else if (SERDES_MODE == "MASTER") begin + isslave = 1'b0; + encasc = 1'b0; + end + else if (SERDES_MODE == "SLAVE") begin + isslave = 1'b1; + if (DATA_WIDTH > 4) + encasc = 1'b1; + else + encasc = 1'b0; + end + else begin + #1; + $display("Attribute Syntax Error : The attribute SERDES_MODE on %s instance %m is set to %s. \nLegal values for this attribute are NONE, MASTER or SLAVE.\n", MODULE_NAME, SERDES_MODE); + serdes_mode_err_flag = 1; + end + +//------------------------------------------------- +//------ OUTPUT_MODE Check +//------------------------------------------------- + if (OUTPUT_MODE == "DIFFERENTIAL") begin + endiffop = 1'b1; + end + else if (OUTPUT_MODE == "SINGLE_ENDED") begin + if ((SERDES_MODE == "SLAVE") || (DATA_WIDTH < 5)) + endiffop = 1'b0; + else + endiffop = 1'b1; + end + else begin + #1; + $display("Attribute Syntax Error : The attribute OUTPUT_MODE on %s instance %m is set to %s. \nLegal values for this attribute are DIFFERENTIAL or SINGLE_ENDED.\n", MODULE_NAME, OUTPUT_MODE); + output_mode_err_flag = 1; + end + +//------------------------------------------------- +//----- TRAIN_PATTERN check +//------------------------------------------------- + if ((TRAIN_PATTERN >= 0) && (TRAIN_PATTERN < 16)) begin + trainp = TRAIN_PATTERN; + end + else begin + #1; + $display("Attribute Syntax Error : The attribute TRAIN_PATTERN on %s instance %m is set to %d. \nLegal values for this attribute are 0, 1, 2, ... 13, 14, 15.\n", MODULE_NAME, TRAIN_PATTERN); + train_pattern_err_flag = 1; + end + +//------------------------------------------------- +//------ Error Flag -------- +//------------------------------------------------- + #1; + if (data_rate_oq_err_flag || data_rate_tq_err_flag || data_width_err_flag || output_mode_err_flag || serdes_mode_err_flag || train_pattern_err_flag) + begin + attr_err_flag = 1; + #1; + $display("Attribute Errors detected : Simulation cannot continue. Exiting. \n"); + $finish; + end + + end // initial begin + +//----------------------------------------------------------------------------------- +//*** GLOBAL hidden GSR pin + always @(GSR_INDELAY) begin + if (GSR_INDELAY == 1'b1) begin + + assign dgff = 4'h0; + assign doff = 4'h0; + + assign tgff = 4'h0; + assign toff = 4'h0; + +// assign Dff = 1'b0; + assign Dpf = 1'b0; +// assign Tff = 1'b0; + assign Tpf = 1'b0; + + end + else begin + + deassign dgff; + deassign doff; + + deassign tgff; + deassign toff; + +// deassign Dff; + deassign Dpf; +// deassign Tff; + deassign Tpf; + + end + end +// ===================== +// DDR doubler +// ===================== + always @(posedge CLK0_INDELAY) begin + clk0_int = 1; + #100 clk0_int = 0; + end + + generate if(DATA_RATE_OQ == "DDR") + always @(posedge CLK1_INDELAY) begin + clk1_int = 1; + #100 clk1_int = 0; + end + endgenerate + + assign clk_int = clk0_int | clk1_int; +// +// ===================== +// IOCE sample +// ===================== +// always @(posedge CLK0_INDELAY or posedge CLK1_INDELAY or posedge RST_INDELAY) begin + always @(posedge clk_int or posedge RST_INDELAY) begin + if (RST_INDELAY == 1'b1) + ioce_int <= 1'b0; + else + ioce_int <= IOCE_INDELAY; + end + +// ====================== +// GCLK Register Bank +// ====================== + + always @(posedge CLKDIV_INDELAY or posedge RST_INDELAY) begin + if (RST_INDELAY == 1'b1) begin + dgff[3] <= 1'b0; + dgff[2] <= 1'b0; + dgff[1] <= 1'b0; + dgff[0] <= 1'b0; + end + else if (OCE_INDELAY == 1'b1) begin + dgff[3] <= #100 D4_INDELAY; + dgff[2] <= #100 D3_INDELAY; + dgff[1] <= #100 D2_INDELAY; + dgff[0] <= #100 D1_INDELAY; + end + end + + always @(posedge CLKDIV_INDELAY or posedge RST_INDELAY) begin + if (RST_INDELAY == 1'b1) begin + tgff[3] <= 1'b0; // tinit? + tgff[2] <= 1'b0; // tinit? + tgff[1] <= 1'b0; // tinit? + tgff[0] <= 1'b0; // tinit? + end + else if (TCE_INDELAY == 1'b1) begin + tgff[3] <= #100 T4_INDELAY; + tgff[2] <= #100 T3_INDELAY; + tgff[1] <= #100 T2_INDELAY; + tgff[0] <= #100 T1_INDELAY; + end + end + +// ====================== +// Bypass Mux +// ====================== + assign ddata = TRAIN_INDELAY ? trainp : (BYPASS_GCLK_FF_BINARY ? {D4_INDELAY, D3_INDELAY, D2_INDELAY, D1_INDELAY} : dgff); + + assign tdata[3] = BYPASS_GCLK_FF_BINARY ? T4_INDELAY : tgff[3]; + assign tdata[2] = BYPASS_GCLK_FF_BINARY ? T3_INDELAY : tgff[2]; + assign tdata[1] = BYPASS_GCLK_FF_BINARY ? T2_INDELAY : tgff[1]; + assign tdata[0] = BYPASS_GCLK_FF_BINARY ? T1_INDELAY : tgff[0]; + +// ======================= +// Output Shift Register +// ======================= + always @(posedge clk_int or posedge RST_INDELAY) begin +// always @(posedge CLK0_INDELAY or posedge CLK1_INDELAY or posedge RST_INDELAY) begin + if (RST_INDELAY == 1'b1) begin + doff <= 4'h0; + toff <= 4'h0; // tinit? + end + else begin + if (OCE_INDELAY == 1'b1) begin + doff <= ioce_int ? ddata : {dcasc_in, doff[3:1]}; + end + if (TCE_INDELAY == 1'b1) begin + toff <= ioce_int ? tdata : {tcasc_in, toff[3:1]}; + end + end + end + +// ========================== +// Bottom of shift register +// ========================== + assign shiftout1_out = doff[0]; + assign shiftout2_out = toff[0]; + assign shiftout3_out = dlsb; + assign shiftout4_out = tlsb; + + assign dlsb = ioce_int ? ddata[0] : doff[1]; + assign tlsb = bypassTFF ? T1_INDELAY : (ioce_int ? tdata[0] : toff[1]); + + + assign dpre = endiffop ? (isslave ? ~dlsb : SHIFTIN3_INDELAY) : dlsb; + assign tpre = endiffop ? (isslave ? tlsb : SHIFTIN4_INDELAY) : tlsb; + + +// ===================== +// Output Sampling FFs +// ===================== + always @(posedge clk_int or posedge RST_INDELAY) begin +// always @(posedge CLK0_INDELAY or posedge CLK1_INDELAY or posedge RST_INDELAY) begin + if (GSR_INDELAY == 1'b1) begin + Dpf <= 1'b0; + Tpf <= 1'b0; + one_shot_OCE <= 1'b1; + one_shot_TCE <= 1'b1; + end + else if (RST_INDELAY == 1'b1) begin + Dpf <= isslave && endiffop; // 1'b0; + Tpf <= 1'b0; // should be tinit + one_shot_OCE <= 1'b1; + one_shot_TCE <= 1'b1; + end + else if ((GSR_INDELAY === 1'b0) && (RST_INDELAY === 1'b0)) begin + if (OCE_INDELAY == 1'b1) Dpf <= dpre; + if (TCE_INDELAY == 1'b1) Tpf <= tpre; + if (OCE_INDELAY == 1'b1) one_shot_OCE <= 1'b0; + if (TCE_INDELAY == 1'b1) one_shot_TCE <= 1'b0; + end + end + +// always @(posedge CLK0_INDELAY or posedge CLK1_INDELAY or posedge RST_INDELAY) begin + always @(posedge clk_int or posedge RST_INDELAY) begin + if (GSR_INDELAY == 1'b1) begin + Dff <= 1'b0; + Tff <= 1'b0; + end + else if (RST_INDELAY == 1'b1) begin + Dff <= 1'b0; + Tff <= tinit; + end + else if ((GSR_INDELAY === 1'b0) && (RST_INDELAY === 1'b0)) begin + if (OCE_INDELAY == 1'b1) Dff <= one_shot_OCE ? Dpf : dpre; + if (TCE_INDELAY == 1'b1) Tff <= one_shot_TCE ? Tpf : tpre; + end + end + +// ================== +// Final Output Mux +// ================== + assign oq_out = Dff; + assign tq_out = bypassTFF ? tpre : Tff; + + + specify + ( CLK0 => OQ) = (0, 0); + ( CLK0 => TQ) = (0, 0); + ( CLK1 => OQ) = (0, 0); + ( CLK1 => TQ) = (0, 0); + + specparam PATHPULSE$ = 0; + endspecify +endmodule // OSERDES2 diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OSERDESE1.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OSERDESE1.v new file mode 100644 index 0000000..2757360 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/OSERDESE1.v @@ -0,0 +1,3216 @@ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2005 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Source Synchronous Output Serializer +// /___/ /\ Filename : OSERDESE1.v +// \ \ / \ Timestamp : Tue Sep 16 15:30:44 PDT 2008 +// \___\/\___\ +// +// Revision: +// 09/16/08 - Initial version. +// 12/05/08 - IR 495397. +// 01/13/09 - IR 503429. +// 01/15/09 - IR 503783 CLKPERF is not inverted for OFB/ofb_out. +// 02/06/09 - CR 507373 Removed IOCLKGLITCH and CLKB +// 02/26/09 - CR 510489 fixed SHIFTIN2_in +// 03/16/09 - CR 512140 and 512139 -- sdf load errors +// 01/27/10 - CR 546419 Updated specify block +// 04/12/10 - CR 551953 Enabled TRISTATE_WIDTH to be 1 in DDR mode. +// End Revision + +`timescale 1 ps / 1 ps + +module OSERDESE1 (OCBEXTEND, OFB, OQ, SHIFTOUT1, SHIFTOUT2, TFB, TQ, + CLK, CLKDIV, CLKPERF, CLKPERFDELAY, D1, D2, D3, D4, D5, D6, OCE, ODV, RST, SHIFTIN1, SHIFTIN2, T1, T2, T3, T4, TCE, WC); + + + + parameter DATA_RATE_OQ = "DDR"; + parameter DATA_RATE_TQ = "DDR"; + parameter integer DATA_WIDTH = 4; + parameter integer DDR3_DATA = 1; + parameter INIT_OQ = 1'b0; + parameter INIT_TQ = 1'b0; + parameter INTERFACE_TYPE = "DEFAULT"; + parameter integer ODELAY_USED = 0; + parameter SERDES_MODE = "MASTER"; + parameter SRVAL_OQ = 1'b0; + parameter SRVAL_TQ = 1'b0; + parameter integer TRISTATE_WIDTH = 4; + + +//------------------------------------------------------------- +// Outputs: +//------------------------------------------------------------- +// OQ: Data output +// TQ: Output of tristate mux +// SHIFTOUT1: Carry out data 1 for slave +// SHIFTOUT2: Carry out data 2 for slave +// OFB: O Feedback output +// TFB: T Feedback output +// + +// +//------------------------------------------------------------- +// Inputs: +//------------------------------------------------------------- +// +// Inputs: +// CLK: High speed clock from DCM +// CLKB: Inverted High speed clock from DCM +// CLKDIV: Low speed divided clock from DCM +// CLKPERF: Performance Path clock +// CLKPERFDELAY: delayed Performance Path clock +// D1, D2, D3, D4, D5, D6 : Data inputs +// OCE: Clock enable for output data flops +// ODV: ODELAY value > 140 degrees +// RST: Reset control +// T1, T2, T3, T4: tristate inputs +// SHIFTIN1: Carry in data 1 for master from slave +// SHIFTIN2: Carry in data 2 for master from slave +// TCE: Tristate clock enable +// WC: Write command given by memory controller + + output OCBEXTEND; + output OFB; + output OQ; + output SHIFTOUT1; + output SHIFTOUT2; + output TFB; + output TQ; + + input CLK; + input CLKDIV; + input CLKPERF; + input CLKPERFDELAY; + input D1; + input D2; + input D3; + input D4; + input D5; + input D6; + input OCE; + input ODV; + input RST; + input SHIFTIN1; + input SHIFTIN2; + input T1; + input T2; + input T3; + input T4; + input TCE; + input WC; + + +// + wire SERDES, DDR_CLK_EDGE; + wire [5:0] SRTYPE; + wire WC_DELAY; + wire [4:0] SELFHEAL; + + + wire load; + wire qmux1, qmux, tmux1, tmux2; + wire data1, data2, triin1, triin2; + wire d2rnk2; + wire CLKD; + wire CLKDIVD; + wire iodelay_state; + +// attribute + reg data_rate_int; + reg [3:0] data_width_int; + reg [1:0] tristate_width_int; + reg data_rate_oq_int; + reg [1:0] data_rate_tq_int; + reg ddr3_data_int; + reg interface_type_int; + reg odelay_used_int; + reg serdes_mode_int; + +// Output signals + wire ioclkglitch_out, ocbextend_out, ofb_out, oq_out, tq_out, shiftout1_out, shiftout2_out; + +// Other signals + tri0 GSR = glbl.GSR; + + + + wire CLK_in; + wire CLKDIV_in; + wire CLKPERF_in; + wire CLKPERFDELAY_in; + wire D1_in; + wire D2_in; + wire D3_in; + wire D4_in; + wire D5_in; + wire D6_in; + wire OCE_in; + wire ODV_in; + wire RST_in; + wire SHIFTIN1_in; + wire SHIFTIN2_in; + wire T1_in; + wire T2_in; + wire T3_in; + wire T4_in; + wire TCE_in; + wire WC_in; + + + + assign CLK_in = CLK; + assign CLKDIV_in = CLKDIV; + assign D1_in = D1; + assign D2_in = D2; + assign D3_in = D3; + assign D4_in = D4; + assign D5_in = D5; + assign D6_in = D6; + assign OCE_in = OCE; + assign T1_in = T1; + assign T2_in = T2; + assign T3_in = T3; + assign T4_in = T4; + assign TCE_in = TCE; + assign WC_in = WC; + + + assign CLKPERF_in = CLKPERF; +// assign CLKPERFDELAY_in = CLKPERFDELAY; +// IR 495397 & IR 499954 +// assign CLKPERFDELAY_in = (CLKPERFDELAY === 1'bx)? 1'b0 : CLKPERFDELAY; + generate + case (ODELAY_USED) + 0: assign CLKPERFDELAY_in = CLKPERF; + 1: assign CLKPERFDELAY_in = (CLKPERFDELAY === 1'bx)? 1'b0 : CLKPERFDELAY; + endcase + endgenerate + + assign SHIFTIN1_in = SHIFTIN1; + assign SHIFTIN2_in = SHIFTIN2; + assign ODV_in = ODV; + assign RST_in = RST; + + + initial begin + +//------------------------------------------------- +//----- DATA_RATE_OQ check +//------------------------------------------------- + case (DATA_RATE_OQ) + "SDR" : data_rate_oq_int <= 1'b1; + "DDR" : data_rate_oq_int <= 1'b0; + default : begin + $display("Attribute Syntax Error : The attribute DATA_RATE_OQ on OSERDESE1 instance %m is set to %s. Legal values for this attribute are SDR or DDR", DATA_RATE_OQ); + $finish; + end + endcase // case(DATA_RATE_OQ) + +//------------------------------------------------- +//----- DATA_RATE_TQ check +//------------------------------------------------- + case (DATA_RATE_TQ) + + "BUF" : data_rate_tq_int <= 2'b00; + "SDR" : data_rate_tq_int <= 2'b01; + "DDR" : data_rate_tq_int <= 2'b10; + default : begin + $display("Attribute Syntax Error : The attribute DATA_RATE_TQ on OSERDESE1 instance %m is set to %s. Legal values for this attribute are BUF, SDR or DDR", DATA_RATE_TQ); + $finish; + end + + endcase // case(DATA_RATE_TQ) + +//------------------------------------------------- +//----- DATA_WIDTH check +//------------------------------------------------- + case (DATA_WIDTH) + + 2, 3, 4, 5, 6, 7, 8, 10 : data_width_int = DATA_WIDTH; + default : begin + $display("Attribute Syntax Error : The attribute DATA_WIDTH on OSERDESE1 instance %m is set to %d. Legal values for this attribute are 2, 3, 4, 5, 6, 7, 8, or 10", DATA_WIDTH); + $finish; + end + endcase // case(DATA_WIDTH) + +//------------------------------------------------- +//----- DDR3_DATA check +//------------------------------------------------- + case (DDR3_DATA) + 0 : ddr3_data_int <= 1'b0; + 1 : ddr3_data_int <= 1'b1; + default : begin + $display("Attribute Syntax Error : The attribute DDR3_DATA on OSERDESE1 instance %m is set to %d. Legal values for this attribute are 0 or 1", DDR3_DATA); + $finish; + end + endcase // case(DDR3_DATA) + +//------------------------------------------------- +//----- INTERFACE_TYPE check +//------------------------------------------------- + case (INTERFACE_TYPE) + "DEFAULT" : interface_type_int <= 1'b0; + "MEMORY_DDR3" : interface_type_int <= 1'b1; + default : begin + $display("Attribute Syntax Error : The attribute INTERFACE_TYPE on OSERDESE1 instance %m is set to %s. Legal values for this attribute are DEFAULT, or MEMORY_DDR3", INTERFACE_TYPE); + $finish; + end + endcase // INTERFACE_TYPE + + +//------------------------------------------------- +//----- ODELAY_USED check +//------------------------------------------------- + case (ODELAY_USED) + +// "FALSE" : odelay_used_int <= 1'b0; +// "TRUE" : odelay_used_int <= 1'b1; + 0 : odelay_used_int <= 1'b0; + 1 : odelay_used_int <= 1'b1; + default : begin + $display("Attribute Syntax Error : The attribute ODELAY_USED on OSERDESE1 instance %m is set to %s. Legal values for this attribute are FALSE or TRUE", ODELAY_USED); + $finish; + end + + endcase // case(ODELAY_USED) + +//------------------------------------------------- +//----- SERDES_MODE check +//------------------------------------------------- + case (SERDES_MODE) + + "MASTER" : serdes_mode_int <= 1'b0; + "SLAVE" : serdes_mode_int <= 1'b1; + default : begin + $display("Attribute Syntax Error : The attribute SERDES_MODE on OSERDESE1 instance %m is set to %s. Legal values for this attribute are MASTER or SLAVE", SERDES_MODE); + $finish; + end + + endcase // case(SERDES_MODE) + +//------------------------------------------------- +//----- TRISTATE_WIDTH check +//------------------------------------------------- + case (TRISTATE_WIDTH) + + 1 : tristate_width_int <= 2'b00; + 2 : tristate_width_int <= 2'b01; + 4 : tristate_width_int <= 2'b10; + default : begin + $display("Attribute Syntax Error : The attribute TRISTATE_WIDTH on OSERDESE1 instance %m is set to %d. Legal values for this attribute are 1, 2 or 4", TRISTATE_WIDTH); + $finish; + end + + endcase // case(TRISTATE_WIDTH) + +//------------------------------------------------- + end // initial begin + +//------------------------------------------------- + + assign SERDES = 1'b1; + assign SRTYPE = 6'b111111; + assign DDR_CLK_EDGE = 1'b1; + assign WC_DELAY = 1'b0; + assign SELFHEAL = 5'b00000; + + assign #0 CLKD = CLK; + assign #0 CLKDIVD = CLKDIV; + + + assign #10 ofb_out = (ODELAY_USED == 1)? CLKPERF : oq_out; + assign #10 tfb_out = iodelay_state; + + +///////////////////////////////////////////////////////// +// +// Delay assignments +// +///////////////////////////////////////////////////////// + +// Data output delays +defparam dfront.FFD = 1; // clock to out delay for flip flops +// driven by clk +defparam datao.FFD = 1; // clock to out delay for flip flops +// driven by clk +defparam dfront.FFCD = 1; // clock to out delay for flip flops +// driven by clkdiv +defparam dfront.MXD = 1; // mux delay + +defparam dfront.MXR1 = 1; // mux before 2nd rank of flops + +// Programmable load generator +defparam dfront.ldgen.ffdcnt = 1; +defparam dfront.ldgen.mxdcnt = 1; +defparam dfront.ldgen.FFRST = 145; // clock to out delay for flop in PLSG + +// Tristate output delays +defparam tfront.ffd = 1; // clock to out delay for flip flops +defparam tfront.mxd = 1; // mux delay + +defparam trio.ffd = 1; // clock to out delay for flip flops +defparam trio.mxd = 1; // mux delay + +//------------------------------------------------------------------ +// Instantiate output data section +//------------------------------------------------------------------ + +rank12d_oserdese1_vlog dfront (.D1(D1_in), .D2(D2_in), .D3(D3_in), .D4(D4_in), .D5(D5_in), .D6(D6_in), + .d2rnk2(d2rnk2), + .SHIFTIN1(SHIFTIN1_in), .SHIFTIN2(SHIFTIN2_in), + .C(CLK_in), .CLKDIV(CLKDIV_in), .SR(RST_in), .OCE(OCE_in), + .data1(data1), .data2(data2), .SHIFTOUT1(shiftout1_out), .SHIFTOUT2(shiftout2_out), + .DATA_RATE_OQ(data_rate_oq_int), .DATA_WIDTH(data_width_int), + .SERDES_MODE(serdes_mode_int), .load(load), + .IOCLK_GLITCH(ioclkglitch_out), + .INIT_OQ(INIT_OQ), .SRVAL_OQ(SRVAL_OQ)); + + +trif_oserdese1_vlog tfront (.T1(T1_in), .T2(T2_in), .T3(T3_in), .T4(T4_in), .load(load), + .C(CLK_in), .CLKDIV(CLKDIV_in), .SR(RST_in), .TCE(TCE_in), + .DATA_RATE_TQ(data_rate_tq_int), .TRISTATE_WIDTH(tristate_width_int), + .INIT_TQ(INIT_TQ), .SRVAL_TQ(SRVAL_TQ), + .data1(triin1), .data2(triin2)); + + +txbuffer_oserdese1_vlog DDR3FIFO (.iodelay_state(iodelay_state), .qmux1(qmux1), .qmux2(qmux2), .tmux1(tmux1), .tmux2(tmux2), + .d1(data1), .d2(data2), .t1(triin1), .t2(triin2), .trif(tq_out), + .WC(WC_in), .ODV(ODV_in), .extra(ocbextend_out), + .clk(CLK_in), .clkdiv(CLKDIV_in), .bufo(CLKPERFDELAY_in), .bufop(CLKPERF_in), .rst(RST_in), + .ODELAY_USED(odelay_used_int), .DDR3_DATA(ddr3_data_int), + .DDR3_MODE(interface_type_int)); + +dout_oserdese1_vlog datao (.data1(qmux1), .data2(qmux2), + .CLK(CLK_in), .BUFO(CLKPERFDELAY_in), .SR(RST_in), .OCE(OCE_in), + .OQ(oq_out), .d2rnk2(d2rnk2), + .DATA_RATE_OQ(data_rate_oq_int), + .INIT_OQ(INIT_OQ), .SRVAL_OQ(SRVAL_OQ), + .DDR3_MODE(interface_type_int)); + +tout_oserdese1_vlog trio (.data1(tmux1), .data2(tmux2), + .CLK(CLK_in), .BUFO(CLKPERFDELAY_in), .SR(RST_in), .TCE(TCE_in), + .DATA_RATE_TQ(data_rate_tq_int), .TRISTATE_WIDTH(tristate_width_int), + .INIT_TQ(INIT_TQ), .SRVAL_TQ(SRVAL_TQ), + .TQ(tq_out), .DDR3_MODE(interface_type_int)); + + assign OCBEXTEND = ocbextend_out; + assign OFB = ofb_out; + assign OQ = oq_out; + assign SHIFTOUT1 = shiftout1_out; + assign SHIFTOUT2 = shiftout2_out; + assign TFB = tfb_out; + assign TQ = tq_out; + + specify + ( CLK => OQ) = (100, 100); + ( CLK => TQ) = (100, 100); + ( CLKPERF => OQ) = (100, 100); + ( CLKPERF => TQ) = (100, 100); + ( CLKPERFDELAY => OQ) = (100, 100); + ( CLKPERFDELAY => TQ) = (100, 100); + ( T1 => TQ) = (0, 0); + + specparam PATHPULSE$ = 0; + + endspecify + +endmodule // OSERDESE1 + +`timescale 1ps/1ps +///////////////////////////////////////////////////////// +// +// module selfheal_oserdese1_vlog +// +/////////////////////////////////////////////////////// +// +// Self healing circuit for Mt Blanc +// This model ONLY works for SERDES operation!! +// +// +// +//////////////////////////////////////////////////////// +// +// +// +///////////////////////////////////////////////////////// +// +// Inputs: +// dq3 - dq0: Data from load counter +// CLKDIV: Divided clock from PLL +// srint: RESET from load generator +// rst: Set/Reset control +// +// +// +// Outputs: +// SHO: Data output +// +// +// +// Programmable Points +// SELFHEAL: String of 5 bits. 1 as enable and 4 as compare +// Test attributes in model +// +// +// +// +// +//////////////////////////////////////////////////////////////////////////////// +// + +module selfheal_oserdese1_vlog (dq3, dq2, dq1, dq0, + CLKDIV, srint, rst, + SHO); + +input dq3, dq2, dq1, dq0; + +input CLKDIV, srint, rst; + +output SHO; + + +reg shr; + +reg SHO; + + +wire clkint; + +wire error; + +wire rst_in, rst_self_heal; + + +// Programmable Points + +wire [4:0] SELFHEAL; +assign SELFHEAL = 5'b00000; + + + +////////////////////////////////////////////////// +// Delay values +// +parameter FFD = 10; // clock to out delay for flip flops +// driven by clk +parameter FFCD = 10; // clock to out delay for flip flops +// driven by clkdiv +parameter MXD = 10; // 60 ps mux delay + +parameter MXR1 = 10; + + + +///////////////////////////////////////// + + +assign clkint = CLKDIV & SELFHEAL[4]; + +assign error = (((~SELFHEAL[4] ^ SELFHEAL[3]) ^ dq3) | ((~SELFHEAL[4] ^ SELFHEAL[2]) ^ dq2) | ((~SELFHEAL[4] ^ SELFHEAL[1]) ^ dq1) | ((~SELFHEAL[4] ^ SELFHEAL[0]) ^ dq0)); + +assign rst_in = (~SELFHEAL[4] | ~srint); + +assign rst_self_heal = (rst | ~shr); + +///////////////////////////////////////// +// Reset Flop +//////////////////////////////////////// + +always @ (posedge clkint or posedge rst) +begin + begin + if (rst) + begin + shr <= # FFD 1'b0; + end + else begin + shr <= #FFD rst_in; + end + end +end + +// Self heal flop +always @ (posedge clkint or posedge rst_self_heal) +begin + begin + + if (rst_self_heal) + begin + SHO <= 1'b0; + end + else + begin + SHO <= # FFD error; + end + end +end + + + + +endmodule +`timescale 1ps/1ps +//////////////////////////////////////////////////////// +// +// module plg_oserdese1_vlog +// +//////////////////////////////////////////////////////// +// +// Programmable Load Generator (PLG) +// Divide by 2-8 counter with load enable output +// +// +///////////////////////////////////////////////////////// +// +// Inputs: +// c23: Selects between divide by 2 or 3 +// c45: Selects between divide by 4 or 5 +// c67: Selects between divide by 6 or 7 +// sel: Selects which divide function is chosen +// 00:2 or 3, 01:4 or 5, 10:6 or 7, 11:8 +// clk: High speed clock from DCM +// clkdiv: Low speed clock from DCM +// rst: Reset +// +// +// +// Outputs: +// +// load: Loads serdes register at terminal count +// +// +// Test attributes: +// INIT_LOADCNT: 4-bits to init counter +// SRTYPE: 1-bit to control synchronous or asynchronous operation +// SELFHEAL: 5-bits to control self healing feature +// +// +// +//////////////////////////////////////////////////////////////////////////////// +// + +module plg_oserdese1_vlog (c23, c45, c67, sel, + clk, clkdiv, rst, + load, IOCLK_GLITCH); + +input c23, c45, c67; + +input [1:0] sel; + +input clk, clkdiv, rst; + +output load; + +output IOCLK_GLITCH; + +wire SRTYPE; +wire [3:0] INIT_LOADCNT; +wire [4:0] SELFHEAL; +assign SRTYPE = 1'b1; +assign INIT_LOADCNT = 4'b0000; +assign SELFHEAL = 5'b00000; + +reg q0, q1, q2, q3; + +reg qhr, qlr; + +reg load, mux; + +wire cntrrst; + + +assign cntrrst = IOCLK_GLITCH | rst; + + + +// Parameters for gate delays +parameter ffdcnt = 1; +parameter mxdcnt = 1; +parameter FFRST = 145; // clock to out delay for flop in PLSG + + + +////////////////////////////////////////////////// + +tri0 GSR = glbl.GSR; + +always @(GSR) +begin + if (GSR) + begin + assign q3 = INIT_LOADCNT[3]; + assign q2 = INIT_LOADCNT[2]; + assign q1 = INIT_LOADCNT[1]; + assign q0 = INIT_LOADCNT[0]; + end + else + begin + deassign q3; + deassign q2; + deassign q1; + deassign q0; + end +end + + + + + + + +// flops for counter +// asynchronous reset +always @ (posedge qhr or posedge clk) +begin + if (qhr & !SRTYPE) + begin + q0 <= # ffdcnt 1'b0; + q1 <= # ffdcnt 1'b0; + q2 <= # ffdcnt 1'b0; + q3 <= # ffdcnt 1'b0; + end + else if (!SRTYPE) + begin + q3 <= # ffdcnt q2; + q2 <= # ffdcnt (!(!q0 & !q2) & q1); + q1 <= # ffdcnt q0; + q0 <= # ffdcnt mux; + end +end +// synchronous reset +always @ (posedge clk) +begin + if (qhr & SRTYPE) + begin + q0 <= # ffdcnt 1'b0; + q1 <= # ffdcnt 1'b0; + q2 <= # ffdcnt 1'b0; + q3 <= # ffdcnt 1'b0; + end + else if (SRTYPE) + begin + q3 <= # ffdcnt q2; + q2 <= # ffdcnt (!(!q0 & !q2) & q1); + q1 <= # ffdcnt q0; + q0 <= # ffdcnt mux; + end +end + + +// mux settings for counter +always @ (sel or c23 or c45 or c67 or q0 or q1 or q2 or q3) + begin + case (sel) + 2'b00: mux <= # mxdcnt (!q0 & !(c23 & q1)); + 2'b01: mux <= # mxdcnt (!q1 & !(c45 & q2)); + 2'b10: mux <= # mxdcnt (!q2 & !(c67 & q3)); + 2'b11: mux <= # mxdcnt !q3; + default: mux <= # mxdcnt 1'b0; + endcase + end + + +// mux decoding for load signal +always @ (sel or c23 or c45 or c67 or q0 or q1 or q2 or q3) + begin + case (sel) + 2'b00: load <= # mxdcnt q0; + 2'b01: load <= # mxdcnt q0 & q1; + 2'b10: load <= # mxdcnt q0 & q2; + 2'b11: load <= # mxdcnt q0 & q3; + default: load <= # mxdcnt 1'b0; + endcase + end + +// flops to reset counter + +// Low speed flop +// asynchronous reset +always @ (posedge cntrrst or posedge clkdiv) + begin + if (cntrrst & !SRTYPE) + begin + qlr <= # FFRST 1'b1; + end + else if (!SRTYPE) + begin + qlr <= # FFRST 1'b0; + end + end +// synchronous reset +always @ (posedge clkdiv) + begin + if (cntrrst & SRTYPE) + begin + qlr <= # FFRST 1'b1; + end + else if (SRTYPE) + begin + qlr <= # FFRST 1'b0; + end + end + + + +// High speed flop +// asynchronous reset +always @ (posedge cntrrst or posedge clk) + begin + if (cntrrst & !SRTYPE) + begin + qhr <= # ffdcnt 1'b1; + end + else if (!SRTYPE) + begin + qhr <= # ffdcnt qlr; + end + end +// synchronous reset +always @ (posedge clk) + begin + if (cntrrst & SRTYPE) + begin + qhr <= # ffdcnt 1'b1; + end + else if (SRTYPE) + begin + qhr <= # ffdcnt qlr; + end + end + +selfheal_oserdese1_vlog fixcntr (.dq3(q3), .dq2(q2), .dq1(q1), .dq0(q0), + .CLKDIV(clkdiv), .srint(qlr), .rst(rst), + .SHO(IOCLK_GLITCH)); +endmodule +`timescale 1ps/1ps +//////////////////////////////////////////////////////// +// +// module rank12d_oserdese1_vlog +// +// +// This model ONLY works for SERDES operation!! +// Does not include tristate circuit +// +// +//////////////////////////////////////////////////////// +// +// Inputs: +// D1: Data input 1 +// D2: Data input 2 +// D3: Data input 3 +// D4: Data input 4 +// D5: Data input 5 +// D6: Data input 6 +// C: High speed clock from DCM +// OCE: Clock enable for output data flops +// SR: Set/Reset control. For the last 3 flops in OQ +// (d1rnk2, d2rnk2 and d2nrnk2) this function is +// controlled bythe attributes SRVAL_OQ. In SERDES mode, +// SR is a RESET ONLY for all other flops! The flops will +// still be RESET even if SR is programmed to a SET! +// CLKDIV: Low speed divided clock from DCM +// SHIFTIN1: Carry in data 1 for master from slave +// SHIFTIN2: Carry in data 2 for master from slave +// +// +// +// Outputs: +// data1: Data output mux for top flop +// data2: Data output mux for bottom flop +// SHIFTOUT1: Carry out data 1 for slave +// SHIFTOUT2: Carry out data 2 for slave +// load: Used for the tristate when combined into a single model +// +// +// +// Programmable Points +// DATA_RATE_OQ: Rate control for data output, 1-bit +// sdr (1), ddr (0) +// DATA_WIDTH: Input data width, +// 4-bits, values can be from 2 to 10 +// SERDES_MODE: Denotes master (0) or slave (1) +// SIM_X_INPUT: This attribute is NOT SUPPORTED in this model!!! +// +// +// +// Programmable points for Test model +// SRTYPE: This is a 4-bit field Sets asynchronous (0) or synchronous (1) set/reset +// 1st bit (msb) sets rank1 flops, 2nd bit sets 4 flops in rank 2, +// 3rd bit sets "3 legacy flops, and 4th (lsb) bit sets the counter +// INIT_ORANK1: Init value for 6 registers in 1st rank (6-bits) +// INIT_ORANK2_PARTIAL: Init value for bottom 4 registers in the 2nd rank (4-bits) +// INIT_LOADCNT: Init value for the load counter (4-bits) +// The other 2 registers in the load counter have init bits, but are +// not supported in this model +// SERDES: Indicates that SERDES mode is chosen +// SLEFHEAL: 5-bit to set self heal circuit +// +// +//////////////////////////////////////////////////////////////////////////////// +// + +module rank12d_oserdese1_vlog (D1, D2, D3, D4, D5, D6, d2rnk2, + SHIFTIN1, SHIFTIN2, + C, CLKDIV, SR, OCE, + data1, data2, SHIFTOUT1, SHIFTOUT2, + DATA_RATE_OQ, DATA_WIDTH, + SERDES_MODE, load, + IOCLK_GLITCH, + INIT_OQ, SRVAL_OQ); + +input D1, D2, D3, D4, D5, D6; + +input d2rnk2; + +input SHIFTIN1, SHIFTIN2; + +input C, CLKDIV, SR, OCE; + +input INIT_OQ, SRVAL_OQ; + +output data1, data2; + +output SHIFTOUT1, SHIFTOUT2; + +output load; + +output IOCLK_GLITCH; + +// Programmable Points + +input DATA_RATE_OQ; + +input [3:0] DATA_WIDTH; + +input SERDES_MODE; + +wire DDR_CLK_EDGE, SERDES; +wire [3:0] SRTYPE; +wire [4:0] SELFHEAL; + +wire [3:0] INIT_ORANK2_PARTIAL; +wire [5:0] INIT_ORANK1; + +assign DDR_CLK_EDGE = 1'b1; +assign SERDES = 1'b1; +assign SRTYPE = 4'b1111; +assign SELFHEAL = 5'b00000; + +assign INIT_ORANK2_PARTIAL = 4'b0000; +assign INIT_ORANK1 = 6'b000000; + +reg d1r, d2r, d3r, d4r, d5r, d6r; + +reg d3rnk2, d4rnk2, d5rnk2, d6rnk2; + +reg data1, data2, data3, data4, data5, data6; + +reg ddr_data, odata_edge, sdata_edge; + +reg c23, c45, c67; + +reg [1:0] sel; + +wire C2p, C3; + +wire loadint; + +wire [3:0] seloq; + +wire oqsr, oqrev; + +wire [2:0] sel1_4; + +wire [3:0] sel5_6; + +wire [4:0] plgcnt; + +assign C2p = (C & DDR_CLK_EDGE) | (!C & !DDR_CLK_EDGE); + +assign C3 = !C2p; + +assign plgcnt = {DATA_RATE_OQ,DATA_WIDTH}; + +assign sel1_4 = {SERDES,loadint,DATA_RATE_OQ}; + +assign sel5_6 = {SERDES,SERDES_MODE,loadint,DATA_RATE_OQ}; + +assign load = loadint; + +assign seloq = {OCE,DATA_RATE_OQ,oqsr,oqrev}; + +assign oqsr = !SRTYPE[1] & SR & !SRVAL_OQ; + +assign oqrev = !SRTYPE[1] & SR & SRVAL_OQ; + + + +////////////////////////////////////////////////// +// Delay values +// +parameter FFD = 1; // clock to out delay for flip flops +// driven by clk +parameter FFCD = 1; // clock to out delay for flip flops +// driven by clkdiv +parameter MXD = 1; // 60 ps mux delay + +parameter MXR1 = 1; + +//////////////////////////////////////////// +// Initialization of flops with GSR for test model +/////////////////////////////////////////// + +tri0 GSR = glbl.GSR; + +always @(GSR) +begin + if (GSR) + begin + assign d6rnk2 = INIT_ORANK2_PARTIAL[3]; + assign d5rnk2 = INIT_ORANK2_PARTIAL[2]; + assign d4rnk2 = INIT_ORANK2_PARTIAL[1]; + assign d3rnk2 = INIT_ORANK2_PARTIAL[0]; + + assign d6r = INIT_ORANK1[5]; + assign d5r = INIT_ORANK1[4]; + assign d4r = INIT_ORANK1[3]; + assign d3r = INIT_ORANK1[2]; + assign d2r = INIT_ORANK1[1]; + assign d1r = INIT_ORANK1[0]; + end + else + begin + deassign d6rnk2; + deassign d5rnk2; + deassign d4rnk2; + deassign d3rnk2; + deassign d6r; + deassign d5r; + deassign d4r; + deassign d3r; + deassign d2r; + deassign d1r; + end +end + +///////////////////////////////////////// + + + +// Assign shiftout1 and shiftout2 + +assign SHIFTOUT1 = d3rnk2 & SERDES_MODE; + +assign SHIFTOUT2 = d4rnk2 & SERDES_MODE; + + + + + + +// last 4 flops which only have reset and init +// asynchronous operation +always @ (posedge C or posedge SR) +begin + begin + if (SR & !SRTYPE[2]) + begin + d3rnk2 <= # FFD 1'b0; + d4rnk2 <= # FFD 1'b0; + d5rnk2 <= # FFD 1'b0; + d6rnk2 <= # FFD 1'b0; + end + else if (!SRTYPE[2]) + begin + d3rnk2 <= # FFD data3; + d4rnk2 <= # FFD data4; + d5rnk2 <= # FFD data5; + d6rnk2 <= # FFD data6; + + end + end +end +// synchronous operation +always @ (posedge C) +begin + begin + if (SR & SRTYPE[2]) + begin + d3rnk2 <= # FFD 1'b0; + d4rnk2 <= # FFD 1'b0; + d5rnk2 <= # FFD 1'b0; + d6rnk2 <= # FFD 1'b0; + end + else if (SRTYPE[2]) + begin + d3rnk2 <= # FFD data3; + d4rnk2 <= # FFD data4; + d5rnk2 <= # FFD data5; + d6rnk2 <= # FFD data6; + + end + end +end + + + + + + + +/////////////////////////////////////////////////// +// First rank of flops for input data +////////////////////////////////////////////////// + +// asynchronous operation +always @ (posedge CLKDIV or posedge SR) +begin + begin + if (SR & !SRTYPE[3]) + begin + d1r <= # FFCD 1'b0; + d2r <= # FFCD 1'b0; + d3r <= # FFCD 1'b0; + d4r <= # FFCD 1'b0; + d5r <= # FFCD 1'b0; + d6r <= # FFCD 1'b0; + end + else if (!SRTYPE[3]) + begin + d1r <= # FFCD D1; + d2r <= # FFCD D2; + d3r <= # FFCD D3; + d4r <= # FFCD D4; + d5r <= # FFCD D5; + d6r <= # FFCD D6; + + end + end +end +// synchronous operation +always @ (posedge CLKDIV) +begin + begin + if (SR & SRTYPE[3]) + begin + d1r <= # FFCD 1'b0; + d2r <= # FFCD 1'b0; + d3r <= # FFCD 1'b0; + d4r <= # FFCD 1'b0; + d5r <= # FFCD 1'b0; + d6r <= # FFCD 1'b0; + end + else if (SRTYPE[3]) + begin + d1r <= # FFCD D1; + d2r <= # FFCD D2; + d3r <= # FFCD D3; + d4r <= # FFCD D4; + d5r <= # FFCD D5; + d6r <= # FFCD D6; + + end + end +end + +// Muxs for 2nd rank of flops +always @ (sel1_4 or d1r or d2rnk2 or d3rnk2) + begin + + casex (sel1_4) + 3'b100: data1 <= # MXR1 d3rnk2; + 3'b110: data1 <= # MXR1 d1r; + 3'b101: data1 <= # MXR1 d2rnk2; + 3'b111: data1 <= # MXR1 d1r; + default: data1 <= # MXR1 d3rnk2; + endcase + end + +always @ (sel1_4 or d2r or d3rnk2 or d4rnk2) + begin + casex (sel1_4) + 3'b100: data2 <= # MXR1 d4rnk2; + 3'b110: data2 <= # MXR1 d2r; + 3'b101: data2 <= # MXR1 d3rnk2; + 3'b111: data2 <= # MXR1 d2r; + default: data2 <= # MXR1 d4rnk2; + endcase + end + +//Note: To stop data rate of 00 from being illegal, register data is fed to mux +always @ (sel1_4 or d3r or d4rnk2 or d5rnk2) + begin + casex (sel1_4) + 3'b100: data3 <= # MXR1 d5rnk2; + 3'b110: data3 <= # MXR1 d3r; + 3'b101: data3 <= # MXR1 d4rnk2; + 3'b111: data3 <= # MXR1 d3r; + default: data3 <= # MXR1 d5rnk2; + endcase + end + +always @ (sel1_4 or d4r or d5rnk2 or d6rnk2) + begin + casex (sel1_4) + 3'b100: data4 <= # MXR1 d6rnk2; + 3'b110: data4 <= # MXR1 d4r; + 3'b101: data4 <= # MXR1 d5rnk2; + 3'b111: data4 <= # MXR1 d4r; + default: data4 <= # MXR1 d6rnk2; + endcase + end + +always @ (sel5_6 or d5r or d6rnk2 or SHIFTIN1) + begin + casex (sel5_6) + 4'b1000: data5 <= # MXR1 SHIFTIN1; + 4'b1010: data5 <= # MXR1 d5r; + 4'b1001: data5 <= # MXR1 d6rnk2; + 4'b1011: data5 <= # MXR1 d5r; + 4'b1100: data5 <= # MXR1 1'b0; + 4'b1110: data5 <= # MXR1 d5r; + 4'b1101: data5 <= # MXR1 d6rnk2; + 4'b1111: data5 <= # MXR1 d5r; + default: data5 <= # MXR1 SHIFTIN1; + endcase + end + +always @ (sel5_6 or D6 or d6r or SHIFTIN1 or SHIFTIN2) + begin + casex (sel5_6) + 4'b1000: data6 <= # MXR1 SHIFTIN2; + 4'b1010: data6 <= # MXR1 d6r; + 4'b1001: data6 <= # MXR1 SHIFTIN1; + 4'b1011: data6 <= # MXR1 d6r; + 4'b1100: data6 <= # MXR1 1'b0; + 4'b1110: data6 <= # MXR1 d6r; + 4'b1101: data6 <= # MXR1 1'b0; + 4'b1111: data6 <= # MXR1 d6r; + default: data6 <= # MXR1 SHIFTIN2; + endcase + end + + + + +// instantiate programmable load generator +plg_oserdese1_vlog ldgen (.c23(c23), .c45(c45), .c67(c67), .sel(sel), + .clk(C), .clkdiv(CLKDIV), .rst(SR), + .load(loadint), .IOCLK_GLITCH(IOCLK_GLITCH)); + +// Set value of counter in programmable load generator +always @ (plgcnt or c23 or c45 or c67 or sel) +begin + casex (plgcnt) + 5'b00100: begin c23=1'b0; c45=1'b0; c67=1'b0; sel=2'b00; end + 5'b00110: begin c23=1'b1; c45=1'b0; c67=1'b0; sel=2'b00; end + 5'b01000: begin c23=1'b0; c45=1'b0; c67=1'b0; sel=2'b01; end + 5'b01010: begin c23=1'b0; c45=1'b1; c67=1'b0; sel=2'b01; end + 5'b10010: begin c23=1'b0; c45=1'b0; c67=1'b0; sel=2'b00; end + 5'b10011: begin c23=1'b1; c45=1'b0; c67=1'b0; sel=2'b00; end + 5'b10100: begin c23=1'b0; c45=1'b0; c67=1'b0; sel=2'b01; end + 5'b10101: begin c23=1'b0; c45=1'b1; c67=1'b0; sel=2'b01; end + 5'b10110: begin c23=1'b0; c45=1'b0; c67=1'b0; sel=2'b10; end + 5'b10111: begin c23=1'b0; c45=1'b0; c67=1'b1; sel=2'b10; end + 5'b11000: begin c23=1'b0; c45=1'b0; c67=1'b0; sel=2'b11; end + default: $display("DATA_WIDTH %b and DATA_RATE_OQ %b at %t is an illegal value", DATA_WIDTH, DATA_RATE_OQ, $time); + endcase +end + +endmodule +`timescale 1ps/1ps +////////////////////////////////////////////////////////// +// +// module trif_oserdese1_vlog +// +///////////////////////////////////////////////////////// +// +// Inputs: +// +// T1, T2, T3, T4: tristate inputs +// load: Programmable load generator output +// TCE: Tristate clock enable +// SR: Set/Reset control. For the last 3 flops in TQ +// (qt1, qt2 and qt2n) this function is +// controlled bythe attributes SRVAL_TQ. In SERDES mode, +// SR is a RESET ONLY for all other flops! The flops will +// still be RESET even if SR is programmed to a SET! +// C, C2: High speed clocks +// C2 drives 2nd latch and C3 (inverse of C2) drives +// 3rd latch in output section +// CLKDIV: Low speed clock +// +// +// +// +// Outputs: +// +// TQ: Output of tristate mux +// +// +// Programmable Options: +// +// DATA_RATE_TQ: 2-bit field for types of operaiton +// 0 (buf from T1), 1 (registered output from T1), 2 (ddr) +// TRISTATE_WIDTH: 2-bit field for input width +// 0 (width 1), 1 (width 2), 2 (width 4) +// INIT_TQ: Init TQ output (0,1) +// SRVAL_TQ: This bit to controls value of SR input. +// Only the last 3 flops (qt1, qt2 and qt2n) are +// affected by this bit.For SERDES mode, this bit +// should be set to '0' making SR a reset. This is the +// desired state since all other flops only +// respond to this pin as a reset. Their function +// cannot be changed. SR is 'O' for SET and '1' for RESET. +// +// +// Programmable Test Options: +// SRTYPE: Control S and R as asynchronous (0) or synchronous (1) +// 2-bit value. 1st bit (msb) controls the 4 input flops +// and the 2nd bit (lsb) controls the "3 legacy flops" +// DDR_CLK_EDGE: Same or opposite edge operation +// +// +// +//////////////////////////////////////////////////////////////////////////////// +// + +module trif_oserdese1_vlog (T1, T2, T3, T4, load, + C, CLKDIV, SR, TCE, + DATA_RATE_TQ, TRISTATE_WIDTH, + INIT_TQ, SRVAL_TQ, + data1, data2); + +input T1, T2, T3, T4, load; + +input C, CLKDIV, SR, TCE; + +input [1:0] TRISTATE_WIDTH; + +input [1:0] DATA_RATE_TQ; + +input INIT_TQ, SRVAL_TQ; + +output data1, data2; + +wire DDR_CLK_EDGE; +wire [3:0] INIT_TRANK1; +wire [1:0] SRTYPE; +assign SRTYPE = 2'b11; +assign DDR_CLK_EDGE = 1'b1; +assign INIT_TRANK1 = 4'b0000; + +reg t1r, t2r, t3r, t4r; + +reg qt1, qt2, qt2n; + +reg data1, data2; + +reg sdata_edge, odata_edge, ddr_data; + +wire C2p, C3; + +wire load; + +wire [6:0] tqsel; + +wire [4:0] sel; + +assign sel = {load,DATA_RATE_TQ,TRISTATE_WIDTH}; + + + + + +////////////////////////////////////////////////// + + +// Parameters for gate delays +parameter ffd = 1; +parameter mxd = 1; + + +///////////////////////////// +// Initialization of Flops +//////////////////////////// + +tri0 GSR = glbl.GSR; + +always @(GSR) +begin + if (GSR) + begin + assign t1r = INIT_TRANK1[0]; + assign t2r = INIT_TRANK1[1]; + assign t3r = INIT_TRANK1[2]; + assign t4r = INIT_TRANK1[3]; + + end + else + begin + deassign t1r; + deassign t2r; + deassign t3r; + deassign t4r; + end +end + + + + +// First rank of flops +// asynchronous reset operation +always @ (posedge CLKDIV or posedge SR) +begin + begin + if (SR & !SRTYPE[1]) + begin + t1r <= # ffd 1'b0; + t2r <= # ffd 1'b0; + t3r <= # ffd 1'b0; + t4r <= # ffd 1'b0; + end + else if (!SRTYPE[1]) + begin + t1r <= # ffd T1; + t2r <= # ffd T2; + t3r <= # ffd T3; + t4r <= # ffd T4; + end + end +end + +// synchronous reset operation +always @ (posedge CLKDIV) +begin + begin + if (SR & SRTYPE[1]) + begin + t1r <= # ffd 1'b0; + t2r <= # ffd 1'b0; + t3r <= # ffd 1'b0; + t4r <= # ffd 1'b0; + end + else if (SRTYPE[1]) + begin + t1r <= # ffd T1; + t2r <= # ffd T2; + t3r <= # ffd T3; + t4r <= # ffd T4; + end + end +end + + + + + +// Data Muxs for tristate otuput signals +always @ (sel or T1 or t1r or t3r) + begin + + casex (sel) + 5'b00000: data1 <= # mxd T1; + 5'b10000: data1 <= # mxd T1; + 5'bX0000: data1 <= # mxd T1; + 5'b00100: data1 <= # mxd T1; + 5'b10100: data1 <= # mxd T1; + 5'bX0100: data1 <= # mxd T1; + 5'b01001: data1 <= # mxd T1; + 5'b11001: data1 <= # mxd T1; + 5'b01010: data1 <= # mxd t3r; + 5'b11010: data1 <= # mxd t1r; +// CR 551953 -- enabled TRISTATE_WIDTH to be 1 in DDR mode. No func change, but removed warnings + 5'b01000: ; + 5'b11000: ; + 5'bX1000: ; + + default: $display("DATA_RATE_TQ %b and/or TRISTATE_WIDTH %b at time %t are not supported by OSERDES", DATA_RATE_TQ,TRISTATE_WIDTH,$time); + endcase + end +// For data 2, width of 1 is inserted as acceptable for buf and sdr +// The capability exists in the device if the feature is added +always @ (sel or T2 or t2r or t4r) + begin + casex (sel) + 5'b00000: data2 <= # mxd T2; + 5'b00100: data2 <= # mxd T2; + 5'b10000: data2 <= # mxd T2; + 5'b10100: data2 <= # mxd T2; + 5'bX0000: data2 <= # mxd T2; + 5'bX0100: data2 <= # mxd T2; + 5'b00X00: data2 <= # mxd T2; + 5'b10X00: data2 <= # mxd T2; + 5'bX0X00: data2 <= # mxd T2; + 5'b01001: data2 <= # mxd T2; + 5'b11001: data2 <= # mxd T2; + 5'bX1001: data2 <= # mxd T2; + 5'b01010: data2 <= # mxd t4r; + 5'b11010: data2 <= # mxd t2r; +// CR 551953 -- enabled TRISTATE_WIDTH to be 1 in DDR mode. No func change, but removed warnings + 5'b01000: ; + 5'b11000: ; + 5'bX1000: ; + + default: $display("DATA_RATE_TQ %b and/or TRISTATE_WIDTH %b at time %t are not supported by OSERDES", DATA_RATE_TQ,TRISTATE_WIDTH,$time); + endcase + end + + +endmodule +`timescale 1ps/1ps +////////////////////////////////////////////////////////// +// +// module txbuffer_oserdese1_vlog +// +///////////////////////////////////////////////////////// +// +// FIFO and Control circuit for OSERDES + +module txbuffer_oserdese1_vlog (iodelay_state, qmux1, qmux2, tmux1, tmux2, + d1, d2, t1, t2, trif, + WC, ODV, extra, + clk, clkdiv, bufo, bufop, rst, + ODELAY_USED, DDR3_DATA, + DDR3_MODE); + +input d1, d2, t1, t2; + +input trif; + +input WC, ODV; + +input rst; + +input clk, clkdiv, bufo, bufop; + +input ODELAY_USED, DDR3_DATA; + +input DDR3_MODE; + +output iodelay_state, extra; + +output qmux1, qmux2, tmux1, tmux2; + +wire WC_DELAY; +assign WC_DELAY = 1'b0; + +wire rd_gap1; + +wire rst_bufo_p, rst_bufg_p; + + +wire rst_bufo_rc, rst_bufg_wc, rst_cntr, rst_bufop_rc; + +wire [1:0] qwc, qrd; + +wire bufo_out; + + +fifo_tdpipe_oserdese1_vlog data1 (.muxout(inv_qmux1), .din(~d1), .qwc(qwc), .qrd(qrd), + .rd_gap1(rd_gap1), + .bufg_clk(clk), .bufo_clk(bufo), .rst_bufo_p(rst_bufo_p), .rst_bufg_p(rst_bufg_p), + .DDR3_DATA(DDR3_DATA), .extra(extra), .ODV(ODV), .DDR3_MODE(DDR3_MODE) + + ); + +fifo_tdpipe_oserdese1_vlog data2 (.muxout(inv_qmux2), .din(~d2), .qwc(qwc), .qrd(qrd), + .rd_gap1(rd_gap1), + .bufg_clk(clk), .bufo_clk(bufo), .rst_bufo_p(rst_bufo_p), .rst_bufg_p(rst_bufg_p), + .DDR3_DATA(DDR3_DATA), .extra(extra), .ODV(ODV), .DDR3_MODE(DDR3_MODE) + + ); + +fifo_tdpipe_oserdese1_vlog tris1 (.muxout(inv_tmux1), .din(~t1), .qwc(qwc), .qrd(qrd), + .rd_gap1(rd_gap1), + .bufg_clk(clk), .bufo_clk(bufo), .rst_bufo_p(rst_bufo_p), .rst_bufg_p(rst_bufg_p), + .DDR3_DATA(DDR3_DATA), .extra(extra), .ODV(ODV), .DDR3_MODE(DDR3_MODE) + + ); + +fifo_tdpipe_oserdese1_vlog tris2 (.muxout(inv_tmux2), .din(~t2), .qwc(qwc), .qrd(qrd), + .rd_gap1(rd_gap1), + .bufg_clk(clk), .bufo_clk(bufo), .rst_bufo_p(rst_bufo_p), .rst_bufg_p(rst_bufg_p), + .DDR3_DATA(DDR3_DATA), .extra(extra), .ODV(ODV), .DDR3_MODE(DDR3_MODE) + + ); + +wire qmux1 = ~inv_qmux1; +wire qmux2 = ~inv_qmux2; +wire tmux1 = ~inv_tmux1; +wire tmux2 = ~inv_tmux2; + +fifo_reset_oserdese1_vlog rstckt (.rst_bufo_p(rst_bufo_p), .rst_bufo_rc(rst_bufo_rc), + .rst_bufg_p(rst_bufg_p), .rst_bufg_wc(rst_bufg_wc), + .rst_cntr(rst_cntr), + .bufg_clk(clk), .bufo_clk(bufo), .clkdiv(clkdiv), .rst(rst), + .divide_2(WC_DELAY), .bufop_clk(bufop), .rst_bufop_rc(rst_bufop_rc) + + ); + + + + +fifo_addr_oserdese1_vlog addcntr (.qwc(qwc), .qrd(qrd), .rd_gap1(rd_gap1), .rst_bufg_wc(rst_bufg_wc), .rst_bufo_rc(rst_bufo_rc), .bufg_clk(clk), .bufo_clk(bufo), + .data(DDR3_DATA), .extra(extra), .rst_bufop_rc(rst_bufop_rc), .bufop_clk(bufop) + + ); + + + +iodlyctrl_npre_oserdese1_vlog idlyctrl (.iodelay_state(iodelay_state), .bufo_out(bufo_out), .rst_cntr(rst_cntr), + .wc(WC), .trif(trif), + .rst(rst_bufg_p), .bufg_clk(clk), .bufo_clk(bufo), .bufg_clkdiv(clkdiv), + .ddr3_dimm(ODELAY_USED), .wl6(WC_DELAY) + ); + +endmodule +`timescale 1ps/1ps +//////////////////////////////////////////////////////// +// +// module fifo_tdpipe_oserdese1_vlog +// +//////////////////////////////////////////////////////// + +// FIFO for write path + +module fifo_tdpipe_oserdese1_vlog (muxout, din, qwc, qrd, + rd_gap1, + bufg_clk, bufo_clk, rst_bufo_p, rst_bufg_p, + DDR3_DATA, extra, ODV, DDR3_MODE + + ); + + +input din; + +input [1:0] qwc, qrd; + +input rd_gap1; + +input rst_bufo_p, rst_bufg_p; + +input bufg_clk, bufo_clk; + +input DDR3_DATA, ODV; + +input extra; + +input DDR3_MODE; + +output muxout; + + +reg muxout; + +reg qout1, qout2; + +reg qout_int, qout_int2; + +reg [4:1] fifo; + +reg cin1; + +reg omux; + +wire [2:0] sel; + +reg pipe1, pipe2; + +wire selqoi, selqoi2; + +wire [2:0] selmuxout; + + + + + + +// 4 flops that make up the basic FIFO. They are all clocked +// off of fast BUFG. The first flop is the top flop in the chain. +// The CE input is used to mux the inputs. If the flop is selected, +// CE is high and it takes data from the output of the mux. If the +// flop is not selected, it retains its data. + +always @ (posedge bufg_clk or posedge rst_bufg_p) + begin + if (rst_bufg_p) + begin + fifo <= #10 4'b0000; + end + else if (!qwc[1] & !qwc[0]) + begin + fifo <= #10 {fifo[4:2],din}; + end + else if (!qwc[1] & qwc[0]) + begin + fifo <= #10 {fifo[4:3],din,fifo[1]}; + end + else if (qwc[1] & qwc[0]) + begin + fifo <= #10 {fifo[4],din,fifo[2:1]}; + end + else if (qwc[1] & !qwc[0]) + begin + fifo <= #10 {din,fifo[3:1]}; + end + end + + + +// Capture stage top +// This is the top flop of the "3 flops" for ODDR. This flop, along with the read +// counter will be clocked off of bufo. A 4:1 mux wil decode the outputs of the +// read counter and load the write data. A subsequent 2:1 mux will decode between +// the fifo and the legacy operation + + +// OMUX + +always @ (qrd or fifo) + begin + case (qrd) + 2'b00: omux <= #10 fifo[1]; + 2'b01: omux <= #10 fifo[2]; + 2'b10: omux <= #10 fifo[4]; + 2'b11: omux <= #10 fifo[3]; + default: omux <= #10 fifo[1]; + endcase + end + + +always @ (posedge bufo_clk or posedge rst_bufo_p) + begin + if (rst_bufo_p) + begin + qout_int <= #10 1'b0; + qout_int2 <= #10 1'b0; + end + else + begin + qout_int <= #10 omux; + qout_int2 <= #10 qout_int; + end + end + +assign #10 selqoi = ODV | rd_gap1; + + +always @ (selqoi or qout_int or omux) + begin + case(selqoi) + 1'b0: qout1 <= #10 omux; + 1'b1: qout1 <= #10 qout_int; + default: qout1 <= #10 omux; + endcase + end + +assign #10 selqoi2 = ODV & rd_gap1; + +always @ (selqoi2 or qout_int2 or qout_int) + begin + case(selqoi2) + 1'b0: qout2 <= #10 qout_int; + 1'b1: qout2 <= #10 qout_int2; + default qout2 <= #10 qout_int; + endcase + end + + +assign #14 selmuxout = {DDR3_MODE,DDR3_DATA,extra}; + + +always @ (selmuxout or din or omux or qout1 or qout2) + begin + case (selmuxout) + 3'b000: muxout = #1 din; + 3'b001: muxout = #1 din; + 3'b010: muxout = #1 din; + 3'b011: muxout = #1 din; + 3'b100: muxout = #1 omux; + 3'b101: muxout = #1 omux; + 3'b110: muxout = #1 qout1; + 3'b111: muxout = #1 qout2; + default: muxout = #10 din; + endcase + end + + + +endmodule +`timescale 1ps/1ps +//////////////////////////////////////////////////////// +// +// module fifo_reset_oserdese1_vlog +// +//////////////////////////////////////////////////////// +// +// TX FIFO reset +// +// This design performs 2 functions. One function is to reset all the +// flops in the TX FIFO. The other function is to respond to the signal +// rst_cntr. This signal comes from iodlyctrl and will be used to initiate an +// orderly transition to switch the DQ/DQS I/O from and read to a write. +// This process is required only for DDR3 DIMM support because the IODELAY +// is used for both the inputs and the outputs. The signal from the +// squelch circuit is a present fabric output. An additional input +// indicating that a write command was issued will be +// required for all I/O to support this signal. +// +// This design uses an asynchronous reset to reset all flops. After the +// reset is disabled, a 0 is propagated through the pipe stages to terminate +// the reset. The first 2 flops run off of the clkdiv domain. Their output +// feeds a latch to cross between the clkdiv and bufg_clk domain. The pipe +// stage for the bufg_clk domain is 3 deep, where the last flop is the +// reset signal for the bufg_clk domain. The 2nd flop of the bufg_clk pipe +// is fed to 2 flops that are in the bufo_clk domain. The 2 flops are +// to resolve metastability between the 2 clock domains. +// +// The circuit to enable an orderly transition from read to write uses the +// PREAMBLE_SYNCHED output of a portion of the squelch circuit. This pulse +// will initiate the reset sequence and also generate an enable which will +// switch the IODELAY from an IDELAY to an ODELAY. Timing is as specified in +// the "State of the Union" presentation. +// +// + + +module fifo_reset_oserdese1_vlog (rst_bufo_p, rst_bufo_rc, + rst_bufg_p, rst_bufg_wc, + rst_cntr, + bufg_clk, bufo_clk, clkdiv, rst, + divide_2, bufop_clk, rst_bufop_rc + + ); + + +input rst_cntr; + +input rst; + +input bufg_clk, bufo_clk, clkdiv; + +input bufop_clk; + + +// Memory cell input to support divide by 1 operation +input divide_2; + + +output rst_bufo_p, rst_bufo_rc; +output rst_bufg_p, rst_bufg_wc; + +output rst_bufop_rc; + + +reg [1:0] clkdiv_pipe; + +reg bufg_pipe; + +reg rst_cntr_reg; + +reg [2:0] bufo_rst_p, bufo_rst_rc; + +reg [1:0] bufop_rst_rc; + +reg [1:0] bufg_rst_p, bufg_rst_wc; + +wire bufg_clkdiv_latch, ltint1, ltint2, ltint3; + +wire latch_in; + + + + + + + +// 2 stage pipe for clkdiv domain to allow user to properly +// time everything + + +always @ (posedge bufg_clk or posedge rst) + begin + if (rst) + begin + rst_cntr_reg <= #10 1'b0; + end + else + begin + rst_cntr_reg <= #10 rst_cntr; + end + end + + +always @ (posedge clkdiv or posedge rst) + begin + if (rst) + begin + clkdiv_pipe <= #10 2'b11; + end + else + begin + clkdiv_pipe <= #10 {clkdiv_pipe[0],1'b0}; + end + end + +// Latch to compensate for clkdiv and bufg_clk clock skew +// Built of actual gates + +assign #1 latch_in = clkdiv_pipe[1]; + +assign #1 bufg_clkdiv_latch = !(ltint1 && ltint3); +assign #1 ltint1 = !(latch_in && bufg_clk); +assign #1 ltint2 = !(ltint1 && bufg_clk); +assign #1 ltint3 = !(bufg_clkdiv_latch && ltint2); + + + + + +// BUFG flop to register latch signal +always @ (posedge bufg_clk or posedge rst) + begin + if (rst) + begin + bufg_pipe <= #10 1'b1; + end + else + begin + bufg_pipe <= #10 bufg_clkdiv_latch; + end + end + + + + +// BUFG clock domain resests + +always @ (posedge bufg_clk or posedge rst) + begin + if (rst) + begin + bufg_rst_p <= #10 2'b11; + end + else + begin + bufg_rst_p <= #10 {bufg_rst_p[0],bufg_pipe}; + end + end + + +always @ (posedge bufg_clk or posedge rst_cntr or posedge rst) + begin + if (rst || rst_cntr) + begin + bufg_rst_wc <= #10 2'b11; + end + else + begin + bufg_rst_wc <= #10 {bufg_rst_wc[0],bufg_pipe}; + end + end + + + +// BUFO clock domain Resets +always @ (posedge bufo_clk or posedge rst) + begin + if (rst) + begin + bufo_rst_p <= #10 3'b111; + end + else + begin + bufo_rst_p <= #10 {bufo_rst_p[1:0],bufg_pipe}; + end + end + +always @ (posedge bufo_clk or posedge rst or posedge rst_cntr) + begin + if (rst || rst_cntr) + begin + bufo_rst_rc <= #10 3'b111; + end + else + begin + bufo_rst_rc <= #10 {bufo_rst_rc[1:0],bufg_pipe}; + end + end + + + +always @ (posedge bufop_clk or posedge rst or posedge rst_cntr) + begin + if (rst || rst_cntr) + begin + bufop_rst_rc <= #10 2'b11; + end + else + begin + bufop_rst_rc <= #10 {bufop_rst_rc[0],bufg_pipe}; + end + end + + +// final reset assignments +assign rst_bufo_rc = bufo_rst_rc[1]; + +assign rst_bufo_p = bufo_rst_p[1]; + +assign rst_bufop_rc = bufop_rst_rc[1]; + +assign rst_bufg_wc = bufg_rst_wc[1]; + +assign rst_bufg_p = bufg_rst_p[1]; + + +endmodule +`timescale 1ps/1ps +//////////////////////////////////////////////////////// +// +// module fifo_addr_oserdese1_vlog +// +//////////////////////////////////////////////////////// +// Read and Write address generators for TX FIFO +// +// This circuit contains 2 greycode read and write address generators +// that will be used with the TX FIFO. Both counters generate a +// count sequence of 00 -> 01 -> 11 -> 10 -> 00. + + + +module fifo_addr_oserdese1_vlog (qwc, qrd, rd_gap1, rst_bufg_wc, rst_bufo_rc, bufg_clk, bufo_clk, + data, extra, rst_bufop_rc, bufop_clk + + ); + + +input bufg_clk, bufo_clk; + +input rst_bufo_rc, rst_bufg_wc; + +input rst_bufop_rc; + +input data; // mc to tell if I/O is DDR3 DQ or DQS + +input bufop_clk; + +output qwc, qrd; + +output rd_gap1, extra; + + + + +reg [1:0] qwc; + +reg [1:0] qrd; + + +reg stop_rd, rd_gap1, extra; + +reg rd_cor, rd_cor_cnt, rd_cor_cnt1; + + +wire qwc0_latch, qwc1_latch; + +wire li01, li02, li03; + +wire li11, li12, li13; + + +wire qwc0_latchn, qwc1_latchn; + +wire li01n, li02n, li03n; + +wire li11n, li12n, li13n; + + +reg stop_rdn, rd_cor_cntn, rd_cor_cnt1n, stop_rc; + + + + +reg [1:0] qwcd; + +reg [1:0] qrdd; + + +reg stop_rdd, rd_gap1d, extrad; + +reg rd_cord, rd_cor_cntd, rd_cor_cnt1d; + + +wire qwcd0_latch, qwcd1_latch; + +wire li01d, li02d, li03d; + +wire li11d, li12d, li13d; + + + +// Write counter +// The write counter uses 2 flops to create the grey code pattern of +// 00 -> 01 -> 11 -> 10 -> 00. The write counter is initialized +// to 11 and the read counter will be initialized to 00. This gives +// a basic 2 clock separation to compensate for the phase differences. +// The write counter is clocked off of the bufg clock + +always @ (posedge bufg_clk or posedge rst_bufg_wc) + begin + if (rst_bufg_wc) + begin + qwc <= # 10 2'b11; + end + else if (qwc[1] ^ qwc[0]) + begin + qwc[1] <= # 10 ~qwc[1]; + qwc[0] <= # 10 qwc[0]; + end + else + begin + qwc[1] <= # 10 qwc[1]; + qwc[0] <= # 10 ~qwc[0]; + end + end + + + + + + +// Read counter +// The read counter uses 2 flops to create the grey code pattern of +// 00 -> 01 -> 11 -> 10 -> 00. The read counter is initialized +// to 00 and the write counter will be initialized to 11. This gives +// a basic 2 clock separation to compensate for the phase differences. +// The read counter is clocked off of the bufo clock + +always @ (posedge bufo_clk or posedge rst_bufo_rc) + + begin + if (rst_bufo_rc) + begin + qrd <= # 10 2'b00; + end + else if (stop_rd && !data) + begin + qrd <= #10 qrd; + end + else if (qrd[1] ^ qrd[0]) + begin + qrd[1] <= # 10 ~qrd[1]; + qrd[0] <= # 10 qrd[0]; + end + else + begin + qrd[1] <= # 10 qrd[1]; + qrd[0] <= # 10 ~qrd[0]; + end + end + +always @ (posedge bufo_clk or posedge rst_bufo_rc) + + begin + if (rst_bufo_rc) + begin + rd_gap1 <= # 10 1'b0; + end +// else if ((qwc1_latch && qwc0_latch) && (qrd[0] ^ qrd[1])) + else if ((qwc1_latch && qwc0_latch) && (qrd[0])) + begin + rd_gap1 <= # 10 1'b1; + end + else + begin + rd_gap1 <= # 10 rd_gap1; + end + end + + + + + +// Looking for 11 + +assign #1 qwc0_latch = !(li01 & li03); +assign #1 li01 = !(qwc[0] & bufo_clk); +assign #1 li02 = !(li01 & bufo_clk); +assign #1 li03 = !(qwc0_latch & li02); + + +assign #1 qwc1_latch = !(li11 & li13); +assign #1 li11 = !(qwc[1] & bufo_clk); +assign #1 li12 = !(li11 & bufo_clk); +assign #1 li13 = !(qwc1_latch & li12); + + +// The following counter is to match the control counter to see if the +// read counter did a hold after reset. This knowledge will enable the +// computation of the 'extra' output. This in turn can add the +// proper number of pipe stages to the output. The circuit must use +// the output of BUFO and not be modified by ODELAY. This is because +// the control pins PP clock was not modified by BUFO. If the +// control pins PP clock was modified by BUFO, the reset must be done +// with this in mind. + +// Read counter +// The read counter uses 2 flops to create the grey code pattern of +// 00 -> 01 -> 11 -> 10 -> 00. The read counter is initialized +// to 00 and the write counter will be initialized to 11. This gives +// a basic 2 clock separation to compensate for the phase differences. +// The read counter is clocked off of the bufo clock + +always @ (posedge bufop_clk or posedge rst_bufop_rc) + + begin + if (rst_bufop_rc) + begin + qrdd <= # 10 2'b00; + end + else if (qrdd[1] ^ qrdd[0]) + begin + qrdd[1] <= # 10 ~qrdd[1]; + qrdd[0] <= # 10 qrdd[0]; + end + else + begin + qrdd[1] <= # 10 qrdd[1]; + qrdd[0] <= # 10 ~qrdd[0]; + end + end + + + +// Looking for 11 + +assign #1 qwcd0_latch = !(li01d & li03d); +assign #1 li01d = !(qwc[0] & bufop_clk); +assign #1 li02d = !(li01d & bufop_clk); +assign #1 li03d = !(qwcd0_latch & li02d); + + +assign #1 qwcd1_latch = !(li11d & li13d); +assign #1 li11d = !(qwc[1] & bufop_clk); +assign #1 li12d = !(li11d & bufop_clk); +assign #1 li13d = !(qwcd1_latch & li12d); + + + +// Circuit to fix read address counters in non data pins +always @ (posedge bufop_clk or posedge rst_bufo_rc) + + begin + if (rst_bufop_rc) + begin + stop_rd <= # 10 1'b0; + rd_cor_cnt <= #10 1'b0; + rd_cor_cnt1 <= #10 1'b0; + end + else if (((qwcd1_latch && qwcd0_latch) && (qrdd[0] ^ qrdd[1]) && !rd_cor_cnt1)) + begin + stop_rd <= #10 1'b1; + rd_cor_cnt <= #10 1'b1; + rd_cor_cnt1 <= #10 rd_cor_cnt; + end + else + begin + stop_rd <= #10 1'b0; + rd_cor_cnt <= #10 1'b1; + rd_cor_cnt1 <= #10 rd_cor_cnt; + end + end + +// Circuit to inform data if control counters habe been fixed + +always @ (posedge bufop_clk or posedge rst_bufop_rc) + begin + if (rst_bufop_rc) + begin + extra <= #10 1'b0; + end + else if (stop_rd) + begin + extra <= #10 1'b1; + end + end + +endmodule +`timescale 1ps/1ps +//////////////////////////////////////////////////////// +// +// module iodlyctrl_npre_oserdese1_vlog +// +//////////////////////////////////////////////////////// +// +// Circuit to automatically switch IODELAY from IDELAY to ODELAY using knowledge +// of write command. This circuit forces the user to wait 3 extra CLK/CLK# cycles +// when performing a read to write turnaround. The JEDEC DDR3 spec states that +// the turnaround can be done in 2 clock cycles. This circuit requires 5 clock +// cycles. +// This circuit is only used for a DDR3 appplication that uses DIMMs + + + +module iodlyctrl_npre_oserdese1_vlog (iodelay_state, bufo_out, rst_cntr, + wc, trif, + rst, bufg_clk, bufo_clk, bufg_clkdiv, + ddr3_dimm, wl6 + ); + + +input wc; + +input trif; + +input rst; + +input bufo_clk, bufg_clk, bufg_clkdiv; + +input ddr3_dimm, wl6; + +output iodelay_state, rst_cntr; + +output bufo_out; + + +reg qw0cd, qw1cd; + +reg turn, turn_p1; + +reg rst_cntr; + +reg w_to_w; + +reg [2:0] wtw_cntr; + +reg cmd0, cmd0_n6, cmd0_6, cmd1; + + + + +wire wr_cmd0; + +wire lt0int1, lt0int2, lt0int3; + +wire lt1int1, lt1int2, lt1int3; + +wire latch_in; + +reg qwcd; + + + + + +assign bufo_out = bufo_clk; + + +// create turn signal for IODELAY +assign iodelay_state = (trif && ~w_to_w) & ((~turn && ~turn_p1) || ~ddr3_dimm); + + + +// Registers to detect write command + +// Registers using bufg clkdiv +always @ (posedge bufg_clkdiv) +begin + if (rst) + begin + qwcd <= #10 0; + end + else + begin + qwcd <= #10 wc; + end +end + + + +// Latch to allow skew between CLK and CLKDIV from BUFGs +assign #1 wr_cmd0 = !(lt0int1 && lt0int3); +assign #1 lt0int1 = !(qwcd && bufg_clk); +assign #1 lt0int2 = !(lt0int1 && bufg_clk); +assign #1 lt0int3 = !(wr_cmd0 && lt0int2); + +always @ (posedge bufg_clk) + begin + if (rst) + begin + cmd0_n6 <= #10 1'b0; + cmd0_6 <= #10 1'b0; + end + else + begin + cmd0_n6 <= #10 wr_cmd0; + cmd0_6 <= #10 cmd0_n6; + end + end + + + +// mux to add extra pipe stage for WL = 6 +always @ (cmd0_n6 or wl6 or cmd0_6) + begin + case (wl6) + 1'b0: cmd0 <= #10 cmd0_n6; + 1'b1: cmd0 <= #10 cmd0_6; + default: cmd0 <= #10 cmd0_n6; + endcase + end + + +// Turn IODELAY and reset FIFO read/write counters +//always @ (posedge bufg_clk) +// begin +// if (rst) +// +// begin +// turn <= #10 1'b0; +// rst_cntr <= #10 1'b0; +// end +// else if (w_to_w) +// begin +// turn <= #10 1'b1; +// rst_cntr <= #10 1'b0; +// end +// else if (cmd0 && !turn) +// begin +// turn <= #10 1'b1; +// rst_cntr <= #10 1'b1; +// end +// else if (~trif) +// begin +// turn <= #10 1'b0; +// rst_cntr <= #10 1'b0; +// end +// else if (turn) +// begin +// turn <= #10 1'b1; +// rst_cntr <= #10 1'b0; +// end +// else +// begin +// turn <= #10 1'b0; +// rst_cntr <= #10 1'b0; +// end +// end + + + +always @ (posedge bufg_clk) +begin + begin + if (rst) + begin + turn <= #10 1'b0; + end + else + begin + turn <= #10 (w_to_w || (cmd0 && ~turn) || + (~wtw_cntr[2] && turn)); + end + + end + + begin + if (rst) + begin + rst_cntr <= #10 1'b0; + end + else + begin + rst_cntr <= #10 (~w_to_w && (cmd0 && ~turn)); + end + end +end + + + + +always @ (posedge bufg_clk) + begin + if (rst) + begin + turn_p1 <= #10 1'b0; + end + else + begin + turn_p1 <= #10 turn; + end + end + + + + +// Detect multiple write commands and don"t turn IODELAY +//always @ (posedge bufg_clk) +// begin +// if (rst) +// begin +// w_to_w <= #10 1'b0; +// wtw_cntr <= #10 3'b000; +// end +// else if (cmd0 && turn_p1) +// begin +// w_to_w <= #10 1'b1; +// wtw_cntr <= #10 3'b000; +// end +// else if (wtw_cntr == 3'b101) +// begin +// w_to_w <= #10 1'b0; +// wtw_cntr <= #10 3'b000; +// end +// else if (w_to_w) +// begin +// w_to_w <= #10 1'b1; +// wtw_cntr <= #10 wtw_cntr + 1; +// end +// end + + +always @ (posedge bufg_clk) +begin + begin + if (rst) + begin + w_to_w <= #10 1'b0; + end + else + begin + w_to_w <= #10 ((cmd0 && turn_p1) || + (w_to_w && (~wtw_cntr[2] || ~wtw_cntr[1]))); + end + end +end + + +always @ (posedge bufg_clk) + + begin + if (!(w_to_w || turn) || (cmd0 && turn_p1)) + begin + wtw_cntr <= #10 3'b000; + end + else if (w_to_w || turn_p1) + begin + wtw_cntr <= #10 wtw_cntr + 1; + end + end + +endmodule +`timescale 1ps/1ps +//////////////////////////////////////////////////////// +// +// MODULE dout_oserdese1_vlog +// +// This model ONLY works for SERDES operation!! +// Does not include tristate circuit +// +///////////////////////////////////////////////////////// +// +// Inputs: +// data1: Data from FIFO +// data2: Data input FIFO +// CLK: High speed clock from DCM +// BUFO: Clock from performance path +// OCE: Clock enable for output data flops +// SR: Set/Reset control. For the last 3 flops in OQ +// (d1rnk2, d2rnk2 and d2nrnk2) this function is +// controlled bythe attributes SRVAL_OQ. In SERDES mode, +// SR is a RESET ONLY for all other flops! The flops will +// still be RESET even if SR is programmed to a SET! +// +// +// +// Outputs: +// OQ: Data output +// +// +// +// Programmable Points +// DATA_RATE_OQ: Rate control for data output, 1-bit +// sdr (1), ddr (0) +// INIT_OQ: Init OQ output "flop" +// SRVAL_OQ: This bit to controls value of SR input. +// Only the last 3 flops (d1rnk2, d2rnk2 and d2nrnk2) +// are affected by this bit.For SERDES mode, this bit +// should be set to '0' making SR a reset. This is the +// desired state since all other flops only respond to +// this pin as a reset. Their function cannot be +// changed. SR is '1' for SET and '0' for RESET. +// +// +// +// Programmable points for Test model +// SRTYPE: This is a 4-bit field Sets asynchronous (0) or synchronous (1) set/reset +// 1st bit (msb) sets rank1 flops, 2nd bit sets 4 flops in rank 2, +// 3rd bit sets "3 legacy flops, and 4th (lsb) bit sets the counter +// DDR_CLK_EDGE: Controls use of 2 or 3 flops for single case. Default to 1 for +// SERDES operation +// +// +/////////////////////////////////////////////////////////////////////////////// +// + +module dout_oserdese1_vlog (data1, data2, + CLK, BUFO, SR, OCE, + OQ, d2rnk2, + DATA_RATE_OQ, + INIT_OQ, SRVAL_OQ, + DDR3_MODE); + +input data1, data2; + +input CLK, SR, OCE; + +input BUFO; + +input INIT_OQ, SRVAL_OQ; + +input DDR3_MODE; + +output OQ; + +output d2rnk2; + + +// Programmable Points + +input DATA_RATE_OQ; + +wire DDR_CLK_EDGE; +wire [3:0] SRTYPE; +assign DDR_CLK_EDGE = 1'b1; +assign SRTYPE = 4'b1111; +reg d1rnk2, d2rnk2, d2nrnk2; + +reg OQ; + +reg ddr_data, odata_edge, sdata_edge; + +reg c23, c45, c67; + +wire C; + +wire C2p, C3; + +wire [3:0] seloq; + +wire oqsr, oqrev; + +assign C = (BUFO & DDR3_MODE) | (CLK & !DDR3_MODE); + +assign C2p = (C & DDR_CLK_EDGE) | (!C & !DDR_CLK_EDGE); + +assign C3 = !C2p; + +assign seloq = {OCE,DATA_RATE_OQ,oqsr,oqrev}; + +assign oqsr = !SRTYPE[1] & SR & !SRVAL_OQ; + +assign oqrev = !SRTYPE[1] & SR & SRVAL_OQ; + + + +////////////////////////////////////////////////// +// Delay values +// +parameter FFD = 1; // clock to out delay for flip flops +// driven by clk +parameter FFCD = 1; // clock to out delay for flip flops +// driven by clkdiv +parameter MXD = 1; // 60 ps mux delay + +parameter MXR1 = 1; + +//////////////////////////////////////////// +// Initialization of flops with GSR for test model +/////////////////////////////////////////// + +tri0 GSR = glbl.GSR; + +always @(GSR) +begin + if (GSR) + begin + assign OQ = INIT_OQ; + assign d1rnk2 = INIT_OQ; + assign d2rnk2 = INIT_OQ; + assign d2nrnk2 = INIT_OQ; + end + else + begin + deassign OQ; + deassign d1rnk2; + deassign d2rnk2; + deassign d2nrnk2; + end +end + +///////////////////////////////////////// + + + + + + +///////////////////////////////////////// +// 3 flops to create DDR operations of 4 latches +//////////////////////////////////////// + +// Representation of top latch +// asynchronous operation +always @ (posedge C or posedge SR) +begin + begin + if (SR & !SRVAL_OQ & !SRTYPE[1]) + begin + d1rnk2 <= # FFD 1'b0; + end + else if (SR & SRVAL_OQ & !SRTYPE[1]) + begin + d1rnk2 <= # FFD 1'b1; + end + else if (!OCE & !SRTYPE[1]) + begin + d1rnk2 <= # FFD OQ; + end + else if (!SRTYPE[1]) + begin + d1rnk2 <= # FFD data1; + end + end +end + +// synchronous operation +always @ (posedge C) +begin + begin + + if (SR & !SRVAL_OQ & SRTYPE[1]) + begin + d1rnk2 <= # FFD 1'b0; + end + else if (SR & SRVAL_OQ & SRTYPE[1]) + begin + d1rnk2 <= # FFD 1'b1; + end + else if (!OCE & SRTYPE[1]) + begin + d1rnk2 <= # FFD OQ; + end + else if (SRTYPE[1]) + begin + d1rnk2 <= # FFD data1; + end + end +end + + + + +// Representation of 2nd latch +// asynchronous operation +always @ (posedge C2p or posedge SR) +begin + begin + if (SR & !SRVAL_OQ & !SRTYPE[1]) + begin + d2rnk2 <= # FFD 1'b0; + end + else if (SR & SRVAL_OQ & !SRTYPE[1]) + begin + d2rnk2 <= # FFD 1'b1; + end + else if (!OCE & !SRTYPE[1]) + begin + d2rnk2 <= # FFD OQ; + end + else if (!SRTYPE[1]) + begin + d2rnk2 <= # FFD data2; + end + end +end + +// synchronous operation +always @ (posedge C2p) +begin + begin + + if (SR & !SRVAL_OQ & SRTYPE[1]) + begin + d2rnk2 <= # FFD 1'b0; + end + else if (SR & SRVAL_OQ & SRTYPE[1]) + begin + d2rnk2 <= # FFD 1'b1; + end + else if (!OCE & SRTYPE[1]) + begin + d2rnk2 <= # FFD OQ; + end + else if (SRTYPE[1]) + begin + d2rnk2 <= # FFD data2; + end + end +end + + + + +// Representation of 3rd flop ( latch and output latch) +// asynchronous operation +always @ (posedge C3 or posedge SR) +begin + begin + if (SR & !SRVAL_OQ & !SRTYPE[1]) + begin + d2nrnk2 <= # FFD 1'b0; + end + else if (SR & SRVAL_OQ & !SRTYPE[1]) + begin + d2nrnk2 <= # FFD 1'b1; + end + else if (!OCE & !SRTYPE[1]) + begin + d2nrnk2 <= # FFD OQ; + end + else if (!SRTYPE[1]) + begin + d2nrnk2 <= # FFD d2rnk2; + end + end +end + +// synchronous operation +always @ (posedge C3) +begin + + begin + if (SR & !SRVAL_OQ & SRTYPE[1]) + begin + d2nrnk2 <= # FFD 1'b0; + end + else if (SR & SRVAL_OQ & SRTYPE[1]) + begin + d2nrnk2 <= # FFD 1'b1; + end + else if (!OCE & SRTYPE[1]) + begin + d2nrnk2 <= # FFD OQ; + end + else if (SRTYPE[1]) + begin + d2nrnk2 <= # FFD d2rnk2; + end + end +end + + +// Logic to generate same edge data from d1rnk2 and d2nrnk2; +always @ (C or C3 or d1rnk2 or d2nrnk2) + begin + sdata_edge <= # MXD (d1rnk2 & C) | (d2nrnk2 & C3); + end + +// Mux to create opposite edge DDR data from d1rnk2 and d2rnk2 +always @ (C or d1rnk2 or d2rnk2) + begin + case (C) + 1'b0: odata_edge <= # MXD d2rnk2; + 1'b1: odata_edge <= # MXD d1rnk2; + default: odata_edge <= # MXD d1rnk2; + endcase + end + +// Logic to same edge and opposite data into just ddr data +always @ (ddr_data or sdata_edge or odata_edge or DDR_CLK_EDGE) + begin + ddr_data <= # MXD (odata_edge & !DDR_CLK_EDGE) | (sdata_edge & DDR_CLK_EDGE); + end + + +// Output mux to generate OQ +always @ (seloq or d1rnk2 or ddr_data or OQ) + begin + casex (seloq) + 4'bXX01: OQ <= # MXD 1'b1; + 4'bXX10: OQ <= # MXD 1'b0; + 4'bXX11: OQ <= # MXD 1'b0; + 4'bX000: OQ <= # MXD ddr_data; + 4'bX100: OQ <= # MXD d1rnk2; + default: OQ <= # MXD ddr_data; + endcase + end + + +endmodule +`timescale 1ps/1ps +////////////////////////////////////////////////////////// +// +// module tout_oserdese1_vlog +// +// Tristate Output cell for Mt Blanc +// +// +//////////////////////////////////////////////////////// +// +// +// +///////////////////////////////////////////////////////// +// +// Inputs: +// +// data1, data2: tristate inputs +// TCE: Tristate clock enable +// SR: Set/Reset control. For the last 3 flops in TQ +// (qt1, qt2 and qt2n) this function is +// controlled bythe attributes SRVAL_TQ. In SERDES mode, +// SR is a RESET ONLY for all other flops! The flops will +// still be RESET even if SR is programmed to a SET! +// CLK: High speed clocks +// C2 drives 2nd latch and C3 (inverse of C2) drives +// 3rd latch in output section +// BUFO: Performance path clock +// +// +// +// +// Outputs: +// +// TQ: Output of tristate mux +// +// +// Programmable Options: +// +// DATA_RATE_TQ: 2-bit field for types of operaiton +// 0 (buf from T1), 1 (registered output from T1), 2 (ddr) +// TRISTATE_WIDTH: 2-bit field for input width +// 0 (width 1), 1 (width 2), 2 (width 4) +// INIT_TQ: Init TQ output (0,1) +// SRVAL_TQ: This bit to controls value of SR input. +// Only the last 3 flops (qt1, qt2 and qt2n) are +// affected by this bit.For SERDES mode, this bit +// should be set to '0' making SR a reset. This is the +// desired state since all other flops only +// respond to this pin as a reset. Their function +// cannot be changed. SR is 'O' for SET and '1' for RESET. +// +// +// Programmable Test Options: +// SRTYPE: Control S and R as asynchronous (0) or synchronous (1) +// 2-bit value. 1st bit (msb) controls the 4 input flops +// and the 2nd bit (lsb) controls the "3 legacy flops" +// DDR_CLK_EDGE: Same or opposite edge operation +// +// +// +//////////////////////////////////////////////////////////////////////////////// +// + +module tout_oserdese1_vlog (data1, data2, + CLK, BUFO, SR, TCE, + DATA_RATE_TQ, TRISTATE_WIDTH, + INIT_TQ, SRVAL_TQ, + TQ, DDR3_MODE); + +input data1, data2; + +input CLK, BUFO, SR, TCE; + +input [1:0] DATA_RATE_TQ, TRISTATE_WIDTH; + +input INIT_TQ, SRVAL_TQ; + +input DDR3_MODE; + +output TQ; + +wire DDR_CLK_EDGE; +wire [1:0] SRTYPE; +assign SRTYPE = 2'b11; +assign DDR_CLK_EDGE = 1'b1; + +reg TQ; + +reg t1r, t2r, t3r, t4r; + +reg qt1, qt2, qt2n; + +reg sdata_edge, odata_edge, ddr_data; + +wire C; + +wire C2p, C3; + +wire load; + +wire [5:0] tqsel; + +wire tqsr, tqrev; + +wire [4:0] sel; + +assign C = (BUFO & DDR3_MODE) | (CLK & !DDR3_MODE); + +assign C2p = (C & DDR_CLK_EDGE) | (!C & !DDR_CLK_EDGE); + +assign C3 = !C2p; + +assign tqsr = (!SRTYPE[0] & SR & !SRVAL_TQ) | (!SRTYPE[0] & SRVAL_TQ); + +assign tqrev = (!SRTYPE[0] & SR & SRVAL_TQ) | (!SRTYPE[0] & !SRVAL_TQ); + +assign tqsel = {TCE,DATA_RATE_TQ,TRISTATE_WIDTH,tqsr}; + + + + + +////////////////////////////////////////////////// + + +// Parameters for gate delays +parameter ffd = 1; +parameter mxd = 1; + + +///////////////////////////// +// Initialization of Flops +//////////////////////////// + +tri0 GSR = glbl.GSR; + +always @(GSR) +begin + if (GSR) + begin + assign TQ = INIT_TQ; + assign qt1 = INIT_TQ; + assign qt2 = INIT_TQ; + assign qt2n = INIT_TQ; + end + else + begin + deassign TQ; + deassign qt1; + deassign qt2; + deassign qt2n; + end +end + + + +///////////////////////////////////////// +// 3 flops to create DDR operations of 4 latches +//////////////////////////////////////// + +// Representation of top latch +// asynchronous operation +always @ (posedge C or posedge SR) +begin + begin + if (SR & !SRVAL_TQ & !SRTYPE[0]) + begin + qt1 <= # ffd 1'b0; + end + else if (SR & SRVAL_TQ & !SRTYPE[0]) + begin + qt1 <= # ffd 1'b1; + end + else if (!TCE & !SRTYPE[0]) + begin + qt1 <= # ffd TQ; + end + else if (!SRTYPE[0]) + begin + qt1 <= # ffd data1; + end + end +end + +// synchronous operation +always @ (posedge C) +begin + begin + + if (SR & !SRVAL_TQ & SRTYPE[0]) + begin + qt1 <= # ffd 1'b0; + end + else if (SR & SRVAL_TQ & SRTYPE[0]) + begin + qt1 <= # ffd 1'b1; + end + else if (!TCE & SRTYPE[0]) + begin + qt1 <= # ffd TQ; + end + else if (SRTYPE[0]) + begin + qt1 <= # ffd data1; + end + end +end + + + + +// Representation of 2nd latch +// asynchronous operation +always @ (posedge C2p or posedge SR) +begin + begin + if (SR & !SRVAL_TQ & !SRTYPE[0]) + begin + qt2 <= # ffd 1'b0; + end + else if (SR & SRVAL_TQ & !SRTYPE[0]) + begin + qt2 <= # ffd 1'b1; + end + else if (!TCE & !SRTYPE[0]) + begin + qt2 <= # ffd TQ; + end + else if (!SRTYPE[0]) + begin + qt2 <= # ffd data2; + end + end +end + +// synchronous operation +always @ (posedge C2p) +begin + begin + if (SR & !SRVAL_TQ & SRTYPE[0]) + begin + qt2 <= # ffd 1'b0; + end + else if (SR & SRVAL_TQ & SRTYPE[0]) + begin + qt2 <= # ffd 1'b1; + end + else if (!TCE & SRTYPE[0]) + begin + qt2 <= # ffd TQ; + end + else if (SRTYPE[0]) + begin + qt2 <= # ffd data2; + end + end +end + + + + +// Representation of 3rd flop ( latch and output latch) +// asynchronous operation +always @ (posedge C3 or posedge SR) +begin + begin + if (SR & !SRVAL_TQ & !SRTYPE[0]) + begin + qt2n <= # ffd 1'b0; + end + else if (SR & SRVAL_TQ & !SRTYPE[0]) + begin + qt2n <= # ffd 1'b1; + end + else if (!TCE & !SRTYPE[0]) + begin + qt2n <= # ffd TQ; + end + else if (!SRTYPE[0]) + begin + qt2n <= # ffd qt2; + end + end +end + +// synchronous operation +always @ (posedge C3) +begin + + begin + if (SR & !SRVAL_TQ & SRTYPE[0]) + begin + qt2n <= # ffd 1'b0; + end + else if (SR & SRVAL_TQ & SRTYPE[0]) + begin + qt2n <= # ffd 1'b1; + end + else if (!TCE & SRTYPE[0]) + begin + qt2n <= # ffd TQ; + end + else if (SRTYPE[0]) + begin + qt2n <= # ffd qt2; + end + end +end + + +// Logic to generate same edge data from qt1, qt3; +always @ (C or C3 or qt1 or qt2n) + begin + sdata_edge <= # mxd (qt1 & C) | (qt2n & C3); + end + +// Mux to create opposite edge DDR function +always @ (C or qt1 or qt2) + begin + case (C) + 1'b0: odata_edge <= # mxd qt2; + 1'b1: odata_edge <= # mxd qt1; + default: odata_edge <= 1'b0; + endcase + end + +// Logic to same edge and opposite data into just ddr data +always @ (ddr_data or sdata_edge or odata_edge or DDR_CLK_EDGE) + begin + ddr_data <= # mxd (odata_edge & !DDR_CLK_EDGE) | (sdata_edge & DDR_CLK_EDGE); + end + +// Output mux to generate TQ +// Note that the TQ mux can also support T2 combinatorial or +// registered outputs. +always @ (tqsel or data1 or ddr_data or qt1 or TQ) + begin + casex (tqsel) + 6'bX01XX1: TQ <= # mxd 1'b0; + 6'bX10XX1: TQ <= # mxd 1'b0; + 6'bX01XX1: TQ <= # mxd 1'b0; + 6'bX10XX1: TQ <= # mxd 1'b0; + 6'bX0000X: TQ <= # mxd data1; + // 6'b001000: TQ <= # mxd TQ; + // 6'b010010: TQ <= # mxd TQ; + // 6'b010100: TQ <= # mxd TQ; + 6'bX01000: TQ <= # mxd qt1; + 6'bX10010: TQ <= # mxd ddr_data; + 6'bX10100: TQ <= # mxd ddr_data; + default: TQ <= # mxd ddr_data; + endcase + end + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/PCIE_2_0.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/PCIE_2_0.v new file mode 100644 index 0000000..fd148bc --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/PCIE_2_0.v @@ -0,0 +1,4514 @@ +/////////////////////////////////////////////////////// +// Copyright (c) 2009 Xilinx Inc. +// All Right Reserved. +/////////////////////////////////////////////////////// +// +// ____ ___ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / +// /__/ /\ Filename : PCIE_2_0.v +// \ \ / \ +// \__\/\__ \ +// +// Revision: 1.0 +// 05/30/08 - CR - Initial version +// 06/18/08 - CR - removed PIPETXSWING, added PLSELLNKWIDTH. +// 07/23/08 - CR1014 - CFGLINKCONTROLRCB typo updated in yml +// 08/29/08 - CR1014 - Added assign statements, instantiation +// 09/16/08 - CR1014 - Added specify block +// 09/23/08 - CR490337 - assign buffer updates _delay to delay_ +// - specify block updates to bit & buses +// 10/13/08 - CR492333 - PCIE_2_0 yml parameter updates +// 10/13/08 - CR492334 - update PCIE_2_0_INST to B_PCIE_2_0_INST +// 11/04/08 - CR493971 - SIM_VERSION real to string +// 11/05/08 - CR495046 - replace case with if for parameter type integer - writer enhancement +// 01/27/09 - CR505569 - Writer update +// 02/18/09 - CR509025 - New pins & timing paths added +// 03/11/09 - CR511750 - Update attribute value to upper case +// 04/13/09 - CR518461 - Connect 4 new pins LNKCLKEN, CFGPMCSR* to RTL +// 05/05/09 - CR520519 - Update specify block from 100ps to 0ps +/////////////////////////////////////////////////////// + +`timescale 1 ps / 1 ps + +module PCIE_2_0 ( + CFGAERECRCCHECKEN, + CFGAERECRCGENEN, + CFGCOMMANDBUSMASTERENABLE, + CFGCOMMANDINTERRUPTDISABLE, + CFGCOMMANDIOENABLE, + CFGCOMMANDMEMENABLE, + CFGCOMMANDSERREN, + CFGDEVCONTROL2CPLTIMEOUTDIS, + CFGDEVCONTROL2CPLTIMEOUTVAL, + CFGDEVCONTROLAUXPOWEREN, + CFGDEVCONTROLCORRERRREPORTINGEN, + CFGDEVCONTROLENABLERO, + CFGDEVCONTROLEXTTAGEN, + CFGDEVCONTROLFATALERRREPORTINGEN, + CFGDEVCONTROLMAXPAYLOAD, + CFGDEVCONTROLMAXREADREQ, + CFGDEVCONTROLNONFATALREPORTINGEN, + CFGDEVCONTROLNOSNOOPEN, + CFGDEVCONTROLPHANTOMEN, + CFGDEVCONTROLURERRREPORTINGEN, + CFGDEVSTATUSCORRERRDETECTED, + CFGDEVSTATUSFATALERRDETECTED, + CFGDEVSTATUSNONFATALERRDETECTED, + CFGDEVSTATUSURDETECTED, + CFGDO, + CFGERRAERHEADERLOGSETN, + CFGERRCPLRDYN, + CFGINTERRUPTDO, + CFGINTERRUPTMMENABLE, + CFGINTERRUPTMSIENABLE, + CFGINTERRUPTMSIXENABLE, + CFGINTERRUPTMSIXFM, + CFGINTERRUPTRDYN, + CFGLINKCONTROLASPMCONTROL, + CFGLINKCONTROLAUTOBANDWIDTHINTEN, + CFGLINKCONTROLBANDWIDTHINTEN, + CFGLINKCONTROLCLOCKPMEN, + CFGLINKCONTROLCOMMONCLOCK, + CFGLINKCONTROLEXTENDEDSYNC, + CFGLINKCONTROLHWAUTOWIDTHDIS, + CFGLINKCONTROLLINKDISABLE, + CFGLINKCONTROLRCB, + CFGLINKCONTROLRETRAINLINK, + CFGLINKSTATUSAUTOBANDWIDTHSTATUS, + CFGLINKSTATUSBANDWITHSTATUS, + CFGLINKSTATUSCURRENTSPEED, + CFGLINKSTATUSDLLACTIVE, + CFGLINKSTATUSLINKTRAINING, + CFGLINKSTATUSNEGOTIATEDWIDTH, + CFGMSGDATA, + CFGMSGRECEIVED, + CFGMSGRECEIVEDASSERTINTA, + CFGMSGRECEIVEDASSERTINTB, + CFGMSGRECEIVEDASSERTINTC, + CFGMSGRECEIVEDASSERTINTD, + CFGMSGRECEIVEDDEASSERTINTA, + CFGMSGRECEIVEDDEASSERTINTB, + CFGMSGRECEIVEDDEASSERTINTC, + CFGMSGRECEIVEDDEASSERTINTD, + CFGMSGRECEIVEDERRCOR, + CFGMSGRECEIVEDERRFATAL, + CFGMSGRECEIVEDERRNONFATAL, + CFGMSGRECEIVEDPMASNAK, + CFGMSGRECEIVEDPMETO, + CFGMSGRECEIVEDPMETOACK, + CFGMSGRECEIVEDPMPME, + CFGMSGRECEIVEDSETSLOTPOWERLIMIT, + CFGMSGRECEIVEDUNLOCK, + CFGPCIELINKSTATE, + CFGPMCSRPMEEN, + CFGPMCSRPMESTATUS, + CFGPMCSRPOWERSTATE, + CFGPMRCVASREQL1N, + CFGPMRCVENTERL1N, + CFGPMRCVENTERL23N, + CFGPMRCVREQACKN, + CFGRDWRDONEN, + CFGSLOTCONTROLELECTROMECHILCTLPULSE, + CFGTRANSACTION, + CFGTRANSACTIONADDR, + CFGTRANSACTIONTYPE, + CFGVCTCVCMAP, + DBGSCLRA, + DBGSCLRB, + DBGSCLRC, + DBGSCLRD, + DBGSCLRE, + DBGSCLRF, + DBGSCLRG, + DBGSCLRH, + DBGSCLRI, + DBGSCLRJ, + DBGSCLRK, + DBGVECA, + DBGVECB, + DBGVECC, + DRPDO, + DRPDRDY, + LL2BADDLLPERRN, + LL2BADTLPERRN, + LL2PROTOCOLERRN, + LL2REPLAYROERRN, + LL2REPLAYTOERRN, + LL2SUSPENDOKN, + LL2TFCINIT1SEQN, + LL2TFCINIT2SEQN, + LNKCLKEN, + MIMRXRADDR, + MIMRXRCE, + MIMRXREN, + MIMRXWADDR, + MIMRXWDATA, + MIMRXWEN, + MIMTXRADDR, + MIMTXRCE, + MIMTXREN, + MIMTXWADDR, + MIMTXWDATA, + MIMTXWEN, + PIPERX0POLARITY, + PIPERX1POLARITY, + PIPERX2POLARITY, + PIPERX3POLARITY, + PIPERX4POLARITY, + PIPERX5POLARITY, + PIPERX6POLARITY, + PIPERX7POLARITY, + PIPETX0CHARISK, + PIPETX0COMPLIANCE, + PIPETX0DATA, + PIPETX0ELECIDLE, + PIPETX0POWERDOWN, + PIPETX1CHARISK, + PIPETX1COMPLIANCE, + PIPETX1DATA, + PIPETX1ELECIDLE, + PIPETX1POWERDOWN, + PIPETX2CHARISK, + PIPETX2COMPLIANCE, + PIPETX2DATA, + PIPETX2ELECIDLE, + PIPETX2POWERDOWN, + PIPETX3CHARISK, + PIPETX3COMPLIANCE, + PIPETX3DATA, + PIPETX3ELECIDLE, + PIPETX3POWERDOWN, + PIPETX4CHARISK, + PIPETX4COMPLIANCE, + PIPETX4DATA, + PIPETX4ELECIDLE, + PIPETX4POWERDOWN, + PIPETX5CHARISK, + PIPETX5COMPLIANCE, + PIPETX5DATA, + PIPETX5ELECIDLE, + PIPETX5POWERDOWN, + PIPETX6CHARISK, + PIPETX6COMPLIANCE, + PIPETX6DATA, + PIPETX6ELECIDLE, + PIPETX6POWERDOWN, + PIPETX7CHARISK, + PIPETX7COMPLIANCE, + PIPETX7DATA, + PIPETX7ELECIDLE, + PIPETX7POWERDOWN, + PIPETXDEEMPH, + PIPETXMARGIN, + PIPETXRATE, + PIPETXRCVRDET, + PIPETXRESET, + PL2LINKUPN, + PL2RECEIVERERRN, + PL2RECOVERYN, + PL2RXELECIDLE, + PL2SUSPENDOK, + PLDBGVEC, + PLINITIALLINKWIDTH, + PLLANEREVERSALMODE, + PLLINKGEN2CAP, + PLLINKPARTNERGEN2SUPPORTED, + PLLINKUPCFGCAP, + PLLTSSMSTATE, + PLPHYLNKUPN, + PLRECEIVEDHOTRST, + PLRXPMSTATE, + PLSELLNKRATE, + PLSELLNKWIDTH, + PLTXPMSTATE, + RECEIVEDFUNCLVLRSTN, + TL2ASPMSUSPENDCREDITCHECKOKN, + TL2ASPMSUSPENDREQN, + TL2PPMSUSPENDOKN, + TRNFCCPLD, + TRNFCCPLH, + TRNFCNPD, + TRNFCNPH, + TRNFCPD, + TRNFCPH, + TRNLNKUPN, + TRNRBARHITN, + TRNRD, + TRNRDLLPDATA, + TRNRDLLPSRCRDYN, + TRNRECRCERRN, + TRNREOFN, + TRNRERRFWDN, + TRNRREMN, + TRNRSOFN, + TRNRSRCDSCN, + TRNRSRCRDYN, + TRNTBUFAV, + TRNTCFGREQN, + TRNTDLLPDSTRDYN, + TRNTDSTRDYN, + TRNTERRDROPN, + USERRSTN, + CFGBYTEENN, + CFGDI, + CFGDSBUSNUMBER, + CFGDSDEVICENUMBER, + CFGDSFUNCTIONNUMBER, + CFGDSN, + CFGDWADDR, + CFGERRACSN, + CFGERRAERHEADERLOG, + CFGERRCORN, + CFGERRCPLABORTN, + CFGERRCPLTIMEOUTN, + CFGERRCPLUNEXPECTN, + CFGERRECRCN, + CFGERRLOCKEDN, + CFGERRPOSTEDN, + CFGERRTLPCPLHEADER, + CFGERRURN, + CFGINTERRUPTASSERTN, + CFGINTERRUPTDI, + CFGINTERRUPTN, + CFGPMDIRECTASPML1N, + CFGPMSENDPMACKN, + CFGPMSENDPMETON, + CFGPMSENDPMNAKN, + CFGPMTURNOFFOKN, + CFGPMWAKEN, + CFGPORTNUMBER, + CFGRDENN, + CFGTRNPENDINGN, + CFGWRENN, + CFGWRREADONLYN, + CFGWRRW1CASRWN, + CMRSTN, + CMSTICKYRSTN, + DBGMODE, + DBGSUBMODE, + DLRSTN, + DRPCLK, + DRPDADDR, + DRPDEN, + DRPDI, + DRPDWE, + FUNCLVLRSTN, + LL2SENDASREQL1N, + LL2SENDENTERL1N, + LL2SENDENTERL23N, + LL2SUSPENDNOWN, + LL2TLPRCVN, + MIMRXRDATA, + MIMTXRDATA, + PIPECLK, + PIPERX0CHANISALIGNED, + PIPERX0CHARISK, + PIPERX0DATA, + PIPERX0ELECIDLE, + PIPERX0PHYSTATUS, + PIPERX0STATUS, + PIPERX0VALID, + PIPERX1CHANISALIGNED, + PIPERX1CHARISK, + PIPERX1DATA, + PIPERX1ELECIDLE, + PIPERX1PHYSTATUS, + PIPERX1STATUS, + PIPERX1VALID, + PIPERX2CHANISALIGNED, + PIPERX2CHARISK, + PIPERX2DATA, + PIPERX2ELECIDLE, + PIPERX2PHYSTATUS, + PIPERX2STATUS, + PIPERX2VALID, + PIPERX3CHANISALIGNED, + PIPERX3CHARISK, + PIPERX3DATA, + PIPERX3ELECIDLE, + PIPERX3PHYSTATUS, + PIPERX3STATUS, + PIPERX3VALID, + PIPERX4CHANISALIGNED, + PIPERX4CHARISK, + PIPERX4DATA, + PIPERX4ELECIDLE, + PIPERX4PHYSTATUS, + PIPERX4STATUS, + PIPERX4VALID, + PIPERX5CHANISALIGNED, + PIPERX5CHARISK, + PIPERX5DATA, + PIPERX5ELECIDLE, + PIPERX5PHYSTATUS, + PIPERX5STATUS, + PIPERX5VALID, + PIPERX6CHANISALIGNED, + PIPERX6CHARISK, + PIPERX6DATA, + PIPERX6ELECIDLE, + PIPERX6PHYSTATUS, + PIPERX6STATUS, + PIPERX6VALID, + PIPERX7CHANISALIGNED, + PIPERX7CHARISK, + PIPERX7DATA, + PIPERX7ELECIDLE, + PIPERX7PHYSTATUS, + PIPERX7STATUS, + PIPERX7VALID, + PL2DIRECTEDLSTATE, + PLDBGMODE, + PLDIRECTEDLINKAUTON, + PLDIRECTEDLINKCHANGE, + PLDIRECTEDLINKSPEED, + PLDIRECTEDLINKWIDTH, + PLDOWNSTREAMDEEMPHSOURCE, + PLRSTN, + PLTRANSMITHOTRST, + PLUPSTREAMPREFERDEEMPH, + SYSRSTN, + TL2ASPMSUSPENDCREDITCHECKN, + TL2PPMSUSPENDREQN, + TLRSTN, + TRNFCSEL, + TRNRDSTRDYN, + TRNRNPOKN, + TRNTCFGGNTN, + TRNTD, + TRNTDLLPDATA, + TRNTDLLPSRCRDYN, + TRNTECRCGENN, + TRNTEOFN, + TRNTERRFWDN, + TRNTREMN, + TRNTSOFN, + TRNTSRCDSCN, + TRNTSRCRDYN, + TRNTSTRN, + USERCLK +); + parameter [11:0] AER_BASE_PTR = 12'h128; + parameter AER_CAP_ECRC_CHECK_CAPABLE = "FALSE"; + parameter AER_CAP_ECRC_GEN_CAPABLE = "FALSE"; + parameter [15:0] AER_CAP_ID = 16'h0001; + parameter [4:0] AER_CAP_INT_MSG_NUM_MSI = 5'h0A; + parameter [4:0] AER_CAP_INT_MSG_NUM_MSIX = 5'h15; + parameter [11:0] AER_CAP_NEXTPTR = 12'h160; + parameter AER_CAP_ON = "FALSE"; + parameter AER_CAP_PERMIT_ROOTERR_UPDATE = "TRUE"; + parameter [3:0] AER_CAP_VERSION = 4'h1; + parameter ALLOW_X8_GEN2 = "FALSE"; + parameter [31:0] BAR0 = 32'hFFFFFF00; + parameter [31:0] BAR1 = 32'hFFFF0000; + parameter [31:0] BAR2 = 32'hFFFF000C; + parameter [31:0] BAR3 = 32'hFFFFFFFF; + parameter [31:0] BAR4 = 32'h00000000; + parameter [31:0] BAR5 = 32'h00000000; + parameter [7:0] CAPABILITIES_PTR = 8'h40; + parameter [31:0] CARDBUS_CIS_POINTER = 32'h00000000; + parameter [23:0] CLASS_CODE = 24'h000000; + parameter CMD_INTX_IMPLEMENTED = "TRUE"; + parameter CPL_TIMEOUT_DISABLE_SUPPORTED = "FALSE"; + parameter [3:0] CPL_TIMEOUT_RANGES_SUPPORTED = 4'h0; + parameter [6:0] CRM_MODULE_RSTS = 7'h00; + parameter [15:0] DEVICE_ID = 16'h0007; + parameter DEV_CAP_ENABLE_SLOT_PWR_LIMIT_SCALE = "TRUE"; + parameter DEV_CAP_ENABLE_SLOT_PWR_LIMIT_VALUE = "TRUE"; + parameter integer DEV_CAP_ENDPOINT_L0S_LATENCY = 0; + parameter integer DEV_CAP_ENDPOINT_L1_LATENCY = 0; + parameter DEV_CAP_EXT_TAG_SUPPORTED = "TRUE"; + parameter DEV_CAP_FUNCTION_LEVEL_RESET_CAPABLE = "FALSE"; + parameter integer DEV_CAP_MAX_PAYLOAD_SUPPORTED = 2; + parameter integer DEV_CAP_PHANTOM_FUNCTIONS_SUPPORT = 0; + parameter DEV_CAP_ROLE_BASED_ERROR = "TRUE"; + parameter integer DEV_CAP_RSVD_14_12 = 0; + parameter integer DEV_CAP_RSVD_17_16 = 0; + parameter integer DEV_CAP_RSVD_31_29 = 0; + parameter DEV_CONTROL_AUX_POWER_SUPPORTED = "FALSE"; + parameter DISABLE_ASPM_L1_TIMER = "FALSE"; + parameter DISABLE_BAR_FILTERING = "FALSE"; + parameter DISABLE_ID_CHECK = "FALSE"; + parameter DISABLE_LANE_REVERSAL = "FALSE"; + parameter DISABLE_RX_TC_FILTER = "FALSE"; + parameter DISABLE_SCRAMBLING = "FALSE"; + parameter [7:0] DNSTREAM_LINK_NUM = 8'h00; + parameter [11:0] DSN_BASE_PTR = 12'h100; + parameter [15:0] DSN_CAP_ID = 16'h0003; + parameter [11:0] DSN_CAP_NEXTPTR = 12'h000; + parameter DSN_CAP_ON = "TRUE"; + parameter [3:0] DSN_CAP_VERSION = 4'h1; + parameter [10:0] ENABLE_MSG_ROUTE = 11'h000; + parameter ENABLE_RX_TD_ECRC_TRIM = "FALSE"; + parameter ENTER_RVRY_EI_L0 = "TRUE"; + parameter EXIT_LOOPBACK_ON_EI = "TRUE"; + parameter [31:0] EXPANSION_ROM = 32'hFFFFF001; + parameter [5:0] EXT_CFG_CAP_PTR = 6'h3F; + parameter [9:0] EXT_CFG_XP_CAP_PTR = 10'h3FF; + parameter [7:0] HEADER_TYPE = 8'h00; + parameter [4:0] INFER_EI = 5'h00; + parameter [7:0] INTERRUPT_PIN = 8'h01; + parameter IS_SWITCH = "FALSE"; + parameter [9:0] LAST_CONFIG_DWORD = 10'h042; + parameter integer LINK_CAP_ASPM_SUPPORT = 1; + parameter LINK_CAP_CLOCK_POWER_MANAGEMENT = "FALSE"; + parameter LINK_CAP_DLL_LINK_ACTIVE_REPORTING_CAP = "FALSE"; + parameter integer LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN1 = 7; + parameter integer LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN2 = 7; + parameter integer LINK_CAP_L0S_EXIT_LATENCY_GEN1 = 7; + parameter integer LINK_CAP_L0S_EXIT_LATENCY_GEN2 = 7; + parameter integer LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN1 = 7; + parameter integer LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN2 = 7; + parameter integer LINK_CAP_L1_EXIT_LATENCY_GEN1 = 7; + parameter integer LINK_CAP_L1_EXIT_LATENCY_GEN2 = 7; + parameter LINK_CAP_LINK_BANDWIDTH_NOTIFICATION_CAP = "FALSE"; + parameter [3:0] LINK_CAP_MAX_LINK_SPEED = 4'h1; + parameter [5:0] LINK_CAP_MAX_LINK_WIDTH = 6'h08; + parameter integer LINK_CAP_RSVD_23_22 = 0; + parameter LINK_CAP_SURPRISE_DOWN_ERROR_CAPABLE = "FALSE"; + parameter integer LINK_CONTROL_RCB = 0; + parameter LINK_CTRL2_DEEMPHASIS = "FALSE"; + parameter LINK_CTRL2_HW_AUTONOMOUS_SPEED_DISABLE = "FALSE"; + parameter [3:0] LINK_CTRL2_TARGET_LINK_SPEED = 4'h2; + parameter LINK_STATUS_SLOT_CLOCK_CONFIG = "TRUE"; + parameter [14:0] LL_ACK_TIMEOUT = 15'h0000; + parameter LL_ACK_TIMEOUT_EN = "FALSE"; + parameter integer LL_ACK_TIMEOUT_FUNC = 0; + parameter [14:0] LL_REPLAY_TIMEOUT = 15'h0000; + parameter LL_REPLAY_TIMEOUT_EN = "FALSE"; + parameter integer LL_REPLAY_TIMEOUT_FUNC = 0; + parameter [5:0] LTSSM_MAX_LINK_WIDTH = 6'h01; + parameter [7:0] MSIX_BASE_PTR = 8'h9C; + parameter [7:0] MSIX_CAP_ID = 8'h11; + parameter [7:0] MSIX_CAP_NEXTPTR = 8'h00; + parameter MSIX_CAP_ON = "FALSE"; + parameter integer MSIX_CAP_PBA_BIR = 0; + parameter [28:0] MSIX_CAP_PBA_OFFSET = 29'h00000050; + parameter integer MSIX_CAP_TABLE_BIR = 0; + parameter [28:0] MSIX_CAP_TABLE_OFFSET = 29'h00000040; + parameter [10:0] MSIX_CAP_TABLE_SIZE = 11'h000; + parameter [7:0] MSI_BASE_PTR = 8'h48; + parameter MSI_CAP_64_BIT_ADDR_CAPABLE = "TRUE"; + parameter [7:0] MSI_CAP_ID = 8'h05; + parameter integer MSI_CAP_MULTIMSGCAP = 0; + parameter integer MSI_CAP_MULTIMSG_EXTENSION = 0; + parameter [7:0] MSI_CAP_NEXTPTR = 8'h60; + parameter MSI_CAP_ON = "FALSE"; + parameter MSI_CAP_PER_VECTOR_MASKING_CAPABLE = "TRUE"; + parameter integer N_FTS_COMCLK_GEN1 = 255; + parameter integer N_FTS_COMCLK_GEN2 = 255; + parameter integer N_FTS_GEN1 = 255; + parameter integer N_FTS_GEN2 = 255; + parameter [7:0] PCIE_BASE_PTR = 8'h60; + parameter [7:0] PCIE_CAP_CAPABILITY_ID = 8'h10; + parameter [3:0] PCIE_CAP_CAPABILITY_VERSION = 4'h2; + parameter [3:0] PCIE_CAP_DEVICE_PORT_TYPE = 4'h0; + parameter [4:0] PCIE_CAP_INT_MSG_NUM = 5'h00; + parameter [7:0] PCIE_CAP_NEXTPTR = 8'h00; + parameter PCIE_CAP_ON = "TRUE"; + parameter integer PCIE_CAP_RSVD_15_14 = 0; + parameter PCIE_CAP_SLOT_IMPLEMENTED = "FALSE"; + parameter integer PCIE_REVISION = 2; + parameter integer PGL0_LANE = 0; + parameter integer PGL1_LANE = 1; + parameter integer PGL2_LANE = 2; + parameter integer PGL3_LANE = 3; + parameter integer PGL4_LANE = 4; + parameter integer PGL5_LANE = 5; + parameter integer PGL6_LANE = 6; + parameter integer PGL7_LANE = 7; + parameter integer PL_AUTO_CONFIG = 0; + parameter PL_FAST_TRAIN = "FALSE"; + parameter [7:0] PM_BASE_PTR = 8'h40; + parameter integer PM_CAP_AUXCURRENT = 0; + parameter PM_CAP_D1SUPPORT = "TRUE"; + parameter PM_CAP_D2SUPPORT = "TRUE"; + parameter PM_CAP_DSI = "FALSE"; + parameter [7:0] PM_CAP_ID = 8'h01; + parameter [7:0] PM_CAP_NEXTPTR = 8'h48; + parameter PM_CAP_ON = "TRUE"; + parameter [4:0] PM_CAP_PMESUPPORT = 5'h0F; + parameter PM_CAP_PME_CLOCK = "FALSE"; + parameter integer PM_CAP_RSVD_04 = 0; + parameter integer PM_CAP_VERSION = 3; + parameter PM_CSR_B2B3 = "FALSE"; + parameter PM_CSR_BPCCEN = "FALSE"; + parameter PM_CSR_NOSOFTRST = "TRUE"; + parameter [7:0] PM_DATA0 = 8'h01; + parameter [7:0] PM_DATA1 = 8'h01; + parameter [7:0] PM_DATA2 = 8'h01; + parameter [7:0] PM_DATA3 = 8'h01; + parameter [7:0] PM_DATA4 = 8'h01; + parameter [7:0] PM_DATA5 = 8'h01; + parameter [7:0] PM_DATA6 = 8'h01; + parameter [7:0] PM_DATA7 = 8'h01; + parameter [1:0] PM_DATA_SCALE0 = 2'h1; + parameter [1:0] PM_DATA_SCALE1 = 2'h1; + parameter [1:0] PM_DATA_SCALE2 = 2'h1; + parameter [1:0] PM_DATA_SCALE3 = 2'h1; + parameter [1:0] PM_DATA_SCALE4 = 2'h1; + parameter [1:0] PM_DATA_SCALE5 = 2'h1; + parameter [1:0] PM_DATA_SCALE6 = 2'h1; + parameter [1:0] PM_DATA_SCALE7 = 2'h1; + parameter integer RECRC_CHK = 0; + parameter RECRC_CHK_TRIM = "FALSE"; + parameter [7:0] REVISION_ID = 8'h00; + parameter ROOT_CAP_CRS_SW_VISIBILITY = "FALSE"; + parameter SELECT_DLL_IF = "FALSE"; + parameter SIM_VERSION = "1.0"; + parameter SLOT_CAP_ATT_BUTTON_PRESENT = "FALSE"; + parameter SLOT_CAP_ATT_INDICATOR_PRESENT = "FALSE"; + parameter SLOT_CAP_ELEC_INTERLOCK_PRESENT = "FALSE"; + parameter SLOT_CAP_HOTPLUG_CAPABLE = "FALSE"; + parameter SLOT_CAP_HOTPLUG_SURPRISE = "FALSE"; + parameter SLOT_CAP_MRL_SENSOR_PRESENT = "FALSE"; + parameter SLOT_CAP_NO_CMD_COMPLETED_SUPPORT = "FALSE"; + parameter [12:0] SLOT_CAP_PHYSICAL_SLOT_NUM = 13'h0000; + parameter SLOT_CAP_POWER_CONTROLLER_PRESENT = "FALSE"; + parameter SLOT_CAP_POWER_INDICATOR_PRESENT = "FALSE"; + parameter integer SLOT_CAP_SLOT_POWER_LIMIT_SCALE = 0; + parameter [7:0] SLOT_CAP_SLOT_POWER_LIMIT_VALUE = 8'h00; + parameter integer SPARE_BIT0 = 0; + parameter integer SPARE_BIT1 = 0; + parameter integer SPARE_BIT2 = 0; + parameter integer SPARE_BIT3 = 0; + parameter integer SPARE_BIT4 = 0; + parameter integer SPARE_BIT5 = 0; + parameter integer SPARE_BIT6 = 0; + parameter integer SPARE_BIT7 = 0; + parameter integer SPARE_BIT8 = 0; + parameter [7:0] SPARE_BYTE0 = 8'h00; + parameter [7:0] SPARE_BYTE1 = 8'h00; + parameter [7:0] SPARE_BYTE2 = 8'h00; + parameter [7:0] SPARE_BYTE3 = 8'h00; + parameter [31:0] SPARE_WORD0 = 32'h00000000; + parameter [31:0] SPARE_WORD1 = 32'h00000000; + parameter [31:0] SPARE_WORD2 = 32'h00000000; + parameter [31:0] SPARE_WORD3 = 32'h00000000; + parameter [15:0] SUBSYSTEM_ID = 16'h0007; + parameter [15:0] SUBSYSTEM_VENDOR_ID = 16'h10EE; + parameter TL_RBYPASS = "FALSE"; + parameter integer TL_RX_RAM_RADDR_LATENCY = 0; + parameter integer TL_RX_RAM_RDATA_LATENCY = 2; + parameter integer TL_RX_RAM_WRITE_LATENCY = 0; + parameter TL_TFC_DISABLE = "FALSE"; + parameter TL_TX_CHECKS_DISABLE = "FALSE"; + parameter integer TL_TX_RAM_RADDR_LATENCY = 0; + parameter integer TL_TX_RAM_RDATA_LATENCY = 2; + parameter integer TL_TX_RAM_WRITE_LATENCY = 0; + parameter UPCONFIG_CAPABLE = "TRUE"; + parameter UPSTREAM_FACING = "TRUE"; + parameter UR_INV_REQ = "TRUE"; + parameter integer USER_CLK_FREQ = 3; + parameter VC0_CPL_INFINITE = "TRUE"; + parameter [12:0] VC0_RX_RAM_LIMIT = 13'h03FF; + parameter integer VC0_TOTAL_CREDITS_CD = 127; + parameter integer VC0_TOTAL_CREDITS_CH = 31; + parameter integer VC0_TOTAL_CREDITS_NPH = 12; + parameter integer VC0_TOTAL_CREDITS_PD = 288; + parameter integer VC0_TOTAL_CREDITS_PH = 32; + parameter integer VC0_TX_LASTPACKET = 31; + parameter [11:0] VC_BASE_PTR = 12'h10C; + parameter [15:0] VC_CAP_ID = 16'h0002; + parameter [11:0] VC_CAP_NEXTPTR = 12'h000; + parameter VC_CAP_ON = "FALSE"; + parameter VC_CAP_REJECT_SNOOP_TRANSACTIONS = "FALSE"; + parameter [3:0] VC_CAP_VERSION = 4'h1; + parameter [15:0] VENDOR_ID = 16'h10EE; + parameter [11:0] VSEC_BASE_PTR = 12'h160; + parameter [15:0] VSEC_CAP_HDR_ID = 16'h1234; + parameter [11:0] VSEC_CAP_HDR_LENGTH = 12'h018; + parameter [3:0] VSEC_CAP_HDR_REVISION = 4'h1; + parameter [15:0] VSEC_CAP_ID = 16'h000B; + parameter VSEC_CAP_IS_LINK_VISIBLE = "TRUE"; + parameter [11:0] VSEC_CAP_NEXTPTR = 12'h000; + parameter VSEC_CAP_ON = "FALSE"; + parameter [3:0] VSEC_CAP_VERSION = 4'h1; + + localparam in_delay = 0; + localparam out_delay = 0; + localparam INCLK_DELAY = 0; + localparam OUTCLK_DELAY = 0; + + output CFGAERECRCCHECKEN; + output CFGAERECRCGENEN; + output CFGCOMMANDBUSMASTERENABLE; + output CFGCOMMANDINTERRUPTDISABLE; + output CFGCOMMANDIOENABLE; + output CFGCOMMANDMEMENABLE; + output CFGCOMMANDSERREN; + output CFGDEVCONTROL2CPLTIMEOUTDIS; + output CFGDEVCONTROLAUXPOWEREN; + output CFGDEVCONTROLCORRERRREPORTINGEN; + output CFGDEVCONTROLENABLERO; + output CFGDEVCONTROLEXTTAGEN; + output CFGDEVCONTROLFATALERRREPORTINGEN; + output CFGDEVCONTROLNONFATALREPORTINGEN; + output CFGDEVCONTROLNOSNOOPEN; + output CFGDEVCONTROLPHANTOMEN; + output CFGDEVCONTROLURERRREPORTINGEN; + output CFGDEVSTATUSCORRERRDETECTED; + output CFGDEVSTATUSFATALERRDETECTED; + output CFGDEVSTATUSNONFATALERRDETECTED; + output CFGDEVSTATUSURDETECTED; + output CFGERRAERHEADERLOGSETN; + output CFGERRCPLRDYN; + output CFGINTERRUPTMSIENABLE; + output CFGINTERRUPTMSIXENABLE; + output CFGINTERRUPTMSIXFM; + output CFGINTERRUPTRDYN; + output CFGLINKCONTROLAUTOBANDWIDTHINTEN; + output CFGLINKCONTROLBANDWIDTHINTEN; + output CFGLINKCONTROLCLOCKPMEN; + output CFGLINKCONTROLCOMMONCLOCK; + output CFGLINKCONTROLEXTENDEDSYNC; + output CFGLINKCONTROLHWAUTOWIDTHDIS; + output CFGLINKCONTROLLINKDISABLE; + output CFGLINKCONTROLRCB; + output CFGLINKCONTROLRETRAINLINK; + output CFGLINKSTATUSAUTOBANDWIDTHSTATUS; + output CFGLINKSTATUSBANDWITHSTATUS; + output CFGLINKSTATUSDLLACTIVE; + output CFGLINKSTATUSLINKTRAINING; + output CFGMSGRECEIVED; + output CFGMSGRECEIVEDASSERTINTA; + output CFGMSGRECEIVEDASSERTINTB; + output CFGMSGRECEIVEDASSERTINTC; + output CFGMSGRECEIVEDASSERTINTD; + output CFGMSGRECEIVEDDEASSERTINTA; + output CFGMSGRECEIVEDDEASSERTINTB; + output CFGMSGRECEIVEDDEASSERTINTC; + output CFGMSGRECEIVEDDEASSERTINTD; + output CFGMSGRECEIVEDERRCOR; + output CFGMSGRECEIVEDERRFATAL; + output CFGMSGRECEIVEDERRNONFATAL; + output CFGMSGRECEIVEDPMASNAK; + output CFGMSGRECEIVEDPMETO; + output CFGMSGRECEIVEDPMETOACK; + output CFGMSGRECEIVEDPMPME; + output CFGMSGRECEIVEDSETSLOTPOWERLIMIT; + output CFGMSGRECEIVEDUNLOCK; + output CFGPMCSRPMEEN; + output CFGPMCSRPMESTATUS; + output CFGPMRCVASREQL1N; + output CFGPMRCVENTERL1N; + output CFGPMRCVENTERL23N; + output CFGPMRCVREQACKN; + output CFGRDWRDONEN; + output CFGSLOTCONTROLELECTROMECHILCTLPULSE; + output CFGTRANSACTION; + output CFGTRANSACTIONTYPE; + output DBGSCLRA; + output DBGSCLRB; + output DBGSCLRC; + output DBGSCLRD; + output DBGSCLRE; + output DBGSCLRF; + output DBGSCLRG; + output DBGSCLRH; + output DBGSCLRI; + output DBGSCLRJ; + output DBGSCLRK; + output DRPDRDY; + output LL2BADDLLPERRN; + output LL2BADTLPERRN; + output LL2PROTOCOLERRN; + output LL2REPLAYROERRN; + output LL2REPLAYTOERRN; + output LL2SUSPENDOKN; + output LL2TFCINIT1SEQN; + output LL2TFCINIT2SEQN; + output LNKCLKEN; + output MIMRXRCE; + output MIMRXREN; + output MIMRXWEN; + output MIMTXRCE; + output MIMTXREN; + output MIMTXWEN; + output PIPERX0POLARITY; + output PIPERX1POLARITY; + output PIPERX2POLARITY; + output PIPERX3POLARITY; + output PIPERX4POLARITY; + output PIPERX5POLARITY; + output PIPERX6POLARITY; + output PIPERX7POLARITY; + output PIPETX0COMPLIANCE; + output PIPETX0ELECIDLE; + output PIPETX1COMPLIANCE; + output PIPETX1ELECIDLE; + output PIPETX2COMPLIANCE; + output PIPETX2ELECIDLE; + output PIPETX3COMPLIANCE; + output PIPETX3ELECIDLE; + output PIPETX4COMPLIANCE; + output PIPETX4ELECIDLE; + output PIPETX5COMPLIANCE; + output PIPETX5ELECIDLE; + output PIPETX6COMPLIANCE; + output PIPETX6ELECIDLE; + output PIPETX7COMPLIANCE; + output PIPETX7ELECIDLE; + output PIPETXDEEMPH; + output PIPETXRATE; + output PIPETXRCVRDET; + output PIPETXRESET; + output PL2LINKUPN; + output PL2RECEIVERERRN; + output PL2RECOVERYN; + output PL2RXELECIDLE; + output PL2SUSPENDOK; + output PLLINKGEN2CAP; + output PLLINKPARTNERGEN2SUPPORTED; + output PLLINKUPCFGCAP; + output PLPHYLNKUPN; + output PLRECEIVEDHOTRST; + output PLSELLNKRATE; + output RECEIVEDFUNCLVLRSTN; + output TL2ASPMSUSPENDCREDITCHECKOKN; + output TL2ASPMSUSPENDREQN; + output TL2PPMSUSPENDOKN; + output TRNLNKUPN; + output TRNRDLLPSRCRDYN; + output TRNRECRCERRN; + output TRNREOFN; + output TRNRERRFWDN; + output TRNRREMN; + output TRNRSOFN; + output TRNRSRCDSCN; + output TRNRSRCRDYN; + output TRNTCFGREQN; + output TRNTDLLPDSTRDYN; + output TRNTDSTRDYN; + output TRNTERRDROPN; + output USERRSTN; + output [11:0] DBGVECC; + output [11:0] PLDBGVEC; + output [11:0] TRNFCCPLD; + output [11:0] TRNFCNPD; + output [11:0] TRNFCPD; + output [12:0] MIMRXRADDR; + output [12:0] MIMRXWADDR; + output [12:0] MIMTXRADDR; + output [12:0] MIMTXWADDR; + output [15:0] CFGMSGDATA; + output [15:0] DRPDO; + output [15:0] PIPETX0DATA; + output [15:0] PIPETX1DATA; + output [15:0] PIPETX2DATA; + output [15:0] PIPETX3DATA; + output [15:0] PIPETX4DATA; + output [15:0] PIPETX5DATA; + output [15:0] PIPETX6DATA; + output [15:0] PIPETX7DATA; + output [1:0] CFGLINKCONTROLASPMCONTROL; + output [1:0] CFGLINKSTATUSCURRENTSPEED; + output [1:0] CFGPMCSRPOWERSTATE; + output [1:0] PIPETX0CHARISK; + output [1:0] PIPETX0POWERDOWN; + output [1:0] PIPETX1CHARISK; + output [1:0] PIPETX1POWERDOWN; + output [1:0] PIPETX2CHARISK; + output [1:0] PIPETX2POWERDOWN; + output [1:0] PIPETX3CHARISK; + output [1:0] PIPETX3POWERDOWN; + output [1:0] PIPETX4CHARISK; + output [1:0] PIPETX4POWERDOWN; + output [1:0] PIPETX5CHARISK; + output [1:0] PIPETX5POWERDOWN; + output [1:0] PIPETX6CHARISK; + output [1:0] PIPETX6POWERDOWN; + output [1:0] PIPETX7CHARISK; + output [1:0] PIPETX7POWERDOWN; + output [1:0] PLLANEREVERSALMODE; + output [1:0] PLRXPMSTATE; + output [1:0] PLSELLNKWIDTH; + output [2:0] CFGDEVCONTROLMAXPAYLOAD; + output [2:0] CFGDEVCONTROLMAXREADREQ; + output [2:0] CFGINTERRUPTMMENABLE; + output [2:0] CFGPCIELINKSTATE; + output [2:0] PIPETXMARGIN; + output [2:0] PLINITIALLINKWIDTH; + output [2:0] PLTXPMSTATE; + output [31:0] CFGDO; + output [31:0] TRNRDLLPDATA; + output [3:0] CFGDEVCONTROL2CPLTIMEOUTVAL; + output [3:0] CFGLINKSTATUSNEGOTIATEDWIDTH; + output [5:0] PLLTSSMSTATE; + output [5:0] TRNTBUFAV; + output [63:0] DBGVECA; + output [63:0] DBGVECB; + output [63:0] TRNRD; + output [67:0] MIMRXWDATA; + output [68:0] MIMTXWDATA; + output [6:0] CFGTRANSACTIONADDR; + output [6:0] CFGVCTCVCMAP; + output [6:0] TRNRBARHITN; + output [7:0] CFGINTERRUPTDO; + output [7:0] TRNFCCPLH; + output [7:0] TRNFCNPH; + output [7:0] TRNFCPH; + + input CFGERRACSN; + input CFGERRCORN; + input CFGERRCPLABORTN; + input CFGERRCPLTIMEOUTN; + input CFGERRCPLUNEXPECTN; + input CFGERRECRCN; + input CFGERRLOCKEDN; + input CFGERRPOSTEDN; + input CFGERRURN; + input CFGINTERRUPTASSERTN; + input CFGINTERRUPTN; + input CFGPMDIRECTASPML1N; + input CFGPMSENDPMACKN; + input CFGPMSENDPMETON; + input CFGPMSENDPMNAKN; + input CFGPMTURNOFFOKN; + input CFGPMWAKEN; + input CFGRDENN; + input CFGTRNPENDINGN; + input CFGWRENN; + input CFGWRREADONLYN; + input CFGWRRW1CASRWN; + input CMRSTN; + input CMSTICKYRSTN; + input DBGSUBMODE; + input DLRSTN; + input DRPCLK; + input DRPDEN; + input DRPDWE; + input FUNCLVLRSTN; + input LL2SENDASREQL1N; + input LL2SENDENTERL1N; + input LL2SENDENTERL23N; + input LL2SUSPENDNOWN; + input LL2TLPRCVN; + input PIPECLK; + input PIPERX0CHANISALIGNED; + input PIPERX0ELECIDLE; + input PIPERX0PHYSTATUS; + input PIPERX0VALID; + input PIPERX1CHANISALIGNED; + input PIPERX1ELECIDLE; + input PIPERX1PHYSTATUS; + input PIPERX1VALID; + input PIPERX2CHANISALIGNED; + input PIPERX2ELECIDLE; + input PIPERX2PHYSTATUS; + input PIPERX2VALID; + input PIPERX3CHANISALIGNED; + input PIPERX3ELECIDLE; + input PIPERX3PHYSTATUS; + input PIPERX3VALID; + input PIPERX4CHANISALIGNED; + input PIPERX4ELECIDLE; + input PIPERX4PHYSTATUS; + input PIPERX4VALID; + input PIPERX5CHANISALIGNED; + input PIPERX5ELECIDLE; + input PIPERX5PHYSTATUS; + input PIPERX5VALID; + input PIPERX6CHANISALIGNED; + input PIPERX6ELECIDLE; + input PIPERX6PHYSTATUS; + input PIPERX6VALID; + input PIPERX7CHANISALIGNED; + input PIPERX7ELECIDLE; + input PIPERX7PHYSTATUS; + input PIPERX7VALID; + input PLDIRECTEDLINKAUTON; + input PLDIRECTEDLINKSPEED; + input PLDOWNSTREAMDEEMPHSOURCE; + input PLRSTN; + input PLTRANSMITHOTRST; + input PLUPSTREAMPREFERDEEMPH; + input SYSRSTN; + input TL2ASPMSUSPENDCREDITCHECKN; + input TL2PPMSUSPENDREQN; + input TLRSTN; + input TRNRDSTRDYN; + input TRNRNPOKN; + input TRNTCFGGNTN; + input TRNTDLLPSRCRDYN; + input TRNTECRCGENN; + input TRNTEOFN; + input TRNTERRFWDN; + input TRNTREMN; + input TRNTSOFN; + input TRNTSRCDSCN; + input TRNTSRCRDYN; + input TRNTSTRN; + input USERCLK; + input [127:0] CFGERRAERHEADERLOG; + input [15:0] DRPDI; + input [15:0] PIPERX0DATA; + input [15:0] PIPERX1DATA; + input [15:0] PIPERX2DATA; + input [15:0] PIPERX3DATA; + input [15:0] PIPERX4DATA; + input [15:0] PIPERX5DATA; + input [15:0] PIPERX6DATA; + input [15:0] PIPERX7DATA; + input [1:0] DBGMODE; + input [1:0] PIPERX0CHARISK; + input [1:0] PIPERX1CHARISK; + input [1:0] PIPERX2CHARISK; + input [1:0] PIPERX3CHARISK; + input [1:0] PIPERX4CHARISK; + input [1:0] PIPERX5CHARISK; + input [1:0] PIPERX6CHARISK; + input [1:0] PIPERX7CHARISK; + input [1:0] PLDIRECTEDLINKCHANGE; + input [1:0] PLDIRECTEDLINKWIDTH; + input [2:0] CFGDSFUNCTIONNUMBER; + input [2:0] PIPERX0STATUS; + input [2:0] PIPERX1STATUS; + input [2:0] PIPERX2STATUS; + input [2:0] PIPERX3STATUS; + input [2:0] PIPERX4STATUS; + input [2:0] PIPERX5STATUS; + input [2:0] PIPERX6STATUS; + input [2:0] PIPERX7STATUS; + input [2:0] PLDBGMODE; + input [2:0] TRNFCSEL; + input [31:0] CFGDI; + input [31:0] TRNTDLLPDATA; + input [3:0] CFGBYTEENN; + input [47:0] CFGERRTLPCPLHEADER; + input [4:0] CFGDSDEVICENUMBER; + input [4:0] PL2DIRECTEDLSTATE; + input [63:0] CFGDSN; + input [63:0] TRNTD; + input [67:0] MIMRXRDATA; + input [68:0] MIMTXRDATA; + input [7:0] CFGDSBUSNUMBER; + input [7:0] CFGINTERRUPTDI; + input [7:0] CFGPORTNUMBER; + input [8:0] DRPDADDR; + input [9:0] CFGDWADDR; + + reg AER_CAP_ECRC_CHECK_CAPABLE_BINARY; + reg AER_CAP_ECRC_GEN_CAPABLE_BINARY; + reg AER_CAP_ON_BINARY; + reg AER_CAP_PERMIT_ROOTERR_UPDATE_BINARY; + reg ALLOW_X8_GEN2_BINARY; + reg CMD_INTX_IMPLEMENTED_BINARY; + reg CPL_TIMEOUT_DISABLE_SUPPORTED_BINARY; + reg DEV_CAP_ENABLE_SLOT_PWR_LIMIT_SCALE_BINARY; + reg DEV_CAP_ENABLE_SLOT_PWR_LIMIT_VALUE_BINARY; + reg DEV_CAP_EXT_TAG_SUPPORTED_BINARY; + reg DEV_CAP_FUNCTION_LEVEL_RESET_CAPABLE_BINARY; + reg DEV_CAP_ROLE_BASED_ERROR_BINARY; + reg DEV_CONTROL_AUX_POWER_SUPPORTED_BINARY; + reg DISABLE_ASPM_L1_TIMER_BINARY; + reg DISABLE_BAR_FILTERING_BINARY; + reg DISABLE_ID_CHECK_BINARY; + reg DISABLE_LANE_REVERSAL_BINARY; + reg DISABLE_RX_TC_FILTER_BINARY; + reg DISABLE_SCRAMBLING_BINARY; + reg DSN_CAP_ON_BINARY; + reg ENABLE_RX_TD_ECRC_TRIM_BINARY; + reg ENTER_RVRY_EI_L0_BINARY; + reg EXIT_LOOPBACK_ON_EI_BINARY; + reg IS_SWITCH_BINARY; + reg LINK_CAP_CLOCK_POWER_MANAGEMENT_BINARY; + reg LINK_CAP_DLL_LINK_ACTIVE_REPORTING_CAP_BINARY; + reg LINK_CAP_LINK_BANDWIDTH_NOTIFICATION_CAP_BINARY; + reg LINK_CAP_SURPRISE_DOWN_ERROR_CAPABLE_BINARY; + reg LINK_CONTROL_RCB_BINARY; + reg LINK_CTRL2_DEEMPHASIS_BINARY; + reg LINK_CTRL2_HW_AUTONOMOUS_SPEED_DISABLE_BINARY; + reg LINK_STATUS_SLOT_CLOCK_CONFIG_BINARY; + reg LL_ACK_TIMEOUT_EN_BINARY; + reg LL_REPLAY_TIMEOUT_EN_BINARY; + reg MSIX_CAP_ON_BINARY; + reg MSI_CAP_64_BIT_ADDR_CAPABLE_BINARY; + reg MSI_CAP_MULTIMSG_EXTENSION_BINARY; + reg MSI_CAP_ON_BINARY; + reg MSI_CAP_PER_VECTOR_MASKING_CAPABLE_BINARY; + reg PCIE_CAP_ON_BINARY; + reg PCIE_CAP_SLOT_IMPLEMENTED_BINARY; + reg PL_FAST_TRAIN_BINARY; + reg PM_CAP_D1SUPPORT_BINARY; + reg PM_CAP_D2SUPPORT_BINARY; + reg PM_CAP_DSI_BINARY; + reg PM_CAP_ON_BINARY; + reg PM_CAP_PME_CLOCK_BINARY; + reg PM_CAP_RSVD_04_BINARY; + reg PM_CSR_B2B3_BINARY; + reg PM_CSR_BPCCEN_BINARY; + reg PM_CSR_NOSOFTRST_BINARY; + reg RECRC_CHK_TRIM_BINARY; + reg ROOT_CAP_CRS_SW_VISIBILITY_BINARY; + reg SELECT_DLL_IF_BINARY; + reg SIM_VERSION_BINARY; + reg SLOT_CAP_ATT_BUTTON_PRESENT_BINARY; + reg SLOT_CAP_ATT_INDICATOR_PRESENT_BINARY; + reg SLOT_CAP_ELEC_INTERLOCK_PRESENT_BINARY; + reg SLOT_CAP_HOTPLUG_CAPABLE_BINARY; + reg SLOT_CAP_HOTPLUG_SURPRISE_BINARY; + reg SLOT_CAP_MRL_SENSOR_PRESENT_BINARY; + reg SLOT_CAP_NO_CMD_COMPLETED_SUPPORT_BINARY; + reg SLOT_CAP_POWER_CONTROLLER_PRESENT_BINARY; + reg SLOT_CAP_POWER_INDICATOR_PRESENT_BINARY; + reg SPARE_BIT0_BINARY; + reg SPARE_BIT1_BINARY; + reg SPARE_BIT2_BINARY; + reg SPARE_BIT3_BINARY; + reg SPARE_BIT4_BINARY; + reg SPARE_BIT5_BINARY; + reg SPARE_BIT6_BINARY; + reg SPARE_BIT7_BINARY; + reg SPARE_BIT8_BINARY; + reg TL_RBYPASS_BINARY; + reg TL_RX_RAM_RADDR_LATENCY_BINARY; + reg TL_RX_RAM_WRITE_LATENCY_BINARY; + reg TL_TFC_DISABLE_BINARY; + reg TL_TX_CHECKS_DISABLE_BINARY; + reg TL_TX_RAM_RADDR_LATENCY_BINARY; + reg TL_TX_RAM_WRITE_LATENCY_BINARY; + reg UPCONFIG_CAPABLE_BINARY; + reg UPSTREAM_FACING_BINARY; + reg UR_INV_REQ_BINARY; + reg VC0_CPL_INFINITE_BINARY; + reg VC_CAP_ON_BINARY; + reg VC_CAP_REJECT_SNOOP_TRANSACTIONS_BINARY; + reg VSEC_CAP_IS_LINK_VISIBLE_BINARY; + reg VSEC_CAP_ON_BINARY; + reg [10:0] VC0_TOTAL_CREDITS_CD_BINARY; + reg [10:0] VC0_TOTAL_CREDITS_PD_BINARY; + reg [1:0] DEV_CAP_PHANTOM_FUNCTIONS_SUPPORT_BINARY; + reg [1:0] DEV_CAP_RSVD_17_16_BINARY; + reg [1:0] LINK_CAP_ASPM_SUPPORT_BINARY; + reg [1:0] LINK_CAP_RSVD_23_22_BINARY; + reg [1:0] LL_ACK_TIMEOUT_FUNC_BINARY; + reg [1:0] LL_REPLAY_TIMEOUT_FUNC_BINARY; + reg [1:0] PCIE_CAP_RSVD_15_14_BINARY; + reg [1:0] RECRC_CHK_BINARY; + reg [1:0] SLOT_CAP_SLOT_POWER_LIMIT_SCALE_BINARY; + reg [1:0] TL_RX_RAM_RDATA_LATENCY_BINARY; + reg [1:0] TL_TX_RAM_RDATA_LATENCY_BINARY; + reg [2:0] DEV_CAP_ENDPOINT_L0S_LATENCY_BINARY; + reg [2:0] DEV_CAP_ENDPOINT_L1_LATENCY_BINARY; + reg [2:0] DEV_CAP_MAX_PAYLOAD_SUPPORTED_BINARY; + reg [2:0] DEV_CAP_RSVD_14_12_BINARY; + reg [2:0] DEV_CAP_RSVD_31_29_BINARY; + reg [2:0] LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN1_BINARY; + reg [2:0] LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN2_BINARY; + reg [2:0] LINK_CAP_L0S_EXIT_LATENCY_GEN1_BINARY; + reg [2:0] LINK_CAP_L0S_EXIT_LATENCY_GEN2_BINARY; + reg [2:0] LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN1_BINARY; + reg [2:0] LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN2_BINARY; + reg [2:0] LINK_CAP_L1_EXIT_LATENCY_GEN1_BINARY; + reg [2:0] LINK_CAP_L1_EXIT_LATENCY_GEN2_BINARY; + reg [2:0] MSIX_CAP_PBA_BIR_BINARY; + reg [2:0] MSIX_CAP_TABLE_BIR_BINARY; + reg [2:0] MSI_CAP_MULTIMSGCAP_BINARY; + reg [2:0] PGL0_LANE_BINARY; + reg [2:0] PGL1_LANE_BINARY; + reg [2:0] PGL2_LANE_BINARY; + reg [2:0] PGL3_LANE_BINARY; + reg [2:0] PGL4_LANE_BINARY; + reg [2:0] PGL5_LANE_BINARY; + reg [2:0] PGL6_LANE_BINARY; + reg [2:0] PGL7_LANE_BINARY; + reg [2:0] PL_AUTO_CONFIG_BINARY; + reg [2:0] PM_CAP_AUXCURRENT_BINARY; + reg [2:0] PM_CAP_VERSION_BINARY; + reg [2:0] USER_CLK_FREQ_BINARY; + reg [3:0] PCIE_REVISION_BINARY; + reg [4:0] VC0_TX_LASTPACKET_BINARY; + reg [6:0] VC0_TOTAL_CREDITS_CH_BINARY; + reg [6:0] VC0_TOTAL_CREDITS_NPH_BINARY; + reg [6:0] VC0_TOTAL_CREDITS_PH_BINARY; + reg [7:0] N_FTS_COMCLK_GEN1_BINARY; + reg [7:0] N_FTS_COMCLK_GEN2_BINARY; + reg [7:0] N_FTS_GEN1_BINARY; + reg [7:0] N_FTS_GEN2_BINARY; + + tri0 GSR = glbl.GSR; + + initial begin + case (AER_CAP_ECRC_CHECK_CAPABLE) + "FALSE" : AER_CAP_ECRC_CHECK_CAPABLE_BINARY = 1'b0; + "TRUE" : AER_CAP_ECRC_CHECK_CAPABLE_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute AER_CAP_ECRC_CHECK_CAPABLE on PCIE_2_0 instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", AER_CAP_ECRC_CHECK_CAPABLE); + $finish; + end + endcase + + case (AER_CAP_ECRC_GEN_CAPABLE) + "FALSE" : AER_CAP_ECRC_GEN_CAPABLE_BINARY = 1'b0; + "TRUE" : AER_CAP_ECRC_GEN_CAPABLE_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute AER_CAP_ECRC_GEN_CAPABLE on PCIE_2_0 instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", AER_CAP_ECRC_GEN_CAPABLE); + $finish; + end + endcase + + case (AER_CAP_ON) + "FALSE" : AER_CAP_ON_BINARY = 1'b0; + "TRUE" : AER_CAP_ON_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute AER_CAP_ON on PCIE_2_0 instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", AER_CAP_ON); + $finish; + end + endcase + + case (AER_CAP_PERMIT_ROOTERR_UPDATE) + "FALSE" : AER_CAP_PERMIT_ROOTERR_UPDATE_BINARY = 1'b0; + "TRUE" : AER_CAP_PERMIT_ROOTERR_UPDATE_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute AER_CAP_PERMIT_ROOTERR_UPDATE on PCIE_2_0 instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", AER_CAP_PERMIT_ROOTERR_UPDATE); + $finish; + end + endcase + + case (ALLOW_X8_GEN2) + "FALSE" : ALLOW_X8_GEN2_BINARY = 1'b0; + "TRUE" : ALLOW_X8_GEN2_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute ALLOW_X8_GEN2 on PCIE_2_0 instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", ALLOW_X8_GEN2); + $finish; + end + endcase + + case (CMD_INTX_IMPLEMENTED) + "FALSE" : CMD_INTX_IMPLEMENTED_BINARY = 1'b0; + "TRUE" : CMD_INTX_IMPLEMENTED_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute CMD_INTX_IMPLEMENTED on PCIE_2_0 instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", CMD_INTX_IMPLEMENTED); + $finish; + end + endcase + + case (CPL_TIMEOUT_DISABLE_SUPPORTED) + "FALSE" : CPL_TIMEOUT_DISABLE_SUPPORTED_BINARY = 1'b0; + "TRUE" : CPL_TIMEOUT_DISABLE_SUPPORTED_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute CPL_TIMEOUT_DISABLE_SUPPORTED on PCIE_2_0 instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", CPL_TIMEOUT_DISABLE_SUPPORTED); + $finish; + end + endcase + + case (DEV_CAP_ENABLE_SLOT_PWR_LIMIT_SCALE) + "FALSE" : DEV_CAP_ENABLE_SLOT_PWR_LIMIT_SCALE_BINARY = 1'b0; + "TRUE" : DEV_CAP_ENABLE_SLOT_PWR_LIMIT_SCALE_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute DEV_CAP_ENABLE_SLOT_PWR_LIMIT_SCALE on PCIE_2_0 instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", DEV_CAP_ENABLE_SLOT_PWR_LIMIT_SCALE); + $finish; + end + endcase + + case (DEV_CAP_ENABLE_SLOT_PWR_LIMIT_VALUE) + "FALSE" : DEV_CAP_ENABLE_SLOT_PWR_LIMIT_VALUE_BINARY = 1'b0; + "TRUE" : DEV_CAP_ENABLE_SLOT_PWR_LIMIT_VALUE_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute DEV_CAP_ENABLE_SLOT_PWR_LIMIT_VALUE on PCIE_2_0 instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", DEV_CAP_ENABLE_SLOT_PWR_LIMIT_VALUE); + $finish; + end + endcase + + case (DEV_CAP_EXT_TAG_SUPPORTED) + "FALSE" : DEV_CAP_EXT_TAG_SUPPORTED_BINARY = 1'b0; + "TRUE" : DEV_CAP_EXT_TAG_SUPPORTED_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute DEV_CAP_EXT_TAG_SUPPORTED on PCIE_2_0 instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", DEV_CAP_EXT_TAG_SUPPORTED); + $finish; + end + endcase + + case (DEV_CAP_FUNCTION_LEVEL_RESET_CAPABLE) + "FALSE" : DEV_CAP_FUNCTION_LEVEL_RESET_CAPABLE_BINARY = 1'b0; + "TRUE" : DEV_CAP_FUNCTION_LEVEL_RESET_CAPABLE_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute DEV_CAP_FUNCTION_LEVEL_RESET_CAPABLE on PCIE_2_0 instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", DEV_CAP_FUNCTION_LEVEL_RESET_CAPABLE); + $finish; + end + endcase + + case (DEV_CAP_ROLE_BASED_ERROR) + "FALSE" : DEV_CAP_ROLE_BASED_ERROR_BINARY = 1'b0; + "TRUE" : DEV_CAP_ROLE_BASED_ERROR_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute DEV_CAP_ROLE_BASED_ERROR on PCIE_2_0 instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", DEV_CAP_ROLE_BASED_ERROR); + $finish; + end + endcase + + case (DEV_CONTROL_AUX_POWER_SUPPORTED) + "FALSE" : DEV_CONTROL_AUX_POWER_SUPPORTED_BINARY = 1'b0; + "TRUE" : DEV_CONTROL_AUX_POWER_SUPPORTED_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute DEV_CONTROL_AUX_POWER_SUPPORTED on PCIE_2_0 instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", DEV_CONTROL_AUX_POWER_SUPPORTED); + $finish; + end + endcase + + case (DISABLE_ASPM_L1_TIMER) + "FALSE" : DISABLE_ASPM_L1_TIMER_BINARY = 1'b0; + "TRUE" : DISABLE_ASPM_L1_TIMER_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute DISABLE_ASPM_L1_TIMER on PCIE_2_0 instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", DISABLE_ASPM_L1_TIMER); + $finish; + end + endcase + + case (DISABLE_BAR_FILTERING) + "FALSE" : DISABLE_BAR_FILTERING_BINARY = 1'b0; + "TRUE" : DISABLE_BAR_FILTERING_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute DISABLE_BAR_FILTERING on PCIE_2_0 instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", DISABLE_BAR_FILTERING); + $finish; + end + endcase + + case (DISABLE_ID_CHECK) + "FALSE" : DISABLE_ID_CHECK_BINARY = 1'b0; + "TRUE" : DISABLE_ID_CHECK_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute DISABLE_ID_CHECK on PCIE_2_0 instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", DISABLE_ID_CHECK); + $finish; + end + endcase + + case (DISABLE_LANE_REVERSAL) + "FALSE" : DISABLE_LANE_REVERSAL_BINARY = 1'b0; + "TRUE" : DISABLE_LANE_REVERSAL_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute DISABLE_LANE_REVERSAL on PCIE_2_0 instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", DISABLE_LANE_REVERSAL); + $finish; + end + endcase + + case (DISABLE_RX_TC_FILTER) + "FALSE" : DISABLE_RX_TC_FILTER_BINARY = 1'b0; + "TRUE" : DISABLE_RX_TC_FILTER_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute DISABLE_RX_TC_FILTER on PCIE_2_0 instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", DISABLE_RX_TC_FILTER); + $finish; + end + endcase + + case (DISABLE_SCRAMBLING) + "FALSE" : DISABLE_SCRAMBLING_BINARY = 1'b0; + "TRUE" : DISABLE_SCRAMBLING_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute DISABLE_SCRAMBLING on PCIE_2_0 instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", DISABLE_SCRAMBLING); + $finish; + end + endcase + + case (DSN_CAP_ON) + "FALSE" : DSN_CAP_ON_BINARY = 1'b0; + "TRUE" : DSN_CAP_ON_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute DSN_CAP_ON on PCIE_2_0 instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", DSN_CAP_ON); + $finish; + end + endcase + + case (ENABLE_RX_TD_ECRC_TRIM) + "FALSE" : ENABLE_RX_TD_ECRC_TRIM_BINARY = 1'b0; + "TRUE" : ENABLE_RX_TD_ECRC_TRIM_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute ENABLE_RX_TD_ECRC_TRIM on PCIE_2_0 instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", ENABLE_RX_TD_ECRC_TRIM); + $finish; + end + endcase + + case (ENTER_RVRY_EI_L0) + "FALSE" : ENTER_RVRY_EI_L0_BINARY = 1'b0; + "TRUE" : ENTER_RVRY_EI_L0_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute ENTER_RVRY_EI_L0 on PCIE_2_0 instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", ENTER_RVRY_EI_L0); + $finish; + end + endcase + + case (EXIT_LOOPBACK_ON_EI) + "FALSE" : EXIT_LOOPBACK_ON_EI_BINARY = 1'b0; + "TRUE" : EXIT_LOOPBACK_ON_EI_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute EXIT_LOOPBACK_ON_EI on PCIE_2_0 instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", EXIT_LOOPBACK_ON_EI); + $finish; + end + endcase + + case (IS_SWITCH) + "FALSE" : IS_SWITCH_BINARY = 1'b0; + "TRUE" : IS_SWITCH_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute IS_SWITCH on PCIE_2_0 instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", IS_SWITCH); + $finish; + end + endcase + + case (LINK_CAP_CLOCK_POWER_MANAGEMENT) + "FALSE" : LINK_CAP_CLOCK_POWER_MANAGEMENT_BINARY = 1'b0; + "TRUE" : LINK_CAP_CLOCK_POWER_MANAGEMENT_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute LINK_CAP_CLOCK_POWER_MANAGEMENT on PCIE_2_0 instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", LINK_CAP_CLOCK_POWER_MANAGEMENT); + $finish; + end + endcase + + case (LINK_CAP_DLL_LINK_ACTIVE_REPORTING_CAP) + "FALSE" : LINK_CAP_DLL_LINK_ACTIVE_REPORTING_CAP_BINARY = 1'b0; + "TRUE" : LINK_CAP_DLL_LINK_ACTIVE_REPORTING_CAP_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute LINK_CAP_DLL_LINK_ACTIVE_REPORTING_CAP on PCIE_2_0 instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", LINK_CAP_DLL_LINK_ACTIVE_REPORTING_CAP); + $finish; + end + endcase + + case (LINK_CAP_LINK_BANDWIDTH_NOTIFICATION_CAP) + "FALSE" : LINK_CAP_LINK_BANDWIDTH_NOTIFICATION_CAP_BINARY = 1'b0; + "TRUE" : LINK_CAP_LINK_BANDWIDTH_NOTIFICATION_CAP_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute LINK_CAP_LINK_BANDWIDTH_NOTIFICATION_CAP on PCIE_2_0 instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", LINK_CAP_LINK_BANDWIDTH_NOTIFICATION_CAP); + $finish; + end + endcase + + case (LINK_CAP_SURPRISE_DOWN_ERROR_CAPABLE) + "FALSE" : LINK_CAP_SURPRISE_DOWN_ERROR_CAPABLE_BINARY = 1'b0; + "TRUE" : LINK_CAP_SURPRISE_DOWN_ERROR_CAPABLE_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute LINK_CAP_SURPRISE_DOWN_ERROR_CAPABLE on PCIE_2_0 instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", LINK_CAP_SURPRISE_DOWN_ERROR_CAPABLE); + $finish; + end + endcase + + case (LINK_CTRL2_DEEMPHASIS) + "FALSE" : LINK_CTRL2_DEEMPHASIS_BINARY = 1'b0; + "TRUE" : LINK_CTRL2_DEEMPHASIS_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute LINK_CTRL2_DEEMPHASIS on PCIE_2_0 instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", LINK_CTRL2_DEEMPHASIS); + $finish; + end + endcase + + case (LINK_CTRL2_HW_AUTONOMOUS_SPEED_DISABLE) + "FALSE" : LINK_CTRL2_HW_AUTONOMOUS_SPEED_DISABLE_BINARY = 1'b0; + "TRUE" : LINK_CTRL2_HW_AUTONOMOUS_SPEED_DISABLE_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute LINK_CTRL2_HW_AUTONOMOUS_SPEED_DISABLE on PCIE_2_0 instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", LINK_CTRL2_HW_AUTONOMOUS_SPEED_DISABLE); + $finish; + end + endcase + + case (LINK_STATUS_SLOT_CLOCK_CONFIG) + "FALSE" : LINK_STATUS_SLOT_CLOCK_CONFIG_BINARY = 1'b0; + "TRUE" : LINK_STATUS_SLOT_CLOCK_CONFIG_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute LINK_STATUS_SLOT_CLOCK_CONFIG on PCIE_2_0 instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", LINK_STATUS_SLOT_CLOCK_CONFIG); + $finish; + end + endcase + + case (LL_ACK_TIMEOUT_EN) + "FALSE" : LL_ACK_TIMEOUT_EN_BINARY = 1'b0; + "TRUE" : LL_ACK_TIMEOUT_EN_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute LL_ACK_TIMEOUT_EN on PCIE_2_0 instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", LL_ACK_TIMEOUT_EN); + $finish; + end + endcase + + case (LL_REPLAY_TIMEOUT_EN) + "FALSE" : LL_REPLAY_TIMEOUT_EN_BINARY = 1'b0; + "TRUE" : LL_REPLAY_TIMEOUT_EN_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute LL_REPLAY_TIMEOUT_EN on PCIE_2_0 instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", LL_REPLAY_TIMEOUT_EN); + $finish; + end + endcase + + case (MSIX_CAP_ON) + "FALSE" : MSIX_CAP_ON_BINARY = 1'b0; + "TRUE" : MSIX_CAP_ON_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute MSIX_CAP_ON on PCIE_2_0 instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", MSIX_CAP_ON); + $finish; + end + endcase + + case (MSI_CAP_64_BIT_ADDR_CAPABLE) + "FALSE" : MSI_CAP_64_BIT_ADDR_CAPABLE_BINARY = 1'b0; + "TRUE" : MSI_CAP_64_BIT_ADDR_CAPABLE_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute MSI_CAP_64_BIT_ADDR_CAPABLE on PCIE_2_0 instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", MSI_CAP_64_BIT_ADDR_CAPABLE); + $finish; + end + endcase + + case (MSI_CAP_ON) + "FALSE" : MSI_CAP_ON_BINARY = 1'b0; + "TRUE" : MSI_CAP_ON_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute MSI_CAP_ON on PCIE_2_0 instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", MSI_CAP_ON); + $finish; + end + endcase + + case (MSI_CAP_PER_VECTOR_MASKING_CAPABLE) + "FALSE" : MSI_CAP_PER_VECTOR_MASKING_CAPABLE_BINARY = 1'b0; + "TRUE" : MSI_CAP_PER_VECTOR_MASKING_CAPABLE_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute MSI_CAP_PER_VECTOR_MASKING_CAPABLE on PCIE_2_0 instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", MSI_CAP_PER_VECTOR_MASKING_CAPABLE); + $finish; + end + endcase + + case (PCIE_CAP_ON) + "FALSE" : PCIE_CAP_ON_BINARY = 1'b0; + "TRUE" : PCIE_CAP_ON_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute PCIE_CAP_ON on PCIE_2_0 instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", PCIE_CAP_ON); + $finish; + end + endcase + + case (PCIE_CAP_SLOT_IMPLEMENTED) + "FALSE" : PCIE_CAP_SLOT_IMPLEMENTED_BINARY = 1'b0; + "TRUE" : PCIE_CAP_SLOT_IMPLEMENTED_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute PCIE_CAP_SLOT_IMPLEMENTED on PCIE_2_0 instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", PCIE_CAP_SLOT_IMPLEMENTED); + $finish; + end + endcase + + case (PL_FAST_TRAIN) + "FALSE" : PL_FAST_TRAIN_BINARY = 1'b0; + "TRUE" : PL_FAST_TRAIN_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute PL_FAST_TRAIN on PCIE_2_0 instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", PL_FAST_TRAIN); + $finish; + end + endcase + + case (PM_CAP_D1SUPPORT) + "FALSE" : PM_CAP_D1SUPPORT_BINARY = 1'b0; + "TRUE" : PM_CAP_D1SUPPORT_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute PM_CAP_D1SUPPORT on PCIE_2_0 instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", PM_CAP_D1SUPPORT); + $finish; + end + endcase + + case (PM_CAP_D2SUPPORT) + "FALSE" : PM_CAP_D2SUPPORT_BINARY = 1'b0; + "TRUE" : PM_CAP_D2SUPPORT_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute PM_CAP_D2SUPPORT on PCIE_2_0 instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", PM_CAP_D2SUPPORT); + $finish; + end + endcase + + case (PM_CAP_DSI) + "FALSE" : PM_CAP_DSI_BINARY = 1'b0; + "TRUE" : PM_CAP_DSI_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute PM_CAP_DSI on PCIE_2_0 instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", PM_CAP_DSI); + $finish; + end + endcase + + case (PM_CAP_ON) + "FALSE" : PM_CAP_ON_BINARY = 1'b0; + "TRUE" : PM_CAP_ON_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute PM_CAP_ON on PCIE_2_0 instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", PM_CAP_ON); + $finish; + end + endcase + + case (PM_CAP_PME_CLOCK) + "FALSE" : PM_CAP_PME_CLOCK_BINARY = 1'b0; + "TRUE" : PM_CAP_PME_CLOCK_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute PM_CAP_PME_CLOCK on PCIE_2_0 instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", PM_CAP_PME_CLOCK); + $finish; + end + endcase + + case (PM_CSR_B2B3) + "FALSE" : PM_CSR_B2B3_BINARY = 1'b0; + "TRUE" : PM_CSR_B2B3_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute PM_CSR_B2B3 on PCIE_2_0 instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", PM_CSR_B2B3); + $finish; + end + endcase + + case (PM_CSR_BPCCEN) + "FALSE" : PM_CSR_BPCCEN_BINARY = 1'b0; + "TRUE" : PM_CSR_BPCCEN_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute PM_CSR_BPCCEN on PCIE_2_0 instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", PM_CSR_BPCCEN); + $finish; + end + endcase + + case (PM_CSR_NOSOFTRST) + "FALSE" : PM_CSR_NOSOFTRST_BINARY = 1'b0; + "TRUE" : PM_CSR_NOSOFTRST_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute PM_CSR_NOSOFTRST on PCIE_2_0 instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", PM_CSR_NOSOFTRST); + $finish; + end + endcase + + case (RECRC_CHK_TRIM) + "FALSE" : RECRC_CHK_TRIM_BINARY = 1'b0; + "TRUE" : RECRC_CHK_TRIM_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute RECRC_CHK_TRIM on PCIE_2_0 instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", RECRC_CHK_TRIM); + $finish; + end + endcase + + case (ROOT_CAP_CRS_SW_VISIBILITY) + "FALSE" : ROOT_CAP_CRS_SW_VISIBILITY_BINARY = 1'b0; + "TRUE" : ROOT_CAP_CRS_SW_VISIBILITY_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute ROOT_CAP_CRS_SW_VISIBILITY on PCIE_2_0 instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", ROOT_CAP_CRS_SW_VISIBILITY); + $finish; + end + endcase + + case (SELECT_DLL_IF) + "FALSE" : SELECT_DLL_IF_BINARY = 1'b0; + "TRUE" : SELECT_DLL_IF_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute SELECT_DLL_IF on PCIE_2_0 instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", SELECT_DLL_IF); + $finish; + end + endcase + + case (SLOT_CAP_ATT_BUTTON_PRESENT) + "FALSE" : SLOT_CAP_ATT_BUTTON_PRESENT_BINARY = 1'b0; + "TRUE" : SLOT_CAP_ATT_BUTTON_PRESENT_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute SLOT_CAP_ATT_BUTTON_PRESENT on PCIE_2_0 instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", SLOT_CAP_ATT_BUTTON_PRESENT); + $finish; + end + endcase + + case (SLOT_CAP_ATT_INDICATOR_PRESENT) + "FALSE" : SLOT_CAP_ATT_INDICATOR_PRESENT_BINARY = 1'b0; + "TRUE" : SLOT_CAP_ATT_INDICATOR_PRESENT_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute SLOT_CAP_ATT_INDICATOR_PRESENT on PCIE_2_0 instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", SLOT_CAP_ATT_INDICATOR_PRESENT); + $finish; + end + endcase + + case (SLOT_CAP_ELEC_INTERLOCK_PRESENT) + "FALSE" : SLOT_CAP_ELEC_INTERLOCK_PRESENT_BINARY = 1'b0; + "TRUE" : SLOT_CAP_ELEC_INTERLOCK_PRESENT_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute SLOT_CAP_ELEC_INTERLOCK_PRESENT on PCIE_2_0 instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", SLOT_CAP_ELEC_INTERLOCK_PRESENT); + $finish; + end + endcase + + case (SLOT_CAP_HOTPLUG_CAPABLE) + "FALSE" : SLOT_CAP_HOTPLUG_CAPABLE_BINARY = 1'b0; + "TRUE" : SLOT_CAP_HOTPLUG_CAPABLE_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute SLOT_CAP_HOTPLUG_CAPABLE on PCIE_2_0 instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", SLOT_CAP_HOTPLUG_CAPABLE); + $finish; + end + endcase + + case (SLOT_CAP_HOTPLUG_SURPRISE) + "FALSE" : SLOT_CAP_HOTPLUG_SURPRISE_BINARY = 1'b0; + "TRUE" : SLOT_CAP_HOTPLUG_SURPRISE_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute SLOT_CAP_HOTPLUG_SURPRISE on PCIE_2_0 instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", SLOT_CAP_HOTPLUG_SURPRISE); + $finish; + end + endcase + + case (SLOT_CAP_MRL_SENSOR_PRESENT) + "FALSE" : SLOT_CAP_MRL_SENSOR_PRESENT_BINARY = 1'b0; + "TRUE" : SLOT_CAP_MRL_SENSOR_PRESENT_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute SLOT_CAP_MRL_SENSOR_PRESENT on PCIE_2_0 instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", SLOT_CAP_MRL_SENSOR_PRESENT); + $finish; + end + endcase + + case (SLOT_CAP_NO_CMD_COMPLETED_SUPPORT) + "FALSE" : SLOT_CAP_NO_CMD_COMPLETED_SUPPORT_BINARY = 1'b0; + "TRUE" : SLOT_CAP_NO_CMD_COMPLETED_SUPPORT_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute SLOT_CAP_NO_CMD_COMPLETED_SUPPORT on PCIE_2_0 instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", SLOT_CAP_NO_CMD_COMPLETED_SUPPORT); + $finish; + end + endcase + + case (SLOT_CAP_POWER_CONTROLLER_PRESENT) + "FALSE" : SLOT_CAP_POWER_CONTROLLER_PRESENT_BINARY = 1'b0; + "TRUE" : SLOT_CAP_POWER_CONTROLLER_PRESENT_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute SLOT_CAP_POWER_CONTROLLER_PRESENT on PCIE_2_0 instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", SLOT_CAP_POWER_CONTROLLER_PRESENT); + $finish; + end + endcase + + case (SLOT_CAP_POWER_INDICATOR_PRESENT) + "FALSE" : SLOT_CAP_POWER_INDICATOR_PRESENT_BINARY = 1'b0; + "TRUE" : SLOT_CAP_POWER_INDICATOR_PRESENT_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute SLOT_CAP_POWER_INDICATOR_PRESENT on PCIE_2_0 instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", SLOT_CAP_POWER_INDICATOR_PRESENT); + $finish; + end + endcase + + case (TL_RBYPASS) + "FALSE" : TL_RBYPASS_BINARY = 1'b0; + "TRUE" : TL_RBYPASS_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute TL_RBYPASS on PCIE_2_0 instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", TL_RBYPASS); + $finish; + end + endcase + + case (TL_TFC_DISABLE) + "FALSE" : TL_TFC_DISABLE_BINARY = 1'b0; + "TRUE" : TL_TFC_DISABLE_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute TL_TFC_DISABLE on PCIE_2_0 instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", TL_TFC_DISABLE); + $finish; + end + endcase + + case (TL_TX_CHECKS_DISABLE) + "FALSE" : TL_TX_CHECKS_DISABLE_BINARY = 1'b0; + "TRUE" : TL_TX_CHECKS_DISABLE_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute TL_TX_CHECKS_DISABLE on PCIE_2_0 instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", TL_TX_CHECKS_DISABLE); + $finish; + end + endcase + + case (UPCONFIG_CAPABLE) + "FALSE" : UPCONFIG_CAPABLE_BINARY = 1'b0; + "TRUE" : UPCONFIG_CAPABLE_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute UPCONFIG_CAPABLE on PCIE_2_0 instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", UPCONFIG_CAPABLE); + $finish; + end + endcase + + case (UPSTREAM_FACING) + "FALSE" : UPSTREAM_FACING_BINARY = 1'b0; + "TRUE" : UPSTREAM_FACING_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute UPSTREAM_FACING on PCIE_2_0 instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", UPSTREAM_FACING); + $finish; + end + endcase + + case (UR_INV_REQ) + "FALSE" : UR_INV_REQ_BINARY = 1'b0; + "TRUE" : UR_INV_REQ_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute UR_INV_REQ on PCIE_2_0 instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", UR_INV_REQ); + $finish; + end + endcase + + case (VC0_CPL_INFINITE) + "FALSE" : VC0_CPL_INFINITE_BINARY = 1'b0; + "TRUE" : VC0_CPL_INFINITE_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute VC0_CPL_INFINITE on PCIE_2_0 instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", VC0_CPL_INFINITE); + $finish; + end + endcase + + case (VC_CAP_ON) + "FALSE" : VC_CAP_ON_BINARY = 1'b0; + "TRUE" : VC_CAP_ON_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute VC_CAP_ON on PCIE_2_0 instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", VC_CAP_ON); + $finish; + end + endcase + + case (VC_CAP_REJECT_SNOOP_TRANSACTIONS) + "FALSE" : VC_CAP_REJECT_SNOOP_TRANSACTIONS_BINARY = 1'b0; + "TRUE" : VC_CAP_REJECT_SNOOP_TRANSACTIONS_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute VC_CAP_REJECT_SNOOP_TRANSACTIONS on PCIE_2_0 instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", VC_CAP_REJECT_SNOOP_TRANSACTIONS); + $finish; + end + endcase + + case (VSEC_CAP_IS_LINK_VISIBLE) + "FALSE" : VSEC_CAP_IS_LINK_VISIBLE_BINARY = 1'b0; + "TRUE" : VSEC_CAP_IS_LINK_VISIBLE_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute VSEC_CAP_IS_LINK_VISIBLE on PCIE_2_0 instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", VSEC_CAP_IS_LINK_VISIBLE); + $finish; + end + endcase + + case (VSEC_CAP_ON) + "FALSE" : VSEC_CAP_ON_BINARY = 1'b0; + "TRUE" : VSEC_CAP_ON_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute VSEC_CAP_ON on PCIE_2_0 instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", VSEC_CAP_ON); + $finish; + end + endcase + + if ((DEV_CAP_ENDPOINT_L0S_LATENCY >= 0) && (DEV_CAP_ENDPOINT_L0S_LATENCY <= 7)) + DEV_CAP_ENDPOINT_L0S_LATENCY_BINARY = DEV_CAP_ENDPOINT_L0S_LATENCY; + else begin + $display("Attribute Syntax Error : The Attribute DEV_CAP_ENDPOINT_L0S_LATENCY on PCIE_2_0 instance %m is set to %d. Legal values for this attribute are 0 to 7.", DEV_CAP_ENDPOINT_L0S_LATENCY); + $finish; + end + + if ((DEV_CAP_ENDPOINT_L1_LATENCY >= 0) && (DEV_CAP_ENDPOINT_L1_LATENCY <= 7)) + DEV_CAP_ENDPOINT_L1_LATENCY_BINARY = DEV_CAP_ENDPOINT_L1_LATENCY; + else begin + $display("Attribute Syntax Error : The Attribute DEV_CAP_ENDPOINT_L1_LATENCY on PCIE_2_0 instance %m is set to %d. Legal values for this attribute are 0 to 7.", DEV_CAP_ENDPOINT_L1_LATENCY); + $finish; + end + + if ((DEV_CAP_MAX_PAYLOAD_SUPPORTED >= 0) && (DEV_CAP_MAX_PAYLOAD_SUPPORTED <= 7)) + DEV_CAP_MAX_PAYLOAD_SUPPORTED_BINARY = DEV_CAP_MAX_PAYLOAD_SUPPORTED; + else begin + $display("Attribute Syntax Error : The Attribute DEV_CAP_MAX_PAYLOAD_SUPPORTED on PCIE_2_0 instance %m is set to %d. Legal values for this attribute are 0 to 7.", DEV_CAP_MAX_PAYLOAD_SUPPORTED); + $finish; + end + + if ((DEV_CAP_PHANTOM_FUNCTIONS_SUPPORT >= 0) && (DEV_CAP_PHANTOM_FUNCTIONS_SUPPORT <= 3)) + DEV_CAP_PHANTOM_FUNCTIONS_SUPPORT_BINARY = DEV_CAP_PHANTOM_FUNCTIONS_SUPPORT; + else begin + $display("Attribute Syntax Error : The Attribute DEV_CAP_PHANTOM_FUNCTIONS_SUPPORT on PCIE_2_0 instance %m is set to %d. Legal values for this attribute are 0 to 3.", DEV_CAP_PHANTOM_FUNCTIONS_SUPPORT); + $finish; + end + + if ((DEV_CAP_RSVD_14_12 >= 0) && (DEV_CAP_RSVD_14_12 <= 7)) + DEV_CAP_RSVD_14_12_BINARY = DEV_CAP_RSVD_14_12; + else begin + $display("Attribute Syntax Error : The Attribute DEV_CAP_RSVD_14_12 on PCIE_2_0 instance %m is set to %d. Legal values for this attribute are 0 to 7.", DEV_CAP_RSVD_14_12); + $finish; + end + + if ((DEV_CAP_RSVD_17_16 >= 0) && (DEV_CAP_RSVD_17_16 <= 3)) + DEV_CAP_RSVD_17_16_BINARY = DEV_CAP_RSVD_17_16; + else begin + $display("Attribute Syntax Error : The Attribute DEV_CAP_RSVD_17_16 on PCIE_2_0 instance %m is set to %d. Legal values for this attribute are 0 to 3.", DEV_CAP_RSVD_17_16); + $finish; + end + + if ((DEV_CAP_RSVD_31_29 >= 0) && (DEV_CAP_RSVD_31_29 <= 7)) + DEV_CAP_RSVD_31_29_BINARY = DEV_CAP_RSVD_31_29; + else begin + $display("Attribute Syntax Error : The Attribute DEV_CAP_RSVD_31_29 on PCIE_2_0 instance %m is set to %d. Legal values for this attribute are 0 to 7.", DEV_CAP_RSVD_31_29); + $finish; + end + + if ((LINK_CAP_ASPM_SUPPORT >= 0) && (LINK_CAP_ASPM_SUPPORT <= 3)) + LINK_CAP_ASPM_SUPPORT_BINARY = LINK_CAP_ASPM_SUPPORT; + else begin + $display("Attribute Syntax Error : The Attribute LINK_CAP_ASPM_SUPPORT on PCIE_2_0 instance %m is set to %d. Legal values for this attribute are 0 to 3.", LINK_CAP_ASPM_SUPPORT); + $finish; + end + + if ((LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN1 >= 0) && (LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN1 <= 7)) + LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN1_BINARY = LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN1; + else begin + $display("Attribute Syntax Error : The Attribute LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN1 on PCIE_2_0 instance %m is set to %d. Legal values for this attribute are 0 to 7.", LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN1); + $finish; + end + + if ((LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN2 >= 0) && (LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN2 <= 7)) + LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN2_BINARY = LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN2; + else begin + $display("Attribute Syntax Error : The Attribute LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN2 on PCIE_2_0 instance %m is set to %d. Legal values for this attribute are 0 to 7.", LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN2); + $finish; + end + + if ((LINK_CAP_L0S_EXIT_LATENCY_GEN1 >= 0) && (LINK_CAP_L0S_EXIT_LATENCY_GEN1 <= 7)) + LINK_CAP_L0S_EXIT_LATENCY_GEN1_BINARY = LINK_CAP_L0S_EXIT_LATENCY_GEN1; + else begin + $display("Attribute Syntax Error : The Attribute LINK_CAP_L0S_EXIT_LATENCY_GEN1 on PCIE_2_0 instance %m is set to %d. Legal values for this attribute are 0 to 7.", LINK_CAP_L0S_EXIT_LATENCY_GEN1); + $finish; + end + + if ((LINK_CAP_L0S_EXIT_LATENCY_GEN2 >= 0) && (LINK_CAP_L0S_EXIT_LATENCY_GEN2 <= 7)) + LINK_CAP_L0S_EXIT_LATENCY_GEN2_BINARY = LINK_CAP_L0S_EXIT_LATENCY_GEN2; + else begin + $display("Attribute Syntax Error : The Attribute LINK_CAP_L0S_EXIT_LATENCY_GEN2 on PCIE_2_0 instance %m is set to %d. Legal values for this attribute are 0 to 7.", LINK_CAP_L0S_EXIT_LATENCY_GEN2); + $finish; + end + + if ((LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN1 >= 0) && (LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN1 <= 7)) + LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN1_BINARY = LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN1; + else begin + $display("Attribute Syntax Error : The Attribute LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN1 on PCIE_2_0 instance %m is set to %d. Legal values for this attribute are 0 to 7.", LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN1); + $finish; + end + + if ((LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN2 >= 0) && (LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN2 <= 7)) + LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN2_BINARY = LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN2; + else begin + $display("Attribute Syntax Error : The Attribute LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN2 on PCIE_2_0 instance %m is set to %d. Legal values for this attribute are 0 to 7.", LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN2); + $finish; + end + + if ((LINK_CAP_L1_EXIT_LATENCY_GEN1 >= 0) && (LINK_CAP_L1_EXIT_LATENCY_GEN1 <= 7)) + LINK_CAP_L1_EXIT_LATENCY_GEN1_BINARY = LINK_CAP_L1_EXIT_LATENCY_GEN1; + else begin + $display("Attribute Syntax Error : The Attribute LINK_CAP_L1_EXIT_LATENCY_GEN1 on PCIE_2_0 instance %m is set to %d. Legal values for this attribute are 0 to 7.", LINK_CAP_L1_EXIT_LATENCY_GEN1); + $finish; + end + + if ((LINK_CAP_L1_EXIT_LATENCY_GEN2 >= 0) && (LINK_CAP_L1_EXIT_LATENCY_GEN2 <= 7)) + LINK_CAP_L1_EXIT_LATENCY_GEN2_BINARY = LINK_CAP_L1_EXIT_LATENCY_GEN2; + else begin + $display("Attribute Syntax Error : The Attribute LINK_CAP_L1_EXIT_LATENCY_GEN2 on PCIE_2_0 instance %m is set to %d. Legal values for this attribute are 0 to 7.", LINK_CAP_L1_EXIT_LATENCY_GEN2); + $finish; + end + + if ((LINK_CAP_RSVD_23_22 >= 0) && (LINK_CAP_RSVD_23_22 <= 3)) + LINK_CAP_RSVD_23_22_BINARY = LINK_CAP_RSVD_23_22; + else begin + $display("Attribute Syntax Error : The Attribute LINK_CAP_RSVD_23_22 on PCIE_2_0 instance %m is set to %d. Legal values for this attribute are 0 to 3.", LINK_CAP_RSVD_23_22); + $finish; + end + + if ((LINK_CONTROL_RCB >= 0) && (LINK_CONTROL_RCB <= 1)) + LINK_CONTROL_RCB_BINARY = LINK_CONTROL_RCB; + else begin + $display("Attribute Syntax Error : The Attribute LINK_CONTROL_RCB on PCIE_2_0 instance %m is set to %d. Legal values for this attribute are 0 to 1.", LINK_CONTROL_RCB); + $finish; + end + + if ((LL_ACK_TIMEOUT_FUNC >= 0) && (LL_ACK_TIMEOUT_FUNC <= 3)) + LL_ACK_TIMEOUT_FUNC_BINARY = LL_ACK_TIMEOUT_FUNC; + else begin + $display("Attribute Syntax Error : The Attribute LL_ACK_TIMEOUT_FUNC on PCIE_2_0 instance %m is set to %d. Legal values for this attribute are 0 to 3.", LL_ACK_TIMEOUT_FUNC); + $finish; + end + + if ((LL_REPLAY_TIMEOUT_FUNC >= 0) && (LL_REPLAY_TIMEOUT_FUNC <= 3)) + LL_REPLAY_TIMEOUT_FUNC_BINARY = LL_REPLAY_TIMEOUT_FUNC; + else begin + $display("Attribute Syntax Error : The Attribute LL_REPLAY_TIMEOUT_FUNC on PCIE_2_0 instance %m is set to %d. Legal values for this attribute are 0 to 3.", LL_REPLAY_TIMEOUT_FUNC); + $finish; + end + + if ((MSIX_CAP_PBA_BIR >= 0) && (MSIX_CAP_PBA_BIR <= 7)) + MSIX_CAP_PBA_BIR_BINARY = MSIX_CAP_PBA_BIR; + else begin + $display("Attribute Syntax Error : The Attribute MSIX_CAP_PBA_BIR on PCIE_2_0 instance %m is set to %d. Legal values for this attribute are 0 to 7.", MSIX_CAP_PBA_BIR); + $finish; + end + + if ((MSIX_CAP_TABLE_BIR >= 0) && (MSIX_CAP_TABLE_BIR <= 7)) + MSIX_CAP_TABLE_BIR_BINARY = MSIX_CAP_TABLE_BIR; + else begin + $display("Attribute Syntax Error : The Attribute MSIX_CAP_TABLE_BIR on PCIE_2_0 instance %m is set to %d. Legal values for this attribute are 0 to 7.", MSIX_CAP_TABLE_BIR); + $finish; + end + + if ((MSI_CAP_MULTIMSGCAP >= 0) && (MSI_CAP_MULTIMSGCAP <= 7)) + MSI_CAP_MULTIMSGCAP_BINARY = MSI_CAP_MULTIMSGCAP; + else begin + $display("Attribute Syntax Error : The Attribute MSI_CAP_MULTIMSGCAP on PCIE_2_0 instance %m is set to %d. Legal values for this attribute are 0 to 7.", MSI_CAP_MULTIMSGCAP); + $finish; + end + + if ((MSI_CAP_MULTIMSG_EXTENSION >= 0) && (MSI_CAP_MULTIMSG_EXTENSION <= 1)) + MSI_CAP_MULTIMSG_EXTENSION_BINARY = MSI_CAP_MULTIMSG_EXTENSION; + else begin + $display("Attribute Syntax Error : The Attribute MSI_CAP_MULTIMSG_EXTENSION on PCIE_2_0 instance %m is set to %d. Legal values for this attribute are 0 to 1.", MSI_CAP_MULTIMSG_EXTENSION); + $finish; + end + + if ((N_FTS_COMCLK_GEN1 >= 0) && (N_FTS_COMCLK_GEN1 <= 255)) + N_FTS_COMCLK_GEN1_BINARY = N_FTS_COMCLK_GEN1; + else begin + $display("Attribute Syntax Error : The Attribute N_FTS_COMCLK_GEN1 on PCIE_2_0 instance %m is set to %d. Legal values for this attribute are 0 to 255.", N_FTS_COMCLK_GEN1); + $finish; + end + + if ((N_FTS_COMCLK_GEN2 >= 0) && (N_FTS_COMCLK_GEN2 <= 255)) + N_FTS_COMCLK_GEN2_BINARY = N_FTS_COMCLK_GEN2; + else begin + $display("Attribute Syntax Error : The Attribute N_FTS_COMCLK_GEN2 on PCIE_2_0 instance %m is set to %d. Legal values for this attribute are 0 to 255.", N_FTS_COMCLK_GEN2); + $finish; + end + + if ((N_FTS_GEN1 >= 0) && (N_FTS_GEN1 <= 255)) + N_FTS_GEN1_BINARY = N_FTS_GEN1; + else begin + $display("Attribute Syntax Error : The Attribute N_FTS_GEN1 on PCIE_2_0 instance %m is set to %d. Legal values for this attribute are 0 to 255.", N_FTS_GEN1); + $finish; + end + + if ((N_FTS_GEN2 >= 0) && (N_FTS_GEN2 <= 255)) + N_FTS_GEN2_BINARY = N_FTS_GEN2; + else begin + $display("Attribute Syntax Error : The Attribute N_FTS_GEN2 on PCIE_2_0 instance %m is set to %d. Legal values for this attribute are 0 to 255.", N_FTS_GEN2); + $finish; + end + + if ((PCIE_CAP_RSVD_15_14 >= 0) && (PCIE_CAP_RSVD_15_14 <= 3)) + PCIE_CAP_RSVD_15_14_BINARY = PCIE_CAP_RSVD_15_14; + else begin + $display("Attribute Syntax Error : The Attribute PCIE_CAP_RSVD_15_14 on PCIE_2_0 instance %m is set to %d. Legal values for this attribute are 0 to 3.", PCIE_CAP_RSVD_15_14); + $finish; + end + + if ((PCIE_REVISION >= 0) && (PCIE_REVISION <= 15)) + PCIE_REVISION_BINARY = PCIE_REVISION; + else begin + $display("Attribute Syntax Error : The Attribute PCIE_REVISION on PCIE_2_0 instance %m is set to %d. Legal values for this attribute are 0 to 15.", PCIE_REVISION); + $finish; + end + + if ((PGL0_LANE >= 0) && (PGL0_LANE <= 7)) + PGL0_LANE_BINARY = PGL0_LANE; + else begin + $display("Attribute Syntax Error : The Attribute PGL0_LANE on PCIE_2_0 instance %m is set to %d. Legal values for this attribute are 0 to 7.", PGL0_LANE); + $finish; + end + + if ((PGL1_LANE >= 0) && (PGL1_LANE <= 7)) + PGL1_LANE_BINARY = PGL1_LANE; + else begin + $display("Attribute Syntax Error : The Attribute PGL1_LANE on PCIE_2_0 instance %m is set to %d. Legal values for this attribute are 0 to 7.", PGL1_LANE); + $finish; + end + + if ((PGL2_LANE >= 0) && (PGL2_LANE <= 7)) + PGL2_LANE_BINARY = PGL2_LANE; + else begin + $display("Attribute Syntax Error : The Attribute PGL2_LANE on PCIE_2_0 instance %m is set to %d. Legal values for this attribute are 0 to 7.", PGL2_LANE); + $finish; + end + + if ((PGL3_LANE >= 0) && (PGL3_LANE <= 7)) + PGL3_LANE_BINARY = PGL3_LANE; + else begin + $display("Attribute Syntax Error : The Attribute PGL3_LANE on PCIE_2_0 instance %m is set to %d. Legal values for this attribute are 0 to 7.", PGL3_LANE); + $finish; + end + + if ((PGL4_LANE >= 0) && (PGL4_LANE <= 7)) + PGL4_LANE_BINARY = PGL4_LANE; + else begin + $display("Attribute Syntax Error : The Attribute PGL4_LANE on PCIE_2_0 instance %m is set to %d. Legal values for this attribute are 0 to 7.", PGL4_LANE); + $finish; + end + + if ((PGL5_LANE >= 0) && (PGL5_LANE <= 7)) + PGL5_LANE_BINARY = PGL5_LANE; + else begin + $display("Attribute Syntax Error : The Attribute PGL5_LANE on PCIE_2_0 instance %m is set to %d. Legal values for this attribute are 0 to 7.", PGL5_LANE); + $finish; + end + + if ((PGL6_LANE >= 0) && (PGL6_LANE <= 7)) + PGL6_LANE_BINARY = PGL6_LANE; + else begin + $display("Attribute Syntax Error : The Attribute PGL6_LANE on PCIE_2_0 instance %m is set to %d. Legal values for this attribute are 0 to 7.", PGL6_LANE); + $finish; + end + + if ((PGL7_LANE >= 0) && (PGL7_LANE <= 7)) + PGL7_LANE_BINARY = PGL7_LANE; + else begin + $display("Attribute Syntax Error : The Attribute PGL7_LANE on PCIE_2_0 instance %m is set to %d. Legal values for this attribute are 0 to 7.", PGL7_LANE); + $finish; + end + + if ((PL_AUTO_CONFIG >= 0) && (PL_AUTO_CONFIG <= 7)) + PL_AUTO_CONFIG_BINARY = PL_AUTO_CONFIG; + else begin + $display("Attribute Syntax Error : The Attribute PL_AUTO_CONFIG on PCIE_2_0 instance %m is set to %d. Legal values for this attribute are 0 to 7.", PL_AUTO_CONFIG); + $finish; + end + + if ((PM_CAP_AUXCURRENT >= 0) && (PM_CAP_AUXCURRENT <= 7)) + PM_CAP_AUXCURRENT_BINARY = PM_CAP_AUXCURRENT; + else begin + $display("Attribute Syntax Error : The Attribute PM_CAP_AUXCURRENT on PCIE_2_0 instance %m is set to %d. Legal values for this attribute are 0 to 7.", PM_CAP_AUXCURRENT); + $finish; + end + + if ((PM_CAP_RSVD_04 >= 0) && (PM_CAP_RSVD_04 <= 1)) + PM_CAP_RSVD_04_BINARY = PM_CAP_RSVD_04; + else begin + $display("Attribute Syntax Error : The Attribute PM_CAP_RSVD_04 on PCIE_2_0 instance %m is set to %d. Legal values for this attribute are 0 to 1.", PM_CAP_RSVD_04); + $finish; + end + + if ((PM_CAP_VERSION >= 0) && (PM_CAP_VERSION <= 7)) + PM_CAP_VERSION_BINARY = PM_CAP_VERSION; + else begin + $display("Attribute Syntax Error : The Attribute PM_CAP_VERSION on PCIE_2_0 instance %m is set to %d. Legal values for this attribute are 0 to 7.", PM_CAP_VERSION); + $finish; + end + + if ((RECRC_CHK >= 0) && (RECRC_CHK <= 3)) + RECRC_CHK_BINARY = RECRC_CHK; + else begin + $display("Attribute Syntax Error : The Attribute RECRC_CHK on PCIE_2_0 instance %m is set to %d. Legal values for this attribute are 0 to 3.", RECRC_CHK); + $finish; + end + + if ((SLOT_CAP_SLOT_POWER_LIMIT_SCALE >= 0) && (SLOT_CAP_SLOT_POWER_LIMIT_SCALE <= 3)) + SLOT_CAP_SLOT_POWER_LIMIT_SCALE_BINARY = SLOT_CAP_SLOT_POWER_LIMIT_SCALE; + else begin + $display("Attribute Syntax Error : The Attribute SLOT_CAP_SLOT_POWER_LIMIT_SCALE on PCIE_2_0 instance %m is set to %d. Legal values for this attribute are 0 to 3.", SLOT_CAP_SLOT_POWER_LIMIT_SCALE); + $finish; + end + + if ((SPARE_BIT0 >= 0) && (SPARE_BIT0 <= 1)) + SPARE_BIT0_BINARY = SPARE_BIT0; + else begin + $display("Attribute Syntax Error : The Attribute SPARE_BIT0 on PCIE_2_0 instance %m is set to %d. Legal values for this attribute are 0 to 1.", SPARE_BIT0); + $finish; + end + + if ((SPARE_BIT1 >= 0) && (SPARE_BIT1 <= 1)) + SPARE_BIT1_BINARY = SPARE_BIT1; + else begin + $display("Attribute Syntax Error : The Attribute SPARE_BIT1 on PCIE_2_0 instance %m is set to %d. Legal values for this attribute are 0 to 1.", SPARE_BIT1); + $finish; + end + + if ((SPARE_BIT2 >= 0) && (SPARE_BIT2 <= 1)) + SPARE_BIT2_BINARY = SPARE_BIT2; + else begin + $display("Attribute Syntax Error : The Attribute SPARE_BIT2 on PCIE_2_0 instance %m is set to %d. Legal values for this attribute are 0 to 1.", SPARE_BIT2); + $finish; + end + + if ((SPARE_BIT3 >= 0) && (SPARE_BIT3 <= 1)) + SPARE_BIT3_BINARY = SPARE_BIT3; + else begin + $display("Attribute Syntax Error : The Attribute SPARE_BIT3 on PCIE_2_0 instance %m is set to %d. Legal values for this attribute are 0 to 1.", SPARE_BIT3); + $finish; + end + + if ((SPARE_BIT4 >= 0) && (SPARE_BIT4 <= 1)) + SPARE_BIT4_BINARY = SPARE_BIT4; + else begin + $display("Attribute Syntax Error : The Attribute SPARE_BIT4 on PCIE_2_0 instance %m is set to %d. Legal values for this attribute are 0 to 1.", SPARE_BIT4); + $finish; + end + + if ((SPARE_BIT5 >= 0) && (SPARE_BIT5 <= 1)) + SPARE_BIT5_BINARY = SPARE_BIT5; + else begin + $display("Attribute Syntax Error : The Attribute SPARE_BIT5 on PCIE_2_0 instance %m is set to %d. Legal values for this attribute are 0 to 1.", SPARE_BIT5); + $finish; + end + + if ((SPARE_BIT6 >= 0) && (SPARE_BIT6 <= 1)) + SPARE_BIT6_BINARY = SPARE_BIT6; + else begin + $display("Attribute Syntax Error : The Attribute SPARE_BIT6 on PCIE_2_0 instance %m is set to %d. Legal values for this attribute are 0 to 1.", SPARE_BIT6); + $finish; + end + + if ((SPARE_BIT7 >= 0) && (SPARE_BIT7 <= 1)) + SPARE_BIT7_BINARY = SPARE_BIT7; + else begin + $display("Attribute Syntax Error : The Attribute SPARE_BIT7 on PCIE_2_0 instance %m is set to %d. Legal values for this attribute are 0 to 1.", SPARE_BIT7); + $finish; + end + + if ((SPARE_BIT8 >= 0) && (SPARE_BIT8 <= 1)) + SPARE_BIT8_BINARY = SPARE_BIT8; + else begin + $display("Attribute Syntax Error : The Attribute SPARE_BIT8 on PCIE_2_0 instance %m is set to %d. Legal values for this attribute are 0 to 1.", SPARE_BIT8); + $finish; + end + + if ((TL_RX_RAM_RADDR_LATENCY >= 0) && (TL_RX_RAM_RADDR_LATENCY <= 1)) + TL_RX_RAM_RADDR_LATENCY_BINARY = TL_RX_RAM_RADDR_LATENCY; + else begin + $display("Attribute Syntax Error : The Attribute TL_RX_RAM_RADDR_LATENCY on PCIE_2_0 instance %m is set to %d. Legal values for this attribute are 0 to 1.", TL_RX_RAM_RADDR_LATENCY); + $finish; + end + + if ((TL_RX_RAM_RDATA_LATENCY >= 0) && (TL_RX_RAM_RDATA_LATENCY <= 3)) + TL_RX_RAM_RDATA_LATENCY_BINARY = TL_RX_RAM_RDATA_LATENCY; + else begin + $display("Attribute Syntax Error : The Attribute TL_RX_RAM_RDATA_LATENCY on PCIE_2_0 instance %m is set to %d. Legal values for this attribute are 0 to 3.", TL_RX_RAM_RDATA_LATENCY); + $finish; + end + + if ((TL_RX_RAM_WRITE_LATENCY >= 0) && (TL_RX_RAM_WRITE_LATENCY <= 1)) + TL_RX_RAM_WRITE_LATENCY_BINARY = TL_RX_RAM_WRITE_LATENCY; + else begin + $display("Attribute Syntax Error : The Attribute TL_RX_RAM_WRITE_LATENCY on PCIE_2_0 instance %m is set to %d. Legal values for this attribute are 0 to 1.", TL_RX_RAM_WRITE_LATENCY); + $finish; + end + + if ((TL_TX_RAM_RADDR_LATENCY >= 0) && (TL_TX_RAM_RADDR_LATENCY <= 1)) + TL_TX_RAM_RADDR_LATENCY_BINARY = TL_TX_RAM_RADDR_LATENCY; + else begin + $display("Attribute Syntax Error : The Attribute TL_TX_RAM_RADDR_LATENCY on PCIE_2_0 instance %m is set to %d. Legal values for this attribute are 0 to 1.", TL_TX_RAM_RADDR_LATENCY); + $finish; + end + + if ((TL_TX_RAM_RDATA_LATENCY >= 0) && (TL_TX_RAM_RDATA_LATENCY <= 3)) + TL_TX_RAM_RDATA_LATENCY_BINARY = TL_TX_RAM_RDATA_LATENCY; + else begin + $display("Attribute Syntax Error : The Attribute TL_TX_RAM_RDATA_LATENCY on PCIE_2_0 instance %m is set to %d. Legal values for this attribute are 0 to 3.", TL_TX_RAM_RDATA_LATENCY); + $finish; + end + + if ((TL_TX_RAM_WRITE_LATENCY >= 0) && (TL_TX_RAM_WRITE_LATENCY <= 1)) + TL_TX_RAM_WRITE_LATENCY_BINARY = TL_TX_RAM_WRITE_LATENCY; + else begin + $display("Attribute Syntax Error : The Attribute TL_TX_RAM_WRITE_LATENCY on PCIE_2_0 instance %m is set to %d. Legal values for this attribute are 0 to 1.", TL_TX_RAM_WRITE_LATENCY); + $finish; + end + + if ((USER_CLK_FREQ >= 0) && (USER_CLK_FREQ <= 7)) + USER_CLK_FREQ_BINARY = USER_CLK_FREQ; + else begin + $display("Attribute Syntax Error : The Attribute USER_CLK_FREQ on PCIE_2_0 instance %m is set to %d. Legal values for this attribute are 0 to 7.", USER_CLK_FREQ); + $finish; + end + + if ((VC0_TOTAL_CREDITS_CD >= 0) && (VC0_TOTAL_CREDITS_CD <= 2047)) + VC0_TOTAL_CREDITS_CD_BINARY = VC0_TOTAL_CREDITS_CD; + else begin + $display("Attribute Syntax Error : The Attribute VC0_TOTAL_CREDITS_CD on PCIE_2_0 instance %m is set to %d. Legal values for this attribute are 0 to 2047.", VC0_TOTAL_CREDITS_CD); + $finish; + end + + if ((VC0_TOTAL_CREDITS_CH >= 0) && (VC0_TOTAL_CREDITS_CH <= 127)) + VC0_TOTAL_CREDITS_CH_BINARY = VC0_TOTAL_CREDITS_CH; + else begin + $display("Attribute Syntax Error : The Attribute VC0_TOTAL_CREDITS_CH on PCIE_2_0 instance %m is set to %d. Legal values for this attribute are 0 to 127.", VC0_TOTAL_CREDITS_CH); + $finish; + end + + if ((VC0_TOTAL_CREDITS_NPH >= 0) && (VC0_TOTAL_CREDITS_NPH <= 127)) + VC0_TOTAL_CREDITS_NPH_BINARY = VC0_TOTAL_CREDITS_NPH; + else begin + $display("Attribute Syntax Error : The Attribute VC0_TOTAL_CREDITS_NPH on PCIE_2_0 instance %m is set to %d. Legal values for this attribute are 0 to 127.", VC0_TOTAL_CREDITS_NPH); + $finish; + end + + if ((VC0_TOTAL_CREDITS_PD >= 0) && (VC0_TOTAL_CREDITS_PD <= 2047)) + VC0_TOTAL_CREDITS_PD_BINARY = VC0_TOTAL_CREDITS_PD; + else begin + $display("Attribute Syntax Error : The Attribute VC0_TOTAL_CREDITS_PD on PCIE_2_0 instance %m is set to %d. Legal values for this attribute are 0 to 2047.", VC0_TOTAL_CREDITS_PD); + $finish; + end + + if ((VC0_TOTAL_CREDITS_PH >= 0) && (VC0_TOTAL_CREDITS_PH <= 127)) + VC0_TOTAL_CREDITS_PH_BINARY = VC0_TOTAL_CREDITS_PH; + else begin + $display("Attribute Syntax Error : The Attribute VC0_TOTAL_CREDITS_PH on PCIE_2_0 instance %m is set to %d. Legal values for this attribute are 0 to 127.", VC0_TOTAL_CREDITS_PH); + $finish; + end + + if ((VC0_TX_LASTPACKET >= 0) && (VC0_TX_LASTPACKET <= 31)) + VC0_TX_LASTPACKET_BINARY = VC0_TX_LASTPACKET; + else begin + $display("Attribute Syntax Error : The Attribute VC0_TX_LASTPACKET on PCIE_2_0 instance %m is set to %d. Legal values for this attribute are 0 to 31.", VC0_TX_LASTPACKET); + $finish; + end + + end + + wire [11:0] delay_DBGVECC; + wire [11:0] delay_PLDBGVEC; + wire [11:0] delay_TRNFCCPLD; + wire [11:0] delay_TRNFCNPD; + wire [11:0] delay_TRNFCPD; + wire [12:0] delay_MIMRXRADDR; + wire [12:0] delay_MIMRXWADDR; + wire [12:0] delay_MIMTXRADDR; + wire [12:0] delay_MIMTXWADDR; + wire [15:0] delay_CFGMSGDATA; + wire [15:0] delay_DRPDO; + wire [15:0] delay_PIPETX0DATA; + wire [15:0] delay_PIPETX1DATA; + wire [15:0] delay_PIPETX2DATA; + wire [15:0] delay_PIPETX3DATA; + wire [15:0] delay_PIPETX4DATA; + wire [15:0] delay_PIPETX5DATA; + wire [15:0] delay_PIPETX6DATA; + wire [15:0] delay_PIPETX7DATA; + wire [1:0] delay_CFGLINKCONTROLASPMCONTROL; + wire [1:0] delay_CFGLINKSTATUSCURRENTSPEED; + wire [1:0] delay_CFGPMCSRPOWERSTATE; + wire [1:0] delay_PIPETX0CHARISK; + wire [1:0] delay_PIPETX0POWERDOWN; + wire [1:0] delay_PIPETX1CHARISK; + wire [1:0] delay_PIPETX1POWERDOWN; + wire [1:0] delay_PIPETX2CHARISK; + wire [1:0] delay_PIPETX2POWERDOWN; + wire [1:0] delay_PIPETX3CHARISK; + wire [1:0] delay_PIPETX3POWERDOWN; + wire [1:0] delay_PIPETX4CHARISK; + wire [1:0] delay_PIPETX4POWERDOWN; + wire [1:0] delay_PIPETX5CHARISK; + wire [1:0] delay_PIPETX5POWERDOWN; + wire [1:0] delay_PIPETX6CHARISK; + wire [1:0] delay_PIPETX6POWERDOWN; + wire [1:0] delay_PIPETX7CHARISK; + wire [1:0] delay_PIPETX7POWERDOWN; + wire [1:0] delay_PLLANEREVERSALMODE; + wire [1:0] delay_PLRXPMSTATE; + wire [1:0] delay_PLSELLNKWIDTH; + wire [2:0] delay_CFGDEVCONTROLMAXPAYLOAD; + wire [2:0] delay_CFGDEVCONTROLMAXREADREQ; + wire [2:0] delay_CFGINTERRUPTMMENABLE; + wire [2:0] delay_CFGPCIELINKSTATE; + wire [2:0] delay_PIPETXMARGIN; + wire [2:0] delay_PLINITIALLINKWIDTH; + wire [2:0] delay_PLTXPMSTATE; + wire [31:0] delay_CFGDO; + wire [31:0] delay_TRNRDLLPDATA; + wire [3:0] delay_CFGDEVCONTROL2CPLTIMEOUTVAL; + wire [3:0] delay_CFGLINKSTATUSNEGOTIATEDWIDTH; + wire [5:0] delay_PLLTSSMSTATE; + wire [5:0] delay_TRNTBUFAV; + wire [63:0] delay_DBGVECA; + wire [63:0] delay_DBGVECB; + wire [63:0] delay_TRNRD; + wire [67:0] delay_MIMRXWDATA; + wire [68:0] delay_MIMTXWDATA; + wire [6:0] delay_CFGTRANSACTIONADDR; + wire [6:0] delay_CFGVCTCVCMAP; + wire [6:0] delay_TRNRBARHITN; + wire [7:0] delay_CFGINTERRUPTDO; + wire [7:0] delay_TRNFCCPLH; + wire [7:0] delay_TRNFCNPH; + wire [7:0] delay_TRNFCPH; + wire delay_CFGAERECRCCHECKEN; + wire delay_CFGAERECRCGENEN; + wire delay_CFGCOMMANDBUSMASTERENABLE; + wire delay_CFGCOMMANDINTERRUPTDISABLE; + wire delay_CFGCOMMANDIOENABLE; + wire delay_CFGCOMMANDMEMENABLE; + wire delay_CFGCOMMANDSERREN; + wire delay_CFGDEVCONTROL2CPLTIMEOUTDIS; + wire delay_CFGDEVCONTROLAUXPOWEREN; + wire delay_CFGDEVCONTROLCORRERRREPORTINGEN; + wire delay_CFGDEVCONTROLENABLERO; + wire delay_CFGDEVCONTROLEXTTAGEN; + wire delay_CFGDEVCONTROLFATALERRREPORTINGEN; + wire delay_CFGDEVCONTROLNONFATALREPORTINGEN; + wire delay_CFGDEVCONTROLNOSNOOPEN; + wire delay_CFGDEVCONTROLPHANTOMEN; + wire delay_CFGDEVCONTROLURERRREPORTINGEN; + wire delay_CFGDEVSTATUSCORRERRDETECTED; + wire delay_CFGDEVSTATUSFATALERRDETECTED; + wire delay_CFGDEVSTATUSNONFATALERRDETECTED; + wire delay_CFGDEVSTATUSURDETECTED; + wire delay_CFGERRAERHEADERLOGSETN; + wire delay_CFGERRCPLRDYN; + wire delay_CFGINTERRUPTMSIENABLE; + wire delay_CFGINTERRUPTMSIXENABLE; + wire delay_CFGINTERRUPTMSIXFM; + wire delay_CFGINTERRUPTRDYN; + wire delay_CFGLINKCONTROLAUTOBANDWIDTHINTEN; + wire delay_CFGLINKCONTROLBANDWIDTHINTEN; + wire delay_CFGLINKCONTROLCLOCKPMEN; + wire delay_CFGLINKCONTROLCOMMONCLOCK; + wire delay_CFGLINKCONTROLEXTENDEDSYNC; + wire delay_CFGLINKCONTROLHWAUTOWIDTHDIS; + wire delay_CFGLINKCONTROLLINKDISABLE; + wire delay_CFGLINKCONTROLRCB; + wire delay_CFGLINKCONTROLRETRAINLINK; + wire delay_CFGLINKSTATUSAUTOBANDWIDTHSTATUS; + wire delay_CFGLINKSTATUSBANDWITHSTATUS; + wire delay_CFGLINKSTATUSDLLACTIVE; + wire delay_CFGLINKSTATUSLINKTRAINING; + wire delay_CFGMSGRECEIVED; + wire delay_CFGMSGRECEIVEDASSERTINTA; + wire delay_CFGMSGRECEIVEDASSERTINTB; + wire delay_CFGMSGRECEIVEDASSERTINTC; + wire delay_CFGMSGRECEIVEDASSERTINTD; + wire delay_CFGMSGRECEIVEDDEASSERTINTA; + wire delay_CFGMSGRECEIVEDDEASSERTINTB; + wire delay_CFGMSGRECEIVEDDEASSERTINTC; + wire delay_CFGMSGRECEIVEDDEASSERTINTD; + wire delay_CFGMSGRECEIVEDERRCOR; + wire delay_CFGMSGRECEIVEDERRFATAL; + wire delay_CFGMSGRECEIVEDERRNONFATAL; + wire delay_CFGMSGRECEIVEDPMASNAK; + wire delay_CFGMSGRECEIVEDPMETO; + wire delay_CFGMSGRECEIVEDPMETOACK; + wire delay_CFGMSGRECEIVEDPMPME; + wire delay_CFGMSGRECEIVEDSETSLOTPOWERLIMIT; + wire delay_CFGMSGRECEIVEDUNLOCK; + wire delay_CFGPMCSRPMEEN; + wire delay_CFGPMCSRPMESTATUS; + wire delay_CFGPMRCVASREQL1N; + wire delay_CFGPMRCVENTERL1N; + wire delay_CFGPMRCVENTERL23N; + wire delay_CFGPMRCVREQACKN; + wire delay_CFGRDWRDONEN; + wire delay_CFGSLOTCONTROLELECTROMECHILCTLPULSE; + wire delay_CFGTRANSACTION; + wire delay_CFGTRANSACTIONTYPE; + wire delay_DBGSCLRA; + wire delay_DBGSCLRB; + wire delay_DBGSCLRC; + wire delay_DBGSCLRD; + wire delay_DBGSCLRE; + wire delay_DBGSCLRF; + wire delay_DBGSCLRG; + wire delay_DBGSCLRH; + wire delay_DBGSCLRI; + wire delay_DBGSCLRJ; + wire delay_DBGSCLRK; + wire delay_DRPDRDY; + wire delay_LL2BADDLLPERRN; + wire delay_LL2BADTLPERRN; + wire delay_LL2PROTOCOLERRN; + wire delay_LL2REPLAYROERRN; + wire delay_LL2REPLAYTOERRN; + wire delay_LL2SUSPENDOKN; + wire delay_LL2TFCINIT1SEQN; + wire delay_LL2TFCINIT2SEQN; + wire delay_LNKCLKEN; + wire delay_MIMRXRCE; + wire delay_MIMRXREN; + wire delay_MIMRXWEN; + wire delay_MIMTXRCE; + wire delay_MIMTXREN; + wire delay_MIMTXWEN; + wire delay_PIPERX0POLARITY; + wire delay_PIPERX1POLARITY; + wire delay_PIPERX2POLARITY; + wire delay_PIPERX3POLARITY; + wire delay_PIPERX4POLARITY; + wire delay_PIPERX5POLARITY; + wire delay_PIPERX6POLARITY; + wire delay_PIPERX7POLARITY; + wire delay_PIPETX0COMPLIANCE; + wire delay_PIPETX0ELECIDLE; + wire delay_PIPETX1COMPLIANCE; + wire delay_PIPETX1ELECIDLE; + wire delay_PIPETX2COMPLIANCE; + wire delay_PIPETX2ELECIDLE; + wire delay_PIPETX3COMPLIANCE; + wire delay_PIPETX3ELECIDLE; + wire delay_PIPETX4COMPLIANCE; + wire delay_PIPETX4ELECIDLE; + wire delay_PIPETX5COMPLIANCE; + wire delay_PIPETX5ELECIDLE; + wire delay_PIPETX6COMPLIANCE; + wire delay_PIPETX6ELECIDLE; + wire delay_PIPETX7COMPLIANCE; + wire delay_PIPETX7ELECIDLE; + wire delay_PIPETXDEEMPH; + wire delay_PIPETXRATE; + wire delay_PIPETXRCVRDET; + wire delay_PIPETXRESET; + wire delay_PL2LINKUPN; + wire delay_PL2RECEIVERERRN; + wire delay_PL2RECOVERYN; + wire delay_PL2RXELECIDLE; + wire delay_PL2SUSPENDOK; + wire delay_PLLINKGEN2CAP; + wire delay_PLLINKPARTNERGEN2SUPPORTED; + wire delay_PLLINKUPCFGCAP; + wire delay_PLPHYLNKUPN; + wire delay_PLRECEIVEDHOTRST; + wire delay_PLSELLNKRATE; + wire delay_RECEIVEDFUNCLVLRSTN; + wire delay_TL2ASPMSUSPENDCREDITCHECKOKN; + wire delay_TL2ASPMSUSPENDREQN; + wire delay_TL2PPMSUSPENDOKN; + wire delay_TRNLNKUPN; + wire delay_TRNRDLLPSRCRDYN; + wire delay_TRNRECRCERRN; + wire delay_TRNREOFN; + wire delay_TRNRERRFWDN; + wire delay_TRNRREMN; + wire delay_TRNRSOFN; + wire delay_TRNRSRCDSCN; + wire delay_TRNRSRCRDYN; + wire delay_TRNTCFGREQN; + wire delay_TRNTDLLPDSTRDYN; + wire delay_TRNTDSTRDYN; + wire delay_TRNTERRDROPN; + wire delay_USERRSTN; + + wire [127:0] delay_CFGERRAERHEADERLOG; + wire [15:0] delay_DRPDI; + wire [15:0] delay_PIPERX0DATA; + wire [15:0] delay_PIPERX1DATA; + wire [15:0] delay_PIPERX2DATA; + wire [15:0] delay_PIPERX3DATA; + wire [15:0] delay_PIPERX4DATA; + wire [15:0] delay_PIPERX5DATA; + wire [15:0] delay_PIPERX6DATA; + wire [15:0] delay_PIPERX7DATA; + wire [1:0] delay_DBGMODE; + wire [1:0] delay_PIPERX0CHARISK; + wire [1:0] delay_PIPERX1CHARISK; + wire [1:0] delay_PIPERX2CHARISK; + wire [1:0] delay_PIPERX3CHARISK; + wire [1:0] delay_PIPERX4CHARISK; + wire [1:0] delay_PIPERX5CHARISK; + wire [1:0] delay_PIPERX6CHARISK; + wire [1:0] delay_PIPERX7CHARISK; + wire [1:0] delay_PLDIRECTEDLINKCHANGE; + wire [1:0] delay_PLDIRECTEDLINKWIDTH; + wire [2:0] delay_CFGDSFUNCTIONNUMBER; + wire [2:0] delay_PIPERX0STATUS; + wire [2:0] delay_PIPERX1STATUS; + wire [2:0] delay_PIPERX2STATUS; + wire [2:0] delay_PIPERX3STATUS; + wire [2:0] delay_PIPERX4STATUS; + wire [2:0] delay_PIPERX5STATUS; + wire [2:0] delay_PIPERX6STATUS; + wire [2:0] delay_PIPERX7STATUS; + wire [2:0] delay_PLDBGMODE; + wire [2:0] delay_TRNFCSEL; + wire [31:0] delay_CFGDI; + wire [31:0] delay_TRNTDLLPDATA; + wire [3:0] delay_CFGBYTEENN; + wire [47:0] delay_CFGERRTLPCPLHEADER; + wire [4:0] delay_CFGDSDEVICENUMBER; + wire [4:0] delay_PL2DIRECTEDLSTATE; + wire [63:0] delay_CFGDSN; + wire [63:0] delay_TRNTD; + wire [67:0] delay_MIMRXRDATA; + wire [68:0] delay_MIMTXRDATA; + wire [7:0] delay_CFGDSBUSNUMBER; + wire [7:0] delay_CFGINTERRUPTDI; + wire [7:0] delay_CFGPORTNUMBER; + wire [8:0] delay_DRPDADDR; + wire [9:0] delay_CFGDWADDR; + wire delay_CFGERRACSN; + wire delay_CFGERRCORN; + wire delay_CFGERRCPLABORTN; + wire delay_CFGERRCPLTIMEOUTN; + wire delay_CFGERRCPLUNEXPECTN; + wire delay_CFGERRECRCN; + wire delay_CFGERRLOCKEDN; + wire delay_CFGERRPOSTEDN; + wire delay_CFGERRURN; + wire delay_CFGINTERRUPTASSERTN; + wire delay_CFGINTERRUPTN; + wire delay_CFGPMDIRECTASPML1N; + wire delay_CFGPMSENDPMACKN; + wire delay_CFGPMSENDPMETON; + wire delay_CFGPMSENDPMNAKN; + wire delay_CFGPMTURNOFFOKN; + wire delay_CFGPMWAKEN; + wire delay_CFGRDENN; + wire delay_CFGTRNPENDINGN; + wire delay_CFGWRENN; + wire delay_CFGWRREADONLYN; + wire delay_CFGWRRW1CASRWN; + wire delay_CMRSTN; + wire delay_CMSTICKYRSTN; + wire delay_DBGSUBMODE; + wire delay_DLRSTN; + wire delay_DRPCLK; + wire delay_DRPDEN; + wire delay_DRPDWE; + wire delay_FUNCLVLRSTN; + wire delay_LL2SENDASREQL1N; + wire delay_LL2SENDENTERL1N; + wire delay_LL2SENDENTERL23N; + wire delay_LL2SUSPENDNOWN; + wire delay_LL2TLPRCVN; + wire delay_PIPECLK; + wire delay_PIPERX0CHANISALIGNED; + wire delay_PIPERX0ELECIDLE; + wire delay_PIPERX0PHYSTATUS; + wire delay_PIPERX0VALID; + wire delay_PIPERX1CHANISALIGNED; + wire delay_PIPERX1ELECIDLE; + wire delay_PIPERX1PHYSTATUS; + wire delay_PIPERX1VALID; + wire delay_PIPERX2CHANISALIGNED; + wire delay_PIPERX2ELECIDLE; + wire delay_PIPERX2PHYSTATUS; + wire delay_PIPERX2VALID; + wire delay_PIPERX3CHANISALIGNED; + wire delay_PIPERX3ELECIDLE; + wire delay_PIPERX3PHYSTATUS; + wire delay_PIPERX3VALID; + wire delay_PIPERX4CHANISALIGNED; + wire delay_PIPERX4ELECIDLE; + wire delay_PIPERX4PHYSTATUS; + wire delay_PIPERX4VALID; + wire delay_PIPERX5CHANISALIGNED; + wire delay_PIPERX5ELECIDLE; + wire delay_PIPERX5PHYSTATUS; + wire delay_PIPERX5VALID; + wire delay_PIPERX6CHANISALIGNED; + wire delay_PIPERX6ELECIDLE; + wire delay_PIPERX6PHYSTATUS; + wire delay_PIPERX6VALID; + wire delay_PIPERX7CHANISALIGNED; + wire delay_PIPERX7ELECIDLE; + wire delay_PIPERX7PHYSTATUS; + wire delay_PIPERX7VALID; + wire delay_PLDIRECTEDLINKAUTON; + wire delay_PLDIRECTEDLINKSPEED; + wire delay_PLDOWNSTREAMDEEMPHSOURCE; + wire delay_PLRSTN; + wire delay_PLTRANSMITHOTRST; + wire delay_PLUPSTREAMPREFERDEEMPH; + wire delay_SYSRSTN; + wire delay_TL2ASPMSUSPENDCREDITCHECKN; + wire delay_TL2PPMSUSPENDREQN; + wire delay_TLRSTN; + wire delay_TRNRDSTRDYN; + wire delay_TRNRNPOKN; + wire delay_TRNTCFGGNTN; + wire delay_TRNTDLLPSRCRDYN; + wire delay_TRNTECRCGENN; + wire delay_TRNTEOFN; + wire delay_TRNTERRFWDN; + wire delay_TRNTREMN; + wire delay_TRNTSOFN; + wire delay_TRNTSRCDSCN; + wire delay_TRNTSRCRDYN; + wire delay_TRNTSTRN; + wire delay_USERCLK; + + assign #(out_delay) CFGAERECRCCHECKEN = delay_CFGAERECRCCHECKEN; + assign #(out_delay) CFGAERECRCGENEN = delay_CFGAERECRCGENEN; + assign #(out_delay) CFGCOMMANDBUSMASTERENABLE = delay_CFGCOMMANDBUSMASTERENABLE; + assign #(out_delay) CFGCOMMANDINTERRUPTDISABLE = delay_CFGCOMMANDINTERRUPTDISABLE; + assign #(out_delay) CFGCOMMANDIOENABLE = delay_CFGCOMMANDIOENABLE; + assign #(out_delay) CFGCOMMANDMEMENABLE = delay_CFGCOMMANDMEMENABLE; + assign #(out_delay) CFGCOMMANDSERREN = delay_CFGCOMMANDSERREN; + assign #(out_delay) CFGDEVCONTROL2CPLTIMEOUTDIS = delay_CFGDEVCONTROL2CPLTIMEOUTDIS; + assign #(out_delay) CFGDEVCONTROL2CPLTIMEOUTVAL = delay_CFGDEVCONTROL2CPLTIMEOUTVAL; + assign #(out_delay) CFGDEVCONTROLAUXPOWEREN = delay_CFGDEVCONTROLAUXPOWEREN; + assign #(out_delay) CFGDEVCONTROLCORRERRREPORTINGEN = delay_CFGDEVCONTROLCORRERRREPORTINGEN; + assign #(out_delay) CFGDEVCONTROLENABLERO = delay_CFGDEVCONTROLENABLERO; + assign #(out_delay) CFGDEVCONTROLEXTTAGEN = delay_CFGDEVCONTROLEXTTAGEN; + assign #(out_delay) CFGDEVCONTROLFATALERRREPORTINGEN = delay_CFGDEVCONTROLFATALERRREPORTINGEN; + assign #(out_delay) CFGDEVCONTROLMAXPAYLOAD = delay_CFGDEVCONTROLMAXPAYLOAD; + assign #(out_delay) CFGDEVCONTROLMAXREADREQ = delay_CFGDEVCONTROLMAXREADREQ; + assign #(out_delay) CFGDEVCONTROLNONFATALREPORTINGEN = delay_CFGDEVCONTROLNONFATALREPORTINGEN; + assign #(out_delay) CFGDEVCONTROLNOSNOOPEN = delay_CFGDEVCONTROLNOSNOOPEN; + assign #(out_delay) CFGDEVCONTROLPHANTOMEN = delay_CFGDEVCONTROLPHANTOMEN; + assign #(out_delay) CFGDEVCONTROLURERRREPORTINGEN = delay_CFGDEVCONTROLURERRREPORTINGEN; + assign #(out_delay) CFGDEVSTATUSCORRERRDETECTED = delay_CFGDEVSTATUSCORRERRDETECTED; + assign #(out_delay) CFGDEVSTATUSFATALERRDETECTED = delay_CFGDEVSTATUSFATALERRDETECTED; + assign #(out_delay) CFGDEVSTATUSNONFATALERRDETECTED = delay_CFGDEVSTATUSNONFATALERRDETECTED; + assign #(out_delay) CFGDEVSTATUSURDETECTED = delay_CFGDEVSTATUSURDETECTED; + assign #(out_delay) CFGDO = delay_CFGDO; + assign #(out_delay) CFGERRAERHEADERLOGSETN = delay_CFGERRAERHEADERLOGSETN; + assign #(out_delay) CFGERRCPLRDYN = delay_CFGERRCPLRDYN; + assign #(out_delay) CFGINTERRUPTDO = delay_CFGINTERRUPTDO; + assign #(out_delay) CFGINTERRUPTMMENABLE = delay_CFGINTERRUPTMMENABLE; + assign #(out_delay) CFGINTERRUPTMSIENABLE = delay_CFGINTERRUPTMSIENABLE; + assign #(out_delay) CFGINTERRUPTMSIXENABLE = delay_CFGINTERRUPTMSIXENABLE; + assign #(out_delay) CFGINTERRUPTMSIXFM = delay_CFGINTERRUPTMSIXFM; + assign #(out_delay) CFGINTERRUPTRDYN = delay_CFGINTERRUPTRDYN; + assign #(out_delay) CFGLINKCONTROLASPMCONTROL = delay_CFGLINKCONTROLASPMCONTROL; + assign #(out_delay) CFGLINKCONTROLAUTOBANDWIDTHINTEN = delay_CFGLINKCONTROLAUTOBANDWIDTHINTEN; + assign #(out_delay) CFGLINKCONTROLBANDWIDTHINTEN = delay_CFGLINKCONTROLBANDWIDTHINTEN; + assign #(out_delay) CFGLINKCONTROLCLOCKPMEN = delay_CFGLINKCONTROLCLOCKPMEN; + assign #(out_delay) CFGLINKCONTROLCOMMONCLOCK = delay_CFGLINKCONTROLCOMMONCLOCK; + assign #(out_delay) CFGLINKCONTROLEXTENDEDSYNC = delay_CFGLINKCONTROLEXTENDEDSYNC; + assign #(out_delay) CFGLINKCONTROLHWAUTOWIDTHDIS = delay_CFGLINKCONTROLHWAUTOWIDTHDIS; + assign #(out_delay) CFGLINKCONTROLLINKDISABLE = delay_CFGLINKCONTROLLINKDISABLE; + assign #(out_delay) CFGLINKCONTROLRCB = delay_CFGLINKCONTROLRCB; + assign #(out_delay) CFGLINKCONTROLRETRAINLINK = delay_CFGLINKCONTROLRETRAINLINK; + assign #(out_delay) CFGLINKSTATUSAUTOBANDWIDTHSTATUS = delay_CFGLINKSTATUSAUTOBANDWIDTHSTATUS; + assign #(out_delay) CFGLINKSTATUSBANDWITHSTATUS = delay_CFGLINKSTATUSBANDWITHSTATUS; + assign #(out_delay) CFGLINKSTATUSCURRENTSPEED = delay_CFGLINKSTATUSCURRENTSPEED; + assign #(out_delay) CFGLINKSTATUSDLLACTIVE = delay_CFGLINKSTATUSDLLACTIVE; + assign #(out_delay) CFGLINKSTATUSLINKTRAINING = delay_CFGLINKSTATUSLINKTRAINING; + assign #(out_delay) CFGLINKSTATUSNEGOTIATEDWIDTH = delay_CFGLINKSTATUSNEGOTIATEDWIDTH; + assign #(out_delay) CFGMSGDATA = delay_CFGMSGDATA; + assign #(out_delay) CFGMSGRECEIVED = delay_CFGMSGRECEIVED; + assign #(out_delay) CFGMSGRECEIVEDASSERTINTA = delay_CFGMSGRECEIVEDASSERTINTA; + assign #(out_delay) CFGMSGRECEIVEDASSERTINTB = delay_CFGMSGRECEIVEDASSERTINTB; + assign #(out_delay) CFGMSGRECEIVEDASSERTINTC = delay_CFGMSGRECEIVEDASSERTINTC; + assign #(out_delay) CFGMSGRECEIVEDASSERTINTD = delay_CFGMSGRECEIVEDASSERTINTD; + assign #(out_delay) CFGMSGRECEIVEDDEASSERTINTA = delay_CFGMSGRECEIVEDDEASSERTINTA; + assign #(out_delay) CFGMSGRECEIVEDDEASSERTINTB = delay_CFGMSGRECEIVEDDEASSERTINTB; + assign #(out_delay) CFGMSGRECEIVEDDEASSERTINTC = delay_CFGMSGRECEIVEDDEASSERTINTC; + assign #(out_delay) CFGMSGRECEIVEDDEASSERTINTD = delay_CFGMSGRECEIVEDDEASSERTINTD; + assign #(out_delay) CFGMSGRECEIVEDERRCOR = delay_CFGMSGRECEIVEDERRCOR; + assign #(out_delay) CFGMSGRECEIVEDERRFATAL = delay_CFGMSGRECEIVEDERRFATAL; + assign #(out_delay) CFGMSGRECEIVEDERRNONFATAL = delay_CFGMSGRECEIVEDERRNONFATAL; + assign #(out_delay) CFGMSGRECEIVEDPMASNAK = delay_CFGMSGRECEIVEDPMASNAK; + assign #(out_delay) CFGMSGRECEIVEDPMETO = delay_CFGMSGRECEIVEDPMETO; + assign #(out_delay) CFGMSGRECEIVEDPMETOACK = delay_CFGMSGRECEIVEDPMETOACK; + assign #(out_delay) CFGMSGRECEIVEDPMPME = delay_CFGMSGRECEIVEDPMPME; + assign #(out_delay) CFGMSGRECEIVEDSETSLOTPOWERLIMIT = delay_CFGMSGRECEIVEDSETSLOTPOWERLIMIT; + assign #(out_delay) CFGMSGRECEIVEDUNLOCK = delay_CFGMSGRECEIVEDUNLOCK; + assign #(out_delay) CFGPCIELINKSTATE = delay_CFGPCIELINKSTATE; + assign #(out_delay) CFGPMCSRPMEEN = delay_CFGPMCSRPMEEN; + assign #(out_delay) CFGPMCSRPMESTATUS = delay_CFGPMCSRPMESTATUS; + assign #(out_delay) CFGPMCSRPOWERSTATE = delay_CFGPMCSRPOWERSTATE; + assign #(out_delay) CFGPMRCVASREQL1N = delay_CFGPMRCVASREQL1N; + assign #(out_delay) CFGPMRCVENTERL1N = delay_CFGPMRCVENTERL1N; + assign #(out_delay) CFGPMRCVENTERL23N = delay_CFGPMRCVENTERL23N; + assign #(out_delay) CFGPMRCVREQACKN = delay_CFGPMRCVREQACKN; + assign #(out_delay) CFGRDWRDONEN = delay_CFGRDWRDONEN; + assign #(out_delay) CFGSLOTCONTROLELECTROMECHILCTLPULSE = delay_CFGSLOTCONTROLELECTROMECHILCTLPULSE; + assign #(out_delay) CFGTRANSACTION = delay_CFGTRANSACTION; + assign #(out_delay) CFGTRANSACTIONADDR = delay_CFGTRANSACTIONADDR; + assign #(out_delay) CFGTRANSACTIONTYPE = delay_CFGTRANSACTIONTYPE; + assign #(out_delay) CFGVCTCVCMAP = delay_CFGVCTCVCMAP; + assign #(out_delay) DBGSCLRA = delay_DBGSCLRA; + assign #(out_delay) DBGSCLRB = delay_DBGSCLRB; + assign #(out_delay) DBGSCLRC = delay_DBGSCLRC; + assign #(out_delay) DBGSCLRD = delay_DBGSCLRD; + assign #(out_delay) DBGSCLRE = delay_DBGSCLRE; + assign #(out_delay) DBGSCLRF = delay_DBGSCLRF; + assign #(out_delay) DBGSCLRG = delay_DBGSCLRG; + assign #(out_delay) DBGSCLRH = delay_DBGSCLRH; + assign #(out_delay) DBGSCLRI = delay_DBGSCLRI; + assign #(out_delay) DBGSCLRJ = delay_DBGSCLRJ; + assign #(out_delay) DBGSCLRK = delay_DBGSCLRK; + assign #(out_delay) DBGVECA = delay_DBGVECA; + assign #(out_delay) DBGVECB = delay_DBGVECB; + assign #(out_delay) DBGVECC = delay_DBGVECC; + assign #(out_delay) DRPDO = delay_DRPDO; + assign #(out_delay) DRPDRDY = delay_DRPDRDY; + assign #(out_delay) LL2BADDLLPERRN = delay_LL2BADDLLPERRN; + assign #(out_delay) LL2BADTLPERRN = delay_LL2BADTLPERRN; + assign #(out_delay) LL2PROTOCOLERRN = delay_LL2PROTOCOLERRN; + assign #(out_delay) LL2REPLAYROERRN = delay_LL2REPLAYROERRN; + assign #(out_delay) LL2REPLAYTOERRN = delay_LL2REPLAYTOERRN; + assign #(out_delay) LL2SUSPENDOKN = delay_LL2SUSPENDOKN; + assign #(out_delay) LL2TFCINIT1SEQN = delay_LL2TFCINIT1SEQN; + assign #(out_delay) LL2TFCINIT2SEQN = delay_LL2TFCINIT2SEQN; + assign #(out_delay) LNKCLKEN = delay_LNKCLKEN; + assign #(out_delay) MIMRXRADDR = delay_MIMRXRADDR; + assign #(out_delay) MIMRXRCE = delay_MIMRXRCE; + assign #(out_delay) MIMRXREN = delay_MIMRXREN; + assign #(out_delay) MIMRXWADDR = delay_MIMRXWADDR; + assign #(out_delay) MIMRXWDATA = delay_MIMRXWDATA; + assign #(out_delay) MIMRXWEN = delay_MIMRXWEN; + assign #(out_delay) MIMTXRADDR = delay_MIMTXRADDR; + assign #(out_delay) MIMTXRCE = delay_MIMTXRCE; + assign #(out_delay) MIMTXREN = delay_MIMTXREN; + assign #(out_delay) MIMTXWADDR = delay_MIMTXWADDR; + assign #(out_delay) MIMTXWDATA = delay_MIMTXWDATA; + assign #(out_delay) MIMTXWEN = delay_MIMTXWEN; + assign #(out_delay) PIPERX0POLARITY = delay_PIPERX0POLARITY; + assign #(out_delay) PIPERX1POLARITY = delay_PIPERX1POLARITY; + assign #(out_delay) PIPERX2POLARITY = delay_PIPERX2POLARITY; + assign #(out_delay) PIPERX3POLARITY = delay_PIPERX3POLARITY; + assign #(out_delay) PIPERX4POLARITY = delay_PIPERX4POLARITY; + assign #(out_delay) PIPERX5POLARITY = delay_PIPERX5POLARITY; + assign #(out_delay) PIPERX6POLARITY = delay_PIPERX6POLARITY; + assign #(out_delay) PIPERX7POLARITY = delay_PIPERX7POLARITY; + assign #(out_delay) PIPETX0CHARISK = delay_PIPETX0CHARISK; + assign #(out_delay) PIPETX0COMPLIANCE = delay_PIPETX0COMPLIANCE; + assign #(out_delay) PIPETX0DATA = delay_PIPETX0DATA; + assign #(out_delay) PIPETX0ELECIDLE = delay_PIPETX0ELECIDLE; + assign #(out_delay) PIPETX0POWERDOWN = delay_PIPETX0POWERDOWN; + assign #(out_delay) PIPETX1CHARISK = delay_PIPETX1CHARISK; + assign #(out_delay) PIPETX1COMPLIANCE = delay_PIPETX1COMPLIANCE; + assign #(out_delay) PIPETX1DATA = delay_PIPETX1DATA; + assign #(out_delay) PIPETX1ELECIDLE = delay_PIPETX1ELECIDLE; + assign #(out_delay) PIPETX1POWERDOWN = delay_PIPETX1POWERDOWN; + assign #(out_delay) PIPETX2CHARISK = delay_PIPETX2CHARISK; + assign #(out_delay) PIPETX2COMPLIANCE = delay_PIPETX2COMPLIANCE; + assign #(out_delay) PIPETX2DATA = delay_PIPETX2DATA; + assign #(out_delay) PIPETX2ELECIDLE = delay_PIPETX2ELECIDLE; + assign #(out_delay) PIPETX2POWERDOWN = delay_PIPETX2POWERDOWN; + assign #(out_delay) PIPETX3CHARISK = delay_PIPETX3CHARISK; + assign #(out_delay) PIPETX3COMPLIANCE = delay_PIPETX3COMPLIANCE; + assign #(out_delay) PIPETX3DATA = delay_PIPETX3DATA; + assign #(out_delay) PIPETX3ELECIDLE = delay_PIPETX3ELECIDLE; + assign #(out_delay) PIPETX3POWERDOWN = delay_PIPETX3POWERDOWN; + assign #(out_delay) PIPETX4CHARISK = delay_PIPETX4CHARISK; + assign #(out_delay) PIPETX4COMPLIANCE = delay_PIPETX4COMPLIANCE; + assign #(out_delay) PIPETX4DATA = delay_PIPETX4DATA; + assign #(out_delay) PIPETX4ELECIDLE = delay_PIPETX4ELECIDLE; + assign #(out_delay) PIPETX4POWERDOWN = delay_PIPETX4POWERDOWN; + assign #(out_delay) PIPETX5CHARISK = delay_PIPETX5CHARISK; + assign #(out_delay) PIPETX5COMPLIANCE = delay_PIPETX5COMPLIANCE; + assign #(out_delay) PIPETX5DATA = delay_PIPETX5DATA; + assign #(out_delay) PIPETX5ELECIDLE = delay_PIPETX5ELECIDLE; + assign #(out_delay) PIPETX5POWERDOWN = delay_PIPETX5POWERDOWN; + assign #(out_delay) PIPETX6CHARISK = delay_PIPETX6CHARISK; + assign #(out_delay) PIPETX6COMPLIANCE = delay_PIPETX6COMPLIANCE; + assign #(out_delay) PIPETX6DATA = delay_PIPETX6DATA; + assign #(out_delay) PIPETX6ELECIDLE = delay_PIPETX6ELECIDLE; + assign #(out_delay) PIPETX6POWERDOWN = delay_PIPETX6POWERDOWN; + assign #(out_delay) PIPETX7CHARISK = delay_PIPETX7CHARISK; + assign #(out_delay) PIPETX7COMPLIANCE = delay_PIPETX7COMPLIANCE; + assign #(out_delay) PIPETX7DATA = delay_PIPETX7DATA; + assign #(out_delay) PIPETX7ELECIDLE = delay_PIPETX7ELECIDLE; + assign #(out_delay) PIPETX7POWERDOWN = delay_PIPETX7POWERDOWN; + assign #(out_delay) PIPETXDEEMPH = delay_PIPETXDEEMPH; + assign #(out_delay) PIPETXMARGIN = delay_PIPETXMARGIN; + assign #(out_delay) PIPETXRATE = delay_PIPETXRATE; + assign #(out_delay) PIPETXRCVRDET = delay_PIPETXRCVRDET; + assign #(out_delay) PIPETXRESET = delay_PIPETXRESET; + assign #(out_delay) PL2LINKUPN = delay_PL2LINKUPN; + assign #(out_delay) PL2RECEIVERERRN = delay_PL2RECEIVERERRN; + assign #(out_delay) PL2RECOVERYN = delay_PL2RECOVERYN; + assign #(out_delay) PL2RXELECIDLE = delay_PL2RXELECIDLE; + assign #(out_delay) PL2SUSPENDOK = delay_PL2SUSPENDOK; + assign #(out_delay) PLDBGVEC = delay_PLDBGVEC; + assign #(out_delay) PLINITIALLINKWIDTH = delay_PLINITIALLINKWIDTH; + assign #(out_delay) PLLANEREVERSALMODE = delay_PLLANEREVERSALMODE; + assign #(out_delay) PLLINKGEN2CAP = delay_PLLINKGEN2CAP; + assign #(out_delay) PLLINKPARTNERGEN2SUPPORTED = delay_PLLINKPARTNERGEN2SUPPORTED; + assign #(out_delay) PLLINKUPCFGCAP = delay_PLLINKUPCFGCAP; + assign #(out_delay) PLLTSSMSTATE = delay_PLLTSSMSTATE; + assign #(out_delay) PLPHYLNKUPN = delay_PLPHYLNKUPN; + assign #(out_delay) PLRECEIVEDHOTRST = delay_PLRECEIVEDHOTRST; + assign #(out_delay) PLRXPMSTATE = delay_PLRXPMSTATE; + assign #(out_delay) PLSELLNKRATE = delay_PLSELLNKRATE; + assign #(out_delay) PLSELLNKWIDTH = delay_PLSELLNKWIDTH; + assign #(out_delay) PLTXPMSTATE = delay_PLTXPMSTATE; + assign #(out_delay) RECEIVEDFUNCLVLRSTN = delay_RECEIVEDFUNCLVLRSTN; + assign #(out_delay) TL2ASPMSUSPENDCREDITCHECKOKN = delay_TL2ASPMSUSPENDCREDITCHECKOKN; + assign #(out_delay) TL2ASPMSUSPENDREQN = delay_TL2ASPMSUSPENDREQN; + assign #(out_delay) TL2PPMSUSPENDOKN = delay_TL2PPMSUSPENDOKN; + assign #(out_delay) TRNFCCPLD = delay_TRNFCCPLD; + assign #(out_delay) TRNFCCPLH = delay_TRNFCCPLH; + assign #(out_delay) TRNFCNPD = delay_TRNFCNPD; + assign #(out_delay) TRNFCNPH = delay_TRNFCNPH; + assign #(out_delay) TRNFCPD = delay_TRNFCPD; + assign #(out_delay) TRNFCPH = delay_TRNFCPH; + assign #(out_delay) TRNLNKUPN = delay_TRNLNKUPN; + assign #(out_delay) TRNRBARHITN = delay_TRNRBARHITN; + assign #(out_delay) TRNRD = delay_TRNRD; + assign #(out_delay) TRNRDLLPDATA = delay_TRNRDLLPDATA; + assign #(out_delay) TRNRDLLPSRCRDYN = delay_TRNRDLLPSRCRDYN; + assign #(out_delay) TRNRECRCERRN = delay_TRNRECRCERRN; + assign #(out_delay) TRNREOFN = delay_TRNREOFN; + assign #(out_delay) TRNRERRFWDN = delay_TRNRERRFWDN; + assign #(out_delay) TRNRREMN = delay_TRNRREMN; + assign #(out_delay) TRNRSOFN = delay_TRNRSOFN; + assign #(out_delay) TRNRSRCDSCN = delay_TRNRSRCDSCN; + assign #(out_delay) TRNRSRCRDYN = delay_TRNRSRCRDYN; + assign #(out_delay) TRNTBUFAV = delay_TRNTBUFAV; + assign #(out_delay) TRNTCFGREQN = delay_TRNTCFGREQN; + assign #(out_delay) TRNTDLLPDSTRDYN = delay_TRNTDLLPDSTRDYN; + assign #(out_delay) TRNTDSTRDYN = delay_TRNTDSTRDYN; + assign #(out_delay) TRNTERRDROPN = delay_TRNTERRDROPN; + assign #(out_delay) USERRSTN = delay_USERRSTN; + + assign #(INCLK_DELAY) delay_DRPCLK = DRPCLK; + assign #(INCLK_DELAY) delay_PIPECLK = PIPECLK; + assign #(INCLK_DELAY) delay_USERCLK = USERCLK; + + assign #(in_delay) delay_CFGBYTEENN = CFGBYTEENN; + assign #(in_delay) delay_CFGDI = CFGDI; + assign #(in_delay) delay_CFGDSBUSNUMBER = CFGDSBUSNUMBER; + assign #(in_delay) delay_CFGDSDEVICENUMBER = CFGDSDEVICENUMBER; + assign #(in_delay) delay_CFGDSFUNCTIONNUMBER = CFGDSFUNCTIONNUMBER; + assign #(in_delay) delay_CFGDSN = CFGDSN; + assign #(in_delay) delay_CFGDWADDR = CFGDWADDR; + assign #(in_delay) delay_CFGERRACSN = CFGERRACSN; + assign #(in_delay) delay_CFGERRAERHEADERLOG = CFGERRAERHEADERLOG; + assign #(in_delay) delay_CFGERRCORN = CFGERRCORN; + assign #(in_delay) delay_CFGERRCPLABORTN = CFGERRCPLABORTN; + assign #(in_delay) delay_CFGERRCPLTIMEOUTN = CFGERRCPLTIMEOUTN; + assign #(in_delay) delay_CFGERRCPLUNEXPECTN = CFGERRCPLUNEXPECTN; + assign #(in_delay) delay_CFGERRECRCN = CFGERRECRCN; + assign #(in_delay) delay_CFGERRLOCKEDN = CFGERRLOCKEDN; + assign #(in_delay) delay_CFGERRPOSTEDN = CFGERRPOSTEDN; + assign #(in_delay) delay_CFGERRTLPCPLHEADER = CFGERRTLPCPLHEADER; + assign #(in_delay) delay_CFGERRURN = CFGERRURN; + assign #(in_delay) delay_CFGINTERRUPTASSERTN = CFGINTERRUPTASSERTN; + assign #(in_delay) delay_CFGINTERRUPTDI = CFGINTERRUPTDI; + assign #(in_delay) delay_CFGINTERRUPTN = CFGINTERRUPTN; + assign #(in_delay) delay_CFGPMDIRECTASPML1N = CFGPMDIRECTASPML1N; + assign #(in_delay) delay_CFGPMSENDPMACKN = CFGPMSENDPMACKN; + assign #(in_delay) delay_CFGPMSENDPMETON = CFGPMSENDPMETON; + assign #(in_delay) delay_CFGPMSENDPMNAKN = CFGPMSENDPMNAKN; + assign #(in_delay) delay_CFGPMTURNOFFOKN = CFGPMTURNOFFOKN; + assign #(in_delay) delay_CFGPMWAKEN = CFGPMWAKEN; + assign #(in_delay) delay_CFGPORTNUMBER = CFGPORTNUMBER; + assign #(in_delay) delay_CFGRDENN = CFGRDENN; + assign #(in_delay) delay_CFGTRNPENDINGN = CFGTRNPENDINGN; + assign #(in_delay) delay_CFGWRENN = CFGWRENN; + assign #(in_delay) delay_CFGWRREADONLYN = CFGWRREADONLYN; + assign #(in_delay) delay_CFGWRRW1CASRWN = CFGWRRW1CASRWN; + assign #(in_delay) delay_CMRSTN = CMRSTN; + assign #(in_delay) delay_CMSTICKYRSTN = CMSTICKYRSTN; + assign #(in_delay) delay_DBGMODE = DBGMODE; + assign #(in_delay) delay_DBGSUBMODE = DBGSUBMODE; + assign #(in_delay) delay_DLRSTN = DLRSTN; + assign #(in_delay) delay_DRPDADDR = DRPDADDR; + assign #(in_delay) delay_DRPDEN = DRPDEN; + assign #(in_delay) delay_DRPDI = DRPDI; + assign #(in_delay) delay_DRPDWE = DRPDWE; + assign #(in_delay) delay_FUNCLVLRSTN = FUNCLVLRSTN; + assign #(in_delay) delay_LL2SENDASREQL1N = LL2SENDASREQL1N; + assign #(in_delay) delay_LL2SENDENTERL1N = LL2SENDENTERL1N; + assign #(in_delay) delay_LL2SENDENTERL23N = LL2SENDENTERL23N; + assign #(in_delay) delay_LL2SUSPENDNOWN = LL2SUSPENDNOWN; + assign #(in_delay) delay_LL2TLPRCVN = LL2TLPRCVN; + assign #(in_delay) delay_MIMRXRDATA = MIMRXRDATA; + assign #(in_delay) delay_MIMTXRDATA = MIMTXRDATA; + assign #(in_delay) delay_PIPERX0CHANISALIGNED = PIPERX0CHANISALIGNED; + assign #(in_delay) delay_PIPERX0CHARISK = PIPERX0CHARISK; + assign #(in_delay) delay_PIPERX0DATA = PIPERX0DATA; + assign #(in_delay) delay_PIPERX0ELECIDLE = PIPERX0ELECIDLE; + assign #(in_delay) delay_PIPERX0PHYSTATUS = PIPERX0PHYSTATUS; + assign #(in_delay) delay_PIPERX0STATUS = PIPERX0STATUS; + assign #(in_delay) delay_PIPERX0VALID = PIPERX0VALID; + assign #(in_delay) delay_PIPERX1CHANISALIGNED = PIPERX1CHANISALIGNED; + assign #(in_delay) delay_PIPERX1CHARISK = PIPERX1CHARISK; + assign #(in_delay) delay_PIPERX1DATA = PIPERX1DATA; + assign #(in_delay) delay_PIPERX1ELECIDLE = PIPERX1ELECIDLE; + assign #(in_delay) delay_PIPERX1PHYSTATUS = PIPERX1PHYSTATUS; + assign #(in_delay) delay_PIPERX1STATUS = PIPERX1STATUS; + assign #(in_delay) delay_PIPERX1VALID = PIPERX1VALID; + assign #(in_delay) delay_PIPERX2CHANISALIGNED = PIPERX2CHANISALIGNED; + assign #(in_delay) delay_PIPERX2CHARISK = PIPERX2CHARISK; + assign #(in_delay) delay_PIPERX2DATA = PIPERX2DATA; + assign #(in_delay) delay_PIPERX2ELECIDLE = PIPERX2ELECIDLE; + assign #(in_delay) delay_PIPERX2PHYSTATUS = PIPERX2PHYSTATUS; + assign #(in_delay) delay_PIPERX2STATUS = PIPERX2STATUS; + assign #(in_delay) delay_PIPERX2VALID = PIPERX2VALID; + assign #(in_delay) delay_PIPERX3CHANISALIGNED = PIPERX3CHANISALIGNED; + assign #(in_delay) delay_PIPERX3CHARISK = PIPERX3CHARISK; + assign #(in_delay) delay_PIPERX3DATA = PIPERX3DATA; + assign #(in_delay) delay_PIPERX3ELECIDLE = PIPERX3ELECIDLE; + assign #(in_delay) delay_PIPERX3PHYSTATUS = PIPERX3PHYSTATUS; + assign #(in_delay) delay_PIPERX3STATUS = PIPERX3STATUS; + assign #(in_delay) delay_PIPERX3VALID = PIPERX3VALID; + assign #(in_delay) delay_PIPERX4CHANISALIGNED = PIPERX4CHANISALIGNED; + assign #(in_delay) delay_PIPERX4CHARISK = PIPERX4CHARISK; + assign #(in_delay) delay_PIPERX4DATA = PIPERX4DATA; + assign #(in_delay) delay_PIPERX4ELECIDLE = PIPERX4ELECIDLE; + assign #(in_delay) delay_PIPERX4PHYSTATUS = PIPERX4PHYSTATUS; + assign #(in_delay) delay_PIPERX4STATUS = PIPERX4STATUS; + assign #(in_delay) delay_PIPERX4VALID = PIPERX4VALID; + assign #(in_delay) delay_PIPERX5CHANISALIGNED = PIPERX5CHANISALIGNED; + assign #(in_delay) delay_PIPERX5CHARISK = PIPERX5CHARISK; + assign #(in_delay) delay_PIPERX5DATA = PIPERX5DATA; + assign #(in_delay) delay_PIPERX5ELECIDLE = PIPERX5ELECIDLE; + assign #(in_delay) delay_PIPERX5PHYSTATUS = PIPERX5PHYSTATUS; + assign #(in_delay) delay_PIPERX5STATUS = PIPERX5STATUS; + assign #(in_delay) delay_PIPERX5VALID = PIPERX5VALID; + assign #(in_delay) delay_PIPERX6CHANISALIGNED = PIPERX6CHANISALIGNED; + assign #(in_delay) delay_PIPERX6CHARISK = PIPERX6CHARISK; + assign #(in_delay) delay_PIPERX6DATA = PIPERX6DATA; + assign #(in_delay) delay_PIPERX6ELECIDLE = PIPERX6ELECIDLE; + assign #(in_delay) delay_PIPERX6PHYSTATUS = PIPERX6PHYSTATUS; + assign #(in_delay) delay_PIPERX6STATUS = PIPERX6STATUS; + assign #(in_delay) delay_PIPERX6VALID = PIPERX6VALID; + assign #(in_delay) delay_PIPERX7CHANISALIGNED = PIPERX7CHANISALIGNED; + assign #(in_delay) delay_PIPERX7CHARISK = PIPERX7CHARISK; + assign #(in_delay) delay_PIPERX7DATA = PIPERX7DATA; + assign #(in_delay) delay_PIPERX7ELECIDLE = PIPERX7ELECIDLE; + assign #(in_delay) delay_PIPERX7PHYSTATUS = PIPERX7PHYSTATUS; + assign #(in_delay) delay_PIPERX7STATUS = PIPERX7STATUS; + assign #(in_delay) delay_PIPERX7VALID = PIPERX7VALID; + assign #(in_delay) delay_PL2DIRECTEDLSTATE = PL2DIRECTEDLSTATE; + assign #(in_delay) delay_PLDBGMODE = PLDBGMODE; + assign #(in_delay) delay_PLDIRECTEDLINKAUTON = PLDIRECTEDLINKAUTON; + assign #(in_delay) delay_PLDIRECTEDLINKCHANGE = PLDIRECTEDLINKCHANGE; + assign #(in_delay) delay_PLDIRECTEDLINKSPEED = PLDIRECTEDLINKSPEED; + assign #(in_delay) delay_PLDIRECTEDLINKWIDTH = PLDIRECTEDLINKWIDTH; + assign #(in_delay) delay_PLDOWNSTREAMDEEMPHSOURCE = PLDOWNSTREAMDEEMPHSOURCE; + assign #(in_delay) delay_PLRSTN = PLRSTN; + assign #(in_delay) delay_PLTRANSMITHOTRST = PLTRANSMITHOTRST; + assign #(in_delay) delay_PLUPSTREAMPREFERDEEMPH = PLUPSTREAMPREFERDEEMPH; + assign #(in_delay) delay_SYSRSTN = SYSRSTN; + assign #(in_delay) delay_TL2ASPMSUSPENDCREDITCHECKN = TL2ASPMSUSPENDCREDITCHECKN; + assign #(in_delay) delay_TL2PPMSUSPENDREQN = TL2PPMSUSPENDREQN; + assign #(in_delay) delay_TLRSTN = TLRSTN; + assign #(in_delay) delay_TRNFCSEL = TRNFCSEL; + assign #(in_delay) delay_TRNRDSTRDYN = TRNRDSTRDYN; + assign #(in_delay) delay_TRNRNPOKN = TRNRNPOKN; + assign #(in_delay) delay_TRNTCFGGNTN = TRNTCFGGNTN; + assign #(in_delay) delay_TRNTD = TRNTD; + assign #(in_delay) delay_TRNTDLLPDATA = TRNTDLLPDATA; + assign #(in_delay) delay_TRNTDLLPSRCRDYN = TRNTDLLPSRCRDYN; + assign #(in_delay) delay_TRNTECRCGENN = TRNTECRCGENN; + assign #(in_delay) delay_TRNTEOFN = TRNTEOFN; + assign #(in_delay) delay_TRNTERRFWDN = TRNTERRFWDN; + assign #(in_delay) delay_TRNTREMN = TRNTREMN; + assign #(in_delay) delay_TRNTSOFN = TRNTSOFN; + assign #(in_delay) delay_TRNTSRCDSCN = TRNTSRCDSCN; + assign #(in_delay) delay_TRNTSRCRDYN = TRNTSRCRDYN; + assign #(in_delay) delay_TRNTSTRN = TRNTSTRN; + + B_PCIE_2_0 #( + .AER_BASE_PTR (AER_BASE_PTR), + .AER_CAP_ECRC_CHECK_CAPABLE (AER_CAP_ECRC_CHECK_CAPABLE), + .AER_CAP_ECRC_GEN_CAPABLE (AER_CAP_ECRC_GEN_CAPABLE), + .AER_CAP_ID (AER_CAP_ID), + .AER_CAP_INT_MSG_NUM_MSI (AER_CAP_INT_MSG_NUM_MSI), + .AER_CAP_INT_MSG_NUM_MSIX (AER_CAP_INT_MSG_NUM_MSIX), + .AER_CAP_NEXTPTR (AER_CAP_NEXTPTR), + .AER_CAP_ON (AER_CAP_ON), + .AER_CAP_PERMIT_ROOTERR_UPDATE (AER_CAP_PERMIT_ROOTERR_UPDATE), + .AER_CAP_VERSION (AER_CAP_VERSION), + .ALLOW_X8_GEN2 (ALLOW_X8_GEN2), + .BAR0 (BAR0), + .BAR1 (BAR1), + .BAR2 (BAR2), + .BAR3 (BAR3), + .BAR4 (BAR4), + .BAR5 (BAR5), + .CAPABILITIES_PTR (CAPABILITIES_PTR), + .CARDBUS_CIS_POINTER (CARDBUS_CIS_POINTER), + .CLASS_CODE (CLASS_CODE), + .CMD_INTX_IMPLEMENTED (CMD_INTX_IMPLEMENTED), + .CPL_TIMEOUT_DISABLE_SUPPORTED (CPL_TIMEOUT_DISABLE_SUPPORTED), + .CPL_TIMEOUT_RANGES_SUPPORTED (CPL_TIMEOUT_RANGES_SUPPORTED), + .CRM_MODULE_RSTS (CRM_MODULE_RSTS), + .DEVICE_ID (DEVICE_ID), + .DEV_CAP_ENABLE_SLOT_PWR_LIMIT_SCALE (DEV_CAP_ENABLE_SLOT_PWR_LIMIT_SCALE), + .DEV_CAP_ENABLE_SLOT_PWR_LIMIT_VALUE (DEV_CAP_ENABLE_SLOT_PWR_LIMIT_VALUE), + .DEV_CAP_ENDPOINT_L0S_LATENCY (DEV_CAP_ENDPOINT_L0S_LATENCY), + .DEV_CAP_ENDPOINT_L1_LATENCY (DEV_CAP_ENDPOINT_L1_LATENCY), + .DEV_CAP_EXT_TAG_SUPPORTED (DEV_CAP_EXT_TAG_SUPPORTED), + .DEV_CAP_FUNCTION_LEVEL_RESET_CAPABLE (DEV_CAP_FUNCTION_LEVEL_RESET_CAPABLE), + .DEV_CAP_MAX_PAYLOAD_SUPPORTED (DEV_CAP_MAX_PAYLOAD_SUPPORTED), + .DEV_CAP_PHANTOM_FUNCTIONS_SUPPORT (DEV_CAP_PHANTOM_FUNCTIONS_SUPPORT), + .DEV_CAP_ROLE_BASED_ERROR (DEV_CAP_ROLE_BASED_ERROR), + .DEV_CAP_RSVD_14_12 (DEV_CAP_RSVD_14_12), + .DEV_CAP_RSVD_17_16 (DEV_CAP_RSVD_17_16), + .DEV_CAP_RSVD_31_29 (DEV_CAP_RSVD_31_29), + .DEV_CONTROL_AUX_POWER_SUPPORTED (DEV_CONTROL_AUX_POWER_SUPPORTED), + .DISABLE_ASPM_L1_TIMER (DISABLE_ASPM_L1_TIMER), + .DISABLE_BAR_FILTERING (DISABLE_BAR_FILTERING), + .DISABLE_ID_CHECK (DISABLE_ID_CHECK), + .DISABLE_LANE_REVERSAL (DISABLE_LANE_REVERSAL), + .DISABLE_RX_TC_FILTER (DISABLE_RX_TC_FILTER), + .DISABLE_SCRAMBLING (DISABLE_SCRAMBLING), + .DNSTREAM_LINK_NUM (DNSTREAM_LINK_NUM), + .DSN_BASE_PTR (DSN_BASE_PTR), + .DSN_CAP_ID (DSN_CAP_ID), + .DSN_CAP_NEXTPTR (DSN_CAP_NEXTPTR), + .DSN_CAP_ON (DSN_CAP_ON), + .DSN_CAP_VERSION (DSN_CAP_VERSION), + .ENABLE_MSG_ROUTE (ENABLE_MSG_ROUTE), + .ENABLE_RX_TD_ECRC_TRIM (ENABLE_RX_TD_ECRC_TRIM), + .ENTER_RVRY_EI_L0 (ENTER_RVRY_EI_L0), + .EXIT_LOOPBACK_ON_EI (EXIT_LOOPBACK_ON_EI), + .EXPANSION_ROM (EXPANSION_ROM), + .EXT_CFG_CAP_PTR (EXT_CFG_CAP_PTR), + .EXT_CFG_XP_CAP_PTR (EXT_CFG_XP_CAP_PTR), + .HEADER_TYPE (HEADER_TYPE), + .INFER_EI (INFER_EI), + .INTERRUPT_PIN (INTERRUPT_PIN), + .IS_SWITCH (IS_SWITCH), + .LAST_CONFIG_DWORD (LAST_CONFIG_DWORD), + .LINK_CAP_ASPM_SUPPORT (LINK_CAP_ASPM_SUPPORT), + .LINK_CAP_CLOCK_POWER_MANAGEMENT (LINK_CAP_CLOCK_POWER_MANAGEMENT), + .LINK_CAP_DLL_LINK_ACTIVE_REPORTING_CAP (LINK_CAP_DLL_LINK_ACTIVE_REPORTING_CAP), + .LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN1 (LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN1), + .LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN2 (LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN2), + .LINK_CAP_L0S_EXIT_LATENCY_GEN1 (LINK_CAP_L0S_EXIT_LATENCY_GEN1), + .LINK_CAP_L0S_EXIT_LATENCY_GEN2 (LINK_CAP_L0S_EXIT_LATENCY_GEN2), + .LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN1 (LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN1), + .LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN2 (LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN2), + .LINK_CAP_L1_EXIT_LATENCY_GEN1 (LINK_CAP_L1_EXIT_LATENCY_GEN1), + .LINK_CAP_L1_EXIT_LATENCY_GEN2 (LINK_CAP_L1_EXIT_LATENCY_GEN2), + .LINK_CAP_LINK_BANDWIDTH_NOTIFICATION_CAP (LINK_CAP_LINK_BANDWIDTH_NOTIFICATION_CAP), + .LINK_CAP_MAX_LINK_SPEED (LINK_CAP_MAX_LINK_SPEED), + .LINK_CAP_MAX_LINK_WIDTH (LINK_CAP_MAX_LINK_WIDTH), + .LINK_CAP_RSVD_23_22 (LINK_CAP_RSVD_23_22), + .LINK_CAP_SURPRISE_DOWN_ERROR_CAPABLE (LINK_CAP_SURPRISE_DOWN_ERROR_CAPABLE), + .LINK_CONTROL_RCB (LINK_CONTROL_RCB), + .LINK_CTRL2_DEEMPHASIS (LINK_CTRL2_DEEMPHASIS), + .LINK_CTRL2_HW_AUTONOMOUS_SPEED_DISABLE (LINK_CTRL2_HW_AUTONOMOUS_SPEED_DISABLE), + .LINK_CTRL2_TARGET_LINK_SPEED (LINK_CTRL2_TARGET_LINK_SPEED), + .LINK_STATUS_SLOT_CLOCK_CONFIG (LINK_STATUS_SLOT_CLOCK_CONFIG), + .LL_ACK_TIMEOUT (LL_ACK_TIMEOUT), + .LL_ACK_TIMEOUT_EN (LL_ACK_TIMEOUT_EN), + .LL_ACK_TIMEOUT_FUNC (LL_ACK_TIMEOUT_FUNC), + .LL_REPLAY_TIMEOUT (LL_REPLAY_TIMEOUT), + .LL_REPLAY_TIMEOUT_EN (LL_REPLAY_TIMEOUT_EN), + .LL_REPLAY_TIMEOUT_FUNC (LL_REPLAY_TIMEOUT_FUNC), + .LTSSM_MAX_LINK_WIDTH (LTSSM_MAX_LINK_WIDTH), + .MSIX_BASE_PTR (MSIX_BASE_PTR), + .MSIX_CAP_ID (MSIX_CAP_ID), + .MSIX_CAP_NEXTPTR (MSIX_CAP_NEXTPTR), + .MSIX_CAP_ON (MSIX_CAP_ON), + .MSIX_CAP_PBA_BIR (MSIX_CAP_PBA_BIR), + .MSIX_CAP_PBA_OFFSET (MSIX_CAP_PBA_OFFSET), + .MSIX_CAP_TABLE_BIR (MSIX_CAP_TABLE_BIR), + .MSIX_CAP_TABLE_OFFSET (MSIX_CAP_TABLE_OFFSET), + .MSIX_CAP_TABLE_SIZE (MSIX_CAP_TABLE_SIZE), + .MSI_BASE_PTR (MSI_BASE_PTR), + .MSI_CAP_64_BIT_ADDR_CAPABLE (MSI_CAP_64_BIT_ADDR_CAPABLE), + .MSI_CAP_ID (MSI_CAP_ID), + .MSI_CAP_MULTIMSGCAP (MSI_CAP_MULTIMSGCAP), + .MSI_CAP_MULTIMSG_EXTENSION (MSI_CAP_MULTIMSG_EXTENSION), + .MSI_CAP_NEXTPTR (MSI_CAP_NEXTPTR), + .MSI_CAP_ON (MSI_CAP_ON), + .MSI_CAP_PER_VECTOR_MASKING_CAPABLE (MSI_CAP_PER_VECTOR_MASKING_CAPABLE), + .N_FTS_COMCLK_GEN1 (N_FTS_COMCLK_GEN1), + .N_FTS_COMCLK_GEN2 (N_FTS_COMCLK_GEN2), + .N_FTS_GEN1 (N_FTS_GEN1), + .N_FTS_GEN2 (N_FTS_GEN2), + .PCIE_BASE_PTR (PCIE_BASE_PTR), + .PCIE_CAP_CAPABILITY_ID (PCIE_CAP_CAPABILITY_ID), + .PCIE_CAP_CAPABILITY_VERSION (PCIE_CAP_CAPABILITY_VERSION), + .PCIE_CAP_DEVICE_PORT_TYPE (PCIE_CAP_DEVICE_PORT_TYPE), + .PCIE_CAP_INT_MSG_NUM (PCIE_CAP_INT_MSG_NUM), + .PCIE_CAP_NEXTPTR (PCIE_CAP_NEXTPTR), + .PCIE_CAP_ON (PCIE_CAP_ON), + .PCIE_CAP_RSVD_15_14 (PCIE_CAP_RSVD_15_14), + .PCIE_CAP_SLOT_IMPLEMENTED (PCIE_CAP_SLOT_IMPLEMENTED), + .PCIE_REVISION (PCIE_REVISION), + .PGL0_LANE (PGL0_LANE), + .PGL1_LANE (PGL1_LANE), + .PGL2_LANE (PGL2_LANE), + .PGL3_LANE (PGL3_LANE), + .PGL4_LANE (PGL4_LANE), + .PGL5_LANE (PGL5_LANE), + .PGL6_LANE (PGL6_LANE), + .PGL7_LANE (PGL7_LANE), + .PL_AUTO_CONFIG (PL_AUTO_CONFIG), + .PL_FAST_TRAIN (PL_FAST_TRAIN), + .PM_BASE_PTR (PM_BASE_PTR), + .PM_CAP_AUXCURRENT (PM_CAP_AUXCURRENT), + .PM_CAP_D1SUPPORT (PM_CAP_D1SUPPORT), + .PM_CAP_D2SUPPORT (PM_CAP_D2SUPPORT), + .PM_CAP_DSI (PM_CAP_DSI), + .PM_CAP_ID (PM_CAP_ID), + .PM_CAP_NEXTPTR (PM_CAP_NEXTPTR), + .PM_CAP_ON (PM_CAP_ON), + .PM_CAP_PMESUPPORT (PM_CAP_PMESUPPORT), + .PM_CAP_PME_CLOCK (PM_CAP_PME_CLOCK), + .PM_CAP_RSVD_04 (PM_CAP_RSVD_04), + .PM_CAP_VERSION (PM_CAP_VERSION), + .PM_CSR_B2B3 (PM_CSR_B2B3), + .PM_CSR_BPCCEN (PM_CSR_BPCCEN), + .PM_CSR_NOSOFTRST (PM_CSR_NOSOFTRST), + .PM_DATA0 (PM_DATA0), + .PM_DATA1 (PM_DATA1), + .PM_DATA2 (PM_DATA2), + .PM_DATA3 (PM_DATA3), + .PM_DATA4 (PM_DATA4), + .PM_DATA5 (PM_DATA5), + .PM_DATA6 (PM_DATA6), + .PM_DATA7 (PM_DATA7), + .PM_DATA_SCALE0 (PM_DATA_SCALE0), + .PM_DATA_SCALE1 (PM_DATA_SCALE1), + .PM_DATA_SCALE2 (PM_DATA_SCALE2), + .PM_DATA_SCALE3 (PM_DATA_SCALE3), + .PM_DATA_SCALE4 (PM_DATA_SCALE4), + .PM_DATA_SCALE5 (PM_DATA_SCALE5), + .PM_DATA_SCALE6 (PM_DATA_SCALE6), + .PM_DATA_SCALE7 (PM_DATA_SCALE7), + .RECRC_CHK (RECRC_CHK), + .RECRC_CHK_TRIM (RECRC_CHK_TRIM), + .REVISION_ID (REVISION_ID), + .ROOT_CAP_CRS_SW_VISIBILITY (ROOT_CAP_CRS_SW_VISIBILITY), + .SELECT_DLL_IF (SELECT_DLL_IF), + .SIM_VERSION (SIM_VERSION), + .SLOT_CAP_ATT_BUTTON_PRESENT (SLOT_CAP_ATT_BUTTON_PRESENT), + .SLOT_CAP_ATT_INDICATOR_PRESENT (SLOT_CAP_ATT_INDICATOR_PRESENT), + .SLOT_CAP_ELEC_INTERLOCK_PRESENT (SLOT_CAP_ELEC_INTERLOCK_PRESENT), + .SLOT_CAP_HOTPLUG_CAPABLE (SLOT_CAP_HOTPLUG_CAPABLE), + .SLOT_CAP_HOTPLUG_SURPRISE (SLOT_CAP_HOTPLUG_SURPRISE), + .SLOT_CAP_MRL_SENSOR_PRESENT (SLOT_CAP_MRL_SENSOR_PRESENT), + .SLOT_CAP_NO_CMD_COMPLETED_SUPPORT (SLOT_CAP_NO_CMD_COMPLETED_SUPPORT), + .SLOT_CAP_PHYSICAL_SLOT_NUM (SLOT_CAP_PHYSICAL_SLOT_NUM), + .SLOT_CAP_POWER_CONTROLLER_PRESENT (SLOT_CAP_POWER_CONTROLLER_PRESENT), + .SLOT_CAP_POWER_INDICATOR_PRESENT (SLOT_CAP_POWER_INDICATOR_PRESENT), + .SLOT_CAP_SLOT_POWER_LIMIT_SCALE (SLOT_CAP_SLOT_POWER_LIMIT_SCALE), + .SLOT_CAP_SLOT_POWER_LIMIT_VALUE (SLOT_CAP_SLOT_POWER_LIMIT_VALUE), + .SPARE_BIT0 (SPARE_BIT0), + .SPARE_BIT1 (SPARE_BIT1), + .SPARE_BIT2 (SPARE_BIT2), + .SPARE_BIT3 (SPARE_BIT3), + .SPARE_BIT4 (SPARE_BIT4), + .SPARE_BIT5 (SPARE_BIT5), + .SPARE_BIT6 (SPARE_BIT6), + .SPARE_BIT7 (SPARE_BIT7), + .SPARE_BIT8 (SPARE_BIT8), + .SPARE_BYTE0 (SPARE_BYTE0), + .SPARE_BYTE1 (SPARE_BYTE1), + .SPARE_BYTE2 (SPARE_BYTE2), + .SPARE_BYTE3 (SPARE_BYTE3), + .SPARE_WORD0 (SPARE_WORD0), + .SPARE_WORD1 (SPARE_WORD1), + .SPARE_WORD2 (SPARE_WORD2), + .SPARE_WORD3 (SPARE_WORD3), + .SUBSYSTEM_ID (SUBSYSTEM_ID), + .SUBSYSTEM_VENDOR_ID (SUBSYSTEM_VENDOR_ID), + .TL_RBYPASS (TL_RBYPASS), + .TL_RX_RAM_RADDR_LATENCY (TL_RX_RAM_RADDR_LATENCY), + .TL_RX_RAM_RDATA_LATENCY (TL_RX_RAM_RDATA_LATENCY), + .TL_RX_RAM_WRITE_LATENCY (TL_RX_RAM_WRITE_LATENCY), + .TL_TFC_DISABLE (TL_TFC_DISABLE), + .TL_TX_CHECKS_DISABLE (TL_TX_CHECKS_DISABLE), + .TL_TX_RAM_RADDR_LATENCY (TL_TX_RAM_RADDR_LATENCY), + .TL_TX_RAM_RDATA_LATENCY (TL_TX_RAM_RDATA_LATENCY), + .TL_TX_RAM_WRITE_LATENCY (TL_TX_RAM_WRITE_LATENCY), + .UPCONFIG_CAPABLE (UPCONFIG_CAPABLE), + .UPSTREAM_FACING (UPSTREAM_FACING), + .UR_INV_REQ (UR_INV_REQ), + .USER_CLK_FREQ (USER_CLK_FREQ), + .VC0_CPL_INFINITE (VC0_CPL_INFINITE), + .VC0_RX_RAM_LIMIT (VC0_RX_RAM_LIMIT), + .VC0_TOTAL_CREDITS_CD (VC0_TOTAL_CREDITS_CD), + .VC0_TOTAL_CREDITS_CH (VC0_TOTAL_CREDITS_CH), + .VC0_TOTAL_CREDITS_NPH (VC0_TOTAL_CREDITS_NPH), + .VC0_TOTAL_CREDITS_PD (VC0_TOTAL_CREDITS_PD), + .VC0_TOTAL_CREDITS_PH (VC0_TOTAL_CREDITS_PH), + .VC0_TX_LASTPACKET (VC0_TX_LASTPACKET), + .VC_BASE_PTR (VC_BASE_PTR), + .VC_CAP_ID (VC_CAP_ID), + .VC_CAP_NEXTPTR (VC_CAP_NEXTPTR), + .VC_CAP_ON (VC_CAP_ON), + .VC_CAP_REJECT_SNOOP_TRANSACTIONS (VC_CAP_REJECT_SNOOP_TRANSACTIONS), + .VC_CAP_VERSION (VC_CAP_VERSION), + .VENDOR_ID (VENDOR_ID), + .VSEC_BASE_PTR (VSEC_BASE_PTR), + .VSEC_CAP_HDR_ID (VSEC_CAP_HDR_ID), + .VSEC_CAP_HDR_LENGTH (VSEC_CAP_HDR_LENGTH), + .VSEC_CAP_HDR_REVISION (VSEC_CAP_HDR_REVISION), + .VSEC_CAP_ID (VSEC_CAP_ID), + .VSEC_CAP_IS_LINK_VISIBLE (VSEC_CAP_IS_LINK_VISIBLE), + .VSEC_CAP_NEXTPTR (VSEC_CAP_NEXTPTR), + .VSEC_CAP_ON (VSEC_CAP_ON), + .VSEC_CAP_VERSION (VSEC_CAP_VERSION)) + + B_PCIE_2_0_INST( + .CFGAERECRCCHECKEN (delay_CFGAERECRCCHECKEN), + .CFGAERECRCGENEN (delay_CFGAERECRCGENEN), + .CFGCOMMANDBUSMASTERENABLE (delay_CFGCOMMANDBUSMASTERENABLE), + .CFGCOMMANDINTERRUPTDISABLE (delay_CFGCOMMANDINTERRUPTDISABLE), + .CFGCOMMANDIOENABLE (delay_CFGCOMMANDIOENABLE), + .CFGCOMMANDMEMENABLE (delay_CFGCOMMANDMEMENABLE), + .CFGCOMMANDSERREN (delay_CFGCOMMANDSERREN), + .CFGDEVCONTROL2CPLTIMEOUTDIS (delay_CFGDEVCONTROL2CPLTIMEOUTDIS), + .CFGDEVCONTROL2CPLTIMEOUTVAL (delay_CFGDEVCONTROL2CPLTIMEOUTVAL), + .CFGDEVCONTROLAUXPOWEREN (delay_CFGDEVCONTROLAUXPOWEREN), + .CFGDEVCONTROLCORRERRREPORTINGEN (delay_CFGDEVCONTROLCORRERRREPORTINGEN), + .CFGDEVCONTROLENABLERO (delay_CFGDEVCONTROLENABLERO), + .CFGDEVCONTROLEXTTAGEN (delay_CFGDEVCONTROLEXTTAGEN), + .CFGDEVCONTROLFATALERRREPORTINGEN (delay_CFGDEVCONTROLFATALERRREPORTINGEN), + .CFGDEVCONTROLMAXPAYLOAD (delay_CFGDEVCONTROLMAXPAYLOAD), + .CFGDEVCONTROLMAXREADREQ (delay_CFGDEVCONTROLMAXREADREQ), + .CFGDEVCONTROLNONFATALREPORTINGEN (delay_CFGDEVCONTROLNONFATALREPORTINGEN), + .CFGDEVCONTROLNOSNOOPEN (delay_CFGDEVCONTROLNOSNOOPEN), + .CFGDEVCONTROLPHANTOMEN (delay_CFGDEVCONTROLPHANTOMEN), + .CFGDEVCONTROLURERRREPORTINGEN (delay_CFGDEVCONTROLURERRREPORTINGEN), + .CFGDEVSTATUSCORRERRDETECTED (delay_CFGDEVSTATUSCORRERRDETECTED), + .CFGDEVSTATUSFATALERRDETECTED (delay_CFGDEVSTATUSFATALERRDETECTED), + .CFGDEVSTATUSNONFATALERRDETECTED (delay_CFGDEVSTATUSNONFATALERRDETECTED), + .CFGDEVSTATUSURDETECTED (delay_CFGDEVSTATUSURDETECTED), + .CFGDO (delay_CFGDO), + .CFGERRAERHEADERLOGSETN (delay_CFGERRAERHEADERLOGSETN), + .CFGERRCPLRDYN (delay_CFGERRCPLRDYN), + .CFGINTERRUPTDO (delay_CFGINTERRUPTDO), + .CFGINTERRUPTMMENABLE (delay_CFGINTERRUPTMMENABLE), + .CFGINTERRUPTMSIENABLE (delay_CFGINTERRUPTMSIENABLE), + .CFGINTERRUPTMSIXENABLE (delay_CFGINTERRUPTMSIXENABLE), + .CFGINTERRUPTMSIXFM (delay_CFGINTERRUPTMSIXFM), + .CFGINTERRUPTRDYN (delay_CFGINTERRUPTRDYN), + .CFGLINKCONTROLASPMCONTROL (delay_CFGLINKCONTROLASPMCONTROL), + .CFGLINKCONTROLAUTOBANDWIDTHINTEN (delay_CFGLINKCONTROLAUTOBANDWIDTHINTEN), + .CFGLINKCONTROLBANDWIDTHINTEN (delay_CFGLINKCONTROLBANDWIDTHINTEN), + .CFGLINKCONTROLCLOCKPMEN (delay_CFGLINKCONTROLCLOCKPMEN), + .CFGLINKCONTROLCOMMONCLOCK (delay_CFGLINKCONTROLCOMMONCLOCK), + .CFGLINKCONTROLEXTENDEDSYNC (delay_CFGLINKCONTROLEXTENDEDSYNC), + .CFGLINKCONTROLHWAUTOWIDTHDIS (delay_CFGLINKCONTROLHWAUTOWIDTHDIS), + .CFGLINKCONTROLLINKDISABLE (delay_CFGLINKCONTROLLINKDISABLE), + .CFGLINKCONTROLRCB (delay_CFGLINKCONTROLRCB), + .CFGLINKCONTROLRETRAINLINK (delay_CFGLINKCONTROLRETRAINLINK), + .CFGLINKSTATUSAUTOBANDWIDTHSTATUS (delay_CFGLINKSTATUSAUTOBANDWIDTHSTATUS), + .CFGLINKSTATUSBANDWITHSTATUS (delay_CFGLINKSTATUSBANDWITHSTATUS), + .CFGLINKSTATUSCURRENTSPEED (delay_CFGLINKSTATUSCURRENTSPEED), + .CFGLINKSTATUSDLLACTIVE (delay_CFGLINKSTATUSDLLACTIVE), + .CFGLINKSTATUSLINKTRAINING (delay_CFGLINKSTATUSLINKTRAINING), + .CFGLINKSTATUSNEGOTIATEDWIDTH (delay_CFGLINKSTATUSNEGOTIATEDWIDTH), + .CFGMSGDATA (delay_CFGMSGDATA), + .CFGMSGRECEIVED (delay_CFGMSGRECEIVED), + .CFGMSGRECEIVEDASSERTINTA (delay_CFGMSGRECEIVEDASSERTINTA), + .CFGMSGRECEIVEDASSERTINTB (delay_CFGMSGRECEIVEDASSERTINTB), + .CFGMSGRECEIVEDASSERTINTC (delay_CFGMSGRECEIVEDASSERTINTC), + .CFGMSGRECEIVEDASSERTINTD (delay_CFGMSGRECEIVEDASSERTINTD), + .CFGMSGRECEIVEDDEASSERTINTA (delay_CFGMSGRECEIVEDDEASSERTINTA), + .CFGMSGRECEIVEDDEASSERTINTB (delay_CFGMSGRECEIVEDDEASSERTINTB), + .CFGMSGRECEIVEDDEASSERTINTC (delay_CFGMSGRECEIVEDDEASSERTINTC), + .CFGMSGRECEIVEDDEASSERTINTD (delay_CFGMSGRECEIVEDDEASSERTINTD), + .CFGMSGRECEIVEDERRCOR (delay_CFGMSGRECEIVEDERRCOR), + .CFGMSGRECEIVEDERRFATAL (delay_CFGMSGRECEIVEDERRFATAL), + .CFGMSGRECEIVEDERRNONFATAL (delay_CFGMSGRECEIVEDERRNONFATAL), + .CFGMSGRECEIVEDPMASNAK (delay_CFGMSGRECEIVEDPMASNAK), + .CFGMSGRECEIVEDPMETO (delay_CFGMSGRECEIVEDPMETO), + .CFGMSGRECEIVEDPMETOACK (delay_CFGMSGRECEIVEDPMETOACK), + .CFGMSGRECEIVEDPMPME (delay_CFGMSGRECEIVEDPMPME), + .CFGMSGRECEIVEDSETSLOTPOWERLIMIT (delay_CFGMSGRECEIVEDSETSLOTPOWERLIMIT), + .CFGMSGRECEIVEDUNLOCK (delay_CFGMSGRECEIVEDUNLOCK), + .CFGPCIELINKSTATE (delay_CFGPCIELINKSTATE), + .CFGPMCSRPMEEN (delay_CFGPMCSRPMEEN), + .CFGPMCSRPMESTATUS(delay_CFGPMCSRPMESTATUS), + .CFGPMCSRPOWERSTATE(delay_CFGPMCSRPOWERSTATE), + .CFGPMRCVASREQL1N (delay_CFGPMRCVASREQL1N), + .CFGPMRCVENTERL1N (delay_CFGPMRCVENTERL1N), + .CFGPMRCVENTERL23N (delay_CFGPMRCVENTERL23N), + .CFGPMRCVREQACKN (delay_CFGPMRCVREQACKN), + .CFGRDWRDONEN (delay_CFGRDWRDONEN), + .CFGSLOTCONTROLELECTROMECHILCTLPULSE (delay_CFGSLOTCONTROLELECTROMECHILCTLPULSE), + .CFGTRANSACTION (delay_CFGTRANSACTION), + .CFGTRANSACTIONADDR (delay_CFGTRANSACTIONADDR), + .CFGTRANSACTIONTYPE (delay_CFGTRANSACTIONTYPE), + .CFGVCTCVCMAP (delay_CFGVCTCVCMAP), + .DBGSCLRA (delay_DBGSCLRA), + .DBGSCLRB (delay_DBGSCLRB), + .DBGSCLRC (delay_DBGSCLRC), + .DBGSCLRD (delay_DBGSCLRD), + .DBGSCLRE (delay_DBGSCLRE), + .DBGSCLRF (delay_DBGSCLRF), + .DBGSCLRG (delay_DBGSCLRG), + .DBGSCLRH (delay_DBGSCLRH), + .DBGSCLRI (delay_DBGSCLRI), + .DBGSCLRJ (delay_DBGSCLRJ), + .DBGSCLRK (delay_DBGSCLRK), + .DBGVECA (delay_DBGVECA), + .DBGVECB (delay_DBGVECB), + .DBGVECC (delay_DBGVECC), + .DRPDO (delay_DRPDO), + .DRPDRDY (delay_DRPDRDY), + .LL2BADDLLPERRN (delay_LL2BADDLLPERRN), + .LL2BADTLPERRN (delay_LL2BADTLPERRN), + .LL2PROTOCOLERRN (delay_LL2PROTOCOLERRN), + .LL2REPLAYROERRN (delay_LL2REPLAYROERRN), + .LL2REPLAYTOERRN (delay_LL2REPLAYTOERRN), + .LL2SUSPENDOKN (delay_LL2SUSPENDOKN), + .LL2TFCINIT1SEQN (delay_LL2TFCINIT1SEQN), + .LL2TFCINIT2SEQN (delay_LL2TFCINIT2SEQN), + .LNKCLKEN (delay_LNKCLKEN), + .MIMRXRADDR (delay_MIMRXRADDR), + .MIMRXRCE (delay_MIMRXRCE), + .MIMRXREN (delay_MIMRXREN), + .MIMRXWADDR (delay_MIMRXWADDR), + .MIMRXWDATA (delay_MIMRXWDATA), + .MIMRXWEN (delay_MIMRXWEN), + .MIMTXRADDR (delay_MIMTXRADDR), + .MIMTXRCE (delay_MIMTXRCE), + .MIMTXREN (delay_MIMTXREN), + .MIMTXWADDR (delay_MIMTXWADDR), + .MIMTXWDATA (delay_MIMTXWDATA), + .MIMTXWEN (delay_MIMTXWEN), + .PIPERX0POLARITY (delay_PIPERX0POLARITY), + .PIPERX1POLARITY (delay_PIPERX1POLARITY), + .PIPERX2POLARITY (delay_PIPERX2POLARITY), + .PIPERX3POLARITY (delay_PIPERX3POLARITY), + .PIPERX4POLARITY (delay_PIPERX4POLARITY), + .PIPERX5POLARITY (delay_PIPERX5POLARITY), + .PIPERX6POLARITY (delay_PIPERX6POLARITY), + .PIPERX7POLARITY (delay_PIPERX7POLARITY), + .PIPETX0CHARISK (delay_PIPETX0CHARISK), + .PIPETX0COMPLIANCE (delay_PIPETX0COMPLIANCE), + .PIPETX0DATA (delay_PIPETX0DATA), + .PIPETX0ELECIDLE (delay_PIPETX0ELECIDLE), + .PIPETX0POWERDOWN (delay_PIPETX0POWERDOWN), + .PIPETX1CHARISK (delay_PIPETX1CHARISK), + .PIPETX1COMPLIANCE (delay_PIPETX1COMPLIANCE), + .PIPETX1DATA (delay_PIPETX1DATA), + .PIPETX1ELECIDLE (delay_PIPETX1ELECIDLE), + .PIPETX1POWERDOWN (delay_PIPETX1POWERDOWN), + .PIPETX2CHARISK (delay_PIPETX2CHARISK), + .PIPETX2COMPLIANCE (delay_PIPETX2COMPLIANCE), + .PIPETX2DATA (delay_PIPETX2DATA), + .PIPETX2ELECIDLE (delay_PIPETX2ELECIDLE), + .PIPETX2POWERDOWN (delay_PIPETX2POWERDOWN), + .PIPETX3CHARISK (delay_PIPETX3CHARISK), + .PIPETX3COMPLIANCE (delay_PIPETX3COMPLIANCE), + .PIPETX3DATA (delay_PIPETX3DATA), + .PIPETX3ELECIDLE (delay_PIPETX3ELECIDLE), + .PIPETX3POWERDOWN (delay_PIPETX3POWERDOWN), + .PIPETX4CHARISK (delay_PIPETX4CHARISK), + .PIPETX4COMPLIANCE (delay_PIPETX4COMPLIANCE), + .PIPETX4DATA (delay_PIPETX4DATA), + .PIPETX4ELECIDLE (delay_PIPETX4ELECIDLE), + .PIPETX4POWERDOWN (delay_PIPETX4POWERDOWN), + .PIPETX5CHARISK (delay_PIPETX5CHARISK), + .PIPETX5COMPLIANCE (delay_PIPETX5COMPLIANCE), + .PIPETX5DATA (delay_PIPETX5DATA), + .PIPETX5ELECIDLE (delay_PIPETX5ELECIDLE), + .PIPETX5POWERDOWN (delay_PIPETX5POWERDOWN), + .PIPETX6CHARISK (delay_PIPETX6CHARISK), + .PIPETX6COMPLIANCE (delay_PIPETX6COMPLIANCE), + .PIPETX6DATA (delay_PIPETX6DATA), + .PIPETX6ELECIDLE (delay_PIPETX6ELECIDLE), + .PIPETX6POWERDOWN (delay_PIPETX6POWERDOWN), + .PIPETX7CHARISK (delay_PIPETX7CHARISK), + .PIPETX7COMPLIANCE (delay_PIPETX7COMPLIANCE), + .PIPETX7DATA (delay_PIPETX7DATA), + .PIPETX7ELECIDLE (delay_PIPETX7ELECIDLE), + .PIPETX7POWERDOWN (delay_PIPETX7POWERDOWN), + .PIPETXDEEMPH (delay_PIPETXDEEMPH), + .PIPETXMARGIN (delay_PIPETXMARGIN), + .PIPETXRATE (delay_PIPETXRATE), + .PIPETXRCVRDET (delay_PIPETXRCVRDET), + .PIPETXRESET (delay_PIPETXRESET), + .PL2LINKUPN (delay_PL2LINKUPN), + .PL2RECEIVERERRN (delay_PL2RECEIVERERRN), + .PL2RECOVERYN (delay_PL2RECOVERYN), + .PL2RXELECIDLE (delay_PL2RXELECIDLE), + .PL2SUSPENDOK (delay_PL2SUSPENDOK), + .PLDBGVEC (delay_PLDBGVEC), + .PLINITIALLINKWIDTH (delay_PLINITIALLINKWIDTH), + .PLLANEREVERSALMODE (delay_PLLANEREVERSALMODE), + .PLLINKGEN2CAP (delay_PLLINKGEN2CAP), + .PLLINKPARTNERGEN2SUPPORTED (delay_PLLINKPARTNERGEN2SUPPORTED), + .PLLINKUPCFGCAP (delay_PLLINKUPCFGCAP), + .PLLTSSMSTATE (delay_PLLTSSMSTATE), + .PLPHYLNKUPN (delay_PLPHYLNKUPN), + .PLRECEIVEDHOTRST (delay_PLRECEIVEDHOTRST), + .PLRXPMSTATE (delay_PLRXPMSTATE), + .PLSELLNKRATE (delay_PLSELLNKRATE), + .PLSELLNKWIDTH (delay_PLSELLNKWIDTH), + .PLTXPMSTATE (delay_PLTXPMSTATE), + .RECEIVEDFUNCLVLRSTN (delay_RECEIVEDFUNCLVLRSTN), + .TL2ASPMSUSPENDCREDITCHECKOKN (delay_TL2ASPMSUSPENDCREDITCHECKOKN), + .TL2ASPMSUSPENDREQN (delay_TL2ASPMSUSPENDREQN), + .TL2PPMSUSPENDOKN (delay_TL2PPMSUSPENDOKN), + .TRNFCCPLD (delay_TRNFCCPLD), + .TRNFCCPLH (delay_TRNFCCPLH), + .TRNFCNPD (delay_TRNFCNPD), + .TRNFCNPH (delay_TRNFCNPH), + .TRNFCPD (delay_TRNFCPD), + .TRNFCPH (delay_TRNFCPH), + .TRNLNKUPN (delay_TRNLNKUPN), + .TRNRBARHITN (delay_TRNRBARHITN), + .TRNRD (delay_TRNRD), + .TRNRDLLPDATA (delay_TRNRDLLPDATA), + .TRNRDLLPSRCRDYN (delay_TRNRDLLPSRCRDYN), + .TRNRECRCERRN (delay_TRNRECRCERRN), + .TRNREOFN (delay_TRNREOFN), + .TRNRERRFWDN (delay_TRNRERRFWDN), + .TRNRREMN (delay_TRNRREMN), + .TRNRSOFN (delay_TRNRSOFN), + .TRNRSRCDSCN (delay_TRNRSRCDSCN), + .TRNRSRCRDYN (delay_TRNRSRCRDYN), + .TRNTBUFAV (delay_TRNTBUFAV), + .TRNTCFGREQN (delay_TRNTCFGREQN), + .TRNTDLLPDSTRDYN (delay_TRNTDLLPDSTRDYN), + .TRNTDSTRDYN (delay_TRNTDSTRDYN), + .TRNTERRDROPN (delay_TRNTERRDROPN), + .USERRSTN (delay_USERRSTN), + .CFGBYTEENN (delay_CFGBYTEENN), + .CFGDI (delay_CFGDI), + .CFGDSBUSNUMBER (delay_CFGDSBUSNUMBER), + .CFGDSDEVICENUMBER (delay_CFGDSDEVICENUMBER), + .CFGDSFUNCTIONNUMBER (delay_CFGDSFUNCTIONNUMBER), + .CFGDSN (delay_CFGDSN), + .CFGDWADDR (delay_CFGDWADDR), + .CFGERRACSN (delay_CFGERRACSN), + .CFGERRAERHEADERLOG (delay_CFGERRAERHEADERLOG), + .CFGERRCORN (delay_CFGERRCORN), + .CFGERRCPLABORTN (delay_CFGERRCPLABORTN), + .CFGERRCPLTIMEOUTN (delay_CFGERRCPLTIMEOUTN), + .CFGERRCPLUNEXPECTN (delay_CFGERRCPLUNEXPECTN), + .CFGERRECRCN (delay_CFGERRECRCN), + .CFGERRLOCKEDN (delay_CFGERRLOCKEDN), + .CFGERRPOSTEDN (delay_CFGERRPOSTEDN), + .CFGERRTLPCPLHEADER (delay_CFGERRTLPCPLHEADER), + .CFGERRURN (delay_CFGERRURN), + .CFGINTERRUPTASSERTN (delay_CFGINTERRUPTASSERTN), + .CFGINTERRUPTDI (delay_CFGINTERRUPTDI), + .CFGINTERRUPTN (delay_CFGINTERRUPTN), + .CFGPMDIRECTASPML1N (delay_CFGPMDIRECTASPML1N), + .CFGPMSENDPMACKN (delay_CFGPMSENDPMACKN), + .CFGPMSENDPMETON (delay_CFGPMSENDPMETON), + .CFGPMSENDPMNAKN (delay_CFGPMSENDPMNAKN), + .CFGPMTURNOFFOKN (delay_CFGPMTURNOFFOKN), + .CFGPMWAKEN (delay_CFGPMWAKEN), + .CFGPORTNUMBER (delay_CFGPORTNUMBER), + .CFGRDENN (delay_CFGRDENN), + .CFGTRNPENDINGN (delay_CFGTRNPENDINGN), + .CFGWRENN (delay_CFGWRENN), + .CFGWRREADONLYN (delay_CFGWRREADONLYN), + .CFGWRRW1CASRWN (delay_CFGWRRW1CASRWN), + .CMRSTN (delay_CMRSTN), + .CMSTICKYRSTN (delay_CMSTICKYRSTN), + .DBGMODE (delay_DBGMODE), + .DBGSUBMODE (delay_DBGSUBMODE), + .DLRSTN (delay_DLRSTN), + .DRPCLK (delay_DRPCLK), + .DRPDADDR (delay_DRPDADDR), + .DRPDEN (delay_DRPDEN), + .DRPDI (delay_DRPDI), + .DRPDWE (delay_DRPDWE), + .FUNCLVLRSTN (delay_FUNCLVLRSTN), + .LL2SENDASREQL1N (delay_LL2SENDASREQL1N), + .LL2SENDENTERL1N (delay_LL2SENDENTERL1N), + .LL2SENDENTERL23N (delay_LL2SENDENTERL23N), + .LL2SUSPENDNOWN (delay_LL2SUSPENDNOWN), + .LL2TLPRCVN (delay_LL2TLPRCVN), + .MIMRXRDATA (delay_MIMRXRDATA), + .MIMTXRDATA (delay_MIMTXRDATA), + .PIPECLK (delay_PIPECLK), + .PIPERX0CHANISALIGNED (delay_PIPERX0CHANISALIGNED), + .PIPERX0CHARISK (delay_PIPERX0CHARISK), + .PIPERX0DATA (delay_PIPERX0DATA), + .PIPERX0ELECIDLE (delay_PIPERX0ELECIDLE), + .PIPERX0PHYSTATUS (delay_PIPERX0PHYSTATUS), + .PIPERX0STATUS (delay_PIPERX0STATUS), + .PIPERX0VALID (delay_PIPERX0VALID), + .PIPERX1CHANISALIGNED (delay_PIPERX1CHANISALIGNED), + .PIPERX1CHARISK (delay_PIPERX1CHARISK), + .PIPERX1DATA (delay_PIPERX1DATA), + .PIPERX1ELECIDLE (delay_PIPERX1ELECIDLE), + .PIPERX1PHYSTATUS (delay_PIPERX1PHYSTATUS), + .PIPERX1STATUS (delay_PIPERX1STATUS), + .PIPERX1VALID (delay_PIPERX1VALID), + .PIPERX2CHANISALIGNED (delay_PIPERX2CHANISALIGNED), + .PIPERX2CHARISK (delay_PIPERX2CHARISK), + .PIPERX2DATA (delay_PIPERX2DATA), + .PIPERX2ELECIDLE (delay_PIPERX2ELECIDLE), + .PIPERX2PHYSTATUS (delay_PIPERX2PHYSTATUS), + .PIPERX2STATUS (delay_PIPERX2STATUS), + .PIPERX2VALID (delay_PIPERX2VALID), + .PIPERX3CHANISALIGNED (delay_PIPERX3CHANISALIGNED), + .PIPERX3CHARISK (delay_PIPERX3CHARISK), + .PIPERX3DATA (delay_PIPERX3DATA), + .PIPERX3ELECIDLE (delay_PIPERX3ELECIDLE), + .PIPERX3PHYSTATUS (delay_PIPERX3PHYSTATUS), + .PIPERX3STATUS (delay_PIPERX3STATUS), + .PIPERX3VALID (delay_PIPERX3VALID), + .PIPERX4CHANISALIGNED (delay_PIPERX4CHANISALIGNED), + .PIPERX4CHARISK (delay_PIPERX4CHARISK), + .PIPERX4DATA (delay_PIPERX4DATA), + .PIPERX4ELECIDLE (delay_PIPERX4ELECIDLE), + .PIPERX4PHYSTATUS (delay_PIPERX4PHYSTATUS), + .PIPERX4STATUS (delay_PIPERX4STATUS), + .PIPERX4VALID (delay_PIPERX4VALID), + .PIPERX5CHANISALIGNED (delay_PIPERX5CHANISALIGNED), + .PIPERX5CHARISK (delay_PIPERX5CHARISK), + .PIPERX5DATA (delay_PIPERX5DATA), + .PIPERX5ELECIDLE (delay_PIPERX5ELECIDLE), + .PIPERX5PHYSTATUS (delay_PIPERX5PHYSTATUS), + .PIPERX5STATUS (delay_PIPERX5STATUS), + .PIPERX5VALID (delay_PIPERX5VALID), + .PIPERX6CHANISALIGNED (delay_PIPERX6CHANISALIGNED), + .PIPERX6CHARISK (delay_PIPERX6CHARISK), + .PIPERX6DATA (delay_PIPERX6DATA), + .PIPERX6ELECIDLE (delay_PIPERX6ELECIDLE), + .PIPERX6PHYSTATUS (delay_PIPERX6PHYSTATUS), + .PIPERX6STATUS (delay_PIPERX6STATUS), + .PIPERX6VALID (delay_PIPERX6VALID), + .PIPERX7CHANISALIGNED (delay_PIPERX7CHANISALIGNED), + .PIPERX7CHARISK (delay_PIPERX7CHARISK), + .PIPERX7DATA (delay_PIPERX7DATA), + .PIPERX7ELECIDLE (delay_PIPERX7ELECIDLE), + .PIPERX7PHYSTATUS (delay_PIPERX7PHYSTATUS), + .PIPERX7STATUS (delay_PIPERX7STATUS), + .PIPERX7VALID (delay_PIPERX7VALID), + .PL2DIRECTEDLSTATE (delay_PL2DIRECTEDLSTATE), + .PLDBGMODE (delay_PLDBGMODE), + .PLDIRECTEDLINKAUTON (delay_PLDIRECTEDLINKAUTON), + .PLDIRECTEDLINKCHANGE (delay_PLDIRECTEDLINKCHANGE), + .PLDIRECTEDLINKSPEED (delay_PLDIRECTEDLINKSPEED), + .PLDIRECTEDLINKWIDTH (delay_PLDIRECTEDLINKWIDTH), + .PLDOWNSTREAMDEEMPHSOURCE (delay_PLDOWNSTREAMDEEMPHSOURCE), + .PLRSTN (delay_PLRSTN), + .PLTRANSMITHOTRST (delay_PLTRANSMITHOTRST), + .PLUPSTREAMPREFERDEEMPH (delay_PLUPSTREAMPREFERDEEMPH), + .SYSRSTN (delay_SYSRSTN), + .TL2ASPMSUSPENDCREDITCHECKN (delay_TL2ASPMSUSPENDCREDITCHECKN), + .TL2PPMSUSPENDREQN (delay_TL2PPMSUSPENDREQN), + .TLRSTN (delay_TLRSTN), + .TRNFCSEL (delay_TRNFCSEL), + .TRNRDSTRDYN (delay_TRNRDSTRDYN), + .TRNRNPOKN (delay_TRNRNPOKN), + .TRNTCFGGNTN (delay_TRNTCFGGNTN), + .TRNTD (delay_TRNTD), + .TRNTDLLPDATA (delay_TRNTDLLPDATA), + .TRNTDLLPSRCRDYN (delay_TRNTDLLPSRCRDYN), + .TRNTECRCGENN (delay_TRNTECRCGENN), + .TRNTEOFN (delay_TRNTEOFN), + .TRNTERRFWDN (delay_TRNTERRFWDN), + .TRNTREMN (delay_TRNTREMN), + .TRNTSOFN (delay_TRNTSOFN), + .TRNTSRCDSCN (delay_TRNTSRCDSCN), + .TRNTSRCRDYN (delay_TRNTSRCRDYN), + .TRNTSTRN (delay_TRNTSTRN), + .USERCLK (delay_USERCLK), + .GSR(GSR) + ); + + specify + ( DRPCLK => DRPDO[0]) = (0, 0); + ( DRPCLK => DRPDO[10]) = (0, 0); + ( DRPCLK => DRPDO[11]) = (0, 0); + ( DRPCLK => DRPDO[12]) = (0, 0); + ( DRPCLK => DRPDO[13]) = (0, 0); + ( DRPCLK => DRPDO[14]) = (0, 0); + ( DRPCLK => DRPDO[15]) = (0, 0); + ( DRPCLK => DRPDO[1]) = (0, 0); + ( DRPCLK => DRPDO[2]) = (0, 0); + ( DRPCLK => DRPDO[3]) = (0, 0); + ( DRPCLK => DRPDO[4]) = (0, 0); + ( DRPCLK => DRPDO[5]) = (0, 0); + ( DRPCLK => DRPDO[6]) = (0, 0); + ( DRPCLK => DRPDO[7]) = (0, 0); + ( DRPCLK => DRPDO[8]) = (0, 0); + ( DRPCLK => DRPDO[9]) = (0, 0); + ( DRPCLK => DRPDRDY) = (0, 0); + ( PIPECLK => PIPERX0POLARITY) = (0, 0); + ( PIPECLK => PIPERX1POLARITY) = (0, 0); + ( PIPECLK => PIPERX2POLARITY) = (0, 0); + ( PIPECLK => PIPERX3POLARITY) = (0, 0); + ( PIPECLK => PIPERX4POLARITY) = (0, 0); + ( PIPECLK => PIPERX5POLARITY) = (0, 0); + ( PIPECLK => PIPERX6POLARITY) = (0, 0); + ( PIPECLK => PIPERX7POLARITY) = (0, 0); + ( PIPECLK => PIPETX0CHARISK[0]) = (0, 0); + ( PIPECLK => PIPETX0CHARISK[1]) = (0, 0); + ( PIPECLK => PIPETX0COMPLIANCE) = (0, 0); + ( PIPECLK => PIPETX0DATA[0]) = (0, 0); + ( PIPECLK => PIPETX0DATA[10]) = (0, 0); + ( PIPECLK => PIPETX0DATA[11]) = (0, 0); + ( PIPECLK => PIPETX0DATA[12]) = (0, 0); + ( PIPECLK => PIPETX0DATA[13]) = (0, 0); + ( PIPECLK => PIPETX0DATA[14]) = (0, 0); + ( PIPECLK => PIPETX0DATA[15]) = (0, 0); + ( PIPECLK => PIPETX0DATA[1]) = (0, 0); + ( PIPECLK => PIPETX0DATA[2]) = (0, 0); + ( PIPECLK => PIPETX0DATA[3]) = (0, 0); + ( PIPECLK => PIPETX0DATA[4]) = (0, 0); + ( PIPECLK => PIPETX0DATA[5]) = (0, 0); + ( PIPECLK => PIPETX0DATA[6]) = (0, 0); + ( PIPECLK => PIPETX0DATA[7]) = (0, 0); + ( PIPECLK => PIPETX0DATA[8]) = (0, 0); + ( PIPECLK => PIPETX0DATA[9]) = (0, 0); + ( PIPECLK => PIPETX0ELECIDLE) = (0, 0); + ( PIPECLK => PIPETX0POWERDOWN[0]) = (0, 0); + ( PIPECLK => PIPETX0POWERDOWN[1]) = (0, 0); + ( PIPECLK => PIPETX1CHARISK[0]) = (0, 0); + ( PIPECLK => PIPETX1CHARISK[1]) = (0, 0); + ( PIPECLK => PIPETX1COMPLIANCE) = (0, 0); + ( PIPECLK => PIPETX1DATA[0]) = (0, 0); + ( PIPECLK => PIPETX1DATA[10]) = (0, 0); + ( PIPECLK => PIPETX1DATA[11]) = (0, 0); + ( PIPECLK => PIPETX1DATA[12]) = (0, 0); + ( PIPECLK => PIPETX1DATA[13]) = (0, 0); + ( PIPECLK => PIPETX1DATA[14]) = (0, 0); + ( PIPECLK => PIPETX1DATA[15]) = (0, 0); + ( PIPECLK => PIPETX1DATA[1]) = (0, 0); + ( PIPECLK => PIPETX1DATA[2]) = (0, 0); + ( PIPECLK => PIPETX1DATA[3]) = (0, 0); + ( PIPECLK => PIPETX1DATA[4]) = (0, 0); + ( PIPECLK => PIPETX1DATA[5]) = (0, 0); + ( PIPECLK => PIPETX1DATA[6]) = (0, 0); + ( PIPECLK => PIPETX1DATA[7]) = (0, 0); + ( PIPECLK => PIPETX1DATA[8]) = (0, 0); + ( PIPECLK => PIPETX1DATA[9]) = (0, 0); + ( PIPECLK => PIPETX1ELECIDLE) = (0, 0); + ( PIPECLK => PIPETX1POWERDOWN[0]) = (0, 0); + ( PIPECLK => PIPETX1POWERDOWN[1]) = (0, 0); + ( PIPECLK => PIPETX2CHARISK[0]) = (0, 0); + ( PIPECLK => PIPETX2CHARISK[1]) = (0, 0); + ( PIPECLK => PIPETX2COMPLIANCE) = (0, 0); + ( PIPECLK => PIPETX2DATA[0]) = (0, 0); + ( PIPECLK => PIPETX2DATA[10]) = (0, 0); + ( PIPECLK => PIPETX2DATA[11]) = (0, 0); + ( PIPECLK => PIPETX2DATA[12]) = (0, 0); + ( PIPECLK => PIPETX2DATA[13]) = (0, 0); + ( PIPECLK => PIPETX2DATA[14]) = (0, 0); + ( PIPECLK => PIPETX2DATA[15]) = (0, 0); + ( PIPECLK => PIPETX2DATA[1]) = (0, 0); + ( PIPECLK => PIPETX2DATA[2]) = (0, 0); + ( PIPECLK => PIPETX2DATA[3]) = (0, 0); + ( PIPECLK => PIPETX2DATA[4]) = (0, 0); + ( PIPECLK => PIPETX2DATA[5]) = (0, 0); + ( PIPECLK => PIPETX2DATA[6]) = (0, 0); + ( PIPECLK => PIPETX2DATA[7]) = (0, 0); + ( PIPECLK => PIPETX2DATA[8]) = (0, 0); + ( PIPECLK => PIPETX2DATA[9]) = (0, 0); + ( PIPECLK => PIPETX2ELECIDLE) = (0, 0); + ( PIPECLK => PIPETX2POWERDOWN[0]) = (0, 0); + ( PIPECLK => PIPETX2POWERDOWN[1]) = (0, 0); + ( PIPECLK => PIPETX3CHARISK[0]) = (0, 0); + ( PIPECLK => PIPETX3CHARISK[1]) = (0, 0); + ( PIPECLK => PIPETX3COMPLIANCE) = (0, 0); + ( PIPECLK => PIPETX3DATA[0]) = (0, 0); + ( PIPECLK => PIPETX3DATA[10]) = (0, 0); + ( PIPECLK => PIPETX3DATA[11]) = (0, 0); + ( PIPECLK => PIPETX3DATA[12]) = (0, 0); + ( PIPECLK => PIPETX3DATA[13]) = (0, 0); + ( PIPECLK => PIPETX3DATA[14]) = (0, 0); + ( PIPECLK => PIPETX3DATA[15]) = (0, 0); + ( PIPECLK => PIPETX3DATA[1]) = (0, 0); + ( PIPECLK => PIPETX3DATA[2]) = (0, 0); + ( PIPECLK => PIPETX3DATA[3]) = (0, 0); + ( PIPECLK => PIPETX3DATA[4]) = (0, 0); + ( PIPECLK => PIPETX3DATA[5]) = (0, 0); + ( PIPECLK => PIPETX3DATA[6]) = (0, 0); + ( PIPECLK => PIPETX3DATA[7]) = (0, 0); + ( PIPECLK => PIPETX3DATA[8]) = (0, 0); + ( PIPECLK => PIPETX3DATA[9]) = (0, 0); + ( PIPECLK => PIPETX3ELECIDLE) = (0, 0); + ( PIPECLK => PIPETX3POWERDOWN[0]) = (0, 0); + ( PIPECLK => PIPETX3POWERDOWN[1]) = (0, 0); + ( PIPECLK => PIPETX4CHARISK[0]) = (0, 0); + ( PIPECLK => PIPETX4CHARISK[1]) = (0, 0); + ( PIPECLK => PIPETX4COMPLIANCE) = (0, 0); + ( PIPECLK => PIPETX4DATA[0]) = (0, 0); + ( PIPECLK => PIPETX4DATA[10]) = (0, 0); + ( PIPECLK => PIPETX4DATA[11]) = (0, 0); + ( PIPECLK => PIPETX4DATA[12]) = (0, 0); + ( PIPECLK => PIPETX4DATA[13]) = (0, 0); + ( PIPECLK => PIPETX4DATA[14]) = (0, 0); + ( PIPECLK => PIPETX4DATA[15]) = (0, 0); + ( PIPECLK => PIPETX4DATA[1]) = (0, 0); + ( PIPECLK => PIPETX4DATA[2]) = (0, 0); + ( PIPECLK => PIPETX4DATA[3]) = (0, 0); + ( PIPECLK => PIPETX4DATA[4]) = (0, 0); + ( PIPECLK => PIPETX4DATA[5]) = (0, 0); + ( PIPECLK => PIPETX4DATA[6]) = (0, 0); + ( PIPECLK => PIPETX4DATA[7]) = (0, 0); + ( PIPECLK => PIPETX4DATA[8]) = (0, 0); + ( PIPECLK => PIPETX4DATA[9]) = (0, 0); + ( PIPECLK => PIPETX4ELECIDLE) = (0, 0); + ( PIPECLK => PIPETX4POWERDOWN[0]) = (0, 0); + ( PIPECLK => PIPETX4POWERDOWN[1]) = (0, 0); + ( PIPECLK => PIPETX5CHARISK[0]) = (0, 0); + ( PIPECLK => PIPETX5CHARISK[1]) = (0, 0); + ( PIPECLK => PIPETX5COMPLIANCE) = (0, 0); + ( PIPECLK => PIPETX5DATA[0]) = (0, 0); + ( PIPECLK => PIPETX5DATA[10]) = (0, 0); + ( PIPECLK => PIPETX5DATA[11]) = (0, 0); + ( PIPECLK => PIPETX5DATA[12]) = (0, 0); + ( PIPECLK => PIPETX5DATA[13]) = (0, 0); + ( PIPECLK => PIPETX5DATA[14]) = (0, 0); + ( PIPECLK => PIPETX5DATA[15]) = (0, 0); + ( PIPECLK => PIPETX5DATA[1]) = (0, 0); + ( PIPECLK => PIPETX5DATA[2]) = (0, 0); + ( PIPECLK => PIPETX5DATA[3]) = (0, 0); + ( PIPECLK => PIPETX5DATA[4]) = (0, 0); + ( PIPECLK => PIPETX5DATA[5]) = (0, 0); + ( PIPECLK => PIPETX5DATA[6]) = (0, 0); + ( PIPECLK => PIPETX5DATA[7]) = (0, 0); + ( PIPECLK => PIPETX5DATA[8]) = (0, 0); + ( PIPECLK => PIPETX5DATA[9]) = (0, 0); + ( PIPECLK => PIPETX5ELECIDLE) = (0, 0); + ( PIPECLK => PIPETX5POWERDOWN[0]) = (0, 0); + ( PIPECLK => PIPETX5POWERDOWN[1]) = (0, 0); + ( PIPECLK => PIPETX6CHARISK[0]) = (0, 0); + ( PIPECLK => PIPETX6CHARISK[1]) = (0, 0); + ( PIPECLK => PIPETX6COMPLIANCE) = (0, 0); + ( PIPECLK => PIPETX6DATA[0]) = (0, 0); + ( PIPECLK => PIPETX6DATA[10]) = (0, 0); + ( PIPECLK => PIPETX6DATA[11]) = (0, 0); + ( PIPECLK => PIPETX6DATA[12]) = (0, 0); + ( PIPECLK => PIPETX6DATA[13]) = (0, 0); + ( PIPECLK => PIPETX6DATA[14]) = (0, 0); + ( PIPECLK => PIPETX6DATA[15]) = (0, 0); + ( PIPECLK => PIPETX6DATA[1]) = (0, 0); + ( PIPECLK => PIPETX6DATA[2]) = (0, 0); + ( PIPECLK => PIPETX6DATA[3]) = (0, 0); + ( PIPECLK => PIPETX6DATA[4]) = (0, 0); + ( PIPECLK => PIPETX6DATA[5]) = (0, 0); + ( PIPECLK => PIPETX6DATA[6]) = (0, 0); + ( PIPECLK => PIPETX6DATA[7]) = (0, 0); + ( PIPECLK => PIPETX6DATA[8]) = (0, 0); + ( PIPECLK => PIPETX6DATA[9]) = (0, 0); + ( PIPECLK => PIPETX6ELECIDLE) = (0, 0); + ( PIPECLK => PIPETX6POWERDOWN[0]) = (0, 0); + ( PIPECLK => PIPETX6POWERDOWN[1]) = (0, 0); + ( PIPECLK => PIPETX7CHARISK[0]) = (0, 0); + ( PIPECLK => PIPETX7CHARISK[1]) = (0, 0); + ( PIPECLK => PIPETX7COMPLIANCE) = (0, 0); + ( PIPECLK => PIPETX7DATA[0]) = (0, 0); + ( PIPECLK => PIPETX7DATA[10]) = (0, 0); + ( PIPECLK => PIPETX7DATA[11]) = (0, 0); + ( PIPECLK => PIPETX7DATA[12]) = (0, 0); + ( PIPECLK => PIPETX7DATA[13]) = (0, 0); + ( PIPECLK => PIPETX7DATA[14]) = (0, 0); + ( PIPECLK => PIPETX7DATA[15]) = (0, 0); + ( PIPECLK => PIPETX7DATA[1]) = (0, 0); + ( PIPECLK => PIPETX7DATA[2]) = (0, 0); + ( PIPECLK => PIPETX7DATA[3]) = (0, 0); + ( PIPECLK => PIPETX7DATA[4]) = (0, 0); + ( PIPECLK => PIPETX7DATA[5]) = (0, 0); + ( PIPECLK => PIPETX7DATA[6]) = (0, 0); + ( PIPECLK => PIPETX7DATA[7]) = (0, 0); + ( PIPECLK => PIPETX7DATA[8]) = (0, 0); + ( PIPECLK => PIPETX7DATA[9]) = (0, 0); + ( PIPECLK => PIPETX7ELECIDLE) = (0, 0); + ( PIPECLK => PIPETX7POWERDOWN[0]) = (0, 0); + ( PIPECLK => PIPETX7POWERDOWN[1]) = (0, 0); + ( PIPECLK => PIPETXDEEMPH) = (0, 0); + ( PIPECLK => PIPETXMARGIN[0]) = (0, 0); + ( PIPECLK => PIPETXMARGIN[1]) = (0, 0); + ( PIPECLK => PIPETXMARGIN[2]) = (0, 0); + ( PIPECLK => PIPETXRATE) = (0, 0); + ( PIPECLK => PIPETXRCVRDET) = (0, 0); + ( PIPECLK => PIPETXRESET) = (0, 0); + ( PIPECLK => PLDBGVEC[0]) = (0, 0); + ( PIPECLK => PLDBGVEC[10]) = (0, 0); + ( PIPECLK => PLDBGVEC[11]) = (0, 0); + ( PIPECLK => PLDBGVEC[1]) = (0, 0); + ( PIPECLK => PLDBGVEC[2]) = (0, 0); + ( PIPECLK => PLDBGVEC[3]) = (0, 0); + ( PIPECLK => PLDBGVEC[4]) = (0, 0); + ( PIPECLK => PLDBGVEC[5]) = (0, 0); + ( PIPECLK => PLDBGVEC[6]) = (0, 0); + ( PIPECLK => PLDBGVEC[7]) = (0, 0); + ( PIPECLK => PLDBGVEC[8]) = (0, 0); + ( PIPECLK => PLDBGVEC[9]) = (0, 0); + ( PIPECLK => PLINITIALLINKWIDTH[0]) = (0, 0); + ( PIPECLK => PLINITIALLINKWIDTH[1]) = (0, 0); + ( PIPECLK => PLINITIALLINKWIDTH[2]) = (0, 0); + ( PIPECLK => PLLANEREVERSALMODE[0]) = (0, 0); + ( PIPECLK => PLLANEREVERSALMODE[1]) = (0, 0); + ( PIPECLK => PLLINKGEN2CAP) = (0, 0); + ( PIPECLK => PLLINKPARTNERGEN2SUPPORTED) = (0, 0); + ( PIPECLK => PLLINKUPCFGCAP) = (0, 0); + ( PIPECLK => PLLTSSMSTATE[0]) = (0, 0); + ( PIPECLK => PLLTSSMSTATE[1]) = (0, 0); + ( PIPECLK => PLLTSSMSTATE[2]) = (0, 0); + ( PIPECLK => PLLTSSMSTATE[3]) = (0, 0); + ( PIPECLK => PLLTSSMSTATE[4]) = (0, 0); + ( PIPECLK => PLLTSSMSTATE[5]) = (0, 0); + ( PIPECLK => PLPHYLNKUPN) = (0, 0); + ( PIPECLK => PLRECEIVEDHOTRST) = (0, 0); + ( PIPECLK => PLRXPMSTATE[0]) = (0, 0); + ( PIPECLK => PLRXPMSTATE[1]) = (0, 0); + ( PIPECLK => PLSELLNKRATE) = (0, 0); + ( PIPECLK => PLSELLNKWIDTH[0]) = (0, 0); + ( PIPECLK => PLSELLNKWIDTH[1]) = (0, 0); + ( PIPECLK => PLTXPMSTATE[0]) = (0, 0); + ( PIPECLK => PLTXPMSTATE[1]) = (0, 0); + ( PIPECLK => PLTXPMSTATE[2]) = (0, 0); + ( USERCLK => CFGAERECRCCHECKEN) = (0, 0); + ( USERCLK => CFGAERECRCGENEN) = (0, 0); + ( USERCLK => CFGCOMMANDBUSMASTERENABLE) = (0, 0); + ( USERCLK => CFGCOMMANDINTERRUPTDISABLE) = (0, 0); + ( USERCLK => CFGCOMMANDIOENABLE) = (0, 0); + ( USERCLK => CFGCOMMANDMEMENABLE) = (0, 0); + ( USERCLK => CFGCOMMANDSERREN) = (0, 0); + ( USERCLK => CFGDEVCONTROL2CPLTIMEOUTDIS) = (0, 0); + ( USERCLK => CFGDEVCONTROL2CPLTIMEOUTVAL[0]) = (0, 0); + ( USERCLK => CFGDEVCONTROL2CPLTIMEOUTVAL[1]) = (0, 0); + ( USERCLK => CFGDEVCONTROL2CPLTIMEOUTVAL[2]) = (0, 0); + ( USERCLK => CFGDEVCONTROL2CPLTIMEOUTVAL[3]) = (0, 0); + ( USERCLK => CFGDEVCONTROLAUXPOWEREN) = (0, 0); + ( USERCLK => CFGDEVCONTROLCORRERRREPORTINGEN) = (0, 0); + ( USERCLK => CFGDEVCONTROLENABLERO) = (0, 0); + ( USERCLK => CFGDEVCONTROLEXTTAGEN) = (0, 0); + ( USERCLK => CFGDEVCONTROLFATALERRREPORTINGEN) = (0, 0); + ( USERCLK => CFGDEVCONTROLMAXPAYLOAD[0]) = (0, 0); + ( USERCLK => CFGDEVCONTROLMAXPAYLOAD[1]) = (0, 0); + ( USERCLK => CFGDEVCONTROLMAXPAYLOAD[2]) = (0, 0); + ( USERCLK => CFGDEVCONTROLMAXREADREQ[0]) = (0, 0); + ( USERCLK => CFGDEVCONTROLMAXREADREQ[1]) = (0, 0); + ( USERCLK => CFGDEVCONTROLMAXREADREQ[2]) = (0, 0); + ( USERCLK => CFGDEVCONTROLNONFATALREPORTINGEN) = (0, 0); + ( USERCLK => CFGDEVCONTROLNOSNOOPEN) = (0, 0); + ( USERCLK => CFGDEVCONTROLPHANTOMEN) = (0, 0); + ( USERCLK => CFGDEVCONTROLURERRREPORTINGEN) = (0, 0); + ( USERCLK => CFGDEVSTATUSCORRERRDETECTED) = (0, 0); + ( USERCLK => CFGDEVSTATUSFATALERRDETECTED) = (0, 0); + ( USERCLK => CFGDEVSTATUSNONFATALERRDETECTED) = (0, 0); + ( USERCLK => CFGDEVSTATUSURDETECTED) = (0, 0); + ( USERCLK => CFGDO[0]) = (0, 0); + ( USERCLK => CFGDO[10]) = (0, 0); + ( USERCLK => CFGDO[11]) = (0, 0); + ( USERCLK => CFGDO[12]) = (0, 0); + ( USERCLK => CFGDO[13]) = (0, 0); + ( USERCLK => CFGDO[14]) = (0, 0); + ( USERCLK => CFGDO[15]) = (0, 0); + ( USERCLK => CFGDO[16]) = (0, 0); + ( USERCLK => CFGDO[17]) = (0, 0); + ( USERCLK => CFGDO[18]) = (0, 0); + ( USERCLK => CFGDO[19]) = (0, 0); + ( USERCLK => CFGDO[1]) = (0, 0); + ( USERCLK => CFGDO[20]) = (0, 0); + ( USERCLK => CFGDO[21]) = (0, 0); + ( USERCLK => CFGDO[22]) = (0, 0); + ( USERCLK => CFGDO[23]) = (0, 0); + ( USERCLK => CFGDO[24]) = (0, 0); + ( USERCLK => CFGDO[25]) = (0, 0); + ( USERCLK => CFGDO[26]) = (0, 0); + ( USERCLK => CFGDO[27]) = (0, 0); + ( USERCLK => CFGDO[28]) = (0, 0); + ( USERCLK => CFGDO[29]) = (0, 0); + ( USERCLK => CFGDO[2]) = (0, 0); + ( USERCLK => CFGDO[30]) = (0, 0); + ( USERCLK => CFGDO[31]) = (0, 0); + ( USERCLK => CFGDO[3]) = (0, 0); + ( USERCLK => CFGDO[4]) = (0, 0); + ( USERCLK => CFGDO[5]) = (0, 0); + ( USERCLK => CFGDO[6]) = (0, 0); + ( USERCLK => CFGDO[7]) = (0, 0); + ( USERCLK => CFGDO[8]) = (0, 0); + ( USERCLK => CFGDO[9]) = (0, 0); + ( USERCLK => CFGERRAERHEADERLOGSETN) = (0, 0); + ( USERCLK => CFGERRCPLRDYN) = (0, 0); + ( USERCLK => CFGINTERRUPTDO[0]) = (0, 0); + ( USERCLK => CFGINTERRUPTDO[1]) = (0, 0); + ( USERCLK => CFGINTERRUPTDO[2]) = (0, 0); + ( USERCLK => CFGINTERRUPTDO[3]) = (0, 0); + ( USERCLK => CFGINTERRUPTDO[4]) = (0, 0); + ( USERCLK => CFGINTERRUPTDO[5]) = (0, 0); + ( USERCLK => CFGINTERRUPTDO[6]) = (0, 0); + ( USERCLK => CFGINTERRUPTDO[7]) = (0, 0); + ( USERCLK => CFGINTERRUPTMMENABLE[0]) = (0, 0); + ( USERCLK => CFGINTERRUPTMMENABLE[1]) = (0, 0); + ( USERCLK => CFGINTERRUPTMMENABLE[2]) = (0, 0); + ( USERCLK => CFGINTERRUPTMSIENABLE) = (0, 0); + ( USERCLK => CFGINTERRUPTMSIXENABLE) = (0, 0); + ( USERCLK => CFGINTERRUPTMSIXFM) = (0, 0); + ( USERCLK => CFGINTERRUPTRDYN) = (0, 0); + ( USERCLK => CFGLINKCONTROLASPMCONTROL[0]) = (0, 0); + ( USERCLK => CFGLINKCONTROLASPMCONTROL[1]) = (0, 0); + ( USERCLK => CFGLINKCONTROLAUTOBANDWIDTHINTEN) = (0, 0); + ( USERCLK => CFGLINKCONTROLBANDWIDTHINTEN) = (0, 0); + ( USERCLK => CFGLINKCONTROLCLOCKPMEN) = (0, 0); + ( USERCLK => CFGLINKCONTROLCOMMONCLOCK) = (0, 0); + ( USERCLK => CFGLINKCONTROLEXTENDEDSYNC) = (0, 0); + ( USERCLK => CFGLINKCONTROLHWAUTOWIDTHDIS) = (0, 0); + ( USERCLK => CFGLINKCONTROLLINKDISABLE) = (0, 0); + ( USERCLK => CFGLINKCONTROLRCB) = (0, 0); + ( USERCLK => CFGLINKCONTROLRETRAINLINK) = (0, 0); + ( USERCLK => CFGLINKSTATUSAUTOBANDWIDTHSTATUS) = (0, 0); + ( USERCLK => CFGLINKSTATUSBANDWITHSTATUS) = (0, 0); + ( USERCLK => CFGLINKSTATUSCURRENTSPEED[0]) = (0, 0); + ( USERCLK => CFGLINKSTATUSCURRENTSPEED[1]) = (0, 0); + ( USERCLK => CFGLINKSTATUSDLLACTIVE) = (0, 0); + ( USERCLK => CFGLINKSTATUSLINKTRAINING) = (0, 0); + ( USERCLK => CFGLINKSTATUSNEGOTIATEDWIDTH[0]) = (0, 0); + ( USERCLK => CFGLINKSTATUSNEGOTIATEDWIDTH[1]) = (0, 0); + ( USERCLK => CFGLINKSTATUSNEGOTIATEDWIDTH[2]) = (0, 0); + ( USERCLK => CFGLINKSTATUSNEGOTIATEDWIDTH[3]) = (0, 0); + ( USERCLK => CFGMSGDATA[0]) = (0, 0); + ( USERCLK => CFGMSGDATA[10]) = (0, 0); + ( USERCLK => CFGMSGDATA[11]) = (0, 0); + ( USERCLK => CFGMSGDATA[12]) = (0, 0); + ( USERCLK => CFGMSGDATA[13]) = (0, 0); + ( USERCLK => CFGMSGDATA[14]) = (0, 0); + ( USERCLK => CFGMSGDATA[15]) = (0, 0); + ( USERCLK => CFGMSGDATA[1]) = (0, 0); + ( USERCLK => CFGMSGDATA[2]) = (0, 0); + ( USERCLK => CFGMSGDATA[3]) = (0, 0); + ( USERCLK => CFGMSGDATA[4]) = (0, 0); + ( USERCLK => CFGMSGDATA[5]) = (0, 0); + ( USERCLK => CFGMSGDATA[6]) = (0, 0); + ( USERCLK => CFGMSGDATA[7]) = (0, 0); + ( USERCLK => CFGMSGDATA[8]) = (0, 0); + ( USERCLK => CFGMSGDATA[9]) = (0, 0); + ( USERCLK => CFGMSGRECEIVED) = (0, 0); + ( USERCLK => CFGMSGRECEIVEDASSERTINTA) = (0, 0); + ( USERCLK => CFGMSGRECEIVEDASSERTINTB) = (0, 0); + ( USERCLK => CFGMSGRECEIVEDASSERTINTC) = (0, 0); + ( USERCLK => CFGMSGRECEIVEDASSERTINTD) = (0, 0); + ( USERCLK => CFGMSGRECEIVEDDEASSERTINTA) = (0, 0); + ( USERCLK => CFGMSGRECEIVEDDEASSERTINTB) = (0, 0); + ( USERCLK => CFGMSGRECEIVEDDEASSERTINTC) = (0, 0); + ( USERCLK => CFGMSGRECEIVEDDEASSERTINTD) = (0, 0); + ( USERCLK => CFGMSGRECEIVEDERRCOR) = (0, 0); + ( USERCLK => CFGMSGRECEIVEDERRFATAL) = (0, 0); + ( USERCLK => CFGMSGRECEIVEDERRNONFATAL) = (0, 0); + ( USERCLK => CFGMSGRECEIVEDPMASNAK) = (0, 0); + ( USERCLK => CFGMSGRECEIVEDPMETO) = (0, 0); + ( USERCLK => CFGMSGRECEIVEDPMETOACK) = (0, 0); + ( USERCLK => CFGMSGRECEIVEDPMPME) = (0, 0); + ( USERCLK => CFGMSGRECEIVEDSETSLOTPOWERLIMIT) = (0, 0); + ( USERCLK => CFGMSGRECEIVEDUNLOCK) = (0, 0); + ( USERCLK => CFGPCIELINKSTATE[0]) = (0, 0); + ( USERCLK => CFGPCIELINKSTATE[1]) = (0, 0); + ( USERCLK => CFGPCIELINKSTATE[2]) = (0, 0); + ( USERCLK => CFGPMCSRPMEEN) = (0, 0); + ( USERCLK => CFGPMCSRPMESTATUS) = (0, 0); + ( USERCLK => CFGPMCSRPOWERSTATE[0]) = (0, 0); + ( USERCLK => CFGPMCSRPOWERSTATE[1]) = (0, 0); + ( USERCLK => CFGPMRCVASREQL1N) = (0, 0); + ( USERCLK => CFGPMRCVENTERL1N) = (0, 0); + ( USERCLK => CFGPMRCVENTERL23N) = (0, 0); + ( USERCLK => CFGPMRCVREQACKN) = (0, 0); + ( USERCLK => CFGRDWRDONEN) = (0, 0); + ( USERCLK => CFGSLOTCONTROLELECTROMECHILCTLPULSE) = (0, 0); + ( USERCLK => CFGTRANSACTION) = (0, 0); + ( USERCLK => CFGTRANSACTIONADDR[0]) = (0, 0); + ( USERCLK => CFGTRANSACTIONADDR[1]) = (0, 0); + ( USERCLK => CFGTRANSACTIONADDR[2]) = (0, 0); + ( USERCLK => CFGTRANSACTIONADDR[3]) = (0, 0); + ( USERCLK => CFGTRANSACTIONADDR[4]) = (0, 0); + ( USERCLK => CFGTRANSACTIONADDR[5]) = (0, 0); + ( USERCLK => CFGTRANSACTIONADDR[6]) = (0, 0); + ( USERCLK => CFGTRANSACTIONTYPE) = (0, 0); + ( USERCLK => CFGVCTCVCMAP[0]) = (0, 0); + ( USERCLK => CFGVCTCVCMAP[1]) = (0, 0); + ( USERCLK => CFGVCTCVCMAP[2]) = (0, 0); + ( USERCLK => CFGVCTCVCMAP[3]) = (0, 0); + ( USERCLK => CFGVCTCVCMAP[4]) = (0, 0); + ( USERCLK => CFGVCTCVCMAP[5]) = (0, 0); + ( USERCLK => CFGVCTCVCMAP[6]) = (0, 0); + ( USERCLK => DBGSCLRA) = (0, 0); + ( USERCLK => DBGSCLRB) = (0, 0); + ( USERCLK => DBGSCLRC) = (0, 0); + ( USERCLK => DBGSCLRD) = (0, 0); + ( USERCLK => DBGSCLRE) = (0, 0); + ( USERCLK => DBGSCLRF) = (0, 0); + ( USERCLK => DBGSCLRG) = (0, 0); + ( USERCLK => DBGSCLRH) = (0, 0); + ( USERCLK => DBGSCLRI) = (0, 0); + ( USERCLK => DBGSCLRJ) = (0, 0); + ( USERCLK => DBGSCLRK) = (0, 0); + ( USERCLK => DBGVECA[0]) = (0, 0); + ( USERCLK => DBGVECA[10]) = (0, 0); + ( USERCLK => DBGVECA[11]) = (0, 0); + ( USERCLK => DBGVECA[12]) = (0, 0); + ( USERCLK => DBGVECA[13]) = (0, 0); + ( USERCLK => DBGVECA[14]) = (0, 0); + ( USERCLK => DBGVECA[15]) = (0, 0); + ( USERCLK => DBGVECA[16]) = (0, 0); + ( USERCLK => DBGVECA[17]) = (0, 0); + ( USERCLK => DBGVECA[18]) = (0, 0); + ( USERCLK => DBGVECA[19]) = (0, 0); + ( USERCLK => DBGVECA[1]) = (0, 0); + ( USERCLK => DBGVECA[20]) = (0, 0); + ( USERCLK => DBGVECA[21]) = (0, 0); + ( USERCLK => DBGVECA[22]) = (0, 0); + ( USERCLK => DBGVECA[23]) = (0, 0); + ( USERCLK => DBGVECA[24]) = (0, 0); + ( USERCLK => DBGVECA[25]) = (0, 0); + ( USERCLK => DBGVECA[26]) = (0, 0); + ( USERCLK => DBGVECA[27]) = (0, 0); + ( USERCLK => DBGVECA[28]) = (0, 0); + ( USERCLK => DBGVECA[29]) = (0, 0); + ( USERCLK => DBGVECA[2]) = (0, 0); + ( USERCLK => DBGVECA[30]) = (0, 0); + ( USERCLK => DBGVECA[31]) = (0, 0); + ( USERCLK => DBGVECA[32]) = (0, 0); + ( USERCLK => DBGVECA[33]) = (0, 0); + ( USERCLK => DBGVECA[34]) = (0, 0); + ( USERCLK => DBGVECA[35]) = (0, 0); + ( USERCLK => DBGVECA[36]) = (0, 0); + ( USERCLK => DBGVECA[37]) = (0, 0); + ( USERCLK => DBGVECA[38]) = (0, 0); + ( USERCLK => DBGVECA[39]) = (0, 0); + ( USERCLK => DBGVECA[3]) = (0, 0); + ( USERCLK => DBGVECA[40]) = (0, 0); + ( USERCLK => DBGVECA[41]) = (0, 0); + ( USERCLK => DBGVECA[42]) = (0, 0); + ( USERCLK => DBGVECA[43]) = (0, 0); + ( USERCLK => DBGVECA[44]) = (0, 0); + ( USERCLK => DBGVECA[45]) = (0, 0); + ( USERCLK => DBGVECA[46]) = (0, 0); + ( USERCLK => DBGVECA[47]) = (0, 0); + ( USERCLK => DBGVECA[48]) = (0, 0); + ( USERCLK => DBGVECA[49]) = (0, 0); + ( USERCLK => DBGVECA[4]) = (0, 0); + ( USERCLK => DBGVECA[50]) = (0, 0); + ( USERCLK => DBGVECA[51]) = (0, 0); + ( USERCLK => DBGVECA[52]) = (0, 0); + ( USERCLK => DBGVECA[53]) = (0, 0); + ( USERCLK => DBGVECA[54]) = (0, 0); + ( USERCLK => DBGVECA[55]) = (0, 0); + ( USERCLK => DBGVECA[56]) = (0, 0); + ( USERCLK => DBGVECA[57]) = (0, 0); + ( USERCLK => DBGVECA[58]) = (0, 0); + ( USERCLK => DBGVECA[59]) = (0, 0); + ( USERCLK => DBGVECA[5]) = (0, 0); + ( USERCLK => DBGVECA[60]) = (0, 0); + ( USERCLK => DBGVECA[61]) = (0, 0); + ( USERCLK => DBGVECA[62]) = (0, 0); + ( USERCLK => DBGVECA[63]) = (0, 0); + ( USERCLK => DBGVECA[6]) = (0, 0); + ( USERCLK => DBGVECA[7]) = (0, 0); + ( USERCLK => DBGVECA[8]) = (0, 0); + ( USERCLK => DBGVECA[9]) = (0, 0); + ( USERCLK => DBGVECB[0]) = (0, 0); + ( USERCLK => DBGVECB[10]) = (0, 0); + ( USERCLK => DBGVECB[11]) = (0, 0); + ( USERCLK => DBGVECB[12]) = (0, 0); + ( USERCLK => DBGVECB[13]) = (0, 0); + ( USERCLK => DBGVECB[14]) = (0, 0); + ( USERCLK => DBGVECB[15]) = (0, 0); + ( USERCLK => DBGVECB[16]) = (0, 0); + ( USERCLK => DBGVECB[17]) = (0, 0); + ( USERCLK => DBGVECB[18]) = (0, 0); + ( USERCLK => DBGVECB[19]) = (0, 0); + ( USERCLK => DBGVECB[1]) = (0, 0); + ( USERCLK => DBGVECB[20]) = (0, 0); + ( USERCLK => DBGVECB[21]) = (0, 0); + ( USERCLK => DBGVECB[22]) = (0, 0); + ( USERCLK => DBGVECB[23]) = (0, 0); + ( USERCLK => DBGVECB[24]) = (0, 0); + ( USERCLK => DBGVECB[25]) = (0, 0); + ( USERCLK => DBGVECB[26]) = (0, 0); + ( USERCLK => DBGVECB[27]) = (0, 0); + ( USERCLK => DBGVECB[28]) = (0, 0); + ( USERCLK => DBGVECB[29]) = (0, 0); + ( USERCLK => DBGVECB[2]) = (0, 0); + ( USERCLK => DBGVECB[30]) = (0, 0); + ( USERCLK => DBGVECB[31]) = (0, 0); + ( USERCLK => DBGVECB[32]) = (0, 0); + ( USERCLK => DBGVECB[33]) = (0, 0); + ( USERCLK => DBGVECB[34]) = (0, 0); + ( USERCLK => DBGVECB[35]) = (0, 0); + ( USERCLK => DBGVECB[36]) = (0, 0); + ( USERCLK => DBGVECB[37]) = (0, 0); + ( USERCLK => DBGVECB[38]) = (0, 0); + ( USERCLK => DBGVECB[39]) = (0, 0); + ( USERCLK => DBGVECB[3]) = (0, 0); + ( USERCLK => DBGVECB[40]) = (0, 0); + ( USERCLK => DBGVECB[41]) = (0, 0); + ( USERCLK => DBGVECB[42]) = (0, 0); + ( USERCLK => DBGVECB[43]) = (0, 0); + ( USERCLK => DBGVECB[44]) = (0, 0); + ( USERCLK => DBGVECB[45]) = (0, 0); + ( USERCLK => DBGVECB[46]) = (0, 0); + ( USERCLK => DBGVECB[47]) = (0, 0); + ( USERCLK => DBGVECB[48]) = (0, 0); + ( USERCLK => DBGVECB[49]) = (0, 0); + ( USERCLK => DBGVECB[4]) = (0, 0); + ( USERCLK => DBGVECB[50]) = (0, 0); + ( USERCLK => DBGVECB[51]) = (0, 0); + ( USERCLK => DBGVECB[52]) = (0, 0); + ( USERCLK => DBGVECB[53]) = (0, 0); + ( USERCLK => DBGVECB[54]) = (0, 0); + ( USERCLK => DBGVECB[55]) = (0, 0); + ( USERCLK => DBGVECB[56]) = (0, 0); + ( USERCLK => DBGVECB[57]) = (0, 0); + ( USERCLK => DBGVECB[58]) = (0, 0); + ( USERCLK => DBGVECB[59]) = (0, 0); + ( USERCLK => DBGVECB[5]) = (0, 0); + ( USERCLK => DBGVECB[60]) = (0, 0); + ( USERCLK => DBGVECB[61]) = (0, 0); + ( USERCLK => DBGVECB[62]) = (0, 0); + ( USERCLK => DBGVECB[63]) = (0, 0); + ( USERCLK => DBGVECB[6]) = (0, 0); + ( USERCLK => DBGVECB[7]) = (0, 0); + ( USERCLK => DBGVECB[8]) = (0, 0); + ( USERCLK => DBGVECB[9]) = (0, 0); + ( USERCLK => DBGVECC[0]) = (0, 0); + ( USERCLK => DBGVECC[10]) = (0, 0); + ( USERCLK => DBGVECC[11]) = (0, 0); + ( USERCLK => DBGVECC[1]) = (0, 0); + ( USERCLK => DBGVECC[2]) = (0, 0); + ( USERCLK => DBGVECC[3]) = (0, 0); + ( USERCLK => DBGVECC[4]) = (0, 0); + ( USERCLK => DBGVECC[5]) = (0, 0); + ( USERCLK => DBGVECC[6]) = (0, 0); + ( USERCLK => DBGVECC[7]) = (0, 0); + ( USERCLK => DBGVECC[8]) = (0, 0); + ( USERCLK => DBGVECC[9]) = (0, 0); + ( USERCLK => LL2BADDLLPERRN) = (0, 0); + ( USERCLK => LL2BADTLPERRN) = (0, 0); + ( USERCLK => LL2PROTOCOLERRN) = (0, 0); + ( USERCLK => LL2REPLAYROERRN) = (0, 0); + ( USERCLK => LL2REPLAYTOERRN) = (0, 0); + ( USERCLK => LL2SUSPENDOKN) = (0, 0); + ( USERCLK => LL2TFCINIT1SEQN) = (0, 0); + ( USERCLK => LL2TFCINIT2SEQN) = (0, 0); + ( USERCLK => LNKCLKEN) = (0, 0); + ( USERCLK => MIMRXRADDR[0]) = (0, 0); + ( USERCLK => MIMRXRADDR[10]) = (0, 0); + ( USERCLK => MIMRXRADDR[11]) = (0, 0); + ( USERCLK => MIMRXRADDR[12]) = (0, 0); + ( USERCLK => MIMRXRADDR[1]) = (0, 0); + ( USERCLK => MIMRXRADDR[2]) = (0, 0); + ( USERCLK => MIMRXRADDR[3]) = (0, 0); + ( USERCLK => MIMRXRADDR[4]) = (0, 0); + ( USERCLK => MIMRXRADDR[5]) = (0, 0); + ( USERCLK => MIMRXRADDR[6]) = (0, 0); + ( USERCLK => MIMRXRADDR[7]) = (0, 0); + ( USERCLK => MIMRXRADDR[8]) = (0, 0); + ( USERCLK => MIMRXRADDR[9]) = (0, 0); + ( USERCLK => MIMRXRCE) = (0, 0); + ( USERCLK => MIMRXREN) = (0, 0); + ( USERCLK => MIMRXWADDR[0]) = (0, 0); + ( USERCLK => MIMRXWADDR[10]) = (0, 0); + ( USERCLK => MIMRXWADDR[11]) = (0, 0); + ( USERCLK => MIMRXWADDR[12]) = (0, 0); + ( USERCLK => MIMRXWADDR[1]) = (0, 0); + ( USERCLK => MIMRXWADDR[2]) = (0, 0); + ( USERCLK => MIMRXWADDR[3]) = (0, 0); + ( USERCLK => MIMRXWADDR[4]) = (0, 0); + ( USERCLK => MIMRXWADDR[5]) = (0, 0); + ( USERCLK => MIMRXWADDR[6]) = (0, 0); + ( USERCLK => MIMRXWADDR[7]) = (0, 0); + ( USERCLK => MIMRXWADDR[8]) = (0, 0); + ( USERCLK => MIMRXWADDR[9]) = (0, 0); + ( USERCLK => MIMRXWDATA[0]) = (0, 0); + ( USERCLK => MIMRXWDATA[10]) = (0, 0); + ( USERCLK => MIMRXWDATA[11]) = (0, 0); + ( USERCLK => MIMRXWDATA[12]) = (0, 0); + ( USERCLK => MIMRXWDATA[13]) = (0, 0); + ( USERCLK => MIMRXWDATA[14]) = (0, 0); + ( USERCLK => MIMRXWDATA[15]) = (0, 0); + ( USERCLK => MIMRXWDATA[16]) = (0, 0); + ( USERCLK => MIMRXWDATA[17]) = (0, 0); + ( USERCLK => MIMRXWDATA[18]) = (0, 0); + ( USERCLK => MIMRXWDATA[19]) = (0, 0); + ( USERCLK => MIMRXWDATA[1]) = (0, 0); + ( USERCLK => MIMRXWDATA[20]) = (0, 0); + ( USERCLK => MIMRXWDATA[21]) = (0, 0); + ( USERCLK => MIMRXWDATA[22]) = (0, 0); + ( USERCLK => MIMRXWDATA[23]) = (0, 0); + ( USERCLK => MIMRXWDATA[24]) = (0, 0); + ( USERCLK => MIMRXWDATA[25]) = (0, 0); + ( USERCLK => MIMRXWDATA[26]) = (0, 0); + ( USERCLK => MIMRXWDATA[27]) = (0, 0); + ( USERCLK => MIMRXWDATA[28]) = (0, 0); + ( USERCLK => MIMRXWDATA[29]) = (0, 0); + ( USERCLK => MIMRXWDATA[2]) = (0, 0); + ( USERCLK => MIMRXWDATA[30]) = (0, 0); + ( USERCLK => MIMRXWDATA[31]) = (0, 0); + ( USERCLK => MIMRXWDATA[32]) = (0, 0); + ( USERCLK => MIMRXWDATA[33]) = (0, 0); + ( USERCLK => MIMRXWDATA[34]) = (0, 0); + ( USERCLK => MIMRXWDATA[35]) = (0, 0); + ( USERCLK => MIMRXWDATA[36]) = (0, 0); + ( USERCLK => MIMRXWDATA[37]) = (0, 0); + ( USERCLK => MIMRXWDATA[38]) = (0, 0); + ( USERCLK => MIMRXWDATA[39]) = (0, 0); + ( USERCLK => MIMRXWDATA[3]) = (0, 0); + ( USERCLK => MIMRXWDATA[40]) = (0, 0); + ( USERCLK => MIMRXWDATA[41]) = (0, 0); + ( USERCLK => MIMRXWDATA[42]) = (0, 0); + ( USERCLK => MIMRXWDATA[43]) = (0, 0); + ( USERCLK => MIMRXWDATA[44]) = (0, 0); + ( USERCLK => MIMRXWDATA[45]) = (0, 0); + ( USERCLK => MIMRXWDATA[46]) = (0, 0); + ( USERCLK => MIMRXWDATA[47]) = (0, 0); + ( USERCLK => MIMRXWDATA[48]) = (0, 0); + ( USERCLK => MIMRXWDATA[49]) = (0, 0); + ( USERCLK => MIMRXWDATA[4]) = (0, 0); + ( USERCLK => MIMRXWDATA[50]) = (0, 0); + ( USERCLK => MIMRXWDATA[51]) = (0, 0); + ( USERCLK => MIMRXWDATA[52]) = (0, 0); + ( USERCLK => MIMRXWDATA[53]) = (0, 0); + ( USERCLK => MIMRXWDATA[54]) = (0, 0); + ( USERCLK => MIMRXWDATA[55]) = (0, 0); + ( USERCLK => MIMRXWDATA[56]) = (0, 0); + ( USERCLK => MIMRXWDATA[57]) = (0, 0); + ( USERCLK => MIMRXWDATA[58]) = (0, 0); + ( USERCLK => MIMRXWDATA[59]) = (0, 0); + ( USERCLK => MIMRXWDATA[5]) = (0, 0); + ( USERCLK => MIMRXWDATA[60]) = (0, 0); + ( USERCLK => MIMRXWDATA[61]) = (0, 0); + ( USERCLK => MIMRXWDATA[62]) = (0, 0); + ( USERCLK => MIMRXWDATA[63]) = (0, 0); + ( USERCLK => MIMRXWDATA[64]) = (0, 0); + ( USERCLK => MIMRXWDATA[65]) = (0, 0); + ( USERCLK => MIMRXWDATA[66]) = (0, 0); + ( USERCLK => MIMRXWDATA[67]) = (0, 0); + ( USERCLK => MIMRXWDATA[6]) = (0, 0); + ( USERCLK => MIMRXWDATA[7]) = (0, 0); + ( USERCLK => MIMRXWDATA[8]) = (0, 0); + ( USERCLK => MIMRXWDATA[9]) = (0, 0); + ( USERCLK => MIMRXWEN) = (0, 0); + ( USERCLK => MIMTXRADDR[0]) = (0, 0); + ( USERCLK => MIMTXRADDR[10]) = (0, 0); + ( USERCLK => MIMTXRADDR[11]) = (0, 0); + ( USERCLK => MIMTXRADDR[12]) = (0, 0); + ( USERCLK => MIMTXRADDR[1]) = (0, 0); + ( USERCLK => MIMTXRADDR[2]) = (0, 0); + ( USERCLK => MIMTXRADDR[3]) = (0, 0); + ( USERCLK => MIMTXRADDR[4]) = (0, 0); + ( USERCLK => MIMTXRADDR[5]) = (0, 0); + ( USERCLK => MIMTXRADDR[6]) = (0, 0); + ( USERCLK => MIMTXRADDR[7]) = (0, 0); + ( USERCLK => MIMTXRADDR[8]) = (0, 0); + ( USERCLK => MIMTXRADDR[9]) = (0, 0); + ( USERCLK => MIMTXRCE) = (0, 0); + ( USERCLK => MIMTXREN) = (0, 0); + ( USERCLK => MIMTXWADDR[0]) = (0, 0); + ( USERCLK => MIMTXWADDR[10]) = (0, 0); + ( USERCLK => MIMTXWADDR[11]) = (0, 0); + ( USERCLK => MIMTXWADDR[12]) = (0, 0); + ( USERCLK => MIMTXWADDR[1]) = (0, 0); + ( USERCLK => MIMTXWADDR[2]) = (0, 0); + ( USERCLK => MIMTXWADDR[3]) = (0, 0); + ( USERCLK => MIMTXWADDR[4]) = (0, 0); + ( USERCLK => MIMTXWADDR[5]) = (0, 0); + ( USERCLK => MIMTXWADDR[6]) = (0, 0); + ( USERCLK => MIMTXWADDR[7]) = (0, 0); + ( USERCLK => MIMTXWADDR[8]) = (0, 0); + ( USERCLK => MIMTXWADDR[9]) = (0, 0); + ( USERCLK => MIMTXWDATA[0]) = (0, 0); + ( USERCLK => MIMTXWDATA[10]) = (0, 0); + ( USERCLK => MIMTXWDATA[11]) = (0, 0); + ( USERCLK => MIMTXWDATA[12]) = (0, 0); + ( USERCLK => MIMTXWDATA[13]) = (0, 0); + ( USERCLK => MIMTXWDATA[14]) = (0, 0); + ( USERCLK => MIMTXWDATA[15]) = (0, 0); + ( USERCLK => MIMTXWDATA[16]) = (0, 0); + ( USERCLK => MIMTXWDATA[17]) = (0, 0); + ( USERCLK => MIMTXWDATA[18]) = (0, 0); + ( USERCLK => MIMTXWDATA[19]) = (0, 0); + ( USERCLK => MIMTXWDATA[1]) = (0, 0); + ( USERCLK => MIMTXWDATA[20]) = (0, 0); + ( USERCLK => MIMTXWDATA[21]) = (0, 0); + ( USERCLK => MIMTXWDATA[22]) = (0, 0); + ( USERCLK => MIMTXWDATA[23]) = (0, 0); + ( USERCLK => MIMTXWDATA[24]) = (0, 0); + ( USERCLK => MIMTXWDATA[25]) = (0, 0); + ( USERCLK => MIMTXWDATA[26]) = (0, 0); + ( USERCLK => MIMTXWDATA[27]) = (0, 0); + ( USERCLK => MIMTXWDATA[28]) = (0, 0); + ( USERCLK => MIMTXWDATA[29]) = (0, 0); + ( USERCLK => MIMTXWDATA[2]) = (0, 0); + ( USERCLK => MIMTXWDATA[30]) = (0, 0); + ( USERCLK => MIMTXWDATA[31]) = (0, 0); + ( USERCLK => MIMTXWDATA[32]) = (0, 0); + ( USERCLK => MIMTXWDATA[33]) = (0, 0); + ( USERCLK => MIMTXWDATA[34]) = (0, 0); + ( USERCLK => MIMTXWDATA[35]) = (0, 0); + ( USERCLK => MIMTXWDATA[36]) = (0, 0); + ( USERCLK => MIMTXWDATA[37]) = (0, 0); + ( USERCLK => MIMTXWDATA[38]) = (0, 0); + ( USERCLK => MIMTXWDATA[39]) = (0, 0); + ( USERCLK => MIMTXWDATA[3]) = (0, 0); + ( USERCLK => MIMTXWDATA[40]) = (0, 0); + ( USERCLK => MIMTXWDATA[41]) = (0, 0); + ( USERCLK => MIMTXWDATA[42]) = (0, 0); + ( USERCLK => MIMTXWDATA[43]) = (0, 0); + ( USERCLK => MIMTXWDATA[44]) = (0, 0); + ( USERCLK => MIMTXWDATA[45]) = (0, 0); + ( USERCLK => MIMTXWDATA[46]) = (0, 0); + ( USERCLK => MIMTXWDATA[47]) = (0, 0); + ( USERCLK => MIMTXWDATA[48]) = (0, 0); + ( USERCLK => MIMTXWDATA[49]) = (0, 0); + ( USERCLK => MIMTXWDATA[4]) = (0, 0); + ( USERCLK => MIMTXWDATA[50]) = (0, 0); + ( USERCLK => MIMTXWDATA[51]) = (0, 0); + ( USERCLK => MIMTXWDATA[52]) = (0, 0); + ( USERCLK => MIMTXWDATA[53]) = (0, 0); + ( USERCLK => MIMTXWDATA[54]) = (0, 0); + ( USERCLK => MIMTXWDATA[55]) = (0, 0); + ( USERCLK => MIMTXWDATA[56]) = (0, 0); + ( USERCLK => MIMTXWDATA[57]) = (0, 0); + ( USERCLK => MIMTXWDATA[58]) = (0, 0); + ( USERCLK => MIMTXWDATA[59]) = (0, 0); + ( USERCLK => MIMTXWDATA[5]) = (0, 0); + ( USERCLK => MIMTXWDATA[60]) = (0, 0); + ( USERCLK => MIMTXWDATA[61]) = (0, 0); + ( USERCLK => MIMTXWDATA[62]) = (0, 0); + ( USERCLK => MIMTXWDATA[63]) = (0, 0); + ( USERCLK => MIMTXWDATA[64]) = (0, 0); + ( USERCLK => MIMTXWDATA[65]) = (0, 0); + ( USERCLK => MIMTXWDATA[66]) = (0, 0); + ( USERCLK => MIMTXWDATA[67]) = (0, 0); + ( USERCLK => MIMTXWDATA[68]) = (0, 0); + ( USERCLK => MIMTXWDATA[6]) = (0, 0); + ( USERCLK => MIMTXWDATA[7]) = (0, 0); + ( USERCLK => MIMTXWDATA[8]) = (0, 0); + ( USERCLK => MIMTXWDATA[9]) = (0, 0); + ( USERCLK => MIMTXWEN) = (0, 0); + ( USERCLK => PL2LINKUPN) = (0, 0); + ( USERCLK => PL2RECEIVERERRN) = (0, 0); + ( USERCLK => PL2RECOVERYN) = (0, 0); + ( USERCLK => PL2RXELECIDLE) = (0, 0); + ( USERCLK => PL2SUSPENDOK) = (0, 0); + ( USERCLK => RECEIVEDFUNCLVLRSTN) = (0, 0); + ( USERCLK => TL2ASPMSUSPENDCREDITCHECKOKN) = (0, 0); + ( USERCLK => TL2ASPMSUSPENDREQN) = (0, 0); + ( USERCLK => TL2PPMSUSPENDOKN) = (0, 0); + ( USERCLK => TRNFCCPLD[0]) = (0, 0); + ( USERCLK => TRNFCCPLD[10]) = (0, 0); + ( USERCLK => TRNFCCPLD[11]) = (0, 0); + ( USERCLK => TRNFCCPLD[1]) = (0, 0); + ( USERCLK => TRNFCCPLD[2]) = (0, 0); + ( USERCLK => TRNFCCPLD[3]) = (0, 0); + ( USERCLK => TRNFCCPLD[4]) = (0, 0); + ( USERCLK => TRNFCCPLD[5]) = (0, 0); + ( USERCLK => TRNFCCPLD[6]) = (0, 0); + ( USERCLK => TRNFCCPLD[7]) = (0, 0); + ( USERCLK => TRNFCCPLD[8]) = (0, 0); + ( USERCLK => TRNFCCPLD[9]) = (0, 0); + ( USERCLK => TRNFCCPLH[0]) = (0, 0); + ( USERCLK => TRNFCCPLH[1]) = (0, 0); + ( USERCLK => TRNFCCPLH[2]) = (0, 0); + ( USERCLK => TRNFCCPLH[3]) = (0, 0); + ( USERCLK => TRNFCCPLH[4]) = (0, 0); + ( USERCLK => TRNFCCPLH[5]) = (0, 0); + ( USERCLK => TRNFCCPLH[6]) = (0, 0); + ( USERCLK => TRNFCCPLH[7]) = (0, 0); + ( USERCLK => TRNFCNPD[0]) = (0, 0); + ( USERCLK => TRNFCNPD[10]) = (0, 0); + ( USERCLK => TRNFCNPD[11]) = (0, 0); + ( USERCLK => TRNFCNPD[1]) = (0, 0); + ( USERCLK => TRNFCNPD[2]) = (0, 0); + ( USERCLK => TRNFCNPD[3]) = (0, 0); + ( USERCLK => TRNFCNPD[4]) = (0, 0); + ( USERCLK => TRNFCNPD[5]) = (0, 0); + ( USERCLK => TRNFCNPD[6]) = (0, 0); + ( USERCLK => TRNFCNPD[7]) = (0, 0); + ( USERCLK => TRNFCNPD[8]) = (0, 0); + ( USERCLK => TRNFCNPD[9]) = (0, 0); + ( USERCLK => TRNFCNPH[0]) = (0, 0); + ( USERCLK => TRNFCNPH[1]) = (0, 0); + ( USERCLK => TRNFCNPH[2]) = (0, 0); + ( USERCLK => TRNFCNPH[3]) = (0, 0); + ( USERCLK => TRNFCNPH[4]) = (0, 0); + ( USERCLK => TRNFCNPH[5]) = (0, 0); + ( USERCLK => TRNFCNPH[6]) = (0, 0); + ( USERCLK => TRNFCNPH[7]) = (0, 0); + ( USERCLK => TRNFCPD[0]) = (0, 0); + ( USERCLK => TRNFCPD[10]) = (0, 0); + ( USERCLK => TRNFCPD[11]) = (0, 0); + ( USERCLK => TRNFCPD[1]) = (0, 0); + ( USERCLK => TRNFCPD[2]) = (0, 0); + ( USERCLK => TRNFCPD[3]) = (0, 0); + ( USERCLK => TRNFCPD[4]) = (0, 0); + ( USERCLK => TRNFCPD[5]) = (0, 0); + ( USERCLK => TRNFCPD[6]) = (0, 0); + ( USERCLK => TRNFCPD[7]) = (0, 0); + ( USERCLK => TRNFCPD[8]) = (0, 0); + ( USERCLK => TRNFCPD[9]) = (0, 0); + ( USERCLK => TRNFCPH[0]) = (0, 0); + ( USERCLK => TRNFCPH[1]) = (0, 0); + ( USERCLK => TRNFCPH[2]) = (0, 0); + ( USERCLK => TRNFCPH[3]) = (0, 0); + ( USERCLK => TRNFCPH[4]) = (0, 0); + ( USERCLK => TRNFCPH[5]) = (0, 0); + ( USERCLK => TRNFCPH[6]) = (0, 0); + ( USERCLK => TRNFCPH[7]) = (0, 0); + ( USERCLK => TRNLNKUPN) = (0, 0); + ( USERCLK => TRNRBARHITN[0]) = (0, 0); + ( USERCLK => TRNRBARHITN[1]) = (0, 0); + ( USERCLK => TRNRBARHITN[2]) = (0, 0); + ( USERCLK => TRNRBARHITN[3]) = (0, 0); + ( USERCLK => TRNRBARHITN[4]) = (0, 0); + ( USERCLK => TRNRBARHITN[5]) = (0, 0); + ( USERCLK => TRNRBARHITN[6]) = (0, 0); + ( USERCLK => TRNRDLLPDATA[0]) = (0, 0); + ( USERCLK => TRNRDLLPDATA[10]) = (0, 0); + ( USERCLK => TRNRDLLPDATA[11]) = (0, 0); + ( USERCLK => TRNRDLLPDATA[12]) = (0, 0); + ( USERCLK => TRNRDLLPDATA[13]) = (0, 0); + ( USERCLK => TRNRDLLPDATA[14]) = (0, 0); + ( USERCLK => TRNRDLLPDATA[15]) = (0, 0); + ( USERCLK => TRNRDLLPDATA[16]) = (0, 0); + ( USERCLK => TRNRDLLPDATA[17]) = (0, 0); + ( USERCLK => TRNRDLLPDATA[18]) = (0, 0); + ( USERCLK => TRNRDLLPDATA[19]) = (0, 0); + ( USERCLK => TRNRDLLPDATA[1]) = (0, 0); + ( USERCLK => TRNRDLLPDATA[20]) = (0, 0); + ( USERCLK => TRNRDLLPDATA[21]) = (0, 0); + ( USERCLK => TRNRDLLPDATA[22]) = (0, 0); + ( USERCLK => TRNRDLLPDATA[23]) = (0, 0); + ( USERCLK => TRNRDLLPDATA[24]) = (0, 0); + ( USERCLK => TRNRDLLPDATA[25]) = (0, 0); + ( USERCLK => TRNRDLLPDATA[26]) = (0, 0); + ( USERCLK => TRNRDLLPDATA[27]) = (0, 0); + ( USERCLK => TRNRDLLPDATA[28]) = (0, 0); + ( USERCLK => TRNRDLLPDATA[29]) = (0, 0); + ( USERCLK => TRNRDLLPDATA[2]) = (0, 0); + ( USERCLK => TRNRDLLPDATA[30]) = (0, 0); + ( USERCLK => TRNRDLLPDATA[31]) = (0, 0); + ( USERCLK => TRNRDLLPDATA[3]) = (0, 0); + ( USERCLK => TRNRDLLPDATA[4]) = (0, 0); + ( USERCLK => TRNRDLLPDATA[5]) = (0, 0); + ( USERCLK => TRNRDLLPDATA[6]) = (0, 0); + ( USERCLK => TRNRDLLPDATA[7]) = (0, 0); + ( USERCLK => TRNRDLLPDATA[8]) = (0, 0); + ( USERCLK => TRNRDLLPDATA[9]) = (0, 0); + ( USERCLK => TRNRDLLPSRCRDYN) = (0, 0); + ( USERCLK => TRNRD[0]) = (0, 0); + ( USERCLK => TRNRD[10]) = (0, 0); + ( USERCLK => TRNRD[11]) = (0, 0); + ( USERCLK => TRNRD[12]) = (0, 0); + ( USERCLK => TRNRD[13]) = (0, 0); + ( USERCLK => TRNRD[14]) = (0, 0); + ( USERCLK => TRNRD[15]) = (0, 0); + ( USERCLK => TRNRD[16]) = (0, 0); + ( USERCLK => TRNRD[17]) = (0, 0); + ( USERCLK => TRNRD[18]) = (0, 0); + ( USERCLK => TRNRD[19]) = (0, 0); + ( USERCLK => TRNRD[1]) = (0, 0); + ( USERCLK => TRNRD[20]) = (0, 0); + ( USERCLK => TRNRD[21]) = (0, 0); + ( USERCLK => TRNRD[22]) = (0, 0); + ( USERCLK => TRNRD[23]) = (0, 0); + ( USERCLK => TRNRD[24]) = (0, 0); + ( USERCLK => TRNRD[25]) = (0, 0); + ( USERCLK => TRNRD[26]) = (0, 0); + ( USERCLK => TRNRD[27]) = (0, 0); + ( USERCLK => TRNRD[28]) = (0, 0); + ( USERCLK => TRNRD[29]) = (0, 0); + ( USERCLK => TRNRD[2]) = (0, 0); + ( USERCLK => TRNRD[30]) = (0, 0); + ( USERCLK => TRNRD[31]) = (0, 0); + ( USERCLK => TRNRD[32]) = (0, 0); + ( USERCLK => TRNRD[33]) = (0, 0); + ( USERCLK => TRNRD[34]) = (0, 0); + ( USERCLK => TRNRD[35]) = (0, 0); + ( USERCLK => TRNRD[36]) = (0, 0); + ( USERCLK => TRNRD[37]) = (0, 0); + ( USERCLK => TRNRD[38]) = (0, 0); + ( USERCLK => TRNRD[39]) = (0, 0); + ( USERCLK => TRNRD[3]) = (0, 0); + ( USERCLK => TRNRD[40]) = (0, 0); + ( USERCLK => TRNRD[41]) = (0, 0); + ( USERCLK => TRNRD[42]) = (0, 0); + ( USERCLK => TRNRD[43]) = (0, 0); + ( USERCLK => TRNRD[44]) = (0, 0); + ( USERCLK => TRNRD[45]) = (0, 0); + ( USERCLK => TRNRD[46]) = (0, 0); + ( USERCLK => TRNRD[47]) = (0, 0); + ( USERCLK => TRNRD[48]) = (0, 0); + ( USERCLK => TRNRD[49]) = (0, 0); + ( USERCLK => TRNRD[4]) = (0, 0); + ( USERCLK => TRNRD[50]) = (0, 0); + ( USERCLK => TRNRD[51]) = (0, 0); + ( USERCLK => TRNRD[52]) = (0, 0); + ( USERCLK => TRNRD[53]) = (0, 0); + ( USERCLK => TRNRD[54]) = (0, 0); + ( USERCLK => TRNRD[55]) = (0, 0); + ( USERCLK => TRNRD[56]) = (0, 0); + ( USERCLK => TRNRD[57]) = (0, 0); + ( USERCLK => TRNRD[58]) = (0, 0); + ( USERCLK => TRNRD[59]) = (0, 0); + ( USERCLK => TRNRD[5]) = (0, 0); + ( USERCLK => TRNRD[60]) = (0, 0); + ( USERCLK => TRNRD[61]) = (0, 0); + ( USERCLK => TRNRD[62]) = (0, 0); + ( USERCLK => TRNRD[63]) = (0, 0); + ( USERCLK => TRNRD[6]) = (0, 0); + ( USERCLK => TRNRD[7]) = (0, 0); + ( USERCLK => TRNRD[8]) = (0, 0); + ( USERCLK => TRNRD[9]) = (0, 0); + ( USERCLK => TRNRECRCERRN) = (0, 0); + ( USERCLK => TRNREOFN) = (0, 0); + ( USERCLK => TRNRERRFWDN) = (0, 0); + ( USERCLK => TRNRREMN) = (0, 0); + ( USERCLK => TRNRSOFN) = (0, 0); + ( USERCLK => TRNRSRCDSCN) = (0, 0); + ( USERCLK => TRNRSRCRDYN) = (0, 0); + ( USERCLK => TRNTBUFAV[0]) = (0, 0); + ( USERCLK => TRNTBUFAV[1]) = (0, 0); + ( USERCLK => TRNTBUFAV[2]) = (0, 0); + ( USERCLK => TRNTBUFAV[3]) = (0, 0); + ( USERCLK => TRNTBUFAV[4]) = (0, 0); + ( USERCLK => TRNTBUFAV[5]) = (0, 0); + ( USERCLK => TRNTCFGREQN) = (0, 0); + ( USERCLK => TRNTDLLPDSTRDYN) = (0, 0); + ( USERCLK => TRNTDSTRDYN) = (0, 0); + ( USERCLK => TRNTERRDROPN) = (0, 0); + ( USERCLK => USERRSTN) = (0, 0); + + specparam PATHPULSE$ = 0; + endspecify +endmodule diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/PCIE_A1.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/PCIE_A1.v new file mode 100644 index 0000000..2f75f19 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/PCIE_A1.v @@ -0,0 +1,2282 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/stan/PCIE_A1.v,v 1.9 2010/02/03 23:42:05 robh Exp $ +/////////////////////////////////////////////////////// +// Copyright (c) 2009 Xilinx Inc. +// All Right Reserved. +/////////////////////////////////////////////////////// +// +// ____ ___ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : PCI Express Secure IP Functional Wrapper +// / / +// /__/ /\ Filename : PCIE_A1.v +// \ \ / \ +// \__\/\__ \ +// +// Revision: Date: Comment +// 1.0: 08/21/08: Initial version. +// 1.1: 11/24/08: Updates to include secureip +// 1.2: 01/22/09: Updates for NCSIM and VCS +// 1.3: 01/29/09: CR503397 remove NCELAB work arounds +// 1.4: 02/03/10: 525925 add skew and period checks. +// End Revision +/////////////////////////////////////////////////////// + +`timescale 1 ps / 1 ps + +module PCIE_A1 ( + CFGBUSNUMBER, + CFGCOMMANDBUSMASTERENABLE, + CFGCOMMANDINTERRUPTDISABLE, + CFGCOMMANDIOENABLE, + CFGCOMMANDMEMENABLE, + CFGCOMMANDSERREN, + CFGDEVCONTROLAUXPOWEREN, + CFGDEVCONTROLCORRERRREPORTINGEN, + CFGDEVCONTROLENABLERO, + CFGDEVCONTROLEXTTAGEN, + CFGDEVCONTROLFATALERRREPORTINGEN, + CFGDEVCONTROLMAXPAYLOAD, + CFGDEVCONTROLMAXREADREQ, + CFGDEVCONTROLNONFATALREPORTINGEN, + CFGDEVCONTROLNOSNOOPEN, + CFGDEVCONTROLPHANTOMEN, + CFGDEVCONTROLURERRREPORTINGEN, + CFGDEVICENUMBER, + CFGDEVSTATUSCORRERRDETECTED, + CFGDEVSTATUSFATALERRDETECTED, + CFGDEVSTATUSNONFATALERRDETECTED, + CFGDEVSTATUSURDETECTED, + CFGDO, + CFGERRCPLRDYN, + CFGFUNCTIONNUMBER, + CFGINTERRUPTDO, + CFGINTERRUPTMMENABLE, + CFGINTERRUPTMSIENABLE, + CFGINTERRUPTRDYN, + CFGLINKCONTOLRCB, + CFGLINKCONTROLASPMCONTROL, + CFGLINKCONTROLCOMMONCLOCK, + CFGLINKCONTROLEXTENDEDSYNC, + CFGLTSSMSTATE, + CFGPCIELINKSTATEN, + CFGRDWRDONEN, + CFGTOTURNOFFN, + DBGBADDLLPSTATUS, + DBGBADTLPLCRC, + DBGBADTLPSEQNUM, + DBGBADTLPSTATUS, + DBGDLPROTOCOLSTATUS, + DBGFCPROTOCOLERRSTATUS, + DBGMLFRMDLENGTH, + DBGMLFRMDMPS, + DBGMLFRMDTCVC, + DBGMLFRMDTLPSTATUS, + DBGMLFRMDUNRECTYPE, + DBGPOISTLPSTATUS, + DBGRCVROVERFLOWSTATUS, + DBGREGDETECTEDCORRECTABLE, + DBGREGDETECTEDFATAL, + DBGREGDETECTEDNONFATAL, + DBGREGDETECTEDUNSUPPORTED, + DBGRPLYROLLOVERSTATUS, + DBGRPLYTIMEOUTSTATUS, + DBGURNOBARHIT, + DBGURPOISCFGWR, + DBGURSTATUS, + DBGURUNSUPMSG, + MIMRXRADDR, + MIMRXREN, + MIMRXWADDR, + MIMRXWDATA, + MIMRXWEN, + MIMTXRADDR, + MIMTXREN, + MIMTXWADDR, + MIMTXWDATA, + MIMTXWEN, + PIPEGTPOWERDOWNA, + PIPEGTPOWERDOWNB, + PIPEGTTXELECIDLEA, + PIPEGTTXELECIDLEB, + PIPERXPOLARITYA, + PIPERXPOLARITYB, + PIPERXRESETA, + PIPERXRESETB, + PIPETXCHARDISPMODEA, + PIPETXCHARDISPMODEB, + PIPETXCHARDISPVALA, + PIPETXCHARDISPVALB, + PIPETXCHARISKA, + PIPETXCHARISKB, + PIPETXDATAA, + PIPETXDATAB, + PIPETXRCVRDETA, + PIPETXRCVRDETB, + RECEIVEDHOTRESET, + TRNFCCPLD, + TRNFCCPLH, + TRNFCNPD, + TRNFCNPH, + TRNFCPD, + TRNFCPH, + TRNLNKUPN, + TRNRBARHITN, + TRNRD, + TRNREOFN, + TRNRERRFWDN, + TRNRSOFN, + TRNRSRCDSCN, + TRNRSRCRDYN, + TRNTBUFAV, + TRNTCFGREQN, + TRNTDSTRDYN, + TRNTERRDROPN, + USERRSTN, + CFGDEVID, + CFGDSN, + CFGDWADDR, + CFGERRCORN, + CFGERRCPLABORTN, + CFGERRCPLTIMEOUTN, + CFGERRECRCN, + CFGERRLOCKEDN, + CFGERRPOSTEDN, + CFGERRTLPCPLHEADER, + CFGERRURN, + CFGINTERRUPTASSERTN, + CFGINTERRUPTDI, + CFGINTERRUPTN, + CFGPMWAKEN, + CFGRDENN, + CFGREVID, + CFGSUBSYSID, + CFGSUBSYSVENID, + CFGTRNPENDINGN, + CFGTURNOFFOKN, + CFGVENID, + CLOCKLOCKED, + MGTCLK, + MIMRXRDATA, + MIMTXRDATA, + PIPEGTRESETDONEA, + PIPEGTRESETDONEB, + PIPEPHYSTATUSA, + PIPEPHYSTATUSB, + PIPERXCHARISKA, + PIPERXCHARISKB, + PIPERXDATAA, + PIPERXDATAB, + PIPERXENTERELECIDLEA, + PIPERXENTERELECIDLEB, + PIPERXSTATUSA, + PIPERXSTATUSB, + SYSRESETN, + TRNFCSEL, + TRNRDSTRDYN, + TRNRNPOKN, + TRNTCFGGNTN, + TRNTD, + TRNTEOFN, + TRNTERRFWDN, + TRNTSOFN, + TRNTSRCDSCN, + TRNTSRCRDYN, + TRNTSTRN, + USERCLK +); + + parameter [31:0] BAR0 = 32'h00000000; + parameter [31:0] BAR1 = 32'h00000000; + parameter [31:0] BAR2 = 32'h00000000; + parameter [31:0] BAR3 = 32'h00000000; + parameter [31:0] BAR4 = 32'h00000000; + parameter [31:0] BAR5 = 32'h00000000; + parameter [31:0] CARDBUS_CIS_POINTER = 32'h00000000; + parameter [23:0] CLASS_CODE = 24'h000000; + parameter integer DEV_CAP_ENDPOINT_L0S_LATENCY = 7; + parameter integer DEV_CAP_ENDPOINT_L1_LATENCY = 7; + parameter DEV_CAP_EXT_TAG_SUPPORTED = "FALSE"; + parameter integer DEV_CAP_MAX_PAYLOAD_SUPPORTED = 2; + parameter integer DEV_CAP_PHANTOM_FUNCTIONS_SUPPORT = 0; + parameter DEV_CAP_ROLE_BASED_ERROR = "TRUE"; + parameter DISABLE_BAR_FILTERING = "FALSE"; + parameter DISABLE_ID_CHECK = "FALSE"; + parameter DISABLE_SCRAMBLING = "FALSE"; + parameter ENABLE_RX_TD_ECRC_TRIM = "FALSE"; + parameter [21:0] EXPANSION_ROM = 22'h000000; + parameter FAST_TRAIN = "FALSE"; + parameter integer GTP_SEL = 0; + parameter integer LINK_CAP_ASPM_SUPPORT = 1; + parameter integer LINK_CAP_L0S_EXIT_LATENCY = 7; + parameter integer LINK_CAP_L1_EXIT_LATENCY = 7; + parameter LINK_STATUS_SLOT_CLOCK_CONFIG = "FALSE"; + parameter [14:0] LL_ACK_TIMEOUT = 15'h0204; + parameter LL_ACK_TIMEOUT_EN = "FALSE"; + parameter [14:0] LL_REPLAY_TIMEOUT = 15'h060D; + parameter LL_REPLAY_TIMEOUT_EN = "FALSE"; + parameter integer MSI_CAP_MULTIMSGCAP = 0; + parameter integer MSI_CAP_MULTIMSG_EXTENSION = 0; + parameter [3:0] PCIE_CAP_CAPABILITY_VERSION = 4'h1; + parameter [3:0] PCIE_CAP_DEVICE_PORT_TYPE = 4'h0; + parameter [4:0] PCIE_CAP_INT_MSG_NUM = 5'b00000; + parameter PCIE_CAP_SLOT_IMPLEMENTED = "FALSE"; + parameter [11:0] PCIE_GENERIC = 12'h000; + parameter PLM_AUTO_CONFIG = "FALSE"; + parameter integer PM_CAP_AUXCURRENT = 0; + parameter PM_CAP_D1SUPPORT = "TRUE"; + parameter PM_CAP_D2SUPPORT = "TRUE"; + parameter PM_CAP_DSI = "FALSE"; + parameter [4:0] PM_CAP_PMESUPPORT = 5'b01111; + parameter PM_CAP_PME_CLOCK = "FALSE"; + parameter integer PM_CAP_VERSION = 3; + parameter [7:0] PM_DATA0 = 8'h1E; + parameter [7:0] PM_DATA1 = 8'h1E; + parameter [7:0] PM_DATA2 = 8'h1E; + parameter [7:0] PM_DATA3 = 8'h1E; + parameter [7:0] PM_DATA4 = 8'h1E; + parameter [7:0] PM_DATA5 = 8'h1E; + parameter [7:0] PM_DATA6 = 8'h1E; + parameter [7:0] PM_DATA7 = 8'h1E; + parameter [1:0] PM_DATA_SCALE0 = 2'b01; + parameter [1:0] PM_DATA_SCALE1 = 2'b01; + parameter [1:0] PM_DATA_SCALE2 = 2'b01; + parameter [1:0] PM_DATA_SCALE3 = 2'b01; + parameter [1:0] PM_DATA_SCALE4 = 2'b01; + parameter [1:0] PM_DATA_SCALE5 = 2'b01; + parameter [1:0] PM_DATA_SCALE6 = 2'b01; + parameter [1:0] PM_DATA_SCALE7 = 2'b01; + parameter SIM_VERSION = "1.0"; + parameter SLOT_CAP_ATT_BUTTON_PRESENT = "FALSE"; + parameter SLOT_CAP_ATT_INDICATOR_PRESENT = "FALSE"; + parameter SLOT_CAP_POWER_INDICATOR_PRESENT = "FALSE"; + parameter integer TL_RX_RAM_RADDR_LATENCY = 1; + parameter integer TL_RX_RAM_RDATA_LATENCY = 2; + parameter integer TL_RX_RAM_WRITE_LATENCY = 0; + parameter TL_TFC_DISABLE = "FALSE"; + parameter TL_TX_CHECKS_DISABLE = "FALSE"; + parameter integer TL_TX_RAM_RADDR_LATENCY = 0; + parameter integer TL_TX_RAM_RDATA_LATENCY = 2; + parameter USR_CFG = "FALSE"; + parameter USR_EXT_CFG = "FALSE"; + parameter VC0_CPL_INFINITE = "TRUE"; + parameter [11:0] VC0_RX_RAM_LIMIT = 12'h01E; + parameter integer VC0_TOTAL_CREDITS_CD = 104; + parameter integer VC0_TOTAL_CREDITS_CH = 36; + parameter integer VC0_TOTAL_CREDITS_NPH = 8; + parameter integer VC0_TOTAL_CREDITS_PD = 288; + parameter integer VC0_TOTAL_CREDITS_PH = 32; + parameter integer VC0_TX_LASTPACKET = 31; + + localparam in_delay = 0; + localparam out_delay = 0; + localparam INCLK_DELAY = 0; + localparam OUTCLK_DELAY = 0; + localparam MODULE_NAME = "PCIE_A1"; + + output CFGCOMMANDBUSMASTERENABLE; + output CFGCOMMANDINTERRUPTDISABLE; + output CFGCOMMANDIOENABLE; + output CFGCOMMANDMEMENABLE; + output CFGCOMMANDSERREN; + output CFGDEVCONTROLAUXPOWEREN; + output CFGDEVCONTROLCORRERRREPORTINGEN; + output CFGDEVCONTROLENABLERO; + output CFGDEVCONTROLEXTTAGEN; + output CFGDEVCONTROLFATALERRREPORTINGEN; + output CFGDEVCONTROLNONFATALREPORTINGEN; + output CFGDEVCONTROLNOSNOOPEN; + output CFGDEVCONTROLPHANTOMEN; + output CFGDEVCONTROLURERRREPORTINGEN; + output CFGDEVSTATUSCORRERRDETECTED; + output CFGDEVSTATUSFATALERRDETECTED; + output CFGDEVSTATUSNONFATALERRDETECTED; + output CFGDEVSTATUSURDETECTED; + output CFGERRCPLRDYN; + output CFGINTERRUPTMSIENABLE; + output CFGINTERRUPTRDYN; + output CFGLINKCONTOLRCB; + output CFGLINKCONTROLCOMMONCLOCK; + output CFGLINKCONTROLEXTENDEDSYNC; + output CFGRDWRDONEN; + output CFGTOTURNOFFN; + output DBGBADDLLPSTATUS; + output DBGBADTLPLCRC; + output DBGBADTLPSEQNUM; + output DBGBADTLPSTATUS; + output DBGDLPROTOCOLSTATUS; + output DBGFCPROTOCOLERRSTATUS; + output DBGMLFRMDLENGTH; + output DBGMLFRMDMPS; + output DBGMLFRMDTCVC; + output DBGMLFRMDTLPSTATUS; + output DBGMLFRMDUNRECTYPE; + output DBGPOISTLPSTATUS; + output DBGRCVROVERFLOWSTATUS; + output DBGREGDETECTEDCORRECTABLE; + output DBGREGDETECTEDFATAL; + output DBGREGDETECTEDNONFATAL; + output DBGREGDETECTEDUNSUPPORTED; + output DBGRPLYROLLOVERSTATUS; + output DBGRPLYTIMEOUTSTATUS; + output DBGURNOBARHIT; + output DBGURPOISCFGWR; + output DBGURSTATUS; + output DBGURUNSUPMSG; + output MIMRXREN; + output MIMRXWEN; + output MIMTXREN; + output MIMTXWEN; + output PIPEGTTXELECIDLEA; + output PIPEGTTXELECIDLEB; + output PIPERXPOLARITYA; + output PIPERXPOLARITYB; + output PIPERXRESETA; + output PIPERXRESETB; + output PIPETXRCVRDETA; + output PIPETXRCVRDETB; + output RECEIVEDHOTRESET; + output TRNLNKUPN; + output TRNREOFN; + output TRNRERRFWDN; + output TRNRSOFN; + output TRNRSRCDSCN; + output TRNRSRCRDYN; + output TRNTCFGREQN; + output TRNTDSTRDYN; + output TRNTERRDROPN; + output USERRSTN; + output [11:0] MIMRXRADDR; + output [11:0] MIMRXWADDR; + output [11:0] MIMTXRADDR; + output [11:0] MIMTXWADDR; + output [11:0] TRNFCCPLD; + output [11:0] TRNFCNPD; + output [11:0] TRNFCPD; + output [15:0] PIPETXDATAA; + output [15:0] PIPETXDATAB; + output [1:0] CFGLINKCONTROLASPMCONTROL; + output [1:0] PIPEGTPOWERDOWNA; + output [1:0] PIPEGTPOWERDOWNB; + output [1:0] PIPETXCHARDISPMODEA; + output [1:0] PIPETXCHARDISPMODEB; + output [1:0] PIPETXCHARDISPVALA; + output [1:0] PIPETXCHARDISPVALB; + output [1:0] PIPETXCHARISKA; + output [1:0] PIPETXCHARISKB; + output [2:0] CFGDEVCONTROLMAXPAYLOAD; + output [2:0] CFGDEVCONTROLMAXREADREQ; + output [2:0] CFGFUNCTIONNUMBER; + output [2:0] CFGINTERRUPTMMENABLE; + output [2:0] CFGPCIELINKSTATEN; + output [31:0] CFGDO; + output [31:0] TRNRD; + output [34:0] MIMRXWDATA; + output [35:0] MIMTXWDATA; + output [4:0] CFGDEVICENUMBER; + output [4:0] CFGLTSSMSTATE; + output [5:0] TRNTBUFAV; + output [6:0] TRNRBARHITN; + output [7:0] CFGBUSNUMBER; + output [7:0] CFGINTERRUPTDO; + output [7:0] TRNFCCPLH; + output [7:0] TRNFCNPH; + output [7:0] TRNFCPH; + + input CFGERRCORN; + input CFGERRCPLABORTN; + input CFGERRCPLTIMEOUTN; + input CFGERRECRCN; + input CFGERRLOCKEDN; + input CFGERRPOSTEDN; + input CFGERRURN; + input CFGINTERRUPTASSERTN; + input CFGINTERRUPTN; + input CFGPMWAKEN; + input CFGRDENN; + input CFGTRNPENDINGN; + input CFGTURNOFFOKN; + input CLOCKLOCKED; + input MGTCLK; + input PIPEGTRESETDONEA; + input PIPEGTRESETDONEB; + input PIPEPHYSTATUSA; + input PIPEPHYSTATUSB; + input PIPERXENTERELECIDLEA; + input PIPERXENTERELECIDLEB; + input SYSRESETN; + input TRNRDSTRDYN; + input TRNRNPOKN; + input TRNTCFGGNTN; + input TRNTEOFN; + input TRNTERRFWDN; + input TRNTSOFN; + input TRNTSRCDSCN; + input TRNTSRCRDYN; + input TRNTSTRN; + input USERCLK; + input [15:0] CFGDEVID; + input [15:0] CFGSUBSYSID; + input [15:0] CFGSUBSYSVENID; + input [15:0] CFGVENID; + input [15:0] PIPERXDATAA; + input [15:0] PIPERXDATAB; + input [1:0] PIPERXCHARISKA; + input [1:0] PIPERXCHARISKB; + input [2:0] PIPERXSTATUSA; + input [2:0] PIPERXSTATUSB; + input [2:0] TRNFCSEL; + input [31:0] TRNTD; + input [34:0] MIMRXRDATA; + input [35:0] MIMTXRDATA; + input [47:0] CFGERRTLPCPLHEADER; + input [63:0] CFGDSN; + input [7:0] CFGINTERRUPTDI; + input [7:0] CFGREVID; + input [9:0] CFGDWADDR; + + reg DEV_CAP_EXT_TAG_SUPPORTED_BINARY; + reg DEV_CAP_ROLE_BASED_ERROR_BINARY; + reg DISABLE_BAR_FILTERING_BINARY; + reg DISABLE_ID_CHECK_BINARY; + reg DISABLE_SCRAMBLING_BINARY; + reg ENABLE_RX_TD_ECRC_TRIM_BINARY; + reg FAST_TRAIN_BINARY; + reg GTP_SEL_BINARY; + reg LINK_STATUS_SLOT_CLOCK_CONFIG_BINARY; + reg LL_ACK_TIMEOUT_EN_BINARY; + reg LL_REPLAY_TIMEOUT_EN_BINARY; + reg MSI_CAP_MULTIMSG_EXTENSION_BINARY; + reg PCIE_CAP_SLOT_IMPLEMENTED_BINARY; + reg PLM_AUTO_CONFIG_BINARY; + reg PM_CAP_D1SUPPORT_BINARY; + reg PM_CAP_D2SUPPORT_BINARY; + reg PM_CAP_DSI_BINARY; + reg PM_CAP_PME_CLOCK_BINARY; + reg SIM_VERSION_BINARY; + reg SLOT_CAP_ATT_BUTTON_PRESENT_BINARY; + reg SLOT_CAP_ATT_INDICATOR_PRESENT_BINARY; + reg SLOT_CAP_POWER_INDICATOR_PRESENT_BINARY; + reg TL_RX_RAM_RADDR_LATENCY_BINARY; + reg TL_RX_RAM_WRITE_LATENCY_BINARY; + reg TL_TFC_DISABLE_BINARY; + reg TL_TX_CHECKS_DISABLE_BINARY; + reg TL_TX_RAM_RADDR_LATENCY_BINARY; + reg USR_CFG_BINARY; + reg USR_EXT_CFG_BINARY; + reg VC0_CPL_INFINITE_BINARY; + reg [10:0] VC0_TOTAL_CREDITS_CD_BINARY; + reg [10:0] VC0_TOTAL_CREDITS_PD_BINARY; + reg [1:0] DEV_CAP_PHANTOM_FUNCTIONS_SUPPORT_BINARY; + reg [1:0] LINK_CAP_ASPM_SUPPORT_BINARY; + reg [1:0] PM_DATA_SCALE0_BINARY; + reg [1:0] PM_DATA_SCALE1_BINARY; + reg [1:0] PM_DATA_SCALE2_BINARY; + reg [1:0] PM_DATA_SCALE3_BINARY; + reg [1:0] PM_DATA_SCALE4_BINARY; + reg [1:0] PM_DATA_SCALE5_BINARY; + reg [1:0] PM_DATA_SCALE6_BINARY; + reg [1:0] PM_DATA_SCALE7_BINARY; + reg [1:0] TL_RX_RAM_RDATA_LATENCY_BINARY; + reg [1:0] TL_TX_RAM_RDATA_LATENCY_BINARY; + reg [2:0] DEV_CAP_ENDPOINT_L0S_LATENCY_BINARY; + reg [2:0] DEV_CAP_ENDPOINT_L1_LATENCY_BINARY; + reg [2:0] DEV_CAP_MAX_PAYLOAD_SUPPORTED_BINARY; + reg [2:0] LINK_CAP_L0S_EXIT_LATENCY_BINARY; + reg [2:0] LINK_CAP_L1_EXIT_LATENCY_BINARY; + reg [2:0] MSI_CAP_MULTIMSGCAP_BINARY; + reg [2:0] PM_CAP_AUXCURRENT_BINARY; + reg [2:0] PM_CAP_VERSION_BINARY; + reg [4:0] PCIE_CAP_INT_MSG_NUM_BINARY; + reg [4:0] PM_CAP_PMESUPPORT_BINARY; + reg [4:0] VC0_TX_LASTPACKET_BINARY; + reg [6:0] VC0_TOTAL_CREDITS_CH_BINARY; + reg [6:0] VC0_TOTAL_CREDITS_NPH_BINARY; + reg [6:0] VC0_TOTAL_CREDITS_PH_BINARY; + + tri0 GSR = glbl.GSR; + wire CFGCOMMANDBUSMASTERENABLE_OUT; + wire CFGCOMMANDINTERRUPTDISABLE_OUT; + wire CFGCOMMANDIOENABLE_OUT; + wire CFGCOMMANDMEMENABLE_OUT; + wire CFGCOMMANDSERREN_OUT; + wire CFGDEVCONTROLAUXPOWEREN_OUT; + wire CFGDEVCONTROLCORRERRREPORTINGEN_OUT; + wire CFGDEVCONTROLENABLERO_OUT; + wire CFGDEVCONTROLEXTTAGEN_OUT; + wire CFGDEVCONTROLFATALERRREPORTINGEN_OUT; + wire CFGDEVCONTROLNONFATALREPORTINGEN_OUT; + wire CFGDEVCONTROLNOSNOOPEN_OUT; + wire CFGDEVCONTROLPHANTOMEN_OUT; + wire CFGDEVCONTROLURERRREPORTINGEN_OUT; + wire CFGDEVSTATUSCORRERRDETECTED_OUT; + wire CFGDEVSTATUSFATALERRDETECTED_OUT; + wire CFGDEVSTATUSNONFATALERRDETECTED_OUT; + wire CFGDEVSTATUSURDETECTED_OUT; + wire CFGERRCPLRDYN_OUT; + wire CFGINTERRUPTMSIENABLE_OUT; + wire CFGINTERRUPTRDYN_OUT; + wire CFGLINKCONTOLRCB_OUT; + wire CFGLINKCONTROLCOMMONCLOCK_OUT; + wire CFGLINKCONTROLEXTENDEDSYNC_OUT; + wire CFGRDWRDONEN_OUT; + wire CFGTOTURNOFFN_OUT; + wire DBGBADDLLPSTATUS_OUT; + wire DBGBADTLPLCRC_OUT; + wire DBGBADTLPSEQNUM_OUT; + wire DBGBADTLPSTATUS_OUT; + wire DBGDLPROTOCOLSTATUS_OUT; + wire DBGFCPROTOCOLERRSTATUS_OUT; + wire DBGMLFRMDLENGTH_OUT; + wire DBGMLFRMDMPS_OUT; + wire DBGMLFRMDTCVC_OUT; + wire DBGMLFRMDTLPSTATUS_OUT; + wire DBGMLFRMDUNRECTYPE_OUT; + wire DBGPOISTLPSTATUS_OUT; + wire DBGRCVROVERFLOWSTATUS_OUT; + wire DBGREGDETECTEDCORRECTABLE_OUT; + wire DBGREGDETECTEDFATAL_OUT; + wire DBGREGDETECTEDNONFATAL_OUT; + wire DBGREGDETECTEDUNSUPPORTED_OUT; + wire DBGRPLYROLLOVERSTATUS_OUT; + wire DBGRPLYTIMEOUTSTATUS_OUT; + wire DBGURNOBARHIT_OUT; + wire DBGURPOISCFGWR_OUT; + wire DBGURSTATUS_OUT; + wire DBGURUNSUPMSG_OUT; + wire MIMRXREN_OUT; + wire MIMRXWEN_OUT; + wire MIMTXREN_OUT; + wire MIMTXWEN_OUT; + wire PIPEGTTXELECIDLEA_OUT; + wire PIPEGTTXELECIDLEB_OUT; + wire PIPERXPOLARITYA_OUT; + wire PIPERXPOLARITYB_OUT; + wire PIPERXRESETA_OUT; + wire PIPERXRESETB_OUT; + wire PIPETXRCVRDETA_OUT; + wire PIPETXRCVRDETB_OUT; + wire RECEIVEDHOTRESET_OUT; + wire TRNLNKUPN_OUT; + wire TRNREOFN_OUT; + wire TRNRERRFWDN_OUT; + wire TRNRSOFN_OUT; + wire TRNRSRCDSCN_OUT; + wire TRNRSRCRDYN_OUT; + wire TRNTCFGREQN_OUT; + wire TRNTDSTRDYN_OUT; + wire TRNTERRDROPN_OUT; + wire USERRSTN_OUT; + wire [11:0] MIMRXRADDR_OUT; + wire [11:0] MIMRXWADDR_OUT; + wire [11:0] MIMTXRADDR_OUT; + wire [11:0] MIMTXWADDR_OUT; + wire [11:0] TRNFCCPLD_OUT; + wire [11:0] TRNFCNPD_OUT; + wire [11:0] TRNFCPD_OUT; + wire [15:0] PIPETXDATAA_OUT; + wire [15:0] PIPETXDATAB_OUT; + wire [1:0] CFGLINKCONTROLASPMCONTROL_OUT; + wire [1:0] PIPEGTPOWERDOWNA_OUT; + wire [1:0] PIPEGTPOWERDOWNB_OUT; + wire [1:0] PIPETXCHARDISPMODEA_OUT; + wire [1:0] PIPETXCHARDISPMODEB_OUT; + wire [1:0] PIPETXCHARDISPVALA_OUT; + wire [1:0] PIPETXCHARDISPVALB_OUT; + wire [1:0] PIPETXCHARISKA_OUT; + wire [1:0] PIPETXCHARISKB_OUT; + wire [2:0] CFGDEVCONTROLMAXPAYLOAD_OUT; + wire [2:0] CFGDEVCONTROLMAXREADREQ_OUT; + wire [2:0] CFGFUNCTIONNUMBER_OUT; + wire [2:0] CFGINTERRUPTMMENABLE_OUT; + wire [2:0] CFGPCIELINKSTATEN_OUT; + wire [31:0] CFGDO_OUT; + wire [31:0] TRNRD_OUT; + wire [34:0] MIMRXWDATA_OUT; + wire [35:0] MIMTXWDATA_OUT; + wire [4:0] CFGDEVICENUMBER_OUT; + wire [4:0] CFGLTSSMSTATE_OUT; + wire [5:0] TRNTBUFAV_OUT; + wire [6:0] TRNRBARHITN_OUT; + wire [7:0] CFGBUSNUMBER_OUT; + wire [7:0] CFGINTERRUPTDO_OUT; + wire [7:0] TRNFCCPLH_OUT; + wire [7:0] TRNFCNPH_OUT; + wire [7:0] TRNFCPH_OUT; + + wire CFGCOMMANDBUSMASTERENABLE_OUTDELAY; + wire CFGCOMMANDINTERRUPTDISABLE_OUTDELAY; + wire CFGCOMMANDIOENABLE_OUTDELAY; + wire CFGCOMMANDMEMENABLE_OUTDELAY; + wire CFGCOMMANDSERREN_OUTDELAY; + wire CFGDEVCONTROLAUXPOWEREN_OUTDELAY; + wire CFGDEVCONTROLCORRERRREPORTINGEN_OUTDELAY; + wire CFGDEVCONTROLENABLERO_OUTDELAY; + wire CFGDEVCONTROLEXTTAGEN_OUTDELAY; + wire CFGDEVCONTROLFATALERRREPORTINGEN_OUTDELAY; + wire CFGDEVCONTROLNONFATALREPORTINGEN_OUTDELAY; + wire CFGDEVCONTROLNOSNOOPEN_OUTDELAY; + wire CFGDEVCONTROLPHANTOMEN_OUTDELAY; + wire CFGDEVCONTROLURERRREPORTINGEN_OUTDELAY; + wire CFGDEVSTATUSCORRERRDETECTED_OUTDELAY; + wire CFGDEVSTATUSFATALERRDETECTED_OUTDELAY; + wire CFGDEVSTATUSNONFATALERRDETECTED_OUTDELAY; + wire CFGDEVSTATUSURDETECTED_OUTDELAY; + wire CFGERRCPLRDYN_OUTDELAY; + wire CFGINTERRUPTMSIENABLE_OUTDELAY; + wire CFGINTERRUPTRDYN_OUTDELAY; + wire CFGLINKCONTOLRCB_OUTDELAY; + wire CFGLINKCONTROLCOMMONCLOCK_OUTDELAY; + wire CFGLINKCONTROLEXTENDEDSYNC_OUTDELAY; + wire CFGRDWRDONEN_OUTDELAY; + wire CFGTOTURNOFFN_OUTDELAY; + wire DBGBADDLLPSTATUS_OUTDELAY; + wire DBGBADTLPLCRC_OUTDELAY; + wire DBGBADTLPSEQNUM_OUTDELAY; + wire DBGBADTLPSTATUS_OUTDELAY; + wire DBGDLPROTOCOLSTATUS_OUTDELAY; + wire DBGFCPROTOCOLERRSTATUS_OUTDELAY; + wire DBGMLFRMDLENGTH_OUTDELAY; + wire DBGMLFRMDMPS_OUTDELAY; + wire DBGMLFRMDTCVC_OUTDELAY; + wire DBGMLFRMDTLPSTATUS_OUTDELAY; + wire DBGMLFRMDUNRECTYPE_OUTDELAY; + wire DBGPOISTLPSTATUS_OUTDELAY; + wire DBGRCVROVERFLOWSTATUS_OUTDELAY; + wire DBGREGDETECTEDCORRECTABLE_OUTDELAY; + wire DBGREGDETECTEDFATAL_OUTDELAY; + wire DBGREGDETECTEDNONFATAL_OUTDELAY; + wire DBGREGDETECTEDUNSUPPORTED_OUTDELAY; + wire DBGRPLYROLLOVERSTATUS_OUTDELAY; + wire DBGRPLYTIMEOUTSTATUS_OUTDELAY; + wire DBGURNOBARHIT_OUTDELAY; + wire DBGURPOISCFGWR_OUTDELAY; + wire DBGURSTATUS_OUTDELAY; + wire DBGURUNSUPMSG_OUTDELAY; + wire MIMRXREN_OUTDELAY; + wire MIMRXWEN_OUTDELAY; + wire MIMTXREN_OUTDELAY; + wire MIMTXWEN_OUTDELAY; + wire PIPEGTTXELECIDLEA_OUTDELAY; + wire PIPEGTTXELECIDLEB_OUTDELAY; + wire PIPERXPOLARITYA_OUTDELAY; + wire PIPERXPOLARITYB_OUTDELAY; + wire PIPERXRESETA_OUTDELAY; + wire PIPERXRESETB_OUTDELAY; + wire PIPETXRCVRDETA_OUTDELAY; + wire PIPETXRCVRDETB_OUTDELAY; + wire RECEIVEDHOTRESET_OUTDELAY; + wire TRNLNKUPN_OUTDELAY; + wire TRNREOFN_OUTDELAY; + wire TRNRERRFWDN_OUTDELAY; + wire TRNRSOFN_OUTDELAY; + wire TRNRSRCDSCN_OUTDELAY; + wire TRNRSRCRDYN_OUTDELAY; + wire TRNTCFGREQN_OUTDELAY; + wire TRNTDSTRDYN_OUTDELAY; + wire TRNTERRDROPN_OUTDELAY; + wire USERRSTN_OUTDELAY; + wire [11:0] MIMRXRADDR_OUTDELAY; + wire [11:0] MIMRXWADDR_OUTDELAY; + wire [11:0] MIMTXRADDR_OUTDELAY; + wire [11:0] MIMTXWADDR_OUTDELAY; + wire [11:0] TRNFCCPLD_OUTDELAY; + wire [11:0] TRNFCNPD_OUTDELAY; + wire [11:0] TRNFCPD_OUTDELAY; + wire [15:0] PIPETXDATAA_OUTDELAY; + wire [15:0] PIPETXDATAB_OUTDELAY; + wire [1:0] CFGLINKCONTROLASPMCONTROL_OUTDELAY; + wire [1:0] PIPEGTPOWERDOWNA_OUTDELAY; + wire [1:0] PIPEGTPOWERDOWNB_OUTDELAY; + wire [1:0] PIPETXCHARDISPMODEA_OUTDELAY; + wire [1:0] PIPETXCHARDISPMODEB_OUTDELAY; + wire [1:0] PIPETXCHARDISPVALA_OUTDELAY; + wire [1:0] PIPETXCHARDISPVALB_OUTDELAY; + wire [1:0] PIPETXCHARISKA_OUTDELAY; + wire [1:0] PIPETXCHARISKB_OUTDELAY; + wire [2:0] CFGDEVCONTROLMAXPAYLOAD_OUTDELAY; + wire [2:0] CFGDEVCONTROLMAXREADREQ_OUTDELAY; + wire [2:0] CFGFUNCTIONNUMBER_OUTDELAY; + wire [2:0] CFGINTERRUPTMMENABLE_OUTDELAY; + wire [2:0] CFGPCIELINKSTATEN_OUTDELAY; + wire [31:0] CFGDO_OUTDELAY; + wire [31:0] TRNRD_OUTDELAY; + wire [34:0] MIMRXWDATA_OUTDELAY; + wire [35:0] MIMTXWDATA_OUTDELAY; + wire [4:0] CFGDEVICENUMBER_OUTDELAY; + wire [4:0] CFGLTSSMSTATE_OUTDELAY; + wire [5:0] TRNTBUFAV_OUTDELAY; + wire [6:0] TRNRBARHITN_OUTDELAY; + wire [7:0] CFGBUSNUMBER_OUTDELAY; + wire [7:0] CFGINTERRUPTDO_OUTDELAY; + wire [7:0] TRNFCCPLH_OUTDELAY; + wire [7:0] TRNFCNPH_OUTDELAY; + wire [7:0] TRNFCPH_OUTDELAY; + + wire CFGERRCORN_IN; + wire CFGERRCPLABORTN_IN; + wire CFGERRCPLTIMEOUTN_IN; + wire CFGERRECRCN_IN; + wire CFGERRLOCKEDN_IN; + wire CFGERRPOSTEDN_IN; + wire CFGERRURN_IN; + wire CFGINTERRUPTASSERTN_IN; + wire CFGINTERRUPTN_IN; + wire CFGPMWAKEN_IN; + wire CFGRDENN_IN; + wire CFGTRNPENDINGN_IN; + wire CFGTURNOFFOKN_IN; + wire CLOCKLOCKED_IN; + wire MGTCLK_IN; + wire PIPEGTRESETDONEA_IN; + wire PIPEGTRESETDONEB_IN; + wire PIPEPHYSTATUSA_IN; + wire PIPEPHYSTATUSB_IN; + wire PIPERXENTERELECIDLEA_IN; + wire PIPERXENTERELECIDLEB_IN; + wire SYSRESETN_IN; + wire TRNRDSTRDYN_IN; + wire TRNRNPOKN_IN; + wire TRNTCFGGNTN_IN; + wire TRNTEOFN_IN; + wire TRNTERRFWDN_IN; + wire TRNTSOFN_IN; + wire TRNTSRCDSCN_IN; + wire TRNTSRCRDYN_IN; + wire TRNTSTRN_IN; + wire USERCLK_IN; + wire [15:0] CFGDEVID_IN; + wire [15:0] CFGSUBSYSID_IN; + wire [15:0] CFGSUBSYSVENID_IN; + wire [15:0] CFGVENID_IN; + wire [15:0] PIPERXDATAA_IN; + wire [15:0] PIPERXDATAB_IN; + wire [1:0] PIPERXCHARISKA_IN; + wire [1:0] PIPERXCHARISKB_IN; + wire [2:0] PIPERXSTATUSA_IN; + wire [2:0] PIPERXSTATUSB_IN; + wire [2:0] TRNFCSEL_IN; + wire [31:0] TRNTD_IN; + wire [34:0] MIMRXRDATA_IN; + wire [35:0] MIMTXRDATA_IN; + wire [47:0] CFGERRTLPCPLHEADER_IN; + wire [63:0] CFGDSN_IN; + wire [7:0] CFGINTERRUPTDI_IN; + wire [7:0] CFGREVID_IN; + wire [9:0] CFGDWADDR_IN; + wire CFGERRCORN_INDELAY; + wire CFGERRCPLABORTN_INDELAY; + wire CFGERRCPLTIMEOUTN_INDELAY; + wire CFGERRECRCN_INDELAY; + wire CFGERRLOCKEDN_INDELAY; + wire CFGERRPOSTEDN_INDELAY; + wire CFGERRURN_INDELAY; + wire CFGINTERRUPTASSERTN_INDELAY; + wire CFGINTERRUPTN_INDELAY; + wire CFGPMWAKEN_INDELAY; + wire CFGRDENN_INDELAY; + wire CFGTRNPENDINGN_INDELAY; + wire CFGTURNOFFOKN_INDELAY; + wire CLOCKLOCKED_INDELAY; + wire MGTCLK_INDELAY; + wire PIPEGTRESETDONEA_INDELAY; + wire PIPEGTRESETDONEB_INDELAY; + wire PIPEPHYSTATUSA_INDELAY; + wire PIPEPHYSTATUSB_INDELAY; + wire PIPERXENTERELECIDLEA_INDELAY; + wire PIPERXENTERELECIDLEB_INDELAY; + wire SYSRESETN_INDELAY; + wire TRNRDSTRDYN_INDELAY; + wire TRNRNPOKN_INDELAY; + wire TRNTCFGGNTN_INDELAY; + wire TRNTEOFN_INDELAY; + wire TRNTERRFWDN_INDELAY; + wire TRNTSOFN_INDELAY; + wire TRNTSRCDSCN_INDELAY; + wire TRNTSRCRDYN_INDELAY; + wire TRNTSTRN_INDELAY; + wire USERCLK_INDELAY; + wire [15:0] CFGDEVID_INDELAY; + wire [15:0] CFGSUBSYSID_INDELAY; + wire [15:0] CFGSUBSYSVENID_INDELAY; + wire [15:0] CFGVENID_INDELAY; + wire [15:0] PIPERXDATAA_INDELAY; + wire [15:0] PIPERXDATAB_INDELAY; + wire [1:0] PIPERXCHARISKA_INDELAY; + wire [1:0] PIPERXCHARISKB_INDELAY; + wire [2:0] PIPERXSTATUSA_INDELAY; + wire [2:0] PIPERXSTATUSB_INDELAY; + wire [2:0] TRNFCSEL_INDELAY; + wire [31:0] TRNTD_INDELAY; + wire [34:0] MIMRXRDATA_INDELAY; + wire [35:0] MIMTXRDATA_INDELAY; + wire [47:0] CFGERRTLPCPLHEADER_INDELAY; + wire [63:0] CFGDSN_INDELAY; + wire [7:0] CFGINTERRUPTDI_INDELAY; + wire [7:0] CFGREVID_INDELAY; + wire [9:0] CFGDWADDR_INDELAY; + + initial begin + case (DEV_CAP_EXT_TAG_SUPPORTED[31:0]) + "ALSE" : DEV_CAP_EXT_TAG_SUPPORTED_BINARY = 1'b0; + "TRUE" : DEV_CAP_EXT_TAG_SUPPORTED_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute DEV_CAP_EXT_TAG_SUPPORTED on %s instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", MODULE_NAME, DEV_CAP_EXT_TAG_SUPPORTED); + $finish; + end + endcase + + case (DEV_CAP_ROLE_BASED_ERROR[31:0]) + "ALSE" : DEV_CAP_ROLE_BASED_ERROR_BINARY = 1'b0; + "TRUE" : DEV_CAP_ROLE_BASED_ERROR_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute DEV_CAP_ROLE_BASED_ERROR on %s instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", MODULE_NAME, DEV_CAP_ROLE_BASED_ERROR); + $finish; + end + endcase + + case (DISABLE_BAR_FILTERING[31:0]) + "ALSE" : DISABLE_BAR_FILTERING_BINARY = 1'b0; + "TRUE" : DISABLE_BAR_FILTERING_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute DISABLE_BAR_FILTERING on %s instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", MODULE_NAME, DISABLE_BAR_FILTERING); + $finish; + end + endcase + + case (DISABLE_ID_CHECK[31:0]) + "ALSE" : DISABLE_ID_CHECK_BINARY = 1'b0; + "TRUE" : DISABLE_ID_CHECK_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute DISABLE_ID_CHECK on %s instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", MODULE_NAME, DISABLE_ID_CHECK); + $finish; + end + endcase + + case (DISABLE_SCRAMBLING[31:0]) + "ALSE" : DISABLE_SCRAMBLING_BINARY = 1'b0; + "TRUE" : DISABLE_SCRAMBLING_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute DISABLE_SCRAMBLING on %s instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", MODULE_NAME, DISABLE_SCRAMBLING); + $finish; + end + endcase + + case (ENABLE_RX_TD_ECRC_TRIM[31:0]) + "ALSE" : ENABLE_RX_TD_ECRC_TRIM_BINARY = 1'b0; + "TRUE" : ENABLE_RX_TD_ECRC_TRIM_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute ENABLE_RX_TD_ECRC_TRIM on %s instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", MODULE_NAME, ENABLE_RX_TD_ECRC_TRIM); + $finish; + end + endcase + + case (FAST_TRAIN[31:0]) + "ALSE" : FAST_TRAIN_BINARY = 1'b0; + "TRUE" : FAST_TRAIN_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute FAST_TRAIN on %s instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", MODULE_NAME, FAST_TRAIN); + $finish; + end + endcase + + case (LINK_STATUS_SLOT_CLOCK_CONFIG[31:0]) + "ALSE" : LINK_STATUS_SLOT_CLOCK_CONFIG_BINARY = 1'b0; + "TRUE" : LINK_STATUS_SLOT_CLOCK_CONFIG_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute LINK_STATUS_SLOT_CLOCK_CONFIG on %s instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", MODULE_NAME, LINK_STATUS_SLOT_CLOCK_CONFIG); + $finish; + end + endcase + + case (LL_ACK_TIMEOUT_EN[31:0]) + "ALSE" : LL_ACK_TIMEOUT_EN_BINARY = 1'b0; + "TRUE" : LL_ACK_TIMEOUT_EN_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute LL_ACK_TIMEOUT_EN on %s instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", MODULE_NAME, LL_ACK_TIMEOUT_EN); + $finish; + end + endcase + + case (LL_REPLAY_TIMEOUT_EN[31:0]) + "ALSE" : LL_REPLAY_TIMEOUT_EN_BINARY = 1'b0; + "TRUE" : LL_REPLAY_TIMEOUT_EN_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute LL_REPLAY_TIMEOUT_EN on %s instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", MODULE_NAME, LL_REPLAY_TIMEOUT_EN); + $finish; + end + endcase + + case (PCIE_CAP_SLOT_IMPLEMENTED[31:0]) + "ALSE" : PCIE_CAP_SLOT_IMPLEMENTED_BINARY = 1'b0; + "TRUE" : PCIE_CAP_SLOT_IMPLEMENTED_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute PCIE_CAP_SLOT_IMPLEMENTED on %s instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", MODULE_NAME, PCIE_CAP_SLOT_IMPLEMENTED); + $finish; + end + endcase + + case (PLM_AUTO_CONFIG[31:0]) + "ALSE" : PLM_AUTO_CONFIG_BINARY = 1'b0; + "TRUE" : PLM_AUTO_CONFIG_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute PLM_AUTO_CONFIG on %s instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", MODULE_NAME, PLM_AUTO_CONFIG); + $finish; + end + endcase + + case (PM_CAP_D1SUPPORT[31:0]) + "ALSE" : PM_CAP_D1SUPPORT_BINARY = 1'b0; + "TRUE" : PM_CAP_D1SUPPORT_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute PM_CAP_D1SUPPORT on %s instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", MODULE_NAME, PM_CAP_D1SUPPORT); + $finish; + end + endcase + + case (PM_CAP_D2SUPPORT[31:0]) + "ALSE" : PM_CAP_D2SUPPORT_BINARY = 1'b0; + "TRUE" : PM_CAP_D2SUPPORT_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute PM_CAP_D2SUPPORT on %s instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", MODULE_NAME, PM_CAP_D2SUPPORT); + $finish; + end + endcase + + case (PM_CAP_DSI[31:0]) + "ALSE" : PM_CAP_DSI_BINARY = 1'b0; + "TRUE" : PM_CAP_DSI_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute PM_CAP_DSI on %s instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", MODULE_NAME, PM_CAP_DSI); + $finish; + end + endcase + + case (PM_CAP_PME_CLOCK[31:0]) + "ALSE" : PM_CAP_PME_CLOCK_BINARY = 1'b0; + "TRUE" : PM_CAP_PME_CLOCK_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute PM_CAP_PME_CLOCK on %s instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", MODULE_NAME, PM_CAP_PME_CLOCK); + $finish; + end + endcase + + case (SIM_VERSION) + "1.0" : SIM_VERSION_BINARY = 0; + "2.0" : SIM_VERSION_BINARY = 0; + "3.0" : SIM_VERSION_BINARY = 0; + "4.0" : SIM_VERSION_BINARY = 0; + "5.0" : SIM_VERSION_BINARY = 0; + "6.0" : SIM_VERSION_BINARY = 0; + default : begin + $display("Attribute Syntax Error : The Attribute SIM_VERSION on %s instance %m is set to %s. Legal values for this attribute are 1.0, 2.0, 3.0, 4.0, 5.0, or 6.0." ,MODULE_NAME, SIM_VERSION); + $finish; + end + endcase + + case (SLOT_CAP_ATT_BUTTON_PRESENT[31:0]) + "ALSE" : SLOT_CAP_ATT_BUTTON_PRESENT_BINARY = 1'b0; + "TRUE" : SLOT_CAP_ATT_BUTTON_PRESENT_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute SLOT_CAP_ATT_BUTTON_PRESENT on %s instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", MODULE_NAME, SLOT_CAP_ATT_BUTTON_PRESENT); + $finish; + end + endcase + + case (SLOT_CAP_ATT_INDICATOR_PRESENT[31:0]) + "ALSE" : SLOT_CAP_ATT_INDICATOR_PRESENT_BINARY = 1'b0; + "TRUE" : SLOT_CAP_ATT_INDICATOR_PRESENT_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute SLOT_CAP_ATT_INDICATOR_PRESENT on %s instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", MODULE_NAME, SLOT_CAP_ATT_INDICATOR_PRESENT); + $finish; + end + endcase + + case (SLOT_CAP_POWER_INDICATOR_PRESENT[31:0]) + "ALSE" : SLOT_CAP_POWER_INDICATOR_PRESENT_BINARY = 1'b0; + "TRUE" : SLOT_CAP_POWER_INDICATOR_PRESENT_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute SLOT_CAP_POWER_INDICATOR_PRESENT on %s instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", MODULE_NAME, SLOT_CAP_POWER_INDICATOR_PRESENT); + $finish; + end + endcase + + case (TL_TFC_DISABLE[31:0]) + "ALSE" : TL_TFC_DISABLE_BINARY = 1'b0; + "TRUE" : TL_TFC_DISABLE_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute TL_TFC_DISABLE on %s instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", MODULE_NAME, TL_TFC_DISABLE); + $finish; + end + endcase + + case (TL_TX_CHECKS_DISABLE[31:0]) + "ALSE" : TL_TX_CHECKS_DISABLE_BINARY = 1'b0; + "TRUE" : TL_TX_CHECKS_DISABLE_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute TL_TX_CHECKS_DISABLE on %s instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", MODULE_NAME, TL_TX_CHECKS_DISABLE); + $finish; + end + endcase + + case (USR_CFG[31:0]) + "ALSE" : USR_CFG_BINARY = 1'b0; + "TRUE" : USR_CFG_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute USR_CFG on %s instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", MODULE_NAME, USR_CFG); + $finish; + end + endcase + + case (USR_EXT_CFG[31:0]) + "ALSE" : USR_EXT_CFG_BINARY = 1'b0; + "TRUE" : USR_EXT_CFG_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute USR_EXT_CFG on %s instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", MODULE_NAME, USR_EXT_CFG); + $finish; + end + endcase + + case (VC0_CPL_INFINITE[31:0]) + "ALSE" : VC0_CPL_INFINITE_BINARY = 1'b0; + "TRUE" : VC0_CPL_INFINITE_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute VC0_CPL_INFINITE on %s instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", MODULE_NAME, VC0_CPL_INFINITE); + $finish; + end + endcase + + if ((DEV_CAP_ENDPOINT_L0S_LATENCY >= 0) && (DEV_CAP_ENDPOINT_L0S_LATENCY <= 7)) + DEV_CAP_ENDPOINT_L0S_LATENCY_BINARY = DEV_CAP_ENDPOINT_L0S_LATENCY; + else begin + $display("Attribute Syntax Error : The Attribute DEV_CAP_ENDPOINT_L0S_LATENCY on %s instance %m is set to %d. Legal values for this attribute are 0 to 7.", MODULE_NAME, DEV_CAP_ENDPOINT_L0S_LATENCY); + $finish; + end + + if ((DEV_CAP_ENDPOINT_L1_LATENCY >= 0) && (DEV_CAP_ENDPOINT_L1_LATENCY <= 7)) + DEV_CAP_ENDPOINT_L1_LATENCY_BINARY = DEV_CAP_ENDPOINT_L1_LATENCY; + else begin + $display("Attribute Syntax Error : The Attribute DEV_CAP_ENDPOINT_L1_LATENCY on %s instance %m is set to %d. Legal values for this attribute are 0 to 7.", MODULE_NAME, DEV_CAP_ENDPOINT_L1_LATENCY); + $finish; + end + + if ((DEV_CAP_MAX_PAYLOAD_SUPPORTED >= 0) && (DEV_CAP_MAX_PAYLOAD_SUPPORTED <= 7)) + DEV_CAP_MAX_PAYLOAD_SUPPORTED_BINARY = DEV_CAP_MAX_PAYLOAD_SUPPORTED; + else begin + $display("Attribute Syntax Error : The Attribute DEV_CAP_MAX_PAYLOAD_SUPPORTED on %s instance %m is set to %d. Legal values for this attribute are 0 to 7.", MODULE_NAME, DEV_CAP_MAX_PAYLOAD_SUPPORTED); + $finish; + end + + if ((DEV_CAP_PHANTOM_FUNCTIONS_SUPPORT >= 0) && (DEV_CAP_PHANTOM_FUNCTIONS_SUPPORT <= 3)) + DEV_CAP_PHANTOM_FUNCTIONS_SUPPORT_BINARY = DEV_CAP_PHANTOM_FUNCTIONS_SUPPORT; + else begin + $display("Attribute Syntax Error : The Attribute DEV_CAP_PHANTOM_FUNCTIONS_SUPPORT on %s instance %m is set to %d. Legal values for this attribute are 0 to 3.", MODULE_NAME, DEV_CAP_PHANTOM_FUNCTIONS_SUPPORT); + $finish; + end + + if ((GTP_SEL >= 0) && (GTP_SEL <= 1)) + GTP_SEL_BINARY = GTP_SEL; + else begin + $display("Attribute Syntax Error : The Attribute GTP_SEL on %s instance %m is set to %d. Legal values for this attribute are 0 to 1.", MODULE_NAME, GTP_SEL); + $finish; + end + + if ((LINK_CAP_ASPM_SUPPORT >= 0) && (LINK_CAP_ASPM_SUPPORT <= 3)) + LINK_CAP_ASPM_SUPPORT_BINARY = LINK_CAP_ASPM_SUPPORT; + else begin + $display("Attribute Syntax Error : The Attribute LINK_CAP_ASPM_SUPPORT on %s instance %m is set to %d. Legal values for this attribute are 0 to 3.", MODULE_NAME, LINK_CAP_ASPM_SUPPORT); + $finish; + end + + if ((LINK_CAP_L0S_EXIT_LATENCY >= 0) && (LINK_CAP_L0S_EXIT_LATENCY <= 7)) + LINK_CAP_L0S_EXIT_LATENCY_BINARY = LINK_CAP_L0S_EXIT_LATENCY; + else begin + $display("Attribute Syntax Error : The Attribute LINK_CAP_L0S_EXIT_LATENCY on %s instance %m is set to %d. Legal values for this attribute are 0 to 7.", MODULE_NAME, LINK_CAP_L0S_EXIT_LATENCY); + $finish; + end + + if ((LINK_CAP_L1_EXIT_LATENCY >= 0) && (LINK_CAP_L1_EXIT_LATENCY <= 7)) + LINK_CAP_L1_EXIT_LATENCY_BINARY = LINK_CAP_L1_EXIT_LATENCY; + else begin + $display("Attribute Syntax Error : The Attribute LINK_CAP_L1_EXIT_LATENCY on %s instance %m is set to %d. Legal values for this attribute are 0 to 7.", MODULE_NAME, LINK_CAP_L1_EXIT_LATENCY); + $finish; + end + + if ((MSI_CAP_MULTIMSGCAP >= 0) && (MSI_CAP_MULTIMSGCAP <= 7)) + MSI_CAP_MULTIMSGCAP_BINARY = MSI_CAP_MULTIMSGCAP; + else begin + $display("Attribute Syntax Error : The Attribute MSI_CAP_MULTIMSGCAP on %s instance %m is set to %d. Legal values for this attribute are 0 to 7.", MODULE_NAME, MSI_CAP_MULTIMSGCAP); + $finish; + end + + if ((MSI_CAP_MULTIMSG_EXTENSION >= 0) && (MSI_CAP_MULTIMSG_EXTENSION <= 1)) + MSI_CAP_MULTIMSG_EXTENSION_BINARY = MSI_CAP_MULTIMSG_EXTENSION; + else begin + $display("Attribute Syntax Error : The Attribute MSI_CAP_MULTIMSG_EXTENSION on %s instance %m is set to %d. Legal values for this attribute are 0 to 1.", MODULE_NAME, MSI_CAP_MULTIMSG_EXTENSION); + $finish; + end + + if ((PCIE_CAP_INT_MSG_NUM >= 0) && (PCIE_CAP_INT_MSG_NUM <= 31)) + PCIE_CAP_INT_MSG_NUM_BINARY = PCIE_CAP_INT_MSG_NUM; + else begin + $display("Attribute Syntax Error : The Attribute PCIE_CAP_INT_MSG_NUM on %s instance %m is set to %d. Legal values for this attribute are 0 to 31.", MODULE_NAME, PCIE_CAP_INT_MSG_NUM); + $finish; + end + + if ((PM_CAP_AUXCURRENT >= 0) && (PM_CAP_AUXCURRENT <= 7)) + PM_CAP_AUXCURRENT_BINARY = PM_CAP_AUXCURRENT; + else begin + $display("Attribute Syntax Error : The Attribute PM_CAP_AUXCURRENT on %s instance %m is set to %d. Legal values for this attribute are 0 to 7.", MODULE_NAME, PM_CAP_AUXCURRENT); + $finish; + end + + if ((PM_CAP_PMESUPPORT >= 0) && (PM_CAP_PMESUPPORT <= 31)) + PM_CAP_PMESUPPORT_BINARY = PM_CAP_PMESUPPORT; + else begin + $display("Attribute Syntax Error : The Attribute PM_CAP_PMESUPPORT on %s instance %m is set to %d. Legal values for this attribute are 0 to 31.", MODULE_NAME,PM_CAP_PMESUPPORT); + $finish; + end + + if ((PM_CAP_VERSION >= 0) && (PM_CAP_VERSION <= 7)) + PM_CAP_VERSION_BINARY = PM_CAP_VERSION; + else begin + $display("Attribute Syntax Error : The Attribute PM_CAP_VERSION on %s instance %m is set to %d. Legal values for this attribute are 0 to 7.", MODULE_NAME, PM_CAP_VERSION); + $finish; + end + + if ((PM_DATA_SCALE0 >= 0) && (PM_DATA_SCALE0 <= 3)) + PM_DATA_SCALE0_BINARY = PM_DATA_SCALE0; + else begin + $display("Attribute Syntax Error : The Attribute PM_DATA_SCALE0 on %s instance %m is set to %d. Legal values for this attribute are 0 to 3.", MODULE_NAME, PM_DATA_SCALE0); + $finish; + end + + if ((PM_DATA_SCALE1 >= 0) && (PM_DATA_SCALE1 <= 3)) + PM_DATA_SCALE1_BINARY = PM_DATA_SCALE1; + else begin + $display("Attribute Syntax Error : The Attribute PM_DATA_SCALE1 on %s instance %m is set to %d. Legal values for this attribute are 0 to 3.", MODULE_NAME, PM_DATA_SCALE1); + $finish; + end + + if ((PM_DATA_SCALE2 >= 0) && (PM_DATA_SCALE2 <= 3)) + PM_DATA_SCALE2_BINARY = PM_DATA_SCALE2; + else begin + $display("Attribute Syntax Error : The Attribute PM_DATA_SCALE2 on %s instance %m is set to %d. Legal values for this attribute are 0 to 3.", MODULE_NAME, PM_DATA_SCALE2); + $finish; + end + + if ((PM_DATA_SCALE3 >= 0) && (PM_DATA_SCALE3 <= 3)) + PM_DATA_SCALE3_BINARY = PM_DATA_SCALE3; + else begin + $display("Attribute Syntax Error : The Attribute PM_DATA_SCALE3 on %s instance %m is set to %d. Legal values for this attribute are 0 to 3.", MODULE_NAME, PM_DATA_SCALE3); + $finish; + end + + if ((PM_DATA_SCALE4 >= 0) && (PM_DATA_SCALE4 <= 3)) + PM_DATA_SCALE4_BINARY = PM_DATA_SCALE4; + else begin + $display("Attribute Syntax Error : The Attribute PM_DATA_SCALE4 on %s instance %m is set to %d. Legal values for this attribute are 0 to 3.", MODULE_NAME, PM_DATA_SCALE4); + $finish; + end + + if ((PM_DATA_SCALE5 >= 0) && (PM_DATA_SCALE5 <= 3)) + PM_DATA_SCALE5_BINARY = PM_DATA_SCALE5; + else begin + $display("Attribute Syntax Error : The Attribute PM_DATA_SCALE5 on %s instance %m is set to %d. Legal values for this attribute are 0 to 3.", MODULE_NAME, PM_DATA_SCALE5); + $finish; + end + + if ((PM_DATA_SCALE6 >= 0) && (PM_DATA_SCALE6 <= 3)) + PM_DATA_SCALE6_BINARY = PM_DATA_SCALE6; + else begin + $display("Attribute Syntax Error : The Attribute PM_DATA_SCALE6 on %s instance %m is set to %d. Legal values for this attribute are 0 to 3.", MODULE_NAME, PM_DATA_SCALE6); + $finish; + end + + if ((PM_DATA_SCALE7 >= 0) && (PM_DATA_SCALE7 <= 3)) + PM_DATA_SCALE7_BINARY = PM_DATA_SCALE7; + else begin + $display("Attribute Syntax Error : The Attribute PM_DATA_SCALE7 on %s instance %m is set to %d. Legal values for this attribute are 0 to 3.", MODULE_NAME, PM_DATA_SCALE7); + $finish; + end + + if ((TL_RX_RAM_RADDR_LATENCY >= 0) && (TL_RX_RAM_RADDR_LATENCY <= 1)) + TL_RX_RAM_RADDR_LATENCY_BINARY = TL_RX_RAM_RADDR_LATENCY; + else begin + $display("Attribute Syntax Error : The Attribute TL_RX_RAM_RADDR_LATENCY on %s instance %m is set to %d. Legal values for this attribute are 0 to 1.", MODULE_NAME, TL_RX_RAM_RADDR_LATENCY); + $finish; + end + + if ((TL_RX_RAM_RDATA_LATENCY >= 0) && (TL_RX_RAM_RDATA_LATENCY <= 3)) + TL_RX_RAM_RDATA_LATENCY_BINARY = TL_RX_RAM_RDATA_LATENCY; + else begin + $display("Attribute Syntax Error : The Attribute TL_RX_RAM_RDATA_LATENCY on %s instance %m is set to %d. Legal values for this attribute are 0 to 3.", MODULE_NAME, TL_RX_RAM_RDATA_LATENCY); + $finish; + end + + if ((TL_RX_RAM_WRITE_LATENCY >= 0) && (TL_RX_RAM_WRITE_LATENCY <= 1)) + TL_RX_RAM_WRITE_LATENCY_BINARY = TL_RX_RAM_WRITE_LATENCY; + else begin + $display("Attribute Syntax Error : The Attribute TL_RX_RAM_WRITE_LATENCY on %s instance %m is set to %d. Legal values for this attribute are 0 to 1.", MODULE_NAME, TL_RX_RAM_WRITE_LATENCY); + $finish; + end + + if ((TL_TX_RAM_RADDR_LATENCY >= 0) && (TL_TX_RAM_RADDR_LATENCY <= 1)) + TL_TX_RAM_RADDR_LATENCY_BINARY = TL_TX_RAM_RADDR_LATENCY; + else begin + $display("Attribute Syntax Error : The Attribute TL_TX_RAM_RADDR_LATENCY on %s instance %m is set to %d. Legal values for this attribute are 0 to 1.", MODULE_NAME, TL_TX_RAM_RADDR_LATENCY); + $finish; + end + + if ((TL_TX_RAM_RDATA_LATENCY >= 0) && (TL_TX_RAM_RDATA_LATENCY <= 3)) + TL_TX_RAM_RDATA_LATENCY_BINARY = TL_TX_RAM_RDATA_LATENCY; + else begin + $display("Attribute Syntax Error : The Attribute TL_TX_RAM_RDATA_LATENCY on %s instance %m is set to %d. Legal values for this attribute are 0 to 3.", MODULE_NAME, TL_TX_RAM_RDATA_LATENCY); + $finish; + end + + if ((VC0_TOTAL_CREDITS_CD >= 0) && (VC0_TOTAL_CREDITS_CD <= 2047)) + VC0_TOTAL_CREDITS_CD_BINARY = VC0_TOTAL_CREDITS_CD; + else begin + $display("Attribute Syntax Error : The Attribute VC0_TOTAL_CREDITS_CD on %s instance %m is set to %d. Legal values for this attribute are 0 to 2047.", MODULE_NAME, VC0_TOTAL_CREDITS_CD); + $finish; + end + + if ((VC0_TOTAL_CREDITS_CH >= 0) && (VC0_TOTAL_CREDITS_CH <= 127)) + VC0_TOTAL_CREDITS_CH_BINARY = VC0_TOTAL_CREDITS_CH; + else begin + $display("Attribute Syntax Error : The Attribute VC0_TOTAL_CREDITS_CH on %s instance %m is set to %d. Legal values for this attribute are 0 to 127.", MODULE_NAME, VC0_TOTAL_CREDITS_CH); + $finish; + end + + if ((VC0_TOTAL_CREDITS_NPH >= 0) && (VC0_TOTAL_CREDITS_NPH <= 127)) + VC0_TOTAL_CREDITS_NPH_BINARY = VC0_TOTAL_CREDITS_NPH; + else begin + $display("Attribute Syntax Error : The Attribute VC0_TOTAL_CREDITS_NPH on %s instance %m is set to %d. Legal values for this attribute are 0 to 127.", MODULE_NAME, VC0_TOTAL_CREDITS_NPH); + $finish; + end + + if ((VC0_TOTAL_CREDITS_PD >= 0) && (VC0_TOTAL_CREDITS_PD <= 2047)) + VC0_TOTAL_CREDITS_PD_BINARY = VC0_TOTAL_CREDITS_PD; + else begin + $display("Attribute Syntax Error : The Attribute VC0_TOTAL_CREDITS_PD on %s instance %m is set to %d. Legal values for this attribute are 0 to 2047.", MODULE_NAME, VC0_TOTAL_CREDITS_PD); + $finish; + end + + if ((VC0_TOTAL_CREDITS_PH >= 0) && (VC0_TOTAL_CREDITS_PH <= 127)) + VC0_TOTAL_CREDITS_PH_BINARY = VC0_TOTAL_CREDITS_PH; + else begin + $display("Attribute Syntax Error : The Attribute VC0_TOTAL_CREDITS_PH on %s instance %m is set to %d. Legal values for this attribute are 0 to 127.", MODULE_NAME, VC0_TOTAL_CREDITS_PH); + $finish; + end + + if ((VC0_TX_LASTPACKET >= 0) && (VC0_TX_LASTPACKET <= 31)) + VC0_TX_LASTPACKET_BINARY = VC0_TX_LASTPACKET; + else begin + $display("Attribute Syntax Error : The Attribute VC0_TX_LASTPACKET on %s instance %m is set to %d. Legal values for this attribute are 0 to 31.", MODULE_NAME, VC0_TX_LASTPACKET); + $finish; + end + + end + + + assign CFGBUSNUMBER = CFGBUSNUMBER_OUTDELAY; + assign CFGCOMMANDBUSMASTERENABLE = CFGCOMMANDBUSMASTERENABLE_OUTDELAY; + assign CFGCOMMANDINTERRUPTDISABLE = CFGCOMMANDINTERRUPTDISABLE_OUTDELAY; + assign CFGCOMMANDIOENABLE = CFGCOMMANDIOENABLE_OUTDELAY; + assign CFGCOMMANDMEMENABLE = CFGCOMMANDMEMENABLE_OUTDELAY; + assign CFGCOMMANDSERREN = CFGCOMMANDSERREN_OUTDELAY; + assign CFGDEVCONTROLAUXPOWEREN = CFGDEVCONTROLAUXPOWEREN_OUTDELAY; + assign CFGDEVCONTROLCORRERRREPORTINGEN = CFGDEVCONTROLCORRERRREPORTINGEN_OUTDELAY; + assign CFGDEVCONTROLENABLERO = CFGDEVCONTROLENABLERO_OUTDELAY; + assign CFGDEVCONTROLEXTTAGEN = CFGDEVCONTROLEXTTAGEN_OUTDELAY; + assign CFGDEVCONTROLFATALERRREPORTINGEN = CFGDEVCONTROLFATALERRREPORTINGEN_OUTDELAY; + assign CFGDEVCONTROLMAXPAYLOAD = CFGDEVCONTROLMAXPAYLOAD_OUTDELAY; + assign CFGDEVCONTROLMAXREADREQ = CFGDEVCONTROLMAXREADREQ_OUTDELAY; + assign CFGDEVCONTROLNONFATALREPORTINGEN = CFGDEVCONTROLNONFATALREPORTINGEN_OUTDELAY; + assign CFGDEVCONTROLNOSNOOPEN = CFGDEVCONTROLNOSNOOPEN_OUTDELAY; + assign CFGDEVCONTROLPHANTOMEN = CFGDEVCONTROLPHANTOMEN_OUTDELAY; + assign CFGDEVCONTROLURERRREPORTINGEN = CFGDEVCONTROLURERRREPORTINGEN_OUTDELAY; + assign CFGDEVICENUMBER = CFGDEVICENUMBER_OUTDELAY; + assign CFGDEVSTATUSCORRERRDETECTED = CFGDEVSTATUSCORRERRDETECTED_OUTDELAY; + assign CFGDEVSTATUSFATALERRDETECTED = CFGDEVSTATUSFATALERRDETECTED_OUTDELAY; + assign CFGDEVSTATUSNONFATALERRDETECTED = CFGDEVSTATUSNONFATALERRDETECTED_OUTDELAY; + assign CFGDEVSTATUSURDETECTED = CFGDEVSTATUSURDETECTED_OUTDELAY; + assign CFGDO = CFGDO_OUTDELAY; + assign CFGERRCPLRDYN = CFGERRCPLRDYN_OUTDELAY; + assign CFGFUNCTIONNUMBER = CFGFUNCTIONNUMBER_OUTDELAY; + assign CFGINTERRUPTDO = CFGINTERRUPTDO_OUTDELAY; + assign CFGINTERRUPTMMENABLE = CFGINTERRUPTMMENABLE_OUTDELAY; + assign CFGINTERRUPTMSIENABLE = CFGINTERRUPTMSIENABLE_OUTDELAY; + assign CFGINTERRUPTRDYN = CFGINTERRUPTRDYN_OUTDELAY; + assign CFGLINKCONTOLRCB = CFGLINKCONTOLRCB_OUTDELAY; + assign CFGLINKCONTROLASPMCONTROL = CFGLINKCONTROLASPMCONTROL_OUTDELAY; + assign CFGLINKCONTROLCOMMONCLOCK = CFGLINKCONTROLCOMMONCLOCK_OUTDELAY; + assign CFGLINKCONTROLEXTENDEDSYNC = CFGLINKCONTROLEXTENDEDSYNC_OUTDELAY; + assign CFGLTSSMSTATE = CFGLTSSMSTATE_OUTDELAY; + assign CFGPCIELINKSTATEN = CFGPCIELINKSTATEN_OUTDELAY; + assign CFGRDWRDONEN = CFGRDWRDONEN_OUTDELAY; + assign CFGTOTURNOFFN = CFGTOTURNOFFN_OUTDELAY; + assign DBGBADDLLPSTATUS = DBGBADDLLPSTATUS_OUTDELAY; + assign DBGBADTLPLCRC = DBGBADTLPLCRC_OUTDELAY; + assign DBGBADTLPSEQNUM = DBGBADTLPSEQNUM_OUTDELAY; + assign DBGBADTLPSTATUS = DBGBADTLPSTATUS_OUTDELAY; + assign DBGDLPROTOCOLSTATUS = DBGDLPROTOCOLSTATUS_OUTDELAY; + assign DBGFCPROTOCOLERRSTATUS = DBGFCPROTOCOLERRSTATUS_OUTDELAY; + assign DBGMLFRMDLENGTH = DBGMLFRMDLENGTH_OUTDELAY; + assign DBGMLFRMDMPS = DBGMLFRMDMPS_OUTDELAY; + assign DBGMLFRMDTCVC = DBGMLFRMDTCVC_OUTDELAY; + assign DBGMLFRMDTLPSTATUS = DBGMLFRMDTLPSTATUS_OUTDELAY; + assign DBGMLFRMDUNRECTYPE = DBGMLFRMDUNRECTYPE_OUTDELAY; + assign DBGPOISTLPSTATUS = DBGPOISTLPSTATUS_OUTDELAY; + assign DBGRCVROVERFLOWSTATUS = DBGRCVROVERFLOWSTATUS_OUTDELAY; + assign DBGREGDETECTEDCORRECTABLE = DBGREGDETECTEDCORRECTABLE_OUTDELAY; + assign DBGREGDETECTEDFATAL = DBGREGDETECTEDFATAL_OUTDELAY; + assign DBGREGDETECTEDNONFATAL = DBGREGDETECTEDNONFATAL_OUTDELAY; + assign DBGREGDETECTEDUNSUPPORTED = DBGREGDETECTEDUNSUPPORTED_OUTDELAY; + assign DBGRPLYROLLOVERSTATUS = DBGRPLYROLLOVERSTATUS_OUTDELAY; + assign DBGRPLYTIMEOUTSTATUS = DBGRPLYTIMEOUTSTATUS_OUTDELAY; + assign DBGURNOBARHIT = DBGURNOBARHIT_OUTDELAY; + assign DBGURPOISCFGWR = DBGURPOISCFGWR_OUTDELAY; + assign DBGURSTATUS = DBGURSTATUS_OUTDELAY; + assign DBGURUNSUPMSG = DBGURUNSUPMSG_OUTDELAY; + assign MIMRXRADDR = MIMRXRADDR_OUTDELAY; + assign MIMRXREN = MIMRXREN_OUTDELAY; + assign MIMRXWADDR = MIMRXWADDR_OUTDELAY; + assign MIMRXWDATA = MIMRXWDATA_OUTDELAY; + assign MIMRXWEN = MIMRXWEN_OUTDELAY; + assign MIMTXRADDR = MIMTXRADDR_OUTDELAY; + assign MIMTXREN = MIMTXREN_OUTDELAY; + assign MIMTXWADDR = MIMTXWADDR_OUTDELAY; + assign MIMTXWDATA = MIMTXWDATA_OUTDELAY; + assign MIMTXWEN = MIMTXWEN_OUTDELAY; + assign PIPEGTPOWERDOWNA = PIPEGTPOWERDOWNA_OUTDELAY; + assign PIPEGTPOWERDOWNB = PIPEGTPOWERDOWNB_OUTDELAY; + assign PIPEGTTXELECIDLEA = PIPEGTTXELECIDLEA_OUTDELAY; + assign PIPEGTTXELECIDLEB = PIPEGTTXELECIDLEB_OUTDELAY; + assign PIPERXPOLARITYA = PIPERXPOLARITYA_OUTDELAY; + assign PIPERXPOLARITYB = PIPERXPOLARITYB_OUTDELAY; + assign PIPERXRESETA = PIPERXRESETA_OUTDELAY; + assign PIPERXRESETB = PIPERXRESETB_OUTDELAY; + assign PIPETXCHARDISPMODEA = PIPETXCHARDISPMODEA_OUTDELAY; + assign PIPETXCHARDISPMODEB = PIPETXCHARDISPMODEB_OUTDELAY; + assign PIPETXCHARDISPVALA = PIPETXCHARDISPVALA_OUTDELAY; + assign PIPETXCHARDISPVALB = PIPETXCHARDISPVALB_OUTDELAY; + assign PIPETXCHARISKA = PIPETXCHARISKA_OUTDELAY; + assign PIPETXCHARISKB = PIPETXCHARISKB_OUTDELAY; + assign PIPETXDATAA = PIPETXDATAA_OUTDELAY; + assign PIPETXDATAB = PIPETXDATAB_OUTDELAY; + assign PIPETXRCVRDETA = PIPETXRCVRDETA_OUTDELAY; + assign PIPETXRCVRDETB = PIPETXRCVRDETB_OUTDELAY; + assign RECEIVEDHOTRESET = RECEIVEDHOTRESET_OUTDELAY; + assign TRNFCCPLD = TRNFCCPLD_OUTDELAY; + assign TRNFCCPLH = TRNFCCPLH_OUTDELAY; + assign TRNFCNPD = TRNFCNPD_OUTDELAY; + assign TRNFCNPH = TRNFCNPH_OUTDELAY; + assign TRNFCPD = TRNFCPD_OUTDELAY; + assign TRNFCPH = TRNFCPH_OUTDELAY; + assign TRNLNKUPN = TRNLNKUPN_OUTDELAY; + assign TRNRBARHITN = TRNRBARHITN_OUTDELAY; + assign TRNRD = TRNRD_OUTDELAY; + assign TRNREOFN = TRNREOFN_OUTDELAY; + assign TRNRERRFWDN = TRNRERRFWDN_OUTDELAY; + assign TRNRSOFN = TRNRSOFN_OUTDELAY; + assign TRNRSRCDSCN = TRNRSRCDSCN_OUTDELAY; + assign TRNRSRCRDYN = TRNRSRCRDYN_OUTDELAY; + assign TRNTBUFAV = TRNTBUFAV_OUTDELAY; + assign TRNTCFGREQN = TRNTCFGREQN_OUTDELAY; + assign TRNTDSTRDYN = TRNTDSTRDYN_OUTDELAY; + assign TRNTERRDROPN = TRNTERRDROPN_OUTDELAY; + assign USERRSTN = USERRSTN_OUTDELAY; + +//---------------------------------------------------------------------- +//------------------------ Input Ports ------------------------------ +//---------------------------------------------------------------------- + assign MGTCLK_IN = MGTCLK; + assign USERCLK_IN = USERCLK; + + assign CFGDEVID_IN = CFGDEVID; + assign CFGDSN_IN = CFGDSN; + assign CFGDWADDR_IN = CFGDWADDR; + assign CFGERRCORN_IN = CFGERRCORN; + assign CFGERRCPLABORTN_IN = CFGERRCPLABORTN; + assign CFGERRCPLTIMEOUTN_IN = CFGERRCPLTIMEOUTN; + assign CFGERRECRCN_IN = CFGERRECRCN; + assign CFGERRLOCKEDN_IN = CFGERRLOCKEDN; + assign CFGERRPOSTEDN_IN = CFGERRPOSTEDN; + assign CFGERRTLPCPLHEADER_IN = CFGERRTLPCPLHEADER; + assign CFGERRURN_IN = CFGERRURN; + assign CFGINTERRUPTASSERTN_IN = CFGINTERRUPTASSERTN; + assign CFGINTERRUPTDI_IN = CFGINTERRUPTDI; + assign CFGINTERRUPTN_IN = CFGINTERRUPTN; + assign CFGPMWAKEN_IN = CFGPMWAKEN; + assign CFGRDENN_IN = CFGRDENN; + assign CFGREVID_IN = CFGREVID; + assign CFGSUBSYSID_IN = CFGSUBSYSID; + assign CFGSUBSYSVENID_IN = CFGSUBSYSVENID; + assign CFGTRNPENDINGN_IN = CFGTRNPENDINGN; + assign CFGTURNOFFOKN_IN = CFGTURNOFFOKN; + assign CFGVENID_IN = CFGVENID; + assign CLOCKLOCKED_IN = CLOCKLOCKED; + assign MIMRXRDATA_IN = MIMRXRDATA; + assign MIMTXRDATA_IN = MIMTXRDATA; + assign PIPEGTRESETDONEA_IN = PIPEGTRESETDONEA; + assign PIPEGTRESETDONEB_IN = PIPEGTRESETDONEB; + assign PIPEPHYSTATUSA_IN = PIPEPHYSTATUSA; + assign PIPEPHYSTATUSB_IN = PIPEPHYSTATUSB; + assign PIPERXCHARISKA_IN = PIPERXCHARISKA; + assign PIPERXCHARISKB_IN = PIPERXCHARISKB; + assign PIPERXDATAA_IN = PIPERXDATAA; + assign PIPERXDATAB_IN = PIPERXDATAB; + assign PIPERXENTERELECIDLEA_IN = PIPERXENTERELECIDLEA; + assign PIPERXENTERELECIDLEB_IN = PIPERXENTERELECIDLEB; + assign PIPERXSTATUSA_IN = PIPERXSTATUSA; + assign PIPERXSTATUSB_IN = PIPERXSTATUSB; + assign SYSRESETN_IN = SYSRESETN; + assign TRNFCSEL_IN = TRNFCSEL; + assign TRNRDSTRDYN_IN = TRNRDSTRDYN; + assign TRNRNPOKN_IN = TRNRNPOKN; + assign TRNTCFGGNTN_IN = TRNTCFGGNTN; + assign TRNTD_IN = TRNTD; + assign TRNTEOFN_IN = TRNTEOFN; + assign TRNTERRFWDN_IN = TRNTERRFWDN; + assign TRNTSOFN_IN = TRNTSOFN; + assign TRNTSRCDSCN_IN = TRNTSRCDSCN; + assign TRNTSRCRDYN_IN = TRNTSRCRDYN; + assign TRNTSTRN_IN = TRNTSTRN; + assign #(out_delay) CFGBUSNUMBER_OUTDELAY = CFGBUSNUMBER_OUT; + assign #(out_delay) CFGCOMMANDBUSMASTERENABLE_OUTDELAY = CFGCOMMANDBUSMASTERENABLE_OUT; + assign #(out_delay) CFGCOMMANDINTERRUPTDISABLE_OUTDELAY = CFGCOMMANDINTERRUPTDISABLE_OUT; + assign #(out_delay) CFGCOMMANDIOENABLE_OUTDELAY = CFGCOMMANDIOENABLE_OUT; + assign #(out_delay) CFGCOMMANDMEMENABLE_OUTDELAY = CFGCOMMANDMEMENABLE_OUT; + assign #(out_delay) CFGCOMMANDSERREN_OUTDELAY = CFGCOMMANDSERREN_OUT; + assign #(out_delay) CFGDEVCONTROLAUXPOWEREN_OUTDELAY = CFGDEVCONTROLAUXPOWEREN_OUT; + assign #(out_delay) CFGDEVCONTROLCORRERRREPORTINGEN_OUTDELAY = CFGDEVCONTROLCORRERRREPORTINGEN_OUT; + assign #(out_delay) CFGDEVCONTROLENABLERO_OUTDELAY = CFGDEVCONTROLENABLERO_OUT; + assign #(out_delay) CFGDEVCONTROLEXTTAGEN_OUTDELAY = CFGDEVCONTROLEXTTAGEN_OUT; + assign #(out_delay) CFGDEVCONTROLFATALERRREPORTINGEN_OUTDELAY = CFGDEVCONTROLFATALERRREPORTINGEN_OUT; + assign #(out_delay) CFGDEVCONTROLMAXPAYLOAD_OUTDELAY = CFGDEVCONTROLMAXPAYLOAD_OUT; + assign #(out_delay) CFGDEVCONTROLMAXREADREQ_OUTDELAY = CFGDEVCONTROLMAXREADREQ_OUT; + assign #(out_delay) CFGDEVCONTROLNONFATALREPORTINGEN_OUTDELAY = CFGDEVCONTROLNONFATALREPORTINGEN_OUT; + assign #(out_delay) CFGDEVCONTROLNOSNOOPEN_OUTDELAY = CFGDEVCONTROLNOSNOOPEN_OUT; + assign #(out_delay) CFGDEVCONTROLPHANTOMEN_OUTDELAY = CFGDEVCONTROLPHANTOMEN_OUT; + assign #(out_delay) CFGDEVCONTROLURERRREPORTINGEN_OUTDELAY = CFGDEVCONTROLURERRREPORTINGEN_OUT; + assign #(out_delay) CFGDEVICENUMBER_OUTDELAY = CFGDEVICENUMBER_OUT; + assign #(out_delay) CFGDEVSTATUSCORRERRDETECTED_OUTDELAY = CFGDEVSTATUSCORRERRDETECTED_OUT; + assign #(out_delay) CFGDEVSTATUSFATALERRDETECTED_OUTDELAY = CFGDEVSTATUSFATALERRDETECTED_OUT; + assign #(out_delay) CFGDEVSTATUSNONFATALERRDETECTED_OUTDELAY = CFGDEVSTATUSNONFATALERRDETECTED_OUT; + assign #(out_delay) CFGDEVSTATUSURDETECTED_OUTDELAY = CFGDEVSTATUSURDETECTED_OUT; + assign #(out_delay) CFGDO_OUTDELAY = CFGDO_OUT; + assign #(out_delay) CFGERRCPLRDYN_OUTDELAY = CFGERRCPLRDYN_OUT; + assign #(out_delay) CFGFUNCTIONNUMBER_OUTDELAY = CFGFUNCTIONNUMBER_OUT; + assign #(out_delay) CFGINTERRUPTDO_OUTDELAY = CFGINTERRUPTDO_OUT; + assign #(out_delay) CFGINTERRUPTMMENABLE_OUTDELAY = CFGINTERRUPTMMENABLE_OUT; + assign #(out_delay) CFGINTERRUPTMSIENABLE_OUTDELAY = CFGINTERRUPTMSIENABLE_OUT; + assign #(out_delay) CFGINTERRUPTRDYN_OUTDELAY = CFGINTERRUPTRDYN_OUT; + assign #(out_delay) CFGLINKCONTOLRCB_OUTDELAY = CFGLINKCONTOLRCB_OUT; + assign #(out_delay) CFGLINKCONTROLASPMCONTROL_OUTDELAY = CFGLINKCONTROLASPMCONTROL_OUT; + assign #(out_delay) CFGLINKCONTROLCOMMONCLOCK_OUTDELAY = CFGLINKCONTROLCOMMONCLOCK_OUT; + assign #(out_delay) CFGLINKCONTROLEXTENDEDSYNC_OUTDELAY = CFGLINKCONTROLEXTENDEDSYNC_OUT; + assign #(out_delay) CFGLTSSMSTATE_OUTDELAY = CFGLTSSMSTATE_OUT; + assign #(out_delay) CFGPCIELINKSTATEN_OUTDELAY = CFGPCIELINKSTATEN_OUT; + assign #(out_delay) CFGRDWRDONEN_OUTDELAY = CFGRDWRDONEN_OUT; + assign #(out_delay) CFGTOTURNOFFN_OUTDELAY = CFGTOTURNOFFN_OUT; + assign #(out_delay) DBGBADDLLPSTATUS_OUTDELAY = DBGBADDLLPSTATUS_OUT; + assign #(out_delay) DBGBADTLPLCRC_OUTDELAY = DBGBADTLPLCRC_OUT; + assign #(out_delay) DBGBADTLPSEQNUM_OUTDELAY = DBGBADTLPSEQNUM_OUT; + assign #(out_delay) DBGBADTLPSTATUS_OUTDELAY = DBGBADTLPSTATUS_OUT; + assign #(out_delay) DBGDLPROTOCOLSTATUS_OUTDELAY = DBGDLPROTOCOLSTATUS_OUT; + assign #(out_delay) DBGFCPROTOCOLERRSTATUS_OUTDELAY = DBGFCPROTOCOLERRSTATUS_OUT; + assign #(out_delay) DBGMLFRMDLENGTH_OUTDELAY = DBGMLFRMDLENGTH_OUT; + assign #(out_delay) DBGMLFRMDMPS_OUTDELAY = DBGMLFRMDMPS_OUT; + assign #(out_delay) DBGMLFRMDTCVC_OUTDELAY = DBGMLFRMDTCVC_OUT; + assign #(out_delay) DBGMLFRMDTLPSTATUS_OUTDELAY = DBGMLFRMDTLPSTATUS_OUT; + assign #(out_delay) DBGMLFRMDUNRECTYPE_OUTDELAY = DBGMLFRMDUNRECTYPE_OUT; + assign #(out_delay) DBGPOISTLPSTATUS_OUTDELAY = DBGPOISTLPSTATUS_OUT; + assign #(out_delay) DBGRCVROVERFLOWSTATUS_OUTDELAY = DBGRCVROVERFLOWSTATUS_OUT; + assign #(out_delay) DBGREGDETECTEDCORRECTABLE_OUTDELAY = DBGREGDETECTEDCORRECTABLE_OUT; + assign #(out_delay) DBGREGDETECTEDFATAL_OUTDELAY = DBGREGDETECTEDFATAL_OUT; + assign #(out_delay) DBGREGDETECTEDNONFATAL_OUTDELAY = DBGREGDETECTEDNONFATAL_OUT; + assign #(out_delay) DBGREGDETECTEDUNSUPPORTED_OUTDELAY = DBGREGDETECTEDUNSUPPORTED_OUT; + assign #(out_delay) DBGRPLYROLLOVERSTATUS_OUTDELAY = DBGRPLYROLLOVERSTATUS_OUT; + assign #(out_delay) DBGRPLYTIMEOUTSTATUS_OUTDELAY = DBGRPLYTIMEOUTSTATUS_OUT; + assign #(out_delay) DBGURNOBARHIT_OUTDELAY = DBGURNOBARHIT_OUT; + assign #(out_delay) DBGURPOISCFGWR_OUTDELAY = DBGURPOISCFGWR_OUT; + assign #(out_delay) DBGURSTATUS_OUTDELAY = DBGURSTATUS_OUT; + assign #(out_delay) DBGURUNSUPMSG_OUTDELAY = DBGURUNSUPMSG_OUT; + assign #(out_delay) MIMRXRADDR_OUTDELAY = MIMRXRADDR_OUT; + assign #(out_delay) MIMRXREN_OUTDELAY = MIMRXREN_OUT; + assign #(out_delay) MIMRXWADDR_OUTDELAY = MIMRXWADDR_OUT; + assign #(out_delay) MIMRXWDATA_OUTDELAY = MIMRXWDATA_OUT; + assign #(out_delay) MIMRXWEN_OUTDELAY = MIMRXWEN_OUT; + assign #(out_delay) MIMTXRADDR_OUTDELAY = MIMTXRADDR_OUT; + assign #(out_delay) MIMTXREN_OUTDELAY = MIMTXREN_OUT; + assign #(out_delay) MIMTXWADDR_OUTDELAY = MIMTXWADDR_OUT; + assign #(out_delay) MIMTXWDATA_OUTDELAY = MIMTXWDATA_OUT; + assign #(out_delay) MIMTXWEN_OUTDELAY = MIMTXWEN_OUT; + assign #(out_delay) PIPEGTPOWERDOWNA_OUTDELAY = PIPEGTPOWERDOWNA_OUT; + assign #(out_delay) PIPEGTPOWERDOWNB_OUTDELAY = PIPEGTPOWERDOWNB_OUT; + assign #(out_delay) PIPEGTTXELECIDLEA_OUTDELAY = PIPEGTTXELECIDLEA_OUT; + assign #(out_delay) PIPEGTTXELECIDLEB_OUTDELAY = PIPEGTTXELECIDLEB_OUT; + assign #(out_delay) PIPERXPOLARITYA_OUTDELAY = PIPERXPOLARITYA_OUT; + assign #(out_delay) PIPERXPOLARITYB_OUTDELAY = PIPERXPOLARITYB_OUT; + assign #(out_delay) PIPERXRESETA_OUTDELAY = PIPERXRESETA_OUT; + assign #(out_delay) PIPERXRESETB_OUTDELAY = PIPERXRESETB_OUT; + assign #(out_delay) PIPETXCHARDISPMODEA_OUTDELAY = PIPETXCHARDISPMODEA_OUT; + assign #(out_delay) PIPETXCHARDISPMODEB_OUTDELAY = PIPETXCHARDISPMODEB_OUT; + assign #(out_delay) PIPETXCHARDISPVALA_OUTDELAY = PIPETXCHARDISPVALA_OUT; + assign #(out_delay) PIPETXCHARDISPVALB_OUTDELAY = PIPETXCHARDISPVALB_OUT; + assign #(out_delay) PIPETXCHARISKA_OUTDELAY = PIPETXCHARISKA_OUT; + assign #(out_delay) PIPETXCHARISKB_OUTDELAY = PIPETXCHARISKB_OUT; + assign #(out_delay) PIPETXDATAA_OUTDELAY = PIPETXDATAA_OUT; + assign #(out_delay) PIPETXDATAB_OUTDELAY = PIPETXDATAB_OUT; + assign #(out_delay) PIPETXRCVRDETA_OUTDELAY = PIPETXRCVRDETA_OUT; + assign #(out_delay) PIPETXRCVRDETB_OUTDELAY = PIPETXRCVRDETB_OUT; + assign #(out_delay) RECEIVEDHOTRESET_OUTDELAY = RECEIVEDHOTRESET_OUT; + assign #(out_delay) TRNFCCPLD_OUTDELAY = TRNFCCPLD_OUT; + assign #(out_delay) TRNFCCPLH_OUTDELAY = TRNFCCPLH_OUT; + assign #(out_delay) TRNFCNPD_OUTDELAY = TRNFCNPD_OUT; + assign #(out_delay) TRNFCNPH_OUTDELAY = TRNFCNPH_OUT; + assign #(out_delay) TRNFCPD_OUTDELAY = TRNFCPD_OUT; + assign #(out_delay) TRNFCPH_OUTDELAY = TRNFCPH_OUT; + assign #(out_delay) TRNLNKUPN_OUTDELAY = TRNLNKUPN_OUT; + assign #(out_delay) TRNRBARHITN_OUTDELAY = TRNRBARHITN_OUT; + assign #(out_delay) TRNRD_OUTDELAY = TRNRD_OUT; + assign #(out_delay) TRNREOFN_OUTDELAY = TRNREOFN_OUT; + assign #(out_delay) TRNRERRFWDN_OUTDELAY = TRNRERRFWDN_OUT; + assign #(out_delay) TRNRSOFN_OUTDELAY = TRNRSOFN_OUT; + assign #(out_delay) TRNRSRCDSCN_OUTDELAY = TRNRSRCDSCN_OUT; + assign #(out_delay) TRNRSRCRDYN_OUTDELAY = TRNRSRCRDYN_OUT; + assign #(out_delay) TRNTBUFAV_OUTDELAY = TRNTBUFAV_OUT; + assign #(out_delay) TRNTCFGREQN_OUTDELAY = TRNTCFGREQN_OUT; + assign #(out_delay) TRNTDSTRDYN_OUTDELAY = TRNTDSTRDYN_OUT; + assign #(out_delay) TRNTERRDROPN_OUTDELAY = TRNTERRDROPN_OUT; + assign #(out_delay) USERRSTN_OUTDELAY = USERRSTN_OUT; + + assign #(INCLK_DELAY) MGTCLK_INDELAY = MGTCLK_IN; + assign #(INCLK_DELAY) USERCLK_INDELAY = USERCLK_IN; + + assign #(in_delay) CFGDEVID_INDELAY = CFGDEVID_IN; + assign #(in_delay) CFGDSN_INDELAY = CFGDSN_IN; + assign #(in_delay) CFGDWADDR_INDELAY = CFGDWADDR_IN; + assign #(in_delay) CFGERRCORN_INDELAY = CFGERRCORN_IN; + assign #(in_delay) CFGERRCPLABORTN_INDELAY = CFGERRCPLABORTN_IN; + assign #(in_delay) CFGERRCPLTIMEOUTN_INDELAY = CFGERRCPLTIMEOUTN_IN; + assign #(in_delay) CFGERRECRCN_INDELAY = CFGERRECRCN_IN; + assign #(in_delay) CFGERRLOCKEDN_INDELAY = CFGERRLOCKEDN_IN; + assign #(in_delay) CFGERRPOSTEDN_INDELAY = CFGERRPOSTEDN_IN; + assign #(in_delay) CFGERRTLPCPLHEADER_INDELAY = CFGERRTLPCPLHEADER_IN; + assign #(in_delay) CFGERRURN_INDELAY = CFGERRURN_IN; + assign #(in_delay) CFGINTERRUPTASSERTN_INDELAY = CFGINTERRUPTASSERTN_IN; + assign #(in_delay) CFGINTERRUPTDI_INDELAY = CFGINTERRUPTDI_IN; + assign #(in_delay) CFGINTERRUPTN_INDELAY = CFGINTERRUPTN_IN; + assign #(in_delay) CFGPMWAKEN_INDELAY = CFGPMWAKEN_IN; + assign #(in_delay) CFGRDENN_INDELAY = CFGRDENN_IN; + assign #(in_delay) CFGREVID_INDELAY = CFGREVID_IN; + assign #(in_delay) CFGSUBSYSID_INDELAY = CFGSUBSYSID_IN; + assign #(in_delay) CFGSUBSYSVENID_INDELAY = CFGSUBSYSVENID_IN; + assign #(in_delay) CFGTRNPENDINGN_INDELAY = CFGTRNPENDINGN_IN; + assign #(in_delay) CFGTURNOFFOKN_INDELAY = CFGTURNOFFOKN_IN; + assign #(in_delay) CFGVENID_INDELAY = CFGVENID_IN; + assign #(in_delay) CLOCKLOCKED_INDELAY = CLOCKLOCKED_IN; + assign #(in_delay) MIMRXRDATA_INDELAY = MIMRXRDATA_IN; + assign #(in_delay) MIMTXRDATA_INDELAY = MIMTXRDATA_IN; + assign #(in_delay) PIPEGTRESETDONEA_INDELAY = PIPEGTRESETDONEA_IN; + assign #(in_delay) PIPEGTRESETDONEB_INDELAY = PIPEGTRESETDONEB_IN; + assign #(in_delay) PIPEPHYSTATUSA_INDELAY = PIPEPHYSTATUSA_IN; + assign #(in_delay) PIPEPHYSTATUSB_INDELAY = PIPEPHYSTATUSB_IN; + assign #(in_delay) PIPERXCHARISKA_INDELAY = PIPERXCHARISKA_IN; + assign #(in_delay) PIPERXCHARISKB_INDELAY = PIPERXCHARISKB_IN; + assign #(in_delay) PIPERXDATAA_INDELAY = PIPERXDATAA_IN; + assign #(in_delay) PIPERXDATAB_INDELAY = PIPERXDATAB_IN; + assign #(in_delay) PIPERXENTERELECIDLEA_INDELAY = PIPERXENTERELECIDLEA_IN; + assign #(in_delay) PIPERXENTERELECIDLEB_INDELAY = PIPERXENTERELECIDLEB_IN; + assign #(in_delay) PIPERXSTATUSA_INDELAY = PIPERXSTATUSA_IN; + assign #(in_delay) PIPERXSTATUSB_INDELAY = PIPERXSTATUSB_IN; + assign #(in_delay) SYSRESETN_INDELAY = SYSRESETN_IN; + assign #(in_delay) TRNFCSEL_INDELAY = TRNFCSEL_IN; + assign #(in_delay) TRNRDSTRDYN_INDELAY = TRNRDSTRDYN_IN; + assign #(in_delay) TRNRNPOKN_INDELAY = TRNRNPOKN_IN; + assign #(in_delay) TRNTCFGGNTN_INDELAY = TRNTCFGGNTN_IN; + assign #(in_delay) TRNTD_INDELAY = TRNTD_IN; + assign #(in_delay) TRNTEOFN_INDELAY = TRNTEOFN_IN; + assign #(in_delay) TRNTERRFWDN_INDELAY = TRNTERRFWDN_IN; + assign #(in_delay) TRNTSOFN_INDELAY = TRNTSOFN_IN; + assign #(in_delay) TRNTSRCDSCN_INDELAY = TRNTSRCDSCN_IN; + assign #(in_delay) TRNTSRCRDYN_INDELAY = TRNTSRCRDYN_IN; + assign #(in_delay) TRNTSTRN_INDELAY = TRNTSTRN_IN; + + B_PCIE_A1 #( + .BAR0 (BAR0), + .BAR1 (BAR1), + .BAR2 (BAR2), + .BAR3 (BAR3), + .BAR4 (BAR4), + .BAR5 (BAR5), + .CARDBUS_CIS_POINTER (CARDBUS_CIS_POINTER), + .CLASS_CODE (CLASS_CODE), + .DEV_CAP_ENDPOINT_L0S_LATENCY (DEV_CAP_ENDPOINT_L0S_LATENCY), + .DEV_CAP_ENDPOINT_L1_LATENCY (DEV_CAP_ENDPOINT_L1_LATENCY), + .DEV_CAP_EXT_TAG_SUPPORTED (DEV_CAP_EXT_TAG_SUPPORTED), + .DEV_CAP_MAX_PAYLOAD_SUPPORTED (DEV_CAP_MAX_PAYLOAD_SUPPORTED), + .DEV_CAP_PHANTOM_FUNCTIONS_SUPPORT (DEV_CAP_PHANTOM_FUNCTIONS_SUPPORT), + .DEV_CAP_ROLE_BASED_ERROR (DEV_CAP_ROLE_BASED_ERROR), + .DISABLE_BAR_FILTERING (DISABLE_BAR_FILTERING), + .DISABLE_ID_CHECK (DISABLE_ID_CHECK), + .DISABLE_SCRAMBLING (DISABLE_SCRAMBLING), + .ENABLE_RX_TD_ECRC_TRIM (ENABLE_RX_TD_ECRC_TRIM), + .EXPANSION_ROM (EXPANSION_ROM), + .FAST_TRAIN (FAST_TRAIN), + .GTP_SEL (GTP_SEL), + .LINK_CAP_ASPM_SUPPORT (LINK_CAP_ASPM_SUPPORT), + .LINK_CAP_L0S_EXIT_LATENCY (LINK_CAP_L0S_EXIT_LATENCY), + .LINK_CAP_L1_EXIT_LATENCY (LINK_CAP_L1_EXIT_LATENCY), + .LINK_STATUS_SLOT_CLOCK_CONFIG (LINK_STATUS_SLOT_CLOCK_CONFIG), + .LL_ACK_TIMEOUT (LL_ACK_TIMEOUT), + .LL_ACK_TIMEOUT_EN (LL_ACK_TIMEOUT_EN), + .LL_REPLAY_TIMEOUT (LL_REPLAY_TIMEOUT), + .LL_REPLAY_TIMEOUT_EN (LL_REPLAY_TIMEOUT_EN), + .MSI_CAP_MULTIMSGCAP (MSI_CAP_MULTIMSGCAP), + .MSI_CAP_MULTIMSG_EXTENSION (MSI_CAP_MULTIMSG_EXTENSION), + .PCIE_CAP_CAPABILITY_VERSION (PCIE_CAP_CAPABILITY_VERSION), + .PCIE_CAP_DEVICE_PORT_TYPE (PCIE_CAP_DEVICE_PORT_TYPE), + .PCIE_CAP_INT_MSG_NUM (PCIE_CAP_INT_MSG_NUM), + .PCIE_CAP_SLOT_IMPLEMENTED (PCIE_CAP_SLOT_IMPLEMENTED), + .PCIE_GENERIC (PCIE_GENERIC), + .PLM_AUTO_CONFIG (PLM_AUTO_CONFIG), + .PM_CAP_AUXCURRENT (PM_CAP_AUXCURRENT), + .PM_CAP_D1SUPPORT (PM_CAP_D1SUPPORT), + .PM_CAP_D2SUPPORT (PM_CAP_D2SUPPORT), + .PM_CAP_DSI (PM_CAP_DSI), + .PM_CAP_PMESUPPORT (PM_CAP_PMESUPPORT), + .PM_CAP_PME_CLOCK (PM_CAP_PME_CLOCK), + .PM_CAP_VERSION (PM_CAP_VERSION), + .PM_DATA0 (PM_DATA0), + .PM_DATA1 (PM_DATA1), + .PM_DATA2 (PM_DATA2), + .PM_DATA3 (PM_DATA3), + .PM_DATA4 (PM_DATA4), + .PM_DATA5 (PM_DATA5), + .PM_DATA6 (PM_DATA6), + .PM_DATA7 (PM_DATA7), + .PM_DATA_SCALE0 (PM_DATA_SCALE0), + .PM_DATA_SCALE1 (PM_DATA_SCALE1), + .PM_DATA_SCALE2 (PM_DATA_SCALE2), + .PM_DATA_SCALE3 (PM_DATA_SCALE3), + .PM_DATA_SCALE4 (PM_DATA_SCALE4), + .PM_DATA_SCALE5 (PM_DATA_SCALE5), + .PM_DATA_SCALE6 (PM_DATA_SCALE6), + .PM_DATA_SCALE7 (PM_DATA_SCALE7), + .SIM_VERSION (SIM_VERSION), + .SLOT_CAP_ATT_BUTTON_PRESENT (SLOT_CAP_ATT_BUTTON_PRESENT), + .SLOT_CAP_ATT_INDICATOR_PRESENT (SLOT_CAP_ATT_INDICATOR_PRESENT), + .SLOT_CAP_POWER_INDICATOR_PRESENT (SLOT_CAP_POWER_INDICATOR_PRESENT), + .TL_RX_RAM_RADDR_LATENCY (TL_RX_RAM_RADDR_LATENCY), + .TL_RX_RAM_RDATA_LATENCY (TL_RX_RAM_RDATA_LATENCY), + .TL_RX_RAM_WRITE_LATENCY (TL_RX_RAM_WRITE_LATENCY), + .TL_TFC_DISABLE (TL_TFC_DISABLE), + .TL_TX_CHECKS_DISABLE (TL_TX_CHECKS_DISABLE), + .TL_TX_RAM_RADDR_LATENCY (TL_TX_RAM_RADDR_LATENCY), + .TL_TX_RAM_RDATA_LATENCY (TL_TX_RAM_RDATA_LATENCY), + .USR_CFG (USR_CFG), + .USR_EXT_CFG (USR_EXT_CFG), + .VC0_CPL_INFINITE (VC0_CPL_INFINITE), + .VC0_RX_RAM_LIMIT (VC0_RX_RAM_LIMIT), + .VC0_TOTAL_CREDITS_CD (VC0_TOTAL_CREDITS_CD), + .VC0_TOTAL_CREDITS_CH (VC0_TOTAL_CREDITS_CH), + .VC0_TOTAL_CREDITS_NPH (VC0_TOTAL_CREDITS_NPH), + .VC0_TOTAL_CREDITS_PD (VC0_TOTAL_CREDITS_PD), + .VC0_TOTAL_CREDITS_PH (VC0_TOTAL_CREDITS_PH), + .VC0_TX_LASTPACKET (VC0_TX_LASTPACKET)) + + B_PCIE_A1_INST ( + .GSR (GSR), + .CFGBUSNUMBER (CFGBUSNUMBER_OUT), + .CFGCOMMANDBUSMASTERENABLE (CFGCOMMANDBUSMASTERENABLE_OUT), + .CFGCOMMANDINTERRUPTDISABLE (CFGCOMMANDINTERRUPTDISABLE_OUT), + .CFGCOMMANDIOENABLE (CFGCOMMANDIOENABLE_OUT), + .CFGCOMMANDMEMENABLE (CFGCOMMANDMEMENABLE_OUT), + .CFGCOMMANDSERREN (CFGCOMMANDSERREN_OUT), + .CFGDEVCONTROLAUXPOWEREN (CFGDEVCONTROLAUXPOWEREN_OUT), + .CFGDEVCONTROLCORRERRREPORTINGEN (CFGDEVCONTROLCORRERRREPORTINGEN_OUT), + .CFGDEVCONTROLENABLERO (CFGDEVCONTROLENABLERO_OUT), + .CFGDEVCONTROLEXTTAGEN (CFGDEVCONTROLEXTTAGEN_OUT), + .CFGDEVCONTROLFATALERRREPORTINGEN (CFGDEVCONTROLFATALERRREPORTINGEN_OUT), + .CFGDEVCONTROLMAXPAYLOAD (CFGDEVCONTROLMAXPAYLOAD_OUT), + .CFGDEVCONTROLMAXREADREQ (CFGDEVCONTROLMAXREADREQ_OUT), + .CFGDEVCONTROLNONFATALREPORTINGEN (CFGDEVCONTROLNONFATALREPORTINGEN_OUT), + .CFGDEVCONTROLNOSNOOPEN (CFGDEVCONTROLNOSNOOPEN_OUT), + .CFGDEVCONTROLPHANTOMEN (CFGDEVCONTROLPHANTOMEN_OUT), + .CFGDEVCONTROLURERRREPORTINGEN (CFGDEVCONTROLURERRREPORTINGEN_OUT), + .CFGDEVICENUMBER (CFGDEVICENUMBER_OUT), + .CFGDEVSTATUSCORRERRDETECTED (CFGDEVSTATUSCORRERRDETECTED_OUT), + .CFGDEVSTATUSFATALERRDETECTED (CFGDEVSTATUSFATALERRDETECTED_OUT), + .CFGDEVSTATUSNONFATALERRDETECTED (CFGDEVSTATUSNONFATALERRDETECTED_OUT), + .CFGDEVSTATUSURDETECTED (CFGDEVSTATUSURDETECTED_OUT), + .CFGDO (CFGDO_OUT), + .CFGERRCPLRDYN (CFGERRCPLRDYN_OUT), + .CFGFUNCTIONNUMBER (CFGFUNCTIONNUMBER_OUT), + .CFGINTERRUPTDO (CFGINTERRUPTDO_OUT), + .CFGINTERRUPTMMENABLE (CFGINTERRUPTMMENABLE_OUT), + .CFGINTERRUPTMSIENABLE (CFGINTERRUPTMSIENABLE_OUT), + .CFGINTERRUPTRDYN (CFGINTERRUPTRDYN_OUT), + .CFGLINKCONTOLRCB (CFGLINKCONTOLRCB_OUT), + .CFGLINKCONTROLASPMCONTROL (CFGLINKCONTROLASPMCONTROL_OUT), + .CFGLINKCONTROLCOMMONCLOCK (CFGLINKCONTROLCOMMONCLOCK_OUT), + .CFGLINKCONTROLEXTENDEDSYNC (CFGLINKCONTROLEXTENDEDSYNC_OUT), + .CFGLTSSMSTATE (CFGLTSSMSTATE_OUT), + .CFGPCIELINKSTATEN (CFGPCIELINKSTATEN_OUT), + .CFGRDWRDONEN (CFGRDWRDONEN_OUT), + .CFGTOTURNOFFN (CFGTOTURNOFFN_OUT), + .DBGBADDLLPSTATUS (DBGBADDLLPSTATUS_OUT), + .DBGBADTLPLCRC (DBGBADTLPLCRC_OUT), + .DBGBADTLPSEQNUM (DBGBADTLPSEQNUM_OUT), + .DBGBADTLPSTATUS (DBGBADTLPSTATUS_OUT), + .DBGDLPROTOCOLSTATUS (DBGDLPROTOCOLSTATUS_OUT), + .DBGFCPROTOCOLERRSTATUS (DBGFCPROTOCOLERRSTATUS_OUT), + .DBGMLFRMDLENGTH (DBGMLFRMDLENGTH_OUT), + .DBGMLFRMDMPS (DBGMLFRMDMPS_OUT), + .DBGMLFRMDTCVC (DBGMLFRMDTCVC_OUT), + .DBGMLFRMDTLPSTATUS (DBGMLFRMDTLPSTATUS_OUT), + .DBGMLFRMDUNRECTYPE (DBGMLFRMDUNRECTYPE_OUT), + .DBGPOISTLPSTATUS (DBGPOISTLPSTATUS_OUT), + .DBGRCVROVERFLOWSTATUS (DBGRCVROVERFLOWSTATUS_OUT), + .DBGREGDETECTEDCORRECTABLE (DBGREGDETECTEDCORRECTABLE_OUT), + .DBGREGDETECTEDFATAL (DBGREGDETECTEDFATAL_OUT), + .DBGREGDETECTEDNONFATAL (DBGREGDETECTEDNONFATAL_OUT), + .DBGREGDETECTEDUNSUPPORTED (DBGREGDETECTEDUNSUPPORTED_OUT), + .DBGRPLYROLLOVERSTATUS (DBGRPLYROLLOVERSTATUS_OUT), + .DBGRPLYTIMEOUTSTATUS (DBGRPLYTIMEOUTSTATUS_OUT), + .DBGURNOBARHIT (DBGURNOBARHIT_OUT), + .DBGURPOISCFGWR (DBGURPOISCFGWR_OUT), + .DBGURSTATUS (DBGURSTATUS_OUT), + .DBGURUNSUPMSG (DBGURUNSUPMSG_OUT), + .MIMRXRADDR (MIMRXRADDR_OUT), + .MIMRXREN (MIMRXREN_OUT), + .MIMRXWADDR (MIMRXWADDR_OUT), + .MIMRXWDATA (MIMRXWDATA_OUT), + .MIMRXWEN (MIMRXWEN_OUT), + .MIMTXRADDR (MIMTXRADDR_OUT), + .MIMTXREN (MIMTXREN_OUT), + .MIMTXWADDR (MIMTXWADDR_OUT), + .MIMTXWDATA (MIMTXWDATA_OUT), + .MIMTXWEN (MIMTXWEN_OUT), + .PIPEGTPOWERDOWNA (PIPEGTPOWERDOWNA_OUT), + .PIPEGTPOWERDOWNB (PIPEGTPOWERDOWNB_OUT), + .PIPEGTTXELECIDLEA (PIPEGTTXELECIDLEA_OUT), + .PIPEGTTXELECIDLEB (PIPEGTTXELECIDLEB_OUT), + .PIPERXPOLARITYA (PIPERXPOLARITYA_OUT), + .PIPERXPOLARITYB (PIPERXPOLARITYB_OUT), + .PIPERXRESETA (PIPERXRESETA_OUT), + .PIPERXRESETB (PIPERXRESETB_OUT), + .PIPETXCHARDISPMODEA (PIPETXCHARDISPMODEA_OUT), + .PIPETXCHARDISPMODEB (PIPETXCHARDISPMODEB_OUT), + .PIPETXCHARDISPVALA (PIPETXCHARDISPVALA_OUT), + .PIPETXCHARDISPVALB (PIPETXCHARDISPVALB_OUT), + .PIPETXCHARISKA (PIPETXCHARISKA_OUT), + .PIPETXCHARISKB (PIPETXCHARISKB_OUT), + .PIPETXDATAA (PIPETXDATAA_OUT), + .PIPETXDATAB (PIPETXDATAB_OUT), + .PIPETXRCVRDETA (PIPETXRCVRDETA_OUT), + .PIPETXRCVRDETB (PIPETXRCVRDETB_OUT), + .RECEIVEDHOTRESET (RECEIVEDHOTRESET_OUT), + .TRNFCCPLD (TRNFCCPLD_OUT), + .TRNFCCPLH (TRNFCCPLH_OUT), + .TRNFCNPD (TRNFCNPD_OUT), + .TRNFCNPH (TRNFCNPH_OUT), + .TRNFCPD (TRNFCPD_OUT), + .TRNFCPH (TRNFCPH_OUT), + .TRNLNKUPN (TRNLNKUPN_OUT), + .TRNRBARHITN (TRNRBARHITN_OUT), + .TRNRD (TRNRD_OUT), + .TRNREOFN (TRNREOFN_OUT), + .TRNRERRFWDN (TRNRERRFWDN_OUT), + .TRNRSOFN (TRNRSOFN_OUT), + .TRNRSRCDSCN (TRNRSRCDSCN_OUT), + .TRNRSRCRDYN (TRNRSRCRDYN_OUT), + .TRNTBUFAV (TRNTBUFAV_OUT), + .TRNTCFGREQN (TRNTCFGREQN_OUT), + .TRNTDSTRDYN (TRNTDSTRDYN_OUT), + .TRNTERRDROPN (TRNTERRDROPN_OUT), + .USERRSTN (USERRSTN_OUT), + .CFGDEVID (CFGDEVID_INDELAY), + .CFGDSN (CFGDSN_INDELAY), + .CFGDWADDR (CFGDWADDR_INDELAY), + .CFGERRCORN (CFGERRCORN_INDELAY), + .CFGERRCPLABORTN (CFGERRCPLABORTN_INDELAY), + .CFGERRCPLTIMEOUTN (CFGERRCPLTIMEOUTN_INDELAY), + .CFGERRECRCN (CFGERRECRCN_INDELAY), + .CFGERRLOCKEDN (CFGERRLOCKEDN_INDELAY), + .CFGERRPOSTEDN (CFGERRPOSTEDN_INDELAY), + .CFGERRTLPCPLHEADER (CFGERRTLPCPLHEADER_INDELAY), + .CFGERRURN (CFGERRURN_INDELAY), + .CFGINTERRUPTASSERTN (CFGINTERRUPTASSERTN_INDELAY), + .CFGINTERRUPTDI (CFGINTERRUPTDI_INDELAY), + .CFGINTERRUPTN (CFGINTERRUPTN_INDELAY), + .CFGPMWAKEN (CFGPMWAKEN_INDELAY), + .CFGRDENN (CFGRDENN_INDELAY), + .CFGREVID (CFGREVID_INDELAY), + .CFGSUBSYSID (CFGSUBSYSID_INDELAY), + .CFGSUBSYSVENID (CFGSUBSYSVENID_INDELAY), + .CFGTRNPENDINGN (CFGTRNPENDINGN_INDELAY), + .CFGTURNOFFOKN (CFGTURNOFFOKN_INDELAY), + .CFGVENID (CFGVENID_INDELAY), + .CLOCKLOCKED (CLOCKLOCKED_INDELAY), + .MGTCLK (MGTCLK_INDELAY), + .MIMRXRDATA (MIMRXRDATA_INDELAY), + .MIMTXRDATA (MIMTXRDATA_INDELAY), + .PIPEGTRESETDONEA (PIPEGTRESETDONEA_INDELAY), + .PIPEGTRESETDONEB (PIPEGTRESETDONEB_INDELAY), + .PIPEPHYSTATUSA (PIPEPHYSTATUSA_INDELAY), + .PIPEPHYSTATUSB (PIPEPHYSTATUSB_INDELAY), + .PIPERXCHARISKA (PIPERXCHARISKA_INDELAY), + .PIPERXCHARISKB (PIPERXCHARISKB_INDELAY), + .PIPERXDATAA (PIPERXDATAA_INDELAY), + .PIPERXDATAB (PIPERXDATAB_INDELAY), + .PIPERXENTERELECIDLEA (PIPERXENTERELECIDLEA_INDELAY), + .PIPERXENTERELECIDLEB (PIPERXENTERELECIDLEB_INDELAY), + .PIPERXSTATUSA (PIPERXSTATUSA_INDELAY), + .PIPERXSTATUSB (PIPERXSTATUSB_INDELAY), + .SYSRESETN (SYSRESETN_INDELAY), + .TRNFCSEL (TRNFCSEL_INDELAY), + .TRNRDSTRDYN (TRNRDSTRDYN_INDELAY), + .TRNRNPOKN (TRNRNPOKN_INDELAY), + .TRNTCFGGNTN (TRNTCFGGNTN_INDELAY), + .TRNTD (TRNTD_INDELAY), + .TRNTEOFN (TRNTEOFN_INDELAY), + .TRNTERRFWDN (TRNTERRFWDN_INDELAY), + .TRNTSOFN (TRNTSOFN_INDELAY), + .TRNTSRCDSCN (TRNTSRCDSCN_INDELAY), + .TRNTSRCRDYN (TRNTSRCRDYN_INDELAY), + .TRNTSTRN (TRNTSTRN_INDELAY), + .USERCLK (USERCLK_INDELAY) + ); + +//---------------------------------------------------------------------- +//------------------------ Specify Block ------------------------------ +//---------------------------------------------------------------------- + specify + ( MGTCLK => CFGLTSSMSTATE[0]) = (0, 0); + ( MGTCLK => CFGLTSSMSTATE[1]) = (0, 0); + ( MGTCLK => CFGLTSSMSTATE[2]) = (0, 0); + ( MGTCLK => CFGLTSSMSTATE[3]) = (0, 0); + ( MGTCLK => CFGLTSSMSTATE[4]) = (0, 0); + ( MGTCLK => PIPEGTPOWERDOWNA[0]) = (0, 0); + ( MGTCLK => PIPEGTPOWERDOWNA[1]) = (0, 0); + ( MGTCLK => PIPEGTPOWERDOWNB[0]) = (0, 0); + ( MGTCLK => PIPEGTPOWERDOWNB[1]) = (0, 0); + ( MGTCLK => PIPEGTTXELECIDLEA) = (0, 0); + ( MGTCLK => PIPEGTTXELECIDLEB) = (0, 0); + ( MGTCLK => PIPERXPOLARITYA) = (0, 0); + ( MGTCLK => PIPERXPOLARITYB) = (0, 0); + ( MGTCLK => PIPERXRESETA) = (0, 0); + ( MGTCLK => PIPERXRESETB) = (0, 0); + ( MGTCLK => PIPETXCHARDISPMODEA[0]) = (0, 0); + ( MGTCLK => PIPETXCHARDISPMODEA[1]) = (0, 0); + ( MGTCLK => PIPETXCHARDISPMODEB[0]) = (0, 0); + ( MGTCLK => PIPETXCHARDISPMODEB[1]) = (0, 0); + ( MGTCLK => PIPETXCHARDISPVALA[0]) = (0, 0); + ( MGTCLK => PIPETXCHARDISPVALA[1]) = (0, 0); + ( MGTCLK => PIPETXCHARDISPVALB[0]) = (0, 0); + ( MGTCLK => PIPETXCHARDISPVALB[1]) = (0, 0); + ( MGTCLK => PIPETXCHARISKA[0]) = (0, 0); + ( MGTCLK => PIPETXCHARISKA[1]) = (0, 0); + ( MGTCLK => PIPETXCHARISKB[0]) = (0, 0); + ( MGTCLK => PIPETXCHARISKB[1]) = (0, 0); + ( MGTCLK => PIPETXDATAA[0]) = (0, 0); + ( MGTCLK => PIPETXDATAA[10]) = (0, 0); + ( MGTCLK => PIPETXDATAA[11]) = (0, 0); + ( MGTCLK => PIPETXDATAA[12]) = (0, 0); + ( MGTCLK => PIPETXDATAA[13]) = (0, 0); + ( MGTCLK => PIPETXDATAA[14]) = (0, 0); + ( MGTCLK => PIPETXDATAA[15]) = (0, 0); + ( MGTCLK => PIPETXDATAA[1]) = (0, 0); + ( MGTCLK => PIPETXDATAA[2]) = (0, 0); + ( MGTCLK => PIPETXDATAA[3]) = (0, 0); + ( MGTCLK => PIPETXDATAA[4]) = (0, 0); + ( MGTCLK => PIPETXDATAA[5]) = (0, 0); + ( MGTCLK => PIPETXDATAA[6]) = (0, 0); + ( MGTCLK => PIPETXDATAA[7]) = (0, 0); + ( MGTCLK => PIPETXDATAA[8]) = (0, 0); + ( MGTCLK => PIPETXDATAA[9]) = (0, 0); + ( MGTCLK => PIPETXDATAB[0]) = (0, 0); + ( MGTCLK => PIPETXDATAB[10]) = (0, 0); + ( MGTCLK => PIPETXDATAB[11]) = (0, 0); + ( MGTCLK => PIPETXDATAB[12]) = (0, 0); + ( MGTCLK => PIPETXDATAB[13]) = (0, 0); + ( MGTCLK => PIPETXDATAB[14]) = (0, 0); + ( MGTCLK => PIPETXDATAB[15]) = (0, 0); + ( MGTCLK => PIPETXDATAB[1]) = (0, 0); + ( MGTCLK => PIPETXDATAB[2]) = (0, 0); + ( MGTCLK => PIPETXDATAB[3]) = (0, 0); + ( MGTCLK => PIPETXDATAB[4]) = (0, 0); + ( MGTCLK => PIPETXDATAB[5]) = (0, 0); + ( MGTCLK => PIPETXDATAB[6]) = (0, 0); + ( MGTCLK => PIPETXDATAB[7]) = (0, 0); + ( MGTCLK => PIPETXDATAB[8]) = (0, 0); + ( MGTCLK => PIPETXDATAB[9]) = (0, 0); + ( MGTCLK => PIPETXRCVRDETA) = (0, 0); + ( MGTCLK => PIPETXRCVRDETB) = (0, 0); + ( USERCLK => CFGBUSNUMBER[0]) = (0, 0); + ( USERCLK => CFGBUSNUMBER[1]) = (0, 0); + ( USERCLK => CFGBUSNUMBER[2]) = (0, 0); + ( USERCLK => CFGBUSNUMBER[3]) = (0, 0); + ( USERCLK => CFGBUSNUMBER[4]) = (0, 0); + ( USERCLK => CFGBUSNUMBER[5]) = (0, 0); + ( USERCLK => CFGBUSNUMBER[6]) = (0, 0); + ( USERCLK => CFGBUSNUMBER[7]) = (0, 0); + ( USERCLK => CFGCOMMANDBUSMASTERENABLE) = (0, 0); + ( USERCLK => CFGCOMMANDINTERRUPTDISABLE) = (0, 0); + ( USERCLK => CFGCOMMANDIOENABLE) = (0, 0); + ( USERCLK => CFGCOMMANDMEMENABLE) = (0, 0); + ( USERCLK => CFGCOMMANDSERREN) = (0, 0); + ( USERCLK => CFGDEVCONTROLAUXPOWEREN) = (0, 0); + ( USERCLK => CFGDEVCONTROLCORRERRREPORTINGEN) = (0, 0); + ( USERCLK => CFGDEVCONTROLENABLERO) = (0, 0); + ( USERCLK => CFGDEVCONTROLEXTTAGEN) = (0, 0); + ( USERCLK => CFGDEVCONTROLFATALERRREPORTINGEN) = (0, 0); + ( USERCLK => CFGDEVCONTROLMAXPAYLOAD[0]) = (0, 0); + ( USERCLK => CFGDEVCONTROLMAXPAYLOAD[1]) = (0, 0); + ( USERCLK => CFGDEVCONTROLMAXPAYLOAD[2]) = (0, 0); + ( USERCLK => CFGDEVCONTROLMAXREADREQ[0]) = (0, 0); + ( USERCLK => CFGDEVCONTROLMAXREADREQ[1]) = (0, 0); + ( USERCLK => CFGDEVCONTROLMAXREADREQ[2]) = (0, 0); + ( USERCLK => CFGDEVCONTROLNONFATALREPORTINGEN) = (0, 0); + ( USERCLK => CFGDEVCONTROLNOSNOOPEN) = (0, 0); + ( USERCLK => CFGDEVCONTROLPHANTOMEN) = (0, 0); + ( USERCLK => CFGDEVCONTROLURERRREPORTINGEN) = (0, 0); + ( USERCLK => CFGDEVICENUMBER[0]) = (0, 0); + ( USERCLK => CFGDEVICENUMBER[1]) = (0, 0); + ( USERCLK => CFGDEVICENUMBER[2]) = (0, 0); + ( USERCLK => CFGDEVICENUMBER[3]) = (0, 0); + ( USERCLK => CFGDEVICENUMBER[4]) = (0, 0); + ( USERCLK => CFGDEVSTATUSCORRERRDETECTED) = (0, 0); + ( USERCLK => CFGDEVSTATUSFATALERRDETECTED) = (0, 0); + ( USERCLK => CFGDEVSTATUSNONFATALERRDETECTED) = (0, 0); + ( USERCLK => CFGDEVSTATUSURDETECTED) = (0, 0); + ( USERCLK => CFGDO[0]) = (0, 0); + ( USERCLK => CFGDO[10]) = (0, 0); + ( USERCLK => CFGDO[11]) = (0, 0); + ( USERCLK => CFGDO[12]) = (0, 0); + ( USERCLK => CFGDO[13]) = (0, 0); + ( USERCLK => CFGDO[14]) = (0, 0); + ( USERCLK => CFGDO[15]) = (0, 0); + ( USERCLK => CFGDO[16]) = (0, 0); + ( USERCLK => CFGDO[17]) = (0, 0); + ( USERCLK => CFGDO[18]) = (0, 0); + ( USERCLK => CFGDO[19]) = (0, 0); + ( USERCLK => CFGDO[1]) = (0, 0); + ( USERCLK => CFGDO[20]) = (0, 0); + ( USERCLK => CFGDO[21]) = (0, 0); + ( USERCLK => CFGDO[22]) = (0, 0); + ( USERCLK => CFGDO[23]) = (0, 0); + ( USERCLK => CFGDO[24]) = (0, 0); + ( USERCLK => CFGDO[25]) = (0, 0); + ( USERCLK => CFGDO[26]) = (0, 0); + ( USERCLK => CFGDO[27]) = (0, 0); + ( USERCLK => CFGDO[28]) = (0, 0); + ( USERCLK => CFGDO[29]) = (0, 0); + ( USERCLK => CFGDO[2]) = (0, 0); + ( USERCLK => CFGDO[30]) = (0, 0); + ( USERCLK => CFGDO[31]) = (0, 0); + ( USERCLK => CFGDO[3]) = (0, 0); + ( USERCLK => CFGDO[4]) = (0, 0); + ( USERCLK => CFGDO[5]) = (0, 0); + ( USERCLK => CFGDO[6]) = (0, 0); + ( USERCLK => CFGDO[7]) = (0, 0); + ( USERCLK => CFGDO[8]) = (0, 0); + ( USERCLK => CFGDO[9]) = (0, 0); + ( USERCLK => CFGERRCPLRDYN) = (0, 0); + ( USERCLK => CFGFUNCTIONNUMBER[0]) = (0, 0); + ( USERCLK => CFGFUNCTIONNUMBER[1]) = (0, 0); + ( USERCLK => CFGFUNCTIONNUMBER[2]) = (0, 0); + ( USERCLK => CFGINTERRUPTDO[0]) = (0, 0); + ( USERCLK => CFGINTERRUPTDO[1]) = (0, 0); + ( USERCLK => CFGINTERRUPTDO[2]) = (0, 0); + ( USERCLK => CFGINTERRUPTDO[3]) = (0, 0); + ( USERCLK => CFGINTERRUPTDO[4]) = (0, 0); + ( USERCLK => CFGINTERRUPTDO[5]) = (0, 0); + ( USERCLK => CFGINTERRUPTDO[6]) = (0, 0); + ( USERCLK => CFGINTERRUPTDO[7]) = (0, 0); + ( USERCLK => CFGINTERRUPTMMENABLE[0]) = (0, 0); + ( USERCLK => CFGINTERRUPTMMENABLE[1]) = (0, 0); + ( USERCLK => CFGINTERRUPTMMENABLE[2]) = (0, 0); + ( USERCLK => CFGINTERRUPTMSIENABLE) = (0, 0); + ( USERCLK => CFGINTERRUPTRDYN) = (0, 0); + ( USERCLK => CFGLINKCONTOLRCB) = (0, 0); + ( USERCLK => CFGLINKCONTROLASPMCONTROL[0]) = (0, 0); + ( USERCLK => CFGLINKCONTROLASPMCONTROL[1]) = (0, 0); + ( USERCLK => CFGLINKCONTROLCOMMONCLOCK) = (0, 0); + ( USERCLK => CFGLINKCONTROLEXTENDEDSYNC) = (0, 0); + ( USERCLK => CFGPCIELINKSTATEN[0]) = (0, 0); + ( USERCLK => CFGPCIELINKSTATEN[1]) = (0, 0); + ( USERCLK => CFGPCIELINKSTATEN[2]) = (0, 0); + ( USERCLK => CFGRDWRDONEN) = (0, 0); + ( USERCLK => CFGTOTURNOFFN) = (0, 0); + ( USERCLK => DBGBADDLLPSTATUS) = (0, 0); + ( USERCLK => DBGBADTLPLCRC) = (0, 0); + ( USERCLK => DBGBADTLPSEQNUM) = (0, 0); + ( USERCLK => DBGBADTLPSTATUS) = (0, 0); + ( USERCLK => DBGDLPROTOCOLSTATUS) = (0, 0); + ( USERCLK => DBGFCPROTOCOLERRSTATUS) = (0, 0); + ( USERCLK => DBGMLFRMDLENGTH) = (0, 0); + ( USERCLK => DBGMLFRMDMPS) = (0, 0); + ( USERCLK => DBGMLFRMDTCVC) = (0, 0); + ( USERCLK => DBGMLFRMDTLPSTATUS) = (0, 0); + ( USERCLK => DBGMLFRMDUNRECTYPE) = (0, 0); + ( USERCLK => DBGPOISTLPSTATUS) = (0, 0); + ( USERCLK => DBGRCVROVERFLOWSTATUS) = (0, 0); + ( USERCLK => DBGREGDETECTEDCORRECTABLE) = (0, 0); + ( USERCLK => DBGREGDETECTEDFATAL) = (0, 0); + ( USERCLK => DBGREGDETECTEDNONFATAL) = (0, 0); + ( USERCLK => DBGREGDETECTEDUNSUPPORTED) = (0, 0); + ( USERCLK => DBGRPLYROLLOVERSTATUS) = (0, 0); + ( USERCLK => DBGRPLYTIMEOUTSTATUS) = (0, 0); + ( USERCLK => DBGURNOBARHIT) = (0, 0); + ( USERCLK => DBGURPOISCFGWR) = (0, 0); + ( USERCLK => DBGURSTATUS) = (0, 0); + ( USERCLK => DBGURUNSUPMSG) = (0, 0); + ( USERCLK => MIMRXRADDR[0]) = (0, 0); + ( USERCLK => MIMRXRADDR[10]) = (0, 0); + ( USERCLK => MIMRXRADDR[11]) = (0, 0); + ( USERCLK => MIMRXRADDR[1]) = (0, 0); + ( USERCLK => MIMRXRADDR[2]) = (0, 0); + ( USERCLK => MIMRXRADDR[3]) = (0, 0); + ( USERCLK => MIMRXRADDR[4]) = (0, 0); + ( USERCLK => MIMRXRADDR[5]) = (0, 0); + ( USERCLK => MIMRXRADDR[6]) = (0, 0); + ( USERCLK => MIMRXRADDR[7]) = (0, 0); + ( USERCLK => MIMRXRADDR[8]) = (0, 0); + ( USERCLK => MIMRXRADDR[9]) = (0, 0); + ( USERCLK => MIMRXREN) = (0, 0); + ( USERCLK => MIMRXWADDR[0]) = (0, 0); + ( USERCLK => MIMRXWADDR[10]) = (0, 0); + ( USERCLK => MIMRXWADDR[11]) = (0, 0); + ( USERCLK => MIMRXWADDR[1]) = (0, 0); + ( USERCLK => MIMRXWADDR[2]) = (0, 0); + ( USERCLK => MIMRXWADDR[3]) = (0, 0); + ( USERCLK => MIMRXWADDR[4]) = (0, 0); + ( USERCLK => MIMRXWADDR[5]) = (0, 0); + ( USERCLK => MIMRXWADDR[6]) = (0, 0); + ( USERCLK => MIMRXWADDR[7]) = (0, 0); + ( USERCLK => MIMRXWADDR[8]) = (0, 0); + ( USERCLK => MIMRXWADDR[9]) = (0, 0); + ( USERCLK => MIMRXWDATA[0]) = (0, 0); + ( USERCLK => MIMRXWDATA[10]) = (0, 0); + ( USERCLK => MIMRXWDATA[11]) = (0, 0); + ( USERCLK => MIMRXWDATA[12]) = (0, 0); + ( USERCLK => MIMRXWDATA[13]) = (0, 0); + ( USERCLK => MIMRXWDATA[14]) = (0, 0); + ( USERCLK => MIMRXWDATA[15]) = (0, 0); + ( USERCLK => MIMRXWDATA[16]) = (0, 0); + ( USERCLK => MIMRXWDATA[17]) = (0, 0); + ( USERCLK => MIMRXWDATA[18]) = (0, 0); + ( USERCLK => MIMRXWDATA[19]) = (0, 0); + ( USERCLK => MIMRXWDATA[1]) = (0, 0); + ( USERCLK => MIMRXWDATA[20]) = (0, 0); + ( USERCLK => MIMRXWDATA[21]) = (0, 0); + ( USERCLK => MIMRXWDATA[22]) = (0, 0); + ( USERCLK => MIMRXWDATA[23]) = (0, 0); + ( USERCLK => MIMRXWDATA[24]) = (0, 0); + ( USERCLK => MIMRXWDATA[25]) = (0, 0); + ( USERCLK => MIMRXWDATA[26]) = (0, 0); + ( USERCLK => MIMRXWDATA[27]) = (0, 0); + ( USERCLK => MIMRXWDATA[28]) = (0, 0); + ( USERCLK => MIMRXWDATA[29]) = (0, 0); + ( USERCLK => MIMRXWDATA[2]) = (0, 0); + ( USERCLK => MIMRXWDATA[30]) = (0, 0); + ( USERCLK => MIMRXWDATA[31]) = (0, 0); + ( USERCLK => MIMRXWDATA[32]) = (0, 0); + ( USERCLK => MIMRXWDATA[33]) = (0, 0); + ( USERCLK => MIMRXWDATA[34]) = (0, 0); + ( USERCLK => MIMRXWDATA[3]) = (0, 0); + ( USERCLK => MIMRXWDATA[4]) = (0, 0); + ( USERCLK => MIMRXWDATA[5]) = (0, 0); + ( USERCLK => MIMRXWDATA[6]) = (0, 0); + ( USERCLK => MIMRXWDATA[7]) = (0, 0); + ( USERCLK => MIMRXWDATA[8]) = (0, 0); + ( USERCLK => MIMRXWDATA[9]) = (0, 0); + ( USERCLK => MIMRXWEN) = (0, 0); + ( USERCLK => MIMTXRADDR[0]) = (0, 0); + ( USERCLK => MIMTXRADDR[10]) = (0, 0); + ( USERCLK => MIMTXRADDR[11]) = (0, 0); + ( USERCLK => MIMTXRADDR[1]) = (0, 0); + ( USERCLK => MIMTXRADDR[2]) = (0, 0); + ( USERCLK => MIMTXRADDR[3]) = (0, 0); + ( USERCLK => MIMTXRADDR[4]) = (0, 0); + ( USERCLK => MIMTXRADDR[5]) = (0, 0); + ( USERCLK => MIMTXRADDR[6]) = (0, 0); + ( USERCLK => MIMTXRADDR[7]) = (0, 0); + ( USERCLK => MIMTXRADDR[8]) = (0, 0); + ( USERCLK => MIMTXRADDR[9]) = (0, 0); + ( USERCLK => MIMTXREN) = (0, 0); + ( USERCLK => MIMTXWADDR[0]) = (0, 0); + ( USERCLK => MIMTXWADDR[10]) = (0, 0); + ( USERCLK => MIMTXWADDR[11]) = (0, 0); + ( USERCLK => MIMTXWADDR[1]) = (0, 0); + ( USERCLK => MIMTXWADDR[2]) = (0, 0); + ( USERCLK => MIMTXWADDR[3]) = (0, 0); + ( USERCLK => MIMTXWADDR[4]) = (0, 0); + ( USERCLK => MIMTXWADDR[5]) = (0, 0); + ( USERCLK => MIMTXWADDR[6]) = (0, 0); + ( USERCLK => MIMTXWADDR[7]) = (0, 0); + ( USERCLK => MIMTXWADDR[8]) = (0, 0); + ( USERCLK => MIMTXWADDR[9]) = (0, 0); + ( USERCLK => MIMTXWDATA[0]) = (0, 0); + ( USERCLK => MIMTXWDATA[10]) = (0, 0); + ( USERCLK => MIMTXWDATA[11]) = (0, 0); + ( USERCLK => MIMTXWDATA[12]) = (0, 0); + ( USERCLK => MIMTXWDATA[13]) = (0, 0); + ( USERCLK => MIMTXWDATA[14]) = (0, 0); + ( USERCLK => MIMTXWDATA[15]) = (0, 0); + ( USERCLK => MIMTXWDATA[16]) = (0, 0); + ( USERCLK => MIMTXWDATA[17]) = (0, 0); + ( USERCLK => MIMTXWDATA[18]) = (0, 0); + ( USERCLK => MIMTXWDATA[19]) = (0, 0); + ( USERCLK => MIMTXWDATA[1]) = (0, 0); + ( USERCLK => MIMTXWDATA[20]) = (0, 0); + ( USERCLK => MIMTXWDATA[21]) = (0, 0); + ( USERCLK => MIMTXWDATA[22]) = (0, 0); + ( USERCLK => MIMTXWDATA[23]) = (0, 0); + ( USERCLK => MIMTXWDATA[24]) = (0, 0); + ( USERCLK => MIMTXWDATA[25]) = (0, 0); + ( USERCLK => MIMTXWDATA[26]) = (0, 0); + ( USERCLK => MIMTXWDATA[27]) = (0, 0); + ( USERCLK => MIMTXWDATA[28]) = (0, 0); + ( USERCLK => MIMTXWDATA[29]) = (0, 0); + ( USERCLK => MIMTXWDATA[2]) = (0, 0); + ( USERCLK => MIMTXWDATA[30]) = (0, 0); + ( USERCLK => MIMTXWDATA[31]) = (0, 0); + ( USERCLK => MIMTXWDATA[32]) = (0, 0); + ( USERCLK => MIMTXWDATA[33]) = (0, 0); + ( USERCLK => MIMTXWDATA[34]) = (0, 0); + ( USERCLK => MIMTXWDATA[35]) = (0, 0); + ( USERCLK => MIMTXWDATA[3]) = (0, 0); + ( USERCLK => MIMTXWDATA[4]) = (0, 0); + ( USERCLK => MIMTXWDATA[5]) = (0, 0); + ( USERCLK => MIMTXWDATA[6]) = (0, 0); + ( USERCLK => MIMTXWDATA[7]) = (0, 0); + ( USERCLK => MIMTXWDATA[8]) = (0, 0); + ( USERCLK => MIMTXWDATA[9]) = (0, 0); + ( USERCLK => MIMTXWEN) = (0, 0); + ( USERCLK => RECEIVEDHOTRESET) = (0, 0); + ( USERCLK => TRNFCCPLD[0]) = (0, 0); + ( USERCLK => TRNFCCPLD[10]) = (0, 0); + ( USERCLK => TRNFCCPLD[11]) = (0, 0); + ( USERCLK => TRNFCCPLD[1]) = (0, 0); + ( USERCLK => TRNFCCPLD[2]) = (0, 0); + ( USERCLK => TRNFCCPLD[3]) = (0, 0); + ( USERCLK => TRNFCCPLD[4]) = (0, 0); + ( USERCLK => TRNFCCPLD[5]) = (0, 0); + ( USERCLK => TRNFCCPLD[6]) = (0, 0); + ( USERCLK => TRNFCCPLD[7]) = (0, 0); + ( USERCLK => TRNFCCPLD[8]) = (0, 0); + ( USERCLK => TRNFCCPLD[9]) = (0, 0); + ( USERCLK => TRNFCCPLH[0]) = (0, 0); + ( USERCLK => TRNFCCPLH[1]) = (0, 0); + ( USERCLK => TRNFCCPLH[2]) = (0, 0); + ( USERCLK => TRNFCCPLH[3]) = (0, 0); + ( USERCLK => TRNFCCPLH[4]) = (0, 0); + ( USERCLK => TRNFCCPLH[5]) = (0, 0); + ( USERCLK => TRNFCCPLH[6]) = (0, 0); + ( USERCLK => TRNFCCPLH[7]) = (0, 0); + ( USERCLK => TRNFCNPD[0]) = (0, 0); + ( USERCLK => TRNFCNPD[10]) = (0, 0); + ( USERCLK => TRNFCNPD[11]) = (0, 0); + ( USERCLK => TRNFCNPD[1]) = (0, 0); + ( USERCLK => TRNFCNPD[2]) = (0, 0); + ( USERCLK => TRNFCNPD[3]) = (0, 0); + ( USERCLK => TRNFCNPD[4]) = (0, 0); + ( USERCLK => TRNFCNPD[5]) = (0, 0); + ( USERCLK => TRNFCNPD[6]) = (0, 0); + ( USERCLK => TRNFCNPD[7]) = (0, 0); + ( USERCLK => TRNFCNPD[8]) = (0, 0); + ( USERCLK => TRNFCNPD[9]) = (0, 0); + ( USERCLK => TRNFCNPH[0]) = (0, 0); + ( USERCLK => TRNFCNPH[1]) = (0, 0); + ( USERCLK => TRNFCNPH[2]) = (0, 0); + ( USERCLK => TRNFCNPH[3]) = (0, 0); + ( USERCLK => TRNFCNPH[4]) = (0, 0); + ( USERCLK => TRNFCNPH[5]) = (0, 0); + ( USERCLK => TRNFCNPH[6]) = (0, 0); + ( USERCLK => TRNFCNPH[7]) = (0, 0); + ( USERCLK => TRNFCPD[0]) = (0, 0); + ( USERCLK => TRNFCPD[10]) = (0, 0); + ( USERCLK => TRNFCPD[11]) = (0, 0); + ( USERCLK => TRNFCPD[1]) = (0, 0); + ( USERCLK => TRNFCPD[2]) = (0, 0); + ( USERCLK => TRNFCPD[3]) = (0, 0); + ( USERCLK => TRNFCPD[4]) = (0, 0); + ( USERCLK => TRNFCPD[5]) = (0, 0); + ( USERCLK => TRNFCPD[6]) = (0, 0); + ( USERCLK => TRNFCPD[7]) = (0, 0); + ( USERCLK => TRNFCPD[8]) = (0, 0); + ( USERCLK => TRNFCPD[9]) = (0, 0); + ( USERCLK => TRNFCPH[0]) = (0, 0); + ( USERCLK => TRNFCPH[1]) = (0, 0); + ( USERCLK => TRNFCPH[2]) = (0, 0); + ( USERCLK => TRNFCPH[3]) = (0, 0); + ( USERCLK => TRNFCPH[4]) = (0, 0); + ( USERCLK => TRNFCPH[5]) = (0, 0); + ( USERCLK => TRNFCPH[6]) = (0, 0); + ( USERCLK => TRNFCPH[7]) = (0, 0); + ( USERCLK => TRNLNKUPN) = (0, 0); + ( USERCLK => TRNRBARHITN[0]) = (0, 0); + ( USERCLK => TRNRBARHITN[1]) = (0, 0); + ( USERCLK => TRNRBARHITN[2]) = (0, 0); + ( USERCLK => TRNRBARHITN[3]) = (0, 0); + ( USERCLK => TRNRBARHITN[4]) = (0, 0); + ( USERCLK => TRNRBARHITN[5]) = (0, 0); + ( USERCLK => TRNRBARHITN[6]) = (0, 0); + ( USERCLK => TRNRD[0]) = (0, 0); + ( USERCLK => TRNRD[10]) = (0, 0); + ( USERCLK => TRNRD[11]) = (0, 0); + ( USERCLK => TRNRD[12]) = (0, 0); + ( USERCLK => TRNRD[13]) = (0, 0); + ( USERCLK => TRNRD[14]) = (0, 0); + ( USERCLK => TRNRD[15]) = (0, 0); + ( USERCLK => TRNRD[16]) = (0, 0); + ( USERCLK => TRNRD[17]) = (0, 0); + ( USERCLK => TRNRD[18]) = (0, 0); + ( USERCLK => TRNRD[19]) = (0, 0); + ( USERCLK => TRNRD[1]) = (0, 0); + ( USERCLK => TRNRD[20]) = (0, 0); + ( USERCLK => TRNRD[21]) = (0, 0); + ( USERCLK => TRNRD[22]) = (0, 0); + ( USERCLK => TRNRD[23]) = (0, 0); + ( USERCLK => TRNRD[24]) = (0, 0); + ( USERCLK => TRNRD[25]) = (0, 0); + ( USERCLK => TRNRD[26]) = (0, 0); + ( USERCLK => TRNRD[27]) = (0, 0); + ( USERCLK => TRNRD[28]) = (0, 0); + ( USERCLK => TRNRD[29]) = (0, 0); + ( USERCLK => TRNRD[2]) = (0, 0); + ( USERCLK => TRNRD[30]) = (0, 0); + ( USERCLK => TRNRD[31]) = (0, 0); + ( USERCLK => TRNRD[3]) = (0, 0); + ( USERCLK => TRNRD[4]) = (0, 0); + ( USERCLK => TRNRD[5]) = (0, 0); + ( USERCLK => TRNRD[6]) = (0, 0); + ( USERCLK => TRNRD[7]) = (0, 0); + ( USERCLK => TRNRD[8]) = (0, 0); + ( USERCLK => TRNRD[9]) = (0, 0); + ( USERCLK => TRNREOFN) = (0, 0); + ( USERCLK => TRNRERRFWDN) = (0, 0); + ( USERCLK => TRNRSOFN) = (0, 0); + ( USERCLK => TRNRSRCDSCN) = (0, 0); + ( USERCLK => TRNRSRCRDYN) = (0, 0); + ( USERCLK => TRNTBUFAV[0]) = (0, 0); + ( USERCLK => TRNTBUFAV[1]) = (0, 0); + ( USERCLK => TRNTBUFAV[2]) = (0, 0); + ( USERCLK => TRNTBUFAV[3]) = (0, 0); + ( USERCLK => TRNTBUFAV[4]) = (0, 0); + ( USERCLK => TRNTBUFAV[5]) = (0, 0); + ( USERCLK => TRNTCFGREQN) = (0, 0); + ( USERCLK => TRNTDSTRDYN) = (0, 0); + ( USERCLK => TRNTERRDROPN) = (0, 0); + ( USERCLK => USERRSTN) = (0, 0); + + specparam PATHPULSE$ = 0; + endspecify +endmodule // PCIE_A1 diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/PCIE_EP.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/PCIE_EP.v new file mode 100644 index 0000000..12237cd --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/PCIE_EP.v @@ -0,0 +1,1425 @@ +/////////////////////////////////////////////////////////// +// Copyright (c) 1995/2006 Xilinx Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////// +// +// ____ ___ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / PCI Express +// /__/ /\ Filename : PCIE_EP.v +// \ \ / \ Timestamp : Thu Dec 8 2005 +// \__\/\__ \ +// +// Revision: +// CR#421379 - 08/14/06 - Initial version. +// - 10/26/06 - Remove in_delay, out_delay localparam +// CR#430518 - 12/05/06 - Add LLKRXDSTCONTREQN +// CR#435993 - 03/13/07 - Add LLKTXCONFIGREADYN +// End Revision +/////////////////////////////////////////////////////////// + +`timescale 1 ps / 1 ps + +module PCIE_EP ( + BUSMASTERENABLE, + CRMDOHOTRESETN, + CRMPWRSOFTRESETN, + DLLTXPMDLLPOUTSTANDING, + INTERRUPTDISABLE, + IOSPACEENABLE, + L0CFGLOOPBACKACK, + L0COMPLETERID, + L0DLLERRORVECTOR, + L0DLLRXACKOUTSTANDING, + L0DLLTXNONFCOUTSTANDING, + L0DLLTXOUTSTANDING, + L0DLLVCSTATUS, + L0DLUPDOWN, + L0FIRSTCFGWRITEOCCURRED, + L0LTSSMSTATE, + L0MACENTEREDL0, + L0MACLINKTRAINING, + L0MACLINKUP, + L0MACNEGOTIATEDLINKWIDTH, + L0MACNEWSTATEACK, + L0MACRXL0SSTATE, + L0MSIENABLE0, + L0MULTIMSGEN0, + L0PMEACK, + L0PMEEN, + L0PMEREQOUT, + L0PWRL1STATE, + L0PWRL23READYSTATE, + L0PWRSTATE0, + L0PWRTURNOFFREQ, + L0PWRTXL0SSTATE, + L0RXDLLPM, + L0RXDLLPMTYPE, + L0RXMACLINKERROR, + L0STATSCFGOTHERRECEIVED, + L0STATSCFGOTHERTRANSMITTED, + L0STATSCFGRECEIVED, + L0STATSCFGTRANSMITTED, + L0STATSDLLPRECEIVED, + L0STATSDLLPTRANSMITTED, + L0STATSOSRECEIVED, + L0STATSOSTRANSMITTED, + L0STATSTLPRECEIVED, + L0STATSTLPTRANSMITTED, + L0UNLOCKRECEIVED, + LLKRXCHCOMPLETIONAVAILABLEN, + LLKRXCHNONPOSTEDAVAILABLEN, + LLKRXCHPOSTEDAVAILABLEN, + LLKRXDATA, + LLKRXEOFN, + LLKRXEOPN, + LLKRXPREFERREDTYPE, + LLKRXSOFN, + LLKRXSOPN, + LLKRXSRCLASTREQN, + LLKRXSRCRDYN, + LLKRXVALIDN, + LLKTCSTATUS, + LLKTXCHANSPACE, + LLKTXCHCOMPLETIONREADYN, + LLKTXCHNONPOSTEDREADYN, + LLKTXCHPOSTEDREADYN, + LLKTXCONFIGREADYN, + LLKTXDSTRDYN, + MAXPAYLOADSIZE, + MAXREADREQUESTSIZE, + MEMSPACEENABLE, + MGMTPSO, + MGMTRDATA, + MGMTSTATSCREDIT, + MIMDLLBRADD, + MIMDLLBREN, + MIMDLLBWADD, + MIMDLLBWDATA, + MIMDLLBWEN, + MIMRXBRADD, + MIMRXBREN, + MIMRXBWADD, + MIMRXBWDATA, + MIMRXBWEN, + MIMTXBRADD, + MIMTXBREN, + MIMTXBWADD, + MIMTXBWDATA, + MIMTXBWEN, + PARITYERRORRESPONSE, + PIPEDESKEWLANESL0, + PIPEDESKEWLANESL1, + PIPEDESKEWLANESL2, + PIPEDESKEWLANESL3, + PIPEDESKEWLANESL4, + PIPEDESKEWLANESL5, + PIPEDESKEWLANESL6, + PIPEDESKEWLANESL7, + PIPEPOWERDOWNL0, + PIPEPOWERDOWNL1, + PIPEPOWERDOWNL2, + PIPEPOWERDOWNL3, + PIPEPOWERDOWNL4, + PIPEPOWERDOWNL5, + PIPEPOWERDOWNL6, + PIPEPOWERDOWNL7, + PIPERESETL0, + PIPERESETL1, + PIPERESETL2, + PIPERESETL3, + PIPERESETL4, + PIPERESETL5, + PIPERESETL6, + PIPERESETL7, + PIPERXPOLARITYL0, + PIPERXPOLARITYL1, + PIPERXPOLARITYL2, + PIPERXPOLARITYL3, + PIPERXPOLARITYL4, + PIPERXPOLARITYL5, + PIPERXPOLARITYL6, + PIPERXPOLARITYL7, + PIPETXCOMPLIANCEL0, + PIPETXCOMPLIANCEL1, + PIPETXCOMPLIANCEL2, + PIPETXCOMPLIANCEL3, + PIPETXCOMPLIANCEL4, + PIPETXCOMPLIANCEL5, + PIPETXCOMPLIANCEL6, + PIPETXCOMPLIANCEL7, + PIPETXDATAKL0, + PIPETXDATAKL1, + PIPETXDATAKL2, + PIPETXDATAKL3, + PIPETXDATAKL4, + PIPETXDATAKL5, + PIPETXDATAKL6, + PIPETXDATAKL7, + PIPETXDATAL0, + PIPETXDATAL1, + PIPETXDATAL2, + PIPETXDATAL3, + PIPETXDATAL4, + PIPETXDATAL5, + PIPETXDATAL6, + PIPETXDATAL7, + PIPETXDETECTRXLOOPBACKL0, + PIPETXDETECTRXLOOPBACKL1, + PIPETXDETECTRXLOOPBACKL2, + PIPETXDETECTRXLOOPBACKL3, + PIPETXDETECTRXLOOPBACKL4, + PIPETXDETECTRXLOOPBACKL5, + PIPETXDETECTRXLOOPBACKL6, + PIPETXDETECTRXLOOPBACKL7, + PIPETXELECIDLEL0, + PIPETXELECIDLEL1, + PIPETXELECIDLEL2, + PIPETXELECIDLEL3, + PIPETXELECIDLEL4, + PIPETXELECIDLEL5, + PIPETXELECIDLEL6, + PIPETXELECIDLEL7, + SERRENABLE, + URREPORTINGENABLE, + + AUXPOWER, + COMPLIANCEAVOID, + CRMCORECLK, + CRMCORECLKDLO, + CRMCORECLKRXO, + CRMCORECLKTXO, + CRMLINKRSTN, + CRMMACRSTN, + CRMMGMTRSTN, + CRMNVRSTN, + CRMURSTN, + CRMUSERCFGRSTN, + CRMUSERCLK, + CRMUSERCLKRXO, + CRMUSERCLKTXO, + L0CFGDISABLESCRAMBLE, + L0CFGLOOPBACKMASTER, + L0LEGACYINTFUNCT0, + L0MSIREQUEST0, + L0PACKETHEADERFROMUSER, + L0PMEREQIN, + L0SETCOMPLETERABORTERROR, + L0SETCOMPLETIONTIMEOUTCORRERROR, + L0SETCOMPLETIONTIMEOUTUNCORRERROR, + L0SETDETECTEDCORRERROR, + L0SETDETECTEDFATALERROR, + L0SETDETECTEDNONFATALERROR, + L0SETUNEXPECTEDCOMPLETIONCORRERROR, + L0SETUNEXPECTEDCOMPLETIONUNCORRERROR, + L0SETUNSUPPORTEDREQUESTNONPOSTEDERROR, + L0SETUNSUPPORTEDREQUESTOTHERERROR, + L0SETUSERDETECTEDPARITYERROR, + L0SETUSERMASTERDATAPARITY, + L0SETUSERRECEIVEDMASTERABORT, + L0SETUSERRECEIVEDTARGETABORT, + L0SETUSERSIGNALLEDTARGETABORT, + L0SETUSERSYSTEMERROR, + L0TRANSACTIONSPENDING, + LLKRXCHFIFO, + LLKRXCHTC, + LLKRXDSTCONTREQN, + LLKRXDSTREQN, + LLKTXCHFIFO, + LLKTXCHTC, + LLKTXDATA, + LLKTXENABLEN, + LLKTXEOFN, + LLKTXEOPN, + LLKTXSOFN, + LLKTXSOPN, + LLKTXSRCDSCN, + LLKTXSRCRDYN, + MGMTADDR, + MGMTBWREN, + MGMTRDEN, + MGMTSTATSCREDITSEL, + MGMTWDATA, + MGMTWREN, + MIMDLLBRDATA, + MIMRXBRDATA, + MIMTXBRDATA, + PIPEPHYSTATUSL0, + PIPEPHYSTATUSL1, + PIPEPHYSTATUSL2, + PIPEPHYSTATUSL3, + PIPEPHYSTATUSL4, + PIPEPHYSTATUSL5, + PIPEPHYSTATUSL6, + PIPEPHYSTATUSL7, + PIPERXCHANISALIGNEDL0, + PIPERXCHANISALIGNEDL1, + PIPERXCHANISALIGNEDL2, + PIPERXCHANISALIGNEDL3, + PIPERXCHANISALIGNEDL4, + PIPERXCHANISALIGNEDL5, + PIPERXCHANISALIGNEDL6, + PIPERXCHANISALIGNEDL7, + PIPERXDATAKL0, + PIPERXDATAKL1, + PIPERXDATAKL2, + PIPERXDATAKL3, + PIPERXDATAKL4, + PIPERXDATAKL5, + PIPERXDATAKL6, + PIPERXDATAKL7, + PIPERXDATAL0, + PIPERXDATAL1, + PIPERXDATAL2, + PIPERXDATAL3, + PIPERXDATAL4, + PIPERXDATAL5, + PIPERXDATAL6, + PIPERXDATAL7, + PIPERXELECIDLEL0, + PIPERXELECIDLEL1, + PIPERXELECIDLEL2, + PIPERXELECIDLEL3, + PIPERXELECIDLEL4, + PIPERXELECIDLEL5, + PIPERXELECIDLEL6, + PIPERXELECIDLEL7, + PIPERXSTATUSL0, + PIPERXSTATUSL1, + PIPERXSTATUSL2, + PIPERXSTATUSL3, + PIPERXSTATUSL4, + PIPERXSTATUSL5, + PIPERXSTATUSL6, + PIPERXSTATUSL7, + PIPERXVALIDL0, + PIPERXVALIDL1, + PIPERXVALIDL2, + PIPERXVALIDL3, + PIPERXVALIDL4, + PIPERXVALIDL5, + PIPERXVALIDL6, + PIPERXVALIDL7 + +); + +parameter BAR0EXIST = "TRUE"; +parameter BAR0PREFETCHABLE = "TRUE"; +parameter BAR1EXIST = "FALSE"; +parameter BAR1PREFETCHABLE = "FALSE"; +parameter BAR2EXIST = "FALSE"; +parameter BAR2PREFETCHABLE = "FALSE"; +parameter BAR3EXIST = "FALSE"; +parameter BAR3PREFETCHABLE = "FALSE"; +parameter BAR4EXIST = "FALSE"; +parameter BAR4PREFETCHABLE = "FALSE"; +parameter BAR5EXIST = "FALSE"; +parameter BAR5PREFETCHABLE = "FALSE"; +parameter CLKDIVIDED = "FALSE"; +parameter INFINITECOMPLETIONS = "TRUE"; +parameter LINKSTATUSSLOTCLOCKCONFIG = "FALSE"; +parameter PBCAPABILITYSYSTEMALLOCATED = "FALSE"; +parameter PMCAPABILITYD1SUPPORT = "FALSE"; +parameter PMCAPABILITYD2SUPPORT = "FALSE"; +parameter PMCAPABILITYDSI = "TRUE"; +parameter RESETMODE = "FALSE"; +parameter [10:0] VC0TOTALCREDITSCD = 11'h0; +parameter [10:0] VC0TOTALCREDITSPD = 11'h34; +parameter [10:0] VC1TOTALCREDITSCD = 11'h0; +parameter [10:0] VC1TOTALCREDITSPD = 11'h0; +parameter [11:0] AERBASEPTR = 12'h110; +parameter [11:0] AERCAPABILITYNEXTPTR = 12'h138; +parameter [11:0] DSNBASEPTR = 12'h148; +parameter [11:0] DSNCAPABILITYNEXTPTR = 12'h154; +parameter [11:0] MSIBASEPTR = 12'h48; +parameter [11:0] PBBASEPTR = 12'h138; +parameter [11:0] PBCAPABILITYNEXTPTR = 12'h148; +parameter [11:0] PMBASEPTR = 12'h40; +parameter [11:0] RETRYRAMSIZE = 12'h9; +parameter [11:0] VCBASEPTR = 12'h154; +parameter [11:0] VCCAPABILITYNEXTPTR = 12'h0; +parameter [12:0] VC0RXFIFOBASEC = 13'h98; +parameter [12:0] VC0RXFIFOBASENP = 13'h80; +parameter [12:0] VC0RXFIFOBASEP = 13'h0; +parameter [12:0] VC0RXFIFOLIMITC = 13'h117; +parameter [12:0] VC0RXFIFOLIMITNP = 13'h97; +parameter [12:0] VC0RXFIFOLIMITP = 13'h7f; +parameter [12:0] VC0TXFIFOBASEC = 13'h98; +parameter [12:0] VC0TXFIFOBASENP = 13'h80; +parameter [12:0] VC0TXFIFOBASEP = 13'h0; +parameter [12:0] VC0TXFIFOLIMITC = 13'h117; +parameter [12:0] VC0TXFIFOLIMITNP = 13'h97; +parameter [12:0] VC0TXFIFOLIMITP = 13'h7f; +parameter [12:0] VC1RXFIFOBASEC = 13'h118; +parameter [12:0] VC1RXFIFOBASENP = 13'h118; +parameter [12:0] VC1RXFIFOBASEP = 13'h118; +parameter [12:0] VC1RXFIFOLIMITC = 13'h118; +parameter [12:0] VC1RXFIFOLIMITNP = 13'h118; +parameter [12:0] VC1RXFIFOLIMITP = 13'h118; +parameter [12:0] VC1TXFIFOBASEC = 13'h118; +parameter [12:0] VC1TXFIFOBASENP = 13'h118; +parameter [12:0] VC1TXFIFOBASEP = 13'h118; +parameter [12:0] VC1TXFIFOLIMITC = 13'h118; +parameter [12:0] VC1TXFIFOLIMITNP = 13'h118; +parameter [12:0] VC1TXFIFOLIMITP = 13'h118; +parameter [15:0] DEVICEID = 16'h5050; +parameter [15:0] SUBSYSTEMID = 16'h5050; +parameter [15:0] SUBSYSTEMVENDORID = 16'h10EE; +parameter [15:0] VENDORID = 16'h10EE; +parameter [1:0] LINKCAPABILITYASPMSUPPORT = 2'h1; +parameter [1:0] PBCAPABILITYDW0DATASCALE = 2'h0; +parameter [1:0] PBCAPABILITYDW0PMSTATE = 2'h0; +parameter [1:0] PBCAPABILITYDW1DATASCALE = 2'h0; +parameter [1:0] PBCAPABILITYDW1PMSTATE = 2'h0; +parameter [1:0] PBCAPABILITYDW2DATASCALE = 2'h0; +parameter [1:0] PBCAPABILITYDW2PMSTATE = 2'h0; +parameter [1:0] PBCAPABILITYDW3DATASCALE = 2'h0; +parameter [1:0] PBCAPABILITYDW3PMSTATE = 2'h0; +parameter [23:0] CLASSCODE = 24'h058000; +parameter [2:0] DEVICECAPABILITYENDPOINTL0SLATENCY = 3'h0; +parameter [2:0] DEVICECAPABILITYENDPOINTL1LATENCY = 3'h0; +parameter [2:0] MSICAPABILITYMULTIMSGCAP = 3'h0; +parameter [2:0] PBCAPABILITYDW0PMSUBSTATE = 3'h0; +parameter [2:0] PBCAPABILITYDW0POWERRAIL = 3'h0; +parameter [2:0] PBCAPABILITYDW0TYPE = 3'h0; +parameter [2:0] PBCAPABILITYDW1PMSUBSTATE = 3'h0; +parameter [2:0] PBCAPABILITYDW1POWERRAIL = 3'h0; +parameter [2:0] PBCAPABILITYDW1TYPE = 3'h0; +parameter [2:0] PBCAPABILITYDW2PMSUBSTATE = 3'h0; +parameter [2:0] PBCAPABILITYDW2POWERRAIL = 3'h0; +parameter [2:0] PBCAPABILITYDW2TYPE = 3'h0; +parameter [2:0] PBCAPABILITYDW3PMSUBSTATE = 3'h0; +parameter [2:0] PBCAPABILITYDW3POWERRAIL = 3'h0; +parameter [2:0] PBCAPABILITYDW3TYPE = 3'h0; +parameter [2:0] PMCAPABILITYAUXCURRENT = 3'h0; +parameter [2:0] PORTVCCAPABILITYEXTENDEDVCCOUNT = 3'h0; +parameter [31:0] CARDBUSCISPOINTER = 32'h0; +parameter [3:0] XPDEVICEPORTTYPE = 4'h0; +parameter [4:0] PMCAPABILITYPMESUPPORT = 5'h0; +parameter [5:0] BAR0MASKWIDTH = 6'h14; +parameter [5:0] BAR1MASKWIDTH = 6'h0; +parameter [5:0] BAR2MASKWIDTH = 6'h0; +parameter [5:0] BAR3MASKWIDTH = 6'h0; +parameter [5:0] BAR4MASKWIDTH = 6'h0; +parameter [5:0] BAR5MASKWIDTH = 6'h0; +parameter [5:0] LINKCAPABILITYMAXLINKWIDTH = 6'h01; +parameter [63:0] DEVICESERIALNUMBER = 64'hE000000001000A35; +parameter [6:0] VC0TOTALCREDITSCH = 7'h0; +parameter [6:0] VC0TOTALCREDITSNPH = 7'h08; +parameter [6:0] VC0TOTALCREDITSPH = 7'h08; +parameter [6:0] VC1TOTALCREDITSCH = 7'h0; +parameter [6:0] VC1TOTALCREDITSNPH = 7'h0; +parameter [6:0] VC1TOTALCREDITSPH = 7'h0; +parameter [7:0] ACTIVELANESIN = 8'h1; +parameter [7:0] CAPABILITIESPOINTER = 8'h40; +parameter [7:0] INTERRUPTPIN = 8'h0; +parameter [7:0] MSICAPABILITYNEXTPTR = 8'h60; +parameter [7:0] PBCAPABILITYDW0BASEPOWER = 8'h0; +parameter [7:0] PBCAPABILITYDW1BASEPOWER = 8'h0; +parameter [7:0] PBCAPABILITYDW2BASEPOWER = 8'h0; +parameter [7:0] PBCAPABILITYDW3BASEPOWER = 8'h0; +parameter [7:0] PCIECAPABILITYNEXTPTR = 8'h0; +parameter [7:0] PMCAPABILITYNEXTPTR = 8'h60; +parameter [7:0] PMDATA0 = 8'h0; +parameter [7:0] PMDATA1 = 8'h0; +parameter [7:0] PMDATA2 = 8'h0; +parameter [7:0] PMDATA3 = 8'h0; +parameter [7:0] PMDATA4 = 8'h0; +parameter [7:0] PMDATA5 = 8'h0; +parameter [7:0] PMDATA6 = 8'h0; +parameter [7:0] PMDATA7 = 8'h0; +parameter [7:0] PORTVCCAPABILITYVCARBCAP = 8'h0; +parameter [7:0] PORTVCCAPABILITYVCARBTABLEOFFSET = 8'h0; +parameter [7:0] REVISIONID = 8'h0; +parameter [7:0] XPBASEPTR = 8'h60; +parameter integer BAR0ADDRWIDTH = 0; +parameter integer BAR0IOMEMN = 0; +parameter integer BAR1ADDRWIDTH = 0; +parameter integer BAR1IOMEMN = 0; +parameter integer BAR2ADDRWIDTH = 0; +parameter integer BAR2IOMEMN = 0; +parameter integer BAR3ADDRWIDTH = 0; +parameter integer BAR3IOMEMN = 0; +parameter integer BAR4ADDRWIDTH = 0; +parameter integer BAR4IOMEMN = 0; +parameter integer BAR5IOMEMN = 0; +parameter integer L0SEXITLATENCY = 7; +parameter integer L0SEXITLATENCYCOMCLK = 7; +parameter integer L1EXITLATENCY = 7; +parameter integer L1EXITLATENCYCOMCLK = 7; +parameter integer LOWPRIORITYVCCOUNT = 0; +parameter integer PMDATASCALE0 = 0; +parameter integer PMDATASCALE1 = 0; +parameter integer PMDATASCALE2 = 0; +parameter integer PMDATASCALE3 = 0; +parameter integer PMDATASCALE4 = 0; +parameter integer PMDATASCALE5 = 0; +parameter integer PMDATASCALE6 = 0; +parameter integer PMDATASCALE7 = 0; +parameter integer RETRYRAMREADLATENCY = 3; +parameter integer RETRYRAMWRITELATENCY = 1; +parameter integer TLRAMREADLATENCY = 3; +parameter integer TLRAMWRITELATENCY = 1; +parameter integer TXTSNFTS = 255; +parameter integer TXTSNFTSCOMCLK = 255; +parameter integer XPMAXPAYLOAD = 0; + +output BUSMASTERENABLE; +output CRMDOHOTRESETN; +output CRMPWRSOFTRESETN; +output DLLTXPMDLLPOUTSTANDING; +output INTERRUPTDISABLE; +output IOSPACEENABLE; +output L0CFGLOOPBACKACK; +output L0DLLRXACKOUTSTANDING; +output L0DLLTXNONFCOUTSTANDING; +output L0DLLTXOUTSTANDING; +output L0FIRSTCFGWRITEOCCURRED; +output L0MACENTEREDL0; +output L0MACLINKTRAINING; +output L0MACLINKUP; +output L0MACNEWSTATEACK; +output L0MACRXL0SSTATE; +output L0MSIENABLE0; +output L0PMEACK; +output L0PMEEN; +output L0PMEREQOUT; +output L0PWRL1STATE; +output L0PWRL23READYSTATE; +output L0PWRTURNOFFREQ; +output L0PWRTXL0SSTATE; +output L0RXDLLPM; +output L0STATSCFGOTHERRECEIVED; +output L0STATSCFGOTHERTRANSMITTED; +output L0STATSCFGRECEIVED; +output L0STATSCFGTRANSMITTED; +output L0STATSDLLPRECEIVED; +output L0STATSDLLPTRANSMITTED; +output L0STATSOSRECEIVED; +output L0STATSOSTRANSMITTED; +output L0STATSTLPRECEIVED; +output L0STATSTLPTRANSMITTED; +output L0UNLOCKRECEIVED; +output LLKRXEOFN; +output LLKRXEOPN; +output LLKRXSOFN; +output LLKRXSOPN; +output LLKRXSRCLASTREQN; +output LLKRXSRCRDYN; +output LLKTXCONFIGREADYN; +output LLKTXDSTRDYN; +output MEMSPACEENABLE; +output MIMDLLBREN; +output MIMDLLBWEN; +output MIMRXBREN; +output MIMRXBWEN; +output MIMTXBREN; +output MIMTXBWEN; +output PARITYERRORRESPONSE; +output PIPEDESKEWLANESL0; +output PIPEDESKEWLANESL1; +output PIPEDESKEWLANESL2; +output PIPEDESKEWLANESL3; +output PIPEDESKEWLANESL4; +output PIPEDESKEWLANESL5; +output PIPEDESKEWLANESL6; +output PIPEDESKEWLANESL7; +output PIPERESETL0; +output PIPERESETL1; +output PIPERESETL2; +output PIPERESETL3; +output PIPERESETL4; +output PIPERESETL5; +output PIPERESETL6; +output PIPERESETL7; +output PIPERXPOLARITYL0; +output PIPERXPOLARITYL1; +output PIPERXPOLARITYL2; +output PIPERXPOLARITYL3; +output PIPERXPOLARITYL4; +output PIPERXPOLARITYL5; +output PIPERXPOLARITYL6; +output PIPERXPOLARITYL7; +output PIPETXCOMPLIANCEL0; +output PIPETXCOMPLIANCEL1; +output PIPETXCOMPLIANCEL2; +output PIPETXCOMPLIANCEL3; +output PIPETXCOMPLIANCEL4; +output PIPETXCOMPLIANCEL5; +output PIPETXCOMPLIANCEL6; +output PIPETXCOMPLIANCEL7; +output PIPETXDATAKL0; +output PIPETXDATAKL1; +output PIPETXDATAKL2; +output PIPETXDATAKL3; +output PIPETXDATAKL4; +output PIPETXDATAKL5; +output PIPETXDATAKL6; +output PIPETXDATAKL7; +output PIPETXDETECTRXLOOPBACKL0; +output PIPETXDETECTRXLOOPBACKL1; +output PIPETXDETECTRXLOOPBACKL2; +output PIPETXDETECTRXLOOPBACKL3; +output PIPETXDETECTRXLOOPBACKL4; +output PIPETXDETECTRXLOOPBACKL5; +output PIPETXDETECTRXLOOPBACKL6; +output PIPETXDETECTRXLOOPBACKL7; +output PIPETXELECIDLEL0; +output PIPETXELECIDLEL1; +output PIPETXELECIDLEL2; +output PIPETXELECIDLEL3; +output PIPETXELECIDLEL4; +output PIPETXELECIDLEL5; +output PIPETXELECIDLEL6; +output PIPETXELECIDLEL7; +output SERRENABLE; +output URREPORTINGENABLE; +output [11:0] MGMTSTATSCREDIT; +output [11:0] MIMDLLBRADD; +output [11:0] MIMDLLBWADD; +output [12:0] L0COMPLETERID; +output [12:0] MIMRXBRADD; +output [12:0] MIMRXBWADD; +output [12:0] MIMTXBRADD; +output [12:0] MIMTXBWADD; +output [15:0] LLKRXPREFERREDTYPE; +output [16:0] MGMTPSO; +output [1:0] L0PWRSTATE0; +output [1:0] L0RXMACLINKERROR; +output [1:0] LLKRXVALIDN; +output [1:0] PIPEPOWERDOWNL0; +output [1:0] PIPEPOWERDOWNL1; +output [1:0] PIPEPOWERDOWNL2; +output [1:0] PIPEPOWERDOWNL3; +output [1:0] PIPEPOWERDOWNL4; +output [1:0] PIPEPOWERDOWNL5; +output [1:0] PIPEPOWERDOWNL6; +output [1:0] PIPEPOWERDOWNL7; +output [2:0] L0MULTIMSGEN0; +output [2:0] L0RXDLLPMTYPE; +output [2:0] MAXPAYLOADSIZE; +output [2:0] MAXREADREQUESTSIZE; +output [31:0] MGMTRDATA; +output [3:0] L0LTSSMSTATE; +output [3:0] L0MACNEGOTIATEDLINKWIDTH; +output [63:0] LLKRXDATA; +output [63:0] MIMDLLBWDATA; +output [63:0] MIMRXBWDATA; +output [63:0] MIMTXBWDATA; +output [6:0] L0DLLERRORVECTOR; +output [7:0] L0DLLVCSTATUS; +output [7:0] L0DLUPDOWN; +output [7:0] LLKRXCHCOMPLETIONAVAILABLEN; +output [7:0] LLKRXCHNONPOSTEDAVAILABLEN; +output [7:0] LLKRXCHPOSTEDAVAILABLEN; +output [7:0] LLKTCSTATUS; +output [7:0] LLKTXCHCOMPLETIONREADYN; +output [7:0] LLKTXCHNONPOSTEDREADYN; +output [7:0] LLKTXCHPOSTEDREADYN; +output [7:0] PIPETXDATAL0; +output [7:0] PIPETXDATAL1; +output [7:0] PIPETXDATAL2; +output [7:0] PIPETXDATAL3; +output [7:0] PIPETXDATAL4; +output [7:0] PIPETXDATAL5; +output [7:0] PIPETXDATAL6; +output [7:0] PIPETXDATAL7; +output [9:0] LLKTXCHANSPACE; + +input AUXPOWER; +input COMPLIANCEAVOID; +input CRMCORECLK; +input CRMCORECLKDLO; +input CRMCORECLKRXO; +input CRMCORECLKTXO; +input CRMLINKRSTN; +input CRMMACRSTN; +input CRMMGMTRSTN; +input CRMNVRSTN; +input CRMURSTN; +input CRMUSERCFGRSTN; +input CRMUSERCLK; +input CRMUSERCLKRXO; +input CRMUSERCLKTXO; +input L0CFGDISABLESCRAMBLE; +input L0CFGLOOPBACKMASTER; +input L0LEGACYINTFUNCT0; +input L0PMEREQIN; +input L0SETCOMPLETERABORTERROR; +input L0SETCOMPLETIONTIMEOUTCORRERROR; +input L0SETCOMPLETIONTIMEOUTUNCORRERROR; +input L0SETDETECTEDCORRERROR; +input L0SETDETECTEDFATALERROR; +input L0SETDETECTEDNONFATALERROR; +input L0SETUNEXPECTEDCOMPLETIONCORRERROR; +input L0SETUNEXPECTEDCOMPLETIONUNCORRERROR; +input L0SETUNSUPPORTEDREQUESTNONPOSTEDERROR; +input L0SETUNSUPPORTEDREQUESTOTHERERROR; +input L0SETUSERDETECTEDPARITYERROR; +input L0SETUSERMASTERDATAPARITY; +input L0SETUSERRECEIVEDMASTERABORT; +input L0SETUSERRECEIVEDTARGETABORT; +input L0SETUSERSIGNALLEDTARGETABORT; +input L0SETUSERSYSTEMERROR; +input L0TRANSACTIONSPENDING; +input LLKRXDSTCONTREQN; +input LLKRXDSTREQN; +input LLKTXEOFN; +input LLKTXEOPN; +input LLKTXSOFN; +input LLKTXSOPN; +input LLKTXSRCDSCN; +input LLKTXSRCRDYN; +input MGMTRDEN; +input MGMTWREN; +input PIPEPHYSTATUSL0; +input PIPEPHYSTATUSL1; +input PIPEPHYSTATUSL2; +input PIPEPHYSTATUSL3; +input PIPEPHYSTATUSL4; +input PIPEPHYSTATUSL5; +input PIPEPHYSTATUSL6; +input PIPEPHYSTATUSL7; +input PIPERXCHANISALIGNEDL0; +input PIPERXCHANISALIGNEDL1; +input PIPERXCHANISALIGNEDL2; +input PIPERXCHANISALIGNEDL3; +input PIPERXCHANISALIGNEDL4; +input PIPERXCHANISALIGNEDL5; +input PIPERXCHANISALIGNEDL6; +input PIPERXCHANISALIGNEDL7; +input PIPERXDATAKL0; +input PIPERXDATAKL1; +input PIPERXDATAKL2; +input PIPERXDATAKL3; +input PIPERXDATAKL4; +input PIPERXDATAKL5; +input PIPERXDATAKL6; +input PIPERXDATAKL7; +input PIPERXELECIDLEL0; +input PIPERXELECIDLEL1; +input PIPERXELECIDLEL2; +input PIPERXELECIDLEL3; +input PIPERXELECIDLEL4; +input PIPERXELECIDLEL5; +input PIPERXELECIDLEL6; +input PIPERXELECIDLEL7; +input PIPERXVALIDL0; +input PIPERXVALIDL1; +input PIPERXVALIDL2; +input PIPERXVALIDL3; +input PIPERXVALIDL4; +input PIPERXVALIDL5; +input PIPERXVALIDL6; +input PIPERXVALIDL7; +input [10:0] MGMTADDR; +input [127:0] L0PACKETHEADERFROMUSER; +input [1:0] LLKRXCHFIFO; +input [1:0] LLKTXCHFIFO; +input [1:0] LLKTXENABLEN; +input [2:0] LLKRXCHTC; +input [2:0] LLKTXCHTC; +input [2:0] PIPERXSTATUSL0; +input [2:0] PIPERXSTATUSL1; +input [2:0] PIPERXSTATUSL2; +input [2:0] PIPERXSTATUSL3; +input [2:0] PIPERXSTATUSL4; +input [2:0] PIPERXSTATUSL5; +input [2:0] PIPERXSTATUSL6; +input [2:0] PIPERXSTATUSL7; +input [31:0] MGMTWDATA; +input [3:0] L0MSIREQUEST0; +input [3:0] MGMTBWREN; +input [63:0] LLKTXDATA; +input [63:0] MIMDLLBRDATA; +input [63:0] MIMRXBRDATA; +input [63:0] MIMTXBRDATA; +input [6:0] MGMTSTATSCREDITSEL; +input [7:0] PIPERXDATAL0; +input [7:0] PIPERXDATAL1; +input [7:0] PIPERXDATAL2; +input [7:0] PIPERXDATAL3; +input [7:0] PIPERXDATAL4; +input [7:0] PIPERXDATAL5; +input [7:0] PIPERXDATAL6; +input [7:0] PIPERXDATAL7; + +wire OPEN_CRMRXHOTRESETN; +wire OPEN_L0ASAUTONOMOUSINITCOMPLETED; +wire OPEN_L0CORRERRMSGRCVD; +wire OPEN_L0DLLASTXSTATE; +wire OPEN_L0FATALERRMSGRCVD; +wire OPEN_L0FWDCORRERROUT; +wire OPEN_L0FWDFATALERROUT; +wire OPEN_L0FWDNONFATALERROUT; +wire OPEN_L0MACUPSTREAMDOWNSTREAM; +wire OPEN_L0NONFATALERRMSGRCVD; +wire OPEN_L0POWERCONTROLLERCONTROL; +wire OPEN_L0PWRINHIBITTRANSFERS; +wire OPEN_L0PWRL23READYDEVICE; +wire OPEN_L0RECEIVEDASSERTINTALEGACYINT; +wire OPEN_L0RECEIVEDASSERTINTBLEGACYINT; +wire OPEN_L0RECEIVEDASSERTINTCLEGACYINT; +wire OPEN_L0RECEIVEDASSERTINTDLEGACYINT; +wire OPEN_L0RECEIVEDDEASSERTINTALEGACYINT; +wire OPEN_L0RECEIVEDDEASSERTINTBLEGACYINT; +wire OPEN_L0RECEIVEDDEASSERTINTCLEGACYINT; +wire OPEN_L0RECEIVEDDEASSERTINTDLEGACYINT; +wire OPEN_L0RXBEACON; +wire OPEN_L0RXDLLSBFCUPDATE; +wire OPEN_L0RXDLLTLPECRCOK; +wire OPEN_L0TOGGLEELECTROMECHANICALINTERLOCK; +wire OPEN_L0TXDLLPMUPDATED; +wire OPEN_L0TXDLLSBFCUPDATED; +wire OPEN_LLKRX4DWHEADERN; +wire OPEN_LLKRXCHCONFIGAVAILABLEN; +wire OPEN_LLKRXCHCONFIGPARTIALN; +wire OPEN_LLKRXECRCBADN; +wire OPEN_LLKRXSRCDSCN; +wire [15:0] OPEN_L0ERRMSGREQID; +wire [18:0] OPEN_L0RXDLLSBFCDATA; +wire [19:0] OPEN_L0RXDLLFCNPOSTBYPCRED; +wire [1:0] OPEN_L0ATTENTIONINDICATORCONTROL; +wire [1:0] OPEN_L0DLLASRXSTATE; +wire [1:0] OPEN_L0POWERINDICATORCONTROL; +wire [1:0] OPEN_L0RXDLLTLPEND; +wire [23:0] OPEN_L0RXDLLFCCMPLMCCRED; +wire [23:0] OPEN_L0RXDLLFCPOSTORDCRED; +wire [2:0] OPEN_L0MCFOUND; +wire [2:0] OPEN_L0TRANSFORMEDVC; +wire [3:0] OPEN_L0UCBYPFOUND; +wire [3:0] OPEN_L0UCORDFOUND; +wire [7:0] OPEN_L0RXDLLFCCMPLMCUPDATE; +wire [7:0] OPEN_L0RXDLLFCNPOSTBYPUPDATE; +wire [7:0] OPEN_L0RXDLLFCPOSTORDUPDATE; +wire [7:0] OPEN_L0TXDLLFCCMPLMCUPDATED; +wire [7:0] OPEN_L0TXDLLFCNPOSTBYPUPDATED; +wire [7:0] OPEN_L0TXDLLFCPOSTORDUPDATED; +wire [7:0] OPEN_LLKRXCHCOMPLETIONPARTIALN; +wire [7:0] OPEN_LLKRXCHNONPOSTEDPARTIALN; +wire [7:0] OPEN_LLKRXCHPOSTEDPARTIALN; + +PCIE_INTERNAL_1_1 pcie_internal_1_1_1 ( + .AUXPOWER (AUXPOWER), + .BUSMASTERENABLE (BUSMASTERENABLE), + .CFGNEGOTIATEDLINKWIDTH (6'b0), + .COMPLIANCEAVOID (COMPLIANCEAVOID), + .CRMCFGBRIDGEHOTRESET (1'b0), + .CRMCORECLK (CRMCORECLK), + .CRMCORECLKDLO (CRMCORECLKDLO), + .CRMCORECLKRXO (CRMCORECLKRXO), + .CRMCORECLKTXO (CRMCORECLKTXO), + .CRMDOHOTRESETN (CRMDOHOTRESETN), + .CRMLINKRSTN (CRMLINKRSTN), + .CRMMACRSTN (CRMMACRSTN), + .CRMMGMTRSTN (CRMMGMTRSTN), + .CRMNVRSTN (CRMNVRSTN), + .CRMPWRSOFTRESETN (CRMPWRSOFTRESETN), + .CRMRXHOTRESETN (OPEN_CRMRXHOTRESETN), + .CRMTXHOTRESETN (1'b1), + .CRMURSTN (CRMURSTN), + .CRMUSERCFGRSTN (CRMUSERCFGRSTN), + .CRMUSERCLK (CRMUSERCLK), + .CRMUSERCLKRXO (CRMUSERCLKRXO), + .CRMUSERCLKTXO (CRMUSERCLKTXO), + .CROSSLINKSEED (1'b1), + .DLLTXPMDLLPOUTSTANDING (DLLTXPMDLLPOUTSTANDING), + .INTERRUPTDISABLE (INTERRUPTDISABLE), + .IOSPACEENABLE (IOSPACEENABLE), + .L0ACKNAKTIMERADJUSTMENT (12'b0), + .L0ALLDOWNPORTSINL1 (1'b0), + .L0ALLDOWNRXPORTSINL0S (1'b0), + .L0ASAUTONOMOUSINITCOMPLETED (OPEN_L0ASAUTONOMOUSINITCOMPLETED), + .L0ASE (1'b0), + .L0ASPORTCOUNT (8'b0), + .L0ASTURNPOOLBITSCONSUMED (3'b0), + .L0ATTENTIONBUTTONPRESSED (1'b0), + .L0ATTENTIONINDICATORCONTROL (OPEN_L0ATTENTIONINDICATORCONTROL), + .L0CFGASSPANTREEOWNEDSTATE (1'b0), + .L0CFGASSTATECHANGECMD (4'b0), + .L0CFGDISABLESCRAMBLE (L0CFGDISABLESCRAMBLE), + .L0CFGEXTENDEDSYNC (1'b0), + .L0CFGL0SENTRYENABLE (1'b0), + .L0CFGL0SENTRYSUP (1'b0), + .L0CFGL0SEXITLAT (3'b0), + .L0CFGLINKDISABLE (1'b0), + .L0CFGLOOPBACKACK (L0CFGLOOPBACKACK), + .L0CFGLOOPBACKMASTER (L0CFGLOOPBACKMASTER), + .L0CFGNEGOTIATEDMAXP (3'b0), + .L0CFGVCENABLE (8'b0), + .L0CFGVCID (24'b0), + .L0COMPLETERID (L0COMPLETERID), + .L0CORRERRMSGRCVD (OPEN_L0CORRERRMSGRCVD), + .L0DLLASRXSTATE (OPEN_L0DLLASRXSTATE), + .L0DLLASTXSTATE (OPEN_L0DLLASTXSTATE), + .L0DLLERRORVECTOR (L0DLLERRORVECTOR), + .L0DLLHOLDLINKUP (1'b0), + .L0DLLRXACKOUTSTANDING (L0DLLRXACKOUTSTANDING), + .L0DLLTXNONFCOUTSTANDING (L0DLLTXNONFCOUTSTANDING), + .L0DLLTXOUTSTANDING (L0DLLTXOUTSTANDING), + .L0DLLVCSTATUS (L0DLLVCSTATUS), + .L0DLUPDOWN (L0DLUPDOWN), + .L0ELECTROMECHANICALINTERLOCKENGAGED (1'b0), + .L0ERRMSGREQID (OPEN_L0ERRMSGREQID), + .L0FATALERRMSGRCVD (OPEN_L0FATALERRMSGRCVD), + .L0FIRSTCFGWRITEOCCURRED (L0FIRSTCFGWRITEOCCURRED), + .L0FWDASSERTINTALEGACYINT (1'b0), + .L0FWDASSERTINTBLEGACYINT (1'b0), + .L0FWDASSERTINTCLEGACYINT (1'b0), + .L0FWDASSERTINTDLEGACYINT (1'b0), + .L0FWDCORRERRIN (1'b0), + .L0FWDCORRERROUT (OPEN_L0FWDCORRERROUT), + .L0FWDDEASSERTINTALEGACYINT (1'b0), + .L0FWDDEASSERTINTBLEGACYINT (1'b0), + .L0FWDDEASSERTINTCLEGACYINT (1'b0), + .L0FWDDEASSERTINTDLEGACYINT (1'b0), + .L0FWDFATALERRIN (1'b0), + .L0FWDFATALERROUT (OPEN_L0FWDFATALERROUT), + .L0FWDNONFATALERRIN (1'b0), + .L0FWDNONFATALERROUT (OPEN_L0FWDNONFATALERROUT), + .L0LEGACYINTFUNCT0 (L0LEGACYINTFUNCT0), + .L0LTSSMSTATE (L0LTSSMSTATE), + .L0MACENTEREDL0 (L0MACENTEREDL0), + .L0MACLINKTRAINING (L0MACLINKTRAINING), + .L0MACLINKUP (L0MACLINKUP), + .L0MACNEGOTIATEDLINKWIDTH (L0MACNEGOTIATEDLINKWIDTH), + .L0MACNEWSTATEACK (L0MACNEWSTATEACK), + .L0MACRXL0SSTATE (L0MACRXL0SSTATE), + .L0MACUPSTREAMDOWNSTREAM (OPEN_L0MACUPSTREAMDOWNSTREAM), + .L0MCFOUND (OPEN_L0MCFOUND), + .L0MRLSENSORCLOSEDN (1'b0), + .L0MSIENABLE0 (L0MSIENABLE0), + .L0MSIREQUEST0 (L0MSIREQUEST0), + .L0MULTIMSGEN0 (L0MULTIMSGEN0), + .L0NONFATALERRMSGRCVD (OPEN_L0NONFATALERRMSGRCVD), + .L0PACKETHEADERFROMUSER (L0PACKETHEADERFROMUSER), + .L0PMEACK (L0PMEACK), + .L0PMEEN (L0PMEEN), + .L0PMEREQIN (L0PMEREQIN), + .L0PMEREQOUT (L0PMEREQOUT), + .L0PORTNUMBER (8'b0), + .L0POWERCONTROLLERCONTROL (OPEN_L0POWERCONTROLLERCONTROL), + .L0POWERFAULTDETECTED (1'b0), + .L0POWERINDICATORCONTROL (OPEN_L0POWERINDICATORCONTROL), + .L0PRESENCEDETECTSLOTEMPTYN (1'b0), + .L0PWRINHIBITTRANSFERS (OPEN_L0PWRINHIBITTRANSFERS), + .L0PWRL1STATE (L0PWRL1STATE), + .L0PWRL23READYDEVICE (OPEN_L0PWRL23READYDEVICE), + .L0PWRL23READYSTATE (L0PWRL23READYSTATE), + .L0PWRNEWSTATEREQ (1'b0), + .L0PWRNEXTLINKSTATE (2'b0), + .L0PWRSTATE0 (L0PWRSTATE0), + .L0PWRTURNOFFREQ (L0PWRTURNOFFREQ), + .L0PWRTXL0SSTATE (L0PWRTXL0SSTATE), + .L0RECEIVEDASSERTINTALEGACYINT (OPEN_L0RECEIVEDASSERTINTALEGACYINT), + .L0RECEIVEDASSERTINTBLEGACYINT (OPEN_L0RECEIVEDASSERTINTBLEGACYINT), + .L0RECEIVEDASSERTINTCLEGACYINT (OPEN_L0RECEIVEDASSERTINTCLEGACYINT), + .L0RECEIVEDASSERTINTDLEGACYINT (OPEN_L0RECEIVEDASSERTINTDLEGACYINT), + .L0RECEIVEDDEASSERTINTALEGACYINT (OPEN_L0RECEIVEDDEASSERTINTALEGACYINT), + .L0RECEIVEDDEASSERTINTBLEGACYINT (OPEN_L0RECEIVEDDEASSERTINTBLEGACYINT), + .L0RECEIVEDDEASSERTINTCLEGACYINT (OPEN_L0RECEIVEDDEASSERTINTCLEGACYINT), + .L0RECEIVEDDEASSERTINTDLEGACYINT (OPEN_L0RECEIVEDDEASSERTINTDLEGACYINT), + .L0REPLAYTIMERADJUSTMENT (12'b0), + .L0ROOTTURNOFFREQ (1'b0), + .L0RXBEACON (OPEN_L0RXBEACON), + .L0RXDLLFCCMPLMCCRED (OPEN_L0RXDLLFCCMPLMCCRED), + .L0RXDLLFCCMPLMCUPDATE (OPEN_L0RXDLLFCCMPLMCUPDATE), + .L0RXDLLFCNPOSTBYPCRED (OPEN_L0RXDLLFCNPOSTBYPCRED), + .L0RXDLLFCNPOSTBYPUPDATE (OPEN_L0RXDLLFCNPOSTBYPUPDATE), + .L0RXDLLFCPOSTORDCRED (OPEN_L0RXDLLFCPOSTORDCRED), + .L0RXDLLFCPOSTORDUPDATE (OPEN_L0RXDLLFCPOSTORDUPDATE), + .L0RXDLLPM (L0RXDLLPM), + .L0RXDLLPMTYPE (L0RXDLLPMTYPE), + .L0RXDLLSBFCDATA (OPEN_L0RXDLLSBFCDATA), + .L0RXDLLSBFCUPDATE (OPEN_L0RXDLLSBFCUPDATE), + .L0RXDLLTLPECRCOK (OPEN_L0RXDLLTLPECRCOK), + .L0RXDLLTLPEND (OPEN_L0RXDLLTLPEND), + .L0RXMACLINKERROR (L0RXMACLINKERROR), + .L0RXTLTLPNONINITIALIZEDVC (8'b0), + .L0SENDUNLOCKMESSAGE (1'b0), + .L0SETCOMPLETERABORTERROR (L0SETCOMPLETERABORTERROR), + .L0SETCOMPLETIONTIMEOUTCORRERROR (L0SETCOMPLETIONTIMEOUTCORRERROR), + .L0SETCOMPLETIONTIMEOUTUNCORRERROR (L0SETCOMPLETIONTIMEOUTUNCORRERROR), + .L0SETDETECTEDCORRERROR (L0SETDETECTEDCORRERROR), + .L0SETDETECTEDFATALERROR (L0SETDETECTEDFATALERROR), + .L0SETDETECTEDNONFATALERROR (L0SETDETECTEDNONFATALERROR), + .L0SETLINKDETECTEDPARITYERROR (1'b0), + .L0SETLINKMASTERDATAPARITY (1'b0), + .L0SETLINKRECEIVEDMASTERABORT (1'b0), + .L0SETLINKRECEIVEDTARGETABORT (1'b0), + .L0SETLINKSIGNALLEDTARGETABORT (1'b0), + .L0SETLINKSYSTEMERROR (1'b0), + .L0SETUNEXPECTEDCOMPLETIONCORRERROR (L0SETUNEXPECTEDCOMPLETIONCORRERROR), + .L0SETUNEXPECTEDCOMPLETIONUNCORRERROR (L0SETUNEXPECTEDCOMPLETIONUNCORRERROR), + .L0SETUNSUPPORTEDREQUESTNONPOSTEDERROR (L0SETUNSUPPORTEDREQUESTNONPOSTEDERROR), + .L0SETUNSUPPORTEDREQUESTOTHERERROR (L0SETUNSUPPORTEDREQUESTOTHERERROR), + .L0SETUSERDETECTEDPARITYERROR (L0SETUSERDETECTEDPARITYERROR), + .L0SETUSERMASTERDATAPARITY (L0SETUSERMASTERDATAPARITY), + .L0SETUSERRECEIVEDMASTERABORT (L0SETUSERRECEIVEDMASTERABORT), + .L0SETUSERRECEIVEDTARGETABORT (L0SETUSERRECEIVEDTARGETABORT), + .L0SETUSERSIGNALLEDTARGETABORT (L0SETUSERSIGNALLEDTARGETABORT), + .L0SETUSERSYSTEMERROR (L0SETUSERSYSTEMERROR), + .L0STATSCFGOTHERRECEIVED (L0STATSCFGOTHERRECEIVED), + .L0STATSCFGOTHERTRANSMITTED (L0STATSCFGOTHERTRANSMITTED), + .L0STATSCFGRECEIVED (L0STATSCFGRECEIVED), + .L0STATSCFGTRANSMITTED (L0STATSCFGTRANSMITTED), + .L0STATSDLLPRECEIVED (L0STATSDLLPRECEIVED), + .L0STATSDLLPTRANSMITTED (L0STATSDLLPTRANSMITTED), + .L0STATSOSRECEIVED (L0STATSOSRECEIVED), + .L0STATSOSTRANSMITTED (L0STATSOSTRANSMITTED), + .L0STATSTLPRECEIVED (L0STATSTLPRECEIVED), + .L0STATSTLPTRANSMITTED (L0STATSTLPTRANSMITTED), + .L0TLASFCCREDSTARVATION (1'b0), + .L0TLLINKRETRAIN (1'b0), + .L0TOGGLEELECTROMECHANICALINTERLOCK (OPEN_L0TOGGLEELECTROMECHANICALINTERLOCK), + .L0TRANSACTIONSPENDING (L0TRANSACTIONSPENDING), + .L0TRANSFORMEDVC (OPEN_L0TRANSFORMEDVC), + .L0TXBEACON (1'b0), + .L0TXCFGPM (1'b0), + .L0TXCFGPMTYPE (3'b0), + .L0TXDLLFCCMPLMCUPDATED (OPEN_L0TXDLLFCCMPLMCUPDATED), + .L0TXDLLFCNPOSTBYPUPDATED (OPEN_L0TXDLLFCNPOSTBYPUPDATED), + .L0TXDLLFCPOSTORDUPDATED (OPEN_L0TXDLLFCPOSTORDUPDATED), + .L0TXDLLPMUPDATED (OPEN_L0TXDLLPMUPDATED), + .L0TXDLLSBFCUPDATED (OPEN_L0TXDLLSBFCUPDATED), + .L0TXTLFCCMPLMCCRED (160'b0), + .L0TXTLFCCMPLMCUPDATE (16'b0), + .L0TXTLFCNPOSTBYPCRED (192'b0), + .L0TXTLFCNPOSTBYPUPDATE (16'b0), + .L0TXTLFCPOSTORDCRED (160'b0), + .L0TXTLFCPOSTORDUPDATE (16'b0), + .L0TXTLSBFCDATA (19'b0), + .L0TXTLSBFCUPDATE (1'b0), + .L0TXTLTLPDATA (64'b0), + .L0TXTLTLPEDB (1'b0), + .L0TXTLTLPENABLE (2'b0), + .L0TXTLTLPEND (2'b0), + .L0TXTLTLPLATENCY (4'b0), + .L0TXTLTLPREQ (1'b0), + .L0TXTLTLPREQEND (1'b0), + .L0TXTLTLPWIDTH (1'b0), + .L0UCBYPFOUND (OPEN_L0UCBYPFOUND), + .L0UCORDFOUND (OPEN_L0UCORDFOUND), + .L0UNLOCKRECEIVED (L0UNLOCKRECEIVED), + .L0UPSTREAMRXPORTINL0S (1'b0), + .L0VC0PREVIEWEXPAND (1'b0), + .L0WAKEN (1'b1), + .LLKRX4DWHEADERN (OPEN_LLKRX4DWHEADERN), + .LLKRXCHCOMPLETIONAVAILABLEN (LLKRXCHCOMPLETIONAVAILABLEN), + .LLKRXCHCOMPLETIONPARTIALN (OPEN_LLKRXCHCOMPLETIONPARTIALN), + .LLKRXCHCONFIGAVAILABLEN (OPEN_LLKRXCHCONFIGAVAILABLEN), + .LLKRXCHCONFIGPARTIALN (OPEN_LLKRXCHCONFIGPARTIALN), + .LLKRXCHFIFO (LLKRXCHFIFO), + .LLKRXCHNONPOSTEDAVAILABLEN (LLKRXCHNONPOSTEDAVAILABLEN), + .LLKRXCHNONPOSTEDPARTIALN (OPEN_LLKRXCHNONPOSTEDPARTIALN), + .LLKRXCHPOSTEDAVAILABLEN (LLKRXCHPOSTEDAVAILABLEN), + .LLKRXCHPOSTEDPARTIALN (OPEN_LLKRXCHPOSTEDPARTIALN), + .LLKRXCHTC (LLKRXCHTC), + .LLKRXDATA (LLKRXDATA), + .LLKRXDSTCONTREQN (LLKRXDSTCONTREQN), + .LLKRXDSTREQN (LLKRXDSTREQN), + .LLKRXECRCBADN (OPEN_LLKRXECRCBADN), + .LLKRXEOFN (LLKRXEOFN), + .LLKRXEOPN (LLKRXEOPN), + .LLKRXPREFERREDTYPE (LLKRXPREFERREDTYPE), + .LLKRXSOFN (LLKRXSOFN), + .LLKRXSOPN (LLKRXSOPN), + .LLKRXSRCDSCN (OPEN_LLKRXSRCDSCN), + .LLKRXSRCLASTREQN (LLKRXSRCLASTREQN), + .LLKRXSRCRDYN (LLKRXSRCRDYN), + .LLKRXVALIDN (LLKRXVALIDN), + .LLKTCSTATUS (LLKTCSTATUS), + .LLKTX4DWHEADERN (1'b1), + .LLKTXCHANSPACE (LLKTXCHANSPACE), + .LLKTXCHCOMPLETIONREADYN (LLKTXCHCOMPLETIONREADYN), + .LLKTXCHFIFO (LLKTXCHFIFO), + .LLKTXCHNONPOSTEDREADYN (LLKTXCHNONPOSTEDREADYN), + .LLKTXCHPOSTEDREADYN (LLKTXCHPOSTEDREADYN), + .LLKTXCHTC (LLKTXCHTC), + .LLKTXCOMPLETEN (1'b1), + .LLKTXCONFIGREADYN (LLKTXCONFIGREADYN), + .LLKTXCREATEECRCN (1'b1), + .LLKTXDATA (LLKTXDATA), + .LLKTXDSTRDYN (LLKTXDSTRDYN), + .LLKTXENABLEN (LLKTXENABLEN), + .LLKTXEOFN (LLKTXEOFN), + .LLKTXEOPN (LLKTXEOPN), + .LLKTXSOFN (LLKTXSOFN), + .LLKTXSOPN (LLKTXSOPN), + .LLKTXSRCDSCN (LLKTXSRCDSCN), + .LLKTXSRCRDYN (LLKTXSRCRDYN), + .MAINPOWER (1'b1), + .MAXPAYLOADSIZE (MAXPAYLOADSIZE), + .MAXREADREQUESTSIZE (MAXREADREQUESTSIZE), + .MEMSPACEENABLE (MEMSPACEENABLE), + .MGMTADDR (MGMTADDR), + .MGMTBWREN (MGMTBWREN), + .MGMTPSO (MGMTPSO), + .MGMTRDATA (MGMTRDATA), + .MGMTRDEN (MGMTRDEN), + .MGMTSTATSCREDIT (MGMTSTATSCREDIT), + .MGMTSTATSCREDITSEL (MGMTSTATSCREDITSEL), + .MGMTWDATA (MGMTWDATA), + .MGMTWREN (MGMTWREN), + .MIMDLLBRADD (MIMDLLBRADD), + .MIMDLLBRDATA (MIMDLLBRDATA), + .MIMDLLBREN (MIMDLLBREN), + .MIMDLLBWADD (MIMDLLBWADD), + .MIMDLLBWDATA (MIMDLLBWDATA), + .MIMDLLBWEN (MIMDLLBWEN), + .MIMRXBRADD (MIMRXBRADD), + .MIMRXBRDATA (MIMRXBRDATA), + .MIMRXBREN (MIMRXBREN), + .MIMRXBWADD (MIMRXBWADD), + .MIMRXBWDATA (MIMRXBWDATA), + .MIMRXBWEN (MIMRXBWEN), + .MIMTXBRADD (MIMTXBRADD), + .MIMTXBRDATA (MIMTXBRDATA), + .MIMTXBREN (MIMTXBREN), + .MIMTXBWADD (MIMTXBWADD), + .MIMTXBWDATA (MIMTXBWDATA), + .MIMTXBWEN (MIMTXBWEN), + .PARITYERRORRESPONSE (PARITYERRORRESPONSE), + .PIPEDESKEWLANESL0 (PIPEDESKEWLANESL0), + .PIPEDESKEWLANESL1 (PIPEDESKEWLANESL1), + .PIPEDESKEWLANESL2 (PIPEDESKEWLANESL2), + .PIPEDESKEWLANESL3 (PIPEDESKEWLANESL3), + .PIPEDESKEWLANESL4 (PIPEDESKEWLANESL4), + .PIPEDESKEWLANESL5 (PIPEDESKEWLANESL5), + .PIPEDESKEWLANESL6 (PIPEDESKEWLANESL6), + .PIPEDESKEWLANESL7 (PIPEDESKEWLANESL7), + .PIPEPHYSTATUSL0 (PIPEPHYSTATUSL0), + .PIPEPHYSTATUSL1 (PIPEPHYSTATUSL1), + .PIPEPHYSTATUSL2 (PIPEPHYSTATUSL2), + .PIPEPHYSTATUSL3 (PIPEPHYSTATUSL3), + .PIPEPHYSTATUSL4 (PIPEPHYSTATUSL4), + .PIPEPHYSTATUSL5 (PIPEPHYSTATUSL5), + .PIPEPHYSTATUSL6 (PIPEPHYSTATUSL6), + .PIPEPHYSTATUSL7 (PIPEPHYSTATUSL7), + .PIPEPOWERDOWNL0 (PIPEPOWERDOWNL0), + .PIPEPOWERDOWNL1 (PIPEPOWERDOWNL1), + .PIPEPOWERDOWNL2 (PIPEPOWERDOWNL2), + .PIPEPOWERDOWNL3 (PIPEPOWERDOWNL3), + .PIPEPOWERDOWNL4 (PIPEPOWERDOWNL4), + .PIPEPOWERDOWNL5 (PIPEPOWERDOWNL5), + .PIPEPOWERDOWNL6 (PIPEPOWERDOWNL6), + .PIPEPOWERDOWNL7 (PIPEPOWERDOWNL7), + .PIPERESETL0 (PIPERESETL0), + .PIPERESETL1 (PIPERESETL1), + .PIPERESETL2 (PIPERESETL2), + .PIPERESETL3 (PIPERESETL3), + .PIPERESETL4 (PIPERESETL4), + .PIPERESETL5 (PIPERESETL5), + .PIPERESETL6 (PIPERESETL6), + .PIPERESETL7 (PIPERESETL7), + .PIPERXCHANISALIGNEDL0 (PIPERXCHANISALIGNEDL0), + .PIPERXCHANISALIGNEDL1 (PIPERXCHANISALIGNEDL1), + .PIPERXCHANISALIGNEDL2 (PIPERXCHANISALIGNEDL2), + .PIPERXCHANISALIGNEDL3 (PIPERXCHANISALIGNEDL3), + .PIPERXCHANISALIGNEDL4 (PIPERXCHANISALIGNEDL4), + .PIPERXCHANISALIGNEDL5 (PIPERXCHANISALIGNEDL5), + .PIPERXCHANISALIGNEDL6 (PIPERXCHANISALIGNEDL6), + .PIPERXCHANISALIGNEDL7 (PIPERXCHANISALIGNEDL7), + .PIPERXDATAKL0 (PIPERXDATAKL0), + .PIPERXDATAKL1 (PIPERXDATAKL1), + .PIPERXDATAKL2 (PIPERXDATAKL2), + .PIPERXDATAKL3 (PIPERXDATAKL3), + .PIPERXDATAKL4 (PIPERXDATAKL4), + .PIPERXDATAKL5 (PIPERXDATAKL5), + .PIPERXDATAKL6 (PIPERXDATAKL6), + .PIPERXDATAKL7 (PIPERXDATAKL7), + .PIPERXDATAL0 (PIPERXDATAL0), + .PIPERXDATAL1 (PIPERXDATAL1), + .PIPERXDATAL2 (PIPERXDATAL2), + .PIPERXDATAL3 (PIPERXDATAL3), + .PIPERXDATAL4 (PIPERXDATAL4), + .PIPERXDATAL5 (PIPERXDATAL5), + .PIPERXDATAL6 (PIPERXDATAL6), + .PIPERXDATAL7 (PIPERXDATAL7), + .PIPERXELECIDLEL0 (PIPERXELECIDLEL0), + .PIPERXELECIDLEL1 (PIPERXELECIDLEL1), + .PIPERXELECIDLEL2 (PIPERXELECIDLEL2), + .PIPERXELECIDLEL3 (PIPERXELECIDLEL3), + .PIPERXELECIDLEL4 (PIPERXELECIDLEL4), + .PIPERXELECIDLEL5 (PIPERXELECIDLEL5), + .PIPERXELECIDLEL6 (PIPERXELECIDLEL6), + .PIPERXELECIDLEL7 (PIPERXELECIDLEL7), + .PIPERXPOLARITYL0 (PIPERXPOLARITYL0), + .PIPERXPOLARITYL1 (PIPERXPOLARITYL1), + .PIPERXPOLARITYL2 (PIPERXPOLARITYL2), + .PIPERXPOLARITYL3 (PIPERXPOLARITYL3), + .PIPERXPOLARITYL4 (PIPERXPOLARITYL4), + .PIPERXPOLARITYL5 (PIPERXPOLARITYL5), + .PIPERXPOLARITYL6 (PIPERXPOLARITYL6), + .PIPERXPOLARITYL7 (PIPERXPOLARITYL7), + .PIPERXSTATUSL0 (PIPERXSTATUSL0), + .PIPERXSTATUSL1 (PIPERXSTATUSL1), + .PIPERXSTATUSL2 (PIPERXSTATUSL2), + .PIPERXSTATUSL3 (PIPERXSTATUSL3), + .PIPERXSTATUSL4 (PIPERXSTATUSL4), + .PIPERXSTATUSL5 (PIPERXSTATUSL5), + .PIPERXSTATUSL6 (PIPERXSTATUSL6), + .PIPERXSTATUSL7 (PIPERXSTATUSL7), + .PIPERXVALIDL0 (PIPERXVALIDL0), + .PIPERXVALIDL1 (PIPERXVALIDL1), + .PIPERXVALIDL2 (PIPERXVALIDL2), + .PIPERXVALIDL3 (PIPERXVALIDL3), + .PIPERXVALIDL4 (PIPERXVALIDL4), + .PIPERXVALIDL5 (PIPERXVALIDL5), + .PIPERXVALIDL6 (PIPERXVALIDL6), + .PIPERXVALIDL7 (PIPERXVALIDL7), + .PIPETXCOMPLIANCEL0 (PIPETXCOMPLIANCEL0), + .PIPETXCOMPLIANCEL1 (PIPETXCOMPLIANCEL1), + .PIPETXCOMPLIANCEL2 (PIPETXCOMPLIANCEL2), + .PIPETXCOMPLIANCEL3 (PIPETXCOMPLIANCEL3), + .PIPETXCOMPLIANCEL4 (PIPETXCOMPLIANCEL4), + .PIPETXCOMPLIANCEL5 (PIPETXCOMPLIANCEL5), + .PIPETXCOMPLIANCEL6 (PIPETXCOMPLIANCEL6), + .PIPETXCOMPLIANCEL7 (PIPETXCOMPLIANCEL7), + .PIPETXDATAKL0 (PIPETXDATAKL0), + .PIPETXDATAKL1 (PIPETXDATAKL1), + .PIPETXDATAKL2 (PIPETXDATAKL2), + .PIPETXDATAKL3 (PIPETXDATAKL3), + .PIPETXDATAKL4 (PIPETXDATAKL4), + .PIPETXDATAKL5 (PIPETXDATAKL5), + .PIPETXDATAKL6 (PIPETXDATAKL6), + .PIPETXDATAKL7 (PIPETXDATAKL7), + .PIPETXDATAL0 (PIPETXDATAL0), + .PIPETXDATAL1 (PIPETXDATAL1), + .PIPETXDATAL2 (PIPETXDATAL2), + .PIPETXDATAL3 (PIPETXDATAL3), + .PIPETXDATAL4 (PIPETXDATAL4), + .PIPETXDATAL5 (PIPETXDATAL5), + .PIPETXDATAL6 (PIPETXDATAL6), + .PIPETXDATAL7 (PIPETXDATAL7), + .PIPETXDETECTRXLOOPBACKL0 (PIPETXDETECTRXLOOPBACKL0), + .PIPETXDETECTRXLOOPBACKL1 (PIPETXDETECTRXLOOPBACKL1), + .PIPETXDETECTRXLOOPBACKL2 (PIPETXDETECTRXLOOPBACKL2), + .PIPETXDETECTRXLOOPBACKL3 (PIPETXDETECTRXLOOPBACKL3), + .PIPETXDETECTRXLOOPBACKL4 (PIPETXDETECTRXLOOPBACKL4), + .PIPETXDETECTRXLOOPBACKL5 (PIPETXDETECTRXLOOPBACKL5), + .PIPETXDETECTRXLOOPBACKL6 (PIPETXDETECTRXLOOPBACKL6), + .PIPETXDETECTRXLOOPBACKL7 (PIPETXDETECTRXLOOPBACKL7), + .PIPETXELECIDLEL0 (PIPETXELECIDLEL0), + .PIPETXELECIDLEL1 (PIPETXELECIDLEL1), + .PIPETXELECIDLEL2 (PIPETXELECIDLEL2), + .PIPETXELECIDLEL3 (PIPETXELECIDLEL3), + .PIPETXELECIDLEL4 (PIPETXELECIDLEL4), + .PIPETXELECIDLEL5 (PIPETXELECIDLEL5), + .PIPETXELECIDLEL6 (PIPETXELECIDLEL6), + .PIPETXELECIDLEL7 (PIPETXELECIDLEL7), + .SERRENABLE (SERRENABLE), + .URREPORTINGENABLE (URREPORTINGENABLE) +); + +defparam pcie_internal_1_1_1.ACTIVELANESIN = ACTIVELANESIN; +defparam pcie_internal_1_1_1.AERBASEPTR = AERBASEPTR; +defparam pcie_internal_1_1_1.AERCAPABILITYECRCCHECKCAPABLE = "FALSE"; +defparam pcie_internal_1_1_1.AERCAPABILITYECRCGENCAPABLE = "FALSE"; +defparam pcie_internal_1_1_1.AERCAPABILITYNEXTPTR = AERCAPABILITYNEXTPTR; +defparam pcie_internal_1_1_1.BAR0ADDRWIDTH = BAR0ADDRWIDTH; +defparam pcie_internal_1_1_1.BAR0EXIST = BAR0EXIST; +defparam pcie_internal_1_1_1.BAR0IOMEMN = BAR0IOMEMN; +defparam pcie_internal_1_1_1.BAR0MASKWIDTH = BAR0MASKWIDTH; +defparam pcie_internal_1_1_1.BAR0PREFETCHABLE = BAR0PREFETCHABLE; +defparam pcie_internal_1_1_1.BAR1ADDRWIDTH = BAR1ADDRWIDTH; +defparam pcie_internal_1_1_1.BAR1EXIST = BAR1EXIST; +defparam pcie_internal_1_1_1.BAR1IOMEMN = BAR1IOMEMN; +defparam pcie_internal_1_1_1.BAR1MASKWIDTH = BAR1MASKWIDTH; +defparam pcie_internal_1_1_1.BAR1PREFETCHABLE = BAR1PREFETCHABLE; +defparam pcie_internal_1_1_1.BAR2ADDRWIDTH = BAR2ADDRWIDTH; +defparam pcie_internal_1_1_1.BAR2EXIST = BAR2EXIST; +defparam pcie_internal_1_1_1.BAR2IOMEMN = BAR2IOMEMN; +defparam pcie_internal_1_1_1.BAR2MASKWIDTH = BAR2MASKWIDTH; +defparam pcie_internal_1_1_1.BAR2PREFETCHABLE = BAR2PREFETCHABLE; +defparam pcie_internal_1_1_1.BAR3ADDRWIDTH = BAR3ADDRWIDTH; +defparam pcie_internal_1_1_1.BAR3EXIST = BAR3EXIST; +defparam pcie_internal_1_1_1.BAR3IOMEMN = BAR3IOMEMN; +defparam pcie_internal_1_1_1.BAR3MASKWIDTH = BAR3MASKWIDTH; +defparam pcie_internal_1_1_1.BAR3PREFETCHABLE = BAR3PREFETCHABLE; +defparam pcie_internal_1_1_1.BAR4ADDRWIDTH = BAR4ADDRWIDTH; +defparam pcie_internal_1_1_1.BAR4EXIST = BAR4EXIST; +defparam pcie_internal_1_1_1.BAR4IOMEMN = BAR4IOMEMN; +defparam pcie_internal_1_1_1.BAR4MASKWIDTH = BAR4MASKWIDTH; +defparam pcie_internal_1_1_1.BAR4PREFETCHABLE = BAR4PREFETCHABLE; +//defparam pcie_internal_1_1_1.BAR5ADDRWIDTH = 0; +defparam pcie_internal_1_1_1.BAR5EXIST = BAR5EXIST; +defparam pcie_internal_1_1_1.BAR5IOMEMN = BAR5IOMEMN; +defparam pcie_internal_1_1_1.BAR5MASKWIDTH = BAR5MASKWIDTH; +defparam pcie_internal_1_1_1.BAR5PREFETCHABLE = BAR5PREFETCHABLE; +defparam pcie_internal_1_1_1.CAPABILITIESPOINTER = CAPABILITIESPOINTER; +defparam pcie_internal_1_1_1.CARDBUSCISPOINTER = CARDBUSCISPOINTER; +defparam pcie_internal_1_1_1.CLASSCODE = CLASSCODE; +defparam pcie_internal_1_1_1.CLKDIVIDED = CLKDIVIDED; +defparam pcie_internal_1_1_1.CONFIGROUTING = 3'h1; +defparam pcie_internal_1_1_1.DEVICECAPABILITYENDPOINTL0SLATENCY = DEVICECAPABILITYENDPOINTL0SLATENCY; +defparam pcie_internal_1_1_1.DEVICECAPABILITYENDPOINTL1LATENCY = DEVICECAPABILITYENDPOINTL1LATENCY; +defparam pcie_internal_1_1_1.DEVICEID = DEVICEID; +defparam pcie_internal_1_1_1.DEVICESERIALNUMBER = DEVICESERIALNUMBER; +defparam pcie_internal_1_1_1.DSNBASEPTR = DSNBASEPTR; +defparam pcie_internal_1_1_1.DSNCAPABILITYNEXTPTR = DSNCAPABILITYNEXTPTR; +defparam pcie_internal_1_1_1.DUALCOREENABLE = "FALSE"; +defparam pcie_internal_1_1_1.DUALCORESLAVE = "FALSE"; +defparam pcie_internal_1_1_1.DUALROLECFGCNTRLROOTEPN = 0; +defparam pcie_internal_1_1_1.EXTCFGCAPPTR = 8'h0; +defparam pcie_internal_1_1_1.EXTCFGXPCAPPTR = 12'h0; +defparam pcie_internal_1_1_1.HEADERTYPE = 8'h0; +defparam pcie_internal_1_1_1.INFINITECOMPLETIONS = INFINITECOMPLETIONS; +defparam pcie_internal_1_1_1.INTERRUPTPIN = INTERRUPTPIN; +defparam pcie_internal_1_1_1.ISSWITCH = "FALSE"; +defparam pcie_internal_1_1_1.L0SEXITLATENCY = L0SEXITLATENCY; +defparam pcie_internal_1_1_1.L0SEXITLATENCYCOMCLK = L0SEXITLATENCYCOMCLK; +defparam pcie_internal_1_1_1.L1EXITLATENCY = L1EXITLATENCY; +defparam pcie_internal_1_1_1.L1EXITLATENCYCOMCLK = L1EXITLATENCYCOMCLK; +defparam pcie_internal_1_1_1.LINKCAPABILITYASPMSUPPORT = LINKCAPABILITYASPMSUPPORT; +defparam pcie_internal_1_1_1.LINKCAPABILITYMAXLINKWIDTH = LINKCAPABILITYMAXLINKWIDTH; +defparam pcie_internal_1_1_1.LINKSTATUSSLOTCLOCKCONFIG = LINKSTATUSSLOTCLOCKCONFIG; +defparam pcie_internal_1_1_1.LLKBYPASS = "FALSE"; +defparam pcie_internal_1_1_1.LOWPRIORITYVCCOUNT = LOWPRIORITYVCCOUNT; +defparam pcie_internal_1_1_1.MSIBASEPTR = MSIBASEPTR; +defparam pcie_internal_1_1_1.MSICAPABILITYMULTIMSGCAP = MSICAPABILITYMULTIMSGCAP; +defparam pcie_internal_1_1_1.MSICAPABILITYNEXTPTR = MSICAPABILITYNEXTPTR; +defparam pcie_internal_1_1_1.PBBASEPTR = PBBASEPTR; +defparam pcie_internal_1_1_1.PBCAPABILITYDW0BASEPOWER = PBCAPABILITYDW0BASEPOWER; +defparam pcie_internal_1_1_1.PBCAPABILITYDW0DATASCALE = PBCAPABILITYDW0DATASCALE; +defparam pcie_internal_1_1_1.PBCAPABILITYDW0PMSTATE = PBCAPABILITYDW0PMSTATE; +defparam pcie_internal_1_1_1.PBCAPABILITYDW0PMSUBSTATE = PBCAPABILITYDW0PMSUBSTATE; +defparam pcie_internal_1_1_1.PBCAPABILITYDW0POWERRAIL = PBCAPABILITYDW0POWERRAIL; +defparam pcie_internal_1_1_1.PBCAPABILITYDW0TYPE = PBCAPABILITYDW0TYPE; +defparam pcie_internal_1_1_1.PBCAPABILITYDW1BASEPOWER = PBCAPABILITYDW1BASEPOWER; +defparam pcie_internal_1_1_1.PBCAPABILITYDW1DATASCALE = PBCAPABILITYDW1DATASCALE; +defparam pcie_internal_1_1_1.PBCAPABILITYDW1PMSTATE = PBCAPABILITYDW1PMSTATE; +defparam pcie_internal_1_1_1.PBCAPABILITYDW1PMSUBSTATE = PBCAPABILITYDW1PMSUBSTATE; +defparam pcie_internal_1_1_1.PBCAPABILITYDW1POWERRAIL = PBCAPABILITYDW1POWERRAIL; +defparam pcie_internal_1_1_1.PBCAPABILITYDW1TYPE = PBCAPABILITYDW1TYPE; +defparam pcie_internal_1_1_1.PBCAPABILITYDW2BASEPOWER = PBCAPABILITYDW2BASEPOWER; +defparam pcie_internal_1_1_1.PBCAPABILITYDW2DATASCALE = PBCAPABILITYDW2DATASCALE; +defparam pcie_internal_1_1_1.PBCAPABILITYDW2PMSTATE = PBCAPABILITYDW2PMSTATE; +defparam pcie_internal_1_1_1.PBCAPABILITYDW2PMSUBSTATE = PBCAPABILITYDW2PMSUBSTATE; +defparam pcie_internal_1_1_1.PBCAPABILITYDW2POWERRAIL = PBCAPABILITYDW2POWERRAIL; +defparam pcie_internal_1_1_1.PBCAPABILITYDW2TYPE = PBCAPABILITYDW2TYPE; +defparam pcie_internal_1_1_1.PBCAPABILITYDW3BASEPOWER = PBCAPABILITYDW3BASEPOWER; +defparam pcie_internal_1_1_1.PBCAPABILITYDW3DATASCALE = PBCAPABILITYDW3DATASCALE; +defparam pcie_internal_1_1_1.PBCAPABILITYDW3PMSTATE = PBCAPABILITYDW3PMSTATE; +defparam pcie_internal_1_1_1.PBCAPABILITYDW3PMSUBSTATE = PBCAPABILITYDW3PMSUBSTATE; +defparam pcie_internal_1_1_1.PBCAPABILITYDW3POWERRAIL = PBCAPABILITYDW3POWERRAIL; +defparam pcie_internal_1_1_1.PBCAPABILITYDW3TYPE = PBCAPABILITYDW3TYPE; +defparam pcie_internal_1_1_1.PBCAPABILITYNEXTPTR = PBCAPABILITYNEXTPTR; +defparam pcie_internal_1_1_1.PBCAPABILITYSYSTEMALLOCATED = PBCAPABILITYSYSTEMALLOCATED; +defparam pcie_internal_1_1_1.PCIECAPABILITYINTMSGNUM = 5'h0; +defparam pcie_internal_1_1_1.PCIECAPABILITYNEXTPTR = PCIECAPABILITYNEXTPTR; +defparam pcie_internal_1_1_1.PCIECAPABILITYSLOTIMPL = "FALSE"; +defparam pcie_internal_1_1_1.PCIEREVISION = 1; +defparam pcie_internal_1_1_1.PMBASEPTR = PMBASEPTR; +defparam pcie_internal_1_1_1.PMCAPABILITYAUXCURRENT = PMCAPABILITYAUXCURRENT; +defparam pcie_internal_1_1_1.PMCAPABILITYD1SUPPORT = PMCAPABILITYD1SUPPORT; +defparam pcie_internal_1_1_1.PMCAPABILITYD2SUPPORT = PMCAPABILITYD2SUPPORT; +defparam pcie_internal_1_1_1.PMCAPABILITYDSI = PMCAPABILITYDSI; +defparam pcie_internal_1_1_1.PMCAPABILITYNEXTPTR = PMCAPABILITYNEXTPTR; +defparam pcie_internal_1_1_1.PMCAPABILITYPMESUPPORT = PMCAPABILITYPMESUPPORT; +defparam pcie_internal_1_1_1.PMDATA0 = PMDATA0; +defparam pcie_internal_1_1_1.PMDATA1 = PMDATA1; +defparam pcie_internal_1_1_1.PMDATA2 = PMDATA2; +defparam pcie_internal_1_1_1.PMDATA3 = PMDATA3; +defparam pcie_internal_1_1_1.PMDATA4 = PMDATA4; +defparam pcie_internal_1_1_1.PMDATA5 = PMDATA5; +defparam pcie_internal_1_1_1.PMDATA6 = PMDATA6; +defparam pcie_internal_1_1_1.PMDATA7 = PMDATA7; +defparam pcie_internal_1_1_1.PMDATA8 = 8'h0; +defparam pcie_internal_1_1_1.PMDATASCALE0 = PMDATASCALE0; +defparam pcie_internal_1_1_1.PMDATASCALE1 = PMDATASCALE1; +defparam pcie_internal_1_1_1.PMDATASCALE2 = PMDATASCALE2; +defparam pcie_internal_1_1_1.PMDATASCALE3 = PMDATASCALE3; +defparam pcie_internal_1_1_1.PMDATASCALE4 = PMDATASCALE4; +defparam pcie_internal_1_1_1.PMDATASCALE5 = PMDATASCALE5; +defparam pcie_internal_1_1_1.PMDATASCALE6 = PMDATASCALE6; +defparam pcie_internal_1_1_1.PMDATASCALE7 = PMDATASCALE7; +defparam pcie_internal_1_1_1.PMDATASCALE8 = 0; +defparam pcie_internal_1_1_1.PMSTATUSCONTROLDATASCALE = 2'h0; +defparam pcie_internal_1_1_1.PORTVCCAPABILITYEXTENDEDVCCOUNT = PORTVCCAPABILITYEXTENDEDVCCOUNT; +defparam pcie_internal_1_1_1.PORTVCCAPABILITYVCARBCAP = PORTVCCAPABILITYVCARBCAP; +defparam pcie_internal_1_1_1.PORTVCCAPABILITYVCARBTABLEOFFSET = PORTVCCAPABILITYVCARBTABLEOFFSET; +defparam pcie_internal_1_1_1.RAMSHARETXRX = "FALSE"; +defparam pcie_internal_1_1_1.RESETMODE = RESETMODE; +defparam pcie_internal_1_1_1.RETRYRAMREADLATENCY = RETRYRAMREADLATENCY; +defparam pcie_internal_1_1_1.RETRYRAMSIZE = RETRYRAMSIZE; +defparam pcie_internal_1_1_1.RETRYRAMWIDTH = 0; +defparam pcie_internal_1_1_1.RETRYRAMWRITELATENCY = RETRYRAMWRITELATENCY; +defparam pcie_internal_1_1_1.RETRYREADADDRPIPE = "FALSE"; +defparam pcie_internal_1_1_1.RETRYREADDATAPIPE = "FALSE"; +defparam pcie_internal_1_1_1.RETRYWRITEPIPE = "FALSE"; +defparam pcie_internal_1_1_1.REVISIONID = REVISIONID; +defparam pcie_internal_1_1_1.RXREADADDRPIPE = "FALSE"; +defparam pcie_internal_1_1_1.RXREADDATAPIPE = "FALSE"; +defparam pcie_internal_1_1_1.RXWRITEPIPE = "FALSE"; +defparam pcie_internal_1_1_1.SELECTASMODE = "FALSE"; +defparam pcie_internal_1_1_1.SELECTDLLIF = "FALSE"; +defparam pcie_internal_1_1_1.SLOTCAPABILITYATTBUTTONPRESENT = "FALSE"; +defparam pcie_internal_1_1_1.SLOTCAPABILITYATTINDICATORPRESENT = "FALSE"; +defparam pcie_internal_1_1_1.SLOTCAPABILITYHOTPLUGCAPABLE = "FALSE"; +defparam pcie_internal_1_1_1.SLOTCAPABILITYHOTPLUGSURPRISE = "FALSE"; +defparam pcie_internal_1_1_1.SLOTCAPABILITYMSLSENSORPRESENT = "FALSE"; +defparam pcie_internal_1_1_1.SLOTCAPABILITYPHYSICALSLOTNUM = 13'h0; +defparam pcie_internal_1_1_1.SLOTCAPABILITYPOWERCONTROLLERPRESENT = "FALSE"; +defparam pcie_internal_1_1_1.SLOTCAPABILITYPOWERINDICATORPRESENT = "FALSE"; +defparam pcie_internal_1_1_1.SLOTCAPABILITYSLOTPOWERLIMITSCALE = 2'h0; +defparam pcie_internal_1_1_1.SLOTCAPABILITYSLOTPOWERLIMITVALUE = 8'h0; +defparam pcie_internal_1_1_1.SLOTIMPLEMENTED = "FALSE"; +defparam pcie_internal_1_1_1.SUBSYSTEMID = SUBSYSTEMID; +defparam pcie_internal_1_1_1.SUBSYSTEMVENDORID = SUBSYSTEMVENDORID; +defparam pcie_internal_1_1_1.TLRAMREADLATENCY = TLRAMREADLATENCY; +defparam pcie_internal_1_1_1.TLRAMWIDTH = 0; +defparam pcie_internal_1_1_1.TLRAMWRITELATENCY = TLRAMWRITELATENCY; +defparam pcie_internal_1_1_1.TXREADADDRPIPE = "FALSE"; +defparam pcie_internal_1_1_1.TXREADDATAPIPE = "FALSE"; +defparam pcie_internal_1_1_1.TXTSNFTS = TXTSNFTS; +defparam pcie_internal_1_1_1.TXTSNFTSCOMCLK = TXTSNFTSCOMCLK; +defparam pcie_internal_1_1_1.TXWRITEPIPE = "FALSE"; +defparam pcie_internal_1_1_1.UPSTREAMFACING = "TRUE"; +defparam pcie_internal_1_1_1.VC0RXFIFOBASEC = VC0RXFIFOBASEC; +defparam pcie_internal_1_1_1.VC0RXFIFOBASENP = VC0RXFIFOBASENP; +defparam pcie_internal_1_1_1.VC0RXFIFOBASEP = VC0RXFIFOBASEP; +defparam pcie_internal_1_1_1.VC0RXFIFOLIMITC = VC0RXFIFOLIMITC; +defparam pcie_internal_1_1_1.VC0RXFIFOLIMITNP = VC0RXFIFOLIMITNP; +defparam pcie_internal_1_1_1.VC0RXFIFOLIMITP = VC0RXFIFOLIMITP; +defparam pcie_internal_1_1_1.VC0TOTALCREDITSCD = VC0TOTALCREDITSCD; +defparam pcie_internal_1_1_1.VC0TOTALCREDITSCH = VC0TOTALCREDITSCH; +defparam pcie_internal_1_1_1.VC0TOTALCREDITSNPH = VC0TOTALCREDITSNPH; +defparam pcie_internal_1_1_1.VC0TOTALCREDITSPD = VC0TOTALCREDITSPD; +defparam pcie_internal_1_1_1.VC0TOTALCREDITSPH = VC0TOTALCREDITSPH; +defparam pcie_internal_1_1_1.VC0TXFIFOBASEC = VC0TXFIFOBASEC; +defparam pcie_internal_1_1_1.VC0TXFIFOBASENP = VC0TXFIFOBASENP; +defparam pcie_internal_1_1_1.VC0TXFIFOBASEP = VC0TXFIFOBASEP; +defparam pcie_internal_1_1_1.VC0TXFIFOLIMITC = VC0TXFIFOLIMITC; +defparam pcie_internal_1_1_1.VC0TXFIFOLIMITNP = VC0TXFIFOLIMITNP; +defparam pcie_internal_1_1_1.VC0TXFIFOLIMITP = VC0TXFIFOLIMITP; +defparam pcie_internal_1_1_1.VC1RXFIFOBASEC = VC1RXFIFOBASEC; +defparam pcie_internal_1_1_1.VC1RXFIFOBASENP = VC1RXFIFOBASENP; +defparam pcie_internal_1_1_1.VC1RXFIFOBASEP = VC1RXFIFOBASEP; +defparam pcie_internal_1_1_1.VC1RXFIFOLIMITC = VC1RXFIFOLIMITC; +defparam pcie_internal_1_1_1.VC1RXFIFOLIMITNP = VC1RXFIFOLIMITNP; +defparam pcie_internal_1_1_1.VC1RXFIFOLIMITP = VC1RXFIFOLIMITP; +defparam pcie_internal_1_1_1.VC1TOTALCREDITSCD = VC1TOTALCREDITSCD; +defparam pcie_internal_1_1_1.VC1TOTALCREDITSCH = VC1TOTALCREDITSCH; +defparam pcie_internal_1_1_1.VC1TOTALCREDITSNPH = VC1TOTALCREDITSNPH; +defparam pcie_internal_1_1_1.VC1TOTALCREDITSPD = VC1TOTALCREDITSPD; +defparam pcie_internal_1_1_1.VC1TOTALCREDITSPH = VC1TOTALCREDITSPH; +defparam pcie_internal_1_1_1.VC1TXFIFOBASEC = VC1TXFIFOBASEC; +defparam pcie_internal_1_1_1.VC1TXFIFOBASENP = VC1TXFIFOBASENP; +defparam pcie_internal_1_1_1.VC1TXFIFOBASEP = VC1TXFIFOBASEP; +defparam pcie_internal_1_1_1.VC1TXFIFOLIMITC = VC1TXFIFOLIMITC; +defparam pcie_internal_1_1_1.VC1TXFIFOLIMITNP = VC1TXFIFOLIMITNP; +defparam pcie_internal_1_1_1.VC1TXFIFOLIMITP = VC1TXFIFOLIMITP; +defparam pcie_internal_1_1_1.VCBASEPTR = VCBASEPTR; +defparam pcie_internal_1_1_1.VCCAPABILITYNEXTPTR = VCCAPABILITYNEXTPTR; +defparam pcie_internal_1_1_1.VENDORID = VENDORID; +defparam pcie_internal_1_1_1.XLINKSUPPORTED = "FALSE"; +defparam pcie_internal_1_1_1.XPBASEPTR = XPBASEPTR; +defparam pcie_internal_1_1_1.XPDEVICEPORTTYPE = XPDEVICEPORTTYPE; +defparam pcie_internal_1_1_1.XPMAXPAYLOAD = XPMAXPAYLOAD; +defparam pcie_internal_1_1_1.XPRCBCONTROL = 0; + +endmodule diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/PCIE_INTERNAL_1_1.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/PCIE_INTERNAL_1_1.v new file mode 100644 index 0000000..42730b8 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/PCIE_INTERNAL_1_1.v @@ -0,0 +1,4285 @@ +/////////////////////////////////////////////////////////// +// Copyright (c) 1995/2006 Xilinx Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////// +// +// ____ ___ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / PCI Express +// /__/ /\ Filename : PCIE_INTERNAL_1_1.v +// \ \ / \ Timestamp : Thu Dec 8 2005 +// \__\/\__ \ +// +// Revision: +// 12/08/05 - Initial version. +// 01/09/06 - Added case statement, specify block +// 01/23/06 - Parameter MC updates CR#224562 +// 02/23/06 - CR#226003 - Added integer, real parameter type +// 04/24/06 - CR#230393 - Updated parameters, timing according to the spreadsheets +// - Updated Header +// 04/28/06 - CR#230712 - Spreadsheet update +// 05/23/06 - CR#231962 - Add buffers for connectivity +// 06/22/06 - CR#233879 - Add parameter bus range +// 08/02/06 - CR#235013 - Missing GSR added in SWIFT instantiation +// 08/14/06 - CR#421379 - PCIE updated to PCIE_INTERNAL_1_1 +// - spreadsheet updates for parameter default values +// 10/26/06 - - replaced zero_delay with CLK_DELAY to be consistent with writers (PPC440 update) +// - in_delay 50 to 0 +// End Revision +/////////////////////////////////////////////////////////// + +`timescale 1 ps / 1 ps + +module PCIE_INTERNAL_1_1 ( + BUSMASTERENABLE, + CRMDOHOTRESETN, + CRMPWRSOFTRESETN, + CRMRXHOTRESETN, + DLLTXPMDLLPOUTSTANDING, + INTERRUPTDISABLE, + IOSPACEENABLE, + L0ASAUTONOMOUSINITCOMPLETED, + L0ATTENTIONINDICATORCONTROL, + L0CFGLOOPBACKACK, + L0COMPLETERID, + L0CORRERRMSGRCVD, + L0DLLASRXSTATE, + L0DLLASTXSTATE, + L0DLLERRORVECTOR, + L0DLLRXACKOUTSTANDING, + L0DLLTXNONFCOUTSTANDING, + L0DLLTXOUTSTANDING, + L0DLLVCSTATUS, + L0DLUPDOWN, + L0ERRMSGREQID, + L0FATALERRMSGRCVD, + L0FIRSTCFGWRITEOCCURRED, + L0FWDCORRERROUT, + L0FWDFATALERROUT, + L0FWDNONFATALERROUT, + L0LTSSMSTATE, + L0MACENTEREDL0, + L0MACLINKTRAINING, + L0MACLINKUP, + L0MACNEGOTIATEDLINKWIDTH, + L0MACNEWSTATEACK, + L0MACRXL0SSTATE, + L0MACUPSTREAMDOWNSTREAM, + L0MCFOUND, + L0MSIENABLE0, + L0MULTIMSGEN0, + L0NONFATALERRMSGRCVD, + L0PMEACK, + L0PMEEN, + L0PMEREQOUT, + L0POWERCONTROLLERCONTROL, + L0POWERINDICATORCONTROL, + L0PWRINHIBITTRANSFERS, + L0PWRL1STATE, + L0PWRL23READYDEVICE, + L0PWRL23READYSTATE, + L0PWRSTATE0, + L0PWRTURNOFFREQ, + L0PWRTXL0SSTATE, + L0RECEIVEDASSERTINTALEGACYINT, + L0RECEIVEDASSERTINTBLEGACYINT, + L0RECEIVEDASSERTINTCLEGACYINT, + L0RECEIVEDASSERTINTDLEGACYINT, + L0RECEIVEDDEASSERTINTALEGACYINT, + L0RECEIVEDDEASSERTINTBLEGACYINT, + L0RECEIVEDDEASSERTINTCLEGACYINT, + L0RECEIVEDDEASSERTINTDLEGACYINT, + L0RXBEACON, + L0RXDLLFCCMPLMCCRED, + L0RXDLLFCCMPLMCUPDATE, + L0RXDLLFCNPOSTBYPCRED, + L0RXDLLFCNPOSTBYPUPDATE, + L0RXDLLFCPOSTORDCRED, + L0RXDLLFCPOSTORDUPDATE, + L0RXDLLPM, + L0RXDLLPMTYPE, + L0RXDLLSBFCDATA, + L0RXDLLSBFCUPDATE, + L0RXDLLTLPECRCOK, + L0RXDLLTLPEND, + L0RXMACLINKERROR, + L0STATSCFGOTHERRECEIVED, + L0STATSCFGOTHERTRANSMITTED, + L0STATSCFGRECEIVED, + L0STATSCFGTRANSMITTED, + L0STATSDLLPRECEIVED, + L0STATSDLLPTRANSMITTED, + L0STATSOSRECEIVED, + L0STATSOSTRANSMITTED, + L0STATSTLPRECEIVED, + L0STATSTLPTRANSMITTED, + L0TOGGLEELECTROMECHANICALINTERLOCK, + L0TRANSFORMEDVC, + L0TXDLLFCCMPLMCUPDATED, + L0TXDLLFCNPOSTBYPUPDATED, + L0TXDLLFCPOSTORDUPDATED, + L0TXDLLPMUPDATED, + L0TXDLLSBFCUPDATED, + L0UCBYPFOUND, + L0UCORDFOUND, + L0UNLOCKRECEIVED, + LLKRX4DWHEADERN, + LLKRXCHCOMPLETIONAVAILABLEN, + LLKRXCHCOMPLETIONPARTIALN, + LLKRXCHCONFIGAVAILABLEN, + LLKRXCHCONFIGPARTIALN, + LLKRXCHNONPOSTEDAVAILABLEN, + LLKRXCHNONPOSTEDPARTIALN, + LLKRXCHPOSTEDAVAILABLEN, + LLKRXCHPOSTEDPARTIALN, + LLKRXDATA, + LLKRXECRCBADN, + LLKRXEOFN, + LLKRXEOPN, + LLKRXPREFERREDTYPE, + LLKRXSOFN, + LLKRXSOPN, + LLKRXSRCDSCN, + LLKRXSRCLASTREQN, + LLKRXSRCRDYN, + LLKRXVALIDN, + LLKTCSTATUS, + LLKTXCHANSPACE, + LLKTXCHCOMPLETIONREADYN, + LLKTXCHNONPOSTEDREADYN, + LLKTXCHPOSTEDREADYN, + LLKTXCONFIGREADYN, + LLKTXDSTRDYN, + MAXPAYLOADSIZE, + MAXREADREQUESTSIZE, + MEMSPACEENABLE, + MGMTPSO, + MGMTRDATA, + MGMTSTATSCREDIT, + MIMDLLBRADD, + MIMDLLBREN, + MIMDLLBWADD, + MIMDLLBWDATA, + MIMDLLBWEN, + MIMRXBRADD, + MIMRXBREN, + MIMRXBWADD, + MIMRXBWDATA, + MIMRXBWEN, + MIMTXBRADD, + MIMTXBREN, + MIMTXBWADD, + MIMTXBWDATA, + MIMTXBWEN, + PARITYERRORRESPONSE, + PIPEDESKEWLANESL0, + PIPEDESKEWLANESL1, + PIPEDESKEWLANESL2, + PIPEDESKEWLANESL3, + PIPEDESKEWLANESL4, + PIPEDESKEWLANESL5, + PIPEDESKEWLANESL6, + PIPEDESKEWLANESL7, + PIPEPOWERDOWNL0, + PIPEPOWERDOWNL1, + PIPEPOWERDOWNL2, + PIPEPOWERDOWNL3, + PIPEPOWERDOWNL4, + PIPEPOWERDOWNL5, + PIPEPOWERDOWNL6, + PIPEPOWERDOWNL7, + PIPERESETL0, + PIPERESETL1, + PIPERESETL2, + PIPERESETL3, + PIPERESETL4, + PIPERESETL5, + PIPERESETL6, + PIPERESETL7, + PIPERXPOLARITYL0, + PIPERXPOLARITYL1, + PIPERXPOLARITYL2, + PIPERXPOLARITYL3, + PIPERXPOLARITYL4, + PIPERXPOLARITYL5, + PIPERXPOLARITYL6, + PIPERXPOLARITYL7, + PIPETXCOMPLIANCEL0, + PIPETXCOMPLIANCEL1, + PIPETXCOMPLIANCEL2, + PIPETXCOMPLIANCEL3, + PIPETXCOMPLIANCEL4, + PIPETXCOMPLIANCEL5, + PIPETXCOMPLIANCEL6, + PIPETXCOMPLIANCEL7, + PIPETXDATAKL0, + PIPETXDATAKL1, + PIPETXDATAKL2, + PIPETXDATAKL3, + PIPETXDATAKL4, + PIPETXDATAKL5, + PIPETXDATAKL6, + PIPETXDATAKL7, + PIPETXDATAL0, + PIPETXDATAL1, + PIPETXDATAL2, + PIPETXDATAL3, + PIPETXDATAL4, + PIPETXDATAL5, + PIPETXDATAL6, + PIPETXDATAL7, + PIPETXDETECTRXLOOPBACKL0, + PIPETXDETECTRXLOOPBACKL1, + PIPETXDETECTRXLOOPBACKL2, + PIPETXDETECTRXLOOPBACKL3, + PIPETXDETECTRXLOOPBACKL4, + PIPETXDETECTRXLOOPBACKL5, + PIPETXDETECTRXLOOPBACKL6, + PIPETXDETECTRXLOOPBACKL7, + PIPETXELECIDLEL0, + PIPETXELECIDLEL1, + PIPETXELECIDLEL2, + PIPETXELECIDLEL3, + PIPETXELECIDLEL4, + PIPETXELECIDLEL5, + PIPETXELECIDLEL6, + PIPETXELECIDLEL7, + SERRENABLE, + URREPORTINGENABLE, + + AUXPOWER, + CFGNEGOTIATEDLINKWIDTH, + COMPLIANCEAVOID, + CRMCFGBRIDGEHOTRESET, + CRMCORECLK, + CRMCORECLKDLO, + CRMCORECLKRXO, + CRMCORECLKTXO, + CRMLINKRSTN, + CRMMACRSTN, + CRMMGMTRSTN, + CRMNVRSTN, + CRMTXHOTRESETN, + CRMURSTN, + CRMUSERCFGRSTN, + CRMUSERCLK, + CRMUSERCLKRXO, + CRMUSERCLKTXO, + CROSSLINKSEED, + L0ACKNAKTIMERADJUSTMENT, + L0ALLDOWNPORTSINL1, + L0ALLDOWNRXPORTSINL0S, + L0ASE, + L0ASPORTCOUNT, + L0ASTURNPOOLBITSCONSUMED, + L0ATTENTIONBUTTONPRESSED, + L0CFGASSPANTREEOWNEDSTATE, + L0CFGASSTATECHANGECMD, + L0CFGDISABLESCRAMBLE, + L0CFGEXTENDEDSYNC, + L0CFGL0SENTRYENABLE, + L0CFGL0SENTRYSUP, + L0CFGL0SEXITLAT, + L0CFGLINKDISABLE, + L0CFGLOOPBACKMASTER, + L0CFGNEGOTIATEDMAXP, + L0CFGVCENABLE, + L0CFGVCID, + L0DLLHOLDLINKUP, + L0ELECTROMECHANICALINTERLOCKENGAGED, + L0FWDASSERTINTALEGACYINT, + L0FWDASSERTINTBLEGACYINT, + L0FWDASSERTINTCLEGACYINT, + L0FWDASSERTINTDLEGACYINT, + L0FWDCORRERRIN, + L0FWDDEASSERTINTALEGACYINT, + L0FWDDEASSERTINTBLEGACYINT, + L0FWDDEASSERTINTCLEGACYINT, + L0FWDDEASSERTINTDLEGACYINT, + L0FWDFATALERRIN, + L0FWDNONFATALERRIN, + L0LEGACYINTFUNCT0, + L0MRLSENSORCLOSEDN, + L0MSIREQUEST0, + L0PACKETHEADERFROMUSER, + L0PMEREQIN, + L0PORTNUMBER, + L0POWERFAULTDETECTED, + L0PRESENCEDETECTSLOTEMPTYN, + L0PWRNEWSTATEREQ, + L0PWRNEXTLINKSTATE, + L0REPLAYTIMERADJUSTMENT, + L0ROOTTURNOFFREQ, + L0RXTLTLPNONINITIALIZEDVC, + L0SENDUNLOCKMESSAGE, + L0SETCOMPLETERABORTERROR, + L0SETCOMPLETIONTIMEOUTCORRERROR, + L0SETCOMPLETIONTIMEOUTUNCORRERROR, + L0SETDETECTEDCORRERROR, + L0SETDETECTEDFATALERROR, + L0SETDETECTEDNONFATALERROR, + L0SETLINKDETECTEDPARITYERROR, + L0SETLINKMASTERDATAPARITY, + L0SETLINKRECEIVEDMASTERABORT, + L0SETLINKRECEIVEDTARGETABORT, + L0SETLINKSIGNALLEDTARGETABORT, + L0SETLINKSYSTEMERROR, + L0SETUNEXPECTEDCOMPLETIONCORRERROR, + L0SETUNEXPECTEDCOMPLETIONUNCORRERROR, + L0SETUNSUPPORTEDREQUESTNONPOSTEDERROR, + L0SETUNSUPPORTEDREQUESTOTHERERROR, + L0SETUSERDETECTEDPARITYERROR, + L0SETUSERMASTERDATAPARITY, + L0SETUSERRECEIVEDMASTERABORT, + L0SETUSERRECEIVEDTARGETABORT, + L0SETUSERSIGNALLEDTARGETABORT, + L0SETUSERSYSTEMERROR, + L0TLASFCCREDSTARVATION, + L0TLLINKRETRAIN, + L0TRANSACTIONSPENDING, + L0TXBEACON, + L0TXCFGPM, + L0TXCFGPMTYPE, + L0TXTLFCCMPLMCCRED, + L0TXTLFCCMPLMCUPDATE, + L0TXTLFCNPOSTBYPCRED, + L0TXTLFCNPOSTBYPUPDATE, + L0TXTLFCPOSTORDCRED, + L0TXTLFCPOSTORDUPDATE, + L0TXTLSBFCDATA, + L0TXTLSBFCUPDATE, + L0TXTLTLPDATA, + L0TXTLTLPEDB, + L0TXTLTLPENABLE, + L0TXTLTLPEND, + L0TXTLTLPLATENCY, + L0TXTLTLPREQ, + L0TXTLTLPREQEND, + L0TXTLTLPWIDTH, + L0UPSTREAMRXPORTINL0S, + L0VC0PREVIEWEXPAND, + L0WAKEN, + LLKRXCHFIFO, + LLKRXCHTC, + LLKRXDSTCONTREQN, + LLKRXDSTREQN, + LLKTX4DWHEADERN, + LLKTXCHFIFO, + LLKTXCHTC, + LLKTXCOMPLETEN, + LLKTXCREATEECRCN, + LLKTXDATA, + LLKTXENABLEN, + LLKTXEOFN, + LLKTXEOPN, + LLKTXSOFN, + LLKTXSOPN, + LLKTXSRCDSCN, + LLKTXSRCRDYN, + MAINPOWER, + MGMTADDR, + MGMTBWREN, + MGMTRDEN, + MGMTSTATSCREDITSEL, + MGMTWDATA, + MGMTWREN, + MIMDLLBRDATA, + MIMRXBRDATA, + MIMTXBRDATA, + PIPEPHYSTATUSL0, + PIPEPHYSTATUSL1, + PIPEPHYSTATUSL2, + PIPEPHYSTATUSL3, + PIPEPHYSTATUSL4, + PIPEPHYSTATUSL5, + PIPEPHYSTATUSL6, + PIPEPHYSTATUSL7, + PIPERXCHANISALIGNEDL0, + PIPERXCHANISALIGNEDL1, + PIPERXCHANISALIGNEDL2, + PIPERXCHANISALIGNEDL3, + PIPERXCHANISALIGNEDL4, + PIPERXCHANISALIGNEDL5, + PIPERXCHANISALIGNEDL6, + PIPERXCHANISALIGNEDL7, + PIPERXDATAKL0, + PIPERXDATAKL1, + PIPERXDATAKL2, + PIPERXDATAKL3, + PIPERXDATAKL4, + PIPERXDATAKL5, + PIPERXDATAKL6, + PIPERXDATAKL7, + PIPERXDATAL0, + PIPERXDATAL1, + PIPERXDATAL2, + PIPERXDATAL3, + PIPERXDATAL4, + PIPERXDATAL5, + PIPERXDATAL6, + PIPERXDATAL7, + PIPERXELECIDLEL0, + PIPERXELECIDLEL1, + PIPERXELECIDLEL2, + PIPERXELECIDLEL3, + PIPERXELECIDLEL4, + PIPERXELECIDLEL5, + PIPERXELECIDLEL6, + PIPERXELECIDLEL7, + PIPERXSTATUSL0, + PIPERXSTATUSL1, + PIPERXSTATUSL2, + PIPERXSTATUSL3, + PIPERXSTATUSL4, + PIPERXSTATUSL5, + PIPERXSTATUSL6, + PIPERXSTATUSL7, + PIPERXVALIDL0, + PIPERXVALIDL1, + PIPERXVALIDL2, + PIPERXVALIDL3, + PIPERXVALIDL4, + PIPERXVALIDL5, + PIPERXVALIDL6, + PIPERXVALIDL7 + +); + +parameter AERCAPABILITYECRCCHECKCAPABLE = "FALSE"; +parameter AERCAPABILITYECRCGENCAPABLE = "FALSE"; +parameter BAR0EXIST = "TRUE"; +parameter BAR0PREFETCHABLE = "TRUE"; +parameter BAR1EXIST = "FALSE"; +parameter BAR1PREFETCHABLE = "FALSE"; +parameter BAR2EXIST = "FALSE"; +parameter BAR2PREFETCHABLE = "FALSE"; +parameter BAR3EXIST = "FALSE"; +parameter BAR3PREFETCHABLE = "FALSE"; +parameter BAR4EXIST = "FALSE"; +parameter BAR4PREFETCHABLE = "FALSE"; +parameter BAR5EXIST = "FALSE"; +parameter BAR5PREFETCHABLE = "FALSE"; +parameter CLKDIVIDED = "FALSE"; +parameter DUALCOREENABLE = "FALSE"; +parameter DUALCORESLAVE = "FALSE"; +parameter INFINITECOMPLETIONS = "TRUE"; +parameter ISSWITCH = "FALSE"; +parameter LINKSTATUSSLOTCLOCKCONFIG = "FALSE"; +parameter LLKBYPASS = "FALSE"; +parameter PBCAPABILITYSYSTEMALLOCATED = "FALSE"; +parameter PCIECAPABILITYSLOTIMPL = "FALSE"; +parameter PMCAPABILITYD1SUPPORT = "FALSE"; +parameter PMCAPABILITYD2SUPPORT = "FALSE"; +parameter PMCAPABILITYDSI = "TRUE"; +parameter RAMSHARETXRX = "FALSE"; +parameter RESETMODE = "FALSE"; +parameter RETRYREADADDRPIPE = "FALSE"; +parameter RETRYREADDATAPIPE = "FALSE"; +parameter RETRYWRITEPIPE = "FALSE"; +parameter RXREADADDRPIPE = "FALSE"; +parameter RXREADDATAPIPE = "FALSE"; +parameter RXWRITEPIPE = "FALSE"; +parameter SELECTASMODE = "FALSE"; +parameter SELECTDLLIF = "FALSE"; +parameter SLOTCAPABILITYATTBUTTONPRESENT = "FALSE"; +parameter SLOTCAPABILITYATTINDICATORPRESENT = "FALSE"; +parameter SLOTCAPABILITYHOTPLUGCAPABLE = "FALSE"; +parameter SLOTCAPABILITYHOTPLUGSURPRISE = "FALSE"; +parameter SLOTCAPABILITYMSLSENSORPRESENT = "FALSE"; +parameter SLOTCAPABILITYPOWERCONTROLLERPRESENT = "FALSE"; +parameter SLOTCAPABILITYPOWERINDICATORPRESENT = "FALSE"; +parameter SLOTIMPLEMENTED = "FALSE"; +parameter TXREADADDRPIPE = "FALSE"; +parameter TXREADDATAPIPE = "FALSE"; +parameter TXWRITEPIPE = "FALSE"; +parameter UPSTREAMFACING = "TRUE"; +parameter XLINKSUPPORTED = "FALSE"; +parameter [10:0] VC0TOTALCREDITSCD = 11'h0; +parameter [10:0] VC0TOTALCREDITSPD = 11'h34; +parameter [10:0] VC1TOTALCREDITSCD = 11'h0; +parameter [10:0] VC1TOTALCREDITSPD = 11'h0; +parameter [11:0] AERBASEPTR = 12'h110; +parameter [11:0] AERCAPABILITYNEXTPTR = 12'h138; +parameter [11:0] DSNBASEPTR = 12'h148; +parameter [11:0] DSNCAPABILITYNEXTPTR = 12'h154; +parameter [11:0] EXTCFGXPCAPPTR = 12'h0; +parameter [11:0] MSIBASEPTR = 12'h48; +parameter [11:0] PBBASEPTR = 12'h138; +parameter [11:0] PBCAPABILITYNEXTPTR = 12'h148; +parameter [11:0] PMBASEPTR = 12'h40; +parameter [11:0] RETRYRAMSIZE = 12'h9; +parameter [11:0] VCBASEPTR = 12'h154; +parameter [11:0] VCCAPABILITYNEXTPTR = 12'h0; +parameter [12:0] SLOTCAPABILITYPHYSICALSLOTNUM = 13'h0; +parameter [12:0] VC0RXFIFOBASEC = 13'h98; +parameter [12:0] VC0RXFIFOBASENP = 13'h80; +parameter [12:0] VC0RXFIFOBASEP = 13'h0; +parameter [12:0] VC0RXFIFOLIMITC = 13'h117; +parameter [12:0] VC0RXFIFOLIMITNP = 13'h97; +parameter [12:0] VC0RXFIFOLIMITP = 13'h7f; +parameter [12:0] VC0TXFIFOBASEC = 13'h98; +parameter [12:0] VC0TXFIFOBASENP = 13'h80; +parameter [12:0] VC0TXFIFOBASEP = 13'h0; +parameter [12:0] VC0TXFIFOLIMITC = 13'h117; +parameter [12:0] VC0TXFIFOLIMITNP = 13'h97; +parameter [12:0] VC0TXFIFOLIMITP = 13'h7f; +parameter [12:0] VC1RXFIFOBASEC = 13'h118; +parameter [12:0] VC1RXFIFOBASENP = 13'h118; +parameter [12:0] VC1RXFIFOBASEP = 13'h118; +parameter [12:0] VC1RXFIFOLIMITC = 13'h118; +parameter [12:0] VC1RXFIFOLIMITNP = 13'h118; +parameter [12:0] VC1RXFIFOLIMITP = 13'h118; +parameter [12:0] VC1TXFIFOBASEC = 13'h118; +parameter [12:0] VC1TXFIFOBASENP = 13'h118; +parameter [12:0] VC1TXFIFOBASEP = 13'h118; +parameter [12:0] VC1TXFIFOLIMITC = 13'h118; +parameter [12:0] VC1TXFIFOLIMITNP = 13'h118; +parameter [12:0] VC1TXFIFOLIMITP = 13'h118; +parameter [15:0] DEVICEID = 16'h5050; +parameter [15:0] SUBSYSTEMID = 16'h5050; +parameter [15:0] SUBSYSTEMVENDORID = 16'h10EE; +parameter [15:0] VENDORID = 16'h10EE; +parameter [1:0] LINKCAPABILITYASPMSUPPORT = 2'h1; +parameter [1:0] PBCAPABILITYDW0DATASCALE = 2'h0; +parameter [1:0] PBCAPABILITYDW0PMSTATE = 2'h0; +parameter [1:0] PBCAPABILITYDW1DATASCALE = 2'h0; +parameter [1:0] PBCAPABILITYDW1PMSTATE = 2'h0; +parameter [1:0] PBCAPABILITYDW2DATASCALE = 2'h0; +parameter [1:0] PBCAPABILITYDW2PMSTATE = 2'h0; +parameter [1:0] PBCAPABILITYDW3DATASCALE = 2'h0; +parameter [1:0] PBCAPABILITYDW3PMSTATE = 2'h0; +parameter [1:0] PMSTATUSCONTROLDATASCALE = 2'h0; +parameter [1:0] SLOTCAPABILITYSLOTPOWERLIMITSCALE = 2'h0; +parameter [23:0] CLASSCODE = 24'h058000; +parameter [2:0] CONFIGROUTING = 3'h1; +parameter [2:0] DEVICECAPABILITYENDPOINTL0SLATENCY = 3'h0; +parameter [2:0] DEVICECAPABILITYENDPOINTL1LATENCY = 3'h0; +parameter [2:0] MSICAPABILITYMULTIMSGCAP = 3'h0; +parameter [2:0] PBCAPABILITYDW0PMSUBSTATE = 3'h0; +parameter [2:0] PBCAPABILITYDW0POWERRAIL = 3'h0; +parameter [2:0] PBCAPABILITYDW0TYPE = 3'h0; +parameter [2:0] PBCAPABILITYDW1PMSUBSTATE = 3'h0; +parameter [2:0] PBCAPABILITYDW1POWERRAIL = 3'h0; +parameter [2:0] PBCAPABILITYDW1TYPE = 3'h0; +parameter [2:0] PBCAPABILITYDW2PMSUBSTATE = 3'h0; +parameter [2:0] PBCAPABILITYDW2POWERRAIL = 3'h0; +parameter [2:0] PBCAPABILITYDW2TYPE = 3'h0; +parameter [2:0] PBCAPABILITYDW3PMSUBSTATE = 3'h0; +parameter [2:0] PBCAPABILITYDW3POWERRAIL = 3'h0; +parameter [2:0] PBCAPABILITYDW3TYPE = 3'h0; +parameter [2:0] PMCAPABILITYAUXCURRENT = 3'h0; +parameter [2:0] PORTVCCAPABILITYEXTENDEDVCCOUNT = 3'h0; +parameter [31:0] CARDBUSCISPOINTER = 32'h0; +parameter [3:0] XPDEVICEPORTTYPE = 4'h0; +parameter [4:0] PCIECAPABILITYINTMSGNUM = 5'h0; +parameter [4:0] PMCAPABILITYPMESUPPORT = 5'h0; +parameter [5:0] BAR0MASKWIDTH = 6'h14; +parameter [5:0] BAR1MASKWIDTH = 6'h0; +parameter [5:0] BAR2MASKWIDTH = 6'h0; +parameter [5:0] BAR3MASKWIDTH = 6'h0; +parameter [5:0] BAR4MASKWIDTH = 6'h0; +parameter [5:0] BAR5MASKWIDTH = 6'h0; +parameter [5:0] LINKCAPABILITYMAXLINKWIDTH = 6'h01; +parameter [63:0] DEVICESERIALNUMBER = 64'hE000000001000A35; +parameter [6:0] VC0TOTALCREDITSCH = 7'h0; +parameter [6:0] VC0TOTALCREDITSNPH = 7'h08; +parameter [6:0] VC0TOTALCREDITSPH = 7'h08; +parameter [6:0] VC1TOTALCREDITSCH = 7'h0; +parameter [6:0] VC1TOTALCREDITSNPH = 7'h0; +parameter [6:0] VC1TOTALCREDITSPH = 7'h0; +parameter [7:0] ACTIVELANESIN = 8'h1; +parameter [7:0] CAPABILITIESPOINTER = 8'h40; +parameter [7:0] EXTCFGCAPPTR = 8'h0; +parameter [7:0] HEADERTYPE = 8'h0; +parameter [7:0] INTERRUPTPIN = 8'h0; +parameter [7:0] MSICAPABILITYNEXTPTR = 8'h60; +parameter [7:0] PBCAPABILITYDW0BASEPOWER = 8'h0; +parameter [7:0] PBCAPABILITYDW1BASEPOWER = 8'h0; +parameter [7:0] PBCAPABILITYDW2BASEPOWER = 8'h0; +parameter [7:0] PBCAPABILITYDW3BASEPOWER = 8'h0; +parameter [7:0] PCIECAPABILITYNEXTPTR = 8'h0; +parameter [7:0] PMCAPABILITYNEXTPTR = 8'h60; +parameter [7:0] PMDATA0 = 8'h0; +parameter [7:0] PMDATA1 = 8'h0; +parameter [7:0] PMDATA2 = 8'h0; +parameter [7:0] PMDATA3 = 8'h0; +parameter [7:0] PMDATA4 = 8'h0; +parameter [7:0] PMDATA5 = 8'h0; +parameter [7:0] PMDATA6 = 8'h0; +parameter [7:0] PMDATA7 = 8'h0; +parameter [7:0] PMDATA8 = 8'h0; +parameter [7:0] PORTVCCAPABILITYVCARBCAP = 8'h0; +parameter [7:0] PORTVCCAPABILITYVCARBTABLEOFFSET = 8'h0; +parameter [7:0] REVISIONID = 8'h0; +parameter [7:0] SLOTCAPABILITYSLOTPOWERLIMITVALUE = 8'h0; +parameter [7:0] XPBASEPTR = 8'h60; +parameter integer BAR0ADDRWIDTH = 0; +parameter integer BAR0IOMEMN = 0; +parameter integer BAR1ADDRWIDTH = 0; +parameter integer BAR1IOMEMN = 0; +parameter integer BAR2ADDRWIDTH = 0; +parameter integer BAR2IOMEMN = 0; +parameter integer BAR3ADDRWIDTH = 0; +parameter integer BAR3IOMEMN = 0; +parameter integer BAR4ADDRWIDTH = 0; +parameter integer BAR4IOMEMN = 0; +parameter integer BAR5IOMEMN = 0; +parameter integer DUALROLECFGCNTRLROOTEPN = 0; +parameter integer L0SEXITLATENCY = 7; +parameter integer L0SEXITLATENCYCOMCLK = 7; +parameter integer L1EXITLATENCY = 7; +parameter integer L1EXITLATENCYCOMCLK = 7; +parameter integer LOWPRIORITYVCCOUNT = 0; +parameter integer PCIEREVISION = 1; +parameter integer PMDATASCALE0 = 0; +parameter integer PMDATASCALE1 = 0; +parameter integer PMDATASCALE2 = 0; +parameter integer PMDATASCALE3 = 0; +parameter integer PMDATASCALE4 = 0; +parameter integer PMDATASCALE5 = 0; +parameter integer PMDATASCALE6 = 0; +parameter integer PMDATASCALE7 = 0; +parameter integer PMDATASCALE8 = 0; +parameter integer RETRYRAMREADLATENCY = 3; +parameter integer RETRYRAMWIDTH = 0; +parameter integer RETRYRAMWRITELATENCY = 1; +parameter integer TLRAMREADLATENCY = 3; +parameter integer TLRAMWIDTH = 0; +parameter integer TLRAMWRITELATENCY = 1; +parameter integer TXTSNFTS = 255; +parameter integer TXTSNFTSCOMCLK = 255; +parameter integer XPMAXPAYLOAD = 0; +parameter integer XPRCBCONTROL = 0; + +localparam in_delay = 0; +localparam out_delay = 0; +localparam CLK_DELAY = 0; + +output BUSMASTERENABLE; +output CRMDOHOTRESETN; +output CRMPWRSOFTRESETN; +output CRMRXHOTRESETN; +output DLLTXPMDLLPOUTSTANDING; +output INTERRUPTDISABLE; +output IOSPACEENABLE; +output L0ASAUTONOMOUSINITCOMPLETED; +output L0CFGLOOPBACKACK; +output L0CORRERRMSGRCVD; +output L0DLLASTXSTATE; +output L0DLLRXACKOUTSTANDING; +output L0DLLTXNONFCOUTSTANDING; +output L0DLLTXOUTSTANDING; +output L0FATALERRMSGRCVD; +output L0FIRSTCFGWRITEOCCURRED; +output L0FWDCORRERROUT; +output L0FWDFATALERROUT; +output L0FWDNONFATALERROUT; +output L0MACENTEREDL0; +output L0MACLINKTRAINING; +output L0MACLINKUP; +output L0MACNEWSTATEACK; +output L0MACRXL0SSTATE; +output L0MACUPSTREAMDOWNSTREAM; +output L0MSIENABLE0; +output L0NONFATALERRMSGRCVD; +output L0PMEACK; +output L0PMEEN; +output L0PMEREQOUT; +output L0POWERCONTROLLERCONTROL; +output L0PWRINHIBITTRANSFERS; +output L0PWRL1STATE; +output L0PWRL23READYDEVICE; +output L0PWRL23READYSTATE; +output L0PWRTURNOFFREQ; +output L0PWRTXL0SSTATE; +output L0RECEIVEDASSERTINTALEGACYINT; +output L0RECEIVEDASSERTINTBLEGACYINT; +output L0RECEIVEDASSERTINTCLEGACYINT; +output L0RECEIVEDASSERTINTDLEGACYINT; +output L0RECEIVEDDEASSERTINTALEGACYINT; +output L0RECEIVEDDEASSERTINTBLEGACYINT; +output L0RECEIVEDDEASSERTINTCLEGACYINT; +output L0RECEIVEDDEASSERTINTDLEGACYINT; +output L0RXBEACON; +output L0RXDLLPM; +output L0RXDLLSBFCUPDATE; +output L0RXDLLTLPECRCOK; +output L0STATSCFGOTHERRECEIVED; +output L0STATSCFGOTHERTRANSMITTED; +output L0STATSCFGRECEIVED; +output L0STATSCFGTRANSMITTED; +output L0STATSDLLPRECEIVED; +output L0STATSDLLPTRANSMITTED; +output L0STATSOSRECEIVED; +output L0STATSOSTRANSMITTED; +output L0STATSTLPRECEIVED; +output L0STATSTLPTRANSMITTED; +output L0TOGGLEELECTROMECHANICALINTERLOCK; +output L0TXDLLPMUPDATED; +output L0TXDLLSBFCUPDATED; +output L0UNLOCKRECEIVED; +output LLKRX4DWHEADERN; +output LLKRXCHCONFIGAVAILABLEN; +output LLKRXCHCONFIGPARTIALN; +output LLKRXECRCBADN; +output LLKRXEOFN; +output LLKRXEOPN; +output LLKRXSOFN; +output LLKRXSOPN; +output LLKRXSRCDSCN; +output LLKRXSRCLASTREQN; +output LLKRXSRCRDYN; +output LLKTXCONFIGREADYN; +output LLKTXDSTRDYN; +output MEMSPACEENABLE; +output MIMDLLBREN; +output MIMDLLBWEN; +output MIMRXBREN; +output MIMRXBWEN; +output MIMTXBREN; +output MIMTXBWEN; +output PARITYERRORRESPONSE; +output PIPEDESKEWLANESL0; +output PIPEDESKEWLANESL1; +output PIPEDESKEWLANESL2; +output PIPEDESKEWLANESL3; +output PIPEDESKEWLANESL4; +output PIPEDESKEWLANESL5; +output PIPEDESKEWLANESL6; +output PIPEDESKEWLANESL7; +output PIPERESETL0; +output PIPERESETL1; +output PIPERESETL2; +output PIPERESETL3; +output PIPERESETL4; +output PIPERESETL5; +output PIPERESETL6; +output PIPERESETL7; +output PIPERXPOLARITYL0; +output PIPERXPOLARITYL1; +output PIPERXPOLARITYL2; +output PIPERXPOLARITYL3; +output PIPERXPOLARITYL4; +output PIPERXPOLARITYL5; +output PIPERXPOLARITYL6; +output PIPERXPOLARITYL7; +output PIPETXCOMPLIANCEL0; +output PIPETXCOMPLIANCEL1; +output PIPETXCOMPLIANCEL2; +output PIPETXCOMPLIANCEL3; +output PIPETXCOMPLIANCEL4; +output PIPETXCOMPLIANCEL5; +output PIPETXCOMPLIANCEL6; +output PIPETXCOMPLIANCEL7; +output PIPETXDATAKL0; +output PIPETXDATAKL1; +output PIPETXDATAKL2; +output PIPETXDATAKL3; +output PIPETXDATAKL4; +output PIPETXDATAKL5; +output PIPETXDATAKL6; +output PIPETXDATAKL7; +output PIPETXDETECTRXLOOPBACKL0; +output PIPETXDETECTRXLOOPBACKL1; +output PIPETXDETECTRXLOOPBACKL2; +output PIPETXDETECTRXLOOPBACKL3; +output PIPETXDETECTRXLOOPBACKL4; +output PIPETXDETECTRXLOOPBACKL5; +output PIPETXDETECTRXLOOPBACKL6; +output PIPETXDETECTRXLOOPBACKL7; +output PIPETXELECIDLEL0; +output PIPETXELECIDLEL1; +output PIPETXELECIDLEL2; +output PIPETXELECIDLEL3; +output PIPETXELECIDLEL4; +output PIPETXELECIDLEL5; +output PIPETXELECIDLEL6; +output PIPETXELECIDLEL7; +output SERRENABLE; +output URREPORTINGENABLE; +output [11:0] MGMTSTATSCREDIT; +output [11:0] MIMDLLBRADD; +output [11:0] MIMDLLBWADD; +output [12:0] L0COMPLETERID; +output [12:0] MIMRXBRADD; +output [12:0] MIMRXBWADD; +output [12:0] MIMTXBRADD; +output [12:0] MIMTXBWADD; +output [15:0] L0ERRMSGREQID; +output [15:0] LLKRXPREFERREDTYPE; +output [16:0] MGMTPSO; +output [18:0] L0RXDLLSBFCDATA; +output [19:0] L0RXDLLFCNPOSTBYPCRED; +output [1:0] L0ATTENTIONINDICATORCONTROL; +output [1:0] L0DLLASRXSTATE; +output [1:0] L0POWERINDICATORCONTROL; +output [1:0] L0PWRSTATE0; +output [1:0] L0RXDLLTLPEND; +output [1:0] L0RXMACLINKERROR; +output [1:0] LLKRXVALIDN; +output [1:0] PIPEPOWERDOWNL0; +output [1:0] PIPEPOWERDOWNL1; +output [1:0] PIPEPOWERDOWNL2; +output [1:0] PIPEPOWERDOWNL3; +output [1:0] PIPEPOWERDOWNL4; +output [1:0] PIPEPOWERDOWNL5; +output [1:0] PIPEPOWERDOWNL6; +output [1:0] PIPEPOWERDOWNL7; +output [23:0] L0RXDLLFCCMPLMCCRED; +output [23:0] L0RXDLLFCPOSTORDCRED; +output [2:0] L0MCFOUND; +output [2:0] L0MULTIMSGEN0; +output [2:0] L0RXDLLPMTYPE; +output [2:0] L0TRANSFORMEDVC; +output [2:0] MAXPAYLOADSIZE; +output [2:0] MAXREADREQUESTSIZE; +output [31:0] MGMTRDATA; +output [3:0] L0LTSSMSTATE; +output [3:0] L0MACNEGOTIATEDLINKWIDTH; +output [3:0] L0UCBYPFOUND; +output [3:0] L0UCORDFOUND; +output [63:0] LLKRXDATA; +output [63:0] MIMDLLBWDATA; +output [63:0] MIMRXBWDATA; +output [63:0] MIMTXBWDATA; +output [6:0] L0DLLERRORVECTOR; +output [7:0] L0DLLVCSTATUS; +output [7:0] L0DLUPDOWN; +output [7:0] L0RXDLLFCCMPLMCUPDATE; +output [7:0] L0RXDLLFCNPOSTBYPUPDATE; +output [7:0] L0RXDLLFCPOSTORDUPDATE; +output [7:0] L0TXDLLFCCMPLMCUPDATED; +output [7:0] L0TXDLLFCNPOSTBYPUPDATED; +output [7:0] L0TXDLLFCPOSTORDUPDATED; +output [7:0] LLKRXCHCOMPLETIONAVAILABLEN; +output [7:0] LLKRXCHCOMPLETIONPARTIALN; +output [7:0] LLKRXCHNONPOSTEDAVAILABLEN; +output [7:0] LLKRXCHNONPOSTEDPARTIALN; +output [7:0] LLKRXCHPOSTEDAVAILABLEN; +output [7:0] LLKRXCHPOSTEDPARTIALN; +output [7:0] LLKTCSTATUS; +output [7:0] LLKTXCHCOMPLETIONREADYN; +output [7:0] LLKTXCHNONPOSTEDREADYN; +output [7:0] LLKTXCHPOSTEDREADYN; +output [7:0] PIPETXDATAL0; +output [7:0] PIPETXDATAL1; +output [7:0] PIPETXDATAL2; +output [7:0] PIPETXDATAL3; +output [7:0] PIPETXDATAL4; +output [7:0] PIPETXDATAL5; +output [7:0] PIPETXDATAL6; +output [7:0] PIPETXDATAL7; +output [9:0] LLKTXCHANSPACE; + +input AUXPOWER; +input COMPLIANCEAVOID; +input CRMCFGBRIDGEHOTRESET; +input CRMCORECLK; +input CRMCORECLKDLO; +input CRMCORECLKRXO; +input CRMCORECLKTXO; +input CRMLINKRSTN; +input CRMMACRSTN; +input CRMMGMTRSTN; +input CRMNVRSTN; +input CRMTXHOTRESETN; +input CRMURSTN; +input CRMUSERCFGRSTN; +input CRMUSERCLK; +input CRMUSERCLKRXO; +input CRMUSERCLKTXO; +input CROSSLINKSEED; +input L0ALLDOWNPORTSINL1; +input L0ALLDOWNRXPORTSINL0S; +input L0ASE; +input L0ATTENTIONBUTTONPRESSED; +input L0CFGASSPANTREEOWNEDSTATE; +input L0CFGDISABLESCRAMBLE; +input L0CFGEXTENDEDSYNC; +input L0CFGL0SENTRYENABLE; +input L0CFGL0SENTRYSUP; +input L0CFGLINKDISABLE; +input L0CFGLOOPBACKMASTER; +input L0DLLHOLDLINKUP; +input L0ELECTROMECHANICALINTERLOCKENGAGED; +input L0FWDASSERTINTALEGACYINT; +input L0FWDASSERTINTBLEGACYINT; +input L0FWDASSERTINTCLEGACYINT; +input L0FWDASSERTINTDLEGACYINT; +input L0FWDCORRERRIN; +input L0FWDDEASSERTINTALEGACYINT; +input L0FWDDEASSERTINTBLEGACYINT; +input L0FWDDEASSERTINTCLEGACYINT; +input L0FWDDEASSERTINTDLEGACYINT; +input L0FWDFATALERRIN; +input L0FWDNONFATALERRIN; +input L0LEGACYINTFUNCT0; +input L0MRLSENSORCLOSEDN; +input L0PMEREQIN; +input L0POWERFAULTDETECTED; +input L0PRESENCEDETECTSLOTEMPTYN; +input L0PWRNEWSTATEREQ; +input L0ROOTTURNOFFREQ; +input L0SENDUNLOCKMESSAGE; +input L0SETCOMPLETERABORTERROR; +input L0SETCOMPLETIONTIMEOUTCORRERROR; +input L0SETCOMPLETIONTIMEOUTUNCORRERROR; +input L0SETDETECTEDCORRERROR; +input L0SETDETECTEDFATALERROR; +input L0SETDETECTEDNONFATALERROR; +input L0SETLINKDETECTEDPARITYERROR; +input L0SETLINKMASTERDATAPARITY; +input L0SETLINKRECEIVEDMASTERABORT; +input L0SETLINKRECEIVEDTARGETABORT; +input L0SETLINKSIGNALLEDTARGETABORT; +input L0SETLINKSYSTEMERROR; +input L0SETUNEXPECTEDCOMPLETIONCORRERROR; +input L0SETUNEXPECTEDCOMPLETIONUNCORRERROR; +input L0SETUNSUPPORTEDREQUESTNONPOSTEDERROR; +input L0SETUNSUPPORTEDREQUESTOTHERERROR; +input L0SETUSERDETECTEDPARITYERROR; +input L0SETUSERMASTERDATAPARITY; +input L0SETUSERRECEIVEDMASTERABORT; +input L0SETUSERRECEIVEDTARGETABORT; +input L0SETUSERSIGNALLEDTARGETABORT; +input L0SETUSERSYSTEMERROR; +input L0TLASFCCREDSTARVATION; +input L0TLLINKRETRAIN; +input L0TRANSACTIONSPENDING; +input L0TXBEACON; +input L0TXCFGPM; +input L0TXTLSBFCUPDATE; +input L0TXTLTLPEDB; +input L0TXTLTLPREQ; +input L0TXTLTLPREQEND; +input L0TXTLTLPWIDTH; +input L0UPSTREAMRXPORTINL0S; +input L0VC0PREVIEWEXPAND; +input L0WAKEN; +input LLKRXDSTCONTREQN; +input LLKRXDSTREQN; +input LLKTX4DWHEADERN; +input LLKTXCOMPLETEN; +input LLKTXCREATEECRCN; +input LLKTXEOFN; +input LLKTXEOPN; +input LLKTXSOFN; +input LLKTXSOPN; +input LLKTXSRCDSCN; +input LLKTXSRCRDYN; +input MAINPOWER; +input MGMTRDEN; +input MGMTWREN; +input PIPEPHYSTATUSL0; +input PIPEPHYSTATUSL1; +input PIPEPHYSTATUSL2; +input PIPEPHYSTATUSL3; +input PIPEPHYSTATUSL4; +input PIPEPHYSTATUSL5; +input PIPEPHYSTATUSL6; +input PIPEPHYSTATUSL7; +input PIPERXCHANISALIGNEDL0; +input PIPERXCHANISALIGNEDL1; +input PIPERXCHANISALIGNEDL2; +input PIPERXCHANISALIGNEDL3; +input PIPERXCHANISALIGNEDL4; +input PIPERXCHANISALIGNEDL5; +input PIPERXCHANISALIGNEDL6; +input PIPERXCHANISALIGNEDL7; +input PIPERXDATAKL0; +input PIPERXDATAKL1; +input PIPERXDATAKL2; +input PIPERXDATAKL3; +input PIPERXDATAKL4; +input PIPERXDATAKL5; +input PIPERXDATAKL6; +input PIPERXDATAKL7; +input PIPERXELECIDLEL0; +input PIPERXELECIDLEL1; +input PIPERXELECIDLEL2; +input PIPERXELECIDLEL3; +input PIPERXELECIDLEL4; +input PIPERXELECIDLEL5; +input PIPERXELECIDLEL6; +input PIPERXELECIDLEL7; +input PIPERXVALIDL0; +input PIPERXVALIDL1; +input PIPERXVALIDL2; +input PIPERXVALIDL3; +input PIPERXVALIDL4; +input PIPERXVALIDL5; +input PIPERXVALIDL6; +input PIPERXVALIDL7; +input [10:0] MGMTADDR; +input [11:0] L0ACKNAKTIMERADJUSTMENT; +input [11:0] L0REPLAYTIMERADJUSTMENT; +input [127:0] L0PACKETHEADERFROMUSER; +input [159:0] L0TXTLFCCMPLMCCRED; +input [159:0] L0TXTLFCPOSTORDCRED; +input [15:0] L0TXTLFCCMPLMCUPDATE; +input [15:0] L0TXTLFCNPOSTBYPUPDATE; +input [15:0] L0TXTLFCPOSTORDUPDATE; +input [18:0] L0TXTLSBFCDATA; +input [191:0] L0TXTLFCNPOSTBYPCRED; +input [1:0] L0PWRNEXTLINKSTATE; +input [1:0] L0TXTLTLPENABLE; +input [1:0] L0TXTLTLPEND; +input [1:0] LLKRXCHFIFO; +input [1:0] LLKTXCHFIFO; +input [1:0] LLKTXENABLEN; +input [23:0] L0CFGVCID; +input [2:0] L0ASTURNPOOLBITSCONSUMED; +input [2:0] L0CFGL0SEXITLAT; +input [2:0] L0CFGNEGOTIATEDMAXP; +input [2:0] L0TXCFGPMTYPE; +input [2:0] LLKRXCHTC; +input [2:0] LLKTXCHTC; +input [2:0] PIPERXSTATUSL0; +input [2:0] PIPERXSTATUSL1; +input [2:0] PIPERXSTATUSL2; +input [2:0] PIPERXSTATUSL3; +input [2:0] PIPERXSTATUSL4; +input [2:0] PIPERXSTATUSL5; +input [2:0] PIPERXSTATUSL6; +input [2:0] PIPERXSTATUSL7; +input [31:0] MGMTWDATA; +input [3:0] L0CFGASSTATECHANGECMD; +input [3:0] L0MSIREQUEST0; +input [3:0] L0TXTLTLPLATENCY; +input [3:0] MGMTBWREN; +input [5:0] CFGNEGOTIATEDLINKWIDTH; +input [63:0] L0TXTLTLPDATA; +input [63:0] LLKTXDATA; +input [63:0] MIMDLLBRDATA; +input [63:0] MIMRXBRDATA; +input [63:0] MIMTXBRDATA; +input [6:0] MGMTSTATSCREDITSEL; +input [7:0] L0ASPORTCOUNT; +input [7:0] L0CFGVCENABLE; +input [7:0] L0PORTNUMBER; +input [7:0] L0RXTLTLPNONINITIALIZEDVC; +input [7:0] PIPERXDATAL0; +input [7:0] PIPERXDATAL1; +input [7:0] PIPERXDATAL2; +input [7:0] PIPERXDATAL3; +input [7:0] PIPERXDATAL4; +input [7:0] PIPERXDATAL5; +input [7:0] PIPERXDATAL6; +input [7:0] PIPERXDATAL7; + +reg AERCAPABILITYECRCCHECKCAPABLE_BINARY; +reg AERCAPABILITYECRCGENCAPABLE_BINARY; +reg BAR0ADDRWIDTH_BINARY; +reg BAR0EXIST_BINARY; +reg BAR0IOMEMN_BINARY; +reg BAR0PREFETCHABLE_BINARY; +reg BAR1ADDRWIDTH_BINARY; +reg BAR1EXIST_BINARY; +reg BAR1IOMEMN_BINARY; +reg BAR1PREFETCHABLE_BINARY; +reg BAR2ADDRWIDTH_BINARY; +reg BAR2EXIST_BINARY; +reg BAR2IOMEMN_BINARY; +reg BAR2PREFETCHABLE_BINARY; +reg BAR3ADDRWIDTH_BINARY; +reg BAR3EXIST_BINARY; +reg BAR3IOMEMN_BINARY; +reg BAR3PREFETCHABLE_BINARY; +reg BAR4ADDRWIDTH_BINARY; +reg BAR4EXIST_BINARY; +reg BAR4IOMEMN_BINARY; +reg BAR4PREFETCHABLE_BINARY; +reg BAR5EXIST_BINARY; +reg BAR5IOMEMN_BINARY; +reg BAR5PREFETCHABLE_BINARY; +reg CLKDIVIDED_BINARY; +reg DUALCOREENABLE_BINARY; +reg DUALCORESLAVE_BINARY; +reg DUALROLECFGCNTRLROOTEPN_BINARY; +reg INFINITECOMPLETIONS_BINARY; +reg ISSWITCH_BINARY; +reg LINKSTATUSSLOTCLOCKCONFIG_BINARY; +reg LLKBYPASS_BINARY; +reg PBCAPABILITYSYSTEMALLOCATED_BINARY; +reg PCIECAPABILITYSLOTIMPL_BINARY; +reg PCIEREVISION_BINARY; +reg PMCAPABILITYD1SUPPORT_BINARY; +reg PMCAPABILITYD2SUPPORT_BINARY; +reg PMCAPABILITYDSI_BINARY; +reg RAMSHARETXRX_BINARY; +reg RESETMODE_BINARY; +reg RETRYRAMWIDTH_BINARY; +reg RETRYREADADDRPIPE_BINARY; +reg RETRYREADDATAPIPE_BINARY; +reg RETRYWRITEPIPE_BINARY; +reg RXREADADDRPIPE_BINARY; +reg RXREADDATAPIPE_BINARY; +reg RXWRITEPIPE_BINARY; +reg SELECTASMODE_BINARY; +reg SELECTDLLIF_BINARY; +reg SLOTCAPABILITYATTBUTTONPRESENT_BINARY; +reg SLOTCAPABILITYATTINDICATORPRESENT_BINARY; +reg SLOTCAPABILITYHOTPLUGCAPABLE_BINARY; +reg SLOTCAPABILITYHOTPLUGSURPRISE_BINARY; +reg SLOTCAPABILITYMSLSENSORPRESENT_BINARY; +reg SLOTCAPABILITYPOWERCONTROLLERPRESENT_BINARY; +reg SLOTCAPABILITYPOWERINDICATORPRESENT_BINARY; +reg SLOTIMPLEMENTED_BINARY; +reg TLRAMWIDTH_BINARY; +reg TXREADADDRPIPE_BINARY; +reg TXREADDATAPIPE_BINARY; +reg TXWRITEPIPE_BINARY; +reg UPSTREAMFACING_BINARY; +reg XLINKSUPPORTED_BINARY; +reg XPRCBCONTROL_BINARY; +reg [1:0] PMDATASCALE0_BINARY; +reg [1:0] PMDATASCALE1_BINARY; +reg [1:0] PMDATASCALE2_BINARY; +reg [1:0] PMDATASCALE3_BINARY; +reg [1:0] PMDATASCALE4_BINARY; +reg [1:0] PMDATASCALE5_BINARY; +reg [1:0] PMDATASCALE6_BINARY; +reg [1:0] PMDATASCALE7_BINARY; +reg [1:0] PMDATASCALE8_BINARY; +reg [2:0] L0SEXITLATENCYCOMCLK_BINARY; +reg [2:0] L0SEXITLATENCY_BINARY; +reg [2:0] L1EXITLATENCYCOMCLK_BINARY; +reg [2:0] L1EXITLATENCY_BINARY; +reg [2:0] LOWPRIORITYVCCOUNT_BINARY; +reg [2:0] RETRYRAMREADLATENCY_BINARY; +reg [2:0] RETRYRAMWRITELATENCY_BINARY; +reg [2:0] TLRAMREADLATENCY_BINARY; +reg [2:0] TLRAMWRITELATENCY_BINARY; +reg [2:0] XPMAXPAYLOAD_BINARY; +reg [7:0] TXTSNFTSCOMCLK_BINARY; +reg [7:0] TXTSNFTS_BINARY; + +tri0 GSR = glbl.GSR; + + +initial begin + case (TXTSNFTS) + 0 : TXTSNFTS_BINARY = 8'b00000000; + 1 : TXTSNFTS_BINARY = 8'b00000001; + 2 : TXTSNFTS_BINARY = 8'b00000010; + 3 : TXTSNFTS_BINARY = 8'b00000011; + 4 : TXTSNFTS_BINARY = 8'b00000100; + 5 : TXTSNFTS_BINARY = 8'b00000101; + 6 : TXTSNFTS_BINARY = 8'b00000110; + 7 : TXTSNFTS_BINARY = 8'b00000111; + 8 : TXTSNFTS_BINARY = 8'b00001000; + 9 : TXTSNFTS_BINARY = 8'b00001001; + 10 : TXTSNFTS_BINARY = 8'b00001010; + 11 : TXTSNFTS_BINARY = 8'b00001011; + 12 : TXTSNFTS_BINARY = 8'b00001100; + 13 : TXTSNFTS_BINARY = 8'b00001101; + 14 : TXTSNFTS_BINARY = 8'b00001110; + 15 : TXTSNFTS_BINARY = 8'b00001111; + 16 : TXTSNFTS_BINARY = 8'b00010000; + 17 : TXTSNFTS_BINARY = 8'b00010001; + 18 : TXTSNFTS_BINARY = 8'b00010010; + 19 : TXTSNFTS_BINARY = 8'b00010011; + 20 : TXTSNFTS_BINARY = 8'b00010100; + 21 : TXTSNFTS_BINARY = 8'b00010101; + 22 : TXTSNFTS_BINARY = 8'b00010110; + 23 : TXTSNFTS_BINARY = 8'b00010111; + 24 : TXTSNFTS_BINARY = 8'b00011000; + 25 : TXTSNFTS_BINARY = 8'b00011001; + 26 : TXTSNFTS_BINARY = 8'b00011010; + 27 : TXTSNFTS_BINARY = 8'b00011011; + 28 : TXTSNFTS_BINARY = 8'b00011100; + 29 : TXTSNFTS_BINARY = 8'b00011101; + 30 : TXTSNFTS_BINARY = 8'b00011110; + 31 : TXTSNFTS_BINARY = 8'b00011111; + 32 : TXTSNFTS_BINARY = 8'b00100000; + 33 : TXTSNFTS_BINARY = 8'b00100001; + 34 : TXTSNFTS_BINARY = 8'b00100010; + 35 : TXTSNFTS_BINARY = 8'b00100011; + 36 : TXTSNFTS_BINARY = 8'b00100100; + 37 : TXTSNFTS_BINARY = 8'b00100101; + 38 : TXTSNFTS_BINARY = 8'b00100110; + 39 : TXTSNFTS_BINARY = 8'b00100111; + 40 : TXTSNFTS_BINARY = 8'b00101000; + 41 : TXTSNFTS_BINARY = 8'b00101001; + 42 : TXTSNFTS_BINARY = 8'b00101010; + 43 : TXTSNFTS_BINARY = 8'b00101011; + 44 : TXTSNFTS_BINARY = 8'b00101100; + 45 : TXTSNFTS_BINARY = 8'b00101101; + 46 : TXTSNFTS_BINARY = 8'b00101110; + 47 : TXTSNFTS_BINARY = 8'b00101111; + 48 : TXTSNFTS_BINARY = 8'b00110000; + 49 : TXTSNFTS_BINARY = 8'b00110001; + 50 : TXTSNFTS_BINARY = 8'b00110010; + 51 : TXTSNFTS_BINARY = 8'b00110011; + 52 : TXTSNFTS_BINARY = 8'b00110100; + 53 : TXTSNFTS_BINARY = 8'b00110101; + 54 : TXTSNFTS_BINARY = 8'b00110110; + 55 : TXTSNFTS_BINARY = 8'b00110111; + 56 : TXTSNFTS_BINARY = 8'b00111000; + 57 : TXTSNFTS_BINARY = 8'b00111001; + 58 : TXTSNFTS_BINARY = 8'b00111010; + 59 : TXTSNFTS_BINARY = 8'b00111011; + 60 : TXTSNFTS_BINARY = 8'b00111100; + 61 : TXTSNFTS_BINARY = 8'b00111101; + 62 : TXTSNFTS_BINARY = 8'b00111110; + 63 : TXTSNFTS_BINARY = 8'b00111111; + 64 : TXTSNFTS_BINARY = 8'b01000000; + 65 : TXTSNFTS_BINARY = 8'b01000001; + 66 : TXTSNFTS_BINARY = 8'b01000010; + 67 : TXTSNFTS_BINARY = 8'b01000011; + 68 : TXTSNFTS_BINARY = 8'b01000100; + 69 : TXTSNFTS_BINARY = 8'b01000101; + 70 : TXTSNFTS_BINARY = 8'b01000110; + 71 : TXTSNFTS_BINARY = 8'b01000111; + 72 : TXTSNFTS_BINARY = 8'b01001000; + 73 : TXTSNFTS_BINARY = 8'b01001001; + 74 : TXTSNFTS_BINARY = 8'b01001010; + 75 : TXTSNFTS_BINARY = 8'b01001011; + 76 : TXTSNFTS_BINARY = 8'b01001100; + 77 : TXTSNFTS_BINARY = 8'b01001101; + 78 : TXTSNFTS_BINARY = 8'b01001110; + 79 : TXTSNFTS_BINARY = 8'b01001111; + 80 : TXTSNFTS_BINARY = 8'b01010000; + 81 : TXTSNFTS_BINARY = 8'b01010001; + 82 : TXTSNFTS_BINARY = 8'b01010010; + 83 : TXTSNFTS_BINARY = 8'b01010011; + 84 : TXTSNFTS_BINARY = 8'b01010100; + 85 : TXTSNFTS_BINARY = 8'b01010101; + 86 : TXTSNFTS_BINARY = 8'b01010110; + 87 : TXTSNFTS_BINARY = 8'b01010111; + 88 : TXTSNFTS_BINARY = 8'b01011000; + 89 : TXTSNFTS_BINARY = 8'b01011001; + 90 : TXTSNFTS_BINARY = 8'b01011010; + 91 : TXTSNFTS_BINARY = 8'b01011011; + 92 : TXTSNFTS_BINARY = 8'b01011100; + 93 : TXTSNFTS_BINARY = 8'b01011101; + 94 : TXTSNFTS_BINARY = 8'b01011110; + 95 : TXTSNFTS_BINARY = 8'b01011111; + 96 : TXTSNFTS_BINARY = 8'b01100000; + 97 : TXTSNFTS_BINARY = 8'b01100001; + 98 : TXTSNFTS_BINARY = 8'b01100010; + 99 : TXTSNFTS_BINARY = 8'b01100011; + 100 : TXTSNFTS_BINARY = 8'b01100100; + 101 : TXTSNFTS_BINARY = 8'b01100101; + 102 : TXTSNFTS_BINARY = 8'b01100110; + 103 : TXTSNFTS_BINARY = 8'b01100111; + 104 : TXTSNFTS_BINARY = 8'b01101000; + 105 : TXTSNFTS_BINARY = 8'b01101001; + 106 : TXTSNFTS_BINARY = 8'b01101010; + 107 : TXTSNFTS_BINARY = 8'b01101011; + 108 : TXTSNFTS_BINARY = 8'b01101100; + 109 : TXTSNFTS_BINARY = 8'b01101101; + 110 : TXTSNFTS_BINARY = 8'b01101110; + 111 : TXTSNFTS_BINARY = 8'b01101111; + 112 : TXTSNFTS_BINARY = 8'b01110000; + 113 : TXTSNFTS_BINARY = 8'b01110001; + 114 : TXTSNFTS_BINARY = 8'b01110010; + 115 : TXTSNFTS_BINARY = 8'b01110011; + 116 : TXTSNFTS_BINARY = 8'b01110100; + 117 : TXTSNFTS_BINARY = 8'b01110101; + 118 : TXTSNFTS_BINARY = 8'b01110110; + 119 : TXTSNFTS_BINARY = 8'b01110111; + 120 : TXTSNFTS_BINARY = 8'b01111000; + 121 : TXTSNFTS_BINARY = 8'b01111001; + 122 : TXTSNFTS_BINARY = 8'b01111010; + 123 : TXTSNFTS_BINARY = 8'b01111011; + 124 : TXTSNFTS_BINARY = 8'b01111100; + 125 : TXTSNFTS_BINARY = 8'b01111101; + 126 : TXTSNFTS_BINARY = 8'b01111110; + 127 : TXTSNFTS_BINARY = 8'b01111111; + 128 : TXTSNFTS_BINARY = 8'b10000000; + 129 : TXTSNFTS_BINARY = 8'b10000001; + 130 : TXTSNFTS_BINARY = 8'b10000010; + 131 : TXTSNFTS_BINARY = 8'b10000011; + 132 : TXTSNFTS_BINARY = 8'b10000100; + 133 : TXTSNFTS_BINARY = 8'b10000101; + 134 : TXTSNFTS_BINARY = 8'b10000110; + 135 : TXTSNFTS_BINARY = 8'b10000111; + 136 : TXTSNFTS_BINARY = 8'b10001000; + 137 : TXTSNFTS_BINARY = 8'b10001001; + 138 : TXTSNFTS_BINARY = 8'b10001010; + 139 : TXTSNFTS_BINARY = 8'b10001011; + 140 : TXTSNFTS_BINARY = 8'b10001100; + 141 : TXTSNFTS_BINARY = 8'b10001101; + 142 : TXTSNFTS_BINARY = 8'b10001110; + 143 : TXTSNFTS_BINARY = 8'b10001111; + 144 : TXTSNFTS_BINARY = 8'b10010000; + 145 : TXTSNFTS_BINARY = 8'b10010001; + 146 : TXTSNFTS_BINARY = 8'b10010010; + 147 : TXTSNFTS_BINARY = 8'b10010011; + 148 : TXTSNFTS_BINARY = 8'b10010100; + 149 : TXTSNFTS_BINARY = 8'b10010101; + 150 : TXTSNFTS_BINARY = 8'b10010110; + 151 : TXTSNFTS_BINARY = 8'b10010111; + 152 : TXTSNFTS_BINARY = 8'b10011000; + 153 : TXTSNFTS_BINARY = 8'b10011001; + 154 : TXTSNFTS_BINARY = 8'b10011010; + 155 : TXTSNFTS_BINARY = 8'b10011011; + 156 : TXTSNFTS_BINARY = 8'b10011100; + 157 : TXTSNFTS_BINARY = 8'b10011101; + 158 : TXTSNFTS_BINARY = 8'b10011110; + 159 : TXTSNFTS_BINARY = 8'b10011111; + 160 : TXTSNFTS_BINARY = 8'b10100000; + 161 : TXTSNFTS_BINARY = 8'b10100001; + 162 : TXTSNFTS_BINARY = 8'b10100010; + 163 : TXTSNFTS_BINARY = 8'b10100011; + 164 : TXTSNFTS_BINARY = 8'b10100100; + 165 : TXTSNFTS_BINARY = 8'b10100101; + 166 : TXTSNFTS_BINARY = 8'b10100110; + 167 : TXTSNFTS_BINARY = 8'b10100111; + 168 : TXTSNFTS_BINARY = 8'b10101000; + 169 : TXTSNFTS_BINARY = 8'b10101001; + 170 : TXTSNFTS_BINARY = 8'b10101010; + 171 : TXTSNFTS_BINARY = 8'b10101011; + 172 : TXTSNFTS_BINARY = 8'b10101100; + 173 : TXTSNFTS_BINARY = 8'b10101101; + 174 : TXTSNFTS_BINARY = 8'b10101110; + 175 : TXTSNFTS_BINARY = 8'b10101111; + 176 : TXTSNFTS_BINARY = 8'b10110000; + 177 : TXTSNFTS_BINARY = 8'b10110001; + 178 : TXTSNFTS_BINARY = 8'b10110010; + 179 : TXTSNFTS_BINARY = 8'b10110011; + 180 : TXTSNFTS_BINARY = 8'b10110100; + 181 : TXTSNFTS_BINARY = 8'b10110101; + 182 : TXTSNFTS_BINARY = 8'b10110110; + 183 : TXTSNFTS_BINARY = 8'b10110111; + 184 : TXTSNFTS_BINARY = 8'b10111000; + 185 : TXTSNFTS_BINARY = 8'b10111001; + 186 : TXTSNFTS_BINARY = 8'b10111010; + 187 : TXTSNFTS_BINARY = 8'b10111011; + 188 : TXTSNFTS_BINARY = 8'b10111100; + 189 : TXTSNFTS_BINARY = 8'b10111101; + 190 : TXTSNFTS_BINARY = 8'b10111110; + 191 : TXTSNFTS_BINARY = 8'b10111111; + 192 : TXTSNFTS_BINARY = 8'b11000000; + 193 : TXTSNFTS_BINARY = 8'b11000001; + 194 : TXTSNFTS_BINARY = 8'b11000010; + 195 : TXTSNFTS_BINARY = 8'b11000011; + 196 : TXTSNFTS_BINARY = 8'b11000100; + 197 : TXTSNFTS_BINARY = 8'b11000101; + 198 : TXTSNFTS_BINARY = 8'b11000110; + 199 : TXTSNFTS_BINARY = 8'b11000111; + 200 : TXTSNFTS_BINARY = 8'b11001000; + 201 : TXTSNFTS_BINARY = 8'b11001001; + 202 : TXTSNFTS_BINARY = 8'b11001010; + 203 : TXTSNFTS_BINARY = 8'b11001011; + 204 : TXTSNFTS_BINARY = 8'b11001100; + 205 : TXTSNFTS_BINARY = 8'b11001101; + 206 : TXTSNFTS_BINARY = 8'b11001110; + 207 : TXTSNFTS_BINARY = 8'b11001111; + 208 : TXTSNFTS_BINARY = 8'b11010000; + 209 : TXTSNFTS_BINARY = 8'b11010001; + 210 : TXTSNFTS_BINARY = 8'b11010010; + 211 : TXTSNFTS_BINARY = 8'b11010011; + 212 : TXTSNFTS_BINARY = 8'b11010100; + 213 : TXTSNFTS_BINARY = 8'b11010101; + 214 : TXTSNFTS_BINARY = 8'b11010110; + 215 : TXTSNFTS_BINARY = 8'b11010111; + 216 : TXTSNFTS_BINARY = 8'b11011000; + 217 : TXTSNFTS_BINARY = 8'b11011001; + 218 : TXTSNFTS_BINARY = 8'b11011010; + 219 : TXTSNFTS_BINARY = 8'b11011011; + 220 : TXTSNFTS_BINARY = 8'b11011100; + 221 : TXTSNFTS_BINARY = 8'b11011101; + 222 : TXTSNFTS_BINARY = 8'b11011110; + 223 : TXTSNFTS_BINARY = 8'b11011111; + 224 : TXTSNFTS_BINARY = 8'b11100000; + 225 : TXTSNFTS_BINARY = 8'b11100001; + 226 : TXTSNFTS_BINARY = 8'b11100010; + 227 : TXTSNFTS_BINARY = 8'b11100011; + 228 : TXTSNFTS_BINARY = 8'b11100100; + 229 : TXTSNFTS_BINARY = 8'b11100101; + 230 : TXTSNFTS_BINARY = 8'b11100110; + 231 : TXTSNFTS_BINARY = 8'b11100111; + 232 : TXTSNFTS_BINARY = 8'b11101000; + 233 : TXTSNFTS_BINARY = 8'b11101001; + 234 : TXTSNFTS_BINARY = 8'b11101010; + 235 : TXTSNFTS_BINARY = 8'b11101011; + 236 : TXTSNFTS_BINARY = 8'b11101100; + 237 : TXTSNFTS_BINARY = 8'b11101101; + 238 : TXTSNFTS_BINARY = 8'b11101110; + 239 : TXTSNFTS_BINARY = 8'b11101111; + 240 : TXTSNFTS_BINARY = 8'b11110000; + 241 : TXTSNFTS_BINARY = 8'b11110001; + 242 : TXTSNFTS_BINARY = 8'b11110010; + 243 : TXTSNFTS_BINARY = 8'b11110011; + 244 : TXTSNFTS_BINARY = 8'b11110100; + 245 : TXTSNFTS_BINARY = 8'b11110101; + 246 : TXTSNFTS_BINARY = 8'b11110110; + 247 : TXTSNFTS_BINARY = 8'b11110111; + 248 : TXTSNFTS_BINARY = 8'b11111000; + 249 : TXTSNFTS_BINARY = 8'b11111001; + 250 : TXTSNFTS_BINARY = 8'b11111010; + 251 : TXTSNFTS_BINARY = 8'b11111011; + 252 : TXTSNFTS_BINARY = 8'b11111100; + 253 : TXTSNFTS_BINARY = 8'b11111101; + 254 : TXTSNFTS_BINARY = 8'b11111110; + 255 : TXTSNFTS_BINARY = 8'b11111111; + default : begin + $display("Attribute Syntax Error : The Attribute TXTSNFTS on PCIE_INTERNAL_1_1 instance %m is set to %d. Legal values for this attribute are 0 to 255.", TXTSNFTS); + $finish; + end + endcase + + case (TXTSNFTSCOMCLK) + 0 : TXTSNFTSCOMCLK_BINARY = 8'b00000000; + 1 : TXTSNFTSCOMCLK_BINARY = 8'b00000001; + 2 : TXTSNFTSCOMCLK_BINARY = 8'b00000010; + 3 : TXTSNFTSCOMCLK_BINARY = 8'b00000011; + 4 : TXTSNFTSCOMCLK_BINARY = 8'b00000100; + 5 : TXTSNFTSCOMCLK_BINARY = 8'b00000101; + 6 : TXTSNFTSCOMCLK_BINARY = 8'b00000110; + 7 : TXTSNFTSCOMCLK_BINARY = 8'b00000111; + 8 : TXTSNFTSCOMCLK_BINARY = 8'b00001000; + 9 : TXTSNFTSCOMCLK_BINARY = 8'b00001001; + 10 : TXTSNFTSCOMCLK_BINARY = 8'b00001010; + 11 : TXTSNFTSCOMCLK_BINARY = 8'b00001011; + 12 : TXTSNFTSCOMCLK_BINARY = 8'b00001100; + 13 : TXTSNFTSCOMCLK_BINARY = 8'b00001101; + 14 : TXTSNFTSCOMCLK_BINARY = 8'b00001110; + 15 : TXTSNFTSCOMCLK_BINARY = 8'b00001111; + 16 : TXTSNFTSCOMCLK_BINARY = 8'b00010000; + 17 : TXTSNFTSCOMCLK_BINARY = 8'b00010001; + 18 : TXTSNFTSCOMCLK_BINARY = 8'b00010010; + 19 : TXTSNFTSCOMCLK_BINARY = 8'b00010011; + 20 : TXTSNFTSCOMCLK_BINARY = 8'b00010100; + 21 : TXTSNFTSCOMCLK_BINARY = 8'b00010101; + 22 : TXTSNFTSCOMCLK_BINARY = 8'b00010110; + 23 : TXTSNFTSCOMCLK_BINARY = 8'b00010111; + 24 : TXTSNFTSCOMCLK_BINARY = 8'b00011000; + 25 : TXTSNFTSCOMCLK_BINARY = 8'b00011001; + 26 : TXTSNFTSCOMCLK_BINARY = 8'b00011010; + 27 : TXTSNFTSCOMCLK_BINARY = 8'b00011011; + 28 : TXTSNFTSCOMCLK_BINARY = 8'b00011100; + 29 : TXTSNFTSCOMCLK_BINARY = 8'b00011101; + 30 : TXTSNFTSCOMCLK_BINARY = 8'b00011110; + 31 : TXTSNFTSCOMCLK_BINARY = 8'b00011111; + 32 : TXTSNFTSCOMCLK_BINARY = 8'b00100000; + 33 : TXTSNFTSCOMCLK_BINARY = 8'b00100001; + 34 : TXTSNFTSCOMCLK_BINARY = 8'b00100010; + 35 : TXTSNFTSCOMCLK_BINARY = 8'b00100011; + 36 : TXTSNFTSCOMCLK_BINARY = 8'b00100100; + 37 : TXTSNFTSCOMCLK_BINARY = 8'b00100101; + 38 : TXTSNFTSCOMCLK_BINARY = 8'b00100110; + 39 : TXTSNFTSCOMCLK_BINARY = 8'b00100111; + 40 : TXTSNFTSCOMCLK_BINARY = 8'b00101000; + 41 : TXTSNFTSCOMCLK_BINARY = 8'b00101001; + 42 : TXTSNFTSCOMCLK_BINARY = 8'b00101010; + 43 : TXTSNFTSCOMCLK_BINARY = 8'b00101011; + 44 : TXTSNFTSCOMCLK_BINARY = 8'b00101100; + 45 : TXTSNFTSCOMCLK_BINARY = 8'b00101101; + 46 : TXTSNFTSCOMCLK_BINARY = 8'b00101110; + 47 : TXTSNFTSCOMCLK_BINARY = 8'b00101111; + 48 : TXTSNFTSCOMCLK_BINARY = 8'b00110000; + 49 : TXTSNFTSCOMCLK_BINARY = 8'b00110001; + 50 : TXTSNFTSCOMCLK_BINARY = 8'b00110010; + 51 : TXTSNFTSCOMCLK_BINARY = 8'b00110011; + 52 : TXTSNFTSCOMCLK_BINARY = 8'b00110100; + 53 : TXTSNFTSCOMCLK_BINARY = 8'b00110101; + 54 : TXTSNFTSCOMCLK_BINARY = 8'b00110110; + 55 : TXTSNFTSCOMCLK_BINARY = 8'b00110111; + 56 : TXTSNFTSCOMCLK_BINARY = 8'b00111000; + 57 : TXTSNFTSCOMCLK_BINARY = 8'b00111001; + 58 : TXTSNFTSCOMCLK_BINARY = 8'b00111010; + 59 : TXTSNFTSCOMCLK_BINARY = 8'b00111011; + 60 : TXTSNFTSCOMCLK_BINARY = 8'b00111100; + 61 : TXTSNFTSCOMCLK_BINARY = 8'b00111101; + 62 : TXTSNFTSCOMCLK_BINARY = 8'b00111110; + 63 : TXTSNFTSCOMCLK_BINARY = 8'b00111111; + 64 : TXTSNFTSCOMCLK_BINARY = 8'b01000000; + 65 : TXTSNFTSCOMCLK_BINARY = 8'b01000001; + 66 : TXTSNFTSCOMCLK_BINARY = 8'b01000010; + 67 : TXTSNFTSCOMCLK_BINARY = 8'b01000011; + 68 : TXTSNFTSCOMCLK_BINARY = 8'b01000100; + 69 : TXTSNFTSCOMCLK_BINARY = 8'b01000101; + 70 : TXTSNFTSCOMCLK_BINARY = 8'b01000110; + 71 : TXTSNFTSCOMCLK_BINARY = 8'b01000111; + 72 : TXTSNFTSCOMCLK_BINARY = 8'b01001000; + 73 : TXTSNFTSCOMCLK_BINARY = 8'b01001001; + 74 : TXTSNFTSCOMCLK_BINARY = 8'b01001010; + 75 : TXTSNFTSCOMCLK_BINARY = 8'b01001011; + 76 : TXTSNFTSCOMCLK_BINARY = 8'b01001100; + 77 : TXTSNFTSCOMCLK_BINARY = 8'b01001101; + 78 : TXTSNFTSCOMCLK_BINARY = 8'b01001110; + 79 : TXTSNFTSCOMCLK_BINARY = 8'b01001111; + 80 : TXTSNFTSCOMCLK_BINARY = 8'b01010000; + 81 : TXTSNFTSCOMCLK_BINARY = 8'b01010001; + 82 : TXTSNFTSCOMCLK_BINARY = 8'b01010010; + 83 : TXTSNFTSCOMCLK_BINARY = 8'b01010011; + 84 : TXTSNFTSCOMCLK_BINARY = 8'b01010100; + 85 : TXTSNFTSCOMCLK_BINARY = 8'b01010101; + 86 : TXTSNFTSCOMCLK_BINARY = 8'b01010110; + 87 : TXTSNFTSCOMCLK_BINARY = 8'b01010111; + 88 : TXTSNFTSCOMCLK_BINARY = 8'b01011000; + 89 : TXTSNFTSCOMCLK_BINARY = 8'b01011001; + 90 : TXTSNFTSCOMCLK_BINARY = 8'b01011010; + 91 : TXTSNFTSCOMCLK_BINARY = 8'b01011011; + 92 : TXTSNFTSCOMCLK_BINARY = 8'b01011100; + 93 : TXTSNFTSCOMCLK_BINARY = 8'b01011101; + 94 : TXTSNFTSCOMCLK_BINARY = 8'b01011110; + 95 : TXTSNFTSCOMCLK_BINARY = 8'b01011111; + 96 : TXTSNFTSCOMCLK_BINARY = 8'b01100000; + 97 : TXTSNFTSCOMCLK_BINARY = 8'b01100001; + 98 : TXTSNFTSCOMCLK_BINARY = 8'b01100010; + 99 : TXTSNFTSCOMCLK_BINARY = 8'b01100011; + 100 : TXTSNFTSCOMCLK_BINARY = 8'b01100100; + 101 : TXTSNFTSCOMCLK_BINARY = 8'b01100101; + 102 : TXTSNFTSCOMCLK_BINARY = 8'b01100110; + 103 : TXTSNFTSCOMCLK_BINARY = 8'b01100111; + 104 : TXTSNFTSCOMCLK_BINARY = 8'b01101000; + 105 : TXTSNFTSCOMCLK_BINARY = 8'b01101001; + 106 : TXTSNFTSCOMCLK_BINARY = 8'b01101010; + 107 : TXTSNFTSCOMCLK_BINARY = 8'b01101011; + 108 : TXTSNFTSCOMCLK_BINARY = 8'b01101100; + 109 : TXTSNFTSCOMCLK_BINARY = 8'b01101101; + 110 : TXTSNFTSCOMCLK_BINARY = 8'b01101110; + 111 : TXTSNFTSCOMCLK_BINARY = 8'b01101111; + 112 : TXTSNFTSCOMCLK_BINARY = 8'b01110000; + 113 : TXTSNFTSCOMCLK_BINARY = 8'b01110001; + 114 : TXTSNFTSCOMCLK_BINARY = 8'b01110010; + 115 : TXTSNFTSCOMCLK_BINARY = 8'b01110011; + 116 : TXTSNFTSCOMCLK_BINARY = 8'b01110100; + 117 : TXTSNFTSCOMCLK_BINARY = 8'b01110101; + 118 : TXTSNFTSCOMCLK_BINARY = 8'b01110110; + 119 : TXTSNFTSCOMCLK_BINARY = 8'b01110111; + 120 : TXTSNFTSCOMCLK_BINARY = 8'b01111000; + 121 : TXTSNFTSCOMCLK_BINARY = 8'b01111001; + 122 : TXTSNFTSCOMCLK_BINARY = 8'b01111010; + 123 : TXTSNFTSCOMCLK_BINARY = 8'b01111011; + 124 : TXTSNFTSCOMCLK_BINARY = 8'b01111100; + 125 : TXTSNFTSCOMCLK_BINARY = 8'b01111101; + 126 : TXTSNFTSCOMCLK_BINARY = 8'b01111110; + 127 : TXTSNFTSCOMCLK_BINARY = 8'b01111111; + 128 : TXTSNFTSCOMCLK_BINARY = 8'b10000000; + 129 : TXTSNFTSCOMCLK_BINARY = 8'b10000001; + 130 : TXTSNFTSCOMCLK_BINARY = 8'b10000010; + 131 : TXTSNFTSCOMCLK_BINARY = 8'b10000011; + 132 : TXTSNFTSCOMCLK_BINARY = 8'b10000100; + 133 : TXTSNFTSCOMCLK_BINARY = 8'b10000101; + 134 : TXTSNFTSCOMCLK_BINARY = 8'b10000110; + 135 : TXTSNFTSCOMCLK_BINARY = 8'b10000111; + 136 : TXTSNFTSCOMCLK_BINARY = 8'b10001000; + 137 : TXTSNFTSCOMCLK_BINARY = 8'b10001001; + 138 : TXTSNFTSCOMCLK_BINARY = 8'b10001010; + 139 : TXTSNFTSCOMCLK_BINARY = 8'b10001011; + 140 : TXTSNFTSCOMCLK_BINARY = 8'b10001100; + 141 : TXTSNFTSCOMCLK_BINARY = 8'b10001101; + 142 : TXTSNFTSCOMCLK_BINARY = 8'b10001110; + 143 : TXTSNFTSCOMCLK_BINARY = 8'b10001111; + 144 : TXTSNFTSCOMCLK_BINARY = 8'b10010000; + 145 : TXTSNFTSCOMCLK_BINARY = 8'b10010001; + 146 : TXTSNFTSCOMCLK_BINARY = 8'b10010010; + 147 : TXTSNFTSCOMCLK_BINARY = 8'b10010011; + 148 : TXTSNFTSCOMCLK_BINARY = 8'b10010100; + 149 : TXTSNFTSCOMCLK_BINARY = 8'b10010101; + 150 : TXTSNFTSCOMCLK_BINARY = 8'b10010110; + 151 : TXTSNFTSCOMCLK_BINARY = 8'b10010111; + 152 : TXTSNFTSCOMCLK_BINARY = 8'b10011000; + 153 : TXTSNFTSCOMCLK_BINARY = 8'b10011001; + 154 : TXTSNFTSCOMCLK_BINARY = 8'b10011010; + 155 : TXTSNFTSCOMCLK_BINARY = 8'b10011011; + 156 : TXTSNFTSCOMCLK_BINARY = 8'b10011100; + 157 : TXTSNFTSCOMCLK_BINARY = 8'b10011101; + 158 : TXTSNFTSCOMCLK_BINARY = 8'b10011110; + 159 : TXTSNFTSCOMCLK_BINARY = 8'b10011111; + 160 : TXTSNFTSCOMCLK_BINARY = 8'b10100000; + 161 : TXTSNFTSCOMCLK_BINARY = 8'b10100001; + 162 : TXTSNFTSCOMCLK_BINARY = 8'b10100010; + 163 : TXTSNFTSCOMCLK_BINARY = 8'b10100011; + 164 : TXTSNFTSCOMCLK_BINARY = 8'b10100100; + 165 : TXTSNFTSCOMCLK_BINARY = 8'b10100101; + 166 : TXTSNFTSCOMCLK_BINARY = 8'b10100110; + 167 : TXTSNFTSCOMCLK_BINARY = 8'b10100111; + 168 : TXTSNFTSCOMCLK_BINARY = 8'b10101000; + 169 : TXTSNFTSCOMCLK_BINARY = 8'b10101001; + 170 : TXTSNFTSCOMCLK_BINARY = 8'b10101010; + 171 : TXTSNFTSCOMCLK_BINARY = 8'b10101011; + 172 : TXTSNFTSCOMCLK_BINARY = 8'b10101100; + 173 : TXTSNFTSCOMCLK_BINARY = 8'b10101101; + 174 : TXTSNFTSCOMCLK_BINARY = 8'b10101110; + 175 : TXTSNFTSCOMCLK_BINARY = 8'b10101111; + 176 : TXTSNFTSCOMCLK_BINARY = 8'b10110000; + 177 : TXTSNFTSCOMCLK_BINARY = 8'b10110001; + 178 : TXTSNFTSCOMCLK_BINARY = 8'b10110010; + 179 : TXTSNFTSCOMCLK_BINARY = 8'b10110011; + 180 : TXTSNFTSCOMCLK_BINARY = 8'b10110100; + 181 : TXTSNFTSCOMCLK_BINARY = 8'b10110101; + 182 : TXTSNFTSCOMCLK_BINARY = 8'b10110110; + 183 : TXTSNFTSCOMCLK_BINARY = 8'b10110111; + 184 : TXTSNFTSCOMCLK_BINARY = 8'b10111000; + 185 : TXTSNFTSCOMCLK_BINARY = 8'b10111001; + 186 : TXTSNFTSCOMCLK_BINARY = 8'b10111010; + 187 : TXTSNFTSCOMCLK_BINARY = 8'b10111011; + 188 : TXTSNFTSCOMCLK_BINARY = 8'b10111100; + 189 : TXTSNFTSCOMCLK_BINARY = 8'b10111101; + 190 : TXTSNFTSCOMCLK_BINARY = 8'b10111110; + 191 : TXTSNFTSCOMCLK_BINARY = 8'b10111111; + 192 : TXTSNFTSCOMCLK_BINARY = 8'b11000000; + 193 : TXTSNFTSCOMCLK_BINARY = 8'b11000001; + 194 : TXTSNFTSCOMCLK_BINARY = 8'b11000010; + 195 : TXTSNFTSCOMCLK_BINARY = 8'b11000011; + 196 : TXTSNFTSCOMCLK_BINARY = 8'b11000100; + 197 : TXTSNFTSCOMCLK_BINARY = 8'b11000101; + 198 : TXTSNFTSCOMCLK_BINARY = 8'b11000110; + 199 : TXTSNFTSCOMCLK_BINARY = 8'b11000111; + 200 : TXTSNFTSCOMCLK_BINARY = 8'b11001000; + 201 : TXTSNFTSCOMCLK_BINARY = 8'b11001001; + 202 : TXTSNFTSCOMCLK_BINARY = 8'b11001010; + 203 : TXTSNFTSCOMCLK_BINARY = 8'b11001011; + 204 : TXTSNFTSCOMCLK_BINARY = 8'b11001100; + 205 : TXTSNFTSCOMCLK_BINARY = 8'b11001101; + 206 : TXTSNFTSCOMCLK_BINARY = 8'b11001110; + 207 : TXTSNFTSCOMCLK_BINARY = 8'b11001111; + 208 : TXTSNFTSCOMCLK_BINARY = 8'b11010000; + 209 : TXTSNFTSCOMCLK_BINARY = 8'b11010001; + 210 : TXTSNFTSCOMCLK_BINARY = 8'b11010010; + 211 : TXTSNFTSCOMCLK_BINARY = 8'b11010011; + 212 : TXTSNFTSCOMCLK_BINARY = 8'b11010100; + 213 : TXTSNFTSCOMCLK_BINARY = 8'b11010101; + 214 : TXTSNFTSCOMCLK_BINARY = 8'b11010110; + 215 : TXTSNFTSCOMCLK_BINARY = 8'b11010111; + 216 : TXTSNFTSCOMCLK_BINARY = 8'b11011000; + 217 : TXTSNFTSCOMCLK_BINARY = 8'b11011001; + 218 : TXTSNFTSCOMCLK_BINARY = 8'b11011010; + 219 : TXTSNFTSCOMCLK_BINARY = 8'b11011011; + 220 : TXTSNFTSCOMCLK_BINARY = 8'b11011100; + 221 : TXTSNFTSCOMCLK_BINARY = 8'b11011101; + 222 : TXTSNFTSCOMCLK_BINARY = 8'b11011110; + 223 : TXTSNFTSCOMCLK_BINARY = 8'b11011111; + 224 : TXTSNFTSCOMCLK_BINARY = 8'b11100000; + 225 : TXTSNFTSCOMCLK_BINARY = 8'b11100001; + 226 : TXTSNFTSCOMCLK_BINARY = 8'b11100010; + 227 : TXTSNFTSCOMCLK_BINARY = 8'b11100011; + 228 : TXTSNFTSCOMCLK_BINARY = 8'b11100100; + 229 : TXTSNFTSCOMCLK_BINARY = 8'b11100101; + 230 : TXTSNFTSCOMCLK_BINARY = 8'b11100110; + 231 : TXTSNFTSCOMCLK_BINARY = 8'b11100111; + 232 : TXTSNFTSCOMCLK_BINARY = 8'b11101000; + 233 : TXTSNFTSCOMCLK_BINARY = 8'b11101001; + 234 : TXTSNFTSCOMCLK_BINARY = 8'b11101010; + 235 : TXTSNFTSCOMCLK_BINARY = 8'b11101011; + 236 : TXTSNFTSCOMCLK_BINARY = 8'b11101100; + 237 : TXTSNFTSCOMCLK_BINARY = 8'b11101101; + 238 : TXTSNFTSCOMCLK_BINARY = 8'b11101110; + 239 : TXTSNFTSCOMCLK_BINARY = 8'b11101111; + 240 : TXTSNFTSCOMCLK_BINARY = 8'b11110000; + 241 : TXTSNFTSCOMCLK_BINARY = 8'b11110001; + 242 : TXTSNFTSCOMCLK_BINARY = 8'b11110010; + 243 : TXTSNFTSCOMCLK_BINARY = 8'b11110011; + 244 : TXTSNFTSCOMCLK_BINARY = 8'b11110100; + 245 : TXTSNFTSCOMCLK_BINARY = 8'b11110101; + 246 : TXTSNFTSCOMCLK_BINARY = 8'b11110110; + 247 : TXTSNFTSCOMCLK_BINARY = 8'b11110111; + 248 : TXTSNFTSCOMCLK_BINARY = 8'b11111000; + 249 : TXTSNFTSCOMCLK_BINARY = 8'b11111001; + 250 : TXTSNFTSCOMCLK_BINARY = 8'b11111010; + 251 : TXTSNFTSCOMCLK_BINARY = 8'b11111011; + 252 : TXTSNFTSCOMCLK_BINARY = 8'b11111100; + 253 : TXTSNFTSCOMCLK_BINARY = 8'b11111101; + 254 : TXTSNFTSCOMCLK_BINARY = 8'b11111110; + 255 : TXTSNFTSCOMCLK_BINARY = 8'b11111111; + default : begin + $display("Attribute Syntax Error : The Attribute TXTSNFTSCOMCLK on PCIE_INTERNAL_1_1 instance %m is set to %d. Legal values for this attribute are 0 to 255.", TXTSNFTSCOMCLK); + $finish; + end + endcase + + case (RETRYRAMREADLATENCY) + 0 : RETRYRAMREADLATENCY_BINARY = 3'b000; + 1 : RETRYRAMREADLATENCY_BINARY = 3'b001; + 2 : RETRYRAMREADLATENCY_BINARY = 3'b010; + 3 : RETRYRAMREADLATENCY_BINARY = 3'b011; + 4 : RETRYRAMREADLATENCY_BINARY = 3'b100; + 5 : RETRYRAMREADLATENCY_BINARY = 3'b101; + 6 : RETRYRAMREADLATENCY_BINARY = 3'b110; + 7 : RETRYRAMREADLATENCY_BINARY = 3'b111; + default : begin + $display("Attribute Syntax Error : The Attribute RETRYRAMREADLATENCY on PCIE_INTERNAL_1_1 instance %m is set to %d. Legal values for this attribute are 0 to 7.", RETRYRAMREADLATENCY); + $finish; + end + endcase + + case (RETRYRAMWRITELATENCY) + 0 : RETRYRAMWRITELATENCY_BINARY = 3'b000; + 1 : RETRYRAMWRITELATENCY_BINARY = 3'b001; + 2 : RETRYRAMWRITELATENCY_BINARY = 3'b010; + 3 : RETRYRAMWRITELATENCY_BINARY = 3'b011; + 4 : RETRYRAMWRITELATENCY_BINARY = 3'b100; + 5 : RETRYRAMWRITELATENCY_BINARY = 3'b101; + 6 : RETRYRAMWRITELATENCY_BINARY = 3'b110; + 7 : RETRYRAMWRITELATENCY_BINARY = 3'b111; + default : begin + $display("Attribute Syntax Error : The Attribute RETRYRAMWRITELATENCY on PCIE_INTERNAL_1_1 instance %m is set to %d. Legal values for this attribute are 0 to 7.", RETRYRAMWRITELATENCY); + $finish; + end + endcase + + case (RETRYRAMWIDTH) + 0 : RETRYRAMWIDTH_BINARY = 1'b0; + 1 : RETRYRAMWIDTH_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute RETRYRAMWIDTH on PCIE_INTERNAL_1_1 instance %m is set to %d. Legal values for this attribute are 0 to 1.", RETRYRAMWIDTH); + $finish; + end + endcase + + case (RETRYWRITEPIPE) + "FALSE" : RETRYWRITEPIPE_BINARY = 1'b0; + "TRUE" : RETRYWRITEPIPE_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute RETRYWRITEPIPE on PCIE_INTERNAL_1_1 instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", RETRYWRITEPIPE); + $finish; + end + endcase + + case (RETRYREADADDRPIPE) + "FALSE" : RETRYREADADDRPIPE_BINARY = 1'b0; + "TRUE" : RETRYREADADDRPIPE_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute RETRYREADADDRPIPE on PCIE_INTERNAL_1_1 instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", RETRYREADADDRPIPE); + $finish; + end + endcase + + case (RETRYREADDATAPIPE) + "FALSE" : RETRYREADDATAPIPE_BINARY = 1'b0; + "TRUE" : RETRYREADDATAPIPE_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute RETRYREADDATAPIPE on PCIE_INTERNAL_1_1 instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", RETRYREADDATAPIPE); + $finish; + end + endcase + + case (XLINKSUPPORTED) + "FALSE" : XLINKSUPPORTED_BINARY = 1'b0; + "TRUE" : XLINKSUPPORTED_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute XLINKSUPPORTED on PCIE_INTERNAL_1_1 instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", XLINKSUPPORTED); + $finish; + end + endcase + + case (INFINITECOMPLETIONS) + "FALSE" : INFINITECOMPLETIONS_BINARY = 1'b0; + "TRUE" : INFINITECOMPLETIONS_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute INFINITECOMPLETIONS on PCIE_INTERNAL_1_1 instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", INFINITECOMPLETIONS); + $finish; + end + endcase + + case (TLRAMREADLATENCY) + 0 : TLRAMREADLATENCY_BINARY = 3'b000; + 1 : TLRAMREADLATENCY_BINARY = 3'b001; + 2 : TLRAMREADLATENCY_BINARY = 3'b010; + 3 : TLRAMREADLATENCY_BINARY = 3'b011; + 4 : TLRAMREADLATENCY_BINARY = 3'b100; + 5 : TLRAMREADLATENCY_BINARY = 3'b101; + 6 : TLRAMREADLATENCY_BINARY = 3'b110; + 7 : TLRAMREADLATENCY_BINARY = 3'b111; + default : begin + $display("Attribute Syntax Error : The Attribute TLRAMREADLATENCY on PCIE_INTERNAL_1_1 instance %m is set to %d. Legal values for this attribute are 0 to 7.", TLRAMREADLATENCY); + $finish; + end + endcase + + case (TLRAMWRITELATENCY) + 0 : TLRAMWRITELATENCY_BINARY = 3'b000; + 1 : TLRAMWRITELATENCY_BINARY = 3'b001; + 2 : TLRAMWRITELATENCY_BINARY = 3'b010; + 3 : TLRAMWRITELATENCY_BINARY = 3'b011; + 4 : TLRAMWRITELATENCY_BINARY = 3'b100; + 5 : TLRAMWRITELATENCY_BINARY = 3'b101; + 6 : TLRAMWRITELATENCY_BINARY = 3'b110; + 7 : TLRAMWRITELATENCY_BINARY = 3'b111; + default : begin + $display("Attribute Syntax Error : The Attribute TLRAMWRITELATENCY on PCIE_INTERNAL_1_1 instance %m is set to %d. Legal values for this attribute are 0 to 7.", TLRAMWRITELATENCY); + $finish; + end + endcase + + case (TLRAMWIDTH) + 0 : TLRAMWIDTH_BINARY = 1'b0; + 1 : TLRAMWIDTH_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute TLRAMWIDTH on PCIE_INTERNAL_1_1 instance %m is set to %d. Legal values for this attribute are 0 to 1.", TLRAMWIDTH); + $finish; + end + endcase + + case (RAMSHARETXRX) + "FALSE" : RAMSHARETXRX_BINARY = 1'b0; + "TRUE" : RAMSHARETXRX_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute RAMSHARETXRX on PCIE_INTERNAL_1_1 instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", RAMSHARETXRX); + $finish; + end + endcase + + case (L0SEXITLATENCY) + 0 : L0SEXITLATENCY_BINARY = 3'b000; + 1 : L0SEXITLATENCY_BINARY = 3'b001; + 2 : L0SEXITLATENCY_BINARY = 3'b010; + 3 : L0SEXITLATENCY_BINARY = 3'b011; + 4 : L0SEXITLATENCY_BINARY = 3'b100; + 5 : L0SEXITLATENCY_BINARY = 3'b101; + 6 : L0SEXITLATENCY_BINARY = 3'b110; + 7 : L0SEXITLATENCY_BINARY = 3'b111; + default : begin + $display("Attribute Syntax Error : The Attribute L0SEXITLATENCY on PCIE_INTERNAL_1_1 instance %m is set to %d. Legal values for this attribute are 0 to 7.", L0SEXITLATENCY); + $finish; + end + endcase + + case (L0SEXITLATENCYCOMCLK) + 0 : L0SEXITLATENCYCOMCLK_BINARY = 3'b000; + 1 : L0SEXITLATENCYCOMCLK_BINARY = 3'b001; + 2 : L0SEXITLATENCYCOMCLK_BINARY = 3'b010; + 3 : L0SEXITLATENCYCOMCLK_BINARY = 3'b011; + 4 : L0SEXITLATENCYCOMCLK_BINARY = 3'b100; + 5 : L0SEXITLATENCYCOMCLK_BINARY = 3'b101; + 6 : L0SEXITLATENCYCOMCLK_BINARY = 3'b110; + 7 : L0SEXITLATENCYCOMCLK_BINARY = 3'b111; + default : begin + $display("Attribute Syntax Error : The Attribute L0SEXITLATENCYCOMCLK on PCIE_INTERNAL_1_1 instance %m is set to %d. Legal values for this attribute are 0 to 7.", L0SEXITLATENCYCOMCLK); + $finish; + end + endcase + + case (L1EXITLATENCY) + 0 : L1EXITLATENCY_BINARY = 3'b000; + 1 : L1EXITLATENCY_BINARY = 3'b001; + 2 : L1EXITLATENCY_BINARY = 3'b010; + 3 : L1EXITLATENCY_BINARY = 3'b011; + 4 : L1EXITLATENCY_BINARY = 3'b100; + 5 : L1EXITLATENCY_BINARY = 3'b101; + 6 : L1EXITLATENCY_BINARY = 3'b110; + 7 : L1EXITLATENCY_BINARY = 3'b111; + default : begin + $display("Attribute Syntax Error : The Attribute L1EXITLATENCY on PCIE_INTERNAL_1_1 instance %m is set to %d. Legal values for this attribute are 0 to 7.", L1EXITLATENCY); + $finish; + end + endcase + + case (L1EXITLATENCYCOMCLK) + 0 : L1EXITLATENCYCOMCLK_BINARY = 3'b000; + 1 : L1EXITLATENCYCOMCLK_BINARY = 3'b001; + 2 : L1EXITLATENCYCOMCLK_BINARY = 3'b010; + 3 : L1EXITLATENCYCOMCLK_BINARY = 3'b011; + 4 : L1EXITLATENCYCOMCLK_BINARY = 3'b100; + 5 : L1EXITLATENCYCOMCLK_BINARY = 3'b101; + 6 : L1EXITLATENCYCOMCLK_BINARY = 3'b110; + 7 : L1EXITLATENCYCOMCLK_BINARY = 3'b111; + default : begin + $display("Attribute Syntax Error : The Attribute L1EXITLATENCYCOMCLK on PCIE_INTERNAL_1_1 instance %m is set to %d. Legal values for this attribute are 0 to 7.", L1EXITLATENCYCOMCLK); + $finish; + end + endcase + + case (DUALCORESLAVE) + "FALSE" : DUALCORESLAVE_BINARY = 1'b0; + "TRUE" : DUALCORESLAVE_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute DUALCORESLAVE on PCIE_INTERNAL_1_1 instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", DUALCORESLAVE); + $finish; + end + endcase + + case (DUALCOREENABLE) + "FALSE" : DUALCOREENABLE_BINARY = 1'b0; + "TRUE" : DUALCOREENABLE_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute DUALCOREENABLE on PCIE_INTERNAL_1_1 instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", DUALCOREENABLE); + $finish; + end + endcase + + case (DUALROLECFGCNTRLROOTEPN) + 0 : DUALROLECFGCNTRLROOTEPN_BINARY = 1'b0; + 1 : DUALROLECFGCNTRLROOTEPN_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute DUALROLECFGCNTRLROOTEPN on PCIE_INTERNAL_1_1 instance %m is set to %d. Legal values for this attribute are 0 to 1.", DUALROLECFGCNTRLROOTEPN); + $finish; + end + endcase + + case (RXREADADDRPIPE) + "FALSE" : RXREADADDRPIPE_BINARY = 1'b0; + "TRUE" : RXREADADDRPIPE_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute RXREADADDRPIPE on PCIE_INTERNAL_1_1 instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", RXREADADDRPIPE); + $finish; + end + endcase + + case (RXREADDATAPIPE) + "FALSE" : RXREADDATAPIPE_BINARY = 1'b0; + "TRUE" : RXREADDATAPIPE_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute RXREADDATAPIPE on PCIE_INTERNAL_1_1 instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", RXREADDATAPIPE); + $finish; + end + endcase + + case (TXWRITEPIPE) + "FALSE" : TXWRITEPIPE_BINARY = 1'b0; + "TRUE" : TXWRITEPIPE_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute TXWRITEPIPE on PCIE_INTERNAL_1_1 instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", TXWRITEPIPE); + $finish; + end + endcase + + case (TXREADADDRPIPE) + "FALSE" : TXREADADDRPIPE_BINARY = 1'b0; + "TRUE" : TXREADADDRPIPE_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute TXREADADDRPIPE on PCIE_INTERNAL_1_1 instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", TXREADADDRPIPE); + $finish; + end + endcase + + case (TXREADDATAPIPE) + "FALSE" : TXREADDATAPIPE_BINARY = 1'b0; + "TRUE" : TXREADDATAPIPE_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute TXREADDATAPIPE on PCIE_INTERNAL_1_1 instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", TXREADDATAPIPE); + $finish; + end + endcase + + case (RXWRITEPIPE) + "FALSE" : RXWRITEPIPE_BINARY = 1'b0; + "TRUE" : RXWRITEPIPE_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute RXWRITEPIPE on PCIE_INTERNAL_1_1 instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", RXWRITEPIPE); + $finish; + end + endcase + + case (LLKBYPASS) + "FALSE" : LLKBYPASS_BINARY = 1'b0; + "TRUE" : LLKBYPASS_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute LLKBYPASS on PCIE_INTERNAL_1_1 instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", LLKBYPASS); + $finish; + end + endcase + + case (PCIEREVISION) + 0 : PCIEREVISION_BINARY = 1'b0; + 1 : PCIEREVISION_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute PCIEREVISION on PCIE_INTERNAL_1_1 instance %m is set to %d. Legal values for this attribute are 0 to 1.", PCIEREVISION); + $finish; + end + endcase + + case (SELECTDLLIF) + "FALSE" : SELECTDLLIF_BINARY = 1'b0; + "TRUE" : SELECTDLLIF_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute SELECTDLLIF on PCIE_INTERNAL_1_1 instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", SELECTDLLIF); + $finish; + end + endcase + + case (SELECTASMODE) + "FALSE" : SELECTASMODE_BINARY = 1'b0; + "TRUE" : SELECTASMODE_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute SELECTASMODE on PCIE_INTERNAL_1_1 instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", SELECTASMODE); + $finish; + end + endcase + + case (ISSWITCH) + "FALSE" : ISSWITCH_BINARY = 1'b0; + "TRUE" : ISSWITCH_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute ISSWITCH on PCIE_INTERNAL_1_1 instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", ISSWITCH); + $finish; + end + endcase + + case (UPSTREAMFACING) + "FALSE" : UPSTREAMFACING_BINARY = 1'b0; + "TRUE" : UPSTREAMFACING_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute UPSTREAMFACING on PCIE_INTERNAL_1_1 instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", UPSTREAMFACING); + $finish; + end + endcase + + case (SLOTIMPLEMENTED) + "FALSE" : SLOTIMPLEMENTED_BINARY = 1'b0; + "TRUE" : SLOTIMPLEMENTED_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute SLOTIMPLEMENTED on PCIE_INTERNAL_1_1 instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", SLOTIMPLEMENTED); + $finish; + end + endcase + + case (BAR0EXIST) + "FALSE" : BAR0EXIST_BINARY = 1'b0; + "TRUE" : BAR0EXIST_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute BAR0EXIST on PCIE_INTERNAL_1_1 instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", BAR0EXIST); + $finish; + end + endcase + + case (BAR1EXIST) + "FALSE" : BAR1EXIST_BINARY = 1'b0; + "TRUE" : BAR1EXIST_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute BAR1EXIST on PCIE_INTERNAL_1_1 instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", BAR1EXIST); + $finish; + end + endcase + + case (BAR2EXIST) + "FALSE" : BAR2EXIST_BINARY = 1'b0; + "TRUE" : BAR2EXIST_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute BAR2EXIST on PCIE_INTERNAL_1_1 instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", BAR2EXIST); + $finish; + end + endcase + + case (BAR3EXIST) + "FALSE" : BAR3EXIST_BINARY = 1'b0; + "TRUE" : BAR3EXIST_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute BAR3EXIST on PCIE_INTERNAL_1_1 instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", BAR3EXIST); + $finish; + end + endcase + + case (BAR4EXIST) + "FALSE" : BAR4EXIST_BINARY = 1'b0; + "TRUE" : BAR4EXIST_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute BAR4EXIST on PCIE_INTERNAL_1_1 instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", BAR4EXIST); + $finish; + end + endcase + + case (BAR5EXIST) + "FALSE" : BAR5EXIST_BINARY = 1'b0; + "TRUE" : BAR5EXIST_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute BAR5EXIST on PCIE_INTERNAL_1_1 instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", BAR5EXIST); + $finish; + end + endcase + + case (BAR0ADDRWIDTH) + 0 : BAR0ADDRWIDTH_BINARY = 1'b0; + 1 : BAR0ADDRWIDTH_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute BAR0ADDRWIDTH on PCIE_INTERNAL_1_1 instance %m is set to %d. Legal values for this attribute are 0 to 1.", BAR0ADDRWIDTH); + $finish; + end + endcase + + case (BAR1ADDRWIDTH) + 0 : BAR1ADDRWIDTH_BINARY = 1'b0; + 1 : BAR1ADDRWIDTH_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute BAR1ADDRWIDTH on PCIE_INTERNAL_1_1 instance %m is set to %d. Legal values for this attribute are 0 to 1.", BAR1ADDRWIDTH); + $finish; + end + endcase + + case (BAR2ADDRWIDTH) + 0 : BAR2ADDRWIDTH_BINARY = 1'b0; + 1 : BAR2ADDRWIDTH_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute BAR2ADDRWIDTH on PCIE_INTERNAL_1_1 instance %m is set to %d. Legal values for this attribute are 0 to 1.", BAR2ADDRWIDTH); + $finish; + end + endcase + + case (BAR3ADDRWIDTH) + 0 : BAR3ADDRWIDTH_BINARY = 1'b0; + 1 : BAR3ADDRWIDTH_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute BAR3ADDRWIDTH on PCIE_INTERNAL_1_1 instance %m is set to %d. Legal values for this attribute are 0 to 1.", BAR3ADDRWIDTH); + $finish; + end + endcase + + case (BAR4ADDRWIDTH) + 0 : BAR4ADDRWIDTH_BINARY = 1'b0; + 1 : BAR4ADDRWIDTH_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute BAR4ADDRWIDTH on PCIE_INTERNAL_1_1 instance %m is set to %d. Legal values for this attribute are 0 to 1.", BAR4ADDRWIDTH); + $finish; + end + endcase + + case (BAR0PREFETCHABLE) + "FALSE" : BAR0PREFETCHABLE_BINARY = 1'b0; + "TRUE" : BAR0PREFETCHABLE_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute BAR0PREFETCHABLE on PCIE_INTERNAL_1_1 instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", BAR0PREFETCHABLE); + $finish; + end + endcase + + case (BAR1PREFETCHABLE) + "FALSE" : BAR1PREFETCHABLE_BINARY = 1'b0; + "TRUE" : BAR1PREFETCHABLE_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute BAR1PREFETCHABLE on PCIE_INTERNAL_1_1 instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", BAR1PREFETCHABLE); + $finish; + end + endcase + + case (BAR2PREFETCHABLE) + "FALSE" : BAR2PREFETCHABLE_BINARY = 1'b0; + "TRUE" : BAR2PREFETCHABLE_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute BAR2PREFETCHABLE on PCIE_INTERNAL_1_1 instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", BAR2PREFETCHABLE); + $finish; + end + endcase + + case (BAR3PREFETCHABLE) + "FALSE" : BAR3PREFETCHABLE_BINARY = 1'b0; + "TRUE" : BAR3PREFETCHABLE_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute BAR3PREFETCHABLE on PCIE_INTERNAL_1_1 instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", BAR3PREFETCHABLE); + $finish; + end + endcase + + case (BAR4PREFETCHABLE) + "FALSE" : BAR4PREFETCHABLE_BINARY = 1'b0; + "TRUE" : BAR4PREFETCHABLE_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute BAR4PREFETCHABLE on PCIE_INTERNAL_1_1 instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", BAR4PREFETCHABLE); + $finish; + end + endcase + + case (BAR5PREFETCHABLE) + "FALSE" : BAR5PREFETCHABLE_BINARY = 1'b0; + "TRUE" : BAR5PREFETCHABLE_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute BAR5PREFETCHABLE on PCIE_INTERNAL_1_1 instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", BAR5PREFETCHABLE); + $finish; + end + endcase + + case (BAR0IOMEMN) + 0 : BAR0IOMEMN_BINARY = 1'b0; + 1 : BAR0IOMEMN_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute BAR0IOMEMN on PCIE_INTERNAL_1_1 instance %m is set to %d. Legal values for this attribute are 0 to 1.", BAR0IOMEMN); + $finish; + end + endcase + + case (BAR1IOMEMN) + 0 : BAR1IOMEMN_BINARY = 1'b0; + 1 : BAR1IOMEMN_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute BAR1IOMEMN on PCIE_INTERNAL_1_1 instance %m is set to %d. Legal values for this attribute are 0 to 1.", BAR1IOMEMN); + $finish; + end + endcase + + case (BAR2IOMEMN) + 0 : BAR2IOMEMN_BINARY = 1'b0; + 1 : BAR2IOMEMN_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute BAR2IOMEMN on PCIE_INTERNAL_1_1 instance %m is set to %d. Legal values for this attribute are 0 to 1.", BAR2IOMEMN); + $finish; + end + endcase + + case (BAR3IOMEMN) + 0 : BAR3IOMEMN_BINARY = 1'b0; + 1 : BAR3IOMEMN_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute BAR3IOMEMN on PCIE_INTERNAL_1_1 instance %m is set to %d. Legal values for this attribute are 0 to 1.", BAR3IOMEMN); + $finish; + end + endcase + + case (BAR4IOMEMN) + 0 : BAR4IOMEMN_BINARY = 1'b0; + 1 : BAR4IOMEMN_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute BAR4IOMEMN on PCIE_INTERNAL_1_1 instance %m is set to %d. Legal values for this attribute are 0 to 1.", BAR4IOMEMN); + $finish; + end + endcase + + case (BAR5IOMEMN) + 0 : BAR5IOMEMN_BINARY = 1'b0; + 1 : BAR5IOMEMN_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute BAR5IOMEMN on PCIE_INTERNAL_1_1 instance %m is set to %d. Legal values for this attribute are 0 to 1.", BAR5IOMEMN); + $finish; + end + endcase + + case (XPMAXPAYLOAD) + 0 : XPMAXPAYLOAD_BINARY = 3'b000; + 1 : XPMAXPAYLOAD_BINARY = 3'b001; + 2 : XPMAXPAYLOAD_BINARY = 3'b010; + 3 : XPMAXPAYLOAD_BINARY = 3'b011; + 4 : XPMAXPAYLOAD_BINARY = 3'b100; + 5 : XPMAXPAYLOAD_BINARY = 3'b101; + 6 : XPMAXPAYLOAD_BINARY = 3'b110; + 7 : XPMAXPAYLOAD_BINARY = 3'b111; + default : begin + $display("Attribute Syntax Error : The Attribute XPMAXPAYLOAD on PCIE_INTERNAL_1_1 instance %m is set to %d. Legal values for this attribute are 0 to 7.", XPMAXPAYLOAD); + $finish; + end + endcase + + case (XPRCBCONTROL) + 0 : XPRCBCONTROL_BINARY = 1'b0; + 1 : XPRCBCONTROL_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute XPRCBCONTROL on PCIE_INTERNAL_1_1 instance %m is set to %d. Legal values for this attribute are 0 to 1.", XPRCBCONTROL); + $finish; + end + endcase + + case (LOWPRIORITYVCCOUNT) + 0 : LOWPRIORITYVCCOUNT_BINARY = 3'b000; + 1 : LOWPRIORITYVCCOUNT_BINARY = 3'b001; + 2 : LOWPRIORITYVCCOUNT_BINARY = 3'b010; + 3 : LOWPRIORITYVCCOUNT_BINARY = 3'b011; + 4 : LOWPRIORITYVCCOUNT_BINARY = 3'b100; + 5 : LOWPRIORITYVCCOUNT_BINARY = 3'b101; + 6 : LOWPRIORITYVCCOUNT_BINARY = 3'b110; + 7 : LOWPRIORITYVCCOUNT_BINARY = 3'b111; + default : begin + $display("Attribute Syntax Error : The Attribute LOWPRIORITYVCCOUNT on PCIE_INTERNAL_1_1 instance %m is set to %d. Legal values for this attribute are 0 to 7.", LOWPRIORITYVCCOUNT); + $finish; + end + endcase + + case (PMCAPABILITYDSI) + "FALSE" : PMCAPABILITYDSI_BINARY = 1'b0; + "TRUE" : PMCAPABILITYDSI_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute PMCAPABILITYDSI on PCIE_INTERNAL_1_1 instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", PMCAPABILITYDSI); + $finish; + end + endcase + + case (PMCAPABILITYD1SUPPORT) + "FALSE" : PMCAPABILITYD1SUPPORT_BINARY = 1'b0; + "TRUE" : PMCAPABILITYD1SUPPORT_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute PMCAPABILITYD1SUPPORT on PCIE_INTERNAL_1_1 instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", PMCAPABILITYD1SUPPORT); + $finish; + end + endcase + + case (PMCAPABILITYD2SUPPORT) + "FALSE" : PMCAPABILITYD2SUPPORT_BINARY = 1'b0; + "TRUE" : PMCAPABILITYD2SUPPORT_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute PMCAPABILITYD2SUPPORT on PCIE_INTERNAL_1_1 instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", PMCAPABILITYD2SUPPORT); + $finish; + end + endcase + + case (PMDATASCALE0) + 0 : PMDATASCALE0_BINARY = 2'b00; + 1 : PMDATASCALE0_BINARY = 2'b01; + 2 : PMDATASCALE0_BINARY = 2'b10; + 3 : PMDATASCALE0_BINARY = 2'b11; + default : begin + $display("Attribute Syntax Error : The Attribute PMDATASCALE0 on PCIE_INTERNAL_1_1 instance %m is set to %d. Legal values for this attribute are 0 to 3.", PMDATASCALE0); + $finish; + end + endcase + + case (PMDATASCALE1) + 0 : PMDATASCALE1_BINARY = 2'b00; + 1 : PMDATASCALE1_BINARY = 2'b01; + 2 : PMDATASCALE1_BINARY = 2'b10; + 3 : PMDATASCALE1_BINARY = 2'b11; + default : begin + $display("Attribute Syntax Error : The Attribute PMDATASCALE1 on PCIE_INTERNAL_1_1 instance %m is set to %d. Legal values for this attribute are 0 to 3.", PMDATASCALE1); + $finish; + end + endcase + + case (PMDATASCALE2) + 0 : PMDATASCALE2_BINARY = 2'b00; + 1 : PMDATASCALE2_BINARY = 2'b01; + 2 : PMDATASCALE2_BINARY = 2'b10; + 3 : PMDATASCALE2_BINARY = 2'b11; + default : begin + $display("Attribute Syntax Error : The Attribute PMDATASCALE2 on PCIE_INTERNAL_1_1 instance %m is set to %d. Legal values for this attribute are 0 to 3.", PMDATASCALE2); + $finish; + end + endcase + + case (PMDATASCALE3) + 0 : PMDATASCALE3_BINARY = 2'b00; + 1 : PMDATASCALE3_BINARY = 2'b01; + 2 : PMDATASCALE3_BINARY = 2'b10; + 3 : PMDATASCALE3_BINARY = 2'b11; + default : begin + $display("Attribute Syntax Error : The Attribute PMDATASCALE3 on PCIE_INTERNAL_1_1 instance %m is set to %d. Legal values for this attribute are 0 to 3.", PMDATASCALE3); + $finish; + end + endcase + + case (PMDATASCALE4) + 0 : PMDATASCALE4_BINARY = 2'b00; + 1 : PMDATASCALE4_BINARY = 2'b01; + 2 : PMDATASCALE4_BINARY = 2'b10; + 3 : PMDATASCALE4_BINARY = 2'b11; + default : begin + $display("Attribute Syntax Error : The Attribute PMDATASCALE4 on PCIE_INTERNAL_1_1 instance %m is set to %d. Legal values for this attribute are 0 to 3.", PMDATASCALE4); + $finish; + end + endcase + + case (PMDATASCALE5) + 0 : PMDATASCALE5_BINARY = 2'b00; + 1 : PMDATASCALE5_BINARY = 2'b01; + 2 : PMDATASCALE5_BINARY = 2'b10; + 3 : PMDATASCALE5_BINARY = 2'b11; + default : begin + $display("Attribute Syntax Error : The Attribute PMDATASCALE5 on PCIE_INTERNAL_1_1 instance %m is set to %d. Legal values for this attribute are 0 to 3.", PMDATASCALE5); + $finish; + end + endcase + + case (PMDATASCALE6) + 0 : PMDATASCALE6_BINARY = 2'b00; + 1 : PMDATASCALE6_BINARY = 2'b01; + 2 : PMDATASCALE6_BINARY = 2'b10; + 3 : PMDATASCALE6_BINARY = 2'b11; + default : begin + $display("Attribute Syntax Error : The Attribute PMDATASCALE6 on PCIE_INTERNAL_1_1 instance %m is set to %d. Legal values for this attribute are 0 to 3.", PMDATASCALE6); + $finish; + end + endcase + + case (PMDATASCALE7) + 0 : PMDATASCALE7_BINARY = 2'b00; + 1 : PMDATASCALE7_BINARY = 2'b01; + 2 : PMDATASCALE7_BINARY = 2'b10; + 3 : PMDATASCALE7_BINARY = 2'b11; + default : begin + $display("Attribute Syntax Error : The Attribute PMDATASCALE7 on PCIE_INTERNAL_1_1 instance %m is set to %d. Legal values for this attribute are 0 to 3.", PMDATASCALE7); + $finish; + end + endcase + + case (PMDATASCALE8) + 0 : PMDATASCALE8_BINARY = 2'b00; + 1 : PMDATASCALE8_BINARY = 2'b01; + 2 : PMDATASCALE8_BINARY = 2'b10; + 3 : PMDATASCALE8_BINARY = 2'b11; + default : begin + $display("Attribute Syntax Error : The Attribute PMDATASCALE8 on PCIE_INTERNAL_1_1 instance %m is set to %d. Legal values for this attribute are 0 to 3.", PMDATASCALE8); + $finish; + end + endcase + + case (PCIECAPABILITYSLOTIMPL) + "FALSE" : PCIECAPABILITYSLOTIMPL_BINARY = 1'b0; + "TRUE" : PCIECAPABILITYSLOTIMPL_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute PCIECAPABILITYSLOTIMPL on PCIE_INTERNAL_1_1 instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", PCIECAPABILITYSLOTIMPL); + $finish; + end + endcase + + case (LINKSTATUSSLOTCLOCKCONFIG) + "FALSE" : LINKSTATUSSLOTCLOCKCONFIG_BINARY = 1'b0; + "TRUE" : LINKSTATUSSLOTCLOCKCONFIG_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute LINKSTATUSSLOTCLOCKCONFIG on PCIE_INTERNAL_1_1 instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", LINKSTATUSSLOTCLOCKCONFIG); + $finish; + end + endcase + + case (SLOTCAPABILITYATTBUTTONPRESENT) + "FALSE" : SLOTCAPABILITYATTBUTTONPRESENT_BINARY = 1'b0; + "TRUE" : SLOTCAPABILITYATTBUTTONPRESENT_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute SLOTCAPABILITYATTBUTTONPRESENT on PCIE_INTERNAL_1_1 instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", SLOTCAPABILITYATTBUTTONPRESENT); + $finish; + end + endcase + + case (SLOTCAPABILITYPOWERCONTROLLERPRESENT) + "FALSE" : SLOTCAPABILITYPOWERCONTROLLERPRESENT_BINARY = 1'b0; + "TRUE" : SLOTCAPABILITYPOWERCONTROLLERPRESENT_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute SLOTCAPABILITYPOWERCONTROLLERPRESENT on PCIE_INTERNAL_1_1 instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", SLOTCAPABILITYPOWERCONTROLLERPRESENT); + $finish; + end + endcase + + case (SLOTCAPABILITYMSLSENSORPRESENT) + "FALSE" : SLOTCAPABILITYMSLSENSORPRESENT_BINARY = 1'b0; + "TRUE" : SLOTCAPABILITYMSLSENSORPRESENT_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute SLOTCAPABILITYMSLSENSORPRESENT on PCIE_INTERNAL_1_1 instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", SLOTCAPABILITYMSLSENSORPRESENT); + $finish; + end + endcase + + case (SLOTCAPABILITYATTINDICATORPRESENT) + "FALSE" : SLOTCAPABILITYATTINDICATORPRESENT_BINARY = 1'b0; + "TRUE" : SLOTCAPABILITYATTINDICATORPRESENT_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute SLOTCAPABILITYATTINDICATORPRESENT on PCIE_INTERNAL_1_1 instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", SLOTCAPABILITYATTINDICATORPRESENT); + $finish; + end + endcase + + case (SLOTCAPABILITYPOWERINDICATORPRESENT) + "FALSE" : SLOTCAPABILITYPOWERINDICATORPRESENT_BINARY = 1'b0; + "TRUE" : SLOTCAPABILITYPOWERINDICATORPRESENT_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute SLOTCAPABILITYPOWERINDICATORPRESENT on PCIE_INTERNAL_1_1 instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", SLOTCAPABILITYPOWERINDICATORPRESENT); + $finish; + end + endcase + + case (SLOTCAPABILITYHOTPLUGSURPRISE) + "FALSE" : SLOTCAPABILITYHOTPLUGSURPRISE_BINARY = 1'b0; + "TRUE" : SLOTCAPABILITYHOTPLUGSURPRISE_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute SLOTCAPABILITYHOTPLUGSURPRISE on PCIE_INTERNAL_1_1 instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", SLOTCAPABILITYHOTPLUGSURPRISE); + $finish; + end + endcase + + case (SLOTCAPABILITYHOTPLUGCAPABLE) + "FALSE" : SLOTCAPABILITYHOTPLUGCAPABLE_BINARY = 1'b0; + "TRUE" : SLOTCAPABILITYHOTPLUGCAPABLE_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute SLOTCAPABILITYHOTPLUGCAPABLE on PCIE_INTERNAL_1_1 instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", SLOTCAPABILITYHOTPLUGCAPABLE); + $finish; + end + endcase + + case (AERCAPABILITYECRCGENCAPABLE) + "FALSE" : AERCAPABILITYECRCGENCAPABLE_BINARY = 1'b0; + "TRUE" : AERCAPABILITYECRCGENCAPABLE_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute AERCAPABILITYECRCGENCAPABLE on PCIE_INTERNAL_1_1 instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", AERCAPABILITYECRCGENCAPABLE); + $finish; + end + endcase + + case (AERCAPABILITYECRCCHECKCAPABLE) + "FALSE" : AERCAPABILITYECRCCHECKCAPABLE_BINARY = 1'b0; + "TRUE" : AERCAPABILITYECRCCHECKCAPABLE_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute AERCAPABILITYECRCCHECKCAPABLE on PCIE_INTERNAL_1_1 instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", AERCAPABILITYECRCCHECKCAPABLE); + $finish; + end + endcase + + case (PBCAPABILITYSYSTEMALLOCATED) + "FALSE" : PBCAPABILITYSYSTEMALLOCATED_BINARY = 1'b0; + "TRUE" : PBCAPABILITYSYSTEMALLOCATED_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute PBCAPABILITYSYSTEMALLOCATED on PCIE_INTERNAL_1_1 instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", PBCAPABILITYSYSTEMALLOCATED); + $finish; + end + endcase + + case (RESETMODE) + "FALSE" : RESETMODE_BINARY = 1'b0; + "TRUE" : RESETMODE_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute RESETMODE on PCIE_INTERNAL_1_1 instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", RESETMODE); + $finish; + end + endcase + + case (CLKDIVIDED) + "FALSE" : CLKDIVIDED_BINARY = 1'b0; + "TRUE" : CLKDIVIDED_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute CLKDIVIDED on PCIE_INTERNAL_1_1 instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", CLKDIVIDED); + $finish; + end + endcase + +end + +wire BUSMASTERENABLE_delay; +wire CRMDOHOTRESETN_delay; +wire CRMPWRSOFTRESETN_delay; +wire CRMRXHOTRESETN_delay; +wire DLLTXPMDLLPOUTSTANDING_delay; +wire INTERRUPTDISABLE_delay; +wire IOSPACEENABLE_delay; +wire L0ASAUTONOMOUSINITCOMPLETED_delay; +wire L0CFGLOOPBACKACK_delay; +wire L0CORRERRMSGRCVD_delay; +wire L0DLLASTXSTATE_delay; +wire L0DLLRXACKOUTSTANDING_delay; +wire L0DLLTXNONFCOUTSTANDING_delay; +wire L0DLLTXOUTSTANDING_delay; +wire L0FATALERRMSGRCVD_delay; +wire L0FIRSTCFGWRITEOCCURRED_delay; +wire L0FWDCORRERROUT_delay; +wire L0FWDFATALERROUT_delay; +wire L0FWDNONFATALERROUT_delay; +wire L0MACENTEREDL0_delay; +wire L0MACLINKTRAINING_delay; +wire L0MACLINKUP_delay; +wire L0MACNEWSTATEACK_delay; +wire L0MACRXL0SSTATE_delay; +wire L0MACUPSTREAMDOWNSTREAM_delay; +wire L0MSIENABLE0_delay; +wire L0NONFATALERRMSGRCVD_delay; +wire L0PMEACK_delay; +wire L0PMEEN_delay; +wire L0PMEREQOUT_delay; +wire L0POWERCONTROLLERCONTROL_delay; +wire L0PWRINHIBITTRANSFERS_delay; +wire L0PWRL1STATE_delay; +wire L0PWRL23READYDEVICE_delay; +wire L0PWRL23READYSTATE_delay; +wire L0PWRTURNOFFREQ_delay; +wire L0PWRTXL0SSTATE_delay; +wire L0RECEIVEDASSERTINTALEGACYINT_delay; +wire L0RECEIVEDASSERTINTBLEGACYINT_delay; +wire L0RECEIVEDASSERTINTCLEGACYINT_delay; +wire L0RECEIVEDASSERTINTDLEGACYINT_delay; +wire L0RECEIVEDDEASSERTINTALEGACYINT_delay; +wire L0RECEIVEDDEASSERTINTBLEGACYINT_delay; +wire L0RECEIVEDDEASSERTINTCLEGACYINT_delay; +wire L0RECEIVEDDEASSERTINTDLEGACYINT_delay; +wire L0RXBEACON_delay; +wire L0RXDLLPM_delay; +wire L0RXDLLSBFCUPDATE_delay; +wire L0RXDLLTLPECRCOK_delay; +wire L0STATSCFGOTHERRECEIVED_delay; +wire L0STATSCFGOTHERTRANSMITTED_delay; +wire L0STATSCFGRECEIVED_delay; +wire L0STATSCFGTRANSMITTED_delay; +wire L0STATSDLLPRECEIVED_delay; +wire L0STATSDLLPTRANSMITTED_delay; +wire L0STATSOSRECEIVED_delay; +wire L0STATSOSTRANSMITTED_delay; +wire L0STATSTLPRECEIVED_delay; +wire L0STATSTLPTRANSMITTED_delay; +wire L0TOGGLEELECTROMECHANICALINTERLOCK_delay; +wire L0TXDLLPMUPDATED_delay; +wire L0TXDLLSBFCUPDATED_delay; +wire L0UNLOCKRECEIVED_delay; +wire LLKRX4DWHEADERN_delay; +wire LLKRXCHCONFIGAVAILABLEN_delay; +wire LLKRXCHCONFIGPARTIALN_delay; +wire LLKRXECRCBADN_delay; +wire LLKRXEOFN_delay; +wire LLKRXEOPN_delay; +wire LLKRXSOFN_delay; +wire LLKRXSOPN_delay; +wire LLKRXSRCDSCN_delay; +wire LLKRXSRCLASTREQN_delay; +wire LLKRXSRCRDYN_delay; +wire LLKTXCONFIGREADYN_delay; +wire LLKTXDSTRDYN_delay; +wire MEMSPACEENABLE_delay; +wire MIMDLLBREN_delay; +wire MIMDLLBWEN_delay; +wire MIMRXBREN_delay; +wire MIMRXBWEN_delay; +wire MIMTXBREN_delay; +wire MIMTXBWEN_delay; +wire PARITYERRORRESPONSE_delay; +wire PIPEDESKEWLANESL0_delay; +wire PIPEDESKEWLANESL1_delay; +wire PIPEDESKEWLANESL2_delay; +wire PIPEDESKEWLANESL3_delay; +wire PIPEDESKEWLANESL4_delay; +wire PIPEDESKEWLANESL5_delay; +wire PIPEDESKEWLANESL6_delay; +wire PIPEDESKEWLANESL7_delay; +wire PIPERESETL0_delay; +wire PIPERESETL1_delay; +wire PIPERESETL2_delay; +wire PIPERESETL3_delay; +wire PIPERESETL4_delay; +wire PIPERESETL5_delay; +wire PIPERESETL6_delay; +wire PIPERESETL7_delay; +wire PIPERXPOLARITYL0_delay; +wire PIPERXPOLARITYL1_delay; +wire PIPERXPOLARITYL2_delay; +wire PIPERXPOLARITYL3_delay; +wire PIPERXPOLARITYL4_delay; +wire PIPERXPOLARITYL5_delay; +wire PIPERXPOLARITYL6_delay; +wire PIPERXPOLARITYL7_delay; +wire PIPETXCOMPLIANCEL0_delay; +wire PIPETXCOMPLIANCEL1_delay; +wire PIPETXCOMPLIANCEL2_delay; +wire PIPETXCOMPLIANCEL3_delay; +wire PIPETXCOMPLIANCEL4_delay; +wire PIPETXCOMPLIANCEL5_delay; +wire PIPETXCOMPLIANCEL6_delay; +wire PIPETXCOMPLIANCEL7_delay; +wire PIPETXDATAKL0_delay; +wire PIPETXDATAKL1_delay; +wire PIPETXDATAKL2_delay; +wire PIPETXDATAKL3_delay; +wire PIPETXDATAKL4_delay; +wire PIPETXDATAKL5_delay; +wire PIPETXDATAKL6_delay; +wire PIPETXDATAKL7_delay; +wire PIPETXDETECTRXLOOPBACKL0_delay; +wire PIPETXDETECTRXLOOPBACKL1_delay; +wire PIPETXDETECTRXLOOPBACKL2_delay; +wire PIPETXDETECTRXLOOPBACKL3_delay; +wire PIPETXDETECTRXLOOPBACKL4_delay; +wire PIPETXDETECTRXLOOPBACKL5_delay; +wire PIPETXDETECTRXLOOPBACKL6_delay; +wire PIPETXDETECTRXLOOPBACKL7_delay; +wire PIPETXELECIDLEL0_delay; +wire PIPETXELECIDLEL1_delay; +wire PIPETXELECIDLEL2_delay; +wire PIPETXELECIDLEL3_delay; +wire PIPETXELECIDLEL4_delay; +wire PIPETXELECIDLEL5_delay; +wire PIPETXELECIDLEL6_delay; +wire PIPETXELECIDLEL7_delay; +wire SERRENABLE_delay; +wire URREPORTINGENABLE_delay; +wire [11:0] MGMTSTATSCREDIT_delay; +wire [11:0] MIMDLLBRADD_delay; +wire [11:0] MIMDLLBWADD_delay; +wire [12:0] L0COMPLETERID_delay; +wire [12:0] MIMRXBRADD_delay; +wire [12:0] MIMRXBWADD_delay; +wire [12:0] MIMTXBRADD_delay; +wire [12:0] MIMTXBWADD_delay; +wire [15:0] L0ERRMSGREQID_delay; +wire [15:0] LLKRXPREFERREDTYPE_delay; +wire [16:0] MGMTPSO_delay; +wire [18:0] L0RXDLLSBFCDATA_delay; +wire [19:0] L0RXDLLFCNPOSTBYPCRED_delay; +wire [1:0] L0ATTENTIONINDICATORCONTROL_delay; +wire [1:0] L0DLLASRXSTATE_delay; +wire [1:0] L0POWERINDICATORCONTROL_delay; +wire [1:0] L0PWRSTATE0_delay; +wire [1:0] L0RXDLLTLPEND_delay; +wire [1:0] L0RXMACLINKERROR_delay; +wire [1:0] LLKRXVALIDN_delay; +wire [1:0] PIPEPOWERDOWNL0_delay; +wire [1:0] PIPEPOWERDOWNL1_delay; +wire [1:0] PIPEPOWERDOWNL2_delay; +wire [1:0] PIPEPOWERDOWNL3_delay; +wire [1:0] PIPEPOWERDOWNL4_delay; +wire [1:0] PIPEPOWERDOWNL5_delay; +wire [1:0] PIPEPOWERDOWNL6_delay; +wire [1:0] PIPEPOWERDOWNL7_delay; +wire [23:0] L0RXDLLFCCMPLMCCRED_delay; +wire [23:0] L0RXDLLFCPOSTORDCRED_delay; +wire [2:0] L0MCFOUND_delay; +wire [2:0] L0MULTIMSGEN0_delay; +wire [2:0] L0RXDLLPMTYPE_delay; +wire [2:0] L0TRANSFORMEDVC_delay; +wire [2:0] MAXPAYLOADSIZE_delay; +wire [2:0] MAXREADREQUESTSIZE_delay; +wire [31:0] MGMTRDATA_delay; +wire [3:0] L0LTSSMSTATE_delay; +wire [3:0] L0MACNEGOTIATEDLINKWIDTH_delay; +wire [3:0] L0UCBYPFOUND_delay; +wire [3:0] L0UCORDFOUND_delay; +wire [63:0] LLKRXDATA_delay; +wire [63:0] MIMDLLBWDATA_delay; +wire [63:0] MIMRXBWDATA_delay; +wire [63:0] MIMTXBWDATA_delay; +wire [6:0] L0DLLERRORVECTOR_delay; +wire [7:0] L0DLLVCSTATUS_delay; +wire [7:0] L0DLUPDOWN_delay; +wire [7:0] L0RXDLLFCCMPLMCUPDATE_delay; +wire [7:0] L0RXDLLFCNPOSTBYPUPDATE_delay; +wire [7:0] L0RXDLLFCPOSTORDUPDATE_delay; +wire [7:0] L0TXDLLFCCMPLMCUPDATED_delay; +wire [7:0] L0TXDLLFCNPOSTBYPUPDATED_delay; +wire [7:0] L0TXDLLFCPOSTORDUPDATED_delay; +wire [7:0] LLKRXCHCOMPLETIONAVAILABLEN_delay; +wire [7:0] LLKRXCHCOMPLETIONPARTIALN_delay; +wire [7:0] LLKRXCHNONPOSTEDAVAILABLEN_delay; +wire [7:0] LLKRXCHNONPOSTEDPARTIALN_delay; +wire [7:0] LLKRXCHPOSTEDAVAILABLEN_delay; +wire [7:0] LLKRXCHPOSTEDPARTIALN_delay; +wire [7:0] LLKTCSTATUS_delay; +wire [7:0] LLKTXCHCOMPLETIONREADYN_delay; +wire [7:0] LLKTXCHNONPOSTEDREADYN_delay; +wire [7:0] LLKTXCHPOSTEDREADYN_delay; +wire [7:0] PIPETXDATAL0_delay; +wire [7:0] PIPETXDATAL1_delay; +wire [7:0] PIPETXDATAL2_delay; +wire [7:0] PIPETXDATAL3_delay; +wire [7:0] PIPETXDATAL4_delay; +wire [7:0] PIPETXDATAL5_delay; +wire [7:0] PIPETXDATAL6_delay; +wire [7:0] PIPETXDATAL7_delay; +wire [9:0] LLKTXCHANSPACE_delay; + +wire AUXPOWER_delay; +wire COMPLIANCEAVOID_delay; +wire CRMCFGBRIDGEHOTRESET_delay; +wire CRMCORECLKDLO_delay; +wire CRMCORECLKRXO_delay; +wire CRMCORECLKTXO_delay; +wire CRMCORECLK_delay; +wire CRMLINKRSTN_delay; +wire CRMMACRSTN_delay; +wire CRMMGMTRSTN_delay; +wire CRMNVRSTN_delay; +wire CRMTXHOTRESETN_delay; +wire CRMURSTN_delay; +wire CRMUSERCFGRSTN_delay; +wire CRMUSERCLKRXO_delay; +wire CRMUSERCLKTXO_delay; +wire CRMUSERCLK_delay; +wire CROSSLINKSEED_delay; +wire L0ALLDOWNPORTSINL1_delay; +wire L0ALLDOWNRXPORTSINL0S_delay; +wire L0ASE_delay; +wire L0ATTENTIONBUTTONPRESSED_delay; +wire L0CFGASSPANTREEOWNEDSTATE_delay; +wire L0CFGDISABLESCRAMBLE_delay; +wire L0CFGEXTENDEDSYNC_delay; +wire L0CFGL0SENTRYENABLE_delay; +wire L0CFGL0SENTRYSUP_delay; +wire L0CFGLINKDISABLE_delay; +wire L0CFGLOOPBACKMASTER_delay; +wire L0DLLHOLDLINKUP_delay; +wire L0ELECTROMECHANICALINTERLOCKENGAGED_delay; +wire L0FWDASSERTINTALEGACYINT_delay; +wire L0FWDASSERTINTBLEGACYINT_delay; +wire L0FWDASSERTINTCLEGACYINT_delay; +wire L0FWDASSERTINTDLEGACYINT_delay; +wire L0FWDCORRERRIN_delay; +wire L0FWDDEASSERTINTALEGACYINT_delay; +wire L0FWDDEASSERTINTBLEGACYINT_delay; +wire L0FWDDEASSERTINTCLEGACYINT_delay; +wire L0FWDDEASSERTINTDLEGACYINT_delay; +wire L0FWDFATALERRIN_delay; +wire L0FWDNONFATALERRIN_delay; +wire L0LEGACYINTFUNCT0_delay; +wire L0MRLSENSORCLOSEDN_delay; +wire L0PMEREQIN_delay; +wire L0POWERFAULTDETECTED_delay; +wire L0PRESENCEDETECTSLOTEMPTYN_delay; +wire L0PWRNEWSTATEREQ_delay; +wire L0ROOTTURNOFFREQ_delay; +wire L0SENDUNLOCKMESSAGE_delay; +wire L0SETCOMPLETERABORTERROR_delay; +wire L0SETCOMPLETIONTIMEOUTCORRERROR_delay; +wire L0SETCOMPLETIONTIMEOUTUNCORRERROR_delay; +wire L0SETDETECTEDCORRERROR_delay; +wire L0SETDETECTEDFATALERROR_delay; +wire L0SETDETECTEDNONFATALERROR_delay; +wire L0SETLINKDETECTEDPARITYERROR_delay; +wire L0SETLINKMASTERDATAPARITY_delay; +wire L0SETLINKRECEIVEDMASTERABORT_delay; +wire L0SETLINKRECEIVEDTARGETABORT_delay; +wire L0SETLINKSIGNALLEDTARGETABORT_delay; +wire L0SETLINKSYSTEMERROR_delay; +wire L0SETUNEXPECTEDCOMPLETIONCORRERROR_delay; +wire L0SETUNEXPECTEDCOMPLETIONUNCORRERROR_delay; +wire L0SETUNSUPPORTEDREQUESTNONPOSTEDERROR_delay; +wire L0SETUNSUPPORTEDREQUESTOTHERERROR_delay; +wire L0SETUSERDETECTEDPARITYERROR_delay; +wire L0SETUSERMASTERDATAPARITY_delay; +wire L0SETUSERRECEIVEDMASTERABORT_delay; +wire L0SETUSERRECEIVEDTARGETABORT_delay; +wire L0SETUSERSIGNALLEDTARGETABORT_delay; +wire L0SETUSERSYSTEMERROR_delay; +wire L0TLASFCCREDSTARVATION_delay; +wire L0TLLINKRETRAIN_delay; +wire L0TRANSACTIONSPENDING_delay; +wire L0TXBEACON_delay; +wire L0TXCFGPM_delay; +wire L0TXTLSBFCUPDATE_delay; +wire L0TXTLTLPEDB_delay; +wire L0TXTLTLPREQEND_delay; +wire L0TXTLTLPREQ_delay; +wire L0TXTLTLPWIDTH_delay; +wire L0UPSTREAMRXPORTINL0S_delay; +wire L0VC0PREVIEWEXPAND_delay; +wire L0WAKEN_delay; +wire LLKRXDSTCONTREQN_delay; +wire LLKRXDSTREQN_delay; +wire LLKTX4DWHEADERN_delay; +wire LLKTXCOMPLETEN_delay; +wire LLKTXCREATEECRCN_delay; +wire LLKTXEOFN_delay; +wire LLKTXEOPN_delay; +wire LLKTXSOFN_delay; +wire LLKTXSOPN_delay; +wire LLKTXSRCDSCN_delay; +wire LLKTXSRCRDYN_delay; +wire MAINPOWER_delay; +wire MGMTRDEN_delay; +wire MGMTWREN_delay; +wire PIPEPHYSTATUSL0_delay; +wire PIPEPHYSTATUSL1_delay; +wire PIPEPHYSTATUSL2_delay; +wire PIPEPHYSTATUSL3_delay; +wire PIPEPHYSTATUSL4_delay; +wire PIPEPHYSTATUSL5_delay; +wire PIPEPHYSTATUSL6_delay; +wire PIPEPHYSTATUSL7_delay; +wire PIPERXCHANISALIGNEDL0_delay; +wire PIPERXCHANISALIGNEDL1_delay; +wire PIPERXCHANISALIGNEDL2_delay; +wire PIPERXCHANISALIGNEDL3_delay; +wire PIPERXCHANISALIGNEDL4_delay; +wire PIPERXCHANISALIGNEDL5_delay; +wire PIPERXCHANISALIGNEDL6_delay; +wire PIPERXCHANISALIGNEDL7_delay; +wire PIPERXDATAKL0_delay; +wire PIPERXDATAKL1_delay; +wire PIPERXDATAKL2_delay; +wire PIPERXDATAKL3_delay; +wire PIPERXDATAKL4_delay; +wire PIPERXDATAKL5_delay; +wire PIPERXDATAKL6_delay; +wire PIPERXDATAKL7_delay; +wire PIPERXELECIDLEL0_delay; +wire PIPERXELECIDLEL1_delay; +wire PIPERXELECIDLEL2_delay; +wire PIPERXELECIDLEL3_delay; +wire PIPERXELECIDLEL4_delay; +wire PIPERXELECIDLEL5_delay; +wire PIPERXELECIDLEL6_delay; +wire PIPERXELECIDLEL7_delay; +wire PIPERXVALIDL0_delay; +wire PIPERXVALIDL1_delay; +wire PIPERXVALIDL2_delay; +wire PIPERXVALIDL3_delay; +wire PIPERXVALIDL4_delay; +wire PIPERXVALIDL5_delay; +wire PIPERXVALIDL6_delay; +wire PIPERXVALIDL7_delay; +wire [10:0] MGMTADDR_delay; +wire [11:0] L0ACKNAKTIMERADJUSTMENT_delay; +wire [11:0] L0REPLAYTIMERADJUSTMENT_delay; +wire [127:0] L0PACKETHEADERFROMUSER_delay; +wire [159:0] L0TXTLFCCMPLMCCRED_delay; +wire [159:0] L0TXTLFCPOSTORDCRED_delay; +wire [15:0] L0TXTLFCCMPLMCUPDATE_delay; +wire [15:0] L0TXTLFCNPOSTBYPUPDATE_delay; +wire [15:0] L0TXTLFCPOSTORDUPDATE_delay; +wire [18:0] L0TXTLSBFCDATA_delay; +wire [191:0] L0TXTLFCNPOSTBYPCRED_delay; +wire [1:0] L0PWRNEXTLINKSTATE_delay; +wire [1:0] L0TXTLTLPENABLE_delay; +wire [1:0] L0TXTLTLPEND_delay; +wire [1:0] LLKRXCHFIFO_delay; +wire [1:0] LLKTXCHFIFO_delay; +wire [1:0] LLKTXENABLEN_delay; +wire [23:0] L0CFGVCID_delay; +wire [2:0] L0ASTURNPOOLBITSCONSUMED_delay; +wire [2:0] L0CFGL0SEXITLAT_delay; +wire [2:0] L0CFGNEGOTIATEDMAXP_delay; +wire [2:0] L0TXCFGPMTYPE_delay; +wire [2:0] LLKRXCHTC_delay; +wire [2:0] LLKTXCHTC_delay; +wire [2:0] PIPERXSTATUSL0_delay; +wire [2:0] PIPERXSTATUSL1_delay; +wire [2:0] PIPERXSTATUSL2_delay; +wire [2:0] PIPERXSTATUSL3_delay; +wire [2:0] PIPERXSTATUSL4_delay; +wire [2:0] PIPERXSTATUSL5_delay; +wire [2:0] PIPERXSTATUSL6_delay; +wire [2:0] PIPERXSTATUSL7_delay; +wire [31:0] MGMTWDATA_delay; +wire [3:0] L0CFGASSTATECHANGECMD_delay; +wire [3:0] L0MSIREQUEST0_delay; +wire [3:0] L0TXTLTLPLATENCY_delay; +wire [3:0] MGMTBWREN_delay; +wire [5:0] CFGNEGOTIATEDLINKWIDTH_delay; +wire [63:0] L0TXTLTLPDATA_delay; +wire [63:0] LLKTXDATA_delay; +wire [63:0] MIMDLLBRDATA_delay; +wire [63:0] MIMRXBRDATA_delay; +wire [63:0] MIMTXBRDATA_delay; +wire [6:0] MGMTSTATSCREDITSEL_delay; +wire [7:0] L0ASPORTCOUNT_delay; +wire [7:0] L0CFGVCENABLE_delay; +wire [7:0] L0PORTNUMBER_delay; +wire [7:0] L0RXTLTLPNONINITIALIZEDVC_delay; +wire [7:0] PIPERXDATAL0_delay; +wire [7:0] PIPERXDATAL1_delay; +wire [7:0] PIPERXDATAL2_delay; +wire [7:0] PIPERXDATAL3_delay; +wire [7:0] PIPERXDATAL4_delay; +wire [7:0] PIPERXDATAL5_delay; +wire [7:0] PIPERXDATAL6_delay; +wire [7:0] PIPERXDATAL7_delay; + + +assign #(out_delay) BUSMASTERENABLE = BUSMASTERENABLE_delay; +assign #(out_delay) CRMDOHOTRESETN = CRMDOHOTRESETN_delay; +assign #(out_delay) CRMPWRSOFTRESETN = CRMPWRSOFTRESETN_delay; +assign #(out_delay) CRMRXHOTRESETN = CRMRXHOTRESETN_delay; +assign #(out_delay) DLLTXPMDLLPOUTSTANDING = DLLTXPMDLLPOUTSTANDING_delay; +assign #(out_delay) INTERRUPTDISABLE = INTERRUPTDISABLE_delay; +assign #(out_delay) IOSPACEENABLE = IOSPACEENABLE_delay; +assign #(out_delay) L0ASAUTONOMOUSINITCOMPLETED = L0ASAUTONOMOUSINITCOMPLETED_delay; +assign #(out_delay) L0ATTENTIONINDICATORCONTROL = L0ATTENTIONINDICATORCONTROL_delay; +assign #(out_delay) L0CFGLOOPBACKACK = L0CFGLOOPBACKACK_delay; +assign #(out_delay) L0COMPLETERID = L0COMPLETERID_delay; +assign #(out_delay) L0CORRERRMSGRCVD = L0CORRERRMSGRCVD_delay; +assign #(out_delay) L0DLLASRXSTATE = L0DLLASRXSTATE_delay; +assign #(out_delay) L0DLLASTXSTATE = L0DLLASTXSTATE_delay; +assign #(out_delay) L0DLLERRORVECTOR = L0DLLERRORVECTOR_delay; +assign #(out_delay) L0DLLRXACKOUTSTANDING = L0DLLRXACKOUTSTANDING_delay; +assign #(out_delay) L0DLLTXNONFCOUTSTANDING = L0DLLTXNONFCOUTSTANDING_delay; +assign #(out_delay) L0DLLTXOUTSTANDING = L0DLLTXOUTSTANDING_delay; +assign #(out_delay) L0DLLVCSTATUS = L0DLLVCSTATUS_delay; +assign #(out_delay) L0DLUPDOWN = L0DLUPDOWN_delay; +assign #(out_delay) L0ERRMSGREQID = L0ERRMSGREQID_delay; +assign #(out_delay) L0FATALERRMSGRCVD = L0FATALERRMSGRCVD_delay; +assign #(out_delay) L0FIRSTCFGWRITEOCCURRED = L0FIRSTCFGWRITEOCCURRED_delay; +assign #(out_delay) L0FWDCORRERROUT = L0FWDCORRERROUT_delay; +assign #(out_delay) L0FWDFATALERROUT = L0FWDFATALERROUT_delay; +assign #(out_delay) L0FWDNONFATALERROUT = L0FWDNONFATALERROUT_delay; +assign #(out_delay) L0LTSSMSTATE = L0LTSSMSTATE_delay; +assign #(out_delay) L0MACENTEREDL0 = L0MACENTEREDL0_delay; +assign #(out_delay) L0MACLINKTRAINING = L0MACLINKTRAINING_delay; +assign #(out_delay) L0MACLINKUP = L0MACLINKUP_delay; +assign #(out_delay) L0MACNEGOTIATEDLINKWIDTH = L0MACNEGOTIATEDLINKWIDTH_delay; +assign #(out_delay) L0MACNEWSTATEACK = L0MACNEWSTATEACK_delay; +assign #(out_delay) L0MACRXL0SSTATE = L0MACRXL0SSTATE_delay; +assign #(out_delay) L0MACUPSTREAMDOWNSTREAM = L0MACUPSTREAMDOWNSTREAM_delay; +assign #(out_delay) L0MCFOUND = L0MCFOUND_delay; +assign #(out_delay) L0MSIENABLE0 = L0MSIENABLE0_delay; +assign #(out_delay) L0MULTIMSGEN0 = L0MULTIMSGEN0_delay; +assign #(out_delay) L0NONFATALERRMSGRCVD = L0NONFATALERRMSGRCVD_delay; +assign #(out_delay) L0PMEACK = L0PMEACK_delay; +assign #(out_delay) L0PMEEN = L0PMEEN_delay; +assign #(out_delay) L0PMEREQOUT = L0PMEREQOUT_delay; +assign #(out_delay) L0POWERCONTROLLERCONTROL = L0POWERCONTROLLERCONTROL_delay; +assign #(out_delay) L0POWERINDICATORCONTROL = L0POWERINDICATORCONTROL_delay; +assign #(out_delay) L0PWRINHIBITTRANSFERS = L0PWRINHIBITTRANSFERS_delay; +assign #(out_delay) L0PWRL1STATE = L0PWRL1STATE_delay; +assign #(out_delay) L0PWRL23READYDEVICE = L0PWRL23READYDEVICE_delay; +assign #(out_delay) L0PWRL23READYSTATE = L0PWRL23READYSTATE_delay; +assign #(out_delay) L0PWRSTATE0 = L0PWRSTATE0_delay; +assign #(out_delay) L0PWRTURNOFFREQ = L0PWRTURNOFFREQ_delay; +assign #(out_delay) L0PWRTXL0SSTATE = L0PWRTXL0SSTATE_delay; +assign #(out_delay) L0RECEIVEDASSERTINTALEGACYINT = L0RECEIVEDASSERTINTALEGACYINT_delay; +assign #(out_delay) L0RECEIVEDASSERTINTBLEGACYINT = L0RECEIVEDASSERTINTBLEGACYINT_delay; +assign #(out_delay) L0RECEIVEDASSERTINTCLEGACYINT = L0RECEIVEDASSERTINTCLEGACYINT_delay; +assign #(out_delay) L0RECEIVEDASSERTINTDLEGACYINT = L0RECEIVEDASSERTINTDLEGACYINT_delay; +assign #(out_delay) L0RECEIVEDDEASSERTINTALEGACYINT = L0RECEIVEDDEASSERTINTALEGACYINT_delay; +assign #(out_delay) L0RECEIVEDDEASSERTINTBLEGACYINT = L0RECEIVEDDEASSERTINTBLEGACYINT_delay; +assign #(out_delay) L0RECEIVEDDEASSERTINTCLEGACYINT = L0RECEIVEDDEASSERTINTCLEGACYINT_delay; +assign #(out_delay) L0RECEIVEDDEASSERTINTDLEGACYINT = L0RECEIVEDDEASSERTINTDLEGACYINT_delay; +assign #(out_delay) L0RXBEACON = L0RXBEACON_delay; +assign #(out_delay) L0RXDLLFCCMPLMCCRED = L0RXDLLFCCMPLMCCRED_delay; +assign #(out_delay) L0RXDLLFCCMPLMCUPDATE = L0RXDLLFCCMPLMCUPDATE_delay; +assign #(out_delay) L0RXDLLFCNPOSTBYPCRED = L0RXDLLFCNPOSTBYPCRED_delay; +assign #(out_delay) L0RXDLLFCNPOSTBYPUPDATE = L0RXDLLFCNPOSTBYPUPDATE_delay; +assign #(out_delay) L0RXDLLFCPOSTORDCRED = L0RXDLLFCPOSTORDCRED_delay; +assign #(out_delay) L0RXDLLFCPOSTORDUPDATE = L0RXDLLFCPOSTORDUPDATE_delay; +assign #(out_delay) L0RXDLLPM = L0RXDLLPM_delay; +assign #(out_delay) L0RXDLLPMTYPE = L0RXDLLPMTYPE_delay; +assign #(out_delay) L0RXDLLSBFCDATA = L0RXDLLSBFCDATA_delay; +assign #(out_delay) L0RXDLLSBFCUPDATE = L0RXDLLSBFCUPDATE_delay; +assign #(out_delay) L0RXDLLTLPECRCOK = L0RXDLLTLPECRCOK_delay; +assign #(out_delay) L0RXDLLTLPEND = L0RXDLLTLPEND_delay; +assign #(out_delay) L0RXMACLINKERROR = L0RXMACLINKERROR_delay; +assign #(out_delay) L0STATSCFGOTHERRECEIVED = L0STATSCFGOTHERRECEIVED_delay; +assign #(out_delay) L0STATSCFGOTHERTRANSMITTED = L0STATSCFGOTHERTRANSMITTED_delay; +assign #(out_delay) L0STATSCFGRECEIVED = L0STATSCFGRECEIVED_delay; +assign #(out_delay) L0STATSCFGTRANSMITTED = L0STATSCFGTRANSMITTED_delay; +assign #(out_delay) L0STATSDLLPRECEIVED = L0STATSDLLPRECEIVED_delay; +assign #(out_delay) L0STATSDLLPTRANSMITTED = L0STATSDLLPTRANSMITTED_delay; +assign #(out_delay) L0STATSOSRECEIVED = L0STATSOSRECEIVED_delay; +assign #(out_delay) L0STATSOSTRANSMITTED = L0STATSOSTRANSMITTED_delay; +assign #(out_delay) L0STATSTLPRECEIVED = L0STATSTLPRECEIVED_delay; +assign #(out_delay) L0STATSTLPTRANSMITTED = L0STATSTLPTRANSMITTED_delay; +assign #(out_delay) L0TOGGLEELECTROMECHANICALINTERLOCK = L0TOGGLEELECTROMECHANICALINTERLOCK_delay; +assign #(out_delay) L0TRANSFORMEDVC = L0TRANSFORMEDVC_delay; +assign #(out_delay) L0TXDLLFCCMPLMCUPDATED = L0TXDLLFCCMPLMCUPDATED_delay; +assign #(out_delay) L0TXDLLFCNPOSTBYPUPDATED = L0TXDLLFCNPOSTBYPUPDATED_delay; +assign #(out_delay) L0TXDLLFCPOSTORDUPDATED = L0TXDLLFCPOSTORDUPDATED_delay; +assign #(out_delay) L0TXDLLPMUPDATED = L0TXDLLPMUPDATED_delay; +assign #(out_delay) L0TXDLLSBFCUPDATED = L0TXDLLSBFCUPDATED_delay; +assign #(out_delay) L0UCBYPFOUND = L0UCBYPFOUND_delay; +assign #(out_delay) L0UCORDFOUND = L0UCORDFOUND_delay; +assign #(out_delay) L0UNLOCKRECEIVED = L0UNLOCKRECEIVED_delay; +assign #(out_delay) LLKRX4DWHEADERN = LLKRX4DWHEADERN_delay; +assign #(out_delay) LLKRXCHCOMPLETIONAVAILABLEN = LLKRXCHCOMPLETIONAVAILABLEN_delay; +assign #(out_delay) LLKRXCHCOMPLETIONPARTIALN = LLKRXCHCOMPLETIONPARTIALN_delay; +assign #(out_delay) LLKRXCHCONFIGAVAILABLEN = LLKRXCHCONFIGAVAILABLEN_delay; +assign #(out_delay) LLKRXCHCONFIGPARTIALN = LLKRXCHCONFIGPARTIALN_delay; +assign #(out_delay) LLKRXCHNONPOSTEDAVAILABLEN = LLKRXCHNONPOSTEDAVAILABLEN_delay; +assign #(out_delay) LLKRXCHNONPOSTEDPARTIALN = LLKRXCHNONPOSTEDPARTIALN_delay; +assign #(out_delay) LLKRXCHPOSTEDAVAILABLEN = LLKRXCHPOSTEDAVAILABLEN_delay; +assign #(out_delay) LLKRXCHPOSTEDPARTIALN = LLKRXCHPOSTEDPARTIALN_delay; +assign #(out_delay) LLKRXDATA = LLKRXDATA_delay; +assign #(out_delay) LLKRXECRCBADN = LLKRXECRCBADN_delay; +assign #(out_delay) LLKRXEOFN = LLKRXEOFN_delay; +assign #(out_delay) LLKRXEOPN = LLKRXEOPN_delay; +assign #(out_delay) LLKRXPREFERREDTYPE = LLKRXPREFERREDTYPE_delay; +assign #(out_delay) LLKRXSOFN = LLKRXSOFN_delay; +assign #(out_delay) LLKRXSOPN = LLKRXSOPN_delay; +assign #(out_delay) LLKRXSRCDSCN = LLKRXSRCDSCN_delay; +assign #(out_delay) LLKRXSRCLASTREQN = LLKRXSRCLASTREQN_delay; +assign #(out_delay) LLKRXSRCRDYN = LLKRXSRCRDYN_delay; +assign #(out_delay) LLKRXVALIDN = LLKRXVALIDN_delay; +assign #(out_delay) LLKTCSTATUS = LLKTCSTATUS_delay; +assign #(out_delay) LLKTXCHANSPACE = LLKTXCHANSPACE_delay; +assign #(out_delay) LLKTXCHCOMPLETIONREADYN = LLKTXCHCOMPLETIONREADYN_delay; +assign #(out_delay) LLKTXCHNONPOSTEDREADYN = LLKTXCHNONPOSTEDREADYN_delay; +assign #(out_delay) LLKTXCHPOSTEDREADYN = LLKTXCHPOSTEDREADYN_delay; +assign #(out_delay) LLKTXCONFIGREADYN = LLKTXCONFIGREADYN_delay; +assign #(out_delay) LLKTXDSTRDYN = LLKTXDSTRDYN_delay; +assign #(out_delay) MAXPAYLOADSIZE = MAXPAYLOADSIZE_delay; +assign #(out_delay) MAXREADREQUESTSIZE = MAXREADREQUESTSIZE_delay; +assign #(out_delay) MEMSPACEENABLE = MEMSPACEENABLE_delay; +assign #(out_delay) MGMTPSO = MGMTPSO_delay; +assign #(out_delay) MGMTRDATA = MGMTRDATA_delay; +assign #(out_delay) MGMTSTATSCREDIT = MGMTSTATSCREDIT_delay; +assign #(out_delay) MIMDLLBRADD = MIMDLLBRADD_delay; +assign #(out_delay) MIMDLLBREN = MIMDLLBREN_delay; +assign #(out_delay) MIMDLLBWADD = MIMDLLBWADD_delay; +assign #(out_delay) MIMDLLBWDATA = MIMDLLBWDATA_delay; +assign #(out_delay) MIMDLLBWEN = MIMDLLBWEN_delay; +assign #(out_delay) MIMRXBRADD = MIMRXBRADD_delay; +assign #(out_delay) MIMRXBREN = MIMRXBREN_delay; +assign #(out_delay) MIMRXBWADD = MIMRXBWADD_delay; +assign #(out_delay) MIMRXBWDATA = MIMRXBWDATA_delay; +assign #(out_delay) MIMRXBWEN = MIMRXBWEN_delay; +assign #(out_delay) MIMTXBRADD = MIMTXBRADD_delay; +assign #(out_delay) MIMTXBREN = MIMTXBREN_delay; +assign #(out_delay) MIMTXBWADD = MIMTXBWADD_delay; +assign #(out_delay) MIMTXBWDATA = MIMTXBWDATA_delay; +assign #(out_delay) MIMTXBWEN = MIMTXBWEN_delay; +assign #(out_delay) PARITYERRORRESPONSE = PARITYERRORRESPONSE_delay; +assign #(out_delay) PIPEDESKEWLANESL0 = PIPEDESKEWLANESL0_delay; +assign #(out_delay) PIPEDESKEWLANESL1 = PIPEDESKEWLANESL1_delay; +assign #(out_delay) PIPEDESKEWLANESL2 = PIPEDESKEWLANESL2_delay; +assign #(out_delay) PIPEDESKEWLANESL3 = PIPEDESKEWLANESL3_delay; +assign #(out_delay) PIPEDESKEWLANESL4 = PIPEDESKEWLANESL4_delay; +assign #(out_delay) PIPEDESKEWLANESL5 = PIPEDESKEWLANESL5_delay; +assign #(out_delay) PIPEDESKEWLANESL6 = PIPEDESKEWLANESL6_delay; +assign #(out_delay) PIPEDESKEWLANESL7 = PIPEDESKEWLANESL7_delay; +assign #(out_delay) PIPEPOWERDOWNL0 = PIPEPOWERDOWNL0_delay; +assign #(out_delay) PIPEPOWERDOWNL1 = PIPEPOWERDOWNL1_delay; +assign #(out_delay) PIPEPOWERDOWNL2 = PIPEPOWERDOWNL2_delay; +assign #(out_delay) PIPEPOWERDOWNL3 = PIPEPOWERDOWNL3_delay; +assign #(out_delay) PIPEPOWERDOWNL4 = PIPEPOWERDOWNL4_delay; +assign #(out_delay) PIPEPOWERDOWNL5 = PIPEPOWERDOWNL5_delay; +assign #(out_delay) PIPEPOWERDOWNL6 = PIPEPOWERDOWNL6_delay; +assign #(out_delay) PIPEPOWERDOWNL7 = PIPEPOWERDOWNL7_delay; +assign #(out_delay) PIPERESETL0 = PIPERESETL0_delay; +assign #(out_delay) PIPERESETL1 = PIPERESETL1_delay; +assign #(out_delay) PIPERESETL2 = PIPERESETL2_delay; +assign #(out_delay) PIPERESETL3 = PIPERESETL3_delay; +assign #(out_delay) PIPERESETL4 = PIPERESETL4_delay; +assign #(out_delay) PIPERESETL5 = PIPERESETL5_delay; +assign #(out_delay) PIPERESETL6 = PIPERESETL6_delay; +assign #(out_delay) PIPERESETL7 = PIPERESETL7_delay; +assign #(out_delay) PIPERXPOLARITYL0 = PIPERXPOLARITYL0_delay; +assign #(out_delay) PIPERXPOLARITYL1 = PIPERXPOLARITYL1_delay; +assign #(out_delay) PIPERXPOLARITYL2 = PIPERXPOLARITYL2_delay; +assign #(out_delay) PIPERXPOLARITYL3 = PIPERXPOLARITYL3_delay; +assign #(out_delay) PIPERXPOLARITYL4 = PIPERXPOLARITYL4_delay; +assign #(out_delay) PIPERXPOLARITYL5 = PIPERXPOLARITYL5_delay; +assign #(out_delay) PIPERXPOLARITYL6 = PIPERXPOLARITYL6_delay; +assign #(out_delay) PIPERXPOLARITYL7 = PIPERXPOLARITYL7_delay; +assign #(out_delay) PIPETXCOMPLIANCEL0 = PIPETXCOMPLIANCEL0_delay; +assign #(out_delay) PIPETXCOMPLIANCEL1 = PIPETXCOMPLIANCEL1_delay; +assign #(out_delay) PIPETXCOMPLIANCEL2 = PIPETXCOMPLIANCEL2_delay; +assign #(out_delay) PIPETXCOMPLIANCEL3 = PIPETXCOMPLIANCEL3_delay; +assign #(out_delay) PIPETXCOMPLIANCEL4 = PIPETXCOMPLIANCEL4_delay; +assign #(out_delay) PIPETXCOMPLIANCEL5 = PIPETXCOMPLIANCEL5_delay; +assign #(out_delay) PIPETXCOMPLIANCEL6 = PIPETXCOMPLIANCEL6_delay; +assign #(out_delay) PIPETXCOMPLIANCEL7 = PIPETXCOMPLIANCEL7_delay; +assign #(out_delay) PIPETXDATAKL0 = PIPETXDATAKL0_delay; +assign #(out_delay) PIPETXDATAKL1 = PIPETXDATAKL1_delay; +assign #(out_delay) PIPETXDATAKL2 = PIPETXDATAKL2_delay; +assign #(out_delay) PIPETXDATAKL3 = PIPETXDATAKL3_delay; +assign #(out_delay) PIPETXDATAKL4 = PIPETXDATAKL4_delay; +assign #(out_delay) PIPETXDATAKL5 = PIPETXDATAKL5_delay; +assign #(out_delay) PIPETXDATAKL6 = PIPETXDATAKL6_delay; +assign #(out_delay) PIPETXDATAKL7 = PIPETXDATAKL7_delay; +assign #(out_delay) PIPETXDATAL0 = PIPETXDATAL0_delay; +assign #(out_delay) PIPETXDATAL1 = PIPETXDATAL1_delay; +assign #(out_delay) PIPETXDATAL2 = PIPETXDATAL2_delay; +assign #(out_delay) PIPETXDATAL3 = PIPETXDATAL3_delay; +assign #(out_delay) PIPETXDATAL4 = PIPETXDATAL4_delay; +assign #(out_delay) PIPETXDATAL5 = PIPETXDATAL5_delay; +assign #(out_delay) PIPETXDATAL6 = PIPETXDATAL6_delay; +assign #(out_delay) PIPETXDATAL7 = PIPETXDATAL7_delay; +assign #(out_delay) PIPETXDETECTRXLOOPBACKL0 = PIPETXDETECTRXLOOPBACKL0_delay; +assign #(out_delay) PIPETXDETECTRXLOOPBACKL1 = PIPETXDETECTRXLOOPBACKL1_delay; +assign #(out_delay) PIPETXDETECTRXLOOPBACKL2 = PIPETXDETECTRXLOOPBACKL2_delay; +assign #(out_delay) PIPETXDETECTRXLOOPBACKL3 = PIPETXDETECTRXLOOPBACKL3_delay; +assign #(out_delay) PIPETXDETECTRXLOOPBACKL4 = PIPETXDETECTRXLOOPBACKL4_delay; +assign #(out_delay) PIPETXDETECTRXLOOPBACKL5 = PIPETXDETECTRXLOOPBACKL5_delay; +assign #(out_delay) PIPETXDETECTRXLOOPBACKL6 = PIPETXDETECTRXLOOPBACKL6_delay; +assign #(out_delay) PIPETXDETECTRXLOOPBACKL7 = PIPETXDETECTRXLOOPBACKL7_delay; +assign #(out_delay) PIPETXELECIDLEL0 = PIPETXELECIDLEL0_delay; +assign #(out_delay) PIPETXELECIDLEL1 = PIPETXELECIDLEL1_delay; +assign #(out_delay) PIPETXELECIDLEL2 = PIPETXELECIDLEL2_delay; +assign #(out_delay) PIPETXELECIDLEL3 = PIPETXELECIDLEL3_delay; +assign #(out_delay) PIPETXELECIDLEL4 = PIPETXELECIDLEL4_delay; +assign #(out_delay) PIPETXELECIDLEL5 = PIPETXELECIDLEL5_delay; +assign #(out_delay) PIPETXELECIDLEL6 = PIPETXELECIDLEL6_delay; +assign #(out_delay) PIPETXELECIDLEL7 = PIPETXELECIDLEL7_delay; +assign #(out_delay) SERRENABLE = SERRENABLE_delay; +assign #(out_delay) URREPORTINGENABLE = URREPORTINGENABLE_delay; + +assign #(CLK_DELAY) CRMCORECLKDLO_delay = CRMCORECLKDLO; +assign #(CLK_DELAY) CRMCORECLKRXO_delay = CRMCORECLKRXO; +assign #(CLK_DELAY) CRMCORECLKTXO_delay = CRMCORECLKTXO; +assign #(CLK_DELAY) CRMCORECLK_delay = CRMCORECLK; +assign #(CLK_DELAY) CRMUSERCLKRXO_delay = CRMUSERCLKRXO; +assign #(CLK_DELAY) CRMUSERCLKTXO_delay = CRMUSERCLKTXO; +assign #(CLK_DELAY) CRMUSERCLK_delay = CRMUSERCLK; + +assign #(in_delay) AUXPOWER_delay = AUXPOWER; +assign #(in_delay) CFGNEGOTIATEDLINKWIDTH_delay = CFGNEGOTIATEDLINKWIDTH; +assign #(in_delay) COMPLIANCEAVOID_delay = COMPLIANCEAVOID; +assign #(in_delay) CRMCFGBRIDGEHOTRESET_delay = CRMCFGBRIDGEHOTRESET; +assign #(in_delay) CRMLINKRSTN_delay = CRMLINKRSTN; +assign #(in_delay) CRMMACRSTN_delay = CRMMACRSTN; +assign #(in_delay) CRMMGMTRSTN_delay = CRMMGMTRSTN; +assign #(in_delay) CRMNVRSTN_delay = CRMNVRSTN; +assign #(in_delay) CRMTXHOTRESETN_delay = CRMTXHOTRESETN; +assign #(in_delay) CRMURSTN_delay = CRMURSTN; +assign #(in_delay) CRMUSERCFGRSTN_delay = CRMUSERCFGRSTN; +assign #(in_delay) CROSSLINKSEED_delay = CROSSLINKSEED; +assign #(in_delay) L0ACKNAKTIMERADJUSTMENT_delay = L0ACKNAKTIMERADJUSTMENT; +assign #(in_delay) L0ALLDOWNPORTSINL1_delay = L0ALLDOWNPORTSINL1; +assign #(in_delay) L0ALLDOWNRXPORTSINL0S_delay = L0ALLDOWNRXPORTSINL0S; +assign #(in_delay) L0ASE_delay = L0ASE; +assign #(in_delay) L0ASPORTCOUNT_delay = L0ASPORTCOUNT; +assign #(in_delay) L0ASTURNPOOLBITSCONSUMED_delay = L0ASTURNPOOLBITSCONSUMED; +assign #(in_delay) L0ATTENTIONBUTTONPRESSED_delay = L0ATTENTIONBUTTONPRESSED; +assign #(in_delay) L0CFGASSPANTREEOWNEDSTATE_delay = L0CFGASSPANTREEOWNEDSTATE; +assign #(in_delay) L0CFGASSTATECHANGECMD_delay = L0CFGASSTATECHANGECMD; +assign #(in_delay) L0CFGDISABLESCRAMBLE_delay = L0CFGDISABLESCRAMBLE; +assign #(in_delay) L0CFGEXTENDEDSYNC_delay = L0CFGEXTENDEDSYNC; +assign #(in_delay) L0CFGL0SENTRYENABLE_delay = L0CFGL0SENTRYENABLE; +assign #(in_delay) L0CFGL0SENTRYSUP_delay = L0CFGL0SENTRYSUP; +assign #(in_delay) L0CFGL0SEXITLAT_delay = L0CFGL0SEXITLAT; +assign #(in_delay) L0CFGLINKDISABLE_delay = L0CFGLINKDISABLE; +assign #(in_delay) L0CFGLOOPBACKMASTER_delay = L0CFGLOOPBACKMASTER; +assign #(in_delay) L0CFGNEGOTIATEDMAXP_delay = L0CFGNEGOTIATEDMAXP; +assign #(in_delay) L0CFGVCENABLE_delay = L0CFGVCENABLE; +assign #(in_delay) L0CFGVCID_delay = L0CFGVCID; +assign #(in_delay) L0DLLHOLDLINKUP_delay = L0DLLHOLDLINKUP; +assign #(in_delay) L0ELECTROMECHANICALINTERLOCKENGAGED_delay = L0ELECTROMECHANICALINTERLOCKENGAGED; +assign #(in_delay) L0FWDASSERTINTALEGACYINT_delay = L0FWDASSERTINTALEGACYINT; +assign #(in_delay) L0FWDASSERTINTBLEGACYINT_delay = L0FWDASSERTINTBLEGACYINT; +assign #(in_delay) L0FWDASSERTINTCLEGACYINT_delay = L0FWDASSERTINTCLEGACYINT; +assign #(in_delay) L0FWDASSERTINTDLEGACYINT_delay = L0FWDASSERTINTDLEGACYINT; +assign #(in_delay) L0FWDCORRERRIN_delay = L0FWDCORRERRIN; +assign #(in_delay) L0FWDDEASSERTINTALEGACYINT_delay = L0FWDDEASSERTINTALEGACYINT; +assign #(in_delay) L0FWDDEASSERTINTBLEGACYINT_delay = L0FWDDEASSERTINTBLEGACYINT; +assign #(in_delay) L0FWDDEASSERTINTCLEGACYINT_delay = L0FWDDEASSERTINTCLEGACYINT; +assign #(in_delay) L0FWDDEASSERTINTDLEGACYINT_delay = L0FWDDEASSERTINTDLEGACYINT; +assign #(in_delay) L0FWDFATALERRIN_delay = L0FWDFATALERRIN; +assign #(in_delay) L0FWDNONFATALERRIN_delay = L0FWDNONFATALERRIN; +assign #(in_delay) L0LEGACYINTFUNCT0_delay = L0LEGACYINTFUNCT0; +assign #(in_delay) L0MRLSENSORCLOSEDN_delay = L0MRLSENSORCLOSEDN; +assign #(in_delay) L0MSIREQUEST0_delay = L0MSIREQUEST0; +assign #(in_delay) L0PACKETHEADERFROMUSER_delay = L0PACKETHEADERFROMUSER; +assign #(in_delay) L0PMEREQIN_delay = L0PMEREQIN; +assign #(in_delay) L0PORTNUMBER_delay = L0PORTNUMBER; +assign #(in_delay) L0POWERFAULTDETECTED_delay = L0POWERFAULTDETECTED; +assign #(in_delay) L0PRESENCEDETECTSLOTEMPTYN_delay = L0PRESENCEDETECTSLOTEMPTYN; +assign #(in_delay) L0PWRNEWSTATEREQ_delay = L0PWRNEWSTATEREQ; +assign #(in_delay) L0PWRNEXTLINKSTATE_delay = L0PWRNEXTLINKSTATE; +assign #(in_delay) L0REPLAYTIMERADJUSTMENT_delay = L0REPLAYTIMERADJUSTMENT; +assign #(in_delay) L0ROOTTURNOFFREQ_delay = L0ROOTTURNOFFREQ; +assign #(in_delay) L0RXTLTLPNONINITIALIZEDVC_delay = L0RXTLTLPNONINITIALIZEDVC; +assign #(in_delay) L0SENDUNLOCKMESSAGE_delay = L0SENDUNLOCKMESSAGE; +assign #(in_delay) L0SETCOMPLETERABORTERROR_delay = L0SETCOMPLETERABORTERROR; +assign #(in_delay) L0SETCOMPLETIONTIMEOUTCORRERROR_delay = L0SETCOMPLETIONTIMEOUTCORRERROR; +assign #(in_delay) L0SETCOMPLETIONTIMEOUTUNCORRERROR_delay = L0SETCOMPLETIONTIMEOUTUNCORRERROR; +assign #(in_delay) L0SETDETECTEDCORRERROR_delay = L0SETDETECTEDCORRERROR; +assign #(in_delay) L0SETDETECTEDFATALERROR_delay = L0SETDETECTEDFATALERROR; +assign #(in_delay) L0SETDETECTEDNONFATALERROR_delay = L0SETDETECTEDNONFATALERROR; +assign #(in_delay) L0SETLINKDETECTEDPARITYERROR_delay = L0SETLINKDETECTEDPARITYERROR; +assign #(in_delay) L0SETLINKMASTERDATAPARITY_delay = L0SETLINKMASTERDATAPARITY; +assign #(in_delay) L0SETLINKRECEIVEDMASTERABORT_delay = L0SETLINKRECEIVEDMASTERABORT; +assign #(in_delay) L0SETLINKRECEIVEDTARGETABORT_delay = L0SETLINKRECEIVEDTARGETABORT; +assign #(in_delay) L0SETLINKSIGNALLEDTARGETABORT_delay = L0SETLINKSIGNALLEDTARGETABORT; +assign #(in_delay) L0SETLINKSYSTEMERROR_delay = L0SETLINKSYSTEMERROR; +assign #(in_delay) L0SETUNEXPECTEDCOMPLETIONCORRERROR_delay = L0SETUNEXPECTEDCOMPLETIONCORRERROR; +assign #(in_delay) L0SETUNEXPECTEDCOMPLETIONUNCORRERROR_delay = L0SETUNEXPECTEDCOMPLETIONUNCORRERROR; +assign #(in_delay) L0SETUNSUPPORTEDREQUESTNONPOSTEDERROR_delay = L0SETUNSUPPORTEDREQUESTNONPOSTEDERROR; +assign #(in_delay) L0SETUNSUPPORTEDREQUESTOTHERERROR_delay = L0SETUNSUPPORTEDREQUESTOTHERERROR; +assign #(in_delay) L0SETUSERDETECTEDPARITYERROR_delay = L0SETUSERDETECTEDPARITYERROR; +assign #(in_delay) L0SETUSERMASTERDATAPARITY_delay = L0SETUSERMASTERDATAPARITY; +assign #(in_delay) L0SETUSERRECEIVEDMASTERABORT_delay = L0SETUSERRECEIVEDMASTERABORT; +assign #(in_delay) L0SETUSERRECEIVEDTARGETABORT_delay = L0SETUSERRECEIVEDTARGETABORT; +assign #(in_delay) L0SETUSERSIGNALLEDTARGETABORT_delay = L0SETUSERSIGNALLEDTARGETABORT; +assign #(in_delay) L0SETUSERSYSTEMERROR_delay = L0SETUSERSYSTEMERROR; +assign #(in_delay) L0TLASFCCREDSTARVATION_delay = L0TLASFCCREDSTARVATION; +assign #(in_delay) L0TLLINKRETRAIN_delay = L0TLLINKRETRAIN; +assign #(in_delay) L0TRANSACTIONSPENDING_delay = L0TRANSACTIONSPENDING; +assign #(in_delay) L0TXBEACON_delay = L0TXBEACON; +assign #(in_delay) L0TXCFGPMTYPE_delay = L0TXCFGPMTYPE; +assign #(in_delay) L0TXCFGPM_delay = L0TXCFGPM; +assign #(in_delay) L0TXTLFCCMPLMCCRED_delay = L0TXTLFCCMPLMCCRED; +assign #(in_delay) L0TXTLFCCMPLMCUPDATE_delay = L0TXTLFCCMPLMCUPDATE; +assign #(in_delay) L0TXTLFCNPOSTBYPCRED_delay = L0TXTLFCNPOSTBYPCRED; +assign #(in_delay) L0TXTLFCNPOSTBYPUPDATE_delay = L0TXTLFCNPOSTBYPUPDATE; +assign #(in_delay) L0TXTLFCPOSTORDCRED_delay = L0TXTLFCPOSTORDCRED; +assign #(in_delay) L0TXTLFCPOSTORDUPDATE_delay = L0TXTLFCPOSTORDUPDATE; +assign #(in_delay) L0TXTLSBFCDATA_delay = L0TXTLSBFCDATA; +assign #(in_delay) L0TXTLSBFCUPDATE_delay = L0TXTLSBFCUPDATE; +assign #(in_delay) L0TXTLTLPDATA_delay = L0TXTLTLPDATA; +assign #(in_delay) L0TXTLTLPEDB_delay = L0TXTLTLPEDB; +assign #(in_delay) L0TXTLTLPENABLE_delay = L0TXTLTLPENABLE; +assign #(in_delay) L0TXTLTLPEND_delay = L0TXTLTLPEND; +assign #(in_delay) L0TXTLTLPLATENCY_delay = L0TXTLTLPLATENCY; +assign #(in_delay) L0TXTLTLPREQEND_delay = L0TXTLTLPREQEND; +assign #(in_delay) L0TXTLTLPREQ_delay = L0TXTLTLPREQ; +assign #(in_delay) L0TXTLTLPWIDTH_delay = L0TXTLTLPWIDTH; +assign #(in_delay) L0UPSTREAMRXPORTINL0S_delay = L0UPSTREAMRXPORTINL0S; +assign #(in_delay) L0VC0PREVIEWEXPAND_delay = L0VC0PREVIEWEXPAND; +assign #(in_delay) L0WAKEN_delay = L0WAKEN; +assign #(in_delay) LLKRXCHFIFO_delay = LLKRXCHFIFO; +assign #(in_delay) LLKRXCHTC_delay = LLKRXCHTC; +assign #(in_delay) LLKRXDSTCONTREQN_delay = LLKRXDSTCONTREQN; +assign #(in_delay) LLKRXDSTREQN_delay = LLKRXDSTREQN; +assign #(in_delay) LLKTX4DWHEADERN_delay = LLKTX4DWHEADERN; +assign #(in_delay) LLKTXCHFIFO_delay = LLKTXCHFIFO; +assign #(in_delay) LLKTXCHTC_delay = LLKTXCHTC; +assign #(in_delay) LLKTXCOMPLETEN_delay = LLKTXCOMPLETEN; +assign #(in_delay) LLKTXCREATEECRCN_delay = LLKTXCREATEECRCN; +assign #(in_delay) LLKTXDATA_delay = LLKTXDATA; +assign #(in_delay) LLKTXENABLEN_delay = LLKTXENABLEN; +assign #(in_delay) LLKTXEOFN_delay = LLKTXEOFN; +assign #(in_delay) LLKTXEOPN_delay = LLKTXEOPN; +assign #(in_delay) LLKTXSOFN_delay = LLKTXSOFN; +assign #(in_delay) LLKTXSOPN_delay = LLKTXSOPN; +assign #(in_delay) LLKTXSRCDSCN_delay = LLKTXSRCDSCN; +assign #(in_delay) LLKTXSRCRDYN_delay = LLKTXSRCRDYN; +assign #(in_delay) MAINPOWER_delay = MAINPOWER; +assign #(in_delay) MGMTADDR_delay = MGMTADDR; +assign #(in_delay) MGMTBWREN_delay = MGMTBWREN; +assign #(in_delay) MGMTRDEN_delay = MGMTRDEN; +assign #(in_delay) MGMTSTATSCREDITSEL_delay = MGMTSTATSCREDITSEL; +assign #(in_delay) MGMTWDATA_delay = MGMTWDATA; +assign #(in_delay) MGMTWREN_delay = MGMTWREN; +assign #(in_delay) MIMDLLBRDATA_delay = MIMDLLBRDATA; +assign #(in_delay) MIMRXBRDATA_delay = MIMRXBRDATA; +assign #(in_delay) MIMTXBRDATA_delay = MIMTXBRDATA; +assign #(in_delay) PIPEPHYSTATUSL0_delay = PIPEPHYSTATUSL0; +assign #(in_delay) PIPEPHYSTATUSL1_delay = PIPEPHYSTATUSL1; +assign #(in_delay) PIPEPHYSTATUSL2_delay = PIPEPHYSTATUSL2; +assign #(in_delay) PIPEPHYSTATUSL3_delay = PIPEPHYSTATUSL3; +assign #(in_delay) PIPEPHYSTATUSL4_delay = PIPEPHYSTATUSL4; +assign #(in_delay) PIPEPHYSTATUSL5_delay = PIPEPHYSTATUSL5; +assign #(in_delay) PIPEPHYSTATUSL6_delay = PIPEPHYSTATUSL6; +assign #(in_delay) PIPEPHYSTATUSL7_delay = PIPEPHYSTATUSL7; +assign #(in_delay) PIPERXCHANISALIGNEDL0_delay = PIPERXCHANISALIGNEDL0; +assign #(in_delay) PIPERXCHANISALIGNEDL1_delay = PIPERXCHANISALIGNEDL1; +assign #(in_delay) PIPERXCHANISALIGNEDL2_delay = PIPERXCHANISALIGNEDL2; +assign #(in_delay) PIPERXCHANISALIGNEDL3_delay = PIPERXCHANISALIGNEDL3; +assign #(in_delay) PIPERXCHANISALIGNEDL4_delay = PIPERXCHANISALIGNEDL4; +assign #(in_delay) PIPERXCHANISALIGNEDL5_delay = PIPERXCHANISALIGNEDL5; +assign #(in_delay) PIPERXCHANISALIGNEDL6_delay = PIPERXCHANISALIGNEDL6; +assign #(in_delay) PIPERXCHANISALIGNEDL7_delay = PIPERXCHANISALIGNEDL7; +assign #(in_delay) PIPERXDATAKL0_delay = PIPERXDATAKL0; +assign #(in_delay) PIPERXDATAKL1_delay = PIPERXDATAKL1; +assign #(in_delay) PIPERXDATAKL2_delay = PIPERXDATAKL2; +assign #(in_delay) PIPERXDATAKL3_delay = PIPERXDATAKL3; +assign #(in_delay) PIPERXDATAKL4_delay = PIPERXDATAKL4; +assign #(in_delay) PIPERXDATAKL5_delay = PIPERXDATAKL5; +assign #(in_delay) PIPERXDATAKL6_delay = PIPERXDATAKL6; +assign #(in_delay) PIPERXDATAKL7_delay = PIPERXDATAKL7; +assign #(in_delay) PIPERXDATAL0_delay = PIPERXDATAL0; +assign #(in_delay) PIPERXDATAL1_delay = PIPERXDATAL1; +assign #(in_delay) PIPERXDATAL2_delay = PIPERXDATAL2; +assign #(in_delay) PIPERXDATAL3_delay = PIPERXDATAL3; +assign #(in_delay) PIPERXDATAL4_delay = PIPERXDATAL4; +assign #(in_delay) PIPERXDATAL5_delay = PIPERXDATAL5; +assign #(in_delay) PIPERXDATAL6_delay = PIPERXDATAL6; +assign #(in_delay) PIPERXDATAL7_delay = PIPERXDATAL7; +assign #(in_delay) PIPERXELECIDLEL0_delay = PIPERXELECIDLEL0; +assign #(in_delay) PIPERXELECIDLEL1_delay = PIPERXELECIDLEL1; +assign #(in_delay) PIPERXELECIDLEL2_delay = PIPERXELECIDLEL2; +assign #(in_delay) PIPERXELECIDLEL3_delay = PIPERXELECIDLEL3; +assign #(in_delay) PIPERXELECIDLEL4_delay = PIPERXELECIDLEL4; +assign #(in_delay) PIPERXELECIDLEL5_delay = PIPERXELECIDLEL5; +assign #(in_delay) PIPERXELECIDLEL6_delay = PIPERXELECIDLEL6; +assign #(in_delay) PIPERXELECIDLEL7_delay = PIPERXELECIDLEL7; +assign #(in_delay) PIPERXSTATUSL0_delay = PIPERXSTATUSL0; +assign #(in_delay) PIPERXSTATUSL1_delay = PIPERXSTATUSL1; +assign #(in_delay) PIPERXSTATUSL2_delay = PIPERXSTATUSL2; +assign #(in_delay) PIPERXSTATUSL3_delay = PIPERXSTATUSL3; +assign #(in_delay) PIPERXSTATUSL4_delay = PIPERXSTATUSL4; +assign #(in_delay) PIPERXSTATUSL5_delay = PIPERXSTATUSL5; +assign #(in_delay) PIPERXSTATUSL6_delay = PIPERXSTATUSL6; +assign #(in_delay) PIPERXSTATUSL7_delay = PIPERXSTATUSL7; +assign #(in_delay) PIPERXVALIDL0_delay = PIPERXVALIDL0; +assign #(in_delay) PIPERXVALIDL1_delay = PIPERXVALIDL1; +assign #(in_delay) PIPERXVALIDL2_delay = PIPERXVALIDL2; +assign #(in_delay) PIPERXVALIDL3_delay = PIPERXVALIDL3; +assign #(in_delay) PIPERXVALIDL4_delay = PIPERXVALIDL4; +assign #(in_delay) PIPERXVALIDL5_delay = PIPERXVALIDL5; +assign #(in_delay) PIPERXVALIDL6_delay = PIPERXVALIDL6; +assign #(in_delay) PIPERXVALIDL7_delay = PIPERXVALIDL7; + +PCIE_INTERNAL_1_1_SWIFT pcie_internal_1_1_swift_1 ( + .MCACTIVELANESIN (ACTIVELANESIN), + .MCAERBASEPTR (AERBASEPTR), + .MCAERCAPABILITYECRCCHECKCAPABLE (AERCAPABILITYECRCCHECKCAPABLE_BINARY), + .MCAERCAPABILITYECRCGENCAPABLE (AERCAPABILITYECRCGENCAPABLE_BINARY), + .MCAERCAPABILITYNEXTPTR (AERCAPABILITYNEXTPTR), + .MCBAR0ADDRWIDTH (BAR0ADDRWIDTH_BINARY), + .MCBAR0EXIST (BAR0EXIST_BINARY), + .MCBAR0IOMEMN (BAR0IOMEMN_BINARY), + .MCBAR0MASKWIDTH (BAR0MASKWIDTH), + .MCBAR0PREFETCHABLE (BAR0PREFETCHABLE_BINARY), + .MCBAR1ADDRWIDTH (BAR1ADDRWIDTH_BINARY), + .MCBAR1EXIST (BAR1EXIST_BINARY), + .MCBAR1IOMEMN (BAR1IOMEMN_BINARY), + .MCBAR1MASKWIDTH (BAR1MASKWIDTH), + .MCBAR1PREFETCHABLE (BAR1PREFETCHABLE_BINARY), + .MCBAR2ADDRWIDTH (BAR2ADDRWIDTH_BINARY), + .MCBAR2EXIST (BAR2EXIST_BINARY), + .MCBAR2IOMEMN (BAR2IOMEMN_BINARY), + .MCBAR2MASKWIDTH (BAR2MASKWIDTH), + .MCBAR2PREFETCHABLE (BAR2PREFETCHABLE_BINARY), + .MCBAR3ADDRWIDTH (BAR3ADDRWIDTH_BINARY), + .MCBAR3EXIST (BAR3EXIST_BINARY), + .MCBAR3IOMEMN (BAR3IOMEMN_BINARY), + .MCBAR3MASKWIDTH (BAR3MASKWIDTH), + .MCBAR3PREFETCHABLE (BAR3PREFETCHABLE_BINARY), + .MCBAR4ADDRWIDTH (BAR4ADDRWIDTH_BINARY), + .MCBAR4EXIST (BAR4EXIST_BINARY), + .MCBAR4IOMEMN (BAR4IOMEMN_BINARY), + .MCBAR4MASKWIDTH (BAR4MASKWIDTH), + .MCBAR4PREFETCHABLE (BAR4PREFETCHABLE_BINARY), + .MCBAR5ADDRWIDTH (1'b0), + .MCBAR5EXIST (BAR5EXIST_BINARY), + .MCBAR5IOMEMN (BAR5IOMEMN_BINARY), + .MCBAR5MASKWIDTH (BAR5MASKWIDTH), + .MCBAR5PREFETCHABLE (BAR5PREFETCHABLE_BINARY), + .MCCAPABILITIESPOINTER (CAPABILITIESPOINTER), + .MCCARDBUSCISPOINTER (CARDBUSCISPOINTER), + .MCCLASSCODE (CLASSCODE), + .MCCONFIGROUTING (CONFIGROUTING), + .MCDEVICECAPABILITYENDPOINTL0SLATENCY (DEVICECAPABILITYENDPOINTL0SLATENCY), + .MCDEVICECAPABILITYENDPOINTL1LATENCY (DEVICECAPABILITYENDPOINTL1LATENCY), + .MCDEVICEID (DEVICEID), + .MCDEVICESERIALNUMBER (DEVICESERIALNUMBER), + .MCDSNBASEPTR (DSNBASEPTR), + .MCDSNCAPABILITYNEXTPTR (DSNCAPABILITYNEXTPTR), + .MCDUALCOREENABLE (DUALCOREENABLE_BINARY), + .MCDUALCORESLAVE (DUALCORESLAVE_BINARY), + .MCDUALROLECFGCNTRLROOTEPN (DUALROLECFGCNTRLROOTEPN_BINARY), + .MCEXTCFGCAPPTR (EXTCFGCAPPTR), + .MCEXTCFGXPCAPPTR (EXTCFGXPCAPPTR), + .MCHEADERTYPE (HEADERTYPE), + .MCINFINITECOMPLETIONS (INFINITECOMPLETIONS_BINARY), + .MCINTERRUPTPIN (INTERRUPTPIN), + .MCISSWITCH (ISSWITCH_BINARY), + .MCL0SEXITLATENCY (L0SEXITLATENCY_BINARY), + .MCL0SEXITLATENCYCOMCLK (L0SEXITLATENCYCOMCLK_BINARY), + .MCL1EXITLATENCY (L1EXITLATENCY_BINARY), + .MCL1EXITLATENCYCOMCLK (L1EXITLATENCYCOMCLK_BINARY), + .MCLINKCAPABILITYASPMSUPPORT (LINKCAPABILITYASPMSUPPORT), + .MCLINKCAPABILITYMAXLINKWIDTH (LINKCAPABILITYMAXLINKWIDTH), + .MCLINKSTATUSSLOTCLOCKCONFIG (LINKSTATUSSLOTCLOCKCONFIG_BINARY), + .MCLLKBYPASS (LLKBYPASS_BINARY), + .MCLOWPRIORITYVCCOUNT (LOWPRIORITYVCCOUNT_BINARY), + .MCMSIBASEPTR (MSIBASEPTR), + .MCMSICAPABILITYMULTIMSGCAP (MSICAPABILITYMULTIMSGCAP), + .MCMSICAPABILITYNEXTPTR (MSICAPABILITYNEXTPTR), + .MCPBBASEPTR (PBBASEPTR), + .MCPBCAPABILITYDW0BASEPOWER (PBCAPABILITYDW0BASEPOWER), + .MCPBCAPABILITYDW0DATASCALE (PBCAPABILITYDW0DATASCALE), + .MCPBCAPABILITYDW0PMSTATE (PBCAPABILITYDW0PMSTATE), + .MCPBCAPABILITYDW0PMSUBSTATE (PBCAPABILITYDW0PMSUBSTATE), + .MCPBCAPABILITYDW0POWERRAIL (PBCAPABILITYDW0POWERRAIL), + .MCPBCAPABILITYDW0TYPE (PBCAPABILITYDW0TYPE), + .MCPBCAPABILITYDW1BASEPOWER (PBCAPABILITYDW1BASEPOWER), + .MCPBCAPABILITYDW1DATASCALE (PBCAPABILITYDW1DATASCALE), + .MCPBCAPABILITYDW1PMSTATE (PBCAPABILITYDW1PMSTATE), + .MCPBCAPABILITYDW1PMSUBSTATE (PBCAPABILITYDW1PMSUBSTATE), + .MCPBCAPABILITYDW1POWERRAIL (PBCAPABILITYDW1POWERRAIL), + .MCPBCAPABILITYDW1TYPE (PBCAPABILITYDW1TYPE), + .MCPBCAPABILITYDW2BASEPOWER (PBCAPABILITYDW2BASEPOWER), + .MCPBCAPABILITYDW2DATASCALE (PBCAPABILITYDW2DATASCALE), + .MCPBCAPABILITYDW2PMSTATE (PBCAPABILITYDW2PMSTATE), + .MCPBCAPABILITYDW2PMSUBSTATE (PBCAPABILITYDW2PMSUBSTATE), + .MCPBCAPABILITYDW2POWERRAIL (PBCAPABILITYDW2POWERRAIL), + .MCPBCAPABILITYDW2TYPE (PBCAPABILITYDW2TYPE), + .MCPBCAPABILITYDW3BASEPOWER (PBCAPABILITYDW3BASEPOWER), + .MCPBCAPABILITYDW3DATASCALE (PBCAPABILITYDW3DATASCALE), + .MCPBCAPABILITYDW3PMSTATE (PBCAPABILITYDW3PMSTATE), + .MCPBCAPABILITYDW3PMSUBSTATE (PBCAPABILITYDW3PMSUBSTATE), + .MCPBCAPABILITYDW3POWERRAIL (PBCAPABILITYDW3POWERRAIL), + .MCPBCAPABILITYDW3TYPE (PBCAPABILITYDW3TYPE), + .MCPBCAPABILITYNEXTPTR (PBCAPABILITYNEXTPTR), + .MCPBCAPABILITYSYSTEMALLOCATED (PBCAPABILITYSYSTEMALLOCATED_BINARY), + .MCPCIECAPABILITYINTMSGNUM (PCIECAPABILITYINTMSGNUM), + .MCPCIECAPABILITYNEXTPTR (PCIECAPABILITYNEXTPTR), + .MCPCIECAPABILITYSLOTIMPL (PCIECAPABILITYSLOTIMPL_BINARY), + .MCPCIEREVISION (PCIEREVISION_BINARY), + .MCPMBASEPTR (PMBASEPTR), + .MCPMCAPABILITYAUXCURRENT (PMCAPABILITYAUXCURRENT), + .MCPMCAPABILITYD1SUPPORT (PMCAPABILITYD1SUPPORT_BINARY), + .MCPMCAPABILITYD2SUPPORT (PMCAPABILITYD2SUPPORT_BINARY), + .MCPMCAPABILITYDSI (PMCAPABILITYDSI_BINARY), + .MCPMCAPABILITYNEXTPTR (PMCAPABILITYNEXTPTR), + .MCPMCAPABILITYPMESUPPORT (PMCAPABILITYPMESUPPORT), + .MCPMDATA0 (PMDATA0), + .MCPMDATA1 (PMDATA1), + .MCPMDATA2 (PMDATA2), + .MCPMDATA3 (PMDATA3), + .MCPMDATA4 (PMDATA4), + .MCPMDATA5 (PMDATA5), + .MCPMDATA6 (PMDATA6), + .MCPMDATA7 (PMDATA7), + .MCPMDATA8 (PMDATA8), + .MCPMDATASCALE0 (PMDATASCALE0_BINARY), + .MCPMDATASCALE1 (PMDATASCALE1_BINARY), + .MCPMDATASCALE2 (PMDATASCALE2_BINARY), + .MCPMDATASCALE3 (PMDATASCALE3_BINARY), + .MCPMDATASCALE4 (PMDATASCALE4_BINARY), + .MCPMDATASCALE5 (PMDATASCALE5_BINARY), + .MCPMDATASCALE6 (PMDATASCALE6_BINARY), + .MCPMDATASCALE7 (PMDATASCALE7_BINARY), + .MCPMDATASCALE8 (PMDATASCALE8_BINARY), + .MCPMSTATUSCONTROLDATASCALE (PMSTATUSCONTROLDATASCALE), + .MCPORTVCCAPABILITYEXTENDEDVCCOUNT (PORTVCCAPABILITYEXTENDEDVCCOUNT), + .MCPORTVCCAPABILITYVCARBCAP (PORTVCCAPABILITYVCARBCAP), + .MCPORTVCCAPABILITYVCARBTABLEOFFSET (PORTVCCAPABILITYVCARBTABLEOFFSET), + .MCRAMSHARETXRX (RAMSHARETXRX_BINARY), + .MCRESETMODE (RESETMODE_BINARY), + .MCRETRYRAMREADLATENCY (RETRYRAMREADLATENCY_BINARY), + .MCRETRYRAMSIZE (RETRYRAMSIZE), + .MCRETRYRAMWIDTH (RETRYRAMWIDTH_BINARY), + .MCRETRYRAMWRITELATENCY (RETRYRAMWRITELATENCY_BINARY), + .MCRETRYREADADDRPIPE (RETRYREADADDRPIPE_BINARY), + .MCRETRYREADDATAPIPE (RETRYREADDATAPIPE_BINARY), + .MCRETRYWRITEPIPE (RETRYWRITEPIPE_BINARY), + .MCREVISIONID (REVISIONID), + .MCRXREADADDRPIPE (RXREADADDRPIPE_BINARY), + .MCRXREADDATAPIPE (RXREADDATAPIPE_BINARY), + .MCRXWRITEPIPE (RXWRITEPIPE_BINARY), + .MCSELECTASMODE (SELECTASMODE_BINARY), + .MCSELECTDLLIF (SELECTDLLIF_BINARY), + .MCSLOTCAPABILITYATTBUTTONPRESENT (SLOTCAPABILITYATTBUTTONPRESENT_BINARY), + .MCSLOTCAPABILITYATTINDICATORPRESENT (SLOTCAPABILITYATTINDICATORPRESENT_BINARY), + .MCSLOTCAPABILITYHOTPLUGCAPABLE (SLOTCAPABILITYHOTPLUGCAPABLE_BINARY), + .MCSLOTCAPABILITYHOTPLUGSURPRISE (SLOTCAPABILITYHOTPLUGSURPRISE_BINARY), + .MCSLOTCAPABILITYMSLSENSORPRESENT (SLOTCAPABILITYMSLSENSORPRESENT_BINARY), + .MCSLOTCAPABILITYPHYSICALSLOTNUM (SLOTCAPABILITYPHYSICALSLOTNUM), + .MCSLOTCAPABILITYPOWERCONTROLLERPRESENT (SLOTCAPABILITYPOWERCONTROLLERPRESENT_BINARY), + .MCSLOTCAPABILITYPOWERINDICATORPRESENT (SLOTCAPABILITYPOWERINDICATORPRESENT_BINARY), + .MCSLOTCAPABILITYSLOTPOWERLIMITSCALE (SLOTCAPABILITYSLOTPOWERLIMITSCALE), + .MCSLOTCAPABILITYSLOTPOWERLIMITVALUE (SLOTCAPABILITYSLOTPOWERLIMITVALUE), + .MCSLOTIMPLEMENTED (SLOTIMPLEMENTED_BINARY), + .MCSUBSYSTEMID (SUBSYSTEMID), + .MCSUBSYSTEMVENDORID (SUBSYSTEMVENDORID), + .MCTLRAMREADLATENCY (TLRAMREADLATENCY_BINARY), + .MCTLRAMWIDTH (TLRAMWIDTH_BINARY), + .MCTLRAMWRITELATENCY (TLRAMWRITELATENCY_BINARY), + .MCTXREADADDRPIPE (TXREADADDRPIPE_BINARY), + .MCTXREADDATAPIPE (TXREADDATAPIPE_BINARY), + .MCTXTSNFTS (TXTSNFTS_BINARY), + .MCTXTSNFTSCOMCLK (TXTSNFTSCOMCLK_BINARY), + .MCTXWRITEPIPE (TXWRITEPIPE_BINARY), + .MCUPSTREAMFACING (UPSTREAMFACING_BINARY), + .MCVC0RXFIFOBASEC (VC0RXFIFOBASEC), + .MCVC0RXFIFOBASENP (VC0RXFIFOBASENP), + .MCVC0RXFIFOBASEP (VC0RXFIFOBASEP), + .MCVC0RXFIFOLIMITC (VC0RXFIFOLIMITC), + .MCVC0RXFIFOLIMITNP (VC0RXFIFOLIMITNP), + .MCVC0RXFIFOLIMITP (VC0RXFIFOLIMITP), + .MCVC0TOTALCREDITSCD (VC0TOTALCREDITSCD), + .MCVC0TOTALCREDITSCH (VC0TOTALCREDITSCH), + .MCVC0TOTALCREDITSNPH (VC0TOTALCREDITSNPH), + .MCVC0TOTALCREDITSPD (VC0TOTALCREDITSPD), + .MCVC0TOTALCREDITSPH (VC0TOTALCREDITSPH), + .MCVC0TXFIFOBASEC (VC0TXFIFOBASEC), + .MCVC0TXFIFOBASENP (VC0TXFIFOBASENP), + .MCVC0TXFIFOBASEP (VC0TXFIFOBASEP), + .MCVC0TXFIFOLIMITC (VC0TXFIFOLIMITC), + .MCVC0TXFIFOLIMITNP (VC0TXFIFOLIMITNP), + .MCVC0TXFIFOLIMITP (VC0TXFIFOLIMITP), + .MCVC1RXFIFOBASEC (VC1RXFIFOBASEC), + .MCVC1RXFIFOBASENP (VC1RXFIFOBASENP), + .MCVC1RXFIFOBASEP (VC1RXFIFOBASEP), + .MCVC1RXFIFOLIMITC (VC1RXFIFOLIMITC), + .MCVC1RXFIFOLIMITNP (VC1RXFIFOLIMITNP), + .MCVC1RXFIFOLIMITP (VC1RXFIFOLIMITP), + .MCVC1TOTALCREDITSCD (VC1TOTALCREDITSCD), + .MCVC1TOTALCREDITSCH (VC1TOTALCREDITSCH), + .MCVC1TOTALCREDITSNPH (VC1TOTALCREDITSNPH), + .MCVC1TOTALCREDITSPD (VC1TOTALCREDITSPD), + .MCVC1TOTALCREDITSPH (VC1TOTALCREDITSPH), + .MCVC1TXFIFOBASEC (VC1TXFIFOBASEC), + .MCVC1TXFIFOBASENP (VC1TXFIFOBASENP), + .MCVC1TXFIFOBASEP (VC1TXFIFOBASEP), + .MCVC1TXFIFOLIMITC (VC1TXFIFOLIMITC), + .MCVC1TXFIFOLIMITNP (VC1TXFIFOLIMITNP), + .MCVC1TXFIFOLIMITP (VC1TXFIFOLIMITP), + .MCVCBASEPTR (VCBASEPTR), + .MCVCCAPABILITYNEXTPTR (VCCAPABILITYNEXTPTR), + .MCVENDORID (VENDORID), + .MCXLINKSUPPORTED (XLINKSUPPORTED_BINARY), + .MCXPBASEPTR (XPBASEPTR), + .MCXPDEVICEPORTTYPE (XPDEVICEPORTTYPE), + .MCXPMAXPAYLOAD (XPMAXPAYLOAD_BINARY), + .MCXPRCBCONTROL (XPRCBCONTROL_BINARY), + + .BUSMASTERENABLE (BUSMASTERENABLE_delay), + .CRMDOHOTRESETN (CRMDOHOTRESETN_delay), + .CRMPWRSOFTRESETN (CRMPWRSOFTRESETN_delay), + .CRMRXHOTRESETN (CRMRXHOTRESETN_delay), + .DLLTXPMDLLPOUTSTANDING (DLLTXPMDLLPOUTSTANDING_delay), + .INTERRUPTDISABLE (INTERRUPTDISABLE_delay), + .IOSPACEENABLE (IOSPACEENABLE_delay), + .L0ASAUTONOMOUSINITCOMPLETED (L0ASAUTONOMOUSINITCOMPLETED_delay), + .L0ATTENTIONINDICATORCONTROL (L0ATTENTIONINDICATORCONTROL_delay), + .L0CFGLOOPBACKACK (L0CFGLOOPBACKACK_delay), + .L0COMPLETERID (L0COMPLETERID_delay), + .L0CORRERRMSGRCVD (L0CORRERRMSGRCVD_delay), + .L0DLLASRXSTATE (L0DLLASRXSTATE_delay), + .L0DLLASTXSTATE (L0DLLASTXSTATE_delay), + .L0DLLERRORVECTOR (L0DLLERRORVECTOR_delay), + .L0DLLRXACKOUTSTANDING (L0DLLRXACKOUTSTANDING_delay), + .L0DLLTXNONFCOUTSTANDING (L0DLLTXNONFCOUTSTANDING_delay), + .L0DLLTXOUTSTANDING (L0DLLTXOUTSTANDING_delay), + .L0DLLVCSTATUS (L0DLLVCSTATUS_delay), + .L0DLUPDOWN (L0DLUPDOWN_delay), + .L0ERRMSGREQID (L0ERRMSGREQID_delay), + .L0FATALERRMSGRCVD (L0FATALERRMSGRCVD_delay), + .L0FIRSTCFGWRITEOCCURRED (L0FIRSTCFGWRITEOCCURRED_delay), + .L0FWDCORRERROUT (L0FWDCORRERROUT_delay), + .L0FWDFATALERROUT (L0FWDFATALERROUT_delay), + .L0FWDNONFATALERROUT (L0FWDNONFATALERROUT_delay), + .L0LTSSMSTATE (L0LTSSMSTATE_delay), + .L0MACENTEREDL0 (L0MACENTEREDL0_delay), + .L0MACLINKTRAINING (L0MACLINKTRAINING_delay), + .L0MACLINKUP (L0MACLINKUP_delay), + .L0MACNEGOTIATEDLINKWIDTH (L0MACNEGOTIATEDLINKWIDTH_delay), + .L0MACNEWSTATEACK (L0MACNEWSTATEACK_delay), + .L0MACRXL0SSTATE (L0MACRXL0SSTATE_delay), + .L0MACUPSTREAMDOWNSTREAM (L0MACUPSTREAMDOWNSTREAM_delay), + .L0MCFOUND (L0MCFOUND_delay), + .L0MSIENABLE0 (L0MSIENABLE0_delay), + .L0MULTIMSGEN0 (L0MULTIMSGEN0_delay), + .L0NONFATALERRMSGRCVD (L0NONFATALERRMSGRCVD_delay), + .L0PMEACK (L0PMEACK_delay), + .L0PMEEN (L0PMEEN_delay), + .L0PMEREQOUT (L0PMEREQOUT_delay), + .L0POWERCONTROLLERCONTROL (L0POWERCONTROLLERCONTROL_delay), + .L0POWERINDICATORCONTROL (L0POWERINDICATORCONTROL_delay), + .L0PWRINHIBITTRANSFERS (L0PWRINHIBITTRANSFERS_delay), + .L0PWRL1STATE (L0PWRL1STATE_delay), + .L0PWRL23READYDEVICE (L0PWRL23READYDEVICE_delay), + .L0PWRL23READYSTATE (L0PWRL23READYSTATE_delay), + .L0PWRSTATE0 (L0PWRSTATE0_delay), + .L0PWRTURNOFFREQ (L0PWRTURNOFFREQ_delay), + .L0PWRTXL0SSTATE (L0PWRTXL0SSTATE_delay), + .L0RECEIVEDASSERTINTALEGACYINT (L0RECEIVEDASSERTINTALEGACYINT_delay), + .L0RECEIVEDASSERTINTBLEGACYINT (L0RECEIVEDASSERTINTBLEGACYINT_delay), + .L0RECEIVEDASSERTINTCLEGACYINT (L0RECEIVEDASSERTINTCLEGACYINT_delay), + .L0RECEIVEDASSERTINTDLEGACYINT (L0RECEIVEDASSERTINTDLEGACYINT_delay), + .L0RECEIVEDDEASSERTINTALEGACYINT (L0RECEIVEDDEASSERTINTALEGACYINT_delay), + .L0RECEIVEDDEASSERTINTBLEGACYINT (L0RECEIVEDDEASSERTINTBLEGACYINT_delay), + .L0RECEIVEDDEASSERTINTCLEGACYINT (L0RECEIVEDDEASSERTINTCLEGACYINT_delay), + .L0RECEIVEDDEASSERTINTDLEGACYINT (L0RECEIVEDDEASSERTINTDLEGACYINT_delay), + .L0RXBEACON (L0RXBEACON_delay), + .L0RXDLLFCCMPLMCCRED (L0RXDLLFCCMPLMCCRED_delay), + .L0RXDLLFCCMPLMCUPDATE (L0RXDLLFCCMPLMCUPDATE_delay), + .L0RXDLLFCNPOSTBYPCRED (L0RXDLLFCNPOSTBYPCRED_delay), + .L0RXDLLFCNPOSTBYPUPDATE (L0RXDLLFCNPOSTBYPUPDATE_delay), + .L0RXDLLFCPOSTORDCRED (L0RXDLLFCPOSTORDCRED_delay), + .L0RXDLLFCPOSTORDUPDATE (L0RXDLLFCPOSTORDUPDATE_delay), + .L0RXDLLPM (L0RXDLLPM_delay), + .L0RXDLLPMTYPE (L0RXDLLPMTYPE_delay), + .L0RXDLLSBFCDATA (L0RXDLLSBFCDATA_delay), + .L0RXDLLSBFCUPDATE (L0RXDLLSBFCUPDATE_delay), + .L0RXDLLTLPECRCOK (L0RXDLLTLPECRCOK_delay), + .L0RXDLLTLPEND (L0RXDLLTLPEND_delay), + .L0RXMACLINKERROR (L0RXMACLINKERROR_delay), + .L0STATSCFGOTHERRECEIVED (L0STATSCFGOTHERRECEIVED_delay), + .L0STATSCFGOTHERTRANSMITTED (L0STATSCFGOTHERTRANSMITTED_delay), + .L0STATSCFGRECEIVED (L0STATSCFGRECEIVED_delay), + .L0STATSCFGTRANSMITTED (L0STATSCFGTRANSMITTED_delay), + .L0STATSDLLPRECEIVED (L0STATSDLLPRECEIVED_delay), + .L0STATSDLLPTRANSMITTED (L0STATSDLLPTRANSMITTED_delay), + .L0STATSOSRECEIVED (L0STATSOSRECEIVED_delay), + .L0STATSOSTRANSMITTED (L0STATSOSTRANSMITTED_delay), + .L0STATSTLPRECEIVED (L0STATSTLPRECEIVED_delay), + .L0STATSTLPTRANSMITTED (L0STATSTLPTRANSMITTED_delay), + .L0TOGGLEELECTROMECHANICALINTERLOCK (L0TOGGLEELECTROMECHANICALINTERLOCK_delay), + .L0TRANSFORMEDVC (L0TRANSFORMEDVC_delay), + .L0TXDLLFCCMPLMCUPDATED (L0TXDLLFCCMPLMCUPDATED_delay), + .L0TXDLLFCNPOSTBYPUPDATED (L0TXDLLFCNPOSTBYPUPDATED_delay), + .L0TXDLLFCPOSTORDUPDATED (L0TXDLLFCPOSTORDUPDATED_delay), + .L0TXDLLPMUPDATED (L0TXDLLPMUPDATED_delay), + .L0TXDLLSBFCUPDATED (L0TXDLLSBFCUPDATED_delay), + .L0UCBYPFOUND (L0UCBYPFOUND_delay), + .L0UCORDFOUND (L0UCORDFOUND_delay), + .L0UNLOCKRECEIVED (L0UNLOCKRECEIVED_delay), + .LLKRX4DWHEADERN (LLKRX4DWHEADERN_delay), + .LLKRXCHCOMPLETIONAVAILABLEN (LLKRXCHCOMPLETIONAVAILABLEN_delay), + .LLKRXCHCOMPLETIONPARTIALN (LLKRXCHCOMPLETIONPARTIALN_delay), + .LLKRXCHCONFIGAVAILABLEN (LLKRXCHCONFIGAVAILABLEN_delay), + .LLKRXCHCONFIGPARTIALN (LLKRXCHCONFIGPARTIALN_delay), + .LLKRXCHNONPOSTEDAVAILABLEN (LLKRXCHNONPOSTEDAVAILABLEN_delay), + .LLKRXCHNONPOSTEDPARTIALN (LLKRXCHNONPOSTEDPARTIALN_delay), + .LLKRXCHPOSTEDAVAILABLEN (LLKRXCHPOSTEDAVAILABLEN_delay), + .LLKRXCHPOSTEDPARTIALN (LLKRXCHPOSTEDPARTIALN_delay), + .LLKRXDATA (LLKRXDATA_delay), + .LLKRXECRCBADN (LLKRXECRCBADN_delay), + .LLKRXEOFN (LLKRXEOFN_delay), + .LLKRXEOPN (LLKRXEOPN_delay), + .LLKRXPREFERREDTYPE (LLKRXPREFERREDTYPE_delay), + .LLKRXSOFN (LLKRXSOFN_delay), + .LLKRXSOPN (LLKRXSOPN_delay), + .LLKRXSRCDSCN (LLKRXSRCDSCN_delay), + .LLKRXSRCLASTREQN (LLKRXSRCLASTREQN_delay), + .LLKRXSRCRDYN (LLKRXSRCRDYN_delay), + .LLKRXVALIDN (LLKRXVALIDN_delay), + .LLKTCSTATUS (LLKTCSTATUS_delay), + .LLKTXCHANSPACE (LLKTXCHANSPACE_delay), + .LLKTXCHCOMPLETIONREADYN (LLKTXCHCOMPLETIONREADYN_delay), + .LLKTXCHNONPOSTEDREADYN (LLKTXCHNONPOSTEDREADYN_delay), + .LLKTXCHPOSTEDREADYN (LLKTXCHPOSTEDREADYN_delay), + .LLKTXCONFIGREADYN (LLKTXCONFIGREADYN_delay), + .LLKTXDSTRDYN (LLKTXDSTRDYN_delay), + .MAXPAYLOADSIZE (MAXPAYLOADSIZE_delay), + .MAXREADREQUESTSIZE (MAXREADREQUESTSIZE_delay), + .MEMSPACEENABLE (MEMSPACEENABLE_delay), + .MGMTPSO (MGMTPSO_delay), + .MGMTRDATA (MGMTRDATA_delay), + .MGMTSTATSCREDIT (MGMTSTATSCREDIT_delay), + .MIMDLLBRADD (MIMDLLBRADD_delay), + .MIMDLLBREN (MIMDLLBREN_delay), + .MIMDLLBWADD (MIMDLLBWADD_delay), + .MIMDLLBWDATA (MIMDLLBWDATA_delay), + .MIMDLLBWEN (MIMDLLBWEN_delay), + .MIMRXBRADD (MIMRXBRADD_delay), + .MIMRXBREN (MIMRXBREN_delay), + .MIMRXBWADD (MIMRXBWADD_delay), + .MIMRXBWDATA (MIMRXBWDATA_delay), + .MIMRXBWEN (MIMRXBWEN_delay), + .MIMTXBRADD (MIMTXBRADD_delay), + .MIMTXBREN (MIMTXBREN_delay), + .MIMTXBWADD (MIMTXBWADD_delay), + .MIMTXBWDATA (MIMTXBWDATA_delay), + .MIMTXBWEN (MIMTXBWEN_delay), + .PARITYERRORRESPONSE (PARITYERRORRESPONSE_delay), + .PIPEDESKEWLANESL0 (PIPEDESKEWLANESL0_delay), + .PIPEDESKEWLANESL1 (PIPEDESKEWLANESL1_delay), + .PIPEDESKEWLANESL2 (PIPEDESKEWLANESL2_delay), + .PIPEDESKEWLANESL3 (PIPEDESKEWLANESL3_delay), + .PIPEDESKEWLANESL4 (PIPEDESKEWLANESL4_delay), + .PIPEDESKEWLANESL5 (PIPEDESKEWLANESL5_delay), + .PIPEDESKEWLANESL6 (PIPEDESKEWLANESL6_delay), + .PIPEDESKEWLANESL7 (PIPEDESKEWLANESL7_delay), + .PIPEPOWERDOWNL0 (PIPEPOWERDOWNL0_delay), + .PIPEPOWERDOWNL1 (PIPEPOWERDOWNL1_delay), + .PIPEPOWERDOWNL2 (PIPEPOWERDOWNL2_delay), + .PIPEPOWERDOWNL3 (PIPEPOWERDOWNL3_delay), + .PIPEPOWERDOWNL4 (PIPEPOWERDOWNL4_delay), + .PIPEPOWERDOWNL5 (PIPEPOWERDOWNL5_delay), + .PIPEPOWERDOWNL6 (PIPEPOWERDOWNL6_delay), + .PIPEPOWERDOWNL7 (PIPEPOWERDOWNL7_delay), + .PIPERESETL0 (PIPERESETL0_delay), + .PIPERESETL1 (PIPERESETL1_delay), + .PIPERESETL2 (PIPERESETL2_delay), + .PIPERESETL3 (PIPERESETL3_delay), + .PIPERESETL4 (PIPERESETL4_delay), + .PIPERESETL5 (PIPERESETL5_delay), + .PIPERESETL6 (PIPERESETL6_delay), + .PIPERESETL7 (PIPERESETL7_delay), + .PIPERXPOLARITYL0 (PIPERXPOLARITYL0_delay), + .PIPERXPOLARITYL1 (PIPERXPOLARITYL1_delay), + .PIPERXPOLARITYL2 (PIPERXPOLARITYL2_delay), + .PIPERXPOLARITYL3 (PIPERXPOLARITYL3_delay), + .PIPERXPOLARITYL4 (PIPERXPOLARITYL4_delay), + .PIPERXPOLARITYL5 (PIPERXPOLARITYL5_delay), + .PIPERXPOLARITYL6 (PIPERXPOLARITYL6_delay), + .PIPERXPOLARITYL7 (PIPERXPOLARITYL7_delay), + .PIPETXCOMPLIANCEL0 (PIPETXCOMPLIANCEL0_delay), + .PIPETXCOMPLIANCEL1 (PIPETXCOMPLIANCEL1_delay), + .PIPETXCOMPLIANCEL2 (PIPETXCOMPLIANCEL2_delay), + .PIPETXCOMPLIANCEL3 (PIPETXCOMPLIANCEL3_delay), + .PIPETXCOMPLIANCEL4 (PIPETXCOMPLIANCEL4_delay), + .PIPETXCOMPLIANCEL5 (PIPETXCOMPLIANCEL5_delay), + .PIPETXCOMPLIANCEL6 (PIPETXCOMPLIANCEL6_delay), + .PIPETXCOMPLIANCEL7 (PIPETXCOMPLIANCEL7_delay), + .PIPETXDATAKL0 (PIPETXDATAKL0_delay), + .PIPETXDATAKL1 (PIPETXDATAKL1_delay), + .PIPETXDATAKL2 (PIPETXDATAKL2_delay), + .PIPETXDATAKL3 (PIPETXDATAKL3_delay), + .PIPETXDATAKL4 (PIPETXDATAKL4_delay), + .PIPETXDATAKL5 (PIPETXDATAKL5_delay), + .PIPETXDATAKL6 (PIPETXDATAKL6_delay), + .PIPETXDATAKL7 (PIPETXDATAKL7_delay), + .PIPETXDATAL0 (PIPETXDATAL0_delay), + .PIPETXDATAL1 (PIPETXDATAL1_delay), + .PIPETXDATAL2 (PIPETXDATAL2_delay), + .PIPETXDATAL3 (PIPETXDATAL3_delay), + .PIPETXDATAL4 (PIPETXDATAL4_delay), + .PIPETXDATAL5 (PIPETXDATAL5_delay), + .PIPETXDATAL6 (PIPETXDATAL6_delay), + .PIPETXDATAL7 (PIPETXDATAL7_delay), + .PIPETXDETECTRXLOOPBACKL0 (PIPETXDETECTRXLOOPBACKL0_delay), + .PIPETXDETECTRXLOOPBACKL1 (PIPETXDETECTRXLOOPBACKL1_delay), + .PIPETXDETECTRXLOOPBACKL2 (PIPETXDETECTRXLOOPBACKL2_delay), + .PIPETXDETECTRXLOOPBACKL3 (PIPETXDETECTRXLOOPBACKL3_delay), + .PIPETXDETECTRXLOOPBACKL4 (PIPETXDETECTRXLOOPBACKL4_delay), + .PIPETXDETECTRXLOOPBACKL5 (PIPETXDETECTRXLOOPBACKL5_delay), + .PIPETXDETECTRXLOOPBACKL6 (PIPETXDETECTRXLOOPBACKL6_delay), + .PIPETXDETECTRXLOOPBACKL7 (PIPETXDETECTRXLOOPBACKL7_delay), + .PIPETXELECIDLEL0 (PIPETXELECIDLEL0_delay), + .PIPETXELECIDLEL1 (PIPETXELECIDLEL1_delay), + .PIPETXELECIDLEL2 (PIPETXELECIDLEL2_delay), + .PIPETXELECIDLEL3 (PIPETXELECIDLEL3_delay), + .PIPETXELECIDLEL4 (PIPETXELECIDLEL4_delay), + .PIPETXELECIDLEL5 (PIPETXELECIDLEL5_delay), + .PIPETXELECIDLEL6 (PIPETXELECIDLEL6_delay), + .PIPETXELECIDLEL7 (PIPETXELECIDLEL7_delay), + .SERRENABLE (SERRENABLE_delay), + .URREPORTINGENABLE (URREPORTINGENABLE_delay), + + .AUXPOWER (AUXPOWER_delay), + .CFGNEGOTIATEDLINKWIDTH (CFGNEGOTIATEDLINKWIDTH_delay), + .COMPLIANCEAVOID (COMPLIANCEAVOID_delay), + .CRMCFGBRIDGEHOTRESET (CRMCFGBRIDGEHOTRESET_delay), + .CRMCORECLK (CRMCORECLK_delay), + .CRMCORECLKDLO (CRMCORECLKDLO_delay), + .CRMCORECLKRXO (CRMCORECLKRXO_delay), + .CRMCORECLKTXO (CRMCORECLKTXO_delay), + .CRMLINKRSTN (CRMLINKRSTN_delay), + .CRMMACRSTN (CRMMACRSTN_delay), + .CRMMGMTRSTN (CRMMGMTRSTN_delay), + .CRMNVRSTN (CRMNVRSTN_delay), + .CRMTXHOTRESETN (CRMTXHOTRESETN_delay), + .CRMURSTN (CRMURSTN_delay), + .CRMUSERCFGRSTN (CRMUSERCFGRSTN_delay), + .CRMUSERCLK (CRMUSERCLK_delay), + .CRMUSERCLKRXO (CRMUSERCLKRXO_delay), + .CRMUSERCLKTXO (CRMUSERCLKTXO_delay), + .CROSSLINKSEED (CROSSLINKSEED_delay), + .L0ACKNAKTIMERADJUSTMENT (L0ACKNAKTIMERADJUSTMENT_delay), + .L0ALLDOWNPORTSINL1 (L0ALLDOWNPORTSINL1_delay), + .L0ALLDOWNRXPORTSINL0S (L0ALLDOWNRXPORTSINL0S_delay), + .L0ASE (L0ASE_delay), + .L0ASPORTCOUNT (L0ASPORTCOUNT_delay), + .L0ASTURNPOOLBITSCONSUMED (L0ASTURNPOOLBITSCONSUMED_delay), + .L0ATTENTIONBUTTONPRESSED (L0ATTENTIONBUTTONPRESSED_delay), + .L0CFGASSPANTREEOWNEDSTATE (L0CFGASSPANTREEOWNEDSTATE_delay), + .L0CFGASSTATECHANGECMD (L0CFGASSTATECHANGECMD_delay), + .L0CFGDISABLESCRAMBLE (L0CFGDISABLESCRAMBLE_delay), + .L0CFGEXTENDEDSYNC (L0CFGEXTENDEDSYNC_delay), + .L0CFGL0SENTRYENABLE (L0CFGL0SENTRYENABLE_delay), + .L0CFGL0SENTRYSUP (L0CFGL0SENTRYSUP_delay), + .L0CFGL0SEXITLAT (L0CFGL0SEXITLAT_delay), + .L0CFGLINKDISABLE (L0CFGLINKDISABLE_delay), + .L0CFGLOOPBACKMASTER (L0CFGLOOPBACKMASTER_delay), + .L0CFGNEGOTIATEDMAXP (L0CFGNEGOTIATEDMAXP_delay), + .L0CFGVCENABLE (L0CFGVCENABLE_delay), + .L0CFGVCID (L0CFGVCID_delay), + .L0DLLHOLDLINKUP (L0DLLHOLDLINKUP_delay), + .L0ELECTROMECHANICALINTERLOCKENGAGED (L0ELECTROMECHANICALINTERLOCKENGAGED_delay), + .L0FWDASSERTINTALEGACYINT (L0FWDASSERTINTALEGACYINT_delay), + .L0FWDASSERTINTBLEGACYINT (L0FWDASSERTINTBLEGACYINT_delay), + .L0FWDASSERTINTCLEGACYINT (L0FWDASSERTINTCLEGACYINT_delay), + .L0FWDASSERTINTDLEGACYINT (L0FWDASSERTINTDLEGACYINT_delay), + .L0FWDCORRERRIN (L0FWDCORRERRIN_delay), + .L0FWDDEASSERTINTALEGACYINT (L0FWDDEASSERTINTALEGACYINT_delay), + .L0FWDDEASSERTINTBLEGACYINT (L0FWDDEASSERTINTBLEGACYINT_delay), + .L0FWDDEASSERTINTCLEGACYINT (L0FWDDEASSERTINTCLEGACYINT_delay), + .L0FWDDEASSERTINTDLEGACYINT (L0FWDDEASSERTINTDLEGACYINT_delay), + .L0FWDFATALERRIN (L0FWDFATALERRIN_delay), + .L0FWDNONFATALERRIN (L0FWDNONFATALERRIN_delay), + .L0LEGACYINTFUNCT0 (L0LEGACYINTFUNCT0_delay), + .L0MRLSENSORCLOSEDN (L0MRLSENSORCLOSEDN_delay), + .L0MSIREQUEST0 (L0MSIREQUEST0_delay), + .L0PACKETHEADERFROMUSER (L0PACKETHEADERFROMUSER_delay), + .L0PMEREQIN (L0PMEREQIN_delay), + .L0PORTNUMBER (L0PORTNUMBER_delay), + .L0POWERFAULTDETECTED (L0POWERFAULTDETECTED_delay), + .L0PRESENCEDETECTSLOTEMPTYN (L0PRESENCEDETECTSLOTEMPTYN_delay), + .L0PWRNEWSTATEREQ (L0PWRNEWSTATEREQ_delay), + .L0PWRNEXTLINKSTATE (L0PWRNEXTLINKSTATE_delay), + .L0REPLAYTIMERADJUSTMENT (L0REPLAYTIMERADJUSTMENT_delay), + .L0ROOTTURNOFFREQ (L0ROOTTURNOFFREQ_delay), + .L0RXTLTLPNONINITIALIZEDVC (L0RXTLTLPNONINITIALIZEDVC_delay), + .L0SENDUNLOCKMESSAGE (L0SENDUNLOCKMESSAGE_delay), + .L0SETCOMPLETERABORTERROR (L0SETCOMPLETERABORTERROR_delay), + .L0SETCOMPLETIONTIMEOUTCORRERROR (L0SETCOMPLETIONTIMEOUTCORRERROR_delay), + .L0SETCOMPLETIONTIMEOUTUNCORRERROR (L0SETCOMPLETIONTIMEOUTUNCORRERROR_delay), + .L0SETDETECTEDCORRERROR (L0SETDETECTEDCORRERROR_delay), + .L0SETDETECTEDFATALERROR (L0SETDETECTEDFATALERROR_delay), + .L0SETDETECTEDNONFATALERROR (L0SETDETECTEDNONFATALERROR_delay), + .L0SETLINKDETECTEDPARITYERROR (L0SETLINKDETECTEDPARITYERROR_delay), + .L0SETLINKMASTERDATAPARITY (L0SETLINKMASTERDATAPARITY_delay), + .L0SETLINKRECEIVEDMASTERABORT (L0SETLINKRECEIVEDMASTERABORT_delay), + .L0SETLINKRECEIVEDTARGETABORT (L0SETLINKRECEIVEDTARGETABORT_delay), + .L0SETLINKSIGNALLEDTARGETABORT (L0SETLINKSIGNALLEDTARGETABORT_delay), + .L0SETLINKSYSTEMERROR (L0SETLINKSYSTEMERROR_delay), + .L0SETUNEXPECTEDCOMPLETIONCORRERROR (L0SETUNEXPECTEDCOMPLETIONCORRERROR_delay), + .L0SETUNEXPECTEDCOMPLETIONUNCORRERROR (L0SETUNEXPECTEDCOMPLETIONUNCORRERROR_delay), + .L0SETUNSUPPORTEDREQUESTNONPOSTEDERROR (L0SETUNSUPPORTEDREQUESTNONPOSTEDERROR_delay), + .L0SETUNSUPPORTEDREQUESTOTHERERROR (L0SETUNSUPPORTEDREQUESTOTHERERROR_delay), + .L0SETUSERDETECTEDPARITYERROR (L0SETUSERDETECTEDPARITYERROR_delay), + .L0SETUSERMASTERDATAPARITY (L0SETUSERMASTERDATAPARITY_delay), + .L0SETUSERRECEIVEDMASTERABORT (L0SETUSERRECEIVEDMASTERABORT_delay), + .L0SETUSERRECEIVEDTARGETABORT (L0SETUSERRECEIVEDTARGETABORT_delay), + .L0SETUSERSIGNALLEDTARGETABORT (L0SETUSERSIGNALLEDTARGETABORT_delay), + .L0SETUSERSYSTEMERROR (L0SETUSERSYSTEMERROR_delay), + .L0TLASFCCREDSTARVATION (L0TLASFCCREDSTARVATION_delay), + .L0TLLINKRETRAIN (L0TLLINKRETRAIN_delay), + .L0TRANSACTIONSPENDING (L0TRANSACTIONSPENDING_delay), + .L0TXBEACON (L0TXBEACON_delay), + .L0TXCFGPM (L0TXCFGPM_delay), + .L0TXCFGPMTYPE (L0TXCFGPMTYPE_delay), + .L0TXTLFCCMPLMCCRED (L0TXTLFCCMPLMCCRED_delay), + .L0TXTLFCCMPLMCUPDATE (L0TXTLFCCMPLMCUPDATE_delay), + .L0TXTLFCNPOSTBYPCRED (L0TXTLFCNPOSTBYPCRED_delay), + .L0TXTLFCNPOSTBYPUPDATE (L0TXTLFCNPOSTBYPUPDATE_delay), + .L0TXTLFCPOSTORDCRED (L0TXTLFCPOSTORDCRED_delay), + .L0TXTLFCPOSTORDUPDATE (L0TXTLFCPOSTORDUPDATE_delay), + .L0TXTLSBFCDATA (L0TXTLSBFCDATA_delay), + .L0TXTLSBFCUPDATE (L0TXTLSBFCUPDATE_delay), + .L0TXTLTLPDATA (L0TXTLTLPDATA_delay), + .L0TXTLTLPEDB (L0TXTLTLPEDB_delay), + .L0TXTLTLPENABLE (L0TXTLTLPENABLE_delay), + .L0TXTLTLPEND (L0TXTLTLPEND_delay), + .L0TXTLTLPLATENCY (L0TXTLTLPLATENCY_delay), + .L0TXTLTLPREQ (L0TXTLTLPREQ_delay), + .L0TXTLTLPREQEND (L0TXTLTLPREQEND_delay), + .L0TXTLTLPWIDTH (L0TXTLTLPWIDTH_delay), + .L0UPSTREAMRXPORTINL0S (L0UPSTREAMRXPORTINL0S_delay), + .L0VC0PREVIEWEXPAND (L0VC0PREVIEWEXPAND_delay), + .L0WAKEN (L0WAKEN_delay), + .LLKRXCHFIFO (LLKRXCHFIFO_delay), + .LLKRXCHTC (LLKRXCHTC_delay), + .LLKRXDSTCONTREQN (LLKRXDSTCONTREQN_delay), + .LLKRXDSTREQN (LLKRXDSTREQN_delay), + .LLKTX4DWHEADERN (LLKTX4DWHEADERN_delay), + .LLKTXCHFIFO (LLKTXCHFIFO_delay), + .LLKTXCHTC (LLKTXCHTC_delay), + .LLKTXCOMPLETEN (LLKTXCOMPLETEN_delay), + .LLKTXCREATEECRCN (LLKTXCREATEECRCN_delay), + .LLKTXDATA (LLKTXDATA_delay), + .LLKTXENABLEN (LLKTXENABLEN_delay), + .LLKTXEOFN (LLKTXEOFN_delay), + .LLKTXEOPN (LLKTXEOPN_delay), + .LLKTXSOFN (LLKTXSOFN_delay), + .LLKTXSOPN (LLKTXSOPN_delay), + .LLKTXSRCDSCN (LLKTXSRCDSCN_delay), + .LLKTXSRCRDYN (LLKTXSRCRDYN_delay), + .MAINPOWER (MAINPOWER_delay), + .MGMTADDR (MGMTADDR_delay), + .MGMTBWREN (MGMTBWREN_delay), + .MGMTRDEN (MGMTRDEN_delay), + .MGMTSTATSCREDITSEL (MGMTSTATSCREDITSEL_delay), + .MGMTWDATA (MGMTWDATA_delay), + .MGMTWREN (MGMTWREN_delay), + .MIMDLLBRDATA (MIMDLLBRDATA_delay), + .MIMRXBRDATA (MIMRXBRDATA_delay), + .MIMTXBRDATA (MIMTXBRDATA_delay), + .PIPEPHYSTATUSL0 (PIPEPHYSTATUSL0_delay), + .PIPEPHYSTATUSL1 (PIPEPHYSTATUSL1_delay), + .PIPEPHYSTATUSL2 (PIPEPHYSTATUSL2_delay), + .PIPEPHYSTATUSL3 (PIPEPHYSTATUSL3_delay), + .PIPEPHYSTATUSL4 (PIPEPHYSTATUSL4_delay), + .PIPEPHYSTATUSL5 (PIPEPHYSTATUSL5_delay), + .PIPEPHYSTATUSL6 (PIPEPHYSTATUSL6_delay), + .PIPEPHYSTATUSL7 (PIPEPHYSTATUSL7_delay), + .PIPERXCHANISALIGNEDL0 (PIPERXCHANISALIGNEDL0_delay), + .PIPERXCHANISALIGNEDL1 (PIPERXCHANISALIGNEDL1_delay), + .PIPERXCHANISALIGNEDL2 (PIPERXCHANISALIGNEDL2_delay), + .PIPERXCHANISALIGNEDL3 (PIPERXCHANISALIGNEDL3_delay), + .PIPERXCHANISALIGNEDL4 (PIPERXCHANISALIGNEDL4_delay), + .PIPERXCHANISALIGNEDL5 (PIPERXCHANISALIGNEDL5_delay), + .PIPERXCHANISALIGNEDL6 (PIPERXCHANISALIGNEDL6_delay), + .PIPERXCHANISALIGNEDL7 (PIPERXCHANISALIGNEDL7_delay), + .PIPERXDATAKL0 (PIPERXDATAKL0_delay), + .PIPERXDATAKL1 (PIPERXDATAKL1_delay), + .PIPERXDATAKL2 (PIPERXDATAKL2_delay), + .PIPERXDATAKL3 (PIPERXDATAKL3_delay), + .PIPERXDATAKL4 (PIPERXDATAKL4_delay), + .PIPERXDATAKL5 (PIPERXDATAKL5_delay), + .PIPERXDATAKL6 (PIPERXDATAKL6_delay), + .PIPERXDATAKL7 (PIPERXDATAKL7_delay), + .PIPERXDATAL0 (PIPERXDATAL0_delay), + .PIPERXDATAL1 (PIPERXDATAL1_delay), + .PIPERXDATAL2 (PIPERXDATAL2_delay), + .PIPERXDATAL3 (PIPERXDATAL3_delay), + .PIPERXDATAL4 (PIPERXDATAL4_delay), + .PIPERXDATAL5 (PIPERXDATAL5_delay), + .PIPERXDATAL6 (PIPERXDATAL6_delay), + .PIPERXDATAL7 (PIPERXDATAL7_delay), + .PIPERXELECIDLEL0 (PIPERXELECIDLEL0_delay), + .PIPERXELECIDLEL1 (PIPERXELECIDLEL1_delay), + .PIPERXELECIDLEL2 (PIPERXELECIDLEL2_delay), + .PIPERXELECIDLEL3 (PIPERXELECIDLEL3_delay), + .PIPERXELECIDLEL4 (PIPERXELECIDLEL4_delay), + .PIPERXELECIDLEL5 (PIPERXELECIDLEL5_delay), + .PIPERXELECIDLEL6 (PIPERXELECIDLEL6_delay), + .PIPERXELECIDLEL7 (PIPERXELECIDLEL7_delay), + .PIPERXSTATUSL0 (PIPERXSTATUSL0_delay), + .PIPERXSTATUSL1 (PIPERXSTATUSL1_delay), + .PIPERXSTATUSL2 (PIPERXSTATUSL2_delay), + .PIPERXSTATUSL3 (PIPERXSTATUSL3_delay), + .PIPERXSTATUSL4 (PIPERXSTATUSL4_delay), + .PIPERXSTATUSL5 (PIPERXSTATUSL5_delay), + .PIPERXSTATUSL6 (PIPERXSTATUSL6_delay), + .PIPERXSTATUSL7 (PIPERXSTATUSL7_delay), + .PIPERXVALIDL0 (PIPERXVALIDL0_delay), + .PIPERXVALIDL1 (PIPERXVALIDL1_delay), + .PIPERXVALIDL2 (PIPERXVALIDL2_delay), + .PIPERXVALIDL3 (PIPERXVALIDL3_delay), + .PIPERXVALIDL4 (PIPERXVALIDL4_delay), + .PIPERXVALIDL5 (PIPERXVALIDL5_delay), + .PIPERXVALIDL6 (PIPERXVALIDL6_delay), + .PIPERXVALIDL7 (PIPERXVALIDL7_delay), + + .GSR(GSR) +); + +specify + (CRMCORECLK => BUSMASTERENABLE) = (100, 100); + (CRMCORECLK => CRMDOHOTRESETN) = (100, 100); + (CRMCORECLK => CRMPWRSOFTRESETN) = (100, 100); + (CRMCORECLK => CRMRXHOTRESETN) = (100, 100); + (CRMCORECLK => DLLTXPMDLLPOUTSTANDING) = (100, 100); + (CRMCORECLK => INTERRUPTDISABLE) = (100, 100); + (CRMCORECLK => IOSPACEENABLE) = (100, 100); + (CRMCORECLK => L0ASAUTONOMOUSINITCOMPLETED) = (100, 100); + (CRMCORECLK => L0ATTENTIONINDICATORCONTROL) = (100, 100); + (CRMCORECLK => L0CFGLOOPBACKACK) = (100, 100); + (CRMCORECLK => L0COMPLETERID) = (100, 100); + (CRMCORECLK => L0CORRERRMSGRCVD) = (100, 100); + (CRMCORECLK => L0DLLASRXSTATE) = (100, 100); + (CRMCORECLK => L0DLLASTXSTATE) = (100, 100); + (CRMCORECLK => L0DLLERRORVECTOR) = (100, 100); + (CRMCORECLK => L0DLLRXACKOUTSTANDING) = (100, 100); + (CRMCORECLK => L0DLLTXNONFCOUTSTANDING) = (100, 100); + (CRMCORECLK => L0DLLTXOUTSTANDING) = (100, 100); + (CRMCORECLK => L0DLLVCSTATUS) = (100, 100); + (CRMCORECLK => L0DLUPDOWN) = (100, 100); + (CRMCORECLK => L0ERRMSGREQID) = (100, 100); + (CRMCORECLK => L0FATALERRMSGRCVD) = (100, 100); + (CRMCORECLK => L0FIRSTCFGWRITEOCCURRED) = (100, 100); + (CRMCORECLK => L0FWDCORRERROUT) = (100, 100); + (CRMCORECLK => L0FWDFATALERROUT) = (100, 100); + (CRMCORECLK => L0FWDNONFATALERROUT) = (100, 100); + (CRMCORECLK => L0LTSSMSTATE) = (100, 100); + (CRMCORECLK => L0MACENTEREDL0) = (100, 100); + (CRMCORECLK => L0MACLINKTRAINING) = (100, 100); + (CRMCORECLK => L0MACLINKUP) = (100, 100); + (CRMCORECLK => L0MACNEGOTIATEDLINKWIDTH) = (100, 100); + (CRMCORECLK => L0MACNEWSTATEACK) = (100, 100); + (CRMCORECLK => L0MACRXL0SSTATE) = (100, 100); + (CRMCORECLK => L0MACUPSTREAMDOWNSTREAM) = (100, 100); + (CRMCORECLK => L0MCFOUND) = (100, 100); + (CRMCORECLK => L0MSIENABLE0) = (100, 100); + (CRMCORECLK => L0MULTIMSGEN0) = (100, 100); + (CRMCORECLK => L0NONFATALERRMSGRCVD) = (100, 100); + (CRMCORECLK => L0PMEACK) = (100, 100); + (CRMCORECLK => L0PMEEN) = (100, 100); + (CRMCORECLK => L0PMEREQOUT) = (100, 100); + (CRMCORECLK => L0POWERCONTROLLERCONTROL) = (100, 100); + (CRMCORECLK => L0POWERINDICATORCONTROL) = (100, 100); + (CRMCORECLK => L0PWRINHIBITTRANSFERS) = (100, 100); + (CRMCORECLK => L0PWRL1STATE) = (100, 100); + (CRMCORECLK => L0PWRL23READYDEVICE) = (100, 100); + (CRMCORECLK => L0PWRL23READYSTATE) = (100, 100); + (CRMCORECLK => L0PWRSTATE0) = (100, 100); + (CRMCORECLK => L0PWRTURNOFFREQ) = (100, 100); + (CRMCORECLK => L0PWRTXL0SSTATE) = (100, 100); + (CRMCORECLK => L0RECEIVEDASSERTINTALEGACYINT) = (100, 100); + (CRMCORECLK => L0RECEIVEDASSERTINTBLEGACYINT) = (100, 100); + (CRMCORECLK => L0RECEIVEDASSERTINTCLEGACYINT) = (100, 100); + (CRMCORECLK => L0RECEIVEDASSERTINTDLEGACYINT) = (100, 100); + (CRMCORECLK => L0RECEIVEDDEASSERTINTALEGACYINT) = (100, 100); + (CRMCORECLK => L0RECEIVEDDEASSERTINTBLEGACYINT) = (100, 100); + (CRMCORECLK => L0RECEIVEDDEASSERTINTCLEGACYINT) = (100, 100); + (CRMCORECLK => L0RECEIVEDDEASSERTINTDLEGACYINT) = (100, 100); + (CRMCORECLK => L0RXBEACON) = (100, 100); + (CRMCORECLK => L0RXDLLFCCMPLMCCRED) = (100, 100); + (CRMCORECLK => L0RXDLLFCCMPLMCUPDATE) = (100, 100); + (CRMCORECLK => L0RXDLLFCNPOSTBYPCRED) = (100, 100); + (CRMCORECLK => L0RXDLLFCNPOSTBYPUPDATE) = (100, 100); + (CRMCORECLK => L0RXDLLFCPOSTORDCRED) = (100, 100); + (CRMCORECLK => L0RXDLLFCPOSTORDUPDATE) = (100, 100); + (CRMCORECLK => L0RXDLLPM) = (100, 100); + (CRMCORECLK => L0RXDLLPMTYPE) = (100, 100); + (CRMCORECLK => L0RXDLLSBFCDATA) = (100, 100); + (CRMCORECLK => L0RXDLLSBFCUPDATE) = (100, 100); + (CRMCORECLK => L0RXDLLTLPECRCOK) = (100, 100); + (CRMCORECLK => L0RXDLLTLPEND) = (100, 100); + (CRMCORECLK => L0RXMACLINKERROR) = (100, 100); + (CRMCORECLK => L0STATSCFGOTHERRECEIVED) = (100, 100); + (CRMCORECLK => L0STATSCFGOTHERTRANSMITTED) = (100, 100); + (CRMCORECLK => L0STATSCFGRECEIVED) = (100, 100); + (CRMCORECLK => L0STATSCFGTRANSMITTED) = (100, 100); + (CRMCORECLK => L0STATSDLLPRECEIVED) = (100, 100); + (CRMCORECLK => L0STATSDLLPTRANSMITTED) = (100, 100); + (CRMCORECLK => L0STATSOSRECEIVED) = (100, 100); + (CRMCORECLK => L0STATSOSTRANSMITTED) = (100, 100); + (CRMCORECLK => L0STATSTLPRECEIVED) = (100, 100); + (CRMCORECLK => L0STATSTLPTRANSMITTED) = (100, 100); + (CRMCORECLK => L0TOGGLEELECTROMECHANICALINTERLOCK) = (100, 100); + (CRMCORECLK => L0TRANSFORMEDVC) = (100, 100); + (CRMCORECLK => L0TXDLLFCCMPLMCUPDATED) = (100, 100); + (CRMCORECLK => L0TXDLLFCNPOSTBYPUPDATED) = (100, 100); + (CRMCORECLK => L0TXDLLFCPOSTORDUPDATED) = (100, 100); + (CRMCORECLK => L0TXDLLPMUPDATED) = (100, 100); + (CRMCORECLK => L0TXDLLSBFCUPDATED) = (100, 100); + (CRMCORECLK => L0UCBYPFOUND) = (100, 100); + (CRMCORECLK => L0UCORDFOUND) = (100, 100); + (CRMCORECLK => L0UNLOCKRECEIVED) = (100, 100); + (CRMCORECLK => LLKRX4DWHEADERN) = (100, 100); + (CRMCORECLK => LLKRXCHCOMPLETIONAVAILABLEN) = (100, 100); + (CRMCORECLK => LLKRXCHCOMPLETIONPARTIALN) = (100, 100); + (CRMCORECLK => LLKRXCHCONFIGAVAILABLEN) = (100, 100); + (CRMCORECLK => LLKRXCHCONFIGPARTIALN) = (100, 100); + (CRMCORECLK => LLKRXCHNONPOSTEDAVAILABLEN) = (100, 100); + (CRMCORECLK => LLKRXCHNONPOSTEDPARTIALN) = (100, 100); + (CRMCORECLK => LLKRXCHPOSTEDAVAILABLEN) = (100, 100); + (CRMCORECLK => LLKRXCHPOSTEDPARTIALN) = (100, 100); + (CRMCORECLK => LLKRXDATA) = (100, 100); + (CRMCORECLK => LLKRXECRCBADN) = (100, 100); + (CRMCORECLK => LLKRXEOFN) = (100, 100); + (CRMCORECLK => LLKRXEOPN) = (100, 100); + (CRMCORECLK => LLKRXPREFERREDTYPE) = (100, 100); + (CRMCORECLK => LLKRXSOFN) = (100, 100); + (CRMCORECLK => LLKRXSOPN) = (100, 100); + (CRMCORECLK => LLKRXSRCDSCN) = (100, 100); + (CRMCORECLK => LLKRXSRCLASTREQN) = (100, 100); + (CRMCORECLK => LLKRXSRCRDYN) = (100, 100); + (CRMCORECLK => LLKRXVALIDN) = (100, 100); + (CRMCORECLK => LLKTCSTATUS) = (100, 100); + (CRMCORECLK => LLKTXCHANSPACE) = (100, 100); + (CRMCORECLK => LLKTXCHCOMPLETIONREADYN) = (100, 100); + (CRMCORECLK => LLKTXCHNONPOSTEDREADYN) = (100, 100); + (CRMCORECLK => LLKTXCHPOSTEDREADYN) = (100, 100); + (CRMCORECLK => LLKTXCONFIGREADYN) = (100, 100); + (CRMCORECLK => LLKTXDSTRDYN) = (100, 100); + (CRMCORECLK => MAXPAYLOADSIZE) = (100, 100); + (CRMCORECLK => MAXREADREQUESTSIZE) = (100, 100); + (CRMCORECLK => MEMSPACEENABLE) = (100, 100); + (CRMCORECLK => MGMTPSO) = (100, 100); + (CRMCORECLK => MGMTRDATA) = (100, 100); + (CRMCORECLK => MGMTSTATSCREDIT) = (100, 100); + (CRMCORECLK => PARITYERRORRESPONSE) = (100, 100); + (CRMCORECLK => PIPEDESKEWLANESL0) = (100, 100); + (CRMCORECLK => PIPEDESKEWLANESL1) = (100, 100); + (CRMCORECLK => PIPEDESKEWLANESL2) = (100, 100); + (CRMCORECLK => PIPEDESKEWLANESL3) = (100, 100); + (CRMCORECLK => PIPEDESKEWLANESL4) = (100, 100); + (CRMCORECLK => PIPEDESKEWLANESL5) = (100, 100); + (CRMCORECLK => PIPEDESKEWLANESL6) = (100, 100); + (CRMCORECLK => PIPEDESKEWLANESL7) = (100, 100); + (CRMCORECLK => PIPEPOWERDOWNL0) = (100, 100); + (CRMCORECLK => PIPEPOWERDOWNL1) = (100, 100); + (CRMCORECLK => PIPEPOWERDOWNL2) = (100, 100); + (CRMCORECLK => PIPEPOWERDOWNL3) = (100, 100); + (CRMCORECLK => PIPEPOWERDOWNL4) = (100, 100); + (CRMCORECLK => PIPEPOWERDOWNL5) = (100, 100); + (CRMCORECLK => PIPEPOWERDOWNL6) = (100, 100); + (CRMCORECLK => PIPEPOWERDOWNL7) = (100, 100); + (CRMCORECLK => PIPERESETL0) = (100, 100); + (CRMCORECLK => PIPERESETL1) = (100, 100); + (CRMCORECLK => PIPERESETL2) = (100, 100); + (CRMCORECLK => PIPERESETL3) = (100, 100); + (CRMCORECLK => PIPERESETL4) = (100, 100); + (CRMCORECLK => PIPERESETL5) = (100, 100); + (CRMCORECLK => PIPERESETL6) = (100, 100); + (CRMCORECLK => PIPERESETL7) = (100, 100); + (CRMCORECLK => PIPERXPOLARITYL0) = (100, 100); + (CRMCORECLK => PIPERXPOLARITYL1) = (100, 100); + (CRMCORECLK => PIPERXPOLARITYL2) = (100, 100); + (CRMCORECLK => PIPERXPOLARITYL3) = (100, 100); + (CRMCORECLK => PIPERXPOLARITYL4) = (100, 100); + (CRMCORECLK => PIPERXPOLARITYL5) = (100, 100); + (CRMCORECLK => PIPERXPOLARITYL6) = (100, 100); + (CRMCORECLK => PIPERXPOLARITYL7) = (100, 100); + (CRMCORECLK => PIPETXCOMPLIANCEL0) = (100, 100); + (CRMCORECLK => PIPETXCOMPLIANCEL1) = (100, 100); + (CRMCORECLK => PIPETXCOMPLIANCEL2) = (100, 100); + (CRMCORECLK => PIPETXCOMPLIANCEL3) = (100, 100); + (CRMCORECLK => PIPETXCOMPLIANCEL4) = (100, 100); + (CRMCORECLK => PIPETXCOMPLIANCEL5) = (100, 100); + (CRMCORECLK => PIPETXCOMPLIANCEL6) = (100, 100); + (CRMCORECLK => PIPETXCOMPLIANCEL7) = (100, 100); + (CRMCORECLK => PIPETXDATAKL0) = (100, 100); + (CRMCORECLK => PIPETXDATAKL1) = (100, 100); + (CRMCORECLK => PIPETXDATAKL2) = (100, 100); + (CRMCORECLK => PIPETXDATAKL3) = (100, 100); + (CRMCORECLK => PIPETXDATAKL4) = (100, 100); + (CRMCORECLK => PIPETXDATAKL5) = (100, 100); + (CRMCORECLK => PIPETXDATAKL6) = (100, 100); + (CRMCORECLK => PIPETXDATAKL7) = (100, 100); + (CRMCORECLK => PIPETXDATAL0) = (100, 100); + (CRMCORECLK => PIPETXDATAL1) = (100, 100); + (CRMCORECLK => PIPETXDATAL2) = (100, 100); + (CRMCORECLK => PIPETXDATAL3) = (100, 100); + (CRMCORECLK => PIPETXDATAL4) = (100, 100); + (CRMCORECLK => PIPETXDATAL5) = (100, 100); + (CRMCORECLK => PIPETXDATAL6) = (100, 100); + (CRMCORECLK => PIPETXDATAL7) = (100, 100); + (CRMCORECLK => PIPETXDETECTRXLOOPBACKL0) = (100, 100); + (CRMCORECLK => PIPETXDETECTRXLOOPBACKL1) = (100, 100); + (CRMCORECLK => PIPETXDETECTRXLOOPBACKL2) = (100, 100); + (CRMCORECLK => PIPETXDETECTRXLOOPBACKL3) = (100, 100); + (CRMCORECLK => PIPETXDETECTRXLOOPBACKL4) = (100, 100); + (CRMCORECLK => PIPETXDETECTRXLOOPBACKL5) = (100, 100); + (CRMCORECLK => PIPETXDETECTRXLOOPBACKL6) = (100, 100); + (CRMCORECLK => PIPETXDETECTRXLOOPBACKL7) = (100, 100); + (CRMCORECLK => PIPETXELECIDLEL0) = (100, 100); + (CRMCORECLK => PIPETXELECIDLEL1) = (100, 100); + (CRMCORECLK => PIPETXELECIDLEL2) = (100, 100); + (CRMCORECLK => PIPETXELECIDLEL3) = (100, 100); + (CRMCORECLK => PIPETXELECIDLEL4) = (100, 100); + (CRMCORECLK => PIPETXELECIDLEL5) = (100, 100); + (CRMCORECLK => PIPETXELECIDLEL6) = (100, 100); + (CRMCORECLK => PIPETXELECIDLEL7) = (100, 100); + (CRMCORECLK => SERRENABLE) = (100, 100); + (CRMCORECLK => URREPORTINGENABLE) = (100, 100); + (CRMCORECLKDLO => MIMDLLBRADD) = (100, 100); + (CRMCORECLKDLO => MIMDLLBREN) = (100, 100); + (CRMCORECLKDLO => MIMDLLBWADD) = (100, 100); + (CRMCORECLKDLO => MIMDLLBWDATA) = (100, 100); + (CRMCORECLKDLO => MIMDLLBWEN) = (100, 100); + (CRMCORECLKRXO => MIMRXBRADD) = (100, 100); + (CRMCORECLKRXO => MIMRXBREN) = (100, 100); + (CRMCORECLKRXO => MIMRXBWADD) = (100, 100); + (CRMCORECLKRXO => MIMRXBWDATA) = (100, 100); + (CRMCORECLKRXO => MIMRXBWEN) = (100, 100); + (CRMCORECLKTXO => MIMTXBRADD) = (100, 100); + (CRMCORECLKTXO => MIMTXBREN) = (100, 100); + (CRMCORECLKTXO => MIMTXBWADD) = (100, 100); + (CRMCORECLKTXO => MIMTXBWDATA) = (100, 100); + (CRMCORECLKTXO => MIMTXBWEN) = (100, 100); + (CRMUSERCLK => BUSMASTERENABLE) = (100, 100); + (CRMUSERCLK => INTERRUPTDISABLE) = (100, 100); + (CRMUSERCLK => IOSPACEENABLE) = (100, 100); + (CRMUSERCLK => L0ATTENTIONINDICATORCONTROL) = (100, 100); + (CRMUSERCLK => L0COMPLETERID) = (100, 100); + (CRMUSERCLK => L0CORRERRMSGRCVD) = (100, 100); + (CRMUSERCLK => L0ERRMSGREQID) = (100, 100); + (CRMUSERCLK => L0FATALERRMSGRCVD) = (100, 100); + (CRMUSERCLK => L0FIRSTCFGWRITEOCCURRED) = (100, 100); + (CRMUSERCLK => L0FWDCORRERROUT) = (100, 100); + (CRMUSERCLK => L0FWDFATALERROUT) = (100, 100); + (CRMUSERCLK => L0FWDNONFATALERROUT) = (100, 100); + (CRMUSERCLK => L0MSIENABLE0) = (100, 100); + (CRMUSERCLK => L0MULTIMSGEN0) = (100, 100); + (CRMUSERCLK => L0NONFATALERRMSGRCVD) = (100, 100); + (CRMUSERCLK => L0PMEACK) = (100, 100); + (CRMUSERCLK => L0PMEEN) = (100, 100); + (CRMUSERCLK => L0PMEREQOUT) = (100, 100); + (CRMUSERCLK => L0POWERCONTROLLERCONTROL) = (100, 100); + (CRMUSERCLK => L0POWERINDICATORCONTROL) = (100, 100); + (CRMUSERCLK => L0PWRL1STATE) = (100, 100); + (CRMUSERCLK => L0PWRL23READYDEVICE) = (100, 100); + (CRMUSERCLK => L0PWRL23READYSTATE) = (100, 100); + (CRMUSERCLK => L0PWRSTATE0) = (100, 100); + (CRMUSERCLK => L0PWRTURNOFFREQ) = (100, 100); + (CRMUSERCLK => L0PWRTXL0SSTATE) = (100, 100); + (CRMUSERCLK => L0RECEIVEDASSERTINTALEGACYINT) = (100, 100); + (CRMUSERCLK => L0RECEIVEDASSERTINTBLEGACYINT) = (100, 100); + (CRMUSERCLK => L0RECEIVEDASSERTINTCLEGACYINT) = (100, 100); + (CRMUSERCLK => L0RECEIVEDASSERTINTDLEGACYINT) = (100, 100); + (CRMUSERCLK => L0RECEIVEDDEASSERTINTALEGACYINT) = (100, 100); + (CRMUSERCLK => L0RECEIVEDDEASSERTINTBLEGACYINT) = (100, 100); + (CRMUSERCLK => L0RECEIVEDDEASSERTINTCLEGACYINT) = (100, 100); + (CRMUSERCLK => L0RECEIVEDDEASSERTINTDLEGACYINT) = (100, 100); + (CRMUSERCLK => L0STATSCFGOTHERRECEIVED) = (100, 100); + (CRMUSERCLK => L0STATSCFGOTHERTRANSMITTED) = (100, 100); + (CRMUSERCLK => L0STATSCFGRECEIVED) = (100, 100); + (CRMUSERCLK => L0STATSCFGTRANSMITTED) = (100, 100); + (CRMUSERCLK => L0TOGGLEELECTROMECHANICALINTERLOCK) = (100, 100); + (CRMUSERCLK => L0UNLOCKRECEIVED) = (100, 100); + (CRMUSERCLK => LLKRX4DWHEADERN) = (100, 100); + (CRMUSERCLK => LLKRXCHCOMPLETIONAVAILABLEN) = (100, 100); + (CRMUSERCLK => LLKRXCHCOMPLETIONPARTIALN) = (100, 100); + (CRMUSERCLK => LLKRXCHCONFIGAVAILABLEN) = (100, 100); + (CRMUSERCLK => LLKRXCHCONFIGPARTIALN) = (100, 100); + (CRMUSERCLK => LLKRXCHNONPOSTEDAVAILABLEN) = (100, 100); + (CRMUSERCLK => LLKRXCHNONPOSTEDPARTIALN) = (100, 100); + (CRMUSERCLK => LLKRXCHPOSTEDAVAILABLEN) = (100, 100); + (CRMUSERCLK => LLKRXCHPOSTEDPARTIALN) = (100, 100); + (CRMUSERCLK => LLKRXDATA) = (100, 100); + (CRMUSERCLK => LLKRXECRCBADN) = (100, 100); + (CRMUSERCLK => LLKRXEOFN) = (100, 100); + (CRMUSERCLK => LLKRXEOPN) = (100, 100); + (CRMUSERCLK => LLKRXPREFERREDTYPE) = (100, 100); + (CRMUSERCLK => LLKRXSOFN) = (100, 100); + (CRMUSERCLK => LLKRXSOPN) = (100, 100); + (CRMUSERCLK => LLKRXSRCDSCN) = (100, 100); + (CRMUSERCLK => LLKRXSRCLASTREQN) = (100, 100); + (CRMUSERCLK => LLKRXSRCRDYN) = (100, 100); + (CRMUSERCLK => LLKRXVALIDN) = (100, 100); + (CRMUSERCLK => LLKTCSTATUS) = (100, 100); + (CRMUSERCLK => LLKTXCHANSPACE) = (100, 100); + (CRMUSERCLK => LLKTXCHCOMPLETIONREADYN) = (100, 100); + (CRMUSERCLK => LLKTXCHNONPOSTEDREADYN) = (100, 100); + (CRMUSERCLK => LLKTXCHPOSTEDREADYN) = (100, 100); + (CRMUSERCLK => LLKTXCONFIGREADYN) = (100, 100); + (CRMUSERCLK => LLKTXDSTRDYN) = (100, 100); + (CRMUSERCLK => MAXPAYLOADSIZE) = (100, 100); + (CRMUSERCLK => MAXREADREQUESTSIZE) = (100, 100); + (CRMUSERCLK => MEMSPACEENABLE) = (100, 100); + (CRMUSERCLK => MGMTPSO) = (100, 100); + (CRMUSERCLK => MGMTRDATA) = (100, 100); + (CRMUSERCLK => MGMTSTATSCREDIT) = (100, 100); + (CRMUSERCLK => PARITYERRORRESPONSE) = (100, 100); + (CRMUSERCLK => SERRENABLE) = (100, 100); + (CRMUSERCLK => URREPORTINGENABLE) = (100, 100); + (CRMUSERCLKRXO => MIMRXBRADD) = (100, 100); + (CRMUSERCLKRXO => MIMRXBREN) = (100, 100); + (CRMUSERCLKTXO => MIMTXBWADD) = (100, 100); + (CRMUSERCLKTXO => MIMTXBWDATA) = (100, 100); + (CRMUSERCLKTXO => MIMTXBWEN) = (100, 100); + (L0WAKEN => L0RXBEACON) = (100, 100); + (MAINPOWER => L0PMEEN) = (100, 100); + (MAINPOWER => L0PMEREQOUT) = (100, 100); + (MAINPOWER => L0RXBEACON) = (100, 100); + (MAINPOWER => PIPEPOWERDOWNL0) = (100, 100); + (MAINPOWER => PIPEPOWERDOWNL1) = (100, 100); + (MAINPOWER => PIPEPOWERDOWNL2) = (100, 100); + (MAINPOWER => PIPEPOWERDOWNL3) = (100, 100); + (MAINPOWER => PIPEPOWERDOWNL4) = (100, 100); + (MAINPOWER => PIPEPOWERDOWNL5) = (100, 100); + (MAINPOWER => PIPEPOWERDOWNL6) = (100, 100); + (MAINPOWER => PIPEPOWERDOWNL7) = (100, 100); + specparam PATHPULSE$ = 0; +endspecify +endmodule diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/PLL_ADV.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/PLL_ADV.v new file mode 100644 index 0000000..f7c3bb7 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/PLL_ADV.v @@ -0,0 +1,2621 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/rainier/PLL_ADV.v,v 1.70.8.1 2010/05/20 20:38:47 yanx Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2010 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Function Simulation Library Component +// / / Phase Lock Loop Clock +// /___/ /\ Filename : PLL_ADV.v +// \ \ / \ Timestamp : Thu Mar 25 16:44:07 PST 2004 +// \___\/\___\ +// +// Revision: +// 10/02/08 - Initial version. +// 10/24/08 - Using internal clock to detect clkin and clkfb stopped (CR493444) +// 11/18/08 - Add timing check. +// 12/02/08 - Fix bug of Duty cycle calculation (CR498696) +// 12/04/08 - make clkfb_tst at least 1 ns wide (CR499318) +// 12/05/08 - change pll_res according to hardware spreadsheet (CR496137) +// 01/09/09 - Make pll_res same for BANDWIDTH=HIGH and OPTIMIZED (CR496137) +// 02/11/09 - Change VCO_FREQ_MAX and MIN to 1441 and 399 to cover the rounded +// error (CR507969) +// 05/13/09 - Use period_avg for clkvco_delay calculation (CR521120) +// 06/11/09 - When calculate clk0_div1, set clk0_nocnt to 1 if CLKOUT0 as feedback (CR524704) +// 09/02/09 - Add SIM_DEVICE attribute (CR532327) +// 09/09/09 - Add DRP support for Spartan6 (CR532327) +// 10/08/09 - Change CLKIN_FREQ MAX & MIN, CLKPFD_FREQ +// MAX & MIN to parameter (CR535828) +// 10/14/09 - Add clkin_chk_t1 and clkin_chk_t2 to handle check (CR535662) +// 12/02/09 - not stop clkvco_lk when jitter (CR538717) +// 02/09/10 - Divide clk0 when CLKOUT0 as feedback (CR548329) +// - Add global PLL_LOCKG (CR547918) +// 05/07/10 - Use period_vco_half_rm1 to reduce jitter (CR558966) +// - Support CLK_FEEDBACK=CLKOUT0 and CLKOUT0_PHASE set(CR559360) +// End Revision + + +`timescale 1 ps / 1 ps + + +module PLL_ADV ( + CLKFBDCM, + CLKFBOUT, + CLKOUT0, + CLKOUT1, + CLKOUT2, + CLKOUT3, + CLKOUT4, + CLKOUT5, + CLKOUTDCM0, + CLKOUTDCM1, + CLKOUTDCM2, + CLKOUTDCM3, + CLKOUTDCM4, + CLKOUTDCM5, + DO, + DRDY, + LOCKED, + CLKFBIN, + CLKIN1, + CLKIN2, + CLKINSEL, + DADDR, + DCLK, + DEN, + DI, + DWE, + REL, + RST +); + +parameter BANDWIDTH = "OPTIMIZED"; +parameter CLK_FEEDBACK = "CLKFBOUT"; +parameter CLKFBOUT_DESKEW_ADJUST = "NONE"; +parameter CLKOUT0_DESKEW_ADJUST = "NONE"; +parameter CLKOUT1_DESKEW_ADJUST = "NONE"; +parameter CLKOUT2_DESKEW_ADJUST = "NONE"; +parameter CLKOUT3_DESKEW_ADJUST = "NONE"; +parameter CLKOUT4_DESKEW_ADJUST = "NONE"; +parameter CLKOUT5_DESKEW_ADJUST = "NONE"; +parameter integer CLKFBOUT_MULT = 1; +parameter real CLKFBOUT_PHASE = 0.0; +parameter real CLKIN1_PERIOD = 0.000; +parameter real CLKIN2_PERIOD = 0.000; +parameter integer CLKOUT0_DIVIDE = 1; +parameter real CLKOUT0_DUTY_CYCLE = 0.5; +parameter real CLKOUT0_PHASE = 0.0; +parameter integer CLKOUT1_DIVIDE = 1; +parameter real CLKOUT1_DUTY_CYCLE = 0.5; +parameter real CLKOUT1_PHASE = 0.0; +parameter integer CLKOUT2_DIVIDE = 1; +parameter real CLKOUT2_DUTY_CYCLE = 0.5; +parameter real CLKOUT2_PHASE = 0.0; +parameter integer CLKOUT3_DIVIDE = 1; +parameter real CLKOUT3_DUTY_CYCLE = 0.5; +parameter real CLKOUT3_PHASE = 0.0; +parameter integer CLKOUT4_DIVIDE = 1; +parameter real CLKOUT4_DUTY_CYCLE = 0.5; +parameter real CLKOUT4_PHASE = 0.0; +parameter integer CLKOUT5_DIVIDE = 1; +parameter real CLKOUT5_DUTY_CYCLE = 0.5; +parameter real CLKOUT5_PHASE = 0.0; +parameter COMPENSATION = "SYSTEM_SYNCHRONOUS"; +parameter integer DIVCLK_DIVIDE = 1; +parameter EN_REL = "FALSE"; +parameter PLL_PMCD_MODE = "FALSE"; +parameter real REF_JITTER = 0.100; +parameter RESET_ON_LOSS_OF_LOCK = "FALSE"; +parameter RST_DEASSERT_CLK = "CLKIN1"; +parameter SIM_DEVICE = "VIRTEX5"; +parameter real VCOCLK_FREQ_MAX = 1440.0; +parameter real VCOCLK_FREQ_MIN = 400.0; +parameter real CLKIN_FREQ_MAX = 710.0; +parameter real CLKIN_FREQ_MIN = 19.0; +parameter real CLKPFD_FREQ_MAX = 550.0; +parameter real CLKPFD_FREQ_MIN = 19.0; + +// `ifdef XIL_TIMING + + + +// `endif + +output CLKFBDCM; +output CLKFBOUT; +output CLKOUT0; +output CLKOUT1; +output CLKOUT2; +output CLKOUT3; +output CLKOUT4; +output CLKOUT5; +output CLKOUTDCM0; +output CLKOUTDCM1; +output CLKOUTDCM2; +output CLKOUTDCM3; +output CLKOUTDCM4; +output CLKOUTDCM5; +output DRDY; +output LOCKED; +output [15:0] DO; + +input CLKFBIN; +input CLKIN1; +input CLKIN2; +input CLKINSEL; +input DCLK; +input DEN; +input DWE; +input REL; +input RST; +input [15:0] DI; +input [4:0] DADDR; + +localparam VCOCLK_FREQ_TARGET = 800; +localparam M_MIN = 1; +localparam M_MAX = 74; +localparam D_MIN = 1; +localparam D_MAX = 52; +localparam O_MIN = 1; +localparam O_MAX = 128; +localparam O_MAX_HT_LT = 64; +localparam REF_CLK_JITTER_MAX = 1000; +localparam REF_CLK_JITTER_SCALE = 0.1; +localparam MAX_FEEDBACK_DELAY = 10.0; +localparam MAX_FEEDBACK_DELAY_SCALE = 1.0; +localparam PLL_LOCK_TIME = 7; +localparam OSC_P2 = 250; + +tri0 GSR = glbl.GSR; +tri1 p_up; + +wire delay_CLKIN1; +wire delay_CLKIN2; +wire delay_CLKINSEL; +wire delay_DCLK; +wire delay_DEN; +wire delay_DWE; +wire delay_REL; +wire [15:0] delay_DI; +wire [4:0] delay_DADDR; + +reg [4:0] daddr_lat; +reg valid_daddr; +reg drdy_out = 0; +reg drdy_out1 = 0; +reg drp_lock, drp_lock1; +reg [15:0] dr_sram [31:0]; +reg [160:0] tmp_string; + +wire CLKFBIN, CLKIN1, CLKIN2, CLKINSEL ; +wire rst_in, RST, orig_rst_in ; +wire locked_out; +reg locked_out1 = 0; +wire clkvco_lk_rst; +reg pwron_int; + +reg clk_osc, clkin_p, clkfb_p; +reg clk0_out, clk1_out, clk2_out, clk3_out, clk4_out, clk5_out; +reg clkfb_out, clkfbm1_out; +reg clkout_en, clkout_en1, clkout_en0, clkout_en0_tmp; +integer clkout_cnt, clkin_cnt, clkin_lock_cnt; +integer clkout_en_time, locked_en_time, lock_cnt_max; +reg clkvco_lk, clkvco_free, clkvco; +integer clkfb_mult_tl; +real clkout0_ps_tmp; +reg fbclk_tmp, clkfb_src; + +reg rst_in1, rst_unlock, rst_on_loss; +time rst_edge, rst_ht; + +reg fb_delay_found, fb_delay_found_tmp; +reg clkfb_tst; +real fb_delay_max; +time fb_delay, clkvco_delay, val_tmp, dly_tmp, fbm1_comp_delay; +time clkin_edge, delay_edge; + +real period_clkin, clkin_period_tmp; +integer clkin_period [4:0]; +integer period_vco, period_vco_half, period_vco_half1, period_vco_half_rm; +integer period_vco_half_rm1, period_vco_half_rm2; +integer period_vco_rm, period_vco_cmp_cnt, clkvco_rm_cnt; +integer period_vco_cmp_flag; +integer period_vco_max, period_vco_min; +integer period_vco1, period_vco2, period_vco3, period_vco4; +integer period_vco5, period_vco6, period_vco7; +integer period_vco_target, period_vco_target_half; +integer period_fb, period_avg; + +real clkvco_freq_init_chk, clkfbm1pm_rl; +real tmp_real; +integer i, j, i1, i2; +integer md_product, m_product, m_product2, period_vco_rm2; +integer clkin_lost_val, clkfb_lost_val; + +time pll_locked_delay, clkin_dly_t, clkfb_dly_t; +reg clkpll_dly, clkfbin_dly; +wire pll_unlock; +reg pll_locked_tmp1, pll_locked_tmp2; +reg lock_period; +reg pll_locked_tm, unlock_recover; +reg clkin_stopped, clkfb_stopped; +reg clkpll_jitter_unlock; +integer clkin_lost_cnt, clkfb_lost_cnt; +integer clkin_jit, REF_CLK_JITTER_MAX_tmp; + +wire REL, DWE, DEN, DCLK, rel_o_mux_clk_tmp, clka1_in, clkb1_in; +wire init_trig, clkpll_tmp, clkpll, clk0in, clk1in, clk2in, clk3in, clk4in, clk5in; +wire clkfbm1in, clkfbm1ps_en; + + +reg clkout0_out; +reg clkout1_out; +reg clkout2_out; +reg clkout3_out; +reg clkout4_out; +reg clkout5_out; + +reg clka1_out, clkb1_out, clka1d2_out, clka1d4_out, clka1d8_out; +reg clkdiv_rel_rst, qrel_o_reg1, qrel_o_reg2, qrel_o_reg3, rel_o_mux_sel; +reg pmcd_mode; +reg chk_ok; +reg sim_d; + +wire rel_rst_o, rel_o_mux_clk; +wire clk0ps_en, clk1ps_en, clk2ps_en, clk3ps_en, clk4ps_en, clk5ps_en; + +reg [7:0] clkout_mux; +reg [2:0] clk0pm_sel, clk1pm_sel, clk2pm_sel, clk3pm_sel, clk4pm_sel, clk5pm_sel; +reg [2:0] clkfbm1pm_sel, clkfbm2pm_sel, clkfbmpm_sel; +reg clk0_edge, clk1_edge, clk2_edge, clk3_edge, clk4_edge, clk5_edge; +reg clkfbm1_edge, clkfbm2_edge, clkind_edge; +reg clk0_nocnt, clk1_nocnt, clk2_nocnt, clk3_nocnt, clk4_nocnt, clk5_nocnt; +reg clkfbm1_nocnt, clkfbm2_nocnt, clkind_nocnt; +reg clkind_edgei, clkind_nocnti; +reg [5:0] clk0_dly_cnt, clkout0_dly; +reg [5:0] clk1_dly_cnt, clkout1_dly; +reg [5:0] clk2_dly_cnt, clkout2_dly; +reg [5:0] clk3_dly_cnt, clkout3_dly; +reg [5:0] clk4_dly_cnt, clkout4_dly; +reg [5:0] clk5_dly_cnt, clkout5_dly; +reg [6:0] clk0_ht, clk0_lt; +reg [6:0] clk1_ht, clk1_lt; +reg [6:0] clk2_ht, clk2_lt; +reg [6:0] clk3_ht, clk3_lt; +reg [6:0] clk4_ht, clk4_lt; +reg [6:0] clk5_ht, clk5_lt; +reg [5:0] clkfbm1_dly_cnt, clkfbm1_dly; +reg [5:0] clkfbm2_dly_cnt, clkfbm2_dly; +reg [5:0] clkfbm_dly; +reg [6:0] clkfbm1_ht, clkfbm1_lt; +reg [6:0] clkfbm2_ht, clkfbm2_lt; +reg [7:0] clkind_ht = 8'b00000001; +reg [7:0] clkind_lt = 8'b00000001; +reg [7:0] clkind_hti, clkind_lti; +reg [7:0] clk0_ht1, clk0_cnt, clk0_div, clk0_div1; +reg [7:0] clk1_ht1, clk1_cnt, clk1_div, clk1_div1; +reg [7:0] clk2_ht1, clk2_cnt, clk2_div, clk2_div1; +reg [7:0] clk3_ht1, clk3_cnt, clk3_div, clk3_div1; +reg [7:0] clk4_ht1, clk4_cnt, clk4_div, clk4_div1; +reg [7:0] clk5_ht1, clk5_cnt, clk5_div, clk5_div1; +reg [7:0] clkfbm1_ht1, clkfbm1_cnt, clkfbm1_div, clkfbm1_div1; +reg [7:0] clkfbm2_ht1, clkfbm2_cnt, clkfbm2_div, clkfbm2_div1; +reg [7:0] clkfbm_div; +reg [7:0] clkind_div, clkind_divi; +reg [3:0] pll_cp, pll_res; +reg [1:0] pll_lfhf; +reg [1:0] pll_cpres = 2'b01; +wire clkinsel_tmp; +real clkin_chk_t1, clkin_chk_t2; + +reg notifier; +wire [15:0] do_out, di_in; +wire clkin1_in, clkin2_in, clkfb_in, clkinsel_in, dwe_in, den_in, dclk_in; +wire [4:0] daddr_in; +wire rel_in, gsr_in, rst_input; + +// `ifndef XIL_TIMING + + assign LOCKED = locked_out1; + assign DRDY = drdy_out1; + assign DO = do_out; + assign clkin1_in = CLKIN1; + assign clkin2_in = CLKIN2; + assign clkfb_in = CLKFBIN; + assign clkinsel_in = CLKINSEL; + assign rst_input = RST; + assign daddr_in = DADDR; + assign di_in = DI; + assign dwe_in = DWE; + assign den_in = DEN; + assign dclk_in = DCLK; + assign rel_in = REL; + + always @(locked_out) + locked_out1 <= #100 locked_out; + + always @(drdy_out) + drdy_out1 <= #100 drdy_out; + + +// `endif `ifdef XIL_TIMING + +initial begin + #1; + if ($realtime == 0) begin + $display ("Simulator Resolution Error : Simulator resolution is set to a value greater than 1 ps."); + $display ("In order to simulate the PLL_ADV, the simulator resolution must be set to 1ps or smaller."); + $finish; + end +end + +initial begin + + case (SIM_DEVICE) + "VIRTEX5" : sim_d = 0; + "SPARTAN6" : sim_d = 1 ; + default : begin + sim_d = 0; + $display("Attribute Syntax Error : The Attribute SIM_DEVICE on PLL_ADV instance %m is set to %s. Legal values for this attribute are VIRTEX5 or SPARTAN6.", SIM_DEVICE); + $finish; + end + endcase + + case (COMPENSATION) + "SYSTEM_SYNCHRONOUS" : ; + "SOURCE_SYNCHRONOUS" : ; + "INTERNAL" : ; + "EXTERNAL" : ; + "DCM2PLL" : ; + "PLL2DCM" : ; + default : begin + $display("Attribute Syntax Error : The Attribute COMPENSATION on PLL_ADV instance %m is set to %s. Legal values for this attribute are SYSTEM_SYNCHRONOUS, SOURCE_SYNCHRONOUS, INTERNAL, EXTERNAL, DCM2PLL or PLL2DCM.", COMPENSATION); + $finish; + end + endcase + + case (BANDWIDTH) + "HIGH" : ; + "LOW" : ; + "OPTIMIZED" : ; + default : begin + $display("Attribute Syntax Error : The Attribute BANDWIDTH on PLL_ADV instance %m is set to %s. Legal values for this attribute are HIGH, LOW or OPTIMIZED.", BANDWIDTH); + $finish; + end + endcase + + case (CLK_FEEDBACK) + "CLKFBOUT" : begin + clkfb_src = 0; + clkfb_mult_tl = CLKFBOUT_MULT; + end + "CLKOUT0" : begin + clkfb_src = 1; + clkfb_mult_tl = CLKFBOUT_MULT * CLKOUT0_DIVIDE; + end + default : begin + $display("Attribute Syntax Error : The Attribute CLK_FEEDBACK on PLL_ADV instance %m is set to %s. The valid values are CLKFBOUT or CLKOUT0.", CLK_FEEDBACK); + $finish; + end + endcase + + + case (CLKOUT0_DESKEW_ADJUST) + "NONE" : ; + "PPC" : ; + default : begin + $display("Attribute Syntax Error : The Attribute CLKOUT0_DESKEW_ADJUST on PLL_ADV instance %m is set to %s. Legal values for this attribute are NONE or PPC.", CLKOUT0_DESKEW_ADJUST); + $finish; + end + endcase + + case (CLKOUT1_DESKEW_ADJUST) + "NONE" : ; + "PPC" : ; + default : begin + $display("Attribute Syntax Error : The Attribute CLKOUT1_DESKEW_ADJUST on PLL_ADV instance %m is set to %s. Legal values for this attribute are NONE or PPC .", CLKOUT1_DESKEW_ADJUST); + $finish; + end + endcase + + case (CLKOUT2_DESKEW_ADJUST) + "NONE" : ; + "PPC" : ; + default : begin + $display("Attribute Syntax Error : The Attribute CLKOUT2_DESKEW_ADJUST on PLL_ADV instance %m is set to %s. Legal values for this attribute are NONE or PPC.", CLKOUT2_DESKEW_ADJUST); + $finish; + end + endcase + + case (CLKOUT3_DESKEW_ADJUST) + "NONE" : ; + "PPC" : ; + default : begin + $display("Attribute Syntax Error : The Attribute CLKOUT3_DESKEW_ADJUST on PLL_ADV instance %m is set to %s. Legal values for this attribute are NONE or PPC.", CLKOUT3_DESKEW_ADJUST); + $finish; + end + endcase + + case (CLKOUT4_DESKEW_ADJUST) + "NONE" : ; + "PPC" : ; + default : begin + $display("Attribute Syntax Error : The Attribute CLKOUT4_DESKEW_ADJUST on PLL_ADV instance %m is set to %s. Legal values for this attribute are NONE or PPC.", CLKOUT4_DESKEW_ADJUST); + $finish; + end + endcase + + case (CLKOUT5_DESKEW_ADJUST) + "NONE" : ; + "PPC" : ; + default : begin + $display("Attribute Syntax Error : The Attribute CLKOUT5_DESKEW_ADJUST on PLL_ADV instance %m is set to %s. Legal values for this attribute are NONE or PPC.", CLKOUT5_DESKEW_ADJUST); + $finish; + end + endcase + + case (CLKFBOUT_DESKEW_ADJUST) + "NONE" : ; + "PPC" : ; + default : begin + $display("Attribute Syntax Error : The Attribute CLKFBOUT_DESKEW_ADJUST on PLL_ADV instance %m is set to %s. Legal values for this attribute are NONE or PPC.", CLKFBOUT_DESKEW_ADJUST); + $finish; + end + endcase + + + case (PLL_PMCD_MODE) + "TRUE" : pmcd_mode = 1'b1; + "FALSE" : pmcd_mode = 1'b0; + default : begin + $display("Attribute Syntax Error : The Attribute PLL_PMCD_MODE on PLL_ADV instance %m is set to %s. Legal values for this attribute are FALSE or TRUE.", PLL_PMCD_MODE); + $finish; + end + endcase + + tmp_string = "CLKOUT0_DIVIDE"; + chk_ok = para_int_pmcd_chk(CLKOUT0_DIVIDE, tmp_string, 1, 128, pmcd_mode, 8); + tmp_string = "CLKOUT0_PHASE"; + chk_ok = para_real_pmcd_chk(CLKOUT0_PHASE, tmp_string, -360.0, 360.0, pmcd_mode, 0.0); + tmp_string = "CLKOUT0_DUTY_CYCLE"; + chk_ok = para_real_pmcd_chk(CLKOUT0_DUTY_CYCLE, tmp_string, 0.0, 1.0, pmcd_mode, 0.5); + + tmp_string = "CLKOUT1_DIVIDE"; + chk_ok = para_int_pmcd_chk(CLKOUT1_DIVIDE, tmp_string, 1, 128, pmcd_mode, 4); + tmp_string = "CLKOUT1_PHASE"; + chk_ok = para_real_pmcd_chk(CLKOUT1_PHASE, tmp_string, -360.0, 360.0, pmcd_mode, 0.0); + tmp_string = "CLKOUT1_DUTY_CYCLE"; + chk_ok = para_real_pmcd_chk(CLKOUT1_DUTY_CYCLE, tmp_string, 0.0, 1.0, pmcd_mode, 0.5); + + tmp_string = "CLKOUT2_DIVIDE"; + chk_ok = para_int_pmcd_chk(CLKOUT2_DIVIDE, tmp_string, 1, 128, pmcd_mode, 2); + tmp_string = "CLKOUT2_PHASE"; + chk_ok = para_real_pmcd_chk(CLKOUT2_PHASE, tmp_string, -360.0, 360.0, pmcd_mode, 0.0); + tmp_string = "CLKOUT2_DUTY_CYCLE"; + chk_ok = para_real_pmcd_chk(CLKOUT2_DUTY_CYCLE, tmp_string, 0.0, 1.0, pmcd_mode, 0.5); + + tmp_string = "CLKOUT3_DIVIDE"; + chk_ok = para_int_pmcd_chk(CLKOUT3_DIVIDE, tmp_string, 1, 128, pmcd_mode, 1); + tmp_string = "CLKOUT3_PHASE"; + chk_ok = para_real_pmcd_chk(CLKOUT3_PHASE, tmp_string, -360.0, 360.0, pmcd_mode, 0.0); + tmp_string = "CLKOUT3_DUTY_CYCLE"; + chk_ok = para_real_pmcd_chk(CLKOUT3_DUTY_CYCLE, tmp_string, 0.0, 1.0, pmcd_mode, 0.5); + + tmp_string = "CLKOUT4_DIVIDE"; + chk_ok = para_int_range_chk(CLKOUT4_DIVIDE, tmp_string, 1, 128); + tmp_string = "CLKOUT4_PHASE"; + chk_ok = para_real_range_chk(CLKOUT4_PHASE, tmp_string, -360.0, 360.0); + tmp_string = "CLKOUT4_DUTY_CYCLE"; + chk_ok = para_real_range_chk(CLKOUT4_DUTY_CYCLE, tmp_string, 0.0, 1.0); + + tmp_string = "CLKOUT5_DIVIDE"; + chk_ok = para_int_range_chk (CLKOUT5_DIVIDE, tmp_string, 1, 128); + tmp_string = "CLKOUT5_PHASE"; + chk_ok = para_real_range_chk(CLKOUT5_PHASE, tmp_string, -360.0, 360.0); + tmp_string = "CLKOUT5_DUTY_CYCLE"; + chk_ok = para_real_range_chk (CLKOUT5_DUTY_CYCLE, tmp_string, 0.0, 1.0); + + tmp_string = "CLKFBOUT_MULT"; + chk_ok = para_int_pmcd_chk(CLKFBOUT_MULT, tmp_string, 1, 74, pmcd_mode, 1); + if (clkfb_src == 1) begin + if (CLKFBOUT_PHASE > 0.001 || CLKFBOUT_PHASE < - 0.001) + $display("Attribute Syntax Error : The Attribute CLKFBOUT_PHASE on PLL_ADV instance %m is set to %f. This attribute should be set to 0.0 when attribute CLKFB_FEEDBACK set to CLKOUT0.", CLKFBOUT_PHASE); + end + else begin + tmp_string = "CLKFBOUT_PHASE"; + chk_ok = para_real_pmcd_chk(CLKFBOUT_PHASE, tmp_string, -360.0, 360.0, pmcd_mode, 0.0); + end + tmp_string = "DIVCLK_DIVIDE"; + chk_ok = para_int_range_chk (DIVCLK_DIVIDE, tmp_string, 1, 52); + + tmp_string = "REF_JITTER"; + chk_ok = para_real_range_chk (REF_JITTER, tmp_string, 0.0, 0.999); + clkin_period_tmp = CLKIN1_PERIOD; + if (((clkin_period_tmp < 1.0) || (clkin_period_tmp > 52.630)) && (pmcd_mode == 0) && (clkinsel_in == 1)) begin + $display("Attribute Syntax Error : CLKIN1_PERIOD is not in range 1.0 ... 52.630."); + end + clkin_period_tmp = CLKIN2_PERIOD; + if (((clkin_period_tmp < 1.0) || (clkin_period_tmp > 52.630)) && (pmcd_mode == 0) && (clkinsel_in == 0)) begin + $display("Attribute Syntax Error : CLKIN2_PERIOD is not in range 1.0 ... 52.630."); + end + + + case (RESET_ON_LOSS_OF_LOCK) + "FALSE" : rst_on_loss = 1'b0; +// "TRUE" : if (pmcd_mode) rst_on_loss = 1'b0; else rst_on_loss = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute RESET_ON_LOSS_OF_LOCK on PLL_ADV instance %m is set to %s. This attribute must always be set to FALSE for PLL_ADV to function correctly. Please correct the setting for the attribute and re-run the simulation.", RESET_ON_LOSS_OF_LOCK); + $finish; + end + endcase + + if (clkfb_src == 1 && clkfb_mult_tl > 64 ) begin + $display("Attribute Syntax Error : The Attributes CLKFBOUT_MULT and CLKOUT0_DIVIDE on PLL_ADV instance %m are set to %d and %d. The product of CLKFBOUT_MULT and CLKOUT0_DIVIDE is %d, which is over the 64 limit.", CLKFBOUT_MULT, CLKOUT0_DIVIDE, clkfb_mult_tl); + $finish; + end + + pll_lfhf = 2'b11; + + case (clkfb_mult_tl) +1 : if (BANDWIDTH === "HIGH" || BANDWIDTH === "OPTIMIZED") begin pll_cp = 4'b0010; pll_res = 4'b1011; end + else if (BANDWIDTH === "LOW") begin pll_cp = 4'b0001; pll_res = 4'b1101; end +2 : if (BANDWIDTH === "HIGH" || BANDWIDTH === "OPTIMIZED") begin pll_cp = 4'b0101; pll_res = 4'b1111; end + else if (BANDWIDTH === "LOW") begin pll_cp = 4'b0001; pll_res = 4'b1110; end +3 : if (BANDWIDTH === "HIGH" || BANDWIDTH === "OPTIMIZED") begin pll_cp = 4'b1100; pll_res = 4'b1111; end + else if (BANDWIDTH === "LOW") begin pll_cp = 4'b0001; pll_res = 4'b0110; end +4 : if (BANDWIDTH === "HIGH" || BANDWIDTH === "OPTIMIZED") begin pll_cp = 4'b1111; pll_res = 4'b1111; end + else if (BANDWIDTH === "LOW") begin pll_cp = 4'b0001; pll_res = 4'b1010; end +5 : if (BANDWIDTH === "HIGH" || BANDWIDTH === "OPTIMIZED") begin pll_cp = 4'b1111; pll_res = 4'b0111; end + else if (BANDWIDTH === "LOW") begin pll_cp = 4'b0001; pll_res = 4'b1100; end +6 : if (BANDWIDTH === "HIGH" || BANDWIDTH === "OPTIMIZED") begin pll_cp = 4'b1111; pll_res = 4'b1101; end + else if (BANDWIDTH === "LOW") begin pll_cp = 4'b0001; pll_res = 4'b1100; end +7 : if (BANDWIDTH === "HIGH" || BANDWIDTH === "OPTIMIZED") begin pll_cp = 4'b1111; pll_res = 4'b0011; end + else if (BANDWIDTH === "LOW") begin pll_cp = 4'b0001; pll_res = 4'b1100; end +8 : if (BANDWIDTH === "HIGH" || BANDWIDTH === "OPTIMIZED") begin pll_cp = 4'b1111; pll_res = 4'b0101; end + else if (BANDWIDTH === "LOW") begin pll_cp = 4'b0001; pll_res = 4'b0010; end +9 : if (BANDWIDTH === "HIGH" || BANDWIDTH === "OPTIMIZED") begin pll_cp = 4'b1111; pll_res = 4'b1001; end + else if (BANDWIDTH === "LOW") begin pll_cp = 4'b0001; pll_res = 4'b0010; end +10 : if (BANDWIDTH === "HIGH" || BANDWIDTH === "OPTIMIZED") begin pll_cp = 4'b1110; pll_res = 4'b1110; end + else if (BANDWIDTH === "LOW") begin pll_cp = 4'b0001; pll_res = 4'b0100; end +11 : if (BANDWIDTH === "HIGH" || BANDWIDTH === "OPTIMIZED") begin pll_cp = 4'b1111; pll_res = 4'b1110; end + else if (BANDWIDTH === "LOW") begin pll_cp = 4'b0001; pll_res = 4'b0100; end +12 : if (BANDWIDTH === "HIGH" || BANDWIDTH === "OPTIMIZED") begin pll_cp = 4'b1111; pll_res = 4'b1110; end + else if (BANDWIDTH === "LOW") begin pll_cp = 4'b0001; pll_res = 4'b0100; end +13 : if (BANDWIDTH === "HIGH" || BANDWIDTH === "OPTIMIZED") begin pll_cp = 4'b1111; pll_res = 4'b0001; end + else if (BANDWIDTH === "LOW") begin pll_cp = 4'b0001; pll_res = 4'b0100; end +14 : if (BANDWIDTH === "HIGH" || BANDWIDTH === "OPTIMIZED") begin pll_cp = 4'b1111; pll_res = 4'b0001; end + else if (BANDWIDTH === "LOW") begin pll_cp = 4'b0001; pll_res = 4'b0100; end +15 : if (BANDWIDTH === "HIGH" || BANDWIDTH === "OPTIMIZED") begin pll_cp = 4'b1111; pll_res = 4'b0001; end + else if (BANDWIDTH === "LOW") begin pll_cp = 4'b0001; pll_res = 4'b0100; end +16 : if (BANDWIDTH === "HIGH" || BANDWIDTH === "OPTIMIZED") begin pll_cp = 4'b1110; pll_res = 4'b0110; end + else if (BANDWIDTH === "LOW") begin pll_cp = 4'b0001; pll_res = 4'b0100; end +17 : if (BANDWIDTH === "HIGH" || BANDWIDTH === "OPTIMIZED") begin pll_cp = 4'b1110; pll_res = 4'b0110; end + else if (BANDWIDTH === "LOW") begin pll_cp = 4'b0001; pll_res = 4'b0100; end +18 : if (BANDWIDTH === "HIGH" || BANDWIDTH === "OPTIMIZED") begin pll_cp = 4'b1111; pll_res = 4'b0110; end + else if (BANDWIDTH === "LOW") begin pll_cp = 4'b0001; pll_res = 4'b0100; end +19 : if (BANDWIDTH === "HIGH" || BANDWIDTH === "OPTIMIZED") begin pll_cp = 4'b1110; pll_res = 4'b1010; end + else if (BANDWIDTH === "LOW") begin pll_cp = 4'b0001; pll_res = 4'b1000; end +20 : if (BANDWIDTH === "HIGH" || BANDWIDTH === "OPTIMIZED") begin pll_cp = 4'b1110; pll_res = 4'b1010; end + else if (BANDWIDTH === "LOW") begin pll_cp = 4'b0001; pll_res = 4'b1000; end +21 : if (BANDWIDTH === "HIGH" || BANDWIDTH === "OPTIMIZED") begin pll_cp = 4'b1111; pll_res = 4'b1010; end + else if (BANDWIDTH === "LOW") begin pll_cp = 4'b0001; pll_res = 4'b1000; end +22 : if (BANDWIDTH === "HIGH" || BANDWIDTH === "OPTIMIZED") begin pll_cp = 4'b1111; pll_res = 4'b1010; end + else if (BANDWIDTH === "LOW") begin pll_cp = 4'b0001; pll_res = 4'b1000; end +23 : if (BANDWIDTH === "HIGH" || BANDWIDTH === "OPTIMIZED") begin pll_cp = 4'b1111; pll_res = 4'b1010; end + else if (BANDWIDTH === "LOW") begin pll_cp = 4'b0001; pll_res = 4'b1000; end +24 : if (BANDWIDTH === "HIGH" || BANDWIDTH === "OPTIMIZED") begin pll_cp = 4'b1111; pll_res = 4'b1010; end + else if (BANDWIDTH === "LOW") begin pll_cp = 4'b0001; pll_res = 4'b1000; end +25 : if (BANDWIDTH === "HIGH" || BANDWIDTH === "OPTIMIZED") begin pll_cp = 4'b1111; pll_res = 4'b1010; end + else if (BANDWIDTH === "LOW") begin pll_cp = 4'b0001; pll_res = 4'b1000; end +26 : if (BANDWIDTH === "HIGH" || BANDWIDTH === "OPTIMIZED") begin pll_cp = 4'b1111; pll_res = 4'b1010; end + else if (BANDWIDTH === "LOW") begin pll_cp = 4'b0001; pll_res = 4'b1000; end +27 : if (BANDWIDTH === "HIGH" || BANDWIDTH === "OPTIMIZED") begin pll_cp = 4'b1101; pll_res = 4'b1100; end + else if (BANDWIDTH === "LOW") begin pll_cp = 4'b0001; pll_res = 4'b1000; end +28 : if (BANDWIDTH === "HIGH" || BANDWIDTH === "OPTIMIZED") begin pll_cp = 4'b1101; pll_res = 4'b1100; end + else if (BANDWIDTH === "LOW") begin pll_cp = 4'b0001; pll_res = 4'b1000; end +29 : if (BANDWIDTH === "HIGH" || BANDWIDTH === "OPTIMIZED") begin pll_cp = 4'b1101; pll_res = 4'b1100; end + else if (BANDWIDTH === "LOW") begin pll_cp = 4'b0001; pll_res = 4'b1000; end +30 : if (BANDWIDTH === "HIGH" || BANDWIDTH === "OPTIMIZED") begin pll_cp = 4'b1110; pll_res = 4'b1100; end + else if (BANDWIDTH === "LOW") begin pll_cp = 4'b0001; pll_res = 4'b1000; end +31 : if (BANDWIDTH === "HIGH" || BANDWIDTH === "OPTIMIZED") begin pll_cp = 4'b1101; pll_res = 4'b1100; end + else if (BANDWIDTH === "LOW") begin pll_cp = 4'b0010; pll_res = 4'b0100; end +32 : if (BANDWIDTH === "HIGH" || BANDWIDTH === "OPTIMIZED") begin pll_cp = 4'b1100; pll_res = 4'b0010; end + else if (BANDWIDTH === "LOW") begin pll_cp = 4'b0010; pll_res = 4'b0100; end +33 : if (BANDWIDTH === "HIGH" || BANDWIDTH === "OPTIMIZED") begin pll_cp = 4'b1111; pll_res = 4'b1010; end + else if (BANDWIDTH === "LOW") begin pll_cp = 4'b0010; pll_res = 4'b0100; end +34 : if (BANDWIDTH === "HIGH" || BANDWIDTH === "OPTIMIZED") begin pll_cp = 4'b0111; pll_res = 4'b0010; end + else if (BANDWIDTH === "LOW") begin pll_cp = 4'b0010; pll_res = 4'b0100; end +35 : if (BANDWIDTH === "HIGH" || BANDWIDTH === "OPTIMIZED") begin pll_cp = 4'b0111; pll_res = 4'b0010; end + else if (BANDWIDTH === "LOW") begin pll_cp = 4'b0010; pll_res = 4'b0100; end +36 : if (BANDWIDTH === "HIGH" || BANDWIDTH === "OPTIMIZED") begin pll_cp = 4'b0111; pll_res = 4'b0010; end + else if (BANDWIDTH === "LOW") begin pll_cp = 4'b0010; pll_res = 4'b0100; end +37 : if (BANDWIDTH === "HIGH" || BANDWIDTH === "OPTIMIZED") begin pll_cp = 4'b0110; pll_res = 4'b0010; end + else if (BANDWIDTH === "LOW") begin pll_cp = 4'b0010; pll_res = 4'b0100; end +38 : if (BANDWIDTH === "HIGH" || BANDWIDTH === "OPTIMIZED") begin pll_cp = 4'b0110; pll_res = 4'b0010; end + else if (BANDWIDTH === "LOW") begin pll_cp = 4'b0010; pll_res = 4'b1000; end +39 : if (BANDWIDTH === "HIGH" || BANDWIDTH === "OPTIMIZED") begin pll_cp = 4'b0110; pll_res = 4'b0010; end + else if (BANDWIDTH === "LOW") begin pll_cp = 4'b0010; pll_res = 4'b1000; end +40 : if (BANDWIDTH === "HIGH" || BANDWIDTH === "OPTIMIZED") begin pll_cp = 4'b0110; pll_res = 4'b0010; end + else if (BANDWIDTH === "LOW") begin pll_cp = 4'b0010; pll_res = 4'b1000; end +41 : if (BANDWIDTH === "HIGH" || BANDWIDTH === "OPTIMIZED") begin pll_cp = 4'b0110; pll_res = 4'b0010; end + else if (BANDWIDTH === "LOW") begin pll_cp = 4'b0010; pll_res = 4'b1000; end +42 : if (BANDWIDTH === "HIGH" || BANDWIDTH === "OPTIMIZED") begin pll_cp = 4'b0100; pll_res = 4'b0100; end + else if (BANDWIDTH === "LOW") begin pll_cp = 4'b0010; pll_res = 4'b1000; end +43 : if (BANDWIDTH === "HIGH" || BANDWIDTH === "OPTIMIZED") begin pll_cp = 4'b0100; pll_res = 4'b0100; end + else if (BANDWIDTH === "LOW") begin pll_cp = 4'b0010; pll_res = 4'b1000; end +44 : if (BANDWIDTH === "HIGH" || BANDWIDTH === "OPTIMIZED") begin pll_cp = 4'b0100; pll_res = 4'b0100; end + else if (BANDWIDTH === "LOW") begin pll_cp = 4'b0010; pll_res = 4'b1000; end +45 : if (BANDWIDTH === "HIGH" || BANDWIDTH === "OPTIMIZED") begin pll_cp = 4'b0011; pll_res = 4'b1000; end + else if (BANDWIDTH === "LOW") begin pll_cp = 4'b0010; pll_res = 4'b1000; end +46 : if (BANDWIDTH === "HIGH" || BANDWIDTH === "OPTIMIZED") begin pll_cp = 4'b0011; pll_res = 4'b1000; end + else if (BANDWIDTH === "LOW") begin pll_cp = 4'b0010; pll_res = 4'b1000; end +47 : if (BANDWIDTH === "HIGH" || BANDWIDTH === "OPTIMIZED") begin pll_cp = 4'b0011; pll_res = 4'b0100; end + else if (BANDWIDTH === "LOW") begin pll_cp = 4'b0010; pll_res = 4'b1000; end +48 : if (BANDWIDTH === "HIGH" || BANDWIDTH === "OPTIMIZED") begin pll_cp = 4'b0011; pll_res = 4'b0100; end + else if (BANDWIDTH === "LOW") begin pll_cp = 4'b0010; pll_res = 4'b1000; end +49 : if (BANDWIDTH === "HIGH" || BANDWIDTH === "OPTIMIZED") begin pll_cp = 4'b0011; pll_res = 4'b0100; end + else if (BANDWIDTH === "LOW") begin pll_cp = 4'b0010; pll_res = 4'b1000; end +50 : if (BANDWIDTH === "HIGH" || BANDWIDTH === "OPTIMIZED") begin pll_cp = 4'b0011; pll_res = 4'b0100; end + else if (BANDWIDTH === "LOW") begin pll_cp = 4'b0010; pll_res = 4'b1000; end +51 : if (BANDWIDTH === "HIGH" || BANDWIDTH === "OPTIMIZED") begin pll_cp = 4'b0011; pll_res = 4'b0100; end + else if (BANDWIDTH === "LOW") begin pll_cp = 4'b0010; pll_res = 4'b1000; end +52 : if (BANDWIDTH === "HIGH" || BANDWIDTH === "OPTIMIZED") begin pll_cp = 4'b0011; pll_res = 4'b0100; end + else if (BANDWIDTH === "LOW") begin pll_cp = 4'b0010; pll_res = 4'b1000; end +53 : if (BANDWIDTH === "HIGH" || BANDWIDTH === "OPTIMIZED") begin pll_cp = 4'b0011; pll_res = 4'b0100; end + else if (BANDWIDTH === "LOW") begin pll_cp = 4'b0010; pll_res = 4'b1000; end +54 : if (BANDWIDTH === "HIGH" || BANDWIDTH === "OPTIMIZED") begin pll_cp = 4'b0011; pll_res = 4'b0100; end + else if (BANDWIDTH === "LOW") begin pll_cp = 4'b0010; pll_res = 4'b1000; end +55 : if (BANDWIDTH === "HIGH" || BANDWIDTH === "OPTIMIZED") begin pll_cp = 4'b0011; pll_res = 4'b0100; end + else if (BANDWIDTH === "LOW") begin pll_cp = 4'b0010; pll_res = 4'b1000; end +56 : if (BANDWIDTH === "HIGH" || BANDWIDTH === "OPTIMIZED") begin pll_cp = 4'b0011; pll_res = 4'b0100; end + else if (BANDWIDTH === "LOW") begin pll_cp = 4'b0010; pll_res = 4'b1000; end +57 : if (BANDWIDTH === "HIGH" || BANDWIDTH === "OPTIMIZED") begin pll_cp = 4'b0010; pll_res = 4'b1000; end + else if (BANDWIDTH === "LOW") begin pll_cp = 4'b0010; pll_res = 4'b1000; end +58 : if (BANDWIDTH === "HIGH" || BANDWIDTH === "OPTIMIZED") begin pll_cp = 4'b0010; pll_res = 4'b1000; end + else if (BANDWIDTH === "LOW") begin pll_cp = 4'b0010; pll_res = 4'b1000; end +59 : if (BANDWIDTH === "HIGH" || BANDWIDTH === "OPTIMIZED") begin pll_cp = 4'b0010; pll_res = 4'b1000; end + else if (BANDWIDTH === "LOW") begin pll_cp = 4'b0010; pll_res = 4'b1000; end +60 : if (BANDWIDTH === "HIGH" || BANDWIDTH === "OPTIMIZED") begin pll_cp = 4'b0010; pll_res = 4'b1000; end + else if (BANDWIDTH === "LOW") begin pll_cp = 4'b0010; pll_res = 4'b1000; end +61 : if (BANDWIDTH === "HIGH" || BANDWIDTH === "OPTIMIZED") begin pll_cp = 4'b0010; pll_res = 4'b1000; end + else if (BANDWIDTH === "LOW") begin pll_cp = 4'b0010; pll_res = 4'b1000; end +62 : if (BANDWIDTH === "HIGH" || BANDWIDTH === "OPTIMIZED") begin pll_cp = 4'b0010; pll_res = 4'b1000; end + else if (BANDWIDTH === "LOW") begin pll_cp = 4'b0010; pll_res = 4'b1000; end +63 : if (BANDWIDTH === "HIGH" || BANDWIDTH === "OPTIMIZED") begin pll_cp = 4'b0010; pll_res = 4'b1000; end + else if (BANDWIDTH === "LOW") begin pll_cp = 4'b0010; pll_res = 4'b1000; end +64 : if (BANDWIDTH === "HIGH" || BANDWIDTH === "OPTIMIZED") begin pll_cp = 4'b0010; pll_res = 4'b1000; end + else if (BANDWIDTH === "LOW") begin pll_cp = 4'b0010; pll_res = 4'b1000; end + endcase + + + tmp_string = "DIVCLK_DIVIDE"; + chk_ok = para_int_range_chk (DIVCLK_DIVIDE, tmp_string, D_MIN, D_MAX); + + tmp_string = "CLKFBOUT_MULT"; + chk_ok = para_int_range_chk (CLKFBOUT_MULT, tmp_string, M_MIN, M_MAX); + + tmp_string = "CLKOUT0_DUTY_CYCLE"; + chk_ok = clkout_duty_chk (CLKOUT0_DIVIDE, CLKOUT0_DUTY_CYCLE, tmp_string); + tmp_string = "CLKOUT1_DUTY_CYCLE"; + chk_ok = clkout_duty_chk (CLKOUT1_DIVIDE, CLKOUT1_DUTY_CYCLE, tmp_string); + tmp_string = "CLKOUT2_DUTY_CYCLE"; + chk_ok = clkout_duty_chk (CLKOUT2_DIVIDE, CLKOUT2_DUTY_CYCLE, tmp_string); + tmp_string = "CLKOUT3_DUTY_CYCLE"; + chk_ok = clkout_duty_chk (CLKOUT3_DIVIDE, CLKOUT3_DUTY_CYCLE, tmp_string); + tmp_string = "CLKOUT4_DUTY_CYCLE"; + chk_ok = clkout_duty_chk (CLKOUT4_DIVIDE, CLKOUT4_DUTY_CYCLE, tmp_string); + tmp_string = "CLKOUT5_DUTY_CYCLE"; + chk_ok = clkout_duty_chk (CLKOUT5_DIVIDE, CLKOUT5_DUTY_CYCLE, tmp_string); + + period_vco_max = 1000000 / VCOCLK_FREQ_MIN; + period_vco_min = 1000000 / VCOCLK_FREQ_MAX; + period_vco_target = 1000000 / VCOCLK_FREQ_TARGET; + period_vco_target_half = period_vco_target / 2; + fb_delay_max = MAX_FEEDBACK_DELAY * MAX_FEEDBACK_DELAY_SCALE; +// md_product = CLKFBOUT_MULT * DIVCLK_DIVIDE; +// m_product = CLKFBOUT_MULT; +// m_product2 = CLKFBOUT_MULT / 2; + md_product = clkfb_mult_tl * DIVCLK_DIVIDE; + m_product = clkfb_mult_tl; + m_product2 = clkfb_mult_tl / 2; + clkout_en_time = PLL_LOCK_TIME + 2; + locked_en_time = md_product + clkout_en_time + 2; // for DCM 3 cycle reset requirement + lock_cnt_max = locked_en_time + 10 + CLKFBOUT_MULT; + REF_CLK_JITTER_MAX_tmp = REF_CLK_JITTER_MAX; + + clk_out_para_cal (clk0_ht, clk0_lt, clk0_nocnt, clk0_edge, CLKOUT0_DIVIDE, CLKOUT0_DUTY_CYCLE); + clk_out_para_cal (clk1_ht, clk1_lt, clk1_nocnt, clk1_edge, CLKOUT1_DIVIDE, CLKOUT1_DUTY_CYCLE); + clk_out_para_cal (clk2_ht, clk2_lt, clk2_nocnt, clk2_edge, CLKOUT2_DIVIDE, CLKOUT2_DUTY_CYCLE); + clk_out_para_cal (clk3_ht, clk3_lt, clk3_nocnt, clk3_edge, CLKOUT3_DIVIDE, CLKOUT3_DUTY_CYCLE); + clk_out_para_cal (clk4_ht, clk4_lt, clk4_nocnt, clk4_edge, CLKOUT4_DIVIDE, CLKOUT4_DUTY_CYCLE); + clk_out_para_cal (clk5_ht, clk5_lt, clk5_nocnt, clk5_edge, CLKOUT5_DIVIDE, CLKOUT5_DUTY_CYCLE); + if (clkfb_src ==1) begin + clk_out_para_cal (clkfbm2_ht, clkfbm2_lt, clkfbm2_nocnt, clkfbm2_edge, CLKFBOUT_MULT, 0.50); + clkout0_ps_tmp = CLKOUT0_PHASE; + clkfbm1_ht = 6'b0; + clkfbm1_lt = 6'b0; + clkfbm1_nocnt = 1; + clkfbm1_edge = 0; + end + else begin + clk_out_para_cal (clkfbm1_ht, clkfbm1_lt, clkfbm1_nocnt, clkfbm1_edge, CLKFBOUT_MULT, 0.50); + clkout0_ps_tmp = CLKOUT0_PHASE; + clkfbm2_ht = 6'b0; + clkfbm2_lt = 6'b0; + clkfbm2_nocnt = 1; + clkfbm2_edge = 0; + end + + clk_out_para_cal (clkind_ht, clkind_lt, clkind_nocnt, clkind_edge, DIVCLK_DIVIDE, 0.50); + tmp_string = "CLKOUT0_PHASE"; + clkout_dly_cal (clkout0_dly, clk0pm_sel, CLKOUT0_DIVIDE, clkout0_ps_tmp, tmp_string); + tmp_string = "CLKOUT1_PHASE"; + clkout_dly_cal (clkout1_dly, clk1pm_sel, CLKOUT1_DIVIDE, CLKOUT1_PHASE, tmp_string); + tmp_string = "CLKOUT2_PHASE"; + clkout_dly_cal (clkout2_dly, clk2pm_sel, CLKOUT2_DIVIDE, CLKOUT2_PHASE, tmp_string); + tmp_string = "CLKOUT3_PHASE"; + clkout_dly_cal (clkout3_dly, clk3pm_sel, CLKOUT3_DIVIDE, CLKOUT3_PHASE, tmp_string); + tmp_string = "CLKOUT4_PHASE"; + clkout_dly_cal (clkout4_dly, clk4pm_sel, CLKOUT4_DIVIDE, CLKOUT4_PHASE, tmp_string); + tmp_string = "CLKOUT5_PHASE"; + clkout_dly_cal (clkout5_dly, clk5pm_sel, CLKOUT5_DIVIDE, CLKOUT5_PHASE, tmp_string); + tmp_string = "CLKFBOUT_PHASE"; + if (clkfb_src == 1) begin + clkfbm2_dly = 6'b0; + clkfbm2pm_sel = 3'b0; + clkfbm1_dly = 6'b0; + clkfbm1pm_sel = 3'b0; + end + else begin + clkout_dly_cal (clkfbm1_dly, clkfbm1pm_sel, CLKFBOUT_MULT, CLKFBOUT_PHASE, tmp_string); + clkfbm2_dly = 6'b0; + clkfbm2pm_sel = 3'b0; + end + + clkind_div = DIVCLK_DIVIDE; + + if (sim_d == 1) begin + dr_sram[5'b00101] = {clkout0_dly[5], 1'bx, clkout0_dly[4], 1'bx, clkout0_dly[2], + clkout0_dly[3], clkout0_dly[1], clkout0_dly[0], 8'bx}; + dr_sram[5'b00110] = {clk1_lt[4], clk1_lt[5], clk1_lt[3], clk1_nocnt, clk1_lt[1], + clk1_lt[2], clkout1_dly[5], 1'bx, clkout1_dly[3], clkout1_dly[2], + clkout1_dly[0], clkout1_dly[1], 1'bx, clk0_edge, 2'bx}; + + dr_sram[5'b00111] = {1'b1, 2'bx, clk1_ht[5], clk1_ht[3], clk1_ht[4], clk1_ht[2:0], clk1pm_sel[0], 1'bx, clk1_edge, 1'b1, 1'bx, clk1pm_sel[1], clk1pm_sel[2]}; + + dr_sram[5'b01000] = {clk2pm_sel[2], 1'b1, clk2_lt[5], clk2pm_sel[1],clk2_nocnt, + clk2_lt[4], clk2_lt[3], clk2_lt[2], clk2_lt[0], + clkout2_dly[5], clkout2_dly[3], clkout2_dly[4], + clkout2_dly[1], clkout2_dly[2], clkout2_dly[0], 1'bx}; + + dr_sram[5'b01001] = {clkout3_dly[0], clkout3_dly[1], clk0pm_sel[1], + clk0pm_sel[2], 2'bx, clk2_ht[4], 1'bx, clk2_ht[3], + clk2_ht[2], clk2_ht[0], clk2_ht[1], clk2_edge, + clk2pm_sel[0], 2'bx}; + + dr_sram[5'b01010] = {1'bx, clk3_edge, 1'b1, 1'bx, clk3pm_sel[1], + clk3pm_sel[2], clk3_lt[5], clk3_lt[4], clk3_nocnt, + clk3_lt[2], clk3_lt[0], clk3_lt[1], clkout3_dly[4], + clkout3_dly[5], clkout3_dly[3], 1'bx}; + + dr_sram[5'b01011] = {clk0_lt[5], clkout4_dly[5], clkout4_dly[0], + clkout4_dly[3], clkout4_dly[1], clkout4_dly[2], + clk0_lt[4], 1'bx, clk3_ht[5:3], 1'bx, clk3_ht[1], + clk3_ht[2], clk3pm_sel[0], clk3_ht[0]}; + + dr_sram[5'b01100] = {clk4_ht[1], clk4_ht[2], clk4pm_sel[0], clk4_ht[0], + 1'bx, clk4_edge, 1'bx, 1'b1, clk4pm_sel[2], clk4pm_sel[1], + clk4_lt[4], clk4_lt[5], clk4_lt[3], clk4_nocnt, + clk4_lt[1], clk4_lt[2]}; + + dr_sram[5'b01101] = {clk5_lt[2], clk5_lt[3], clk5_lt[0], clk5_lt[1], + clkout5_dly[4], clkout5_dly[5], clkout5_dly[3], + clkout5_dly[2], clkout5_dly[1], clk0_lt[3], + clk0_lt[0], clk0_lt[2], 1'bx, clk4_ht[5], + clk4_ht[3], clk4_ht[4]}; + + dr_sram[5'b01110] = {clk5_ht[4], clk5_ht[5], clk5_ht[2], clk5_ht[3], + clk5_ht[0], clk5_ht[1], clk5pm_sel[0], clk5_edge, + 2'bx, clk5pm_sel[2], 1'b1, clk5_lt[5], clk5pm_sel[1], + clk5_nocnt, clk5_lt[4]}; + + dr_sram[5'b01111] = {clkfbm1_lt[4], clkfbm1_lt[5], clkfbm1_lt[3], + clkfbm1_nocnt, clkfbm1_lt[1], clkfbm1_lt[2], clkfbm1_lt[0], + clkfbm1_dly[5], clkfbm1_dly[4], clkfbm1_dly[3], + clkfbm1_dly[1], clkfbm1_dly[2], clk0_nocnt, clk0_lt[1], 2'bx}; + + dr_sram[5'b10000] = {1'bx, clk0_ht[3], clk0_ht[5], clk0_ht[4], clkfbm1_ht[4], + clkfbm1_ht[5], clkfbm1_ht[3:0], clkfbm1_edge, + clkfbm1pm_sel[0], 1'b1, 1'bx, clkfbm1pm_sel[1], clkfbm1pm_sel[2]}; + dr_sram[5'b10001] = {clkfbm2_lt[0], clkfbm2_dly[3], clkfbm2_ht[2], clkfbm2_ht[1], + clkfbm2_lt[1], clkfbm2_ht[4], clk3_lt[3], clkout3_dly[2], + clk2_ht[5], clk2_lt[1], clkout1_dly[4], clk1_lt[0], + clk0_ht[0], clk0pm_sel[0], clk0_ht[2], clk0_ht[1]}; + dr_sram[5'b10010] = {4'bx, clkout5_dly[0], clkfbm1_dly[0], clk4_lt[0], + clkout4_dly[4], 4'bx, clkfbm2_nocnt, 1'bx, clkfbm2_dly[2], + clkfbm2_lt[4]}; + dr_sram[5'b10011] = {clkind_ht[5], clkfbm2_ht[3], clkind_ht[4], 1'bx, + clkind_ht[1], clkind_ht[2], clkind_lt[0], 1'bx, + clkind_lt[5], clkind_lt[2], 1'bx, clkind_edge, 4'bx}; + dr_sram[5'b10100] = {6'bx, pll_res[1], pll_res[3], + pll_res[0], pll_cpres[0], pll_cpres[1], clkfbm2_dly[1], + clkfbm2_lt[3], clkfbm2_ht[0], clkfbm2_dly[4], + clkfbm2_dly[0], clkfbm2_dly[5], clkfbm2_ht[5]}; + dr_sram[5'b10101] = {1'bx, clkind_nocnt, 7'bx, clkfbm2_edge, clkfbm2_lt[5], + clkfbm2_lt[2], 4'bx}; + dr_sram[5'b10110] = {4'bx, pll_lfhf[0], 2'bx, clkind_ht[3], clkind_lt[1], + 1'bx, clkind_ht[0], 1'bx, clkind_lt[3], 1'bx, + clkind_lt[4], 1'bx}; + dr_sram[5'b10111] = {6'bx, pll_lfhf[1], 9'bx}; + dr_sram[5'b11000] = {pll_res[0], pll_res[1], pll_cp[0], 1'bx, pll_cp[2], pll_cp[1], pll_cp[0], pll_cp[3], pll_res[3], pll_res[2], 6'bx}; + + end + else begin + dr_sram[5'b11100] = {8'bx, clk0_edge, clk0_nocnt, clkout0_dly[5:0]}; + dr_sram[5'b11011] = {clk0pm_sel[2:0], 1'b1, clk0_ht[5:0], clk0_lt[5:0]}; + dr_sram[5'b11010] = {8'bx, clk1_edge, clk1_nocnt, clkout1_dly[5:0]}; + dr_sram[5'b11001] = {clk1pm_sel[2:0], 1'b1, clk1_ht[5:0], clk1_lt[5:0]}; + dr_sram[5'b10111] = {8'bx, clk2_edge, clk2_nocnt, clkout2_dly[5:0]}; + dr_sram[5'b10110] = {clk2pm_sel[2:0], 1'b1, clk2_ht[5:0], clk2_lt[5:0]}; + dr_sram[5'b10101] = {8'bx, clk3_edge, clk3_nocnt, clkout3_dly[5:0]}; + dr_sram[5'b10100] = {clk3pm_sel[2:0], 1'b1, clk3_ht[5:0], clk3_lt[5:0]}; + dr_sram[5'b10011] = {8'bx, clk4_edge, clk4_nocnt, clkout4_dly[5:0]}; + dr_sram[5'b10010] = {clk4pm_sel[2:0], 1'b1, clk4_ht[5:0], clk4_lt[5:0]}; + dr_sram[5'b01111] = {8'bx, clk5_edge, clk5_nocnt, clkout5_dly[5:0]}; + dr_sram[5'b01110] = {clk5pm_sel[2:0], 1'b1, clk5_ht[5:0], clk5_lt[5:0]}; + dr_sram[5'b01101] = {8'bx, clkfbm1_edge, clkfbm1_nocnt, clkfbm1_dly[5:0]}; + dr_sram[5'b01100] = {clkfbm1pm_sel[2:0], 1'b1, clkfbm1_ht[5:0], clkfbm1_lt[5:0]}; + dr_sram[5'b01010] = {8'bx, clkfbm2_edge, clkfbm2_nocnt, clkfbm2_dly[5:0]}; + dr_sram[5'b01001] = {4'bx, clkfbm2_ht[5:0], clkfbm2_lt[5:0]}; + + dr_sram[5'b00110] = {2'bx, clkind_edge, clkind_nocnt, clkind_ht[5:0], clkind_lt[5:0]}; + dr_sram[5'b00001] = {8'bx, pll_lfhf, pll_cpres, pll_cp}; + dr_sram[5'b00000] = {6'bx, pll_res, 6'bx}; + end + + +// **** PMCD ******* + +//*** Clocks MUX + + case (RST_DEASSERT_CLK) + "CLKIN1" : rel_o_mux_sel = 1'b1; + "CLKFBIN" : rel_o_mux_sel = 1'b0; + default : begin + $display("Attribute Syntax Error : The attribute RST_DEASSERT_CLK on PLL_ADV instance %m is set to %s. Legal values for this attribute are CLKIN1 and CLKFBIN.", RST_DEASSERT_CLK); + $finish; + end + endcase + +//*** CLKDIV_RST + case (EN_REL) + "FALSE" : clkdiv_rel_rst = 1'b0; + "TRUE" : clkdiv_rel_rst = 1'b1; + default : begin + $display("Attribute Syntax Error : The attribute EN_REL on PLL_ADV instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", EN_REL); + $finish; + end + endcase + + +end + +initial begin + rst_in1 = 0; + rst_unlock = 0; + clkin_period[0] = 0; + clkin_period[1] = 0; + clkin_period[2] = 0; + clkin_period[3] = 0; + clkin_period[4] = 0; + period_avg = 0; + period_fb = 0; + fb_delay = 0; + clkfbm1_div = 1; + clkfbm1_div1 = 0; + clkfbm2_div = 1; + clkfbm_div = 1; + clkvco_delay = 0; + fbm1_comp_delay = 0; + clkfbm1pm_rl = 0; + period_vco = 0; + period_vco1 = 0; + period_vco2 = 0; + period_vco3 = 0; + period_vco4 = 0; + period_vco5 = 0; + period_vco6 = 0; + period_vco7 = 0; + period_vco_half = 0; + period_vco_half1 = 0; + period_vco_half_rm = 0; + period_vco_half_rm1 = 0; + period_vco_half_rm2 = 0; + period_vco_rm = 0; + period_vco_cmp_cnt = 0; + period_vco_cmp_flag = 0; + clkvco_rm_cnt = 0; + fb_delay_found = 0; + fb_delay_found_tmp = 0; + clkin_edge = 0; + delay_edge = 0; + clkvco_free = 0; + clkvco_lk = 0; + fbclk_tmp = 0; + clkfb_tst = 0; + clkout_cnt = 0; + clkout_en = 0; + clkout_en0 = 0; + clkout_en0_tmp = 0; + clkout_en1 = 0; + pll_locked_tmp1 = 0; + pll_locked_tmp2 = 0; + pll_locked_tm = 0; + pll_locked_delay = 0; + clkout_mux = 3'b0; + unlock_recover = 0; + clkin_lost_val = 0; + clkin_lost_val = 0; + clk_osc = 0; + clkin_p = 0; + clkfb_p = 0; + clkin_lost_cnt = 0; + clkfb_lost_cnt = 0; + clkin_stopped = 0; + clkfb_stopped = 0; + clkpll_jitter_unlock = 0; + clkin_jit = 0; + clkin_cnt = 0; + clkin_lock_cnt = 0; + clkpll_dly = 0; + clkfbin_dly = 0; + lock_period = 0; + rst_edge = 0; + rst_ht = 0; + drdy_out = 0; + drp_lock = 0; + drp_lock1 = 0; + clkout0_out = 0; + clkout1_out = 0; + clkout2_out = 0; + clkout3_out = 0; + clkout4_out = 0; + clkout5_out = 0; + clka1_out = 1'b0; + clkb1_out = 1'b0; + clka1d2_out = 1'b0; + clka1d4_out = 1'b0; + clka1d8_out = 1'b0; + qrel_o_reg1 = 1'b0; + qrel_o_reg2 = 1'b0; + qrel_o_reg3 = 1'b0; + clk0_dly_cnt = 6'b0; + clk1_dly_cnt = 6'b0; + clk2_dly_cnt = 6'b0; + clk3_dly_cnt = 6'b0; + clk4_dly_cnt = 6'b0; + clk5_dly_cnt = 6'b0; + clkfbm1_dly_cnt = 6'b0; + clk0_cnt = 8'b0; + clk1_cnt = 8'b0; + clk2_cnt = 8'b0; + clk3_cnt = 8'b0; + clk4_cnt = 8'b0; + clk5_cnt = 8'b0; + clkfbm1_cnt = 8'b0; + clk0_out = 0; + clk1_out = 0; + clk2_out = 0; + clk3_out = 0; + clk4_out = 0; + clk5_out = 0; + clkfb_out = 0; + clkfbm1_out = 0; + pwron_int = 1; + #100000 pwron_int = 0; +end + +// PMCD function + +//*** asyn RST + always @(orig_rst_in) + if (orig_rst_in == 1'b1) begin + assign qrel_o_reg1 = 1'b1; + assign qrel_o_reg2 = 1'b1; + assign qrel_o_reg3 = 1'b1; + end + else if (orig_rst_in == 1'b0) begin + deassign qrel_o_reg1; + deassign qrel_o_reg2; + deassign qrel_o_reg3; + end + +//*** Clocks MUX + + assign rel_o_mux_clk_tmp = rel_o_mux_sel ? clkin1_in : clkfb_in; + assign rel_o_mux_clk = (pmcd_mode) ? rel_o_mux_clk_tmp : 0; + assign clka1_in = (pmcd_mode) ? clkin1_in : 0; + assign clkb1_in = (pmcd_mode) ? clkfb_in : 0; + + +//*** Rel and Rst + always @(posedge rel_o_mux_clk) + qrel_o_reg1 <= 1'b0; + + always @(negedge rel_o_mux_clk) + qrel_o_reg2 <= qrel_o_reg1; + + always @(posedge rel_in) + qrel_o_reg3 <= 1'b0; + + assign rel_rst_o = clkdiv_rel_rst ? (qrel_o_reg3 || qrel_o_reg1) : qrel_o_reg1; + +//*** CLKA + always @(clka1_in or qrel_o_reg2) + if (qrel_o_reg2 == 1'b1) + clka1_out <= 1'b0; + else if (qrel_o_reg2 == 1'b0) + clka1_out <= clka1_in; + +//*** CLKB + always @(clkb1_in or qrel_o_reg2) + if (qrel_o_reg2 == 1'b1) + clkb1_out <= 1'b0; + else if (qrel_o_reg2 == 1'b0) + clkb1_out <= clkb1_in; + + +//*** Clock divider + always @(posedge clka1_in or posedge rel_rst_o) + if (rel_rst_o == 1'b1) + clka1d2_out <= 1'b0; + else if (rel_rst_o == 1'b0) + clka1d2_out <= ~clka1d2_out; + + always @(posedge clka1d2_out or posedge rel_rst_o) + if (rel_rst_o == 1'b1) + clka1d4_out <= 1'b0; + else if (rel_rst_o == 1'b0) + clka1d4_out <= ~clka1d4_out; + + always @(posedge clka1d4_out or posedge rel_rst_o) + if (rel_rst_o == 1'b1) + clka1d8_out <= 1'b0; + else if (rel_rst_o == 1'b0) + clka1d8_out <= ~clka1d8_out; + + assign CLKOUT5 = (pmcd_mode) ? 0 : clkout5_out; + assign CLKOUT4 = (pmcd_mode) ? 0 : clkout4_out; + assign CLKOUT3 = (pmcd_mode) ? clka1_out : clkout3_out; + assign CLKOUT2 = (pmcd_mode) ? clka1d2_out : clkout2_out; + assign CLKOUT1 = (pmcd_mode) ? clka1d4_out : clkout1_out; + assign CLKOUT0 = (pmcd_mode) ? clka1d8_out : clkout0_out; + assign CLKFBOUT = (pmcd_mode) ? clkb1_out : clkfb_out; + assign CLKOUTDCM5 = (pmcd_mode) ? 0 : clkout5_out; + assign CLKOUTDCM4 = (pmcd_mode) ? 0 : clkout4_out; + assign CLKOUTDCM3 = (pmcd_mode) ? clka1_out : clkout3_out; + assign CLKOUTDCM2 = (pmcd_mode) ? clka1d2_out : clkout2_out; + assign CLKOUTDCM1 = (pmcd_mode) ? clka1d4_out : clkout1_out; + assign CLKOUTDCM0 = (pmcd_mode) ? clka1d8_out : clkout0_out; + assign CLKFBDCM = (pmcd_mode) ? clkb1_out : clkfb_out; + +// PLL function + + assign #1 clkinsel_tmp = clkinsel_in; + assign (weak1, strong0) glbl.PLL_LOCKG = (locked_out == 0) ? 0 : p_up; + +always @(clkinsel_in ) + if (pmcd_mode != 1) begin + if ($time > 1 && rst_in === 0 && (clkinsel_tmp === 0 || clkinsel_tmp === 1)) begin + $display("Input Error : PLL input clock can only be switched when RST=1. CLKINSEL on instance %m at time %t changed when RST low, should change at RST high.", $time); + $finish; + end + + clkin_chk_t1 = 1000.0 / CLKIN_FREQ_MIN; + clkin_chk_t2 = 1000.0 / CLKIN_FREQ_MAX; + + if (clkinsel_in ==1) begin + if (CLKIN1_PERIOD > clkin_chk_t1 || CLKIN1_PERIOD < clkin_chk_t2) begin + $display (" Attribute Syntax Error : The attribute CLKIN1_PERIOD is set to %f ns and out the allowed range %f ns to %f ns.", CLKIN1_PERIOD, clkin_chk_t2, clkin_chk_t1); + $finish; + end + end + else if (clkinsel_in ==0) begin + if (CLKIN2_PERIOD > clkin_chk_t1 || CLKIN2_PERIOD < clkin_chk_t2) begin + $display (" Attribute Syntax Error : The attribute CLKIN2_PERIOD is set to %f ns and out the allowed range %f ns to %f ns.", CLKIN2_PERIOD, clkin_chk_t2, clkin_chk_t1); + $finish; + end + end + + period_clkin = (clkinsel_in) ? CLKIN1_PERIOD : CLKIN2_PERIOD; + if (clkfb_src == 1) + clkvco_freq_init_chk = ( 1000.0 * CLKFBOUT_MULT * CLKOUT0_DIVIDE) / (period_clkin * DIVCLK_DIVIDE); + else + clkvco_freq_init_chk = (1000.0 * CLKFBOUT_MULT) / (period_clkin * DIVCLK_DIVIDE); + + if (clkvco_freq_init_chk > VCOCLK_FREQ_MAX || clkvco_freq_init_chk < VCOCLK_FREQ_MIN) begin + if (clkfb_src == 1) begin + $display (" Attribute Syntax Error : The calculation of VCO frequency=%f Mhz. This exceeds the permitted VCO frequency range of %f Mhz to %f Mhz. The VCO frequency is calculated with formula: VCO frequency = CLKFBOUT_MULT * CLKOUT0_DIVIDE/ (DIVCLK_DIVIDE * CLKIN_PERIOD). Please adjust the attributes to the permitted VCO frequency range.", clkvco_freq_init_chk, VCOCLK_FREQ_MIN, VCOCLK_FREQ_MAX); + $finish; + end + else begin + $display (" Attribute Syntax Error : The calculation of VCO frequency=%f Mhz. This exceeds the permitted VCO frequency range of %f Mhz to %f Mhz. The VCO frequency is calculated with formula: VCO frequency = CLKFBOUT_MULT / (DIVCLK_DIVIDE * CLKIN_PERIOD). Please adjust the attributes to the permitted VCO frequency range.", clkvco_freq_init_chk, VCOCLK_FREQ_MIN, VCOCLK_FREQ_MAX); + $finish; + end + end + +end + + assign init_trig = 1; + + + assign clkpll_tmp = (clkinsel_in) ? clkin1_in : clkin2_in; + assign clkpll = (pmcd_mode) ? 0 : clkpll_tmp; + + assign orig_rst_in = rst_input; + +always @(posedge clkpll or posedge orig_rst_in) + if (orig_rst_in) + rst_in1 <= 1; + else + rst_in1 <= orig_rst_in; + + assign rst_in = (rst_in1 || rst_unlock); + + always @(posedge pll_unlock) + if (rst_on_loss ) begin + rst_unlock <= 1'b1; + rst_unlock <= #10000 1'b0; + end + +always @(rst_input ) + if (rst_input==1) + rst_edge = $time; + else if (rst_input==0 && rst_edge > 1) begin + rst_ht = $time - rst_edge; + if (rst_ht < 10000) + $display("Input Error : RST on instance %m at time %t must be asserted at least for 10 ns.", $time); + end + +// +// DRP port read and write +// + + assign do_out = dr_sram[daddr_lat]; + +always @(posedge dclk_in or posedge gsr_in) + if (gsr_in == 1) begin + drp_lock <= 0; + drp_lock1 <= 0; + drdy_out <= 0; + end + else begin + if (den_in == 1) begin + valid_daddr = addr_is_valid(daddr_in); + if (drp_lock == 1) begin + $display(" Warning : DEN is high at PLL_ADV instance %m at time %t. Need wait for DRDY signal before next read/write operation through DRP. ", $time); + end + else begin + drp_lock <= 1; + daddr_lat <= daddr_in; + end + + if (sim_d == 1) begin + if (valid_daddr && ( daddr_in >= 5'b00101 && daddr_in <= 5'b11000)) + begin + end + else begin + $display(" Warning : Address DADDR=%b is unsupported at PLL_ADV instance %m at time %t. ", DADDR, $time); + end + end + else begin + if (valid_daddr && ( daddr_in == 5'b00110 || daddr_in == 5'b00001 || daddr_in == 5'b00000 || + daddr_in == 5'b01010 || daddr_in == 5'b01001 || + (daddr_in >= 5'b01100 && daddr_in <= 5'b11100 && daddr_in != 5'b10000 && + daddr_in != 5'b10001 && daddr_in != 5'b11000 ))) begin + end + else begin + $display(" Warning : Address DADDR=%b is unsupported at PLL_ADV instance %m at time %t. ", DADDR, $time); + end + + end + + + if (dwe_in == 1) begin // write process + if (rst_input == 1) begin + + dr_sram[daddr_in] <= di_in; + + if (sim_d == 1) begin + if (daddr_in == 5'b00101) begin + clkout0_dly[5] = di_in[15]; + clkout0_dly[4] = di_in[13]; + clkout0_dly[2] = di_in[11]; + clkout0_dly[3] = di_in[10]; + clkout0_dly[1] = di_in[9]; + clkout0_dly[0] = di_in[8]; + end + if (daddr_in == 5'b00110) begin + clk1_lt[4] = di_in[15]; + clk1_lt[5] = di_in[14]; + clk1_lt[3] = di_in[13]; + clk1_nocnt = di_in[12]; + clk1_lt[1] = di_in[11]; + clk1_lt[2] = di_in[10]; + clkout1_dly[5] = di_in[9]; + clkout1_dly[3] = di_in[7]; + clkout1_dly[2] = di_in[6]; + clkout1_dly[0] = di_in[5]; + clkout1_dly[1] = di_in[4]; + clk0_edge = di_in[2]; + end + if (daddr_in == 5'b00111) begin + clk1_ht[5] = di_in[12]; + clk1_ht[3] = di_in[11]; + clk1_ht[4] = di_in[10]; + clk1_ht[2:0] = di_in[9:7]; + clk1pm_sel[0] = di_in[6]; + clk1_edge = di_in[4]; + clk1pm_sel[1] = di_in[1]; + clk1pm_sel[2] = di_in[0]; + end + if (daddr_in == 5'b01000) begin + clk2pm_sel[2] = di_in[15]; + clk2_lt[5] = di_in[13]; + clk2pm_sel[1] = di_in[12]; + clk2_nocnt = di_in[11]; + clk2_lt[4] = di_in[10]; + clk2_lt[3] = di_in[9]; + clk2_lt[2] = di_in[8]; + clk2_lt[0] = di_in[7]; + clkout2_dly[5] = di_in[6]; + clkout2_dly[3] = di_in[5]; + clkout2_dly[4] = di_in[4]; + clkout2_dly[1] = di_in[3]; + clkout2_dly[2] = di_in[2]; + clkout2_dly[0] = di_in[1]; + end + if (daddr_in == 5'b01001) begin + clkout3_dly[0] = di_in[15]; + clkout3_dly[1] = di_in[14]; + clk0pm_sel[1] = di_in[13]; + clk0pm_sel[2] = di_in[12]; + clk2_ht[4] = di_in[9]; + clk2_ht[3] = di_in[7]; + clk2_ht[2] = di_in[6]; + clk2_ht[0] = di_in[5]; + clk2_ht[1] = di_in[4]; + clk2_edge = di_in[3]; + clk2pm_sel[0] = di_in[2]; + end + if (daddr_in == 5'b01010) begin + clk3_edge = di_in[14]; + clk3pm_sel[1] = di_in[11]; + clk3pm_sel[2] = di_in[10]; + clk3_lt[5] = di_in[9]; + clk3_lt[4] = di_in[8]; + clk3_nocnt = di_in[7]; + clk3_lt[2] = di_in[6]; + clk3_lt[0] = di_in[5]; + clk3_lt[1] = di_in[4]; + clkout3_dly[4] = di_in[3]; + clkout3_dly[5] = di_in[2]; + clkout3_dly[3] = di_in[1]; + end + if (daddr_in == 5'b01011) begin + clk0_lt[5] = di_in[15]; + clkout4_dly[5] = di_in[14]; + clkout4_dly[0] = di_in[13]; + clkout4_dly[3] = di_in[12]; + clkout4_dly[1] = di_in[11]; + clkout4_dly[2] = di_in[10]; + clk0_lt[4] = di_in[9]; + clk3_ht[5:3] = di_in[7:5]; + clk3_ht[1] = di_in[3]; + clk3_ht[2] = di_in[2]; + clk3pm_sel[0] = di_in[1]; + clk3_ht[0] = di_in[0]; + end + if (daddr_in == 5'b01100) begin + clk4_ht[1] = di_in[15]; + clk4_ht[2] = di_in[14]; + clk4pm_sel[0] = di_in[13]; + clk4_ht[0] = di_in[12]; + clk4_edge = di_in[10]; + clk4pm_sel[2] = di_in[7]; + clk4pm_sel[1] = di_in[6]; + clk4_lt[4] = di_in[5]; + clk4_lt[5] = di_in[4]; + clk4_lt[3] = di_in[3]; + clk4_nocnt = di_in[2]; + clk4_lt[1] = di_in[1]; + clk4_lt[2] = di_in[0]; + end + if (daddr_in == 5'b01101) begin + clk5_lt[2] = di_in[15]; + clk5_lt[3] = di_in[14]; + clk5_lt[0] = di_in[13]; + clk5_lt[1] = di_in[12]; + clkout5_dly[4] = di_in[11]; + clkout5_dly[5] = di_in[10]; + clkout5_dly[3] = di_in[9]; + clkout5_dly[2] = di_in[8]; + clkout5_dly[1] = di_in[7]; + clk0_lt[3] = di_in[6]; + clk0_lt[0] = di_in[5]; + clk0_lt[2] = di_in[4]; + clk4_ht[5] = di_in[2]; + clk4_ht[3] = di_in[1]; + clk4_ht[4] = di_in[0]; + end + if (daddr_in == 5'b01110) begin + clk5_ht[4] = di_in[15]; + clk5_ht[5] = di_in[14]; + clk5_ht[2] = di_in[13]; + clk5_ht[3] = di_in[12]; + clk5_ht[0] = di_in[11]; + clk5_ht[1] = di_in[10]; + clk5pm_sel[0] = di_in[9]; + clk5_edge = di_in[8]; + clk5pm_sel[2] = di_in[5]; + clk5_lt[5] = di_in[3]; + clk5pm_sel[1] = di_in[2]; + clk5_nocnt = di_in[1]; + clk5_lt[4] = di_in[0]; + end + if (daddr_in == 5'b01111) begin + clkfbm1_lt[4] = di_in[15]; + clkfbm1_lt[5] = di_in[14]; + clkfbm1_lt[3] = di_in[13]; + clkfbm1_nocnt = di_in[12]; + clkfbm1_lt[1] = di_in[11]; + clkfbm1_lt[2] = di_in[10]; + clkfbm1_lt[0] = di_in[9]; + clkfbm1_dly[5] = di_in[8]; + clkfbm1_dly[4] = di_in[7]; + clkfbm1_dly[3] = di_in[6]; + clkfbm1_dly[1] = di_in[5]; + clkfbm1_dly[2] = di_in[4]; + clk0_nocnt = di_in[3]; + clk0_lt[1] = di_in[2]; + end + if (daddr_in == 5'b10000) begin + clk0_ht[3] = di_in[14]; + clk0_ht[5] = di_in[13]; + clk0_ht[4] = di_in[12]; + clkfbm1_ht[4] = di_in[11]; + clkfbm1_ht[5] = di_in[10]; + clkfbm1_ht[3:0] = di_in[9:6]; + clkfbm1_edge = di_in[5]; + clkfbm1pm_sel[0] = di_in[4]; + clkfbm1pm_sel[1] = di_in[1]; + clkfbm1pm_sel[2] = di_in[0]; + end + if (daddr_in == 5'b10001) begin + clkfbm2_lt[0] = di_in[15]; + clkfbm2_dly[3] = di_in[14]; + clkfbm2_ht[2] = di_in[13]; + clkfbm2_ht[1] = di_in[12]; + clkfbm2_lt[1] = di_in[11]; + clkfbm2_ht[4] = di_in[10]; + clk3_lt[3] = di_in[9]; + clkout3_dly[2] = di_in[8]; + clk2_ht[5] = di_in[7]; + clk2_lt[1] = di_in[6]; + clkout1_dly[4] = di_in[5]; + clk1_lt[0] = di_in[4]; + clk0_ht[0] = di_in[3]; + clk0pm_sel[0] = di_in[2]; + clk0_ht[2] = di_in[1]; + clk0_ht[1] = di_in[0]; + end + if (daddr_in == 5'b10010) begin + clkout5_dly[0] = di_in[11]; + clkfbm1_dly[0] = di_in[10]; + clk4_lt[0] = di_in[9]; + clkout4_dly[4] = di_in[8]; + clkfbm2_nocnt = di_in[3]; + clkfbm2_dly[2] = di_in[1]; + clkfbm2_lt[4] = di_in[0]; + end + if (daddr_in == 5'b10011) begin + clkind_ht[5] = di_in[15]; + clkfbm2_ht[3] = di_in[14]; + clkind_ht[4] = di_in[13]; + clkind_ht[1] = di_in[11]; + clkind_ht[2] = di_in[10]; + clkind_lt[0] = di_in[9]; + clkind_lt[5] = di_in[7]; + clkind_lt[2] = di_in[6]; + clkind_edge = di_in[4]; + if (clkind_nocnt == 1) + clkind_div = 8'b00000001; + else if (clkind_ht[5:0] == 6'b0 && clkind_lt[5:0] == 6'b0) + clkind_div = 8'b10000000; + else if (clkind_lt[5:0] == 6'b0) + clkind_div = 64 + clkind_ht; + else if (clkind_ht[5:0] == 6'b0) + clkind_div = 64 + clkind_lt; + else + clkind_div = clkind_ht + clkind_lt; + + end + if (daddr_in == 5'b10100) begin + pll_cpres[0] = di_in[8]; + pll_cpres[1] = di_in[7]; + clkfbm2_dly[1] = di_in[6]; + clkfbm2_lt[3] = di_in[5]; + clkfbm2_ht[0] = di_in[4]; + clkfbm2_dly[4] = di_in[3]; + clkfbm2_dly[0] = di_in[2]; + clkfbm2_dly[5] = di_in[1]; + clkfbm2_ht[5] = di_in[0]; + end + if (daddr_in == 5'b10101) begin + clkind_nocnt = di_in[14]; + clkfbm2_edge = di_in[6]; + clkfbm2_lt[5] = di_in[5]; + clkfbm2_lt[2] = di_in[4]; + if (clkind_nocnt == 1) + clkind_div = 8'b00000001; + else if (clkind_ht[5:0] == 6'b0 && clkind_lt[5:0] == 6'b0) + clkind_div = 8'b10000000; + else if (clkind_lt[5:0] == 6'b0) + clkind_div = 64 + clkind_ht; + else if (clkind_ht[5:0] == 6'b0) + clkind_div = 64 + clkind_lt; + else + clkind_div = clkind_ht + clkind_lt; + + end + if (daddr_in == 5'b10110) begin + pll_lfhf[0] = di_in[11]; + clkind_ht[3] = di_in[8]; + clkind_lt[1] = di_in[7]; + clkind_ht[0] = di_in[5]; + clkind_lt[3] = di_in[3]; + clkind_lt[4] = di_in[1]; + if (clkind_nocnt == 1) + clkind_div = 8'b00000001; + else if (clkind_ht[5:0] == 6'b0 && clkind_lt[5:0] == 6'b0) + clkind_div = 8'b10000000; + else if (clkind_lt[5:0] == 6'b0) + clkind_div = 64 + clkind_ht; + else if (clkind_ht[5:0] == 6'b0) + clkind_div = 64 + clkind_lt; + else + clkind_div = clkind_ht + clkind_lt; + + end + if (daddr_in == 5'b10111) begin + pll_lfhf[1] = di_in[9]; + end + if (daddr_in == 5'b11000) begin + pll_res[0] = di_in[15]; + pll_res[1] = di_in[14]; + pll_cp[0] = di_in[13]; + pll_cp[2] = di_in[11]; + pll_cp[1] = di_in[10]; + pll_cp[3] = di_in[9]; + pll_res[3] = di_in[8]; + pll_res[2] = di_in[7]; + end + end + else begin + + if (daddr_in == 5'b11100) + clkout_delay_para_drp (clkout0_dly, clk0_nocnt, clk0_edge, di_in, daddr_in); + + if (daddr_in == 5'b11011) + clkout_hl_para_drp (clk0_lt, clk0_ht, clk0pm_sel, di_in, daddr_in); + + if (daddr_in == 5'b11010) + clkout_delay_para_drp (clkout1_dly, clk1_nocnt, clk1_edge, di_in, daddr_in); + + if (daddr_in == 5'b11001) + clkout_hl_para_drp (clk1_lt, clk1_ht, clk1pm_sel, di_in, daddr_in); + + if (daddr_in == 5'b10111) + clkout_delay_para_drp (clkout2_dly, clk2_nocnt, clk2_edge, di_in, daddr_in); + + if (daddr_in == 5'b10110) + clkout_hl_para_drp (clk2_lt, clk2_ht, clk2pm_sel, di_in, daddr_in); + + if (daddr_in == 5'b10101) + clkout_delay_para_drp (clkout3_dly, clk3_nocnt, clk3_edge, di_in, daddr_in); + + if (daddr_in == 5'b10100) + clkout_hl_para_drp (clk3_lt, clk3_ht, clk3pm_sel, di_in, daddr_in); + + if (daddr_in == 5'b10011) + clkout_delay_para_drp (clkout4_dly, clk4_nocnt, clk4_edge, di_in, daddr_in); + + if (daddr_in == 5'b10010) + clkout_hl_para_drp (clk4_lt, clk4_ht, clk4pm_sel, di_in, daddr_in); + + if (daddr_in == 5'b01111) + clkout_delay_para_drp (clkout5_dly, clk5_nocnt, clk5_edge, di_in, daddr_in); + + if (daddr_in == 5'b01110) + clkout_hl_para_drp (clk5_lt, clk5_ht, clk5pm_sel, di_in, daddr_in); + + if (daddr_in == 5'b01101) + clkout_delay_para_drp (clkfbm1_dly, clkfbm1_nocnt, clkfbm1_edge, di_in, daddr_in); + + if (daddr_in == 5'b01100) + clkout_hl_para_drp (clkfbm1_lt, clkfbm1_ht, clkfbm1pm_sel, di_in, daddr_in); + + if (daddr_in == 5'b01010) + clkout_delay_para_drp (clkfbm2_dly, clkfbm2_nocnt, clkfbm2_edge, di_in, daddr_in); + + if (daddr_in == 5'b01001) + clkout_hl_para_drp (clkfbm2_lt, clkfbm2_ht, clkfbm2pm_sel, di_in, daddr_in); + + if (daddr_in == 5'b00110) begin + clkind_lti = {2'b00, di_in[5:0]}; + clkind_hti = {2'b00, di_in[11:6]}; + clkind_lt <= clkind_lti; + clkind_ht <= clkind_hti; + clkind_nocnt <= di_in[12]; + clkind_edge <= di_in[13]; + if (di_in[12] == 1) + clkind_divi = 8'b00000001; + else if (di_in[5:0] == 6'b0 && di_in[11:6] == 6'b0) + clkind_divi = 8'b10000000; + else if (di_in[5:0] == 6'b0) + clkind_divi = 64 + clkind_hti; + else if (di_in[11:6] == 6'b0) + clkind_divi = 64 + clkind_lti; + else + clkind_divi = clkind_hti + clkind_lti; + + clkind_div <= clkind_divi; + if (clkind_divi > 52 || (clkind_divi < 1 && clkind_nocnti == 0)) + $display(" Input Error : DI at Address DADDR=%b is %h at PLL_ADV instance %m at time %t. The sum of DI[11:6] and DI[5:0] is %d and over the range of 1 to 52.", daddr_in, di_in, clkind_divi, $time); + end + end + end //rst_input + else begin + $display(" Error : RST is low at PLL_ADV instance %m at time %t. RST need to be high when change PLL_ADV paramters through DRP. ", $time); + end + + end //DWE + + end //DEN + if ( drp_lock == 1) begin + drp_lock <= 0; + drp_lock1 <= 1; + end + if (drp_lock1 == 1) begin + drp_lock1 <= 0; + drdy_out <= 1; + end + if (drdy_out == 1) + drdy_out <= 0; +end + +function addr_is_valid; +input [6:0] daddr_funcin; +begin + addr_is_valid = 1; + for (i=0; i<=6; i=i+1) + if ( daddr_funcin[i] != 0 && daddr_funcin[i] != 1) + addr_is_valid = 0; +end +endfunction + + +// end process drp; + + +// +// determine clock period +// + + always @(posedge clkpll or posedge rst_in) + if (rst_in) + begin + clkin_period[0] <= period_vco_target; + clkin_period[1] <= period_vco_target; + clkin_period[2] <= period_vco_target; + clkin_period[3] <= period_vco_target; + clkin_period[4] <= period_vco_target; + clkin_jit <= 0; + clkin_lock_cnt <= 0; + pll_locked_tm <= 0; + lock_period <= 0; + pll_locked_tmp1 <= 0; + clkout_en0_tmp <= 0; + unlock_recover <= 0; + clkin_edge <= 0; + end + else begin + clkin_edge <= $time; + clkin_period[4] <= clkin_period[3]; + clkin_period[3] <= clkin_period[2]; + clkin_period[2] <= clkin_period[1]; + clkin_period[1] <= clkin_period[0]; + if (clkin_edge != 0 && clkin_stopped == 0) + clkin_period[0] <= $time - clkin_edge; + + if (pll_unlock == 0) + clkin_jit <= $time - clkin_edge - clkin_period[0]; + else + clkin_jit <= 0; + + if ( (clkin_lock_cnt < lock_cnt_max) && fb_delay_found && pll_unlock == 0) + clkin_lock_cnt <= clkin_lock_cnt + 1; + else if (pll_unlock == 1 && rst_on_loss ==0 && pll_locked_tmp1 ==1 ) begin + clkin_lock_cnt <= locked_en_time; + unlock_recover <= 1; + end + + if ( clkin_lock_cnt >= PLL_LOCK_TIME && pll_unlock == 0) + pll_locked_tm <= 1; + + if ( clkin_lock_cnt == 6 ) + lock_period <= 1; + + if (clkin_lock_cnt >= clkout_en_time) begin + clkout_en0_tmp <= 1; + end + + if (clkin_lock_cnt >= locked_en_time) + pll_locked_tmp1 <= 1; + + if (unlock_recover ==1 && clkin_lock_cnt >= lock_cnt_max) + unlock_recover <= 0; + end + + always @(clkout_en0_tmp) + if (clkout_en0_tmp==0) + clkout_en0 = 0; + else + @(negedge clkpll) + clkout_en0 <= #(clkin_period[0]/2) clkout_en0_tmp; + + always @(clkout_en0) + clkout_en <= #(clkvco_delay) clkout_en0; + + always @(pll_locked_tmp1 ) + if (pll_locked_tmp1==0) + pll_locked_tmp2 = pll_locked_tmp1; + else begin + pll_locked_tmp2 <= #pll_locked_delay pll_locked_tmp1; + end + + + always @(rst_in) + if (rst_in) begin + assign pll_locked_tmp2 = 0; + assign clkout_en0 = 0; + assign clkout_en = 0; + end + else begin + deassign pll_locked_tmp2; + deassign clkout_en0; + deassign clkout_en; + end + + assign locked_out = (pll_locked_tm && pll_locked_tmp2 && ~pll_unlock && !unlock_recover) ? 1 : 0; + + + always @(clkin_period[0] or clkin_period[1] or clkin_period[2] or + clkin_period[3] or clkin_period[4] or period_avg) + if ( clkin_period[0] != period_avg) + period_avg = (clkin_period[0] + clkin_period[1] + clkin_period[2] + + clkin_period[3] + clkin_period[4])/5; + + always @(period_avg or clkind_div or clkfbm_div) begin + md_product = clkind_div * clkfbm_div; + m_product = clkfbm_div; + m_product2 = clkfbm_div / 2; + period_fb = period_avg * clkind_div; + period_vco = period_fb / clkfbm_div; + period_vco_rm = period_fb % clkfbm_div; + clkin_lost_val = (period_avg * 2) / 500; + clkfb_lost_val = (period_fb * 2) / 500; + if (period_vco_rm > 1) begin + if (period_vco_rm > m_product2) begin + period_vco_cmp_cnt = m_product / (m_product - period_vco_rm) - 1; + period_vco_cmp_flag = 2; + end + else begin + period_vco_cmp_cnt = (m_product / period_vco_rm) - 1; + period_vco_cmp_flag = 1; + end + end + else begin + period_vco_cmp_cnt = 0; + period_vco_cmp_flag = 0; + end + period_vco_half = period_vco /2; + period_vco_half_rm = period_vco - period_vco_half; + period_vco_half_rm1 = period_vco_half_rm + 1; + period_vco_half_rm2 = period_vco_half_rm - 1; + period_vco_half1 = period_vco - period_vco_half + 1; + pll_locked_delay = period_fb * clkfbm_div; + clkin_dly_t = period_avg * (clkind_div + 1.25); + clkfb_dly_t = period_fb * 2.25 ; + period_vco1 = period_vco / 8; + period_vco2 = period_vco / 4; + period_vco3 = period_vco * 3/ 8; + period_vco4 = period_vco / 2; + period_vco5 = period_vco * 5 / 8; + period_vco6 = period_vco *3 / 4; + period_vco7 = period_vco * 7 / 8; + end + + assign clkvco_lk_rst = ( rst_in == 1 || pll_unlock == 1 || pll_locked_tm == 0) ? 1 : 0; + + always @(clkvco_lk_rst) + if (clkvco_lk_rst) + assign clkvco_lk = 0; + else + deassign clkvco_lk; + + + always @(posedge clkpll) + if (pll_locked_tm ==1) begin + clkvco_lk <= 1; + clkvco_rm_cnt = 0; + if ( period_vco_cmp_flag == 1) + for (i1=1; i1 < m_product; i1=i1+1) begin + #(period_vco_half) clkvco_lk <= 0; + if ( clkvco_rm_cnt == 1) + #(period_vco_half_rm1) clkvco_lk <= 1; + else + #(period_vco_half_rm) clkvco_lk <= 1; + + if ( clkvco_rm_cnt == period_vco_cmp_cnt) + clkvco_rm_cnt <= 0; + else + clkvco_rm_cnt <= clkvco_rm_cnt + 1; + end + else if ( period_vco_cmp_flag == 2) + for (i1=1; i1 < m_product; i1=i1+1) begin + #(period_vco_half) clkvco_lk <= 0; + if ( clkvco_rm_cnt == 1) + #(period_vco_half_rm) clkvco_lk <= 1; + else + #(period_vco_half_rm1) clkvco_lk <= 1; + + if ( clkvco_rm_cnt == period_vco_cmp_cnt) + clkvco_rm_cnt <= 0; + else + clkvco_rm_cnt <= clkvco_rm_cnt + 1; + end + else + for (i1=1; i1 < m_product; i1=i1+1) begin + #(period_vco_half) clkvco_lk <= 0; + #(period_vco_half_rm) clkvco_lk <= 1; + end + + #(period_vco_half) clkvco_lk <= 0; + + if (clkpll == 1) begin + for (i1=1; i1 < m_product; i1=i1+1) begin + #(period_vco_half) clkvco_lk <= 0; + #(period_vco_half_rm) clkvco_lk <= 1; + end + + #(period_vco_half) clkvco_lk <= 0; + end + + end + + +// always @(fb_delay or period_vco or clkfbm1_dly or clkfbm1pm_rl) + always @(fb_delay or period_vco or clkfbm_dly or clkfbm1pm_rl) + if (period_vco > 0) begin +// val_tmp = period_vco * md_product; + val_tmp = period_avg * DIVCLK_DIVIDE; +// if (clkfb_src ==1) +// fbm1_comp_delay = period_vco * clkfbm_dly; +// else + fbm1_comp_delay = period_vco *(clkfbm_dly + clkfbm1pm_rl ); + dly_tmp = fb_delay + fbm1_comp_delay; + if ( dly_tmp < val_tmp) + clkvco_delay = val_tmp - dly_tmp; + else + clkvco_delay = val_tmp - dly_tmp % val_tmp ; + end + + always @(clkfbmpm_sel) + case (clkfbmpm_sel) + 3'b000 : clkfbm1pm_rl = 0.0; + 3'b001 : clkfbm1pm_rl = 0.125; + 3'b010 : clkfbm1pm_rl = 0.25; + 3'b011 : clkfbm1pm_rl = 0.375; + 3'b100 : clkfbm1pm_rl = 0.50; + 3'b101 : clkfbm1pm_rl = 0.625; + 3'b110 : clkfbm1pm_rl = 0.75; + 3'b111 : clkfbm1pm_rl = 0.875; + endcase + + always @(clkvco_free ) + if (pmcd_mode != 1 && pll_locked_tm == 0) + clkvco_free <= #period_vco_target_half ~clkvco_free; + + always @(clkvco_lk or clkvco_free or pll_locked_tm) + if ( pll_locked_tm) + clkvco <= #clkvco_delay clkvco_lk; + else + clkvco <= #clkvco_delay clkvco_free; + + always @(clk0_ht or clk0_lt or clk0_nocnt or init_trig or clk0_edge) + clkout_pm_cal(clk0_ht1, clk0_div, clk0_div1, clk0_ht, clk0_lt, clk0_nocnt, clk0_edge); + + always @(clk1_ht or clk1_lt or clk1_nocnt or init_trig or clk1_edge) + clkout_pm_cal(clk1_ht1, clk1_div, clk1_div1, clk1_ht, clk1_lt, clk1_nocnt, clk1_edge); + + always @(clk2_ht or clk2_lt or clk2_nocnt or init_trig or clk2_edge) + clkout_pm_cal(clk2_ht1, clk2_div, clk2_div1, clk2_ht, clk2_lt, clk2_nocnt, clk2_edge); + + always @(clk3_ht or clk3_lt or clk3_nocnt or init_trig or clk3_edge) + clkout_pm_cal(clk3_ht1, clk3_div, clk3_div1, clk3_ht, clk3_lt, clk3_nocnt, clk3_edge); + + always @(clk4_ht or clk4_lt or clk4_nocnt or init_trig or clk4_edge) + clkout_pm_cal(clk4_ht1, clk4_div, clk4_div1, clk4_ht, clk4_lt, clk4_nocnt, clk4_edge); + + always @(clk5_ht or clk5_lt or clk5_nocnt or init_trig or clk5_edge) + clkout_pm_cal(clk5_ht1, clk5_div, clk5_div1, clk5_ht, clk5_lt, clk5_nocnt, clk5_edge); + + always @(clkfbm1_ht or clkfbm1_lt or clkfbm1_nocnt or init_trig or clkfbm1_edge) + clkout_pm_cal(clkfbm1_ht1, clkfbm1_div, clkfbm1_div1, clkfbm1_ht, clkfbm1_lt, clkfbm1_nocnt, clkfbm1_edge); + + always @(clkfbm2_ht or clkfbm2_lt or clkfbm2_nocnt or init_trig or clkfbm2_edge) + clkout_pm_cal(clkfbm2_ht1, clkfbm2_div, clkfbm2_div1, clkfbm2_ht, clkfbm2_lt, clkfbm2_nocnt, clkfbm2_edge); + + always @( clkfbm1_div or clkfbm2_div or clk0_div or init_trig) + if (clkfb_src ==1) + clkfbm_div = clkfbm2_div * clk0_div; + else + clkfbm_div = clkfbm1_div; + + always @( clkfbm1_dly or clkout0_dly or init_trig) + if (clkfb_src ==1) + clkfbm_dly = clkout0_dly; + else + clkfbm_dly = clkfbm1_dly; + + + always @( clkfbm1pm_sel or clk0pm_sel or init_trig) + if (clkfb_src ==1) + clkfbmpm_sel = clk0pm_sel; + else + clkfbmpm_sel = clkfbm1pm_sel; + + always @(rst_in) + if (rst_in) + assign clkout_mux = 8'b0; + else + deassign clkout_mux; + + always @(clkvco or clkout_en ) + if (clkout_en) begin + clkout_mux[0] <= clkvco; + clkout_mux[1] <= #(period_vco1) clkvco; + clkout_mux[2] <= #(period_vco2) clkvco; + clkout_mux[3] <= #(period_vco3) clkvco; + clkout_mux[4] <= #(period_vco4) clkvco; + clkout_mux[5] <= #(period_vco5) clkvco; + clkout_mux[6] <= #(period_vco6) clkvco; + clkout_mux[7] <= #(period_vco7) clkvco; + end + + assign clk0in = clkout_mux[clk0pm_sel]; + assign clk1in = clkout_mux[clk1pm_sel]; + assign clk2in = clkout_mux[clk2pm_sel]; + assign clk3in = clkout_mux[clk3pm_sel]; + assign clk4in = clkout_mux[clk4pm_sel]; + assign clk5in = clkout_mux[clk5pm_sel]; + assign clkfbm1in = clkout_mux[clkfbm1pm_sel]; + + assign clk0ps_en = (clk0_dly_cnt == clkout0_dly) ? clkout_en : 0; + assign clk1ps_en = (clk1_dly_cnt == clkout1_dly) ? clkout_en : 0; + assign clk2ps_en = (clk2_dly_cnt == clkout2_dly) ? clkout_en : 0; + assign clk3ps_en = (clk3_dly_cnt == clkout3_dly) ? clkout_en : 0; + assign clk4ps_en = (clk4_dly_cnt == clkout4_dly) ? clkout_en : 0; + assign clk5ps_en = (clk5_dly_cnt == clkout5_dly) ? clkout_en : 0; + assign clkfbm1ps_en = (clkfbm1_dly_cnt == clkfbm1_dly) ? clkout_en : 0; + + always @(negedge clk0in or posedge rst_in) + if (rst_in) + clk0_dly_cnt <= 6'b0; + else + if (clk0_dly_cnt < clkout0_dly && clkout_en ==1) + clk0_dly_cnt <= clk0_dly_cnt + 1; + + always @(negedge clk1in or posedge rst_in) + if (rst_in) + clk1_dly_cnt <= 6'b0; + else + if (clk1_dly_cnt < clkout1_dly && clkout_en ==1) + clk1_dly_cnt <= clk1_dly_cnt + 1; + + always @(negedge clk2in or posedge rst_in) + if (rst_in) + clk2_dly_cnt <= 6'b0; + else + if (clk2_dly_cnt < clkout2_dly && clkout_en ==1) + clk2_dly_cnt <= clk2_dly_cnt + 1; + + always @(negedge clk3in or posedge rst_in) + if (rst_in) + clk3_dly_cnt <= 6'b0; + else + if (clk3_dly_cnt < clkout3_dly && clkout_en ==1) + clk3_dly_cnt <= clk3_dly_cnt + 1; + + always @(negedge clk4in or posedge rst_in) + if (rst_in) + clk4_dly_cnt <= 6'b0; + else + if (clk4_dly_cnt < clkout4_dly && clkout_en ==1) + clk4_dly_cnt <= clk4_dly_cnt + 1; + + always @(negedge clk5in or posedge rst_in) + if (rst_in) + clk5_dly_cnt <= 6'b0; + else + if (clk5_dly_cnt < clkout5_dly && clkout_en ==1) + clk5_dly_cnt <= clk5_dly_cnt + 1; + + always @(negedge clkfbm1in or posedge rst_in) + if (rst_in) + clkfbm1_dly_cnt <= 6'b0; + else + if (clkfbm1_dly_cnt < clkfbm1_dly && clkout_en ==1) + clkfbm1_dly_cnt <= clkfbm1_dly_cnt + 1; + + always @(posedge clk0in or negedge clk0in or posedge rst_in) + if (rst_in) begin + clk0_cnt <= 8'b0; + clk0_out <= 0; + end + else if (clk0ps_en) begin + if (clk0_cnt < clk0_div1) + clk0_cnt <= clk0_cnt + 1; + else + clk0_cnt <= 8'b0; + + if (clk0_cnt < clk0_ht1) + clk0_out <= 1; + else + clk0_out <= 0; + end + else begin + clk0_cnt <= 8'b0; + clk0_out <= 0; + end + + always @(posedge clk1in or negedge clk1in or posedge rst_in) + if (rst_in) begin + clk1_cnt <= 8'b0; + clk1_out <= 0; + end + else if (clk1ps_en) begin + if (clk1_cnt < clk1_div1) + clk1_cnt <= clk1_cnt + 1; + else + clk1_cnt <= 8'b0; + + if (clk1_cnt < clk1_ht1) + clk1_out <= 1; + else + clk1_out <= 0; + end + else begin + clk1_cnt <= 8'b0; + clk1_out <= 0; + end + + always @(posedge clk2in or negedge clk2in or posedge rst_in) + if (rst_in) begin + clk2_cnt <= 8'b0; + clk2_out <= 0; + end + else if (clk2ps_en) begin + if (clk2_cnt < clk2_div1) + clk2_cnt <= clk2_cnt + 1; + else + clk2_cnt <= 8'b0; + + if (clk2_cnt < clk2_ht1) + clk2_out <= 1; + else + clk2_out <= 0; + end + else begin + clk2_cnt <= 8'b0; + clk2_out <= 0; + end + + always @(posedge clk3in or negedge clk3in or posedge rst_in) + if (rst_in) begin + clk3_cnt <= 8'b0; + clk3_out <= 0; + end + else if (clk3ps_en) begin + if (clk3_cnt < clk3_div1) + clk3_cnt <= clk3_cnt + 1; + else + clk3_cnt <= 8'b0; + + if (clk3_cnt < clk3_ht1) + clk3_out <= 1; + else + clk3_out <= 0; + end + else begin + clk3_cnt <= 8'b0; + clk3_out <= 0; + end + + + always @(posedge clk4in or negedge clk4in or posedge rst_in) + if (rst_in) begin + clk4_cnt <= 8'b0; + clk4_out <= 0; + end + else if (clk4ps_en) begin + if (clk4_cnt < clk4_div1) + clk4_cnt <= clk4_cnt + 1; + else + clk4_cnt <= 8'b0; + + if (clk4_cnt < clk4_ht1) + clk4_out <= 1; + else + clk4_out <= 0; + end + else begin + clk4_cnt <= 8'b0; + clk4_out <= 0; + end + + + always @(posedge clk5in or negedge clk5in or posedge rst_in) + if (rst_in) begin + clk5_cnt <= 8'b0; + clk5_out <= 0; + end + else if (clk5ps_en) begin + if (clk5_cnt < clk5_div1) + clk5_cnt <= clk5_cnt + 1; + else + clk5_cnt <= 8'b0; + + if (clk5_cnt < clk5_ht1) + clk5_out <= 1; + else + clk5_out <= 0; + end + else begin + clk5_cnt <= 8'b0; + clk5_out <= 0; + end + + + always @(posedge clkfbm1in or negedge clkfbm1in or posedge rst_in) + if (rst_in) begin + clkfbm1_cnt <= 8'b0; + clkfbm1_out <= 0; + end + else if (clkfbm1ps_en) begin + if (clkfbm1_cnt < clkfbm1_div1) + clkfbm1_cnt <= clkfbm1_cnt + 1; + else + clkfbm1_cnt <= 8'b0; + + if (clkfbm1_cnt < clkfbm1_ht1) + clkfbm1_out <= 1; + else + clkfbm1_out <= 0; + end + else begin + clkfbm1_cnt <= 8'b0; + clkfbm1_out <= 0; + end + + + + always @(clk0_out or clkfb_tst or fb_delay_found) + if (fb_delay_found == 1) + clkout0_out = clk0_out; + else + clkout0_out = clkfb_tst; + + always @(clk1_out or clkfb_tst or fb_delay_found) + if (fb_delay_found == 1) + clkout1_out = clk1_out; + else + clkout1_out = clkfb_tst; + + always @(clk2_out or clkfb_tst or fb_delay_found) + if (fb_delay_found == 1) + clkout2_out = clk2_out; + else + clkout2_out = clkfb_tst; + + always @(clk3_out or clkfb_tst or fb_delay_found) + if (fb_delay_found == 1) + clkout3_out = clk3_out; + else + clkout3_out = clkfb_tst; + + always @(clk4_out or clkfb_tst or fb_delay_found) + if (fb_delay_found == 1) + clkout4_out = clk4_out; + else + clkout4_out = clkfb_tst; + + always @(clk5_out or clkfb_tst or fb_delay_found) + if (fb_delay_found == 1) + clkout5_out = clk5_out; + else + clkout5_out = clkfb_tst; + + always @(clkfbm1_out or clkfb_tst or fb_delay_found) + if (fb_delay_found == 1) + clkfb_out = clkfbm1_out; + else + clkfb_out = clkfb_tst; + +// +// determine feedback delay +// + +//always @(rst_in1) +// if (rst_in1) +// assign clkfb_tst = 0; +// else +// deassign clkfb_tst; + +always @(posedge clkpll ) + if (fb_delay_found_tmp == 0 && pwron_int == 0 && rst_in1 == 0) begin + clkfb_tst <= 1'b1; + end + else + clkfb_tst <= 1'b0; + + +always @( posedge clkfb_tst or posedge rst_in1 ) + if (rst_in1) + delay_edge <= 0; + else + delay_edge <= $time; + +always @(posedge clkfb_in or posedge rst_in1 ) + if (rst_in1) begin + fb_delay <= 0; + fb_delay_found_tmp <= 0; + end + else + if (fb_delay_found_tmp ==0 ) begin + if ( delay_edge != 0) + fb_delay <= ($time - delay_edge); + else + fb_delay <= 0; + fb_delay_found_tmp <= 1; + end + +always @(rst_in1) + if (rst_in1) + assign fb_delay_found = 0; + else + deassign fb_delay_found; + +always @(fb_delay_found_tmp or clkvco_delay ) + if (clkvco_delay == 0) + fb_delay_found <= #1000 fb_delay_found_tmp; + else + fb_delay_found <= #(clkvco_delay) fb_delay_found_tmp; + + +always @(fb_delay) + if (rst_in1==0 && (fb_delay/1000.0 > fb_delay_max)) begin + $display("Warning : The feedback delay on PLL_ADV instance %m at time %t is %f ns. It is over the maximun value %f ns.", $time, fb_delay / 1000.0, fb_delay_max); + end + +// +// generate unlock signal +// + +always @(clk_osc or rst_in) + if (rst_in) + clk_osc <= 0; + else + clk_osc <= #OSC_P2 ~clk_osc; + +always @(posedge clkpll or negedge clkpll) begin + clkin_p <= 1; + clkin_p <= #100 0; +end + +always @(posedge clkfb_in or negedge clkfb_in) begin + clkfb_p <= 1; + clkfb_p <= #100 0; +end + +always @(posedge clk_osc or posedge rst_in or posedge clkin_p) + if (rst_in == 1 || clkin_p == 1) begin + clkin_stopped <= 0; + clkin_lost_cnt <= 0; + end + else if (locked_out && pmcd_mode == 0) begin + if (clkin_lost_cnt < clkin_lost_val) begin + clkin_lost_cnt <= clkin_lost_cnt + 1; + clkin_stopped <= 0; + end + else + clkin_stopped <= 1; + end + +always @(posedge clk_osc or posedge rst_in or posedge clkfb_p) + if (rst_in == 1 || clkfb_p == 1) begin + clkfb_stopped <= 0; + clkfb_lost_cnt <= 0; + end + else if (locked_out && pmcd_mode == 0) begin + if (clkfb_lost_cnt < clkfb_lost_val) begin + clkfb_lost_cnt <= clkfb_lost_cnt + 1; + clkfb_stopped <= 0; + end + else + clkfb_stopped <= 1; + end + + +always @(clkin_jit or rst_in ) + if (rst_in) + clkpll_jitter_unlock = 0; + else + if ( pll_locked_tmp2 && clkfb_stopped == 0 && clkin_stopped == 0) begin + if ((clkin_jit > REF_CLK_JITTER_MAX_tmp) || (clkin_jit < -REF_CLK_JITTER_MAX_tmp)) + clkpll_jitter_unlock = 1; + else + clkpll_jitter_unlock = 0; + end + else + clkpll_jitter_unlock = 0; + + assign pll_unlock = (clkin_stopped || clkfb_stopped || clkpll_jitter_unlock) ? 1 : 0; + +// tasks + + +task clkout_dly_cal; +output [5:0] clkout_dly; +output [2:0] clkpm_sel; +input clkdiv; +input clk_ps; +input reg [160:0] clk_ps_name; + +integer clkdiv; +real clk_ps; +real clk_ps_rl; + +real clk_dly_rl, clk_dly_rem; +integer clkout_dly_tmp; + +begin + + if (clk_ps < 0.0) + clk_dly_rl = (360.0 + clk_ps) * clkdiv / 360.0; + else + clk_dly_rl = clk_ps * clkdiv / 360.0; + + clkout_dly_tmp = $rtoi(clk_dly_rl); + + if (clkout_dly_tmp > 63) begin + $display(" Warning : Attribute %s of PLL_ADV on instance %m is set to %f. Required phase shifting can not be reached since it is over the maximum phase shifting ability of PLL_ADV", clk_ps_name, clk_ps); + clkout_dly = 6'b111111; + end + else + clkout_dly = clkout_dly_tmp; + + clk_dly_rem = clk_dly_rl - clkout_dly; + + if (clk_dly_rem < 0.125) + clkpm_sel = 0; + else if (clk_dly_rem >= 0.125 && clk_dly_rem < 0.25) + clkpm_sel = 1; + else if (clk_dly_rem >= 0.25 && clk_dly_rem < 0.375) + clkpm_sel = 2; + else if (clk_dly_rem >= 0.375 && clk_dly_rem < 0.5) + clkpm_sel = 3; + else if (clk_dly_rem >= 0.5 && clk_dly_rem < 0.625) + clkpm_sel = 4; + else if (clk_dly_rem >= 0.625 && clk_dly_rem < 0.75) + clkpm_sel = 5; + else if (clk_dly_rem >= 0.75 && clk_dly_rem < 0.875) + clkpm_sel = 6; + else if (clk_dly_rem >= 0.875 ) + clkpm_sel = 7; + + if (clk_ps < 0.0) + clk_ps_rl = (clkout_dly + 0.125 * clkpm_sel)* 360.0 / clkdiv - 360.0; + else + clk_ps_rl = (clkout_dly + 0.125 * clkpm_sel) * 360.0 / clkdiv; + + if (((clk_ps_rl- clk_ps) > 0.001) || ((clk_ps_rl- clk_ps) < -0.001)) + $display(" Warning : Attribute %s of PLL_ADV on instance %m is set to %f. Real phase shifting is %f. Required phase shifting can not be reached.", clk_ps_name, clk_ps, clk_ps_rl); + +end +endtask + + +task clk_out_para_cal; +output [6:0] clk_ht; +output [6:0] clk_lt; +output clk_nocnt; +output clk_edge; +input CLKOUT_DIVIDE; +input CLKOUT_DUTY_CYCLE; + +integer CLKOUT_DIVIDE; +real CLKOUT_DUTY_CYCLE; + +real tmp_value; +integer tmp_value1; +real tmp_value2; + +begin + tmp_value = CLKOUT_DIVIDE * CLKOUT_DUTY_CYCLE; + tmp_value1 = $rtoi(tmp_value * 2) % 2; + tmp_value2 = CLKOUT_DIVIDE - tmp_value; + + + if ((tmp_value2) >= O_MAX_HT_LT) begin + clk_lt = 7'b1000000; + end + else begin + if (tmp_value2 < 1.0) + clk_lt = 1; + else + if ( tmp_value1 != 0) + clk_lt = $rtoi(tmp_value2) + 1; + else + clk_lt = $rtoi(tmp_value2); + end + + if ( (CLKOUT_DIVIDE - clk_lt) >= O_MAX_HT_LT) + clk_ht = 7'b1000000; + else + clk_ht = CLKOUT_DIVIDE - clk_lt; + + clk_nocnt = (CLKOUT_DIVIDE ==1) ? 1 : 0; + if ( tmp_value < 1.0) + clk_edge = 1; + else if (tmp_value1 != 0) + clk_edge = 1; + else + clk_edge = 0; +end +endtask + + +function clkout_duty_chk; + input CLKOUT_DIVIDE; + input CLKOUT_DUTY_CYCLE; + input reg [160:0] CLKOUT_DUTY_CYCLE_N; + + integer CLKOUT_DIVIDE, step_tmp; + real CLKOUT_DUTY_CYCLE; + + real CLK_DUTY_CYCLE_MIN, CLK_DUTY_CYCLE_MAX, CLK_DUTY_CYCLE_STEP; + real CLK_DUTY_CYCLE_MIN_rnd; + reg clk_duty_tmp_int; + +begin + + if (CLKOUT_DIVIDE > O_MAX_HT_LT) begin + CLK_DUTY_CYCLE_MIN = (CLKOUT_DIVIDE - O_MAX_HT_LT)/CLKOUT_DIVIDE; + CLK_DUTY_CYCLE_MAX = (O_MAX_HT_LT + 0.5)/CLKOUT_DIVIDE; + CLK_DUTY_CYCLE_MIN_rnd = CLK_DUTY_CYCLE_MIN; + end + else begin + if (CLKOUT_DIVIDE == 1) begin + CLK_DUTY_CYCLE_MIN = 0.0; + CLK_DUTY_CYCLE_MIN_rnd = 0.0; + end + else begin + step_tmp = 1000 / CLKOUT_DIVIDE; + CLK_DUTY_CYCLE_MIN_rnd = step_tmp / 1000.0; + CLK_DUTY_CYCLE_MIN = 1.0 /CLKOUT_DIVIDE; + end + CLK_DUTY_CYCLE_MAX = 1.0; + end + + if (CLKOUT_DUTY_CYCLE > CLK_DUTY_CYCLE_MAX || CLKOUT_DUTY_CYCLE < CLK_DUTY_CYCLE_MIN_rnd) begin + $display(" Attribute Syntax Warning : %s is set to %f on instance %m and is not in the allowed range %f to %f.", CLKOUT_DUTY_CYCLE_N, CLKOUT_DUTY_CYCLE, CLK_DUTY_CYCLE_MIN, CLK_DUTY_CYCLE_MAX ); + end + + clk_duty_tmp_int = 0; + CLK_DUTY_CYCLE_STEP = 0.5 / CLKOUT_DIVIDE; + for (j = 0; j < (2 * CLKOUT_DIVIDE - CLK_DUTY_CYCLE_MIN/CLK_DUTY_CYCLE_STEP); j = j + 1) + if (((CLK_DUTY_CYCLE_MIN + CLK_DUTY_CYCLE_STEP * j) - CLKOUT_DUTY_CYCLE) > -0.001 && + ((CLK_DUTY_CYCLE_MIN + CLK_DUTY_CYCLE_STEP * j) - CLKOUT_DUTY_CYCLE) < 0.001) + clk_duty_tmp_int = 1; + + if ( clk_duty_tmp_int != 1) begin + $display(" Attribute Syntax Warning : %s is set to %f on instance %m and is not an allowed value. Allowed values are:", CLKOUT_DUTY_CYCLE_N, CLKOUT_DUTY_CYCLE); + for (j = 0; j < (2 * CLKOUT_DIVIDE - CLK_DUTY_CYCLE_MIN/CLK_DUTY_CYCLE_STEP); j = j + 1) + $display("%f", CLK_DUTY_CYCLE_MIN + CLK_DUTY_CYCLE_STEP * j); + end + + clkout_duty_chk = 1'b1; +end +endfunction + + +function para_int_pmcd_chk; + input para_in; + input reg [160:0] para_name; + input range_low; + input range_high; + input pmcd_mode; + input pmcd_value; + + integer para_in; + integer range_low; + integer range_high; + integer pmcd_value; +begin + + if (para_in < range_low || para_in > range_high) + begin + $display("Attribute Syntax Error : The Attribute %s on PLL_ADV instance %m is set to %d. Legal values for this attribute are %d to %d.", para_name, para_in, range_low, range_high); + $finish; + end + else if (pmcd_mode == 1 && para_in != pmcd_value) begin + $display("Attribute Syntax Error : The Attribute %s on PLL_ADV instance %m is set to %d when attribute PLL_PMCD_MODE is set to TRUE. Legal values for this attribute is %d when PLL in PMCD MODE.", para_name, para_in, pmcd_value); + $finish; + end + + para_int_pmcd_chk = 1'b1; +end +endfunction + +function para_real_pmcd_chk; + input para_in; + input reg [160:0] para_name; + input range_low; + input range_high; + input pmcd_mode; + input pmcd_value; + + real para_in; + real range_low; + real range_high; + real pmcd_value; +begin + + if (para_in < range_low || para_in > range_high) + begin + $display("Attribute Syntax Error : The Attribute %s on PLL_ADV instance %m is set to %f. Legal values for this attribute are %f to %f.", para_name, para_in, range_low, range_high); + $finish; + end + else if (pmcd_mode == 1 && para_in != pmcd_value) begin + $display("Attribute Syntax Error : The Attribute %s on PLL_ADV instance %m is set to %f when attribute PLL_PMCD_MODE is set to TRUE. Legal values for this attribute is %f when PLL in PMCD MODE.", para_name, para_in, pmcd_value); + $finish; + end + + para_real_pmcd_chk = 1'b0; +end +endfunction + +function para_int_range_chk; + input para_in; + input reg [160:0] para_name; + input range_low; + input range_high; + + integer para_in; + integer range_low; + integer range_high; +begin + if ( para_in < range_low || para_in > range_high) begin + $display("Attribute Syntax Error : The Attribute %s on PLL_ADV instance %m is set to %d. Legal values for this attribute are %d to %d.", para_name, para_in, range_low, range_high); + $finish; + end + para_int_range_chk = 1'b1; +end +endfunction + +function para_real_range_chk; + input para_in; + input reg [160:0] para_name; + input range_low; + input range_high; + + real para_in; + real range_low; + real range_high; +begin + if ( para_in < range_low || para_in > range_high) begin + $display("Attribute Syntax Error : The Attribute %s on PLL_ADV instance %m is set to %f. Legal values for this attribute are %f to %f.", para_name, para_in, range_low, range_high); + $finish; + end + + para_real_range_chk = 1'b0; +end +endfunction + +task clkout_pm_cal; + output [7:0] clk_ht1; + output [7:0] clk_div; + output [7:0] clk_div1; + input [6:0] clk_ht; + input [6:0] clk_lt; + input clk_nocnt; + input clk_edge; + +begin + if (clk_nocnt ==1) begin +// clk_div = 8'b00000001; + clk_div = clk_ht + clk_lt ; + clk_div1 = 8'b00000001; + clk_ht1 = 8'b00000001; + end + else begin + if ( clk_edge == 1) + clk_ht1 = 2 * clk_ht + 1; + else + clk_ht1 = 2 * clk_ht; + clk_div = clk_ht + clk_lt ; + clk_div1 = 2 * clk_div -1; + end +end +endtask + +task clkout_delay_para_drp; + output [5:0] clkout_dly; + output clk_nocnt; + output clk_edge; + input [15:0] di_in; + input [4:0] daddr_in; +begin + +// if (di_in[15:8] != 8'h00) begin +// $display(" Error : PLL_ADV on instance %m input DI[15:8] is set to %h and need to be set to 00h at address DADDR=%b at time %t.", di_in[15:8], daddr_in, $time); +// $finish; +// end + clkout_dly = di_in[5:0]; + clk_nocnt = di_in[6]; + clk_edge = di_in[7]; +end +endtask + +task clkout_hl_para_drp; + output [6:0] clk_lt; + output [6:0] clk_ht; + output [2:0] clkpm_sel; + input [15:0] di_in_tmp; + input [4:0] daddr_in_tmp; +begin + if (di_in_tmp[12] != 1) begin + $display(" Error : PLL_ADV on instance %m input DI is %h at address DADDR=%b at time %t. The bit 12 need to be set to 1 .", di_in_tmp, daddr_in_tmp, $time); +// $finish; + end + if ( di_in_tmp[5:0] == 6'b0) + clk_lt = 7'b1000000; + else + clk_lt = { 1'b0, di_in_tmp[5:0]}; + + if (di_in_tmp[11:6] == 6'b0) + clk_ht = 7'b1000000; + else + clk_ht = { 1'b0, di_in_tmp[11:6]}; + clkpm_sel = di_in_tmp[15:13]; +end +endtask + + + +endmodule diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/PLL_BASE.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/PLL_BASE.v new file mode 100644 index 0000000..af73ad1 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/PLL_BASE.v @@ -0,0 +1,153 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/rainier/PLL_BASE.v,v 1.8 2010/02/23 00:00:26 yanx Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Timing Simulation Library Component +// / / Phase Lock Loop Clock +// /___/ /\ Filename : PLL_BASE.v +// \ \ / \ Timestamp : +// \___\/\___\ +// +// Revision: +// 12/02/05 - Initial version. +// 02/24/06 - Add real/integer to parameter. +// 02/26/09 - Add CLK_FEEDBACK parameter for spartan6. +// 02/23/10 - Pass CLK_FEEDBACK to PLL_ADV (CR549901) +// End Revision + + +`timescale 1 ps / 1 ps + + module PLL_BASE ( + CLKFBOUT, + CLKOUT0, + CLKOUT1, + CLKOUT2, + CLKOUT3, + CLKOUT4, + CLKOUT5, + LOCKED, + CLKFBIN, + CLKIN, + RST + ); + + parameter BANDWIDTH = "OPTIMIZED"; + parameter integer CLKFBOUT_MULT = 1; + parameter real CLKFBOUT_PHASE = 0.0; + parameter real CLKIN_PERIOD = 0.000; + parameter integer CLKOUT0_DIVIDE = 1; + parameter real CLKOUT0_DUTY_CYCLE = 0.5; + parameter real CLKOUT0_PHASE = 0.0; + parameter integer CLKOUT1_DIVIDE = 1; + parameter real CLKOUT1_DUTY_CYCLE = 0.5; + parameter real CLKOUT1_PHASE = 0.0; + parameter integer CLKOUT2_DIVIDE = 1; + parameter real CLKOUT2_DUTY_CYCLE = 0.5; + parameter real CLKOUT2_PHASE = 0.0; + parameter integer CLKOUT3_DIVIDE = 1; + parameter real CLKOUT3_DUTY_CYCLE = 0.5; + parameter real CLKOUT3_PHASE = 0.0; + parameter integer CLKOUT4_DIVIDE = 1; + parameter real CLKOUT4_DUTY_CYCLE = 0.5; + parameter real CLKOUT4_PHASE = 0.0; + parameter integer CLKOUT5_DIVIDE = 1; + parameter real CLKOUT5_DUTY_CYCLE = 0.5; + parameter real CLKOUT5_PHASE = 0.0; + parameter CLK_FEEDBACK = "CLKFBOUT"; + parameter COMPENSATION = "SYSTEM_SYNCHRONOUS"; + parameter integer DIVCLK_DIVIDE = 1; + parameter real REF_JITTER = 0.100; + parameter RESET_ON_LOSS_OF_LOCK = "FALSE"; + + output CLKFBOUT; + output CLKOUT0; + output CLKOUT1; + output CLKOUT2; + output CLKOUT3; + output CLKOUT4; + output CLKOUT5; + output LOCKED; + + input CLKFBIN; + input CLKIN; + input RST; + + + wire OPEN_CLKFBDCM; + wire OPEN_CLKOUTDCM0; + wire OPEN_CLKOUTDCM1; + wire OPEN_CLKOUTDCM2; + wire OPEN_CLKOUTDCM3; + wire OPEN_CLKOUTDCM4; + wire OPEN_CLKOUTDCM5; + wire OPEN_DRDY; + wire [15:0] OPEN_DO; + + PLL_ADV #( + .BANDWIDTH(BANDWIDTH), + .CLKFBOUT_MULT(CLKFBOUT_MULT), + .CLKFBOUT_PHASE(CLKFBOUT_PHASE), + .CLKIN1_PERIOD(CLKIN_PERIOD), + .CLKIN2_PERIOD(10.0), + .CLKOUT0_DIVIDE(CLKOUT0_DIVIDE), + .CLKOUT0_DUTY_CYCLE(CLKOUT0_DUTY_CYCLE), + .CLKOUT0_PHASE(CLKOUT0_PHASE), + .CLKOUT1_DIVIDE(CLKOUT1_DIVIDE), + .CLKOUT1_DUTY_CYCLE(CLKOUT1_DUTY_CYCLE), + .CLKOUT1_PHASE(CLKOUT1_PHASE), + .CLKOUT2_DIVIDE(CLKOUT2_DIVIDE), + .CLKOUT2_DUTY_CYCLE(CLKOUT2_DUTY_CYCLE), + .CLKOUT2_PHASE(CLKOUT2_PHASE), + .CLKOUT3_DIVIDE(CLKOUT3_DIVIDE), + .CLKOUT3_DUTY_CYCLE(CLKOUT3_DUTY_CYCLE), + .CLKOUT3_PHASE(CLKOUT3_PHASE), + .CLKOUT4_DIVIDE(CLKOUT4_DIVIDE), + .CLKOUT4_DUTY_CYCLE(CLKOUT4_DUTY_CYCLE), + .CLKOUT4_PHASE(CLKOUT4_PHASE), + .CLKOUT5_DIVIDE(CLKOUT5_DIVIDE), + .CLKOUT5_DUTY_CYCLE(CLKOUT5_DUTY_CYCLE), + .CLKOUT5_PHASE(CLKOUT5_PHASE), + .CLK_FEEDBACK(CLK_FEEDBACK), + .COMPENSATION(COMPENSATION), + .DIVCLK_DIVIDE(DIVCLK_DIVIDE), + .REF_JITTER(REF_JITTER), + .RESET_ON_LOSS_OF_LOCK(RESET_ON_LOSS_OF_LOCK) + ) + pll_adv_1 ( + .CLKFBDCM (OPEN_CLKFBDCM), + .CLKFBIN (CLKFBIN), + .CLKFBOUT (CLKFBOUT), + .CLKIN1 (CLKIN), + .CLKIN2 (1'b0), + .CLKOUT0 (CLKOUT0), + .CLKOUT1 (CLKOUT1), + .CLKOUT2 (CLKOUT2), + .CLKOUT3 (CLKOUT3), + .CLKOUT4 (CLKOUT4), + .CLKOUT5 (CLKOUT5), + .CLKOUTDCM0 (OPEN_CLKOUTDCM0), + .CLKOUTDCM1 (OPEN_CLKOUTDCM1), + .CLKOUTDCM2 (OPEN_CLKOUTDCM2), + .CLKOUTDCM3 (OPEN_CLKOUTDCM3), + .CLKOUTDCM4 (OPEN_CLKOUTDCM4), + .CLKOUTDCM5 (OPEN_CLKOUTDCM5), + .DADDR (5'b0), + .DCLK (1'b0), + .DEN (1'b0), + .DI (16'b0), + .DO (OPEN_DO), + .DRDY (OPEN_DRDY), + .DWE (1'b0), + .LOCKED (LOCKED), + .CLKINSEL(1'b1), + .REL (1'b0), + .RST (RST) + ); + +endmodule diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/PMCD.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/PMCD.v new file mode 100644 index 0000000..eae1c6d --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/PMCD.v @@ -0,0 +1,187 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/virtex4/PMCD.v,v 1.7 2008/04/04 00:30:50 fphillip Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Phase-Matched Clock Divider +// /___/ /\ Filename : PMCD.v +// \ \ / \ Timestamp : Thu Mar 25 16:43:52 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 06/20/07 - generate clka1d2 clka1d4 clka1d8 in same always block to remove delta delay (CR440337) +// - remove buf. +// 04/03/08 - CR 467565 -- Div clocks toggle before REL goes high when EN_REL=TRUE +// End Revision + +`timescale 1 ps / 1 ps + +module PMCD (CLKA1, CLKA1D2, CLKA1D4, CLKA1D8, CLKB1, CLKC1, CLKD1, CLKA, CLKB, CLKC, CLKD, REL, RST); + + output CLKA1; + output CLKA1D2; + output CLKA1D4; + output CLKA1D8; + output CLKB1; + output CLKC1; + output CLKD1; + + input CLKA; + input CLKB; + input CLKC; + input CLKD; + input REL; + input RST; + + parameter EN_REL = "FALSE"; + parameter RST_DEASSERT_CLK = "CLKA"; + + reg CLKA1, CLKB1, CLKC1, CLKD1; + reg CLKA1D2, CLKA1D4, CLKA1D8; + reg clkdiv_rel_rst; + reg qrel_o_reg1, qrel_o_reg2, qrel_o_reg3; + reg rel_o_mux; + wire rel_rst_o; + + initial begin + + CLKA1 <= 1'b0; + CLKB1 <= 1'b0; + CLKC1 <= 1'b0; + CLKD1 <= 1'b0; + CLKA1D2 <= 1'b0; + CLKA1D4 <= 1'b0; + CLKA1D8 <= 1'b0; + qrel_o_reg1 <= 1'b0; + qrel_o_reg2 <= 1'b0; + qrel_o_reg3 <= 1'b0; + + end + + +//*** asyn RST + always @(RST) begin + + if (RST == 1'b1) begin + + assign qrel_o_reg1 = 1'b1; + assign qrel_o_reg2 = 1'b1; + assign qrel_o_reg3 = 1'b1; + + end + else if (RST == 1'b0) begin + + deassign qrel_o_reg1; + deassign qrel_o_reg2; + deassign qrel_o_reg3; + + end + end + + +//*** Clocks MUX + + always @(CLKA or CLKB or CLKC or CLKD) begin + case (RST_DEASSERT_CLK) + "CLKA" : rel_o_mux <= CLKA; + "CLKB" : rel_o_mux <= CLKB; + "CLKC" : rel_o_mux <= CLKC; + "CLKD" : rel_o_mux <= CLKD; + default : begin + $display("Attribute Syntax Error : The attribute RST_DEASSERT_CLK on PMCD instance %m is set to %s. Legal values for this attribute are CLKA, CLKB, CLKC or CLKD.", RST_DEASSERT_CLK); + $finish; + end + endcase + end + +//*** CLKDIV_RST + initial begin + case (EN_REL) + "FALSE" : begin + clkdiv_rel_rst <= 1'b0; + qrel_o_reg3 <= 1'b0; + end + "TRUE" : begin + clkdiv_rel_rst <= 1'b1; + qrel_o_reg3 <= 1'b1; + end + default : begin + $display("Attribute Syntax Error : The attribute EN_REL on PMCD instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", EN_REL); + $finish; + end + endcase + end + + +//*** Rel and Rst + always @(posedge rel_o_mux) begin + qrel_o_reg1 <= 1'b0; + end + + always @(negedge rel_o_mux) begin + qrel_o_reg2 <= qrel_o_reg1; + end + + always @(posedge REL) begin + qrel_o_reg3 <= 1'b0; + end + + assign rel_rst_o = clkdiv_rel_rst ? (qrel_o_reg3 || qrel_o_reg1) : qrel_o_reg1; + + +//*** CLKA + always @(CLKA or qrel_o_reg2) + if (qrel_o_reg2 == 1'b1) + CLKA1 <= 1'b0; + else if (qrel_o_reg2 == 1'b0) + CLKA1 <= CLKA; + +//*** CLKB + always @(CLKB or qrel_o_reg2) + if (qrel_o_reg2 == 1'b1) + CLKB1 <= 1'b0; + else if (qrel_o_reg2 == 1'b0) + CLKB1 <= CLKB; + +//*** CLKC + always @(CLKC or qrel_o_reg2) + if (qrel_o_reg2 == 1'b1) + CLKC1 <= 1'b0; + else if (qrel_o_reg2 == 1'b0) + CLKC1 <= CLKC; + +//*** CLKD + always @(CLKD or qrel_o_reg2) + if (qrel_o_reg2 == 1'b1) + CLKD1 <= 1'b0; + else if (qrel_o_reg2 == 1'b0) + CLKD1 <= CLKD; + + +//*** Clock divider + +always @(posedge CLKA or posedge rel_rst_o) + if (rel_rst_o == 1'b1) + begin + CLKA1D2 <= 1'b0; + CLKA1D4 <= 1'b0; + CLKA1D8 <= 1'b0; + end + else if (rel_rst_o == 1'b0) + begin + CLKA1D2 <= ~CLKA1D2; + if (!CLKA1D2) + begin + CLKA1D4 <= ~CLKA1D4; + if (!CLKA1D4) + CLKA1D8 <= ~CLKA1D8; + end + end + +endmodule diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/POST_CRC_INTERNAL.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/POST_CRC_INTERNAL.v new file mode 100644 index 0000000..6ab459d --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/POST_CRC_INTERNAL.v @@ -0,0 +1,29 @@ +/////////////////////////////////////////////////////// +// Copyright (c) 2008 Xilinx Inc. +// All Right Reserved. +/////////////////////////////////////////////////////// +// +// ____ ___ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : +// / / +// /__/ /\ Filename : POST_CRC_INTERNAL.v +// \ \ / \ +// \__\/\__ \ +// +// Revision: 1.0 +/////////////////////////////////////////////////////// + +`timescale 1 ps / 1 ps + +module POST_CRC_INTERNAL ( + CRCERROR +); + + output CRCERROR; + + assign CRCERROR = 0; + +endmodule diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/PPC405_ADV.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/PPC405_ADV.v new file mode 100644 index 0000000..2048713 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/PPC405_ADV.v @@ -0,0 +1,1385 @@ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Power PC Core +// /___/ /\ Filename : PPC405_ADV.v +// \ \ / \ Timestamp : Fri Jun 18 10:57:22 PDT 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. + +`timescale 1 ps / 1 ps + +module PPC405_ADV ( + APUFCMDECODED, + APUFCMDECUDI, + APUFCMDECUDIVALID, + APUFCMENDIAN, + APUFCMFLUSH, + APUFCMINSTRUCTION, + APUFCMINSTRVALID, + APUFCMLOADBYTEEN, + APUFCMLOADDATA, + APUFCMLOADDVALID, + APUFCMOPERANDVALID, + APUFCMRADATA, + APUFCMRBDATA, + APUFCMWRITEBACKOK, + APUFCMXERCA, + C405CPMCORESLEEPREQ, + C405CPMMSRCE, + C405CPMMSREE, + C405CPMTIMERIRQ, + C405CPMTIMERRESETREQ, + C405DBGLOADDATAONAPUDBUS, + C405DBGMSRWE, + C405DBGSTOPACK, + C405DBGWBCOMPLETE, + C405DBGWBFULL, + C405DBGWBIAR, + C405JTGCAPTUREDR, + C405JTGEXTEST, + C405JTGPGMOUT, + C405JTGSHIFTDR, + C405JTGTDO, + C405JTGTDOEN, + C405JTGUPDATEDR, + C405PLBDCUABORT, + C405PLBDCUABUS, + C405PLBDCUBE, + C405PLBDCUCACHEABLE, + C405PLBDCUGUARDED, + C405PLBDCUPRIORITY, + C405PLBDCUREQUEST, + C405PLBDCURNW, + C405PLBDCUSIZE2, + C405PLBDCUU0ATTR, + C405PLBDCUWRDBUS, + C405PLBDCUWRITETHRU, + C405PLBICUABORT, + C405PLBICUABUS, + C405PLBICUCACHEABLE, + C405PLBICUPRIORITY, + C405PLBICUREQUEST, + C405PLBICUSIZE, + C405PLBICUU0ATTR, + C405RSTCHIPRESETREQ, + C405RSTCORERESETREQ, + C405RSTSYSRESETREQ, + C405TRCCYCLE, + C405TRCEVENEXECUTIONSTATUS, + C405TRCODDEXECUTIONSTATUS, + C405TRCTRACESTATUS, + C405TRCTRIGGEREVENTOUT, + C405TRCTRIGGEREVENTTYPE, + C405XXXMACHINECHECK, + DCREMACABUS, + DCREMACCLK, + DCREMACDBUS, + DCREMACENABLER, + DCREMACREAD, + DCREMACWRITE, + DSOCMBRAMABUS, + DSOCMBRAMBYTEWRITE, + DSOCMBRAMEN, + DSOCMBRAMWRDBUS, + DSOCMBUSY, + DSOCMRDADDRVALID, + DSOCMWRADDRVALID, + EXTDCRABUS, + EXTDCRDBUSOUT, + EXTDCRREAD, + EXTDCRWRITE, + ISOCMBRAMEN, + ISOCMBRAMEVENWRITEEN, + ISOCMBRAMODDWRITEEN, + ISOCMBRAMRDABUS, + ISOCMBRAMWRABUS, + ISOCMBRAMWRDBUS, + ISOCMDCRBRAMEVENEN, + ISOCMDCRBRAMODDEN, + ISOCMDCRBRAMRDSELECT, + BRAMDSOCMCLK, + BRAMDSOCMRDDBUS, + BRAMISOCMCLK, + BRAMISOCMDCRRDDBUS, + BRAMISOCMRDDBUS, + CPMC405CLOCK, + CPMC405CORECLKINACTIVE, + CPMC405CPUCLKEN, + CPMC405JTAGCLKEN, + CPMC405SYNCBYPASS, + CPMC405TIMERCLKEN, + CPMC405TIMERTICK, + CPMDCRCLK, + CPMFCMCLK, + DBGC405DEBUGHALT, + DBGC405EXTBUSHOLDACK, + DBGC405UNCONDDEBUGEVENT, + DSARCVALUE, + DSCNTLVALUE, + DSOCMRWCOMPLETE, + EICC405CRITINPUTIRQ, + EICC405EXTINPUTIRQ, + EMACDCRACK, + EMACDCRDBUS, + EXTDCRACK, + EXTDCRDBUSIN, + FCMAPUCR, + FCMAPUDCDCREN, + FCMAPUDCDFORCEALIGN, + FCMAPUDCDFORCEBESTEERING, + FCMAPUDCDFPUOP, + FCMAPUDCDGPRWRITE, + FCMAPUDCDLDSTBYTE, + FCMAPUDCDLDSTDW, + FCMAPUDCDLDSTHW, + FCMAPUDCDLDSTQW, + FCMAPUDCDLDSTWD, + FCMAPUDCDLOAD, + FCMAPUDCDPRIVOP, + FCMAPUDCDRAEN, + FCMAPUDCDRBEN, + FCMAPUDCDSTORE, + FCMAPUDCDTRAPBE, + FCMAPUDCDTRAPLE, + FCMAPUDCDUPDATE, + FCMAPUDCDXERCAEN, + FCMAPUDCDXEROVEN, + FCMAPUDECODEBUSY, + FCMAPUDONE, + FCMAPUEXCEPTION, + FCMAPUEXEBLOCKINGMCO, + FCMAPUEXECRFIELD, + FCMAPUEXENONBLOCKINGMCO, + FCMAPUINSTRACK, + FCMAPULOADWAIT, + FCMAPURESULT, + FCMAPURESULTVALID, + FCMAPUSLEEPNOTREADY, + FCMAPUXERCA, + FCMAPUXEROV, + ISARCVALUE, + ISCNTLVALUE, + JTGC405BNDSCANTDO, + JTGC405TCK, + JTGC405TDI, + JTGC405TMS, + JTGC405TRSTNEG, + MCBCPUCLKEN, + MCBJTAGEN, + MCBTIMEREN, + MCPPCRST, + PLBC405DCUADDRACK, + PLBC405DCUBUSY, + PLBC405DCUERR, + PLBC405DCURDDACK, + PLBC405DCURDDBUS, + PLBC405DCURDWDADDR, + PLBC405DCUSSIZE1, + PLBC405DCUWRDACK, + PLBC405ICUADDRACK, + PLBC405ICUBUSY, + PLBC405ICUERR, + PLBC405ICURDDACK, + PLBC405ICURDDBUS, + PLBC405ICURDWDADDR, + PLBC405ICUSSIZE1, + PLBCLK, + RSTC405RESETCHIP, + RSTC405RESETCORE, + RSTC405RESETSYS, + TIEAPUCONTROL, + TIEAPUUDI1, + TIEAPUUDI2, + TIEAPUUDI3, + TIEAPUUDI4, + TIEAPUUDI5, + TIEAPUUDI6, + TIEAPUUDI7, + TIEAPUUDI8, + TIEC405DETERMINISTICMULT, + TIEC405DISOPERANDFWD, + TIEC405MMUEN, + TIEDCRADDR, + TIEPVRBIT10, + TIEPVRBIT11, + TIEPVRBIT28, + TIEPVRBIT29, + TIEPVRBIT30, + TIEPVRBIT31, + TIEPVRBIT8, + TIEPVRBIT9, + TRCC405TRACEDISABLE, + TRCC405TRIGGEREVENTIN +); + +localparam in_delay=1; +localparam out_delay=100; + +output APUFCMDECODED; +output APUFCMDECUDIVALID; +output APUFCMENDIAN; +output APUFCMFLUSH; +output APUFCMINSTRVALID; +output APUFCMLOADDVALID; +output APUFCMOPERANDVALID; +output APUFCMWRITEBACKOK; +output APUFCMXERCA; +output C405CPMCORESLEEPREQ; +output C405CPMMSRCE; +output C405CPMMSREE; +output C405CPMTIMERIRQ; +output C405CPMTIMERRESETREQ; +output C405DBGLOADDATAONAPUDBUS; +output C405DBGMSRWE; +output C405DBGSTOPACK; +output C405DBGWBCOMPLETE; +output C405DBGWBFULL; +output C405JTGCAPTUREDR; +output C405JTGEXTEST; +output C405JTGPGMOUT; +output C405JTGSHIFTDR; +output C405JTGTDO; +output C405JTGTDOEN; +output C405JTGUPDATEDR; +output C405PLBDCUABORT; +output C405PLBDCUCACHEABLE; +output C405PLBDCUGUARDED; +output C405PLBDCUREQUEST; +output C405PLBDCURNW; +output C405PLBDCUSIZE2; +output C405PLBDCUU0ATTR; +output C405PLBDCUWRITETHRU; +output C405PLBICUABORT; +output C405PLBICUCACHEABLE; +output C405PLBICUREQUEST; +output C405PLBICUU0ATTR; +output C405RSTCHIPRESETREQ; +output C405RSTCORERESETREQ; +output C405RSTSYSRESETREQ; +output C405TRCCYCLE; +output C405TRCTRIGGEREVENTOUT; +output C405XXXMACHINECHECK; +output DCREMACCLK; +output DCREMACENABLER; +output DCREMACREAD; +output DCREMACWRITE; +output DSOCMBRAMEN; +output DSOCMBUSY; +output DSOCMRDADDRVALID; +output DSOCMWRADDRVALID; +output EXTDCRREAD; +output EXTDCRWRITE; +output ISOCMBRAMEN; +output ISOCMBRAMEVENWRITEEN; +output ISOCMBRAMODDWRITEEN; +output ISOCMDCRBRAMEVENEN; +output ISOCMDCRBRAMODDEN; +output ISOCMDCRBRAMRDSELECT; +output [0:10] C405TRCTRIGGEREVENTTYPE; +output [0:1] C405PLBDCUPRIORITY; +output [0:1] C405PLBICUPRIORITY; +output [0:1] C405TRCEVENEXECUTIONSTATUS; +output [0:1] C405TRCODDEXECUTIONSTATUS; +output [0:29] C405DBGWBIAR; +output [0:29] C405PLBICUABUS; +output [0:2] APUFCMDECUDI; +output [0:31] APUFCMINSTRUCTION; +output [0:31] APUFCMLOADDATA; +output [0:31] APUFCMRADATA; +output [0:31] APUFCMRBDATA; +output [0:31] C405PLBDCUABUS; +output [0:31] DCREMACDBUS; +output [0:31] DSOCMBRAMWRDBUS; +output [0:31] EXTDCRDBUSOUT; +output [0:31] ISOCMBRAMWRDBUS; +output [0:3] APUFCMLOADBYTEEN; +output [0:3] C405TRCTRACESTATUS; +output [0:3] DSOCMBRAMBYTEWRITE; +output [0:63] C405PLBDCUWRDBUS; +output [0:7] C405PLBDCUBE; +output [0:9] EXTDCRABUS; +output [2:3] C405PLBICUSIZE; +output [8:28] ISOCMBRAMRDABUS; +output [8:28] ISOCMBRAMWRABUS; +output [8:29] DSOCMBRAMABUS; +output [8:9] DCREMACABUS; + +input BRAMDSOCMCLK; +input BRAMISOCMCLK; +input CPMC405CLOCK; +input CPMC405CORECLKINACTIVE; +input CPMC405CPUCLKEN; +input CPMC405JTAGCLKEN; +input CPMC405SYNCBYPASS; +input CPMC405TIMERCLKEN; +input CPMC405TIMERTICK; +input CPMDCRCLK; +input CPMFCMCLK; +input DBGC405DEBUGHALT; +input DBGC405EXTBUSHOLDACK; +input DBGC405UNCONDDEBUGEVENT; +input DSOCMRWCOMPLETE; +input EICC405CRITINPUTIRQ; +input EICC405EXTINPUTIRQ; +input EMACDCRACK; +input EXTDCRACK; +input FCMAPUDCDCREN; +input FCMAPUDCDFORCEALIGN; +input FCMAPUDCDFORCEBESTEERING; +input FCMAPUDCDFPUOP; +input FCMAPUDCDGPRWRITE; +input FCMAPUDCDLDSTBYTE; +input FCMAPUDCDLDSTDW; +input FCMAPUDCDLDSTHW; +input FCMAPUDCDLDSTQW; +input FCMAPUDCDLDSTWD; +input FCMAPUDCDLOAD; +input FCMAPUDCDPRIVOP; +input FCMAPUDCDRAEN; +input FCMAPUDCDRBEN; +input FCMAPUDCDSTORE; +input FCMAPUDCDTRAPBE; +input FCMAPUDCDTRAPLE; +input FCMAPUDCDUPDATE; +input FCMAPUDCDXERCAEN; +input FCMAPUDCDXEROVEN; +input FCMAPUDECODEBUSY; +input FCMAPUDONE; +input FCMAPUEXCEPTION; +input FCMAPUEXEBLOCKINGMCO; +input FCMAPUEXENONBLOCKINGMCO; +input FCMAPUINSTRACK; +input FCMAPULOADWAIT; +input FCMAPURESULTVALID; +input FCMAPUSLEEPNOTREADY; +input FCMAPUXERCA; +input FCMAPUXEROV; +input JTGC405BNDSCANTDO; +input JTGC405TCK; +input JTGC405TDI; +input JTGC405TMS; +input JTGC405TRSTNEG; +input MCBCPUCLKEN; +input MCBJTAGEN; +input MCBTIMEREN; +input MCPPCRST; +input PLBC405DCUADDRACK; +input PLBC405DCUBUSY; +input PLBC405DCUERR; +input PLBC405DCURDDACK; +input PLBC405DCUSSIZE1; +input PLBC405DCUWRDACK; +input PLBC405ICUADDRACK; +input PLBC405ICUBUSY; +input PLBC405ICUERR; +input PLBC405ICURDDACK; +input PLBC405ICUSSIZE1; +input PLBCLK; +input RSTC405RESETCHIP; +input RSTC405RESETCORE; +input RSTC405RESETSYS; +input TIEC405DETERMINISTICMULT; +input TIEC405DISOPERANDFWD; +input TIEC405MMUEN; +input TIEPVRBIT10; +input TIEPVRBIT11; +input TIEPVRBIT28; +input TIEPVRBIT29; +input TIEPVRBIT30; +input TIEPVRBIT31; +input TIEPVRBIT8; +input TIEPVRBIT9; +input TRCC405TRACEDISABLE; +input TRCC405TRIGGEREVENTIN; +input [0:15] TIEAPUCONTROL; +input [0:23] TIEAPUUDI1; +input [0:23] TIEAPUUDI2; +input [0:23] TIEAPUUDI3; +input [0:23] TIEAPUUDI4; +input [0:23] TIEAPUUDI5; +input [0:23] TIEAPUUDI6; +input [0:23] TIEAPUUDI7; +input [0:23] TIEAPUUDI8; +input [0:2] FCMAPUEXECRFIELD; +input [0:31] BRAMDSOCMRDDBUS; +input [0:31] BRAMISOCMDCRRDDBUS; +input [0:31] EMACDCRDBUS; +input [0:31] EXTDCRDBUSIN; +input [0:31] FCMAPURESULT; +input [0:3] FCMAPUCR; +input [0:5] TIEDCRADDR; +input [0:63] BRAMISOCMRDDBUS; +input [0:63] PLBC405DCURDDBUS; +input [0:63] PLBC405ICURDDBUS; +input [0:7] DSARCVALUE; +input [0:7] DSCNTLVALUE; +input [0:7] ISARCVALUE; +input [0:7] ISCNTLVALUE; +input [1:3] PLBC405DCURDWDADDR; +input [1:3] PLBC405ICURDWDADDR; + +wire APUFCMDECODED_delay; +wire APUFCMDECUDIVALID_delay; +wire APUFCMENDIAN_delay; +wire APUFCMFLUSH_delay; +wire APUFCMINSTRVALID_delay; +wire APUFCMLOADDVALID_delay; +wire APUFCMOPERANDVALID_delay; +wire APUFCMWRITEBACKOK_delay; +wire APUFCMXERCA_delay; +wire BRAMDSOCMCLK_delay; +wire BRAMISOCMCLK_delay; +wire C405CPMCORESLEEPREQ_delay; +wire C405CPMMSRCE_delay; +wire C405CPMMSREE_delay; +wire C405CPMTIMERIRQ_delay; +wire C405CPMTIMERRESETREQ_delay; +wire C405DBGLOADDATAONAPUDBUS_delay; +wire C405DBGMSRWE_delay; +wire C405DBGSTOPACK_delay; +wire C405DBGWBCOMPLETE_delay; +wire C405DBGWBFULL_delay; +wire C405JTGCAPTUREDR_delay; +wire C405JTGEXTEST_delay; +wire C405JTGPGMOUT_delay; +wire C405JTGSHIFTDR_delay; +wire C405JTGTDOEN_delay; +wire C405JTGTDO_delay; +wire C405JTGUPDATEDR_delay; +wire C405PLBDCUABORT_delay; +wire C405PLBDCUCACHEABLE_delay; +wire C405PLBDCUGUARDED_delay; +wire C405PLBDCUREQUEST_delay; +wire C405PLBDCURNW_delay; +wire C405PLBDCUSIZE2_delay; +wire C405PLBDCUU0ATTR_delay; +wire C405PLBDCUWRITETHRU_delay; +wire C405PLBICUABORT_delay; +wire C405PLBICUCACHEABLE_delay; +wire C405PLBICUREQUEST_delay; +wire C405PLBICUU0ATTR_delay; +wire C405RSTCHIPRESETREQ_delay; +wire C405RSTCORERESETREQ_delay; +wire C405RSTSYSRESETREQ_delay; +wire C405TRCCYCLE_delay; +wire C405TRCTRIGGEREVENTOUT_delay; +wire C405XXXMACHINECHECK_delay; +wire CPMC405CLOCK_delay; +wire CPMC405CORECLKINACTIVE_delay; +wire CPMC405CPUCLKEN_delay; +wire CPMC405JTAGCLKEN_delay; +wire CPMC405SYNCBYPASS_delay; +wire CPMC405TIMERCLKEN_delay; +wire CPMC405TIMERTICK_delay; +wire CPMDCRCLK_delay; +wire CPMFCMCLK_delay; +wire DBGC405DEBUGHALT_delay; +wire DBGC405EXTBUSHOLDACK_delay; +wire DBGC405UNCONDDEBUGEVENT_delay; +wire DCREMACCLK_delay; +wire DCREMACENABLER_delay; +wire DCREMACREAD_delay; +wire DCREMACWRITE_delay; +wire DSOCMBRAMEN_delay; +wire DSOCMBUSY_delay; +wire DSOCMRDADDRVALID_delay; +wire DSOCMRWCOMPLETE_delay; +wire DSOCMWRADDRVALID_delay; +wire EICC405CRITINPUTIRQ_delay; +wire EICC405EXTINPUTIRQ_delay; +wire EMACDCRACK_delay; +wire EXTDCRACK_delay; +wire EXTDCRREAD_delay; +wire EXTDCRWRITE_delay; +wire FCMAPUDCDCREN_delay; +wire FCMAPUDCDFORCEALIGN_delay; +wire FCMAPUDCDFORCEBESTEERING_delay; +wire FCMAPUDCDFPUOP_delay; +wire FCMAPUDCDGPRWRITE_delay; +wire FCMAPUDCDLDSTBYTE_delay; +wire FCMAPUDCDLDSTDW_delay; +wire FCMAPUDCDLDSTHW_delay; +wire FCMAPUDCDLDSTQW_delay; +wire FCMAPUDCDLDSTWD_delay; +wire FCMAPUDCDLOAD_delay; +wire FCMAPUDCDPRIVOP_delay; +wire FCMAPUDCDRAEN_delay; +wire FCMAPUDCDRBEN_delay; +wire FCMAPUDCDSTORE_delay; +wire FCMAPUDCDTRAPBE_delay; +wire FCMAPUDCDTRAPLE_delay; +wire FCMAPUDCDUPDATE_delay; +wire FCMAPUDCDXERCAEN_delay; +wire FCMAPUDCDXEROVEN_delay; +wire FCMAPUDECODEBUSY_delay; +wire FCMAPUDONE_delay; +wire FCMAPUEXCEPTION_delay; +wire FCMAPUEXEBLOCKINGMCO_delay; +wire FCMAPUEXENONBLOCKINGMCO_delay; +wire FCMAPUINSTRACK_delay; +wire FCMAPULOADWAIT_delay; +wire FCMAPURESULTVALID_delay; +wire FCMAPUSLEEPNOTREADY_delay; +wire FCMAPUXERCA_delay; +wire FCMAPUXEROV_delay; +wire ISOCMBRAMEN_delay; +wire ISOCMBRAMEVENWRITEEN_delay; +wire ISOCMBRAMODDWRITEEN_delay; +wire ISOCMDCRBRAMEVENEN_delay; +wire ISOCMDCRBRAMODDEN_delay; +wire ISOCMDCRBRAMRDSELECT_delay; +wire JTGC405BNDSCANTDO_delay; +wire JTGC405TCK_delay; +wire JTGC405TDI_delay; +wire JTGC405TMS_delay; +wire JTGC405TRSTNEG_delay; +wire MCBCPUCLKEN_delay; +wire MCBJTAGEN_delay; +wire MCBTIMEREN_delay; +wire MCPPCRST_delay; +wire PLBC405DCUADDRACK_delay; +wire PLBC405DCUBUSY_delay; +wire PLBC405DCUERR_delay; +wire PLBC405DCURDDACK_delay; +wire PLBC405DCUSSIZE1_delay; +wire PLBC405DCUWRDACK_delay; +wire PLBC405ICUADDRACK_delay; +wire PLBC405ICUBUSY_delay; +wire PLBC405ICUERR_delay; +wire PLBC405ICURDDACK_delay; +wire PLBC405ICUSSIZE1_delay; +wire PLBCLK_delay; +wire RSTC405RESETCHIP_delay; +wire RSTC405RESETCORE_delay; +wire RSTC405RESETSYS_delay; +wire TIEC405DETERMINISTICMULT_delay; +wire TIEC405DISOPERANDFWD_delay; +wire TIEC405MMUEN_delay; +wire TIEPVRBIT10_delay; +wire TIEPVRBIT11_delay; +wire TIEPVRBIT28_delay; +wire TIEPVRBIT29_delay; +wire TIEPVRBIT30_delay; +wire TIEPVRBIT31_delay; +wire TIEPVRBIT8_delay; +wire TIEPVRBIT9_delay; +wire TRCC405TRACEDISABLE_delay; +wire TRCC405TRIGGEREVENTIN_delay; +wire [0:10] C405TRCTRIGGEREVENTTYPE_delay; +wire [0:15] TIEAPUCONTROL_delay; +wire [0:1] C405PLBDCUPRIORITY_delay; +wire [0:1] C405PLBICUPRIORITY_delay; +wire [0:1] C405TRCEVENEXECUTIONSTATUS_delay; +wire [0:1] C405TRCODDEXECUTIONSTATUS_delay; +wire [0:23] TIEAPUUDI1_delay; +wire [0:23] TIEAPUUDI2_delay; +wire [0:23] TIEAPUUDI3_delay; +wire [0:23] TIEAPUUDI4_delay; +wire [0:23] TIEAPUUDI5_delay; +wire [0:23] TIEAPUUDI6_delay; +wire [0:23] TIEAPUUDI7_delay; +wire [0:23] TIEAPUUDI8_delay; +wire [0:29] C405DBGWBIAR_delay; +wire [0:29] C405PLBICUABUS_delay; +wire [0:2] APUFCMDECUDI_delay; +wire [0:2] FCMAPUEXECRFIELD_delay; +wire [0:31] APUFCMINSTRUCTION_delay; +wire [0:31] APUFCMLOADDATA_delay; +wire [0:31] APUFCMRADATA_delay; +wire [0:31] APUFCMRBDATA_delay; +wire [0:31] BRAMDSOCMRDDBUS_delay; +wire [0:31] BRAMISOCMDCRRDDBUS_delay; +wire [0:31] C405PLBDCUABUS_delay; +wire [0:31] DCREMACDBUS_delay; +wire [0:31] DSOCMBRAMWRDBUS_delay; +wire [0:31] EMACDCRDBUS_delay; +wire [0:31] EXTDCRDBUSIN_delay; +wire [0:31] EXTDCRDBUSOUT_delay; +wire [0:31] FCMAPURESULT_delay; +wire [0:31] ISOCMBRAMWRDBUS_delay; +wire [0:3] APUFCMLOADBYTEEN_delay; +wire [0:3] C405TRCTRACESTATUS_delay; +wire [0:3] DSOCMBRAMBYTEWRITE_delay; +wire [0:3] FCMAPUCR_delay; +wire [0:5] TIEDCRADDR_delay; +wire [0:63] BRAMISOCMRDDBUS_delay; +wire [0:63] C405PLBDCUWRDBUS_delay; +wire [0:63] PLBC405DCURDDBUS_delay; +wire [0:63] PLBC405ICURDDBUS_delay; +wire [0:7] C405PLBDCUBE_delay; +wire [0:7] DSARCVALUE_delay; +wire [0:7] DSCNTLVALUE_delay; +wire [0:7] ISARCVALUE_delay; +wire [0:7] ISCNTLVALUE_delay; +wire [0:9] EXTDCRABUS_delay; +wire [1:3] PLBC405DCURDWDADDR_delay; +wire [1:3] PLBC405ICURDWDADDR_delay; +wire [2:3] C405PLBICUSIZE_delay; +wire [8:28] ISOCMBRAMRDABUS_delay; +wire [8:28] ISOCMBRAMWRABUS_delay; +wire [8:29] DSOCMBRAMABUS_delay; +wire [8:9] DCREMACABUS_delay; + +wire BRAMDSOCMCLK_delay_1; +wire BRAMISOCMCLK_delay_1; +wire CPMC405CLOCK_delay_1; +wire CPMC405CORECLKINACTIVE_delay_1; +wire CPMC405CPUCLKEN_delay_1; +wire CPMC405JTAGCLKEN_delay_1; +wire CPMC405SYNCBYPASS_delay_1; +wire CPMC405TIMERCLKEN_delay_1; +wire CPMC405TIMERTICK_delay_1; +wire CPMDCRCLK_delay_1; +wire CPMFCMCLK_delay_1; +wire DBGC405DEBUGHALT_delay_1; +wire DBGC405EXTBUSHOLDACK_delay_1; +wire DBGC405UNCONDDEBUGEVENT_delay_1; +wire DSOCMRWCOMPLETE_delay_1; +wire EICC405CRITINPUTIRQ_delay_1; +wire EICC405EXTINPUTIRQ_delay_1; +wire EMACDCRACK_delay_1; +wire EXTDCRACK_delay_1; +wire FCMAPUDCDCREN_delay_1; +wire FCMAPUDCDFORCEALIGN_delay_1; +wire FCMAPUDCDFORCEBESTEERING_delay_1; +wire FCMAPUDCDFPUOP_delay_1; +wire FCMAPUDCDGPRWRITE_delay_1; +wire FCMAPUDCDLDSTBYTE_delay_1; +wire FCMAPUDCDLDSTDW_delay_1; +wire FCMAPUDCDLDSTHW_delay_1; +wire FCMAPUDCDLDSTQW_delay_1; +wire FCMAPUDCDLDSTWD_delay_1; +wire FCMAPUDCDLOAD_delay_1; +wire FCMAPUDCDPRIVOP_delay_1; +wire FCMAPUDCDRAEN_delay_1; +wire FCMAPUDCDRBEN_delay_1; +wire FCMAPUDCDSTORE_delay_1; +wire FCMAPUDCDTRAPBE_delay_1; +wire FCMAPUDCDTRAPLE_delay_1; +wire FCMAPUDCDUPDATE_delay_1; +wire FCMAPUDCDXERCAEN_delay_1; +wire FCMAPUDCDXEROVEN_delay_1; +wire FCMAPUDECODEBUSY_delay_1; +wire FCMAPUDONE_delay_1; +wire FCMAPUEXCEPTION_delay_1; +wire FCMAPUEXEBLOCKINGMCO_delay_1; +wire FCMAPUEXENONBLOCKINGMCO_delay_1; +wire FCMAPUINSTRACK_delay_1; +wire FCMAPULOADWAIT_delay_1; +wire FCMAPURESULTVALID_delay_1; +wire FCMAPUSLEEPNOTREADY_delay_1; +wire FCMAPUXERCA_delay_1; +wire FCMAPUXEROV_delay_1; +wire JTGC405BNDSCANTDO_delay_1; +wire JTGC405TCK_delay_1; +wire JTGC405TDI_delay_1; +wire JTGC405TMS_delay_1; +wire JTGC405TRSTNEG_delay_1; +wire MCBCPUCLKEN_delay_1; +wire MCBJTAGEN_delay_1; +wire MCBTIMEREN_delay_1; +wire MCPPCRST_delay_1; +wire PLBC405DCUADDRACK_delay_1; +wire PLBC405DCUBUSY_delay_1; +wire PLBC405DCUERR_delay_1; +wire PLBC405DCURDDACK_delay_1; +wire PLBC405DCUSSIZE1_delay_1; +wire PLBC405DCUWRDACK_delay_1; +wire PLBC405ICUADDRACK_delay_1; +wire PLBC405ICUBUSY_delay_1; +wire PLBC405ICUERR_delay_1; +wire PLBC405ICURDDACK_delay_1; +wire PLBC405ICUSSIZE1_delay_1; +wire PLBCLK_delay_1; +wire RSTC405RESETCHIP_delay_1; +wire RSTC405RESETCORE_delay_1; +wire RSTC405RESETSYS_delay_1; +wire TIEC405DETERMINISTICMULT_delay_1; +wire TIEC405DISOPERANDFWD_delay_1; +wire TIEC405MMUEN_delay_1; +wire TIEPVRBIT10_delay_1; +wire TIEPVRBIT11_delay_1; +wire TIEPVRBIT28_delay_1; +wire TIEPVRBIT29_delay_1; +wire TIEPVRBIT30_delay_1; +wire TIEPVRBIT31_delay_1; +wire TIEPVRBIT8_delay_1; +wire TIEPVRBIT9_delay_1; +wire TRCC405TRACEDISABLE_delay_1; +wire TRCC405TRIGGEREVENTIN_delay_1; +wire [0:15] TIEAPUCONTROL_delay_1; +wire [0:23] TIEAPUUDI1_delay_1; +wire [0:23] TIEAPUUDI2_delay_1; +wire [0:23] TIEAPUUDI3_delay_1; +wire [0:23] TIEAPUUDI4_delay_1; +wire [0:23] TIEAPUUDI5_delay_1; +wire [0:23] TIEAPUUDI6_delay_1; +wire [0:23] TIEAPUUDI7_delay_1; +wire [0:23] TIEAPUUDI8_delay_1; +wire [0:2] FCMAPUEXECRFIELD_delay_1; +wire [0:31] BRAMDSOCMRDDBUS_delay_1; +wire [0:31] BRAMISOCMDCRRDDBUS_delay_1; +wire [0:31] EMACDCRDBUS_delay_1; +wire [0:31] EXTDCRDBUSIN_delay_1; +wire [0:31] FCMAPURESULT_delay_1; +wire [0:3] FCMAPUCR_delay_1; +wire [0:5] TIEDCRADDR_delay_1; +wire [0:63] BRAMISOCMRDDBUS_delay_1; +wire [0:63] PLBC405DCURDDBUS_delay_1; +wire [0:63] PLBC405ICURDDBUS_delay_1; +wire [0:7] DSARCVALUE_delay_1; +wire [0:7] DSCNTLVALUE_delay_1; +wire [0:7] ISARCVALUE_delay_1; +wire [0:7] ISCNTLVALUE_delay_1; +wire [1:3] PLBC405DCURDWDADDR_delay_1; +wire [1:3] PLBC405ICURDWDADDR_delay_1; + + +assign #0 EMACDCRACK_delay = EMACDCRACK; +assign #0 EMACDCRDBUS_delay[0:31] = EMACDCRDBUS[0:31]; +assign #0 BRAMDSOCMRDDBUS_delay[0:31] = BRAMDSOCMRDDBUS[0:31]; +assign #0 DSOCMRWCOMPLETE_delay = DSOCMRWCOMPLETE; +assign #0 BRAMISOCMRDDBUS_delay[0:63] = BRAMISOCMRDDBUS[0:63]; +assign #0 BRAMISOCMDCRRDDBUS_delay[0:31] = BRAMISOCMDCRRDDBUS[0:31]; +assign #0 CPMC405CORECLKINACTIVE_delay = CPMC405CORECLKINACTIVE; +assign #0 CPMC405CPUCLKEN_delay = CPMC405CPUCLKEN; +assign #0 CPMC405JTAGCLKEN_delay = CPMC405JTAGCLKEN; +assign #0 CPMC405TIMERCLKEN_delay = CPMC405TIMERCLKEN; +assign #0 CPMC405SYNCBYPASS_delay = CPMC405SYNCBYPASS; +assign #0 CPMC405TIMERTICK_delay = CPMC405TIMERTICK; +assign #0 DBGC405DEBUGHALT_delay = DBGC405DEBUGHALT; +assign #0 DBGC405EXTBUSHOLDACK_delay = DBGC405EXTBUSHOLDACK; +assign #0 DBGC405UNCONDDEBUGEVENT_delay = DBGC405UNCONDDEBUGEVENT; +assign #0 EXTDCRACK_delay = EXTDCRACK; +assign #0 EXTDCRDBUSIN_delay[0:31] = EXTDCRDBUSIN[0:31]; +assign #0 DSARCVALUE_delay[0:7] = DSARCVALUE[0:7]; +assign #0 DSCNTLVALUE_delay[0:7] = DSCNTLVALUE[0:7]; +assign #0 EICC405CRITINPUTIRQ_delay = EICC405CRITINPUTIRQ; +assign #0 EICC405EXTINPUTIRQ_delay = EICC405EXTINPUTIRQ; +assign #0 ISARCVALUE_delay[0:7] = ISARCVALUE[0:7]; +assign #0 ISCNTLVALUE_delay[0:7] = ISCNTLVALUE[0:7]; +assign #0 JTGC405BNDSCANTDO_delay = JTGC405BNDSCANTDO; +assign #0 JTGC405TCK_delay = JTGC405TCK; +assign #0 JTGC405TDI_delay = JTGC405TDI; +assign #0 JTGC405TMS_delay = JTGC405TMS; +assign #0 JTGC405TRSTNEG_delay = JTGC405TRSTNEG; +assign #0 MCBCPUCLKEN_delay = MCBCPUCLKEN; +assign #0 MCBJTAGEN_delay = MCBJTAGEN; +assign #0 MCBTIMEREN_delay = MCBTIMEREN; +assign #0 MCPPCRST_delay = MCPPCRST; +assign #0 PLBC405DCUADDRACK_delay = PLBC405DCUADDRACK; +assign #0 PLBC405DCUBUSY_delay = PLBC405DCUBUSY; +assign #0 PLBC405DCUERR_delay = PLBC405DCUERR; +assign #0 PLBC405DCURDDACK_delay = PLBC405DCURDDACK; +assign #0 PLBC405DCURDDBUS_delay[0:63] = PLBC405DCURDDBUS[0:63]; +assign #0 PLBC405DCURDWDADDR_delay[1:3] = PLBC405DCURDWDADDR[1:3]; +assign #0 PLBC405DCUSSIZE1_delay = PLBC405DCUSSIZE1; +assign #0 PLBC405DCUWRDACK_delay = PLBC405DCUWRDACK; +assign #0 PLBC405ICUADDRACK_delay = PLBC405ICUADDRACK; +assign #0 PLBC405ICUBUSY_delay = PLBC405ICUBUSY; +assign #0 PLBC405ICUERR_delay = PLBC405ICUERR; +assign #0 PLBC405ICURDDACK_delay = PLBC405ICURDDACK; +assign #0 PLBC405ICURDDBUS_delay[0:63] = PLBC405ICURDDBUS[0:63]; +assign #0 PLBC405ICURDWDADDR_delay[1:3] = PLBC405ICURDWDADDR[1:3]; +assign #0 PLBC405ICUSSIZE1_delay = PLBC405ICUSSIZE1; +assign #0 RSTC405RESETCHIP_delay = RSTC405RESETCHIP; +assign #0 RSTC405RESETCORE_delay = RSTC405RESETCORE; +assign #0 RSTC405RESETSYS_delay = RSTC405RESETSYS; +assign #0 TIEC405DETERMINISTICMULT_delay = TIEC405DETERMINISTICMULT; +assign #0 TIEC405DISOPERANDFWD_delay = TIEC405DISOPERANDFWD; +assign #0 TIEC405MMUEN_delay = TIEC405MMUEN; +assign #0 TIEDCRADDR_delay[0:5] = TIEDCRADDR[0:5]; +assign #0 TRCC405TRACEDISABLE_delay = TRCC405TRACEDISABLE; +assign #0 TRCC405TRIGGEREVENTIN_delay = TRCC405TRIGGEREVENTIN; +assign #0 FCMAPURESULT_delay[0:31] = FCMAPURESULT[0:31]; +assign #0 FCMAPUCR_delay[0:3] = FCMAPUCR[0:3]; +assign #0 FCMAPUEXECRFIELD_delay[0:2] = FCMAPUEXECRFIELD[0:2]; +assign #0 FCMAPUDONE_delay = FCMAPUDONE; +assign #0 FCMAPURESULTVALID_delay = FCMAPURESULTVALID; +assign #0 FCMAPUINSTRACK_delay = FCMAPUINSTRACK; +assign #0 FCMAPUEXCEPTION_delay = FCMAPUEXCEPTION; +assign #0 FCMAPUXERCA_delay = FCMAPUXERCA; +assign #0 FCMAPUXEROV_delay = FCMAPUXEROV; +assign #0 FCMAPUDCDFPUOP_delay = FCMAPUDCDFPUOP; +assign #0 FCMAPUDCDGPRWRITE_delay = FCMAPUDCDGPRWRITE; +assign #0 FCMAPUDCDRAEN_delay = FCMAPUDCDRAEN; +assign #0 FCMAPUDCDRBEN_delay = FCMAPUDCDRBEN; +assign #0 FCMAPUDCDLOAD_delay = FCMAPUDCDLOAD; +assign #0 FCMAPUDCDSTORE_delay = FCMAPUDCDSTORE; +assign #0 FCMAPUDCDXERCAEN_delay = FCMAPUDCDXERCAEN; +assign #0 FCMAPUDCDXEROVEN_delay = FCMAPUDCDXEROVEN; +assign #0 FCMAPUDCDPRIVOP_delay = FCMAPUDCDPRIVOP; +assign #0 FCMAPUDCDCREN_delay = FCMAPUDCDCREN; +assign #0 FCMAPUDCDUPDATE_delay = FCMAPUDCDUPDATE; +assign #0 FCMAPUDCDFORCEALIGN_delay = FCMAPUDCDFORCEALIGN; +assign #0 FCMAPUDCDFORCEBESTEERING_delay = FCMAPUDCDFORCEBESTEERING; +assign #0 FCMAPUDCDLDSTBYTE_delay = FCMAPUDCDLDSTBYTE; +assign #0 FCMAPUDCDLDSTHW_delay = FCMAPUDCDLDSTHW; +assign #0 FCMAPUDCDLDSTWD_delay = FCMAPUDCDLDSTWD; +assign #0 FCMAPUDCDLDSTDW_delay = FCMAPUDCDLDSTDW; +assign #0 FCMAPUDCDLDSTQW_delay = FCMAPUDCDLDSTQW; +assign #0 FCMAPUDCDTRAPBE_delay = FCMAPUDCDTRAPBE; +assign #0 FCMAPUDCDTRAPLE_delay = FCMAPUDCDTRAPLE; +assign #0 FCMAPUEXEBLOCKINGMCO_delay = FCMAPUEXEBLOCKINGMCO; +assign #0 FCMAPUEXENONBLOCKINGMCO_delay = FCMAPUEXENONBLOCKINGMCO; +assign #0 FCMAPUSLEEPNOTREADY_delay = FCMAPUSLEEPNOTREADY; +assign #0 FCMAPULOADWAIT_delay = FCMAPULOADWAIT; +assign #0 FCMAPUDECODEBUSY_delay = FCMAPUDECODEBUSY; +assign #0 TIEAPUCONTROL_delay[0:15] = TIEAPUCONTROL[0:15]; +assign #0 TIEAPUUDI1_delay[0:23] = TIEAPUUDI1[0:23]; +assign #0 TIEAPUUDI2_delay[0:23] = TIEAPUUDI2[0:23]; +assign #0 TIEAPUUDI3_delay[0:23] = TIEAPUUDI3[0:23]; +assign #0 TIEAPUUDI4_delay[0:23] = TIEAPUUDI4[0:23]; +assign #0 TIEAPUUDI5_delay[0:23] = TIEAPUUDI5[0:23]; +assign #0 TIEAPUUDI6_delay[0:23] = TIEAPUUDI6[0:23]; +assign #0 TIEAPUUDI7_delay[0:23] = TIEAPUUDI7[0:23]; +assign #0 TIEAPUUDI8_delay[0:23] = TIEAPUUDI8[0:23]; + + +assign #0 DCREMACABUS[8:9] = DCREMACABUS_delay[8:9]; +assign #0 DCREMACDBUS[0:31] = DCREMACDBUS_delay[0:31]; +assign #0 DCREMACENABLER = DCREMACENABLER_delay; +assign #0 DCREMACREAD = DCREMACREAD_delay; +assign #0 DCREMACWRITE = DCREMACWRITE_delay; + +assign #(out_delay) C405CPMCORESLEEPREQ = C405CPMCORESLEEPREQ_delay; +assign #(out_delay) C405CPMMSRCE = C405CPMMSRCE_delay; +assign #(out_delay) C405CPMMSREE = C405CPMMSREE_delay; +assign #(out_delay) C405CPMTIMERIRQ = C405CPMTIMERIRQ_delay; +assign #(out_delay) C405CPMTIMERRESETREQ = C405CPMTIMERRESETREQ_delay; +assign #(out_delay) C405DBGMSRWE = C405DBGMSRWE_delay; +assign #(out_delay) C405DBGSTOPACK = C405DBGSTOPACK_delay; +assign #(out_delay) C405DBGWBCOMPLETE = C405DBGWBCOMPLETE_delay; +assign #(out_delay) C405DBGWBFULL = C405DBGWBFULL_delay; +assign #(out_delay) C405DBGWBIAR[0:29] = C405DBGWBIAR_delay[0:29]; +assign #(out_delay) EXTDCRABUS[0:9] = EXTDCRABUS_delay[0:9]; +assign #(out_delay) EXTDCRDBUSOUT[0:31] = EXTDCRDBUSOUT_delay[0:31]; +assign #(out_delay) EXTDCRREAD = EXTDCRREAD_delay; +assign #(out_delay) EXTDCRWRITE = EXTDCRWRITE_delay; +assign #(out_delay) C405JTGCAPTUREDR = C405JTGCAPTUREDR_delay; +assign #(out_delay) C405JTGEXTEST = C405JTGEXTEST_delay; +assign #(out_delay) C405JTGPGMOUT = C405JTGPGMOUT_delay; +assign #(out_delay) C405JTGSHIFTDR = C405JTGSHIFTDR_delay; +assign #(out_delay) C405JTGTDO = C405JTGTDO_delay; +assign #(out_delay) C405JTGTDOEN = C405JTGTDOEN_delay; +assign #(out_delay) C405JTGUPDATEDR = C405JTGUPDATEDR_delay; +assign #(out_delay) C405PLBDCUABORT = C405PLBDCUABORT_delay; +assign #(out_delay) C405PLBDCUABUS[0:31] = C405PLBDCUABUS_delay[0:31]; +assign #(out_delay) C405PLBDCUBE[0:7] = C405PLBDCUBE_delay[0:7]; +assign #(out_delay) C405PLBDCUCACHEABLE = C405PLBDCUCACHEABLE_delay; +assign #(out_delay) C405PLBDCUGUARDED = C405PLBDCUGUARDED_delay; +assign #(out_delay) C405PLBDCUPRIORITY[0:1] = C405PLBDCUPRIORITY_delay[0:1]; +assign #(out_delay) C405PLBDCUREQUEST = C405PLBDCUREQUEST_delay; +assign #(out_delay) C405PLBDCURNW = C405PLBDCURNW_delay; +assign #(out_delay) C405PLBDCUSIZE2 = C405PLBDCUSIZE2_delay; +assign #(out_delay) C405PLBDCUU0ATTR = C405PLBDCUU0ATTR_delay; +assign #(out_delay) C405PLBDCUWRDBUS[0:63] = C405PLBDCUWRDBUS_delay[0:63]; +assign #(out_delay) C405PLBDCUWRITETHRU = C405PLBDCUWRITETHRU_delay; +assign #(out_delay) C405PLBICUABORT = C405PLBICUABORT_delay; +assign #(out_delay) C405PLBICUABUS[0:29] = C405PLBICUABUS_delay[0:29]; +assign #(out_delay) C405PLBICUCACHEABLE = C405PLBICUCACHEABLE_delay; +assign #(out_delay) C405PLBICUPRIORITY[0:1] = C405PLBICUPRIORITY_delay[0:1]; +assign #(out_delay) C405PLBICUREQUEST = C405PLBICUREQUEST_delay; +assign #(out_delay) C405PLBICUSIZE[2:3] = C405PLBICUSIZE_delay[2:3]; +assign #(out_delay) C405PLBICUU0ATTR = C405PLBICUU0ATTR_delay; +assign #(out_delay) C405RSTCHIPRESETREQ = C405RSTCHIPRESETREQ_delay; +assign #(out_delay) C405RSTCORERESETREQ = C405RSTCORERESETREQ_delay; +assign #(out_delay) C405RSTSYSRESETREQ = C405RSTSYSRESETREQ_delay; +assign #(out_delay) C405TRCCYCLE = C405TRCCYCLE_delay; +assign #(out_delay) C405TRCEVENEXECUTIONSTATUS[0:1] = C405TRCEVENEXECUTIONSTATUS_delay[0:1]; +assign #(out_delay) C405TRCODDEXECUTIONSTATUS[0:1] = C405TRCODDEXECUTIONSTATUS_delay[0:1]; +assign #(out_delay) C405TRCTRACESTATUS[0:3] = C405TRCTRACESTATUS_delay[0:3]; +assign #(out_delay) C405TRCTRIGGEREVENTOUT = C405TRCTRIGGEREVENTOUT_delay; +assign #(out_delay) C405TRCTRIGGEREVENTTYPE[0:10] = C405TRCTRIGGEREVENTTYPE_delay[0:10]; +assign #(out_delay) C405XXXMACHINECHECK = C405XXXMACHINECHECK_delay; +assign #(out_delay) DSOCMBRAMABUS[8:29] = DSOCMBRAMABUS_delay[8:29]; +assign #(out_delay) DSOCMBRAMBYTEWRITE[0:3] = DSOCMBRAMBYTEWRITE_delay[0:3]; +assign #(out_delay) DSOCMBRAMEN = DSOCMBRAMEN_delay; +assign #(out_delay) DSOCMBRAMWRDBUS[0:31] = DSOCMBRAMWRDBUS_delay[0:31]; +assign #(out_delay) DSOCMBUSY = DSOCMBUSY_delay; +assign #(out_delay) DSOCMWRADDRVALID = DSOCMWRADDRVALID_delay; +assign #(out_delay) DSOCMRDADDRVALID = DSOCMRDADDRVALID_delay; +assign #(out_delay) ISOCMBRAMEN = ISOCMBRAMEN_delay; +assign #(out_delay) ISOCMBRAMEVENWRITEEN = ISOCMBRAMEVENWRITEEN_delay; +assign #(out_delay) ISOCMBRAMODDWRITEEN = ISOCMBRAMODDWRITEEN_delay; +assign #(out_delay) ISOCMDCRBRAMEVENEN = ISOCMDCRBRAMEVENEN_delay; +assign #(out_delay) ISOCMDCRBRAMODDEN = ISOCMDCRBRAMODDEN_delay; +assign #(out_delay) ISOCMDCRBRAMRDSELECT = ISOCMDCRBRAMRDSELECT_delay; +assign #(out_delay) ISOCMBRAMRDABUS[8:28] = ISOCMBRAMRDABUS_delay[8:28]; +assign #(out_delay) ISOCMBRAMWRABUS[8:28] = ISOCMBRAMWRABUS_delay[8:28]; +assign #(out_delay) ISOCMBRAMWRDBUS[0:31] = ISOCMBRAMWRDBUS_delay[0:31]; +assign #(out_delay) C405DBGLOADDATAONAPUDBUS = C405DBGLOADDATAONAPUDBUS_delay; +assign #(out_delay) APUFCMINSTRUCTION[0:31] = APUFCMINSTRUCTION_delay[0:31]; +assign #(out_delay) APUFCMRADATA[0:31] = APUFCMRADATA_delay[0:31]; +assign #(out_delay) APUFCMRBDATA[0:31] = APUFCMRBDATA_delay[0:31]; +assign #(out_delay) APUFCMLOADDATA[0:31] = APUFCMLOADDATA_delay[0:31]; +assign #(out_delay) APUFCMLOADBYTEEN[0:3] = APUFCMLOADBYTEEN_delay[0:3]; +assign #(out_delay) APUFCMINSTRVALID = APUFCMINSTRVALID_delay; +assign #(out_delay) APUFCMOPERANDVALID = APUFCMOPERANDVALID_delay; +assign #(out_delay) APUFCMLOADDVALID = APUFCMLOADDVALID_delay; +assign #(out_delay) APUFCMFLUSH = APUFCMFLUSH_delay; +assign #(out_delay) APUFCMWRITEBACKOK = APUFCMWRITEBACKOK_delay; +assign #(out_delay) APUFCMENDIAN = APUFCMENDIAN_delay; +assign #(out_delay) APUFCMXERCA = APUFCMXERCA_delay; +assign #(out_delay) APUFCMDECODED = APUFCMDECODED_delay; +assign #(out_delay) APUFCMDECUDI[0:2] = APUFCMDECUDI_delay[0:2]; +assign #(out_delay) APUFCMDECUDIVALID = APUFCMDECUDIVALID_delay; + +assign #(in_delay) BRAMDSOCMCLK_delay_1 = BRAMDSOCMCLK_delay; +assign #(in_delay) BRAMISOCMCLK_delay_1 = BRAMISOCMCLK_delay; +assign #(in_delay) CPMC405CLOCK_delay_1 = CPMC405CLOCK_delay; +assign #(in_delay) CPMC405CORECLKINACTIVE_delay_1 = CPMC405CORECLKINACTIVE_delay; +assign #(in_delay) CPMC405CPUCLKEN_delay_1 = CPMC405CPUCLKEN_delay; +assign #(in_delay) CPMC405JTAGCLKEN_delay_1 = CPMC405JTAGCLKEN_delay; +assign #(in_delay) CPMC405SYNCBYPASS_delay_1 = CPMC405SYNCBYPASS_delay; +assign #(in_delay) CPMC405TIMERCLKEN_delay_1 = CPMC405TIMERCLKEN_delay; +assign #(in_delay) CPMC405TIMERTICK_delay_1 = CPMC405TIMERTICK_delay; +assign #(in_delay) CPMDCRCLK_delay_1 = CPMDCRCLK_delay; +assign #(in_delay) CPMFCMCLK_delay_1 = CPMFCMCLK_delay; +assign #(in_delay) DBGC405DEBUGHALT_delay_1 = DBGC405DEBUGHALT_delay; +assign #(in_delay) DBGC405EXTBUSHOLDACK_delay_1 = DBGC405EXTBUSHOLDACK_delay; +assign #(in_delay) DBGC405UNCONDDEBUGEVENT_delay_1 = DBGC405UNCONDDEBUGEVENT_delay; +assign #(in_delay) DSOCMRWCOMPLETE_delay_1 = DSOCMRWCOMPLETE_delay; +assign #(in_delay) EICC405CRITINPUTIRQ_delay_1 = EICC405CRITINPUTIRQ_delay; +assign #(in_delay) EICC405EXTINPUTIRQ_delay_1 = EICC405EXTINPUTIRQ_delay; +assign #(in_delay) EMACDCRACK_delay_1 = EMACDCRACK_delay; +assign #(in_delay) EXTDCRACK_delay_1 = EXTDCRACK_delay; +assign #(in_delay) FCMAPUDCDCREN_delay_1 = FCMAPUDCDCREN_delay; +assign #(in_delay) FCMAPUDCDFORCEALIGN_delay_1 = FCMAPUDCDFORCEALIGN_delay; +assign #(in_delay) FCMAPUDCDFORCEBESTEERING_delay_1 = FCMAPUDCDFORCEBESTEERING_delay; +assign #(in_delay) FCMAPUDCDFPUOP_delay_1 = FCMAPUDCDFPUOP_delay; +assign #(in_delay) FCMAPUDCDGPRWRITE_delay_1 = FCMAPUDCDGPRWRITE_delay; +assign #(in_delay) FCMAPUDCDLDSTBYTE_delay_1 = FCMAPUDCDLDSTBYTE_delay; +assign #(in_delay) FCMAPUDCDLDSTDW_delay_1 = FCMAPUDCDLDSTDW_delay; +assign #(in_delay) FCMAPUDCDLDSTHW_delay_1 = FCMAPUDCDLDSTHW_delay; +assign #(in_delay) FCMAPUDCDLDSTQW_delay_1 = FCMAPUDCDLDSTQW_delay; +assign #(in_delay) FCMAPUDCDLDSTWD_delay_1 = FCMAPUDCDLDSTWD_delay; +assign #(in_delay) FCMAPUDCDLOAD_delay_1 = FCMAPUDCDLOAD_delay; +assign #(in_delay) FCMAPUDCDPRIVOP_delay_1 = FCMAPUDCDPRIVOP_delay; +assign #(in_delay) FCMAPUDCDRAEN_delay_1 = FCMAPUDCDRAEN_delay; +assign #(in_delay) FCMAPUDCDRBEN_delay_1 = FCMAPUDCDRBEN_delay; +assign #(in_delay) FCMAPUDCDSTORE_delay_1 = FCMAPUDCDSTORE_delay; +assign #(in_delay) FCMAPUDCDTRAPBE_delay_1 = FCMAPUDCDTRAPBE_delay; +assign #(in_delay) FCMAPUDCDTRAPLE_delay_1 = FCMAPUDCDTRAPLE_delay; +assign #(in_delay) FCMAPUDCDUPDATE_delay_1 = FCMAPUDCDUPDATE_delay; +assign #(in_delay) FCMAPUDCDXERCAEN_delay_1 = FCMAPUDCDXERCAEN_delay; +assign #(in_delay) FCMAPUDCDXEROVEN_delay_1 = FCMAPUDCDXEROVEN_delay; +assign #(in_delay) FCMAPUDECODEBUSY_delay_1 = FCMAPUDECODEBUSY_delay; +assign #(in_delay) FCMAPUDONE_delay_1 = FCMAPUDONE_delay; +assign #(in_delay) FCMAPUEXCEPTION_delay_1 = FCMAPUEXCEPTION_delay; +assign #(in_delay) FCMAPUEXEBLOCKINGMCO_delay_1 = FCMAPUEXEBLOCKINGMCO_delay; +assign #(in_delay) FCMAPUEXENONBLOCKINGMCO_delay_1 = FCMAPUEXENONBLOCKINGMCO_delay; +assign #(in_delay) FCMAPUINSTRACK_delay_1 = FCMAPUINSTRACK_delay; +assign #(in_delay) FCMAPULOADWAIT_delay_1 = FCMAPULOADWAIT_delay; +assign #(in_delay) FCMAPURESULTVALID_delay_1 = FCMAPURESULTVALID_delay; +assign #(in_delay) FCMAPUSLEEPNOTREADY_delay_1 = FCMAPUSLEEPNOTREADY_delay; +assign #(in_delay) FCMAPUXERCA_delay_1 = FCMAPUXERCA_delay; +assign #(in_delay) FCMAPUXEROV_delay_1 = FCMAPUXEROV_delay; +assign #(in_delay) JTGC405BNDSCANTDO_delay_1 = JTGC405BNDSCANTDO_delay; +assign #(in_delay) JTGC405TCK_delay_1 = JTGC405TCK_delay; +assign #(in_delay) JTGC405TDI_delay_1 = JTGC405TDI_delay; +assign #(in_delay) JTGC405TMS_delay_1 = JTGC405TMS_delay; +assign #(in_delay) JTGC405TRSTNEG_delay_1 = JTGC405TRSTNEG_delay; +assign #(in_delay) MCBCPUCLKEN_delay_1 = MCBCPUCLKEN_delay; +assign #(in_delay) MCBJTAGEN_delay_1 = MCBJTAGEN_delay; +assign #(in_delay) MCBTIMEREN_delay_1 = MCBTIMEREN_delay; +assign #(in_delay) MCPPCRST_delay_1 = MCPPCRST_delay; +assign #(in_delay) PLBC405DCUADDRACK_delay_1 = PLBC405DCUADDRACK_delay; +assign #(in_delay) PLBC405DCUBUSY_delay_1 = PLBC405DCUBUSY_delay; +assign #(in_delay) PLBC405DCUERR_delay_1 = PLBC405DCUERR_delay; +assign #(in_delay) PLBC405DCURDDACK_delay_1 = PLBC405DCURDDACK_delay; +assign #(in_delay) PLBC405DCUSSIZE1_delay_1 = PLBC405DCUSSIZE1_delay; +assign #(in_delay) PLBC405DCUWRDACK_delay_1 = PLBC405DCUWRDACK_delay; +assign #(in_delay) PLBC405ICUADDRACK_delay_1 = PLBC405ICUADDRACK_delay; +assign #(in_delay) PLBC405ICUBUSY_delay_1 = PLBC405ICUBUSY_delay; +assign #(in_delay) PLBC405ICUERR_delay_1 = PLBC405ICUERR_delay; +assign #(in_delay) PLBC405ICURDDACK_delay_1 = PLBC405ICURDDACK_delay; +assign #(in_delay) PLBC405ICUSSIZE1_delay_1 = PLBC405ICUSSIZE1_delay; +assign #(in_delay) PLBCLK_delay_1 = PLBCLK_delay; +assign #(in_delay) RSTC405RESETCHIP_delay_1 = RSTC405RESETCHIP_delay; +assign #(in_delay) RSTC405RESETCORE_delay_1 = RSTC405RESETCORE_delay; +assign #(in_delay) RSTC405RESETSYS_delay_1 = RSTC405RESETSYS_delay; +assign #(in_delay) TIEC405DETERMINISTICMULT_delay_1 = TIEC405DETERMINISTICMULT_delay; +assign #(in_delay) TIEC405DISOPERANDFWD_delay_1 = TIEC405DISOPERANDFWD_delay; +assign #(in_delay) TIEC405MMUEN_delay_1 = TIEC405MMUEN_delay; +assign #(in_delay) TIEPVRBIT10_delay_1 = TIEPVRBIT10_delay; +assign #(in_delay) TIEPVRBIT11_delay_1 = TIEPVRBIT11_delay; +assign #(in_delay) TIEPVRBIT28_delay_1 = TIEPVRBIT28_delay; +assign #(in_delay) TIEPVRBIT29_delay_1 = TIEPVRBIT29_delay; +assign #(in_delay) TIEPVRBIT30_delay_1 = TIEPVRBIT30_delay; +assign #(in_delay) TIEPVRBIT31_delay_1 = TIEPVRBIT31_delay; +assign #(in_delay) TIEPVRBIT8_delay_1 = TIEPVRBIT8_delay; +assign #(in_delay) TIEPVRBIT9_delay_1 = TIEPVRBIT9_delay; +assign #(in_delay) TRCC405TRACEDISABLE_delay_1 = TRCC405TRACEDISABLE_delay; +assign #(in_delay) TRCC405TRIGGEREVENTIN_delay_1 = TRCC405TRIGGEREVENTIN_delay; +assign #(in_delay) TIEAPUCONTROL_delay_1[0:15] = TIEAPUCONTROL_delay[0:15] ; +assign #(in_delay) TIEAPUUDI1_delay_1[0:23] = TIEAPUUDI1_delay[0:23]; +assign #(in_delay) TIEAPUUDI2_delay_1[0:23] = TIEAPUUDI2_delay[0:23]; +assign #(in_delay) TIEAPUUDI3_delay_1[0:23] = TIEAPUUDI3_delay[0:23]; +assign #(in_delay) TIEAPUUDI4_delay_1[0:23] = TIEAPUUDI4_delay[0:23]; +assign #(in_delay) TIEAPUUDI5_delay_1[0:23] = TIEAPUUDI5_delay[0:23]; +assign #(in_delay) TIEAPUUDI6_delay_1[0:23] = TIEAPUUDI6_delay[0:23]; +assign #(in_delay) TIEAPUUDI7_delay_1[0:23] = TIEAPUUDI7_delay[0:23]; +assign #(in_delay) TIEAPUUDI8_delay_1[0:23] = TIEAPUUDI8_delay[0:23]; +assign #(in_delay) FCMAPUEXECRFIELD_delay_1[0:2] = FCMAPUEXECRFIELD_delay[0:2] ; +assign #(in_delay) BRAMDSOCMRDDBUS_delay_1[0:31] = BRAMDSOCMRDDBUS_delay[0:31] ; +assign #(in_delay) BRAMISOCMDCRRDDBUS_delay_1[0:31] = BRAMISOCMDCRRDDBUS_delay[0:31] ; +assign #(in_delay) EMACDCRDBUS_delay_1[0:31] = EMACDCRDBUS_delay[0:31] ; +assign #(in_delay) EXTDCRDBUSIN_delay_1[0:31] = EXTDCRDBUSIN_delay[0:31] ; +assign #(in_delay) FCMAPURESULT_delay_1[0:31] = FCMAPURESULT_delay[0:31] ; +assign #(in_delay) FCMAPUCR_delay_1[0:3] = FCMAPUCR_delay[0:3] ; +assign #(in_delay) TIEDCRADDR_delay_1[0:5] = TIEDCRADDR_delay[0:5] ; +assign #(in_delay) BRAMISOCMRDDBUS_delay_1[0:63] = BRAMISOCMRDDBUS_delay[0:63] ; +assign #(in_delay) PLBC405DCURDDBUS_delay_1[0:63] = PLBC405DCURDDBUS_delay[0:63] ; +assign #(in_delay) PLBC405ICURDDBUS_delay_1[0:63] = PLBC405ICURDDBUS_delay[0:63] ; +assign #(in_delay) DSARCVALUE_delay_1[0:7] = DSARCVALUE_delay[0:7] ; +assign #(in_delay) DSCNTLVALUE_delay_1[0:7] = DSCNTLVALUE_delay[0:7] ; +assign #(in_delay) ISARCVALUE_delay_1[0:7] = ISARCVALUE_delay[0:7] ; +assign #(in_delay) ISCNTLVALUE_delay_1[0:7] = ISCNTLVALUE_delay[0:7] ; +assign #(in_delay) PLBC405DCURDWDADDR_delay_1[1:3] = PLBC405DCURDWDADDR_delay[1:3] ; +assign #(in_delay) PLBC405ICURDWDADDR_delay_1[1:3] = PLBC405ICURDWDADDR_delay[1:3] ; + +wire FPGA_CCLK; +wire FPGA_BUS_RESET; +wire FPGA_GSR; +wire FPGA_GWE; +wire FPGA_GHIGHB; +wire GSR_OR; + +reg FPGA_POR; +reg FPGA_CCLK_REG; + +tri0 GSR = glbl.GSR; + +`ifdef STARTUP_BLK +assign FPGA_CCLK = TESTBENCH.FPGA_cclk; +assign FPGA_BUS_RESET = TESTBENCH.FPGA_bus_reset; +assign GSR_OR = TESTBENCH.FPGA_gsr; +assign FPGA_GWE = TESTBENCH.FPGA_gwe; +assign FPGA_GHIGHB = TESTBENCH.FPGA_ghigh_b; +`else + +FPGA_startup_VIRTEX4 start_blk( + .bus_reset (FPGA_BUS_RESET), + .ghigh_b (FPGA_GHIGHB), + .gsr (FPGA_GSR), + .done (), + .gwe (FPGA_GWE), + .gts_b (), + .shutdown (1'b0), + .cclk (FPGA_CCLK), + .por (FPGA_POR) +); + +or IGSR_OR (GSR_OR, FPGA_GSR, GSR); + +`define Loc_FPGA_POR_TIME_VIRTEX4 1000 // FPGA Power-On Reset time + +// Generate FPGA CCLK +always + #5000 FPGA_CCLK_REG = ~FPGA_CCLK_REG; + +assign FPGA_CCLK = FPGA_CCLK_REG; + +initial begin + FPGA_CCLK_REG = 0; + FPGA_POR = 1'b1; + #(`Loc_FPGA_POR_TIME_VIRTEX4) FPGA_POR = 1'b0; +end + +`endif // STARTUP_BLK + +wire FPGA_BUS_RESET_delay; +wire GSR_delay; +wire FPGA_GWE_delay; +wire FPGA_GHIGHB_delay; + +assign #0 FPGA_BUS_RESET_delay = FPGA_BUS_RESET; +assign #0 GSR_delay = GSR_OR; +assign #0 FPGA_GWE_delay = FPGA_GWE; +assign #0 FPGA_GHIGHB_delay = FPGA_GHIGHB; + +//`ifdef PROCBLK_NOSWIFT +//usr_pblk_adv_cap Iusr_proc_block_cap( +//`else +PPC405_ADV_SWIFT IPPC405_SWIFT( +//`endif //PROCBLK_NOSWIFT + + .BUS_RESET (FPGA_BUS_RESET_delay), + .GSR (GSR_delay), + .GWE (FPGA_GWE_delay), + .GHIGHB (FPGA_GHIGHB_delay), + .CFG_MCLK (FPGA_CCLK), + + .APUFCMDECODED(APUFCMDECODED_delay), + .APUFCMDECUDIVALID(APUFCMDECUDIVALID_delay), + .APUFCMENDIAN(APUFCMENDIAN_delay), + .APUFCMFLUSH(APUFCMFLUSH_delay), + .APUFCMINSTRVALID(APUFCMINSTRVALID_delay), + .APUFCMLOADDVALID(APUFCMLOADDVALID_delay), + .APUFCMOPERANDVALID(APUFCMOPERANDVALID_delay), + .APUFCMWRITEBACKOK(APUFCMWRITEBACKOK_delay), + .APUFCMXERCA(APUFCMXERCA_delay), + .C405CPMCORESLEEPREQ(C405CPMCORESLEEPREQ_delay), + .C405CPMMSRCE(C405CPMMSRCE_delay), + .C405CPMMSREE(C405CPMMSREE_delay), + .C405CPMTIMERIRQ(C405CPMTIMERIRQ_delay), + .C405CPMTIMERRESETREQ(C405CPMTIMERRESETREQ_delay), + .C405DBGLOADDATAONAPUDBUS(C405DBGLOADDATAONAPUDBUS_delay), + .C405DBGMSRWE(C405DBGMSRWE_delay), + .C405DBGSTOPACK(C405DBGSTOPACK_delay), + .C405DBGWBCOMPLETE(C405DBGWBCOMPLETE_delay), + .C405DBGWBFULL(C405DBGWBFULL_delay), + .C405JTGCAPTUREDR(C405JTGCAPTUREDR_delay), + .C405JTGEXTEST(C405JTGEXTEST_delay), + .C405JTGPGMOUT(C405JTGPGMOUT_delay), + .C405JTGSHIFTDR(C405JTGSHIFTDR_delay), + .C405JTGTDO(C405JTGTDO_delay), + .C405JTGTDOEN(C405JTGTDOEN_delay), + .C405JTGUPDATEDR(C405JTGUPDATEDR_delay), + .C405PLBDCUABORT(C405PLBDCUABORT_delay), + .C405PLBDCUCACHEABLE(C405PLBDCUCACHEABLE_delay), + .C405PLBDCUGUARDED(C405PLBDCUGUARDED_delay), + .C405PLBDCUREQUEST(C405PLBDCUREQUEST_delay), + .C405PLBDCURNW(C405PLBDCURNW_delay), + .C405PLBDCUSIZE2(C405PLBDCUSIZE2_delay), + .C405PLBDCUU0ATTR(C405PLBDCUU0ATTR_delay), + .C405PLBDCUWRITETHRU(C405PLBDCUWRITETHRU_delay), + .C405PLBICUABORT(C405PLBICUABORT_delay), + .C405PLBICUCACHEABLE(C405PLBICUCACHEABLE_delay), + .C405PLBICUREQUEST(C405PLBICUREQUEST_delay), + .C405PLBICUU0ATTR(C405PLBICUU0ATTR_delay), + .C405RSTCHIPRESETREQ(C405RSTCHIPRESETREQ_delay), + .C405RSTCORERESETREQ(C405RSTCORERESETREQ_delay), + .C405RSTSYSRESETREQ(C405RSTSYSRESETREQ_delay), + .C405TRCCYCLE(C405TRCCYCLE_delay), + .C405TRCTRIGGEREVENTOUT(C405TRCTRIGGEREVENTOUT_delay), + .C405XXXMACHINECHECK(C405XXXMACHINECHECK_delay), + .DCREMACCLK(DCREMACCLK), + .DCREMACENABLER(DCREMACENABLER_delay), + .DCREMACREAD(DCREMACREAD_delay), + .DCREMACWRITE(DCREMACWRITE_delay), + .DSOCMBRAMEN(DSOCMBRAMEN_delay), + .DSOCMBUSY(DSOCMBUSY_delay), + .DSOCMRDADDRVALID(DSOCMRDADDRVALID_delay), + .DSOCMWRADDRVALID(DSOCMWRADDRVALID_delay), + .EXTDCRREAD(EXTDCRREAD_delay), + .EXTDCRWRITE(EXTDCRWRITE_delay), + .ISOCMBRAMEN(ISOCMBRAMEN_delay), + .ISOCMBRAMEVENWRITEEN(ISOCMBRAMEVENWRITEEN_delay), + .ISOCMBRAMODDWRITEEN(ISOCMBRAMODDWRITEEN_delay), + .ISOCMDCRBRAMEVENEN(ISOCMDCRBRAMEVENEN_delay), + .ISOCMDCRBRAMODDEN(ISOCMDCRBRAMODDEN_delay), + .ISOCMDCRBRAMRDSELECT(ISOCMDCRBRAMRDSELECT_delay), + .C405TRCTRIGGEREVENTTYPE(C405TRCTRIGGEREVENTTYPE_delay), + .C405PLBDCUPRIORITY(C405PLBDCUPRIORITY_delay), + .C405PLBICUPRIORITY(C405PLBICUPRIORITY_delay), + .C405TRCEVENEXECUTIONSTATUS(C405TRCEVENEXECUTIONSTATUS_delay), + .C405TRCODDEXECUTIONSTATUS(C405TRCODDEXECUTIONSTATUS_delay), + .C405DBGWBIAR(C405DBGWBIAR_delay), + .C405PLBICUABUS(C405PLBICUABUS_delay), + .APUFCMDECUDI(APUFCMDECUDI_delay), + .APUFCMINSTRUCTION(APUFCMINSTRUCTION_delay), + .APUFCMLOADDATA(APUFCMLOADDATA_delay), + .APUFCMRADATA(APUFCMRADATA_delay), + .APUFCMRBDATA(APUFCMRBDATA_delay), + .C405PLBDCUABUS(C405PLBDCUABUS_delay), + .DCREMACDBUS(DCREMACDBUS_delay), + .DSOCMBRAMWRDBUS(DSOCMBRAMWRDBUS_delay), + .EXTDCRDBUSOUT(EXTDCRDBUSOUT_delay), + .ISOCMBRAMWRDBUS(ISOCMBRAMWRDBUS_delay), + .APUFCMLOADBYTEEN(APUFCMLOADBYTEEN_delay), + .C405TRCTRACESTATUS(C405TRCTRACESTATUS_delay), + .DSOCMBRAMBYTEWRITE(DSOCMBRAMBYTEWRITE_delay), + .C405PLBDCUWRDBUS(C405PLBDCUWRDBUS_delay), + .C405PLBDCUBE(C405PLBDCUBE_delay), + .EXTDCRABUS(EXTDCRABUS_delay), + .C405PLBICUSIZE(C405PLBICUSIZE_delay), + .ISOCMBRAMRDABUS(ISOCMBRAMRDABUS_delay), + .ISOCMBRAMWRABUS(ISOCMBRAMWRABUS_delay), + .DSOCMBRAMABUS(DSOCMBRAMABUS_delay), + .DCREMACABUS(DCREMACABUS_delay), + + .BRAMDSOCMCLK(BRAMDSOCMCLK), + .BRAMISOCMCLK(BRAMISOCMCLK), + .CPMC405CLOCK(CPMC405CLOCK), + .CPMC405CORECLKINACTIVE(CPMC405CORECLKINACTIVE_delay_1), + .CPMC405CPUCLKEN(CPMC405CPUCLKEN_delay_1), + .CPMC405JTAGCLKEN(CPMC405JTAGCLKEN_delay_1), + .CPMC405SYNCBYPASS(CPMC405SYNCBYPASS_delay_1), + .CPMC405TIMERCLKEN(CPMC405TIMERCLKEN_delay_1), + .CPMC405TIMERTICK(CPMC405TIMERTICK_delay_1), + .CPMDCRCLK(CPMDCRCLK), + .CPMFCMCLK(CPMFCMCLK), + .DBGC405DEBUGHALT(DBGC405DEBUGHALT_delay_1), + .DBGC405EXTBUSHOLDACK(DBGC405EXTBUSHOLDACK_delay_1), + .DBGC405UNCONDDEBUGEVENT(DBGC405UNCONDDEBUGEVENT_delay_1), + .DSOCMRWCOMPLETE(DSOCMRWCOMPLETE_delay_1), + .EICC405CRITINPUTIRQ(EICC405CRITINPUTIRQ_delay_1), + .EICC405EXTINPUTIRQ(EICC405EXTINPUTIRQ_delay_1), + .EMACDCRACK(EMACDCRACK_delay_1), + .EXTDCRACK(EXTDCRACK_delay_1), + .FCMAPUDCDCREN(FCMAPUDCDCREN_delay_1), + .FCMAPUDCDFORCEALIGN(FCMAPUDCDFORCEALIGN_delay_1), + .FCMAPUDCDFORCEBESTEERING(FCMAPUDCDFORCEBESTEERING_delay_1), + .FCMAPUDCDFPUOP(FCMAPUDCDFPUOP_delay_1), + .FCMAPUDCDGPRWRITE(FCMAPUDCDGPRWRITE_delay_1), + .FCMAPUDCDLDSTBYTE(FCMAPUDCDLDSTBYTE_delay_1), + .FCMAPUDCDLDSTDW(FCMAPUDCDLDSTDW_delay_1), + .FCMAPUDCDLDSTHW(FCMAPUDCDLDSTHW_delay_1), + .FCMAPUDCDLDSTQW(FCMAPUDCDLDSTQW_delay_1), + .FCMAPUDCDLDSTWD(FCMAPUDCDLDSTWD_delay_1), + .FCMAPUDCDLOAD(FCMAPUDCDLOAD_delay_1), + .FCMAPUDCDPRIVOP(FCMAPUDCDPRIVOP_delay_1), + .FCMAPUDCDRAEN(FCMAPUDCDRAEN_delay_1), + .FCMAPUDCDRBEN(FCMAPUDCDRBEN_delay_1), + .FCMAPUDCDSTORE(FCMAPUDCDSTORE_delay_1), + .FCMAPUDCDTRAPBE(FCMAPUDCDTRAPBE_delay_1), + .FCMAPUDCDTRAPLE(FCMAPUDCDTRAPLE_delay_1), + .FCMAPUDCDUPDATE(FCMAPUDCDUPDATE_delay_1), + .FCMAPUDCDXERCAEN(FCMAPUDCDXERCAEN_delay_1), + .FCMAPUDCDXEROVEN(FCMAPUDCDXEROVEN_delay_1), + .FCMAPUDECODEBUSY(FCMAPUDECODEBUSY_delay_1), + .FCMAPUDONE(FCMAPUDONE_delay_1), + .FCMAPUEXCEPTION(FCMAPUEXCEPTION_delay_1), + .FCMAPUEXEBLOCKINGMCO(FCMAPUEXEBLOCKINGMCO_delay_1), + .FCMAPUEXENONBLOCKINGMCO(FCMAPUEXENONBLOCKINGMCO_delay_1), + .FCMAPUINSTRACK(FCMAPUINSTRACK_delay_1), + .FCMAPULOADWAIT(FCMAPULOADWAIT_delay_1), + .FCMAPURESULTVALID(FCMAPURESULTVALID_delay_1), + .FCMAPUSLEEPNOTREADY(FCMAPUSLEEPNOTREADY_delay_1), + .FCMAPUXERCA(FCMAPUXERCA_delay_1), + .FCMAPUXEROV(FCMAPUXEROV_delay_1), + .JTGC405BNDSCANTDO(JTGC405BNDSCANTDO_delay_1), + .JTGC405TCK(JTGC405TCK), + .JTGC405TDI(JTGC405TDI_delay_1), + .JTGC405TMS(JTGC405TMS_delay_1), + .JTGC405TRSTNEG(JTGC405TRSTNEG_delay_1), + .MCBCPUCLKEN(MCBCPUCLKEN_delay_1), + .MCBJTAGEN(MCBJTAGEN_delay_1), + .MCBTIMEREN(MCBTIMEREN_delay_1), + .MCPPCRST(MCPPCRST_delay_1), + .PLBC405DCUADDRACK(PLBC405DCUADDRACK_delay_1), + .PLBC405DCUBUSY(PLBC405DCUBUSY_delay_1), + .PLBC405DCUERR(PLBC405DCUERR_delay_1), + .PLBC405DCURDDACK(PLBC405DCURDDACK_delay_1), + .PLBC405DCUSSIZE1(PLBC405DCUSSIZE1_delay_1), + .PLBC405DCUWRDACK(PLBC405DCUWRDACK_delay_1), + .PLBC405ICUADDRACK(PLBC405ICUADDRACK_delay_1), + .PLBC405ICUBUSY(PLBC405ICUBUSY_delay_1), + .PLBC405ICUERR(PLBC405ICUERR_delay_1), + .PLBC405ICURDDACK(PLBC405ICURDDACK_delay_1), + .PLBC405ICUSSIZE1(PLBC405ICUSSIZE1_delay_1), + .PLBCLK(PLBCLK), + .RSTC405RESETCHIP(RSTC405RESETCHIP_delay_1), + .RSTC405RESETCORE(RSTC405RESETCORE_delay_1), + .RSTC405RESETSYS(RSTC405RESETSYS_delay_1), + .TIEC405DETERMINISTICMULT(TIEC405DETERMINISTICMULT_delay_1), + .TIEC405DISOPERANDFWD(TIEC405DISOPERANDFWD_delay_1), + .TIEC405MMUEN(TIEC405MMUEN_delay_1), + .TIEPVRBIT10(TIEPVRBIT10), + .TIEPVRBIT11(TIEPVRBIT11), + .TIEPVRBIT28(TIEPVRBIT28), + .TIEPVRBIT29(TIEPVRBIT29), + .TIEPVRBIT30(TIEPVRBIT30), + .TIEPVRBIT31(TIEPVRBIT31), + .TIEPVRBIT8(TIEPVRBIT8), + .TIEPVRBIT9(TIEPVRBIT9), + .TRCC405TRACEDISABLE(TRCC405TRACEDISABLE_delay_1), + .TRCC405TRIGGEREVENTIN(TRCC405TRIGGEREVENTIN_delay_1), + .TIEAPUCONTROL(TIEAPUCONTROL_delay_1), + .TIEAPUUDI1(TIEAPUUDI1_delay_1), + .TIEAPUUDI2(TIEAPUUDI2_delay_1), + .TIEAPUUDI3(TIEAPUUDI3_delay_1), + .TIEAPUUDI4(TIEAPUUDI4_delay_1), + .TIEAPUUDI5(TIEAPUUDI5_delay_1), + .TIEAPUUDI6(TIEAPUUDI6_delay_1), + .TIEAPUUDI7(TIEAPUUDI7_delay_1), + .TIEAPUUDI8(TIEAPUUDI8_delay_1), + .FCMAPUEXECRFIELD(FCMAPUEXECRFIELD_delay_1), + .BRAMDSOCMRDDBUS(BRAMDSOCMRDDBUS_delay_1), + .BRAMISOCMDCRRDDBUS(BRAMISOCMDCRRDDBUS_delay_1), + .EMACDCRDBUS(EMACDCRDBUS_delay_1), + .EXTDCRDBUSIN(EXTDCRDBUSIN_delay_1), + .FCMAPURESULT(FCMAPURESULT_delay_1), + .FCMAPUCR(FCMAPUCR_delay_1), + .TIEDCRADDR(TIEDCRADDR_delay_1), + .BRAMISOCMRDDBUS(BRAMISOCMRDDBUS_delay_1), + .PLBC405DCURDDBUS(PLBC405DCURDDBUS_delay_1), + .PLBC405ICURDDBUS(PLBC405ICURDDBUS_delay_1), + .DSARCVALUE(DSARCVALUE_delay_1), + .DSCNTLVALUE(DSCNTLVALUE_delay_1), + .ISARCVALUE(ISARCVALUE_delay_1), + .ISCNTLVALUE(ISCNTLVALUE_delay_1), + .PLBC405DCURDWDADDR(PLBC405DCURDWDADDR_delay_1), + .PLBC405ICURDWDADDR(PLBC405ICURDWDADDR_delay_1) +); + +endmodule + +module FPGA_startup_VIRTEX4 (bus_reset, ghigh_b, gsr, done, gwe, gts_b, shutdown, cclk, por); + +output bus_reset; +output ghigh_b; +output gsr; +output done; +output gwe; +output gts_b; + +input shutdown; +input cclk, por; + +reg bus_reset, abus_reset; +reg ghigh_b, aghigh_b; +reg gsr, agsr; +reg done, adone; +reg gwe, agwe; +reg gts_b, agts_b; + +reg [7:0] count; + +always @ (posedge cclk or posedge por) begin + if (por) count <= {8{1'b0}}; + else if (shutdown &&(count > {8{1'b0}})) count = count - 1; + else if (!shutdown &&(count < {8'hFF})) count = count + 1; +end + +always @ (posedge cclk or posedge por) begin + if (por) begin + {bus_reset,ghigh_b,gsr,done,gwe,gts_b} <= 6'b100000; + end + else begin + {bus_reset,ghigh_b,gsr,done,gwe,gts_b} <= {abus_reset,aghigh_b,agsr,adone,agwe,agts_b}; + end +end + +always @ (count) begin + // defaults + + abus_reset = 1; + aghigh_b = 0; + agsr = 0; + adone = 0; + agwe = 0; + agts_b = 0; + + // Trip times are in order for default sequence. + if (count >= 8'h02) abus_reset = 0; + if (count == 8'h17 || count == 8'h18) agsr = 1; + if (count > 8'h27) aghigh_b = 1; + if (count > 8'h31) adone = 1; + if (count == 8'h33 || count == 8'h34) agsr = 1; + if (count > 8'h36) agwe = 1; + if (count > 8'h37) agts_b = 1; +end + +endmodule // FPGA_startup diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/PPC440.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/PPC440.v new file mode 100644 index 0000000..a7250d4 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/PPC440.v @@ -0,0 +1,2002 @@ +/////////////////////////////////////////////////////////// +// Copyright (c) 1995/2006 Xilinx Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////// +// +// ____ ___ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : +// / / +// /__/ /\ Filename : PPC440.v +// \ \ / \ Timestamp : Thu Apr 19 10:07:12 2007 + +// \__\/\__ \ +// +// Generated by : SmartModelVerilogFileWriter (sm_verilog) +// Revision: +/////////////////////////////////////////////////////////// + +`timescale 1 ps / 1 ps + +module PPC440 ( + APUFCMDECFPUOP, + APUFCMDECLDSTXFERSIZE, + APUFCMDECLOAD, + APUFCMDECNONAUTON, + APUFCMDECSTORE, + APUFCMDECUDI, + APUFCMDECUDIVALID, + APUFCMENDIAN, + APUFCMFLUSH, + APUFCMINSTRUCTION, + APUFCMINSTRVALID, + APUFCMLOADBYTEADDR, + APUFCMLOADDATA, + APUFCMLOADDVALID, + APUFCMMSRFE0, + APUFCMMSRFE1, + APUFCMNEXTINSTRREADY, + APUFCMOPERANDVALID, + APUFCMRADATA, + APUFCMRBDATA, + APUFCMWRITEBACKOK, + C440CPMCORESLEEPREQ, + C440CPMDECIRPTREQ, + C440CPMFITIRPTREQ, + C440CPMMSRCE, + C440CPMMSREE, + C440CPMTIMERRESETREQ, + C440CPMWDIRPTREQ, + C440DBGSYSTEMCONTROL, + C440JTGTDO, + C440JTGTDOEN, + C440MACHINECHECK, + C440RSTCHIPRESETREQ, + C440RSTCORERESETREQ, + C440RSTSYSTEMRESETREQ, + C440TRCBRANCHSTATUS, + C440TRCCYCLE, + C440TRCEXECUTIONSTATUS, + C440TRCTRACESTATUS, + C440TRCTRIGGEREVENTOUT, + C440TRCTRIGGEREVENTTYPE, + DMA0LLRSTENGINEACK, + DMA0LLRXDSTRDYN, + DMA0LLTXD, + DMA0LLTXEOFN, + DMA0LLTXEOPN, + DMA0LLTXREM, + DMA0LLTXSOFN, + DMA0LLTXSOPN, + DMA0LLTXSRCRDYN, + DMA0RXIRQ, + DMA0TXIRQ, + DMA1LLRSTENGINEACK, + DMA1LLRXDSTRDYN, + DMA1LLTXD, + DMA1LLTXEOFN, + DMA1LLTXEOPN, + DMA1LLTXREM, + DMA1LLTXSOFN, + DMA1LLTXSOPN, + DMA1LLTXSRCRDYN, + DMA1RXIRQ, + DMA1TXIRQ, + DMA2LLRSTENGINEACK, + DMA2LLRXDSTRDYN, + DMA2LLTXD, + DMA2LLTXEOFN, + DMA2LLTXEOPN, + DMA2LLTXREM, + DMA2LLTXSOFN, + DMA2LLTXSOPN, + DMA2LLTXSRCRDYN, + DMA2RXIRQ, + DMA2TXIRQ, + DMA3LLRSTENGINEACK, + DMA3LLRXDSTRDYN, + DMA3LLTXD, + DMA3LLTXEOFN, + DMA3LLTXEOPN, + DMA3LLTXREM, + DMA3LLTXSOFN, + DMA3LLTXSOPN, + DMA3LLTXSRCRDYN, + DMA3RXIRQ, + DMA3TXIRQ, + MIMCADDRESS, + MIMCADDRESSVALID, + MIMCBANKCONFLICT, + MIMCBYTEENABLE, + MIMCREADNOTWRITE, + MIMCROWCONFLICT, + MIMCWRITEDATA, + MIMCWRITEDATAVALID, + PPCCPMINTERCONNECTBUSY, + PPCDMDCRABUS, + PPCDMDCRDBUSOUT, + PPCDMDCRREAD, + PPCDMDCRUABUS, + PPCDMDCRWRITE, + PPCDSDCRACK, + PPCDSDCRDBUSIN, + PPCDSDCRTIMEOUTWAIT, + PPCEICINTERCONNECTIRQ, + PPCMPLBABORT, + PPCMPLBABUS, + PPCMPLBBE, + PPCMPLBBUSLOCK, + PPCMPLBLOCKERR, + PPCMPLBPRIORITY, + PPCMPLBRDBURST, + PPCMPLBREQUEST, + PPCMPLBRNW, + PPCMPLBSIZE, + PPCMPLBTATTRIBUTE, + PPCMPLBTYPE, + PPCMPLBUABUS, + PPCMPLBWRBURST, + PPCMPLBWRDBUS, + PPCS0PLBADDRACK, + PPCS0PLBMBUSY, + PPCS0PLBMIRQ, + PPCS0PLBMRDERR, + PPCS0PLBMWRERR, + PPCS0PLBRDBTERM, + PPCS0PLBRDCOMP, + PPCS0PLBRDDACK, + PPCS0PLBRDDBUS, + PPCS0PLBRDWDADDR, + PPCS0PLBREARBITRATE, + PPCS0PLBSSIZE, + PPCS0PLBWAIT, + PPCS0PLBWRBTERM, + PPCS0PLBWRCOMP, + PPCS0PLBWRDACK, + PPCS1PLBADDRACK, + PPCS1PLBMBUSY, + PPCS1PLBMIRQ, + PPCS1PLBMRDERR, + PPCS1PLBMWRERR, + PPCS1PLBRDBTERM, + PPCS1PLBRDCOMP, + PPCS1PLBRDDACK, + PPCS1PLBRDDBUS, + PPCS1PLBRDWDADDR, + PPCS1PLBREARBITRATE, + PPCS1PLBSSIZE, + PPCS1PLBWAIT, + PPCS1PLBWRBTERM, + PPCS1PLBWRCOMP, + PPCS1PLBWRDACK, + + CPMC440CLK, + CPMC440CLKEN, + CPMC440CORECLOCKINACTIVE, + CPMC440TIMERCLOCK, + CPMDCRCLK, + CPMDMA0LLCLK, + CPMDMA1LLCLK, + CPMDMA2LLCLK, + CPMDMA3LLCLK, + CPMFCMCLK, + CPMINTERCONNECTCLK, + CPMINTERCONNECTCLKEN, + CPMINTERCONNECTCLKNTO1, + CPMMCCLK, + CPMPPCMPLBCLK, + CPMPPCS0PLBCLK, + CPMPPCS1PLBCLK, + DBGC440DEBUGHALT, + DBGC440SYSTEMSTATUS, + DBGC440UNCONDDEBUGEVENT, + DCRPPCDMACK, + DCRPPCDMDBUSIN, + DCRPPCDMTIMEOUTWAIT, + DCRPPCDSABUS, + DCRPPCDSDBUSOUT, + DCRPPCDSREAD, + DCRPPCDSWRITE, + EICC440CRITIRQ, + EICC440EXTIRQ, + FCMAPUCONFIRMINSTR, + FCMAPUCR, + FCMAPUDONE, + FCMAPUEXCEPTION, + FCMAPUFPSCRFEX, + FCMAPURESULT, + FCMAPURESULTVALID, + FCMAPUSLEEPNOTREADY, + FCMAPUSTOREDATA, + JTGC440TCK, + JTGC440TDI, + JTGC440TMS, + JTGC440TRSTNEG, + LLDMA0RSTENGINEREQ, + LLDMA0RXD, + LLDMA0RXEOFN, + LLDMA0RXEOPN, + LLDMA0RXREM, + LLDMA0RXSOFN, + LLDMA0RXSOPN, + LLDMA0RXSRCRDYN, + LLDMA0TXDSTRDYN, + LLDMA1RSTENGINEREQ, + LLDMA1RXD, + LLDMA1RXEOFN, + LLDMA1RXEOPN, + LLDMA1RXREM, + LLDMA1RXSOFN, + LLDMA1RXSOPN, + LLDMA1RXSRCRDYN, + LLDMA1TXDSTRDYN, + LLDMA2RSTENGINEREQ, + LLDMA2RXD, + LLDMA2RXEOFN, + LLDMA2RXEOPN, + LLDMA2RXREM, + LLDMA2RXSOFN, + LLDMA2RXSOPN, + LLDMA2RXSRCRDYN, + LLDMA2TXDSTRDYN, + LLDMA3RSTENGINEREQ, + LLDMA3RXD, + LLDMA3RXEOFN, + LLDMA3RXEOPN, + LLDMA3RXREM, + LLDMA3RXSOFN, + LLDMA3RXSOPN, + LLDMA3RXSRCRDYN, + LLDMA3TXDSTRDYN, + MCMIADDRREADYTOACCEPT, + MCMIREADDATA, + MCMIREADDATAERR, + MCMIREADDATAVALID, + PLBPPCMADDRACK, + PLBPPCMMBUSY, + PLBPPCMMIRQ, + PLBPPCMMRDERR, + PLBPPCMMWRERR, + PLBPPCMRDBTERM, + PLBPPCMRDDACK, + PLBPPCMRDDBUS, + PLBPPCMRDPENDPRI, + PLBPPCMRDPENDREQ, + PLBPPCMRDWDADDR, + PLBPPCMREARBITRATE, + PLBPPCMREQPRI, + PLBPPCMSSIZE, + PLBPPCMTIMEOUT, + PLBPPCMWRBTERM, + PLBPPCMWRDACK, + PLBPPCMWRPENDPRI, + PLBPPCMWRPENDREQ, + PLBPPCS0ABORT, + PLBPPCS0ABUS, + PLBPPCS0BE, + PLBPPCS0BUSLOCK, + PLBPPCS0LOCKERR, + PLBPPCS0MASTERID, + PLBPPCS0MSIZE, + PLBPPCS0PAVALID, + PLBPPCS0RDBURST, + PLBPPCS0RDPENDPRI, + PLBPPCS0RDPENDREQ, + PLBPPCS0RDPRIM, + PLBPPCS0REQPRI, + PLBPPCS0RNW, + PLBPPCS0SAVALID, + PLBPPCS0SIZE, + PLBPPCS0TATTRIBUTE, + PLBPPCS0TYPE, + PLBPPCS0UABUS, + PLBPPCS0WRBURST, + PLBPPCS0WRDBUS, + PLBPPCS0WRPENDPRI, + PLBPPCS0WRPENDREQ, + PLBPPCS0WRPRIM, + PLBPPCS1ABORT, + PLBPPCS1ABUS, + PLBPPCS1BE, + PLBPPCS1BUSLOCK, + PLBPPCS1LOCKERR, + PLBPPCS1MASTERID, + PLBPPCS1MSIZE, + PLBPPCS1PAVALID, + PLBPPCS1RDBURST, + PLBPPCS1RDPENDPRI, + PLBPPCS1RDPENDREQ, + PLBPPCS1RDPRIM, + PLBPPCS1REQPRI, + PLBPPCS1RNW, + PLBPPCS1SAVALID, + PLBPPCS1SIZE, + PLBPPCS1TATTRIBUTE, + PLBPPCS1TYPE, + PLBPPCS1UABUS, + PLBPPCS1WRBURST, + PLBPPCS1WRDBUS, + PLBPPCS1WRPENDPRI, + PLBPPCS1WRPENDREQ, + PLBPPCS1WRPRIM, + RSTC440RESETCHIP, + RSTC440RESETCORE, + RSTC440RESETSYSTEM, + TIEC440DCURDLDCACHEPLBPRIO, + TIEC440DCURDNONCACHEPLBPRIO, + TIEC440DCURDTOUCHPLBPRIO, + TIEC440DCURDURGENTPLBPRIO, + TIEC440DCUWRFLUSHPLBPRIO, + TIEC440DCUWRSTOREPLBPRIO, + TIEC440DCUWRURGENTPLBPRIO, + TIEC440ENDIANRESET, + TIEC440ERPNRESET, + TIEC440ICURDFETCHPLBPRIO, + TIEC440ICURDSPECPLBPRIO, + TIEC440ICURDTOUCHPLBPRIO, + TIEC440PIR, + TIEC440PVR, + TIEC440USERRESET, + TIEDCRBASEADDR, + TRCC440TRACEDISABLE, + TRCC440TRIGGEREVENTIN + +); + +parameter CLOCK_DELAY = "FALSE"; +parameter DCR_AUTOLOCK_ENABLE = "TRUE"; +parameter PPCDM_ASYNCMODE = "FALSE"; +parameter PPCDS_ASYNCMODE = "FALSE"; +parameter PPCS0_WIDTH_128N64 = "TRUE"; +parameter PPCS1_WIDTH_128N64 = "TRUE"; +parameter [0:16] APU_CONTROL = 17'h02000; +parameter [0:23] APU_UDI0 = 24'h000000; +parameter [0:23] APU_UDI1 = 24'h000000; +parameter [0:23] APU_UDI10 = 24'h000000; +parameter [0:23] APU_UDI11 = 24'h000000; +parameter [0:23] APU_UDI12 = 24'h000000; +parameter [0:23] APU_UDI13 = 24'h000000; +parameter [0:23] APU_UDI14 = 24'h000000; +parameter [0:23] APU_UDI15 = 24'h000000; +parameter [0:23] APU_UDI2 = 24'h000000; +parameter [0:23] APU_UDI3 = 24'h000000; +parameter [0:23] APU_UDI4 = 24'h000000; +parameter [0:23] APU_UDI5 = 24'h000000; +parameter [0:23] APU_UDI6 = 24'h000000; +parameter [0:23] APU_UDI7 = 24'h000000; +parameter [0:23] APU_UDI8 = 24'h000000; +parameter [0:23] APU_UDI9 = 24'h000000; +parameter [0:31] DMA0_RXCHANNELCTRL = 32'h01010000; +parameter [0:31] DMA0_TXCHANNELCTRL = 32'h01010000; +parameter [0:31] DMA1_RXCHANNELCTRL = 32'h01010000; +parameter [0:31] DMA1_TXCHANNELCTRL = 32'h01010000; +parameter [0:31] DMA2_RXCHANNELCTRL = 32'h01010000; +parameter [0:31] DMA2_TXCHANNELCTRL = 32'h01010000; +parameter [0:31] DMA3_RXCHANNELCTRL = 32'h01010000; +parameter [0:31] DMA3_TXCHANNELCTRL = 32'h01010000; +parameter [0:31] INTERCONNECT_IMASK = 32'hFFFFFFFF; +parameter [0:31] INTERCONNECT_TMPL_SEL = 32'h3FFFFFFF; +parameter [0:31] MI_ARBCONFIG = 32'h00432010; +parameter [0:31] MI_BANKCONFLICT_MASK = 32'h00000000; +parameter [0:31] MI_CONTROL = 32'h0000008F; +parameter [0:31] MI_ROWCONFLICT_MASK = 32'h00000000; +parameter [0:31] PPCM_ARBCONFIG = 32'h00432010; +parameter [0:31] PPCM_CONTROL = 32'h8000009F; +parameter [0:31] PPCM_COUNTER = 32'h00000500; +parameter [0:31] PPCS0_ADDRMAP_TMPL0 = 32'hFFFFFFFF; +parameter [0:31] PPCS0_ADDRMAP_TMPL1 = 32'hFFFFFFFF; +parameter [0:31] PPCS0_ADDRMAP_TMPL2 = 32'hFFFFFFFF; +parameter [0:31] PPCS0_ADDRMAP_TMPL3 = 32'hFFFFFFFF; +parameter [0:31] PPCS0_CONTROL = 32'h8033336C; +parameter [0:31] PPCS1_ADDRMAP_TMPL0 = 32'hFFFFFFFF; +parameter [0:31] PPCS1_ADDRMAP_TMPL1 = 32'hFFFFFFFF; +parameter [0:31] PPCS1_ADDRMAP_TMPL2 = 32'hFFFFFFFF; +parameter [0:31] PPCS1_ADDRMAP_TMPL3 = 32'hFFFFFFFF; +parameter [0:31] PPCS1_CONTROL = 32'h8033336C; +parameter [0:31] XBAR_ADDRMAP_TMPL0 = 32'hFFFF0000; +parameter [0:31] XBAR_ADDRMAP_TMPL1 = 32'h00000000; +parameter [0:31] XBAR_ADDRMAP_TMPL2 = 32'h00000000; +parameter [0:31] XBAR_ADDRMAP_TMPL3 = 32'h00000000; +parameter [0:7] DMA0_CONTROL = 8'h00; +parameter [0:7] DMA1_CONTROL = 8'h00; +parameter [0:7] DMA2_CONTROL = 8'h00; +parameter [0:7] DMA3_CONTROL = 8'h00; +parameter [0:9] DMA0_RXIRQTIMER = 10'h3FF; +parameter [0:9] DMA0_TXIRQTIMER = 10'h3FF; +parameter [0:9] DMA1_RXIRQTIMER = 10'h3FF; +parameter [0:9] DMA1_TXIRQTIMER = 10'h3FF; +parameter [0:9] DMA2_RXIRQTIMER = 10'h3FF; +parameter [0:9] DMA2_TXIRQTIMER = 10'h3FF; +parameter [0:9] DMA3_RXIRQTIMER = 10'h3FF; +parameter [0:9] DMA3_TXIRQTIMER = 10'h3FF; + +localparam in_delay = 1; +localparam out_delay = 0; +localparam CLK_DELAY = 0; + +output APUFCMDECFPUOP; +output APUFCMDECLOAD; +output APUFCMDECNONAUTON; +output APUFCMDECSTORE; +output APUFCMDECUDIVALID; +output APUFCMENDIAN; +output APUFCMFLUSH; +output APUFCMINSTRVALID; +output APUFCMLOADDVALID; +output APUFCMMSRFE0; +output APUFCMMSRFE1; +output APUFCMNEXTINSTRREADY; +output APUFCMOPERANDVALID; +output APUFCMWRITEBACKOK; +output C440CPMCORESLEEPREQ; +output C440CPMDECIRPTREQ; +output C440CPMFITIRPTREQ; +output C440CPMMSRCE; +output C440CPMMSREE; +output C440CPMTIMERRESETREQ; +output C440CPMWDIRPTREQ; +output C440JTGTDO; +output C440JTGTDOEN; +output C440MACHINECHECK; +output C440RSTCHIPRESETREQ; +output C440RSTCORERESETREQ; +output C440RSTSYSTEMRESETREQ; +output C440TRCCYCLE; +output C440TRCTRIGGEREVENTOUT; +output DMA0LLRSTENGINEACK; +output DMA0LLRXDSTRDYN; +output DMA0LLTXEOFN; +output DMA0LLTXEOPN; +output DMA0LLTXSOFN; +output DMA0LLTXSOPN; +output DMA0LLTXSRCRDYN; +output DMA0RXIRQ; +output DMA0TXIRQ; +output DMA1LLRSTENGINEACK; +output DMA1LLRXDSTRDYN; +output DMA1LLTXEOFN; +output DMA1LLTXEOPN; +output DMA1LLTXSOFN; +output DMA1LLTXSOPN; +output DMA1LLTXSRCRDYN; +output DMA1RXIRQ; +output DMA1TXIRQ; +output DMA2LLRSTENGINEACK; +output DMA2LLRXDSTRDYN; +output DMA2LLTXEOFN; +output DMA2LLTXEOPN; +output DMA2LLTXSOFN; +output DMA2LLTXSOPN; +output DMA2LLTXSRCRDYN; +output DMA2RXIRQ; +output DMA2TXIRQ; +output DMA3LLRSTENGINEACK; +output DMA3LLRXDSTRDYN; +output DMA3LLTXEOFN; +output DMA3LLTXEOPN; +output DMA3LLTXSOFN; +output DMA3LLTXSOPN; +output DMA3LLTXSRCRDYN; +output DMA3RXIRQ; +output DMA3TXIRQ; +output MIMCADDRESSVALID; +output MIMCBANKCONFLICT; +output MIMCREADNOTWRITE; +output MIMCROWCONFLICT; +output MIMCWRITEDATAVALID; +output PPCCPMINTERCONNECTBUSY; +output PPCDMDCRREAD; +output PPCDMDCRWRITE; +output PPCDSDCRACK; +output PPCDSDCRTIMEOUTWAIT; +output PPCEICINTERCONNECTIRQ; +output PPCMPLBABORT; +output PPCMPLBBUSLOCK; +output PPCMPLBLOCKERR; +output PPCMPLBRDBURST; +output PPCMPLBREQUEST; +output PPCMPLBRNW; +output PPCMPLBWRBURST; +output PPCS0PLBADDRACK; +output PPCS0PLBRDBTERM; +output PPCS0PLBRDCOMP; +output PPCS0PLBRDDACK; +output PPCS0PLBREARBITRATE; +output PPCS0PLBWAIT; +output PPCS0PLBWRBTERM; +output PPCS0PLBWRCOMP; +output PPCS0PLBWRDACK; +output PPCS1PLBADDRACK; +output PPCS1PLBRDBTERM; +output PPCS1PLBRDCOMP; +output PPCS1PLBRDDACK; +output PPCS1PLBREARBITRATE; +output PPCS1PLBWAIT; +output PPCS1PLBWRBTERM; +output PPCS1PLBWRCOMP; +output PPCS1PLBWRDACK; +output [0:127] APUFCMLOADDATA; +output [0:127] MIMCWRITEDATA; +output [0:127] PPCMPLBWRDBUS; +output [0:127] PPCS0PLBRDDBUS; +output [0:127] PPCS1PLBRDDBUS; +output [0:13] C440TRCTRIGGEREVENTTYPE; +output [0:15] MIMCBYTEENABLE; +output [0:15] PPCMPLBBE; +output [0:15] PPCMPLBTATTRIBUTE; +output [0:1] PPCMPLBPRIORITY; +output [0:1] PPCS0PLBSSIZE; +output [0:1] PPCS1PLBSSIZE; +output [0:2] APUFCMDECLDSTXFERSIZE; +output [0:2] C440TRCBRANCHSTATUS; +output [0:2] PPCMPLBTYPE; +output [0:31] APUFCMINSTRUCTION; +output [0:31] APUFCMRADATA; +output [0:31] APUFCMRBDATA; +output [0:31] DMA0LLTXD; +output [0:31] DMA1LLTXD; +output [0:31] DMA2LLTXD; +output [0:31] DMA3LLTXD; +output [0:31] PPCDMDCRDBUSOUT; +output [0:31] PPCDSDCRDBUSIN; +output [0:31] PPCMPLBABUS; +output [0:35] MIMCADDRESS; +output [0:3] APUFCMDECUDI; +output [0:3] APUFCMLOADBYTEADDR; +output [0:3] DMA0LLTXREM; +output [0:3] DMA1LLTXREM; +output [0:3] DMA2LLTXREM; +output [0:3] DMA3LLTXREM; +output [0:3] PPCMPLBSIZE; +output [0:3] PPCS0PLBMBUSY; +output [0:3] PPCS0PLBMIRQ; +output [0:3] PPCS0PLBMRDERR; +output [0:3] PPCS0PLBMWRERR; +output [0:3] PPCS0PLBRDWDADDR; +output [0:3] PPCS1PLBMBUSY; +output [0:3] PPCS1PLBMIRQ; +output [0:3] PPCS1PLBMRDERR; +output [0:3] PPCS1PLBMWRERR; +output [0:3] PPCS1PLBRDWDADDR; +output [0:4] C440TRCEXECUTIONSTATUS; +output [0:6] C440TRCTRACESTATUS; +output [0:7] C440DBGSYSTEMCONTROL; +output [0:9] PPCDMDCRABUS; +output [20:21] PPCDMDCRUABUS; +output [28:31] PPCMPLBUABUS; + +input CPMC440CLK; +input CPMC440CLKEN; +input CPMC440CORECLOCKINACTIVE; +input CPMC440TIMERCLOCK; +input CPMDCRCLK; +input CPMDMA0LLCLK; +input CPMDMA1LLCLK; +input CPMDMA2LLCLK; +input CPMDMA3LLCLK; +input CPMFCMCLK; +input CPMINTERCONNECTCLK; +input CPMINTERCONNECTCLKEN; +input CPMINTERCONNECTCLKNTO1; +input CPMMCCLK; +input CPMPPCMPLBCLK; +input CPMPPCS0PLBCLK; +input CPMPPCS1PLBCLK; +input DBGC440DEBUGHALT; +input DBGC440UNCONDDEBUGEVENT; +input DCRPPCDMACK; +input DCRPPCDMTIMEOUTWAIT; +input DCRPPCDSREAD; +input DCRPPCDSWRITE; +input EICC440CRITIRQ; +input EICC440EXTIRQ; +input FCMAPUCONFIRMINSTR; +input FCMAPUDONE; +input FCMAPUEXCEPTION; +input FCMAPUFPSCRFEX; +input FCMAPURESULTVALID; +input FCMAPUSLEEPNOTREADY; +input JTGC440TCK; +input JTGC440TDI; +input JTGC440TMS; +input JTGC440TRSTNEG; +input LLDMA0RSTENGINEREQ; +input LLDMA0RXEOFN; +input LLDMA0RXEOPN; +input LLDMA0RXSOFN; +input LLDMA0RXSOPN; +input LLDMA0RXSRCRDYN; +input LLDMA0TXDSTRDYN; +input LLDMA1RSTENGINEREQ; +input LLDMA1RXEOFN; +input LLDMA1RXEOPN; +input LLDMA1RXSOFN; +input LLDMA1RXSOPN; +input LLDMA1RXSRCRDYN; +input LLDMA1TXDSTRDYN; +input LLDMA2RSTENGINEREQ; +input LLDMA2RXEOFN; +input LLDMA2RXEOPN; +input LLDMA2RXSOFN; +input LLDMA2RXSOPN; +input LLDMA2RXSRCRDYN; +input LLDMA2TXDSTRDYN; +input LLDMA3RSTENGINEREQ; +input LLDMA3RXEOFN; +input LLDMA3RXEOPN; +input LLDMA3RXSOFN; +input LLDMA3RXSOPN; +input LLDMA3RXSRCRDYN; +input LLDMA3TXDSTRDYN; +input MCMIADDRREADYTOACCEPT; +input MCMIREADDATAERR; +input MCMIREADDATAVALID; +input PLBPPCMADDRACK; +input PLBPPCMMBUSY; +input PLBPPCMMIRQ; +input PLBPPCMMRDERR; +input PLBPPCMMWRERR; +input PLBPPCMRDBTERM; +input PLBPPCMRDDACK; +input PLBPPCMRDPENDREQ; +input PLBPPCMREARBITRATE; +input PLBPPCMTIMEOUT; +input PLBPPCMWRBTERM; +input PLBPPCMWRDACK; +input PLBPPCMWRPENDREQ; +input PLBPPCS0ABORT; +input PLBPPCS0BUSLOCK; +input PLBPPCS0LOCKERR; +input PLBPPCS0PAVALID; +input PLBPPCS0RDBURST; +input PLBPPCS0RDPENDREQ; +input PLBPPCS0RDPRIM; +input PLBPPCS0RNW; +input PLBPPCS0SAVALID; +input PLBPPCS0WRBURST; +input PLBPPCS0WRPENDREQ; +input PLBPPCS0WRPRIM; +input PLBPPCS1ABORT; +input PLBPPCS1BUSLOCK; +input PLBPPCS1LOCKERR; +input PLBPPCS1PAVALID; +input PLBPPCS1RDBURST; +input PLBPPCS1RDPENDREQ; +input PLBPPCS1RDPRIM; +input PLBPPCS1RNW; +input PLBPPCS1SAVALID; +input PLBPPCS1WRBURST; +input PLBPPCS1WRPENDREQ; +input PLBPPCS1WRPRIM; +input RSTC440RESETCHIP; +input RSTC440RESETCORE; +input RSTC440RESETSYSTEM; +input TIEC440ENDIANRESET; +input TRCC440TRACEDISABLE; +input TRCC440TRIGGEREVENTIN; +input [0:127] FCMAPUSTOREDATA; +input [0:127] MCMIREADDATA; +input [0:127] PLBPPCMRDDBUS; +input [0:127] PLBPPCS0WRDBUS; +input [0:127] PLBPPCS1WRDBUS; +input [0:15] PLBPPCS0BE; +input [0:15] PLBPPCS0TATTRIBUTE; +input [0:15] PLBPPCS1BE; +input [0:15] PLBPPCS1TATTRIBUTE; +input [0:1] PLBPPCMRDPENDPRI; +input [0:1] PLBPPCMREQPRI; +input [0:1] PLBPPCMSSIZE; +input [0:1] PLBPPCMWRPENDPRI; +input [0:1] PLBPPCS0MASTERID; +input [0:1] PLBPPCS0MSIZE; +input [0:1] PLBPPCS0RDPENDPRI; +input [0:1] PLBPPCS0REQPRI; +input [0:1] PLBPPCS0WRPENDPRI; +input [0:1] PLBPPCS1MASTERID; +input [0:1] PLBPPCS1MSIZE; +input [0:1] PLBPPCS1RDPENDPRI; +input [0:1] PLBPPCS1REQPRI; +input [0:1] PLBPPCS1WRPENDPRI; +input [0:1] TIEC440DCURDLDCACHEPLBPRIO; +input [0:1] TIEC440DCURDNONCACHEPLBPRIO; +input [0:1] TIEC440DCURDTOUCHPLBPRIO; +input [0:1] TIEC440DCURDURGENTPLBPRIO; +input [0:1] TIEC440DCUWRFLUSHPLBPRIO; +input [0:1] TIEC440DCUWRSTOREPLBPRIO; +input [0:1] TIEC440DCUWRURGENTPLBPRIO; +input [0:1] TIEC440ICURDFETCHPLBPRIO; +input [0:1] TIEC440ICURDSPECPLBPRIO; +input [0:1] TIEC440ICURDTOUCHPLBPRIO; +input [0:1] TIEDCRBASEADDR; +input [0:2] PLBPPCS0TYPE; +input [0:2] PLBPPCS1TYPE; +input [0:31] DCRPPCDMDBUSIN; +input [0:31] DCRPPCDSDBUSOUT; +input [0:31] FCMAPURESULT; +input [0:31] LLDMA0RXD; +input [0:31] LLDMA1RXD; +input [0:31] LLDMA2RXD; +input [0:31] LLDMA3RXD; +input [0:31] PLBPPCS0ABUS; +input [0:31] PLBPPCS1ABUS; +input [0:3] FCMAPUCR; +input [0:3] LLDMA0RXREM; +input [0:3] LLDMA1RXREM; +input [0:3] LLDMA2RXREM; +input [0:3] LLDMA3RXREM; +input [0:3] PLBPPCMRDWDADDR; +input [0:3] PLBPPCS0SIZE; +input [0:3] PLBPPCS1SIZE; +input [0:3] TIEC440ERPNRESET; +input [0:3] TIEC440USERRESET; +input [0:4] DBGC440SYSTEMSTATUS; +input [0:9] DCRPPCDSABUS; +input [28:31] PLBPPCS0UABUS; +input [28:31] PLBPPCS1UABUS; +input [28:31] TIEC440PIR; +input [28:31] TIEC440PVR; + +reg [0:4] CLOCK_DELAY_BINARY; +reg DCR_AUTOLOCK_ENABLE_BINARY; +reg PPCDM_ASYNCMODE_BINARY; +reg PPCDS_ASYNCMODE_BINARY; +reg PPCS0_WIDTH_128N64_BINARY; +reg PPCS1_WIDTH_128N64_BINARY; + +tri0 GSR = glbl.GSR; + + +initial begin + case (PPCS0_WIDTH_128N64) + "FALSE" : PPCS0_WIDTH_128N64_BINARY = 1'b0; + "TRUE" : PPCS0_WIDTH_128N64_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute PPCS0_WIDTH_128N64 on PPC440 instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", PPCS0_WIDTH_128N64); + $finish; + end + endcase + + case (PPCS1_WIDTH_128N64) + "FALSE" : PPCS1_WIDTH_128N64_BINARY = 1'b0; + "TRUE" : PPCS1_WIDTH_128N64_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute PPCS1_WIDTH_128N64 on PPC440 instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", PPCS1_WIDTH_128N64); + $finish; + end + endcase + + case (PPCDM_ASYNCMODE) + "FALSE" : PPCDM_ASYNCMODE_BINARY = 1'b0; + "TRUE" : PPCDM_ASYNCMODE_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute PPCDM_ASYNCMODE on PPC440 instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", PPCDM_ASYNCMODE); + $finish; + end + endcase + + case (PPCDS_ASYNCMODE) + "FALSE" : PPCDS_ASYNCMODE_BINARY = 1'b0; + "TRUE" : PPCDS_ASYNCMODE_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute PPCDS_ASYNCMODE on PPC440 instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", PPCDS_ASYNCMODE); + $finish; + end + endcase + + case (DCR_AUTOLOCK_ENABLE) + "FALSE" : DCR_AUTOLOCK_ENABLE_BINARY = 1'b0; + "TRUE" : DCR_AUTOLOCK_ENABLE_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute DCR_AUTOLOCK_ENABLE on PPC440 instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", DCR_AUTOLOCK_ENABLE); + $finish; + end + endcase + + case (CLOCK_DELAY) +// "FALSE" : CLOCK_DELAY_BINARY = 1'b0; +// "TRUE" : CLOCK_DELAY_BINARY = 1'b1; +// "FALSE" : CLOCK_DELAY_BINARY = 5'b00100; + "FALSE" : CLOCK_DELAY_BINARY = 5'b10000; + "TRUE" : CLOCK_DELAY_BINARY = 5'b00000; + default : begin + $display("Attribute Syntax Error : The Attribute CLOCK_DELAY on PPC440 instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", CLOCK_DELAY); + $finish; + end + endcase + +end + +wire APUFCMDECFPUOP_delay; +wire APUFCMDECLOAD_delay; +wire APUFCMDECNONAUTON_delay; +wire APUFCMDECSTORE_delay; +wire APUFCMDECUDIVALID_delay; +wire APUFCMENDIAN_delay; +wire APUFCMFLUSH_delay; +wire APUFCMINSTRVALID_delay; +wire APUFCMLOADDVALID_delay; +wire APUFCMMSRFE0_delay; +wire APUFCMMSRFE1_delay; +wire APUFCMNEXTINSTRREADY_delay; +wire APUFCMOPERANDVALID_delay; +wire APUFCMWRITEBACKOK_delay; +wire C440CPMCORESLEEPREQ_delay; +wire C440CPMDECIRPTREQ_delay; +wire C440CPMFITIRPTREQ_delay; +wire C440CPMMSRCE_delay; +wire C440CPMMSREE_delay; +wire C440CPMTIMERRESETREQ_delay; +wire C440CPMWDIRPTREQ_delay; +wire C440JTGTDOEN_delay; +wire C440JTGTDO_delay; +wire C440MACHINECHECK_delay; +wire C440RSTCHIPRESETREQ_delay; +wire C440RSTCORERESETREQ_delay; +wire C440RSTSYSTEMRESETREQ_delay; +wire C440TRCCYCLE_delay; +wire C440TRCTRIGGEREVENTOUT_delay; +wire DMA0LLRSTENGINEACK_delay; +wire DMA0LLRXDSTRDYN_delay; +wire DMA0LLTXEOFN_delay; +wire DMA0LLTXEOPN_delay; +wire DMA0LLTXSOFN_delay; +wire DMA0LLTXSOPN_delay; +wire DMA0LLTXSRCRDYN_delay; +wire DMA0RXIRQ_delay; +wire DMA0TXIRQ_delay; +wire DMA1LLRSTENGINEACK_delay; +wire DMA1LLRXDSTRDYN_delay; +wire DMA1LLTXEOFN_delay; +wire DMA1LLTXEOPN_delay; +wire DMA1LLTXSOFN_delay; +wire DMA1LLTXSOPN_delay; +wire DMA1LLTXSRCRDYN_delay; +wire DMA1RXIRQ_delay; +wire DMA1TXIRQ_delay; +wire DMA2LLRSTENGINEACK_delay; +wire DMA2LLRXDSTRDYN_delay; +wire DMA2LLTXEOFN_delay; +wire DMA2LLTXEOPN_delay; +wire DMA2LLTXSOFN_delay; +wire DMA2LLTXSOPN_delay; +wire DMA2LLTXSRCRDYN_delay; +wire DMA2RXIRQ_delay; +wire DMA2TXIRQ_delay; +wire DMA3LLRSTENGINEACK_delay; +wire DMA3LLRXDSTRDYN_delay; +wire DMA3LLTXEOFN_delay; +wire DMA3LLTXEOPN_delay; +wire DMA3LLTXSOFN_delay; +wire DMA3LLTXSOPN_delay; +wire DMA3LLTXSRCRDYN_delay; +wire DMA3RXIRQ_delay; +wire DMA3TXIRQ_delay; +wire MIMCADDRESSVALID_delay; +wire MIMCBANKCONFLICT_delay; +wire MIMCREADNOTWRITE_delay; +wire MIMCROWCONFLICT_delay; +wire MIMCWRITEDATAVALID_delay; +wire PPCCPMINTERCONNECTBUSY_delay; +wire PPCDMDCRREAD_delay; +wire PPCDMDCRWRITE_delay; +wire PPCDSDCRACK_delay; +wire PPCDSDCRTIMEOUTWAIT_delay; +wire PPCEICINTERCONNECTIRQ_delay; +wire PPCMPLBABORT_delay; +wire PPCMPLBBUSLOCK_delay; +wire PPCMPLBLOCKERR_delay; +wire PPCMPLBRDBURST_delay; +wire PPCMPLBREQUEST_delay; +wire PPCMPLBRNW_delay; +wire PPCMPLBWRBURST_delay; +wire PPCS0PLBADDRACK_delay; +wire PPCS0PLBRDBTERM_delay; +wire PPCS0PLBRDCOMP_delay; +wire PPCS0PLBRDDACK_delay; +wire PPCS0PLBREARBITRATE_delay; +wire PPCS0PLBWAIT_delay; +wire PPCS0PLBWRBTERM_delay; +wire PPCS0PLBWRCOMP_delay; +wire PPCS0PLBWRDACK_delay; +wire PPCS1PLBADDRACK_delay; +wire PPCS1PLBRDBTERM_delay; +wire PPCS1PLBRDCOMP_delay; +wire PPCS1PLBRDDACK_delay; +wire PPCS1PLBREARBITRATE_delay; +wire PPCS1PLBWAIT_delay; +wire PPCS1PLBWRBTERM_delay; +wire PPCS1PLBWRCOMP_delay; +wire PPCS1PLBWRDACK_delay; +wire [0:127] APUFCMLOADDATA_delay; +wire [0:127] MIMCWRITEDATA_delay; +wire [0:127] PPCMPLBWRDBUS_delay; +wire [0:127] PPCS0PLBRDDBUS_delay; +wire [0:127] PPCS1PLBRDDBUS_delay; +wire [0:13] C440TRCTRIGGEREVENTTYPE_delay; +wire [0:15] MIMCBYTEENABLE_delay; +wire [0:15] PPCMPLBBE_delay; +wire [0:15] PPCMPLBTATTRIBUTE_delay; +wire [0:1] PPCMPLBPRIORITY_delay; +wire [0:1] PPCS0PLBSSIZE_delay; +wire [0:1] PPCS1PLBSSIZE_delay; +wire [0:2] APUFCMDECLDSTXFERSIZE_delay; +wire [0:2] C440TRCBRANCHSTATUS_delay; +wire [0:2] PPCMPLBTYPE_delay; +wire [0:31] APUFCMINSTRUCTION_delay; +wire [0:31] APUFCMRADATA_delay; +wire [0:31] APUFCMRBDATA_delay; +wire [0:31] DMA0LLTXD_delay; +wire [0:31] DMA1LLTXD_delay; +wire [0:31] DMA2LLTXD_delay; +wire [0:31] DMA3LLTXD_delay; +wire [0:31] PPCDMDCRDBUSOUT_delay; +wire [0:31] PPCDSDCRDBUSIN_delay; +wire [0:31] PPCMPLBABUS_delay; +wire [0:35] MIMCADDRESS_delay; +wire [0:3] APUFCMDECUDI_delay; +wire [0:3] APUFCMLOADBYTEADDR_delay; +wire [0:3] DMA0LLTXREM_delay; +wire [0:3] DMA1LLTXREM_delay; +wire [0:3] DMA2LLTXREM_delay; +wire [0:3] DMA3LLTXREM_delay; +wire [0:3] PPCMPLBSIZE_delay; +wire [0:3] PPCS0PLBMBUSY_delay; +wire [0:3] PPCS0PLBMIRQ_delay; +wire [0:3] PPCS0PLBMRDERR_delay; +wire [0:3] PPCS0PLBMWRERR_delay; +wire [0:3] PPCS0PLBRDWDADDR_delay; +wire [0:3] PPCS1PLBMBUSY_delay; +wire [0:3] PPCS1PLBMIRQ_delay; +wire [0:3] PPCS1PLBMRDERR_delay; +wire [0:3] PPCS1PLBMWRERR_delay; +wire [0:3] PPCS1PLBRDWDADDR_delay; +wire [0:4] C440TRCEXECUTIONSTATUS_delay; +wire [0:6] C440TRCTRACESTATUS_delay; +wire [0:7] C440DBGSYSTEMCONTROL_delay; +wire [0:9] PPCDMDCRABUS_delay; +wire [20:21] PPCDMDCRUABUS_delay; +wire [28:31] PPCMPLBUABUS_delay; + +wire CPMC440CLKEN_delay; +wire CPMC440CLK_delay; +wire CPMC440CORECLOCKINACTIVE_delay; +wire CPMC440TIMERCLOCK_delay; +wire CPMDCRCLK_delay; +wire CPMDMA0LLCLK_delay; +wire CPMDMA1LLCLK_delay; +wire CPMDMA2LLCLK_delay; +wire CPMDMA3LLCLK_delay; +wire CPMFCMCLK_delay; +wire CPMINTERCONNECTCLKEN_delay; +wire CPMINTERCONNECTCLKNTO1_delay; +wire CPMINTERCONNECTCLK_delay; +wire CPMMCCLK_delay; +wire CPMPPCMPLBCLK_delay; +wire CPMPPCS0PLBCLK_delay; +wire CPMPPCS1PLBCLK_delay; +wire DBGC440DEBUGHALT_delay; +wire DBGC440UNCONDDEBUGEVENT_delay; +wire DCRPPCDMACK_delay; +wire DCRPPCDMTIMEOUTWAIT_delay; +wire DCRPPCDSREAD_delay; +wire DCRPPCDSWRITE_delay; +wire EICC440CRITIRQ_delay; +wire EICC440EXTIRQ_delay; +wire FCMAPUCONFIRMINSTR_delay; +wire FCMAPUDONE_delay; +wire FCMAPUEXCEPTION_delay; +wire FCMAPUFPSCRFEX_delay; +wire FCMAPURESULTVALID_delay; +wire FCMAPUSLEEPNOTREADY_delay; +wire JTGC440TCK_delay; +wire JTGC440TDI_delay; +wire JTGC440TMS_delay; +wire JTGC440TRSTNEG_delay; +wire LLDMA0RSTENGINEREQ_delay; +wire LLDMA0RXEOFN_delay; +wire LLDMA0RXEOPN_delay; +wire LLDMA0RXSOFN_delay; +wire LLDMA0RXSOPN_delay; +wire LLDMA0RXSRCRDYN_delay; +wire LLDMA0TXDSTRDYN_delay; +wire LLDMA1RSTENGINEREQ_delay; +wire LLDMA1RXEOFN_delay; +wire LLDMA1RXEOPN_delay; +wire LLDMA1RXSOFN_delay; +wire LLDMA1RXSOPN_delay; +wire LLDMA1RXSRCRDYN_delay; +wire LLDMA1TXDSTRDYN_delay; +wire LLDMA2RSTENGINEREQ_delay; +wire LLDMA2RXEOFN_delay; +wire LLDMA2RXEOPN_delay; +wire LLDMA2RXSOFN_delay; +wire LLDMA2RXSOPN_delay; +wire LLDMA2RXSRCRDYN_delay; +wire LLDMA2TXDSTRDYN_delay; +wire LLDMA3RSTENGINEREQ_delay; +wire LLDMA3RXEOFN_delay; +wire LLDMA3RXEOPN_delay; +wire LLDMA3RXSOFN_delay; +wire LLDMA3RXSOPN_delay; +wire LLDMA3RXSRCRDYN_delay; +wire LLDMA3TXDSTRDYN_delay; +wire MCMIADDRREADYTOACCEPT_delay; +wire MCMIREADDATAERR_delay; +wire MCMIREADDATAVALID_delay; +wire PLBPPCMADDRACK_delay; +wire PLBPPCMMBUSY_delay; +wire PLBPPCMMIRQ_delay; +wire PLBPPCMMRDERR_delay; +wire PLBPPCMMWRERR_delay; +wire PLBPPCMRDBTERM_delay; +wire PLBPPCMRDDACK_delay; +wire PLBPPCMRDPENDREQ_delay; +wire PLBPPCMREARBITRATE_delay; +wire PLBPPCMTIMEOUT_delay; +wire PLBPPCMWRBTERM_delay; +wire PLBPPCMWRDACK_delay; +wire PLBPPCMWRPENDREQ_delay; +wire PLBPPCS0ABORT_delay; +wire PLBPPCS0BUSLOCK_delay; +wire PLBPPCS0LOCKERR_delay; +wire PLBPPCS0PAVALID_delay; +wire PLBPPCS0RDBURST_delay; +wire PLBPPCS0RDPENDREQ_delay; +wire PLBPPCS0RDPRIM_delay; +wire PLBPPCS0RNW_delay; +wire PLBPPCS0SAVALID_delay; +wire PLBPPCS0WRBURST_delay; +wire PLBPPCS0WRPENDREQ_delay; +wire PLBPPCS0WRPRIM_delay; +wire PLBPPCS1ABORT_delay; +wire PLBPPCS1BUSLOCK_delay; +wire PLBPPCS1LOCKERR_delay; +wire PLBPPCS1PAVALID_delay; +wire PLBPPCS1RDBURST_delay; +wire PLBPPCS1RDPENDREQ_delay; +wire PLBPPCS1RDPRIM_delay; +wire PLBPPCS1RNW_delay; +wire PLBPPCS1SAVALID_delay; +wire PLBPPCS1WRBURST_delay; +wire PLBPPCS1WRPENDREQ_delay; +wire PLBPPCS1WRPRIM_delay; +wire RSTC440RESETCHIP_delay; +wire RSTC440RESETCORE_delay; +wire RSTC440RESETSYSTEM_delay; +wire TIEC440ENDIANRESET_delay; +wire TRCC440TRACEDISABLE_delay; +wire TRCC440TRIGGEREVENTIN_delay; +wire [0:127] FCMAPUSTOREDATA_delay; +wire [0:127] MCMIREADDATA_delay; +wire [0:127] PLBPPCMRDDBUS_delay; +wire [0:127] PLBPPCS0WRDBUS_delay; +wire [0:127] PLBPPCS1WRDBUS_delay; +wire [0:15] PLBPPCS0BE_delay; +wire [0:15] PLBPPCS0TATTRIBUTE_delay; +wire [0:15] PLBPPCS1BE_delay; +wire [0:15] PLBPPCS1TATTRIBUTE_delay; +wire [0:1] PLBPPCMRDPENDPRI_delay; +wire [0:1] PLBPPCMREQPRI_delay; +wire [0:1] PLBPPCMSSIZE_delay; +wire [0:1] PLBPPCMWRPENDPRI_delay; +wire [0:1] PLBPPCS0MASTERID_delay; +wire [0:1] PLBPPCS0MSIZE_delay; +wire [0:1] PLBPPCS0RDPENDPRI_delay; +wire [0:1] PLBPPCS0REQPRI_delay; +wire [0:1] PLBPPCS0WRPENDPRI_delay; +wire [0:1] PLBPPCS1MASTERID_delay; +wire [0:1] PLBPPCS1MSIZE_delay; +wire [0:1] PLBPPCS1RDPENDPRI_delay; +wire [0:1] PLBPPCS1REQPRI_delay; +wire [0:1] PLBPPCS1WRPENDPRI_delay; +wire [0:1] TIEC440DCURDLDCACHEPLBPRIO_delay; +wire [0:1] TIEC440DCURDNONCACHEPLBPRIO_delay; +wire [0:1] TIEC440DCURDTOUCHPLBPRIO_delay; +wire [0:1] TIEC440DCURDURGENTPLBPRIO_delay; +wire [0:1] TIEC440DCUWRFLUSHPLBPRIO_delay; +wire [0:1] TIEC440DCUWRSTOREPLBPRIO_delay; +wire [0:1] TIEC440DCUWRURGENTPLBPRIO_delay; +wire [0:1] TIEC440ICURDFETCHPLBPRIO_delay; +wire [0:1] TIEC440ICURDSPECPLBPRIO_delay; +wire [0:1] TIEC440ICURDTOUCHPLBPRIO_delay; +wire [0:1] TIEDCRBASEADDR_delay; +wire [0:2] PLBPPCS0TYPE_delay; +wire [0:2] PLBPPCS1TYPE_delay; +wire [0:31] DCRPPCDMDBUSIN_delay; +wire [0:31] DCRPPCDSDBUSOUT_delay; +wire [0:31] FCMAPURESULT_delay; +wire [0:31] LLDMA0RXD_delay; +wire [0:31] LLDMA1RXD_delay; +wire [0:31] LLDMA2RXD_delay; +wire [0:31] LLDMA3RXD_delay; +wire [0:31] PLBPPCS0ABUS_delay; +wire [0:31] PLBPPCS1ABUS_delay; +wire [0:3] FCMAPUCR_delay; +wire [0:3] LLDMA0RXREM_delay; +wire [0:3] LLDMA1RXREM_delay; +wire [0:3] LLDMA2RXREM_delay; +wire [0:3] LLDMA3RXREM_delay; +wire [0:3] PLBPPCMRDWDADDR_delay; +wire [0:3] PLBPPCS0SIZE_delay; +wire [0:3] PLBPPCS1SIZE_delay; +wire [0:3] TIEC440ERPNRESET_delay; +wire [0:3] TIEC440USERRESET_delay; +wire [0:4] DBGC440SYSTEMSTATUS_delay; +wire [0:9] DCRPPCDSABUS_delay; +wire [28:31] PLBPPCS0UABUS_delay; +wire [28:31] PLBPPCS1UABUS_delay; +wire [28:31] TIEC440PIR_delay; +wire [28:31] TIEC440PVR_delay; + + +assign #(out_delay) APUFCMDECFPUOP = APUFCMDECFPUOP_delay; +assign #(out_delay) APUFCMDECLDSTXFERSIZE = APUFCMDECLDSTXFERSIZE_delay; +assign #(out_delay) APUFCMDECLOAD = APUFCMDECLOAD_delay; +assign #(out_delay) APUFCMDECNONAUTON = APUFCMDECNONAUTON_delay; +assign #(out_delay) APUFCMDECSTORE = APUFCMDECSTORE_delay; +assign #(out_delay) APUFCMDECUDI = APUFCMDECUDI_delay; +assign #(out_delay) APUFCMDECUDIVALID = APUFCMDECUDIVALID_delay; +assign #(out_delay) APUFCMENDIAN = APUFCMENDIAN_delay; +assign #(out_delay) APUFCMFLUSH = APUFCMFLUSH_delay; +assign #(out_delay) APUFCMINSTRUCTION = APUFCMINSTRUCTION_delay; +assign #(out_delay) APUFCMINSTRVALID = APUFCMINSTRVALID_delay; +assign #(out_delay) APUFCMLOADBYTEADDR = APUFCMLOADBYTEADDR_delay; +assign #(out_delay) APUFCMLOADDATA = APUFCMLOADDATA_delay; +assign #(out_delay) APUFCMLOADDVALID = APUFCMLOADDVALID_delay; +assign #(out_delay) APUFCMMSRFE0 = APUFCMMSRFE0_delay; +assign #(out_delay) APUFCMMSRFE1 = APUFCMMSRFE1_delay; +assign #(out_delay) APUFCMNEXTINSTRREADY = APUFCMNEXTINSTRREADY_delay; +assign #(out_delay) APUFCMOPERANDVALID = APUFCMOPERANDVALID_delay; +assign #(out_delay) APUFCMRADATA = APUFCMRADATA_delay; +assign #(out_delay) APUFCMRBDATA = APUFCMRBDATA_delay; +assign #(out_delay) APUFCMWRITEBACKOK = APUFCMWRITEBACKOK_delay; +assign #(out_delay) C440CPMCORESLEEPREQ = C440CPMCORESLEEPREQ_delay; +assign #(out_delay) C440CPMDECIRPTREQ = C440CPMDECIRPTREQ_delay; +assign #(out_delay) C440CPMFITIRPTREQ = C440CPMFITIRPTREQ_delay; +assign #(out_delay) C440CPMMSRCE = C440CPMMSRCE_delay; +assign #(out_delay) C440CPMMSREE = C440CPMMSREE_delay; +assign #(out_delay) C440CPMTIMERRESETREQ = C440CPMTIMERRESETREQ_delay; +assign #(out_delay) C440CPMWDIRPTREQ = C440CPMWDIRPTREQ_delay; +assign #(out_delay) C440DBGSYSTEMCONTROL = C440DBGSYSTEMCONTROL_delay; +assign #(out_delay) C440JTGTDO = C440JTGTDO_delay; +assign #(out_delay) C440JTGTDOEN = C440JTGTDOEN_delay; +assign #(out_delay) C440MACHINECHECK = C440MACHINECHECK_delay; +assign #(out_delay) C440RSTCHIPRESETREQ = C440RSTCHIPRESETREQ_delay; +assign #(out_delay) C440RSTCORERESETREQ = C440RSTCORERESETREQ_delay; +assign #(out_delay) C440RSTSYSTEMRESETREQ = C440RSTSYSTEMRESETREQ_delay; +assign #(out_delay) C440TRCBRANCHSTATUS = C440TRCBRANCHSTATUS_delay; +assign #(out_delay) C440TRCCYCLE = C440TRCCYCLE_delay; +assign #(out_delay) C440TRCEXECUTIONSTATUS = C440TRCEXECUTIONSTATUS_delay; +assign #(out_delay) C440TRCTRACESTATUS = C440TRCTRACESTATUS_delay; +assign #(out_delay) C440TRCTRIGGEREVENTOUT = C440TRCTRIGGEREVENTOUT_delay; +assign #(out_delay) C440TRCTRIGGEREVENTTYPE = C440TRCTRIGGEREVENTTYPE_delay; +assign #(out_delay) DMA0LLRSTENGINEACK = DMA0LLRSTENGINEACK_delay; +assign #(out_delay) DMA0LLRXDSTRDYN = DMA0LLRXDSTRDYN_delay; +assign #(out_delay) DMA0LLTXD = DMA0LLTXD_delay; +assign #(out_delay) DMA0LLTXEOFN = DMA0LLTXEOFN_delay; +assign #(out_delay) DMA0LLTXEOPN = DMA0LLTXEOPN_delay; +assign #(out_delay) DMA0LLTXREM = DMA0LLTXREM_delay; +assign #(out_delay) DMA0LLTXSOFN = DMA0LLTXSOFN_delay; +assign #(out_delay) DMA0LLTXSOPN = DMA0LLTXSOPN_delay; +assign #(out_delay) DMA0LLTXSRCRDYN = DMA0LLTXSRCRDYN_delay; +assign #(out_delay) DMA0RXIRQ = DMA0RXIRQ_delay; +assign #(out_delay) DMA0TXIRQ = DMA0TXIRQ_delay; +assign #(out_delay) DMA1LLRSTENGINEACK = DMA1LLRSTENGINEACK_delay; +assign #(out_delay) DMA1LLRXDSTRDYN = DMA1LLRXDSTRDYN_delay; +assign #(out_delay) DMA1LLTXD = DMA1LLTXD_delay; +assign #(out_delay) DMA1LLTXEOFN = DMA1LLTXEOFN_delay; +assign #(out_delay) DMA1LLTXEOPN = DMA1LLTXEOPN_delay; +assign #(out_delay) DMA1LLTXREM = DMA1LLTXREM_delay; +assign #(out_delay) DMA1LLTXSOFN = DMA1LLTXSOFN_delay; +assign #(out_delay) DMA1LLTXSOPN = DMA1LLTXSOPN_delay; +assign #(out_delay) DMA1LLTXSRCRDYN = DMA1LLTXSRCRDYN_delay; +assign #(out_delay) DMA1RXIRQ = DMA1RXIRQ_delay; +assign #(out_delay) DMA1TXIRQ = DMA1TXIRQ_delay; +assign #(out_delay) DMA2LLRSTENGINEACK = DMA2LLRSTENGINEACK_delay; +assign #(out_delay) DMA2LLRXDSTRDYN = DMA2LLRXDSTRDYN_delay; +assign #(out_delay) DMA2LLTXD = DMA2LLTXD_delay; +assign #(out_delay) DMA2LLTXEOFN = DMA2LLTXEOFN_delay; +assign #(out_delay) DMA2LLTXEOPN = DMA2LLTXEOPN_delay; +assign #(out_delay) DMA2LLTXREM = DMA2LLTXREM_delay; +assign #(out_delay) DMA2LLTXSOFN = DMA2LLTXSOFN_delay; +assign #(out_delay) DMA2LLTXSOPN = DMA2LLTXSOPN_delay; +assign #(out_delay) DMA2LLTXSRCRDYN = DMA2LLTXSRCRDYN_delay; +assign #(out_delay) DMA2RXIRQ = DMA2RXIRQ_delay; +assign #(out_delay) DMA2TXIRQ = DMA2TXIRQ_delay; +assign #(out_delay) DMA3LLRSTENGINEACK = DMA3LLRSTENGINEACK_delay; +assign #(out_delay) DMA3LLRXDSTRDYN = DMA3LLRXDSTRDYN_delay; +assign #(out_delay) DMA3LLTXD = DMA3LLTXD_delay; +assign #(out_delay) DMA3LLTXEOFN = DMA3LLTXEOFN_delay; +assign #(out_delay) DMA3LLTXEOPN = DMA3LLTXEOPN_delay; +assign #(out_delay) DMA3LLTXREM = DMA3LLTXREM_delay; +assign #(out_delay) DMA3LLTXSOFN = DMA3LLTXSOFN_delay; +assign #(out_delay) DMA3LLTXSOPN = DMA3LLTXSOPN_delay; +assign #(out_delay) DMA3LLTXSRCRDYN = DMA3LLTXSRCRDYN_delay; +assign #(out_delay) DMA3RXIRQ = DMA3RXIRQ_delay; +assign #(out_delay) DMA3TXIRQ = DMA3TXIRQ_delay; +assign #(out_delay) MIMCADDRESS = MIMCADDRESS_delay; +assign #(out_delay) MIMCADDRESSVALID = MIMCADDRESSVALID_delay; +assign #(out_delay) MIMCBANKCONFLICT = MIMCBANKCONFLICT_delay; +assign #(out_delay) MIMCBYTEENABLE = MIMCBYTEENABLE_delay; +assign #(out_delay) MIMCREADNOTWRITE = MIMCREADNOTWRITE_delay; +assign #(out_delay) MIMCROWCONFLICT = MIMCROWCONFLICT_delay; +assign #(out_delay) MIMCWRITEDATA = MIMCWRITEDATA_delay; +assign #(out_delay) MIMCWRITEDATAVALID = MIMCWRITEDATAVALID_delay; +assign #(out_delay) PPCCPMINTERCONNECTBUSY = PPCCPMINTERCONNECTBUSY_delay; +assign #(out_delay) PPCDMDCRABUS = PPCDMDCRABUS_delay; +assign #(out_delay) PPCDMDCRDBUSOUT = PPCDMDCRDBUSOUT_delay; +assign #(out_delay) PPCDMDCRREAD = PPCDMDCRREAD_delay; +assign #(out_delay) PPCDMDCRUABUS = PPCDMDCRUABUS_delay; +assign #(out_delay) PPCDMDCRWRITE = PPCDMDCRWRITE_delay; +assign #(out_delay) PPCDSDCRACK = PPCDSDCRACK_delay; +assign #(out_delay) PPCDSDCRDBUSIN = PPCDSDCRDBUSIN_delay; +assign #(out_delay) PPCDSDCRTIMEOUTWAIT = PPCDSDCRTIMEOUTWAIT_delay; +assign #(out_delay) PPCEICINTERCONNECTIRQ = PPCEICINTERCONNECTIRQ_delay; +assign #(out_delay) PPCMPLBABORT = PPCMPLBABORT_delay; +assign #(out_delay) PPCMPLBABUS = PPCMPLBABUS_delay; +assign #(out_delay) PPCMPLBBE = PPCMPLBBE_delay; +assign #(out_delay) PPCMPLBBUSLOCK = PPCMPLBBUSLOCK_delay; +assign #(out_delay) PPCMPLBLOCKERR = PPCMPLBLOCKERR_delay; +assign #(out_delay) PPCMPLBPRIORITY = PPCMPLBPRIORITY_delay; +assign #(out_delay) PPCMPLBRDBURST = PPCMPLBRDBURST_delay; +assign #(out_delay) PPCMPLBREQUEST = PPCMPLBREQUEST_delay; +assign #(out_delay) PPCMPLBRNW = PPCMPLBRNW_delay; +assign #(out_delay) PPCMPLBSIZE = PPCMPLBSIZE_delay; +assign #(out_delay) PPCMPLBTATTRIBUTE = PPCMPLBTATTRIBUTE_delay; +assign #(out_delay) PPCMPLBTYPE = PPCMPLBTYPE_delay; +assign #(out_delay) PPCMPLBUABUS = PPCMPLBUABUS_delay; +assign #(out_delay) PPCMPLBWRBURST = PPCMPLBWRBURST_delay; +assign #(out_delay) PPCMPLBWRDBUS = PPCMPLBWRDBUS_delay; +assign #(out_delay) PPCS0PLBADDRACK = PPCS0PLBADDRACK_delay; +assign #(out_delay) PPCS0PLBMBUSY = PPCS0PLBMBUSY_delay; +assign #(out_delay) PPCS0PLBMIRQ = PPCS0PLBMIRQ_delay; +assign #(out_delay) PPCS0PLBMRDERR = PPCS0PLBMRDERR_delay; +assign #(out_delay) PPCS0PLBMWRERR = PPCS0PLBMWRERR_delay; +assign #(out_delay) PPCS0PLBRDBTERM = PPCS0PLBRDBTERM_delay; +assign #(out_delay) PPCS0PLBRDCOMP = PPCS0PLBRDCOMP_delay; +assign #(out_delay) PPCS0PLBRDDACK = PPCS0PLBRDDACK_delay; +assign #(out_delay) PPCS0PLBRDDBUS = PPCS0PLBRDDBUS_delay; +assign #(out_delay) PPCS0PLBRDWDADDR = PPCS0PLBRDWDADDR_delay; +assign #(out_delay) PPCS0PLBREARBITRATE = PPCS0PLBREARBITRATE_delay; +assign #(out_delay) PPCS0PLBSSIZE = PPCS0PLBSSIZE_delay; +assign #(out_delay) PPCS0PLBWAIT = PPCS0PLBWAIT_delay; +assign #(out_delay) PPCS0PLBWRBTERM = PPCS0PLBWRBTERM_delay; +assign #(out_delay) PPCS0PLBWRCOMP = PPCS0PLBWRCOMP_delay; +assign #(out_delay) PPCS0PLBWRDACK = PPCS0PLBWRDACK_delay; +assign #(out_delay) PPCS1PLBADDRACK = PPCS1PLBADDRACK_delay; +assign #(out_delay) PPCS1PLBMBUSY = PPCS1PLBMBUSY_delay; +assign #(out_delay) PPCS1PLBMIRQ = PPCS1PLBMIRQ_delay; +assign #(out_delay) PPCS1PLBMRDERR = PPCS1PLBMRDERR_delay; +assign #(out_delay) PPCS1PLBMWRERR = PPCS1PLBMWRERR_delay; +assign #(out_delay) PPCS1PLBRDBTERM = PPCS1PLBRDBTERM_delay; +assign #(out_delay) PPCS1PLBRDCOMP = PPCS1PLBRDCOMP_delay; +assign #(out_delay) PPCS1PLBRDDACK = PPCS1PLBRDDACK_delay; +assign #(out_delay) PPCS1PLBRDDBUS = PPCS1PLBRDDBUS_delay; +assign #(out_delay) PPCS1PLBRDWDADDR = PPCS1PLBRDWDADDR_delay; +assign #(out_delay) PPCS1PLBREARBITRATE = PPCS1PLBREARBITRATE_delay; +assign #(out_delay) PPCS1PLBSSIZE = PPCS1PLBSSIZE_delay; +assign #(out_delay) PPCS1PLBWAIT = PPCS1PLBWAIT_delay; +assign #(out_delay) PPCS1PLBWRBTERM = PPCS1PLBWRBTERM_delay; +assign #(out_delay) PPCS1PLBWRCOMP = PPCS1PLBWRCOMP_delay; +assign #(out_delay) PPCS1PLBWRDACK = PPCS1PLBWRDACK_delay; + +assign #(CLK_DELAY) CPMC440CLK_delay = CPMC440CLK; +assign #(CLK_DELAY) CPMC440TIMERCLOCK_delay = CPMC440TIMERCLOCK; +assign #(CLK_DELAY) CPMDCRCLK_delay = CPMDCRCLK; +assign #(CLK_DELAY) CPMDMA0LLCLK_delay = CPMDMA0LLCLK; +assign #(CLK_DELAY) CPMDMA1LLCLK_delay = CPMDMA1LLCLK; +assign #(CLK_DELAY) CPMDMA2LLCLK_delay = CPMDMA2LLCLK; +assign #(CLK_DELAY) CPMDMA3LLCLK_delay = CPMDMA3LLCLK; +assign #(CLK_DELAY) CPMFCMCLK_delay = CPMFCMCLK; +assign #(CLK_DELAY) CPMINTERCONNECTCLK_delay = CPMINTERCONNECTCLK; +assign #(CLK_DELAY) CPMMCCLK_delay = CPMMCCLK; +assign #(CLK_DELAY) CPMPPCMPLBCLK_delay = CPMPPCMPLBCLK; +assign #(CLK_DELAY) CPMPPCS0PLBCLK_delay = CPMPPCS0PLBCLK; +assign #(CLK_DELAY) CPMPPCS1PLBCLK_delay = CPMPPCS1PLBCLK; +assign #(CLK_DELAY) JTGC440TCK_delay = JTGC440TCK; + +assign #(in_delay) CPMC440CLKEN_delay = CPMC440CLKEN; +assign #(in_delay) CPMC440CORECLOCKINACTIVE_delay = CPMC440CORECLOCKINACTIVE; +assign #(in_delay) CPMINTERCONNECTCLKEN_delay = CPMINTERCONNECTCLKEN; +assign #(in_delay) CPMINTERCONNECTCLKNTO1_delay = CPMINTERCONNECTCLKNTO1; +assign #(in_delay) DBGC440DEBUGHALT_delay = DBGC440DEBUGHALT; +assign #(in_delay) DBGC440SYSTEMSTATUS_delay = DBGC440SYSTEMSTATUS; +assign #(in_delay) DBGC440UNCONDDEBUGEVENT_delay = DBGC440UNCONDDEBUGEVENT; +assign #(in_delay) DCRPPCDMACK_delay = DCRPPCDMACK; +assign #(in_delay) DCRPPCDMDBUSIN_delay = DCRPPCDMDBUSIN; +assign #(in_delay) DCRPPCDMTIMEOUTWAIT_delay = DCRPPCDMTIMEOUTWAIT; +assign #(in_delay) DCRPPCDSABUS_delay = DCRPPCDSABUS; +assign #(in_delay) DCRPPCDSDBUSOUT_delay = DCRPPCDSDBUSOUT; +assign #(in_delay) DCRPPCDSREAD_delay = DCRPPCDSREAD; +assign #(in_delay) DCRPPCDSWRITE_delay = DCRPPCDSWRITE; +assign #(in_delay) EICC440CRITIRQ_delay = EICC440CRITIRQ; +assign #(in_delay) EICC440EXTIRQ_delay = EICC440EXTIRQ; +assign #(in_delay) FCMAPUCONFIRMINSTR_delay = FCMAPUCONFIRMINSTR; +assign #(in_delay) FCMAPUCR_delay = FCMAPUCR; +assign #(in_delay) FCMAPUDONE_delay = FCMAPUDONE; +assign #(in_delay) FCMAPUEXCEPTION_delay = FCMAPUEXCEPTION; +assign #(in_delay) FCMAPUFPSCRFEX_delay = FCMAPUFPSCRFEX; +assign #(in_delay) FCMAPURESULTVALID_delay = FCMAPURESULTVALID; +assign #(in_delay) FCMAPURESULT_delay = FCMAPURESULT; +assign #(in_delay) FCMAPUSLEEPNOTREADY_delay = FCMAPUSLEEPNOTREADY; +assign #(in_delay) FCMAPUSTOREDATA_delay = FCMAPUSTOREDATA; +assign #(in_delay) JTGC440TDI_delay = JTGC440TDI; +assign #(in_delay) JTGC440TMS_delay = JTGC440TMS; +assign #(in_delay) JTGC440TRSTNEG_delay = JTGC440TRSTNEG; +assign #(in_delay) LLDMA0RSTENGINEREQ_delay = LLDMA0RSTENGINEREQ; +assign #(in_delay) LLDMA0RXD_delay = LLDMA0RXD; +assign #(in_delay) LLDMA0RXEOFN_delay = LLDMA0RXEOFN; +assign #(in_delay) LLDMA0RXEOPN_delay = LLDMA0RXEOPN; +assign #(in_delay) LLDMA0RXREM_delay = LLDMA0RXREM; +assign #(in_delay) LLDMA0RXSOFN_delay = LLDMA0RXSOFN; +assign #(in_delay) LLDMA0RXSOPN_delay = LLDMA0RXSOPN; +assign #(in_delay) LLDMA0RXSRCRDYN_delay = LLDMA0RXSRCRDYN; +assign #(in_delay) LLDMA0TXDSTRDYN_delay = LLDMA0TXDSTRDYN; +assign #(in_delay) LLDMA1RSTENGINEREQ_delay = LLDMA1RSTENGINEREQ; +assign #(in_delay) LLDMA1RXD_delay = LLDMA1RXD; +assign #(in_delay) LLDMA1RXEOFN_delay = LLDMA1RXEOFN; +assign #(in_delay) LLDMA1RXEOPN_delay = LLDMA1RXEOPN; +assign #(in_delay) LLDMA1RXREM_delay = LLDMA1RXREM; +assign #(in_delay) LLDMA1RXSOFN_delay = LLDMA1RXSOFN; +assign #(in_delay) LLDMA1RXSOPN_delay = LLDMA1RXSOPN; +assign #(in_delay) LLDMA1RXSRCRDYN_delay = LLDMA1RXSRCRDYN; +assign #(in_delay) LLDMA1TXDSTRDYN_delay = LLDMA1TXDSTRDYN; +assign #(in_delay) LLDMA2RSTENGINEREQ_delay = LLDMA2RSTENGINEREQ; +assign #(in_delay) LLDMA2RXD_delay = LLDMA2RXD; +assign #(in_delay) LLDMA2RXEOFN_delay = LLDMA2RXEOFN; +assign #(in_delay) LLDMA2RXEOPN_delay = LLDMA2RXEOPN; +assign #(in_delay) LLDMA2RXREM_delay = LLDMA2RXREM; +assign #(in_delay) LLDMA2RXSOFN_delay = LLDMA2RXSOFN; +assign #(in_delay) LLDMA2RXSOPN_delay = LLDMA2RXSOPN; +assign #(in_delay) LLDMA2RXSRCRDYN_delay = LLDMA2RXSRCRDYN; +assign #(in_delay) LLDMA2TXDSTRDYN_delay = LLDMA2TXDSTRDYN; +assign #(in_delay) LLDMA3RSTENGINEREQ_delay = LLDMA3RSTENGINEREQ; +assign #(in_delay) LLDMA3RXD_delay = LLDMA3RXD; +assign #(in_delay) LLDMA3RXEOFN_delay = LLDMA3RXEOFN; +assign #(in_delay) LLDMA3RXEOPN_delay = LLDMA3RXEOPN; +assign #(in_delay) LLDMA3RXREM_delay = LLDMA3RXREM; +assign #(in_delay) LLDMA3RXSOFN_delay = LLDMA3RXSOFN; +assign #(in_delay) LLDMA3RXSOPN_delay = LLDMA3RXSOPN; +assign #(in_delay) LLDMA3RXSRCRDYN_delay = LLDMA3RXSRCRDYN; +assign #(in_delay) LLDMA3TXDSTRDYN_delay = LLDMA3TXDSTRDYN; +assign #(in_delay) MCMIADDRREADYTOACCEPT_delay = MCMIADDRREADYTOACCEPT; +assign #(in_delay) MCMIREADDATAERR_delay = MCMIREADDATAERR; +assign #(in_delay) MCMIREADDATAVALID_delay = MCMIREADDATAVALID; +assign #(in_delay) MCMIREADDATA_delay = MCMIREADDATA; +assign #(in_delay) PLBPPCMADDRACK_delay = PLBPPCMADDRACK; +assign #(in_delay) PLBPPCMMBUSY_delay = PLBPPCMMBUSY; +assign #(in_delay) PLBPPCMMIRQ_delay = PLBPPCMMIRQ; +assign #(in_delay) PLBPPCMMRDERR_delay = PLBPPCMMRDERR; +assign #(in_delay) PLBPPCMMWRERR_delay = PLBPPCMMWRERR; +assign #(in_delay) PLBPPCMRDBTERM_delay = PLBPPCMRDBTERM; +assign #(in_delay) PLBPPCMRDDACK_delay = PLBPPCMRDDACK; +assign #(in_delay) PLBPPCMRDDBUS_delay = PLBPPCMRDDBUS; +assign #(in_delay) PLBPPCMRDPENDPRI_delay = PLBPPCMRDPENDPRI; +assign #(in_delay) PLBPPCMRDPENDREQ_delay = PLBPPCMRDPENDREQ; +assign #(in_delay) PLBPPCMRDWDADDR_delay = PLBPPCMRDWDADDR; +assign #(in_delay) PLBPPCMREARBITRATE_delay = PLBPPCMREARBITRATE; +assign #(in_delay) PLBPPCMREQPRI_delay = PLBPPCMREQPRI; +assign #(in_delay) PLBPPCMSSIZE_delay = PLBPPCMSSIZE; +assign #(in_delay) PLBPPCMTIMEOUT_delay = PLBPPCMTIMEOUT; +assign #(in_delay) PLBPPCMWRBTERM_delay = PLBPPCMWRBTERM; +assign #(in_delay) PLBPPCMWRDACK_delay = PLBPPCMWRDACK; +assign #(in_delay) PLBPPCMWRPENDPRI_delay = PLBPPCMWRPENDPRI; +assign #(in_delay) PLBPPCMWRPENDREQ_delay = PLBPPCMWRPENDREQ; +assign #(in_delay) PLBPPCS0ABORT_delay = PLBPPCS0ABORT; +assign #(in_delay) PLBPPCS0ABUS_delay = PLBPPCS0ABUS; +assign #(in_delay) PLBPPCS0BE_delay = PLBPPCS0BE; +assign #(in_delay) PLBPPCS0BUSLOCK_delay = PLBPPCS0BUSLOCK; +assign #(in_delay) PLBPPCS0LOCKERR_delay = PLBPPCS0LOCKERR; +assign #(in_delay) PLBPPCS0MASTERID_delay = PLBPPCS0MASTERID; +assign #(in_delay) PLBPPCS0MSIZE_delay = PLBPPCS0MSIZE; +assign #(in_delay) PLBPPCS0PAVALID_delay = PLBPPCS0PAVALID; +assign #(in_delay) PLBPPCS0RDBURST_delay = PLBPPCS0RDBURST; +assign #(in_delay) PLBPPCS0RDPENDPRI_delay = PLBPPCS0RDPENDPRI; +assign #(in_delay) PLBPPCS0RDPENDREQ_delay = PLBPPCS0RDPENDREQ; +assign #(in_delay) PLBPPCS0RDPRIM_delay = PLBPPCS0RDPRIM; +assign #(in_delay) PLBPPCS0REQPRI_delay = PLBPPCS0REQPRI; +assign #(in_delay) PLBPPCS0RNW_delay = PLBPPCS0RNW; +assign #(in_delay) PLBPPCS0SAVALID_delay = PLBPPCS0SAVALID; +assign #(in_delay) PLBPPCS0SIZE_delay = PLBPPCS0SIZE; +assign #(in_delay) PLBPPCS0TATTRIBUTE_delay = PLBPPCS0TATTRIBUTE; +assign #(in_delay) PLBPPCS0TYPE_delay = PLBPPCS0TYPE; +assign #(in_delay) PLBPPCS0UABUS_delay = PLBPPCS0UABUS; +assign #(in_delay) PLBPPCS0WRBURST_delay = PLBPPCS0WRBURST; +assign #(in_delay) PLBPPCS0WRDBUS_delay = PLBPPCS0WRDBUS; +assign #(in_delay) PLBPPCS0WRPENDPRI_delay = PLBPPCS0WRPENDPRI; +assign #(in_delay) PLBPPCS0WRPENDREQ_delay = PLBPPCS0WRPENDREQ; +assign #(in_delay) PLBPPCS0WRPRIM_delay = PLBPPCS0WRPRIM; +assign #(in_delay) PLBPPCS1ABORT_delay = PLBPPCS1ABORT; +assign #(in_delay) PLBPPCS1ABUS_delay = PLBPPCS1ABUS; +assign #(in_delay) PLBPPCS1BE_delay = PLBPPCS1BE; +assign #(in_delay) PLBPPCS1BUSLOCK_delay = PLBPPCS1BUSLOCK; +assign #(in_delay) PLBPPCS1LOCKERR_delay = PLBPPCS1LOCKERR; +assign #(in_delay) PLBPPCS1MASTERID_delay = PLBPPCS1MASTERID; +assign #(in_delay) PLBPPCS1MSIZE_delay = PLBPPCS1MSIZE; +assign #(in_delay) PLBPPCS1PAVALID_delay = PLBPPCS1PAVALID; +assign #(in_delay) PLBPPCS1RDBURST_delay = PLBPPCS1RDBURST; +assign #(in_delay) PLBPPCS1RDPENDPRI_delay = PLBPPCS1RDPENDPRI; +assign #(in_delay) PLBPPCS1RDPENDREQ_delay = PLBPPCS1RDPENDREQ; +assign #(in_delay) PLBPPCS1RDPRIM_delay = PLBPPCS1RDPRIM; +assign #(in_delay) PLBPPCS1REQPRI_delay = PLBPPCS1REQPRI; +assign #(in_delay) PLBPPCS1RNW_delay = PLBPPCS1RNW; +assign #(in_delay) PLBPPCS1SAVALID_delay = PLBPPCS1SAVALID; +assign #(in_delay) PLBPPCS1SIZE_delay = PLBPPCS1SIZE; +assign #(in_delay) PLBPPCS1TATTRIBUTE_delay = PLBPPCS1TATTRIBUTE; +assign #(in_delay) PLBPPCS1TYPE_delay = PLBPPCS1TYPE; +assign #(in_delay) PLBPPCS1UABUS_delay = PLBPPCS1UABUS; +assign #(in_delay) PLBPPCS1WRBURST_delay = PLBPPCS1WRBURST; +assign #(in_delay) PLBPPCS1WRDBUS_delay = PLBPPCS1WRDBUS; +assign #(in_delay) PLBPPCS1WRPENDPRI_delay = PLBPPCS1WRPENDPRI; +assign #(in_delay) PLBPPCS1WRPENDREQ_delay = PLBPPCS1WRPENDREQ; +assign #(in_delay) PLBPPCS1WRPRIM_delay = PLBPPCS1WRPRIM; +assign #(in_delay) RSTC440RESETCHIP_delay = RSTC440RESETCHIP; +assign #(in_delay) RSTC440RESETCORE_delay = RSTC440RESETCORE; +assign #(in_delay) RSTC440RESETSYSTEM_delay = RSTC440RESETSYSTEM; +assign #(in_delay) TIEC440DCURDLDCACHEPLBPRIO_delay = TIEC440DCURDLDCACHEPLBPRIO; +assign #(in_delay) TIEC440DCURDNONCACHEPLBPRIO_delay = TIEC440DCURDNONCACHEPLBPRIO; +assign #(in_delay) TIEC440DCURDTOUCHPLBPRIO_delay = TIEC440DCURDTOUCHPLBPRIO; +assign #(in_delay) TIEC440DCURDURGENTPLBPRIO_delay = TIEC440DCURDURGENTPLBPRIO; +assign #(in_delay) TIEC440DCUWRFLUSHPLBPRIO_delay = TIEC440DCUWRFLUSHPLBPRIO; +assign #(in_delay) TIEC440DCUWRSTOREPLBPRIO_delay = TIEC440DCUWRSTOREPLBPRIO; +assign #(in_delay) TIEC440DCUWRURGENTPLBPRIO_delay = TIEC440DCUWRURGENTPLBPRIO; +assign #(in_delay) TIEC440ENDIANRESET_delay = TIEC440ENDIANRESET; +assign #(in_delay) TIEC440ERPNRESET_delay = TIEC440ERPNRESET; +assign #(in_delay) TIEC440ICURDFETCHPLBPRIO_delay = TIEC440ICURDFETCHPLBPRIO; +assign #(in_delay) TIEC440ICURDSPECPLBPRIO_delay = TIEC440ICURDSPECPLBPRIO; +assign #(in_delay) TIEC440ICURDTOUCHPLBPRIO_delay = TIEC440ICURDTOUCHPLBPRIO; +assign #(in_delay) TIEC440PIR_delay = TIEC440PIR; +assign #(in_delay) TIEC440PVR_delay = TIEC440PVR; +assign #(in_delay) TIEC440USERRESET_delay = TIEC440USERRESET; +assign #(in_delay) TIEDCRBASEADDR_delay = TIEDCRBASEADDR; +assign #(in_delay) TRCC440TRACEDISABLE_delay = TRCC440TRACEDISABLE; +assign #(in_delay) TRCC440TRIGGEREVENTIN_delay = TRCC440TRIGGEREVENTIN; + +PPC440_SWIFT ppc440_swift_1 ( + .APU_CONTROL (APU_CONTROL), + .APU_UDI0 (APU_UDI0), + .APU_UDI1 (APU_UDI1), + .APU_UDI10 (APU_UDI10), + .APU_UDI11 (APU_UDI11), + .APU_UDI12 (APU_UDI12), + .APU_UDI13 (APU_UDI13), + .APU_UDI14 (APU_UDI14), + .APU_UDI15 (APU_UDI15), + .APU_UDI2 (APU_UDI2), + .APU_UDI3 (APU_UDI3), + .APU_UDI4 (APU_UDI4), + .APU_UDI5 (APU_UDI5), + .APU_UDI6 (APU_UDI6), + .APU_UDI7 (APU_UDI7), + .APU_UDI8 (APU_UDI8), + .APU_UDI9 (APU_UDI9), + .CLOCK_DELAY (CLOCK_DELAY_BINARY), + .DCR_AUTOLOCK_ENABLE (DCR_AUTOLOCK_ENABLE_BINARY), + .DMA0_CONTROL (DMA0_CONTROL), + .DMA0_RXCHANNELCTRL (DMA0_RXCHANNELCTRL), + .DMA0_RXIRQTIMER (DMA0_RXIRQTIMER), + .DMA0_TXCHANNELCTRL (DMA0_TXCHANNELCTRL), + .DMA0_TXIRQTIMER (DMA0_TXIRQTIMER), + .DMA1_CONTROL (DMA1_CONTROL), + .DMA1_RXCHANNELCTRL (DMA1_RXCHANNELCTRL), + .DMA1_RXIRQTIMER (DMA1_RXIRQTIMER), + .DMA1_TXCHANNELCTRL (DMA1_TXCHANNELCTRL), + .DMA1_TXIRQTIMER (DMA1_TXIRQTIMER), + .DMA2_CONTROL (DMA2_CONTROL), + .DMA2_RXCHANNELCTRL (DMA2_RXCHANNELCTRL), + .DMA2_RXIRQTIMER (DMA2_RXIRQTIMER), + .DMA2_TXCHANNELCTRL (DMA2_TXCHANNELCTRL), + .DMA2_TXIRQTIMER (DMA2_TXIRQTIMER), + .DMA3_CONTROL (DMA3_CONTROL), + .DMA3_RXCHANNELCTRL (DMA3_RXCHANNELCTRL), + .DMA3_RXIRQTIMER (DMA3_RXIRQTIMER), + .DMA3_TXCHANNELCTRL (DMA3_TXCHANNELCTRL), + .DMA3_TXIRQTIMER (DMA3_TXIRQTIMER), + .INTERCONNECT_IMASK (INTERCONNECT_IMASK), + .INTERCONNECT_TMPL_SEL (INTERCONNECT_TMPL_SEL), + .MI_ARBCONFIG (MI_ARBCONFIG), + .MI_BANKCONFLICT_MASK (MI_BANKCONFLICT_MASK), + .MI_CONTROL (MI_CONTROL), + .MI_ROWCONFLICT_MASK (MI_ROWCONFLICT_MASK), + .PPCDM_ASYNCMODE (PPCDM_ASYNCMODE_BINARY), + .PPCDS_ASYNCMODE (PPCDS_ASYNCMODE_BINARY), + .PPCM_ARBCONFIG (PPCM_ARBCONFIG), + .PPCM_CONTROL (PPCM_CONTROL), + .PPCM_COUNTER (PPCM_COUNTER), + .PPCS0_ADDRMAP_TMPL0 (PPCS0_ADDRMAP_TMPL0), + .PPCS0_ADDRMAP_TMPL1 (PPCS0_ADDRMAP_TMPL1), + .PPCS0_ADDRMAP_TMPL2 (PPCS0_ADDRMAP_TMPL2), + .PPCS0_ADDRMAP_TMPL3 (PPCS0_ADDRMAP_TMPL3), + .PPCS0_CONTROL (PPCS0_CONTROL), + .PPCS0_WIDTH_128N64 (PPCS0_WIDTH_128N64_BINARY), + .PPCS1_ADDRMAP_TMPL0 (PPCS1_ADDRMAP_TMPL0), + .PPCS1_ADDRMAP_TMPL1 (PPCS1_ADDRMAP_TMPL1), + .PPCS1_ADDRMAP_TMPL2 (PPCS1_ADDRMAP_TMPL2), + .PPCS1_ADDRMAP_TMPL3 (PPCS1_ADDRMAP_TMPL3), + .PPCS1_CONTROL (PPCS1_CONTROL), + .PPCS1_WIDTH_128N64 (PPCS1_WIDTH_128N64_BINARY), + .XBAR_ADDRMAP_TMPL0 (XBAR_ADDRMAP_TMPL0), + .XBAR_ADDRMAP_TMPL1 (XBAR_ADDRMAP_TMPL1), + .XBAR_ADDRMAP_TMPL2 (XBAR_ADDRMAP_TMPL2), + .XBAR_ADDRMAP_TMPL3 (XBAR_ADDRMAP_TMPL3), + + .APUFCMDECFPUOP (APUFCMDECFPUOP_delay), + .APUFCMDECLDSTXFERSIZE (APUFCMDECLDSTXFERSIZE_delay), + .APUFCMDECLOAD (APUFCMDECLOAD_delay), + .APUFCMDECNONAUTON (APUFCMDECNONAUTON_delay), + .APUFCMDECSTORE (APUFCMDECSTORE_delay), + .APUFCMDECUDI (APUFCMDECUDI_delay), + .APUFCMDECUDIVALID (APUFCMDECUDIVALID_delay), + .APUFCMENDIAN (APUFCMENDIAN_delay), + .APUFCMFLUSH (APUFCMFLUSH_delay), + .APUFCMINSTRUCTION (APUFCMINSTRUCTION_delay), + .APUFCMINSTRVALID (APUFCMINSTRVALID_delay), + .APUFCMLOADBYTEADDR (APUFCMLOADBYTEADDR_delay), + .APUFCMLOADDATA (APUFCMLOADDATA_delay), + .APUFCMLOADDVALID (APUFCMLOADDVALID_delay), + .APUFCMMSRFE0 (APUFCMMSRFE0_delay), + .APUFCMMSRFE1 (APUFCMMSRFE1_delay), + .APUFCMNEXTINSTRREADY (APUFCMNEXTINSTRREADY_delay), + .APUFCMOPERANDVALID (APUFCMOPERANDVALID_delay), + .APUFCMRADATA (APUFCMRADATA_delay), + .APUFCMRBDATA (APUFCMRBDATA_delay), + .APUFCMWRITEBACKOK (APUFCMWRITEBACKOK_delay), + .C440CPMCORESLEEPREQ (C440CPMCORESLEEPREQ_delay), + .C440CPMDECIRPTREQ (C440CPMDECIRPTREQ_delay), + .C440CPMFITIRPTREQ (C440CPMFITIRPTREQ_delay), + .C440CPMMSRCE (C440CPMMSRCE_delay), + .C440CPMMSREE (C440CPMMSREE_delay), + .C440CPMTIMERRESETREQ (C440CPMTIMERRESETREQ_delay), + .C440CPMWDIRPTREQ (C440CPMWDIRPTREQ_delay), + .C440DBGSYSTEMCONTROL (C440DBGSYSTEMCONTROL_delay), + .C440JTGTDO (C440JTGTDO_delay), + .C440JTGTDOEN (C440JTGTDOEN_delay), + .C440MACHINECHECK (C440MACHINECHECK_delay), + .C440RSTCHIPRESETREQ (C440RSTCHIPRESETREQ_delay), + .C440RSTCORERESETREQ (C440RSTCORERESETREQ_delay), + .C440RSTSYSTEMRESETREQ (C440RSTSYSTEMRESETREQ_delay), + .C440TRCBRANCHSTATUS (C440TRCBRANCHSTATUS_delay), + .C440TRCCYCLE (C440TRCCYCLE_delay), + .C440TRCEXECUTIONSTATUS (C440TRCEXECUTIONSTATUS_delay), + .C440TRCTRACESTATUS (C440TRCTRACESTATUS_delay), + .C440TRCTRIGGEREVENTOUT (C440TRCTRIGGEREVENTOUT_delay), + .C440TRCTRIGGEREVENTTYPE (C440TRCTRIGGEREVENTTYPE_delay), + .DMA0LLRSTENGINEACK (DMA0LLRSTENGINEACK_delay), + .DMA0LLRXDSTRDYN (DMA0LLRXDSTRDYN_delay), + .DMA0LLTXD (DMA0LLTXD_delay), + .DMA0LLTXEOFN (DMA0LLTXEOFN_delay), + .DMA0LLTXEOPN (DMA0LLTXEOPN_delay), + .DMA0LLTXREM (DMA0LLTXREM_delay), + .DMA0LLTXSOFN (DMA0LLTXSOFN_delay), + .DMA0LLTXSOPN (DMA0LLTXSOPN_delay), + .DMA0LLTXSRCRDYN (DMA0LLTXSRCRDYN_delay), + .DMA0RXIRQ (DMA0RXIRQ_delay), + .DMA0TXIRQ (DMA0TXIRQ_delay), + .DMA1LLRSTENGINEACK (DMA1LLRSTENGINEACK_delay), + .DMA1LLRXDSTRDYN (DMA1LLRXDSTRDYN_delay), + .DMA1LLTXD (DMA1LLTXD_delay), + .DMA1LLTXEOFN (DMA1LLTXEOFN_delay), + .DMA1LLTXEOPN (DMA1LLTXEOPN_delay), + .DMA1LLTXREM (DMA1LLTXREM_delay), + .DMA1LLTXSOFN (DMA1LLTXSOFN_delay), + .DMA1LLTXSOPN (DMA1LLTXSOPN_delay), + .DMA1LLTXSRCRDYN (DMA1LLTXSRCRDYN_delay), + .DMA1RXIRQ (DMA1RXIRQ_delay), + .DMA1TXIRQ (DMA1TXIRQ_delay), + .DMA2LLRSTENGINEACK (DMA2LLRSTENGINEACK_delay), + .DMA2LLRXDSTRDYN (DMA2LLRXDSTRDYN_delay), + .DMA2LLTXD (DMA2LLTXD_delay), + .DMA2LLTXEOFN (DMA2LLTXEOFN_delay), + .DMA2LLTXEOPN (DMA2LLTXEOPN_delay), + .DMA2LLTXREM (DMA2LLTXREM_delay), + .DMA2LLTXSOFN (DMA2LLTXSOFN_delay), + .DMA2LLTXSOPN (DMA2LLTXSOPN_delay), + .DMA2LLTXSRCRDYN (DMA2LLTXSRCRDYN_delay), + .DMA2RXIRQ (DMA2RXIRQ_delay), + .DMA2TXIRQ (DMA2TXIRQ_delay), + .DMA3LLRSTENGINEACK (DMA3LLRSTENGINEACK_delay), + .DMA3LLRXDSTRDYN (DMA3LLRXDSTRDYN_delay), + .DMA3LLTXD (DMA3LLTXD_delay), + .DMA3LLTXEOFN (DMA3LLTXEOFN_delay), + .DMA3LLTXEOPN (DMA3LLTXEOPN_delay), + .DMA3LLTXREM (DMA3LLTXREM_delay), + .DMA3LLTXSOFN (DMA3LLTXSOFN_delay), + .DMA3LLTXSOPN (DMA3LLTXSOPN_delay), + .DMA3LLTXSRCRDYN (DMA3LLTXSRCRDYN_delay), + .DMA3RXIRQ (DMA3RXIRQ_delay), + .DMA3TXIRQ (DMA3TXIRQ_delay), + .MIMCADDRESS (MIMCADDRESS_delay), + .MIMCADDRESSVALID (MIMCADDRESSVALID_delay), + .MIMCBANKCONFLICT (MIMCBANKCONFLICT_delay), + .MIMCBYTEENABLE (MIMCBYTEENABLE_delay), + .MIMCREADNOTWRITE (MIMCREADNOTWRITE_delay), + .MIMCROWCONFLICT (MIMCROWCONFLICT_delay), + .MIMCWRITEDATA (MIMCWRITEDATA_delay), + .MIMCWRITEDATAVALID (MIMCWRITEDATAVALID_delay), + .PPCCPMINTERCONNECTBUSY (PPCCPMINTERCONNECTBUSY_delay), + .PPCDMDCRABUS (PPCDMDCRABUS_delay), + .PPCDMDCRDBUSOUT (PPCDMDCRDBUSOUT_delay), + .PPCDMDCRREAD (PPCDMDCRREAD_delay), + .PPCDMDCRUABUS (PPCDMDCRUABUS_delay), + .PPCDMDCRWRITE (PPCDMDCRWRITE_delay), + .PPCDSDCRACK (PPCDSDCRACK_delay), + .PPCDSDCRDBUSIN (PPCDSDCRDBUSIN_delay), + .PPCDSDCRTIMEOUTWAIT (PPCDSDCRTIMEOUTWAIT_delay), + .PPCEICINTERCONNECTIRQ (PPCEICINTERCONNECTIRQ_delay), + .PPCMPLBABORT (PPCMPLBABORT_delay), + .PPCMPLBABUS (PPCMPLBABUS_delay), + .PPCMPLBBE (PPCMPLBBE_delay), + .PPCMPLBBUSLOCK (PPCMPLBBUSLOCK_delay), + .PPCMPLBLOCKERR (PPCMPLBLOCKERR_delay), + .PPCMPLBPRIORITY (PPCMPLBPRIORITY_delay), + .PPCMPLBRDBURST (PPCMPLBRDBURST_delay), + .PPCMPLBREQUEST (PPCMPLBREQUEST_delay), + .PPCMPLBRNW (PPCMPLBRNW_delay), + .PPCMPLBSIZE (PPCMPLBSIZE_delay), + .PPCMPLBTATTRIBUTE (PPCMPLBTATTRIBUTE_delay), + .PPCMPLBTYPE (PPCMPLBTYPE_delay), + .PPCMPLBUABUS (PPCMPLBUABUS_delay), + .PPCMPLBWRBURST (PPCMPLBWRBURST_delay), + .PPCMPLBWRDBUS (PPCMPLBWRDBUS_delay), + .PPCS0PLBADDRACK (PPCS0PLBADDRACK_delay), + .PPCS0PLBMBUSY (PPCS0PLBMBUSY_delay), + .PPCS0PLBMIRQ (PPCS0PLBMIRQ_delay), + .PPCS0PLBMRDERR (PPCS0PLBMRDERR_delay), + .PPCS0PLBMWRERR (PPCS0PLBMWRERR_delay), + .PPCS0PLBRDBTERM (PPCS0PLBRDBTERM_delay), + .PPCS0PLBRDCOMP (PPCS0PLBRDCOMP_delay), + .PPCS0PLBRDDACK (PPCS0PLBRDDACK_delay), + .PPCS0PLBRDDBUS (PPCS0PLBRDDBUS_delay), + .PPCS0PLBRDWDADDR (PPCS0PLBRDWDADDR_delay), + .PPCS0PLBREARBITRATE (PPCS0PLBREARBITRATE_delay), + .PPCS0PLBSSIZE (PPCS0PLBSSIZE_delay), + .PPCS0PLBWAIT (PPCS0PLBWAIT_delay), + .PPCS0PLBWRBTERM (PPCS0PLBWRBTERM_delay), + .PPCS0PLBWRCOMP (PPCS0PLBWRCOMP_delay), + .PPCS0PLBWRDACK (PPCS0PLBWRDACK_delay), + .PPCS1PLBADDRACK (PPCS1PLBADDRACK_delay), + .PPCS1PLBMBUSY (PPCS1PLBMBUSY_delay), + .PPCS1PLBMIRQ (PPCS1PLBMIRQ_delay), + .PPCS1PLBMRDERR (PPCS1PLBMRDERR_delay), + .PPCS1PLBMWRERR (PPCS1PLBMWRERR_delay), + .PPCS1PLBRDBTERM (PPCS1PLBRDBTERM_delay), + .PPCS1PLBRDCOMP (PPCS1PLBRDCOMP_delay), + .PPCS1PLBRDDACK (PPCS1PLBRDDACK_delay), + .PPCS1PLBRDDBUS (PPCS1PLBRDDBUS_delay), + .PPCS1PLBRDWDADDR (PPCS1PLBRDWDADDR_delay), + .PPCS1PLBREARBITRATE (PPCS1PLBREARBITRATE_delay), + .PPCS1PLBSSIZE (PPCS1PLBSSIZE_delay), + .PPCS1PLBWAIT (PPCS1PLBWAIT_delay), + .PPCS1PLBWRBTERM (PPCS1PLBWRBTERM_delay), + .PPCS1PLBWRCOMP (PPCS1PLBWRCOMP_delay), + .PPCS1PLBWRDACK (PPCS1PLBWRDACK_delay), + + .CPMC440CLK (CPMC440CLK_delay), + .CPMC440CLKEN (CPMC440CLKEN_delay), + .CPMC440CORECLOCKINACTIVE (CPMC440CORECLOCKINACTIVE_delay), + .CPMC440TIMERCLOCK (CPMC440TIMERCLOCK_delay), + .CPMDCRCLK (CPMDCRCLK_delay), + .CPMDMA0LLCLK (CPMDMA0LLCLK_delay), + .CPMDMA1LLCLK (CPMDMA1LLCLK_delay), + .CPMDMA2LLCLK (CPMDMA2LLCLK_delay), + .CPMDMA3LLCLK (CPMDMA3LLCLK_delay), + .CPMFCMCLK (CPMFCMCLK_delay), + .CPMINTERCONNECTCLK (CPMINTERCONNECTCLK_delay), + .CPMINTERCONNECTCLKEN (CPMINTERCONNECTCLKEN_delay), + .CPMINTERCONNECTCLKNTO1 (CPMINTERCONNECTCLKNTO1_delay), + .CPMMCCLK (CPMMCCLK_delay), + .CPMPPCMPLBCLK (CPMPPCMPLBCLK_delay), + .CPMPPCS0PLBCLK (CPMPPCS0PLBCLK_delay), + .CPMPPCS1PLBCLK (CPMPPCS1PLBCLK_delay), + .DBGC440DEBUGHALT (DBGC440DEBUGHALT_delay), + .DBGC440SYSTEMSTATUS (DBGC440SYSTEMSTATUS_delay), + .DBGC440UNCONDDEBUGEVENT (DBGC440UNCONDDEBUGEVENT_delay), + .DCRPPCDMACK (DCRPPCDMACK_delay), + .DCRPPCDMDBUSIN (DCRPPCDMDBUSIN_delay), + .DCRPPCDMTIMEOUTWAIT (DCRPPCDMTIMEOUTWAIT_delay), + .DCRPPCDSABUS (DCRPPCDSABUS_delay), + .DCRPPCDSDBUSOUT (DCRPPCDSDBUSOUT_delay), + .DCRPPCDSREAD (DCRPPCDSREAD_delay), + .DCRPPCDSWRITE (DCRPPCDSWRITE_delay), + .EICC440CRITIRQ (EICC440CRITIRQ_delay), + .EICC440EXTIRQ (EICC440EXTIRQ_delay), + .FCMAPUCONFIRMINSTR (FCMAPUCONFIRMINSTR_delay), + .FCMAPUCR (FCMAPUCR_delay), + .FCMAPUDONE (FCMAPUDONE_delay), + .FCMAPUEXCEPTION (FCMAPUEXCEPTION_delay), + .FCMAPUFPSCRFEX (FCMAPUFPSCRFEX_delay), + .FCMAPURESULT (FCMAPURESULT_delay), + .FCMAPURESULTVALID (FCMAPURESULTVALID_delay), + .FCMAPUSLEEPNOTREADY (FCMAPUSLEEPNOTREADY_delay), + .FCMAPUSTOREDATA (FCMAPUSTOREDATA_delay), + .JTGC440TCK (JTGC440TCK_delay), + .JTGC440TDI (JTGC440TDI_delay), + .JTGC440TMS (JTGC440TMS_delay), + .JTGC440TRSTNEG (JTGC440TRSTNEG_delay), + .LLDMA0RSTENGINEREQ (LLDMA0RSTENGINEREQ_delay), + .LLDMA0RXD (LLDMA0RXD_delay), + .LLDMA0RXEOFN (LLDMA0RXEOFN_delay), + .LLDMA0RXEOPN (LLDMA0RXEOPN_delay), + .LLDMA0RXREM (LLDMA0RXREM_delay), + .LLDMA0RXSOFN (LLDMA0RXSOFN_delay), + .LLDMA0RXSOPN (LLDMA0RXSOPN_delay), + .LLDMA0RXSRCRDYN (LLDMA0RXSRCRDYN_delay), + .LLDMA0TXDSTRDYN (LLDMA0TXDSTRDYN_delay), + .LLDMA1RSTENGINEREQ (LLDMA1RSTENGINEREQ_delay), + .LLDMA1RXD (LLDMA1RXD_delay), + .LLDMA1RXEOFN (LLDMA1RXEOFN_delay), + .LLDMA1RXEOPN (LLDMA1RXEOPN_delay), + .LLDMA1RXREM (LLDMA1RXREM_delay), + .LLDMA1RXSOFN (LLDMA1RXSOFN_delay), + .LLDMA1RXSOPN (LLDMA1RXSOPN_delay), + .LLDMA1RXSRCRDYN (LLDMA1RXSRCRDYN_delay), + .LLDMA1TXDSTRDYN (LLDMA1TXDSTRDYN_delay), + .LLDMA2RSTENGINEREQ (LLDMA2RSTENGINEREQ_delay), + .LLDMA2RXD (LLDMA2RXD_delay), + .LLDMA2RXEOFN (LLDMA2RXEOFN_delay), + .LLDMA2RXEOPN (LLDMA2RXEOPN_delay), + .LLDMA2RXREM (LLDMA2RXREM_delay), + .LLDMA2RXSOFN (LLDMA2RXSOFN_delay), + .LLDMA2RXSOPN (LLDMA2RXSOPN_delay), + .LLDMA2RXSRCRDYN (LLDMA2RXSRCRDYN_delay), + .LLDMA2TXDSTRDYN (LLDMA2TXDSTRDYN_delay), + .LLDMA3RSTENGINEREQ (LLDMA3RSTENGINEREQ_delay), + .LLDMA3RXD (LLDMA3RXD_delay), + .LLDMA3RXEOFN (LLDMA3RXEOFN_delay), + .LLDMA3RXEOPN (LLDMA3RXEOPN_delay), + .LLDMA3RXREM (LLDMA3RXREM_delay), + .LLDMA3RXSOFN (LLDMA3RXSOFN_delay), + .LLDMA3RXSOPN (LLDMA3RXSOPN_delay), + .LLDMA3RXSRCRDYN (LLDMA3RXSRCRDYN_delay), + .LLDMA3TXDSTRDYN (LLDMA3TXDSTRDYN_delay), + .MCMIADDRREADYTOACCEPT (MCMIADDRREADYTOACCEPT_delay), + .MCMIREADDATA (MCMIREADDATA_delay), + .MCMIREADDATAERR (MCMIREADDATAERR_delay), + .MCMIREADDATAVALID (MCMIREADDATAVALID_delay), + .PLBPPCMADDRACK (PLBPPCMADDRACK_delay), + .PLBPPCMMBUSY (PLBPPCMMBUSY_delay), + .PLBPPCMMIRQ (PLBPPCMMIRQ_delay), + .PLBPPCMMRDERR (PLBPPCMMRDERR_delay), + .PLBPPCMMWRERR (PLBPPCMMWRERR_delay), + .PLBPPCMRDBTERM (PLBPPCMRDBTERM_delay), + .PLBPPCMRDDACK (PLBPPCMRDDACK_delay), + .PLBPPCMRDDBUS (PLBPPCMRDDBUS_delay), + .PLBPPCMRDPENDPRI (PLBPPCMRDPENDPRI_delay), + .PLBPPCMRDPENDREQ (PLBPPCMRDPENDREQ_delay), + .PLBPPCMRDWDADDR (PLBPPCMRDWDADDR_delay), + .PLBPPCMREARBITRATE (PLBPPCMREARBITRATE_delay), + .PLBPPCMREQPRI (PLBPPCMREQPRI_delay), + .PLBPPCMSSIZE (PLBPPCMSSIZE_delay), + .PLBPPCMTIMEOUT (PLBPPCMTIMEOUT_delay), + .PLBPPCMWRBTERM (PLBPPCMWRBTERM_delay), + .PLBPPCMWRDACK (PLBPPCMWRDACK_delay), + .PLBPPCMWRPENDPRI (PLBPPCMWRPENDPRI_delay), + .PLBPPCMWRPENDREQ (PLBPPCMWRPENDREQ_delay), + .PLBPPCS0ABORT (PLBPPCS0ABORT_delay), + .PLBPPCS0ABUS (PLBPPCS0ABUS_delay), + .PLBPPCS0BE (PLBPPCS0BE_delay), + .PLBPPCS0BUSLOCK (PLBPPCS0BUSLOCK_delay), + .PLBPPCS0LOCKERR (PLBPPCS0LOCKERR_delay), + .PLBPPCS0MASTERID (PLBPPCS0MASTERID_delay), + .PLBPPCS0MSIZE (PLBPPCS0MSIZE_delay), + .PLBPPCS0PAVALID (PLBPPCS0PAVALID_delay), + .PLBPPCS0RDBURST (PLBPPCS0RDBURST_delay), + .PLBPPCS0RDPENDPRI (PLBPPCS0RDPENDPRI_delay), + .PLBPPCS0RDPENDREQ (PLBPPCS0RDPENDREQ_delay), + .PLBPPCS0RDPRIM (PLBPPCS0RDPRIM_delay), + .PLBPPCS0REQPRI (PLBPPCS0REQPRI_delay), + .PLBPPCS0RNW (PLBPPCS0RNW_delay), + .PLBPPCS0SAVALID (PLBPPCS0SAVALID_delay), + .PLBPPCS0SIZE (PLBPPCS0SIZE_delay), + .PLBPPCS0TATTRIBUTE (PLBPPCS0TATTRIBUTE_delay), + .PLBPPCS0TYPE (PLBPPCS0TYPE_delay), + .PLBPPCS0UABUS (PLBPPCS0UABUS_delay), + .PLBPPCS0WRBURST (PLBPPCS0WRBURST_delay), + .PLBPPCS0WRDBUS (PLBPPCS0WRDBUS_delay), + .PLBPPCS0WRPENDPRI (PLBPPCS0WRPENDPRI_delay), + .PLBPPCS0WRPENDREQ (PLBPPCS0WRPENDREQ_delay), + .PLBPPCS0WRPRIM (PLBPPCS0WRPRIM_delay), + .PLBPPCS1ABORT (PLBPPCS1ABORT_delay), + .PLBPPCS1ABUS (PLBPPCS1ABUS_delay), + .PLBPPCS1BE (PLBPPCS1BE_delay), + .PLBPPCS1BUSLOCK (PLBPPCS1BUSLOCK_delay), + .PLBPPCS1LOCKERR (PLBPPCS1LOCKERR_delay), + .PLBPPCS1MASTERID (PLBPPCS1MASTERID_delay), + .PLBPPCS1MSIZE (PLBPPCS1MSIZE_delay), + .PLBPPCS1PAVALID (PLBPPCS1PAVALID_delay), + .PLBPPCS1RDBURST (PLBPPCS1RDBURST_delay), + .PLBPPCS1RDPENDPRI (PLBPPCS1RDPENDPRI_delay), + .PLBPPCS1RDPENDREQ (PLBPPCS1RDPENDREQ_delay), + .PLBPPCS1RDPRIM (PLBPPCS1RDPRIM_delay), + .PLBPPCS1REQPRI (PLBPPCS1REQPRI_delay), + .PLBPPCS1RNW (PLBPPCS1RNW_delay), + .PLBPPCS1SAVALID (PLBPPCS1SAVALID_delay), + .PLBPPCS1SIZE (PLBPPCS1SIZE_delay), + .PLBPPCS1TATTRIBUTE (PLBPPCS1TATTRIBUTE_delay), + .PLBPPCS1TYPE (PLBPPCS1TYPE_delay), + .PLBPPCS1UABUS (PLBPPCS1UABUS_delay), + .PLBPPCS1WRBURST (PLBPPCS1WRBURST_delay), + .PLBPPCS1WRDBUS (PLBPPCS1WRDBUS_delay), + .PLBPPCS1WRPENDPRI (PLBPPCS1WRPENDPRI_delay), + .PLBPPCS1WRPENDREQ (PLBPPCS1WRPENDREQ_delay), + .PLBPPCS1WRPRIM (PLBPPCS1WRPRIM_delay), + .RSTC440RESETCHIP (RSTC440RESETCHIP_delay), + .RSTC440RESETCORE (RSTC440RESETCORE_delay), + .RSTC440RESETSYSTEM (RSTC440RESETSYSTEM_delay), + .TIEC440DCURDLDCACHEPLBPRIO (TIEC440DCURDLDCACHEPLBPRIO_delay), + .TIEC440DCURDNONCACHEPLBPRIO (TIEC440DCURDNONCACHEPLBPRIO_delay), + .TIEC440DCURDTOUCHPLBPRIO (TIEC440DCURDTOUCHPLBPRIO_delay), + .TIEC440DCURDURGENTPLBPRIO (TIEC440DCURDURGENTPLBPRIO_delay), + .TIEC440DCUWRFLUSHPLBPRIO (TIEC440DCUWRFLUSHPLBPRIO_delay), + .TIEC440DCUWRSTOREPLBPRIO (TIEC440DCUWRSTOREPLBPRIO_delay), + .TIEC440DCUWRURGENTPLBPRIO (TIEC440DCUWRURGENTPLBPRIO_delay), + .TIEC440ENDIANRESET (TIEC440ENDIANRESET_delay), + .TIEC440ERPNRESET (TIEC440ERPNRESET_delay), + .TIEC440ICURDFETCHPLBPRIO (TIEC440ICURDFETCHPLBPRIO_delay), + .TIEC440ICURDSPECPLBPRIO (TIEC440ICURDSPECPLBPRIO_delay), + .TIEC440ICURDTOUCHPLBPRIO (TIEC440ICURDTOUCHPLBPRIO_delay), + .TIEC440PIR (TIEC440PIR_delay), + .TIEC440PVR (TIEC440PVR_delay), + .TIEC440USERRESET (TIEC440USERRESET_delay), + .TIEDCRBASEADDR (TIEDCRBASEADDR_delay), + .TRCC440TRACEDISABLE (TRCC440TRACEDISABLE_delay), + .TRCC440TRIGGEREVENTIN (TRCC440TRIGGEREVENTIN_delay), + .GSR (GSR) +); + +specify + (CPMC440CLK => C440CPMCORESLEEPREQ) = (100, 100); + (CPMC440CLK => C440CPMDECIRPTREQ) = (100, 100); + (CPMC440CLK => C440CPMFITIRPTREQ) = (100, 100); + (CPMC440CLK => C440CPMMSRCE) = (100, 100); + (CPMC440CLK => C440CPMMSREE) = (100, 100); + (CPMC440CLK => C440CPMTIMERRESETREQ) = (100, 100); + (CPMC440CLK => C440CPMWDIRPTREQ) = (100, 100); + (CPMC440CLK => C440DBGSYSTEMCONTROL) = (100, 100); + (CPMC440CLK => C440MACHINECHECK) = (100, 100); + (CPMC440CLK => C440TRCBRANCHSTATUS) = (100, 100); + (CPMC440CLK => C440TRCCYCLE) = (100, 100); + (CPMC440CLK => C440TRCEXECUTIONSTATUS) = (100, 100); + (CPMC440CLK => C440TRCTRACESTATUS) = (100, 100); + (CPMC440CLK => C440TRCTRIGGEREVENTOUT) = (100, 100); + (CPMC440CLK => C440TRCTRIGGEREVENTTYPE) = (100, 100); + (CPMDCRCLK => PPCDMDCRABUS) = (100, 100); + (CPMDCRCLK => PPCDMDCRDBUSOUT) = (100, 100); + (CPMDCRCLK => PPCDMDCRREAD) = (100, 100); + (CPMDCRCLK => PPCDMDCRUABUS) = (100, 100); + (CPMDCRCLK => PPCDMDCRWRITE) = (100, 100); + (CPMDCRCLK => PPCDSDCRACK) = (100, 100); + (CPMDCRCLK => PPCDSDCRDBUSIN) = (100, 100); + (CPMDCRCLK => PPCDSDCRTIMEOUTWAIT) = (100, 100); + (CPMDMA0LLCLK => DMA0LLRSTENGINEACK) = (100, 100); + (CPMDMA0LLCLK => DMA0LLRXDSTRDYN) = (100, 100); + (CPMDMA0LLCLK => DMA0LLTXD) = (100, 100); + (CPMDMA0LLCLK => DMA0LLTXEOFN) = (100, 100); + (CPMDMA0LLCLK => DMA0LLTXEOPN) = (100, 100); + (CPMDMA0LLCLK => DMA0LLTXREM) = (100, 100); + (CPMDMA0LLCLK => DMA0LLTXSOFN) = (100, 100); + (CPMDMA0LLCLK => DMA0LLTXSOPN) = (100, 100); + (CPMDMA0LLCLK => DMA0LLTXSRCRDYN) = (100, 100); + (CPMDMA0LLCLK => DMA0RXIRQ) = (100, 100); + (CPMDMA0LLCLK => DMA0TXIRQ) = (100, 100); + (CPMDMA1LLCLK => DMA1LLRSTENGINEACK) = (100, 100); + (CPMDMA1LLCLK => DMA1LLRXDSTRDYN) = (100, 100); + (CPMDMA1LLCLK => DMA1LLTXD) = (100, 100); + (CPMDMA1LLCLK => DMA1LLTXEOFN) = (100, 100); + (CPMDMA1LLCLK => DMA1LLTXEOPN) = (100, 100); + (CPMDMA1LLCLK => DMA1LLTXREM) = (100, 100); + (CPMDMA1LLCLK => DMA1LLTXSOFN) = (100, 100); + (CPMDMA1LLCLK => DMA1LLTXSOPN) = (100, 100); + (CPMDMA1LLCLK => DMA1LLTXSRCRDYN) = (100, 100); + (CPMDMA1LLCLK => DMA1RXIRQ) = (100, 100); + (CPMDMA1LLCLK => DMA1TXIRQ) = (100, 100); + (CPMDMA2LLCLK => DMA2LLRSTENGINEACK) = (100, 100); + (CPMDMA2LLCLK => DMA2LLRXDSTRDYN) = (100, 100); + (CPMDMA2LLCLK => DMA2LLTXD) = (100, 100); + (CPMDMA2LLCLK => DMA2LLTXEOFN) = (100, 100); + (CPMDMA2LLCLK => DMA2LLTXEOPN) = (100, 100); + (CPMDMA2LLCLK => DMA2LLTXREM) = (100, 100); + (CPMDMA2LLCLK => DMA2LLTXSOFN) = (100, 100); + (CPMDMA2LLCLK => DMA2LLTXSOPN) = (100, 100); + (CPMDMA2LLCLK => DMA2LLTXSRCRDYN) = (100, 100); + (CPMDMA2LLCLK => DMA2RXIRQ) = (100, 100); + (CPMDMA2LLCLK => DMA2TXIRQ) = (100, 100); + (CPMDMA3LLCLK => DMA3LLRSTENGINEACK) = (100, 100); + (CPMDMA3LLCLK => DMA3LLRXDSTRDYN) = (100, 100); + (CPMDMA3LLCLK => DMA3LLTXD) = (100, 100); + (CPMDMA3LLCLK => DMA3LLTXEOFN) = (100, 100); + (CPMDMA3LLCLK => DMA3LLTXEOPN) = (100, 100); + (CPMDMA3LLCLK => DMA3LLTXREM) = (100, 100); + (CPMDMA3LLCLK => DMA3LLTXSOFN) = (100, 100); + (CPMDMA3LLCLK => DMA3LLTXSOPN) = (100, 100); + (CPMDMA3LLCLK => DMA3LLTXSRCRDYN) = (100, 100); + (CPMDMA3LLCLK => DMA3RXIRQ) = (100, 100); + (CPMDMA3LLCLK => DMA3TXIRQ) = (100, 100); + (CPMFCMCLK => APUFCMDECFPUOP) = (100, 100); + (CPMFCMCLK => APUFCMDECLDSTXFERSIZE) = (100, 100); + (CPMFCMCLK => APUFCMDECLOAD) = (100, 100); + (CPMFCMCLK => APUFCMDECNONAUTON) = (100, 100); + (CPMFCMCLK => APUFCMDECSTORE) = (100, 100); + (CPMFCMCLK => APUFCMDECUDI) = (100, 100); + (CPMFCMCLK => APUFCMDECUDIVALID) = (100, 100); + (CPMFCMCLK => APUFCMENDIAN) = (100, 100); + (CPMFCMCLK => APUFCMFLUSH) = (100, 100); + (CPMFCMCLK => APUFCMINSTRUCTION) = (100, 100); + (CPMFCMCLK => APUFCMINSTRVALID) = (100, 100); + (CPMFCMCLK => APUFCMLOADBYTEADDR) = (100, 100); + (CPMFCMCLK => APUFCMLOADDATA) = (100, 100); + (CPMFCMCLK => APUFCMLOADDVALID) = (100, 100); + (CPMFCMCLK => APUFCMMSRFE0) = (100, 100); + (CPMFCMCLK => APUFCMMSRFE1) = (100, 100); + (CPMFCMCLK => APUFCMNEXTINSTRREADY) = (100, 100); + (CPMFCMCLK => APUFCMOPERANDVALID) = (100, 100); + (CPMFCMCLK => APUFCMRADATA) = (100, 100); + (CPMFCMCLK => APUFCMRBDATA) = (100, 100); + (CPMFCMCLK => APUFCMWRITEBACKOK) = (100, 100); + (CPMINTERCONNECTCLK => C440RSTCHIPRESETREQ) = (100, 100); + (CPMINTERCONNECTCLK => C440RSTCORERESETREQ) = (100, 100); + (CPMINTERCONNECTCLK => C440RSTSYSTEMRESETREQ) = (100, 100); + (CPMINTERCONNECTCLK => PPCCPMINTERCONNECTBUSY) = (100, 100); + (CPMINTERCONNECTCLK => PPCEICINTERCONNECTIRQ) = (100, 100); + (CPMMCCLK => MIMCADDRESS) = (100, 100); + (CPMMCCLK => MIMCADDRESSVALID) = (100, 100); + (CPMMCCLK => MIMCBANKCONFLICT) = (100, 100); + (CPMMCCLK => MIMCBYTEENABLE) = (100, 100); + (CPMMCCLK => MIMCREADNOTWRITE) = (100, 100); + (CPMMCCLK => MIMCROWCONFLICT) = (100, 100); + (CPMMCCLK => MIMCWRITEDATA) = (100, 100); + (CPMMCCLK => MIMCWRITEDATAVALID) = (100, 100); + (CPMPPCMPLBCLK => PPCMPLBABORT) = (100, 100); + (CPMPPCMPLBCLK => PPCMPLBABUS) = (100, 100); + (CPMPPCMPLBCLK => PPCMPLBBE) = (100, 100); + (CPMPPCMPLBCLK => PPCMPLBBUSLOCK) = (100, 100); + (CPMPPCMPLBCLK => PPCMPLBLOCKERR) = (100, 100); + (CPMPPCMPLBCLK => PPCMPLBPRIORITY) = (100, 100); + (CPMPPCMPLBCLK => PPCMPLBRDBURST) = (100, 100); + (CPMPPCMPLBCLK => PPCMPLBREQUEST) = (100, 100); + (CPMPPCMPLBCLK => PPCMPLBRNW) = (100, 100); + (CPMPPCMPLBCLK => PPCMPLBSIZE) = (100, 100); + (CPMPPCMPLBCLK => PPCMPLBTATTRIBUTE) = (100, 100); + (CPMPPCMPLBCLK => PPCMPLBTYPE) = (100, 100); + (CPMPPCMPLBCLK => PPCMPLBUABUS) = (100, 100); + (CPMPPCMPLBCLK => PPCMPLBWRBURST) = (100, 100); + (CPMPPCMPLBCLK => PPCMPLBWRDBUS) = (100, 100); + (CPMPPCS0PLBCLK => PPCS0PLBADDRACK) = (100, 100); + (CPMPPCS0PLBCLK => PPCS0PLBMBUSY) = (100, 100); + (CPMPPCS0PLBCLK => PPCS0PLBMIRQ) = (100, 100); + (CPMPPCS0PLBCLK => PPCS0PLBMRDERR) = (100, 100); + (CPMPPCS0PLBCLK => PPCS0PLBMWRERR) = (100, 100); + (CPMPPCS0PLBCLK => PPCS0PLBRDBTERM) = (100, 100); + (CPMPPCS0PLBCLK => PPCS0PLBRDCOMP) = (100, 100); + (CPMPPCS0PLBCLK => PPCS0PLBRDDACK) = (100, 100); + (CPMPPCS0PLBCLK => PPCS0PLBRDDBUS) = (100, 100); + (CPMPPCS0PLBCLK => PPCS0PLBRDWDADDR) = (100, 100); + (CPMPPCS0PLBCLK => PPCS0PLBREARBITRATE) = (100, 100); + (CPMPPCS0PLBCLK => PPCS0PLBSSIZE) = (100, 100); + (CPMPPCS0PLBCLK => PPCS0PLBWAIT) = (100, 100); + (CPMPPCS0PLBCLK => PPCS0PLBWRBTERM) = (100, 100); + (CPMPPCS0PLBCLK => PPCS0PLBWRCOMP) = (100, 100); + (CPMPPCS0PLBCLK => PPCS0PLBWRDACK) = (100, 100); + (CPMPPCS1PLBCLK => PPCS1PLBADDRACK) = (100, 100); + (CPMPPCS1PLBCLK => PPCS1PLBMBUSY) = (100, 100); + (CPMPPCS1PLBCLK => PPCS1PLBMIRQ) = (100, 100); + (CPMPPCS1PLBCLK => PPCS1PLBMRDERR) = (100, 100); + (CPMPPCS1PLBCLK => PPCS1PLBMWRERR) = (100, 100); + (CPMPPCS1PLBCLK => PPCS1PLBRDBTERM) = (100, 100); + (CPMPPCS1PLBCLK => PPCS1PLBRDCOMP) = (100, 100); + (CPMPPCS1PLBCLK => PPCS1PLBRDDACK) = (100, 100); + (CPMPPCS1PLBCLK => PPCS1PLBRDDBUS) = (100, 100); + (CPMPPCS1PLBCLK => PPCS1PLBRDWDADDR) = (100, 100); + (CPMPPCS1PLBCLK => PPCS1PLBREARBITRATE) = (100, 100); + (CPMPPCS1PLBCLK => PPCS1PLBSSIZE) = (100, 100); + (CPMPPCS1PLBCLK => PPCS1PLBWAIT) = (100, 100); + (CPMPPCS1PLBCLK => PPCS1PLBWRBTERM) = (100, 100); + (CPMPPCS1PLBCLK => PPCS1PLBWRCOMP) = (100, 100); + (CPMPPCS1PLBCLK => PPCS1PLBWRDACK) = (100, 100); + (JTGC440TCK => C440JTGTDO) = (100, 100); + (JTGC440TCK => C440JTGTDOEN) = (100, 100); + specparam PATHPULSE$ = 0; +endspecify +endmodule diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/PULLDOWN.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/PULLDOWN.v new file mode 100644 index 0000000..b226331 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/PULLDOWN.v @@ -0,0 +1,34 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/PULLDOWN.v,v 1.5 2007/05/23 21:43:44 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Resistor to GND +// /___/ /\ Filename : PULLDOWN.v +// \ \ / \ Timestamp : Thu Mar 25 16:43:32 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. +// 05/23/07 - Added wire declaration for internal signals. + +`timescale 1 ps / 1 ps + + +module PULLDOWN (O); + + output O; + + wire A; + + pulldown (A); + buf (weak0,weak1) #(100,100) (O,A); + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/PULLUP.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/PULLUP.v new file mode 100644 index 0000000..1665e0b --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/PULLUP.v @@ -0,0 +1,34 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/PULLUP.v,v 1.5 2007/05/23 21:43:44 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Resistor to VCC +// /___/ /\ Filename : PULLUP.v +// \ \ / \ Timestamp : Thu Mar 25 16:43:32 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. +// 05/23/07 - Added wire declaration for internal signals. + +`timescale 1 ps / 1 ps + + +module PULLUP (O); + + output O; + + wire A; + + pullup (A); + buf (weak0,weak1) #(100,100) (O,A); + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/RAM128X1D.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/RAM128X1D.v new file mode 100644 index 0000000..82731ba --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/RAM128X1D.v @@ -0,0 +1,52 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/rainier/RAM128X1D.v,v 1.5 2006/06/23 21:24:41 yanx Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Static Dual Port Synchronous RAM 128-Deep by 1-Wide +// /___/ /\ Filename : RAM128X1D.v +// \ \ / \ Timestamp : Thu Mar 25 16:43:34 PST 2004 +// \___\/\___\ +// +// Revision: +// 02/07/05 - Initial version. +// 06/22/06 - Change initial to hex (CR 233085). +// End Revision + +`timescale 1 ps / 1 ps + + +module RAM128X1D (DPO, SPO, A, D, DPRA, WCLK, WE); + + parameter INIT = 128'h0; + + output DPO, SPO; + + input [6:0] A; + input [6:0] DPRA; + input D; + input WCLK; + input WE; + + reg [127:0] mem; + + + assign SPO = mem[A]; + assign DPO = mem[DPRA]; + + + initial + mem = INIT; + + always @(posedge WCLK) + if (WE == 1'b1) + mem[A] <= #100 D; + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/RAM128X1S.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/RAM128X1S.v new file mode 100644 index 0000000..63add0a --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/RAM128X1S.v @@ -0,0 +1,46 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/RAM128X1S.v,v 1.6 2005/03/14 22:32:58 yanx Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Static Synchronous RAM 128-Deep by 1-Wide +// /___/ /\ Filename : RAM128X1S.v +// \ \ / \ Timestamp : Thu Mar 25 16:43:32 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 02/04/05 - Rev 0.0.1 Remove input/output bufs; Remove for-loop in initial block; +// End Revision + +`timescale 1 ps / 1 ps + + +module RAM128X1S (O, A0, A1, A2, A3, A4, A5, A6, D, WCLK, WE); + + parameter INIT = 128'h00000000000000000000000000000000; + + output O; + + input A0, A1, A2, A3, A4, A5, A6, D, WCLK, WE; + + reg [127:0] mem; + wire [6:0] adr; + + assign adr = {A6, A5, A4, A3, A2, A1, A0}; + assign O = mem[adr]; + + initial + mem = INIT; + + always @(posedge WCLK) + if (WE == 1'b1) + mem[adr] <= #100 D; + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/RAM128X1S_1.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/RAM128X1S_1.v new file mode 100644 index 0000000..06502be --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/RAM128X1S_1.v @@ -0,0 +1,46 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/RAM128X1S_1.v,v 1.7 2005/03/14 22:32:58 yanx Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Static Synchronous RAM 128-Deep by 1-Wide +// /___/ /\ Filename : RAM128X1S_1.v +// \ \ / \ Timestamp : Thu Mar 25 16:43:32 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 02/04/05 - Rev 0.0.1 Remove input/output bufs; Remove for-loop in initial block; +// End Revision + +`timescale 1 ps / 1 ps + + +module RAM128X1S_1 (O, A0, A1, A2, A3, A4, A5, A6, D, WCLK, WE); + + parameter INIT = 128'h00000000000000000000000000000000; + + output O; + + input A0, A1, A2, A3, A4, A5, A6, D, WCLK, WE; + + reg [127:0] mem; + wire [6:0] adr; + + assign adr = {A6, A5, A4, A3, A2, A1, A0}; + assign O = mem[adr]; + + initial + mem = INIT; + + always @(negedge WCLK) + if (WE == 1'b1) + mem[adr] <= #100 D; + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/RAM16X1D.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/RAM16X1D.v new file mode 100644 index 0000000..a0dad23 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/RAM16X1D.v @@ -0,0 +1,47 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/RAM16X1D.v,v 1.8 2005/03/14 22:32:58 yanx Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Static Dual Port Synchronous RAM 16-Deep by 1-Wide +// /___/ /\ Filename : RAM16X1D.v +// \ \ / \ Timestamp : Thu Mar 25 16:43:33 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 02/04/05 - Rev 0.0.1 Remove input/output bufs; Remove for-loop in initial block; +// End Revision + +`timescale 1 ps / 1 ps + + +module RAM16X1D (DPO, SPO, A0, A1, A2, A3, D, DPRA0, DPRA1, DPRA2, DPRA3, WCLK, WE); + + parameter INIT = 16'h0000; + + output DPO, SPO; + + input A0, A1, A2, A3, D, DPRA0, DPRA1, DPRA2, DPRA3, WCLK, WE; + + reg [15:0] mem; + wire [3:0] adr; + + assign adr = {A3, A2, A1, A0}; + assign SPO = mem[adr]; + assign DPO = mem[{DPRA3, DPRA2, DPRA1, DPRA0}]; + + initial + mem = INIT; + + always @(posedge WCLK) + if (WE == 1'b1) + mem[adr] <= #100 D; + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/RAM16X1D_1.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/RAM16X1D_1.v new file mode 100644 index 0000000..fd2b048 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/RAM16X1D_1.v @@ -0,0 +1,48 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/RAM16X1D_1.v,v 1.8 2005/03/14 22:32:58 yanx Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Static Dual Port Synchronous RAM 16-Deep by 1-Wide +// /___/ /\ Filename : RAM16X1D_1.v +// \ \ / \ Timestamp : Thu Mar 25 16:43:33 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 02/04/05 - Rev 0.0.1 Remove input/output bufs; Remove for-loop in initial block; +// End Revision + +`timescale 1 ps / 1 ps + + +module RAM16X1D_1 (DPO, SPO, A0, A1, A2, A3, D, DPRA0, DPRA1, DPRA2, DPRA3, WCLK, WE); + + parameter INIT = 16'h0000; + + output DPO, SPO; + + input A0, A1, A2, A3, D, DPRA0, DPRA1, DPRA2, DPRA3, WCLK, WE; + + reg [15:0] mem; + wire [3:0] adr; + + assign adr = {A3, A2, A1, A0}; + assign SPO = mem[adr]; + assign DPO = mem[{DPRA3, DPRA2, DPRA1, DPRA0}]; + + initial + mem = INIT; + + always @(negedge WCLK) + if (WE == 1'b1) + mem[adr] <= #100 D; + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/RAM16X1S.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/RAM16X1S.v new file mode 100644 index 0000000..25e07dd --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/RAM16X1S.v @@ -0,0 +1,46 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/RAM16X1S.v,v 1.8 2005/03/14 22:32:58 yanx Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Static Synchronous RAM 16-Deep by 1-Wide +// /___/ /\ Filename : RAM16X1S.v +// \ \ / \ Timestamp : Thu Mar 25 16:43:33 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 02/04/05 - Rev 0.0.1 Remove input/output bufs; Remove for-loop in initial block; +// End Revision + +`timescale 1 ps / 1 ps + + +module RAM16X1S (O, A0, A1, A2, A3, D, WCLK, WE); + + parameter INIT = 16'h0000; + + output O; + + input A0, A1, A2, A3, D, WCLK, WE; + + reg [15:0] mem; + wire [3:0] adr; + + assign adr = {A3, A2, A1, A0}; + assign O = mem[adr]; + + initial + mem = INIT; + + always @(posedge WCLK) + if (WE == 1'b1) + mem[adr] <= #100 D; + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/RAM16X1S_1.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/RAM16X1S_1.v new file mode 100644 index 0000000..f40ade8 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/RAM16X1S_1.v @@ -0,0 +1,46 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/RAM16X1S_1.v,v 1.8 2005/03/14 22:32:58 yanx Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Static Synchronous RAM 16-Deep by 1 -Wide +// /___/ /\ Filename : RAM16X1S_1.v +// \ \ / \ Timestamp : Thu Mar 25 16:43:33 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 02/04/05 - Rev 0.0.1 Remove input/output bufs; Remove for-loop in initial block; +// End Revision + +`timescale 1 ps / 1 ps + + +module RAM16X1S_1 (O, A0, A1, A2, A3, D, WCLK, WE); + + parameter INIT = 16'h0000; + + output O; + + input A0, A1, A2, A3, D, WCLK, WE; + + reg [15:0] mem; + wire [3:0] adr; + + assign adr = {A3, A2, A1, A0}; + assign O = mem[adr]; + + initial + mem = INIT; + + always @(negedge WCLK) + if (WE == 1'b1) + mem[adr] <= #100 D; + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/RAM16X2S.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/RAM16X2S.v new file mode 100644 index 0000000..6de6574 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/RAM16X2S.v @@ -0,0 +1,54 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/RAM16X2S.v,v 1.8 2005/03/14 22:32:58 yanx Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Static Synchronous RAM 16-Deep by 2-Wide +// /___/ /\ Filename : RAM16X2S.v +// \ \ / \ Timestamp : Thu Mar 25 16:43:33 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 02/04/05 - Rev 0.0.1 Remove input/output bufs; Remove for-loop in initial block; +// End Revision + +`timescale 1 ps / 1 ps + + +module RAM16X2S (O0, O1, A0, A1, A2, A3, D0, D1, WCLK, WE); + + parameter INIT_00 = 16'h0000; + parameter INIT_01 = 16'h0000; + + output O0, O1; + + input A0, A1, A2, A3, D0, D1, WCLK, WE; + + reg [15:0] mem1; + reg [15:0] mem2; + + wire [3:0] adr; + + assign adr = {A3, A2, A1, A0}; + assign O0 = mem1[adr]; + assign O1 = mem2[adr]; + + initial begin + mem1 = INIT_00; + mem2 = INIT_01; + end + + always @(posedge WCLK) + if (WE == 1'b1) begin + mem1[adr] <= #100 D0; + mem2[adr] <= #100 D1; + end + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/RAM16X4S.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/RAM16X4S.v new file mode 100644 index 0000000..0fa23c2 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/RAM16X4S.v @@ -0,0 +1,64 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/RAM16X4S.v,v 1.8 2005/03/14 22:32:58 yanx Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Static Synchronous RAM 16-Deep by 4-Wide +// /___/ /\ Filename : RAM16X4S.v +// \ \ / \ Timestamp : Thu Mar 25 16:43:33 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 02/04/05 - Rev 0.0.1 Remove input/output bufs; Remove for-loop in initial block; +// End Revision + +`timescale 1 ps / 1 ps + + +module RAM16X4S (O0, O1, O2, O3, A0, A1, A2, A3, D0, D1, D2, D3, WCLK, WE); + + parameter INIT_00 = 16'h0000; + parameter INIT_01 = 16'h0000; + parameter INIT_02 = 16'h0000; + parameter INIT_03 = 16'h0000; + + output O0, O1, O2, O3; + + input A0, A1, A2, A3, D0, D1, D2, D3, WCLK, WE; + + reg [15:0] mem0; + reg [15:0] mem1; + reg [15:0] mem2; + reg [15:0] mem3; + + wire [3:0] adr; + + assign adr = {A3, A2, A1, A0}; + assign O0 = mem0[adr]; + assign O1 = mem1[adr]; + assign O2 = mem2[adr]; + assign O3 = mem3[adr]; + + initial begin + mem0 = INIT_00; + mem1 = INIT_01; + mem2 = INIT_02; + mem3 = INIT_03; + end + + always @(posedge WCLK) + if (WE == 1'b1) begin + mem0[adr] <= #100 D0; + mem1[adr] <= #100 D1; + mem2[adr] <= #100 D2; + mem3[adr] <= #100 D3; + end + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/RAM16X8S.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/RAM16X8S.v new file mode 100644 index 0000000..8d5d17a --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/RAM16X8S.v @@ -0,0 +1,61 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/RAM16X8S.v,v 1.9 2005/05/23 22:42:09 yanx Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Static Synchronous RAM 16-Deep by 8-Wide +// /___/ /\ Filename : RAM16X8S.v +// \ \ / \ Timestamp : Thu Mar 25 16:43:33 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 02/04/05 - Rev 0.0.1 Remove input/output bufs; Remove for-loop in initial block; +// 05/23/05 - Change initial order (BugTrack#194). +// End Revision + +`timescale 1 ps / 1 ps + + +module RAM16X8S (O, A0, A1, A2, A3, D, WCLK, WE); + + parameter INIT_00 = 16'h0000; + parameter INIT_01 = 16'h0000; + parameter INIT_02 = 16'h0000; + parameter INIT_03 = 16'h0000; + parameter INIT_04 = 16'h0000; + parameter INIT_05 = 16'h0000; + parameter INIT_06 = 16'h0000; + parameter INIT_07 = 16'h0000; + + output [7:0] O; + + input A0, A1, A2, A3, WCLK, WE; + input [7:0] D; + + + reg [7:0] mem [15:0]; + integer i; + reg test; + + wire [3:0] adr; + + assign adr = {A3, A2, A1, A0}; + assign O = mem[adr]; + + initial + for (i = 0; i < 16; i=i+1) + mem[i] = {INIT_07[i], INIT_06[i], INIT_05[i], INIT_04[i], INIT_03[i], INIT_02[i], + INIT_01[i], INIT_00[i]}; + + always @(posedge WCLK) + if (WE == 1'b1) + mem[adr] <= #100 D; + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/RAM256X1S.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/RAM256X1S.v new file mode 100644 index 0000000..9072785 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/RAM256X1S.v @@ -0,0 +1,48 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/rainier/RAM256X1S.v,v 1.5 2006/06/23 21:24:41 yanx Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Static Synchronous RAM 256-Deep by 1-Wide +// /___/ /\ Filename : RAM256X1S.v +// \ \ / \ Timestamp : Thu Mar 25 16:43:32 PST 2004 +// \___\/\___\ +// +// Revision: +// 02/07/05 - Initial version. +// 06/22/06 - Change initial to hex (CR 233085). +// End Revision + +`timescale 1 ps / 1 ps + + +module RAM256X1S (O, A, D, WCLK, WE); + + parameter INIT = 256'h0; + + output O; + + input [7:0] A; + input D; + input WCLK; + input WE; + + reg [255:0] mem; + + initial + mem = INIT; + + assign O = mem[A]; + + always @(posedge WCLK) + if (WE == 1'b1) + mem[A] <= #100 D; + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/RAM32M.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/RAM32M.v new file mode 100644 index 0000000..5105304 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/RAM32M.v @@ -0,0 +1,75 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/rainier/RAM32M.v,v 1.5 2010/01/14 00:42:01 yanx Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Function Simulation Library Component +// / / 32-Deep by 8-bit Wide Multi Port RAM +// /___/ /\ Filename : RAM32M.v +// \ \ / \ Timestamp : +// \___\/\___\ +// +// Revision: +// 03/21/06 - Initial version. +// 01/13/10 - Remove notifier block (CR544157) +// End Revision + +`timescale 1 ps/1 ps + +module RAM32M (DOA, DOB, DOC, DOD, ADDRA, ADDRB, ADDRC, ADDRD, DIA, DIB, DIC, DID, WCLK, WE); + + parameter INIT_A = 64'h0000000000000000; + parameter INIT_B = 64'h0000000000000000; + parameter INIT_C = 64'h0000000000000000; + parameter INIT_D = 64'h0000000000000000; + + output [1:0] DOA; + output [1:0] DOB; + output [1:0] DOC; + output [1:0] DOD; + input [4:0] ADDRA; + input [4:0] ADDRB; + input [4:0] ADDRC; + input [4:0] ADDRD; + input [1:0] DIA; + input [1:0] DIB; + input [1:0] DIC; + input [1:0] DID; + input WCLK; + input WE; + + reg [63:0] mem_a, mem_b, mem_c, mem_d; + + initial begin + mem_a = INIT_A; + mem_b = INIT_B; + mem_c = INIT_C; + mem_d = INIT_D; + end + + always @(posedge WCLK) + if (WE) begin + mem_a[2*ADDRD] <= #100 DIA[0]; + mem_a[2*ADDRD + 1] <= #100 DIA[1]; + mem_b[2*ADDRD] <= #100 DIB[0]; + mem_b[2*ADDRD + 1] <= #100 DIB[1]; + mem_c[2*ADDRD] <= #100 DIC[0]; + mem_c[2*ADDRD + 1] <= #100 DIC[1]; + mem_d[2*ADDRD] <= #100 DID[0]; + mem_d[2*ADDRD + 1] <= #100 DID[1]; + end + + assign DOA[0] = mem_a[2*ADDRA]; + assign DOA[1] = mem_a[2*ADDRA + 1]; + assign DOB[0] = mem_b[2*ADDRB]; + assign DOB[1] = mem_b[2*ADDRB + 1]; + assign DOC[0] = mem_c[2*ADDRC]; + assign DOC[1] = mem_c[2*ADDRC + 1]; + assign DOD[0] = mem_d[2*ADDRD]; + assign DOD[1] = mem_d[2*ADDRD + 1]; + +endmodule diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/RAM32X1D.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/RAM32X1D.v new file mode 100644 index 0000000..2410f54 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/RAM32X1D.v @@ -0,0 +1,46 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/RAM32X1D.v,v 1.8 2005/03/14 22:32:58 yanx Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Static Dual Port Synchronous RAM 32-Deep by 1-Wide +// /___/ /\ Filename : RAM32X1D.v +// \ \ / \ Timestamp : Thu Mar 25 16:43:33 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 02/04/05 - Rev 0.0.1 Remove input/output bufs; Remove for-loop in initial block; +// End Revision + +`timescale 1 ps / 1 ps + +module RAM32X1D (DPO, SPO, A0, A1, A2, A3, A4, D, DPRA0, DPRA1, DPRA2, DPRA3, DPRA4, WCLK, WE); + + parameter INIT = 32'h00000000; + + output DPO, SPO; + + input A0, A1, A2, A3, A4, D, DPRA0, DPRA1, DPRA2, DPRA3, DPRA4, WCLK, WE; + + reg [31:0] mem; + wire [4:0] adr; + + assign adr = {A4, A3, A2, A1, A0}; + assign SPO = mem[adr]; + assign DPO = mem[{DPRA4, DPRA3, DPRA2, DPRA1, DPRA0}]; + + initial + mem = INIT; + + always @(posedge WCLK) + if (WE == 1'b1) + mem[adr] <= #100 D; + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/RAM32X1D_1.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/RAM32X1D_1.v new file mode 100644 index 0000000..55025b9 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/RAM32X1D_1.v @@ -0,0 +1,47 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/RAM32X1D_1.v,v 1.8 2005/03/14 22:32:58 yanx Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Static Dual Port Synchronous RAM 32-Deep by 1-Wide +// /___/ /\ Filename : RAM32X1D_1.v +// \ \ / \ Timestamp : Thu Mar 25 16:43:33 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 02/04/05 - Rev 0.0.1 Remove input/output bufs; Remove for-loop in initial block; +// End Revision + +`timescale 1 ps / 1 ps + + +module RAM32X1D_1 (DPO, SPO, A0, A1, A2, A3, A4, D, DPRA0, DPRA1, DPRA2, DPRA3, DPRA4, WCLK, WE); + + parameter INIT = 32'h00000000; + + output DPO, SPO; + + input A0, A1, A2, A3, A4, D, DPRA0, DPRA1, DPRA2, DPRA3, DPRA4, WCLK, WE; + + reg [31:0] mem; + wire [4:0] adr; + + assign adr = {A4, A3, A2, A1, A0}; + assign SPO = mem[adr]; + assign DPO = mem[{DPRA4, DPRA3, DPRA2, DPRA1, DPRA0}]; + + initial + mem = INIT; + + always @(negedge WCLK) + if (WE == 1'b1) + mem[adr] <= #100 D; + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/RAM32X1S.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/RAM32X1S.v new file mode 100644 index 0000000..9cd39f3 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/RAM32X1S.v @@ -0,0 +1,46 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/RAM32X1S.v,v 1.8 2005/03/14 22:32:58 yanx Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Static Synchronous RAM 32-Deep by 1-Wide +// /___/ /\ Filename : RAM32X1S.v +// \ \ / \ Timestamp : Thu Mar 25 16:43:33 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 02/04/05 - Rev 0.0.1 Remove input/output bufs; Remove for-loop in initial block; +// End Revision + +`timescale 1 ps / 1 ps + + +module RAM32X1S (O, A0, A1, A2, A3, A4, D, WCLK, WE); + + parameter INIT = 32'h00000000; + + output O; + + input A0, A1, A2, A3, A4, D, WCLK, WE; + + reg [31:0] mem; + wire [4:0] adr; + + assign adr = {A4, A3, A2, A1, A0}; + assign O = mem[adr]; + + initial + mem = INIT; + + always @(posedge WCLK) + if (WE == 1'b1) + mem[adr] <= #100 D; + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/RAM32X1S_1.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/RAM32X1S_1.v new file mode 100644 index 0000000..92f05c8 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/RAM32X1S_1.v @@ -0,0 +1,46 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/RAM32X1S_1.v,v 1.8 2005/03/14 22:32:58 yanx Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Static Synchronous RAM 32-Deep by 1-Wide +// /___/ /\ Filename : RAM32X1S_1.v +// \ \ / \ Timestamp : Thu Mar 25 16:43:34 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 02/04/05 - Rev 0.0.1 Remove input/output bufs; Remove for-loop in initial block; +// End Revision + +`timescale 1 ps / 1 ps + + +module RAM32X1S_1 (O, A0, A1, A2, A3, A4, D, WCLK, WE); + + parameter INIT = 32'h00000000; + + output O; + + input A0, A1, A2, A3, A4, D, WCLK, WE; + + reg [31:0] mem; + wire [4:0] adr; + + assign adr = {A4, A3, A2, A1, A0}; + assign O = mem[adr]; + + initial + mem = INIT; + + always @(negedge WCLK) + if (WE == 1'b1) + mem[adr] <= #100 D; + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/RAM32X2S.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/RAM32X2S.v new file mode 100644 index 0000000..fac8ce2 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/RAM32X2S.v @@ -0,0 +1,55 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/RAM32X2S.v,v 1.9 2005/05/07 00:23:42 yanx Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Static Synchronous RAM 32-Deep by 2-Wide +// /___/ /\ Filename : RAM32X2S.v +// \ \ / \ Timestamp : Thu Mar 25 16:43:34 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 02/04/05 - Rev 0.0.1 Remove input/output bufs; Remove for-loop in initial block; +// 05/06/05 - Change adr from vector [3:0] to vector [4:0]. +// End Revision + +`timescale 1 ps / 1 ps + + +module RAM32X2S (O0, O1, A0, A1, A2, A3, A4, D0, D1, WCLK, WE); + + parameter INIT_00 = 32'h00000000; + parameter INIT_01 = 32'h00000000; + + output O0, O1; + + input A0, A1, A2, A3, A4, D0, D1, WCLK, WE; + + reg [31:0] mem1; + reg [31:0] mem2; + + wire [4:0] adr; + + assign adr = {A4, A3, A2, A1, A0}; + assign O0 = mem1[adr]; + assign O1 = mem2[adr]; + + initial begin + mem1 = INIT_00; + mem2 = INIT_01; + end + + always @(posedge WCLK) + if (WE == 1'b1) begin + mem1[adr] <= #100 D0; + mem2[adr] <= #100 D1; + end + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/RAM32X4S.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/RAM32X4S.v new file mode 100644 index 0000000..ae83cf9 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/RAM32X4S.v @@ -0,0 +1,64 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/RAM32X4S.v,v 1.8 2005/03/14 22:32:58 yanx Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Static Synchronous RAM 32-Deep by 4-Wide +// /___/ /\ Filename : RAM32X4S.v +// \ \ / \ Timestamp : Thu Mar 25 16:43:34 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 02/04/05 - Rev 0.0.1 Remove input/output bufs; Remove for-loop in initial block; +// End Revision + +`timescale 1 ps / 1 ps + + +module RAM32X4S (O0, O1, O2, O3, A0, A1, A2, A3, A4, D0, D1, D2, D3, WCLK, WE); + + parameter INIT_00 = 32'h00000000; + parameter INIT_01 = 32'h00000000; + parameter INIT_02 = 32'h00000000; + parameter INIT_03 = 32'h00000000; + + output O0, O1, O2, O3; + + input A0, A1, A2, A3, A4, D0, D1, D2, D3, WCLK, WE; + + reg [31:0] mem0; + reg [31:0] mem1; + reg [31:0] mem2; + reg [31:0] mem3; + + wire [4:0] adr; + + assign adr = {A4, A3, A2, A1, A0}; + assign O0 = mem0[adr]; + assign O1 = mem1[adr]; + assign O2 = mem2[adr]; + assign O3 = mem3[adr]; + + initial begin + mem0 = INIT_00; + mem1 = INIT_01; + mem2 = INIT_02; + mem3 = INIT_03; + end + + always @(posedge WCLK) + if (WE == 1'b1) begin + mem0[adr] <= #100 D0; + mem1[adr] <= #100 D1; + mem2[adr] <= #100 D2; + mem3[adr] <= #100 D3; + end + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/RAM32X8S.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/RAM32X8S.v new file mode 100644 index 0000000..9ecbb52 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/RAM32X8S.v @@ -0,0 +1,59 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/RAM32X8S.v,v 1.9 2005/05/23 22:42:09 yanx Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Static Synchronous RAM 32-Deep by 8-Wide +// /___/ /\ Filename : RAM32X8S.v +// \ \ / \ Timestamp : Thu Mar 25 16:43:34 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 02/04/05 - Rev 0.0.1 Remove input/output bufs; Remove for-loop in initial block; +// 05/23/05 - Change initial order (BugTrack#194). +// End Revision + +`timescale 1 ps / 1 ps + + +module RAM32X8S (O, A0, A1, A2, A3, A4, D, WCLK, WE); + + parameter INIT_00 = 32'h00000000; + parameter INIT_01 = 32'h00000000; + parameter INIT_02 = 32'h00000000; + parameter INIT_03 = 32'h00000000; + parameter INIT_04 = 32'h00000000; + parameter INIT_05 = 32'h00000000; + parameter INIT_06 = 32'h00000000; + parameter INIT_07 = 32'h00000000; + + output [7:0] O; + + input A0, A1, A2, A3, A4, WCLK, WE; + input [7:0] D; + + reg [7:0] mem [31:0]; + integer i; + + wire [4:0] adr; + + assign adr = {A4, A3, A2, A1, A0}; + assign O = mem[adr]; + + initial + for (i = 0; i < 32; i=i+1) + mem[i] = {INIT_07[i], INIT_06[i], INIT_05[i], INIT_04[i], INIT_03[i], INIT_02[i], + INIT_01[i], INIT_00[i]}; + + always @(posedge WCLK) + if (WE == 1'b1) + mem[adr] <= #100 D; + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/RAM64M.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/RAM64M.v new file mode 100644 index 0000000..5ca0df4 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/RAM64M.v @@ -0,0 +1,67 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/rainier/RAM64M.v,v 1.5 2010/01/14 00:42:01 yanx Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Function Simulation Library Component +// / / 64-Deep by 4-bit Wide Multi Port RAM +// /___/ /\ Filename : RAM64M.v +// \ \ / \ Timestamp : +// \___\/\___\ +// +// Revision: +// 03/21/06 - Initial version. +// 01/13/10 - Remove notifier block (CR544157) +// End Revision + +`timescale 1 ps/1 ps + +module RAM64M (DOA, DOB, DOC, DOD, ADDRA, ADDRB, ADDRC, ADDRD, DIA, DIB, DIC, DID, WCLK, WE); + + parameter INIT_A = 64'h0000000000000000; + parameter INIT_B = 64'h0000000000000000; + parameter INIT_C = 64'h0000000000000000; + parameter INIT_D = 64'h0000000000000000; + + output DOA; + output DOB; + output DOC; + output DOD; + input [5:0] ADDRA; + input [5:0] ADDRB; + input [5:0] ADDRC; + input [5:0] ADDRD; + input DIA; + input DIB; + input DIC; + input DID; + input WCLK; + input WE; + + reg [63:0] mem_a, mem_b, mem_c, mem_d; + + initial begin + mem_a = INIT_A; + mem_b = INIT_B; + mem_c = INIT_C; + mem_d = INIT_D; + end + + always @(posedge WCLK) + if (WE) begin + mem_a[ADDRD] <= #100 DIA; + mem_b[ADDRD] <= #100 DIB; + mem_c[ADDRD] <= #100 DIC; + mem_d[ADDRD] <= #100 DID; + end + + assign DOA = mem_a[ADDRA]; + assign DOB = mem_b[ADDRB]; + assign DOC = mem_c[ADDRC]; + assign DOD = mem_d[ADDRD]; + +endmodule diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/RAM64X1D.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/RAM64X1D.v new file mode 100644 index 0000000..70bc3cc --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/RAM64X1D.v @@ -0,0 +1,47 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/RAM64X1D.v,v 1.8 2005/03/14 22:32:58 yanx Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Static Dual Port Synchronous RAM 64-Deep by 1-Wide +// /___/ /\ Filename : RAM64X1D.v +// \ \ / \ Timestamp : Thu Mar 25 16:43:34 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 02/04/05 - Rev 0.0.1 Remove input/output bufs; Remove for-loop in initial block; +// End Revision + +`timescale 1 ps / 1 ps + + +module RAM64X1D (DPO, SPO, A0, A1, A2, A3, A4, A5, D, DPRA0, DPRA1, DPRA2, DPRA3, DPRA4, DPRA5, WCLK, WE); + + parameter INIT = 64'h0000000000000000; + + output DPO, SPO; + + input A0, A1, A2, A3, A4, A5, D, DPRA0, DPRA1, DPRA2, DPRA3, DPRA4, DPRA5, WCLK, WE; + + reg [63:0] mem; + wire [5:0] adr; + + assign adr = {A5, A4, A3, A2, A1, A0}; + assign SPO = mem[adr]; + assign DPO = mem[{DPRA5, DPRA4, DPRA3, DPRA2, DPRA1, DPRA0}]; + + initial + mem = INIT; + + always @(posedge WCLK) + if (WE == 1'b1) + mem[adr] <= #100 D; + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/RAM64X1D_1.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/RAM64X1D_1.v new file mode 100644 index 0000000..743584c --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/RAM64X1D_1.v @@ -0,0 +1,47 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/RAM64X1D_1.v,v 1.8 2005/03/14 22:32:58 yanx Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Static Dual Port Synchronous RAM 64-Deep by 1-Wide +// /___/ /\ Filename : RAM64X1D_1.v +// \ \ / \ Timestamp : Thu Mar 25 16:43:34 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 02/04/05 - Rev 0.0.1 Remove input/output bufs; Remove for-loop in initial block; +// End Revision + +`timescale 1 ps / 1 ps + + +module RAM64X1D_1 (DPO, SPO, A0, A1, A2, A3, A4, A5, D, DPRA0, DPRA1, DPRA2, DPRA3, DPRA4, DPRA5, WCLK, WE); + + parameter INIT = 64'h0000000000000000; + + output DPO, SPO; + + input A0, A1, A2, A3, A4, A5, D, DPRA0, DPRA1, DPRA2, DPRA3, DPRA4, DPRA5, WCLK, WE; + + reg [63:0] mem; + wire [5:0] adr; + + assign adr = {A5, A4, A3, A2, A1, A0}; + assign SPO = mem[adr]; + assign DPO = mem[{DPRA5, DPRA4, DPRA3, DPRA2, DPRA1, DPRA0}]; + + initial + mem = INIT; + + always @(negedge WCLK) + if (WE == 1'b1) + mem[adr] <= #100 D; + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/RAM64X1S.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/RAM64X1S.v new file mode 100644 index 0000000..a7f3475 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/RAM64X1S.v @@ -0,0 +1,46 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/RAM64X1S.v,v 1.8 2005/03/14 22:32:58 yanx Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Static Synchronous RAM 64-Deep by 1-Wide +// /___/ /\ Filename : RAM64X1S.v +// \ \ / \ Timestamp : Thu Mar 25 16:43:34 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 02/04/05 - Rev 0.0.1 Remove input/output bufs; Remove for-loop in initial block; +// End Revision + +`timescale 1 ps / 1 ps + + +module RAM64X1S (O, A0, A1, A2, A3, A4, A5, D, WCLK, WE); + + parameter INIT = 64'h0000000000000000; + + output O; + + input A0, A1, A2, A3, A4, A5, D, WCLK, WE; + + reg [63:0] mem; + wire [5:0] adr; + + assign adr = {A5, A4, A3, A2, A1, A0}; + assign O = mem[adr]; + + initial + mem = INIT; + + always @(posedge WCLK) + if (WE == 1'b1) + mem[adr] <= #100 D; + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/RAM64X1S_1.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/RAM64X1S_1.v new file mode 100644 index 0000000..5c977ba --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/RAM64X1S_1.v @@ -0,0 +1,46 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/RAM64X1S_1.v,v 1.8 2005/03/14 22:32:58 yanx Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Static Synchronous RAM 64-Deep by 1-Wide +// /___/ /\ Filename : RAM64X1S_1.v +// \ \ / \ Timestamp : Thu Mar 25 16:43:34 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 02/04/05 - Rev 0.0.1 Remove input/output bufs; Remove for-loop in initial block; +// End Revision + +`timescale 1 ps / 1 ps + + +module RAM64X1S_1 (O, A0, A1, A2, A3, A4, A5, D, WCLK, WE); + + parameter INIT = 64'h0000000000000000; + + output O; + + input A0, A1, A2, A3, A4, A5, D, WCLK, WE; + + reg [63:0] mem; + wire [5:0] adr; + + assign adr = {A5, A4, A3, A2, A1, A0}; + assign O = mem[adr]; + + initial + mem = INIT; + + always @(negedge WCLK) + if (WE == 1'b1) + mem[adr] <= #100 D; + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/RAM64X2S.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/RAM64X2S.v new file mode 100644 index 0000000..a349658 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/RAM64X2S.v @@ -0,0 +1,54 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/RAM64X2S.v,v 1.8 2005/03/14 22:32:58 yanx Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Static Synchronous RAM 64-Deep by 2-Wide +// /___/ /\ Filename : RAM64X2S.v +// \ \ / \ Timestamp : Thu Mar 25 16:43:34 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 02/04/05 - Rev 0.0.1 Remove input/output bufs; Remove for-loop in initial block; +// End Revision + +`timescale 1 ps / 1 ps + + +module RAM64X2S (O0, O1, A0, A1, A2, A3, A4, A5, D0, D1, WCLK, WE); + + parameter INIT_00 = 64'h0000000000000000; + parameter INIT_01 = 64'h0000000000000000; + + output O0, O1; + + input A0, A1, A2, A3, A4, A5, D0, D1, WCLK, WE; + + reg [63:0] mem1; + reg [63:0] mem2; + + wire [5:0] adr; + + assign adr = {A5, A4, A3, A2, A1, A0}; + assign O0 = mem1[adr]; + assign O1 = mem2[adr]; + + initial begin + mem1 = INIT_00; + mem2 = INIT_01; + end + + always @(posedge WCLK) + if (WE == 1'b1) begin + mem1[adr] <= #100 D0; + mem2[adr] <= #100 D1; + end + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/RAMB16.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/RAMB16.v new file mode 100644 index 0000000..cd8869d --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/RAMB16.v @@ -0,0 +1,366 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/virtex4/RAMB16.v,v 1.26 2007/06/06 22:10:08 wloo Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2005 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / 16K-Bit Data and 2K-Bit Parity Dual Port Block RAM +// /___/ /\ Filename : RAMB16.v +// \ \ / \ Timestamp : Thu Mar 11 16:43:59 PST 2005 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 03/11/05 - Added LOC parameter, removed GSR ports and initialized outputs. +// 03/18/05 - Added output register for ECC. +// 06/20/05 - Removed LOC from unisims. +// 07/11/05 - Fixed output to clear from X's, when GSR deasserted and SSR was high. +// 06/27/06 - Added 2 dimensional memory array feature. +// 01/24/07 - Added support of memory file to initialize memory and parity (CR 431584). +// 02/13/07 - Fixed register output in cascaded mode (CR 433819). +// 03/14/07 - Removed attribute INITP_FILE (CR 436003). +// 04/03/07 - Changed INIT_FILE = "NONE" as default (CR 436812). +// 06/06/07 - Added wire declaration for internal signals. +// End Revision + +`timescale 1 ps/1 ps +module RAMB16 (CASCADEOUTA, CASCADEOUTB, DOA, DOB, DOPA, DOPB, + ADDRA, ADDRB, CASCADEINA, CASCADEINB, CLKA, CLKB, DIA, DIB, DIPA, DIPB, ENA, ENB, REGCEA, REGCEB, SSRA, SSRB, WEA, WEB); + + parameter integer DOA_REG = 0; + parameter integer DOB_REG = 0; + parameter INITP_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_A = 36'h0; + parameter INIT_B = 36'h0; + parameter INIT_FILE = "NONE"; + parameter INVERT_CLK_DOA_REG = "FALSE"; + parameter INVERT_CLK_DOB_REG = "FALSE"; + parameter RAM_EXTENSION_A = "NONE"; + parameter RAM_EXTENSION_B = "NONE"; + parameter integer READ_WIDTH_A = 0; + parameter integer READ_WIDTH_B = 0; + parameter SIM_COLLISION_CHECK = "ALL"; + parameter SRVAL_A = 36'h0; + parameter SRVAL_B = 36'h0; + parameter WRITE_MODE_A = "WRITE_FIRST"; + parameter WRITE_MODE_B = "WRITE_FIRST"; + parameter integer WRITE_WIDTH_A = 0; + parameter integer WRITE_WIDTH_B = 0; + + output CASCADEOUTA; + output CASCADEOUTB; + output [31:0] DOA; + output [31:0] DOB; + output [3:0] DOPA; + output [3:0] DOPB; + + input ENA, CLKA, SSRA, CASCADEINA, REGCEA; + input ENB, CLKB, SSRB, CASCADEINB, REGCEB; + input [14:0] ADDRA; + input [14:0] ADDRB; + input [31:0] DIA; + input [31:0] DIB; + input [3:0] DIPA; + input [3:0] DIPB; + input [3:0] WEA; + input [3:0] WEB; + + tri0 GSR = glbl.GSR; + + localparam SETUP_ALL = 1000; + localparam SETUP_READ_FIRST = 3000; + + wire [31:0] dangle_out32; + wire [3:0] dangle_out4; + wire [7:0] dangle_out8; + wire dangle_out; + wire cascadeoutlata_wire, cascadeoutlatb_wire, cascadeoutrega_wire, cascadeoutregb_wire; + wire clka_wire, clkb_wire; + + assign clka_wire = (DOA_REG == 1 && INVERT_CLK_DOA_REG == "TRUE") ? ~CLKA : CLKA; + assign clkb_wire = (DOB_REG == 1 && INVERT_CLK_DOB_REG == "TRUE") ? ~CLKB : CLKB; + + initial begin + + if ((INVERT_CLK_DOA_REG == "TRUE") && (DOA_REG != 1)) begin + $display("Attribute Syntax Error : When INVERT_CLK_DOA_REG is set to TRUE, then DOA_REG has to be set to 1."); + $finish; + end + + if ((INVERT_CLK_DOB_REG == "TRUE") && (DOB_REG != 1)) begin + $display("Attribute Syntax Error : When INVERT_CLK_DOB_REG is set to TRUE, then DOB_REG has to be set to 1."); + $finish; + end + + if ((INVERT_CLK_DOA_REG != "FALSE") && (INVERT_CLK_DOA_REG != "TRUE")) begin + $display("Attribute Syntax Error : The attribute INVERT_CLK_DOA_REG on RAMB16 instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", INVERT_CLK_DOA_REG); + $finish; + end + + if ((INVERT_CLK_DOB_REG != "FALSE") && (INVERT_CLK_DOB_REG != "TRUE")) begin + $display("Attribute Syntax Error : The attribute INVERT_CLK_DOB_REG on RAMB16 instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", INVERT_CLK_DOB_REG); + $finish; + end + + end + + assign CASCADEOUTA = (DOA_REG == 1) ? cascadeoutrega_wire : cascadeoutlata_wire; + assign CASCADEOUTB = (DOB_REG == 1) ? cascadeoutregb_wire : cascadeoutlatb_wire; + + ARAMB36_INTERNAL INT_RAMB (.DIA({32'b0,DIA}), .ENA(ENA), .WEA({2{WEA}}), .SSRA(SSRA), .ADDRA({ADDRA[14],1'b0,ADDRA[13:0]}), .CLKA(CLKA), .DOA({dangle_out32,DOA}), .DIB({32'b0,DIB}), .ENB(ENB), .WEB({2{WEB}}), .SSRB(SSRB), .ADDRB({ADDRB[14],1'b0,ADDRB[13:0]}), .CLKB(CLKB), .DOB(DOB), .GSR(GSR), .DOPA({dangle_out4,DOPA}), .DOPB(DOPB), .DIPA(DIPA), .DIPB({4'b0,DIPB}), .CASCADEOUTLATA(cascadeoutlata_wire), .CASCADEOUTLATB(cascadeoutlatb_wire), .CASCADEOUTREGA(cascadeoutrega_wire), .CASCADEOUTREGB(cascadeoutregb_wire), .CASCADEINLATA(CASCADEINA), .CASCADEINLATB(CASCADEINB), .CASCADEINREGA(CASCADEINA), .CASCADEINREGB(CASCADEINB), .REGCEA(REGCEA), .REGCEB(REGCEB), .REGCLKA(clka_wire), .REGCLKB(clkb_wire), .DBITERR(dangle_out), .ECCPARITY(dangle_out8), .SBITERR(dangle_out)); + + defparam INT_RAMB.BRAM_SIZE = 16; + defparam INT_RAMB.BRAM_MODE = "TRUE_DUAL_PORT"; + defparam INT_RAMB.INIT_A = INIT_A; + defparam INT_RAMB.INIT_B = INIT_B; + defparam INT_RAMB.INIT_FILE = INIT_FILE; + defparam INT_RAMB.SRVAL_A = SRVAL_A; + defparam INT_RAMB.SRVAL_B = SRVAL_B; + defparam INT_RAMB.RAM_EXTENSION_A = RAM_EXTENSION_A; + defparam INT_RAMB.RAM_EXTENSION_B = RAM_EXTENSION_B; + defparam INT_RAMB.READ_WIDTH_A = READ_WIDTH_A; + defparam INT_RAMB.READ_WIDTH_B = READ_WIDTH_B; + defparam INT_RAMB.WRITE_WIDTH_A = WRITE_WIDTH_A; + defparam INT_RAMB.WRITE_WIDTH_B = WRITE_WIDTH_B; + defparam INT_RAMB.WRITE_MODE_A = WRITE_MODE_A; + defparam INT_RAMB.WRITE_MODE_B = WRITE_MODE_B; + defparam INT_RAMB.SETUP_ALL = SETUP_ALL; + defparam INT_RAMB.SETUP_READ_FIRST = SETUP_READ_FIRST; + defparam INT_RAMB.SIM_COLLISION_CHECK = SIM_COLLISION_CHECK; + defparam INT_RAMB.EN_ECC_READ = "FALSE"; + defparam INT_RAMB.EN_ECC_SCRUB = "FALSE"; + defparam INT_RAMB.EN_ECC_WRITE = "FALSE"; + defparam INT_RAMB.DOA_REG = DOA_REG; + defparam INT_RAMB.DOB_REG = DOB_REG; + defparam INT_RAMB.INIT_00 = INIT_00; + defparam INT_RAMB.INIT_01 = INIT_01; + defparam INT_RAMB.INIT_02 = INIT_02; + defparam INT_RAMB.INIT_03 = INIT_03; + defparam INT_RAMB.INIT_04 = INIT_04; + defparam INT_RAMB.INIT_05 = INIT_05; + defparam INT_RAMB.INIT_06 = INIT_06; + defparam INT_RAMB.INIT_07 = INIT_07; + defparam INT_RAMB.INIT_08 = INIT_08; + defparam INT_RAMB.INIT_09 = INIT_09; + defparam INT_RAMB.INIT_0A = INIT_0A; + defparam INT_RAMB.INIT_0B = INIT_0B; + defparam INT_RAMB.INIT_0C = INIT_0C; + defparam INT_RAMB.INIT_0D = INIT_0D; + defparam INT_RAMB.INIT_0E = INIT_0E; + defparam INT_RAMB.INIT_0F = INIT_0F; + defparam INT_RAMB.INIT_10 = INIT_10; + defparam INT_RAMB.INIT_11 = INIT_11; + defparam INT_RAMB.INIT_12 = INIT_12; + defparam INT_RAMB.INIT_13 = INIT_13; + defparam INT_RAMB.INIT_14 = INIT_14; + defparam INT_RAMB.INIT_15 = INIT_15; + defparam INT_RAMB.INIT_16 = INIT_16; + defparam INT_RAMB.INIT_17 = INIT_17; + defparam INT_RAMB.INIT_18 = INIT_18; + defparam INT_RAMB.INIT_19 = INIT_19; + defparam INT_RAMB.INIT_1A = INIT_1A; + defparam INT_RAMB.INIT_1B = INIT_1B; + defparam INT_RAMB.INIT_1C = INIT_1C; + defparam INT_RAMB.INIT_1D = INIT_1D; + defparam INT_RAMB.INIT_1E = INIT_1E; + defparam INT_RAMB.INIT_1F = INIT_1F; + defparam INT_RAMB.INIT_20 = INIT_20; + defparam INT_RAMB.INIT_21 = INIT_21; + defparam INT_RAMB.INIT_22 = INIT_22; + defparam INT_RAMB.INIT_23 = INIT_23; + defparam INT_RAMB.INIT_24 = INIT_24; + defparam INT_RAMB.INIT_25 = INIT_25; + defparam INT_RAMB.INIT_26 = INIT_26; + defparam INT_RAMB.INIT_27 = INIT_27; + defparam INT_RAMB.INIT_28 = INIT_28; + defparam INT_RAMB.INIT_29 = INIT_29; + defparam INT_RAMB.INIT_2A = INIT_2A; + defparam INT_RAMB.INIT_2B = INIT_2B; + defparam INT_RAMB.INIT_2C = INIT_2C; + defparam INT_RAMB.INIT_2D = INIT_2D; + defparam INT_RAMB.INIT_2E = INIT_2E; + defparam INT_RAMB.INIT_2F = INIT_2F; + defparam INT_RAMB.INIT_30 = INIT_30; + defparam INT_RAMB.INIT_31 = INIT_31; + defparam INT_RAMB.INIT_32 = INIT_32; + defparam INT_RAMB.INIT_33 = INIT_33; + defparam INT_RAMB.INIT_34 = INIT_34; + defparam INT_RAMB.INIT_35 = INIT_35; + defparam INT_RAMB.INIT_36 = INIT_36; + defparam INT_RAMB.INIT_37 = INIT_37; + defparam INT_RAMB.INIT_38 = INIT_38; + defparam INT_RAMB.INIT_39 = INIT_39; + defparam INT_RAMB.INIT_3A = INIT_3A; + defparam INT_RAMB.INIT_3B = INIT_3B; + defparam INT_RAMB.INIT_3C = INIT_3C; + defparam INT_RAMB.INIT_3D = INIT_3D; + defparam INT_RAMB.INIT_3E = INIT_3E; + defparam INT_RAMB.INIT_3F = INIT_3F; + defparam INT_RAMB.INITP_00 = INITP_00; + defparam INT_RAMB.INITP_01 = INITP_01; + defparam INT_RAMB.INITP_02 = INITP_02; + defparam INT_RAMB.INITP_03 = INITP_03; + defparam INT_RAMB.INITP_04 = INITP_04; + defparam INT_RAMB.INITP_05 = INITP_05; + defparam INT_RAMB.INITP_06 = INITP_06; + defparam INT_RAMB.INITP_07 = INITP_07; + + //*** Timing Checks Start here + + specify + + (CLKA => DOA[0]) = (100, 100); + (CLKA => DOA[1]) = (100, 100); + (CLKA => DOA[2]) = (100, 100); + (CLKA => DOA[3]) = (100, 100); + (CLKA => DOA[4]) = (100, 100); + (CLKA => DOA[5]) = (100, 100); + (CLKA => DOA[6]) = (100, 100); + (CLKA => DOA[7]) = (100, 100); + (CLKA => DOA[8]) = (100, 100); + (CLKA => DOA[9]) = (100, 100); + (CLKA => DOA[10]) = (100, 100); + (CLKA => DOA[11]) = (100, 100); + (CLKA => DOA[12]) = (100, 100); + (CLKA => DOA[13]) = (100, 100); + (CLKA => DOA[14]) = (100, 100); + (CLKA => DOA[15]) = (100, 100); + (CLKA => DOA[16]) = (100, 100); + (CLKA => DOA[17]) = (100, 100); + (CLKA => DOA[18]) = (100, 100); + (CLKA => DOA[19]) = (100, 100); + (CLKA => DOA[20]) = (100, 100); + (CLKA => DOA[21]) = (100, 100); + (CLKA => DOA[22]) = (100, 100); + (CLKA => DOA[23]) = (100, 100); + (CLKA => DOA[24]) = (100, 100); + (CLKA => DOA[25]) = (100, 100); + (CLKA => DOA[26]) = (100, 100); + (CLKA => DOA[27]) = (100, 100); + (CLKA => DOA[28]) = (100, 100); + (CLKA => DOA[29]) = (100, 100); + (CLKA => DOA[30]) = (100, 100); + (CLKA => DOA[31]) = (100, 100); + (CLKA => DOPA[0]) = (100, 100); + (CLKA => DOPA[1]) = (100, 100); + (CLKA => DOPA[2]) = (100, 100); + (CLKA => DOPA[3]) = (100, 100); + (CLKA => CASCADEOUTA) = (100, 100); + + (CLKB => DOB[0]) = (100, 100); + (CLKB => DOB[1]) = (100, 100); + (CLKB => DOB[2]) = (100, 100); + (CLKB => DOB[3]) = (100, 100); + (CLKB => DOB[4]) = (100, 100); + (CLKB => DOB[5]) = (100, 100); + (CLKB => DOB[6]) = (100, 100); + (CLKB => DOB[7]) = (100, 100); + (CLKB => DOB[8]) = (100, 100); + (CLKB => DOB[9]) = (100, 100); + (CLKB => DOB[10]) = (100, 100); + (CLKB => DOB[11]) = (100, 100); + (CLKB => DOB[12]) = (100, 100); + (CLKB => DOB[13]) = (100, 100); + (CLKB => DOB[14]) = (100, 100); + (CLKB => DOB[15]) = (100, 100); + (CLKB => DOB[16]) = (100, 100); + (CLKB => DOB[17]) = (100, 100); + (CLKB => DOB[18]) = (100, 100); + (CLKB => DOB[19]) = (100, 100); + (CLKB => DOB[20]) = (100, 100); + (CLKB => DOB[21]) = (100, 100); + (CLKB => DOB[22]) = (100, 100); + (CLKB => DOB[23]) = (100, 100); + (CLKB => DOB[24]) = (100, 100); + (CLKB => DOB[25]) = (100, 100); + (CLKB => DOB[26]) = (100, 100); + (CLKB => DOB[27]) = (100, 100); + (CLKB => DOB[28]) = (100, 100); + (CLKB => DOB[29]) = (100, 100); + (CLKB => DOB[30]) = (100, 100); + (CLKB => DOB[31]) = (100, 100); + (CLKB => DOPB[0]) = (100, 100); + (CLKB => DOPB[1]) = (100, 100); + (CLKB => DOPB[2]) = (100, 100); + (CLKB => DOPB[3]) = (100, 100); + (CLKB => CASCADEOUTB) = (100, 100); + specparam PATHPULSE$ = 0; + + endspecify + +endmodule // RAMB16 diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/RAMB16BWE.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/RAMB16BWE.v new file mode 100644 index 0000000..eaedc9e --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/RAMB16BWE.v @@ -0,0 +1,1542 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/trilogy/RAMB16BWE.v,v 1.12 2009/12/17 19:41:39 wloo Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2009 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component 16K-Bit Data and +// / / 2K-Bit Parity Dual Port Block RAM. +// /___/ /\ Filename : RAMB16BWE.v +// \ \ / \ Timestamp : Wed Sep 9 15:21:09 PDT 2009 +// \___\/\___\ +// +// Revision: +// 09/09/09 - Initial version. +// 12/16/09 - Enhanced memory initialization (CR 540764). +// End Revision + +`timescale 1 ps/1 ps + +module RAMB16BWE (DOA, DOB, DOPA, DOPB, + ADDRA, ADDRB, CLKA, CLKB, DIA, DIB, DIPA, DIPB, ENA, ENB, SSRA, SSRB, WEA, WEB); + + parameter integer DATA_WIDTH_A = 0; + parameter integer DATA_WIDTH_B = 0; + parameter INITP_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_A = 36'h0; + parameter INIT_B = 36'h0; + parameter INIT_FILE = "NONE"; + parameter SIM_COLLISION_CHECK = "ALL"; + parameter SRVAL_A = 36'h0; + parameter SRVAL_B = 36'h0; + parameter WRITE_MODE_A = "WRITE_FIRST"; + parameter WRITE_MODE_B = "WRITE_FIRST"; + + output [31:0] DOA; + output [31:0] DOB; + output [3:0] DOPA; + output [3:0] DOPB; + + input [13:0] ADDRA; + input [13:0] ADDRB; + input CLKA; + input CLKB; + input [31:0] DIA; + input [31:0] DIB; + input [3:0] DIPA; + input [3:0] DIPB; + input ENA; + input ENB; + input SSRA; + input SSRB; + input [3:0] WEA; + input [3:0] WEB; + + + localparam SETUP_ALL = 1000; + localparam SETUP_READ_FIRST = 3000; + + localparam widest_width = (DATA_WIDTH_A >= DATA_WIDTH_B) ? DATA_WIDTH_A : DATA_WIDTH_B; + + localparam a_width = (DATA_WIDTH_A == 1) ? 1 : (DATA_WIDTH_A == 2) ? 2 : (DATA_WIDTH_A == 4) ? 4 : + (DATA_WIDTH_A == 9) ? 8 : (DATA_WIDTH_A == 18) ? 16 : (DATA_WIDTH_A == 36) ? 32 : 32; + + localparam b_width = (DATA_WIDTH_B == 1) ? 1 : (DATA_WIDTH_B == 2) ? 2 : (DATA_WIDTH_B == 4) ? 4 : + (DATA_WIDTH_B == 9) ? 8 : (DATA_WIDTH_B == 18) ? 16 : (DATA_WIDTH_B == 36) ? 32 : 32; + + localparam a_widthp = (DATA_WIDTH_A == 9) ? 1 : (DATA_WIDTH_A == 18) ? 2 : (DATA_WIDTH_A == 36) ? 4 : 4; + + localparam b_widthp = (DATA_WIDTH_B == 9) ? 1 : (DATA_WIDTH_B == 18) ? 2 : (DATA_WIDTH_B == 36) ? 4 : 4; + + localparam col_addr_lsb = (widest_width == 1) ? 0 : (widest_width == 2) ? 1 : (widest_width == 4) ? 2 : + (widest_width == 9) ? 3 : (widest_width == 18) ? 4 : (widest_width == 36) ? 5 : 0; + + localparam width = (widest_width == 1) ? 1 : (widest_width == 2) ? 2 : (widest_width == 4) ? 4 : + (widest_width == 9) ? 8 : (widest_width == 18) ? 16 : (widest_width == 36) ? 32 : 32; + + localparam widthp = (widest_width == 9) ? 1 : (widest_width == 18) ? 2 : (widest_width == 36) ? 4 : 4; + + localparam addrawraddr_lbit_124 = (DATA_WIDTH_A == 1) ? 0 : (DATA_WIDTH_A == 2) ? 1 : + (DATA_WIDTH_A == 4) ? 2 : (DATA_WIDTH_A == 9) ? 3 : + (DATA_WIDTH_A == 18) ? 4 : (DATA_WIDTH_A == 36) ? 5 : 5; + + localparam addrbrdaddr_lbit_124 = (DATA_WIDTH_B == 1) ? 0 : (DATA_WIDTH_B == 2) ? 1 : + (DATA_WIDTH_B == 4) ? 2 : (DATA_WIDTH_B == 9) ? 3 : + (DATA_WIDTH_B == 18) ? 4 : (DATA_WIDTH_B == 36) ? 5 : 5; + + localparam addrawraddr_bit_124 = (DATA_WIDTH_A == 1 && widest_width == 2) ? 0 : (DATA_WIDTH_A == 1 && widest_width == 4) ? 1 : + (DATA_WIDTH_A == 1 && widest_width == 9) ? 2 : (DATA_WIDTH_A == 1 && widest_width == 18) ? 3 : + (DATA_WIDTH_A == 1 && widest_width == 36) ? 4 : (DATA_WIDTH_A == 2 && widest_width == 4) ? 1 : + (DATA_WIDTH_A == 2 && widest_width == 9) ? 2 : (DATA_WIDTH_A == 2 && widest_width == 18) ? 3 : + (DATA_WIDTH_A == 2 && widest_width == 36) ? 4 : (DATA_WIDTH_A == 4 && widest_width == 9) ? 2 : + (DATA_WIDTH_A == 4 && widest_width == 18) ? 3 : (DATA_WIDTH_A == 4 && widest_width == 36) ? 4 : 5; + + localparam addrbrdaddr_bit_124 = (DATA_WIDTH_B == 1 && widest_width == 2) ? 0 : (DATA_WIDTH_B == 1 && widest_width == 4) ? 1 : + (DATA_WIDTH_B == 1 && widest_width == 9) ? 2 : (DATA_WIDTH_B == 1 && widest_width == 18) ? 3 : + (DATA_WIDTH_B == 1 && widest_width == 36) ? 4 : (DATA_WIDTH_B == 2 && widest_width == 4) ? 1 : + (DATA_WIDTH_B == 2 && widest_width == 9) ? 2 : (DATA_WIDTH_B == 2 && widest_width == 18) ? 3 : + (DATA_WIDTH_B == 2 && widest_width == 36) ? 4 : (DATA_WIDTH_B == 4 && widest_width == 9) ? 2 : + (DATA_WIDTH_B == 4 && widest_width == 18) ? 3 : (DATA_WIDTH_B == 4 && widest_width == 36) ? 4 : 5; + + localparam addrawraddr_bit_8 = (DATA_WIDTH_A == 9 && widest_width == 18) ? 3 : (DATA_WIDTH_A == 9 && widest_width == 36) ? 4 : 4; + + localparam addrawraddr_bit_16 = 4; // There is only 36 larger than 18 + + localparam addrbrdaddr_bit_8 = (DATA_WIDTH_B == 9 && widest_width == 18) ? 3 : (DATA_WIDTH_B == 9 && widest_width == 36) ? 4 : 4; + + localparam addrbrdaddr_bit_16 = 4; // There is only 36 larger than 18 + + + localparam mem_depth = (widest_width == 1) ? 16384 : (widest_width == 2) ? 8192 : (widest_width == 4) ? 4096 : (widest_width == 9) ? 2048 : + (widest_width == 18) ? 1024 :(widest_width == 36) ? 512 : 16384; + + localparam memp_depth = (widest_width == 9) ? 2048 : (widest_width == 18) ? 1024 : (widest_width == 36) ? 512 : 2048; + + reg [widest_width-1:0] tmp_mem [mem_depth-1:0]; + + reg [width-1:0] mem [mem_depth-1:0]; + reg [widthp-1:0] memp [memp_depth-1:0]; + + integer count, countp, init_mult, initp_mult; + integer count1, countp1, i_mem, init_offset, initp_offset; + + reg tmp1; + reg [1:0] wr_mode_a, wr_mode_b; + + reg [31:0] doado_out = 32'b0, doado_buf = 32'b0; + reg [31:0] dobdo_out = 32'b0, dobdo_buf = 32'b0; + reg [3:0] dopbdop_out = 4'b0, dopbdop_buf = 4'b0; + reg [3:0] dopadop_out = 4'b0, dopadop_buf = 4'b0; + + reg [63:0] di_x = 64'bx; + + reg [7:0] weawel_reg; + reg enbrden_reg; + reg [7:0] webweu_reg, webweu_tmp; + reg rising_clkawrclk = 1'b0, rising_clkbrdclk = 1'b0; + reg [15:0] addrawraddr_reg, addrbrdaddr_reg, addrawraddr_tmp, addrbrdaddr_tmp; + + reg [63:0] diadi_reg, dibdi_reg; + reg [3:0] dipadip_reg; + reg [7:0] dipbdip_reg; + reg [1:0] viol_type = 2'b00, seq = 2'b00; + integer viol_time = 0; + reg col_wr_wr_msg = 1, col_wra_rdb_msg = 1, col_wrb_rda_msg = 1; + reg finish_error = 0; + + time curr_time, prev_time; + + wire [15:0] addrawraddr_in, addrbrdaddr_in; + wire clkawrclk_in, clkbrdclk_in; + + wire enawren_in, enbrden_in, rsta_in, rstbrst_in; + + wire [a_width-1:0] diadi_int; + wire [b_width-1:0] dibdi_int; + wire [a_widthp-1:0] dipadip_int; + wire [b_widthp-1:0] dipbdip_int; + wire [3:0] weawel_int, webweu_int; + + reg notifier, notifier_a, notifier_b; + reg notifier_addra0, notifier_addra1, notifier_addra2, notifier_addra3, notifier_addra4; + reg notifier_addra5, notifier_addra6, notifier_addra7, notifier_addra8, notifier_addra9; + reg notifier_addra10, notifier_addra11, notifier_addra12, notifier_addra13; + reg notifier_addrb0, notifier_addrb1, notifier_addrb2, notifier_addrb3, notifier_addrb4; + reg notifier_addrb5, notifier_addrb6, notifier_addrb7, notifier_addrb8, notifier_addrb9; + reg notifier_addrb10, notifier_addrb11, notifier_addrb12, notifier_addrb13; + + + tri0 gsr_in = glbl.GSR; + + assign clkawrclk_in = CLKA; + assign clkbrdclk_in = CLKB; + + assign diadi_int = DIA; + assign dibdi_int = DIB; + assign dipadip_int = DIPA; + assign dipbdip_int = DIPB; + assign DOA = doado_out; + assign DOPA = dopadop_out; + assign DOB = dobdo_out; + assign DOPB = dopbdop_out; + + assign enawren_in = ENA; + assign enbrden_in = ENB; + assign rsta_in = SSRA; + assign rstbrst_in = SSRB; + assign weawel_int = WEA; + assign webweu_int = WEB; + + assign addrawraddr_in = {2'b00,ADDRA}; + assign addrbrdaddr_in = {2'b00,ADDRB}; + + + initial begin + + if (INIT_FILE == "NONE") begin + + init_mult = 256/width; + + for (count = 0; count < init_mult; count = count + 1) begin + + init_offset = count * width; + + mem[count] = INIT_00[init_offset +:width]; + mem[count + (init_mult * 1)] = INIT_01[init_offset +:width]; + mem[count + (init_mult * 2)] = INIT_02[init_offset +:width]; + mem[count + (init_mult * 3)] = INIT_03[init_offset +:width]; + mem[count + (init_mult * 4)] = INIT_04[init_offset +:width]; + mem[count + (init_mult * 5)] = INIT_05[init_offset +:width]; + mem[count + (init_mult * 6)] = INIT_06[init_offset +:width]; + mem[count + (init_mult * 7)] = INIT_07[init_offset +:width]; + mem[count + (init_mult * 8)] = INIT_08[init_offset +:width]; + mem[count + (init_mult * 9)] = INIT_09[init_offset +:width]; + mem[count + (init_mult * 10)] = INIT_0A[init_offset +:width]; + mem[count + (init_mult * 11)] = INIT_0B[init_offset +:width]; + mem[count + (init_mult * 12)] = INIT_0C[init_offset +:width]; + mem[count + (init_mult * 13)] = INIT_0D[init_offset +:width]; + mem[count + (init_mult * 14)] = INIT_0E[init_offset +:width]; + mem[count + (init_mult * 15)] = INIT_0F[init_offset +:width]; + mem[count + (init_mult * 16)] = INIT_10[init_offset +:width]; + mem[count + (init_mult * 17)] = INIT_11[init_offset +:width]; + mem[count + (init_mult * 18)] = INIT_12[init_offset +:width]; + mem[count + (init_mult * 19)] = INIT_13[init_offset +:width]; + mem[count + (init_mult * 20)] = INIT_14[init_offset +:width]; + mem[count + (init_mult * 21)] = INIT_15[init_offset +:width]; + mem[count + (init_mult * 22)] = INIT_16[init_offset +:width]; + mem[count + (init_mult * 23)] = INIT_17[init_offset +:width]; + mem[count + (init_mult * 24)] = INIT_18[init_offset +:width]; + mem[count + (init_mult * 25)] = INIT_19[init_offset +:width]; + mem[count + (init_mult * 26)] = INIT_1A[init_offset +:width]; + mem[count + (init_mult * 27)] = INIT_1B[init_offset +:width]; + mem[count + (init_mult * 28)] = INIT_1C[init_offset +:width]; + mem[count + (init_mult * 29)] = INIT_1D[init_offset +:width]; + mem[count + (init_mult * 30)] = INIT_1E[init_offset +:width]; + mem[count + (init_mult * 31)] = INIT_1F[init_offset +:width]; + mem[count + (init_mult * 32)] = INIT_20[init_offset +:width]; + mem[count + (init_mult * 33)] = INIT_21[init_offset +:width]; + mem[count + (init_mult * 34)] = INIT_22[init_offset +:width]; + mem[count + (init_mult * 35)] = INIT_23[init_offset +:width]; + mem[count + (init_mult * 36)] = INIT_24[init_offset +:width]; + mem[count + (init_mult * 37)] = INIT_25[init_offset +:width]; + mem[count + (init_mult * 38)] = INIT_26[init_offset +:width]; + mem[count + (init_mult * 39)] = INIT_27[init_offset +:width]; + mem[count + (init_mult * 40)] = INIT_28[init_offset +:width]; + mem[count + (init_mult * 41)] = INIT_29[init_offset +:width]; + mem[count + (init_mult * 42)] = INIT_2A[init_offset +:width]; + mem[count + (init_mult * 43)] = INIT_2B[init_offset +:width]; + mem[count + (init_mult * 44)] = INIT_2C[init_offset +:width]; + mem[count + (init_mult * 45)] = INIT_2D[init_offset +:width]; + mem[count + (init_mult * 46)] = INIT_2E[init_offset +:width]; + mem[count + (init_mult * 47)] = INIT_2F[init_offset +:width]; + mem[count + (init_mult * 48)] = INIT_30[init_offset +:width]; + mem[count + (init_mult * 49)] = INIT_31[init_offset +:width]; + mem[count + (init_mult * 50)] = INIT_32[init_offset +:width]; + mem[count + (init_mult * 51)] = INIT_33[init_offset +:width]; + mem[count + (init_mult * 52)] = INIT_34[init_offset +:width]; + mem[count + (init_mult * 53)] = INIT_35[init_offset +:width]; + mem[count + (init_mult * 54)] = INIT_36[init_offset +:width]; + mem[count + (init_mult * 55)] = INIT_37[init_offset +:width]; + mem[count + (init_mult * 56)] = INIT_38[init_offset +:width]; + mem[count + (init_mult * 57)] = INIT_39[init_offset +:width]; + mem[count + (init_mult * 58)] = INIT_3A[init_offset +:width]; + mem[count + (init_mult * 59)] = INIT_3B[init_offset +:width]; + mem[count + (init_mult * 60)] = INIT_3C[init_offset +:width]; + mem[count + (init_mult * 61)] = INIT_3D[init_offset +:width]; + mem[count + (init_mult * 62)] = INIT_3E[init_offset +:width]; + mem[count + (init_mult * 63)] = INIT_3F[init_offset +:width]; + end // for (count = 0; count < init_mult; count = count + 1) + + + if (width >= 8) begin + + initp_mult = 256/widthp; + + for (countp = 0; countp < initp_mult; countp = countp + 1) begin + + initp_offset = countp * widthp; + + memp[countp] = INITP_00[initp_offset +:widthp]; + memp[countp + (initp_mult * 1)] = INITP_01[initp_offset +:widthp]; + memp[countp + (initp_mult * 2)] = INITP_02[initp_offset +:widthp]; + memp[countp + (initp_mult * 3)] = INITP_03[initp_offset +:widthp]; + memp[countp + (initp_mult * 4)] = INITP_04[initp_offset +:widthp]; + memp[countp + (initp_mult * 5)] = INITP_05[initp_offset +:widthp]; + memp[countp + (initp_mult * 6)] = INITP_06[initp_offset +:widthp]; + memp[countp + (initp_mult * 7)] = INITP_07[initp_offset +:widthp]; + + end // for (countp = 0; countp < initp_mult; countp = countp + 1) + end // if (width >= 8) + + end // if (INIT_FILE == "NONE") + + else begin + + $readmemh (INIT_FILE, tmp_mem); + + case (widest_width) + + 1, 2, 4 : for (i_mem = 0; i_mem <= mem_depth; i_mem = i_mem + 1) + mem[i_mem] = tmp_mem [i_mem]; + + 9 : for (i_mem = 0; i_mem <= mem_depth; i_mem = i_mem + 1) begin + mem[i_mem] = tmp_mem[i_mem][0 +: 8]; + memp[i_mem] = tmp_mem[i_mem][8 +: 1]; + end + + 18 : for (i_mem = 0; i_mem <= mem_depth; i_mem = i_mem + 1) begin + mem[i_mem] = tmp_mem[i_mem][0 +: 16]; + memp[i_mem] = tmp_mem[i_mem][16 +: 2]; + end + + 36 : for (i_mem = 0; i_mem <= mem_depth; i_mem = i_mem + 1) begin + mem[i_mem] = tmp_mem[i_mem][0 +: 32]; + memp[i_mem] = tmp_mem[i_mem][32 +: 4]; + end + + endcase // case(widest_width) + + end // else: !if(INIT_FILE == "NONE") + + + case (DATA_WIDTH_A) + + 0, 1, 2, 4, 9, 18, 36: ; + + default : begin + $display("Attribute Syntax Error : The attribute DATA_WIDTH_A on RAMB16BWE instance %m is set to %d. Legal values for this attribute are 0, 1, 2, 4, 9, 18 or 36.", DATA_WIDTH_A); + finish_error = 1; + end + + endcase // case(DATA_WIDTH_A) + + + case (DATA_WIDTH_B) + + 0, 1, 2, 4, 9, 18, 36: ; + + default : begin + $display("Attribute Syntax Error : The attribute DATA_WIDTH_B on RAMB16BWE instance %m is set to %d. Legal values for this attribute are 0, 1, 2, 4, 9, 18 or 36.", DATA_WIDTH_B); + finish_error = 1; + end + + endcase // case(DATA_WIDTH_B) + + + if (DATA_WIDTH_A == 0 && DATA_WIDTH_B == 0) begin + $display("Attribute Syntax Error : Attributes DATA_WIDTH_A and DATA_WIDTH_B on RAMB16BWE instance %m, both can not be 0."); + finish_error = 1; + end + + + case (WRITE_MODE_A) + "WRITE_FIRST" : wr_mode_a <= 2'b00; + "READ_FIRST" : wr_mode_a <= 2'b01; + "NO_CHANGE" : wr_mode_a <= 2'b10; + default : begin + $display("Attribute Syntax Error : The Attribute WRITE_MODE_A on RAMB16BWE instance %m is set to %s. Legal values for this attribute are WRITE_FIRST, READ_FIRST or NO_CHANGE.", WRITE_MODE_A); + finish_error = 1; + end + endcase + + + case (WRITE_MODE_B) + "WRITE_FIRST" : wr_mode_b <= 2'b00; + "READ_FIRST" : wr_mode_b <= 2'b01; + "NO_CHANGE" : wr_mode_b <= 2'b10; + default : begin + $display("Attribute Syntax Error : The Attribute WRITE_MODE_B on RAMB16BWE instance %m is set to %s. Legal values for this attribute are WRITE_FIRST, READ_FIRST or NO_CHANGE.", WRITE_MODE_B); + finish_error = 1; + end + endcase + + + if ((SIM_COLLISION_CHECK != "ALL") && (SIM_COLLISION_CHECK != "NONE") && (SIM_COLLISION_CHECK != "WARNING_ONLY") && (SIM_COLLISION_CHECK != "GENERATE_X_ONLY")) begin + + $display("Attribute Syntax Error : The attribute SIM_COLLISION_CHECK on RAMB16BWE instance %m is set to %s. Legal values for this attribute are ALL, NONE, WARNING_ONLY or GENERATE_X_ONLY.", SIM_COLLISION_CHECK); + finish_error = 1; + + end + + + if (finish_error == 1) + $finish; + + + end // initial begin + + + always @(gsr_in) + if (gsr_in) begin + + assign doado_out = INIT_A[0 +: a_width]; + + if (a_width >= 8) begin + assign dopadop_out = INIT_A[a_width +: a_widthp]; + end + + assign dobdo_out = INIT_B[0 +: b_width]; + + if (b_width >= 8) begin + assign dopbdop_out = INIT_B[b_width +: b_widthp]; + end + + end + else begin + deassign doado_out; + deassign dopadop_out; + deassign dobdo_out; + deassign dopbdop_out; + end + + + always @(posedge clkawrclk_in) begin + + rising_clkawrclk = 1; + + if (enawren_in === 1'b1) begin + prev_time = curr_time; + curr_time = $time; + addrawraddr_reg = addrawraddr_in; + weawel_reg = weawel_int; + diadi_reg = diadi_int; + dipadip_reg = dipadip_int; + end + + end + + always @(posedge clkbrdclk_in) begin + + rising_clkbrdclk = 1; + + if (enbrden_in === 1'b1) begin + prev_time = curr_time; + curr_time = $time; + addrbrdaddr_reg = addrbrdaddr_in; + webweu_reg = webweu_int; + enbrden_reg = enbrden_in; + dibdi_reg = dibdi_int; + dipbdip_reg = dipbdip_int; + end + + end // always @ (posedge clkbrdclk_in) + + + always @(posedge rising_clkawrclk or posedge rising_clkbrdclk) begin + + +/************************************* Collision starts *****************************************/ + + if (SIM_COLLISION_CHECK != "NONE") begin + + if (gsr_in === 1'b0) begin + if (curr_time - prev_time == 0) begin + viol_time = 1; + end + else if (curr_time - prev_time <= SETUP_READ_FIRST) begin + viol_time = 2; + end + + + if (enawren_in === 1'b0 || enbrden_in === 1'b0) + viol_time = 0; + + + if ((DATA_WIDTH_A <= 9 && weawel_int[0] === 1'b0) || (DATA_WIDTH_A == 18 && weawel_int[1:0] === 2'b00) || (DATA_WIDTH_A == 36 && weawel_int[3:0] === 4'b0000)) + if ((DATA_WIDTH_B <= 9 && webweu_int[0] === 1'b0) || (DATA_WIDTH_B == 18 && webweu_int[1:0] === 2'b00) || (DATA_WIDTH_B == 36 && webweu_int[3:0] === 4'b0000)) + viol_time = 0; + + + if (viol_time != 0) begin + + if (rising_clkawrclk && rising_clkbrdclk) begin + if (addrawraddr_in[13:col_addr_lsb] === addrbrdaddr_in[13:col_addr_lsb]) begin + + viol_type = 2'b01; + + task_rd_ram_a (addrawraddr_in, doado_buf, dopadop_buf); + task_rd_ram_b (addrbrdaddr_in, dobdo_buf, dopbdop_buf); + + task_col_wr_ram_a (2'b00, webweu_int, weawel_int, di_x, di_x[7:0], addrbrdaddr_in, addrawraddr_in); + task_col_wr_ram_b (2'b00, weawel_int, webweu_int, di_x, di_x[7:0], addrawraddr_in, addrbrdaddr_in); + + task_col_rd_ram_a (2'b01, webweu_int, weawel_int, addrawraddr_in, doado_buf, dopadop_buf); + task_col_rd_ram_b (2'b01, weawel_int, webweu_int, addrbrdaddr_in, dobdo_buf, dopbdop_buf); + + task_col_wr_ram_a (2'b10, webweu_int, weawel_int, diadi_int, dipadip_int, addrbrdaddr_in, addrawraddr_in); + task_col_wr_ram_b (2'b10, weawel_int, webweu_int, dibdi_int, dipbdip_int, addrawraddr_in, addrbrdaddr_in); + + if (wr_mode_a != 2'b01) + task_col_rd_ram_a (2'b11, webweu_int, weawel_int, addrawraddr_in, doado_buf, dopadop_buf); + if (wr_mode_b != 2'b01) + task_col_rd_ram_b (2'b11, weawel_int, webweu_int, addrbrdaddr_in, dobdo_buf, dopbdop_buf); + + end // if (addrawraddr_in[13:col_addr_lsb] === addrbrdaddr_in[13:col_addr_lsb]) + else + viol_time = 0; + + end + else if (rising_clkawrclk && !rising_clkbrdclk) begin + if (addrawraddr_in[13:col_addr_lsb] === addrbrdaddr_reg[13:col_addr_lsb]) begin + + viol_type = 2'b10; + + task_rd_ram_a (addrawraddr_in, doado_buf, dopadop_buf); + + task_col_wr_ram_a (2'b00, webweu_reg, weawel_int, di_x, di_x[7:0], addrbrdaddr_reg, addrawraddr_in); + task_col_wr_ram_b (2'b00, weawel_int, webweu_reg, di_x, di_x[7:0], addrawraddr_in, addrbrdaddr_reg); + + task_col_rd_ram_a (2'b01, webweu_reg, weawel_int, addrawraddr_in, doado_buf, dopadop_buf); + task_col_rd_ram_b (2'b01, weawel_int, webweu_reg, addrbrdaddr_reg, dobdo_buf, dopbdop_buf); + + task_col_wr_ram_a (2'b10, webweu_reg, weawel_int, diadi_int, dipadip_int, addrbrdaddr_reg, addrawraddr_in); + task_col_wr_ram_b (2'b10, weawel_int, webweu_reg, dibdi_reg, dipbdip_reg, addrawraddr_in, addrbrdaddr_reg); + + if (wr_mode_a != 2'b01) + task_col_rd_ram_a (2'b11, webweu_reg, weawel_int, addrawraddr_in, doado_buf, dopadop_buf); + if (wr_mode_b != 2'b01) + task_col_rd_ram_b (2'b11, weawel_int, webweu_reg, addrbrdaddr_reg, dobdo_buf, dopbdop_buf); + + end // if (addrawraddr_in[13:col_addr_lsb] === addrbrdaddr_reg[13:col_addr_lsb]) + else + viol_time = 0; + + end + else if (!rising_clkawrclk && rising_clkbrdclk) begin + if (addrawraddr_reg[13:col_addr_lsb] === addrbrdaddr_in[13:col_addr_lsb]) begin + + viol_type = 2'b11; + + task_rd_ram_b (addrbrdaddr_in, dobdo_buf, dopbdop_buf); + + task_col_wr_ram_a (2'b00, webweu_int, weawel_reg, di_x, di_x[7:0], addrbrdaddr_in, addrawraddr_reg); + task_col_wr_ram_b (2'b00, weawel_reg, webweu_int, di_x, di_x[7:0], addrawraddr_reg, addrbrdaddr_in); + + task_col_rd_ram_a (2'b01, webweu_int, weawel_reg, addrawraddr_reg, doado_buf, dopadop_buf); + task_col_rd_ram_b (2'b01, weawel_reg, webweu_int, addrbrdaddr_in, dobdo_buf, dopbdop_buf); + + task_col_wr_ram_a (2'b10, webweu_int, weawel_reg, diadi_reg, dipadip_reg, addrbrdaddr_in, addrawraddr_reg); + task_col_wr_ram_b (2'b10, weawel_reg, webweu_int, dibdi_int, dipbdip_int, addrawraddr_reg, addrbrdaddr_in); + + if (wr_mode_a != 2'b01) + task_col_rd_ram_a (2'b11, webweu_int, weawel_reg, addrawraddr_reg, doado_buf, dopadop_buf); + if (wr_mode_b != 2'b01) + task_col_rd_ram_b (2'b11, weawel_reg, webweu_int, addrbrdaddr_in, dobdo_buf, dopbdop_buf); + + end // if (addrawraddr_reg[13:col_addr_lsb] === addrbrdaddr_in[13:col_addr_lsb]) + else + viol_time = 0; + + end + + end // if (viol_time != 0) + end // if (gsr_in === 1'b0) + + if (SIM_COLLISION_CHECK == "WARNING_ONLY") + viol_time = 0; + + end // if (SIM_COLLISION_CHECK != "NONE") + + +/*************************************** end collision ********************************/ + + + if (gsr_in == 1'b0) begin + +/**************************** Port A ****************************************/ + if (rising_clkawrclk) begin + + if (enawren_in == 1'b1) begin + + if (rsta_in == 1'b1) begin // sync reset + doado_buf = SRVAL_A[0 +: a_width]; + doado_out = SRVAL_A[0 +: a_width]; + + if (a_width >= 8) begin + dopadop_buf = SRVAL_A[a_width +: a_widthp]; + dopadop_out = SRVAL_A[a_width +: a_widthp]; + end + end + + + if (viol_time == 0) begin + + if (wr_mode_a == 2'b01 && rsta_in === 1'b0) // read_first + task_rd_ram_a (addrawraddr_in, doado_buf, dopadop_buf); + + + if (enawren_in == 1'b1) + task_wr_ram_a (weawel_int, diadi_int, dipadip_int, addrawraddr_in); // write + + + if (wr_mode_a != 2'b01 && rsta_in === 1'b0) // !read_first + task_rd_ram_a (addrawraddr_in, doado_buf, dopadop_buf); + + end // if (viol_time == 0) + + end // if (enawren_in == 1'b1) + + end // if (rising_clkawrclk) + // end of port A + + +/************************************** port B ***************************************************************/ + if (rising_clkbrdclk) begin + + if (enbrden_in == 1'b1) begin + if (rstbrst_in == 1'b1) begin + + dobdo_buf = SRVAL_B[0 +: b_width]; + dobdo_out = SRVAL_B[0 +: b_width]; + + if (b_width >= 8) begin + dopbdop_buf = SRVAL_B[b_width +: b_widthp]; + dopbdop_out = SRVAL_B[b_width +: b_widthp]; + end + + end + + + if (viol_time == 0) begin + + if (wr_mode_b == 2'b01 && rstbrst_in === 1'b0) // read_first + task_rd_ram_b (addrbrdaddr_in, dobdo_buf, dopbdop_buf); + + + if (enbrden_in == 1'b1) + task_wr_ram_b (webweu_int, dibdi_int, dipbdip_int, addrbrdaddr_in); // write + + + if (wr_mode_b != 2'b01 && rstbrst_in === 1'b0) // !read_first + task_rd_ram_b (addrbrdaddr_in, dobdo_buf, dopbdop_buf); + + end // if (viol_time == 0) + + end // if (enbrden_in == 1'b1) + + end // if (rising_clkbrdclk) + // end of port B + + + // writing outputs of port A + if (enawren_in && (rising_clkawrclk || viol_time != 0)) begin + + if (rsta_in === 1'b0 && (wr_mode_a != 2'b10 || (DATA_WIDTH_A <= 9 && weawel_int[0] === 1'b0) || (DATA_WIDTH_A == 18 && weawel_int[1:0] === 2'b00) || (DATA_WIDTH_A == 36 && weawel_int[3:0] === 4'b0000))) begin + + doado_out <= doado_buf; + + if (a_width >= 8) + dopadop_out <= dopadop_buf; + + end + + end + + + // writing outputs of port B + if (enbrden_in && (rising_clkbrdclk || viol_time != 0)) begin + + if (rstbrst_in === 1'b0 && (wr_mode_b != 2'b10 || (DATA_WIDTH_B <= 9 && webweu_int[0] === 1'b0) || (DATA_WIDTH_B == 18 && webweu_int[1:0] === 2'b00) || (DATA_WIDTH_B == 36 && webweu_int[3:0] === 4'b0000))) begin + + dobdo_out <= dobdo_buf; + + if (b_width >= 8) + dopbdop_out <= dopbdop_buf; + + end + + end + + end // if (gsr_in == 1'b0) + + + viol_time = 0; + rising_clkawrclk = 0; + rising_clkbrdclk = 0; + viol_type = 2'b00; + col_wr_wr_msg = 1; + col_wra_rdb_msg = 1; + col_wrb_rda_msg = 1; + + + end // always @ (posedge rising_clkawrclk or posedge rising_clkbrdclk) + + + +/******************************************** task and function **************************************/ + + task task_ram; + + input we; + input [7:0] di; + input dip; + inout [7:0] mem_task; + inout memp_task; + + begin + + if (we == 1'b1) begin + + mem_task = di; + + if (width >= 8) + memp_task = dip; + end + end + + endtask // task_ram + + + task task_ram_col; + + input we_o; + input we; + input [7:0] di; + input dip; + inout [7:0] mem_task; + inout memp_task; + integer i; + + begin + + if (we == 1'b1) begin + + for (i = 0; i < 8; i = i + 1) + if (mem_task[i] !== 1'bx || !(we === we_o && we === 1'b1)) + mem_task[i] = di[i]; + + if (width >= 8 && (memp_task !== 1'bx || !(we === we_o && we === 1'b1))) + memp_task = dip; + + end + end + + endtask // task_ram_col + + + task task_x_buf; + input [1:0] wr_rd_mode; + input integer do_uindex; + input integer do_lindex; + input integer dop_index; + input [63:0] do_ltmp; + inout [63:0] do_tmp; + input [7:0] dop_ltmp; + inout [7:0] dop_tmp; + integer i; + + begin + + if (wr_rd_mode == 2'b01) begin + for (i = do_lindex; i <= do_uindex; i = i + 1) begin + if (do_ltmp[i] === 1'bx) + do_tmp[i] = 1'bx; + end + + if (dop_ltmp[dop_index] === 1'bx) + dop_tmp[dop_index] = 1'bx; + + end // if (wr_rd_mode == 2'b01) + else begin + do_tmp[do_lindex +: 8] = do_ltmp[do_lindex +: 8]; + dop_tmp[dop_index] = dop_ltmp[dop_index]; + + end // else: !if(wr_rd_mode == 2'b01) + end + + endtask // task_x_buf + + + task task_col_wr_ram_a; + + input [1:0] seq; + input [7:0] webweu_tmp; + input [7:0] weawel_tmp; + input [63:0] diadi_tmp; + input [7:0] dipadip_tmp; + input [15:0] addrbrdaddr_tmp; + input [15:0] addrawraddr_tmp; + + begin + + case (a_width) + + 1, 2, 4 : begin + if (!(weawel_tmp[0] === 1'b1 && webweu_tmp[0] === 1'b1 && a_width > b_width) || seq == 2'b10) begin + if (a_width >= width) + task_ram_col (webweu_tmp[0], weawel_tmp[0], diadi_tmp[a_width-1:0], 1'b0, mem[addrawraddr_tmp[14:addrawraddr_lbit_124]], tmp1); + else + task_ram_col (webweu_tmp[0], weawel_tmp[0], diadi_tmp[a_width-1:0], 1'b0, mem[addrawraddr_tmp[14:addrawraddr_bit_124+1]][(addrawraddr_tmp[addrawraddr_bit_124:addrawraddr_lbit_124] * a_width) +: a_width], tmp1); + + if (seq == 2'b00) + chk_for_col_msg (weawel_tmp[0], webweu_tmp[0], addrawraddr_tmp, addrbrdaddr_tmp); + + end // if (!(weawel_tmp[0] === 1'b1 && webweu_tmp[0] === 1'b1 && a_width > b_width) || seq == 2'b10) + end // case: 1, 2, 4 + 8 : begin + if (!(weawel_tmp[0] === 1'b1 && webweu_tmp[0] === 1'b1 && a_width > b_width) || seq == 2'b10) begin + if (a_width >= width) + task_ram_col (webweu_tmp[0], weawel_tmp[0], diadi_tmp[7:0], dipadip_tmp[0], mem[addrawraddr_tmp[14:3]], memp[addrawraddr_tmp[14:3]]); + else + task_ram_col (webweu_tmp[0], weawel_tmp[0], diadi_tmp[7:0], dipadip_tmp[0], mem[addrawraddr_tmp[14:addrawraddr_bit_8+1]][(addrawraddr_tmp[addrawraddr_bit_8:3] * 8) +: 8], memp[addrawraddr_tmp[14:addrawraddr_bit_8+1]][(addrawraddr_tmp[addrawraddr_bit_8:3] * 1) +: 1]); + + if (seq == 2'b00) + chk_for_col_msg (weawel_tmp[0], webweu_tmp[0], addrawraddr_tmp, addrbrdaddr_tmp); + + end // if (a_width <= b_width) + end // case: 8 + 16 : begin + if (!(weawel_tmp[0] === 1'b1 && webweu_tmp[0] === 1'b1 && a_width > b_width) || seq == 2'b10) begin + if (a_width >= width) + task_ram_col (webweu_tmp[0], weawel_tmp[0], diadi_tmp[7:0], dipadip_tmp[0], mem[addrawraddr_tmp[14:4]][0 +: 8], memp[addrawraddr_tmp[14:4]][0]); + else + task_ram_col (webweu_tmp[0], weawel_tmp[0], diadi_tmp[7:0], dipadip_tmp[0], mem[addrawraddr_tmp[14:addrawraddr_bit_16+1]][(addrawraddr_tmp[addrawraddr_bit_16:4] * 16) +: 8], memp[addrawraddr_tmp[14:addrawraddr_bit_16+1]][(addrawraddr_tmp[addrawraddr_bit_16:4] * 2) +: 1]); + + if (seq == 2'b00) + chk_for_col_msg (weawel_tmp[0], webweu_tmp[0], addrawraddr_tmp, addrbrdaddr_tmp); + + if (a_width >= width) + task_ram_col (webweu_tmp[1], weawel_tmp[1], diadi_tmp[15:8], dipadip_tmp[1], mem[addrawraddr_tmp[14:4]][8 +: 8], memp[addrawraddr_tmp[14:4]][1]); + else + task_ram_col (webweu_tmp[1], weawel_tmp[1], diadi_tmp[15:8], dipadip_tmp[1], mem[addrawraddr_tmp[14:addrawraddr_bit_16+1]][((addrawraddr_tmp[addrawraddr_bit_16:4] * 16) + 8) +: 8], memp[addrawraddr_tmp[14:addrawraddr_bit_16+1]][((addrawraddr_tmp[addrawraddr_bit_16:4] * 2) + 1) +: 1]); + + if (seq == 2'b00) + chk_for_col_msg (weawel_tmp[1], webweu_tmp[1], addrawraddr_tmp, addrbrdaddr_tmp); + + end // if (a_width <= b_width) + end // case: 16 + 32 : begin + if (!(weawel_tmp[0] === 1'b1 && webweu_tmp[0] === 1'b1 && a_width > b_width) || seq == 2'b10) begin + task_ram_col (webweu_tmp[0], weawel_tmp[0], diadi_tmp[7:0], dipadip_tmp[0], mem[addrawraddr_tmp[14:5]][0 +: 8], memp[addrawraddr_tmp[14:5]][0]); + if (seq == 2'b00) + chk_for_col_msg (weawel_tmp[0], webweu_tmp[0], addrawraddr_tmp, addrbrdaddr_tmp); + + task_ram_col (webweu_tmp[1], weawel_tmp[1], diadi_tmp[15:8], dipadip_tmp[1], mem[addrawraddr_tmp[14:5]][8 +: 8], memp[addrawraddr_tmp[14:5]][1]); + if (seq == 2'b00) + chk_for_col_msg (weawel_tmp[1], webweu_tmp[1], addrawraddr_tmp, addrbrdaddr_tmp); + + task_ram_col (webweu_tmp[2], weawel_tmp[2], diadi_tmp[23:16], dipadip_tmp[2], mem[addrawraddr_tmp[14:5]][16 +: 8], memp[addrawraddr_tmp[14:5]][2]); + if (seq == 2'b00) + chk_for_col_msg (weawel_tmp[2], webweu_tmp[2], addrawraddr_tmp, addrbrdaddr_tmp); + + task_ram_col (webweu_tmp[3], weawel_tmp[3], diadi_tmp[31:24], dipadip_tmp[3], mem[addrawraddr_tmp[14:5]][24 +: 8], memp[addrawraddr_tmp[14:5]][3]); + if (seq == 2'b00) + chk_for_col_msg (weawel_tmp[3], webweu_tmp[3], addrawraddr_tmp, addrbrdaddr_tmp); + + end // if (a_width <= b_width) + end // case: 32 + + endcase // case(a_width) + + end + + endtask // task_col_wr_ram_a + + + task task_col_wr_ram_b; + + input [1:0] seq; + input [7:0] weawel_tmp; + input [7:0] webweu_tmp; + input [63:0] dibdi_tmp; + input [7:0] dipbdip_tmp; + input [15:0] addrawraddr_tmp; + input [15:0] addrbrdaddr_tmp; + + begin + + case (b_width) + + 1, 2, 4 : begin + if (!(weawel_tmp[0] === 1'b1 && webweu_tmp[0] === 1'b1 && b_width > a_width) || seq == 2'b10) begin + if (b_width >= width) + task_ram_col (weawel_tmp[0], webweu_tmp[0], dibdi_tmp[b_width-1:0], 1'b0, mem[addrbrdaddr_tmp[14:addrbrdaddr_lbit_124]], tmp1); + else + task_ram_col (weawel_tmp[0], webweu_tmp[0], dibdi_tmp[b_width-1:0], 1'b0, mem[addrbrdaddr_tmp[14:addrbrdaddr_bit_124+1]][(addrbrdaddr_tmp[addrbrdaddr_bit_124:addrbrdaddr_lbit_124] * b_width) +: b_width], tmp1); + + if (seq == 2'b00) + chk_for_col_msg (weawel_tmp[0], webweu_tmp[0], addrawraddr_tmp, addrbrdaddr_tmp); + + end // if (b_width <= a_width) + end // case: 1, 2, 4 + 8 : begin + if (!(weawel_tmp[0] === 1'b1 && webweu_tmp[0] === 1'b1 && b_width > a_width) || seq == 2'b10) begin + if (b_width >= width) + task_ram_col (weawel_tmp[0], webweu_tmp[0], dibdi_tmp[7:0], dipbdip_tmp[0], mem[addrbrdaddr_tmp[14:3]], memp[addrbrdaddr_tmp[14:3]]); + else + task_ram_col (weawel_tmp[0], webweu_tmp[0], dibdi_tmp[7:0], dipbdip_tmp[0], mem[addrbrdaddr_tmp[14:addrbrdaddr_bit_8+1]][(addrbrdaddr_tmp[addrbrdaddr_bit_8:3] * 8) +: 8], memp[addrbrdaddr_tmp[14:addrbrdaddr_bit_8+1]][(addrbrdaddr_tmp[addrbrdaddr_bit_8:3] * 1) +: 1]); + + if (seq == 2'b00) + chk_for_col_msg (weawel_tmp[0], webweu_tmp[0], addrawraddr_tmp, addrbrdaddr_tmp); + + end // if (b_width <= a_width) + end // case: 8 + 16 : begin + if (!(weawel_tmp[0] === 1'b1 && webweu_tmp[0] === 1'b1 && b_width > a_width) || seq == 2'b10) begin + if (b_width >= width) + task_ram_col (weawel_tmp[0], webweu_tmp[0], dibdi_tmp[7:0], dipbdip_tmp[0], mem[addrbrdaddr_tmp[14:4]][0 +: 8], memp[addrbrdaddr_tmp[14:4]][0:0]); + else + task_ram_col (weawel_tmp[0], webweu_tmp[0], dibdi_tmp[7:0], dipbdip_tmp[0], mem[addrbrdaddr_tmp[14:addrbrdaddr_bit_16+1]][(addrbrdaddr_tmp[addrbrdaddr_bit_16:4] * 16) +: 8], memp[addrbrdaddr_tmp[14:addrbrdaddr_bit_16+1]][(addrbrdaddr_tmp[addrbrdaddr_bit_16:4] * 2) +: 1]); + + if (seq == 2'b00) + chk_for_col_msg (weawel_tmp[0], webweu_tmp[0], addrawraddr_tmp, addrbrdaddr_tmp); + + + if (b_width >= width) + task_ram_col (weawel_tmp[1], webweu_tmp[1], dibdi_tmp[15:8], dipbdip_tmp[1], mem[addrbrdaddr_tmp[14:4]][8 +: 8], memp[addrbrdaddr_tmp[14:4]][1:1]); + else + task_ram_col (weawel_tmp[1], webweu_tmp[1], dibdi_tmp[15:8], dipbdip_tmp[1], mem[addrbrdaddr_tmp[14:addrbrdaddr_bit_16+1]][((addrbrdaddr_tmp[addrbrdaddr_bit_16:4] * 16) + 8) +: 8], memp[addrbrdaddr_tmp[14:addrbrdaddr_bit_16+1]][((addrbrdaddr_tmp[addrbrdaddr_bit_16:4] * 2) + 1) +: 1]); + + if (seq == 2'b00) + chk_for_col_msg (weawel_tmp[1], webweu_tmp[1], addrawraddr_tmp, addrbrdaddr_tmp); + + end // if (!(weawel_tmp[0] === 1'b1 && webweu_tmp[0] === 1'b1 && b_width > a_width) || seq == 2'b10) + end // case: 16 + 32 : begin + if (!(weawel_tmp[0] === 1'b1 && webweu_tmp[0] === 1'b1 && b_width > a_width) || seq == 2'b10) begin + task_ram_col (weawel_tmp[0], webweu_tmp[0], dibdi_tmp[7:0], dipbdip_tmp[0], mem[addrbrdaddr_tmp[14:5]][0 +: 8], memp[addrbrdaddr_tmp[14:5]][0:0]); + if (seq == 2'b00) + chk_for_col_msg (weawel_tmp[0], webweu_tmp[0], addrawraddr_tmp, addrbrdaddr_tmp); + + task_ram_col (weawel_tmp[1], webweu_tmp[1], dibdi_tmp[15:8], dipbdip_tmp[1], mem[addrbrdaddr_tmp[14:5]][8 +: 8], memp[addrbrdaddr_tmp[14:5]][1:1]); + if (seq == 2'b00) + chk_for_col_msg (weawel_tmp[1], webweu_tmp[1], addrawraddr_tmp, addrbrdaddr_tmp); + + task_ram_col (weawel_tmp[2], webweu_tmp[2], dibdi_tmp[23:16], dipbdip_tmp[2], mem[addrbrdaddr_tmp[14:5]][16 +: 8], memp[addrbrdaddr_tmp[14:5]][2:2]); + if (seq == 2'b00) + chk_for_col_msg (weawel_tmp[2], webweu_tmp[2], addrawraddr_tmp, addrbrdaddr_tmp); + + task_ram_col (weawel_tmp[3], webweu_tmp[3], dibdi_tmp[31:24], dipbdip_tmp[3], mem[addrbrdaddr_tmp[14:5]][24 +: 8], memp[addrbrdaddr_tmp[14:5]][3:3]); + if (seq == 2'b00) + chk_for_col_msg (weawel_tmp[3], webweu_tmp[3], addrawraddr_tmp, addrbrdaddr_tmp); + + end // if (b_width <= a_width) + end // case: 32 + + endcase // case(b_width) + + end + + endtask // task_col_wr_ram_b + + + task task_wr_ram_a; + + input [7:0] weawel_tmp; + input [63:0] diadi_tmp; + input [7:0] dipadip_tmp; + input [15:0] addrawraddr_tmp; + + begin + + case (a_width) + + 1, 2, 4 : begin + + if (a_width >= width) + task_ram (weawel_tmp[0], diadi_tmp[a_width-1:0], 1'b0, mem[addrawraddr_tmp[14:addrawraddr_lbit_124]], tmp1); + else + task_ram (weawel_tmp[0], diadi_tmp[a_width-1:0], 1'b0, mem[addrawraddr_tmp[14:addrawraddr_bit_124+1]][(addrawraddr_tmp[addrawraddr_bit_124:addrawraddr_lbit_124] * a_width) +: a_width], tmp1); + + end + 8 : begin + + if (a_width >= width) + task_ram (weawel_tmp[0], diadi_tmp[7:0], dipadip_tmp[0], mem[addrawraddr_tmp[14:3]], memp[addrawraddr_tmp[14:3]]); + else + task_ram (weawel_tmp[0], diadi_tmp[7:0], dipadip_tmp[0], mem[addrawraddr_tmp[14:addrawraddr_bit_8+1]][(addrawraddr_tmp[addrawraddr_bit_8:3] * 8) +: 8], memp[addrawraddr_tmp[14:addrawraddr_bit_8+1]][(addrawraddr_tmp[addrawraddr_bit_8:3] * 1) +: 1]); + + end + 16 : begin + + if (a_width >= width) begin + task_ram (weawel_tmp[0], diadi_tmp[7:0], dipadip_tmp[0], mem[addrawraddr_tmp[14:4]][0 +: 8], memp[addrawraddr_tmp[14:4]][0:0]); + task_ram (weawel_tmp[1], diadi_tmp[15:8], dipadip_tmp[1], mem[addrawraddr_tmp[14:4]][8 +: 8], memp[addrawraddr_tmp[14:4]][1:1]); + end + else begin + task_ram (weawel_tmp[0], diadi_tmp[7:0], dipadip_tmp[0], mem[addrawraddr_tmp[14:addrawraddr_bit_16+1]][(addrawraddr_tmp[addrawraddr_bit_16:4] * 16) +: 8], memp[addrawraddr_tmp[14:addrawraddr_bit_16+1]][(addrawraddr_tmp[addrawraddr_bit_16:4] * 2) +: 1]); + task_ram (weawel_tmp[1], diadi_tmp[15:8], dipadip_tmp[1], mem[addrawraddr_tmp[14:addrawraddr_bit_16+1]][((addrawraddr_tmp[addrawraddr_bit_16:4] * 16) + 8) +: 8], memp[addrawraddr_tmp[14:addrawraddr_bit_16+1]][((addrawraddr_tmp[addrawraddr_bit_16:4] * 2) + 1) +: 1]); + end // else: !if(a_width >= b_width) + + end // case: 16 + 32 : begin + + task_ram (weawel_tmp[0], diadi_tmp[7:0], dipadip_tmp[0], mem[addrawraddr_tmp[14:5]][0 +: 8], memp[addrawraddr_tmp[14:5]][0:0]); + task_ram (weawel_tmp[1], diadi_tmp[15:8], dipadip_tmp[1], mem[addrawraddr_tmp[14:5]][8 +: 8], memp[addrawraddr_tmp[14:5]][1:1]); + task_ram (weawel_tmp[2], diadi_tmp[23:16], dipadip_tmp[2], mem[addrawraddr_tmp[14:5]][16 +: 8], memp[addrawraddr_tmp[14:5]][2:2]); + task_ram (weawel_tmp[3], diadi_tmp[31:24], dipadip_tmp[3], mem[addrawraddr_tmp[14:5]][24 +: 8], memp[addrawraddr_tmp[14:5]][3:3]); + + end // case: 32 + endcase // case(a_width) + end + + endtask // task_wr_ram_a + + + task task_wr_ram_b; + + input [7:0] webweu_tmp; + input [63:0] dibdi_tmp; + input [7:0] dipbdip_tmp; + input [15:0] addrbrdaddr_tmp; + + begin + + case (b_width) + + 1, 2, 4 : begin + + if (b_width >= width) + task_ram (webweu_tmp[0], dibdi_tmp[b_width-1:0], 1'b0, mem[addrbrdaddr_tmp[14:addrbrdaddr_lbit_124]], tmp1); + else + task_ram (webweu_tmp[0], dibdi_tmp[b_width-1:0], 1'b0, mem[addrbrdaddr_tmp[14:addrbrdaddr_bit_124+1]][(addrbrdaddr_tmp[addrbrdaddr_bit_124:addrbrdaddr_lbit_124] * b_width) +: b_width], tmp1); + end + 8 : begin + + if (b_width >= width) + task_ram (webweu_tmp[0], dibdi_tmp[7:0], dipbdip_tmp[0], mem[addrbrdaddr_tmp[14:3]], memp[addrbrdaddr_tmp[14:3]]); + else + task_ram (webweu_tmp[0], dibdi_tmp[7:0], dipbdip_tmp[0], mem[addrbrdaddr_tmp[14:addrbrdaddr_bit_8+1]][(addrbrdaddr_tmp[addrbrdaddr_bit_8:3] * 8) +: 8], memp[addrbrdaddr_tmp[14:addrbrdaddr_bit_8+1]][(addrbrdaddr_tmp[addrbrdaddr_bit_8:3] * 1) +: 1]); + + end + 16 : begin + + if (b_width >= width) begin + task_ram (webweu_tmp[0], dibdi_tmp[7:0], dipbdip_tmp[0], mem[addrbrdaddr_tmp[14:4]][0 +: 8], memp[addrbrdaddr_tmp[14:4]][0:0]); + task_ram (webweu_tmp[1], dibdi_tmp[15:8], dipbdip_tmp[1], mem[addrbrdaddr_tmp[14:4]][8 +: 8], memp[addrbrdaddr_tmp[14:4]][1:1]); + end + else begin + task_ram (webweu_tmp[0], dibdi_tmp[7:0], dipbdip_tmp[0], mem[addrbrdaddr_tmp[14:addrbrdaddr_bit_16+1]][(addrbrdaddr_tmp[addrbrdaddr_bit_16:4] * 16) +: 8], memp[addrbrdaddr_tmp[14:addrbrdaddr_bit_16+1]][(addrbrdaddr_tmp[addrbrdaddr_bit_16:4] * 2) +: 1]); + task_ram (webweu_tmp[1], dibdi_tmp[15:8], dipbdip_tmp[1], mem[addrbrdaddr_tmp[14:addrbrdaddr_bit_16+1]][((addrbrdaddr_tmp[addrbrdaddr_bit_16:4] * 16) + 8) +: 8], memp[addrbrdaddr_tmp[14:addrbrdaddr_bit_16+1]][((addrbrdaddr_tmp[addrbrdaddr_bit_16:4] * 2) + 1) +: 1]); + end + + end // case: 16 + 32 : begin + + task_ram (webweu_tmp[0], dibdi_tmp[7:0], dipbdip_tmp[0], mem[addrbrdaddr_tmp[14:5]][0 +: 8], memp[addrbrdaddr_tmp[14:5]][0:0]); + task_ram (webweu_tmp[1], dibdi_tmp[15:8], dipbdip_tmp[1], mem[addrbrdaddr_tmp[14:5]][8 +: 8], memp[addrbrdaddr_tmp[14:5]][1:1]); + task_ram (webweu_tmp[2], dibdi_tmp[23:16], dipbdip_tmp[2], mem[addrbrdaddr_tmp[14:5]][16 +: 8], memp[addrbrdaddr_tmp[14:5]][2:2]); + task_ram (webweu_tmp[3], dibdi_tmp[31:24], dipbdip_tmp[3], mem[addrbrdaddr_tmp[14:5]][24 +: 8], memp[addrbrdaddr_tmp[14:5]][3:3]); + + end // case: 32 + endcase // case(b_width) + end + + endtask // task_wr_ram_b + + + task task_col_rd_ram_a; + + input [1:0] seq; // 1 is bypass + input [7:0] webweu_tmp; + input [7:0] weawel_tmp; + input [15:0] addrawraddr_tmp; + inout [63:0] doado_tmp; + inout [7:0] dopadop_tmp; + reg [63:0] doado_ltmp; + reg [7:0] dopadop_ltmp; + + begin + + doado_ltmp= 64'b0; + dopadop_ltmp= 8'b0; + + case (a_width) + 1, 2, 4 : begin + + if ((webweu_tmp[0] === 1'b1 && weawel_tmp[0] === 1'b1) || (seq == 2'b01 && webweu_tmp[0] === 1'b1 && weawel_tmp[0] === 1'b0 && viol_type == 2'b10) || (seq == 2'b01 && wr_mode_a != 2'b01 && wr_mode_b != 2'b01) || (seq == 2'b01 && wr_mode_a == 2'b01 && wr_mode_b != 2'b01 && webweu_tmp[0] === 1'b1) || (seq == 2'b11 && wr_mode_a == 2'b00 && webweu_tmp[0] !== 1'b1)) begin + if (a_width >= width) + doado_ltmp = mem[addrawraddr_tmp[14:addrawraddr_lbit_124]]; + else + doado_ltmp = mem[addrawraddr_tmp[14:addrawraddr_bit_124+1]][(addrawraddr_tmp[addrawraddr_bit_124:addrawraddr_lbit_124] * a_width) +: a_width]; + task_x_buf (wr_mode_a, 3, 0, 0, doado_ltmp, doado_tmp, dopadop_ltmp, dopadop_tmp); + end + end // case: 1, 2, 4 + 8 : begin + + if ((webweu_tmp[0] === 1'b1 && weawel_tmp[0] === 1'b1) || (seq == 2'b01 && webweu_tmp[0] === 1'b1 && weawel_tmp[0] === 1'b0 && viol_type == 2'b10) || (seq == 2'b01 && wr_mode_a != 2'b01 && wr_mode_b != 2'b01) || (seq == 2'b01 && wr_mode_a == 2'b01 && wr_mode_b != 2'b01 && webweu_tmp[0] === 1'b1) || (seq == 2'b11 && wr_mode_a == 2'b00 && webweu_tmp[0] !== 1'b1)) begin + if (a_width >= width) begin + doado_ltmp = mem[addrawraddr_tmp[14:3]]; + dopadop_ltmp = memp[addrawraddr_tmp[14:3]]; + end + else begin + doado_ltmp = mem[addrawraddr_tmp[14:addrawraddr_bit_8+1]][(addrawraddr_tmp[addrawraddr_bit_8:3] * 8) +: 8]; + dopadop_ltmp = memp[addrawraddr_tmp[14:addrawraddr_bit_8+1]][(addrawraddr_tmp[addrawraddr_bit_8:3] * 1) +: 1]; + end + + task_x_buf (wr_mode_a, 7, 0, 0, doado_ltmp, doado_tmp, dopadop_ltmp, dopadop_tmp); + + end + end // case: 8 + 16 : begin + + if ((webweu_tmp[0] === 1'b1 && weawel_tmp[0] === 1'b1) || (seq == 2'b01 && webweu_tmp[0] === 1'b1 && weawel_tmp[0] === 1'b0 && viol_type == 2'b10) || (seq == 2'b01 && wr_mode_a != 2'b01 && wr_mode_b != 2'b01) || (seq == 2'b01 && wr_mode_a == 2'b01 && wr_mode_b != 2'b01 && webweu_tmp[0] === 1'b1) || (seq == 2'b11 && wr_mode_a == 2'b00 && webweu_tmp[0] !== 1'b1)) begin + if (a_width >= width) begin + doado_ltmp[7:0] = mem[addrawraddr_tmp[14:4]][7:0]; + dopadop_ltmp[0:0] = memp[addrawraddr_tmp[14:4]][0:0]; + end + else begin + doado_ltmp[7:0] = mem[addrawraddr_tmp[14:addrawraddr_bit_16+1]][(addrawraddr_tmp[addrawraddr_bit_16:4] * 16) +: 8]; + dopadop_ltmp[0:0] = memp[addrawraddr_tmp[14:addrawraddr_bit_16+1]][(addrawraddr_tmp[addrawraddr_bit_16:4] * 2) +: 1]; + end + task_x_buf (wr_mode_a, 7, 0, 0, doado_ltmp, doado_tmp, dopadop_ltmp, dopadop_tmp); + end + + if ((webweu_tmp[1] === 1'b1 && weawel_tmp[1] === 1'b1) || (seq == 2'b01 && webweu_tmp[1] === 1'b1 && weawel_tmp[1] === 1'b0 && viol_type == 2'b10) || (seq == 2'b01 && wr_mode_a != 2'b01 && wr_mode_b != 2'b01) || (seq == 2'b01 && wr_mode_a == 2'b01 && wr_mode_b != 2'b01 && webweu_tmp[1] === 1'b1) || (seq == 2'b11 && wr_mode_a == 2'b00 && webweu_tmp[1] !== 1'b1)) begin + if (a_width >= width) begin + doado_ltmp[15:8] = mem[addrawraddr_tmp[14:4]][15:8]; + dopadop_ltmp[1:1] = memp[addrawraddr_tmp[14:4]][1:1]; + end + else begin + doado_ltmp[15:8] = mem[addrawraddr_tmp[14:addrawraddr_bit_16+1]][((addrawraddr_tmp[addrawraddr_bit_16:4] * 16) + 8) +: 8]; + dopadop_ltmp[1:1] = memp[addrawraddr_tmp[14:addrawraddr_bit_16+1]][((addrawraddr_tmp[addrawraddr_bit_16:4] * 2) + 1) +: 1]; + end + task_x_buf (wr_mode_a, 15, 8, 1, doado_ltmp, doado_tmp, dopadop_ltmp, dopadop_tmp); + end + + end + 32 : begin + if (a_width >= width) begin + + if ((webweu_tmp[0] === 1'b1 && weawel_tmp[0] === 1'b1) || (seq == 2'b01 && webweu_tmp[0] === 1'b1 && weawel_tmp[0] === 1'b0 && viol_type == 2'b10) || (seq == 2'b01 && wr_mode_a != 2'b01 && wr_mode_b != 2'b01) || (seq == 2'b01 && wr_mode_a == 2'b01 && wr_mode_b != 2'b01 && webweu_tmp[0] === 1'b1) || (seq == 2'b11 && wr_mode_a == 2'b00 && webweu_tmp[0] !== 1'b1)) begin + doado_ltmp[7:0] = mem[addrawraddr_tmp[14:5]][7:0]; + dopadop_ltmp[0:0] = memp[addrawraddr_tmp[14:5]][0:0]; + task_x_buf (wr_mode_a, 7, 0, 0, doado_ltmp, doado_tmp, dopadop_ltmp, dopadop_tmp); + end + + if ((webweu_tmp[1] === 1'b1 && weawel_tmp[1] === 1'b1) || (seq == 2'b01 && webweu_tmp[1] === 1'b1 && weawel_tmp[1] === 1'b0 && viol_type == 2'b10) || (seq == 2'b01 && wr_mode_a != 2'b01 && wr_mode_b != 2'b01) || (seq == 2'b01 && wr_mode_a == 2'b01 && wr_mode_b != 2'b01 && webweu_tmp[1] === 1'b1) || (seq == 2'b11 && wr_mode_a == 2'b00 && webweu_tmp[1] !== 1'b1)) begin + doado_ltmp[15:8] = mem[addrawraddr_tmp[14:5]][15:8]; + dopadop_ltmp[1:1] = memp[addrawraddr_tmp[14:5]][1:1]; + task_x_buf (wr_mode_a, 15, 8, 1, doado_ltmp, doado_tmp, dopadop_ltmp, dopadop_tmp); + end + + if ((webweu_tmp[2] === 1'b1 && weawel_tmp[2] === 1'b1) || (seq == 2'b01 && webweu_tmp[2] === 1'b1 && weawel_tmp[2] === 1'b0 && viol_type == 2'b10) || (seq == 2'b01 && wr_mode_a != 2'b01 && wr_mode_b != 2'b01) || (seq == 2'b01 && wr_mode_a == 2'b01 && wr_mode_b != 2'b01 && webweu_tmp[2] === 1'b1) || (seq == 2'b11 && wr_mode_a == 2'b00 && webweu_tmp[2] !== 1'b1)) begin + doado_ltmp[23:16] = mem[addrawraddr_tmp[14:5]][23:16]; + dopadop_ltmp[2:2] = memp[addrawraddr_tmp[14:5]][2:2]; + task_x_buf (wr_mode_a, 23, 16, 2, doado_ltmp, doado_tmp, dopadop_ltmp, dopadop_tmp); + end + + if ((webweu_tmp[3] === 1'b1 && weawel_tmp[3] === 1'b1) || (seq == 2'b01 && webweu_tmp[3] === 1'b1 && weawel_tmp[3] === 1'b0 && viol_type == 2'b10) || (seq == 2'b01 && wr_mode_a != 2'b01 && wr_mode_b != 2'b01) || (seq == 2'b01 && wr_mode_a == 2'b01 && wr_mode_b != 2'b01 && webweu_tmp[3] === 1'b1) || (seq == 2'b11 && wr_mode_a == 2'b00 && webweu_tmp[3] !== 1'b1)) begin + doado_ltmp[31:24] = mem[addrawraddr_tmp[14:5]][31:24]; + dopadop_ltmp[3:3] = memp[addrawraddr_tmp[14:5]][3:3]; + task_x_buf (wr_mode_a, 31, 24, 3, doado_ltmp, doado_tmp, dopadop_ltmp, dopadop_tmp); + end + + end // if (a_width >= width) + end + + endcase // case(a_width) + end + endtask // task_col_rd_ram_a + + + task task_col_rd_ram_b; + + input [1:0] seq; // 1 is bypass + input [7:0] weawel_tmp; + input [7:0] webweu_tmp; + input [15:0] addrbrdaddr_tmp; + inout [63:0] dobdo_tmp; + inout [7:0] dopbdop_tmp; + reg [63:0] dobdo_ltmp; + reg [7:0] dopbdop_ltmp; + + begin + + dobdo_ltmp= 64'b0; + dopbdop_ltmp= 8'b0; + + case (b_width) + 1, 2, 4 : begin + + if ((webweu_tmp[0] === 1'b1 && weawel_tmp[0] === 1'b1) || (seq == 2'b01 && weawel_tmp[0] === 1'b1 && webweu_tmp[0] === 1'b0 && viol_type == 2'b11) || (seq == 2'b01 && wr_mode_b != 2'b01 && wr_mode_a != 2'b01) || (seq == 2'b01 && wr_mode_b == 2'b01 && wr_mode_a != 2'b01 && weawel_tmp[0] === 1'b1) || (seq == 2'b11 && wr_mode_b == 2'b00 && weawel_tmp[0] !== 1'b1)) begin + if (b_width >= width) + dobdo_ltmp = mem[addrbrdaddr_tmp[14:addrbrdaddr_lbit_124]]; + else + dobdo_ltmp = mem[addrbrdaddr_tmp[14:addrbrdaddr_bit_124+1]][(addrbrdaddr_tmp[addrbrdaddr_bit_124:addrbrdaddr_lbit_124] * b_width) +: b_width]; + + task_x_buf (wr_mode_b, 3, 0, 0, dobdo_ltmp, dobdo_tmp, dopbdop_ltmp, dopbdop_tmp); + + end + end // case: 1, 2, 4 + 8 : begin + + if ((webweu_tmp[0] === 1'b1 && weawel_tmp[0] === 1'b1) || (seq == 2'b01 && weawel_tmp[0] === 1'b1 && webweu_tmp[0] === 1'b0 && viol_type == 2'b11) || (seq == 2'b01 && wr_mode_b != 2'b01 && wr_mode_a != 2'b01) || (seq == 2'b01 && wr_mode_b == 2'b01 && wr_mode_a != 2'b01 && weawel_tmp[0] === 1'b1) || (seq == 2'b11 && wr_mode_b == 2'b00 && weawel_tmp[0] !== 1'b1)) begin + + if (b_width >= width) begin + dobdo_ltmp = mem[addrbrdaddr_tmp[14:3]]; + dopbdop_ltmp = memp[addrbrdaddr_tmp[14:3]]; + end + else begin + dobdo_ltmp = mem[addrbrdaddr_tmp[14:addrbrdaddr_bit_8+1]][(addrbrdaddr_tmp[addrbrdaddr_bit_8:3] * 8) +: 8]; + dopbdop_ltmp = memp[addrbrdaddr_tmp[14:addrbrdaddr_bit_8+1]][(addrbrdaddr_tmp[addrbrdaddr_bit_8:3] * 1) +: 1]; + end + + task_x_buf (wr_mode_b, 7, 0, 0, dobdo_ltmp, dobdo_tmp, dopbdop_ltmp, dopbdop_tmp); + + end + end // case: 8 + 16 : begin + + if ((webweu_tmp[0] === 1'b1 && weawel_tmp[0] === 1'b1) || (seq == 2'b01 && weawel_tmp[0] === 1'b1 && webweu_tmp[0] === 1'b0 && viol_type == 2'b11) || (seq == 2'b01 && wr_mode_b != 2'b01 && wr_mode_a != 2'b01) || (seq == 2'b01 && wr_mode_b == 2'b01 && wr_mode_a != 2'b01 && weawel_tmp[0] === 1'b1) || (seq == 2'b11 && wr_mode_b == 2'b00 && weawel_tmp[0] !== 1'b1)) begin + if (b_width >= width) begin + dobdo_ltmp[7:0] = mem[addrbrdaddr_tmp[14:4]][7:0]; + dopbdop_ltmp[0:0] = memp[addrbrdaddr_tmp[14:4]][0:0]; + end + else begin + dobdo_ltmp[7:0] = mem[addrbrdaddr_tmp[14:addrbrdaddr_bit_16+1]][(addrbrdaddr_tmp[addrbrdaddr_bit_16:4] * 16) +: 8]; + dopbdop_ltmp[0:0] = memp[addrbrdaddr_tmp[14:addrbrdaddr_bit_16+1]][(addrbrdaddr_tmp[addrbrdaddr_bit_16:4] * 2) +: 1]; + end + task_x_buf (wr_mode_b, 7, 0, 0, dobdo_ltmp, dobdo_tmp, dopbdop_ltmp, dopbdop_tmp); + end + + + if ((webweu_tmp[1] === 1'b1 && weawel_tmp[1] === 1'b1) || (seq == 2'b01 && weawel_tmp[1] === 1'b1 && webweu_tmp[1] === 1'b0 && viol_type == 2'b11) || (seq == 2'b01 && wr_mode_b != 2'b01 && wr_mode_a != 2'b01) || (seq == 2'b01 && wr_mode_b == 2'b01 && wr_mode_a != 2'b01 && weawel_tmp[1] === 1'b1) || (seq == 2'b11 && wr_mode_b == 2'b00 && weawel_tmp[1] !== 1'b1)) begin + + if (b_width >= width) begin + dobdo_ltmp[15:8] = mem[addrbrdaddr_tmp[14:4]][15:8]; + dopbdop_ltmp[1:1] = memp[addrbrdaddr_tmp[14:4]][1:1]; + end + else begin + dobdo_ltmp[15:8] = mem[addrbrdaddr_tmp[14:addrbrdaddr_bit_16+1]][((addrbrdaddr_tmp[addrbrdaddr_bit_16:4] * 16) + 8) +: 8]; + dopbdop_ltmp[1:1] = memp[addrbrdaddr_tmp[14:addrbrdaddr_bit_16+1]][((addrbrdaddr_tmp[addrbrdaddr_bit_16:4] * 2) + 1) +: 1]; + end + task_x_buf (wr_mode_b, 15, 8, 1, dobdo_ltmp, dobdo_tmp, dopbdop_ltmp, dopbdop_tmp); + end + + end + 32 : begin + if (b_width >= width) begin + + if ((webweu_tmp[0] === 1'b1 && weawel_tmp[0] === 1'b1) || (seq == 2'b01 && weawel_tmp[0] === 1'b1 && webweu_tmp[0] === 1'b0 && viol_type == 2'b11) || (seq == 2'b01 && wr_mode_b != 2'b01 && wr_mode_a != 2'b01) || (seq == 2'b01 && wr_mode_b == 2'b01 && wr_mode_a != 2'b01 && weawel_tmp[0] === 1'b1) || (seq == 2'b11 && wr_mode_b == 2'b00 && weawel_tmp[0] !== 1'b1)) begin + dobdo_ltmp[7:0] = mem[addrbrdaddr_tmp[14:5]][7:0]; + dopbdop_ltmp[0:0] = memp[addrbrdaddr_tmp[14:5]][0:0]; + task_x_buf (wr_mode_b, 7, 0, 0, dobdo_ltmp, dobdo_tmp, dopbdop_ltmp, dopbdop_tmp); + end + + if ((webweu_tmp[1] === 1'b1 && weawel_tmp[1] === 1'b1) || (seq == 2'b01 && weawel_tmp[1] === 1'b1 && webweu_tmp[1] === 1'b0 && viol_type == 2'b11) || (seq == 2'b01 && wr_mode_b != 2'b01 && wr_mode_a != 2'b01) || (seq == 2'b01 && wr_mode_b == 2'b01 && wr_mode_a != 2'b01 && weawel_tmp[1] === 1'b1) || (seq == 2'b11 && wr_mode_b == 2'b00 && weawel_tmp[1] !== 1'b1)) begin + dobdo_ltmp[15:8] = mem[addrbrdaddr_tmp[14:5]][15:8]; + dopbdop_ltmp[1:1] = memp[addrbrdaddr_tmp[14:5]][1:1]; + task_x_buf (wr_mode_b, 15, 8, 1, dobdo_ltmp, dobdo_tmp, dopbdop_ltmp, dopbdop_tmp); + end + + if ((webweu_tmp[2] === 1'b1 && weawel_tmp[2] === 1'b1) || (seq == 2'b01 && weawel_tmp[2] === 1'b1 && webweu_tmp[2] === 1'b0 && viol_type == 2'b11) || (seq == 2'b01 && wr_mode_b != 2'b01 && wr_mode_a != 2'b01) || (seq == 2'b01 && wr_mode_b == 2'b01 && wr_mode_a != 2'b01 && weawel_tmp[2] === 1'b1) || (seq == 2'b11 && wr_mode_b == 2'b00 && weawel_tmp[2] !== 1'b1)) begin + dobdo_ltmp[23:16] = mem[addrbrdaddr_tmp[14:5]][23:16]; + dopbdop_ltmp[2:2] = memp[addrbrdaddr_tmp[14:5]][2:2]; + task_x_buf (wr_mode_b, 23, 16, 2, dobdo_ltmp, dobdo_tmp, dopbdop_ltmp, dopbdop_tmp); + end + + if ((webweu_tmp[3] === 1'b1 && weawel_tmp[3] === 1'b1) || (seq == 2'b01 && weawel_tmp[3] === 1'b1 && webweu_tmp[3] === 1'b0 && viol_type == 2'b11) || (seq == 2'b01 && wr_mode_b != 2'b01 && wr_mode_a != 2'b01) || (seq == 2'b01 && wr_mode_b == 2'b01 && wr_mode_a != 2'b01 && weawel_tmp[3] === 1'b1) || (seq == 2'b11 && wr_mode_b == 2'b00 && weawel_tmp[3] !== 1'b1)) begin + dobdo_ltmp[31:24] = mem[addrbrdaddr_tmp[14:5]][31:24]; + dopbdop_ltmp[3:3] = memp[addrbrdaddr_tmp[14:5]][3:3]; + task_x_buf (wr_mode_b, 31, 24, 3, dobdo_ltmp, dobdo_tmp, dopbdop_ltmp, dopbdop_tmp); + end + + end // if (b_width >= width) + end + + endcase // case(b_width) + end + endtask // task_col_rd_ram_b + + + task task_rd_ram_a; + + input [15:0] addrawraddr_tmp; + inout [63:0] doado_tmp; + inout [7:0] dopadop_tmp; + + begin + + case (a_width) + 1, 2, 4 : begin + if (a_width >= width) + doado_tmp = mem[addrawraddr_tmp[14:addrawraddr_lbit_124]]; + + else + doado_tmp = mem[addrawraddr_tmp[14:addrawraddr_bit_124+1]][(addrawraddr_tmp[addrawraddr_bit_124:addrawraddr_lbit_124] * a_width) +: a_width]; + end + 8 : begin + if (a_width >= width) begin + doado_tmp = mem[addrawraddr_tmp[14:3]]; + dopadop_tmp = memp[addrawraddr_tmp[14:3]]; + end + else begin + doado_tmp = mem[addrawraddr_tmp[14:addrawraddr_bit_8+1]][(addrawraddr_tmp[addrawraddr_bit_8:3] * 8) +: 8]; + dopadop_tmp = memp[addrawraddr_tmp[14:addrawraddr_bit_8+1]][(addrawraddr_tmp[addrawraddr_bit_8:3] * 1) +: 1]; + end + end + 16 : begin + if (a_width >= width) begin + doado_tmp = mem[addrawraddr_tmp[14:4]]; + dopadop_tmp = memp[addrawraddr_tmp[14:4]]; + end + else begin + doado_tmp = mem[addrawraddr_tmp[14:addrawraddr_bit_16+1]][(addrawraddr_tmp[addrawraddr_bit_16:4] * 16) +: 16]; + dopadop_tmp = memp[addrawraddr_tmp[14:addrawraddr_bit_16+1]][(addrawraddr_tmp[addrawraddr_bit_16:4] * 2) +: 2]; + end + end + 32 : begin + if (a_width >= width) begin + doado_tmp = mem[addrawraddr_tmp[14:5]]; + dopadop_tmp = memp[addrawraddr_tmp[14:5]]; + end + end + + endcase // case(a_width) + + end + endtask // task_rd_ram_a + + + task task_rd_ram_b; + + input [15:0] addrbrdaddr_tmp; + inout [31:0] dobdo_tmp; + inout [3:0] dopbdop_tmp; + + begin + + case (b_width) + 1, 2, 4 : begin + if (b_width >= width) + dobdo_tmp = mem[addrbrdaddr_tmp[14:addrbrdaddr_lbit_124]]; + else + dobdo_tmp = mem[addrbrdaddr_tmp[14:addrbrdaddr_bit_124+1]][(addrbrdaddr_tmp[addrbrdaddr_bit_124:addrbrdaddr_lbit_124] * b_width) +: b_width]; + end + 8 : begin + if (b_width >= width) begin + dobdo_tmp = mem[addrbrdaddr_tmp[14:3]]; + dopbdop_tmp = memp[addrbrdaddr_tmp[14:3]]; + end + else begin + dobdo_tmp = mem[addrbrdaddr_tmp[14:addrbrdaddr_bit_8+1]][(addrbrdaddr_tmp[addrbrdaddr_bit_8:3] * 8) +: 8]; + dopbdop_tmp = memp[addrbrdaddr_tmp[14:addrbrdaddr_bit_8+1]][(addrbrdaddr_tmp[addrbrdaddr_bit_8:3] * 1) +: 1]; + end + end + 16 : begin + if (b_width >= width) begin + dobdo_tmp = mem[addrbrdaddr_tmp[14:4]]; + dopbdop_tmp = memp[addrbrdaddr_tmp[14:4]]; + end + else begin + dobdo_tmp = mem[addrbrdaddr_tmp[14:addrbrdaddr_bit_16+1]][(addrbrdaddr_tmp[addrbrdaddr_bit_16:4] * 16) +: 16]; + dopbdop_tmp = memp[addrbrdaddr_tmp[14:addrbrdaddr_bit_16+1]][(addrbrdaddr_tmp[addrbrdaddr_bit_16:4] * 2) +: 2]; + end + end + 32 : begin + dobdo_tmp = mem[addrbrdaddr_tmp[14:5]]; + dopbdop_tmp = memp[addrbrdaddr_tmp[14:5]]; + end + + endcase + end + endtask // task_rd_ram_b + + + task chk_for_col_msg; + + input weawel_tmp; + input webweu_tmp; + input [15:0] addrawraddr_tmp; + input [15:0] addrbrdaddr_tmp; + + begin + + if ((SIM_COLLISION_CHECK == "ALL" || SIM_COLLISION_CHECK == "WARNING_ONLY") && !(((wr_mode_b == 2'b01 && webweu_tmp === 1'b1 && weawel_tmp === 1'b0) && !(rising_clkawrclk && !rising_clkbrdclk)) || ((wr_mode_a == 2'b01 && weawel_tmp === 1'b1 && webweu_tmp === 1'b0) && !(rising_clkbrdclk && !rising_clkawrclk)))) + + if (weawel_tmp === 1'b1 && webweu_tmp === 1'b1 && col_wr_wr_msg == 1) begin + $display("Memory Collision Error on RAMB16BWE : %m at simulation time %.3f ns.\nA write was requested to the same address simultaneously at both port A and port B of the RAM. The contents written to the RAM at address location %h (hex) of port A and address location %h (hex) of port B are unknown.", $time/1000.0, addrawraddr_tmp, addrbrdaddr_tmp); + col_wr_wr_msg = 0; + end + + else if (weawel_tmp === 1'b1 && webweu_tmp === 1'b0 && col_wra_rdb_msg == 1) begin + $display("Memory Collision Error on RAMB16BWE : %m at simulation time %.3f ns.\nA read was performed on address %h (hex) of port B while a write was requested to the same address on port A. The write will be successful however the read value on port B is unknown until the next CLKBRDCLK cycle.", $time/1000.0, addrbrdaddr_tmp); + col_wra_rdb_msg = 0; + end + + else if (weawel_tmp === 1'b0 && webweu_tmp === 1'b1 && col_wrb_rda_msg == 1) begin + $display("Memory Collision Error on RAMB16BWE : %m at simulation time %.3f ns.\nA read was performed on address %h (hex) of port A while a write was requested to the same address on port B. The write will be successful however the read value on port A is unknown until the next CLKAWRCLK cycle.", $time/1000.0, addrawraddr_tmp); + col_wrb_rda_msg = 0; + end + + end + + endtask // chk_for_col_msg + + + specify + + (CLKA => DOA[0]) = (100, 100); + (CLKA => DOA[1]) = (100, 100); + (CLKA => DOA[2]) = (100, 100); + (CLKA => DOA[3]) = (100, 100); + (CLKA => DOA[4]) = (100, 100); + (CLKA => DOA[5]) = (100, 100); + (CLKA => DOA[6]) = (100, 100); + (CLKA => DOA[7]) = (100, 100); + (CLKA => DOA[8]) = (100, 100); + (CLKA => DOA[9]) = (100, 100); + (CLKA => DOA[10]) = (100, 100); + (CLKA => DOA[11]) = (100, 100); + (CLKA => DOA[12]) = (100, 100); + (CLKA => DOA[13]) = (100, 100); + (CLKA => DOA[14]) = (100, 100); + (CLKA => DOA[15]) = (100, 100); + (CLKA => DOA[16]) = (100, 100); + (CLKA => DOA[17]) = (100, 100); + (CLKA => DOA[18]) = (100, 100); + (CLKA => DOA[19]) = (100, 100); + (CLKA => DOA[20]) = (100, 100); + (CLKA => DOA[21]) = (100, 100); + (CLKA => DOA[22]) = (100, 100); + (CLKA => DOA[23]) = (100, 100); + (CLKA => DOA[24]) = (100, 100); + (CLKA => DOA[25]) = (100, 100); + (CLKA => DOA[26]) = (100, 100); + (CLKA => DOA[27]) = (100, 100); + (CLKA => DOA[28]) = (100, 100); + (CLKA => DOA[29]) = (100, 100); + (CLKA => DOA[30]) = (100, 100); + (CLKA => DOA[31]) = (100, 100); + (CLKA => DOPA[0]) = (100, 100); + (CLKA => DOPA[1]) = (100, 100); + (CLKA => DOPA[2]) = (100, 100); + (CLKA => DOPA[3]) = (100, 100); + (CLKB => DOB[0]) = (100, 100); + (CLKB => DOB[1]) = (100, 100); + (CLKB => DOB[2]) = (100, 100); + (CLKB => DOB[3]) = (100, 100); + (CLKB => DOB[4]) = (100, 100); + (CLKB => DOB[5]) = (100, 100); + (CLKB => DOB[6]) = (100, 100); + (CLKB => DOB[7]) = (100, 100); + (CLKB => DOB[8]) = (100, 100); + (CLKB => DOB[9]) = (100, 100); + (CLKB => DOB[10]) = (100, 100); + (CLKB => DOB[11]) = (100, 100); + (CLKB => DOB[12]) = (100, 100); + (CLKB => DOB[13]) = (100, 100); + (CLKB => DOB[14]) = (100, 100); + (CLKB => DOB[15]) = (100, 100); + (CLKB => DOB[16]) = (100, 100); + (CLKB => DOB[17]) = (100, 100); + (CLKB => DOB[18]) = (100, 100); + (CLKB => DOB[19]) = (100, 100); + (CLKB => DOB[20]) = (100, 100); + (CLKB => DOB[21]) = (100, 100); + (CLKB => DOB[22]) = (100, 100); + (CLKB => DOB[23]) = (100, 100); + (CLKB => DOB[24]) = (100, 100); + (CLKB => DOB[25]) = (100, 100); + (CLKB => DOB[26]) = (100, 100); + (CLKB => DOB[27]) = (100, 100); + (CLKB => DOB[28]) = (100, 100); + (CLKB => DOB[29]) = (100, 100); + (CLKB => DOB[30]) = (100, 100); + (CLKB => DOB[31]) = (100, 100); + (CLKB => DOPB[0]) = (100, 100); + (CLKB => DOPB[1]) = (100, 100); + (CLKB => DOPB[2]) = (100, 100); + (CLKB => DOPB[3]) = (100, 100); + + specparam PATHPULSE$ = 0; + + endspecify + + +endmodule // RAMB16BWE diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/RAMB16BWER.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/RAMB16BWER.v new file mode 100644 index 0000000..1ace65b --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/RAMB16BWER.v @@ -0,0 +1,1972 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/sandia/RAMB16BWER.v,v 1.28.24.1 2010/03/29 22:55:36 wloo Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2008 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component 16K-Bit Data and +// / / 2K-Bit Parity Dual Port Block RAM. +// /___/ /\ Filename : RAMB16BWER.v +// \ \ / \ Timestamp : Wed Dec 24 14:38:27 PST 2008 +// \___\/\___\ +// +// Revision: +// 12/24/08 - Initial version. +// 01/26/09 - Update reset behavior (IR 500935). +// 02/11/09 - Update address mapping for spartan6 (IR 506186). +// 02/19/09 - Fixed asychronous reset in register mode (IR 506208). +// 03/10/09 - Remove address mapping for spartan6 (CR 508325). +// - X's the unused bits of outputs (CR 511363). +// 03/20/09 - Fix unusual behavior of X's in the unused bits of outputs (CR 513167). +// 03/15/10 - Updated address collision for asynchronous clocks and read first mode (CR 547447). +// End Revision + +`timescale 1 ps/1 ps + +module RAMB16BWER (DOA, DOB, DOPA, DOPB, + ADDRA, ADDRB, CLKA, CLKB, DIA, DIB, DIPA, DIPB, ENA, ENB, REGCEA, REGCEB, RSTA, RSTB, WEA, WEB); + + output [31:0] DOA; + output [31:0] DOB; + output [3:0] DOPA; + output [3:0] DOPB; + + input [13:0] ADDRA; + input [13:0] ADDRB; + input CLKA; + input CLKB; + input [31:0] DIA; + input [31:0] DIB; + input [3:0] DIPA; + input [3:0] DIPB; + input ENA; + input ENB; + input REGCEA; + input REGCEB; + input RSTA; + input RSTB; + input [3:0] WEA; + input [3:0] WEB; + + parameter integer DATA_WIDTH_A = 0; + parameter integer DATA_WIDTH_B = 0; + parameter integer DOA_REG = 0; + parameter integer DOB_REG = 0; + parameter EN_RSTRAM_A = "TRUE"; + parameter EN_RSTRAM_B = "TRUE"; + parameter INITP_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_A = 36'h0; + parameter INIT_B = 36'h0; + parameter INIT_FILE = "NONE"; + parameter RSTTYPE = "SYNC"; + parameter RST_PRIORITY_A = "CE"; + parameter RST_PRIORITY_B = "CE"; + parameter SETUP_ALL = 1000; + parameter SETUP_READ_FIRST = 3000; + parameter SIM_DEVICE = "SPARTAN3ADSP"; + parameter SIM_COLLISION_CHECK = "ALL"; + parameter SRVAL_A = 36'h0; + parameter SRVAL_B = 36'h0; + parameter WRITE_MODE_A = "WRITE_FIRST"; + parameter WRITE_MODE_B = "WRITE_FIRST"; + + + wire [15:0] addrawraddr_in, addrbrdaddr_in; + wire [13:0] col_addra_reconstruct, col_addrb_reconstruct; + reg [13:0] col_addra_reconstruct_reg, col_addrb_reconstruct_reg; + + localparam widest_width = (DATA_WIDTH_A >= DATA_WIDTH_B) ? DATA_WIDTH_A : DATA_WIDTH_B; + + localparam a_width = (DATA_WIDTH_A == 1) ? 1 : (DATA_WIDTH_A == 2) ? 2 : (DATA_WIDTH_A == 4) ? 4 : + (DATA_WIDTH_A == 9) ? 8 : (DATA_WIDTH_A == 18) ? 16 : (DATA_WIDTH_A == 36) ? 32 : 32; + + localparam b_width = (DATA_WIDTH_B == 1) ? 1 : (DATA_WIDTH_B == 2) ? 2 : (DATA_WIDTH_B == 4) ? 4 : + (DATA_WIDTH_B == 9) ? 8 : (DATA_WIDTH_B == 18) ? 16 : (DATA_WIDTH_B == 36) ? 32 : 32; + + localparam a_widthp = (DATA_WIDTH_A == 9) ? 1 : (DATA_WIDTH_A == 18) ? 2 : (DATA_WIDTH_A == 36) ? 4 : 4; + + localparam b_widthp = (DATA_WIDTH_B == 9) ? 1 : (DATA_WIDTH_B == 18) ? 2 : (DATA_WIDTH_B == 36) ? 4 : 4; + + localparam col_addr_lsb = (widest_width == 1) ? 0 : (widest_width == 2) ? 1 : (widest_width == 4) ? 2 : + (widest_width == 9) ? 3 : (widest_width == 18) ? 4 : (widest_width == 36) ? 5 : 0; + + assign col_addra_reconstruct[13:0] = (SIM_DEVICE == "SPARTAN6" && (WRITE_MODE_A == "READ_FIRST" || WRITE_MODE_B == "READ_FIRST")) ? + ((DATA_WIDTH_A <= 18 && DATA_WIDTH_B <= 18) ? {addrawraddr_in[13:6],1'b0,addrawraddr_in[4],4'b0} : + (DATA_WIDTH_A == 36 || DATA_WIDTH_B == 36) ? {addrawraddr_in[13:7],1'b0,addrawraddr_in[5],5'b0} : addrawraddr_in[13:0]) : + addrawraddr_in[13:0]; + + assign col_addrb_reconstruct[13:0] = (SIM_DEVICE == "SPARTAN6" && (WRITE_MODE_A == "READ_FIRST" || WRITE_MODE_B == "READ_FIRST")) ? + ((DATA_WIDTH_A <= 18 && DATA_WIDTH_B <= 18) ? {addrbrdaddr_in[13:6],1'b0,addrbrdaddr_in[4],4'b0} : + (DATA_WIDTH_A == 36 || DATA_WIDTH_B == 36) ? {addrbrdaddr_in[13:7],1'b0,addrbrdaddr_in[5],5'b0} : addrbrdaddr_in[13:0]) : + addrbrdaddr_in[13:0]; + + localparam width = (widest_width == 1) ? 1 : (widest_width == 2) ? 2 : (widest_width == 4) ? 4 : + (widest_width == 9) ? 8 : (widest_width == 18) ? 16 : (widest_width == 36) ? 32 : 32; + + localparam widthp = (widest_width == 9) ? 1 : (widest_width == 18) ? 2 : (widest_width == 36) ? 4 : 4; + + localparam addrawraddr_lbit_124 = (DATA_WIDTH_A == 1) ? 0 : (DATA_WIDTH_A == 2) ? 1 : + (DATA_WIDTH_A == 4) ? 2 : (DATA_WIDTH_A == 9) ? 3 : + (DATA_WIDTH_A == 18) ? 4 : (DATA_WIDTH_A == 36) ? 5 : 5; + + localparam addrbrdaddr_lbit_124 = (DATA_WIDTH_B == 1) ? 0 : (DATA_WIDTH_B == 2) ? 1 : + (DATA_WIDTH_B == 4) ? 2 : (DATA_WIDTH_B == 9) ? 3 : + (DATA_WIDTH_B == 18) ? 4 : (DATA_WIDTH_B == 36) ? 5 : 5; + + localparam addrawraddr_bit_124 = (DATA_WIDTH_A == 1 && widest_width == 2) ? 0 : (DATA_WIDTH_A == 1 && widest_width == 4) ? 1 : + (DATA_WIDTH_A == 1 && widest_width == 9) ? 2 : (DATA_WIDTH_A == 1 && widest_width == 18) ? 3 : + (DATA_WIDTH_A == 1 && widest_width == 36) ? 4 : (DATA_WIDTH_A == 2 && widest_width == 4) ? 1 : + (DATA_WIDTH_A == 2 && widest_width == 9) ? 2 : (DATA_WIDTH_A == 2 && widest_width == 18) ? 3 : + (DATA_WIDTH_A == 2 && widest_width == 36) ? 4 : (DATA_WIDTH_A == 4 && widest_width == 9) ? 2 : + (DATA_WIDTH_A == 4 && widest_width == 18) ? 3 : (DATA_WIDTH_A == 4 && widest_width == 36) ? 4 : 5; + + localparam addrbrdaddr_bit_124 = (DATA_WIDTH_B == 1 && widest_width == 2) ? 0 : (DATA_WIDTH_B == 1 && widest_width == 4) ? 1 : + (DATA_WIDTH_B == 1 && widest_width == 9) ? 2 : (DATA_WIDTH_B == 1 && widest_width == 18) ? 3 : + (DATA_WIDTH_B == 1 && widest_width == 36) ? 4 : (DATA_WIDTH_B == 2 && widest_width == 4) ? 1 : + (DATA_WIDTH_B == 2 && widest_width == 9) ? 2 : (DATA_WIDTH_B == 2 && widest_width == 18) ? 3 : + (DATA_WIDTH_B == 2 && widest_width == 36) ? 4 : (DATA_WIDTH_B == 4 && widest_width == 9) ? 2 : + (DATA_WIDTH_B == 4 && widest_width == 18) ? 3 : (DATA_WIDTH_B == 4 && widest_width == 36) ? 4 : 5; + + localparam addrawraddr_bit_8 = (DATA_WIDTH_A == 9 && widest_width == 18) ? 3 : (DATA_WIDTH_A == 9 && widest_width == 36) ? 4 : 4; + + localparam addrawraddr_bit_16 = 4; // There is only 36 larger than 18 + + localparam addrbrdaddr_bit_8 = (DATA_WIDTH_B == 9 && widest_width == 18) ? 3 : (DATA_WIDTH_B == 9 && widest_width == 36) ? 4 : 4; + + localparam addrbrdaddr_bit_16 = 4; // There is only 36 larger than 18 + + + localparam mem_depth = (widest_width == 1) ? 16384 : (widest_width == 2) ? 8192 : (widest_width == 4) ? 4096 : (widest_width == 9) ? 2048 : + (widest_width == 18) ? 1024 :(widest_width == 36) ? 512 : 16384; + + localparam memp_depth = (widest_width == 9) ? 2048 : (widest_width == 18) ? 1024 : (widest_width == 36) ? 512 : 2048; + + reg [widest_width-1:0] tmp_mem [mem_depth-1:0]; + + reg [width-1:0] mem [mem_depth-1:0]; + reg [widthp-1:0] memp [memp_depth-1:0]; + + integer count, countp, init_mult, initp_mult, large_width; + integer count1, countp1, i, i1, i_p, i_mem; + + reg tmp1; + reg [1:0] wr_mode_a, wr_mode_b; + + reg [31:0] doado_out, doado_buf, doado_outreg, doado_out_out; + reg [31:0] dobdo_out, dobdo_buf, dobdo_outreg, dobdo_out_out; + reg [3:0] dopbdop_out, dopbdop_buf, dopbdop_outreg, dopbdop_out_out; + reg [3:0] dopadop_out, dopadop_buf, dopadop_outreg, dopadop_out_out; + + reg [63:0] di_x = 64'bx; + + reg [7:0] weawel_reg; + reg enbrden_reg; + reg [7:0] webweu_reg, webweu_tmp; + reg rising_clkawrclk = 1'b0, rising_clkbrdclk = 1'b0; + reg [15:0] addrawraddr_reg, addrbrdaddr_reg, addrawraddr_tmp, addrbrdaddr_tmp; + + reg [63:0] diadi_reg, dibdi_reg; + reg [3:0] dipadip_reg; + reg [7:0] dipbdip_reg; + reg [1:0] viol_type = 2'b00, seq = 2'b00; + reg [15:0] addr_tmp; + reg [7:0] we_tmp; + integer viol_time = 0; + reg col_wr_wr_msg = 1, col_wra_rdb_msg = 1, col_wrb_rda_msg = 1; + reg finish_error = 0; + + time curr_time, prev_time; + + wire clkawrclk_in, clkbrdclk_in; + + wire enawren_in, enbrden_in, regcea_in, regcebregce_in, rsta_in, rstbrst_in; + + wire [a_width-1:0] diadi_int; + wire [b_width-1:0] dibdi_int; + wire [a_widthp-1:0] dipadip_int; + wire [b_widthp-1:0] dipbdip_int; + wire [3:0] weawel_int, webweu_int; + + reg notifier, notifier_a, notifier_b; + reg notifier_addra0, notifier_addra1, notifier_addra2, notifier_addra3, notifier_addra4; + reg notifier_addra5, notifier_addra6, notifier_addra7, notifier_addra8, notifier_addra9; + reg notifier_addra10, notifier_addra11, notifier_addra12, notifier_addra13; + reg notifier_addrb0, notifier_addrb1, notifier_addrb2, notifier_addrb3, notifier_addrb4; + reg notifier_addrb5, notifier_addrb6, notifier_addrb7, notifier_addrb8, notifier_addrb9; + reg notifier_addrb10, notifier_addrb11, notifier_addrb12, notifier_addrb13; + + + tri0 gsr_in = glbl.GSR; + + assign clkawrclk_in = CLKA; + assign clkbrdclk_in = CLKB; + + assign diadi_int = DIA; + assign dibdi_int = DIB; + assign dipadip_int = DIPA; + assign dipbdip_int = DIPB; + assign DOA = doado_out_out; + assign DOPA = dopadop_out_out; + assign DOB = dobdo_out_out; + assign DOPB = dopbdop_out_out; + + assign enawren_in = ENA; + assign enbrden_in = ENB; + assign regcea_in = REGCEA; + assign regcebregce_in = REGCEB; + assign rsta_in = RSTA; + assign rstbrst_in = RSTB; + assign weawel_int = WEA; + assign webweu_int = WEB; + + assign addrawraddr_in = {2'b00,ADDRA}; + assign addrbrdaddr_in = {2'b00,ADDRB}; + + + initial begin + + if (INIT_FILE == "NONE") begin + + init_mult = 256/width; + + for (count = 0; count < init_mult; count = count + 1) begin + for (count1 = 0; count1 < width; count1 = count1 + 1) begin + + mem[count][count1] = INIT_00[(count * width) + count1]; + mem[count + (init_mult * 1)][count1] = INIT_01[(count * width) + count1]; + mem[count + (init_mult * 2)][count1] = INIT_02[(count * width) + count1]; + mem[count + (init_mult * 3)][count1] = INIT_03[(count * width) + count1]; + mem[count + (init_mult * 4)][count1] = INIT_04[(count * width) + count1]; + mem[count + (init_mult * 5)][count1] = INIT_05[(count * width) + count1]; + mem[count + (init_mult * 6)][count1] = INIT_06[(count * width) + count1]; + mem[count + (init_mult * 7)][count1] = INIT_07[(count * width) + count1]; + mem[count + (init_mult * 8)][count1] = INIT_08[(count * width) + count1]; + mem[count + (init_mult * 9)][count1] = INIT_09[(count * width) + count1]; + mem[count + (init_mult * 10)][count1] = INIT_0A[(count * width) + count1]; + mem[count + (init_mult * 11)][count1] = INIT_0B[(count * width) + count1]; + mem[count + (init_mult * 12)][count1] = INIT_0C[(count * width) + count1]; + mem[count + (init_mult * 13)][count1] = INIT_0D[(count * width) + count1]; + mem[count + (init_mult * 14)][count1] = INIT_0E[(count * width) + count1]; + mem[count + (init_mult * 15)][count1] = INIT_0F[(count * width) + count1]; + mem[count + (init_mult * 16)][count1] = INIT_10[(count * width) + count1]; + mem[count + (init_mult * 17)][count1] = INIT_11[(count * width) + count1]; + mem[count + (init_mult * 18)][count1] = INIT_12[(count * width) + count1]; + mem[count + (init_mult * 19)][count1] = INIT_13[(count * width) + count1]; + mem[count + (init_mult * 20)][count1] = INIT_14[(count * width) + count1]; + mem[count + (init_mult * 21)][count1] = INIT_15[(count * width) + count1]; + mem[count + (init_mult * 22)][count1] = INIT_16[(count * width) + count1]; + mem[count + (init_mult * 23)][count1] = INIT_17[(count * width) + count1]; + mem[count + (init_mult * 24)][count1] = INIT_18[(count * width) + count1]; + mem[count + (init_mult * 25)][count1] = INIT_19[(count * width) + count1]; + mem[count + (init_mult * 26)][count1] = INIT_1A[(count * width) + count1]; + mem[count + (init_mult * 27)][count1] = INIT_1B[(count * width) + count1]; + mem[count + (init_mult * 28)][count1] = INIT_1C[(count * width) + count1]; + mem[count + (init_mult * 29)][count1] = INIT_1D[(count * width) + count1]; + mem[count + (init_mult * 30)][count1] = INIT_1E[(count * width) + count1]; + mem[count + (init_mult * 31)][count1] = INIT_1F[(count * width) + count1]; + mem[count + (init_mult * 32)][count1] = INIT_20[(count * width) + count1]; + mem[count + (init_mult * 33)][count1] = INIT_21[(count * width) + count1]; + mem[count + (init_mult * 34)][count1] = INIT_22[(count * width) + count1]; + mem[count + (init_mult * 35)][count1] = INIT_23[(count * width) + count1]; + mem[count + (init_mult * 36)][count1] = INIT_24[(count * width) + count1]; + mem[count + (init_mult * 37)][count1] = INIT_25[(count * width) + count1]; + mem[count + (init_mult * 38)][count1] = INIT_26[(count * width) + count1]; + mem[count + (init_mult * 39)][count1] = INIT_27[(count * width) + count1]; + mem[count + (init_mult * 40)][count1] = INIT_28[(count * width) + count1]; + mem[count + (init_mult * 41)][count1] = INIT_29[(count * width) + count1]; + mem[count + (init_mult * 42)][count1] = INIT_2A[(count * width) + count1]; + mem[count + (init_mult * 43)][count1] = INIT_2B[(count * width) + count1]; + mem[count + (init_mult * 44)][count1] = INIT_2C[(count * width) + count1]; + mem[count + (init_mult * 45)][count1] = INIT_2D[(count * width) + count1]; + mem[count + (init_mult * 46)][count1] = INIT_2E[(count * width) + count1]; + mem[count + (init_mult * 47)][count1] = INIT_2F[(count * width) + count1]; + mem[count + (init_mult * 48)][count1] = INIT_30[(count * width) + count1]; + mem[count + (init_mult * 49)][count1] = INIT_31[(count * width) + count1]; + mem[count + (init_mult * 50)][count1] = INIT_32[(count * width) + count1]; + mem[count + (init_mult * 51)][count1] = INIT_33[(count * width) + count1]; + mem[count + (init_mult * 52)][count1] = INIT_34[(count * width) + count1]; + mem[count + (init_mult * 53)][count1] = INIT_35[(count * width) + count1]; + mem[count + (init_mult * 54)][count1] = INIT_36[(count * width) + count1]; + mem[count + (init_mult * 55)][count1] = INIT_37[(count * width) + count1]; + mem[count + (init_mult * 56)][count1] = INIT_38[(count * width) + count1]; + mem[count + (init_mult * 57)][count1] = INIT_39[(count * width) + count1]; + mem[count + (init_mult * 58)][count1] = INIT_3A[(count * width) + count1]; + mem[count + (init_mult * 59)][count1] = INIT_3B[(count * width) + count1]; + mem[count + (init_mult * 60)][count1] = INIT_3C[(count * width) + count1]; + mem[count + (init_mult * 61)][count1] = INIT_3D[(count * width) + count1]; + mem[count + (init_mult * 62)][count1] = INIT_3E[(count * width) + count1]; + mem[count + (init_mult * 63)][count1] = INIT_3F[(count * width) + count1]; + end // for (count1 = 0; count1 < width; count1 = count1 + 1) + end // for (count = 0; count < init_mult; count = count + 1) + + + if (width >= 8) begin + + initp_mult = 256/widthp; + + for (countp = 0; countp < initp_mult; countp = countp + 1) begin + for (countp1 = 0; countp1 < widthp; countp1 = countp1 + 1) begin + + memp[countp][countp1] = INITP_00[(countp * widthp) + countp1]; + memp[countp + (initp_mult * 1)][countp1] = INITP_01[(countp * widthp) + countp1]; + memp[countp + (initp_mult * 2)][countp1] = INITP_02[(countp * widthp) + countp1]; + memp[countp + (initp_mult * 3)][countp1] = INITP_03[(countp * widthp) + countp1]; + memp[countp + (initp_mult * 4)][countp1] = INITP_04[(countp * widthp) + countp1]; + memp[countp + (initp_mult * 5)][countp1] = INITP_05[(countp * widthp) + countp1]; + memp[countp + (initp_mult * 6)][countp1] = INITP_06[(countp * widthp) + countp1]; + memp[countp + (initp_mult * 7)][countp1] = INITP_07[(countp * widthp) + countp1]; + + end // for (countp1 = 0; countp1 < widthp; countp1 = countp1 + 1) + end // for (countp = 0; countp < initp_mult; countp = countp + 1) + + end // if (width >= 8) + + end // if (INIT_FILE == "NONE") + + else begin + + $readmemh (INIT_FILE, tmp_mem); + + case (widest_width) + + 1, 2, 4 : for (i_mem = 0; i_mem <= mem_depth; i_mem = i_mem + 1) + mem[i_mem] = tmp_mem [i_mem]; + + 9 : for (i_mem = 0; i_mem <= mem_depth; i_mem = i_mem + 1) begin + mem[i_mem] = tmp_mem[i_mem][0 +: 8]; + memp[i_mem] = tmp_mem[i_mem][8 +: 1]; + end + + 18 : for (i_mem = 0; i_mem <= mem_depth; i_mem = i_mem + 1) begin + mem[i_mem] = tmp_mem[i_mem][0 +: 16]; + memp[i_mem] = tmp_mem[i_mem][16 +: 2]; + end + + 36 : for (i_mem = 0; i_mem <= mem_depth; i_mem = i_mem + 1) begin + mem[i_mem] = tmp_mem[i_mem][0 +: 32]; + memp[i_mem] = tmp_mem[i_mem][32 +: 4]; + end + + endcase // case(widest_width) + + end // else: !if(INIT_FILE == "NONE") + + + case (DATA_WIDTH_A) + + 0, 1, 2, 4, 9, 18, 36: ; + + default : begin + $display("Attribute Syntax Error : The attribute DATA_WIDTH_A on RAMB16BWER instance %m is set to %d. Legal values for this attribute are 0, 1, 2, 4, 9, 18 or 36.", DATA_WIDTH_A); + finish_error = 1; + end + + endcase // case(DATA_WIDTH_A) + + + case (DATA_WIDTH_B) + + 0, 1, 2, 4, 9, 18, 36: ; + + default : begin + $display("Attribute Syntax Error : The attribute DATA_WIDTH_B on RAMB16BWER instance %m is set to %d. Legal values for this attribute are 0, 1, 2, 4, 9, 18 or 36.", DATA_WIDTH_B); + finish_error = 1; + end + + endcase // case(DATA_WIDTH_B) + + + if (DATA_WIDTH_A == 0 && DATA_WIDTH_B == 0) begin + $display("Attribute Syntax Error : Attributes DATA_WIDTH_A and DATA_WIDTH_B on RAMB16BWER instance %m, both can not be 0."); + finish_error = 1; + end + + + case (WRITE_MODE_A) + "WRITE_FIRST" : wr_mode_a <= 2'b00; + "READ_FIRST" : wr_mode_a <= 2'b01; + "NO_CHANGE" : wr_mode_a <= 2'b10; + default : begin + $display("Attribute Syntax Error : The Attribute WRITE_MODE_A on RAMB16BWER instance %m is set to %s. Legal values for this attribute are WRITE_FIRST, READ_FIRST or NO_CHANGE.", WRITE_MODE_A); + finish_error = 1; + end + endcase + + + case (WRITE_MODE_B) + "WRITE_FIRST" : wr_mode_b <= 2'b00; + "READ_FIRST" : wr_mode_b <= 2'b01; + "NO_CHANGE" : wr_mode_b <= 2'b10; + default : begin + $display("Attribute Syntax Error : The Attribute WRITE_MODE_B on RAMB16BWER instance %m is set to %s. Legal values for this attribute are WRITE_FIRST, READ_FIRST or NO_CHANGE.", WRITE_MODE_B); + finish_error = 1; + end + endcase + + + if ((SIM_COLLISION_CHECK != "ALL") && (SIM_COLLISION_CHECK != "NONE") && (SIM_COLLISION_CHECK != "WARNING_ONLY") && (SIM_COLLISION_CHECK != "GENERATE_X_ONLY")) begin + + $display("Attribute Syntax Error : The attribute SIM_COLLISION_CHECK on RAMB16BWER instance %m is set to %s. Legal values for this attribute are ALL, NONE, WARNING_ONLY or GENERATE_X_ONLY.", SIM_COLLISION_CHECK); + finish_error = 1; + + end + + + if ((EN_RSTRAM_A != "TRUE") && (EN_RSTRAM_A != "FALSE")) begin + $display("Attribute Syntax Error : The attribute EN_RSTRAM_A on RAMB16BWER instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", EN_RSTRAM_A); + finish_error = 1; + end + + + if ((EN_RSTRAM_B != "TRUE") && (EN_RSTRAM_B != "FALSE")) begin + $display("Attribute Syntax Error : The attribute EN_RSTRAM_B on RAMB16BWER instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", EN_RSTRAM_B); + finish_error = 1; + end + + + if ((RST_PRIORITY_A != "SR") && (RST_PRIORITY_A != "CE")) begin + $display("Attribute Syntax Error : The attribute RST_PRIORITY_A on RAMB16BWER instance %m is set to %s. Legal values for this attribute are CE or SR.", RST_PRIORITY_A); + finish_error = 1; + end + + + if ((RST_PRIORITY_B != "SR") && (RST_PRIORITY_B != "CE")) begin + $display("Attribute Syntax Error : The attribute RST_PRIORITY_B on RAMB16BWER instance %m is set to %s. Legal values for this attribute are CE or SR.", RST_PRIORITY_B); + finish_error = 1; + end + + + if (finish_error == 1) + $finish; + + + end // initial begin + + + always @(gsr_in) + if (gsr_in) begin + + assign doado_out = INIT_A[0 +: a_width]; + + if (a_width >= 8) begin + assign dopadop_out = INIT_A[a_width +: a_widthp]; + end + + assign dobdo_out = INIT_B[0 +: b_width]; + + if (b_width >= 8) begin + assign dopbdop_out = INIT_B[b_width +: b_widthp]; + end + + end + else begin + deassign doado_out; + deassign dopadop_out; + deassign dobdo_out; + deassign dopbdop_out; + end + + + always @(rsta_in or enawren_in or regcea_in) begin + + if (RSTTYPE == "ASYNC" && gsr_in == 1'b0 && rsta_in === 1'b1) begin // async reset + + // reset latch regardless DOA_REG + if (((enawren_in == 1'b1 && RST_PRIORITY_A == "CE") || RST_PRIORITY_A == "SR") && EN_RSTRAM_A == "TRUE") begin + + assign doado_buf = SRVAL_A[0 +: a_width]; + assign doado_out = SRVAL_A[0 +: a_width]; + + if (a_width >= 8) begin + assign dopadop_buf = SRVAL_A[a_width +: a_widthp]; + assign dopadop_out = SRVAL_A[a_width +: a_widthp]; + end + end + + + if (DOA_REG == 1) begin + + if (SIM_DEVICE == "SPARTAN3ADSP") begin + + if ((enawren_in == 1'b1 && RST_PRIORITY_A == "CE") || RST_PRIORITY_A == "SR") begin + assign doado_outreg = SRVAL_A[0 +: a_width]; + + if (a_width >= 8) + assign dopadop_outreg = SRVAL_A[a_width +: a_widthp]; + + end + end // if (SIM_DEVICE == "SPARTAN3ADSP") + else if (SIM_DEVICE == "SPARTAN6") begin + + if ((regcea_in == 1'b1 && RST_PRIORITY_A == "CE") || RST_PRIORITY_A == "SR") begin + assign doado_outreg = SRVAL_A[0 +: a_width]; + + if (a_width >= 8) + assign dopadop_outreg = SRVAL_A[a_width +: a_widthp]; + + end + end + end // if (DOA_REG == 1) + end // if (RSTTYPE == "ASYNC" && gsr_in == 1'b0 && rsta_in === 1'b1) + else if (rsta_in === 1'b0) begin + + deassign doado_buf; + deassign doado_out; + deassign dopadop_buf; + deassign dopadop_out; + deassign doado_outreg; + deassign dopadop_outreg; + + end + + end // always @ (rsta_in or enawren_in or regcea_in) + + + always @(rstbrst_in or enbrden_in or regcebregce_in) begin + + if (RSTTYPE == "ASYNC" && gsr_in == 1'b0 && rstbrst_in == 1'b1) begin + + // reset latch regardless DOB_REG + if (((enbrden_in == 1'b1 && RST_PRIORITY_B == "CE") || RST_PRIORITY_B == "SR") && EN_RSTRAM_B == "TRUE") begin + + assign dobdo_buf = SRVAL_B[0 +: b_width]; + assign dobdo_out = SRVAL_B[0 +: b_width]; + + if (b_width >= 8) begin + assign dopbdop_buf = SRVAL_B[b_width +: b_widthp]; + assign dopbdop_out = SRVAL_B[b_width +: b_widthp]; + end + end + + + if (DOB_REG == 1) begin + + if (SIM_DEVICE == "SPARTAN3ADSP") begin + + if ((enbrden_in == 1'b1 && RST_PRIORITY_B == "CE") || RST_PRIORITY_B == "SR") begin + assign dobdo_outreg = SRVAL_B[0 +: b_width]; + + if (b_width >= 8) + assign dopbdop_outreg = SRVAL_B[b_width +: b_widthp]; + + end + end // if (SIM_DEVICE == "SPARTAN3ADSP") + else if (SIM_DEVICE == "SPARTAN6") begin + + if ((regcebregce_in == 1'b1 && RST_PRIORITY_B == "CE") || RST_PRIORITY_B == "SR") begin + assign dobdo_outreg = SRVAL_B[0 +: b_width]; + + if (b_width >= 8) + assign dopbdop_outreg = SRVAL_B[b_width +: b_widthp]; + + end + end + end // if (DOB_REG == 1) + end // if (RSTTYPE == "ASYNC" && gsr_in == 1'b0 && rstbrst_in == 1'b1) + else if (rstbrst_in == 1'b0) begin + + deassign dobdo_buf; + deassign dobdo_out; + deassign dopbdop_buf; + deassign dopbdop_out; + deassign dobdo_outreg; + deassign dopbdop_outreg; + + end + + end // always @ (rstbrst_in or enbrden_in or regcebregce_in) + + + always @(posedge clkawrclk_in) begin + + rising_clkawrclk = 1; + + if (enawren_in === 1'b1) begin + prev_time = curr_time; + curr_time = $time; + addrawraddr_reg = addrawraddr_in; + weawel_reg = weawel_int; + diadi_reg = diadi_int; + dipadip_reg = dipadip_int; + col_addra_reconstruct_reg = col_addra_reconstruct; + end + + end + + always @(posedge clkbrdclk_in) begin + + rising_clkbrdclk = 1; + + if (enbrden_in === 1'b1) begin + prev_time = curr_time; + curr_time = $time; + addrbrdaddr_reg = addrbrdaddr_in; + webweu_reg = webweu_int; + enbrden_reg = enbrden_in; + dibdi_reg = dibdi_int; + dipbdip_reg = dipbdip_int; + col_addrb_reconstruct_reg = col_addrb_reconstruct; + end + + end // always @ (posedge clkbrdclk_in) + + + always @(posedge rising_clkawrclk or posedge rising_clkbrdclk) begin + + +/************************************* Collision starts *****************************************/ + + if (SIM_COLLISION_CHECK != "NONE") begin + + if (gsr_in === 1'b0) begin + if (curr_time - prev_time <= 100) begin + viol_time = 1; + end + else if (curr_time - prev_time <= SETUP_READ_FIRST) begin + viol_time = 2; + end + + + if (enawren_in === 1'b0 || enbrden_in === 1'b0) + viol_time = 0; + + + if ((DATA_WIDTH_A <= 9 && weawel_int[0] === 1'b0) || (DATA_WIDTH_A == 18 && weawel_int[1:0] === 2'b00) || (DATA_WIDTH_A == 36 && weawel_int[3:0] === 4'b0000)) + if ((DATA_WIDTH_B <= 9 && webweu_int[0] === 1'b0) || (DATA_WIDTH_B == 18 && webweu_int[1:0] === 2'b00) || (DATA_WIDTH_B == 36 && webweu_int[3:0] === 4'b0000)) + viol_time = 0; + + + if (viol_time != 0) begin + + if ((rising_clkawrclk && rising_clkbrdclk) || viol_time == 1) begin + if (addrawraddr_in[13:col_addr_lsb] === addrbrdaddr_in[13:col_addr_lsb]) begin + + viol_type = 2'b01; + + task_rd_ram_a (addrawraddr_in, doado_buf, dopadop_buf); + task_rd_ram_b (addrbrdaddr_in, dobdo_buf, dopbdop_buf); + + task_col_wr_ram_a (2'b00, webweu_int, weawel_int, di_x, di_x[7:0], addrbrdaddr_in, addrawraddr_in); + task_col_wr_ram_b (2'b00, weawel_int, webweu_int, di_x, di_x[7:0], addrawraddr_in, addrbrdaddr_in); + + task_col_rd_ram_a (2'b01, webweu_int, weawel_int, addrawraddr_in, doado_buf, dopadop_buf); + task_col_rd_ram_b (2'b01, weawel_int, webweu_int, addrbrdaddr_in, dobdo_buf, dopbdop_buf); + + task_col_wr_ram_a (2'b10, webweu_int, weawel_int, diadi_int, dipadip_int, addrbrdaddr_in, addrawraddr_in); + task_col_wr_ram_b (2'b10, weawel_int, webweu_int, dibdi_int, dipbdip_int, addrawraddr_in, addrbrdaddr_in); + + if (wr_mode_a != 2'b01) + task_col_rd_ram_a (2'b11, webweu_int, weawel_int, addrawraddr_in, doado_buf, dopadop_buf); + if (wr_mode_b != 2'b01) + task_col_rd_ram_b (2'b11, weawel_int, webweu_int, addrbrdaddr_in, dobdo_buf, dopbdop_buf); + + end // if (addrawraddr_in[13:col_addr_lsb] === addrbrdaddr_in[13:col_addr_lsb]) + else + viol_time = 0; + + end + else if (rising_clkawrclk && !rising_clkbrdclk) begin + if (col_addra_reconstruct[13:col_addr_lsb] === col_addrb_reconstruct_reg[13:col_addr_lsb]) begin + + viol_type = 2'b10; + + task_rd_ram_a (addrawraddr_in, doado_buf, dopadop_buf); + + task_col_wr_ram_a (2'b00, webweu_reg, weawel_int, di_x, di_x[7:0], addrbrdaddr_reg, addrawraddr_in); + task_col_wr_ram_b (2'b00, weawel_int, webweu_reg, di_x, di_x[7:0], addrawraddr_in, addrbrdaddr_reg); + + task_col_rd_ram_a (2'b01, webweu_reg, weawel_int, addrawraddr_in, doado_buf, dopadop_buf); + task_col_rd_ram_b (2'b01, weawel_int, webweu_reg, addrbrdaddr_reg, dobdo_buf, dopbdop_buf); + + task_col_wr_ram_a (2'b10, webweu_reg, weawel_int, diadi_int, dipadip_int, addrbrdaddr_reg, addrawraddr_in); + task_col_wr_ram_b (2'b10, weawel_int, webweu_reg, dibdi_reg, dipbdip_reg, addrawraddr_in, addrbrdaddr_reg); + + if (wr_mode_a != 2'b01) + task_col_rd_ram_a (2'b11, webweu_reg, weawel_int, addrawraddr_in, doado_buf, dopadop_buf); + if (wr_mode_b != 2'b01) + task_col_rd_ram_b (2'b11, weawel_int, webweu_reg, addrbrdaddr_reg, dobdo_buf, dopbdop_buf); + + if (wr_mode_a == 2'b01 || wr_mode_b == 2'b01) begin + task_col_wr_ram_a (2'b10, webweu_reg, weawel_int, di_x, di_x[7:0], addrbrdaddr_reg, addrawraddr_in); + task_col_wr_ram_b (2'b10, weawel_int, webweu_reg, di_x, di_x[7:0], addrawraddr_in, addrbrdaddr_reg); + end + + end // if (addrawraddr_in[13:col_addr_lsb] === addrbrdaddr_reg[13:col_addr_lsb]) + else + viol_time = 0; + + end + else if (!rising_clkawrclk && rising_clkbrdclk) begin + if (col_addra_reconstruct_reg[13:col_addr_lsb] === col_addrb_reconstruct[13:col_addr_lsb]) begin + + viol_type = 2'b11; + + task_rd_ram_b (addrbrdaddr_in, dobdo_buf, dopbdop_buf); + + task_col_wr_ram_a (2'b00, webweu_int, weawel_reg, di_x, di_x[7:0], addrbrdaddr_in, addrawraddr_reg); + task_col_wr_ram_b (2'b00, weawel_reg, webweu_int, di_x, di_x[7:0], addrawraddr_reg, addrbrdaddr_in); + + task_col_rd_ram_a (2'b01, webweu_int, weawel_reg, addrawraddr_reg, doado_buf, dopadop_buf); + task_col_rd_ram_b (2'b01, weawel_reg, webweu_int, addrbrdaddr_in, dobdo_buf, dopbdop_buf); + + task_col_wr_ram_a (2'b10, webweu_int, weawel_reg, diadi_reg, dipadip_reg, addrbrdaddr_in, addrawraddr_reg); + task_col_wr_ram_b (2'b10, weawel_reg, webweu_int, dibdi_int, dipbdip_int, addrawraddr_reg, addrbrdaddr_in); + + if (wr_mode_a != 2'b01) + task_col_rd_ram_a (2'b11, webweu_int, weawel_reg, addrawraddr_reg, doado_buf, dopadop_buf); + if (wr_mode_b != 2'b01) + task_col_rd_ram_b (2'b11, weawel_reg, webweu_int, addrbrdaddr_in, dobdo_buf, dopbdop_buf); + + if (wr_mode_a == 2'b01 || wr_mode_b == 2'b01) begin + task_col_wr_ram_a (2'b10, webweu_int, weawel_reg, di_x, di_x[7:0], addrbrdaddr_in, addrawraddr_reg); + task_col_wr_ram_b (2'b10, weawel_reg, webweu_int, di_x, di_x[7:0], addrawraddr_reg, addrbrdaddr_in); + end + + end // if (addrawraddr_reg[13:col_addr_lsb] === addrbrdaddr_in[13:col_addr_lsb]) + else + viol_time = 0; + + end + + end // if (viol_time != 0) + end // if (gsr_in === 1'b0) + + if (SIM_COLLISION_CHECK == "WARNING_ONLY") + viol_time = 0; + + end // if (SIM_COLLISION_CHECK != "NONE") + + +/*************************************** end collision ********************************/ + + + if (gsr_in == 1'b0) begin + +/**************************** Port A ****************************************/ + if (rising_clkawrclk) begin + + if ((enawren_in == 1'b1 && RST_PRIORITY_A == "CE") || RST_PRIORITY_A == "SR") begin + + if (rsta_in == 1'b1 && EN_RSTRAM_A == "TRUE") begin // sync reset + doado_buf = SRVAL_A[0 +: a_width]; + doado_out = SRVAL_A[0 +: a_width]; + + if (a_width >= 8) begin + dopadop_buf = SRVAL_A[a_width +: a_widthp]; + dopadop_out = SRVAL_A[a_width +: a_widthp]; + end + end + + + if (viol_time == 0) begin + + if (wr_mode_a == 2'b01 && (rsta_in === 1'b0 || EN_RSTRAM_A == "FALSE")) // read_first + task_rd_ram_a (addrawraddr_in, doado_buf, dopadop_buf); + + + if (enawren_in == 1'b1) + task_wr_ram_a (weawel_int, diadi_int, dipadip_int, addrawraddr_in); // write + + + if (wr_mode_a != 2'b01 && (rsta_in === 1'b0 || EN_RSTRAM_A == "FALSE")) // !read_first + task_rd_ram_a (addrawraddr_in, doado_buf, dopadop_buf); + + end // if (viol_time == 0) + + end // if ((enawren_in == 1'b1 && RST_PRIORITY_A == "CE") || RST_PRIORITY_A == "SR") + + end // if (rising_clkawrclk) + // end of port A + + +/************************************** port B ***************************************************************/ + if (rising_clkbrdclk) begin + + if ((enbrden_in == 1'b1 && RST_PRIORITY_B == "CE") || RST_PRIORITY_B == "SR") begin + if (rstbrst_in == 1'b1 && EN_RSTRAM_B == "TRUE") begin + + dobdo_buf = SRVAL_B[0 +: b_width]; + dobdo_out = SRVAL_B[0 +: b_width]; + + if (b_width >= 8) begin + dopbdop_buf = SRVAL_B[b_width +: b_widthp]; + dopbdop_out = SRVAL_B[b_width +: b_widthp]; + end + + end + + + if (viol_time == 0) begin + + if (wr_mode_b == 2'b01 && (rstbrst_in === 1'b0 || EN_RSTRAM_B == "FALSE")) // read_first + task_rd_ram_b (addrbrdaddr_in, dobdo_buf, dopbdop_buf); + + + if (enbrden_in == 1'b1) + task_wr_ram_b (webweu_int, dibdi_int, dipbdip_int, addrbrdaddr_in); // write + + + if (wr_mode_b != 2'b01 && (rstbrst_in === 1'b0 || EN_RSTRAM_B == "FALSE")) // !read_first + task_rd_ram_b (addrbrdaddr_in, dobdo_buf, dopbdop_buf); + + end // if (viol_time == 0) + + end // if ((enbrden_in == 1'b1 && RST_PRIORITY_B == "CE") || RST_PRIORITY_B == "SR") + + end // if (rising_clkbrdclk) + // end of port B + + + // writing outputs of port A + if (enawren_in && (rising_clkawrclk || viol_time != 0)) begin + + if ((rsta_in === 1'b0 || EN_RSTRAM_A == "FALSE") && (wr_mode_a != 2'b10 || (DATA_WIDTH_A <= 9 && weawel_int[0] === 1'b0) || (DATA_WIDTH_A == 18 && weawel_int[1:0] === 2'b00) || (DATA_WIDTH_A == 36 && weawel_int[3:0] === 4'b0000))) begin + + doado_out <= doado_buf; + + if (a_width >= 8) + dopadop_out <= dopadop_buf; + + end + + end + + + // writing outputs of port B + if (enbrden_in && (rising_clkbrdclk || viol_time != 0)) begin + + if ((rstbrst_in === 1'b0 || EN_RSTRAM_B == "FALSE") && (wr_mode_b != 2'b10 || (DATA_WIDTH_B <= 9 && webweu_int[0] === 1'b0) || (DATA_WIDTH_B == 18 && webweu_int[1:0] === 2'b00) || (DATA_WIDTH_B == 36 && webweu_int[3:0] === 4'b0000))) begin + + dobdo_out <= dobdo_buf; + + if (b_width >= 8) + dopbdop_out <= dopbdop_buf; + + end + + end + + end // if (gsr_in == 1'b0) + + + viol_time = 0; + rising_clkawrclk = 0; + rising_clkbrdclk = 0; + viol_type = 2'b00; + col_wr_wr_msg = 1; + col_wra_rdb_msg = 1; + col_wrb_rda_msg = 1; + + + end // always @ (posedge rising_clkawrclk or posedge rising_clkbrdclk) + + + // ***** Output Registers **** Port A ***** + always @(posedge clkawrclk_in or posedge gsr_in) begin + + if (DOA_REG == 1) begin + + if (gsr_in == 1'b1) begin + + doado_outreg <= INIT_A[0 +: a_width]; + + if (a_width >= 8) + dopadop_outreg <= INIT_A[a_width +: a_widthp]; + + end + else if (gsr_in == 1'b0) begin + + if (RST_PRIORITY_A == "CE") begin + + if (SIM_DEVICE == "SPARTAN6") begin + + if (regcea_in == 1'b1) begin + + if (rsta_in === 1'b1) begin + + doado_outreg <= SRVAL_A[0 +: a_width]; + + if (a_width >= 8) + dopadop_outreg <= SRVAL_A[a_width +: a_widthp]; + + end + else if (rsta_in === 1'b0) begin + + doado_outreg <= doado_out; + + if (a_width >= 8) + dopadop_outreg <= dopadop_out; + + end + + end // if (regcea_in == 1'b1) + + end // if (SIM_DEVICE == "SPARTAN6") + else if (SIM_DEVICE == "SPARTAN3ADSP") begin + + if (rsta_in === 1'b1 && enawren_in == 1'b1) begin + + doado_outreg <= SRVAL_A[0 +: a_width]; + + if (a_width >= 8) + dopadop_outreg <= SRVAL_A[a_width +: a_widthp]; + + end + else if (rsta_in === 1'b0 && regcea_in == 1'b1) begin + + doado_outreg <= doado_out; + + if (a_width >= 8) + dopadop_outreg <= dopadop_out; + + end + end // if (SIM_DEVICE == "SPARTAN3ADSP") + + end // if (RST_PRIORITY_A == "CE") + else begin + + if (rsta_in === 1'b1) begin + + doado_outreg <= SRVAL_A[0 +: a_width]; + + if (a_width >= 8) + dopadop_outreg <= SRVAL_A[a_width +: a_widthp]; + + end + else if (rsta_in === 1'b0) begin + + if (regcea_in == 1'b1) begin + + doado_outreg <= doado_out; + + if (a_width >= 8) + dopadop_outreg <= dopadop_out; + + end + + end + + end + + end // if (gsr_in == 1'b0) + + end // if (DOA_REG == 1) + + end // always @ (posedge clkawrclk_in or posedge gsr_in) + + + always @(doado_out or dopadop_out or doado_outreg or dopadop_outreg) begin + + case (DOA_REG) + + 0 : begin + doado_out_out[0 +: a_width] = doado_out[0 +: a_width]; + + if (a_width >= 8) + dopadop_out_out[0 +: a_widthp] = dopadop_out[0 +: a_widthp]; + + end + 1 : begin + doado_out_out[0 +: a_width] = doado_outreg[0 +: a_width]; + + if (a_width >= 8) + dopadop_out_out[0 +: a_widthp] = dopadop_outreg[0 +: a_widthp]; + + end + default : begin + $display("Attribute Syntax Error : The attribute DOA_REG on RAMB16BWER instance %m is set to %2d. Legal values for this attribute are 0 or 1.", DOA_REG); + $finish; + end + + endcase + + end // always @ (doado_out or dopadop_out or doado_outreg or dopadop_outreg) + + +// ***** Output Registers **** Port B ***** + always @(posedge clkbrdclk_in or posedge gsr_in) begin + + if (DOB_REG == 1) begin + + if (gsr_in == 1'b1) begin + + dobdo_outreg <= INIT_B[0 +: b_width]; + + if (b_width >= 8) + dopbdop_outreg <= INIT_B[b_width +: b_widthp]; + + end + else if (gsr_in == 1'b0) begin + + if (RST_PRIORITY_B == "CE") begin + + if (SIM_DEVICE == "SPARTAN6") begin + + if (regcebregce_in == 1'b1) begin + + if (rstbrst_in === 1'b1) begin + + dobdo_outreg <= SRVAL_B[0 +: b_width]; + + if (b_width >= 8) + dopbdop_outreg <= SRVAL_B[b_width +: b_widthp]; + + end + else if (rstbrst_in === 1'b0) begin + + dobdo_outreg <= dobdo_out; + + if (b_width >= 8) + dopbdop_outreg <= dopbdop_out; + + end + + end // if (regcebregce_in == 1'b1) + + end // if (SIM_DEVICE == "SPARTAN6") + else if (SIM_DEVICE == "SPARTAN3ADSP") begin + + if (rstbrst_in === 1'b1 && enbrden_in == 1'b1) begin + + dobdo_outreg <= SRVAL_B[0 +: b_width]; + + if (b_width >= 8) + dopbdop_outreg <= SRVAL_B[b_width +: b_widthp]; + + end + else if (rstbrst_in === 1'b0 && regcebregce_in == 1'b1) begin + + dobdo_outreg <= dobdo_out; + + if (b_width >= 8) + dopbdop_outreg <= dopbdop_out; + + end + end // if (SIM_DEVICE == "SPARTAN3ADSP") + + end // if (RST_PRIORITY_B == "CE") + else begin + + if (rstbrst_in === 1'b1) begin + + dobdo_outreg <= SRVAL_B[0 +: b_width]; + + if (b_width >= 8) + dopbdop_outreg <= SRVAL_B[b_width +: b_widthp]; + + end + else if (rstbrst_in === 1'b0) begin + + if (regcebregce_in == 1'b1) begin + + dobdo_outreg <= dobdo_out; + + if (b_width >= 8) + dopbdop_outreg <= dopbdop_out; + + end + + end + + end // else: !if(RST_PRIORITY_B == "CE") + + end // if (gsr_in == 1'b0) + + end // if (DOB_REG == 1) + + end // always @ (posedge clkbrdclk_in or posedge gsr_in) + + + always @(dobdo_out or dopbdop_out or dobdo_outreg or dopbdop_outreg) begin + + case (DOB_REG) + + 0 : begin + dobdo_out_out[0 +: b_width] = dobdo_out[0 +: b_width]; + + if (b_width >= 8) + dopbdop_out_out[0 +: b_widthp] = dopbdop_out[0 +: b_widthp]; + + end + 1 : begin + dobdo_out_out[0 +: b_width] = dobdo_outreg[0 +: b_width]; + + if (b_width >= 8) + dopbdop_out_out[0 +: b_widthp] = dopbdop_outreg[0 +: b_widthp]; + + end + default : begin + $display("Attribute Syntax Error : The attribute DOB_REG on RAMB16BWER instance %m is set to %2d. Legal values for this attribute are 0 or 1.", DOB_REG); + $finish; + end + + endcase + + end // always @ (dobdo_out or dopbdop_out or dobdo_outreg or dopbdop_outreg) + + +/******************************************** task and function **************************************/ + + task task_ram; + + input we; + input [7:0] di; + input dip; + inout [7:0] mem_task; + inout memp_task; + + begin + + if (we == 1'b1) begin + + mem_task = di; + + if (width >= 8) + memp_task = dip; + end + end + + endtask // task_ram + + + task task_ram_col; + + input we_o; + input we; + input [7:0] di; + input dip; + inout [7:0] mem_task; + inout memp_task; + integer i; + + begin + + if (we == 1'b1) begin + + for (i = 0; i < 8; i = i + 1) + if (mem_task[i] !== 1'bx || !(we === we_o && we === 1'b1)) + mem_task[i] = di[i]; + + if (width >= 8 && (memp_task !== 1'bx || !(we === we_o && we === 1'b1))) + memp_task = dip; + + end + end + + endtask // task_ram_col + + + task task_x_buf; + input [1:0] wr_rd_mode; + input integer do_uindex; + input integer do_lindex; + input integer dop_index; + input [63:0] do_ltmp; + inout [63:0] do_tmp; + input [7:0] dop_ltmp; + inout [7:0] dop_tmp; + integer i; + + begin + + if (wr_rd_mode == 2'b01) begin + for (i = do_lindex; i <= do_uindex; i = i + 1) begin + if (do_ltmp[i] === 1'bx) + do_tmp[i] = 1'bx; + end + + if (dop_ltmp[dop_index] === 1'bx) + dop_tmp[dop_index] = 1'bx; + + end // if (wr_rd_mode == 2'b01) + else begin + do_tmp[do_lindex +: 8] = do_ltmp[do_lindex +: 8]; + dop_tmp[dop_index] = dop_ltmp[dop_index]; + + end // else: !if(wr_rd_mode == 2'b01) + end + + endtask // task_x_buf + + + task task_col_wr_ram_a; + + input [1:0] seq; + input [7:0] webweu_tmp; + input [7:0] weawel_tmp; + input [63:0] diadi_tmp; + input [7:0] dipadip_tmp; + input [15:0] addrbrdaddr_tmp; + input [15:0] addrawraddr_tmp; + + begin + + case (a_width) + + 1, 2, 4 : begin + if (!(weawel_tmp[0] === 1'b1 && webweu_tmp[0] === 1'b1 && a_width > b_width) || seq == 2'b10) begin + if (a_width >= width) + task_ram_col (webweu_tmp[0], weawel_tmp[0], diadi_tmp[a_width-1:0], 1'b0, mem[addrawraddr_tmp[14:addrawraddr_lbit_124]], tmp1); + else + task_ram_col (webweu_tmp[0], weawel_tmp[0], diadi_tmp[a_width-1:0], 1'b0, mem[addrawraddr_tmp[14:addrawraddr_bit_124+1]][(addrawraddr_tmp[addrawraddr_bit_124:addrawraddr_lbit_124] * a_width) +: a_width], tmp1); + + if (seq == 2'b00) + chk_for_col_msg (weawel_tmp[0], webweu_tmp[0], addrawraddr_tmp, addrbrdaddr_tmp); + + end // if (!(weawel_tmp[0] === 1'b1 && webweu_tmp[0] === 1'b1 && a_width > b_width) || seq == 2'b10) + end // case: 1, 2, 4 + 8 : begin + if (!(weawel_tmp[0] === 1'b1 && webweu_tmp[0] === 1'b1 && a_width > b_width) || seq == 2'b10) begin + if (a_width >= width) + task_ram_col (webweu_tmp[0], weawel_tmp[0], diadi_tmp[7:0], dipadip_tmp[0], mem[addrawraddr_tmp[14:3]], memp[addrawraddr_tmp[14:3]]); + else + task_ram_col (webweu_tmp[0], weawel_tmp[0], diadi_tmp[7:0], dipadip_tmp[0], mem[addrawraddr_tmp[14:addrawraddr_bit_8+1]][(addrawraddr_tmp[addrawraddr_bit_8:3] * 8) +: 8], memp[addrawraddr_tmp[14:addrawraddr_bit_8+1]][(addrawraddr_tmp[addrawraddr_bit_8:3] * 1) +: 1]); + + if (seq == 2'b00) + chk_for_col_msg (weawel_tmp[0], webweu_tmp[0], addrawraddr_tmp, addrbrdaddr_tmp); + + end // if (a_width <= b_width) + end // case: 8 + 16 : begin + if (!(weawel_tmp[0] === 1'b1 && webweu_tmp[0] === 1'b1 && a_width > b_width) || seq == 2'b10) begin + if (a_width >= width) + task_ram_col (webweu_tmp[0], weawel_tmp[0], diadi_tmp[7:0], dipadip_tmp[0], mem[addrawraddr_tmp[14:4]][0 +: 8], memp[addrawraddr_tmp[14:4]][0]); + else + task_ram_col (webweu_tmp[0], weawel_tmp[0], diadi_tmp[7:0], dipadip_tmp[0], mem[addrawraddr_tmp[14:addrawraddr_bit_16+1]][(addrawraddr_tmp[addrawraddr_bit_16:4] * 16) +: 8], memp[addrawraddr_tmp[14:addrawraddr_bit_16+1]][(addrawraddr_tmp[addrawraddr_bit_16:4] * 2) +: 1]); + + if (seq == 2'b00) + chk_for_col_msg (weawel_tmp[0], webweu_tmp[0], addrawraddr_tmp, addrbrdaddr_tmp); + + if (a_width >= width) + task_ram_col (webweu_tmp[1], weawel_tmp[1], diadi_tmp[15:8], dipadip_tmp[1], mem[addrawraddr_tmp[14:4]][8 +: 8], memp[addrawraddr_tmp[14:4]][1]); + else + task_ram_col (webweu_tmp[1], weawel_tmp[1], diadi_tmp[15:8], dipadip_tmp[1], mem[addrawraddr_tmp[14:addrawraddr_bit_16+1]][((addrawraddr_tmp[addrawraddr_bit_16:4] * 16) + 8) +: 8], memp[addrawraddr_tmp[14:addrawraddr_bit_16+1]][((addrawraddr_tmp[addrawraddr_bit_16:4] * 2) + 1) +: 1]); + + if (seq == 2'b00) + chk_for_col_msg (weawel_tmp[1], webweu_tmp[1], addrawraddr_tmp, addrbrdaddr_tmp); + + end // if (a_width <= b_width) + end // case: 16 + 32 : begin + if (!(weawel_tmp[0] === 1'b1 && webweu_tmp[0] === 1'b1 && a_width > b_width) || seq == 2'b10) begin + task_ram_col (webweu_tmp[0], weawel_tmp[0], diadi_tmp[7:0], dipadip_tmp[0], mem[addrawraddr_tmp[14:5]][0 +: 8], memp[addrawraddr_tmp[14:5]][0]); + if (seq == 2'b00) + chk_for_col_msg (weawel_tmp[0], webweu_tmp[0], addrawraddr_tmp, addrbrdaddr_tmp); + + task_ram_col (webweu_tmp[1], weawel_tmp[1], diadi_tmp[15:8], dipadip_tmp[1], mem[addrawraddr_tmp[14:5]][8 +: 8], memp[addrawraddr_tmp[14:5]][1]); + if (seq == 2'b00) + chk_for_col_msg (weawel_tmp[1], webweu_tmp[1], addrawraddr_tmp, addrbrdaddr_tmp); + + task_ram_col (webweu_tmp[2], weawel_tmp[2], diadi_tmp[23:16], dipadip_tmp[2], mem[addrawraddr_tmp[14:5]][16 +: 8], memp[addrawraddr_tmp[14:5]][2]); + if (seq == 2'b00) + chk_for_col_msg (weawel_tmp[2], webweu_tmp[2], addrawraddr_tmp, addrbrdaddr_tmp); + + task_ram_col (webweu_tmp[3], weawel_tmp[3], diadi_tmp[31:24], dipadip_tmp[3], mem[addrawraddr_tmp[14:5]][24 +: 8], memp[addrawraddr_tmp[14:5]][3]); + if (seq == 2'b00) + chk_for_col_msg (weawel_tmp[3], webweu_tmp[3], addrawraddr_tmp, addrbrdaddr_tmp); + + end // if (a_width <= b_width) + end // case: 32 + + endcase // case(a_width) + + end + + endtask // task_col_wr_ram_a + + + task task_col_wr_ram_b; + + input [1:0] seq; + input [7:0] weawel_tmp; + input [7:0] webweu_tmp; + input [63:0] dibdi_tmp; + input [7:0] dipbdip_tmp; + input [15:0] addrawraddr_tmp; + input [15:0] addrbrdaddr_tmp; + + begin + + case (b_width) + + 1, 2, 4 : begin + if (!(weawel_tmp[0] === 1'b1 && webweu_tmp[0] === 1'b1 && b_width > a_width) || seq == 2'b10) begin + if (b_width >= width) + task_ram_col (weawel_tmp[0], webweu_tmp[0], dibdi_tmp[b_width-1:0], 1'b0, mem[addrbrdaddr_tmp[14:addrbrdaddr_lbit_124]], tmp1); + else + task_ram_col (weawel_tmp[0], webweu_tmp[0], dibdi_tmp[b_width-1:0], 1'b0, mem[addrbrdaddr_tmp[14:addrbrdaddr_bit_124+1]][(addrbrdaddr_tmp[addrbrdaddr_bit_124:addrbrdaddr_lbit_124] * b_width) +: b_width], tmp1); + + if (seq == 2'b00) + chk_for_col_msg (weawel_tmp[0], webweu_tmp[0], addrawraddr_tmp, addrbrdaddr_tmp); + + end // if (b_width <= a_width) + end // case: 1, 2, 4 + 8 : begin + if (!(weawel_tmp[0] === 1'b1 && webweu_tmp[0] === 1'b1 && b_width > a_width) || seq == 2'b10) begin + if (b_width >= width) + task_ram_col (weawel_tmp[0], webweu_tmp[0], dibdi_tmp[7:0], dipbdip_tmp[0], mem[addrbrdaddr_tmp[14:3]], memp[addrbrdaddr_tmp[14:3]]); + else + task_ram_col (weawel_tmp[0], webweu_tmp[0], dibdi_tmp[7:0], dipbdip_tmp[0], mem[addrbrdaddr_tmp[14:addrbrdaddr_bit_8+1]][(addrbrdaddr_tmp[addrbrdaddr_bit_8:3] * 8) +: 8], memp[addrbrdaddr_tmp[14:addrbrdaddr_bit_8+1]][(addrbrdaddr_tmp[addrbrdaddr_bit_8:3] * 1) +: 1]); + + if (seq == 2'b00) + chk_for_col_msg (weawel_tmp[0], webweu_tmp[0], addrawraddr_tmp, addrbrdaddr_tmp); + + end // if (b_width <= a_width) + end // case: 8 + 16 : begin + if (!(weawel_tmp[0] === 1'b1 && webweu_tmp[0] === 1'b1 && b_width > a_width) || seq == 2'b10) begin + if (b_width >= width) + task_ram_col (weawel_tmp[0], webweu_tmp[0], dibdi_tmp[7:0], dipbdip_tmp[0], mem[addrbrdaddr_tmp[14:4]][0 +: 8], memp[addrbrdaddr_tmp[14:4]][0:0]); + else + task_ram_col (weawel_tmp[0], webweu_tmp[0], dibdi_tmp[7:0], dipbdip_tmp[0], mem[addrbrdaddr_tmp[14:addrbrdaddr_bit_16+1]][(addrbrdaddr_tmp[addrbrdaddr_bit_16:4] * 16) +: 8], memp[addrbrdaddr_tmp[14:addrbrdaddr_bit_16+1]][(addrbrdaddr_tmp[addrbrdaddr_bit_16:4] * 2) +: 1]); + + if (seq == 2'b00) + chk_for_col_msg (weawel_tmp[0], webweu_tmp[0], addrawraddr_tmp, addrbrdaddr_tmp); + + + if (b_width >= width) + task_ram_col (weawel_tmp[1], webweu_tmp[1], dibdi_tmp[15:8], dipbdip_tmp[1], mem[addrbrdaddr_tmp[14:4]][8 +: 8], memp[addrbrdaddr_tmp[14:4]][1:1]); + else + task_ram_col (weawel_tmp[1], webweu_tmp[1], dibdi_tmp[15:8], dipbdip_tmp[1], mem[addrbrdaddr_tmp[14:addrbrdaddr_bit_16+1]][((addrbrdaddr_tmp[addrbrdaddr_bit_16:4] * 16) + 8) +: 8], memp[addrbrdaddr_tmp[14:addrbrdaddr_bit_16+1]][((addrbrdaddr_tmp[addrbrdaddr_bit_16:4] * 2) + 1) +: 1]); + + if (seq == 2'b00) + chk_for_col_msg (weawel_tmp[1], webweu_tmp[1], addrawraddr_tmp, addrbrdaddr_tmp); + + end // if (!(weawel_tmp[0] === 1'b1 && webweu_tmp[0] === 1'b1 && b_width > a_width) || seq == 2'b10) + end // case: 16 + 32 : begin + if (!(weawel_tmp[0] === 1'b1 && webweu_tmp[0] === 1'b1 && b_width > a_width) || seq == 2'b10) begin + task_ram_col (weawel_tmp[0], webweu_tmp[0], dibdi_tmp[7:0], dipbdip_tmp[0], mem[addrbrdaddr_tmp[14:5]][0 +: 8], memp[addrbrdaddr_tmp[14:5]][0:0]); + if (seq == 2'b00) + chk_for_col_msg (weawel_tmp[0], webweu_tmp[0], addrawraddr_tmp, addrbrdaddr_tmp); + + task_ram_col (weawel_tmp[1], webweu_tmp[1], dibdi_tmp[15:8], dipbdip_tmp[1], mem[addrbrdaddr_tmp[14:5]][8 +: 8], memp[addrbrdaddr_tmp[14:5]][1:1]); + if (seq == 2'b00) + chk_for_col_msg (weawel_tmp[1], webweu_tmp[1], addrawraddr_tmp, addrbrdaddr_tmp); + + task_ram_col (weawel_tmp[2], webweu_tmp[2], dibdi_tmp[23:16], dipbdip_tmp[2], mem[addrbrdaddr_tmp[14:5]][16 +: 8], memp[addrbrdaddr_tmp[14:5]][2:2]); + if (seq == 2'b00) + chk_for_col_msg (weawel_tmp[2], webweu_tmp[2], addrawraddr_tmp, addrbrdaddr_tmp); + + task_ram_col (weawel_tmp[3], webweu_tmp[3], dibdi_tmp[31:24], dipbdip_tmp[3], mem[addrbrdaddr_tmp[14:5]][24 +: 8], memp[addrbrdaddr_tmp[14:5]][3:3]); + if (seq == 2'b00) + chk_for_col_msg (weawel_tmp[3], webweu_tmp[3], addrawraddr_tmp, addrbrdaddr_tmp); + + end // if (b_width <= a_width) + end // case: 32 + + endcase // case(b_width) + + end + + endtask // task_col_wr_ram_b + + + task task_wr_ram_a; + + input [7:0] weawel_tmp; + input [63:0] diadi_tmp; + input [7:0] dipadip_tmp; + input [15:0] addrawraddr_tmp; + + begin + + case (a_width) + + 1, 2, 4 : begin + + if (a_width >= width) + task_ram (weawel_tmp[0], diadi_tmp[a_width-1:0], 1'b0, mem[addrawraddr_tmp[14:addrawraddr_lbit_124]], tmp1); + else + task_ram (weawel_tmp[0], diadi_tmp[a_width-1:0], 1'b0, mem[addrawraddr_tmp[14:addrawraddr_bit_124+1]][(addrawraddr_tmp[addrawraddr_bit_124:addrawraddr_lbit_124] * a_width) +: a_width], tmp1); + + end + 8 : begin + + if (a_width >= width) + task_ram (weawel_tmp[0], diadi_tmp[7:0], dipadip_tmp[0], mem[addrawraddr_tmp[14:3]], memp[addrawraddr_tmp[14:3]]); + else + task_ram (weawel_tmp[0], diadi_tmp[7:0], dipadip_tmp[0], mem[addrawraddr_tmp[14:addrawraddr_bit_8+1]][(addrawraddr_tmp[addrawraddr_bit_8:3] * 8) +: 8], memp[addrawraddr_tmp[14:addrawraddr_bit_8+1]][(addrawraddr_tmp[addrawraddr_bit_8:3] * 1) +: 1]); + + end + 16 : begin + + if (a_width >= width) begin + task_ram (weawel_tmp[0], diadi_tmp[7:0], dipadip_tmp[0], mem[addrawraddr_tmp[14:4]][0 +: 8], memp[addrawraddr_tmp[14:4]][0:0]); + task_ram (weawel_tmp[1], diadi_tmp[15:8], dipadip_tmp[1], mem[addrawraddr_tmp[14:4]][8 +: 8], memp[addrawraddr_tmp[14:4]][1:1]); + end + else begin + task_ram (weawel_tmp[0], diadi_tmp[7:0], dipadip_tmp[0], mem[addrawraddr_tmp[14:addrawraddr_bit_16+1]][(addrawraddr_tmp[addrawraddr_bit_16:4] * 16) +: 8], memp[addrawraddr_tmp[14:addrawraddr_bit_16+1]][(addrawraddr_tmp[addrawraddr_bit_16:4] * 2) +: 1]); + task_ram (weawel_tmp[1], diadi_tmp[15:8], dipadip_tmp[1], mem[addrawraddr_tmp[14:addrawraddr_bit_16+1]][((addrawraddr_tmp[addrawraddr_bit_16:4] * 16) + 8) +: 8], memp[addrawraddr_tmp[14:addrawraddr_bit_16+1]][((addrawraddr_tmp[addrawraddr_bit_16:4] * 2) + 1) +: 1]); + end // else: !if(a_width >= b_width) + + end // case: 16 + 32 : begin + + task_ram (weawel_tmp[0], diadi_tmp[7:0], dipadip_tmp[0], mem[addrawraddr_tmp[14:5]][0 +: 8], memp[addrawraddr_tmp[14:5]][0:0]); + task_ram (weawel_tmp[1], diadi_tmp[15:8], dipadip_tmp[1], mem[addrawraddr_tmp[14:5]][8 +: 8], memp[addrawraddr_tmp[14:5]][1:1]); + task_ram (weawel_tmp[2], diadi_tmp[23:16], dipadip_tmp[2], mem[addrawraddr_tmp[14:5]][16 +: 8], memp[addrawraddr_tmp[14:5]][2:2]); + task_ram (weawel_tmp[3], diadi_tmp[31:24], dipadip_tmp[3], mem[addrawraddr_tmp[14:5]][24 +: 8], memp[addrawraddr_tmp[14:5]][3:3]); + + end // case: 32 + endcase // case(a_width) + end + + endtask // task_wr_ram_a + + + task task_wr_ram_b; + + input [7:0] webweu_tmp; + input [63:0] dibdi_tmp; + input [7:0] dipbdip_tmp; + input [15:0] addrbrdaddr_tmp; + + begin + + case (b_width) + + 1, 2, 4 : begin + + if (b_width >= width) + task_ram (webweu_tmp[0], dibdi_tmp[b_width-1:0], 1'b0, mem[addrbrdaddr_tmp[14:addrbrdaddr_lbit_124]], tmp1); + else + task_ram (webweu_tmp[0], dibdi_tmp[b_width-1:0], 1'b0, mem[addrbrdaddr_tmp[14:addrbrdaddr_bit_124+1]][(addrbrdaddr_tmp[addrbrdaddr_bit_124:addrbrdaddr_lbit_124] * b_width) +: b_width], tmp1); + end + 8 : begin + + if (b_width >= width) + task_ram (webweu_tmp[0], dibdi_tmp[7:0], dipbdip_tmp[0], mem[addrbrdaddr_tmp[14:3]], memp[addrbrdaddr_tmp[14:3]]); + else + task_ram (webweu_tmp[0], dibdi_tmp[7:0], dipbdip_tmp[0], mem[addrbrdaddr_tmp[14:addrbrdaddr_bit_8+1]][(addrbrdaddr_tmp[addrbrdaddr_bit_8:3] * 8) +: 8], memp[addrbrdaddr_tmp[14:addrbrdaddr_bit_8+1]][(addrbrdaddr_tmp[addrbrdaddr_bit_8:3] * 1) +: 1]); + + end + 16 : begin + + if (b_width >= width) begin + task_ram (webweu_tmp[0], dibdi_tmp[7:0], dipbdip_tmp[0], mem[addrbrdaddr_tmp[14:4]][0 +: 8], memp[addrbrdaddr_tmp[14:4]][0:0]); + task_ram (webweu_tmp[1], dibdi_tmp[15:8], dipbdip_tmp[1], mem[addrbrdaddr_tmp[14:4]][8 +: 8], memp[addrbrdaddr_tmp[14:4]][1:1]); + end + else begin + task_ram (webweu_tmp[0], dibdi_tmp[7:0], dipbdip_tmp[0], mem[addrbrdaddr_tmp[14:addrbrdaddr_bit_16+1]][(addrbrdaddr_tmp[addrbrdaddr_bit_16:4] * 16) +: 8], memp[addrbrdaddr_tmp[14:addrbrdaddr_bit_16+1]][(addrbrdaddr_tmp[addrbrdaddr_bit_16:4] * 2) +: 1]); + task_ram (webweu_tmp[1], dibdi_tmp[15:8], dipbdip_tmp[1], mem[addrbrdaddr_tmp[14:addrbrdaddr_bit_16+1]][((addrbrdaddr_tmp[addrbrdaddr_bit_16:4] * 16) + 8) +: 8], memp[addrbrdaddr_tmp[14:addrbrdaddr_bit_16+1]][((addrbrdaddr_tmp[addrbrdaddr_bit_16:4] * 2) + 1) +: 1]); + end + + end // case: 16 + 32 : begin + + task_ram (webweu_tmp[0], dibdi_tmp[7:0], dipbdip_tmp[0], mem[addrbrdaddr_tmp[14:5]][0 +: 8], memp[addrbrdaddr_tmp[14:5]][0:0]); + task_ram (webweu_tmp[1], dibdi_tmp[15:8], dipbdip_tmp[1], mem[addrbrdaddr_tmp[14:5]][8 +: 8], memp[addrbrdaddr_tmp[14:5]][1:1]); + task_ram (webweu_tmp[2], dibdi_tmp[23:16], dipbdip_tmp[2], mem[addrbrdaddr_tmp[14:5]][16 +: 8], memp[addrbrdaddr_tmp[14:5]][2:2]); + task_ram (webweu_tmp[3], dibdi_tmp[31:24], dipbdip_tmp[3], mem[addrbrdaddr_tmp[14:5]][24 +: 8], memp[addrbrdaddr_tmp[14:5]][3:3]); + + end // case: 32 + endcase // case(b_width) + end + + endtask // task_wr_ram_b + + + task task_col_rd_ram_a; + + input [1:0] seq; // 1 is bypass + input [7:0] webweu_tmp; + input [7:0] weawel_tmp; + input [15:0] addrawraddr_tmp; + inout [63:0] doado_tmp; + inout [7:0] dopadop_tmp; + reg [63:0] doado_ltmp; + reg [7:0] dopadop_ltmp; + + begin + + doado_ltmp= 64'b0; + dopadop_ltmp= 8'b0; + + case (a_width) + 1, 2, 4 : begin + + if ((webweu_tmp[0] === 1'b1 && weawel_tmp[0] === 1'b1) || (seq == 2'b01 && webweu_tmp[0] === 1'b1 && weawel_tmp[0] === 1'b0 && viol_type == 2'b10) || (seq == 2'b01 && wr_mode_a != 2'b01 && wr_mode_b != 2'b01) || (seq == 2'b01 && wr_mode_a == 2'b01 && wr_mode_b != 2'b01 && webweu_tmp[0] === 1'b1) || (seq == 2'b11 && wr_mode_a == 2'b00 && webweu_tmp[0] !== 1'b1)) begin + if (a_width >= width) + doado_ltmp = mem[addrawraddr_tmp[14:addrawraddr_lbit_124]]; + else + doado_ltmp = mem[addrawraddr_tmp[14:addrawraddr_bit_124+1]][(addrawraddr_tmp[addrawraddr_bit_124:addrawraddr_lbit_124] * a_width) +: a_width]; + task_x_buf (wr_mode_a, 3, 0, 0, doado_ltmp, doado_tmp, dopadop_ltmp, dopadop_tmp); + end + end // case: 1, 2, 4 + 8 : begin + + if ((webweu_tmp[0] === 1'b1 && weawel_tmp[0] === 1'b1) || (seq == 2'b01 && webweu_tmp[0] === 1'b1 && weawel_tmp[0] === 1'b0 && viol_type == 2'b10) || (seq == 2'b01 && wr_mode_a != 2'b01 && wr_mode_b != 2'b01) || (seq == 2'b01 && wr_mode_a == 2'b01 && wr_mode_b != 2'b01 && webweu_tmp[0] === 1'b1) || (seq == 2'b11 && wr_mode_a == 2'b00 && webweu_tmp[0] !== 1'b1)) begin + if (a_width >= width) begin + doado_ltmp = mem[addrawraddr_tmp[14:3]]; + dopadop_ltmp = memp[addrawraddr_tmp[14:3]]; + end + else begin + doado_ltmp = mem[addrawraddr_tmp[14:addrawraddr_bit_8+1]][(addrawraddr_tmp[addrawraddr_bit_8:3] * 8) +: 8]; + dopadop_ltmp = memp[addrawraddr_tmp[14:addrawraddr_bit_8+1]][(addrawraddr_tmp[addrawraddr_bit_8:3] * 1) +: 1]; + end + + task_x_buf (wr_mode_a, 7, 0, 0, doado_ltmp, doado_tmp, dopadop_ltmp, dopadop_tmp); + + end + end // case: 8 + 16 : begin + + if ((webweu_tmp[0] === 1'b1 && weawel_tmp[0] === 1'b1) || (seq == 2'b01 && webweu_tmp[0] === 1'b1 && weawel_tmp[0] === 1'b0 && viol_type == 2'b10) || (seq == 2'b01 && wr_mode_a != 2'b01 && wr_mode_b != 2'b01) || (seq == 2'b01 && wr_mode_a == 2'b01 && wr_mode_b != 2'b01 && webweu_tmp[0] === 1'b1) || (seq == 2'b11 && wr_mode_a == 2'b00 && webweu_tmp[0] !== 1'b1)) begin + if (a_width >= width) begin + doado_ltmp[7:0] = mem[addrawraddr_tmp[14:4]][7:0]; + dopadop_ltmp[0:0] = memp[addrawraddr_tmp[14:4]][0:0]; + end + else begin + doado_ltmp[7:0] = mem[addrawraddr_tmp[14:addrawraddr_bit_16+1]][(addrawraddr_tmp[addrawraddr_bit_16:4] * 16) +: 8]; + dopadop_ltmp[0:0] = memp[addrawraddr_tmp[14:addrawraddr_bit_16+1]][(addrawraddr_tmp[addrawraddr_bit_16:4] * 2) +: 1]; + end + task_x_buf (wr_mode_a, 7, 0, 0, doado_ltmp, doado_tmp, dopadop_ltmp, dopadop_tmp); + end + + if ((webweu_tmp[1] === 1'b1 && weawel_tmp[1] === 1'b1) || (seq == 2'b01 && webweu_tmp[1] === 1'b1 && weawel_tmp[1] === 1'b0 && viol_type == 2'b10) || (seq == 2'b01 && wr_mode_a != 2'b01 && wr_mode_b != 2'b01) || (seq == 2'b01 && wr_mode_a == 2'b01 && wr_mode_b != 2'b01 && webweu_tmp[1] === 1'b1) || (seq == 2'b11 && wr_mode_a == 2'b00 && webweu_tmp[1] !== 1'b1)) begin + if (a_width >= width) begin + doado_ltmp[15:8] = mem[addrawraddr_tmp[14:4]][15:8]; + dopadop_ltmp[1:1] = memp[addrawraddr_tmp[14:4]][1:1]; + end + else begin + doado_ltmp[15:8] = mem[addrawraddr_tmp[14:addrawraddr_bit_16+1]][((addrawraddr_tmp[addrawraddr_bit_16:4] * 16) + 8) +: 8]; + dopadop_ltmp[1:1] = memp[addrawraddr_tmp[14:addrawraddr_bit_16+1]][((addrawraddr_tmp[addrawraddr_bit_16:4] * 2) + 1) +: 1]; + end + task_x_buf (wr_mode_a, 15, 8, 1, doado_ltmp, doado_tmp, dopadop_ltmp, dopadop_tmp); + end + + end + 32 : begin + if (a_width >= width) begin + + if ((webweu_tmp[0] === 1'b1 && weawel_tmp[0] === 1'b1) || (seq == 2'b01 && webweu_tmp[0] === 1'b1 && weawel_tmp[0] === 1'b0 && viol_type == 2'b10) || (seq == 2'b01 && wr_mode_a != 2'b01 && wr_mode_b != 2'b01) || (seq == 2'b01 && wr_mode_a == 2'b01 && wr_mode_b != 2'b01 && webweu_tmp[0] === 1'b1) || (seq == 2'b11 && wr_mode_a == 2'b00 && webweu_tmp[0] !== 1'b1)) begin + doado_ltmp[7:0] = mem[addrawraddr_tmp[14:5]][7:0]; + dopadop_ltmp[0:0] = memp[addrawraddr_tmp[14:5]][0:0]; + task_x_buf (wr_mode_a, 7, 0, 0, doado_ltmp, doado_tmp, dopadop_ltmp, dopadop_tmp); + end + + if ((webweu_tmp[1] === 1'b1 && weawel_tmp[1] === 1'b1) || (seq == 2'b01 && webweu_tmp[1] === 1'b1 && weawel_tmp[1] === 1'b0 && viol_type == 2'b10) || (seq == 2'b01 && wr_mode_a != 2'b01 && wr_mode_b != 2'b01) || (seq == 2'b01 && wr_mode_a == 2'b01 && wr_mode_b != 2'b01 && webweu_tmp[1] === 1'b1) || (seq == 2'b11 && wr_mode_a == 2'b00 && webweu_tmp[1] !== 1'b1)) begin + doado_ltmp[15:8] = mem[addrawraddr_tmp[14:5]][15:8]; + dopadop_ltmp[1:1] = memp[addrawraddr_tmp[14:5]][1:1]; + task_x_buf (wr_mode_a, 15, 8, 1, doado_ltmp, doado_tmp, dopadop_ltmp, dopadop_tmp); + end + + if ((webweu_tmp[2] === 1'b1 && weawel_tmp[2] === 1'b1) || (seq == 2'b01 && webweu_tmp[2] === 1'b1 && weawel_tmp[2] === 1'b0 && viol_type == 2'b10) || (seq == 2'b01 && wr_mode_a != 2'b01 && wr_mode_b != 2'b01) || (seq == 2'b01 && wr_mode_a == 2'b01 && wr_mode_b != 2'b01 && webweu_tmp[2] === 1'b1) || (seq == 2'b11 && wr_mode_a == 2'b00 && webweu_tmp[2] !== 1'b1)) begin + doado_ltmp[23:16] = mem[addrawraddr_tmp[14:5]][23:16]; + dopadop_ltmp[2:2] = memp[addrawraddr_tmp[14:5]][2:2]; + task_x_buf (wr_mode_a, 23, 16, 2, doado_ltmp, doado_tmp, dopadop_ltmp, dopadop_tmp); + end + + if ((webweu_tmp[3] === 1'b1 && weawel_tmp[3] === 1'b1) || (seq == 2'b01 && webweu_tmp[3] === 1'b1 && weawel_tmp[3] === 1'b0 && viol_type == 2'b10) || (seq == 2'b01 && wr_mode_a != 2'b01 && wr_mode_b != 2'b01) || (seq == 2'b01 && wr_mode_a == 2'b01 && wr_mode_b != 2'b01 && webweu_tmp[3] === 1'b1) || (seq == 2'b11 && wr_mode_a == 2'b00 && webweu_tmp[3] !== 1'b1)) begin + doado_ltmp[31:24] = mem[addrawraddr_tmp[14:5]][31:24]; + dopadop_ltmp[3:3] = memp[addrawraddr_tmp[14:5]][3:3]; + task_x_buf (wr_mode_a, 31, 24, 3, doado_ltmp, doado_tmp, dopadop_ltmp, dopadop_tmp); + end + + end // if (a_width >= width) + end + + endcase // case(a_width) + end + endtask // task_col_rd_ram_a + + + task task_col_rd_ram_b; + + input [1:0] seq; // 1 is bypass + input [7:0] weawel_tmp; + input [7:0] webweu_tmp; + input [15:0] addrbrdaddr_tmp; + inout [63:0] dobdo_tmp; + inout [7:0] dopbdop_tmp; + reg [63:0] dobdo_ltmp; + reg [7:0] dopbdop_ltmp; + + begin + + dobdo_ltmp= 64'b0; + dopbdop_ltmp= 8'b0; + + case (b_width) + 1, 2, 4 : begin + + if ((webweu_tmp[0] === 1'b1 && weawel_tmp[0] === 1'b1) || (seq == 2'b01 && weawel_tmp[0] === 1'b1 && webweu_tmp[0] === 1'b0 && viol_type == 2'b11) || (seq == 2'b01 && wr_mode_b != 2'b01 && wr_mode_a != 2'b01) || (seq == 2'b01 && wr_mode_b == 2'b01 && wr_mode_a != 2'b01 && weawel_tmp[0] === 1'b1) || (seq == 2'b11 && wr_mode_b == 2'b00 && weawel_tmp[0] !== 1'b1)) begin + if (b_width >= width) + dobdo_ltmp = mem[addrbrdaddr_tmp[14:addrbrdaddr_lbit_124]]; + else + dobdo_ltmp = mem[addrbrdaddr_tmp[14:addrbrdaddr_bit_124+1]][(addrbrdaddr_tmp[addrbrdaddr_bit_124:addrbrdaddr_lbit_124] * b_width) +: b_width]; + + task_x_buf (wr_mode_b, 3, 0, 0, dobdo_ltmp, dobdo_tmp, dopbdop_ltmp, dopbdop_tmp); + + end + end // case: 1, 2, 4 + 8 : begin + + if ((webweu_tmp[0] === 1'b1 && weawel_tmp[0] === 1'b1) || (seq == 2'b01 && weawel_tmp[0] === 1'b1 && webweu_tmp[0] === 1'b0 && viol_type == 2'b11) || (seq == 2'b01 && wr_mode_b != 2'b01 && wr_mode_a != 2'b01) || (seq == 2'b01 && wr_mode_b == 2'b01 && wr_mode_a != 2'b01 && weawel_tmp[0] === 1'b1) || (seq == 2'b11 && wr_mode_b == 2'b00 && weawel_tmp[0] !== 1'b1)) begin + + if (b_width >= width) begin + dobdo_ltmp = mem[addrbrdaddr_tmp[14:3]]; + dopbdop_ltmp = memp[addrbrdaddr_tmp[14:3]]; + end + else begin + dobdo_ltmp = mem[addrbrdaddr_tmp[14:addrbrdaddr_bit_8+1]][(addrbrdaddr_tmp[addrbrdaddr_bit_8:3] * 8) +: 8]; + dopbdop_ltmp = memp[addrbrdaddr_tmp[14:addrbrdaddr_bit_8+1]][(addrbrdaddr_tmp[addrbrdaddr_bit_8:3] * 1) +: 1]; + end + + task_x_buf (wr_mode_b, 7, 0, 0, dobdo_ltmp, dobdo_tmp, dopbdop_ltmp, dopbdop_tmp); + + end + end // case: 8 + 16 : begin + + if ((webweu_tmp[0] === 1'b1 && weawel_tmp[0] === 1'b1) || (seq == 2'b01 && weawel_tmp[0] === 1'b1 && webweu_tmp[0] === 1'b0 && viol_type == 2'b11) || (seq == 2'b01 && wr_mode_b != 2'b01 && wr_mode_a != 2'b01) || (seq == 2'b01 && wr_mode_b == 2'b01 && wr_mode_a != 2'b01 && weawel_tmp[0] === 1'b1) || (seq == 2'b11 && wr_mode_b == 2'b00 && weawel_tmp[0] !== 1'b1)) begin + if (b_width >= width) begin + dobdo_ltmp[7:0] = mem[addrbrdaddr_tmp[14:4]][7:0]; + dopbdop_ltmp[0:0] = memp[addrbrdaddr_tmp[14:4]][0:0]; + end + else begin + dobdo_ltmp[7:0] = mem[addrbrdaddr_tmp[14:addrbrdaddr_bit_16+1]][(addrbrdaddr_tmp[addrbrdaddr_bit_16:4] * 16) +: 8]; + dopbdop_ltmp[0:0] = memp[addrbrdaddr_tmp[14:addrbrdaddr_bit_16+1]][(addrbrdaddr_tmp[addrbrdaddr_bit_16:4] * 2) +: 1]; + end + task_x_buf (wr_mode_b, 7, 0, 0, dobdo_ltmp, dobdo_tmp, dopbdop_ltmp, dopbdop_tmp); + end + + + if ((webweu_tmp[1] === 1'b1 && weawel_tmp[1] === 1'b1) || (seq == 2'b01 && weawel_tmp[1] === 1'b1 && webweu_tmp[1] === 1'b0 && viol_type == 2'b11) || (seq == 2'b01 && wr_mode_b != 2'b01 && wr_mode_a != 2'b01) || (seq == 2'b01 && wr_mode_b == 2'b01 && wr_mode_a != 2'b01 && weawel_tmp[1] === 1'b1) || (seq == 2'b11 && wr_mode_b == 2'b00 && weawel_tmp[1] !== 1'b1)) begin + + if (b_width >= width) begin + dobdo_ltmp[15:8] = mem[addrbrdaddr_tmp[14:4]][15:8]; + dopbdop_ltmp[1:1] = memp[addrbrdaddr_tmp[14:4]][1:1]; + end + else begin + dobdo_ltmp[15:8] = mem[addrbrdaddr_tmp[14:addrbrdaddr_bit_16+1]][((addrbrdaddr_tmp[addrbrdaddr_bit_16:4] * 16) + 8) +: 8]; + dopbdop_ltmp[1:1] = memp[addrbrdaddr_tmp[14:addrbrdaddr_bit_16+1]][((addrbrdaddr_tmp[addrbrdaddr_bit_16:4] * 2) + 1) +: 1]; + end + task_x_buf (wr_mode_b, 15, 8, 1, dobdo_ltmp, dobdo_tmp, dopbdop_ltmp, dopbdop_tmp); + end + + end + 32 : begin + if (b_width >= width) begin + + if ((webweu_tmp[0] === 1'b1 && weawel_tmp[0] === 1'b1) || (seq == 2'b01 && weawel_tmp[0] === 1'b1 && webweu_tmp[0] === 1'b0 && viol_type == 2'b11) || (seq == 2'b01 && wr_mode_b != 2'b01 && wr_mode_a != 2'b01) || (seq == 2'b01 && wr_mode_b == 2'b01 && wr_mode_a != 2'b01 && weawel_tmp[0] === 1'b1) || (seq == 2'b11 && wr_mode_b == 2'b00 && weawel_tmp[0] !== 1'b1)) begin + dobdo_ltmp[7:0] = mem[addrbrdaddr_tmp[14:5]][7:0]; + dopbdop_ltmp[0:0] = memp[addrbrdaddr_tmp[14:5]][0:0]; + task_x_buf (wr_mode_b, 7, 0, 0, dobdo_ltmp, dobdo_tmp, dopbdop_ltmp, dopbdop_tmp); + end + + if ((webweu_tmp[1] === 1'b1 && weawel_tmp[1] === 1'b1) || (seq == 2'b01 && weawel_tmp[1] === 1'b1 && webweu_tmp[1] === 1'b0 && viol_type == 2'b11) || (seq == 2'b01 && wr_mode_b != 2'b01 && wr_mode_a != 2'b01) || (seq == 2'b01 && wr_mode_b == 2'b01 && wr_mode_a != 2'b01 && weawel_tmp[1] === 1'b1) || (seq == 2'b11 && wr_mode_b == 2'b00 && weawel_tmp[1] !== 1'b1)) begin + dobdo_ltmp[15:8] = mem[addrbrdaddr_tmp[14:5]][15:8]; + dopbdop_ltmp[1:1] = memp[addrbrdaddr_tmp[14:5]][1:1]; + task_x_buf (wr_mode_b, 15, 8, 1, dobdo_ltmp, dobdo_tmp, dopbdop_ltmp, dopbdop_tmp); + end + + if ((webweu_tmp[2] === 1'b1 && weawel_tmp[2] === 1'b1) || (seq == 2'b01 && weawel_tmp[2] === 1'b1 && webweu_tmp[2] === 1'b0 && viol_type == 2'b11) || (seq == 2'b01 && wr_mode_b != 2'b01 && wr_mode_a != 2'b01) || (seq == 2'b01 && wr_mode_b == 2'b01 && wr_mode_a != 2'b01 && weawel_tmp[2] === 1'b1) || (seq == 2'b11 && wr_mode_b == 2'b00 && weawel_tmp[2] !== 1'b1)) begin + dobdo_ltmp[23:16] = mem[addrbrdaddr_tmp[14:5]][23:16]; + dopbdop_ltmp[2:2] = memp[addrbrdaddr_tmp[14:5]][2:2]; + task_x_buf (wr_mode_b, 23, 16, 2, dobdo_ltmp, dobdo_tmp, dopbdop_ltmp, dopbdop_tmp); + end + + if ((webweu_tmp[3] === 1'b1 && weawel_tmp[3] === 1'b1) || (seq == 2'b01 && weawel_tmp[3] === 1'b1 && webweu_tmp[3] === 1'b0 && viol_type == 2'b11) || (seq == 2'b01 && wr_mode_b != 2'b01 && wr_mode_a != 2'b01) || (seq == 2'b01 && wr_mode_b == 2'b01 && wr_mode_a != 2'b01 && weawel_tmp[3] === 1'b1) || (seq == 2'b11 && wr_mode_b == 2'b00 && weawel_tmp[3] !== 1'b1)) begin + dobdo_ltmp[31:24] = mem[addrbrdaddr_tmp[14:5]][31:24]; + dopbdop_ltmp[3:3] = memp[addrbrdaddr_tmp[14:5]][3:3]; + task_x_buf (wr_mode_b, 31, 24, 3, dobdo_ltmp, dobdo_tmp, dopbdop_ltmp, dopbdop_tmp); + end + + end // if (b_width >= width) + end + + endcase // case(b_width) + end + endtask // task_col_rd_ram_b + + + task task_rd_ram_a; + + input [15:0] addrawraddr_tmp; + inout [63:0] doado_tmp; + inout [7:0] dopadop_tmp; + + begin + + case (a_width) + 1, 2, 4 : begin + if (a_width >= width) + doado_tmp = mem[addrawraddr_tmp[14:addrawraddr_lbit_124]]; + + else + doado_tmp = mem[addrawraddr_tmp[14:addrawraddr_bit_124+1]][(addrawraddr_tmp[addrawraddr_bit_124:addrawraddr_lbit_124] * a_width) +: a_width]; + end + 8 : begin + if (a_width >= width) begin + doado_tmp = mem[addrawraddr_tmp[14:3]]; + dopadop_tmp = memp[addrawraddr_tmp[14:3]]; + end + else begin + doado_tmp = mem[addrawraddr_tmp[14:addrawraddr_bit_8+1]][(addrawraddr_tmp[addrawraddr_bit_8:3] * 8) +: 8]; + dopadop_tmp = memp[addrawraddr_tmp[14:addrawraddr_bit_8+1]][(addrawraddr_tmp[addrawraddr_bit_8:3] * 1) +: 1]; + end + end + 16 : begin + if (a_width >= width) begin + doado_tmp = mem[addrawraddr_tmp[14:4]]; + dopadop_tmp = memp[addrawraddr_tmp[14:4]]; + end + else begin + doado_tmp = mem[addrawraddr_tmp[14:addrawraddr_bit_16+1]][(addrawraddr_tmp[addrawraddr_bit_16:4] * 16) +: 16]; + dopadop_tmp = memp[addrawraddr_tmp[14:addrawraddr_bit_16+1]][(addrawraddr_tmp[addrawraddr_bit_16:4] * 2) +: 2]; + end + end + 32 : begin + if (a_width >= width) begin + doado_tmp = mem[addrawraddr_tmp[14:5]]; + dopadop_tmp = memp[addrawraddr_tmp[14:5]]; + end + end + + endcase // case(a_width) + + end + endtask // task_rd_ram_a + + + task task_rd_ram_b; + + input [15:0] addrbrdaddr_tmp; + inout [31:0] dobdo_tmp; + inout [3:0] dopbdop_tmp; + + begin + + case (b_width) + 1, 2, 4 : begin + if (b_width >= width) + dobdo_tmp = mem[addrbrdaddr_tmp[14:addrbrdaddr_lbit_124]]; + else + dobdo_tmp = mem[addrbrdaddr_tmp[14:addrbrdaddr_bit_124+1]][(addrbrdaddr_tmp[addrbrdaddr_bit_124:addrbrdaddr_lbit_124] * b_width) +: b_width]; + end + 8 : begin + if (b_width >= width) begin + dobdo_tmp = mem[addrbrdaddr_tmp[14:3]]; + dopbdop_tmp = memp[addrbrdaddr_tmp[14:3]]; + end + else begin + dobdo_tmp = mem[addrbrdaddr_tmp[14:addrbrdaddr_bit_8+1]][(addrbrdaddr_tmp[addrbrdaddr_bit_8:3] * 8) +: 8]; + dopbdop_tmp = memp[addrbrdaddr_tmp[14:addrbrdaddr_bit_8+1]][(addrbrdaddr_tmp[addrbrdaddr_bit_8:3] * 1) +: 1]; + end + end + 16 : begin + if (b_width >= width) begin + dobdo_tmp = mem[addrbrdaddr_tmp[14:4]]; + dopbdop_tmp = memp[addrbrdaddr_tmp[14:4]]; + end + else begin + dobdo_tmp = mem[addrbrdaddr_tmp[14:addrbrdaddr_bit_16+1]][(addrbrdaddr_tmp[addrbrdaddr_bit_16:4] * 16) +: 16]; + dopbdop_tmp = memp[addrbrdaddr_tmp[14:addrbrdaddr_bit_16+1]][(addrbrdaddr_tmp[addrbrdaddr_bit_16:4] * 2) +: 2]; + end + end + 32 : begin + dobdo_tmp = mem[addrbrdaddr_tmp[14:5]]; + dopbdop_tmp = memp[addrbrdaddr_tmp[14:5]]; + end + + endcase + end + endtask // task_rd_ram_b + + + task chk_for_col_msg; + + input weawel_tmp; + input webweu_tmp; + input [15:0] addrawraddr_tmp; + input [15:0] addrbrdaddr_tmp; + + begin + + if ((SIM_COLLISION_CHECK == "ALL" || SIM_COLLISION_CHECK == "WARNING_ONLY") && !(((wr_mode_b == 2'b01 && webweu_tmp === 1'b1 && weawel_tmp === 1'b0) && viol_time == 1) || ((wr_mode_a == 2'b01 && weawel_tmp === 1'b1 && webweu_tmp === 1'b0) && viol_time == 1))) + + if (weawel_tmp === 1'b1 && webweu_tmp === 1'b1 && col_wr_wr_msg == 1) begin + $display("Memory Collision Error on RAMB16BWER : %m at simulation time %.3f ns.\nA write was requested to the same address simultaneously at both port A and port B of the RAM. The contents written to the RAM at address location %h (hex) of port A and address location %h (hex) of port B are unknown.", $time/1000.0, addrawraddr_tmp, addrbrdaddr_tmp); + col_wr_wr_msg = 0; + end + + else if (weawel_tmp === 1'b1 && webweu_tmp === 1'b0 && col_wra_rdb_msg == 1) begin + + if ((wr_mode_a == 2'b01 || wr_mode_b == 2'b01) && viol_time == 2 && SIM_DEVICE == "SPARTAN6") + $display("Memory Collision Error on RAMB16BWER : %m at simulation time %.3f ns.\nA read was performed on address %h (hex) of port B while a write was requested to the same address on port A. The write will be unsuccessful and the content of the RAM at address location %h (hex) of port A became unknown.", $time/1000.0, addrbrdaddr_tmp, addrawraddr_tmp); + else + $display("Memory Collision Error on RAMB16BWER : %m at simulation time %.3f ns.\nA read was performed on address %h (hex) of port B while a write was requested to the same address on port A. The write will be successful however the read value on port B is unknown until the next CLKBRDCLK cycle.", $time/1000.0, addrbrdaddr_tmp); + col_wra_rdb_msg = 0; + end + + else if (weawel_tmp === 1'b0 && webweu_tmp === 1'b1 && col_wrb_rda_msg == 1) begin + + if ((wr_mode_a == 2'b01 || wr_mode_b == 2'b01) && viol_time == 2 && SIM_DEVICE == "SPARTAN6") + $display("Memory Collision Error on RAMB16BWER : %m at simulation time %.3f ns.\nA read was performed on address %h (hex) of port A while a write was requested to the same address on port B. The write will be unsuccessful and the content of the RAM at address location %h (hex) of port B became unknown.", $time/1000.0, addrawraddr_tmp, addrbrdaddr_tmp); + else + $display("Memory Collision Error on RAMB16BWER : %m at simulation time %.3f ns.\nA read was performed on address %h (hex) of port A while a write was requested to the same address on port B. The write will be successful however the read value on port A is unknown until the next CLKAWRCLK cycle.", $time/1000.0, addrawraddr_tmp); + col_wrb_rda_msg = 0; + end + + end + + endtask // chk_for_col_msg + + + specify + + (CLKA => DOA[0]) = (100, 100); + (CLKA => DOA[1]) = (100, 100); + (CLKA => DOA[2]) = (100, 100); + (CLKA => DOA[3]) = (100, 100); + (CLKA => DOA[4]) = (100, 100); + (CLKA => DOA[5]) = (100, 100); + (CLKA => DOA[6]) = (100, 100); + (CLKA => DOA[7]) = (100, 100); + (CLKA => DOA[8]) = (100, 100); + (CLKA => DOA[9]) = (100, 100); + (CLKA => DOA[10]) = (100, 100); + (CLKA => DOA[11]) = (100, 100); + (CLKA => DOA[12]) = (100, 100); + (CLKA => DOA[13]) = (100, 100); + (CLKA => DOA[14]) = (100, 100); + (CLKA => DOA[15]) = (100, 100); + (CLKA => DOA[16]) = (100, 100); + (CLKA => DOA[17]) = (100, 100); + (CLKA => DOA[18]) = (100, 100); + (CLKA => DOA[19]) = (100, 100); + (CLKA => DOA[20]) = (100, 100); + (CLKA => DOA[21]) = (100, 100); + (CLKA => DOA[22]) = (100, 100); + (CLKA => DOA[23]) = (100, 100); + (CLKA => DOA[24]) = (100, 100); + (CLKA => DOA[25]) = (100, 100); + (CLKA => DOA[26]) = (100, 100); + (CLKA => DOA[27]) = (100, 100); + (CLKA => DOA[28]) = (100, 100); + (CLKA => DOA[29]) = (100, 100); + (CLKA => DOA[30]) = (100, 100); + (CLKA => DOA[31]) = (100, 100); + (CLKA => DOPA[0]) = (100, 100); + (CLKA => DOPA[1]) = (100, 100); + (CLKA => DOPA[2]) = (100, 100); + (CLKA => DOPA[3]) = (100, 100); + (CLKB => DOB[0]) = (100, 100); + (CLKB => DOB[1]) = (100, 100); + (CLKB => DOB[2]) = (100, 100); + (CLKB => DOB[3]) = (100, 100); + (CLKB => DOB[4]) = (100, 100); + (CLKB => DOB[5]) = (100, 100); + (CLKB => DOB[6]) = (100, 100); + (CLKB => DOB[7]) = (100, 100); + (CLKB => DOB[8]) = (100, 100); + (CLKB => DOB[9]) = (100, 100); + (CLKB => DOB[10]) = (100, 100); + (CLKB => DOB[11]) = (100, 100); + (CLKB => DOB[12]) = (100, 100); + (CLKB => DOB[13]) = (100, 100); + (CLKB => DOB[14]) = (100, 100); + (CLKB => DOB[15]) = (100, 100); + (CLKB => DOB[16]) = (100, 100); + (CLKB => DOB[17]) = (100, 100); + (CLKB => DOB[18]) = (100, 100); + (CLKB => DOB[19]) = (100, 100); + (CLKB => DOB[20]) = (100, 100); + (CLKB => DOB[21]) = (100, 100); + (CLKB => DOB[22]) = (100, 100); + (CLKB => DOB[23]) = (100, 100); + (CLKB => DOB[24]) = (100, 100); + (CLKB => DOB[25]) = (100, 100); + (CLKB => DOB[26]) = (100, 100); + (CLKB => DOB[27]) = (100, 100); + (CLKB => DOB[28]) = (100, 100); + (CLKB => DOB[29]) = (100, 100); + (CLKB => DOB[30]) = (100, 100); + (CLKB => DOB[31]) = (100, 100); + (CLKB => DOPB[0]) = (100, 100); + (CLKB => DOPB[1]) = (100, 100); + (CLKB => DOPB[2]) = (100, 100); + (CLKB => DOPB[3]) = (100, 100); + + specparam PATHPULSE$ = 0; + + endspecify + + +endmodule // RAMB16BWER diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/RAMB16BWE_S18.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/RAMB16BWE_S18.v new file mode 100644 index 0000000..bda09c0 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/RAMB16BWE_S18.v @@ -0,0 +1,233 @@ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2005 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / 16K-Bit Data and 2K-Bit Parity Dual Port Block RAM +// /___/ /\ Filename : RAMB16BWE_S18.v +// \ \ / \ Timestamp : Wed Jun 8 16:43:35 PST 2005 +// \___\/\___\ +// +// Generated by : VerilogFileWriter (write_verilog) +// +// Revision: +// 06/08/05 - Initial version. +// End Revision +`timescale 1 ps / 1 ps + +module RAMB16BWE_S18 ( + DO, + DOP, + ADDR, + CLK, + DI, + DIP, + EN, + SSR, + WE + +); + +output [15:0] DO; +output [1:0] DOP; + +input CLK; +input EN; +input SSR; +input [1:0] WE; +input [15:0] DI; +input [1:0] DIP; +input [9:0] ADDR; + + +parameter INIT = 18'h0; +parameter INITP_00 = 256'h0; +parameter INITP_01 = 256'h0; +parameter INITP_02 = 256'h0; +parameter INITP_03 = 256'h0; +parameter INITP_04 = 256'h0; +parameter INITP_05 = 256'h0; +parameter INITP_06 = 256'h0; +parameter INITP_07 = 256'h0; +parameter INIT_00 = 256'h0; +parameter INIT_01 = 256'h0; +parameter INIT_02 = 256'h0; +parameter INIT_03 = 256'h0; +parameter INIT_04 = 256'h0; +parameter INIT_05 = 256'h0; +parameter INIT_06 = 256'h0; +parameter INIT_07 = 256'h0; +parameter INIT_08 = 256'h0; +parameter INIT_09 = 256'h0; +parameter INIT_0A = 256'h0; +parameter INIT_0B = 256'h0; +parameter INIT_0C = 256'h0; +parameter INIT_0D = 256'h0; +parameter INIT_0E = 256'h0; +parameter INIT_0F = 256'h0; +parameter INIT_10 = 256'h0; +parameter INIT_11 = 256'h0; +parameter INIT_12 = 256'h0; +parameter INIT_13 = 256'h0; +parameter INIT_14 = 256'h0; +parameter INIT_15 = 256'h0; +parameter INIT_16 = 256'h0; +parameter INIT_17 = 256'h0; +parameter INIT_18 = 256'h0; +parameter INIT_19 = 256'h0; +parameter INIT_1A = 256'h0; +parameter INIT_1B = 256'h0; +parameter INIT_1C = 256'h0; +parameter INIT_1D = 256'h0; +parameter INIT_1E = 256'h0; +parameter INIT_1F = 256'h0; +parameter INIT_20 = 256'h0; +parameter INIT_21 = 256'h0; +parameter INIT_22 = 256'h0; +parameter INIT_23 = 256'h0; +parameter INIT_24 = 256'h0; +parameter INIT_25 = 256'h0; +parameter INIT_26 = 256'h0; +parameter INIT_27 = 256'h0; +parameter INIT_28 = 256'h0; +parameter INIT_29 = 256'h0; +parameter INIT_2A = 256'h0; +parameter INIT_2B = 256'h0; +parameter INIT_2C = 256'h0; +parameter INIT_2D = 256'h0; +parameter INIT_2E = 256'h0; +parameter INIT_2F = 256'h0; +parameter INIT_30 = 256'h0; +parameter INIT_31 = 256'h0; +parameter INIT_32 = 256'h0; +parameter INIT_33 = 256'h0; +parameter INIT_34 = 256'h0; +parameter INIT_35 = 256'h0; +parameter INIT_36 = 256'h0; +parameter INIT_37 = 256'h0; +parameter INIT_38 = 256'h0; +parameter INIT_39 = 256'h0; +parameter INIT_3A = 256'h0; +parameter INIT_3B = 256'h0; +parameter INIT_3C = 256'h0; +parameter INIT_3D = 256'h0; +parameter INIT_3E = 256'h0; +parameter INIT_3F = 256'h0; +parameter SRVAL = 18'h0; +parameter WRITE_MODE = "WRITE_FIRST"; + + + +wire [15:0] OPEN_DO; +wire [1:0] OPEN_DOP; +wire [31:0] OPEN_DOA; +wire [31:0] OPEN_DOB; +wire [3:0] OPEN_DOPA; +wire [3:0] OPEN_DOPB; + +RAMB16BWE ramb16bwe_1 ( + .ADDRA ({ADDR, 4'b0}), + .ADDRB (14'b0), + .CLKA (CLK), + .CLKB (1'b0), + .DIA ({16'b0, DI}), + .DIPA ({2'b0, DIP}), + .DIB (32'b0), + .DIPB (4'b0), + + .DOA ({OPEN_DO, DO}), + .DOB (OPEN_DOB), + .DOPA ({OPEN_DOP, DOP}), + .DOPB (OPEN_DOPB), + .ENA (EN), + .ENB (1'b0), + .SSRA (SSR), + .SSRB (1'b0), + .WEA ({WE[1],WE[0],WE[1],WE[0]}), + .WEB (4'b0) +); + +defparam ramb16bwe_1.DATA_WIDTH_A = 18; +defparam ramb16bwe_1.DATA_WIDTH_B = 0; + +defparam ramb16bwe_1.INITP_00 = INITP_00; +defparam ramb16bwe_1.INITP_01 = INITP_01; +defparam ramb16bwe_1.INITP_02 = INITP_02; +defparam ramb16bwe_1.INITP_03 = INITP_03; +defparam ramb16bwe_1.INITP_04 = INITP_04; +defparam ramb16bwe_1.INITP_05 = INITP_05; +defparam ramb16bwe_1.INITP_06 = INITP_06; +defparam ramb16bwe_1.INITP_07 = INITP_07; +defparam ramb16bwe_1.INIT_00 = INIT_00; +defparam ramb16bwe_1.INIT_01 = INIT_01; +defparam ramb16bwe_1.INIT_02 = INIT_02; +defparam ramb16bwe_1.INIT_03 = INIT_03; +defparam ramb16bwe_1.INIT_04 = INIT_04; +defparam ramb16bwe_1.INIT_05 = INIT_05; +defparam ramb16bwe_1.INIT_06 = INIT_06; +defparam ramb16bwe_1.INIT_07 = INIT_07; +defparam ramb16bwe_1.INIT_08 = INIT_08; +defparam ramb16bwe_1.INIT_09 = INIT_09; +defparam ramb16bwe_1.INIT_0A = INIT_0A; +defparam ramb16bwe_1.INIT_0B = INIT_0B; +defparam ramb16bwe_1.INIT_0C = INIT_0C; +defparam ramb16bwe_1.INIT_0D = INIT_0D; +defparam ramb16bwe_1.INIT_0E = INIT_0E; +defparam ramb16bwe_1.INIT_0F = INIT_0F; +defparam ramb16bwe_1.INIT_10 = INIT_10; +defparam ramb16bwe_1.INIT_11 = INIT_11; +defparam ramb16bwe_1.INIT_12 = INIT_12; +defparam ramb16bwe_1.INIT_13 = INIT_13; +defparam ramb16bwe_1.INIT_14 = INIT_14; +defparam ramb16bwe_1.INIT_15 = INIT_15; +defparam ramb16bwe_1.INIT_16 = INIT_16; +defparam ramb16bwe_1.INIT_17 = INIT_17; +defparam ramb16bwe_1.INIT_18 = INIT_18; +defparam ramb16bwe_1.INIT_19 = INIT_19; +defparam ramb16bwe_1.INIT_1A = INIT_1A; +defparam ramb16bwe_1.INIT_1B = INIT_1B; +defparam ramb16bwe_1.INIT_1C = INIT_1C; +defparam ramb16bwe_1.INIT_1D = INIT_1D; +defparam ramb16bwe_1.INIT_1E = INIT_1E; +defparam ramb16bwe_1.INIT_1F = INIT_1F; +defparam ramb16bwe_1.INIT_20 = INIT_20; +defparam ramb16bwe_1.INIT_21 = INIT_21; +defparam ramb16bwe_1.INIT_22 = INIT_22; +defparam ramb16bwe_1.INIT_23 = INIT_23; +defparam ramb16bwe_1.INIT_24 = INIT_24; +defparam ramb16bwe_1.INIT_25 = INIT_25; +defparam ramb16bwe_1.INIT_26 = INIT_26; +defparam ramb16bwe_1.INIT_27 = INIT_27; +defparam ramb16bwe_1.INIT_28 = INIT_28; +defparam ramb16bwe_1.INIT_29 = INIT_29; +defparam ramb16bwe_1.INIT_2A = INIT_2A; +defparam ramb16bwe_1.INIT_2B = INIT_2B; +defparam ramb16bwe_1.INIT_2C = INIT_2C; +defparam ramb16bwe_1.INIT_2D = INIT_2D; +defparam ramb16bwe_1.INIT_2E = INIT_2E; +defparam ramb16bwe_1.INIT_2F = INIT_2F; +defparam ramb16bwe_1.INIT_30 = INIT_30; +defparam ramb16bwe_1.INIT_31 = INIT_31; +defparam ramb16bwe_1.INIT_32 = INIT_32; +defparam ramb16bwe_1.INIT_33 = INIT_33; +defparam ramb16bwe_1.INIT_34 = INIT_34; +defparam ramb16bwe_1.INIT_35 = INIT_35; +defparam ramb16bwe_1.INIT_36 = INIT_36; +defparam ramb16bwe_1.INIT_37 = INIT_37; +defparam ramb16bwe_1.INIT_38 = INIT_38; +defparam ramb16bwe_1.INIT_39 = INIT_39; +defparam ramb16bwe_1.INIT_3A = INIT_3A; +defparam ramb16bwe_1.INIT_3B = INIT_3B; +defparam ramb16bwe_1.INIT_3C = INIT_3C; +defparam ramb16bwe_1.INIT_3D = INIT_3D; +defparam ramb16bwe_1.INIT_3E = INIT_3E; +defparam ramb16bwe_1.INIT_3F = INIT_3F; +defparam ramb16bwe_1.INIT_A = INIT; +defparam ramb16bwe_1.SIM_COLLISION_CHECK = "NONE"; +defparam ramb16bwe_1.SRVAL_A = SRVAL; +defparam ramb16bwe_1.WRITE_MODE_A = WRITE_MODE; +endmodule diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/RAMB16BWE_S18_S18.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/RAMB16BWE_S18_S18.v new file mode 100644 index 0000000..eb795c1 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/RAMB16BWE_S18_S18.v @@ -0,0 +1,257 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/trilogy/RAMB16BWE_S18_S18.v,v 1.3 2006/02/22 23:58:03 fphillip Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2005 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / 16K-Bit Data and 2K-Bit Parity Dual Port Block RAM +// /___/ /\ Filename : RAMB16BWE_S18_S18.v +// \ \ / \ Timestamp : Wed Jun 8 16:43:35 PST 2005 +// \___\/\___\ +// +// Generated by : VerilogFileWriter (write_verilog) +// +// Revision: +// 06/08/05 - Initial version. +// End Revision + +`timescale 1 ps / 1 ps + +module RAMB16BWE_S18_S18 ( + DOA, + DOB, + DOPA, + DOPB, + ADDRA, + ADDRB, + CLKA, + CLKB, + DIA, + DIB, + DIPA, + DIPB, + ENA, + ENB, + SSRA, + SSRB, + WEA, + WEB + +); + +output [15:0] DOA; +output [15:0] DOB; +output [1:0] DOPA; +output [1:0] DOPB; + +input CLKA; +input CLKB; +input ENA; +input ENB; +input SSRA; +input SSRB; +input [1:0] WEB; +input [1:0] WEA; +input [15:0] DIA; +input [15:0] DIB; +input [1:0] DIPA; +input [1:0] DIPB; +input [9:0] ADDRA; +input [9:0] ADDRB; + +parameter INITP_00 = 256'h0; +parameter INITP_01 = 256'h0; +parameter INITP_02 = 256'h0; +parameter INITP_03 = 256'h0; +parameter INITP_04 = 256'h0; +parameter INITP_05 = 256'h0; +parameter INITP_06 = 256'h0; +parameter INITP_07 = 256'h0; +parameter INIT_00 = 256'h0; +parameter INIT_01 = 256'h0; +parameter INIT_02 = 256'h0; +parameter INIT_03 = 256'h0; +parameter INIT_04 = 256'h0; +parameter INIT_05 = 256'h0; +parameter INIT_06 = 256'h0; +parameter INIT_07 = 256'h0; +parameter INIT_08 = 256'h0; +parameter INIT_09 = 256'h0; +parameter INIT_0A = 256'h0; +parameter INIT_0B = 256'h0; +parameter INIT_0C = 256'h0; +parameter INIT_0D = 256'h0; +parameter INIT_0E = 256'h0; +parameter INIT_0F = 256'h0; +parameter INIT_10 = 256'h0; +parameter INIT_11 = 256'h0; +parameter INIT_12 = 256'h0; +parameter INIT_13 = 256'h0; +parameter INIT_14 = 256'h0; +parameter INIT_15 = 256'h0; +parameter INIT_16 = 256'h0; +parameter INIT_17 = 256'h0; +parameter INIT_18 = 256'h0; +parameter INIT_19 = 256'h0; +parameter INIT_1A = 256'h0; +parameter INIT_1B = 256'h0; +parameter INIT_1C = 256'h0; +parameter INIT_1D = 256'h0; +parameter INIT_1E = 256'h0; +parameter INIT_1F = 256'h0; +parameter INIT_20 = 256'h0; +parameter INIT_21 = 256'h0; +parameter INIT_22 = 256'h0; +parameter INIT_23 = 256'h0; +parameter INIT_24 = 256'h0; +parameter INIT_25 = 256'h0; +parameter INIT_26 = 256'h0; +parameter INIT_27 = 256'h0; +parameter INIT_28 = 256'h0; +parameter INIT_29 = 256'h0; +parameter INIT_2A = 256'h0; +parameter INIT_2B = 256'h0; +parameter INIT_2C = 256'h0; +parameter INIT_2D = 256'h0; +parameter INIT_2E = 256'h0; +parameter INIT_2F = 256'h0; +parameter INIT_30 = 256'h0; +parameter INIT_31 = 256'h0; +parameter INIT_32 = 256'h0; +parameter INIT_33 = 256'h0; +parameter INIT_34 = 256'h0; +parameter INIT_35 = 256'h0; +parameter INIT_36 = 256'h0; +parameter INIT_37 = 256'h0; +parameter INIT_38 = 256'h0; +parameter INIT_39 = 256'h0; +parameter INIT_3A = 256'h0; +parameter INIT_3B = 256'h0; +parameter INIT_3C = 256'h0; +parameter INIT_3D = 256'h0; +parameter INIT_3E = 256'h0; +parameter INIT_3F = 256'h0; +parameter INIT_A = 18'h0; +parameter INIT_B = 18'h0; +parameter SIM_COLLISION_CHECK = "ALL"; +parameter SRVAL_A = 18'h0; +parameter SRVAL_B = 18'h0; +parameter WRITE_MODE_A = "WRITE_FIRST"; +parameter WRITE_MODE_B = "WRITE_FIRST"; + + + +wire [15:0] OPEN_DOA; +wire [15:0] OPEN_DOB; +wire [1:0] OPEN_DOPA; +wire [1:0] OPEN_DOPB; + +RAMB16BWE ramb16bwe_1 ( + .ADDRA ({ADDRA, 4'b0}), + .ADDRB ({ADDRB, 4'b0}), + .CLKA (CLKA), + .CLKB (CLKB), + .DIA ({16'b0, DIA}), + .DIB ({16'b0, DIB}), + .DIPA ({2'b0, DIPA}), + .DIPB ({2'b0, DIPB}), + .DOA ({OPEN_DOA, DOA}), + .DOB ({OPEN_DOB, DOB}), + .DOPA ({OPEN_DOPA, DOPA}), + .DOPB ({OPEN_DOPB, DOPB}), + .ENA (ENA), + .ENB (ENB), + .SSRA (SSRA), + .SSRB (SSRB), + .WEA ({WEA[1],WEA[0],WEA[1],WEA[0]}), + .WEB ({WEB[1],WEB[0],WEB[1],WEB[0]}) +); + +defparam ramb16bwe_1.DATA_WIDTH_A = 18; +defparam ramb16bwe_1.DATA_WIDTH_B = 18; + +defparam ramb16bwe_1.INITP_00 = INITP_00; +defparam ramb16bwe_1.INITP_01 = INITP_01; +defparam ramb16bwe_1.INITP_02 = INITP_02; +defparam ramb16bwe_1.INITP_03 = INITP_03; +defparam ramb16bwe_1.INITP_04 = INITP_04; +defparam ramb16bwe_1.INITP_05 = INITP_05; +defparam ramb16bwe_1.INITP_06 = INITP_06; +defparam ramb16bwe_1.INITP_07 = INITP_07; +defparam ramb16bwe_1.INIT_00 = INIT_00; +defparam ramb16bwe_1.INIT_01 = INIT_01; +defparam ramb16bwe_1.INIT_02 = INIT_02; +defparam ramb16bwe_1.INIT_03 = INIT_03; +defparam ramb16bwe_1.INIT_04 = INIT_04; +defparam ramb16bwe_1.INIT_05 = INIT_05; +defparam ramb16bwe_1.INIT_06 = INIT_06; +defparam ramb16bwe_1.INIT_07 = INIT_07; +defparam ramb16bwe_1.INIT_08 = INIT_08; +defparam ramb16bwe_1.INIT_09 = INIT_09; +defparam ramb16bwe_1.INIT_0A = INIT_0A; +defparam ramb16bwe_1.INIT_0B = INIT_0B; +defparam ramb16bwe_1.INIT_0C = INIT_0C; +defparam ramb16bwe_1.INIT_0D = INIT_0D; +defparam ramb16bwe_1.INIT_0E = INIT_0E; +defparam ramb16bwe_1.INIT_0F = INIT_0F; +defparam ramb16bwe_1.INIT_10 = INIT_10; +defparam ramb16bwe_1.INIT_11 = INIT_11; +defparam ramb16bwe_1.INIT_12 = INIT_12; +defparam ramb16bwe_1.INIT_13 = INIT_13; +defparam ramb16bwe_1.INIT_14 = INIT_14; +defparam ramb16bwe_1.INIT_15 = INIT_15; +defparam ramb16bwe_1.INIT_16 = INIT_16; +defparam ramb16bwe_1.INIT_17 = INIT_17; +defparam ramb16bwe_1.INIT_18 = INIT_18; +defparam ramb16bwe_1.INIT_19 = INIT_19; +defparam ramb16bwe_1.INIT_1A = INIT_1A; +defparam ramb16bwe_1.INIT_1B = INIT_1B; +defparam ramb16bwe_1.INIT_1C = INIT_1C; +defparam ramb16bwe_1.INIT_1D = INIT_1D; +defparam ramb16bwe_1.INIT_1E = INIT_1E; +defparam ramb16bwe_1.INIT_1F = INIT_1F; +defparam ramb16bwe_1.INIT_20 = INIT_20; +defparam ramb16bwe_1.INIT_21 = INIT_21; +defparam ramb16bwe_1.INIT_22 = INIT_22; +defparam ramb16bwe_1.INIT_23 = INIT_23; +defparam ramb16bwe_1.INIT_24 = INIT_24; +defparam ramb16bwe_1.INIT_25 = INIT_25; +defparam ramb16bwe_1.INIT_26 = INIT_26; +defparam ramb16bwe_1.INIT_27 = INIT_27; +defparam ramb16bwe_1.INIT_28 = INIT_28; +defparam ramb16bwe_1.INIT_29 = INIT_29; +defparam ramb16bwe_1.INIT_2A = INIT_2A; +defparam ramb16bwe_1.INIT_2B = INIT_2B; +defparam ramb16bwe_1.INIT_2C = INIT_2C; +defparam ramb16bwe_1.INIT_2D = INIT_2D; +defparam ramb16bwe_1.INIT_2E = INIT_2E; +defparam ramb16bwe_1.INIT_2F = INIT_2F; +defparam ramb16bwe_1.INIT_30 = INIT_30; +defparam ramb16bwe_1.INIT_31 = INIT_31; +defparam ramb16bwe_1.INIT_32 = INIT_32; +defparam ramb16bwe_1.INIT_33 = INIT_33; +defparam ramb16bwe_1.INIT_34 = INIT_34; +defparam ramb16bwe_1.INIT_35 = INIT_35; +defparam ramb16bwe_1.INIT_36 = INIT_36; +defparam ramb16bwe_1.INIT_37 = INIT_37; +defparam ramb16bwe_1.INIT_38 = INIT_38; +defparam ramb16bwe_1.INIT_39 = INIT_39; +defparam ramb16bwe_1.INIT_3A = INIT_3A; +defparam ramb16bwe_1.INIT_3B = INIT_3B; +defparam ramb16bwe_1.INIT_3C = INIT_3C; +defparam ramb16bwe_1.INIT_3D = INIT_3D; +defparam ramb16bwe_1.INIT_3E = INIT_3E; +defparam ramb16bwe_1.INIT_3F = INIT_3F; +defparam ramb16bwe_1.INIT_A = INIT_A; +defparam ramb16bwe_1.INIT_B = INIT_B; +defparam ramb16bwe_1.SIM_COLLISION_CHECK = SIM_COLLISION_CHECK; +defparam ramb16bwe_1.SRVAL_A = SRVAL_A; +defparam ramb16bwe_1.SRVAL_B = SRVAL_B; +defparam ramb16bwe_1.WRITE_MODE_A = WRITE_MODE_A; +defparam ramb16bwe_1.WRITE_MODE_B = WRITE_MODE_B; + +endmodule diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/RAMB16BWE_S18_S9.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/RAMB16BWE_S18_S9.v new file mode 100644 index 0000000..c91958b --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/RAMB16BWE_S18_S9.v @@ -0,0 +1,254 @@ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2005 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / 16K-Bit Data and 2K-Bit Parity Dual Port Block RAM +// /___/ /\ Filename : RAMB16BWE_S18_S9.v +// \ \ / \ Timestamp : Wed Jun 8 16:43:35 PST 2005 +// \___\/\___\ +// +// Generated by : VerilogFileWriter (write_verilog) +// +// Revision: +// 06/08/05 - Initial version. +// End Revision +`timescale 1 ps / 1 ps + +module RAMB16BWE_S18_S9 ( + DOA, + DOB, + DOPA, + DOPB, + ADDRA, + ADDRB, + CLKA, + CLKB, + DIA, + DIB, + DIPA, + DIPB, + ENA, + ENB, + SSRA, + SSRB, + WEA, + WEB + +); + +output [15:0] DOA; +output [1:0] DOPA; +output [7:0] DOB; +output [0:0] DOPB; + +input [9:0] ADDRA; +input [10:0] ADDRB; +input CLKA; +input CLKB; +input [15:0] DIA; +input [1:0] DIPA; +input [7:0] DIB; +input [0:0] DIPB; +input ENA; +input ENB; +input SSRA; +input SSRB; +input [1:0] WEA; +input WEB; + +parameter INITP_00 = 256'h0; +parameter INITP_01 = 256'h0; +parameter INITP_02 = 256'h0; +parameter INITP_03 = 256'h0; +parameter INITP_04 = 256'h0; +parameter INITP_05 = 256'h0; +parameter INITP_06 = 256'h0; +parameter INITP_07 = 256'h0; +parameter INIT_00 = 256'h0; +parameter INIT_01 = 256'h0; +parameter INIT_02 = 256'h0; +parameter INIT_03 = 256'h0; +parameter INIT_04 = 256'h0; +parameter INIT_05 = 256'h0; +parameter INIT_06 = 256'h0; +parameter INIT_07 = 256'h0; +parameter INIT_08 = 256'h0; +parameter INIT_09 = 256'h0; +parameter INIT_0A = 256'h0; +parameter INIT_0B = 256'h0; +parameter INIT_0C = 256'h0; +parameter INIT_0D = 256'h0; +parameter INIT_0E = 256'h0; +parameter INIT_0F = 256'h0; +parameter INIT_10 = 256'h0; +parameter INIT_11 = 256'h0; +parameter INIT_12 = 256'h0; +parameter INIT_13 = 256'h0; +parameter INIT_14 = 256'h0; +parameter INIT_15 = 256'h0; +parameter INIT_16 = 256'h0; +parameter INIT_17 = 256'h0; +parameter INIT_18 = 256'h0; +parameter INIT_19 = 256'h0; +parameter INIT_1A = 256'h0; +parameter INIT_1B = 256'h0; +parameter INIT_1C = 256'h0; +parameter INIT_1D = 256'h0; +parameter INIT_1E = 256'h0; +parameter INIT_1F = 256'h0; +parameter INIT_20 = 256'h0; +parameter INIT_21 = 256'h0; +parameter INIT_22 = 256'h0; +parameter INIT_23 = 256'h0; +parameter INIT_24 = 256'h0; +parameter INIT_25 = 256'h0; +parameter INIT_26 = 256'h0; +parameter INIT_27 = 256'h0; +parameter INIT_28 = 256'h0; +parameter INIT_29 = 256'h0; +parameter INIT_2A = 256'h0; +parameter INIT_2B = 256'h0; +parameter INIT_2C = 256'h0; +parameter INIT_2D = 256'h0; +parameter INIT_2E = 256'h0; +parameter INIT_2F = 256'h0; +parameter INIT_30 = 256'h0; +parameter INIT_31 = 256'h0; +parameter INIT_32 = 256'h0; +parameter INIT_33 = 256'h0; +parameter INIT_34 = 256'h0; +parameter INIT_35 = 256'h0; +parameter INIT_36 = 256'h0; +parameter INIT_37 = 256'h0; +parameter INIT_38 = 256'h0; +parameter INIT_39 = 256'h0; +parameter INIT_3A = 256'h0; +parameter INIT_3B = 256'h0; +parameter INIT_3C = 256'h0; +parameter INIT_3D = 256'h0; +parameter INIT_3E = 256'h0; +parameter INIT_3F = 256'h0; +parameter INIT_A = 18'h0; +parameter INIT_B = 9'h0; +parameter SIM_COLLISION_CHECK = "ALL"; +parameter SRVAL_A = 18'h0; +parameter SRVAL_B = 9'h0; +parameter WRITE_MODE_A = "WRITE_FIRST"; +parameter WRITE_MODE_B = "WRITE_FIRST"; + + + +wire [15:0] OPEN_DOA; +wire [1:0] OPEN_DOPA; +wire [23:0] OPEN_DOB; +wire [2:0] OPEN_DOPB; + +RAMB16BWE ramb16bwe_1 ( + .ADDRA ({ADDRA, 4'b0}), + .ADDRB ({ADDRB, 3'b0}), + .CLKA (CLKA), + .CLKB (CLKB), + .DIA ({16'b0, DIA}), + .DIB ({24'b0, DIB}), + .DIPA ({2'b0, DIPA}), + .DIPB ({3'b0, DIPB}), + .DOA ({OPEN_DOA, DOA}), + .DOB ({OPEN_DOB, DOB}), + .DOPA ({OPEN_DOPA, DOPA}), + .DOPB ({OPEN_DOPB, DOPB}), + .ENA (ENA), + .ENB (ENB), + .SSRA (SSRA), + .SSRB (SSRB), + .WEA ({WEA[1], WEA[0], WEA[1], WEA[0]}), + .WEB ({WEB, WEB, WEB, WEB}) +); + +defparam ramb16bwe_1.DATA_WIDTH_A = 18; +defparam ramb16bwe_1.DATA_WIDTH_B = 9; + +defparam ramb16bwe_1.INITP_00 = INITP_00; +defparam ramb16bwe_1.INITP_01 = INITP_01; +defparam ramb16bwe_1.INITP_02 = INITP_02; +defparam ramb16bwe_1.INITP_03 = INITP_03; +defparam ramb16bwe_1.INITP_04 = INITP_04; +defparam ramb16bwe_1.INITP_05 = INITP_05; +defparam ramb16bwe_1.INITP_06 = INITP_06; +defparam ramb16bwe_1.INITP_07 = INITP_07; +defparam ramb16bwe_1.INIT_00 = INIT_00; +defparam ramb16bwe_1.INIT_01 = INIT_01; +defparam ramb16bwe_1.INIT_02 = INIT_02; +defparam ramb16bwe_1.INIT_03 = INIT_03; +defparam ramb16bwe_1.INIT_04 = INIT_04; +defparam ramb16bwe_1.INIT_05 = INIT_05; +defparam ramb16bwe_1.INIT_06 = INIT_06; +defparam ramb16bwe_1.INIT_07 = INIT_07; +defparam ramb16bwe_1.INIT_08 = INIT_08; +defparam ramb16bwe_1.INIT_09 = INIT_09; +defparam ramb16bwe_1.INIT_0A = INIT_0A; +defparam ramb16bwe_1.INIT_0B = INIT_0B; +defparam ramb16bwe_1.INIT_0C = INIT_0C; +defparam ramb16bwe_1.INIT_0D = INIT_0D; +defparam ramb16bwe_1.INIT_0E = INIT_0E; +defparam ramb16bwe_1.INIT_0F = INIT_0F; +defparam ramb16bwe_1.INIT_10 = INIT_10; +defparam ramb16bwe_1.INIT_11 = INIT_11; +defparam ramb16bwe_1.INIT_12 = INIT_12; +defparam ramb16bwe_1.INIT_13 = INIT_13; +defparam ramb16bwe_1.INIT_14 = INIT_14; +defparam ramb16bwe_1.INIT_15 = INIT_15; +defparam ramb16bwe_1.INIT_16 = INIT_16; +defparam ramb16bwe_1.INIT_17 = INIT_17; +defparam ramb16bwe_1.INIT_18 = INIT_18; +defparam ramb16bwe_1.INIT_19 = INIT_19; +defparam ramb16bwe_1.INIT_1A = INIT_1A; +defparam ramb16bwe_1.INIT_1B = INIT_1B; +defparam ramb16bwe_1.INIT_1C = INIT_1C; +defparam ramb16bwe_1.INIT_1D = INIT_1D; +defparam ramb16bwe_1.INIT_1E = INIT_1E; +defparam ramb16bwe_1.INIT_1F = INIT_1F; +defparam ramb16bwe_1.INIT_20 = INIT_20; +defparam ramb16bwe_1.INIT_21 = INIT_21; +defparam ramb16bwe_1.INIT_22 = INIT_22; +defparam ramb16bwe_1.INIT_23 = INIT_23; +defparam ramb16bwe_1.INIT_24 = INIT_24; +defparam ramb16bwe_1.INIT_25 = INIT_25; +defparam ramb16bwe_1.INIT_26 = INIT_26; +defparam ramb16bwe_1.INIT_27 = INIT_27; +defparam ramb16bwe_1.INIT_28 = INIT_28; +defparam ramb16bwe_1.INIT_29 = INIT_29; +defparam ramb16bwe_1.INIT_2A = INIT_2A; +defparam ramb16bwe_1.INIT_2B = INIT_2B; +defparam ramb16bwe_1.INIT_2C = INIT_2C; +defparam ramb16bwe_1.INIT_2D = INIT_2D; +defparam ramb16bwe_1.INIT_2E = INIT_2E; +defparam ramb16bwe_1.INIT_2F = INIT_2F; +defparam ramb16bwe_1.INIT_30 = INIT_30; +defparam ramb16bwe_1.INIT_31 = INIT_31; +defparam ramb16bwe_1.INIT_32 = INIT_32; +defparam ramb16bwe_1.INIT_33 = INIT_33; +defparam ramb16bwe_1.INIT_34 = INIT_34; +defparam ramb16bwe_1.INIT_35 = INIT_35; +defparam ramb16bwe_1.INIT_36 = INIT_36; +defparam ramb16bwe_1.INIT_37 = INIT_37; +defparam ramb16bwe_1.INIT_38 = INIT_38; +defparam ramb16bwe_1.INIT_39 = INIT_39; +defparam ramb16bwe_1.INIT_3A = INIT_3A; +defparam ramb16bwe_1.INIT_3B = INIT_3B; +defparam ramb16bwe_1.INIT_3C = INIT_3C; +defparam ramb16bwe_1.INIT_3D = INIT_3D; +defparam ramb16bwe_1.INIT_3E = INIT_3E; +defparam ramb16bwe_1.INIT_3F = INIT_3F; +defparam ramb16bwe_1.INIT_A = INIT_A; +defparam ramb16bwe_1.INIT_B = INIT_B; +defparam ramb16bwe_1.SIM_COLLISION_CHECK = SIM_COLLISION_CHECK; +defparam ramb16bwe_1.SRVAL_A = SRVAL_A; +defparam ramb16bwe_1.SRVAL_B = SRVAL_B; +defparam ramb16bwe_1.WRITE_MODE_A = WRITE_MODE_A; +defparam ramb16bwe_1.WRITE_MODE_B = WRITE_MODE_B; +endmodule diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/RAMB16BWE_S36.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/RAMB16BWE_S36.v new file mode 100644 index 0000000..146d809 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/RAMB16BWE_S36.v @@ -0,0 +1,233 @@ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2005 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / 16K-Bit Data and 2K-Bit Parity Dual Port Block RAM +// /___/ /\ Filename : RAMB16BWE_S36.v +// \ \ / \ Timestamp : Wed Jun 8 16:43:35 PST 2005 +// \___\/\___\ +// +// Generated by : VerilogFileWriter (write_verilog) +// +// Revision: +// 06/08/05 - Initial version. +// End Revision +`timescale 1 ps / 1 ps + +module RAMB16BWE_S36 ( + DO, + DOP, + ADDR, + CLK, + DI, + DIP, + EN, + SSR, + WE + +); + +output [31:0] DO; +output [3:0] DOP; + +input CLK; +input EN; +input SSR; +input [3:0] WE; +input [31:0] DI; +input [3:0] DIP; +input [8:0] ADDR; + +parameter INIT = 36'h0; +parameter INITP_00 = 256'h0; +parameter INITP_01 = 256'h0; +parameter INITP_02 = 256'h0; +parameter INITP_03 = 256'h0; +parameter INITP_04 = 256'h0; +parameter INITP_05 = 256'h0; +parameter INITP_06 = 256'h0; +parameter INITP_07 = 256'h0; +parameter INIT_00 = 256'h0; +parameter INIT_01 = 256'h0; +parameter INIT_02 = 256'h0; +parameter INIT_03 = 256'h0; +parameter INIT_04 = 256'h0; +parameter INIT_05 = 256'h0; +parameter INIT_06 = 256'h0; +parameter INIT_07 = 256'h0; +parameter INIT_08 = 256'h0; +parameter INIT_09 = 256'h0; +parameter INIT_0A = 256'h0; +parameter INIT_0B = 256'h0; +parameter INIT_0C = 256'h0; +parameter INIT_0D = 256'h0; +parameter INIT_0E = 256'h0; +parameter INIT_0F = 256'h0; +parameter INIT_10 = 256'h0; +parameter INIT_11 = 256'h0; +parameter INIT_12 = 256'h0; +parameter INIT_13 = 256'h0; +parameter INIT_14 = 256'h0; +parameter INIT_15 = 256'h0; +parameter INIT_16 = 256'h0; +parameter INIT_17 = 256'h0; +parameter INIT_18 = 256'h0; +parameter INIT_19 = 256'h0; +parameter INIT_1A = 256'h0; +parameter INIT_1B = 256'h0; +parameter INIT_1C = 256'h0; +parameter INIT_1D = 256'h0; +parameter INIT_1E = 256'h0; +parameter INIT_1F = 256'h0; +parameter INIT_20 = 256'h0; +parameter INIT_21 = 256'h0; +parameter INIT_22 = 256'h0; +parameter INIT_23 = 256'h0; +parameter INIT_24 = 256'h0; +parameter INIT_25 = 256'h0; +parameter INIT_26 = 256'h0; +parameter INIT_27 = 256'h0; +parameter INIT_28 = 256'h0; +parameter INIT_29 = 256'h0; +parameter INIT_2A = 256'h0; +parameter INIT_2B = 256'h0; +parameter INIT_2C = 256'h0; +parameter INIT_2D = 256'h0; +parameter INIT_2E = 256'h0; +parameter INIT_2F = 256'h0; +parameter INIT_30 = 256'h0; +parameter INIT_31 = 256'h0; +parameter INIT_32 = 256'h0; +parameter INIT_33 = 256'h0; +parameter INIT_34 = 256'h0; +parameter INIT_35 = 256'h0; +parameter INIT_36 = 256'h0; +parameter INIT_37 = 256'h0; +parameter INIT_38 = 256'h0; +parameter INIT_39 = 256'h0; +parameter INIT_3A = 256'h0; +parameter INIT_3B = 256'h0; +parameter INIT_3C = 256'h0; +parameter INIT_3D = 256'h0; +parameter INIT_3E = 256'h0; +parameter INIT_3F = 256'h0; +parameter SRVAL = 36'h0; +parameter WRITE_MODE = "WRITE_FIRST"; + + + +wire [31:0] OPEN_DOA; +wire [31:0] OPEN_DOB; +wire [3:0] OPEN_DOPA; +wire [3:0] OPEN_DOPB; + +RAMB16BWE ramb16bwe_1 ( + .ADDRA ({ADDR, 5'b0}), + .ADDRB (14'b0), + .CLKA (CLK), + .CLKB (1'b0), + .DIA (DI), + .DIPA (DIP), + .DIB (32'b0), + .DIPB (4'b0), + + .DOA (DO), + .DOB (OPEN_DOB), + .DOPA (DOP), + .DOPB (OPEN_DOPB), + .ENA (EN), + .ENB (1'b0), + .SSRA (SSR), + .SSRB (1'b0), + .WEA ({WE[3],WE[2],WE[1],WE[0]}), + .WEB (4'b0) + +); + + +defparam ramb16bwe_1.DATA_WIDTH_A = 36; +defparam ramb16bwe_1.DATA_WIDTH_B = 0; + +defparam ramb16bwe_1.INITP_00 = INITP_00; +defparam ramb16bwe_1.INITP_01 = INITP_01; +defparam ramb16bwe_1.INITP_02 = INITP_02; +defparam ramb16bwe_1.INITP_03 = INITP_03; +defparam ramb16bwe_1.INITP_04 = INITP_04; +defparam ramb16bwe_1.INITP_05 = INITP_05; +defparam ramb16bwe_1.INITP_06 = INITP_06; +defparam ramb16bwe_1.INITP_07 = INITP_07; +defparam ramb16bwe_1.INIT_00 = INIT_00; +defparam ramb16bwe_1.INIT_01 = INIT_01; +defparam ramb16bwe_1.INIT_02 = INIT_02; +defparam ramb16bwe_1.INIT_03 = INIT_03; +defparam ramb16bwe_1.INIT_04 = INIT_04; +defparam ramb16bwe_1.INIT_05 = INIT_05; +defparam ramb16bwe_1.INIT_06 = INIT_06; +defparam ramb16bwe_1.INIT_07 = INIT_07; +defparam ramb16bwe_1.INIT_08 = INIT_08; +defparam ramb16bwe_1.INIT_09 = INIT_09; +defparam ramb16bwe_1.INIT_0A = INIT_0A; +defparam ramb16bwe_1.INIT_0B = INIT_0B; +defparam ramb16bwe_1.INIT_0C = INIT_0C; +defparam ramb16bwe_1.INIT_0D = INIT_0D; +defparam ramb16bwe_1.INIT_0E = INIT_0E; +defparam ramb16bwe_1.INIT_0F = INIT_0F; +defparam ramb16bwe_1.INIT_10 = INIT_10; +defparam ramb16bwe_1.INIT_11 = INIT_11; +defparam ramb16bwe_1.INIT_12 = INIT_12; +defparam ramb16bwe_1.INIT_13 = INIT_13; +defparam ramb16bwe_1.INIT_14 = INIT_14; +defparam ramb16bwe_1.INIT_15 = INIT_15; +defparam ramb16bwe_1.INIT_16 = INIT_16; +defparam ramb16bwe_1.INIT_17 = INIT_17; +defparam ramb16bwe_1.INIT_18 = INIT_18; +defparam ramb16bwe_1.INIT_19 = INIT_19; +defparam ramb16bwe_1.INIT_1A = INIT_1A; +defparam ramb16bwe_1.INIT_1B = INIT_1B; +defparam ramb16bwe_1.INIT_1C = INIT_1C; +defparam ramb16bwe_1.INIT_1D = INIT_1D; +defparam ramb16bwe_1.INIT_1E = INIT_1E; +defparam ramb16bwe_1.INIT_1F = INIT_1F; +defparam ramb16bwe_1.INIT_20 = INIT_20; +defparam ramb16bwe_1.INIT_21 = INIT_21; +defparam ramb16bwe_1.INIT_22 = INIT_22; +defparam ramb16bwe_1.INIT_23 = INIT_23; +defparam ramb16bwe_1.INIT_24 = INIT_24; +defparam ramb16bwe_1.INIT_25 = INIT_25; +defparam ramb16bwe_1.INIT_26 = INIT_26; +defparam ramb16bwe_1.INIT_27 = INIT_27; +defparam ramb16bwe_1.INIT_28 = INIT_28; +defparam ramb16bwe_1.INIT_29 = INIT_29; +defparam ramb16bwe_1.INIT_2A = INIT_2A; +defparam ramb16bwe_1.INIT_2B = INIT_2B; +defparam ramb16bwe_1.INIT_2C = INIT_2C; +defparam ramb16bwe_1.INIT_2D = INIT_2D; +defparam ramb16bwe_1.INIT_2E = INIT_2E; +defparam ramb16bwe_1.INIT_2F = INIT_2F; +defparam ramb16bwe_1.INIT_30 = INIT_30; +defparam ramb16bwe_1.INIT_31 = INIT_31; +defparam ramb16bwe_1.INIT_32 = INIT_32; +defparam ramb16bwe_1.INIT_33 = INIT_33; +defparam ramb16bwe_1.INIT_34 = INIT_34; +defparam ramb16bwe_1.INIT_35 = INIT_35; +defparam ramb16bwe_1.INIT_36 = INIT_36; +defparam ramb16bwe_1.INIT_37 = INIT_37; +defparam ramb16bwe_1.INIT_38 = INIT_38; +defparam ramb16bwe_1.INIT_39 = INIT_39; +defparam ramb16bwe_1.INIT_3A = INIT_3A; +defparam ramb16bwe_1.INIT_3B = INIT_3B; +defparam ramb16bwe_1.INIT_3C = INIT_3C; +defparam ramb16bwe_1.INIT_3D = INIT_3D; +defparam ramb16bwe_1.INIT_3E = INIT_3E; +defparam ramb16bwe_1.INIT_3F = INIT_3F; +defparam ramb16bwe_1.INIT_A = INIT; +defparam ramb16bwe_1.SIM_COLLISION_CHECK = "NONE"; +defparam ramb16bwe_1.SRVAL_A = SRVAL; +defparam ramb16bwe_1.WRITE_MODE_A = WRITE_MODE; + +endmodule diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/RAMB16BWE_S36_S18.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/RAMB16BWE_S36_S18.v new file mode 100644 index 0000000..af4ac7e --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/RAMB16BWE_S36_S18.v @@ -0,0 +1,254 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/trilogy/RAMB16BWE_S36_S18.v,v 1.2 2006/02/22 23:58:03 fphillip Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2005 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / 16K-Bit Data and 2K-Bit Parity Dual Port Block RAM +// /___/ /\ Filename : RAMB16BWE_S36_S18.v +// \ \ / \ Timestamp : Wed Jun 8 16:43:35 PST 2005 +// \___\/\___\ +// +// Generated by : VerilogFileWriter (write_verilog) +// +// Revision: +// 06/08/05 - Initial version. +// End Revision + +`timescale 1 ps / 1 ps + +module RAMB16BWE_S36_S18 ( + DOA, + DOB, + DOPA, + DOPB, + ADDRA, + ADDRB, + CLKA, + CLKB, + DIA, + DIB, + DIPA, + DIPB, + ENA, + ENB, + SSRA, + SSRB, + WEA, + WEB + +); + +output [31:0] DOA; +output [3:0] DOPA; +output [15:0] DOB; +output [1:0] DOPB; + +input CLKA; +input CLKB; +input ENA; +input ENB; +input SSRA; +input SSRB; +input [3:0] WEA; +input [1:0] WEB; +input [31:0] DIA; +input [3:0] DIPA; +input [15:0] DIB; +input [1:0] DIPB; +input [8:0] ADDRA; +input [9:0] ADDRB; + +parameter INITP_00 = 256'h0; +parameter INITP_01 = 256'h0; +parameter INITP_02 = 256'h0; +parameter INITP_03 = 256'h0; +parameter INITP_04 = 256'h0; +parameter INITP_05 = 256'h0; +parameter INITP_06 = 256'h0; +parameter INITP_07 = 256'h0; +parameter INIT_00 = 256'h0; +parameter INIT_01 = 256'h0; +parameter INIT_02 = 256'h0; +parameter INIT_03 = 256'h0; +parameter INIT_04 = 256'h0; +parameter INIT_05 = 256'h0; +parameter INIT_06 = 256'h0; +parameter INIT_07 = 256'h0; +parameter INIT_08 = 256'h0; +parameter INIT_09 = 256'h0; +parameter INIT_0A = 256'h0; +parameter INIT_0B = 256'h0; +parameter INIT_0C = 256'h0; +parameter INIT_0D = 256'h0; +parameter INIT_0E = 256'h0; +parameter INIT_0F = 256'h0; +parameter INIT_10 = 256'h0; +parameter INIT_11 = 256'h0; +parameter INIT_12 = 256'h0; +parameter INIT_13 = 256'h0; +parameter INIT_14 = 256'h0; +parameter INIT_15 = 256'h0; +parameter INIT_16 = 256'h0; +parameter INIT_17 = 256'h0; +parameter INIT_18 = 256'h0; +parameter INIT_19 = 256'h0; +parameter INIT_1A = 256'h0; +parameter INIT_1B = 256'h0; +parameter INIT_1C = 256'h0; +parameter INIT_1D = 256'h0; +parameter INIT_1E = 256'h0; +parameter INIT_1F = 256'h0; +parameter INIT_20 = 256'h0; +parameter INIT_21 = 256'h0; +parameter INIT_22 = 256'h0; +parameter INIT_23 = 256'h0; +parameter INIT_24 = 256'h0; +parameter INIT_25 = 256'h0; +parameter INIT_26 = 256'h0; +parameter INIT_27 = 256'h0; +parameter INIT_28 = 256'h0; +parameter INIT_29 = 256'h0; +parameter INIT_2A = 256'h0; +parameter INIT_2B = 256'h0; +parameter INIT_2C = 256'h0; +parameter INIT_2D = 256'h0; +parameter INIT_2E = 256'h0; +parameter INIT_2F = 256'h0; +parameter INIT_30 = 256'h0; +parameter INIT_31 = 256'h0; +parameter INIT_32 = 256'h0; +parameter INIT_33 = 256'h0; +parameter INIT_34 = 256'h0; +parameter INIT_35 = 256'h0; +parameter INIT_36 = 256'h0; +parameter INIT_37 = 256'h0; +parameter INIT_38 = 256'h0; +parameter INIT_39 = 256'h0; +parameter INIT_3A = 256'h0; +parameter INIT_3B = 256'h0; +parameter INIT_3C = 256'h0; +parameter INIT_3D = 256'h0; +parameter INIT_3E = 256'h0; +parameter INIT_3F = 256'h0; +parameter INIT_A = 36'h0; +parameter INIT_B = 18'h0; +parameter SIM_COLLISION_CHECK = "ALL"; +parameter SRVAL_A = 36'h0; +parameter SRVAL_B = 18'h0; +parameter WRITE_MODE_A = "WRITE_FIRST"; +parameter WRITE_MODE_B = "WRITE_FIRST"; + + + +wire [15:0] OPEN_DOB; +wire [1:0] OPEN_DOPB; + +RAMB16BWE ramb16bwe_1 ( + .ADDRA ({ADDRA, 5'b0}), + .ADDRB ({ADDRB, 4'b0}), + .CLKA (CLKA), + .CLKB (CLKB), + .DIA (DIA), + .DIPA (DIPA), + .DIB ({16'b0, DIB}), + .DIPB ({2'b0, DIPB}), + .DOA (DOA), + .DOPA (DOPA), + .DOB ({OPEN_DOB, DOB}), + .DOPB ({OPEN_DOPB, DOPB}), + .ENA (ENA), + .ENB (ENB), + .SSRA (SSRA), + .SSRB (SSRB), + .WEA ({WEA[3], WEA[2], WEA[1], WEA[0]}), + .WEB ({WEB[1], WEB[0], WEB[1], WEB[0]}) +); + +defparam ramb16bwe_1.DATA_WIDTH_A = 36; +defparam ramb16bwe_1.DATA_WIDTH_B = 18; + +defparam ramb16bwe_1.INITP_00 = INITP_00; +defparam ramb16bwe_1.INITP_01 = INITP_01; +defparam ramb16bwe_1.INITP_02 = INITP_02; +defparam ramb16bwe_1.INITP_03 = INITP_03; +defparam ramb16bwe_1.INITP_04 = INITP_04; +defparam ramb16bwe_1.INITP_05 = INITP_05; +defparam ramb16bwe_1.INITP_06 = INITP_06; +defparam ramb16bwe_1.INITP_07 = INITP_07; +defparam ramb16bwe_1.INIT_00 = INIT_00; +defparam ramb16bwe_1.INIT_01 = INIT_01; +defparam ramb16bwe_1.INIT_02 = INIT_02; +defparam ramb16bwe_1.INIT_03 = INIT_03; +defparam ramb16bwe_1.INIT_04 = INIT_04; +defparam ramb16bwe_1.INIT_05 = INIT_05; +defparam ramb16bwe_1.INIT_06 = INIT_06; +defparam ramb16bwe_1.INIT_07 = INIT_07; +defparam ramb16bwe_1.INIT_08 = INIT_08; +defparam ramb16bwe_1.INIT_09 = INIT_09; +defparam ramb16bwe_1.INIT_0A = INIT_0A; +defparam ramb16bwe_1.INIT_0B = INIT_0B; +defparam ramb16bwe_1.INIT_0C = INIT_0C; +defparam ramb16bwe_1.INIT_0D = INIT_0D; +defparam ramb16bwe_1.INIT_0E = INIT_0E; +defparam ramb16bwe_1.INIT_0F = INIT_0F; +defparam ramb16bwe_1.INIT_10 = INIT_10; +defparam ramb16bwe_1.INIT_11 = INIT_11; +defparam ramb16bwe_1.INIT_12 = INIT_12; +defparam ramb16bwe_1.INIT_13 = INIT_13; +defparam ramb16bwe_1.INIT_14 = INIT_14; +defparam ramb16bwe_1.INIT_15 = INIT_15; +defparam ramb16bwe_1.INIT_16 = INIT_16; +defparam ramb16bwe_1.INIT_17 = INIT_17; +defparam ramb16bwe_1.INIT_18 = INIT_18; +defparam ramb16bwe_1.INIT_19 = INIT_19; +defparam ramb16bwe_1.INIT_1A = INIT_1A; +defparam ramb16bwe_1.INIT_1B = INIT_1B; +defparam ramb16bwe_1.INIT_1C = INIT_1C; +defparam ramb16bwe_1.INIT_1D = INIT_1D; +defparam ramb16bwe_1.INIT_1E = INIT_1E; +defparam ramb16bwe_1.INIT_1F = INIT_1F; +defparam ramb16bwe_1.INIT_20 = INIT_20; +defparam ramb16bwe_1.INIT_21 = INIT_21; +defparam ramb16bwe_1.INIT_22 = INIT_22; +defparam ramb16bwe_1.INIT_23 = INIT_23; +defparam ramb16bwe_1.INIT_24 = INIT_24; +defparam ramb16bwe_1.INIT_25 = INIT_25; +defparam ramb16bwe_1.INIT_26 = INIT_26; +defparam ramb16bwe_1.INIT_27 = INIT_27; +defparam ramb16bwe_1.INIT_28 = INIT_28; +defparam ramb16bwe_1.INIT_29 = INIT_29; +defparam ramb16bwe_1.INIT_2A = INIT_2A; +defparam ramb16bwe_1.INIT_2B = INIT_2B; +defparam ramb16bwe_1.INIT_2C = INIT_2C; +defparam ramb16bwe_1.INIT_2D = INIT_2D; +defparam ramb16bwe_1.INIT_2E = INIT_2E; +defparam ramb16bwe_1.INIT_2F = INIT_2F; +defparam ramb16bwe_1.INIT_30 = INIT_30; +defparam ramb16bwe_1.INIT_31 = INIT_31; +defparam ramb16bwe_1.INIT_32 = INIT_32; +defparam ramb16bwe_1.INIT_33 = INIT_33; +defparam ramb16bwe_1.INIT_34 = INIT_34; +defparam ramb16bwe_1.INIT_35 = INIT_35; +defparam ramb16bwe_1.INIT_36 = INIT_36; +defparam ramb16bwe_1.INIT_37 = INIT_37; +defparam ramb16bwe_1.INIT_38 = INIT_38; +defparam ramb16bwe_1.INIT_39 = INIT_39; +defparam ramb16bwe_1.INIT_3A = INIT_3A; +defparam ramb16bwe_1.INIT_3B = INIT_3B; +defparam ramb16bwe_1.INIT_3C = INIT_3C; +defparam ramb16bwe_1.INIT_3D = INIT_3D; +defparam ramb16bwe_1.INIT_3E = INIT_3E; +defparam ramb16bwe_1.INIT_3F = INIT_3F; +defparam ramb16bwe_1.INIT_A = INIT_A; +defparam ramb16bwe_1.INIT_B = INIT_B; +defparam ramb16bwe_1.SIM_COLLISION_CHECK = SIM_COLLISION_CHECK; +defparam ramb16bwe_1.SRVAL_A = SRVAL_A; +defparam ramb16bwe_1.SRVAL_B = SRVAL_B; +defparam ramb16bwe_1.WRITE_MODE_A = WRITE_MODE_A; +defparam ramb16bwe_1.WRITE_MODE_B = WRITE_MODE_B; +endmodule diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/RAMB16BWE_S36_S36.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/RAMB16BWE_S36_S36.v new file mode 100644 index 0000000..a91d4aa --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/RAMB16BWE_S36_S36.v @@ -0,0 +1,249 @@ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2005 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / 16K-Bit Data and 2K-Bit Parity Dual Port Block RAM +// /___/ /\ Filename : RAMB16BWE_S36_S36.v +// \ \ / \ Timestamp : Wed Jun 8 16:43:35 PST 2005 +// \___\/\___\ +// +// Generated by : VerilogFileWriter (write_verilog) +// +// Revision: +// 06/08/05 - Initial version. +// End Revision + +`timescale 1 ps / 1 ps + +module RAMB16BWE_S36_S36 ( + DOA, + DOB, + DOPA, + DOPB, + ADDRA, + ADDRB, + CLKA, + CLKB, + DIA, + DIB, + DIPA, + DIPB, + ENA, + ENB, + SSRA, + SSRB, + WEA, + WEB + +); + +output [31:0] DOA; +output [31:0] DOB; +output [3:0] DOPA; +output [3:0] DOPB; + +input CLKA; +input CLKB; +input ENA; +input ENB; +input SSRA; +input SSRB; +input [3:0] WEA; +input [3:0] WEB; +input [31:0] DIA; +input [31:0] DIB; +input [3:0] DIPA; +input [3:0] DIPB; +input [8:0] ADDRA; +input [8:0] ADDRB; + +parameter INITP_00 = 256'h0; +parameter INITP_01 = 256'h0; +parameter INITP_02 = 256'h0; +parameter INITP_03 = 256'h0; +parameter INITP_04 = 256'h0; +parameter INITP_05 = 256'h0; +parameter INITP_06 = 256'h0; +parameter INITP_07 = 256'h0; +parameter INIT_00 = 256'h0; +parameter INIT_01 = 256'h0; +parameter INIT_02 = 256'h0; +parameter INIT_03 = 256'h0; +parameter INIT_04 = 256'h0; +parameter INIT_05 = 256'h0; +parameter INIT_06 = 256'h0; +parameter INIT_07 = 256'h0; +parameter INIT_08 = 256'h0; +parameter INIT_09 = 256'h0; +parameter INIT_0A = 256'h0; +parameter INIT_0B = 256'h0; +parameter INIT_0C = 256'h0; +parameter INIT_0D = 256'h0; +parameter INIT_0E = 256'h0; +parameter INIT_0F = 256'h0; +parameter INIT_10 = 256'h0; +parameter INIT_11 = 256'h0; +parameter INIT_12 = 256'h0; +parameter INIT_13 = 256'h0; +parameter INIT_14 = 256'h0; +parameter INIT_15 = 256'h0; +parameter INIT_16 = 256'h0; +parameter INIT_17 = 256'h0; +parameter INIT_18 = 256'h0; +parameter INIT_19 = 256'h0; +parameter INIT_1A = 256'h0; +parameter INIT_1B = 256'h0; +parameter INIT_1C = 256'h0; +parameter INIT_1D = 256'h0; +parameter INIT_1E = 256'h0; +parameter INIT_1F = 256'h0; +parameter INIT_20 = 256'h0; +parameter INIT_21 = 256'h0; +parameter INIT_22 = 256'h0; +parameter INIT_23 = 256'h0; +parameter INIT_24 = 256'h0; +parameter INIT_25 = 256'h0; +parameter INIT_26 = 256'h0; +parameter INIT_27 = 256'h0; +parameter INIT_28 = 256'h0; +parameter INIT_29 = 256'h0; +parameter INIT_2A = 256'h0; +parameter INIT_2B = 256'h0; +parameter INIT_2C = 256'h0; +parameter INIT_2D = 256'h0; +parameter INIT_2E = 256'h0; +parameter INIT_2F = 256'h0; +parameter INIT_30 = 256'h0; +parameter INIT_31 = 256'h0; +parameter INIT_32 = 256'h0; +parameter INIT_33 = 256'h0; +parameter INIT_34 = 256'h0; +parameter INIT_35 = 256'h0; +parameter INIT_36 = 256'h0; +parameter INIT_37 = 256'h0; +parameter INIT_38 = 256'h0; +parameter INIT_39 = 256'h0; +parameter INIT_3A = 256'h0; +parameter INIT_3B = 256'h0; +parameter INIT_3C = 256'h0; +parameter INIT_3D = 256'h0; +parameter INIT_3E = 256'h0; +parameter INIT_3F = 256'h0; +parameter INIT_A = 36'h0; +parameter INIT_B = 36'h0; +parameter SIM_COLLISION_CHECK = "ALL"; +parameter SRVAL_A = 36'h0; +parameter SRVAL_B = 36'h0; +parameter WRITE_MODE_A = "WRITE_FIRST"; +parameter WRITE_MODE_B = "WRITE_FIRST"; + + +RAMB16BWE ramb16bwe_1 ( + .ADDRA ({ADDRA, 5'b0}), + .ADDRB ({ADDRB, 5'b0}), + .CLKA (CLKA), + .CLKB (CLKB), + .DIA (DIA), + .DIB (DIB), + .DIPA (DIPA), + .DIPB (DIPB), + .DOA (DOA), + .DOB (DOB), + .DOPA (DOPA), + .DOPB (DOPB), + .ENA (ENA), + .ENB (ENB), + .SSRA (SSRA), + .SSRB (SSRB), + .WEA (WEA), + .WEB (WEB) +); + +defparam ramb16bwe_1.DATA_WIDTH_A = 36; +defparam ramb16bwe_1.DATA_WIDTH_B = 36; + +defparam ramb16bwe_1.INITP_00 = INITP_00; +defparam ramb16bwe_1.INITP_01 = INITP_01; +defparam ramb16bwe_1.INITP_02 = INITP_02; +defparam ramb16bwe_1.INITP_03 = INITP_03; +defparam ramb16bwe_1.INITP_04 = INITP_04; +defparam ramb16bwe_1.INITP_05 = INITP_05; +defparam ramb16bwe_1.INITP_06 = INITP_06; +defparam ramb16bwe_1.INITP_07 = INITP_07; +defparam ramb16bwe_1.INIT_00 = INIT_00; +defparam ramb16bwe_1.INIT_01 = INIT_01; +defparam ramb16bwe_1.INIT_02 = INIT_02; +defparam ramb16bwe_1.INIT_03 = INIT_03; +defparam ramb16bwe_1.INIT_04 = INIT_04; +defparam ramb16bwe_1.INIT_05 = INIT_05; +defparam ramb16bwe_1.INIT_06 = INIT_06; +defparam ramb16bwe_1.INIT_07 = INIT_07; +defparam ramb16bwe_1.INIT_08 = INIT_08; +defparam ramb16bwe_1.INIT_09 = INIT_09; +defparam ramb16bwe_1.INIT_0A = INIT_0A; +defparam ramb16bwe_1.INIT_0B = INIT_0B; +defparam ramb16bwe_1.INIT_0C = INIT_0C; +defparam ramb16bwe_1.INIT_0D = INIT_0D; +defparam ramb16bwe_1.INIT_0E = INIT_0E; +defparam ramb16bwe_1.INIT_0F = INIT_0F; +defparam ramb16bwe_1.INIT_10 = INIT_10; +defparam ramb16bwe_1.INIT_11 = INIT_11; +defparam ramb16bwe_1.INIT_12 = INIT_12; +defparam ramb16bwe_1.INIT_13 = INIT_13; +defparam ramb16bwe_1.INIT_14 = INIT_14; +defparam ramb16bwe_1.INIT_15 = INIT_15; +defparam ramb16bwe_1.INIT_16 = INIT_16; +defparam ramb16bwe_1.INIT_17 = INIT_17; +defparam ramb16bwe_1.INIT_18 = INIT_18; +defparam ramb16bwe_1.INIT_19 = INIT_19; +defparam ramb16bwe_1.INIT_1A = INIT_1A; +defparam ramb16bwe_1.INIT_1B = INIT_1B; +defparam ramb16bwe_1.INIT_1C = INIT_1C; +defparam ramb16bwe_1.INIT_1D = INIT_1D; +defparam ramb16bwe_1.INIT_1E = INIT_1E; +defparam ramb16bwe_1.INIT_1F = INIT_1F; +defparam ramb16bwe_1.INIT_20 = INIT_20; +defparam ramb16bwe_1.INIT_21 = INIT_21; +defparam ramb16bwe_1.INIT_22 = INIT_22; +defparam ramb16bwe_1.INIT_23 = INIT_23; +defparam ramb16bwe_1.INIT_24 = INIT_24; +defparam ramb16bwe_1.INIT_25 = INIT_25; +defparam ramb16bwe_1.INIT_26 = INIT_26; +defparam ramb16bwe_1.INIT_27 = INIT_27; +defparam ramb16bwe_1.INIT_28 = INIT_28; +defparam ramb16bwe_1.INIT_29 = INIT_29; +defparam ramb16bwe_1.INIT_2A = INIT_2A; +defparam ramb16bwe_1.INIT_2B = INIT_2B; +defparam ramb16bwe_1.INIT_2C = INIT_2C; +defparam ramb16bwe_1.INIT_2D = INIT_2D; +defparam ramb16bwe_1.INIT_2E = INIT_2E; +defparam ramb16bwe_1.INIT_2F = INIT_2F; +defparam ramb16bwe_1.INIT_30 = INIT_30; +defparam ramb16bwe_1.INIT_31 = INIT_31; +defparam ramb16bwe_1.INIT_32 = INIT_32; +defparam ramb16bwe_1.INIT_33 = INIT_33; +defparam ramb16bwe_1.INIT_34 = INIT_34; +defparam ramb16bwe_1.INIT_35 = INIT_35; +defparam ramb16bwe_1.INIT_36 = INIT_36; +defparam ramb16bwe_1.INIT_37 = INIT_37; +defparam ramb16bwe_1.INIT_38 = INIT_38; +defparam ramb16bwe_1.INIT_39 = INIT_39; +defparam ramb16bwe_1.INIT_3A = INIT_3A; +defparam ramb16bwe_1.INIT_3B = INIT_3B; +defparam ramb16bwe_1.INIT_3C = INIT_3C; +defparam ramb16bwe_1.INIT_3D = INIT_3D; +defparam ramb16bwe_1.INIT_3E = INIT_3E; +defparam ramb16bwe_1.INIT_3F = INIT_3F; +defparam ramb16bwe_1.INIT_A = INIT_A; +defparam ramb16bwe_1.INIT_B = INIT_B; +defparam ramb16bwe_1.SIM_COLLISION_CHECK = SIM_COLLISION_CHECK; +defparam ramb16bwe_1.SRVAL_A = SRVAL_A; +defparam ramb16bwe_1.SRVAL_B = SRVAL_B; +defparam ramb16bwe_1.WRITE_MODE_A = WRITE_MODE_A; +defparam ramb16bwe_1.WRITE_MODE_B = WRITE_MODE_B; +endmodule diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/RAMB16BWE_S36_S9.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/RAMB16BWE_S36_S9.v new file mode 100644 index 0000000..a50fd42 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/RAMB16BWE_S36_S9.v @@ -0,0 +1,253 @@ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2005 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / 16K-Bit Data and 2K-Bit Parity Dual Port Block RAM +// /___/ /\ Filename : RAMB16BWE_S36_S9.v +// \ \ / \ Timestamp : Wed Jun 8 16:43:35 PST 2005 +// \___\/\___\ +// +// Generated by : VerilogFileWriter (write_verilog) +// +// Revision: +// 06/08/05 - Initial version. +// End Revision +`timescale 1 ps / 1 ps + +module RAMB16BWE_S36_S9 ( + DOA, + DOB, + DOPA, + DOPB, + ADDRA, + ADDRB, + CLKA, + CLKB, + DIA, + DIB, + DIPA, + DIPB, + ENA, + ENB, + SSRA, + SSRB, + WEA, + WEB + +); + +output [31:0] DOA; +output [3:0] DOPA; +output [7:0] DOB; +output [0:0] DOPB; + +input [8:0] ADDRA; +input [10:0] ADDRB; +input CLKA; +input CLKB; +input ENA; +input ENB; +input SSRA; +input SSRB; +input [3:0] WEA; +input WEB; +input [31:0] DIA; +input [3:0] DIPA; +input [7:0] DIB; +input [0:0] DIPB; + +parameter INITP_00 = 256'h0; +parameter INITP_01 = 256'h0; +parameter INITP_02 = 256'h0; +parameter INITP_03 = 256'h0; +parameter INITP_04 = 256'h0; +parameter INITP_05 = 256'h0; +parameter INITP_06 = 256'h0; +parameter INITP_07 = 256'h0; +parameter INIT_00 = 256'h0; +parameter INIT_01 = 256'h0; +parameter INIT_02 = 256'h0; +parameter INIT_03 = 256'h0; +parameter INIT_04 = 256'h0; +parameter INIT_05 = 256'h0; +parameter INIT_06 = 256'h0; +parameter INIT_07 = 256'h0; +parameter INIT_08 = 256'h0; +parameter INIT_09 = 256'h0; +parameter INIT_0A = 256'h0; +parameter INIT_0B = 256'h0; +parameter INIT_0C = 256'h0; +parameter INIT_0D = 256'h0; +parameter INIT_0E = 256'h0; +parameter INIT_0F = 256'h0; +parameter INIT_10 = 256'h0; +parameter INIT_11 = 256'h0; +parameter INIT_12 = 256'h0; +parameter INIT_13 = 256'h0; +parameter INIT_14 = 256'h0; +parameter INIT_15 = 256'h0; +parameter INIT_16 = 256'h0; +parameter INIT_17 = 256'h0; +parameter INIT_18 = 256'h0; +parameter INIT_19 = 256'h0; +parameter INIT_1A = 256'h0; +parameter INIT_1B = 256'h0; +parameter INIT_1C = 256'h0; +parameter INIT_1D = 256'h0; +parameter INIT_1E = 256'h0; +parameter INIT_1F = 256'h0; +parameter INIT_20 = 256'h0; +parameter INIT_21 = 256'h0; +parameter INIT_22 = 256'h0; +parameter INIT_23 = 256'h0; +parameter INIT_24 = 256'h0; +parameter INIT_25 = 256'h0; +parameter INIT_26 = 256'h0; +parameter INIT_27 = 256'h0; +parameter INIT_28 = 256'h0; +parameter INIT_29 = 256'h0; +parameter INIT_2A = 256'h0; +parameter INIT_2B = 256'h0; +parameter INIT_2C = 256'h0; +parameter INIT_2D = 256'h0; +parameter INIT_2E = 256'h0; +parameter INIT_2F = 256'h0; +parameter INIT_30 = 256'h0; +parameter INIT_31 = 256'h0; +parameter INIT_32 = 256'h0; +parameter INIT_33 = 256'h0; +parameter INIT_34 = 256'h0; +parameter INIT_35 = 256'h0; +parameter INIT_36 = 256'h0; +parameter INIT_37 = 256'h0; +parameter INIT_38 = 256'h0; +parameter INIT_39 = 256'h0; +parameter INIT_3A = 256'h0; +parameter INIT_3B = 256'h0; +parameter INIT_3C = 256'h0; +parameter INIT_3D = 256'h0; +parameter INIT_3E = 256'h0; +parameter INIT_3F = 256'h0; +parameter INIT_A = 36'h0; +parameter INIT_B = 9'h0; +parameter SIM_COLLISION_CHECK = "ALL"; +parameter SRVAL_A = 36'h0; +parameter SRVAL_B = 9'h0; +parameter WRITE_MODE_A = "WRITE_FIRST"; +parameter WRITE_MODE_B = "WRITE_FIRST"; + + + +wire [23:0] OPEN_DOB; +wire [2:0] OPEN_DOPB; + +RAMB16BWE ramb16bwe_1 ( + .ADDRA ({ADDRA, 5'b0}), + .ADDRB ({ADDRB, 3'b0}), + .CLKA (CLKA), + .CLKB (CLKB), + .DIA (DIA), + .DIPA (DIPA), + .DIB ({24'b0, DIB}), + .DIPB ({3'b0, DIPB}), + .DOA (DOA), + .DOPA (DOPA), + .DOB ({OPEN_DOB, DOB}), + .DOPB ({OPEN_DOPB, DOPB}), + .ENA (ENA), + .ENB (ENB), + .SSRA (SSRA), + .SSRB (SSRB), + .WEA ({WEA[3], WEA[2], WEA[1], WEA[0]}), + .WEB ({WEB, WEB, WEB, WEB}) +); + +defparam ramb16bwe_1.DATA_WIDTH_A = 36; +defparam ramb16bwe_1.DATA_WIDTH_B = 9; + +defparam ramb16bwe_1.INITP_00 = INITP_00; +defparam ramb16bwe_1.INITP_01 = INITP_01; +defparam ramb16bwe_1.INITP_02 = INITP_02; +defparam ramb16bwe_1.INITP_03 = INITP_03; +defparam ramb16bwe_1.INITP_04 = INITP_04; +defparam ramb16bwe_1.INITP_05 = INITP_05; +defparam ramb16bwe_1.INITP_06 = INITP_06; +defparam ramb16bwe_1.INITP_07 = INITP_07; +defparam ramb16bwe_1.INIT_00 = INIT_00; +defparam ramb16bwe_1.INIT_01 = INIT_01; +defparam ramb16bwe_1.INIT_02 = INIT_02; +defparam ramb16bwe_1.INIT_03 = INIT_03; +defparam ramb16bwe_1.INIT_04 = INIT_04; +defparam ramb16bwe_1.INIT_05 = INIT_05; +defparam ramb16bwe_1.INIT_06 = INIT_06; +defparam ramb16bwe_1.INIT_07 = INIT_07; +defparam ramb16bwe_1.INIT_08 = INIT_08; +defparam ramb16bwe_1.INIT_09 = INIT_09; +defparam ramb16bwe_1.INIT_0A = INIT_0A; +defparam ramb16bwe_1.INIT_0B = INIT_0B; +defparam ramb16bwe_1.INIT_0C = INIT_0C; +defparam ramb16bwe_1.INIT_0D = INIT_0D; +defparam ramb16bwe_1.INIT_0E = INIT_0E; +defparam ramb16bwe_1.INIT_0F = INIT_0F; +defparam ramb16bwe_1.INIT_10 = INIT_10; +defparam ramb16bwe_1.INIT_11 = INIT_11; +defparam ramb16bwe_1.INIT_12 = INIT_12; +defparam ramb16bwe_1.INIT_13 = INIT_13; +defparam ramb16bwe_1.INIT_14 = INIT_14; +defparam ramb16bwe_1.INIT_15 = INIT_15; +defparam ramb16bwe_1.INIT_16 = INIT_16; +defparam ramb16bwe_1.INIT_17 = INIT_17; +defparam ramb16bwe_1.INIT_18 = INIT_18; +defparam ramb16bwe_1.INIT_19 = INIT_19; +defparam ramb16bwe_1.INIT_1A = INIT_1A; +defparam ramb16bwe_1.INIT_1B = INIT_1B; +defparam ramb16bwe_1.INIT_1C = INIT_1C; +defparam ramb16bwe_1.INIT_1D = INIT_1D; +defparam ramb16bwe_1.INIT_1E = INIT_1E; +defparam ramb16bwe_1.INIT_1F = INIT_1F; +defparam ramb16bwe_1.INIT_20 = INIT_20; +defparam ramb16bwe_1.INIT_21 = INIT_21; +defparam ramb16bwe_1.INIT_22 = INIT_22; +defparam ramb16bwe_1.INIT_23 = INIT_23; +defparam ramb16bwe_1.INIT_24 = INIT_24; +defparam ramb16bwe_1.INIT_25 = INIT_25; +defparam ramb16bwe_1.INIT_26 = INIT_26; +defparam ramb16bwe_1.INIT_27 = INIT_27; +defparam ramb16bwe_1.INIT_28 = INIT_28; +defparam ramb16bwe_1.INIT_29 = INIT_29; +defparam ramb16bwe_1.INIT_2A = INIT_2A; +defparam ramb16bwe_1.INIT_2B = INIT_2B; +defparam ramb16bwe_1.INIT_2C = INIT_2C; +defparam ramb16bwe_1.INIT_2D = INIT_2D; +defparam ramb16bwe_1.INIT_2E = INIT_2E; +defparam ramb16bwe_1.INIT_2F = INIT_2F; +defparam ramb16bwe_1.INIT_30 = INIT_30; +defparam ramb16bwe_1.INIT_31 = INIT_31; +defparam ramb16bwe_1.INIT_32 = INIT_32; +defparam ramb16bwe_1.INIT_33 = INIT_33; +defparam ramb16bwe_1.INIT_34 = INIT_34; +defparam ramb16bwe_1.INIT_35 = INIT_35; +defparam ramb16bwe_1.INIT_36 = INIT_36; +defparam ramb16bwe_1.INIT_37 = INIT_37; +defparam ramb16bwe_1.INIT_38 = INIT_38; +defparam ramb16bwe_1.INIT_39 = INIT_39; +defparam ramb16bwe_1.INIT_3A = INIT_3A; +defparam ramb16bwe_1.INIT_3B = INIT_3B; +defparam ramb16bwe_1.INIT_3C = INIT_3C; +defparam ramb16bwe_1.INIT_3D = INIT_3D; +defparam ramb16bwe_1.INIT_3E = INIT_3E; +defparam ramb16bwe_1.INIT_3F = INIT_3F; +defparam ramb16bwe_1.INIT_A = INIT_A; +defparam ramb16bwe_1.INIT_B = INIT_B; +defparam ramb16bwe_1.SIM_COLLISION_CHECK = SIM_COLLISION_CHECK; +defparam ramb16bwe_1.SRVAL_A = SRVAL_A; +defparam ramb16bwe_1.SRVAL_B = SRVAL_B; +defparam ramb16bwe_1.WRITE_MODE_A = WRITE_MODE_A; +defparam ramb16bwe_1.WRITE_MODE_B = WRITE_MODE_B; + +endmodule diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/RAMB16_S1.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/RAMB16_S1.v new file mode 100644 index 0000000..d6cc476 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/RAMB16_S1.v @@ -0,0 +1,512 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/RAMB16_S1.v,v 1.7 2005/03/14 22:54:41 wloo Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2005 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / 16K-Bit Data and 2K-Bit Parity Single Port Block RAM +// /___/ /\ Filename : RAMB16_S1.v +// \ \ / \ Timestamp : Thu Mar 10 16:43:34 PST 2005 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// End Revision + +`ifdef legacy_model + +`timescale 1 ps / 1 ps + +module RAMB16_S1 (DO, ADDR, CLK, DI, EN, SSR, WE); + + parameter INIT = 1'h0; + parameter SRVAL = 1'h0; + parameter WRITE_MODE = "WRITE_FIRST"; + + parameter INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + + output [0:0] DO; + reg do0_out; + + input [13:0] ADDR; + input [0:0] DI; + input EN, CLK, WE, SSR; + + reg [18431:0] mem; + reg [8:0] count; + reg [1:0] wr_mode; + + wire [13:0] addr_int; + wire [0:0] di_int; + wire en_int, clk_int, we_int, ssr_int; + + tri0 GSR = glbl.GSR; + + always @(GSR) + if (GSR) begin + assign do0_out = INIT[0]; + end + else begin + deassign do0_out; + end + + buf b_do_out0 (DO[0], do0_out); + buf b_addr_0 (addr_int[0], ADDR[0]); + buf b_addr_1 (addr_int[1], ADDR[1]); + buf b_addr_2 (addr_int[2], ADDR[2]); + buf b_addr_3 (addr_int[3], ADDR[3]); + buf b_addr_4 (addr_int[4], ADDR[4]); + buf b_addr_5 (addr_int[5], ADDR[5]); + buf b_addr_6 (addr_int[6], ADDR[6]); + buf b_addr_7 (addr_int[7], ADDR[7]); + buf b_addr_8 (addr_int[8], ADDR[8]); + buf b_addr_9 (addr_int[9], ADDR[9]); + buf b_addr_10 (addr_int[10], ADDR[10]); + buf b_addr_11 (addr_int[11], ADDR[11]); + buf b_addr_12 (addr_int[12], ADDR[12]); + buf b_addr_13 (addr_int[13], ADDR[13]); + buf b_di_0 (di_int[0], DI[0]); + buf b_en (en_int, EN); + buf b_clk (clk_int, CLK); + buf b_we (we_int, WE); + buf b_ssr (ssr_int, SSR); + + initial begin + for (count = 0; count < 256; count = count + 1) begin + mem[count] <= INIT_00[count]; + mem[256 * 1 + count] <= INIT_01[count]; + mem[256 * 2 + count] <= INIT_02[count]; + mem[256 * 3 + count] <= INIT_03[count]; + mem[256 * 4 + count] <= INIT_04[count]; + mem[256 * 5 + count] <= INIT_05[count]; + mem[256 * 6 + count] <= INIT_06[count]; + mem[256 * 7 + count] <= INIT_07[count]; + mem[256 * 8 + count] <= INIT_08[count]; + mem[256 * 9 + count] <= INIT_09[count]; + mem[256 * 10 + count] <= INIT_0A[count]; + mem[256 * 11 + count] <= INIT_0B[count]; + mem[256 * 12 + count] <= INIT_0C[count]; + mem[256 * 13 + count] <= INIT_0D[count]; + mem[256 * 14 + count] <= INIT_0E[count]; + mem[256 * 15 + count] <= INIT_0F[count]; + mem[256 * 16 + count] <= INIT_10[count]; + mem[256 * 17 + count] <= INIT_11[count]; + mem[256 * 18 + count] <= INIT_12[count]; + mem[256 * 19 + count] <= INIT_13[count]; + mem[256 * 20 + count] <= INIT_14[count]; + mem[256 * 21 + count] <= INIT_15[count]; + mem[256 * 22 + count] <= INIT_16[count]; + mem[256 * 23 + count] <= INIT_17[count]; + mem[256 * 24 + count] <= INIT_18[count]; + mem[256 * 25 + count] <= INIT_19[count]; + mem[256 * 26 + count] <= INIT_1A[count]; + mem[256 * 27 + count] <= INIT_1B[count]; + mem[256 * 28 + count] <= INIT_1C[count]; + mem[256 * 29 + count] <= INIT_1D[count]; + mem[256 * 30 + count] <= INIT_1E[count]; + mem[256 * 31 + count] <= INIT_1F[count]; + mem[256 * 32 + count] <= INIT_20[count]; + mem[256 * 33 + count] <= INIT_21[count]; + mem[256 * 34 + count] <= INIT_22[count]; + mem[256 * 35 + count] <= INIT_23[count]; + mem[256 * 36 + count] <= INIT_24[count]; + mem[256 * 37 + count] <= INIT_25[count]; + mem[256 * 38 + count] <= INIT_26[count]; + mem[256 * 39 + count] <= INIT_27[count]; + mem[256 * 40 + count] <= INIT_28[count]; + mem[256 * 41 + count] <= INIT_29[count]; + mem[256 * 42 + count] <= INIT_2A[count]; + mem[256 * 43 + count] <= INIT_2B[count]; + mem[256 * 44 + count] <= INIT_2C[count]; + mem[256 * 45 + count] <= INIT_2D[count]; + mem[256 * 46 + count] <= INIT_2E[count]; + mem[256 * 47 + count] <= INIT_2F[count]; + mem[256 * 48 + count] <= INIT_30[count]; + mem[256 * 49 + count] <= INIT_31[count]; + mem[256 * 50 + count] <= INIT_32[count]; + mem[256 * 51 + count] <= INIT_33[count]; + mem[256 * 52 + count] <= INIT_34[count]; + mem[256 * 53 + count] <= INIT_35[count]; + mem[256 * 54 + count] <= INIT_36[count]; + mem[256 * 55 + count] <= INIT_37[count]; + mem[256 * 56 + count] <= INIT_38[count]; + mem[256 * 57 + count] <= INIT_39[count]; + mem[256 * 58 + count] <= INIT_3A[count]; + mem[256 * 59 + count] <= INIT_3B[count]; + mem[256 * 60 + count] <= INIT_3C[count]; + mem[256 * 61 + count] <= INIT_3D[count]; + mem[256 * 62 + count] <= INIT_3E[count]; + mem[256 * 63 + count] <= INIT_3F[count]; + end + end + + initial begin + case (WRITE_MODE) + "WRITE_FIRST" : wr_mode <= 2'b00; + "READ_FIRST" : wr_mode <= 2'b01; + "NO_CHANGE" : wr_mode <= 2'b10; + default : begin + $display("Attribute Syntax Error : The attribute WRITE_MODE on RAMB16_S1 instance %m is set to %s. Legal values for this attribute are WRITE_FIRST, READ_FIRST or NO_CHANGE.", WRITE_MODE); + $finish; + end + endcase + end + + always @(posedge clk_int) begin + if (en_int == 1'b1) begin + if (ssr_int == 1'b1) begin + do0_out <= SRVAL[0]; + end + else begin + if (we_int == 1'b1) begin + if (wr_mode == 2'b00) begin + do0_out <= di_int[0]; + end + else if (wr_mode == 2'b01) begin + do0_out <= mem[addr_int * 1 + 0]; + end + else begin + do0_out <= do0_out; + end + end + else begin + do0_out <= mem[addr_int * 1 + 0]; + end + end + end + end + + always @(posedge clk_int) begin + if (en_int == 1'b1 && we_int == 1'b1) begin + mem[addr_int * 1 + 0] <= di_int[0]; + end + end + + specify + (CLK *> DO) = (100, 100); + endspecify + +endmodule + +`else + +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/RAMB16_S1.v,v 1.7 2005/03/14 22:54:41 wloo Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2005 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Timing Simulation Library Component +// / / 16K-Bit Data and 2K-Bit Parity Single Port Block RAM +// /___/ /\ Filename : RAMB16_S1.v +// \ \ / \ Timestamp : Thu Mar 10 16:44:01 PST 2005 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 03/10/05 - Initialized outputs. +// End Revision + +`timescale 1 ps/1 ps + +module RAMB16_S1 (DO, ADDR, CLK, DI, EN, SSR, WE); + + parameter INIT = 1'h0; + parameter SRVAL = 1'h0; + parameter WRITE_MODE = "WRITE_FIRST"; + + parameter INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + + output [0:0] DO; + + input [13:0] ADDR; + input [0:0] DI; + input EN, CLK, WE, SSR; + + reg [0:0] do_out = INIT[0:0]; + + reg [0:0] mem [16383:0]; + + reg [8:0] count, countp; + reg [1:0] wr_mode; + + wire [13:0] addr_int; + wire [0:0] di_int; + wire en_int, clk_int, we_int, ssr_int; + + wire di_enable = en_int && we_int; + + tri0 GSR = glbl.GSR; + wire gsr_int; + + buf b_gsr (gsr_int, GSR); + + buf b_do [0:0] (DO, do_out); + buf b_addr [13:0] (addr_int, ADDR); + buf b_di [0:0] (di_int, DI); + buf b_en (en_int, EN); + buf b_clk (clk_int, CLK); + buf b_ssr (ssr_int, SSR); + buf b_we (we_int, WE); + + + always @(gsr_int) + if (gsr_int) begin + assign {do_out} = INIT; + end + else begin + deassign do_out; + end + + + initial begin + + for (count = 0; count < 256; count = count + 1) begin + mem[count] = INIT_00[(count * 1) +: 1]; + mem[256 * 1 + count] = INIT_01[(count * 1) +: 1]; + mem[256 * 2 + count] = INIT_02[(count * 1) +: 1]; + mem[256 * 3 + count] = INIT_03[(count * 1) +: 1]; + mem[256 * 4 + count] = INIT_04[(count * 1) +: 1]; + mem[256 * 5 + count] = INIT_05[(count * 1) +: 1]; + mem[256 * 6 + count] = INIT_06[(count * 1) +: 1]; + mem[256 * 7 + count] = INIT_07[(count * 1) +: 1]; + mem[256 * 8 + count] = INIT_08[(count * 1) +: 1]; + mem[256 * 9 + count] = INIT_09[(count * 1) +: 1]; + mem[256 * 10 + count] = INIT_0A[(count * 1) +: 1]; + mem[256 * 11 + count] = INIT_0B[(count * 1) +: 1]; + mem[256 * 12 + count] = INIT_0C[(count * 1) +: 1]; + mem[256 * 13 + count] = INIT_0D[(count * 1) +: 1]; + mem[256 * 14 + count] = INIT_0E[(count * 1) +: 1]; + mem[256 * 15 + count] = INIT_0F[(count * 1) +: 1]; + mem[256 * 16 + count] = INIT_10[(count * 1) +: 1]; + mem[256 * 17 + count] = INIT_11[(count * 1) +: 1]; + mem[256 * 18 + count] = INIT_12[(count * 1) +: 1]; + mem[256 * 19 + count] = INIT_13[(count * 1) +: 1]; + mem[256 * 20 + count] = INIT_14[(count * 1) +: 1]; + mem[256 * 21 + count] = INIT_15[(count * 1) +: 1]; + mem[256 * 22 + count] = INIT_16[(count * 1) +: 1]; + mem[256 * 23 + count] = INIT_17[(count * 1) +: 1]; + mem[256 * 24 + count] = INIT_18[(count * 1) +: 1]; + mem[256 * 25 + count] = INIT_19[(count * 1) +: 1]; + mem[256 * 26 + count] = INIT_1A[(count * 1) +: 1]; + mem[256 * 27 + count] = INIT_1B[(count * 1) +: 1]; + mem[256 * 28 + count] = INIT_1C[(count * 1) +: 1]; + mem[256 * 29 + count] = INIT_1D[(count * 1) +: 1]; + mem[256 * 30 + count] = INIT_1E[(count * 1) +: 1]; + mem[256 * 31 + count] = INIT_1F[(count * 1) +: 1]; + mem[256 * 32 + count] = INIT_20[(count * 1) +: 1]; + mem[256 * 33 + count] = INIT_21[(count * 1) +: 1]; + mem[256 * 34 + count] = INIT_22[(count * 1) +: 1]; + mem[256 * 35 + count] = INIT_23[(count * 1) +: 1]; + mem[256 * 36 + count] = INIT_24[(count * 1) +: 1]; + mem[256 * 37 + count] = INIT_25[(count * 1) +: 1]; + mem[256 * 38 + count] = INIT_26[(count * 1) +: 1]; + mem[256 * 39 + count] = INIT_27[(count * 1) +: 1]; + mem[256 * 40 + count] = INIT_28[(count * 1) +: 1]; + mem[256 * 41 + count] = INIT_29[(count * 1) +: 1]; + mem[256 * 42 + count] = INIT_2A[(count * 1) +: 1]; + mem[256 * 43 + count] = INIT_2B[(count * 1) +: 1]; + mem[256 * 44 + count] = INIT_2C[(count * 1) +: 1]; + mem[256 * 45 + count] = INIT_2D[(count * 1) +: 1]; + mem[256 * 46 + count] = INIT_2E[(count * 1) +: 1]; + mem[256 * 47 + count] = INIT_2F[(count * 1) +: 1]; + mem[256 * 48 + count] = INIT_30[(count * 1) +: 1]; + mem[256 * 49 + count] = INIT_31[(count * 1) +: 1]; + mem[256 * 50 + count] = INIT_32[(count * 1) +: 1]; + mem[256 * 51 + count] = INIT_33[(count * 1) +: 1]; + mem[256 * 52 + count] = INIT_34[(count * 1) +: 1]; + mem[256 * 53 + count] = INIT_35[(count * 1) +: 1]; + mem[256 * 54 + count] = INIT_36[(count * 1) +: 1]; + mem[256 * 55 + count] = INIT_37[(count * 1) +: 1]; + mem[256 * 56 + count] = INIT_38[(count * 1) +: 1]; + mem[256 * 57 + count] = INIT_39[(count * 1) +: 1]; + mem[256 * 58 + count] = INIT_3A[(count * 1) +: 1]; + mem[256 * 59 + count] = INIT_3B[(count * 1) +: 1]; + mem[256 * 60 + count] = INIT_3C[(count * 1) +: 1]; + mem[256 * 61 + count] = INIT_3D[(count * 1) +: 1]; + mem[256 * 62 + count] = INIT_3E[(count * 1) +: 1]; + mem[256 * 63 + count] = INIT_3F[(count * 1) +: 1]; + end + + end // initial begin + + + initial begin + case (WRITE_MODE) + "WRITE_FIRST" : wr_mode <= 2'b00; + "READ_FIRST" : wr_mode <= 2'b01; + "NO_CHANGE" : wr_mode <= 2'b10; + default : begin + $display("Attribute Syntax Error : The Attribute WRITE_MODE on RAMB16_S1 instance %m is set to %s. Legal values for this attribute are WRITE_FIRST, READ_FIRST or NO_CHANGE.", WRITE_MODE); + $finish; + end + endcase + end + + + always @(posedge clk_int) begin + + if (en_int == 1'b1) begin + + if (ssr_int == 1'b1) begin + {do_out} <= #100 SRVAL; + end + else begin + if (we_int == 1'b1) begin + if (wr_mode == 2'b00) begin + do_out <= #100 di_int; + end + else if (wr_mode == 2'b01) begin + do_out <= #100 mem[addr_int]; + end + end + else begin + do_out <= #100 mem[addr_int]; + end + end + + // memory + if (we_int == 1'b1) begin + mem[addr_int] <= di_int; + end + + end + end + + +endmodule + +`endif diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/RAMB16_S18.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/RAMB16_S18.v new file mode 100644 index 0000000..9140c80 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/RAMB16_S18.v @@ -0,0 +1,731 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/RAMB16_S18.v,v 1.6 2005/03/14 22:54:41 wloo Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2005 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / 16K-Bit Data and 2K-Bit Parity Single Port Block RAM +// /___/ /\ Filename : RAMB16_S18.v +// \ \ / \ Timestamp : Thu Mar 10 16:43:34 PST 2005 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// End Revision + +`ifdef legacy_model + +`timescale 1 ps / 1 ps + +module RAMB16_S18 (DO, DOP, ADDR, CLK, DI, DIP, EN, SSR, WE); + + parameter INIT = 18'h0; + parameter SRVAL = 18'h0; + parameter WRITE_MODE = "WRITE_FIRST"; + + parameter INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + + output [15:0] DO; + output [1:0] DOP; + reg do0_out, do1_out, do2_out, do3_out, do4_out, do5_out, do6_out, do7_out, do8_out, do9_out, do10_out, do11_out, do12_out, do13_out, do14_out, do15_out; + reg dop0_out, dop1_out; + + input [9:0] ADDR; + input [15:0] DI; + input [1:0] DIP; + input EN, CLK, WE, SSR; + + reg [18431:0] mem; + reg [8:0] count; + reg [1:0] wr_mode; + + wire [9:0] addr_int; + wire [15:0] di_int; + wire [1:0] dip_int; + wire en_int, clk_int, we_int, ssr_int; + + tri0 GSR = glbl.GSR; + + always @(GSR) + if (GSR) begin + assign do0_out = INIT[0]; + assign do1_out = INIT[1]; + assign do2_out = INIT[2]; + assign do3_out = INIT[3]; + assign do4_out = INIT[4]; + assign do5_out = INIT[5]; + assign do6_out = INIT[6]; + assign do7_out = INIT[7]; + assign do8_out = INIT[8]; + assign do9_out = INIT[9]; + assign do10_out = INIT[10]; + assign do11_out = INIT[11]; + assign do12_out = INIT[12]; + assign do13_out = INIT[13]; + assign do14_out = INIT[14]; + assign do15_out = INIT[15]; + assign dop0_out = INIT[16]; + assign dop1_out = INIT[17]; + end + else begin + deassign do0_out; + deassign do1_out; + deassign do2_out; + deassign do3_out; + deassign do4_out; + deassign do5_out; + deassign do6_out; + deassign do7_out; + deassign do8_out; + deassign do9_out; + deassign do10_out; + deassign do11_out; + deassign do12_out; + deassign do13_out; + deassign do14_out; + deassign do15_out; + deassign dop0_out; + deassign dop1_out; + end + + buf b_do_out0 (DO[0], do0_out); + buf b_do_out1 (DO[1], do1_out); + buf b_do_out2 (DO[2], do2_out); + buf b_do_out3 (DO[3], do3_out); + buf b_do_out4 (DO[4], do4_out); + buf b_do_out5 (DO[5], do5_out); + buf b_do_out6 (DO[6], do6_out); + buf b_do_out7 (DO[7], do7_out); + buf b_do_out8 (DO[8], do8_out); + buf b_do_out9 (DO[9], do9_out); + buf b_do_out10 (DO[10], do10_out); + buf b_do_out11 (DO[11], do11_out); + buf b_do_out12 (DO[12], do12_out); + buf b_do_out13 (DO[13], do13_out); + buf b_do_out14 (DO[14], do14_out); + buf b_do_out15 (DO[15], do15_out); + buf b_dop_out0 (DOP[0], dop0_out); + buf b_dop_out1 (DOP[1], dop1_out); + buf b_addr_0 (addr_int[0], ADDR[0]); + buf b_addr_1 (addr_int[1], ADDR[1]); + buf b_addr_2 (addr_int[2], ADDR[2]); + buf b_addr_3 (addr_int[3], ADDR[3]); + buf b_addr_4 (addr_int[4], ADDR[4]); + buf b_addr_5 (addr_int[5], ADDR[5]); + buf b_addr_6 (addr_int[6], ADDR[6]); + buf b_addr_7 (addr_int[7], ADDR[7]); + buf b_addr_8 (addr_int[8], ADDR[8]); + buf b_addr_9 (addr_int[9], ADDR[9]); + buf b_di_0 (di_int[0], DI[0]); + buf b_di_1 (di_int[1], DI[1]); + buf b_di_2 (di_int[2], DI[2]); + buf b_di_3 (di_int[3], DI[3]); + buf b_di_4 (di_int[4], DI[4]); + buf b_di_5 (di_int[5], DI[5]); + buf b_di_6 (di_int[6], DI[6]); + buf b_di_7 (di_int[7], DI[7]); + buf b_di_8 (di_int[8], DI[8]); + buf b_di_9 (di_int[9], DI[9]); + buf b_di_10 (di_int[10], DI[10]); + buf b_di_11 (di_int[11], DI[11]); + buf b_di_12 (di_int[12], DI[12]); + buf b_di_13 (di_int[13], DI[13]); + buf b_di_14 (di_int[14], DI[14]); + buf b_di_15 (di_int[15], DI[15]); + buf b_dip_0 (dip_int[0], DIP[0]); + buf b_dip_1 (dip_int[1], DIP[1]); + buf b_en (en_int, EN); + buf b_clk (clk_int, CLK); + buf b_we (we_int, WE); + buf b_ssr (ssr_int, SSR); + + initial begin + for (count = 0; count < 256; count = count + 1) begin + mem[count] <= INIT_00[count]; + mem[256 * 1 + count] <= INIT_01[count]; + mem[256 * 2 + count] <= INIT_02[count]; + mem[256 * 3 + count] <= INIT_03[count]; + mem[256 * 4 + count] <= INIT_04[count]; + mem[256 * 5 + count] <= INIT_05[count]; + mem[256 * 6 + count] <= INIT_06[count]; + mem[256 * 7 + count] <= INIT_07[count]; + mem[256 * 8 + count] <= INIT_08[count]; + mem[256 * 9 + count] <= INIT_09[count]; + mem[256 * 10 + count] <= INIT_0A[count]; + mem[256 * 11 + count] <= INIT_0B[count]; + mem[256 * 12 + count] <= INIT_0C[count]; + mem[256 * 13 + count] <= INIT_0D[count]; + mem[256 * 14 + count] <= INIT_0E[count]; + mem[256 * 15 + count] <= INIT_0F[count]; + mem[256 * 16 + count] <= INIT_10[count]; + mem[256 * 17 + count] <= INIT_11[count]; + mem[256 * 18 + count] <= INIT_12[count]; + mem[256 * 19 + count] <= INIT_13[count]; + mem[256 * 20 + count] <= INIT_14[count]; + mem[256 * 21 + count] <= INIT_15[count]; + mem[256 * 22 + count] <= INIT_16[count]; + mem[256 * 23 + count] <= INIT_17[count]; + mem[256 * 24 + count] <= INIT_18[count]; + mem[256 * 25 + count] <= INIT_19[count]; + mem[256 * 26 + count] <= INIT_1A[count]; + mem[256 * 27 + count] <= INIT_1B[count]; + mem[256 * 28 + count] <= INIT_1C[count]; + mem[256 * 29 + count] <= INIT_1D[count]; + mem[256 * 30 + count] <= INIT_1E[count]; + mem[256 * 31 + count] <= INIT_1F[count]; + mem[256 * 32 + count] <= INIT_20[count]; + mem[256 * 33 + count] <= INIT_21[count]; + mem[256 * 34 + count] <= INIT_22[count]; + mem[256 * 35 + count] <= INIT_23[count]; + mem[256 * 36 + count] <= INIT_24[count]; + mem[256 * 37 + count] <= INIT_25[count]; + mem[256 * 38 + count] <= INIT_26[count]; + mem[256 * 39 + count] <= INIT_27[count]; + mem[256 * 40 + count] <= INIT_28[count]; + mem[256 * 41 + count] <= INIT_29[count]; + mem[256 * 42 + count] <= INIT_2A[count]; + mem[256 * 43 + count] <= INIT_2B[count]; + mem[256 * 44 + count] <= INIT_2C[count]; + mem[256 * 45 + count] <= INIT_2D[count]; + mem[256 * 46 + count] <= INIT_2E[count]; + mem[256 * 47 + count] <= INIT_2F[count]; + mem[256 * 48 + count] <= INIT_30[count]; + mem[256 * 49 + count] <= INIT_31[count]; + mem[256 * 50 + count] <= INIT_32[count]; + mem[256 * 51 + count] <= INIT_33[count]; + mem[256 * 52 + count] <= INIT_34[count]; + mem[256 * 53 + count] <= INIT_35[count]; + mem[256 * 54 + count] <= INIT_36[count]; + mem[256 * 55 + count] <= INIT_37[count]; + mem[256 * 56 + count] <= INIT_38[count]; + mem[256 * 57 + count] <= INIT_39[count]; + mem[256 * 58 + count] <= INIT_3A[count]; + mem[256 * 59 + count] <= INIT_3B[count]; + mem[256 * 60 + count] <= INIT_3C[count]; + mem[256 * 61 + count] <= INIT_3D[count]; + mem[256 * 62 + count] <= INIT_3E[count]; + mem[256 * 63 + count] <= INIT_3F[count]; + mem[256 * 64 + count] <= INITP_00[count]; + mem[256 * 65 + count] <= INITP_01[count]; + mem[256 * 66 + count] <= INITP_02[count]; + mem[256 * 67 + count] <= INITP_03[count]; + mem[256 * 68 + count] <= INITP_04[count]; + mem[256 * 69 + count] <= INITP_05[count]; + mem[256 * 70 + count] <= INITP_06[count]; + mem[256 * 71 + count] <= INITP_07[count]; + end + end + + initial begin + case (WRITE_MODE) + "WRITE_FIRST" : wr_mode <= 2'b00; + "READ_FIRST" : wr_mode <= 2'b01; + "NO_CHANGE" : wr_mode <= 2'b10; + default : begin + $display("Attribute Syntax Error : The attribute WRITE_MODE on RAMB16_S18 instance %m is set to %s. The legal values for this attribute are WRITE_FIRST, READ_FIRST or NO_CHANGE.", WRITE_MODE); + $finish; + end + endcase + end + + always @(posedge clk_int) begin + if (en_int == 1'b1) begin + if (ssr_int == 1'b1) begin + do0_out <= SRVAL[0]; + do1_out <= SRVAL[1]; + do2_out <= SRVAL[2]; + do3_out <= SRVAL[3]; + do4_out <= SRVAL[4]; + do5_out <= SRVAL[5]; + do6_out <= SRVAL[6]; + do7_out <= SRVAL[7]; + do8_out <= SRVAL[8]; + do9_out <= SRVAL[9]; + do10_out <= SRVAL[10]; + do11_out <= SRVAL[11]; + do12_out <= SRVAL[12]; + do13_out <= SRVAL[13]; + do14_out <= SRVAL[14]; + do15_out <= SRVAL[15]; + dop0_out <= SRVAL[16]; + dop1_out <= SRVAL[17]; + end + else begin + if (we_int == 1'b1) begin + if (wr_mode == 2'b00) begin + do0_out <= di_int[0]; + do1_out <= di_int[1]; + do2_out <= di_int[2]; + do3_out <= di_int[3]; + do4_out <= di_int[4]; + do5_out <= di_int[5]; + do6_out <= di_int[6]; + do7_out <= di_int[7]; + do8_out <= di_int[8]; + do9_out <= di_int[9]; + do10_out <= di_int[10]; + do11_out <= di_int[11]; + do12_out <= di_int[12]; + do13_out <= di_int[13]; + do14_out <= di_int[14]; + do15_out <= di_int[15]; + dop0_out <= dip_int[0]; + dop1_out <= dip_int[1]; + end + else if (wr_mode == 2'b01) begin + do0_out <= mem[addr_int * 16 + 0]; + do1_out <= mem[addr_int * 16 + 1]; + do2_out <= mem[addr_int * 16 + 2]; + do3_out <= mem[addr_int * 16 + 3]; + do4_out <= mem[addr_int * 16 + 4]; + do5_out <= mem[addr_int * 16 + 5]; + do6_out <= mem[addr_int * 16 + 6]; + do7_out <= mem[addr_int * 16 + 7]; + do8_out <= mem[addr_int * 16 + 8]; + do9_out <= mem[addr_int * 16 + 9]; + do10_out <= mem[addr_int * 16 + 10]; + do11_out <= mem[addr_int * 16 + 11]; + do12_out <= mem[addr_int * 16 + 12]; + do13_out <= mem[addr_int * 16 + 13]; + do14_out <= mem[addr_int * 16 + 14]; + do15_out <= mem[addr_int * 16 + 15]; + dop0_out <= mem[16384 + addr_int * 2 + 0]; + dop1_out <= mem[16384 + addr_int * 2 + 1]; + end + else begin + do0_out <= do0_out; + do1_out <= do1_out; + do2_out <= do2_out; + do3_out <= do3_out; + do4_out <= do4_out; + do5_out <= do5_out; + do6_out <= do6_out; + do7_out <= do7_out; + do8_out <= do8_out; + do9_out <= do9_out; + do10_out <= do10_out; + do11_out <= do11_out; + do12_out <= do12_out; + do13_out <= do13_out; + do14_out <= do14_out; + do15_out <= do15_out; + dop0_out <= dop0_out; + dop1_out <= dop1_out; + end + end + else begin + do0_out <= mem[addr_int * 16 + 0]; + do1_out <= mem[addr_int * 16 + 1]; + do2_out <= mem[addr_int * 16 + 2]; + do3_out <= mem[addr_int * 16 + 3]; + do4_out <= mem[addr_int * 16 + 4]; + do5_out <= mem[addr_int * 16 + 5]; + do6_out <= mem[addr_int * 16 + 6]; + do7_out <= mem[addr_int * 16 + 7]; + do8_out <= mem[addr_int * 16 + 8]; + do9_out <= mem[addr_int * 16 + 9]; + do10_out <= mem[addr_int * 16 + 10]; + do11_out <= mem[addr_int * 16 + 11]; + do12_out <= mem[addr_int * 16 + 12]; + do13_out <= mem[addr_int * 16 + 13]; + do14_out <= mem[addr_int * 16 + 14]; + do15_out <= mem[addr_int * 16 + 15]; + dop0_out <= mem[16384 + addr_int * 2 + 0]; + dop1_out <= mem[16384 + addr_int * 2 + 1]; + end + end + end + end + + always @(posedge clk_int) begin + if (en_int == 1'b1 && we_int == 1'b1) begin + mem[addr_int * 16 + 0] <= di_int[0]; + mem[addr_int * 16 + 1] <= di_int[1]; + mem[addr_int * 16 + 2] <= di_int[2]; + mem[addr_int * 16 + 3] <= di_int[3]; + mem[addr_int * 16 + 4] <= di_int[4]; + mem[addr_int * 16 + 5] <= di_int[5]; + mem[addr_int * 16 + 6] <= di_int[6]; + mem[addr_int * 16 + 7] <= di_int[7]; + mem[addr_int * 16 + 8] <= di_int[8]; + mem[addr_int * 16 + 9] <= di_int[9]; + mem[addr_int * 16 + 10] <= di_int[10]; + mem[addr_int * 16 + 11] <= di_int[11]; + mem[addr_int * 16 + 12] <= di_int[12]; + mem[addr_int * 16 + 13] <= di_int[13]; + mem[addr_int * 16 + 14] <= di_int[14]; + mem[addr_int * 16 + 15] <= di_int[15]; + mem[16384 + addr_int * 2 + 0] <= dip_int[0]; + mem[16384 + addr_int * 2 + 1] <= dip_int[1]; + end + end + + specify + (CLK *> DO) = (100, 100); + (CLK *> DOP) = (100, 100); + endspecify + +endmodule + +`else + +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/RAMB16_S18.v,v 1.6 2005/03/14 22:54:41 wloo Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2005 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Timing Simulation Library Component +// / / 16K-Bit Data and 2K-Bit Parity Single Port Block RAM +// /___/ /\ Filename : RAMB16_S18.v +// \ \ / \ Timestamp : Thu Mar 10 16:44:01 PST 2005 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 03/10/05 - Initialized outputs. +// End Revision + +`timescale 1 ps/1 ps + +module RAMB16_S18 (DO, DOP, ADDR, CLK, DI, DIP, EN, SSR, WE); + + parameter INIT = 18'h0; + parameter SRVAL = 18'h0; + parameter WRITE_MODE = "WRITE_FIRST"; + + parameter INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + + output [15:0] DO; + output [1:0] DOP; + + input [9:0] ADDR; + input [15:0] DI; + input [1:0] DIP; + input EN, CLK, WE, SSR; + + reg [15:0] do_out = INIT[15:0]; + reg [1:0] dop_out = INIT[17:16]; + + reg [15:0] mem [1023:0]; + reg [1:0] memp [1023:0]; + + reg [8:0] count, countp; + reg [1:0] wr_mode; + + wire [9:0] addr_int; + wire [15:0] di_int; + wire [1:0] dip_int; + wire en_int, clk_int, we_int, ssr_int; + + wire di_enable = en_int && we_int; + + tri0 GSR = glbl.GSR; + wire gsr_int; + + buf b_gsr (gsr_int, GSR); + + buf b_do [15:0] (DO, do_out); + buf b_dop [1:0] (DOP, dop_out); + buf b_addr [9:0] (addr_int, ADDR); + buf b_di [15:0] (di_int, DI); + buf b_dip [1:0] (dip_int, DIP); + buf b_en (en_int, EN); + buf b_clk (clk_int, CLK); + buf b_ssr (ssr_int, SSR); + buf b_we (we_int, WE); + + + always @(gsr_int) + if (gsr_int) begin + assign {dop_out, do_out} = INIT; + end + else begin + deassign do_out; + deassign dop_out; + end + + + initial begin + + for (count = 0; count < 16; count = count + 1) begin + mem[count] = INIT_00[(count * 16) +: 16]; + mem[16 * 1 + count] = INIT_01[(count * 16) +: 16]; + mem[16 * 2 + count] = INIT_02[(count * 16) +: 16]; + mem[16 * 3 + count] = INIT_03[(count * 16) +: 16]; + mem[16 * 4 + count] = INIT_04[(count * 16) +: 16]; + mem[16 * 5 + count] = INIT_05[(count * 16) +: 16]; + mem[16 * 6 + count] = INIT_06[(count * 16) +: 16]; + mem[16 * 7 + count] = INIT_07[(count * 16) +: 16]; + mem[16 * 8 + count] = INIT_08[(count * 16) +: 16]; + mem[16 * 9 + count] = INIT_09[(count * 16) +: 16]; + mem[16 * 10 + count] = INIT_0A[(count * 16) +: 16]; + mem[16 * 11 + count] = INIT_0B[(count * 16) +: 16]; + mem[16 * 12 + count] = INIT_0C[(count * 16) +: 16]; + mem[16 * 13 + count] = INIT_0D[(count * 16) +: 16]; + mem[16 * 14 + count] = INIT_0E[(count * 16) +: 16]; + mem[16 * 15 + count] = INIT_0F[(count * 16) +: 16]; + mem[16 * 16 + count] = INIT_10[(count * 16) +: 16]; + mem[16 * 17 + count] = INIT_11[(count * 16) +: 16]; + mem[16 * 18 + count] = INIT_12[(count * 16) +: 16]; + mem[16 * 19 + count] = INIT_13[(count * 16) +: 16]; + mem[16 * 20 + count] = INIT_14[(count * 16) +: 16]; + mem[16 * 21 + count] = INIT_15[(count * 16) +: 16]; + mem[16 * 22 + count] = INIT_16[(count * 16) +: 16]; + mem[16 * 23 + count] = INIT_17[(count * 16) +: 16]; + mem[16 * 24 + count] = INIT_18[(count * 16) +: 16]; + mem[16 * 25 + count] = INIT_19[(count * 16) +: 16]; + mem[16 * 26 + count] = INIT_1A[(count * 16) +: 16]; + mem[16 * 27 + count] = INIT_1B[(count * 16) +: 16]; + mem[16 * 28 + count] = INIT_1C[(count * 16) +: 16]; + mem[16 * 29 + count] = INIT_1D[(count * 16) +: 16]; + mem[16 * 30 + count] = INIT_1E[(count * 16) +: 16]; + mem[16 * 31 + count] = INIT_1F[(count * 16) +: 16]; + mem[16 * 32 + count] = INIT_20[(count * 16) +: 16]; + mem[16 * 33 + count] = INIT_21[(count * 16) +: 16]; + mem[16 * 34 + count] = INIT_22[(count * 16) +: 16]; + mem[16 * 35 + count] = INIT_23[(count * 16) +: 16]; + mem[16 * 36 + count] = INIT_24[(count * 16) +: 16]; + mem[16 * 37 + count] = INIT_25[(count * 16) +: 16]; + mem[16 * 38 + count] = INIT_26[(count * 16) +: 16]; + mem[16 * 39 + count] = INIT_27[(count * 16) +: 16]; + mem[16 * 40 + count] = INIT_28[(count * 16) +: 16]; + mem[16 * 41 + count] = INIT_29[(count * 16) +: 16]; + mem[16 * 42 + count] = INIT_2A[(count * 16) +: 16]; + mem[16 * 43 + count] = INIT_2B[(count * 16) +: 16]; + mem[16 * 44 + count] = INIT_2C[(count * 16) +: 16]; + mem[16 * 45 + count] = INIT_2D[(count * 16) +: 16]; + mem[16 * 46 + count] = INIT_2E[(count * 16) +: 16]; + mem[16 * 47 + count] = INIT_2F[(count * 16) +: 16]; + mem[16 * 48 + count] = INIT_30[(count * 16) +: 16]; + mem[16 * 49 + count] = INIT_31[(count * 16) +: 16]; + mem[16 * 50 + count] = INIT_32[(count * 16) +: 16]; + mem[16 * 51 + count] = INIT_33[(count * 16) +: 16]; + mem[16 * 52 + count] = INIT_34[(count * 16) +: 16]; + mem[16 * 53 + count] = INIT_35[(count * 16) +: 16]; + mem[16 * 54 + count] = INIT_36[(count * 16) +: 16]; + mem[16 * 55 + count] = INIT_37[(count * 16) +: 16]; + mem[16 * 56 + count] = INIT_38[(count * 16) +: 16]; + mem[16 * 57 + count] = INIT_39[(count * 16) +: 16]; + mem[16 * 58 + count] = INIT_3A[(count * 16) +: 16]; + mem[16 * 59 + count] = INIT_3B[(count * 16) +: 16]; + mem[16 * 60 + count] = INIT_3C[(count * 16) +: 16]; + mem[16 * 61 + count] = INIT_3D[(count * 16) +: 16]; + mem[16 * 62 + count] = INIT_3E[(count * 16) +: 16]; + mem[16 * 63 + count] = INIT_3F[(count * 16) +: 16]; + end + +// initiate parity start + for (countp = 0; countp < 128; countp = countp + 1) begin + memp[countp] = INITP_00[(countp * 2) +: 2]; + memp[128 * 1 + countp] = INITP_01[(countp * 2) +: 2]; + memp[128 * 2 + countp] = INITP_02[(countp * 2) +: 2]; + memp[128 * 3 + countp] = INITP_03[(countp * 2) +: 2]; + memp[128 * 4 + countp] = INITP_04[(countp * 2) +: 2]; + memp[128 * 5 + countp] = INITP_05[(countp * 2) +: 2]; + memp[128 * 6 + countp] = INITP_06[(countp * 2) +: 2]; + memp[128 * 7 + countp] = INITP_07[(countp * 2) +: 2]; + end +// initiate parity end + end // initial begin + + + initial begin + case (WRITE_MODE) + "WRITE_FIRST" : wr_mode <= 2'b00; + "READ_FIRST" : wr_mode <= 2'b01; + "NO_CHANGE" : wr_mode <= 2'b10; + default : begin + $display("Attribute Syntax Error : The Attribute WRITE_MODE on RAMB16_S18 instance %m is set to %s. Legal values for this attribute are WRITE_FIRST, READ_FIRST or NO_CHANGE.", WRITE_MODE); + $finish; + end + endcase + end + + + always @(posedge clk_int) begin + + if (en_int == 1'b1) begin + + if (ssr_int == 1'b1) begin + {dop_out, do_out} <= #100 SRVAL; + end + else begin + if (we_int == 1'b1) begin + if (wr_mode == 2'b00) begin + do_out <= #100 di_int; + dop_out <= #100 dip_int; + end + else if (wr_mode == 2'b01) begin + do_out <= #100 mem[addr_int]; + dop_out <= #100 memp[addr_int]; + end + end + else begin + do_out <= #100 mem[addr_int]; + dop_out <= #100 memp[addr_int]; + end + end + + // memory + if (we_int == 1'b1) begin + mem[addr_int] <= di_int; + memp[addr_int] <= dip_int; + end + + end + end + + +endmodule + +`endif diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/RAMB16_S18_S18.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/RAMB16_S18_S18.v new file mode 100644 index 0000000..d4cc13b --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/RAMB16_S18_S18.v @@ -0,0 +1,1944 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/RAMB16_S18_S18.v,v 1.10 2007/02/22 01:58:05 wloo Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2005 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / 16K-Bit Data and 2K-Bit Parity Dual Port Block RAM +// /___/ /\ Filename : RAMB16_S18_S18.v +// \ \ / \ Timestamp : Thu Mar 10 16:43:35 PST 2005 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// End Revision + +`ifdef legacy_model + +`timescale 1 ps / 1 ps + +module RAMB16_S18_S18 (DOA, DOB, DOPA, DOPB, ADDRA, ADDRB, CLKA, CLKB, DIA, DIB, DIPA, DIPB, ENA, ENB, SSRA, SSRB, WEA, WEB); + + parameter INIT_A = 18'h0; + parameter INIT_B = 18'h0; + parameter SRVAL_A = 18'h0; + parameter SRVAL_B = 18'h0; + parameter WRITE_MODE_A = "WRITE_FIRST"; + parameter WRITE_MODE_B = "WRITE_FIRST"; + parameter SIM_COLLISION_CHECK = "ALL"; + localparam SETUP_ALL = 1000; + localparam SETUP_READ_FIRST = 3000; + + parameter INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + + output [15:0] DOA; + output [1:0] DOPA; + reg [15:0] doa_out; + reg [1:0] dopa_out; + wire doa_out0, doa_out1, doa_out2, doa_out3, doa_out4, doa_out5, doa_out6, doa_out7, doa_out8, doa_out9, doa_out10, doa_out11, doa_out12, doa_out13, doa_out14, doa_out15; + wire dopa0_out, dopa1_out; + + input [9:0] ADDRA; + input [15:0] DIA; + input [1:0] DIPA; + input ENA, CLKA, WEA, SSRA; + + output [15:0] DOB; + output [1:0] DOPB; + reg [15:0] dob_out; + reg [1:0] dopb_out; + wire dob_out0, dob_out1, dob_out2, dob_out3, dob_out4, dob_out5, dob_out6, dob_out7, dob_out8, dob_out9, dob_out10, dob_out11, dob_out12, dob_out13, dob_out14, dob_out15; + wire dopb0_out, dopb1_out; + + input [9:0] ADDRB; + input [15:0] DIB; + input [1:0] DIPB; + input ENB, CLKB, WEB, SSRB; + + reg [18431:0] mem; + reg [8:0] count; + reg [1:0] wr_mode_a, wr_mode_b; + + reg [5:0] dmi, dbi; + reg [5:0] pmi, pbi; + + wire [9:0] addra_int; + reg [9:0] addra_reg; + wire [15:0] dia_int; + wire [1:0] dipa_int; + wire ena_int, clka_int, wea_int, ssra_int; + reg ena_reg, wea_reg, ssra_reg; + wire [9:0] addrb_int; + reg [9:0] addrb_reg; + wire [15:0] dib_int; + wire [1:0] dipb_int; + wire enb_int, clkb_int, web_int, ssrb_int; + reg display_flag; + reg enb_reg, web_reg, ssrb_reg; + + time time_clka, time_clkb; + time time_clka_clkb; + time time_clkb_clka; + + reg setup_all_a_b; + reg setup_all_b_a; + reg setup_zero; + reg setup_rf_a_b; + reg setup_rf_b_a; + reg [1:0] data_collision, data_collision_a_b, data_collision_b_a; + reg memory_collision, memory_collision_a_b, memory_collision_b_a; + reg address_collision, address_collision_a_b, address_collision_b_a; + reg change_clka; + reg change_clkb; + + wire [14:0] data_addra_int; + wire [14:0] data_addra_reg; + wire [14:0] data_addrb_int; + wire [14:0] data_addrb_reg; + wire [15:0] parity_addra_int; + wire [15:0] parity_addra_reg; + wire [15:0] parity_addrb_int; + wire [15:0] parity_addrb_reg; + + tri0 GSR = glbl.GSR; + + always @(GSR) + if (GSR) begin + assign doa_out = INIT_A[15:0]; + assign dopa_out = INIT_A[17:16]; + assign dob_out = INIT_B[15:0]; + assign dopb_out = INIT_B[17:16]; + end + else begin + deassign doa_out; + deassign dopa_out; + deassign dob_out; + deassign dopb_out; + end + + buf b_doa_out0 (doa_out0, doa_out[0]); + buf b_doa_out1 (doa_out1, doa_out[1]); + buf b_doa_out2 (doa_out2, doa_out[2]); + buf b_doa_out3 (doa_out3, doa_out[3]); + buf b_doa_out4 (doa_out4, doa_out[4]); + buf b_doa_out5 (doa_out5, doa_out[5]); + buf b_doa_out6 (doa_out6, doa_out[6]); + buf b_doa_out7 (doa_out7, doa_out[7]); + buf b_doa_out8 (doa_out8, doa_out[8]); + buf b_doa_out9 (doa_out9, doa_out[9]); + buf b_doa_out10 (doa_out10, doa_out[10]); + buf b_doa_out11 (doa_out11, doa_out[11]); + buf b_doa_out12 (doa_out12, doa_out[12]); + buf b_doa_out13 (doa_out13, doa_out[13]); + buf b_doa_out14 (doa_out14, doa_out[14]); + buf b_doa_out15 (doa_out15, doa_out[15]); + buf b_dopa_out0 (dopa_out0, dopa_out[0]); + buf b_dopa_out1 (dopa_out1, dopa_out[1]); + buf b_dob_out0 (dob_out0, dob_out[0]); + buf b_dob_out1 (dob_out1, dob_out[1]); + buf b_dob_out2 (dob_out2, dob_out[2]); + buf b_dob_out3 (dob_out3, dob_out[3]); + buf b_dob_out4 (dob_out4, dob_out[4]); + buf b_dob_out5 (dob_out5, dob_out[5]); + buf b_dob_out6 (dob_out6, dob_out[6]); + buf b_dob_out7 (dob_out7, dob_out[7]); + buf b_dob_out8 (dob_out8, dob_out[8]); + buf b_dob_out9 (dob_out9, dob_out[9]); + buf b_dob_out10 (dob_out10, dob_out[10]); + buf b_dob_out11 (dob_out11, dob_out[11]); + buf b_dob_out12 (dob_out12, dob_out[12]); + buf b_dob_out13 (dob_out13, dob_out[13]); + buf b_dob_out14 (dob_out14, dob_out[14]); + buf b_dob_out15 (dob_out15, dob_out[15]); + buf b_dopb_out0 (dopb_out0, dopb_out[0]); + buf b_dopb_out1 (dopb_out1, dopb_out[1]); + + buf b_doa0 (DOA[0], doa_out0); + buf b_doa1 (DOA[1], doa_out1); + buf b_doa2 (DOA[2], doa_out2); + buf b_doa3 (DOA[3], doa_out3); + buf b_doa4 (DOA[4], doa_out4); + buf b_doa5 (DOA[5], doa_out5); + buf b_doa6 (DOA[6], doa_out6); + buf b_doa7 (DOA[7], doa_out7); + buf b_doa8 (DOA[8], doa_out8); + buf b_doa9 (DOA[9], doa_out9); + buf b_doa10 (DOA[10], doa_out10); + buf b_doa11 (DOA[11], doa_out11); + buf b_doa12 (DOA[12], doa_out12); + buf b_doa13 (DOA[13], doa_out13); + buf b_doa14 (DOA[14], doa_out14); + buf b_doa15 (DOA[15], doa_out15); + buf b_dopa0 (DOPA[0], dopa_out0); + buf b_dopa1 (DOPA[1], dopa_out1); + buf b_dob0 (DOB[0], dob_out0); + buf b_dob1 (DOB[1], dob_out1); + buf b_dob2 (DOB[2], dob_out2); + buf b_dob3 (DOB[3], dob_out3); + buf b_dob4 (DOB[4], dob_out4); + buf b_dob5 (DOB[5], dob_out5); + buf b_dob6 (DOB[6], dob_out6); + buf b_dob7 (DOB[7], dob_out7); + buf b_dob8 (DOB[8], dob_out8); + buf b_dob9 (DOB[9], dob_out9); + buf b_dob10 (DOB[10], dob_out10); + buf b_dob11 (DOB[11], dob_out11); + buf b_dob12 (DOB[12], dob_out12); + buf b_dob13 (DOB[13], dob_out13); + buf b_dob14 (DOB[14], dob_out14); + buf b_dob15 (DOB[15], dob_out15); + buf b_dopb0 (DOPB[0], dopb_out0); + buf b_dopb1 (DOPB[1], dopb_out1); + + buf b_addra_0 (addra_int[0], ADDRA[0]); + buf b_addra_1 (addra_int[1], ADDRA[1]); + buf b_addra_2 (addra_int[2], ADDRA[2]); + buf b_addra_3 (addra_int[3], ADDRA[3]); + buf b_addra_4 (addra_int[4], ADDRA[4]); + buf b_addra_5 (addra_int[5], ADDRA[5]); + buf b_addra_6 (addra_int[6], ADDRA[6]); + buf b_addra_7 (addra_int[7], ADDRA[7]); + buf b_addra_8 (addra_int[8], ADDRA[8]); + buf b_addra_9 (addra_int[9], ADDRA[9]); + buf b_dia_0 (dia_int[0], DIA[0]); + buf b_dia_1 (dia_int[1], DIA[1]); + buf b_dia_2 (dia_int[2], DIA[2]); + buf b_dia_3 (dia_int[3], DIA[3]); + buf b_dia_4 (dia_int[4], DIA[4]); + buf b_dia_5 (dia_int[5], DIA[5]); + buf b_dia_6 (dia_int[6], DIA[6]); + buf b_dia_7 (dia_int[7], DIA[7]); + buf b_dia_8 (dia_int[8], DIA[8]); + buf b_dia_9 (dia_int[9], DIA[9]); + buf b_dia_10 (dia_int[10], DIA[10]); + buf b_dia_11 (dia_int[11], DIA[11]); + buf b_dia_12 (dia_int[12], DIA[12]); + buf b_dia_13 (dia_int[13], DIA[13]); + buf b_dia_14 (dia_int[14], DIA[14]); + buf b_dia_15 (dia_int[15], DIA[15]); + buf b_dipa_0 (dipa_int[0], DIPA[0]); + buf b_dipa_1 (dipa_int[1], DIPA[1]); + buf b_ena (ena_int, ENA); + buf b_clka (clka_int, CLKA); + buf b_ssra (ssra_int, SSRA); + buf b_wea (wea_int, WEA); + buf b_addrb_0 (addrb_int[0], ADDRB[0]); + buf b_addrb_1 (addrb_int[1], ADDRB[1]); + buf b_addrb_2 (addrb_int[2], ADDRB[2]); + buf b_addrb_3 (addrb_int[3], ADDRB[3]); + buf b_addrb_4 (addrb_int[4], ADDRB[4]); + buf b_addrb_5 (addrb_int[5], ADDRB[5]); + buf b_addrb_6 (addrb_int[6], ADDRB[6]); + buf b_addrb_7 (addrb_int[7], ADDRB[7]); + buf b_addrb_8 (addrb_int[8], ADDRB[8]); + buf b_addrb_9 (addrb_int[9], ADDRB[9]); + buf b_dib_0 (dib_int[0], DIB[0]); + buf b_dib_1 (dib_int[1], DIB[1]); + buf b_dib_2 (dib_int[2], DIB[2]); + buf b_dib_3 (dib_int[3], DIB[3]); + buf b_dib_4 (dib_int[4], DIB[4]); + buf b_dib_5 (dib_int[5], DIB[5]); + buf b_dib_6 (dib_int[6], DIB[6]); + buf b_dib_7 (dib_int[7], DIB[7]); + buf b_dib_8 (dib_int[8], DIB[8]); + buf b_dib_9 (dib_int[9], DIB[9]); + buf b_dib_10 (dib_int[10], DIB[10]); + buf b_dib_11 (dib_int[11], DIB[11]); + buf b_dib_12 (dib_int[12], DIB[12]); + buf b_dib_13 (dib_int[13], DIB[13]); + buf b_dib_14 (dib_int[14], DIB[14]); + buf b_dib_15 (dib_int[15], DIB[15]); + buf b_dipb_0 (dipb_int[0], DIPB[0]); + buf b_dipb_1 (dipb_int[1], DIPB[1]); + buf b_enb (enb_int, ENB); + buf b_clkb (clkb_int, CLKB); + buf b_ssrb (ssrb_int, SSRB); + buf b_web (web_int, WEB); + + initial begin + for (count = 0; count < 256; count = count + 1) begin + mem[count] <= INIT_00[count]; + mem[256 * 1 + count] <= INIT_01[count]; + mem[256 * 2 + count] <= INIT_02[count]; + mem[256 * 3 + count] <= INIT_03[count]; + mem[256 * 4 + count] <= INIT_04[count]; + mem[256 * 5 + count] <= INIT_05[count]; + mem[256 * 6 + count] <= INIT_06[count]; + mem[256 * 7 + count] <= INIT_07[count]; + mem[256 * 8 + count] <= INIT_08[count]; + mem[256 * 9 + count] <= INIT_09[count]; + mem[256 * 10 + count] <= INIT_0A[count]; + mem[256 * 11 + count] <= INIT_0B[count]; + mem[256 * 12 + count] <= INIT_0C[count]; + mem[256 * 13 + count] <= INIT_0D[count]; + mem[256 * 14 + count] <= INIT_0E[count]; + mem[256 * 15 + count] <= INIT_0F[count]; + mem[256 * 16 + count] <= INIT_10[count]; + mem[256 * 17 + count] <= INIT_11[count]; + mem[256 * 18 + count] <= INIT_12[count]; + mem[256 * 19 + count] <= INIT_13[count]; + mem[256 * 20 + count] <= INIT_14[count]; + mem[256 * 21 + count] <= INIT_15[count]; + mem[256 * 22 + count] <= INIT_16[count]; + mem[256 * 23 + count] <= INIT_17[count]; + mem[256 * 24 + count] <= INIT_18[count]; + mem[256 * 25 + count] <= INIT_19[count]; + mem[256 * 26 + count] <= INIT_1A[count]; + mem[256 * 27 + count] <= INIT_1B[count]; + mem[256 * 28 + count] <= INIT_1C[count]; + mem[256 * 29 + count] <= INIT_1D[count]; + mem[256 * 30 + count] <= INIT_1E[count]; + mem[256 * 31 + count] <= INIT_1F[count]; + mem[256 * 32 + count] <= INIT_20[count]; + mem[256 * 33 + count] <= INIT_21[count]; + mem[256 * 34 + count] <= INIT_22[count]; + mem[256 * 35 + count] <= INIT_23[count]; + mem[256 * 36 + count] <= INIT_24[count]; + mem[256 * 37 + count] <= INIT_25[count]; + mem[256 * 38 + count] <= INIT_26[count]; + mem[256 * 39 + count] <= INIT_27[count]; + mem[256 * 40 + count] <= INIT_28[count]; + mem[256 * 41 + count] <= INIT_29[count]; + mem[256 * 42 + count] <= INIT_2A[count]; + mem[256 * 43 + count] <= INIT_2B[count]; + mem[256 * 44 + count] <= INIT_2C[count]; + mem[256 * 45 + count] <= INIT_2D[count]; + mem[256 * 46 + count] <= INIT_2E[count]; + mem[256 * 47 + count] <= INIT_2F[count]; + mem[256 * 48 + count] <= INIT_30[count]; + mem[256 * 49 + count] <= INIT_31[count]; + mem[256 * 50 + count] <= INIT_32[count]; + mem[256 * 51 + count] <= INIT_33[count]; + mem[256 * 52 + count] <= INIT_34[count]; + mem[256 * 53 + count] <= INIT_35[count]; + mem[256 * 54 + count] <= INIT_36[count]; + mem[256 * 55 + count] <= INIT_37[count]; + mem[256 * 56 + count] <= INIT_38[count]; + mem[256 * 57 + count] <= INIT_39[count]; + mem[256 * 58 + count] <= INIT_3A[count]; + mem[256 * 59 + count] <= INIT_3B[count]; + mem[256 * 60 + count] <= INIT_3C[count]; + mem[256 * 61 + count] <= INIT_3D[count]; + mem[256 * 62 + count] <= INIT_3E[count]; + mem[256 * 63 + count] <= INIT_3F[count]; + mem[256 * 64 + count] <= INITP_00[count]; + mem[256 * 65 + count] <= INITP_01[count]; + mem[256 * 66 + count] <= INITP_02[count]; + mem[256 * 67 + count] <= INITP_03[count]; + mem[256 * 68 + count] <= INITP_04[count]; + mem[256 * 69 + count] <= INITP_05[count]; + mem[256 * 70 + count] <= INITP_06[count]; + mem[256 * 71 + count] <= INITP_07[count]; + end + address_collision <= 0; + address_collision_a_b <= 0; + address_collision_b_a <= 0; + change_clka <= 0; + change_clkb <= 0; + data_collision <= 0; + data_collision_a_b <= 0; + data_collision_b_a <= 0; + memory_collision <= 0; + memory_collision_a_b <= 0; + memory_collision_b_a <= 0; + setup_all_a_b <= 0; + setup_all_b_a <= 0; + setup_zero <= 0; + setup_rf_a_b <= 0; + setup_rf_b_a <= 0; + end + + assign data_addra_int = addra_int * 16; + assign data_addra_reg = addra_reg * 16; + assign data_addrb_int = addrb_int * 16; + assign data_addrb_reg = addrb_reg * 16; + assign parity_addra_int = 16384 + addra_int * 2; + assign parity_addra_reg = 16384 + addra_reg * 2; + assign parity_addrb_int = 16384 + addrb_int * 2; + assign parity_addrb_reg = 16384 + addrb_reg * 2; + + + initial begin + + display_flag = 1; + + case (SIM_COLLISION_CHECK) + + "NONE" : begin + assign setup_all_a_b = 1'b0; + assign setup_all_b_a = 1'b0; + assign setup_zero = 1'b0; + assign setup_rf_a_b = 1'b0; + assign setup_rf_b_a = 1'b0; + assign display_flag = 0; + end + "WARNING_ONLY" : begin + assign data_collision = 2'b00; + assign data_collision_a_b = 2'b00; + assign data_collision_b_a = 2'b00; + assign memory_collision = 1'b0; + assign memory_collision_a_b = 1'b0; + assign memory_collision_b_a = 1'b0; + end + "GENERATE_X_ONLY" : begin + assign display_flag = 0; + end + "ALL" : ; + default : begin + $display("Attribute Syntax Error : The Attribute SIM_COLLISION_CHECK on RAMB16_S18_S18 instance %m is set to %s. Legal values for this attribute are ALL, NONE, WARNING_ONLY or GENERATE_X_ONLY.", SIM_COLLISION_CHECK); + $finish; + end + + endcase // case(SIM_COLLISION_CHECK) + + end // initial begin + + + always @(posedge clka_int) begin + time_clka = $time; + #0 time_clkb_clka = time_clka - time_clkb; + change_clka = ~change_clka; + end + + always @(posedge clkb_int) begin + time_clkb = $time; + #0 time_clka_clkb = time_clkb - time_clka; + change_clkb = ~change_clkb; + end + + always @(change_clkb) begin + if ((0 < time_clka_clkb) && (time_clka_clkb < SETUP_ALL)) + setup_all_a_b = 1; + if ((0 < time_clka_clkb) && (time_clka_clkb < SETUP_READ_FIRST)) + setup_rf_a_b = 1; + end + + always @(change_clka) begin + if ((0 < time_clkb_clka) && (time_clkb_clka < SETUP_ALL)) + setup_all_b_a = 1; + if ((0 < time_clkb_clka) && (time_clkb_clka < SETUP_READ_FIRST)) + setup_rf_b_a = 1; + end + + always @(change_clkb or change_clka) begin + if ((time_clkb_clka == 0) && (time_clka_clkb == 0)) + setup_zero = 1; + end + + always @(posedge setup_zero) begin + if ((ena_int == 1) && (wea_int == 1) && + (enb_int == 1) && (web_int == 1) && + (data_addra_int[14:4] == data_addrb_int[14:4])) + memory_collision <= 1; + end + + always @(posedge setup_all_a_b or posedge setup_rf_a_b) begin + if ((ena_reg == 1) && (wea_reg == 1) && + (enb_int == 1) && (web_int == 1) && + (data_addra_reg[14:4] == data_addrb_int[14:4])) + memory_collision_a_b <= 1; + end + + always @(posedge setup_all_b_a or posedge setup_rf_b_a) begin + if ((ena_int == 1) && (wea_int == 1) && + (enb_reg == 1) && (web_reg == 1) && + (data_addra_int[14:4] == data_addrb_reg[14:4])) + memory_collision_b_a <= 1; + end + + always @(posedge setup_all_a_b) begin + if (data_addra_reg[14:4] == data_addrb_int[14:4]) begin + if ((ena_reg == 1) && (enb_int == 1)) begin + case ({wr_mode_a, wr_mode_b, wea_reg, web_int}) + 6'b000011 : begin data_collision_a_b <= 2'b11; display_wa_wb; end + 6'b000111 : begin data_collision_a_b <= 2'b11; display_wa_wb; end + 6'b001011 : begin data_collision_a_b <= 2'b10; display_wa_wb; end +// 6'b010011 : begin data_collision_a_b <= 2'b00; display_wa_wb; end +// 6'b010111 : begin data_collision_a_b <= 2'b00; display_wa_wb; end +// 6'b011011 : begin data_collision_a_b <= 2'b00; display_wa_wb; end + 6'b100011 : begin data_collision_a_b <= 2'b01; display_wa_wb; end + 6'b100111 : begin data_collision_a_b <= 2'b01; display_wa_wb; end + 6'b101011 : begin display_wa_wb; end + 6'b000001 : begin data_collision_a_b <= 2'b10; display_ra_wb; end +// 6'b000101 : begin data_collision_a_b <= 2'b00; display_ra_wb; end + 6'b001001 : begin data_collision_a_b <= 2'b10; display_ra_wb; end + 6'b010001 : begin data_collision_a_b <= 2'b10; display_ra_wb; end +// 6'b010101 : begin data_collision_a_b <= 2'b00; display_ra_wb; end + 6'b011001 : begin data_collision_a_b <= 2'b10; display_ra_wb; end + 6'b100001 : begin data_collision_a_b <= 2'b10; display_ra_wb; end +// 6'b100101 : begin data_collision_a_b <= 2'b00; display_ra_wb; end + 6'b101001 : begin data_collision_a_b <= 2'b10; display_ra_wb; end + 6'b000010 : begin data_collision_a_b <= 2'b01; display_wa_rb; end + 6'b000110 : begin data_collision_a_b <= 2'b01; display_wa_rb; end + 6'b001010 : begin data_collision_a_b <= 2'b01; display_wa_rb; end +// 6'b010010 : begin data_collision_a_b <= 2'b00; display_wa_rb; end +// 6'b010110 : begin data_collision_a_b <= 2'b00; display_wa_rb; end +// 6'b011010 : begin data_collision_a_b <= 2'b00; display_wa_rb; end + 6'b100010 : begin data_collision_a_b <= 2'b01; display_wa_rb; end + 6'b100110 : begin data_collision_a_b <= 2'b01; display_wa_rb; end + 6'b101010 : begin data_collision_a_b <= 2'b01; display_wa_rb; end + endcase + end + end + setup_all_a_b <= 0; + end + + + always @(posedge setup_all_b_a) begin + if (data_addra_int[14:4] == data_addrb_reg[14:4]) begin + if ((ena_int == 1) && (enb_reg == 1)) begin + case ({wr_mode_a, wr_mode_b, wea_int, web_reg}) + 6'b000011 : begin data_collision_b_a <= 2'b11; display_wa_wb; end +// 6'b000111 : begin data_collision_b_a <= 2'b00; display_wa_wb; end + 6'b001011 : begin data_collision_b_a <= 2'b10; display_wa_wb; end + 6'b010011 : begin data_collision_b_a <= 2'b11; display_wa_wb; end +// 6'b010111 : begin data_collision_b_a <= 2'b00; display_wa_wb; end + 6'b011011 : begin data_collision_b_a <= 2'b10; display_wa_wb; end + 6'b100011 : begin data_collision_b_a <= 2'b01; display_wa_wb; end + 6'b100111 : begin data_collision_b_a <= 2'b01; display_wa_wb; end + 6'b101011 : begin display_wa_wb; end + 6'b000001 : begin data_collision_b_a <= 2'b10; display_ra_wb; end + 6'b000101 : begin data_collision_b_a <= 2'b10; display_ra_wb; end + 6'b001001 : begin data_collision_b_a <= 2'b10; display_ra_wb; end + 6'b010001 : begin data_collision_b_a <= 2'b10; display_ra_wb; end + 6'b010101 : begin data_collision_b_a <= 2'b10; display_ra_wb; end + 6'b011001 : begin data_collision_b_a <= 2'b10; display_ra_wb; end + 6'b100001 : begin data_collision_b_a <= 2'b10; display_ra_wb; end + 6'b100101 : begin data_collision_b_a <= 2'b10; display_ra_wb; end + 6'b101001 : begin data_collision_b_a <= 2'b10; display_ra_wb; end + 6'b000010 : begin data_collision_b_a <= 2'b01; display_wa_rb; end + 6'b000110 : begin data_collision_b_a <= 2'b01; display_wa_rb; end + 6'b001010 : begin data_collision_b_a <= 2'b01; display_wa_rb; end +// 6'b010010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end +// 6'b010110 : begin data_collision_b_a <= 2'b00; display_wa_rb; end +// 6'b011010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end + 6'b100010 : begin data_collision_b_a <= 2'b01; display_wa_rb; end + 6'b100110 : begin data_collision_b_a <= 2'b01; display_wa_rb; end + 6'b101010 : begin data_collision_b_a <= 2'b01; display_wa_rb; end + endcase + end + end + setup_all_b_a <= 0; + end + + + always @(posedge setup_zero) begin + if (data_addra_int[14:4] == data_addrb_int[14:4]) begin + if ((ena_int == 1) && (enb_int == 1)) begin + case ({wr_mode_a, wr_mode_b, wea_int, web_int}) + 6'b000011 : begin data_collision <= 2'b11; display_wa_wb; end + 6'b000111 : begin data_collision <= 2'b11; display_wa_wb; end + 6'b001011 : begin data_collision <= 2'b10; display_wa_wb; end + 6'b010011 : begin data_collision <= 2'b11; display_wa_wb; end + 6'b010111 : begin data_collision <= 2'b11; display_wa_wb; end + 6'b011011 : begin data_collision <= 2'b10; display_wa_wb; end + 6'b100011 : begin data_collision <= 2'b01; display_wa_wb; end + 6'b100111 : begin data_collision <= 2'b01; display_wa_wb; end + 6'b101011 : begin display_wa_wb; end + 6'b000001 : begin data_collision <= 2'b10; display_ra_wb; end +// 6'b000101 : begin data_collision <= 2'b00; display_ra_wb; end + 6'b001001 : begin data_collision <= 2'b10; display_ra_wb; end + 6'b010001 : begin data_collision <= 2'b10; display_ra_wb; end +// 6'b010101 : begin data_collision <= 2'b00; display_ra_wb; end + 6'b011001 : begin data_collision <= 2'b10; display_ra_wb; end + 6'b100001 : begin data_collision <= 2'b10; display_ra_wb; end +// 6'b100101 : begin data_collision <= 2'b00; display_ra_wb; end + 6'b101001 : begin data_collision <= 2'b10; display_ra_wb; end + 6'b000010 : begin data_collision <= 2'b01; display_wa_rb; end + 6'b000110 : begin data_collision <= 2'b01; display_wa_rb; end + 6'b001010 : begin data_collision <= 2'b01; display_wa_rb; end +// 6'b010010 : begin data_collision <= 2'b00; display_wa_rb; end +// 6'b010110 : begin data_collision <= 2'b00; display_wa_rb; end +// 6'b011010 : begin data_collision <= 2'b00; display_wa_rb; end + 6'b100010 : begin data_collision <= 2'b01; display_wa_rb; end + 6'b100110 : begin data_collision <= 2'b01; display_wa_rb; end + 6'b101010 : begin data_collision <= 2'b01; display_wa_rb; end + endcase + end + end + setup_zero <= 0; + end + + task display_ra_wb; + begin + if (display_flag) + $display("Memory Collision Error on RAMB16_S18_S18:%m at simulation time %.3f ns\nA read was performed on address %h (hex) of Port A while a write was requested to the same address on Port B. The write will be successful however the read value on Port A is unknown until the next CLKA cycle.", $time/1000.0, addra_int); + end + endtask + + task display_wa_rb; + begin + if (display_flag) + $display("Memory Collision Error on RAMB16_S18_S18:%m at simulation time %.3f ns\nA read was performed on address %h (hex) of Port B while a write was requested to the same address on Port A. The write will be successful however the read value on Port B is unknown until the next CLKB cycle.", $time/1000.0, addrb_int); + end + endtask + + task display_wa_wb; + begin + if (display_flag) + $display("Memory Collision Error on RAMB16_S18_S18:%m at simulation time %.3f ns\nA write was requested to the same address simultaneously at both Port A and Port B of the RAM. The contents written to the RAM at address location %h (hex) of Port A and address location %h (hex) of Port B are unknown.", $time/1000.0, addra_int, addrb_int); + end + endtask + + + always @(posedge setup_rf_a_b) begin + if (data_addra_reg[14:4] == data_addrb_int[14:4]) begin + if ((ena_reg == 1) && (enb_int == 1)) begin + case ({wr_mode_a, wr_mode_b, wea_reg, web_int}) +// 6'b000011 : begin data_collision_a_b <= 2'b00; display_wa_wb; end +// 6'b000111 : begin data_collision_a_b <= 2'b00; display_wa_wb; end +// 6'b001011 : begin data_collision_a_b <= 2'b00; display_wa_wb; end + 6'b010011 : begin data_collision_a_b <= 2'b11; display_wa_wb; end + 6'b010111 : begin data_collision_a_b <= 2'b11; display_wa_wb; end + 6'b011011 : begin data_collision_a_b <= 2'b10; display_wa_wb; end +// 6'b100011 : begin data_collision_a_b <= 2'b00; display_wa_wb; end +// 6'b100111 : begin data_collision_a_b <= 2'b00; display_wa_wb; end +// 6'b101011 : begin data_collision_a_b <= 2'b00; display_wa_wb; end +// 6'b000001 : begin data_collision_a_b <= 2'b00; display_ra_wb; end +// 6'b000101 : begin data_collision_a_b <= 2'b00; display_ra_wb; end +// 6'b001001 : begin data_collision_a_b <= 2'b00; display_ra_wb; end +// 6'b010001 : begin data_collision_a_b <= 2'b00; display_ra_wb; end +// 6'b010101 : begin data_collision_a_b <= 2'b00; display_ra_wb; end +// 6'b011001 : begin data_collision_a_b <= 2'b00; display_ra_wb; end +// 6'b100001 : begin data_collision_a_b <= 2'b00; display_ra_wb; end +// 6'b100101 : begin data_collision_a_b <= 2'b00; display_ra_wb; end +// 6'b101001 : begin data_collision_a_b <= 2'b00; display_ra_wb; end +// 6'b000010 : begin data_collision_a_b <= 2'b00; display_wa_rb; end +// 6'b000110 : begin data_collision_a_b <= 2'b00; display_wa_rb; end +// 6'b001010 : begin data_collision_a_b <= 2'b00; display_wa_rb; end + 6'b010010 : begin data_collision_a_b <= 2'b01; display_wa_rb; end + 6'b010110 : begin data_collision_a_b <= 2'b01; display_wa_rb; end + 6'b011010 : begin data_collision_a_b <= 2'b01; display_wa_rb; end +// 6'b100010 : begin data_collision_a_b <= 2'b00; display_wa_rb; end +// 6'b100110 : begin data_collision_a_b <= 2'b00; display_wa_rb; end +// 6'b101010 : begin data_collision_a_b <= 2'b00; display_wa_rb; end + endcase + end + end + setup_rf_a_b <= 0; + end + + + always @(posedge setup_rf_b_a) begin + if (data_addra_int[14:4] == data_addrb_reg[14:4]) begin + if ((ena_int == 1) && (enb_reg == 1)) begin + case ({wr_mode_a, wr_mode_b, wea_int, web_reg}) +// 6'b000011 : begin data_collision_b_a <= 2'b00; display_wa_wb; end + 6'b000111 : begin data_collision_b_a <= 2'b11; display_wa_wb; end +// 6'b001011 : begin data_collision_b_a <= 2'b00; display_wa_wb; end +// 6'b010011 : begin data_collision_b_a <= 2'b00; display_wa_wb; end + 6'b010111 : begin data_collision_b_a <= 2'b11; display_wa_wb; end +// 6'b011011 : begin data_collision_b_a <= 2'b00; display_wa_wb; end +// 6'b100011 : begin data_collision_b_a <= 2'b00; display_wa_wb; end + 6'b100111 : begin data_collision_b_a <= 2'b01; display_wa_wb; end +// 6'b101011 : begin data_collision_b_a <= 2'b00; display_wa_wb; end +// 6'b000001 : begin data_collision_b_a <= 2'b00; display_ra_wb; end + 6'b000101 : begin data_collision_b_a <= 2'b10; display_ra_wb; end +// 6'b001001 : begin data_collision_b_a <= 2'b00; display_ra_wb; end +// 6'b010001 : begin data_collision_b_a <= 2'b00; display_ra_wb; end + 6'b010101 : begin data_collision_b_a <= 2'b10; display_ra_wb; end +// 6'b011001 : begin data_collision_b_a <= 2'b00; display_ra_wb; end +// 6'b100001 : begin data_collision_b_a <= 2'b00; display_ra_wb; end + 6'b100101 : begin data_collision_b_a <= 2'b10; display_ra_wb; end +// 6'b101001 : begin data_collision_b_a <= 2'b00; display_ra_wb; end +// 6'b000010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end +// 6'b000110 : begin data_collision_b_a <= 2'b00; display_wa_rb; end +// 6'b001010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end +// 6'b010010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end +// 6'b010110 : begin data_collision_b_a <= 2'b00; display_wa_rb; end +// 6'b011010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end +// 6'b100010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end +// 6'b100110 : begin data_collision_b_a <= 2'b00; display_wa_rb; end +// 6'b101010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end + endcase + end + end + setup_rf_b_a <= 0; + end + + + always @(posedge clka_int) begin + addra_reg <= addra_int; + ena_reg <= ena_int; + ssra_reg <= ssra_int; + wea_reg <= wea_int; + end + + always @(posedge clkb_int) begin + addrb_reg <= addrb_int; + enb_reg <= enb_int; + ssrb_reg <= ssrb_int; + web_reg <= web_int; + end + + // Data + always @(posedge memory_collision) begin + for (dmi = 0; dmi < 16; dmi = dmi + 1) begin + mem[data_addra_int + dmi] <= 1'bX; + end + memory_collision <= 0; + end + + always @(posedge memory_collision_a_b) begin + for (dmi = 0; dmi < 16; dmi = dmi + 1) begin + mem[data_addra_reg + dmi] <= 1'bX; + end + memory_collision_a_b <= 0; + end + + always @(posedge memory_collision_b_a) begin + for (dmi = 0; dmi < 16; dmi = dmi + 1) begin + mem[data_addra_int + dmi] <= 1'bX; + end + memory_collision_b_a <= 0; + end + + always @(posedge data_collision[1]) begin + if (ssra_int == 0) begin + doa_out <= 16'bX; + end + data_collision[1] <= 0; + end + + always @(posedge data_collision[0]) begin + if (ssrb_int == 0) begin + dob_out <= 16'bX; + end + data_collision[0] <= 0; + end + + always @(posedge data_collision_a_b[1]) begin + if (ssra_reg == 0) begin + doa_out <= 16'bX; + end + data_collision_a_b[1] <= 0; + end + + always @(posedge data_collision_a_b[0]) begin + if (ssrb_int == 0) begin + dob_out <= 16'bX; + end + data_collision_a_b[0] <= 0; + end + + always @(posedge data_collision_b_a[1]) begin + if (ssra_int == 0) begin + doa_out <= 16'bX; + end + data_collision_b_a[1] <= 0; + end + + always @(posedge data_collision_b_a[0]) begin + if (ssrb_reg == 0) begin + dob_out <= 16'bX; + end + data_collision_b_a[0] <= 0; + end + + + // Parity + always @(posedge memory_collision) begin + for (pmi = 0; pmi < 2; pmi = pmi + 1) begin + mem[parity_addra_int + pmi] <= 1'bX; + end + end + + always @(posedge memory_collision_a_b) begin + for (pmi = 0; pmi < 2; pmi = pmi + 1) begin + mem[parity_addra_reg + pmi] <= 1'bX; + end + end + + always @(posedge memory_collision_b_a) begin + for (pmi = 0; pmi < 2; pmi = pmi + 1) begin + mem[parity_addra_int + pmi] <= 1'bX; + end + end + + always @(posedge data_collision[1]) begin + if (ssra_int == 0) begin + dopa_out <= 2'bX; + end + end + + always @(posedge data_collision[0]) begin + if (ssrb_int == 0) begin + dopb_out <= 2'bX; + end + end + + always @(posedge data_collision_a_b[1]) begin + if (ssra_reg == 0) begin + dopa_out <= 2'bX; + end + end + + always @(posedge data_collision_a_b[0]) begin + if (ssrb_int == 0) begin + dopb_out <= 2'bX; + end + end + + always @(posedge data_collision_b_a[1]) begin + if (ssra_int == 0) begin + dopa_out <= 2'bX; + end + end + + always @(posedge data_collision_b_a[0]) begin + if (ssrb_reg == 0) begin + dopb_out <= 2'bX; + end + end + + + initial begin + case (WRITE_MODE_A) + "WRITE_FIRST" : wr_mode_a <= 2'b00; + "READ_FIRST" : wr_mode_a <= 2'b01; + "NO_CHANGE" : wr_mode_a <= 2'b10; + default : begin + $display("Attribute Syntax Error : The Attribute WRITE_MODE_A on RAMB16_S18_S18 instance %m is set to %s. Legal values for this attribute are WRITE_FIRST, READ_FIRST or NO_CHANGE.", WRITE_MODE_A); + $finish; + end + endcase + end + + initial begin + case (WRITE_MODE_B) + "WRITE_FIRST" : wr_mode_b <= 2'b00; + "READ_FIRST" : wr_mode_b <= 2'b01; + "NO_CHANGE" : wr_mode_b <= 2'b10; + default : begin + $display("Attribute Syntax Error : The Attribute WRITE_MODE_B on RAMB16_S18_S18 instance %m is set to %s. Legal values for this attribute are WRITE_FIRST, READ_FIRST or NO_CHANGE.", WRITE_MODE_B); + $finish; + end + endcase + end + + // Port A + always @(posedge clka_int) begin + if (ena_int == 1'b1) begin + if (ssra_int == 1'b1) begin + doa_out[0] <= SRVAL_A[0]; + doa_out[1] <= SRVAL_A[1]; + doa_out[2] <= SRVAL_A[2]; + doa_out[3] <= SRVAL_A[3]; + doa_out[4] <= SRVAL_A[4]; + doa_out[5] <= SRVAL_A[5]; + doa_out[6] <= SRVAL_A[6]; + doa_out[7] <= SRVAL_A[7]; + doa_out[8] <= SRVAL_A[8]; + doa_out[9] <= SRVAL_A[9]; + doa_out[10] <= SRVAL_A[10]; + doa_out[11] <= SRVAL_A[11]; + doa_out[12] <= SRVAL_A[12]; + doa_out[13] <= SRVAL_A[13]; + doa_out[14] <= SRVAL_A[14]; + doa_out[15] <= SRVAL_A[15]; + dopa_out[0] <= SRVAL_A[16]; + dopa_out[1] <= SRVAL_A[17]; + end + else begin + if (wea_int == 1'b1) begin + if (wr_mode_a == 2'b00) begin + doa_out <= dia_int; + dopa_out <= dipa_int; + end + else if (wr_mode_a == 2'b01) begin + doa_out[0] <= mem[data_addra_int + 0]; + doa_out[1] <= mem[data_addra_int + 1]; + doa_out[2] <= mem[data_addra_int + 2]; + doa_out[3] <= mem[data_addra_int + 3]; + doa_out[4] <= mem[data_addra_int + 4]; + doa_out[5] <= mem[data_addra_int + 5]; + doa_out[6] <= mem[data_addra_int + 6]; + doa_out[7] <= mem[data_addra_int + 7]; + doa_out[8] <= mem[data_addra_int + 8]; + doa_out[9] <= mem[data_addra_int + 9]; + doa_out[10] <= mem[data_addra_int + 10]; + doa_out[11] <= mem[data_addra_int + 11]; + doa_out[12] <= mem[data_addra_int + 12]; + doa_out[13] <= mem[data_addra_int + 13]; + doa_out[14] <= mem[data_addra_int + 14]; + doa_out[15] <= mem[data_addra_int + 15]; + dopa_out[0] <= mem[parity_addra_int + 0]; + dopa_out[1] <= mem[parity_addra_int + 1]; + end + end + else begin + doa_out[0] <= mem[data_addra_int + 0]; + doa_out[1] <= mem[data_addra_int + 1]; + doa_out[2] <= mem[data_addra_int + 2]; + doa_out[3] <= mem[data_addra_int + 3]; + doa_out[4] <= mem[data_addra_int + 4]; + doa_out[5] <= mem[data_addra_int + 5]; + doa_out[6] <= mem[data_addra_int + 6]; + doa_out[7] <= mem[data_addra_int + 7]; + doa_out[8] <= mem[data_addra_int + 8]; + doa_out[9] <= mem[data_addra_int + 9]; + doa_out[10] <= mem[data_addra_int + 10]; + doa_out[11] <= mem[data_addra_int + 11]; + doa_out[12] <= mem[data_addra_int + 12]; + doa_out[13] <= mem[data_addra_int + 13]; + doa_out[14] <= mem[data_addra_int + 14]; + doa_out[15] <= mem[data_addra_int + 15]; + dopa_out[0] <= mem[parity_addra_int + 0]; + dopa_out[1] <= mem[parity_addra_int + 1]; + end + end + end + end + + always @(posedge clka_int) begin + if (ena_int == 1'b1 && wea_int == 1'b1) begin + mem[data_addra_int + 0] <= dia_int[0]; + mem[data_addra_int + 1] <= dia_int[1]; + mem[data_addra_int + 2] <= dia_int[2]; + mem[data_addra_int + 3] <= dia_int[3]; + mem[data_addra_int + 4] <= dia_int[4]; + mem[data_addra_int + 5] <= dia_int[5]; + mem[data_addra_int + 6] <= dia_int[6]; + mem[data_addra_int + 7] <= dia_int[7]; + mem[data_addra_int + 8] <= dia_int[8]; + mem[data_addra_int + 9] <= dia_int[9]; + mem[data_addra_int + 10] <= dia_int[10]; + mem[data_addra_int + 11] <= dia_int[11]; + mem[data_addra_int + 12] <= dia_int[12]; + mem[data_addra_int + 13] <= dia_int[13]; + mem[data_addra_int + 14] <= dia_int[14]; + mem[data_addra_int + 15] <= dia_int[15]; + mem[parity_addra_int + 0] <= dipa_int[0]; + mem[parity_addra_int + 1] <= dipa_int[1]; + end + end + + // Port B + always @(posedge clkb_int) begin + if (enb_int == 1'b1) begin + if (ssrb_int == 1'b1) begin + dob_out[0] <= SRVAL_B[0]; + dob_out[1] <= SRVAL_B[1]; + dob_out[2] <= SRVAL_B[2]; + dob_out[3] <= SRVAL_B[3]; + dob_out[4] <= SRVAL_B[4]; + dob_out[5] <= SRVAL_B[5]; + dob_out[6] <= SRVAL_B[6]; + dob_out[7] <= SRVAL_B[7]; + dob_out[8] <= SRVAL_B[8]; + dob_out[9] <= SRVAL_B[9]; + dob_out[10] <= SRVAL_B[10]; + dob_out[11] <= SRVAL_B[11]; + dob_out[12] <= SRVAL_B[12]; + dob_out[13] <= SRVAL_B[13]; + dob_out[14] <= SRVAL_B[14]; + dob_out[15] <= SRVAL_B[15]; + dopb_out[0] <= SRVAL_B[16]; + dopb_out[1] <= SRVAL_B[17]; + end + else begin + if (web_int == 1'b1) begin + if (wr_mode_b == 2'b00) begin + dob_out <= dib_int; + dopb_out <= dipb_int; + end + else if (wr_mode_b == 2'b01) begin + dob_out[0] <= mem[data_addrb_int + 0]; + dob_out[1] <= mem[data_addrb_int + 1]; + dob_out[2] <= mem[data_addrb_int + 2]; + dob_out[3] <= mem[data_addrb_int + 3]; + dob_out[4] <= mem[data_addrb_int + 4]; + dob_out[5] <= mem[data_addrb_int + 5]; + dob_out[6] <= mem[data_addrb_int + 6]; + dob_out[7] <= mem[data_addrb_int + 7]; + dob_out[8] <= mem[data_addrb_int + 8]; + dob_out[9] <= mem[data_addrb_int + 9]; + dob_out[10] <= mem[data_addrb_int + 10]; + dob_out[11] <= mem[data_addrb_int + 11]; + dob_out[12] <= mem[data_addrb_int + 12]; + dob_out[13] <= mem[data_addrb_int + 13]; + dob_out[14] <= mem[data_addrb_int + 14]; + dob_out[15] <= mem[data_addrb_int + 15]; + dopb_out[0] <= mem[parity_addrb_int + 0]; + dopb_out[1] <= mem[parity_addrb_int + 1]; + end + end + else begin + dob_out[0] <= mem[data_addrb_int + 0]; + dob_out[1] <= mem[data_addrb_int + 1]; + dob_out[2] <= mem[data_addrb_int + 2]; + dob_out[3] <= mem[data_addrb_int + 3]; + dob_out[4] <= mem[data_addrb_int + 4]; + dob_out[5] <= mem[data_addrb_int + 5]; + dob_out[6] <= mem[data_addrb_int + 6]; + dob_out[7] <= mem[data_addrb_int + 7]; + dob_out[8] <= mem[data_addrb_int + 8]; + dob_out[9] <= mem[data_addrb_int + 9]; + dob_out[10] <= mem[data_addrb_int + 10]; + dob_out[11] <= mem[data_addrb_int + 11]; + dob_out[12] <= mem[data_addrb_int + 12]; + dob_out[13] <= mem[data_addrb_int + 13]; + dob_out[14] <= mem[data_addrb_int + 14]; + dob_out[15] <= mem[data_addrb_int + 15]; + dopb_out[0] <= mem[parity_addrb_int + 0]; + dopb_out[1] <= mem[parity_addrb_int + 1]; + end + end + end + end + + always @(posedge clkb_int) begin + if (enb_int == 1'b1 && web_int == 1'b1) begin + mem[data_addrb_int + 0] <= dib_int[0]; + mem[data_addrb_int + 1] <= dib_int[1]; + mem[data_addrb_int + 2] <= dib_int[2]; + mem[data_addrb_int + 3] <= dib_int[3]; + mem[data_addrb_int + 4] <= dib_int[4]; + mem[data_addrb_int + 5] <= dib_int[5]; + mem[data_addrb_int + 6] <= dib_int[6]; + mem[data_addrb_int + 7] <= dib_int[7]; + mem[data_addrb_int + 8] <= dib_int[8]; + mem[data_addrb_int + 9] <= dib_int[9]; + mem[data_addrb_int + 10] <= dib_int[10]; + mem[data_addrb_int + 11] <= dib_int[11]; + mem[data_addrb_int + 12] <= dib_int[12]; + mem[data_addrb_int + 13] <= dib_int[13]; + mem[data_addrb_int + 14] <= dib_int[14]; + mem[data_addrb_int + 15] <= dib_int[15]; + mem[parity_addrb_int + 0] <= dipb_int[0]; + mem[parity_addrb_int + 1] <= dipb_int[1]; + end + end + + specify + (CLKA *> DOA) = (100, 100); + (CLKA *> DOPA) = (100, 100); + (CLKB *> DOB) = (100, 100); + (CLKB *> DOPB) = (100, 100); + endspecify + +endmodule + +`else + +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/RAMB16_S18_S18.v,v 1.10 2007/02/22 01:58:05 wloo Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2005 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Timing Simulation Library Component +// / / 16K-Bit Data and 2K-Bit Parity Dual Port Block RAM +// /___/ /\ Filename : RAMB16_S18_S18.v +// \ \ / \ Timestamp : Thu Mar 10 16:44:01 PST 2005 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 03/10/05 - Initialized outputs. +// 02/21/07 - Fixed parameter SIM_COLLISION_CHECK (CR 433281). +// End Revision + +`timescale 1 ps/1 ps + +module RAMB16_S18_S18 (DOA, DOB, DOPA, DOPB, ADDRA, ADDRB, CLKA, CLKB, DIA, DIB, DIPA, DIPB, ENA, ENB, SSRA, SSRB, WEA, WEB); + + parameter INIT_A = 18'h0; + parameter INIT_B = 18'h0; + parameter SRVAL_A = 18'h0; + parameter SRVAL_B = 18'h0; + parameter WRITE_MODE_A = "WRITE_FIRST"; + parameter WRITE_MODE_B = "WRITE_FIRST"; + parameter SIM_COLLISION_CHECK = "ALL"; + localparam SETUP_ALL = 1000; + localparam SETUP_READ_FIRST = 3000; + + parameter INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + + output [15:0] DOA; + output [1:0] DOPA; + output [15:0] DOB; + output [1:0] DOPB; + + input [9:0] ADDRA; + input [15:0] DIA; + input [1:0] DIPA; + input ENA, CLKA, WEA, SSRA; + input [9:0] ADDRB; + input [15:0] DIB; + input [1:0] DIPB; + input ENB, CLKB, WEB, SSRB; + + reg [15:0] doa_out = INIT_A[15:0]; + reg [1:0] dopa_out = INIT_A[17:16]; + reg [15:0] dob_out = INIT_B[15:0]; + reg [1:0] dopb_out = INIT_B[17:16]; + + reg [15:0] mem [1023:0]; + reg [1:0] memp [1023:0]; + + reg [8:0] count, countp; + reg [1:0] wr_mode_a, wr_mode_b; + + reg [5:0] dmi, dbi; + reg [5:0] pmi, pbi; + + wire [9:0] addra_int; + reg [9:0] addra_reg; + wire [15:0] dia_int; + wire [1:0] dipa_int; + wire ena_int, clka_int, wea_int, ssra_int; + reg ena_reg, wea_reg, ssra_reg; + wire [9:0] addrb_int; + reg [9:0] addrb_reg; + wire [15:0] dib_int; + wire [1:0] dipb_int; + wire enb_int, clkb_int, web_int, ssrb_int; + reg display_flag, output_flag; + reg enb_reg, web_reg, ssrb_reg; + + time time_clka, time_clkb; + time time_clka_clkb; + time time_clkb_clka; + + reg setup_all_a_b; + reg setup_all_b_a; + reg setup_zero; + reg setup_rf_a_b; + reg setup_rf_b_a; + reg [1:0] data_collision, data_collision_a_b, data_collision_b_a; + reg memory_collision, memory_collision_a_b, memory_collision_b_a; + reg change_clka; + reg change_clkb; + + wire [14:0] data_addra_int; + wire [14:0] data_addra_reg; + wire [14:0] data_addrb_int; + wire [14:0] data_addrb_reg; + + wire dia_enable = ena_int && wea_int; + wire dib_enable = enb_int && web_int; + + tri0 GSR = glbl.GSR; + wire gsr_int; + + buf b_gsr (gsr_int, GSR); + + buf b_doa [15:0] (DOA, doa_out); + buf b_dopa [1:0] (DOPA, dopa_out); + buf b_addra [9:0] (addra_int, ADDRA); + buf b_dia [15:0] (dia_int, DIA); + buf b_dipa [1:0] (dipa_int, DIPA); + buf b_ena (ena_int, ENA); + buf b_clka (clka_int, CLKA); + buf b_ssra (ssra_int, SSRA); + buf b_wea (wea_int, WEA); + + buf b_dob [15:0] (DOB, dob_out); + buf b_dopb [1:0] (DOPB, dopb_out); + buf b_addrb [9:0] (addrb_int, ADDRB); + buf b_dib [15:0] (dib_int, DIB); + buf b_dipb [1:0] (dipb_int, DIPB); + buf b_enb (enb_int, ENB); + buf b_clkb (clkb_int, CLKB); + buf b_ssrb (ssrb_int, SSRB); + buf b_web (web_int, WEB); + + + always @(gsr_int) + if (gsr_int) begin + assign {dopa_out, doa_out} = INIT_A; + assign {dopb_out, dob_out} = INIT_B; + end + else begin + deassign doa_out; + deassign dopa_out; + deassign dob_out; + deassign dopb_out; + end + + + initial begin + + for (count = 0; count < 16; count = count + 1) begin + mem[count] = INIT_00[(count * 16) +: 16]; + mem[16 * 1 + count] = INIT_01[(count * 16) +: 16]; + mem[16 * 2 + count] = INIT_02[(count * 16) +: 16]; + mem[16 * 3 + count] = INIT_03[(count * 16) +: 16]; + mem[16 * 4 + count] = INIT_04[(count * 16) +: 16]; + mem[16 * 5 + count] = INIT_05[(count * 16) +: 16]; + mem[16 * 6 + count] = INIT_06[(count * 16) +: 16]; + mem[16 * 7 + count] = INIT_07[(count * 16) +: 16]; + mem[16 * 8 + count] = INIT_08[(count * 16) +: 16]; + mem[16 * 9 + count] = INIT_09[(count * 16) +: 16]; + mem[16 * 10 + count] = INIT_0A[(count * 16) +: 16]; + mem[16 * 11 + count] = INIT_0B[(count * 16) +: 16]; + mem[16 * 12 + count] = INIT_0C[(count * 16) +: 16]; + mem[16 * 13 + count] = INIT_0D[(count * 16) +: 16]; + mem[16 * 14 + count] = INIT_0E[(count * 16) +: 16]; + mem[16 * 15 + count] = INIT_0F[(count * 16) +: 16]; + mem[16 * 16 + count] = INIT_10[(count * 16) +: 16]; + mem[16 * 17 + count] = INIT_11[(count * 16) +: 16]; + mem[16 * 18 + count] = INIT_12[(count * 16) +: 16]; + mem[16 * 19 + count] = INIT_13[(count * 16) +: 16]; + mem[16 * 20 + count] = INIT_14[(count * 16) +: 16]; + mem[16 * 21 + count] = INIT_15[(count * 16) +: 16]; + mem[16 * 22 + count] = INIT_16[(count * 16) +: 16]; + mem[16 * 23 + count] = INIT_17[(count * 16) +: 16]; + mem[16 * 24 + count] = INIT_18[(count * 16) +: 16]; + mem[16 * 25 + count] = INIT_19[(count * 16) +: 16]; + mem[16 * 26 + count] = INIT_1A[(count * 16) +: 16]; + mem[16 * 27 + count] = INIT_1B[(count * 16) +: 16]; + mem[16 * 28 + count] = INIT_1C[(count * 16) +: 16]; + mem[16 * 29 + count] = INIT_1D[(count * 16) +: 16]; + mem[16 * 30 + count] = INIT_1E[(count * 16) +: 16]; + mem[16 * 31 + count] = INIT_1F[(count * 16) +: 16]; + mem[16 * 32 + count] = INIT_20[(count * 16) +: 16]; + mem[16 * 33 + count] = INIT_21[(count * 16) +: 16]; + mem[16 * 34 + count] = INIT_22[(count * 16) +: 16]; + mem[16 * 35 + count] = INIT_23[(count * 16) +: 16]; + mem[16 * 36 + count] = INIT_24[(count * 16) +: 16]; + mem[16 * 37 + count] = INIT_25[(count * 16) +: 16]; + mem[16 * 38 + count] = INIT_26[(count * 16) +: 16]; + mem[16 * 39 + count] = INIT_27[(count * 16) +: 16]; + mem[16 * 40 + count] = INIT_28[(count * 16) +: 16]; + mem[16 * 41 + count] = INIT_29[(count * 16) +: 16]; + mem[16 * 42 + count] = INIT_2A[(count * 16) +: 16]; + mem[16 * 43 + count] = INIT_2B[(count * 16) +: 16]; + mem[16 * 44 + count] = INIT_2C[(count * 16) +: 16]; + mem[16 * 45 + count] = INIT_2D[(count * 16) +: 16]; + mem[16 * 46 + count] = INIT_2E[(count * 16) +: 16]; + mem[16 * 47 + count] = INIT_2F[(count * 16) +: 16]; + mem[16 * 48 + count] = INIT_30[(count * 16) +: 16]; + mem[16 * 49 + count] = INIT_31[(count * 16) +: 16]; + mem[16 * 50 + count] = INIT_32[(count * 16) +: 16]; + mem[16 * 51 + count] = INIT_33[(count * 16) +: 16]; + mem[16 * 52 + count] = INIT_34[(count * 16) +: 16]; + mem[16 * 53 + count] = INIT_35[(count * 16) +: 16]; + mem[16 * 54 + count] = INIT_36[(count * 16) +: 16]; + mem[16 * 55 + count] = INIT_37[(count * 16) +: 16]; + mem[16 * 56 + count] = INIT_38[(count * 16) +: 16]; + mem[16 * 57 + count] = INIT_39[(count * 16) +: 16]; + mem[16 * 58 + count] = INIT_3A[(count * 16) +: 16]; + mem[16 * 59 + count] = INIT_3B[(count * 16) +: 16]; + mem[16 * 60 + count] = INIT_3C[(count * 16) +: 16]; + mem[16 * 61 + count] = INIT_3D[(count * 16) +: 16]; + mem[16 * 62 + count] = INIT_3E[(count * 16) +: 16]; + mem[16 * 63 + count] = INIT_3F[(count * 16) +: 16]; + end + +// initiate parity start + for (countp = 0; countp < 128; countp = countp + 1) begin + memp[countp] = INITP_00[(countp * 2) +: 2]; + memp[128 * 1 + countp] = INITP_01[(countp * 2) +: 2]; + memp[128 * 2 + countp] = INITP_02[(countp * 2) +: 2]; + memp[128 * 3 + countp] = INITP_03[(countp * 2) +: 2]; + memp[128 * 4 + countp] = INITP_04[(countp * 2) +: 2]; + memp[128 * 5 + countp] = INITP_05[(countp * 2) +: 2]; + memp[128 * 6 + countp] = INITP_06[(countp * 2) +: 2]; + memp[128 * 7 + countp] = INITP_07[(countp * 2) +: 2]; + end +// initiate parity end + + change_clka <= 0; + change_clkb <= 0; + data_collision <= 0; + data_collision_a_b <= 0; + data_collision_b_a <= 0; + memory_collision <= 0; + memory_collision_a_b <= 0; + memory_collision_b_a <= 0; + setup_all_a_b <= 0; + setup_all_b_a <= 0; + setup_zero <= 0; + setup_rf_a_b <= 0; + setup_rf_b_a <= 0; + end + + assign data_addra_int = addra_int * 16; + assign data_addra_reg = addra_reg * 16; + assign data_addrb_int = addrb_int * 16; + assign data_addrb_reg = addrb_reg * 16; + + + initial begin + + display_flag = 1; + output_flag = 1; + + case (SIM_COLLISION_CHECK) + + "NONE" : begin + output_flag = 0; + display_flag = 0; + end + "WARNING_ONLY" : output_flag = 0; + "GENERATE_X_ONLY" : display_flag = 0; + "ALL" : ; + + default : begin + $display("Attribute Syntax Error : The Attribute SIM_COLLISION_CHECK on RAMB16_S18_S18 instance %m is set to %s. Legal values for this attribute are ALL, NONE, WARNING_ONLY or GENERATE_X_ONLY.", SIM_COLLISION_CHECK); + $finish; + end + + endcase // case(SIM_COLLISION_CHECK) + + end // initial begin + + + always @(posedge clka_int) begin + if ((output_flag || display_flag)) begin + time_clka = $time; + #0 time_clkb_clka = time_clka - time_clkb; + change_clka = ~change_clka; + end + end + + always @(posedge clkb_int) begin + if ((output_flag || display_flag)) begin + time_clkb = $time; + #0 time_clka_clkb = time_clkb - time_clka; + change_clkb = ~change_clkb; + end + end + + always @(change_clkb) begin + if ((0 < time_clka_clkb) && (time_clka_clkb < SETUP_ALL)) + setup_all_a_b = 1; + if ((0 < time_clka_clkb) && (time_clka_clkb < SETUP_READ_FIRST)) + setup_rf_a_b = 1; + end + + always @(change_clka) begin + if ((0 < time_clkb_clka) && (time_clkb_clka < SETUP_ALL)) + setup_all_b_a = 1; + if ((0 < time_clkb_clka) && (time_clkb_clka < SETUP_READ_FIRST)) + setup_rf_b_a = 1; + end + + always @(change_clkb or change_clka) begin + if ((time_clkb_clka == 0) && (time_clka_clkb == 0)) + setup_zero = 1; + end + + always @(posedge setup_zero) begin + if ((ena_int == 1) && (wea_int == 1) && + (enb_int == 1) && (web_int == 1) && + (data_addra_int[14:4] == data_addrb_int[14:4])) + memory_collision <= 1; + end + + always @(posedge setup_all_a_b or posedge setup_rf_a_b) begin + if ((ena_reg == 1) && (wea_reg == 1) && + (enb_int == 1) && (web_int == 1) && + (data_addra_reg[14:4] == data_addrb_int[14:4])) + memory_collision_a_b <= 1; + end + + always @(posedge setup_all_b_a or posedge setup_rf_b_a) begin + if ((ena_int == 1) && (wea_int == 1) && + (enb_reg == 1) && (web_reg == 1) && + (data_addra_int[14:4] == data_addrb_reg[14:4])) + memory_collision_b_a <= 1; + end + + always @(posedge setup_all_a_b) begin + if (data_addra_reg[14:4] == data_addrb_int[14:4]) begin + if ((ena_reg == 1) && (enb_int == 1)) begin + case ({wr_mode_a, wr_mode_b, wea_reg, web_int}) + 6'b000011 : begin data_collision_a_b <= 2'b11; display_wa_wb; end + 6'b000111 : begin data_collision_a_b <= 2'b11; display_wa_wb; end + 6'b001011 : begin data_collision_a_b <= 2'b10; display_wa_wb; end +// 6'b010011 : begin data_collision_a_b <= 2'b00; display_wa_wb; end +// 6'b010111 : begin data_collision_a_b <= 2'b00; display_wa_wb; end +// 6'b011011 : begin data_collision_a_b <= 2'b00; display_wa_wb; end + 6'b100011 : begin data_collision_a_b <= 2'b01; display_wa_wb; end + 6'b100111 : begin data_collision_a_b <= 2'b01; display_wa_wb; end + 6'b101011 : begin display_wa_wb; end + 6'b000001 : begin data_collision_a_b <= 2'b10; display_ra_wb; end +// 6'b000101 : begin data_collision_a_b <= 2'b00; display_ra_wb; end + 6'b001001 : begin data_collision_a_b <= 2'b10; display_ra_wb; end + 6'b010001 : begin data_collision_a_b <= 2'b10; display_ra_wb; end +// 6'b010101 : begin data_collision_a_b <= 2'b00; display_ra_wb; end + 6'b011001 : begin data_collision_a_b <= 2'b10; display_ra_wb; end + 6'b100001 : begin data_collision_a_b <= 2'b10; display_ra_wb; end +// 6'b100101 : begin data_collision_a_b <= 2'b00; display_ra_wb; end + 6'b101001 : begin data_collision_a_b <= 2'b10; display_ra_wb; end + 6'b000010 : begin data_collision_a_b <= 2'b01; display_wa_rb; end + 6'b000110 : begin data_collision_a_b <= 2'b01; display_wa_rb; end + 6'b001010 : begin data_collision_a_b <= 2'b01; display_wa_rb; end +// 6'b010010 : begin data_collision_a_b <= 2'b00; display_wa_rb; end +// 6'b010110 : begin data_collision_a_b <= 2'b00; display_wa_rb; end +// 6'b011010 : begin data_collision_a_b <= 2'b00; display_wa_rb; end + 6'b100010 : begin data_collision_a_b <= 2'b01; display_wa_rb; end + 6'b100110 : begin data_collision_a_b <= 2'b01; display_wa_rb; end + 6'b101010 : begin data_collision_a_b <= 2'b01; display_wa_rb; end + endcase + end + end + setup_all_a_b <= 0; + end + + + always @(posedge setup_all_b_a) begin + if (data_addra_int[14:4] == data_addrb_reg[14:4]) begin + if ((ena_int == 1) && (enb_reg == 1)) begin + case ({wr_mode_a, wr_mode_b, wea_int, web_reg}) + 6'b000011 : begin data_collision_b_a <= 2'b11; display_wa_wb; end +// 6'b000111 : begin data_collision_b_a <= 2'b00; display_wa_wb; end + 6'b001011 : begin data_collision_b_a <= 2'b10; display_wa_wb; end + 6'b010011 : begin data_collision_b_a <= 2'b11; display_wa_wb; end +// 6'b010111 : begin data_collision_b_a <= 2'b00; display_wa_wb; end + 6'b011011 : begin data_collision_b_a <= 2'b10; display_wa_wb; end + 6'b100011 : begin data_collision_b_a <= 2'b01; display_wa_wb; end + 6'b100111 : begin data_collision_b_a <= 2'b01; display_wa_wb; end + 6'b101011 : begin display_wa_wb; end + 6'b000001 : begin data_collision_b_a <= 2'b10; display_ra_wb; end + 6'b000101 : begin data_collision_b_a <= 2'b10; display_ra_wb; end + 6'b001001 : begin data_collision_b_a <= 2'b10; display_ra_wb; end + 6'b010001 : begin data_collision_b_a <= 2'b10; display_ra_wb; end + 6'b010101 : begin data_collision_b_a <= 2'b10; display_ra_wb; end + 6'b011001 : begin data_collision_b_a <= 2'b10; display_ra_wb; end + 6'b100001 : begin data_collision_b_a <= 2'b10; display_ra_wb; end + 6'b100101 : begin data_collision_b_a <= 2'b10; display_ra_wb; end + 6'b101001 : begin data_collision_b_a <= 2'b10; display_ra_wb; end + 6'b000010 : begin data_collision_b_a <= 2'b01; display_wa_rb; end + 6'b000110 : begin data_collision_b_a <= 2'b01; display_wa_rb; end + 6'b001010 : begin data_collision_b_a <= 2'b01; display_wa_rb; end +// 6'b010010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end +// 6'b010110 : begin data_collision_b_a <= 2'b00; display_wa_rb; end +// 6'b011010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end + 6'b100010 : begin data_collision_b_a <= 2'b01; display_wa_rb; end + 6'b100110 : begin data_collision_b_a <= 2'b01; display_wa_rb; end + 6'b101010 : begin data_collision_b_a <= 2'b01; display_wa_rb; end + endcase + end + end + setup_all_b_a <= 0; + end + + + always @(posedge setup_zero) begin + if (data_addra_int[14:4] == data_addrb_int[14:4]) begin + if ((ena_int == 1) && (enb_int == 1)) begin + case ({wr_mode_a, wr_mode_b, wea_int, web_int}) + 6'b000011 : begin data_collision <= 2'b11; display_wa_wb; end + 6'b000111 : begin data_collision <= 2'b11; display_wa_wb; end + 6'b001011 : begin data_collision <= 2'b10; display_wa_wb; end + 6'b010011 : begin data_collision <= 2'b11; display_wa_wb; end + 6'b010111 : begin data_collision <= 2'b11; display_wa_wb; end + 6'b011011 : begin data_collision <= 2'b10; display_wa_wb; end + 6'b100011 : begin data_collision <= 2'b01; display_wa_wb; end + 6'b100111 : begin data_collision <= 2'b01; display_wa_wb; end + 6'b101011 : begin display_wa_wb; end + 6'b000001 : begin data_collision <= 2'b10; display_ra_wb; end +// 6'b000101 : begin data_collision <= 2'b00; display_ra_wb; end + 6'b001001 : begin data_collision <= 2'b10; display_ra_wb; end + 6'b010001 : begin data_collision <= 2'b10; display_ra_wb; end +// 6'b010101 : begin data_collision <= 2'b00; display_ra_wb; end + 6'b011001 : begin data_collision <= 2'b10; display_ra_wb; end + 6'b100001 : begin data_collision <= 2'b10; display_ra_wb; end +// 6'b100101 : begin data_collision <= 2'b00; display_ra_wb; end + 6'b101001 : begin data_collision <= 2'b10; display_ra_wb; end + 6'b000010 : begin data_collision <= 2'b01; display_wa_rb; end + 6'b000110 : begin data_collision <= 2'b01; display_wa_rb; end + 6'b001010 : begin data_collision <= 2'b01; display_wa_rb; end +// 6'b010010 : begin data_collision <= 2'b00; display_wa_rb; end +// 6'b010110 : begin data_collision <= 2'b00; display_wa_rb; end +// 6'b011010 : begin data_collision <= 2'b00; display_wa_rb; end + 6'b100010 : begin data_collision <= 2'b01; display_wa_rb; end + 6'b100110 : begin data_collision <= 2'b01; display_wa_rb; end + 6'b101010 : begin data_collision <= 2'b01; display_wa_rb; end + endcase + end + end + setup_zero <= 0; + end + + task display_ra_wb; + begin + if (display_flag) + $display("Memory Collision Error on RAMB16_S18_S18:%m at simulation time %.3f ns\nA read was performed on address %h (hex) of Port A while a write was requested to the same address on Port B. The write will be successful however the read value on Port A is unknown until the next CLKA cycle.", $time/1000.0, addra_int); + end + endtask + + task display_wa_rb; + begin + if (display_flag) + $display("Memory Collision Error on RAMB16_S18_S18:%m at simulation time %.3f ns\nA read was performed on address %h (hex) of Port B while a write was requested to the same address on Port A. The write will be successful however the read value on Port B is unknown until the next CLKB cycle.", $time/1000.0, addrb_int); + end + endtask + + task display_wa_wb; + begin + if (display_flag) + $display("Memory Collision Error on RAMB16_S18_S18:%m at simulation time %.3f ns\nA write was requested to the same address simultaneously at both Port A and Port B of the RAM. The contents written to the RAM at address location %h (hex) of Port A and address location %h (hex) of Port B are unknown.", $time/1000.0, addra_int, addrb_int); + end + endtask + + + always @(posedge setup_rf_a_b) begin + if (data_addra_reg[14:4] == data_addrb_int[14:4]) begin + if ((ena_reg == 1) && (enb_int == 1)) begin + case ({wr_mode_a, wr_mode_b, wea_reg, web_int}) +// 6'b000011 : begin data_collision_a_b <= 2'b00; display_wa_wb; end +// 6'b000111 : begin data_collision_a_b <= 2'b00; display_wa_wb; end +// 6'b001011 : begin data_collision_a_b <= 2'b00; display_wa_wb; end + 6'b010011 : begin data_collision_a_b <= 2'b11; display_wa_wb; end + 6'b010111 : begin data_collision_a_b <= 2'b11; display_wa_wb; end + 6'b011011 : begin data_collision_a_b <= 2'b10; display_wa_wb; end +// 6'b100011 : begin data_collision_a_b <= 2'b00; display_wa_wb; end +// 6'b100111 : begin data_collision_a_b <= 2'b00; display_wa_wb; end +// 6'b101011 : begin data_collision_a_b <= 2'b00; display_wa_wb; end +// 6'b000001 : begin data_collision_a_b <= 2'b00; display_ra_wb; end +// 6'b000101 : begin data_collision_a_b <= 2'b00; display_ra_wb; end +// 6'b001001 : begin data_collision_a_b <= 2'b00; display_ra_wb; end +// 6'b010001 : begin data_collision_a_b <= 2'b00; display_ra_wb; end +// 6'b010101 : begin data_collision_a_b <= 2'b00; display_ra_wb; end +// 6'b011001 : begin data_collision_a_b <= 2'b00; display_ra_wb; end +// 6'b100001 : begin data_collision_a_b <= 2'b00; display_ra_wb; end +// 6'b100101 : begin data_collision_a_b <= 2'b00; display_ra_wb; end +// 6'b101001 : begin data_collision_a_b <= 2'b00; display_ra_wb; end +// 6'b000010 : begin data_collision_a_b <= 2'b00; display_wa_rb; end +// 6'b000110 : begin data_collision_a_b <= 2'b00; display_wa_rb; end +// 6'b001010 : begin data_collision_a_b <= 2'b00; display_wa_rb; end + 6'b010010 : begin data_collision_a_b <= 2'b01; display_wa_rb; end + 6'b010110 : begin data_collision_a_b <= 2'b01; display_wa_rb; end + 6'b011010 : begin data_collision_a_b <= 2'b01; display_wa_rb; end +// 6'b100010 : begin data_collision_a_b <= 2'b00; display_wa_rb; end +// 6'b100110 : begin data_collision_a_b <= 2'b00; display_wa_rb; end +// 6'b101010 : begin data_collision_a_b <= 2'b00; display_wa_rb; end + endcase + end + end + setup_rf_a_b <= 0; + end + + + always @(posedge setup_rf_b_a) begin + if (data_addra_int[14:4] == data_addrb_reg[14:4]) begin + if ((ena_int == 1) && (enb_reg == 1)) begin + case ({wr_mode_a, wr_mode_b, wea_int, web_reg}) +// 6'b000011 : begin data_collision_b_a <= 2'b00; display_wa_wb; end + 6'b000111 : begin data_collision_b_a <= 2'b11; display_wa_wb; end +// 6'b001011 : begin data_collision_b_a <= 2'b00; display_wa_wb; end +// 6'b010011 : begin data_collision_b_a <= 2'b00; display_wa_wb; end + 6'b010111 : begin data_collision_b_a <= 2'b11; display_wa_wb; end +// 6'b011011 : begin data_collision_b_a <= 2'b00; display_wa_wb; end +// 6'b100011 : begin data_collision_b_a <= 2'b00; display_wa_wb; end + 6'b100111 : begin data_collision_b_a <= 2'b01; display_wa_wb; end +// 6'b101011 : begin data_collision_b_a <= 2'b00; display_wa_wb; end +// 6'b000001 : begin data_collision_b_a <= 2'b00; display_ra_wb; end + 6'b000101 : begin data_collision_b_a <= 2'b10; display_ra_wb; end +// 6'b001001 : begin data_collision_b_a <= 2'b00; display_ra_wb; end +// 6'b010001 : begin data_collision_b_a <= 2'b00; display_ra_wb; end + 6'b010101 : begin data_collision_b_a <= 2'b10; display_ra_wb; end +// 6'b011001 : begin data_collision_b_a <= 2'b00; display_ra_wb; end +// 6'b100001 : begin data_collision_b_a <= 2'b00; display_ra_wb; end + 6'b100101 : begin data_collision_b_a <= 2'b10; display_ra_wb; end +// 6'b101001 : begin data_collision_b_a <= 2'b00; display_ra_wb; end +// 6'b000010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end +// 6'b000110 : begin data_collision_b_a <= 2'b00; display_wa_rb; end +// 6'b001010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end +// 6'b010010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end +// 6'b010110 : begin data_collision_b_a <= 2'b00; display_wa_rb; end +// 6'b011010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end +// 6'b100010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end +// 6'b100110 : begin data_collision_b_a <= 2'b00; display_wa_rb; end +// 6'b101010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end + endcase + end + end + setup_rf_b_a <= 0; + end + + + always @(posedge clka_int) begin + if ((output_flag || display_flag)) begin + addra_reg <= addra_int; + ena_reg <= ena_int; + ssra_reg <= ssra_int; + wea_reg <= wea_int; + end + end + + always @(posedge clkb_int) begin + if ((output_flag || display_flag)) begin + addrb_reg <= addrb_int; + enb_reg <= enb_int; + ssrb_reg <= ssrb_int; + web_reg <= web_int; + end + end + + + // Data + always @(posedge memory_collision) begin + if ((output_flag || display_flag)) begin + mem[addra_int] <= 16'bx; + memory_collision <= 0; + end + + end + + always @(posedge memory_collision_a_b) begin + if ((output_flag || display_flag)) begin + mem[addra_reg] <= 16'bx; + memory_collision_a_b <= 0; + end + end + + always @(posedge memory_collision_b_a) begin + if ((output_flag || display_flag)) begin + mem[addra_int] <= 16'bx; + memory_collision_b_a <= 0; + end + end + + always @(posedge data_collision[1]) begin + if (ssra_int == 0 && output_flag) begin + doa_out <= #100 16'bX; + end + data_collision[1] <= 0; + end + + always @(posedge data_collision[0]) begin + if (ssrb_int == 0 && output_flag) begin + dob_out <= #100 16'bX; + end + data_collision[0] <= 0; + end + + always @(posedge data_collision_a_b[1]) begin + if (ssra_reg == 0 && output_flag) begin + doa_out <= #100 16'bX; + end + data_collision_a_b[1] <= 0; + end + + always @(posedge data_collision_a_b[0]) begin + if (ssrb_int == 0 && output_flag) begin + dob_out <= #100 16'bX; + end + data_collision_a_b[0] <= 0; + end + + always @(posedge data_collision_b_a[1]) begin + if (ssra_int == 0 && output_flag) begin + doa_out <= #100 16'bX; + end + data_collision_b_a[1] <= 0; + end + + always @(posedge data_collision_b_a[0]) begin + if (ssrb_reg == 0 && output_flag) begin + dob_out <= #100 16'bX; + end + data_collision_b_a[0] <= 0; + end + +// x parity start + always @(posedge memory_collision) begin + if ((output_flag || display_flag)) + memp[addra_int] <= 2'bx; + end + + always @(posedge memory_collision_a_b) begin + if ((output_flag || display_flag)) + memp[addra_reg] <= 2'bx; + end + + always @(posedge memory_collision_b_a) begin + if ((output_flag || display_flag)) + memp[addra_int] <= 2'bx; + end + + always @(posedge data_collision[1]) begin + if (ssra_int == 0 && output_flag) begin + dopa_out <= #100 2'bX; + end + end + + always @(posedge data_collision_a_b[1]) begin + if (ssra_reg == 0 && output_flag) begin + dopa_out <= #100 2'bX; + end + end + + + always @(posedge data_collision_b_a[1]) begin + if (ssra_int == 0 && output_flag) begin + dopa_out <= #100 2'bX; + end + end + + always @(posedge data_collision[0]) begin + if (ssrb_int == 0 && output_flag) begin + dopb_out <= #100 2'bx; + end + end + + always @(posedge data_collision_a_b[0]) begin + if (ssrb_int == 0 && output_flag) begin + dopb_out <= #100 2'bx; + end + end + + always @(posedge data_collision_b_a[0]) begin + if (ssrb_reg == 0 && output_flag) begin + dopb_out <= #100 2'bx; + end + end +// x parity end + + initial begin + case (WRITE_MODE_A) + "WRITE_FIRST" : wr_mode_a <= 2'b00; + "READ_FIRST" : wr_mode_a <= 2'b01; + "NO_CHANGE" : wr_mode_a <= 2'b10; + default : begin + $display("Attribute Syntax Error : The Attribute WRITE_MODE_A on RAMB16_S18_S18 instance %m is set to %s. Legal values for this attribute are WRITE_FIRST, READ_FIRST or NO_CHANGE.", WRITE_MODE_A); + $finish; + end + endcase + end + + initial begin + case (WRITE_MODE_B) + "WRITE_FIRST" : wr_mode_b <= 2'b00; + "READ_FIRST" : wr_mode_b <= 2'b01; + "NO_CHANGE" : wr_mode_b <= 2'b10; + default : begin + $display("Attribute Syntax Error : The Attribute WRITE_MODE_B on RAMB16_S18_S18 instance %m is set to %s. Legal values for this attribute are WRITE_FIRST, READ_FIRST or NO_CHANGE.", WRITE_MODE_B); + $finish; + end + endcase + end + + + // Port A + always @(posedge clka_int) begin + + if (ena_int == 1'b1) begin + + if (ssra_int == 1'b1) begin + {dopa_out, doa_out} <= #100 SRVAL_A; + end + else begin + if (wea_int == 1'b1) begin + if (wr_mode_a == 2'b00) begin + doa_out <= #100 dia_int; + dopa_out <= #100 dipa_int; + end + else if (wr_mode_a == 2'b01) begin + + doa_out <= #100 mem[addra_int]; + dopa_out <= #100 memp[addra_int]; + + end + end + else begin + + doa_out <= #100 mem[addra_int]; + dopa_out <= #100 memp[addra_int]; + + end + end + + // memory + if (wea_int == 1'b1) begin + mem[addra_int] <= dia_int; + memp[addra_int] <= dipa_int; + end + + end + end + + + // Port B + always @(posedge clkb_int) begin + + if (enb_int == 1'b1) begin + + if (ssrb_int == 1'b1) begin + {dopb_out, dob_out} <= #100 SRVAL_B; + end + else begin + if (web_int == 1'b1) begin + if (wr_mode_b == 2'b00) begin + dob_out <= #100 dib_int; + dopb_out <= #100 dipb_int; + end + else if (wr_mode_b == 2'b01) begin + dob_out <= #100 mem[addrb_int]; + dopb_out <= #100 memp[addrb_int]; + end + end + else begin + dob_out <= #100 mem[addrb_int]; + dopb_out <= #100 memp[addrb_int]; + end + end + + // memory + if (web_int == 1'b1) begin + mem[addrb_int] <= dib_int; + memp[addrb_int] <= dipb_int; + end + + end + end + + +endmodule + +`endif diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/RAMB16_S18_S36.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/RAMB16_S18_S36.v new file mode 100644 index 0000000..719e395 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/RAMB16_S18_S36.v @@ -0,0 +1,2081 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/RAMB16_S18_S36.v,v 1.10 2007/02/22 01:58:05 wloo Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2005 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / 16K-Bit Data and 2K-Bit Parity Dual Port Block RAM +// /___/ /\ Filename : RAMB16_S18_S36.v +// \ \ / \ Timestamp : Thu Mar 10 16:43:35 PST 2005 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// End Revision + +`ifdef legacy_model + +`timescale 1 ps / 1 ps + +module RAMB16_S18_S36 (DOA, DOB, DOPA, DOPB, ADDRA, ADDRB, CLKA, CLKB, DIA, DIB, DIPA, DIPB, ENA, ENB, SSRA, SSRB, WEA, WEB); + + parameter INIT_A = 18'h0; + parameter INIT_B = 36'h0; + parameter SRVAL_A = 18'h0; + parameter SRVAL_B = 36'h0; + parameter WRITE_MODE_A = "WRITE_FIRST"; + parameter WRITE_MODE_B = "WRITE_FIRST"; + parameter SIM_COLLISION_CHECK = "ALL"; + localparam SETUP_ALL = 1000; + localparam SETUP_READ_FIRST = 3000; + + parameter INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + + output [15:0] DOA; + output [1:0] DOPA; + reg [15:0] doa_out; + reg [1:0] dopa_out; + wire doa_out0, doa_out1, doa_out2, doa_out3, doa_out4, doa_out5, doa_out6, doa_out7, doa_out8, doa_out9, doa_out10, doa_out11, doa_out12, doa_out13, doa_out14, doa_out15; + wire dopa0_out, dopa1_out; + + input [9:0] ADDRA; + input [15:0] DIA; + input [1:0] DIPA; + input ENA, CLKA, WEA, SSRA; + + output [31:0] DOB; + output [3:0] DOPB; + reg [31:0] dob_out; + reg [3:0] dopb_out; + wire dob_out0, dob_out1, dob_out2, dob_out3, dob_out4, dob_out5, dob_out6, dob_out7, dob_out8, dob_out9, dob_out10, dob_out11, dob_out12, dob_out13, dob_out14, dob_out15, dob_out16, dob_out17, dob_out18, dob_out19, dob_out20, dob_out21, dob_out22, dob_out23, dob_out24, dob_out25, dob_out26, dob_out27, dob_out28, dob_out29, dob_out30, dob_out31; + wire dopb0_out, dopb1_out, dopb2_out, dopb3_out; + + input [8:0] ADDRB; + input [31:0] DIB; + input [3:0] DIPB; + input ENB, CLKB, WEB, SSRB; + + reg [18431:0] mem; + reg [8:0] count; + reg [1:0] wr_mode_a, wr_mode_b; + + reg [5:0] dmi, dbi; + reg [5:0] pmi, pbi; + + wire [9:0] addra_int; + reg [9:0] addra_reg; + wire [15:0] dia_int; + wire [1:0] dipa_int; + wire ena_int, clka_int, wea_int, ssra_int; + reg ena_reg, wea_reg, ssra_reg; + wire [8:0] addrb_int; + reg [8:0] addrb_reg; + wire [31:0] dib_int; + wire [3:0] dipb_int; + wire enb_int, clkb_int, web_int, ssrb_int; + reg display_flag; + reg enb_reg, web_reg, ssrb_reg; + + time time_clka, time_clkb; + time time_clka_clkb; + time time_clkb_clka; + + reg setup_all_a_b; + reg setup_all_b_a; + reg setup_zero; + reg setup_rf_a_b; + reg setup_rf_b_a; + reg [1:0] data_collision, data_collision_a_b, data_collision_b_a; + reg memory_collision, memory_collision_a_b, memory_collision_b_a; + reg address_collision, address_collision_a_b, address_collision_b_a; + reg change_clka; + reg change_clkb; + + wire [14:0] data_addra_int; + wire [14:0] data_addra_reg; + wire [14:0] data_addrb_int; + wire [14:0] data_addrb_reg; + wire [15:0] parity_addra_int; + wire [15:0] parity_addra_reg; + wire [15:0] parity_addrb_int; + wire [15:0] parity_addrb_reg; + + tri0 GSR = glbl.GSR; + + always @(GSR) + if (GSR) begin + assign doa_out = INIT_A[15:0]; + assign dopa_out = INIT_A[17:16]; + assign dob_out = INIT_B[31:0]; + assign dopb_out = INIT_B[35:32]; + end + else begin + deassign doa_out; + deassign dopa_out; + deassign dob_out; + deassign dopb_out; + end + + buf b_doa_out0 (doa_out0, doa_out[0]); + buf b_doa_out1 (doa_out1, doa_out[1]); + buf b_doa_out2 (doa_out2, doa_out[2]); + buf b_doa_out3 (doa_out3, doa_out[3]); + buf b_doa_out4 (doa_out4, doa_out[4]); + buf b_doa_out5 (doa_out5, doa_out[5]); + buf b_doa_out6 (doa_out6, doa_out[6]); + buf b_doa_out7 (doa_out7, doa_out[7]); + buf b_doa_out8 (doa_out8, doa_out[8]); + buf b_doa_out9 (doa_out9, doa_out[9]); + buf b_doa_out10 (doa_out10, doa_out[10]); + buf b_doa_out11 (doa_out11, doa_out[11]); + buf b_doa_out12 (doa_out12, doa_out[12]); + buf b_doa_out13 (doa_out13, doa_out[13]); + buf b_doa_out14 (doa_out14, doa_out[14]); + buf b_doa_out15 (doa_out15, doa_out[15]); + buf b_dopa_out0 (dopa_out0, dopa_out[0]); + buf b_dopa_out1 (dopa_out1, dopa_out[1]); + buf b_dob_out0 (dob_out0, dob_out[0]); + buf b_dob_out1 (dob_out1, dob_out[1]); + buf b_dob_out2 (dob_out2, dob_out[2]); + buf b_dob_out3 (dob_out3, dob_out[3]); + buf b_dob_out4 (dob_out4, dob_out[4]); + buf b_dob_out5 (dob_out5, dob_out[5]); + buf b_dob_out6 (dob_out6, dob_out[6]); + buf b_dob_out7 (dob_out7, dob_out[7]); + buf b_dob_out8 (dob_out8, dob_out[8]); + buf b_dob_out9 (dob_out9, dob_out[9]); + buf b_dob_out10 (dob_out10, dob_out[10]); + buf b_dob_out11 (dob_out11, dob_out[11]); + buf b_dob_out12 (dob_out12, dob_out[12]); + buf b_dob_out13 (dob_out13, dob_out[13]); + buf b_dob_out14 (dob_out14, dob_out[14]); + buf b_dob_out15 (dob_out15, dob_out[15]); + buf b_dob_out16 (dob_out16, dob_out[16]); + buf b_dob_out17 (dob_out17, dob_out[17]); + buf b_dob_out18 (dob_out18, dob_out[18]); + buf b_dob_out19 (dob_out19, dob_out[19]); + buf b_dob_out20 (dob_out20, dob_out[20]); + buf b_dob_out21 (dob_out21, dob_out[21]); + buf b_dob_out22 (dob_out22, dob_out[22]); + buf b_dob_out23 (dob_out23, dob_out[23]); + buf b_dob_out24 (dob_out24, dob_out[24]); + buf b_dob_out25 (dob_out25, dob_out[25]); + buf b_dob_out26 (dob_out26, dob_out[26]); + buf b_dob_out27 (dob_out27, dob_out[27]); + buf b_dob_out28 (dob_out28, dob_out[28]); + buf b_dob_out29 (dob_out29, dob_out[29]); + buf b_dob_out30 (dob_out30, dob_out[30]); + buf b_dob_out31 (dob_out31, dob_out[31]); + buf b_dopb_out0 (dopb_out0, dopb_out[0]); + buf b_dopb_out1 (dopb_out1, dopb_out[1]); + buf b_dopb_out2 (dopb_out2, dopb_out[2]); + buf b_dopb_out3 (dopb_out3, dopb_out[3]); + + buf b_doa0 (DOA[0], doa_out0); + buf b_doa1 (DOA[1], doa_out1); + buf b_doa2 (DOA[2], doa_out2); + buf b_doa3 (DOA[3], doa_out3); + buf b_doa4 (DOA[4], doa_out4); + buf b_doa5 (DOA[5], doa_out5); + buf b_doa6 (DOA[6], doa_out6); + buf b_doa7 (DOA[7], doa_out7); + buf b_doa8 (DOA[8], doa_out8); + buf b_doa9 (DOA[9], doa_out9); + buf b_doa10 (DOA[10], doa_out10); + buf b_doa11 (DOA[11], doa_out11); + buf b_doa12 (DOA[12], doa_out12); + buf b_doa13 (DOA[13], doa_out13); + buf b_doa14 (DOA[14], doa_out14); + buf b_doa15 (DOA[15], doa_out15); + buf b_dopa0 (DOPA[0], dopa_out0); + buf b_dopa1 (DOPA[1], dopa_out1); + buf b_dob0 (DOB[0], dob_out0); + buf b_dob1 (DOB[1], dob_out1); + buf b_dob2 (DOB[2], dob_out2); + buf b_dob3 (DOB[3], dob_out3); + buf b_dob4 (DOB[4], dob_out4); + buf b_dob5 (DOB[5], dob_out5); + buf b_dob6 (DOB[6], dob_out6); + buf b_dob7 (DOB[7], dob_out7); + buf b_dob8 (DOB[8], dob_out8); + buf b_dob9 (DOB[9], dob_out9); + buf b_dob10 (DOB[10], dob_out10); + buf b_dob11 (DOB[11], dob_out11); + buf b_dob12 (DOB[12], dob_out12); + buf b_dob13 (DOB[13], dob_out13); + buf b_dob14 (DOB[14], dob_out14); + buf b_dob15 (DOB[15], dob_out15); + buf b_dob16 (DOB[16], dob_out16); + buf b_dob17 (DOB[17], dob_out17); + buf b_dob18 (DOB[18], dob_out18); + buf b_dob19 (DOB[19], dob_out19); + buf b_dob20 (DOB[20], dob_out20); + buf b_dob21 (DOB[21], dob_out21); + buf b_dob22 (DOB[22], dob_out22); + buf b_dob23 (DOB[23], dob_out23); + buf b_dob24 (DOB[24], dob_out24); + buf b_dob25 (DOB[25], dob_out25); + buf b_dob26 (DOB[26], dob_out26); + buf b_dob27 (DOB[27], dob_out27); + buf b_dob28 (DOB[28], dob_out28); + buf b_dob29 (DOB[29], dob_out29); + buf b_dob30 (DOB[30], dob_out30); + buf b_dob31 (DOB[31], dob_out31); + buf b_dopb0 (DOPB[0], dopb_out0); + buf b_dopb1 (DOPB[1], dopb_out1); + buf b_dopb2 (DOPB[2], dopb_out2); + buf b_dopb3 (DOPB[3], dopb_out3); + + buf b_addra_0 (addra_int[0], ADDRA[0]); + buf b_addra_1 (addra_int[1], ADDRA[1]); + buf b_addra_2 (addra_int[2], ADDRA[2]); + buf b_addra_3 (addra_int[3], ADDRA[3]); + buf b_addra_4 (addra_int[4], ADDRA[4]); + buf b_addra_5 (addra_int[5], ADDRA[5]); + buf b_addra_6 (addra_int[6], ADDRA[6]); + buf b_addra_7 (addra_int[7], ADDRA[7]); + buf b_addra_8 (addra_int[8], ADDRA[8]); + buf b_addra_9 (addra_int[9], ADDRA[9]); + buf b_dia_0 (dia_int[0], DIA[0]); + buf b_dia_1 (dia_int[1], DIA[1]); + buf b_dia_2 (dia_int[2], DIA[2]); + buf b_dia_3 (dia_int[3], DIA[3]); + buf b_dia_4 (dia_int[4], DIA[4]); + buf b_dia_5 (dia_int[5], DIA[5]); + buf b_dia_6 (dia_int[6], DIA[6]); + buf b_dia_7 (dia_int[7], DIA[7]); + buf b_dia_8 (dia_int[8], DIA[8]); + buf b_dia_9 (dia_int[9], DIA[9]); + buf b_dia_10 (dia_int[10], DIA[10]); + buf b_dia_11 (dia_int[11], DIA[11]); + buf b_dia_12 (dia_int[12], DIA[12]); + buf b_dia_13 (dia_int[13], DIA[13]); + buf b_dia_14 (dia_int[14], DIA[14]); + buf b_dia_15 (dia_int[15], DIA[15]); + buf b_dipa_0 (dipa_int[0], DIPA[0]); + buf b_dipa_1 (dipa_int[1], DIPA[1]); + buf b_ena (ena_int, ENA); + buf b_clka (clka_int, CLKA); + buf b_ssra (ssra_int, SSRA); + buf b_wea (wea_int, WEA); + buf b_addrb_0 (addrb_int[0], ADDRB[0]); + buf b_addrb_1 (addrb_int[1], ADDRB[1]); + buf b_addrb_2 (addrb_int[2], ADDRB[2]); + buf b_addrb_3 (addrb_int[3], ADDRB[3]); + buf b_addrb_4 (addrb_int[4], ADDRB[4]); + buf b_addrb_5 (addrb_int[5], ADDRB[5]); + buf b_addrb_6 (addrb_int[6], ADDRB[6]); + buf b_addrb_7 (addrb_int[7], ADDRB[7]); + buf b_addrb_8 (addrb_int[8], ADDRB[8]); + buf b_dib_0 (dib_int[0], DIB[0]); + buf b_dib_1 (dib_int[1], DIB[1]); + buf b_dib_2 (dib_int[2], DIB[2]); + buf b_dib_3 (dib_int[3], DIB[3]); + buf b_dib_4 (dib_int[4], DIB[4]); + buf b_dib_5 (dib_int[5], DIB[5]); + buf b_dib_6 (dib_int[6], DIB[6]); + buf b_dib_7 (dib_int[7], DIB[7]); + buf b_dib_8 (dib_int[8], DIB[8]); + buf b_dib_9 (dib_int[9], DIB[9]); + buf b_dib_10 (dib_int[10], DIB[10]); + buf b_dib_11 (dib_int[11], DIB[11]); + buf b_dib_12 (dib_int[12], DIB[12]); + buf b_dib_13 (dib_int[13], DIB[13]); + buf b_dib_14 (dib_int[14], DIB[14]); + buf b_dib_15 (dib_int[15], DIB[15]); + buf b_dib_16 (dib_int[16], DIB[16]); + buf b_dib_17 (dib_int[17], DIB[17]); + buf b_dib_18 (dib_int[18], DIB[18]); + buf b_dib_19 (dib_int[19], DIB[19]); + buf b_dib_20 (dib_int[20], DIB[20]); + buf b_dib_21 (dib_int[21], DIB[21]); + buf b_dib_22 (dib_int[22], DIB[22]); + buf b_dib_23 (dib_int[23], DIB[23]); + buf b_dib_24 (dib_int[24], DIB[24]); + buf b_dib_25 (dib_int[25], DIB[25]); + buf b_dib_26 (dib_int[26], DIB[26]); + buf b_dib_27 (dib_int[27], DIB[27]); + buf b_dib_28 (dib_int[28], DIB[28]); + buf b_dib_29 (dib_int[29], DIB[29]); + buf b_dib_30 (dib_int[30], DIB[30]); + buf b_dib_31 (dib_int[31], DIB[31]); + buf b_dipb_0 (dipb_int[0], DIPB[0]); + buf b_dipb_1 (dipb_int[1], DIPB[1]); + buf b_dipb_2 (dipb_int[2], DIPB[2]); + buf b_dipb_3 (dipb_int[3], DIPB[3]); + buf b_enb (enb_int, ENB); + buf b_clkb (clkb_int, CLKB); + buf b_ssrb (ssrb_int, SSRB); + buf b_web (web_int, WEB); + + initial begin + for (count = 0; count < 256; count = count + 1) begin + mem[count] <= INIT_00[count]; + mem[256 * 1 + count] <= INIT_01[count]; + mem[256 * 2 + count] <= INIT_02[count]; + mem[256 * 3 + count] <= INIT_03[count]; + mem[256 * 4 + count] <= INIT_04[count]; + mem[256 * 5 + count] <= INIT_05[count]; + mem[256 * 6 + count] <= INIT_06[count]; + mem[256 * 7 + count] <= INIT_07[count]; + mem[256 * 8 + count] <= INIT_08[count]; + mem[256 * 9 + count] <= INIT_09[count]; + mem[256 * 10 + count] <= INIT_0A[count]; + mem[256 * 11 + count] <= INIT_0B[count]; + mem[256 * 12 + count] <= INIT_0C[count]; + mem[256 * 13 + count] <= INIT_0D[count]; + mem[256 * 14 + count] <= INIT_0E[count]; + mem[256 * 15 + count] <= INIT_0F[count]; + mem[256 * 16 + count] <= INIT_10[count]; + mem[256 * 17 + count] <= INIT_11[count]; + mem[256 * 18 + count] <= INIT_12[count]; + mem[256 * 19 + count] <= INIT_13[count]; + mem[256 * 20 + count] <= INIT_14[count]; + mem[256 * 21 + count] <= INIT_15[count]; + mem[256 * 22 + count] <= INIT_16[count]; + mem[256 * 23 + count] <= INIT_17[count]; + mem[256 * 24 + count] <= INIT_18[count]; + mem[256 * 25 + count] <= INIT_19[count]; + mem[256 * 26 + count] <= INIT_1A[count]; + mem[256 * 27 + count] <= INIT_1B[count]; + mem[256 * 28 + count] <= INIT_1C[count]; + mem[256 * 29 + count] <= INIT_1D[count]; + mem[256 * 30 + count] <= INIT_1E[count]; + mem[256 * 31 + count] <= INIT_1F[count]; + mem[256 * 32 + count] <= INIT_20[count]; + mem[256 * 33 + count] <= INIT_21[count]; + mem[256 * 34 + count] <= INIT_22[count]; + mem[256 * 35 + count] <= INIT_23[count]; + mem[256 * 36 + count] <= INIT_24[count]; + mem[256 * 37 + count] <= INIT_25[count]; + mem[256 * 38 + count] <= INIT_26[count]; + mem[256 * 39 + count] <= INIT_27[count]; + mem[256 * 40 + count] <= INIT_28[count]; + mem[256 * 41 + count] <= INIT_29[count]; + mem[256 * 42 + count] <= INIT_2A[count]; + mem[256 * 43 + count] <= INIT_2B[count]; + mem[256 * 44 + count] <= INIT_2C[count]; + mem[256 * 45 + count] <= INIT_2D[count]; + mem[256 * 46 + count] <= INIT_2E[count]; + mem[256 * 47 + count] <= INIT_2F[count]; + mem[256 * 48 + count] <= INIT_30[count]; + mem[256 * 49 + count] <= INIT_31[count]; + mem[256 * 50 + count] <= INIT_32[count]; + mem[256 * 51 + count] <= INIT_33[count]; + mem[256 * 52 + count] <= INIT_34[count]; + mem[256 * 53 + count] <= INIT_35[count]; + mem[256 * 54 + count] <= INIT_36[count]; + mem[256 * 55 + count] <= INIT_37[count]; + mem[256 * 56 + count] <= INIT_38[count]; + mem[256 * 57 + count] <= INIT_39[count]; + mem[256 * 58 + count] <= INIT_3A[count]; + mem[256 * 59 + count] <= INIT_3B[count]; + mem[256 * 60 + count] <= INIT_3C[count]; + mem[256 * 61 + count] <= INIT_3D[count]; + mem[256 * 62 + count] <= INIT_3E[count]; + mem[256 * 63 + count] <= INIT_3F[count]; + mem[256 * 64 + count] <= INITP_00[count]; + mem[256 * 65 + count] <= INITP_01[count]; + mem[256 * 66 + count] <= INITP_02[count]; + mem[256 * 67 + count] <= INITP_03[count]; + mem[256 * 68 + count] <= INITP_04[count]; + mem[256 * 69 + count] <= INITP_05[count]; + mem[256 * 70 + count] <= INITP_06[count]; + mem[256 * 71 + count] <= INITP_07[count]; + end + address_collision <= 0; + address_collision_a_b <= 0; + address_collision_b_a <= 0; + change_clka <= 0; + change_clkb <= 0; + data_collision <= 0; + data_collision_a_b <= 0; + data_collision_b_a <= 0; + memory_collision <= 0; + memory_collision_a_b <= 0; + memory_collision_b_a <= 0; + setup_all_a_b <= 0; + setup_all_b_a <= 0; + setup_zero <= 0; + setup_rf_a_b <= 0; + setup_rf_b_a <= 0; + end + + assign data_addra_int = addra_int * 16; + assign data_addra_reg = addra_reg * 16; + assign data_addrb_int = addrb_int * 32; + assign data_addrb_reg = addrb_reg * 32; + assign parity_addra_int = 16384 + addra_int * 2; + assign parity_addra_reg = 16384 + addra_reg * 2; + assign parity_addrb_int = 16384 + addrb_int * 4; + assign parity_addrb_reg = 16384 + addrb_reg * 4; + + + initial begin + + display_flag = 1; + + case (SIM_COLLISION_CHECK) + + "NONE" : begin + assign setup_all_a_b = 1'b0; + assign setup_all_b_a = 1'b0; + assign setup_zero = 1'b0; + assign setup_rf_a_b = 1'b0; + assign setup_rf_b_a = 1'b0; + assign display_flag = 0; + end + "WARNING_ONLY" : begin + assign data_collision = 2'b00; + assign data_collision_a_b = 2'b00; + assign data_collision_b_a = 2'b00; + assign memory_collision = 1'b0; + assign memory_collision_a_b = 1'b0; + assign memory_collision_b_a = 1'b0; + end + "GENERATE_X_ONLY" : begin + assign display_flag = 0; + end + "ALL" : ; + default : begin + $display("Attribute Syntax Error : The Attribute SIM_COLLISION_CHECK on RAMB16_S18_S36 instance %m is set to %s. Legal values for this attribute are ALL, NONE, WARNING_ONLY or GENERATE_X_ONLY.", SIM_COLLISION_CHECK); + $finish; + end + + endcase // case(SIM_COLLISION_CHECK) + + end // initial begin + + + always @(posedge clka_int) begin + time_clka = $time; + #0 time_clkb_clka = time_clka - time_clkb; + change_clka = ~change_clka; + end + + always @(posedge clkb_int) begin + time_clkb = $time; + #0 time_clka_clkb = time_clkb - time_clka; + change_clkb = ~change_clkb; + end + + always @(change_clkb) begin + if ((0 < time_clka_clkb) && (time_clka_clkb < SETUP_ALL)) + setup_all_a_b = 1; + if ((0 < time_clka_clkb) && (time_clka_clkb < SETUP_READ_FIRST)) + setup_rf_a_b = 1; + end + + always @(change_clka) begin + if ((0 < time_clkb_clka) && (time_clkb_clka < SETUP_ALL)) + setup_all_b_a = 1; + if ((0 < time_clkb_clka) && (time_clkb_clka < SETUP_READ_FIRST)) + setup_rf_b_a = 1; + end + + always @(change_clkb or change_clka) begin + if ((time_clkb_clka == 0) && (time_clka_clkb == 0)) + setup_zero = 1; + end + + always @(posedge setup_zero) begin + if ((ena_int == 1) && (wea_int == 1) && + (enb_int == 1) && (web_int == 1) && + (data_addra_int[14:5] == data_addrb_int[14:5])) + memory_collision <= 1; + end + + always @(posedge setup_all_a_b or posedge setup_rf_a_b) begin + if ((ena_reg == 1) && (wea_reg == 1) && + (enb_int == 1) && (web_int == 1) && + (data_addra_reg[14:5] == data_addrb_int[14:5])) + memory_collision_a_b <= 1; + end + + always @(posedge setup_all_b_a or posedge setup_rf_b_a) begin + if ((ena_int == 1) && (wea_int == 1) && + (enb_reg == 1) && (web_reg == 1) && + (data_addra_int[14:5] == data_addrb_reg[14:5])) + memory_collision_b_a <= 1; + end + + always @(posedge setup_all_a_b) begin + if (data_addra_reg[14:5] == data_addrb_int[14:5]) begin + if ((ena_reg == 1) && (enb_int == 1)) begin + case ({wr_mode_a, wr_mode_b, wea_reg, web_int}) + 6'b000011 : begin data_collision_a_b <= 2'b11; display_wa_wb; end + 6'b000111 : begin data_collision_a_b <= 2'b11; display_wa_wb; end + 6'b001011 : begin data_collision_a_b <= 2'b10; display_wa_wb; end +// 6'b010011 : begin data_collision_a_b <= 2'b00; display_wa_wb; end +// 6'b010111 : begin data_collision_a_b <= 2'b00; display_wa_wb; end +// 6'b011011 : begin data_collision_a_b <= 2'b00; display_wa_wb; end + 6'b100011 : begin data_collision_a_b <= 2'b01; display_wa_wb; end + 6'b100111 : begin data_collision_a_b <= 2'b01; display_wa_wb; end + 6'b101011 : begin display_wa_wb; end + 6'b000001 : begin data_collision_a_b <= 2'b10; display_ra_wb; end +// 6'b000101 : begin data_collision_a_b <= 2'b00; display_ra_wb; end + 6'b001001 : begin data_collision_a_b <= 2'b10; display_ra_wb; end + 6'b010001 : begin data_collision_a_b <= 2'b10; display_ra_wb; end +// 6'b010101 : begin data_collision_a_b <= 2'b00; display_ra_wb; end + 6'b011001 : begin data_collision_a_b <= 2'b10; display_ra_wb; end + 6'b100001 : begin data_collision_a_b <= 2'b10; display_ra_wb; end +// 6'b100101 : begin data_collision_a_b <= 2'b00; display_ra_wb; end + 6'b101001 : begin data_collision_a_b <= 2'b10; display_ra_wb; end + 6'b000010 : begin data_collision_a_b <= 2'b01; display_wa_rb; end + 6'b000110 : begin data_collision_a_b <= 2'b01; display_wa_rb; end + 6'b001010 : begin data_collision_a_b <= 2'b01; display_wa_rb; end +// 6'b010010 : begin data_collision_a_b <= 2'b00; display_wa_rb; end +// 6'b010110 : begin data_collision_a_b <= 2'b00; display_wa_rb; end +// 6'b011010 : begin data_collision_a_b <= 2'b00; display_wa_rb; end + 6'b100010 : begin data_collision_a_b <= 2'b01; display_wa_rb; end + 6'b100110 : begin data_collision_a_b <= 2'b01; display_wa_rb; end + 6'b101010 : begin data_collision_a_b <= 2'b01; display_wa_rb; end + endcase + end + end + setup_all_a_b <= 0; + end + + + always @(posedge setup_all_b_a) begin + if (data_addra_int[14:5] == data_addrb_reg[14:5]) begin + if ((ena_int == 1) && (enb_reg == 1)) begin + case ({wr_mode_a, wr_mode_b, wea_int, web_reg}) + 6'b000011 : begin data_collision_b_a <= 2'b11; display_wa_wb; end +// 6'b000111 : begin data_collision_b_a <= 2'b00; display_wa_wb; end + 6'b001011 : begin data_collision_b_a <= 2'b10; display_wa_wb; end + 6'b010011 : begin data_collision_b_a <= 2'b11; display_wa_wb; end +// 6'b010111 : begin data_collision_b_a <= 2'b00; display_wa_wb; end + 6'b011011 : begin data_collision_b_a <= 2'b10; display_wa_wb; end + 6'b100011 : begin data_collision_b_a <= 2'b01; display_wa_wb; end + 6'b100111 : begin data_collision_b_a <= 2'b01; display_wa_wb; end + 6'b101011 : begin display_wa_wb; end + 6'b000001 : begin data_collision_b_a <= 2'b10; display_ra_wb; end + 6'b000101 : begin data_collision_b_a <= 2'b10; display_ra_wb; end + 6'b001001 : begin data_collision_b_a <= 2'b10; display_ra_wb; end + 6'b010001 : begin data_collision_b_a <= 2'b10; display_ra_wb; end + 6'b010101 : begin data_collision_b_a <= 2'b10; display_ra_wb; end + 6'b011001 : begin data_collision_b_a <= 2'b10; display_ra_wb; end + 6'b100001 : begin data_collision_b_a <= 2'b10; display_ra_wb; end + 6'b100101 : begin data_collision_b_a <= 2'b10; display_ra_wb; end + 6'b101001 : begin data_collision_b_a <= 2'b10; display_ra_wb; end + 6'b000010 : begin data_collision_b_a <= 2'b01; display_wa_rb; end + 6'b000110 : begin data_collision_b_a <= 2'b01; display_wa_rb; end + 6'b001010 : begin data_collision_b_a <= 2'b01; display_wa_rb; end +// 6'b010010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end +// 6'b010110 : begin data_collision_b_a <= 2'b00; display_wa_rb; end +// 6'b011010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end + 6'b100010 : begin data_collision_b_a <= 2'b01; display_wa_rb; end + 6'b100110 : begin data_collision_b_a <= 2'b01; display_wa_rb; end + 6'b101010 : begin data_collision_b_a <= 2'b01; display_wa_rb; end + endcase + end + end + setup_all_b_a <= 0; + end + + + always @(posedge setup_zero) begin + if (data_addra_int[14:5] == data_addrb_int[14:5]) begin + if ((ena_int == 1) && (enb_int == 1)) begin + case ({wr_mode_a, wr_mode_b, wea_int, web_int}) + 6'b000011 : begin data_collision <= 2'b11; display_wa_wb; end + 6'b000111 : begin data_collision <= 2'b11; display_wa_wb; end + 6'b001011 : begin data_collision <= 2'b10; display_wa_wb; end + 6'b010011 : begin data_collision <= 2'b11; display_wa_wb; end + 6'b010111 : begin data_collision <= 2'b11; display_wa_wb; end + 6'b011011 : begin data_collision <= 2'b10; display_wa_wb; end + 6'b100011 : begin data_collision <= 2'b01; display_wa_wb; end + 6'b100111 : begin data_collision <= 2'b01; display_wa_wb; end + 6'b101011 : begin display_wa_wb; end + 6'b000001 : begin data_collision <= 2'b10; display_ra_wb; end +// 6'b000101 : begin data_collision <= 2'b00; display_ra_wb; end + 6'b001001 : begin data_collision <= 2'b10; display_ra_wb; end + 6'b010001 : begin data_collision <= 2'b10; display_ra_wb; end +// 6'b010101 : begin data_collision <= 2'b00; display_ra_wb; end + 6'b011001 : begin data_collision <= 2'b10; display_ra_wb; end + 6'b100001 : begin data_collision <= 2'b10; display_ra_wb; end +// 6'b100101 : begin data_collision <= 2'b00; display_ra_wb; end + 6'b101001 : begin data_collision <= 2'b10; display_ra_wb; end + 6'b000010 : begin data_collision <= 2'b01; display_wa_rb; end + 6'b000110 : begin data_collision <= 2'b01; display_wa_rb; end + 6'b001010 : begin data_collision <= 2'b01; display_wa_rb; end +// 6'b010010 : begin data_collision <= 2'b00; display_wa_rb; end +// 6'b010110 : begin data_collision <= 2'b00; display_wa_rb; end +// 6'b011010 : begin data_collision <= 2'b00; display_wa_rb; end + 6'b100010 : begin data_collision <= 2'b01; display_wa_rb; end + 6'b100110 : begin data_collision <= 2'b01; display_wa_rb; end + 6'b101010 : begin data_collision <= 2'b01; display_wa_rb; end + endcase + end + end + setup_zero <= 0; + end + + task display_ra_wb; + begin + if (display_flag) + $display("Memory Collision Error on RAMB16_S18_S36:%m at simulation time %.3f ns\nA read was performed on address %h (hex) of Port A while a write was requested to the same address on Port B. The write will be successful however the read value on Port A is unknown until the next CLKA cycle.", $time/1000.0, addra_int); + end + endtask + + task display_wa_rb; + begin + if (display_flag) + $display("Memory Collision Error on RAMB16_S18_S36:%m at simulation time %.3f ns\nA read was performed on address %h (hex) of Port B while a write was requested to the same address on Port A. The write will be successful however the read value on Port B is unknown until the next CLKB cycle.", $time/1000.0, addrb_int); + end + endtask + + task display_wa_wb; + begin + if (display_flag) + $display("Memory Collision Error on RAMB16_S18_S36:%m at simulation time %.3f ns\nA write was requested to the same address simultaneously at both Port A and Port B of the RAM. The contents written to the RAM at address location %h (hex) of Port A and address location %h (hex) of Port B are unknown.", $time/1000.0, addra_int, addrb_int); + end + endtask + + + always @(posedge setup_rf_a_b) begin + if (data_addra_reg[14:5] == data_addrb_int[14:5]) begin + if ((ena_reg == 1) && (enb_int == 1)) begin + case ({wr_mode_a, wr_mode_b, wea_reg, web_int}) +// 6'b000011 : begin data_collision_a_b <= 2'b00; display_wa_wb; end +// 6'b000111 : begin data_collision_a_b <= 2'b00; display_wa_wb; end +// 6'b001011 : begin data_collision_a_b <= 2'b00; display_wa_wb; end + 6'b010011 : begin data_collision_a_b <= 2'b11; display_wa_wb; end + 6'b010111 : begin data_collision_a_b <= 2'b11; display_wa_wb; end + 6'b011011 : begin data_collision_a_b <= 2'b10; display_wa_wb; end +// 6'b100011 : begin data_collision_a_b <= 2'b00; display_wa_wb; end +// 6'b100111 : begin data_collision_a_b <= 2'b00; display_wa_wb; end +// 6'b101011 : begin data_collision_a_b <= 2'b00; display_wa_wb; end +// 6'b000001 : begin data_collision_a_b <= 2'b00; display_ra_wb; end +// 6'b000101 : begin data_collision_a_b <= 2'b00; display_ra_wb; end +// 6'b001001 : begin data_collision_a_b <= 2'b00; display_ra_wb; end +// 6'b010001 : begin data_collision_a_b <= 2'b00; display_ra_wb; end +// 6'b010101 : begin data_collision_a_b <= 2'b00; display_ra_wb; end +// 6'b011001 : begin data_collision_a_b <= 2'b00; display_ra_wb; end +// 6'b100001 : begin data_collision_a_b <= 2'b00; display_ra_wb; end +// 6'b100101 : begin data_collision_a_b <= 2'b00; display_ra_wb; end +// 6'b101001 : begin data_collision_a_b <= 2'b00; display_ra_wb; end +// 6'b000010 : begin data_collision_a_b <= 2'b00; display_wa_rb; end +// 6'b000110 : begin data_collision_a_b <= 2'b00; display_wa_rb; end +// 6'b001010 : begin data_collision_a_b <= 2'b00; display_wa_rb; end + 6'b010010 : begin data_collision_a_b <= 2'b01; display_wa_rb; end + 6'b010110 : begin data_collision_a_b <= 2'b01; display_wa_rb; end + 6'b011010 : begin data_collision_a_b <= 2'b01; display_wa_rb; end +// 6'b100010 : begin data_collision_a_b <= 2'b00; display_wa_rb; end +// 6'b100110 : begin data_collision_a_b <= 2'b00; display_wa_rb; end +// 6'b101010 : begin data_collision_a_b <= 2'b00; display_wa_rb; end + endcase + end + end + setup_rf_a_b <= 0; + end + + + always @(posedge setup_rf_b_a) begin + if (data_addra_int[14:5] == data_addrb_reg[14:5]) begin + if ((ena_int == 1) && (enb_reg == 1)) begin + case ({wr_mode_a, wr_mode_b, wea_int, web_reg}) +// 6'b000011 : begin data_collision_b_a <= 2'b00; display_wa_wb; end + 6'b000111 : begin data_collision_b_a <= 2'b11; display_wa_wb; end +// 6'b001011 : begin data_collision_b_a <= 2'b00; display_wa_wb; end +// 6'b010011 : begin data_collision_b_a <= 2'b00; display_wa_wb; end + 6'b010111 : begin data_collision_b_a <= 2'b11; display_wa_wb; end +// 6'b011011 : begin data_collision_b_a <= 2'b00; display_wa_wb; end +// 6'b100011 : begin data_collision_b_a <= 2'b00; display_wa_wb; end + 6'b100111 : begin data_collision_b_a <= 2'b01; display_wa_wb; end +// 6'b101011 : begin data_collision_b_a <= 2'b00; display_wa_wb; end +// 6'b000001 : begin data_collision_b_a <= 2'b00; display_ra_wb; end + 6'b000101 : begin data_collision_b_a <= 2'b10; display_ra_wb; end +// 6'b001001 : begin data_collision_b_a <= 2'b00; display_ra_wb; end +// 6'b010001 : begin data_collision_b_a <= 2'b00; display_ra_wb; end + 6'b010101 : begin data_collision_b_a <= 2'b10; display_ra_wb; end +// 6'b011001 : begin data_collision_b_a <= 2'b00; display_ra_wb; end +// 6'b100001 : begin data_collision_b_a <= 2'b00; display_ra_wb; end + 6'b100101 : begin data_collision_b_a <= 2'b10; display_ra_wb; end +// 6'b101001 : begin data_collision_b_a <= 2'b00; display_ra_wb; end +// 6'b000010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end +// 6'b000110 : begin data_collision_b_a <= 2'b00; display_wa_rb; end +// 6'b001010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end +// 6'b010010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end +// 6'b010110 : begin data_collision_b_a <= 2'b00; display_wa_rb; end +// 6'b011010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end +// 6'b100010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end +// 6'b100110 : begin data_collision_b_a <= 2'b00; display_wa_rb; end +// 6'b101010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end + endcase + end + end + setup_rf_b_a <= 0; + end + + + always @(posedge clka_int) begin + addra_reg <= addra_int; + ena_reg <= ena_int; + ssra_reg <= ssra_int; + wea_reg <= wea_int; + end + + always @(posedge clkb_int) begin + addrb_reg <= addrb_int; + enb_reg <= enb_int; + ssrb_reg <= ssrb_int; + web_reg <= web_int; + end + + // Data + always @(posedge memory_collision) begin + for (dmi = 0; dmi < 16; dmi = dmi + 1) begin + mem[data_addra_int + dmi] <= 1'bX; + end + memory_collision <= 0; + end + + always @(posedge memory_collision_a_b) begin + for (dmi = 0; dmi < 16; dmi = dmi + 1) begin + mem[data_addra_reg + dmi] <= 1'bX; + end + memory_collision_a_b <= 0; + end + + always @(posedge memory_collision_b_a) begin + for (dmi = 0; dmi < 16; dmi = dmi + 1) begin + mem[data_addra_int + dmi] <= 1'bX; + end + memory_collision_b_a <= 0; + end + + always @(posedge data_collision[1]) begin + if (ssra_int == 0) begin + doa_out <= 16'bX; + end + data_collision[1] <= 0; + end + + always @(posedge data_collision[0]) begin + if (ssrb_int == 0) begin + for (dbi = 0; dbi < 16; dbi = dbi + 1) begin + dob_out[data_addra_int[4 : 0] + dbi] <= 1'bX; + end + end + data_collision[0] <= 0; + end + + always @(posedge data_collision_a_b[1]) begin + if (ssra_reg == 0) begin + doa_out <= 16'bX; + end + data_collision_a_b[1] <= 0; + end + + always @(posedge data_collision_a_b[0]) begin + if (ssrb_int == 0) begin + for (dbi = 0; dbi < 16; dbi = dbi + 1) begin + dob_out[data_addra_reg[4 : 0] + dbi] <= 1'bX; + end + end + data_collision_a_b[0] <= 0; + end + + always @(posedge data_collision_b_a[1]) begin + if (ssra_int == 0) begin + doa_out <= 16'bX; + end + data_collision_b_a[1] <= 0; + end + + always @(posedge data_collision_b_a[0]) begin + if (ssrb_reg == 0) begin + for (dbi = 0; dbi < 16; dbi = dbi + 1) begin + dob_out[data_addra_int[4 : 0] + dbi] <= 1'bX; + end + end + data_collision_b_a[0] <= 0; + end + + + // Parity + always @(posedge memory_collision) begin + for (pmi = 0; pmi < 2; pmi = pmi + 1) begin + mem[parity_addra_int + pmi] <= 1'bX; + end + end + + always @(posedge memory_collision_a_b) begin + for (pmi = 0; pmi < 2; pmi = pmi + 1) begin + mem[parity_addra_reg + pmi] <= 1'bX; + end + end + + always @(posedge memory_collision_b_a) begin + for (pmi = 0; pmi < 2; pmi = pmi + 1) begin + mem[parity_addra_int + pmi] <= 1'bX; + end + end + + always @(posedge data_collision[1]) begin + if (ssra_int == 0) begin + dopa_out <= 2'bX; + end + end + + always @(posedge data_collision[0]) begin + if (ssrb_int == 0) begin + for (pbi = 0; pbi < 2; pbi = pbi + 1) begin + dopb_out[parity_addra_int[0 : 0] + pbi] <= 1'bX; + end + end + end + + always @(posedge data_collision_a_b[1]) begin + if (ssra_reg == 0) begin + dopa_out <= 2'bX; + end + end + + always @(posedge data_collision_a_b[0]) begin + if (ssrb_int == 0) begin + for (pbi = 0; pbi < 2; pbi = pbi + 1) begin + dopb_out[parity_addra_reg[0 : 0] + pbi] <= 1'bX; + end + end + end + + always @(posedge data_collision_b_a[1]) begin + if (ssra_int == 0) begin + dopa_out <= 2'bX; + end + end + + always @(posedge data_collision_b_a[0]) begin + if (ssrb_reg == 0) begin + for (pbi = 0; pbi < 2; pbi = pbi + 1) begin + dopb_out[parity_addra_int[0 : 0] + pbi] <= 1'bX; + end + end + end + + + initial begin + case (WRITE_MODE_A) + "WRITE_FIRST" : wr_mode_a <= 2'b00; + "READ_FIRST" : wr_mode_a <= 2'b01; + "NO_CHANGE" : wr_mode_a <= 2'b10; + default : begin + $display("Attribute Syntax Error : The Attribute WRITE_MODE_A on RAMB16_S18_S36 instance %m is set to %s. Legal values for this attribute are WRITE_FIRST, READ_FIRST or NO_CHANGE.", WRITE_MODE_A); + $finish; + end + endcase + end + + initial begin + case (WRITE_MODE_B) + "WRITE_FIRST" : wr_mode_b <= 2'b00; + "READ_FIRST" : wr_mode_b <= 2'b01; + "NO_CHANGE" : wr_mode_b <= 2'b10; + default : begin + $display("Attribute Syntax Error : The Attribute WRITE_MODE_B on RAMB16_S18_S36 instance %m is set to %s. Legal values for this attribute are WRITE_FIRST, READ_FIRST or NO_CHANGE.", WRITE_MODE_B); + $finish; + end + endcase + end + + // Port A + always @(posedge clka_int) begin + if (ena_int == 1'b1) begin + if (ssra_int == 1'b1) begin + doa_out[0] <= SRVAL_A[0]; + doa_out[1] <= SRVAL_A[1]; + doa_out[2] <= SRVAL_A[2]; + doa_out[3] <= SRVAL_A[3]; + doa_out[4] <= SRVAL_A[4]; + doa_out[5] <= SRVAL_A[5]; + doa_out[6] <= SRVAL_A[6]; + doa_out[7] <= SRVAL_A[7]; + doa_out[8] <= SRVAL_A[8]; + doa_out[9] <= SRVAL_A[9]; + doa_out[10] <= SRVAL_A[10]; + doa_out[11] <= SRVAL_A[11]; + doa_out[12] <= SRVAL_A[12]; + doa_out[13] <= SRVAL_A[13]; + doa_out[14] <= SRVAL_A[14]; + doa_out[15] <= SRVAL_A[15]; + dopa_out[0] <= SRVAL_A[16]; + dopa_out[1] <= SRVAL_A[17]; + end + else begin + if (wea_int == 1'b1) begin + if (wr_mode_a == 2'b00) begin + doa_out <= dia_int; + dopa_out <= dipa_int; + end + else if (wr_mode_a == 2'b01) begin + doa_out[0] <= mem[data_addra_int + 0]; + doa_out[1] <= mem[data_addra_int + 1]; + doa_out[2] <= mem[data_addra_int + 2]; + doa_out[3] <= mem[data_addra_int + 3]; + doa_out[4] <= mem[data_addra_int + 4]; + doa_out[5] <= mem[data_addra_int + 5]; + doa_out[6] <= mem[data_addra_int + 6]; + doa_out[7] <= mem[data_addra_int + 7]; + doa_out[8] <= mem[data_addra_int + 8]; + doa_out[9] <= mem[data_addra_int + 9]; + doa_out[10] <= mem[data_addra_int + 10]; + doa_out[11] <= mem[data_addra_int + 11]; + doa_out[12] <= mem[data_addra_int + 12]; + doa_out[13] <= mem[data_addra_int + 13]; + doa_out[14] <= mem[data_addra_int + 14]; + doa_out[15] <= mem[data_addra_int + 15]; + dopa_out[0] <= mem[parity_addra_int + 0]; + dopa_out[1] <= mem[parity_addra_int + 1]; + end + end + else begin + doa_out[0] <= mem[data_addra_int + 0]; + doa_out[1] <= mem[data_addra_int + 1]; + doa_out[2] <= mem[data_addra_int + 2]; + doa_out[3] <= mem[data_addra_int + 3]; + doa_out[4] <= mem[data_addra_int + 4]; + doa_out[5] <= mem[data_addra_int + 5]; + doa_out[6] <= mem[data_addra_int + 6]; + doa_out[7] <= mem[data_addra_int + 7]; + doa_out[8] <= mem[data_addra_int + 8]; + doa_out[9] <= mem[data_addra_int + 9]; + doa_out[10] <= mem[data_addra_int + 10]; + doa_out[11] <= mem[data_addra_int + 11]; + doa_out[12] <= mem[data_addra_int + 12]; + doa_out[13] <= mem[data_addra_int + 13]; + doa_out[14] <= mem[data_addra_int + 14]; + doa_out[15] <= mem[data_addra_int + 15]; + dopa_out[0] <= mem[parity_addra_int + 0]; + dopa_out[1] <= mem[parity_addra_int + 1]; + end + end + end + end + + always @(posedge clka_int) begin + if (ena_int == 1'b1 && wea_int == 1'b1) begin + mem[data_addra_int + 0] <= dia_int[0]; + mem[data_addra_int + 1] <= dia_int[1]; + mem[data_addra_int + 2] <= dia_int[2]; + mem[data_addra_int + 3] <= dia_int[3]; + mem[data_addra_int + 4] <= dia_int[4]; + mem[data_addra_int + 5] <= dia_int[5]; + mem[data_addra_int + 6] <= dia_int[6]; + mem[data_addra_int + 7] <= dia_int[7]; + mem[data_addra_int + 8] <= dia_int[8]; + mem[data_addra_int + 9] <= dia_int[9]; + mem[data_addra_int + 10] <= dia_int[10]; + mem[data_addra_int + 11] <= dia_int[11]; + mem[data_addra_int + 12] <= dia_int[12]; + mem[data_addra_int + 13] <= dia_int[13]; + mem[data_addra_int + 14] <= dia_int[14]; + mem[data_addra_int + 15] <= dia_int[15]; + mem[parity_addra_int + 0] <= dipa_int[0]; + mem[parity_addra_int + 1] <= dipa_int[1]; + end + end + + // Port B + always @(posedge clkb_int) begin + if (enb_int == 1'b1) begin + if (ssrb_int == 1'b1) begin + dob_out[0] <= SRVAL_B[0]; + dob_out[1] <= SRVAL_B[1]; + dob_out[2] <= SRVAL_B[2]; + dob_out[3] <= SRVAL_B[3]; + dob_out[4] <= SRVAL_B[4]; + dob_out[5] <= SRVAL_B[5]; + dob_out[6] <= SRVAL_B[6]; + dob_out[7] <= SRVAL_B[7]; + dob_out[8] <= SRVAL_B[8]; + dob_out[9] <= SRVAL_B[9]; + dob_out[10] <= SRVAL_B[10]; + dob_out[11] <= SRVAL_B[11]; + dob_out[12] <= SRVAL_B[12]; + dob_out[13] <= SRVAL_B[13]; + dob_out[14] <= SRVAL_B[14]; + dob_out[15] <= SRVAL_B[15]; + dob_out[16] <= SRVAL_B[16]; + dob_out[17] <= SRVAL_B[17]; + dob_out[18] <= SRVAL_B[18]; + dob_out[19] <= SRVAL_B[19]; + dob_out[20] <= SRVAL_B[20]; + dob_out[21] <= SRVAL_B[21]; + dob_out[22] <= SRVAL_B[22]; + dob_out[23] <= SRVAL_B[23]; + dob_out[24] <= SRVAL_B[24]; + dob_out[25] <= SRVAL_B[25]; + dob_out[26] <= SRVAL_B[26]; + dob_out[27] <= SRVAL_B[27]; + dob_out[28] <= SRVAL_B[28]; + dob_out[29] <= SRVAL_B[29]; + dob_out[30] <= SRVAL_B[30]; + dob_out[31] <= SRVAL_B[31]; + dopb_out[0] <= SRVAL_B[32]; + dopb_out[1] <= SRVAL_B[33]; + dopb_out[2] <= SRVAL_B[34]; + dopb_out[3] <= SRVAL_B[35]; + end + else begin + if (web_int == 1'b1) begin + if (wr_mode_b == 2'b00) begin + dob_out <= dib_int; + dopb_out <= dipb_int; + end + else if (wr_mode_b == 2'b01) begin + dob_out[0] <= mem[data_addrb_int + 0]; + dob_out[1] <= mem[data_addrb_int + 1]; + dob_out[2] <= mem[data_addrb_int + 2]; + dob_out[3] <= mem[data_addrb_int + 3]; + dob_out[4] <= mem[data_addrb_int + 4]; + dob_out[5] <= mem[data_addrb_int + 5]; + dob_out[6] <= mem[data_addrb_int + 6]; + dob_out[7] <= mem[data_addrb_int + 7]; + dob_out[8] <= mem[data_addrb_int + 8]; + dob_out[9] <= mem[data_addrb_int + 9]; + dob_out[10] <= mem[data_addrb_int + 10]; + dob_out[11] <= mem[data_addrb_int + 11]; + dob_out[12] <= mem[data_addrb_int + 12]; + dob_out[13] <= mem[data_addrb_int + 13]; + dob_out[14] <= mem[data_addrb_int + 14]; + dob_out[15] <= mem[data_addrb_int + 15]; + dob_out[16] <= mem[data_addrb_int + 16]; + dob_out[17] <= mem[data_addrb_int + 17]; + dob_out[18] <= mem[data_addrb_int + 18]; + dob_out[19] <= mem[data_addrb_int + 19]; + dob_out[20] <= mem[data_addrb_int + 20]; + dob_out[21] <= mem[data_addrb_int + 21]; + dob_out[22] <= mem[data_addrb_int + 22]; + dob_out[23] <= mem[data_addrb_int + 23]; + dob_out[24] <= mem[data_addrb_int + 24]; + dob_out[25] <= mem[data_addrb_int + 25]; + dob_out[26] <= mem[data_addrb_int + 26]; + dob_out[27] <= mem[data_addrb_int + 27]; + dob_out[28] <= mem[data_addrb_int + 28]; + dob_out[29] <= mem[data_addrb_int + 29]; + dob_out[30] <= mem[data_addrb_int + 30]; + dob_out[31] <= mem[data_addrb_int + 31]; + dopb_out[0] <= mem[parity_addrb_int + 0]; + dopb_out[1] <= mem[parity_addrb_int + 1]; + dopb_out[2] <= mem[parity_addrb_int + 2]; + dopb_out[3] <= mem[parity_addrb_int + 3]; + end + end + else begin + dob_out[0] <= mem[data_addrb_int + 0]; + dob_out[1] <= mem[data_addrb_int + 1]; + dob_out[2] <= mem[data_addrb_int + 2]; + dob_out[3] <= mem[data_addrb_int + 3]; + dob_out[4] <= mem[data_addrb_int + 4]; + dob_out[5] <= mem[data_addrb_int + 5]; + dob_out[6] <= mem[data_addrb_int + 6]; + dob_out[7] <= mem[data_addrb_int + 7]; + dob_out[8] <= mem[data_addrb_int + 8]; + dob_out[9] <= mem[data_addrb_int + 9]; + dob_out[10] <= mem[data_addrb_int + 10]; + dob_out[11] <= mem[data_addrb_int + 11]; + dob_out[12] <= mem[data_addrb_int + 12]; + dob_out[13] <= mem[data_addrb_int + 13]; + dob_out[14] <= mem[data_addrb_int + 14]; + dob_out[15] <= mem[data_addrb_int + 15]; + dob_out[16] <= mem[data_addrb_int + 16]; + dob_out[17] <= mem[data_addrb_int + 17]; + dob_out[18] <= mem[data_addrb_int + 18]; + dob_out[19] <= mem[data_addrb_int + 19]; + dob_out[20] <= mem[data_addrb_int + 20]; + dob_out[21] <= mem[data_addrb_int + 21]; + dob_out[22] <= mem[data_addrb_int + 22]; + dob_out[23] <= mem[data_addrb_int + 23]; + dob_out[24] <= mem[data_addrb_int + 24]; + dob_out[25] <= mem[data_addrb_int + 25]; + dob_out[26] <= mem[data_addrb_int + 26]; + dob_out[27] <= mem[data_addrb_int + 27]; + dob_out[28] <= mem[data_addrb_int + 28]; + dob_out[29] <= mem[data_addrb_int + 29]; + dob_out[30] <= mem[data_addrb_int + 30]; + dob_out[31] <= mem[data_addrb_int + 31]; + dopb_out[0] <= mem[parity_addrb_int + 0]; + dopb_out[1] <= mem[parity_addrb_int + 1]; + dopb_out[2] <= mem[parity_addrb_int + 2]; + dopb_out[3] <= mem[parity_addrb_int + 3]; + end + end + end + end + + always @(posedge clkb_int) begin + if (enb_int == 1'b1 && web_int == 1'b1) begin + mem[data_addrb_int + 0] <= dib_int[0]; + mem[data_addrb_int + 1] <= dib_int[1]; + mem[data_addrb_int + 2] <= dib_int[2]; + mem[data_addrb_int + 3] <= dib_int[3]; + mem[data_addrb_int + 4] <= dib_int[4]; + mem[data_addrb_int + 5] <= dib_int[5]; + mem[data_addrb_int + 6] <= dib_int[6]; + mem[data_addrb_int + 7] <= dib_int[7]; + mem[data_addrb_int + 8] <= dib_int[8]; + mem[data_addrb_int + 9] <= dib_int[9]; + mem[data_addrb_int + 10] <= dib_int[10]; + mem[data_addrb_int + 11] <= dib_int[11]; + mem[data_addrb_int + 12] <= dib_int[12]; + mem[data_addrb_int + 13] <= dib_int[13]; + mem[data_addrb_int + 14] <= dib_int[14]; + mem[data_addrb_int + 15] <= dib_int[15]; + mem[data_addrb_int + 16] <= dib_int[16]; + mem[data_addrb_int + 17] <= dib_int[17]; + mem[data_addrb_int + 18] <= dib_int[18]; + mem[data_addrb_int + 19] <= dib_int[19]; + mem[data_addrb_int + 20] <= dib_int[20]; + mem[data_addrb_int + 21] <= dib_int[21]; + mem[data_addrb_int + 22] <= dib_int[22]; + mem[data_addrb_int + 23] <= dib_int[23]; + mem[data_addrb_int + 24] <= dib_int[24]; + mem[data_addrb_int + 25] <= dib_int[25]; + mem[data_addrb_int + 26] <= dib_int[26]; + mem[data_addrb_int + 27] <= dib_int[27]; + mem[data_addrb_int + 28] <= dib_int[28]; + mem[data_addrb_int + 29] <= dib_int[29]; + mem[data_addrb_int + 30] <= dib_int[30]; + mem[data_addrb_int + 31] <= dib_int[31]; + mem[parity_addrb_int + 0] <= dipb_int[0]; + mem[parity_addrb_int + 1] <= dipb_int[1]; + mem[parity_addrb_int + 2] <= dipb_int[2]; + mem[parity_addrb_int + 3] <= dipb_int[3]; + end + end + + specify + (CLKA *> DOA) = (100, 100); + (CLKA *> DOPA) = (100, 100); + (CLKB *> DOB) = (100, 100); + (CLKB *> DOPB) = (100, 100); + endspecify + +endmodule + +`else + +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/RAMB16_S18_S36.v,v 1.10 2007/02/22 01:58:05 wloo Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2005 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Timing Simulation Library Component +// / / 16K-Bit Data and 2K-Bit Parity Dual Port Block RAM +// /___/ /\ Filename : RAMB16_S18_S36.v +// \ \ / \ Timestamp : Thu Mar 10 16:44:01 PST 2005 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 03/10/05 - Initialized outputs. +// 02/21/07 - Fixed parameter SIM_COLLISION_CHECK (CR 433281). +// End Revision + +`timescale 1 ps/1 ps + +module RAMB16_S18_S36 (DOA, DOB, DOPA, DOPB, ADDRA, ADDRB, CLKA, CLKB, DIA, DIB, DIPA, DIPB, ENA, ENB, SSRA, SSRB, WEA, WEB); + + parameter INIT_A = 18'h0; + parameter INIT_B = 36'h0; + parameter SRVAL_A = 18'h0; + parameter SRVAL_B = 36'h0; + parameter WRITE_MODE_A = "WRITE_FIRST"; + parameter WRITE_MODE_B = "WRITE_FIRST"; + parameter SIM_COLLISION_CHECK = "ALL"; + localparam SETUP_ALL = 1000; + localparam SETUP_READ_FIRST = 3000; + + parameter INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + + output [15:0] DOA; + output [1:0] DOPA; + output [31:0] DOB; + output [3:0] DOPB; + + input [9:0] ADDRA; + input [15:0] DIA; + input [1:0] DIPA; + input ENA, CLKA, WEA, SSRA; + input [8:0] ADDRB; + input [31:0] DIB; + input [3:0] DIPB; + input ENB, CLKB, WEB, SSRB; + + reg [15:0] doa_out = INIT_A[15:0]; + reg [1:0] dopa_out = INIT_A[17:16]; + reg [31:0] dob_out = INIT_B[31:0]; + reg [3:0] dopb_out = INIT_B[35:32]; + + reg [31:0] mem [511:0]; + reg [3:0] memp [511:0]; + + reg [8:0] count, countp; + reg [1:0] wr_mode_a, wr_mode_b; + + reg [5:0] dmi, dbi; + reg [5:0] pmi, pbi; + + wire [9:0] addra_int; + reg [9:0] addra_reg; + wire [15:0] dia_int; + wire [1:0] dipa_int; + wire ena_int, clka_int, wea_int, ssra_int; + reg ena_reg, wea_reg, ssra_reg; + wire [8:0] addrb_int; + reg [8:0] addrb_reg; + wire [31:0] dib_int; + wire [3:0] dipb_int; + wire enb_int, clkb_int, web_int, ssrb_int; + reg display_flag, output_flag; + reg enb_reg, web_reg, ssrb_reg; + + time time_clka, time_clkb; + time time_clka_clkb; + time time_clkb_clka; + + reg setup_all_a_b; + reg setup_all_b_a; + reg setup_zero; + reg setup_rf_a_b; + reg setup_rf_b_a; + reg [1:0] data_collision, data_collision_a_b, data_collision_b_a; + reg memory_collision, memory_collision_a_b, memory_collision_b_a; + reg change_clka; + reg change_clkb; + + wire [14:0] data_addra_int; + wire [14:0] data_addra_reg; + wire [14:0] data_addrb_int; + wire [14:0] data_addrb_reg; + + wire dia_enable = ena_int && wea_int; + wire dib_enable = enb_int && web_int; + + tri0 GSR = glbl.GSR; + wire gsr_int; + + buf b_gsr (gsr_int, GSR); + + buf b_doa [15:0] (DOA, doa_out); + buf b_dopa [1:0] (DOPA, dopa_out); + buf b_addra [9:0] (addra_int, ADDRA); + buf b_dia [15:0] (dia_int, DIA); + buf b_dipa [1:0] (dipa_int, DIPA); + buf b_ena (ena_int, ENA); + buf b_clka (clka_int, CLKA); + buf b_ssra (ssra_int, SSRA); + buf b_wea (wea_int, WEA); + + buf b_dob [31:0] (DOB, dob_out); + buf b_dopb [3:0] (DOPB, dopb_out); + buf b_addrb [8:0] (addrb_int, ADDRB); + buf b_dib [31:0] (dib_int, DIB); + buf b_dipb [3:0] (dipb_int, DIPB); + buf b_enb (enb_int, ENB); + buf b_clkb (clkb_int, CLKB); + buf b_ssrb (ssrb_int, SSRB); + buf b_web (web_int, WEB); + + + always @(gsr_int) + if (gsr_int) begin + assign {dopa_out, doa_out} = INIT_A; + assign {dopb_out, dob_out} = INIT_B; + end + else begin + deassign doa_out; + deassign dopa_out; + deassign dob_out; + deassign dopb_out; + end + + + initial begin + + for (count = 0; count < 8; count = count + 1) begin + mem[count] = INIT_00[(count * 32) +: 32]; + mem[8 * 1 + count] = INIT_01[(count * 32) +: 32]; + mem[8 * 2 + count] = INIT_02[(count * 32) +: 32]; + mem[8 * 3 + count] = INIT_03[(count * 32) +: 32]; + mem[8 * 4 + count] = INIT_04[(count * 32) +: 32]; + mem[8 * 5 + count] = INIT_05[(count * 32) +: 32]; + mem[8 * 6 + count] = INIT_06[(count * 32) +: 32]; + mem[8 * 7 + count] = INIT_07[(count * 32) +: 32]; + mem[8 * 8 + count] = INIT_08[(count * 32) +: 32]; + mem[8 * 9 + count] = INIT_09[(count * 32) +: 32]; + mem[8 * 10 + count] = INIT_0A[(count * 32) +: 32]; + mem[8 * 11 + count] = INIT_0B[(count * 32) +: 32]; + mem[8 * 12 + count] = INIT_0C[(count * 32) +: 32]; + mem[8 * 13 + count] = INIT_0D[(count * 32) +: 32]; + mem[8 * 14 + count] = INIT_0E[(count * 32) +: 32]; + mem[8 * 15 + count] = INIT_0F[(count * 32) +: 32]; + mem[8 * 16 + count] = INIT_10[(count * 32) +: 32]; + mem[8 * 17 + count] = INIT_11[(count * 32) +: 32]; + mem[8 * 18 + count] = INIT_12[(count * 32) +: 32]; + mem[8 * 19 + count] = INIT_13[(count * 32) +: 32]; + mem[8 * 20 + count] = INIT_14[(count * 32) +: 32]; + mem[8 * 21 + count] = INIT_15[(count * 32) +: 32]; + mem[8 * 22 + count] = INIT_16[(count * 32) +: 32]; + mem[8 * 23 + count] = INIT_17[(count * 32) +: 32]; + mem[8 * 24 + count] = INIT_18[(count * 32) +: 32]; + mem[8 * 25 + count] = INIT_19[(count * 32) +: 32]; + mem[8 * 26 + count] = INIT_1A[(count * 32) +: 32]; + mem[8 * 27 + count] = INIT_1B[(count * 32) +: 32]; + mem[8 * 28 + count] = INIT_1C[(count * 32) +: 32]; + mem[8 * 29 + count] = INIT_1D[(count * 32) +: 32]; + mem[8 * 30 + count] = INIT_1E[(count * 32) +: 32]; + mem[8 * 31 + count] = INIT_1F[(count * 32) +: 32]; + mem[8 * 32 + count] = INIT_20[(count * 32) +: 32]; + mem[8 * 33 + count] = INIT_21[(count * 32) +: 32]; + mem[8 * 34 + count] = INIT_22[(count * 32) +: 32]; + mem[8 * 35 + count] = INIT_23[(count * 32) +: 32]; + mem[8 * 36 + count] = INIT_24[(count * 32) +: 32]; + mem[8 * 37 + count] = INIT_25[(count * 32) +: 32]; + mem[8 * 38 + count] = INIT_26[(count * 32) +: 32]; + mem[8 * 39 + count] = INIT_27[(count * 32) +: 32]; + mem[8 * 40 + count] = INIT_28[(count * 32) +: 32]; + mem[8 * 41 + count] = INIT_29[(count * 32) +: 32]; + mem[8 * 42 + count] = INIT_2A[(count * 32) +: 32]; + mem[8 * 43 + count] = INIT_2B[(count * 32) +: 32]; + mem[8 * 44 + count] = INIT_2C[(count * 32) +: 32]; + mem[8 * 45 + count] = INIT_2D[(count * 32) +: 32]; + mem[8 * 46 + count] = INIT_2E[(count * 32) +: 32]; + mem[8 * 47 + count] = INIT_2F[(count * 32) +: 32]; + mem[8 * 48 + count] = INIT_30[(count * 32) +: 32]; + mem[8 * 49 + count] = INIT_31[(count * 32) +: 32]; + mem[8 * 50 + count] = INIT_32[(count * 32) +: 32]; + mem[8 * 51 + count] = INIT_33[(count * 32) +: 32]; + mem[8 * 52 + count] = INIT_34[(count * 32) +: 32]; + mem[8 * 53 + count] = INIT_35[(count * 32) +: 32]; + mem[8 * 54 + count] = INIT_36[(count * 32) +: 32]; + mem[8 * 55 + count] = INIT_37[(count * 32) +: 32]; + mem[8 * 56 + count] = INIT_38[(count * 32) +: 32]; + mem[8 * 57 + count] = INIT_39[(count * 32) +: 32]; + mem[8 * 58 + count] = INIT_3A[(count * 32) +: 32]; + mem[8 * 59 + count] = INIT_3B[(count * 32) +: 32]; + mem[8 * 60 + count] = INIT_3C[(count * 32) +: 32]; + mem[8 * 61 + count] = INIT_3D[(count * 32) +: 32]; + mem[8 * 62 + count] = INIT_3E[(count * 32) +: 32]; + mem[8 * 63 + count] = INIT_3F[(count * 32) +: 32]; + end + +// initiate parity start + for (countp = 0; countp < 64; countp = countp + 1) begin + memp[countp] = INITP_00[(countp * 4) +: 4]; + memp[64 * 1 + countp] = INITP_01[(countp * 4) +: 4]; + memp[64 * 2 + countp] = INITP_02[(countp * 4) +: 4]; + memp[64 * 3 + countp] = INITP_03[(countp * 4) +: 4]; + memp[64 * 4 + countp] = INITP_04[(countp * 4) +: 4]; + memp[64 * 5 + countp] = INITP_05[(countp * 4) +: 4]; + memp[64 * 6 + countp] = INITP_06[(countp * 4) +: 4]; + memp[64 * 7 + countp] = INITP_07[(countp * 4) +: 4]; + end +// initiate parity end + + change_clka <= 0; + change_clkb <= 0; + data_collision <= 0; + data_collision_a_b <= 0; + data_collision_b_a <= 0; + memory_collision <= 0; + memory_collision_a_b <= 0; + memory_collision_b_a <= 0; + setup_all_a_b <= 0; + setup_all_b_a <= 0; + setup_zero <= 0; + setup_rf_a_b <= 0; + setup_rf_b_a <= 0; + end + + assign data_addra_int = addra_int * 16; + assign data_addra_reg = addra_reg * 16; + assign data_addrb_int = addrb_int * 32; + assign data_addrb_reg = addrb_reg * 32; + + + initial begin + + display_flag = 1; + output_flag = 1; + + case (SIM_COLLISION_CHECK) + + "NONE" : begin + output_flag = 0; + display_flag = 0; + end + "WARNING_ONLY" : output_flag = 0; + "GENERATE_X_ONLY" : display_flag = 0; + "ALL" : ; + + default : begin + $display("Attribute Syntax Error : The Attribute SIM_COLLISION_CHECK on RAMB16_S18_S36 instance %m is set to %s. Legal values for this attribute are ALL, NONE, WARNING_ONLY or GENERATE_X_ONLY.", SIM_COLLISION_CHECK); + $finish; + end + + endcase // case(SIM_COLLISION_CHECK) + + end // initial begin + + + always @(posedge clka_int) begin + if ((output_flag || display_flag)) begin + time_clka = $time; + #0 time_clkb_clka = time_clka - time_clkb; + change_clka = ~change_clka; + end + end + + always @(posedge clkb_int) begin + if ((output_flag || display_flag)) begin + time_clkb = $time; + #0 time_clka_clkb = time_clkb - time_clka; + change_clkb = ~change_clkb; + end + end + + always @(change_clkb) begin + if ((0 < time_clka_clkb) && (time_clka_clkb < SETUP_ALL)) + setup_all_a_b = 1; + if ((0 < time_clka_clkb) && (time_clka_clkb < SETUP_READ_FIRST)) + setup_rf_a_b = 1; + end + + always @(change_clka) begin + if ((0 < time_clkb_clka) && (time_clkb_clka < SETUP_ALL)) + setup_all_b_a = 1; + if ((0 < time_clkb_clka) && (time_clkb_clka < SETUP_READ_FIRST)) + setup_rf_b_a = 1; + end + + always @(change_clkb or change_clka) begin + if ((time_clkb_clka == 0) && (time_clka_clkb == 0)) + setup_zero = 1; + end + + always @(posedge setup_zero) begin + if ((ena_int == 1) && (wea_int == 1) && + (enb_int == 1) && (web_int == 1) && + (data_addra_int[14:5] == data_addrb_int[14:5])) + memory_collision <= 1; + end + + always @(posedge setup_all_a_b or posedge setup_rf_a_b) begin + if ((ena_reg == 1) && (wea_reg == 1) && + (enb_int == 1) && (web_int == 1) && + (data_addra_reg[14:5] == data_addrb_int[14:5])) + memory_collision_a_b <= 1; + end + + always @(posedge setup_all_b_a or posedge setup_rf_b_a) begin + if ((ena_int == 1) && (wea_int == 1) && + (enb_reg == 1) && (web_reg == 1) && + (data_addra_int[14:5] == data_addrb_reg[14:5])) + memory_collision_b_a <= 1; + end + + always @(posedge setup_all_a_b) begin + if (data_addra_reg[14:5] == data_addrb_int[14:5]) begin + if ((ena_reg == 1) && (enb_int == 1)) begin + case ({wr_mode_a, wr_mode_b, wea_reg, web_int}) + 6'b000011 : begin data_collision_a_b <= 2'b11; display_wa_wb; end + 6'b000111 : begin data_collision_a_b <= 2'b11; display_wa_wb; end + 6'b001011 : begin data_collision_a_b <= 2'b10; display_wa_wb; end +// 6'b010011 : begin data_collision_a_b <= 2'b00; display_wa_wb; end +// 6'b010111 : begin data_collision_a_b <= 2'b00; display_wa_wb; end +// 6'b011011 : begin data_collision_a_b <= 2'b00; display_wa_wb; end + 6'b100011 : begin data_collision_a_b <= 2'b01; display_wa_wb; end + 6'b100111 : begin data_collision_a_b <= 2'b01; display_wa_wb; end + 6'b101011 : begin display_wa_wb; end + 6'b000001 : begin data_collision_a_b <= 2'b10; display_ra_wb; end +// 6'b000101 : begin data_collision_a_b <= 2'b00; display_ra_wb; end + 6'b001001 : begin data_collision_a_b <= 2'b10; display_ra_wb; end + 6'b010001 : begin data_collision_a_b <= 2'b10; display_ra_wb; end +// 6'b010101 : begin data_collision_a_b <= 2'b00; display_ra_wb; end + 6'b011001 : begin data_collision_a_b <= 2'b10; display_ra_wb; end + 6'b100001 : begin data_collision_a_b <= 2'b10; display_ra_wb; end +// 6'b100101 : begin data_collision_a_b <= 2'b00; display_ra_wb; end + 6'b101001 : begin data_collision_a_b <= 2'b10; display_ra_wb; end + 6'b000010 : begin data_collision_a_b <= 2'b01; display_wa_rb; end + 6'b000110 : begin data_collision_a_b <= 2'b01; display_wa_rb; end + 6'b001010 : begin data_collision_a_b <= 2'b01; display_wa_rb; end +// 6'b010010 : begin data_collision_a_b <= 2'b00; display_wa_rb; end +// 6'b010110 : begin data_collision_a_b <= 2'b00; display_wa_rb; end +// 6'b011010 : begin data_collision_a_b <= 2'b00; display_wa_rb; end + 6'b100010 : begin data_collision_a_b <= 2'b01; display_wa_rb; end + 6'b100110 : begin data_collision_a_b <= 2'b01; display_wa_rb; end + 6'b101010 : begin data_collision_a_b <= 2'b01; display_wa_rb; end + endcase + end + end + setup_all_a_b <= 0; + end + + + always @(posedge setup_all_b_a) begin + if (data_addra_int[14:5] == data_addrb_reg[14:5]) begin + if ((ena_int == 1) && (enb_reg == 1)) begin + case ({wr_mode_a, wr_mode_b, wea_int, web_reg}) + 6'b000011 : begin data_collision_b_a <= 2'b11; display_wa_wb; end +// 6'b000111 : begin data_collision_b_a <= 2'b00; display_wa_wb; end + 6'b001011 : begin data_collision_b_a <= 2'b10; display_wa_wb; end + 6'b010011 : begin data_collision_b_a <= 2'b11; display_wa_wb; end +// 6'b010111 : begin data_collision_b_a <= 2'b00; display_wa_wb; end + 6'b011011 : begin data_collision_b_a <= 2'b10; display_wa_wb; end + 6'b100011 : begin data_collision_b_a <= 2'b01; display_wa_wb; end + 6'b100111 : begin data_collision_b_a <= 2'b01; display_wa_wb; end + 6'b101011 : begin display_wa_wb; end + 6'b000001 : begin data_collision_b_a <= 2'b10; display_ra_wb; end + 6'b000101 : begin data_collision_b_a <= 2'b10; display_ra_wb; end + 6'b001001 : begin data_collision_b_a <= 2'b10; display_ra_wb; end + 6'b010001 : begin data_collision_b_a <= 2'b10; display_ra_wb; end + 6'b010101 : begin data_collision_b_a <= 2'b10; display_ra_wb; end + 6'b011001 : begin data_collision_b_a <= 2'b10; display_ra_wb; end + 6'b100001 : begin data_collision_b_a <= 2'b10; display_ra_wb; end + 6'b100101 : begin data_collision_b_a <= 2'b10; display_ra_wb; end + 6'b101001 : begin data_collision_b_a <= 2'b10; display_ra_wb; end + 6'b000010 : begin data_collision_b_a <= 2'b01; display_wa_rb; end + 6'b000110 : begin data_collision_b_a <= 2'b01; display_wa_rb; end + 6'b001010 : begin data_collision_b_a <= 2'b01; display_wa_rb; end +// 6'b010010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end +// 6'b010110 : begin data_collision_b_a <= 2'b00; display_wa_rb; end +// 6'b011010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end + 6'b100010 : begin data_collision_b_a <= 2'b01; display_wa_rb; end + 6'b100110 : begin data_collision_b_a <= 2'b01; display_wa_rb; end + 6'b101010 : begin data_collision_b_a <= 2'b01; display_wa_rb; end + endcase + end + end + setup_all_b_a <= 0; + end + + + always @(posedge setup_zero) begin + if (data_addra_int[14:5] == data_addrb_int[14:5]) begin + if ((ena_int == 1) && (enb_int == 1)) begin + case ({wr_mode_a, wr_mode_b, wea_int, web_int}) + 6'b000011 : begin data_collision <= 2'b11; display_wa_wb; end + 6'b000111 : begin data_collision <= 2'b11; display_wa_wb; end + 6'b001011 : begin data_collision <= 2'b10; display_wa_wb; end + 6'b010011 : begin data_collision <= 2'b11; display_wa_wb; end + 6'b010111 : begin data_collision <= 2'b11; display_wa_wb; end + 6'b011011 : begin data_collision <= 2'b10; display_wa_wb; end + 6'b100011 : begin data_collision <= 2'b01; display_wa_wb; end + 6'b100111 : begin data_collision <= 2'b01; display_wa_wb; end + 6'b101011 : begin display_wa_wb; end + 6'b000001 : begin data_collision <= 2'b10; display_ra_wb; end +// 6'b000101 : begin data_collision <= 2'b00; display_ra_wb; end + 6'b001001 : begin data_collision <= 2'b10; display_ra_wb; end + 6'b010001 : begin data_collision <= 2'b10; display_ra_wb; end +// 6'b010101 : begin data_collision <= 2'b00; display_ra_wb; end + 6'b011001 : begin data_collision <= 2'b10; display_ra_wb; end + 6'b100001 : begin data_collision <= 2'b10; display_ra_wb; end +// 6'b100101 : begin data_collision <= 2'b00; display_ra_wb; end + 6'b101001 : begin data_collision <= 2'b10; display_ra_wb; end + 6'b000010 : begin data_collision <= 2'b01; display_wa_rb; end + 6'b000110 : begin data_collision <= 2'b01; display_wa_rb; end + 6'b001010 : begin data_collision <= 2'b01; display_wa_rb; end +// 6'b010010 : begin data_collision <= 2'b00; display_wa_rb; end +// 6'b010110 : begin data_collision <= 2'b00; display_wa_rb; end +// 6'b011010 : begin data_collision <= 2'b00; display_wa_rb; end + 6'b100010 : begin data_collision <= 2'b01; display_wa_rb; end + 6'b100110 : begin data_collision <= 2'b01; display_wa_rb; end + 6'b101010 : begin data_collision <= 2'b01; display_wa_rb; end + endcase + end + end + setup_zero <= 0; + end + + task display_ra_wb; + begin + if (display_flag) + $display("Memory Collision Error on RAMB16_S18_S36:%m at simulation time %.3f ns\nA read was performed on address %h (hex) of Port A while a write was requested to the same address on Port B. The write will be successful however the read value on Port A is unknown until the next CLKA cycle.", $time/1000.0, addra_int); + end + endtask + + task display_wa_rb; + begin + if (display_flag) + $display("Memory Collision Error on RAMB16_S18_S36:%m at simulation time %.3f ns\nA read was performed on address %h (hex) of Port B while a write was requested to the same address on Port A. The write will be successful however the read value on Port B is unknown until the next CLKB cycle.", $time/1000.0, addrb_int); + end + endtask + + task display_wa_wb; + begin + if (display_flag) + $display("Memory Collision Error on RAMB16_S18_S36:%m at simulation time %.3f ns\nA write was requested to the same address simultaneously at both Port A and Port B of the RAM. The contents written to the RAM at address location %h (hex) of Port A and address location %h (hex) of Port B are unknown.", $time/1000.0, addra_int, addrb_int); + end + endtask + + + always @(posedge setup_rf_a_b) begin + if (data_addra_reg[14:5] == data_addrb_int[14:5]) begin + if ((ena_reg == 1) && (enb_int == 1)) begin + case ({wr_mode_a, wr_mode_b, wea_reg, web_int}) +// 6'b000011 : begin data_collision_a_b <= 2'b00; display_wa_wb; end +// 6'b000111 : begin data_collision_a_b <= 2'b00; display_wa_wb; end +// 6'b001011 : begin data_collision_a_b <= 2'b00; display_wa_wb; end + 6'b010011 : begin data_collision_a_b <= 2'b11; display_wa_wb; end + 6'b010111 : begin data_collision_a_b <= 2'b11; display_wa_wb; end + 6'b011011 : begin data_collision_a_b <= 2'b10; display_wa_wb; end +// 6'b100011 : begin data_collision_a_b <= 2'b00; display_wa_wb; end +// 6'b100111 : begin data_collision_a_b <= 2'b00; display_wa_wb; end +// 6'b101011 : begin data_collision_a_b <= 2'b00; display_wa_wb; end +// 6'b000001 : begin data_collision_a_b <= 2'b00; display_ra_wb; end +// 6'b000101 : begin data_collision_a_b <= 2'b00; display_ra_wb; end +// 6'b001001 : begin data_collision_a_b <= 2'b00; display_ra_wb; end +// 6'b010001 : begin data_collision_a_b <= 2'b00; display_ra_wb; end +// 6'b010101 : begin data_collision_a_b <= 2'b00; display_ra_wb; end +// 6'b011001 : begin data_collision_a_b <= 2'b00; display_ra_wb; end +// 6'b100001 : begin data_collision_a_b <= 2'b00; display_ra_wb; end +// 6'b100101 : begin data_collision_a_b <= 2'b00; display_ra_wb; end +// 6'b101001 : begin data_collision_a_b <= 2'b00; display_ra_wb; end +// 6'b000010 : begin data_collision_a_b <= 2'b00; display_wa_rb; end +// 6'b000110 : begin data_collision_a_b <= 2'b00; display_wa_rb; end +// 6'b001010 : begin data_collision_a_b <= 2'b00; display_wa_rb; end + 6'b010010 : begin data_collision_a_b <= 2'b01; display_wa_rb; end + 6'b010110 : begin data_collision_a_b <= 2'b01; display_wa_rb; end + 6'b011010 : begin data_collision_a_b <= 2'b01; display_wa_rb; end +// 6'b100010 : begin data_collision_a_b <= 2'b00; display_wa_rb; end +// 6'b100110 : begin data_collision_a_b <= 2'b00; display_wa_rb; end +// 6'b101010 : begin data_collision_a_b <= 2'b00; display_wa_rb; end + endcase + end + end + setup_rf_a_b <= 0; + end + + + always @(posedge setup_rf_b_a) begin + if (data_addra_int[14:5] == data_addrb_reg[14:5]) begin + if ((ena_int == 1) && (enb_reg == 1)) begin + case ({wr_mode_a, wr_mode_b, wea_int, web_reg}) +// 6'b000011 : begin data_collision_b_a <= 2'b00; display_wa_wb; end + 6'b000111 : begin data_collision_b_a <= 2'b11; display_wa_wb; end +// 6'b001011 : begin data_collision_b_a <= 2'b00; display_wa_wb; end +// 6'b010011 : begin data_collision_b_a <= 2'b00; display_wa_wb; end + 6'b010111 : begin data_collision_b_a <= 2'b11; display_wa_wb; end +// 6'b011011 : begin data_collision_b_a <= 2'b00; display_wa_wb; end +// 6'b100011 : begin data_collision_b_a <= 2'b00; display_wa_wb; end + 6'b100111 : begin data_collision_b_a <= 2'b01; display_wa_wb; end +// 6'b101011 : begin data_collision_b_a <= 2'b00; display_wa_wb; end +// 6'b000001 : begin data_collision_b_a <= 2'b00; display_ra_wb; end + 6'b000101 : begin data_collision_b_a <= 2'b10; display_ra_wb; end +// 6'b001001 : begin data_collision_b_a <= 2'b00; display_ra_wb; end +// 6'b010001 : begin data_collision_b_a <= 2'b00; display_ra_wb; end + 6'b010101 : begin data_collision_b_a <= 2'b10; display_ra_wb; end +// 6'b011001 : begin data_collision_b_a <= 2'b00; display_ra_wb; end +// 6'b100001 : begin data_collision_b_a <= 2'b00; display_ra_wb; end + 6'b100101 : begin data_collision_b_a <= 2'b10; display_ra_wb; end +// 6'b101001 : begin data_collision_b_a <= 2'b00; display_ra_wb; end +// 6'b000010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end +// 6'b000110 : begin data_collision_b_a <= 2'b00; display_wa_rb; end +// 6'b001010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end +// 6'b010010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end +// 6'b010110 : begin data_collision_b_a <= 2'b00; display_wa_rb; end +// 6'b011010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end +// 6'b100010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end +// 6'b100110 : begin data_collision_b_a <= 2'b00; display_wa_rb; end +// 6'b101010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end + endcase + end + end + setup_rf_b_a <= 0; + end + + + always @(posedge clka_int) begin + if ((output_flag || display_flag)) begin + addra_reg <= addra_int; + ena_reg <= ena_int; + ssra_reg <= ssra_int; + wea_reg <= wea_int; + end + end + + always @(posedge clkb_int) begin + if ((output_flag || display_flag)) begin + addrb_reg <= addrb_int; + enb_reg <= enb_int; + ssrb_reg <= ssrb_int; + web_reg <= web_int; + end + end + + + // Data + always @(posedge memory_collision) begin + if ((output_flag || display_flag)) begin + mem[addra_int[9:1]][addra_int[0:0] * 16 +: 16] <= 16'bx; + memory_collision <= 0; + end + + end + + always @(posedge memory_collision_a_b) begin + if ((output_flag || display_flag)) begin + mem[addra_reg[9:1]][addra_reg[0:0] * 16 +: 16] <= 16'bx; + memory_collision_a_b <= 0; + end + end + + always @(posedge memory_collision_b_a) begin + if ((output_flag || display_flag)) begin + mem[addra_int[9:1]][addra_int[0:0] * 16 +: 16] <= 16'bx; + memory_collision_b_a <= 0; + end + end + + always @(posedge data_collision[1]) begin + if (ssra_int == 0 && output_flag) begin + doa_out <= #100 16'bX; + end + data_collision[1] <= 0; + end + + always @(posedge data_collision[0]) begin + if (ssrb_int == 0 && output_flag) begin + dob_out[addra_int[0:0] * 16 +: 16] <= #100 16'bX; + end + data_collision[0] <= 0; + end + + always @(posedge data_collision_a_b[1]) begin + if (ssra_reg == 0 && output_flag) begin + doa_out <= #100 16'bX; + end + data_collision_a_b[1] <= 0; + end + + always @(posedge data_collision_a_b[0]) begin + if (ssrb_int == 0 && output_flag) begin + dob_out[addra_reg[0:0] * 16 +: 16] <= #100 16'bX; + end + data_collision_a_b[0] <= 0; + end + + always @(posedge data_collision_b_a[1]) begin + if (ssra_int == 0 && output_flag) begin + doa_out <= #100 16'bX; + end + data_collision_b_a[1] <= 0; + end + + always @(posedge data_collision_b_a[0]) begin + if (ssrb_reg == 0 && output_flag) begin + dob_out[addra_int[0:0] * 16 +: 16] <= #100 16'bX; + end + data_collision_b_a[0] <= 0; + end + +// x parity start + always @(posedge memory_collision) begin + if ((output_flag || display_flag)) + memp[addra_int[9:1]][addra_int[0:0] * 2 +: 2] <= 2'bx; + end + + always @(posedge memory_collision_a_b) begin + if ((output_flag || display_flag)) + memp[addra_reg[9:1]][addra_reg[0:0] * 2 +: 2] <= 2'bx; + end + + always @(posedge memory_collision_b_a) begin + if ((output_flag || display_flag)) + memp[addra_int[9:1]][addra_int[0:0] * 2 +: 2] <= 2'bx; + end + + always @(posedge data_collision[1]) begin + if (ssra_int == 0 && output_flag) begin + dopa_out <= #100 2'bX; + end + end + + always @(posedge data_collision_a_b[1]) begin + if (ssra_reg == 0 && output_flag) begin + dopa_out <= #100 2'bX; + end + end + + + always @(posedge data_collision_b_a[1]) begin + if (ssra_int == 0 && output_flag) begin + dopa_out <= #100 2'bX; + end + end + + always @(posedge data_collision[0]) begin + if (ssrb_int == 0 && output_flag) begin + dopb_out[addra_int[0:0] +: 2] <= #100 2'bx; + end + end + + always @(posedge data_collision_a_b[0]) begin + if (ssrb_int == 0 && output_flag) begin + dopb_out[addra_reg[0:0] +: 2] <= #100 2'bx; + end + end + + always @(posedge data_collision_b_a[0]) begin + if (ssrb_reg == 0 && output_flag) begin + dopb_out[addra_int[0:0] +: 2] <= #100 2'bx; + end + end +// x parity end + + initial begin + case (WRITE_MODE_A) + "WRITE_FIRST" : wr_mode_a <= 2'b00; + "READ_FIRST" : wr_mode_a <= 2'b01; + "NO_CHANGE" : wr_mode_a <= 2'b10; + default : begin + $display("Attribute Syntax Error : The Attribute WRITE_MODE_A on RAMB16_S18_S36 instance %m is set to %s. Legal values for this attribute are WRITE_FIRST, READ_FIRST or NO_CHANGE.", WRITE_MODE_A); + $finish; + end + endcase + end + + initial begin + case (WRITE_MODE_B) + "WRITE_FIRST" : wr_mode_b <= 2'b00; + "READ_FIRST" : wr_mode_b <= 2'b01; + "NO_CHANGE" : wr_mode_b <= 2'b10; + default : begin + $display("Attribute Syntax Error : The Attribute WRITE_MODE_B on RAMB16_S18_S36 instance %m is set to %s. Legal values for this attribute are WRITE_FIRST, READ_FIRST or NO_CHANGE.", WRITE_MODE_B); + $finish; + end + endcase + end + + + // Port A + always @(posedge clka_int) begin + + if (ena_int == 1'b1) begin + + if (ssra_int == 1'b1) begin + {dopa_out, doa_out} <= #100 SRVAL_A; + end + else begin + if (wea_int == 1'b1) begin + if (wr_mode_a == 2'b00) begin + doa_out <= #100 dia_int; + dopa_out <= #100 dipa_int; + end + else if (wr_mode_a == 2'b01) begin + + doa_out <= #100 mem[addra_int[9:1]][addra_int[0:0] * 16 +: 16]; + dopa_out <= #100 memp[addra_int[9:1]][addra_int[0:0] * 2 +: 2]; + + end + end + else begin + + doa_out <= #100 mem[addra_int[9:1]][addra_int[0:0] * 16 +: 16]; + dopa_out <= #100 memp[addra_int[9:1]][addra_int[0:0] * 2 +: 2]; + + end + end + + // memory + if (wea_int == 1'b1) begin + mem[addra_int[9:1]][addra_int[0:0] * 16 +: 16] <= dia_int; + memp[addra_int[9:1]][addra_int[0:0] * 2 +: 2] <= dipa_int; + end + + end + end + + + // Port B + always @(posedge clkb_int) begin + + if (enb_int == 1'b1) begin + + if (ssrb_int == 1'b1) begin + {dopb_out, dob_out} <= #100 SRVAL_B; + end + else begin + if (web_int == 1'b1) begin + if (wr_mode_b == 2'b00) begin + dob_out <= #100 dib_int; + dopb_out <= #100 dipb_int; + end + else if (wr_mode_b == 2'b01) begin + dob_out <= #100 mem[addrb_int]; + dopb_out <= #100 memp[addrb_int]; + end + end + else begin + dob_out <= #100 mem[addrb_int]; + dopb_out <= #100 memp[addrb_int]; + end + end + + // memory + if (web_int == 1'b1) begin + mem[addrb_int] <= dib_int; + memp[addrb_int] <= dipb_int; + end + + end + end + + +endmodule + +`endif diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/RAMB16_S1_S1.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/RAMB16_S1_S1.v new file mode 100644 index 0000000..456a98d --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/RAMB16_S1_S1.v @@ -0,0 +1,1524 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/RAMB16_S1_S1.v,v 1.11 2007/02/22 01:58:05 wloo Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2005 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / 16K-Bit Data and 2K-Bit Parity Dual Port Block RAM +// /___/ /\ Filename : RAMB16_S1_S1.v +// \ \ / \ Timestamp : Thu Mar 10 16:43:35 PST 2005 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// End Revision + +`ifdef legacy_model + +`timescale 1 ps / 1 ps + +module RAMB16_S1_S1 (DOA, DOB, ADDRA, ADDRB, CLKA, CLKB, DIA, DIB, ENA, ENB, SSRA, SSRB, WEA, WEB); + + parameter INIT_A = 1'h0; + parameter INIT_B = 1'h0; + parameter SRVAL_A = 1'h0; + parameter SRVAL_B = 1'h0; + parameter WRITE_MODE_A = "WRITE_FIRST"; + parameter WRITE_MODE_B = "WRITE_FIRST"; + parameter SIM_COLLISION_CHECK = "ALL"; + localparam SETUP_ALL = 1000; + localparam SETUP_READ_FIRST = 3000; + + parameter INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + + output [0:0] DOA; + reg [0:0] doa_out; + wire doa_out0; + + input [13:0] ADDRA; + input [0:0] DIA; + input ENA, CLKA, WEA, SSRA; + + output [0:0] DOB; + reg [0:0] dob_out; + wire dob_out0; + + input [13:0] ADDRB; + input [0:0] DIB; + input ENB, CLKB, WEB, SSRB; + + reg [18431:0] mem; + reg [8:0] count; + reg [1:0] wr_mode_a, wr_mode_b; + + reg [5:0] dmi, dbi; + reg [5:0] pmi, pbi; + + wire [13:0] addra_int; + reg [13:0] addra_reg; + wire [0:0] dia_int; + wire ena_int, clka_int, wea_int, ssra_int; + reg ena_reg, wea_reg, ssra_reg; + wire [13:0] addrb_int; + reg [13:0] addrb_reg; + wire [0:0] dib_int; + wire enb_int, clkb_int, web_int, ssrb_int; + reg display_flag; + reg enb_reg, web_reg, ssrb_reg; + + time time_clka, time_clkb; + time time_clka_clkb; + time time_clkb_clka; + + reg setup_all_a_b; + reg setup_all_b_a; + reg setup_zero; + reg setup_rf_a_b; + reg setup_rf_b_a; + reg [1:0] data_collision, data_collision_a_b, data_collision_b_a; + reg memory_collision, memory_collision_a_b, memory_collision_b_a; + reg address_collision, address_collision_a_b, address_collision_b_a; + reg change_clka; + reg change_clkb; + + wire [14:0] data_addra_int; + wire [14:0] data_addra_reg; + wire [14:0] data_addrb_int; + wire [14:0] data_addrb_reg; + wire [15:0] parity_addra_int; + wire [15:0] parity_addra_reg; + wire [15:0] parity_addrb_int; + wire [15:0] parity_addrb_reg; + + tri0 GSR = glbl.GSR; + + always @(GSR) + if (GSR) begin + assign doa_out = INIT_A[0:0]; + assign dob_out = INIT_B[0:0]; + end + else begin + deassign doa_out; + deassign dob_out; + end + + buf b_doa_out0 (doa_out0, doa_out[0]); + buf b_dob_out0 (dob_out0, dob_out[0]); + + buf b_doa0 (DOA[0], doa_out0); + buf b_dob0 (DOB[0], dob_out0); + + buf b_addra_0 (addra_int[0], ADDRA[0]); + buf b_addra_1 (addra_int[1], ADDRA[1]); + buf b_addra_2 (addra_int[2], ADDRA[2]); + buf b_addra_3 (addra_int[3], ADDRA[3]); + buf b_addra_4 (addra_int[4], ADDRA[4]); + buf b_addra_5 (addra_int[5], ADDRA[5]); + buf b_addra_6 (addra_int[6], ADDRA[6]); + buf b_addra_7 (addra_int[7], ADDRA[7]); + buf b_addra_8 (addra_int[8], ADDRA[8]); + buf b_addra_9 (addra_int[9], ADDRA[9]); + buf b_addra_10 (addra_int[10], ADDRA[10]); + buf b_addra_11 (addra_int[11], ADDRA[11]); + buf b_addra_12 (addra_int[12], ADDRA[12]); + buf b_addra_13 (addra_int[13], ADDRA[13]); + buf b_dia_0 (dia_int[0], DIA[0]); + buf b_ena (ena_int, ENA); + buf b_clka (clka_int, CLKA); + buf b_ssra (ssra_int, SSRA); + buf b_wea (wea_int, WEA); + buf b_addrb_0 (addrb_int[0], ADDRB[0]); + buf b_addrb_1 (addrb_int[1], ADDRB[1]); + buf b_addrb_2 (addrb_int[2], ADDRB[2]); + buf b_addrb_3 (addrb_int[3], ADDRB[3]); + buf b_addrb_4 (addrb_int[4], ADDRB[4]); + buf b_addrb_5 (addrb_int[5], ADDRB[5]); + buf b_addrb_6 (addrb_int[6], ADDRB[6]); + buf b_addrb_7 (addrb_int[7], ADDRB[7]); + buf b_addrb_8 (addrb_int[8], ADDRB[8]); + buf b_addrb_9 (addrb_int[9], ADDRB[9]); + buf b_addrb_10 (addrb_int[10], ADDRB[10]); + buf b_addrb_11 (addrb_int[11], ADDRB[11]); + buf b_addrb_12 (addrb_int[12], ADDRB[12]); + buf b_addrb_13 (addrb_int[13], ADDRB[13]); + buf b_dib_0 (dib_int[0], DIB[0]); + buf b_enb (enb_int, ENB); + buf b_clkb (clkb_int, CLKB); + buf b_ssrb (ssrb_int, SSRB); + buf b_web (web_int, WEB); + + initial begin + for (count = 0; count < 256; count = count + 1) begin + mem[count] <= INIT_00[count]; + mem[256 * 1 + count] <= INIT_01[count]; + mem[256 * 2 + count] <= INIT_02[count]; + mem[256 * 3 + count] <= INIT_03[count]; + mem[256 * 4 + count] <= INIT_04[count]; + mem[256 * 5 + count] <= INIT_05[count]; + mem[256 * 6 + count] <= INIT_06[count]; + mem[256 * 7 + count] <= INIT_07[count]; + mem[256 * 8 + count] <= INIT_08[count]; + mem[256 * 9 + count] <= INIT_09[count]; + mem[256 * 10 + count] <= INIT_0A[count]; + mem[256 * 11 + count] <= INIT_0B[count]; + mem[256 * 12 + count] <= INIT_0C[count]; + mem[256 * 13 + count] <= INIT_0D[count]; + mem[256 * 14 + count] <= INIT_0E[count]; + mem[256 * 15 + count] <= INIT_0F[count]; + mem[256 * 16 + count] <= INIT_10[count]; + mem[256 * 17 + count] <= INIT_11[count]; + mem[256 * 18 + count] <= INIT_12[count]; + mem[256 * 19 + count] <= INIT_13[count]; + mem[256 * 20 + count] <= INIT_14[count]; + mem[256 * 21 + count] <= INIT_15[count]; + mem[256 * 22 + count] <= INIT_16[count]; + mem[256 * 23 + count] <= INIT_17[count]; + mem[256 * 24 + count] <= INIT_18[count]; + mem[256 * 25 + count] <= INIT_19[count]; + mem[256 * 26 + count] <= INIT_1A[count]; + mem[256 * 27 + count] <= INIT_1B[count]; + mem[256 * 28 + count] <= INIT_1C[count]; + mem[256 * 29 + count] <= INIT_1D[count]; + mem[256 * 30 + count] <= INIT_1E[count]; + mem[256 * 31 + count] <= INIT_1F[count]; + mem[256 * 32 + count] <= INIT_20[count]; + mem[256 * 33 + count] <= INIT_21[count]; + mem[256 * 34 + count] <= INIT_22[count]; + mem[256 * 35 + count] <= INIT_23[count]; + mem[256 * 36 + count] <= INIT_24[count]; + mem[256 * 37 + count] <= INIT_25[count]; + mem[256 * 38 + count] <= INIT_26[count]; + mem[256 * 39 + count] <= INIT_27[count]; + mem[256 * 40 + count] <= INIT_28[count]; + mem[256 * 41 + count] <= INIT_29[count]; + mem[256 * 42 + count] <= INIT_2A[count]; + mem[256 * 43 + count] <= INIT_2B[count]; + mem[256 * 44 + count] <= INIT_2C[count]; + mem[256 * 45 + count] <= INIT_2D[count]; + mem[256 * 46 + count] <= INIT_2E[count]; + mem[256 * 47 + count] <= INIT_2F[count]; + mem[256 * 48 + count] <= INIT_30[count]; + mem[256 * 49 + count] <= INIT_31[count]; + mem[256 * 50 + count] <= INIT_32[count]; + mem[256 * 51 + count] <= INIT_33[count]; + mem[256 * 52 + count] <= INIT_34[count]; + mem[256 * 53 + count] <= INIT_35[count]; + mem[256 * 54 + count] <= INIT_36[count]; + mem[256 * 55 + count] <= INIT_37[count]; + mem[256 * 56 + count] <= INIT_38[count]; + mem[256 * 57 + count] <= INIT_39[count]; + mem[256 * 58 + count] <= INIT_3A[count]; + mem[256 * 59 + count] <= INIT_3B[count]; + mem[256 * 60 + count] <= INIT_3C[count]; + mem[256 * 61 + count] <= INIT_3D[count]; + mem[256 * 62 + count] <= INIT_3E[count]; + mem[256 * 63 + count] <= INIT_3F[count]; + end + address_collision <= 0; + address_collision_a_b <= 0; + address_collision_b_a <= 0; + change_clka <= 0; + change_clkb <= 0; + data_collision <= 0; + data_collision_a_b <= 0; + data_collision_b_a <= 0; + memory_collision <= 0; + memory_collision_a_b <= 0; + memory_collision_b_a <= 0; + setup_all_a_b <= 0; + setup_all_b_a <= 0; + setup_zero <= 0; + setup_rf_a_b <= 0; + setup_rf_b_a <= 0; + end + + assign data_addra_int = addra_int * 1; + assign data_addra_reg = addra_reg * 1; + assign data_addrb_int = addrb_int * 1; + assign data_addrb_reg = addrb_reg * 1; + + + initial begin + + display_flag = 1; + + case (SIM_COLLISION_CHECK) + + "NONE" : begin + assign setup_all_a_b = 1'b0; + assign setup_all_b_a = 1'b0; + assign setup_zero = 1'b0; + assign setup_rf_a_b = 1'b0; + assign setup_rf_b_a = 1'b0; + assign display_flag = 0; + end + "WARNING_ONLY" : begin + assign data_collision = 2'b00; + assign data_collision_a_b = 2'b00; + assign data_collision_b_a = 2'b00; + assign memory_collision = 1'b0; + assign memory_collision_a_b = 1'b0; + assign memory_collision_b_a = 1'b0; + end + "GENERATE_X_ONLY" : begin + assign display_flag = 0; + end + "ALL" : ; + default : begin + $display("Attribute Syntax Error : The Attribute SIM_COLLISION_CHECK on RAMB16_S1_S1 instance %m is set to %s. Legal values for this attribute are ALL, NONE, WARNING_ONLY or GENERATE_X_ONLY.", SIM_COLLISION_CHECK); + $finish; + end + + endcase // case(SIM_COLLISION_CHECK) + + end // initial begin + + + always @(posedge clka_int) begin + time_clka = $time; + #0 time_clkb_clka = time_clka - time_clkb; + change_clka = ~change_clka; + end + + always @(posedge clkb_int) begin + time_clkb = $time; + #0 time_clka_clkb = time_clkb - time_clka; + change_clkb = ~change_clkb; + end + + always @(change_clkb) begin + if ((0 < time_clka_clkb) && (time_clka_clkb < SETUP_ALL)) + setup_all_a_b = 1; + if ((0 < time_clka_clkb) && (time_clka_clkb < SETUP_READ_FIRST)) + setup_rf_a_b = 1; + end + + always @(change_clka) begin + if ((0 < time_clkb_clka) && (time_clkb_clka < SETUP_ALL)) + setup_all_b_a = 1; + if ((0 < time_clkb_clka) && (time_clkb_clka < SETUP_READ_FIRST)) + setup_rf_b_a = 1; + end + + always @(change_clkb or change_clka) begin + if ((time_clkb_clka == 0) && (time_clka_clkb == 0)) + setup_zero = 1; + end + + always @(posedge setup_zero) begin + if ((ena_int == 1) && (wea_int == 1) && + (enb_int == 1) && (web_int == 1) && + (data_addra_int[14:0] == data_addrb_int[14:0])) + memory_collision <= 1; + end + + always @(posedge setup_all_a_b or posedge setup_rf_a_b) begin + if ((ena_reg == 1) && (wea_reg == 1) && + (enb_int == 1) && (web_int == 1) && + (data_addra_reg[14:0] == data_addrb_int[14:0])) + memory_collision_a_b <= 1; + end + + always @(posedge setup_all_b_a or posedge setup_rf_b_a) begin + if ((ena_int == 1) && (wea_int == 1) && + (enb_reg == 1) && (web_reg == 1) && + (data_addra_int[14:0] == data_addrb_reg[14:0])) + memory_collision_b_a <= 1; + end + + always @(posedge setup_all_a_b) begin + if (data_addra_reg[14:0] == data_addrb_int[14:0]) begin + if ((ena_reg == 1) && (enb_int == 1)) begin + case ({wr_mode_a, wr_mode_b, wea_reg, web_int}) + 6'b000011 : begin data_collision_a_b <= 2'b11; display_wa_wb; end + 6'b000111 : begin data_collision_a_b <= 2'b11; display_wa_wb; end + 6'b001011 : begin data_collision_a_b <= 2'b10; display_wa_wb; end +// 6'b010011 : begin data_collision_a_b <= 2'b00; display_wa_wb; end +// 6'b010111 : begin data_collision_a_b <= 2'b00; display_wa_wb; end +// 6'b011011 : begin data_collision_a_b <= 2'b00; display_wa_wb; end + 6'b100011 : begin data_collision_a_b <= 2'b01; display_wa_wb; end + 6'b100111 : begin data_collision_a_b <= 2'b01; display_wa_wb; end + 6'b101011 : begin display_wa_wb; end + 6'b000001 : begin data_collision_a_b <= 2'b10; display_ra_wb; end +// 6'b000101 : begin data_collision_a_b <= 2'b00; display_ra_wb; end + 6'b001001 : begin data_collision_a_b <= 2'b10; display_ra_wb; end + 6'b010001 : begin data_collision_a_b <= 2'b10; display_ra_wb; end +// 6'b010101 : begin data_collision_a_b <= 2'b00; display_ra_wb; end + 6'b011001 : begin data_collision_a_b <= 2'b10; display_ra_wb; end + 6'b100001 : begin data_collision_a_b <= 2'b10; display_ra_wb; end +// 6'b100101 : begin data_collision_a_b <= 2'b00; display_ra_wb; end + 6'b101001 : begin data_collision_a_b <= 2'b10; display_ra_wb; end + 6'b000010 : begin data_collision_a_b <= 2'b01; display_wa_rb; end + 6'b000110 : begin data_collision_a_b <= 2'b01; display_wa_rb; end + 6'b001010 : begin data_collision_a_b <= 2'b01; display_wa_rb; end +// 6'b010010 : begin data_collision_a_b <= 2'b00; display_wa_rb; end +// 6'b010110 : begin data_collision_a_b <= 2'b00; display_wa_rb; end +// 6'b011010 : begin data_collision_a_b <= 2'b00; display_wa_rb; end + 6'b100010 : begin data_collision_a_b <= 2'b01; display_wa_rb; end + 6'b100110 : begin data_collision_a_b <= 2'b01; display_wa_rb; end + 6'b101010 : begin data_collision_a_b <= 2'b01; display_wa_rb; end + endcase + end + end + setup_all_a_b <= 0; + end + + + always @(posedge setup_all_b_a) begin + if (data_addra_int[14:0] == data_addrb_reg[14:0]) begin + if ((ena_int == 1) && (enb_reg == 1)) begin + case ({wr_mode_a, wr_mode_b, wea_int, web_reg}) + 6'b000011 : begin data_collision_b_a <= 2'b11; display_wa_wb; end +// 6'b000111 : begin data_collision_b_a <= 2'b00; display_wa_wb; end + 6'b001011 : begin data_collision_b_a <= 2'b10; display_wa_wb; end + 6'b010011 : begin data_collision_b_a <= 2'b11; display_wa_wb; end +// 6'b010111 : begin data_collision_b_a <= 2'b00; display_wa_wb; end + 6'b011011 : begin data_collision_b_a <= 2'b10; display_wa_wb; end + 6'b100011 : begin data_collision_b_a <= 2'b01; display_wa_wb; end + 6'b100111 : begin data_collision_b_a <= 2'b01; display_wa_wb; end + 6'b101011 : begin display_wa_wb; end + 6'b000001 : begin data_collision_b_a <= 2'b10; display_ra_wb; end + 6'b000101 : begin data_collision_b_a <= 2'b10; display_ra_wb; end + 6'b001001 : begin data_collision_b_a <= 2'b10; display_ra_wb; end + 6'b010001 : begin data_collision_b_a <= 2'b10; display_ra_wb; end + 6'b010101 : begin data_collision_b_a <= 2'b10; display_ra_wb; end + 6'b011001 : begin data_collision_b_a <= 2'b10; display_ra_wb; end + 6'b100001 : begin data_collision_b_a <= 2'b10; display_ra_wb; end + 6'b100101 : begin data_collision_b_a <= 2'b10; display_ra_wb; end + 6'b101001 : begin data_collision_b_a <= 2'b10; display_ra_wb; end + 6'b000010 : begin data_collision_b_a <= 2'b01; display_wa_rb; end + 6'b000110 : begin data_collision_b_a <= 2'b01; display_wa_rb; end + 6'b001010 : begin data_collision_b_a <= 2'b01; display_wa_rb; end +// 6'b010010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end +// 6'b010110 : begin data_collision_b_a <= 2'b00; display_wa_rb; end +// 6'b011010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end + 6'b100010 : begin data_collision_b_a <= 2'b01; display_wa_rb; end + 6'b100110 : begin data_collision_b_a <= 2'b01; display_wa_rb; end + 6'b101010 : begin data_collision_b_a <= 2'b01; display_wa_rb; end + endcase + end + end + setup_all_b_a <= 0; + end + + + always @(posedge setup_zero) begin + if (data_addra_int[14:0] == data_addrb_int[14:0]) begin + if ((ena_int == 1) && (enb_int == 1)) begin + case ({wr_mode_a, wr_mode_b, wea_int, web_int}) + 6'b000011 : begin data_collision <= 2'b11; display_wa_wb; end + 6'b000111 : begin data_collision <= 2'b11; display_wa_wb; end + 6'b001011 : begin data_collision <= 2'b10; display_wa_wb; end + 6'b010011 : begin data_collision <= 2'b11; display_wa_wb; end + 6'b010111 : begin data_collision <= 2'b11; display_wa_wb; end + 6'b011011 : begin data_collision <= 2'b10; display_wa_wb; end + 6'b100011 : begin data_collision <= 2'b01; display_wa_wb; end + 6'b100111 : begin data_collision <= 2'b01; display_wa_wb; end + 6'b101011 : begin display_wa_wb; end + 6'b000001 : begin data_collision <= 2'b10; display_ra_wb; end +// 6'b000101 : begin data_collision <= 2'b00; display_ra_wb; end + 6'b001001 : begin data_collision <= 2'b10; display_ra_wb; end + 6'b010001 : begin data_collision <= 2'b10; display_ra_wb; end +// 6'b010101 : begin data_collision <= 2'b00; display_ra_wb; end + 6'b011001 : begin data_collision <= 2'b10; display_ra_wb; end + 6'b100001 : begin data_collision <= 2'b10; display_ra_wb; end +// 6'b100101 : begin data_collision <= 2'b00; display_ra_wb; end + 6'b101001 : begin data_collision <= 2'b10; display_ra_wb; end + 6'b000010 : begin data_collision <= 2'b01; display_wa_rb; end + 6'b000110 : begin data_collision <= 2'b01; display_wa_rb; end + 6'b001010 : begin data_collision <= 2'b01; display_wa_rb; end +// 6'b010010 : begin data_collision <= 2'b00; display_wa_rb; end +// 6'b010110 : begin data_collision <= 2'b00; display_wa_rb; end +// 6'b011010 : begin data_collision <= 2'b00; display_wa_rb; end + 6'b100010 : begin data_collision <= 2'b01; display_wa_rb; end + 6'b100110 : begin data_collision <= 2'b01; display_wa_rb; end + 6'b101010 : begin data_collision <= 2'b01; display_wa_rb; end + endcase + end + end + setup_zero <= 0; + end + + task display_ra_wb; + begin + if (display_flag) + $display("Memory Collision Error on RAMB16_S1_S1:%m at simulation time %.3f ns\nA read was performed on address %h (hex) of Port A while a write was requested to the same address on Port B. The write will be successful however the read value on Port A is unknown until the next CLKA cycle.", $time/1000.0, addra_int); + end + endtask + + task display_wa_rb; + begin + if (display_flag) + $display("Memory Collision Error on RAMB16_S1_S1:%m at simulation time %.3f ns\nA read was performed on address %h (hex) of Port B while a write was requested to the same address on Port A. The write will be successful however the read value on Port B is unknown until the next CLKB cycle.", $time/1000.0, addrb_int); + end + endtask + + task display_wa_wb; + begin + if (display_flag) + $display("Memory Collision Error on RAMB16_S1_S1:%m at simulation time %.3f ns\nA write was requested to the same address simultaneously at both Port A and Port B of the RAM. The contents written to the RAM at address location %h (hex) of Port A and address location %h (hex) of Port B are unknown.", $time/1000.0, addra_int, addrb_int); + end + endtask + + + always @(posedge setup_rf_a_b) begin + if (data_addra_reg[14:0] == data_addrb_int[14:0]) begin + if ((ena_reg == 1) && (enb_int == 1)) begin + case ({wr_mode_a, wr_mode_b, wea_reg, web_int}) +// 6'b000011 : begin data_collision_a_b <= 2'b00; display_wa_wb; end +// 6'b000111 : begin data_collision_a_b <= 2'b00; display_wa_wb; end +// 6'b001011 : begin data_collision_a_b <= 2'b00; display_wa_wb; end + 6'b010011 : begin data_collision_a_b <= 2'b11; display_wa_wb; end + 6'b010111 : begin data_collision_a_b <= 2'b11; display_wa_wb; end + 6'b011011 : begin data_collision_a_b <= 2'b10; display_wa_wb; end +// 6'b100011 : begin data_collision_a_b <= 2'b00; display_wa_wb; end +// 6'b100111 : begin data_collision_a_b <= 2'b00; display_wa_wb; end +// 6'b101011 : begin data_collision_a_b <= 2'b00; display_wa_wb; end +// 6'b000001 : begin data_collision_a_b <= 2'b00; display_ra_wb; end +// 6'b000101 : begin data_collision_a_b <= 2'b00; display_ra_wb; end +// 6'b001001 : begin data_collision_a_b <= 2'b00; display_ra_wb; end +// 6'b010001 : begin data_collision_a_b <= 2'b00; display_ra_wb; end +// 6'b010101 : begin data_collision_a_b <= 2'b00; display_ra_wb; end +// 6'b011001 : begin data_collision_a_b <= 2'b00; display_ra_wb; end +// 6'b100001 : begin data_collision_a_b <= 2'b00; display_ra_wb; end +// 6'b100101 : begin data_collision_a_b <= 2'b00; display_ra_wb; end +// 6'b101001 : begin data_collision_a_b <= 2'b00; display_ra_wb; end +// 6'b000010 : begin data_collision_a_b <= 2'b00; display_wa_rb; end +// 6'b000110 : begin data_collision_a_b <= 2'b00; display_wa_rb; end +// 6'b001010 : begin data_collision_a_b <= 2'b00; display_wa_rb; end + 6'b010010 : begin data_collision_a_b <= 2'b01; display_wa_rb; end + 6'b010110 : begin data_collision_a_b <= 2'b01; display_wa_rb; end + 6'b011010 : begin data_collision_a_b <= 2'b01; display_wa_rb; end +// 6'b100010 : begin data_collision_a_b <= 2'b00; display_wa_rb; end +// 6'b100110 : begin data_collision_a_b <= 2'b00; display_wa_rb; end +// 6'b101010 : begin data_collision_a_b <= 2'b00; display_wa_rb; end + endcase + end + end + setup_rf_a_b <= 0; + end + + + always @(posedge setup_rf_b_a) begin + if (data_addra_int[14:0] == data_addrb_reg[14:0]) begin + if ((ena_int == 1) && (enb_reg == 1)) begin + case ({wr_mode_a, wr_mode_b, wea_int, web_reg}) +// 6'b000011 : begin data_collision_b_a <= 2'b00; display_wa_wb; end + 6'b000111 : begin data_collision_b_a <= 2'b11; display_wa_wb; end +// 6'b001011 : begin data_collision_b_a <= 2'b00; display_wa_wb; end +// 6'b010011 : begin data_collision_b_a <= 2'b00; display_wa_wb; end + 6'b010111 : begin data_collision_b_a <= 2'b11; display_wa_wb; end +// 6'b011011 : begin data_collision_b_a <= 2'b00; display_wa_wb; end +// 6'b100011 : begin data_collision_b_a <= 2'b00; display_wa_wb; end + 6'b100111 : begin data_collision_b_a <= 2'b01; display_wa_wb; end +// 6'b101011 : begin data_collision_b_a <= 2'b00; display_wa_wb; end +// 6'b000001 : begin data_collision_b_a <= 2'b00; display_ra_wb; end + 6'b000101 : begin data_collision_b_a <= 2'b10; display_ra_wb; end +// 6'b001001 : begin data_collision_b_a <= 2'b00; display_ra_wb; end +// 6'b010001 : begin data_collision_b_a <= 2'b00; display_ra_wb; end + 6'b010101 : begin data_collision_b_a <= 2'b10; display_ra_wb; end +// 6'b011001 : begin data_collision_b_a <= 2'b00; display_ra_wb; end +// 6'b100001 : begin data_collision_b_a <= 2'b00; display_ra_wb; end + 6'b100101 : begin data_collision_b_a <= 2'b10; display_ra_wb; end +// 6'b101001 : begin data_collision_b_a <= 2'b00; display_ra_wb; end +// 6'b000010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end +// 6'b000110 : begin data_collision_b_a <= 2'b00; display_wa_rb; end +// 6'b001010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end +// 6'b010010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end +// 6'b010110 : begin data_collision_b_a <= 2'b00; display_wa_rb; end +// 6'b011010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end +// 6'b100010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end +// 6'b100110 : begin data_collision_b_a <= 2'b00; display_wa_rb; end +// 6'b101010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end + endcase + end + end + setup_rf_b_a <= 0; + end + + + always @(posedge clka_int) begin + addra_reg <= addra_int; + ena_reg <= ena_int; + ssra_reg <= ssra_int; + wea_reg <= wea_int; + end + + always @(posedge clkb_int) begin + addrb_reg <= addrb_int; + enb_reg <= enb_int; + ssrb_reg <= ssrb_int; + web_reg <= web_int; + end + + // Data + always @(posedge memory_collision) begin + for (dmi = 0; dmi < 1; dmi = dmi + 1) begin + mem[data_addra_int + dmi] <= 1'bX; + end + memory_collision <= 0; + end + + always @(posedge memory_collision_a_b) begin + for (dmi = 0; dmi < 1; dmi = dmi + 1) begin + mem[data_addra_reg + dmi] <= 1'bX; + end + memory_collision_a_b <= 0; + end + + always @(posedge memory_collision_b_a) begin + for (dmi = 0; dmi < 1; dmi = dmi + 1) begin + mem[data_addra_int + dmi] <= 1'bX; + end + memory_collision_b_a <= 0; + end + + always @(posedge data_collision[1]) begin + if (ssra_int == 0) begin + doa_out <= 1'bX; + end + data_collision[1] <= 0; + end + + always @(posedge data_collision[0]) begin + if (ssrb_int == 0) begin + dob_out <= 1'bX; + end + data_collision[0] <= 0; + end + + always @(posedge data_collision_a_b[1]) begin + if (ssra_reg == 0) begin + doa_out <= 1'bX; + end + data_collision_a_b[1] <= 0; + end + + always @(posedge data_collision_a_b[0]) begin + if (ssrb_int == 0) begin + dob_out <= 1'bX; + end + data_collision_a_b[0] <= 0; + end + + always @(posedge data_collision_b_a[1]) begin + if (ssra_int == 0) begin + doa_out <= 1'bX; + end + data_collision_b_a[1] <= 0; + end + + always @(posedge data_collision_b_a[0]) begin + if (ssrb_reg == 0) begin + dob_out <= 1'bX; + end + data_collision_b_a[0] <= 0; + end + + + initial begin + case (WRITE_MODE_A) + "WRITE_FIRST" : wr_mode_a <= 2'b00; + "READ_FIRST" : wr_mode_a <= 2'b01; + "NO_CHANGE" : wr_mode_a <= 2'b10; + default : begin + $display("Attribute Syntax Error : The Attribute WRITE_MODE_A on RAMB16_S1_S1 instance %m is set to %s. Legal values for this attribute are WRITE_FIRST, READ_FIRST or NO_CHANGE.", WRITE_MODE_A); + $finish; + end + endcase + end + + initial begin + case (WRITE_MODE_B) + "WRITE_FIRST" : wr_mode_b <= 2'b00; + "READ_FIRST" : wr_mode_b <= 2'b01; + "NO_CHANGE" : wr_mode_b <= 2'b10; + default : begin + $display("Attribute Syntax Error : The Attribute WRITE_MODE_B on RAMB16_S1_S1 instance %m is set to %s. Legal values for this attribute are WRITE_FIRST, READ_FIRST or NO_CHANGE.", WRITE_MODE_B); + $finish; + end + endcase + end + + // Port A + always @(posedge clka_int) begin + if (ena_int == 1'b1) begin + if (ssra_int == 1'b1) begin + doa_out[0] <= SRVAL_A[0]; + end + else begin + if (wea_int == 1'b1) begin + if (wr_mode_a == 2'b00) begin + doa_out <= dia_int; + end + else if (wr_mode_a == 2'b01) begin + doa_out[0] <= mem[data_addra_int + 0]; + end + end + else begin + doa_out[0] <= mem[data_addra_int + 0]; + end + end + end + end + + always @(posedge clka_int) begin + if (ena_int == 1'b1 && wea_int == 1'b1) begin + mem[data_addra_int + 0] <= dia_int[0]; + end + end + + // Port B + always @(posedge clkb_int) begin + if (enb_int == 1'b1) begin + if (ssrb_int == 1'b1) begin + dob_out[0] <= SRVAL_B[0]; + end + else begin + if (web_int == 1'b1) begin + if (wr_mode_b == 2'b00) begin + dob_out <= dib_int; + end + else if (wr_mode_b == 2'b01) begin + dob_out[0] <= mem[data_addrb_int + 0]; + end + end + else begin + dob_out[0] <= mem[data_addrb_int + 0]; + end + end + end + end + + always @(posedge clkb_int) begin + if (enb_int == 1'b1 && web_int == 1'b1) begin + mem[data_addrb_int + 0] <= dib_int[0]; + end + end + + specify + (CLKA *> DOA) = (100, 100); + (CLKB *> DOB) = (100, 100); + endspecify + +endmodule + +`else + +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/RAMB16_S1_S1.v,v 1.11 2007/02/22 01:58:05 wloo Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2005 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Timing Simulation Library Component +// / / 16K-Bit Data and 2K-Bit Parity Dual Port Block RAM +// /___/ /\ Filename : RAMB16_S1_S1.v +// \ \ / \ Timestamp : Thu Mar 10 16:44:01 PST 2005 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 03/10/05 - Initialized outputs. +// 02/21/07 - Fixed parameter SIM_COLLISION_CHECK (CR 433281). +// End Revision + +`timescale 1 ps/1 ps + +module RAMB16_S1_S1 (DOA, DOB, ADDRA, ADDRB, CLKA, CLKB, DIA, DIB, ENA, ENB, SSRA, SSRB, WEA, WEB); + + parameter INIT_A = 1'h0; + parameter INIT_B = 1'h0; + parameter SRVAL_A = 1'h0; + parameter SRVAL_B = 1'h0; + parameter WRITE_MODE_A = "WRITE_FIRST"; + parameter WRITE_MODE_B = "WRITE_FIRST"; + parameter SIM_COLLISION_CHECK = "ALL"; + localparam SETUP_ALL = 1000; + localparam SETUP_READ_FIRST = 3000; + + parameter INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + + output [0:0] DOA; + output [0:0] DOB; + + input [13:0] ADDRA; + input [0:0] DIA; + input ENA, CLKA, WEA, SSRA; + input [13:0] ADDRB; + input [0:0] DIB; + input ENB, CLKB, WEB, SSRB; + + reg [0:0] doa_out = INIT_A[0:0]; + reg [0:0] dob_out = INIT_B[0:0]; + + reg [0:0] mem [16383:0]; + + reg [8:0] count, countp; + reg [1:0] wr_mode_a, wr_mode_b; + + reg [5:0] dmi, dbi; + reg [5:0] pmi, pbi; + + wire [13:0] addra_int; + reg [13:0] addra_reg; + wire [0:0] dia_int; + wire ena_int, clka_int, wea_int, ssra_int; + reg ena_reg, wea_reg, ssra_reg; + wire [13:0] addrb_int; + reg [13:0] addrb_reg; + wire [0:0] dib_int; + wire enb_int, clkb_int, web_int, ssrb_int; + reg display_flag, output_flag; + reg enb_reg, web_reg, ssrb_reg; + + time time_clka, time_clkb; + time time_clka_clkb; + time time_clkb_clka; + + reg setup_all_a_b; + reg setup_all_b_a; + reg setup_zero; + reg setup_rf_a_b; + reg setup_rf_b_a; + reg [1:0] data_collision, data_collision_a_b, data_collision_b_a; + reg memory_collision, memory_collision_a_b, memory_collision_b_a; + reg change_clka; + reg change_clkb; + + wire [14:0] data_addra_int; + wire [14:0] data_addra_reg; + wire [14:0] data_addrb_int; + wire [14:0] data_addrb_reg; + + wire dia_enable = ena_int && wea_int; + wire dib_enable = enb_int && web_int; + + tri0 GSR = glbl.GSR; + wire gsr_int; + + buf b_gsr (gsr_int, GSR); + + buf b_doa [0:0] (DOA, doa_out); + buf b_addra [13:0] (addra_int, ADDRA); + buf b_dia [0:0] (dia_int, DIA); + buf b_ena (ena_int, ENA); + buf b_clka (clka_int, CLKA); + buf b_ssra (ssra_int, SSRA); + buf b_wea (wea_int, WEA); + + buf b_dob [0:0] (DOB, dob_out); + buf b_addrb [13:0] (addrb_int, ADDRB); + buf b_dib [0:0] (dib_int, DIB); + buf b_enb (enb_int, ENB); + buf b_clkb (clkb_int, CLKB); + buf b_ssrb (ssrb_int, SSRB); + buf b_web (web_int, WEB); + + + always @(gsr_int) + if (gsr_int) begin + assign {doa_out} = INIT_A; + assign {dob_out} = INIT_B; + end + else begin + deassign doa_out; + deassign dob_out; + end + + + initial begin + + for (count = 0; count < 256; count = count + 1) begin + mem[count] = INIT_00[(count * 1) +: 1]; + mem[256 * 1 + count] = INIT_01[(count * 1) +: 1]; + mem[256 * 2 + count] = INIT_02[(count * 1) +: 1]; + mem[256 * 3 + count] = INIT_03[(count * 1) +: 1]; + mem[256 * 4 + count] = INIT_04[(count * 1) +: 1]; + mem[256 * 5 + count] = INIT_05[(count * 1) +: 1]; + mem[256 * 6 + count] = INIT_06[(count * 1) +: 1]; + mem[256 * 7 + count] = INIT_07[(count * 1) +: 1]; + mem[256 * 8 + count] = INIT_08[(count * 1) +: 1]; + mem[256 * 9 + count] = INIT_09[(count * 1) +: 1]; + mem[256 * 10 + count] = INIT_0A[(count * 1) +: 1]; + mem[256 * 11 + count] = INIT_0B[(count * 1) +: 1]; + mem[256 * 12 + count] = INIT_0C[(count * 1) +: 1]; + mem[256 * 13 + count] = INIT_0D[(count * 1) +: 1]; + mem[256 * 14 + count] = INIT_0E[(count * 1) +: 1]; + mem[256 * 15 + count] = INIT_0F[(count * 1) +: 1]; + mem[256 * 16 + count] = INIT_10[(count * 1) +: 1]; + mem[256 * 17 + count] = INIT_11[(count * 1) +: 1]; + mem[256 * 18 + count] = INIT_12[(count * 1) +: 1]; + mem[256 * 19 + count] = INIT_13[(count * 1) +: 1]; + mem[256 * 20 + count] = INIT_14[(count * 1) +: 1]; + mem[256 * 21 + count] = INIT_15[(count * 1) +: 1]; + mem[256 * 22 + count] = INIT_16[(count * 1) +: 1]; + mem[256 * 23 + count] = INIT_17[(count * 1) +: 1]; + mem[256 * 24 + count] = INIT_18[(count * 1) +: 1]; + mem[256 * 25 + count] = INIT_19[(count * 1) +: 1]; + mem[256 * 26 + count] = INIT_1A[(count * 1) +: 1]; + mem[256 * 27 + count] = INIT_1B[(count * 1) +: 1]; + mem[256 * 28 + count] = INIT_1C[(count * 1) +: 1]; + mem[256 * 29 + count] = INIT_1D[(count * 1) +: 1]; + mem[256 * 30 + count] = INIT_1E[(count * 1) +: 1]; + mem[256 * 31 + count] = INIT_1F[(count * 1) +: 1]; + mem[256 * 32 + count] = INIT_20[(count * 1) +: 1]; + mem[256 * 33 + count] = INIT_21[(count * 1) +: 1]; + mem[256 * 34 + count] = INIT_22[(count * 1) +: 1]; + mem[256 * 35 + count] = INIT_23[(count * 1) +: 1]; + mem[256 * 36 + count] = INIT_24[(count * 1) +: 1]; + mem[256 * 37 + count] = INIT_25[(count * 1) +: 1]; + mem[256 * 38 + count] = INIT_26[(count * 1) +: 1]; + mem[256 * 39 + count] = INIT_27[(count * 1) +: 1]; + mem[256 * 40 + count] = INIT_28[(count * 1) +: 1]; + mem[256 * 41 + count] = INIT_29[(count * 1) +: 1]; + mem[256 * 42 + count] = INIT_2A[(count * 1) +: 1]; + mem[256 * 43 + count] = INIT_2B[(count * 1) +: 1]; + mem[256 * 44 + count] = INIT_2C[(count * 1) +: 1]; + mem[256 * 45 + count] = INIT_2D[(count * 1) +: 1]; + mem[256 * 46 + count] = INIT_2E[(count * 1) +: 1]; + mem[256 * 47 + count] = INIT_2F[(count * 1) +: 1]; + mem[256 * 48 + count] = INIT_30[(count * 1) +: 1]; + mem[256 * 49 + count] = INIT_31[(count * 1) +: 1]; + mem[256 * 50 + count] = INIT_32[(count * 1) +: 1]; + mem[256 * 51 + count] = INIT_33[(count * 1) +: 1]; + mem[256 * 52 + count] = INIT_34[(count * 1) +: 1]; + mem[256 * 53 + count] = INIT_35[(count * 1) +: 1]; + mem[256 * 54 + count] = INIT_36[(count * 1) +: 1]; + mem[256 * 55 + count] = INIT_37[(count * 1) +: 1]; + mem[256 * 56 + count] = INIT_38[(count * 1) +: 1]; + mem[256 * 57 + count] = INIT_39[(count * 1) +: 1]; + mem[256 * 58 + count] = INIT_3A[(count * 1) +: 1]; + mem[256 * 59 + count] = INIT_3B[(count * 1) +: 1]; + mem[256 * 60 + count] = INIT_3C[(count * 1) +: 1]; + mem[256 * 61 + count] = INIT_3D[(count * 1) +: 1]; + mem[256 * 62 + count] = INIT_3E[(count * 1) +: 1]; + mem[256 * 63 + count] = INIT_3F[(count * 1) +: 1]; + end + + + change_clka <= 0; + change_clkb <= 0; + data_collision <= 0; + data_collision_a_b <= 0; + data_collision_b_a <= 0; + memory_collision <= 0; + memory_collision_a_b <= 0; + memory_collision_b_a <= 0; + setup_all_a_b <= 0; + setup_all_b_a <= 0; + setup_zero <= 0; + setup_rf_a_b <= 0; + setup_rf_b_a <= 0; + end + + assign data_addra_int = addra_int * 1; + assign data_addra_reg = addra_reg * 1; + assign data_addrb_int = addrb_int * 1; + assign data_addrb_reg = addrb_reg * 1; + + + initial begin + + display_flag = 1; + output_flag = 1; + + case (SIM_COLLISION_CHECK) + + "NONE" : begin + output_flag = 0; + display_flag = 0; + end + "WARNING_ONLY" : output_flag = 0; + "GENERATE_X_ONLY" : display_flag = 0; + "ALL" : ; + + default : begin + $display("Attribute Syntax Error : The Attribute SIM_COLLISION_CHECK on RAMB16_S1_S1 instance %m is set to %s. Legal values for this attribute are ALL, NONE, WARNING_ONLY or GENERATE_X_ONLY.", SIM_COLLISION_CHECK); + $finish; + end + + endcase // case(SIM_COLLISION_CHECK) + + end // initial begin + + + always @(posedge clka_int) begin + if ((output_flag || display_flag)) begin + time_clka = $time; + #0 time_clkb_clka = time_clka - time_clkb; + change_clka = ~change_clka; + end + end + + always @(posedge clkb_int) begin + if ((output_flag || display_flag)) begin + time_clkb = $time; + #0 time_clka_clkb = time_clkb - time_clka; + change_clkb = ~change_clkb; + end + end + + always @(change_clkb) begin + if ((0 < time_clka_clkb) && (time_clka_clkb < SETUP_ALL)) + setup_all_a_b = 1; + if ((0 < time_clka_clkb) && (time_clka_clkb < SETUP_READ_FIRST)) + setup_rf_a_b = 1; + end + + always @(change_clka) begin + if ((0 < time_clkb_clka) && (time_clkb_clka < SETUP_ALL)) + setup_all_b_a = 1; + if ((0 < time_clkb_clka) && (time_clkb_clka < SETUP_READ_FIRST)) + setup_rf_b_a = 1; + end + + always @(change_clkb or change_clka) begin + if ((time_clkb_clka == 0) && (time_clka_clkb == 0)) + setup_zero = 1; + end + + always @(posedge setup_zero) begin + if ((ena_int == 1) && (wea_int == 1) && + (enb_int == 1) && (web_int == 1) && + (data_addra_int[14:0] == data_addrb_int[14:0])) + memory_collision <= 1; + end + + always @(posedge setup_all_a_b or posedge setup_rf_a_b) begin + if ((ena_reg == 1) && (wea_reg == 1) && + (enb_int == 1) && (web_int == 1) && + (data_addra_reg[14:0] == data_addrb_int[14:0])) + memory_collision_a_b <= 1; + end + + always @(posedge setup_all_b_a or posedge setup_rf_b_a) begin + if ((ena_int == 1) && (wea_int == 1) && + (enb_reg == 1) && (web_reg == 1) && + (data_addra_int[14:0] == data_addrb_reg[14:0])) + memory_collision_b_a <= 1; + end + + always @(posedge setup_all_a_b) begin + if (data_addra_reg[14:0] == data_addrb_int[14:0]) begin + if ((ena_reg == 1) && (enb_int == 1)) begin + case ({wr_mode_a, wr_mode_b, wea_reg, web_int}) + 6'b000011 : begin data_collision_a_b <= 2'b11; display_wa_wb; end + 6'b000111 : begin data_collision_a_b <= 2'b11; display_wa_wb; end + 6'b001011 : begin data_collision_a_b <= 2'b10; display_wa_wb; end +// 6'b010011 : begin data_collision_a_b <= 2'b00; display_wa_wb; end +// 6'b010111 : begin data_collision_a_b <= 2'b00; display_wa_wb; end +// 6'b011011 : begin data_collision_a_b <= 2'b00; display_wa_wb; end + 6'b100011 : begin data_collision_a_b <= 2'b01; display_wa_wb; end + 6'b100111 : begin data_collision_a_b <= 2'b01; display_wa_wb; end + 6'b101011 : begin display_wa_wb; end + 6'b000001 : begin data_collision_a_b <= 2'b10; display_ra_wb; end +// 6'b000101 : begin data_collision_a_b <= 2'b00; display_ra_wb; end + 6'b001001 : begin data_collision_a_b <= 2'b10; display_ra_wb; end + 6'b010001 : begin data_collision_a_b <= 2'b10; display_ra_wb; end +// 6'b010101 : begin data_collision_a_b <= 2'b00; display_ra_wb; end + 6'b011001 : begin data_collision_a_b <= 2'b10; display_ra_wb; end + 6'b100001 : begin data_collision_a_b <= 2'b10; display_ra_wb; end +// 6'b100101 : begin data_collision_a_b <= 2'b00; display_ra_wb; end + 6'b101001 : begin data_collision_a_b <= 2'b10; display_ra_wb; end + 6'b000010 : begin data_collision_a_b <= 2'b01; display_wa_rb; end + 6'b000110 : begin data_collision_a_b <= 2'b01; display_wa_rb; end + 6'b001010 : begin data_collision_a_b <= 2'b01; display_wa_rb; end +// 6'b010010 : begin data_collision_a_b <= 2'b00; display_wa_rb; end +// 6'b010110 : begin data_collision_a_b <= 2'b00; display_wa_rb; end +// 6'b011010 : begin data_collision_a_b <= 2'b00; display_wa_rb; end + 6'b100010 : begin data_collision_a_b <= 2'b01; display_wa_rb; end + 6'b100110 : begin data_collision_a_b <= 2'b01; display_wa_rb; end + 6'b101010 : begin data_collision_a_b <= 2'b01; display_wa_rb; end + endcase + end + end + setup_all_a_b <= 0; + end + + + always @(posedge setup_all_b_a) begin + if (data_addra_int[14:0] == data_addrb_reg[14:0]) begin + if ((ena_int == 1) && (enb_reg == 1)) begin + case ({wr_mode_a, wr_mode_b, wea_int, web_reg}) + 6'b000011 : begin data_collision_b_a <= 2'b11; display_wa_wb; end +// 6'b000111 : begin data_collision_b_a <= 2'b00; display_wa_wb; end + 6'b001011 : begin data_collision_b_a <= 2'b10; display_wa_wb; end + 6'b010011 : begin data_collision_b_a <= 2'b11; display_wa_wb; end +// 6'b010111 : begin data_collision_b_a <= 2'b00; display_wa_wb; end + 6'b011011 : begin data_collision_b_a <= 2'b10; display_wa_wb; end + 6'b100011 : begin data_collision_b_a <= 2'b01; display_wa_wb; end + 6'b100111 : begin data_collision_b_a <= 2'b01; display_wa_wb; end + 6'b101011 : begin display_wa_wb; end + 6'b000001 : begin data_collision_b_a <= 2'b10; display_ra_wb; end + 6'b000101 : begin data_collision_b_a <= 2'b10; display_ra_wb; end + 6'b001001 : begin data_collision_b_a <= 2'b10; display_ra_wb; end + 6'b010001 : begin data_collision_b_a <= 2'b10; display_ra_wb; end + 6'b010101 : begin data_collision_b_a <= 2'b10; display_ra_wb; end + 6'b011001 : begin data_collision_b_a <= 2'b10; display_ra_wb; end + 6'b100001 : begin data_collision_b_a <= 2'b10; display_ra_wb; end + 6'b100101 : begin data_collision_b_a <= 2'b10; display_ra_wb; end + 6'b101001 : begin data_collision_b_a <= 2'b10; display_ra_wb; end + 6'b000010 : begin data_collision_b_a <= 2'b01; display_wa_rb; end + 6'b000110 : begin data_collision_b_a <= 2'b01; display_wa_rb; end + 6'b001010 : begin data_collision_b_a <= 2'b01; display_wa_rb; end +// 6'b010010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end +// 6'b010110 : begin data_collision_b_a <= 2'b00; display_wa_rb; end +// 6'b011010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end + 6'b100010 : begin data_collision_b_a <= 2'b01; display_wa_rb; end + 6'b100110 : begin data_collision_b_a <= 2'b01; display_wa_rb; end + 6'b101010 : begin data_collision_b_a <= 2'b01; display_wa_rb; end + endcase + end + end + setup_all_b_a <= 0; + end + + + always @(posedge setup_zero) begin + if (data_addra_int[14:0] == data_addrb_int[14:0]) begin + if ((ena_int == 1) && (enb_int == 1)) begin + case ({wr_mode_a, wr_mode_b, wea_int, web_int}) + 6'b000011 : begin data_collision <= 2'b11; display_wa_wb; end + 6'b000111 : begin data_collision <= 2'b11; display_wa_wb; end + 6'b001011 : begin data_collision <= 2'b10; display_wa_wb; end + 6'b010011 : begin data_collision <= 2'b11; display_wa_wb; end + 6'b010111 : begin data_collision <= 2'b11; display_wa_wb; end + 6'b011011 : begin data_collision <= 2'b10; display_wa_wb; end + 6'b100011 : begin data_collision <= 2'b01; display_wa_wb; end + 6'b100111 : begin data_collision <= 2'b01; display_wa_wb; end + 6'b101011 : begin display_wa_wb; end + 6'b000001 : begin data_collision <= 2'b10; display_ra_wb; end +// 6'b000101 : begin data_collision <= 2'b00; display_ra_wb; end + 6'b001001 : begin data_collision <= 2'b10; display_ra_wb; end + 6'b010001 : begin data_collision <= 2'b10; display_ra_wb; end +// 6'b010101 : begin data_collision <= 2'b00; display_ra_wb; end + 6'b011001 : begin data_collision <= 2'b10; display_ra_wb; end + 6'b100001 : begin data_collision <= 2'b10; display_ra_wb; end +// 6'b100101 : begin data_collision <= 2'b00; display_ra_wb; end + 6'b101001 : begin data_collision <= 2'b10; display_ra_wb; end + 6'b000010 : begin data_collision <= 2'b01; display_wa_rb; end + 6'b000110 : begin data_collision <= 2'b01; display_wa_rb; end + 6'b001010 : begin data_collision <= 2'b01; display_wa_rb; end +// 6'b010010 : begin data_collision <= 2'b00; display_wa_rb; end +// 6'b010110 : begin data_collision <= 2'b00; display_wa_rb; end +// 6'b011010 : begin data_collision <= 2'b00; display_wa_rb; end + 6'b100010 : begin data_collision <= 2'b01; display_wa_rb; end + 6'b100110 : begin data_collision <= 2'b01; display_wa_rb; end + 6'b101010 : begin data_collision <= 2'b01; display_wa_rb; end + endcase + end + end + setup_zero <= 0; + end + + task display_ra_wb; + begin + if (display_flag) + $display("Memory Collision Error on RAMB16_S1_S1:%m at simulation time %.3f ns\nA read was performed on address %h (hex) of Port A while a write was requested to the same address on Port B. The write will be successful however the read value on Port A is unknown until the next CLKA cycle.", $time/1000.0, addra_int); + end + endtask + + task display_wa_rb; + begin + if (display_flag) + $display("Memory Collision Error on RAMB16_S1_S1:%m at simulation time %.3f ns\nA read was performed on address %h (hex) of Port B while a write was requested to the same address on Port A. The write will be successful however the read value on Port B is unknown until the next CLKB cycle.", $time/1000.0, addrb_int); + end + endtask + + task display_wa_wb; + begin + if (display_flag) + $display("Memory Collision Error on RAMB16_S1_S1:%m at simulation time %.3f ns\nA write was requested to the same address simultaneously at both Port A and Port B of the RAM. The contents written to the RAM at address location %h (hex) of Port A and address location %h (hex) of Port B are unknown.", $time/1000.0, addra_int, addrb_int); + end + endtask + + + always @(posedge setup_rf_a_b) begin + if (data_addra_reg[14:0] == data_addrb_int[14:0]) begin + if ((ena_reg == 1) && (enb_int == 1)) begin + case ({wr_mode_a, wr_mode_b, wea_reg, web_int}) +// 6'b000011 : begin data_collision_a_b <= 2'b00; display_wa_wb; end +// 6'b000111 : begin data_collision_a_b <= 2'b00; display_wa_wb; end +// 6'b001011 : begin data_collision_a_b <= 2'b00; display_wa_wb; end + 6'b010011 : begin data_collision_a_b <= 2'b11; display_wa_wb; end + 6'b010111 : begin data_collision_a_b <= 2'b11; display_wa_wb; end + 6'b011011 : begin data_collision_a_b <= 2'b10; display_wa_wb; end +// 6'b100011 : begin data_collision_a_b <= 2'b00; display_wa_wb; end +// 6'b100111 : begin data_collision_a_b <= 2'b00; display_wa_wb; end +// 6'b101011 : begin data_collision_a_b <= 2'b00; display_wa_wb; end +// 6'b000001 : begin data_collision_a_b <= 2'b00; display_ra_wb; end +// 6'b000101 : begin data_collision_a_b <= 2'b00; display_ra_wb; end +// 6'b001001 : begin data_collision_a_b <= 2'b00; display_ra_wb; end +// 6'b010001 : begin data_collision_a_b <= 2'b00; display_ra_wb; end +// 6'b010101 : begin data_collision_a_b <= 2'b00; display_ra_wb; end +// 6'b011001 : begin data_collision_a_b <= 2'b00; display_ra_wb; end +// 6'b100001 : begin data_collision_a_b <= 2'b00; display_ra_wb; end +// 6'b100101 : begin data_collision_a_b <= 2'b00; display_ra_wb; end +// 6'b101001 : begin data_collision_a_b <= 2'b00; display_ra_wb; end +// 6'b000010 : begin data_collision_a_b <= 2'b00; display_wa_rb; end +// 6'b000110 : begin data_collision_a_b <= 2'b00; display_wa_rb; end +// 6'b001010 : begin data_collision_a_b <= 2'b00; display_wa_rb; end + 6'b010010 : begin data_collision_a_b <= 2'b01; display_wa_rb; end + 6'b010110 : begin data_collision_a_b <= 2'b01; display_wa_rb; end + 6'b011010 : begin data_collision_a_b <= 2'b01; display_wa_rb; end +// 6'b100010 : begin data_collision_a_b <= 2'b00; display_wa_rb; end +// 6'b100110 : begin data_collision_a_b <= 2'b00; display_wa_rb; end +// 6'b101010 : begin data_collision_a_b <= 2'b00; display_wa_rb; end + endcase + end + end + setup_rf_a_b <= 0; + end + + + always @(posedge setup_rf_b_a) begin + if (data_addra_int[14:0] == data_addrb_reg[14:0]) begin + if ((ena_int == 1) && (enb_reg == 1)) begin + case ({wr_mode_a, wr_mode_b, wea_int, web_reg}) +// 6'b000011 : begin data_collision_b_a <= 2'b00; display_wa_wb; end + 6'b000111 : begin data_collision_b_a <= 2'b11; display_wa_wb; end +// 6'b001011 : begin data_collision_b_a <= 2'b00; display_wa_wb; end +// 6'b010011 : begin data_collision_b_a <= 2'b00; display_wa_wb; end + 6'b010111 : begin data_collision_b_a <= 2'b11; display_wa_wb; end +// 6'b011011 : begin data_collision_b_a <= 2'b00; display_wa_wb; end +// 6'b100011 : begin data_collision_b_a <= 2'b00; display_wa_wb; end + 6'b100111 : begin data_collision_b_a <= 2'b01; display_wa_wb; end +// 6'b101011 : begin data_collision_b_a <= 2'b00; display_wa_wb; end +// 6'b000001 : begin data_collision_b_a <= 2'b00; display_ra_wb; end + 6'b000101 : begin data_collision_b_a <= 2'b10; display_ra_wb; end +// 6'b001001 : begin data_collision_b_a <= 2'b00; display_ra_wb; end +// 6'b010001 : begin data_collision_b_a <= 2'b00; display_ra_wb; end + 6'b010101 : begin data_collision_b_a <= 2'b10; display_ra_wb; end +// 6'b011001 : begin data_collision_b_a <= 2'b00; display_ra_wb; end +// 6'b100001 : begin data_collision_b_a <= 2'b00; display_ra_wb; end + 6'b100101 : begin data_collision_b_a <= 2'b10; display_ra_wb; end +// 6'b101001 : begin data_collision_b_a <= 2'b00; display_ra_wb; end +// 6'b000010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end +// 6'b000110 : begin data_collision_b_a <= 2'b00; display_wa_rb; end +// 6'b001010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end +// 6'b010010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end +// 6'b010110 : begin data_collision_b_a <= 2'b00; display_wa_rb; end +// 6'b011010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end +// 6'b100010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end +// 6'b100110 : begin data_collision_b_a <= 2'b00; display_wa_rb; end +// 6'b101010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end + endcase + end + end + setup_rf_b_a <= 0; + end + + + always @(posedge clka_int) begin + if ((output_flag || display_flag)) begin + addra_reg <= addra_int; + ena_reg <= ena_int; + ssra_reg <= ssra_int; + wea_reg <= wea_int; + end + end + + always @(posedge clkb_int) begin + if ((output_flag || display_flag)) begin + addrb_reg <= addrb_int; + enb_reg <= enb_int; + ssrb_reg <= ssrb_int; + web_reg <= web_int; + end + end + + + // Data + always @(posedge memory_collision) begin + if ((output_flag || display_flag)) begin + mem[addra_int] <= 1'bx; + memory_collision <= 0; + end + + end + + always @(posedge memory_collision_a_b) begin + if ((output_flag || display_flag)) begin + mem[addra_reg] <= 1'bx; + memory_collision_a_b <= 0; + end + end + + always @(posedge memory_collision_b_a) begin + if ((output_flag || display_flag)) begin + mem[addra_int] <= 1'bx; + memory_collision_b_a <= 0; + end + end + + always @(posedge data_collision[1]) begin + if (ssra_int == 0 && output_flag) begin + doa_out <= #100 1'bX; + end + data_collision[1] <= 0; + end + + always @(posedge data_collision[0]) begin + if (ssrb_int == 0 && output_flag) begin + dob_out <= #100 1'bX; + end + data_collision[0] <= 0; + end + + always @(posedge data_collision_a_b[1]) begin + if (ssra_reg == 0 && output_flag) begin + doa_out <= #100 1'bX; + end + data_collision_a_b[1] <= 0; + end + + always @(posedge data_collision_a_b[0]) begin + if (ssrb_int == 0 && output_flag) begin + dob_out <= #100 1'bX; + end + data_collision_a_b[0] <= 0; + end + + always @(posedge data_collision_b_a[1]) begin + if (ssra_int == 0 && output_flag) begin + doa_out <= #100 1'bX; + end + data_collision_b_a[1] <= 0; + end + + always @(posedge data_collision_b_a[0]) begin + if (ssrb_reg == 0 && output_flag) begin + dob_out <= #100 1'bX; + end + data_collision_b_a[0] <= 0; + end + + + initial begin + case (WRITE_MODE_A) + "WRITE_FIRST" : wr_mode_a <= 2'b00; + "READ_FIRST" : wr_mode_a <= 2'b01; + "NO_CHANGE" : wr_mode_a <= 2'b10; + default : begin + $display("Attribute Syntax Error : The Attribute WRITE_MODE_A on RAMB16_S1_S1 instance %m is set to %s. Legal values for this attribute are WRITE_FIRST, READ_FIRST or NO_CHANGE.", WRITE_MODE_A); + $finish; + end + endcase + end + + initial begin + case (WRITE_MODE_B) + "WRITE_FIRST" : wr_mode_b <= 2'b00; + "READ_FIRST" : wr_mode_b <= 2'b01; + "NO_CHANGE" : wr_mode_b <= 2'b10; + default : begin + $display("Attribute Syntax Error : The Attribute WRITE_MODE_B on RAMB16_S1_S1 instance %m is set to %s. Legal values for this attribute are WRITE_FIRST, READ_FIRST or NO_CHANGE.", WRITE_MODE_B); + $finish; + end + endcase + end + + + // Port A + always @(posedge clka_int) begin + + if (ena_int == 1'b1) begin + + if (ssra_int == 1'b1) begin + {doa_out} <= #100 SRVAL_A; + end + else begin + if (wea_int == 1'b1) begin + if (wr_mode_a == 2'b00) begin + doa_out <= #100 dia_int; + end + else if (wr_mode_a == 2'b01) begin + + doa_out <= #100 mem[addra_int]; + + end + end + else begin + + doa_out <= #100 mem[addra_int]; + + end + end + + // memory + if (wea_int == 1'b1) begin + mem[addra_int] <= dia_int; + end + + end + end + + + // Port B + always @(posedge clkb_int) begin + + if (enb_int == 1'b1) begin + + if (ssrb_int == 1'b1) begin + {dob_out} <= #100 SRVAL_B; + end + else begin + if (web_int == 1'b1) begin + if (wr_mode_b == 2'b00) begin + dob_out <= #100 dib_int; + end + else if (wr_mode_b == 2'b01) begin + dob_out <= #100 mem[addrb_int]; + end + end + else begin + dob_out <= #100 mem[addrb_int]; + end + end + + // memory + if (web_int == 1'b1) begin + mem[addrb_int] <= dib_int; + end + + end + end + + +endmodule + +`endif diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/RAMB16_S1_S18.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/RAMB16_S1_S18.v new file mode 100644 index 0000000..5948d77 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/RAMB16_S1_S18.v @@ -0,0 +1,1704 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/RAMB16_S1_S18.v,v 1.10 2007/02/22 01:58:05 wloo Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2005 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / 16K-Bit Data and 2K-Bit Parity Dual Port Block RAM +// /___/ /\ Filename : RAMB16_S1_S18.v +// \ \ / \ Timestamp : Thu Mar 10 16:43:35 PST 2005 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// End Revision + +`ifdef legacy_model + +`timescale 1 ps / 1 ps + +module RAMB16_S1_S18 (DOA, DOB, DOPB, ADDRA, ADDRB, CLKA, CLKB, DIA, DIB, DIPB, ENA, ENB, SSRA, SSRB, WEA, WEB); + + parameter INIT_A = 1'h0; + parameter INIT_B = 18'h0; + parameter SRVAL_A = 1'h0; + parameter SRVAL_B = 18'h0; + parameter WRITE_MODE_A = "WRITE_FIRST"; + parameter WRITE_MODE_B = "WRITE_FIRST"; + parameter SIM_COLLISION_CHECK = "ALL"; + localparam SETUP_ALL = 1000; + localparam SETUP_READ_FIRST = 3000; + + parameter INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + + output [0:0] DOA; + reg [0:0] doa_out; + wire doa_out0; + + input [13:0] ADDRA; + input [0:0] DIA; + input ENA, CLKA, WEA, SSRA; + + output [15:0] DOB; + output [1:0] DOPB; + reg [15:0] dob_out; + reg [1:0] dopb_out; + wire dob_out0, dob_out1, dob_out2, dob_out3, dob_out4, dob_out5, dob_out6, dob_out7, dob_out8, dob_out9, dob_out10, dob_out11, dob_out12, dob_out13, dob_out14, dob_out15; + wire dopb0_out, dopb1_out; + + input [9:0] ADDRB; + input [15:0] DIB; + input [1:0] DIPB; + input ENB, CLKB, WEB, SSRB; + + reg [18431:0] mem; + reg [8:0] count; + reg [1:0] wr_mode_a, wr_mode_b; + + reg [5:0] dmi, dbi; + reg [5:0] pmi, pbi; + + wire [13:0] addra_int; + reg [13:0] addra_reg; + wire [0:0] dia_int; + wire ena_int, clka_int, wea_int, ssra_int; + reg ena_reg, wea_reg, ssra_reg; + wire [9:0] addrb_int; + reg [9:0] addrb_reg; + wire [15:0] dib_int; + wire [1:0] dipb_int; + wire enb_int, clkb_int, web_int, ssrb_int; + reg display_flag; + reg enb_reg, web_reg, ssrb_reg; + + time time_clka, time_clkb; + time time_clka_clkb; + time time_clkb_clka; + + reg setup_all_a_b; + reg setup_all_b_a; + reg setup_zero; + reg setup_rf_a_b; + reg setup_rf_b_a; + reg [1:0] data_collision, data_collision_a_b, data_collision_b_a; + reg memory_collision, memory_collision_a_b, memory_collision_b_a; + reg address_collision, address_collision_a_b, address_collision_b_a; + reg change_clka; + reg change_clkb; + + wire [14:0] data_addra_int; + wire [14:0] data_addra_reg; + wire [14:0] data_addrb_int; + wire [14:0] data_addrb_reg; + wire [15:0] parity_addra_int; + wire [15:0] parity_addra_reg; + wire [15:0] parity_addrb_int; + wire [15:0] parity_addrb_reg; + + tri0 GSR = glbl.GSR; + + always @(GSR) + if (GSR) begin + assign doa_out = INIT_A[0:0]; + assign dob_out = INIT_B[15:0]; + assign dopb_out = INIT_B[17:16]; + end + else begin + deassign doa_out; + deassign dob_out; + deassign dopb_out; + end + + buf b_doa_out0 (doa_out0, doa_out[0]); + buf b_dob_out0 (dob_out0, dob_out[0]); + buf b_dob_out1 (dob_out1, dob_out[1]); + buf b_dob_out2 (dob_out2, dob_out[2]); + buf b_dob_out3 (dob_out3, dob_out[3]); + buf b_dob_out4 (dob_out4, dob_out[4]); + buf b_dob_out5 (dob_out5, dob_out[5]); + buf b_dob_out6 (dob_out6, dob_out[6]); + buf b_dob_out7 (dob_out7, dob_out[7]); + buf b_dob_out8 (dob_out8, dob_out[8]); + buf b_dob_out9 (dob_out9, dob_out[9]); + buf b_dob_out10 (dob_out10, dob_out[10]); + buf b_dob_out11 (dob_out11, dob_out[11]); + buf b_dob_out12 (dob_out12, dob_out[12]); + buf b_dob_out13 (dob_out13, dob_out[13]); + buf b_dob_out14 (dob_out14, dob_out[14]); + buf b_dob_out15 (dob_out15, dob_out[15]); + buf b_dopb_out0 (dopb_out0, dopb_out[0]); + buf b_dopb_out1 (dopb_out1, dopb_out[1]); + + buf b_doa0 (DOA[0], doa_out0); + buf b_dob0 (DOB[0], dob_out0); + buf b_dob1 (DOB[1], dob_out1); + buf b_dob2 (DOB[2], dob_out2); + buf b_dob3 (DOB[3], dob_out3); + buf b_dob4 (DOB[4], dob_out4); + buf b_dob5 (DOB[5], dob_out5); + buf b_dob6 (DOB[6], dob_out6); + buf b_dob7 (DOB[7], dob_out7); + buf b_dob8 (DOB[8], dob_out8); + buf b_dob9 (DOB[9], dob_out9); + buf b_dob10 (DOB[10], dob_out10); + buf b_dob11 (DOB[11], dob_out11); + buf b_dob12 (DOB[12], dob_out12); + buf b_dob13 (DOB[13], dob_out13); + buf b_dob14 (DOB[14], dob_out14); + buf b_dob15 (DOB[15], dob_out15); + buf b_dopb0 (DOPB[0], dopb_out0); + buf b_dopb1 (DOPB[1], dopb_out1); + + buf b_addra_0 (addra_int[0], ADDRA[0]); + buf b_addra_1 (addra_int[1], ADDRA[1]); + buf b_addra_2 (addra_int[2], ADDRA[2]); + buf b_addra_3 (addra_int[3], ADDRA[3]); + buf b_addra_4 (addra_int[4], ADDRA[4]); + buf b_addra_5 (addra_int[5], ADDRA[5]); + buf b_addra_6 (addra_int[6], ADDRA[6]); + buf b_addra_7 (addra_int[7], ADDRA[7]); + buf b_addra_8 (addra_int[8], ADDRA[8]); + buf b_addra_9 (addra_int[9], ADDRA[9]); + buf b_addra_10 (addra_int[10], ADDRA[10]); + buf b_addra_11 (addra_int[11], ADDRA[11]); + buf b_addra_12 (addra_int[12], ADDRA[12]); + buf b_addra_13 (addra_int[13], ADDRA[13]); + buf b_dia_0 (dia_int[0], DIA[0]); + buf b_ena (ena_int, ENA); + buf b_clka (clka_int, CLKA); + buf b_ssra (ssra_int, SSRA); + buf b_wea (wea_int, WEA); + buf b_addrb_0 (addrb_int[0], ADDRB[0]); + buf b_addrb_1 (addrb_int[1], ADDRB[1]); + buf b_addrb_2 (addrb_int[2], ADDRB[2]); + buf b_addrb_3 (addrb_int[3], ADDRB[3]); + buf b_addrb_4 (addrb_int[4], ADDRB[4]); + buf b_addrb_5 (addrb_int[5], ADDRB[5]); + buf b_addrb_6 (addrb_int[6], ADDRB[6]); + buf b_addrb_7 (addrb_int[7], ADDRB[7]); + buf b_addrb_8 (addrb_int[8], ADDRB[8]); + buf b_addrb_9 (addrb_int[9], ADDRB[9]); + buf b_dib_0 (dib_int[0], DIB[0]); + buf b_dib_1 (dib_int[1], DIB[1]); + buf b_dib_2 (dib_int[2], DIB[2]); + buf b_dib_3 (dib_int[3], DIB[3]); + buf b_dib_4 (dib_int[4], DIB[4]); + buf b_dib_5 (dib_int[5], DIB[5]); + buf b_dib_6 (dib_int[6], DIB[6]); + buf b_dib_7 (dib_int[7], DIB[7]); + buf b_dib_8 (dib_int[8], DIB[8]); + buf b_dib_9 (dib_int[9], DIB[9]); + buf b_dib_10 (dib_int[10], DIB[10]); + buf b_dib_11 (dib_int[11], DIB[11]); + buf b_dib_12 (dib_int[12], DIB[12]); + buf b_dib_13 (dib_int[13], DIB[13]); + buf b_dib_14 (dib_int[14], DIB[14]); + buf b_dib_15 (dib_int[15], DIB[15]); + buf b_dipb_0 (dipb_int[0], DIPB[0]); + buf b_dipb_1 (dipb_int[1], DIPB[1]); + buf b_enb (enb_int, ENB); + buf b_clkb (clkb_int, CLKB); + buf b_ssrb (ssrb_int, SSRB); + buf b_web (web_int, WEB); + + initial begin + for (count = 0; count < 256; count = count + 1) begin + mem[count] <= INIT_00[count]; + mem[256 * 1 + count] <= INIT_01[count]; + mem[256 * 2 + count] <= INIT_02[count]; + mem[256 * 3 + count] <= INIT_03[count]; + mem[256 * 4 + count] <= INIT_04[count]; + mem[256 * 5 + count] <= INIT_05[count]; + mem[256 * 6 + count] <= INIT_06[count]; + mem[256 * 7 + count] <= INIT_07[count]; + mem[256 * 8 + count] <= INIT_08[count]; + mem[256 * 9 + count] <= INIT_09[count]; + mem[256 * 10 + count] <= INIT_0A[count]; + mem[256 * 11 + count] <= INIT_0B[count]; + mem[256 * 12 + count] <= INIT_0C[count]; + mem[256 * 13 + count] <= INIT_0D[count]; + mem[256 * 14 + count] <= INIT_0E[count]; + mem[256 * 15 + count] <= INIT_0F[count]; + mem[256 * 16 + count] <= INIT_10[count]; + mem[256 * 17 + count] <= INIT_11[count]; + mem[256 * 18 + count] <= INIT_12[count]; + mem[256 * 19 + count] <= INIT_13[count]; + mem[256 * 20 + count] <= INIT_14[count]; + mem[256 * 21 + count] <= INIT_15[count]; + mem[256 * 22 + count] <= INIT_16[count]; + mem[256 * 23 + count] <= INIT_17[count]; + mem[256 * 24 + count] <= INIT_18[count]; + mem[256 * 25 + count] <= INIT_19[count]; + mem[256 * 26 + count] <= INIT_1A[count]; + mem[256 * 27 + count] <= INIT_1B[count]; + mem[256 * 28 + count] <= INIT_1C[count]; + mem[256 * 29 + count] <= INIT_1D[count]; + mem[256 * 30 + count] <= INIT_1E[count]; + mem[256 * 31 + count] <= INIT_1F[count]; + mem[256 * 32 + count] <= INIT_20[count]; + mem[256 * 33 + count] <= INIT_21[count]; + mem[256 * 34 + count] <= INIT_22[count]; + mem[256 * 35 + count] <= INIT_23[count]; + mem[256 * 36 + count] <= INIT_24[count]; + mem[256 * 37 + count] <= INIT_25[count]; + mem[256 * 38 + count] <= INIT_26[count]; + mem[256 * 39 + count] <= INIT_27[count]; + mem[256 * 40 + count] <= INIT_28[count]; + mem[256 * 41 + count] <= INIT_29[count]; + mem[256 * 42 + count] <= INIT_2A[count]; + mem[256 * 43 + count] <= INIT_2B[count]; + mem[256 * 44 + count] <= INIT_2C[count]; + mem[256 * 45 + count] <= INIT_2D[count]; + mem[256 * 46 + count] <= INIT_2E[count]; + mem[256 * 47 + count] <= INIT_2F[count]; + mem[256 * 48 + count] <= INIT_30[count]; + mem[256 * 49 + count] <= INIT_31[count]; + mem[256 * 50 + count] <= INIT_32[count]; + mem[256 * 51 + count] <= INIT_33[count]; + mem[256 * 52 + count] <= INIT_34[count]; + mem[256 * 53 + count] <= INIT_35[count]; + mem[256 * 54 + count] <= INIT_36[count]; + mem[256 * 55 + count] <= INIT_37[count]; + mem[256 * 56 + count] <= INIT_38[count]; + mem[256 * 57 + count] <= INIT_39[count]; + mem[256 * 58 + count] <= INIT_3A[count]; + mem[256 * 59 + count] <= INIT_3B[count]; + mem[256 * 60 + count] <= INIT_3C[count]; + mem[256 * 61 + count] <= INIT_3D[count]; + mem[256 * 62 + count] <= INIT_3E[count]; + mem[256 * 63 + count] <= INIT_3F[count]; + mem[256 * 64 + count] <= INITP_00[count]; + mem[256 * 65 + count] <= INITP_01[count]; + mem[256 * 66 + count] <= INITP_02[count]; + mem[256 * 67 + count] <= INITP_03[count]; + mem[256 * 68 + count] <= INITP_04[count]; + mem[256 * 69 + count] <= INITP_05[count]; + mem[256 * 70 + count] <= INITP_06[count]; + mem[256 * 71 + count] <= INITP_07[count]; + end + address_collision <= 0; + address_collision_a_b <= 0; + address_collision_b_a <= 0; + change_clka <= 0; + change_clkb <= 0; + data_collision <= 0; + data_collision_a_b <= 0; + data_collision_b_a <= 0; + memory_collision <= 0; + memory_collision_a_b <= 0; + memory_collision_b_a <= 0; + setup_all_a_b <= 0; + setup_all_b_a <= 0; + setup_zero <= 0; + setup_rf_a_b <= 0; + setup_rf_b_a <= 0; + end + + assign data_addra_int = addra_int * 1; + assign data_addra_reg = addra_reg * 1; + assign data_addrb_int = addrb_int * 16; + assign data_addrb_reg = addrb_reg * 16; + assign parity_addrb_int = 16384 + addrb_int * 2; + assign parity_addrb_reg = 16384 + addrb_reg * 2; + + + initial begin + + display_flag = 1; + + case (SIM_COLLISION_CHECK) + + "NONE" : begin + assign setup_all_a_b = 1'b0; + assign setup_all_b_a = 1'b0; + assign setup_zero = 1'b0; + assign setup_rf_a_b = 1'b0; + assign setup_rf_b_a = 1'b0; + assign display_flag = 0; + end + "WARNING_ONLY" : begin + assign data_collision = 2'b00; + assign data_collision_a_b = 2'b00; + assign data_collision_b_a = 2'b00; + assign memory_collision = 1'b0; + assign memory_collision_a_b = 1'b0; + assign memory_collision_b_a = 1'b0; + end + "GENERATE_X_ONLY" : begin + assign display_flag = 0; + end + "ALL" : ; + default : begin + $display("Attribute Syntax Error : The Attribute SIM_COLLISION_CHECK on RAMB16_S1_S18 instance %m is set to %s. Legal values for this attribute are ALL, NONE, WARNING_ONLY or GENERATE_X_ONLY.", SIM_COLLISION_CHECK); + $finish; + end + + endcase // case(SIM_COLLISION_CHECK) + + end // initial begin + + + always @(posedge clka_int) begin + time_clka = $time; + #0 time_clkb_clka = time_clka - time_clkb; + change_clka = ~change_clka; + end + + always @(posedge clkb_int) begin + time_clkb = $time; + #0 time_clka_clkb = time_clkb - time_clka; + change_clkb = ~change_clkb; + end + + always @(change_clkb) begin + if ((0 < time_clka_clkb) && (time_clka_clkb < SETUP_ALL)) + setup_all_a_b = 1; + if ((0 < time_clka_clkb) && (time_clka_clkb < SETUP_READ_FIRST)) + setup_rf_a_b = 1; + end + + always @(change_clka) begin + if ((0 < time_clkb_clka) && (time_clkb_clka < SETUP_ALL)) + setup_all_b_a = 1; + if ((0 < time_clkb_clka) && (time_clkb_clka < SETUP_READ_FIRST)) + setup_rf_b_a = 1; + end + + always @(change_clkb or change_clka) begin + if ((time_clkb_clka == 0) && (time_clka_clkb == 0)) + setup_zero = 1; + end + + always @(posedge setup_zero) begin + if ((ena_int == 1) && (wea_int == 1) && + (enb_int == 1) && (web_int == 1) && + (data_addra_int[14:4] == data_addrb_int[14:4])) + memory_collision <= 1; + end + + always @(posedge setup_all_a_b or posedge setup_rf_a_b) begin + if ((ena_reg == 1) && (wea_reg == 1) && + (enb_int == 1) && (web_int == 1) && + (data_addra_reg[14:4] == data_addrb_int[14:4])) + memory_collision_a_b <= 1; + end + + always @(posedge setup_all_b_a or posedge setup_rf_b_a) begin + if ((ena_int == 1) && (wea_int == 1) && + (enb_reg == 1) && (web_reg == 1) && + (data_addra_int[14:4] == data_addrb_reg[14:4])) + memory_collision_b_a <= 1; + end + + always @(posedge setup_all_a_b) begin + if (data_addra_reg[14:4] == data_addrb_int[14:4]) begin + if ((ena_reg == 1) && (enb_int == 1)) begin + case ({wr_mode_a, wr_mode_b, wea_reg, web_int}) + 6'b000011 : begin data_collision_a_b <= 2'b11; display_wa_wb; end + 6'b000111 : begin data_collision_a_b <= 2'b11; display_wa_wb; end + 6'b001011 : begin data_collision_a_b <= 2'b10; display_wa_wb; end +// 6'b010011 : begin data_collision_a_b <= 2'b00; display_wa_wb; end +// 6'b010111 : begin data_collision_a_b <= 2'b00; display_wa_wb; end +// 6'b011011 : begin data_collision_a_b <= 2'b00; display_wa_wb; end + 6'b100011 : begin data_collision_a_b <= 2'b01; display_wa_wb; end + 6'b100111 : begin data_collision_a_b <= 2'b01; display_wa_wb; end + 6'b101011 : begin display_wa_wb; end + 6'b000001 : begin data_collision_a_b <= 2'b10; display_ra_wb; end +// 6'b000101 : begin data_collision_a_b <= 2'b00; display_ra_wb; end + 6'b001001 : begin data_collision_a_b <= 2'b10; display_ra_wb; end + 6'b010001 : begin data_collision_a_b <= 2'b10; display_ra_wb; end +// 6'b010101 : begin data_collision_a_b <= 2'b00; display_ra_wb; end + 6'b011001 : begin data_collision_a_b <= 2'b10; display_ra_wb; end + 6'b100001 : begin data_collision_a_b <= 2'b10; display_ra_wb; end +// 6'b100101 : begin data_collision_a_b <= 2'b00; display_ra_wb; end + 6'b101001 : begin data_collision_a_b <= 2'b10; display_ra_wb; end + 6'b000010 : begin data_collision_a_b <= 2'b01; display_wa_rb; end + 6'b000110 : begin data_collision_a_b <= 2'b01; display_wa_rb; end + 6'b001010 : begin data_collision_a_b <= 2'b01; display_wa_rb; end +// 6'b010010 : begin data_collision_a_b <= 2'b00; display_wa_rb; end +// 6'b010110 : begin data_collision_a_b <= 2'b00; display_wa_rb; end +// 6'b011010 : begin data_collision_a_b <= 2'b00; display_wa_rb; end + 6'b100010 : begin data_collision_a_b <= 2'b01; display_wa_rb; end + 6'b100110 : begin data_collision_a_b <= 2'b01; display_wa_rb; end + 6'b101010 : begin data_collision_a_b <= 2'b01; display_wa_rb; end + endcase + end + end + setup_all_a_b <= 0; + end + + + always @(posedge setup_all_b_a) begin + if (data_addra_int[14:4] == data_addrb_reg[14:4]) begin + if ((ena_int == 1) && (enb_reg == 1)) begin + case ({wr_mode_a, wr_mode_b, wea_int, web_reg}) + 6'b000011 : begin data_collision_b_a <= 2'b11; display_wa_wb; end +// 6'b000111 : begin data_collision_b_a <= 2'b00; display_wa_wb; end + 6'b001011 : begin data_collision_b_a <= 2'b10; display_wa_wb; end + 6'b010011 : begin data_collision_b_a <= 2'b11; display_wa_wb; end +// 6'b010111 : begin data_collision_b_a <= 2'b00; display_wa_wb; end + 6'b011011 : begin data_collision_b_a <= 2'b10; display_wa_wb; end + 6'b100011 : begin data_collision_b_a <= 2'b01; display_wa_wb; end + 6'b100111 : begin data_collision_b_a <= 2'b01; display_wa_wb; end + 6'b101011 : begin display_wa_wb; end + 6'b000001 : begin data_collision_b_a <= 2'b10; display_ra_wb; end + 6'b000101 : begin data_collision_b_a <= 2'b10; display_ra_wb; end + 6'b001001 : begin data_collision_b_a <= 2'b10; display_ra_wb; end + 6'b010001 : begin data_collision_b_a <= 2'b10; display_ra_wb; end + 6'b010101 : begin data_collision_b_a <= 2'b10; display_ra_wb; end + 6'b011001 : begin data_collision_b_a <= 2'b10; display_ra_wb; end + 6'b100001 : begin data_collision_b_a <= 2'b10; display_ra_wb; end + 6'b100101 : begin data_collision_b_a <= 2'b10; display_ra_wb; end + 6'b101001 : begin data_collision_b_a <= 2'b10; display_ra_wb; end + 6'b000010 : begin data_collision_b_a <= 2'b01; display_wa_rb; end + 6'b000110 : begin data_collision_b_a <= 2'b01; display_wa_rb; end + 6'b001010 : begin data_collision_b_a <= 2'b01; display_wa_rb; end +// 6'b010010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end +// 6'b010110 : begin data_collision_b_a <= 2'b00; display_wa_rb; end +// 6'b011010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end + 6'b100010 : begin data_collision_b_a <= 2'b01; display_wa_rb; end + 6'b100110 : begin data_collision_b_a <= 2'b01; display_wa_rb; end + 6'b101010 : begin data_collision_b_a <= 2'b01; display_wa_rb; end + endcase + end + end + setup_all_b_a <= 0; + end + + + always @(posedge setup_zero) begin + if (data_addra_int[14:4] == data_addrb_int[14:4]) begin + if ((ena_int == 1) && (enb_int == 1)) begin + case ({wr_mode_a, wr_mode_b, wea_int, web_int}) + 6'b000011 : begin data_collision <= 2'b11; display_wa_wb; end + 6'b000111 : begin data_collision <= 2'b11; display_wa_wb; end + 6'b001011 : begin data_collision <= 2'b10; display_wa_wb; end + 6'b010011 : begin data_collision <= 2'b11; display_wa_wb; end + 6'b010111 : begin data_collision <= 2'b11; display_wa_wb; end + 6'b011011 : begin data_collision <= 2'b10; display_wa_wb; end + 6'b100011 : begin data_collision <= 2'b01; display_wa_wb; end + 6'b100111 : begin data_collision <= 2'b01; display_wa_wb; end + 6'b101011 : begin display_wa_wb; end + 6'b000001 : begin data_collision <= 2'b10; display_ra_wb; end +// 6'b000101 : begin data_collision <= 2'b00; display_ra_wb; end + 6'b001001 : begin data_collision <= 2'b10; display_ra_wb; end + 6'b010001 : begin data_collision <= 2'b10; display_ra_wb; end +// 6'b010101 : begin data_collision <= 2'b00; display_ra_wb; end + 6'b011001 : begin data_collision <= 2'b10; display_ra_wb; end + 6'b100001 : begin data_collision <= 2'b10; display_ra_wb; end +// 6'b100101 : begin data_collision <= 2'b00; display_ra_wb; end + 6'b101001 : begin data_collision <= 2'b10; display_ra_wb; end + 6'b000010 : begin data_collision <= 2'b01; display_wa_rb; end + 6'b000110 : begin data_collision <= 2'b01; display_wa_rb; end + 6'b001010 : begin data_collision <= 2'b01; display_wa_rb; end +// 6'b010010 : begin data_collision <= 2'b00; display_wa_rb; end +// 6'b010110 : begin data_collision <= 2'b00; display_wa_rb; end +// 6'b011010 : begin data_collision <= 2'b00; display_wa_rb; end + 6'b100010 : begin data_collision <= 2'b01; display_wa_rb; end + 6'b100110 : begin data_collision <= 2'b01; display_wa_rb; end + 6'b101010 : begin data_collision <= 2'b01; display_wa_rb; end + endcase + end + end + setup_zero <= 0; + end + + task display_ra_wb; + begin + if (display_flag) + $display("Memory Collision Error on RAMB16_S1_S18:%m at simulation time %.3f ns\nA read was performed on address %h (hex) of Port A while a write was requested to the same address on Port B. The write will be successful however the read value on Port A is unknown until the next CLKA cycle.", $time/1000.0, addra_int); + end + endtask + + task display_wa_rb; + begin + if (display_flag) + $display("Memory Collision Error on RAMB16_S1_S18:%m at simulation time %.3f ns\nA read was performed on address %h (hex) of Port B while a write was requested to the same address on Port A. The write will be successful however the read value on Port B is unknown until the next CLKB cycle.", $time/1000.0, addrb_int); + end + endtask + + task display_wa_wb; + begin + if (display_flag) + $display("Memory Collision Error on RAMB16_S1_S18:%m at simulation time %.3f ns\nA write was requested to the same address simultaneously at both Port A and Port B of the RAM. The contents written to the RAM at address location %h (hex) of Port A and address location %h (hex) of Port B are unknown.", $time/1000.0, addra_int, addrb_int); + end + endtask + + + always @(posedge setup_rf_a_b) begin + if (data_addra_reg[14:4] == data_addrb_int[14:4]) begin + if ((ena_reg == 1) && (enb_int == 1)) begin + case ({wr_mode_a, wr_mode_b, wea_reg, web_int}) +// 6'b000011 : begin data_collision_a_b <= 2'b00; display_wa_wb; end +// 6'b000111 : begin data_collision_a_b <= 2'b00; display_wa_wb; end +// 6'b001011 : begin data_collision_a_b <= 2'b00; display_wa_wb; end + 6'b010011 : begin data_collision_a_b <= 2'b11; display_wa_wb; end + 6'b010111 : begin data_collision_a_b <= 2'b11; display_wa_wb; end + 6'b011011 : begin data_collision_a_b <= 2'b10; display_wa_wb; end +// 6'b100011 : begin data_collision_a_b <= 2'b00; display_wa_wb; end +// 6'b100111 : begin data_collision_a_b <= 2'b00; display_wa_wb; end +// 6'b101011 : begin data_collision_a_b <= 2'b00; display_wa_wb; end +// 6'b000001 : begin data_collision_a_b <= 2'b00; display_ra_wb; end +// 6'b000101 : begin data_collision_a_b <= 2'b00; display_ra_wb; end +// 6'b001001 : begin data_collision_a_b <= 2'b00; display_ra_wb; end +// 6'b010001 : begin data_collision_a_b <= 2'b00; display_ra_wb; end +// 6'b010101 : begin data_collision_a_b <= 2'b00; display_ra_wb; end +// 6'b011001 : begin data_collision_a_b <= 2'b00; display_ra_wb; end +// 6'b100001 : begin data_collision_a_b <= 2'b00; display_ra_wb; end +// 6'b100101 : begin data_collision_a_b <= 2'b00; display_ra_wb; end +// 6'b101001 : begin data_collision_a_b <= 2'b00; display_ra_wb; end +// 6'b000010 : begin data_collision_a_b <= 2'b00; display_wa_rb; end +// 6'b000110 : begin data_collision_a_b <= 2'b00; display_wa_rb; end +// 6'b001010 : begin data_collision_a_b <= 2'b00; display_wa_rb; end + 6'b010010 : begin data_collision_a_b <= 2'b01; display_wa_rb; end + 6'b010110 : begin data_collision_a_b <= 2'b01; display_wa_rb; end + 6'b011010 : begin data_collision_a_b <= 2'b01; display_wa_rb; end +// 6'b100010 : begin data_collision_a_b <= 2'b00; display_wa_rb; end +// 6'b100110 : begin data_collision_a_b <= 2'b00; display_wa_rb; end +// 6'b101010 : begin data_collision_a_b <= 2'b00; display_wa_rb; end + endcase + end + end + setup_rf_a_b <= 0; + end + + + always @(posedge setup_rf_b_a) begin + if (data_addra_int[14:4] == data_addrb_reg[14:4]) begin + if ((ena_int == 1) && (enb_reg == 1)) begin + case ({wr_mode_a, wr_mode_b, wea_int, web_reg}) +// 6'b000011 : begin data_collision_b_a <= 2'b00; display_wa_wb; end + 6'b000111 : begin data_collision_b_a <= 2'b11; display_wa_wb; end +// 6'b001011 : begin data_collision_b_a <= 2'b00; display_wa_wb; end +// 6'b010011 : begin data_collision_b_a <= 2'b00; display_wa_wb; end + 6'b010111 : begin data_collision_b_a <= 2'b11; display_wa_wb; end +// 6'b011011 : begin data_collision_b_a <= 2'b00; display_wa_wb; end +// 6'b100011 : begin data_collision_b_a <= 2'b00; display_wa_wb; end + 6'b100111 : begin data_collision_b_a <= 2'b01; display_wa_wb; end +// 6'b101011 : begin data_collision_b_a <= 2'b00; display_wa_wb; end +// 6'b000001 : begin data_collision_b_a <= 2'b00; display_ra_wb; end + 6'b000101 : begin data_collision_b_a <= 2'b10; display_ra_wb; end +// 6'b001001 : begin data_collision_b_a <= 2'b00; display_ra_wb; end +// 6'b010001 : begin data_collision_b_a <= 2'b00; display_ra_wb; end + 6'b010101 : begin data_collision_b_a <= 2'b10; display_ra_wb; end +// 6'b011001 : begin data_collision_b_a <= 2'b00; display_ra_wb; end +// 6'b100001 : begin data_collision_b_a <= 2'b00; display_ra_wb; end + 6'b100101 : begin data_collision_b_a <= 2'b10; display_ra_wb; end +// 6'b101001 : begin data_collision_b_a <= 2'b00; display_ra_wb; end +// 6'b000010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end +// 6'b000110 : begin data_collision_b_a <= 2'b00; display_wa_rb; end +// 6'b001010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end +// 6'b010010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end +// 6'b010110 : begin data_collision_b_a <= 2'b00; display_wa_rb; end +// 6'b011010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end +// 6'b100010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end +// 6'b100110 : begin data_collision_b_a <= 2'b00; display_wa_rb; end +// 6'b101010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end + endcase + end + end + setup_rf_b_a <= 0; + end + + + always @(posedge clka_int) begin + addra_reg <= addra_int; + ena_reg <= ena_int; + ssra_reg <= ssra_int; + wea_reg <= wea_int; + end + + always @(posedge clkb_int) begin + addrb_reg <= addrb_int; + enb_reg <= enb_int; + ssrb_reg <= ssrb_int; + web_reg <= web_int; + end + + // Data + always @(posedge memory_collision) begin + for (dmi = 0; dmi < 1; dmi = dmi + 1) begin + mem[data_addra_int + dmi] <= 1'bX; + end + memory_collision <= 0; + end + + always @(posedge memory_collision_a_b) begin + for (dmi = 0; dmi < 1; dmi = dmi + 1) begin + mem[data_addra_reg + dmi] <= 1'bX; + end + memory_collision_a_b <= 0; + end + + always @(posedge memory_collision_b_a) begin + for (dmi = 0; dmi < 1; dmi = dmi + 1) begin + mem[data_addra_int + dmi] <= 1'bX; + end + memory_collision_b_a <= 0; + end + + always @(posedge data_collision[1]) begin + if (ssra_int == 0) begin + doa_out <= 1'bX; + end + data_collision[1] <= 0; + end + + always @(posedge data_collision[0]) begin + if (ssrb_int == 0) begin + for (dbi = 0; dbi < 1; dbi = dbi + 1) begin + dob_out[data_addra_int[3 : 0] + dbi] <= 1'bX; + end + end + data_collision[0] <= 0; + end + + always @(posedge data_collision_a_b[1]) begin + if (ssra_reg == 0) begin + doa_out <= 1'bX; + end + data_collision_a_b[1] <= 0; + end + + always @(posedge data_collision_a_b[0]) begin + if (ssrb_int == 0) begin + for (dbi = 0; dbi < 1; dbi = dbi + 1) begin + dob_out[data_addra_reg[3 : 0] + dbi] <= 1'bX; + end + end + data_collision_a_b[0] <= 0; + end + + always @(posedge data_collision_b_a[1]) begin + if (ssra_int == 0) begin + doa_out <= 1'bX; + end + data_collision_b_a[1] <= 0; + end + + always @(posedge data_collision_b_a[0]) begin + if (ssrb_reg == 0) begin + for (dbi = 0; dbi < 1; dbi = dbi + 1) begin + dob_out[data_addra_int[3 : 0] + dbi] <= 1'bX; + end + end + data_collision_b_a[0] <= 0; + end + + + initial begin + case (WRITE_MODE_A) + "WRITE_FIRST" : wr_mode_a <= 2'b00; + "READ_FIRST" : wr_mode_a <= 2'b01; + "NO_CHANGE" : wr_mode_a <= 2'b10; + default : begin + $display("Attribute Syntax Error : The Attribute WRITE_MODE_A on RAMB16_S1_S18 instance %m is set to %s. Legal values for this attribute are WRITE_FIRST, READ_FIRST or NO_CHANGE.", WRITE_MODE_A); + $finish; + end + endcase + end + + initial begin + case (WRITE_MODE_B) + "WRITE_FIRST" : wr_mode_b <= 2'b00; + "READ_FIRST" : wr_mode_b <= 2'b01; + "NO_CHANGE" : wr_mode_b <= 2'b10; + default : begin + $display("Attribute Syntax Error : The Attribute WRITE_MODE_B on RAMB16_S1_S18 instance %m is set to %s. Legal values for this attribute are WRITE_FIRST, READ_FIRST or NO_CHANGE.", WRITE_MODE_B); + $finish; + end + endcase + end + + // Port A + always @(posedge clka_int) begin + if (ena_int == 1'b1) begin + if (ssra_int == 1'b1) begin + doa_out[0] <= SRVAL_A[0]; + end + else begin + if (wea_int == 1'b1) begin + if (wr_mode_a == 2'b00) begin + doa_out <= dia_int; + end + else if (wr_mode_a == 2'b01) begin + doa_out[0] <= mem[data_addra_int + 0]; + end + end + else begin + doa_out[0] <= mem[data_addra_int + 0]; + end + end + end + end + + always @(posedge clka_int) begin + if (ena_int == 1'b1 && wea_int == 1'b1) begin + mem[data_addra_int + 0] <= dia_int[0]; + end + end + + // Port B + always @(posedge clkb_int) begin + if (enb_int == 1'b1) begin + if (ssrb_int == 1'b1) begin + dob_out[0] <= SRVAL_B[0]; + dob_out[1] <= SRVAL_B[1]; + dob_out[2] <= SRVAL_B[2]; + dob_out[3] <= SRVAL_B[3]; + dob_out[4] <= SRVAL_B[4]; + dob_out[5] <= SRVAL_B[5]; + dob_out[6] <= SRVAL_B[6]; + dob_out[7] <= SRVAL_B[7]; + dob_out[8] <= SRVAL_B[8]; + dob_out[9] <= SRVAL_B[9]; + dob_out[10] <= SRVAL_B[10]; + dob_out[11] <= SRVAL_B[11]; + dob_out[12] <= SRVAL_B[12]; + dob_out[13] <= SRVAL_B[13]; + dob_out[14] <= SRVAL_B[14]; + dob_out[15] <= SRVAL_B[15]; + dopb_out[0] <= SRVAL_B[16]; + dopb_out[1] <= SRVAL_B[17]; + end + else begin + if (web_int == 1'b1) begin + if (wr_mode_b == 2'b00) begin + dob_out <= dib_int; + dopb_out <= dipb_int; + end + else if (wr_mode_b == 2'b01) begin + dob_out[0] <= mem[data_addrb_int + 0]; + dob_out[1] <= mem[data_addrb_int + 1]; + dob_out[2] <= mem[data_addrb_int + 2]; + dob_out[3] <= mem[data_addrb_int + 3]; + dob_out[4] <= mem[data_addrb_int + 4]; + dob_out[5] <= mem[data_addrb_int + 5]; + dob_out[6] <= mem[data_addrb_int + 6]; + dob_out[7] <= mem[data_addrb_int + 7]; + dob_out[8] <= mem[data_addrb_int + 8]; + dob_out[9] <= mem[data_addrb_int + 9]; + dob_out[10] <= mem[data_addrb_int + 10]; + dob_out[11] <= mem[data_addrb_int + 11]; + dob_out[12] <= mem[data_addrb_int + 12]; + dob_out[13] <= mem[data_addrb_int + 13]; + dob_out[14] <= mem[data_addrb_int + 14]; + dob_out[15] <= mem[data_addrb_int + 15]; + dopb_out[0] <= mem[parity_addrb_int + 0]; + dopb_out[1] <= mem[parity_addrb_int + 1]; + end + end + else begin + dob_out[0] <= mem[data_addrb_int + 0]; + dob_out[1] <= mem[data_addrb_int + 1]; + dob_out[2] <= mem[data_addrb_int + 2]; + dob_out[3] <= mem[data_addrb_int + 3]; + dob_out[4] <= mem[data_addrb_int + 4]; + dob_out[5] <= mem[data_addrb_int + 5]; + dob_out[6] <= mem[data_addrb_int + 6]; + dob_out[7] <= mem[data_addrb_int + 7]; + dob_out[8] <= mem[data_addrb_int + 8]; + dob_out[9] <= mem[data_addrb_int + 9]; + dob_out[10] <= mem[data_addrb_int + 10]; + dob_out[11] <= mem[data_addrb_int + 11]; + dob_out[12] <= mem[data_addrb_int + 12]; + dob_out[13] <= mem[data_addrb_int + 13]; + dob_out[14] <= mem[data_addrb_int + 14]; + dob_out[15] <= mem[data_addrb_int + 15]; + dopb_out[0] <= mem[parity_addrb_int + 0]; + dopb_out[1] <= mem[parity_addrb_int + 1]; + end + end + end + end + + always @(posedge clkb_int) begin + if (enb_int == 1'b1 && web_int == 1'b1) begin + mem[data_addrb_int + 0] <= dib_int[0]; + mem[data_addrb_int + 1] <= dib_int[1]; + mem[data_addrb_int + 2] <= dib_int[2]; + mem[data_addrb_int + 3] <= dib_int[3]; + mem[data_addrb_int + 4] <= dib_int[4]; + mem[data_addrb_int + 5] <= dib_int[5]; + mem[data_addrb_int + 6] <= dib_int[6]; + mem[data_addrb_int + 7] <= dib_int[7]; + mem[data_addrb_int + 8] <= dib_int[8]; + mem[data_addrb_int + 9] <= dib_int[9]; + mem[data_addrb_int + 10] <= dib_int[10]; + mem[data_addrb_int + 11] <= dib_int[11]; + mem[data_addrb_int + 12] <= dib_int[12]; + mem[data_addrb_int + 13] <= dib_int[13]; + mem[data_addrb_int + 14] <= dib_int[14]; + mem[data_addrb_int + 15] <= dib_int[15]; + mem[parity_addrb_int + 0] <= dipb_int[0]; + mem[parity_addrb_int + 1] <= dipb_int[1]; + end + end + + specify + (CLKA *> DOA) = (100, 100); + (CLKB *> DOB) = (100, 100); + (CLKB *> DOPB) = (100, 100); + endspecify + +endmodule + +`else + +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/RAMB16_S1_S18.v,v 1.10 2007/02/22 01:58:05 wloo Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2005 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Timing Simulation Library Component +// / / 16K-Bit Data and 2K-Bit Parity Dual Port Block RAM +// /___/ /\ Filename : RAMB16_S1_S18.v +// \ \ / \ Timestamp : Thu Mar 10 16:44:01 PST 2005 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 03/10/05 - Initialized outputs. +// 02/21/07 - Fixed parameter SIM_COLLISION_CHECK (CR 433281). +// End Revision + +`timescale 1 ps/1 ps + +module RAMB16_S1_S18 (DOA, DOB, DOPB, ADDRA, ADDRB, CLKA, CLKB, DIA, DIB, DIPB, ENA, ENB, SSRA, SSRB, WEA, WEB); + + parameter INIT_A = 1'h0; + parameter INIT_B = 18'h0; + parameter SRVAL_A = 1'h0; + parameter SRVAL_B = 18'h0; + parameter WRITE_MODE_A = "WRITE_FIRST"; + parameter WRITE_MODE_B = "WRITE_FIRST"; + parameter SIM_COLLISION_CHECK = "ALL"; + localparam SETUP_ALL = 1000; + localparam SETUP_READ_FIRST = 3000; + + parameter INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + + output [0:0] DOA; + output [15:0] DOB; + output [1:0] DOPB; + + input [13:0] ADDRA; + input [0:0] DIA; + input ENA, CLKA, WEA, SSRA; + input [9:0] ADDRB; + input [15:0] DIB; + input [1:0] DIPB; + input ENB, CLKB, WEB, SSRB; + + reg [0:0] doa_out = INIT_A[0:0]; + reg [15:0] dob_out = INIT_B[15:0]; + reg [1:0] dopb_out = INIT_B[17:16]; + + reg [15:0] mem [1023:0]; + reg [1:0] memp [1023:0]; + + reg [8:0] count, countp; + reg [1:0] wr_mode_a, wr_mode_b; + + reg [5:0] dmi, dbi; + reg [5:0] pmi, pbi; + + wire [13:0] addra_int; + reg [13:0] addra_reg; + wire [0:0] dia_int; + wire ena_int, clka_int, wea_int, ssra_int; + reg ena_reg, wea_reg, ssra_reg; + wire [9:0] addrb_int; + reg [9:0] addrb_reg; + wire [15:0] dib_int; + wire [1:0] dipb_int; + wire enb_int, clkb_int, web_int, ssrb_int; + reg display_flag, output_flag; + reg enb_reg, web_reg, ssrb_reg; + + time time_clka, time_clkb; + time time_clka_clkb; + time time_clkb_clka; + + reg setup_all_a_b; + reg setup_all_b_a; + reg setup_zero; + reg setup_rf_a_b; + reg setup_rf_b_a; + reg [1:0] data_collision, data_collision_a_b, data_collision_b_a; + reg memory_collision, memory_collision_a_b, memory_collision_b_a; + reg change_clka; + reg change_clkb; + + wire [14:0] data_addra_int; + wire [14:0] data_addra_reg; + wire [14:0] data_addrb_int; + wire [14:0] data_addrb_reg; + + wire dia_enable = ena_int && wea_int; + wire dib_enable = enb_int && web_int; + + tri0 GSR = glbl.GSR; + wire gsr_int; + + buf b_gsr (gsr_int, GSR); + + buf b_doa [0:0] (DOA, doa_out); + buf b_addra [13:0] (addra_int, ADDRA); + buf b_dia [0:0] (dia_int, DIA); + buf b_ena (ena_int, ENA); + buf b_clka (clka_int, CLKA); + buf b_ssra (ssra_int, SSRA); + buf b_wea (wea_int, WEA); + + buf b_dob [15:0] (DOB, dob_out); + buf b_dopb [1:0] (DOPB, dopb_out); + buf b_addrb [9:0] (addrb_int, ADDRB); + buf b_dib [15:0] (dib_int, DIB); + buf b_dipb [1:0] (dipb_int, DIPB); + buf b_enb (enb_int, ENB); + buf b_clkb (clkb_int, CLKB); + buf b_ssrb (ssrb_int, SSRB); + buf b_web (web_int, WEB); + + + always @(gsr_int) + if (gsr_int) begin + assign {doa_out} = INIT_A; + assign {dopb_out, dob_out} = INIT_B; + end + else begin + deassign doa_out; + deassign dob_out; + deassign dopb_out; + end + + + initial begin + + for (count = 0; count < 16; count = count + 1) begin + mem[count] = INIT_00[(count * 16) +: 16]; + mem[16 * 1 + count] = INIT_01[(count * 16) +: 16]; + mem[16 * 2 + count] = INIT_02[(count * 16) +: 16]; + mem[16 * 3 + count] = INIT_03[(count * 16) +: 16]; + mem[16 * 4 + count] = INIT_04[(count * 16) +: 16]; + mem[16 * 5 + count] = INIT_05[(count * 16) +: 16]; + mem[16 * 6 + count] = INIT_06[(count * 16) +: 16]; + mem[16 * 7 + count] = INIT_07[(count * 16) +: 16]; + mem[16 * 8 + count] = INIT_08[(count * 16) +: 16]; + mem[16 * 9 + count] = INIT_09[(count * 16) +: 16]; + mem[16 * 10 + count] = INIT_0A[(count * 16) +: 16]; + mem[16 * 11 + count] = INIT_0B[(count * 16) +: 16]; + mem[16 * 12 + count] = INIT_0C[(count * 16) +: 16]; + mem[16 * 13 + count] = INIT_0D[(count * 16) +: 16]; + mem[16 * 14 + count] = INIT_0E[(count * 16) +: 16]; + mem[16 * 15 + count] = INIT_0F[(count * 16) +: 16]; + mem[16 * 16 + count] = INIT_10[(count * 16) +: 16]; + mem[16 * 17 + count] = INIT_11[(count * 16) +: 16]; + mem[16 * 18 + count] = INIT_12[(count * 16) +: 16]; + mem[16 * 19 + count] = INIT_13[(count * 16) +: 16]; + mem[16 * 20 + count] = INIT_14[(count * 16) +: 16]; + mem[16 * 21 + count] = INIT_15[(count * 16) +: 16]; + mem[16 * 22 + count] = INIT_16[(count * 16) +: 16]; + mem[16 * 23 + count] = INIT_17[(count * 16) +: 16]; + mem[16 * 24 + count] = INIT_18[(count * 16) +: 16]; + mem[16 * 25 + count] = INIT_19[(count * 16) +: 16]; + mem[16 * 26 + count] = INIT_1A[(count * 16) +: 16]; + mem[16 * 27 + count] = INIT_1B[(count * 16) +: 16]; + mem[16 * 28 + count] = INIT_1C[(count * 16) +: 16]; + mem[16 * 29 + count] = INIT_1D[(count * 16) +: 16]; + mem[16 * 30 + count] = INIT_1E[(count * 16) +: 16]; + mem[16 * 31 + count] = INIT_1F[(count * 16) +: 16]; + mem[16 * 32 + count] = INIT_20[(count * 16) +: 16]; + mem[16 * 33 + count] = INIT_21[(count * 16) +: 16]; + mem[16 * 34 + count] = INIT_22[(count * 16) +: 16]; + mem[16 * 35 + count] = INIT_23[(count * 16) +: 16]; + mem[16 * 36 + count] = INIT_24[(count * 16) +: 16]; + mem[16 * 37 + count] = INIT_25[(count * 16) +: 16]; + mem[16 * 38 + count] = INIT_26[(count * 16) +: 16]; + mem[16 * 39 + count] = INIT_27[(count * 16) +: 16]; + mem[16 * 40 + count] = INIT_28[(count * 16) +: 16]; + mem[16 * 41 + count] = INIT_29[(count * 16) +: 16]; + mem[16 * 42 + count] = INIT_2A[(count * 16) +: 16]; + mem[16 * 43 + count] = INIT_2B[(count * 16) +: 16]; + mem[16 * 44 + count] = INIT_2C[(count * 16) +: 16]; + mem[16 * 45 + count] = INIT_2D[(count * 16) +: 16]; + mem[16 * 46 + count] = INIT_2E[(count * 16) +: 16]; + mem[16 * 47 + count] = INIT_2F[(count * 16) +: 16]; + mem[16 * 48 + count] = INIT_30[(count * 16) +: 16]; + mem[16 * 49 + count] = INIT_31[(count * 16) +: 16]; + mem[16 * 50 + count] = INIT_32[(count * 16) +: 16]; + mem[16 * 51 + count] = INIT_33[(count * 16) +: 16]; + mem[16 * 52 + count] = INIT_34[(count * 16) +: 16]; + mem[16 * 53 + count] = INIT_35[(count * 16) +: 16]; + mem[16 * 54 + count] = INIT_36[(count * 16) +: 16]; + mem[16 * 55 + count] = INIT_37[(count * 16) +: 16]; + mem[16 * 56 + count] = INIT_38[(count * 16) +: 16]; + mem[16 * 57 + count] = INIT_39[(count * 16) +: 16]; + mem[16 * 58 + count] = INIT_3A[(count * 16) +: 16]; + mem[16 * 59 + count] = INIT_3B[(count * 16) +: 16]; + mem[16 * 60 + count] = INIT_3C[(count * 16) +: 16]; + mem[16 * 61 + count] = INIT_3D[(count * 16) +: 16]; + mem[16 * 62 + count] = INIT_3E[(count * 16) +: 16]; + mem[16 * 63 + count] = INIT_3F[(count * 16) +: 16]; + end + +// initiate parity start + for (countp = 0; countp < 128; countp = countp + 1) begin + memp[countp] = INITP_00[(countp * 2) +: 2]; + memp[128 * 1 + countp] = INITP_01[(countp * 2) +: 2]; + memp[128 * 2 + countp] = INITP_02[(countp * 2) +: 2]; + memp[128 * 3 + countp] = INITP_03[(countp * 2) +: 2]; + memp[128 * 4 + countp] = INITP_04[(countp * 2) +: 2]; + memp[128 * 5 + countp] = INITP_05[(countp * 2) +: 2]; + memp[128 * 6 + countp] = INITP_06[(countp * 2) +: 2]; + memp[128 * 7 + countp] = INITP_07[(countp * 2) +: 2]; + end +// initiate parity end + + change_clka <= 0; + change_clkb <= 0; + data_collision <= 0; + data_collision_a_b <= 0; + data_collision_b_a <= 0; + memory_collision <= 0; + memory_collision_a_b <= 0; + memory_collision_b_a <= 0; + setup_all_a_b <= 0; + setup_all_b_a <= 0; + setup_zero <= 0; + setup_rf_a_b <= 0; + setup_rf_b_a <= 0; + end + + assign data_addra_int = addra_int * 1; + assign data_addra_reg = addra_reg * 1; + assign data_addrb_int = addrb_int * 16; + assign data_addrb_reg = addrb_reg * 16; + + + initial begin + + display_flag = 1; + output_flag = 1; + + case (SIM_COLLISION_CHECK) + + "NONE" : begin + output_flag = 0; + display_flag = 0; + end + "WARNING_ONLY" : output_flag = 0; + "GENERATE_X_ONLY" : display_flag = 0; + "ALL" : ; + + default : begin + $display("Attribute Syntax Error : The Attribute SIM_COLLISION_CHECK on RAMB16_S1_S18 instance %m is set to %s. Legal values for this attribute are ALL, NONE, WARNING_ONLY or GENERATE_X_ONLY.", SIM_COLLISION_CHECK); + $finish; + end + + endcase // case(SIM_COLLISION_CHECK) + + end // initial begin + + + always @(posedge clka_int) begin + if ((output_flag || display_flag)) begin + time_clka = $time; + #0 time_clkb_clka = time_clka - time_clkb; + change_clka = ~change_clka; + end + end + + always @(posedge clkb_int) begin + if ((output_flag || display_flag)) begin + time_clkb = $time; + #0 time_clka_clkb = time_clkb - time_clka; + change_clkb = ~change_clkb; + end + end + + always @(change_clkb) begin + if ((0 < time_clka_clkb) && (time_clka_clkb < SETUP_ALL)) + setup_all_a_b = 1; + if ((0 < time_clka_clkb) && (time_clka_clkb < SETUP_READ_FIRST)) + setup_rf_a_b = 1; + end + + always @(change_clka) begin + if ((0 < time_clkb_clka) && (time_clkb_clka < SETUP_ALL)) + setup_all_b_a = 1; + if ((0 < time_clkb_clka) && (time_clkb_clka < SETUP_READ_FIRST)) + setup_rf_b_a = 1; + end + + always @(change_clkb or change_clka) begin + if ((time_clkb_clka == 0) && (time_clka_clkb == 0)) + setup_zero = 1; + end + + always @(posedge setup_zero) begin + if ((ena_int == 1) && (wea_int == 1) && + (enb_int == 1) && (web_int == 1) && + (data_addra_int[14:4] == data_addrb_int[14:4])) + memory_collision <= 1; + end + + always @(posedge setup_all_a_b or posedge setup_rf_a_b) begin + if ((ena_reg == 1) && (wea_reg == 1) && + (enb_int == 1) && (web_int == 1) && + (data_addra_reg[14:4] == data_addrb_int[14:4])) + memory_collision_a_b <= 1; + end + + always @(posedge setup_all_b_a or posedge setup_rf_b_a) begin + if ((ena_int == 1) && (wea_int == 1) && + (enb_reg == 1) && (web_reg == 1) && + (data_addra_int[14:4] == data_addrb_reg[14:4])) + memory_collision_b_a <= 1; + end + + always @(posedge setup_all_a_b) begin + if (data_addra_reg[14:4] == data_addrb_int[14:4]) begin + if ((ena_reg == 1) && (enb_int == 1)) begin + case ({wr_mode_a, wr_mode_b, wea_reg, web_int}) + 6'b000011 : begin data_collision_a_b <= 2'b11; display_wa_wb; end + 6'b000111 : begin data_collision_a_b <= 2'b11; display_wa_wb; end + 6'b001011 : begin data_collision_a_b <= 2'b10; display_wa_wb; end +// 6'b010011 : begin data_collision_a_b <= 2'b00; display_wa_wb; end +// 6'b010111 : begin data_collision_a_b <= 2'b00; display_wa_wb; end +// 6'b011011 : begin data_collision_a_b <= 2'b00; display_wa_wb; end + 6'b100011 : begin data_collision_a_b <= 2'b01; display_wa_wb; end + 6'b100111 : begin data_collision_a_b <= 2'b01; display_wa_wb; end + 6'b101011 : begin display_wa_wb; end + 6'b000001 : begin data_collision_a_b <= 2'b10; display_ra_wb; end +// 6'b000101 : begin data_collision_a_b <= 2'b00; display_ra_wb; end + 6'b001001 : begin data_collision_a_b <= 2'b10; display_ra_wb; end + 6'b010001 : begin data_collision_a_b <= 2'b10; display_ra_wb; end +// 6'b010101 : begin data_collision_a_b <= 2'b00; display_ra_wb; end + 6'b011001 : begin data_collision_a_b <= 2'b10; display_ra_wb; end + 6'b100001 : begin data_collision_a_b <= 2'b10; display_ra_wb; end +// 6'b100101 : begin data_collision_a_b <= 2'b00; display_ra_wb; end + 6'b101001 : begin data_collision_a_b <= 2'b10; display_ra_wb; end + 6'b000010 : begin data_collision_a_b <= 2'b01; display_wa_rb; end + 6'b000110 : begin data_collision_a_b <= 2'b01; display_wa_rb; end + 6'b001010 : begin data_collision_a_b <= 2'b01; display_wa_rb; end +// 6'b010010 : begin data_collision_a_b <= 2'b00; display_wa_rb; end +// 6'b010110 : begin data_collision_a_b <= 2'b00; display_wa_rb; end +// 6'b011010 : begin data_collision_a_b <= 2'b00; display_wa_rb; end + 6'b100010 : begin data_collision_a_b <= 2'b01; display_wa_rb; end + 6'b100110 : begin data_collision_a_b <= 2'b01; display_wa_rb; end + 6'b101010 : begin data_collision_a_b <= 2'b01; display_wa_rb; end + endcase + end + end + setup_all_a_b <= 0; + end + + + always @(posedge setup_all_b_a) begin + if (data_addra_int[14:4] == data_addrb_reg[14:4]) begin + if ((ena_int == 1) && (enb_reg == 1)) begin + case ({wr_mode_a, wr_mode_b, wea_int, web_reg}) + 6'b000011 : begin data_collision_b_a <= 2'b11; display_wa_wb; end +// 6'b000111 : begin data_collision_b_a <= 2'b00; display_wa_wb; end + 6'b001011 : begin data_collision_b_a <= 2'b10; display_wa_wb; end + 6'b010011 : begin data_collision_b_a <= 2'b11; display_wa_wb; end +// 6'b010111 : begin data_collision_b_a <= 2'b00; display_wa_wb; end + 6'b011011 : begin data_collision_b_a <= 2'b10; display_wa_wb; end + 6'b100011 : begin data_collision_b_a <= 2'b01; display_wa_wb; end + 6'b100111 : begin data_collision_b_a <= 2'b01; display_wa_wb; end + 6'b101011 : begin display_wa_wb; end + 6'b000001 : begin data_collision_b_a <= 2'b10; display_ra_wb; end + 6'b000101 : begin data_collision_b_a <= 2'b10; display_ra_wb; end + 6'b001001 : begin data_collision_b_a <= 2'b10; display_ra_wb; end + 6'b010001 : begin data_collision_b_a <= 2'b10; display_ra_wb; end + 6'b010101 : begin data_collision_b_a <= 2'b10; display_ra_wb; end + 6'b011001 : begin data_collision_b_a <= 2'b10; display_ra_wb; end + 6'b100001 : begin data_collision_b_a <= 2'b10; display_ra_wb; end + 6'b100101 : begin data_collision_b_a <= 2'b10; display_ra_wb; end + 6'b101001 : begin data_collision_b_a <= 2'b10; display_ra_wb; end + 6'b000010 : begin data_collision_b_a <= 2'b01; display_wa_rb; end + 6'b000110 : begin data_collision_b_a <= 2'b01; display_wa_rb; end + 6'b001010 : begin data_collision_b_a <= 2'b01; display_wa_rb; end +// 6'b010010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end +// 6'b010110 : begin data_collision_b_a <= 2'b00; display_wa_rb; end +// 6'b011010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end + 6'b100010 : begin data_collision_b_a <= 2'b01; display_wa_rb; end + 6'b100110 : begin data_collision_b_a <= 2'b01; display_wa_rb; end + 6'b101010 : begin data_collision_b_a <= 2'b01; display_wa_rb; end + endcase + end + end + setup_all_b_a <= 0; + end + + + always @(posedge setup_zero) begin + if (data_addra_int[14:4] == data_addrb_int[14:4]) begin + if ((ena_int == 1) && (enb_int == 1)) begin + case ({wr_mode_a, wr_mode_b, wea_int, web_int}) + 6'b000011 : begin data_collision <= 2'b11; display_wa_wb; end + 6'b000111 : begin data_collision <= 2'b11; display_wa_wb; end + 6'b001011 : begin data_collision <= 2'b10; display_wa_wb; end + 6'b010011 : begin data_collision <= 2'b11; display_wa_wb; end + 6'b010111 : begin data_collision <= 2'b11; display_wa_wb; end + 6'b011011 : begin data_collision <= 2'b10; display_wa_wb; end + 6'b100011 : begin data_collision <= 2'b01; display_wa_wb; end + 6'b100111 : begin data_collision <= 2'b01; display_wa_wb; end + 6'b101011 : begin display_wa_wb; end + 6'b000001 : begin data_collision <= 2'b10; display_ra_wb; end +// 6'b000101 : begin data_collision <= 2'b00; display_ra_wb; end + 6'b001001 : begin data_collision <= 2'b10; display_ra_wb; end + 6'b010001 : begin data_collision <= 2'b10; display_ra_wb; end +// 6'b010101 : begin data_collision <= 2'b00; display_ra_wb; end + 6'b011001 : begin data_collision <= 2'b10; display_ra_wb; end + 6'b100001 : begin data_collision <= 2'b10; display_ra_wb; end +// 6'b100101 : begin data_collision <= 2'b00; display_ra_wb; end + 6'b101001 : begin data_collision <= 2'b10; display_ra_wb; end + 6'b000010 : begin data_collision <= 2'b01; display_wa_rb; end + 6'b000110 : begin data_collision <= 2'b01; display_wa_rb; end + 6'b001010 : begin data_collision <= 2'b01; display_wa_rb; end +// 6'b010010 : begin data_collision <= 2'b00; display_wa_rb; end +// 6'b010110 : begin data_collision <= 2'b00; display_wa_rb; end +// 6'b011010 : begin data_collision <= 2'b00; display_wa_rb; end + 6'b100010 : begin data_collision <= 2'b01; display_wa_rb; end + 6'b100110 : begin data_collision <= 2'b01; display_wa_rb; end + 6'b101010 : begin data_collision <= 2'b01; display_wa_rb; end + endcase + end + end + setup_zero <= 0; + end + + task display_ra_wb; + begin + if (display_flag) + $display("Memory Collision Error on RAMB16_S1_S18:%m at simulation time %.3f ns\nA read was performed on address %h (hex) of Port A while a write was requested to the same address on Port B. The write will be successful however the read value on Port A is unknown until the next CLKA cycle.", $time/1000.0, addra_int); + end + endtask + + task display_wa_rb; + begin + if (display_flag) + $display("Memory Collision Error on RAMB16_S1_S18:%m at simulation time %.3f ns\nA read was performed on address %h (hex) of Port B while a write was requested to the same address on Port A. The write will be successful however the read value on Port B is unknown until the next CLKB cycle.", $time/1000.0, addrb_int); + end + endtask + + task display_wa_wb; + begin + if (display_flag) + $display("Memory Collision Error on RAMB16_S1_S18:%m at simulation time %.3f ns\nA write was requested to the same address simultaneously at both Port A and Port B of the RAM. The contents written to the RAM at address location %h (hex) of Port A and address location %h (hex) of Port B are unknown.", $time/1000.0, addra_int, addrb_int); + end + endtask + + + always @(posedge setup_rf_a_b) begin + if (data_addra_reg[14:4] == data_addrb_int[14:4]) begin + if ((ena_reg == 1) && (enb_int == 1)) begin + case ({wr_mode_a, wr_mode_b, wea_reg, web_int}) +// 6'b000011 : begin data_collision_a_b <= 2'b00; display_wa_wb; end +// 6'b000111 : begin data_collision_a_b <= 2'b00; display_wa_wb; end +// 6'b001011 : begin data_collision_a_b <= 2'b00; display_wa_wb; end + 6'b010011 : begin data_collision_a_b <= 2'b11; display_wa_wb; end + 6'b010111 : begin data_collision_a_b <= 2'b11; display_wa_wb; end + 6'b011011 : begin data_collision_a_b <= 2'b10; display_wa_wb; end +// 6'b100011 : begin data_collision_a_b <= 2'b00; display_wa_wb; end +// 6'b100111 : begin data_collision_a_b <= 2'b00; display_wa_wb; end +// 6'b101011 : begin data_collision_a_b <= 2'b00; display_wa_wb; end +// 6'b000001 : begin data_collision_a_b <= 2'b00; display_ra_wb; end +// 6'b000101 : begin data_collision_a_b <= 2'b00; display_ra_wb; end +// 6'b001001 : begin data_collision_a_b <= 2'b00; display_ra_wb; end +// 6'b010001 : begin data_collision_a_b <= 2'b00; display_ra_wb; end +// 6'b010101 : begin data_collision_a_b <= 2'b00; display_ra_wb; end +// 6'b011001 : begin data_collision_a_b <= 2'b00; display_ra_wb; end +// 6'b100001 : begin data_collision_a_b <= 2'b00; display_ra_wb; end +// 6'b100101 : begin data_collision_a_b <= 2'b00; display_ra_wb; end +// 6'b101001 : begin data_collision_a_b <= 2'b00; display_ra_wb; end +// 6'b000010 : begin data_collision_a_b <= 2'b00; display_wa_rb; end +// 6'b000110 : begin data_collision_a_b <= 2'b00; display_wa_rb; end +// 6'b001010 : begin data_collision_a_b <= 2'b00; display_wa_rb; end + 6'b010010 : begin data_collision_a_b <= 2'b01; display_wa_rb; end + 6'b010110 : begin data_collision_a_b <= 2'b01; display_wa_rb; end + 6'b011010 : begin data_collision_a_b <= 2'b01; display_wa_rb; end +// 6'b100010 : begin data_collision_a_b <= 2'b00; display_wa_rb; end +// 6'b100110 : begin data_collision_a_b <= 2'b00; display_wa_rb; end +// 6'b101010 : begin data_collision_a_b <= 2'b00; display_wa_rb; end + endcase + end + end + setup_rf_a_b <= 0; + end + + + always @(posedge setup_rf_b_a) begin + if (data_addra_int[14:4] == data_addrb_reg[14:4]) begin + if ((ena_int == 1) && (enb_reg == 1)) begin + case ({wr_mode_a, wr_mode_b, wea_int, web_reg}) +// 6'b000011 : begin data_collision_b_a <= 2'b00; display_wa_wb; end + 6'b000111 : begin data_collision_b_a <= 2'b11; display_wa_wb; end +// 6'b001011 : begin data_collision_b_a <= 2'b00; display_wa_wb; end +// 6'b010011 : begin data_collision_b_a <= 2'b00; display_wa_wb; end + 6'b010111 : begin data_collision_b_a <= 2'b11; display_wa_wb; end +// 6'b011011 : begin data_collision_b_a <= 2'b00; display_wa_wb; end +// 6'b100011 : begin data_collision_b_a <= 2'b00; display_wa_wb; end + 6'b100111 : begin data_collision_b_a <= 2'b01; display_wa_wb; end +// 6'b101011 : begin data_collision_b_a <= 2'b00; display_wa_wb; end +// 6'b000001 : begin data_collision_b_a <= 2'b00; display_ra_wb; end + 6'b000101 : begin data_collision_b_a <= 2'b10; display_ra_wb; end +// 6'b001001 : begin data_collision_b_a <= 2'b00; display_ra_wb; end +// 6'b010001 : begin data_collision_b_a <= 2'b00; display_ra_wb; end + 6'b010101 : begin data_collision_b_a <= 2'b10; display_ra_wb; end +// 6'b011001 : begin data_collision_b_a <= 2'b00; display_ra_wb; end +// 6'b100001 : begin data_collision_b_a <= 2'b00; display_ra_wb; end + 6'b100101 : begin data_collision_b_a <= 2'b10; display_ra_wb; end +// 6'b101001 : begin data_collision_b_a <= 2'b00; display_ra_wb; end +// 6'b000010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end +// 6'b000110 : begin data_collision_b_a <= 2'b00; display_wa_rb; end +// 6'b001010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end +// 6'b010010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end +// 6'b010110 : begin data_collision_b_a <= 2'b00; display_wa_rb; end +// 6'b011010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end +// 6'b100010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end +// 6'b100110 : begin data_collision_b_a <= 2'b00; display_wa_rb; end +// 6'b101010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end + endcase + end + end + setup_rf_b_a <= 0; + end + + + always @(posedge clka_int) begin + if ((output_flag || display_flag)) begin + addra_reg <= addra_int; + ena_reg <= ena_int; + ssra_reg <= ssra_int; + wea_reg <= wea_int; + end + end + + always @(posedge clkb_int) begin + if ((output_flag || display_flag)) begin + addrb_reg <= addrb_int; + enb_reg <= enb_int; + ssrb_reg <= ssrb_int; + web_reg <= web_int; + end + end + + + // Data + always @(posedge memory_collision) begin + if ((output_flag || display_flag)) begin + mem[addra_int[13:4]][addra_int[3:0] * 1 +: 1] <= 1'bx; + memory_collision <= 0; + end + + end + + always @(posedge memory_collision_a_b) begin + if ((output_flag || display_flag)) begin + mem[addra_reg[13:4]][addra_reg[3:0] * 1 +: 1] <= 1'bx; + memory_collision_a_b <= 0; + end + end + + always @(posedge memory_collision_b_a) begin + if ((output_flag || display_flag)) begin + mem[addra_int[13:4]][addra_int[3:0] * 1 +: 1] <= 1'bx; + memory_collision_b_a <= 0; + end + end + + always @(posedge data_collision[1]) begin + if (ssra_int == 0 && output_flag) begin + doa_out <= #100 1'bX; + end + data_collision[1] <= 0; + end + + always @(posedge data_collision[0]) begin + if (ssrb_int == 0 && output_flag) begin + dob_out[addra_int[3:0] * 1 +: 1] <= #100 1'bX; + end + data_collision[0] <= 0; + end + + always @(posedge data_collision_a_b[1]) begin + if (ssra_reg == 0 && output_flag) begin + doa_out <= #100 1'bX; + end + data_collision_a_b[1] <= 0; + end + + always @(posedge data_collision_a_b[0]) begin + if (ssrb_int == 0 && output_flag) begin + dob_out[addra_reg[3:0] * 1 +: 1] <= #100 1'bX; + end + data_collision_a_b[0] <= 0; + end + + always @(posedge data_collision_b_a[1]) begin + if (ssra_int == 0 && output_flag) begin + doa_out <= #100 1'bX; + end + data_collision_b_a[1] <= 0; + end + + always @(posedge data_collision_b_a[0]) begin + if (ssrb_reg == 0 && output_flag) begin + dob_out[addra_int[3:0] * 1 +: 1] <= #100 1'bX; + end + data_collision_b_a[0] <= 0; + end + + + initial begin + case (WRITE_MODE_A) + "WRITE_FIRST" : wr_mode_a <= 2'b00; + "READ_FIRST" : wr_mode_a <= 2'b01; + "NO_CHANGE" : wr_mode_a <= 2'b10; + default : begin + $display("Attribute Syntax Error : The Attribute WRITE_MODE_A on RAMB16_S1_S18 instance %m is set to %s. Legal values for this attribute are WRITE_FIRST, READ_FIRST or NO_CHANGE.", WRITE_MODE_A); + $finish; + end + endcase + end + + initial begin + case (WRITE_MODE_B) + "WRITE_FIRST" : wr_mode_b <= 2'b00; + "READ_FIRST" : wr_mode_b <= 2'b01; + "NO_CHANGE" : wr_mode_b <= 2'b10; + default : begin + $display("Attribute Syntax Error : The Attribute WRITE_MODE_B on RAMB16_S1_S18 instance %m is set to %s. Legal values for this attribute are WRITE_FIRST, READ_FIRST or NO_CHANGE.", WRITE_MODE_B); + $finish; + end + endcase + end + + + // Port A + always @(posedge clka_int) begin + + if (ena_int == 1'b1) begin + + if (ssra_int == 1'b1) begin + {doa_out} <= #100 SRVAL_A; + end + else begin + if (wea_int == 1'b1) begin + if (wr_mode_a == 2'b00) begin + doa_out <= #100 dia_int; + end + else if (wr_mode_a == 2'b01) begin + + doa_out <= #100 mem[addra_int[13:4]][addra_int[3:0] * 1 +: 1]; + + end + end + else begin + + doa_out <= #100 mem[addra_int[13:4]][addra_int[3:0] * 1 +: 1]; + + end + end + + // memory + if (wea_int == 1'b1) begin + mem[addra_int[13:4]][addra_int[3:0] * 1 +: 1] <= dia_int; + end + + end + end + + + // Port B + always @(posedge clkb_int) begin + + if (enb_int == 1'b1) begin + + if (ssrb_int == 1'b1) begin + {dopb_out, dob_out} <= #100 SRVAL_B; + end + else begin + if (web_int == 1'b1) begin + if (wr_mode_b == 2'b00) begin + dob_out <= #100 dib_int; + dopb_out <= #100 dipb_int; + end + else if (wr_mode_b == 2'b01) begin + dob_out <= #100 mem[addrb_int]; + dopb_out <= #100 memp[addrb_int]; + end + end + else begin + dob_out <= #100 mem[addrb_int]; + dopb_out <= #100 memp[addrb_int]; + end + end + + // memory + if (web_int == 1'b1) begin + mem[addrb_int] <= dib_int; + memp[addrb_int] <= dipb_int; + end + + end + end + + +endmodule + +`endif diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/RAMB16_S1_S2.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/RAMB16_S1_S2.v new file mode 100644 index 0000000..6624566 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/RAMB16_S1_S2.v @@ -0,0 +1,1536 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/RAMB16_S1_S2.v,v 1.11 2007/02/22 01:58:05 wloo Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2005 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / 16K-Bit Data and 2K-Bit Parity Dual Port Block RAM +// /___/ /\ Filename : RAMB16_S1_S2.v +// \ \ / \ Timestamp : Thu Mar 10 16:43:35 PST 2005 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// End Revision + +`ifdef legacy_model + +`timescale 1 ps / 1 ps + +module RAMB16_S1_S2 (DOA, DOB, ADDRA, ADDRB, CLKA, CLKB, DIA, DIB, ENA, ENB, SSRA, SSRB, WEA, WEB); + + parameter INIT_A = 1'h0; + parameter INIT_B = 2'h0; + parameter SRVAL_A = 1'h0; + parameter SRVAL_B = 2'h0; + parameter WRITE_MODE_A = "WRITE_FIRST"; + parameter WRITE_MODE_B = "WRITE_FIRST"; + parameter SIM_COLLISION_CHECK = "ALL"; + localparam SETUP_ALL = 1000; + localparam SETUP_READ_FIRST = 3000; + + parameter INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + + output [0:0] DOA; + reg [0:0] doa_out; + wire doa_out0; + + input [13:0] ADDRA; + input [0:0] DIA; + input ENA, CLKA, WEA, SSRA; + + output [1:0] DOB; + reg [1:0] dob_out; + wire dob_out0, dob_out1; + + input [12:0] ADDRB; + input [1:0] DIB; + input ENB, CLKB, WEB, SSRB; + + reg [18431:0] mem; + reg [8:0] count; + reg [1:0] wr_mode_a, wr_mode_b; + + reg [5:0] dmi, dbi; + reg [5:0] pmi, pbi; + + wire [13:0] addra_int; + reg [13:0] addra_reg; + wire [0:0] dia_int; + wire ena_int, clka_int, wea_int, ssra_int; + reg ena_reg, wea_reg, ssra_reg; + wire [12:0] addrb_int; + reg [12:0] addrb_reg; + wire [1:0] dib_int; + wire enb_int, clkb_int, web_int, ssrb_int; + reg display_flag; + reg enb_reg, web_reg, ssrb_reg; + + time time_clka, time_clkb; + time time_clka_clkb; + time time_clkb_clka; + + reg setup_all_a_b; + reg setup_all_b_a; + reg setup_zero; + reg setup_rf_a_b; + reg setup_rf_b_a; + reg [1:0] data_collision, data_collision_a_b, data_collision_b_a; + reg memory_collision, memory_collision_a_b, memory_collision_b_a; + reg address_collision, address_collision_a_b, address_collision_b_a; + reg change_clka; + reg change_clkb; + + wire [14:0] data_addra_int; + wire [14:0] data_addra_reg; + wire [14:0] data_addrb_int; + wire [14:0] data_addrb_reg; + wire [15:0] parity_addra_int; + wire [15:0] parity_addra_reg; + wire [15:0] parity_addrb_int; + wire [15:0] parity_addrb_reg; + + tri0 GSR = glbl.GSR; + + always @(GSR) + if (GSR) begin + assign doa_out = INIT_A[0:0]; + assign dob_out = INIT_B[1:0]; + end + else begin + deassign doa_out; + deassign dob_out; + end + + buf b_doa_out0 (doa_out0, doa_out[0]); + buf b_dob_out0 (dob_out0, dob_out[0]); + buf b_dob_out1 (dob_out1, dob_out[1]); + + buf b_doa0 (DOA[0], doa_out0); + buf b_dob0 (DOB[0], dob_out0); + buf b_dob1 (DOB[1], dob_out1); + + buf b_addra_0 (addra_int[0], ADDRA[0]); + buf b_addra_1 (addra_int[1], ADDRA[1]); + buf b_addra_2 (addra_int[2], ADDRA[2]); + buf b_addra_3 (addra_int[3], ADDRA[3]); + buf b_addra_4 (addra_int[4], ADDRA[4]); + buf b_addra_5 (addra_int[5], ADDRA[5]); + buf b_addra_6 (addra_int[6], ADDRA[6]); + buf b_addra_7 (addra_int[7], ADDRA[7]); + buf b_addra_8 (addra_int[8], ADDRA[8]); + buf b_addra_9 (addra_int[9], ADDRA[9]); + buf b_addra_10 (addra_int[10], ADDRA[10]); + buf b_addra_11 (addra_int[11], ADDRA[11]); + buf b_addra_12 (addra_int[12], ADDRA[12]); + buf b_addra_13 (addra_int[13], ADDRA[13]); + buf b_dia_0 (dia_int[0], DIA[0]); + buf b_ena (ena_int, ENA); + buf b_clka (clka_int, CLKA); + buf b_ssra (ssra_int, SSRA); + buf b_wea (wea_int, WEA); + buf b_addrb_0 (addrb_int[0], ADDRB[0]); + buf b_addrb_1 (addrb_int[1], ADDRB[1]); + buf b_addrb_2 (addrb_int[2], ADDRB[2]); + buf b_addrb_3 (addrb_int[3], ADDRB[3]); + buf b_addrb_4 (addrb_int[4], ADDRB[4]); + buf b_addrb_5 (addrb_int[5], ADDRB[5]); + buf b_addrb_6 (addrb_int[6], ADDRB[6]); + buf b_addrb_7 (addrb_int[7], ADDRB[7]); + buf b_addrb_8 (addrb_int[8], ADDRB[8]); + buf b_addrb_9 (addrb_int[9], ADDRB[9]); + buf b_addrb_10 (addrb_int[10], ADDRB[10]); + buf b_addrb_11 (addrb_int[11], ADDRB[11]); + buf b_addrb_12 (addrb_int[12], ADDRB[12]); + buf b_dib_0 (dib_int[0], DIB[0]); + buf b_dib_1 (dib_int[1], DIB[1]); + buf b_enb (enb_int, ENB); + buf b_clkb (clkb_int, CLKB); + buf b_ssrb (ssrb_int, SSRB); + buf b_web (web_int, WEB); + + initial begin + for (count = 0; count < 256; count = count + 1) begin + mem[count] <= INIT_00[count]; + mem[256 * 1 + count] <= INIT_01[count]; + mem[256 * 2 + count] <= INIT_02[count]; + mem[256 * 3 + count] <= INIT_03[count]; + mem[256 * 4 + count] <= INIT_04[count]; + mem[256 * 5 + count] <= INIT_05[count]; + mem[256 * 6 + count] <= INIT_06[count]; + mem[256 * 7 + count] <= INIT_07[count]; + mem[256 * 8 + count] <= INIT_08[count]; + mem[256 * 9 + count] <= INIT_09[count]; + mem[256 * 10 + count] <= INIT_0A[count]; + mem[256 * 11 + count] <= INIT_0B[count]; + mem[256 * 12 + count] <= INIT_0C[count]; + mem[256 * 13 + count] <= INIT_0D[count]; + mem[256 * 14 + count] <= INIT_0E[count]; + mem[256 * 15 + count] <= INIT_0F[count]; + mem[256 * 16 + count] <= INIT_10[count]; + mem[256 * 17 + count] <= INIT_11[count]; + mem[256 * 18 + count] <= INIT_12[count]; + mem[256 * 19 + count] <= INIT_13[count]; + mem[256 * 20 + count] <= INIT_14[count]; + mem[256 * 21 + count] <= INIT_15[count]; + mem[256 * 22 + count] <= INIT_16[count]; + mem[256 * 23 + count] <= INIT_17[count]; + mem[256 * 24 + count] <= INIT_18[count]; + mem[256 * 25 + count] <= INIT_19[count]; + mem[256 * 26 + count] <= INIT_1A[count]; + mem[256 * 27 + count] <= INIT_1B[count]; + mem[256 * 28 + count] <= INIT_1C[count]; + mem[256 * 29 + count] <= INIT_1D[count]; + mem[256 * 30 + count] <= INIT_1E[count]; + mem[256 * 31 + count] <= INIT_1F[count]; + mem[256 * 32 + count] <= INIT_20[count]; + mem[256 * 33 + count] <= INIT_21[count]; + mem[256 * 34 + count] <= INIT_22[count]; + mem[256 * 35 + count] <= INIT_23[count]; + mem[256 * 36 + count] <= INIT_24[count]; + mem[256 * 37 + count] <= INIT_25[count]; + mem[256 * 38 + count] <= INIT_26[count]; + mem[256 * 39 + count] <= INIT_27[count]; + mem[256 * 40 + count] <= INIT_28[count]; + mem[256 * 41 + count] <= INIT_29[count]; + mem[256 * 42 + count] <= INIT_2A[count]; + mem[256 * 43 + count] <= INIT_2B[count]; + mem[256 * 44 + count] <= INIT_2C[count]; + mem[256 * 45 + count] <= INIT_2D[count]; + mem[256 * 46 + count] <= INIT_2E[count]; + mem[256 * 47 + count] <= INIT_2F[count]; + mem[256 * 48 + count] <= INIT_30[count]; + mem[256 * 49 + count] <= INIT_31[count]; + mem[256 * 50 + count] <= INIT_32[count]; + mem[256 * 51 + count] <= INIT_33[count]; + mem[256 * 52 + count] <= INIT_34[count]; + mem[256 * 53 + count] <= INIT_35[count]; + mem[256 * 54 + count] <= INIT_36[count]; + mem[256 * 55 + count] <= INIT_37[count]; + mem[256 * 56 + count] <= INIT_38[count]; + mem[256 * 57 + count] <= INIT_39[count]; + mem[256 * 58 + count] <= INIT_3A[count]; + mem[256 * 59 + count] <= INIT_3B[count]; + mem[256 * 60 + count] <= INIT_3C[count]; + mem[256 * 61 + count] <= INIT_3D[count]; + mem[256 * 62 + count] <= INIT_3E[count]; + mem[256 * 63 + count] <= INIT_3F[count]; + end + address_collision <= 0; + address_collision_a_b <= 0; + address_collision_b_a <= 0; + change_clka <= 0; + change_clkb <= 0; + data_collision <= 0; + data_collision_a_b <= 0; + data_collision_b_a <= 0; + memory_collision <= 0; + memory_collision_a_b <= 0; + memory_collision_b_a <= 0; + setup_all_a_b <= 0; + setup_all_b_a <= 0; + setup_zero <= 0; + setup_rf_a_b <= 0; + setup_rf_b_a <= 0; + end + + assign data_addra_int = addra_int * 1; + assign data_addra_reg = addra_reg * 1; + assign data_addrb_int = addrb_int * 2; + assign data_addrb_reg = addrb_reg * 2; + + + initial begin + + display_flag = 1; + + case (SIM_COLLISION_CHECK) + + "NONE" : begin + assign setup_all_a_b = 1'b0; + assign setup_all_b_a = 1'b0; + assign setup_zero = 1'b0; + assign setup_rf_a_b = 1'b0; + assign setup_rf_b_a = 1'b0; + assign display_flag = 0; + end + "WARNING_ONLY" : begin + assign data_collision = 2'b00; + assign data_collision_a_b = 2'b00; + assign data_collision_b_a = 2'b00; + assign memory_collision = 1'b0; + assign memory_collision_a_b = 1'b0; + assign memory_collision_b_a = 1'b0; + end + "GENERATE_X_ONLY" : begin + assign display_flag = 0; + end + "ALL" : ; + default : begin + $display("Attribute Syntax Error : The Attribute SIM_COLLISION_CHECK on RAMB16_S1_S2 instance %m is set to %s. Legal values for this attribute are ALL, NONE, WARNING_ONLY or GENERATE_X_ONLY.", SIM_COLLISION_CHECK); + $finish; + end + + endcase // case(SIM_COLLISION_CHECK) + + end // initial begin + + + always @(posedge clka_int) begin + time_clka = $time; + #0 time_clkb_clka = time_clka - time_clkb; + change_clka = ~change_clka; + end + + always @(posedge clkb_int) begin + time_clkb = $time; + #0 time_clka_clkb = time_clkb - time_clka; + change_clkb = ~change_clkb; + end + + always @(change_clkb) begin + if ((0 < time_clka_clkb) && (time_clka_clkb < SETUP_ALL)) + setup_all_a_b = 1; + if ((0 < time_clka_clkb) && (time_clka_clkb < SETUP_READ_FIRST)) + setup_rf_a_b = 1; + end + + always @(change_clka) begin + if ((0 < time_clkb_clka) && (time_clkb_clka < SETUP_ALL)) + setup_all_b_a = 1; + if ((0 < time_clkb_clka) && (time_clkb_clka < SETUP_READ_FIRST)) + setup_rf_b_a = 1; + end + + always @(change_clkb or change_clka) begin + if ((time_clkb_clka == 0) && (time_clka_clkb == 0)) + setup_zero = 1; + end + + always @(posedge setup_zero) begin + if ((ena_int == 1) && (wea_int == 1) && + (enb_int == 1) && (web_int == 1) && + (data_addra_int[14:1] == data_addrb_int[14:1])) + memory_collision <= 1; + end + + always @(posedge setup_all_a_b or posedge setup_rf_a_b) begin + if ((ena_reg == 1) && (wea_reg == 1) && + (enb_int == 1) && (web_int == 1) && + (data_addra_reg[14:1] == data_addrb_int[14:1])) + memory_collision_a_b <= 1; + end + + always @(posedge setup_all_b_a or posedge setup_rf_b_a) begin + if ((ena_int == 1) && (wea_int == 1) && + (enb_reg == 1) && (web_reg == 1) && + (data_addra_int[14:1] == data_addrb_reg[14:1])) + memory_collision_b_a <= 1; + end + + always @(posedge setup_all_a_b) begin + if (data_addra_reg[14:1] == data_addrb_int[14:1]) begin + if ((ena_reg == 1) && (enb_int == 1)) begin + case ({wr_mode_a, wr_mode_b, wea_reg, web_int}) + 6'b000011 : begin data_collision_a_b <= 2'b11; display_wa_wb; end + 6'b000111 : begin data_collision_a_b <= 2'b11; display_wa_wb; end + 6'b001011 : begin data_collision_a_b <= 2'b10; display_wa_wb; end +// 6'b010011 : begin data_collision_a_b <= 2'b00; display_wa_wb; end +// 6'b010111 : begin data_collision_a_b <= 2'b00; display_wa_wb; end +// 6'b011011 : begin data_collision_a_b <= 2'b00; display_wa_wb; end + 6'b100011 : begin data_collision_a_b <= 2'b01; display_wa_wb; end + 6'b100111 : begin data_collision_a_b <= 2'b01; display_wa_wb; end + 6'b101011 : begin display_wa_wb; end + 6'b000001 : begin data_collision_a_b <= 2'b10; display_ra_wb; end +// 6'b000101 : begin data_collision_a_b <= 2'b00; display_ra_wb; end + 6'b001001 : begin data_collision_a_b <= 2'b10; display_ra_wb; end + 6'b010001 : begin data_collision_a_b <= 2'b10; display_ra_wb; end +// 6'b010101 : begin data_collision_a_b <= 2'b00; display_ra_wb; end + 6'b011001 : begin data_collision_a_b <= 2'b10; display_ra_wb; end + 6'b100001 : begin data_collision_a_b <= 2'b10; display_ra_wb; end +// 6'b100101 : begin data_collision_a_b <= 2'b00; display_ra_wb; end + 6'b101001 : begin data_collision_a_b <= 2'b10; display_ra_wb; end + 6'b000010 : begin data_collision_a_b <= 2'b01; display_wa_rb; end + 6'b000110 : begin data_collision_a_b <= 2'b01; display_wa_rb; end + 6'b001010 : begin data_collision_a_b <= 2'b01; display_wa_rb; end +// 6'b010010 : begin data_collision_a_b <= 2'b00; display_wa_rb; end +// 6'b010110 : begin data_collision_a_b <= 2'b00; display_wa_rb; end +// 6'b011010 : begin data_collision_a_b <= 2'b00; display_wa_rb; end + 6'b100010 : begin data_collision_a_b <= 2'b01; display_wa_rb; end + 6'b100110 : begin data_collision_a_b <= 2'b01; display_wa_rb; end + 6'b101010 : begin data_collision_a_b <= 2'b01; display_wa_rb; end + endcase + end + end + setup_all_a_b <= 0; + end + + + always @(posedge setup_all_b_a) begin + if (data_addra_int[14:1] == data_addrb_reg[14:1]) begin + if ((ena_int == 1) && (enb_reg == 1)) begin + case ({wr_mode_a, wr_mode_b, wea_int, web_reg}) + 6'b000011 : begin data_collision_b_a <= 2'b11; display_wa_wb; end +// 6'b000111 : begin data_collision_b_a <= 2'b00; display_wa_wb; end + 6'b001011 : begin data_collision_b_a <= 2'b10; display_wa_wb; end + 6'b010011 : begin data_collision_b_a <= 2'b11; display_wa_wb; end +// 6'b010111 : begin data_collision_b_a <= 2'b00; display_wa_wb; end + 6'b011011 : begin data_collision_b_a <= 2'b10; display_wa_wb; end + 6'b100011 : begin data_collision_b_a <= 2'b01; display_wa_wb; end + 6'b100111 : begin data_collision_b_a <= 2'b01; display_wa_wb; end + 6'b101011 : begin display_wa_wb; end + 6'b000001 : begin data_collision_b_a <= 2'b10; display_ra_wb; end + 6'b000101 : begin data_collision_b_a <= 2'b10; display_ra_wb; end + 6'b001001 : begin data_collision_b_a <= 2'b10; display_ra_wb; end + 6'b010001 : begin data_collision_b_a <= 2'b10; display_ra_wb; end + 6'b010101 : begin data_collision_b_a <= 2'b10; display_ra_wb; end + 6'b011001 : begin data_collision_b_a <= 2'b10; display_ra_wb; end + 6'b100001 : begin data_collision_b_a <= 2'b10; display_ra_wb; end + 6'b100101 : begin data_collision_b_a <= 2'b10; display_ra_wb; end + 6'b101001 : begin data_collision_b_a <= 2'b10; display_ra_wb; end + 6'b000010 : begin data_collision_b_a <= 2'b01; display_wa_rb; end + 6'b000110 : begin data_collision_b_a <= 2'b01; display_wa_rb; end + 6'b001010 : begin data_collision_b_a <= 2'b01; display_wa_rb; end +// 6'b010010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end +// 6'b010110 : begin data_collision_b_a <= 2'b00; display_wa_rb; end +// 6'b011010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end + 6'b100010 : begin data_collision_b_a <= 2'b01; display_wa_rb; end + 6'b100110 : begin data_collision_b_a <= 2'b01; display_wa_rb; end + 6'b101010 : begin data_collision_b_a <= 2'b01; display_wa_rb; end + endcase + end + end + setup_all_b_a <= 0; + end + + + always @(posedge setup_zero) begin + if (data_addra_int[14:1] == data_addrb_int[14:1]) begin + if ((ena_int == 1) && (enb_int == 1)) begin + case ({wr_mode_a, wr_mode_b, wea_int, web_int}) + 6'b000011 : begin data_collision <= 2'b11; display_wa_wb; end + 6'b000111 : begin data_collision <= 2'b11; display_wa_wb; end + 6'b001011 : begin data_collision <= 2'b10; display_wa_wb; end + 6'b010011 : begin data_collision <= 2'b11; display_wa_wb; end + 6'b010111 : begin data_collision <= 2'b11; display_wa_wb; end + 6'b011011 : begin data_collision <= 2'b10; display_wa_wb; end + 6'b100011 : begin data_collision <= 2'b01; display_wa_wb; end + 6'b100111 : begin data_collision <= 2'b01; display_wa_wb; end + 6'b101011 : begin display_wa_wb; end + 6'b000001 : begin data_collision <= 2'b10; display_ra_wb; end +// 6'b000101 : begin data_collision <= 2'b00; display_ra_wb; end + 6'b001001 : begin data_collision <= 2'b10; display_ra_wb; end + 6'b010001 : begin data_collision <= 2'b10; display_ra_wb; end +// 6'b010101 : begin data_collision <= 2'b00; display_ra_wb; end + 6'b011001 : begin data_collision <= 2'b10; display_ra_wb; end + 6'b100001 : begin data_collision <= 2'b10; display_ra_wb; end +// 6'b100101 : begin data_collision <= 2'b00; display_ra_wb; end + 6'b101001 : begin data_collision <= 2'b10; display_ra_wb; end + 6'b000010 : begin data_collision <= 2'b01; display_wa_rb; end + 6'b000110 : begin data_collision <= 2'b01; display_wa_rb; end + 6'b001010 : begin data_collision <= 2'b01; display_wa_rb; end +// 6'b010010 : begin data_collision <= 2'b00; display_wa_rb; end +// 6'b010110 : begin data_collision <= 2'b00; display_wa_rb; end +// 6'b011010 : begin data_collision <= 2'b00; display_wa_rb; end + 6'b100010 : begin data_collision <= 2'b01; display_wa_rb; end + 6'b100110 : begin data_collision <= 2'b01; display_wa_rb; end + 6'b101010 : begin data_collision <= 2'b01; display_wa_rb; end + endcase + end + end + setup_zero <= 0; + end + + task display_ra_wb; + begin + if (display_flag) + $display("Memory Collision Error on RAMB16_S1_S2:%m at simulation time %.3f ns\nA read was performed on address %h (hex) of Port A while a write was requested to the same address on Port B. The write will be successful however the read value on Port A is unknown until the next CLKA cycle.", $time/1000.0, addra_int); + end + endtask + + task display_wa_rb; + begin + if (display_flag) + $display("Memory Collision Error on RAMB16_S1_S2:%m at simulation time %.3f ns\nA read was performed on address %h (hex) of Port B while a write was requested to the same address on Port A. The write will be successful however the read value on Port B is unknown until the next CLKB cycle.", $time/1000.0, addrb_int); + end + endtask + + task display_wa_wb; + begin + if (display_flag) + $display("Memory Collision Error on RAMB16_S1_S2:%m at simulation time %.3f ns\nA write was requested to the same address simultaneously at both Port A and Port B of the RAM. The contents written to the RAM at address location %h (hex) of Port A and address location %h (hex) of Port B are unknown.", $time/1000.0, addra_int, addrb_int); + end + endtask + + + always @(posedge setup_rf_a_b) begin + if (data_addra_reg[14:1] == data_addrb_int[14:1]) begin + if ((ena_reg == 1) && (enb_int == 1)) begin + case ({wr_mode_a, wr_mode_b, wea_reg, web_int}) +// 6'b000011 : begin data_collision_a_b <= 2'b00; display_wa_wb; end +// 6'b000111 : begin data_collision_a_b <= 2'b00; display_wa_wb; end +// 6'b001011 : begin data_collision_a_b <= 2'b00; display_wa_wb; end + 6'b010011 : begin data_collision_a_b <= 2'b11; display_wa_wb; end + 6'b010111 : begin data_collision_a_b <= 2'b11; display_wa_wb; end + 6'b011011 : begin data_collision_a_b <= 2'b10; display_wa_wb; end +// 6'b100011 : begin data_collision_a_b <= 2'b00; display_wa_wb; end +// 6'b100111 : begin data_collision_a_b <= 2'b00; display_wa_wb; end +// 6'b101011 : begin data_collision_a_b <= 2'b00; display_wa_wb; end +// 6'b000001 : begin data_collision_a_b <= 2'b00; display_ra_wb; end +// 6'b000101 : begin data_collision_a_b <= 2'b00; display_ra_wb; end +// 6'b001001 : begin data_collision_a_b <= 2'b00; display_ra_wb; end +// 6'b010001 : begin data_collision_a_b <= 2'b00; display_ra_wb; end +// 6'b010101 : begin data_collision_a_b <= 2'b00; display_ra_wb; end +// 6'b011001 : begin data_collision_a_b <= 2'b00; display_ra_wb; end +// 6'b100001 : begin data_collision_a_b <= 2'b00; display_ra_wb; end +// 6'b100101 : begin data_collision_a_b <= 2'b00; display_ra_wb; end +// 6'b101001 : begin data_collision_a_b <= 2'b00; display_ra_wb; end +// 6'b000010 : begin data_collision_a_b <= 2'b00; display_wa_rb; end +// 6'b000110 : begin data_collision_a_b <= 2'b00; display_wa_rb; end +// 6'b001010 : begin data_collision_a_b <= 2'b00; display_wa_rb; end + 6'b010010 : begin data_collision_a_b <= 2'b01; display_wa_rb; end + 6'b010110 : begin data_collision_a_b <= 2'b01; display_wa_rb; end + 6'b011010 : begin data_collision_a_b <= 2'b01; display_wa_rb; end +// 6'b100010 : begin data_collision_a_b <= 2'b00; display_wa_rb; end +// 6'b100110 : begin data_collision_a_b <= 2'b00; display_wa_rb; end +// 6'b101010 : begin data_collision_a_b <= 2'b00; display_wa_rb; end + endcase + end + end + setup_rf_a_b <= 0; + end + + + always @(posedge setup_rf_b_a) begin + if (data_addra_int[14:1] == data_addrb_reg[14:1]) begin + if ((ena_int == 1) && (enb_reg == 1)) begin + case ({wr_mode_a, wr_mode_b, wea_int, web_reg}) +// 6'b000011 : begin data_collision_b_a <= 2'b00; display_wa_wb; end + 6'b000111 : begin data_collision_b_a <= 2'b11; display_wa_wb; end +// 6'b001011 : begin data_collision_b_a <= 2'b00; display_wa_wb; end +// 6'b010011 : begin data_collision_b_a <= 2'b00; display_wa_wb; end + 6'b010111 : begin data_collision_b_a <= 2'b11; display_wa_wb; end +// 6'b011011 : begin data_collision_b_a <= 2'b00; display_wa_wb; end +// 6'b100011 : begin data_collision_b_a <= 2'b00; display_wa_wb; end + 6'b100111 : begin data_collision_b_a <= 2'b01; display_wa_wb; end +// 6'b101011 : begin data_collision_b_a <= 2'b00; display_wa_wb; end +// 6'b000001 : begin data_collision_b_a <= 2'b00; display_ra_wb; end + 6'b000101 : begin data_collision_b_a <= 2'b10; display_ra_wb; end +// 6'b001001 : begin data_collision_b_a <= 2'b00; display_ra_wb; end +// 6'b010001 : begin data_collision_b_a <= 2'b00; display_ra_wb; end + 6'b010101 : begin data_collision_b_a <= 2'b10; display_ra_wb; end +// 6'b011001 : begin data_collision_b_a <= 2'b00; display_ra_wb; end +// 6'b100001 : begin data_collision_b_a <= 2'b00; display_ra_wb; end + 6'b100101 : begin data_collision_b_a <= 2'b10; display_ra_wb; end +// 6'b101001 : begin data_collision_b_a <= 2'b00; display_ra_wb; end +// 6'b000010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end +// 6'b000110 : begin data_collision_b_a <= 2'b00; display_wa_rb; end +// 6'b001010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end +// 6'b010010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end +// 6'b010110 : begin data_collision_b_a <= 2'b00; display_wa_rb; end +// 6'b011010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end +// 6'b100010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end +// 6'b100110 : begin data_collision_b_a <= 2'b00; display_wa_rb; end +// 6'b101010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end + endcase + end + end + setup_rf_b_a <= 0; + end + + + always @(posedge clka_int) begin + addra_reg <= addra_int; + ena_reg <= ena_int; + ssra_reg <= ssra_int; + wea_reg <= wea_int; + end + + always @(posedge clkb_int) begin + addrb_reg <= addrb_int; + enb_reg <= enb_int; + ssrb_reg <= ssrb_int; + web_reg <= web_int; + end + + // Data + always @(posedge memory_collision) begin + for (dmi = 0; dmi < 1; dmi = dmi + 1) begin + mem[data_addra_int + dmi] <= 1'bX; + end + memory_collision <= 0; + end + + always @(posedge memory_collision_a_b) begin + for (dmi = 0; dmi < 1; dmi = dmi + 1) begin + mem[data_addra_reg + dmi] <= 1'bX; + end + memory_collision_a_b <= 0; + end + + always @(posedge memory_collision_b_a) begin + for (dmi = 0; dmi < 1; dmi = dmi + 1) begin + mem[data_addra_int + dmi] <= 1'bX; + end + memory_collision_b_a <= 0; + end + + always @(posedge data_collision[1]) begin + if (ssra_int == 0) begin + doa_out <= 1'bX; + end + data_collision[1] <= 0; + end + + always @(posedge data_collision[0]) begin + if (ssrb_int == 0) begin + for (dbi = 0; dbi < 1; dbi = dbi + 1) begin + dob_out[data_addra_int[0 : 0] + dbi] <= 1'bX; + end + end + data_collision[0] <= 0; + end + + always @(posedge data_collision_a_b[1]) begin + if (ssra_reg == 0) begin + doa_out <= 1'bX; + end + data_collision_a_b[1] <= 0; + end + + always @(posedge data_collision_a_b[0]) begin + if (ssrb_int == 0) begin + for (dbi = 0; dbi < 1; dbi = dbi + 1) begin + dob_out[data_addra_reg[0 : 0] + dbi] <= 1'bX; + end + end + data_collision_a_b[0] <= 0; + end + + always @(posedge data_collision_b_a[1]) begin + if (ssra_int == 0) begin + doa_out <= 1'bX; + end + data_collision_b_a[1] <= 0; + end + + always @(posedge data_collision_b_a[0]) begin + if (ssrb_reg == 0) begin + for (dbi = 0; dbi < 1; dbi = dbi + 1) begin + dob_out[data_addra_int[0 : 0] + dbi] <= 1'bX; + end + end + data_collision_b_a[0] <= 0; + end + + + initial begin + case (WRITE_MODE_A) + "WRITE_FIRST" : wr_mode_a <= 2'b00; + "READ_FIRST" : wr_mode_a <= 2'b01; + "NO_CHANGE" : wr_mode_a <= 2'b10; + default : begin + $display("Attribute Syntax Error : The Attribute WRITE_MODE_A on RAMB16_S1_S2 instance %m is set to %s. Legal values for this attribute are WRITE_FIRST, READ_FIRST or NO_CHANGE.", WRITE_MODE_A); + $finish; + end + endcase + end + + initial begin + case (WRITE_MODE_B) + "WRITE_FIRST" : wr_mode_b <= 2'b00; + "READ_FIRST" : wr_mode_b <= 2'b01; + "NO_CHANGE" : wr_mode_b <= 2'b10; + default : begin + $display("Attribute Syntax Error : The Attribute WRITE_MODE_B on RAMB16_S1_S2 instance %m is set to %s. Legal values for this attribute are WRITE_FIRST, READ_FIRST or NO_CHANGE.", WRITE_MODE_B); + $finish; + end + endcase + end + + // Port A + always @(posedge clka_int) begin + if (ena_int == 1'b1) begin + if (ssra_int == 1'b1) begin + doa_out[0] <= SRVAL_A[0]; + end + else begin + if (wea_int == 1'b1) begin + if (wr_mode_a == 2'b00) begin + doa_out <= dia_int; + end + else if (wr_mode_a == 2'b01) begin + doa_out[0] <= mem[data_addra_int + 0]; + end + end + else begin + doa_out[0] <= mem[data_addra_int + 0]; + end + end + end + end + + always @(posedge clka_int) begin + if (ena_int == 1'b1 && wea_int == 1'b1) begin + mem[data_addra_int + 0] <= dia_int[0]; + end + end + + // Port B + always @(posedge clkb_int) begin + if (enb_int == 1'b1) begin + if (ssrb_int == 1'b1) begin + dob_out[0] <= SRVAL_B[0]; + dob_out[1] <= SRVAL_B[1]; + end + else begin + if (web_int == 1'b1) begin + if (wr_mode_b == 2'b00) begin + dob_out <= dib_int; + end + else if (wr_mode_b == 2'b01) begin + dob_out[0] <= mem[data_addrb_int + 0]; + dob_out[1] <= mem[data_addrb_int + 1]; + end + end + else begin + dob_out[0] <= mem[data_addrb_int + 0]; + dob_out[1] <= mem[data_addrb_int + 1]; + end + end + end + end + + always @(posedge clkb_int) begin + if (enb_int == 1'b1 && web_int == 1'b1) begin + mem[data_addrb_int + 0] <= dib_int[0]; + mem[data_addrb_int + 1] <= dib_int[1]; + end + end + + specify + (CLKA *> DOA) = (100, 100); + (CLKB *> DOB) = (100, 100); + endspecify + +endmodule + +`else + +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/RAMB16_S1_S2.v,v 1.11 2007/02/22 01:58:05 wloo Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2005 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Timing Simulation Library Component +// / / 16K-Bit Data and 2K-Bit Parity Dual Port Block RAM +// /___/ /\ Filename : RAMB16_S1_S2.v +// \ \ / \ Timestamp : Thu Mar 10 16:44:01 PST 2005 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 03/10/05 - Initialized outputs. +// 02/21/07 - Fixed parameter SIM_COLLISION_CHECK (CR 433281). +// End Revision + +`timescale 1 ps/1 ps + +module RAMB16_S1_S2 (DOA, DOB, ADDRA, ADDRB, CLKA, CLKB, DIA, DIB, ENA, ENB, SSRA, SSRB, WEA, WEB); + + parameter INIT_A = 1'h0; + parameter INIT_B = 2'h0; + parameter SRVAL_A = 1'h0; + parameter SRVAL_B = 2'h0; + parameter WRITE_MODE_A = "WRITE_FIRST"; + parameter WRITE_MODE_B = "WRITE_FIRST"; + parameter SIM_COLLISION_CHECK = "ALL"; + localparam SETUP_ALL = 1000; + localparam SETUP_READ_FIRST = 3000; + + parameter INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + + output [0:0] DOA; + output [1:0] DOB; + + input [13:0] ADDRA; + input [0:0] DIA; + input ENA, CLKA, WEA, SSRA; + input [12:0] ADDRB; + input [1:0] DIB; + input ENB, CLKB, WEB, SSRB; + + reg [0:0] doa_out = INIT_A[0:0]; + reg [1:0] dob_out = INIT_B[1:0]; + + reg [1:0] mem [8191:0]; + + reg [8:0] count, countp; + reg [1:0] wr_mode_a, wr_mode_b; + + reg [5:0] dmi, dbi; + reg [5:0] pmi, pbi; + + wire [13:0] addra_int; + reg [13:0] addra_reg; + wire [0:0] dia_int; + wire ena_int, clka_int, wea_int, ssra_int; + reg ena_reg, wea_reg, ssra_reg; + wire [12:0] addrb_int; + reg [12:0] addrb_reg; + wire [1:0] dib_int; + wire enb_int, clkb_int, web_int, ssrb_int; + reg display_flag, output_flag; + reg enb_reg, web_reg, ssrb_reg; + + time time_clka, time_clkb; + time time_clka_clkb; + time time_clkb_clka; + + reg setup_all_a_b; + reg setup_all_b_a; + reg setup_zero; + reg setup_rf_a_b; + reg setup_rf_b_a; + reg [1:0] data_collision, data_collision_a_b, data_collision_b_a; + reg memory_collision, memory_collision_a_b, memory_collision_b_a; + reg change_clka; + reg change_clkb; + + wire [14:0] data_addra_int; + wire [14:0] data_addra_reg; + wire [14:0] data_addrb_int; + wire [14:0] data_addrb_reg; + + wire dia_enable = ena_int && wea_int; + wire dib_enable = enb_int && web_int; + + tri0 GSR = glbl.GSR; + wire gsr_int; + + buf b_gsr (gsr_int, GSR); + + buf b_doa [0:0] (DOA, doa_out); + buf b_addra [13:0] (addra_int, ADDRA); + buf b_dia [0:0] (dia_int, DIA); + buf b_ena (ena_int, ENA); + buf b_clka (clka_int, CLKA); + buf b_ssra (ssra_int, SSRA); + buf b_wea (wea_int, WEA); + + buf b_dob [1:0] (DOB, dob_out); + buf b_addrb [12:0] (addrb_int, ADDRB); + buf b_dib [1:0] (dib_int, DIB); + buf b_enb (enb_int, ENB); + buf b_clkb (clkb_int, CLKB); + buf b_ssrb (ssrb_int, SSRB); + buf b_web (web_int, WEB); + + + always @(gsr_int) + if (gsr_int) begin + assign {doa_out} = INIT_A; + assign {dob_out} = INIT_B; + end + else begin + deassign doa_out; + deassign dob_out; + end + + + initial begin + + for (count = 0; count < 128; count = count + 1) begin + mem[count] = INIT_00[(count * 2) +: 2]; + mem[128 * 1 + count] = INIT_01[(count * 2) +: 2]; + mem[128 * 2 + count] = INIT_02[(count * 2) +: 2]; + mem[128 * 3 + count] = INIT_03[(count * 2) +: 2]; + mem[128 * 4 + count] = INIT_04[(count * 2) +: 2]; + mem[128 * 5 + count] = INIT_05[(count * 2) +: 2]; + mem[128 * 6 + count] = INIT_06[(count * 2) +: 2]; + mem[128 * 7 + count] = INIT_07[(count * 2) +: 2]; + mem[128 * 8 + count] = INIT_08[(count * 2) +: 2]; + mem[128 * 9 + count] = INIT_09[(count * 2) +: 2]; + mem[128 * 10 + count] = INIT_0A[(count * 2) +: 2]; + mem[128 * 11 + count] = INIT_0B[(count * 2) +: 2]; + mem[128 * 12 + count] = INIT_0C[(count * 2) +: 2]; + mem[128 * 13 + count] = INIT_0D[(count * 2) +: 2]; + mem[128 * 14 + count] = INIT_0E[(count * 2) +: 2]; + mem[128 * 15 + count] = INIT_0F[(count * 2) +: 2]; + mem[128 * 16 + count] = INIT_10[(count * 2) +: 2]; + mem[128 * 17 + count] = INIT_11[(count * 2) +: 2]; + mem[128 * 18 + count] = INIT_12[(count * 2) +: 2]; + mem[128 * 19 + count] = INIT_13[(count * 2) +: 2]; + mem[128 * 20 + count] = INIT_14[(count * 2) +: 2]; + mem[128 * 21 + count] = INIT_15[(count * 2) +: 2]; + mem[128 * 22 + count] = INIT_16[(count * 2) +: 2]; + mem[128 * 23 + count] = INIT_17[(count * 2) +: 2]; + mem[128 * 24 + count] = INIT_18[(count * 2) +: 2]; + mem[128 * 25 + count] = INIT_19[(count * 2) +: 2]; + mem[128 * 26 + count] = INIT_1A[(count * 2) +: 2]; + mem[128 * 27 + count] = INIT_1B[(count * 2) +: 2]; + mem[128 * 28 + count] = INIT_1C[(count * 2) +: 2]; + mem[128 * 29 + count] = INIT_1D[(count * 2) +: 2]; + mem[128 * 30 + count] = INIT_1E[(count * 2) +: 2]; + mem[128 * 31 + count] = INIT_1F[(count * 2) +: 2]; + mem[128 * 32 + count] = INIT_20[(count * 2) +: 2]; + mem[128 * 33 + count] = INIT_21[(count * 2) +: 2]; + mem[128 * 34 + count] = INIT_22[(count * 2) +: 2]; + mem[128 * 35 + count] = INIT_23[(count * 2) +: 2]; + mem[128 * 36 + count] = INIT_24[(count * 2) +: 2]; + mem[128 * 37 + count] = INIT_25[(count * 2) +: 2]; + mem[128 * 38 + count] = INIT_26[(count * 2) +: 2]; + mem[128 * 39 + count] = INIT_27[(count * 2) +: 2]; + mem[128 * 40 + count] = INIT_28[(count * 2) +: 2]; + mem[128 * 41 + count] = INIT_29[(count * 2) +: 2]; + mem[128 * 42 + count] = INIT_2A[(count * 2) +: 2]; + mem[128 * 43 + count] = INIT_2B[(count * 2) +: 2]; + mem[128 * 44 + count] = INIT_2C[(count * 2) +: 2]; + mem[128 * 45 + count] = INIT_2D[(count * 2) +: 2]; + mem[128 * 46 + count] = INIT_2E[(count * 2) +: 2]; + mem[128 * 47 + count] = INIT_2F[(count * 2) +: 2]; + mem[128 * 48 + count] = INIT_30[(count * 2) +: 2]; + mem[128 * 49 + count] = INIT_31[(count * 2) +: 2]; + mem[128 * 50 + count] = INIT_32[(count * 2) +: 2]; + mem[128 * 51 + count] = INIT_33[(count * 2) +: 2]; + mem[128 * 52 + count] = INIT_34[(count * 2) +: 2]; + mem[128 * 53 + count] = INIT_35[(count * 2) +: 2]; + mem[128 * 54 + count] = INIT_36[(count * 2) +: 2]; + mem[128 * 55 + count] = INIT_37[(count * 2) +: 2]; + mem[128 * 56 + count] = INIT_38[(count * 2) +: 2]; + mem[128 * 57 + count] = INIT_39[(count * 2) +: 2]; + mem[128 * 58 + count] = INIT_3A[(count * 2) +: 2]; + mem[128 * 59 + count] = INIT_3B[(count * 2) +: 2]; + mem[128 * 60 + count] = INIT_3C[(count * 2) +: 2]; + mem[128 * 61 + count] = INIT_3D[(count * 2) +: 2]; + mem[128 * 62 + count] = INIT_3E[(count * 2) +: 2]; + mem[128 * 63 + count] = INIT_3F[(count * 2) +: 2]; + end + + + change_clka <= 0; + change_clkb <= 0; + data_collision <= 0; + data_collision_a_b <= 0; + data_collision_b_a <= 0; + memory_collision <= 0; + memory_collision_a_b <= 0; + memory_collision_b_a <= 0; + setup_all_a_b <= 0; + setup_all_b_a <= 0; + setup_zero <= 0; + setup_rf_a_b <= 0; + setup_rf_b_a <= 0; + end + + assign data_addra_int = addra_int * 1; + assign data_addra_reg = addra_reg * 1; + assign data_addrb_int = addrb_int * 2; + assign data_addrb_reg = addrb_reg * 2; + + + initial begin + + display_flag = 1; + output_flag = 1; + + case (SIM_COLLISION_CHECK) + + "NONE" : begin + output_flag = 0; + display_flag = 0; + end + "WARNING_ONLY" : output_flag = 0; + "GENERATE_X_ONLY" : display_flag = 0; + "ALL" : ; + + default : begin + $display("Attribute Syntax Error : The Attribute SIM_COLLISION_CHECK on RAMB16_S1_S2 instance %m is set to %s. Legal values for this attribute are ALL, NONE, WARNING_ONLY or GENERATE_X_ONLY.", SIM_COLLISION_CHECK); + $finish; + end + + endcase // case(SIM_COLLISION_CHECK) + + end // initial begin + + + always @(posedge clka_int) begin + if ((output_flag || display_flag)) begin + time_clka = $time; + #0 time_clkb_clka = time_clka - time_clkb; + change_clka = ~change_clka; + end + end + + always @(posedge clkb_int) begin + if ((output_flag || display_flag)) begin + time_clkb = $time; + #0 time_clka_clkb = time_clkb - time_clka; + change_clkb = ~change_clkb; + end + end + + always @(change_clkb) begin + if ((0 < time_clka_clkb) && (time_clka_clkb < SETUP_ALL)) + setup_all_a_b = 1; + if ((0 < time_clka_clkb) && (time_clka_clkb < SETUP_READ_FIRST)) + setup_rf_a_b = 1; + end + + always @(change_clka) begin + if ((0 < time_clkb_clka) && (time_clkb_clka < SETUP_ALL)) + setup_all_b_a = 1; + if ((0 < time_clkb_clka) && (time_clkb_clka < SETUP_READ_FIRST)) + setup_rf_b_a = 1; + end + + always @(change_clkb or change_clka) begin + if ((time_clkb_clka == 0) && (time_clka_clkb == 0)) + setup_zero = 1; + end + + always @(posedge setup_zero) begin + if ((ena_int == 1) && (wea_int == 1) && + (enb_int == 1) && (web_int == 1) && + (data_addra_int[14:1] == data_addrb_int[14:1])) + memory_collision <= 1; + end + + always @(posedge setup_all_a_b or posedge setup_rf_a_b) begin + if ((ena_reg == 1) && (wea_reg == 1) && + (enb_int == 1) && (web_int == 1) && + (data_addra_reg[14:1] == data_addrb_int[14:1])) + memory_collision_a_b <= 1; + end + + always @(posedge setup_all_b_a or posedge setup_rf_b_a) begin + if ((ena_int == 1) && (wea_int == 1) && + (enb_reg == 1) && (web_reg == 1) && + (data_addra_int[14:1] == data_addrb_reg[14:1])) + memory_collision_b_a <= 1; + end + + always @(posedge setup_all_a_b) begin + if (data_addra_reg[14:1] == data_addrb_int[14:1]) begin + if ((ena_reg == 1) && (enb_int == 1)) begin + case ({wr_mode_a, wr_mode_b, wea_reg, web_int}) + 6'b000011 : begin data_collision_a_b <= 2'b11; display_wa_wb; end + 6'b000111 : begin data_collision_a_b <= 2'b11; display_wa_wb; end + 6'b001011 : begin data_collision_a_b <= 2'b10; display_wa_wb; end +// 6'b010011 : begin data_collision_a_b <= 2'b00; display_wa_wb; end +// 6'b010111 : begin data_collision_a_b <= 2'b00; display_wa_wb; end +// 6'b011011 : begin data_collision_a_b <= 2'b00; display_wa_wb; end + 6'b100011 : begin data_collision_a_b <= 2'b01; display_wa_wb; end + 6'b100111 : begin data_collision_a_b <= 2'b01; display_wa_wb; end + 6'b101011 : begin display_wa_wb; end + 6'b000001 : begin data_collision_a_b <= 2'b10; display_ra_wb; end +// 6'b000101 : begin data_collision_a_b <= 2'b00; display_ra_wb; end + 6'b001001 : begin data_collision_a_b <= 2'b10; display_ra_wb; end + 6'b010001 : begin data_collision_a_b <= 2'b10; display_ra_wb; end +// 6'b010101 : begin data_collision_a_b <= 2'b00; display_ra_wb; end + 6'b011001 : begin data_collision_a_b <= 2'b10; display_ra_wb; end + 6'b100001 : begin data_collision_a_b <= 2'b10; display_ra_wb; end +// 6'b100101 : begin data_collision_a_b <= 2'b00; display_ra_wb; end + 6'b101001 : begin data_collision_a_b <= 2'b10; display_ra_wb; end + 6'b000010 : begin data_collision_a_b <= 2'b01; display_wa_rb; end + 6'b000110 : begin data_collision_a_b <= 2'b01; display_wa_rb; end + 6'b001010 : begin data_collision_a_b <= 2'b01; display_wa_rb; end +// 6'b010010 : begin data_collision_a_b <= 2'b00; display_wa_rb; end +// 6'b010110 : begin data_collision_a_b <= 2'b00; display_wa_rb; end +// 6'b011010 : begin data_collision_a_b <= 2'b00; display_wa_rb; end + 6'b100010 : begin data_collision_a_b <= 2'b01; display_wa_rb; end + 6'b100110 : begin data_collision_a_b <= 2'b01; display_wa_rb; end + 6'b101010 : begin data_collision_a_b <= 2'b01; display_wa_rb; end + endcase + end + end + setup_all_a_b <= 0; + end + + + always @(posedge setup_all_b_a) begin + if (data_addra_int[14:1] == data_addrb_reg[14:1]) begin + if ((ena_int == 1) && (enb_reg == 1)) begin + case ({wr_mode_a, wr_mode_b, wea_int, web_reg}) + 6'b000011 : begin data_collision_b_a <= 2'b11; display_wa_wb; end +// 6'b000111 : begin data_collision_b_a <= 2'b00; display_wa_wb; end + 6'b001011 : begin data_collision_b_a <= 2'b10; display_wa_wb; end + 6'b010011 : begin data_collision_b_a <= 2'b11; display_wa_wb; end +// 6'b010111 : begin data_collision_b_a <= 2'b00; display_wa_wb; end + 6'b011011 : begin data_collision_b_a <= 2'b10; display_wa_wb; end + 6'b100011 : begin data_collision_b_a <= 2'b01; display_wa_wb; end + 6'b100111 : begin data_collision_b_a <= 2'b01; display_wa_wb; end + 6'b101011 : begin display_wa_wb; end + 6'b000001 : begin data_collision_b_a <= 2'b10; display_ra_wb; end + 6'b000101 : begin data_collision_b_a <= 2'b10; display_ra_wb; end + 6'b001001 : begin data_collision_b_a <= 2'b10; display_ra_wb; end + 6'b010001 : begin data_collision_b_a <= 2'b10; display_ra_wb; end + 6'b010101 : begin data_collision_b_a <= 2'b10; display_ra_wb; end + 6'b011001 : begin data_collision_b_a <= 2'b10; display_ra_wb; end + 6'b100001 : begin data_collision_b_a <= 2'b10; display_ra_wb; end + 6'b100101 : begin data_collision_b_a <= 2'b10; display_ra_wb; end + 6'b101001 : begin data_collision_b_a <= 2'b10; display_ra_wb; end + 6'b000010 : begin data_collision_b_a <= 2'b01; display_wa_rb; end + 6'b000110 : begin data_collision_b_a <= 2'b01; display_wa_rb; end + 6'b001010 : begin data_collision_b_a <= 2'b01; display_wa_rb; end +// 6'b010010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end +// 6'b010110 : begin data_collision_b_a <= 2'b00; display_wa_rb; end +// 6'b011010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end + 6'b100010 : begin data_collision_b_a <= 2'b01; display_wa_rb; end + 6'b100110 : begin data_collision_b_a <= 2'b01; display_wa_rb; end + 6'b101010 : begin data_collision_b_a <= 2'b01; display_wa_rb; end + endcase + end + end + setup_all_b_a <= 0; + end + + + always @(posedge setup_zero) begin + if (data_addra_int[14:1] == data_addrb_int[14:1]) begin + if ((ena_int == 1) && (enb_int == 1)) begin + case ({wr_mode_a, wr_mode_b, wea_int, web_int}) + 6'b000011 : begin data_collision <= 2'b11; display_wa_wb; end + 6'b000111 : begin data_collision <= 2'b11; display_wa_wb; end + 6'b001011 : begin data_collision <= 2'b10; display_wa_wb; end + 6'b010011 : begin data_collision <= 2'b11; display_wa_wb; end + 6'b010111 : begin data_collision <= 2'b11; display_wa_wb; end + 6'b011011 : begin data_collision <= 2'b10; display_wa_wb; end + 6'b100011 : begin data_collision <= 2'b01; display_wa_wb; end + 6'b100111 : begin data_collision <= 2'b01; display_wa_wb; end + 6'b101011 : begin display_wa_wb; end + 6'b000001 : begin data_collision <= 2'b10; display_ra_wb; end +// 6'b000101 : begin data_collision <= 2'b00; display_ra_wb; end + 6'b001001 : begin data_collision <= 2'b10; display_ra_wb; end + 6'b010001 : begin data_collision <= 2'b10; display_ra_wb; end +// 6'b010101 : begin data_collision <= 2'b00; display_ra_wb; end + 6'b011001 : begin data_collision <= 2'b10; display_ra_wb; end + 6'b100001 : begin data_collision <= 2'b10; display_ra_wb; end +// 6'b100101 : begin data_collision <= 2'b00; display_ra_wb; end + 6'b101001 : begin data_collision <= 2'b10; display_ra_wb; end + 6'b000010 : begin data_collision <= 2'b01; display_wa_rb; end + 6'b000110 : begin data_collision <= 2'b01; display_wa_rb; end + 6'b001010 : begin data_collision <= 2'b01; display_wa_rb; end +// 6'b010010 : begin data_collision <= 2'b00; display_wa_rb; end +// 6'b010110 : begin data_collision <= 2'b00; display_wa_rb; end +// 6'b011010 : begin data_collision <= 2'b00; display_wa_rb; end + 6'b100010 : begin data_collision <= 2'b01; display_wa_rb; end + 6'b100110 : begin data_collision <= 2'b01; display_wa_rb; end + 6'b101010 : begin data_collision <= 2'b01; display_wa_rb; end + endcase + end + end + setup_zero <= 0; + end + + task display_ra_wb; + begin + if (display_flag) + $display("Memory Collision Error on RAMB16_S1_S2:%m at simulation time %.3f ns\nA read was performed on address %h (hex) of Port A while a write was requested to the same address on Port B. The write will be successful however the read value on Port A is unknown until the next CLKA cycle.", $time/1000.0, addra_int); + end + endtask + + task display_wa_rb; + begin + if (display_flag) + $display("Memory Collision Error on RAMB16_S1_S2:%m at simulation time %.3f ns\nA read was performed on address %h (hex) of Port B while a write was requested to the same address on Port A. The write will be successful however the read value on Port B is unknown until the next CLKB cycle.", $time/1000.0, addrb_int); + end + endtask + + task display_wa_wb; + begin + if (display_flag) + $display("Memory Collision Error on RAMB16_S1_S2:%m at simulation time %.3f ns\nA write was requested to the same address simultaneously at both Port A and Port B of the RAM. The contents written to the RAM at address location %h (hex) of Port A and address location %h (hex) of Port B are unknown.", $time/1000.0, addra_int, addrb_int); + end + endtask + + + always @(posedge setup_rf_a_b) begin + if (data_addra_reg[14:1] == data_addrb_int[14:1]) begin + if ((ena_reg == 1) && (enb_int == 1)) begin + case ({wr_mode_a, wr_mode_b, wea_reg, web_int}) +// 6'b000011 : begin data_collision_a_b <= 2'b00; display_wa_wb; end +// 6'b000111 : begin data_collision_a_b <= 2'b00; display_wa_wb; end +// 6'b001011 : begin data_collision_a_b <= 2'b00; display_wa_wb; end + 6'b010011 : begin data_collision_a_b <= 2'b11; display_wa_wb; end + 6'b010111 : begin data_collision_a_b <= 2'b11; display_wa_wb; end + 6'b011011 : begin data_collision_a_b <= 2'b10; display_wa_wb; end +// 6'b100011 : begin data_collision_a_b <= 2'b00; display_wa_wb; end +// 6'b100111 : begin data_collision_a_b <= 2'b00; display_wa_wb; end +// 6'b101011 : begin data_collision_a_b <= 2'b00; display_wa_wb; end +// 6'b000001 : begin data_collision_a_b <= 2'b00; display_ra_wb; end +// 6'b000101 : begin data_collision_a_b <= 2'b00; display_ra_wb; end +// 6'b001001 : begin data_collision_a_b <= 2'b00; display_ra_wb; end +// 6'b010001 : begin data_collision_a_b <= 2'b00; display_ra_wb; end +// 6'b010101 : begin data_collision_a_b <= 2'b00; display_ra_wb; end +// 6'b011001 : begin data_collision_a_b <= 2'b00; display_ra_wb; end +// 6'b100001 : begin data_collision_a_b <= 2'b00; display_ra_wb; end +// 6'b100101 : begin data_collision_a_b <= 2'b00; display_ra_wb; end +// 6'b101001 : begin data_collision_a_b <= 2'b00; display_ra_wb; end +// 6'b000010 : begin data_collision_a_b <= 2'b00; display_wa_rb; end +// 6'b000110 : begin data_collision_a_b <= 2'b00; display_wa_rb; end +// 6'b001010 : begin data_collision_a_b <= 2'b00; display_wa_rb; end + 6'b010010 : begin data_collision_a_b <= 2'b01; display_wa_rb; end + 6'b010110 : begin data_collision_a_b <= 2'b01; display_wa_rb; end + 6'b011010 : begin data_collision_a_b <= 2'b01; display_wa_rb; end +// 6'b100010 : begin data_collision_a_b <= 2'b00; display_wa_rb; end +// 6'b100110 : begin data_collision_a_b <= 2'b00; display_wa_rb; end +// 6'b101010 : begin data_collision_a_b <= 2'b00; display_wa_rb; end + endcase + end + end + setup_rf_a_b <= 0; + end + + + always @(posedge setup_rf_b_a) begin + if (data_addra_int[14:1] == data_addrb_reg[14:1]) begin + if ((ena_int == 1) && (enb_reg == 1)) begin + case ({wr_mode_a, wr_mode_b, wea_int, web_reg}) +// 6'b000011 : begin data_collision_b_a <= 2'b00; display_wa_wb; end + 6'b000111 : begin data_collision_b_a <= 2'b11; display_wa_wb; end +// 6'b001011 : begin data_collision_b_a <= 2'b00; display_wa_wb; end +// 6'b010011 : begin data_collision_b_a <= 2'b00; display_wa_wb; end + 6'b010111 : begin data_collision_b_a <= 2'b11; display_wa_wb; end +// 6'b011011 : begin data_collision_b_a <= 2'b00; display_wa_wb; end +// 6'b100011 : begin data_collision_b_a <= 2'b00; display_wa_wb; end + 6'b100111 : begin data_collision_b_a <= 2'b01; display_wa_wb; end +// 6'b101011 : begin data_collision_b_a <= 2'b00; display_wa_wb; end +// 6'b000001 : begin data_collision_b_a <= 2'b00; display_ra_wb; end + 6'b000101 : begin data_collision_b_a <= 2'b10; display_ra_wb; end +// 6'b001001 : begin data_collision_b_a <= 2'b00; display_ra_wb; end +// 6'b010001 : begin data_collision_b_a <= 2'b00; display_ra_wb; end + 6'b010101 : begin data_collision_b_a <= 2'b10; display_ra_wb; end +// 6'b011001 : begin data_collision_b_a <= 2'b00; display_ra_wb; end +// 6'b100001 : begin data_collision_b_a <= 2'b00; display_ra_wb; end + 6'b100101 : begin data_collision_b_a <= 2'b10; display_ra_wb; end +// 6'b101001 : begin data_collision_b_a <= 2'b00; display_ra_wb; end +// 6'b000010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end +// 6'b000110 : begin data_collision_b_a <= 2'b00; display_wa_rb; end +// 6'b001010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end +// 6'b010010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end +// 6'b010110 : begin data_collision_b_a <= 2'b00; display_wa_rb; end +// 6'b011010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end +// 6'b100010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end +// 6'b100110 : begin data_collision_b_a <= 2'b00; display_wa_rb; end +// 6'b101010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end + endcase + end + end + setup_rf_b_a <= 0; + end + + + always @(posedge clka_int) begin + if ((output_flag || display_flag)) begin + addra_reg <= addra_int; + ena_reg <= ena_int; + ssra_reg <= ssra_int; + wea_reg <= wea_int; + end + end + + always @(posedge clkb_int) begin + if ((output_flag || display_flag)) begin + addrb_reg <= addrb_int; + enb_reg <= enb_int; + ssrb_reg <= ssrb_int; + web_reg <= web_int; + end + end + + + // Data + always @(posedge memory_collision) begin + if ((output_flag || display_flag)) begin + mem[addra_int[13:1]][addra_int[0:0] * 1 +: 1] <= 1'bx; + memory_collision <= 0; + end + + end + + always @(posedge memory_collision_a_b) begin + if ((output_flag || display_flag)) begin + mem[addra_reg[13:1]][addra_reg[0:0] * 1 +: 1] <= 1'bx; + memory_collision_a_b <= 0; + end + end + + always @(posedge memory_collision_b_a) begin + if ((output_flag || display_flag)) begin + mem[addra_int[13:1]][addra_int[0:0] * 1 +: 1] <= 1'bx; + memory_collision_b_a <= 0; + end + end + + always @(posedge data_collision[1]) begin + if (ssra_int == 0 && output_flag) begin + doa_out <= #100 1'bX; + end + data_collision[1] <= 0; + end + + always @(posedge data_collision[0]) begin + if (ssrb_int == 0 && output_flag) begin + dob_out[addra_int[0:0] * 1 +: 1] <= #100 1'bX; + end + data_collision[0] <= 0; + end + + always @(posedge data_collision_a_b[1]) begin + if (ssra_reg == 0 && output_flag) begin + doa_out <= #100 1'bX; + end + data_collision_a_b[1] <= 0; + end + + always @(posedge data_collision_a_b[0]) begin + if (ssrb_int == 0 && output_flag) begin + dob_out[addra_reg[0:0] * 1 +: 1] <= #100 1'bX; + end + data_collision_a_b[0] <= 0; + end + + always @(posedge data_collision_b_a[1]) begin + if (ssra_int == 0 && output_flag) begin + doa_out <= #100 1'bX; + end + data_collision_b_a[1] <= 0; + end + + always @(posedge data_collision_b_a[0]) begin + if (ssrb_reg == 0 && output_flag) begin + dob_out[addra_int[0:0] * 1 +: 1] <= #100 1'bX; + end + data_collision_b_a[0] <= 0; + end + + + initial begin + case (WRITE_MODE_A) + "WRITE_FIRST" : wr_mode_a <= 2'b00; + "READ_FIRST" : wr_mode_a <= 2'b01; + "NO_CHANGE" : wr_mode_a <= 2'b10; + default : begin + $display("Attribute Syntax Error : The Attribute WRITE_MODE_A on RAMB16_S1_S2 instance %m is set to %s. Legal values for this attribute are WRITE_FIRST, READ_FIRST or NO_CHANGE.", WRITE_MODE_A); + $finish; + end + endcase + end + + initial begin + case (WRITE_MODE_B) + "WRITE_FIRST" : wr_mode_b <= 2'b00; + "READ_FIRST" : wr_mode_b <= 2'b01; + "NO_CHANGE" : wr_mode_b <= 2'b10; + default : begin + $display("Attribute Syntax Error : The Attribute WRITE_MODE_B on RAMB16_S1_S2 instance %m is set to %s. Legal values for this attribute are WRITE_FIRST, READ_FIRST or NO_CHANGE.", WRITE_MODE_B); + $finish; + end + endcase + end + + + // Port A + always @(posedge clka_int) begin + + if (ena_int == 1'b1) begin + + if (ssra_int == 1'b1) begin + {doa_out} <= #100 SRVAL_A; + end + else begin + if (wea_int == 1'b1) begin + if (wr_mode_a == 2'b00) begin + doa_out <= #100 dia_int; + end + else if (wr_mode_a == 2'b01) begin + + doa_out <= #100 mem[addra_int[13:1]][addra_int[0:0] * 1 +: 1]; + + end + end + else begin + + doa_out <= #100 mem[addra_int[13:1]][addra_int[0:0] * 1 +: 1]; + + end + end + + // memory + if (wea_int == 1'b1) begin + mem[addra_int[13:1]][addra_int[0:0] * 1 +: 1] <= dia_int; + end + + end + end + + + // Port B + always @(posedge clkb_int) begin + + if (enb_int == 1'b1) begin + + if (ssrb_int == 1'b1) begin + {dob_out} <= #100 SRVAL_B; + end + else begin + if (web_int == 1'b1) begin + if (wr_mode_b == 2'b00) begin + dob_out <= #100 dib_int; + end + else if (wr_mode_b == 2'b01) begin + dob_out <= #100 mem[addrb_int]; + end + end + else begin + dob_out <= #100 mem[addrb_int]; + end + end + + // memory + if (web_int == 1'b1) begin + mem[addrb_int] <= dib_int; + end + + end + end + + +endmodule + +`endif diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/RAMB16_S1_S36.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/RAMB16_S1_S36.v new file mode 100644 index 0000000..2e413cf --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/RAMB16_S1_S36.v @@ -0,0 +1,1829 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/RAMB16_S1_S36.v,v 1.10 2007/02/22 01:58:05 wloo Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2005 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / 16K-Bit Data and 2K-Bit Parity Dual Port Block RAM +// /___/ /\ Filename : RAMB16_S1_S36.v +// \ \ / \ Timestamp : Thu Mar 10 16:43:35 PST 2005 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// End Revision + +`ifdef legacy_model + +`timescale 1 ps / 1 ps + +module RAMB16_S1_S36 (DOA, DOB, DOPB, ADDRA, ADDRB, CLKA, CLKB, DIA, DIB, DIPB, ENA, ENB, SSRA, SSRB, WEA, WEB); + + parameter INIT_A = 1'h0; + parameter INIT_B = 36'h0; + parameter SRVAL_A = 1'h0; + parameter SRVAL_B = 36'h0; + parameter WRITE_MODE_A = "WRITE_FIRST"; + parameter WRITE_MODE_B = "WRITE_FIRST"; + parameter SIM_COLLISION_CHECK = "ALL"; + localparam SETUP_ALL = 1000; + localparam SETUP_READ_FIRST = 3000; + + parameter INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + + output [0:0] DOA; + reg [0:0] doa_out; + wire doa_out0; + + input [13:0] ADDRA; + input [0:0] DIA; + input ENA, CLKA, WEA, SSRA; + + output [31:0] DOB; + output [3:0] DOPB; + reg [31:0] dob_out; + reg [3:0] dopb_out; + wire dob_out0, dob_out1, dob_out2, dob_out3, dob_out4, dob_out5, dob_out6, dob_out7, dob_out8, dob_out9, dob_out10, dob_out11, dob_out12, dob_out13, dob_out14, dob_out15, dob_out16, dob_out17, dob_out18, dob_out19, dob_out20, dob_out21, dob_out22, dob_out23, dob_out24, dob_out25, dob_out26, dob_out27, dob_out28, dob_out29, dob_out30, dob_out31; + wire dopb0_out, dopb1_out, dopb2_out, dopb3_out; + + input [8:0] ADDRB; + input [31:0] DIB; + input [3:0] DIPB; + input ENB, CLKB, WEB, SSRB; + + reg [18431:0] mem; + reg [8:0] count; + reg [1:0] wr_mode_a, wr_mode_b; + + reg [5:0] dmi, dbi; + reg [5:0] pmi, pbi; + + wire [13:0] addra_int; + reg [13:0] addra_reg; + wire [0:0] dia_int; + wire ena_int, clka_int, wea_int, ssra_int; + reg ena_reg, wea_reg, ssra_reg; + wire [8:0] addrb_int; + reg [8:0] addrb_reg; + wire [31:0] dib_int; + wire [3:0] dipb_int; + wire enb_int, clkb_int, web_int, ssrb_int; + reg display_flag; + reg enb_reg, web_reg, ssrb_reg; + + time time_clka, time_clkb; + time time_clka_clkb; + time time_clkb_clka; + + reg setup_all_a_b; + reg setup_all_b_a; + reg setup_zero; + reg setup_rf_a_b; + reg setup_rf_b_a; + reg [1:0] data_collision, data_collision_a_b, data_collision_b_a; + reg memory_collision, memory_collision_a_b, memory_collision_b_a; + reg address_collision, address_collision_a_b, address_collision_b_a; + reg change_clka; + reg change_clkb; + + wire [14:0] data_addra_int; + wire [14:0] data_addra_reg; + wire [14:0] data_addrb_int; + wire [14:0] data_addrb_reg; + wire [15:0] parity_addra_int; + wire [15:0] parity_addra_reg; + wire [15:0] parity_addrb_int; + wire [15:0] parity_addrb_reg; + + tri0 GSR = glbl.GSR; + + always @(GSR) + if (GSR) begin + assign doa_out = INIT_A[0:0]; + assign dob_out = INIT_B[31:0]; + assign dopb_out = INIT_B[35:32]; + end + else begin + deassign doa_out; + deassign dob_out; + deassign dopb_out; + end + + buf b_doa_out0 (doa_out0, doa_out[0]); + buf b_dob_out0 (dob_out0, dob_out[0]); + buf b_dob_out1 (dob_out1, dob_out[1]); + buf b_dob_out2 (dob_out2, dob_out[2]); + buf b_dob_out3 (dob_out3, dob_out[3]); + buf b_dob_out4 (dob_out4, dob_out[4]); + buf b_dob_out5 (dob_out5, dob_out[5]); + buf b_dob_out6 (dob_out6, dob_out[6]); + buf b_dob_out7 (dob_out7, dob_out[7]); + buf b_dob_out8 (dob_out8, dob_out[8]); + buf b_dob_out9 (dob_out9, dob_out[9]); + buf b_dob_out10 (dob_out10, dob_out[10]); + buf b_dob_out11 (dob_out11, dob_out[11]); + buf b_dob_out12 (dob_out12, dob_out[12]); + buf b_dob_out13 (dob_out13, dob_out[13]); + buf b_dob_out14 (dob_out14, dob_out[14]); + buf b_dob_out15 (dob_out15, dob_out[15]); + buf b_dob_out16 (dob_out16, dob_out[16]); + buf b_dob_out17 (dob_out17, dob_out[17]); + buf b_dob_out18 (dob_out18, dob_out[18]); + buf b_dob_out19 (dob_out19, dob_out[19]); + buf b_dob_out20 (dob_out20, dob_out[20]); + buf b_dob_out21 (dob_out21, dob_out[21]); + buf b_dob_out22 (dob_out22, dob_out[22]); + buf b_dob_out23 (dob_out23, dob_out[23]); + buf b_dob_out24 (dob_out24, dob_out[24]); + buf b_dob_out25 (dob_out25, dob_out[25]); + buf b_dob_out26 (dob_out26, dob_out[26]); + buf b_dob_out27 (dob_out27, dob_out[27]); + buf b_dob_out28 (dob_out28, dob_out[28]); + buf b_dob_out29 (dob_out29, dob_out[29]); + buf b_dob_out30 (dob_out30, dob_out[30]); + buf b_dob_out31 (dob_out31, dob_out[31]); + buf b_dopb_out0 (dopb_out0, dopb_out[0]); + buf b_dopb_out1 (dopb_out1, dopb_out[1]); + buf b_dopb_out2 (dopb_out2, dopb_out[2]); + buf b_dopb_out3 (dopb_out3, dopb_out[3]); + + buf b_doa0 (DOA[0], doa_out0); + buf b_dob0 (DOB[0], dob_out0); + buf b_dob1 (DOB[1], dob_out1); + buf b_dob2 (DOB[2], dob_out2); + buf b_dob3 (DOB[3], dob_out3); + buf b_dob4 (DOB[4], dob_out4); + buf b_dob5 (DOB[5], dob_out5); + buf b_dob6 (DOB[6], dob_out6); + buf b_dob7 (DOB[7], dob_out7); + buf b_dob8 (DOB[8], dob_out8); + buf b_dob9 (DOB[9], dob_out9); + buf b_dob10 (DOB[10], dob_out10); + buf b_dob11 (DOB[11], dob_out11); + buf b_dob12 (DOB[12], dob_out12); + buf b_dob13 (DOB[13], dob_out13); + buf b_dob14 (DOB[14], dob_out14); + buf b_dob15 (DOB[15], dob_out15); + buf b_dob16 (DOB[16], dob_out16); + buf b_dob17 (DOB[17], dob_out17); + buf b_dob18 (DOB[18], dob_out18); + buf b_dob19 (DOB[19], dob_out19); + buf b_dob20 (DOB[20], dob_out20); + buf b_dob21 (DOB[21], dob_out21); + buf b_dob22 (DOB[22], dob_out22); + buf b_dob23 (DOB[23], dob_out23); + buf b_dob24 (DOB[24], dob_out24); + buf b_dob25 (DOB[25], dob_out25); + buf b_dob26 (DOB[26], dob_out26); + buf b_dob27 (DOB[27], dob_out27); + buf b_dob28 (DOB[28], dob_out28); + buf b_dob29 (DOB[29], dob_out29); + buf b_dob30 (DOB[30], dob_out30); + buf b_dob31 (DOB[31], dob_out31); + buf b_dopb0 (DOPB[0], dopb_out0); + buf b_dopb1 (DOPB[1], dopb_out1); + buf b_dopb2 (DOPB[2], dopb_out2); + buf b_dopb3 (DOPB[3], dopb_out3); + + buf b_addra_0 (addra_int[0], ADDRA[0]); + buf b_addra_1 (addra_int[1], ADDRA[1]); + buf b_addra_2 (addra_int[2], ADDRA[2]); + buf b_addra_3 (addra_int[3], ADDRA[3]); + buf b_addra_4 (addra_int[4], ADDRA[4]); + buf b_addra_5 (addra_int[5], ADDRA[5]); + buf b_addra_6 (addra_int[6], ADDRA[6]); + buf b_addra_7 (addra_int[7], ADDRA[7]); + buf b_addra_8 (addra_int[8], ADDRA[8]); + buf b_addra_9 (addra_int[9], ADDRA[9]); + buf b_addra_10 (addra_int[10], ADDRA[10]); + buf b_addra_11 (addra_int[11], ADDRA[11]); + buf b_addra_12 (addra_int[12], ADDRA[12]); + buf b_addra_13 (addra_int[13], ADDRA[13]); + buf b_dia_0 (dia_int[0], DIA[0]); + buf b_ena (ena_int, ENA); + buf b_clka (clka_int, CLKA); + buf b_ssra (ssra_int, SSRA); + buf b_wea (wea_int, WEA); + buf b_addrb_0 (addrb_int[0], ADDRB[0]); + buf b_addrb_1 (addrb_int[1], ADDRB[1]); + buf b_addrb_2 (addrb_int[2], ADDRB[2]); + buf b_addrb_3 (addrb_int[3], ADDRB[3]); + buf b_addrb_4 (addrb_int[4], ADDRB[4]); + buf b_addrb_5 (addrb_int[5], ADDRB[5]); + buf b_addrb_6 (addrb_int[6], ADDRB[6]); + buf b_addrb_7 (addrb_int[7], ADDRB[7]); + buf b_addrb_8 (addrb_int[8], ADDRB[8]); + buf b_dib_0 (dib_int[0], DIB[0]); + buf b_dib_1 (dib_int[1], DIB[1]); + buf b_dib_2 (dib_int[2], DIB[2]); + buf b_dib_3 (dib_int[3], DIB[3]); + buf b_dib_4 (dib_int[4], DIB[4]); + buf b_dib_5 (dib_int[5], DIB[5]); + buf b_dib_6 (dib_int[6], DIB[6]); + buf b_dib_7 (dib_int[7], DIB[7]); + buf b_dib_8 (dib_int[8], DIB[8]); + buf b_dib_9 (dib_int[9], DIB[9]); + buf b_dib_10 (dib_int[10], DIB[10]); + buf b_dib_11 (dib_int[11], DIB[11]); + buf b_dib_12 (dib_int[12], DIB[12]); + buf b_dib_13 (dib_int[13], DIB[13]); + buf b_dib_14 (dib_int[14], DIB[14]); + buf b_dib_15 (dib_int[15], DIB[15]); + buf b_dib_16 (dib_int[16], DIB[16]); + buf b_dib_17 (dib_int[17], DIB[17]); + buf b_dib_18 (dib_int[18], DIB[18]); + buf b_dib_19 (dib_int[19], DIB[19]); + buf b_dib_20 (dib_int[20], DIB[20]); + buf b_dib_21 (dib_int[21], DIB[21]); + buf b_dib_22 (dib_int[22], DIB[22]); + buf b_dib_23 (dib_int[23], DIB[23]); + buf b_dib_24 (dib_int[24], DIB[24]); + buf b_dib_25 (dib_int[25], DIB[25]); + buf b_dib_26 (dib_int[26], DIB[26]); + buf b_dib_27 (dib_int[27], DIB[27]); + buf b_dib_28 (dib_int[28], DIB[28]); + buf b_dib_29 (dib_int[29], DIB[29]); + buf b_dib_30 (dib_int[30], DIB[30]); + buf b_dib_31 (dib_int[31], DIB[31]); + buf b_dipb_0 (dipb_int[0], DIPB[0]); + buf b_dipb_1 (dipb_int[1], DIPB[1]); + buf b_dipb_2 (dipb_int[2], DIPB[2]); + buf b_dipb_3 (dipb_int[3], DIPB[3]); + buf b_enb (enb_int, ENB); + buf b_clkb (clkb_int, CLKB); + buf b_ssrb (ssrb_int, SSRB); + buf b_web (web_int, WEB); + + initial begin + for (count = 0; count < 256; count = count + 1) begin + mem[count] <= INIT_00[count]; + mem[256 * 1 + count] <= INIT_01[count]; + mem[256 * 2 + count] <= INIT_02[count]; + mem[256 * 3 + count] <= INIT_03[count]; + mem[256 * 4 + count] <= INIT_04[count]; + mem[256 * 5 + count] <= INIT_05[count]; + mem[256 * 6 + count] <= INIT_06[count]; + mem[256 * 7 + count] <= INIT_07[count]; + mem[256 * 8 + count] <= INIT_08[count]; + mem[256 * 9 + count] <= INIT_09[count]; + mem[256 * 10 + count] <= INIT_0A[count]; + mem[256 * 11 + count] <= INIT_0B[count]; + mem[256 * 12 + count] <= INIT_0C[count]; + mem[256 * 13 + count] <= INIT_0D[count]; + mem[256 * 14 + count] <= INIT_0E[count]; + mem[256 * 15 + count] <= INIT_0F[count]; + mem[256 * 16 + count] <= INIT_10[count]; + mem[256 * 17 + count] <= INIT_11[count]; + mem[256 * 18 + count] <= INIT_12[count]; + mem[256 * 19 + count] <= INIT_13[count]; + mem[256 * 20 + count] <= INIT_14[count]; + mem[256 * 21 + count] <= INIT_15[count]; + mem[256 * 22 + count] <= INIT_16[count]; + mem[256 * 23 + count] <= INIT_17[count]; + mem[256 * 24 + count] <= INIT_18[count]; + mem[256 * 25 + count] <= INIT_19[count]; + mem[256 * 26 + count] <= INIT_1A[count]; + mem[256 * 27 + count] <= INIT_1B[count]; + mem[256 * 28 + count] <= INIT_1C[count]; + mem[256 * 29 + count] <= INIT_1D[count]; + mem[256 * 30 + count] <= INIT_1E[count]; + mem[256 * 31 + count] <= INIT_1F[count]; + mem[256 * 32 + count] <= INIT_20[count]; + mem[256 * 33 + count] <= INIT_21[count]; + mem[256 * 34 + count] <= INIT_22[count]; + mem[256 * 35 + count] <= INIT_23[count]; + mem[256 * 36 + count] <= INIT_24[count]; + mem[256 * 37 + count] <= INIT_25[count]; + mem[256 * 38 + count] <= INIT_26[count]; + mem[256 * 39 + count] <= INIT_27[count]; + mem[256 * 40 + count] <= INIT_28[count]; + mem[256 * 41 + count] <= INIT_29[count]; + mem[256 * 42 + count] <= INIT_2A[count]; + mem[256 * 43 + count] <= INIT_2B[count]; + mem[256 * 44 + count] <= INIT_2C[count]; + mem[256 * 45 + count] <= INIT_2D[count]; + mem[256 * 46 + count] <= INIT_2E[count]; + mem[256 * 47 + count] <= INIT_2F[count]; + mem[256 * 48 + count] <= INIT_30[count]; + mem[256 * 49 + count] <= INIT_31[count]; + mem[256 * 50 + count] <= INIT_32[count]; + mem[256 * 51 + count] <= INIT_33[count]; + mem[256 * 52 + count] <= INIT_34[count]; + mem[256 * 53 + count] <= INIT_35[count]; + mem[256 * 54 + count] <= INIT_36[count]; + mem[256 * 55 + count] <= INIT_37[count]; + mem[256 * 56 + count] <= INIT_38[count]; + mem[256 * 57 + count] <= INIT_39[count]; + mem[256 * 58 + count] <= INIT_3A[count]; + mem[256 * 59 + count] <= INIT_3B[count]; + mem[256 * 60 + count] <= INIT_3C[count]; + mem[256 * 61 + count] <= INIT_3D[count]; + mem[256 * 62 + count] <= INIT_3E[count]; + mem[256 * 63 + count] <= INIT_3F[count]; + mem[256 * 64 + count] <= INITP_00[count]; + mem[256 * 65 + count] <= INITP_01[count]; + mem[256 * 66 + count] <= INITP_02[count]; + mem[256 * 67 + count] <= INITP_03[count]; + mem[256 * 68 + count] <= INITP_04[count]; + mem[256 * 69 + count] <= INITP_05[count]; + mem[256 * 70 + count] <= INITP_06[count]; + mem[256 * 71 + count] <= INITP_07[count]; + end + address_collision <= 0; + address_collision_a_b <= 0; + address_collision_b_a <= 0; + change_clka <= 0; + change_clkb <= 0; + data_collision <= 0; + data_collision_a_b <= 0; + data_collision_b_a <= 0; + memory_collision <= 0; + memory_collision_a_b <= 0; + memory_collision_b_a <= 0; + setup_all_a_b <= 0; + setup_all_b_a <= 0; + setup_zero <= 0; + setup_rf_a_b <= 0; + setup_rf_b_a <= 0; + end + + assign data_addra_int = addra_int * 1; + assign data_addra_reg = addra_reg * 1; + assign data_addrb_int = addrb_int * 32; + assign data_addrb_reg = addrb_reg * 32; + assign parity_addrb_int = 16384 + addrb_int * 4; + assign parity_addrb_reg = 16384 + addrb_reg * 4; + + + initial begin + + display_flag = 1; + + case (SIM_COLLISION_CHECK) + + "NONE" : begin + assign setup_all_a_b = 1'b0; + assign setup_all_b_a = 1'b0; + assign setup_zero = 1'b0; + assign setup_rf_a_b = 1'b0; + assign setup_rf_b_a = 1'b0; + assign display_flag = 0; + end + "WARNING_ONLY" : begin + assign data_collision = 2'b00; + assign data_collision_a_b = 2'b00; + assign data_collision_b_a = 2'b00; + assign memory_collision = 1'b0; + assign memory_collision_a_b = 1'b0; + assign memory_collision_b_a = 1'b0; + end + "GENERATE_X_ONLY" : begin + assign display_flag = 0; + end + "ALL" : ; + default : begin + $display("Attribute Syntax Error : The Attribute SIM_COLLISION_CHECK on RAMB16_S1_S36 instance %m is set to %s. Legal values for this attribute are ALL, NONE, WARNING_ONLY or GENERATE_X_ONLY.", SIM_COLLISION_CHECK); + $finish; + end + + endcase // case(SIM_COLLISION_CHECK) + + end // initial begin + + + always @(posedge clka_int) begin + time_clka = $time; + #0 time_clkb_clka = time_clka - time_clkb; + change_clka = ~change_clka; + end + + always @(posedge clkb_int) begin + time_clkb = $time; + #0 time_clka_clkb = time_clkb - time_clka; + change_clkb = ~change_clkb; + end + + always @(change_clkb) begin + if ((0 < time_clka_clkb) && (time_clka_clkb < SETUP_ALL)) + setup_all_a_b = 1; + if ((0 < time_clka_clkb) && (time_clka_clkb < SETUP_READ_FIRST)) + setup_rf_a_b = 1; + end + + always @(change_clka) begin + if ((0 < time_clkb_clka) && (time_clkb_clka < SETUP_ALL)) + setup_all_b_a = 1; + if ((0 < time_clkb_clka) && (time_clkb_clka < SETUP_READ_FIRST)) + setup_rf_b_a = 1; + end + + always @(change_clkb or change_clka) begin + if ((time_clkb_clka == 0) && (time_clka_clkb == 0)) + setup_zero = 1; + end + + always @(posedge setup_zero) begin + if ((ena_int == 1) && (wea_int == 1) && + (enb_int == 1) && (web_int == 1) && + (data_addra_int[14:5] == data_addrb_int[14:5])) + memory_collision <= 1; + end + + always @(posedge setup_all_a_b or posedge setup_rf_a_b) begin + if ((ena_reg == 1) && (wea_reg == 1) && + (enb_int == 1) && (web_int == 1) && + (data_addra_reg[14:5] == data_addrb_int[14:5])) + memory_collision_a_b <= 1; + end + + always @(posedge setup_all_b_a or posedge setup_rf_b_a) begin + if ((ena_int == 1) && (wea_int == 1) && + (enb_reg == 1) && (web_reg == 1) && + (data_addra_int[14:5] == data_addrb_reg[14:5])) + memory_collision_b_a <= 1; + end + + always @(posedge setup_all_a_b) begin + if (data_addra_reg[14:5] == data_addrb_int[14:5]) begin + if ((ena_reg == 1) && (enb_int == 1)) begin + case ({wr_mode_a, wr_mode_b, wea_reg, web_int}) + 6'b000011 : begin data_collision_a_b <= 2'b11; display_wa_wb; end + 6'b000111 : begin data_collision_a_b <= 2'b11; display_wa_wb; end + 6'b001011 : begin data_collision_a_b <= 2'b10; display_wa_wb; end +// 6'b010011 : begin data_collision_a_b <= 2'b00; display_wa_wb; end +// 6'b010111 : begin data_collision_a_b <= 2'b00; display_wa_wb; end +// 6'b011011 : begin data_collision_a_b <= 2'b00; display_wa_wb; end + 6'b100011 : begin data_collision_a_b <= 2'b01; display_wa_wb; end + 6'b100111 : begin data_collision_a_b <= 2'b01; display_wa_wb; end + 6'b101011 : begin display_wa_wb; end + 6'b000001 : begin data_collision_a_b <= 2'b10; display_ra_wb; end +// 6'b000101 : begin data_collision_a_b <= 2'b00; display_ra_wb; end + 6'b001001 : begin data_collision_a_b <= 2'b10; display_ra_wb; end + 6'b010001 : begin data_collision_a_b <= 2'b10; display_ra_wb; end +// 6'b010101 : begin data_collision_a_b <= 2'b00; display_ra_wb; end + 6'b011001 : begin data_collision_a_b <= 2'b10; display_ra_wb; end + 6'b100001 : begin data_collision_a_b <= 2'b10; display_ra_wb; end +// 6'b100101 : begin data_collision_a_b <= 2'b00; display_ra_wb; end + 6'b101001 : begin data_collision_a_b <= 2'b10; display_ra_wb; end + 6'b000010 : begin data_collision_a_b <= 2'b01; display_wa_rb; end + 6'b000110 : begin data_collision_a_b <= 2'b01; display_wa_rb; end + 6'b001010 : begin data_collision_a_b <= 2'b01; display_wa_rb; end +// 6'b010010 : begin data_collision_a_b <= 2'b00; display_wa_rb; end +// 6'b010110 : begin data_collision_a_b <= 2'b00; display_wa_rb; end +// 6'b011010 : begin data_collision_a_b <= 2'b00; display_wa_rb; end + 6'b100010 : begin data_collision_a_b <= 2'b01; display_wa_rb; end + 6'b100110 : begin data_collision_a_b <= 2'b01; display_wa_rb; end + 6'b101010 : begin data_collision_a_b <= 2'b01; display_wa_rb; end + endcase + end + end + setup_all_a_b <= 0; + end + + + always @(posedge setup_all_b_a) begin + if (data_addra_int[14:5] == data_addrb_reg[14:5]) begin + if ((ena_int == 1) && (enb_reg == 1)) begin + case ({wr_mode_a, wr_mode_b, wea_int, web_reg}) + 6'b000011 : begin data_collision_b_a <= 2'b11; display_wa_wb; end +// 6'b000111 : begin data_collision_b_a <= 2'b00; display_wa_wb; end + 6'b001011 : begin data_collision_b_a <= 2'b10; display_wa_wb; end + 6'b010011 : begin data_collision_b_a <= 2'b11; display_wa_wb; end +// 6'b010111 : begin data_collision_b_a <= 2'b00; display_wa_wb; end + 6'b011011 : begin data_collision_b_a <= 2'b10; display_wa_wb; end + 6'b100011 : begin data_collision_b_a <= 2'b01; display_wa_wb; end + 6'b100111 : begin data_collision_b_a <= 2'b01; display_wa_wb; end + 6'b101011 : begin display_wa_wb; end + 6'b000001 : begin data_collision_b_a <= 2'b10; display_ra_wb; end + 6'b000101 : begin data_collision_b_a <= 2'b10; display_ra_wb; end + 6'b001001 : begin data_collision_b_a <= 2'b10; display_ra_wb; end + 6'b010001 : begin data_collision_b_a <= 2'b10; display_ra_wb; end + 6'b010101 : begin data_collision_b_a <= 2'b10; display_ra_wb; end + 6'b011001 : begin data_collision_b_a <= 2'b10; display_ra_wb; end + 6'b100001 : begin data_collision_b_a <= 2'b10; display_ra_wb; end + 6'b100101 : begin data_collision_b_a <= 2'b10; display_ra_wb; end + 6'b101001 : begin data_collision_b_a <= 2'b10; display_ra_wb; end + 6'b000010 : begin data_collision_b_a <= 2'b01; display_wa_rb; end + 6'b000110 : begin data_collision_b_a <= 2'b01; display_wa_rb; end + 6'b001010 : begin data_collision_b_a <= 2'b01; display_wa_rb; end +// 6'b010010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end +// 6'b010110 : begin data_collision_b_a <= 2'b00; display_wa_rb; end +// 6'b011010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end + 6'b100010 : begin data_collision_b_a <= 2'b01; display_wa_rb; end + 6'b100110 : begin data_collision_b_a <= 2'b01; display_wa_rb; end + 6'b101010 : begin data_collision_b_a <= 2'b01; display_wa_rb; end + endcase + end + end + setup_all_b_a <= 0; + end + + + always @(posedge setup_zero) begin + if (data_addra_int[14:5] == data_addrb_int[14:5]) begin + if ((ena_int == 1) && (enb_int == 1)) begin + case ({wr_mode_a, wr_mode_b, wea_int, web_int}) + 6'b000011 : begin data_collision <= 2'b11; display_wa_wb; end + 6'b000111 : begin data_collision <= 2'b11; display_wa_wb; end + 6'b001011 : begin data_collision <= 2'b10; display_wa_wb; end + 6'b010011 : begin data_collision <= 2'b11; display_wa_wb; end + 6'b010111 : begin data_collision <= 2'b11; display_wa_wb; end + 6'b011011 : begin data_collision <= 2'b10; display_wa_wb; end + 6'b100011 : begin data_collision <= 2'b01; display_wa_wb; end + 6'b100111 : begin data_collision <= 2'b01; display_wa_wb; end + 6'b101011 : begin display_wa_wb; end + 6'b000001 : begin data_collision <= 2'b10; display_ra_wb; end +// 6'b000101 : begin data_collision <= 2'b00; display_ra_wb; end + 6'b001001 : begin data_collision <= 2'b10; display_ra_wb; end + 6'b010001 : begin data_collision <= 2'b10; display_ra_wb; end +// 6'b010101 : begin data_collision <= 2'b00; display_ra_wb; end + 6'b011001 : begin data_collision <= 2'b10; display_ra_wb; end + 6'b100001 : begin data_collision <= 2'b10; display_ra_wb; end +// 6'b100101 : begin data_collision <= 2'b00; display_ra_wb; end + 6'b101001 : begin data_collision <= 2'b10; display_ra_wb; end + 6'b000010 : begin data_collision <= 2'b01; display_wa_rb; end + 6'b000110 : begin data_collision <= 2'b01; display_wa_rb; end + 6'b001010 : begin data_collision <= 2'b01; display_wa_rb; end +// 6'b010010 : begin data_collision <= 2'b00; display_wa_rb; end +// 6'b010110 : begin data_collision <= 2'b00; display_wa_rb; end +// 6'b011010 : begin data_collision <= 2'b00; display_wa_rb; end + 6'b100010 : begin data_collision <= 2'b01; display_wa_rb; end + 6'b100110 : begin data_collision <= 2'b01; display_wa_rb; end + 6'b101010 : begin data_collision <= 2'b01; display_wa_rb; end + endcase + end + end + setup_zero <= 0; + end + + task display_ra_wb; + begin + if (display_flag) + $display("Memory Collision Error on RAMB16_S1_S36:%m at simulation time %.3f ns\nA read was performed on address %h (hex) of Port A while a write was requested to the same address on Port B. The write will be successful however the read value on Port A is unknown until the next CLKA cycle.", $time/1000.0, addra_int); + end + endtask + + task display_wa_rb; + begin + if (display_flag) + $display("Memory Collision Error on RAMB16_S1_S36:%m at simulation time %.3f ns\nA read was performed on address %h (hex) of Port B while a write was requested to the same address on Port A. The write will be successful however the read value on Port B is unknown until the next CLKB cycle.", $time/1000.0, addrb_int); + end + endtask + + task display_wa_wb; + begin + if (display_flag) + $display("Memory Collision Error on RAMB16_S1_S36:%m at simulation time %.3f ns\nA write was requested to the same address simultaneously at both Port A and Port B of the RAM. The contents written to the RAM at address location %h (hex) of Port A and address location %h (hex) of Port B are unknown.", $time/1000.0, addra_int, addrb_int); + end + endtask + + + always @(posedge setup_rf_a_b) begin + if (data_addra_reg[14:5] == data_addrb_int[14:5]) begin + if ((ena_reg == 1) && (enb_int == 1)) begin + case ({wr_mode_a, wr_mode_b, wea_reg, web_int}) +// 6'b000011 : begin data_collision_a_b <= 2'b00; display_wa_wb; end +// 6'b000111 : begin data_collision_a_b <= 2'b00; display_wa_wb; end +// 6'b001011 : begin data_collision_a_b <= 2'b00; display_wa_wb; end + 6'b010011 : begin data_collision_a_b <= 2'b11; display_wa_wb; end + 6'b010111 : begin data_collision_a_b <= 2'b11; display_wa_wb; end + 6'b011011 : begin data_collision_a_b <= 2'b10; display_wa_wb; end +// 6'b100011 : begin data_collision_a_b <= 2'b00; display_wa_wb; end +// 6'b100111 : begin data_collision_a_b <= 2'b00; display_wa_wb; end +// 6'b101011 : begin data_collision_a_b <= 2'b00; display_wa_wb; end +// 6'b000001 : begin data_collision_a_b <= 2'b00; display_ra_wb; end +// 6'b000101 : begin data_collision_a_b <= 2'b00; display_ra_wb; end +// 6'b001001 : begin data_collision_a_b <= 2'b00; display_ra_wb; end +// 6'b010001 : begin data_collision_a_b <= 2'b00; display_ra_wb; end +// 6'b010101 : begin data_collision_a_b <= 2'b00; display_ra_wb; end +// 6'b011001 : begin data_collision_a_b <= 2'b00; display_ra_wb; end +// 6'b100001 : begin data_collision_a_b <= 2'b00; display_ra_wb; end +// 6'b100101 : begin data_collision_a_b <= 2'b00; display_ra_wb; end +// 6'b101001 : begin data_collision_a_b <= 2'b00; display_ra_wb; end +// 6'b000010 : begin data_collision_a_b <= 2'b00; display_wa_rb; end +// 6'b000110 : begin data_collision_a_b <= 2'b00; display_wa_rb; end +// 6'b001010 : begin data_collision_a_b <= 2'b00; display_wa_rb; end + 6'b010010 : begin data_collision_a_b <= 2'b01; display_wa_rb; end + 6'b010110 : begin data_collision_a_b <= 2'b01; display_wa_rb; end + 6'b011010 : begin data_collision_a_b <= 2'b01; display_wa_rb; end +// 6'b100010 : begin data_collision_a_b <= 2'b00; display_wa_rb; end +// 6'b100110 : begin data_collision_a_b <= 2'b00; display_wa_rb; end +// 6'b101010 : begin data_collision_a_b <= 2'b00; display_wa_rb; end + endcase + end + end + setup_rf_a_b <= 0; + end + + + always @(posedge setup_rf_b_a) begin + if (data_addra_int[14:5] == data_addrb_reg[14:5]) begin + if ((ena_int == 1) && (enb_reg == 1)) begin + case ({wr_mode_a, wr_mode_b, wea_int, web_reg}) +// 6'b000011 : begin data_collision_b_a <= 2'b00; display_wa_wb; end + 6'b000111 : begin data_collision_b_a <= 2'b11; display_wa_wb; end +// 6'b001011 : begin data_collision_b_a <= 2'b00; display_wa_wb; end +// 6'b010011 : begin data_collision_b_a <= 2'b00; display_wa_wb; end + 6'b010111 : begin data_collision_b_a <= 2'b11; display_wa_wb; end +// 6'b011011 : begin data_collision_b_a <= 2'b00; display_wa_wb; end +// 6'b100011 : begin data_collision_b_a <= 2'b00; display_wa_wb; end + 6'b100111 : begin data_collision_b_a <= 2'b01; display_wa_wb; end +// 6'b101011 : begin data_collision_b_a <= 2'b00; display_wa_wb; end +// 6'b000001 : begin data_collision_b_a <= 2'b00; display_ra_wb; end + 6'b000101 : begin data_collision_b_a <= 2'b10; display_ra_wb; end +// 6'b001001 : begin data_collision_b_a <= 2'b00; display_ra_wb; end +// 6'b010001 : begin data_collision_b_a <= 2'b00; display_ra_wb; end + 6'b010101 : begin data_collision_b_a <= 2'b10; display_ra_wb; end +// 6'b011001 : begin data_collision_b_a <= 2'b00; display_ra_wb; end +// 6'b100001 : begin data_collision_b_a <= 2'b00; display_ra_wb; end + 6'b100101 : begin data_collision_b_a <= 2'b10; display_ra_wb; end +// 6'b101001 : begin data_collision_b_a <= 2'b00; display_ra_wb; end +// 6'b000010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end +// 6'b000110 : begin data_collision_b_a <= 2'b00; display_wa_rb; end +// 6'b001010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end +// 6'b010010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end +// 6'b010110 : begin data_collision_b_a <= 2'b00; display_wa_rb; end +// 6'b011010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end +// 6'b100010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end +// 6'b100110 : begin data_collision_b_a <= 2'b00; display_wa_rb; end +// 6'b101010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end + endcase + end + end + setup_rf_b_a <= 0; + end + + + always @(posedge clka_int) begin + addra_reg <= addra_int; + ena_reg <= ena_int; + ssra_reg <= ssra_int; + wea_reg <= wea_int; + end + + always @(posedge clkb_int) begin + addrb_reg <= addrb_int; + enb_reg <= enb_int; + ssrb_reg <= ssrb_int; + web_reg <= web_int; + end + + // Data + always @(posedge memory_collision) begin + for (dmi = 0; dmi < 1; dmi = dmi + 1) begin + mem[data_addra_int + dmi] <= 1'bX; + end + memory_collision <= 0; + end + + always @(posedge memory_collision_a_b) begin + for (dmi = 0; dmi < 1; dmi = dmi + 1) begin + mem[data_addra_reg + dmi] <= 1'bX; + end + memory_collision_a_b <= 0; + end + + always @(posedge memory_collision_b_a) begin + for (dmi = 0; dmi < 1; dmi = dmi + 1) begin + mem[data_addra_int + dmi] <= 1'bX; + end + memory_collision_b_a <= 0; + end + + always @(posedge data_collision[1]) begin + if (ssra_int == 0) begin + doa_out <= 1'bX; + end + data_collision[1] <= 0; + end + + always @(posedge data_collision[0]) begin + if (ssrb_int == 0) begin + for (dbi = 0; dbi < 1; dbi = dbi + 1) begin + dob_out[data_addra_int[4 : 0] + dbi] <= 1'bX; + end + end + data_collision[0] <= 0; + end + + always @(posedge data_collision_a_b[1]) begin + if (ssra_reg == 0) begin + doa_out <= 1'bX; + end + data_collision_a_b[1] <= 0; + end + + always @(posedge data_collision_a_b[0]) begin + if (ssrb_int == 0) begin + for (dbi = 0; dbi < 1; dbi = dbi + 1) begin + dob_out[data_addra_reg[4 : 0] + dbi] <= 1'bX; + end + end + data_collision_a_b[0] <= 0; + end + + always @(posedge data_collision_b_a[1]) begin + if (ssra_int == 0) begin + doa_out <= 1'bX; + end + data_collision_b_a[1] <= 0; + end + + always @(posedge data_collision_b_a[0]) begin + if (ssrb_reg == 0) begin + for (dbi = 0; dbi < 1; dbi = dbi + 1) begin + dob_out[data_addra_int[4 : 0] + dbi] <= 1'bX; + end + end + data_collision_b_a[0] <= 0; + end + + + initial begin + case (WRITE_MODE_A) + "WRITE_FIRST" : wr_mode_a <= 2'b00; + "READ_FIRST" : wr_mode_a <= 2'b01; + "NO_CHANGE" : wr_mode_a <= 2'b10; + default : begin + $display("Attribute Syntax Error : The Attribute WRITE_MODE_A on RAMB16_S1_S36 instance %m is set to %s. Legal values for this attribute are WRITE_FIRST, READ_FIRST or NO_CHANGE.", WRITE_MODE_A); + $finish; + end + endcase + end + + initial begin + case (WRITE_MODE_B) + "WRITE_FIRST" : wr_mode_b <= 2'b00; + "READ_FIRST" : wr_mode_b <= 2'b01; + "NO_CHANGE" : wr_mode_b <= 2'b10; + default : begin + $display("Attribute Syntax Error : The Attribute WRITE_MODE_B on RAMB16_S1_S36 instance %m is set to %s. Legal values for this attribute are WRITE_FIRST, READ_FIRST or NO_CHANGE.", WRITE_MODE_B); + $finish; + end + endcase + end + + // Port A + always @(posedge clka_int) begin + if (ena_int == 1'b1) begin + if (ssra_int == 1'b1) begin + doa_out[0] <= SRVAL_A[0]; + end + else begin + if (wea_int == 1'b1) begin + if (wr_mode_a == 2'b00) begin + doa_out <= dia_int; + end + else if (wr_mode_a == 2'b01) begin + doa_out[0] <= mem[data_addra_int + 0]; + end + end + else begin + doa_out[0] <= mem[data_addra_int + 0]; + end + end + end + end + + always @(posedge clka_int) begin + if (ena_int == 1'b1 && wea_int == 1'b1) begin + mem[data_addra_int + 0] <= dia_int[0]; + end + end + + // Port B + always @(posedge clkb_int) begin + if (enb_int == 1'b1) begin + if (ssrb_int == 1'b1) begin + dob_out[0] <= SRVAL_B[0]; + dob_out[1] <= SRVAL_B[1]; + dob_out[2] <= SRVAL_B[2]; + dob_out[3] <= SRVAL_B[3]; + dob_out[4] <= SRVAL_B[4]; + dob_out[5] <= SRVAL_B[5]; + dob_out[6] <= SRVAL_B[6]; + dob_out[7] <= SRVAL_B[7]; + dob_out[8] <= SRVAL_B[8]; + dob_out[9] <= SRVAL_B[9]; + dob_out[10] <= SRVAL_B[10]; + dob_out[11] <= SRVAL_B[11]; + dob_out[12] <= SRVAL_B[12]; + dob_out[13] <= SRVAL_B[13]; + dob_out[14] <= SRVAL_B[14]; + dob_out[15] <= SRVAL_B[15]; + dob_out[16] <= SRVAL_B[16]; + dob_out[17] <= SRVAL_B[17]; + dob_out[18] <= SRVAL_B[18]; + dob_out[19] <= SRVAL_B[19]; + dob_out[20] <= SRVAL_B[20]; + dob_out[21] <= SRVAL_B[21]; + dob_out[22] <= SRVAL_B[22]; + dob_out[23] <= SRVAL_B[23]; + dob_out[24] <= SRVAL_B[24]; + dob_out[25] <= SRVAL_B[25]; + dob_out[26] <= SRVAL_B[26]; + dob_out[27] <= SRVAL_B[27]; + dob_out[28] <= SRVAL_B[28]; + dob_out[29] <= SRVAL_B[29]; + dob_out[30] <= SRVAL_B[30]; + dob_out[31] <= SRVAL_B[31]; + dopb_out[0] <= SRVAL_B[32]; + dopb_out[1] <= SRVAL_B[33]; + dopb_out[2] <= SRVAL_B[34]; + dopb_out[3] <= SRVAL_B[35]; + end + else begin + if (web_int == 1'b1) begin + if (wr_mode_b == 2'b00) begin + dob_out <= dib_int; + dopb_out <= dipb_int; + end + else if (wr_mode_b == 2'b01) begin + dob_out[0] <= mem[data_addrb_int + 0]; + dob_out[1] <= mem[data_addrb_int + 1]; + dob_out[2] <= mem[data_addrb_int + 2]; + dob_out[3] <= mem[data_addrb_int + 3]; + dob_out[4] <= mem[data_addrb_int + 4]; + dob_out[5] <= mem[data_addrb_int + 5]; + dob_out[6] <= mem[data_addrb_int + 6]; + dob_out[7] <= mem[data_addrb_int + 7]; + dob_out[8] <= mem[data_addrb_int + 8]; + dob_out[9] <= mem[data_addrb_int + 9]; + dob_out[10] <= mem[data_addrb_int + 10]; + dob_out[11] <= mem[data_addrb_int + 11]; + dob_out[12] <= mem[data_addrb_int + 12]; + dob_out[13] <= mem[data_addrb_int + 13]; + dob_out[14] <= mem[data_addrb_int + 14]; + dob_out[15] <= mem[data_addrb_int + 15]; + dob_out[16] <= mem[data_addrb_int + 16]; + dob_out[17] <= mem[data_addrb_int + 17]; + dob_out[18] <= mem[data_addrb_int + 18]; + dob_out[19] <= mem[data_addrb_int + 19]; + dob_out[20] <= mem[data_addrb_int + 20]; + dob_out[21] <= mem[data_addrb_int + 21]; + dob_out[22] <= mem[data_addrb_int + 22]; + dob_out[23] <= mem[data_addrb_int + 23]; + dob_out[24] <= mem[data_addrb_int + 24]; + dob_out[25] <= mem[data_addrb_int + 25]; + dob_out[26] <= mem[data_addrb_int + 26]; + dob_out[27] <= mem[data_addrb_int + 27]; + dob_out[28] <= mem[data_addrb_int + 28]; + dob_out[29] <= mem[data_addrb_int + 29]; + dob_out[30] <= mem[data_addrb_int + 30]; + dob_out[31] <= mem[data_addrb_int + 31]; + dopb_out[0] <= mem[parity_addrb_int + 0]; + dopb_out[1] <= mem[parity_addrb_int + 1]; + dopb_out[2] <= mem[parity_addrb_int + 2]; + dopb_out[3] <= mem[parity_addrb_int + 3]; + end + end + else begin + dob_out[0] <= mem[data_addrb_int + 0]; + dob_out[1] <= mem[data_addrb_int + 1]; + dob_out[2] <= mem[data_addrb_int + 2]; + dob_out[3] <= mem[data_addrb_int + 3]; + dob_out[4] <= mem[data_addrb_int + 4]; + dob_out[5] <= mem[data_addrb_int + 5]; + dob_out[6] <= mem[data_addrb_int + 6]; + dob_out[7] <= mem[data_addrb_int + 7]; + dob_out[8] <= mem[data_addrb_int + 8]; + dob_out[9] <= mem[data_addrb_int + 9]; + dob_out[10] <= mem[data_addrb_int + 10]; + dob_out[11] <= mem[data_addrb_int + 11]; + dob_out[12] <= mem[data_addrb_int + 12]; + dob_out[13] <= mem[data_addrb_int + 13]; + dob_out[14] <= mem[data_addrb_int + 14]; + dob_out[15] <= mem[data_addrb_int + 15]; + dob_out[16] <= mem[data_addrb_int + 16]; + dob_out[17] <= mem[data_addrb_int + 17]; + dob_out[18] <= mem[data_addrb_int + 18]; + dob_out[19] <= mem[data_addrb_int + 19]; + dob_out[20] <= mem[data_addrb_int + 20]; + dob_out[21] <= mem[data_addrb_int + 21]; + dob_out[22] <= mem[data_addrb_int + 22]; + dob_out[23] <= mem[data_addrb_int + 23]; + dob_out[24] <= mem[data_addrb_int + 24]; + dob_out[25] <= mem[data_addrb_int + 25]; + dob_out[26] <= mem[data_addrb_int + 26]; + dob_out[27] <= mem[data_addrb_int + 27]; + dob_out[28] <= mem[data_addrb_int + 28]; + dob_out[29] <= mem[data_addrb_int + 29]; + dob_out[30] <= mem[data_addrb_int + 30]; + dob_out[31] <= mem[data_addrb_int + 31]; + dopb_out[0] <= mem[parity_addrb_int + 0]; + dopb_out[1] <= mem[parity_addrb_int + 1]; + dopb_out[2] <= mem[parity_addrb_int + 2]; + dopb_out[3] <= mem[parity_addrb_int + 3]; + end + end + end + end + + always @(posedge clkb_int) begin + if (enb_int == 1'b1 && web_int == 1'b1) begin + mem[data_addrb_int + 0] <= dib_int[0]; + mem[data_addrb_int + 1] <= dib_int[1]; + mem[data_addrb_int + 2] <= dib_int[2]; + mem[data_addrb_int + 3] <= dib_int[3]; + mem[data_addrb_int + 4] <= dib_int[4]; + mem[data_addrb_int + 5] <= dib_int[5]; + mem[data_addrb_int + 6] <= dib_int[6]; + mem[data_addrb_int + 7] <= dib_int[7]; + mem[data_addrb_int + 8] <= dib_int[8]; + mem[data_addrb_int + 9] <= dib_int[9]; + mem[data_addrb_int + 10] <= dib_int[10]; + mem[data_addrb_int + 11] <= dib_int[11]; + mem[data_addrb_int + 12] <= dib_int[12]; + mem[data_addrb_int + 13] <= dib_int[13]; + mem[data_addrb_int + 14] <= dib_int[14]; + mem[data_addrb_int + 15] <= dib_int[15]; + mem[data_addrb_int + 16] <= dib_int[16]; + mem[data_addrb_int + 17] <= dib_int[17]; + mem[data_addrb_int + 18] <= dib_int[18]; + mem[data_addrb_int + 19] <= dib_int[19]; + mem[data_addrb_int + 20] <= dib_int[20]; + mem[data_addrb_int + 21] <= dib_int[21]; + mem[data_addrb_int + 22] <= dib_int[22]; + mem[data_addrb_int + 23] <= dib_int[23]; + mem[data_addrb_int + 24] <= dib_int[24]; + mem[data_addrb_int + 25] <= dib_int[25]; + mem[data_addrb_int + 26] <= dib_int[26]; + mem[data_addrb_int + 27] <= dib_int[27]; + mem[data_addrb_int + 28] <= dib_int[28]; + mem[data_addrb_int + 29] <= dib_int[29]; + mem[data_addrb_int + 30] <= dib_int[30]; + mem[data_addrb_int + 31] <= dib_int[31]; + mem[parity_addrb_int + 0] <= dipb_int[0]; + mem[parity_addrb_int + 1] <= dipb_int[1]; + mem[parity_addrb_int + 2] <= dipb_int[2]; + mem[parity_addrb_int + 3] <= dipb_int[3]; + end + end + + specify + (CLKA *> DOA) = (100, 100); + (CLKB *> DOB) = (100, 100); + (CLKB *> DOPB) = (100, 100); + endspecify + +endmodule + +`else + +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/RAMB16_S1_S36.v,v 1.10 2007/02/22 01:58:05 wloo Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2005 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Timing Simulation Library Component +// / / 16K-Bit Data and 2K-Bit Parity Dual Port Block RAM +// /___/ /\ Filename : RAMB16_S1_S36.v +// \ \ / \ Timestamp : Thu Mar 10 16:44:01 PST 2005 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 03/10/05 - Initialized outputs. +// 02/21/07 - Fixed parameter SIM_COLLISION_CHECK (CR 433281). +// End Revision + +`timescale 1 ps/1 ps + +module RAMB16_S1_S36 (DOA, DOB, DOPB, ADDRA, ADDRB, CLKA, CLKB, DIA, DIB, DIPB, ENA, ENB, SSRA, SSRB, WEA, WEB); + + parameter INIT_A = 1'h0; + parameter INIT_B = 36'h0; + parameter SRVAL_A = 1'h0; + parameter SRVAL_B = 36'h0; + parameter WRITE_MODE_A = "WRITE_FIRST"; + parameter WRITE_MODE_B = "WRITE_FIRST"; + parameter SIM_COLLISION_CHECK = "ALL"; + localparam SETUP_ALL = 1000; + localparam SETUP_READ_FIRST = 3000; + + parameter INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + + output [0:0] DOA; + output [31:0] DOB; + output [3:0] DOPB; + + input [13:0] ADDRA; + input [0:0] DIA; + input ENA, CLKA, WEA, SSRA; + input [8:0] ADDRB; + input [31:0] DIB; + input [3:0] DIPB; + input ENB, CLKB, WEB, SSRB; + + reg [0:0] doa_out = INIT_A[0:0]; + reg [31:0] dob_out = INIT_B[31:0]; + reg [3:0] dopb_out = INIT_B[35:32]; + + reg [31:0] mem [511:0]; + reg [3:0] memp [511:0]; + + reg [8:0] count, countp; + reg [1:0] wr_mode_a, wr_mode_b; + + reg [5:0] dmi, dbi; + reg [5:0] pmi, pbi; + + wire [13:0] addra_int; + reg [13:0] addra_reg; + wire [0:0] dia_int; + wire ena_int, clka_int, wea_int, ssra_int; + reg ena_reg, wea_reg, ssra_reg; + wire [8:0] addrb_int; + reg [8:0] addrb_reg; + wire [31:0] dib_int; + wire [3:0] dipb_int; + wire enb_int, clkb_int, web_int, ssrb_int; + reg display_flag, output_flag; + reg enb_reg, web_reg, ssrb_reg; + + time time_clka, time_clkb; + time time_clka_clkb; + time time_clkb_clka; + + reg setup_all_a_b; + reg setup_all_b_a; + reg setup_zero; + reg setup_rf_a_b; + reg setup_rf_b_a; + reg [1:0] data_collision, data_collision_a_b, data_collision_b_a; + reg memory_collision, memory_collision_a_b, memory_collision_b_a; + reg change_clka; + reg change_clkb; + + wire [14:0] data_addra_int; + wire [14:0] data_addra_reg; + wire [14:0] data_addrb_int; + wire [14:0] data_addrb_reg; + + wire dia_enable = ena_int && wea_int; + wire dib_enable = enb_int && web_int; + + tri0 GSR = glbl.GSR; + wire gsr_int; + + buf b_gsr (gsr_int, GSR); + + buf b_doa [0:0] (DOA, doa_out); + buf b_addra [13:0] (addra_int, ADDRA); + buf b_dia [0:0] (dia_int, DIA); + buf b_ena (ena_int, ENA); + buf b_clka (clka_int, CLKA); + buf b_ssra (ssra_int, SSRA); + buf b_wea (wea_int, WEA); + + buf b_dob [31:0] (DOB, dob_out); + buf b_dopb [3:0] (DOPB, dopb_out); + buf b_addrb [8:0] (addrb_int, ADDRB); + buf b_dib [31:0] (dib_int, DIB); + buf b_dipb [3:0] (dipb_int, DIPB); + buf b_enb (enb_int, ENB); + buf b_clkb (clkb_int, CLKB); + buf b_ssrb (ssrb_int, SSRB); + buf b_web (web_int, WEB); + + + always @(gsr_int) + if (gsr_int) begin + assign {doa_out} = INIT_A; + assign {dopb_out, dob_out} = INIT_B; + end + else begin + deassign doa_out; + deassign dob_out; + deassign dopb_out; + end + + + initial begin + + for (count = 0; count < 8; count = count + 1) begin + mem[count] = INIT_00[(count * 32) +: 32]; + mem[8 * 1 + count] = INIT_01[(count * 32) +: 32]; + mem[8 * 2 + count] = INIT_02[(count * 32) +: 32]; + mem[8 * 3 + count] = INIT_03[(count * 32) +: 32]; + mem[8 * 4 + count] = INIT_04[(count * 32) +: 32]; + mem[8 * 5 + count] = INIT_05[(count * 32) +: 32]; + mem[8 * 6 + count] = INIT_06[(count * 32) +: 32]; + mem[8 * 7 + count] = INIT_07[(count * 32) +: 32]; + mem[8 * 8 + count] = INIT_08[(count * 32) +: 32]; + mem[8 * 9 + count] = INIT_09[(count * 32) +: 32]; + mem[8 * 10 + count] = INIT_0A[(count * 32) +: 32]; + mem[8 * 11 + count] = INIT_0B[(count * 32) +: 32]; + mem[8 * 12 + count] = INIT_0C[(count * 32) +: 32]; + mem[8 * 13 + count] = INIT_0D[(count * 32) +: 32]; + mem[8 * 14 + count] = INIT_0E[(count * 32) +: 32]; + mem[8 * 15 + count] = INIT_0F[(count * 32) +: 32]; + mem[8 * 16 + count] = INIT_10[(count * 32) +: 32]; + mem[8 * 17 + count] = INIT_11[(count * 32) +: 32]; + mem[8 * 18 + count] = INIT_12[(count * 32) +: 32]; + mem[8 * 19 + count] = INIT_13[(count * 32) +: 32]; + mem[8 * 20 + count] = INIT_14[(count * 32) +: 32]; + mem[8 * 21 + count] = INIT_15[(count * 32) +: 32]; + mem[8 * 22 + count] = INIT_16[(count * 32) +: 32]; + mem[8 * 23 + count] = INIT_17[(count * 32) +: 32]; + mem[8 * 24 + count] = INIT_18[(count * 32) +: 32]; + mem[8 * 25 + count] = INIT_19[(count * 32) +: 32]; + mem[8 * 26 + count] = INIT_1A[(count * 32) +: 32]; + mem[8 * 27 + count] = INIT_1B[(count * 32) +: 32]; + mem[8 * 28 + count] = INIT_1C[(count * 32) +: 32]; + mem[8 * 29 + count] = INIT_1D[(count * 32) +: 32]; + mem[8 * 30 + count] = INIT_1E[(count * 32) +: 32]; + mem[8 * 31 + count] = INIT_1F[(count * 32) +: 32]; + mem[8 * 32 + count] = INIT_20[(count * 32) +: 32]; + mem[8 * 33 + count] = INIT_21[(count * 32) +: 32]; + mem[8 * 34 + count] = INIT_22[(count * 32) +: 32]; + mem[8 * 35 + count] = INIT_23[(count * 32) +: 32]; + mem[8 * 36 + count] = INIT_24[(count * 32) +: 32]; + mem[8 * 37 + count] = INIT_25[(count * 32) +: 32]; + mem[8 * 38 + count] = INIT_26[(count * 32) +: 32]; + mem[8 * 39 + count] = INIT_27[(count * 32) +: 32]; + mem[8 * 40 + count] = INIT_28[(count * 32) +: 32]; + mem[8 * 41 + count] = INIT_29[(count * 32) +: 32]; + mem[8 * 42 + count] = INIT_2A[(count * 32) +: 32]; + mem[8 * 43 + count] = INIT_2B[(count * 32) +: 32]; + mem[8 * 44 + count] = INIT_2C[(count * 32) +: 32]; + mem[8 * 45 + count] = INIT_2D[(count * 32) +: 32]; + mem[8 * 46 + count] = INIT_2E[(count * 32) +: 32]; + mem[8 * 47 + count] = INIT_2F[(count * 32) +: 32]; + mem[8 * 48 + count] = INIT_30[(count * 32) +: 32]; + mem[8 * 49 + count] = INIT_31[(count * 32) +: 32]; + mem[8 * 50 + count] = INIT_32[(count * 32) +: 32]; + mem[8 * 51 + count] = INIT_33[(count * 32) +: 32]; + mem[8 * 52 + count] = INIT_34[(count * 32) +: 32]; + mem[8 * 53 + count] = INIT_35[(count * 32) +: 32]; + mem[8 * 54 + count] = INIT_36[(count * 32) +: 32]; + mem[8 * 55 + count] = INIT_37[(count * 32) +: 32]; + mem[8 * 56 + count] = INIT_38[(count * 32) +: 32]; + mem[8 * 57 + count] = INIT_39[(count * 32) +: 32]; + mem[8 * 58 + count] = INIT_3A[(count * 32) +: 32]; + mem[8 * 59 + count] = INIT_3B[(count * 32) +: 32]; + mem[8 * 60 + count] = INIT_3C[(count * 32) +: 32]; + mem[8 * 61 + count] = INIT_3D[(count * 32) +: 32]; + mem[8 * 62 + count] = INIT_3E[(count * 32) +: 32]; + mem[8 * 63 + count] = INIT_3F[(count * 32) +: 32]; + end + +// initiate parity start + for (countp = 0; countp < 64; countp = countp + 1) begin + memp[countp] = INITP_00[(countp * 4) +: 4]; + memp[64 * 1 + countp] = INITP_01[(countp * 4) +: 4]; + memp[64 * 2 + countp] = INITP_02[(countp * 4) +: 4]; + memp[64 * 3 + countp] = INITP_03[(countp * 4) +: 4]; + memp[64 * 4 + countp] = INITP_04[(countp * 4) +: 4]; + memp[64 * 5 + countp] = INITP_05[(countp * 4) +: 4]; + memp[64 * 6 + countp] = INITP_06[(countp * 4) +: 4]; + memp[64 * 7 + countp] = INITP_07[(countp * 4) +: 4]; + end +// initiate parity end + + change_clka <= 0; + change_clkb <= 0; + data_collision <= 0; + data_collision_a_b <= 0; + data_collision_b_a <= 0; + memory_collision <= 0; + memory_collision_a_b <= 0; + memory_collision_b_a <= 0; + setup_all_a_b <= 0; + setup_all_b_a <= 0; + setup_zero <= 0; + setup_rf_a_b <= 0; + setup_rf_b_a <= 0; + end + + assign data_addra_int = addra_int * 1; + assign data_addra_reg = addra_reg * 1; + assign data_addrb_int = addrb_int * 32; + assign data_addrb_reg = addrb_reg * 32; + + + initial begin + + display_flag = 1; + output_flag = 1; + + case (SIM_COLLISION_CHECK) + + "NONE" : begin + output_flag = 0; + display_flag = 0; + end + "WARNING_ONLY" : output_flag = 0; + "GENERATE_X_ONLY" : display_flag = 0; + "ALL" : ; + + default : begin + $display("Attribute Syntax Error : The Attribute SIM_COLLISION_CHECK on RAMB16_S1_S36 instance %m is set to %s. Legal values for this attribute are ALL, NONE, WARNING_ONLY or GENERATE_X_ONLY.", SIM_COLLISION_CHECK); + $finish; + end + + endcase // case(SIM_COLLISION_CHECK) + + end // initial begin + + + always @(posedge clka_int) begin + if ((output_flag || display_flag)) begin + time_clka = $time; + #0 time_clkb_clka = time_clka - time_clkb; + change_clka = ~change_clka; + end + end + + always @(posedge clkb_int) begin + if ((output_flag || display_flag)) begin + time_clkb = $time; + #0 time_clka_clkb = time_clkb - time_clka; + change_clkb = ~change_clkb; + end + end + + always @(change_clkb) begin + if ((0 < time_clka_clkb) && (time_clka_clkb < SETUP_ALL)) + setup_all_a_b = 1; + if ((0 < time_clka_clkb) && (time_clka_clkb < SETUP_READ_FIRST)) + setup_rf_a_b = 1; + end + + always @(change_clka) begin + if ((0 < time_clkb_clka) && (time_clkb_clka < SETUP_ALL)) + setup_all_b_a = 1; + if ((0 < time_clkb_clka) && (time_clkb_clka < SETUP_READ_FIRST)) + setup_rf_b_a = 1; + end + + always @(change_clkb or change_clka) begin + if ((time_clkb_clka == 0) && (time_clka_clkb == 0)) + setup_zero = 1; + end + + always @(posedge setup_zero) begin + if ((ena_int == 1) && (wea_int == 1) && + (enb_int == 1) && (web_int == 1) && + (data_addra_int[14:5] == data_addrb_int[14:5])) + memory_collision <= 1; + end + + always @(posedge setup_all_a_b or posedge setup_rf_a_b) begin + if ((ena_reg == 1) && (wea_reg == 1) && + (enb_int == 1) && (web_int == 1) && + (data_addra_reg[14:5] == data_addrb_int[14:5])) + memory_collision_a_b <= 1; + end + + always @(posedge setup_all_b_a or posedge setup_rf_b_a) begin + if ((ena_int == 1) && (wea_int == 1) && + (enb_reg == 1) && (web_reg == 1) && + (data_addra_int[14:5] == data_addrb_reg[14:5])) + memory_collision_b_a <= 1; + end + + always @(posedge setup_all_a_b) begin + if (data_addra_reg[14:5] == data_addrb_int[14:5]) begin + if ((ena_reg == 1) && (enb_int == 1)) begin + case ({wr_mode_a, wr_mode_b, wea_reg, web_int}) + 6'b000011 : begin data_collision_a_b <= 2'b11; display_wa_wb; end + 6'b000111 : begin data_collision_a_b <= 2'b11; display_wa_wb; end + 6'b001011 : begin data_collision_a_b <= 2'b10; display_wa_wb; end +// 6'b010011 : begin data_collision_a_b <= 2'b00; display_wa_wb; end +// 6'b010111 : begin data_collision_a_b <= 2'b00; display_wa_wb; end +// 6'b011011 : begin data_collision_a_b <= 2'b00; display_wa_wb; end + 6'b100011 : begin data_collision_a_b <= 2'b01; display_wa_wb; end + 6'b100111 : begin data_collision_a_b <= 2'b01; display_wa_wb; end + 6'b101011 : begin display_wa_wb; end + 6'b000001 : begin data_collision_a_b <= 2'b10; display_ra_wb; end +// 6'b000101 : begin data_collision_a_b <= 2'b00; display_ra_wb; end + 6'b001001 : begin data_collision_a_b <= 2'b10; display_ra_wb; end + 6'b010001 : begin data_collision_a_b <= 2'b10; display_ra_wb; end +// 6'b010101 : begin data_collision_a_b <= 2'b00; display_ra_wb; end + 6'b011001 : begin data_collision_a_b <= 2'b10; display_ra_wb; end + 6'b100001 : begin data_collision_a_b <= 2'b10; display_ra_wb; end +// 6'b100101 : begin data_collision_a_b <= 2'b00; display_ra_wb; end + 6'b101001 : begin data_collision_a_b <= 2'b10; display_ra_wb; end + 6'b000010 : begin data_collision_a_b <= 2'b01; display_wa_rb; end + 6'b000110 : begin data_collision_a_b <= 2'b01; display_wa_rb; end + 6'b001010 : begin data_collision_a_b <= 2'b01; display_wa_rb; end +// 6'b010010 : begin data_collision_a_b <= 2'b00; display_wa_rb; end +// 6'b010110 : begin data_collision_a_b <= 2'b00; display_wa_rb; end +// 6'b011010 : begin data_collision_a_b <= 2'b00; display_wa_rb; end + 6'b100010 : begin data_collision_a_b <= 2'b01; display_wa_rb; end + 6'b100110 : begin data_collision_a_b <= 2'b01; display_wa_rb; end + 6'b101010 : begin data_collision_a_b <= 2'b01; display_wa_rb; end + endcase + end + end + setup_all_a_b <= 0; + end + + + always @(posedge setup_all_b_a) begin + if (data_addra_int[14:5] == data_addrb_reg[14:5]) begin + if ((ena_int == 1) && (enb_reg == 1)) begin + case ({wr_mode_a, wr_mode_b, wea_int, web_reg}) + 6'b000011 : begin data_collision_b_a <= 2'b11; display_wa_wb; end +// 6'b000111 : begin data_collision_b_a <= 2'b00; display_wa_wb; end + 6'b001011 : begin data_collision_b_a <= 2'b10; display_wa_wb; end + 6'b010011 : begin data_collision_b_a <= 2'b11; display_wa_wb; end +// 6'b010111 : begin data_collision_b_a <= 2'b00; display_wa_wb; end + 6'b011011 : begin data_collision_b_a <= 2'b10; display_wa_wb; end + 6'b100011 : begin data_collision_b_a <= 2'b01; display_wa_wb; end + 6'b100111 : begin data_collision_b_a <= 2'b01; display_wa_wb; end + 6'b101011 : begin display_wa_wb; end + 6'b000001 : begin data_collision_b_a <= 2'b10; display_ra_wb; end + 6'b000101 : begin data_collision_b_a <= 2'b10; display_ra_wb; end + 6'b001001 : begin data_collision_b_a <= 2'b10; display_ra_wb; end + 6'b010001 : begin data_collision_b_a <= 2'b10; display_ra_wb; end + 6'b010101 : begin data_collision_b_a <= 2'b10; display_ra_wb; end + 6'b011001 : begin data_collision_b_a <= 2'b10; display_ra_wb; end + 6'b100001 : begin data_collision_b_a <= 2'b10; display_ra_wb; end + 6'b100101 : begin data_collision_b_a <= 2'b10; display_ra_wb; end + 6'b101001 : begin data_collision_b_a <= 2'b10; display_ra_wb; end + 6'b000010 : begin data_collision_b_a <= 2'b01; display_wa_rb; end + 6'b000110 : begin data_collision_b_a <= 2'b01; display_wa_rb; end + 6'b001010 : begin data_collision_b_a <= 2'b01; display_wa_rb; end +// 6'b010010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end +// 6'b010110 : begin data_collision_b_a <= 2'b00; display_wa_rb; end +// 6'b011010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end + 6'b100010 : begin data_collision_b_a <= 2'b01; display_wa_rb; end + 6'b100110 : begin data_collision_b_a <= 2'b01; display_wa_rb; end + 6'b101010 : begin data_collision_b_a <= 2'b01; display_wa_rb; end + endcase + end + end + setup_all_b_a <= 0; + end + + + always @(posedge setup_zero) begin + if (data_addra_int[14:5] == data_addrb_int[14:5]) begin + if ((ena_int == 1) && (enb_int == 1)) begin + case ({wr_mode_a, wr_mode_b, wea_int, web_int}) + 6'b000011 : begin data_collision <= 2'b11; display_wa_wb; end + 6'b000111 : begin data_collision <= 2'b11; display_wa_wb; end + 6'b001011 : begin data_collision <= 2'b10; display_wa_wb; end + 6'b010011 : begin data_collision <= 2'b11; display_wa_wb; end + 6'b010111 : begin data_collision <= 2'b11; display_wa_wb; end + 6'b011011 : begin data_collision <= 2'b10; display_wa_wb; end + 6'b100011 : begin data_collision <= 2'b01; display_wa_wb; end + 6'b100111 : begin data_collision <= 2'b01; display_wa_wb; end + 6'b101011 : begin display_wa_wb; end + 6'b000001 : begin data_collision <= 2'b10; display_ra_wb; end +// 6'b000101 : begin data_collision <= 2'b00; display_ra_wb; end + 6'b001001 : begin data_collision <= 2'b10; display_ra_wb; end + 6'b010001 : begin data_collision <= 2'b10; display_ra_wb; end +// 6'b010101 : begin data_collision <= 2'b00; display_ra_wb; end + 6'b011001 : begin data_collision <= 2'b10; display_ra_wb; end + 6'b100001 : begin data_collision <= 2'b10; display_ra_wb; end +// 6'b100101 : begin data_collision <= 2'b00; display_ra_wb; end + 6'b101001 : begin data_collision <= 2'b10; display_ra_wb; end + 6'b000010 : begin data_collision <= 2'b01; display_wa_rb; end + 6'b000110 : begin data_collision <= 2'b01; display_wa_rb; end + 6'b001010 : begin data_collision <= 2'b01; display_wa_rb; end +// 6'b010010 : begin data_collision <= 2'b00; display_wa_rb; end +// 6'b010110 : begin data_collision <= 2'b00; display_wa_rb; end +// 6'b011010 : begin data_collision <= 2'b00; display_wa_rb; end + 6'b100010 : begin data_collision <= 2'b01; display_wa_rb; end + 6'b100110 : begin data_collision <= 2'b01; display_wa_rb; end + 6'b101010 : begin data_collision <= 2'b01; display_wa_rb; end + endcase + end + end + setup_zero <= 0; + end + + task display_ra_wb; + begin + if (display_flag) + $display("Memory Collision Error on RAMB16_S1_S36:%m at simulation time %.3f ns\nA read was performed on address %h (hex) of Port A while a write was requested to the same address on Port B. The write will be successful however the read value on Port A is unknown until the next CLKA cycle.", $time/1000.0, addra_int); + end + endtask + + task display_wa_rb; + begin + if (display_flag) + $display("Memory Collision Error on RAMB16_S1_S36:%m at simulation time %.3f ns\nA read was performed on address %h (hex) of Port B while a write was requested to the same address on Port A. The write will be successful however the read value on Port B is unknown until the next CLKB cycle.", $time/1000.0, addrb_int); + end + endtask + + task display_wa_wb; + begin + if (display_flag) + $display("Memory Collision Error on RAMB16_S1_S36:%m at simulation time %.3f ns\nA write was requested to the same address simultaneously at both Port A and Port B of the RAM. The contents written to the RAM at address location %h (hex) of Port A and address location %h (hex) of Port B are unknown.", $time/1000.0, addra_int, addrb_int); + end + endtask + + + always @(posedge setup_rf_a_b) begin + if (data_addra_reg[14:5] == data_addrb_int[14:5]) begin + if ((ena_reg == 1) && (enb_int == 1)) begin + case ({wr_mode_a, wr_mode_b, wea_reg, web_int}) +// 6'b000011 : begin data_collision_a_b <= 2'b00; display_wa_wb; end +// 6'b000111 : begin data_collision_a_b <= 2'b00; display_wa_wb; end +// 6'b001011 : begin data_collision_a_b <= 2'b00; display_wa_wb; end + 6'b010011 : begin data_collision_a_b <= 2'b11; display_wa_wb; end + 6'b010111 : begin data_collision_a_b <= 2'b11; display_wa_wb; end + 6'b011011 : begin data_collision_a_b <= 2'b10; display_wa_wb; end +// 6'b100011 : begin data_collision_a_b <= 2'b00; display_wa_wb; end +// 6'b100111 : begin data_collision_a_b <= 2'b00; display_wa_wb; end +// 6'b101011 : begin data_collision_a_b <= 2'b00; display_wa_wb; end +// 6'b000001 : begin data_collision_a_b <= 2'b00; display_ra_wb; end +// 6'b000101 : begin data_collision_a_b <= 2'b00; display_ra_wb; end +// 6'b001001 : begin data_collision_a_b <= 2'b00; display_ra_wb; end +// 6'b010001 : begin data_collision_a_b <= 2'b00; display_ra_wb; end +// 6'b010101 : begin data_collision_a_b <= 2'b00; display_ra_wb; end +// 6'b011001 : begin data_collision_a_b <= 2'b00; display_ra_wb; end +// 6'b100001 : begin data_collision_a_b <= 2'b00; display_ra_wb; end +// 6'b100101 : begin data_collision_a_b <= 2'b00; display_ra_wb; end +// 6'b101001 : begin data_collision_a_b <= 2'b00; display_ra_wb; end +// 6'b000010 : begin data_collision_a_b <= 2'b00; display_wa_rb; end +// 6'b000110 : begin data_collision_a_b <= 2'b00; display_wa_rb; end +// 6'b001010 : begin data_collision_a_b <= 2'b00; display_wa_rb; end + 6'b010010 : begin data_collision_a_b <= 2'b01; display_wa_rb; end + 6'b010110 : begin data_collision_a_b <= 2'b01; display_wa_rb; end + 6'b011010 : begin data_collision_a_b <= 2'b01; display_wa_rb; end +// 6'b100010 : begin data_collision_a_b <= 2'b00; display_wa_rb; end +// 6'b100110 : begin data_collision_a_b <= 2'b00; display_wa_rb; end +// 6'b101010 : begin data_collision_a_b <= 2'b00; display_wa_rb; end + endcase + end + end + setup_rf_a_b <= 0; + end + + + always @(posedge setup_rf_b_a) begin + if (data_addra_int[14:5] == data_addrb_reg[14:5]) begin + if ((ena_int == 1) && (enb_reg == 1)) begin + case ({wr_mode_a, wr_mode_b, wea_int, web_reg}) +// 6'b000011 : begin data_collision_b_a <= 2'b00; display_wa_wb; end + 6'b000111 : begin data_collision_b_a <= 2'b11; display_wa_wb; end +// 6'b001011 : begin data_collision_b_a <= 2'b00; display_wa_wb; end +// 6'b010011 : begin data_collision_b_a <= 2'b00; display_wa_wb; end + 6'b010111 : begin data_collision_b_a <= 2'b11; display_wa_wb; end +// 6'b011011 : begin data_collision_b_a <= 2'b00; display_wa_wb; end +// 6'b100011 : begin data_collision_b_a <= 2'b00; display_wa_wb; end + 6'b100111 : begin data_collision_b_a <= 2'b01; display_wa_wb; end +// 6'b101011 : begin data_collision_b_a <= 2'b00; display_wa_wb; end +// 6'b000001 : begin data_collision_b_a <= 2'b00; display_ra_wb; end + 6'b000101 : begin data_collision_b_a <= 2'b10; display_ra_wb; end +// 6'b001001 : begin data_collision_b_a <= 2'b00; display_ra_wb; end +// 6'b010001 : begin data_collision_b_a <= 2'b00; display_ra_wb; end + 6'b010101 : begin data_collision_b_a <= 2'b10; display_ra_wb; end +// 6'b011001 : begin data_collision_b_a <= 2'b00; display_ra_wb; end +// 6'b100001 : begin data_collision_b_a <= 2'b00; display_ra_wb; end + 6'b100101 : begin data_collision_b_a <= 2'b10; display_ra_wb; end +// 6'b101001 : begin data_collision_b_a <= 2'b00; display_ra_wb; end +// 6'b000010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end +// 6'b000110 : begin data_collision_b_a <= 2'b00; display_wa_rb; end +// 6'b001010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end +// 6'b010010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end +// 6'b010110 : begin data_collision_b_a <= 2'b00; display_wa_rb; end +// 6'b011010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end +// 6'b100010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end +// 6'b100110 : begin data_collision_b_a <= 2'b00; display_wa_rb; end +// 6'b101010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end + endcase + end + end + setup_rf_b_a <= 0; + end + + + always @(posedge clka_int) begin + if ((output_flag || display_flag)) begin + addra_reg <= addra_int; + ena_reg <= ena_int; + ssra_reg <= ssra_int; + wea_reg <= wea_int; + end + end + + always @(posedge clkb_int) begin + if ((output_flag || display_flag)) begin + addrb_reg <= addrb_int; + enb_reg <= enb_int; + ssrb_reg <= ssrb_int; + web_reg <= web_int; + end + end + + + // Data + always @(posedge memory_collision) begin + if ((output_flag || display_flag)) begin + mem[addra_int[13:5]][addra_int[4:0] * 1 +: 1] <= 1'bx; + memory_collision <= 0; + end + + end + + always @(posedge memory_collision_a_b) begin + if ((output_flag || display_flag)) begin + mem[addra_reg[13:5]][addra_reg[4:0] * 1 +: 1] <= 1'bx; + memory_collision_a_b <= 0; + end + end + + always @(posedge memory_collision_b_a) begin + if ((output_flag || display_flag)) begin + mem[addra_int[13:5]][addra_int[4:0] * 1 +: 1] <= 1'bx; + memory_collision_b_a <= 0; + end + end + + always @(posedge data_collision[1]) begin + if (ssra_int == 0 && output_flag) begin + doa_out <= #100 1'bX; + end + data_collision[1] <= 0; + end + + always @(posedge data_collision[0]) begin + if (ssrb_int == 0 && output_flag) begin + dob_out[addra_int[4:0] * 1 +: 1] <= #100 1'bX; + end + data_collision[0] <= 0; + end + + always @(posedge data_collision_a_b[1]) begin + if (ssra_reg == 0 && output_flag) begin + doa_out <= #100 1'bX; + end + data_collision_a_b[1] <= 0; + end + + always @(posedge data_collision_a_b[0]) begin + if (ssrb_int == 0 && output_flag) begin + dob_out[addra_reg[4:0] * 1 +: 1] <= #100 1'bX; + end + data_collision_a_b[0] <= 0; + end + + always @(posedge data_collision_b_a[1]) begin + if (ssra_int == 0 && output_flag) begin + doa_out <= #100 1'bX; + end + data_collision_b_a[1] <= 0; + end + + always @(posedge data_collision_b_a[0]) begin + if (ssrb_reg == 0 && output_flag) begin + dob_out[addra_int[4:0] * 1 +: 1] <= #100 1'bX; + end + data_collision_b_a[0] <= 0; + end + + + initial begin + case (WRITE_MODE_A) + "WRITE_FIRST" : wr_mode_a <= 2'b00; + "READ_FIRST" : wr_mode_a <= 2'b01; + "NO_CHANGE" : wr_mode_a <= 2'b10; + default : begin + $display("Attribute Syntax Error : The Attribute WRITE_MODE_A on RAMB16_S1_S36 instance %m is set to %s. Legal values for this attribute are WRITE_FIRST, READ_FIRST or NO_CHANGE.", WRITE_MODE_A); + $finish; + end + endcase + end + + initial begin + case (WRITE_MODE_B) + "WRITE_FIRST" : wr_mode_b <= 2'b00; + "READ_FIRST" : wr_mode_b <= 2'b01; + "NO_CHANGE" : wr_mode_b <= 2'b10; + default : begin + $display("Attribute Syntax Error : The Attribute WRITE_MODE_B on RAMB16_S1_S36 instance %m is set to %s. Legal values for this attribute are WRITE_FIRST, READ_FIRST or NO_CHANGE.", WRITE_MODE_B); + $finish; + end + endcase + end + + + // Port A + always @(posedge clka_int) begin + + if (ena_int == 1'b1) begin + + if (ssra_int == 1'b1) begin + {doa_out} <= #100 SRVAL_A; + end + else begin + if (wea_int == 1'b1) begin + if (wr_mode_a == 2'b00) begin + doa_out <= #100 dia_int; + end + else if (wr_mode_a == 2'b01) begin + + doa_out <= #100 mem[addra_int[13:5]][addra_int[4:0] * 1 +: 1]; + + end + end + else begin + + doa_out <= #100 mem[addra_int[13:5]][addra_int[4:0] * 1 +: 1]; + + end + end + + // memory + if (wea_int == 1'b1) begin + mem[addra_int[13:5]][addra_int[4:0] * 1 +: 1] <= dia_int; + end + + end + end + + + // Port B + always @(posedge clkb_int) begin + + if (enb_int == 1'b1) begin + + if (ssrb_int == 1'b1) begin + {dopb_out, dob_out} <= #100 SRVAL_B; + end + else begin + if (web_int == 1'b1) begin + if (wr_mode_b == 2'b00) begin + dob_out <= #100 dib_int; + dopb_out <= #100 dipb_int; + end + else if (wr_mode_b == 2'b01) begin + dob_out <= #100 mem[addrb_int]; + dopb_out <= #100 memp[addrb_int]; + end + end + else begin + dob_out <= #100 mem[addrb_int]; + dopb_out <= #100 memp[addrb_int]; + end + end + + // memory + if (web_int == 1'b1) begin + mem[addrb_int] <= dib_int; + memp[addrb_int] <= dipb_int; + end + + end + end + + +endmodule + +`endif diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/RAMB16_S1_S4.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/RAMB16_S1_S4.v new file mode 100644 index 0000000..638db7b --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/RAMB16_S1_S4.v @@ -0,0 +1,1549 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/RAMB16_S1_S4.v,v 1.11 2007/02/22 01:58:05 wloo Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2005 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / 16K-Bit Data and 2K-Bit Parity Dual Port Block RAM +// /___/ /\ Filename : RAMB16_S1_S4.v +// \ \ / \ Timestamp : Thu Mar 10 16:43:35 PST 2005 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// End Revision + +`ifdef legacy_model + +`timescale 1 ps / 1 ps + +module RAMB16_S1_S4 (DOA, DOB, ADDRA, ADDRB, CLKA, CLKB, DIA, DIB, ENA, ENB, SSRA, SSRB, WEA, WEB); + + parameter INIT_A = 1'h0; + parameter INIT_B = 4'h0; + parameter SRVAL_A = 1'h0; + parameter SRVAL_B = 4'h0; + parameter WRITE_MODE_A = "WRITE_FIRST"; + parameter WRITE_MODE_B = "WRITE_FIRST"; + parameter SIM_COLLISION_CHECK = "ALL"; + localparam SETUP_ALL = 1000; + localparam SETUP_READ_FIRST = 3000; + + parameter INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + + output [0:0] DOA; + reg [0:0] doa_out; + wire doa_out0; + + input [13:0] ADDRA; + input [0:0] DIA; + input ENA, CLKA, WEA, SSRA; + + output [3:0] DOB; + reg [3:0] dob_out; + wire dob_out0, dob_out1, dob_out2, dob_out3; + + input [11:0] ADDRB; + input [3:0] DIB; + input ENB, CLKB, WEB, SSRB; + + reg [18431:0] mem; + reg [8:0] count; + reg [1:0] wr_mode_a, wr_mode_b; + + reg [5:0] dmi, dbi; + reg [5:0] pmi, pbi; + + wire [13:0] addra_int; + reg [13:0] addra_reg; + wire [0:0] dia_int; + wire ena_int, clka_int, wea_int, ssra_int; + reg ena_reg, wea_reg, ssra_reg; + wire [11:0] addrb_int; + reg [11:0] addrb_reg; + wire [3:0] dib_int; + wire enb_int, clkb_int, web_int, ssrb_int; + reg display_flag; + reg enb_reg, web_reg, ssrb_reg; + + time time_clka, time_clkb; + time time_clka_clkb; + time time_clkb_clka; + + reg setup_all_a_b; + reg setup_all_b_a; + reg setup_zero; + reg setup_rf_a_b; + reg setup_rf_b_a; + reg [1:0] data_collision, data_collision_a_b, data_collision_b_a; + reg memory_collision, memory_collision_a_b, memory_collision_b_a; + reg address_collision, address_collision_a_b, address_collision_b_a; + reg change_clka; + reg change_clkb; + + wire [14:0] data_addra_int; + wire [14:0] data_addra_reg; + wire [14:0] data_addrb_int; + wire [14:0] data_addrb_reg; + wire [15:0] parity_addra_int; + wire [15:0] parity_addra_reg; + wire [15:0] parity_addrb_int; + wire [15:0] parity_addrb_reg; + + tri0 GSR = glbl.GSR; + + always @(GSR) + if (GSR) begin + assign doa_out = INIT_A[0:0]; + assign dob_out = INIT_B[3:0]; + end + else begin + deassign doa_out; + deassign dob_out; + end + + buf b_doa_out0 (doa_out0, doa_out[0]); + buf b_dob_out0 (dob_out0, dob_out[0]); + buf b_dob_out1 (dob_out1, dob_out[1]); + buf b_dob_out2 (dob_out2, dob_out[2]); + buf b_dob_out3 (dob_out3, dob_out[3]); + + buf b_doa0 (DOA[0], doa_out0); + buf b_dob0 (DOB[0], dob_out0); + buf b_dob1 (DOB[1], dob_out1); + buf b_dob2 (DOB[2], dob_out2); + buf b_dob3 (DOB[3], dob_out3); + + buf b_addra_0 (addra_int[0], ADDRA[0]); + buf b_addra_1 (addra_int[1], ADDRA[1]); + buf b_addra_2 (addra_int[2], ADDRA[2]); + buf b_addra_3 (addra_int[3], ADDRA[3]); + buf b_addra_4 (addra_int[4], ADDRA[4]); + buf b_addra_5 (addra_int[5], ADDRA[5]); + buf b_addra_6 (addra_int[6], ADDRA[6]); + buf b_addra_7 (addra_int[7], ADDRA[7]); + buf b_addra_8 (addra_int[8], ADDRA[8]); + buf b_addra_9 (addra_int[9], ADDRA[9]); + buf b_addra_10 (addra_int[10], ADDRA[10]); + buf b_addra_11 (addra_int[11], ADDRA[11]); + buf b_addra_12 (addra_int[12], ADDRA[12]); + buf b_addra_13 (addra_int[13], ADDRA[13]); + buf b_dia_0 (dia_int[0], DIA[0]); + buf b_ena (ena_int, ENA); + buf b_clka (clka_int, CLKA); + buf b_ssra (ssra_int, SSRA); + buf b_wea (wea_int, WEA); + buf b_addrb_0 (addrb_int[0], ADDRB[0]); + buf b_addrb_1 (addrb_int[1], ADDRB[1]); + buf b_addrb_2 (addrb_int[2], ADDRB[2]); + buf b_addrb_3 (addrb_int[3], ADDRB[3]); + buf b_addrb_4 (addrb_int[4], ADDRB[4]); + buf b_addrb_5 (addrb_int[5], ADDRB[5]); + buf b_addrb_6 (addrb_int[6], ADDRB[6]); + buf b_addrb_7 (addrb_int[7], ADDRB[7]); + buf b_addrb_8 (addrb_int[8], ADDRB[8]); + buf b_addrb_9 (addrb_int[9], ADDRB[9]); + buf b_addrb_10 (addrb_int[10], ADDRB[10]); + buf b_addrb_11 (addrb_int[11], ADDRB[11]); + buf b_dib_0 (dib_int[0], DIB[0]); + buf b_dib_1 (dib_int[1], DIB[1]); + buf b_dib_2 (dib_int[2], DIB[2]); + buf b_dib_3 (dib_int[3], DIB[3]); + buf b_enb (enb_int, ENB); + buf b_clkb (clkb_int, CLKB); + buf b_ssrb (ssrb_int, SSRB); + buf b_web (web_int, WEB); + + initial begin + for (count = 0; count < 256; count = count + 1) begin + mem[count] <= INIT_00[count]; + mem[256 * 1 + count] <= INIT_01[count]; + mem[256 * 2 + count] <= INIT_02[count]; + mem[256 * 3 + count] <= INIT_03[count]; + mem[256 * 4 + count] <= INIT_04[count]; + mem[256 * 5 + count] <= INIT_05[count]; + mem[256 * 6 + count] <= INIT_06[count]; + mem[256 * 7 + count] <= INIT_07[count]; + mem[256 * 8 + count] <= INIT_08[count]; + mem[256 * 9 + count] <= INIT_09[count]; + mem[256 * 10 + count] <= INIT_0A[count]; + mem[256 * 11 + count] <= INIT_0B[count]; + mem[256 * 12 + count] <= INIT_0C[count]; + mem[256 * 13 + count] <= INIT_0D[count]; + mem[256 * 14 + count] <= INIT_0E[count]; + mem[256 * 15 + count] <= INIT_0F[count]; + mem[256 * 16 + count] <= INIT_10[count]; + mem[256 * 17 + count] <= INIT_11[count]; + mem[256 * 18 + count] <= INIT_12[count]; + mem[256 * 19 + count] <= INIT_13[count]; + mem[256 * 20 + count] <= INIT_14[count]; + mem[256 * 21 + count] <= INIT_15[count]; + mem[256 * 22 + count] <= INIT_16[count]; + mem[256 * 23 + count] <= INIT_17[count]; + mem[256 * 24 + count] <= INIT_18[count]; + mem[256 * 25 + count] <= INIT_19[count]; + mem[256 * 26 + count] <= INIT_1A[count]; + mem[256 * 27 + count] <= INIT_1B[count]; + mem[256 * 28 + count] <= INIT_1C[count]; + mem[256 * 29 + count] <= INIT_1D[count]; + mem[256 * 30 + count] <= INIT_1E[count]; + mem[256 * 31 + count] <= INIT_1F[count]; + mem[256 * 32 + count] <= INIT_20[count]; + mem[256 * 33 + count] <= INIT_21[count]; + mem[256 * 34 + count] <= INIT_22[count]; + mem[256 * 35 + count] <= INIT_23[count]; + mem[256 * 36 + count] <= INIT_24[count]; + mem[256 * 37 + count] <= INIT_25[count]; + mem[256 * 38 + count] <= INIT_26[count]; + mem[256 * 39 + count] <= INIT_27[count]; + mem[256 * 40 + count] <= INIT_28[count]; + mem[256 * 41 + count] <= INIT_29[count]; + mem[256 * 42 + count] <= INIT_2A[count]; + mem[256 * 43 + count] <= INIT_2B[count]; + mem[256 * 44 + count] <= INIT_2C[count]; + mem[256 * 45 + count] <= INIT_2D[count]; + mem[256 * 46 + count] <= INIT_2E[count]; + mem[256 * 47 + count] <= INIT_2F[count]; + mem[256 * 48 + count] <= INIT_30[count]; + mem[256 * 49 + count] <= INIT_31[count]; + mem[256 * 50 + count] <= INIT_32[count]; + mem[256 * 51 + count] <= INIT_33[count]; + mem[256 * 52 + count] <= INIT_34[count]; + mem[256 * 53 + count] <= INIT_35[count]; + mem[256 * 54 + count] <= INIT_36[count]; + mem[256 * 55 + count] <= INIT_37[count]; + mem[256 * 56 + count] <= INIT_38[count]; + mem[256 * 57 + count] <= INIT_39[count]; + mem[256 * 58 + count] <= INIT_3A[count]; + mem[256 * 59 + count] <= INIT_3B[count]; + mem[256 * 60 + count] <= INIT_3C[count]; + mem[256 * 61 + count] <= INIT_3D[count]; + mem[256 * 62 + count] <= INIT_3E[count]; + mem[256 * 63 + count] <= INIT_3F[count]; + end + address_collision <= 0; + address_collision_a_b <= 0; + address_collision_b_a <= 0; + change_clka <= 0; + change_clkb <= 0; + data_collision <= 0; + data_collision_a_b <= 0; + data_collision_b_a <= 0; + memory_collision <= 0; + memory_collision_a_b <= 0; + memory_collision_b_a <= 0; + setup_all_a_b <= 0; + setup_all_b_a <= 0; + setup_zero <= 0; + setup_rf_a_b <= 0; + setup_rf_b_a <= 0; + end + + assign data_addra_int = addra_int * 1; + assign data_addra_reg = addra_reg * 1; + assign data_addrb_int = addrb_int * 4; + assign data_addrb_reg = addrb_reg * 4; + + + initial begin + + display_flag = 1; + + case (SIM_COLLISION_CHECK) + + "NONE" : begin + assign setup_all_a_b = 1'b0; + assign setup_all_b_a = 1'b0; + assign setup_zero = 1'b0; + assign setup_rf_a_b = 1'b0; + assign setup_rf_b_a = 1'b0; + assign display_flag = 0; + end + "WARNING_ONLY" : begin + assign data_collision = 2'b00; + assign data_collision_a_b = 2'b00; + assign data_collision_b_a = 2'b00; + assign memory_collision = 1'b0; + assign memory_collision_a_b = 1'b0; + assign memory_collision_b_a = 1'b0; + end + "GENERATE_X_ONLY" : begin + assign display_flag = 0; + end + "ALL" : ; + default : begin + $display("Attribute Syntax Error : The Attribute SIM_COLLISION_CHECK on RAMB16_S1_S4 instance %m is set to %s. Legal values for this attribute are ALL, NONE, WARNING_ONLY or GENERATE_X_ONLY.", SIM_COLLISION_CHECK); + $finish; + end + + endcase // case(SIM_COLLISION_CHECK) + + end // initial begin + + + always @(posedge clka_int) begin + time_clka = $time; + #0 time_clkb_clka = time_clka - time_clkb; + change_clka = ~change_clka; + end + + always @(posedge clkb_int) begin + time_clkb = $time; + #0 time_clka_clkb = time_clkb - time_clka; + change_clkb = ~change_clkb; + end + + always @(change_clkb) begin + if ((0 < time_clka_clkb) && (time_clka_clkb < SETUP_ALL)) + setup_all_a_b = 1; + if ((0 < time_clka_clkb) && (time_clka_clkb < SETUP_READ_FIRST)) + setup_rf_a_b = 1; + end + + always @(change_clka) begin + if ((0 < time_clkb_clka) && (time_clkb_clka < SETUP_ALL)) + setup_all_b_a = 1; + if ((0 < time_clkb_clka) && (time_clkb_clka < SETUP_READ_FIRST)) + setup_rf_b_a = 1; + end + + always @(change_clkb or change_clka) begin + if ((time_clkb_clka == 0) && (time_clka_clkb == 0)) + setup_zero = 1; + end + + always @(posedge setup_zero) begin + if ((ena_int == 1) && (wea_int == 1) && + (enb_int == 1) && (web_int == 1) && + (data_addra_int[14:2] == data_addrb_int[14:2])) + memory_collision <= 1; + end + + always @(posedge setup_all_a_b or posedge setup_rf_a_b) begin + if ((ena_reg == 1) && (wea_reg == 1) && + (enb_int == 1) && (web_int == 1) && + (data_addra_reg[14:2] == data_addrb_int[14:2])) + memory_collision_a_b <= 1; + end + + always @(posedge setup_all_b_a or posedge setup_rf_b_a) begin + if ((ena_int == 1) && (wea_int == 1) && + (enb_reg == 1) && (web_reg == 1) && + (data_addra_int[14:2] == data_addrb_reg[14:2])) + memory_collision_b_a <= 1; + end + + always @(posedge setup_all_a_b) begin + if (data_addra_reg[14:2] == data_addrb_int[14:2]) begin + if ((ena_reg == 1) && (enb_int == 1)) begin + case ({wr_mode_a, wr_mode_b, wea_reg, web_int}) + 6'b000011 : begin data_collision_a_b <= 2'b11; display_wa_wb; end + 6'b000111 : begin data_collision_a_b <= 2'b11; display_wa_wb; end + 6'b001011 : begin data_collision_a_b <= 2'b10; display_wa_wb; end +// 6'b010011 : begin data_collision_a_b <= 2'b00; display_wa_wb; end +// 6'b010111 : begin data_collision_a_b <= 2'b00; display_wa_wb; end +// 6'b011011 : begin data_collision_a_b <= 2'b00; display_wa_wb; end + 6'b100011 : begin data_collision_a_b <= 2'b01; display_wa_wb; end + 6'b100111 : begin data_collision_a_b <= 2'b01; display_wa_wb; end + 6'b101011 : begin display_wa_wb; end + 6'b000001 : begin data_collision_a_b <= 2'b10; display_ra_wb; end +// 6'b000101 : begin data_collision_a_b <= 2'b00; display_ra_wb; end + 6'b001001 : begin data_collision_a_b <= 2'b10; display_ra_wb; end + 6'b010001 : begin data_collision_a_b <= 2'b10; display_ra_wb; end +// 6'b010101 : begin data_collision_a_b <= 2'b00; display_ra_wb; end + 6'b011001 : begin data_collision_a_b <= 2'b10; display_ra_wb; end + 6'b100001 : begin data_collision_a_b <= 2'b10; display_ra_wb; end +// 6'b100101 : begin data_collision_a_b <= 2'b00; display_ra_wb; end + 6'b101001 : begin data_collision_a_b <= 2'b10; display_ra_wb; end + 6'b000010 : begin data_collision_a_b <= 2'b01; display_wa_rb; end + 6'b000110 : begin data_collision_a_b <= 2'b01; display_wa_rb; end + 6'b001010 : begin data_collision_a_b <= 2'b01; display_wa_rb; end +// 6'b010010 : begin data_collision_a_b <= 2'b00; display_wa_rb; end +// 6'b010110 : begin data_collision_a_b <= 2'b00; display_wa_rb; end +// 6'b011010 : begin data_collision_a_b <= 2'b00; display_wa_rb; end + 6'b100010 : begin data_collision_a_b <= 2'b01; display_wa_rb; end + 6'b100110 : begin data_collision_a_b <= 2'b01; display_wa_rb; end + 6'b101010 : begin data_collision_a_b <= 2'b01; display_wa_rb; end + endcase + end + end + setup_all_a_b <= 0; + end + + + always @(posedge setup_all_b_a) begin + if (data_addra_int[14:2] == data_addrb_reg[14:2]) begin + if ((ena_int == 1) && (enb_reg == 1)) begin + case ({wr_mode_a, wr_mode_b, wea_int, web_reg}) + 6'b000011 : begin data_collision_b_a <= 2'b11; display_wa_wb; end +// 6'b000111 : begin data_collision_b_a <= 2'b00; display_wa_wb; end + 6'b001011 : begin data_collision_b_a <= 2'b10; display_wa_wb; end + 6'b010011 : begin data_collision_b_a <= 2'b11; display_wa_wb; end +// 6'b010111 : begin data_collision_b_a <= 2'b00; display_wa_wb; end + 6'b011011 : begin data_collision_b_a <= 2'b10; display_wa_wb; end + 6'b100011 : begin data_collision_b_a <= 2'b01; display_wa_wb; end + 6'b100111 : begin data_collision_b_a <= 2'b01; display_wa_wb; end + 6'b101011 : begin display_wa_wb; end + 6'b000001 : begin data_collision_b_a <= 2'b10; display_ra_wb; end + 6'b000101 : begin data_collision_b_a <= 2'b10; display_ra_wb; end + 6'b001001 : begin data_collision_b_a <= 2'b10; display_ra_wb; end + 6'b010001 : begin data_collision_b_a <= 2'b10; display_ra_wb; end + 6'b010101 : begin data_collision_b_a <= 2'b10; display_ra_wb; end + 6'b011001 : begin data_collision_b_a <= 2'b10; display_ra_wb; end + 6'b100001 : begin data_collision_b_a <= 2'b10; display_ra_wb; end + 6'b100101 : begin data_collision_b_a <= 2'b10; display_ra_wb; end + 6'b101001 : begin data_collision_b_a <= 2'b10; display_ra_wb; end + 6'b000010 : begin data_collision_b_a <= 2'b01; display_wa_rb; end + 6'b000110 : begin data_collision_b_a <= 2'b01; display_wa_rb; end + 6'b001010 : begin data_collision_b_a <= 2'b01; display_wa_rb; end +// 6'b010010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end +// 6'b010110 : begin data_collision_b_a <= 2'b00; display_wa_rb; end +// 6'b011010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end + 6'b100010 : begin data_collision_b_a <= 2'b01; display_wa_rb; end + 6'b100110 : begin data_collision_b_a <= 2'b01; display_wa_rb; end + 6'b101010 : begin data_collision_b_a <= 2'b01; display_wa_rb; end + endcase + end + end + setup_all_b_a <= 0; + end + + + always @(posedge setup_zero) begin + if (data_addra_int[14:2] == data_addrb_int[14:2]) begin + if ((ena_int == 1) && (enb_int == 1)) begin + case ({wr_mode_a, wr_mode_b, wea_int, web_int}) + 6'b000011 : begin data_collision <= 2'b11; display_wa_wb; end + 6'b000111 : begin data_collision <= 2'b11; display_wa_wb; end + 6'b001011 : begin data_collision <= 2'b10; display_wa_wb; end + 6'b010011 : begin data_collision <= 2'b11; display_wa_wb; end + 6'b010111 : begin data_collision <= 2'b11; display_wa_wb; end + 6'b011011 : begin data_collision <= 2'b10; display_wa_wb; end + 6'b100011 : begin data_collision <= 2'b01; display_wa_wb; end + 6'b100111 : begin data_collision <= 2'b01; display_wa_wb; end + 6'b101011 : begin display_wa_wb; end + 6'b000001 : begin data_collision <= 2'b10; display_ra_wb; end +// 6'b000101 : begin data_collision <= 2'b00; display_ra_wb; end + 6'b001001 : begin data_collision <= 2'b10; display_ra_wb; end + 6'b010001 : begin data_collision <= 2'b10; display_ra_wb; end +// 6'b010101 : begin data_collision <= 2'b00; display_ra_wb; end + 6'b011001 : begin data_collision <= 2'b10; display_ra_wb; end + 6'b100001 : begin data_collision <= 2'b10; display_ra_wb; end +// 6'b100101 : begin data_collision <= 2'b00; display_ra_wb; end + 6'b101001 : begin data_collision <= 2'b10; display_ra_wb; end + 6'b000010 : begin data_collision <= 2'b01; display_wa_rb; end + 6'b000110 : begin data_collision <= 2'b01; display_wa_rb; end + 6'b001010 : begin data_collision <= 2'b01; display_wa_rb; end +// 6'b010010 : begin data_collision <= 2'b00; display_wa_rb; end +// 6'b010110 : begin data_collision <= 2'b00; display_wa_rb; end +// 6'b011010 : begin data_collision <= 2'b00; display_wa_rb; end + 6'b100010 : begin data_collision <= 2'b01; display_wa_rb; end + 6'b100110 : begin data_collision <= 2'b01; display_wa_rb; end + 6'b101010 : begin data_collision <= 2'b01; display_wa_rb; end + endcase + end + end + setup_zero <= 0; + end + + task display_ra_wb; + begin + if (display_flag) + $display("Memory Collision Error on RAMB16_S1_S4:%m at simulation time %.3f ns\nA read was performed on address %h (hex) of Port A while a write was requested to the same address on Port B. The write will be successful however the read value on Port A is unknown until the next CLKA cycle.", $time/1000.0, addra_int); + end + endtask + + task display_wa_rb; + begin + if (display_flag) + $display("Memory Collision Error on RAMB16_S1_S4:%m at simulation time %.3f ns\nA read was performed on address %h (hex) of Port B while a write was requested to the same address on Port A. The write will be successful however the read value on Port B is unknown until the next CLKB cycle.", $time/1000.0, addrb_int); + end + endtask + + task display_wa_wb; + begin + if (display_flag) + $display("Memory Collision Error on RAMB16_S1_S4:%m at simulation time %.3f ns\nA write was requested to the same address simultaneously at both Port A and Port B of the RAM. The contents written to the RAM at address location %h (hex) of Port A and address location %h (hex) of Port B are unknown.", $time/1000.0, addra_int, addrb_int); + end + endtask + + + always @(posedge setup_rf_a_b) begin + if (data_addra_reg[14:2] == data_addrb_int[14:2]) begin + if ((ena_reg == 1) && (enb_int == 1)) begin + case ({wr_mode_a, wr_mode_b, wea_reg, web_int}) +// 6'b000011 : begin data_collision_a_b <= 2'b00; display_wa_wb; end +// 6'b000111 : begin data_collision_a_b <= 2'b00; display_wa_wb; end +// 6'b001011 : begin data_collision_a_b <= 2'b00; display_wa_wb; end + 6'b010011 : begin data_collision_a_b <= 2'b11; display_wa_wb; end + 6'b010111 : begin data_collision_a_b <= 2'b11; display_wa_wb; end + 6'b011011 : begin data_collision_a_b <= 2'b10; display_wa_wb; end +// 6'b100011 : begin data_collision_a_b <= 2'b00; display_wa_wb; end +// 6'b100111 : begin data_collision_a_b <= 2'b00; display_wa_wb; end +// 6'b101011 : begin data_collision_a_b <= 2'b00; display_wa_wb; end +// 6'b000001 : begin data_collision_a_b <= 2'b00; display_ra_wb; end +// 6'b000101 : begin data_collision_a_b <= 2'b00; display_ra_wb; end +// 6'b001001 : begin data_collision_a_b <= 2'b00; display_ra_wb; end +// 6'b010001 : begin data_collision_a_b <= 2'b00; display_ra_wb; end +// 6'b010101 : begin data_collision_a_b <= 2'b00; display_ra_wb; end +// 6'b011001 : begin data_collision_a_b <= 2'b00; display_ra_wb; end +// 6'b100001 : begin data_collision_a_b <= 2'b00; display_ra_wb; end +// 6'b100101 : begin data_collision_a_b <= 2'b00; display_ra_wb; end +// 6'b101001 : begin data_collision_a_b <= 2'b00; display_ra_wb; end +// 6'b000010 : begin data_collision_a_b <= 2'b00; display_wa_rb; end +// 6'b000110 : begin data_collision_a_b <= 2'b00; display_wa_rb; end +// 6'b001010 : begin data_collision_a_b <= 2'b00; display_wa_rb; end + 6'b010010 : begin data_collision_a_b <= 2'b01; display_wa_rb; end + 6'b010110 : begin data_collision_a_b <= 2'b01; display_wa_rb; end + 6'b011010 : begin data_collision_a_b <= 2'b01; display_wa_rb; end +// 6'b100010 : begin data_collision_a_b <= 2'b00; display_wa_rb; end +// 6'b100110 : begin data_collision_a_b <= 2'b00; display_wa_rb; end +// 6'b101010 : begin data_collision_a_b <= 2'b00; display_wa_rb; end + endcase + end + end + setup_rf_a_b <= 0; + end + + + always @(posedge setup_rf_b_a) begin + if (data_addra_int[14:2] == data_addrb_reg[14:2]) begin + if ((ena_int == 1) && (enb_reg == 1)) begin + case ({wr_mode_a, wr_mode_b, wea_int, web_reg}) +// 6'b000011 : begin data_collision_b_a <= 2'b00; display_wa_wb; end + 6'b000111 : begin data_collision_b_a <= 2'b11; display_wa_wb; end +// 6'b001011 : begin data_collision_b_a <= 2'b00; display_wa_wb; end +// 6'b010011 : begin data_collision_b_a <= 2'b00; display_wa_wb; end + 6'b010111 : begin data_collision_b_a <= 2'b11; display_wa_wb; end +// 6'b011011 : begin data_collision_b_a <= 2'b00; display_wa_wb; end +// 6'b100011 : begin data_collision_b_a <= 2'b00; display_wa_wb; end + 6'b100111 : begin data_collision_b_a <= 2'b01; display_wa_wb; end +// 6'b101011 : begin data_collision_b_a <= 2'b00; display_wa_wb; end +// 6'b000001 : begin data_collision_b_a <= 2'b00; display_ra_wb; end + 6'b000101 : begin data_collision_b_a <= 2'b10; display_ra_wb; end +// 6'b001001 : begin data_collision_b_a <= 2'b00; display_ra_wb; end +// 6'b010001 : begin data_collision_b_a <= 2'b00; display_ra_wb; end + 6'b010101 : begin data_collision_b_a <= 2'b10; display_ra_wb; end +// 6'b011001 : begin data_collision_b_a <= 2'b00; display_ra_wb; end +// 6'b100001 : begin data_collision_b_a <= 2'b00; display_ra_wb; end + 6'b100101 : begin data_collision_b_a <= 2'b10; display_ra_wb; end +// 6'b101001 : begin data_collision_b_a <= 2'b00; display_ra_wb; end +// 6'b000010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end +// 6'b000110 : begin data_collision_b_a <= 2'b00; display_wa_rb; end +// 6'b001010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end +// 6'b010010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end +// 6'b010110 : begin data_collision_b_a <= 2'b00; display_wa_rb; end +// 6'b011010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end +// 6'b100010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end +// 6'b100110 : begin data_collision_b_a <= 2'b00; display_wa_rb; end +// 6'b101010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end + endcase + end + end + setup_rf_b_a <= 0; + end + + + always @(posedge clka_int) begin + addra_reg <= addra_int; + ena_reg <= ena_int; + ssra_reg <= ssra_int; + wea_reg <= wea_int; + end + + always @(posedge clkb_int) begin + addrb_reg <= addrb_int; + enb_reg <= enb_int; + ssrb_reg <= ssrb_int; + web_reg <= web_int; + end + + // Data + always @(posedge memory_collision) begin + for (dmi = 0; dmi < 1; dmi = dmi + 1) begin + mem[data_addra_int + dmi] <= 1'bX; + end + memory_collision <= 0; + end + + always @(posedge memory_collision_a_b) begin + for (dmi = 0; dmi < 1; dmi = dmi + 1) begin + mem[data_addra_reg + dmi] <= 1'bX; + end + memory_collision_a_b <= 0; + end + + always @(posedge memory_collision_b_a) begin + for (dmi = 0; dmi < 1; dmi = dmi + 1) begin + mem[data_addra_int + dmi] <= 1'bX; + end + memory_collision_b_a <= 0; + end + + always @(posedge data_collision[1]) begin + if (ssra_int == 0) begin + doa_out <= 1'bX; + end + data_collision[1] <= 0; + end + + always @(posedge data_collision[0]) begin + if (ssrb_int == 0) begin + for (dbi = 0; dbi < 1; dbi = dbi + 1) begin + dob_out[data_addra_int[1 : 0] + dbi] <= 1'bX; + end + end + data_collision[0] <= 0; + end + + always @(posedge data_collision_a_b[1]) begin + if (ssra_reg == 0) begin + doa_out <= 1'bX; + end + data_collision_a_b[1] <= 0; + end + + always @(posedge data_collision_a_b[0]) begin + if (ssrb_int == 0) begin + for (dbi = 0; dbi < 1; dbi = dbi + 1) begin + dob_out[data_addra_reg[1 : 0] + dbi] <= 1'bX; + end + end + data_collision_a_b[0] <= 0; + end + + always @(posedge data_collision_b_a[1]) begin + if (ssra_int == 0) begin + doa_out <= 1'bX; + end + data_collision_b_a[1] <= 0; + end + + always @(posedge data_collision_b_a[0]) begin + if (ssrb_reg == 0) begin + for (dbi = 0; dbi < 1; dbi = dbi + 1) begin + dob_out[data_addra_int[1 : 0] + dbi] <= 1'bX; + end + end + data_collision_b_a[0] <= 0; + end + + + initial begin + case (WRITE_MODE_A) + "WRITE_FIRST" : wr_mode_a <= 2'b00; + "READ_FIRST" : wr_mode_a <= 2'b01; + "NO_CHANGE" : wr_mode_a <= 2'b10; + default : begin + $display("Attribute Syntax Error : The Attribute WRITE_MODE_A on RAMB16_S1_S4 instance %m is set to %s. Legal values for this attribute are WRITE_FIRST, READ_FIRST or NO_CHANGE.", WRITE_MODE_A); + $finish; + end + endcase + end + + initial begin + case (WRITE_MODE_B) + "WRITE_FIRST" : wr_mode_b <= 2'b00; + "READ_FIRST" : wr_mode_b <= 2'b01; + "NO_CHANGE" : wr_mode_b <= 2'b10; + default : begin + $display("Attribute Syntax Error : The Attribute WRITE_MODE_B on RAMB16_S1_S4 instance %m is set to %s. Legal values for this attribute are WRITE_FIRST, READ_FIRST or NO_CHANGE.", WRITE_MODE_B); + $finish; + end + endcase + end + + // Port A + always @(posedge clka_int) begin + if (ena_int == 1'b1) begin + if (ssra_int == 1'b1) begin + doa_out[0] <= SRVAL_A[0]; + end + else begin + if (wea_int == 1'b1) begin + if (wr_mode_a == 2'b00) begin + doa_out <= dia_int; + end + else if (wr_mode_a == 2'b01) begin + doa_out[0] <= mem[data_addra_int + 0]; + end + end + else begin + doa_out[0] <= mem[data_addra_int + 0]; + end + end + end + end + + always @(posedge clka_int) begin + if (ena_int == 1'b1 && wea_int == 1'b1) begin + mem[data_addra_int + 0] <= dia_int[0]; + end + end + + // Port B + always @(posedge clkb_int) begin + if (enb_int == 1'b1) begin + if (ssrb_int == 1'b1) begin + dob_out[0] <= SRVAL_B[0]; + dob_out[1] <= SRVAL_B[1]; + dob_out[2] <= SRVAL_B[2]; + dob_out[3] <= SRVAL_B[3]; + end + else begin + if (web_int == 1'b1) begin + if (wr_mode_b == 2'b00) begin + dob_out <= dib_int; + end + else if (wr_mode_b == 2'b01) begin + dob_out[0] <= mem[data_addrb_int + 0]; + dob_out[1] <= mem[data_addrb_int + 1]; + dob_out[2] <= mem[data_addrb_int + 2]; + dob_out[3] <= mem[data_addrb_int + 3]; + end + end + else begin + dob_out[0] <= mem[data_addrb_int + 0]; + dob_out[1] <= mem[data_addrb_int + 1]; + dob_out[2] <= mem[data_addrb_int + 2]; + dob_out[3] <= mem[data_addrb_int + 3]; + end + end + end + end + + always @(posedge clkb_int) begin + if (enb_int == 1'b1 && web_int == 1'b1) begin + mem[data_addrb_int + 0] <= dib_int[0]; + mem[data_addrb_int + 1] <= dib_int[1]; + mem[data_addrb_int + 2] <= dib_int[2]; + mem[data_addrb_int + 3] <= dib_int[3]; + end + end + + specify + (CLKA *> DOA) = (100, 100); + (CLKB *> DOB) = (100, 100); + endspecify + +endmodule + +`else + +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/RAMB16_S1_S4.v,v 1.11 2007/02/22 01:58:05 wloo Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2005 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Timing Simulation Library Component +// / / 16K-Bit Data and 2K-Bit Parity Dual Port Block RAM +// /___/ /\ Filename : RAMB16_S1_S4.v +// \ \ / \ Timestamp : Thu Mar 10 16:44:01 PST 2005 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 03/10/05 - Initialized outputs. +// 02/21/07 - Fixed parameter SIM_COLLISION_CHECK (CR 433281). +// End Revision + +`timescale 1 ps/1 ps + +module RAMB16_S1_S4 (DOA, DOB, ADDRA, ADDRB, CLKA, CLKB, DIA, DIB, ENA, ENB, SSRA, SSRB, WEA, WEB); + + parameter INIT_A = 1'h0; + parameter INIT_B = 4'h0; + parameter SRVAL_A = 1'h0; + parameter SRVAL_B = 4'h0; + parameter WRITE_MODE_A = "WRITE_FIRST"; + parameter WRITE_MODE_B = "WRITE_FIRST"; + parameter SIM_COLLISION_CHECK = "ALL"; + localparam SETUP_ALL = 1000; + localparam SETUP_READ_FIRST = 3000; + + parameter INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + + output [0:0] DOA; + output [3:0] DOB; + + input [13:0] ADDRA; + input [0:0] DIA; + input ENA, CLKA, WEA, SSRA; + input [11:0] ADDRB; + input [3:0] DIB; + input ENB, CLKB, WEB, SSRB; + + reg [0:0] doa_out = INIT_A[0:0]; + reg [3:0] dob_out = INIT_B[3:0]; + + reg [3:0] mem [4095:0]; + + reg [8:0] count, countp; + reg [1:0] wr_mode_a, wr_mode_b; + + reg [5:0] dmi, dbi; + reg [5:0] pmi, pbi; + + wire [13:0] addra_int; + reg [13:0] addra_reg; + wire [0:0] dia_int; + wire ena_int, clka_int, wea_int, ssra_int; + reg ena_reg, wea_reg, ssra_reg; + wire [11:0] addrb_int; + reg [11:0] addrb_reg; + wire [3:0] dib_int; + wire enb_int, clkb_int, web_int, ssrb_int; + reg display_flag, output_flag; + reg enb_reg, web_reg, ssrb_reg; + + time time_clka, time_clkb; + time time_clka_clkb; + time time_clkb_clka; + + reg setup_all_a_b; + reg setup_all_b_a; + reg setup_zero; + reg setup_rf_a_b; + reg setup_rf_b_a; + reg [1:0] data_collision, data_collision_a_b, data_collision_b_a; + reg memory_collision, memory_collision_a_b, memory_collision_b_a; + reg change_clka; + reg change_clkb; + + wire [14:0] data_addra_int; + wire [14:0] data_addra_reg; + wire [14:0] data_addrb_int; + wire [14:0] data_addrb_reg; + + wire dia_enable = ena_int && wea_int; + wire dib_enable = enb_int && web_int; + + tri0 GSR = glbl.GSR; + wire gsr_int; + + buf b_gsr (gsr_int, GSR); + + buf b_doa [0:0] (DOA, doa_out); + buf b_addra [13:0] (addra_int, ADDRA); + buf b_dia [0:0] (dia_int, DIA); + buf b_ena (ena_int, ENA); + buf b_clka (clka_int, CLKA); + buf b_ssra (ssra_int, SSRA); + buf b_wea (wea_int, WEA); + + buf b_dob [3:0] (DOB, dob_out); + buf b_addrb [11:0] (addrb_int, ADDRB); + buf b_dib [3:0] (dib_int, DIB); + buf b_enb (enb_int, ENB); + buf b_clkb (clkb_int, CLKB); + buf b_ssrb (ssrb_int, SSRB); + buf b_web (web_int, WEB); + + + always @(gsr_int) + if (gsr_int) begin + assign {doa_out} = INIT_A; + assign {dob_out} = INIT_B; + end + else begin + deassign doa_out; + deassign dob_out; + end + + + initial begin + + for (count = 0; count < 64; count = count + 1) begin + mem[count] = INIT_00[(count * 4) +: 4]; + mem[64 * 1 + count] = INIT_01[(count * 4) +: 4]; + mem[64 * 2 + count] = INIT_02[(count * 4) +: 4]; + mem[64 * 3 + count] = INIT_03[(count * 4) +: 4]; + mem[64 * 4 + count] = INIT_04[(count * 4) +: 4]; + mem[64 * 5 + count] = INIT_05[(count * 4) +: 4]; + mem[64 * 6 + count] = INIT_06[(count * 4) +: 4]; + mem[64 * 7 + count] = INIT_07[(count * 4) +: 4]; + mem[64 * 8 + count] = INIT_08[(count * 4) +: 4]; + mem[64 * 9 + count] = INIT_09[(count * 4) +: 4]; + mem[64 * 10 + count] = INIT_0A[(count * 4) +: 4]; + mem[64 * 11 + count] = INIT_0B[(count * 4) +: 4]; + mem[64 * 12 + count] = INIT_0C[(count * 4) +: 4]; + mem[64 * 13 + count] = INIT_0D[(count * 4) +: 4]; + mem[64 * 14 + count] = INIT_0E[(count * 4) +: 4]; + mem[64 * 15 + count] = INIT_0F[(count * 4) +: 4]; + mem[64 * 16 + count] = INIT_10[(count * 4) +: 4]; + mem[64 * 17 + count] = INIT_11[(count * 4) +: 4]; + mem[64 * 18 + count] = INIT_12[(count * 4) +: 4]; + mem[64 * 19 + count] = INIT_13[(count * 4) +: 4]; + mem[64 * 20 + count] = INIT_14[(count * 4) +: 4]; + mem[64 * 21 + count] = INIT_15[(count * 4) +: 4]; + mem[64 * 22 + count] = INIT_16[(count * 4) +: 4]; + mem[64 * 23 + count] = INIT_17[(count * 4) +: 4]; + mem[64 * 24 + count] = INIT_18[(count * 4) +: 4]; + mem[64 * 25 + count] = INIT_19[(count * 4) +: 4]; + mem[64 * 26 + count] = INIT_1A[(count * 4) +: 4]; + mem[64 * 27 + count] = INIT_1B[(count * 4) +: 4]; + mem[64 * 28 + count] = INIT_1C[(count * 4) +: 4]; + mem[64 * 29 + count] = INIT_1D[(count * 4) +: 4]; + mem[64 * 30 + count] = INIT_1E[(count * 4) +: 4]; + mem[64 * 31 + count] = INIT_1F[(count * 4) +: 4]; + mem[64 * 32 + count] = INIT_20[(count * 4) +: 4]; + mem[64 * 33 + count] = INIT_21[(count * 4) +: 4]; + mem[64 * 34 + count] = INIT_22[(count * 4) +: 4]; + mem[64 * 35 + count] = INIT_23[(count * 4) +: 4]; + mem[64 * 36 + count] = INIT_24[(count * 4) +: 4]; + mem[64 * 37 + count] = INIT_25[(count * 4) +: 4]; + mem[64 * 38 + count] = INIT_26[(count * 4) +: 4]; + mem[64 * 39 + count] = INIT_27[(count * 4) +: 4]; + mem[64 * 40 + count] = INIT_28[(count * 4) +: 4]; + mem[64 * 41 + count] = INIT_29[(count * 4) +: 4]; + mem[64 * 42 + count] = INIT_2A[(count * 4) +: 4]; + mem[64 * 43 + count] = INIT_2B[(count * 4) +: 4]; + mem[64 * 44 + count] = INIT_2C[(count * 4) +: 4]; + mem[64 * 45 + count] = INIT_2D[(count * 4) +: 4]; + mem[64 * 46 + count] = INIT_2E[(count * 4) +: 4]; + mem[64 * 47 + count] = INIT_2F[(count * 4) +: 4]; + mem[64 * 48 + count] = INIT_30[(count * 4) +: 4]; + mem[64 * 49 + count] = INIT_31[(count * 4) +: 4]; + mem[64 * 50 + count] = INIT_32[(count * 4) +: 4]; + mem[64 * 51 + count] = INIT_33[(count * 4) +: 4]; + mem[64 * 52 + count] = INIT_34[(count * 4) +: 4]; + mem[64 * 53 + count] = INIT_35[(count * 4) +: 4]; + mem[64 * 54 + count] = INIT_36[(count * 4) +: 4]; + mem[64 * 55 + count] = INIT_37[(count * 4) +: 4]; + mem[64 * 56 + count] = INIT_38[(count * 4) +: 4]; + mem[64 * 57 + count] = INIT_39[(count * 4) +: 4]; + mem[64 * 58 + count] = INIT_3A[(count * 4) +: 4]; + mem[64 * 59 + count] = INIT_3B[(count * 4) +: 4]; + mem[64 * 60 + count] = INIT_3C[(count * 4) +: 4]; + mem[64 * 61 + count] = INIT_3D[(count * 4) +: 4]; + mem[64 * 62 + count] = INIT_3E[(count * 4) +: 4]; + mem[64 * 63 + count] = INIT_3F[(count * 4) +: 4]; + end + + + change_clka <= 0; + change_clkb <= 0; + data_collision <= 0; + data_collision_a_b <= 0; + data_collision_b_a <= 0; + memory_collision <= 0; + memory_collision_a_b <= 0; + memory_collision_b_a <= 0; + setup_all_a_b <= 0; + setup_all_b_a <= 0; + setup_zero <= 0; + setup_rf_a_b <= 0; + setup_rf_b_a <= 0; + end + + assign data_addra_int = addra_int * 1; + assign data_addra_reg = addra_reg * 1; + assign data_addrb_int = addrb_int * 4; + assign data_addrb_reg = addrb_reg * 4; + + + initial begin + + display_flag = 1; + output_flag = 1; + + case (SIM_COLLISION_CHECK) + + "NONE" : begin + output_flag = 0; + display_flag = 0; + end + "WARNING_ONLY" : output_flag = 0; + "GENERATE_X_ONLY" : display_flag = 0; + "ALL" : ; + + default : begin + $display("Attribute Syntax Error : The Attribute SIM_COLLISION_CHECK on RAMB16_S1_S4 instance %m is set to %s. Legal values for this attribute are ALL, NONE, WARNING_ONLY or GENERATE_X_ONLY.", SIM_COLLISION_CHECK); + $finish; + end + + endcase // case(SIM_COLLISION_CHECK) + + end // initial begin + + + always @(posedge clka_int) begin + if ((output_flag || display_flag)) begin + time_clka = $time; + #0 time_clkb_clka = time_clka - time_clkb; + change_clka = ~change_clka; + end + end + + always @(posedge clkb_int) begin + if ((output_flag || display_flag)) begin + time_clkb = $time; + #0 time_clka_clkb = time_clkb - time_clka; + change_clkb = ~change_clkb; + end + end + + always @(change_clkb) begin + if ((0 < time_clka_clkb) && (time_clka_clkb < SETUP_ALL)) + setup_all_a_b = 1; + if ((0 < time_clka_clkb) && (time_clka_clkb < SETUP_READ_FIRST)) + setup_rf_a_b = 1; + end + + always @(change_clka) begin + if ((0 < time_clkb_clka) && (time_clkb_clka < SETUP_ALL)) + setup_all_b_a = 1; + if ((0 < time_clkb_clka) && (time_clkb_clka < SETUP_READ_FIRST)) + setup_rf_b_a = 1; + end + + always @(change_clkb or change_clka) begin + if ((time_clkb_clka == 0) && (time_clka_clkb == 0)) + setup_zero = 1; + end + + always @(posedge setup_zero) begin + if ((ena_int == 1) && (wea_int == 1) && + (enb_int == 1) && (web_int == 1) && + (data_addra_int[14:2] == data_addrb_int[14:2])) + memory_collision <= 1; + end + + always @(posedge setup_all_a_b or posedge setup_rf_a_b) begin + if ((ena_reg == 1) && (wea_reg == 1) && + (enb_int == 1) && (web_int == 1) && + (data_addra_reg[14:2] == data_addrb_int[14:2])) + memory_collision_a_b <= 1; + end + + always @(posedge setup_all_b_a or posedge setup_rf_b_a) begin + if ((ena_int == 1) && (wea_int == 1) && + (enb_reg == 1) && (web_reg == 1) && + (data_addra_int[14:2] == data_addrb_reg[14:2])) + memory_collision_b_a <= 1; + end + + always @(posedge setup_all_a_b) begin + if (data_addra_reg[14:2] == data_addrb_int[14:2]) begin + if ((ena_reg == 1) && (enb_int == 1)) begin + case ({wr_mode_a, wr_mode_b, wea_reg, web_int}) + 6'b000011 : begin data_collision_a_b <= 2'b11; display_wa_wb; end + 6'b000111 : begin data_collision_a_b <= 2'b11; display_wa_wb; end + 6'b001011 : begin data_collision_a_b <= 2'b10; display_wa_wb; end +// 6'b010011 : begin data_collision_a_b <= 2'b00; display_wa_wb; end +// 6'b010111 : begin data_collision_a_b <= 2'b00; display_wa_wb; end +// 6'b011011 : begin data_collision_a_b <= 2'b00; display_wa_wb; end + 6'b100011 : begin data_collision_a_b <= 2'b01; display_wa_wb; end + 6'b100111 : begin data_collision_a_b <= 2'b01; display_wa_wb; end + 6'b101011 : begin display_wa_wb; end + 6'b000001 : begin data_collision_a_b <= 2'b10; display_ra_wb; end +// 6'b000101 : begin data_collision_a_b <= 2'b00; display_ra_wb; end + 6'b001001 : begin data_collision_a_b <= 2'b10; display_ra_wb; end + 6'b010001 : begin data_collision_a_b <= 2'b10; display_ra_wb; end +// 6'b010101 : begin data_collision_a_b <= 2'b00; display_ra_wb; end + 6'b011001 : begin data_collision_a_b <= 2'b10; display_ra_wb; end + 6'b100001 : begin data_collision_a_b <= 2'b10; display_ra_wb; end +// 6'b100101 : begin data_collision_a_b <= 2'b00; display_ra_wb; end + 6'b101001 : begin data_collision_a_b <= 2'b10; display_ra_wb; end + 6'b000010 : begin data_collision_a_b <= 2'b01; display_wa_rb; end + 6'b000110 : begin data_collision_a_b <= 2'b01; display_wa_rb; end + 6'b001010 : begin data_collision_a_b <= 2'b01; display_wa_rb; end +// 6'b010010 : begin data_collision_a_b <= 2'b00; display_wa_rb; end +// 6'b010110 : begin data_collision_a_b <= 2'b00; display_wa_rb; end +// 6'b011010 : begin data_collision_a_b <= 2'b00; display_wa_rb; end + 6'b100010 : begin data_collision_a_b <= 2'b01; display_wa_rb; end + 6'b100110 : begin data_collision_a_b <= 2'b01; display_wa_rb; end + 6'b101010 : begin data_collision_a_b <= 2'b01; display_wa_rb; end + endcase + end + end + setup_all_a_b <= 0; + end + + + always @(posedge setup_all_b_a) begin + if (data_addra_int[14:2] == data_addrb_reg[14:2]) begin + if ((ena_int == 1) && (enb_reg == 1)) begin + case ({wr_mode_a, wr_mode_b, wea_int, web_reg}) + 6'b000011 : begin data_collision_b_a <= 2'b11; display_wa_wb; end +// 6'b000111 : begin data_collision_b_a <= 2'b00; display_wa_wb; end + 6'b001011 : begin data_collision_b_a <= 2'b10; display_wa_wb; end + 6'b010011 : begin data_collision_b_a <= 2'b11; display_wa_wb; end +// 6'b010111 : begin data_collision_b_a <= 2'b00; display_wa_wb; end + 6'b011011 : begin data_collision_b_a <= 2'b10; display_wa_wb; end + 6'b100011 : begin data_collision_b_a <= 2'b01; display_wa_wb; end + 6'b100111 : begin data_collision_b_a <= 2'b01; display_wa_wb; end + 6'b101011 : begin display_wa_wb; end + 6'b000001 : begin data_collision_b_a <= 2'b10; display_ra_wb; end + 6'b000101 : begin data_collision_b_a <= 2'b10; display_ra_wb; end + 6'b001001 : begin data_collision_b_a <= 2'b10; display_ra_wb; end + 6'b010001 : begin data_collision_b_a <= 2'b10; display_ra_wb; end + 6'b010101 : begin data_collision_b_a <= 2'b10; display_ra_wb; end + 6'b011001 : begin data_collision_b_a <= 2'b10; display_ra_wb; end + 6'b100001 : begin data_collision_b_a <= 2'b10; display_ra_wb; end + 6'b100101 : begin data_collision_b_a <= 2'b10; display_ra_wb; end + 6'b101001 : begin data_collision_b_a <= 2'b10; display_ra_wb; end + 6'b000010 : begin data_collision_b_a <= 2'b01; display_wa_rb; end + 6'b000110 : begin data_collision_b_a <= 2'b01; display_wa_rb; end + 6'b001010 : begin data_collision_b_a <= 2'b01; display_wa_rb; end +// 6'b010010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end +// 6'b010110 : begin data_collision_b_a <= 2'b00; display_wa_rb; end +// 6'b011010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end + 6'b100010 : begin data_collision_b_a <= 2'b01; display_wa_rb; end + 6'b100110 : begin data_collision_b_a <= 2'b01; display_wa_rb; end + 6'b101010 : begin data_collision_b_a <= 2'b01; display_wa_rb; end + endcase + end + end + setup_all_b_a <= 0; + end + + + always @(posedge setup_zero) begin + if (data_addra_int[14:2] == data_addrb_int[14:2]) begin + if ((ena_int == 1) && (enb_int == 1)) begin + case ({wr_mode_a, wr_mode_b, wea_int, web_int}) + 6'b000011 : begin data_collision <= 2'b11; display_wa_wb; end + 6'b000111 : begin data_collision <= 2'b11; display_wa_wb; end + 6'b001011 : begin data_collision <= 2'b10; display_wa_wb; end + 6'b010011 : begin data_collision <= 2'b11; display_wa_wb; end + 6'b010111 : begin data_collision <= 2'b11; display_wa_wb; end + 6'b011011 : begin data_collision <= 2'b10; display_wa_wb; end + 6'b100011 : begin data_collision <= 2'b01; display_wa_wb; end + 6'b100111 : begin data_collision <= 2'b01; display_wa_wb; end + 6'b101011 : begin display_wa_wb; end + 6'b000001 : begin data_collision <= 2'b10; display_ra_wb; end +// 6'b000101 : begin data_collision <= 2'b00; display_ra_wb; end + 6'b001001 : begin data_collision <= 2'b10; display_ra_wb; end + 6'b010001 : begin data_collision <= 2'b10; display_ra_wb; end +// 6'b010101 : begin data_collision <= 2'b00; display_ra_wb; end + 6'b011001 : begin data_collision <= 2'b10; display_ra_wb; end + 6'b100001 : begin data_collision <= 2'b10; display_ra_wb; end +// 6'b100101 : begin data_collision <= 2'b00; display_ra_wb; end + 6'b101001 : begin data_collision <= 2'b10; display_ra_wb; end + 6'b000010 : begin data_collision <= 2'b01; display_wa_rb; end + 6'b000110 : begin data_collision <= 2'b01; display_wa_rb; end + 6'b001010 : begin data_collision <= 2'b01; display_wa_rb; end +// 6'b010010 : begin data_collision <= 2'b00; display_wa_rb; end +// 6'b010110 : begin data_collision <= 2'b00; display_wa_rb; end +// 6'b011010 : begin data_collision <= 2'b00; display_wa_rb; end + 6'b100010 : begin data_collision <= 2'b01; display_wa_rb; end + 6'b100110 : begin data_collision <= 2'b01; display_wa_rb; end + 6'b101010 : begin data_collision <= 2'b01; display_wa_rb; end + endcase + end + end + setup_zero <= 0; + end + + task display_ra_wb; + begin + if (display_flag) + $display("Memory Collision Error on RAMB16_S1_S4:%m at simulation time %.3f ns\nA read was performed on address %h (hex) of Port A while a write was requested to the same address on Port B. The write will be successful however the read value on Port A is unknown until the next CLKA cycle.", $time/1000.0, addra_int); + end + endtask + + task display_wa_rb; + begin + if (display_flag) + $display("Memory Collision Error on RAMB16_S1_S4:%m at simulation time %.3f ns\nA read was performed on address %h (hex) of Port B while a write was requested to the same address on Port A. The write will be successful however the read value on Port B is unknown until the next CLKB cycle.", $time/1000.0, addrb_int); + end + endtask + + task display_wa_wb; + begin + if (display_flag) + $display("Memory Collision Error on RAMB16_S1_S4:%m at simulation time %.3f ns\nA write was requested to the same address simultaneously at both Port A and Port B of the RAM. The contents written to the RAM at address location %h (hex) of Port A and address location %h (hex) of Port B are unknown.", $time/1000.0, addra_int, addrb_int); + end + endtask + + + always @(posedge setup_rf_a_b) begin + if (data_addra_reg[14:2] == data_addrb_int[14:2]) begin + if ((ena_reg == 1) && (enb_int == 1)) begin + case ({wr_mode_a, wr_mode_b, wea_reg, web_int}) +// 6'b000011 : begin data_collision_a_b <= 2'b00; display_wa_wb; end +// 6'b000111 : begin data_collision_a_b <= 2'b00; display_wa_wb; end +// 6'b001011 : begin data_collision_a_b <= 2'b00; display_wa_wb; end + 6'b010011 : begin data_collision_a_b <= 2'b11; display_wa_wb; end + 6'b010111 : begin data_collision_a_b <= 2'b11; display_wa_wb; end + 6'b011011 : begin data_collision_a_b <= 2'b10; display_wa_wb; end +// 6'b100011 : begin data_collision_a_b <= 2'b00; display_wa_wb; end +// 6'b100111 : begin data_collision_a_b <= 2'b00; display_wa_wb; end +// 6'b101011 : begin data_collision_a_b <= 2'b00; display_wa_wb; end +// 6'b000001 : begin data_collision_a_b <= 2'b00; display_ra_wb; end +// 6'b000101 : begin data_collision_a_b <= 2'b00; display_ra_wb; end +// 6'b001001 : begin data_collision_a_b <= 2'b00; display_ra_wb; end +// 6'b010001 : begin data_collision_a_b <= 2'b00; display_ra_wb; end +// 6'b010101 : begin data_collision_a_b <= 2'b00; display_ra_wb; end +// 6'b011001 : begin data_collision_a_b <= 2'b00; display_ra_wb; end +// 6'b100001 : begin data_collision_a_b <= 2'b00; display_ra_wb; end +// 6'b100101 : begin data_collision_a_b <= 2'b00; display_ra_wb; end +// 6'b101001 : begin data_collision_a_b <= 2'b00; display_ra_wb; end +// 6'b000010 : begin data_collision_a_b <= 2'b00; display_wa_rb; end +// 6'b000110 : begin data_collision_a_b <= 2'b00; display_wa_rb; end +// 6'b001010 : begin data_collision_a_b <= 2'b00; display_wa_rb; end + 6'b010010 : begin data_collision_a_b <= 2'b01; display_wa_rb; end + 6'b010110 : begin data_collision_a_b <= 2'b01; display_wa_rb; end + 6'b011010 : begin data_collision_a_b <= 2'b01; display_wa_rb; end +// 6'b100010 : begin data_collision_a_b <= 2'b00; display_wa_rb; end +// 6'b100110 : begin data_collision_a_b <= 2'b00; display_wa_rb; end +// 6'b101010 : begin data_collision_a_b <= 2'b00; display_wa_rb; end + endcase + end + end + setup_rf_a_b <= 0; + end + + + always @(posedge setup_rf_b_a) begin + if (data_addra_int[14:2] == data_addrb_reg[14:2]) begin + if ((ena_int == 1) && (enb_reg == 1)) begin + case ({wr_mode_a, wr_mode_b, wea_int, web_reg}) +// 6'b000011 : begin data_collision_b_a <= 2'b00; display_wa_wb; end + 6'b000111 : begin data_collision_b_a <= 2'b11; display_wa_wb; end +// 6'b001011 : begin data_collision_b_a <= 2'b00; display_wa_wb; end +// 6'b010011 : begin data_collision_b_a <= 2'b00; display_wa_wb; end + 6'b010111 : begin data_collision_b_a <= 2'b11; display_wa_wb; end +// 6'b011011 : begin data_collision_b_a <= 2'b00; display_wa_wb; end +// 6'b100011 : begin data_collision_b_a <= 2'b00; display_wa_wb; end + 6'b100111 : begin data_collision_b_a <= 2'b01; display_wa_wb; end +// 6'b101011 : begin data_collision_b_a <= 2'b00; display_wa_wb; end +// 6'b000001 : begin data_collision_b_a <= 2'b00; display_ra_wb; end + 6'b000101 : begin data_collision_b_a <= 2'b10; display_ra_wb; end +// 6'b001001 : begin data_collision_b_a <= 2'b00; display_ra_wb; end +// 6'b010001 : begin data_collision_b_a <= 2'b00; display_ra_wb; end + 6'b010101 : begin data_collision_b_a <= 2'b10; display_ra_wb; end +// 6'b011001 : begin data_collision_b_a <= 2'b00; display_ra_wb; end +// 6'b100001 : begin data_collision_b_a <= 2'b00; display_ra_wb; end + 6'b100101 : begin data_collision_b_a <= 2'b10; display_ra_wb; end +// 6'b101001 : begin data_collision_b_a <= 2'b00; display_ra_wb; end +// 6'b000010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end +// 6'b000110 : begin data_collision_b_a <= 2'b00; display_wa_rb; end +// 6'b001010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end +// 6'b010010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end +// 6'b010110 : begin data_collision_b_a <= 2'b00; display_wa_rb; end +// 6'b011010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end +// 6'b100010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end +// 6'b100110 : begin data_collision_b_a <= 2'b00; display_wa_rb; end +// 6'b101010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end + endcase + end + end + setup_rf_b_a <= 0; + end + + + always @(posedge clka_int) begin + if ((output_flag || display_flag)) begin + addra_reg <= addra_int; + ena_reg <= ena_int; + ssra_reg <= ssra_int; + wea_reg <= wea_int; + end + end + + always @(posedge clkb_int) begin + if ((output_flag || display_flag)) begin + addrb_reg <= addrb_int; + enb_reg <= enb_int; + ssrb_reg <= ssrb_int; + web_reg <= web_int; + end + end + + + // Data + always @(posedge memory_collision) begin + if ((output_flag || display_flag)) begin + mem[addra_int[13:2]][addra_int[1:0] * 1 +: 1] <= 1'bx; + memory_collision <= 0; + end + + end + + always @(posedge memory_collision_a_b) begin + if ((output_flag || display_flag)) begin + mem[addra_reg[13:2]][addra_reg[1:0] * 1 +: 1] <= 1'bx; + memory_collision_a_b <= 0; + end + end + + always @(posedge memory_collision_b_a) begin + if ((output_flag || display_flag)) begin + mem[addra_int[13:2]][addra_int[1:0] * 1 +: 1] <= 1'bx; + memory_collision_b_a <= 0; + end + end + + always @(posedge data_collision[1]) begin + if (ssra_int == 0 && output_flag) begin + doa_out <= #100 1'bX; + end + data_collision[1] <= 0; + end + + always @(posedge data_collision[0]) begin + if (ssrb_int == 0 && output_flag) begin + dob_out[addra_int[1:0] * 1 +: 1] <= #100 1'bX; + end + data_collision[0] <= 0; + end + + always @(posedge data_collision_a_b[1]) begin + if (ssra_reg == 0 && output_flag) begin + doa_out <= #100 1'bX; + end + data_collision_a_b[1] <= 0; + end + + always @(posedge data_collision_a_b[0]) begin + if (ssrb_int == 0 && output_flag) begin + dob_out[addra_reg[1:0] * 1 +: 1] <= #100 1'bX; + end + data_collision_a_b[0] <= 0; + end + + always @(posedge data_collision_b_a[1]) begin + if (ssra_int == 0 && output_flag) begin + doa_out <= #100 1'bX; + end + data_collision_b_a[1] <= 0; + end + + always @(posedge data_collision_b_a[0]) begin + if (ssrb_reg == 0 && output_flag) begin + dob_out[addra_int[1:0] * 1 +: 1] <= #100 1'bX; + end + data_collision_b_a[0] <= 0; + end + + + initial begin + case (WRITE_MODE_A) + "WRITE_FIRST" : wr_mode_a <= 2'b00; + "READ_FIRST" : wr_mode_a <= 2'b01; + "NO_CHANGE" : wr_mode_a <= 2'b10; + default : begin + $display("Attribute Syntax Error : The Attribute WRITE_MODE_A on RAMB16_S1_S4 instance %m is set to %s. Legal values for this attribute are WRITE_FIRST, READ_FIRST or NO_CHANGE.", WRITE_MODE_A); + $finish; + end + endcase + end + + initial begin + case (WRITE_MODE_B) + "WRITE_FIRST" : wr_mode_b <= 2'b00; + "READ_FIRST" : wr_mode_b <= 2'b01; + "NO_CHANGE" : wr_mode_b <= 2'b10; + default : begin + $display("Attribute Syntax Error : The Attribute WRITE_MODE_B on RAMB16_S1_S4 instance %m is set to %s. Legal values for this attribute are WRITE_FIRST, READ_FIRST or NO_CHANGE.", WRITE_MODE_B); + $finish; + end + endcase + end + + + // Port A + always @(posedge clka_int) begin + + if (ena_int == 1'b1) begin + + if (ssra_int == 1'b1) begin + {doa_out} <= #100 SRVAL_A; + end + else begin + if (wea_int == 1'b1) begin + if (wr_mode_a == 2'b00) begin + doa_out <= #100 dia_int; + end + else if (wr_mode_a == 2'b01) begin + + doa_out <= #100 mem[addra_int[13:2]][addra_int[1:0] * 1 +: 1]; + + end + end + else begin + + doa_out <= #100 mem[addra_int[13:2]][addra_int[1:0] * 1 +: 1]; + + end + end + + // memory + if (wea_int == 1'b1) begin + mem[addra_int[13:2]][addra_int[1:0] * 1 +: 1] <= dia_int; + end + + end + end + + + // Port B + always @(posedge clkb_int) begin + + if (enb_int == 1'b1) begin + + if (ssrb_int == 1'b1) begin + {dob_out} <= #100 SRVAL_B; + end + else begin + if (web_int == 1'b1) begin + if (wr_mode_b == 2'b00) begin + dob_out <= #100 dib_int; + end + else if (wr_mode_b == 2'b01) begin + dob_out <= #100 mem[addrb_int]; + end + end + else begin + dob_out <= #100 mem[addrb_int]; + end + end + + // memory + if (web_int == 1'b1) begin + mem[addrb_int] <= dib_int; + end + + end + end + + +endmodule + +`endif diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/RAMB16_S1_S9.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/RAMB16_S1_S9.v new file mode 100644 index 0000000..c03cc2c --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/RAMB16_S1_S9.v @@ -0,0 +1,1642 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/RAMB16_S1_S9.v,v 1.10 2007/02/22 01:58:05 wloo Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2005 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / 16K-Bit Data and 2K-Bit Parity Dual Port Block RAM +// /___/ /\ Filename : RAMB16_S1_S9.v +// \ \ / \ Timestamp : Thu Mar 10 16:43:35 PST 2005 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// End Revision + +`ifdef legacy_model + +`timescale 1 ps / 1 ps + +module RAMB16_S1_S9 (DOA, DOB, DOPB, ADDRA, ADDRB, CLKA, CLKB, DIA, DIB, DIPB, ENA, ENB, SSRA, SSRB, WEA, WEB); + + parameter INIT_A = 1'h0; + parameter INIT_B = 9'h0; + parameter SRVAL_A = 1'h0; + parameter SRVAL_B = 9'h0; + parameter WRITE_MODE_A = "WRITE_FIRST"; + parameter WRITE_MODE_B = "WRITE_FIRST"; + parameter SIM_COLLISION_CHECK = "ALL"; + localparam SETUP_ALL = 1000; + localparam SETUP_READ_FIRST = 3000; + + parameter INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + + output [0:0] DOA; + reg [0:0] doa_out; + wire doa_out0; + + input [13:0] ADDRA; + input [0:0] DIA; + input ENA, CLKA, WEA, SSRA; + + output [7:0] DOB; + output [0:0] DOPB; + reg [7:0] dob_out; + reg [0:0] dopb_out; + wire dob_out0, dob_out1, dob_out2, dob_out3, dob_out4, dob_out5, dob_out6, dob_out7; + wire dopb0_out; + + input [10:0] ADDRB; + input [7:0] DIB; + input [0:0] DIPB; + input ENB, CLKB, WEB, SSRB; + + reg [18431:0] mem; + reg [8:0] count; + reg [1:0] wr_mode_a, wr_mode_b; + + reg [5:0] dmi, dbi; + reg [5:0] pmi, pbi; + + wire [13:0] addra_int; + reg [13:0] addra_reg; + wire [0:0] dia_int; + wire ena_int, clka_int, wea_int, ssra_int; + reg ena_reg, wea_reg, ssra_reg; + wire [10:0] addrb_int; + reg [10:0] addrb_reg; + wire [7:0] dib_int; + wire [0:0] dipb_int; + wire enb_int, clkb_int, web_int, ssrb_int; + reg display_flag; + reg enb_reg, web_reg, ssrb_reg; + + time time_clka, time_clkb; + time time_clka_clkb; + time time_clkb_clka; + + reg setup_all_a_b; + reg setup_all_b_a; + reg setup_zero; + reg setup_rf_a_b; + reg setup_rf_b_a; + reg [1:0] data_collision, data_collision_a_b, data_collision_b_a; + reg memory_collision, memory_collision_a_b, memory_collision_b_a; + reg address_collision, address_collision_a_b, address_collision_b_a; + reg change_clka; + reg change_clkb; + + wire [14:0] data_addra_int; + wire [14:0] data_addra_reg; + wire [14:0] data_addrb_int; + wire [14:0] data_addrb_reg; + wire [15:0] parity_addra_int; + wire [15:0] parity_addra_reg; + wire [15:0] parity_addrb_int; + wire [15:0] parity_addrb_reg; + + tri0 GSR = glbl.GSR; + + always @(GSR) + if (GSR) begin + assign doa_out = INIT_A[0:0]; + assign dob_out = INIT_B[7:0]; + assign dopb_out = INIT_B[8:8]; + end + else begin + deassign doa_out; + deassign dob_out; + deassign dopb_out; + end + + buf b_doa_out0 (doa_out0, doa_out[0]); + buf b_dob_out0 (dob_out0, dob_out[0]); + buf b_dob_out1 (dob_out1, dob_out[1]); + buf b_dob_out2 (dob_out2, dob_out[2]); + buf b_dob_out3 (dob_out3, dob_out[3]); + buf b_dob_out4 (dob_out4, dob_out[4]); + buf b_dob_out5 (dob_out5, dob_out[5]); + buf b_dob_out6 (dob_out6, dob_out[6]); + buf b_dob_out7 (dob_out7, dob_out[7]); + buf b_dopb_out0 (dopb_out0, dopb_out[0]); + + buf b_doa0 (DOA[0], doa_out0); + buf b_dob0 (DOB[0], dob_out0); + buf b_dob1 (DOB[1], dob_out1); + buf b_dob2 (DOB[2], dob_out2); + buf b_dob3 (DOB[3], dob_out3); + buf b_dob4 (DOB[4], dob_out4); + buf b_dob5 (DOB[5], dob_out5); + buf b_dob6 (DOB[6], dob_out6); + buf b_dob7 (DOB[7], dob_out7); + buf b_dopb0 (DOPB[0], dopb_out0); + + buf b_addra_0 (addra_int[0], ADDRA[0]); + buf b_addra_1 (addra_int[1], ADDRA[1]); + buf b_addra_2 (addra_int[2], ADDRA[2]); + buf b_addra_3 (addra_int[3], ADDRA[3]); + buf b_addra_4 (addra_int[4], ADDRA[4]); + buf b_addra_5 (addra_int[5], ADDRA[5]); + buf b_addra_6 (addra_int[6], ADDRA[6]); + buf b_addra_7 (addra_int[7], ADDRA[7]); + buf b_addra_8 (addra_int[8], ADDRA[8]); + buf b_addra_9 (addra_int[9], ADDRA[9]); + buf b_addra_10 (addra_int[10], ADDRA[10]); + buf b_addra_11 (addra_int[11], ADDRA[11]); + buf b_addra_12 (addra_int[12], ADDRA[12]); + buf b_addra_13 (addra_int[13], ADDRA[13]); + buf b_dia_0 (dia_int[0], DIA[0]); + buf b_ena (ena_int, ENA); + buf b_clka (clka_int, CLKA); + buf b_ssra (ssra_int, SSRA); + buf b_wea (wea_int, WEA); + buf b_addrb_0 (addrb_int[0], ADDRB[0]); + buf b_addrb_1 (addrb_int[1], ADDRB[1]); + buf b_addrb_2 (addrb_int[2], ADDRB[2]); + buf b_addrb_3 (addrb_int[3], ADDRB[3]); + buf b_addrb_4 (addrb_int[4], ADDRB[4]); + buf b_addrb_5 (addrb_int[5], ADDRB[5]); + buf b_addrb_6 (addrb_int[6], ADDRB[6]); + buf b_addrb_7 (addrb_int[7], ADDRB[7]); + buf b_addrb_8 (addrb_int[8], ADDRB[8]); + buf b_addrb_9 (addrb_int[9], ADDRB[9]); + buf b_addrb_10 (addrb_int[10], ADDRB[10]); + buf b_dib_0 (dib_int[0], DIB[0]); + buf b_dib_1 (dib_int[1], DIB[1]); + buf b_dib_2 (dib_int[2], DIB[2]); + buf b_dib_3 (dib_int[3], DIB[3]); + buf b_dib_4 (dib_int[4], DIB[4]); + buf b_dib_5 (dib_int[5], DIB[5]); + buf b_dib_6 (dib_int[6], DIB[6]); + buf b_dib_7 (dib_int[7], DIB[7]); + buf b_dipb_0 (dipb_int[0], DIPB[0]); + buf b_enb (enb_int, ENB); + buf b_clkb (clkb_int, CLKB); + buf b_ssrb (ssrb_int, SSRB); + buf b_web (web_int, WEB); + + initial begin + for (count = 0; count < 256; count = count + 1) begin + mem[count] <= INIT_00[count]; + mem[256 * 1 + count] <= INIT_01[count]; + mem[256 * 2 + count] <= INIT_02[count]; + mem[256 * 3 + count] <= INIT_03[count]; + mem[256 * 4 + count] <= INIT_04[count]; + mem[256 * 5 + count] <= INIT_05[count]; + mem[256 * 6 + count] <= INIT_06[count]; + mem[256 * 7 + count] <= INIT_07[count]; + mem[256 * 8 + count] <= INIT_08[count]; + mem[256 * 9 + count] <= INIT_09[count]; + mem[256 * 10 + count] <= INIT_0A[count]; + mem[256 * 11 + count] <= INIT_0B[count]; + mem[256 * 12 + count] <= INIT_0C[count]; + mem[256 * 13 + count] <= INIT_0D[count]; + mem[256 * 14 + count] <= INIT_0E[count]; + mem[256 * 15 + count] <= INIT_0F[count]; + mem[256 * 16 + count] <= INIT_10[count]; + mem[256 * 17 + count] <= INIT_11[count]; + mem[256 * 18 + count] <= INIT_12[count]; + mem[256 * 19 + count] <= INIT_13[count]; + mem[256 * 20 + count] <= INIT_14[count]; + mem[256 * 21 + count] <= INIT_15[count]; + mem[256 * 22 + count] <= INIT_16[count]; + mem[256 * 23 + count] <= INIT_17[count]; + mem[256 * 24 + count] <= INIT_18[count]; + mem[256 * 25 + count] <= INIT_19[count]; + mem[256 * 26 + count] <= INIT_1A[count]; + mem[256 * 27 + count] <= INIT_1B[count]; + mem[256 * 28 + count] <= INIT_1C[count]; + mem[256 * 29 + count] <= INIT_1D[count]; + mem[256 * 30 + count] <= INIT_1E[count]; + mem[256 * 31 + count] <= INIT_1F[count]; + mem[256 * 32 + count] <= INIT_20[count]; + mem[256 * 33 + count] <= INIT_21[count]; + mem[256 * 34 + count] <= INIT_22[count]; + mem[256 * 35 + count] <= INIT_23[count]; + mem[256 * 36 + count] <= INIT_24[count]; + mem[256 * 37 + count] <= INIT_25[count]; + mem[256 * 38 + count] <= INIT_26[count]; + mem[256 * 39 + count] <= INIT_27[count]; + mem[256 * 40 + count] <= INIT_28[count]; + mem[256 * 41 + count] <= INIT_29[count]; + mem[256 * 42 + count] <= INIT_2A[count]; + mem[256 * 43 + count] <= INIT_2B[count]; + mem[256 * 44 + count] <= INIT_2C[count]; + mem[256 * 45 + count] <= INIT_2D[count]; + mem[256 * 46 + count] <= INIT_2E[count]; + mem[256 * 47 + count] <= INIT_2F[count]; + mem[256 * 48 + count] <= INIT_30[count]; + mem[256 * 49 + count] <= INIT_31[count]; + mem[256 * 50 + count] <= INIT_32[count]; + mem[256 * 51 + count] <= INIT_33[count]; + mem[256 * 52 + count] <= INIT_34[count]; + mem[256 * 53 + count] <= INIT_35[count]; + mem[256 * 54 + count] <= INIT_36[count]; + mem[256 * 55 + count] <= INIT_37[count]; + mem[256 * 56 + count] <= INIT_38[count]; + mem[256 * 57 + count] <= INIT_39[count]; + mem[256 * 58 + count] <= INIT_3A[count]; + mem[256 * 59 + count] <= INIT_3B[count]; + mem[256 * 60 + count] <= INIT_3C[count]; + mem[256 * 61 + count] <= INIT_3D[count]; + mem[256 * 62 + count] <= INIT_3E[count]; + mem[256 * 63 + count] <= INIT_3F[count]; + mem[256 * 64 + count] <= INITP_00[count]; + mem[256 * 65 + count] <= INITP_01[count]; + mem[256 * 66 + count] <= INITP_02[count]; + mem[256 * 67 + count] <= INITP_03[count]; + mem[256 * 68 + count] <= INITP_04[count]; + mem[256 * 69 + count] <= INITP_05[count]; + mem[256 * 70 + count] <= INITP_06[count]; + mem[256 * 71 + count] <= INITP_07[count]; + end + address_collision <= 0; + address_collision_a_b <= 0; + address_collision_b_a <= 0; + change_clka <= 0; + change_clkb <= 0; + data_collision <= 0; + data_collision_a_b <= 0; + data_collision_b_a <= 0; + memory_collision <= 0; + memory_collision_a_b <= 0; + memory_collision_b_a <= 0; + setup_all_a_b <= 0; + setup_all_b_a <= 0; + setup_zero <= 0; + setup_rf_a_b <= 0; + setup_rf_b_a <= 0; + end + + assign data_addra_int = addra_int * 1; + assign data_addra_reg = addra_reg * 1; + assign data_addrb_int = addrb_int * 8; + assign data_addrb_reg = addrb_reg * 8; + assign parity_addrb_int = 16384 + addrb_int * 1; + assign parity_addrb_reg = 16384 + addrb_reg * 1; + + + initial begin + + display_flag = 1; + + case (SIM_COLLISION_CHECK) + + "NONE" : begin + assign setup_all_a_b = 1'b0; + assign setup_all_b_a = 1'b0; + assign setup_zero = 1'b0; + assign setup_rf_a_b = 1'b0; + assign setup_rf_b_a = 1'b0; + assign display_flag = 0; + end + "WARNING_ONLY" : begin + assign data_collision = 2'b00; + assign data_collision_a_b = 2'b00; + assign data_collision_b_a = 2'b00; + assign memory_collision = 1'b0; + assign memory_collision_a_b = 1'b0; + assign memory_collision_b_a = 1'b0; + end + "GENERATE_X_ONLY" : begin + assign display_flag = 0; + end + "ALL" : ; + default : begin + $display("Attribute Syntax Error : The Attribute SIM_COLLISION_CHECK on RAMB16_S1_S9 instance %m is set to %s. Legal values for this attribute are ALL, NONE, WARNING_ONLY or GENERATE_X_ONLY.", SIM_COLLISION_CHECK); + $finish; + end + + endcase // case(SIM_COLLISION_CHECK) + + end // initial begin + + + always @(posedge clka_int) begin + time_clka = $time; + #0 time_clkb_clka = time_clka - time_clkb; + change_clka = ~change_clka; + end + + always @(posedge clkb_int) begin + time_clkb = $time; + #0 time_clka_clkb = time_clkb - time_clka; + change_clkb = ~change_clkb; + end + + always @(change_clkb) begin + if ((0 < time_clka_clkb) && (time_clka_clkb < SETUP_ALL)) + setup_all_a_b = 1; + if ((0 < time_clka_clkb) && (time_clka_clkb < SETUP_READ_FIRST)) + setup_rf_a_b = 1; + end + + always @(change_clka) begin + if ((0 < time_clkb_clka) && (time_clkb_clka < SETUP_ALL)) + setup_all_b_a = 1; + if ((0 < time_clkb_clka) && (time_clkb_clka < SETUP_READ_FIRST)) + setup_rf_b_a = 1; + end + + always @(change_clkb or change_clka) begin + if ((time_clkb_clka == 0) && (time_clka_clkb == 0)) + setup_zero = 1; + end + + always @(posedge setup_zero) begin + if ((ena_int == 1) && (wea_int == 1) && + (enb_int == 1) && (web_int == 1) && + (data_addra_int[14:3] == data_addrb_int[14:3])) + memory_collision <= 1; + end + + always @(posedge setup_all_a_b or posedge setup_rf_a_b) begin + if ((ena_reg == 1) && (wea_reg == 1) && + (enb_int == 1) && (web_int == 1) && + (data_addra_reg[14:3] == data_addrb_int[14:3])) + memory_collision_a_b <= 1; + end + + always @(posedge setup_all_b_a or posedge setup_rf_b_a) begin + if ((ena_int == 1) && (wea_int == 1) && + (enb_reg == 1) && (web_reg == 1) && + (data_addra_int[14:3] == data_addrb_reg[14:3])) + memory_collision_b_a <= 1; + end + + always @(posedge setup_all_a_b) begin + if (data_addra_reg[14:3] == data_addrb_int[14:3]) begin + if ((ena_reg == 1) && (enb_int == 1)) begin + case ({wr_mode_a, wr_mode_b, wea_reg, web_int}) + 6'b000011 : begin data_collision_a_b <= 2'b11; display_wa_wb; end + 6'b000111 : begin data_collision_a_b <= 2'b11; display_wa_wb; end + 6'b001011 : begin data_collision_a_b <= 2'b10; display_wa_wb; end +// 6'b010011 : begin data_collision_a_b <= 2'b00; display_wa_wb; end +// 6'b010111 : begin data_collision_a_b <= 2'b00; display_wa_wb; end +// 6'b011011 : begin data_collision_a_b <= 2'b00; display_wa_wb; end + 6'b100011 : begin data_collision_a_b <= 2'b01; display_wa_wb; end + 6'b100111 : begin data_collision_a_b <= 2'b01; display_wa_wb; end + 6'b101011 : begin display_wa_wb; end + 6'b000001 : begin data_collision_a_b <= 2'b10; display_ra_wb; end +// 6'b000101 : begin data_collision_a_b <= 2'b00; display_ra_wb; end + 6'b001001 : begin data_collision_a_b <= 2'b10; display_ra_wb; end + 6'b010001 : begin data_collision_a_b <= 2'b10; display_ra_wb; end +// 6'b010101 : begin data_collision_a_b <= 2'b00; display_ra_wb; end + 6'b011001 : begin data_collision_a_b <= 2'b10; display_ra_wb; end + 6'b100001 : begin data_collision_a_b <= 2'b10; display_ra_wb; end +// 6'b100101 : begin data_collision_a_b <= 2'b00; display_ra_wb; end + 6'b101001 : begin data_collision_a_b <= 2'b10; display_ra_wb; end + 6'b000010 : begin data_collision_a_b <= 2'b01; display_wa_rb; end + 6'b000110 : begin data_collision_a_b <= 2'b01; display_wa_rb; end + 6'b001010 : begin data_collision_a_b <= 2'b01; display_wa_rb; end +// 6'b010010 : begin data_collision_a_b <= 2'b00; display_wa_rb; end +// 6'b010110 : begin data_collision_a_b <= 2'b00; display_wa_rb; end +// 6'b011010 : begin data_collision_a_b <= 2'b00; display_wa_rb; end + 6'b100010 : begin data_collision_a_b <= 2'b01; display_wa_rb; end + 6'b100110 : begin data_collision_a_b <= 2'b01; display_wa_rb; end + 6'b101010 : begin data_collision_a_b <= 2'b01; display_wa_rb; end + endcase + end + end + setup_all_a_b <= 0; + end + + + always @(posedge setup_all_b_a) begin + if (data_addra_int[14:3] == data_addrb_reg[14:3]) begin + if ((ena_int == 1) && (enb_reg == 1)) begin + case ({wr_mode_a, wr_mode_b, wea_int, web_reg}) + 6'b000011 : begin data_collision_b_a <= 2'b11; display_wa_wb; end +// 6'b000111 : begin data_collision_b_a <= 2'b00; display_wa_wb; end + 6'b001011 : begin data_collision_b_a <= 2'b10; display_wa_wb; end + 6'b010011 : begin data_collision_b_a <= 2'b11; display_wa_wb; end +// 6'b010111 : begin data_collision_b_a <= 2'b00; display_wa_wb; end + 6'b011011 : begin data_collision_b_a <= 2'b10; display_wa_wb; end + 6'b100011 : begin data_collision_b_a <= 2'b01; display_wa_wb; end + 6'b100111 : begin data_collision_b_a <= 2'b01; display_wa_wb; end + 6'b101011 : begin display_wa_wb; end + 6'b000001 : begin data_collision_b_a <= 2'b10; display_ra_wb; end + 6'b000101 : begin data_collision_b_a <= 2'b10; display_ra_wb; end + 6'b001001 : begin data_collision_b_a <= 2'b10; display_ra_wb; end + 6'b010001 : begin data_collision_b_a <= 2'b10; display_ra_wb; end + 6'b010101 : begin data_collision_b_a <= 2'b10; display_ra_wb; end + 6'b011001 : begin data_collision_b_a <= 2'b10; display_ra_wb; end + 6'b100001 : begin data_collision_b_a <= 2'b10; display_ra_wb; end + 6'b100101 : begin data_collision_b_a <= 2'b10; display_ra_wb; end + 6'b101001 : begin data_collision_b_a <= 2'b10; display_ra_wb; end + 6'b000010 : begin data_collision_b_a <= 2'b01; display_wa_rb; end + 6'b000110 : begin data_collision_b_a <= 2'b01; display_wa_rb; end + 6'b001010 : begin data_collision_b_a <= 2'b01; display_wa_rb; end +// 6'b010010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end +// 6'b010110 : begin data_collision_b_a <= 2'b00; display_wa_rb; end +// 6'b011010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end + 6'b100010 : begin data_collision_b_a <= 2'b01; display_wa_rb; end + 6'b100110 : begin data_collision_b_a <= 2'b01; display_wa_rb; end + 6'b101010 : begin data_collision_b_a <= 2'b01; display_wa_rb; end + endcase + end + end + setup_all_b_a <= 0; + end + + + always @(posedge setup_zero) begin + if (data_addra_int[14:3] == data_addrb_int[14:3]) begin + if ((ena_int == 1) && (enb_int == 1)) begin + case ({wr_mode_a, wr_mode_b, wea_int, web_int}) + 6'b000011 : begin data_collision <= 2'b11; display_wa_wb; end + 6'b000111 : begin data_collision <= 2'b11; display_wa_wb; end + 6'b001011 : begin data_collision <= 2'b10; display_wa_wb; end + 6'b010011 : begin data_collision <= 2'b11; display_wa_wb; end + 6'b010111 : begin data_collision <= 2'b11; display_wa_wb; end + 6'b011011 : begin data_collision <= 2'b10; display_wa_wb; end + 6'b100011 : begin data_collision <= 2'b01; display_wa_wb; end + 6'b100111 : begin data_collision <= 2'b01; display_wa_wb; end + 6'b101011 : begin display_wa_wb; end + 6'b000001 : begin data_collision <= 2'b10; display_ra_wb; end +// 6'b000101 : begin data_collision <= 2'b00; display_ra_wb; end + 6'b001001 : begin data_collision <= 2'b10; display_ra_wb; end + 6'b010001 : begin data_collision <= 2'b10; display_ra_wb; end +// 6'b010101 : begin data_collision <= 2'b00; display_ra_wb; end + 6'b011001 : begin data_collision <= 2'b10; display_ra_wb; end + 6'b100001 : begin data_collision <= 2'b10; display_ra_wb; end +// 6'b100101 : begin data_collision <= 2'b00; display_ra_wb; end + 6'b101001 : begin data_collision <= 2'b10; display_ra_wb; end + 6'b000010 : begin data_collision <= 2'b01; display_wa_rb; end + 6'b000110 : begin data_collision <= 2'b01; display_wa_rb; end + 6'b001010 : begin data_collision <= 2'b01; display_wa_rb; end +// 6'b010010 : begin data_collision <= 2'b00; display_wa_rb; end +// 6'b010110 : begin data_collision <= 2'b00; display_wa_rb; end +// 6'b011010 : begin data_collision <= 2'b00; display_wa_rb; end + 6'b100010 : begin data_collision <= 2'b01; display_wa_rb; end + 6'b100110 : begin data_collision <= 2'b01; display_wa_rb; end + 6'b101010 : begin data_collision <= 2'b01; display_wa_rb; end + endcase + end + end + setup_zero <= 0; + end + + task display_ra_wb; + begin + if (display_flag) + $display("Memory Collision Error on RAMB16_S1_S9:%m at simulation time %.3f ns\nA read was performed on address %h (hex) of Port A while a write was requested to the same address on Port B. The write will be successful however the read value on Port A is unknown until the next CLKA cycle.", $time/1000.0, addra_int); + end + endtask + + task display_wa_rb; + begin + if (display_flag) + $display("Memory Collision Error on RAMB16_S1_S9:%m at simulation time %.3f ns\nA read was performed on address %h (hex) of Port B while a write was requested to the same address on Port A. The write will be successful however the read value on Port B is unknown until the next CLKB cycle.", $time/1000.0, addrb_int); + end + endtask + + task display_wa_wb; + begin + if (display_flag) + $display("Memory Collision Error on RAMB16_S1_S9:%m at simulation time %.3f ns\nA write was requested to the same address simultaneously at both Port A and Port B of the RAM. The contents written to the RAM at address location %h (hex) of Port A and address location %h (hex) of Port B are unknown.", $time/1000.0, addra_int, addrb_int); + end + endtask + + + always @(posedge setup_rf_a_b) begin + if (data_addra_reg[14:3] == data_addrb_int[14:3]) begin + if ((ena_reg == 1) && (enb_int == 1)) begin + case ({wr_mode_a, wr_mode_b, wea_reg, web_int}) +// 6'b000011 : begin data_collision_a_b <= 2'b00; display_wa_wb; end +// 6'b000111 : begin data_collision_a_b <= 2'b00; display_wa_wb; end +// 6'b001011 : begin data_collision_a_b <= 2'b00; display_wa_wb; end + 6'b010011 : begin data_collision_a_b <= 2'b11; display_wa_wb; end + 6'b010111 : begin data_collision_a_b <= 2'b11; display_wa_wb; end + 6'b011011 : begin data_collision_a_b <= 2'b10; display_wa_wb; end +// 6'b100011 : begin data_collision_a_b <= 2'b00; display_wa_wb; end +// 6'b100111 : begin data_collision_a_b <= 2'b00; display_wa_wb; end +// 6'b101011 : begin data_collision_a_b <= 2'b00; display_wa_wb; end +// 6'b000001 : begin data_collision_a_b <= 2'b00; display_ra_wb; end +// 6'b000101 : begin data_collision_a_b <= 2'b00; display_ra_wb; end +// 6'b001001 : begin data_collision_a_b <= 2'b00; display_ra_wb; end +// 6'b010001 : begin data_collision_a_b <= 2'b00; display_ra_wb; end +// 6'b010101 : begin data_collision_a_b <= 2'b00; display_ra_wb; end +// 6'b011001 : begin data_collision_a_b <= 2'b00; display_ra_wb; end +// 6'b100001 : begin data_collision_a_b <= 2'b00; display_ra_wb; end +// 6'b100101 : begin data_collision_a_b <= 2'b00; display_ra_wb; end +// 6'b101001 : begin data_collision_a_b <= 2'b00; display_ra_wb; end +// 6'b000010 : begin data_collision_a_b <= 2'b00; display_wa_rb; end +// 6'b000110 : begin data_collision_a_b <= 2'b00; display_wa_rb; end +// 6'b001010 : begin data_collision_a_b <= 2'b00; display_wa_rb; end + 6'b010010 : begin data_collision_a_b <= 2'b01; display_wa_rb; end + 6'b010110 : begin data_collision_a_b <= 2'b01; display_wa_rb; end + 6'b011010 : begin data_collision_a_b <= 2'b01; display_wa_rb; end +// 6'b100010 : begin data_collision_a_b <= 2'b00; display_wa_rb; end +// 6'b100110 : begin data_collision_a_b <= 2'b00; display_wa_rb; end +// 6'b101010 : begin data_collision_a_b <= 2'b00; display_wa_rb; end + endcase + end + end + setup_rf_a_b <= 0; + end + + + always @(posedge setup_rf_b_a) begin + if (data_addra_int[14:3] == data_addrb_reg[14:3]) begin + if ((ena_int == 1) && (enb_reg == 1)) begin + case ({wr_mode_a, wr_mode_b, wea_int, web_reg}) +// 6'b000011 : begin data_collision_b_a <= 2'b00; display_wa_wb; end + 6'b000111 : begin data_collision_b_a <= 2'b11; display_wa_wb; end +// 6'b001011 : begin data_collision_b_a <= 2'b00; display_wa_wb; end +// 6'b010011 : begin data_collision_b_a <= 2'b00; display_wa_wb; end + 6'b010111 : begin data_collision_b_a <= 2'b11; display_wa_wb; end +// 6'b011011 : begin data_collision_b_a <= 2'b00; display_wa_wb; end +// 6'b100011 : begin data_collision_b_a <= 2'b00; display_wa_wb; end + 6'b100111 : begin data_collision_b_a <= 2'b01; display_wa_wb; end +// 6'b101011 : begin data_collision_b_a <= 2'b00; display_wa_wb; end +// 6'b000001 : begin data_collision_b_a <= 2'b00; display_ra_wb; end + 6'b000101 : begin data_collision_b_a <= 2'b10; display_ra_wb; end +// 6'b001001 : begin data_collision_b_a <= 2'b00; display_ra_wb; end +// 6'b010001 : begin data_collision_b_a <= 2'b00; display_ra_wb; end + 6'b010101 : begin data_collision_b_a <= 2'b10; display_ra_wb; end +// 6'b011001 : begin data_collision_b_a <= 2'b00; display_ra_wb; end +// 6'b100001 : begin data_collision_b_a <= 2'b00; display_ra_wb; end + 6'b100101 : begin data_collision_b_a <= 2'b10; display_ra_wb; end +// 6'b101001 : begin data_collision_b_a <= 2'b00; display_ra_wb; end +// 6'b000010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end +// 6'b000110 : begin data_collision_b_a <= 2'b00; display_wa_rb; end +// 6'b001010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end +// 6'b010010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end +// 6'b010110 : begin data_collision_b_a <= 2'b00; display_wa_rb; end +// 6'b011010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end +// 6'b100010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end +// 6'b100110 : begin data_collision_b_a <= 2'b00; display_wa_rb; end +// 6'b101010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end + endcase + end + end + setup_rf_b_a <= 0; + end + + + always @(posedge clka_int) begin + addra_reg <= addra_int; + ena_reg <= ena_int; + ssra_reg <= ssra_int; + wea_reg <= wea_int; + end + + always @(posedge clkb_int) begin + addrb_reg <= addrb_int; + enb_reg <= enb_int; + ssrb_reg <= ssrb_int; + web_reg <= web_int; + end + + // Data + always @(posedge memory_collision) begin + for (dmi = 0; dmi < 1; dmi = dmi + 1) begin + mem[data_addra_int + dmi] <= 1'bX; + end + memory_collision <= 0; + end + + always @(posedge memory_collision_a_b) begin + for (dmi = 0; dmi < 1; dmi = dmi + 1) begin + mem[data_addra_reg + dmi] <= 1'bX; + end + memory_collision_a_b <= 0; + end + + always @(posedge memory_collision_b_a) begin + for (dmi = 0; dmi < 1; dmi = dmi + 1) begin + mem[data_addra_int + dmi] <= 1'bX; + end + memory_collision_b_a <= 0; + end + + always @(posedge data_collision[1]) begin + if (ssra_int == 0) begin + doa_out <= 1'bX; + end + data_collision[1] <= 0; + end + + always @(posedge data_collision[0]) begin + if (ssrb_int == 0) begin + for (dbi = 0; dbi < 1; dbi = dbi + 1) begin + dob_out[data_addra_int[2 : 0] + dbi] <= 1'bX; + end + end + data_collision[0] <= 0; + end + + always @(posedge data_collision_a_b[1]) begin + if (ssra_reg == 0) begin + doa_out <= 1'bX; + end + data_collision_a_b[1] <= 0; + end + + always @(posedge data_collision_a_b[0]) begin + if (ssrb_int == 0) begin + for (dbi = 0; dbi < 1; dbi = dbi + 1) begin + dob_out[data_addra_reg[2 : 0] + dbi] <= 1'bX; + end + end + data_collision_a_b[0] <= 0; + end + + always @(posedge data_collision_b_a[1]) begin + if (ssra_int == 0) begin + doa_out <= 1'bX; + end + data_collision_b_a[1] <= 0; + end + + always @(posedge data_collision_b_a[0]) begin + if (ssrb_reg == 0) begin + for (dbi = 0; dbi < 1; dbi = dbi + 1) begin + dob_out[data_addra_int[2 : 0] + dbi] <= 1'bX; + end + end + data_collision_b_a[0] <= 0; + end + + + initial begin + case (WRITE_MODE_A) + "WRITE_FIRST" : wr_mode_a <= 2'b00; + "READ_FIRST" : wr_mode_a <= 2'b01; + "NO_CHANGE" : wr_mode_a <= 2'b10; + default : begin + $display("Attribute Syntax Error : The Attribute WRITE_MODE_A on RAMB16_S1_S9 instance %m is set to %s. Legal values for this attribute are WRITE_FIRST, READ_FIRST or NO_CHANGE.", WRITE_MODE_A); + $finish; + end + endcase + end + + initial begin + case (WRITE_MODE_B) + "WRITE_FIRST" : wr_mode_b <= 2'b00; + "READ_FIRST" : wr_mode_b <= 2'b01; + "NO_CHANGE" : wr_mode_b <= 2'b10; + default : begin + $display("Attribute Syntax Error : The Attribute WRITE_MODE_B on RAMB16_S1_S9 instance %m is set to %s. Legal values for this attribute are WRITE_FIRST, READ_FIRST or NO_CHANGE.", WRITE_MODE_B); + $finish; + end + endcase + end + + // Port A + always @(posedge clka_int) begin + if (ena_int == 1'b1) begin + if (ssra_int == 1'b1) begin + doa_out[0] <= SRVAL_A[0]; + end + else begin + if (wea_int == 1'b1) begin + if (wr_mode_a == 2'b00) begin + doa_out <= dia_int; + end + else if (wr_mode_a == 2'b01) begin + doa_out[0] <= mem[data_addra_int + 0]; + end + end + else begin + doa_out[0] <= mem[data_addra_int + 0]; + end + end + end + end + + always @(posedge clka_int) begin + if (ena_int == 1'b1 && wea_int == 1'b1) begin + mem[data_addra_int + 0] <= dia_int[0]; + end + end + + // Port B + always @(posedge clkb_int) begin + if (enb_int == 1'b1) begin + if (ssrb_int == 1'b1) begin + dob_out[0] <= SRVAL_B[0]; + dob_out[1] <= SRVAL_B[1]; + dob_out[2] <= SRVAL_B[2]; + dob_out[3] <= SRVAL_B[3]; + dob_out[4] <= SRVAL_B[4]; + dob_out[5] <= SRVAL_B[5]; + dob_out[6] <= SRVAL_B[6]; + dob_out[7] <= SRVAL_B[7]; + dopb_out[0] <= SRVAL_B[8]; + end + else begin + if (web_int == 1'b1) begin + if (wr_mode_b == 2'b00) begin + dob_out <= dib_int; + dopb_out <= dipb_int; + end + else if (wr_mode_b == 2'b01) begin + dob_out[0] <= mem[data_addrb_int + 0]; + dob_out[1] <= mem[data_addrb_int + 1]; + dob_out[2] <= mem[data_addrb_int + 2]; + dob_out[3] <= mem[data_addrb_int + 3]; + dob_out[4] <= mem[data_addrb_int + 4]; + dob_out[5] <= mem[data_addrb_int + 5]; + dob_out[6] <= mem[data_addrb_int + 6]; + dob_out[7] <= mem[data_addrb_int + 7]; + dopb_out[0] <= mem[parity_addrb_int + 0]; + end + end + else begin + dob_out[0] <= mem[data_addrb_int + 0]; + dob_out[1] <= mem[data_addrb_int + 1]; + dob_out[2] <= mem[data_addrb_int + 2]; + dob_out[3] <= mem[data_addrb_int + 3]; + dob_out[4] <= mem[data_addrb_int + 4]; + dob_out[5] <= mem[data_addrb_int + 5]; + dob_out[6] <= mem[data_addrb_int + 6]; + dob_out[7] <= mem[data_addrb_int + 7]; + dopb_out[0] <= mem[parity_addrb_int + 0]; + end + end + end + end + + always @(posedge clkb_int) begin + if (enb_int == 1'b1 && web_int == 1'b1) begin + mem[data_addrb_int + 0] <= dib_int[0]; + mem[data_addrb_int + 1] <= dib_int[1]; + mem[data_addrb_int + 2] <= dib_int[2]; + mem[data_addrb_int + 3] <= dib_int[3]; + mem[data_addrb_int + 4] <= dib_int[4]; + mem[data_addrb_int + 5] <= dib_int[5]; + mem[data_addrb_int + 6] <= dib_int[6]; + mem[data_addrb_int + 7] <= dib_int[7]; + mem[parity_addrb_int + 0] <= dipb_int[0]; + end + end + + specify + (CLKA *> DOA) = (100, 100); + (CLKB *> DOB) = (100, 100); + (CLKB *> DOPB) = (100, 100); + endspecify + +endmodule + +`else + +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/RAMB16_S1_S9.v,v 1.10 2007/02/22 01:58:05 wloo Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2005 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Timing Simulation Library Component +// / / 16K-Bit Data and 2K-Bit Parity Dual Port Block RAM +// /___/ /\ Filename : RAMB16_S1_S9.v +// \ \ / \ Timestamp : Thu Mar 10 16:44:01 PST 2005 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 03/10/05 - Initialized outputs. +// 02/21/07 - Fixed parameter SIM_COLLISION_CHECK (CR 433281). +// End Revision + +`timescale 1 ps/1 ps + +module RAMB16_S1_S9 (DOA, DOB, DOPB, ADDRA, ADDRB, CLKA, CLKB, DIA, DIB, DIPB, ENA, ENB, SSRA, SSRB, WEA, WEB); + + parameter INIT_A = 1'h0; + parameter INIT_B = 9'h0; + parameter SRVAL_A = 1'h0; + parameter SRVAL_B = 9'h0; + parameter WRITE_MODE_A = "WRITE_FIRST"; + parameter WRITE_MODE_B = "WRITE_FIRST"; + parameter SIM_COLLISION_CHECK = "ALL"; + localparam SETUP_ALL = 1000; + localparam SETUP_READ_FIRST = 3000; + + parameter INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + + output [0:0] DOA; + output [7:0] DOB; + output [0:0] DOPB; + + input [13:0] ADDRA; + input [0:0] DIA; + input ENA, CLKA, WEA, SSRA; + input [10:0] ADDRB; + input [7:0] DIB; + input [0:0] DIPB; + input ENB, CLKB, WEB, SSRB; + + reg [0:0] doa_out = INIT_A[0:0]; + reg [7:0] dob_out = INIT_B[7:0]; + reg [0:0] dopb_out = INIT_B[8:8]; + + reg [7:0] mem [2047:0]; + reg [0:0] memp [2047:0]; + + reg [8:0] count, countp; + reg [1:0] wr_mode_a, wr_mode_b; + + reg [5:0] dmi, dbi; + reg [5:0] pmi, pbi; + + wire [13:0] addra_int; + reg [13:0] addra_reg; + wire [0:0] dia_int; + wire ena_int, clka_int, wea_int, ssra_int; + reg ena_reg, wea_reg, ssra_reg; + wire [10:0] addrb_int; + reg [10:0] addrb_reg; + wire [7:0] dib_int; + wire [0:0] dipb_int; + wire enb_int, clkb_int, web_int, ssrb_int; + reg display_flag, output_flag; + reg enb_reg, web_reg, ssrb_reg; + + time time_clka, time_clkb; + time time_clka_clkb; + time time_clkb_clka; + + reg setup_all_a_b; + reg setup_all_b_a; + reg setup_zero; + reg setup_rf_a_b; + reg setup_rf_b_a; + reg [1:0] data_collision, data_collision_a_b, data_collision_b_a; + reg memory_collision, memory_collision_a_b, memory_collision_b_a; + reg change_clka; + reg change_clkb; + + wire [14:0] data_addra_int; + wire [14:0] data_addra_reg; + wire [14:0] data_addrb_int; + wire [14:0] data_addrb_reg; + + wire dia_enable = ena_int && wea_int; + wire dib_enable = enb_int && web_int; + + tri0 GSR = glbl.GSR; + wire gsr_int; + + buf b_gsr (gsr_int, GSR); + + buf b_doa [0:0] (DOA, doa_out); + buf b_addra [13:0] (addra_int, ADDRA); + buf b_dia [0:0] (dia_int, DIA); + buf b_ena (ena_int, ENA); + buf b_clka (clka_int, CLKA); + buf b_ssra (ssra_int, SSRA); + buf b_wea (wea_int, WEA); + + buf b_dob [7:0] (DOB, dob_out); + buf b_dopb [0:0] (DOPB, dopb_out); + buf b_addrb [10:0] (addrb_int, ADDRB); + buf b_dib [7:0] (dib_int, DIB); + buf b_dipb [0:0] (dipb_int, DIPB); + buf b_enb (enb_int, ENB); + buf b_clkb (clkb_int, CLKB); + buf b_ssrb (ssrb_int, SSRB); + buf b_web (web_int, WEB); + + + always @(gsr_int) + if (gsr_int) begin + assign {doa_out} = INIT_A; + assign {dopb_out, dob_out} = INIT_B; + end + else begin + deassign doa_out; + deassign dob_out; + deassign dopb_out; + end + + + initial begin + + for (count = 0; count < 32; count = count + 1) begin + mem[count] = INIT_00[(count * 8) +: 8]; + mem[32 * 1 + count] = INIT_01[(count * 8) +: 8]; + mem[32 * 2 + count] = INIT_02[(count * 8) +: 8]; + mem[32 * 3 + count] = INIT_03[(count * 8) +: 8]; + mem[32 * 4 + count] = INIT_04[(count * 8) +: 8]; + mem[32 * 5 + count] = INIT_05[(count * 8) +: 8]; + mem[32 * 6 + count] = INIT_06[(count * 8) +: 8]; + mem[32 * 7 + count] = INIT_07[(count * 8) +: 8]; + mem[32 * 8 + count] = INIT_08[(count * 8) +: 8]; + mem[32 * 9 + count] = INIT_09[(count * 8) +: 8]; + mem[32 * 10 + count] = INIT_0A[(count * 8) +: 8]; + mem[32 * 11 + count] = INIT_0B[(count * 8) +: 8]; + mem[32 * 12 + count] = INIT_0C[(count * 8) +: 8]; + mem[32 * 13 + count] = INIT_0D[(count * 8) +: 8]; + mem[32 * 14 + count] = INIT_0E[(count * 8) +: 8]; + mem[32 * 15 + count] = INIT_0F[(count * 8) +: 8]; + mem[32 * 16 + count] = INIT_10[(count * 8) +: 8]; + mem[32 * 17 + count] = INIT_11[(count * 8) +: 8]; + mem[32 * 18 + count] = INIT_12[(count * 8) +: 8]; + mem[32 * 19 + count] = INIT_13[(count * 8) +: 8]; + mem[32 * 20 + count] = INIT_14[(count * 8) +: 8]; + mem[32 * 21 + count] = INIT_15[(count * 8) +: 8]; + mem[32 * 22 + count] = INIT_16[(count * 8) +: 8]; + mem[32 * 23 + count] = INIT_17[(count * 8) +: 8]; + mem[32 * 24 + count] = INIT_18[(count * 8) +: 8]; + mem[32 * 25 + count] = INIT_19[(count * 8) +: 8]; + mem[32 * 26 + count] = INIT_1A[(count * 8) +: 8]; + mem[32 * 27 + count] = INIT_1B[(count * 8) +: 8]; + mem[32 * 28 + count] = INIT_1C[(count * 8) +: 8]; + mem[32 * 29 + count] = INIT_1D[(count * 8) +: 8]; + mem[32 * 30 + count] = INIT_1E[(count * 8) +: 8]; + mem[32 * 31 + count] = INIT_1F[(count * 8) +: 8]; + mem[32 * 32 + count] = INIT_20[(count * 8) +: 8]; + mem[32 * 33 + count] = INIT_21[(count * 8) +: 8]; + mem[32 * 34 + count] = INIT_22[(count * 8) +: 8]; + mem[32 * 35 + count] = INIT_23[(count * 8) +: 8]; + mem[32 * 36 + count] = INIT_24[(count * 8) +: 8]; + mem[32 * 37 + count] = INIT_25[(count * 8) +: 8]; + mem[32 * 38 + count] = INIT_26[(count * 8) +: 8]; + mem[32 * 39 + count] = INIT_27[(count * 8) +: 8]; + mem[32 * 40 + count] = INIT_28[(count * 8) +: 8]; + mem[32 * 41 + count] = INIT_29[(count * 8) +: 8]; + mem[32 * 42 + count] = INIT_2A[(count * 8) +: 8]; + mem[32 * 43 + count] = INIT_2B[(count * 8) +: 8]; + mem[32 * 44 + count] = INIT_2C[(count * 8) +: 8]; + mem[32 * 45 + count] = INIT_2D[(count * 8) +: 8]; + mem[32 * 46 + count] = INIT_2E[(count * 8) +: 8]; + mem[32 * 47 + count] = INIT_2F[(count * 8) +: 8]; + mem[32 * 48 + count] = INIT_30[(count * 8) +: 8]; + mem[32 * 49 + count] = INIT_31[(count * 8) +: 8]; + mem[32 * 50 + count] = INIT_32[(count * 8) +: 8]; + mem[32 * 51 + count] = INIT_33[(count * 8) +: 8]; + mem[32 * 52 + count] = INIT_34[(count * 8) +: 8]; + mem[32 * 53 + count] = INIT_35[(count * 8) +: 8]; + mem[32 * 54 + count] = INIT_36[(count * 8) +: 8]; + mem[32 * 55 + count] = INIT_37[(count * 8) +: 8]; + mem[32 * 56 + count] = INIT_38[(count * 8) +: 8]; + mem[32 * 57 + count] = INIT_39[(count * 8) +: 8]; + mem[32 * 58 + count] = INIT_3A[(count * 8) +: 8]; + mem[32 * 59 + count] = INIT_3B[(count * 8) +: 8]; + mem[32 * 60 + count] = INIT_3C[(count * 8) +: 8]; + mem[32 * 61 + count] = INIT_3D[(count * 8) +: 8]; + mem[32 * 62 + count] = INIT_3E[(count * 8) +: 8]; + mem[32 * 63 + count] = INIT_3F[(count * 8) +: 8]; + end + +// initiate parity start + for (countp = 0; countp < 256; countp = countp + 1) begin + memp[countp] = INITP_00[(countp * 1) +: 1]; + memp[256 * 1 + countp] = INITP_01[(countp * 1) +: 1]; + memp[256 * 2 + countp] = INITP_02[(countp * 1) +: 1]; + memp[256 * 3 + countp] = INITP_03[(countp * 1) +: 1]; + memp[256 * 4 + countp] = INITP_04[(countp * 1) +: 1]; + memp[256 * 5 + countp] = INITP_05[(countp * 1) +: 1]; + memp[256 * 6 + countp] = INITP_06[(countp * 1) +: 1]; + memp[256 * 7 + countp] = INITP_07[(countp * 1) +: 1]; + end +// initiate parity end + + change_clka <= 0; + change_clkb <= 0; + data_collision <= 0; + data_collision_a_b <= 0; + data_collision_b_a <= 0; + memory_collision <= 0; + memory_collision_a_b <= 0; + memory_collision_b_a <= 0; + setup_all_a_b <= 0; + setup_all_b_a <= 0; + setup_zero <= 0; + setup_rf_a_b <= 0; + setup_rf_b_a <= 0; + end + + assign data_addra_int = addra_int * 1; + assign data_addra_reg = addra_reg * 1; + assign data_addrb_int = addrb_int * 8; + assign data_addrb_reg = addrb_reg * 8; + + + initial begin + + display_flag = 1; + output_flag = 1; + + case (SIM_COLLISION_CHECK) + + "NONE" : begin + output_flag = 0; + display_flag = 0; + end + "WARNING_ONLY" : output_flag = 0; + "GENERATE_X_ONLY" : display_flag = 0; + "ALL" : ; + + default : begin + $display("Attribute Syntax Error : The Attribute SIM_COLLISION_CHECK on RAMB16_S1_S9 instance %m is set to %s. Legal values for this attribute are ALL, NONE, WARNING_ONLY or GENERATE_X_ONLY.", SIM_COLLISION_CHECK); + $finish; + end + + endcase // case(SIM_COLLISION_CHECK) + + end // initial begin + + + always @(posedge clka_int) begin + if ((output_flag || display_flag)) begin + time_clka = $time; + #0 time_clkb_clka = time_clka - time_clkb; + change_clka = ~change_clka; + end + end + + always @(posedge clkb_int) begin + if ((output_flag || display_flag)) begin + time_clkb = $time; + #0 time_clka_clkb = time_clkb - time_clka; + change_clkb = ~change_clkb; + end + end + + always @(change_clkb) begin + if ((0 < time_clka_clkb) && (time_clka_clkb < SETUP_ALL)) + setup_all_a_b = 1; + if ((0 < time_clka_clkb) && (time_clka_clkb < SETUP_READ_FIRST)) + setup_rf_a_b = 1; + end + + always @(change_clka) begin + if ((0 < time_clkb_clka) && (time_clkb_clka < SETUP_ALL)) + setup_all_b_a = 1; + if ((0 < time_clkb_clka) && (time_clkb_clka < SETUP_READ_FIRST)) + setup_rf_b_a = 1; + end + + always @(change_clkb or change_clka) begin + if ((time_clkb_clka == 0) && (time_clka_clkb == 0)) + setup_zero = 1; + end + + always @(posedge setup_zero) begin + if ((ena_int == 1) && (wea_int == 1) && + (enb_int == 1) && (web_int == 1) && + (data_addra_int[14:3] == data_addrb_int[14:3])) + memory_collision <= 1; + end + + always @(posedge setup_all_a_b or posedge setup_rf_a_b) begin + if ((ena_reg == 1) && (wea_reg == 1) && + (enb_int == 1) && (web_int == 1) && + (data_addra_reg[14:3] == data_addrb_int[14:3])) + memory_collision_a_b <= 1; + end + + always @(posedge setup_all_b_a or posedge setup_rf_b_a) begin + if ((ena_int == 1) && (wea_int == 1) && + (enb_reg == 1) && (web_reg == 1) && + (data_addra_int[14:3] == data_addrb_reg[14:3])) + memory_collision_b_a <= 1; + end + + always @(posedge setup_all_a_b) begin + if (data_addra_reg[14:3] == data_addrb_int[14:3]) begin + if ((ena_reg == 1) && (enb_int == 1)) begin + case ({wr_mode_a, wr_mode_b, wea_reg, web_int}) + 6'b000011 : begin data_collision_a_b <= 2'b11; display_wa_wb; end + 6'b000111 : begin data_collision_a_b <= 2'b11; display_wa_wb; end + 6'b001011 : begin data_collision_a_b <= 2'b10; display_wa_wb; end +// 6'b010011 : begin data_collision_a_b <= 2'b00; display_wa_wb; end +// 6'b010111 : begin data_collision_a_b <= 2'b00; display_wa_wb; end +// 6'b011011 : begin data_collision_a_b <= 2'b00; display_wa_wb; end + 6'b100011 : begin data_collision_a_b <= 2'b01; display_wa_wb; end + 6'b100111 : begin data_collision_a_b <= 2'b01; display_wa_wb; end + 6'b101011 : begin display_wa_wb; end + 6'b000001 : begin data_collision_a_b <= 2'b10; display_ra_wb; end +// 6'b000101 : begin data_collision_a_b <= 2'b00; display_ra_wb; end + 6'b001001 : begin data_collision_a_b <= 2'b10; display_ra_wb; end + 6'b010001 : begin data_collision_a_b <= 2'b10; display_ra_wb; end +// 6'b010101 : begin data_collision_a_b <= 2'b00; display_ra_wb; end + 6'b011001 : begin data_collision_a_b <= 2'b10; display_ra_wb; end + 6'b100001 : begin data_collision_a_b <= 2'b10; display_ra_wb; end +// 6'b100101 : begin data_collision_a_b <= 2'b00; display_ra_wb; end + 6'b101001 : begin data_collision_a_b <= 2'b10; display_ra_wb; end + 6'b000010 : begin data_collision_a_b <= 2'b01; display_wa_rb; end + 6'b000110 : begin data_collision_a_b <= 2'b01; display_wa_rb; end + 6'b001010 : begin data_collision_a_b <= 2'b01; display_wa_rb; end +// 6'b010010 : begin data_collision_a_b <= 2'b00; display_wa_rb; end +// 6'b010110 : begin data_collision_a_b <= 2'b00; display_wa_rb; end +// 6'b011010 : begin data_collision_a_b <= 2'b00; display_wa_rb; end + 6'b100010 : begin data_collision_a_b <= 2'b01; display_wa_rb; end + 6'b100110 : begin data_collision_a_b <= 2'b01; display_wa_rb; end + 6'b101010 : begin data_collision_a_b <= 2'b01; display_wa_rb; end + endcase + end + end + setup_all_a_b <= 0; + end + + + always @(posedge setup_all_b_a) begin + if (data_addra_int[14:3] == data_addrb_reg[14:3]) begin + if ((ena_int == 1) && (enb_reg == 1)) begin + case ({wr_mode_a, wr_mode_b, wea_int, web_reg}) + 6'b000011 : begin data_collision_b_a <= 2'b11; display_wa_wb; end +// 6'b000111 : begin data_collision_b_a <= 2'b00; display_wa_wb; end + 6'b001011 : begin data_collision_b_a <= 2'b10; display_wa_wb; end + 6'b010011 : begin data_collision_b_a <= 2'b11; display_wa_wb; end +// 6'b010111 : begin data_collision_b_a <= 2'b00; display_wa_wb; end + 6'b011011 : begin data_collision_b_a <= 2'b10; display_wa_wb; end + 6'b100011 : begin data_collision_b_a <= 2'b01; display_wa_wb; end + 6'b100111 : begin data_collision_b_a <= 2'b01; display_wa_wb; end + 6'b101011 : begin display_wa_wb; end + 6'b000001 : begin data_collision_b_a <= 2'b10; display_ra_wb; end + 6'b000101 : begin data_collision_b_a <= 2'b10; display_ra_wb; end + 6'b001001 : begin data_collision_b_a <= 2'b10; display_ra_wb; end + 6'b010001 : begin data_collision_b_a <= 2'b10; display_ra_wb; end + 6'b010101 : begin data_collision_b_a <= 2'b10; display_ra_wb; end + 6'b011001 : begin data_collision_b_a <= 2'b10; display_ra_wb; end + 6'b100001 : begin data_collision_b_a <= 2'b10; display_ra_wb; end + 6'b100101 : begin data_collision_b_a <= 2'b10; display_ra_wb; end + 6'b101001 : begin data_collision_b_a <= 2'b10; display_ra_wb; end + 6'b000010 : begin data_collision_b_a <= 2'b01; display_wa_rb; end + 6'b000110 : begin data_collision_b_a <= 2'b01; display_wa_rb; end + 6'b001010 : begin data_collision_b_a <= 2'b01; display_wa_rb; end +// 6'b010010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end +// 6'b010110 : begin data_collision_b_a <= 2'b00; display_wa_rb; end +// 6'b011010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end + 6'b100010 : begin data_collision_b_a <= 2'b01; display_wa_rb; end + 6'b100110 : begin data_collision_b_a <= 2'b01; display_wa_rb; end + 6'b101010 : begin data_collision_b_a <= 2'b01; display_wa_rb; end + endcase + end + end + setup_all_b_a <= 0; + end + + + always @(posedge setup_zero) begin + if (data_addra_int[14:3] == data_addrb_int[14:3]) begin + if ((ena_int == 1) && (enb_int == 1)) begin + case ({wr_mode_a, wr_mode_b, wea_int, web_int}) + 6'b000011 : begin data_collision <= 2'b11; display_wa_wb; end + 6'b000111 : begin data_collision <= 2'b11; display_wa_wb; end + 6'b001011 : begin data_collision <= 2'b10; display_wa_wb; end + 6'b010011 : begin data_collision <= 2'b11; display_wa_wb; end + 6'b010111 : begin data_collision <= 2'b11; display_wa_wb; end + 6'b011011 : begin data_collision <= 2'b10; display_wa_wb; end + 6'b100011 : begin data_collision <= 2'b01; display_wa_wb; end + 6'b100111 : begin data_collision <= 2'b01; display_wa_wb; end + 6'b101011 : begin display_wa_wb; end + 6'b000001 : begin data_collision <= 2'b10; display_ra_wb; end +// 6'b000101 : begin data_collision <= 2'b00; display_ra_wb; end + 6'b001001 : begin data_collision <= 2'b10; display_ra_wb; end + 6'b010001 : begin data_collision <= 2'b10; display_ra_wb; end +// 6'b010101 : begin data_collision <= 2'b00; display_ra_wb; end + 6'b011001 : begin data_collision <= 2'b10; display_ra_wb; end + 6'b100001 : begin data_collision <= 2'b10; display_ra_wb; end +// 6'b100101 : begin data_collision <= 2'b00; display_ra_wb; end + 6'b101001 : begin data_collision <= 2'b10; display_ra_wb; end + 6'b000010 : begin data_collision <= 2'b01; display_wa_rb; end + 6'b000110 : begin data_collision <= 2'b01; display_wa_rb; end + 6'b001010 : begin data_collision <= 2'b01; display_wa_rb; end +// 6'b010010 : begin data_collision <= 2'b00; display_wa_rb; end +// 6'b010110 : begin data_collision <= 2'b00; display_wa_rb; end +// 6'b011010 : begin data_collision <= 2'b00; display_wa_rb; end + 6'b100010 : begin data_collision <= 2'b01; display_wa_rb; end + 6'b100110 : begin data_collision <= 2'b01; display_wa_rb; end + 6'b101010 : begin data_collision <= 2'b01; display_wa_rb; end + endcase + end + end + setup_zero <= 0; + end + + task display_ra_wb; + begin + if (display_flag) + $display("Memory Collision Error on RAMB16_S1_S9:%m at simulation time %.3f ns\nA read was performed on address %h (hex) of Port A while a write was requested to the same address on Port B. The write will be successful however the read value on Port A is unknown until the next CLKA cycle.", $time/1000.0, addra_int); + end + endtask + + task display_wa_rb; + begin + if (display_flag) + $display("Memory Collision Error on RAMB16_S1_S9:%m at simulation time %.3f ns\nA read was performed on address %h (hex) of Port B while a write was requested to the same address on Port A. The write will be successful however the read value on Port B is unknown until the next CLKB cycle.", $time/1000.0, addrb_int); + end + endtask + + task display_wa_wb; + begin + if (display_flag) + $display("Memory Collision Error on RAMB16_S1_S9:%m at simulation time %.3f ns\nA write was requested to the same address simultaneously at both Port A and Port B of the RAM. The contents written to the RAM at address location %h (hex) of Port A and address location %h (hex) of Port B are unknown.", $time/1000.0, addra_int, addrb_int); + end + endtask + + + always @(posedge setup_rf_a_b) begin + if (data_addra_reg[14:3] == data_addrb_int[14:3]) begin + if ((ena_reg == 1) && (enb_int == 1)) begin + case ({wr_mode_a, wr_mode_b, wea_reg, web_int}) +// 6'b000011 : begin data_collision_a_b <= 2'b00; display_wa_wb; end +// 6'b000111 : begin data_collision_a_b <= 2'b00; display_wa_wb; end +// 6'b001011 : begin data_collision_a_b <= 2'b00; display_wa_wb; end + 6'b010011 : begin data_collision_a_b <= 2'b11; display_wa_wb; end + 6'b010111 : begin data_collision_a_b <= 2'b11; display_wa_wb; end + 6'b011011 : begin data_collision_a_b <= 2'b10; display_wa_wb; end +// 6'b100011 : begin data_collision_a_b <= 2'b00; display_wa_wb; end +// 6'b100111 : begin data_collision_a_b <= 2'b00; display_wa_wb; end +// 6'b101011 : begin data_collision_a_b <= 2'b00; display_wa_wb; end +// 6'b000001 : begin data_collision_a_b <= 2'b00; display_ra_wb; end +// 6'b000101 : begin data_collision_a_b <= 2'b00; display_ra_wb; end +// 6'b001001 : begin data_collision_a_b <= 2'b00; display_ra_wb; end +// 6'b010001 : begin data_collision_a_b <= 2'b00; display_ra_wb; end +// 6'b010101 : begin data_collision_a_b <= 2'b00; display_ra_wb; end +// 6'b011001 : begin data_collision_a_b <= 2'b00; display_ra_wb; end +// 6'b100001 : begin data_collision_a_b <= 2'b00; display_ra_wb; end +// 6'b100101 : begin data_collision_a_b <= 2'b00; display_ra_wb; end +// 6'b101001 : begin data_collision_a_b <= 2'b00; display_ra_wb; end +// 6'b000010 : begin data_collision_a_b <= 2'b00; display_wa_rb; end +// 6'b000110 : begin data_collision_a_b <= 2'b00; display_wa_rb; end +// 6'b001010 : begin data_collision_a_b <= 2'b00; display_wa_rb; end + 6'b010010 : begin data_collision_a_b <= 2'b01; display_wa_rb; end + 6'b010110 : begin data_collision_a_b <= 2'b01; display_wa_rb; end + 6'b011010 : begin data_collision_a_b <= 2'b01; display_wa_rb; end +// 6'b100010 : begin data_collision_a_b <= 2'b00; display_wa_rb; end +// 6'b100110 : begin data_collision_a_b <= 2'b00; display_wa_rb; end +// 6'b101010 : begin data_collision_a_b <= 2'b00; display_wa_rb; end + endcase + end + end + setup_rf_a_b <= 0; + end + + + always @(posedge setup_rf_b_a) begin + if (data_addra_int[14:3] == data_addrb_reg[14:3]) begin + if ((ena_int == 1) && (enb_reg == 1)) begin + case ({wr_mode_a, wr_mode_b, wea_int, web_reg}) +// 6'b000011 : begin data_collision_b_a <= 2'b00; display_wa_wb; end + 6'b000111 : begin data_collision_b_a <= 2'b11; display_wa_wb; end +// 6'b001011 : begin data_collision_b_a <= 2'b00; display_wa_wb; end +// 6'b010011 : begin data_collision_b_a <= 2'b00; display_wa_wb; end + 6'b010111 : begin data_collision_b_a <= 2'b11; display_wa_wb; end +// 6'b011011 : begin data_collision_b_a <= 2'b00; display_wa_wb; end +// 6'b100011 : begin data_collision_b_a <= 2'b00; display_wa_wb; end + 6'b100111 : begin data_collision_b_a <= 2'b01; display_wa_wb; end +// 6'b101011 : begin data_collision_b_a <= 2'b00; display_wa_wb; end +// 6'b000001 : begin data_collision_b_a <= 2'b00; display_ra_wb; end + 6'b000101 : begin data_collision_b_a <= 2'b10; display_ra_wb; end +// 6'b001001 : begin data_collision_b_a <= 2'b00; display_ra_wb; end +// 6'b010001 : begin data_collision_b_a <= 2'b00; display_ra_wb; end + 6'b010101 : begin data_collision_b_a <= 2'b10; display_ra_wb; end +// 6'b011001 : begin data_collision_b_a <= 2'b00; display_ra_wb; end +// 6'b100001 : begin data_collision_b_a <= 2'b00; display_ra_wb; end + 6'b100101 : begin data_collision_b_a <= 2'b10; display_ra_wb; end +// 6'b101001 : begin data_collision_b_a <= 2'b00; display_ra_wb; end +// 6'b000010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end +// 6'b000110 : begin data_collision_b_a <= 2'b00; display_wa_rb; end +// 6'b001010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end +// 6'b010010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end +// 6'b010110 : begin data_collision_b_a <= 2'b00; display_wa_rb; end +// 6'b011010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end +// 6'b100010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end +// 6'b100110 : begin data_collision_b_a <= 2'b00; display_wa_rb; end +// 6'b101010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end + endcase + end + end + setup_rf_b_a <= 0; + end + + + always @(posedge clka_int) begin + if ((output_flag || display_flag)) begin + addra_reg <= addra_int; + ena_reg <= ena_int; + ssra_reg <= ssra_int; + wea_reg <= wea_int; + end + end + + always @(posedge clkb_int) begin + if ((output_flag || display_flag)) begin + addrb_reg <= addrb_int; + enb_reg <= enb_int; + ssrb_reg <= ssrb_int; + web_reg <= web_int; + end + end + + + // Data + always @(posedge memory_collision) begin + if ((output_flag || display_flag)) begin + mem[addra_int[13:3]][addra_int[2:0] * 1 +: 1] <= 1'bx; + memory_collision <= 0; + end + + end + + always @(posedge memory_collision_a_b) begin + if ((output_flag || display_flag)) begin + mem[addra_reg[13:3]][addra_reg[2:0] * 1 +: 1] <= 1'bx; + memory_collision_a_b <= 0; + end + end + + always @(posedge memory_collision_b_a) begin + if ((output_flag || display_flag)) begin + mem[addra_int[13:3]][addra_int[2:0] * 1 +: 1] <= 1'bx; + memory_collision_b_a <= 0; + end + end + + always @(posedge data_collision[1]) begin + if (ssra_int == 0 && output_flag) begin + doa_out <= #100 1'bX; + end + data_collision[1] <= 0; + end + + always @(posedge data_collision[0]) begin + if (ssrb_int == 0 && output_flag) begin + dob_out[addra_int[2:0] * 1 +: 1] <= #100 1'bX; + end + data_collision[0] <= 0; + end + + always @(posedge data_collision_a_b[1]) begin + if (ssra_reg == 0 && output_flag) begin + doa_out <= #100 1'bX; + end + data_collision_a_b[1] <= 0; + end + + always @(posedge data_collision_a_b[0]) begin + if (ssrb_int == 0 && output_flag) begin + dob_out[addra_reg[2:0] * 1 +: 1] <= #100 1'bX; + end + data_collision_a_b[0] <= 0; + end + + always @(posedge data_collision_b_a[1]) begin + if (ssra_int == 0 && output_flag) begin + doa_out <= #100 1'bX; + end + data_collision_b_a[1] <= 0; + end + + always @(posedge data_collision_b_a[0]) begin + if (ssrb_reg == 0 && output_flag) begin + dob_out[addra_int[2:0] * 1 +: 1] <= #100 1'bX; + end + data_collision_b_a[0] <= 0; + end + + + initial begin + case (WRITE_MODE_A) + "WRITE_FIRST" : wr_mode_a <= 2'b00; + "READ_FIRST" : wr_mode_a <= 2'b01; + "NO_CHANGE" : wr_mode_a <= 2'b10; + default : begin + $display("Attribute Syntax Error : The Attribute WRITE_MODE_A on RAMB16_S1_S9 instance %m is set to %s. Legal values for this attribute are WRITE_FIRST, READ_FIRST or NO_CHANGE.", WRITE_MODE_A); + $finish; + end + endcase + end + + initial begin + case (WRITE_MODE_B) + "WRITE_FIRST" : wr_mode_b <= 2'b00; + "READ_FIRST" : wr_mode_b <= 2'b01; + "NO_CHANGE" : wr_mode_b <= 2'b10; + default : begin + $display("Attribute Syntax Error : The Attribute WRITE_MODE_B on RAMB16_S1_S9 instance %m is set to %s. Legal values for this attribute are WRITE_FIRST, READ_FIRST or NO_CHANGE.", WRITE_MODE_B); + $finish; + end + endcase + end + + + // Port A + always @(posedge clka_int) begin + + if (ena_int == 1'b1) begin + + if (ssra_int == 1'b1) begin + {doa_out} <= #100 SRVAL_A; + end + else begin + if (wea_int == 1'b1) begin + if (wr_mode_a == 2'b00) begin + doa_out <= #100 dia_int; + end + else if (wr_mode_a == 2'b01) begin + + doa_out <= #100 mem[addra_int[13:3]][addra_int[2:0] * 1 +: 1]; + + end + end + else begin + + doa_out <= #100 mem[addra_int[13:3]][addra_int[2:0] * 1 +: 1]; + + end + end + + // memory + if (wea_int == 1'b1) begin + mem[addra_int[13:3]][addra_int[2:0] * 1 +: 1] <= dia_int; + end + + end + end + + + // Port B + always @(posedge clkb_int) begin + + if (enb_int == 1'b1) begin + + if (ssrb_int == 1'b1) begin + {dopb_out, dob_out} <= #100 SRVAL_B; + end + else begin + if (web_int == 1'b1) begin + if (wr_mode_b == 2'b00) begin + dob_out <= #100 dib_int; + dopb_out <= #100 dipb_int; + end + else if (wr_mode_b == 2'b01) begin + dob_out <= #100 mem[addrb_int]; + dopb_out <= #100 memp[addrb_int]; + end + end + else begin + dob_out <= #100 mem[addrb_int]; + dopb_out <= #100 memp[addrb_int]; + end + end + + // memory + if (web_int == 1'b1) begin + mem[addrb_int] <= dib_int; + memp[addrb_int] <= dipb_int; + end + + end + end + + +endmodule + +`endif diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/RAMB16_S2.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/RAMB16_S2.v new file mode 100644 index 0000000..1b91bf2 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/RAMB16_S2.v @@ -0,0 +1,521 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/RAMB16_S2.v,v 1.7 2005/03/14 22:54:41 wloo Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2005 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / 16K-Bit Data and 2K-Bit Parity Single Port Block RAM +// /___/ /\ Filename : RAMB16_S2.v +// \ \ / \ Timestamp : Thu Mar 10 16:43:35 PST 2005 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// End Revision + +`ifdef legacy_model + +`timescale 1 ps / 1 ps + +module RAMB16_S2 (DO, ADDR, CLK, DI, EN, SSR, WE); + + parameter INIT = 2'h0; + parameter SRVAL = 2'h0; + parameter WRITE_MODE = "WRITE_FIRST"; + + parameter INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + + output [1:0] DO; + reg do0_out, do1_out; + + input [12:0] ADDR; + input [1:0] DI; + input EN, CLK, WE, SSR; + + reg [18431:0] mem; + reg [8:0] count; + reg [1:0] wr_mode; + + wire [12:0] addr_int; + wire [1:0] di_int; + wire en_int, clk_int, we_int, ssr_int; + + tri0 GSR = glbl.GSR; + + always @(GSR) + if (GSR) begin + assign do0_out = INIT[0]; + assign do1_out = INIT[1]; + end + else begin + deassign do0_out; + deassign do1_out; + end + + buf b_do_out0 (DO[0], do0_out); + buf b_do_out1 (DO[1], do1_out); + buf b_addr_0 (addr_int[0], ADDR[0]); + buf b_addr_1 (addr_int[1], ADDR[1]); + buf b_addr_2 (addr_int[2], ADDR[2]); + buf b_addr_3 (addr_int[3], ADDR[3]); + buf b_addr_4 (addr_int[4], ADDR[4]); + buf b_addr_5 (addr_int[5], ADDR[5]); + buf b_addr_6 (addr_int[6], ADDR[6]); + buf b_addr_7 (addr_int[7], ADDR[7]); + buf b_addr_8 (addr_int[8], ADDR[8]); + buf b_addr_9 (addr_int[9], ADDR[9]); + buf b_addr_10 (addr_int[10], ADDR[10]); + buf b_addr_11 (addr_int[11], ADDR[11]); + buf b_addr_12 (addr_int[12], ADDR[12]); + buf b_di_0 (di_int[0], DI[0]); + buf b_di_1 (di_int[1], DI[1]); + buf b_en (en_int, EN); + buf b_clk (clk_int, CLK); + buf b_we (we_int, WE); + buf b_ssr (ssr_int, SSR); + + initial begin + for (count = 0; count < 256; count = count + 1) begin + mem[count] <= INIT_00[count]; + mem[256 * 1 + count] <= INIT_01[count]; + mem[256 * 2 + count] <= INIT_02[count]; + mem[256 * 3 + count] <= INIT_03[count]; + mem[256 * 4 + count] <= INIT_04[count]; + mem[256 * 5 + count] <= INIT_05[count]; + mem[256 * 6 + count] <= INIT_06[count]; + mem[256 * 7 + count] <= INIT_07[count]; + mem[256 * 8 + count] <= INIT_08[count]; + mem[256 * 9 + count] <= INIT_09[count]; + mem[256 * 10 + count] <= INIT_0A[count]; + mem[256 * 11 + count] <= INIT_0B[count]; + mem[256 * 12 + count] <= INIT_0C[count]; + mem[256 * 13 + count] <= INIT_0D[count]; + mem[256 * 14 + count] <= INIT_0E[count]; + mem[256 * 15 + count] <= INIT_0F[count]; + mem[256 * 16 + count] <= INIT_10[count]; + mem[256 * 17 + count] <= INIT_11[count]; + mem[256 * 18 + count] <= INIT_12[count]; + mem[256 * 19 + count] <= INIT_13[count]; + mem[256 * 20 + count] <= INIT_14[count]; + mem[256 * 21 + count] <= INIT_15[count]; + mem[256 * 22 + count] <= INIT_16[count]; + mem[256 * 23 + count] <= INIT_17[count]; + mem[256 * 24 + count] <= INIT_18[count]; + mem[256 * 25 + count] <= INIT_19[count]; + mem[256 * 26 + count] <= INIT_1A[count]; + mem[256 * 27 + count] <= INIT_1B[count]; + mem[256 * 28 + count] <= INIT_1C[count]; + mem[256 * 29 + count] <= INIT_1D[count]; + mem[256 * 30 + count] <= INIT_1E[count]; + mem[256 * 31 + count] <= INIT_1F[count]; + mem[256 * 32 + count] <= INIT_20[count]; + mem[256 * 33 + count] <= INIT_21[count]; + mem[256 * 34 + count] <= INIT_22[count]; + mem[256 * 35 + count] <= INIT_23[count]; + mem[256 * 36 + count] <= INIT_24[count]; + mem[256 * 37 + count] <= INIT_25[count]; + mem[256 * 38 + count] <= INIT_26[count]; + mem[256 * 39 + count] <= INIT_27[count]; + mem[256 * 40 + count] <= INIT_28[count]; + mem[256 * 41 + count] <= INIT_29[count]; + mem[256 * 42 + count] <= INIT_2A[count]; + mem[256 * 43 + count] <= INIT_2B[count]; + mem[256 * 44 + count] <= INIT_2C[count]; + mem[256 * 45 + count] <= INIT_2D[count]; + mem[256 * 46 + count] <= INIT_2E[count]; + mem[256 * 47 + count] <= INIT_2F[count]; + mem[256 * 48 + count] <= INIT_30[count]; + mem[256 * 49 + count] <= INIT_31[count]; + mem[256 * 50 + count] <= INIT_32[count]; + mem[256 * 51 + count] <= INIT_33[count]; + mem[256 * 52 + count] <= INIT_34[count]; + mem[256 * 53 + count] <= INIT_35[count]; + mem[256 * 54 + count] <= INIT_36[count]; + mem[256 * 55 + count] <= INIT_37[count]; + mem[256 * 56 + count] <= INIT_38[count]; + mem[256 * 57 + count] <= INIT_39[count]; + mem[256 * 58 + count] <= INIT_3A[count]; + mem[256 * 59 + count] <= INIT_3B[count]; + mem[256 * 60 + count] <= INIT_3C[count]; + mem[256 * 61 + count] <= INIT_3D[count]; + mem[256 * 62 + count] <= INIT_3E[count]; + mem[256 * 63 + count] <= INIT_3F[count]; + end + end + + initial begin + case (WRITE_MODE) + "WRITE_FIRST" : wr_mode <= 2'b00; + "READ_FIRST" : wr_mode <= 2'b01; + "NO_CHANGE" : wr_mode <= 2'b10; + default : begin + $display("Attribute Syntax Error : The attribute WRITE_MODE on RAMB16_S2 instance %m is set to %s. Legal values for this attribute are WRITE_FIRST, READ_FIRST or NO_CHANGE.", WRITE_MODE); + $finish; + end + endcase + end + + always @(posedge clk_int) begin + if (en_int == 1'b1) begin + if (ssr_int == 1'b1) begin + do0_out <= SRVAL[0]; + do1_out <= SRVAL[1]; + end + else begin + if (we_int == 1'b1) begin + if (wr_mode == 2'b00) begin + do0_out <= di_int[0]; + do1_out <= di_int[1]; + end + else if (wr_mode == 2'b01) begin + do0_out <= mem[addr_int * 2 + 0]; + do1_out <= mem[addr_int * 2 + 1]; + end + else begin + do0_out <= do0_out; + do1_out <= do1_out; + end + end + else begin + do0_out <= mem[addr_int * 2 + 0]; + do1_out <= mem[addr_int * 2 + 1]; + end + end + end + end + + always @(posedge clk_int) begin + if (en_int == 1'b1 && we_int == 1'b1) begin + mem[addr_int * 2 + 0] <= di_int[0]; + mem[addr_int * 2 + 1] <= di_int[1]; + end + end + + specify + (CLK *> DO) = (100, 100); + endspecify + +endmodule + +`else + +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/RAMB16_S2.v,v 1.7 2005/03/14 22:54:41 wloo Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2005 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Timing Simulation Library Component +// / / 16K-Bit Data and 2K-Bit Parity Single Port Block RAM +// /___/ /\ Filename : RAMB16_S2.v +// \ \ / \ Timestamp : Thu Mar 10 16:44:01 PST 2005 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 03/10/05 - Initialized outputs. +// End Revision + +`timescale 1 ps/1 ps + +module RAMB16_S2 (DO, ADDR, CLK, DI, EN, SSR, WE); + + parameter INIT = 2'h0; + parameter SRVAL = 2'h0; + parameter WRITE_MODE = "WRITE_FIRST"; + + parameter INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + + output [1:0] DO; + + input [12:0] ADDR; + input [1:0] DI; + input EN, CLK, WE, SSR; + + reg [1:0] do_out = INIT[1:0]; + + reg [1:0] mem [8191:0]; + + reg [8:0] count, countp; + reg [1:0] wr_mode; + + wire [12:0] addr_int; + wire [1:0] di_int; + wire en_int, clk_int, we_int, ssr_int; + + wire di_enable = en_int && we_int; + + tri0 GSR = glbl.GSR; + wire gsr_int; + + buf b_gsr (gsr_int, GSR); + + buf b_do [1:0] (DO, do_out); + buf b_addr [12:0] (addr_int, ADDR); + buf b_di [1:0] (di_int, DI); + buf b_en (en_int, EN); + buf b_clk (clk_int, CLK); + buf b_ssr (ssr_int, SSR); + buf b_we (we_int, WE); + + + always @(gsr_int) + if (gsr_int) begin + assign {do_out} = INIT; + end + else begin + deassign do_out; + end + + + initial begin + + for (count = 0; count < 128; count = count + 1) begin + mem[count] = INIT_00[(count * 2) +: 2]; + mem[128 * 1 + count] = INIT_01[(count * 2) +: 2]; + mem[128 * 2 + count] = INIT_02[(count * 2) +: 2]; + mem[128 * 3 + count] = INIT_03[(count * 2) +: 2]; + mem[128 * 4 + count] = INIT_04[(count * 2) +: 2]; + mem[128 * 5 + count] = INIT_05[(count * 2) +: 2]; + mem[128 * 6 + count] = INIT_06[(count * 2) +: 2]; + mem[128 * 7 + count] = INIT_07[(count * 2) +: 2]; + mem[128 * 8 + count] = INIT_08[(count * 2) +: 2]; + mem[128 * 9 + count] = INIT_09[(count * 2) +: 2]; + mem[128 * 10 + count] = INIT_0A[(count * 2) +: 2]; + mem[128 * 11 + count] = INIT_0B[(count * 2) +: 2]; + mem[128 * 12 + count] = INIT_0C[(count * 2) +: 2]; + mem[128 * 13 + count] = INIT_0D[(count * 2) +: 2]; + mem[128 * 14 + count] = INIT_0E[(count * 2) +: 2]; + mem[128 * 15 + count] = INIT_0F[(count * 2) +: 2]; + mem[128 * 16 + count] = INIT_10[(count * 2) +: 2]; + mem[128 * 17 + count] = INIT_11[(count * 2) +: 2]; + mem[128 * 18 + count] = INIT_12[(count * 2) +: 2]; + mem[128 * 19 + count] = INIT_13[(count * 2) +: 2]; + mem[128 * 20 + count] = INIT_14[(count * 2) +: 2]; + mem[128 * 21 + count] = INIT_15[(count * 2) +: 2]; + mem[128 * 22 + count] = INIT_16[(count * 2) +: 2]; + mem[128 * 23 + count] = INIT_17[(count * 2) +: 2]; + mem[128 * 24 + count] = INIT_18[(count * 2) +: 2]; + mem[128 * 25 + count] = INIT_19[(count * 2) +: 2]; + mem[128 * 26 + count] = INIT_1A[(count * 2) +: 2]; + mem[128 * 27 + count] = INIT_1B[(count * 2) +: 2]; + mem[128 * 28 + count] = INIT_1C[(count * 2) +: 2]; + mem[128 * 29 + count] = INIT_1D[(count * 2) +: 2]; + mem[128 * 30 + count] = INIT_1E[(count * 2) +: 2]; + mem[128 * 31 + count] = INIT_1F[(count * 2) +: 2]; + mem[128 * 32 + count] = INIT_20[(count * 2) +: 2]; + mem[128 * 33 + count] = INIT_21[(count * 2) +: 2]; + mem[128 * 34 + count] = INIT_22[(count * 2) +: 2]; + mem[128 * 35 + count] = INIT_23[(count * 2) +: 2]; + mem[128 * 36 + count] = INIT_24[(count * 2) +: 2]; + mem[128 * 37 + count] = INIT_25[(count * 2) +: 2]; + mem[128 * 38 + count] = INIT_26[(count * 2) +: 2]; + mem[128 * 39 + count] = INIT_27[(count * 2) +: 2]; + mem[128 * 40 + count] = INIT_28[(count * 2) +: 2]; + mem[128 * 41 + count] = INIT_29[(count * 2) +: 2]; + mem[128 * 42 + count] = INIT_2A[(count * 2) +: 2]; + mem[128 * 43 + count] = INIT_2B[(count * 2) +: 2]; + mem[128 * 44 + count] = INIT_2C[(count * 2) +: 2]; + mem[128 * 45 + count] = INIT_2D[(count * 2) +: 2]; + mem[128 * 46 + count] = INIT_2E[(count * 2) +: 2]; + mem[128 * 47 + count] = INIT_2F[(count * 2) +: 2]; + mem[128 * 48 + count] = INIT_30[(count * 2) +: 2]; + mem[128 * 49 + count] = INIT_31[(count * 2) +: 2]; + mem[128 * 50 + count] = INIT_32[(count * 2) +: 2]; + mem[128 * 51 + count] = INIT_33[(count * 2) +: 2]; + mem[128 * 52 + count] = INIT_34[(count * 2) +: 2]; + mem[128 * 53 + count] = INIT_35[(count * 2) +: 2]; + mem[128 * 54 + count] = INIT_36[(count * 2) +: 2]; + mem[128 * 55 + count] = INIT_37[(count * 2) +: 2]; + mem[128 * 56 + count] = INIT_38[(count * 2) +: 2]; + mem[128 * 57 + count] = INIT_39[(count * 2) +: 2]; + mem[128 * 58 + count] = INIT_3A[(count * 2) +: 2]; + mem[128 * 59 + count] = INIT_3B[(count * 2) +: 2]; + mem[128 * 60 + count] = INIT_3C[(count * 2) +: 2]; + mem[128 * 61 + count] = INIT_3D[(count * 2) +: 2]; + mem[128 * 62 + count] = INIT_3E[(count * 2) +: 2]; + mem[128 * 63 + count] = INIT_3F[(count * 2) +: 2]; + end + + end // initial begin + + + initial begin + case (WRITE_MODE) + "WRITE_FIRST" : wr_mode <= 2'b00; + "READ_FIRST" : wr_mode <= 2'b01; + "NO_CHANGE" : wr_mode <= 2'b10; + default : begin + $display("Attribute Syntax Error : The Attribute WRITE_MODE on RAMB16_S2 instance %m is set to %s. Legal values for this attribute are WRITE_FIRST, READ_FIRST or NO_CHANGE.", WRITE_MODE); + $finish; + end + endcase + end + + + always @(posedge clk_int) begin + + if (en_int == 1'b1) begin + + if (ssr_int == 1'b1) begin + {do_out} <= #100 SRVAL; + end + else begin + if (we_int == 1'b1) begin + if (wr_mode == 2'b00) begin + do_out <= #100 di_int; + end + else if (wr_mode == 2'b01) begin + do_out <= #100 mem[addr_int]; + end + end + else begin + do_out <= #100 mem[addr_int]; + end + end + + // memory + if (we_int == 1'b1) begin + mem[addr_int] <= di_int; + end + + end + end + + +endmodule + +`endif diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/RAMB16_S2_S18.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/RAMB16_S2_S18.v new file mode 100644 index 0000000..6fb301b --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/RAMB16_S2_S18.v @@ -0,0 +1,1710 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/RAMB16_S2_S18.v,v 1.10 2007/02/22 01:58:05 wloo Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2005 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / 16K-Bit Data and 2K-Bit Parity Dual Port Block RAM +// /___/ /\ Filename : RAMB16_S2_S18.v +// \ \ / \ Timestamp : Thu Mar 10 16:43:36 PST 2005 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// End Revision + +`ifdef legacy_model + +`timescale 1 ps / 1 ps + +module RAMB16_S2_S18 (DOA, DOB, DOPB, ADDRA, ADDRB, CLKA, CLKB, DIA, DIB, DIPB, ENA, ENB, SSRA, SSRB, WEA, WEB); + + parameter INIT_A = 2'h0; + parameter INIT_B = 18'h0; + parameter SRVAL_A = 2'h0; + parameter SRVAL_B = 18'h0; + parameter WRITE_MODE_A = "WRITE_FIRST"; + parameter WRITE_MODE_B = "WRITE_FIRST"; + parameter SIM_COLLISION_CHECK = "ALL"; + localparam SETUP_ALL = 1000; + localparam SETUP_READ_FIRST = 3000; + + parameter INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + + output [1:0] DOA; + reg [1:0] doa_out; + wire doa_out0, doa_out1; + + input [12:0] ADDRA; + input [1:0] DIA; + input ENA, CLKA, WEA, SSRA; + + output [15:0] DOB; + output [1:0] DOPB; + reg [15:0] dob_out; + reg [1:0] dopb_out; + wire dob_out0, dob_out1, dob_out2, dob_out3, dob_out4, dob_out5, dob_out6, dob_out7, dob_out8, dob_out9, dob_out10, dob_out11, dob_out12, dob_out13, dob_out14, dob_out15; + wire dopb0_out, dopb1_out; + + input [9:0] ADDRB; + input [15:0] DIB; + input [1:0] DIPB; + input ENB, CLKB, WEB, SSRB; + + reg [18431:0] mem; + reg [8:0] count; + reg [1:0] wr_mode_a, wr_mode_b; + + reg [5:0] dmi, dbi; + reg [5:0] pmi, pbi; + + wire [12:0] addra_int; + reg [12:0] addra_reg; + wire [1:0] dia_int; + wire ena_int, clka_int, wea_int, ssra_int; + reg ena_reg, wea_reg, ssra_reg; + wire [9:0] addrb_int; + reg [9:0] addrb_reg; + wire [15:0] dib_int; + wire [1:0] dipb_int; + wire enb_int, clkb_int, web_int, ssrb_int; + reg display_flag; + reg enb_reg, web_reg, ssrb_reg; + + time time_clka, time_clkb; + time time_clka_clkb; + time time_clkb_clka; + + reg setup_all_a_b; + reg setup_all_b_a; + reg setup_zero; + reg setup_rf_a_b; + reg setup_rf_b_a; + reg [1:0] data_collision, data_collision_a_b, data_collision_b_a; + reg memory_collision, memory_collision_a_b, memory_collision_b_a; + reg address_collision, address_collision_a_b, address_collision_b_a; + reg change_clka; + reg change_clkb; + + wire [14:0] data_addra_int; + wire [14:0] data_addra_reg; + wire [14:0] data_addrb_int; + wire [14:0] data_addrb_reg; + wire [15:0] parity_addra_int; + wire [15:0] parity_addra_reg; + wire [15:0] parity_addrb_int; + wire [15:0] parity_addrb_reg; + + tri0 GSR = glbl.GSR; + + always @(GSR) + if (GSR) begin + assign doa_out = INIT_A[1:0]; + assign dob_out = INIT_B[15:0]; + assign dopb_out = INIT_B[17:16]; + end + else begin + deassign doa_out; + deassign dob_out; + deassign dopb_out; + end + + buf b_doa_out0 (doa_out0, doa_out[0]); + buf b_doa_out1 (doa_out1, doa_out[1]); + buf b_dob_out0 (dob_out0, dob_out[0]); + buf b_dob_out1 (dob_out1, dob_out[1]); + buf b_dob_out2 (dob_out2, dob_out[2]); + buf b_dob_out3 (dob_out3, dob_out[3]); + buf b_dob_out4 (dob_out4, dob_out[4]); + buf b_dob_out5 (dob_out5, dob_out[5]); + buf b_dob_out6 (dob_out6, dob_out[6]); + buf b_dob_out7 (dob_out7, dob_out[7]); + buf b_dob_out8 (dob_out8, dob_out[8]); + buf b_dob_out9 (dob_out9, dob_out[9]); + buf b_dob_out10 (dob_out10, dob_out[10]); + buf b_dob_out11 (dob_out11, dob_out[11]); + buf b_dob_out12 (dob_out12, dob_out[12]); + buf b_dob_out13 (dob_out13, dob_out[13]); + buf b_dob_out14 (dob_out14, dob_out[14]); + buf b_dob_out15 (dob_out15, dob_out[15]); + buf b_dopb_out0 (dopb_out0, dopb_out[0]); + buf b_dopb_out1 (dopb_out1, dopb_out[1]); + + buf b_doa0 (DOA[0], doa_out0); + buf b_doa1 (DOA[1], doa_out1); + buf b_dob0 (DOB[0], dob_out0); + buf b_dob1 (DOB[1], dob_out1); + buf b_dob2 (DOB[2], dob_out2); + buf b_dob3 (DOB[3], dob_out3); + buf b_dob4 (DOB[4], dob_out4); + buf b_dob5 (DOB[5], dob_out5); + buf b_dob6 (DOB[6], dob_out6); + buf b_dob7 (DOB[7], dob_out7); + buf b_dob8 (DOB[8], dob_out8); + buf b_dob9 (DOB[9], dob_out9); + buf b_dob10 (DOB[10], dob_out10); + buf b_dob11 (DOB[11], dob_out11); + buf b_dob12 (DOB[12], dob_out12); + buf b_dob13 (DOB[13], dob_out13); + buf b_dob14 (DOB[14], dob_out14); + buf b_dob15 (DOB[15], dob_out15); + buf b_dopb0 (DOPB[0], dopb_out0); + buf b_dopb1 (DOPB[1], dopb_out1); + + buf b_addra_0 (addra_int[0], ADDRA[0]); + buf b_addra_1 (addra_int[1], ADDRA[1]); + buf b_addra_2 (addra_int[2], ADDRA[2]); + buf b_addra_3 (addra_int[3], ADDRA[3]); + buf b_addra_4 (addra_int[4], ADDRA[4]); + buf b_addra_5 (addra_int[5], ADDRA[5]); + buf b_addra_6 (addra_int[6], ADDRA[6]); + buf b_addra_7 (addra_int[7], ADDRA[7]); + buf b_addra_8 (addra_int[8], ADDRA[8]); + buf b_addra_9 (addra_int[9], ADDRA[9]); + buf b_addra_10 (addra_int[10], ADDRA[10]); + buf b_addra_11 (addra_int[11], ADDRA[11]); + buf b_addra_12 (addra_int[12], ADDRA[12]); + buf b_dia_0 (dia_int[0], DIA[0]); + buf b_dia_1 (dia_int[1], DIA[1]); + buf b_ena (ena_int, ENA); + buf b_clka (clka_int, CLKA); + buf b_ssra (ssra_int, SSRA); + buf b_wea (wea_int, WEA); + buf b_addrb_0 (addrb_int[0], ADDRB[0]); + buf b_addrb_1 (addrb_int[1], ADDRB[1]); + buf b_addrb_2 (addrb_int[2], ADDRB[2]); + buf b_addrb_3 (addrb_int[3], ADDRB[3]); + buf b_addrb_4 (addrb_int[4], ADDRB[4]); + buf b_addrb_5 (addrb_int[5], ADDRB[5]); + buf b_addrb_6 (addrb_int[6], ADDRB[6]); + buf b_addrb_7 (addrb_int[7], ADDRB[7]); + buf b_addrb_8 (addrb_int[8], ADDRB[8]); + buf b_addrb_9 (addrb_int[9], ADDRB[9]); + buf b_dib_0 (dib_int[0], DIB[0]); + buf b_dib_1 (dib_int[1], DIB[1]); + buf b_dib_2 (dib_int[2], DIB[2]); + buf b_dib_3 (dib_int[3], DIB[3]); + buf b_dib_4 (dib_int[4], DIB[4]); + buf b_dib_5 (dib_int[5], DIB[5]); + buf b_dib_6 (dib_int[6], DIB[6]); + buf b_dib_7 (dib_int[7], DIB[7]); + buf b_dib_8 (dib_int[8], DIB[8]); + buf b_dib_9 (dib_int[9], DIB[9]); + buf b_dib_10 (dib_int[10], DIB[10]); + buf b_dib_11 (dib_int[11], DIB[11]); + buf b_dib_12 (dib_int[12], DIB[12]); + buf b_dib_13 (dib_int[13], DIB[13]); + buf b_dib_14 (dib_int[14], DIB[14]); + buf b_dib_15 (dib_int[15], DIB[15]); + buf b_dipb_0 (dipb_int[0], DIPB[0]); + buf b_dipb_1 (dipb_int[1], DIPB[1]); + buf b_enb (enb_int, ENB); + buf b_clkb (clkb_int, CLKB); + buf b_ssrb (ssrb_int, SSRB); + buf b_web (web_int, WEB); + + initial begin + for (count = 0; count < 256; count = count + 1) begin + mem[count] <= INIT_00[count]; + mem[256 * 1 + count] <= INIT_01[count]; + mem[256 * 2 + count] <= INIT_02[count]; + mem[256 * 3 + count] <= INIT_03[count]; + mem[256 * 4 + count] <= INIT_04[count]; + mem[256 * 5 + count] <= INIT_05[count]; + mem[256 * 6 + count] <= INIT_06[count]; + mem[256 * 7 + count] <= INIT_07[count]; + mem[256 * 8 + count] <= INIT_08[count]; + mem[256 * 9 + count] <= INIT_09[count]; + mem[256 * 10 + count] <= INIT_0A[count]; + mem[256 * 11 + count] <= INIT_0B[count]; + mem[256 * 12 + count] <= INIT_0C[count]; + mem[256 * 13 + count] <= INIT_0D[count]; + mem[256 * 14 + count] <= INIT_0E[count]; + mem[256 * 15 + count] <= INIT_0F[count]; + mem[256 * 16 + count] <= INIT_10[count]; + mem[256 * 17 + count] <= INIT_11[count]; + mem[256 * 18 + count] <= INIT_12[count]; + mem[256 * 19 + count] <= INIT_13[count]; + mem[256 * 20 + count] <= INIT_14[count]; + mem[256 * 21 + count] <= INIT_15[count]; + mem[256 * 22 + count] <= INIT_16[count]; + mem[256 * 23 + count] <= INIT_17[count]; + mem[256 * 24 + count] <= INIT_18[count]; + mem[256 * 25 + count] <= INIT_19[count]; + mem[256 * 26 + count] <= INIT_1A[count]; + mem[256 * 27 + count] <= INIT_1B[count]; + mem[256 * 28 + count] <= INIT_1C[count]; + mem[256 * 29 + count] <= INIT_1D[count]; + mem[256 * 30 + count] <= INIT_1E[count]; + mem[256 * 31 + count] <= INIT_1F[count]; + mem[256 * 32 + count] <= INIT_20[count]; + mem[256 * 33 + count] <= INIT_21[count]; + mem[256 * 34 + count] <= INIT_22[count]; + mem[256 * 35 + count] <= INIT_23[count]; + mem[256 * 36 + count] <= INIT_24[count]; + mem[256 * 37 + count] <= INIT_25[count]; + mem[256 * 38 + count] <= INIT_26[count]; + mem[256 * 39 + count] <= INIT_27[count]; + mem[256 * 40 + count] <= INIT_28[count]; + mem[256 * 41 + count] <= INIT_29[count]; + mem[256 * 42 + count] <= INIT_2A[count]; + mem[256 * 43 + count] <= INIT_2B[count]; + mem[256 * 44 + count] <= INIT_2C[count]; + mem[256 * 45 + count] <= INIT_2D[count]; + mem[256 * 46 + count] <= INIT_2E[count]; + mem[256 * 47 + count] <= INIT_2F[count]; + mem[256 * 48 + count] <= INIT_30[count]; + mem[256 * 49 + count] <= INIT_31[count]; + mem[256 * 50 + count] <= INIT_32[count]; + mem[256 * 51 + count] <= INIT_33[count]; + mem[256 * 52 + count] <= INIT_34[count]; + mem[256 * 53 + count] <= INIT_35[count]; + mem[256 * 54 + count] <= INIT_36[count]; + mem[256 * 55 + count] <= INIT_37[count]; + mem[256 * 56 + count] <= INIT_38[count]; + mem[256 * 57 + count] <= INIT_39[count]; + mem[256 * 58 + count] <= INIT_3A[count]; + mem[256 * 59 + count] <= INIT_3B[count]; + mem[256 * 60 + count] <= INIT_3C[count]; + mem[256 * 61 + count] <= INIT_3D[count]; + mem[256 * 62 + count] <= INIT_3E[count]; + mem[256 * 63 + count] <= INIT_3F[count]; + mem[256 * 64 + count] <= INITP_00[count]; + mem[256 * 65 + count] <= INITP_01[count]; + mem[256 * 66 + count] <= INITP_02[count]; + mem[256 * 67 + count] <= INITP_03[count]; + mem[256 * 68 + count] <= INITP_04[count]; + mem[256 * 69 + count] <= INITP_05[count]; + mem[256 * 70 + count] <= INITP_06[count]; + mem[256 * 71 + count] <= INITP_07[count]; + end + address_collision <= 0; + address_collision_a_b <= 0; + address_collision_b_a <= 0; + change_clka <= 0; + change_clkb <= 0; + data_collision <= 0; + data_collision_a_b <= 0; + data_collision_b_a <= 0; + memory_collision <= 0; + memory_collision_a_b <= 0; + memory_collision_b_a <= 0; + setup_all_a_b <= 0; + setup_all_b_a <= 0; + setup_zero <= 0; + setup_rf_a_b <= 0; + setup_rf_b_a <= 0; + end + + assign data_addra_int = addra_int * 2; + assign data_addra_reg = addra_reg * 2; + assign data_addrb_int = addrb_int * 16; + assign data_addrb_reg = addrb_reg * 16; + assign parity_addrb_int = 16384 + addrb_int * 2; + assign parity_addrb_reg = 16384 + addrb_reg * 2; + + + initial begin + + display_flag = 1; + + case (SIM_COLLISION_CHECK) + + "NONE" : begin + assign setup_all_a_b = 1'b0; + assign setup_all_b_a = 1'b0; + assign setup_zero = 1'b0; + assign setup_rf_a_b = 1'b0; + assign setup_rf_b_a = 1'b0; + assign display_flag = 0; + end + "WARNING_ONLY" : begin + assign data_collision = 2'b00; + assign data_collision_a_b = 2'b00; + assign data_collision_b_a = 2'b00; + assign memory_collision = 1'b0; + assign memory_collision_a_b = 1'b0; + assign memory_collision_b_a = 1'b0; + end + "GENERATE_X_ONLY" : begin + assign display_flag = 0; + end + "ALL" : ; + default : begin + $display("Attribute Syntax Error : The Attribute SIM_COLLISION_CHECK on RAMB16_S2_S18 instance %m is set to %s. Legal values for this attribute are ALL, NONE, WARNING_ONLY or GENERATE_X_ONLY.", SIM_COLLISION_CHECK); + $finish; + end + + endcase // case(SIM_COLLISION_CHECK) + + end // initial begin + + + always @(posedge clka_int) begin + time_clka = $time; + #0 time_clkb_clka = time_clka - time_clkb; + change_clka = ~change_clka; + end + + always @(posedge clkb_int) begin + time_clkb = $time; + #0 time_clka_clkb = time_clkb - time_clka; + change_clkb = ~change_clkb; + end + + always @(change_clkb) begin + if ((0 < time_clka_clkb) && (time_clka_clkb < SETUP_ALL)) + setup_all_a_b = 1; + if ((0 < time_clka_clkb) && (time_clka_clkb < SETUP_READ_FIRST)) + setup_rf_a_b = 1; + end + + always @(change_clka) begin + if ((0 < time_clkb_clka) && (time_clkb_clka < SETUP_ALL)) + setup_all_b_a = 1; + if ((0 < time_clkb_clka) && (time_clkb_clka < SETUP_READ_FIRST)) + setup_rf_b_a = 1; + end + + always @(change_clkb or change_clka) begin + if ((time_clkb_clka == 0) && (time_clka_clkb == 0)) + setup_zero = 1; + end + + always @(posedge setup_zero) begin + if ((ena_int == 1) && (wea_int == 1) && + (enb_int == 1) && (web_int == 1) && + (data_addra_int[14:4] == data_addrb_int[14:4])) + memory_collision <= 1; + end + + always @(posedge setup_all_a_b or posedge setup_rf_a_b) begin + if ((ena_reg == 1) && (wea_reg == 1) && + (enb_int == 1) && (web_int == 1) && + (data_addra_reg[14:4] == data_addrb_int[14:4])) + memory_collision_a_b <= 1; + end + + always @(posedge setup_all_b_a or posedge setup_rf_b_a) begin + if ((ena_int == 1) && (wea_int == 1) && + (enb_reg == 1) && (web_reg == 1) && + (data_addra_int[14:4] == data_addrb_reg[14:4])) + memory_collision_b_a <= 1; + end + + always @(posedge setup_all_a_b) begin + if (data_addra_reg[14:4] == data_addrb_int[14:4]) begin + if ((ena_reg == 1) && (enb_int == 1)) begin + case ({wr_mode_a, wr_mode_b, wea_reg, web_int}) + 6'b000011 : begin data_collision_a_b <= 2'b11; display_wa_wb; end + 6'b000111 : begin data_collision_a_b <= 2'b11; display_wa_wb; end + 6'b001011 : begin data_collision_a_b <= 2'b10; display_wa_wb; end +// 6'b010011 : begin data_collision_a_b <= 2'b00; display_wa_wb; end +// 6'b010111 : begin data_collision_a_b <= 2'b00; display_wa_wb; end +// 6'b011011 : begin data_collision_a_b <= 2'b00; display_wa_wb; end + 6'b100011 : begin data_collision_a_b <= 2'b01; display_wa_wb; end + 6'b100111 : begin data_collision_a_b <= 2'b01; display_wa_wb; end + 6'b101011 : begin display_wa_wb; end + 6'b000001 : begin data_collision_a_b <= 2'b10; display_ra_wb; end +// 6'b000101 : begin data_collision_a_b <= 2'b00; display_ra_wb; end + 6'b001001 : begin data_collision_a_b <= 2'b10; display_ra_wb; end + 6'b010001 : begin data_collision_a_b <= 2'b10; display_ra_wb; end +// 6'b010101 : begin data_collision_a_b <= 2'b00; display_ra_wb; end + 6'b011001 : begin data_collision_a_b <= 2'b10; display_ra_wb; end + 6'b100001 : begin data_collision_a_b <= 2'b10; display_ra_wb; end +// 6'b100101 : begin data_collision_a_b <= 2'b00; display_ra_wb; end + 6'b101001 : begin data_collision_a_b <= 2'b10; display_ra_wb; end + 6'b000010 : begin data_collision_a_b <= 2'b01; display_wa_rb; end + 6'b000110 : begin data_collision_a_b <= 2'b01; display_wa_rb; end + 6'b001010 : begin data_collision_a_b <= 2'b01; display_wa_rb; end +// 6'b010010 : begin data_collision_a_b <= 2'b00; display_wa_rb; end +// 6'b010110 : begin data_collision_a_b <= 2'b00; display_wa_rb; end +// 6'b011010 : begin data_collision_a_b <= 2'b00; display_wa_rb; end + 6'b100010 : begin data_collision_a_b <= 2'b01; display_wa_rb; end + 6'b100110 : begin data_collision_a_b <= 2'b01; display_wa_rb; end + 6'b101010 : begin data_collision_a_b <= 2'b01; display_wa_rb; end + endcase + end + end + setup_all_a_b <= 0; + end + + + always @(posedge setup_all_b_a) begin + if (data_addra_int[14:4] == data_addrb_reg[14:4]) begin + if ((ena_int == 1) && (enb_reg == 1)) begin + case ({wr_mode_a, wr_mode_b, wea_int, web_reg}) + 6'b000011 : begin data_collision_b_a <= 2'b11; display_wa_wb; end +// 6'b000111 : begin data_collision_b_a <= 2'b00; display_wa_wb; end + 6'b001011 : begin data_collision_b_a <= 2'b10; display_wa_wb; end + 6'b010011 : begin data_collision_b_a <= 2'b11; display_wa_wb; end +// 6'b010111 : begin data_collision_b_a <= 2'b00; display_wa_wb; end + 6'b011011 : begin data_collision_b_a <= 2'b10; display_wa_wb; end + 6'b100011 : begin data_collision_b_a <= 2'b01; display_wa_wb; end + 6'b100111 : begin data_collision_b_a <= 2'b01; display_wa_wb; end + 6'b101011 : begin display_wa_wb; end + 6'b000001 : begin data_collision_b_a <= 2'b10; display_ra_wb; end + 6'b000101 : begin data_collision_b_a <= 2'b10; display_ra_wb; end + 6'b001001 : begin data_collision_b_a <= 2'b10; display_ra_wb; end + 6'b010001 : begin data_collision_b_a <= 2'b10; display_ra_wb; end + 6'b010101 : begin data_collision_b_a <= 2'b10; display_ra_wb; end + 6'b011001 : begin data_collision_b_a <= 2'b10; display_ra_wb; end + 6'b100001 : begin data_collision_b_a <= 2'b10; display_ra_wb; end + 6'b100101 : begin data_collision_b_a <= 2'b10; display_ra_wb; end + 6'b101001 : begin data_collision_b_a <= 2'b10; display_ra_wb; end + 6'b000010 : begin data_collision_b_a <= 2'b01; display_wa_rb; end + 6'b000110 : begin data_collision_b_a <= 2'b01; display_wa_rb; end + 6'b001010 : begin data_collision_b_a <= 2'b01; display_wa_rb; end +// 6'b010010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end +// 6'b010110 : begin data_collision_b_a <= 2'b00; display_wa_rb; end +// 6'b011010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end + 6'b100010 : begin data_collision_b_a <= 2'b01; display_wa_rb; end + 6'b100110 : begin data_collision_b_a <= 2'b01; display_wa_rb; end + 6'b101010 : begin data_collision_b_a <= 2'b01; display_wa_rb; end + endcase + end + end + setup_all_b_a <= 0; + end + + + always @(posedge setup_zero) begin + if (data_addra_int[14:4] == data_addrb_int[14:4]) begin + if ((ena_int == 1) && (enb_int == 1)) begin + case ({wr_mode_a, wr_mode_b, wea_int, web_int}) + 6'b000011 : begin data_collision <= 2'b11; display_wa_wb; end + 6'b000111 : begin data_collision <= 2'b11; display_wa_wb; end + 6'b001011 : begin data_collision <= 2'b10; display_wa_wb; end + 6'b010011 : begin data_collision <= 2'b11; display_wa_wb; end + 6'b010111 : begin data_collision <= 2'b11; display_wa_wb; end + 6'b011011 : begin data_collision <= 2'b10; display_wa_wb; end + 6'b100011 : begin data_collision <= 2'b01; display_wa_wb; end + 6'b100111 : begin data_collision <= 2'b01; display_wa_wb; end + 6'b101011 : begin display_wa_wb; end + 6'b000001 : begin data_collision <= 2'b10; display_ra_wb; end +// 6'b000101 : begin data_collision <= 2'b00; display_ra_wb; end + 6'b001001 : begin data_collision <= 2'b10; display_ra_wb; end + 6'b010001 : begin data_collision <= 2'b10; display_ra_wb; end +// 6'b010101 : begin data_collision <= 2'b00; display_ra_wb; end + 6'b011001 : begin data_collision <= 2'b10; display_ra_wb; end + 6'b100001 : begin data_collision <= 2'b10; display_ra_wb; end +// 6'b100101 : begin data_collision <= 2'b00; display_ra_wb; end + 6'b101001 : begin data_collision <= 2'b10; display_ra_wb; end + 6'b000010 : begin data_collision <= 2'b01; display_wa_rb; end + 6'b000110 : begin data_collision <= 2'b01; display_wa_rb; end + 6'b001010 : begin data_collision <= 2'b01; display_wa_rb; end +// 6'b010010 : begin data_collision <= 2'b00; display_wa_rb; end +// 6'b010110 : begin data_collision <= 2'b00; display_wa_rb; end +// 6'b011010 : begin data_collision <= 2'b00; display_wa_rb; end + 6'b100010 : begin data_collision <= 2'b01; display_wa_rb; end + 6'b100110 : begin data_collision <= 2'b01; display_wa_rb; end + 6'b101010 : begin data_collision <= 2'b01; display_wa_rb; end + endcase + end + end + setup_zero <= 0; + end + + task display_ra_wb; + begin + if (display_flag) + $display("Memory Collision Error on RAMB16_S2_S18:%m at simulation time %.3f ns\nA read was performed on address %h (hex) of Port A while a write was requested to the same address on Port B. The write will be successful however the read value on Port A is unknown until the next CLKA cycle.", $time/1000.0, addra_int); + end + endtask + + task display_wa_rb; + begin + if (display_flag) + $display("Memory Collision Error on RAMB16_S2_S18:%m at simulation time %.3f ns\nA read was performed on address %h (hex) of Port B while a write was requested to the same address on Port A. The write will be successful however the read value on Port B is unknown until the next CLKB cycle.", $time/1000.0, addrb_int); + end + endtask + + task display_wa_wb; + begin + if (display_flag) + $display("Memory Collision Error on RAMB16_S2_S18:%m at simulation time %.3f ns\nA write was requested to the same address simultaneously at both Port A and Port B of the RAM. The contents written to the RAM at address location %h (hex) of Port A and address location %h (hex) of Port B are unknown.", $time/1000.0, addra_int, addrb_int); + end + endtask + + + always @(posedge setup_rf_a_b) begin + if (data_addra_reg[14:4] == data_addrb_int[14:4]) begin + if ((ena_reg == 1) && (enb_int == 1)) begin + case ({wr_mode_a, wr_mode_b, wea_reg, web_int}) +// 6'b000011 : begin data_collision_a_b <= 2'b00; display_wa_wb; end +// 6'b000111 : begin data_collision_a_b <= 2'b00; display_wa_wb; end +// 6'b001011 : begin data_collision_a_b <= 2'b00; display_wa_wb; end + 6'b010011 : begin data_collision_a_b <= 2'b11; display_wa_wb; end + 6'b010111 : begin data_collision_a_b <= 2'b11; display_wa_wb; end + 6'b011011 : begin data_collision_a_b <= 2'b10; display_wa_wb; end +// 6'b100011 : begin data_collision_a_b <= 2'b00; display_wa_wb; end +// 6'b100111 : begin data_collision_a_b <= 2'b00; display_wa_wb; end +// 6'b101011 : begin data_collision_a_b <= 2'b00; display_wa_wb; end +// 6'b000001 : begin data_collision_a_b <= 2'b00; display_ra_wb; end +// 6'b000101 : begin data_collision_a_b <= 2'b00; display_ra_wb; end +// 6'b001001 : begin data_collision_a_b <= 2'b00; display_ra_wb; end +// 6'b010001 : begin data_collision_a_b <= 2'b00; display_ra_wb; end +// 6'b010101 : begin data_collision_a_b <= 2'b00; display_ra_wb; end +// 6'b011001 : begin data_collision_a_b <= 2'b00; display_ra_wb; end +// 6'b100001 : begin data_collision_a_b <= 2'b00; display_ra_wb; end +// 6'b100101 : begin data_collision_a_b <= 2'b00; display_ra_wb; end +// 6'b101001 : begin data_collision_a_b <= 2'b00; display_ra_wb; end +// 6'b000010 : begin data_collision_a_b <= 2'b00; display_wa_rb; end +// 6'b000110 : begin data_collision_a_b <= 2'b00; display_wa_rb; end +// 6'b001010 : begin data_collision_a_b <= 2'b00; display_wa_rb; end + 6'b010010 : begin data_collision_a_b <= 2'b01; display_wa_rb; end + 6'b010110 : begin data_collision_a_b <= 2'b01; display_wa_rb; end + 6'b011010 : begin data_collision_a_b <= 2'b01; display_wa_rb; end +// 6'b100010 : begin data_collision_a_b <= 2'b00; display_wa_rb; end +// 6'b100110 : begin data_collision_a_b <= 2'b00; display_wa_rb; end +// 6'b101010 : begin data_collision_a_b <= 2'b00; display_wa_rb; end + endcase + end + end + setup_rf_a_b <= 0; + end + + + always @(posedge setup_rf_b_a) begin + if (data_addra_int[14:4] == data_addrb_reg[14:4]) begin + if ((ena_int == 1) && (enb_reg == 1)) begin + case ({wr_mode_a, wr_mode_b, wea_int, web_reg}) +// 6'b000011 : begin data_collision_b_a <= 2'b00; display_wa_wb; end + 6'b000111 : begin data_collision_b_a <= 2'b11; display_wa_wb; end +// 6'b001011 : begin data_collision_b_a <= 2'b00; display_wa_wb; end +// 6'b010011 : begin data_collision_b_a <= 2'b00; display_wa_wb; end + 6'b010111 : begin data_collision_b_a <= 2'b11; display_wa_wb; end +// 6'b011011 : begin data_collision_b_a <= 2'b00; display_wa_wb; end +// 6'b100011 : begin data_collision_b_a <= 2'b00; display_wa_wb; end + 6'b100111 : begin data_collision_b_a <= 2'b01; display_wa_wb; end +// 6'b101011 : begin data_collision_b_a <= 2'b00; display_wa_wb; end +// 6'b000001 : begin data_collision_b_a <= 2'b00; display_ra_wb; end + 6'b000101 : begin data_collision_b_a <= 2'b10; display_ra_wb; end +// 6'b001001 : begin data_collision_b_a <= 2'b00; display_ra_wb; end +// 6'b010001 : begin data_collision_b_a <= 2'b00; display_ra_wb; end + 6'b010101 : begin data_collision_b_a <= 2'b10; display_ra_wb; end +// 6'b011001 : begin data_collision_b_a <= 2'b00; display_ra_wb; end +// 6'b100001 : begin data_collision_b_a <= 2'b00; display_ra_wb; end + 6'b100101 : begin data_collision_b_a <= 2'b10; display_ra_wb; end +// 6'b101001 : begin data_collision_b_a <= 2'b00; display_ra_wb; end +// 6'b000010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end +// 6'b000110 : begin data_collision_b_a <= 2'b00; display_wa_rb; end +// 6'b001010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end +// 6'b010010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end +// 6'b010110 : begin data_collision_b_a <= 2'b00; display_wa_rb; end +// 6'b011010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end +// 6'b100010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end +// 6'b100110 : begin data_collision_b_a <= 2'b00; display_wa_rb; end +// 6'b101010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end + endcase + end + end + setup_rf_b_a <= 0; + end + + + always @(posedge clka_int) begin + addra_reg <= addra_int; + ena_reg <= ena_int; + ssra_reg <= ssra_int; + wea_reg <= wea_int; + end + + always @(posedge clkb_int) begin + addrb_reg <= addrb_int; + enb_reg <= enb_int; + ssrb_reg <= ssrb_int; + web_reg <= web_int; + end + + // Data + always @(posedge memory_collision) begin + for (dmi = 0; dmi < 2; dmi = dmi + 1) begin + mem[data_addra_int + dmi] <= 1'bX; + end + memory_collision <= 0; + end + + always @(posedge memory_collision_a_b) begin + for (dmi = 0; dmi < 2; dmi = dmi + 1) begin + mem[data_addra_reg + dmi] <= 1'bX; + end + memory_collision_a_b <= 0; + end + + always @(posedge memory_collision_b_a) begin + for (dmi = 0; dmi < 2; dmi = dmi + 1) begin + mem[data_addra_int + dmi] <= 1'bX; + end + memory_collision_b_a <= 0; + end + + always @(posedge data_collision[1]) begin + if (ssra_int == 0) begin + doa_out <= 2'bX; + end + data_collision[1] <= 0; + end + + always @(posedge data_collision[0]) begin + if (ssrb_int == 0) begin + for (dbi = 0; dbi < 2; dbi = dbi + 1) begin + dob_out[data_addra_int[3 : 0] + dbi] <= 1'bX; + end + end + data_collision[0] <= 0; + end + + always @(posedge data_collision_a_b[1]) begin + if (ssra_reg == 0) begin + doa_out <= 2'bX; + end + data_collision_a_b[1] <= 0; + end + + always @(posedge data_collision_a_b[0]) begin + if (ssrb_int == 0) begin + for (dbi = 0; dbi < 2; dbi = dbi + 1) begin + dob_out[data_addra_reg[3 : 0] + dbi] <= 1'bX; + end + end + data_collision_a_b[0] <= 0; + end + + always @(posedge data_collision_b_a[1]) begin + if (ssra_int == 0) begin + doa_out <= 2'bX; + end + data_collision_b_a[1] <= 0; + end + + always @(posedge data_collision_b_a[0]) begin + if (ssrb_reg == 0) begin + for (dbi = 0; dbi < 2; dbi = dbi + 1) begin + dob_out[data_addra_int[3 : 0] + dbi] <= 1'bX; + end + end + data_collision_b_a[0] <= 0; + end + + + initial begin + case (WRITE_MODE_A) + "WRITE_FIRST" : wr_mode_a <= 2'b00; + "READ_FIRST" : wr_mode_a <= 2'b01; + "NO_CHANGE" : wr_mode_a <= 2'b10; + default : begin + $display("Attribute Syntax Error : The Attribute WRITE_MODE_A on RAMB16_S2_S18 instance %m is set to %s. Legal values for this attribute are WRITE_FIRST, READ_FIRST or NO_CHANGE.", WRITE_MODE_A); + $finish; + end + endcase + end + + initial begin + case (WRITE_MODE_B) + "WRITE_FIRST" : wr_mode_b <= 2'b00; + "READ_FIRST" : wr_mode_b <= 2'b01; + "NO_CHANGE" : wr_mode_b <= 2'b10; + default : begin + $display("Attribute Syntax Error : The Attribute WRITE_MODE_B on RAMB16_S2_S18 instance %m is set to %s. Legal values for this attribute are WRITE_FIRST, READ_FIRST or NO_CHANGE.", WRITE_MODE_B); + $finish; + end + endcase + end + + // Port A + always @(posedge clka_int) begin + if (ena_int == 1'b1) begin + if (ssra_int == 1'b1) begin + doa_out[0] <= SRVAL_A[0]; + doa_out[1] <= SRVAL_A[1]; + end + else begin + if (wea_int == 1'b1) begin + if (wr_mode_a == 2'b00) begin + doa_out <= dia_int; + end + else if (wr_mode_a == 2'b01) begin + doa_out[0] <= mem[data_addra_int + 0]; + doa_out[1] <= mem[data_addra_int + 1]; + end + end + else begin + doa_out[0] <= mem[data_addra_int + 0]; + doa_out[1] <= mem[data_addra_int + 1]; + end + end + end + end + + always @(posedge clka_int) begin + if (ena_int == 1'b1 && wea_int == 1'b1) begin + mem[data_addra_int + 0] <= dia_int[0]; + mem[data_addra_int + 1] <= dia_int[1]; + end + end + + // Port B + always @(posedge clkb_int) begin + if (enb_int == 1'b1) begin + if (ssrb_int == 1'b1) begin + dob_out[0] <= SRVAL_B[0]; + dob_out[1] <= SRVAL_B[1]; + dob_out[2] <= SRVAL_B[2]; + dob_out[3] <= SRVAL_B[3]; + dob_out[4] <= SRVAL_B[4]; + dob_out[5] <= SRVAL_B[5]; + dob_out[6] <= SRVAL_B[6]; + dob_out[7] <= SRVAL_B[7]; + dob_out[8] <= SRVAL_B[8]; + dob_out[9] <= SRVAL_B[9]; + dob_out[10] <= SRVAL_B[10]; + dob_out[11] <= SRVAL_B[11]; + dob_out[12] <= SRVAL_B[12]; + dob_out[13] <= SRVAL_B[13]; + dob_out[14] <= SRVAL_B[14]; + dob_out[15] <= SRVAL_B[15]; + dopb_out[0] <= SRVAL_B[16]; + dopb_out[1] <= SRVAL_B[17]; + end + else begin + if (web_int == 1'b1) begin + if (wr_mode_b == 2'b00) begin + dob_out <= dib_int; + dopb_out <= dipb_int; + end + else if (wr_mode_b == 2'b01) begin + dob_out[0] <= mem[data_addrb_int + 0]; + dob_out[1] <= mem[data_addrb_int + 1]; + dob_out[2] <= mem[data_addrb_int + 2]; + dob_out[3] <= mem[data_addrb_int + 3]; + dob_out[4] <= mem[data_addrb_int + 4]; + dob_out[5] <= mem[data_addrb_int + 5]; + dob_out[6] <= mem[data_addrb_int + 6]; + dob_out[7] <= mem[data_addrb_int + 7]; + dob_out[8] <= mem[data_addrb_int + 8]; + dob_out[9] <= mem[data_addrb_int + 9]; + dob_out[10] <= mem[data_addrb_int + 10]; + dob_out[11] <= mem[data_addrb_int + 11]; + dob_out[12] <= mem[data_addrb_int + 12]; + dob_out[13] <= mem[data_addrb_int + 13]; + dob_out[14] <= mem[data_addrb_int + 14]; + dob_out[15] <= mem[data_addrb_int + 15]; + dopb_out[0] <= mem[parity_addrb_int + 0]; + dopb_out[1] <= mem[parity_addrb_int + 1]; + end + end + else begin + dob_out[0] <= mem[data_addrb_int + 0]; + dob_out[1] <= mem[data_addrb_int + 1]; + dob_out[2] <= mem[data_addrb_int + 2]; + dob_out[3] <= mem[data_addrb_int + 3]; + dob_out[4] <= mem[data_addrb_int + 4]; + dob_out[5] <= mem[data_addrb_int + 5]; + dob_out[6] <= mem[data_addrb_int + 6]; + dob_out[7] <= mem[data_addrb_int + 7]; + dob_out[8] <= mem[data_addrb_int + 8]; + dob_out[9] <= mem[data_addrb_int + 9]; + dob_out[10] <= mem[data_addrb_int + 10]; + dob_out[11] <= mem[data_addrb_int + 11]; + dob_out[12] <= mem[data_addrb_int + 12]; + dob_out[13] <= mem[data_addrb_int + 13]; + dob_out[14] <= mem[data_addrb_int + 14]; + dob_out[15] <= mem[data_addrb_int + 15]; + dopb_out[0] <= mem[parity_addrb_int + 0]; + dopb_out[1] <= mem[parity_addrb_int + 1]; + end + end + end + end + + always @(posedge clkb_int) begin + if (enb_int == 1'b1 && web_int == 1'b1) begin + mem[data_addrb_int + 0] <= dib_int[0]; + mem[data_addrb_int + 1] <= dib_int[1]; + mem[data_addrb_int + 2] <= dib_int[2]; + mem[data_addrb_int + 3] <= dib_int[3]; + mem[data_addrb_int + 4] <= dib_int[4]; + mem[data_addrb_int + 5] <= dib_int[5]; + mem[data_addrb_int + 6] <= dib_int[6]; + mem[data_addrb_int + 7] <= dib_int[7]; + mem[data_addrb_int + 8] <= dib_int[8]; + mem[data_addrb_int + 9] <= dib_int[9]; + mem[data_addrb_int + 10] <= dib_int[10]; + mem[data_addrb_int + 11] <= dib_int[11]; + mem[data_addrb_int + 12] <= dib_int[12]; + mem[data_addrb_int + 13] <= dib_int[13]; + mem[data_addrb_int + 14] <= dib_int[14]; + mem[data_addrb_int + 15] <= dib_int[15]; + mem[parity_addrb_int + 0] <= dipb_int[0]; + mem[parity_addrb_int + 1] <= dipb_int[1]; + end + end + + specify + (CLKA *> DOA) = (100, 100); + (CLKB *> DOB) = (100, 100); + (CLKB *> DOPB) = (100, 100); + endspecify + +endmodule + +`else + +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/RAMB16_S2_S18.v,v 1.10 2007/02/22 01:58:05 wloo Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2005 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Timing Simulation Library Component +// / / 16K-Bit Data and 2K-Bit Parity Dual Port Block RAM +// /___/ /\ Filename : RAMB16_S2_S18.v +// \ \ / \ Timestamp : Thu Mar 10 16:44:01 PST 2005 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 03/10/05 - Initialized outputs. +// 02/21/07 - Fixed parameter SIM_COLLISION_CHECK (CR 433281). +// End Revision + +`timescale 1 ps/1 ps + +module RAMB16_S2_S18 (DOA, DOB, DOPB, ADDRA, ADDRB, CLKA, CLKB, DIA, DIB, DIPB, ENA, ENB, SSRA, SSRB, WEA, WEB); + + parameter INIT_A = 2'h0; + parameter INIT_B = 18'h0; + parameter SRVAL_A = 2'h0; + parameter SRVAL_B = 18'h0; + parameter WRITE_MODE_A = "WRITE_FIRST"; + parameter WRITE_MODE_B = "WRITE_FIRST"; + parameter SIM_COLLISION_CHECK = "ALL"; + localparam SETUP_ALL = 1000; + localparam SETUP_READ_FIRST = 3000; + + parameter INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + + output [1:0] DOA; + output [15:0] DOB; + output [1:0] DOPB; + + input [12:0] ADDRA; + input [1:0] DIA; + input ENA, CLKA, WEA, SSRA; + input [9:0] ADDRB; + input [15:0] DIB; + input [1:0] DIPB; + input ENB, CLKB, WEB, SSRB; + + reg [1:0] doa_out = INIT_A[1:0]; + reg [15:0] dob_out = INIT_B[15:0]; + reg [1:0] dopb_out = INIT_B[17:16]; + + reg [15:0] mem [1023:0]; + reg [1:0] memp [1023:0]; + + reg [8:0] count, countp; + reg [1:0] wr_mode_a, wr_mode_b; + + reg [5:0] dmi, dbi; + reg [5:0] pmi, pbi; + + wire [12:0] addra_int; + reg [12:0] addra_reg; + wire [1:0] dia_int; + wire ena_int, clka_int, wea_int, ssra_int; + reg ena_reg, wea_reg, ssra_reg; + wire [9:0] addrb_int; + reg [9:0] addrb_reg; + wire [15:0] dib_int; + wire [1:0] dipb_int; + wire enb_int, clkb_int, web_int, ssrb_int; + reg display_flag, output_flag; + reg enb_reg, web_reg, ssrb_reg; + + time time_clka, time_clkb; + time time_clka_clkb; + time time_clkb_clka; + + reg setup_all_a_b; + reg setup_all_b_a; + reg setup_zero; + reg setup_rf_a_b; + reg setup_rf_b_a; + reg [1:0] data_collision, data_collision_a_b, data_collision_b_a; + reg memory_collision, memory_collision_a_b, memory_collision_b_a; + reg change_clka; + reg change_clkb; + + wire [14:0] data_addra_int; + wire [14:0] data_addra_reg; + wire [14:0] data_addrb_int; + wire [14:0] data_addrb_reg; + + wire dia_enable = ena_int && wea_int; + wire dib_enable = enb_int && web_int; + + tri0 GSR = glbl.GSR; + wire gsr_int; + + buf b_gsr (gsr_int, GSR); + + buf b_doa [1:0] (DOA, doa_out); + buf b_addra [12:0] (addra_int, ADDRA); + buf b_dia [1:0] (dia_int, DIA); + buf b_ena (ena_int, ENA); + buf b_clka (clka_int, CLKA); + buf b_ssra (ssra_int, SSRA); + buf b_wea (wea_int, WEA); + + buf b_dob [15:0] (DOB, dob_out); + buf b_dopb [1:0] (DOPB, dopb_out); + buf b_addrb [9:0] (addrb_int, ADDRB); + buf b_dib [15:0] (dib_int, DIB); + buf b_dipb [1:0] (dipb_int, DIPB); + buf b_enb (enb_int, ENB); + buf b_clkb (clkb_int, CLKB); + buf b_ssrb (ssrb_int, SSRB); + buf b_web (web_int, WEB); + + + always @(gsr_int) + if (gsr_int) begin + assign {doa_out} = INIT_A; + assign {dopb_out, dob_out} = INIT_B; + end + else begin + deassign doa_out; + deassign dob_out; + deassign dopb_out; + end + + + initial begin + + for (count = 0; count < 16; count = count + 1) begin + mem[count] = INIT_00[(count * 16) +: 16]; + mem[16 * 1 + count] = INIT_01[(count * 16) +: 16]; + mem[16 * 2 + count] = INIT_02[(count * 16) +: 16]; + mem[16 * 3 + count] = INIT_03[(count * 16) +: 16]; + mem[16 * 4 + count] = INIT_04[(count * 16) +: 16]; + mem[16 * 5 + count] = INIT_05[(count * 16) +: 16]; + mem[16 * 6 + count] = INIT_06[(count * 16) +: 16]; + mem[16 * 7 + count] = INIT_07[(count * 16) +: 16]; + mem[16 * 8 + count] = INIT_08[(count * 16) +: 16]; + mem[16 * 9 + count] = INIT_09[(count * 16) +: 16]; + mem[16 * 10 + count] = INIT_0A[(count * 16) +: 16]; + mem[16 * 11 + count] = INIT_0B[(count * 16) +: 16]; + mem[16 * 12 + count] = INIT_0C[(count * 16) +: 16]; + mem[16 * 13 + count] = INIT_0D[(count * 16) +: 16]; + mem[16 * 14 + count] = INIT_0E[(count * 16) +: 16]; + mem[16 * 15 + count] = INIT_0F[(count * 16) +: 16]; + mem[16 * 16 + count] = INIT_10[(count * 16) +: 16]; + mem[16 * 17 + count] = INIT_11[(count * 16) +: 16]; + mem[16 * 18 + count] = INIT_12[(count * 16) +: 16]; + mem[16 * 19 + count] = INIT_13[(count * 16) +: 16]; + mem[16 * 20 + count] = INIT_14[(count * 16) +: 16]; + mem[16 * 21 + count] = INIT_15[(count * 16) +: 16]; + mem[16 * 22 + count] = INIT_16[(count * 16) +: 16]; + mem[16 * 23 + count] = INIT_17[(count * 16) +: 16]; + mem[16 * 24 + count] = INIT_18[(count * 16) +: 16]; + mem[16 * 25 + count] = INIT_19[(count * 16) +: 16]; + mem[16 * 26 + count] = INIT_1A[(count * 16) +: 16]; + mem[16 * 27 + count] = INIT_1B[(count * 16) +: 16]; + mem[16 * 28 + count] = INIT_1C[(count * 16) +: 16]; + mem[16 * 29 + count] = INIT_1D[(count * 16) +: 16]; + mem[16 * 30 + count] = INIT_1E[(count * 16) +: 16]; + mem[16 * 31 + count] = INIT_1F[(count * 16) +: 16]; + mem[16 * 32 + count] = INIT_20[(count * 16) +: 16]; + mem[16 * 33 + count] = INIT_21[(count * 16) +: 16]; + mem[16 * 34 + count] = INIT_22[(count * 16) +: 16]; + mem[16 * 35 + count] = INIT_23[(count * 16) +: 16]; + mem[16 * 36 + count] = INIT_24[(count * 16) +: 16]; + mem[16 * 37 + count] = INIT_25[(count * 16) +: 16]; + mem[16 * 38 + count] = INIT_26[(count * 16) +: 16]; + mem[16 * 39 + count] = INIT_27[(count * 16) +: 16]; + mem[16 * 40 + count] = INIT_28[(count * 16) +: 16]; + mem[16 * 41 + count] = INIT_29[(count * 16) +: 16]; + mem[16 * 42 + count] = INIT_2A[(count * 16) +: 16]; + mem[16 * 43 + count] = INIT_2B[(count * 16) +: 16]; + mem[16 * 44 + count] = INIT_2C[(count * 16) +: 16]; + mem[16 * 45 + count] = INIT_2D[(count * 16) +: 16]; + mem[16 * 46 + count] = INIT_2E[(count * 16) +: 16]; + mem[16 * 47 + count] = INIT_2F[(count * 16) +: 16]; + mem[16 * 48 + count] = INIT_30[(count * 16) +: 16]; + mem[16 * 49 + count] = INIT_31[(count * 16) +: 16]; + mem[16 * 50 + count] = INIT_32[(count * 16) +: 16]; + mem[16 * 51 + count] = INIT_33[(count * 16) +: 16]; + mem[16 * 52 + count] = INIT_34[(count * 16) +: 16]; + mem[16 * 53 + count] = INIT_35[(count * 16) +: 16]; + mem[16 * 54 + count] = INIT_36[(count * 16) +: 16]; + mem[16 * 55 + count] = INIT_37[(count * 16) +: 16]; + mem[16 * 56 + count] = INIT_38[(count * 16) +: 16]; + mem[16 * 57 + count] = INIT_39[(count * 16) +: 16]; + mem[16 * 58 + count] = INIT_3A[(count * 16) +: 16]; + mem[16 * 59 + count] = INIT_3B[(count * 16) +: 16]; + mem[16 * 60 + count] = INIT_3C[(count * 16) +: 16]; + mem[16 * 61 + count] = INIT_3D[(count * 16) +: 16]; + mem[16 * 62 + count] = INIT_3E[(count * 16) +: 16]; + mem[16 * 63 + count] = INIT_3F[(count * 16) +: 16]; + end + +// initiate parity start + for (countp = 0; countp < 128; countp = countp + 1) begin + memp[countp] = INITP_00[(countp * 2) +: 2]; + memp[128 * 1 + countp] = INITP_01[(countp * 2) +: 2]; + memp[128 * 2 + countp] = INITP_02[(countp * 2) +: 2]; + memp[128 * 3 + countp] = INITP_03[(countp * 2) +: 2]; + memp[128 * 4 + countp] = INITP_04[(countp * 2) +: 2]; + memp[128 * 5 + countp] = INITP_05[(countp * 2) +: 2]; + memp[128 * 6 + countp] = INITP_06[(countp * 2) +: 2]; + memp[128 * 7 + countp] = INITP_07[(countp * 2) +: 2]; + end +// initiate parity end + + change_clka <= 0; + change_clkb <= 0; + data_collision <= 0; + data_collision_a_b <= 0; + data_collision_b_a <= 0; + memory_collision <= 0; + memory_collision_a_b <= 0; + memory_collision_b_a <= 0; + setup_all_a_b <= 0; + setup_all_b_a <= 0; + setup_zero <= 0; + setup_rf_a_b <= 0; + setup_rf_b_a <= 0; + end + + assign data_addra_int = addra_int * 2; + assign data_addra_reg = addra_reg * 2; + assign data_addrb_int = addrb_int * 16; + assign data_addrb_reg = addrb_reg * 16; + + + initial begin + + display_flag = 1; + output_flag = 1; + + case (SIM_COLLISION_CHECK) + + "NONE" : begin + output_flag = 0; + display_flag = 0; + end + "WARNING_ONLY" : output_flag = 0; + "GENERATE_X_ONLY" : display_flag = 0; + "ALL" : ; + + default : begin + $display("Attribute Syntax Error : The Attribute SIM_COLLISION_CHECK on RAMB16_S2_S18 instance %m is set to %s. Legal values for this attribute are ALL, NONE, WARNING_ONLY or GENERATE_X_ONLY.", SIM_COLLISION_CHECK); + $finish; + end + + endcase // case(SIM_COLLISION_CHECK) + + end // initial begin + + + always @(posedge clka_int) begin + if ((output_flag || display_flag)) begin + time_clka = $time; + #0 time_clkb_clka = time_clka - time_clkb; + change_clka = ~change_clka; + end + end + + always @(posedge clkb_int) begin + if ((output_flag || display_flag)) begin + time_clkb = $time; + #0 time_clka_clkb = time_clkb - time_clka; + change_clkb = ~change_clkb; + end + end + + always @(change_clkb) begin + if ((0 < time_clka_clkb) && (time_clka_clkb < SETUP_ALL)) + setup_all_a_b = 1; + if ((0 < time_clka_clkb) && (time_clka_clkb < SETUP_READ_FIRST)) + setup_rf_a_b = 1; + end + + always @(change_clka) begin + if ((0 < time_clkb_clka) && (time_clkb_clka < SETUP_ALL)) + setup_all_b_a = 1; + if ((0 < time_clkb_clka) && (time_clkb_clka < SETUP_READ_FIRST)) + setup_rf_b_a = 1; + end + + always @(change_clkb or change_clka) begin + if ((time_clkb_clka == 0) && (time_clka_clkb == 0)) + setup_zero = 1; + end + + always @(posedge setup_zero) begin + if ((ena_int == 1) && (wea_int == 1) && + (enb_int == 1) && (web_int == 1) && + (data_addra_int[14:4] == data_addrb_int[14:4])) + memory_collision <= 1; + end + + always @(posedge setup_all_a_b or posedge setup_rf_a_b) begin + if ((ena_reg == 1) && (wea_reg == 1) && + (enb_int == 1) && (web_int == 1) && + (data_addra_reg[14:4] == data_addrb_int[14:4])) + memory_collision_a_b <= 1; + end + + always @(posedge setup_all_b_a or posedge setup_rf_b_a) begin + if ((ena_int == 1) && (wea_int == 1) && + (enb_reg == 1) && (web_reg == 1) && + (data_addra_int[14:4] == data_addrb_reg[14:4])) + memory_collision_b_a <= 1; + end + + always @(posedge setup_all_a_b) begin + if (data_addra_reg[14:4] == data_addrb_int[14:4]) begin + if ((ena_reg == 1) && (enb_int == 1)) begin + case ({wr_mode_a, wr_mode_b, wea_reg, web_int}) + 6'b000011 : begin data_collision_a_b <= 2'b11; display_wa_wb; end + 6'b000111 : begin data_collision_a_b <= 2'b11; display_wa_wb; end + 6'b001011 : begin data_collision_a_b <= 2'b10; display_wa_wb; end +// 6'b010011 : begin data_collision_a_b <= 2'b00; display_wa_wb; end +// 6'b010111 : begin data_collision_a_b <= 2'b00; display_wa_wb; end +// 6'b011011 : begin data_collision_a_b <= 2'b00; display_wa_wb; end + 6'b100011 : begin data_collision_a_b <= 2'b01; display_wa_wb; end + 6'b100111 : begin data_collision_a_b <= 2'b01; display_wa_wb; end + 6'b101011 : begin display_wa_wb; end + 6'b000001 : begin data_collision_a_b <= 2'b10; display_ra_wb; end +// 6'b000101 : begin data_collision_a_b <= 2'b00; display_ra_wb; end + 6'b001001 : begin data_collision_a_b <= 2'b10; display_ra_wb; end + 6'b010001 : begin data_collision_a_b <= 2'b10; display_ra_wb; end +// 6'b010101 : begin data_collision_a_b <= 2'b00; display_ra_wb; end + 6'b011001 : begin data_collision_a_b <= 2'b10; display_ra_wb; end + 6'b100001 : begin data_collision_a_b <= 2'b10; display_ra_wb; end +// 6'b100101 : begin data_collision_a_b <= 2'b00; display_ra_wb; end + 6'b101001 : begin data_collision_a_b <= 2'b10; display_ra_wb; end + 6'b000010 : begin data_collision_a_b <= 2'b01; display_wa_rb; end + 6'b000110 : begin data_collision_a_b <= 2'b01; display_wa_rb; end + 6'b001010 : begin data_collision_a_b <= 2'b01; display_wa_rb; end +// 6'b010010 : begin data_collision_a_b <= 2'b00; display_wa_rb; end +// 6'b010110 : begin data_collision_a_b <= 2'b00; display_wa_rb; end +// 6'b011010 : begin data_collision_a_b <= 2'b00; display_wa_rb; end + 6'b100010 : begin data_collision_a_b <= 2'b01; display_wa_rb; end + 6'b100110 : begin data_collision_a_b <= 2'b01; display_wa_rb; end + 6'b101010 : begin data_collision_a_b <= 2'b01; display_wa_rb; end + endcase + end + end + setup_all_a_b <= 0; + end + + + always @(posedge setup_all_b_a) begin + if (data_addra_int[14:4] == data_addrb_reg[14:4]) begin + if ((ena_int == 1) && (enb_reg == 1)) begin + case ({wr_mode_a, wr_mode_b, wea_int, web_reg}) + 6'b000011 : begin data_collision_b_a <= 2'b11; display_wa_wb; end +// 6'b000111 : begin data_collision_b_a <= 2'b00; display_wa_wb; end + 6'b001011 : begin data_collision_b_a <= 2'b10; display_wa_wb; end + 6'b010011 : begin data_collision_b_a <= 2'b11; display_wa_wb; end +// 6'b010111 : begin data_collision_b_a <= 2'b00; display_wa_wb; end + 6'b011011 : begin data_collision_b_a <= 2'b10; display_wa_wb; end + 6'b100011 : begin data_collision_b_a <= 2'b01; display_wa_wb; end + 6'b100111 : begin data_collision_b_a <= 2'b01; display_wa_wb; end + 6'b101011 : begin display_wa_wb; end + 6'b000001 : begin data_collision_b_a <= 2'b10; display_ra_wb; end + 6'b000101 : begin data_collision_b_a <= 2'b10; display_ra_wb; end + 6'b001001 : begin data_collision_b_a <= 2'b10; display_ra_wb; end + 6'b010001 : begin data_collision_b_a <= 2'b10; display_ra_wb; end + 6'b010101 : begin data_collision_b_a <= 2'b10; display_ra_wb; end + 6'b011001 : begin data_collision_b_a <= 2'b10; display_ra_wb; end + 6'b100001 : begin data_collision_b_a <= 2'b10; display_ra_wb; end + 6'b100101 : begin data_collision_b_a <= 2'b10; display_ra_wb; end + 6'b101001 : begin data_collision_b_a <= 2'b10; display_ra_wb; end + 6'b000010 : begin data_collision_b_a <= 2'b01; display_wa_rb; end + 6'b000110 : begin data_collision_b_a <= 2'b01; display_wa_rb; end + 6'b001010 : begin data_collision_b_a <= 2'b01; display_wa_rb; end +// 6'b010010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end +// 6'b010110 : begin data_collision_b_a <= 2'b00; display_wa_rb; end +// 6'b011010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end + 6'b100010 : begin data_collision_b_a <= 2'b01; display_wa_rb; end + 6'b100110 : begin data_collision_b_a <= 2'b01; display_wa_rb; end + 6'b101010 : begin data_collision_b_a <= 2'b01; display_wa_rb; end + endcase + end + end + setup_all_b_a <= 0; + end + + + always @(posedge setup_zero) begin + if (data_addra_int[14:4] == data_addrb_int[14:4]) begin + if ((ena_int == 1) && (enb_int == 1)) begin + case ({wr_mode_a, wr_mode_b, wea_int, web_int}) + 6'b000011 : begin data_collision <= 2'b11; display_wa_wb; end + 6'b000111 : begin data_collision <= 2'b11; display_wa_wb; end + 6'b001011 : begin data_collision <= 2'b10; display_wa_wb; end + 6'b010011 : begin data_collision <= 2'b11; display_wa_wb; end + 6'b010111 : begin data_collision <= 2'b11; display_wa_wb; end + 6'b011011 : begin data_collision <= 2'b10; display_wa_wb; end + 6'b100011 : begin data_collision <= 2'b01; display_wa_wb; end + 6'b100111 : begin data_collision <= 2'b01; display_wa_wb; end + 6'b101011 : begin display_wa_wb; end + 6'b000001 : begin data_collision <= 2'b10; display_ra_wb; end +// 6'b000101 : begin data_collision <= 2'b00; display_ra_wb; end + 6'b001001 : begin data_collision <= 2'b10; display_ra_wb; end + 6'b010001 : begin data_collision <= 2'b10; display_ra_wb; end +// 6'b010101 : begin data_collision <= 2'b00; display_ra_wb; end + 6'b011001 : begin data_collision <= 2'b10; display_ra_wb; end + 6'b100001 : begin data_collision <= 2'b10; display_ra_wb; end +// 6'b100101 : begin data_collision <= 2'b00; display_ra_wb; end + 6'b101001 : begin data_collision <= 2'b10; display_ra_wb; end + 6'b000010 : begin data_collision <= 2'b01; display_wa_rb; end + 6'b000110 : begin data_collision <= 2'b01; display_wa_rb; end + 6'b001010 : begin data_collision <= 2'b01; display_wa_rb; end +// 6'b010010 : begin data_collision <= 2'b00; display_wa_rb; end +// 6'b010110 : begin data_collision <= 2'b00; display_wa_rb; end +// 6'b011010 : begin data_collision <= 2'b00; display_wa_rb; end + 6'b100010 : begin data_collision <= 2'b01; display_wa_rb; end + 6'b100110 : begin data_collision <= 2'b01; display_wa_rb; end + 6'b101010 : begin data_collision <= 2'b01; display_wa_rb; end + endcase + end + end + setup_zero <= 0; + end + + task display_ra_wb; + begin + if (display_flag) + $display("Memory Collision Error on RAMB16_S2_S18:%m at simulation time %.3f ns\nA read was performed on address %h (hex) of Port A while a write was requested to the same address on Port B. The write will be successful however the read value on Port A is unknown until the next CLKA cycle.", $time/1000.0, addra_int); + end + endtask + + task display_wa_rb; + begin + if (display_flag) + $display("Memory Collision Error on RAMB16_S2_S18:%m at simulation time %.3f ns\nA read was performed on address %h (hex) of Port B while a write was requested to the same address on Port A. The write will be successful however the read value on Port B is unknown until the next CLKB cycle.", $time/1000.0, addrb_int); + end + endtask + + task display_wa_wb; + begin + if (display_flag) + $display("Memory Collision Error on RAMB16_S2_S18:%m at simulation time %.3f ns\nA write was requested to the same address simultaneously at both Port A and Port B of the RAM. The contents written to the RAM at address location %h (hex) of Port A and address location %h (hex) of Port B are unknown.", $time/1000.0, addra_int, addrb_int); + end + endtask + + + always @(posedge setup_rf_a_b) begin + if (data_addra_reg[14:4] == data_addrb_int[14:4]) begin + if ((ena_reg == 1) && (enb_int == 1)) begin + case ({wr_mode_a, wr_mode_b, wea_reg, web_int}) +// 6'b000011 : begin data_collision_a_b <= 2'b00; display_wa_wb; end +// 6'b000111 : begin data_collision_a_b <= 2'b00; display_wa_wb; end +// 6'b001011 : begin data_collision_a_b <= 2'b00; display_wa_wb; end + 6'b010011 : begin data_collision_a_b <= 2'b11; display_wa_wb; end + 6'b010111 : begin data_collision_a_b <= 2'b11; display_wa_wb; end + 6'b011011 : begin data_collision_a_b <= 2'b10; display_wa_wb; end +// 6'b100011 : begin data_collision_a_b <= 2'b00; display_wa_wb; end +// 6'b100111 : begin data_collision_a_b <= 2'b00; display_wa_wb; end +// 6'b101011 : begin data_collision_a_b <= 2'b00; display_wa_wb; end +// 6'b000001 : begin data_collision_a_b <= 2'b00; display_ra_wb; end +// 6'b000101 : begin data_collision_a_b <= 2'b00; display_ra_wb; end +// 6'b001001 : begin data_collision_a_b <= 2'b00; display_ra_wb; end +// 6'b010001 : begin data_collision_a_b <= 2'b00; display_ra_wb; end +// 6'b010101 : begin data_collision_a_b <= 2'b00; display_ra_wb; end +// 6'b011001 : begin data_collision_a_b <= 2'b00; display_ra_wb; end +// 6'b100001 : begin data_collision_a_b <= 2'b00; display_ra_wb; end +// 6'b100101 : begin data_collision_a_b <= 2'b00; display_ra_wb; end +// 6'b101001 : begin data_collision_a_b <= 2'b00; display_ra_wb; end +// 6'b000010 : begin data_collision_a_b <= 2'b00; display_wa_rb; end +// 6'b000110 : begin data_collision_a_b <= 2'b00; display_wa_rb; end +// 6'b001010 : begin data_collision_a_b <= 2'b00; display_wa_rb; end + 6'b010010 : begin data_collision_a_b <= 2'b01; display_wa_rb; end + 6'b010110 : begin data_collision_a_b <= 2'b01; display_wa_rb; end + 6'b011010 : begin data_collision_a_b <= 2'b01; display_wa_rb; end +// 6'b100010 : begin data_collision_a_b <= 2'b00; display_wa_rb; end +// 6'b100110 : begin data_collision_a_b <= 2'b00; display_wa_rb; end +// 6'b101010 : begin data_collision_a_b <= 2'b00; display_wa_rb; end + endcase + end + end + setup_rf_a_b <= 0; + end + + + always @(posedge setup_rf_b_a) begin + if (data_addra_int[14:4] == data_addrb_reg[14:4]) begin + if ((ena_int == 1) && (enb_reg == 1)) begin + case ({wr_mode_a, wr_mode_b, wea_int, web_reg}) +// 6'b000011 : begin data_collision_b_a <= 2'b00; display_wa_wb; end + 6'b000111 : begin data_collision_b_a <= 2'b11; display_wa_wb; end +// 6'b001011 : begin data_collision_b_a <= 2'b00; display_wa_wb; end +// 6'b010011 : begin data_collision_b_a <= 2'b00; display_wa_wb; end + 6'b010111 : begin data_collision_b_a <= 2'b11; display_wa_wb; end +// 6'b011011 : begin data_collision_b_a <= 2'b00; display_wa_wb; end +// 6'b100011 : begin data_collision_b_a <= 2'b00; display_wa_wb; end + 6'b100111 : begin data_collision_b_a <= 2'b01; display_wa_wb; end +// 6'b101011 : begin data_collision_b_a <= 2'b00; display_wa_wb; end +// 6'b000001 : begin data_collision_b_a <= 2'b00; display_ra_wb; end + 6'b000101 : begin data_collision_b_a <= 2'b10; display_ra_wb; end +// 6'b001001 : begin data_collision_b_a <= 2'b00; display_ra_wb; end +// 6'b010001 : begin data_collision_b_a <= 2'b00; display_ra_wb; end + 6'b010101 : begin data_collision_b_a <= 2'b10; display_ra_wb; end +// 6'b011001 : begin data_collision_b_a <= 2'b00; display_ra_wb; end +// 6'b100001 : begin data_collision_b_a <= 2'b00; display_ra_wb; end + 6'b100101 : begin data_collision_b_a <= 2'b10; display_ra_wb; end +// 6'b101001 : begin data_collision_b_a <= 2'b00; display_ra_wb; end +// 6'b000010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end +// 6'b000110 : begin data_collision_b_a <= 2'b00; display_wa_rb; end +// 6'b001010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end +// 6'b010010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end +// 6'b010110 : begin data_collision_b_a <= 2'b00; display_wa_rb; end +// 6'b011010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end +// 6'b100010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end +// 6'b100110 : begin data_collision_b_a <= 2'b00; display_wa_rb; end +// 6'b101010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end + endcase + end + end + setup_rf_b_a <= 0; + end + + + always @(posedge clka_int) begin + if ((output_flag || display_flag)) begin + addra_reg <= addra_int; + ena_reg <= ena_int; + ssra_reg <= ssra_int; + wea_reg <= wea_int; + end + end + + always @(posedge clkb_int) begin + if ((output_flag || display_flag)) begin + addrb_reg <= addrb_int; + enb_reg <= enb_int; + ssrb_reg <= ssrb_int; + web_reg <= web_int; + end + end + + + // Data + always @(posedge memory_collision) begin + if ((output_flag || display_flag)) begin + mem[addra_int[12:3]][addra_int[2:0] * 2 +: 2] <= 2'bx; + memory_collision <= 0; + end + + end + + always @(posedge memory_collision_a_b) begin + if ((output_flag || display_flag)) begin + mem[addra_reg[12:3]][addra_reg[2:0] * 2 +: 2] <= 2'bx; + memory_collision_a_b <= 0; + end + end + + always @(posedge memory_collision_b_a) begin + if ((output_flag || display_flag)) begin + mem[addra_int[12:3]][addra_int[2:0] * 2 +: 2] <= 2'bx; + memory_collision_b_a <= 0; + end + end + + always @(posedge data_collision[1]) begin + if (ssra_int == 0 && output_flag) begin + doa_out <= #100 2'bX; + end + data_collision[1] <= 0; + end + + always @(posedge data_collision[0]) begin + if (ssrb_int == 0 && output_flag) begin + dob_out[addra_int[2:0] * 2 +: 2] <= #100 2'bX; + end + data_collision[0] <= 0; + end + + always @(posedge data_collision_a_b[1]) begin + if (ssra_reg == 0 && output_flag) begin + doa_out <= #100 2'bX; + end + data_collision_a_b[1] <= 0; + end + + always @(posedge data_collision_a_b[0]) begin + if (ssrb_int == 0 && output_flag) begin + dob_out[addra_reg[2:0] * 2 +: 2] <= #100 2'bX; + end + data_collision_a_b[0] <= 0; + end + + always @(posedge data_collision_b_a[1]) begin + if (ssra_int == 0 && output_flag) begin + doa_out <= #100 2'bX; + end + data_collision_b_a[1] <= 0; + end + + always @(posedge data_collision_b_a[0]) begin + if (ssrb_reg == 0 && output_flag) begin + dob_out[addra_int[2:0] * 2 +: 2] <= #100 2'bX; + end + data_collision_b_a[0] <= 0; + end + + + initial begin + case (WRITE_MODE_A) + "WRITE_FIRST" : wr_mode_a <= 2'b00; + "READ_FIRST" : wr_mode_a <= 2'b01; + "NO_CHANGE" : wr_mode_a <= 2'b10; + default : begin + $display("Attribute Syntax Error : The Attribute WRITE_MODE_A on RAMB16_S2_S18 instance %m is set to %s. Legal values for this attribute are WRITE_FIRST, READ_FIRST or NO_CHANGE.", WRITE_MODE_A); + $finish; + end + endcase + end + + initial begin + case (WRITE_MODE_B) + "WRITE_FIRST" : wr_mode_b <= 2'b00; + "READ_FIRST" : wr_mode_b <= 2'b01; + "NO_CHANGE" : wr_mode_b <= 2'b10; + default : begin + $display("Attribute Syntax Error : The Attribute WRITE_MODE_B on RAMB16_S2_S18 instance %m is set to %s. Legal values for this attribute are WRITE_FIRST, READ_FIRST or NO_CHANGE.", WRITE_MODE_B); + $finish; + end + endcase + end + + + // Port A + always @(posedge clka_int) begin + + if (ena_int == 1'b1) begin + + if (ssra_int == 1'b1) begin + {doa_out} <= #100 SRVAL_A; + end + else begin + if (wea_int == 1'b1) begin + if (wr_mode_a == 2'b00) begin + doa_out <= #100 dia_int; + end + else if (wr_mode_a == 2'b01) begin + + doa_out <= #100 mem[addra_int[12:3]][addra_int[2:0] * 2 +: 2]; + + end + end + else begin + + doa_out <= #100 mem[addra_int[12:3]][addra_int[2:0] * 2 +: 2]; + + end + end + + // memory + if (wea_int == 1'b1) begin + mem[addra_int[12:3]][addra_int[2:0] * 2 +: 2] <= dia_int; + end + + end + end + + + // Port B + always @(posedge clkb_int) begin + + if (enb_int == 1'b1) begin + + if (ssrb_int == 1'b1) begin + {dopb_out, dob_out} <= #100 SRVAL_B; + end + else begin + if (web_int == 1'b1) begin + if (wr_mode_b == 2'b00) begin + dob_out <= #100 dib_int; + dopb_out <= #100 dipb_int; + end + else if (wr_mode_b == 2'b01) begin + dob_out <= #100 mem[addrb_int]; + dopb_out <= #100 memp[addrb_int]; + end + end + else begin + dob_out <= #100 mem[addrb_int]; + dopb_out <= #100 memp[addrb_int]; + end + end + + // memory + if (web_int == 1'b1) begin + mem[addrb_int] <= dib_int; + memp[addrb_int] <= dipb_int; + end + + end + end + + +endmodule + +`endif diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/RAMB16_S2_S2.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/RAMB16_S2_S2.v new file mode 100644 index 0000000..2a0b22e --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/RAMB16_S2_S2.v @@ -0,0 +1,1536 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/RAMB16_S2_S2.v,v 1.11 2007/02/22 01:58:06 wloo Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2005 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / 16K-Bit Data and 2K-Bit Parity Dual Port Block RAM +// /___/ /\ Filename : RAMB16_S2_S2.v +// \ \ / \ Timestamp : Thu Mar 10 16:43:36 PST 2005 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// End Revision + +`ifdef legacy_model + +`timescale 1 ps / 1 ps + +module RAMB16_S2_S2 (DOA, DOB, ADDRA, ADDRB, CLKA, CLKB, DIA, DIB, ENA, ENB, SSRA, SSRB, WEA, WEB); + + parameter INIT_A = 2'h0; + parameter INIT_B = 2'h0; + parameter SRVAL_A = 2'h0; + parameter SRVAL_B = 2'h0; + parameter WRITE_MODE_A = "WRITE_FIRST"; + parameter WRITE_MODE_B = "WRITE_FIRST"; + parameter SIM_COLLISION_CHECK = "ALL"; + localparam SETUP_ALL = 1000; + localparam SETUP_READ_FIRST = 3000; + + parameter INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + + output [1:0] DOA; + reg [1:0] doa_out; + wire doa_out0, doa_out1; + + input [12:0] ADDRA; + input [1:0] DIA; + input ENA, CLKA, WEA, SSRA; + + output [1:0] DOB; + reg [1:0] dob_out; + wire dob_out0, dob_out1; + + input [12:0] ADDRB; + input [1:0] DIB; + input ENB, CLKB, WEB, SSRB; + + reg [18431:0] mem; + reg [8:0] count; + reg [1:0] wr_mode_a, wr_mode_b; + + reg [5:0] dmi, dbi; + reg [5:0] pmi, pbi; + + wire [12:0] addra_int; + reg [12:0] addra_reg; + wire [1:0] dia_int; + wire ena_int, clka_int, wea_int, ssra_int; + reg ena_reg, wea_reg, ssra_reg; + wire [12:0] addrb_int; + reg [12:0] addrb_reg; + wire [1:0] dib_int; + wire enb_int, clkb_int, web_int, ssrb_int; + reg display_flag; + reg enb_reg, web_reg, ssrb_reg; + + time time_clka, time_clkb; + time time_clka_clkb; + time time_clkb_clka; + + reg setup_all_a_b; + reg setup_all_b_a; + reg setup_zero; + reg setup_rf_a_b; + reg setup_rf_b_a; + reg [1:0] data_collision, data_collision_a_b, data_collision_b_a; + reg memory_collision, memory_collision_a_b, memory_collision_b_a; + reg address_collision, address_collision_a_b, address_collision_b_a; + reg change_clka; + reg change_clkb; + + wire [14:0] data_addra_int; + wire [14:0] data_addra_reg; + wire [14:0] data_addrb_int; + wire [14:0] data_addrb_reg; + wire [15:0] parity_addra_int; + wire [15:0] parity_addra_reg; + wire [15:0] parity_addrb_int; + wire [15:0] parity_addrb_reg; + + tri0 GSR = glbl.GSR; + + always @(GSR) + if (GSR) begin + assign doa_out = INIT_A[1:0]; + assign dob_out = INIT_B[1:0]; + end + else begin + deassign doa_out; + deassign dob_out; + end + + buf b_doa_out0 (doa_out0, doa_out[0]); + buf b_doa_out1 (doa_out1, doa_out[1]); + buf b_dob_out0 (dob_out0, dob_out[0]); + buf b_dob_out1 (dob_out1, dob_out[1]); + + buf b_doa0 (DOA[0], doa_out0); + buf b_doa1 (DOA[1], doa_out1); + buf b_dob0 (DOB[0], dob_out0); + buf b_dob1 (DOB[1], dob_out1); + + buf b_addra_0 (addra_int[0], ADDRA[0]); + buf b_addra_1 (addra_int[1], ADDRA[1]); + buf b_addra_2 (addra_int[2], ADDRA[2]); + buf b_addra_3 (addra_int[3], ADDRA[3]); + buf b_addra_4 (addra_int[4], ADDRA[4]); + buf b_addra_5 (addra_int[5], ADDRA[5]); + buf b_addra_6 (addra_int[6], ADDRA[6]); + buf b_addra_7 (addra_int[7], ADDRA[7]); + buf b_addra_8 (addra_int[8], ADDRA[8]); + buf b_addra_9 (addra_int[9], ADDRA[9]); + buf b_addra_10 (addra_int[10], ADDRA[10]); + buf b_addra_11 (addra_int[11], ADDRA[11]); + buf b_addra_12 (addra_int[12], ADDRA[12]); + buf b_dia_0 (dia_int[0], DIA[0]); + buf b_dia_1 (dia_int[1], DIA[1]); + buf b_ena (ena_int, ENA); + buf b_clka (clka_int, CLKA); + buf b_ssra (ssra_int, SSRA); + buf b_wea (wea_int, WEA); + buf b_addrb_0 (addrb_int[0], ADDRB[0]); + buf b_addrb_1 (addrb_int[1], ADDRB[1]); + buf b_addrb_2 (addrb_int[2], ADDRB[2]); + buf b_addrb_3 (addrb_int[3], ADDRB[3]); + buf b_addrb_4 (addrb_int[4], ADDRB[4]); + buf b_addrb_5 (addrb_int[5], ADDRB[5]); + buf b_addrb_6 (addrb_int[6], ADDRB[6]); + buf b_addrb_7 (addrb_int[7], ADDRB[7]); + buf b_addrb_8 (addrb_int[8], ADDRB[8]); + buf b_addrb_9 (addrb_int[9], ADDRB[9]); + buf b_addrb_10 (addrb_int[10], ADDRB[10]); + buf b_addrb_11 (addrb_int[11], ADDRB[11]); + buf b_addrb_12 (addrb_int[12], ADDRB[12]); + buf b_dib_0 (dib_int[0], DIB[0]); + buf b_dib_1 (dib_int[1], DIB[1]); + buf b_enb (enb_int, ENB); + buf b_clkb (clkb_int, CLKB); + buf b_ssrb (ssrb_int, SSRB); + buf b_web (web_int, WEB); + + initial begin + for (count = 0; count < 256; count = count + 1) begin + mem[count] <= INIT_00[count]; + mem[256 * 1 + count] <= INIT_01[count]; + mem[256 * 2 + count] <= INIT_02[count]; + mem[256 * 3 + count] <= INIT_03[count]; + mem[256 * 4 + count] <= INIT_04[count]; + mem[256 * 5 + count] <= INIT_05[count]; + mem[256 * 6 + count] <= INIT_06[count]; + mem[256 * 7 + count] <= INIT_07[count]; + mem[256 * 8 + count] <= INIT_08[count]; + mem[256 * 9 + count] <= INIT_09[count]; + mem[256 * 10 + count] <= INIT_0A[count]; + mem[256 * 11 + count] <= INIT_0B[count]; + mem[256 * 12 + count] <= INIT_0C[count]; + mem[256 * 13 + count] <= INIT_0D[count]; + mem[256 * 14 + count] <= INIT_0E[count]; + mem[256 * 15 + count] <= INIT_0F[count]; + mem[256 * 16 + count] <= INIT_10[count]; + mem[256 * 17 + count] <= INIT_11[count]; + mem[256 * 18 + count] <= INIT_12[count]; + mem[256 * 19 + count] <= INIT_13[count]; + mem[256 * 20 + count] <= INIT_14[count]; + mem[256 * 21 + count] <= INIT_15[count]; + mem[256 * 22 + count] <= INIT_16[count]; + mem[256 * 23 + count] <= INIT_17[count]; + mem[256 * 24 + count] <= INIT_18[count]; + mem[256 * 25 + count] <= INIT_19[count]; + mem[256 * 26 + count] <= INIT_1A[count]; + mem[256 * 27 + count] <= INIT_1B[count]; + mem[256 * 28 + count] <= INIT_1C[count]; + mem[256 * 29 + count] <= INIT_1D[count]; + mem[256 * 30 + count] <= INIT_1E[count]; + mem[256 * 31 + count] <= INIT_1F[count]; + mem[256 * 32 + count] <= INIT_20[count]; + mem[256 * 33 + count] <= INIT_21[count]; + mem[256 * 34 + count] <= INIT_22[count]; + mem[256 * 35 + count] <= INIT_23[count]; + mem[256 * 36 + count] <= INIT_24[count]; + mem[256 * 37 + count] <= INIT_25[count]; + mem[256 * 38 + count] <= INIT_26[count]; + mem[256 * 39 + count] <= INIT_27[count]; + mem[256 * 40 + count] <= INIT_28[count]; + mem[256 * 41 + count] <= INIT_29[count]; + mem[256 * 42 + count] <= INIT_2A[count]; + mem[256 * 43 + count] <= INIT_2B[count]; + mem[256 * 44 + count] <= INIT_2C[count]; + mem[256 * 45 + count] <= INIT_2D[count]; + mem[256 * 46 + count] <= INIT_2E[count]; + mem[256 * 47 + count] <= INIT_2F[count]; + mem[256 * 48 + count] <= INIT_30[count]; + mem[256 * 49 + count] <= INIT_31[count]; + mem[256 * 50 + count] <= INIT_32[count]; + mem[256 * 51 + count] <= INIT_33[count]; + mem[256 * 52 + count] <= INIT_34[count]; + mem[256 * 53 + count] <= INIT_35[count]; + mem[256 * 54 + count] <= INIT_36[count]; + mem[256 * 55 + count] <= INIT_37[count]; + mem[256 * 56 + count] <= INIT_38[count]; + mem[256 * 57 + count] <= INIT_39[count]; + mem[256 * 58 + count] <= INIT_3A[count]; + mem[256 * 59 + count] <= INIT_3B[count]; + mem[256 * 60 + count] <= INIT_3C[count]; + mem[256 * 61 + count] <= INIT_3D[count]; + mem[256 * 62 + count] <= INIT_3E[count]; + mem[256 * 63 + count] <= INIT_3F[count]; + end + address_collision <= 0; + address_collision_a_b <= 0; + address_collision_b_a <= 0; + change_clka <= 0; + change_clkb <= 0; + data_collision <= 0; + data_collision_a_b <= 0; + data_collision_b_a <= 0; + memory_collision <= 0; + memory_collision_a_b <= 0; + memory_collision_b_a <= 0; + setup_all_a_b <= 0; + setup_all_b_a <= 0; + setup_zero <= 0; + setup_rf_a_b <= 0; + setup_rf_b_a <= 0; + end + + assign data_addra_int = addra_int * 2; + assign data_addra_reg = addra_reg * 2; + assign data_addrb_int = addrb_int * 2; + assign data_addrb_reg = addrb_reg * 2; + + + initial begin + + display_flag = 1; + + case (SIM_COLLISION_CHECK) + + "NONE" : begin + assign setup_all_a_b = 1'b0; + assign setup_all_b_a = 1'b0; + assign setup_zero = 1'b0; + assign setup_rf_a_b = 1'b0; + assign setup_rf_b_a = 1'b0; + assign display_flag = 0; + end + "WARNING_ONLY" : begin + assign data_collision = 2'b00; + assign data_collision_a_b = 2'b00; + assign data_collision_b_a = 2'b00; + assign memory_collision = 1'b0; + assign memory_collision_a_b = 1'b0; + assign memory_collision_b_a = 1'b0; + end + "GENERATE_X_ONLY" : begin + assign display_flag = 0; + end + "ALL" : ; + default : begin + $display("Attribute Syntax Error : The Attribute SIM_COLLISION_CHECK on RAMB16_S2_S2 instance %m is set to %s. Legal values for this attribute are ALL, NONE, WARNING_ONLY or GENERATE_X_ONLY.", SIM_COLLISION_CHECK); + $finish; + end + + endcase // case(SIM_COLLISION_CHECK) + + end // initial begin + + + always @(posedge clka_int) begin + time_clka = $time; + #0 time_clkb_clka = time_clka - time_clkb; + change_clka = ~change_clka; + end + + always @(posedge clkb_int) begin + time_clkb = $time; + #0 time_clka_clkb = time_clkb - time_clka; + change_clkb = ~change_clkb; + end + + always @(change_clkb) begin + if ((0 < time_clka_clkb) && (time_clka_clkb < SETUP_ALL)) + setup_all_a_b = 1; + if ((0 < time_clka_clkb) && (time_clka_clkb < SETUP_READ_FIRST)) + setup_rf_a_b = 1; + end + + always @(change_clka) begin + if ((0 < time_clkb_clka) && (time_clkb_clka < SETUP_ALL)) + setup_all_b_a = 1; + if ((0 < time_clkb_clka) && (time_clkb_clka < SETUP_READ_FIRST)) + setup_rf_b_a = 1; + end + + always @(change_clkb or change_clka) begin + if ((time_clkb_clka == 0) && (time_clka_clkb == 0)) + setup_zero = 1; + end + + always @(posedge setup_zero) begin + if ((ena_int == 1) && (wea_int == 1) && + (enb_int == 1) && (web_int == 1) && + (data_addra_int[14:1] == data_addrb_int[14:1])) + memory_collision <= 1; + end + + always @(posedge setup_all_a_b or posedge setup_rf_a_b) begin + if ((ena_reg == 1) && (wea_reg == 1) && + (enb_int == 1) && (web_int == 1) && + (data_addra_reg[14:1] == data_addrb_int[14:1])) + memory_collision_a_b <= 1; + end + + always @(posedge setup_all_b_a or posedge setup_rf_b_a) begin + if ((ena_int == 1) && (wea_int == 1) && + (enb_reg == 1) && (web_reg == 1) && + (data_addra_int[14:1] == data_addrb_reg[14:1])) + memory_collision_b_a <= 1; + end + + always @(posedge setup_all_a_b) begin + if (data_addra_reg[14:1] == data_addrb_int[14:1]) begin + if ((ena_reg == 1) && (enb_int == 1)) begin + case ({wr_mode_a, wr_mode_b, wea_reg, web_int}) + 6'b000011 : begin data_collision_a_b <= 2'b11; display_wa_wb; end + 6'b000111 : begin data_collision_a_b <= 2'b11; display_wa_wb; end + 6'b001011 : begin data_collision_a_b <= 2'b10; display_wa_wb; end +// 6'b010011 : begin data_collision_a_b <= 2'b00; display_wa_wb; end +// 6'b010111 : begin data_collision_a_b <= 2'b00; display_wa_wb; end +// 6'b011011 : begin data_collision_a_b <= 2'b00; display_wa_wb; end + 6'b100011 : begin data_collision_a_b <= 2'b01; display_wa_wb; end + 6'b100111 : begin data_collision_a_b <= 2'b01; display_wa_wb; end + 6'b101011 : begin display_wa_wb; end + 6'b000001 : begin data_collision_a_b <= 2'b10; display_ra_wb; end +// 6'b000101 : begin data_collision_a_b <= 2'b00; display_ra_wb; end + 6'b001001 : begin data_collision_a_b <= 2'b10; display_ra_wb; end + 6'b010001 : begin data_collision_a_b <= 2'b10; display_ra_wb; end +// 6'b010101 : begin data_collision_a_b <= 2'b00; display_ra_wb; end + 6'b011001 : begin data_collision_a_b <= 2'b10; display_ra_wb; end + 6'b100001 : begin data_collision_a_b <= 2'b10; display_ra_wb; end +// 6'b100101 : begin data_collision_a_b <= 2'b00; display_ra_wb; end + 6'b101001 : begin data_collision_a_b <= 2'b10; display_ra_wb; end + 6'b000010 : begin data_collision_a_b <= 2'b01; display_wa_rb; end + 6'b000110 : begin data_collision_a_b <= 2'b01; display_wa_rb; end + 6'b001010 : begin data_collision_a_b <= 2'b01; display_wa_rb; end +// 6'b010010 : begin data_collision_a_b <= 2'b00; display_wa_rb; end +// 6'b010110 : begin data_collision_a_b <= 2'b00; display_wa_rb; end +// 6'b011010 : begin data_collision_a_b <= 2'b00; display_wa_rb; end + 6'b100010 : begin data_collision_a_b <= 2'b01; display_wa_rb; end + 6'b100110 : begin data_collision_a_b <= 2'b01; display_wa_rb; end + 6'b101010 : begin data_collision_a_b <= 2'b01; display_wa_rb; end + endcase + end + end + setup_all_a_b <= 0; + end + + + always @(posedge setup_all_b_a) begin + if (data_addra_int[14:1] == data_addrb_reg[14:1]) begin + if ((ena_int == 1) && (enb_reg == 1)) begin + case ({wr_mode_a, wr_mode_b, wea_int, web_reg}) + 6'b000011 : begin data_collision_b_a <= 2'b11; display_wa_wb; end +// 6'b000111 : begin data_collision_b_a <= 2'b00; display_wa_wb; end + 6'b001011 : begin data_collision_b_a <= 2'b10; display_wa_wb; end + 6'b010011 : begin data_collision_b_a <= 2'b11; display_wa_wb; end +// 6'b010111 : begin data_collision_b_a <= 2'b00; display_wa_wb; end + 6'b011011 : begin data_collision_b_a <= 2'b10; display_wa_wb; end + 6'b100011 : begin data_collision_b_a <= 2'b01; display_wa_wb; end + 6'b100111 : begin data_collision_b_a <= 2'b01; display_wa_wb; end + 6'b101011 : begin display_wa_wb; end + 6'b000001 : begin data_collision_b_a <= 2'b10; display_ra_wb; end + 6'b000101 : begin data_collision_b_a <= 2'b10; display_ra_wb; end + 6'b001001 : begin data_collision_b_a <= 2'b10; display_ra_wb; end + 6'b010001 : begin data_collision_b_a <= 2'b10; display_ra_wb; end + 6'b010101 : begin data_collision_b_a <= 2'b10; display_ra_wb; end + 6'b011001 : begin data_collision_b_a <= 2'b10; display_ra_wb; end + 6'b100001 : begin data_collision_b_a <= 2'b10; display_ra_wb; end + 6'b100101 : begin data_collision_b_a <= 2'b10; display_ra_wb; end + 6'b101001 : begin data_collision_b_a <= 2'b10; display_ra_wb; end + 6'b000010 : begin data_collision_b_a <= 2'b01; display_wa_rb; end + 6'b000110 : begin data_collision_b_a <= 2'b01; display_wa_rb; end + 6'b001010 : begin data_collision_b_a <= 2'b01; display_wa_rb; end +// 6'b010010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end +// 6'b010110 : begin data_collision_b_a <= 2'b00; display_wa_rb; end +// 6'b011010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end + 6'b100010 : begin data_collision_b_a <= 2'b01; display_wa_rb; end + 6'b100110 : begin data_collision_b_a <= 2'b01; display_wa_rb; end + 6'b101010 : begin data_collision_b_a <= 2'b01; display_wa_rb; end + endcase + end + end + setup_all_b_a <= 0; + end + + + always @(posedge setup_zero) begin + if (data_addra_int[14:1] == data_addrb_int[14:1]) begin + if ((ena_int == 1) && (enb_int == 1)) begin + case ({wr_mode_a, wr_mode_b, wea_int, web_int}) + 6'b000011 : begin data_collision <= 2'b11; display_wa_wb; end + 6'b000111 : begin data_collision <= 2'b11; display_wa_wb; end + 6'b001011 : begin data_collision <= 2'b10; display_wa_wb; end + 6'b010011 : begin data_collision <= 2'b11; display_wa_wb; end + 6'b010111 : begin data_collision <= 2'b11; display_wa_wb; end + 6'b011011 : begin data_collision <= 2'b10; display_wa_wb; end + 6'b100011 : begin data_collision <= 2'b01; display_wa_wb; end + 6'b100111 : begin data_collision <= 2'b01; display_wa_wb; end + 6'b101011 : begin display_wa_wb; end + 6'b000001 : begin data_collision <= 2'b10; display_ra_wb; end +// 6'b000101 : begin data_collision <= 2'b00; display_ra_wb; end + 6'b001001 : begin data_collision <= 2'b10; display_ra_wb; end + 6'b010001 : begin data_collision <= 2'b10; display_ra_wb; end +// 6'b010101 : begin data_collision <= 2'b00; display_ra_wb; end + 6'b011001 : begin data_collision <= 2'b10; display_ra_wb; end + 6'b100001 : begin data_collision <= 2'b10; display_ra_wb; end +// 6'b100101 : begin data_collision <= 2'b00; display_ra_wb; end + 6'b101001 : begin data_collision <= 2'b10; display_ra_wb; end + 6'b000010 : begin data_collision <= 2'b01; display_wa_rb; end + 6'b000110 : begin data_collision <= 2'b01; display_wa_rb; end + 6'b001010 : begin data_collision <= 2'b01; display_wa_rb; end +// 6'b010010 : begin data_collision <= 2'b00; display_wa_rb; end +// 6'b010110 : begin data_collision <= 2'b00; display_wa_rb; end +// 6'b011010 : begin data_collision <= 2'b00; display_wa_rb; end + 6'b100010 : begin data_collision <= 2'b01; display_wa_rb; end + 6'b100110 : begin data_collision <= 2'b01; display_wa_rb; end + 6'b101010 : begin data_collision <= 2'b01; display_wa_rb; end + endcase + end + end + setup_zero <= 0; + end + + task display_ra_wb; + begin + if (display_flag) + $display("Memory Collision Error on RAMB16_S2_S2:%m at simulation time %.3f ns\nA read was performed on address %h (hex) of Port A while a write was requested to the same address on Port B. The write will be successful however the read value on Port A is unknown until the next CLKA cycle.", $time/1000.0, addra_int); + end + endtask + + task display_wa_rb; + begin + if (display_flag) + $display("Memory Collision Error on RAMB16_S2_S2:%m at simulation time %.3f ns\nA read was performed on address %h (hex) of Port B while a write was requested to the same address on Port A. The write will be successful however the read value on Port B is unknown until the next CLKB cycle.", $time/1000.0, addrb_int); + end + endtask + + task display_wa_wb; + begin + if (display_flag) + $display("Memory Collision Error on RAMB16_S2_S2:%m at simulation time %.3f ns\nA write was requested to the same address simultaneously at both Port A and Port B of the RAM. The contents written to the RAM at address location %h (hex) of Port A and address location %h (hex) of Port B are unknown.", $time/1000.0, addra_int, addrb_int); + end + endtask + + + always @(posedge setup_rf_a_b) begin + if (data_addra_reg[14:1] == data_addrb_int[14:1]) begin + if ((ena_reg == 1) && (enb_int == 1)) begin + case ({wr_mode_a, wr_mode_b, wea_reg, web_int}) +// 6'b000011 : begin data_collision_a_b <= 2'b00; display_wa_wb; end +// 6'b000111 : begin data_collision_a_b <= 2'b00; display_wa_wb; end +// 6'b001011 : begin data_collision_a_b <= 2'b00; display_wa_wb; end + 6'b010011 : begin data_collision_a_b <= 2'b11; display_wa_wb; end + 6'b010111 : begin data_collision_a_b <= 2'b11; display_wa_wb; end + 6'b011011 : begin data_collision_a_b <= 2'b10; display_wa_wb; end +// 6'b100011 : begin data_collision_a_b <= 2'b00; display_wa_wb; end +// 6'b100111 : begin data_collision_a_b <= 2'b00; display_wa_wb; end +// 6'b101011 : begin data_collision_a_b <= 2'b00; display_wa_wb; end +// 6'b000001 : begin data_collision_a_b <= 2'b00; display_ra_wb; end +// 6'b000101 : begin data_collision_a_b <= 2'b00; display_ra_wb; end +// 6'b001001 : begin data_collision_a_b <= 2'b00; display_ra_wb; end +// 6'b010001 : begin data_collision_a_b <= 2'b00; display_ra_wb; end +// 6'b010101 : begin data_collision_a_b <= 2'b00; display_ra_wb; end +// 6'b011001 : begin data_collision_a_b <= 2'b00; display_ra_wb; end +// 6'b100001 : begin data_collision_a_b <= 2'b00; display_ra_wb; end +// 6'b100101 : begin data_collision_a_b <= 2'b00; display_ra_wb; end +// 6'b101001 : begin data_collision_a_b <= 2'b00; display_ra_wb; end +// 6'b000010 : begin data_collision_a_b <= 2'b00; display_wa_rb; end +// 6'b000110 : begin data_collision_a_b <= 2'b00; display_wa_rb; end +// 6'b001010 : begin data_collision_a_b <= 2'b00; display_wa_rb; end + 6'b010010 : begin data_collision_a_b <= 2'b01; display_wa_rb; end + 6'b010110 : begin data_collision_a_b <= 2'b01; display_wa_rb; end + 6'b011010 : begin data_collision_a_b <= 2'b01; display_wa_rb; end +// 6'b100010 : begin data_collision_a_b <= 2'b00; display_wa_rb; end +// 6'b100110 : begin data_collision_a_b <= 2'b00; display_wa_rb; end +// 6'b101010 : begin data_collision_a_b <= 2'b00; display_wa_rb; end + endcase + end + end + setup_rf_a_b <= 0; + end + + + always @(posedge setup_rf_b_a) begin + if (data_addra_int[14:1] == data_addrb_reg[14:1]) begin + if ((ena_int == 1) && (enb_reg == 1)) begin + case ({wr_mode_a, wr_mode_b, wea_int, web_reg}) +// 6'b000011 : begin data_collision_b_a <= 2'b00; display_wa_wb; end + 6'b000111 : begin data_collision_b_a <= 2'b11; display_wa_wb; end +// 6'b001011 : begin data_collision_b_a <= 2'b00; display_wa_wb; end +// 6'b010011 : begin data_collision_b_a <= 2'b00; display_wa_wb; end + 6'b010111 : begin data_collision_b_a <= 2'b11; display_wa_wb; end +// 6'b011011 : begin data_collision_b_a <= 2'b00; display_wa_wb; end +// 6'b100011 : begin data_collision_b_a <= 2'b00; display_wa_wb; end + 6'b100111 : begin data_collision_b_a <= 2'b01; display_wa_wb; end +// 6'b101011 : begin data_collision_b_a <= 2'b00; display_wa_wb; end +// 6'b000001 : begin data_collision_b_a <= 2'b00; display_ra_wb; end + 6'b000101 : begin data_collision_b_a <= 2'b10; display_ra_wb; end +// 6'b001001 : begin data_collision_b_a <= 2'b00; display_ra_wb; end +// 6'b010001 : begin data_collision_b_a <= 2'b00; display_ra_wb; end + 6'b010101 : begin data_collision_b_a <= 2'b10; display_ra_wb; end +// 6'b011001 : begin data_collision_b_a <= 2'b00; display_ra_wb; end +// 6'b100001 : begin data_collision_b_a <= 2'b00; display_ra_wb; end + 6'b100101 : begin data_collision_b_a <= 2'b10; display_ra_wb; end +// 6'b101001 : begin data_collision_b_a <= 2'b00; display_ra_wb; end +// 6'b000010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end +// 6'b000110 : begin data_collision_b_a <= 2'b00; display_wa_rb; end +// 6'b001010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end +// 6'b010010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end +// 6'b010110 : begin data_collision_b_a <= 2'b00; display_wa_rb; end +// 6'b011010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end +// 6'b100010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end +// 6'b100110 : begin data_collision_b_a <= 2'b00; display_wa_rb; end +// 6'b101010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end + endcase + end + end + setup_rf_b_a <= 0; + end + + + always @(posedge clka_int) begin + addra_reg <= addra_int; + ena_reg <= ena_int; + ssra_reg <= ssra_int; + wea_reg <= wea_int; + end + + always @(posedge clkb_int) begin + addrb_reg <= addrb_int; + enb_reg <= enb_int; + ssrb_reg <= ssrb_int; + web_reg <= web_int; + end + + // Data + always @(posedge memory_collision) begin + for (dmi = 0; dmi < 2; dmi = dmi + 1) begin + mem[data_addra_int + dmi] <= 1'bX; + end + memory_collision <= 0; + end + + always @(posedge memory_collision_a_b) begin + for (dmi = 0; dmi < 2; dmi = dmi + 1) begin + mem[data_addra_reg + dmi] <= 1'bX; + end + memory_collision_a_b <= 0; + end + + always @(posedge memory_collision_b_a) begin + for (dmi = 0; dmi < 2; dmi = dmi + 1) begin + mem[data_addra_int + dmi] <= 1'bX; + end + memory_collision_b_a <= 0; + end + + always @(posedge data_collision[1]) begin + if (ssra_int == 0) begin + doa_out <= 2'bX; + end + data_collision[1] <= 0; + end + + always @(posedge data_collision[0]) begin + if (ssrb_int == 0) begin + dob_out <= 2'bX; + end + data_collision[0] <= 0; + end + + always @(posedge data_collision_a_b[1]) begin + if (ssra_reg == 0) begin + doa_out <= 2'bX; + end + data_collision_a_b[1] <= 0; + end + + always @(posedge data_collision_a_b[0]) begin + if (ssrb_int == 0) begin + dob_out <= 2'bX; + end + data_collision_a_b[0] <= 0; + end + + always @(posedge data_collision_b_a[1]) begin + if (ssra_int == 0) begin + doa_out <= 2'bX; + end + data_collision_b_a[1] <= 0; + end + + always @(posedge data_collision_b_a[0]) begin + if (ssrb_reg == 0) begin + dob_out <= 2'bX; + end + data_collision_b_a[0] <= 0; + end + + + initial begin + case (WRITE_MODE_A) + "WRITE_FIRST" : wr_mode_a <= 2'b00; + "READ_FIRST" : wr_mode_a <= 2'b01; + "NO_CHANGE" : wr_mode_a <= 2'b10; + default : begin + $display("Attribute Syntax Error : The Attribute WRITE_MODE_A on RAMB16_S2_S2 instance %m is set to %s. Legal values for this attribute are WRITE_FIRST, READ_FIRST or NO_CHANGE.", WRITE_MODE_A); + $finish; + end + endcase + end + + initial begin + case (WRITE_MODE_B) + "WRITE_FIRST" : wr_mode_b <= 2'b00; + "READ_FIRST" : wr_mode_b <= 2'b01; + "NO_CHANGE" : wr_mode_b <= 2'b10; + default : begin + $display("Attribute Syntax Error : The Attribute WRITE_MODE_B on RAMB16_S2_S2 instance %m is set to %s. Legal values for this attribute are WRITE_FIRST, READ_FIRST or NO_CHANGE.", WRITE_MODE_B); + $finish; + end + endcase + end + + // Port A + always @(posedge clka_int) begin + if (ena_int == 1'b1) begin + if (ssra_int == 1'b1) begin + doa_out[0] <= SRVAL_A[0]; + doa_out[1] <= SRVAL_A[1]; + end + else begin + if (wea_int == 1'b1) begin + if (wr_mode_a == 2'b00) begin + doa_out <= dia_int; + end + else if (wr_mode_a == 2'b01) begin + doa_out[0] <= mem[data_addra_int + 0]; + doa_out[1] <= mem[data_addra_int + 1]; + end + end + else begin + doa_out[0] <= mem[data_addra_int + 0]; + doa_out[1] <= mem[data_addra_int + 1]; + end + end + end + end + + always @(posedge clka_int) begin + if (ena_int == 1'b1 && wea_int == 1'b1) begin + mem[data_addra_int + 0] <= dia_int[0]; + mem[data_addra_int + 1] <= dia_int[1]; + end + end + + // Port B + always @(posedge clkb_int) begin + if (enb_int == 1'b1) begin + if (ssrb_int == 1'b1) begin + dob_out[0] <= SRVAL_B[0]; + dob_out[1] <= SRVAL_B[1]; + end + else begin + if (web_int == 1'b1) begin + if (wr_mode_b == 2'b00) begin + dob_out <= dib_int; + end + else if (wr_mode_b == 2'b01) begin + dob_out[0] <= mem[data_addrb_int + 0]; + dob_out[1] <= mem[data_addrb_int + 1]; + end + end + else begin + dob_out[0] <= mem[data_addrb_int + 0]; + dob_out[1] <= mem[data_addrb_int + 1]; + end + end + end + end + + always @(posedge clkb_int) begin + if (enb_int == 1'b1 && web_int == 1'b1) begin + mem[data_addrb_int + 0] <= dib_int[0]; + mem[data_addrb_int + 1] <= dib_int[1]; + end + end + + specify + (CLKA *> DOA) = (100, 100); + (CLKB *> DOB) = (100, 100); + endspecify + +endmodule + +`else + +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/RAMB16_S2_S2.v,v 1.11 2007/02/22 01:58:06 wloo Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2005 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Timing Simulation Library Component +// / / 16K-Bit Data and 2K-Bit Parity Dual Port Block RAM +// /___/ /\ Filename : RAMB16_S2_S2.v +// \ \ / \ Timestamp : Thu Mar 10 16:44:01 PST 2005 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 03/10/05 - Initialized outputs. +// 02/21/07 - Fixed parameter SIM_COLLISION_CHECK (CR 433281). +// End Revision + +`timescale 1 ps/1 ps + +module RAMB16_S2_S2 (DOA, DOB, ADDRA, ADDRB, CLKA, CLKB, DIA, DIB, ENA, ENB, SSRA, SSRB, WEA, WEB); + + parameter INIT_A = 2'h0; + parameter INIT_B = 2'h0; + parameter SRVAL_A = 2'h0; + parameter SRVAL_B = 2'h0; + parameter WRITE_MODE_A = "WRITE_FIRST"; + parameter WRITE_MODE_B = "WRITE_FIRST"; + parameter SIM_COLLISION_CHECK = "ALL"; + localparam SETUP_ALL = 1000; + localparam SETUP_READ_FIRST = 3000; + + parameter INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + + output [1:0] DOA; + output [1:0] DOB; + + input [12:0] ADDRA; + input [1:0] DIA; + input ENA, CLKA, WEA, SSRA; + input [12:0] ADDRB; + input [1:0] DIB; + input ENB, CLKB, WEB, SSRB; + + reg [1:0] doa_out = INIT_A[1:0]; + reg [1:0] dob_out = INIT_B[1:0]; + + reg [1:0] mem [8191:0]; + + reg [8:0] count, countp; + reg [1:0] wr_mode_a, wr_mode_b; + + reg [5:0] dmi, dbi; + reg [5:0] pmi, pbi; + + wire [12:0] addra_int; + reg [12:0] addra_reg; + wire [1:0] dia_int; + wire ena_int, clka_int, wea_int, ssra_int; + reg ena_reg, wea_reg, ssra_reg; + wire [12:0] addrb_int; + reg [12:0] addrb_reg; + wire [1:0] dib_int; + wire enb_int, clkb_int, web_int, ssrb_int; + reg display_flag, output_flag; + reg enb_reg, web_reg, ssrb_reg; + + time time_clka, time_clkb; + time time_clka_clkb; + time time_clkb_clka; + + reg setup_all_a_b; + reg setup_all_b_a; + reg setup_zero; + reg setup_rf_a_b; + reg setup_rf_b_a; + reg [1:0] data_collision, data_collision_a_b, data_collision_b_a; + reg memory_collision, memory_collision_a_b, memory_collision_b_a; + reg change_clka; + reg change_clkb; + + wire [14:0] data_addra_int; + wire [14:0] data_addra_reg; + wire [14:0] data_addrb_int; + wire [14:0] data_addrb_reg; + + wire dia_enable = ena_int && wea_int; + wire dib_enable = enb_int && web_int; + + tri0 GSR = glbl.GSR; + wire gsr_int; + + buf b_gsr (gsr_int, GSR); + + buf b_doa [1:0] (DOA, doa_out); + buf b_addra [12:0] (addra_int, ADDRA); + buf b_dia [1:0] (dia_int, DIA); + buf b_ena (ena_int, ENA); + buf b_clka (clka_int, CLKA); + buf b_ssra (ssra_int, SSRA); + buf b_wea (wea_int, WEA); + + buf b_dob [1:0] (DOB, dob_out); + buf b_addrb [12:0] (addrb_int, ADDRB); + buf b_dib [1:0] (dib_int, DIB); + buf b_enb (enb_int, ENB); + buf b_clkb (clkb_int, CLKB); + buf b_ssrb (ssrb_int, SSRB); + buf b_web (web_int, WEB); + + + always @(gsr_int) + if (gsr_int) begin + assign {doa_out} = INIT_A; + assign {dob_out} = INIT_B; + end + else begin + deassign doa_out; + deassign dob_out; + end + + + initial begin + + for (count = 0; count < 128; count = count + 1) begin + mem[count] = INIT_00[(count * 2) +: 2]; + mem[128 * 1 + count] = INIT_01[(count * 2) +: 2]; + mem[128 * 2 + count] = INIT_02[(count * 2) +: 2]; + mem[128 * 3 + count] = INIT_03[(count * 2) +: 2]; + mem[128 * 4 + count] = INIT_04[(count * 2) +: 2]; + mem[128 * 5 + count] = INIT_05[(count * 2) +: 2]; + mem[128 * 6 + count] = INIT_06[(count * 2) +: 2]; + mem[128 * 7 + count] = INIT_07[(count * 2) +: 2]; + mem[128 * 8 + count] = INIT_08[(count * 2) +: 2]; + mem[128 * 9 + count] = INIT_09[(count * 2) +: 2]; + mem[128 * 10 + count] = INIT_0A[(count * 2) +: 2]; + mem[128 * 11 + count] = INIT_0B[(count * 2) +: 2]; + mem[128 * 12 + count] = INIT_0C[(count * 2) +: 2]; + mem[128 * 13 + count] = INIT_0D[(count * 2) +: 2]; + mem[128 * 14 + count] = INIT_0E[(count * 2) +: 2]; + mem[128 * 15 + count] = INIT_0F[(count * 2) +: 2]; + mem[128 * 16 + count] = INIT_10[(count * 2) +: 2]; + mem[128 * 17 + count] = INIT_11[(count * 2) +: 2]; + mem[128 * 18 + count] = INIT_12[(count * 2) +: 2]; + mem[128 * 19 + count] = INIT_13[(count * 2) +: 2]; + mem[128 * 20 + count] = INIT_14[(count * 2) +: 2]; + mem[128 * 21 + count] = INIT_15[(count * 2) +: 2]; + mem[128 * 22 + count] = INIT_16[(count * 2) +: 2]; + mem[128 * 23 + count] = INIT_17[(count * 2) +: 2]; + mem[128 * 24 + count] = INIT_18[(count * 2) +: 2]; + mem[128 * 25 + count] = INIT_19[(count * 2) +: 2]; + mem[128 * 26 + count] = INIT_1A[(count * 2) +: 2]; + mem[128 * 27 + count] = INIT_1B[(count * 2) +: 2]; + mem[128 * 28 + count] = INIT_1C[(count * 2) +: 2]; + mem[128 * 29 + count] = INIT_1D[(count * 2) +: 2]; + mem[128 * 30 + count] = INIT_1E[(count * 2) +: 2]; + mem[128 * 31 + count] = INIT_1F[(count * 2) +: 2]; + mem[128 * 32 + count] = INIT_20[(count * 2) +: 2]; + mem[128 * 33 + count] = INIT_21[(count * 2) +: 2]; + mem[128 * 34 + count] = INIT_22[(count * 2) +: 2]; + mem[128 * 35 + count] = INIT_23[(count * 2) +: 2]; + mem[128 * 36 + count] = INIT_24[(count * 2) +: 2]; + mem[128 * 37 + count] = INIT_25[(count * 2) +: 2]; + mem[128 * 38 + count] = INIT_26[(count * 2) +: 2]; + mem[128 * 39 + count] = INIT_27[(count * 2) +: 2]; + mem[128 * 40 + count] = INIT_28[(count * 2) +: 2]; + mem[128 * 41 + count] = INIT_29[(count * 2) +: 2]; + mem[128 * 42 + count] = INIT_2A[(count * 2) +: 2]; + mem[128 * 43 + count] = INIT_2B[(count * 2) +: 2]; + mem[128 * 44 + count] = INIT_2C[(count * 2) +: 2]; + mem[128 * 45 + count] = INIT_2D[(count * 2) +: 2]; + mem[128 * 46 + count] = INIT_2E[(count * 2) +: 2]; + mem[128 * 47 + count] = INIT_2F[(count * 2) +: 2]; + mem[128 * 48 + count] = INIT_30[(count * 2) +: 2]; + mem[128 * 49 + count] = INIT_31[(count * 2) +: 2]; + mem[128 * 50 + count] = INIT_32[(count * 2) +: 2]; + mem[128 * 51 + count] = INIT_33[(count * 2) +: 2]; + mem[128 * 52 + count] = INIT_34[(count * 2) +: 2]; + mem[128 * 53 + count] = INIT_35[(count * 2) +: 2]; + mem[128 * 54 + count] = INIT_36[(count * 2) +: 2]; + mem[128 * 55 + count] = INIT_37[(count * 2) +: 2]; + mem[128 * 56 + count] = INIT_38[(count * 2) +: 2]; + mem[128 * 57 + count] = INIT_39[(count * 2) +: 2]; + mem[128 * 58 + count] = INIT_3A[(count * 2) +: 2]; + mem[128 * 59 + count] = INIT_3B[(count * 2) +: 2]; + mem[128 * 60 + count] = INIT_3C[(count * 2) +: 2]; + mem[128 * 61 + count] = INIT_3D[(count * 2) +: 2]; + mem[128 * 62 + count] = INIT_3E[(count * 2) +: 2]; + mem[128 * 63 + count] = INIT_3F[(count * 2) +: 2]; + end + + + change_clka <= 0; + change_clkb <= 0; + data_collision <= 0; + data_collision_a_b <= 0; + data_collision_b_a <= 0; + memory_collision <= 0; + memory_collision_a_b <= 0; + memory_collision_b_a <= 0; + setup_all_a_b <= 0; + setup_all_b_a <= 0; + setup_zero <= 0; + setup_rf_a_b <= 0; + setup_rf_b_a <= 0; + end + + assign data_addra_int = addra_int * 2; + assign data_addra_reg = addra_reg * 2; + assign data_addrb_int = addrb_int * 2; + assign data_addrb_reg = addrb_reg * 2; + + + initial begin + + display_flag = 1; + output_flag = 1; + + case (SIM_COLLISION_CHECK) + + "NONE" : begin + output_flag = 0; + display_flag = 0; + end + "WARNING_ONLY" : output_flag = 0; + "GENERATE_X_ONLY" : display_flag = 0; + "ALL" : ; + + default : begin + $display("Attribute Syntax Error : The Attribute SIM_COLLISION_CHECK on RAMB16_S2_S2 instance %m is set to %s. Legal values for this attribute are ALL, NONE, WARNING_ONLY or GENERATE_X_ONLY.", SIM_COLLISION_CHECK); + $finish; + end + + endcase // case(SIM_COLLISION_CHECK) + + end // initial begin + + + always @(posedge clka_int) begin + if ((output_flag || display_flag)) begin + time_clka = $time; + #0 time_clkb_clka = time_clka - time_clkb; + change_clka = ~change_clka; + end + end + + always @(posedge clkb_int) begin + if ((output_flag || display_flag)) begin + time_clkb = $time; + #0 time_clka_clkb = time_clkb - time_clka; + change_clkb = ~change_clkb; + end + end + + always @(change_clkb) begin + if ((0 < time_clka_clkb) && (time_clka_clkb < SETUP_ALL)) + setup_all_a_b = 1; + if ((0 < time_clka_clkb) && (time_clka_clkb < SETUP_READ_FIRST)) + setup_rf_a_b = 1; + end + + always @(change_clka) begin + if ((0 < time_clkb_clka) && (time_clkb_clka < SETUP_ALL)) + setup_all_b_a = 1; + if ((0 < time_clkb_clka) && (time_clkb_clka < SETUP_READ_FIRST)) + setup_rf_b_a = 1; + end + + always @(change_clkb or change_clka) begin + if ((time_clkb_clka == 0) && (time_clka_clkb == 0)) + setup_zero = 1; + end + + always @(posedge setup_zero) begin + if ((ena_int == 1) && (wea_int == 1) && + (enb_int == 1) && (web_int == 1) && + (data_addra_int[14:1] == data_addrb_int[14:1])) + memory_collision <= 1; + end + + always @(posedge setup_all_a_b or posedge setup_rf_a_b) begin + if ((ena_reg == 1) && (wea_reg == 1) && + (enb_int == 1) && (web_int == 1) && + (data_addra_reg[14:1] == data_addrb_int[14:1])) + memory_collision_a_b <= 1; + end + + always @(posedge setup_all_b_a or posedge setup_rf_b_a) begin + if ((ena_int == 1) && (wea_int == 1) && + (enb_reg == 1) && (web_reg == 1) && + (data_addra_int[14:1] == data_addrb_reg[14:1])) + memory_collision_b_a <= 1; + end + + always @(posedge setup_all_a_b) begin + if (data_addra_reg[14:1] == data_addrb_int[14:1]) begin + if ((ena_reg == 1) && (enb_int == 1)) begin + case ({wr_mode_a, wr_mode_b, wea_reg, web_int}) + 6'b000011 : begin data_collision_a_b <= 2'b11; display_wa_wb; end + 6'b000111 : begin data_collision_a_b <= 2'b11; display_wa_wb; end + 6'b001011 : begin data_collision_a_b <= 2'b10; display_wa_wb; end +// 6'b010011 : begin data_collision_a_b <= 2'b00; display_wa_wb; end +// 6'b010111 : begin data_collision_a_b <= 2'b00; display_wa_wb; end +// 6'b011011 : begin data_collision_a_b <= 2'b00; display_wa_wb; end + 6'b100011 : begin data_collision_a_b <= 2'b01; display_wa_wb; end + 6'b100111 : begin data_collision_a_b <= 2'b01; display_wa_wb; end + 6'b101011 : begin display_wa_wb; end + 6'b000001 : begin data_collision_a_b <= 2'b10; display_ra_wb; end +// 6'b000101 : begin data_collision_a_b <= 2'b00; display_ra_wb; end + 6'b001001 : begin data_collision_a_b <= 2'b10; display_ra_wb; end + 6'b010001 : begin data_collision_a_b <= 2'b10; display_ra_wb; end +// 6'b010101 : begin data_collision_a_b <= 2'b00; display_ra_wb; end + 6'b011001 : begin data_collision_a_b <= 2'b10; display_ra_wb; end + 6'b100001 : begin data_collision_a_b <= 2'b10; display_ra_wb; end +// 6'b100101 : begin data_collision_a_b <= 2'b00; display_ra_wb; end + 6'b101001 : begin data_collision_a_b <= 2'b10; display_ra_wb; end + 6'b000010 : begin data_collision_a_b <= 2'b01; display_wa_rb; end + 6'b000110 : begin data_collision_a_b <= 2'b01; display_wa_rb; end + 6'b001010 : begin data_collision_a_b <= 2'b01; display_wa_rb; end +// 6'b010010 : begin data_collision_a_b <= 2'b00; display_wa_rb; end +// 6'b010110 : begin data_collision_a_b <= 2'b00; display_wa_rb; end +// 6'b011010 : begin data_collision_a_b <= 2'b00; display_wa_rb; end + 6'b100010 : begin data_collision_a_b <= 2'b01; display_wa_rb; end + 6'b100110 : begin data_collision_a_b <= 2'b01; display_wa_rb; end + 6'b101010 : begin data_collision_a_b <= 2'b01; display_wa_rb; end + endcase + end + end + setup_all_a_b <= 0; + end + + + always @(posedge setup_all_b_a) begin + if (data_addra_int[14:1] == data_addrb_reg[14:1]) begin + if ((ena_int == 1) && (enb_reg == 1)) begin + case ({wr_mode_a, wr_mode_b, wea_int, web_reg}) + 6'b000011 : begin data_collision_b_a <= 2'b11; display_wa_wb; end +// 6'b000111 : begin data_collision_b_a <= 2'b00; display_wa_wb; end + 6'b001011 : begin data_collision_b_a <= 2'b10; display_wa_wb; end + 6'b010011 : begin data_collision_b_a <= 2'b11; display_wa_wb; end +// 6'b010111 : begin data_collision_b_a <= 2'b00; display_wa_wb; end + 6'b011011 : begin data_collision_b_a <= 2'b10; display_wa_wb; end + 6'b100011 : begin data_collision_b_a <= 2'b01; display_wa_wb; end + 6'b100111 : begin data_collision_b_a <= 2'b01; display_wa_wb; end + 6'b101011 : begin display_wa_wb; end + 6'b000001 : begin data_collision_b_a <= 2'b10; display_ra_wb; end + 6'b000101 : begin data_collision_b_a <= 2'b10; display_ra_wb; end + 6'b001001 : begin data_collision_b_a <= 2'b10; display_ra_wb; end + 6'b010001 : begin data_collision_b_a <= 2'b10; display_ra_wb; end + 6'b010101 : begin data_collision_b_a <= 2'b10; display_ra_wb; end + 6'b011001 : begin data_collision_b_a <= 2'b10; display_ra_wb; end + 6'b100001 : begin data_collision_b_a <= 2'b10; display_ra_wb; end + 6'b100101 : begin data_collision_b_a <= 2'b10; display_ra_wb; end + 6'b101001 : begin data_collision_b_a <= 2'b10; display_ra_wb; end + 6'b000010 : begin data_collision_b_a <= 2'b01; display_wa_rb; end + 6'b000110 : begin data_collision_b_a <= 2'b01; display_wa_rb; end + 6'b001010 : begin data_collision_b_a <= 2'b01; display_wa_rb; end +// 6'b010010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end +// 6'b010110 : begin data_collision_b_a <= 2'b00; display_wa_rb; end +// 6'b011010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end + 6'b100010 : begin data_collision_b_a <= 2'b01; display_wa_rb; end + 6'b100110 : begin data_collision_b_a <= 2'b01; display_wa_rb; end + 6'b101010 : begin data_collision_b_a <= 2'b01; display_wa_rb; end + endcase + end + end + setup_all_b_a <= 0; + end + + + always @(posedge setup_zero) begin + if (data_addra_int[14:1] == data_addrb_int[14:1]) begin + if ((ena_int == 1) && (enb_int == 1)) begin + case ({wr_mode_a, wr_mode_b, wea_int, web_int}) + 6'b000011 : begin data_collision <= 2'b11; display_wa_wb; end + 6'b000111 : begin data_collision <= 2'b11; display_wa_wb; end + 6'b001011 : begin data_collision <= 2'b10; display_wa_wb; end + 6'b010011 : begin data_collision <= 2'b11; display_wa_wb; end + 6'b010111 : begin data_collision <= 2'b11; display_wa_wb; end + 6'b011011 : begin data_collision <= 2'b10; display_wa_wb; end + 6'b100011 : begin data_collision <= 2'b01; display_wa_wb; end + 6'b100111 : begin data_collision <= 2'b01; display_wa_wb; end + 6'b101011 : begin display_wa_wb; end + 6'b000001 : begin data_collision <= 2'b10; display_ra_wb; end +// 6'b000101 : begin data_collision <= 2'b00; display_ra_wb; end + 6'b001001 : begin data_collision <= 2'b10; display_ra_wb; end + 6'b010001 : begin data_collision <= 2'b10; display_ra_wb; end +// 6'b010101 : begin data_collision <= 2'b00; display_ra_wb; end + 6'b011001 : begin data_collision <= 2'b10; display_ra_wb; end + 6'b100001 : begin data_collision <= 2'b10; display_ra_wb; end +// 6'b100101 : begin data_collision <= 2'b00; display_ra_wb; end + 6'b101001 : begin data_collision <= 2'b10; display_ra_wb; end + 6'b000010 : begin data_collision <= 2'b01; display_wa_rb; end + 6'b000110 : begin data_collision <= 2'b01; display_wa_rb; end + 6'b001010 : begin data_collision <= 2'b01; display_wa_rb; end +// 6'b010010 : begin data_collision <= 2'b00; display_wa_rb; end +// 6'b010110 : begin data_collision <= 2'b00; display_wa_rb; end +// 6'b011010 : begin data_collision <= 2'b00; display_wa_rb; end + 6'b100010 : begin data_collision <= 2'b01; display_wa_rb; end + 6'b100110 : begin data_collision <= 2'b01; display_wa_rb; end + 6'b101010 : begin data_collision <= 2'b01; display_wa_rb; end + endcase + end + end + setup_zero <= 0; + end + + task display_ra_wb; + begin + if (display_flag) + $display("Memory Collision Error on RAMB16_S2_S2:%m at simulation time %.3f ns\nA read was performed on address %h (hex) of Port A while a write was requested to the same address on Port B. The write will be successful however the read value on Port A is unknown until the next CLKA cycle.", $time/1000.0, addra_int); + end + endtask + + task display_wa_rb; + begin + if (display_flag) + $display("Memory Collision Error on RAMB16_S2_S2:%m at simulation time %.3f ns\nA read was performed on address %h (hex) of Port B while a write was requested to the same address on Port A. The write will be successful however the read value on Port B is unknown until the next CLKB cycle.", $time/1000.0, addrb_int); + end + endtask + + task display_wa_wb; + begin + if (display_flag) + $display("Memory Collision Error on RAMB16_S2_S2:%m at simulation time %.3f ns\nA write was requested to the same address simultaneously at both Port A and Port B of the RAM. The contents written to the RAM at address location %h (hex) of Port A and address location %h (hex) of Port B are unknown.", $time/1000.0, addra_int, addrb_int); + end + endtask + + + always @(posedge setup_rf_a_b) begin + if (data_addra_reg[14:1] == data_addrb_int[14:1]) begin + if ((ena_reg == 1) && (enb_int == 1)) begin + case ({wr_mode_a, wr_mode_b, wea_reg, web_int}) +// 6'b000011 : begin data_collision_a_b <= 2'b00; display_wa_wb; end +// 6'b000111 : begin data_collision_a_b <= 2'b00; display_wa_wb; end +// 6'b001011 : begin data_collision_a_b <= 2'b00; display_wa_wb; end + 6'b010011 : begin data_collision_a_b <= 2'b11; display_wa_wb; end + 6'b010111 : begin data_collision_a_b <= 2'b11; display_wa_wb; end + 6'b011011 : begin data_collision_a_b <= 2'b10; display_wa_wb; end +// 6'b100011 : begin data_collision_a_b <= 2'b00; display_wa_wb; end +// 6'b100111 : begin data_collision_a_b <= 2'b00; display_wa_wb; end +// 6'b101011 : begin data_collision_a_b <= 2'b00; display_wa_wb; end +// 6'b000001 : begin data_collision_a_b <= 2'b00; display_ra_wb; end +// 6'b000101 : begin data_collision_a_b <= 2'b00; display_ra_wb; end +// 6'b001001 : begin data_collision_a_b <= 2'b00; display_ra_wb; end +// 6'b010001 : begin data_collision_a_b <= 2'b00; display_ra_wb; end +// 6'b010101 : begin data_collision_a_b <= 2'b00; display_ra_wb; end +// 6'b011001 : begin data_collision_a_b <= 2'b00; display_ra_wb; end +// 6'b100001 : begin data_collision_a_b <= 2'b00; display_ra_wb; end +// 6'b100101 : begin data_collision_a_b <= 2'b00; display_ra_wb; end +// 6'b101001 : begin data_collision_a_b <= 2'b00; display_ra_wb; end +// 6'b000010 : begin data_collision_a_b <= 2'b00; display_wa_rb; end +// 6'b000110 : begin data_collision_a_b <= 2'b00; display_wa_rb; end +// 6'b001010 : begin data_collision_a_b <= 2'b00; display_wa_rb; end + 6'b010010 : begin data_collision_a_b <= 2'b01; display_wa_rb; end + 6'b010110 : begin data_collision_a_b <= 2'b01; display_wa_rb; end + 6'b011010 : begin data_collision_a_b <= 2'b01; display_wa_rb; end +// 6'b100010 : begin data_collision_a_b <= 2'b00; display_wa_rb; end +// 6'b100110 : begin data_collision_a_b <= 2'b00; display_wa_rb; end +// 6'b101010 : begin data_collision_a_b <= 2'b00; display_wa_rb; end + endcase + end + end + setup_rf_a_b <= 0; + end + + + always @(posedge setup_rf_b_a) begin + if (data_addra_int[14:1] == data_addrb_reg[14:1]) begin + if ((ena_int == 1) && (enb_reg == 1)) begin + case ({wr_mode_a, wr_mode_b, wea_int, web_reg}) +// 6'b000011 : begin data_collision_b_a <= 2'b00; display_wa_wb; end + 6'b000111 : begin data_collision_b_a <= 2'b11; display_wa_wb; end +// 6'b001011 : begin data_collision_b_a <= 2'b00; display_wa_wb; end +// 6'b010011 : begin data_collision_b_a <= 2'b00; display_wa_wb; end + 6'b010111 : begin data_collision_b_a <= 2'b11; display_wa_wb; end +// 6'b011011 : begin data_collision_b_a <= 2'b00; display_wa_wb; end +// 6'b100011 : begin data_collision_b_a <= 2'b00; display_wa_wb; end + 6'b100111 : begin data_collision_b_a <= 2'b01; display_wa_wb; end +// 6'b101011 : begin data_collision_b_a <= 2'b00; display_wa_wb; end +// 6'b000001 : begin data_collision_b_a <= 2'b00; display_ra_wb; end + 6'b000101 : begin data_collision_b_a <= 2'b10; display_ra_wb; end +// 6'b001001 : begin data_collision_b_a <= 2'b00; display_ra_wb; end +// 6'b010001 : begin data_collision_b_a <= 2'b00; display_ra_wb; end + 6'b010101 : begin data_collision_b_a <= 2'b10; display_ra_wb; end +// 6'b011001 : begin data_collision_b_a <= 2'b00; display_ra_wb; end +// 6'b100001 : begin data_collision_b_a <= 2'b00; display_ra_wb; end + 6'b100101 : begin data_collision_b_a <= 2'b10; display_ra_wb; end +// 6'b101001 : begin data_collision_b_a <= 2'b00; display_ra_wb; end +// 6'b000010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end +// 6'b000110 : begin data_collision_b_a <= 2'b00; display_wa_rb; end +// 6'b001010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end +// 6'b010010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end +// 6'b010110 : begin data_collision_b_a <= 2'b00; display_wa_rb; end +// 6'b011010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end +// 6'b100010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end +// 6'b100110 : begin data_collision_b_a <= 2'b00; display_wa_rb; end +// 6'b101010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end + endcase + end + end + setup_rf_b_a <= 0; + end + + + always @(posedge clka_int) begin + if ((output_flag || display_flag)) begin + addra_reg <= addra_int; + ena_reg <= ena_int; + ssra_reg <= ssra_int; + wea_reg <= wea_int; + end + end + + always @(posedge clkb_int) begin + if ((output_flag || display_flag)) begin + addrb_reg <= addrb_int; + enb_reg <= enb_int; + ssrb_reg <= ssrb_int; + web_reg <= web_int; + end + end + + + // Data + always @(posedge memory_collision) begin + if ((output_flag || display_flag)) begin + mem[addra_int] <= 2'bx; + memory_collision <= 0; + end + + end + + always @(posedge memory_collision_a_b) begin + if ((output_flag || display_flag)) begin + mem[addra_reg] <= 2'bx; + memory_collision_a_b <= 0; + end + end + + always @(posedge memory_collision_b_a) begin + if ((output_flag || display_flag)) begin + mem[addra_int] <= 2'bx; + memory_collision_b_a <= 0; + end + end + + always @(posedge data_collision[1]) begin + if (ssra_int == 0 && output_flag) begin + doa_out <= #100 2'bX; + end + data_collision[1] <= 0; + end + + always @(posedge data_collision[0]) begin + if (ssrb_int == 0 && output_flag) begin + dob_out <= #100 2'bX; + end + data_collision[0] <= 0; + end + + always @(posedge data_collision_a_b[1]) begin + if (ssra_reg == 0 && output_flag) begin + doa_out <= #100 2'bX; + end + data_collision_a_b[1] <= 0; + end + + always @(posedge data_collision_a_b[0]) begin + if (ssrb_int == 0 && output_flag) begin + dob_out <= #100 2'bX; + end + data_collision_a_b[0] <= 0; + end + + always @(posedge data_collision_b_a[1]) begin + if (ssra_int == 0 && output_flag) begin + doa_out <= #100 2'bX; + end + data_collision_b_a[1] <= 0; + end + + always @(posedge data_collision_b_a[0]) begin + if (ssrb_reg == 0 && output_flag) begin + dob_out <= #100 2'bX; + end + data_collision_b_a[0] <= 0; + end + + + initial begin + case (WRITE_MODE_A) + "WRITE_FIRST" : wr_mode_a <= 2'b00; + "READ_FIRST" : wr_mode_a <= 2'b01; + "NO_CHANGE" : wr_mode_a <= 2'b10; + default : begin + $display("Attribute Syntax Error : The Attribute WRITE_MODE_A on RAMB16_S2_S2 instance %m is set to %s. Legal values for this attribute are WRITE_FIRST, READ_FIRST or NO_CHANGE.", WRITE_MODE_A); + $finish; + end + endcase + end + + initial begin + case (WRITE_MODE_B) + "WRITE_FIRST" : wr_mode_b <= 2'b00; + "READ_FIRST" : wr_mode_b <= 2'b01; + "NO_CHANGE" : wr_mode_b <= 2'b10; + default : begin + $display("Attribute Syntax Error : The Attribute WRITE_MODE_B on RAMB16_S2_S2 instance %m is set to %s. Legal values for this attribute are WRITE_FIRST, READ_FIRST or NO_CHANGE.", WRITE_MODE_B); + $finish; + end + endcase + end + + + // Port A + always @(posedge clka_int) begin + + if (ena_int == 1'b1) begin + + if (ssra_int == 1'b1) begin + {doa_out} <= #100 SRVAL_A; + end + else begin + if (wea_int == 1'b1) begin + if (wr_mode_a == 2'b00) begin + doa_out <= #100 dia_int; + end + else if (wr_mode_a == 2'b01) begin + + doa_out <= #100 mem[addra_int]; + + end + end + else begin + + doa_out <= #100 mem[addra_int]; + + end + end + + // memory + if (wea_int == 1'b1) begin + mem[addra_int] <= dia_int; + end + + end + end + + + // Port B + always @(posedge clkb_int) begin + + if (enb_int == 1'b1) begin + + if (ssrb_int == 1'b1) begin + {dob_out} <= #100 SRVAL_B; + end + else begin + if (web_int == 1'b1) begin + if (wr_mode_b == 2'b00) begin + dob_out <= #100 dib_int; + end + else if (wr_mode_b == 2'b01) begin + dob_out <= #100 mem[addrb_int]; + end + end + else begin + dob_out <= #100 mem[addrb_int]; + end + end + + // memory + if (web_int == 1'b1) begin + mem[addrb_int] <= dib_int; + end + + end + end + + +endmodule + +`endif diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/RAMB16_S2_S36.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/RAMB16_S2_S36.v new file mode 100644 index 0000000..f023902 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/RAMB16_S2_S36.v @@ -0,0 +1,1835 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/RAMB16_S2_S36.v,v 1.10 2007/02/22 01:58:06 wloo Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2005 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / 16K-Bit Data and 2K-Bit Parity Dual Port Block RAM +// /___/ /\ Filename : RAMB16_S2_S36.v +// \ \ / \ Timestamp : Thu Mar 10 16:43:36 PST 2005 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// End Revision + +`ifdef legacy_model + +`timescale 1 ps / 1 ps + +module RAMB16_S2_S36 (DOA, DOB, DOPB, ADDRA, ADDRB, CLKA, CLKB, DIA, DIB, DIPB, ENA, ENB, SSRA, SSRB, WEA, WEB); + + parameter INIT_A = 2'h0; + parameter INIT_B = 36'h0; + parameter SRVAL_A = 2'h0; + parameter SRVAL_B = 36'h0; + parameter WRITE_MODE_A = "WRITE_FIRST"; + parameter WRITE_MODE_B = "WRITE_FIRST"; + parameter SIM_COLLISION_CHECK = "ALL"; + localparam SETUP_ALL = 1000; + localparam SETUP_READ_FIRST = 3000; + + parameter INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + + output [1:0] DOA; + reg [1:0] doa_out; + wire doa_out0, doa_out1; + + input [12:0] ADDRA; + input [1:0] DIA; + input ENA, CLKA, WEA, SSRA; + + output [31:0] DOB; + output [3:0] DOPB; + reg [31:0] dob_out; + reg [3:0] dopb_out; + wire dob_out0, dob_out1, dob_out2, dob_out3, dob_out4, dob_out5, dob_out6, dob_out7, dob_out8, dob_out9, dob_out10, dob_out11, dob_out12, dob_out13, dob_out14, dob_out15, dob_out16, dob_out17, dob_out18, dob_out19, dob_out20, dob_out21, dob_out22, dob_out23, dob_out24, dob_out25, dob_out26, dob_out27, dob_out28, dob_out29, dob_out30, dob_out31; + wire dopb0_out, dopb1_out, dopb2_out, dopb3_out; + + input [8:0] ADDRB; + input [31:0] DIB; + input [3:0] DIPB; + input ENB, CLKB, WEB, SSRB; + + reg [18431:0] mem; + reg [8:0] count; + reg [1:0] wr_mode_a, wr_mode_b; + + reg [5:0] dmi, dbi; + reg [5:0] pmi, pbi; + + wire [12:0] addra_int; + reg [12:0] addra_reg; + wire [1:0] dia_int; + wire ena_int, clka_int, wea_int, ssra_int; + reg ena_reg, wea_reg, ssra_reg; + wire [8:0] addrb_int; + reg [8:0] addrb_reg; + wire [31:0] dib_int; + wire [3:0] dipb_int; + wire enb_int, clkb_int, web_int, ssrb_int; + reg display_flag; + reg enb_reg, web_reg, ssrb_reg; + + time time_clka, time_clkb; + time time_clka_clkb; + time time_clkb_clka; + + reg setup_all_a_b; + reg setup_all_b_a; + reg setup_zero; + reg setup_rf_a_b; + reg setup_rf_b_a; + reg [1:0] data_collision, data_collision_a_b, data_collision_b_a; + reg memory_collision, memory_collision_a_b, memory_collision_b_a; + reg address_collision, address_collision_a_b, address_collision_b_a; + reg change_clka; + reg change_clkb; + + wire [14:0] data_addra_int; + wire [14:0] data_addra_reg; + wire [14:0] data_addrb_int; + wire [14:0] data_addrb_reg; + wire [15:0] parity_addra_int; + wire [15:0] parity_addra_reg; + wire [15:0] parity_addrb_int; + wire [15:0] parity_addrb_reg; + + tri0 GSR = glbl.GSR; + + always @(GSR) + if (GSR) begin + assign doa_out = INIT_A[1:0]; + assign dob_out = INIT_B[31:0]; + assign dopb_out = INIT_B[35:32]; + end + else begin + deassign doa_out; + deassign dob_out; + deassign dopb_out; + end + + buf b_doa_out0 (doa_out0, doa_out[0]); + buf b_doa_out1 (doa_out1, doa_out[1]); + buf b_dob_out0 (dob_out0, dob_out[0]); + buf b_dob_out1 (dob_out1, dob_out[1]); + buf b_dob_out2 (dob_out2, dob_out[2]); + buf b_dob_out3 (dob_out3, dob_out[3]); + buf b_dob_out4 (dob_out4, dob_out[4]); + buf b_dob_out5 (dob_out5, dob_out[5]); + buf b_dob_out6 (dob_out6, dob_out[6]); + buf b_dob_out7 (dob_out7, dob_out[7]); + buf b_dob_out8 (dob_out8, dob_out[8]); + buf b_dob_out9 (dob_out9, dob_out[9]); + buf b_dob_out10 (dob_out10, dob_out[10]); + buf b_dob_out11 (dob_out11, dob_out[11]); + buf b_dob_out12 (dob_out12, dob_out[12]); + buf b_dob_out13 (dob_out13, dob_out[13]); + buf b_dob_out14 (dob_out14, dob_out[14]); + buf b_dob_out15 (dob_out15, dob_out[15]); + buf b_dob_out16 (dob_out16, dob_out[16]); + buf b_dob_out17 (dob_out17, dob_out[17]); + buf b_dob_out18 (dob_out18, dob_out[18]); + buf b_dob_out19 (dob_out19, dob_out[19]); + buf b_dob_out20 (dob_out20, dob_out[20]); + buf b_dob_out21 (dob_out21, dob_out[21]); + buf b_dob_out22 (dob_out22, dob_out[22]); + buf b_dob_out23 (dob_out23, dob_out[23]); + buf b_dob_out24 (dob_out24, dob_out[24]); + buf b_dob_out25 (dob_out25, dob_out[25]); + buf b_dob_out26 (dob_out26, dob_out[26]); + buf b_dob_out27 (dob_out27, dob_out[27]); + buf b_dob_out28 (dob_out28, dob_out[28]); + buf b_dob_out29 (dob_out29, dob_out[29]); + buf b_dob_out30 (dob_out30, dob_out[30]); + buf b_dob_out31 (dob_out31, dob_out[31]); + buf b_dopb_out0 (dopb_out0, dopb_out[0]); + buf b_dopb_out1 (dopb_out1, dopb_out[1]); + buf b_dopb_out2 (dopb_out2, dopb_out[2]); + buf b_dopb_out3 (dopb_out3, dopb_out[3]); + + buf b_doa0 (DOA[0], doa_out0); + buf b_doa1 (DOA[1], doa_out1); + buf b_dob0 (DOB[0], dob_out0); + buf b_dob1 (DOB[1], dob_out1); + buf b_dob2 (DOB[2], dob_out2); + buf b_dob3 (DOB[3], dob_out3); + buf b_dob4 (DOB[4], dob_out4); + buf b_dob5 (DOB[5], dob_out5); + buf b_dob6 (DOB[6], dob_out6); + buf b_dob7 (DOB[7], dob_out7); + buf b_dob8 (DOB[8], dob_out8); + buf b_dob9 (DOB[9], dob_out9); + buf b_dob10 (DOB[10], dob_out10); + buf b_dob11 (DOB[11], dob_out11); + buf b_dob12 (DOB[12], dob_out12); + buf b_dob13 (DOB[13], dob_out13); + buf b_dob14 (DOB[14], dob_out14); + buf b_dob15 (DOB[15], dob_out15); + buf b_dob16 (DOB[16], dob_out16); + buf b_dob17 (DOB[17], dob_out17); + buf b_dob18 (DOB[18], dob_out18); + buf b_dob19 (DOB[19], dob_out19); + buf b_dob20 (DOB[20], dob_out20); + buf b_dob21 (DOB[21], dob_out21); + buf b_dob22 (DOB[22], dob_out22); + buf b_dob23 (DOB[23], dob_out23); + buf b_dob24 (DOB[24], dob_out24); + buf b_dob25 (DOB[25], dob_out25); + buf b_dob26 (DOB[26], dob_out26); + buf b_dob27 (DOB[27], dob_out27); + buf b_dob28 (DOB[28], dob_out28); + buf b_dob29 (DOB[29], dob_out29); + buf b_dob30 (DOB[30], dob_out30); + buf b_dob31 (DOB[31], dob_out31); + buf b_dopb0 (DOPB[0], dopb_out0); + buf b_dopb1 (DOPB[1], dopb_out1); + buf b_dopb2 (DOPB[2], dopb_out2); + buf b_dopb3 (DOPB[3], dopb_out3); + + buf b_addra_0 (addra_int[0], ADDRA[0]); + buf b_addra_1 (addra_int[1], ADDRA[1]); + buf b_addra_2 (addra_int[2], ADDRA[2]); + buf b_addra_3 (addra_int[3], ADDRA[3]); + buf b_addra_4 (addra_int[4], ADDRA[4]); + buf b_addra_5 (addra_int[5], ADDRA[5]); + buf b_addra_6 (addra_int[6], ADDRA[6]); + buf b_addra_7 (addra_int[7], ADDRA[7]); + buf b_addra_8 (addra_int[8], ADDRA[8]); + buf b_addra_9 (addra_int[9], ADDRA[9]); + buf b_addra_10 (addra_int[10], ADDRA[10]); + buf b_addra_11 (addra_int[11], ADDRA[11]); + buf b_addra_12 (addra_int[12], ADDRA[12]); + buf b_dia_0 (dia_int[0], DIA[0]); + buf b_dia_1 (dia_int[1], DIA[1]); + buf b_ena (ena_int, ENA); + buf b_clka (clka_int, CLKA); + buf b_ssra (ssra_int, SSRA); + buf b_wea (wea_int, WEA); + buf b_addrb_0 (addrb_int[0], ADDRB[0]); + buf b_addrb_1 (addrb_int[1], ADDRB[1]); + buf b_addrb_2 (addrb_int[2], ADDRB[2]); + buf b_addrb_3 (addrb_int[3], ADDRB[3]); + buf b_addrb_4 (addrb_int[4], ADDRB[4]); + buf b_addrb_5 (addrb_int[5], ADDRB[5]); + buf b_addrb_6 (addrb_int[6], ADDRB[6]); + buf b_addrb_7 (addrb_int[7], ADDRB[7]); + buf b_addrb_8 (addrb_int[8], ADDRB[8]); + buf b_dib_0 (dib_int[0], DIB[0]); + buf b_dib_1 (dib_int[1], DIB[1]); + buf b_dib_2 (dib_int[2], DIB[2]); + buf b_dib_3 (dib_int[3], DIB[3]); + buf b_dib_4 (dib_int[4], DIB[4]); + buf b_dib_5 (dib_int[5], DIB[5]); + buf b_dib_6 (dib_int[6], DIB[6]); + buf b_dib_7 (dib_int[7], DIB[7]); + buf b_dib_8 (dib_int[8], DIB[8]); + buf b_dib_9 (dib_int[9], DIB[9]); + buf b_dib_10 (dib_int[10], DIB[10]); + buf b_dib_11 (dib_int[11], DIB[11]); + buf b_dib_12 (dib_int[12], DIB[12]); + buf b_dib_13 (dib_int[13], DIB[13]); + buf b_dib_14 (dib_int[14], DIB[14]); + buf b_dib_15 (dib_int[15], DIB[15]); + buf b_dib_16 (dib_int[16], DIB[16]); + buf b_dib_17 (dib_int[17], DIB[17]); + buf b_dib_18 (dib_int[18], DIB[18]); + buf b_dib_19 (dib_int[19], DIB[19]); + buf b_dib_20 (dib_int[20], DIB[20]); + buf b_dib_21 (dib_int[21], DIB[21]); + buf b_dib_22 (dib_int[22], DIB[22]); + buf b_dib_23 (dib_int[23], DIB[23]); + buf b_dib_24 (dib_int[24], DIB[24]); + buf b_dib_25 (dib_int[25], DIB[25]); + buf b_dib_26 (dib_int[26], DIB[26]); + buf b_dib_27 (dib_int[27], DIB[27]); + buf b_dib_28 (dib_int[28], DIB[28]); + buf b_dib_29 (dib_int[29], DIB[29]); + buf b_dib_30 (dib_int[30], DIB[30]); + buf b_dib_31 (dib_int[31], DIB[31]); + buf b_dipb_0 (dipb_int[0], DIPB[0]); + buf b_dipb_1 (dipb_int[1], DIPB[1]); + buf b_dipb_2 (dipb_int[2], DIPB[2]); + buf b_dipb_3 (dipb_int[3], DIPB[3]); + buf b_enb (enb_int, ENB); + buf b_clkb (clkb_int, CLKB); + buf b_ssrb (ssrb_int, SSRB); + buf b_web (web_int, WEB); + + initial begin + for (count = 0; count < 256; count = count + 1) begin + mem[count] <= INIT_00[count]; + mem[256 * 1 + count] <= INIT_01[count]; + mem[256 * 2 + count] <= INIT_02[count]; + mem[256 * 3 + count] <= INIT_03[count]; + mem[256 * 4 + count] <= INIT_04[count]; + mem[256 * 5 + count] <= INIT_05[count]; + mem[256 * 6 + count] <= INIT_06[count]; + mem[256 * 7 + count] <= INIT_07[count]; + mem[256 * 8 + count] <= INIT_08[count]; + mem[256 * 9 + count] <= INIT_09[count]; + mem[256 * 10 + count] <= INIT_0A[count]; + mem[256 * 11 + count] <= INIT_0B[count]; + mem[256 * 12 + count] <= INIT_0C[count]; + mem[256 * 13 + count] <= INIT_0D[count]; + mem[256 * 14 + count] <= INIT_0E[count]; + mem[256 * 15 + count] <= INIT_0F[count]; + mem[256 * 16 + count] <= INIT_10[count]; + mem[256 * 17 + count] <= INIT_11[count]; + mem[256 * 18 + count] <= INIT_12[count]; + mem[256 * 19 + count] <= INIT_13[count]; + mem[256 * 20 + count] <= INIT_14[count]; + mem[256 * 21 + count] <= INIT_15[count]; + mem[256 * 22 + count] <= INIT_16[count]; + mem[256 * 23 + count] <= INIT_17[count]; + mem[256 * 24 + count] <= INIT_18[count]; + mem[256 * 25 + count] <= INIT_19[count]; + mem[256 * 26 + count] <= INIT_1A[count]; + mem[256 * 27 + count] <= INIT_1B[count]; + mem[256 * 28 + count] <= INIT_1C[count]; + mem[256 * 29 + count] <= INIT_1D[count]; + mem[256 * 30 + count] <= INIT_1E[count]; + mem[256 * 31 + count] <= INIT_1F[count]; + mem[256 * 32 + count] <= INIT_20[count]; + mem[256 * 33 + count] <= INIT_21[count]; + mem[256 * 34 + count] <= INIT_22[count]; + mem[256 * 35 + count] <= INIT_23[count]; + mem[256 * 36 + count] <= INIT_24[count]; + mem[256 * 37 + count] <= INIT_25[count]; + mem[256 * 38 + count] <= INIT_26[count]; + mem[256 * 39 + count] <= INIT_27[count]; + mem[256 * 40 + count] <= INIT_28[count]; + mem[256 * 41 + count] <= INIT_29[count]; + mem[256 * 42 + count] <= INIT_2A[count]; + mem[256 * 43 + count] <= INIT_2B[count]; + mem[256 * 44 + count] <= INIT_2C[count]; + mem[256 * 45 + count] <= INIT_2D[count]; + mem[256 * 46 + count] <= INIT_2E[count]; + mem[256 * 47 + count] <= INIT_2F[count]; + mem[256 * 48 + count] <= INIT_30[count]; + mem[256 * 49 + count] <= INIT_31[count]; + mem[256 * 50 + count] <= INIT_32[count]; + mem[256 * 51 + count] <= INIT_33[count]; + mem[256 * 52 + count] <= INIT_34[count]; + mem[256 * 53 + count] <= INIT_35[count]; + mem[256 * 54 + count] <= INIT_36[count]; + mem[256 * 55 + count] <= INIT_37[count]; + mem[256 * 56 + count] <= INIT_38[count]; + mem[256 * 57 + count] <= INIT_39[count]; + mem[256 * 58 + count] <= INIT_3A[count]; + mem[256 * 59 + count] <= INIT_3B[count]; + mem[256 * 60 + count] <= INIT_3C[count]; + mem[256 * 61 + count] <= INIT_3D[count]; + mem[256 * 62 + count] <= INIT_3E[count]; + mem[256 * 63 + count] <= INIT_3F[count]; + mem[256 * 64 + count] <= INITP_00[count]; + mem[256 * 65 + count] <= INITP_01[count]; + mem[256 * 66 + count] <= INITP_02[count]; + mem[256 * 67 + count] <= INITP_03[count]; + mem[256 * 68 + count] <= INITP_04[count]; + mem[256 * 69 + count] <= INITP_05[count]; + mem[256 * 70 + count] <= INITP_06[count]; + mem[256 * 71 + count] <= INITP_07[count]; + end + address_collision <= 0; + address_collision_a_b <= 0; + address_collision_b_a <= 0; + change_clka <= 0; + change_clkb <= 0; + data_collision <= 0; + data_collision_a_b <= 0; + data_collision_b_a <= 0; + memory_collision <= 0; + memory_collision_a_b <= 0; + memory_collision_b_a <= 0; + setup_all_a_b <= 0; + setup_all_b_a <= 0; + setup_zero <= 0; + setup_rf_a_b <= 0; + setup_rf_b_a <= 0; + end + + assign data_addra_int = addra_int * 2; + assign data_addra_reg = addra_reg * 2; + assign data_addrb_int = addrb_int * 32; + assign data_addrb_reg = addrb_reg * 32; + assign parity_addrb_int = 16384 + addrb_int * 4; + assign parity_addrb_reg = 16384 + addrb_reg * 4; + + + initial begin + + display_flag = 1; + + case (SIM_COLLISION_CHECK) + + "NONE" : begin + assign setup_all_a_b = 1'b0; + assign setup_all_b_a = 1'b0; + assign setup_zero = 1'b0; + assign setup_rf_a_b = 1'b0; + assign setup_rf_b_a = 1'b0; + assign display_flag = 0; + end + "WARNING_ONLY" : begin + assign data_collision = 2'b00; + assign data_collision_a_b = 2'b00; + assign data_collision_b_a = 2'b00; + assign memory_collision = 1'b0; + assign memory_collision_a_b = 1'b0; + assign memory_collision_b_a = 1'b0; + end + "GENERATE_X_ONLY" : begin + assign display_flag = 0; + end + "ALL" : ; + default : begin + $display("Attribute Syntax Error : The Attribute SIM_COLLISION_CHECK on RAMB16_S2_S36 instance %m is set to %s. Legal values for this attribute are ALL, NONE, WARNING_ONLY or GENERATE_X_ONLY.", SIM_COLLISION_CHECK); + $finish; + end + + endcase // case(SIM_COLLISION_CHECK) + + end // initial begin + + + always @(posedge clka_int) begin + time_clka = $time; + #0 time_clkb_clka = time_clka - time_clkb; + change_clka = ~change_clka; + end + + always @(posedge clkb_int) begin + time_clkb = $time; + #0 time_clka_clkb = time_clkb - time_clka; + change_clkb = ~change_clkb; + end + + always @(change_clkb) begin + if ((0 < time_clka_clkb) && (time_clka_clkb < SETUP_ALL)) + setup_all_a_b = 1; + if ((0 < time_clka_clkb) && (time_clka_clkb < SETUP_READ_FIRST)) + setup_rf_a_b = 1; + end + + always @(change_clka) begin + if ((0 < time_clkb_clka) && (time_clkb_clka < SETUP_ALL)) + setup_all_b_a = 1; + if ((0 < time_clkb_clka) && (time_clkb_clka < SETUP_READ_FIRST)) + setup_rf_b_a = 1; + end + + always @(change_clkb or change_clka) begin + if ((time_clkb_clka == 0) && (time_clka_clkb == 0)) + setup_zero = 1; + end + + always @(posedge setup_zero) begin + if ((ena_int == 1) && (wea_int == 1) && + (enb_int == 1) && (web_int == 1) && + (data_addra_int[14:5] == data_addrb_int[14:5])) + memory_collision <= 1; + end + + always @(posedge setup_all_a_b or posedge setup_rf_a_b) begin + if ((ena_reg == 1) && (wea_reg == 1) && + (enb_int == 1) && (web_int == 1) && + (data_addra_reg[14:5] == data_addrb_int[14:5])) + memory_collision_a_b <= 1; + end + + always @(posedge setup_all_b_a or posedge setup_rf_b_a) begin + if ((ena_int == 1) && (wea_int == 1) && + (enb_reg == 1) && (web_reg == 1) && + (data_addra_int[14:5] == data_addrb_reg[14:5])) + memory_collision_b_a <= 1; + end + + always @(posedge setup_all_a_b) begin + if (data_addra_reg[14:5] == data_addrb_int[14:5]) begin + if ((ena_reg == 1) && (enb_int == 1)) begin + case ({wr_mode_a, wr_mode_b, wea_reg, web_int}) + 6'b000011 : begin data_collision_a_b <= 2'b11; display_wa_wb; end + 6'b000111 : begin data_collision_a_b <= 2'b11; display_wa_wb; end + 6'b001011 : begin data_collision_a_b <= 2'b10; display_wa_wb; end +// 6'b010011 : begin data_collision_a_b <= 2'b00; display_wa_wb; end +// 6'b010111 : begin data_collision_a_b <= 2'b00; display_wa_wb; end +// 6'b011011 : begin data_collision_a_b <= 2'b00; display_wa_wb; end + 6'b100011 : begin data_collision_a_b <= 2'b01; display_wa_wb; end + 6'b100111 : begin data_collision_a_b <= 2'b01; display_wa_wb; end + 6'b101011 : begin display_wa_wb; end + 6'b000001 : begin data_collision_a_b <= 2'b10; display_ra_wb; end +// 6'b000101 : begin data_collision_a_b <= 2'b00; display_ra_wb; end + 6'b001001 : begin data_collision_a_b <= 2'b10; display_ra_wb; end + 6'b010001 : begin data_collision_a_b <= 2'b10; display_ra_wb; end +// 6'b010101 : begin data_collision_a_b <= 2'b00; display_ra_wb; end + 6'b011001 : begin data_collision_a_b <= 2'b10; display_ra_wb; end + 6'b100001 : begin data_collision_a_b <= 2'b10; display_ra_wb; end +// 6'b100101 : begin data_collision_a_b <= 2'b00; display_ra_wb; end + 6'b101001 : begin data_collision_a_b <= 2'b10; display_ra_wb; end + 6'b000010 : begin data_collision_a_b <= 2'b01; display_wa_rb; end + 6'b000110 : begin data_collision_a_b <= 2'b01; display_wa_rb; end + 6'b001010 : begin data_collision_a_b <= 2'b01; display_wa_rb; end +// 6'b010010 : begin data_collision_a_b <= 2'b00; display_wa_rb; end +// 6'b010110 : begin data_collision_a_b <= 2'b00; display_wa_rb; end +// 6'b011010 : begin data_collision_a_b <= 2'b00; display_wa_rb; end + 6'b100010 : begin data_collision_a_b <= 2'b01; display_wa_rb; end + 6'b100110 : begin data_collision_a_b <= 2'b01; display_wa_rb; end + 6'b101010 : begin data_collision_a_b <= 2'b01; display_wa_rb; end + endcase + end + end + setup_all_a_b <= 0; + end + + + always @(posedge setup_all_b_a) begin + if (data_addra_int[14:5] == data_addrb_reg[14:5]) begin + if ((ena_int == 1) && (enb_reg == 1)) begin + case ({wr_mode_a, wr_mode_b, wea_int, web_reg}) + 6'b000011 : begin data_collision_b_a <= 2'b11; display_wa_wb; end +// 6'b000111 : begin data_collision_b_a <= 2'b00; display_wa_wb; end + 6'b001011 : begin data_collision_b_a <= 2'b10; display_wa_wb; end + 6'b010011 : begin data_collision_b_a <= 2'b11; display_wa_wb; end +// 6'b010111 : begin data_collision_b_a <= 2'b00; display_wa_wb; end + 6'b011011 : begin data_collision_b_a <= 2'b10; display_wa_wb; end + 6'b100011 : begin data_collision_b_a <= 2'b01; display_wa_wb; end + 6'b100111 : begin data_collision_b_a <= 2'b01; display_wa_wb; end + 6'b101011 : begin display_wa_wb; end + 6'b000001 : begin data_collision_b_a <= 2'b10; display_ra_wb; end + 6'b000101 : begin data_collision_b_a <= 2'b10; display_ra_wb; end + 6'b001001 : begin data_collision_b_a <= 2'b10; display_ra_wb; end + 6'b010001 : begin data_collision_b_a <= 2'b10; display_ra_wb; end + 6'b010101 : begin data_collision_b_a <= 2'b10; display_ra_wb; end + 6'b011001 : begin data_collision_b_a <= 2'b10; display_ra_wb; end + 6'b100001 : begin data_collision_b_a <= 2'b10; display_ra_wb; end + 6'b100101 : begin data_collision_b_a <= 2'b10; display_ra_wb; end + 6'b101001 : begin data_collision_b_a <= 2'b10; display_ra_wb; end + 6'b000010 : begin data_collision_b_a <= 2'b01; display_wa_rb; end + 6'b000110 : begin data_collision_b_a <= 2'b01; display_wa_rb; end + 6'b001010 : begin data_collision_b_a <= 2'b01; display_wa_rb; end +// 6'b010010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end +// 6'b010110 : begin data_collision_b_a <= 2'b00; display_wa_rb; end +// 6'b011010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end + 6'b100010 : begin data_collision_b_a <= 2'b01; display_wa_rb; end + 6'b100110 : begin data_collision_b_a <= 2'b01; display_wa_rb; end + 6'b101010 : begin data_collision_b_a <= 2'b01; display_wa_rb; end + endcase + end + end + setup_all_b_a <= 0; + end + + + always @(posedge setup_zero) begin + if (data_addra_int[14:5] == data_addrb_int[14:5]) begin + if ((ena_int == 1) && (enb_int == 1)) begin + case ({wr_mode_a, wr_mode_b, wea_int, web_int}) + 6'b000011 : begin data_collision <= 2'b11; display_wa_wb; end + 6'b000111 : begin data_collision <= 2'b11; display_wa_wb; end + 6'b001011 : begin data_collision <= 2'b10; display_wa_wb; end + 6'b010011 : begin data_collision <= 2'b11; display_wa_wb; end + 6'b010111 : begin data_collision <= 2'b11; display_wa_wb; end + 6'b011011 : begin data_collision <= 2'b10; display_wa_wb; end + 6'b100011 : begin data_collision <= 2'b01; display_wa_wb; end + 6'b100111 : begin data_collision <= 2'b01; display_wa_wb; end + 6'b101011 : begin display_wa_wb; end + 6'b000001 : begin data_collision <= 2'b10; display_ra_wb; end +// 6'b000101 : begin data_collision <= 2'b00; display_ra_wb; end + 6'b001001 : begin data_collision <= 2'b10; display_ra_wb; end + 6'b010001 : begin data_collision <= 2'b10; display_ra_wb; end +// 6'b010101 : begin data_collision <= 2'b00; display_ra_wb; end + 6'b011001 : begin data_collision <= 2'b10; display_ra_wb; end + 6'b100001 : begin data_collision <= 2'b10; display_ra_wb; end +// 6'b100101 : begin data_collision <= 2'b00; display_ra_wb; end + 6'b101001 : begin data_collision <= 2'b10; display_ra_wb; end + 6'b000010 : begin data_collision <= 2'b01; display_wa_rb; end + 6'b000110 : begin data_collision <= 2'b01; display_wa_rb; end + 6'b001010 : begin data_collision <= 2'b01; display_wa_rb; end +// 6'b010010 : begin data_collision <= 2'b00; display_wa_rb; end +// 6'b010110 : begin data_collision <= 2'b00; display_wa_rb; end +// 6'b011010 : begin data_collision <= 2'b00; display_wa_rb; end + 6'b100010 : begin data_collision <= 2'b01; display_wa_rb; end + 6'b100110 : begin data_collision <= 2'b01; display_wa_rb; end + 6'b101010 : begin data_collision <= 2'b01; display_wa_rb; end + endcase + end + end + setup_zero <= 0; + end + + task display_ra_wb; + begin + if (display_flag) + $display("Memory Collision Error on RAMB16_S2_S36:%m at simulation time %.3f ns\nA read was performed on address %h (hex) of Port A while a write was requested to the same address on Port B. The write will be successful however the read value on Port A is unknown until the next CLKA cycle.", $time/1000.0, addra_int); + end + endtask + + task display_wa_rb; + begin + if (display_flag) + $display("Memory Collision Error on RAMB16_S2_S36:%m at simulation time %.3f ns\nA read was performed on address %h (hex) of Port B while a write was requested to the same address on Port A. The write will be successful however the read value on Port B is unknown until the next CLKB cycle.", $time/1000.0, addrb_int); + end + endtask + + task display_wa_wb; + begin + if (display_flag) + $display("Memory Collision Error on RAMB16_S2_S36:%m at simulation time %.3f ns\nA write was requested to the same address simultaneously at both Port A and Port B of the RAM. The contents written to the RAM at address location %h (hex) of Port A and address location %h (hex) of Port B are unknown.", $time/1000.0, addra_int, addrb_int); + end + endtask + + + always @(posedge setup_rf_a_b) begin + if (data_addra_reg[14:5] == data_addrb_int[14:5]) begin + if ((ena_reg == 1) && (enb_int == 1)) begin + case ({wr_mode_a, wr_mode_b, wea_reg, web_int}) +// 6'b000011 : begin data_collision_a_b <= 2'b00; display_wa_wb; end +// 6'b000111 : begin data_collision_a_b <= 2'b00; display_wa_wb; end +// 6'b001011 : begin data_collision_a_b <= 2'b00; display_wa_wb; end + 6'b010011 : begin data_collision_a_b <= 2'b11; display_wa_wb; end + 6'b010111 : begin data_collision_a_b <= 2'b11; display_wa_wb; end + 6'b011011 : begin data_collision_a_b <= 2'b10; display_wa_wb; end +// 6'b100011 : begin data_collision_a_b <= 2'b00; display_wa_wb; end +// 6'b100111 : begin data_collision_a_b <= 2'b00; display_wa_wb; end +// 6'b101011 : begin data_collision_a_b <= 2'b00; display_wa_wb; end +// 6'b000001 : begin data_collision_a_b <= 2'b00; display_ra_wb; end +// 6'b000101 : begin data_collision_a_b <= 2'b00; display_ra_wb; end +// 6'b001001 : begin data_collision_a_b <= 2'b00; display_ra_wb; end +// 6'b010001 : begin data_collision_a_b <= 2'b00; display_ra_wb; end +// 6'b010101 : begin data_collision_a_b <= 2'b00; display_ra_wb; end +// 6'b011001 : begin data_collision_a_b <= 2'b00; display_ra_wb; end +// 6'b100001 : begin data_collision_a_b <= 2'b00; display_ra_wb; end +// 6'b100101 : begin data_collision_a_b <= 2'b00; display_ra_wb; end +// 6'b101001 : begin data_collision_a_b <= 2'b00; display_ra_wb; end +// 6'b000010 : begin data_collision_a_b <= 2'b00; display_wa_rb; end +// 6'b000110 : begin data_collision_a_b <= 2'b00; display_wa_rb; end +// 6'b001010 : begin data_collision_a_b <= 2'b00; display_wa_rb; end + 6'b010010 : begin data_collision_a_b <= 2'b01; display_wa_rb; end + 6'b010110 : begin data_collision_a_b <= 2'b01; display_wa_rb; end + 6'b011010 : begin data_collision_a_b <= 2'b01; display_wa_rb; end +// 6'b100010 : begin data_collision_a_b <= 2'b00; display_wa_rb; end +// 6'b100110 : begin data_collision_a_b <= 2'b00; display_wa_rb; end +// 6'b101010 : begin data_collision_a_b <= 2'b00; display_wa_rb; end + endcase + end + end + setup_rf_a_b <= 0; + end + + + always @(posedge setup_rf_b_a) begin + if (data_addra_int[14:5] == data_addrb_reg[14:5]) begin + if ((ena_int == 1) && (enb_reg == 1)) begin + case ({wr_mode_a, wr_mode_b, wea_int, web_reg}) +// 6'b000011 : begin data_collision_b_a <= 2'b00; display_wa_wb; end + 6'b000111 : begin data_collision_b_a <= 2'b11; display_wa_wb; end +// 6'b001011 : begin data_collision_b_a <= 2'b00; display_wa_wb; end +// 6'b010011 : begin data_collision_b_a <= 2'b00; display_wa_wb; end + 6'b010111 : begin data_collision_b_a <= 2'b11; display_wa_wb; end +// 6'b011011 : begin data_collision_b_a <= 2'b00; display_wa_wb; end +// 6'b100011 : begin data_collision_b_a <= 2'b00; display_wa_wb; end + 6'b100111 : begin data_collision_b_a <= 2'b01; display_wa_wb; end +// 6'b101011 : begin data_collision_b_a <= 2'b00; display_wa_wb; end +// 6'b000001 : begin data_collision_b_a <= 2'b00; display_ra_wb; end + 6'b000101 : begin data_collision_b_a <= 2'b10; display_ra_wb; end +// 6'b001001 : begin data_collision_b_a <= 2'b00; display_ra_wb; end +// 6'b010001 : begin data_collision_b_a <= 2'b00; display_ra_wb; end + 6'b010101 : begin data_collision_b_a <= 2'b10; display_ra_wb; end +// 6'b011001 : begin data_collision_b_a <= 2'b00; display_ra_wb; end +// 6'b100001 : begin data_collision_b_a <= 2'b00; display_ra_wb; end + 6'b100101 : begin data_collision_b_a <= 2'b10; display_ra_wb; end +// 6'b101001 : begin data_collision_b_a <= 2'b00; display_ra_wb; end +// 6'b000010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end +// 6'b000110 : begin data_collision_b_a <= 2'b00; display_wa_rb; end +// 6'b001010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end +// 6'b010010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end +// 6'b010110 : begin data_collision_b_a <= 2'b00; display_wa_rb; end +// 6'b011010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end +// 6'b100010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end +// 6'b100110 : begin data_collision_b_a <= 2'b00; display_wa_rb; end +// 6'b101010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end + endcase + end + end + setup_rf_b_a <= 0; + end + + + always @(posedge clka_int) begin + addra_reg <= addra_int; + ena_reg <= ena_int; + ssra_reg <= ssra_int; + wea_reg <= wea_int; + end + + always @(posedge clkb_int) begin + addrb_reg <= addrb_int; + enb_reg <= enb_int; + ssrb_reg <= ssrb_int; + web_reg <= web_int; + end + + // Data + always @(posedge memory_collision) begin + for (dmi = 0; dmi < 2; dmi = dmi + 1) begin + mem[data_addra_int + dmi] <= 1'bX; + end + memory_collision <= 0; + end + + always @(posedge memory_collision_a_b) begin + for (dmi = 0; dmi < 2; dmi = dmi + 1) begin + mem[data_addra_reg + dmi] <= 1'bX; + end + memory_collision_a_b <= 0; + end + + always @(posedge memory_collision_b_a) begin + for (dmi = 0; dmi < 2; dmi = dmi + 1) begin + mem[data_addra_int + dmi] <= 1'bX; + end + memory_collision_b_a <= 0; + end + + always @(posedge data_collision[1]) begin + if (ssra_int == 0) begin + doa_out <= 2'bX; + end + data_collision[1] <= 0; + end + + always @(posedge data_collision[0]) begin + if (ssrb_int == 0) begin + for (dbi = 0; dbi < 2; dbi = dbi + 1) begin + dob_out[data_addra_int[4 : 0] + dbi] <= 1'bX; + end + end + data_collision[0] <= 0; + end + + always @(posedge data_collision_a_b[1]) begin + if (ssra_reg == 0) begin + doa_out <= 2'bX; + end + data_collision_a_b[1] <= 0; + end + + always @(posedge data_collision_a_b[0]) begin + if (ssrb_int == 0) begin + for (dbi = 0; dbi < 2; dbi = dbi + 1) begin + dob_out[data_addra_reg[4 : 0] + dbi] <= 1'bX; + end + end + data_collision_a_b[0] <= 0; + end + + always @(posedge data_collision_b_a[1]) begin + if (ssra_int == 0) begin + doa_out <= 2'bX; + end + data_collision_b_a[1] <= 0; + end + + always @(posedge data_collision_b_a[0]) begin + if (ssrb_reg == 0) begin + for (dbi = 0; dbi < 2; dbi = dbi + 1) begin + dob_out[data_addra_int[4 : 0] + dbi] <= 1'bX; + end + end + data_collision_b_a[0] <= 0; + end + + + initial begin + case (WRITE_MODE_A) + "WRITE_FIRST" : wr_mode_a <= 2'b00; + "READ_FIRST" : wr_mode_a <= 2'b01; + "NO_CHANGE" : wr_mode_a <= 2'b10; + default : begin + $display("Attribute Syntax Error : The Attribute WRITE_MODE_A on RAMB16_S2_S36 instance %m is set to %s. Legal values for this attribute are WRITE_FIRST, READ_FIRST or NO_CHANGE.", WRITE_MODE_A); + $finish; + end + endcase + end + + initial begin + case (WRITE_MODE_B) + "WRITE_FIRST" : wr_mode_b <= 2'b00; + "READ_FIRST" : wr_mode_b <= 2'b01; + "NO_CHANGE" : wr_mode_b <= 2'b10; + default : begin + $display("Attribute Syntax Error : The Attribute WRITE_MODE_B on RAMB16_S2_S36 instance %m is set to %s. Legal values for this attribute are WRITE_FIRST, READ_FIRST or NO_CHANGE.", WRITE_MODE_B); + $finish; + end + endcase + end + + // Port A + always @(posedge clka_int) begin + if (ena_int == 1'b1) begin + if (ssra_int == 1'b1) begin + doa_out[0] <= SRVAL_A[0]; + doa_out[1] <= SRVAL_A[1]; + end + else begin + if (wea_int == 1'b1) begin + if (wr_mode_a == 2'b00) begin + doa_out <= dia_int; + end + else if (wr_mode_a == 2'b01) begin + doa_out[0] <= mem[data_addra_int + 0]; + doa_out[1] <= mem[data_addra_int + 1]; + end + end + else begin + doa_out[0] <= mem[data_addra_int + 0]; + doa_out[1] <= mem[data_addra_int + 1]; + end + end + end + end + + always @(posedge clka_int) begin + if (ena_int == 1'b1 && wea_int == 1'b1) begin + mem[data_addra_int + 0] <= dia_int[0]; + mem[data_addra_int + 1] <= dia_int[1]; + end + end + + // Port B + always @(posedge clkb_int) begin + if (enb_int == 1'b1) begin + if (ssrb_int == 1'b1) begin + dob_out[0] <= SRVAL_B[0]; + dob_out[1] <= SRVAL_B[1]; + dob_out[2] <= SRVAL_B[2]; + dob_out[3] <= SRVAL_B[3]; + dob_out[4] <= SRVAL_B[4]; + dob_out[5] <= SRVAL_B[5]; + dob_out[6] <= SRVAL_B[6]; + dob_out[7] <= SRVAL_B[7]; + dob_out[8] <= SRVAL_B[8]; + dob_out[9] <= SRVAL_B[9]; + dob_out[10] <= SRVAL_B[10]; + dob_out[11] <= SRVAL_B[11]; + dob_out[12] <= SRVAL_B[12]; + dob_out[13] <= SRVAL_B[13]; + dob_out[14] <= SRVAL_B[14]; + dob_out[15] <= SRVAL_B[15]; + dob_out[16] <= SRVAL_B[16]; + dob_out[17] <= SRVAL_B[17]; + dob_out[18] <= SRVAL_B[18]; + dob_out[19] <= SRVAL_B[19]; + dob_out[20] <= SRVAL_B[20]; + dob_out[21] <= SRVAL_B[21]; + dob_out[22] <= SRVAL_B[22]; + dob_out[23] <= SRVAL_B[23]; + dob_out[24] <= SRVAL_B[24]; + dob_out[25] <= SRVAL_B[25]; + dob_out[26] <= SRVAL_B[26]; + dob_out[27] <= SRVAL_B[27]; + dob_out[28] <= SRVAL_B[28]; + dob_out[29] <= SRVAL_B[29]; + dob_out[30] <= SRVAL_B[30]; + dob_out[31] <= SRVAL_B[31]; + dopb_out[0] <= SRVAL_B[32]; + dopb_out[1] <= SRVAL_B[33]; + dopb_out[2] <= SRVAL_B[34]; + dopb_out[3] <= SRVAL_B[35]; + end + else begin + if (web_int == 1'b1) begin + if (wr_mode_b == 2'b00) begin + dob_out <= dib_int; + dopb_out <= dipb_int; + end + else if (wr_mode_b == 2'b01) begin + dob_out[0] <= mem[data_addrb_int + 0]; + dob_out[1] <= mem[data_addrb_int + 1]; + dob_out[2] <= mem[data_addrb_int + 2]; + dob_out[3] <= mem[data_addrb_int + 3]; + dob_out[4] <= mem[data_addrb_int + 4]; + dob_out[5] <= mem[data_addrb_int + 5]; + dob_out[6] <= mem[data_addrb_int + 6]; + dob_out[7] <= mem[data_addrb_int + 7]; + dob_out[8] <= mem[data_addrb_int + 8]; + dob_out[9] <= mem[data_addrb_int + 9]; + dob_out[10] <= mem[data_addrb_int + 10]; + dob_out[11] <= mem[data_addrb_int + 11]; + dob_out[12] <= mem[data_addrb_int + 12]; + dob_out[13] <= mem[data_addrb_int + 13]; + dob_out[14] <= mem[data_addrb_int + 14]; + dob_out[15] <= mem[data_addrb_int + 15]; + dob_out[16] <= mem[data_addrb_int + 16]; + dob_out[17] <= mem[data_addrb_int + 17]; + dob_out[18] <= mem[data_addrb_int + 18]; + dob_out[19] <= mem[data_addrb_int + 19]; + dob_out[20] <= mem[data_addrb_int + 20]; + dob_out[21] <= mem[data_addrb_int + 21]; + dob_out[22] <= mem[data_addrb_int + 22]; + dob_out[23] <= mem[data_addrb_int + 23]; + dob_out[24] <= mem[data_addrb_int + 24]; + dob_out[25] <= mem[data_addrb_int + 25]; + dob_out[26] <= mem[data_addrb_int + 26]; + dob_out[27] <= mem[data_addrb_int + 27]; + dob_out[28] <= mem[data_addrb_int + 28]; + dob_out[29] <= mem[data_addrb_int + 29]; + dob_out[30] <= mem[data_addrb_int + 30]; + dob_out[31] <= mem[data_addrb_int + 31]; + dopb_out[0] <= mem[parity_addrb_int + 0]; + dopb_out[1] <= mem[parity_addrb_int + 1]; + dopb_out[2] <= mem[parity_addrb_int + 2]; + dopb_out[3] <= mem[parity_addrb_int + 3]; + end + end + else begin + dob_out[0] <= mem[data_addrb_int + 0]; + dob_out[1] <= mem[data_addrb_int + 1]; + dob_out[2] <= mem[data_addrb_int + 2]; + dob_out[3] <= mem[data_addrb_int + 3]; + dob_out[4] <= mem[data_addrb_int + 4]; + dob_out[5] <= mem[data_addrb_int + 5]; + dob_out[6] <= mem[data_addrb_int + 6]; + dob_out[7] <= mem[data_addrb_int + 7]; + dob_out[8] <= mem[data_addrb_int + 8]; + dob_out[9] <= mem[data_addrb_int + 9]; + dob_out[10] <= mem[data_addrb_int + 10]; + dob_out[11] <= mem[data_addrb_int + 11]; + dob_out[12] <= mem[data_addrb_int + 12]; + dob_out[13] <= mem[data_addrb_int + 13]; + dob_out[14] <= mem[data_addrb_int + 14]; + dob_out[15] <= mem[data_addrb_int + 15]; + dob_out[16] <= mem[data_addrb_int + 16]; + dob_out[17] <= mem[data_addrb_int + 17]; + dob_out[18] <= mem[data_addrb_int + 18]; + dob_out[19] <= mem[data_addrb_int + 19]; + dob_out[20] <= mem[data_addrb_int + 20]; + dob_out[21] <= mem[data_addrb_int + 21]; + dob_out[22] <= mem[data_addrb_int + 22]; + dob_out[23] <= mem[data_addrb_int + 23]; + dob_out[24] <= mem[data_addrb_int + 24]; + dob_out[25] <= mem[data_addrb_int + 25]; + dob_out[26] <= mem[data_addrb_int + 26]; + dob_out[27] <= mem[data_addrb_int + 27]; + dob_out[28] <= mem[data_addrb_int + 28]; + dob_out[29] <= mem[data_addrb_int + 29]; + dob_out[30] <= mem[data_addrb_int + 30]; + dob_out[31] <= mem[data_addrb_int + 31]; + dopb_out[0] <= mem[parity_addrb_int + 0]; + dopb_out[1] <= mem[parity_addrb_int + 1]; + dopb_out[2] <= mem[parity_addrb_int + 2]; + dopb_out[3] <= mem[parity_addrb_int + 3]; + end + end + end + end + + always @(posedge clkb_int) begin + if (enb_int == 1'b1 && web_int == 1'b1) begin + mem[data_addrb_int + 0] <= dib_int[0]; + mem[data_addrb_int + 1] <= dib_int[1]; + mem[data_addrb_int + 2] <= dib_int[2]; + mem[data_addrb_int + 3] <= dib_int[3]; + mem[data_addrb_int + 4] <= dib_int[4]; + mem[data_addrb_int + 5] <= dib_int[5]; + mem[data_addrb_int + 6] <= dib_int[6]; + mem[data_addrb_int + 7] <= dib_int[7]; + mem[data_addrb_int + 8] <= dib_int[8]; + mem[data_addrb_int + 9] <= dib_int[9]; + mem[data_addrb_int + 10] <= dib_int[10]; + mem[data_addrb_int + 11] <= dib_int[11]; + mem[data_addrb_int + 12] <= dib_int[12]; + mem[data_addrb_int + 13] <= dib_int[13]; + mem[data_addrb_int + 14] <= dib_int[14]; + mem[data_addrb_int + 15] <= dib_int[15]; + mem[data_addrb_int + 16] <= dib_int[16]; + mem[data_addrb_int + 17] <= dib_int[17]; + mem[data_addrb_int + 18] <= dib_int[18]; + mem[data_addrb_int + 19] <= dib_int[19]; + mem[data_addrb_int + 20] <= dib_int[20]; + mem[data_addrb_int + 21] <= dib_int[21]; + mem[data_addrb_int + 22] <= dib_int[22]; + mem[data_addrb_int + 23] <= dib_int[23]; + mem[data_addrb_int + 24] <= dib_int[24]; + mem[data_addrb_int + 25] <= dib_int[25]; + mem[data_addrb_int + 26] <= dib_int[26]; + mem[data_addrb_int + 27] <= dib_int[27]; + mem[data_addrb_int + 28] <= dib_int[28]; + mem[data_addrb_int + 29] <= dib_int[29]; + mem[data_addrb_int + 30] <= dib_int[30]; + mem[data_addrb_int + 31] <= dib_int[31]; + mem[parity_addrb_int + 0] <= dipb_int[0]; + mem[parity_addrb_int + 1] <= dipb_int[1]; + mem[parity_addrb_int + 2] <= dipb_int[2]; + mem[parity_addrb_int + 3] <= dipb_int[3]; + end + end + + specify + (CLKA *> DOA) = (100, 100); + (CLKB *> DOB) = (100, 100); + (CLKB *> DOPB) = (100, 100); + endspecify + +endmodule + +`else + +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/RAMB16_S2_S36.v,v 1.10 2007/02/22 01:58:06 wloo Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2005 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Timing Simulation Library Component +// / / 16K-Bit Data and 2K-Bit Parity Dual Port Block RAM +// /___/ /\ Filename : RAMB16_S2_S36.v +// \ \ / \ Timestamp : Thu Mar 10 16:44:01 PST 2005 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 03/10/05 - Initialized outputs. +// 02/21/07 - Fixed parameter SIM_COLLISION_CHECK (CR 433281). +// End Revision + +`timescale 1 ps/1 ps + +module RAMB16_S2_S36 (DOA, DOB, DOPB, ADDRA, ADDRB, CLKA, CLKB, DIA, DIB, DIPB, ENA, ENB, SSRA, SSRB, WEA, WEB); + + parameter INIT_A = 2'h0; + parameter INIT_B = 36'h0; + parameter SRVAL_A = 2'h0; + parameter SRVAL_B = 36'h0; + parameter WRITE_MODE_A = "WRITE_FIRST"; + parameter WRITE_MODE_B = "WRITE_FIRST"; + parameter SIM_COLLISION_CHECK = "ALL"; + localparam SETUP_ALL = 1000; + localparam SETUP_READ_FIRST = 3000; + + parameter INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + + output [1:0] DOA; + output [31:0] DOB; + output [3:0] DOPB; + + input [12:0] ADDRA; + input [1:0] DIA; + input ENA, CLKA, WEA, SSRA; + input [8:0] ADDRB; + input [31:0] DIB; + input [3:0] DIPB; + input ENB, CLKB, WEB, SSRB; + + reg [1:0] doa_out = INIT_A[1:0]; + reg [31:0] dob_out = INIT_B[31:0]; + reg [3:0] dopb_out = INIT_B[35:32]; + + reg [31:0] mem [511:0]; + reg [3:0] memp [511:0]; + + reg [8:0] count, countp; + reg [1:0] wr_mode_a, wr_mode_b; + + reg [5:0] dmi, dbi; + reg [5:0] pmi, pbi; + + wire [12:0] addra_int; + reg [12:0] addra_reg; + wire [1:0] dia_int; + wire ena_int, clka_int, wea_int, ssra_int; + reg ena_reg, wea_reg, ssra_reg; + wire [8:0] addrb_int; + reg [8:0] addrb_reg; + wire [31:0] dib_int; + wire [3:0] dipb_int; + wire enb_int, clkb_int, web_int, ssrb_int; + reg display_flag, output_flag; + reg enb_reg, web_reg, ssrb_reg; + + time time_clka, time_clkb; + time time_clka_clkb; + time time_clkb_clka; + + reg setup_all_a_b; + reg setup_all_b_a; + reg setup_zero; + reg setup_rf_a_b; + reg setup_rf_b_a; + reg [1:0] data_collision, data_collision_a_b, data_collision_b_a; + reg memory_collision, memory_collision_a_b, memory_collision_b_a; + reg change_clka; + reg change_clkb; + + wire [14:0] data_addra_int; + wire [14:0] data_addra_reg; + wire [14:0] data_addrb_int; + wire [14:0] data_addrb_reg; + + wire dia_enable = ena_int && wea_int; + wire dib_enable = enb_int && web_int; + + tri0 GSR = glbl.GSR; + wire gsr_int; + + buf b_gsr (gsr_int, GSR); + + buf b_doa [1:0] (DOA, doa_out); + buf b_addra [12:0] (addra_int, ADDRA); + buf b_dia [1:0] (dia_int, DIA); + buf b_ena (ena_int, ENA); + buf b_clka (clka_int, CLKA); + buf b_ssra (ssra_int, SSRA); + buf b_wea (wea_int, WEA); + + buf b_dob [31:0] (DOB, dob_out); + buf b_dopb [3:0] (DOPB, dopb_out); + buf b_addrb [8:0] (addrb_int, ADDRB); + buf b_dib [31:0] (dib_int, DIB); + buf b_dipb [3:0] (dipb_int, DIPB); + buf b_enb (enb_int, ENB); + buf b_clkb (clkb_int, CLKB); + buf b_ssrb (ssrb_int, SSRB); + buf b_web (web_int, WEB); + + + always @(gsr_int) + if (gsr_int) begin + assign {doa_out} = INIT_A; + assign {dopb_out, dob_out} = INIT_B; + end + else begin + deassign doa_out; + deassign dob_out; + deassign dopb_out; + end + + + initial begin + + for (count = 0; count < 8; count = count + 1) begin + mem[count] = INIT_00[(count * 32) +: 32]; + mem[8 * 1 + count] = INIT_01[(count * 32) +: 32]; + mem[8 * 2 + count] = INIT_02[(count * 32) +: 32]; + mem[8 * 3 + count] = INIT_03[(count * 32) +: 32]; + mem[8 * 4 + count] = INIT_04[(count * 32) +: 32]; + mem[8 * 5 + count] = INIT_05[(count * 32) +: 32]; + mem[8 * 6 + count] = INIT_06[(count * 32) +: 32]; + mem[8 * 7 + count] = INIT_07[(count * 32) +: 32]; + mem[8 * 8 + count] = INIT_08[(count * 32) +: 32]; + mem[8 * 9 + count] = INIT_09[(count * 32) +: 32]; + mem[8 * 10 + count] = INIT_0A[(count * 32) +: 32]; + mem[8 * 11 + count] = INIT_0B[(count * 32) +: 32]; + mem[8 * 12 + count] = INIT_0C[(count * 32) +: 32]; + mem[8 * 13 + count] = INIT_0D[(count * 32) +: 32]; + mem[8 * 14 + count] = INIT_0E[(count * 32) +: 32]; + mem[8 * 15 + count] = INIT_0F[(count * 32) +: 32]; + mem[8 * 16 + count] = INIT_10[(count * 32) +: 32]; + mem[8 * 17 + count] = INIT_11[(count * 32) +: 32]; + mem[8 * 18 + count] = INIT_12[(count * 32) +: 32]; + mem[8 * 19 + count] = INIT_13[(count * 32) +: 32]; + mem[8 * 20 + count] = INIT_14[(count * 32) +: 32]; + mem[8 * 21 + count] = INIT_15[(count * 32) +: 32]; + mem[8 * 22 + count] = INIT_16[(count * 32) +: 32]; + mem[8 * 23 + count] = INIT_17[(count * 32) +: 32]; + mem[8 * 24 + count] = INIT_18[(count * 32) +: 32]; + mem[8 * 25 + count] = INIT_19[(count * 32) +: 32]; + mem[8 * 26 + count] = INIT_1A[(count * 32) +: 32]; + mem[8 * 27 + count] = INIT_1B[(count * 32) +: 32]; + mem[8 * 28 + count] = INIT_1C[(count * 32) +: 32]; + mem[8 * 29 + count] = INIT_1D[(count * 32) +: 32]; + mem[8 * 30 + count] = INIT_1E[(count * 32) +: 32]; + mem[8 * 31 + count] = INIT_1F[(count * 32) +: 32]; + mem[8 * 32 + count] = INIT_20[(count * 32) +: 32]; + mem[8 * 33 + count] = INIT_21[(count * 32) +: 32]; + mem[8 * 34 + count] = INIT_22[(count * 32) +: 32]; + mem[8 * 35 + count] = INIT_23[(count * 32) +: 32]; + mem[8 * 36 + count] = INIT_24[(count * 32) +: 32]; + mem[8 * 37 + count] = INIT_25[(count * 32) +: 32]; + mem[8 * 38 + count] = INIT_26[(count * 32) +: 32]; + mem[8 * 39 + count] = INIT_27[(count * 32) +: 32]; + mem[8 * 40 + count] = INIT_28[(count * 32) +: 32]; + mem[8 * 41 + count] = INIT_29[(count * 32) +: 32]; + mem[8 * 42 + count] = INIT_2A[(count * 32) +: 32]; + mem[8 * 43 + count] = INIT_2B[(count * 32) +: 32]; + mem[8 * 44 + count] = INIT_2C[(count * 32) +: 32]; + mem[8 * 45 + count] = INIT_2D[(count * 32) +: 32]; + mem[8 * 46 + count] = INIT_2E[(count * 32) +: 32]; + mem[8 * 47 + count] = INIT_2F[(count * 32) +: 32]; + mem[8 * 48 + count] = INIT_30[(count * 32) +: 32]; + mem[8 * 49 + count] = INIT_31[(count * 32) +: 32]; + mem[8 * 50 + count] = INIT_32[(count * 32) +: 32]; + mem[8 * 51 + count] = INIT_33[(count * 32) +: 32]; + mem[8 * 52 + count] = INIT_34[(count * 32) +: 32]; + mem[8 * 53 + count] = INIT_35[(count * 32) +: 32]; + mem[8 * 54 + count] = INIT_36[(count * 32) +: 32]; + mem[8 * 55 + count] = INIT_37[(count * 32) +: 32]; + mem[8 * 56 + count] = INIT_38[(count * 32) +: 32]; + mem[8 * 57 + count] = INIT_39[(count * 32) +: 32]; + mem[8 * 58 + count] = INIT_3A[(count * 32) +: 32]; + mem[8 * 59 + count] = INIT_3B[(count * 32) +: 32]; + mem[8 * 60 + count] = INIT_3C[(count * 32) +: 32]; + mem[8 * 61 + count] = INIT_3D[(count * 32) +: 32]; + mem[8 * 62 + count] = INIT_3E[(count * 32) +: 32]; + mem[8 * 63 + count] = INIT_3F[(count * 32) +: 32]; + end + +// initiate parity start + for (countp = 0; countp < 64; countp = countp + 1) begin + memp[countp] = INITP_00[(countp * 4) +: 4]; + memp[64 * 1 + countp] = INITP_01[(countp * 4) +: 4]; + memp[64 * 2 + countp] = INITP_02[(countp * 4) +: 4]; + memp[64 * 3 + countp] = INITP_03[(countp * 4) +: 4]; + memp[64 * 4 + countp] = INITP_04[(countp * 4) +: 4]; + memp[64 * 5 + countp] = INITP_05[(countp * 4) +: 4]; + memp[64 * 6 + countp] = INITP_06[(countp * 4) +: 4]; + memp[64 * 7 + countp] = INITP_07[(countp * 4) +: 4]; + end +// initiate parity end + + change_clka <= 0; + change_clkb <= 0; + data_collision <= 0; + data_collision_a_b <= 0; + data_collision_b_a <= 0; + memory_collision <= 0; + memory_collision_a_b <= 0; + memory_collision_b_a <= 0; + setup_all_a_b <= 0; + setup_all_b_a <= 0; + setup_zero <= 0; + setup_rf_a_b <= 0; + setup_rf_b_a <= 0; + end + + assign data_addra_int = addra_int * 2; + assign data_addra_reg = addra_reg * 2; + assign data_addrb_int = addrb_int * 32; + assign data_addrb_reg = addrb_reg * 32; + + + initial begin + + display_flag = 1; + output_flag = 1; + + case (SIM_COLLISION_CHECK) + + "NONE" : begin + output_flag = 0; + display_flag = 0; + end + "WARNING_ONLY" : output_flag = 0; + "GENERATE_X_ONLY" : display_flag = 0; + "ALL" : ; + + default : begin + $display("Attribute Syntax Error : The Attribute SIM_COLLISION_CHECK on RAMB16_S2_S36 instance %m is set to %s. Legal values for this attribute are ALL, NONE, WARNING_ONLY or GENERATE_X_ONLY.", SIM_COLLISION_CHECK); + $finish; + end + + endcase // case(SIM_COLLISION_CHECK) + + end // initial begin + + + always @(posedge clka_int) begin + if ((output_flag || display_flag)) begin + time_clka = $time; + #0 time_clkb_clka = time_clka - time_clkb; + change_clka = ~change_clka; + end + end + + always @(posedge clkb_int) begin + if ((output_flag || display_flag)) begin + time_clkb = $time; + #0 time_clka_clkb = time_clkb - time_clka; + change_clkb = ~change_clkb; + end + end + + always @(change_clkb) begin + if ((0 < time_clka_clkb) && (time_clka_clkb < SETUP_ALL)) + setup_all_a_b = 1; + if ((0 < time_clka_clkb) && (time_clka_clkb < SETUP_READ_FIRST)) + setup_rf_a_b = 1; + end + + always @(change_clka) begin + if ((0 < time_clkb_clka) && (time_clkb_clka < SETUP_ALL)) + setup_all_b_a = 1; + if ((0 < time_clkb_clka) && (time_clkb_clka < SETUP_READ_FIRST)) + setup_rf_b_a = 1; + end + + always @(change_clkb or change_clka) begin + if ((time_clkb_clka == 0) && (time_clka_clkb == 0)) + setup_zero = 1; + end + + always @(posedge setup_zero) begin + if ((ena_int == 1) && (wea_int == 1) && + (enb_int == 1) && (web_int == 1) && + (data_addra_int[14:5] == data_addrb_int[14:5])) + memory_collision <= 1; + end + + always @(posedge setup_all_a_b or posedge setup_rf_a_b) begin + if ((ena_reg == 1) && (wea_reg == 1) && + (enb_int == 1) && (web_int == 1) && + (data_addra_reg[14:5] == data_addrb_int[14:5])) + memory_collision_a_b <= 1; + end + + always @(posedge setup_all_b_a or posedge setup_rf_b_a) begin + if ((ena_int == 1) && (wea_int == 1) && + (enb_reg == 1) && (web_reg == 1) && + (data_addra_int[14:5] == data_addrb_reg[14:5])) + memory_collision_b_a <= 1; + end + + always @(posedge setup_all_a_b) begin + if (data_addra_reg[14:5] == data_addrb_int[14:5]) begin + if ((ena_reg == 1) && (enb_int == 1)) begin + case ({wr_mode_a, wr_mode_b, wea_reg, web_int}) + 6'b000011 : begin data_collision_a_b <= 2'b11; display_wa_wb; end + 6'b000111 : begin data_collision_a_b <= 2'b11; display_wa_wb; end + 6'b001011 : begin data_collision_a_b <= 2'b10; display_wa_wb; end +// 6'b010011 : begin data_collision_a_b <= 2'b00; display_wa_wb; end +// 6'b010111 : begin data_collision_a_b <= 2'b00; display_wa_wb; end +// 6'b011011 : begin data_collision_a_b <= 2'b00; display_wa_wb; end + 6'b100011 : begin data_collision_a_b <= 2'b01; display_wa_wb; end + 6'b100111 : begin data_collision_a_b <= 2'b01; display_wa_wb; end + 6'b101011 : begin display_wa_wb; end + 6'b000001 : begin data_collision_a_b <= 2'b10; display_ra_wb; end +// 6'b000101 : begin data_collision_a_b <= 2'b00; display_ra_wb; end + 6'b001001 : begin data_collision_a_b <= 2'b10; display_ra_wb; end + 6'b010001 : begin data_collision_a_b <= 2'b10; display_ra_wb; end +// 6'b010101 : begin data_collision_a_b <= 2'b00; display_ra_wb; end + 6'b011001 : begin data_collision_a_b <= 2'b10; display_ra_wb; end + 6'b100001 : begin data_collision_a_b <= 2'b10; display_ra_wb; end +// 6'b100101 : begin data_collision_a_b <= 2'b00; display_ra_wb; end + 6'b101001 : begin data_collision_a_b <= 2'b10; display_ra_wb; end + 6'b000010 : begin data_collision_a_b <= 2'b01; display_wa_rb; end + 6'b000110 : begin data_collision_a_b <= 2'b01; display_wa_rb; end + 6'b001010 : begin data_collision_a_b <= 2'b01; display_wa_rb; end +// 6'b010010 : begin data_collision_a_b <= 2'b00; display_wa_rb; end +// 6'b010110 : begin data_collision_a_b <= 2'b00; display_wa_rb; end +// 6'b011010 : begin data_collision_a_b <= 2'b00; display_wa_rb; end + 6'b100010 : begin data_collision_a_b <= 2'b01; display_wa_rb; end + 6'b100110 : begin data_collision_a_b <= 2'b01; display_wa_rb; end + 6'b101010 : begin data_collision_a_b <= 2'b01; display_wa_rb; end + endcase + end + end + setup_all_a_b <= 0; + end + + + always @(posedge setup_all_b_a) begin + if (data_addra_int[14:5] == data_addrb_reg[14:5]) begin + if ((ena_int == 1) && (enb_reg == 1)) begin + case ({wr_mode_a, wr_mode_b, wea_int, web_reg}) + 6'b000011 : begin data_collision_b_a <= 2'b11; display_wa_wb; end +// 6'b000111 : begin data_collision_b_a <= 2'b00; display_wa_wb; end + 6'b001011 : begin data_collision_b_a <= 2'b10; display_wa_wb; end + 6'b010011 : begin data_collision_b_a <= 2'b11; display_wa_wb; end +// 6'b010111 : begin data_collision_b_a <= 2'b00; display_wa_wb; end + 6'b011011 : begin data_collision_b_a <= 2'b10; display_wa_wb; end + 6'b100011 : begin data_collision_b_a <= 2'b01; display_wa_wb; end + 6'b100111 : begin data_collision_b_a <= 2'b01; display_wa_wb; end + 6'b101011 : begin display_wa_wb; end + 6'b000001 : begin data_collision_b_a <= 2'b10; display_ra_wb; end + 6'b000101 : begin data_collision_b_a <= 2'b10; display_ra_wb; end + 6'b001001 : begin data_collision_b_a <= 2'b10; display_ra_wb; end + 6'b010001 : begin data_collision_b_a <= 2'b10; display_ra_wb; end + 6'b010101 : begin data_collision_b_a <= 2'b10; display_ra_wb; end + 6'b011001 : begin data_collision_b_a <= 2'b10; display_ra_wb; end + 6'b100001 : begin data_collision_b_a <= 2'b10; display_ra_wb; end + 6'b100101 : begin data_collision_b_a <= 2'b10; display_ra_wb; end + 6'b101001 : begin data_collision_b_a <= 2'b10; display_ra_wb; end + 6'b000010 : begin data_collision_b_a <= 2'b01; display_wa_rb; end + 6'b000110 : begin data_collision_b_a <= 2'b01; display_wa_rb; end + 6'b001010 : begin data_collision_b_a <= 2'b01; display_wa_rb; end +// 6'b010010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end +// 6'b010110 : begin data_collision_b_a <= 2'b00; display_wa_rb; end +// 6'b011010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end + 6'b100010 : begin data_collision_b_a <= 2'b01; display_wa_rb; end + 6'b100110 : begin data_collision_b_a <= 2'b01; display_wa_rb; end + 6'b101010 : begin data_collision_b_a <= 2'b01; display_wa_rb; end + endcase + end + end + setup_all_b_a <= 0; + end + + + always @(posedge setup_zero) begin + if (data_addra_int[14:5] == data_addrb_int[14:5]) begin + if ((ena_int == 1) && (enb_int == 1)) begin + case ({wr_mode_a, wr_mode_b, wea_int, web_int}) + 6'b000011 : begin data_collision <= 2'b11; display_wa_wb; end + 6'b000111 : begin data_collision <= 2'b11; display_wa_wb; end + 6'b001011 : begin data_collision <= 2'b10; display_wa_wb; end + 6'b010011 : begin data_collision <= 2'b11; display_wa_wb; end + 6'b010111 : begin data_collision <= 2'b11; display_wa_wb; end + 6'b011011 : begin data_collision <= 2'b10; display_wa_wb; end + 6'b100011 : begin data_collision <= 2'b01; display_wa_wb; end + 6'b100111 : begin data_collision <= 2'b01; display_wa_wb; end + 6'b101011 : begin display_wa_wb; end + 6'b000001 : begin data_collision <= 2'b10; display_ra_wb; end +// 6'b000101 : begin data_collision <= 2'b00; display_ra_wb; end + 6'b001001 : begin data_collision <= 2'b10; display_ra_wb; end + 6'b010001 : begin data_collision <= 2'b10; display_ra_wb; end +// 6'b010101 : begin data_collision <= 2'b00; display_ra_wb; end + 6'b011001 : begin data_collision <= 2'b10; display_ra_wb; end + 6'b100001 : begin data_collision <= 2'b10; display_ra_wb; end +// 6'b100101 : begin data_collision <= 2'b00; display_ra_wb; end + 6'b101001 : begin data_collision <= 2'b10; display_ra_wb; end + 6'b000010 : begin data_collision <= 2'b01; display_wa_rb; end + 6'b000110 : begin data_collision <= 2'b01; display_wa_rb; end + 6'b001010 : begin data_collision <= 2'b01; display_wa_rb; end +// 6'b010010 : begin data_collision <= 2'b00; display_wa_rb; end +// 6'b010110 : begin data_collision <= 2'b00; display_wa_rb; end +// 6'b011010 : begin data_collision <= 2'b00; display_wa_rb; end + 6'b100010 : begin data_collision <= 2'b01; display_wa_rb; end + 6'b100110 : begin data_collision <= 2'b01; display_wa_rb; end + 6'b101010 : begin data_collision <= 2'b01; display_wa_rb; end + endcase + end + end + setup_zero <= 0; + end + + task display_ra_wb; + begin + if (display_flag) + $display("Memory Collision Error on RAMB16_S2_S36:%m at simulation time %.3f ns\nA read was performed on address %h (hex) of Port A while a write was requested to the same address on Port B. The write will be successful however the read value on Port A is unknown until the next CLKA cycle.", $time/1000.0, addra_int); + end + endtask + + task display_wa_rb; + begin + if (display_flag) + $display("Memory Collision Error on RAMB16_S2_S36:%m at simulation time %.3f ns\nA read was performed on address %h (hex) of Port B while a write was requested to the same address on Port A. The write will be successful however the read value on Port B is unknown until the next CLKB cycle.", $time/1000.0, addrb_int); + end + endtask + + task display_wa_wb; + begin + if (display_flag) + $display("Memory Collision Error on RAMB16_S2_S36:%m at simulation time %.3f ns\nA write was requested to the same address simultaneously at both Port A and Port B of the RAM. The contents written to the RAM at address location %h (hex) of Port A and address location %h (hex) of Port B are unknown.", $time/1000.0, addra_int, addrb_int); + end + endtask + + + always @(posedge setup_rf_a_b) begin + if (data_addra_reg[14:5] == data_addrb_int[14:5]) begin + if ((ena_reg == 1) && (enb_int == 1)) begin + case ({wr_mode_a, wr_mode_b, wea_reg, web_int}) +// 6'b000011 : begin data_collision_a_b <= 2'b00; display_wa_wb; end +// 6'b000111 : begin data_collision_a_b <= 2'b00; display_wa_wb; end +// 6'b001011 : begin data_collision_a_b <= 2'b00; display_wa_wb; end + 6'b010011 : begin data_collision_a_b <= 2'b11; display_wa_wb; end + 6'b010111 : begin data_collision_a_b <= 2'b11; display_wa_wb; end + 6'b011011 : begin data_collision_a_b <= 2'b10; display_wa_wb; end +// 6'b100011 : begin data_collision_a_b <= 2'b00; display_wa_wb; end +// 6'b100111 : begin data_collision_a_b <= 2'b00; display_wa_wb; end +// 6'b101011 : begin data_collision_a_b <= 2'b00; display_wa_wb; end +// 6'b000001 : begin data_collision_a_b <= 2'b00; display_ra_wb; end +// 6'b000101 : begin data_collision_a_b <= 2'b00; display_ra_wb; end +// 6'b001001 : begin data_collision_a_b <= 2'b00; display_ra_wb; end +// 6'b010001 : begin data_collision_a_b <= 2'b00; display_ra_wb; end +// 6'b010101 : begin data_collision_a_b <= 2'b00; display_ra_wb; end +// 6'b011001 : begin data_collision_a_b <= 2'b00; display_ra_wb; end +// 6'b100001 : begin data_collision_a_b <= 2'b00; display_ra_wb; end +// 6'b100101 : begin data_collision_a_b <= 2'b00; display_ra_wb; end +// 6'b101001 : begin data_collision_a_b <= 2'b00; display_ra_wb; end +// 6'b000010 : begin data_collision_a_b <= 2'b00; display_wa_rb; end +// 6'b000110 : begin data_collision_a_b <= 2'b00; display_wa_rb; end +// 6'b001010 : begin data_collision_a_b <= 2'b00; display_wa_rb; end + 6'b010010 : begin data_collision_a_b <= 2'b01; display_wa_rb; end + 6'b010110 : begin data_collision_a_b <= 2'b01; display_wa_rb; end + 6'b011010 : begin data_collision_a_b <= 2'b01; display_wa_rb; end +// 6'b100010 : begin data_collision_a_b <= 2'b00; display_wa_rb; end +// 6'b100110 : begin data_collision_a_b <= 2'b00; display_wa_rb; end +// 6'b101010 : begin data_collision_a_b <= 2'b00; display_wa_rb; end + endcase + end + end + setup_rf_a_b <= 0; + end + + + always @(posedge setup_rf_b_a) begin + if (data_addra_int[14:5] == data_addrb_reg[14:5]) begin + if ((ena_int == 1) && (enb_reg == 1)) begin + case ({wr_mode_a, wr_mode_b, wea_int, web_reg}) +// 6'b000011 : begin data_collision_b_a <= 2'b00; display_wa_wb; end + 6'b000111 : begin data_collision_b_a <= 2'b11; display_wa_wb; end +// 6'b001011 : begin data_collision_b_a <= 2'b00; display_wa_wb; end +// 6'b010011 : begin data_collision_b_a <= 2'b00; display_wa_wb; end + 6'b010111 : begin data_collision_b_a <= 2'b11; display_wa_wb; end +// 6'b011011 : begin data_collision_b_a <= 2'b00; display_wa_wb; end +// 6'b100011 : begin data_collision_b_a <= 2'b00; display_wa_wb; end + 6'b100111 : begin data_collision_b_a <= 2'b01; display_wa_wb; end +// 6'b101011 : begin data_collision_b_a <= 2'b00; display_wa_wb; end +// 6'b000001 : begin data_collision_b_a <= 2'b00; display_ra_wb; end + 6'b000101 : begin data_collision_b_a <= 2'b10; display_ra_wb; end +// 6'b001001 : begin data_collision_b_a <= 2'b00; display_ra_wb; end +// 6'b010001 : begin data_collision_b_a <= 2'b00; display_ra_wb; end + 6'b010101 : begin data_collision_b_a <= 2'b10; display_ra_wb; end +// 6'b011001 : begin data_collision_b_a <= 2'b00; display_ra_wb; end +// 6'b100001 : begin data_collision_b_a <= 2'b00; display_ra_wb; end + 6'b100101 : begin data_collision_b_a <= 2'b10; display_ra_wb; end +// 6'b101001 : begin data_collision_b_a <= 2'b00; display_ra_wb; end +// 6'b000010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end +// 6'b000110 : begin data_collision_b_a <= 2'b00; display_wa_rb; end +// 6'b001010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end +// 6'b010010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end +// 6'b010110 : begin data_collision_b_a <= 2'b00; display_wa_rb; end +// 6'b011010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end +// 6'b100010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end +// 6'b100110 : begin data_collision_b_a <= 2'b00; display_wa_rb; end +// 6'b101010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end + endcase + end + end + setup_rf_b_a <= 0; + end + + + always @(posedge clka_int) begin + if ((output_flag || display_flag)) begin + addra_reg <= addra_int; + ena_reg <= ena_int; + ssra_reg <= ssra_int; + wea_reg <= wea_int; + end + end + + always @(posedge clkb_int) begin + if ((output_flag || display_flag)) begin + addrb_reg <= addrb_int; + enb_reg <= enb_int; + ssrb_reg <= ssrb_int; + web_reg <= web_int; + end + end + + + // Data + always @(posedge memory_collision) begin + if ((output_flag || display_flag)) begin + mem[addra_int[12:4]][addra_int[3:0] * 2 +: 2] <= 2'bx; + memory_collision <= 0; + end + + end + + always @(posedge memory_collision_a_b) begin + if ((output_flag || display_flag)) begin + mem[addra_reg[12:4]][addra_reg[3:0] * 2 +: 2] <= 2'bx; + memory_collision_a_b <= 0; + end + end + + always @(posedge memory_collision_b_a) begin + if ((output_flag || display_flag)) begin + mem[addra_int[12:4]][addra_int[3:0] * 2 +: 2] <= 2'bx; + memory_collision_b_a <= 0; + end + end + + always @(posedge data_collision[1]) begin + if (ssra_int == 0 && output_flag) begin + doa_out <= #100 2'bX; + end + data_collision[1] <= 0; + end + + always @(posedge data_collision[0]) begin + if (ssrb_int == 0 && output_flag) begin + dob_out[addra_int[3:0] * 2 +: 2] <= #100 2'bX; + end + data_collision[0] <= 0; + end + + always @(posedge data_collision_a_b[1]) begin + if (ssra_reg == 0 && output_flag) begin + doa_out <= #100 2'bX; + end + data_collision_a_b[1] <= 0; + end + + always @(posedge data_collision_a_b[0]) begin + if (ssrb_int == 0 && output_flag) begin + dob_out[addra_reg[3:0] * 2 +: 2] <= #100 2'bX; + end + data_collision_a_b[0] <= 0; + end + + always @(posedge data_collision_b_a[1]) begin + if (ssra_int == 0 && output_flag) begin + doa_out <= #100 2'bX; + end + data_collision_b_a[1] <= 0; + end + + always @(posedge data_collision_b_a[0]) begin + if (ssrb_reg == 0 && output_flag) begin + dob_out[addra_int[3:0] * 2 +: 2] <= #100 2'bX; + end + data_collision_b_a[0] <= 0; + end + + + initial begin + case (WRITE_MODE_A) + "WRITE_FIRST" : wr_mode_a <= 2'b00; + "READ_FIRST" : wr_mode_a <= 2'b01; + "NO_CHANGE" : wr_mode_a <= 2'b10; + default : begin + $display("Attribute Syntax Error : The Attribute WRITE_MODE_A on RAMB16_S2_S36 instance %m is set to %s. Legal values for this attribute are WRITE_FIRST, READ_FIRST or NO_CHANGE.", WRITE_MODE_A); + $finish; + end + endcase + end + + initial begin + case (WRITE_MODE_B) + "WRITE_FIRST" : wr_mode_b <= 2'b00; + "READ_FIRST" : wr_mode_b <= 2'b01; + "NO_CHANGE" : wr_mode_b <= 2'b10; + default : begin + $display("Attribute Syntax Error : The Attribute WRITE_MODE_B on RAMB16_S2_S36 instance %m is set to %s. Legal values for this attribute are WRITE_FIRST, READ_FIRST or NO_CHANGE.", WRITE_MODE_B); + $finish; + end + endcase + end + + + // Port A + always @(posedge clka_int) begin + + if (ena_int == 1'b1) begin + + if (ssra_int == 1'b1) begin + {doa_out} <= #100 SRVAL_A; + end + else begin + if (wea_int == 1'b1) begin + if (wr_mode_a == 2'b00) begin + doa_out <= #100 dia_int; + end + else if (wr_mode_a == 2'b01) begin + + doa_out <= #100 mem[addra_int[12:4]][addra_int[3:0] * 2 +: 2]; + + end + end + else begin + + doa_out <= #100 mem[addra_int[12:4]][addra_int[3:0] * 2 +: 2]; + + end + end + + // memory + if (wea_int == 1'b1) begin + mem[addra_int[12:4]][addra_int[3:0] * 2 +: 2] <= dia_int; + end + + end + end + + + // Port B + always @(posedge clkb_int) begin + + if (enb_int == 1'b1) begin + + if (ssrb_int == 1'b1) begin + {dopb_out, dob_out} <= #100 SRVAL_B; + end + else begin + if (web_int == 1'b1) begin + if (wr_mode_b == 2'b00) begin + dob_out <= #100 dib_int; + dopb_out <= #100 dipb_int; + end + else if (wr_mode_b == 2'b01) begin + dob_out <= #100 mem[addrb_int]; + dopb_out <= #100 memp[addrb_int]; + end + end + else begin + dob_out <= #100 mem[addrb_int]; + dopb_out <= #100 memp[addrb_int]; + end + end + + // memory + if (web_int == 1'b1) begin + mem[addrb_int] <= dib_int; + memp[addrb_int] <= dipb_int; + end + + end + end + + +endmodule + +`endif diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/RAMB16_S2_S4.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/RAMB16_S2_S4.v new file mode 100644 index 0000000..d67737e --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/RAMB16_S2_S4.v @@ -0,0 +1,1555 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/RAMB16_S2_S4.v,v 1.11 2007/02/22 01:58:06 wloo Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2005 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / 16K-Bit Data and 2K-Bit Parity Dual Port Block RAM +// /___/ /\ Filename : RAMB16_S2_S4.v +// \ \ / \ Timestamp : Thu Mar 10 16:43:36 PST 2005 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// End Revision + +`ifdef legacy_model + +`timescale 1 ps / 1 ps + +module RAMB16_S2_S4 (DOA, DOB, ADDRA, ADDRB, CLKA, CLKB, DIA, DIB, ENA, ENB, SSRA, SSRB, WEA, WEB); + + parameter INIT_A = 2'h0; + parameter INIT_B = 4'h0; + parameter SRVAL_A = 2'h0; + parameter SRVAL_B = 4'h0; + parameter WRITE_MODE_A = "WRITE_FIRST"; + parameter WRITE_MODE_B = "WRITE_FIRST"; + parameter SIM_COLLISION_CHECK = "ALL"; + localparam SETUP_ALL = 1000; + localparam SETUP_READ_FIRST = 3000; + + parameter INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + + output [1:0] DOA; + reg [1:0] doa_out; + wire doa_out0, doa_out1; + + input [12:0] ADDRA; + input [1:0] DIA; + input ENA, CLKA, WEA, SSRA; + + output [3:0] DOB; + reg [3:0] dob_out; + wire dob_out0, dob_out1, dob_out2, dob_out3; + + input [11:0] ADDRB; + input [3:0] DIB; + input ENB, CLKB, WEB, SSRB; + + reg [18431:0] mem; + reg [8:0] count; + reg [1:0] wr_mode_a, wr_mode_b; + + reg [5:0] dmi, dbi; + reg [5:0] pmi, pbi; + + wire [12:0] addra_int; + reg [12:0] addra_reg; + wire [1:0] dia_int; + wire ena_int, clka_int, wea_int, ssra_int; + reg ena_reg, wea_reg, ssra_reg; + wire [11:0] addrb_int; + reg [11:0] addrb_reg; + wire [3:0] dib_int; + wire enb_int, clkb_int, web_int, ssrb_int; + reg display_flag; + reg enb_reg, web_reg, ssrb_reg; + + time time_clka, time_clkb; + time time_clka_clkb; + time time_clkb_clka; + + reg setup_all_a_b; + reg setup_all_b_a; + reg setup_zero; + reg setup_rf_a_b; + reg setup_rf_b_a; + reg [1:0] data_collision, data_collision_a_b, data_collision_b_a; + reg memory_collision, memory_collision_a_b, memory_collision_b_a; + reg address_collision, address_collision_a_b, address_collision_b_a; + reg change_clka; + reg change_clkb; + + wire [14:0] data_addra_int; + wire [14:0] data_addra_reg; + wire [14:0] data_addrb_int; + wire [14:0] data_addrb_reg; + wire [15:0] parity_addra_int; + wire [15:0] parity_addra_reg; + wire [15:0] parity_addrb_int; + wire [15:0] parity_addrb_reg; + + tri0 GSR = glbl.GSR; + + always @(GSR) + if (GSR) begin + assign doa_out = INIT_A[1:0]; + assign dob_out = INIT_B[3:0]; + end + else begin + deassign doa_out; + deassign dob_out; + end + + buf b_doa_out0 (doa_out0, doa_out[0]); + buf b_doa_out1 (doa_out1, doa_out[1]); + buf b_dob_out0 (dob_out0, dob_out[0]); + buf b_dob_out1 (dob_out1, dob_out[1]); + buf b_dob_out2 (dob_out2, dob_out[2]); + buf b_dob_out3 (dob_out3, dob_out[3]); + + buf b_doa0 (DOA[0], doa_out0); + buf b_doa1 (DOA[1], doa_out1); + buf b_dob0 (DOB[0], dob_out0); + buf b_dob1 (DOB[1], dob_out1); + buf b_dob2 (DOB[2], dob_out2); + buf b_dob3 (DOB[3], dob_out3); + + buf b_addra_0 (addra_int[0], ADDRA[0]); + buf b_addra_1 (addra_int[1], ADDRA[1]); + buf b_addra_2 (addra_int[2], ADDRA[2]); + buf b_addra_3 (addra_int[3], ADDRA[3]); + buf b_addra_4 (addra_int[4], ADDRA[4]); + buf b_addra_5 (addra_int[5], ADDRA[5]); + buf b_addra_6 (addra_int[6], ADDRA[6]); + buf b_addra_7 (addra_int[7], ADDRA[7]); + buf b_addra_8 (addra_int[8], ADDRA[8]); + buf b_addra_9 (addra_int[9], ADDRA[9]); + buf b_addra_10 (addra_int[10], ADDRA[10]); + buf b_addra_11 (addra_int[11], ADDRA[11]); + buf b_addra_12 (addra_int[12], ADDRA[12]); + buf b_dia_0 (dia_int[0], DIA[0]); + buf b_dia_1 (dia_int[1], DIA[1]); + buf b_ena (ena_int, ENA); + buf b_clka (clka_int, CLKA); + buf b_ssra (ssra_int, SSRA); + buf b_wea (wea_int, WEA); + buf b_addrb_0 (addrb_int[0], ADDRB[0]); + buf b_addrb_1 (addrb_int[1], ADDRB[1]); + buf b_addrb_2 (addrb_int[2], ADDRB[2]); + buf b_addrb_3 (addrb_int[3], ADDRB[3]); + buf b_addrb_4 (addrb_int[4], ADDRB[4]); + buf b_addrb_5 (addrb_int[5], ADDRB[5]); + buf b_addrb_6 (addrb_int[6], ADDRB[6]); + buf b_addrb_7 (addrb_int[7], ADDRB[7]); + buf b_addrb_8 (addrb_int[8], ADDRB[8]); + buf b_addrb_9 (addrb_int[9], ADDRB[9]); + buf b_addrb_10 (addrb_int[10], ADDRB[10]); + buf b_addrb_11 (addrb_int[11], ADDRB[11]); + buf b_dib_0 (dib_int[0], DIB[0]); + buf b_dib_1 (dib_int[1], DIB[1]); + buf b_dib_2 (dib_int[2], DIB[2]); + buf b_dib_3 (dib_int[3], DIB[3]); + buf b_enb (enb_int, ENB); + buf b_clkb (clkb_int, CLKB); + buf b_ssrb (ssrb_int, SSRB); + buf b_web (web_int, WEB); + + initial begin + for (count = 0; count < 256; count = count + 1) begin + mem[count] <= INIT_00[count]; + mem[256 * 1 + count] <= INIT_01[count]; + mem[256 * 2 + count] <= INIT_02[count]; + mem[256 * 3 + count] <= INIT_03[count]; + mem[256 * 4 + count] <= INIT_04[count]; + mem[256 * 5 + count] <= INIT_05[count]; + mem[256 * 6 + count] <= INIT_06[count]; + mem[256 * 7 + count] <= INIT_07[count]; + mem[256 * 8 + count] <= INIT_08[count]; + mem[256 * 9 + count] <= INIT_09[count]; + mem[256 * 10 + count] <= INIT_0A[count]; + mem[256 * 11 + count] <= INIT_0B[count]; + mem[256 * 12 + count] <= INIT_0C[count]; + mem[256 * 13 + count] <= INIT_0D[count]; + mem[256 * 14 + count] <= INIT_0E[count]; + mem[256 * 15 + count] <= INIT_0F[count]; + mem[256 * 16 + count] <= INIT_10[count]; + mem[256 * 17 + count] <= INIT_11[count]; + mem[256 * 18 + count] <= INIT_12[count]; + mem[256 * 19 + count] <= INIT_13[count]; + mem[256 * 20 + count] <= INIT_14[count]; + mem[256 * 21 + count] <= INIT_15[count]; + mem[256 * 22 + count] <= INIT_16[count]; + mem[256 * 23 + count] <= INIT_17[count]; + mem[256 * 24 + count] <= INIT_18[count]; + mem[256 * 25 + count] <= INIT_19[count]; + mem[256 * 26 + count] <= INIT_1A[count]; + mem[256 * 27 + count] <= INIT_1B[count]; + mem[256 * 28 + count] <= INIT_1C[count]; + mem[256 * 29 + count] <= INIT_1D[count]; + mem[256 * 30 + count] <= INIT_1E[count]; + mem[256 * 31 + count] <= INIT_1F[count]; + mem[256 * 32 + count] <= INIT_20[count]; + mem[256 * 33 + count] <= INIT_21[count]; + mem[256 * 34 + count] <= INIT_22[count]; + mem[256 * 35 + count] <= INIT_23[count]; + mem[256 * 36 + count] <= INIT_24[count]; + mem[256 * 37 + count] <= INIT_25[count]; + mem[256 * 38 + count] <= INIT_26[count]; + mem[256 * 39 + count] <= INIT_27[count]; + mem[256 * 40 + count] <= INIT_28[count]; + mem[256 * 41 + count] <= INIT_29[count]; + mem[256 * 42 + count] <= INIT_2A[count]; + mem[256 * 43 + count] <= INIT_2B[count]; + mem[256 * 44 + count] <= INIT_2C[count]; + mem[256 * 45 + count] <= INIT_2D[count]; + mem[256 * 46 + count] <= INIT_2E[count]; + mem[256 * 47 + count] <= INIT_2F[count]; + mem[256 * 48 + count] <= INIT_30[count]; + mem[256 * 49 + count] <= INIT_31[count]; + mem[256 * 50 + count] <= INIT_32[count]; + mem[256 * 51 + count] <= INIT_33[count]; + mem[256 * 52 + count] <= INIT_34[count]; + mem[256 * 53 + count] <= INIT_35[count]; + mem[256 * 54 + count] <= INIT_36[count]; + mem[256 * 55 + count] <= INIT_37[count]; + mem[256 * 56 + count] <= INIT_38[count]; + mem[256 * 57 + count] <= INIT_39[count]; + mem[256 * 58 + count] <= INIT_3A[count]; + mem[256 * 59 + count] <= INIT_3B[count]; + mem[256 * 60 + count] <= INIT_3C[count]; + mem[256 * 61 + count] <= INIT_3D[count]; + mem[256 * 62 + count] <= INIT_3E[count]; + mem[256 * 63 + count] <= INIT_3F[count]; + end + address_collision <= 0; + address_collision_a_b <= 0; + address_collision_b_a <= 0; + change_clka <= 0; + change_clkb <= 0; + data_collision <= 0; + data_collision_a_b <= 0; + data_collision_b_a <= 0; + memory_collision <= 0; + memory_collision_a_b <= 0; + memory_collision_b_a <= 0; + setup_all_a_b <= 0; + setup_all_b_a <= 0; + setup_zero <= 0; + setup_rf_a_b <= 0; + setup_rf_b_a <= 0; + end + + assign data_addra_int = addra_int * 2; + assign data_addra_reg = addra_reg * 2; + assign data_addrb_int = addrb_int * 4; + assign data_addrb_reg = addrb_reg * 4; + + + initial begin + + display_flag = 1; + + case (SIM_COLLISION_CHECK) + + "NONE" : begin + assign setup_all_a_b = 1'b0; + assign setup_all_b_a = 1'b0; + assign setup_zero = 1'b0; + assign setup_rf_a_b = 1'b0; + assign setup_rf_b_a = 1'b0; + assign display_flag = 0; + end + "WARNING_ONLY" : begin + assign data_collision = 2'b00; + assign data_collision_a_b = 2'b00; + assign data_collision_b_a = 2'b00; + assign memory_collision = 1'b0; + assign memory_collision_a_b = 1'b0; + assign memory_collision_b_a = 1'b0; + end + "GENERATE_X_ONLY" : begin + assign display_flag = 0; + end + "ALL" : ; + default : begin + $display("Attribute Syntax Error : The Attribute SIM_COLLISION_CHECK on RAMB16_S2_S4 instance %m is set to %s. Legal values for this attribute are ALL, NONE, WARNING_ONLY or GENERATE_X_ONLY.", SIM_COLLISION_CHECK); + $finish; + end + + endcase // case(SIM_COLLISION_CHECK) + + end // initial begin + + + always @(posedge clka_int) begin + time_clka = $time; + #0 time_clkb_clka = time_clka - time_clkb; + change_clka = ~change_clka; + end + + always @(posedge clkb_int) begin + time_clkb = $time; + #0 time_clka_clkb = time_clkb - time_clka; + change_clkb = ~change_clkb; + end + + always @(change_clkb) begin + if ((0 < time_clka_clkb) && (time_clka_clkb < SETUP_ALL)) + setup_all_a_b = 1; + if ((0 < time_clka_clkb) && (time_clka_clkb < SETUP_READ_FIRST)) + setup_rf_a_b = 1; + end + + always @(change_clka) begin + if ((0 < time_clkb_clka) && (time_clkb_clka < SETUP_ALL)) + setup_all_b_a = 1; + if ((0 < time_clkb_clka) && (time_clkb_clka < SETUP_READ_FIRST)) + setup_rf_b_a = 1; + end + + always @(change_clkb or change_clka) begin + if ((time_clkb_clka == 0) && (time_clka_clkb == 0)) + setup_zero = 1; + end + + always @(posedge setup_zero) begin + if ((ena_int == 1) && (wea_int == 1) && + (enb_int == 1) && (web_int == 1) && + (data_addra_int[14:2] == data_addrb_int[14:2])) + memory_collision <= 1; + end + + always @(posedge setup_all_a_b or posedge setup_rf_a_b) begin + if ((ena_reg == 1) && (wea_reg == 1) && + (enb_int == 1) && (web_int == 1) && + (data_addra_reg[14:2] == data_addrb_int[14:2])) + memory_collision_a_b <= 1; + end + + always @(posedge setup_all_b_a or posedge setup_rf_b_a) begin + if ((ena_int == 1) && (wea_int == 1) && + (enb_reg == 1) && (web_reg == 1) && + (data_addra_int[14:2] == data_addrb_reg[14:2])) + memory_collision_b_a <= 1; + end + + always @(posedge setup_all_a_b) begin + if (data_addra_reg[14:2] == data_addrb_int[14:2]) begin + if ((ena_reg == 1) && (enb_int == 1)) begin + case ({wr_mode_a, wr_mode_b, wea_reg, web_int}) + 6'b000011 : begin data_collision_a_b <= 2'b11; display_wa_wb; end + 6'b000111 : begin data_collision_a_b <= 2'b11; display_wa_wb; end + 6'b001011 : begin data_collision_a_b <= 2'b10; display_wa_wb; end +// 6'b010011 : begin data_collision_a_b <= 2'b00; display_wa_wb; end +// 6'b010111 : begin data_collision_a_b <= 2'b00; display_wa_wb; end +// 6'b011011 : begin data_collision_a_b <= 2'b00; display_wa_wb; end + 6'b100011 : begin data_collision_a_b <= 2'b01; display_wa_wb; end + 6'b100111 : begin data_collision_a_b <= 2'b01; display_wa_wb; end + 6'b101011 : begin display_wa_wb; end + 6'b000001 : begin data_collision_a_b <= 2'b10; display_ra_wb; end +// 6'b000101 : begin data_collision_a_b <= 2'b00; display_ra_wb; end + 6'b001001 : begin data_collision_a_b <= 2'b10; display_ra_wb; end + 6'b010001 : begin data_collision_a_b <= 2'b10; display_ra_wb; end +// 6'b010101 : begin data_collision_a_b <= 2'b00; display_ra_wb; end + 6'b011001 : begin data_collision_a_b <= 2'b10; display_ra_wb; end + 6'b100001 : begin data_collision_a_b <= 2'b10; display_ra_wb; end +// 6'b100101 : begin data_collision_a_b <= 2'b00; display_ra_wb; end + 6'b101001 : begin data_collision_a_b <= 2'b10; display_ra_wb; end + 6'b000010 : begin data_collision_a_b <= 2'b01; display_wa_rb; end + 6'b000110 : begin data_collision_a_b <= 2'b01; display_wa_rb; end + 6'b001010 : begin data_collision_a_b <= 2'b01; display_wa_rb; end +// 6'b010010 : begin data_collision_a_b <= 2'b00; display_wa_rb; end +// 6'b010110 : begin data_collision_a_b <= 2'b00; display_wa_rb; end +// 6'b011010 : begin data_collision_a_b <= 2'b00; display_wa_rb; end + 6'b100010 : begin data_collision_a_b <= 2'b01; display_wa_rb; end + 6'b100110 : begin data_collision_a_b <= 2'b01; display_wa_rb; end + 6'b101010 : begin data_collision_a_b <= 2'b01; display_wa_rb; end + endcase + end + end + setup_all_a_b <= 0; + end + + + always @(posedge setup_all_b_a) begin + if (data_addra_int[14:2] == data_addrb_reg[14:2]) begin + if ((ena_int == 1) && (enb_reg == 1)) begin + case ({wr_mode_a, wr_mode_b, wea_int, web_reg}) + 6'b000011 : begin data_collision_b_a <= 2'b11; display_wa_wb; end +// 6'b000111 : begin data_collision_b_a <= 2'b00; display_wa_wb; end + 6'b001011 : begin data_collision_b_a <= 2'b10; display_wa_wb; end + 6'b010011 : begin data_collision_b_a <= 2'b11; display_wa_wb; end +// 6'b010111 : begin data_collision_b_a <= 2'b00; display_wa_wb; end + 6'b011011 : begin data_collision_b_a <= 2'b10; display_wa_wb; end + 6'b100011 : begin data_collision_b_a <= 2'b01; display_wa_wb; end + 6'b100111 : begin data_collision_b_a <= 2'b01; display_wa_wb; end + 6'b101011 : begin display_wa_wb; end + 6'b000001 : begin data_collision_b_a <= 2'b10; display_ra_wb; end + 6'b000101 : begin data_collision_b_a <= 2'b10; display_ra_wb; end + 6'b001001 : begin data_collision_b_a <= 2'b10; display_ra_wb; end + 6'b010001 : begin data_collision_b_a <= 2'b10; display_ra_wb; end + 6'b010101 : begin data_collision_b_a <= 2'b10; display_ra_wb; end + 6'b011001 : begin data_collision_b_a <= 2'b10; display_ra_wb; end + 6'b100001 : begin data_collision_b_a <= 2'b10; display_ra_wb; end + 6'b100101 : begin data_collision_b_a <= 2'b10; display_ra_wb; end + 6'b101001 : begin data_collision_b_a <= 2'b10; display_ra_wb; end + 6'b000010 : begin data_collision_b_a <= 2'b01; display_wa_rb; end + 6'b000110 : begin data_collision_b_a <= 2'b01; display_wa_rb; end + 6'b001010 : begin data_collision_b_a <= 2'b01; display_wa_rb; end +// 6'b010010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end +// 6'b010110 : begin data_collision_b_a <= 2'b00; display_wa_rb; end +// 6'b011010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end + 6'b100010 : begin data_collision_b_a <= 2'b01; display_wa_rb; end + 6'b100110 : begin data_collision_b_a <= 2'b01; display_wa_rb; end + 6'b101010 : begin data_collision_b_a <= 2'b01; display_wa_rb; end + endcase + end + end + setup_all_b_a <= 0; + end + + + always @(posedge setup_zero) begin + if (data_addra_int[14:2] == data_addrb_int[14:2]) begin + if ((ena_int == 1) && (enb_int == 1)) begin + case ({wr_mode_a, wr_mode_b, wea_int, web_int}) + 6'b000011 : begin data_collision <= 2'b11; display_wa_wb; end + 6'b000111 : begin data_collision <= 2'b11; display_wa_wb; end + 6'b001011 : begin data_collision <= 2'b10; display_wa_wb; end + 6'b010011 : begin data_collision <= 2'b11; display_wa_wb; end + 6'b010111 : begin data_collision <= 2'b11; display_wa_wb; end + 6'b011011 : begin data_collision <= 2'b10; display_wa_wb; end + 6'b100011 : begin data_collision <= 2'b01; display_wa_wb; end + 6'b100111 : begin data_collision <= 2'b01; display_wa_wb; end + 6'b101011 : begin display_wa_wb; end + 6'b000001 : begin data_collision <= 2'b10; display_ra_wb; end +// 6'b000101 : begin data_collision <= 2'b00; display_ra_wb; end + 6'b001001 : begin data_collision <= 2'b10; display_ra_wb; end + 6'b010001 : begin data_collision <= 2'b10; display_ra_wb; end +// 6'b010101 : begin data_collision <= 2'b00; display_ra_wb; end + 6'b011001 : begin data_collision <= 2'b10; display_ra_wb; end + 6'b100001 : begin data_collision <= 2'b10; display_ra_wb; end +// 6'b100101 : begin data_collision <= 2'b00; display_ra_wb; end + 6'b101001 : begin data_collision <= 2'b10; display_ra_wb; end + 6'b000010 : begin data_collision <= 2'b01; display_wa_rb; end + 6'b000110 : begin data_collision <= 2'b01; display_wa_rb; end + 6'b001010 : begin data_collision <= 2'b01; display_wa_rb; end +// 6'b010010 : begin data_collision <= 2'b00; display_wa_rb; end +// 6'b010110 : begin data_collision <= 2'b00; display_wa_rb; end +// 6'b011010 : begin data_collision <= 2'b00; display_wa_rb; end + 6'b100010 : begin data_collision <= 2'b01; display_wa_rb; end + 6'b100110 : begin data_collision <= 2'b01; display_wa_rb; end + 6'b101010 : begin data_collision <= 2'b01; display_wa_rb; end + endcase + end + end + setup_zero <= 0; + end + + task display_ra_wb; + begin + if (display_flag) + $display("Memory Collision Error on RAMB16_S2_S4:%m at simulation time %.3f ns\nA read was performed on address %h (hex) of Port A while a write was requested to the same address on Port B. The write will be successful however the read value on Port A is unknown until the next CLKA cycle.", $time/1000.0, addra_int); + end + endtask + + task display_wa_rb; + begin + if (display_flag) + $display("Memory Collision Error on RAMB16_S2_S4:%m at simulation time %.3f ns\nA read was performed on address %h (hex) of Port B while a write was requested to the same address on Port A. The write will be successful however the read value on Port B is unknown until the next CLKB cycle.", $time/1000.0, addrb_int); + end + endtask + + task display_wa_wb; + begin + if (display_flag) + $display("Memory Collision Error on RAMB16_S2_S4:%m at simulation time %.3f ns\nA write was requested to the same address simultaneously at both Port A and Port B of the RAM. The contents written to the RAM at address location %h (hex) of Port A and address location %h (hex) of Port B are unknown.", $time/1000.0, addra_int, addrb_int); + end + endtask + + + always @(posedge setup_rf_a_b) begin + if (data_addra_reg[14:2] == data_addrb_int[14:2]) begin + if ((ena_reg == 1) && (enb_int == 1)) begin + case ({wr_mode_a, wr_mode_b, wea_reg, web_int}) +// 6'b000011 : begin data_collision_a_b <= 2'b00; display_wa_wb; end +// 6'b000111 : begin data_collision_a_b <= 2'b00; display_wa_wb; end +// 6'b001011 : begin data_collision_a_b <= 2'b00; display_wa_wb; end + 6'b010011 : begin data_collision_a_b <= 2'b11; display_wa_wb; end + 6'b010111 : begin data_collision_a_b <= 2'b11; display_wa_wb; end + 6'b011011 : begin data_collision_a_b <= 2'b10; display_wa_wb; end +// 6'b100011 : begin data_collision_a_b <= 2'b00; display_wa_wb; end +// 6'b100111 : begin data_collision_a_b <= 2'b00; display_wa_wb; end +// 6'b101011 : begin data_collision_a_b <= 2'b00; display_wa_wb; end +// 6'b000001 : begin data_collision_a_b <= 2'b00; display_ra_wb; end +// 6'b000101 : begin data_collision_a_b <= 2'b00; display_ra_wb; end +// 6'b001001 : begin data_collision_a_b <= 2'b00; display_ra_wb; end +// 6'b010001 : begin data_collision_a_b <= 2'b00; display_ra_wb; end +// 6'b010101 : begin data_collision_a_b <= 2'b00; display_ra_wb; end +// 6'b011001 : begin data_collision_a_b <= 2'b00; display_ra_wb; end +// 6'b100001 : begin data_collision_a_b <= 2'b00; display_ra_wb; end +// 6'b100101 : begin data_collision_a_b <= 2'b00; display_ra_wb; end +// 6'b101001 : begin data_collision_a_b <= 2'b00; display_ra_wb; end +// 6'b000010 : begin data_collision_a_b <= 2'b00; display_wa_rb; end +// 6'b000110 : begin data_collision_a_b <= 2'b00; display_wa_rb; end +// 6'b001010 : begin data_collision_a_b <= 2'b00; display_wa_rb; end + 6'b010010 : begin data_collision_a_b <= 2'b01; display_wa_rb; end + 6'b010110 : begin data_collision_a_b <= 2'b01; display_wa_rb; end + 6'b011010 : begin data_collision_a_b <= 2'b01; display_wa_rb; end +// 6'b100010 : begin data_collision_a_b <= 2'b00; display_wa_rb; end +// 6'b100110 : begin data_collision_a_b <= 2'b00; display_wa_rb; end +// 6'b101010 : begin data_collision_a_b <= 2'b00; display_wa_rb; end + endcase + end + end + setup_rf_a_b <= 0; + end + + + always @(posedge setup_rf_b_a) begin + if (data_addra_int[14:2] == data_addrb_reg[14:2]) begin + if ((ena_int == 1) && (enb_reg == 1)) begin + case ({wr_mode_a, wr_mode_b, wea_int, web_reg}) +// 6'b000011 : begin data_collision_b_a <= 2'b00; display_wa_wb; end + 6'b000111 : begin data_collision_b_a <= 2'b11; display_wa_wb; end +// 6'b001011 : begin data_collision_b_a <= 2'b00; display_wa_wb; end +// 6'b010011 : begin data_collision_b_a <= 2'b00; display_wa_wb; end + 6'b010111 : begin data_collision_b_a <= 2'b11; display_wa_wb; end +// 6'b011011 : begin data_collision_b_a <= 2'b00; display_wa_wb; end +// 6'b100011 : begin data_collision_b_a <= 2'b00; display_wa_wb; end + 6'b100111 : begin data_collision_b_a <= 2'b01; display_wa_wb; end +// 6'b101011 : begin data_collision_b_a <= 2'b00; display_wa_wb; end +// 6'b000001 : begin data_collision_b_a <= 2'b00; display_ra_wb; end + 6'b000101 : begin data_collision_b_a <= 2'b10; display_ra_wb; end +// 6'b001001 : begin data_collision_b_a <= 2'b00; display_ra_wb; end +// 6'b010001 : begin data_collision_b_a <= 2'b00; display_ra_wb; end + 6'b010101 : begin data_collision_b_a <= 2'b10; display_ra_wb; end +// 6'b011001 : begin data_collision_b_a <= 2'b00; display_ra_wb; end +// 6'b100001 : begin data_collision_b_a <= 2'b00; display_ra_wb; end + 6'b100101 : begin data_collision_b_a <= 2'b10; display_ra_wb; end +// 6'b101001 : begin data_collision_b_a <= 2'b00; display_ra_wb; end +// 6'b000010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end +// 6'b000110 : begin data_collision_b_a <= 2'b00; display_wa_rb; end +// 6'b001010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end +// 6'b010010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end +// 6'b010110 : begin data_collision_b_a <= 2'b00; display_wa_rb; end +// 6'b011010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end +// 6'b100010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end +// 6'b100110 : begin data_collision_b_a <= 2'b00; display_wa_rb; end +// 6'b101010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end + endcase + end + end + setup_rf_b_a <= 0; + end + + + always @(posedge clka_int) begin + addra_reg <= addra_int; + ena_reg <= ena_int; + ssra_reg <= ssra_int; + wea_reg <= wea_int; + end + + always @(posedge clkb_int) begin + addrb_reg <= addrb_int; + enb_reg <= enb_int; + ssrb_reg <= ssrb_int; + web_reg <= web_int; + end + + // Data + always @(posedge memory_collision) begin + for (dmi = 0; dmi < 2; dmi = dmi + 1) begin + mem[data_addra_int + dmi] <= 1'bX; + end + memory_collision <= 0; + end + + always @(posedge memory_collision_a_b) begin + for (dmi = 0; dmi < 2; dmi = dmi + 1) begin + mem[data_addra_reg + dmi] <= 1'bX; + end + memory_collision_a_b <= 0; + end + + always @(posedge memory_collision_b_a) begin + for (dmi = 0; dmi < 2; dmi = dmi + 1) begin + mem[data_addra_int + dmi] <= 1'bX; + end + memory_collision_b_a <= 0; + end + + always @(posedge data_collision[1]) begin + if (ssra_int == 0) begin + doa_out <= 2'bX; + end + data_collision[1] <= 0; + end + + always @(posedge data_collision[0]) begin + if (ssrb_int == 0) begin + for (dbi = 0; dbi < 2; dbi = dbi + 1) begin + dob_out[data_addra_int[1 : 0] + dbi] <= 1'bX; + end + end + data_collision[0] <= 0; + end + + always @(posedge data_collision_a_b[1]) begin + if (ssra_reg == 0) begin + doa_out <= 2'bX; + end + data_collision_a_b[1] <= 0; + end + + always @(posedge data_collision_a_b[0]) begin + if (ssrb_int == 0) begin + for (dbi = 0; dbi < 2; dbi = dbi + 1) begin + dob_out[data_addra_reg[1 : 0] + dbi] <= 1'bX; + end + end + data_collision_a_b[0] <= 0; + end + + always @(posedge data_collision_b_a[1]) begin + if (ssra_int == 0) begin + doa_out <= 2'bX; + end + data_collision_b_a[1] <= 0; + end + + always @(posedge data_collision_b_a[0]) begin + if (ssrb_reg == 0) begin + for (dbi = 0; dbi < 2; dbi = dbi + 1) begin + dob_out[data_addra_int[1 : 0] + dbi] <= 1'bX; + end + end + data_collision_b_a[0] <= 0; + end + + + initial begin + case (WRITE_MODE_A) + "WRITE_FIRST" : wr_mode_a <= 2'b00; + "READ_FIRST" : wr_mode_a <= 2'b01; + "NO_CHANGE" : wr_mode_a <= 2'b10; + default : begin + $display("Attribute Syntax Error : The Attribute WRITE_MODE_A on RAMB16_S2_S4 instance %m is set to %s. Legal values for this attribute are WRITE_FIRST, READ_FIRST or NO_CHANGE.", WRITE_MODE_A); + $finish; + end + endcase + end + + initial begin + case (WRITE_MODE_B) + "WRITE_FIRST" : wr_mode_b <= 2'b00; + "READ_FIRST" : wr_mode_b <= 2'b01; + "NO_CHANGE" : wr_mode_b <= 2'b10; + default : begin + $display("Attribute Syntax Error : The Attribute WRITE_MODE_B on RAMB16_S2_S4 instance %m is set to %s. Legal values for this attribute are WRITE_FIRST, READ_FIRST or NO_CHANGE.", WRITE_MODE_B); + $finish; + end + endcase + end + + // Port A + always @(posedge clka_int) begin + if (ena_int == 1'b1) begin + if (ssra_int == 1'b1) begin + doa_out[0] <= SRVAL_A[0]; + doa_out[1] <= SRVAL_A[1]; + end + else begin + if (wea_int == 1'b1) begin + if (wr_mode_a == 2'b00) begin + doa_out <= dia_int; + end + else if (wr_mode_a == 2'b01) begin + doa_out[0] <= mem[data_addra_int + 0]; + doa_out[1] <= mem[data_addra_int + 1]; + end + end + else begin + doa_out[0] <= mem[data_addra_int + 0]; + doa_out[1] <= mem[data_addra_int + 1]; + end + end + end + end + + always @(posedge clka_int) begin + if (ena_int == 1'b1 && wea_int == 1'b1) begin + mem[data_addra_int + 0] <= dia_int[0]; + mem[data_addra_int + 1] <= dia_int[1]; + end + end + + // Port B + always @(posedge clkb_int) begin + if (enb_int == 1'b1) begin + if (ssrb_int == 1'b1) begin + dob_out[0] <= SRVAL_B[0]; + dob_out[1] <= SRVAL_B[1]; + dob_out[2] <= SRVAL_B[2]; + dob_out[3] <= SRVAL_B[3]; + end + else begin + if (web_int == 1'b1) begin + if (wr_mode_b == 2'b00) begin + dob_out <= dib_int; + end + else if (wr_mode_b == 2'b01) begin + dob_out[0] <= mem[data_addrb_int + 0]; + dob_out[1] <= mem[data_addrb_int + 1]; + dob_out[2] <= mem[data_addrb_int + 2]; + dob_out[3] <= mem[data_addrb_int + 3]; + end + end + else begin + dob_out[0] <= mem[data_addrb_int + 0]; + dob_out[1] <= mem[data_addrb_int + 1]; + dob_out[2] <= mem[data_addrb_int + 2]; + dob_out[3] <= mem[data_addrb_int + 3]; + end + end + end + end + + always @(posedge clkb_int) begin + if (enb_int == 1'b1 && web_int == 1'b1) begin + mem[data_addrb_int + 0] <= dib_int[0]; + mem[data_addrb_int + 1] <= dib_int[1]; + mem[data_addrb_int + 2] <= dib_int[2]; + mem[data_addrb_int + 3] <= dib_int[3]; + end + end + + specify + (CLKA *> DOA) = (100, 100); + (CLKB *> DOB) = (100, 100); + endspecify + +endmodule + +`else + +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/RAMB16_S2_S4.v,v 1.11 2007/02/22 01:58:06 wloo Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2005 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Timing Simulation Library Component +// / / 16K-Bit Data and 2K-Bit Parity Dual Port Block RAM +// /___/ /\ Filename : RAMB16_S2_S4.v +// \ \ / \ Timestamp : Thu Mar 10 16:44:01 PST 2005 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 03/10/05 - Initialized outputs. +// 02/21/07 - Fixed parameter SIM_COLLISION_CHECK (CR 433281). +// End Revision + +`timescale 1 ps/1 ps + +module RAMB16_S2_S4 (DOA, DOB, ADDRA, ADDRB, CLKA, CLKB, DIA, DIB, ENA, ENB, SSRA, SSRB, WEA, WEB); + + parameter INIT_A = 2'h0; + parameter INIT_B = 4'h0; + parameter SRVAL_A = 2'h0; + parameter SRVAL_B = 4'h0; + parameter WRITE_MODE_A = "WRITE_FIRST"; + parameter WRITE_MODE_B = "WRITE_FIRST"; + parameter SIM_COLLISION_CHECK = "ALL"; + localparam SETUP_ALL = 1000; + localparam SETUP_READ_FIRST = 3000; + + parameter INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + + output [1:0] DOA; + output [3:0] DOB; + + input [12:0] ADDRA; + input [1:0] DIA; + input ENA, CLKA, WEA, SSRA; + input [11:0] ADDRB; + input [3:0] DIB; + input ENB, CLKB, WEB, SSRB; + + reg [1:0] doa_out = INIT_A[1:0]; + reg [3:0] dob_out = INIT_B[3:0]; + + reg [3:0] mem [4095:0]; + + reg [8:0] count, countp; + reg [1:0] wr_mode_a, wr_mode_b; + + reg [5:0] dmi, dbi; + reg [5:0] pmi, pbi; + + wire [12:0] addra_int; + reg [12:0] addra_reg; + wire [1:0] dia_int; + wire ena_int, clka_int, wea_int, ssra_int; + reg ena_reg, wea_reg, ssra_reg; + wire [11:0] addrb_int; + reg [11:0] addrb_reg; + wire [3:0] dib_int; + wire enb_int, clkb_int, web_int, ssrb_int; + reg display_flag, output_flag; + reg enb_reg, web_reg, ssrb_reg; + + time time_clka, time_clkb; + time time_clka_clkb; + time time_clkb_clka; + + reg setup_all_a_b; + reg setup_all_b_a; + reg setup_zero; + reg setup_rf_a_b; + reg setup_rf_b_a; + reg [1:0] data_collision, data_collision_a_b, data_collision_b_a; + reg memory_collision, memory_collision_a_b, memory_collision_b_a; + reg change_clka; + reg change_clkb; + + wire [14:0] data_addra_int; + wire [14:0] data_addra_reg; + wire [14:0] data_addrb_int; + wire [14:0] data_addrb_reg; + + wire dia_enable = ena_int && wea_int; + wire dib_enable = enb_int && web_int; + + tri0 GSR = glbl.GSR; + wire gsr_int; + + buf b_gsr (gsr_int, GSR); + + buf b_doa [1:0] (DOA, doa_out); + buf b_addra [12:0] (addra_int, ADDRA); + buf b_dia [1:0] (dia_int, DIA); + buf b_ena (ena_int, ENA); + buf b_clka (clka_int, CLKA); + buf b_ssra (ssra_int, SSRA); + buf b_wea (wea_int, WEA); + + buf b_dob [3:0] (DOB, dob_out); + buf b_addrb [11:0] (addrb_int, ADDRB); + buf b_dib [3:0] (dib_int, DIB); + buf b_enb (enb_int, ENB); + buf b_clkb (clkb_int, CLKB); + buf b_ssrb (ssrb_int, SSRB); + buf b_web (web_int, WEB); + + + always @(gsr_int) + if (gsr_int) begin + assign {doa_out} = INIT_A; + assign {dob_out} = INIT_B; + end + else begin + deassign doa_out; + deassign dob_out; + end + + + initial begin + + for (count = 0; count < 64; count = count + 1) begin + mem[count] = INIT_00[(count * 4) +: 4]; + mem[64 * 1 + count] = INIT_01[(count * 4) +: 4]; + mem[64 * 2 + count] = INIT_02[(count * 4) +: 4]; + mem[64 * 3 + count] = INIT_03[(count * 4) +: 4]; + mem[64 * 4 + count] = INIT_04[(count * 4) +: 4]; + mem[64 * 5 + count] = INIT_05[(count * 4) +: 4]; + mem[64 * 6 + count] = INIT_06[(count * 4) +: 4]; + mem[64 * 7 + count] = INIT_07[(count * 4) +: 4]; + mem[64 * 8 + count] = INIT_08[(count * 4) +: 4]; + mem[64 * 9 + count] = INIT_09[(count * 4) +: 4]; + mem[64 * 10 + count] = INIT_0A[(count * 4) +: 4]; + mem[64 * 11 + count] = INIT_0B[(count * 4) +: 4]; + mem[64 * 12 + count] = INIT_0C[(count * 4) +: 4]; + mem[64 * 13 + count] = INIT_0D[(count * 4) +: 4]; + mem[64 * 14 + count] = INIT_0E[(count * 4) +: 4]; + mem[64 * 15 + count] = INIT_0F[(count * 4) +: 4]; + mem[64 * 16 + count] = INIT_10[(count * 4) +: 4]; + mem[64 * 17 + count] = INIT_11[(count * 4) +: 4]; + mem[64 * 18 + count] = INIT_12[(count * 4) +: 4]; + mem[64 * 19 + count] = INIT_13[(count * 4) +: 4]; + mem[64 * 20 + count] = INIT_14[(count * 4) +: 4]; + mem[64 * 21 + count] = INIT_15[(count * 4) +: 4]; + mem[64 * 22 + count] = INIT_16[(count * 4) +: 4]; + mem[64 * 23 + count] = INIT_17[(count * 4) +: 4]; + mem[64 * 24 + count] = INIT_18[(count * 4) +: 4]; + mem[64 * 25 + count] = INIT_19[(count * 4) +: 4]; + mem[64 * 26 + count] = INIT_1A[(count * 4) +: 4]; + mem[64 * 27 + count] = INIT_1B[(count * 4) +: 4]; + mem[64 * 28 + count] = INIT_1C[(count * 4) +: 4]; + mem[64 * 29 + count] = INIT_1D[(count * 4) +: 4]; + mem[64 * 30 + count] = INIT_1E[(count * 4) +: 4]; + mem[64 * 31 + count] = INIT_1F[(count * 4) +: 4]; + mem[64 * 32 + count] = INIT_20[(count * 4) +: 4]; + mem[64 * 33 + count] = INIT_21[(count * 4) +: 4]; + mem[64 * 34 + count] = INIT_22[(count * 4) +: 4]; + mem[64 * 35 + count] = INIT_23[(count * 4) +: 4]; + mem[64 * 36 + count] = INIT_24[(count * 4) +: 4]; + mem[64 * 37 + count] = INIT_25[(count * 4) +: 4]; + mem[64 * 38 + count] = INIT_26[(count * 4) +: 4]; + mem[64 * 39 + count] = INIT_27[(count * 4) +: 4]; + mem[64 * 40 + count] = INIT_28[(count * 4) +: 4]; + mem[64 * 41 + count] = INIT_29[(count * 4) +: 4]; + mem[64 * 42 + count] = INIT_2A[(count * 4) +: 4]; + mem[64 * 43 + count] = INIT_2B[(count * 4) +: 4]; + mem[64 * 44 + count] = INIT_2C[(count * 4) +: 4]; + mem[64 * 45 + count] = INIT_2D[(count * 4) +: 4]; + mem[64 * 46 + count] = INIT_2E[(count * 4) +: 4]; + mem[64 * 47 + count] = INIT_2F[(count * 4) +: 4]; + mem[64 * 48 + count] = INIT_30[(count * 4) +: 4]; + mem[64 * 49 + count] = INIT_31[(count * 4) +: 4]; + mem[64 * 50 + count] = INIT_32[(count * 4) +: 4]; + mem[64 * 51 + count] = INIT_33[(count * 4) +: 4]; + mem[64 * 52 + count] = INIT_34[(count * 4) +: 4]; + mem[64 * 53 + count] = INIT_35[(count * 4) +: 4]; + mem[64 * 54 + count] = INIT_36[(count * 4) +: 4]; + mem[64 * 55 + count] = INIT_37[(count * 4) +: 4]; + mem[64 * 56 + count] = INIT_38[(count * 4) +: 4]; + mem[64 * 57 + count] = INIT_39[(count * 4) +: 4]; + mem[64 * 58 + count] = INIT_3A[(count * 4) +: 4]; + mem[64 * 59 + count] = INIT_3B[(count * 4) +: 4]; + mem[64 * 60 + count] = INIT_3C[(count * 4) +: 4]; + mem[64 * 61 + count] = INIT_3D[(count * 4) +: 4]; + mem[64 * 62 + count] = INIT_3E[(count * 4) +: 4]; + mem[64 * 63 + count] = INIT_3F[(count * 4) +: 4]; + end + + + change_clka <= 0; + change_clkb <= 0; + data_collision <= 0; + data_collision_a_b <= 0; + data_collision_b_a <= 0; + memory_collision <= 0; + memory_collision_a_b <= 0; + memory_collision_b_a <= 0; + setup_all_a_b <= 0; + setup_all_b_a <= 0; + setup_zero <= 0; + setup_rf_a_b <= 0; + setup_rf_b_a <= 0; + end + + assign data_addra_int = addra_int * 2; + assign data_addra_reg = addra_reg * 2; + assign data_addrb_int = addrb_int * 4; + assign data_addrb_reg = addrb_reg * 4; + + + initial begin + + display_flag = 1; + output_flag = 1; + + case (SIM_COLLISION_CHECK) + + "NONE" : begin + output_flag = 0; + display_flag = 0; + end + "WARNING_ONLY" : output_flag = 0; + "GENERATE_X_ONLY" : display_flag = 0; + "ALL" : ; + + default : begin + $display("Attribute Syntax Error : The Attribute SIM_COLLISION_CHECK on RAMB16_S2_S4 instance %m is set to %s. Legal values for this attribute are ALL, NONE, WARNING_ONLY or GENERATE_X_ONLY.", SIM_COLLISION_CHECK); + $finish; + end + + endcase // case(SIM_COLLISION_CHECK) + + end // initial begin + + + always @(posedge clka_int) begin + if ((output_flag || display_flag)) begin + time_clka = $time; + #0 time_clkb_clka = time_clka - time_clkb; + change_clka = ~change_clka; + end + end + + always @(posedge clkb_int) begin + if ((output_flag || display_flag)) begin + time_clkb = $time; + #0 time_clka_clkb = time_clkb - time_clka; + change_clkb = ~change_clkb; + end + end + + always @(change_clkb) begin + if ((0 < time_clka_clkb) && (time_clka_clkb < SETUP_ALL)) + setup_all_a_b = 1; + if ((0 < time_clka_clkb) && (time_clka_clkb < SETUP_READ_FIRST)) + setup_rf_a_b = 1; + end + + always @(change_clka) begin + if ((0 < time_clkb_clka) && (time_clkb_clka < SETUP_ALL)) + setup_all_b_a = 1; + if ((0 < time_clkb_clka) && (time_clkb_clka < SETUP_READ_FIRST)) + setup_rf_b_a = 1; + end + + always @(change_clkb or change_clka) begin + if ((time_clkb_clka == 0) && (time_clka_clkb == 0)) + setup_zero = 1; + end + + always @(posedge setup_zero) begin + if ((ena_int == 1) && (wea_int == 1) && + (enb_int == 1) && (web_int == 1) && + (data_addra_int[14:2] == data_addrb_int[14:2])) + memory_collision <= 1; + end + + always @(posedge setup_all_a_b or posedge setup_rf_a_b) begin + if ((ena_reg == 1) && (wea_reg == 1) && + (enb_int == 1) && (web_int == 1) && + (data_addra_reg[14:2] == data_addrb_int[14:2])) + memory_collision_a_b <= 1; + end + + always @(posedge setup_all_b_a or posedge setup_rf_b_a) begin + if ((ena_int == 1) && (wea_int == 1) && + (enb_reg == 1) && (web_reg == 1) && + (data_addra_int[14:2] == data_addrb_reg[14:2])) + memory_collision_b_a <= 1; + end + + always @(posedge setup_all_a_b) begin + if (data_addra_reg[14:2] == data_addrb_int[14:2]) begin + if ((ena_reg == 1) && (enb_int == 1)) begin + case ({wr_mode_a, wr_mode_b, wea_reg, web_int}) + 6'b000011 : begin data_collision_a_b <= 2'b11; display_wa_wb; end + 6'b000111 : begin data_collision_a_b <= 2'b11; display_wa_wb; end + 6'b001011 : begin data_collision_a_b <= 2'b10; display_wa_wb; end +// 6'b010011 : begin data_collision_a_b <= 2'b00; display_wa_wb; end +// 6'b010111 : begin data_collision_a_b <= 2'b00; display_wa_wb; end +// 6'b011011 : begin data_collision_a_b <= 2'b00; display_wa_wb; end + 6'b100011 : begin data_collision_a_b <= 2'b01; display_wa_wb; end + 6'b100111 : begin data_collision_a_b <= 2'b01; display_wa_wb; end + 6'b101011 : begin display_wa_wb; end + 6'b000001 : begin data_collision_a_b <= 2'b10; display_ra_wb; end +// 6'b000101 : begin data_collision_a_b <= 2'b00; display_ra_wb; end + 6'b001001 : begin data_collision_a_b <= 2'b10; display_ra_wb; end + 6'b010001 : begin data_collision_a_b <= 2'b10; display_ra_wb; end +// 6'b010101 : begin data_collision_a_b <= 2'b00; display_ra_wb; end + 6'b011001 : begin data_collision_a_b <= 2'b10; display_ra_wb; end + 6'b100001 : begin data_collision_a_b <= 2'b10; display_ra_wb; end +// 6'b100101 : begin data_collision_a_b <= 2'b00; display_ra_wb; end + 6'b101001 : begin data_collision_a_b <= 2'b10; display_ra_wb; end + 6'b000010 : begin data_collision_a_b <= 2'b01; display_wa_rb; end + 6'b000110 : begin data_collision_a_b <= 2'b01; display_wa_rb; end + 6'b001010 : begin data_collision_a_b <= 2'b01; display_wa_rb; end +// 6'b010010 : begin data_collision_a_b <= 2'b00; display_wa_rb; end +// 6'b010110 : begin data_collision_a_b <= 2'b00; display_wa_rb; end +// 6'b011010 : begin data_collision_a_b <= 2'b00; display_wa_rb; end + 6'b100010 : begin data_collision_a_b <= 2'b01; display_wa_rb; end + 6'b100110 : begin data_collision_a_b <= 2'b01; display_wa_rb; end + 6'b101010 : begin data_collision_a_b <= 2'b01; display_wa_rb; end + endcase + end + end + setup_all_a_b <= 0; + end + + + always @(posedge setup_all_b_a) begin + if (data_addra_int[14:2] == data_addrb_reg[14:2]) begin + if ((ena_int == 1) && (enb_reg == 1)) begin + case ({wr_mode_a, wr_mode_b, wea_int, web_reg}) + 6'b000011 : begin data_collision_b_a <= 2'b11; display_wa_wb; end +// 6'b000111 : begin data_collision_b_a <= 2'b00; display_wa_wb; end + 6'b001011 : begin data_collision_b_a <= 2'b10; display_wa_wb; end + 6'b010011 : begin data_collision_b_a <= 2'b11; display_wa_wb; end +// 6'b010111 : begin data_collision_b_a <= 2'b00; display_wa_wb; end + 6'b011011 : begin data_collision_b_a <= 2'b10; display_wa_wb; end + 6'b100011 : begin data_collision_b_a <= 2'b01; display_wa_wb; end + 6'b100111 : begin data_collision_b_a <= 2'b01; display_wa_wb; end + 6'b101011 : begin display_wa_wb; end + 6'b000001 : begin data_collision_b_a <= 2'b10; display_ra_wb; end + 6'b000101 : begin data_collision_b_a <= 2'b10; display_ra_wb; end + 6'b001001 : begin data_collision_b_a <= 2'b10; display_ra_wb; end + 6'b010001 : begin data_collision_b_a <= 2'b10; display_ra_wb; end + 6'b010101 : begin data_collision_b_a <= 2'b10; display_ra_wb; end + 6'b011001 : begin data_collision_b_a <= 2'b10; display_ra_wb; end + 6'b100001 : begin data_collision_b_a <= 2'b10; display_ra_wb; end + 6'b100101 : begin data_collision_b_a <= 2'b10; display_ra_wb; end + 6'b101001 : begin data_collision_b_a <= 2'b10; display_ra_wb; end + 6'b000010 : begin data_collision_b_a <= 2'b01; display_wa_rb; end + 6'b000110 : begin data_collision_b_a <= 2'b01; display_wa_rb; end + 6'b001010 : begin data_collision_b_a <= 2'b01; display_wa_rb; end +// 6'b010010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end +// 6'b010110 : begin data_collision_b_a <= 2'b00; display_wa_rb; end +// 6'b011010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end + 6'b100010 : begin data_collision_b_a <= 2'b01; display_wa_rb; end + 6'b100110 : begin data_collision_b_a <= 2'b01; display_wa_rb; end + 6'b101010 : begin data_collision_b_a <= 2'b01; display_wa_rb; end + endcase + end + end + setup_all_b_a <= 0; + end + + + always @(posedge setup_zero) begin + if (data_addra_int[14:2] == data_addrb_int[14:2]) begin + if ((ena_int == 1) && (enb_int == 1)) begin + case ({wr_mode_a, wr_mode_b, wea_int, web_int}) + 6'b000011 : begin data_collision <= 2'b11; display_wa_wb; end + 6'b000111 : begin data_collision <= 2'b11; display_wa_wb; end + 6'b001011 : begin data_collision <= 2'b10; display_wa_wb; end + 6'b010011 : begin data_collision <= 2'b11; display_wa_wb; end + 6'b010111 : begin data_collision <= 2'b11; display_wa_wb; end + 6'b011011 : begin data_collision <= 2'b10; display_wa_wb; end + 6'b100011 : begin data_collision <= 2'b01; display_wa_wb; end + 6'b100111 : begin data_collision <= 2'b01; display_wa_wb; end + 6'b101011 : begin display_wa_wb; end + 6'b000001 : begin data_collision <= 2'b10; display_ra_wb; end +// 6'b000101 : begin data_collision <= 2'b00; display_ra_wb; end + 6'b001001 : begin data_collision <= 2'b10; display_ra_wb; end + 6'b010001 : begin data_collision <= 2'b10; display_ra_wb; end +// 6'b010101 : begin data_collision <= 2'b00; display_ra_wb; end + 6'b011001 : begin data_collision <= 2'b10; display_ra_wb; end + 6'b100001 : begin data_collision <= 2'b10; display_ra_wb; end +// 6'b100101 : begin data_collision <= 2'b00; display_ra_wb; end + 6'b101001 : begin data_collision <= 2'b10; display_ra_wb; end + 6'b000010 : begin data_collision <= 2'b01; display_wa_rb; end + 6'b000110 : begin data_collision <= 2'b01; display_wa_rb; end + 6'b001010 : begin data_collision <= 2'b01; display_wa_rb; end +// 6'b010010 : begin data_collision <= 2'b00; display_wa_rb; end +// 6'b010110 : begin data_collision <= 2'b00; display_wa_rb; end +// 6'b011010 : begin data_collision <= 2'b00; display_wa_rb; end + 6'b100010 : begin data_collision <= 2'b01; display_wa_rb; end + 6'b100110 : begin data_collision <= 2'b01; display_wa_rb; end + 6'b101010 : begin data_collision <= 2'b01; display_wa_rb; end + endcase + end + end + setup_zero <= 0; + end + + task display_ra_wb; + begin + if (display_flag) + $display("Memory Collision Error on RAMB16_S2_S4:%m at simulation time %.3f ns\nA read was performed on address %h (hex) of Port A while a write was requested to the same address on Port B. The write will be successful however the read value on Port A is unknown until the next CLKA cycle.", $time/1000.0, addra_int); + end + endtask + + task display_wa_rb; + begin + if (display_flag) + $display("Memory Collision Error on RAMB16_S2_S4:%m at simulation time %.3f ns\nA read was performed on address %h (hex) of Port B while a write was requested to the same address on Port A. The write will be successful however the read value on Port B is unknown until the next CLKB cycle.", $time/1000.0, addrb_int); + end + endtask + + task display_wa_wb; + begin + if (display_flag) + $display("Memory Collision Error on RAMB16_S2_S4:%m at simulation time %.3f ns\nA write was requested to the same address simultaneously at both Port A and Port B of the RAM. The contents written to the RAM at address location %h (hex) of Port A and address location %h (hex) of Port B are unknown.", $time/1000.0, addra_int, addrb_int); + end + endtask + + + always @(posedge setup_rf_a_b) begin + if (data_addra_reg[14:2] == data_addrb_int[14:2]) begin + if ((ena_reg == 1) && (enb_int == 1)) begin + case ({wr_mode_a, wr_mode_b, wea_reg, web_int}) +// 6'b000011 : begin data_collision_a_b <= 2'b00; display_wa_wb; end +// 6'b000111 : begin data_collision_a_b <= 2'b00; display_wa_wb; end +// 6'b001011 : begin data_collision_a_b <= 2'b00; display_wa_wb; end + 6'b010011 : begin data_collision_a_b <= 2'b11; display_wa_wb; end + 6'b010111 : begin data_collision_a_b <= 2'b11; display_wa_wb; end + 6'b011011 : begin data_collision_a_b <= 2'b10; display_wa_wb; end +// 6'b100011 : begin data_collision_a_b <= 2'b00; display_wa_wb; end +// 6'b100111 : begin data_collision_a_b <= 2'b00; display_wa_wb; end +// 6'b101011 : begin data_collision_a_b <= 2'b00; display_wa_wb; end +// 6'b000001 : begin data_collision_a_b <= 2'b00; display_ra_wb; end +// 6'b000101 : begin data_collision_a_b <= 2'b00; display_ra_wb; end +// 6'b001001 : begin data_collision_a_b <= 2'b00; display_ra_wb; end +// 6'b010001 : begin data_collision_a_b <= 2'b00; display_ra_wb; end +// 6'b010101 : begin data_collision_a_b <= 2'b00; display_ra_wb; end +// 6'b011001 : begin data_collision_a_b <= 2'b00; display_ra_wb; end +// 6'b100001 : begin data_collision_a_b <= 2'b00; display_ra_wb; end +// 6'b100101 : begin data_collision_a_b <= 2'b00; display_ra_wb; end +// 6'b101001 : begin data_collision_a_b <= 2'b00; display_ra_wb; end +// 6'b000010 : begin data_collision_a_b <= 2'b00; display_wa_rb; end +// 6'b000110 : begin data_collision_a_b <= 2'b00; display_wa_rb; end +// 6'b001010 : begin data_collision_a_b <= 2'b00; display_wa_rb; end + 6'b010010 : begin data_collision_a_b <= 2'b01; display_wa_rb; end + 6'b010110 : begin data_collision_a_b <= 2'b01; display_wa_rb; end + 6'b011010 : begin data_collision_a_b <= 2'b01; display_wa_rb; end +// 6'b100010 : begin data_collision_a_b <= 2'b00; display_wa_rb; end +// 6'b100110 : begin data_collision_a_b <= 2'b00; display_wa_rb; end +// 6'b101010 : begin data_collision_a_b <= 2'b00; display_wa_rb; end + endcase + end + end + setup_rf_a_b <= 0; + end + + + always @(posedge setup_rf_b_a) begin + if (data_addra_int[14:2] == data_addrb_reg[14:2]) begin + if ((ena_int == 1) && (enb_reg == 1)) begin + case ({wr_mode_a, wr_mode_b, wea_int, web_reg}) +// 6'b000011 : begin data_collision_b_a <= 2'b00; display_wa_wb; end + 6'b000111 : begin data_collision_b_a <= 2'b11; display_wa_wb; end +// 6'b001011 : begin data_collision_b_a <= 2'b00; display_wa_wb; end +// 6'b010011 : begin data_collision_b_a <= 2'b00; display_wa_wb; end + 6'b010111 : begin data_collision_b_a <= 2'b11; display_wa_wb; end +// 6'b011011 : begin data_collision_b_a <= 2'b00; display_wa_wb; end +// 6'b100011 : begin data_collision_b_a <= 2'b00; display_wa_wb; end + 6'b100111 : begin data_collision_b_a <= 2'b01; display_wa_wb; end +// 6'b101011 : begin data_collision_b_a <= 2'b00; display_wa_wb; end +// 6'b000001 : begin data_collision_b_a <= 2'b00; display_ra_wb; end + 6'b000101 : begin data_collision_b_a <= 2'b10; display_ra_wb; end +// 6'b001001 : begin data_collision_b_a <= 2'b00; display_ra_wb; end +// 6'b010001 : begin data_collision_b_a <= 2'b00; display_ra_wb; end + 6'b010101 : begin data_collision_b_a <= 2'b10; display_ra_wb; end +// 6'b011001 : begin data_collision_b_a <= 2'b00; display_ra_wb; end +// 6'b100001 : begin data_collision_b_a <= 2'b00; display_ra_wb; end + 6'b100101 : begin data_collision_b_a <= 2'b10; display_ra_wb; end +// 6'b101001 : begin data_collision_b_a <= 2'b00; display_ra_wb; end +// 6'b000010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end +// 6'b000110 : begin data_collision_b_a <= 2'b00; display_wa_rb; end +// 6'b001010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end +// 6'b010010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end +// 6'b010110 : begin data_collision_b_a <= 2'b00; display_wa_rb; end +// 6'b011010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end +// 6'b100010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end +// 6'b100110 : begin data_collision_b_a <= 2'b00; display_wa_rb; end +// 6'b101010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end + endcase + end + end + setup_rf_b_a <= 0; + end + + + always @(posedge clka_int) begin + if ((output_flag || display_flag)) begin + addra_reg <= addra_int; + ena_reg <= ena_int; + ssra_reg <= ssra_int; + wea_reg <= wea_int; + end + end + + always @(posedge clkb_int) begin + if ((output_flag || display_flag)) begin + addrb_reg <= addrb_int; + enb_reg <= enb_int; + ssrb_reg <= ssrb_int; + web_reg <= web_int; + end + end + + + // Data + always @(posedge memory_collision) begin + if ((output_flag || display_flag)) begin + mem[addra_int[12:1]][addra_int[0:0] * 2 +: 2] <= 2'bx; + memory_collision <= 0; + end + + end + + always @(posedge memory_collision_a_b) begin + if ((output_flag || display_flag)) begin + mem[addra_reg[12:1]][addra_reg[0:0] * 2 +: 2] <= 2'bx; + memory_collision_a_b <= 0; + end + end + + always @(posedge memory_collision_b_a) begin + if ((output_flag || display_flag)) begin + mem[addra_int[12:1]][addra_int[0:0] * 2 +: 2] <= 2'bx; + memory_collision_b_a <= 0; + end + end + + always @(posedge data_collision[1]) begin + if (ssra_int == 0 && output_flag) begin + doa_out <= #100 2'bX; + end + data_collision[1] <= 0; + end + + always @(posedge data_collision[0]) begin + if (ssrb_int == 0 && output_flag) begin + dob_out[addra_int[0:0] * 2 +: 2] <= #100 2'bX; + end + data_collision[0] <= 0; + end + + always @(posedge data_collision_a_b[1]) begin + if (ssra_reg == 0 && output_flag) begin + doa_out <= #100 2'bX; + end + data_collision_a_b[1] <= 0; + end + + always @(posedge data_collision_a_b[0]) begin + if (ssrb_int == 0 && output_flag) begin + dob_out[addra_reg[0:0] * 2 +: 2] <= #100 2'bX; + end + data_collision_a_b[0] <= 0; + end + + always @(posedge data_collision_b_a[1]) begin + if (ssra_int == 0 && output_flag) begin + doa_out <= #100 2'bX; + end + data_collision_b_a[1] <= 0; + end + + always @(posedge data_collision_b_a[0]) begin + if (ssrb_reg == 0 && output_flag) begin + dob_out[addra_int[0:0] * 2 +: 2] <= #100 2'bX; + end + data_collision_b_a[0] <= 0; + end + + + initial begin + case (WRITE_MODE_A) + "WRITE_FIRST" : wr_mode_a <= 2'b00; + "READ_FIRST" : wr_mode_a <= 2'b01; + "NO_CHANGE" : wr_mode_a <= 2'b10; + default : begin + $display("Attribute Syntax Error : The Attribute WRITE_MODE_A on RAMB16_S2_S4 instance %m is set to %s. Legal values for this attribute are WRITE_FIRST, READ_FIRST or NO_CHANGE.", WRITE_MODE_A); + $finish; + end + endcase + end + + initial begin + case (WRITE_MODE_B) + "WRITE_FIRST" : wr_mode_b <= 2'b00; + "READ_FIRST" : wr_mode_b <= 2'b01; + "NO_CHANGE" : wr_mode_b <= 2'b10; + default : begin + $display("Attribute Syntax Error : The Attribute WRITE_MODE_B on RAMB16_S2_S4 instance %m is set to %s. Legal values for this attribute are WRITE_FIRST, READ_FIRST or NO_CHANGE.", WRITE_MODE_B); + $finish; + end + endcase + end + + + // Port A + always @(posedge clka_int) begin + + if (ena_int == 1'b1) begin + + if (ssra_int == 1'b1) begin + {doa_out} <= #100 SRVAL_A; + end + else begin + if (wea_int == 1'b1) begin + if (wr_mode_a == 2'b00) begin + doa_out <= #100 dia_int; + end + else if (wr_mode_a == 2'b01) begin + + doa_out <= #100 mem[addra_int[12:1]][addra_int[0:0] * 2 +: 2]; + + end + end + else begin + + doa_out <= #100 mem[addra_int[12:1]][addra_int[0:0] * 2 +: 2]; + + end + end + + // memory + if (wea_int == 1'b1) begin + mem[addra_int[12:1]][addra_int[0:0] * 2 +: 2] <= dia_int; + end + + end + end + + + // Port B + always @(posedge clkb_int) begin + + if (enb_int == 1'b1) begin + + if (ssrb_int == 1'b1) begin + {dob_out} <= #100 SRVAL_B; + end + else begin + if (web_int == 1'b1) begin + if (wr_mode_b == 2'b00) begin + dob_out <= #100 dib_int; + end + else if (wr_mode_b == 2'b01) begin + dob_out <= #100 mem[addrb_int]; + end + end + else begin + dob_out <= #100 mem[addrb_int]; + end + end + + // memory + if (web_int == 1'b1) begin + mem[addrb_int] <= dib_int; + end + + end + end + + +endmodule + +`endif diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/RAMB16_S2_S9.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/RAMB16_S2_S9.v new file mode 100644 index 0000000..514427f --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/RAMB16_S2_S9.v @@ -0,0 +1,1648 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/RAMB16_S2_S9.v,v 1.10 2007/02/22 01:58:06 wloo Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2005 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / 16K-Bit Data and 2K-Bit Parity Dual Port Block RAM +// /___/ /\ Filename : RAMB16_S2_S9.v +// \ \ / \ Timestamp : Thu Mar 10 16:43:36 PST 2005 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// End Revision + +`ifdef legacy_model + +`timescale 1 ps / 1 ps + +module RAMB16_S2_S9 (DOA, DOB, DOPB, ADDRA, ADDRB, CLKA, CLKB, DIA, DIB, DIPB, ENA, ENB, SSRA, SSRB, WEA, WEB); + + parameter INIT_A = 2'h0; + parameter INIT_B = 9'h0; + parameter SRVAL_A = 2'h0; + parameter SRVAL_B = 9'h0; + parameter WRITE_MODE_A = "WRITE_FIRST"; + parameter WRITE_MODE_B = "WRITE_FIRST"; + parameter SIM_COLLISION_CHECK = "ALL"; + localparam SETUP_ALL = 1000; + localparam SETUP_READ_FIRST = 3000; + + parameter INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + + output [1:0] DOA; + reg [1:0] doa_out; + wire doa_out0, doa_out1; + + input [12:0] ADDRA; + input [1:0] DIA; + input ENA, CLKA, WEA, SSRA; + + output [7:0] DOB; + output [0:0] DOPB; + reg [7:0] dob_out; + reg [0:0] dopb_out; + wire dob_out0, dob_out1, dob_out2, dob_out3, dob_out4, dob_out5, dob_out6, dob_out7; + wire dopb0_out; + + input [10:0] ADDRB; + input [7:0] DIB; + input [0:0] DIPB; + input ENB, CLKB, WEB, SSRB; + + reg [18431:0] mem; + reg [8:0] count; + reg [1:0] wr_mode_a, wr_mode_b; + + reg [5:0] dmi, dbi; + reg [5:0] pmi, pbi; + + wire [12:0] addra_int; + reg [12:0] addra_reg; + wire [1:0] dia_int; + wire ena_int, clka_int, wea_int, ssra_int; + reg ena_reg, wea_reg, ssra_reg; + wire [10:0] addrb_int; + reg [10:0] addrb_reg; + wire [7:0] dib_int; + wire [0:0] dipb_int; + wire enb_int, clkb_int, web_int, ssrb_int; + reg display_flag; + reg enb_reg, web_reg, ssrb_reg; + + time time_clka, time_clkb; + time time_clka_clkb; + time time_clkb_clka; + + reg setup_all_a_b; + reg setup_all_b_a; + reg setup_zero; + reg setup_rf_a_b; + reg setup_rf_b_a; + reg [1:0] data_collision, data_collision_a_b, data_collision_b_a; + reg memory_collision, memory_collision_a_b, memory_collision_b_a; + reg address_collision, address_collision_a_b, address_collision_b_a; + reg change_clka; + reg change_clkb; + + wire [14:0] data_addra_int; + wire [14:0] data_addra_reg; + wire [14:0] data_addrb_int; + wire [14:0] data_addrb_reg; + wire [15:0] parity_addra_int; + wire [15:0] parity_addra_reg; + wire [15:0] parity_addrb_int; + wire [15:0] parity_addrb_reg; + + tri0 GSR = glbl.GSR; + + always @(GSR) + if (GSR) begin + assign doa_out = INIT_A[1:0]; + assign dob_out = INIT_B[7:0]; + assign dopb_out = INIT_B[8:8]; + end + else begin + deassign doa_out; + deassign dob_out; + deassign dopb_out; + end + + buf b_doa_out0 (doa_out0, doa_out[0]); + buf b_doa_out1 (doa_out1, doa_out[1]); + buf b_dob_out0 (dob_out0, dob_out[0]); + buf b_dob_out1 (dob_out1, dob_out[1]); + buf b_dob_out2 (dob_out2, dob_out[2]); + buf b_dob_out3 (dob_out3, dob_out[3]); + buf b_dob_out4 (dob_out4, dob_out[4]); + buf b_dob_out5 (dob_out5, dob_out[5]); + buf b_dob_out6 (dob_out6, dob_out[6]); + buf b_dob_out7 (dob_out7, dob_out[7]); + buf b_dopb_out0 (dopb_out0, dopb_out[0]); + + buf b_doa0 (DOA[0], doa_out0); + buf b_doa1 (DOA[1], doa_out1); + buf b_dob0 (DOB[0], dob_out0); + buf b_dob1 (DOB[1], dob_out1); + buf b_dob2 (DOB[2], dob_out2); + buf b_dob3 (DOB[3], dob_out3); + buf b_dob4 (DOB[4], dob_out4); + buf b_dob5 (DOB[5], dob_out5); + buf b_dob6 (DOB[6], dob_out6); + buf b_dob7 (DOB[7], dob_out7); + buf b_dopb0 (DOPB[0], dopb_out0); + + buf b_addra_0 (addra_int[0], ADDRA[0]); + buf b_addra_1 (addra_int[1], ADDRA[1]); + buf b_addra_2 (addra_int[2], ADDRA[2]); + buf b_addra_3 (addra_int[3], ADDRA[3]); + buf b_addra_4 (addra_int[4], ADDRA[4]); + buf b_addra_5 (addra_int[5], ADDRA[5]); + buf b_addra_6 (addra_int[6], ADDRA[6]); + buf b_addra_7 (addra_int[7], ADDRA[7]); + buf b_addra_8 (addra_int[8], ADDRA[8]); + buf b_addra_9 (addra_int[9], ADDRA[9]); + buf b_addra_10 (addra_int[10], ADDRA[10]); + buf b_addra_11 (addra_int[11], ADDRA[11]); + buf b_addra_12 (addra_int[12], ADDRA[12]); + buf b_dia_0 (dia_int[0], DIA[0]); + buf b_dia_1 (dia_int[1], DIA[1]); + buf b_ena (ena_int, ENA); + buf b_clka (clka_int, CLKA); + buf b_ssra (ssra_int, SSRA); + buf b_wea (wea_int, WEA); + buf b_addrb_0 (addrb_int[0], ADDRB[0]); + buf b_addrb_1 (addrb_int[1], ADDRB[1]); + buf b_addrb_2 (addrb_int[2], ADDRB[2]); + buf b_addrb_3 (addrb_int[3], ADDRB[3]); + buf b_addrb_4 (addrb_int[4], ADDRB[4]); + buf b_addrb_5 (addrb_int[5], ADDRB[5]); + buf b_addrb_6 (addrb_int[6], ADDRB[6]); + buf b_addrb_7 (addrb_int[7], ADDRB[7]); + buf b_addrb_8 (addrb_int[8], ADDRB[8]); + buf b_addrb_9 (addrb_int[9], ADDRB[9]); + buf b_addrb_10 (addrb_int[10], ADDRB[10]); + buf b_dib_0 (dib_int[0], DIB[0]); + buf b_dib_1 (dib_int[1], DIB[1]); + buf b_dib_2 (dib_int[2], DIB[2]); + buf b_dib_3 (dib_int[3], DIB[3]); + buf b_dib_4 (dib_int[4], DIB[4]); + buf b_dib_5 (dib_int[5], DIB[5]); + buf b_dib_6 (dib_int[6], DIB[6]); + buf b_dib_7 (dib_int[7], DIB[7]); + buf b_dipb_0 (dipb_int[0], DIPB[0]); + buf b_enb (enb_int, ENB); + buf b_clkb (clkb_int, CLKB); + buf b_ssrb (ssrb_int, SSRB); + buf b_web (web_int, WEB); + + initial begin + for (count = 0; count < 256; count = count + 1) begin + mem[count] <= INIT_00[count]; + mem[256 * 1 + count] <= INIT_01[count]; + mem[256 * 2 + count] <= INIT_02[count]; + mem[256 * 3 + count] <= INIT_03[count]; + mem[256 * 4 + count] <= INIT_04[count]; + mem[256 * 5 + count] <= INIT_05[count]; + mem[256 * 6 + count] <= INIT_06[count]; + mem[256 * 7 + count] <= INIT_07[count]; + mem[256 * 8 + count] <= INIT_08[count]; + mem[256 * 9 + count] <= INIT_09[count]; + mem[256 * 10 + count] <= INIT_0A[count]; + mem[256 * 11 + count] <= INIT_0B[count]; + mem[256 * 12 + count] <= INIT_0C[count]; + mem[256 * 13 + count] <= INIT_0D[count]; + mem[256 * 14 + count] <= INIT_0E[count]; + mem[256 * 15 + count] <= INIT_0F[count]; + mem[256 * 16 + count] <= INIT_10[count]; + mem[256 * 17 + count] <= INIT_11[count]; + mem[256 * 18 + count] <= INIT_12[count]; + mem[256 * 19 + count] <= INIT_13[count]; + mem[256 * 20 + count] <= INIT_14[count]; + mem[256 * 21 + count] <= INIT_15[count]; + mem[256 * 22 + count] <= INIT_16[count]; + mem[256 * 23 + count] <= INIT_17[count]; + mem[256 * 24 + count] <= INIT_18[count]; + mem[256 * 25 + count] <= INIT_19[count]; + mem[256 * 26 + count] <= INIT_1A[count]; + mem[256 * 27 + count] <= INIT_1B[count]; + mem[256 * 28 + count] <= INIT_1C[count]; + mem[256 * 29 + count] <= INIT_1D[count]; + mem[256 * 30 + count] <= INIT_1E[count]; + mem[256 * 31 + count] <= INIT_1F[count]; + mem[256 * 32 + count] <= INIT_20[count]; + mem[256 * 33 + count] <= INIT_21[count]; + mem[256 * 34 + count] <= INIT_22[count]; + mem[256 * 35 + count] <= INIT_23[count]; + mem[256 * 36 + count] <= INIT_24[count]; + mem[256 * 37 + count] <= INIT_25[count]; + mem[256 * 38 + count] <= INIT_26[count]; + mem[256 * 39 + count] <= INIT_27[count]; + mem[256 * 40 + count] <= INIT_28[count]; + mem[256 * 41 + count] <= INIT_29[count]; + mem[256 * 42 + count] <= INIT_2A[count]; + mem[256 * 43 + count] <= INIT_2B[count]; + mem[256 * 44 + count] <= INIT_2C[count]; + mem[256 * 45 + count] <= INIT_2D[count]; + mem[256 * 46 + count] <= INIT_2E[count]; + mem[256 * 47 + count] <= INIT_2F[count]; + mem[256 * 48 + count] <= INIT_30[count]; + mem[256 * 49 + count] <= INIT_31[count]; + mem[256 * 50 + count] <= INIT_32[count]; + mem[256 * 51 + count] <= INIT_33[count]; + mem[256 * 52 + count] <= INIT_34[count]; + mem[256 * 53 + count] <= INIT_35[count]; + mem[256 * 54 + count] <= INIT_36[count]; + mem[256 * 55 + count] <= INIT_37[count]; + mem[256 * 56 + count] <= INIT_38[count]; + mem[256 * 57 + count] <= INIT_39[count]; + mem[256 * 58 + count] <= INIT_3A[count]; + mem[256 * 59 + count] <= INIT_3B[count]; + mem[256 * 60 + count] <= INIT_3C[count]; + mem[256 * 61 + count] <= INIT_3D[count]; + mem[256 * 62 + count] <= INIT_3E[count]; + mem[256 * 63 + count] <= INIT_3F[count]; + mem[256 * 64 + count] <= INITP_00[count]; + mem[256 * 65 + count] <= INITP_01[count]; + mem[256 * 66 + count] <= INITP_02[count]; + mem[256 * 67 + count] <= INITP_03[count]; + mem[256 * 68 + count] <= INITP_04[count]; + mem[256 * 69 + count] <= INITP_05[count]; + mem[256 * 70 + count] <= INITP_06[count]; + mem[256 * 71 + count] <= INITP_07[count]; + end + address_collision <= 0; + address_collision_a_b <= 0; + address_collision_b_a <= 0; + change_clka <= 0; + change_clkb <= 0; + data_collision <= 0; + data_collision_a_b <= 0; + data_collision_b_a <= 0; + memory_collision <= 0; + memory_collision_a_b <= 0; + memory_collision_b_a <= 0; + setup_all_a_b <= 0; + setup_all_b_a <= 0; + setup_zero <= 0; + setup_rf_a_b <= 0; + setup_rf_b_a <= 0; + end + + assign data_addra_int = addra_int * 2; + assign data_addra_reg = addra_reg * 2; + assign data_addrb_int = addrb_int * 8; + assign data_addrb_reg = addrb_reg * 8; + assign parity_addrb_int = 16384 + addrb_int * 1; + assign parity_addrb_reg = 16384 + addrb_reg * 1; + + + initial begin + + display_flag = 1; + + case (SIM_COLLISION_CHECK) + + "NONE" : begin + assign setup_all_a_b = 1'b0; + assign setup_all_b_a = 1'b0; + assign setup_zero = 1'b0; + assign setup_rf_a_b = 1'b0; + assign setup_rf_b_a = 1'b0; + assign display_flag = 0; + end + "WARNING_ONLY" : begin + assign data_collision = 2'b00; + assign data_collision_a_b = 2'b00; + assign data_collision_b_a = 2'b00; + assign memory_collision = 1'b0; + assign memory_collision_a_b = 1'b0; + assign memory_collision_b_a = 1'b0; + end + "GENERATE_X_ONLY" : begin + assign display_flag = 0; + end + "ALL" : ; + default : begin + $display("Attribute Syntax Error : The Attribute SIM_COLLISION_CHECK on RAMB16_S2_S9 instance %m is set to %s. Legal values for this attribute are ALL, NONE, WARNING_ONLY or GENERATE_X_ONLY.", SIM_COLLISION_CHECK); + $finish; + end + + endcase // case(SIM_COLLISION_CHECK) + + end // initial begin + + + always @(posedge clka_int) begin + time_clka = $time; + #0 time_clkb_clka = time_clka - time_clkb; + change_clka = ~change_clka; + end + + always @(posedge clkb_int) begin + time_clkb = $time; + #0 time_clka_clkb = time_clkb - time_clka; + change_clkb = ~change_clkb; + end + + always @(change_clkb) begin + if ((0 < time_clka_clkb) && (time_clka_clkb < SETUP_ALL)) + setup_all_a_b = 1; + if ((0 < time_clka_clkb) && (time_clka_clkb < SETUP_READ_FIRST)) + setup_rf_a_b = 1; + end + + always @(change_clka) begin + if ((0 < time_clkb_clka) && (time_clkb_clka < SETUP_ALL)) + setup_all_b_a = 1; + if ((0 < time_clkb_clka) && (time_clkb_clka < SETUP_READ_FIRST)) + setup_rf_b_a = 1; + end + + always @(change_clkb or change_clka) begin + if ((time_clkb_clka == 0) && (time_clka_clkb == 0)) + setup_zero = 1; + end + + always @(posedge setup_zero) begin + if ((ena_int == 1) && (wea_int == 1) && + (enb_int == 1) && (web_int == 1) && + (data_addra_int[14:3] == data_addrb_int[14:3])) + memory_collision <= 1; + end + + always @(posedge setup_all_a_b or posedge setup_rf_a_b) begin + if ((ena_reg == 1) && (wea_reg == 1) && + (enb_int == 1) && (web_int == 1) && + (data_addra_reg[14:3] == data_addrb_int[14:3])) + memory_collision_a_b <= 1; + end + + always @(posedge setup_all_b_a or posedge setup_rf_b_a) begin + if ((ena_int == 1) && (wea_int == 1) && + (enb_reg == 1) && (web_reg == 1) && + (data_addra_int[14:3] == data_addrb_reg[14:3])) + memory_collision_b_a <= 1; + end + + always @(posedge setup_all_a_b) begin + if (data_addra_reg[14:3] == data_addrb_int[14:3]) begin + if ((ena_reg == 1) && (enb_int == 1)) begin + case ({wr_mode_a, wr_mode_b, wea_reg, web_int}) + 6'b000011 : begin data_collision_a_b <= 2'b11; display_wa_wb; end + 6'b000111 : begin data_collision_a_b <= 2'b11; display_wa_wb; end + 6'b001011 : begin data_collision_a_b <= 2'b10; display_wa_wb; end +// 6'b010011 : begin data_collision_a_b <= 2'b00; display_wa_wb; end +// 6'b010111 : begin data_collision_a_b <= 2'b00; display_wa_wb; end +// 6'b011011 : begin data_collision_a_b <= 2'b00; display_wa_wb; end + 6'b100011 : begin data_collision_a_b <= 2'b01; display_wa_wb; end + 6'b100111 : begin data_collision_a_b <= 2'b01; display_wa_wb; end + 6'b101011 : begin display_wa_wb; end + 6'b000001 : begin data_collision_a_b <= 2'b10; display_ra_wb; end +// 6'b000101 : begin data_collision_a_b <= 2'b00; display_ra_wb; end + 6'b001001 : begin data_collision_a_b <= 2'b10; display_ra_wb; end + 6'b010001 : begin data_collision_a_b <= 2'b10; display_ra_wb; end +// 6'b010101 : begin data_collision_a_b <= 2'b00; display_ra_wb; end + 6'b011001 : begin data_collision_a_b <= 2'b10; display_ra_wb; end + 6'b100001 : begin data_collision_a_b <= 2'b10; display_ra_wb; end +// 6'b100101 : begin data_collision_a_b <= 2'b00; display_ra_wb; end + 6'b101001 : begin data_collision_a_b <= 2'b10; display_ra_wb; end + 6'b000010 : begin data_collision_a_b <= 2'b01; display_wa_rb; end + 6'b000110 : begin data_collision_a_b <= 2'b01; display_wa_rb; end + 6'b001010 : begin data_collision_a_b <= 2'b01; display_wa_rb; end +// 6'b010010 : begin data_collision_a_b <= 2'b00; display_wa_rb; end +// 6'b010110 : begin data_collision_a_b <= 2'b00; display_wa_rb; end +// 6'b011010 : begin data_collision_a_b <= 2'b00; display_wa_rb; end + 6'b100010 : begin data_collision_a_b <= 2'b01; display_wa_rb; end + 6'b100110 : begin data_collision_a_b <= 2'b01; display_wa_rb; end + 6'b101010 : begin data_collision_a_b <= 2'b01; display_wa_rb; end + endcase + end + end + setup_all_a_b <= 0; + end + + + always @(posedge setup_all_b_a) begin + if (data_addra_int[14:3] == data_addrb_reg[14:3]) begin + if ((ena_int == 1) && (enb_reg == 1)) begin + case ({wr_mode_a, wr_mode_b, wea_int, web_reg}) + 6'b000011 : begin data_collision_b_a <= 2'b11; display_wa_wb; end +// 6'b000111 : begin data_collision_b_a <= 2'b00; display_wa_wb; end + 6'b001011 : begin data_collision_b_a <= 2'b10; display_wa_wb; end + 6'b010011 : begin data_collision_b_a <= 2'b11; display_wa_wb; end +// 6'b010111 : begin data_collision_b_a <= 2'b00; display_wa_wb; end + 6'b011011 : begin data_collision_b_a <= 2'b10; display_wa_wb; end + 6'b100011 : begin data_collision_b_a <= 2'b01; display_wa_wb; end + 6'b100111 : begin data_collision_b_a <= 2'b01; display_wa_wb; end + 6'b101011 : begin display_wa_wb; end + 6'b000001 : begin data_collision_b_a <= 2'b10; display_ra_wb; end + 6'b000101 : begin data_collision_b_a <= 2'b10; display_ra_wb; end + 6'b001001 : begin data_collision_b_a <= 2'b10; display_ra_wb; end + 6'b010001 : begin data_collision_b_a <= 2'b10; display_ra_wb; end + 6'b010101 : begin data_collision_b_a <= 2'b10; display_ra_wb; end + 6'b011001 : begin data_collision_b_a <= 2'b10; display_ra_wb; end + 6'b100001 : begin data_collision_b_a <= 2'b10; display_ra_wb; end + 6'b100101 : begin data_collision_b_a <= 2'b10; display_ra_wb; end + 6'b101001 : begin data_collision_b_a <= 2'b10; display_ra_wb; end + 6'b000010 : begin data_collision_b_a <= 2'b01; display_wa_rb; end + 6'b000110 : begin data_collision_b_a <= 2'b01; display_wa_rb; end + 6'b001010 : begin data_collision_b_a <= 2'b01; display_wa_rb; end +// 6'b010010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end +// 6'b010110 : begin data_collision_b_a <= 2'b00; display_wa_rb; end +// 6'b011010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end + 6'b100010 : begin data_collision_b_a <= 2'b01; display_wa_rb; end + 6'b100110 : begin data_collision_b_a <= 2'b01; display_wa_rb; end + 6'b101010 : begin data_collision_b_a <= 2'b01; display_wa_rb; end + endcase + end + end + setup_all_b_a <= 0; + end + + + always @(posedge setup_zero) begin + if (data_addra_int[14:3] == data_addrb_int[14:3]) begin + if ((ena_int == 1) && (enb_int == 1)) begin + case ({wr_mode_a, wr_mode_b, wea_int, web_int}) + 6'b000011 : begin data_collision <= 2'b11; display_wa_wb; end + 6'b000111 : begin data_collision <= 2'b11; display_wa_wb; end + 6'b001011 : begin data_collision <= 2'b10; display_wa_wb; end + 6'b010011 : begin data_collision <= 2'b11; display_wa_wb; end + 6'b010111 : begin data_collision <= 2'b11; display_wa_wb; end + 6'b011011 : begin data_collision <= 2'b10; display_wa_wb; end + 6'b100011 : begin data_collision <= 2'b01; display_wa_wb; end + 6'b100111 : begin data_collision <= 2'b01; display_wa_wb; end + 6'b101011 : begin display_wa_wb; end + 6'b000001 : begin data_collision <= 2'b10; display_ra_wb; end +// 6'b000101 : begin data_collision <= 2'b00; display_ra_wb; end + 6'b001001 : begin data_collision <= 2'b10; display_ra_wb; end + 6'b010001 : begin data_collision <= 2'b10; display_ra_wb; end +// 6'b010101 : begin data_collision <= 2'b00; display_ra_wb; end + 6'b011001 : begin data_collision <= 2'b10; display_ra_wb; end + 6'b100001 : begin data_collision <= 2'b10; display_ra_wb; end +// 6'b100101 : begin data_collision <= 2'b00; display_ra_wb; end + 6'b101001 : begin data_collision <= 2'b10; display_ra_wb; end + 6'b000010 : begin data_collision <= 2'b01; display_wa_rb; end + 6'b000110 : begin data_collision <= 2'b01; display_wa_rb; end + 6'b001010 : begin data_collision <= 2'b01; display_wa_rb; end +// 6'b010010 : begin data_collision <= 2'b00; display_wa_rb; end +// 6'b010110 : begin data_collision <= 2'b00; display_wa_rb; end +// 6'b011010 : begin data_collision <= 2'b00; display_wa_rb; end + 6'b100010 : begin data_collision <= 2'b01; display_wa_rb; end + 6'b100110 : begin data_collision <= 2'b01; display_wa_rb; end + 6'b101010 : begin data_collision <= 2'b01; display_wa_rb; end + endcase + end + end + setup_zero <= 0; + end + + task display_ra_wb; + begin + if (display_flag) + $display("Memory Collision Error on RAMB16_S2_S9:%m at simulation time %.3f ns\nA read was performed on address %h (hex) of Port A while a write was requested to the same address on Port B. The write will be successful however the read value on Port A is unknown until the next CLKA cycle.", $time/1000.0, addra_int); + end + endtask + + task display_wa_rb; + begin + if (display_flag) + $display("Memory Collision Error on RAMB16_S2_S9:%m at simulation time %.3f ns\nA read was performed on address %h (hex) of Port B while a write was requested to the same address on Port A. The write will be successful however the read value on Port B is unknown until the next CLKB cycle.", $time/1000.0, addrb_int); + end + endtask + + task display_wa_wb; + begin + if (display_flag) + $display("Memory Collision Error on RAMB16_S2_S9:%m at simulation time %.3f ns\nA write was requested to the same address simultaneously at both Port A and Port B of the RAM. The contents written to the RAM at address location %h (hex) of Port A and address location %h (hex) of Port B are unknown.", $time/1000.0, addra_int, addrb_int); + end + endtask + + + always @(posedge setup_rf_a_b) begin + if (data_addra_reg[14:3] == data_addrb_int[14:3]) begin + if ((ena_reg == 1) && (enb_int == 1)) begin + case ({wr_mode_a, wr_mode_b, wea_reg, web_int}) +// 6'b000011 : begin data_collision_a_b <= 2'b00; display_wa_wb; end +// 6'b000111 : begin data_collision_a_b <= 2'b00; display_wa_wb; end +// 6'b001011 : begin data_collision_a_b <= 2'b00; display_wa_wb; end + 6'b010011 : begin data_collision_a_b <= 2'b11; display_wa_wb; end + 6'b010111 : begin data_collision_a_b <= 2'b11; display_wa_wb; end + 6'b011011 : begin data_collision_a_b <= 2'b10; display_wa_wb; end +// 6'b100011 : begin data_collision_a_b <= 2'b00; display_wa_wb; end +// 6'b100111 : begin data_collision_a_b <= 2'b00; display_wa_wb; end +// 6'b101011 : begin data_collision_a_b <= 2'b00; display_wa_wb; end +// 6'b000001 : begin data_collision_a_b <= 2'b00; display_ra_wb; end +// 6'b000101 : begin data_collision_a_b <= 2'b00; display_ra_wb; end +// 6'b001001 : begin data_collision_a_b <= 2'b00; display_ra_wb; end +// 6'b010001 : begin data_collision_a_b <= 2'b00; display_ra_wb; end +// 6'b010101 : begin data_collision_a_b <= 2'b00; display_ra_wb; end +// 6'b011001 : begin data_collision_a_b <= 2'b00; display_ra_wb; end +// 6'b100001 : begin data_collision_a_b <= 2'b00; display_ra_wb; end +// 6'b100101 : begin data_collision_a_b <= 2'b00; display_ra_wb; end +// 6'b101001 : begin data_collision_a_b <= 2'b00; display_ra_wb; end +// 6'b000010 : begin data_collision_a_b <= 2'b00; display_wa_rb; end +// 6'b000110 : begin data_collision_a_b <= 2'b00; display_wa_rb; end +// 6'b001010 : begin data_collision_a_b <= 2'b00; display_wa_rb; end + 6'b010010 : begin data_collision_a_b <= 2'b01; display_wa_rb; end + 6'b010110 : begin data_collision_a_b <= 2'b01; display_wa_rb; end + 6'b011010 : begin data_collision_a_b <= 2'b01; display_wa_rb; end +// 6'b100010 : begin data_collision_a_b <= 2'b00; display_wa_rb; end +// 6'b100110 : begin data_collision_a_b <= 2'b00; display_wa_rb; end +// 6'b101010 : begin data_collision_a_b <= 2'b00; display_wa_rb; end + endcase + end + end + setup_rf_a_b <= 0; + end + + + always @(posedge setup_rf_b_a) begin + if (data_addra_int[14:3] == data_addrb_reg[14:3]) begin + if ((ena_int == 1) && (enb_reg == 1)) begin + case ({wr_mode_a, wr_mode_b, wea_int, web_reg}) +// 6'b000011 : begin data_collision_b_a <= 2'b00; display_wa_wb; end + 6'b000111 : begin data_collision_b_a <= 2'b11; display_wa_wb; end +// 6'b001011 : begin data_collision_b_a <= 2'b00; display_wa_wb; end +// 6'b010011 : begin data_collision_b_a <= 2'b00; display_wa_wb; end + 6'b010111 : begin data_collision_b_a <= 2'b11; display_wa_wb; end +// 6'b011011 : begin data_collision_b_a <= 2'b00; display_wa_wb; end +// 6'b100011 : begin data_collision_b_a <= 2'b00; display_wa_wb; end + 6'b100111 : begin data_collision_b_a <= 2'b01; display_wa_wb; end +// 6'b101011 : begin data_collision_b_a <= 2'b00; display_wa_wb; end +// 6'b000001 : begin data_collision_b_a <= 2'b00; display_ra_wb; end + 6'b000101 : begin data_collision_b_a <= 2'b10; display_ra_wb; end +// 6'b001001 : begin data_collision_b_a <= 2'b00; display_ra_wb; end +// 6'b010001 : begin data_collision_b_a <= 2'b00; display_ra_wb; end + 6'b010101 : begin data_collision_b_a <= 2'b10; display_ra_wb; end +// 6'b011001 : begin data_collision_b_a <= 2'b00; display_ra_wb; end +// 6'b100001 : begin data_collision_b_a <= 2'b00; display_ra_wb; end + 6'b100101 : begin data_collision_b_a <= 2'b10; display_ra_wb; end +// 6'b101001 : begin data_collision_b_a <= 2'b00; display_ra_wb; end +// 6'b000010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end +// 6'b000110 : begin data_collision_b_a <= 2'b00; display_wa_rb; end +// 6'b001010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end +// 6'b010010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end +// 6'b010110 : begin data_collision_b_a <= 2'b00; display_wa_rb; end +// 6'b011010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end +// 6'b100010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end +// 6'b100110 : begin data_collision_b_a <= 2'b00; display_wa_rb; end +// 6'b101010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end + endcase + end + end + setup_rf_b_a <= 0; + end + + + always @(posedge clka_int) begin + addra_reg <= addra_int; + ena_reg <= ena_int; + ssra_reg <= ssra_int; + wea_reg <= wea_int; + end + + always @(posedge clkb_int) begin + addrb_reg <= addrb_int; + enb_reg <= enb_int; + ssrb_reg <= ssrb_int; + web_reg <= web_int; + end + + // Data + always @(posedge memory_collision) begin + for (dmi = 0; dmi < 2; dmi = dmi + 1) begin + mem[data_addra_int + dmi] <= 1'bX; + end + memory_collision <= 0; + end + + always @(posedge memory_collision_a_b) begin + for (dmi = 0; dmi < 2; dmi = dmi + 1) begin + mem[data_addra_reg + dmi] <= 1'bX; + end + memory_collision_a_b <= 0; + end + + always @(posedge memory_collision_b_a) begin + for (dmi = 0; dmi < 2; dmi = dmi + 1) begin + mem[data_addra_int + dmi] <= 1'bX; + end + memory_collision_b_a <= 0; + end + + always @(posedge data_collision[1]) begin + if (ssra_int == 0) begin + doa_out <= 2'bX; + end + data_collision[1] <= 0; + end + + always @(posedge data_collision[0]) begin + if (ssrb_int == 0) begin + for (dbi = 0; dbi < 2; dbi = dbi + 1) begin + dob_out[data_addra_int[2 : 0] + dbi] <= 1'bX; + end + end + data_collision[0] <= 0; + end + + always @(posedge data_collision_a_b[1]) begin + if (ssra_reg == 0) begin + doa_out <= 2'bX; + end + data_collision_a_b[1] <= 0; + end + + always @(posedge data_collision_a_b[0]) begin + if (ssrb_int == 0) begin + for (dbi = 0; dbi < 2; dbi = dbi + 1) begin + dob_out[data_addra_reg[2 : 0] + dbi] <= 1'bX; + end + end + data_collision_a_b[0] <= 0; + end + + always @(posedge data_collision_b_a[1]) begin + if (ssra_int == 0) begin + doa_out <= 2'bX; + end + data_collision_b_a[1] <= 0; + end + + always @(posedge data_collision_b_a[0]) begin + if (ssrb_reg == 0) begin + for (dbi = 0; dbi < 2; dbi = dbi + 1) begin + dob_out[data_addra_int[2 : 0] + dbi] <= 1'bX; + end + end + data_collision_b_a[0] <= 0; + end + + + initial begin + case (WRITE_MODE_A) + "WRITE_FIRST" : wr_mode_a <= 2'b00; + "READ_FIRST" : wr_mode_a <= 2'b01; + "NO_CHANGE" : wr_mode_a <= 2'b10; + default : begin + $display("Attribute Syntax Error : The Attribute WRITE_MODE_A on RAMB16_S2_S9 instance %m is set to %s. Legal values for this attribute are WRITE_FIRST, READ_FIRST or NO_CHANGE.", WRITE_MODE_A); + $finish; + end + endcase + end + + initial begin + case (WRITE_MODE_B) + "WRITE_FIRST" : wr_mode_b <= 2'b00; + "READ_FIRST" : wr_mode_b <= 2'b01; + "NO_CHANGE" : wr_mode_b <= 2'b10; + default : begin + $display("Attribute Syntax Error : The Attribute WRITE_MODE_B on RAMB16_S2_S9 instance %m is set to %s. Legal values for this attribute are WRITE_FIRST, READ_FIRST or NO_CHANGE.", WRITE_MODE_B); + $finish; + end + endcase + end + + // Port A + always @(posedge clka_int) begin + if (ena_int == 1'b1) begin + if (ssra_int == 1'b1) begin + doa_out[0] <= SRVAL_A[0]; + doa_out[1] <= SRVAL_A[1]; + end + else begin + if (wea_int == 1'b1) begin + if (wr_mode_a == 2'b00) begin + doa_out <= dia_int; + end + else if (wr_mode_a == 2'b01) begin + doa_out[0] <= mem[data_addra_int + 0]; + doa_out[1] <= mem[data_addra_int + 1]; + end + end + else begin + doa_out[0] <= mem[data_addra_int + 0]; + doa_out[1] <= mem[data_addra_int + 1]; + end + end + end + end + + always @(posedge clka_int) begin + if (ena_int == 1'b1 && wea_int == 1'b1) begin + mem[data_addra_int + 0] <= dia_int[0]; + mem[data_addra_int + 1] <= dia_int[1]; + end + end + + // Port B + always @(posedge clkb_int) begin + if (enb_int == 1'b1) begin + if (ssrb_int == 1'b1) begin + dob_out[0] <= SRVAL_B[0]; + dob_out[1] <= SRVAL_B[1]; + dob_out[2] <= SRVAL_B[2]; + dob_out[3] <= SRVAL_B[3]; + dob_out[4] <= SRVAL_B[4]; + dob_out[5] <= SRVAL_B[5]; + dob_out[6] <= SRVAL_B[6]; + dob_out[7] <= SRVAL_B[7]; + dopb_out[0] <= SRVAL_B[8]; + end + else begin + if (web_int == 1'b1) begin + if (wr_mode_b == 2'b00) begin + dob_out <= dib_int; + dopb_out <= dipb_int; + end + else if (wr_mode_b == 2'b01) begin + dob_out[0] <= mem[data_addrb_int + 0]; + dob_out[1] <= mem[data_addrb_int + 1]; + dob_out[2] <= mem[data_addrb_int + 2]; + dob_out[3] <= mem[data_addrb_int + 3]; + dob_out[4] <= mem[data_addrb_int + 4]; + dob_out[5] <= mem[data_addrb_int + 5]; + dob_out[6] <= mem[data_addrb_int + 6]; + dob_out[7] <= mem[data_addrb_int + 7]; + dopb_out[0] <= mem[parity_addrb_int + 0]; + end + end + else begin + dob_out[0] <= mem[data_addrb_int + 0]; + dob_out[1] <= mem[data_addrb_int + 1]; + dob_out[2] <= mem[data_addrb_int + 2]; + dob_out[3] <= mem[data_addrb_int + 3]; + dob_out[4] <= mem[data_addrb_int + 4]; + dob_out[5] <= mem[data_addrb_int + 5]; + dob_out[6] <= mem[data_addrb_int + 6]; + dob_out[7] <= mem[data_addrb_int + 7]; + dopb_out[0] <= mem[parity_addrb_int + 0]; + end + end + end + end + + always @(posedge clkb_int) begin + if (enb_int == 1'b1 && web_int == 1'b1) begin + mem[data_addrb_int + 0] <= dib_int[0]; + mem[data_addrb_int + 1] <= dib_int[1]; + mem[data_addrb_int + 2] <= dib_int[2]; + mem[data_addrb_int + 3] <= dib_int[3]; + mem[data_addrb_int + 4] <= dib_int[4]; + mem[data_addrb_int + 5] <= dib_int[5]; + mem[data_addrb_int + 6] <= dib_int[6]; + mem[data_addrb_int + 7] <= dib_int[7]; + mem[parity_addrb_int + 0] <= dipb_int[0]; + end + end + + specify + (CLKA *> DOA) = (100, 100); + (CLKB *> DOB) = (100, 100); + (CLKB *> DOPB) = (100, 100); + endspecify + +endmodule + +`else + +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/RAMB16_S2_S9.v,v 1.10 2007/02/22 01:58:06 wloo Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2005 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Timing Simulation Library Component +// / / 16K-Bit Data and 2K-Bit Parity Dual Port Block RAM +// /___/ /\ Filename : RAMB16_S2_S9.v +// \ \ / \ Timestamp : Thu Mar 10 16:44:01 PST 2005 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 03/10/05 - Initialized outputs. +// 02/21/07 - Fixed parameter SIM_COLLISION_CHECK (CR 433281). +// End Revision + +`timescale 1 ps/1 ps + +module RAMB16_S2_S9 (DOA, DOB, DOPB, ADDRA, ADDRB, CLKA, CLKB, DIA, DIB, DIPB, ENA, ENB, SSRA, SSRB, WEA, WEB); + + parameter INIT_A = 2'h0; + parameter INIT_B = 9'h0; + parameter SRVAL_A = 2'h0; + parameter SRVAL_B = 9'h0; + parameter WRITE_MODE_A = "WRITE_FIRST"; + parameter WRITE_MODE_B = "WRITE_FIRST"; + parameter SIM_COLLISION_CHECK = "ALL"; + localparam SETUP_ALL = 1000; + localparam SETUP_READ_FIRST = 3000; + + parameter INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + + output [1:0] DOA; + output [7:0] DOB; + output [0:0] DOPB; + + input [12:0] ADDRA; + input [1:0] DIA; + input ENA, CLKA, WEA, SSRA; + input [10:0] ADDRB; + input [7:0] DIB; + input [0:0] DIPB; + input ENB, CLKB, WEB, SSRB; + + reg [1:0] doa_out = INIT_A[1:0]; + reg [7:0] dob_out = INIT_B[7:0]; + reg [0:0] dopb_out = INIT_B[8:8]; + + reg [7:0] mem [2047:0]; + reg [0:0] memp [2047:0]; + + reg [8:0] count, countp; + reg [1:0] wr_mode_a, wr_mode_b; + + reg [5:0] dmi, dbi; + reg [5:0] pmi, pbi; + + wire [12:0] addra_int; + reg [12:0] addra_reg; + wire [1:0] dia_int; + wire ena_int, clka_int, wea_int, ssra_int; + reg ena_reg, wea_reg, ssra_reg; + wire [10:0] addrb_int; + reg [10:0] addrb_reg; + wire [7:0] dib_int; + wire [0:0] dipb_int; + wire enb_int, clkb_int, web_int, ssrb_int; + reg display_flag, output_flag; + reg enb_reg, web_reg, ssrb_reg; + + time time_clka, time_clkb; + time time_clka_clkb; + time time_clkb_clka; + + reg setup_all_a_b; + reg setup_all_b_a; + reg setup_zero; + reg setup_rf_a_b; + reg setup_rf_b_a; + reg [1:0] data_collision, data_collision_a_b, data_collision_b_a; + reg memory_collision, memory_collision_a_b, memory_collision_b_a; + reg change_clka; + reg change_clkb; + + wire [14:0] data_addra_int; + wire [14:0] data_addra_reg; + wire [14:0] data_addrb_int; + wire [14:0] data_addrb_reg; + + wire dia_enable = ena_int && wea_int; + wire dib_enable = enb_int && web_int; + + tri0 GSR = glbl.GSR; + wire gsr_int; + + buf b_gsr (gsr_int, GSR); + + buf b_doa [1:0] (DOA, doa_out); + buf b_addra [12:0] (addra_int, ADDRA); + buf b_dia [1:0] (dia_int, DIA); + buf b_ena (ena_int, ENA); + buf b_clka (clka_int, CLKA); + buf b_ssra (ssra_int, SSRA); + buf b_wea (wea_int, WEA); + + buf b_dob [7:0] (DOB, dob_out); + buf b_dopb [0:0] (DOPB, dopb_out); + buf b_addrb [10:0] (addrb_int, ADDRB); + buf b_dib [7:0] (dib_int, DIB); + buf b_dipb [0:0] (dipb_int, DIPB); + buf b_enb (enb_int, ENB); + buf b_clkb (clkb_int, CLKB); + buf b_ssrb (ssrb_int, SSRB); + buf b_web (web_int, WEB); + + + always @(gsr_int) + if (gsr_int) begin + assign {doa_out} = INIT_A; + assign {dopb_out, dob_out} = INIT_B; + end + else begin + deassign doa_out; + deassign dob_out; + deassign dopb_out; + end + + + initial begin + + for (count = 0; count < 32; count = count + 1) begin + mem[count] = INIT_00[(count * 8) +: 8]; + mem[32 * 1 + count] = INIT_01[(count * 8) +: 8]; + mem[32 * 2 + count] = INIT_02[(count * 8) +: 8]; + mem[32 * 3 + count] = INIT_03[(count * 8) +: 8]; + mem[32 * 4 + count] = INIT_04[(count * 8) +: 8]; + mem[32 * 5 + count] = INIT_05[(count * 8) +: 8]; + mem[32 * 6 + count] = INIT_06[(count * 8) +: 8]; + mem[32 * 7 + count] = INIT_07[(count * 8) +: 8]; + mem[32 * 8 + count] = INIT_08[(count * 8) +: 8]; + mem[32 * 9 + count] = INIT_09[(count * 8) +: 8]; + mem[32 * 10 + count] = INIT_0A[(count * 8) +: 8]; + mem[32 * 11 + count] = INIT_0B[(count * 8) +: 8]; + mem[32 * 12 + count] = INIT_0C[(count * 8) +: 8]; + mem[32 * 13 + count] = INIT_0D[(count * 8) +: 8]; + mem[32 * 14 + count] = INIT_0E[(count * 8) +: 8]; + mem[32 * 15 + count] = INIT_0F[(count * 8) +: 8]; + mem[32 * 16 + count] = INIT_10[(count * 8) +: 8]; + mem[32 * 17 + count] = INIT_11[(count * 8) +: 8]; + mem[32 * 18 + count] = INIT_12[(count * 8) +: 8]; + mem[32 * 19 + count] = INIT_13[(count * 8) +: 8]; + mem[32 * 20 + count] = INIT_14[(count * 8) +: 8]; + mem[32 * 21 + count] = INIT_15[(count * 8) +: 8]; + mem[32 * 22 + count] = INIT_16[(count * 8) +: 8]; + mem[32 * 23 + count] = INIT_17[(count * 8) +: 8]; + mem[32 * 24 + count] = INIT_18[(count * 8) +: 8]; + mem[32 * 25 + count] = INIT_19[(count * 8) +: 8]; + mem[32 * 26 + count] = INIT_1A[(count * 8) +: 8]; + mem[32 * 27 + count] = INIT_1B[(count * 8) +: 8]; + mem[32 * 28 + count] = INIT_1C[(count * 8) +: 8]; + mem[32 * 29 + count] = INIT_1D[(count * 8) +: 8]; + mem[32 * 30 + count] = INIT_1E[(count * 8) +: 8]; + mem[32 * 31 + count] = INIT_1F[(count * 8) +: 8]; + mem[32 * 32 + count] = INIT_20[(count * 8) +: 8]; + mem[32 * 33 + count] = INIT_21[(count * 8) +: 8]; + mem[32 * 34 + count] = INIT_22[(count * 8) +: 8]; + mem[32 * 35 + count] = INIT_23[(count * 8) +: 8]; + mem[32 * 36 + count] = INIT_24[(count * 8) +: 8]; + mem[32 * 37 + count] = INIT_25[(count * 8) +: 8]; + mem[32 * 38 + count] = INIT_26[(count * 8) +: 8]; + mem[32 * 39 + count] = INIT_27[(count * 8) +: 8]; + mem[32 * 40 + count] = INIT_28[(count * 8) +: 8]; + mem[32 * 41 + count] = INIT_29[(count * 8) +: 8]; + mem[32 * 42 + count] = INIT_2A[(count * 8) +: 8]; + mem[32 * 43 + count] = INIT_2B[(count * 8) +: 8]; + mem[32 * 44 + count] = INIT_2C[(count * 8) +: 8]; + mem[32 * 45 + count] = INIT_2D[(count * 8) +: 8]; + mem[32 * 46 + count] = INIT_2E[(count * 8) +: 8]; + mem[32 * 47 + count] = INIT_2F[(count * 8) +: 8]; + mem[32 * 48 + count] = INIT_30[(count * 8) +: 8]; + mem[32 * 49 + count] = INIT_31[(count * 8) +: 8]; + mem[32 * 50 + count] = INIT_32[(count * 8) +: 8]; + mem[32 * 51 + count] = INIT_33[(count * 8) +: 8]; + mem[32 * 52 + count] = INIT_34[(count * 8) +: 8]; + mem[32 * 53 + count] = INIT_35[(count * 8) +: 8]; + mem[32 * 54 + count] = INIT_36[(count * 8) +: 8]; + mem[32 * 55 + count] = INIT_37[(count * 8) +: 8]; + mem[32 * 56 + count] = INIT_38[(count * 8) +: 8]; + mem[32 * 57 + count] = INIT_39[(count * 8) +: 8]; + mem[32 * 58 + count] = INIT_3A[(count * 8) +: 8]; + mem[32 * 59 + count] = INIT_3B[(count * 8) +: 8]; + mem[32 * 60 + count] = INIT_3C[(count * 8) +: 8]; + mem[32 * 61 + count] = INIT_3D[(count * 8) +: 8]; + mem[32 * 62 + count] = INIT_3E[(count * 8) +: 8]; + mem[32 * 63 + count] = INIT_3F[(count * 8) +: 8]; + end + +// initiate parity start + for (countp = 0; countp < 256; countp = countp + 1) begin + memp[countp] = INITP_00[(countp * 1) +: 1]; + memp[256 * 1 + countp] = INITP_01[(countp * 1) +: 1]; + memp[256 * 2 + countp] = INITP_02[(countp * 1) +: 1]; + memp[256 * 3 + countp] = INITP_03[(countp * 1) +: 1]; + memp[256 * 4 + countp] = INITP_04[(countp * 1) +: 1]; + memp[256 * 5 + countp] = INITP_05[(countp * 1) +: 1]; + memp[256 * 6 + countp] = INITP_06[(countp * 1) +: 1]; + memp[256 * 7 + countp] = INITP_07[(countp * 1) +: 1]; + end +// initiate parity end + + change_clka <= 0; + change_clkb <= 0; + data_collision <= 0; + data_collision_a_b <= 0; + data_collision_b_a <= 0; + memory_collision <= 0; + memory_collision_a_b <= 0; + memory_collision_b_a <= 0; + setup_all_a_b <= 0; + setup_all_b_a <= 0; + setup_zero <= 0; + setup_rf_a_b <= 0; + setup_rf_b_a <= 0; + end + + assign data_addra_int = addra_int * 2; + assign data_addra_reg = addra_reg * 2; + assign data_addrb_int = addrb_int * 8; + assign data_addrb_reg = addrb_reg * 8; + + + initial begin + + display_flag = 1; + output_flag = 1; + + case (SIM_COLLISION_CHECK) + + "NONE" : begin + output_flag = 0; + display_flag = 0; + end + "WARNING_ONLY" : output_flag = 0; + "GENERATE_X_ONLY" : display_flag = 0; + "ALL" : ; + + default : begin + $display("Attribute Syntax Error : The Attribute SIM_COLLISION_CHECK on RAMB16_S2_S9 instance %m is set to %s. Legal values for this attribute are ALL, NONE, WARNING_ONLY or GENERATE_X_ONLY.", SIM_COLLISION_CHECK); + $finish; + end + + endcase // case(SIM_COLLISION_CHECK) + + end // initial begin + + + always @(posedge clka_int) begin + if ((output_flag || display_flag)) begin + time_clka = $time; + #0 time_clkb_clka = time_clka - time_clkb; + change_clka = ~change_clka; + end + end + + always @(posedge clkb_int) begin + if ((output_flag || display_flag)) begin + time_clkb = $time; + #0 time_clka_clkb = time_clkb - time_clka; + change_clkb = ~change_clkb; + end + end + + always @(change_clkb) begin + if ((0 < time_clka_clkb) && (time_clka_clkb < SETUP_ALL)) + setup_all_a_b = 1; + if ((0 < time_clka_clkb) && (time_clka_clkb < SETUP_READ_FIRST)) + setup_rf_a_b = 1; + end + + always @(change_clka) begin + if ((0 < time_clkb_clka) && (time_clkb_clka < SETUP_ALL)) + setup_all_b_a = 1; + if ((0 < time_clkb_clka) && (time_clkb_clka < SETUP_READ_FIRST)) + setup_rf_b_a = 1; + end + + always @(change_clkb or change_clka) begin + if ((time_clkb_clka == 0) && (time_clka_clkb == 0)) + setup_zero = 1; + end + + always @(posedge setup_zero) begin + if ((ena_int == 1) && (wea_int == 1) && + (enb_int == 1) && (web_int == 1) && + (data_addra_int[14:3] == data_addrb_int[14:3])) + memory_collision <= 1; + end + + always @(posedge setup_all_a_b or posedge setup_rf_a_b) begin + if ((ena_reg == 1) && (wea_reg == 1) && + (enb_int == 1) && (web_int == 1) && + (data_addra_reg[14:3] == data_addrb_int[14:3])) + memory_collision_a_b <= 1; + end + + always @(posedge setup_all_b_a or posedge setup_rf_b_a) begin + if ((ena_int == 1) && (wea_int == 1) && + (enb_reg == 1) && (web_reg == 1) && + (data_addra_int[14:3] == data_addrb_reg[14:3])) + memory_collision_b_a <= 1; + end + + always @(posedge setup_all_a_b) begin + if (data_addra_reg[14:3] == data_addrb_int[14:3]) begin + if ((ena_reg == 1) && (enb_int == 1)) begin + case ({wr_mode_a, wr_mode_b, wea_reg, web_int}) + 6'b000011 : begin data_collision_a_b <= 2'b11; display_wa_wb; end + 6'b000111 : begin data_collision_a_b <= 2'b11; display_wa_wb; end + 6'b001011 : begin data_collision_a_b <= 2'b10; display_wa_wb; end +// 6'b010011 : begin data_collision_a_b <= 2'b00; display_wa_wb; end +// 6'b010111 : begin data_collision_a_b <= 2'b00; display_wa_wb; end +// 6'b011011 : begin data_collision_a_b <= 2'b00; display_wa_wb; end + 6'b100011 : begin data_collision_a_b <= 2'b01; display_wa_wb; end + 6'b100111 : begin data_collision_a_b <= 2'b01; display_wa_wb; end + 6'b101011 : begin display_wa_wb; end + 6'b000001 : begin data_collision_a_b <= 2'b10; display_ra_wb; end +// 6'b000101 : begin data_collision_a_b <= 2'b00; display_ra_wb; end + 6'b001001 : begin data_collision_a_b <= 2'b10; display_ra_wb; end + 6'b010001 : begin data_collision_a_b <= 2'b10; display_ra_wb; end +// 6'b010101 : begin data_collision_a_b <= 2'b00; display_ra_wb; end + 6'b011001 : begin data_collision_a_b <= 2'b10; display_ra_wb; end + 6'b100001 : begin data_collision_a_b <= 2'b10; display_ra_wb; end +// 6'b100101 : begin data_collision_a_b <= 2'b00; display_ra_wb; end + 6'b101001 : begin data_collision_a_b <= 2'b10; display_ra_wb; end + 6'b000010 : begin data_collision_a_b <= 2'b01; display_wa_rb; end + 6'b000110 : begin data_collision_a_b <= 2'b01; display_wa_rb; end + 6'b001010 : begin data_collision_a_b <= 2'b01; display_wa_rb; end +// 6'b010010 : begin data_collision_a_b <= 2'b00; display_wa_rb; end +// 6'b010110 : begin data_collision_a_b <= 2'b00; display_wa_rb; end +// 6'b011010 : begin data_collision_a_b <= 2'b00; display_wa_rb; end + 6'b100010 : begin data_collision_a_b <= 2'b01; display_wa_rb; end + 6'b100110 : begin data_collision_a_b <= 2'b01; display_wa_rb; end + 6'b101010 : begin data_collision_a_b <= 2'b01; display_wa_rb; end + endcase + end + end + setup_all_a_b <= 0; + end + + + always @(posedge setup_all_b_a) begin + if (data_addra_int[14:3] == data_addrb_reg[14:3]) begin + if ((ena_int == 1) && (enb_reg == 1)) begin + case ({wr_mode_a, wr_mode_b, wea_int, web_reg}) + 6'b000011 : begin data_collision_b_a <= 2'b11; display_wa_wb; end +// 6'b000111 : begin data_collision_b_a <= 2'b00; display_wa_wb; end + 6'b001011 : begin data_collision_b_a <= 2'b10; display_wa_wb; end + 6'b010011 : begin data_collision_b_a <= 2'b11; display_wa_wb; end +// 6'b010111 : begin data_collision_b_a <= 2'b00; display_wa_wb; end + 6'b011011 : begin data_collision_b_a <= 2'b10; display_wa_wb; end + 6'b100011 : begin data_collision_b_a <= 2'b01; display_wa_wb; end + 6'b100111 : begin data_collision_b_a <= 2'b01; display_wa_wb; end + 6'b101011 : begin display_wa_wb; end + 6'b000001 : begin data_collision_b_a <= 2'b10; display_ra_wb; end + 6'b000101 : begin data_collision_b_a <= 2'b10; display_ra_wb; end + 6'b001001 : begin data_collision_b_a <= 2'b10; display_ra_wb; end + 6'b010001 : begin data_collision_b_a <= 2'b10; display_ra_wb; end + 6'b010101 : begin data_collision_b_a <= 2'b10; display_ra_wb; end + 6'b011001 : begin data_collision_b_a <= 2'b10; display_ra_wb; end + 6'b100001 : begin data_collision_b_a <= 2'b10; display_ra_wb; end + 6'b100101 : begin data_collision_b_a <= 2'b10; display_ra_wb; end + 6'b101001 : begin data_collision_b_a <= 2'b10; display_ra_wb; end + 6'b000010 : begin data_collision_b_a <= 2'b01; display_wa_rb; end + 6'b000110 : begin data_collision_b_a <= 2'b01; display_wa_rb; end + 6'b001010 : begin data_collision_b_a <= 2'b01; display_wa_rb; end +// 6'b010010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end +// 6'b010110 : begin data_collision_b_a <= 2'b00; display_wa_rb; end +// 6'b011010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end + 6'b100010 : begin data_collision_b_a <= 2'b01; display_wa_rb; end + 6'b100110 : begin data_collision_b_a <= 2'b01; display_wa_rb; end + 6'b101010 : begin data_collision_b_a <= 2'b01; display_wa_rb; end + endcase + end + end + setup_all_b_a <= 0; + end + + + always @(posedge setup_zero) begin + if (data_addra_int[14:3] == data_addrb_int[14:3]) begin + if ((ena_int == 1) && (enb_int == 1)) begin + case ({wr_mode_a, wr_mode_b, wea_int, web_int}) + 6'b000011 : begin data_collision <= 2'b11; display_wa_wb; end + 6'b000111 : begin data_collision <= 2'b11; display_wa_wb; end + 6'b001011 : begin data_collision <= 2'b10; display_wa_wb; end + 6'b010011 : begin data_collision <= 2'b11; display_wa_wb; end + 6'b010111 : begin data_collision <= 2'b11; display_wa_wb; end + 6'b011011 : begin data_collision <= 2'b10; display_wa_wb; end + 6'b100011 : begin data_collision <= 2'b01; display_wa_wb; end + 6'b100111 : begin data_collision <= 2'b01; display_wa_wb; end + 6'b101011 : begin display_wa_wb; end + 6'b000001 : begin data_collision <= 2'b10; display_ra_wb; end +// 6'b000101 : begin data_collision <= 2'b00; display_ra_wb; end + 6'b001001 : begin data_collision <= 2'b10; display_ra_wb; end + 6'b010001 : begin data_collision <= 2'b10; display_ra_wb; end +// 6'b010101 : begin data_collision <= 2'b00; display_ra_wb; end + 6'b011001 : begin data_collision <= 2'b10; display_ra_wb; end + 6'b100001 : begin data_collision <= 2'b10; display_ra_wb; end +// 6'b100101 : begin data_collision <= 2'b00; display_ra_wb; end + 6'b101001 : begin data_collision <= 2'b10; display_ra_wb; end + 6'b000010 : begin data_collision <= 2'b01; display_wa_rb; end + 6'b000110 : begin data_collision <= 2'b01; display_wa_rb; end + 6'b001010 : begin data_collision <= 2'b01; display_wa_rb; end +// 6'b010010 : begin data_collision <= 2'b00; display_wa_rb; end +// 6'b010110 : begin data_collision <= 2'b00; display_wa_rb; end +// 6'b011010 : begin data_collision <= 2'b00; display_wa_rb; end + 6'b100010 : begin data_collision <= 2'b01; display_wa_rb; end + 6'b100110 : begin data_collision <= 2'b01; display_wa_rb; end + 6'b101010 : begin data_collision <= 2'b01; display_wa_rb; end + endcase + end + end + setup_zero <= 0; + end + + task display_ra_wb; + begin + if (display_flag) + $display("Memory Collision Error on RAMB16_S2_S9:%m at simulation time %.3f ns\nA read was performed on address %h (hex) of Port A while a write was requested to the same address on Port B. The write will be successful however the read value on Port A is unknown until the next CLKA cycle.", $time/1000.0, addra_int); + end + endtask + + task display_wa_rb; + begin + if (display_flag) + $display("Memory Collision Error on RAMB16_S2_S9:%m at simulation time %.3f ns\nA read was performed on address %h (hex) of Port B while a write was requested to the same address on Port A. The write will be successful however the read value on Port B is unknown until the next CLKB cycle.", $time/1000.0, addrb_int); + end + endtask + + task display_wa_wb; + begin + if (display_flag) + $display("Memory Collision Error on RAMB16_S2_S9:%m at simulation time %.3f ns\nA write was requested to the same address simultaneously at both Port A and Port B of the RAM. The contents written to the RAM at address location %h (hex) of Port A and address location %h (hex) of Port B are unknown.", $time/1000.0, addra_int, addrb_int); + end + endtask + + + always @(posedge setup_rf_a_b) begin + if (data_addra_reg[14:3] == data_addrb_int[14:3]) begin + if ((ena_reg == 1) && (enb_int == 1)) begin + case ({wr_mode_a, wr_mode_b, wea_reg, web_int}) +// 6'b000011 : begin data_collision_a_b <= 2'b00; display_wa_wb; end +// 6'b000111 : begin data_collision_a_b <= 2'b00; display_wa_wb; end +// 6'b001011 : begin data_collision_a_b <= 2'b00; display_wa_wb; end + 6'b010011 : begin data_collision_a_b <= 2'b11; display_wa_wb; end + 6'b010111 : begin data_collision_a_b <= 2'b11; display_wa_wb; end + 6'b011011 : begin data_collision_a_b <= 2'b10; display_wa_wb; end +// 6'b100011 : begin data_collision_a_b <= 2'b00; display_wa_wb; end +// 6'b100111 : begin data_collision_a_b <= 2'b00; display_wa_wb; end +// 6'b101011 : begin data_collision_a_b <= 2'b00; display_wa_wb; end +// 6'b000001 : begin data_collision_a_b <= 2'b00; display_ra_wb; end +// 6'b000101 : begin data_collision_a_b <= 2'b00; display_ra_wb; end +// 6'b001001 : begin data_collision_a_b <= 2'b00; display_ra_wb; end +// 6'b010001 : begin data_collision_a_b <= 2'b00; display_ra_wb; end +// 6'b010101 : begin data_collision_a_b <= 2'b00; display_ra_wb; end +// 6'b011001 : begin data_collision_a_b <= 2'b00; display_ra_wb; end +// 6'b100001 : begin data_collision_a_b <= 2'b00; display_ra_wb; end +// 6'b100101 : begin data_collision_a_b <= 2'b00; display_ra_wb; end +// 6'b101001 : begin data_collision_a_b <= 2'b00; display_ra_wb; end +// 6'b000010 : begin data_collision_a_b <= 2'b00; display_wa_rb; end +// 6'b000110 : begin data_collision_a_b <= 2'b00; display_wa_rb; end +// 6'b001010 : begin data_collision_a_b <= 2'b00; display_wa_rb; end + 6'b010010 : begin data_collision_a_b <= 2'b01; display_wa_rb; end + 6'b010110 : begin data_collision_a_b <= 2'b01; display_wa_rb; end + 6'b011010 : begin data_collision_a_b <= 2'b01; display_wa_rb; end +// 6'b100010 : begin data_collision_a_b <= 2'b00; display_wa_rb; end +// 6'b100110 : begin data_collision_a_b <= 2'b00; display_wa_rb; end +// 6'b101010 : begin data_collision_a_b <= 2'b00; display_wa_rb; end + endcase + end + end + setup_rf_a_b <= 0; + end + + + always @(posedge setup_rf_b_a) begin + if (data_addra_int[14:3] == data_addrb_reg[14:3]) begin + if ((ena_int == 1) && (enb_reg == 1)) begin + case ({wr_mode_a, wr_mode_b, wea_int, web_reg}) +// 6'b000011 : begin data_collision_b_a <= 2'b00; display_wa_wb; end + 6'b000111 : begin data_collision_b_a <= 2'b11; display_wa_wb; end +// 6'b001011 : begin data_collision_b_a <= 2'b00; display_wa_wb; end +// 6'b010011 : begin data_collision_b_a <= 2'b00; display_wa_wb; end + 6'b010111 : begin data_collision_b_a <= 2'b11; display_wa_wb; end +// 6'b011011 : begin data_collision_b_a <= 2'b00; display_wa_wb; end +// 6'b100011 : begin data_collision_b_a <= 2'b00; display_wa_wb; end + 6'b100111 : begin data_collision_b_a <= 2'b01; display_wa_wb; end +// 6'b101011 : begin data_collision_b_a <= 2'b00; display_wa_wb; end +// 6'b000001 : begin data_collision_b_a <= 2'b00; display_ra_wb; end + 6'b000101 : begin data_collision_b_a <= 2'b10; display_ra_wb; end +// 6'b001001 : begin data_collision_b_a <= 2'b00; display_ra_wb; end +// 6'b010001 : begin data_collision_b_a <= 2'b00; display_ra_wb; end + 6'b010101 : begin data_collision_b_a <= 2'b10; display_ra_wb; end +// 6'b011001 : begin data_collision_b_a <= 2'b00; display_ra_wb; end +// 6'b100001 : begin data_collision_b_a <= 2'b00; display_ra_wb; end + 6'b100101 : begin data_collision_b_a <= 2'b10; display_ra_wb; end +// 6'b101001 : begin data_collision_b_a <= 2'b00; display_ra_wb; end +// 6'b000010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end +// 6'b000110 : begin data_collision_b_a <= 2'b00; display_wa_rb; end +// 6'b001010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end +// 6'b010010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end +// 6'b010110 : begin data_collision_b_a <= 2'b00; display_wa_rb; end +// 6'b011010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end +// 6'b100010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end +// 6'b100110 : begin data_collision_b_a <= 2'b00; display_wa_rb; end +// 6'b101010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end + endcase + end + end + setup_rf_b_a <= 0; + end + + + always @(posedge clka_int) begin + if ((output_flag || display_flag)) begin + addra_reg <= addra_int; + ena_reg <= ena_int; + ssra_reg <= ssra_int; + wea_reg <= wea_int; + end + end + + always @(posedge clkb_int) begin + if ((output_flag || display_flag)) begin + addrb_reg <= addrb_int; + enb_reg <= enb_int; + ssrb_reg <= ssrb_int; + web_reg <= web_int; + end + end + + + // Data + always @(posedge memory_collision) begin + if ((output_flag || display_flag)) begin + mem[addra_int[12:2]][addra_int[1:0] * 2 +: 2] <= 2'bx; + memory_collision <= 0; + end + + end + + always @(posedge memory_collision_a_b) begin + if ((output_flag || display_flag)) begin + mem[addra_reg[12:2]][addra_reg[1:0] * 2 +: 2] <= 2'bx; + memory_collision_a_b <= 0; + end + end + + always @(posedge memory_collision_b_a) begin + if ((output_flag || display_flag)) begin + mem[addra_int[12:2]][addra_int[1:0] * 2 +: 2] <= 2'bx; + memory_collision_b_a <= 0; + end + end + + always @(posedge data_collision[1]) begin + if (ssra_int == 0 && output_flag) begin + doa_out <= #100 2'bX; + end + data_collision[1] <= 0; + end + + always @(posedge data_collision[0]) begin + if (ssrb_int == 0 && output_flag) begin + dob_out[addra_int[1:0] * 2 +: 2] <= #100 2'bX; + end + data_collision[0] <= 0; + end + + always @(posedge data_collision_a_b[1]) begin + if (ssra_reg == 0 && output_flag) begin + doa_out <= #100 2'bX; + end + data_collision_a_b[1] <= 0; + end + + always @(posedge data_collision_a_b[0]) begin + if (ssrb_int == 0 && output_flag) begin + dob_out[addra_reg[1:0] * 2 +: 2] <= #100 2'bX; + end + data_collision_a_b[0] <= 0; + end + + always @(posedge data_collision_b_a[1]) begin + if (ssra_int == 0 && output_flag) begin + doa_out <= #100 2'bX; + end + data_collision_b_a[1] <= 0; + end + + always @(posedge data_collision_b_a[0]) begin + if (ssrb_reg == 0 && output_flag) begin + dob_out[addra_int[1:0] * 2 +: 2] <= #100 2'bX; + end + data_collision_b_a[0] <= 0; + end + + + initial begin + case (WRITE_MODE_A) + "WRITE_FIRST" : wr_mode_a <= 2'b00; + "READ_FIRST" : wr_mode_a <= 2'b01; + "NO_CHANGE" : wr_mode_a <= 2'b10; + default : begin + $display("Attribute Syntax Error : The Attribute WRITE_MODE_A on RAMB16_S2_S9 instance %m is set to %s. Legal values for this attribute are WRITE_FIRST, READ_FIRST or NO_CHANGE.", WRITE_MODE_A); + $finish; + end + endcase + end + + initial begin + case (WRITE_MODE_B) + "WRITE_FIRST" : wr_mode_b <= 2'b00; + "READ_FIRST" : wr_mode_b <= 2'b01; + "NO_CHANGE" : wr_mode_b <= 2'b10; + default : begin + $display("Attribute Syntax Error : The Attribute WRITE_MODE_B on RAMB16_S2_S9 instance %m is set to %s. Legal values for this attribute are WRITE_FIRST, READ_FIRST or NO_CHANGE.", WRITE_MODE_B); + $finish; + end + endcase + end + + + // Port A + always @(posedge clka_int) begin + + if (ena_int == 1'b1) begin + + if (ssra_int == 1'b1) begin + {doa_out} <= #100 SRVAL_A; + end + else begin + if (wea_int == 1'b1) begin + if (wr_mode_a == 2'b00) begin + doa_out <= #100 dia_int; + end + else if (wr_mode_a == 2'b01) begin + + doa_out <= #100 mem[addra_int[12:2]][addra_int[1:0] * 2 +: 2]; + + end + end + else begin + + doa_out <= #100 mem[addra_int[12:2]][addra_int[1:0] * 2 +: 2]; + + end + end + + // memory + if (wea_int == 1'b1) begin + mem[addra_int[12:2]][addra_int[1:0] * 2 +: 2] <= dia_int; + end + + end + end + + + // Port B + always @(posedge clkb_int) begin + + if (enb_int == 1'b1) begin + + if (ssrb_int == 1'b1) begin + {dopb_out, dob_out} <= #100 SRVAL_B; + end + else begin + if (web_int == 1'b1) begin + if (wr_mode_b == 2'b00) begin + dob_out <= #100 dib_int; + dopb_out <= #100 dipb_int; + end + else if (wr_mode_b == 2'b01) begin + dob_out <= #100 mem[addrb_int]; + dopb_out <= #100 memp[addrb_int]; + end + end + else begin + dob_out <= #100 mem[addrb_int]; + dopb_out <= #100 memp[addrb_int]; + end + end + + // memory + if (web_int == 1'b1) begin + mem[addrb_int] <= dib_int; + memp[addrb_int] <= dipb_int; + end + + end + end + + +endmodule + +`endif diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/RAMB16_S36.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/RAMB16_S36.v new file mode 100644 index 0000000..e3de9fe --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/RAMB16_S36.v @@ -0,0 +1,910 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/RAMB16_S36.v,v 1.6 2005/03/14 22:54:41 wloo Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2005 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / 16K-Bit Data and 2K-Bit Parity Single Port Block RAM +// /___/ /\ Filename : RAMB16_S36.v +// \ \ / \ Timestamp : Thu Mar 10 16:43:36 PST 2005 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// End Revision + +`ifdef legacy_model + +`timescale 1 ps / 1 ps + +module RAMB16_S36 (DO, DOP, ADDR, CLK, DI, DIP, EN, SSR, WE); + + parameter INIT = 36'h0; + parameter SRVAL = 36'h0; + parameter WRITE_MODE = "WRITE_FIRST"; + + parameter INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + + output [31:0] DO; + output [3:0] DOP; + reg do0_out, do1_out, do2_out, do3_out, do4_out, do5_out, do6_out, do7_out, do8_out, do9_out, do10_out, do11_out, do12_out, do13_out, do14_out, do15_out, do16_out, do17_out, do18_out, do19_out, do20_out, do21_out, do22_out, do23_out, do24_out, do25_out, do26_out, do27_out, do28_out, do29_out, do30_out, do31_out; + reg dop0_out, dop1_out, dop2_out, dop3_out; + + input [8:0] ADDR; + input [31:0] DI; + input [3:0] DIP; + input EN, CLK, WE, SSR; + + reg [18431:0] mem; + reg [8:0] count; + reg [1:0] wr_mode; + + wire [8:0] addr_int; + wire [31:0] di_int; + wire [3:0] dip_int; + wire en_int, clk_int, we_int, ssr_int; + + tri0 GSR = glbl.GSR; + + always @(GSR) + if (GSR) begin + assign do0_out = INIT[0]; + assign do1_out = INIT[1]; + assign do2_out = INIT[2]; + assign do3_out = INIT[3]; + assign do4_out = INIT[4]; + assign do5_out = INIT[5]; + assign do6_out = INIT[6]; + assign do7_out = INIT[7]; + assign do8_out = INIT[8]; + assign do9_out = INIT[9]; + assign do10_out = INIT[10]; + assign do11_out = INIT[11]; + assign do12_out = INIT[12]; + assign do13_out = INIT[13]; + assign do14_out = INIT[14]; + assign do15_out = INIT[15]; + assign do16_out = INIT[16]; + assign do17_out = INIT[17]; + assign do18_out = INIT[18]; + assign do19_out = INIT[19]; + assign do20_out = INIT[20]; + assign do21_out = INIT[21]; + assign do22_out = INIT[22]; + assign do23_out = INIT[23]; + assign do24_out = INIT[24]; + assign do25_out = INIT[25]; + assign do26_out = INIT[26]; + assign do27_out = INIT[27]; + assign do28_out = INIT[28]; + assign do29_out = INIT[29]; + assign do30_out = INIT[30]; + assign do31_out = INIT[31]; + assign dop0_out = INIT[32]; + assign dop1_out = INIT[33]; + assign dop2_out = INIT[34]; + assign dop3_out = INIT[35]; + end + else begin + deassign do0_out; + deassign do1_out; + deassign do2_out; + deassign do3_out; + deassign do4_out; + deassign do5_out; + deassign do6_out; + deassign do7_out; + deassign do8_out; + deassign do9_out; + deassign do10_out; + deassign do11_out; + deassign do12_out; + deassign do13_out; + deassign do14_out; + deassign do15_out; + deassign do16_out; + deassign do17_out; + deassign do18_out; + deassign do19_out; + deassign do20_out; + deassign do21_out; + deassign do22_out; + deassign do23_out; + deassign do24_out; + deassign do25_out; + deassign do26_out; + deassign do27_out; + deassign do28_out; + deassign do29_out; + deassign do30_out; + deassign do31_out; + deassign dop0_out; + deassign dop1_out; + deassign dop2_out; + deassign dop3_out; + end + + buf b_do_out0 (DO[0], do0_out); + buf b_do_out1 (DO[1], do1_out); + buf b_do_out2 (DO[2], do2_out); + buf b_do_out3 (DO[3], do3_out); + buf b_do_out4 (DO[4], do4_out); + buf b_do_out5 (DO[5], do5_out); + buf b_do_out6 (DO[6], do6_out); + buf b_do_out7 (DO[7], do7_out); + buf b_do_out8 (DO[8], do8_out); + buf b_do_out9 (DO[9], do9_out); + buf b_do_out10 (DO[10], do10_out); + buf b_do_out11 (DO[11], do11_out); + buf b_do_out12 (DO[12], do12_out); + buf b_do_out13 (DO[13], do13_out); + buf b_do_out14 (DO[14], do14_out); + buf b_do_out15 (DO[15], do15_out); + buf b_do_out16 (DO[16], do16_out); + buf b_do_out17 (DO[17], do17_out); + buf b_do_out18 (DO[18], do18_out); + buf b_do_out19 (DO[19], do19_out); + buf b_do_out20 (DO[20], do20_out); + buf b_do_out21 (DO[21], do21_out); + buf b_do_out22 (DO[22], do22_out); + buf b_do_out23 (DO[23], do23_out); + buf b_do_out24 (DO[24], do24_out); + buf b_do_out25 (DO[25], do25_out); + buf b_do_out26 (DO[26], do26_out); + buf b_do_out27 (DO[27], do27_out); + buf b_do_out28 (DO[28], do28_out); + buf b_do_out29 (DO[29], do29_out); + buf b_do_out30 (DO[30], do30_out); + buf b_do_out31 (DO[31], do31_out); + buf b_dop_out0 (DOP[0], dop0_out); + buf b_dop_out1 (DOP[1], dop1_out); + buf b_dop_out2 (DOP[2], dop2_out); + buf b_dop_out3 (DOP[3], dop3_out); + buf b_addr_0 (addr_int[0], ADDR[0]); + buf b_addr_1 (addr_int[1], ADDR[1]); + buf b_addr_2 (addr_int[2], ADDR[2]); + buf b_addr_3 (addr_int[3], ADDR[3]); + buf b_addr_4 (addr_int[4], ADDR[4]); + buf b_addr_5 (addr_int[5], ADDR[5]); + buf b_addr_6 (addr_int[6], ADDR[6]); + buf b_addr_7 (addr_int[7], ADDR[7]); + buf b_addr_8 (addr_int[8], ADDR[8]); + buf b_di_0 (di_int[0], DI[0]); + buf b_di_1 (di_int[1], DI[1]); + buf b_di_2 (di_int[2], DI[2]); + buf b_di_3 (di_int[3], DI[3]); + buf b_di_4 (di_int[4], DI[4]); + buf b_di_5 (di_int[5], DI[5]); + buf b_di_6 (di_int[6], DI[6]); + buf b_di_7 (di_int[7], DI[7]); + buf b_di_8 (di_int[8], DI[8]); + buf b_di_9 (di_int[9], DI[9]); + buf b_di_10 (di_int[10], DI[10]); + buf b_di_11 (di_int[11], DI[11]); + buf b_di_12 (di_int[12], DI[12]); + buf b_di_13 (di_int[13], DI[13]); + buf b_di_14 (di_int[14], DI[14]); + buf b_di_15 (di_int[15], DI[15]); + buf b_di_16 (di_int[16], DI[16]); + buf b_di_17 (di_int[17], DI[17]); + buf b_di_18 (di_int[18], DI[18]); + buf b_di_19 (di_int[19], DI[19]); + buf b_di_20 (di_int[20], DI[20]); + buf b_di_21 (di_int[21], DI[21]); + buf b_di_22 (di_int[22], DI[22]); + buf b_di_23 (di_int[23], DI[23]); + buf b_di_24 (di_int[24], DI[24]); + buf b_di_25 (di_int[25], DI[25]); + buf b_di_26 (di_int[26], DI[26]); + buf b_di_27 (di_int[27], DI[27]); + buf b_di_28 (di_int[28], DI[28]); + buf b_di_29 (di_int[29], DI[29]); + buf b_di_30 (di_int[30], DI[30]); + buf b_di_31 (di_int[31], DI[31]); + buf b_dip_0 (dip_int[0], DIP[0]); + buf b_dip_1 (dip_int[1], DIP[1]); + buf b_dip_2 (dip_int[2], DIP[2]); + buf b_dip_3 (dip_int[3], DIP[3]); + buf b_en (en_int, EN); + buf b_clk (clk_int, CLK); + buf b_we (we_int, WE); + buf b_ssr (ssr_int, SSR); + + initial begin + for (count = 0; count < 256; count = count + 1) begin + mem[count] <= INIT_00[count]; + mem[256 * 1 + count] <= INIT_01[count]; + mem[256 * 2 + count] <= INIT_02[count]; + mem[256 * 3 + count] <= INIT_03[count]; + mem[256 * 4 + count] <= INIT_04[count]; + mem[256 * 5 + count] <= INIT_05[count]; + mem[256 * 6 + count] <= INIT_06[count]; + mem[256 * 7 + count] <= INIT_07[count]; + mem[256 * 8 + count] <= INIT_08[count]; + mem[256 * 9 + count] <= INIT_09[count]; + mem[256 * 10 + count] <= INIT_0A[count]; + mem[256 * 11 + count] <= INIT_0B[count]; + mem[256 * 12 + count] <= INIT_0C[count]; + mem[256 * 13 + count] <= INIT_0D[count]; + mem[256 * 14 + count] <= INIT_0E[count]; + mem[256 * 15 + count] <= INIT_0F[count]; + mem[256 * 16 + count] <= INIT_10[count]; + mem[256 * 17 + count] <= INIT_11[count]; + mem[256 * 18 + count] <= INIT_12[count]; + mem[256 * 19 + count] <= INIT_13[count]; + mem[256 * 20 + count] <= INIT_14[count]; + mem[256 * 21 + count] <= INIT_15[count]; + mem[256 * 22 + count] <= INIT_16[count]; + mem[256 * 23 + count] <= INIT_17[count]; + mem[256 * 24 + count] <= INIT_18[count]; + mem[256 * 25 + count] <= INIT_19[count]; + mem[256 * 26 + count] <= INIT_1A[count]; + mem[256 * 27 + count] <= INIT_1B[count]; + mem[256 * 28 + count] <= INIT_1C[count]; + mem[256 * 29 + count] <= INIT_1D[count]; + mem[256 * 30 + count] <= INIT_1E[count]; + mem[256 * 31 + count] <= INIT_1F[count]; + mem[256 * 32 + count] <= INIT_20[count]; + mem[256 * 33 + count] <= INIT_21[count]; + mem[256 * 34 + count] <= INIT_22[count]; + mem[256 * 35 + count] <= INIT_23[count]; + mem[256 * 36 + count] <= INIT_24[count]; + mem[256 * 37 + count] <= INIT_25[count]; + mem[256 * 38 + count] <= INIT_26[count]; + mem[256 * 39 + count] <= INIT_27[count]; + mem[256 * 40 + count] <= INIT_28[count]; + mem[256 * 41 + count] <= INIT_29[count]; + mem[256 * 42 + count] <= INIT_2A[count]; + mem[256 * 43 + count] <= INIT_2B[count]; + mem[256 * 44 + count] <= INIT_2C[count]; + mem[256 * 45 + count] <= INIT_2D[count]; + mem[256 * 46 + count] <= INIT_2E[count]; + mem[256 * 47 + count] <= INIT_2F[count]; + mem[256 * 48 + count] <= INIT_30[count]; + mem[256 * 49 + count] <= INIT_31[count]; + mem[256 * 50 + count] <= INIT_32[count]; + mem[256 * 51 + count] <= INIT_33[count]; + mem[256 * 52 + count] <= INIT_34[count]; + mem[256 * 53 + count] <= INIT_35[count]; + mem[256 * 54 + count] <= INIT_36[count]; + mem[256 * 55 + count] <= INIT_37[count]; + mem[256 * 56 + count] <= INIT_38[count]; + mem[256 * 57 + count] <= INIT_39[count]; + mem[256 * 58 + count] <= INIT_3A[count]; + mem[256 * 59 + count] <= INIT_3B[count]; + mem[256 * 60 + count] <= INIT_3C[count]; + mem[256 * 61 + count] <= INIT_3D[count]; + mem[256 * 62 + count] <= INIT_3E[count]; + mem[256 * 63 + count] <= INIT_3F[count]; + mem[256 * 64 + count] <= INITP_00[count]; + mem[256 * 65 + count] <= INITP_01[count]; + mem[256 * 66 + count] <= INITP_02[count]; + mem[256 * 67 + count] <= INITP_03[count]; + mem[256 * 68 + count] <= INITP_04[count]; + mem[256 * 69 + count] <= INITP_05[count]; + mem[256 * 70 + count] <= INITP_06[count]; + mem[256 * 71 + count] <= INITP_07[count]; + end + end + + initial begin + case (WRITE_MODE) + "WRITE_FIRST" : wr_mode <= 2'b00; + "READ_FIRST" : wr_mode <= 2'b01; + "NO_CHANGE" : wr_mode <= 2'b10; + default : begin + $display("Attribute Syntax Error : The attribute WRITE_MODE on RAMB16_S36 instance %m is set to %s. The legal values for this attribute are WRITE_FIRST, READ_FIRST or NO_CHANGE.", WRITE_MODE); + $finish; + end + endcase + end + + always @(posedge clk_int) begin + if (en_int == 1'b1) begin + if (ssr_int == 1'b1) begin + do0_out <= SRVAL[0]; + do1_out <= SRVAL[1]; + do2_out <= SRVAL[2]; + do3_out <= SRVAL[3]; + do4_out <= SRVAL[4]; + do5_out <= SRVAL[5]; + do6_out <= SRVAL[6]; + do7_out <= SRVAL[7]; + do8_out <= SRVAL[8]; + do9_out <= SRVAL[9]; + do10_out <= SRVAL[10]; + do11_out <= SRVAL[11]; + do12_out <= SRVAL[12]; + do13_out <= SRVAL[13]; + do14_out <= SRVAL[14]; + do15_out <= SRVAL[15]; + do16_out <= SRVAL[16]; + do17_out <= SRVAL[17]; + do18_out <= SRVAL[18]; + do19_out <= SRVAL[19]; + do20_out <= SRVAL[20]; + do21_out <= SRVAL[21]; + do22_out <= SRVAL[22]; + do23_out <= SRVAL[23]; + do24_out <= SRVAL[24]; + do25_out <= SRVAL[25]; + do26_out <= SRVAL[26]; + do27_out <= SRVAL[27]; + do28_out <= SRVAL[28]; + do29_out <= SRVAL[29]; + do30_out <= SRVAL[30]; + do31_out <= SRVAL[31]; + dop0_out <= SRVAL[32]; + dop1_out <= SRVAL[33]; + dop2_out <= SRVAL[34]; + dop3_out <= SRVAL[35]; + end + else begin + if (we_int == 1'b1) begin + if (wr_mode == 2'b00) begin + do0_out <= di_int[0]; + do1_out <= di_int[1]; + do2_out <= di_int[2]; + do3_out <= di_int[3]; + do4_out <= di_int[4]; + do5_out <= di_int[5]; + do6_out <= di_int[6]; + do7_out <= di_int[7]; + do8_out <= di_int[8]; + do9_out <= di_int[9]; + do10_out <= di_int[10]; + do11_out <= di_int[11]; + do12_out <= di_int[12]; + do13_out <= di_int[13]; + do14_out <= di_int[14]; + do15_out <= di_int[15]; + do16_out <= di_int[16]; + do17_out <= di_int[17]; + do18_out <= di_int[18]; + do19_out <= di_int[19]; + do20_out <= di_int[20]; + do21_out <= di_int[21]; + do22_out <= di_int[22]; + do23_out <= di_int[23]; + do24_out <= di_int[24]; + do25_out <= di_int[25]; + do26_out <= di_int[26]; + do27_out <= di_int[27]; + do28_out <= di_int[28]; + do29_out <= di_int[29]; + do30_out <= di_int[30]; + do31_out <= di_int[31]; + dop0_out <= dip_int[0]; + dop1_out <= dip_int[1]; + dop2_out <= dip_int[2]; + dop3_out <= dip_int[3]; + end + else if (wr_mode == 2'b01) begin + do0_out <= mem[addr_int * 32 + 0]; + do1_out <= mem[addr_int * 32 + 1]; + do2_out <= mem[addr_int * 32 + 2]; + do3_out <= mem[addr_int * 32 + 3]; + do4_out <= mem[addr_int * 32 + 4]; + do5_out <= mem[addr_int * 32 + 5]; + do6_out <= mem[addr_int * 32 + 6]; + do7_out <= mem[addr_int * 32 + 7]; + do8_out <= mem[addr_int * 32 + 8]; + do9_out <= mem[addr_int * 32 + 9]; + do10_out <= mem[addr_int * 32 + 10]; + do11_out <= mem[addr_int * 32 + 11]; + do12_out <= mem[addr_int * 32 + 12]; + do13_out <= mem[addr_int * 32 + 13]; + do14_out <= mem[addr_int * 32 + 14]; + do15_out <= mem[addr_int * 32 + 15]; + do16_out <= mem[addr_int * 32 + 16]; + do17_out <= mem[addr_int * 32 + 17]; + do18_out <= mem[addr_int * 32 + 18]; + do19_out <= mem[addr_int * 32 + 19]; + do20_out <= mem[addr_int * 32 + 20]; + do21_out <= mem[addr_int * 32 + 21]; + do22_out <= mem[addr_int * 32 + 22]; + do23_out <= mem[addr_int * 32 + 23]; + do24_out <= mem[addr_int * 32 + 24]; + do25_out <= mem[addr_int * 32 + 25]; + do26_out <= mem[addr_int * 32 + 26]; + do27_out <= mem[addr_int * 32 + 27]; + do28_out <= mem[addr_int * 32 + 28]; + do29_out <= mem[addr_int * 32 + 29]; + do30_out <= mem[addr_int * 32 + 30]; + do31_out <= mem[addr_int * 32 + 31]; + dop0_out <= mem[16384 + addr_int * 4 + 0]; + dop1_out <= mem[16384 + addr_int * 4 + 1]; + dop2_out <= mem[16384 + addr_int * 4 + 2]; + dop3_out <= mem[16384 + addr_int * 4 + 3]; + end + else begin + do0_out <= do0_out; + do1_out <= do1_out; + do2_out <= do2_out; + do3_out <= do3_out; + do4_out <= do4_out; + do5_out <= do5_out; + do6_out <= do6_out; + do7_out <= do7_out; + do8_out <= do8_out; + do9_out <= do9_out; + do10_out <= do10_out; + do11_out <= do11_out; + do12_out <= do12_out; + do13_out <= do13_out; + do14_out <= do14_out; + do15_out <= do15_out; + do16_out <= do16_out; + do17_out <= do17_out; + do18_out <= do18_out; + do19_out <= do19_out; + do20_out <= do20_out; + do21_out <= do21_out; + do22_out <= do22_out; + do23_out <= do23_out; + do24_out <= do24_out; + do25_out <= do25_out; + do26_out <= do26_out; + do27_out <= do27_out; + do28_out <= do28_out; + do29_out <= do29_out; + do30_out <= do30_out; + do31_out <= do31_out; + dop0_out <= dop0_out; + dop1_out <= dop1_out; + dop2_out <= dop2_out; + dop3_out <= dop3_out; + end + end + else begin + do0_out <= mem[addr_int * 32 + 0]; + do1_out <= mem[addr_int * 32 + 1]; + do2_out <= mem[addr_int * 32 + 2]; + do3_out <= mem[addr_int * 32 + 3]; + do4_out <= mem[addr_int * 32 + 4]; + do5_out <= mem[addr_int * 32 + 5]; + do6_out <= mem[addr_int * 32 + 6]; + do7_out <= mem[addr_int * 32 + 7]; + do8_out <= mem[addr_int * 32 + 8]; + do9_out <= mem[addr_int * 32 + 9]; + do10_out <= mem[addr_int * 32 + 10]; + do11_out <= mem[addr_int * 32 + 11]; + do12_out <= mem[addr_int * 32 + 12]; + do13_out <= mem[addr_int * 32 + 13]; + do14_out <= mem[addr_int * 32 + 14]; + do15_out <= mem[addr_int * 32 + 15]; + do16_out <= mem[addr_int * 32 + 16]; + do17_out <= mem[addr_int * 32 + 17]; + do18_out <= mem[addr_int * 32 + 18]; + do19_out <= mem[addr_int * 32 + 19]; + do20_out <= mem[addr_int * 32 + 20]; + do21_out <= mem[addr_int * 32 + 21]; + do22_out <= mem[addr_int * 32 + 22]; + do23_out <= mem[addr_int * 32 + 23]; + do24_out <= mem[addr_int * 32 + 24]; + do25_out <= mem[addr_int * 32 + 25]; + do26_out <= mem[addr_int * 32 + 26]; + do27_out <= mem[addr_int * 32 + 27]; + do28_out <= mem[addr_int * 32 + 28]; + do29_out <= mem[addr_int * 32 + 29]; + do30_out <= mem[addr_int * 32 + 30]; + do31_out <= mem[addr_int * 32 + 31]; + dop0_out <= mem[16384 + addr_int * 4 + 0]; + dop1_out <= mem[16384 + addr_int * 4 + 1]; + dop2_out <= mem[16384 + addr_int * 4 + 2]; + dop3_out <= mem[16384 + addr_int * 4 + 3]; + end + end + end + end + + always @(posedge clk_int) begin + if (en_int == 1'b1 && we_int == 1'b1) begin + mem[addr_int * 32 + 0] <= di_int[0]; + mem[addr_int * 32 + 1] <= di_int[1]; + mem[addr_int * 32 + 2] <= di_int[2]; + mem[addr_int * 32 + 3] <= di_int[3]; + mem[addr_int * 32 + 4] <= di_int[4]; + mem[addr_int * 32 + 5] <= di_int[5]; + mem[addr_int * 32 + 6] <= di_int[6]; + mem[addr_int * 32 + 7] <= di_int[7]; + mem[addr_int * 32 + 8] <= di_int[8]; + mem[addr_int * 32 + 9] <= di_int[9]; + mem[addr_int * 32 + 10] <= di_int[10]; + mem[addr_int * 32 + 11] <= di_int[11]; + mem[addr_int * 32 + 12] <= di_int[12]; + mem[addr_int * 32 + 13] <= di_int[13]; + mem[addr_int * 32 + 14] <= di_int[14]; + mem[addr_int * 32 + 15] <= di_int[15]; + mem[addr_int * 32 + 16] <= di_int[16]; + mem[addr_int * 32 + 17] <= di_int[17]; + mem[addr_int * 32 + 18] <= di_int[18]; + mem[addr_int * 32 + 19] <= di_int[19]; + mem[addr_int * 32 + 20] <= di_int[20]; + mem[addr_int * 32 + 21] <= di_int[21]; + mem[addr_int * 32 + 22] <= di_int[22]; + mem[addr_int * 32 + 23] <= di_int[23]; + mem[addr_int * 32 + 24] <= di_int[24]; + mem[addr_int * 32 + 25] <= di_int[25]; + mem[addr_int * 32 + 26] <= di_int[26]; + mem[addr_int * 32 + 27] <= di_int[27]; + mem[addr_int * 32 + 28] <= di_int[28]; + mem[addr_int * 32 + 29] <= di_int[29]; + mem[addr_int * 32 + 30] <= di_int[30]; + mem[addr_int * 32 + 31] <= di_int[31]; + mem[16384 + addr_int * 4 + 0] <= dip_int[0]; + mem[16384 + addr_int * 4 + 1] <= dip_int[1]; + mem[16384 + addr_int * 4 + 2] <= dip_int[2]; + mem[16384 + addr_int * 4 + 3] <= dip_int[3]; + end + end + + specify + (CLK *> DO) = (100, 100); + (CLK *> DOP) = (100, 100); + endspecify + +endmodule + +`else + +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/RAMB16_S36.v,v 1.6 2005/03/14 22:54:41 wloo Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2005 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Timing Simulation Library Component +// / / 16K-Bit Data and 2K-Bit Parity Single Port Block RAM +// /___/ /\ Filename : RAMB16_S36.v +// \ \ / \ Timestamp : Thu Mar 10 16:44:01 PST 2005 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 03/10/05 - Initialized outputs. +// End Revision + +`timescale 1 ps/1 ps + +module RAMB16_S36 (DO, DOP, ADDR, CLK, DI, DIP, EN, SSR, WE); + + parameter INIT = 36'h0; + parameter SRVAL = 36'h0; + parameter WRITE_MODE = "WRITE_FIRST"; + + parameter INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + + output [31:0] DO; + output [3:0] DOP; + + input [8:0] ADDR; + input [31:0] DI; + input [3:0] DIP; + input EN, CLK, WE, SSR; + + reg [31:0] do_out = INIT[31:0]; + reg [3:0] dop_out = INIT[35:32]; + + reg [31:0] mem [511:0]; + reg [3:0] memp [511:0]; + + reg [8:0] count, countp; + reg [1:0] wr_mode; + + wire [8:0] addr_int; + wire [31:0] di_int; + wire [3:0] dip_int; + wire en_int, clk_int, we_int, ssr_int; + + wire di_enable = en_int && we_int; + + tri0 GSR = glbl.GSR; + wire gsr_int; + + buf b_gsr (gsr_int, GSR); + + buf b_do [31:0] (DO, do_out); + buf b_dop [3:0] (DOP, dop_out); + buf b_addr [8:0] (addr_int, ADDR); + buf b_di [31:0] (di_int, DI); + buf b_dip [3:0] (dip_int, DIP); + buf b_en (en_int, EN); + buf b_clk (clk_int, CLK); + buf b_ssr (ssr_int, SSR); + buf b_we (we_int, WE); + + + always @(gsr_int) + if (gsr_int) begin + assign {dop_out, do_out} = INIT; + end + else begin + deassign do_out; + deassign dop_out; + end + + + initial begin + + for (count = 0; count < 8; count = count + 1) begin + mem[count] = INIT_00[(count * 32) +: 32]; + mem[8 * 1 + count] = INIT_01[(count * 32) +: 32]; + mem[8 * 2 + count] = INIT_02[(count * 32) +: 32]; + mem[8 * 3 + count] = INIT_03[(count * 32) +: 32]; + mem[8 * 4 + count] = INIT_04[(count * 32) +: 32]; + mem[8 * 5 + count] = INIT_05[(count * 32) +: 32]; + mem[8 * 6 + count] = INIT_06[(count * 32) +: 32]; + mem[8 * 7 + count] = INIT_07[(count * 32) +: 32]; + mem[8 * 8 + count] = INIT_08[(count * 32) +: 32]; + mem[8 * 9 + count] = INIT_09[(count * 32) +: 32]; + mem[8 * 10 + count] = INIT_0A[(count * 32) +: 32]; + mem[8 * 11 + count] = INIT_0B[(count * 32) +: 32]; + mem[8 * 12 + count] = INIT_0C[(count * 32) +: 32]; + mem[8 * 13 + count] = INIT_0D[(count * 32) +: 32]; + mem[8 * 14 + count] = INIT_0E[(count * 32) +: 32]; + mem[8 * 15 + count] = INIT_0F[(count * 32) +: 32]; + mem[8 * 16 + count] = INIT_10[(count * 32) +: 32]; + mem[8 * 17 + count] = INIT_11[(count * 32) +: 32]; + mem[8 * 18 + count] = INIT_12[(count * 32) +: 32]; + mem[8 * 19 + count] = INIT_13[(count * 32) +: 32]; + mem[8 * 20 + count] = INIT_14[(count * 32) +: 32]; + mem[8 * 21 + count] = INIT_15[(count * 32) +: 32]; + mem[8 * 22 + count] = INIT_16[(count * 32) +: 32]; + mem[8 * 23 + count] = INIT_17[(count * 32) +: 32]; + mem[8 * 24 + count] = INIT_18[(count * 32) +: 32]; + mem[8 * 25 + count] = INIT_19[(count * 32) +: 32]; + mem[8 * 26 + count] = INIT_1A[(count * 32) +: 32]; + mem[8 * 27 + count] = INIT_1B[(count * 32) +: 32]; + mem[8 * 28 + count] = INIT_1C[(count * 32) +: 32]; + mem[8 * 29 + count] = INIT_1D[(count * 32) +: 32]; + mem[8 * 30 + count] = INIT_1E[(count * 32) +: 32]; + mem[8 * 31 + count] = INIT_1F[(count * 32) +: 32]; + mem[8 * 32 + count] = INIT_20[(count * 32) +: 32]; + mem[8 * 33 + count] = INIT_21[(count * 32) +: 32]; + mem[8 * 34 + count] = INIT_22[(count * 32) +: 32]; + mem[8 * 35 + count] = INIT_23[(count * 32) +: 32]; + mem[8 * 36 + count] = INIT_24[(count * 32) +: 32]; + mem[8 * 37 + count] = INIT_25[(count * 32) +: 32]; + mem[8 * 38 + count] = INIT_26[(count * 32) +: 32]; + mem[8 * 39 + count] = INIT_27[(count * 32) +: 32]; + mem[8 * 40 + count] = INIT_28[(count * 32) +: 32]; + mem[8 * 41 + count] = INIT_29[(count * 32) +: 32]; + mem[8 * 42 + count] = INIT_2A[(count * 32) +: 32]; + mem[8 * 43 + count] = INIT_2B[(count * 32) +: 32]; + mem[8 * 44 + count] = INIT_2C[(count * 32) +: 32]; + mem[8 * 45 + count] = INIT_2D[(count * 32) +: 32]; + mem[8 * 46 + count] = INIT_2E[(count * 32) +: 32]; + mem[8 * 47 + count] = INIT_2F[(count * 32) +: 32]; + mem[8 * 48 + count] = INIT_30[(count * 32) +: 32]; + mem[8 * 49 + count] = INIT_31[(count * 32) +: 32]; + mem[8 * 50 + count] = INIT_32[(count * 32) +: 32]; + mem[8 * 51 + count] = INIT_33[(count * 32) +: 32]; + mem[8 * 52 + count] = INIT_34[(count * 32) +: 32]; + mem[8 * 53 + count] = INIT_35[(count * 32) +: 32]; + mem[8 * 54 + count] = INIT_36[(count * 32) +: 32]; + mem[8 * 55 + count] = INIT_37[(count * 32) +: 32]; + mem[8 * 56 + count] = INIT_38[(count * 32) +: 32]; + mem[8 * 57 + count] = INIT_39[(count * 32) +: 32]; + mem[8 * 58 + count] = INIT_3A[(count * 32) +: 32]; + mem[8 * 59 + count] = INIT_3B[(count * 32) +: 32]; + mem[8 * 60 + count] = INIT_3C[(count * 32) +: 32]; + mem[8 * 61 + count] = INIT_3D[(count * 32) +: 32]; + mem[8 * 62 + count] = INIT_3E[(count * 32) +: 32]; + mem[8 * 63 + count] = INIT_3F[(count * 32) +: 32]; + end + +// initiate parity start + for (countp = 0; countp < 64; countp = countp + 1) begin + memp[countp] = INITP_00[(countp * 4) +: 4]; + memp[64 * 1 + countp] = INITP_01[(countp * 4) +: 4]; + memp[64 * 2 + countp] = INITP_02[(countp * 4) +: 4]; + memp[64 * 3 + countp] = INITP_03[(countp * 4) +: 4]; + memp[64 * 4 + countp] = INITP_04[(countp * 4) +: 4]; + memp[64 * 5 + countp] = INITP_05[(countp * 4) +: 4]; + memp[64 * 6 + countp] = INITP_06[(countp * 4) +: 4]; + memp[64 * 7 + countp] = INITP_07[(countp * 4) +: 4]; + end +// initiate parity end + end // initial begin + + + initial begin + case (WRITE_MODE) + "WRITE_FIRST" : wr_mode <= 2'b00; + "READ_FIRST" : wr_mode <= 2'b01; + "NO_CHANGE" : wr_mode <= 2'b10; + default : begin + $display("Attribute Syntax Error : The Attribute WRITE_MODE on RAMB16_S36 instance %m is set to %s. Legal values for this attribute are WRITE_FIRST, READ_FIRST or NO_CHANGE.", WRITE_MODE); + $finish; + end + endcase + end + + + always @(posedge clk_int) begin + + if (en_int == 1'b1) begin + + if (ssr_int == 1'b1) begin + {dop_out, do_out} <= #100 SRVAL; + end + else begin + if (we_int == 1'b1) begin + if (wr_mode == 2'b00) begin + do_out <= #100 di_int; + dop_out <= #100 dip_int; + end + else if (wr_mode == 2'b01) begin + do_out <= #100 mem[addr_int]; + dop_out <= #100 memp[addr_int]; + end + end + else begin + do_out <= #100 mem[addr_int]; + dop_out <= #100 memp[addr_int]; + end + end + + // memory + if (we_int == 1'b1) begin + mem[addr_int] <= di_int; + memp[addr_int] <= dip_int; + end + + end + end + + +endmodule + +`endif diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/RAMB16_S36_S36.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/RAMB16_S36_S36.v new file mode 100644 index 0000000..f1a92c7 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/RAMB16_S36_S36.v @@ -0,0 +1,2194 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/RAMB16_S36_S36.v,v 1.10 2007/02/22 01:58:06 wloo Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2005 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / 16K-Bit Data and 2K-Bit Parity Dual Port Block RAM +// /___/ /\ Filename : RAMB16_S36_S36.v +// \ \ / \ Timestamp : Thu Mar 10 16:43:36 PST 2005 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// End Revision + +`ifdef legacy_model + +`timescale 1 ps / 1 ps + +module RAMB16_S36_S36 (DOA, DOB, DOPA, DOPB, ADDRA, ADDRB, CLKA, CLKB, DIA, DIB, DIPA, DIPB, ENA, ENB, SSRA, SSRB, WEA, WEB); + + parameter INIT_A = 36'h0; + parameter INIT_B = 36'h0; + parameter SRVAL_A = 36'h0; + parameter SRVAL_B = 36'h0; + parameter WRITE_MODE_A = "WRITE_FIRST"; + parameter WRITE_MODE_B = "WRITE_FIRST"; + parameter SIM_COLLISION_CHECK = "ALL"; + localparam SETUP_ALL = 1000; + localparam SETUP_READ_FIRST = 3000; + + parameter INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + + output [31:0] DOA; + output [3:0] DOPA; + reg [31:0] doa_out; + reg [3:0] dopa_out; + wire doa_out0, doa_out1, doa_out2, doa_out3, doa_out4, doa_out5, doa_out6, doa_out7, doa_out8, doa_out9, doa_out10, doa_out11, doa_out12, doa_out13, doa_out14, doa_out15, doa_out16, doa_out17, doa_out18, doa_out19, doa_out20, doa_out21, doa_out22, doa_out23, doa_out24, doa_out25, doa_out26, doa_out27, doa_out28, doa_out29, doa_out30, doa_out31; + wire dopa0_out, dopa1_out, dopa2_out, dopa3_out; + + input [8:0] ADDRA; + input [31:0] DIA; + input [3:0] DIPA; + input ENA, CLKA, WEA, SSRA; + + output [31:0] DOB; + output [3:0] DOPB; + reg [31:0] dob_out; + reg [3:0] dopb_out; + wire dob_out0, dob_out1, dob_out2, dob_out3, dob_out4, dob_out5, dob_out6, dob_out7, dob_out8, dob_out9, dob_out10, dob_out11, dob_out12, dob_out13, dob_out14, dob_out15, dob_out16, dob_out17, dob_out18, dob_out19, dob_out20, dob_out21, dob_out22, dob_out23, dob_out24, dob_out25, dob_out26, dob_out27, dob_out28, dob_out29, dob_out30, dob_out31; + wire dopb0_out, dopb1_out, dopb2_out, dopb3_out; + + input [8:0] ADDRB; + input [31:0] DIB; + input [3:0] DIPB; + input ENB, CLKB, WEB, SSRB; + + reg [18431:0] mem; + reg [8:0] count; + reg [1:0] wr_mode_a, wr_mode_b; + + reg [5:0] dmi, dbi; + reg [5:0] pmi, pbi; + + wire [8:0] addra_int; + reg [8:0] addra_reg; + wire [31:0] dia_int; + wire [3:0] dipa_int; + wire ena_int, clka_int, wea_int, ssra_int; + reg ena_reg, wea_reg, ssra_reg; + wire [8:0] addrb_int; + reg [8:0] addrb_reg; + wire [31:0] dib_int; + wire [3:0] dipb_int; + wire enb_int, clkb_int, web_int, ssrb_int; + reg display_flag; + reg enb_reg, web_reg, ssrb_reg; + + time time_clka, time_clkb; + time time_clka_clkb; + time time_clkb_clka; + + reg setup_all_a_b; + reg setup_all_b_a; + reg setup_zero; + reg setup_rf_a_b; + reg setup_rf_b_a; + reg [1:0] data_collision, data_collision_a_b, data_collision_b_a; + reg memory_collision, memory_collision_a_b, memory_collision_b_a; + reg address_collision, address_collision_a_b, address_collision_b_a; + reg change_clka; + reg change_clkb; + + wire [14:0] data_addra_int; + wire [14:0] data_addra_reg; + wire [14:0] data_addrb_int; + wire [14:0] data_addrb_reg; + wire [15:0] parity_addra_int; + wire [15:0] parity_addra_reg; + wire [15:0] parity_addrb_int; + wire [15:0] parity_addrb_reg; + + tri0 GSR = glbl.GSR; + + always @(GSR) + if (GSR) begin + assign doa_out = INIT_A[31:0]; + assign dopa_out = INIT_A[35:32]; + assign dob_out = INIT_B[31:0]; + assign dopb_out = INIT_B[35:32]; + end + else begin + deassign doa_out; + deassign dopa_out; + deassign dob_out; + deassign dopb_out; + end + + buf b_doa_out0 (doa_out0, doa_out[0]); + buf b_doa_out1 (doa_out1, doa_out[1]); + buf b_doa_out2 (doa_out2, doa_out[2]); + buf b_doa_out3 (doa_out3, doa_out[3]); + buf b_doa_out4 (doa_out4, doa_out[4]); + buf b_doa_out5 (doa_out5, doa_out[5]); + buf b_doa_out6 (doa_out6, doa_out[6]); + buf b_doa_out7 (doa_out7, doa_out[7]); + buf b_doa_out8 (doa_out8, doa_out[8]); + buf b_doa_out9 (doa_out9, doa_out[9]); + buf b_doa_out10 (doa_out10, doa_out[10]); + buf b_doa_out11 (doa_out11, doa_out[11]); + buf b_doa_out12 (doa_out12, doa_out[12]); + buf b_doa_out13 (doa_out13, doa_out[13]); + buf b_doa_out14 (doa_out14, doa_out[14]); + buf b_doa_out15 (doa_out15, doa_out[15]); + buf b_doa_out16 (doa_out16, doa_out[16]); + buf b_doa_out17 (doa_out17, doa_out[17]); + buf b_doa_out18 (doa_out18, doa_out[18]); + buf b_doa_out19 (doa_out19, doa_out[19]); + buf b_doa_out20 (doa_out20, doa_out[20]); + buf b_doa_out21 (doa_out21, doa_out[21]); + buf b_doa_out22 (doa_out22, doa_out[22]); + buf b_doa_out23 (doa_out23, doa_out[23]); + buf b_doa_out24 (doa_out24, doa_out[24]); + buf b_doa_out25 (doa_out25, doa_out[25]); + buf b_doa_out26 (doa_out26, doa_out[26]); + buf b_doa_out27 (doa_out27, doa_out[27]); + buf b_doa_out28 (doa_out28, doa_out[28]); + buf b_doa_out29 (doa_out29, doa_out[29]); + buf b_doa_out30 (doa_out30, doa_out[30]); + buf b_doa_out31 (doa_out31, doa_out[31]); + buf b_dopa_out0 (dopa_out0, dopa_out[0]); + buf b_dopa_out1 (dopa_out1, dopa_out[1]); + buf b_dopa_out2 (dopa_out2, dopa_out[2]); + buf b_dopa_out3 (dopa_out3, dopa_out[3]); + buf b_dob_out0 (dob_out0, dob_out[0]); + buf b_dob_out1 (dob_out1, dob_out[1]); + buf b_dob_out2 (dob_out2, dob_out[2]); + buf b_dob_out3 (dob_out3, dob_out[3]); + buf b_dob_out4 (dob_out4, dob_out[4]); + buf b_dob_out5 (dob_out5, dob_out[5]); + buf b_dob_out6 (dob_out6, dob_out[6]); + buf b_dob_out7 (dob_out7, dob_out[7]); + buf b_dob_out8 (dob_out8, dob_out[8]); + buf b_dob_out9 (dob_out9, dob_out[9]); + buf b_dob_out10 (dob_out10, dob_out[10]); + buf b_dob_out11 (dob_out11, dob_out[11]); + buf b_dob_out12 (dob_out12, dob_out[12]); + buf b_dob_out13 (dob_out13, dob_out[13]); + buf b_dob_out14 (dob_out14, dob_out[14]); + buf b_dob_out15 (dob_out15, dob_out[15]); + buf b_dob_out16 (dob_out16, dob_out[16]); + buf b_dob_out17 (dob_out17, dob_out[17]); + buf b_dob_out18 (dob_out18, dob_out[18]); + buf b_dob_out19 (dob_out19, dob_out[19]); + buf b_dob_out20 (dob_out20, dob_out[20]); + buf b_dob_out21 (dob_out21, dob_out[21]); + buf b_dob_out22 (dob_out22, dob_out[22]); + buf b_dob_out23 (dob_out23, dob_out[23]); + buf b_dob_out24 (dob_out24, dob_out[24]); + buf b_dob_out25 (dob_out25, dob_out[25]); + buf b_dob_out26 (dob_out26, dob_out[26]); + buf b_dob_out27 (dob_out27, dob_out[27]); + buf b_dob_out28 (dob_out28, dob_out[28]); + buf b_dob_out29 (dob_out29, dob_out[29]); + buf b_dob_out30 (dob_out30, dob_out[30]); + buf b_dob_out31 (dob_out31, dob_out[31]); + buf b_dopb_out0 (dopb_out0, dopb_out[0]); + buf b_dopb_out1 (dopb_out1, dopb_out[1]); + buf b_dopb_out2 (dopb_out2, dopb_out[2]); + buf b_dopb_out3 (dopb_out3, dopb_out[3]); + + buf b_doa0 (DOA[0], doa_out0); + buf b_doa1 (DOA[1], doa_out1); + buf b_doa2 (DOA[2], doa_out2); + buf b_doa3 (DOA[3], doa_out3); + buf b_doa4 (DOA[4], doa_out4); + buf b_doa5 (DOA[5], doa_out5); + buf b_doa6 (DOA[6], doa_out6); + buf b_doa7 (DOA[7], doa_out7); + buf b_doa8 (DOA[8], doa_out8); + buf b_doa9 (DOA[9], doa_out9); + buf b_doa10 (DOA[10], doa_out10); + buf b_doa11 (DOA[11], doa_out11); + buf b_doa12 (DOA[12], doa_out12); + buf b_doa13 (DOA[13], doa_out13); + buf b_doa14 (DOA[14], doa_out14); + buf b_doa15 (DOA[15], doa_out15); + buf b_doa16 (DOA[16], doa_out16); + buf b_doa17 (DOA[17], doa_out17); + buf b_doa18 (DOA[18], doa_out18); + buf b_doa19 (DOA[19], doa_out19); + buf b_doa20 (DOA[20], doa_out20); + buf b_doa21 (DOA[21], doa_out21); + buf b_doa22 (DOA[22], doa_out22); + buf b_doa23 (DOA[23], doa_out23); + buf b_doa24 (DOA[24], doa_out24); + buf b_doa25 (DOA[25], doa_out25); + buf b_doa26 (DOA[26], doa_out26); + buf b_doa27 (DOA[27], doa_out27); + buf b_doa28 (DOA[28], doa_out28); + buf b_doa29 (DOA[29], doa_out29); + buf b_doa30 (DOA[30], doa_out30); + buf b_doa31 (DOA[31], doa_out31); + buf b_dopa0 (DOPA[0], dopa_out0); + buf b_dopa1 (DOPA[1], dopa_out1); + buf b_dopa2 (DOPA[2], dopa_out2); + buf b_dopa3 (DOPA[3], dopa_out3); + buf b_dob0 (DOB[0], dob_out0); + buf b_dob1 (DOB[1], dob_out1); + buf b_dob2 (DOB[2], dob_out2); + buf b_dob3 (DOB[3], dob_out3); + buf b_dob4 (DOB[4], dob_out4); + buf b_dob5 (DOB[5], dob_out5); + buf b_dob6 (DOB[6], dob_out6); + buf b_dob7 (DOB[7], dob_out7); + buf b_dob8 (DOB[8], dob_out8); + buf b_dob9 (DOB[9], dob_out9); + buf b_dob10 (DOB[10], dob_out10); + buf b_dob11 (DOB[11], dob_out11); + buf b_dob12 (DOB[12], dob_out12); + buf b_dob13 (DOB[13], dob_out13); + buf b_dob14 (DOB[14], dob_out14); + buf b_dob15 (DOB[15], dob_out15); + buf b_dob16 (DOB[16], dob_out16); + buf b_dob17 (DOB[17], dob_out17); + buf b_dob18 (DOB[18], dob_out18); + buf b_dob19 (DOB[19], dob_out19); + buf b_dob20 (DOB[20], dob_out20); + buf b_dob21 (DOB[21], dob_out21); + buf b_dob22 (DOB[22], dob_out22); + buf b_dob23 (DOB[23], dob_out23); + buf b_dob24 (DOB[24], dob_out24); + buf b_dob25 (DOB[25], dob_out25); + buf b_dob26 (DOB[26], dob_out26); + buf b_dob27 (DOB[27], dob_out27); + buf b_dob28 (DOB[28], dob_out28); + buf b_dob29 (DOB[29], dob_out29); + buf b_dob30 (DOB[30], dob_out30); + buf b_dob31 (DOB[31], dob_out31); + buf b_dopb0 (DOPB[0], dopb_out0); + buf b_dopb1 (DOPB[1], dopb_out1); + buf b_dopb2 (DOPB[2], dopb_out2); + buf b_dopb3 (DOPB[3], dopb_out3); + + buf b_addra_0 (addra_int[0], ADDRA[0]); + buf b_addra_1 (addra_int[1], ADDRA[1]); + buf b_addra_2 (addra_int[2], ADDRA[2]); + buf b_addra_3 (addra_int[3], ADDRA[3]); + buf b_addra_4 (addra_int[4], ADDRA[4]); + buf b_addra_5 (addra_int[5], ADDRA[5]); + buf b_addra_6 (addra_int[6], ADDRA[6]); + buf b_addra_7 (addra_int[7], ADDRA[7]); + buf b_addra_8 (addra_int[8], ADDRA[8]); + buf b_dia_0 (dia_int[0], DIA[0]); + buf b_dia_1 (dia_int[1], DIA[1]); + buf b_dia_2 (dia_int[2], DIA[2]); + buf b_dia_3 (dia_int[3], DIA[3]); + buf b_dia_4 (dia_int[4], DIA[4]); + buf b_dia_5 (dia_int[5], DIA[5]); + buf b_dia_6 (dia_int[6], DIA[6]); + buf b_dia_7 (dia_int[7], DIA[7]); + buf b_dia_8 (dia_int[8], DIA[8]); + buf b_dia_9 (dia_int[9], DIA[9]); + buf b_dia_10 (dia_int[10], DIA[10]); + buf b_dia_11 (dia_int[11], DIA[11]); + buf b_dia_12 (dia_int[12], DIA[12]); + buf b_dia_13 (dia_int[13], DIA[13]); + buf b_dia_14 (dia_int[14], DIA[14]); + buf b_dia_15 (dia_int[15], DIA[15]); + buf b_dia_16 (dia_int[16], DIA[16]); + buf b_dia_17 (dia_int[17], DIA[17]); + buf b_dia_18 (dia_int[18], DIA[18]); + buf b_dia_19 (dia_int[19], DIA[19]); + buf b_dia_20 (dia_int[20], DIA[20]); + buf b_dia_21 (dia_int[21], DIA[21]); + buf b_dia_22 (dia_int[22], DIA[22]); + buf b_dia_23 (dia_int[23], DIA[23]); + buf b_dia_24 (dia_int[24], DIA[24]); + buf b_dia_25 (dia_int[25], DIA[25]); + buf b_dia_26 (dia_int[26], DIA[26]); + buf b_dia_27 (dia_int[27], DIA[27]); + buf b_dia_28 (dia_int[28], DIA[28]); + buf b_dia_29 (dia_int[29], DIA[29]); + buf b_dia_30 (dia_int[30], DIA[30]); + buf b_dia_31 (dia_int[31], DIA[31]); + buf b_dipa_0 (dipa_int[0], DIPA[0]); + buf b_dipa_1 (dipa_int[1], DIPA[1]); + buf b_dipa_2 (dipa_int[2], DIPA[2]); + buf b_dipa_3 (dipa_int[3], DIPA[3]); + buf b_ena (ena_int, ENA); + buf b_clka (clka_int, CLKA); + buf b_ssra (ssra_int, SSRA); + buf b_wea (wea_int, WEA); + buf b_addrb_0 (addrb_int[0], ADDRB[0]); + buf b_addrb_1 (addrb_int[1], ADDRB[1]); + buf b_addrb_2 (addrb_int[2], ADDRB[2]); + buf b_addrb_3 (addrb_int[3], ADDRB[3]); + buf b_addrb_4 (addrb_int[4], ADDRB[4]); + buf b_addrb_5 (addrb_int[5], ADDRB[5]); + buf b_addrb_6 (addrb_int[6], ADDRB[6]); + buf b_addrb_7 (addrb_int[7], ADDRB[7]); + buf b_addrb_8 (addrb_int[8], ADDRB[8]); + buf b_dib_0 (dib_int[0], DIB[0]); + buf b_dib_1 (dib_int[1], DIB[1]); + buf b_dib_2 (dib_int[2], DIB[2]); + buf b_dib_3 (dib_int[3], DIB[3]); + buf b_dib_4 (dib_int[4], DIB[4]); + buf b_dib_5 (dib_int[5], DIB[5]); + buf b_dib_6 (dib_int[6], DIB[6]); + buf b_dib_7 (dib_int[7], DIB[7]); + buf b_dib_8 (dib_int[8], DIB[8]); + buf b_dib_9 (dib_int[9], DIB[9]); + buf b_dib_10 (dib_int[10], DIB[10]); + buf b_dib_11 (dib_int[11], DIB[11]); + buf b_dib_12 (dib_int[12], DIB[12]); + buf b_dib_13 (dib_int[13], DIB[13]); + buf b_dib_14 (dib_int[14], DIB[14]); + buf b_dib_15 (dib_int[15], DIB[15]); + buf b_dib_16 (dib_int[16], DIB[16]); + buf b_dib_17 (dib_int[17], DIB[17]); + buf b_dib_18 (dib_int[18], DIB[18]); + buf b_dib_19 (dib_int[19], DIB[19]); + buf b_dib_20 (dib_int[20], DIB[20]); + buf b_dib_21 (dib_int[21], DIB[21]); + buf b_dib_22 (dib_int[22], DIB[22]); + buf b_dib_23 (dib_int[23], DIB[23]); + buf b_dib_24 (dib_int[24], DIB[24]); + buf b_dib_25 (dib_int[25], DIB[25]); + buf b_dib_26 (dib_int[26], DIB[26]); + buf b_dib_27 (dib_int[27], DIB[27]); + buf b_dib_28 (dib_int[28], DIB[28]); + buf b_dib_29 (dib_int[29], DIB[29]); + buf b_dib_30 (dib_int[30], DIB[30]); + buf b_dib_31 (dib_int[31], DIB[31]); + buf b_dipb_0 (dipb_int[0], DIPB[0]); + buf b_dipb_1 (dipb_int[1], DIPB[1]); + buf b_dipb_2 (dipb_int[2], DIPB[2]); + buf b_dipb_3 (dipb_int[3], DIPB[3]); + buf b_enb (enb_int, ENB); + buf b_clkb (clkb_int, CLKB); + buf b_ssrb (ssrb_int, SSRB); + buf b_web (web_int, WEB); + + initial begin + for (count = 0; count < 256; count = count + 1) begin + mem[count] <= INIT_00[count]; + mem[256 * 1 + count] <= INIT_01[count]; + mem[256 * 2 + count] <= INIT_02[count]; + mem[256 * 3 + count] <= INIT_03[count]; + mem[256 * 4 + count] <= INIT_04[count]; + mem[256 * 5 + count] <= INIT_05[count]; + mem[256 * 6 + count] <= INIT_06[count]; + mem[256 * 7 + count] <= INIT_07[count]; + mem[256 * 8 + count] <= INIT_08[count]; + mem[256 * 9 + count] <= INIT_09[count]; + mem[256 * 10 + count] <= INIT_0A[count]; + mem[256 * 11 + count] <= INIT_0B[count]; + mem[256 * 12 + count] <= INIT_0C[count]; + mem[256 * 13 + count] <= INIT_0D[count]; + mem[256 * 14 + count] <= INIT_0E[count]; + mem[256 * 15 + count] <= INIT_0F[count]; + mem[256 * 16 + count] <= INIT_10[count]; + mem[256 * 17 + count] <= INIT_11[count]; + mem[256 * 18 + count] <= INIT_12[count]; + mem[256 * 19 + count] <= INIT_13[count]; + mem[256 * 20 + count] <= INIT_14[count]; + mem[256 * 21 + count] <= INIT_15[count]; + mem[256 * 22 + count] <= INIT_16[count]; + mem[256 * 23 + count] <= INIT_17[count]; + mem[256 * 24 + count] <= INIT_18[count]; + mem[256 * 25 + count] <= INIT_19[count]; + mem[256 * 26 + count] <= INIT_1A[count]; + mem[256 * 27 + count] <= INIT_1B[count]; + mem[256 * 28 + count] <= INIT_1C[count]; + mem[256 * 29 + count] <= INIT_1D[count]; + mem[256 * 30 + count] <= INIT_1E[count]; + mem[256 * 31 + count] <= INIT_1F[count]; + mem[256 * 32 + count] <= INIT_20[count]; + mem[256 * 33 + count] <= INIT_21[count]; + mem[256 * 34 + count] <= INIT_22[count]; + mem[256 * 35 + count] <= INIT_23[count]; + mem[256 * 36 + count] <= INIT_24[count]; + mem[256 * 37 + count] <= INIT_25[count]; + mem[256 * 38 + count] <= INIT_26[count]; + mem[256 * 39 + count] <= INIT_27[count]; + mem[256 * 40 + count] <= INIT_28[count]; + mem[256 * 41 + count] <= INIT_29[count]; + mem[256 * 42 + count] <= INIT_2A[count]; + mem[256 * 43 + count] <= INIT_2B[count]; + mem[256 * 44 + count] <= INIT_2C[count]; + mem[256 * 45 + count] <= INIT_2D[count]; + mem[256 * 46 + count] <= INIT_2E[count]; + mem[256 * 47 + count] <= INIT_2F[count]; + mem[256 * 48 + count] <= INIT_30[count]; + mem[256 * 49 + count] <= INIT_31[count]; + mem[256 * 50 + count] <= INIT_32[count]; + mem[256 * 51 + count] <= INIT_33[count]; + mem[256 * 52 + count] <= INIT_34[count]; + mem[256 * 53 + count] <= INIT_35[count]; + mem[256 * 54 + count] <= INIT_36[count]; + mem[256 * 55 + count] <= INIT_37[count]; + mem[256 * 56 + count] <= INIT_38[count]; + mem[256 * 57 + count] <= INIT_39[count]; + mem[256 * 58 + count] <= INIT_3A[count]; + mem[256 * 59 + count] <= INIT_3B[count]; + mem[256 * 60 + count] <= INIT_3C[count]; + mem[256 * 61 + count] <= INIT_3D[count]; + mem[256 * 62 + count] <= INIT_3E[count]; + mem[256 * 63 + count] <= INIT_3F[count]; + mem[256 * 64 + count] <= INITP_00[count]; + mem[256 * 65 + count] <= INITP_01[count]; + mem[256 * 66 + count] <= INITP_02[count]; + mem[256 * 67 + count] <= INITP_03[count]; + mem[256 * 68 + count] <= INITP_04[count]; + mem[256 * 69 + count] <= INITP_05[count]; + mem[256 * 70 + count] <= INITP_06[count]; + mem[256 * 71 + count] <= INITP_07[count]; + end + address_collision <= 0; + address_collision_a_b <= 0; + address_collision_b_a <= 0; + change_clka <= 0; + change_clkb <= 0; + data_collision <= 0; + data_collision_a_b <= 0; + data_collision_b_a <= 0; + memory_collision <= 0; + memory_collision_a_b <= 0; + memory_collision_b_a <= 0; + setup_all_a_b <= 0; + setup_all_b_a <= 0; + setup_zero <= 0; + setup_rf_a_b <= 0; + setup_rf_b_a <= 0; + end + + assign data_addra_int = addra_int * 32; + assign data_addra_reg = addra_reg * 32; + assign data_addrb_int = addrb_int * 32; + assign data_addrb_reg = addrb_reg * 32; + assign parity_addra_int = 16384 + addra_int * 4; + assign parity_addra_reg = 16384 + addra_reg * 4; + assign parity_addrb_int = 16384 + addrb_int * 4; + assign parity_addrb_reg = 16384 + addrb_reg * 4; + + + initial begin + + display_flag = 1; + + case (SIM_COLLISION_CHECK) + + "NONE" : begin + assign setup_all_a_b = 1'b0; + assign setup_all_b_a = 1'b0; + assign setup_zero = 1'b0; + assign setup_rf_a_b = 1'b0; + assign setup_rf_b_a = 1'b0; + assign display_flag = 0; + end + "WARNING_ONLY" : begin + assign data_collision = 2'b00; + assign data_collision_a_b = 2'b00; + assign data_collision_b_a = 2'b00; + assign memory_collision = 1'b0; + assign memory_collision_a_b = 1'b0; + assign memory_collision_b_a = 1'b0; + end + "GENERATE_X_ONLY" : begin + assign display_flag = 0; + end + "ALL" : ; + default : begin + $display("Attribute Syntax Error : The Attribute SIM_COLLISION_CHECK on RAMB16_S36_S36 instance %m is set to %s. Legal values for this attribute are ALL, NONE, WARNING_ONLY or GENERATE_X_ONLY.", SIM_COLLISION_CHECK); + $finish; + end + + endcase // case(SIM_COLLISION_CHECK) + + end // initial begin + + + always @(posedge clka_int) begin + time_clka = $time; + #0 time_clkb_clka = time_clka - time_clkb; + change_clka = ~change_clka; + end + + always @(posedge clkb_int) begin + time_clkb = $time; + #0 time_clka_clkb = time_clkb - time_clka; + change_clkb = ~change_clkb; + end + + always @(change_clkb) begin + if ((0 < time_clka_clkb) && (time_clka_clkb < SETUP_ALL)) + setup_all_a_b = 1; + if ((0 < time_clka_clkb) && (time_clka_clkb < SETUP_READ_FIRST)) + setup_rf_a_b = 1; + end + + always @(change_clka) begin + if ((0 < time_clkb_clka) && (time_clkb_clka < SETUP_ALL)) + setup_all_b_a = 1; + if ((0 < time_clkb_clka) && (time_clkb_clka < SETUP_READ_FIRST)) + setup_rf_b_a = 1; + end + + always @(change_clkb or change_clka) begin + if ((time_clkb_clka == 0) && (time_clka_clkb == 0)) + setup_zero = 1; + end + + always @(posedge setup_zero) begin + if ((ena_int == 1) && (wea_int == 1) && + (enb_int == 1) && (web_int == 1) && + (data_addra_int[14:5] == data_addrb_int[14:5])) + memory_collision <= 1; + end + + always @(posedge setup_all_a_b or posedge setup_rf_a_b) begin + if ((ena_reg == 1) && (wea_reg == 1) && + (enb_int == 1) && (web_int == 1) && + (data_addra_reg[14:5] == data_addrb_int[14:5])) + memory_collision_a_b <= 1; + end + + always @(posedge setup_all_b_a or posedge setup_rf_b_a) begin + if ((ena_int == 1) && (wea_int == 1) && + (enb_reg == 1) && (web_reg == 1) && + (data_addra_int[14:5] == data_addrb_reg[14:5])) + memory_collision_b_a <= 1; + end + + always @(posedge setup_all_a_b) begin + if (data_addra_reg[14:5] == data_addrb_int[14:5]) begin + if ((ena_reg == 1) && (enb_int == 1)) begin + case ({wr_mode_a, wr_mode_b, wea_reg, web_int}) + 6'b000011 : begin data_collision_a_b <= 2'b11; display_wa_wb; end + 6'b000111 : begin data_collision_a_b <= 2'b11; display_wa_wb; end + 6'b001011 : begin data_collision_a_b <= 2'b10; display_wa_wb; end +// 6'b010011 : begin data_collision_a_b <= 2'b00; display_wa_wb; end +// 6'b010111 : begin data_collision_a_b <= 2'b00; display_wa_wb; end +// 6'b011011 : begin data_collision_a_b <= 2'b00; display_wa_wb; end + 6'b100011 : begin data_collision_a_b <= 2'b01; display_wa_wb; end + 6'b100111 : begin data_collision_a_b <= 2'b01; display_wa_wb; end + 6'b101011 : begin display_wa_wb; end + 6'b000001 : begin data_collision_a_b <= 2'b10; display_ra_wb; end +// 6'b000101 : begin data_collision_a_b <= 2'b00; display_ra_wb; end + 6'b001001 : begin data_collision_a_b <= 2'b10; display_ra_wb; end + 6'b010001 : begin data_collision_a_b <= 2'b10; display_ra_wb; end +// 6'b010101 : begin data_collision_a_b <= 2'b00; display_ra_wb; end + 6'b011001 : begin data_collision_a_b <= 2'b10; display_ra_wb; end + 6'b100001 : begin data_collision_a_b <= 2'b10; display_ra_wb; end +// 6'b100101 : begin data_collision_a_b <= 2'b00; display_ra_wb; end + 6'b101001 : begin data_collision_a_b <= 2'b10; display_ra_wb; end + 6'b000010 : begin data_collision_a_b <= 2'b01; display_wa_rb; end + 6'b000110 : begin data_collision_a_b <= 2'b01; display_wa_rb; end + 6'b001010 : begin data_collision_a_b <= 2'b01; display_wa_rb; end +// 6'b010010 : begin data_collision_a_b <= 2'b00; display_wa_rb; end +// 6'b010110 : begin data_collision_a_b <= 2'b00; display_wa_rb; end +// 6'b011010 : begin data_collision_a_b <= 2'b00; display_wa_rb; end + 6'b100010 : begin data_collision_a_b <= 2'b01; display_wa_rb; end + 6'b100110 : begin data_collision_a_b <= 2'b01; display_wa_rb; end + 6'b101010 : begin data_collision_a_b <= 2'b01; display_wa_rb; end + endcase + end + end + setup_all_a_b <= 0; + end + + + always @(posedge setup_all_b_a) begin + if (data_addra_int[14:5] == data_addrb_reg[14:5]) begin + if ((ena_int == 1) && (enb_reg == 1)) begin + case ({wr_mode_a, wr_mode_b, wea_int, web_reg}) + 6'b000011 : begin data_collision_b_a <= 2'b11; display_wa_wb; end +// 6'b000111 : begin data_collision_b_a <= 2'b00; display_wa_wb; end + 6'b001011 : begin data_collision_b_a <= 2'b10; display_wa_wb; end + 6'b010011 : begin data_collision_b_a <= 2'b11; display_wa_wb; end +// 6'b010111 : begin data_collision_b_a <= 2'b00; display_wa_wb; end + 6'b011011 : begin data_collision_b_a <= 2'b10; display_wa_wb; end + 6'b100011 : begin data_collision_b_a <= 2'b01; display_wa_wb; end + 6'b100111 : begin data_collision_b_a <= 2'b01; display_wa_wb; end + 6'b101011 : begin display_wa_wb; end + 6'b000001 : begin data_collision_b_a <= 2'b10; display_ra_wb; end + 6'b000101 : begin data_collision_b_a <= 2'b10; display_ra_wb; end + 6'b001001 : begin data_collision_b_a <= 2'b10; display_ra_wb; end + 6'b010001 : begin data_collision_b_a <= 2'b10; display_ra_wb; end + 6'b010101 : begin data_collision_b_a <= 2'b10; display_ra_wb; end + 6'b011001 : begin data_collision_b_a <= 2'b10; display_ra_wb; end + 6'b100001 : begin data_collision_b_a <= 2'b10; display_ra_wb; end + 6'b100101 : begin data_collision_b_a <= 2'b10; display_ra_wb; end + 6'b101001 : begin data_collision_b_a <= 2'b10; display_ra_wb; end + 6'b000010 : begin data_collision_b_a <= 2'b01; display_wa_rb; end + 6'b000110 : begin data_collision_b_a <= 2'b01; display_wa_rb; end + 6'b001010 : begin data_collision_b_a <= 2'b01; display_wa_rb; end +// 6'b010010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end +// 6'b010110 : begin data_collision_b_a <= 2'b00; display_wa_rb; end +// 6'b011010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end + 6'b100010 : begin data_collision_b_a <= 2'b01; display_wa_rb; end + 6'b100110 : begin data_collision_b_a <= 2'b01; display_wa_rb; end + 6'b101010 : begin data_collision_b_a <= 2'b01; display_wa_rb; end + endcase + end + end + setup_all_b_a <= 0; + end + + + always @(posedge setup_zero) begin + if (data_addra_int[14:5] == data_addrb_int[14:5]) begin + if ((ena_int == 1) && (enb_int == 1)) begin + case ({wr_mode_a, wr_mode_b, wea_int, web_int}) + 6'b000011 : begin data_collision <= 2'b11; display_wa_wb; end + 6'b000111 : begin data_collision <= 2'b11; display_wa_wb; end + 6'b001011 : begin data_collision <= 2'b10; display_wa_wb; end + 6'b010011 : begin data_collision <= 2'b11; display_wa_wb; end + 6'b010111 : begin data_collision <= 2'b11; display_wa_wb; end + 6'b011011 : begin data_collision <= 2'b10; display_wa_wb; end + 6'b100011 : begin data_collision <= 2'b01; display_wa_wb; end + 6'b100111 : begin data_collision <= 2'b01; display_wa_wb; end + 6'b101011 : begin display_wa_wb; end + 6'b000001 : begin data_collision <= 2'b10; display_ra_wb; end +// 6'b000101 : begin data_collision <= 2'b00; display_ra_wb; end + 6'b001001 : begin data_collision <= 2'b10; display_ra_wb; end + 6'b010001 : begin data_collision <= 2'b10; display_ra_wb; end +// 6'b010101 : begin data_collision <= 2'b00; display_ra_wb; end + 6'b011001 : begin data_collision <= 2'b10; display_ra_wb; end + 6'b100001 : begin data_collision <= 2'b10; display_ra_wb; end +// 6'b100101 : begin data_collision <= 2'b00; display_ra_wb; end + 6'b101001 : begin data_collision <= 2'b10; display_ra_wb; end + 6'b000010 : begin data_collision <= 2'b01; display_wa_rb; end + 6'b000110 : begin data_collision <= 2'b01; display_wa_rb; end + 6'b001010 : begin data_collision <= 2'b01; display_wa_rb; end +// 6'b010010 : begin data_collision <= 2'b00; display_wa_rb; end +// 6'b010110 : begin data_collision <= 2'b00; display_wa_rb; end +// 6'b011010 : begin data_collision <= 2'b00; display_wa_rb; end + 6'b100010 : begin data_collision <= 2'b01; display_wa_rb; end + 6'b100110 : begin data_collision <= 2'b01; display_wa_rb; end + 6'b101010 : begin data_collision <= 2'b01; display_wa_rb; end + endcase + end + end + setup_zero <= 0; + end + + task display_ra_wb; + begin + if (display_flag) + $display("Memory Collision Error on RAMB16_S36_S36:%m at simulation time %.3f ns\nA read was performed on address %h (hex) of Port A while a write was requested to the same address on Port B. The write will be successful however the read value on Port A is unknown until the next CLKA cycle.", $time/1000.0, addra_int); + end + endtask + + task display_wa_rb; + begin + if (display_flag) + $display("Memory Collision Error on RAMB16_S36_S36:%m at simulation time %.3f ns\nA read was performed on address %h (hex) of Port B while a write was requested to the same address on Port A. The write will be successful however the read value on Port B is unknown until the next CLKB cycle.", $time/1000.0, addrb_int); + end + endtask + + task display_wa_wb; + begin + if (display_flag) + $display("Memory Collision Error on RAMB16_S36_S36:%m at simulation time %.3f ns\nA write was requested to the same address simultaneously at both Port A and Port B of the RAM. The contents written to the RAM at address location %h (hex) of Port A and address location %h (hex) of Port B are unknown.", $time/1000.0, addra_int, addrb_int); + end + endtask + + + always @(posedge setup_rf_a_b) begin + if (data_addra_reg[14:5] == data_addrb_int[14:5]) begin + if ((ena_reg == 1) && (enb_int == 1)) begin + case ({wr_mode_a, wr_mode_b, wea_reg, web_int}) +// 6'b000011 : begin data_collision_a_b <= 2'b00; display_wa_wb; end +// 6'b000111 : begin data_collision_a_b <= 2'b00; display_wa_wb; end +// 6'b001011 : begin data_collision_a_b <= 2'b00; display_wa_wb; end + 6'b010011 : begin data_collision_a_b <= 2'b11; display_wa_wb; end + 6'b010111 : begin data_collision_a_b <= 2'b11; display_wa_wb; end + 6'b011011 : begin data_collision_a_b <= 2'b10; display_wa_wb; end +// 6'b100011 : begin data_collision_a_b <= 2'b00; display_wa_wb; end +// 6'b100111 : begin data_collision_a_b <= 2'b00; display_wa_wb; end +// 6'b101011 : begin data_collision_a_b <= 2'b00; display_wa_wb; end +// 6'b000001 : begin data_collision_a_b <= 2'b00; display_ra_wb; end +// 6'b000101 : begin data_collision_a_b <= 2'b00; display_ra_wb; end +// 6'b001001 : begin data_collision_a_b <= 2'b00; display_ra_wb; end +// 6'b010001 : begin data_collision_a_b <= 2'b00; display_ra_wb; end +// 6'b010101 : begin data_collision_a_b <= 2'b00; display_ra_wb; end +// 6'b011001 : begin data_collision_a_b <= 2'b00; display_ra_wb; end +// 6'b100001 : begin data_collision_a_b <= 2'b00; display_ra_wb; end +// 6'b100101 : begin data_collision_a_b <= 2'b00; display_ra_wb; end +// 6'b101001 : begin data_collision_a_b <= 2'b00; display_ra_wb; end +// 6'b000010 : begin data_collision_a_b <= 2'b00; display_wa_rb; end +// 6'b000110 : begin data_collision_a_b <= 2'b00; display_wa_rb; end +// 6'b001010 : begin data_collision_a_b <= 2'b00; display_wa_rb; end + 6'b010010 : begin data_collision_a_b <= 2'b01; display_wa_rb; end + 6'b010110 : begin data_collision_a_b <= 2'b01; display_wa_rb; end + 6'b011010 : begin data_collision_a_b <= 2'b01; display_wa_rb; end +// 6'b100010 : begin data_collision_a_b <= 2'b00; display_wa_rb; end +// 6'b100110 : begin data_collision_a_b <= 2'b00; display_wa_rb; end +// 6'b101010 : begin data_collision_a_b <= 2'b00; display_wa_rb; end + endcase + end + end + setup_rf_a_b <= 0; + end + + + always @(posedge setup_rf_b_a) begin + if (data_addra_int[14:5] == data_addrb_reg[14:5]) begin + if ((ena_int == 1) && (enb_reg == 1)) begin + case ({wr_mode_a, wr_mode_b, wea_int, web_reg}) +// 6'b000011 : begin data_collision_b_a <= 2'b00; display_wa_wb; end + 6'b000111 : begin data_collision_b_a <= 2'b11; display_wa_wb; end +// 6'b001011 : begin data_collision_b_a <= 2'b00; display_wa_wb; end +// 6'b010011 : begin data_collision_b_a <= 2'b00; display_wa_wb; end + 6'b010111 : begin data_collision_b_a <= 2'b11; display_wa_wb; end +// 6'b011011 : begin data_collision_b_a <= 2'b00; display_wa_wb; end +// 6'b100011 : begin data_collision_b_a <= 2'b00; display_wa_wb; end + 6'b100111 : begin data_collision_b_a <= 2'b01; display_wa_wb; end +// 6'b101011 : begin data_collision_b_a <= 2'b00; display_wa_wb; end +// 6'b000001 : begin data_collision_b_a <= 2'b00; display_ra_wb; end + 6'b000101 : begin data_collision_b_a <= 2'b10; display_ra_wb; end +// 6'b001001 : begin data_collision_b_a <= 2'b00; display_ra_wb; end +// 6'b010001 : begin data_collision_b_a <= 2'b00; display_ra_wb; end + 6'b010101 : begin data_collision_b_a <= 2'b10; display_ra_wb; end +// 6'b011001 : begin data_collision_b_a <= 2'b00; display_ra_wb; end +// 6'b100001 : begin data_collision_b_a <= 2'b00; display_ra_wb; end + 6'b100101 : begin data_collision_b_a <= 2'b10; display_ra_wb; end +// 6'b101001 : begin data_collision_b_a <= 2'b00; display_ra_wb; end +// 6'b000010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end +// 6'b000110 : begin data_collision_b_a <= 2'b00; display_wa_rb; end +// 6'b001010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end +// 6'b010010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end +// 6'b010110 : begin data_collision_b_a <= 2'b00; display_wa_rb; end +// 6'b011010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end +// 6'b100010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end +// 6'b100110 : begin data_collision_b_a <= 2'b00; display_wa_rb; end +// 6'b101010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end + endcase + end + end + setup_rf_b_a <= 0; + end + + + always @(posedge clka_int) begin + addra_reg <= addra_int; + ena_reg <= ena_int; + ssra_reg <= ssra_int; + wea_reg <= wea_int; + end + + always @(posedge clkb_int) begin + addrb_reg <= addrb_int; + enb_reg <= enb_int; + ssrb_reg <= ssrb_int; + web_reg <= web_int; + end + + // Data + always @(posedge memory_collision) begin + for (dmi = 0; dmi < 32; dmi = dmi + 1) begin + mem[data_addra_int + dmi] <= 1'bX; + end + memory_collision <= 0; + end + + always @(posedge memory_collision_a_b) begin + for (dmi = 0; dmi < 32; dmi = dmi + 1) begin + mem[data_addra_reg + dmi] <= 1'bX; + end + memory_collision_a_b <= 0; + end + + always @(posedge memory_collision_b_a) begin + for (dmi = 0; dmi < 32; dmi = dmi + 1) begin + mem[data_addra_int + dmi] <= 1'bX; + end + memory_collision_b_a <= 0; + end + + always @(posedge data_collision[1]) begin + if (ssra_int == 0) begin + doa_out <= 32'bX; + end + data_collision[1] <= 0; + end + + always @(posedge data_collision[0]) begin + if (ssrb_int == 0) begin + dob_out <= 32'bX; + end + data_collision[0] <= 0; + end + + always @(posedge data_collision_a_b[1]) begin + if (ssra_reg == 0) begin + doa_out <= 32'bX; + end + data_collision_a_b[1] <= 0; + end + + always @(posedge data_collision_a_b[0]) begin + if (ssrb_int == 0) begin + dob_out <= 32'bX; + end + data_collision_a_b[0] <= 0; + end + + always @(posedge data_collision_b_a[1]) begin + if (ssra_int == 0) begin + doa_out <= 32'bX; + end + data_collision_b_a[1] <= 0; + end + + always @(posedge data_collision_b_a[0]) begin + if (ssrb_reg == 0) begin + dob_out <= 32'bX; + end + data_collision_b_a[0] <= 0; + end + + + // Parity + always @(posedge memory_collision) begin + for (pmi = 0; pmi < 4; pmi = pmi + 1) begin + mem[parity_addra_int + pmi] <= 1'bX; + end + end + + always @(posedge memory_collision_a_b) begin + for (pmi = 0; pmi < 4; pmi = pmi + 1) begin + mem[parity_addra_reg + pmi] <= 1'bX; + end + end + + always @(posedge memory_collision_b_a) begin + for (pmi = 0; pmi < 4; pmi = pmi + 1) begin + mem[parity_addra_int + pmi] <= 1'bX; + end + end + + always @(posedge data_collision[1]) begin + if (ssra_int == 0) begin + dopa_out <= 4'bX; + end + end + + always @(posedge data_collision[0]) begin + if (ssrb_int == 0) begin + dopb_out <= 4'bX; + end + end + + always @(posedge data_collision_a_b[1]) begin + if (ssra_reg == 0) begin + dopa_out <= 4'bX; + end + end + + always @(posedge data_collision_a_b[0]) begin + if (ssrb_int == 0) begin + dopb_out <= 4'bX; + end + end + + always @(posedge data_collision_b_a[1]) begin + if (ssra_int == 0) begin + dopa_out <= 4'bX; + end + end + + always @(posedge data_collision_b_a[0]) begin + if (ssrb_reg == 0) begin + dopb_out <= 4'bX; + end + end + + + initial begin + case (WRITE_MODE_A) + "WRITE_FIRST" : wr_mode_a <= 2'b00; + "READ_FIRST" : wr_mode_a <= 2'b01; + "NO_CHANGE" : wr_mode_a <= 2'b10; + default : begin + $display("Attribute Syntax Error : The Attribute WRITE_MODE_A on RAMB16_S36_S36 instance %m is set to %s. Legal values for this attribute are WRITE_FIRST, READ_FIRST or NO_CHANGE.", WRITE_MODE_A); + $finish; + end + endcase + end + + initial begin + case (WRITE_MODE_B) + "WRITE_FIRST" : wr_mode_b <= 2'b00; + "READ_FIRST" : wr_mode_b <= 2'b01; + "NO_CHANGE" : wr_mode_b <= 2'b10; + default : begin + $display("Attribute Syntax Error : The Attribute WRITE_MODE_B on RAMB16_S36_S36 instance %m is set to %s. Legal values for this attribute are WRITE_FIRST, READ_FIRST or NO_CHANGE.", WRITE_MODE_B); + $finish; + end + endcase + end + + // Port A + always @(posedge clka_int) begin + if (ena_int == 1'b1) begin + if (ssra_int == 1'b1) begin + doa_out[0] <= SRVAL_A[0]; + doa_out[1] <= SRVAL_A[1]; + doa_out[2] <= SRVAL_A[2]; + doa_out[3] <= SRVAL_A[3]; + doa_out[4] <= SRVAL_A[4]; + doa_out[5] <= SRVAL_A[5]; + doa_out[6] <= SRVAL_A[6]; + doa_out[7] <= SRVAL_A[7]; + doa_out[8] <= SRVAL_A[8]; + doa_out[9] <= SRVAL_A[9]; + doa_out[10] <= SRVAL_A[10]; + doa_out[11] <= SRVAL_A[11]; + doa_out[12] <= SRVAL_A[12]; + doa_out[13] <= SRVAL_A[13]; + doa_out[14] <= SRVAL_A[14]; + doa_out[15] <= SRVAL_A[15]; + doa_out[16] <= SRVAL_A[16]; + doa_out[17] <= SRVAL_A[17]; + doa_out[18] <= SRVAL_A[18]; + doa_out[19] <= SRVAL_A[19]; + doa_out[20] <= SRVAL_A[20]; + doa_out[21] <= SRVAL_A[21]; + doa_out[22] <= SRVAL_A[22]; + doa_out[23] <= SRVAL_A[23]; + doa_out[24] <= SRVAL_A[24]; + doa_out[25] <= SRVAL_A[25]; + doa_out[26] <= SRVAL_A[26]; + doa_out[27] <= SRVAL_A[27]; + doa_out[28] <= SRVAL_A[28]; + doa_out[29] <= SRVAL_A[29]; + doa_out[30] <= SRVAL_A[30]; + doa_out[31] <= SRVAL_A[31]; + dopa_out[0] <= SRVAL_A[32]; + dopa_out[1] <= SRVAL_A[33]; + dopa_out[2] <= SRVAL_A[34]; + dopa_out[3] <= SRVAL_A[35]; + end + else begin + if (wea_int == 1'b1) begin + if (wr_mode_a == 2'b00) begin + doa_out <= dia_int; + dopa_out <= dipa_int; + end + else if (wr_mode_a == 2'b01) begin + doa_out[0] <= mem[data_addra_int + 0]; + doa_out[1] <= mem[data_addra_int + 1]; + doa_out[2] <= mem[data_addra_int + 2]; + doa_out[3] <= mem[data_addra_int + 3]; + doa_out[4] <= mem[data_addra_int + 4]; + doa_out[5] <= mem[data_addra_int + 5]; + doa_out[6] <= mem[data_addra_int + 6]; + doa_out[7] <= mem[data_addra_int + 7]; + doa_out[8] <= mem[data_addra_int + 8]; + doa_out[9] <= mem[data_addra_int + 9]; + doa_out[10] <= mem[data_addra_int + 10]; + doa_out[11] <= mem[data_addra_int + 11]; + doa_out[12] <= mem[data_addra_int + 12]; + doa_out[13] <= mem[data_addra_int + 13]; + doa_out[14] <= mem[data_addra_int + 14]; + doa_out[15] <= mem[data_addra_int + 15]; + doa_out[16] <= mem[data_addra_int + 16]; + doa_out[17] <= mem[data_addra_int + 17]; + doa_out[18] <= mem[data_addra_int + 18]; + doa_out[19] <= mem[data_addra_int + 19]; + doa_out[20] <= mem[data_addra_int + 20]; + doa_out[21] <= mem[data_addra_int + 21]; + doa_out[22] <= mem[data_addra_int + 22]; + doa_out[23] <= mem[data_addra_int + 23]; + doa_out[24] <= mem[data_addra_int + 24]; + doa_out[25] <= mem[data_addra_int + 25]; + doa_out[26] <= mem[data_addra_int + 26]; + doa_out[27] <= mem[data_addra_int + 27]; + doa_out[28] <= mem[data_addra_int + 28]; + doa_out[29] <= mem[data_addra_int + 29]; + doa_out[30] <= mem[data_addra_int + 30]; + doa_out[31] <= mem[data_addra_int + 31]; + dopa_out[0] <= mem[parity_addra_int + 0]; + dopa_out[1] <= mem[parity_addra_int + 1]; + dopa_out[2] <= mem[parity_addra_int + 2]; + dopa_out[3] <= mem[parity_addra_int + 3]; + end + end + else begin + doa_out[0] <= mem[data_addra_int + 0]; + doa_out[1] <= mem[data_addra_int + 1]; + doa_out[2] <= mem[data_addra_int + 2]; + doa_out[3] <= mem[data_addra_int + 3]; + doa_out[4] <= mem[data_addra_int + 4]; + doa_out[5] <= mem[data_addra_int + 5]; + doa_out[6] <= mem[data_addra_int + 6]; + doa_out[7] <= mem[data_addra_int + 7]; + doa_out[8] <= mem[data_addra_int + 8]; + doa_out[9] <= mem[data_addra_int + 9]; + doa_out[10] <= mem[data_addra_int + 10]; + doa_out[11] <= mem[data_addra_int + 11]; + doa_out[12] <= mem[data_addra_int + 12]; + doa_out[13] <= mem[data_addra_int + 13]; + doa_out[14] <= mem[data_addra_int + 14]; + doa_out[15] <= mem[data_addra_int + 15]; + doa_out[16] <= mem[data_addra_int + 16]; + doa_out[17] <= mem[data_addra_int + 17]; + doa_out[18] <= mem[data_addra_int + 18]; + doa_out[19] <= mem[data_addra_int + 19]; + doa_out[20] <= mem[data_addra_int + 20]; + doa_out[21] <= mem[data_addra_int + 21]; + doa_out[22] <= mem[data_addra_int + 22]; + doa_out[23] <= mem[data_addra_int + 23]; + doa_out[24] <= mem[data_addra_int + 24]; + doa_out[25] <= mem[data_addra_int + 25]; + doa_out[26] <= mem[data_addra_int + 26]; + doa_out[27] <= mem[data_addra_int + 27]; + doa_out[28] <= mem[data_addra_int + 28]; + doa_out[29] <= mem[data_addra_int + 29]; + doa_out[30] <= mem[data_addra_int + 30]; + doa_out[31] <= mem[data_addra_int + 31]; + dopa_out[0] <= mem[parity_addra_int + 0]; + dopa_out[1] <= mem[parity_addra_int + 1]; + dopa_out[2] <= mem[parity_addra_int + 2]; + dopa_out[3] <= mem[parity_addra_int + 3]; + end + end + end + end + + always @(posedge clka_int) begin + if (ena_int == 1'b1 && wea_int == 1'b1) begin + mem[data_addra_int + 0] <= dia_int[0]; + mem[data_addra_int + 1] <= dia_int[1]; + mem[data_addra_int + 2] <= dia_int[2]; + mem[data_addra_int + 3] <= dia_int[3]; + mem[data_addra_int + 4] <= dia_int[4]; + mem[data_addra_int + 5] <= dia_int[5]; + mem[data_addra_int + 6] <= dia_int[6]; + mem[data_addra_int + 7] <= dia_int[7]; + mem[data_addra_int + 8] <= dia_int[8]; + mem[data_addra_int + 9] <= dia_int[9]; + mem[data_addra_int + 10] <= dia_int[10]; + mem[data_addra_int + 11] <= dia_int[11]; + mem[data_addra_int + 12] <= dia_int[12]; + mem[data_addra_int + 13] <= dia_int[13]; + mem[data_addra_int + 14] <= dia_int[14]; + mem[data_addra_int + 15] <= dia_int[15]; + mem[data_addra_int + 16] <= dia_int[16]; + mem[data_addra_int + 17] <= dia_int[17]; + mem[data_addra_int + 18] <= dia_int[18]; + mem[data_addra_int + 19] <= dia_int[19]; + mem[data_addra_int + 20] <= dia_int[20]; + mem[data_addra_int + 21] <= dia_int[21]; + mem[data_addra_int + 22] <= dia_int[22]; + mem[data_addra_int + 23] <= dia_int[23]; + mem[data_addra_int + 24] <= dia_int[24]; + mem[data_addra_int + 25] <= dia_int[25]; + mem[data_addra_int + 26] <= dia_int[26]; + mem[data_addra_int + 27] <= dia_int[27]; + mem[data_addra_int + 28] <= dia_int[28]; + mem[data_addra_int + 29] <= dia_int[29]; + mem[data_addra_int + 30] <= dia_int[30]; + mem[data_addra_int + 31] <= dia_int[31]; + mem[parity_addra_int + 0] <= dipa_int[0]; + mem[parity_addra_int + 1] <= dipa_int[1]; + mem[parity_addra_int + 2] <= dipa_int[2]; + mem[parity_addra_int + 3] <= dipa_int[3]; + end + end + + // Port B + always @(posedge clkb_int) begin + if (enb_int == 1'b1) begin + if (ssrb_int == 1'b1) begin + dob_out[0] <= SRVAL_B[0]; + dob_out[1] <= SRVAL_B[1]; + dob_out[2] <= SRVAL_B[2]; + dob_out[3] <= SRVAL_B[3]; + dob_out[4] <= SRVAL_B[4]; + dob_out[5] <= SRVAL_B[5]; + dob_out[6] <= SRVAL_B[6]; + dob_out[7] <= SRVAL_B[7]; + dob_out[8] <= SRVAL_B[8]; + dob_out[9] <= SRVAL_B[9]; + dob_out[10] <= SRVAL_B[10]; + dob_out[11] <= SRVAL_B[11]; + dob_out[12] <= SRVAL_B[12]; + dob_out[13] <= SRVAL_B[13]; + dob_out[14] <= SRVAL_B[14]; + dob_out[15] <= SRVAL_B[15]; + dob_out[16] <= SRVAL_B[16]; + dob_out[17] <= SRVAL_B[17]; + dob_out[18] <= SRVAL_B[18]; + dob_out[19] <= SRVAL_B[19]; + dob_out[20] <= SRVAL_B[20]; + dob_out[21] <= SRVAL_B[21]; + dob_out[22] <= SRVAL_B[22]; + dob_out[23] <= SRVAL_B[23]; + dob_out[24] <= SRVAL_B[24]; + dob_out[25] <= SRVAL_B[25]; + dob_out[26] <= SRVAL_B[26]; + dob_out[27] <= SRVAL_B[27]; + dob_out[28] <= SRVAL_B[28]; + dob_out[29] <= SRVAL_B[29]; + dob_out[30] <= SRVAL_B[30]; + dob_out[31] <= SRVAL_B[31]; + dopb_out[0] <= SRVAL_B[32]; + dopb_out[1] <= SRVAL_B[33]; + dopb_out[2] <= SRVAL_B[34]; + dopb_out[3] <= SRVAL_B[35]; + end + else begin + if (web_int == 1'b1) begin + if (wr_mode_b == 2'b00) begin + dob_out <= dib_int; + dopb_out <= dipb_int; + end + else if (wr_mode_b == 2'b01) begin + dob_out[0] <= mem[data_addrb_int + 0]; + dob_out[1] <= mem[data_addrb_int + 1]; + dob_out[2] <= mem[data_addrb_int + 2]; + dob_out[3] <= mem[data_addrb_int + 3]; + dob_out[4] <= mem[data_addrb_int + 4]; + dob_out[5] <= mem[data_addrb_int + 5]; + dob_out[6] <= mem[data_addrb_int + 6]; + dob_out[7] <= mem[data_addrb_int + 7]; + dob_out[8] <= mem[data_addrb_int + 8]; + dob_out[9] <= mem[data_addrb_int + 9]; + dob_out[10] <= mem[data_addrb_int + 10]; + dob_out[11] <= mem[data_addrb_int + 11]; + dob_out[12] <= mem[data_addrb_int + 12]; + dob_out[13] <= mem[data_addrb_int + 13]; + dob_out[14] <= mem[data_addrb_int + 14]; + dob_out[15] <= mem[data_addrb_int + 15]; + dob_out[16] <= mem[data_addrb_int + 16]; + dob_out[17] <= mem[data_addrb_int + 17]; + dob_out[18] <= mem[data_addrb_int + 18]; + dob_out[19] <= mem[data_addrb_int + 19]; + dob_out[20] <= mem[data_addrb_int + 20]; + dob_out[21] <= mem[data_addrb_int + 21]; + dob_out[22] <= mem[data_addrb_int + 22]; + dob_out[23] <= mem[data_addrb_int + 23]; + dob_out[24] <= mem[data_addrb_int + 24]; + dob_out[25] <= mem[data_addrb_int + 25]; + dob_out[26] <= mem[data_addrb_int + 26]; + dob_out[27] <= mem[data_addrb_int + 27]; + dob_out[28] <= mem[data_addrb_int + 28]; + dob_out[29] <= mem[data_addrb_int + 29]; + dob_out[30] <= mem[data_addrb_int + 30]; + dob_out[31] <= mem[data_addrb_int + 31]; + dopb_out[0] <= mem[parity_addrb_int + 0]; + dopb_out[1] <= mem[parity_addrb_int + 1]; + dopb_out[2] <= mem[parity_addrb_int + 2]; + dopb_out[3] <= mem[parity_addrb_int + 3]; + end + end + else begin + dob_out[0] <= mem[data_addrb_int + 0]; + dob_out[1] <= mem[data_addrb_int + 1]; + dob_out[2] <= mem[data_addrb_int + 2]; + dob_out[3] <= mem[data_addrb_int + 3]; + dob_out[4] <= mem[data_addrb_int + 4]; + dob_out[5] <= mem[data_addrb_int + 5]; + dob_out[6] <= mem[data_addrb_int + 6]; + dob_out[7] <= mem[data_addrb_int + 7]; + dob_out[8] <= mem[data_addrb_int + 8]; + dob_out[9] <= mem[data_addrb_int + 9]; + dob_out[10] <= mem[data_addrb_int + 10]; + dob_out[11] <= mem[data_addrb_int + 11]; + dob_out[12] <= mem[data_addrb_int + 12]; + dob_out[13] <= mem[data_addrb_int + 13]; + dob_out[14] <= mem[data_addrb_int + 14]; + dob_out[15] <= mem[data_addrb_int + 15]; + dob_out[16] <= mem[data_addrb_int + 16]; + dob_out[17] <= mem[data_addrb_int + 17]; + dob_out[18] <= mem[data_addrb_int + 18]; + dob_out[19] <= mem[data_addrb_int + 19]; + dob_out[20] <= mem[data_addrb_int + 20]; + dob_out[21] <= mem[data_addrb_int + 21]; + dob_out[22] <= mem[data_addrb_int + 22]; + dob_out[23] <= mem[data_addrb_int + 23]; + dob_out[24] <= mem[data_addrb_int + 24]; + dob_out[25] <= mem[data_addrb_int + 25]; + dob_out[26] <= mem[data_addrb_int + 26]; + dob_out[27] <= mem[data_addrb_int + 27]; + dob_out[28] <= mem[data_addrb_int + 28]; + dob_out[29] <= mem[data_addrb_int + 29]; + dob_out[30] <= mem[data_addrb_int + 30]; + dob_out[31] <= mem[data_addrb_int + 31]; + dopb_out[0] <= mem[parity_addrb_int + 0]; + dopb_out[1] <= mem[parity_addrb_int + 1]; + dopb_out[2] <= mem[parity_addrb_int + 2]; + dopb_out[3] <= mem[parity_addrb_int + 3]; + end + end + end + end + + always @(posedge clkb_int) begin + if (enb_int == 1'b1 && web_int == 1'b1) begin + mem[data_addrb_int + 0] <= dib_int[0]; + mem[data_addrb_int + 1] <= dib_int[1]; + mem[data_addrb_int + 2] <= dib_int[2]; + mem[data_addrb_int + 3] <= dib_int[3]; + mem[data_addrb_int + 4] <= dib_int[4]; + mem[data_addrb_int + 5] <= dib_int[5]; + mem[data_addrb_int + 6] <= dib_int[6]; + mem[data_addrb_int + 7] <= dib_int[7]; + mem[data_addrb_int + 8] <= dib_int[8]; + mem[data_addrb_int + 9] <= dib_int[9]; + mem[data_addrb_int + 10] <= dib_int[10]; + mem[data_addrb_int + 11] <= dib_int[11]; + mem[data_addrb_int + 12] <= dib_int[12]; + mem[data_addrb_int + 13] <= dib_int[13]; + mem[data_addrb_int + 14] <= dib_int[14]; + mem[data_addrb_int + 15] <= dib_int[15]; + mem[data_addrb_int + 16] <= dib_int[16]; + mem[data_addrb_int + 17] <= dib_int[17]; + mem[data_addrb_int + 18] <= dib_int[18]; + mem[data_addrb_int + 19] <= dib_int[19]; + mem[data_addrb_int + 20] <= dib_int[20]; + mem[data_addrb_int + 21] <= dib_int[21]; + mem[data_addrb_int + 22] <= dib_int[22]; + mem[data_addrb_int + 23] <= dib_int[23]; + mem[data_addrb_int + 24] <= dib_int[24]; + mem[data_addrb_int + 25] <= dib_int[25]; + mem[data_addrb_int + 26] <= dib_int[26]; + mem[data_addrb_int + 27] <= dib_int[27]; + mem[data_addrb_int + 28] <= dib_int[28]; + mem[data_addrb_int + 29] <= dib_int[29]; + mem[data_addrb_int + 30] <= dib_int[30]; + mem[data_addrb_int + 31] <= dib_int[31]; + mem[parity_addrb_int + 0] <= dipb_int[0]; + mem[parity_addrb_int + 1] <= dipb_int[1]; + mem[parity_addrb_int + 2] <= dipb_int[2]; + mem[parity_addrb_int + 3] <= dipb_int[3]; + end + end + + specify + (CLKA *> DOA) = (100, 100); + (CLKA *> DOPA) = (100, 100); + (CLKB *> DOB) = (100, 100); + (CLKB *> DOPB) = (100, 100); + endspecify + +endmodule + +`else + +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/RAMB16_S36_S36.v,v 1.10 2007/02/22 01:58:06 wloo Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2005 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Timing Simulation Library Component +// / / 16K-Bit Data and 2K-Bit Parity Dual Port Block RAM +// /___/ /\ Filename : RAMB16_S36_S36.v +// \ \ / \ Timestamp : Thu Mar 10 16:44:01 PST 2005 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 03/10/05 - Initialized outputs. +// 02/21/07 - Fixed parameter SIM_COLLISION_CHECK (CR 433281). +// End Revision + +`timescale 1 ps/1 ps + +module RAMB16_S36_S36 (DOA, DOB, DOPA, DOPB, ADDRA, ADDRB, CLKA, CLKB, DIA, DIB, DIPA, DIPB, ENA, ENB, SSRA, SSRB, WEA, WEB); + + parameter INIT_A = 36'h0; + parameter INIT_B = 36'h0; + parameter SRVAL_A = 36'h0; + parameter SRVAL_B = 36'h0; + parameter WRITE_MODE_A = "WRITE_FIRST"; + parameter WRITE_MODE_B = "WRITE_FIRST"; + parameter SIM_COLLISION_CHECK = "ALL"; + localparam SETUP_ALL = 1000; + localparam SETUP_READ_FIRST = 3000; + + parameter INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + + output [31:0] DOA; + output [3:0] DOPA; + output [31:0] DOB; + output [3:0] DOPB; + + input [8:0] ADDRA; + input [31:0] DIA; + input [3:0] DIPA; + input ENA, CLKA, WEA, SSRA; + input [8:0] ADDRB; + input [31:0] DIB; + input [3:0] DIPB; + input ENB, CLKB, WEB, SSRB; + + reg [31:0] doa_out = INIT_A[31:0]; + reg [3:0] dopa_out = INIT_A[35:32]; + reg [31:0] dob_out = INIT_B[31:0]; + reg [3:0] dopb_out = INIT_B[35:32]; + + reg [31:0] mem [511:0]; + reg [3:0] memp [511:0]; + + reg [8:0] count, countp; + reg [1:0] wr_mode_a, wr_mode_b; + + reg [5:0] dmi, dbi; + reg [5:0] pmi, pbi; + + wire [8:0] addra_int; + reg [8:0] addra_reg; + wire [31:0] dia_int; + wire [3:0] dipa_int; + wire ena_int, clka_int, wea_int, ssra_int; + reg ena_reg, wea_reg, ssra_reg; + wire [8:0] addrb_int; + reg [8:0] addrb_reg; + wire [31:0] dib_int; + wire [3:0] dipb_int; + wire enb_int, clkb_int, web_int, ssrb_int; + reg display_flag, output_flag; + reg enb_reg, web_reg, ssrb_reg; + + time time_clka, time_clkb; + time time_clka_clkb; + time time_clkb_clka; + + reg setup_all_a_b; + reg setup_all_b_a; + reg setup_zero; + reg setup_rf_a_b; + reg setup_rf_b_a; + reg [1:0] data_collision, data_collision_a_b, data_collision_b_a; + reg memory_collision, memory_collision_a_b, memory_collision_b_a; + reg change_clka; + reg change_clkb; + + wire [14:0] data_addra_int; + wire [14:0] data_addra_reg; + wire [14:0] data_addrb_int; + wire [14:0] data_addrb_reg; + + wire dia_enable = ena_int && wea_int; + wire dib_enable = enb_int && web_int; + + tri0 GSR = glbl.GSR; + wire gsr_int; + + buf b_gsr (gsr_int, GSR); + + buf b_doa [31:0] (DOA, doa_out); + buf b_dopa [3:0] (DOPA, dopa_out); + buf b_addra [8:0] (addra_int, ADDRA); + buf b_dia [31:0] (dia_int, DIA); + buf b_dipa [3:0] (dipa_int, DIPA); + buf b_ena (ena_int, ENA); + buf b_clka (clka_int, CLKA); + buf b_ssra (ssra_int, SSRA); + buf b_wea (wea_int, WEA); + + buf b_dob [31:0] (DOB, dob_out); + buf b_dopb [3:0] (DOPB, dopb_out); + buf b_addrb [8:0] (addrb_int, ADDRB); + buf b_dib [31:0] (dib_int, DIB); + buf b_dipb [3:0] (dipb_int, DIPB); + buf b_enb (enb_int, ENB); + buf b_clkb (clkb_int, CLKB); + buf b_ssrb (ssrb_int, SSRB); + buf b_web (web_int, WEB); + + + always @(gsr_int) + if (gsr_int) begin + assign {dopa_out, doa_out} = INIT_A; + assign {dopb_out, dob_out} = INIT_B; + end + else begin + deassign doa_out; + deassign dopa_out; + deassign dob_out; + deassign dopb_out; + end + + + initial begin + + for (count = 0; count < 8; count = count + 1) begin + mem[count] = INIT_00[(count * 32) +: 32]; + mem[8 * 1 + count] = INIT_01[(count * 32) +: 32]; + mem[8 * 2 + count] = INIT_02[(count * 32) +: 32]; + mem[8 * 3 + count] = INIT_03[(count * 32) +: 32]; + mem[8 * 4 + count] = INIT_04[(count * 32) +: 32]; + mem[8 * 5 + count] = INIT_05[(count * 32) +: 32]; + mem[8 * 6 + count] = INIT_06[(count * 32) +: 32]; + mem[8 * 7 + count] = INIT_07[(count * 32) +: 32]; + mem[8 * 8 + count] = INIT_08[(count * 32) +: 32]; + mem[8 * 9 + count] = INIT_09[(count * 32) +: 32]; + mem[8 * 10 + count] = INIT_0A[(count * 32) +: 32]; + mem[8 * 11 + count] = INIT_0B[(count * 32) +: 32]; + mem[8 * 12 + count] = INIT_0C[(count * 32) +: 32]; + mem[8 * 13 + count] = INIT_0D[(count * 32) +: 32]; + mem[8 * 14 + count] = INIT_0E[(count * 32) +: 32]; + mem[8 * 15 + count] = INIT_0F[(count * 32) +: 32]; + mem[8 * 16 + count] = INIT_10[(count * 32) +: 32]; + mem[8 * 17 + count] = INIT_11[(count * 32) +: 32]; + mem[8 * 18 + count] = INIT_12[(count * 32) +: 32]; + mem[8 * 19 + count] = INIT_13[(count * 32) +: 32]; + mem[8 * 20 + count] = INIT_14[(count * 32) +: 32]; + mem[8 * 21 + count] = INIT_15[(count * 32) +: 32]; + mem[8 * 22 + count] = INIT_16[(count * 32) +: 32]; + mem[8 * 23 + count] = INIT_17[(count * 32) +: 32]; + mem[8 * 24 + count] = INIT_18[(count * 32) +: 32]; + mem[8 * 25 + count] = INIT_19[(count * 32) +: 32]; + mem[8 * 26 + count] = INIT_1A[(count * 32) +: 32]; + mem[8 * 27 + count] = INIT_1B[(count * 32) +: 32]; + mem[8 * 28 + count] = INIT_1C[(count * 32) +: 32]; + mem[8 * 29 + count] = INIT_1D[(count * 32) +: 32]; + mem[8 * 30 + count] = INIT_1E[(count * 32) +: 32]; + mem[8 * 31 + count] = INIT_1F[(count * 32) +: 32]; + mem[8 * 32 + count] = INIT_20[(count * 32) +: 32]; + mem[8 * 33 + count] = INIT_21[(count * 32) +: 32]; + mem[8 * 34 + count] = INIT_22[(count * 32) +: 32]; + mem[8 * 35 + count] = INIT_23[(count * 32) +: 32]; + mem[8 * 36 + count] = INIT_24[(count * 32) +: 32]; + mem[8 * 37 + count] = INIT_25[(count * 32) +: 32]; + mem[8 * 38 + count] = INIT_26[(count * 32) +: 32]; + mem[8 * 39 + count] = INIT_27[(count * 32) +: 32]; + mem[8 * 40 + count] = INIT_28[(count * 32) +: 32]; + mem[8 * 41 + count] = INIT_29[(count * 32) +: 32]; + mem[8 * 42 + count] = INIT_2A[(count * 32) +: 32]; + mem[8 * 43 + count] = INIT_2B[(count * 32) +: 32]; + mem[8 * 44 + count] = INIT_2C[(count * 32) +: 32]; + mem[8 * 45 + count] = INIT_2D[(count * 32) +: 32]; + mem[8 * 46 + count] = INIT_2E[(count * 32) +: 32]; + mem[8 * 47 + count] = INIT_2F[(count * 32) +: 32]; + mem[8 * 48 + count] = INIT_30[(count * 32) +: 32]; + mem[8 * 49 + count] = INIT_31[(count * 32) +: 32]; + mem[8 * 50 + count] = INIT_32[(count * 32) +: 32]; + mem[8 * 51 + count] = INIT_33[(count * 32) +: 32]; + mem[8 * 52 + count] = INIT_34[(count * 32) +: 32]; + mem[8 * 53 + count] = INIT_35[(count * 32) +: 32]; + mem[8 * 54 + count] = INIT_36[(count * 32) +: 32]; + mem[8 * 55 + count] = INIT_37[(count * 32) +: 32]; + mem[8 * 56 + count] = INIT_38[(count * 32) +: 32]; + mem[8 * 57 + count] = INIT_39[(count * 32) +: 32]; + mem[8 * 58 + count] = INIT_3A[(count * 32) +: 32]; + mem[8 * 59 + count] = INIT_3B[(count * 32) +: 32]; + mem[8 * 60 + count] = INIT_3C[(count * 32) +: 32]; + mem[8 * 61 + count] = INIT_3D[(count * 32) +: 32]; + mem[8 * 62 + count] = INIT_3E[(count * 32) +: 32]; + mem[8 * 63 + count] = INIT_3F[(count * 32) +: 32]; + end + +// initiate parity start + for (countp = 0; countp < 64; countp = countp + 1) begin + memp[countp] = INITP_00[(countp * 4) +: 4]; + memp[64 * 1 + countp] = INITP_01[(countp * 4) +: 4]; + memp[64 * 2 + countp] = INITP_02[(countp * 4) +: 4]; + memp[64 * 3 + countp] = INITP_03[(countp * 4) +: 4]; + memp[64 * 4 + countp] = INITP_04[(countp * 4) +: 4]; + memp[64 * 5 + countp] = INITP_05[(countp * 4) +: 4]; + memp[64 * 6 + countp] = INITP_06[(countp * 4) +: 4]; + memp[64 * 7 + countp] = INITP_07[(countp * 4) +: 4]; + end +// initiate parity end + + change_clka <= 0; + change_clkb <= 0; + data_collision <= 0; + data_collision_a_b <= 0; + data_collision_b_a <= 0; + memory_collision <= 0; + memory_collision_a_b <= 0; + memory_collision_b_a <= 0; + setup_all_a_b <= 0; + setup_all_b_a <= 0; + setup_zero <= 0; + setup_rf_a_b <= 0; + setup_rf_b_a <= 0; + end + + assign data_addra_int = addra_int * 32; + assign data_addra_reg = addra_reg * 32; + assign data_addrb_int = addrb_int * 32; + assign data_addrb_reg = addrb_reg * 32; + + + initial begin + + display_flag = 1; + output_flag = 1; + + case (SIM_COLLISION_CHECK) + + "NONE" : begin + output_flag = 0; + display_flag = 0; + end + "WARNING_ONLY" : output_flag = 0; + "GENERATE_X_ONLY" : display_flag = 0; + "ALL" : ; + + default : begin + $display("Attribute Syntax Error : The Attribute SIM_COLLISION_CHECK on RAMB16_S36_S36 instance %m is set to %s. Legal values for this attribute are ALL, NONE, WARNING_ONLY or GENERATE_X_ONLY.", SIM_COLLISION_CHECK); + $finish; + end + + endcase // case(SIM_COLLISION_CHECK) + + end // initial begin + + + always @(posedge clka_int) begin + if ((output_flag || display_flag)) begin + time_clka = $time; + #0 time_clkb_clka = time_clka - time_clkb; + change_clka = ~change_clka; + end + end + + always @(posedge clkb_int) begin + if ((output_flag || display_flag)) begin + time_clkb = $time; + #0 time_clka_clkb = time_clkb - time_clka; + change_clkb = ~change_clkb; + end + end + + always @(change_clkb) begin + if ((0 < time_clka_clkb) && (time_clka_clkb < SETUP_ALL)) + setup_all_a_b = 1; + if ((0 < time_clka_clkb) && (time_clka_clkb < SETUP_READ_FIRST)) + setup_rf_a_b = 1; + end + + always @(change_clka) begin + if ((0 < time_clkb_clka) && (time_clkb_clka < SETUP_ALL)) + setup_all_b_a = 1; + if ((0 < time_clkb_clka) && (time_clkb_clka < SETUP_READ_FIRST)) + setup_rf_b_a = 1; + end + + always @(change_clkb or change_clka) begin + if ((time_clkb_clka == 0) && (time_clka_clkb == 0)) + setup_zero = 1; + end + + always @(posedge setup_zero) begin + if ((ena_int == 1) && (wea_int == 1) && + (enb_int == 1) && (web_int == 1) && + (data_addra_int[14:5] == data_addrb_int[14:5])) + memory_collision <= 1; + end + + always @(posedge setup_all_a_b or posedge setup_rf_a_b) begin + if ((ena_reg == 1) && (wea_reg == 1) && + (enb_int == 1) && (web_int == 1) && + (data_addra_reg[14:5] == data_addrb_int[14:5])) + memory_collision_a_b <= 1; + end + + always @(posedge setup_all_b_a or posedge setup_rf_b_a) begin + if ((ena_int == 1) && (wea_int == 1) && + (enb_reg == 1) && (web_reg == 1) && + (data_addra_int[14:5] == data_addrb_reg[14:5])) + memory_collision_b_a <= 1; + end + + always @(posedge setup_all_a_b) begin + if (data_addra_reg[14:5] == data_addrb_int[14:5]) begin + if ((ena_reg == 1) && (enb_int == 1)) begin + case ({wr_mode_a, wr_mode_b, wea_reg, web_int}) + 6'b000011 : begin data_collision_a_b <= 2'b11; display_wa_wb; end + 6'b000111 : begin data_collision_a_b <= 2'b11; display_wa_wb; end + 6'b001011 : begin data_collision_a_b <= 2'b10; display_wa_wb; end +// 6'b010011 : begin data_collision_a_b <= 2'b00; display_wa_wb; end +// 6'b010111 : begin data_collision_a_b <= 2'b00; display_wa_wb; end +// 6'b011011 : begin data_collision_a_b <= 2'b00; display_wa_wb; end + 6'b100011 : begin data_collision_a_b <= 2'b01; display_wa_wb; end + 6'b100111 : begin data_collision_a_b <= 2'b01; display_wa_wb; end + 6'b101011 : begin display_wa_wb; end + 6'b000001 : begin data_collision_a_b <= 2'b10; display_ra_wb; end +// 6'b000101 : begin data_collision_a_b <= 2'b00; display_ra_wb; end + 6'b001001 : begin data_collision_a_b <= 2'b10; display_ra_wb; end + 6'b010001 : begin data_collision_a_b <= 2'b10; display_ra_wb; end +// 6'b010101 : begin data_collision_a_b <= 2'b00; display_ra_wb; end + 6'b011001 : begin data_collision_a_b <= 2'b10; display_ra_wb; end + 6'b100001 : begin data_collision_a_b <= 2'b10; display_ra_wb; end +// 6'b100101 : begin data_collision_a_b <= 2'b00; display_ra_wb; end + 6'b101001 : begin data_collision_a_b <= 2'b10; display_ra_wb; end + 6'b000010 : begin data_collision_a_b <= 2'b01; display_wa_rb; end + 6'b000110 : begin data_collision_a_b <= 2'b01; display_wa_rb; end + 6'b001010 : begin data_collision_a_b <= 2'b01; display_wa_rb; end +// 6'b010010 : begin data_collision_a_b <= 2'b00; display_wa_rb; end +// 6'b010110 : begin data_collision_a_b <= 2'b00; display_wa_rb; end +// 6'b011010 : begin data_collision_a_b <= 2'b00; display_wa_rb; end + 6'b100010 : begin data_collision_a_b <= 2'b01; display_wa_rb; end + 6'b100110 : begin data_collision_a_b <= 2'b01; display_wa_rb; end + 6'b101010 : begin data_collision_a_b <= 2'b01; display_wa_rb; end + endcase + end + end + setup_all_a_b <= 0; + end + + + always @(posedge setup_all_b_a) begin + if (data_addra_int[14:5] == data_addrb_reg[14:5]) begin + if ((ena_int == 1) && (enb_reg == 1)) begin + case ({wr_mode_a, wr_mode_b, wea_int, web_reg}) + 6'b000011 : begin data_collision_b_a <= 2'b11; display_wa_wb; end +// 6'b000111 : begin data_collision_b_a <= 2'b00; display_wa_wb; end + 6'b001011 : begin data_collision_b_a <= 2'b10; display_wa_wb; end + 6'b010011 : begin data_collision_b_a <= 2'b11; display_wa_wb; end +// 6'b010111 : begin data_collision_b_a <= 2'b00; display_wa_wb; end + 6'b011011 : begin data_collision_b_a <= 2'b10; display_wa_wb; end + 6'b100011 : begin data_collision_b_a <= 2'b01; display_wa_wb; end + 6'b100111 : begin data_collision_b_a <= 2'b01; display_wa_wb; end + 6'b101011 : begin display_wa_wb; end + 6'b000001 : begin data_collision_b_a <= 2'b10; display_ra_wb; end + 6'b000101 : begin data_collision_b_a <= 2'b10; display_ra_wb; end + 6'b001001 : begin data_collision_b_a <= 2'b10; display_ra_wb; end + 6'b010001 : begin data_collision_b_a <= 2'b10; display_ra_wb; end + 6'b010101 : begin data_collision_b_a <= 2'b10; display_ra_wb; end + 6'b011001 : begin data_collision_b_a <= 2'b10; display_ra_wb; end + 6'b100001 : begin data_collision_b_a <= 2'b10; display_ra_wb; end + 6'b100101 : begin data_collision_b_a <= 2'b10; display_ra_wb; end + 6'b101001 : begin data_collision_b_a <= 2'b10; display_ra_wb; end + 6'b000010 : begin data_collision_b_a <= 2'b01; display_wa_rb; end + 6'b000110 : begin data_collision_b_a <= 2'b01; display_wa_rb; end + 6'b001010 : begin data_collision_b_a <= 2'b01; display_wa_rb; end +// 6'b010010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end +// 6'b010110 : begin data_collision_b_a <= 2'b00; display_wa_rb; end +// 6'b011010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end + 6'b100010 : begin data_collision_b_a <= 2'b01; display_wa_rb; end + 6'b100110 : begin data_collision_b_a <= 2'b01; display_wa_rb; end + 6'b101010 : begin data_collision_b_a <= 2'b01; display_wa_rb; end + endcase + end + end + setup_all_b_a <= 0; + end + + + always @(posedge setup_zero) begin + if (data_addra_int[14:5] == data_addrb_int[14:5]) begin + if ((ena_int == 1) && (enb_int == 1)) begin + case ({wr_mode_a, wr_mode_b, wea_int, web_int}) + 6'b000011 : begin data_collision <= 2'b11; display_wa_wb; end + 6'b000111 : begin data_collision <= 2'b11; display_wa_wb; end + 6'b001011 : begin data_collision <= 2'b10; display_wa_wb; end + 6'b010011 : begin data_collision <= 2'b11; display_wa_wb; end + 6'b010111 : begin data_collision <= 2'b11; display_wa_wb; end + 6'b011011 : begin data_collision <= 2'b10; display_wa_wb; end + 6'b100011 : begin data_collision <= 2'b01; display_wa_wb; end + 6'b100111 : begin data_collision <= 2'b01; display_wa_wb; end + 6'b101011 : begin display_wa_wb; end + 6'b000001 : begin data_collision <= 2'b10; display_ra_wb; end +// 6'b000101 : begin data_collision <= 2'b00; display_ra_wb; end + 6'b001001 : begin data_collision <= 2'b10; display_ra_wb; end + 6'b010001 : begin data_collision <= 2'b10; display_ra_wb; end +// 6'b010101 : begin data_collision <= 2'b00; display_ra_wb; end + 6'b011001 : begin data_collision <= 2'b10; display_ra_wb; end + 6'b100001 : begin data_collision <= 2'b10; display_ra_wb; end +// 6'b100101 : begin data_collision <= 2'b00; display_ra_wb; end + 6'b101001 : begin data_collision <= 2'b10; display_ra_wb; end + 6'b000010 : begin data_collision <= 2'b01; display_wa_rb; end + 6'b000110 : begin data_collision <= 2'b01; display_wa_rb; end + 6'b001010 : begin data_collision <= 2'b01; display_wa_rb; end +// 6'b010010 : begin data_collision <= 2'b00; display_wa_rb; end +// 6'b010110 : begin data_collision <= 2'b00; display_wa_rb; end +// 6'b011010 : begin data_collision <= 2'b00; display_wa_rb; end + 6'b100010 : begin data_collision <= 2'b01; display_wa_rb; end + 6'b100110 : begin data_collision <= 2'b01; display_wa_rb; end + 6'b101010 : begin data_collision <= 2'b01; display_wa_rb; end + endcase + end + end + setup_zero <= 0; + end + + task display_ra_wb; + begin + if (display_flag) + $display("Memory Collision Error on RAMB16_S36_S36:%m at simulation time %.3f ns\nA read was performed on address %h (hex) of Port A while a write was requested to the same address on Port B. The write will be successful however the read value on Port A is unknown until the next CLKA cycle.", $time/1000.0, addra_int); + end + endtask + + task display_wa_rb; + begin + if (display_flag) + $display("Memory Collision Error on RAMB16_S36_S36:%m at simulation time %.3f ns\nA read was performed on address %h (hex) of Port B while a write was requested to the same address on Port A. The write will be successful however the read value on Port B is unknown until the next CLKB cycle.", $time/1000.0, addrb_int); + end + endtask + + task display_wa_wb; + begin + if (display_flag) + $display("Memory Collision Error on RAMB16_S36_S36:%m at simulation time %.3f ns\nA write was requested to the same address simultaneously at both Port A and Port B of the RAM. The contents written to the RAM at address location %h (hex) of Port A and address location %h (hex) of Port B are unknown.", $time/1000.0, addra_int, addrb_int); + end + endtask + + + always @(posedge setup_rf_a_b) begin + if (data_addra_reg[14:5] == data_addrb_int[14:5]) begin + if ((ena_reg == 1) && (enb_int == 1)) begin + case ({wr_mode_a, wr_mode_b, wea_reg, web_int}) +// 6'b000011 : begin data_collision_a_b <= 2'b00; display_wa_wb; end +// 6'b000111 : begin data_collision_a_b <= 2'b00; display_wa_wb; end +// 6'b001011 : begin data_collision_a_b <= 2'b00; display_wa_wb; end + 6'b010011 : begin data_collision_a_b <= 2'b11; display_wa_wb; end + 6'b010111 : begin data_collision_a_b <= 2'b11; display_wa_wb; end + 6'b011011 : begin data_collision_a_b <= 2'b10; display_wa_wb; end +// 6'b100011 : begin data_collision_a_b <= 2'b00; display_wa_wb; end +// 6'b100111 : begin data_collision_a_b <= 2'b00; display_wa_wb; end +// 6'b101011 : begin data_collision_a_b <= 2'b00; display_wa_wb; end +// 6'b000001 : begin data_collision_a_b <= 2'b00; display_ra_wb; end +// 6'b000101 : begin data_collision_a_b <= 2'b00; display_ra_wb; end +// 6'b001001 : begin data_collision_a_b <= 2'b00; display_ra_wb; end +// 6'b010001 : begin data_collision_a_b <= 2'b00; display_ra_wb; end +// 6'b010101 : begin data_collision_a_b <= 2'b00; display_ra_wb; end +// 6'b011001 : begin data_collision_a_b <= 2'b00; display_ra_wb; end +// 6'b100001 : begin data_collision_a_b <= 2'b00; display_ra_wb; end +// 6'b100101 : begin data_collision_a_b <= 2'b00; display_ra_wb; end +// 6'b101001 : begin data_collision_a_b <= 2'b00; display_ra_wb; end +// 6'b000010 : begin data_collision_a_b <= 2'b00; display_wa_rb; end +// 6'b000110 : begin data_collision_a_b <= 2'b00; display_wa_rb; end +// 6'b001010 : begin data_collision_a_b <= 2'b00; display_wa_rb; end + 6'b010010 : begin data_collision_a_b <= 2'b01; display_wa_rb; end + 6'b010110 : begin data_collision_a_b <= 2'b01; display_wa_rb; end + 6'b011010 : begin data_collision_a_b <= 2'b01; display_wa_rb; end +// 6'b100010 : begin data_collision_a_b <= 2'b00; display_wa_rb; end +// 6'b100110 : begin data_collision_a_b <= 2'b00; display_wa_rb; end +// 6'b101010 : begin data_collision_a_b <= 2'b00; display_wa_rb; end + endcase + end + end + setup_rf_a_b <= 0; + end + + + always @(posedge setup_rf_b_a) begin + if (data_addra_int[14:5] == data_addrb_reg[14:5]) begin + if ((ena_int == 1) && (enb_reg == 1)) begin + case ({wr_mode_a, wr_mode_b, wea_int, web_reg}) +// 6'b000011 : begin data_collision_b_a <= 2'b00; display_wa_wb; end + 6'b000111 : begin data_collision_b_a <= 2'b11; display_wa_wb; end +// 6'b001011 : begin data_collision_b_a <= 2'b00; display_wa_wb; end +// 6'b010011 : begin data_collision_b_a <= 2'b00; display_wa_wb; end + 6'b010111 : begin data_collision_b_a <= 2'b11; display_wa_wb; end +// 6'b011011 : begin data_collision_b_a <= 2'b00; display_wa_wb; end +// 6'b100011 : begin data_collision_b_a <= 2'b00; display_wa_wb; end + 6'b100111 : begin data_collision_b_a <= 2'b01; display_wa_wb; end +// 6'b101011 : begin data_collision_b_a <= 2'b00; display_wa_wb; end +// 6'b000001 : begin data_collision_b_a <= 2'b00; display_ra_wb; end + 6'b000101 : begin data_collision_b_a <= 2'b10; display_ra_wb; end +// 6'b001001 : begin data_collision_b_a <= 2'b00; display_ra_wb; end +// 6'b010001 : begin data_collision_b_a <= 2'b00; display_ra_wb; end + 6'b010101 : begin data_collision_b_a <= 2'b10; display_ra_wb; end +// 6'b011001 : begin data_collision_b_a <= 2'b00; display_ra_wb; end +// 6'b100001 : begin data_collision_b_a <= 2'b00; display_ra_wb; end + 6'b100101 : begin data_collision_b_a <= 2'b10; display_ra_wb; end +// 6'b101001 : begin data_collision_b_a <= 2'b00; display_ra_wb; end +// 6'b000010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end +// 6'b000110 : begin data_collision_b_a <= 2'b00; display_wa_rb; end +// 6'b001010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end +// 6'b010010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end +// 6'b010110 : begin data_collision_b_a <= 2'b00; display_wa_rb; end +// 6'b011010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end +// 6'b100010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end +// 6'b100110 : begin data_collision_b_a <= 2'b00; display_wa_rb; end +// 6'b101010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end + endcase + end + end + setup_rf_b_a <= 0; + end + + + always @(posedge clka_int) begin + if ((output_flag || display_flag)) begin + addra_reg <= addra_int; + ena_reg <= ena_int; + ssra_reg <= ssra_int; + wea_reg <= wea_int; + end + end + + always @(posedge clkb_int) begin + if ((output_flag || display_flag)) begin + addrb_reg <= addrb_int; + enb_reg <= enb_int; + ssrb_reg <= ssrb_int; + web_reg <= web_int; + end + end + + + // Data + always @(posedge memory_collision) begin + if ((output_flag || display_flag)) begin + mem[addra_int] <= 32'bx; + memory_collision <= 0; + end + + end + + always @(posedge memory_collision_a_b) begin + if ((output_flag || display_flag)) begin + mem[addra_reg] <= 32'bx; + memory_collision_a_b <= 0; + end + end + + always @(posedge memory_collision_b_a) begin + if ((output_flag || display_flag)) begin + mem[addra_int] <= 32'bx; + memory_collision_b_a <= 0; + end + end + + always @(posedge data_collision[1]) begin + if (ssra_int == 0 && output_flag) begin + doa_out <= #100 32'bX; + end + data_collision[1] <= 0; + end + + always @(posedge data_collision[0]) begin + if (ssrb_int == 0 && output_flag) begin + dob_out <= #100 32'bX; + end + data_collision[0] <= 0; + end + + always @(posedge data_collision_a_b[1]) begin + if (ssra_reg == 0 && output_flag) begin + doa_out <= #100 32'bX; + end + data_collision_a_b[1] <= 0; + end + + always @(posedge data_collision_a_b[0]) begin + if (ssrb_int == 0 && output_flag) begin + dob_out <= #100 32'bX; + end + data_collision_a_b[0] <= 0; + end + + always @(posedge data_collision_b_a[1]) begin + if (ssra_int == 0 && output_flag) begin + doa_out <= #100 32'bX; + end + data_collision_b_a[1] <= 0; + end + + always @(posedge data_collision_b_a[0]) begin + if (ssrb_reg == 0 && output_flag) begin + dob_out <= #100 32'bX; + end + data_collision_b_a[0] <= 0; + end + +// x parity start + always @(posedge memory_collision) begin + if ((output_flag || display_flag)) + memp[addra_int] <= 4'bx; + end + + always @(posedge memory_collision_a_b) begin + if ((output_flag || display_flag)) + memp[addra_reg] <= 4'bx; + end + + always @(posedge memory_collision_b_a) begin + if ((output_flag || display_flag)) + memp[addra_int] <= 4'bx; + end + + always @(posedge data_collision[1]) begin + if (ssra_int == 0 && output_flag) begin + dopa_out <= #100 4'bX; + end + end + + always @(posedge data_collision_a_b[1]) begin + if (ssra_reg == 0 && output_flag) begin + dopa_out <= #100 4'bX; + end + end + + + always @(posedge data_collision_b_a[1]) begin + if (ssra_int == 0 && output_flag) begin + dopa_out <= #100 4'bX; + end + end + + always @(posedge data_collision[0]) begin + if (ssrb_int == 0 && output_flag) begin + dopb_out <= #100 4'bx; + end + end + + always @(posedge data_collision_a_b[0]) begin + if (ssrb_int == 0 && output_flag) begin + dopb_out <= #100 4'bx; + end + end + + always @(posedge data_collision_b_a[0]) begin + if (ssrb_reg == 0 && output_flag) begin + dopb_out <= #100 4'bx; + end + end +// x parity end + + initial begin + case (WRITE_MODE_A) + "WRITE_FIRST" : wr_mode_a <= 2'b00; + "READ_FIRST" : wr_mode_a <= 2'b01; + "NO_CHANGE" : wr_mode_a <= 2'b10; + default : begin + $display("Attribute Syntax Error : The Attribute WRITE_MODE_A on RAMB16_S36_S36 instance %m is set to %s. Legal values for this attribute are WRITE_FIRST, READ_FIRST or NO_CHANGE.", WRITE_MODE_A); + $finish; + end + endcase + end + + initial begin + case (WRITE_MODE_B) + "WRITE_FIRST" : wr_mode_b <= 2'b00; + "READ_FIRST" : wr_mode_b <= 2'b01; + "NO_CHANGE" : wr_mode_b <= 2'b10; + default : begin + $display("Attribute Syntax Error : The Attribute WRITE_MODE_B on RAMB16_S36_S36 instance %m is set to %s. Legal values for this attribute are WRITE_FIRST, READ_FIRST or NO_CHANGE.", WRITE_MODE_B); + $finish; + end + endcase + end + + + // Port A + always @(posedge clka_int) begin + + if (ena_int == 1'b1) begin + + if (ssra_int == 1'b1) begin + {dopa_out, doa_out} <= #100 SRVAL_A; + end + else begin + if (wea_int == 1'b1) begin + if (wr_mode_a == 2'b00) begin + doa_out <= #100 dia_int; + dopa_out <= #100 dipa_int; + end + else if (wr_mode_a == 2'b01) begin + + doa_out <= #100 mem[addra_int]; + dopa_out <= #100 memp[addra_int]; + + end + end + else begin + + doa_out <= #100 mem[addra_int]; + dopa_out <= #100 memp[addra_int]; + + end + end + + // memory + if (wea_int == 1'b1) begin + mem[addra_int] <= dia_int; + memp[addra_int] <= dipa_int; + end + + end + end + + + // Port B + always @(posedge clkb_int) begin + + if (enb_int == 1'b1) begin + + if (ssrb_int == 1'b1) begin + {dopb_out, dob_out} <= #100 SRVAL_B; + end + else begin + if (web_int == 1'b1) begin + if (wr_mode_b == 2'b00) begin + dob_out <= #100 dib_int; + dopb_out <= #100 dipb_int; + end + else if (wr_mode_b == 2'b01) begin + dob_out <= #100 mem[addrb_int]; + dopb_out <= #100 memp[addrb_int]; + end + end + else begin + dob_out <= #100 mem[addrb_int]; + dopb_out <= #100 memp[addrb_int]; + end + end + + // memory + if (web_int == 1'b1) begin + mem[addrb_int] <= dib_int; + memp[addrb_int] <= dipb_int; + end + + end + end + + +endmodule + +`endif diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/RAMB16_S4.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/RAMB16_S4.v new file mode 100644 index 0000000..c2fe21a --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/RAMB16_S4.v @@ -0,0 +1,540 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/RAMB16_S4.v,v 1.7 2005/03/14 22:54:41 wloo Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2005 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / 16K-Bit Data and 2K-Bit Parity Single Port Block RAM +// /___/ /\ Filename : RAMB16_S4.v +// \ \ / \ Timestamp : Thu Mar 10 16:43:36 PST 2005 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// End Revision + +`ifdef legacy_model + +`timescale 1 ps / 1 ps + +module RAMB16_S4 (DO, ADDR, CLK, DI, EN, SSR, WE); + + parameter INIT = 4'h0; + parameter SRVAL = 4'h0; + parameter WRITE_MODE = "WRITE_FIRST"; + + parameter INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + + output [3:0] DO; + reg do0_out, do1_out, do2_out, do3_out; + + input [11:0] ADDR; + input [3:0] DI; + input EN, CLK, WE, SSR; + + reg [18431:0] mem; + reg [8:0] count; + reg [1:0] wr_mode; + + wire [11:0] addr_int; + wire [3:0] di_int; + wire en_int, clk_int, we_int, ssr_int; + + tri0 GSR = glbl.GSR; + + always @(GSR) + if (GSR) begin + assign do0_out = INIT[0]; + assign do1_out = INIT[1]; + assign do2_out = INIT[2]; + assign do3_out = INIT[3]; + end + else begin + deassign do0_out; + deassign do1_out; + deassign do2_out; + deassign do3_out; + end + + buf b_do_out0 (DO[0], do0_out); + buf b_do_out1 (DO[1], do1_out); + buf b_do_out2 (DO[2], do2_out); + buf b_do_out3 (DO[3], do3_out); + buf b_addr_0 (addr_int[0], ADDR[0]); + buf b_addr_1 (addr_int[1], ADDR[1]); + buf b_addr_2 (addr_int[2], ADDR[2]); + buf b_addr_3 (addr_int[3], ADDR[3]); + buf b_addr_4 (addr_int[4], ADDR[4]); + buf b_addr_5 (addr_int[5], ADDR[5]); + buf b_addr_6 (addr_int[6], ADDR[6]); + buf b_addr_7 (addr_int[7], ADDR[7]); + buf b_addr_8 (addr_int[8], ADDR[8]); + buf b_addr_9 (addr_int[9], ADDR[9]); + buf b_addr_10 (addr_int[10], ADDR[10]); + buf b_addr_11 (addr_int[11], ADDR[11]); + buf b_di_0 (di_int[0], DI[0]); + buf b_di_1 (di_int[1], DI[1]); + buf b_di_2 (di_int[2], DI[2]); + buf b_di_3 (di_int[3], DI[3]); + buf b_en (en_int, EN); + buf b_clk (clk_int, CLK); + buf b_we (we_int, WE); + buf b_ssr (ssr_int, SSR); + + initial begin + for (count = 0; count < 256; count = count + 1) begin + mem[count] <= INIT_00[count]; + mem[256 * 1 + count] <= INIT_01[count]; + mem[256 * 2 + count] <= INIT_02[count]; + mem[256 * 3 + count] <= INIT_03[count]; + mem[256 * 4 + count] <= INIT_04[count]; + mem[256 * 5 + count] <= INIT_05[count]; + mem[256 * 6 + count] <= INIT_06[count]; + mem[256 * 7 + count] <= INIT_07[count]; + mem[256 * 8 + count] <= INIT_08[count]; + mem[256 * 9 + count] <= INIT_09[count]; + mem[256 * 10 + count] <= INIT_0A[count]; + mem[256 * 11 + count] <= INIT_0B[count]; + mem[256 * 12 + count] <= INIT_0C[count]; + mem[256 * 13 + count] <= INIT_0D[count]; + mem[256 * 14 + count] <= INIT_0E[count]; + mem[256 * 15 + count] <= INIT_0F[count]; + mem[256 * 16 + count] <= INIT_10[count]; + mem[256 * 17 + count] <= INIT_11[count]; + mem[256 * 18 + count] <= INIT_12[count]; + mem[256 * 19 + count] <= INIT_13[count]; + mem[256 * 20 + count] <= INIT_14[count]; + mem[256 * 21 + count] <= INIT_15[count]; + mem[256 * 22 + count] <= INIT_16[count]; + mem[256 * 23 + count] <= INIT_17[count]; + mem[256 * 24 + count] <= INIT_18[count]; + mem[256 * 25 + count] <= INIT_19[count]; + mem[256 * 26 + count] <= INIT_1A[count]; + mem[256 * 27 + count] <= INIT_1B[count]; + mem[256 * 28 + count] <= INIT_1C[count]; + mem[256 * 29 + count] <= INIT_1D[count]; + mem[256 * 30 + count] <= INIT_1E[count]; + mem[256 * 31 + count] <= INIT_1F[count]; + mem[256 * 32 + count] <= INIT_20[count]; + mem[256 * 33 + count] <= INIT_21[count]; + mem[256 * 34 + count] <= INIT_22[count]; + mem[256 * 35 + count] <= INIT_23[count]; + mem[256 * 36 + count] <= INIT_24[count]; + mem[256 * 37 + count] <= INIT_25[count]; + mem[256 * 38 + count] <= INIT_26[count]; + mem[256 * 39 + count] <= INIT_27[count]; + mem[256 * 40 + count] <= INIT_28[count]; + mem[256 * 41 + count] <= INIT_29[count]; + mem[256 * 42 + count] <= INIT_2A[count]; + mem[256 * 43 + count] <= INIT_2B[count]; + mem[256 * 44 + count] <= INIT_2C[count]; + mem[256 * 45 + count] <= INIT_2D[count]; + mem[256 * 46 + count] <= INIT_2E[count]; + mem[256 * 47 + count] <= INIT_2F[count]; + mem[256 * 48 + count] <= INIT_30[count]; + mem[256 * 49 + count] <= INIT_31[count]; + mem[256 * 50 + count] <= INIT_32[count]; + mem[256 * 51 + count] <= INIT_33[count]; + mem[256 * 52 + count] <= INIT_34[count]; + mem[256 * 53 + count] <= INIT_35[count]; + mem[256 * 54 + count] <= INIT_36[count]; + mem[256 * 55 + count] <= INIT_37[count]; + mem[256 * 56 + count] <= INIT_38[count]; + mem[256 * 57 + count] <= INIT_39[count]; + mem[256 * 58 + count] <= INIT_3A[count]; + mem[256 * 59 + count] <= INIT_3B[count]; + mem[256 * 60 + count] <= INIT_3C[count]; + mem[256 * 61 + count] <= INIT_3D[count]; + mem[256 * 62 + count] <= INIT_3E[count]; + mem[256 * 63 + count] <= INIT_3F[count]; + end + end + + initial begin + case (WRITE_MODE) + "WRITE_FIRST" : wr_mode <= 2'b00; + "READ_FIRST" : wr_mode <= 2'b01; + "NO_CHANGE" : wr_mode <= 2'b10; + default : begin + $display("Attribute Syntax Error : The attribute WRITE_MODE on RAMB16_S4 instance %m is set to %s. Legal values for this attribute are WRITE_FIRST, READ_FIRST or NO_CHANGE.", WRITE_MODE); + $finish; + end + endcase + end + + always @(posedge clk_int) begin + if (en_int == 1'b1) begin + if (ssr_int == 1'b1) begin + do0_out <= SRVAL[0]; + do1_out <= SRVAL[1]; + do2_out <= SRVAL[2]; + do3_out <= SRVAL[3]; + end + else begin + if (we_int == 1'b1) begin + if (wr_mode == 2'b00) begin + do0_out <= di_int[0]; + do1_out <= di_int[1]; + do2_out <= di_int[2]; + do3_out <= di_int[3]; + end + else if (wr_mode == 2'b01) begin + do0_out <= mem[addr_int * 4 + 0]; + do1_out <= mem[addr_int * 4 + 1]; + do2_out <= mem[addr_int * 4 + 2]; + do3_out <= mem[addr_int * 4 + 3]; + end + else begin + do0_out <= do0_out; + do1_out <= do1_out; + do2_out <= do2_out; + do3_out <= do3_out; + end + end + else begin + do0_out <= mem[addr_int * 4 + 0]; + do1_out <= mem[addr_int * 4 + 1]; + do2_out <= mem[addr_int * 4 + 2]; + do3_out <= mem[addr_int * 4 + 3]; + end + end + end + end + + always @(posedge clk_int) begin + if (en_int == 1'b1 && we_int == 1'b1) begin + mem[addr_int * 4 + 0] <= di_int[0]; + mem[addr_int * 4 + 1] <= di_int[1]; + mem[addr_int * 4 + 2] <= di_int[2]; + mem[addr_int * 4 + 3] <= di_int[3]; + end + end + + specify + (CLK *> DO) = (100, 100); + endspecify + +endmodule + +`else + +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/RAMB16_S4.v,v 1.7 2005/03/14 22:54:41 wloo Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2005 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Timing Simulation Library Component +// / / 16K-Bit Data and 2K-Bit Parity Single Port Block RAM +// /___/ /\ Filename : RAMB16_S4.v +// \ \ / \ Timestamp : Thu Mar 10 16:44:01 PST 2005 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 03/10/05 - Initialized outputs. +// End Revision + +`timescale 1 ps/1 ps + +module RAMB16_S4 (DO, ADDR, CLK, DI, EN, SSR, WE); + + parameter INIT = 4'h0; + parameter SRVAL = 4'h0; + parameter WRITE_MODE = "WRITE_FIRST"; + + parameter INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + + output [3:0] DO; + + input [11:0] ADDR; + input [3:0] DI; + input EN, CLK, WE, SSR; + + reg [3:0] do_out = INIT[3:0]; + + reg [3:0] mem [4095:0]; + + reg [8:0] count, countp; + reg [1:0] wr_mode; + + wire [11:0] addr_int; + wire [3:0] di_int; + wire en_int, clk_int, we_int, ssr_int; + + wire di_enable = en_int && we_int; + + tri0 GSR = glbl.GSR; + wire gsr_int; + + buf b_gsr (gsr_int, GSR); + + buf b_do [3:0] (DO, do_out); + buf b_addr [11:0] (addr_int, ADDR); + buf b_di [3:0] (di_int, DI); + buf b_en (en_int, EN); + buf b_clk (clk_int, CLK); + buf b_ssr (ssr_int, SSR); + buf b_we (we_int, WE); + + + always @(gsr_int) + if (gsr_int) begin + assign {do_out} = INIT; + end + else begin + deassign do_out; + end + + + initial begin + + for (count = 0; count < 64; count = count + 1) begin + mem[count] = INIT_00[(count * 4) +: 4]; + mem[64 * 1 + count] = INIT_01[(count * 4) +: 4]; + mem[64 * 2 + count] = INIT_02[(count * 4) +: 4]; + mem[64 * 3 + count] = INIT_03[(count * 4) +: 4]; + mem[64 * 4 + count] = INIT_04[(count * 4) +: 4]; + mem[64 * 5 + count] = INIT_05[(count * 4) +: 4]; + mem[64 * 6 + count] = INIT_06[(count * 4) +: 4]; + mem[64 * 7 + count] = INIT_07[(count * 4) +: 4]; + mem[64 * 8 + count] = INIT_08[(count * 4) +: 4]; + mem[64 * 9 + count] = INIT_09[(count * 4) +: 4]; + mem[64 * 10 + count] = INIT_0A[(count * 4) +: 4]; + mem[64 * 11 + count] = INIT_0B[(count * 4) +: 4]; + mem[64 * 12 + count] = INIT_0C[(count * 4) +: 4]; + mem[64 * 13 + count] = INIT_0D[(count * 4) +: 4]; + mem[64 * 14 + count] = INIT_0E[(count * 4) +: 4]; + mem[64 * 15 + count] = INIT_0F[(count * 4) +: 4]; + mem[64 * 16 + count] = INIT_10[(count * 4) +: 4]; + mem[64 * 17 + count] = INIT_11[(count * 4) +: 4]; + mem[64 * 18 + count] = INIT_12[(count * 4) +: 4]; + mem[64 * 19 + count] = INIT_13[(count * 4) +: 4]; + mem[64 * 20 + count] = INIT_14[(count * 4) +: 4]; + mem[64 * 21 + count] = INIT_15[(count * 4) +: 4]; + mem[64 * 22 + count] = INIT_16[(count * 4) +: 4]; + mem[64 * 23 + count] = INIT_17[(count * 4) +: 4]; + mem[64 * 24 + count] = INIT_18[(count * 4) +: 4]; + mem[64 * 25 + count] = INIT_19[(count * 4) +: 4]; + mem[64 * 26 + count] = INIT_1A[(count * 4) +: 4]; + mem[64 * 27 + count] = INIT_1B[(count * 4) +: 4]; + mem[64 * 28 + count] = INIT_1C[(count * 4) +: 4]; + mem[64 * 29 + count] = INIT_1D[(count * 4) +: 4]; + mem[64 * 30 + count] = INIT_1E[(count * 4) +: 4]; + mem[64 * 31 + count] = INIT_1F[(count * 4) +: 4]; + mem[64 * 32 + count] = INIT_20[(count * 4) +: 4]; + mem[64 * 33 + count] = INIT_21[(count * 4) +: 4]; + mem[64 * 34 + count] = INIT_22[(count * 4) +: 4]; + mem[64 * 35 + count] = INIT_23[(count * 4) +: 4]; + mem[64 * 36 + count] = INIT_24[(count * 4) +: 4]; + mem[64 * 37 + count] = INIT_25[(count * 4) +: 4]; + mem[64 * 38 + count] = INIT_26[(count * 4) +: 4]; + mem[64 * 39 + count] = INIT_27[(count * 4) +: 4]; + mem[64 * 40 + count] = INIT_28[(count * 4) +: 4]; + mem[64 * 41 + count] = INIT_29[(count * 4) +: 4]; + mem[64 * 42 + count] = INIT_2A[(count * 4) +: 4]; + mem[64 * 43 + count] = INIT_2B[(count * 4) +: 4]; + mem[64 * 44 + count] = INIT_2C[(count * 4) +: 4]; + mem[64 * 45 + count] = INIT_2D[(count * 4) +: 4]; + mem[64 * 46 + count] = INIT_2E[(count * 4) +: 4]; + mem[64 * 47 + count] = INIT_2F[(count * 4) +: 4]; + mem[64 * 48 + count] = INIT_30[(count * 4) +: 4]; + mem[64 * 49 + count] = INIT_31[(count * 4) +: 4]; + mem[64 * 50 + count] = INIT_32[(count * 4) +: 4]; + mem[64 * 51 + count] = INIT_33[(count * 4) +: 4]; + mem[64 * 52 + count] = INIT_34[(count * 4) +: 4]; + mem[64 * 53 + count] = INIT_35[(count * 4) +: 4]; + mem[64 * 54 + count] = INIT_36[(count * 4) +: 4]; + mem[64 * 55 + count] = INIT_37[(count * 4) +: 4]; + mem[64 * 56 + count] = INIT_38[(count * 4) +: 4]; + mem[64 * 57 + count] = INIT_39[(count * 4) +: 4]; + mem[64 * 58 + count] = INIT_3A[(count * 4) +: 4]; + mem[64 * 59 + count] = INIT_3B[(count * 4) +: 4]; + mem[64 * 60 + count] = INIT_3C[(count * 4) +: 4]; + mem[64 * 61 + count] = INIT_3D[(count * 4) +: 4]; + mem[64 * 62 + count] = INIT_3E[(count * 4) +: 4]; + mem[64 * 63 + count] = INIT_3F[(count * 4) +: 4]; + end + + end // initial begin + + + initial begin + case (WRITE_MODE) + "WRITE_FIRST" : wr_mode <= 2'b00; + "READ_FIRST" : wr_mode <= 2'b01; + "NO_CHANGE" : wr_mode <= 2'b10; + default : begin + $display("Attribute Syntax Error : The Attribute WRITE_MODE on RAMB16_S4 instance %m is set to %s. Legal values for this attribute are WRITE_FIRST, READ_FIRST or NO_CHANGE.", WRITE_MODE); + $finish; + end + endcase + end + + + always @(posedge clk_int) begin + + if (en_int == 1'b1) begin + + if (ssr_int == 1'b1) begin + {do_out} <= #100 SRVAL; + end + else begin + if (we_int == 1'b1) begin + if (wr_mode == 2'b00) begin + do_out <= #100 di_int; + end + else if (wr_mode == 2'b01) begin + do_out <= #100 mem[addr_int]; + end + end + else begin + do_out <= #100 mem[addr_int]; + end + end + + // memory + if (we_int == 1'b1) begin + mem[addr_int] <= di_int; + end + + end + end + + +endmodule + +`endif diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/RAMB16_S4_S18.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/RAMB16_S4_S18.v new file mode 100644 index 0000000..f4eee36 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/RAMB16_S4_S18.v @@ -0,0 +1,1723 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/RAMB16_S4_S18.v,v 1.10 2007/02/22 01:58:06 wloo Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2005 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / 16K-Bit Data and 2K-Bit Parity Dual Port Block RAM +// /___/ /\ Filename : RAMB16_S4_S18.v +// \ \ / \ Timestamp : Thu Mar 10 16:43:36 PST 2005 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// End Revision + +`ifdef legacy_model + +`timescale 1 ps / 1 ps + +module RAMB16_S4_S18 (DOA, DOB, DOPB, ADDRA, ADDRB, CLKA, CLKB, DIA, DIB, DIPB, ENA, ENB, SSRA, SSRB, WEA, WEB); + + parameter INIT_A = 4'h0; + parameter INIT_B = 18'h0; + parameter SRVAL_A = 4'h0; + parameter SRVAL_B = 18'h0; + parameter WRITE_MODE_A = "WRITE_FIRST"; + parameter WRITE_MODE_B = "WRITE_FIRST"; + parameter SIM_COLLISION_CHECK = "ALL"; + localparam SETUP_ALL = 1000; + localparam SETUP_READ_FIRST = 3000; + + parameter INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + + output [3:0] DOA; + reg [3:0] doa_out; + wire doa_out0, doa_out1, doa_out2, doa_out3; + + input [11:0] ADDRA; + input [3:0] DIA; + input ENA, CLKA, WEA, SSRA; + + output [15:0] DOB; + output [1:0] DOPB; + reg [15:0] dob_out; + reg [1:0] dopb_out; + wire dob_out0, dob_out1, dob_out2, dob_out3, dob_out4, dob_out5, dob_out6, dob_out7, dob_out8, dob_out9, dob_out10, dob_out11, dob_out12, dob_out13, dob_out14, dob_out15; + wire dopb0_out, dopb1_out; + + input [9:0] ADDRB; + input [15:0] DIB; + input [1:0] DIPB; + input ENB, CLKB, WEB, SSRB; + + reg [18431:0] mem; + reg [8:0] count; + reg [1:0] wr_mode_a, wr_mode_b; + + reg [5:0] dmi, dbi; + reg [5:0] pmi, pbi; + + wire [11:0] addra_int; + reg [11:0] addra_reg; + wire [3:0] dia_int; + wire ena_int, clka_int, wea_int, ssra_int; + reg ena_reg, wea_reg, ssra_reg; + wire [9:0] addrb_int; + reg [9:0] addrb_reg; + wire [15:0] dib_int; + wire [1:0] dipb_int; + wire enb_int, clkb_int, web_int, ssrb_int; + reg display_flag; + reg enb_reg, web_reg, ssrb_reg; + + time time_clka, time_clkb; + time time_clka_clkb; + time time_clkb_clka; + + reg setup_all_a_b; + reg setup_all_b_a; + reg setup_zero; + reg setup_rf_a_b; + reg setup_rf_b_a; + reg [1:0] data_collision, data_collision_a_b, data_collision_b_a; + reg memory_collision, memory_collision_a_b, memory_collision_b_a; + reg address_collision, address_collision_a_b, address_collision_b_a; + reg change_clka; + reg change_clkb; + + wire [14:0] data_addra_int; + wire [14:0] data_addra_reg; + wire [14:0] data_addrb_int; + wire [14:0] data_addrb_reg; + wire [15:0] parity_addra_int; + wire [15:0] parity_addra_reg; + wire [15:0] parity_addrb_int; + wire [15:0] parity_addrb_reg; + + tri0 GSR = glbl.GSR; + + always @(GSR) + if (GSR) begin + assign doa_out = INIT_A[3:0]; + assign dob_out = INIT_B[15:0]; + assign dopb_out = INIT_B[17:16]; + end + else begin + deassign doa_out; + deassign dob_out; + deassign dopb_out; + end + + buf b_doa_out0 (doa_out0, doa_out[0]); + buf b_doa_out1 (doa_out1, doa_out[1]); + buf b_doa_out2 (doa_out2, doa_out[2]); + buf b_doa_out3 (doa_out3, doa_out[3]); + buf b_dob_out0 (dob_out0, dob_out[0]); + buf b_dob_out1 (dob_out1, dob_out[1]); + buf b_dob_out2 (dob_out2, dob_out[2]); + buf b_dob_out3 (dob_out3, dob_out[3]); + buf b_dob_out4 (dob_out4, dob_out[4]); + buf b_dob_out5 (dob_out5, dob_out[5]); + buf b_dob_out6 (dob_out6, dob_out[6]); + buf b_dob_out7 (dob_out7, dob_out[7]); + buf b_dob_out8 (dob_out8, dob_out[8]); + buf b_dob_out9 (dob_out9, dob_out[9]); + buf b_dob_out10 (dob_out10, dob_out[10]); + buf b_dob_out11 (dob_out11, dob_out[11]); + buf b_dob_out12 (dob_out12, dob_out[12]); + buf b_dob_out13 (dob_out13, dob_out[13]); + buf b_dob_out14 (dob_out14, dob_out[14]); + buf b_dob_out15 (dob_out15, dob_out[15]); + buf b_dopb_out0 (dopb_out0, dopb_out[0]); + buf b_dopb_out1 (dopb_out1, dopb_out[1]); + + buf b_doa0 (DOA[0], doa_out0); + buf b_doa1 (DOA[1], doa_out1); + buf b_doa2 (DOA[2], doa_out2); + buf b_doa3 (DOA[3], doa_out3); + buf b_dob0 (DOB[0], dob_out0); + buf b_dob1 (DOB[1], dob_out1); + buf b_dob2 (DOB[2], dob_out2); + buf b_dob3 (DOB[3], dob_out3); + buf b_dob4 (DOB[4], dob_out4); + buf b_dob5 (DOB[5], dob_out5); + buf b_dob6 (DOB[6], dob_out6); + buf b_dob7 (DOB[7], dob_out7); + buf b_dob8 (DOB[8], dob_out8); + buf b_dob9 (DOB[9], dob_out9); + buf b_dob10 (DOB[10], dob_out10); + buf b_dob11 (DOB[11], dob_out11); + buf b_dob12 (DOB[12], dob_out12); + buf b_dob13 (DOB[13], dob_out13); + buf b_dob14 (DOB[14], dob_out14); + buf b_dob15 (DOB[15], dob_out15); + buf b_dopb0 (DOPB[0], dopb_out0); + buf b_dopb1 (DOPB[1], dopb_out1); + + buf b_addra_0 (addra_int[0], ADDRA[0]); + buf b_addra_1 (addra_int[1], ADDRA[1]); + buf b_addra_2 (addra_int[2], ADDRA[2]); + buf b_addra_3 (addra_int[3], ADDRA[3]); + buf b_addra_4 (addra_int[4], ADDRA[4]); + buf b_addra_5 (addra_int[5], ADDRA[5]); + buf b_addra_6 (addra_int[6], ADDRA[6]); + buf b_addra_7 (addra_int[7], ADDRA[7]); + buf b_addra_8 (addra_int[8], ADDRA[8]); + buf b_addra_9 (addra_int[9], ADDRA[9]); + buf b_addra_10 (addra_int[10], ADDRA[10]); + buf b_addra_11 (addra_int[11], ADDRA[11]); + buf b_dia_0 (dia_int[0], DIA[0]); + buf b_dia_1 (dia_int[1], DIA[1]); + buf b_dia_2 (dia_int[2], DIA[2]); + buf b_dia_3 (dia_int[3], DIA[3]); + buf b_ena (ena_int, ENA); + buf b_clka (clka_int, CLKA); + buf b_ssra (ssra_int, SSRA); + buf b_wea (wea_int, WEA); + buf b_addrb_0 (addrb_int[0], ADDRB[0]); + buf b_addrb_1 (addrb_int[1], ADDRB[1]); + buf b_addrb_2 (addrb_int[2], ADDRB[2]); + buf b_addrb_3 (addrb_int[3], ADDRB[3]); + buf b_addrb_4 (addrb_int[4], ADDRB[4]); + buf b_addrb_5 (addrb_int[5], ADDRB[5]); + buf b_addrb_6 (addrb_int[6], ADDRB[6]); + buf b_addrb_7 (addrb_int[7], ADDRB[7]); + buf b_addrb_8 (addrb_int[8], ADDRB[8]); + buf b_addrb_9 (addrb_int[9], ADDRB[9]); + buf b_dib_0 (dib_int[0], DIB[0]); + buf b_dib_1 (dib_int[1], DIB[1]); + buf b_dib_2 (dib_int[2], DIB[2]); + buf b_dib_3 (dib_int[3], DIB[3]); + buf b_dib_4 (dib_int[4], DIB[4]); + buf b_dib_5 (dib_int[5], DIB[5]); + buf b_dib_6 (dib_int[6], DIB[6]); + buf b_dib_7 (dib_int[7], DIB[7]); + buf b_dib_8 (dib_int[8], DIB[8]); + buf b_dib_9 (dib_int[9], DIB[9]); + buf b_dib_10 (dib_int[10], DIB[10]); + buf b_dib_11 (dib_int[11], DIB[11]); + buf b_dib_12 (dib_int[12], DIB[12]); + buf b_dib_13 (dib_int[13], DIB[13]); + buf b_dib_14 (dib_int[14], DIB[14]); + buf b_dib_15 (dib_int[15], DIB[15]); + buf b_dipb_0 (dipb_int[0], DIPB[0]); + buf b_dipb_1 (dipb_int[1], DIPB[1]); + buf b_enb (enb_int, ENB); + buf b_clkb (clkb_int, CLKB); + buf b_ssrb (ssrb_int, SSRB); + buf b_web (web_int, WEB); + + initial begin + for (count = 0; count < 256; count = count + 1) begin + mem[count] <= INIT_00[count]; + mem[256 * 1 + count] <= INIT_01[count]; + mem[256 * 2 + count] <= INIT_02[count]; + mem[256 * 3 + count] <= INIT_03[count]; + mem[256 * 4 + count] <= INIT_04[count]; + mem[256 * 5 + count] <= INIT_05[count]; + mem[256 * 6 + count] <= INIT_06[count]; + mem[256 * 7 + count] <= INIT_07[count]; + mem[256 * 8 + count] <= INIT_08[count]; + mem[256 * 9 + count] <= INIT_09[count]; + mem[256 * 10 + count] <= INIT_0A[count]; + mem[256 * 11 + count] <= INIT_0B[count]; + mem[256 * 12 + count] <= INIT_0C[count]; + mem[256 * 13 + count] <= INIT_0D[count]; + mem[256 * 14 + count] <= INIT_0E[count]; + mem[256 * 15 + count] <= INIT_0F[count]; + mem[256 * 16 + count] <= INIT_10[count]; + mem[256 * 17 + count] <= INIT_11[count]; + mem[256 * 18 + count] <= INIT_12[count]; + mem[256 * 19 + count] <= INIT_13[count]; + mem[256 * 20 + count] <= INIT_14[count]; + mem[256 * 21 + count] <= INIT_15[count]; + mem[256 * 22 + count] <= INIT_16[count]; + mem[256 * 23 + count] <= INIT_17[count]; + mem[256 * 24 + count] <= INIT_18[count]; + mem[256 * 25 + count] <= INIT_19[count]; + mem[256 * 26 + count] <= INIT_1A[count]; + mem[256 * 27 + count] <= INIT_1B[count]; + mem[256 * 28 + count] <= INIT_1C[count]; + mem[256 * 29 + count] <= INIT_1D[count]; + mem[256 * 30 + count] <= INIT_1E[count]; + mem[256 * 31 + count] <= INIT_1F[count]; + mem[256 * 32 + count] <= INIT_20[count]; + mem[256 * 33 + count] <= INIT_21[count]; + mem[256 * 34 + count] <= INIT_22[count]; + mem[256 * 35 + count] <= INIT_23[count]; + mem[256 * 36 + count] <= INIT_24[count]; + mem[256 * 37 + count] <= INIT_25[count]; + mem[256 * 38 + count] <= INIT_26[count]; + mem[256 * 39 + count] <= INIT_27[count]; + mem[256 * 40 + count] <= INIT_28[count]; + mem[256 * 41 + count] <= INIT_29[count]; + mem[256 * 42 + count] <= INIT_2A[count]; + mem[256 * 43 + count] <= INIT_2B[count]; + mem[256 * 44 + count] <= INIT_2C[count]; + mem[256 * 45 + count] <= INIT_2D[count]; + mem[256 * 46 + count] <= INIT_2E[count]; + mem[256 * 47 + count] <= INIT_2F[count]; + mem[256 * 48 + count] <= INIT_30[count]; + mem[256 * 49 + count] <= INIT_31[count]; + mem[256 * 50 + count] <= INIT_32[count]; + mem[256 * 51 + count] <= INIT_33[count]; + mem[256 * 52 + count] <= INIT_34[count]; + mem[256 * 53 + count] <= INIT_35[count]; + mem[256 * 54 + count] <= INIT_36[count]; + mem[256 * 55 + count] <= INIT_37[count]; + mem[256 * 56 + count] <= INIT_38[count]; + mem[256 * 57 + count] <= INIT_39[count]; + mem[256 * 58 + count] <= INIT_3A[count]; + mem[256 * 59 + count] <= INIT_3B[count]; + mem[256 * 60 + count] <= INIT_3C[count]; + mem[256 * 61 + count] <= INIT_3D[count]; + mem[256 * 62 + count] <= INIT_3E[count]; + mem[256 * 63 + count] <= INIT_3F[count]; + mem[256 * 64 + count] <= INITP_00[count]; + mem[256 * 65 + count] <= INITP_01[count]; + mem[256 * 66 + count] <= INITP_02[count]; + mem[256 * 67 + count] <= INITP_03[count]; + mem[256 * 68 + count] <= INITP_04[count]; + mem[256 * 69 + count] <= INITP_05[count]; + mem[256 * 70 + count] <= INITP_06[count]; + mem[256 * 71 + count] <= INITP_07[count]; + end + address_collision <= 0; + address_collision_a_b <= 0; + address_collision_b_a <= 0; + change_clka <= 0; + change_clkb <= 0; + data_collision <= 0; + data_collision_a_b <= 0; + data_collision_b_a <= 0; + memory_collision <= 0; + memory_collision_a_b <= 0; + memory_collision_b_a <= 0; + setup_all_a_b <= 0; + setup_all_b_a <= 0; + setup_zero <= 0; + setup_rf_a_b <= 0; + setup_rf_b_a <= 0; + end + + assign data_addra_int = addra_int * 4; + assign data_addra_reg = addra_reg * 4; + assign data_addrb_int = addrb_int * 16; + assign data_addrb_reg = addrb_reg * 16; + assign parity_addrb_int = 16384 + addrb_int * 2; + assign parity_addrb_reg = 16384 + addrb_reg * 2; + + + initial begin + + display_flag = 1; + + case (SIM_COLLISION_CHECK) + + "NONE" : begin + assign setup_all_a_b = 1'b0; + assign setup_all_b_a = 1'b0; + assign setup_zero = 1'b0; + assign setup_rf_a_b = 1'b0; + assign setup_rf_b_a = 1'b0; + assign display_flag = 0; + end + "WARNING_ONLY" : begin + assign data_collision = 2'b00; + assign data_collision_a_b = 2'b00; + assign data_collision_b_a = 2'b00; + assign memory_collision = 1'b0; + assign memory_collision_a_b = 1'b0; + assign memory_collision_b_a = 1'b0; + end + "GENERATE_X_ONLY" : begin + assign display_flag = 0; + end + "ALL" : ; + default : begin + $display("Attribute Syntax Error : The Attribute SIM_COLLISION_CHECK on RAMB16_S4_S18 instance %m is set to %s. Legal values for this attribute are ALL, NONE, WARNING_ONLY or GENERATE_X_ONLY.", SIM_COLLISION_CHECK); + $finish; + end + + endcase // case(SIM_COLLISION_CHECK) + + end // initial begin + + + always @(posedge clka_int) begin + time_clka = $time; + #0 time_clkb_clka = time_clka - time_clkb; + change_clka = ~change_clka; + end + + always @(posedge clkb_int) begin + time_clkb = $time; + #0 time_clka_clkb = time_clkb - time_clka; + change_clkb = ~change_clkb; + end + + always @(change_clkb) begin + if ((0 < time_clka_clkb) && (time_clka_clkb < SETUP_ALL)) + setup_all_a_b = 1; + if ((0 < time_clka_clkb) && (time_clka_clkb < SETUP_READ_FIRST)) + setup_rf_a_b = 1; + end + + always @(change_clka) begin + if ((0 < time_clkb_clka) && (time_clkb_clka < SETUP_ALL)) + setup_all_b_a = 1; + if ((0 < time_clkb_clka) && (time_clkb_clka < SETUP_READ_FIRST)) + setup_rf_b_a = 1; + end + + always @(change_clkb or change_clka) begin + if ((time_clkb_clka == 0) && (time_clka_clkb == 0)) + setup_zero = 1; + end + + always @(posedge setup_zero) begin + if ((ena_int == 1) && (wea_int == 1) && + (enb_int == 1) && (web_int == 1) && + (data_addra_int[14:4] == data_addrb_int[14:4])) + memory_collision <= 1; + end + + always @(posedge setup_all_a_b or posedge setup_rf_a_b) begin + if ((ena_reg == 1) && (wea_reg == 1) && + (enb_int == 1) && (web_int == 1) && + (data_addra_reg[14:4] == data_addrb_int[14:4])) + memory_collision_a_b <= 1; + end + + always @(posedge setup_all_b_a or posedge setup_rf_b_a) begin + if ((ena_int == 1) && (wea_int == 1) && + (enb_reg == 1) && (web_reg == 1) && + (data_addra_int[14:4] == data_addrb_reg[14:4])) + memory_collision_b_a <= 1; + end + + always @(posedge setup_all_a_b) begin + if (data_addra_reg[14:4] == data_addrb_int[14:4]) begin + if ((ena_reg == 1) && (enb_int == 1)) begin + case ({wr_mode_a, wr_mode_b, wea_reg, web_int}) + 6'b000011 : begin data_collision_a_b <= 2'b11; display_wa_wb; end + 6'b000111 : begin data_collision_a_b <= 2'b11; display_wa_wb; end + 6'b001011 : begin data_collision_a_b <= 2'b10; display_wa_wb; end +// 6'b010011 : begin data_collision_a_b <= 2'b00; display_wa_wb; end +// 6'b010111 : begin data_collision_a_b <= 2'b00; display_wa_wb; end +// 6'b011011 : begin data_collision_a_b <= 2'b00; display_wa_wb; end + 6'b100011 : begin data_collision_a_b <= 2'b01; display_wa_wb; end + 6'b100111 : begin data_collision_a_b <= 2'b01; display_wa_wb; end + 6'b101011 : begin display_wa_wb; end + 6'b000001 : begin data_collision_a_b <= 2'b10; display_ra_wb; end +// 6'b000101 : begin data_collision_a_b <= 2'b00; display_ra_wb; end + 6'b001001 : begin data_collision_a_b <= 2'b10; display_ra_wb; end + 6'b010001 : begin data_collision_a_b <= 2'b10; display_ra_wb; end +// 6'b010101 : begin data_collision_a_b <= 2'b00; display_ra_wb; end + 6'b011001 : begin data_collision_a_b <= 2'b10; display_ra_wb; end + 6'b100001 : begin data_collision_a_b <= 2'b10; display_ra_wb; end +// 6'b100101 : begin data_collision_a_b <= 2'b00; display_ra_wb; end + 6'b101001 : begin data_collision_a_b <= 2'b10; display_ra_wb; end + 6'b000010 : begin data_collision_a_b <= 2'b01; display_wa_rb; end + 6'b000110 : begin data_collision_a_b <= 2'b01; display_wa_rb; end + 6'b001010 : begin data_collision_a_b <= 2'b01; display_wa_rb; end +// 6'b010010 : begin data_collision_a_b <= 2'b00; display_wa_rb; end +// 6'b010110 : begin data_collision_a_b <= 2'b00; display_wa_rb; end +// 6'b011010 : begin data_collision_a_b <= 2'b00; display_wa_rb; end + 6'b100010 : begin data_collision_a_b <= 2'b01; display_wa_rb; end + 6'b100110 : begin data_collision_a_b <= 2'b01; display_wa_rb; end + 6'b101010 : begin data_collision_a_b <= 2'b01; display_wa_rb; end + endcase + end + end + setup_all_a_b <= 0; + end + + + always @(posedge setup_all_b_a) begin + if (data_addra_int[14:4] == data_addrb_reg[14:4]) begin + if ((ena_int == 1) && (enb_reg == 1)) begin + case ({wr_mode_a, wr_mode_b, wea_int, web_reg}) + 6'b000011 : begin data_collision_b_a <= 2'b11; display_wa_wb; end +// 6'b000111 : begin data_collision_b_a <= 2'b00; display_wa_wb; end + 6'b001011 : begin data_collision_b_a <= 2'b10; display_wa_wb; end + 6'b010011 : begin data_collision_b_a <= 2'b11; display_wa_wb; end +// 6'b010111 : begin data_collision_b_a <= 2'b00; display_wa_wb; end + 6'b011011 : begin data_collision_b_a <= 2'b10; display_wa_wb; end + 6'b100011 : begin data_collision_b_a <= 2'b01; display_wa_wb; end + 6'b100111 : begin data_collision_b_a <= 2'b01; display_wa_wb; end + 6'b101011 : begin display_wa_wb; end + 6'b000001 : begin data_collision_b_a <= 2'b10; display_ra_wb; end + 6'b000101 : begin data_collision_b_a <= 2'b10; display_ra_wb; end + 6'b001001 : begin data_collision_b_a <= 2'b10; display_ra_wb; end + 6'b010001 : begin data_collision_b_a <= 2'b10; display_ra_wb; end + 6'b010101 : begin data_collision_b_a <= 2'b10; display_ra_wb; end + 6'b011001 : begin data_collision_b_a <= 2'b10; display_ra_wb; end + 6'b100001 : begin data_collision_b_a <= 2'b10; display_ra_wb; end + 6'b100101 : begin data_collision_b_a <= 2'b10; display_ra_wb; end + 6'b101001 : begin data_collision_b_a <= 2'b10; display_ra_wb; end + 6'b000010 : begin data_collision_b_a <= 2'b01; display_wa_rb; end + 6'b000110 : begin data_collision_b_a <= 2'b01; display_wa_rb; end + 6'b001010 : begin data_collision_b_a <= 2'b01; display_wa_rb; end +// 6'b010010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end +// 6'b010110 : begin data_collision_b_a <= 2'b00; display_wa_rb; end +// 6'b011010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end + 6'b100010 : begin data_collision_b_a <= 2'b01; display_wa_rb; end + 6'b100110 : begin data_collision_b_a <= 2'b01; display_wa_rb; end + 6'b101010 : begin data_collision_b_a <= 2'b01; display_wa_rb; end + endcase + end + end + setup_all_b_a <= 0; + end + + + always @(posedge setup_zero) begin + if (data_addra_int[14:4] == data_addrb_int[14:4]) begin + if ((ena_int == 1) && (enb_int == 1)) begin + case ({wr_mode_a, wr_mode_b, wea_int, web_int}) + 6'b000011 : begin data_collision <= 2'b11; display_wa_wb; end + 6'b000111 : begin data_collision <= 2'b11; display_wa_wb; end + 6'b001011 : begin data_collision <= 2'b10; display_wa_wb; end + 6'b010011 : begin data_collision <= 2'b11; display_wa_wb; end + 6'b010111 : begin data_collision <= 2'b11; display_wa_wb; end + 6'b011011 : begin data_collision <= 2'b10; display_wa_wb; end + 6'b100011 : begin data_collision <= 2'b01; display_wa_wb; end + 6'b100111 : begin data_collision <= 2'b01; display_wa_wb; end + 6'b101011 : begin display_wa_wb; end + 6'b000001 : begin data_collision <= 2'b10; display_ra_wb; end +// 6'b000101 : begin data_collision <= 2'b00; display_ra_wb; end + 6'b001001 : begin data_collision <= 2'b10; display_ra_wb; end + 6'b010001 : begin data_collision <= 2'b10; display_ra_wb; end +// 6'b010101 : begin data_collision <= 2'b00; display_ra_wb; end + 6'b011001 : begin data_collision <= 2'b10; display_ra_wb; end + 6'b100001 : begin data_collision <= 2'b10; display_ra_wb; end +// 6'b100101 : begin data_collision <= 2'b00; display_ra_wb; end + 6'b101001 : begin data_collision <= 2'b10; display_ra_wb; end + 6'b000010 : begin data_collision <= 2'b01; display_wa_rb; end + 6'b000110 : begin data_collision <= 2'b01; display_wa_rb; end + 6'b001010 : begin data_collision <= 2'b01; display_wa_rb; end +// 6'b010010 : begin data_collision <= 2'b00; display_wa_rb; end +// 6'b010110 : begin data_collision <= 2'b00; display_wa_rb; end +// 6'b011010 : begin data_collision <= 2'b00; display_wa_rb; end + 6'b100010 : begin data_collision <= 2'b01; display_wa_rb; end + 6'b100110 : begin data_collision <= 2'b01; display_wa_rb; end + 6'b101010 : begin data_collision <= 2'b01; display_wa_rb; end + endcase + end + end + setup_zero <= 0; + end + + task display_ra_wb; + begin + if (display_flag) + $display("Memory Collision Error on RAMB16_S4_S18:%m at simulation time %.3f ns\nA read was performed on address %h (hex) of Port A while a write was requested to the same address on Port B. The write will be successful however the read value on Port A is unknown until the next CLKA cycle.", $time/1000.0, addra_int); + end + endtask + + task display_wa_rb; + begin + if (display_flag) + $display("Memory Collision Error on RAMB16_S4_S18:%m at simulation time %.3f ns\nA read was performed on address %h (hex) of Port B while a write was requested to the same address on Port A. The write will be successful however the read value on Port B is unknown until the next CLKB cycle.", $time/1000.0, addrb_int); + end + endtask + + task display_wa_wb; + begin + if (display_flag) + $display("Memory Collision Error on RAMB16_S4_S18:%m at simulation time %.3f ns\nA write was requested to the same address simultaneously at both Port A and Port B of the RAM. The contents written to the RAM at address location %h (hex) of Port A and address location %h (hex) of Port B are unknown.", $time/1000.0, addra_int, addrb_int); + end + endtask + + + always @(posedge setup_rf_a_b) begin + if (data_addra_reg[14:4] == data_addrb_int[14:4]) begin + if ((ena_reg == 1) && (enb_int == 1)) begin + case ({wr_mode_a, wr_mode_b, wea_reg, web_int}) +// 6'b000011 : begin data_collision_a_b <= 2'b00; display_wa_wb; end +// 6'b000111 : begin data_collision_a_b <= 2'b00; display_wa_wb; end +// 6'b001011 : begin data_collision_a_b <= 2'b00; display_wa_wb; end + 6'b010011 : begin data_collision_a_b <= 2'b11; display_wa_wb; end + 6'b010111 : begin data_collision_a_b <= 2'b11; display_wa_wb; end + 6'b011011 : begin data_collision_a_b <= 2'b10; display_wa_wb; end +// 6'b100011 : begin data_collision_a_b <= 2'b00; display_wa_wb; end +// 6'b100111 : begin data_collision_a_b <= 2'b00; display_wa_wb; end +// 6'b101011 : begin data_collision_a_b <= 2'b00; display_wa_wb; end +// 6'b000001 : begin data_collision_a_b <= 2'b00; display_ra_wb; end +// 6'b000101 : begin data_collision_a_b <= 2'b00; display_ra_wb; end +// 6'b001001 : begin data_collision_a_b <= 2'b00; display_ra_wb; end +// 6'b010001 : begin data_collision_a_b <= 2'b00; display_ra_wb; end +// 6'b010101 : begin data_collision_a_b <= 2'b00; display_ra_wb; end +// 6'b011001 : begin data_collision_a_b <= 2'b00; display_ra_wb; end +// 6'b100001 : begin data_collision_a_b <= 2'b00; display_ra_wb; end +// 6'b100101 : begin data_collision_a_b <= 2'b00; display_ra_wb; end +// 6'b101001 : begin data_collision_a_b <= 2'b00; display_ra_wb; end +// 6'b000010 : begin data_collision_a_b <= 2'b00; display_wa_rb; end +// 6'b000110 : begin data_collision_a_b <= 2'b00; display_wa_rb; end +// 6'b001010 : begin data_collision_a_b <= 2'b00; display_wa_rb; end + 6'b010010 : begin data_collision_a_b <= 2'b01; display_wa_rb; end + 6'b010110 : begin data_collision_a_b <= 2'b01; display_wa_rb; end + 6'b011010 : begin data_collision_a_b <= 2'b01; display_wa_rb; end +// 6'b100010 : begin data_collision_a_b <= 2'b00; display_wa_rb; end +// 6'b100110 : begin data_collision_a_b <= 2'b00; display_wa_rb; end +// 6'b101010 : begin data_collision_a_b <= 2'b00; display_wa_rb; end + endcase + end + end + setup_rf_a_b <= 0; + end + + + always @(posedge setup_rf_b_a) begin + if (data_addra_int[14:4] == data_addrb_reg[14:4]) begin + if ((ena_int == 1) && (enb_reg == 1)) begin + case ({wr_mode_a, wr_mode_b, wea_int, web_reg}) +// 6'b000011 : begin data_collision_b_a <= 2'b00; display_wa_wb; end + 6'b000111 : begin data_collision_b_a <= 2'b11; display_wa_wb; end +// 6'b001011 : begin data_collision_b_a <= 2'b00; display_wa_wb; end +// 6'b010011 : begin data_collision_b_a <= 2'b00; display_wa_wb; end + 6'b010111 : begin data_collision_b_a <= 2'b11; display_wa_wb; end +// 6'b011011 : begin data_collision_b_a <= 2'b00; display_wa_wb; end +// 6'b100011 : begin data_collision_b_a <= 2'b00; display_wa_wb; end + 6'b100111 : begin data_collision_b_a <= 2'b01; display_wa_wb; end +// 6'b101011 : begin data_collision_b_a <= 2'b00; display_wa_wb; end +// 6'b000001 : begin data_collision_b_a <= 2'b00; display_ra_wb; end + 6'b000101 : begin data_collision_b_a <= 2'b10; display_ra_wb; end +// 6'b001001 : begin data_collision_b_a <= 2'b00; display_ra_wb; end +// 6'b010001 : begin data_collision_b_a <= 2'b00; display_ra_wb; end + 6'b010101 : begin data_collision_b_a <= 2'b10; display_ra_wb; end +// 6'b011001 : begin data_collision_b_a <= 2'b00; display_ra_wb; end +// 6'b100001 : begin data_collision_b_a <= 2'b00; display_ra_wb; end + 6'b100101 : begin data_collision_b_a <= 2'b10; display_ra_wb; end +// 6'b101001 : begin data_collision_b_a <= 2'b00; display_ra_wb; end +// 6'b000010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end +// 6'b000110 : begin data_collision_b_a <= 2'b00; display_wa_rb; end +// 6'b001010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end +// 6'b010010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end +// 6'b010110 : begin data_collision_b_a <= 2'b00; display_wa_rb; end +// 6'b011010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end +// 6'b100010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end +// 6'b100110 : begin data_collision_b_a <= 2'b00; display_wa_rb; end +// 6'b101010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end + endcase + end + end + setup_rf_b_a <= 0; + end + + + always @(posedge clka_int) begin + addra_reg <= addra_int; + ena_reg <= ena_int; + ssra_reg <= ssra_int; + wea_reg <= wea_int; + end + + always @(posedge clkb_int) begin + addrb_reg <= addrb_int; + enb_reg <= enb_int; + ssrb_reg <= ssrb_int; + web_reg <= web_int; + end + + // Data + always @(posedge memory_collision) begin + for (dmi = 0; dmi < 4; dmi = dmi + 1) begin + mem[data_addra_int + dmi] <= 1'bX; + end + memory_collision <= 0; + end + + always @(posedge memory_collision_a_b) begin + for (dmi = 0; dmi < 4; dmi = dmi + 1) begin + mem[data_addra_reg + dmi] <= 1'bX; + end + memory_collision_a_b <= 0; + end + + always @(posedge memory_collision_b_a) begin + for (dmi = 0; dmi < 4; dmi = dmi + 1) begin + mem[data_addra_int + dmi] <= 1'bX; + end + memory_collision_b_a <= 0; + end + + always @(posedge data_collision[1]) begin + if (ssra_int == 0) begin + doa_out <= 4'bX; + end + data_collision[1] <= 0; + end + + always @(posedge data_collision[0]) begin + if (ssrb_int == 0) begin + for (dbi = 0; dbi < 4; dbi = dbi + 1) begin + dob_out[data_addra_int[3 : 0] + dbi] <= 1'bX; + end + end + data_collision[0] <= 0; + end + + always @(posedge data_collision_a_b[1]) begin + if (ssra_reg == 0) begin + doa_out <= 4'bX; + end + data_collision_a_b[1] <= 0; + end + + always @(posedge data_collision_a_b[0]) begin + if (ssrb_int == 0) begin + for (dbi = 0; dbi < 4; dbi = dbi + 1) begin + dob_out[data_addra_reg[3 : 0] + dbi] <= 1'bX; + end + end + data_collision_a_b[0] <= 0; + end + + always @(posedge data_collision_b_a[1]) begin + if (ssra_int == 0) begin + doa_out <= 4'bX; + end + data_collision_b_a[1] <= 0; + end + + always @(posedge data_collision_b_a[0]) begin + if (ssrb_reg == 0) begin + for (dbi = 0; dbi < 4; dbi = dbi + 1) begin + dob_out[data_addra_int[3 : 0] + dbi] <= 1'bX; + end + end + data_collision_b_a[0] <= 0; + end + + + initial begin + case (WRITE_MODE_A) + "WRITE_FIRST" : wr_mode_a <= 2'b00; + "READ_FIRST" : wr_mode_a <= 2'b01; + "NO_CHANGE" : wr_mode_a <= 2'b10; + default : begin + $display("Attribute Syntax Error : The Attribute WRITE_MODE_A on RAMB16_S4_S18 instance %m is set to %s. Legal values for this attribute are WRITE_FIRST, READ_FIRST or NO_CHANGE.", WRITE_MODE_A); + $finish; + end + endcase + end + + initial begin + case (WRITE_MODE_B) + "WRITE_FIRST" : wr_mode_b <= 2'b00; + "READ_FIRST" : wr_mode_b <= 2'b01; + "NO_CHANGE" : wr_mode_b <= 2'b10; + default : begin + $display("Attribute Syntax Error : The Attribute WRITE_MODE_B on RAMB16_S4_S18 instance %m is set to %s. Legal values for this attribute are WRITE_FIRST, READ_FIRST or NO_CHANGE.", WRITE_MODE_B); + $finish; + end + endcase + end + + // Port A + always @(posedge clka_int) begin + if (ena_int == 1'b1) begin + if (ssra_int == 1'b1) begin + doa_out[0] <= SRVAL_A[0]; + doa_out[1] <= SRVAL_A[1]; + doa_out[2] <= SRVAL_A[2]; + doa_out[3] <= SRVAL_A[3]; + end + else begin + if (wea_int == 1'b1) begin + if (wr_mode_a == 2'b00) begin + doa_out <= dia_int; + end + else if (wr_mode_a == 2'b01) begin + doa_out[0] <= mem[data_addra_int + 0]; + doa_out[1] <= mem[data_addra_int + 1]; + doa_out[2] <= mem[data_addra_int + 2]; + doa_out[3] <= mem[data_addra_int + 3]; + end + end + else begin + doa_out[0] <= mem[data_addra_int + 0]; + doa_out[1] <= mem[data_addra_int + 1]; + doa_out[2] <= mem[data_addra_int + 2]; + doa_out[3] <= mem[data_addra_int + 3]; + end + end + end + end + + always @(posedge clka_int) begin + if (ena_int == 1'b1 && wea_int == 1'b1) begin + mem[data_addra_int + 0] <= dia_int[0]; + mem[data_addra_int + 1] <= dia_int[1]; + mem[data_addra_int + 2] <= dia_int[2]; + mem[data_addra_int + 3] <= dia_int[3]; + end + end + + // Port B + always @(posedge clkb_int) begin + if (enb_int == 1'b1) begin + if (ssrb_int == 1'b1) begin + dob_out[0] <= SRVAL_B[0]; + dob_out[1] <= SRVAL_B[1]; + dob_out[2] <= SRVAL_B[2]; + dob_out[3] <= SRVAL_B[3]; + dob_out[4] <= SRVAL_B[4]; + dob_out[5] <= SRVAL_B[5]; + dob_out[6] <= SRVAL_B[6]; + dob_out[7] <= SRVAL_B[7]; + dob_out[8] <= SRVAL_B[8]; + dob_out[9] <= SRVAL_B[9]; + dob_out[10] <= SRVAL_B[10]; + dob_out[11] <= SRVAL_B[11]; + dob_out[12] <= SRVAL_B[12]; + dob_out[13] <= SRVAL_B[13]; + dob_out[14] <= SRVAL_B[14]; + dob_out[15] <= SRVAL_B[15]; + dopb_out[0] <= SRVAL_B[16]; + dopb_out[1] <= SRVAL_B[17]; + end + else begin + if (web_int == 1'b1) begin + if (wr_mode_b == 2'b00) begin + dob_out <= dib_int; + dopb_out <= dipb_int; + end + else if (wr_mode_b == 2'b01) begin + dob_out[0] <= mem[data_addrb_int + 0]; + dob_out[1] <= mem[data_addrb_int + 1]; + dob_out[2] <= mem[data_addrb_int + 2]; + dob_out[3] <= mem[data_addrb_int + 3]; + dob_out[4] <= mem[data_addrb_int + 4]; + dob_out[5] <= mem[data_addrb_int + 5]; + dob_out[6] <= mem[data_addrb_int + 6]; + dob_out[7] <= mem[data_addrb_int + 7]; + dob_out[8] <= mem[data_addrb_int + 8]; + dob_out[9] <= mem[data_addrb_int + 9]; + dob_out[10] <= mem[data_addrb_int + 10]; + dob_out[11] <= mem[data_addrb_int + 11]; + dob_out[12] <= mem[data_addrb_int + 12]; + dob_out[13] <= mem[data_addrb_int + 13]; + dob_out[14] <= mem[data_addrb_int + 14]; + dob_out[15] <= mem[data_addrb_int + 15]; + dopb_out[0] <= mem[parity_addrb_int + 0]; + dopb_out[1] <= mem[parity_addrb_int + 1]; + end + end + else begin + dob_out[0] <= mem[data_addrb_int + 0]; + dob_out[1] <= mem[data_addrb_int + 1]; + dob_out[2] <= mem[data_addrb_int + 2]; + dob_out[3] <= mem[data_addrb_int + 3]; + dob_out[4] <= mem[data_addrb_int + 4]; + dob_out[5] <= mem[data_addrb_int + 5]; + dob_out[6] <= mem[data_addrb_int + 6]; + dob_out[7] <= mem[data_addrb_int + 7]; + dob_out[8] <= mem[data_addrb_int + 8]; + dob_out[9] <= mem[data_addrb_int + 9]; + dob_out[10] <= mem[data_addrb_int + 10]; + dob_out[11] <= mem[data_addrb_int + 11]; + dob_out[12] <= mem[data_addrb_int + 12]; + dob_out[13] <= mem[data_addrb_int + 13]; + dob_out[14] <= mem[data_addrb_int + 14]; + dob_out[15] <= mem[data_addrb_int + 15]; + dopb_out[0] <= mem[parity_addrb_int + 0]; + dopb_out[1] <= mem[parity_addrb_int + 1]; + end + end + end + end + + always @(posedge clkb_int) begin + if (enb_int == 1'b1 && web_int == 1'b1) begin + mem[data_addrb_int + 0] <= dib_int[0]; + mem[data_addrb_int + 1] <= dib_int[1]; + mem[data_addrb_int + 2] <= dib_int[2]; + mem[data_addrb_int + 3] <= dib_int[3]; + mem[data_addrb_int + 4] <= dib_int[4]; + mem[data_addrb_int + 5] <= dib_int[5]; + mem[data_addrb_int + 6] <= dib_int[6]; + mem[data_addrb_int + 7] <= dib_int[7]; + mem[data_addrb_int + 8] <= dib_int[8]; + mem[data_addrb_int + 9] <= dib_int[9]; + mem[data_addrb_int + 10] <= dib_int[10]; + mem[data_addrb_int + 11] <= dib_int[11]; + mem[data_addrb_int + 12] <= dib_int[12]; + mem[data_addrb_int + 13] <= dib_int[13]; + mem[data_addrb_int + 14] <= dib_int[14]; + mem[data_addrb_int + 15] <= dib_int[15]; + mem[parity_addrb_int + 0] <= dipb_int[0]; + mem[parity_addrb_int + 1] <= dipb_int[1]; + end + end + + specify + (CLKA *> DOA) = (100, 100); + (CLKB *> DOB) = (100, 100); + (CLKB *> DOPB) = (100, 100); + endspecify + +endmodule + +`else + +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/RAMB16_S4_S18.v,v 1.10 2007/02/22 01:58:06 wloo Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2005 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Timing Simulation Library Component +// / / 16K-Bit Data and 2K-Bit Parity Dual Port Block RAM +// /___/ /\ Filename : RAMB16_S4_S18.v +// \ \ / \ Timestamp : Thu Mar 10 16:44:01 PST 2005 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 03/10/05 - Initialized outputs. +// 02/21/07 - Fixed parameter SIM_COLLISION_CHECK (CR 433281). +// End Revision + +`timescale 1 ps/1 ps + +module RAMB16_S4_S18 (DOA, DOB, DOPB, ADDRA, ADDRB, CLKA, CLKB, DIA, DIB, DIPB, ENA, ENB, SSRA, SSRB, WEA, WEB); + + parameter INIT_A = 4'h0; + parameter INIT_B = 18'h0; + parameter SRVAL_A = 4'h0; + parameter SRVAL_B = 18'h0; + parameter WRITE_MODE_A = "WRITE_FIRST"; + parameter WRITE_MODE_B = "WRITE_FIRST"; + parameter SIM_COLLISION_CHECK = "ALL"; + localparam SETUP_ALL = 1000; + localparam SETUP_READ_FIRST = 3000; + + parameter INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + + output [3:0] DOA; + output [15:0] DOB; + output [1:0] DOPB; + + input [11:0] ADDRA; + input [3:0] DIA; + input ENA, CLKA, WEA, SSRA; + input [9:0] ADDRB; + input [15:0] DIB; + input [1:0] DIPB; + input ENB, CLKB, WEB, SSRB; + + reg [3:0] doa_out = INIT_A[3:0]; + reg [15:0] dob_out = INIT_B[15:0]; + reg [1:0] dopb_out = INIT_B[17:16]; + + reg [15:0] mem [1023:0]; + reg [1:0] memp [1023:0]; + + reg [8:0] count, countp; + reg [1:0] wr_mode_a, wr_mode_b; + + reg [5:0] dmi, dbi; + reg [5:0] pmi, pbi; + + wire [11:0] addra_int; + reg [11:0] addra_reg; + wire [3:0] dia_int; + wire ena_int, clka_int, wea_int, ssra_int; + reg ena_reg, wea_reg, ssra_reg; + wire [9:0] addrb_int; + reg [9:0] addrb_reg; + wire [15:0] dib_int; + wire [1:0] dipb_int; + wire enb_int, clkb_int, web_int, ssrb_int; + reg display_flag, output_flag; + reg enb_reg, web_reg, ssrb_reg; + + time time_clka, time_clkb; + time time_clka_clkb; + time time_clkb_clka; + + reg setup_all_a_b; + reg setup_all_b_a; + reg setup_zero; + reg setup_rf_a_b; + reg setup_rf_b_a; + reg [1:0] data_collision, data_collision_a_b, data_collision_b_a; + reg memory_collision, memory_collision_a_b, memory_collision_b_a; + reg change_clka; + reg change_clkb; + + wire [14:0] data_addra_int; + wire [14:0] data_addra_reg; + wire [14:0] data_addrb_int; + wire [14:0] data_addrb_reg; + + wire dia_enable = ena_int && wea_int; + wire dib_enable = enb_int && web_int; + + tri0 GSR = glbl.GSR; + wire gsr_int; + + buf b_gsr (gsr_int, GSR); + + buf b_doa [3:0] (DOA, doa_out); + buf b_addra [11:0] (addra_int, ADDRA); + buf b_dia [3:0] (dia_int, DIA); + buf b_ena (ena_int, ENA); + buf b_clka (clka_int, CLKA); + buf b_ssra (ssra_int, SSRA); + buf b_wea (wea_int, WEA); + + buf b_dob [15:0] (DOB, dob_out); + buf b_dopb [1:0] (DOPB, dopb_out); + buf b_addrb [9:0] (addrb_int, ADDRB); + buf b_dib [15:0] (dib_int, DIB); + buf b_dipb [1:0] (dipb_int, DIPB); + buf b_enb (enb_int, ENB); + buf b_clkb (clkb_int, CLKB); + buf b_ssrb (ssrb_int, SSRB); + buf b_web (web_int, WEB); + + + always @(gsr_int) + if (gsr_int) begin + assign {doa_out} = INIT_A; + assign {dopb_out, dob_out} = INIT_B; + end + else begin + deassign doa_out; + deassign dob_out; + deassign dopb_out; + end + + + initial begin + + for (count = 0; count < 16; count = count + 1) begin + mem[count] = INIT_00[(count * 16) +: 16]; + mem[16 * 1 + count] = INIT_01[(count * 16) +: 16]; + mem[16 * 2 + count] = INIT_02[(count * 16) +: 16]; + mem[16 * 3 + count] = INIT_03[(count * 16) +: 16]; + mem[16 * 4 + count] = INIT_04[(count * 16) +: 16]; + mem[16 * 5 + count] = INIT_05[(count * 16) +: 16]; + mem[16 * 6 + count] = INIT_06[(count * 16) +: 16]; + mem[16 * 7 + count] = INIT_07[(count * 16) +: 16]; + mem[16 * 8 + count] = INIT_08[(count * 16) +: 16]; + mem[16 * 9 + count] = INIT_09[(count * 16) +: 16]; + mem[16 * 10 + count] = INIT_0A[(count * 16) +: 16]; + mem[16 * 11 + count] = INIT_0B[(count * 16) +: 16]; + mem[16 * 12 + count] = INIT_0C[(count * 16) +: 16]; + mem[16 * 13 + count] = INIT_0D[(count * 16) +: 16]; + mem[16 * 14 + count] = INIT_0E[(count * 16) +: 16]; + mem[16 * 15 + count] = INIT_0F[(count * 16) +: 16]; + mem[16 * 16 + count] = INIT_10[(count * 16) +: 16]; + mem[16 * 17 + count] = INIT_11[(count * 16) +: 16]; + mem[16 * 18 + count] = INIT_12[(count * 16) +: 16]; + mem[16 * 19 + count] = INIT_13[(count * 16) +: 16]; + mem[16 * 20 + count] = INIT_14[(count * 16) +: 16]; + mem[16 * 21 + count] = INIT_15[(count * 16) +: 16]; + mem[16 * 22 + count] = INIT_16[(count * 16) +: 16]; + mem[16 * 23 + count] = INIT_17[(count * 16) +: 16]; + mem[16 * 24 + count] = INIT_18[(count * 16) +: 16]; + mem[16 * 25 + count] = INIT_19[(count * 16) +: 16]; + mem[16 * 26 + count] = INIT_1A[(count * 16) +: 16]; + mem[16 * 27 + count] = INIT_1B[(count * 16) +: 16]; + mem[16 * 28 + count] = INIT_1C[(count * 16) +: 16]; + mem[16 * 29 + count] = INIT_1D[(count * 16) +: 16]; + mem[16 * 30 + count] = INIT_1E[(count * 16) +: 16]; + mem[16 * 31 + count] = INIT_1F[(count * 16) +: 16]; + mem[16 * 32 + count] = INIT_20[(count * 16) +: 16]; + mem[16 * 33 + count] = INIT_21[(count * 16) +: 16]; + mem[16 * 34 + count] = INIT_22[(count * 16) +: 16]; + mem[16 * 35 + count] = INIT_23[(count * 16) +: 16]; + mem[16 * 36 + count] = INIT_24[(count * 16) +: 16]; + mem[16 * 37 + count] = INIT_25[(count * 16) +: 16]; + mem[16 * 38 + count] = INIT_26[(count * 16) +: 16]; + mem[16 * 39 + count] = INIT_27[(count * 16) +: 16]; + mem[16 * 40 + count] = INIT_28[(count * 16) +: 16]; + mem[16 * 41 + count] = INIT_29[(count * 16) +: 16]; + mem[16 * 42 + count] = INIT_2A[(count * 16) +: 16]; + mem[16 * 43 + count] = INIT_2B[(count * 16) +: 16]; + mem[16 * 44 + count] = INIT_2C[(count * 16) +: 16]; + mem[16 * 45 + count] = INIT_2D[(count * 16) +: 16]; + mem[16 * 46 + count] = INIT_2E[(count * 16) +: 16]; + mem[16 * 47 + count] = INIT_2F[(count * 16) +: 16]; + mem[16 * 48 + count] = INIT_30[(count * 16) +: 16]; + mem[16 * 49 + count] = INIT_31[(count * 16) +: 16]; + mem[16 * 50 + count] = INIT_32[(count * 16) +: 16]; + mem[16 * 51 + count] = INIT_33[(count * 16) +: 16]; + mem[16 * 52 + count] = INIT_34[(count * 16) +: 16]; + mem[16 * 53 + count] = INIT_35[(count * 16) +: 16]; + mem[16 * 54 + count] = INIT_36[(count * 16) +: 16]; + mem[16 * 55 + count] = INIT_37[(count * 16) +: 16]; + mem[16 * 56 + count] = INIT_38[(count * 16) +: 16]; + mem[16 * 57 + count] = INIT_39[(count * 16) +: 16]; + mem[16 * 58 + count] = INIT_3A[(count * 16) +: 16]; + mem[16 * 59 + count] = INIT_3B[(count * 16) +: 16]; + mem[16 * 60 + count] = INIT_3C[(count * 16) +: 16]; + mem[16 * 61 + count] = INIT_3D[(count * 16) +: 16]; + mem[16 * 62 + count] = INIT_3E[(count * 16) +: 16]; + mem[16 * 63 + count] = INIT_3F[(count * 16) +: 16]; + end + +// initiate parity start + for (countp = 0; countp < 128; countp = countp + 1) begin + memp[countp] = INITP_00[(countp * 2) +: 2]; + memp[128 * 1 + countp] = INITP_01[(countp * 2) +: 2]; + memp[128 * 2 + countp] = INITP_02[(countp * 2) +: 2]; + memp[128 * 3 + countp] = INITP_03[(countp * 2) +: 2]; + memp[128 * 4 + countp] = INITP_04[(countp * 2) +: 2]; + memp[128 * 5 + countp] = INITP_05[(countp * 2) +: 2]; + memp[128 * 6 + countp] = INITP_06[(countp * 2) +: 2]; + memp[128 * 7 + countp] = INITP_07[(countp * 2) +: 2]; + end +// initiate parity end + + change_clka <= 0; + change_clkb <= 0; + data_collision <= 0; + data_collision_a_b <= 0; + data_collision_b_a <= 0; + memory_collision <= 0; + memory_collision_a_b <= 0; + memory_collision_b_a <= 0; + setup_all_a_b <= 0; + setup_all_b_a <= 0; + setup_zero <= 0; + setup_rf_a_b <= 0; + setup_rf_b_a <= 0; + end + + assign data_addra_int = addra_int * 4; + assign data_addra_reg = addra_reg * 4; + assign data_addrb_int = addrb_int * 16; + assign data_addrb_reg = addrb_reg * 16; + + + initial begin + + display_flag = 1; + output_flag = 1; + + case (SIM_COLLISION_CHECK) + + "NONE" : begin + output_flag = 0; + display_flag = 0; + end + "WARNING_ONLY" : output_flag = 0; + "GENERATE_X_ONLY" : display_flag = 0; + "ALL" : ; + + default : begin + $display("Attribute Syntax Error : The Attribute SIM_COLLISION_CHECK on RAMB16_S4_S18 instance %m is set to %s. Legal values for this attribute are ALL, NONE, WARNING_ONLY or GENERATE_X_ONLY.", SIM_COLLISION_CHECK); + $finish; + end + + endcase // case(SIM_COLLISION_CHECK) + + end // initial begin + + + always @(posedge clka_int) begin + if ((output_flag || display_flag)) begin + time_clka = $time; + #0 time_clkb_clka = time_clka - time_clkb; + change_clka = ~change_clka; + end + end + + always @(posedge clkb_int) begin + if ((output_flag || display_flag)) begin + time_clkb = $time; + #0 time_clka_clkb = time_clkb - time_clka; + change_clkb = ~change_clkb; + end + end + + always @(change_clkb) begin + if ((0 < time_clka_clkb) && (time_clka_clkb < SETUP_ALL)) + setup_all_a_b = 1; + if ((0 < time_clka_clkb) && (time_clka_clkb < SETUP_READ_FIRST)) + setup_rf_a_b = 1; + end + + always @(change_clka) begin + if ((0 < time_clkb_clka) && (time_clkb_clka < SETUP_ALL)) + setup_all_b_a = 1; + if ((0 < time_clkb_clka) && (time_clkb_clka < SETUP_READ_FIRST)) + setup_rf_b_a = 1; + end + + always @(change_clkb or change_clka) begin + if ((time_clkb_clka == 0) && (time_clka_clkb == 0)) + setup_zero = 1; + end + + always @(posedge setup_zero) begin + if ((ena_int == 1) && (wea_int == 1) && + (enb_int == 1) && (web_int == 1) && + (data_addra_int[14:4] == data_addrb_int[14:4])) + memory_collision <= 1; + end + + always @(posedge setup_all_a_b or posedge setup_rf_a_b) begin + if ((ena_reg == 1) && (wea_reg == 1) && + (enb_int == 1) && (web_int == 1) && + (data_addra_reg[14:4] == data_addrb_int[14:4])) + memory_collision_a_b <= 1; + end + + always @(posedge setup_all_b_a or posedge setup_rf_b_a) begin + if ((ena_int == 1) && (wea_int == 1) && + (enb_reg == 1) && (web_reg == 1) && + (data_addra_int[14:4] == data_addrb_reg[14:4])) + memory_collision_b_a <= 1; + end + + always @(posedge setup_all_a_b) begin + if (data_addra_reg[14:4] == data_addrb_int[14:4]) begin + if ((ena_reg == 1) && (enb_int == 1)) begin + case ({wr_mode_a, wr_mode_b, wea_reg, web_int}) + 6'b000011 : begin data_collision_a_b <= 2'b11; display_wa_wb; end + 6'b000111 : begin data_collision_a_b <= 2'b11; display_wa_wb; end + 6'b001011 : begin data_collision_a_b <= 2'b10; display_wa_wb; end +// 6'b010011 : begin data_collision_a_b <= 2'b00; display_wa_wb; end +// 6'b010111 : begin data_collision_a_b <= 2'b00; display_wa_wb; end +// 6'b011011 : begin data_collision_a_b <= 2'b00; display_wa_wb; end + 6'b100011 : begin data_collision_a_b <= 2'b01; display_wa_wb; end + 6'b100111 : begin data_collision_a_b <= 2'b01; display_wa_wb; end + 6'b101011 : begin display_wa_wb; end + 6'b000001 : begin data_collision_a_b <= 2'b10; display_ra_wb; end +// 6'b000101 : begin data_collision_a_b <= 2'b00; display_ra_wb; end + 6'b001001 : begin data_collision_a_b <= 2'b10; display_ra_wb; end + 6'b010001 : begin data_collision_a_b <= 2'b10; display_ra_wb; end +// 6'b010101 : begin data_collision_a_b <= 2'b00; display_ra_wb; end + 6'b011001 : begin data_collision_a_b <= 2'b10; display_ra_wb; end + 6'b100001 : begin data_collision_a_b <= 2'b10; display_ra_wb; end +// 6'b100101 : begin data_collision_a_b <= 2'b00; display_ra_wb; end + 6'b101001 : begin data_collision_a_b <= 2'b10; display_ra_wb; end + 6'b000010 : begin data_collision_a_b <= 2'b01; display_wa_rb; end + 6'b000110 : begin data_collision_a_b <= 2'b01; display_wa_rb; end + 6'b001010 : begin data_collision_a_b <= 2'b01; display_wa_rb; end +// 6'b010010 : begin data_collision_a_b <= 2'b00; display_wa_rb; end +// 6'b010110 : begin data_collision_a_b <= 2'b00; display_wa_rb; end +// 6'b011010 : begin data_collision_a_b <= 2'b00; display_wa_rb; end + 6'b100010 : begin data_collision_a_b <= 2'b01; display_wa_rb; end + 6'b100110 : begin data_collision_a_b <= 2'b01; display_wa_rb; end + 6'b101010 : begin data_collision_a_b <= 2'b01; display_wa_rb; end + endcase + end + end + setup_all_a_b <= 0; + end + + + always @(posedge setup_all_b_a) begin + if (data_addra_int[14:4] == data_addrb_reg[14:4]) begin + if ((ena_int == 1) && (enb_reg == 1)) begin + case ({wr_mode_a, wr_mode_b, wea_int, web_reg}) + 6'b000011 : begin data_collision_b_a <= 2'b11; display_wa_wb; end +// 6'b000111 : begin data_collision_b_a <= 2'b00; display_wa_wb; end + 6'b001011 : begin data_collision_b_a <= 2'b10; display_wa_wb; end + 6'b010011 : begin data_collision_b_a <= 2'b11; display_wa_wb; end +// 6'b010111 : begin data_collision_b_a <= 2'b00; display_wa_wb; end + 6'b011011 : begin data_collision_b_a <= 2'b10; display_wa_wb; end + 6'b100011 : begin data_collision_b_a <= 2'b01; display_wa_wb; end + 6'b100111 : begin data_collision_b_a <= 2'b01; display_wa_wb; end + 6'b101011 : begin display_wa_wb; end + 6'b000001 : begin data_collision_b_a <= 2'b10; display_ra_wb; end + 6'b000101 : begin data_collision_b_a <= 2'b10; display_ra_wb; end + 6'b001001 : begin data_collision_b_a <= 2'b10; display_ra_wb; end + 6'b010001 : begin data_collision_b_a <= 2'b10; display_ra_wb; end + 6'b010101 : begin data_collision_b_a <= 2'b10; display_ra_wb; end + 6'b011001 : begin data_collision_b_a <= 2'b10; display_ra_wb; end + 6'b100001 : begin data_collision_b_a <= 2'b10; display_ra_wb; end + 6'b100101 : begin data_collision_b_a <= 2'b10; display_ra_wb; end + 6'b101001 : begin data_collision_b_a <= 2'b10; display_ra_wb; end + 6'b000010 : begin data_collision_b_a <= 2'b01; display_wa_rb; end + 6'b000110 : begin data_collision_b_a <= 2'b01; display_wa_rb; end + 6'b001010 : begin data_collision_b_a <= 2'b01; display_wa_rb; end +// 6'b010010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end +// 6'b010110 : begin data_collision_b_a <= 2'b00; display_wa_rb; end +// 6'b011010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end + 6'b100010 : begin data_collision_b_a <= 2'b01; display_wa_rb; end + 6'b100110 : begin data_collision_b_a <= 2'b01; display_wa_rb; end + 6'b101010 : begin data_collision_b_a <= 2'b01; display_wa_rb; end + endcase + end + end + setup_all_b_a <= 0; + end + + + always @(posedge setup_zero) begin + if (data_addra_int[14:4] == data_addrb_int[14:4]) begin + if ((ena_int == 1) && (enb_int == 1)) begin + case ({wr_mode_a, wr_mode_b, wea_int, web_int}) + 6'b000011 : begin data_collision <= 2'b11; display_wa_wb; end + 6'b000111 : begin data_collision <= 2'b11; display_wa_wb; end + 6'b001011 : begin data_collision <= 2'b10; display_wa_wb; end + 6'b010011 : begin data_collision <= 2'b11; display_wa_wb; end + 6'b010111 : begin data_collision <= 2'b11; display_wa_wb; end + 6'b011011 : begin data_collision <= 2'b10; display_wa_wb; end + 6'b100011 : begin data_collision <= 2'b01; display_wa_wb; end + 6'b100111 : begin data_collision <= 2'b01; display_wa_wb; end + 6'b101011 : begin display_wa_wb; end + 6'b000001 : begin data_collision <= 2'b10; display_ra_wb; end +// 6'b000101 : begin data_collision <= 2'b00; display_ra_wb; end + 6'b001001 : begin data_collision <= 2'b10; display_ra_wb; end + 6'b010001 : begin data_collision <= 2'b10; display_ra_wb; end +// 6'b010101 : begin data_collision <= 2'b00; display_ra_wb; end + 6'b011001 : begin data_collision <= 2'b10; display_ra_wb; end + 6'b100001 : begin data_collision <= 2'b10; display_ra_wb; end +// 6'b100101 : begin data_collision <= 2'b00; display_ra_wb; end + 6'b101001 : begin data_collision <= 2'b10; display_ra_wb; end + 6'b000010 : begin data_collision <= 2'b01; display_wa_rb; end + 6'b000110 : begin data_collision <= 2'b01; display_wa_rb; end + 6'b001010 : begin data_collision <= 2'b01; display_wa_rb; end +// 6'b010010 : begin data_collision <= 2'b00; display_wa_rb; end +// 6'b010110 : begin data_collision <= 2'b00; display_wa_rb; end +// 6'b011010 : begin data_collision <= 2'b00; display_wa_rb; end + 6'b100010 : begin data_collision <= 2'b01; display_wa_rb; end + 6'b100110 : begin data_collision <= 2'b01; display_wa_rb; end + 6'b101010 : begin data_collision <= 2'b01; display_wa_rb; end + endcase + end + end + setup_zero <= 0; + end + + task display_ra_wb; + begin + if (display_flag) + $display("Memory Collision Error on RAMB16_S4_S18:%m at simulation time %.3f ns\nA read was performed on address %h (hex) of Port A while a write was requested to the same address on Port B. The write will be successful however the read value on Port A is unknown until the next CLKA cycle.", $time/1000.0, addra_int); + end + endtask + + task display_wa_rb; + begin + if (display_flag) + $display("Memory Collision Error on RAMB16_S4_S18:%m at simulation time %.3f ns\nA read was performed on address %h (hex) of Port B while a write was requested to the same address on Port A. The write will be successful however the read value on Port B is unknown until the next CLKB cycle.", $time/1000.0, addrb_int); + end + endtask + + task display_wa_wb; + begin + if (display_flag) + $display("Memory Collision Error on RAMB16_S4_S18:%m at simulation time %.3f ns\nA write was requested to the same address simultaneously at both Port A and Port B of the RAM. The contents written to the RAM at address location %h (hex) of Port A and address location %h (hex) of Port B are unknown.", $time/1000.0, addra_int, addrb_int); + end + endtask + + + always @(posedge setup_rf_a_b) begin + if (data_addra_reg[14:4] == data_addrb_int[14:4]) begin + if ((ena_reg == 1) && (enb_int == 1)) begin + case ({wr_mode_a, wr_mode_b, wea_reg, web_int}) +// 6'b000011 : begin data_collision_a_b <= 2'b00; display_wa_wb; end +// 6'b000111 : begin data_collision_a_b <= 2'b00; display_wa_wb; end +// 6'b001011 : begin data_collision_a_b <= 2'b00; display_wa_wb; end + 6'b010011 : begin data_collision_a_b <= 2'b11; display_wa_wb; end + 6'b010111 : begin data_collision_a_b <= 2'b11; display_wa_wb; end + 6'b011011 : begin data_collision_a_b <= 2'b10; display_wa_wb; end +// 6'b100011 : begin data_collision_a_b <= 2'b00; display_wa_wb; end +// 6'b100111 : begin data_collision_a_b <= 2'b00; display_wa_wb; end +// 6'b101011 : begin data_collision_a_b <= 2'b00; display_wa_wb; end +// 6'b000001 : begin data_collision_a_b <= 2'b00; display_ra_wb; end +// 6'b000101 : begin data_collision_a_b <= 2'b00; display_ra_wb; end +// 6'b001001 : begin data_collision_a_b <= 2'b00; display_ra_wb; end +// 6'b010001 : begin data_collision_a_b <= 2'b00; display_ra_wb; end +// 6'b010101 : begin data_collision_a_b <= 2'b00; display_ra_wb; end +// 6'b011001 : begin data_collision_a_b <= 2'b00; display_ra_wb; end +// 6'b100001 : begin data_collision_a_b <= 2'b00; display_ra_wb; end +// 6'b100101 : begin data_collision_a_b <= 2'b00; display_ra_wb; end +// 6'b101001 : begin data_collision_a_b <= 2'b00; display_ra_wb; end +// 6'b000010 : begin data_collision_a_b <= 2'b00; display_wa_rb; end +// 6'b000110 : begin data_collision_a_b <= 2'b00; display_wa_rb; end +// 6'b001010 : begin data_collision_a_b <= 2'b00; display_wa_rb; end + 6'b010010 : begin data_collision_a_b <= 2'b01; display_wa_rb; end + 6'b010110 : begin data_collision_a_b <= 2'b01; display_wa_rb; end + 6'b011010 : begin data_collision_a_b <= 2'b01; display_wa_rb; end +// 6'b100010 : begin data_collision_a_b <= 2'b00; display_wa_rb; end +// 6'b100110 : begin data_collision_a_b <= 2'b00; display_wa_rb; end +// 6'b101010 : begin data_collision_a_b <= 2'b00; display_wa_rb; end + endcase + end + end + setup_rf_a_b <= 0; + end + + + always @(posedge setup_rf_b_a) begin + if (data_addra_int[14:4] == data_addrb_reg[14:4]) begin + if ((ena_int == 1) && (enb_reg == 1)) begin + case ({wr_mode_a, wr_mode_b, wea_int, web_reg}) +// 6'b000011 : begin data_collision_b_a <= 2'b00; display_wa_wb; end + 6'b000111 : begin data_collision_b_a <= 2'b11; display_wa_wb; end +// 6'b001011 : begin data_collision_b_a <= 2'b00; display_wa_wb; end +// 6'b010011 : begin data_collision_b_a <= 2'b00; display_wa_wb; end + 6'b010111 : begin data_collision_b_a <= 2'b11; display_wa_wb; end +// 6'b011011 : begin data_collision_b_a <= 2'b00; display_wa_wb; end +// 6'b100011 : begin data_collision_b_a <= 2'b00; display_wa_wb; end + 6'b100111 : begin data_collision_b_a <= 2'b01; display_wa_wb; end +// 6'b101011 : begin data_collision_b_a <= 2'b00; display_wa_wb; end +// 6'b000001 : begin data_collision_b_a <= 2'b00; display_ra_wb; end + 6'b000101 : begin data_collision_b_a <= 2'b10; display_ra_wb; end +// 6'b001001 : begin data_collision_b_a <= 2'b00; display_ra_wb; end +// 6'b010001 : begin data_collision_b_a <= 2'b00; display_ra_wb; end + 6'b010101 : begin data_collision_b_a <= 2'b10; display_ra_wb; end +// 6'b011001 : begin data_collision_b_a <= 2'b00; display_ra_wb; end +// 6'b100001 : begin data_collision_b_a <= 2'b00; display_ra_wb; end + 6'b100101 : begin data_collision_b_a <= 2'b10; display_ra_wb; end +// 6'b101001 : begin data_collision_b_a <= 2'b00; display_ra_wb; end +// 6'b000010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end +// 6'b000110 : begin data_collision_b_a <= 2'b00; display_wa_rb; end +// 6'b001010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end +// 6'b010010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end +// 6'b010110 : begin data_collision_b_a <= 2'b00; display_wa_rb; end +// 6'b011010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end +// 6'b100010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end +// 6'b100110 : begin data_collision_b_a <= 2'b00; display_wa_rb; end +// 6'b101010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end + endcase + end + end + setup_rf_b_a <= 0; + end + + + always @(posedge clka_int) begin + if ((output_flag || display_flag)) begin + addra_reg <= addra_int; + ena_reg <= ena_int; + ssra_reg <= ssra_int; + wea_reg <= wea_int; + end + end + + always @(posedge clkb_int) begin + if ((output_flag || display_flag)) begin + addrb_reg <= addrb_int; + enb_reg <= enb_int; + ssrb_reg <= ssrb_int; + web_reg <= web_int; + end + end + + + // Data + always @(posedge memory_collision) begin + if ((output_flag || display_flag)) begin + mem[addra_int[11:2]][addra_int[1:0] * 4 +: 4] <= 4'bx; + memory_collision <= 0; + end + + end + + always @(posedge memory_collision_a_b) begin + if ((output_flag || display_flag)) begin + mem[addra_reg[11:2]][addra_reg[1:0] * 4 +: 4] <= 4'bx; + memory_collision_a_b <= 0; + end + end + + always @(posedge memory_collision_b_a) begin + if ((output_flag || display_flag)) begin + mem[addra_int[11:2]][addra_int[1:0] * 4 +: 4] <= 4'bx; + memory_collision_b_a <= 0; + end + end + + always @(posedge data_collision[1]) begin + if (ssra_int == 0 && output_flag) begin + doa_out <= #100 4'bX; + end + data_collision[1] <= 0; + end + + always @(posedge data_collision[0]) begin + if (ssrb_int == 0 && output_flag) begin + dob_out[addra_int[1:0] * 4 +: 4] <= #100 4'bX; + end + data_collision[0] <= 0; + end + + always @(posedge data_collision_a_b[1]) begin + if (ssra_reg == 0 && output_flag) begin + doa_out <= #100 4'bX; + end + data_collision_a_b[1] <= 0; + end + + always @(posedge data_collision_a_b[0]) begin + if (ssrb_int == 0 && output_flag) begin + dob_out[addra_reg[1:0] * 4 +: 4] <= #100 4'bX; + end + data_collision_a_b[0] <= 0; + end + + always @(posedge data_collision_b_a[1]) begin + if (ssra_int == 0 && output_flag) begin + doa_out <= #100 4'bX; + end + data_collision_b_a[1] <= 0; + end + + always @(posedge data_collision_b_a[0]) begin + if (ssrb_reg == 0 && output_flag) begin + dob_out[addra_int[1:0] * 4 +: 4] <= #100 4'bX; + end + data_collision_b_a[0] <= 0; + end + + + initial begin + case (WRITE_MODE_A) + "WRITE_FIRST" : wr_mode_a <= 2'b00; + "READ_FIRST" : wr_mode_a <= 2'b01; + "NO_CHANGE" : wr_mode_a <= 2'b10; + default : begin + $display("Attribute Syntax Error : The Attribute WRITE_MODE_A on RAMB16_S4_S18 instance %m is set to %s. Legal values for this attribute are WRITE_FIRST, READ_FIRST or NO_CHANGE.", WRITE_MODE_A); + $finish; + end + endcase + end + + initial begin + case (WRITE_MODE_B) + "WRITE_FIRST" : wr_mode_b <= 2'b00; + "READ_FIRST" : wr_mode_b <= 2'b01; + "NO_CHANGE" : wr_mode_b <= 2'b10; + default : begin + $display("Attribute Syntax Error : The Attribute WRITE_MODE_B on RAMB16_S4_S18 instance %m is set to %s. Legal values for this attribute are WRITE_FIRST, READ_FIRST or NO_CHANGE.", WRITE_MODE_B); + $finish; + end + endcase + end + + + // Port A + always @(posedge clka_int) begin + + if (ena_int == 1'b1) begin + + if (ssra_int == 1'b1) begin + {doa_out} <= #100 SRVAL_A; + end + else begin + if (wea_int == 1'b1) begin + if (wr_mode_a == 2'b00) begin + doa_out <= #100 dia_int; + end + else if (wr_mode_a == 2'b01) begin + + doa_out <= #100 mem[addra_int[11:2]][addra_int[1:0] * 4 +: 4]; + + end + end + else begin + + doa_out <= #100 mem[addra_int[11:2]][addra_int[1:0] * 4 +: 4]; + + end + end + + // memory + if (wea_int == 1'b1) begin + mem[addra_int[11:2]][addra_int[1:0] * 4 +: 4] <= dia_int; + end + + end + end + + + // Port B + always @(posedge clkb_int) begin + + if (enb_int == 1'b1) begin + + if (ssrb_int == 1'b1) begin + {dopb_out, dob_out} <= #100 SRVAL_B; + end + else begin + if (web_int == 1'b1) begin + if (wr_mode_b == 2'b00) begin + dob_out <= #100 dib_int; + dopb_out <= #100 dipb_int; + end + else if (wr_mode_b == 2'b01) begin + dob_out <= #100 mem[addrb_int]; + dopb_out <= #100 memp[addrb_int]; + end + end + else begin + dob_out <= #100 mem[addrb_int]; + dopb_out <= #100 memp[addrb_int]; + end + end + + // memory + if (web_int == 1'b1) begin + mem[addrb_int] <= dib_int; + memp[addrb_int] <= dipb_int; + end + + end + end + + +endmodule + +`endif diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/RAMB16_S4_S36.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/RAMB16_S4_S36.v new file mode 100644 index 0000000..8a4e488 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/RAMB16_S4_S36.v @@ -0,0 +1,1848 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/RAMB16_S4_S36.v,v 1.10 2007/02/22 01:58:06 wloo Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2005 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / 16K-Bit Data and 2K-Bit Parity Dual Port Block RAM +// /___/ /\ Filename : RAMB16_S4_S36.v +// \ \ / \ Timestamp : Thu Mar 10 16:43:37 PST 2005 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// End Revision + +`ifdef legacy_model + +`timescale 1 ps / 1 ps + +module RAMB16_S4_S36 (DOA, DOB, DOPB, ADDRA, ADDRB, CLKA, CLKB, DIA, DIB, DIPB, ENA, ENB, SSRA, SSRB, WEA, WEB); + + parameter INIT_A = 4'h0; + parameter INIT_B = 36'h0; + parameter SRVAL_A = 4'h0; + parameter SRVAL_B = 36'h0; + parameter WRITE_MODE_A = "WRITE_FIRST"; + parameter WRITE_MODE_B = "WRITE_FIRST"; + parameter SIM_COLLISION_CHECK = "ALL"; + localparam SETUP_ALL = 1000; + localparam SETUP_READ_FIRST = 3000; + + parameter INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + + output [3:0] DOA; + reg [3:0] doa_out; + wire doa_out0, doa_out1, doa_out2, doa_out3; + + input [11:0] ADDRA; + input [3:0] DIA; + input ENA, CLKA, WEA, SSRA; + + output [31:0] DOB; + output [3:0] DOPB; + reg [31:0] dob_out; + reg [3:0] dopb_out; + wire dob_out0, dob_out1, dob_out2, dob_out3, dob_out4, dob_out5, dob_out6, dob_out7, dob_out8, dob_out9, dob_out10, dob_out11, dob_out12, dob_out13, dob_out14, dob_out15, dob_out16, dob_out17, dob_out18, dob_out19, dob_out20, dob_out21, dob_out22, dob_out23, dob_out24, dob_out25, dob_out26, dob_out27, dob_out28, dob_out29, dob_out30, dob_out31; + wire dopb0_out, dopb1_out, dopb2_out, dopb3_out; + + input [8:0] ADDRB; + input [31:0] DIB; + input [3:0] DIPB; + input ENB, CLKB, WEB, SSRB; + + reg [18431:0] mem; + reg [8:0] count; + reg [1:0] wr_mode_a, wr_mode_b; + + reg [5:0] dmi, dbi; + reg [5:0] pmi, pbi; + + wire [11:0] addra_int; + reg [11:0] addra_reg; + wire [3:0] dia_int; + wire ena_int, clka_int, wea_int, ssra_int; + reg ena_reg, wea_reg, ssra_reg; + wire [8:0] addrb_int; + reg [8:0] addrb_reg; + wire [31:0] dib_int; + wire [3:0] dipb_int; + wire enb_int, clkb_int, web_int, ssrb_int; + reg display_flag; + reg enb_reg, web_reg, ssrb_reg; + + time time_clka, time_clkb; + time time_clka_clkb; + time time_clkb_clka; + + reg setup_all_a_b; + reg setup_all_b_a; + reg setup_zero; + reg setup_rf_a_b; + reg setup_rf_b_a; + reg [1:0] data_collision, data_collision_a_b, data_collision_b_a; + reg memory_collision, memory_collision_a_b, memory_collision_b_a; + reg address_collision, address_collision_a_b, address_collision_b_a; + reg change_clka; + reg change_clkb; + + wire [14:0] data_addra_int; + wire [14:0] data_addra_reg; + wire [14:0] data_addrb_int; + wire [14:0] data_addrb_reg; + wire [15:0] parity_addra_int; + wire [15:0] parity_addra_reg; + wire [15:0] parity_addrb_int; + wire [15:0] parity_addrb_reg; + + tri0 GSR = glbl.GSR; + + always @(GSR) + if (GSR) begin + assign doa_out = INIT_A[3:0]; + assign dob_out = INIT_B[31:0]; + assign dopb_out = INIT_B[35:32]; + end + else begin + deassign doa_out; + deassign dob_out; + deassign dopb_out; + end + + buf b_doa_out0 (doa_out0, doa_out[0]); + buf b_doa_out1 (doa_out1, doa_out[1]); + buf b_doa_out2 (doa_out2, doa_out[2]); + buf b_doa_out3 (doa_out3, doa_out[3]); + buf b_dob_out0 (dob_out0, dob_out[0]); + buf b_dob_out1 (dob_out1, dob_out[1]); + buf b_dob_out2 (dob_out2, dob_out[2]); + buf b_dob_out3 (dob_out3, dob_out[3]); + buf b_dob_out4 (dob_out4, dob_out[4]); + buf b_dob_out5 (dob_out5, dob_out[5]); + buf b_dob_out6 (dob_out6, dob_out[6]); + buf b_dob_out7 (dob_out7, dob_out[7]); + buf b_dob_out8 (dob_out8, dob_out[8]); + buf b_dob_out9 (dob_out9, dob_out[9]); + buf b_dob_out10 (dob_out10, dob_out[10]); + buf b_dob_out11 (dob_out11, dob_out[11]); + buf b_dob_out12 (dob_out12, dob_out[12]); + buf b_dob_out13 (dob_out13, dob_out[13]); + buf b_dob_out14 (dob_out14, dob_out[14]); + buf b_dob_out15 (dob_out15, dob_out[15]); + buf b_dob_out16 (dob_out16, dob_out[16]); + buf b_dob_out17 (dob_out17, dob_out[17]); + buf b_dob_out18 (dob_out18, dob_out[18]); + buf b_dob_out19 (dob_out19, dob_out[19]); + buf b_dob_out20 (dob_out20, dob_out[20]); + buf b_dob_out21 (dob_out21, dob_out[21]); + buf b_dob_out22 (dob_out22, dob_out[22]); + buf b_dob_out23 (dob_out23, dob_out[23]); + buf b_dob_out24 (dob_out24, dob_out[24]); + buf b_dob_out25 (dob_out25, dob_out[25]); + buf b_dob_out26 (dob_out26, dob_out[26]); + buf b_dob_out27 (dob_out27, dob_out[27]); + buf b_dob_out28 (dob_out28, dob_out[28]); + buf b_dob_out29 (dob_out29, dob_out[29]); + buf b_dob_out30 (dob_out30, dob_out[30]); + buf b_dob_out31 (dob_out31, dob_out[31]); + buf b_dopb_out0 (dopb_out0, dopb_out[0]); + buf b_dopb_out1 (dopb_out1, dopb_out[1]); + buf b_dopb_out2 (dopb_out2, dopb_out[2]); + buf b_dopb_out3 (dopb_out3, dopb_out[3]); + + buf b_doa0 (DOA[0], doa_out0); + buf b_doa1 (DOA[1], doa_out1); + buf b_doa2 (DOA[2], doa_out2); + buf b_doa3 (DOA[3], doa_out3); + buf b_dob0 (DOB[0], dob_out0); + buf b_dob1 (DOB[1], dob_out1); + buf b_dob2 (DOB[2], dob_out2); + buf b_dob3 (DOB[3], dob_out3); + buf b_dob4 (DOB[4], dob_out4); + buf b_dob5 (DOB[5], dob_out5); + buf b_dob6 (DOB[6], dob_out6); + buf b_dob7 (DOB[7], dob_out7); + buf b_dob8 (DOB[8], dob_out8); + buf b_dob9 (DOB[9], dob_out9); + buf b_dob10 (DOB[10], dob_out10); + buf b_dob11 (DOB[11], dob_out11); + buf b_dob12 (DOB[12], dob_out12); + buf b_dob13 (DOB[13], dob_out13); + buf b_dob14 (DOB[14], dob_out14); + buf b_dob15 (DOB[15], dob_out15); + buf b_dob16 (DOB[16], dob_out16); + buf b_dob17 (DOB[17], dob_out17); + buf b_dob18 (DOB[18], dob_out18); + buf b_dob19 (DOB[19], dob_out19); + buf b_dob20 (DOB[20], dob_out20); + buf b_dob21 (DOB[21], dob_out21); + buf b_dob22 (DOB[22], dob_out22); + buf b_dob23 (DOB[23], dob_out23); + buf b_dob24 (DOB[24], dob_out24); + buf b_dob25 (DOB[25], dob_out25); + buf b_dob26 (DOB[26], dob_out26); + buf b_dob27 (DOB[27], dob_out27); + buf b_dob28 (DOB[28], dob_out28); + buf b_dob29 (DOB[29], dob_out29); + buf b_dob30 (DOB[30], dob_out30); + buf b_dob31 (DOB[31], dob_out31); + buf b_dopb0 (DOPB[0], dopb_out0); + buf b_dopb1 (DOPB[1], dopb_out1); + buf b_dopb2 (DOPB[2], dopb_out2); + buf b_dopb3 (DOPB[3], dopb_out3); + + buf b_addra_0 (addra_int[0], ADDRA[0]); + buf b_addra_1 (addra_int[1], ADDRA[1]); + buf b_addra_2 (addra_int[2], ADDRA[2]); + buf b_addra_3 (addra_int[3], ADDRA[3]); + buf b_addra_4 (addra_int[4], ADDRA[4]); + buf b_addra_5 (addra_int[5], ADDRA[5]); + buf b_addra_6 (addra_int[6], ADDRA[6]); + buf b_addra_7 (addra_int[7], ADDRA[7]); + buf b_addra_8 (addra_int[8], ADDRA[8]); + buf b_addra_9 (addra_int[9], ADDRA[9]); + buf b_addra_10 (addra_int[10], ADDRA[10]); + buf b_addra_11 (addra_int[11], ADDRA[11]); + buf b_dia_0 (dia_int[0], DIA[0]); + buf b_dia_1 (dia_int[1], DIA[1]); + buf b_dia_2 (dia_int[2], DIA[2]); + buf b_dia_3 (dia_int[3], DIA[3]); + buf b_ena (ena_int, ENA); + buf b_clka (clka_int, CLKA); + buf b_ssra (ssra_int, SSRA); + buf b_wea (wea_int, WEA); + buf b_addrb_0 (addrb_int[0], ADDRB[0]); + buf b_addrb_1 (addrb_int[1], ADDRB[1]); + buf b_addrb_2 (addrb_int[2], ADDRB[2]); + buf b_addrb_3 (addrb_int[3], ADDRB[3]); + buf b_addrb_4 (addrb_int[4], ADDRB[4]); + buf b_addrb_5 (addrb_int[5], ADDRB[5]); + buf b_addrb_6 (addrb_int[6], ADDRB[6]); + buf b_addrb_7 (addrb_int[7], ADDRB[7]); + buf b_addrb_8 (addrb_int[8], ADDRB[8]); + buf b_dib_0 (dib_int[0], DIB[0]); + buf b_dib_1 (dib_int[1], DIB[1]); + buf b_dib_2 (dib_int[2], DIB[2]); + buf b_dib_3 (dib_int[3], DIB[3]); + buf b_dib_4 (dib_int[4], DIB[4]); + buf b_dib_5 (dib_int[5], DIB[5]); + buf b_dib_6 (dib_int[6], DIB[6]); + buf b_dib_7 (dib_int[7], DIB[7]); + buf b_dib_8 (dib_int[8], DIB[8]); + buf b_dib_9 (dib_int[9], DIB[9]); + buf b_dib_10 (dib_int[10], DIB[10]); + buf b_dib_11 (dib_int[11], DIB[11]); + buf b_dib_12 (dib_int[12], DIB[12]); + buf b_dib_13 (dib_int[13], DIB[13]); + buf b_dib_14 (dib_int[14], DIB[14]); + buf b_dib_15 (dib_int[15], DIB[15]); + buf b_dib_16 (dib_int[16], DIB[16]); + buf b_dib_17 (dib_int[17], DIB[17]); + buf b_dib_18 (dib_int[18], DIB[18]); + buf b_dib_19 (dib_int[19], DIB[19]); + buf b_dib_20 (dib_int[20], DIB[20]); + buf b_dib_21 (dib_int[21], DIB[21]); + buf b_dib_22 (dib_int[22], DIB[22]); + buf b_dib_23 (dib_int[23], DIB[23]); + buf b_dib_24 (dib_int[24], DIB[24]); + buf b_dib_25 (dib_int[25], DIB[25]); + buf b_dib_26 (dib_int[26], DIB[26]); + buf b_dib_27 (dib_int[27], DIB[27]); + buf b_dib_28 (dib_int[28], DIB[28]); + buf b_dib_29 (dib_int[29], DIB[29]); + buf b_dib_30 (dib_int[30], DIB[30]); + buf b_dib_31 (dib_int[31], DIB[31]); + buf b_dipb_0 (dipb_int[0], DIPB[0]); + buf b_dipb_1 (dipb_int[1], DIPB[1]); + buf b_dipb_2 (dipb_int[2], DIPB[2]); + buf b_dipb_3 (dipb_int[3], DIPB[3]); + buf b_enb (enb_int, ENB); + buf b_clkb (clkb_int, CLKB); + buf b_ssrb (ssrb_int, SSRB); + buf b_web (web_int, WEB); + + initial begin + for (count = 0; count < 256; count = count + 1) begin + mem[count] <= INIT_00[count]; + mem[256 * 1 + count] <= INIT_01[count]; + mem[256 * 2 + count] <= INIT_02[count]; + mem[256 * 3 + count] <= INIT_03[count]; + mem[256 * 4 + count] <= INIT_04[count]; + mem[256 * 5 + count] <= INIT_05[count]; + mem[256 * 6 + count] <= INIT_06[count]; + mem[256 * 7 + count] <= INIT_07[count]; + mem[256 * 8 + count] <= INIT_08[count]; + mem[256 * 9 + count] <= INIT_09[count]; + mem[256 * 10 + count] <= INIT_0A[count]; + mem[256 * 11 + count] <= INIT_0B[count]; + mem[256 * 12 + count] <= INIT_0C[count]; + mem[256 * 13 + count] <= INIT_0D[count]; + mem[256 * 14 + count] <= INIT_0E[count]; + mem[256 * 15 + count] <= INIT_0F[count]; + mem[256 * 16 + count] <= INIT_10[count]; + mem[256 * 17 + count] <= INIT_11[count]; + mem[256 * 18 + count] <= INIT_12[count]; + mem[256 * 19 + count] <= INIT_13[count]; + mem[256 * 20 + count] <= INIT_14[count]; + mem[256 * 21 + count] <= INIT_15[count]; + mem[256 * 22 + count] <= INIT_16[count]; + mem[256 * 23 + count] <= INIT_17[count]; + mem[256 * 24 + count] <= INIT_18[count]; + mem[256 * 25 + count] <= INIT_19[count]; + mem[256 * 26 + count] <= INIT_1A[count]; + mem[256 * 27 + count] <= INIT_1B[count]; + mem[256 * 28 + count] <= INIT_1C[count]; + mem[256 * 29 + count] <= INIT_1D[count]; + mem[256 * 30 + count] <= INIT_1E[count]; + mem[256 * 31 + count] <= INIT_1F[count]; + mem[256 * 32 + count] <= INIT_20[count]; + mem[256 * 33 + count] <= INIT_21[count]; + mem[256 * 34 + count] <= INIT_22[count]; + mem[256 * 35 + count] <= INIT_23[count]; + mem[256 * 36 + count] <= INIT_24[count]; + mem[256 * 37 + count] <= INIT_25[count]; + mem[256 * 38 + count] <= INIT_26[count]; + mem[256 * 39 + count] <= INIT_27[count]; + mem[256 * 40 + count] <= INIT_28[count]; + mem[256 * 41 + count] <= INIT_29[count]; + mem[256 * 42 + count] <= INIT_2A[count]; + mem[256 * 43 + count] <= INIT_2B[count]; + mem[256 * 44 + count] <= INIT_2C[count]; + mem[256 * 45 + count] <= INIT_2D[count]; + mem[256 * 46 + count] <= INIT_2E[count]; + mem[256 * 47 + count] <= INIT_2F[count]; + mem[256 * 48 + count] <= INIT_30[count]; + mem[256 * 49 + count] <= INIT_31[count]; + mem[256 * 50 + count] <= INIT_32[count]; + mem[256 * 51 + count] <= INIT_33[count]; + mem[256 * 52 + count] <= INIT_34[count]; + mem[256 * 53 + count] <= INIT_35[count]; + mem[256 * 54 + count] <= INIT_36[count]; + mem[256 * 55 + count] <= INIT_37[count]; + mem[256 * 56 + count] <= INIT_38[count]; + mem[256 * 57 + count] <= INIT_39[count]; + mem[256 * 58 + count] <= INIT_3A[count]; + mem[256 * 59 + count] <= INIT_3B[count]; + mem[256 * 60 + count] <= INIT_3C[count]; + mem[256 * 61 + count] <= INIT_3D[count]; + mem[256 * 62 + count] <= INIT_3E[count]; + mem[256 * 63 + count] <= INIT_3F[count]; + mem[256 * 64 + count] <= INITP_00[count]; + mem[256 * 65 + count] <= INITP_01[count]; + mem[256 * 66 + count] <= INITP_02[count]; + mem[256 * 67 + count] <= INITP_03[count]; + mem[256 * 68 + count] <= INITP_04[count]; + mem[256 * 69 + count] <= INITP_05[count]; + mem[256 * 70 + count] <= INITP_06[count]; + mem[256 * 71 + count] <= INITP_07[count]; + end + address_collision <= 0; + address_collision_a_b <= 0; + address_collision_b_a <= 0; + change_clka <= 0; + change_clkb <= 0; + data_collision <= 0; + data_collision_a_b <= 0; + data_collision_b_a <= 0; + memory_collision <= 0; + memory_collision_a_b <= 0; + memory_collision_b_a <= 0; + setup_all_a_b <= 0; + setup_all_b_a <= 0; + setup_zero <= 0; + setup_rf_a_b <= 0; + setup_rf_b_a <= 0; + end + + assign data_addra_int = addra_int * 4; + assign data_addra_reg = addra_reg * 4; + assign data_addrb_int = addrb_int * 32; + assign data_addrb_reg = addrb_reg * 32; + assign parity_addrb_int = 16384 + addrb_int * 4; + assign parity_addrb_reg = 16384 + addrb_reg * 4; + + + initial begin + + display_flag = 1; + + case (SIM_COLLISION_CHECK) + + "NONE" : begin + assign setup_all_a_b = 1'b0; + assign setup_all_b_a = 1'b0; + assign setup_zero = 1'b0; + assign setup_rf_a_b = 1'b0; + assign setup_rf_b_a = 1'b0; + assign display_flag = 0; + end + "WARNING_ONLY" : begin + assign data_collision = 2'b00; + assign data_collision_a_b = 2'b00; + assign data_collision_b_a = 2'b00; + assign memory_collision = 1'b0; + assign memory_collision_a_b = 1'b0; + assign memory_collision_b_a = 1'b0; + end + "GENERATE_X_ONLY" : begin + assign display_flag = 0; + end + "ALL" : ; + default : begin + $display("Attribute Syntax Error : The Attribute SIM_COLLISION_CHECK on RAMB16_S4_S36 instance %m is set to %s. Legal values for this attribute are ALL, NONE, WARNING_ONLY or GENERATE_X_ONLY.", SIM_COLLISION_CHECK); + $finish; + end + + endcase // case(SIM_COLLISION_CHECK) + + end // initial begin + + + always @(posedge clka_int) begin + time_clka = $time; + #0 time_clkb_clka = time_clka - time_clkb; + change_clka = ~change_clka; + end + + always @(posedge clkb_int) begin + time_clkb = $time; + #0 time_clka_clkb = time_clkb - time_clka; + change_clkb = ~change_clkb; + end + + always @(change_clkb) begin + if ((0 < time_clka_clkb) && (time_clka_clkb < SETUP_ALL)) + setup_all_a_b = 1; + if ((0 < time_clka_clkb) && (time_clka_clkb < SETUP_READ_FIRST)) + setup_rf_a_b = 1; + end + + always @(change_clka) begin + if ((0 < time_clkb_clka) && (time_clkb_clka < SETUP_ALL)) + setup_all_b_a = 1; + if ((0 < time_clkb_clka) && (time_clkb_clka < SETUP_READ_FIRST)) + setup_rf_b_a = 1; + end + + always @(change_clkb or change_clka) begin + if ((time_clkb_clka == 0) && (time_clka_clkb == 0)) + setup_zero = 1; + end + + always @(posedge setup_zero) begin + if ((ena_int == 1) && (wea_int == 1) && + (enb_int == 1) && (web_int == 1) && + (data_addra_int[14:5] == data_addrb_int[14:5])) + memory_collision <= 1; + end + + always @(posedge setup_all_a_b or posedge setup_rf_a_b) begin + if ((ena_reg == 1) && (wea_reg == 1) && + (enb_int == 1) && (web_int == 1) && + (data_addra_reg[14:5] == data_addrb_int[14:5])) + memory_collision_a_b <= 1; + end + + always @(posedge setup_all_b_a or posedge setup_rf_b_a) begin + if ((ena_int == 1) && (wea_int == 1) && + (enb_reg == 1) && (web_reg == 1) && + (data_addra_int[14:5] == data_addrb_reg[14:5])) + memory_collision_b_a <= 1; + end + + always @(posedge setup_all_a_b) begin + if (data_addra_reg[14:5] == data_addrb_int[14:5]) begin + if ((ena_reg == 1) && (enb_int == 1)) begin + case ({wr_mode_a, wr_mode_b, wea_reg, web_int}) + 6'b000011 : begin data_collision_a_b <= 2'b11; display_wa_wb; end + 6'b000111 : begin data_collision_a_b <= 2'b11; display_wa_wb; end + 6'b001011 : begin data_collision_a_b <= 2'b10; display_wa_wb; end +// 6'b010011 : begin data_collision_a_b <= 2'b00; display_wa_wb; end +// 6'b010111 : begin data_collision_a_b <= 2'b00; display_wa_wb; end +// 6'b011011 : begin data_collision_a_b <= 2'b00; display_wa_wb; end + 6'b100011 : begin data_collision_a_b <= 2'b01; display_wa_wb; end + 6'b100111 : begin data_collision_a_b <= 2'b01; display_wa_wb; end + 6'b101011 : begin display_wa_wb; end + 6'b000001 : begin data_collision_a_b <= 2'b10; display_ra_wb; end +// 6'b000101 : begin data_collision_a_b <= 2'b00; display_ra_wb; end + 6'b001001 : begin data_collision_a_b <= 2'b10; display_ra_wb; end + 6'b010001 : begin data_collision_a_b <= 2'b10; display_ra_wb; end +// 6'b010101 : begin data_collision_a_b <= 2'b00; display_ra_wb; end + 6'b011001 : begin data_collision_a_b <= 2'b10; display_ra_wb; end + 6'b100001 : begin data_collision_a_b <= 2'b10; display_ra_wb; end +// 6'b100101 : begin data_collision_a_b <= 2'b00; display_ra_wb; end + 6'b101001 : begin data_collision_a_b <= 2'b10; display_ra_wb; end + 6'b000010 : begin data_collision_a_b <= 2'b01; display_wa_rb; end + 6'b000110 : begin data_collision_a_b <= 2'b01; display_wa_rb; end + 6'b001010 : begin data_collision_a_b <= 2'b01; display_wa_rb; end +// 6'b010010 : begin data_collision_a_b <= 2'b00; display_wa_rb; end +// 6'b010110 : begin data_collision_a_b <= 2'b00; display_wa_rb; end +// 6'b011010 : begin data_collision_a_b <= 2'b00; display_wa_rb; end + 6'b100010 : begin data_collision_a_b <= 2'b01; display_wa_rb; end + 6'b100110 : begin data_collision_a_b <= 2'b01; display_wa_rb; end + 6'b101010 : begin data_collision_a_b <= 2'b01; display_wa_rb; end + endcase + end + end + setup_all_a_b <= 0; + end + + + always @(posedge setup_all_b_a) begin + if (data_addra_int[14:5] == data_addrb_reg[14:5]) begin + if ((ena_int == 1) && (enb_reg == 1)) begin + case ({wr_mode_a, wr_mode_b, wea_int, web_reg}) + 6'b000011 : begin data_collision_b_a <= 2'b11; display_wa_wb; end +// 6'b000111 : begin data_collision_b_a <= 2'b00; display_wa_wb; end + 6'b001011 : begin data_collision_b_a <= 2'b10; display_wa_wb; end + 6'b010011 : begin data_collision_b_a <= 2'b11; display_wa_wb; end +// 6'b010111 : begin data_collision_b_a <= 2'b00; display_wa_wb; end + 6'b011011 : begin data_collision_b_a <= 2'b10; display_wa_wb; end + 6'b100011 : begin data_collision_b_a <= 2'b01; display_wa_wb; end + 6'b100111 : begin data_collision_b_a <= 2'b01; display_wa_wb; end + 6'b101011 : begin display_wa_wb; end + 6'b000001 : begin data_collision_b_a <= 2'b10; display_ra_wb; end + 6'b000101 : begin data_collision_b_a <= 2'b10; display_ra_wb; end + 6'b001001 : begin data_collision_b_a <= 2'b10; display_ra_wb; end + 6'b010001 : begin data_collision_b_a <= 2'b10; display_ra_wb; end + 6'b010101 : begin data_collision_b_a <= 2'b10; display_ra_wb; end + 6'b011001 : begin data_collision_b_a <= 2'b10; display_ra_wb; end + 6'b100001 : begin data_collision_b_a <= 2'b10; display_ra_wb; end + 6'b100101 : begin data_collision_b_a <= 2'b10; display_ra_wb; end + 6'b101001 : begin data_collision_b_a <= 2'b10; display_ra_wb; end + 6'b000010 : begin data_collision_b_a <= 2'b01; display_wa_rb; end + 6'b000110 : begin data_collision_b_a <= 2'b01; display_wa_rb; end + 6'b001010 : begin data_collision_b_a <= 2'b01; display_wa_rb; end +// 6'b010010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end +// 6'b010110 : begin data_collision_b_a <= 2'b00; display_wa_rb; end +// 6'b011010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end + 6'b100010 : begin data_collision_b_a <= 2'b01; display_wa_rb; end + 6'b100110 : begin data_collision_b_a <= 2'b01; display_wa_rb; end + 6'b101010 : begin data_collision_b_a <= 2'b01; display_wa_rb; end + endcase + end + end + setup_all_b_a <= 0; + end + + + always @(posedge setup_zero) begin + if (data_addra_int[14:5] == data_addrb_int[14:5]) begin + if ((ena_int == 1) && (enb_int == 1)) begin + case ({wr_mode_a, wr_mode_b, wea_int, web_int}) + 6'b000011 : begin data_collision <= 2'b11; display_wa_wb; end + 6'b000111 : begin data_collision <= 2'b11; display_wa_wb; end + 6'b001011 : begin data_collision <= 2'b10; display_wa_wb; end + 6'b010011 : begin data_collision <= 2'b11; display_wa_wb; end + 6'b010111 : begin data_collision <= 2'b11; display_wa_wb; end + 6'b011011 : begin data_collision <= 2'b10; display_wa_wb; end + 6'b100011 : begin data_collision <= 2'b01; display_wa_wb; end + 6'b100111 : begin data_collision <= 2'b01; display_wa_wb; end + 6'b101011 : begin display_wa_wb; end + 6'b000001 : begin data_collision <= 2'b10; display_ra_wb; end +// 6'b000101 : begin data_collision <= 2'b00; display_ra_wb; end + 6'b001001 : begin data_collision <= 2'b10; display_ra_wb; end + 6'b010001 : begin data_collision <= 2'b10; display_ra_wb; end +// 6'b010101 : begin data_collision <= 2'b00; display_ra_wb; end + 6'b011001 : begin data_collision <= 2'b10; display_ra_wb; end + 6'b100001 : begin data_collision <= 2'b10; display_ra_wb; end +// 6'b100101 : begin data_collision <= 2'b00; display_ra_wb; end + 6'b101001 : begin data_collision <= 2'b10; display_ra_wb; end + 6'b000010 : begin data_collision <= 2'b01; display_wa_rb; end + 6'b000110 : begin data_collision <= 2'b01; display_wa_rb; end + 6'b001010 : begin data_collision <= 2'b01; display_wa_rb; end +// 6'b010010 : begin data_collision <= 2'b00; display_wa_rb; end +// 6'b010110 : begin data_collision <= 2'b00; display_wa_rb; end +// 6'b011010 : begin data_collision <= 2'b00; display_wa_rb; end + 6'b100010 : begin data_collision <= 2'b01; display_wa_rb; end + 6'b100110 : begin data_collision <= 2'b01; display_wa_rb; end + 6'b101010 : begin data_collision <= 2'b01; display_wa_rb; end + endcase + end + end + setup_zero <= 0; + end + + task display_ra_wb; + begin + if (display_flag) + $display("Memory Collision Error on RAMB16_S4_S36:%m at simulation time %.3f ns\nA read was performed on address %h (hex) of Port A while a write was requested to the same address on Port B. The write will be successful however the read value on Port A is unknown until the next CLKA cycle.", $time/1000.0, addra_int); + end + endtask + + task display_wa_rb; + begin + if (display_flag) + $display("Memory Collision Error on RAMB16_S4_S36:%m at simulation time %.3f ns\nA read was performed on address %h (hex) of Port B while a write was requested to the same address on Port A. The write will be successful however the read value on Port B is unknown until the next CLKB cycle.", $time/1000.0, addrb_int); + end + endtask + + task display_wa_wb; + begin + if (display_flag) + $display("Memory Collision Error on RAMB16_S4_S36:%m at simulation time %.3f ns\nA write was requested to the same address simultaneously at both Port A and Port B of the RAM. The contents written to the RAM at address location %h (hex) of Port A and address location %h (hex) of Port B are unknown.", $time/1000.0, addra_int, addrb_int); + end + endtask + + + always @(posedge setup_rf_a_b) begin + if (data_addra_reg[14:5] == data_addrb_int[14:5]) begin + if ((ena_reg == 1) && (enb_int == 1)) begin + case ({wr_mode_a, wr_mode_b, wea_reg, web_int}) +// 6'b000011 : begin data_collision_a_b <= 2'b00; display_wa_wb; end +// 6'b000111 : begin data_collision_a_b <= 2'b00; display_wa_wb; end +// 6'b001011 : begin data_collision_a_b <= 2'b00; display_wa_wb; end + 6'b010011 : begin data_collision_a_b <= 2'b11; display_wa_wb; end + 6'b010111 : begin data_collision_a_b <= 2'b11; display_wa_wb; end + 6'b011011 : begin data_collision_a_b <= 2'b10; display_wa_wb; end +// 6'b100011 : begin data_collision_a_b <= 2'b00; display_wa_wb; end +// 6'b100111 : begin data_collision_a_b <= 2'b00; display_wa_wb; end +// 6'b101011 : begin data_collision_a_b <= 2'b00; display_wa_wb; end +// 6'b000001 : begin data_collision_a_b <= 2'b00; display_ra_wb; end +// 6'b000101 : begin data_collision_a_b <= 2'b00; display_ra_wb; end +// 6'b001001 : begin data_collision_a_b <= 2'b00; display_ra_wb; end +// 6'b010001 : begin data_collision_a_b <= 2'b00; display_ra_wb; end +// 6'b010101 : begin data_collision_a_b <= 2'b00; display_ra_wb; end +// 6'b011001 : begin data_collision_a_b <= 2'b00; display_ra_wb; end +// 6'b100001 : begin data_collision_a_b <= 2'b00; display_ra_wb; end +// 6'b100101 : begin data_collision_a_b <= 2'b00; display_ra_wb; end +// 6'b101001 : begin data_collision_a_b <= 2'b00; display_ra_wb; end +// 6'b000010 : begin data_collision_a_b <= 2'b00; display_wa_rb; end +// 6'b000110 : begin data_collision_a_b <= 2'b00; display_wa_rb; end +// 6'b001010 : begin data_collision_a_b <= 2'b00; display_wa_rb; end + 6'b010010 : begin data_collision_a_b <= 2'b01; display_wa_rb; end + 6'b010110 : begin data_collision_a_b <= 2'b01; display_wa_rb; end + 6'b011010 : begin data_collision_a_b <= 2'b01; display_wa_rb; end +// 6'b100010 : begin data_collision_a_b <= 2'b00; display_wa_rb; end +// 6'b100110 : begin data_collision_a_b <= 2'b00; display_wa_rb; end +// 6'b101010 : begin data_collision_a_b <= 2'b00; display_wa_rb; end + endcase + end + end + setup_rf_a_b <= 0; + end + + + always @(posedge setup_rf_b_a) begin + if (data_addra_int[14:5] == data_addrb_reg[14:5]) begin + if ((ena_int == 1) && (enb_reg == 1)) begin + case ({wr_mode_a, wr_mode_b, wea_int, web_reg}) +// 6'b000011 : begin data_collision_b_a <= 2'b00; display_wa_wb; end + 6'b000111 : begin data_collision_b_a <= 2'b11; display_wa_wb; end +// 6'b001011 : begin data_collision_b_a <= 2'b00; display_wa_wb; end +// 6'b010011 : begin data_collision_b_a <= 2'b00; display_wa_wb; end + 6'b010111 : begin data_collision_b_a <= 2'b11; display_wa_wb; end +// 6'b011011 : begin data_collision_b_a <= 2'b00; display_wa_wb; end +// 6'b100011 : begin data_collision_b_a <= 2'b00; display_wa_wb; end + 6'b100111 : begin data_collision_b_a <= 2'b01; display_wa_wb; end +// 6'b101011 : begin data_collision_b_a <= 2'b00; display_wa_wb; end +// 6'b000001 : begin data_collision_b_a <= 2'b00; display_ra_wb; end + 6'b000101 : begin data_collision_b_a <= 2'b10; display_ra_wb; end +// 6'b001001 : begin data_collision_b_a <= 2'b00; display_ra_wb; end +// 6'b010001 : begin data_collision_b_a <= 2'b00; display_ra_wb; end + 6'b010101 : begin data_collision_b_a <= 2'b10; display_ra_wb; end +// 6'b011001 : begin data_collision_b_a <= 2'b00; display_ra_wb; end +// 6'b100001 : begin data_collision_b_a <= 2'b00; display_ra_wb; end + 6'b100101 : begin data_collision_b_a <= 2'b10; display_ra_wb; end +// 6'b101001 : begin data_collision_b_a <= 2'b00; display_ra_wb; end +// 6'b000010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end +// 6'b000110 : begin data_collision_b_a <= 2'b00; display_wa_rb; end +// 6'b001010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end +// 6'b010010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end +// 6'b010110 : begin data_collision_b_a <= 2'b00; display_wa_rb; end +// 6'b011010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end +// 6'b100010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end +// 6'b100110 : begin data_collision_b_a <= 2'b00; display_wa_rb; end +// 6'b101010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end + endcase + end + end + setup_rf_b_a <= 0; + end + + + always @(posedge clka_int) begin + addra_reg <= addra_int; + ena_reg <= ena_int; + ssra_reg <= ssra_int; + wea_reg <= wea_int; + end + + always @(posedge clkb_int) begin + addrb_reg <= addrb_int; + enb_reg <= enb_int; + ssrb_reg <= ssrb_int; + web_reg <= web_int; + end + + // Data + always @(posedge memory_collision) begin + for (dmi = 0; dmi < 4; dmi = dmi + 1) begin + mem[data_addra_int + dmi] <= 1'bX; + end + memory_collision <= 0; + end + + always @(posedge memory_collision_a_b) begin + for (dmi = 0; dmi < 4; dmi = dmi + 1) begin + mem[data_addra_reg + dmi] <= 1'bX; + end + memory_collision_a_b <= 0; + end + + always @(posedge memory_collision_b_a) begin + for (dmi = 0; dmi < 4; dmi = dmi + 1) begin + mem[data_addra_int + dmi] <= 1'bX; + end + memory_collision_b_a <= 0; + end + + always @(posedge data_collision[1]) begin + if (ssra_int == 0) begin + doa_out <= 4'bX; + end + data_collision[1] <= 0; + end + + always @(posedge data_collision[0]) begin + if (ssrb_int == 0) begin + for (dbi = 0; dbi < 4; dbi = dbi + 1) begin + dob_out[data_addra_int[4 : 0] + dbi] <= 1'bX; + end + end + data_collision[0] <= 0; + end + + always @(posedge data_collision_a_b[1]) begin + if (ssra_reg == 0) begin + doa_out <= 4'bX; + end + data_collision_a_b[1] <= 0; + end + + always @(posedge data_collision_a_b[0]) begin + if (ssrb_int == 0) begin + for (dbi = 0; dbi < 4; dbi = dbi + 1) begin + dob_out[data_addra_reg[4 : 0] + dbi] <= 1'bX; + end + end + data_collision_a_b[0] <= 0; + end + + always @(posedge data_collision_b_a[1]) begin + if (ssra_int == 0) begin + doa_out <= 4'bX; + end + data_collision_b_a[1] <= 0; + end + + always @(posedge data_collision_b_a[0]) begin + if (ssrb_reg == 0) begin + for (dbi = 0; dbi < 4; dbi = dbi + 1) begin + dob_out[data_addra_int[4 : 0] + dbi] <= 1'bX; + end + end + data_collision_b_a[0] <= 0; + end + + + initial begin + case (WRITE_MODE_A) + "WRITE_FIRST" : wr_mode_a <= 2'b00; + "READ_FIRST" : wr_mode_a <= 2'b01; + "NO_CHANGE" : wr_mode_a <= 2'b10; + default : begin + $display("Attribute Syntax Error : The Attribute WRITE_MODE_A on RAMB16_S4_S36 instance %m is set to %s. Legal values for this attribute are WRITE_FIRST, READ_FIRST or NO_CHANGE.", WRITE_MODE_A); + $finish; + end + endcase + end + + initial begin + case (WRITE_MODE_B) + "WRITE_FIRST" : wr_mode_b <= 2'b00; + "READ_FIRST" : wr_mode_b <= 2'b01; + "NO_CHANGE" : wr_mode_b <= 2'b10; + default : begin + $display("Attribute Syntax Error : The Attribute WRITE_MODE_B on RAMB16_S4_S36 instance %m is set to %s. Legal values for this attribute are WRITE_FIRST, READ_FIRST or NO_CHANGE.", WRITE_MODE_B); + $finish; + end + endcase + end + + // Port A + always @(posedge clka_int) begin + if (ena_int == 1'b1) begin + if (ssra_int == 1'b1) begin + doa_out[0] <= SRVAL_A[0]; + doa_out[1] <= SRVAL_A[1]; + doa_out[2] <= SRVAL_A[2]; + doa_out[3] <= SRVAL_A[3]; + end + else begin + if (wea_int == 1'b1) begin + if (wr_mode_a == 2'b00) begin + doa_out <= dia_int; + end + else if (wr_mode_a == 2'b01) begin + doa_out[0] <= mem[data_addra_int + 0]; + doa_out[1] <= mem[data_addra_int + 1]; + doa_out[2] <= mem[data_addra_int + 2]; + doa_out[3] <= mem[data_addra_int + 3]; + end + end + else begin + doa_out[0] <= mem[data_addra_int + 0]; + doa_out[1] <= mem[data_addra_int + 1]; + doa_out[2] <= mem[data_addra_int + 2]; + doa_out[3] <= mem[data_addra_int + 3]; + end + end + end + end + + always @(posedge clka_int) begin + if (ena_int == 1'b1 && wea_int == 1'b1) begin + mem[data_addra_int + 0] <= dia_int[0]; + mem[data_addra_int + 1] <= dia_int[1]; + mem[data_addra_int + 2] <= dia_int[2]; + mem[data_addra_int + 3] <= dia_int[3]; + end + end + + // Port B + always @(posedge clkb_int) begin + if (enb_int == 1'b1) begin + if (ssrb_int == 1'b1) begin + dob_out[0] <= SRVAL_B[0]; + dob_out[1] <= SRVAL_B[1]; + dob_out[2] <= SRVAL_B[2]; + dob_out[3] <= SRVAL_B[3]; + dob_out[4] <= SRVAL_B[4]; + dob_out[5] <= SRVAL_B[5]; + dob_out[6] <= SRVAL_B[6]; + dob_out[7] <= SRVAL_B[7]; + dob_out[8] <= SRVAL_B[8]; + dob_out[9] <= SRVAL_B[9]; + dob_out[10] <= SRVAL_B[10]; + dob_out[11] <= SRVAL_B[11]; + dob_out[12] <= SRVAL_B[12]; + dob_out[13] <= SRVAL_B[13]; + dob_out[14] <= SRVAL_B[14]; + dob_out[15] <= SRVAL_B[15]; + dob_out[16] <= SRVAL_B[16]; + dob_out[17] <= SRVAL_B[17]; + dob_out[18] <= SRVAL_B[18]; + dob_out[19] <= SRVAL_B[19]; + dob_out[20] <= SRVAL_B[20]; + dob_out[21] <= SRVAL_B[21]; + dob_out[22] <= SRVAL_B[22]; + dob_out[23] <= SRVAL_B[23]; + dob_out[24] <= SRVAL_B[24]; + dob_out[25] <= SRVAL_B[25]; + dob_out[26] <= SRVAL_B[26]; + dob_out[27] <= SRVAL_B[27]; + dob_out[28] <= SRVAL_B[28]; + dob_out[29] <= SRVAL_B[29]; + dob_out[30] <= SRVAL_B[30]; + dob_out[31] <= SRVAL_B[31]; + dopb_out[0] <= SRVAL_B[32]; + dopb_out[1] <= SRVAL_B[33]; + dopb_out[2] <= SRVAL_B[34]; + dopb_out[3] <= SRVAL_B[35]; + end + else begin + if (web_int == 1'b1) begin + if (wr_mode_b == 2'b00) begin + dob_out <= dib_int; + dopb_out <= dipb_int; + end + else if (wr_mode_b == 2'b01) begin + dob_out[0] <= mem[data_addrb_int + 0]; + dob_out[1] <= mem[data_addrb_int + 1]; + dob_out[2] <= mem[data_addrb_int + 2]; + dob_out[3] <= mem[data_addrb_int + 3]; + dob_out[4] <= mem[data_addrb_int + 4]; + dob_out[5] <= mem[data_addrb_int + 5]; + dob_out[6] <= mem[data_addrb_int + 6]; + dob_out[7] <= mem[data_addrb_int + 7]; + dob_out[8] <= mem[data_addrb_int + 8]; + dob_out[9] <= mem[data_addrb_int + 9]; + dob_out[10] <= mem[data_addrb_int + 10]; + dob_out[11] <= mem[data_addrb_int + 11]; + dob_out[12] <= mem[data_addrb_int + 12]; + dob_out[13] <= mem[data_addrb_int + 13]; + dob_out[14] <= mem[data_addrb_int + 14]; + dob_out[15] <= mem[data_addrb_int + 15]; + dob_out[16] <= mem[data_addrb_int + 16]; + dob_out[17] <= mem[data_addrb_int + 17]; + dob_out[18] <= mem[data_addrb_int + 18]; + dob_out[19] <= mem[data_addrb_int + 19]; + dob_out[20] <= mem[data_addrb_int + 20]; + dob_out[21] <= mem[data_addrb_int + 21]; + dob_out[22] <= mem[data_addrb_int + 22]; + dob_out[23] <= mem[data_addrb_int + 23]; + dob_out[24] <= mem[data_addrb_int + 24]; + dob_out[25] <= mem[data_addrb_int + 25]; + dob_out[26] <= mem[data_addrb_int + 26]; + dob_out[27] <= mem[data_addrb_int + 27]; + dob_out[28] <= mem[data_addrb_int + 28]; + dob_out[29] <= mem[data_addrb_int + 29]; + dob_out[30] <= mem[data_addrb_int + 30]; + dob_out[31] <= mem[data_addrb_int + 31]; + dopb_out[0] <= mem[parity_addrb_int + 0]; + dopb_out[1] <= mem[parity_addrb_int + 1]; + dopb_out[2] <= mem[parity_addrb_int + 2]; + dopb_out[3] <= mem[parity_addrb_int + 3]; + end + end + else begin + dob_out[0] <= mem[data_addrb_int + 0]; + dob_out[1] <= mem[data_addrb_int + 1]; + dob_out[2] <= mem[data_addrb_int + 2]; + dob_out[3] <= mem[data_addrb_int + 3]; + dob_out[4] <= mem[data_addrb_int + 4]; + dob_out[5] <= mem[data_addrb_int + 5]; + dob_out[6] <= mem[data_addrb_int + 6]; + dob_out[7] <= mem[data_addrb_int + 7]; + dob_out[8] <= mem[data_addrb_int + 8]; + dob_out[9] <= mem[data_addrb_int + 9]; + dob_out[10] <= mem[data_addrb_int + 10]; + dob_out[11] <= mem[data_addrb_int + 11]; + dob_out[12] <= mem[data_addrb_int + 12]; + dob_out[13] <= mem[data_addrb_int + 13]; + dob_out[14] <= mem[data_addrb_int + 14]; + dob_out[15] <= mem[data_addrb_int + 15]; + dob_out[16] <= mem[data_addrb_int + 16]; + dob_out[17] <= mem[data_addrb_int + 17]; + dob_out[18] <= mem[data_addrb_int + 18]; + dob_out[19] <= mem[data_addrb_int + 19]; + dob_out[20] <= mem[data_addrb_int + 20]; + dob_out[21] <= mem[data_addrb_int + 21]; + dob_out[22] <= mem[data_addrb_int + 22]; + dob_out[23] <= mem[data_addrb_int + 23]; + dob_out[24] <= mem[data_addrb_int + 24]; + dob_out[25] <= mem[data_addrb_int + 25]; + dob_out[26] <= mem[data_addrb_int + 26]; + dob_out[27] <= mem[data_addrb_int + 27]; + dob_out[28] <= mem[data_addrb_int + 28]; + dob_out[29] <= mem[data_addrb_int + 29]; + dob_out[30] <= mem[data_addrb_int + 30]; + dob_out[31] <= mem[data_addrb_int + 31]; + dopb_out[0] <= mem[parity_addrb_int + 0]; + dopb_out[1] <= mem[parity_addrb_int + 1]; + dopb_out[2] <= mem[parity_addrb_int + 2]; + dopb_out[3] <= mem[parity_addrb_int + 3]; + end + end + end + end + + always @(posedge clkb_int) begin + if (enb_int == 1'b1 && web_int == 1'b1) begin + mem[data_addrb_int + 0] <= dib_int[0]; + mem[data_addrb_int + 1] <= dib_int[1]; + mem[data_addrb_int + 2] <= dib_int[2]; + mem[data_addrb_int + 3] <= dib_int[3]; + mem[data_addrb_int + 4] <= dib_int[4]; + mem[data_addrb_int + 5] <= dib_int[5]; + mem[data_addrb_int + 6] <= dib_int[6]; + mem[data_addrb_int + 7] <= dib_int[7]; + mem[data_addrb_int + 8] <= dib_int[8]; + mem[data_addrb_int + 9] <= dib_int[9]; + mem[data_addrb_int + 10] <= dib_int[10]; + mem[data_addrb_int + 11] <= dib_int[11]; + mem[data_addrb_int + 12] <= dib_int[12]; + mem[data_addrb_int + 13] <= dib_int[13]; + mem[data_addrb_int + 14] <= dib_int[14]; + mem[data_addrb_int + 15] <= dib_int[15]; + mem[data_addrb_int + 16] <= dib_int[16]; + mem[data_addrb_int + 17] <= dib_int[17]; + mem[data_addrb_int + 18] <= dib_int[18]; + mem[data_addrb_int + 19] <= dib_int[19]; + mem[data_addrb_int + 20] <= dib_int[20]; + mem[data_addrb_int + 21] <= dib_int[21]; + mem[data_addrb_int + 22] <= dib_int[22]; + mem[data_addrb_int + 23] <= dib_int[23]; + mem[data_addrb_int + 24] <= dib_int[24]; + mem[data_addrb_int + 25] <= dib_int[25]; + mem[data_addrb_int + 26] <= dib_int[26]; + mem[data_addrb_int + 27] <= dib_int[27]; + mem[data_addrb_int + 28] <= dib_int[28]; + mem[data_addrb_int + 29] <= dib_int[29]; + mem[data_addrb_int + 30] <= dib_int[30]; + mem[data_addrb_int + 31] <= dib_int[31]; + mem[parity_addrb_int + 0] <= dipb_int[0]; + mem[parity_addrb_int + 1] <= dipb_int[1]; + mem[parity_addrb_int + 2] <= dipb_int[2]; + mem[parity_addrb_int + 3] <= dipb_int[3]; + end + end + + specify + (CLKA *> DOA) = (100, 100); + (CLKB *> DOB) = (100, 100); + (CLKB *> DOPB) = (100, 100); + endspecify + +endmodule + +`else + +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/RAMB16_S4_S36.v,v 1.10 2007/02/22 01:58:06 wloo Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2005 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Timing Simulation Library Component +// / / 16K-Bit Data and 2K-Bit Parity Dual Port Block RAM +// /___/ /\ Filename : RAMB16_S4_S36.v +// \ \ / \ Timestamp : Thu Mar 10 16:44:01 PST 2005 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 03/10/05 - Initialized outputs. +// 02/21/07 - Fixed parameter SIM_COLLISION_CHECK (CR 433281). +// End Revision + +`timescale 1 ps/1 ps + +module RAMB16_S4_S36 (DOA, DOB, DOPB, ADDRA, ADDRB, CLKA, CLKB, DIA, DIB, DIPB, ENA, ENB, SSRA, SSRB, WEA, WEB); + + parameter INIT_A = 4'h0; + parameter INIT_B = 36'h0; + parameter SRVAL_A = 4'h0; + parameter SRVAL_B = 36'h0; + parameter WRITE_MODE_A = "WRITE_FIRST"; + parameter WRITE_MODE_B = "WRITE_FIRST"; + parameter SIM_COLLISION_CHECK = "ALL"; + localparam SETUP_ALL = 1000; + localparam SETUP_READ_FIRST = 3000; + + parameter INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + + output [3:0] DOA; + output [31:0] DOB; + output [3:0] DOPB; + + input [11:0] ADDRA; + input [3:0] DIA; + input ENA, CLKA, WEA, SSRA; + input [8:0] ADDRB; + input [31:0] DIB; + input [3:0] DIPB; + input ENB, CLKB, WEB, SSRB; + + reg [3:0] doa_out = INIT_A[3:0]; + reg [31:0] dob_out = INIT_B[31:0]; + reg [3:0] dopb_out = INIT_B[35:32]; + + reg [31:0] mem [511:0]; + reg [3:0] memp [511:0]; + + reg [8:0] count, countp; + reg [1:0] wr_mode_a, wr_mode_b; + + reg [5:0] dmi, dbi; + reg [5:0] pmi, pbi; + + wire [11:0] addra_int; + reg [11:0] addra_reg; + wire [3:0] dia_int; + wire ena_int, clka_int, wea_int, ssra_int; + reg ena_reg, wea_reg, ssra_reg; + wire [8:0] addrb_int; + reg [8:0] addrb_reg; + wire [31:0] dib_int; + wire [3:0] dipb_int; + wire enb_int, clkb_int, web_int, ssrb_int; + reg display_flag, output_flag; + reg enb_reg, web_reg, ssrb_reg; + + time time_clka, time_clkb; + time time_clka_clkb; + time time_clkb_clka; + + reg setup_all_a_b; + reg setup_all_b_a; + reg setup_zero; + reg setup_rf_a_b; + reg setup_rf_b_a; + reg [1:0] data_collision, data_collision_a_b, data_collision_b_a; + reg memory_collision, memory_collision_a_b, memory_collision_b_a; + reg change_clka; + reg change_clkb; + + wire [14:0] data_addra_int; + wire [14:0] data_addra_reg; + wire [14:0] data_addrb_int; + wire [14:0] data_addrb_reg; + + wire dia_enable = ena_int && wea_int; + wire dib_enable = enb_int && web_int; + + tri0 GSR = glbl.GSR; + wire gsr_int; + + buf b_gsr (gsr_int, GSR); + + buf b_doa [3:0] (DOA, doa_out); + buf b_addra [11:0] (addra_int, ADDRA); + buf b_dia [3:0] (dia_int, DIA); + buf b_ena (ena_int, ENA); + buf b_clka (clka_int, CLKA); + buf b_ssra (ssra_int, SSRA); + buf b_wea (wea_int, WEA); + + buf b_dob [31:0] (DOB, dob_out); + buf b_dopb [3:0] (DOPB, dopb_out); + buf b_addrb [8:0] (addrb_int, ADDRB); + buf b_dib [31:0] (dib_int, DIB); + buf b_dipb [3:0] (dipb_int, DIPB); + buf b_enb (enb_int, ENB); + buf b_clkb (clkb_int, CLKB); + buf b_ssrb (ssrb_int, SSRB); + buf b_web (web_int, WEB); + + + always @(gsr_int) + if (gsr_int) begin + assign {doa_out} = INIT_A; + assign {dopb_out, dob_out} = INIT_B; + end + else begin + deassign doa_out; + deassign dob_out; + deassign dopb_out; + end + + + initial begin + + for (count = 0; count < 8; count = count + 1) begin + mem[count] = INIT_00[(count * 32) +: 32]; + mem[8 * 1 + count] = INIT_01[(count * 32) +: 32]; + mem[8 * 2 + count] = INIT_02[(count * 32) +: 32]; + mem[8 * 3 + count] = INIT_03[(count * 32) +: 32]; + mem[8 * 4 + count] = INIT_04[(count * 32) +: 32]; + mem[8 * 5 + count] = INIT_05[(count * 32) +: 32]; + mem[8 * 6 + count] = INIT_06[(count * 32) +: 32]; + mem[8 * 7 + count] = INIT_07[(count * 32) +: 32]; + mem[8 * 8 + count] = INIT_08[(count * 32) +: 32]; + mem[8 * 9 + count] = INIT_09[(count * 32) +: 32]; + mem[8 * 10 + count] = INIT_0A[(count * 32) +: 32]; + mem[8 * 11 + count] = INIT_0B[(count * 32) +: 32]; + mem[8 * 12 + count] = INIT_0C[(count * 32) +: 32]; + mem[8 * 13 + count] = INIT_0D[(count * 32) +: 32]; + mem[8 * 14 + count] = INIT_0E[(count * 32) +: 32]; + mem[8 * 15 + count] = INIT_0F[(count * 32) +: 32]; + mem[8 * 16 + count] = INIT_10[(count * 32) +: 32]; + mem[8 * 17 + count] = INIT_11[(count * 32) +: 32]; + mem[8 * 18 + count] = INIT_12[(count * 32) +: 32]; + mem[8 * 19 + count] = INIT_13[(count * 32) +: 32]; + mem[8 * 20 + count] = INIT_14[(count * 32) +: 32]; + mem[8 * 21 + count] = INIT_15[(count * 32) +: 32]; + mem[8 * 22 + count] = INIT_16[(count * 32) +: 32]; + mem[8 * 23 + count] = INIT_17[(count * 32) +: 32]; + mem[8 * 24 + count] = INIT_18[(count * 32) +: 32]; + mem[8 * 25 + count] = INIT_19[(count * 32) +: 32]; + mem[8 * 26 + count] = INIT_1A[(count * 32) +: 32]; + mem[8 * 27 + count] = INIT_1B[(count * 32) +: 32]; + mem[8 * 28 + count] = INIT_1C[(count * 32) +: 32]; + mem[8 * 29 + count] = INIT_1D[(count * 32) +: 32]; + mem[8 * 30 + count] = INIT_1E[(count * 32) +: 32]; + mem[8 * 31 + count] = INIT_1F[(count * 32) +: 32]; + mem[8 * 32 + count] = INIT_20[(count * 32) +: 32]; + mem[8 * 33 + count] = INIT_21[(count * 32) +: 32]; + mem[8 * 34 + count] = INIT_22[(count * 32) +: 32]; + mem[8 * 35 + count] = INIT_23[(count * 32) +: 32]; + mem[8 * 36 + count] = INIT_24[(count * 32) +: 32]; + mem[8 * 37 + count] = INIT_25[(count * 32) +: 32]; + mem[8 * 38 + count] = INIT_26[(count * 32) +: 32]; + mem[8 * 39 + count] = INIT_27[(count * 32) +: 32]; + mem[8 * 40 + count] = INIT_28[(count * 32) +: 32]; + mem[8 * 41 + count] = INIT_29[(count * 32) +: 32]; + mem[8 * 42 + count] = INIT_2A[(count * 32) +: 32]; + mem[8 * 43 + count] = INIT_2B[(count * 32) +: 32]; + mem[8 * 44 + count] = INIT_2C[(count * 32) +: 32]; + mem[8 * 45 + count] = INIT_2D[(count * 32) +: 32]; + mem[8 * 46 + count] = INIT_2E[(count * 32) +: 32]; + mem[8 * 47 + count] = INIT_2F[(count * 32) +: 32]; + mem[8 * 48 + count] = INIT_30[(count * 32) +: 32]; + mem[8 * 49 + count] = INIT_31[(count * 32) +: 32]; + mem[8 * 50 + count] = INIT_32[(count * 32) +: 32]; + mem[8 * 51 + count] = INIT_33[(count * 32) +: 32]; + mem[8 * 52 + count] = INIT_34[(count * 32) +: 32]; + mem[8 * 53 + count] = INIT_35[(count * 32) +: 32]; + mem[8 * 54 + count] = INIT_36[(count * 32) +: 32]; + mem[8 * 55 + count] = INIT_37[(count * 32) +: 32]; + mem[8 * 56 + count] = INIT_38[(count * 32) +: 32]; + mem[8 * 57 + count] = INIT_39[(count * 32) +: 32]; + mem[8 * 58 + count] = INIT_3A[(count * 32) +: 32]; + mem[8 * 59 + count] = INIT_3B[(count * 32) +: 32]; + mem[8 * 60 + count] = INIT_3C[(count * 32) +: 32]; + mem[8 * 61 + count] = INIT_3D[(count * 32) +: 32]; + mem[8 * 62 + count] = INIT_3E[(count * 32) +: 32]; + mem[8 * 63 + count] = INIT_3F[(count * 32) +: 32]; + end + +// initiate parity start + for (countp = 0; countp < 64; countp = countp + 1) begin + memp[countp] = INITP_00[(countp * 4) +: 4]; + memp[64 * 1 + countp] = INITP_01[(countp * 4) +: 4]; + memp[64 * 2 + countp] = INITP_02[(countp * 4) +: 4]; + memp[64 * 3 + countp] = INITP_03[(countp * 4) +: 4]; + memp[64 * 4 + countp] = INITP_04[(countp * 4) +: 4]; + memp[64 * 5 + countp] = INITP_05[(countp * 4) +: 4]; + memp[64 * 6 + countp] = INITP_06[(countp * 4) +: 4]; + memp[64 * 7 + countp] = INITP_07[(countp * 4) +: 4]; + end +// initiate parity end + + change_clka <= 0; + change_clkb <= 0; + data_collision <= 0; + data_collision_a_b <= 0; + data_collision_b_a <= 0; + memory_collision <= 0; + memory_collision_a_b <= 0; + memory_collision_b_a <= 0; + setup_all_a_b <= 0; + setup_all_b_a <= 0; + setup_zero <= 0; + setup_rf_a_b <= 0; + setup_rf_b_a <= 0; + end + + assign data_addra_int = addra_int * 4; + assign data_addra_reg = addra_reg * 4; + assign data_addrb_int = addrb_int * 32; + assign data_addrb_reg = addrb_reg * 32; + + + initial begin + + display_flag = 1; + output_flag = 1; + + case (SIM_COLLISION_CHECK) + + "NONE" : begin + output_flag = 0; + display_flag = 0; + end + "WARNING_ONLY" : output_flag = 0; + "GENERATE_X_ONLY" : display_flag = 0; + "ALL" : ; + + default : begin + $display("Attribute Syntax Error : The Attribute SIM_COLLISION_CHECK on RAMB16_S4_S36 instance %m is set to %s. Legal values for this attribute are ALL, NONE, WARNING_ONLY or GENERATE_X_ONLY.", SIM_COLLISION_CHECK); + $finish; + end + + endcase // case(SIM_COLLISION_CHECK) + + end // initial begin + + + always @(posedge clka_int) begin + if ((output_flag || display_flag)) begin + time_clka = $time; + #0 time_clkb_clka = time_clka - time_clkb; + change_clka = ~change_clka; + end + end + + always @(posedge clkb_int) begin + if ((output_flag || display_flag)) begin + time_clkb = $time; + #0 time_clka_clkb = time_clkb - time_clka; + change_clkb = ~change_clkb; + end + end + + always @(change_clkb) begin + if ((0 < time_clka_clkb) && (time_clka_clkb < SETUP_ALL)) + setup_all_a_b = 1; + if ((0 < time_clka_clkb) && (time_clka_clkb < SETUP_READ_FIRST)) + setup_rf_a_b = 1; + end + + always @(change_clka) begin + if ((0 < time_clkb_clka) && (time_clkb_clka < SETUP_ALL)) + setup_all_b_a = 1; + if ((0 < time_clkb_clka) && (time_clkb_clka < SETUP_READ_FIRST)) + setup_rf_b_a = 1; + end + + always @(change_clkb or change_clka) begin + if ((time_clkb_clka == 0) && (time_clka_clkb == 0)) + setup_zero = 1; + end + + always @(posedge setup_zero) begin + if ((ena_int == 1) && (wea_int == 1) && + (enb_int == 1) && (web_int == 1) && + (data_addra_int[14:5] == data_addrb_int[14:5])) + memory_collision <= 1; + end + + always @(posedge setup_all_a_b or posedge setup_rf_a_b) begin + if ((ena_reg == 1) && (wea_reg == 1) && + (enb_int == 1) && (web_int == 1) && + (data_addra_reg[14:5] == data_addrb_int[14:5])) + memory_collision_a_b <= 1; + end + + always @(posedge setup_all_b_a or posedge setup_rf_b_a) begin + if ((ena_int == 1) && (wea_int == 1) && + (enb_reg == 1) && (web_reg == 1) && + (data_addra_int[14:5] == data_addrb_reg[14:5])) + memory_collision_b_a <= 1; + end + + always @(posedge setup_all_a_b) begin + if (data_addra_reg[14:5] == data_addrb_int[14:5]) begin + if ((ena_reg == 1) && (enb_int == 1)) begin + case ({wr_mode_a, wr_mode_b, wea_reg, web_int}) + 6'b000011 : begin data_collision_a_b <= 2'b11; display_wa_wb; end + 6'b000111 : begin data_collision_a_b <= 2'b11; display_wa_wb; end + 6'b001011 : begin data_collision_a_b <= 2'b10; display_wa_wb; end +// 6'b010011 : begin data_collision_a_b <= 2'b00; display_wa_wb; end +// 6'b010111 : begin data_collision_a_b <= 2'b00; display_wa_wb; end +// 6'b011011 : begin data_collision_a_b <= 2'b00; display_wa_wb; end + 6'b100011 : begin data_collision_a_b <= 2'b01; display_wa_wb; end + 6'b100111 : begin data_collision_a_b <= 2'b01; display_wa_wb; end + 6'b101011 : begin display_wa_wb; end + 6'b000001 : begin data_collision_a_b <= 2'b10; display_ra_wb; end +// 6'b000101 : begin data_collision_a_b <= 2'b00; display_ra_wb; end + 6'b001001 : begin data_collision_a_b <= 2'b10; display_ra_wb; end + 6'b010001 : begin data_collision_a_b <= 2'b10; display_ra_wb; end +// 6'b010101 : begin data_collision_a_b <= 2'b00; display_ra_wb; end + 6'b011001 : begin data_collision_a_b <= 2'b10; display_ra_wb; end + 6'b100001 : begin data_collision_a_b <= 2'b10; display_ra_wb; end +// 6'b100101 : begin data_collision_a_b <= 2'b00; display_ra_wb; end + 6'b101001 : begin data_collision_a_b <= 2'b10; display_ra_wb; end + 6'b000010 : begin data_collision_a_b <= 2'b01; display_wa_rb; end + 6'b000110 : begin data_collision_a_b <= 2'b01; display_wa_rb; end + 6'b001010 : begin data_collision_a_b <= 2'b01; display_wa_rb; end +// 6'b010010 : begin data_collision_a_b <= 2'b00; display_wa_rb; end +// 6'b010110 : begin data_collision_a_b <= 2'b00; display_wa_rb; end +// 6'b011010 : begin data_collision_a_b <= 2'b00; display_wa_rb; end + 6'b100010 : begin data_collision_a_b <= 2'b01; display_wa_rb; end + 6'b100110 : begin data_collision_a_b <= 2'b01; display_wa_rb; end + 6'b101010 : begin data_collision_a_b <= 2'b01; display_wa_rb; end + endcase + end + end + setup_all_a_b <= 0; + end + + + always @(posedge setup_all_b_a) begin + if (data_addra_int[14:5] == data_addrb_reg[14:5]) begin + if ((ena_int == 1) && (enb_reg == 1)) begin + case ({wr_mode_a, wr_mode_b, wea_int, web_reg}) + 6'b000011 : begin data_collision_b_a <= 2'b11; display_wa_wb; end +// 6'b000111 : begin data_collision_b_a <= 2'b00; display_wa_wb; end + 6'b001011 : begin data_collision_b_a <= 2'b10; display_wa_wb; end + 6'b010011 : begin data_collision_b_a <= 2'b11; display_wa_wb; end +// 6'b010111 : begin data_collision_b_a <= 2'b00; display_wa_wb; end + 6'b011011 : begin data_collision_b_a <= 2'b10; display_wa_wb; end + 6'b100011 : begin data_collision_b_a <= 2'b01; display_wa_wb; end + 6'b100111 : begin data_collision_b_a <= 2'b01; display_wa_wb; end + 6'b101011 : begin display_wa_wb; end + 6'b000001 : begin data_collision_b_a <= 2'b10; display_ra_wb; end + 6'b000101 : begin data_collision_b_a <= 2'b10; display_ra_wb; end + 6'b001001 : begin data_collision_b_a <= 2'b10; display_ra_wb; end + 6'b010001 : begin data_collision_b_a <= 2'b10; display_ra_wb; end + 6'b010101 : begin data_collision_b_a <= 2'b10; display_ra_wb; end + 6'b011001 : begin data_collision_b_a <= 2'b10; display_ra_wb; end + 6'b100001 : begin data_collision_b_a <= 2'b10; display_ra_wb; end + 6'b100101 : begin data_collision_b_a <= 2'b10; display_ra_wb; end + 6'b101001 : begin data_collision_b_a <= 2'b10; display_ra_wb; end + 6'b000010 : begin data_collision_b_a <= 2'b01; display_wa_rb; end + 6'b000110 : begin data_collision_b_a <= 2'b01; display_wa_rb; end + 6'b001010 : begin data_collision_b_a <= 2'b01; display_wa_rb; end +// 6'b010010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end +// 6'b010110 : begin data_collision_b_a <= 2'b00; display_wa_rb; end +// 6'b011010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end + 6'b100010 : begin data_collision_b_a <= 2'b01; display_wa_rb; end + 6'b100110 : begin data_collision_b_a <= 2'b01; display_wa_rb; end + 6'b101010 : begin data_collision_b_a <= 2'b01; display_wa_rb; end + endcase + end + end + setup_all_b_a <= 0; + end + + + always @(posedge setup_zero) begin + if (data_addra_int[14:5] == data_addrb_int[14:5]) begin + if ((ena_int == 1) && (enb_int == 1)) begin + case ({wr_mode_a, wr_mode_b, wea_int, web_int}) + 6'b000011 : begin data_collision <= 2'b11; display_wa_wb; end + 6'b000111 : begin data_collision <= 2'b11; display_wa_wb; end + 6'b001011 : begin data_collision <= 2'b10; display_wa_wb; end + 6'b010011 : begin data_collision <= 2'b11; display_wa_wb; end + 6'b010111 : begin data_collision <= 2'b11; display_wa_wb; end + 6'b011011 : begin data_collision <= 2'b10; display_wa_wb; end + 6'b100011 : begin data_collision <= 2'b01; display_wa_wb; end + 6'b100111 : begin data_collision <= 2'b01; display_wa_wb; end + 6'b101011 : begin display_wa_wb; end + 6'b000001 : begin data_collision <= 2'b10; display_ra_wb; end +// 6'b000101 : begin data_collision <= 2'b00; display_ra_wb; end + 6'b001001 : begin data_collision <= 2'b10; display_ra_wb; end + 6'b010001 : begin data_collision <= 2'b10; display_ra_wb; end +// 6'b010101 : begin data_collision <= 2'b00; display_ra_wb; end + 6'b011001 : begin data_collision <= 2'b10; display_ra_wb; end + 6'b100001 : begin data_collision <= 2'b10; display_ra_wb; end +// 6'b100101 : begin data_collision <= 2'b00; display_ra_wb; end + 6'b101001 : begin data_collision <= 2'b10; display_ra_wb; end + 6'b000010 : begin data_collision <= 2'b01; display_wa_rb; end + 6'b000110 : begin data_collision <= 2'b01; display_wa_rb; end + 6'b001010 : begin data_collision <= 2'b01; display_wa_rb; end +// 6'b010010 : begin data_collision <= 2'b00; display_wa_rb; end +// 6'b010110 : begin data_collision <= 2'b00; display_wa_rb; end +// 6'b011010 : begin data_collision <= 2'b00; display_wa_rb; end + 6'b100010 : begin data_collision <= 2'b01; display_wa_rb; end + 6'b100110 : begin data_collision <= 2'b01; display_wa_rb; end + 6'b101010 : begin data_collision <= 2'b01; display_wa_rb; end + endcase + end + end + setup_zero <= 0; + end + + task display_ra_wb; + begin + if (display_flag) + $display("Memory Collision Error on RAMB16_S4_S36:%m at simulation time %.3f ns\nA read was performed on address %h (hex) of Port A while a write was requested to the same address on Port B. The write will be successful however the read value on Port A is unknown until the next CLKA cycle.", $time/1000.0, addra_int); + end + endtask + + task display_wa_rb; + begin + if (display_flag) + $display("Memory Collision Error on RAMB16_S4_S36:%m at simulation time %.3f ns\nA read was performed on address %h (hex) of Port B while a write was requested to the same address on Port A. The write will be successful however the read value on Port B is unknown until the next CLKB cycle.", $time/1000.0, addrb_int); + end + endtask + + task display_wa_wb; + begin + if (display_flag) + $display("Memory Collision Error on RAMB16_S4_S36:%m at simulation time %.3f ns\nA write was requested to the same address simultaneously at both Port A and Port B of the RAM. The contents written to the RAM at address location %h (hex) of Port A and address location %h (hex) of Port B are unknown.", $time/1000.0, addra_int, addrb_int); + end + endtask + + + always @(posedge setup_rf_a_b) begin + if (data_addra_reg[14:5] == data_addrb_int[14:5]) begin + if ((ena_reg == 1) && (enb_int == 1)) begin + case ({wr_mode_a, wr_mode_b, wea_reg, web_int}) +// 6'b000011 : begin data_collision_a_b <= 2'b00; display_wa_wb; end +// 6'b000111 : begin data_collision_a_b <= 2'b00; display_wa_wb; end +// 6'b001011 : begin data_collision_a_b <= 2'b00; display_wa_wb; end + 6'b010011 : begin data_collision_a_b <= 2'b11; display_wa_wb; end + 6'b010111 : begin data_collision_a_b <= 2'b11; display_wa_wb; end + 6'b011011 : begin data_collision_a_b <= 2'b10; display_wa_wb; end +// 6'b100011 : begin data_collision_a_b <= 2'b00; display_wa_wb; end +// 6'b100111 : begin data_collision_a_b <= 2'b00; display_wa_wb; end +// 6'b101011 : begin data_collision_a_b <= 2'b00; display_wa_wb; end +// 6'b000001 : begin data_collision_a_b <= 2'b00; display_ra_wb; end +// 6'b000101 : begin data_collision_a_b <= 2'b00; display_ra_wb; end +// 6'b001001 : begin data_collision_a_b <= 2'b00; display_ra_wb; end +// 6'b010001 : begin data_collision_a_b <= 2'b00; display_ra_wb; end +// 6'b010101 : begin data_collision_a_b <= 2'b00; display_ra_wb; end +// 6'b011001 : begin data_collision_a_b <= 2'b00; display_ra_wb; end +// 6'b100001 : begin data_collision_a_b <= 2'b00; display_ra_wb; end +// 6'b100101 : begin data_collision_a_b <= 2'b00; display_ra_wb; end +// 6'b101001 : begin data_collision_a_b <= 2'b00; display_ra_wb; end +// 6'b000010 : begin data_collision_a_b <= 2'b00; display_wa_rb; end +// 6'b000110 : begin data_collision_a_b <= 2'b00; display_wa_rb; end +// 6'b001010 : begin data_collision_a_b <= 2'b00; display_wa_rb; end + 6'b010010 : begin data_collision_a_b <= 2'b01; display_wa_rb; end + 6'b010110 : begin data_collision_a_b <= 2'b01; display_wa_rb; end + 6'b011010 : begin data_collision_a_b <= 2'b01; display_wa_rb; end +// 6'b100010 : begin data_collision_a_b <= 2'b00; display_wa_rb; end +// 6'b100110 : begin data_collision_a_b <= 2'b00; display_wa_rb; end +// 6'b101010 : begin data_collision_a_b <= 2'b00; display_wa_rb; end + endcase + end + end + setup_rf_a_b <= 0; + end + + + always @(posedge setup_rf_b_a) begin + if (data_addra_int[14:5] == data_addrb_reg[14:5]) begin + if ((ena_int == 1) && (enb_reg == 1)) begin + case ({wr_mode_a, wr_mode_b, wea_int, web_reg}) +// 6'b000011 : begin data_collision_b_a <= 2'b00; display_wa_wb; end + 6'b000111 : begin data_collision_b_a <= 2'b11; display_wa_wb; end +// 6'b001011 : begin data_collision_b_a <= 2'b00; display_wa_wb; end +// 6'b010011 : begin data_collision_b_a <= 2'b00; display_wa_wb; end + 6'b010111 : begin data_collision_b_a <= 2'b11; display_wa_wb; end +// 6'b011011 : begin data_collision_b_a <= 2'b00; display_wa_wb; end +// 6'b100011 : begin data_collision_b_a <= 2'b00; display_wa_wb; end + 6'b100111 : begin data_collision_b_a <= 2'b01; display_wa_wb; end +// 6'b101011 : begin data_collision_b_a <= 2'b00; display_wa_wb; end +// 6'b000001 : begin data_collision_b_a <= 2'b00; display_ra_wb; end + 6'b000101 : begin data_collision_b_a <= 2'b10; display_ra_wb; end +// 6'b001001 : begin data_collision_b_a <= 2'b00; display_ra_wb; end +// 6'b010001 : begin data_collision_b_a <= 2'b00; display_ra_wb; end + 6'b010101 : begin data_collision_b_a <= 2'b10; display_ra_wb; end +// 6'b011001 : begin data_collision_b_a <= 2'b00; display_ra_wb; end +// 6'b100001 : begin data_collision_b_a <= 2'b00; display_ra_wb; end + 6'b100101 : begin data_collision_b_a <= 2'b10; display_ra_wb; end +// 6'b101001 : begin data_collision_b_a <= 2'b00; display_ra_wb; end +// 6'b000010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end +// 6'b000110 : begin data_collision_b_a <= 2'b00; display_wa_rb; end +// 6'b001010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end +// 6'b010010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end +// 6'b010110 : begin data_collision_b_a <= 2'b00; display_wa_rb; end +// 6'b011010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end +// 6'b100010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end +// 6'b100110 : begin data_collision_b_a <= 2'b00; display_wa_rb; end +// 6'b101010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end + endcase + end + end + setup_rf_b_a <= 0; + end + + + always @(posedge clka_int) begin + if ((output_flag || display_flag)) begin + addra_reg <= addra_int; + ena_reg <= ena_int; + ssra_reg <= ssra_int; + wea_reg <= wea_int; + end + end + + always @(posedge clkb_int) begin + if ((output_flag || display_flag)) begin + addrb_reg <= addrb_int; + enb_reg <= enb_int; + ssrb_reg <= ssrb_int; + web_reg <= web_int; + end + end + + + // Data + always @(posedge memory_collision) begin + if ((output_flag || display_flag)) begin + mem[addra_int[11:3]][addra_int[2:0] * 4 +: 4] <= 4'bx; + memory_collision <= 0; + end + + end + + always @(posedge memory_collision_a_b) begin + if ((output_flag || display_flag)) begin + mem[addra_reg[11:3]][addra_reg[2:0] * 4 +: 4] <= 4'bx; + memory_collision_a_b <= 0; + end + end + + always @(posedge memory_collision_b_a) begin + if ((output_flag || display_flag)) begin + mem[addra_int[11:3]][addra_int[2:0] * 4 +: 4] <= 4'bx; + memory_collision_b_a <= 0; + end + end + + always @(posedge data_collision[1]) begin + if (ssra_int == 0 && output_flag) begin + doa_out <= #100 4'bX; + end + data_collision[1] <= 0; + end + + always @(posedge data_collision[0]) begin + if (ssrb_int == 0 && output_flag) begin + dob_out[addra_int[2:0] * 4 +: 4] <= #100 4'bX; + end + data_collision[0] <= 0; + end + + always @(posedge data_collision_a_b[1]) begin + if (ssra_reg == 0 && output_flag) begin + doa_out <= #100 4'bX; + end + data_collision_a_b[1] <= 0; + end + + always @(posedge data_collision_a_b[0]) begin + if (ssrb_int == 0 && output_flag) begin + dob_out[addra_reg[2:0] * 4 +: 4] <= #100 4'bX; + end + data_collision_a_b[0] <= 0; + end + + always @(posedge data_collision_b_a[1]) begin + if (ssra_int == 0 && output_flag) begin + doa_out <= #100 4'bX; + end + data_collision_b_a[1] <= 0; + end + + always @(posedge data_collision_b_a[0]) begin + if (ssrb_reg == 0 && output_flag) begin + dob_out[addra_int[2:0] * 4 +: 4] <= #100 4'bX; + end + data_collision_b_a[0] <= 0; + end + + + initial begin + case (WRITE_MODE_A) + "WRITE_FIRST" : wr_mode_a <= 2'b00; + "READ_FIRST" : wr_mode_a <= 2'b01; + "NO_CHANGE" : wr_mode_a <= 2'b10; + default : begin + $display("Attribute Syntax Error : The Attribute WRITE_MODE_A on RAMB16_S4_S36 instance %m is set to %s. Legal values for this attribute are WRITE_FIRST, READ_FIRST or NO_CHANGE.", WRITE_MODE_A); + $finish; + end + endcase + end + + initial begin + case (WRITE_MODE_B) + "WRITE_FIRST" : wr_mode_b <= 2'b00; + "READ_FIRST" : wr_mode_b <= 2'b01; + "NO_CHANGE" : wr_mode_b <= 2'b10; + default : begin + $display("Attribute Syntax Error : The Attribute WRITE_MODE_B on RAMB16_S4_S36 instance %m is set to %s. Legal values for this attribute are WRITE_FIRST, READ_FIRST or NO_CHANGE.", WRITE_MODE_B); + $finish; + end + endcase + end + + + // Port A + always @(posedge clka_int) begin + + if (ena_int == 1'b1) begin + + if (ssra_int == 1'b1) begin + {doa_out} <= #100 SRVAL_A; + end + else begin + if (wea_int == 1'b1) begin + if (wr_mode_a == 2'b00) begin + doa_out <= #100 dia_int; + end + else if (wr_mode_a == 2'b01) begin + + doa_out <= #100 mem[addra_int[11:3]][addra_int[2:0] * 4 +: 4]; + + end + end + else begin + + doa_out <= #100 mem[addra_int[11:3]][addra_int[2:0] * 4 +: 4]; + + end + end + + // memory + if (wea_int == 1'b1) begin + mem[addra_int[11:3]][addra_int[2:0] * 4 +: 4] <= dia_int; + end + + end + end + + + // Port B + always @(posedge clkb_int) begin + + if (enb_int == 1'b1) begin + + if (ssrb_int == 1'b1) begin + {dopb_out, dob_out} <= #100 SRVAL_B; + end + else begin + if (web_int == 1'b1) begin + if (wr_mode_b == 2'b00) begin + dob_out <= #100 dib_int; + dopb_out <= #100 dipb_int; + end + else if (wr_mode_b == 2'b01) begin + dob_out <= #100 mem[addrb_int]; + dopb_out <= #100 memp[addrb_int]; + end + end + else begin + dob_out <= #100 mem[addrb_int]; + dopb_out <= #100 memp[addrb_int]; + end + end + + // memory + if (web_int == 1'b1) begin + mem[addrb_int] <= dib_int; + memp[addrb_int] <= dipb_int; + end + + end + end + + +endmodule + +`endif diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/RAMB16_S4_S4.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/RAMB16_S4_S4.v new file mode 100644 index 0000000..b6cb984 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/RAMB16_S4_S4.v @@ -0,0 +1,1562 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/RAMB16_S4_S4.v,v 1.11 2007/02/22 01:58:06 wloo Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2005 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / 16K-Bit Data and 2K-Bit Parity Dual Port Block RAM +// /___/ /\ Filename : RAMB16_S4_S4.v +// \ \ / \ Timestamp : Thu Mar 10 16:43:37 PST 2005 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// End Revision + +`ifdef legacy_model + +`timescale 1 ps / 1 ps + +module RAMB16_S4_S4 (DOA, DOB, ADDRA, ADDRB, CLKA, CLKB, DIA, DIB, ENA, ENB, SSRA, SSRB, WEA, WEB); + + parameter INIT_A = 4'h0; + parameter INIT_B = 4'h0; + parameter SRVAL_A = 4'h0; + parameter SRVAL_B = 4'h0; + parameter WRITE_MODE_A = "WRITE_FIRST"; + parameter WRITE_MODE_B = "WRITE_FIRST"; + parameter SIM_COLLISION_CHECK = "ALL"; + localparam SETUP_ALL = 1000; + localparam SETUP_READ_FIRST = 3000; + + parameter INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + + output [3:0] DOA; + reg [3:0] doa_out; + wire doa_out0, doa_out1, doa_out2, doa_out3; + + input [11:0] ADDRA; + input [3:0] DIA; + input ENA, CLKA, WEA, SSRA; + + output [3:0] DOB; + reg [3:0] dob_out; + wire dob_out0, dob_out1, dob_out2, dob_out3; + + input [11:0] ADDRB; + input [3:0] DIB; + input ENB, CLKB, WEB, SSRB; + + reg [18431:0] mem; + reg [8:0] count; + reg [1:0] wr_mode_a, wr_mode_b; + + reg [5:0] dmi, dbi; + reg [5:0] pmi, pbi; + + wire [11:0] addra_int; + reg [11:0] addra_reg; + wire [3:0] dia_int; + wire ena_int, clka_int, wea_int, ssra_int; + reg ena_reg, wea_reg, ssra_reg; + wire [11:0] addrb_int; + reg [11:0] addrb_reg; + wire [3:0] dib_int; + wire enb_int, clkb_int, web_int, ssrb_int; + reg display_flag; + reg enb_reg, web_reg, ssrb_reg; + + time time_clka, time_clkb; + time time_clka_clkb; + time time_clkb_clka; + + reg setup_all_a_b; + reg setup_all_b_a; + reg setup_zero; + reg setup_rf_a_b; + reg setup_rf_b_a; + reg [1:0] data_collision, data_collision_a_b, data_collision_b_a; + reg memory_collision, memory_collision_a_b, memory_collision_b_a; + reg address_collision, address_collision_a_b, address_collision_b_a; + reg change_clka; + reg change_clkb; + + wire [14:0] data_addra_int; + wire [14:0] data_addra_reg; + wire [14:0] data_addrb_int; + wire [14:0] data_addrb_reg; + wire [15:0] parity_addra_int; + wire [15:0] parity_addra_reg; + wire [15:0] parity_addrb_int; + wire [15:0] parity_addrb_reg; + + tri0 GSR = glbl.GSR; + + always @(GSR) + if (GSR) begin + assign doa_out = INIT_A[3:0]; + assign dob_out = INIT_B[3:0]; + end + else begin + deassign doa_out; + deassign dob_out; + end + + buf b_doa_out0 (doa_out0, doa_out[0]); + buf b_doa_out1 (doa_out1, doa_out[1]); + buf b_doa_out2 (doa_out2, doa_out[2]); + buf b_doa_out3 (doa_out3, doa_out[3]); + buf b_dob_out0 (dob_out0, dob_out[0]); + buf b_dob_out1 (dob_out1, dob_out[1]); + buf b_dob_out2 (dob_out2, dob_out[2]); + buf b_dob_out3 (dob_out3, dob_out[3]); + + buf b_doa0 (DOA[0], doa_out0); + buf b_doa1 (DOA[1], doa_out1); + buf b_doa2 (DOA[2], doa_out2); + buf b_doa3 (DOA[3], doa_out3); + buf b_dob0 (DOB[0], dob_out0); + buf b_dob1 (DOB[1], dob_out1); + buf b_dob2 (DOB[2], dob_out2); + buf b_dob3 (DOB[3], dob_out3); + + buf b_addra_0 (addra_int[0], ADDRA[0]); + buf b_addra_1 (addra_int[1], ADDRA[1]); + buf b_addra_2 (addra_int[2], ADDRA[2]); + buf b_addra_3 (addra_int[3], ADDRA[3]); + buf b_addra_4 (addra_int[4], ADDRA[4]); + buf b_addra_5 (addra_int[5], ADDRA[5]); + buf b_addra_6 (addra_int[6], ADDRA[6]); + buf b_addra_7 (addra_int[7], ADDRA[7]); + buf b_addra_8 (addra_int[8], ADDRA[8]); + buf b_addra_9 (addra_int[9], ADDRA[9]); + buf b_addra_10 (addra_int[10], ADDRA[10]); + buf b_addra_11 (addra_int[11], ADDRA[11]); + buf b_dia_0 (dia_int[0], DIA[0]); + buf b_dia_1 (dia_int[1], DIA[1]); + buf b_dia_2 (dia_int[2], DIA[2]); + buf b_dia_3 (dia_int[3], DIA[3]); + buf b_ena (ena_int, ENA); + buf b_clka (clka_int, CLKA); + buf b_ssra (ssra_int, SSRA); + buf b_wea (wea_int, WEA); + buf b_addrb_0 (addrb_int[0], ADDRB[0]); + buf b_addrb_1 (addrb_int[1], ADDRB[1]); + buf b_addrb_2 (addrb_int[2], ADDRB[2]); + buf b_addrb_3 (addrb_int[3], ADDRB[3]); + buf b_addrb_4 (addrb_int[4], ADDRB[4]); + buf b_addrb_5 (addrb_int[5], ADDRB[5]); + buf b_addrb_6 (addrb_int[6], ADDRB[6]); + buf b_addrb_7 (addrb_int[7], ADDRB[7]); + buf b_addrb_8 (addrb_int[8], ADDRB[8]); + buf b_addrb_9 (addrb_int[9], ADDRB[9]); + buf b_addrb_10 (addrb_int[10], ADDRB[10]); + buf b_addrb_11 (addrb_int[11], ADDRB[11]); + buf b_dib_0 (dib_int[0], DIB[0]); + buf b_dib_1 (dib_int[1], DIB[1]); + buf b_dib_2 (dib_int[2], DIB[2]); + buf b_dib_3 (dib_int[3], DIB[3]); + buf b_enb (enb_int, ENB); + buf b_clkb (clkb_int, CLKB); + buf b_ssrb (ssrb_int, SSRB); + buf b_web (web_int, WEB); + + initial begin + for (count = 0; count < 256; count = count + 1) begin + mem[count] <= INIT_00[count]; + mem[256 * 1 + count] <= INIT_01[count]; + mem[256 * 2 + count] <= INIT_02[count]; + mem[256 * 3 + count] <= INIT_03[count]; + mem[256 * 4 + count] <= INIT_04[count]; + mem[256 * 5 + count] <= INIT_05[count]; + mem[256 * 6 + count] <= INIT_06[count]; + mem[256 * 7 + count] <= INIT_07[count]; + mem[256 * 8 + count] <= INIT_08[count]; + mem[256 * 9 + count] <= INIT_09[count]; + mem[256 * 10 + count] <= INIT_0A[count]; + mem[256 * 11 + count] <= INIT_0B[count]; + mem[256 * 12 + count] <= INIT_0C[count]; + mem[256 * 13 + count] <= INIT_0D[count]; + mem[256 * 14 + count] <= INIT_0E[count]; + mem[256 * 15 + count] <= INIT_0F[count]; + mem[256 * 16 + count] <= INIT_10[count]; + mem[256 * 17 + count] <= INIT_11[count]; + mem[256 * 18 + count] <= INIT_12[count]; + mem[256 * 19 + count] <= INIT_13[count]; + mem[256 * 20 + count] <= INIT_14[count]; + mem[256 * 21 + count] <= INIT_15[count]; + mem[256 * 22 + count] <= INIT_16[count]; + mem[256 * 23 + count] <= INIT_17[count]; + mem[256 * 24 + count] <= INIT_18[count]; + mem[256 * 25 + count] <= INIT_19[count]; + mem[256 * 26 + count] <= INIT_1A[count]; + mem[256 * 27 + count] <= INIT_1B[count]; + mem[256 * 28 + count] <= INIT_1C[count]; + mem[256 * 29 + count] <= INIT_1D[count]; + mem[256 * 30 + count] <= INIT_1E[count]; + mem[256 * 31 + count] <= INIT_1F[count]; + mem[256 * 32 + count] <= INIT_20[count]; + mem[256 * 33 + count] <= INIT_21[count]; + mem[256 * 34 + count] <= INIT_22[count]; + mem[256 * 35 + count] <= INIT_23[count]; + mem[256 * 36 + count] <= INIT_24[count]; + mem[256 * 37 + count] <= INIT_25[count]; + mem[256 * 38 + count] <= INIT_26[count]; + mem[256 * 39 + count] <= INIT_27[count]; + mem[256 * 40 + count] <= INIT_28[count]; + mem[256 * 41 + count] <= INIT_29[count]; + mem[256 * 42 + count] <= INIT_2A[count]; + mem[256 * 43 + count] <= INIT_2B[count]; + mem[256 * 44 + count] <= INIT_2C[count]; + mem[256 * 45 + count] <= INIT_2D[count]; + mem[256 * 46 + count] <= INIT_2E[count]; + mem[256 * 47 + count] <= INIT_2F[count]; + mem[256 * 48 + count] <= INIT_30[count]; + mem[256 * 49 + count] <= INIT_31[count]; + mem[256 * 50 + count] <= INIT_32[count]; + mem[256 * 51 + count] <= INIT_33[count]; + mem[256 * 52 + count] <= INIT_34[count]; + mem[256 * 53 + count] <= INIT_35[count]; + mem[256 * 54 + count] <= INIT_36[count]; + mem[256 * 55 + count] <= INIT_37[count]; + mem[256 * 56 + count] <= INIT_38[count]; + mem[256 * 57 + count] <= INIT_39[count]; + mem[256 * 58 + count] <= INIT_3A[count]; + mem[256 * 59 + count] <= INIT_3B[count]; + mem[256 * 60 + count] <= INIT_3C[count]; + mem[256 * 61 + count] <= INIT_3D[count]; + mem[256 * 62 + count] <= INIT_3E[count]; + mem[256 * 63 + count] <= INIT_3F[count]; + end + address_collision <= 0; + address_collision_a_b <= 0; + address_collision_b_a <= 0; + change_clka <= 0; + change_clkb <= 0; + data_collision <= 0; + data_collision_a_b <= 0; + data_collision_b_a <= 0; + memory_collision <= 0; + memory_collision_a_b <= 0; + memory_collision_b_a <= 0; + setup_all_a_b <= 0; + setup_all_b_a <= 0; + setup_zero <= 0; + setup_rf_a_b <= 0; + setup_rf_b_a <= 0; + end + + assign data_addra_int = addra_int * 4; + assign data_addra_reg = addra_reg * 4; + assign data_addrb_int = addrb_int * 4; + assign data_addrb_reg = addrb_reg * 4; + + + initial begin + + display_flag = 1; + + case (SIM_COLLISION_CHECK) + + "NONE" : begin + assign setup_all_a_b = 1'b0; + assign setup_all_b_a = 1'b0; + assign setup_zero = 1'b0; + assign setup_rf_a_b = 1'b0; + assign setup_rf_b_a = 1'b0; + assign display_flag = 0; + end + "WARNING_ONLY" : begin + assign data_collision = 2'b00; + assign data_collision_a_b = 2'b00; + assign data_collision_b_a = 2'b00; + assign memory_collision = 1'b0; + assign memory_collision_a_b = 1'b0; + assign memory_collision_b_a = 1'b0; + end + "GENERATE_X_ONLY" : begin + assign display_flag = 0; + end + "ALL" : ; + default : begin + $display("Attribute Syntax Error : The Attribute SIM_COLLISION_CHECK on RAMB16_S4_S4 instance %m is set to %s. Legal values for this attribute are ALL, NONE, WARNING_ONLY or GENERATE_X_ONLY.", SIM_COLLISION_CHECK); + $finish; + end + + endcase // case(SIM_COLLISION_CHECK) + + end // initial begin + + + always @(posedge clka_int) begin + time_clka = $time; + #0 time_clkb_clka = time_clka - time_clkb; + change_clka = ~change_clka; + end + + always @(posedge clkb_int) begin + time_clkb = $time; + #0 time_clka_clkb = time_clkb - time_clka; + change_clkb = ~change_clkb; + end + + always @(change_clkb) begin + if ((0 < time_clka_clkb) && (time_clka_clkb < SETUP_ALL)) + setup_all_a_b = 1; + if ((0 < time_clka_clkb) && (time_clka_clkb < SETUP_READ_FIRST)) + setup_rf_a_b = 1; + end + + always @(change_clka) begin + if ((0 < time_clkb_clka) && (time_clkb_clka < SETUP_ALL)) + setup_all_b_a = 1; + if ((0 < time_clkb_clka) && (time_clkb_clka < SETUP_READ_FIRST)) + setup_rf_b_a = 1; + end + + always @(change_clkb or change_clka) begin + if ((time_clkb_clka == 0) && (time_clka_clkb == 0)) + setup_zero = 1; + end + + always @(posedge setup_zero) begin + if ((ena_int == 1) && (wea_int == 1) && + (enb_int == 1) && (web_int == 1) && + (data_addra_int[14:2] == data_addrb_int[14:2])) + memory_collision <= 1; + end + + always @(posedge setup_all_a_b or posedge setup_rf_a_b) begin + if ((ena_reg == 1) && (wea_reg == 1) && + (enb_int == 1) && (web_int == 1) && + (data_addra_reg[14:2] == data_addrb_int[14:2])) + memory_collision_a_b <= 1; + end + + always @(posedge setup_all_b_a or posedge setup_rf_b_a) begin + if ((ena_int == 1) && (wea_int == 1) && + (enb_reg == 1) && (web_reg == 1) && + (data_addra_int[14:2] == data_addrb_reg[14:2])) + memory_collision_b_a <= 1; + end + + always @(posedge setup_all_a_b) begin + if (data_addra_reg[14:2] == data_addrb_int[14:2]) begin + if ((ena_reg == 1) && (enb_int == 1)) begin + case ({wr_mode_a, wr_mode_b, wea_reg, web_int}) + 6'b000011 : begin data_collision_a_b <= 2'b11; display_wa_wb; end + 6'b000111 : begin data_collision_a_b <= 2'b11; display_wa_wb; end + 6'b001011 : begin data_collision_a_b <= 2'b10; display_wa_wb; end +// 6'b010011 : begin data_collision_a_b <= 2'b00; display_wa_wb; end +// 6'b010111 : begin data_collision_a_b <= 2'b00; display_wa_wb; end +// 6'b011011 : begin data_collision_a_b <= 2'b00; display_wa_wb; end + 6'b100011 : begin data_collision_a_b <= 2'b01; display_wa_wb; end + 6'b100111 : begin data_collision_a_b <= 2'b01; display_wa_wb; end + 6'b101011 : begin display_wa_wb; end + 6'b000001 : begin data_collision_a_b <= 2'b10; display_ra_wb; end +// 6'b000101 : begin data_collision_a_b <= 2'b00; display_ra_wb; end + 6'b001001 : begin data_collision_a_b <= 2'b10; display_ra_wb; end + 6'b010001 : begin data_collision_a_b <= 2'b10; display_ra_wb; end +// 6'b010101 : begin data_collision_a_b <= 2'b00; display_ra_wb; end + 6'b011001 : begin data_collision_a_b <= 2'b10; display_ra_wb; end + 6'b100001 : begin data_collision_a_b <= 2'b10; display_ra_wb; end +// 6'b100101 : begin data_collision_a_b <= 2'b00; display_ra_wb; end + 6'b101001 : begin data_collision_a_b <= 2'b10; display_ra_wb; end + 6'b000010 : begin data_collision_a_b <= 2'b01; display_wa_rb; end + 6'b000110 : begin data_collision_a_b <= 2'b01; display_wa_rb; end + 6'b001010 : begin data_collision_a_b <= 2'b01; display_wa_rb; end +// 6'b010010 : begin data_collision_a_b <= 2'b00; display_wa_rb; end +// 6'b010110 : begin data_collision_a_b <= 2'b00; display_wa_rb; end +// 6'b011010 : begin data_collision_a_b <= 2'b00; display_wa_rb; end + 6'b100010 : begin data_collision_a_b <= 2'b01; display_wa_rb; end + 6'b100110 : begin data_collision_a_b <= 2'b01; display_wa_rb; end + 6'b101010 : begin data_collision_a_b <= 2'b01; display_wa_rb; end + endcase + end + end + setup_all_a_b <= 0; + end + + + always @(posedge setup_all_b_a) begin + if (data_addra_int[14:2] == data_addrb_reg[14:2]) begin + if ((ena_int == 1) && (enb_reg == 1)) begin + case ({wr_mode_a, wr_mode_b, wea_int, web_reg}) + 6'b000011 : begin data_collision_b_a <= 2'b11; display_wa_wb; end +// 6'b000111 : begin data_collision_b_a <= 2'b00; display_wa_wb; end + 6'b001011 : begin data_collision_b_a <= 2'b10; display_wa_wb; end + 6'b010011 : begin data_collision_b_a <= 2'b11; display_wa_wb; end +// 6'b010111 : begin data_collision_b_a <= 2'b00; display_wa_wb; end + 6'b011011 : begin data_collision_b_a <= 2'b10; display_wa_wb; end + 6'b100011 : begin data_collision_b_a <= 2'b01; display_wa_wb; end + 6'b100111 : begin data_collision_b_a <= 2'b01; display_wa_wb; end + 6'b101011 : begin display_wa_wb; end + 6'b000001 : begin data_collision_b_a <= 2'b10; display_ra_wb; end + 6'b000101 : begin data_collision_b_a <= 2'b10; display_ra_wb; end + 6'b001001 : begin data_collision_b_a <= 2'b10; display_ra_wb; end + 6'b010001 : begin data_collision_b_a <= 2'b10; display_ra_wb; end + 6'b010101 : begin data_collision_b_a <= 2'b10; display_ra_wb; end + 6'b011001 : begin data_collision_b_a <= 2'b10; display_ra_wb; end + 6'b100001 : begin data_collision_b_a <= 2'b10; display_ra_wb; end + 6'b100101 : begin data_collision_b_a <= 2'b10; display_ra_wb; end + 6'b101001 : begin data_collision_b_a <= 2'b10; display_ra_wb; end + 6'b000010 : begin data_collision_b_a <= 2'b01; display_wa_rb; end + 6'b000110 : begin data_collision_b_a <= 2'b01; display_wa_rb; end + 6'b001010 : begin data_collision_b_a <= 2'b01; display_wa_rb; end +// 6'b010010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end +// 6'b010110 : begin data_collision_b_a <= 2'b00; display_wa_rb; end +// 6'b011010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end + 6'b100010 : begin data_collision_b_a <= 2'b01; display_wa_rb; end + 6'b100110 : begin data_collision_b_a <= 2'b01; display_wa_rb; end + 6'b101010 : begin data_collision_b_a <= 2'b01; display_wa_rb; end + endcase + end + end + setup_all_b_a <= 0; + end + + + always @(posedge setup_zero) begin + if (data_addra_int[14:2] == data_addrb_int[14:2]) begin + if ((ena_int == 1) && (enb_int == 1)) begin + case ({wr_mode_a, wr_mode_b, wea_int, web_int}) + 6'b000011 : begin data_collision <= 2'b11; display_wa_wb; end + 6'b000111 : begin data_collision <= 2'b11; display_wa_wb; end + 6'b001011 : begin data_collision <= 2'b10; display_wa_wb; end + 6'b010011 : begin data_collision <= 2'b11; display_wa_wb; end + 6'b010111 : begin data_collision <= 2'b11; display_wa_wb; end + 6'b011011 : begin data_collision <= 2'b10; display_wa_wb; end + 6'b100011 : begin data_collision <= 2'b01; display_wa_wb; end + 6'b100111 : begin data_collision <= 2'b01; display_wa_wb; end + 6'b101011 : begin display_wa_wb; end + 6'b000001 : begin data_collision <= 2'b10; display_ra_wb; end +// 6'b000101 : begin data_collision <= 2'b00; display_ra_wb; end + 6'b001001 : begin data_collision <= 2'b10; display_ra_wb; end + 6'b010001 : begin data_collision <= 2'b10; display_ra_wb; end +// 6'b010101 : begin data_collision <= 2'b00; display_ra_wb; end + 6'b011001 : begin data_collision <= 2'b10; display_ra_wb; end + 6'b100001 : begin data_collision <= 2'b10; display_ra_wb; end +// 6'b100101 : begin data_collision <= 2'b00; display_ra_wb; end + 6'b101001 : begin data_collision <= 2'b10; display_ra_wb; end + 6'b000010 : begin data_collision <= 2'b01; display_wa_rb; end + 6'b000110 : begin data_collision <= 2'b01; display_wa_rb; end + 6'b001010 : begin data_collision <= 2'b01; display_wa_rb; end +// 6'b010010 : begin data_collision <= 2'b00; display_wa_rb; end +// 6'b010110 : begin data_collision <= 2'b00; display_wa_rb; end +// 6'b011010 : begin data_collision <= 2'b00; display_wa_rb; end + 6'b100010 : begin data_collision <= 2'b01; display_wa_rb; end + 6'b100110 : begin data_collision <= 2'b01; display_wa_rb; end + 6'b101010 : begin data_collision <= 2'b01; display_wa_rb; end + endcase + end + end + setup_zero <= 0; + end + + task display_ra_wb; + begin + if (display_flag) + $display("Memory Collision Error on RAMB16_S4_S4:%m at simulation time %.3f ns\nA read was performed on address %h (hex) of Port A while a write was requested to the same address on Port B. The write will be successful however the read value on Port A is unknown until the next CLKA cycle.", $time/1000.0, addra_int); + end + endtask + + task display_wa_rb; + begin + if (display_flag) + $display("Memory Collision Error on RAMB16_S4_S4:%m at simulation time %.3f ns\nA read was performed on address %h (hex) of Port B while a write was requested to the same address on Port A. The write will be successful however the read value on Port B is unknown until the next CLKB cycle.", $time/1000.0, addrb_int); + end + endtask + + task display_wa_wb; + begin + if (display_flag) + $display("Memory Collision Error on RAMB16_S4_S4:%m at simulation time %.3f ns\nA write was requested to the same address simultaneously at both Port A and Port B of the RAM. The contents written to the RAM at address location %h (hex) of Port A and address location %h (hex) of Port B are unknown.", $time/1000.0, addra_int, addrb_int); + end + endtask + + + always @(posedge setup_rf_a_b) begin + if (data_addra_reg[14:2] == data_addrb_int[14:2]) begin + if ((ena_reg == 1) && (enb_int == 1)) begin + case ({wr_mode_a, wr_mode_b, wea_reg, web_int}) +// 6'b000011 : begin data_collision_a_b <= 2'b00; display_wa_wb; end +// 6'b000111 : begin data_collision_a_b <= 2'b00; display_wa_wb; end +// 6'b001011 : begin data_collision_a_b <= 2'b00; display_wa_wb; end + 6'b010011 : begin data_collision_a_b <= 2'b11; display_wa_wb; end + 6'b010111 : begin data_collision_a_b <= 2'b11; display_wa_wb; end + 6'b011011 : begin data_collision_a_b <= 2'b10; display_wa_wb; end +// 6'b100011 : begin data_collision_a_b <= 2'b00; display_wa_wb; end +// 6'b100111 : begin data_collision_a_b <= 2'b00; display_wa_wb; end +// 6'b101011 : begin data_collision_a_b <= 2'b00; display_wa_wb; end +// 6'b000001 : begin data_collision_a_b <= 2'b00; display_ra_wb; end +// 6'b000101 : begin data_collision_a_b <= 2'b00; display_ra_wb; end +// 6'b001001 : begin data_collision_a_b <= 2'b00; display_ra_wb; end +// 6'b010001 : begin data_collision_a_b <= 2'b00; display_ra_wb; end +// 6'b010101 : begin data_collision_a_b <= 2'b00; display_ra_wb; end +// 6'b011001 : begin data_collision_a_b <= 2'b00; display_ra_wb; end +// 6'b100001 : begin data_collision_a_b <= 2'b00; display_ra_wb; end +// 6'b100101 : begin data_collision_a_b <= 2'b00; display_ra_wb; end +// 6'b101001 : begin data_collision_a_b <= 2'b00; display_ra_wb; end +// 6'b000010 : begin data_collision_a_b <= 2'b00; display_wa_rb; end +// 6'b000110 : begin data_collision_a_b <= 2'b00; display_wa_rb; end +// 6'b001010 : begin data_collision_a_b <= 2'b00; display_wa_rb; end + 6'b010010 : begin data_collision_a_b <= 2'b01; display_wa_rb; end + 6'b010110 : begin data_collision_a_b <= 2'b01; display_wa_rb; end + 6'b011010 : begin data_collision_a_b <= 2'b01; display_wa_rb; end +// 6'b100010 : begin data_collision_a_b <= 2'b00; display_wa_rb; end +// 6'b100110 : begin data_collision_a_b <= 2'b00; display_wa_rb; end +// 6'b101010 : begin data_collision_a_b <= 2'b00; display_wa_rb; end + endcase + end + end + setup_rf_a_b <= 0; + end + + + always @(posedge setup_rf_b_a) begin + if (data_addra_int[14:2] == data_addrb_reg[14:2]) begin + if ((ena_int == 1) && (enb_reg == 1)) begin + case ({wr_mode_a, wr_mode_b, wea_int, web_reg}) +// 6'b000011 : begin data_collision_b_a <= 2'b00; display_wa_wb; end + 6'b000111 : begin data_collision_b_a <= 2'b11; display_wa_wb; end +// 6'b001011 : begin data_collision_b_a <= 2'b00; display_wa_wb; end +// 6'b010011 : begin data_collision_b_a <= 2'b00; display_wa_wb; end + 6'b010111 : begin data_collision_b_a <= 2'b11; display_wa_wb; end +// 6'b011011 : begin data_collision_b_a <= 2'b00; display_wa_wb; end +// 6'b100011 : begin data_collision_b_a <= 2'b00; display_wa_wb; end + 6'b100111 : begin data_collision_b_a <= 2'b01; display_wa_wb; end +// 6'b101011 : begin data_collision_b_a <= 2'b00; display_wa_wb; end +// 6'b000001 : begin data_collision_b_a <= 2'b00; display_ra_wb; end + 6'b000101 : begin data_collision_b_a <= 2'b10; display_ra_wb; end +// 6'b001001 : begin data_collision_b_a <= 2'b00; display_ra_wb; end +// 6'b010001 : begin data_collision_b_a <= 2'b00; display_ra_wb; end + 6'b010101 : begin data_collision_b_a <= 2'b10; display_ra_wb; end +// 6'b011001 : begin data_collision_b_a <= 2'b00; display_ra_wb; end +// 6'b100001 : begin data_collision_b_a <= 2'b00; display_ra_wb; end + 6'b100101 : begin data_collision_b_a <= 2'b10; display_ra_wb; end +// 6'b101001 : begin data_collision_b_a <= 2'b00; display_ra_wb; end +// 6'b000010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end +// 6'b000110 : begin data_collision_b_a <= 2'b00; display_wa_rb; end +// 6'b001010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end +// 6'b010010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end +// 6'b010110 : begin data_collision_b_a <= 2'b00; display_wa_rb; end +// 6'b011010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end +// 6'b100010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end +// 6'b100110 : begin data_collision_b_a <= 2'b00; display_wa_rb; end +// 6'b101010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end + endcase + end + end + setup_rf_b_a <= 0; + end + + + always @(posedge clka_int) begin + addra_reg <= addra_int; + ena_reg <= ena_int; + ssra_reg <= ssra_int; + wea_reg <= wea_int; + end + + always @(posedge clkb_int) begin + addrb_reg <= addrb_int; + enb_reg <= enb_int; + ssrb_reg <= ssrb_int; + web_reg <= web_int; + end + + // Data + always @(posedge memory_collision) begin + for (dmi = 0; dmi < 4; dmi = dmi + 1) begin + mem[data_addra_int + dmi] <= 1'bX; + end + memory_collision <= 0; + end + + always @(posedge memory_collision_a_b) begin + for (dmi = 0; dmi < 4; dmi = dmi + 1) begin + mem[data_addra_reg + dmi] <= 1'bX; + end + memory_collision_a_b <= 0; + end + + always @(posedge memory_collision_b_a) begin + for (dmi = 0; dmi < 4; dmi = dmi + 1) begin + mem[data_addra_int + dmi] <= 1'bX; + end + memory_collision_b_a <= 0; + end + + always @(posedge data_collision[1]) begin + if (ssra_int == 0) begin + doa_out <= 4'bX; + end + data_collision[1] <= 0; + end + + always @(posedge data_collision[0]) begin + if (ssrb_int == 0) begin + dob_out <= 4'bX; + end + data_collision[0] <= 0; + end + + always @(posedge data_collision_a_b[1]) begin + if (ssra_reg == 0) begin + doa_out <= 4'bX; + end + data_collision_a_b[1] <= 0; + end + + always @(posedge data_collision_a_b[0]) begin + if (ssrb_int == 0) begin + dob_out <= 4'bX; + end + data_collision_a_b[0] <= 0; + end + + always @(posedge data_collision_b_a[1]) begin + if (ssra_int == 0) begin + doa_out <= 4'bX; + end + data_collision_b_a[1] <= 0; + end + + always @(posedge data_collision_b_a[0]) begin + if (ssrb_reg == 0) begin + dob_out <= 4'bX; + end + data_collision_b_a[0] <= 0; + end + + + initial begin + case (WRITE_MODE_A) + "WRITE_FIRST" : wr_mode_a <= 2'b00; + "READ_FIRST" : wr_mode_a <= 2'b01; + "NO_CHANGE" : wr_mode_a <= 2'b10; + default : begin + $display("Attribute Syntax Error : The Attribute WRITE_MODE_A on RAMB16_S4_S4 instance %m is set to %s. Legal values for this attribute are WRITE_FIRST, READ_FIRST or NO_CHANGE.", WRITE_MODE_A); + $finish; + end + endcase + end + + initial begin + case (WRITE_MODE_B) + "WRITE_FIRST" : wr_mode_b <= 2'b00; + "READ_FIRST" : wr_mode_b <= 2'b01; + "NO_CHANGE" : wr_mode_b <= 2'b10; + default : begin + $display("Attribute Syntax Error : The Attribute WRITE_MODE_B on RAMB16_S4_S4 instance %m is set to %s. Legal values for this attribute are WRITE_FIRST, READ_FIRST or NO_CHANGE.", WRITE_MODE_B); + $finish; + end + endcase + end + + // Port A + always @(posedge clka_int) begin + if (ena_int == 1'b1) begin + if (ssra_int == 1'b1) begin + doa_out[0] <= SRVAL_A[0]; + doa_out[1] <= SRVAL_A[1]; + doa_out[2] <= SRVAL_A[2]; + doa_out[3] <= SRVAL_A[3]; + end + else begin + if (wea_int == 1'b1) begin + if (wr_mode_a == 2'b00) begin + doa_out <= dia_int; + end + else if (wr_mode_a == 2'b01) begin + doa_out[0] <= mem[data_addra_int + 0]; + doa_out[1] <= mem[data_addra_int + 1]; + doa_out[2] <= mem[data_addra_int + 2]; + doa_out[3] <= mem[data_addra_int + 3]; + end + end + else begin + doa_out[0] <= mem[data_addra_int + 0]; + doa_out[1] <= mem[data_addra_int + 1]; + doa_out[2] <= mem[data_addra_int + 2]; + doa_out[3] <= mem[data_addra_int + 3]; + end + end + end + end + + always @(posedge clka_int) begin + if (ena_int == 1'b1 && wea_int == 1'b1) begin + mem[data_addra_int + 0] <= dia_int[0]; + mem[data_addra_int + 1] <= dia_int[1]; + mem[data_addra_int + 2] <= dia_int[2]; + mem[data_addra_int + 3] <= dia_int[3]; + end + end + + // Port B + always @(posedge clkb_int) begin + if (enb_int == 1'b1) begin + if (ssrb_int == 1'b1) begin + dob_out[0] <= SRVAL_B[0]; + dob_out[1] <= SRVAL_B[1]; + dob_out[2] <= SRVAL_B[2]; + dob_out[3] <= SRVAL_B[3]; + end + else begin + if (web_int == 1'b1) begin + if (wr_mode_b == 2'b00) begin + dob_out <= dib_int; + end + else if (wr_mode_b == 2'b01) begin + dob_out[0] <= mem[data_addrb_int + 0]; + dob_out[1] <= mem[data_addrb_int + 1]; + dob_out[2] <= mem[data_addrb_int + 2]; + dob_out[3] <= mem[data_addrb_int + 3]; + end + end + else begin + dob_out[0] <= mem[data_addrb_int + 0]; + dob_out[1] <= mem[data_addrb_int + 1]; + dob_out[2] <= mem[data_addrb_int + 2]; + dob_out[3] <= mem[data_addrb_int + 3]; + end + end + end + end + + always @(posedge clkb_int) begin + if (enb_int == 1'b1 && web_int == 1'b1) begin + mem[data_addrb_int + 0] <= dib_int[0]; + mem[data_addrb_int + 1] <= dib_int[1]; + mem[data_addrb_int + 2] <= dib_int[2]; + mem[data_addrb_int + 3] <= dib_int[3]; + end + end + + specify + (CLKA *> DOA) = (100, 100); + (CLKB *> DOB) = (100, 100); + endspecify + +endmodule + +`else + +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/RAMB16_S4_S4.v,v 1.11 2007/02/22 01:58:06 wloo Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2005 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Timing Simulation Library Component +// / / 16K-Bit Data and 2K-Bit Parity Dual Port Block RAM +// /___/ /\ Filename : RAMB16_S4_S4.v +// \ \ / \ Timestamp : Thu Mar 10 16:44:01 PST 2005 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 03/10/05 - Initialized outputs. +// 02/21/07 - Fixed parameter SIM_COLLISION_CHECK (CR 433281). +// End Revision + +`timescale 1 ps/1 ps + +module RAMB16_S4_S4 (DOA, DOB, ADDRA, ADDRB, CLKA, CLKB, DIA, DIB, ENA, ENB, SSRA, SSRB, WEA, WEB); + + parameter INIT_A = 4'h0; + parameter INIT_B = 4'h0; + parameter SRVAL_A = 4'h0; + parameter SRVAL_B = 4'h0; + parameter WRITE_MODE_A = "WRITE_FIRST"; + parameter WRITE_MODE_B = "WRITE_FIRST"; + parameter SIM_COLLISION_CHECK = "ALL"; + localparam SETUP_ALL = 1000; + localparam SETUP_READ_FIRST = 3000; + + parameter INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + + output [3:0] DOA; + output [3:0] DOB; + + input [11:0] ADDRA; + input [3:0] DIA; + input ENA, CLKA, WEA, SSRA; + input [11:0] ADDRB; + input [3:0] DIB; + input ENB, CLKB, WEB, SSRB; + + reg [3:0] doa_out = INIT_A[3:0]; + reg [3:0] dob_out = INIT_B[3:0]; + + reg [3:0] mem [4095:0]; + + reg [8:0] count, countp; + reg [1:0] wr_mode_a, wr_mode_b; + + reg [5:0] dmi, dbi; + reg [5:0] pmi, pbi; + + wire [11:0] addra_int; + reg [11:0] addra_reg; + wire [3:0] dia_int; + wire ena_int, clka_int, wea_int, ssra_int; + reg ena_reg, wea_reg, ssra_reg; + wire [11:0] addrb_int; + reg [11:0] addrb_reg; + wire [3:0] dib_int; + wire enb_int, clkb_int, web_int, ssrb_int; + reg display_flag, output_flag; + reg enb_reg, web_reg, ssrb_reg; + + time time_clka, time_clkb; + time time_clka_clkb; + time time_clkb_clka; + + reg setup_all_a_b; + reg setup_all_b_a; + reg setup_zero; + reg setup_rf_a_b; + reg setup_rf_b_a; + reg [1:0] data_collision, data_collision_a_b, data_collision_b_a; + reg memory_collision, memory_collision_a_b, memory_collision_b_a; + reg change_clka; + reg change_clkb; + + wire [14:0] data_addra_int; + wire [14:0] data_addra_reg; + wire [14:0] data_addrb_int; + wire [14:0] data_addrb_reg; + + wire dia_enable = ena_int && wea_int; + wire dib_enable = enb_int && web_int; + + tri0 GSR = glbl.GSR; + wire gsr_int; + + buf b_gsr (gsr_int, GSR); + + buf b_doa [3:0] (DOA, doa_out); + buf b_addra [11:0] (addra_int, ADDRA); + buf b_dia [3:0] (dia_int, DIA); + buf b_ena (ena_int, ENA); + buf b_clka (clka_int, CLKA); + buf b_ssra (ssra_int, SSRA); + buf b_wea (wea_int, WEA); + + buf b_dob [3:0] (DOB, dob_out); + buf b_addrb [11:0] (addrb_int, ADDRB); + buf b_dib [3:0] (dib_int, DIB); + buf b_enb (enb_int, ENB); + buf b_clkb (clkb_int, CLKB); + buf b_ssrb (ssrb_int, SSRB); + buf b_web (web_int, WEB); + + + always @(gsr_int) + if (gsr_int) begin + assign {doa_out} = INIT_A; + assign {dob_out} = INIT_B; + end + else begin + deassign doa_out; + deassign dob_out; + end + + + initial begin + + for (count = 0; count < 64; count = count + 1) begin + mem[count] = INIT_00[(count * 4) +: 4]; + mem[64 * 1 + count] = INIT_01[(count * 4) +: 4]; + mem[64 * 2 + count] = INIT_02[(count * 4) +: 4]; + mem[64 * 3 + count] = INIT_03[(count * 4) +: 4]; + mem[64 * 4 + count] = INIT_04[(count * 4) +: 4]; + mem[64 * 5 + count] = INIT_05[(count * 4) +: 4]; + mem[64 * 6 + count] = INIT_06[(count * 4) +: 4]; + mem[64 * 7 + count] = INIT_07[(count * 4) +: 4]; + mem[64 * 8 + count] = INIT_08[(count * 4) +: 4]; + mem[64 * 9 + count] = INIT_09[(count * 4) +: 4]; + mem[64 * 10 + count] = INIT_0A[(count * 4) +: 4]; + mem[64 * 11 + count] = INIT_0B[(count * 4) +: 4]; + mem[64 * 12 + count] = INIT_0C[(count * 4) +: 4]; + mem[64 * 13 + count] = INIT_0D[(count * 4) +: 4]; + mem[64 * 14 + count] = INIT_0E[(count * 4) +: 4]; + mem[64 * 15 + count] = INIT_0F[(count * 4) +: 4]; + mem[64 * 16 + count] = INIT_10[(count * 4) +: 4]; + mem[64 * 17 + count] = INIT_11[(count * 4) +: 4]; + mem[64 * 18 + count] = INIT_12[(count * 4) +: 4]; + mem[64 * 19 + count] = INIT_13[(count * 4) +: 4]; + mem[64 * 20 + count] = INIT_14[(count * 4) +: 4]; + mem[64 * 21 + count] = INIT_15[(count * 4) +: 4]; + mem[64 * 22 + count] = INIT_16[(count * 4) +: 4]; + mem[64 * 23 + count] = INIT_17[(count * 4) +: 4]; + mem[64 * 24 + count] = INIT_18[(count * 4) +: 4]; + mem[64 * 25 + count] = INIT_19[(count * 4) +: 4]; + mem[64 * 26 + count] = INIT_1A[(count * 4) +: 4]; + mem[64 * 27 + count] = INIT_1B[(count * 4) +: 4]; + mem[64 * 28 + count] = INIT_1C[(count * 4) +: 4]; + mem[64 * 29 + count] = INIT_1D[(count * 4) +: 4]; + mem[64 * 30 + count] = INIT_1E[(count * 4) +: 4]; + mem[64 * 31 + count] = INIT_1F[(count * 4) +: 4]; + mem[64 * 32 + count] = INIT_20[(count * 4) +: 4]; + mem[64 * 33 + count] = INIT_21[(count * 4) +: 4]; + mem[64 * 34 + count] = INIT_22[(count * 4) +: 4]; + mem[64 * 35 + count] = INIT_23[(count * 4) +: 4]; + mem[64 * 36 + count] = INIT_24[(count * 4) +: 4]; + mem[64 * 37 + count] = INIT_25[(count * 4) +: 4]; + mem[64 * 38 + count] = INIT_26[(count * 4) +: 4]; + mem[64 * 39 + count] = INIT_27[(count * 4) +: 4]; + mem[64 * 40 + count] = INIT_28[(count * 4) +: 4]; + mem[64 * 41 + count] = INIT_29[(count * 4) +: 4]; + mem[64 * 42 + count] = INIT_2A[(count * 4) +: 4]; + mem[64 * 43 + count] = INIT_2B[(count * 4) +: 4]; + mem[64 * 44 + count] = INIT_2C[(count * 4) +: 4]; + mem[64 * 45 + count] = INIT_2D[(count * 4) +: 4]; + mem[64 * 46 + count] = INIT_2E[(count * 4) +: 4]; + mem[64 * 47 + count] = INIT_2F[(count * 4) +: 4]; + mem[64 * 48 + count] = INIT_30[(count * 4) +: 4]; + mem[64 * 49 + count] = INIT_31[(count * 4) +: 4]; + mem[64 * 50 + count] = INIT_32[(count * 4) +: 4]; + mem[64 * 51 + count] = INIT_33[(count * 4) +: 4]; + mem[64 * 52 + count] = INIT_34[(count * 4) +: 4]; + mem[64 * 53 + count] = INIT_35[(count * 4) +: 4]; + mem[64 * 54 + count] = INIT_36[(count * 4) +: 4]; + mem[64 * 55 + count] = INIT_37[(count * 4) +: 4]; + mem[64 * 56 + count] = INIT_38[(count * 4) +: 4]; + mem[64 * 57 + count] = INIT_39[(count * 4) +: 4]; + mem[64 * 58 + count] = INIT_3A[(count * 4) +: 4]; + mem[64 * 59 + count] = INIT_3B[(count * 4) +: 4]; + mem[64 * 60 + count] = INIT_3C[(count * 4) +: 4]; + mem[64 * 61 + count] = INIT_3D[(count * 4) +: 4]; + mem[64 * 62 + count] = INIT_3E[(count * 4) +: 4]; + mem[64 * 63 + count] = INIT_3F[(count * 4) +: 4]; + end + + + change_clka <= 0; + change_clkb <= 0; + data_collision <= 0; + data_collision_a_b <= 0; + data_collision_b_a <= 0; + memory_collision <= 0; + memory_collision_a_b <= 0; + memory_collision_b_a <= 0; + setup_all_a_b <= 0; + setup_all_b_a <= 0; + setup_zero <= 0; + setup_rf_a_b <= 0; + setup_rf_b_a <= 0; + end + + assign data_addra_int = addra_int * 4; + assign data_addra_reg = addra_reg * 4; + assign data_addrb_int = addrb_int * 4; + assign data_addrb_reg = addrb_reg * 4; + + + initial begin + + display_flag = 1; + output_flag = 1; + + case (SIM_COLLISION_CHECK) + + "NONE" : begin + output_flag = 0; + display_flag = 0; + end + "WARNING_ONLY" : output_flag = 0; + "GENERATE_X_ONLY" : display_flag = 0; + "ALL" : ; + + default : begin + $display("Attribute Syntax Error : The Attribute SIM_COLLISION_CHECK on RAMB16_S4_S4 instance %m is set to %s. Legal values for this attribute are ALL, NONE, WARNING_ONLY or GENERATE_X_ONLY.", SIM_COLLISION_CHECK); + $finish; + end + + endcase // case(SIM_COLLISION_CHECK) + + end // initial begin + + + always @(posedge clka_int) begin + if ((output_flag || display_flag)) begin + time_clka = $time; + #0 time_clkb_clka = time_clka - time_clkb; + change_clka = ~change_clka; + end + end + + always @(posedge clkb_int) begin + if ((output_flag || display_flag)) begin + time_clkb = $time; + #0 time_clka_clkb = time_clkb - time_clka; + change_clkb = ~change_clkb; + end + end + + always @(change_clkb) begin + if ((0 < time_clka_clkb) && (time_clka_clkb < SETUP_ALL)) + setup_all_a_b = 1; + if ((0 < time_clka_clkb) && (time_clka_clkb < SETUP_READ_FIRST)) + setup_rf_a_b = 1; + end + + always @(change_clka) begin + if ((0 < time_clkb_clka) && (time_clkb_clka < SETUP_ALL)) + setup_all_b_a = 1; + if ((0 < time_clkb_clka) && (time_clkb_clka < SETUP_READ_FIRST)) + setup_rf_b_a = 1; + end + + always @(change_clkb or change_clka) begin + if ((time_clkb_clka == 0) && (time_clka_clkb == 0)) + setup_zero = 1; + end + + always @(posedge setup_zero) begin + if ((ena_int == 1) && (wea_int == 1) && + (enb_int == 1) && (web_int == 1) && + (data_addra_int[14:2] == data_addrb_int[14:2])) + memory_collision <= 1; + end + + always @(posedge setup_all_a_b or posedge setup_rf_a_b) begin + if ((ena_reg == 1) && (wea_reg == 1) && + (enb_int == 1) && (web_int == 1) && + (data_addra_reg[14:2] == data_addrb_int[14:2])) + memory_collision_a_b <= 1; + end + + always @(posedge setup_all_b_a or posedge setup_rf_b_a) begin + if ((ena_int == 1) && (wea_int == 1) && + (enb_reg == 1) && (web_reg == 1) && + (data_addra_int[14:2] == data_addrb_reg[14:2])) + memory_collision_b_a <= 1; + end + + always @(posedge setup_all_a_b) begin + if (data_addra_reg[14:2] == data_addrb_int[14:2]) begin + if ((ena_reg == 1) && (enb_int == 1)) begin + case ({wr_mode_a, wr_mode_b, wea_reg, web_int}) + 6'b000011 : begin data_collision_a_b <= 2'b11; display_wa_wb; end + 6'b000111 : begin data_collision_a_b <= 2'b11; display_wa_wb; end + 6'b001011 : begin data_collision_a_b <= 2'b10; display_wa_wb; end +// 6'b010011 : begin data_collision_a_b <= 2'b00; display_wa_wb; end +// 6'b010111 : begin data_collision_a_b <= 2'b00; display_wa_wb; end +// 6'b011011 : begin data_collision_a_b <= 2'b00; display_wa_wb; end + 6'b100011 : begin data_collision_a_b <= 2'b01; display_wa_wb; end + 6'b100111 : begin data_collision_a_b <= 2'b01; display_wa_wb; end + 6'b101011 : begin display_wa_wb; end + 6'b000001 : begin data_collision_a_b <= 2'b10; display_ra_wb; end +// 6'b000101 : begin data_collision_a_b <= 2'b00; display_ra_wb; end + 6'b001001 : begin data_collision_a_b <= 2'b10; display_ra_wb; end + 6'b010001 : begin data_collision_a_b <= 2'b10; display_ra_wb; end +// 6'b010101 : begin data_collision_a_b <= 2'b00; display_ra_wb; end + 6'b011001 : begin data_collision_a_b <= 2'b10; display_ra_wb; end + 6'b100001 : begin data_collision_a_b <= 2'b10; display_ra_wb; end +// 6'b100101 : begin data_collision_a_b <= 2'b00; display_ra_wb; end + 6'b101001 : begin data_collision_a_b <= 2'b10; display_ra_wb; end + 6'b000010 : begin data_collision_a_b <= 2'b01; display_wa_rb; end + 6'b000110 : begin data_collision_a_b <= 2'b01; display_wa_rb; end + 6'b001010 : begin data_collision_a_b <= 2'b01; display_wa_rb; end +// 6'b010010 : begin data_collision_a_b <= 2'b00; display_wa_rb; end +// 6'b010110 : begin data_collision_a_b <= 2'b00; display_wa_rb; end +// 6'b011010 : begin data_collision_a_b <= 2'b00; display_wa_rb; end + 6'b100010 : begin data_collision_a_b <= 2'b01; display_wa_rb; end + 6'b100110 : begin data_collision_a_b <= 2'b01; display_wa_rb; end + 6'b101010 : begin data_collision_a_b <= 2'b01; display_wa_rb; end + endcase + end + end + setup_all_a_b <= 0; + end + + + always @(posedge setup_all_b_a) begin + if (data_addra_int[14:2] == data_addrb_reg[14:2]) begin + if ((ena_int == 1) && (enb_reg == 1)) begin + case ({wr_mode_a, wr_mode_b, wea_int, web_reg}) + 6'b000011 : begin data_collision_b_a <= 2'b11; display_wa_wb; end +// 6'b000111 : begin data_collision_b_a <= 2'b00; display_wa_wb; end + 6'b001011 : begin data_collision_b_a <= 2'b10; display_wa_wb; end + 6'b010011 : begin data_collision_b_a <= 2'b11; display_wa_wb; end +// 6'b010111 : begin data_collision_b_a <= 2'b00; display_wa_wb; end + 6'b011011 : begin data_collision_b_a <= 2'b10; display_wa_wb; end + 6'b100011 : begin data_collision_b_a <= 2'b01; display_wa_wb; end + 6'b100111 : begin data_collision_b_a <= 2'b01; display_wa_wb; end + 6'b101011 : begin display_wa_wb; end + 6'b000001 : begin data_collision_b_a <= 2'b10; display_ra_wb; end + 6'b000101 : begin data_collision_b_a <= 2'b10; display_ra_wb; end + 6'b001001 : begin data_collision_b_a <= 2'b10; display_ra_wb; end + 6'b010001 : begin data_collision_b_a <= 2'b10; display_ra_wb; end + 6'b010101 : begin data_collision_b_a <= 2'b10; display_ra_wb; end + 6'b011001 : begin data_collision_b_a <= 2'b10; display_ra_wb; end + 6'b100001 : begin data_collision_b_a <= 2'b10; display_ra_wb; end + 6'b100101 : begin data_collision_b_a <= 2'b10; display_ra_wb; end + 6'b101001 : begin data_collision_b_a <= 2'b10; display_ra_wb; end + 6'b000010 : begin data_collision_b_a <= 2'b01; display_wa_rb; end + 6'b000110 : begin data_collision_b_a <= 2'b01; display_wa_rb; end + 6'b001010 : begin data_collision_b_a <= 2'b01; display_wa_rb; end +// 6'b010010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end +// 6'b010110 : begin data_collision_b_a <= 2'b00; display_wa_rb; end +// 6'b011010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end + 6'b100010 : begin data_collision_b_a <= 2'b01; display_wa_rb; end + 6'b100110 : begin data_collision_b_a <= 2'b01; display_wa_rb; end + 6'b101010 : begin data_collision_b_a <= 2'b01; display_wa_rb; end + endcase + end + end + setup_all_b_a <= 0; + end + + + always @(posedge setup_zero) begin + if (data_addra_int[14:2] == data_addrb_int[14:2]) begin + if ((ena_int == 1) && (enb_int == 1)) begin + case ({wr_mode_a, wr_mode_b, wea_int, web_int}) + 6'b000011 : begin data_collision <= 2'b11; display_wa_wb; end + 6'b000111 : begin data_collision <= 2'b11; display_wa_wb; end + 6'b001011 : begin data_collision <= 2'b10; display_wa_wb; end + 6'b010011 : begin data_collision <= 2'b11; display_wa_wb; end + 6'b010111 : begin data_collision <= 2'b11; display_wa_wb; end + 6'b011011 : begin data_collision <= 2'b10; display_wa_wb; end + 6'b100011 : begin data_collision <= 2'b01; display_wa_wb; end + 6'b100111 : begin data_collision <= 2'b01; display_wa_wb; end + 6'b101011 : begin display_wa_wb; end + 6'b000001 : begin data_collision <= 2'b10; display_ra_wb; end +// 6'b000101 : begin data_collision <= 2'b00; display_ra_wb; end + 6'b001001 : begin data_collision <= 2'b10; display_ra_wb; end + 6'b010001 : begin data_collision <= 2'b10; display_ra_wb; end +// 6'b010101 : begin data_collision <= 2'b00; display_ra_wb; end + 6'b011001 : begin data_collision <= 2'b10; display_ra_wb; end + 6'b100001 : begin data_collision <= 2'b10; display_ra_wb; end +// 6'b100101 : begin data_collision <= 2'b00; display_ra_wb; end + 6'b101001 : begin data_collision <= 2'b10; display_ra_wb; end + 6'b000010 : begin data_collision <= 2'b01; display_wa_rb; end + 6'b000110 : begin data_collision <= 2'b01; display_wa_rb; end + 6'b001010 : begin data_collision <= 2'b01; display_wa_rb; end +// 6'b010010 : begin data_collision <= 2'b00; display_wa_rb; end +// 6'b010110 : begin data_collision <= 2'b00; display_wa_rb; end +// 6'b011010 : begin data_collision <= 2'b00; display_wa_rb; end + 6'b100010 : begin data_collision <= 2'b01; display_wa_rb; end + 6'b100110 : begin data_collision <= 2'b01; display_wa_rb; end + 6'b101010 : begin data_collision <= 2'b01; display_wa_rb; end + endcase + end + end + setup_zero <= 0; + end + + task display_ra_wb; + begin + if (display_flag) + $display("Memory Collision Error on RAMB16_S4_S4:%m at simulation time %.3f ns\nA read was performed on address %h (hex) of Port A while a write was requested to the same address on Port B. The write will be successful however the read value on Port A is unknown until the next CLKA cycle.", $time/1000.0, addra_int); + end + endtask + + task display_wa_rb; + begin + if (display_flag) + $display("Memory Collision Error on RAMB16_S4_S4:%m at simulation time %.3f ns\nA read was performed on address %h (hex) of Port B while a write was requested to the same address on Port A. The write will be successful however the read value on Port B is unknown until the next CLKB cycle.", $time/1000.0, addrb_int); + end + endtask + + task display_wa_wb; + begin + if (display_flag) + $display("Memory Collision Error on RAMB16_S4_S4:%m at simulation time %.3f ns\nA write was requested to the same address simultaneously at both Port A and Port B of the RAM. The contents written to the RAM at address location %h (hex) of Port A and address location %h (hex) of Port B are unknown.", $time/1000.0, addra_int, addrb_int); + end + endtask + + + always @(posedge setup_rf_a_b) begin + if (data_addra_reg[14:2] == data_addrb_int[14:2]) begin + if ((ena_reg == 1) && (enb_int == 1)) begin + case ({wr_mode_a, wr_mode_b, wea_reg, web_int}) +// 6'b000011 : begin data_collision_a_b <= 2'b00; display_wa_wb; end +// 6'b000111 : begin data_collision_a_b <= 2'b00; display_wa_wb; end +// 6'b001011 : begin data_collision_a_b <= 2'b00; display_wa_wb; end + 6'b010011 : begin data_collision_a_b <= 2'b11; display_wa_wb; end + 6'b010111 : begin data_collision_a_b <= 2'b11; display_wa_wb; end + 6'b011011 : begin data_collision_a_b <= 2'b10; display_wa_wb; end +// 6'b100011 : begin data_collision_a_b <= 2'b00; display_wa_wb; end +// 6'b100111 : begin data_collision_a_b <= 2'b00; display_wa_wb; end +// 6'b101011 : begin data_collision_a_b <= 2'b00; display_wa_wb; end +// 6'b000001 : begin data_collision_a_b <= 2'b00; display_ra_wb; end +// 6'b000101 : begin data_collision_a_b <= 2'b00; display_ra_wb; end +// 6'b001001 : begin data_collision_a_b <= 2'b00; display_ra_wb; end +// 6'b010001 : begin data_collision_a_b <= 2'b00; display_ra_wb; end +// 6'b010101 : begin data_collision_a_b <= 2'b00; display_ra_wb; end +// 6'b011001 : begin data_collision_a_b <= 2'b00; display_ra_wb; end +// 6'b100001 : begin data_collision_a_b <= 2'b00; display_ra_wb; end +// 6'b100101 : begin data_collision_a_b <= 2'b00; display_ra_wb; end +// 6'b101001 : begin data_collision_a_b <= 2'b00; display_ra_wb; end +// 6'b000010 : begin data_collision_a_b <= 2'b00; display_wa_rb; end +// 6'b000110 : begin data_collision_a_b <= 2'b00; display_wa_rb; end +// 6'b001010 : begin data_collision_a_b <= 2'b00; display_wa_rb; end + 6'b010010 : begin data_collision_a_b <= 2'b01; display_wa_rb; end + 6'b010110 : begin data_collision_a_b <= 2'b01; display_wa_rb; end + 6'b011010 : begin data_collision_a_b <= 2'b01; display_wa_rb; end +// 6'b100010 : begin data_collision_a_b <= 2'b00; display_wa_rb; end +// 6'b100110 : begin data_collision_a_b <= 2'b00; display_wa_rb; end +// 6'b101010 : begin data_collision_a_b <= 2'b00; display_wa_rb; end + endcase + end + end + setup_rf_a_b <= 0; + end + + + always @(posedge setup_rf_b_a) begin + if (data_addra_int[14:2] == data_addrb_reg[14:2]) begin + if ((ena_int == 1) && (enb_reg == 1)) begin + case ({wr_mode_a, wr_mode_b, wea_int, web_reg}) +// 6'b000011 : begin data_collision_b_a <= 2'b00; display_wa_wb; end + 6'b000111 : begin data_collision_b_a <= 2'b11; display_wa_wb; end +// 6'b001011 : begin data_collision_b_a <= 2'b00; display_wa_wb; end +// 6'b010011 : begin data_collision_b_a <= 2'b00; display_wa_wb; end + 6'b010111 : begin data_collision_b_a <= 2'b11; display_wa_wb; end +// 6'b011011 : begin data_collision_b_a <= 2'b00; display_wa_wb; end +// 6'b100011 : begin data_collision_b_a <= 2'b00; display_wa_wb; end + 6'b100111 : begin data_collision_b_a <= 2'b01; display_wa_wb; end +// 6'b101011 : begin data_collision_b_a <= 2'b00; display_wa_wb; end +// 6'b000001 : begin data_collision_b_a <= 2'b00; display_ra_wb; end + 6'b000101 : begin data_collision_b_a <= 2'b10; display_ra_wb; end +// 6'b001001 : begin data_collision_b_a <= 2'b00; display_ra_wb; end +// 6'b010001 : begin data_collision_b_a <= 2'b00; display_ra_wb; end + 6'b010101 : begin data_collision_b_a <= 2'b10; display_ra_wb; end +// 6'b011001 : begin data_collision_b_a <= 2'b00; display_ra_wb; end +// 6'b100001 : begin data_collision_b_a <= 2'b00; display_ra_wb; end + 6'b100101 : begin data_collision_b_a <= 2'b10; display_ra_wb; end +// 6'b101001 : begin data_collision_b_a <= 2'b00; display_ra_wb; end +// 6'b000010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end +// 6'b000110 : begin data_collision_b_a <= 2'b00; display_wa_rb; end +// 6'b001010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end +// 6'b010010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end +// 6'b010110 : begin data_collision_b_a <= 2'b00; display_wa_rb; end +// 6'b011010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end +// 6'b100010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end +// 6'b100110 : begin data_collision_b_a <= 2'b00; display_wa_rb; end +// 6'b101010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end + endcase + end + end + setup_rf_b_a <= 0; + end + + + always @(posedge clka_int) begin + if ((output_flag || display_flag)) begin + addra_reg <= addra_int; + ena_reg <= ena_int; + ssra_reg <= ssra_int; + wea_reg <= wea_int; + end + end + + always @(posedge clkb_int) begin + if ((output_flag || display_flag)) begin + addrb_reg <= addrb_int; + enb_reg <= enb_int; + ssrb_reg <= ssrb_int; + web_reg <= web_int; + end + end + + + // Data + always @(posedge memory_collision) begin + if ((output_flag || display_flag)) begin + mem[addra_int] <= 4'bx; + memory_collision <= 0; + end + + end + + always @(posedge memory_collision_a_b) begin + if ((output_flag || display_flag)) begin + mem[addra_reg] <= 4'bx; + memory_collision_a_b <= 0; + end + end + + always @(posedge memory_collision_b_a) begin + if ((output_flag || display_flag)) begin + mem[addra_int] <= 4'bx; + memory_collision_b_a <= 0; + end + end + + always @(posedge data_collision[1]) begin + if (ssra_int == 0 && output_flag) begin + doa_out <= #100 4'bX; + end + data_collision[1] <= 0; + end + + always @(posedge data_collision[0]) begin + if (ssrb_int == 0 && output_flag) begin + dob_out <= #100 4'bX; + end + data_collision[0] <= 0; + end + + always @(posedge data_collision_a_b[1]) begin + if (ssra_reg == 0 && output_flag) begin + doa_out <= #100 4'bX; + end + data_collision_a_b[1] <= 0; + end + + always @(posedge data_collision_a_b[0]) begin + if (ssrb_int == 0 && output_flag) begin + dob_out <= #100 4'bX; + end + data_collision_a_b[0] <= 0; + end + + always @(posedge data_collision_b_a[1]) begin + if (ssra_int == 0 && output_flag) begin + doa_out <= #100 4'bX; + end + data_collision_b_a[1] <= 0; + end + + always @(posedge data_collision_b_a[0]) begin + if (ssrb_reg == 0 && output_flag) begin + dob_out <= #100 4'bX; + end + data_collision_b_a[0] <= 0; + end + + + initial begin + case (WRITE_MODE_A) + "WRITE_FIRST" : wr_mode_a <= 2'b00; + "READ_FIRST" : wr_mode_a <= 2'b01; + "NO_CHANGE" : wr_mode_a <= 2'b10; + default : begin + $display("Attribute Syntax Error : The Attribute WRITE_MODE_A on RAMB16_S4_S4 instance %m is set to %s. Legal values for this attribute are WRITE_FIRST, READ_FIRST or NO_CHANGE.", WRITE_MODE_A); + $finish; + end + endcase + end + + initial begin + case (WRITE_MODE_B) + "WRITE_FIRST" : wr_mode_b <= 2'b00; + "READ_FIRST" : wr_mode_b <= 2'b01; + "NO_CHANGE" : wr_mode_b <= 2'b10; + default : begin + $display("Attribute Syntax Error : The Attribute WRITE_MODE_B on RAMB16_S4_S4 instance %m is set to %s. Legal values for this attribute are WRITE_FIRST, READ_FIRST or NO_CHANGE.", WRITE_MODE_B); + $finish; + end + endcase + end + + + // Port A + always @(posedge clka_int) begin + + if (ena_int == 1'b1) begin + + if (ssra_int == 1'b1) begin + {doa_out} <= #100 SRVAL_A; + end + else begin + if (wea_int == 1'b1) begin + if (wr_mode_a == 2'b00) begin + doa_out <= #100 dia_int; + end + else if (wr_mode_a == 2'b01) begin + + doa_out <= #100 mem[addra_int]; + + end + end + else begin + + doa_out <= #100 mem[addra_int]; + + end + end + + // memory + if (wea_int == 1'b1) begin + mem[addra_int] <= dia_int; + end + + end + end + + + // Port B + always @(posedge clkb_int) begin + + if (enb_int == 1'b1) begin + + if (ssrb_int == 1'b1) begin + {dob_out} <= #100 SRVAL_B; + end + else begin + if (web_int == 1'b1) begin + if (wr_mode_b == 2'b00) begin + dob_out <= #100 dib_int; + end + else if (wr_mode_b == 2'b01) begin + dob_out <= #100 mem[addrb_int]; + end + end + else begin + dob_out <= #100 mem[addrb_int]; + end + end + + // memory + if (web_int == 1'b1) begin + mem[addrb_int] <= dib_int; + end + + end + end + + +endmodule + +`endif diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/RAMB16_S4_S9.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/RAMB16_S4_S9.v new file mode 100644 index 0000000..28abc0d --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/RAMB16_S4_S9.v @@ -0,0 +1,1661 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/RAMB16_S4_S9.v,v 1.10 2007/02/22 01:58:06 wloo Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2005 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / 16K-Bit Data and 2K-Bit Parity Dual Port Block RAM +// /___/ /\ Filename : RAMB16_S4_S9.v +// \ \ / \ Timestamp : Thu Mar 10 16:43:37 PST 2005 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// End Revision + +`ifdef legacy_model + +`timescale 1 ps / 1 ps + +module RAMB16_S4_S9 (DOA, DOB, DOPB, ADDRA, ADDRB, CLKA, CLKB, DIA, DIB, DIPB, ENA, ENB, SSRA, SSRB, WEA, WEB); + + parameter INIT_A = 4'h0; + parameter INIT_B = 9'h0; + parameter SRVAL_A = 4'h0; + parameter SRVAL_B = 9'h0; + parameter WRITE_MODE_A = "WRITE_FIRST"; + parameter WRITE_MODE_B = "WRITE_FIRST"; + parameter SIM_COLLISION_CHECK = "ALL"; + localparam SETUP_ALL = 1000; + localparam SETUP_READ_FIRST = 3000; + + parameter INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + + output [3:0] DOA; + reg [3:0] doa_out; + wire doa_out0, doa_out1, doa_out2, doa_out3; + + input [11:0] ADDRA; + input [3:0] DIA; + input ENA, CLKA, WEA, SSRA; + + output [7:0] DOB; + output [0:0] DOPB; + reg [7:0] dob_out; + reg [0:0] dopb_out; + wire dob_out0, dob_out1, dob_out2, dob_out3, dob_out4, dob_out5, dob_out6, dob_out7; + wire dopb0_out; + + input [10:0] ADDRB; + input [7:0] DIB; + input [0:0] DIPB; + input ENB, CLKB, WEB, SSRB; + + reg [18431:0] mem; + reg [8:0] count; + reg [1:0] wr_mode_a, wr_mode_b; + + reg [5:0] dmi, dbi; + reg [5:0] pmi, pbi; + + wire [11:0] addra_int; + reg [11:0] addra_reg; + wire [3:0] dia_int; + wire ena_int, clka_int, wea_int, ssra_int; + reg ena_reg, wea_reg, ssra_reg; + wire [10:0] addrb_int; + reg [10:0] addrb_reg; + wire [7:0] dib_int; + wire [0:0] dipb_int; + wire enb_int, clkb_int, web_int, ssrb_int; + reg display_flag; + reg enb_reg, web_reg, ssrb_reg; + + time time_clka, time_clkb; + time time_clka_clkb; + time time_clkb_clka; + + reg setup_all_a_b; + reg setup_all_b_a; + reg setup_zero; + reg setup_rf_a_b; + reg setup_rf_b_a; + reg [1:0] data_collision, data_collision_a_b, data_collision_b_a; + reg memory_collision, memory_collision_a_b, memory_collision_b_a; + reg address_collision, address_collision_a_b, address_collision_b_a; + reg change_clka; + reg change_clkb; + + wire [14:0] data_addra_int; + wire [14:0] data_addra_reg; + wire [14:0] data_addrb_int; + wire [14:0] data_addrb_reg; + wire [15:0] parity_addra_int; + wire [15:0] parity_addra_reg; + wire [15:0] parity_addrb_int; + wire [15:0] parity_addrb_reg; + + tri0 GSR = glbl.GSR; + + always @(GSR) + if (GSR) begin + assign doa_out = INIT_A[3:0]; + assign dob_out = INIT_B[7:0]; + assign dopb_out = INIT_B[8:8]; + end + else begin + deassign doa_out; + deassign dob_out; + deassign dopb_out; + end + + buf b_doa_out0 (doa_out0, doa_out[0]); + buf b_doa_out1 (doa_out1, doa_out[1]); + buf b_doa_out2 (doa_out2, doa_out[2]); + buf b_doa_out3 (doa_out3, doa_out[3]); + buf b_dob_out0 (dob_out0, dob_out[0]); + buf b_dob_out1 (dob_out1, dob_out[1]); + buf b_dob_out2 (dob_out2, dob_out[2]); + buf b_dob_out3 (dob_out3, dob_out[3]); + buf b_dob_out4 (dob_out4, dob_out[4]); + buf b_dob_out5 (dob_out5, dob_out[5]); + buf b_dob_out6 (dob_out6, dob_out[6]); + buf b_dob_out7 (dob_out7, dob_out[7]); + buf b_dopb_out0 (dopb_out0, dopb_out[0]); + + buf b_doa0 (DOA[0], doa_out0); + buf b_doa1 (DOA[1], doa_out1); + buf b_doa2 (DOA[2], doa_out2); + buf b_doa3 (DOA[3], doa_out3); + buf b_dob0 (DOB[0], dob_out0); + buf b_dob1 (DOB[1], dob_out1); + buf b_dob2 (DOB[2], dob_out2); + buf b_dob3 (DOB[3], dob_out3); + buf b_dob4 (DOB[4], dob_out4); + buf b_dob5 (DOB[5], dob_out5); + buf b_dob6 (DOB[6], dob_out6); + buf b_dob7 (DOB[7], dob_out7); + buf b_dopb0 (DOPB[0], dopb_out0); + + buf b_addra_0 (addra_int[0], ADDRA[0]); + buf b_addra_1 (addra_int[1], ADDRA[1]); + buf b_addra_2 (addra_int[2], ADDRA[2]); + buf b_addra_3 (addra_int[3], ADDRA[3]); + buf b_addra_4 (addra_int[4], ADDRA[4]); + buf b_addra_5 (addra_int[5], ADDRA[5]); + buf b_addra_6 (addra_int[6], ADDRA[6]); + buf b_addra_7 (addra_int[7], ADDRA[7]); + buf b_addra_8 (addra_int[8], ADDRA[8]); + buf b_addra_9 (addra_int[9], ADDRA[9]); + buf b_addra_10 (addra_int[10], ADDRA[10]); + buf b_addra_11 (addra_int[11], ADDRA[11]); + buf b_dia_0 (dia_int[0], DIA[0]); + buf b_dia_1 (dia_int[1], DIA[1]); + buf b_dia_2 (dia_int[2], DIA[2]); + buf b_dia_3 (dia_int[3], DIA[3]); + buf b_ena (ena_int, ENA); + buf b_clka (clka_int, CLKA); + buf b_ssra (ssra_int, SSRA); + buf b_wea (wea_int, WEA); + buf b_addrb_0 (addrb_int[0], ADDRB[0]); + buf b_addrb_1 (addrb_int[1], ADDRB[1]); + buf b_addrb_2 (addrb_int[2], ADDRB[2]); + buf b_addrb_3 (addrb_int[3], ADDRB[3]); + buf b_addrb_4 (addrb_int[4], ADDRB[4]); + buf b_addrb_5 (addrb_int[5], ADDRB[5]); + buf b_addrb_6 (addrb_int[6], ADDRB[6]); + buf b_addrb_7 (addrb_int[7], ADDRB[7]); + buf b_addrb_8 (addrb_int[8], ADDRB[8]); + buf b_addrb_9 (addrb_int[9], ADDRB[9]); + buf b_addrb_10 (addrb_int[10], ADDRB[10]); + buf b_dib_0 (dib_int[0], DIB[0]); + buf b_dib_1 (dib_int[1], DIB[1]); + buf b_dib_2 (dib_int[2], DIB[2]); + buf b_dib_3 (dib_int[3], DIB[3]); + buf b_dib_4 (dib_int[4], DIB[4]); + buf b_dib_5 (dib_int[5], DIB[5]); + buf b_dib_6 (dib_int[6], DIB[6]); + buf b_dib_7 (dib_int[7], DIB[7]); + buf b_dipb_0 (dipb_int[0], DIPB[0]); + buf b_enb (enb_int, ENB); + buf b_clkb (clkb_int, CLKB); + buf b_ssrb (ssrb_int, SSRB); + buf b_web (web_int, WEB); + + initial begin + for (count = 0; count < 256; count = count + 1) begin + mem[count] <= INIT_00[count]; + mem[256 * 1 + count] <= INIT_01[count]; + mem[256 * 2 + count] <= INIT_02[count]; + mem[256 * 3 + count] <= INIT_03[count]; + mem[256 * 4 + count] <= INIT_04[count]; + mem[256 * 5 + count] <= INIT_05[count]; + mem[256 * 6 + count] <= INIT_06[count]; + mem[256 * 7 + count] <= INIT_07[count]; + mem[256 * 8 + count] <= INIT_08[count]; + mem[256 * 9 + count] <= INIT_09[count]; + mem[256 * 10 + count] <= INIT_0A[count]; + mem[256 * 11 + count] <= INIT_0B[count]; + mem[256 * 12 + count] <= INIT_0C[count]; + mem[256 * 13 + count] <= INIT_0D[count]; + mem[256 * 14 + count] <= INIT_0E[count]; + mem[256 * 15 + count] <= INIT_0F[count]; + mem[256 * 16 + count] <= INIT_10[count]; + mem[256 * 17 + count] <= INIT_11[count]; + mem[256 * 18 + count] <= INIT_12[count]; + mem[256 * 19 + count] <= INIT_13[count]; + mem[256 * 20 + count] <= INIT_14[count]; + mem[256 * 21 + count] <= INIT_15[count]; + mem[256 * 22 + count] <= INIT_16[count]; + mem[256 * 23 + count] <= INIT_17[count]; + mem[256 * 24 + count] <= INIT_18[count]; + mem[256 * 25 + count] <= INIT_19[count]; + mem[256 * 26 + count] <= INIT_1A[count]; + mem[256 * 27 + count] <= INIT_1B[count]; + mem[256 * 28 + count] <= INIT_1C[count]; + mem[256 * 29 + count] <= INIT_1D[count]; + mem[256 * 30 + count] <= INIT_1E[count]; + mem[256 * 31 + count] <= INIT_1F[count]; + mem[256 * 32 + count] <= INIT_20[count]; + mem[256 * 33 + count] <= INIT_21[count]; + mem[256 * 34 + count] <= INIT_22[count]; + mem[256 * 35 + count] <= INIT_23[count]; + mem[256 * 36 + count] <= INIT_24[count]; + mem[256 * 37 + count] <= INIT_25[count]; + mem[256 * 38 + count] <= INIT_26[count]; + mem[256 * 39 + count] <= INIT_27[count]; + mem[256 * 40 + count] <= INIT_28[count]; + mem[256 * 41 + count] <= INIT_29[count]; + mem[256 * 42 + count] <= INIT_2A[count]; + mem[256 * 43 + count] <= INIT_2B[count]; + mem[256 * 44 + count] <= INIT_2C[count]; + mem[256 * 45 + count] <= INIT_2D[count]; + mem[256 * 46 + count] <= INIT_2E[count]; + mem[256 * 47 + count] <= INIT_2F[count]; + mem[256 * 48 + count] <= INIT_30[count]; + mem[256 * 49 + count] <= INIT_31[count]; + mem[256 * 50 + count] <= INIT_32[count]; + mem[256 * 51 + count] <= INIT_33[count]; + mem[256 * 52 + count] <= INIT_34[count]; + mem[256 * 53 + count] <= INIT_35[count]; + mem[256 * 54 + count] <= INIT_36[count]; + mem[256 * 55 + count] <= INIT_37[count]; + mem[256 * 56 + count] <= INIT_38[count]; + mem[256 * 57 + count] <= INIT_39[count]; + mem[256 * 58 + count] <= INIT_3A[count]; + mem[256 * 59 + count] <= INIT_3B[count]; + mem[256 * 60 + count] <= INIT_3C[count]; + mem[256 * 61 + count] <= INIT_3D[count]; + mem[256 * 62 + count] <= INIT_3E[count]; + mem[256 * 63 + count] <= INIT_3F[count]; + mem[256 * 64 + count] <= INITP_00[count]; + mem[256 * 65 + count] <= INITP_01[count]; + mem[256 * 66 + count] <= INITP_02[count]; + mem[256 * 67 + count] <= INITP_03[count]; + mem[256 * 68 + count] <= INITP_04[count]; + mem[256 * 69 + count] <= INITP_05[count]; + mem[256 * 70 + count] <= INITP_06[count]; + mem[256 * 71 + count] <= INITP_07[count]; + end + address_collision <= 0; + address_collision_a_b <= 0; + address_collision_b_a <= 0; + change_clka <= 0; + change_clkb <= 0; + data_collision <= 0; + data_collision_a_b <= 0; + data_collision_b_a <= 0; + memory_collision <= 0; + memory_collision_a_b <= 0; + memory_collision_b_a <= 0; + setup_all_a_b <= 0; + setup_all_b_a <= 0; + setup_zero <= 0; + setup_rf_a_b <= 0; + setup_rf_b_a <= 0; + end + + assign data_addra_int = addra_int * 4; + assign data_addra_reg = addra_reg * 4; + assign data_addrb_int = addrb_int * 8; + assign data_addrb_reg = addrb_reg * 8; + assign parity_addrb_int = 16384 + addrb_int * 1; + assign parity_addrb_reg = 16384 + addrb_reg * 1; + + + initial begin + + display_flag = 1; + + case (SIM_COLLISION_CHECK) + + "NONE" : begin + assign setup_all_a_b = 1'b0; + assign setup_all_b_a = 1'b0; + assign setup_zero = 1'b0; + assign setup_rf_a_b = 1'b0; + assign setup_rf_b_a = 1'b0; + assign display_flag = 0; + end + "WARNING_ONLY" : begin + assign data_collision = 2'b00; + assign data_collision_a_b = 2'b00; + assign data_collision_b_a = 2'b00; + assign memory_collision = 1'b0; + assign memory_collision_a_b = 1'b0; + assign memory_collision_b_a = 1'b0; + end + "GENERATE_X_ONLY" : begin + assign display_flag = 0; + end + "ALL" : ; + default : begin + $display("Attribute Syntax Error : The Attribute SIM_COLLISION_CHECK on RAMB16_S4_S9 instance %m is set to %s. Legal values for this attribute are ALL, NONE, WARNING_ONLY or GENERATE_X_ONLY.", SIM_COLLISION_CHECK); + $finish; + end + + endcase // case(SIM_COLLISION_CHECK) + + end // initial begin + + + always @(posedge clka_int) begin + time_clka = $time; + #0 time_clkb_clka = time_clka - time_clkb; + change_clka = ~change_clka; + end + + always @(posedge clkb_int) begin + time_clkb = $time; + #0 time_clka_clkb = time_clkb - time_clka; + change_clkb = ~change_clkb; + end + + always @(change_clkb) begin + if ((0 < time_clka_clkb) && (time_clka_clkb < SETUP_ALL)) + setup_all_a_b = 1; + if ((0 < time_clka_clkb) && (time_clka_clkb < SETUP_READ_FIRST)) + setup_rf_a_b = 1; + end + + always @(change_clka) begin + if ((0 < time_clkb_clka) && (time_clkb_clka < SETUP_ALL)) + setup_all_b_a = 1; + if ((0 < time_clkb_clka) && (time_clkb_clka < SETUP_READ_FIRST)) + setup_rf_b_a = 1; + end + + always @(change_clkb or change_clka) begin + if ((time_clkb_clka == 0) && (time_clka_clkb == 0)) + setup_zero = 1; + end + + always @(posedge setup_zero) begin + if ((ena_int == 1) && (wea_int == 1) && + (enb_int == 1) && (web_int == 1) && + (data_addra_int[14:3] == data_addrb_int[14:3])) + memory_collision <= 1; + end + + always @(posedge setup_all_a_b or posedge setup_rf_a_b) begin + if ((ena_reg == 1) && (wea_reg == 1) && + (enb_int == 1) && (web_int == 1) && + (data_addra_reg[14:3] == data_addrb_int[14:3])) + memory_collision_a_b <= 1; + end + + always @(posedge setup_all_b_a or posedge setup_rf_b_a) begin + if ((ena_int == 1) && (wea_int == 1) && + (enb_reg == 1) && (web_reg == 1) && + (data_addra_int[14:3] == data_addrb_reg[14:3])) + memory_collision_b_a <= 1; + end + + always @(posedge setup_all_a_b) begin + if (data_addra_reg[14:3] == data_addrb_int[14:3]) begin + if ((ena_reg == 1) && (enb_int == 1)) begin + case ({wr_mode_a, wr_mode_b, wea_reg, web_int}) + 6'b000011 : begin data_collision_a_b <= 2'b11; display_wa_wb; end + 6'b000111 : begin data_collision_a_b <= 2'b11; display_wa_wb; end + 6'b001011 : begin data_collision_a_b <= 2'b10; display_wa_wb; end +// 6'b010011 : begin data_collision_a_b <= 2'b00; display_wa_wb; end +// 6'b010111 : begin data_collision_a_b <= 2'b00; display_wa_wb; end +// 6'b011011 : begin data_collision_a_b <= 2'b00; display_wa_wb; end + 6'b100011 : begin data_collision_a_b <= 2'b01; display_wa_wb; end + 6'b100111 : begin data_collision_a_b <= 2'b01; display_wa_wb; end + 6'b101011 : begin display_wa_wb; end + 6'b000001 : begin data_collision_a_b <= 2'b10; display_ra_wb; end +// 6'b000101 : begin data_collision_a_b <= 2'b00; display_ra_wb; end + 6'b001001 : begin data_collision_a_b <= 2'b10; display_ra_wb; end + 6'b010001 : begin data_collision_a_b <= 2'b10; display_ra_wb; end +// 6'b010101 : begin data_collision_a_b <= 2'b00; display_ra_wb; end + 6'b011001 : begin data_collision_a_b <= 2'b10; display_ra_wb; end + 6'b100001 : begin data_collision_a_b <= 2'b10; display_ra_wb; end +// 6'b100101 : begin data_collision_a_b <= 2'b00; display_ra_wb; end + 6'b101001 : begin data_collision_a_b <= 2'b10; display_ra_wb; end + 6'b000010 : begin data_collision_a_b <= 2'b01; display_wa_rb; end + 6'b000110 : begin data_collision_a_b <= 2'b01; display_wa_rb; end + 6'b001010 : begin data_collision_a_b <= 2'b01; display_wa_rb; end +// 6'b010010 : begin data_collision_a_b <= 2'b00; display_wa_rb; end +// 6'b010110 : begin data_collision_a_b <= 2'b00; display_wa_rb; end +// 6'b011010 : begin data_collision_a_b <= 2'b00; display_wa_rb; end + 6'b100010 : begin data_collision_a_b <= 2'b01; display_wa_rb; end + 6'b100110 : begin data_collision_a_b <= 2'b01; display_wa_rb; end + 6'b101010 : begin data_collision_a_b <= 2'b01; display_wa_rb; end + endcase + end + end + setup_all_a_b <= 0; + end + + + always @(posedge setup_all_b_a) begin + if (data_addra_int[14:3] == data_addrb_reg[14:3]) begin + if ((ena_int == 1) && (enb_reg == 1)) begin + case ({wr_mode_a, wr_mode_b, wea_int, web_reg}) + 6'b000011 : begin data_collision_b_a <= 2'b11; display_wa_wb; end +// 6'b000111 : begin data_collision_b_a <= 2'b00; display_wa_wb; end + 6'b001011 : begin data_collision_b_a <= 2'b10; display_wa_wb; end + 6'b010011 : begin data_collision_b_a <= 2'b11; display_wa_wb; end +// 6'b010111 : begin data_collision_b_a <= 2'b00; display_wa_wb; end + 6'b011011 : begin data_collision_b_a <= 2'b10; display_wa_wb; end + 6'b100011 : begin data_collision_b_a <= 2'b01; display_wa_wb; end + 6'b100111 : begin data_collision_b_a <= 2'b01; display_wa_wb; end + 6'b101011 : begin display_wa_wb; end + 6'b000001 : begin data_collision_b_a <= 2'b10; display_ra_wb; end + 6'b000101 : begin data_collision_b_a <= 2'b10; display_ra_wb; end + 6'b001001 : begin data_collision_b_a <= 2'b10; display_ra_wb; end + 6'b010001 : begin data_collision_b_a <= 2'b10; display_ra_wb; end + 6'b010101 : begin data_collision_b_a <= 2'b10; display_ra_wb; end + 6'b011001 : begin data_collision_b_a <= 2'b10; display_ra_wb; end + 6'b100001 : begin data_collision_b_a <= 2'b10; display_ra_wb; end + 6'b100101 : begin data_collision_b_a <= 2'b10; display_ra_wb; end + 6'b101001 : begin data_collision_b_a <= 2'b10; display_ra_wb; end + 6'b000010 : begin data_collision_b_a <= 2'b01; display_wa_rb; end + 6'b000110 : begin data_collision_b_a <= 2'b01; display_wa_rb; end + 6'b001010 : begin data_collision_b_a <= 2'b01; display_wa_rb; end +// 6'b010010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end +// 6'b010110 : begin data_collision_b_a <= 2'b00; display_wa_rb; end +// 6'b011010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end + 6'b100010 : begin data_collision_b_a <= 2'b01; display_wa_rb; end + 6'b100110 : begin data_collision_b_a <= 2'b01; display_wa_rb; end + 6'b101010 : begin data_collision_b_a <= 2'b01; display_wa_rb; end + endcase + end + end + setup_all_b_a <= 0; + end + + + always @(posedge setup_zero) begin + if (data_addra_int[14:3] == data_addrb_int[14:3]) begin + if ((ena_int == 1) && (enb_int == 1)) begin + case ({wr_mode_a, wr_mode_b, wea_int, web_int}) + 6'b000011 : begin data_collision <= 2'b11; display_wa_wb; end + 6'b000111 : begin data_collision <= 2'b11; display_wa_wb; end + 6'b001011 : begin data_collision <= 2'b10; display_wa_wb; end + 6'b010011 : begin data_collision <= 2'b11; display_wa_wb; end + 6'b010111 : begin data_collision <= 2'b11; display_wa_wb; end + 6'b011011 : begin data_collision <= 2'b10; display_wa_wb; end + 6'b100011 : begin data_collision <= 2'b01; display_wa_wb; end + 6'b100111 : begin data_collision <= 2'b01; display_wa_wb; end + 6'b101011 : begin display_wa_wb; end + 6'b000001 : begin data_collision <= 2'b10; display_ra_wb; end +// 6'b000101 : begin data_collision <= 2'b00; display_ra_wb; end + 6'b001001 : begin data_collision <= 2'b10; display_ra_wb; end + 6'b010001 : begin data_collision <= 2'b10; display_ra_wb; end +// 6'b010101 : begin data_collision <= 2'b00; display_ra_wb; end + 6'b011001 : begin data_collision <= 2'b10; display_ra_wb; end + 6'b100001 : begin data_collision <= 2'b10; display_ra_wb; end +// 6'b100101 : begin data_collision <= 2'b00; display_ra_wb; end + 6'b101001 : begin data_collision <= 2'b10; display_ra_wb; end + 6'b000010 : begin data_collision <= 2'b01; display_wa_rb; end + 6'b000110 : begin data_collision <= 2'b01; display_wa_rb; end + 6'b001010 : begin data_collision <= 2'b01; display_wa_rb; end +// 6'b010010 : begin data_collision <= 2'b00; display_wa_rb; end +// 6'b010110 : begin data_collision <= 2'b00; display_wa_rb; end +// 6'b011010 : begin data_collision <= 2'b00; display_wa_rb; end + 6'b100010 : begin data_collision <= 2'b01; display_wa_rb; end + 6'b100110 : begin data_collision <= 2'b01; display_wa_rb; end + 6'b101010 : begin data_collision <= 2'b01; display_wa_rb; end + endcase + end + end + setup_zero <= 0; + end + + task display_ra_wb; + begin + if (display_flag) + $display("Memory Collision Error on RAMB16_S4_S9:%m at simulation time %.3f ns\nA read was performed on address %h (hex) of Port A while a write was requested to the same address on Port B. The write will be successful however the read value on Port A is unknown until the next CLKA cycle.", $time/1000.0, addra_int); + end + endtask + + task display_wa_rb; + begin + if (display_flag) + $display("Memory Collision Error on RAMB16_S4_S9:%m at simulation time %.3f ns\nA read was performed on address %h (hex) of Port B while a write was requested to the same address on Port A. The write will be successful however the read value on Port B is unknown until the next CLKB cycle.", $time/1000.0, addrb_int); + end + endtask + + task display_wa_wb; + begin + if (display_flag) + $display("Memory Collision Error on RAMB16_S4_S9:%m at simulation time %.3f ns\nA write was requested to the same address simultaneously at both Port A and Port B of the RAM. The contents written to the RAM at address location %h (hex) of Port A and address location %h (hex) of Port B are unknown.", $time/1000.0, addra_int, addrb_int); + end + endtask + + + always @(posedge setup_rf_a_b) begin + if (data_addra_reg[14:3] == data_addrb_int[14:3]) begin + if ((ena_reg == 1) && (enb_int == 1)) begin + case ({wr_mode_a, wr_mode_b, wea_reg, web_int}) +// 6'b000011 : begin data_collision_a_b <= 2'b00; display_wa_wb; end +// 6'b000111 : begin data_collision_a_b <= 2'b00; display_wa_wb; end +// 6'b001011 : begin data_collision_a_b <= 2'b00; display_wa_wb; end + 6'b010011 : begin data_collision_a_b <= 2'b11; display_wa_wb; end + 6'b010111 : begin data_collision_a_b <= 2'b11; display_wa_wb; end + 6'b011011 : begin data_collision_a_b <= 2'b10; display_wa_wb; end +// 6'b100011 : begin data_collision_a_b <= 2'b00; display_wa_wb; end +// 6'b100111 : begin data_collision_a_b <= 2'b00; display_wa_wb; end +// 6'b101011 : begin data_collision_a_b <= 2'b00; display_wa_wb; end +// 6'b000001 : begin data_collision_a_b <= 2'b00; display_ra_wb; end +// 6'b000101 : begin data_collision_a_b <= 2'b00; display_ra_wb; end +// 6'b001001 : begin data_collision_a_b <= 2'b00; display_ra_wb; end +// 6'b010001 : begin data_collision_a_b <= 2'b00; display_ra_wb; end +// 6'b010101 : begin data_collision_a_b <= 2'b00; display_ra_wb; end +// 6'b011001 : begin data_collision_a_b <= 2'b00; display_ra_wb; end +// 6'b100001 : begin data_collision_a_b <= 2'b00; display_ra_wb; end +// 6'b100101 : begin data_collision_a_b <= 2'b00; display_ra_wb; end +// 6'b101001 : begin data_collision_a_b <= 2'b00; display_ra_wb; end +// 6'b000010 : begin data_collision_a_b <= 2'b00; display_wa_rb; end +// 6'b000110 : begin data_collision_a_b <= 2'b00; display_wa_rb; end +// 6'b001010 : begin data_collision_a_b <= 2'b00; display_wa_rb; end + 6'b010010 : begin data_collision_a_b <= 2'b01; display_wa_rb; end + 6'b010110 : begin data_collision_a_b <= 2'b01; display_wa_rb; end + 6'b011010 : begin data_collision_a_b <= 2'b01; display_wa_rb; end +// 6'b100010 : begin data_collision_a_b <= 2'b00; display_wa_rb; end +// 6'b100110 : begin data_collision_a_b <= 2'b00; display_wa_rb; end +// 6'b101010 : begin data_collision_a_b <= 2'b00; display_wa_rb; end + endcase + end + end + setup_rf_a_b <= 0; + end + + + always @(posedge setup_rf_b_a) begin + if (data_addra_int[14:3] == data_addrb_reg[14:3]) begin + if ((ena_int == 1) && (enb_reg == 1)) begin + case ({wr_mode_a, wr_mode_b, wea_int, web_reg}) +// 6'b000011 : begin data_collision_b_a <= 2'b00; display_wa_wb; end + 6'b000111 : begin data_collision_b_a <= 2'b11; display_wa_wb; end +// 6'b001011 : begin data_collision_b_a <= 2'b00; display_wa_wb; end +// 6'b010011 : begin data_collision_b_a <= 2'b00; display_wa_wb; end + 6'b010111 : begin data_collision_b_a <= 2'b11; display_wa_wb; end +// 6'b011011 : begin data_collision_b_a <= 2'b00; display_wa_wb; end +// 6'b100011 : begin data_collision_b_a <= 2'b00; display_wa_wb; end + 6'b100111 : begin data_collision_b_a <= 2'b01; display_wa_wb; end +// 6'b101011 : begin data_collision_b_a <= 2'b00; display_wa_wb; end +// 6'b000001 : begin data_collision_b_a <= 2'b00; display_ra_wb; end + 6'b000101 : begin data_collision_b_a <= 2'b10; display_ra_wb; end +// 6'b001001 : begin data_collision_b_a <= 2'b00; display_ra_wb; end +// 6'b010001 : begin data_collision_b_a <= 2'b00; display_ra_wb; end + 6'b010101 : begin data_collision_b_a <= 2'b10; display_ra_wb; end +// 6'b011001 : begin data_collision_b_a <= 2'b00; display_ra_wb; end +// 6'b100001 : begin data_collision_b_a <= 2'b00; display_ra_wb; end + 6'b100101 : begin data_collision_b_a <= 2'b10; display_ra_wb; end +// 6'b101001 : begin data_collision_b_a <= 2'b00; display_ra_wb; end +// 6'b000010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end +// 6'b000110 : begin data_collision_b_a <= 2'b00; display_wa_rb; end +// 6'b001010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end +// 6'b010010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end +// 6'b010110 : begin data_collision_b_a <= 2'b00; display_wa_rb; end +// 6'b011010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end +// 6'b100010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end +// 6'b100110 : begin data_collision_b_a <= 2'b00; display_wa_rb; end +// 6'b101010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end + endcase + end + end + setup_rf_b_a <= 0; + end + + + always @(posedge clka_int) begin + addra_reg <= addra_int; + ena_reg <= ena_int; + ssra_reg <= ssra_int; + wea_reg <= wea_int; + end + + always @(posedge clkb_int) begin + addrb_reg <= addrb_int; + enb_reg <= enb_int; + ssrb_reg <= ssrb_int; + web_reg <= web_int; + end + + // Data + always @(posedge memory_collision) begin + for (dmi = 0; dmi < 4; dmi = dmi + 1) begin + mem[data_addra_int + dmi] <= 1'bX; + end + memory_collision <= 0; + end + + always @(posedge memory_collision_a_b) begin + for (dmi = 0; dmi < 4; dmi = dmi + 1) begin + mem[data_addra_reg + dmi] <= 1'bX; + end + memory_collision_a_b <= 0; + end + + always @(posedge memory_collision_b_a) begin + for (dmi = 0; dmi < 4; dmi = dmi + 1) begin + mem[data_addra_int + dmi] <= 1'bX; + end + memory_collision_b_a <= 0; + end + + always @(posedge data_collision[1]) begin + if (ssra_int == 0) begin + doa_out <= 4'bX; + end + data_collision[1] <= 0; + end + + always @(posedge data_collision[0]) begin + if (ssrb_int == 0) begin + for (dbi = 0; dbi < 4; dbi = dbi + 1) begin + dob_out[data_addra_int[2 : 0] + dbi] <= 1'bX; + end + end + data_collision[0] <= 0; + end + + always @(posedge data_collision_a_b[1]) begin + if (ssra_reg == 0) begin + doa_out <= 4'bX; + end + data_collision_a_b[1] <= 0; + end + + always @(posedge data_collision_a_b[0]) begin + if (ssrb_int == 0) begin + for (dbi = 0; dbi < 4; dbi = dbi + 1) begin + dob_out[data_addra_reg[2 : 0] + dbi] <= 1'bX; + end + end + data_collision_a_b[0] <= 0; + end + + always @(posedge data_collision_b_a[1]) begin + if (ssra_int == 0) begin + doa_out <= 4'bX; + end + data_collision_b_a[1] <= 0; + end + + always @(posedge data_collision_b_a[0]) begin + if (ssrb_reg == 0) begin + for (dbi = 0; dbi < 4; dbi = dbi + 1) begin + dob_out[data_addra_int[2 : 0] + dbi] <= 1'bX; + end + end + data_collision_b_a[0] <= 0; + end + + + initial begin + case (WRITE_MODE_A) + "WRITE_FIRST" : wr_mode_a <= 2'b00; + "READ_FIRST" : wr_mode_a <= 2'b01; + "NO_CHANGE" : wr_mode_a <= 2'b10; + default : begin + $display("Attribute Syntax Error : The Attribute WRITE_MODE_A on RAMB16_S4_S9 instance %m is set to %s. Legal values for this attribute are WRITE_FIRST, READ_FIRST or NO_CHANGE.", WRITE_MODE_A); + $finish; + end + endcase + end + + initial begin + case (WRITE_MODE_B) + "WRITE_FIRST" : wr_mode_b <= 2'b00; + "READ_FIRST" : wr_mode_b <= 2'b01; + "NO_CHANGE" : wr_mode_b <= 2'b10; + default : begin + $display("Attribute Syntax Error : The Attribute WRITE_MODE_B on RAMB16_S4_S9 instance %m is set to %s. Legal values for this attribute are WRITE_FIRST, READ_FIRST or NO_CHANGE.", WRITE_MODE_B); + $finish; + end + endcase + end + + // Port A + always @(posedge clka_int) begin + if (ena_int == 1'b1) begin + if (ssra_int == 1'b1) begin + doa_out[0] <= SRVAL_A[0]; + doa_out[1] <= SRVAL_A[1]; + doa_out[2] <= SRVAL_A[2]; + doa_out[3] <= SRVAL_A[3]; + end + else begin + if (wea_int == 1'b1) begin + if (wr_mode_a == 2'b00) begin + doa_out <= dia_int; + end + else if (wr_mode_a == 2'b01) begin + doa_out[0] <= mem[data_addra_int + 0]; + doa_out[1] <= mem[data_addra_int + 1]; + doa_out[2] <= mem[data_addra_int + 2]; + doa_out[3] <= mem[data_addra_int + 3]; + end + end + else begin + doa_out[0] <= mem[data_addra_int + 0]; + doa_out[1] <= mem[data_addra_int + 1]; + doa_out[2] <= mem[data_addra_int + 2]; + doa_out[3] <= mem[data_addra_int + 3]; + end + end + end + end + + always @(posedge clka_int) begin + if (ena_int == 1'b1 && wea_int == 1'b1) begin + mem[data_addra_int + 0] <= dia_int[0]; + mem[data_addra_int + 1] <= dia_int[1]; + mem[data_addra_int + 2] <= dia_int[2]; + mem[data_addra_int + 3] <= dia_int[3]; + end + end + + // Port B + always @(posedge clkb_int) begin + if (enb_int == 1'b1) begin + if (ssrb_int == 1'b1) begin + dob_out[0] <= SRVAL_B[0]; + dob_out[1] <= SRVAL_B[1]; + dob_out[2] <= SRVAL_B[2]; + dob_out[3] <= SRVAL_B[3]; + dob_out[4] <= SRVAL_B[4]; + dob_out[5] <= SRVAL_B[5]; + dob_out[6] <= SRVAL_B[6]; + dob_out[7] <= SRVAL_B[7]; + dopb_out[0] <= SRVAL_B[8]; + end + else begin + if (web_int == 1'b1) begin + if (wr_mode_b == 2'b00) begin + dob_out <= dib_int; + dopb_out <= dipb_int; + end + else if (wr_mode_b == 2'b01) begin + dob_out[0] <= mem[data_addrb_int + 0]; + dob_out[1] <= mem[data_addrb_int + 1]; + dob_out[2] <= mem[data_addrb_int + 2]; + dob_out[3] <= mem[data_addrb_int + 3]; + dob_out[4] <= mem[data_addrb_int + 4]; + dob_out[5] <= mem[data_addrb_int + 5]; + dob_out[6] <= mem[data_addrb_int + 6]; + dob_out[7] <= mem[data_addrb_int + 7]; + dopb_out[0] <= mem[parity_addrb_int + 0]; + end + end + else begin + dob_out[0] <= mem[data_addrb_int + 0]; + dob_out[1] <= mem[data_addrb_int + 1]; + dob_out[2] <= mem[data_addrb_int + 2]; + dob_out[3] <= mem[data_addrb_int + 3]; + dob_out[4] <= mem[data_addrb_int + 4]; + dob_out[5] <= mem[data_addrb_int + 5]; + dob_out[6] <= mem[data_addrb_int + 6]; + dob_out[7] <= mem[data_addrb_int + 7]; + dopb_out[0] <= mem[parity_addrb_int + 0]; + end + end + end + end + + always @(posedge clkb_int) begin + if (enb_int == 1'b1 && web_int == 1'b1) begin + mem[data_addrb_int + 0] <= dib_int[0]; + mem[data_addrb_int + 1] <= dib_int[1]; + mem[data_addrb_int + 2] <= dib_int[2]; + mem[data_addrb_int + 3] <= dib_int[3]; + mem[data_addrb_int + 4] <= dib_int[4]; + mem[data_addrb_int + 5] <= dib_int[5]; + mem[data_addrb_int + 6] <= dib_int[6]; + mem[data_addrb_int + 7] <= dib_int[7]; + mem[parity_addrb_int + 0] <= dipb_int[0]; + end + end + + specify + (CLKA *> DOA) = (100, 100); + (CLKB *> DOB) = (100, 100); + (CLKB *> DOPB) = (100, 100); + endspecify + +endmodule + +`else + +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/RAMB16_S4_S9.v,v 1.10 2007/02/22 01:58:06 wloo Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2005 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Timing Simulation Library Component +// / / 16K-Bit Data and 2K-Bit Parity Dual Port Block RAM +// /___/ /\ Filename : RAMB16_S4_S9.v +// \ \ / \ Timestamp : Thu Mar 10 16:44:01 PST 2005 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 03/10/05 - Initialized outputs. +// 02/21/07 - Fixed parameter SIM_COLLISION_CHECK (CR 433281). +// End Revision + +`timescale 1 ps/1 ps + +module RAMB16_S4_S9 (DOA, DOB, DOPB, ADDRA, ADDRB, CLKA, CLKB, DIA, DIB, DIPB, ENA, ENB, SSRA, SSRB, WEA, WEB); + + parameter INIT_A = 4'h0; + parameter INIT_B = 9'h0; + parameter SRVAL_A = 4'h0; + parameter SRVAL_B = 9'h0; + parameter WRITE_MODE_A = "WRITE_FIRST"; + parameter WRITE_MODE_B = "WRITE_FIRST"; + parameter SIM_COLLISION_CHECK = "ALL"; + localparam SETUP_ALL = 1000; + localparam SETUP_READ_FIRST = 3000; + + parameter INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + + output [3:0] DOA; + output [7:0] DOB; + output [0:0] DOPB; + + input [11:0] ADDRA; + input [3:0] DIA; + input ENA, CLKA, WEA, SSRA; + input [10:0] ADDRB; + input [7:0] DIB; + input [0:0] DIPB; + input ENB, CLKB, WEB, SSRB; + + reg [3:0] doa_out = INIT_A[3:0]; + reg [7:0] dob_out = INIT_B[7:0]; + reg [0:0] dopb_out = INIT_B[8:8]; + + reg [7:0] mem [2047:0]; + reg [0:0] memp [2047:0]; + + reg [8:0] count, countp; + reg [1:0] wr_mode_a, wr_mode_b; + + reg [5:0] dmi, dbi; + reg [5:0] pmi, pbi; + + wire [11:0] addra_int; + reg [11:0] addra_reg; + wire [3:0] dia_int; + wire ena_int, clka_int, wea_int, ssra_int; + reg ena_reg, wea_reg, ssra_reg; + wire [10:0] addrb_int; + reg [10:0] addrb_reg; + wire [7:0] dib_int; + wire [0:0] dipb_int; + wire enb_int, clkb_int, web_int, ssrb_int; + reg display_flag, output_flag; + reg enb_reg, web_reg, ssrb_reg; + + time time_clka, time_clkb; + time time_clka_clkb; + time time_clkb_clka; + + reg setup_all_a_b; + reg setup_all_b_a; + reg setup_zero; + reg setup_rf_a_b; + reg setup_rf_b_a; + reg [1:0] data_collision, data_collision_a_b, data_collision_b_a; + reg memory_collision, memory_collision_a_b, memory_collision_b_a; + reg change_clka; + reg change_clkb; + + wire [14:0] data_addra_int; + wire [14:0] data_addra_reg; + wire [14:0] data_addrb_int; + wire [14:0] data_addrb_reg; + + wire dia_enable = ena_int && wea_int; + wire dib_enable = enb_int && web_int; + + tri0 GSR = glbl.GSR; + wire gsr_int; + + buf b_gsr (gsr_int, GSR); + + buf b_doa [3:0] (DOA, doa_out); + buf b_addra [11:0] (addra_int, ADDRA); + buf b_dia [3:0] (dia_int, DIA); + buf b_ena (ena_int, ENA); + buf b_clka (clka_int, CLKA); + buf b_ssra (ssra_int, SSRA); + buf b_wea (wea_int, WEA); + + buf b_dob [7:0] (DOB, dob_out); + buf b_dopb [0:0] (DOPB, dopb_out); + buf b_addrb [10:0] (addrb_int, ADDRB); + buf b_dib [7:0] (dib_int, DIB); + buf b_dipb [0:0] (dipb_int, DIPB); + buf b_enb (enb_int, ENB); + buf b_clkb (clkb_int, CLKB); + buf b_ssrb (ssrb_int, SSRB); + buf b_web (web_int, WEB); + + + always @(gsr_int) + if (gsr_int) begin + assign {doa_out} = INIT_A; + assign {dopb_out, dob_out} = INIT_B; + end + else begin + deassign doa_out; + deassign dob_out; + deassign dopb_out; + end + + + initial begin + + for (count = 0; count < 32; count = count + 1) begin + mem[count] = INIT_00[(count * 8) +: 8]; + mem[32 * 1 + count] = INIT_01[(count * 8) +: 8]; + mem[32 * 2 + count] = INIT_02[(count * 8) +: 8]; + mem[32 * 3 + count] = INIT_03[(count * 8) +: 8]; + mem[32 * 4 + count] = INIT_04[(count * 8) +: 8]; + mem[32 * 5 + count] = INIT_05[(count * 8) +: 8]; + mem[32 * 6 + count] = INIT_06[(count * 8) +: 8]; + mem[32 * 7 + count] = INIT_07[(count * 8) +: 8]; + mem[32 * 8 + count] = INIT_08[(count * 8) +: 8]; + mem[32 * 9 + count] = INIT_09[(count * 8) +: 8]; + mem[32 * 10 + count] = INIT_0A[(count * 8) +: 8]; + mem[32 * 11 + count] = INIT_0B[(count * 8) +: 8]; + mem[32 * 12 + count] = INIT_0C[(count * 8) +: 8]; + mem[32 * 13 + count] = INIT_0D[(count * 8) +: 8]; + mem[32 * 14 + count] = INIT_0E[(count * 8) +: 8]; + mem[32 * 15 + count] = INIT_0F[(count * 8) +: 8]; + mem[32 * 16 + count] = INIT_10[(count * 8) +: 8]; + mem[32 * 17 + count] = INIT_11[(count * 8) +: 8]; + mem[32 * 18 + count] = INIT_12[(count * 8) +: 8]; + mem[32 * 19 + count] = INIT_13[(count * 8) +: 8]; + mem[32 * 20 + count] = INIT_14[(count * 8) +: 8]; + mem[32 * 21 + count] = INIT_15[(count * 8) +: 8]; + mem[32 * 22 + count] = INIT_16[(count * 8) +: 8]; + mem[32 * 23 + count] = INIT_17[(count * 8) +: 8]; + mem[32 * 24 + count] = INIT_18[(count * 8) +: 8]; + mem[32 * 25 + count] = INIT_19[(count * 8) +: 8]; + mem[32 * 26 + count] = INIT_1A[(count * 8) +: 8]; + mem[32 * 27 + count] = INIT_1B[(count * 8) +: 8]; + mem[32 * 28 + count] = INIT_1C[(count * 8) +: 8]; + mem[32 * 29 + count] = INIT_1D[(count * 8) +: 8]; + mem[32 * 30 + count] = INIT_1E[(count * 8) +: 8]; + mem[32 * 31 + count] = INIT_1F[(count * 8) +: 8]; + mem[32 * 32 + count] = INIT_20[(count * 8) +: 8]; + mem[32 * 33 + count] = INIT_21[(count * 8) +: 8]; + mem[32 * 34 + count] = INIT_22[(count * 8) +: 8]; + mem[32 * 35 + count] = INIT_23[(count * 8) +: 8]; + mem[32 * 36 + count] = INIT_24[(count * 8) +: 8]; + mem[32 * 37 + count] = INIT_25[(count * 8) +: 8]; + mem[32 * 38 + count] = INIT_26[(count * 8) +: 8]; + mem[32 * 39 + count] = INIT_27[(count * 8) +: 8]; + mem[32 * 40 + count] = INIT_28[(count * 8) +: 8]; + mem[32 * 41 + count] = INIT_29[(count * 8) +: 8]; + mem[32 * 42 + count] = INIT_2A[(count * 8) +: 8]; + mem[32 * 43 + count] = INIT_2B[(count * 8) +: 8]; + mem[32 * 44 + count] = INIT_2C[(count * 8) +: 8]; + mem[32 * 45 + count] = INIT_2D[(count * 8) +: 8]; + mem[32 * 46 + count] = INIT_2E[(count * 8) +: 8]; + mem[32 * 47 + count] = INIT_2F[(count * 8) +: 8]; + mem[32 * 48 + count] = INIT_30[(count * 8) +: 8]; + mem[32 * 49 + count] = INIT_31[(count * 8) +: 8]; + mem[32 * 50 + count] = INIT_32[(count * 8) +: 8]; + mem[32 * 51 + count] = INIT_33[(count * 8) +: 8]; + mem[32 * 52 + count] = INIT_34[(count * 8) +: 8]; + mem[32 * 53 + count] = INIT_35[(count * 8) +: 8]; + mem[32 * 54 + count] = INIT_36[(count * 8) +: 8]; + mem[32 * 55 + count] = INIT_37[(count * 8) +: 8]; + mem[32 * 56 + count] = INIT_38[(count * 8) +: 8]; + mem[32 * 57 + count] = INIT_39[(count * 8) +: 8]; + mem[32 * 58 + count] = INIT_3A[(count * 8) +: 8]; + mem[32 * 59 + count] = INIT_3B[(count * 8) +: 8]; + mem[32 * 60 + count] = INIT_3C[(count * 8) +: 8]; + mem[32 * 61 + count] = INIT_3D[(count * 8) +: 8]; + mem[32 * 62 + count] = INIT_3E[(count * 8) +: 8]; + mem[32 * 63 + count] = INIT_3F[(count * 8) +: 8]; + end + +// initiate parity start + for (countp = 0; countp < 256; countp = countp + 1) begin + memp[countp] = INITP_00[(countp * 1) +: 1]; + memp[256 * 1 + countp] = INITP_01[(countp * 1) +: 1]; + memp[256 * 2 + countp] = INITP_02[(countp * 1) +: 1]; + memp[256 * 3 + countp] = INITP_03[(countp * 1) +: 1]; + memp[256 * 4 + countp] = INITP_04[(countp * 1) +: 1]; + memp[256 * 5 + countp] = INITP_05[(countp * 1) +: 1]; + memp[256 * 6 + countp] = INITP_06[(countp * 1) +: 1]; + memp[256 * 7 + countp] = INITP_07[(countp * 1) +: 1]; + end +// initiate parity end + + change_clka <= 0; + change_clkb <= 0; + data_collision <= 0; + data_collision_a_b <= 0; + data_collision_b_a <= 0; + memory_collision <= 0; + memory_collision_a_b <= 0; + memory_collision_b_a <= 0; + setup_all_a_b <= 0; + setup_all_b_a <= 0; + setup_zero <= 0; + setup_rf_a_b <= 0; + setup_rf_b_a <= 0; + end + + assign data_addra_int = addra_int * 4; + assign data_addra_reg = addra_reg * 4; + assign data_addrb_int = addrb_int * 8; + assign data_addrb_reg = addrb_reg * 8; + + + initial begin + + display_flag = 1; + output_flag = 1; + + case (SIM_COLLISION_CHECK) + + "NONE" : begin + output_flag = 0; + display_flag = 0; + end + "WARNING_ONLY" : output_flag = 0; + "GENERATE_X_ONLY" : display_flag = 0; + "ALL" : ; + + default : begin + $display("Attribute Syntax Error : The Attribute SIM_COLLISION_CHECK on RAMB16_S4_S9 instance %m is set to %s. Legal values for this attribute are ALL, NONE, WARNING_ONLY or GENERATE_X_ONLY.", SIM_COLLISION_CHECK); + $finish; + end + + endcase // case(SIM_COLLISION_CHECK) + + end // initial begin + + + always @(posedge clka_int) begin + if ((output_flag || display_flag)) begin + time_clka = $time; + #0 time_clkb_clka = time_clka - time_clkb; + change_clka = ~change_clka; + end + end + + always @(posedge clkb_int) begin + if ((output_flag || display_flag)) begin + time_clkb = $time; + #0 time_clka_clkb = time_clkb - time_clka; + change_clkb = ~change_clkb; + end + end + + always @(change_clkb) begin + if ((0 < time_clka_clkb) && (time_clka_clkb < SETUP_ALL)) + setup_all_a_b = 1; + if ((0 < time_clka_clkb) && (time_clka_clkb < SETUP_READ_FIRST)) + setup_rf_a_b = 1; + end + + always @(change_clka) begin + if ((0 < time_clkb_clka) && (time_clkb_clka < SETUP_ALL)) + setup_all_b_a = 1; + if ((0 < time_clkb_clka) && (time_clkb_clka < SETUP_READ_FIRST)) + setup_rf_b_a = 1; + end + + always @(change_clkb or change_clka) begin + if ((time_clkb_clka == 0) && (time_clka_clkb == 0)) + setup_zero = 1; + end + + always @(posedge setup_zero) begin + if ((ena_int == 1) && (wea_int == 1) && + (enb_int == 1) && (web_int == 1) && + (data_addra_int[14:3] == data_addrb_int[14:3])) + memory_collision <= 1; + end + + always @(posedge setup_all_a_b or posedge setup_rf_a_b) begin + if ((ena_reg == 1) && (wea_reg == 1) && + (enb_int == 1) && (web_int == 1) && + (data_addra_reg[14:3] == data_addrb_int[14:3])) + memory_collision_a_b <= 1; + end + + always @(posedge setup_all_b_a or posedge setup_rf_b_a) begin + if ((ena_int == 1) && (wea_int == 1) && + (enb_reg == 1) && (web_reg == 1) && + (data_addra_int[14:3] == data_addrb_reg[14:3])) + memory_collision_b_a <= 1; + end + + always @(posedge setup_all_a_b) begin + if (data_addra_reg[14:3] == data_addrb_int[14:3]) begin + if ((ena_reg == 1) && (enb_int == 1)) begin + case ({wr_mode_a, wr_mode_b, wea_reg, web_int}) + 6'b000011 : begin data_collision_a_b <= 2'b11; display_wa_wb; end + 6'b000111 : begin data_collision_a_b <= 2'b11; display_wa_wb; end + 6'b001011 : begin data_collision_a_b <= 2'b10; display_wa_wb; end +// 6'b010011 : begin data_collision_a_b <= 2'b00; display_wa_wb; end +// 6'b010111 : begin data_collision_a_b <= 2'b00; display_wa_wb; end +// 6'b011011 : begin data_collision_a_b <= 2'b00; display_wa_wb; end + 6'b100011 : begin data_collision_a_b <= 2'b01; display_wa_wb; end + 6'b100111 : begin data_collision_a_b <= 2'b01; display_wa_wb; end + 6'b101011 : begin display_wa_wb; end + 6'b000001 : begin data_collision_a_b <= 2'b10; display_ra_wb; end +// 6'b000101 : begin data_collision_a_b <= 2'b00; display_ra_wb; end + 6'b001001 : begin data_collision_a_b <= 2'b10; display_ra_wb; end + 6'b010001 : begin data_collision_a_b <= 2'b10; display_ra_wb; end +// 6'b010101 : begin data_collision_a_b <= 2'b00; display_ra_wb; end + 6'b011001 : begin data_collision_a_b <= 2'b10; display_ra_wb; end + 6'b100001 : begin data_collision_a_b <= 2'b10; display_ra_wb; end +// 6'b100101 : begin data_collision_a_b <= 2'b00; display_ra_wb; end + 6'b101001 : begin data_collision_a_b <= 2'b10; display_ra_wb; end + 6'b000010 : begin data_collision_a_b <= 2'b01; display_wa_rb; end + 6'b000110 : begin data_collision_a_b <= 2'b01; display_wa_rb; end + 6'b001010 : begin data_collision_a_b <= 2'b01; display_wa_rb; end +// 6'b010010 : begin data_collision_a_b <= 2'b00; display_wa_rb; end +// 6'b010110 : begin data_collision_a_b <= 2'b00; display_wa_rb; end +// 6'b011010 : begin data_collision_a_b <= 2'b00; display_wa_rb; end + 6'b100010 : begin data_collision_a_b <= 2'b01; display_wa_rb; end + 6'b100110 : begin data_collision_a_b <= 2'b01; display_wa_rb; end + 6'b101010 : begin data_collision_a_b <= 2'b01; display_wa_rb; end + endcase + end + end + setup_all_a_b <= 0; + end + + + always @(posedge setup_all_b_a) begin + if (data_addra_int[14:3] == data_addrb_reg[14:3]) begin + if ((ena_int == 1) && (enb_reg == 1)) begin + case ({wr_mode_a, wr_mode_b, wea_int, web_reg}) + 6'b000011 : begin data_collision_b_a <= 2'b11; display_wa_wb; end +// 6'b000111 : begin data_collision_b_a <= 2'b00; display_wa_wb; end + 6'b001011 : begin data_collision_b_a <= 2'b10; display_wa_wb; end + 6'b010011 : begin data_collision_b_a <= 2'b11; display_wa_wb; end +// 6'b010111 : begin data_collision_b_a <= 2'b00; display_wa_wb; end + 6'b011011 : begin data_collision_b_a <= 2'b10; display_wa_wb; end + 6'b100011 : begin data_collision_b_a <= 2'b01; display_wa_wb; end + 6'b100111 : begin data_collision_b_a <= 2'b01; display_wa_wb; end + 6'b101011 : begin display_wa_wb; end + 6'b000001 : begin data_collision_b_a <= 2'b10; display_ra_wb; end + 6'b000101 : begin data_collision_b_a <= 2'b10; display_ra_wb; end + 6'b001001 : begin data_collision_b_a <= 2'b10; display_ra_wb; end + 6'b010001 : begin data_collision_b_a <= 2'b10; display_ra_wb; end + 6'b010101 : begin data_collision_b_a <= 2'b10; display_ra_wb; end + 6'b011001 : begin data_collision_b_a <= 2'b10; display_ra_wb; end + 6'b100001 : begin data_collision_b_a <= 2'b10; display_ra_wb; end + 6'b100101 : begin data_collision_b_a <= 2'b10; display_ra_wb; end + 6'b101001 : begin data_collision_b_a <= 2'b10; display_ra_wb; end + 6'b000010 : begin data_collision_b_a <= 2'b01; display_wa_rb; end + 6'b000110 : begin data_collision_b_a <= 2'b01; display_wa_rb; end + 6'b001010 : begin data_collision_b_a <= 2'b01; display_wa_rb; end +// 6'b010010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end +// 6'b010110 : begin data_collision_b_a <= 2'b00; display_wa_rb; end +// 6'b011010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end + 6'b100010 : begin data_collision_b_a <= 2'b01; display_wa_rb; end + 6'b100110 : begin data_collision_b_a <= 2'b01; display_wa_rb; end + 6'b101010 : begin data_collision_b_a <= 2'b01; display_wa_rb; end + endcase + end + end + setup_all_b_a <= 0; + end + + + always @(posedge setup_zero) begin + if (data_addra_int[14:3] == data_addrb_int[14:3]) begin + if ((ena_int == 1) && (enb_int == 1)) begin + case ({wr_mode_a, wr_mode_b, wea_int, web_int}) + 6'b000011 : begin data_collision <= 2'b11; display_wa_wb; end + 6'b000111 : begin data_collision <= 2'b11; display_wa_wb; end + 6'b001011 : begin data_collision <= 2'b10; display_wa_wb; end + 6'b010011 : begin data_collision <= 2'b11; display_wa_wb; end + 6'b010111 : begin data_collision <= 2'b11; display_wa_wb; end + 6'b011011 : begin data_collision <= 2'b10; display_wa_wb; end + 6'b100011 : begin data_collision <= 2'b01; display_wa_wb; end + 6'b100111 : begin data_collision <= 2'b01; display_wa_wb; end + 6'b101011 : begin display_wa_wb; end + 6'b000001 : begin data_collision <= 2'b10; display_ra_wb; end +// 6'b000101 : begin data_collision <= 2'b00; display_ra_wb; end + 6'b001001 : begin data_collision <= 2'b10; display_ra_wb; end + 6'b010001 : begin data_collision <= 2'b10; display_ra_wb; end +// 6'b010101 : begin data_collision <= 2'b00; display_ra_wb; end + 6'b011001 : begin data_collision <= 2'b10; display_ra_wb; end + 6'b100001 : begin data_collision <= 2'b10; display_ra_wb; end +// 6'b100101 : begin data_collision <= 2'b00; display_ra_wb; end + 6'b101001 : begin data_collision <= 2'b10; display_ra_wb; end + 6'b000010 : begin data_collision <= 2'b01; display_wa_rb; end + 6'b000110 : begin data_collision <= 2'b01; display_wa_rb; end + 6'b001010 : begin data_collision <= 2'b01; display_wa_rb; end +// 6'b010010 : begin data_collision <= 2'b00; display_wa_rb; end +// 6'b010110 : begin data_collision <= 2'b00; display_wa_rb; end +// 6'b011010 : begin data_collision <= 2'b00; display_wa_rb; end + 6'b100010 : begin data_collision <= 2'b01; display_wa_rb; end + 6'b100110 : begin data_collision <= 2'b01; display_wa_rb; end + 6'b101010 : begin data_collision <= 2'b01; display_wa_rb; end + endcase + end + end + setup_zero <= 0; + end + + task display_ra_wb; + begin + if (display_flag) + $display("Memory Collision Error on RAMB16_S4_S9:%m at simulation time %.3f ns\nA read was performed on address %h (hex) of Port A while a write was requested to the same address on Port B. The write will be successful however the read value on Port A is unknown until the next CLKA cycle.", $time/1000.0, addra_int); + end + endtask + + task display_wa_rb; + begin + if (display_flag) + $display("Memory Collision Error on RAMB16_S4_S9:%m at simulation time %.3f ns\nA read was performed on address %h (hex) of Port B while a write was requested to the same address on Port A. The write will be successful however the read value on Port B is unknown until the next CLKB cycle.", $time/1000.0, addrb_int); + end + endtask + + task display_wa_wb; + begin + if (display_flag) + $display("Memory Collision Error on RAMB16_S4_S9:%m at simulation time %.3f ns\nA write was requested to the same address simultaneously at both Port A and Port B of the RAM. The contents written to the RAM at address location %h (hex) of Port A and address location %h (hex) of Port B are unknown.", $time/1000.0, addra_int, addrb_int); + end + endtask + + + always @(posedge setup_rf_a_b) begin + if (data_addra_reg[14:3] == data_addrb_int[14:3]) begin + if ((ena_reg == 1) && (enb_int == 1)) begin + case ({wr_mode_a, wr_mode_b, wea_reg, web_int}) +// 6'b000011 : begin data_collision_a_b <= 2'b00; display_wa_wb; end +// 6'b000111 : begin data_collision_a_b <= 2'b00; display_wa_wb; end +// 6'b001011 : begin data_collision_a_b <= 2'b00; display_wa_wb; end + 6'b010011 : begin data_collision_a_b <= 2'b11; display_wa_wb; end + 6'b010111 : begin data_collision_a_b <= 2'b11; display_wa_wb; end + 6'b011011 : begin data_collision_a_b <= 2'b10; display_wa_wb; end +// 6'b100011 : begin data_collision_a_b <= 2'b00; display_wa_wb; end +// 6'b100111 : begin data_collision_a_b <= 2'b00; display_wa_wb; end +// 6'b101011 : begin data_collision_a_b <= 2'b00; display_wa_wb; end +// 6'b000001 : begin data_collision_a_b <= 2'b00; display_ra_wb; end +// 6'b000101 : begin data_collision_a_b <= 2'b00; display_ra_wb; end +// 6'b001001 : begin data_collision_a_b <= 2'b00; display_ra_wb; end +// 6'b010001 : begin data_collision_a_b <= 2'b00; display_ra_wb; end +// 6'b010101 : begin data_collision_a_b <= 2'b00; display_ra_wb; end +// 6'b011001 : begin data_collision_a_b <= 2'b00; display_ra_wb; end +// 6'b100001 : begin data_collision_a_b <= 2'b00; display_ra_wb; end +// 6'b100101 : begin data_collision_a_b <= 2'b00; display_ra_wb; end +// 6'b101001 : begin data_collision_a_b <= 2'b00; display_ra_wb; end +// 6'b000010 : begin data_collision_a_b <= 2'b00; display_wa_rb; end +// 6'b000110 : begin data_collision_a_b <= 2'b00; display_wa_rb; end +// 6'b001010 : begin data_collision_a_b <= 2'b00; display_wa_rb; end + 6'b010010 : begin data_collision_a_b <= 2'b01; display_wa_rb; end + 6'b010110 : begin data_collision_a_b <= 2'b01; display_wa_rb; end + 6'b011010 : begin data_collision_a_b <= 2'b01; display_wa_rb; end +// 6'b100010 : begin data_collision_a_b <= 2'b00; display_wa_rb; end +// 6'b100110 : begin data_collision_a_b <= 2'b00; display_wa_rb; end +// 6'b101010 : begin data_collision_a_b <= 2'b00; display_wa_rb; end + endcase + end + end + setup_rf_a_b <= 0; + end + + + always @(posedge setup_rf_b_a) begin + if (data_addra_int[14:3] == data_addrb_reg[14:3]) begin + if ((ena_int == 1) && (enb_reg == 1)) begin + case ({wr_mode_a, wr_mode_b, wea_int, web_reg}) +// 6'b000011 : begin data_collision_b_a <= 2'b00; display_wa_wb; end + 6'b000111 : begin data_collision_b_a <= 2'b11; display_wa_wb; end +// 6'b001011 : begin data_collision_b_a <= 2'b00; display_wa_wb; end +// 6'b010011 : begin data_collision_b_a <= 2'b00; display_wa_wb; end + 6'b010111 : begin data_collision_b_a <= 2'b11; display_wa_wb; end +// 6'b011011 : begin data_collision_b_a <= 2'b00; display_wa_wb; end +// 6'b100011 : begin data_collision_b_a <= 2'b00; display_wa_wb; end + 6'b100111 : begin data_collision_b_a <= 2'b01; display_wa_wb; end +// 6'b101011 : begin data_collision_b_a <= 2'b00; display_wa_wb; end +// 6'b000001 : begin data_collision_b_a <= 2'b00; display_ra_wb; end + 6'b000101 : begin data_collision_b_a <= 2'b10; display_ra_wb; end +// 6'b001001 : begin data_collision_b_a <= 2'b00; display_ra_wb; end +// 6'b010001 : begin data_collision_b_a <= 2'b00; display_ra_wb; end + 6'b010101 : begin data_collision_b_a <= 2'b10; display_ra_wb; end +// 6'b011001 : begin data_collision_b_a <= 2'b00; display_ra_wb; end +// 6'b100001 : begin data_collision_b_a <= 2'b00; display_ra_wb; end + 6'b100101 : begin data_collision_b_a <= 2'b10; display_ra_wb; end +// 6'b101001 : begin data_collision_b_a <= 2'b00; display_ra_wb; end +// 6'b000010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end +// 6'b000110 : begin data_collision_b_a <= 2'b00; display_wa_rb; end +// 6'b001010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end +// 6'b010010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end +// 6'b010110 : begin data_collision_b_a <= 2'b00; display_wa_rb; end +// 6'b011010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end +// 6'b100010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end +// 6'b100110 : begin data_collision_b_a <= 2'b00; display_wa_rb; end +// 6'b101010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end + endcase + end + end + setup_rf_b_a <= 0; + end + + + always @(posedge clka_int) begin + if ((output_flag || display_flag)) begin + addra_reg <= addra_int; + ena_reg <= ena_int; + ssra_reg <= ssra_int; + wea_reg <= wea_int; + end + end + + always @(posedge clkb_int) begin + if ((output_flag || display_flag)) begin + addrb_reg <= addrb_int; + enb_reg <= enb_int; + ssrb_reg <= ssrb_int; + web_reg <= web_int; + end + end + + + // Data + always @(posedge memory_collision) begin + if ((output_flag || display_flag)) begin + mem[addra_int[11:1]][addra_int[0:0] * 4 +: 4] <= 4'bx; + memory_collision <= 0; + end + + end + + always @(posedge memory_collision_a_b) begin + if ((output_flag || display_flag)) begin + mem[addra_reg[11:1]][addra_reg[0:0] * 4 +: 4] <= 4'bx; + memory_collision_a_b <= 0; + end + end + + always @(posedge memory_collision_b_a) begin + if ((output_flag || display_flag)) begin + mem[addra_int[11:1]][addra_int[0:0] * 4 +: 4] <= 4'bx; + memory_collision_b_a <= 0; + end + end + + always @(posedge data_collision[1]) begin + if (ssra_int == 0 && output_flag) begin + doa_out <= #100 4'bX; + end + data_collision[1] <= 0; + end + + always @(posedge data_collision[0]) begin + if (ssrb_int == 0 && output_flag) begin + dob_out[addra_int[0:0] * 4 +: 4] <= #100 4'bX; + end + data_collision[0] <= 0; + end + + always @(posedge data_collision_a_b[1]) begin + if (ssra_reg == 0 && output_flag) begin + doa_out <= #100 4'bX; + end + data_collision_a_b[1] <= 0; + end + + always @(posedge data_collision_a_b[0]) begin + if (ssrb_int == 0 && output_flag) begin + dob_out[addra_reg[0:0] * 4 +: 4] <= #100 4'bX; + end + data_collision_a_b[0] <= 0; + end + + always @(posedge data_collision_b_a[1]) begin + if (ssra_int == 0 && output_flag) begin + doa_out <= #100 4'bX; + end + data_collision_b_a[1] <= 0; + end + + always @(posedge data_collision_b_a[0]) begin + if (ssrb_reg == 0 && output_flag) begin + dob_out[addra_int[0:0] * 4 +: 4] <= #100 4'bX; + end + data_collision_b_a[0] <= 0; + end + + + initial begin + case (WRITE_MODE_A) + "WRITE_FIRST" : wr_mode_a <= 2'b00; + "READ_FIRST" : wr_mode_a <= 2'b01; + "NO_CHANGE" : wr_mode_a <= 2'b10; + default : begin + $display("Attribute Syntax Error : The Attribute WRITE_MODE_A on RAMB16_S4_S9 instance %m is set to %s. Legal values for this attribute are WRITE_FIRST, READ_FIRST or NO_CHANGE.", WRITE_MODE_A); + $finish; + end + endcase + end + + initial begin + case (WRITE_MODE_B) + "WRITE_FIRST" : wr_mode_b <= 2'b00; + "READ_FIRST" : wr_mode_b <= 2'b01; + "NO_CHANGE" : wr_mode_b <= 2'b10; + default : begin + $display("Attribute Syntax Error : The Attribute WRITE_MODE_B on RAMB16_S4_S9 instance %m is set to %s. Legal values for this attribute are WRITE_FIRST, READ_FIRST or NO_CHANGE.", WRITE_MODE_B); + $finish; + end + endcase + end + + + // Port A + always @(posedge clka_int) begin + + if (ena_int == 1'b1) begin + + if (ssra_int == 1'b1) begin + {doa_out} <= #100 SRVAL_A; + end + else begin + if (wea_int == 1'b1) begin + if (wr_mode_a == 2'b00) begin + doa_out <= #100 dia_int; + end + else if (wr_mode_a == 2'b01) begin + + doa_out <= #100 mem[addra_int[11:1]][addra_int[0:0] * 4 +: 4]; + + end + end + else begin + + doa_out <= #100 mem[addra_int[11:1]][addra_int[0:0] * 4 +: 4]; + + end + end + + // memory + if (wea_int == 1'b1) begin + mem[addra_int[11:1]][addra_int[0:0] * 4 +: 4] <= dia_int; + end + + end + end + + + // Port B + always @(posedge clkb_int) begin + + if (enb_int == 1'b1) begin + + if (ssrb_int == 1'b1) begin + {dopb_out, dob_out} <= #100 SRVAL_B; + end + else begin + if (web_int == 1'b1) begin + if (wr_mode_b == 2'b00) begin + dob_out <= #100 dib_int; + dopb_out <= #100 dipb_int; + end + else if (wr_mode_b == 2'b01) begin + dob_out <= #100 mem[addrb_int]; + dopb_out <= #100 memp[addrb_int]; + end + end + else begin + dob_out <= #100 mem[addrb_int]; + dopb_out <= #100 memp[addrb_int]; + end + end + + // memory + if (web_int == 1'b1) begin + mem[addrb_int] <= dib_int; + memp[addrb_int] <= dipb_int; + end + + end + end + + +endmodule + +`endif diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/RAMB16_S9.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/RAMB16_S9.v new file mode 100644 index 0000000..77f0d29 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/RAMB16_S9.v @@ -0,0 +1,642 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/RAMB16_S9.v,v 1.6 2005/03/14 22:54:41 wloo Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2005 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / 16K-Bit Data and 2K-Bit Parity Single Port Block RAM +// /___/ /\ Filename : RAMB16_S9.v +// \ \ / \ Timestamp : Thu Mar 10 16:43:37 PST 2005 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// End Revision + +`ifdef legacy_model + +`timescale 1 ps / 1 ps + +module RAMB16_S9 (DO, DOP, ADDR, CLK, DI, DIP, EN, SSR, WE); + + parameter INIT = 9'h0; + parameter SRVAL = 9'h0; + parameter WRITE_MODE = "WRITE_FIRST"; + + parameter INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + + output [7:0] DO; + output [0:0] DOP; + reg do0_out, do1_out, do2_out, do3_out, do4_out, do5_out, do6_out, do7_out; + reg dop0_out; + + input [10:0] ADDR; + input [7:0] DI; + input [0:0] DIP; + input EN, CLK, WE, SSR; + + reg [18431:0] mem; + reg [8:0] count; + reg [1:0] wr_mode; + + wire [10:0] addr_int; + wire [7:0] di_int; + wire [0:0] dip_int; + wire en_int, clk_int, we_int, ssr_int; + + tri0 GSR = glbl.GSR; + + always @(GSR) + if (GSR) begin + assign do0_out = INIT[0]; + assign do1_out = INIT[1]; + assign do2_out = INIT[2]; + assign do3_out = INIT[3]; + assign do4_out = INIT[4]; + assign do5_out = INIT[5]; + assign do6_out = INIT[6]; + assign do7_out = INIT[7]; + assign dop0_out = INIT[8]; + end + else begin + deassign do0_out; + deassign do1_out; + deassign do2_out; + deassign do3_out; + deassign do4_out; + deassign do5_out; + deassign do6_out; + deassign do7_out; + deassign dop0_out; + end + + buf b_do_out0 (DO[0], do0_out); + buf b_do_out1 (DO[1], do1_out); + buf b_do_out2 (DO[2], do2_out); + buf b_do_out3 (DO[3], do3_out); + buf b_do_out4 (DO[4], do4_out); + buf b_do_out5 (DO[5], do5_out); + buf b_do_out6 (DO[6], do6_out); + buf b_do_out7 (DO[7], do7_out); + buf b_dop_out0 (DOP[0], dop0_out); + buf b_addr_0 (addr_int[0], ADDR[0]); + buf b_addr_1 (addr_int[1], ADDR[1]); + buf b_addr_2 (addr_int[2], ADDR[2]); + buf b_addr_3 (addr_int[3], ADDR[3]); + buf b_addr_4 (addr_int[4], ADDR[4]); + buf b_addr_5 (addr_int[5], ADDR[5]); + buf b_addr_6 (addr_int[6], ADDR[6]); + buf b_addr_7 (addr_int[7], ADDR[7]); + buf b_addr_8 (addr_int[8], ADDR[8]); + buf b_addr_9 (addr_int[9], ADDR[9]); + buf b_addr_10 (addr_int[10], ADDR[10]); + buf b_di_0 (di_int[0], DI[0]); + buf b_di_1 (di_int[1], DI[1]); + buf b_di_2 (di_int[2], DI[2]); + buf b_di_3 (di_int[3], DI[3]); + buf b_di_4 (di_int[4], DI[4]); + buf b_di_5 (di_int[5], DI[5]); + buf b_di_6 (di_int[6], DI[6]); + buf b_di_7 (di_int[7], DI[7]); + buf b_dip_0 (dip_int[0], DIP[0]); + buf b_en (en_int, EN); + buf b_clk (clk_int, CLK); + buf b_we (we_int, WE); + buf b_ssr (ssr_int, SSR); + + initial begin + for (count = 0; count < 256; count = count + 1) begin + mem[count] <= INIT_00[count]; + mem[256 * 1 + count] <= INIT_01[count]; + mem[256 * 2 + count] <= INIT_02[count]; + mem[256 * 3 + count] <= INIT_03[count]; + mem[256 * 4 + count] <= INIT_04[count]; + mem[256 * 5 + count] <= INIT_05[count]; + mem[256 * 6 + count] <= INIT_06[count]; + mem[256 * 7 + count] <= INIT_07[count]; + mem[256 * 8 + count] <= INIT_08[count]; + mem[256 * 9 + count] <= INIT_09[count]; + mem[256 * 10 + count] <= INIT_0A[count]; + mem[256 * 11 + count] <= INIT_0B[count]; + mem[256 * 12 + count] <= INIT_0C[count]; + mem[256 * 13 + count] <= INIT_0D[count]; + mem[256 * 14 + count] <= INIT_0E[count]; + mem[256 * 15 + count] <= INIT_0F[count]; + mem[256 * 16 + count] <= INIT_10[count]; + mem[256 * 17 + count] <= INIT_11[count]; + mem[256 * 18 + count] <= INIT_12[count]; + mem[256 * 19 + count] <= INIT_13[count]; + mem[256 * 20 + count] <= INIT_14[count]; + mem[256 * 21 + count] <= INIT_15[count]; + mem[256 * 22 + count] <= INIT_16[count]; + mem[256 * 23 + count] <= INIT_17[count]; + mem[256 * 24 + count] <= INIT_18[count]; + mem[256 * 25 + count] <= INIT_19[count]; + mem[256 * 26 + count] <= INIT_1A[count]; + mem[256 * 27 + count] <= INIT_1B[count]; + mem[256 * 28 + count] <= INIT_1C[count]; + mem[256 * 29 + count] <= INIT_1D[count]; + mem[256 * 30 + count] <= INIT_1E[count]; + mem[256 * 31 + count] <= INIT_1F[count]; + mem[256 * 32 + count] <= INIT_20[count]; + mem[256 * 33 + count] <= INIT_21[count]; + mem[256 * 34 + count] <= INIT_22[count]; + mem[256 * 35 + count] <= INIT_23[count]; + mem[256 * 36 + count] <= INIT_24[count]; + mem[256 * 37 + count] <= INIT_25[count]; + mem[256 * 38 + count] <= INIT_26[count]; + mem[256 * 39 + count] <= INIT_27[count]; + mem[256 * 40 + count] <= INIT_28[count]; + mem[256 * 41 + count] <= INIT_29[count]; + mem[256 * 42 + count] <= INIT_2A[count]; + mem[256 * 43 + count] <= INIT_2B[count]; + mem[256 * 44 + count] <= INIT_2C[count]; + mem[256 * 45 + count] <= INIT_2D[count]; + mem[256 * 46 + count] <= INIT_2E[count]; + mem[256 * 47 + count] <= INIT_2F[count]; + mem[256 * 48 + count] <= INIT_30[count]; + mem[256 * 49 + count] <= INIT_31[count]; + mem[256 * 50 + count] <= INIT_32[count]; + mem[256 * 51 + count] <= INIT_33[count]; + mem[256 * 52 + count] <= INIT_34[count]; + mem[256 * 53 + count] <= INIT_35[count]; + mem[256 * 54 + count] <= INIT_36[count]; + mem[256 * 55 + count] <= INIT_37[count]; + mem[256 * 56 + count] <= INIT_38[count]; + mem[256 * 57 + count] <= INIT_39[count]; + mem[256 * 58 + count] <= INIT_3A[count]; + mem[256 * 59 + count] <= INIT_3B[count]; + mem[256 * 60 + count] <= INIT_3C[count]; + mem[256 * 61 + count] <= INIT_3D[count]; + mem[256 * 62 + count] <= INIT_3E[count]; + mem[256 * 63 + count] <= INIT_3F[count]; + mem[256 * 64 + count] <= INITP_00[count]; + mem[256 * 65 + count] <= INITP_01[count]; + mem[256 * 66 + count] <= INITP_02[count]; + mem[256 * 67 + count] <= INITP_03[count]; + mem[256 * 68 + count] <= INITP_04[count]; + mem[256 * 69 + count] <= INITP_05[count]; + mem[256 * 70 + count] <= INITP_06[count]; + mem[256 * 71 + count] <= INITP_07[count]; + end + end + + initial begin + case (WRITE_MODE) + "WRITE_FIRST" : wr_mode <= 2'b00; + "READ_FIRST" : wr_mode <= 2'b01; + "NO_CHANGE" : wr_mode <= 2'b10; + default : begin + $display("Attribute Syntax Error : The attribute WRITE_MODE on RAMB16_S9 instance %m is set to %s. The legal values for this attribute are WRITE_FIRST, READ_FIRST or NO_CHANGE.", WRITE_MODE); + $finish; + end + endcase + end + + always @(posedge clk_int) begin + if (en_int == 1'b1) begin + if (ssr_int == 1'b1) begin + do0_out <= SRVAL[0]; + do1_out <= SRVAL[1]; + do2_out <= SRVAL[2]; + do3_out <= SRVAL[3]; + do4_out <= SRVAL[4]; + do5_out <= SRVAL[5]; + do6_out <= SRVAL[6]; + do7_out <= SRVAL[7]; + dop0_out <= SRVAL[8]; + end + else begin + if (we_int == 1'b1) begin + if (wr_mode == 2'b00) begin + do0_out <= di_int[0]; + do1_out <= di_int[1]; + do2_out <= di_int[2]; + do3_out <= di_int[3]; + do4_out <= di_int[4]; + do5_out <= di_int[5]; + do6_out <= di_int[6]; + do7_out <= di_int[7]; + dop0_out <= dip_int[0]; + end + else if (wr_mode == 2'b01) begin + do0_out <= mem[addr_int * 8 + 0]; + do1_out <= mem[addr_int * 8 + 1]; + do2_out <= mem[addr_int * 8 + 2]; + do3_out <= mem[addr_int * 8 + 3]; + do4_out <= mem[addr_int * 8 + 4]; + do5_out <= mem[addr_int * 8 + 5]; + do6_out <= mem[addr_int * 8 + 6]; + do7_out <= mem[addr_int * 8 + 7]; + dop0_out <= mem[16384 + addr_int * 1 + 0]; + end + else begin + do0_out <= do0_out; + do1_out <= do1_out; + do2_out <= do2_out; + do3_out <= do3_out; + do4_out <= do4_out; + do5_out <= do5_out; + do6_out <= do6_out; + do7_out <= do7_out; + dop0_out <= dop0_out; + end + end + else begin + do0_out <= mem[addr_int * 8 + 0]; + do1_out <= mem[addr_int * 8 + 1]; + do2_out <= mem[addr_int * 8 + 2]; + do3_out <= mem[addr_int * 8 + 3]; + do4_out <= mem[addr_int * 8 + 4]; + do5_out <= mem[addr_int * 8 + 5]; + do6_out <= mem[addr_int * 8 + 6]; + do7_out <= mem[addr_int * 8 + 7]; + dop0_out <= mem[16384 + addr_int * 1 + 0]; + end + end + end + end + + always @(posedge clk_int) begin + if (en_int == 1'b1 && we_int == 1'b1) begin + mem[addr_int * 8 + 0] <= di_int[0]; + mem[addr_int * 8 + 1] <= di_int[1]; + mem[addr_int * 8 + 2] <= di_int[2]; + mem[addr_int * 8 + 3] <= di_int[3]; + mem[addr_int * 8 + 4] <= di_int[4]; + mem[addr_int * 8 + 5] <= di_int[5]; + mem[addr_int * 8 + 6] <= di_int[6]; + mem[addr_int * 8 + 7] <= di_int[7]; + mem[16384 + addr_int * 1 + 0] <= dip_int[0]; + end + end + + specify + (CLK *> DO) = (100, 100); + (CLK *> DOP) = (100, 100); + endspecify + +endmodule + +`else + +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/RAMB16_S9.v,v 1.6 2005/03/14 22:54:41 wloo Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2005 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Timing Simulation Library Component +// / / 16K-Bit Data and 2K-Bit Parity Single Port Block RAM +// /___/ /\ Filename : RAMB16_S9.v +// \ \ / \ Timestamp : Thu Mar 10 16:44:01 PST 2005 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 03/10/05 - Initialized outputs. +// End Revision + +`timescale 1 ps/1 ps + +module RAMB16_S9 (DO, DOP, ADDR, CLK, DI, DIP, EN, SSR, WE); + + parameter INIT = 9'h0; + parameter SRVAL = 9'h0; + parameter WRITE_MODE = "WRITE_FIRST"; + + parameter INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + + output [7:0] DO; + output [0:0] DOP; + + input [10:0] ADDR; + input [7:0] DI; + input [0:0] DIP; + input EN, CLK, WE, SSR; + + reg [7:0] do_out = INIT[7:0]; + reg [0:0] dop_out = INIT[8:8]; + + reg [7:0] mem [2047:0]; + reg [0:0] memp [2047:0]; + + reg [8:0] count, countp; + reg [1:0] wr_mode; + + wire [10:0] addr_int; + wire [7:0] di_int; + wire [0:0] dip_int; + wire en_int, clk_int, we_int, ssr_int; + + wire di_enable = en_int && we_int; + + tri0 GSR = glbl.GSR; + wire gsr_int; + + buf b_gsr (gsr_int, GSR); + + buf b_do [7:0] (DO, do_out); + buf b_dop [0:0] (DOP, dop_out); + buf b_addr [10:0] (addr_int, ADDR); + buf b_di [7:0] (di_int, DI); + buf b_dip [0:0] (dip_int, DIP); + buf b_en (en_int, EN); + buf b_clk (clk_int, CLK); + buf b_ssr (ssr_int, SSR); + buf b_we (we_int, WE); + + + always @(gsr_int) + if (gsr_int) begin + assign {dop_out, do_out} = INIT; + end + else begin + deassign do_out; + deassign dop_out; + end + + + initial begin + + for (count = 0; count < 32; count = count + 1) begin + mem[count] = INIT_00[(count * 8) +: 8]; + mem[32 * 1 + count] = INIT_01[(count * 8) +: 8]; + mem[32 * 2 + count] = INIT_02[(count * 8) +: 8]; + mem[32 * 3 + count] = INIT_03[(count * 8) +: 8]; + mem[32 * 4 + count] = INIT_04[(count * 8) +: 8]; + mem[32 * 5 + count] = INIT_05[(count * 8) +: 8]; + mem[32 * 6 + count] = INIT_06[(count * 8) +: 8]; + mem[32 * 7 + count] = INIT_07[(count * 8) +: 8]; + mem[32 * 8 + count] = INIT_08[(count * 8) +: 8]; + mem[32 * 9 + count] = INIT_09[(count * 8) +: 8]; + mem[32 * 10 + count] = INIT_0A[(count * 8) +: 8]; + mem[32 * 11 + count] = INIT_0B[(count * 8) +: 8]; + mem[32 * 12 + count] = INIT_0C[(count * 8) +: 8]; + mem[32 * 13 + count] = INIT_0D[(count * 8) +: 8]; + mem[32 * 14 + count] = INIT_0E[(count * 8) +: 8]; + mem[32 * 15 + count] = INIT_0F[(count * 8) +: 8]; + mem[32 * 16 + count] = INIT_10[(count * 8) +: 8]; + mem[32 * 17 + count] = INIT_11[(count * 8) +: 8]; + mem[32 * 18 + count] = INIT_12[(count * 8) +: 8]; + mem[32 * 19 + count] = INIT_13[(count * 8) +: 8]; + mem[32 * 20 + count] = INIT_14[(count * 8) +: 8]; + mem[32 * 21 + count] = INIT_15[(count * 8) +: 8]; + mem[32 * 22 + count] = INIT_16[(count * 8) +: 8]; + mem[32 * 23 + count] = INIT_17[(count * 8) +: 8]; + mem[32 * 24 + count] = INIT_18[(count * 8) +: 8]; + mem[32 * 25 + count] = INIT_19[(count * 8) +: 8]; + mem[32 * 26 + count] = INIT_1A[(count * 8) +: 8]; + mem[32 * 27 + count] = INIT_1B[(count * 8) +: 8]; + mem[32 * 28 + count] = INIT_1C[(count * 8) +: 8]; + mem[32 * 29 + count] = INIT_1D[(count * 8) +: 8]; + mem[32 * 30 + count] = INIT_1E[(count * 8) +: 8]; + mem[32 * 31 + count] = INIT_1F[(count * 8) +: 8]; + mem[32 * 32 + count] = INIT_20[(count * 8) +: 8]; + mem[32 * 33 + count] = INIT_21[(count * 8) +: 8]; + mem[32 * 34 + count] = INIT_22[(count * 8) +: 8]; + mem[32 * 35 + count] = INIT_23[(count * 8) +: 8]; + mem[32 * 36 + count] = INIT_24[(count * 8) +: 8]; + mem[32 * 37 + count] = INIT_25[(count * 8) +: 8]; + mem[32 * 38 + count] = INIT_26[(count * 8) +: 8]; + mem[32 * 39 + count] = INIT_27[(count * 8) +: 8]; + mem[32 * 40 + count] = INIT_28[(count * 8) +: 8]; + mem[32 * 41 + count] = INIT_29[(count * 8) +: 8]; + mem[32 * 42 + count] = INIT_2A[(count * 8) +: 8]; + mem[32 * 43 + count] = INIT_2B[(count * 8) +: 8]; + mem[32 * 44 + count] = INIT_2C[(count * 8) +: 8]; + mem[32 * 45 + count] = INIT_2D[(count * 8) +: 8]; + mem[32 * 46 + count] = INIT_2E[(count * 8) +: 8]; + mem[32 * 47 + count] = INIT_2F[(count * 8) +: 8]; + mem[32 * 48 + count] = INIT_30[(count * 8) +: 8]; + mem[32 * 49 + count] = INIT_31[(count * 8) +: 8]; + mem[32 * 50 + count] = INIT_32[(count * 8) +: 8]; + mem[32 * 51 + count] = INIT_33[(count * 8) +: 8]; + mem[32 * 52 + count] = INIT_34[(count * 8) +: 8]; + mem[32 * 53 + count] = INIT_35[(count * 8) +: 8]; + mem[32 * 54 + count] = INIT_36[(count * 8) +: 8]; + mem[32 * 55 + count] = INIT_37[(count * 8) +: 8]; + mem[32 * 56 + count] = INIT_38[(count * 8) +: 8]; + mem[32 * 57 + count] = INIT_39[(count * 8) +: 8]; + mem[32 * 58 + count] = INIT_3A[(count * 8) +: 8]; + mem[32 * 59 + count] = INIT_3B[(count * 8) +: 8]; + mem[32 * 60 + count] = INIT_3C[(count * 8) +: 8]; + mem[32 * 61 + count] = INIT_3D[(count * 8) +: 8]; + mem[32 * 62 + count] = INIT_3E[(count * 8) +: 8]; + mem[32 * 63 + count] = INIT_3F[(count * 8) +: 8]; + end + +// initiate parity start + for (countp = 0; countp < 256; countp = countp + 1) begin + memp[countp] = INITP_00[(countp * 1) +: 1]; + memp[256 * 1 + countp] = INITP_01[(countp * 1) +: 1]; + memp[256 * 2 + countp] = INITP_02[(countp * 1) +: 1]; + memp[256 * 3 + countp] = INITP_03[(countp * 1) +: 1]; + memp[256 * 4 + countp] = INITP_04[(countp * 1) +: 1]; + memp[256 * 5 + countp] = INITP_05[(countp * 1) +: 1]; + memp[256 * 6 + countp] = INITP_06[(countp * 1) +: 1]; + memp[256 * 7 + countp] = INITP_07[(countp * 1) +: 1]; + end +// initiate parity end + end // initial begin + + + initial begin + case (WRITE_MODE) + "WRITE_FIRST" : wr_mode <= 2'b00; + "READ_FIRST" : wr_mode <= 2'b01; + "NO_CHANGE" : wr_mode <= 2'b10; + default : begin + $display("Attribute Syntax Error : The Attribute WRITE_MODE on RAMB16_S9 instance %m is set to %s. Legal values for this attribute are WRITE_FIRST, READ_FIRST or NO_CHANGE.", WRITE_MODE); + $finish; + end + endcase + end + + + always @(posedge clk_int) begin + + if (en_int == 1'b1) begin + + if (ssr_int == 1'b1) begin + {dop_out, do_out} <= #100 SRVAL; + end + else begin + if (we_int == 1'b1) begin + if (wr_mode == 2'b00) begin + do_out <= #100 di_int; + dop_out <= #100 dip_int; + end + else if (wr_mode == 2'b01) begin + do_out <= #100 mem[addr_int]; + dop_out <= #100 memp[addr_int]; + end + end + else begin + do_out <= #100 mem[addr_int]; + dop_out <= #100 memp[addr_int]; + end + end + + // memory + if (we_int == 1'b1) begin + mem[addr_int] <= di_int; + memp[addr_int] <= dip_int; + end + + end + end + + +endmodule + +`endif diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/RAMB16_S9_S18.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/RAMB16_S9_S18.v new file mode 100644 index 0000000..a8cee47 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/RAMB16_S9_S18.v @@ -0,0 +1,1894 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/RAMB16_S9_S18.v,v 1.10 2007/02/22 01:58:06 wloo Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2005 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / 16K-Bit Data and 2K-Bit Parity Dual Port Block RAM +// /___/ /\ Filename : RAMB16_S9_S18.v +// \ \ / \ Timestamp : Thu Mar 10 16:43:37 PST 2005 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// End Revision + +`ifdef legacy_model + +`timescale 1 ps / 1 ps + +module RAMB16_S9_S18 (DOA, DOB, DOPA, DOPB, ADDRA, ADDRB, CLKA, CLKB, DIA, DIB, DIPA, DIPB, ENA, ENB, SSRA, SSRB, WEA, WEB); + + parameter INIT_A = 9'h0; + parameter INIT_B = 18'h0; + parameter SRVAL_A = 9'h0; + parameter SRVAL_B = 18'h0; + parameter WRITE_MODE_A = "WRITE_FIRST"; + parameter WRITE_MODE_B = "WRITE_FIRST"; + parameter SIM_COLLISION_CHECK = "ALL"; + localparam SETUP_ALL = 1000; + localparam SETUP_READ_FIRST = 3000; + + parameter INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + + output [7:0] DOA; + output [0:0] DOPA; + reg [7:0] doa_out; + reg [0:0] dopa_out; + wire doa_out0, doa_out1, doa_out2, doa_out3, doa_out4, doa_out5, doa_out6, doa_out7; + wire dopa0_out; + + input [10:0] ADDRA; + input [7:0] DIA; + input [0:0] DIPA; + input ENA, CLKA, WEA, SSRA; + + output [15:0] DOB; + output [1:0] DOPB; + reg [15:0] dob_out; + reg [1:0] dopb_out; + wire dob_out0, dob_out1, dob_out2, dob_out3, dob_out4, dob_out5, dob_out6, dob_out7, dob_out8, dob_out9, dob_out10, dob_out11, dob_out12, dob_out13, dob_out14, dob_out15; + wire dopb0_out, dopb1_out; + + input [9:0] ADDRB; + input [15:0] DIB; + input [1:0] DIPB; + input ENB, CLKB, WEB, SSRB; + + reg [18431:0] mem; + reg [8:0] count; + reg [1:0] wr_mode_a, wr_mode_b; + + reg [5:0] dmi, dbi; + reg [5:0] pmi, pbi; + + wire [10:0] addra_int; + reg [10:0] addra_reg; + wire [7:0] dia_int; + wire [0:0] dipa_int; + wire ena_int, clka_int, wea_int, ssra_int; + reg ena_reg, wea_reg, ssra_reg; + wire [9:0] addrb_int; + reg [9:0] addrb_reg; + wire [15:0] dib_int; + wire [1:0] dipb_int; + wire enb_int, clkb_int, web_int, ssrb_int; + reg display_flag; + reg enb_reg, web_reg, ssrb_reg; + + time time_clka, time_clkb; + time time_clka_clkb; + time time_clkb_clka; + + reg setup_all_a_b; + reg setup_all_b_a; + reg setup_zero; + reg setup_rf_a_b; + reg setup_rf_b_a; + reg [1:0] data_collision, data_collision_a_b, data_collision_b_a; + reg memory_collision, memory_collision_a_b, memory_collision_b_a; + reg address_collision, address_collision_a_b, address_collision_b_a; + reg change_clka; + reg change_clkb; + + wire [14:0] data_addra_int; + wire [14:0] data_addra_reg; + wire [14:0] data_addrb_int; + wire [14:0] data_addrb_reg; + wire [15:0] parity_addra_int; + wire [15:0] parity_addra_reg; + wire [15:0] parity_addrb_int; + wire [15:0] parity_addrb_reg; + + tri0 GSR = glbl.GSR; + + always @(GSR) + if (GSR) begin + assign doa_out = INIT_A[7:0]; + assign dopa_out = INIT_A[8:8]; + assign dob_out = INIT_B[15:0]; + assign dopb_out = INIT_B[17:16]; + end + else begin + deassign doa_out; + deassign dopa_out; + deassign dob_out; + deassign dopb_out; + end + + buf b_doa_out0 (doa_out0, doa_out[0]); + buf b_doa_out1 (doa_out1, doa_out[1]); + buf b_doa_out2 (doa_out2, doa_out[2]); + buf b_doa_out3 (doa_out3, doa_out[3]); + buf b_doa_out4 (doa_out4, doa_out[4]); + buf b_doa_out5 (doa_out5, doa_out[5]); + buf b_doa_out6 (doa_out6, doa_out[6]); + buf b_doa_out7 (doa_out7, doa_out[7]); + buf b_dopa_out0 (dopa_out0, dopa_out[0]); + buf b_dob_out0 (dob_out0, dob_out[0]); + buf b_dob_out1 (dob_out1, dob_out[1]); + buf b_dob_out2 (dob_out2, dob_out[2]); + buf b_dob_out3 (dob_out3, dob_out[3]); + buf b_dob_out4 (dob_out4, dob_out[4]); + buf b_dob_out5 (dob_out5, dob_out[5]); + buf b_dob_out6 (dob_out6, dob_out[6]); + buf b_dob_out7 (dob_out7, dob_out[7]); + buf b_dob_out8 (dob_out8, dob_out[8]); + buf b_dob_out9 (dob_out9, dob_out[9]); + buf b_dob_out10 (dob_out10, dob_out[10]); + buf b_dob_out11 (dob_out11, dob_out[11]); + buf b_dob_out12 (dob_out12, dob_out[12]); + buf b_dob_out13 (dob_out13, dob_out[13]); + buf b_dob_out14 (dob_out14, dob_out[14]); + buf b_dob_out15 (dob_out15, dob_out[15]); + buf b_dopb_out0 (dopb_out0, dopb_out[0]); + buf b_dopb_out1 (dopb_out1, dopb_out[1]); + + buf b_doa0 (DOA[0], doa_out0); + buf b_doa1 (DOA[1], doa_out1); + buf b_doa2 (DOA[2], doa_out2); + buf b_doa3 (DOA[3], doa_out3); + buf b_doa4 (DOA[4], doa_out4); + buf b_doa5 (DOA[5], doa_out5); + buf b_doa6 (DOA[6], doa_out6); + buf b_doa7 (DOA[7], doa_out7); + buf b_dopa0 (DOPA[0], dopa_out0); + buf b_dob0 (DOB[0], dob_out0); + buf b_dob1 (DOB[1], dob_out1); + buf b_dob2 (DOB[2], dob_out2); + buf b_dob3 (DOB[3], dob_out3); + buf b_dob4 (DOB[4], dob_out4); + buf b_dob5 (DOB[5], dob_out5); + buf b_dob6 (DOB[6], dob_out6); + buf b_dob7 (DOB[7], dob_out7); + buf b_dob8 (DOB[8], dob_out8); + buf b_dob9 (DOB[9], dob_out9); + buf b_dob10 (DOB[10], dob_out10); + buf b_dob11 (DOB[11], dob_out11); + buf b_dob12 (DOB[12], dob_out12); + buf b_dob13 (DOB[13], dob_out13); + buf b_dob14 (DOB[14], dob_out14); + buf b_dob15 (DOB[15], dob_out15); + buf b_dopb0 (DOPB[0], dopb_out0); + buf b_dopb1 (DOPB[1], dopb_out1); + + buf b_addra_0 (addra_int[0], ADDRA[0]); + buf b_addra_1 (addra_int[1], ADDRA[1]); + buf b_addra_2 (addra_int[2], ADDRA[2]); + buf b_addra_3 (addra_int[3], ADDRA[3]); + buf b_addra_4 (addra_int[4], ADDRA[4]); + buf b_addra_5 (addra_int[5], ADDRA[5]); + buf b_addra_6 (addra_int[6], ADDRA[6]); + buf b_addra_7 (addra_int[7], ADDRA[7]); + buf b_addra_8 (addra_int[8], ADDRA[8]); + buf b_addra_9 (addra_int[9], ADDRA[9]); + buf b_addra_10 (addra_int[10], ADDRA[10]); + buf b_dia_0 (dia_int[0], DIA[0]); + buf b_dia_1 (dia_int[1], DIA[1]); + buf b_dia_2 (dia_int[2], DIA[2]); + buf b_dia_3 (dia_int[3], DIA[3]); + buf b_dia_4 (dia_int[4], DIA[4]); + buf b_dia_5 (dia_int[5], DIA[5]); + buf b_dia_6 (dia_int[6], DIA[6]); + buf b_dia_7 (dia_int[7], DIA[7]); + buf b_dipa_0 (dipa_int[0], DIPA[0]); + buf b_ena (ena_int, ENA); + buf b_clka (clka_int, CLKA); + buf b_ssra (ssra_int, SSRA); + buf b_wea (wea_int, WEA); + buf b_addrb_0 (addrb_int[0], ADDRB[0]); + buf b_addrb_1 (addrb_int[1], ADDRB[1]); + buf b_addrb_2 (addrb_int[2], ADDRB[2]); + buf b_addrb_3 (addrb_int[3], ADDRB[3]); + buf b_addrb_4 (addrb_int[4], ADDRB[4]); + buf b_addrb_5 (addrb_int[5], ADDRB[5]); + buf b_addrb_6 (addrb_int[6], ADDRB[6]); + buf b_addrb_7 (addrb_int[7], ADDRB[7]); + buf b_addrb_8 (addrb_int[8], ADDRB[8]); + buf b_addrb_9 (addrb_int[9], ADDRB[9]); + buf b_dib_0 (dib_int[0], DIB[0]); + buf b_dib_1 (dib_int[1], DIB[1]); + buf b_dib_2 (dib_int[2], DIB[2]); + buf b_dib_3 (dib_int[3], DIB[3]); + buf b_dib_4 (dib_int[4], DIB[4]); + buf b_dib_5 (dib_int[5], DIB[5]); + buf b_dib_6 (dib_int[6], DIB[6]); + buf b_dib_7 (dib_int[7], DIB[7]); + buf b_dib_8 (dib_int[8], DIB[8]); + buf b_dib_9 (dib_int[9], DIB[9]); + buf b_dib_10 (dib_int[10], DIB[10]); + buf b_dib_11 (dib_int[11], DIB[11]); + buf b_dib_12 (dib_int[12], DIB[12]); + buf b_dib_13 (dib_int[13], DIB[13]); + buf b_dib_14 (dib_int[14], DIB[14]); + buf b_dib_15 (dib_int[15], DIB[15]); + buf b_dipb_0 (dipb_int[0], DIPB[0]); + buf b_dipb_1 (dipb_int[1], DIPB[1]); + buf b_enb (enb_int, ENB); + buf b_clkb (clkb_int, CLKB); + buf b_ssrb (ssrb_int, SSRB); + buf b_web (web_int, WEB); + + initial begin + for (count = 0; count < 256; count = count + 1) begin + mem[count] <= INIT_00[count]; + mem[256 * 1 + count] <= INIT_01[count]; + mem[256 * 2 + count] <= INIT_02[count]; + mem[256 * 3 + count] <= INIT_03[count]; + mem[256 * 4 + count] <= INIT_04[count]; + mem[256 * 5 + count] <= INIT_05[count]; + mem[256 * 6 + count] <= INIT_06[count]; + mem[256 * 7 + count] <= INIT_07[count]; + mem[256 * 8 + count] <= INIT_08[count]; + mem[256 * 9 + count] <= INIT_09[count]; + mem[256 * 10 + count] <= INIT_0A[count]; + mem[256 * 11 + count] <= INIT_0B[count]; + mem[256 * 12 + count] <= INIT_0C[count]; + mem[256 * 13 + count] <= INIT_0D[count]; + mem[256 * 14 + count] <= INIT_0E[count]; + mem[256 * 15 + count] <= INIT_0F[count]; + mem[256 * 16 + count] <= INIT_10[count]; + mem[256 * 17 + count] <= INIT_11[count]; + mem[256 * 18 + count] <= INIT_12[count]; + mem[256 * 19 + count] <= INIT_13[count]; + mem[256 * 20 + count] <= INIT_14[count]; + mem[256 * 21 + count] <= INIT_15[count]; + mem[256 * 22 + count] <= INIT_16[count]; + mem[256 * 23 + count] <= INIT_17[count]; + mem[256 * 24 + count] <= INIT_18[count]; + mem[256 * 25 + count] <= INIT_19[count]; + mem[256 * 26 + count] <= INIT_1A[count]; + mem[256 * 27 + count] <= INIT_1B[count]; + mem[256 * 28 + count] <= INIT_1C[count]; + mem[256 * 29 + count] <= INIT_1D[count]; + mem[256 * 30 + count] <= INIT_1E[count]; + mem[256 * 31 + count] <= INIT_1F[count]; + mem[256 * 32 + count] <= INIT_20[count]; + mem[256 * 33 + count] <= INIT_21[count]; + mem[256 * 34 + count] <= INIT_22[count]; + mem[256 * 35 + count] <= INIT_23[count]; + mem[256 * 36 + count] <= INIT_24[count]; + mem[256 * 37 + count] <= INIT_25[count]; + mem[256 * 38 + count] <= INIT_26[count]; + mem[256 * 39 + count] <= INIT_27[count]; + mem[256 * 40 + count] <= INIT_28[count]; + mem[256 * 41 + count] <= INIT_29[count]; + mem[256 * 42 + count] <= INIT_2A[count]; + mem[256 * 43 + count] <= INIT_2B[count]; + mem[256 * 44 + count] <= INIT_2C[count]; + mem[256 * 45 + count] <= INIT_2D[count]; + mem[256 * 46 + count] <= INIT_2E[count]; + mem[256 * 47 + count] <= INIT_2F[count]; + mem[256 * 48 + count] <= INIT_30[count]; + mem[256 * 49 + count] <= INIT_31[count]; + mem[256 * 50 + count] <= INIT_32[count]; + mem[256 * 51 + count] <= INIT_33[count]; + mem[256 * 52 + count] <= INIT_34[count]; + mem[256 * 53 + count] <= INIT_35[count]; + mem[256 * 54 + count] <= INIT_36[count]; + mem[256 * 55 + count] <= INIT_37[count]; + mem[256 * 56 + count] <= INIT_38[count]; + mem[256 * 57 + count] <= INIT_39[count]; + mem[256 * 58 + count] <= INIT_3A[count]; + mem[256 * 59 + count] <= INIT_3B[count]; + mem[256 * 60 + count] <= INIT_3C[count]; + mem[256 * 61 + count] <= INIT_3D[count]; + mem[256 * 62 + count] <= INIT_3E[count]; + mem[256 * 63 + count] <= INIT_3F[count]; + mem[256 * 64 + count] <= INITP_00[count]; + mem[256 * 65 + count] <= INITP_01[count]; + mem[256 * 66 + count] <= INITP_02[count]; + mem[256 * 67 + count] <= INITP_03[count]; + mem[256 * 68 + count] <= INITP_04[count]; + mem[256 * 69 + count] <= INITP_05[count]; + mem[256 * 70 + count] <= INITP_06[count]; + mem[256 * 71 + count] <= INITP_07[count]; + end + address_collision <= 0; + address_collision_a_b <= 0; + address_collision_b_a <= 0; + change_clka <= 0; + change_clkb <= 0; + data_collision <= 0; + data_collision_a_b <= 0; + data_collision_b_a <= 0; + memory_collision <= 0; + memory_collision_a_b <= 0; + memory_collision_b_a <= 0; + setup_all_a_b <= 0; + setup_all_b_a <= 0; + setup_zero <= 0; + setup_rf_a_b <= 0; + setup_rf_b_a <= 0; + end + + assign data_addra_int = addra_int * 8; + assign data_addra_reg = addra_reg * 8; + assign data_addrb_int = addrb_int * 16; + assign data_addrb_reg = addrb_reg * 16; + assign parity_addra_int = 16384 + addra_int * 1; + assign parity_addra_reg = 16384 + addra_reg * 1; + assign parity_addrb_int = 16384 + addrb_int * 2; + assign parity_addrb_reg = 16384 + addrb_reg * 2; + + + initial begin + + display_flag = 1; + + case (SIM_COLLISION_CHECK) + + "NONE" : begin + assign setup_all_a_b = 1'b0; + assign setup_all_b_a = 1'b0; + assign setup_zero = 1'b0; + assign setup_rf_a_b = 1'b0; + assign setup_rf_b_a = 1'b0; + assign display_flag = 0; + end + "WARNING_ONLY" : begin + assign data_collision = 2'b00; + assign data_collision_a_b = 2'b00; + assign data_collision_b_a = 2'b00; + assign memory_collision = 1'b0; + assign memory_collision_a_b = 1'b0; + assign memory_collision_b_a = 1'b0; + end + "GENERATE_X_ONLY" : begin + assign display_flag = 0; + end + "ALL" : ; + default : begin + $display("Attribute Syntax Error : The Attribute SIM_COLLISION_CHECK on RAMB16_S9_S18 instance %m is set to %s. Legal values for this attribute are ALL, NONE, WARNING_ONLY or GENERATE_X_ONLY.", SIM_COLLISION_CHECK); + $finish; + end + + endcase // case(SIM_COLLISION_CHECK) + + end // initial begin + + + always @(posedge clka_int) begin + time_clka = $time; + #0 time_clkb_clka = time_clka - time_clkb; + change_clka = ~change_clka; + end + + always @(posedge clkb_int) begin + time_clkb = $time; + #0 time_clka_clkb = time_clkb - time_clka; + change_clkb = ~change_clkb; + end + + always @(change_clkb) begin + if ((0 < time_clka_clkb) && (time_clka_clkb < SETUP_ALL)) + setup_all_a_b = 1; + if ((0 < time_clka_clkb) && (time_clka_clkb < SETUP_READ_FIRST)) + setup_rf_a_b = 1; + end + + always @(change_clka) begin + if ((0 < time_clkb_clka) && (time_clkb_clka < SETUP_ALL)) + setup_all_b_a = 1; + if ((0 < time_clkb_clka) && (time_clkb_clka < SETUP_READ_FIRST)) + setup_rf_b_a = 1; + end + + always @(change_clkb or change_clka) begin + if ((time_clkb_clka == 0) && (time_clka_clkb == 0)) + setup_zero = 1; + end + + always @(posedge setup_zero) begin + if ((ena_int == 1) && (wea_int == 1) && + (enb_int == 1) && (web_int == 1) && + (data_addra_int[14:4] == data_addrb_int[14:4])) + memory_collision <= 1; + end + + always @(posedge setup_all_a_b or posedge setup_rf_a_b) begin + if ((ena_reg == 1) && (wea_reg == 1) && + (enb_int == 1) && (web_int == 1) && + (data_addra_reg[14:4] == data_addrb_int[14:4])) + memory_collision_a_b <= 1; + end + + always @(posedge setup_all_b_a or posedge setup_rf_b_a) begin + if ((ena_int == 1) && (wea_int == 1) && + (enb_reg == 1) && (web_reg == 1) && + (data_addra_int[14:4] == data_addrb_reg[14:4])) + memory_collision_b_a <= 1; + end + + always @(posedge setup_all_a_b) begin + if (data_addra_reg[14:4] == data_addrb_int[14:4]) begin + if ((ena_reg == 1) && (enb_int == 1)) begin + case ({wr_mode_a, wr_mode_b, wea_reg, web_int}) + 6'b000011 : begin data_collision_a_b <= 2'b11; display_wa_wb; end + 6'b000111 : begin data_collision_a_b <= 2'b11; display_wa_wb; end + 6'b001011 : begin data_collision_a_b <= 2'b10; display_wa_wb; end +// 6'b010011 : begin data_collision_a_b <= 2'b00; display_wa_wb; end +// 6'b010111 : begin data_collision_a_b <= 2'b00; display_wa_wb; end +// 6'b011011 : begin data_collision_a_b <= 2'b00; display_wa_wb; end + 6'b100011 : begin data_collision_a_b <= 2'b01; display_wa_wb; end + 6'b100111 : begin data_collision_a_b <= 2'b01; display_wa_wb; end + 6'b101011 : begin display_wa_wb; end + 6'b000001 : begin data_collision_a_b <= 2'b10; display_ra_wb; end +// 6'b000101 : begin data_collision_a_b <= 2'b00; display_ra_wb; end + 6'b001001 : begin data_collision_a_b <= 2'b10; display_ra_wb; end + 6'b010001 : begin data_collision_a_b <= 2'b10; display_ra_wb; end +// 6'b010101 : begin data_collision_a_b <= 2'b00; display_ra_wb; end + 6'b011001 : begin data_collision_a_b <= 2'b10; display_ra_wb; end + 6'b100001 : begin data_collision_a_b <= 2'b10; display_ra_wb; end +// 6'b100101 : begin data_collision_a_b <= 2'b00; display_ra_wb; end + 6'b101001 : begin data_collision_a_b <= 2'b10; display_ra_wb; end + 6'b000010 : begin data_collision_a_b <= 2'b01; display_wa_rb; end + 6'b000110 : begin data_collision_a_b <= 2'b01; display_wa_rb; end + 6'b001010 : begin data_collision_a_b <= 2'b01; display_wa_rb; end +// 6'b010010 : begin data_collision_a_b <= 2'b00; display_wa_rb; end +// 6'b010110 : begin data_collision_a_b <= 2'b00; display_wa_rb; end +// 6'b011010 : begin data_collision_a_b <= 2'b00; display_wa_rb; end + 6'b100010 : begin data_collision_a_b <= 2'b01; display_wa_rb; end + 6'b100110 : begin data_collision_a_b <= 2'b01; display_wa_rb; end + 6'b101010 : begin data_collision_a_b <= 2'b01; display_wa_rb; end + endcase + end + end + setup_all_a_b <= 0; + end + + + always @(posedge setup_all_b_a) begin + if (data_addra_int[14:4] == data_addrb_reg[14:4]) begin + if ((ena_int == 1) && (enb_reg == 1)) begin + case ({wr_mode_a, wr_mode_b, wea_int, web_reg}) + 6'b000011 : begin data_collision_b_a <= 2'b11; display_wa_wb; end +// 6'b000111 : begin data_collision_b_a <= 2'b00; display_wa_wb; end + 6'b001011 : begin data_collision_b_a <= 2'b10; display_wa_wb; end + 6'b010011 : begin data_collision_b_a <= 2'b11; display_wa_wb; end +// 6'b010111 : begin data_collision_b_a <= 2'b00; display_wa_wb; end + 6'b011011 : begin data_collision_b_a <= 2'b10; display_wa_wb; end + 6'b100011 : begin data_collision_b_a <= 2'b01; display_wa_wb; end + 6'b100111 : begin data_collision_b_a <= 2'b01; display_wa_wb; end + 6'b101011 : begin display_wa_wb; end + 6'b000001 : begin data_collision_b_a <= 2'b10; display_ra_wb; end + 6'b000101 : begin data_collision_b_a <= 2'b10; display_ra_wb; end + 6'b001001 : begin data_collision_b_a <= 2'b10; display_ra_wb; end + 6'b010001 : begin data_collision_b_a <= 2'b10; display_ra_wb; end + 6'b010101 : begin data_collision_b_a <= 2'b10; display_ra_wb; end + 6'b011001 : begin data_collision_b_a <= 2'b10; display_ra_wb; end + 6'b100001 : begin data_collision_b_a <= 2'b10; display_ra_wb; end + 6'b100101 : begin data_collision_b_a <= 2'b10; display_ra_wb; end + 6'b101001 : begin data_collision_b_a <= 2'b10; display_ra_wb; end + 6'b000010 : begin data_collision_b_a <= 2'b01; display_wa_rb; end + 6'b000110 : begin data_collision_b_a <= 2'b01; display_wa_rb; end + 6'b001010 : begin data_collision_b_a <= 2'b01; display_wa_rb; end +// 6'b010010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end +// 6'b010110 : begin data_collision_b_a <= 2'b00; display_wa_rb; end +// 6'b011010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end + 6'b100010 : begin data_collision_b_a <= 2'b01; display_wa_rb; end + 6'b100110 : begin data_collision_b_a <= 2'b01; display_wa_rb; end + 6'b101010 : begin data_collision_b_a <= 2'b01; display_wa_rb; end + endcase + end + end + setup_all_b_a <= 0; + end + + + always @(posedge setup_zero) begin + if (data_addra_int[14:4] == data_addrb_int[14:4]) begin + if ((ena_int == 1) && (enb_int == 1)) begin + case ({wr_mode_a, wr_mode_b, wea_int, web_int}) + 6'b000011 : begin data_collision <= 2'b11; display_wa_wb; end + 6'b000111 : begin data_collision <= 2'b11; display_wa_wb; end + 6'b001011 : begin data_collision <= 2'b10; display_wa_wb; end + 6'b010011 : begin data_collision <= 2'b11; display_wa_wb; end + 6'b010111 : begin data_collision <= 2'b11; display_wa_wb; end + 6'b011011 : begin data_collision <= 2'b10; display_wa_wb; end + 6'b100011 : begin data_collision <= 2'b01; display_wa_wb; end + 6'b100111 : begin data_collision <= 2'b01; display_wa_wb; end + 6'b101011 : begin display_wa_wb; end + 6'b000001 : begin data_collision <= 2'b10; display_ra_wb; end +// 6'b000101 : begin data_collision <= 2'b00; display_ra_wb; end + 6'b001001 : begin data_collision <= 2'b10; display_ra_wb; end + 6'b010001 : begin data_collision <= 2'b10; display_ra_wb; end +// 6'b010101 : begin data_collision <= 2'b00; display_ra_wb; end + 6'b011001 : begin data_collision <= 2'b10; display_ra_wb; end + 6'b100001 : begin data_collision <= 2'b10; display_ra_wb; end +// 6'b100101 : begin data_collision <= 2'b00; display_ra_wb; end + 6'b101001 : begin data_collision <= 2'b10; display_ra_wb; end + 6'b000010 : begin data_collision <= 2'b01; display_wa_rb; end + 6'b000110 : begin data_collision <= 2'b01; display_wa_rb; end + 6'b001010 : begin data_collision <= 2'b01; display_wa_rb; end +// 6'b010010 : begin data_collision <= 2'b00; display_wa_rb; end +// 6'b010110 : begin data_collision <= 2'b00; display_wa_rb; end +// 6'b011010 : begin data_collision <= 2'b00; display_wa_rb; end + 6'b100010 : begin data_collision <= 2'b01; display_wa_rb; end + 6'b100110 : begin data_collision <= 2'b01; display_wa_rb; end + 6'b101010 : begin data_collision <= 2'b01; display_wa_rb; end + endcase + end + end + setup_zero <= 0; + end + + task display_ra_wb; + begin + if (display_flag) + $display("Memory Collision Error on RAMB16_S9_S18:%m at simulation time %.3f ns\nA read was performed on address %h (hex) of Port A while a write was requested to the same address on Port B. The write will be successful however the read value on Port A is unknown until the next CLKA cycle.", $time/1000.0, addra_int); + end + endtask + + task display_wa_rb; + begin + if (display_flag) + $display("Memory Collision Error on RAMB16_S9_S18:%m at simulation time %.3f ns\nA read was performed on address %h (hex) of Port B while a write was requested to the same address on Port A. The write will be successful however the read value on Port B is unknown until the next CLKB cycle.", $time/1000.0, addrb_int); + end + endtask + + task display_wa_wb; + begin + if (display_flag) + $display("Memory Collision Error on RAMB16_S9_S18:%m at simulation time %.3f ns\nA write was requested to the same address simultaneously at both Port A and Port B of the RAM. The contents written to the RAM at address location %h (hex) of Port A and address location %h (hex) of Port B are unknown.", $time/1000.0, addra_int, addrb_int); + end + endtask + + + always @(posedge setup_rf_a_b) begin + if (data_addra_reg[14:4] == data_addrb_int[14:4]) begin + if ((ena_reg == 1) && (enb_int == 1)) begin + case ({wr_mode_a, wr_mode_b, wea_reg, web_int}) +// 6'b000011 : begin data_collision_a_b <= 2'b00; display_wa_wb; end +// 6'b000111 : begin data_collision_a_b <= 2'b00; display_wa_wb; end +// 6'b001011 : begin data_collision_a_b <= 2'b00; display_wa_wb; end + 6'b010011 : begin data_collision_a_b <= 2'b11; display_wa_wb; end + 6'b010111 : begin data_collision_a_b <= 2'b11; display_wa_wb; end + 6'b011011 : begin data_collision_a_b <= 2'b10; display_wa_wb; end +// 6'b100011 : begin data_collision_a_b <= 2'b00; display_wa_wb; end +// 6'b100111 : begin data_collision_a_b <= 2'b00; display_wa_wb; end +// 6'b101011 : begin data_collision_a_b <= 2'b00; display_wa_wb; end +// 6'b000001 : begin data_collision_a_b <= 2'b00; display_ra_wb; end +// 6'b000101 : begin data_collision_a_b <= 2'b00; display_ra_wb; end +// 6'b001001 : begin data_collision_a_b <= 2'b00; display_ra_wb; end +// 6'b010001 : begin data_collision_a_b <= 2'b00; display_ra_wb; end +// 6'b010101 : begin data_collision_a_b <= 2'b00; display_ra_wb; end +// 6'b011001 : begin data_collision_a_b <= 2'b00; display_ra_wb; end +// 6'b100001 : begin data_collision_a_b <= 2'b00; display_ra_wb; end +// 6'b100101 : begin data_collision_a_b <= 2'b00; display_ra_wb; end +// 6'b101001 : begin data_collision_a_b <= 2'b00; display_ra_wb; end +// 6'b000010 : begin data_collision_a_b <= 2'b00; display_wa_rb; end +// 6'b000110 : begin data_collision_a_b <= 2'b00; display_wa_rb; end +// 6'b001010 : begin data_collision_a_b <= 2'b00; display_wa_rb; end + 6'b010010 : begin data_collision_a_b <= 2'b01; display_wa_rb; end + 6'b010110 : begin data_collision_a_b <= 2'b01; display_wa_rb; end + 6'b011010 : begin data_collision_a_b <= 2'b01; display_wa_rb; end +// 6'b100010 : begin data_collision_a_b <= 2'b00; display_wa_rb; end +// 6'b100110 : begin data_collision_a_b <= 2'b00; display_wa_rb; end +// 6'b101010 : begin data_collision_a_b <= 2'b00; display_wa_rb; end + endcase + end + end + setup_rf_a_b <= 0; + end + + + always @(posedge setup_rf_b_a) begin + if (data_addra_int[14:4] == data_addrb_reg[14:4]) begin + if ((ena_int == 1) && (enb_reg == 1)) begin + case ({wr_mode_a, wr_mode_b, wea_int, web_reg}) +// 6'b000011 : begin data_collision_b_a <= 2'b00; display_wa_wb; end + 6'b000111 : begin data_collision_b_a <= 2'b11; display_wa_wb; end +// 6'b001011 : begin data_collision_b_a <= 2'b00; display_wa_wb; end +// 6'b010011 : begin data_collision_b_a <= 2'b00; display_wa_wb; end + 6'b010111 : begin data_collision_b_a <= 2'b11; display_wa_wb; end +// 6'b011011 : begin data_collision_b_a <= 2'b00; display_wa_wb; end +// 6'b100011 : begin data_collision_b_a <= 2'b00; display_wa_wb; end + 6'b100111 : begin data_collision_b_a <= 2'b01; display_wa_wb; end +// 6'b101011 : begin data_collision_b_a <= 2'b00; display_wa_wb; end +// 6'b000001 : begin data_collision_b_a <= 2'b00; display_ra_wb; end + 6'b000101 : begin data_collision_b_a <= 2'b10; display_ra_wb; end +// 6'b001001 : begin data_collision_b_a <= 2'b00; display_ra_wb; end +// 6'b010001 : begin data_collision_b_a <= 2'b00; display_ra_wb; end + 6'b010101 : begin data_collision_b_a <= 2'b10; display_ra_wb; end +// 6'b011001 : begin data_collision_b_a <= 2'b00; display_ra_wb; end +// 6'b100001 : begin data_collision_b_a <= 2'b00; display_ra_wb; end + 6'b100101 : begin data_collision_b_a <= 2'b10; display_ra_wb; end +// 6'b101001 : begin data_collision_b_a <= 2'b00; display_ra_wb; end +// 6'b000010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end +// 6'b000110 : begin data_collision_b_a <= 2'b00; display_wa_rb; end +// 6'b001010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end +// 6'b010010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end +// 6'b010110 : begin data_collision_b_a <= 2'b00; display_wa_rb; end +// 6'b011010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end +// 6'b100010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end +// 6'b100110 : begin data_collision_b_a <= 2'b00; display_wa_rb; end +// 6'b101010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end + endcase + end + end + setup_rf_b_a <= 0; + end + + + always @(posedge clka_int) begin + addra_reg <= addra_int; + ena_reg <= ena_int; + ssra_reg <= ssra_int; + wea_reg <= wea_int; + end + + always @(posedge clkb_int) begin + addrb_reg <= addrb_int; + enb_reg <= enb_int; + ssrb_reg <= ssrb_int; + web_reg <= web_int; + end + + // Data + always @(posedge memory_collision) begin + for (dmi = 0; dmi < 8; dmi = dmi + 1) begin + mem[data_addra_int + dmi] <= 1'bX; + end + memory_collision <= 0; + end + + always @(posedge memory_collision_a_b) begin + for (dmi = 0; dmi < 8; dmi = dmi + 1) begin + mem[data_addra_reg + dmi] <= 1'bX; + end + memory_collision_a_b <= 0; + end + + always @(posedge memory_collision_b_a) begin + for (dmi = 0; dmi < 8; dmi = dmi + 1) begin + mem[data_addra_int + dmi] <= 1'bX; + end + memory_collision_b_a <= 0; + end + + always @(posedge data_collision[1]) begin + if (ssra_int == 0) begin + doa_out <= 8'bX; + end + data_collision[1] <= 0; + end + + always @(posedge data_collision[0]) begin + if (ssrb_int == 0) begin + for (dbi = 0; dbi < 8; dbi = dbi + 1) begin + dob_out[data_addra_int[3 : 0] + dbi] <= 1'bX; + end + end + data_collision[0] <= 0; + end + + always @(posedge data_collision_a_b[1]) begin + if (ssra_reg == 0) begin + doa_out <= 8'bX; + end + data_collision_a_b[1] <= 0; + end + + always @(posedge data_collision_a_b[0]) begin + if (ssrb_int == 0) begin + for (dbi = 0; dbi < 8; dbi = dbi + 1) begin + dob_out[data_addra_reg[3 : 0] + dbi] <= 1'bX; + end + end + data_collision_a_b[0] <= 0; + end + + always @(posedge data_collision_b_a[1]) begin + if (ssra_int == 0) begin + doa_out <= 8'bX; + end + data_collision_b_a[1] <= 0; + end + + always @(posedge data_collision_b_a[0]) begin + if (ssrb_reg == 0) begin + for (dbi = 0; dbi < 8; dbi = dbi + 1) begin + dob_out[data_addra_int[3 : 0] + dbi] <= 1'bX; + end + end + data_collision_b_a[0] <= 0; + end + + + // Parity + always @(posedge memory_collision) begin + for (pmi = 0; pmi < 1; pmi = pmi + 1) begin + mem[parity_addra_int + pmi] <= 1'bX; + end + end + + always @(posedge memory_collision_a_b) begin + for (pmi = 0; pmi < 1; pmi = pmi + 1) begin + mem[parity_addra_reg + pmi] <= 1'bX; + end + end + + always @(posedge memory_collision_b_a) begin + for (pmi = 0; pmi < 1; pmi = pmi + 1) begin + mem[parity_addra_int + pmi] <= 1'bX; + end + end + + always @(posedge data_collision[1]) begin + if (ssra_int == 0) begin + dopa_out <= 1'bX; + end + end + + always @(posedge data_collision[0]) begin + if (ssrb_int == 0) begin + for (pbi = 0; pbi < 1; pbi = pbi + 1) begin + dopb_out[parity_addra_int[0 : 0] + pbi] <= 1'bX; + end + end + end + + always @(posedge data_collision_a_b[1]) begin + if (ssra_reg == 0) begin + dopa_out <= 1'bX; + end + end + + always @(posedge data_collision_a_b[0]) begin + if (ssrb_int == 0) begin + for (pbi = 0; pbi < 1; pbi = pbi + 1) begin + dopb_out[parity_addra_reg[0 : 0] + pbi] <= 1'bX; + end + end + end + + always @(posedge data_collision_b_a[1]) begin + if (ssra_int == 0) begin + dopa_out <= 1'bX; + end + end + + always @(posedge data_collision_b_a[0]) begin + if (ssrb_reg == 0) begin + for (pbi = 0; pbi < 1; pbi = pbi + 1) begin + dopb_out[parity_addra_int[0 : 0] + pbi] <= 1'bX; + end + end + end + + + initial begin + case (WRITE_MODE_A) + "WRITE_FIRST" : wr_mode_a <= 2'b00; + "READ_FIRST" : wr_mode_a <= 2'b01; + "NO_CHANGE" : wr_mode_a <= 2'b10; + default : begin + $display("Attribute Syntax Error : The Attribute WRITE_MODE_A on RAMB16_S9_S18 instance %m is set to %s. Legal values for this attribute are WRITE_FIRST, READ_FIRST or NO_CHANGE.", WRITE_MODE_A); + $finish; + end + endcase + end + + initial begin + case (WRITE_MODE_B) + "WRITE_FIRST" : wr_mode_b <= 2'b00; + "READ_FIRST" : wr_mode_b <= 2'b01; + "NO_CHANGE" : wr_mode_b <= 2'b10; + default : begin + $display("Attribute Syntax Error : The Attribute WRITE_MODE_B on RAMB16_S9_S18 instance %m is set to %s. Legal values for this attribute are WRITE_FIRST, READ_FIRST or NO_CHANGE.", WRITE_MODE_B); + $finish; + end + endcase + end + + // Port A + always @(posedge clka_int) begin + if (ena_int == 1'b1) begin + if (ssra_int == 1'b1) begin + doa_out[0] <= SRVAL_A[0]; + doa_out[1] <= SRVAL_A[1]; + doa_out[2] <= SRVAL_A[2]; + doa_out[3] <= SRVAL_A[3]; + doa_out[4] <= SRVAL_A[4]; + doa_out[5] <= SRVAL_A[5]; + doa_out[6] <= SRVAL_A[6]; + doa_out[7] <= SRVAL_A[7]; + dopa_out[0] <= SRVAL_A[8]; + end + else begin + if (wea_int == 1'b1) begin + if (wr_mode_a == 2'b00) begin + doa_out <= dia_int; + dopa_out <= dipa_int; + end + else if (wr_mode_a == 2'b01) begin + doa_out[0] <= mem[data_addra_int + 0]; + doa_out[1] <= mem[data_addra_int + 1]; + doa_out[2] <= mem[data_addra_int + 2]; + doa_out[3] <= mem[data_addra_int + 3]; + doa_out[4] <= mem[data_addra_int + 4]; + doa_out[5] <= mem[data_addra_int + 5]; + doa_out[6] <= mem[data_addra_int + 6]; + doa_out[7] <= mem[data_addra_int + 7]; + dopa_out[0] <= mem[parity_addra_int + 0]; + end + end + else begin + doa_out[0] <= mem[data_addra_int + 0]; + doa_out[1] <= mem[data_addra_int + 1]; + doa_out[2] <= mem[data_addra_int + 2]; + doa_out[3] <= mem[data_addra_int + 3]; + doa_out[4] <= mem[data_addra_int + 4]; + doa_out[5] <= mem[data_addra_int + 5]; + doa_out[6] <= mem[data_addra_int + 6]; + doa_out[7] <= mem[data_addra_int + 7]; + dopa_out[0] <= mem[parity_addra_int + 0]; + end + end + end + end + + always @(posedge clka_int) begin + if (ena_int == 1'b1 && wea_int == 1'b1) begin + mem[data_addra_int + 0] <= dia_int[0]; + mem[data_addra_int + 1] <= dia_int[1]; + mem[data_addra_int + 2] <= dia_int[2]; + mem[data_addra_int + 3] <= dia_int[3]; + mem[data_addra_int + 4] <= dia_int[4]; + mem[data_addra_int + 5] <= dia_int[5]; + mem[data_addra_int + 6] <= dia_int[6]; + mem[data_addra_int + 7] <= dia_int[7]; + mem[parity_addra_int + 0] <= dipa_int[0]; + end + end + + // Port B + always @(posedge clkb_int) begin + if (enb_int == 1'b1) begin + if (ssrb_int == 1'b1) begin + dob_out[0] <= SRVAL_B[0]; + dob_out[1] <= SRVAL_B[1]; + dob_out[2] <= SRVAL_B[2]; + dob_out[3] <= SRVAL_B[3]; + dob_out[4] <= SRVAL_B[4]; + dob_out[5] <= SRVAL_B[5]; + dob_out[6] <= SRVAL_B[6]; + dob_out[7] <= SRVAL_B[7]; + dob_out[8] <= SRVAL_B[8]; + dob_out[9] <= SRVAL_B[9]; + dob_out[10] <= SRVAL_B[10]; + dob_out[11] <= SRVAL_B[11]; + dob_out[12] <= SRVAL_B[12]; + dob_out[13] <= SRVAL_B[13]; + dob_out[14] <= SRVAL_B[14]; + dob_out[15] <= SRVAL_B[15]; + dopb_out[0] <= SRVAL_B[16]; + dopb_out[1] <= SRVAL_B[17]; + end + else begin + if (web_int == 1'b1) begin + if (wr_mode_b == 2'b00) begin + dob_out <= dib_int; + dopb_out <= dipb_int; + end + else if (wr_mode_b == 2'b01) begin + dob_out[0] <= mem[data_addrb_int + 0]; + dob_out[1] <= mem[data_addrb_int + 1]; + dob_out[2] <= mem[data_addrb_int + 2]; + dob_out[3] <= mem[data_addrb_int + 3]; + dob_out[4] <= mem[data_addrb_int + 4]; + dob_out[5] <= mem[data_addrb_int + 5]; + dob_out[6] <= mem[data_addrb_int + 6]; + dob_out[7] <= mem[data_addrb_int + 7]; + dob_out[8] <= mem[data_addrb_int + 8]; + dob_out[9] <= mem[data_addrb_int + 9]; + dob_out[10] <= mem[data_addrb_int + 10]; + dob_out[11] <= mem[data_addrb_int + 11]; + dob_out[12] <= mem[data_addrb_int + 12]; + dob_out[13] <= mem[data_addrb_int + 13]; + dob_out[14] <= mem[data_addrb_int + 14]; + dob_out[15] <= mem[data_addrb_int + 15]; + dopb_out[0] <= mem[parity_addrb_int + 0]; + dopb_out[1] <= mem[parity_addrb_int + 1]; + end + end + else begin + dob_out[0] <= mem[data_addrb_int + 0]; + dob_out[1] <= mem[data_addrb_int + 1]; + dob_out[2] <= mem[data_addrb_int + 2]; + dob_out[3] <= mem[data_addrb_int + 3]; + dob_out[4] <= mem[data_addrb_int + 4]; + dob_out[5] <= mem[data_addrb_int + 5]; + dob_out[6] <= mem[data_addrb_int + 6]; + dob_out[7] <= mem[data_addrb_int + 7]; + dob_out[8] <= mem[data_addrb_int + 8]; + dob_out[9] <= mem[data_addrb_int + 9]; + dob_out[10] <= mem[data_addrb_int + 10]; + dob_out[11] <= mem[data_addrb_int + 11]; + dob_out[12] <= mem[data_addrb_int + 12]; + dob_out[13] <= mem[data_addrb_int + 13]; + dob_out[14] <= mem[data_addrb_int + 14]; + dob_out[15] <= mem[data_addrb_int + 15]; + dopb_out[0] <= mem[parity_addrb_int + 0]; + dopb_out[1] <= mem[parity_addrb_int + 1]; + end + end + end + end + + always @(posedge clkb_int) begin + if (enb_int == 1'b1 && web_int == 1'b1) begin + mem[data_addrb_int + 0] <= dib_int[0]; + mem[data_addrb_int + 1] <= dib_int[1]; + mem[data_addrb_int + 2] <= dib_int[2]; + mem[data_addrb_int + 3] <= dib_int[3]; + mem[data_addrb_int + 4] <= dib_int[4]; + mem[data_addrb_int + 5] <= dib_int[5]; + mem[data_addrb_int + 6] <= dib_int[6]; + mem[data_addrb_int + 7] <= dib_int[7]; + mem[data_addrb_int + 8] <= dib_int[8]; + mem[data_addrb_int + 9] <= dib_int[9]; + mem[data_addrb_int + 10] <= dib_int[10]; + mem[data_addrb_int + 11] <= dib_int[11]; + mem[data_addrb_int + 12] <= dib_int[12]; + mem[data_addrb_int + 13] <= dib_int[13]; + mem[data_addrb_int + 14] <= dib_int[14]; + mem[data_addrb_int + 15] <= dib_int[15]; + mem[parity_addrb_int + 0] <= dipb_int[0]; + mem[parity_addrb_int + 1] <= dipb_int[1]; + end + end + + specify + (CLKA *> DOA) = (100, 100); + (CLKA *> DOPA) = (100, 100); + (CLKB *> DOB) = (100, 100); + (CLKB *> DOPB) = (100, 100); + endspecify + +endmodule + +`else + +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/RAMB16_S9_S18.v,v 1.10 2007/02/22 01:58:06 wloo Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2005 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Timing Simulation Library Component +// / / 16K-Bit Data and 2K-Bit Parity Dual Port Block RAM +// /___/ /\ Filename : RAMB16_S9_S18.v +// \ \ / \ Timestamp : Thu Mar 10 16:44:01 PST 2005 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 03/10/05 - Initialized outputs. +// 02/21/07 - Fixed parameter SIM_COLLISION_CHECK (CR 433281). +// End Revision + +`timescale 1 ps/1 ps + +module RAMB16_S9_S18 (DOA, DOB, DOPA, DOPB, ADDRA, ADDRB, CLKA, CLKB, DIA, DIB, DIPA, DIPB, ENA, ENB, SSRA, SSRB, WEA, WEB); + + parameter INIT_A = 9'h0; + parameter INIT_B = 18'h0; + parameter SRVAL_A = 9'h0; + parameter SRVAL_B = 18'h0; + parameter WRITE_MODE_A = "WRITE_FIRST"; + parameter WRITE_MODE_B = "WRITE_FIRST"; + parameter SIM_COLLISION_CHECK = "ALL"; + localparam SETUP_ALL = 1000; + localparam SETUP_READ_FIRST = 3000; + + parameter INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + + output [7:0] DOA; + output [0:0] DOPA; + output [15:0] DOB; + output [1:0] DOPB; + + input [10:0] ADDRA; + input [7:0] DIA; + input [0:0] DIPA; + input ENA, CLKA, WEA, SSRA; + input [9:0] ADDRB; + input [15:0] DIB; + input [1:0] DIPB; + input ENB, CLKB, WEB, SSRB; + + reg [7:0] doa_out = INIT_A[7:0]; + reg [0:0] dopa_out = INIT_A[8:8]; + reg [15:0] dob_out = INIT_B[15:0]; + reg [1:0] dopb_out = INIT_B[17:16]; + + reg [15:0] mem [1023:0]; + reg [1:0] memp [1023:0]; + + reg [8:0] count, countp; + reg [1:0] wr_mode_a, wr_mode_b; + + reg [5:0] dmi, dbi; + reg [5:0] pmi, pbi; + + wire [10:0] addra_int; + reg [10:0] addra_reg; + wire [7:0] dia_int; + wire [0:0] dipa_int; + wire ena_int, clka_int, wea_int, ssra_int; + reg ena_reg, wea_reg, ssra_reg; + wire [9:0] addrb_int; + reg [9:0] addrb_reg; + wire [15:0] dib_int; + wire [1:0] dipb_int; + wire enb_int, clkb_int, web_int, ssrb_int; + reg display_flag, output_flag; + reg enb_reg, web_reg, ssrb_reg; + + time time_clka, time_clkb; + time time_clka_clkb; + time time_clkb_clka; + + reg setup_all_a_b; + reg setup_all_b_a; + reg setup_zero; + reg setup_rf_a_b; + reg setup_rf_b_a; + reg [1:0] data_collision, data_collision_a_b, data_collision_b_a; + reg memory_collision, memory_collision_a_b, memory_collision_b_a; + reg change_clka; + reg change_clkb; + + wire [14:0] data_addra_int; + wire [14:0] data_addra_reg; + wire [14:0] data_addrb_int; + wire [14:0] data_addrb_reg; + + wire dia_enable = ena_int && wea_int; + wire dib_enable = enb_int && web_int; + + tri0 GSR = glbl.GSR; + wire gsr_int; + + buf b_gsr (gsr_int, GSR); + + buf b_doa [7:0] (DOA, doa_out); + buf b_dopa [0:0] (DOPA, dopa_out); + buf b_addra [10:0] (addra_int, ADDRA); + buf b_dia [7:0] (dia_int, DIA); + buf b_dipa [0:0] (dipa_int, DIPA); + buf b_ena (ena_int, ENA); + buf b_clka (clka_int, CLKA); + buf b_ssra (ssra_int, SSRA); + buf b_wea (wea_int, WEA); + + buf b_dob [15:0] (DOB, dob_out); + buf b_dopb [1:0] (DOPB, dopb_out); + buf b_addrb [9:0] (addrb_int, ADDRB); + buf b_dib [15:0] (dib_int, DIB); + buf b_dipb [1:0] (dipb_int, DIPB); + buf b_enb (enb_int, ENB); + buf b_clkb (clkb_int, CLKB); + buf b_ssrb (ssrb_int, SSRB); + buf b_web (web_int, WEB); + + + always @(gsr_int) + if (gsr_int) begin + assign {dopa_out, doa_out} = INIT_A; + assign {dopb_out, dob_out} = INIT_B; + end + else begin + deassign doa_out; + deassign dopa_out; + deassign dob_out; + deassign dopb_out; + end + + + initial begin + + for (count = 0; count < 16; count = count + 1) begin + mem[count] = INIT_00[(count * 16) +: 16]; + mem[16 * 1 + count] = INIT_01[(count * 16) +: 16]; + mem[16 * 2 + count] = INIT_02[(count * 16) +: 16]; + mem[16 * 3 + count] = INIT_03[(count * 16) +: 16]; + mem[16 * 4 + count] = INIT_04[(count * 16) +: 16]; + mem[16 * 5 + count] = INIT_05[(count * 16) +: 16]; + mem[16 * 6 + count] = INIT_06[(count * 16) +: 16]; + mem[16 * 7 + count] = INIT_07[(count * 16) +: 16]; + mem[16 * 8 + count] = INIT_08[(count * 16) +: 16]; + mem[16 * 9 + count] = INIT_09[(count * 16) +: 16]; + mem[16 * 10 + count] = INIT_0A[(count * 16) +: 16]; + mem[16 * 11 + count] = INIT_0B[(count * 16) +: 16]; + mem[16 * 12 + count] = INIT_0C[(count * 16) +: 16]; + mem[16 * 13 + count] = INIT_0D[(count * 16) +: 16]; + mem[16 * 14 + count] = INIT_0E[(count * 16) +: 16]; + mem[16 * 15 + count] = INIT_0F[(count * 16) +: 16]; + mem[16 * 16 + count] = INIT_10[(count * 16) +: 16]; + mem[16 * 17 + count] = INIT_11[(count * 16) +: 16]; + mem[16 * 18 + count] = INIT_12[(count * 16) +: 16]; + mem[16 * 19 + count] = INIT_13[(count * 16) +: 16]; + mem[16 * 20 + count] = INIT_14[(count * 16) +: 16]; + mem[16 * 21 + count] = INIT_15[(count * 16) +: 16]; + mem[16 * 22 + count] = INIT_16[(count * 16) +: 16]; + mem[16 * 23 + count] = INIT_17[(count * 16) +: 16]; + mem[16 * 24 + count] = INIT_18[(count * 16) +: 16]; + mem[16 * 25 + count] = INIT_19[(count * 16) +: 16]; + mem[16 * 26 + count] = INIT_1A[(count * 16) +: 16]; + mem[16 * 27 + count] = INIT_1B[(count * 16) +: 16]; + mem[16 * 28 + count] = INIT_1C[(count * 16) +: 16]; + mem[16 * 29 + count] = INIT_1D[(count * 16) +: 16]; + mem[16 * 30 + count] = INIT_1E[(count * 16) +: 16]; + mem[16 * 31 + count] = INIT_1F[(count * 16) +: 16]; + mem[16 * 32 + count] = INIT_20[(count * 16) +: 16]; + mem[16 * 33 + count] = INIT_21[(count * 16) +: 16]; + mem[16 * 34 + count] = INIT_22[(count * 16) +: 16]; + mem[16 * 35 + count] = INIT_23[(count * 16) +: 16]; + mem[16 * 36 + count] = INIT_24[(count * 16) +: 16]; + mem[16 * 37 + count] = INIT_25[(count * 16) +: 16]; + mem[16 * 38 + count] = INIT_26[(count * 16) +: 16]; + mem[16 * 39 + count] = INIT_27[(count * 16) +: 16]; + mem[16 * 40 + count] = INIT_28[(count * 16) +: 16]; + mem[16 * 41 + count] = INIT_29[(count * 16) +: 16]; + mem[16 * 42 + count] = INIT_2A[(count * 16) +: 16]; + mem[16 * 43 + count] = INIT_2B[(count * 16) +: 16]; + mem[16 * 44 + count] = INIT_2C[(count * 16) +: 16]; + mem[16 * 45 + count] = INIT_2D[(count * 16) +: 16]; + mem[16 * 46 + count] = INIT_2E[(count * 16) +: 16]; + mem[16 * 47 + count] = INIT_2F[(count * 16) +: 16]; + mem[16 * 48 + count] = INIT_30[(count * 16) +: 16]; + mem[16 * 49 + count] = INIT_31[(count * 16) +: 16]; + mem[16 * 50 + count] = INIT_32[(count * 16) +: 16]; + mem[16 * 51 + count] = INIT_33[(count * 16) +: 16]; + mem[16 * 52 + count] = INIT_34[(count * 16) +: 16]; + mem[16 * 53 + count] = INIT_35[(count * 16) +: 16]; + mem[16 * 54 + count] = INIT_36[(count * 16) +: 16]; + mem[16 * 55 + count] = INIT_37[(count * 16) +: 16]; + mem[16 * 56 + count] = INIT_38[(count * 16) +: 16]; + mem[16 * 57 + count] = INIT_39[(count * 16) +: 16]; + mem[16 * 58 + count] = INIT_3A[(count * 16) +: 16]; + mem[16 * 59 + count] = INIT_3B[(count * 16) +: 16]; + mem[16 * 60 + count] = INIT_3C[(count * 16) +: 16]; + mem[16 * 61 + count] = INIT_3D[(count * 16) +: 16]; + mem[16 * 62 + count] = INIT_3E[(count * 16) +: 16]; + mem[16 * 63 + count] = INIT_3F[(count * 16) +: 16]; + end + +// initiate parity start + for (countp = 0; countp < 128; countp = countp + 1) begin + memp[countp] = INITP_00[(countp * 2) +: 2]; + memp[128 * 1 + countp] = INITP_01[(countp * 2) +: 2]; + memp[128 * 2 + countp] = INITP_02[(countp * 2) +: 2]; + memp[128 * 3 + countp] = INITP_03[(countp * 2) +: 2]; + memp[128 * 4 + countp] = INITP_04[(countp * 2) +: 2]; + memp[128 * 5 + countp] = INITP_05[(countp * 2) +: 2]; + memp[128 * 6 + countp] = INITP_06[(countp * 2) +: 2]; + memp[128 * 7 + countp] = INITP_07[(countp * 2) +: 2]; + end +// initiate parity end + + change_clka <= 0; + change_clkb <= 0; + data_collision <= 0; + data_collision_a_b <= 0; + data_collision_b_a <= 0; + memory_collision <= 0; + memory_collision_a_b <= 0; + memory_collision_b_a <= 0; + setup_all_a_b <= 0; + setup_all_b_a <= 0; + setup_zero <= 0; + setup_rf_a_b <= 0; + setup_rf_b_a <= 0; + end + + assign data_addra_int = addra_int * 8; + assign data_addra_reg = addra_reg * 8; + assign data_addrb_int = addrb_int * 16; + assign data_addrb_reg = addrb_reg * 16; + + + initial begin + + display_flag = 1; + output_flag = 1; + + case (SIM_COLLISION_CHECK) + + "NONE" : begin + output_flag = 0; + display_flag = 0; + end + "WARNING_ONLY" : output_flag = 0; + "GENERATE_X_ONLY" : display_flag = 0; + "ALL" : ; + + default : begin + $display("Attribute Syntax Error : The Attribute SIM_COLLISION_CHECK on RAMB16_S9_S18 instance %m is set to %s. Legal values for this attribute are ALL, NONE, WARNING_ONLY or GENERATE_X_ONLY.", SIM_COLLISION_CHECK); + $finish; + end + + endcase // case(SIM_COLLISION_CHECK) + + end // initial begin + + + always @(posedge clka_int) begin + if ((output_flag || display_flag)) begin + time_clka = $time; + #0 time_clkb_clka = time_clka - time_clkb; + change_clka = ~change_clka; + end + end + + always @(posedge clkb_int) begin + if ((output_flag || display_flag)) begin + time_clkb = $time; + #0 time_clka_clkb = time_clkb - time_clka; + change_clkb = ~change_clkb; + end + end + + always @(change_clkb) begin + if ((0 < time_clka_clkb) && (time_clka_clkb < SETUP_ALL)) + setup_all_a_b = 1; + if ((0 < time_clka_clkb) && (time_clka_clkb < SETUP_READ_FIRST)) + setup_rf_a_b = 1; + end + + always @(change_clka) begin + if ((0 < time_clkb_clka) && (time_clkb_clka < SETUP_ALL)) + setup_all_b_a = 1; + if ((0 < time_clkb_clka) && (time_clkb_clka < SETUP_READ_FIRST)) + setup_rf_b_a = 1; + end + + always @(change_clkb or change_clka) begin + if ((time_clkb_clka == 0) && (time_clka_clkb == 0)) + setup_zero = 1; + end + + always @(posedge setup_zero) begin + if ((ena_int == 1) && (wea_int == 1) && + (enb_int == 1) && (web_int == 1) && + (data_addra_int[14:4] == data_addrb_int[14:4])) + memory_collision <= 1; + end + + always @(posedge setup_all_a_b or posedge setup_rf_a_b) begin + if ((ena_reg == 1) && (wea_reg == 1) && + (enb_int == 1) && (web_int == 1) && + (data_addra_reg[14:4] == data_addrb_int[14:4])) + memory_collision_a_b <= 1; + end + + always @(posedge setup_all_b_a or posedge setup_rf_b_a) begin + if ((ena_int == 1) && (wea_int == 1) && + (enb_reg == 1) && (web_reg == 1) && + (data_addra_int[14:4] == data_addrb_reg[14:4])) + memory_collision_b_a <= 1; + end + + always @(posedge setup_all_a_b) begin + if (data_addra_reg[14:4] == data_addrb_int[14:4]) begin + if ((ena_reg == 1) && (enb_int == 1)) begin + case ({wr_mode_a, wr_mode_b, wea_reg, web_int}) + 6'b000011 : begin data_collision_a_b <= 2'b11; display_wa_wb; end + 6'b000111 : begin data_collision_a_b <= 2'b11; display_wa_wb; end + 6'b001011 : begin data_collision_a_b <= 2'b10; display_wa_wb; end +// 6'b010011 : begin data_collision_a_b <= 2'b00; display_wa_wb; end +// 6'b010111 : begin data_collision_a_b <= 2'b00; display_wa_wb; end +// 6'b011011 : begin data_collision_a_b <= 2'b00; display_wa_wb; end + 6'b100011 : begin data_collision_a_b <= 2'b01; display_wa_wb; end + 6'b100111 : begin data_collision_a_b <= 2'b01; display_wa_wb; end + 6'b101011 : begin display_wa_wb; end + 6'b000001 : begin data_collision_a_b <= 2'b10; display_ra_wb; end +// 6'b000101 : begin data_collision_a_b <= 2'b00; display_ra_wb; end + 6'b001001 : begin data_collision_a_b <= 2'b10; display_ra_wb; end + 6'b010001 : begin data_collision_a_b <= 2'b10; display_ra_wb; end +// 6'b010101 : begin data_collision_a_b <= 2'b00; display_ra_wb; end + 6'b011001 : begin data_collision_a_b <= 2'b10; display_ra_wb; end + 6'b100001 : begin data_collision_a_b <= 2'b10; display_ra_wb; end +// 6'b100101 : begin data_collision_a_b <= 2'b00; display_ra_wb; end + 6'b101001 : begin data_collision_a_b <= 2'b10; display_ra_wb; end + 6'b000010 : begin data_collision_a_b <= 2'b01; display_wa_rb; end + 6'b000110 : begin data_collision_a_b <= 2'b01; display_wa_rb; end + 6'b001010 : begin data_collision_a_b <= 2'b01; display_wa_rb; end +// 6'b010010 : begin data_collision_a_b <= 2'b00; display_wa_rb; end +// 6'b010110 : begin data_collision_a_b <= 2'b00; display_wa_rb; end +// 6'b011010 : begin data_collision_a_b <= 2'b00; display_wa_rb; end + 6'b100010 : begin data_collision_a_b <= 2'b01; display_wa_rb; end + 6'b100110 : begin data_collision_a_b <= 2'b01; display_wa_rb; end + 6'b101010 : begin data_collision_a_b <= 2'b01; display_wa_rb; end + endcase + end + end + setup_all_a_b <= 0; + end + + + always @(posedge setup_all_b_a) begin + if (data_addra_int[14:4] == data_addrb_reg[14:4]) begin + if ((ena_int == 1) && (enb_reg == 1)) begin + case ({wr_mode_a, wr_mode_b, wea_int, web_reg}) + 6'b000011 : begin data_collision_b_a <= 2'b11; display_wa_wb; end +// 6'b000111 : begin data_collision_b_a <= 2'b00; display_wa_wb; end + 6'b001011 : begin data_collision_b_a <= 2'b10; display_wa_wb; end + 6'b010011 : begin data_collision_b_a <= 2'b11; display_wa_wb; end +// 6'b010111 : begin data_collision_b_a <= 2'b00; display_wa_wb; end + 6'b011011 : begin data_collision_b_a <= 2'b10; display_wa_wb; end + 6'b100011 : begin data_collision_b_a <= 2'b01; display_wa_wb; end + 6'b100111 : begin data_collision_b_a <= 2'b01; display_wa_wb; end + 6'b101011 : begin display_wa_wb; end + 6'b000001 : begin data_collision_b_a <= 2'b10; display_ra_wb; end + 6'b000101 : begin data_collision_b_a <= 2'b10; display_ra_wb; end + 6'b001001 : begin data_collision_b_a <= 2'b10; display_ra_wb; end + 6'b010001 : begin data_collision_b_a <= 2'b10; display_ra_wb; end + 6'b010101 : begin data_collision_b_a <= 2'b10; display_ra_wb; end + 6'b011001 : begin data_collision_b_a <= 2'b10; display_ra_wb; end + 6'b100001 : begin data_collision_b_a <= 2'b10; display_ra_wb; end + 6'b100101 : begin data_collision_b_a <= 2'b10; display_ra_wb; end + 6'b101001 : begin data_collision_b_a <= 2'b10; display_ra_wb; end + 6'b000010 : begin data_collision_b_a <= 2'b01; display_wa_rb; end + 6'b000110 : begin data_collision_b_a <= 2'b01; display_wa_rb; end + 6'b001010 : begin data_collision_b_a <= 2'b01; display_wa_rb; end +// 6'b010010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end +// 6'b010110 : begin data_collision_b_a <= 2'b00; display_wa_rb; end +// 6'b011010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end + 6'b100010 : begin data_collision_b_a <= 2'b01; display_wa_rb; end + 6'b100110 : begin data_collision_b_a <= 2'b01; display_wa_rb; end + 6'b101010 : begin data_collision_b_a <= 2'b01; display_wa_rb; end + endcase + end + end + setup_all_b_a <= 0; + end + + + always @(posedge setup_zero) begin + if (data_addra_int[14:4] == data_addrb_int[14:4]) begin + if ((ena_int == 1) && (enb_int == 1)) begin + case ({wr_mode_a, wr_mode_b, wea_int, web_int}) + 6'b000011 : begin data_collision <= 2'b11; display_wa_wb; end + 6'b000111 : begin data_collision <= 2'b11; display_wa_wb; end + 6'b001011 : begin data_collision <= 2'b10; display_wa_wb; end + 6'b010011 : begin data_collision <= 2'b11; display_wa_wb; end + 6'b010111 : begin data_collision <= 2'b11; display_wa_wb; end + 6'b011011 : begin data_collision <= 2'b10; display_wa_wb; end + 6'b100011 : begin data_collision <= 2'b01; display_wa_wb; end + 6'b100111 : begin data_collision <= 2'b01; display_wa_wb; end + 6'b101011 : begin display_wa_wb; end + 6'b000001 : begin data_collision <= 2'b10; display_ra_wb; end +// 6'b000101 : begin data_collision <= 2'b00; display_ra_wb; end + 6'b001001 : begin data_collision <= 2'b10; display_ra_wb; end + 6'b010001 : begin data_collision <= 2'b10; display_ra_wb; end +// 6'b010101 : begin data_collision <= 2'b00; display_ra_wb; end + 6'b011001 : begin data_collision <= 2'b10; display_ra_wb; end + 6'b100001 : begin data_collision <= 2'b10; display_ra_wb; end +// 6'b100101 : begin data_collision <= 2'b00; display_ra_wb; end + 6'b101001 : begin data_collision <= 2'b10; display_ra_wb; end + 6'b000010 : begin data_collision <= 2'b01; display_wa_rb; end + 6'b000110 : begin data_collision <= 2'b01; display_wa_rb; end + 6'b001010 : begin data_collision <= 2'b01; display_wa_rb; end +// 6'b010010 : begin data_collision <= 2'b00; display_wa_rb; end +// 6'b010110 : begin data_collision <= 2'b00; display_wa_rb; end +// 6'b011010 : begin data_collision <= 2'b00; display_wa_rb; end + 6'b100010 : begin data_collision <= 2'b01; display_wa_rb; end + 6'b100110 : begin data_collision <= 2'b01; display_wa_rb; end + 6'b101010 : begin data_collision <= 2'b01; display_wa_rb; end + endcase + end + end + setup_zero <= 0; + end + + task display_ra_wb; + begin + if (display_flag) + $display("Memory Collision Error on RAMB16_S9_S18:%m at simulation time %.3f ns\nA read was performed on address %h (hex) of Port A while a write was requested to the same address on Port B. The write will be successful however the read value on Port A is unknown until the next CLKA cycle.", $time/1000.0, addra_int); + end + endtask + + task display_wa_rb; + begin + if (display_flag) + $display("Memory Collision Error on RAMB16_S9_S18:%m at simulation time %.3f ns\nA read was performed on address %h (hex) of Port B while a write was requested to the same address on Port A. The write will be successful however the read value on Port B is unknown until the next CLKB cycle.", $time/1000.0, addrb_int); + end + endtask + + task display_wa_wb; + begin + if (display_flag) + $display("Memory Collision Error on RAMB16_S9_S18:%m at simulation time %.3f ns\nA write was requested to the same address simultaneously at both Port A and Port B of the RAM. The contents written to the RAM at address location %h (hex) of Port A and address location %h (hex) of Port B are unknown.", $time/1000.0, addra_int, addrb_int); + end + endtask + + + always @(posedge setup_rf_a_b) begin + if (data_addra_reg[14:4] == data_addrb_int[14:4]) begin + if ((ena_reg == 1) && (enb_int == 1)) begin + case ({wr_mode_a, wr_mode_b, wea_reg, web_int}) +// 6'b000011 : begin data_collision_a_b <= 2'b00; display_wa_wb; end +// 6'b000111 : begin data_collision_a_b <= 2'b00; display_wa_wb; end +// 6'b001011 : begin data_collision_a_b <= 2'b00; display_wa_wb; end + 6'b010011 : begin data_collision_a_b <= 2'b11; display_wa_wb; end + 6'b010111 : begin data_collision_a_b <= 2'b11; display_wa_wb; end + 6'b011011 : begin data_collision_a_b <= 2'b10; display_wa_wb; end +// 6'b100011 : begin data_collision_a_b <= 2'b00; display_wa_wb; end +// 6'b100111 : begin data_collision_a_b <= 2'b00; display_wa_wb; end +// 6'b101011 : begin data_collision_a_b <= 2'b00; display_wa_wb; end +// 6'b000001 : begin data_collision_a_b <= 2'b00; display_ra_wb; end +// 6'b000101 : begin data_collision_a_b <= 2'b00; display_ra_wb; end +// 6'b001001 : begin data_collision_a_b <= 2'b00; display_ra_wb; end +// 6'b010001 : begin data_collision_a_b <= 2'b00; display_ra_wb; end +// 6'b010101 : begin data_collision_a_b <= 2'b00; display_ra_wb; end +// 6'b011001 : begin data_collision_a_b <= 2'b00; display_ra_wb; end +// 6'b100001 : begin data_collision_a_b <= 2'b00; display_ra_wb; end +// 6'b100101 : begin data_collision_a_b <= 2'b00; display_ra_wb; end +// 6'b101001 : begin data_collision_a_b <= 2'b00; display_ra_wb; end +// 6'b000010 : begin data_collision_a_b <= 2'b00; display_wa_rb; end +// 6'b000110 : begin data_collision_a_b <= 2'b00; display_wa_rb; end +// 6'b001010 : begin data_collision_a_b <= 2'b00; display_wa_rb; end + 6'b010010 : begin data_collision_a_b <= 2'b01; display_wa_rb; end + 6'b010110 : begin data_collision_a_b <= 2'b01; display_wa_rb; end + 6'b011010 : begin data_collision_a_b <= 2'b01; display_wa_rb; end +// 6'b100010 : begin data_collision_a_b <= 2'b00; display_wa_rb; end +// 6'b100110 : begin data_collision_a_b <= 2'b00; display_wa_rb; end +// 6'b101010 : begin data_collision_a_b <= 2'b00; display_wa_rb; end + endcase + end + end + setup_rf_a_b <= 0; + end + + + always @(posedge setup_rf_b_a) begin + if (data_addra_int[14:4] == data_addrb_reg[14:4]) begin + if ((ena_int == 1) && (enb_reg == 1)) begin + case ({wr_mode_a, wr_mode_b, wea_int, web_reg}) +// 6'b000011 : begin data_collision_b_a <= 2'b00; display_wa_wb; end + 6'b000111 : begin data_collision_b_a <= 2'b11; display_wa_wb; end +// 6'b001011 : begin data_collision_b_a <= 2'b00; display_wa_wb; end +// 6'b010011 : begin data_collision_b_a <= 2'b00; display_wa_wb; end + 6'b010111 : begin data_collision_b_a <= 2'b11; display_wa_wb; end +// 6'b011011 : begin data_collision_b_a <= 2'b00; display_wa_wb; end +// 6'b100011 : begin data_collision_b_a <= 2'b00; display_wa_wb; end + 6'b100111 : begin data_collision_b_a <= 2'b01; display_wa_wb; end +// 6'b101011 : begin data_collision_b_a <= 2'b00; display_wa_wb; end +// 6'b000001 : begin data_collision_b_a <= 2'b00; display_ra_wb; end + 6'b000101 : begin data_collision_b_a <= 2'b10; display_ra_wb; end +// 6'b001001 : begin data_collision_b_a <= 2'b00; display_ra_wb; end +// 6'b010001 : begin data_collision_b_a <= 2'b00; display_ra_wb; end + 6'b010101 : begin data_collision_b_a <= 2'b10; display_ra_wb; end +// 6'b011001 : begin data_collision_b_a <= 2'b00; display_ra_wb; end +// 6'b100001 : begin data_collision_b_a <= 2'b00; display_ra_wb; end + 6'b100101 : begin data_collision_b_a <= 2'b10; display_ra_wb; end +// 6'b101001 : begin data_collision_b_a <= 2'b00; display_ra_wb; end +// 6'b000010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end +// 6'b000110 : begin data_collision_b_a <= 2'b00; display_wa_rb; end +// 6'b001010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end +// 6'b010010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end +// 6'b010110 : begin data_collision_b_a <= 2'b00; display_wa_rb; end +// 6'b011010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end +// 6'b100010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end +// 6'b100110 : begin data_collision_b_a <= 2'b00; display_wa_rb; end +// 6'b101010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end + endcase + end + end + setup_rf_b_a <= 0; + end + + + always @(posedge clka_int) begin + if ((output_flag || display_flag)) begin + addra_reg <= addra_int; + ena_reg <= ena_int; + ssra_reg <= ssra_int; + wea_reg <= wea_int; + end + end + + always @(posedge clkb_int) begin + if ((output_flag || display_flag)) begin + addrb_reg <= addrb_int; + enb_reg <= enb_int; + ssrb_reg <= ssrb_int; + web_reg <= web_int; + end + end + + + // Data + always @(posedge memory_collision) begin + if ((output_flag || display_flag)) begin + mem[addra_int[10:1]][addra_int[0:0] * 8 +: 8] <= 8'bx; + memory_collision <= 0; + end + + end + + always @(posedge memory_collision_a_b) begin + if ((output_flag || display_flag)) begin + mem[addra_reg[10:1]][addra_reg[0:0] * 8 +: 8] <= 8'bx; + memory_collision_a_b <= 0; + end + end + + always @(posedge memory_collision_b_a) begin + if ((output_flag || display_flag)) begin + mem[addra_int[10:1]][addra_int[0:0] * 8 +: 8] <= 8'bx; + memory_collision_b_a <= 0; + end + end + + always @(posedge data_collision[1]) begin + if (ssra_int == 0 && output_flag) begin + doa_out <= #100 8'bX; + end + data_collision[1] <= 0; + end + + always @(posedge data_collision[0]) begin + if (ssrb_int == 0 && output_flag) begin + dob_out[addra_int[0:0] * 8 +: 8] <= #100 8'bX; + end + data_collision[0] <= 0; + end + + always @(posedge data_collision_a_b[1]) begin + if (ssra_reg == 0 && output_flag) begin + doa_out <= #100 8'bX; + end + data_collision_a_b[1] <= 0; + end + + always @(posedge data_collision_a_b[0]) begin + if (ssrb_int == 0 && output_flag) begin + dob_out[addra_reg[0:0] * 8 +: 8] <= #100 8'bX; + end + data_collision_a_b[0] <= 0; + end + + always @(posedge data_collision_b_a[1]) begin + if (ssra_int == 0 && output_flag) begin + doa_out <= #100 8'bX; + end + data_collision_b_a[1] <= 0; + end + + always @(posedge data_collision_b_a[0]) begin + if (ssrb_reg == 0 && output_flag) begin + dob_out[addra_int[0:0] * 8 +: 8] <= #100 8'bX; + end + data_collision_b_a[0] <= 0; + end + +// x parity start + always @(posedge memory_collision) begin + if ((output_flag || display_flag)) + memp[addra_int[10:1]][addra_int[0:0] * 1 +: 1] <= 1'bx; + end + + always @(posedge memory_collision_a_b) begin + if ((output_flag || display_flag)) + memp[addra_reg[10:1]][addra_reg[0:0] * 1 +: 1] <= 1'bx; + end + + always @(posedge memory_collision_b_a) begin + if ((output_flag || display_flag)) + memp[addra_int[10:1]][addra_int[0:0] * 1 +: 1] <= 1'bx; + end + + always @(posedge data_collision[1]) begin + if (ssra_int == 0 && output_flag) begin + dopa_out <= #100 1'bX; + end + end + + always @(posedge data_collision_a_b[1]) begin + if (ssra_reg == 0 && output_flag) begin + dopa_out <= #100 1'bX; + end + end + + + always @(posedge data_collision_b_a[1]) begin + if (ssra_int == 0 && output_flag) begin + dopa_out <= #100 1'bX; + end + end + + always @(posedge data_collision[0]) begin + if (ssrb_int == 0 && output_flag) begin + dopb_out[addra_int[0:0] +: 1] <= #100 1'bx; + end + end + + always @(posedge data_collision_a_b[0]) begin + if (ssrb_int == 0 && output_flag) begin + dopb_out[addra_reg[0:0] +: 1] <= #100 1'bx; + end + end + + always @(posedge data_collision_b_a[0]) begin + if (ssrb_reg == 0 && output_flag) begin + dopb_out[addra_int[0:0] +: 1] <= #100 1'bx; + end + end +// x parity end + + initial begin + case (WRITE_MODE_A) + "WRITE_FIRST" : wr_mode_a <= 2'b00; + "READ_FIRST" : wr_mode_a <= 2'b01; + "NO_CHANGE" : wr_mode_a <= 2'b10; + default : begin + $display("Attribute Syntax Error : The Attribute WRITE_MODE_A on RAMB16_S9_S18 instance %m is set to %s. Legal values for this attribute are WRITE_FIRST, READ_FIRST or NO_CHANGE.", WRITE_MODE_A); + $finish; + end + endcase + end + + initial begin + case (WRITE_MODE_B) + "WRITE_FIRST" : wr_mode_b <= 2'b00; + "READ_FIRST" : wr_mode_b <= 2'b01; + "NO_CHANGE" : wr_mode_b <= 2'b10; + default : begin + $display("Attribute Syntax Error : The Attribute WRITE_MODE_B on RAMB16_S9_S18 instance %m is set to %s. Legal values for this attribute are WRITE_FIRST, READ_FIRST or NO_CHANGE.", WRITE_MODE_B); + $finish; + end + endcase + end + + + // Port A + always @(posedge clka_int) begin + + if (ena_int == 1'b1) begin + + if (ssra_int == 1'b1) begin + {dopa_out, doa_out} <= #100 SRVAL_A; + end + else begin + if (wea_int == 1'b1) begin + if (wr_mode_a == 2'b00) begin + doa_out <= #100 dia_int; + dopa_out <= #100 dipa_int; + end + else if (wr_mode_a == 2'b01) begin + + doa_out <= #100 mem[addra_int[10:1]][addra_int[0:0] * 8 +: 8]; + dopa_out <= #100 memp[addra_int[10:1]][addra_int[0:0] * 1 +: 1]; + + end + end + else begin + + doa_out <= #100 mem[addra_int[10:1]][addra_int[0:0] * 8 +: 8]; + dopa_out <= #100 memp[addra_int[10:1]][addra_int[0:0] * 1 +: 1]; + + end + end + + // memory + if (wea_int == 1'b1) begin + mem[addra_int[10:1]][addra_int[0:0] * 8 +: 8] <= dia_int; + memp[addra_int[10:1]][addra_int[0:0] * 1 +: 1] <= dipa_int; + end + + end + end + + + // Port B + always @(posedge clkb_int) begin + + if (enb_int == 1'b1) begin + + if (ssrb_int == 1'b1) begin + {dopb_out, dob_out} <= #100 SRVAL_B; + end + else begin + if (web_int == 1'b1) begin + if (wr_mode_b == 2'b00) begin + dob_out <= #100 dib_int; + dopb_out <= #100 dipb_int; + end + else if (wr_mode_b == 2'b01) begin + dob_out <= #100 mem[addrb_int]; + dopb_out <= #100 memp[addrb_int]; + end + end + else begin + dob_out <= #100 mem[addrb_int]; + dopb_out <= #100 memp[addrb_int]; + end + end + + // memory + if (web_int == 1'b1) begin + mem[addrb_int] <= dib_int; + memp[addrb_int] <= dipb_int; + end + + end + end + + +endmodule + +`endif diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/RAMB16_S9_S36.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/RAMB16_S9_S36.v new file mode 100644 index 0000000..198bc48 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/RAMB16_S9_S36.v @@ -0,0 +1,2019 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/RAMB16_S9_S36.v,v 1.10 2007/02/22 01:58:06 wloo Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2005 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / 16K-Bit Data and 2K-Bit Parity Dual Port Block RAM +// /___/ /\ Filename : RAMB16_S9_S36.v +// \ \ / \ Timestamp : Thu Mar 10 16:43:37 PST 2005 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// End Revision + +`ifdef legacy_model + +`timescale 1 ps / 1 ps + +module RAMB16_S9_S36 (DOA, DOB, DOPA, DOPB, ADDRA, ADDRB, CLKA, CLKB, DIA, DIB, DIPA, DIPB, ENA, ENB, SSRA, SSRB, WEA, WEB); + + parameter INIT_A = 9'h0; + parameter INIT_B = 36'h0; + parameter SRVAL_A = 9'h0; + parameter SRVAL_B = 36'h0; + parameter WRITE_MODE_A = "WRITE_FIRST"; + parameter WRITE_MODE_B = "WRITE_FIRST"; + parameter SIM_COLLISION_CHECK = "ALL"; + localparam SETUP_ALL = 1000; + localparam SETUP_READ_FIRST = 3000; + + parameter INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + + output [7:0] DOA; + output [0:0] DOPA; + reg [7:0] doa_out; + reg [0:0] dopa_out; + wire doa_out0, doa_out1, doa_out2, doa_out3, doa_out4, doa_out5, doa_out6, doa_out7; + wire dopa0_out; + + input [10:0] ADDRA; + input [7:0] DIA; + input [0:0] DIPA; + input ENA, CLKA, WEA, SSRA; + + output [31:0] DOB; + output [3:0] DOPB; + reg [31:0] dob_out; + reg [3:0] dopb_out; + wire dob_out0, dob_out1, dob_out2, dob_out3, dob_out4, dob_out5, dob_out6, dob_out7, dob_out8, dob_out9, dob_out10, dob_out11, dob_out12, dob_out13, dob_out14, dob_out15, dob_out16, dob_out17, dob_out18, dob_out19, dob_out20, dob_out21, dob_out22, dob_out23, dob_out24, dob_out25, dob_out26, dob_out27, dob_out28, dob_out29, dob_out30, dob_out31; + wire dopb0_out, dopb1_out, dopb2_out, dopb3_out; + + input [8:0] ADDRB; + input [31:0] DIB; + input [3:0] DIPB; + input ENB, CLKB, WEB, SSRB; + + reg [18431:0] mem; + reg [8:0] count; + reg [1:0] wr_mode_a, wr_mode_b; + + reg [5:0] dmi, dbi; + reg [5:0] pmi, pbi; + + wire [10:0] addra_int; + reg [10:0] addra_reg; + wire [7:0] dia_int; + wire [0:0] dipa_int; + wire ena_int, clka_int, wea_int, ssra_int; + reg ena_reg, wea_reg, ssra_reg; + wire [8:0] addrb_int; + reg [8:0] addrb_reg; + wire [31:0] dib_int; + wire [3:0] dipb_int; + wire enb_int, clkb_int, web_int, ssrb_int; + reg display_flag; + reg enb_reg, web_reg, ssrb_reg; + + time time_clka, time_clkb; + time time_clka_clkb; + time time_clkb_clka; + + reg setup_all_a_b; + reg setup_all_b_a; + reg setup_zero; + reg setup_rf_a_b; + reg setup_rf_b_a; + reg [1:0] data_collision, data_collision_a_b, data_collision_b_a; + reg memory_collision, memory_collision_a_b, memory_collision_b_a; + reg address_collision, address_collision_a_b, address_collision_b_a; + reg change_clka; + reg change_clkb; + + wire [14:0] data_addra_int; + wire [14:0] data_addra_reg; + wire [14:0] data_addrb_int; + wire [14:0] data_addrb_reg; + wire [15:0] parity_addra_int; + wire [15:0] parity_addra_reg; + wire [15:0] parity_addrb_int; + wire [15:0] parity_addrb_reg; + + tri0 GSR = glbl.GSR; + + always @(GSR) + if (GSR) begin + assign doa_out = INIT_A[7:0]; + assign dopa_out = INIT_A[8:8]; + assign dob_out = INIT_B[31:0]; + assign dopb_out = INIT_B[35:32]; + end + else begin + deassign doa_out; + deassign dopa_out; + deassign dob_out; + deassign dopb_out; + end + + buf b_doa_out0 (doa_out0, doa_out[0]); + buf b_doa_out1 (doa_out1, doa_out[1]); + buf b_doa_out2 (doa_out2, doa_out[2]); + buf b_doa_out3 (doa_out3, doa_out[3]); + buf b_doa_out4 (doa_out4, doa_out[4]); + buf b_doa_out5 (doa_out5, doa_out[5]); + buf b_doa_out6 (doa_out6, doa_out[6]); + buf b_doa_out7 (doa_out7, doa_out[7]); + buf b_dopa_out0 (dopa_out0, dopa_out[0]); + buf b_dob_out0 (dob_out0, dob_out[0]); + buf b_dob_out1 (dob_out1, dob_out[1]); + buf b_dob_out2 (dob_out2, dob_out[2]); + buf b_dob_out3 (dob_out3, dob_out[3]); + buf b_dob_out4 (dob_out4, dob_out[4]); + buf b_dob_out5 (dob_out5, dob_out[5]); + buf b_dob_out6 (dob_out6, dob_out[6]); + buf b_dob_out7 (dob_out7, dob_out[7]); + buf b_dob_out8 (dob_out8, dob_out[8]); + buf b_dob_out9 (dob_out9, dob_out[9]); + buf b_dob_out10 (dob_out10, dob_out[10]); + buf b_dob_out11 (dob_out11, dob_out[11]); + buf b_dob_out12 (dob_out12, dob_out[12]); + buf b_dob_out13 (dob_out13, dob_out[13]); + buf b_dob_out14 (dob_out14, dob_out[14]); + buf b_dob_out15 (dob_out15, dob_out[15]); + buf b_dob_out16 (dob_out16, dob_out[16]); + buf b_dob_out17 (dob_out17, dob_out[17]); + buf b_dob_out18 (dob_out18, dob_out[18]); + buf b_dob_out19 (dob_out19, dob_out[19]); + buf b_dob_out20 (dob_out20, dob_out[20]); + buf b_dob_out21 (dob_out21, dob_out[21]); + buf b_dob_out22 (dob_out22, dob_out[22]); + buf b_dob_out23 (dob_out23, dob_out[23]); + buf b_dob_out24 (dob_out24, dob_out[24]); + buf b_dob_out25 (dob_out25, dob_out[25]); + buf b_dob_out26 (dob_out26, dob_out[26]); + buf b_dob_out27 (dob_out27, dob_out[27]); + buf b_dob_out28 (dob_out28, dob_out[28]); + buf b_dob_out29 (dob_out29, dob_out[29]); + buf b_dob_out30 (dob_out30, dob_out[30]); + buf b_dob_out31 (dob_out31, dob_out[31]); + buf b_dopb_out0 (dopb_out0, dopb_out[0]); + buf b_dopb_out1 (dopb_out1, dopb_out[1]); + buf b_dopb_out2 (dopb_out2, dopb_out[2]); + buf b_dopb_out3 (dopb_out3, dopb_out[3]); + + buf b_doa0 (DOA[0], doa_out0); + buf b_doa1 (DOA[1], doa_out1); + buf b_doa2 (DOA[2], doa_out2); + buf b_doa3 (DOA[3], doa_out3); + buf b_doa4 (DOA[4], doa_out4); + buf b_doa5 (DOA[5], doa_out5); + buf b_doa6 (DOA[6], doa_out6); + buf b_doa7 (DOA[7], doa_out7); + buf b_dopa0 (DOPA[0], dopa_out0); + buf b_dob0 (DOB[0], dob_out0); + buf b_dob1 (DOB[1], dob_out1); + buf b_dob2 (DOB[2], dob_out2); + buf b_dob3 (DOB[3], dob_out3); + buf b_dob4 (DOB[4], dob_out4); + buf b_dob5 (DOB[5], dob_out5); + buf b_dob6 (DOB[6], dob_out6); + buf b_dob7 (DOB[7], dob_out7); + buf b_dob8 (DOB[8], dob_out8); + buf b_dob9 (DOB[9], dob_out9); + buf b_dob10 (DOB[10], dob_out10); + buf b_dob11 (DOB[11], dob_out11); + buf b_dob12 (DOB[12], dob_out12); + buf b_dob13 (DOB[13], dob_out13); + buf b_dob14 (DOB[14], dob_out14); + buf b_dob15 (DOB[15], dob_out15); + buf b_dob16 (DOB[16], dob_out16); + buf b_dob17 (DOB[17], dob_out17); + buf b_dob18 (DOB[18], dob_out18); + buf b_dob19 (DOB[19], dob_out19); + buf b_dob20 (DOB[20], dob_out20); + buf b_dob21 (DOB[21], dob_out21); + buf b_dob22 (DOB[22], dob_out22); + buf b_dob23 (DOB[23], dob_out23); + buf b_dob24 (DOB[24], dob_out24); + buf b_dob25 (DOB[25], dob_out25); + buf b_dob26 (DOB[26], dob_out26); + buf b_dob27 (DOB[27], dob_out27); + buf b_dob28 (DOB[28], dob_out28); + buf b_dob29 (DOB[29], dob_out29); + buf b_dob30 (DOB[30], dob_out30); + buf b_dob31 (DOB[31], dob_out31); + buf b_dopb0 (DOPB[0], dopb_out0); + buf b_dopb1 (DOPB[1], dopb_out1); + buf b_dopb2 (DOPB[2], dopb_out2); + buf b_dopb3 (DOPB[3], dopb_out3); + + buf b_addra_0 (addra_int[0], ADDRA[0]); + buf b_addra_1 (addra_int[1], ADDRA[1]); + buf b_addra_2 (addra_int[2], ADDRA[2]); + buf b_addra_3 (addra_int[3], ADDRA[3]); + buf b_addra_4 (addra_int[4], ADDRA[4]); + buf b_addra_5 (addra_int[5], ADDRA[5]); + buf b_addra_6 (addra_int[6], ADDRA[6]); + buf b_addra_7 (addra_int[7], ADDRA[7]); + buf b_addra_8 (addra_int[8], ADDRA[8]); + buf b_addra_9 (addra_int[9], ADDRA[9]); + buf b_addra_10 (addra_int[10], ADDRA[10]); + buf b_dia_0 (dia_int[0], DIA[0]); + buf b_dia_1 (dia_int[1], DIA[1]); + buf b_dia_2 (dia_int[2], DIA[2]); + buf b_dia_3 (dia_int[3], DIA[3]); + buf b_dia_4 (dia_int[4], DIA[4]); + buf b_dia_5 (dia_int[5], DIA[5]); + buf b_dia_6 (dia_int[6], DIA[6]); + buf b_dia_7 (dia_int[7], DIA[7]); + buf b_dipa_0 (dipa_int[0], DIPA[0]); + buf b_ena (ena_int, ENA); + buf b_clka (clka_int, CLKA); + buf b_ssra (ssra_int, SSRA); + buf b_wea (wea_int, WEA); + buf b_addrb_0 (addrb_int[0], ADDRB[0]); + buf b_addrb_1 (addrb_int[1], ADDRB[1]); + buf b_addrb_2 (addrb_int[2], ADDRB[2]); + buf b_addrb_3 (addrb_int[3], ADDRB[3]); + buf b_addrb_4 (addrb_int[4], ADDRB[4]); + buf b_addrb_5 (addrb_int[5], ADDRB[5]); + buf b_addrb_6 (addrb_int[6], ADDRB[6]); + buf b_addrb_7 (addrb_int[7], ADDRB[7]); + buf b_addrb_8 (addrb_int[8], ADDRB[8]); + buf b_dib_0 (dib_int[0], DIB[0]); + buf b_dib_1 (dib_int[1], DIB[1]); + buf b_dib_2 (dib_int[2], DIB[2]); + buf b_dib_3 (dib_int[3], DIB[3]); + buf b_dib_4 (dib_int[4], DIB[4]); + buf b_dib_5 (dib_int[5], DIB[5]); + buf b_dib_6 (dib_int[6], DIB[6]); + buf b_dib_7 (dib_int[7], DIB[7]); + buf b_dib_8 (dib_int[8], DIB[8]); + buf b_dib_9 (dib_int[9], DIB[9]); + buf b_dib_10 (dib_int[10], DIB[10]); + buf b_dib_11 (dib_int[11], DIB[11]); + buf b_dib_12 (dib_int[12], DIB[12]); + buf b_dib_13 (dib_int[13], DIB[13]); + buf b_dib_14 (dib_int[14], DIB[14]); + buf b_dib_15 (dib_int[15], DIB[15]); + buf b_dib_16 (dib_int[16], DIB[16]); + buf b_dib_17 (dib_int[17], DIB[17]); + buf b_dib_18 (dib_int[18], DIB[18]); + buf b_dib_19 (dib_int[19], DIB[19]); + buf b_dib_20 (dib_int[20], DIB[20]); + buf b_dib_21 (dib_int[21], DIB[21]); + buf b_dib_22 (dib_int[22], DIB[22]); + buf b_dib_23 (dib_int[23], DIB[23]); + buf b_dib_24 (dib_int[24], DIB[24]); + buf b_dib_25 (dib_int[25], DIB[25]); + buf b_dib_26 (dib_int[26], DIB[26]); + buf b_dib_27 (dib_int[27], DIB[27]); + buf b_dib_28 (dib_int[28], DIB[28]); + buf b_dib_29 (dib_int[29], DIB[29]); + buf b_dib_30 (dib_int[30], DIB[30]); + buf b_dib_31 (dib_int[31], DIB[31]); + buf b_dipb_0 (dipb_int[0], DIPB[0]); + buf b_dipb_1 (dipb_int[1], DIPB[1]); + buf b_dipb_2 (dipb_int[2], DIPB[2]); + buf b_dipb_3 (dipb_int[3], DIPB[3]); + buf b_enb (enb_int, ENB); + buf b_clkb (clkb_int, CLKB); + buf b_ssrb (ssrb_int, SSRB); + buf b_web (web_int, WEB); + + initial begin + for (count = 0; count < 256; count = count + 1) begin + mem[count] <= INIT_00[count]; + mem[256 * 1 + count] <= INIT_01[count]; + mem[256 * 2 + count] <= INIT_02[count]; + mem[256 * 3 + count] <= INIT_03[count]; + mem[256 * 4 + count] <= INIT_04[count]; + mem[256 * 5 + count] <= INIT_05[count]; + mem[256 * 6 + count] <= INIT_06[count]; + mem[256 * 7 + count] <= INIT_07[count]; + mem[256 * 8 + count] <= INIT_08[count]; + mem[256 * 9 + count] <= INIT_09[count]; + mem[256 * 10 + count] <= INIT_0A[count]; + mem[256 * 11 + count] <= INIT_0B[count]; + mem[256 * 12 + count] <= INIT_0C[count]; + mem[256 * 13 + count] <= INIT_0D[count]; + mem[256 * 14 + count] <= INIT_0E[count]; + mem[256 * 15 + count] <= INIT_0F[count]; + mem[256 * 16 + count] <= INIT_10[count]; + mem[256 * 17 + count] <= INIT_11[count]; + mem[256 * 18 + count] <= INIT_12[count]; + mem[256 * 19 + count] <= INIT_13[count]; + mem[256 * 20 + count] <= INIT_14[count]; + mem[256 * 21 + count] <= INIT_15[count]; + mem[256 * 22 + count] <= INIT_16[count]; + mem[256 * 23 + count] <= INIT_17[count]; + mem[256 * 24 + count] <= INIT_18[count]; + mem[256 * 25 + count] <= INIT_19[count]; + mem[256 * 26 + count] <= INIT_1A[count]; + mem[256 * 27 + count] <= INIT_1B[count]; + mem[256 * 28 + count] <= INIT_1C[count]; + mem[256 * 29 + count] <= INIT_1D[count]; + mem[256 * 30 + count] <= INIT_1E[count]; + mem[256 * 31 + count] <= INIT_1F[count]; + mem[256 * 32 + count] <= INIT_20[count]; + mem[256 * 33 + count] <= INIT_21[count]; + mem[256 * 34 + count] <= INIT_22[count]; + mem[256 * 35 + count] <= INIT_23[count]; + mem[256 * 36 + count] <= INIT_24[count]; + mem[256 * 37 + count] <= INIT_25[count]; + mem[256 * 38 + count] <= INIT_26[count]; + mem[256 * 39 + count] <= INIT_27[count]; + mem[256 * 40 + count] <= INIT_28[count]; + mem[256 * 41 + count] <= INIT_29[count]; + mem[256 * 42 + count] <= INIT_2A[count]; + mem[256 * 43 + count] <= INIT_2B[count]; + mem[256 * 44 + count] <= INIT_2C[count]; + mem[256 * 45 + count] <= INIT_2D[count]; + mem[256 * 46 + count] <= INIT_2E[count]; + mem[256 * 47 + count] <= INIT_2F[count]; + mem[256 * 48 + count] <= INIT_30[count]; + mem[256 * 49 + count] <= INIT_31[count]; + mem[256 * 50 + count] <= INIT_32[count]; + mem[256 * 51 + count] <= INIT_33[count]; + mem[256 * 52 + count] <= INIT_34[count]; + mem[256 * 53 + count] <= INIT_35[count]; + mem[256 * 54 + count] <= INIT_36[count]; + mem[256 * 55 + count] <= INIT_37[count]; + mem[256 * 56 + count] <= INIT_38[count]; + mem[256 * 57 + count] <= INIT_39[count]; + mem[256 * 58 + count] <= INIT_3A[count]; + mem[256 * 59 + count] <= INIT_3B[count]; + mem[256 * 60 + count] <= INIT_3C[count]; + mem[256 * 61 + count] <= INIT_3D[count]; + mem[256 * 62 + count] <= INIT_3E[count]; + mem[256 * 63 + count] <= INIT_3F[count]; + mem[256 * 64 + count] <= INITP_00[count]; + mem[256 * 65 + count] <= INITP_01[count]; + mem[256 * 66 + count] <= INITP_02[count]; + mem[256 * 67 + count] <= INITP_03[count]; + mem[256 * 68 + count] <= INITP_04[count]; + mem[256 * 69 + count] <= INITP_05[count]; + mem[256 * 70 + count] <= INITP_06[count]; + mem[256 * 71 + count] <= INITP_07[count]; + end + address_collision <= 0; + address_collision_a_b <= 0; + address_collision_b_a <= 0; + change_clka <= 0; + change_clkb <= 0; + data_collision <= 0; + data_collision_a_b <= 0; + data_collision_b_a <= 0; + memory_collision <= 0; + memory_collision_a_b <= 0; + memory_collision_b_a <= 0; + setup_all_a_b <= 0; + setup_all_b_a <= 0; + setup_zero <= 0; + setup_rf_a_b <= 0; + setup_rf_b_a <= 0; + end + + assign data_addra_int = addra_int * 8; + assign data_addra_reg = addra_reg * 8; + assign data_addrb_int = addrb_int * 32; + assign data_addrb_reg = addrb_reg * 32; + assign parity_addra_int = 16384 + addra_int * 1; + assign parity_addra_reg = 16384 + addra_reg * 1; + assign parity_addrb_int = 16384 + addrb_int * 4; + assign parity_addrb_reg = 16384 + addrb_reg * 4; + + + initial begin + + display_flag = 1; + + case (SIM_COLLISION_CHECK) + + "NONE" : begin + assign setup_all_a_b = 1'b0; + assign setup_all_b_a = 1'b0; + assign setup_zero = 1'b0; + assign setup_rf_a_b = 1'b0; + assign setup_rf_b_a = 1'b0; + assign display_flag = 0; + end + "WARNING_ONLY" : begin + assign data_collision = 2'b00; + assign data_collision_a_b = 2'b00; + assign data_collision_b_a = 2'b00; + assign memory_collision = 1'b0; + assign memory_collision_a_b = 1'b0; + assign memory_collision_b_a = 1'b0; + end + "GENERATE_X_ONLY" : begin + assign display_flag = 0; + end + "ALL" : ; + default : begin + $display("Attribute Syntax Error : The Attribute SIM_COLLISION_CHECK on RAMB16_S9_S36 instance %m is set to %s. Legal values for this attribute are ALL, NONE, WARNING_ONLY or GENERATE_X_ONLY.", SIM_COLLISION_CHECK); + $finish; + end + + endcase // case(SIM_COLLISION_CHECK) + + end // initial begin + + + always @(posedge clka_int) begin + time_clka = $time; + #0 time_clkb_clka = time_clka - time_clkb; + change_clka = ~change_clka; + end + + always @(posedge clkb_int) begin + time_clkb = $time; + #0 time_clka_clkb = time_clkb - time_clka; + change_clkb = ~change_clkb; + end + + always @(change_clkb) begin + if ((0 < time_clka_clkb) && (time_clka_clkb < SETUP_ALL)) + setup_all_a_b = 1; + if ((0 < time_clka_clkb) && (time_clka_clkb < SETUP_READ_FIRST)) + setup_rf_a_b = 1; + end + + always @(change_clka) begin + if ((0 < time_clkb_clka) && (time_clkb_clka < SETUP_ALL)) + setup_all_b_a = 1; + if ((0 < time_clkb_clka) && (time_clkb_clka < SETUP_READ_FIRST)) + setup_rf_b_a = 1; + end + + always @(change_clkb or change_clka) begin + if ((time_clkb_clka == 0) && (time_clka_clkb == 0)) + setup_zero = 1; + end + + always @(posedge setup_zero) begin + if ((ena_int == 1) && (wea_int == 1) && + (enb_int == 1) && (web_int == 1) && + (data_addra_int[14:5] == data_addrb_int[14:5])) + memory_collision <= 1; + end + + always @(posedge setup_all_a_b or posedge setup_rf_a_b) begin + if ((ena_reg == 1) && (wea_reg == 1) && + (enb_int == 1) && (web_int == 1) && + (data_addra_reg[14:5] == data_addrb_int[14:5])) + memory_collision_a_b <= 1; + end + + always @(posedge setup_all_b_a or posedge setup_rf_b_a) begin + if ((ena_int == 1) && (wea_int == 1) && + (enb_reg == 1) && (web_reg == 1) && + (data_addra_int[14:5] == data_addrb_reg[14:5])) + memory_collision_b_a <= 1; + end + + always @(posedge setup_all_a_b) begin + if (data_addra_reg[14:5] == data_addrb_int[14:5]) begin + if ((ena_reg == 1) && (enb_int == 1)) begin + case ({wr_mode_a, wr_mode_b, wea_reg, web_int}) + 6'b000011 : begin data_collision_a_b <= 2'b11; display_wa_wb; end + 6'b000111 : begin data_collision_a_b <= 2'b11; display_wa_wb; end + 6'b001011 : begin data_collision_a_b <= 2'b10; display_wa_wb; end +// 6'b010011 : begin data_collision_a_b <= 2'b00; display_wa_wb; end +// 6'b010111 : begin data_collision_a_b <= 2'b00; display_wa_wb; end +// 6'b011011 : begin data_collision_a_b <= 2'b00; display_wa_wb; end + 6'b100011 : begin data_collision_a_b <= 2'b01; display_wa_wb; end + 6'b100111 : begin data_collision_a_b <= 2'b01; display_wa_wb; end + 6'b101011 : begin display_wa_wb; end + 6'b000001 : begin data_collision_a_b <= 2'b10; display_ra_wb; end +// 6'b000101 : begin data_collision_a_b <= 2'b00; display_ra_wb; end + 6'b001001 : begin data_collision_a_b <= 2'b10; display_ra_wb; end + 6'b010001 : begin data_collision_a_b <= 2'b10; display_ra_wb; end +// 6'b010101 : begin data_collision_a_b <= 2'b00; display_ra_wb; end + 6'b011001 : begin data_collision_a_b <= 2'b10; display_ra_wb; end + 6'b100001 : begin data_collision_a_b <= 2'b10; display_ra_wb; end +// 6'b100101 : begin data_collision_a_b <= 2'b00; display_ra_wb; end + 6'b101001 : begin data_collision_a_b <= 2'b10; display_ra_wb; end + 6'b000010 : begin data_collision_a_b <= 2'b01; display_wa_rb; end + 6'b000110 : begin data_collision_a_b <= 2'b01; display_wa_rb; end + 6'b001010 : begin data_collision_a_b <= 2'b01; display_wa_rb; end +// 6'b010010 : begin data_collision_a_b <= 2'b00; display_wa_rb; end +// 6'b010110 : begin data_collision_a_b <= 2'b00; display_wa_rb; end +// 6'b011010 : begin data_collision_a_b <= 2'b00; display_wa_rb; end + 6'b100010 : begin data_collision_a_b <= 2'b01; display_wa_rb; end + 6'b100110 : begin data_collision_a_b <= 2'b01; display_wa_rb; end + 6'b101010 : begin data_collision_a_b <= 2'b01; display_wa_rb; end + endcase + end + end + setup_all_a_b <= 0; + end + + + always @(posedge setup_all_b_a) begin + if (data_addra_int[14:5] == data_addrb_reg[14:5]) begin + if ((ena_int == 1) && (enb_reg == 1)) begin + case ({wr_mode_a, wr_mode_b, wea_int, web_reg}) + 6'b000011 : begin data_collision_b_a <= 2'b11; display_wa_wb; end +// 6'b000111 : begin data_collision_b_a <= 2'b00; display_wa_wb; end + 6'b001011 : begin data_collision_b_a <= 2'b10; display_wa_wb; end + 6'b010011 : begin data_collision_b_a <= 2'b11; display_wa_wb; end +// 6'b010111 : begin data_collision_b_a <= 2'b00; display_wa_wb; end + 6'b011011 : begin data_collision_b_a <= 2'b10; display_wa_wb; end + 6'b100011 : begin data_collision_b_a <= 2'b01; display_wa_wb; end + 6'b100111 : begin data_collision_b_a <= 2'b01; display_wa_wb; end + 6'b101011 : begin display_wa_wb; end + 6'b000001 : begin data_collision_b_a <= 2'b10; display_ra_wb; end + 6'b000101 : begin data_collision_b_a <= 2'b10; display_ra_wb; end + 6'b001001 : begin data_collision_b_a <= 2'b10; display_ra_wb; end + 6'b010001 : begin data_collision_b_a <= 2'b10; display_ra_wb; end + 6'b010101 : begin data_collision_b_a <= 2'b10; display_ra_wb; end + 6'b011001 : begin data_collision_b_a <= 2'b10; display_ra_wb; end + 6'b100001 : begin data_collision_b_a <= 2'b10; display_ra_wb; end + 6'b100101 : begin data_collision_b_a <= 2'b10; display_ra_wb; end + 6'b101001 : begin data_collision_b_a <= 2'b10; display_ra_wb; end + 6'b000010 : begin data_collision_b_a <= 2'b01; display_wa_rb; end + 6'b000110 : begin data_collision_b_a <= 2'b01; display_wa_rb; end + 6'b001010 : begin data_collision_b_a <= 2'b01; display_wa_rb; end +// 6'b010010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end +// 6'b010110 : begin data_collision_b_a <= 2'b00; display_wa_rb; end +// 6'b011010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end + 6'b100010 : begin data_collision_b_a <= 2'b01; display_wa_rb; end + 6'b100110 : begin data_collision_b_a <= 2'b01; display_wa_rb; end + 6'b101010 : begin data_collision_b_a <= 2'b01; display_wa_rb; end + endcase + end + end + setup_all_b_a <= 0; + end + + + always @(posedge setup_zero) begin + if (data_addra_int[14:5] == data_addrb_int[14:5]) begin + if ((ena_int == 1) && (enb_int == 1)) begin + case ({wr_mode_a, wr_mode_b, wea_int, web_int}) + 6'b000011 : begin data_collision <= 2'b11; display_wa_wb; end + 6'b000111 : begin data_collision <= 2'b11; display_wa_wb; end + 6'b001011 : begin data_collision <= 2'b10; display_wa_wb; end + 6'b010011 : begin data_collision <= 2'b11; display_wa_wb; end + 6'b010111 : begin data_collision <= 2'b11; display_wa_wb; end + 6'b011011 : begin data_collision <= 2'b10; display_wa_wb; end + 6'b100011 : begin data_collision <= 2'b01; display_wa_wb; end + 6'b100111 : begin data_collision <= 2'b01; display_wa_wb; end + 6'b101011 : begin display_wa_wb; end + 6'b000001 : begin data_collision <= 2'b10; display_ra_wb; end +// 6'b000101 : begin data_collision <= 2'b00; display_ra_wb; end + 6'b001001 : begin data_collision <= 2'b10; display_ra_wb; end + 6'b010001 : begin data_collision <= 2'b10; display_ra_wb; end +// 6'b010101 : begin data_collision <= 2'b00; display_ra_wb; end + 6'b011001 : begin data_collision <= 2'b10; display_ra_wb; end + 6'b100001 : begin data_collision <= 2'b10; display_ra_wb; end +// 6'b100101 : begin data_collision <= 2'b00; display_ra_wb; end + 6'b101001 : begin data_collision <= 2'b10; display_ra_wb; end + 6'b000010 : begin data_collision <= 2'b01; display_wa_rb; end + 6'b000110 : begin data_collision <= 2'b01; display_wa_rb; end + 6'b001010 : begin data_collision <= 2'b01; display_wa_rb; end +// 6'b010010 : begin data_collision <= 2'b00; display_wa_rb; end +// 6'b010110 : begin data_collision <= 2'b00; display_wa_rb; end +// 6'b011010 : begin data_collision <= 2'b00; display_wa_rb; end + 6'b100010 : begin data_collision <= 2'b01; display_wa_rb; end + 6'b100110 : begin data_collision <= 2'b01; display_wa_rb; end + 6'b101010 : begin data_collision <= 2'b01; display_wa_rb; end + endcase + end + end + setup_zero <= 0; + end + + task display_ra_wb; + begin + if (display_flag) + $display("Memory Collision Error on RAMB16_S9_S36:%m at simulation time %.3f ns\nA read was performed on address %h (hex) of Port A while a write was requested to the same address on Port B. The write will be successful however the read value on Port A is unknown until the next CLKA cycle.", $time/1000.0, addra_int); + end + endtask + + task display_wa_rb; + begin + if (display_flag) + $display("Memory Collision Error on RAMB16_S9_S36:%m at simulation time %.3f ns\nA read was performed on address %h (hex) of Port B while a write was requested to the same address on Port A. The write will be successful however the read value on Port B is unknown until the next CLKB cycle.", $time/1000.0, addrb_int); + end + endtask + + task display_wa_wb; + begin + if (display_flag) + $display("Memory Collision Error on RAMB16_S9_S36:%m at simulation time %.3f ns\nA write was requested to the same address simultaneously at both Port A and Port B of the RAM. The contents written to the RAM at address location %h (hex) of Port A and address location %h (hex) of Port B are unknown.", $time/1000.0, addra_int, addrb_int); + end + endtask + + + always @(posedge setup_rf_a_b) begin + if (data_addra_reg[14:5] == data_addrb_int[14:5]) begin + if ((ena_reg == 1) && (enb_int == 1)) begin + case ({wr_mode_a, wr_mode_b, wea_reg, web_int}) +// 6'b000011 : begin data_collision_a_b <= 2'b00; display_wa_wb; end +// 6'b000111 : begin data_collision_a_b <= 2'b00; display_wa_wb; end +// 6'b001011 : begin data_collision_a_b <= 2'b00; display_wa_wb; end + 6'b010011 : begin data_collision_a_b <= 2'b11; display_wa_wb; end + 6'b010111 : begin data_collision_a_b <= 2'b11; display_wa_wb; end + 6'b011011 : begin data_collision_a_b <= 2'b10; display_wa_wb; end +// 6'b100011 : begin data_collision_a_b <= 2'b00; display_wa_wb; end +// 6'b100111 : begin data_collision_a_b <= 2'b00; display_wa_wb; end +// 6'b101011 : begin data_collision_a_b <= 2'b00; display_wa_wb; end +// 6'b000001 : begin data_collision_a_b <= 2'b00; display_ra_wb; end +// 6'b000101 : begin data_collision_a_b <= 2'b00; display_ra_wb; end +// 6'b001001 : begin data_collision_a_b <= 2'b00; display_ra_wb; end +// 6'b010001 : begin data_collision_a_b <= 2'b00; display_ra_wb; end +// 6'b010101 : begin data_collision_a_b <= 2'b00; display_ra_wb; end +// 6'b011001 : begin data_collision_a_b <= 2'b00; display_ra_wb; end +// 6'b100001 : begin data_collision_a_b <= 2'b00; display_ra_wb; end +// 6'b100101 : begin data_collision_a_b <= 2'b00; display_ra_wb; end +// 6'b101001 : begin data_collision_a_b <= 2'b00; display_ra_wb; end +// 6'b000010 : begin data_collision_a_b <= 2'b00; display_wa_rb; end +// 6'b000110 : begin data_collision_a_b <= 2'b00; display_wa_rb; end +// 6'b001010 : begin data_collision_a_b <= 2'b00; display_wa_rb; end + 6'b010010 : begin data_collision_a_b <= 2'b01; display_wa_rb; end + 6'b010110 : begin data_collision_a_b <= 2'b01; display_wa_rb; end + 6'b011010 : begin data_collision_a_b <= 2'b01; display_wa_rb; end +// 6'b100010 : begin data_collision_a_b <= 2'b00; display_wa_rb; end +// 6'b100110 : begin data_collision_a_b <= 2'b00; display_wa_rb; end +// 6'b101010 : begin data_collision_a_b <= 2'b00; display_wa_rb; end + endcase + end + end + setup_rf_a_b <= 0; + end + + + always @(posedge setup_rf_b_a) begin + if (data_addra_int[14:5] == data_addrb_reg[14:5]) begin + if ((ena_int == 1) && (enb_reg == 1)) begin + case ({wr_mode_a, wr_mode_b, wea_int, web_reg}) +// 6'b000011 : begin data_collision_b_a <= 2'b00; display_wa_wb; end + 6'b000111 : begin data_collision_b_a <= 2'b11; display_wa_wb; end +// 6'b001011 : begin data_collision_b_a <= 2'b00; display_wa_wb; end +// 6'b010011 : begin data_collision_b_a <= 2'b00; display_wa_wb; end + 6'b010111 : begin data_collision_b_a <= 2'b11; display_wa_wb; end +// 6'b011011 : begin data_collision_b_a <= 2'b00; display_wa_wb; end +// 6'b100011 : begin data_collision_b_a <= 2'b00; display_wa_wb; end + 6'b100111 : begin data_collision_b_a <= 2'b01; display_wa_wb; end +// 6'b101011 : begin data_collision_b_a <= 2'b00; display_wa_wb; end +// 6'b000001 : begin data_collision_b_a <= 2'b00; display_ra_wb; end + 6'b000101 : begin data_collision_b_a <= 2'b10; display_ra_wb; end +// 6'b001001 : begin data_collision_b_a <= 2'b00; display_ra_wb; end +// 6'b010001 : begin data_collision_b_a <= 2'b00; display_ra_wb; end + 6'b010101 : begin data_collision_b_a <= 2'b10; display_ra_wb; end +// 6'b011001 : begin data_collision_b_a <= 2'b00; display_ra_wb; end +// 6'b100001 : begin data_collision_b_a <= 2'b00; display_ra_wb; end + 6'b100101 : begin data_collision_b_a <= 2'b10; display_ra_wb; end +// 6'b101001 : begin data_collision_b_a <= 2'b00; display_ra_wb; end +// 6'b000010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end +// 6'b000110 : begin data_collision_b_a <= 2'b00; display_wa_rb; end +// 6'b001010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end +// 6'b010010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end +// 6'b010110 : begin data_collision_b_a <= 2'b00; display_wa_rb; end +// 6'b011010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end +// 6'b100010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end +// 6'b100110 : begin data_collision_b_a <= 2'b00; display_wa_rb; end +// 6'b101010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end + endcase + end + end + setup_rf_b_a <= 0; + end + + + always @(posedge clka_int) begin + addra_reg <= addra_int; + ena_reg <= ena_int; + ssra_reg <= ssra_int; + wea_reg <= wea_int; + end + + always @(posedge clkb_int) begin + addrb_reg <= addrb_int; + enb_reg <= enb_int; + ssrb_reg <= ssrb_int; + web_reg <= web_int; + end + + // Data + always @(posedge memory_collision) begin + for (dmi = 0; dmi < 8; dmi = dmi + 1) begin + mem[data_addra_int + dmi] <= 1'bX; + end + memory_collision <= 0; + end + + always @(posedge memory_collision_a_b) begin + for (dmi = 0; dmi < 8; dmi = dmi + 1) begin + mem[data_addra_reg + dmi] <= 1'bX; + end + memory_collision_a_b <= 0; + end + + always @(posedge memory_collision_b_a) begin + for (dmi = 0; dmi < 8; dmi = dmi + 1) begin + mem[data_addra_int + dmi] <= 1'bX; + end + memory_collision_b_a <= 0; + end + + always @(posedge data_collision[1]) begin + if (ssra_int == 0) begin + doa_out <= 8'bX; + end + data_collision[1] <= 0; + end + + always @(posedge data_collision[0]) begin + if (ssrb_int == 0) begin + for (dbi = 0; dbi < 8; dbi = dbi + 1) begin + dob_out[data_addra_int[4 : 0] + dbi] <= 1'bX; + end + end + data_collision[0] <= 0; + end + + always @(posedge data_collision_a_b[1]) begin + if (ssra_reg == 0) begin + doa_out <= 8'bX; + end + data_collision_a_b[1] <= 0; + end + + always @(posedge data_collision_a_b[0]) begin + if (ssrb_int == 0) begin + for (dbi = 0; dbi < 8; dbi = dbi + 1) begin + dob_out[data_addra_reg[4 : 0] + dbi] <= 1'bX; + end + end + data_collision_a_b[0] <= 0; + end + + always @(posedge data_collision_b_a[1]) begin + if (ssra_int == 0) begin + doa_out <= 8'bX; + end + data_collision_b_a[1] <= 0; + end + + always @(posedge data_collision_b_a[0]) begin + if (ssrb_reg == 0) begin + for (dbi = 0; dbi < 8; dbi = dbi + 1) begin + dob_out[data_addra_int[4 : 0] + dbi] <= 1'bX; + end + end + data_collision_b_a[0] <= 0; + end + + + // Parity + always @(posedge memory_collision) begin + for (pmi = 0; pmi < 1; pmi = pmi + 1) begin + mem[parity_addra_int + pmi] <= 1'bX; + end + end + + always @(posedge memory_collision_a_b) begin + for (pmi = 0; pmi < 1; pmi = pmi + 1) begin + mem[parity_addra_reg + pmi] <= 1'bX; + end + end + + always @(posedge memory_collision_b_a) begin + for (pmi = 0; pmi < 1; pmi = pmi + 1) begin + mem[parity_addra_int + pmi] <= 1'bX; + end + end + + always @(posedge data_collision[1]) begin + if (ssra_int == 0) begin + dopa_out <= 1'bX; + end + end + + always @(posedge data_collision[0]) begin + if (ssrb_int == 0) begin + for (pbi = 0; pbi < 1; pbi = pbi + 1) begin + dopb_out[parity_addra_int[1 : 0] + pbi] <= 1'bX; + end + end + end + + always @(posedge data_collision_a_b[1]) begin + if (ssra_reg == 0) begin + dopa_out <= 1'bX; + end + end + + always @(posedge data_collision_a_b[0]) begin + if (ssrb_int == 0) begin + for (pbi = 0; pbi < 1; pbi = pbi + 1) begin + dopb_out[parity_addra_reg[1 : 0] + pbi] <= 1'bX; + end + end + end + + always @(posedge data_collision_b_a[1]) begin + if (ssra_int == 0) begin + dopa_out <= 1'bX; + end + end + + always @(posedge data_collision_b_a[0]) begin + if (ssrb_reg == 0) begin + for (pbi = 0; pbi < 1; pbi = pbi + 1) begin + dopb_out[parity_addra_int[1 : 0] + pbi] <= 1'bX; + end + end + end + + + initial begin + case (WRITE_MODE_A) + "WRITE_FIRST" : wr_mode_a <= 2'b00; + "READ_FIRST" : wr_mode_a <= 2'b01; + "NO_CHANGE" : wr_mode_a <= 2'b10; + default : begin + $display("Attribute Syntax Error : The Attribute WRITE_MODE_A on RAMB16_S9_S36 instance %m is set to %s. Legal values for this attribute are WRITE_FIRST, READ_FIRST or NO_CHANGE.", WRITE_MODE_A); + $finish; + end + endcase + end + + initial begin + case (WRITE_MODE_B) + "WRITE_FIRST" : wr_mode_b <= 2'b00; + "READ_FIRST" : wr_mode_b <= 2'b01; + "NO_CHANGE" : wr_mode_b <= 2'b10; + default : begin + $display("Attribute Syntax Error : The Attribute WRITE_MODE_B on RAMB16_S9_S36 instance %m is set to %s. Legal values for this attribute are WRITE_FIRST, READ_FIRST or NO_CHANGE.", WRITE_MODE_B); + $finish; + end + endcase + end + + // Port A + always @(posedge clka_int) begin + if (ena_int == 1'b1) begin + if (ssra_int == 1'b1) begin + doa_out[0] <= SRVAL_A[0]; + doa_out[1] <= SRVAL_A[1]; + doa_out[2] <= SRVAL_A[2]; + doa_out[3] <= SRVAL_A[3]; + doa_out[4] <= SRVAL_A[4]; + doa_out[5] <= SRVAL_A[5]; + doa_out[6] <= SRVAL_A[6]; + doa_out[7] <= SRVAL_A[7]; + dopa_out[0] <= SRVAL_A[8]; + end + else begin + if (wea_int == 1'b1) begin + if (wr_mode_a == 2'b00) begin + doa_out <= dia_int; + dopa_out <= dipa_int; + end + else if (wr_mode_a == 2'b01) begin + doa_out[0] <= mem[data_addra_int + 0]; + doa_out[1] <= mem[data_addra_int + 1]; + doa_out[2] <= mem[data_addra_int + 2]; + doa_out[3] <= mem[data_addra_int + 3]; + doa_out[4] <= mem[data_addra_int + 4]; + doa_out[5] <= mem[data_addra_int + 5]; + doa_out[6] <= mem[data_addra_int + 6]; + doa_out[7] <= mem[data_addra_int + 7]; + dopa_out[0] <= mem[parity_addra_int + 0]; + end + end + else begin + doa_out[0] <= mem[data_addra_int + 0]; + doa_out[1] <= mem[data_addra_int + 1]; + doa_out[2] <= mem[data_addra_int + 2]; + doa_out[3] <= mem[data_addra_int + 3]; + doa_out[4] <= mem[data_addra_int + 4]; + doa_out[5] <= mem[data_addra_int + 5]; + doa_out[6] <= mem[data_addra_int + 6]; + doa_out[7] <= mem[data_addra_int + 7]; + dopa_out[0] <= mem[parity_addra_int + 0]; + end + end + end + end + + always @(posedge clka_int) begin + if (ena_int == 1'b1 && wea_int == 1'b1) begin + mem[data_addra_int + 0] <= dia_int[0]; + mem[data_addra_int + 1] <= dia_int[1]; + mem[data_addra_int + 2] <= dia_int[2]; + mem[data_addra_int + 3] <= dia_int[3]; + mem[data_addra_int + 4] <= dia_int[4]; + mem[data_addra_int + 5] <= dia_int[5]; + mem[data_addra_int + 6] <= dia_int[6]; + mem[data_addra_int + 7] <= dia_int[7]; + mem[parity_addra_int + 0] <= dipa_int[0]; + end + end + + // Port B + always @(posedge clkb_int) begin + if (enb_int == 1'b1) begin + if (ssrb_int == 1'b1) begin + dob_out[0] <= SRVAL_B[0]; + dob_out[1] <= SRVAL_B[1]; + dob_out[2] <= SRVAL_B[2]; + dob_out[3] <= SRVAL_B[3]; + dob_out[4] <= SRVAL_B[4]; + dob_out[5] <= SRVAL_B[5]; + dob_out[6] <= SRVAL_B[6]; + dob_out[7] <= SRVAL_B[7]; + dob_out[8] <= SRVAL_B[8]; + dob_out[9] <= SRVAL_B[9]; + dob_out[10] <= SRVAL_B[10]; + dob_out[11] <= SRVAL_B[11]; + dob_out[12] <= SRVAL_B[12]; + dob_out[13] <= SRVAL_B[13]; + dob_out[14] <= SRVAL_B[14]; + dob_out[15] <= SRVAL_B[15]; + dob_out[16] <= SRVAL_B[16]; + dob_out[17] <= SRVAL_B[17]; + dob_out[18] <= SRVAL_B[18]; + dob_out[19] <= SRVAL_B[19]; + dob_out[20] <= SRVAL_B[20]; + dob_out[21] <= SRVAL_B[21]; + dob_out[22] <= SRVAL_B[22]; + dob_out[23] <= SRVAL_B[23]; + dob_out[24] <= SRVAL_B[24]; + dob_out[25] <= SRVAL_B[25]; + dob_out[26] <= SRVAL_B[26]; + dob_out[27] <= SRVAL_B[27]; + dob_out[28] <= SRVAL_B[28]; + dob_out[29] <= SRVAL_B[29]; + dob_out[30] <= SRVAL_B[30]; + dob_out[31] <= SRVAL_B[31]; + dopb_out[0] <= SRVAL_B[32]; + dopb_out[1] <= SRVAL_B[33]; + dopb_out[2] <= SRVAL_B[34]; + dopb_out[3] <= SRVAL_B[35]; + end + else begin + if (web_int == 1'b1) begin + if (wr_mode_b == 2'b00) begin + dob_out <= dib_int; + dopb_out <= dipb_int; + end + else if (wr_mode_b == 2'b01) begin + dob_out[0] <= mem[data_addrb_int + 0]; + dob_out[1] <= mem[data_addrb_int + 1]; + dob_out[2] <= mem[data_addrb_int + 2]; + dob_out[3] <= mem[data_addrb_int + 3]; + dob_out[4] <= mem[data_addrb_int + 4]; + dob_out[5] <= mem[data_addrb_int + 5]; + dob_out[6] <= mem[data_addrb_int + 6]; + dob_out[7] <= mem[data_addrb_int + 7]; + dob_out[8] <= mem[data_addrb_int + 8]; + dob_out[9] <= mem[data_addrb_int + 9]; + dob_out[10] <= mem[data_addrb_int + 10]; + dob_out[11] <= mem[data_addrb_int + 11]; + dob_out[12] <= mem[data_addrb_int + 12]; + dob_out[13] <= mem[data_addrb_int + 13]; + dob_out[14] <= mem[data_addrb_int + 14]; + dob_out[15] <= mem[data_addrb_int + 15]; + dob_out[16] <= mem[data_addrb_int + 16]; + dob_out[17] <= mem[data_addrb_int + 17]; + dob_out[18] <= mem[data_addrb_int + 18]; + dob_out[19] <= mem[data_addrb_int + 19]; + dob_out[20] <= mem[data_addrb_int + 20]; + dob_out[21] <= mem[data_addrb_int + 21]; + dob_out[22] <= mem[data_addrb_int + 22]; + dob_out[23] <= mem[data_addrb_int + 23]; + dob_out[24] <= mem[data_addrb_int + 24]; + dob_out[25] <= mem[data_addrb_int + 25]; + dob_out[26] <= mem[data_addrb_int + 26]; + dob_out[27] <= mem[data_addrb_int + 27]; + dob_out[28] <= mem[data_addrb_int + 28]; + dob_out[29] <= mem[data_addrb_int + 29]; + dob_out[30] <= mem[data_addrb_int + 30]; + dob_out[31] <= mem[data_addrb_int + 31]; + dopb_out[0] <= mem[parity_addrb_int + 0]; + dopb_out[1] <= mem[parity_addrb_int + 1]; + dopb_out[2] <= mem[parity_addrb_int + 2]; + dopb_out[3] <= mem[parity_addrb_int + 3]; + end + end + else begin + dob_out[0] <= mem[data_addrb_int + 0]; + dob_out[1] <= mem[data_addrb_int + 1]; + dob_out[2] <= mem[data_addrb_int + 2]; + dob_out[3] <= mem[data_addrb_int + 3]; + dob_out[4] <= mem[data_addrb_int + 4]; + dob_out[5] <= mem[data_addrb_int + 5]; + dob_out[6] <= mem[data_addrb_int + 6]; + dob_out[7] <= mem[data_addrb_int + 7]; + dob_out[8] <= mem[data_addrb_int + 8]; + dob_out[9] <= mem[data_addrb_int + 9]; + dob_out[10] <= mem[data_addrb_int + 10]; + dob_out[11] <= mem[data_addrb_int + 11]; + dob_out[12] <= mem[data_addrb_int + 12]; + dob_out[13] <= mem[data_addrb_int + 13]; + dob_out[14] <= mem[data_addrb_int + 14]; + dob_out[15] <= mem[data_addrb_int + 15]; + dob_out[16] <= mem[data_addrb_int + 16]; + dob_out[17] <= mem[data_addrb_int + 17]; + dob_out[18] <= mem[data_addrb_int + 18]; + dob_out[19] <= mem[data_addrb_int + 19]; + dob_out[20] <= mem[data_addrb_int + 20]; + dob_out[21] <= mem[data_addrb_int + 21]; + dob_out[22] <= mem[data_addrb_int + 22]; + dob_out[23] <= mem[data_addrb_int + 23]; + dob_out[24] <= mem[data_addrb_int + 24]; + dob_out[25] <= mem[data_addrb_int + 25]; + dob_out[26] <= mem[data_addrb_int + 26]; + dob_out[27] <= mem[data_addrb_int + 27]; + dob_out[28] <= mem[data_addrb_int + 28]; + dob_out[29] <= mem[data_addrb_int + 29]; + dob_out[30] <= mem[data_addrb_int + 30]; + dob_out[31] <= mem[data_addrb_int + 31]; + dopb_out[0] <= mem[parity_addrb_int + 0]; + dopb_out[1] <= mem[parity_addrb_int + 1]; + dopb_out[2] <= mem[parity_addrb_int + 2]; + dopb_out[3] <= mem[parity_addrb_int + 3]; + end + end + end + end + + always @(posedge clkb_int) begin + if (enb_int == 1'b1 && web_int == 1'b1) begin + mem[data_addrb_int + 0] <= dib_int[0]; + mem[data_addrb_int + 1] <= dib_int[1]; + mem[data_addrb_int + 2] <= dib_int[2]; + mem[data_addrb_int + 3] <= dib_int[3]; + mem[data_addrb_int + 4] <= dib_int[4]; + mem[data_addrb_int + 5] <= dib_int[5]; + mem[data_addrb_int + 6] <= dib_int[6]; + mem[data_addrb_int + 7] <= dib_int[7]; + mem[data_addrb_int + 8] <= dib_int[8]; + mem[data_addrb_int + 9] <= dib_int[9]; + mem[data_addrb_int + 10] <= dib_int[10]; + mem[data_addrb_int + 11] <= dib_int[11]; + mem[data_addrb_int + 12] <= dib_int[12]; + mem[data_addrb_int + 13] <= dib_int[13]; + mem[data_addrb_int + 14] <= dib_int[14]; + mem[data_addrb_int + 15] <= dib_int[15]; + mem[data_addrb_int + 16] <= dib_int[16]; + mem[data_addrb_int + 17] <= dib_int[17]; + mem[data_addrb_int + 18] <= dib_int[18]; + mem[data_addrb_int + 19] <= dib_int[19]; + mem[data_addrb_int + 20] <= dib_int[20]; + mem[data_addrb_int + 21] <= dib_int[21]; + mem[data_addrb_int + 22] <= dib_int[22]; + mem[data_addrb_int + 23] <= dib_int[23]; + mem[data_addrb_int + 24] <= dib_int[24]; + mem[data_addrb_int + 25] <= dib_int[25]; + mem[data_addrb_int + 26] <= dib_int[26]; + mem[data_addrb_int + 27] <= dib_int[27]; + mem[data_addrb_int + 28] <= dib_int[28]; + mem[data_addrb_int + 29] <= dib_int[29]; + mem[data_addrb_int + 30] <= dib_int[30]; + mem[data_addrb_int + 31] <= dib_int[31]; + mem[parity_addrb_int + 0] <= dipb_int[0]; + mem[parity_addrb_int + 1] <= dipb_int[1]; + mem[parity_addrb_int + 2] <= dipb_int[2]; + mem[parity_addrb_int + 3] <= dipb_int[3]; + end + end + + specify + (CLKA *> DOA) = (100, 100); + (CLKA *> DOPA) = (100, 100); + (CLKB *> DOB) = (100, 100); + (CLKB *> DOPB) = (100, 100); + endspecify + +endmodule + +`else + +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/RAMB16_S9_S36.v,v 1.10 2007/02/22 01:58:06 wloo Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2005 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Timing Simulation Library Component +// / / 16K-Bit Data and 2K-Bit Parity Dual Port Block RAM +// /___/ /\ Filename : RAMB16_S9_S36.v +// \ \ / \ Timestamp : Thu Mar 10 16:44:01 PST 2005 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 03/10/05 - Initialized outputs. +// 02/21/07 - Fixed parameter SIM_COLLISION_CHECK (CR 433281). +// End Revision + +`timescale 1 ps/1 ps + +module RAMB16_S9_S36 (DOA, DOB, DOPA, DOPB, ADDRA, ADDRB, CLKA, CLKB, DIA, DIB, DIPA, DIPB, ENA, ENB, SSRA, SSRB, WEA, WEB); + + parameter INIT_A = 9'h0; + parameter INIT_B = 36'h0; + parameter SRVAL_A = 9'h0; + parameter SRVAL_B = 36'h0; + parameter WRITE_MODE_A = "WRITE_FIRST"; + parameter WRITE_MODE_B = "WRITE_FIRST"; + parameter SIM_COLLISION_CHECK = "ALL"; + localparam SETUP_ALL = 1000; + localparam SETUP_READ_FIRST = 3000; + + parameter INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + + output [7:0] DOA; + output [0:0] DOPA; + output [31:0] DOB; + output [3:0] DOPB; + + input [10:0] ADDRA; + input [7:0] DIA; + input [0:0] DIPA; + input ENA, CLKA, WEA, SSRA; + input [8:0] ADDRB; + input [31:0] DIB; + input [3:0] DIPB; + input ENB, CLKB, WEB, SSRB; + + reg [7:0] doa_out = INIT_A[7:0]; + reg [0:0] dopa_out = INIT_A[8:8]; + reg [31:0] dob_out = INIT_B[31:0]; + reg [3:0] dopb_out = INIT_B[35:32]; + + reg [31:0] mem [511:0]; + reg [3:0] memp [511:0]; + + reg [8:0] count, countp; + reg [1:0] wr_mode_a, wr_mode_b; + + reg [5:0] dmi, dbi; + reg [5:0] pmi, pbi; + + wire [10:0] addra_int; + reg [10:0] addra_reg; + wire [7:0] dia_int; + wire [0:0] dipa_int; + wire ena_int, clka_int, wea_int, ssra_int; + reg ena_reg, wea_reg, ssra_reg; + wire [8:0] addrb_int; + reg [8:0] addrb_reg; + wire [31:0] dib_int; + wire [3:0] dipb_int; + wire enb_int, clkb_int, web_int, ssrb_int; + reg display_flag, output_flag; + reg enb_reg, web_reg, ssrb_reg; + + time time_clka, time_clkb; + time time_clka_clkb; + time time_clkb_clka; + + reg setup_all_a_b; + reg setup_all_b_a; + reg setup_zero; + reg setup_rf_a_b; + reg setup_rf_b_a; + reg [1:0] data_collision, data_collision_a_b, data_collision_b_a; + reg memory_collision, memory_collision_a_b, memory_collision_b_a; + reg change_clka; + reg change_clkb; + + wire [14:0] data_addra_int; + wire [14:0] data_addra_reg; + wire [14:0] data_addrb_int; + wire [14:0] data_addrb_reg; + + wire dia_enable = ena_int && wea_int; + wire dib_enable = enb_int && web_int; + + tri0 GSR = glbl.GSR; + wire gsr_int; + + buf b_gsr (gsr_int, GSR); + + buf b_doa [7:0] (DOA, doa_out); + buf b_dopa [0:0] (DOPA, dopa_out); + buf b_addra [10:0] (addra_int, ADDRA); + buf b_dia [7:0] (dia_int, DIA); + buf b_dipa [0:0] (dipa_int, DIPA); + buf b_ena (ena_int, ENA); + buf b_clka (clka_int, CLKA); + buf b_ssra (ssra_int, SSRA); + buf b_wea (wea_int, WEA); + + buf b_dob [31:0] (DOB, dob_out); + buf b_dopb [3:0] (DOPB, dopb_out); + buf b_addrb [8:0] (addrb_int, ADDRB); + buf b_dib [31:0] (dib_int, DIB); + buf b_dipb [3:0] (dipb_int, DIPB); + buf b_enb (enb_int, ENB); + buf b_clkb (clkb_int, CLKB); + buf b_ssrb (ssrb_int, SSRB); + buf b_web (web_int, WEB); + + + always @(gsr_int) + if (gsr_int) begin + assign {dopa_out, doa_out} = INIT_A; + assign {dopb_out, dob_out} = INIT_B; + end + else begin + deassign doa_out; + deassign dopa_out; + deassign dob_out; + deassign dopb_out; + end + + + initial begin + + for (count = 0; count < 8; count = count + 1) begin + mem[count] = INIT_00[(count * 32) +: 32]; + mem[8 * 1 + count] = INIT_01[(count * 32) +: 32]; + mem[8 * 2 + count] = INIT_02[(count * 32) +: 32]; + mem[8 * 3 + count] = INIT_03[(count * 32) +: 32]; + mem[8 * 4 + count] = INIT_04[(count * 32) +: 32]; + mem[8 * 5 + count] = INIT_05[(count * 32) +: 32]; + mem[8 * 6 + count] = INIT_06[(count * 32) +: 32]; + mem[8 * 7 + count] = INIT_07[(count * 32) +: 32]; + mem[8 * 8 + count] = INIT_08[(count * 32) +: 32]; + mem[8 * 9 + count] = INIT_09[(count * 32) +: 32]; + mem[8 * 10 + count] = INIT_0A[(count * 32) +: 32]; + mem[8 * 11 + count] = INIT_0B[(count * 32) +: 32]; + mem[8 * 12 + count] = INIT_0C[(count * 32) +: 32]; + mem[8 * 13 + count] = INIT_0D[(count * 32) +: 32]; + mem[8 * 14 + count] = INIT_0E[(count * 32) +: 32]; + mem[8 * 15 + count] = INIT_0F[(count * 32) +: 32]; + mem[8 * 16 + count] = INIT_10[(count * 32) +: 32]; + mem[8 * 17 + count] = INIT_11[(count * 32) +: 32]; + mem[8 * 18 + count] = INIT_12[(count * 32) +: 32]; + mem[8 * 19 + count] = INIT_13[(count * 32) +: 32]; + mem[8 * 20 + count] = INIT_14[(count * 32) +: 32]; + mem[8 * 21 + count] = INIT_15[(count * 32) +: 32]; + mem[8 * 22 + count] = INIT_16[(count * 32) +: 32]; + mem[8 * 23 + count] = INIT_17[(count * 32) +: 32]; + mem[8 * 24 + count] = INIT_18[(count * 32) +: 32]; + mem[8 * 25 + count] = INIT_19[(count * 32) +: 32]; + mem[8 * 26 + count] = INIT_1A[(count * 32) +: 32]; + mem[8 * 27 + count] = INIT_1B[(count * 32) +: 32]; + mem[8 * 28 + count] = INIT_1C[(count * 32) +: 32]; + mem[8 * 29 + count] = INIT_1D[(count * 32) +: 32]; + mem[8 * 30 + count] = INIT_1E[(count * 32) +: 32]; + mem[8 * 31 + count] = INIT_1F[(count * 32) +: 32]; + mem[8 * 32 + count] = INIT_20[(count * 32) +: 32]; + mem[8 * 33 + count] = INIT_21[(count * 32) +: 32]; + mem[8 * 34 + count] = INIT_22[(count * 32) +: 32]; + mem[8 * 35 + count] = INIT_23[(count * 32) +: 32]; + mem[8 * 36 + count] = INIT_24[(count * 32) +: 32]; + mem[8 * 37 + count] = INIT_25[(count * 32) +: 32]; + mem[8 * 38 + count] = INIT_26[(count * 32) +: 32]; + mem[8 * 39 + count] = INIT_27[(count * 32) +: 32]; + mem[8 * 40 + count] = INIT_28[(count * 32) +: 32]; + mem[8 * 41 + count] = INIT_29[(count * 32) +: 32]; + mem[8 * 42 + count] = INIT_2A[(count * 32) +: 32]; + mem[8 * 43 + count] = INIT_2B[(count * 32) +: 32]; + mem[8 * 44 + count] = INIT_2C[(count * 32) +: 32]; + mem[8 * 45 + count] = INIT_2D[(count * 32) +: 32]; + mem[8 * 46 + count] = INIT_2E[(count * 32) +: 32]; + mem[8 * 47 + count] = INIT_2F[(count * 32) +: 32]; + mem[8 * 48 + count] = INIT_30[(count * 32) +: 32]; + mem[8 * 49 + count] = INIT_31[(count * 32) +: 32]; + mem[8 * 50 + count] = INIT_32[(count * 32) +: 32]; + mem[8 * 51 + count] = INIT_33[(count * 32) +: 32]; + mem[8 * 52 + count] = INIT_34[(count * 32) +: 32]; + mem[8 * 53 + count] = INIT_35[(count * 32) +: 32]; + mem[8 * 54 + count] = INIT_36[(count * 32) +: 32]; + mem[8 * 55 + count] = INIT_37[(count * 32) +: 32]; + mem[8 * 56 + count] = INIT_38[(count * 32) +: 32]; + mem[8 * 57 + count] = INIT_39[(count * 32) +: 32]; + mem[8 * 58 + count] = INIT_3A[(count * 32) +: 32]; + mem[8 * 59 + count] = INIT_3B[(count * 32) +: 32]; + mem[8 * 60 + count] = INIT_3C[(count * 32) +: 32]; + mem[8 * 61 + count] = INIT_3D[(count * 32) +: 32]; + mem[8 * 62 + count] = INIT_3E[(count * 32) +: 32]; + mem[8 * 63 + count] = INIT_3F[(count * 32) +: 32]; + end + +// initiate parity start + for (countp = 0; countp < 64; countp = countp + 1) begin + memp[countp] = INITP_00[(countp * 4) +: 4]; + memp[64 * 1 + countp] = INITP_01[(countp * 4) +: 4]; + memp[64 * 2 + countp] = INITP_02[(countp * 4) +: 4]; + memp[64 * 3 + countp] = INITP_03[(countp * 4) +: 4]; + memp[64 * 4 + countp] = INITP_04[(countp * 4) +: 4]; + memp[64 * 5 + countp] = INITP_05[(countp * 4) +: 4]; + memp[64 * 6 + countp] = INITP_06[(countp * 4) +: 4]; + memp[64 * 7 + countp] = INITP_07[(countp * 4) +: 4]; + end +// initiate parity end + + change_clka <= 0; + change_clkb <= 0; + data_collision <= 0; + data_collision_a_b <= 0; + data_collision_b_a <= 0; + memory_collision <= 0; + memory_collision_a_b <= 0; + memory_collision_b_a <= 0; + setup_all_a_b <= 0; + setup_all_b_a <= 0; + setup_zero <= 0; + setup_rf_a_b <= 0; + setup_rf_b_a <= 0; + end + + assign data_addra_int = addra_int * 8; + assign data_addra_reg = addra_reg * 8; + assign data_addrb_int = addrb_int * 32; + assign data_addrb_reg = addrb_reg * 32; + + + initial begin + + display_flag = 1; + output_flag = 1; + + case (SIM_COLLISION_CHECK) + + "NONE" : begin + output_flag = 0; + display_flag = 0; + end + "WARNING_ONLY" : output_flag = 0; + "GENERATE_X_ONLY" : display_flag = 0; + "ALL" : ; + + default : begin + $display("Attribute Syntax Error : The Attribute SIM_COLLISION_CHECK on RAMB16_S9_S36 instance %m is set to %s. Legal values for this attribute are ALL, NONE, WARNING_ONLY or GENERATE_X_ONLY.", SIM_COLLISION_CHECK); + $finish; + end + + endcase // case(SIM_COLLISION_CHECK) + + end // initial begin + + + always @(posedge clka_int) begin + if ((output_flag || display_flag)) begin + time_clka = $time; + #0 time_clkb_clka = time_clka - time_clkb; + change_clka = ~change_clka; + end + end + + always @(posedge clkb_int) begin + if ((output_flag || display_flag)) begin + time_clkb = $time; + #0 time_clka_clkb = time_clkb - time_clka; + change_clkb = ~change_clkb; + end + end + + always @(change_clkb) begin + if ((0 < time_clka_clkb) && (time_clka_clkb < SETUP_ALL)) + setup_all_a_b = 1; + if ((0 < time_clka_clkb) && (time_clka_clkb < SETUP_READ_FIRST)) + setup_rf_a_b = 1; + end + + always @(change_clka) begin + if ((0 < time_clkb_clka) && (time_clkb_clka < SETUP_ALL)) + setup_all_b_a = 1; + if ((0 < time_clkb_clka) && (time_clkb_clka < SETUP_READ_FIRST)) + setup_rf_b_a = 1; + end + + always @(change_clkb or change_clka) begin + if ((time_clkb_clka == 0) && (time_clka_clkb == 0)) + setup_zero = 1; + end + + always @(posedge setup_zero) begin + if ((ena_int == 1) && (wea_int == 1) && + (enb_int == 1) && (web_int == 1) && + (data_addra_int[14:5] == data_addrb_int[14:5])) + memory_collision <= 1; + end + + always @(posedge setup_all_a_b or posedge setup_rf_a_b) begin + if ((ena_reg == 1) && (wea_reg == 1) && + (enb_int == 1) && (web_int == 1) && + (data_addra_reg[14:5] == data_addrb_int[14:5])) + memory_collision_a_b <= 1; + end + + always @(posedge setup_all_b_a or posedge setup_rf_b_a) begin + if ((ena_int == 1) && (wea_int == 1) && + (enb_reg == 1) && (web_reg == 1) && + (data_addra_int[14:5] == data_addrb_reg[14:5])) + memory_collision_b_a <= 1; + end + + always @(posedge setup_all_a_b) begin + if (data_addra_reg[14:5] == data_addrb_int[14:5]) begin + if ((ena_reg == 1) && (enb_int == 1)) begin + case ({wr_mode_a, wr_mode_b, wea_reg, web_int}) + 6'b000011 : begin data_collision_a_b <= 2'b11; display_wa_wb; end + 6'b000111 : begin data_collision_a_b <= 2'b11; display_wa_wb; end + 6'b001011 : begin data_collision_a_b <= 2'b10; display_wa_wb; end +// 6'b010011 : begin data_collision_a_b <= 2'b00; display_wa_wb; end +// 6'b010111 : begin data_collision_a_b <= 2'b00; display_wa_wb; end +// 6'b011011 : begin data_collision_a_b <= 2'b00; display_wa_wb; end + 6'b100011 : begin data_collision_a_b <= 2'b01; display_wa_wb; end + 6'b100111 : begin data_collision_a_b <= 2'b01; display_wa_wb; end + 6'b101011 : begin display_wa_wb; end + 6'b000001 : begin data_collision_a_b <= 2'b10; display_ra_wb; end +// 6'b000101 : begin data_collision_a_b <= 2'b00; display_ra_wb; end + 6'b001001 : begin data_collision_a_b <= 2'b10; display_ra_wb; end + 6'b010001 : begin data_collision_a_b <= 2'b10; display_ra_wb; end +// 6'b010101 : begin data_collision_a_b <= 2'b00; display_ra_wb; end + 6'b011001 : begin data_collision_a_b <= 2'b10; display_ra_wb; end + 6'b100001 : begin data_collision_a_b <= 2'b10; display_ra_wb; end +// 6'b100101 : begin data_collision_a_b <= 2'b00; display_ra_wb; end + 6'b101001 : begin data_collision_a_b <= 2'b10; display_ra_wb; end + 6'b000010 : begin data_collision_a_b <= 2'b01; display_wa_rb; end + 6'b000110 : begin data_collision_a_b <= 2'b01; display_wa_rb; end + 6'b001010 : begin data_collision_a_b <= 2'b01; display_wa_rb; end +// 6'b010010 : begin data_collision_a_b <= 2'b00; display_wa_rb; end +// 6'b010110 : begin data_collision_a_b <= 2'b00; display_wa_rb; end +// 6'b011010 : begin data_collision_a_b <= 2'b00; display_wa_rb; end + 6'b100010 : begin data_collision_a_b <= 2'b01; display_wa_rb; end + 6'b100110 : begin data_collision_a_b <= 2'b01; display_wa_rb; end + 6'b101010 : begin data_collision_a_b <= 2'b01; display_wa_rb; end + endcase + end + end + setup_all_a_b <= 0; + end + + + always @(posedge setup_all_b_a) begin + if (data_addra_int[14:5] == data_addrb_reg[14:5]) begin + if ((ena_int == 1) && (enb_reg == 1)) begin + case ({wr_mode_a, wr_mode_b, wea_int, web_reg}) + 6'b000011 : begin data_collision_b_a <= 2'b11; display_wa_wb; end +// 6'b000111 : begin data_collision_b_a <= 2'b00; display_wa_wb; end + 6'b001011 : begin data_collision_b_a <= 2'b10; display_wa_wb; end + 6'b010011 : begin data_collision_b_a <= 2'b11; display_wa_wb; end +// 6'b010111 : begin data_collision_b_a <= 2'b00; display_wa_wb; end + 6'b011011 : begin data_collision_b_a <= 2'b10; display_wa_wb; end + 6'b100011 : begin data_collision_b_a <= 2'b01; display_wa_wb; end + 6'b100111 : begin data_collision_b_a <= 2'b01; display_wa_wb; end + 6'b101011 : begin display_wa_wb; end + 6'b000001 : begin data_collision_b_a <= 2'b10; display_ra_wb; end + 6'b000101 : begin data_collision_b_a <= 2'b10; display_ra_wb; end + 6'b001001 : begin data_collision_b_a <= 2'b10; display_ra_wb; end + 6'b010001 : begin data_collision_b_a <= 2'b10; display_ra_wb; end + 6'b010101 : begin data_collision_b_a <= 2'b10; display_ra_wb; end + 6'b011001 : begin data_collision_b_a <= 2'b10; display_ra_wb; end + 6'b100001 : begin data_collision_b_a <= 2'b10; display_ra_wb; end + 6'b100101 : begin data_collision_b_a <= 2'b10; display_ra_wb; end + 6'b101001 : begin data_collision_b_a <= 2'b10; display_ra_wb; end + 6'b000010 : begin data_collision_b_a <= 2'b01; display_wa_rb; end + 6'b000110 : begin data_collision_b_a <= 2'b01; display_wa_rb; end + 6'b001010 : begin data_collision_b_a <= 2'b01; display_wa_rb; end +// 6'b010010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end +// 6'b010110 : begin data_collision_b_a <= 2'b00; display_wa_rb; end +// 6'b011010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end + 6'b100010 : begin data_collision_b_a <= 2'b01; display_wa_rb; end + 6'b100110 : begin data_collision_b_a <= 2'b01; display_wa_rb; end + 6'b101010 : begin data_collision_b_a <= 2'b01; display_wa_rb; end + endcase + end + end + setup_all_b_a <= 0; + end + + + always @(posedge setup_zero) begin + if (data_addra_int[14:5] == data_addrb_int[14:5]) begin + if ((ena_int == 1) && (enb_int == 1)) begin + case ({wr_mode_a, wr_mode_b, wea_int, web_int}) + 6'b000011 : begin data_collision <= 2'b11; display_wa_wb; end + 6'b000111 : begin data_collision <= 2'b11; display_wa_wb; end + 6'b001011 : begin data_collision <= 2'b10; display_wa_wb; end + 6'b010011 : begin data_collision <= 2'b11; display_wa_wb; end + 6'b010111 : begin data_collision <= 2'b11; display_wa_wb; end + 6'b011011 : begin data_collision <= 2'b10; display_wa_wb; end + 6'b100011 : begin data_collision <= 2'b01; display_wa_wb; end + 6'b100111 : begin data_collision <= 2'b01; display_wa_wb; end + 6'b101011 : begin display_wa_wb; end + 6'b000001 : begin data_collision <= 2'b10; display_ra_wb; end +// 6'b000101 : begin data_collision <= 2'b00; display_ra_wb; end + 6'b001001 : begin data_collision <= 2'b10; display_ra_wb; end + 6'b010001 : begin data_collision <= 2'b10; display_ra_wb; end +// 6'b010101 : begin data_collision <= 2'b00; display_ra_wb; end + 6'b011001 : begin data_collision <= 2'b10; display_ra_wb; end + 6'b100001 : begin data_collision <= 2'b10; display_ra_wb; end +// 6'b100101 : begin data_collision <= 2'b00; display_ra_wb; end + 6'b101001 : begin data_collision <= 2'b10; display_ra_wb; end + 6'b000010 : begin data_collision <= 2'b01; display_wa_rb; end + 6'b000110 : begin data_collision <= 2'b01; display_wa_rb; end + 6'b001010 : begin data_collision <= 2'b01; display_wa_rb; end +// 6'b010010 : begin data_collision <= 2'b00; display_wa_rb; end +// 6'b010110 : begin data_collision <= 2'b00; display_wa_rb; end +// 6'b011010 : begin data_collision <= 2'b00; display_wa_rb; end + 6'b100010 : begin data_collision <= 2'b01; display_wa_rb; end + 6'b100110 : begin data_collision <= 2'b01; display_wa_rb; end + 6'b101010 : begin data_collision <= 2'b01; display_wa_rb; end + endcase + end + end + setup_zero <= 0; + end + + task display_ra_wb; + begin + if (display_flag) + $display("Memory Collision Error on RAMB16_S9_S36:%m at simulation time %.3f ns\nA read was performed on address %h (hex) of Port A while a write was requested to the same address on Port B. The write will be successful however the read value on Port A is unknown until the next CLKA cycle.", $time/1000.0, addra_int); + end + endtask + + task display_wa_rb; + begin + if (display_flag) + $display("Memory Collision Error on RAMB16_S9_S36:%m at simulation time %.3f ns\nA read was performed on address %h (hex) of Port B while a write was requested to the same address on Port A. The write will be successful however the read value on Port B is unknown until the next CLKB cycle.", $time/1000.0, addrb_int); + end + endtask + + task display_wa_wb; + begin + if (display_flag) + $display("Memory Collision Error on RAMB16_S9_S36:%m at simulation time %.3f ns\nA write was requested to the same address simultaneously at both Port A and Port B of the RAM. The contents written to the RAM at address location %h (hex) of Port A and address location %h (hex) of Port B are unknown.", $time/1000.0, addra_int, addrb_int); + end + endtask + + + always @(posedge setup_rf_a_b) begin + if (data_addra_reg[14:5] == data_addrb_int[14:5]) begin + if ((ena_reg == 1) && (enb_int == 1)) begin + case ({wr_mode_a, wr_mode_b, wea_reg, web_int}) +// 6'b000011 : begin data_collision_a_b <= 2'b00; display_wa_wb; end +// 6'b000111 : begin data_collision_a_b <= 2'b00; display_wa_wb; end +// 6'b001011 : begin data_collision_a_b <= 2'b00; display_wa_wb; end + 6'b010011 : begin data_collision_a_b <= 2'b11; display_wa_wb; end + 6'b010111 : begin data_collision_a_b <= 2'b11; display_wa_wb; end + 6'b011011 : begin data_collision_a_b <= 2'b10; display_wa_wb; end +// 6'b100011 : begin data_collision_a_b <= 2'b00; display_wa_wb; end +// 6'b100111 : begin data_collision_a_b <= 2'b00; display_wa_wb; end +// 6'b101011 : begin data_collision_a_b <= 2'b00; display_wa_wb; end +// 6'b000001 : begin data_collision_a_b <= 2'b00; display_ra_wb; end +// 6'b000101 : begin data_collision_a_b <= 2'b00; display_ra_wb; end +// 6'b001001 : begin data_collision_a_b <= 2'b00; display_ra_wb; end +// 6'b010001 : begin data_collision_a_b <= 2'b00; display_ra_wb; end +// 6'b010101 : begin data_collision_a_b <= 2'b00; display_ra_wb; end +// 6'b011001 : begin data_collision_a_b <= 2'b00; display_ra_wb; end +// 6'b100001 : begin data_collision_a_b <= 2'b00; display_ra_wb; end +// 6'b100101 : begin data_collision_a_b <= 2'b00; display_ra_wb; end +// 6'b101001 : begin data_collision_a_b <= 2'b00; display_ra_wb; end +// 6'b000010 : begin data_collision_a_b <= 2'b00; display_wa_rb; end +// 6'b000110 : begin data_collision_a_b <= 2'b00; display_wa_rb; end +// 6'b001010 : begin data_collision_a_b <= 2'b00; display_wa_rb; end + 6'b010010 : begin data_collision_a_b <= 2'b01; display_wa_rb; end + 6'b010110 : begin data_collision_a_b <= 2'b01; display_wa_rb; end + 6'b011010 : begin data_collision_a_b <= 2'b01; display_wa_rb; end +// 6'b100010 : begin data_collision_a_b <= 2'b00; display_wa_rb; end +// 6'b100110 : begin data_collision_a_b <= 2'b00; display_wa_rb; end +// 6'b101010 : begin data_collision_a_b <= 2'b00; display_wa_rb; end + endcase + end + end + setup_rf_a_b <= 0; + end + + + always @(posedge setup_rf_b_a) begin + if (data_addra_int[14:5] == data_addrb_reg[14:5]) begin + if ((ena_int == 1) && (enb_reg == 1)) begin + case ({wr_mode_a, wr_mode_b, wea_int, web_reg}) +// 6'b000011 : begin data_collision_b_a <= 2'b00; display_wa_wb; end + 6'b000111 : begin data_collision_b_a <= 2'b11; display_wa_wb; end +// 6'b001011 : begin data_collision_b_a <= 2'b00; display_wa_wb; end +// 6'b010011 : begin data_collision_b_a <= 2'b00; display_wa_wb; end + 6'b010111 : begin data_collision_b_a <= 2'b11; display_wa_wb; end +// 6'b011011 : begin data_collision_b_a <= 2'b00; display_wa_wb; end +// 6'b100011 : begin data_collision_b_a <= 2'b00; display_wa_wb; end + 6'b100111 : begin data_collision_b_a <= 2'b01; display_wa_wb; end +// 6'b101011 : begin data_collision_b_a <= 2'b00; display_wa_wb; end +// 6'b000001 : begin data_collision_b_a <= 2'b00; display_ra_wb; end + 6'b000101 : begin data_collision_b_a <= 2'b10; display_ra_wb; end +// 6'b001001 : begin data_collision_b_a <= 2'b00; display_ra_wb; end +// 6'b010001 : begin data_collision_b_a <= 2'b00; display_ra_wb; end + 6'b010101 : begin data_collision_b_a <= 2'b10; display_ra_wb; end +// 6'b011001 : begin data_collision_b_a <= 2'b00; display_ra_wb; end +// 6'b100001 : begin data_collision_b_a <= 2'b00; display_ra_wb; end + 6'b100101 : begin data_collision_b_a <= 2'b10; display_ra_wb; end +// 6'b101001 : begin data_collision_b_a <= 2'b00; display_ra_wb; end +// 6'b000010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end +// 6'b000110 : begin data_collision_b_a <= 2'b00; display_wa_rb; end +// 6'b001010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end +// 6'b010010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end +// 6'b010110 : begin data_collision_b_a <= 2'b00; display_wa_rb; end +// 6'b011010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end +// 6'b100010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end +// 6'b100110 : begin data_collision_b_a <= 2'b00; display_wa_rb; end +// 6'b101010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end + endcase + end + end + setup_rf_b_a <= 0; + end + + + always @(posedge clka_int) begin + if ((output_flag || display_flag)) begin + addra_reg <= addra_int; + ena_reg <= ena_int; + ssra_reg <= ssra_int; + wea_reg <= wea_int; + end + end + + always @(posedge clkb_int) begin + if ((output_flag || display_flag)) begin + addrb_reg <= addrb_int; + enb_reg <= enb_int; + ssrb_reg <= ssrb_int; + web_reg <= web_int; + end + end + + + // Data + always @(posedge memory_collision) begin + if ((output_flag || display_flag)) begin + mem[addra_int[10:2]][addra_int[1:0] * 8 +: 8] <= 8'bx; + memory_collision <= 0; + end + + end + + always @(posedge memory_collision_a_b) begin + if ((output_flag || display_flag)) begin + mem[addra_reg[10:2]][addra_reg[1:0] * 8 +: 8] <= 8'bx; + memory_collision_a_b <= 0; + end + end + + always @(posedge memory_collision_b_a) begin + if ((output_flag || display_flag)) begin + mem[addra_int[10:2]][addra_int[1:0] * 8 +: 8] <= 8'bx; + memory_collision_b_a <= 0; + end + end + + always @(posedge data_collision[1]) begin + if (ssra_int == 0 && output_flag) begin + doa_out <= #100 8'bX; + end + data_collision[1] <= 0; + end + + always @(posedge data_collision[0]) begin + if (ssrb_int == 0 && output_flag) begin + dob_out[addra_int[1:0] * 8 +: 8] <= #100 8'bX; + end + data_collision[0] <= 0; + end + + always @(posedge data_collision_a_b[1]) begin + if (ssra_reg == 0 && output_flag) begin + doa_out <= #100 8'bX; + end + data_collision_a_b[1] <= 0; + end + + always @(posedge data_collision_a_b[0]) begin + if (ssrb_int == 0 && output_flag) begin + dob_out[addra_reg[1:0] * 8 +: 8] <= #100 8'bX; + end + data_collision_a_b[0] <= 0; + end + + always @(posedge data_collision_b_a[1]) begin + if (ssra_int == 0 && output_flag) begin + doa_out <= #100 8'bX; + end + data_collision_b_a[1] <= 0; + end + + always @(posedge data_collision_b_a[0]) begin + if (ssrb_reg == 0 && output_flag) begin + dob_out[addra_int[1:0] * 8 +: 8] <= #100 8'bX; + end + data_collision_b_a[0] <= 0; + end + +// x parity start + always @(posedge memory_collision) begin + if ((output_flag || display_flag)) + memp[addra_int[10:2]][addra_int[1:0] * 1 +: 1] <= 1'bx; + end + + always @(posedge memory_collision_a_b) begin + if ((output_flag || display_flag)) + memp[addra_reg[10:2]][addra_reg[1:0] * 1 +: 1] <= 1'bx; + end + + always @(posedge memory_collision_b_a) begin + if ((output_flag || display_flag)) + memp[addra_int[10:2]][addra_int[1:0] * 1 +: 1] <= 1'bx; + end + + always @(posedge data_collision[1]) begin + if (ssra_int == 0 && output_flag) begin + dopa_out <= #100 1'bX; + end + end + + always @(posedge data_collision_a_b[1]) begin + if (ssra_reg == 0 && output_flag) begin + dopa_out <= #100 1'bX; + end + end + + + always @(posedge data_collision_b_a[1]) begin + if (ssra_int == 0 && output_flag) begin + dopa_out <= #100 1'bX; + end + end + + always @(posedge data_collision[0]) begin + if (ssrb_int == 0 && output_flag) begin + dopb_out[addra_int[1:0] +: 1] <= #100 1'bx; + end + end + + always @(posedge data_collision_a_b[0]) begin + if (ssrb_int == 0 && output_flag) begin + dopb_out[addra_reg[1:0] +: 1] <= #100 1'bx; + end + end + + always @(posedge data_collision_b_a[0]) begin + if (ssrb_reg == 0 && output_flag) begin + dopb_out[addra_int[1:0] +: 1] <= #100 1'bx; + end + end +// x parity end + + initial begin + case (WRITE_MODE_A) + "WRITE_FIRST" : wr_mode_a <= 2'b00; + "READ_FIRST" : wr_mode_a <= 2'b01; + "NO_CHANGE" : wr_mode_a <= 2'b10; + default : begin + $display("Attribute Syntax Error : The Attribute WRITE_MODE_A on RAMB16_S9_S36 instance %m is set to %s. Legal values for this attribute are WRITE_FIRST, READ_FIRST or NO_CHANGE.", WRITE_MODE_A); + $finish; + end + endcase + end + + initial begin + case (WRITE_MODE_B) + "WRITE_FIRST" : wr_mode_b <= 2'b00; + "READ_FIRST" : wr_mode_b <= 2'b01; + "NO_CHANGE" : wr_mode_b <= 2'b10; + default : begin + $display("Attribute Syntax Error : The Attribute WRITE_MODE_B on RAMB16_S9_S36 instance %m is set to %s. Legal values for this attribute are WRITE_FIRST, READ_FIRST or NO_CHANGE.", WRITE_MODE_B); + $finish; + end + endcase + end + + + // Port A + always @(posedge clka_int) begin + + if (ena_int == 1'b1) begin + + if (ssra_int == 1'b1) begin + {dopa_out, doa_out} <= #100 SRVAL_A; + end + else begin + if (wea_int == 1'b1) begin + if (wr_mode_a == 2'b00) begin + doa_out <= #100 dia_int; + dopa_out <= #100 dipa_int; + end + else if (wr_mode_a == 2'b01) begin + + doa_out <= #100 mem[addra_int[10:2]][addra_int[1:0] * 8 +: 8]; + dopa_out <= #100 memp[addra_int[10:2]][addra_int[1:0] * 1 +: 1]; + + end + end + else begin + + doa_out <= #100 mem[addra_int[10:2]][addra_int[1:0] * 8 +: 8]; + dopa_out <= #100 memp[addra_int[10:2]][addra_int[1:0] * 1 +: 1]; + + end + end + + // memory + if (wea_int == 1'b1) begin + mem[addra_int[10:2]][addra_int[1:0] * 8 +: 8] <= dia_int; + memp[addra_int[10:2]][addra_int[1:0] * 1 +: 1] <= dipa_int; + end + + end + end + + + // Port B + always @(posedge clkb_int) begin + + if (enb_int == 1'b1) begin + + if (ssrb_int == 1'b1) begin + {dopb_out, dob_out} <= #100 SRVAL_B; + end + else begin + if (web_int == 1'b1) begin + if (wr_mode_b == 2'b00) begin + dob_out <= #100 dib_int; + dopb_out <= #100 dipb_int; + end + else if (wr_mode_b == 2'b01) begin + dob_out <= #100 mem[addrb_int]; + dopb_out <= #100 memp[addrb_int]; + end + end + else begin + dob_out <= #100 mem[addrb_int]; + dopb_out <= #100 memp[addrb_int]; + end + end + + // memory + if (web_int == 1'b1) begin + mem[addrb_int] <= dib_int; + memp[addrb_int] <= dipb_int; + end + + end + end + + +endmodule + +`endif diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/RAMB16_S9_S9.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/RAMB16_S9_S9.v new file mode 100644 index 0000000..30bf3ad --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/RAMB16_S9_S9.v @@ -0,0 +1,1819 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/RAMB16_S9_S9.v,v 1.10 2007/02/22 01:58:06 wloo Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2005 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / 16K-Bit Data and 2K-Bit Parity Dual Port Block RAM +// /___/ /\ Filename : RAMB16_S9_S9.v +// \ \ / \ Timestamp : Thu Mar 10 16:43:37 PST 2005 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// End Revision + +`ifdef legacy_model + +`timescale 1 ps / 1 ps + +module RAMB16_S9_S9 (DOA, DOB, DOPA, DOPB, ADDRA, ADDRB, CLKA, CLKB, DIA, DIB, DIPA, DIPB, ENA, ENB, SSRA, SSRB, WEA, WEB); + + parameter INIT_A = 9'h0; + parameter INIT_B = 9'h0; + parameter SRVAL_A = 9'h0; + parameter SRVAL_B = 9'h0; + parameter WRITE_MODE_A = "WRITE_FIRST"; + parameter WRITE_MODE_B = "WRITE_FIRST"; + parameter SIM_COLLISION_CHECK = "ALL"; + localparam SETUP_ALL = 1000; + localparam SETUP_READ_FIRST = 3000; + + parameter INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + + output [7:0] DOA; + output [0:0] DOPA; + reg [7:0] doa_out; + reg [0:0] dopa_out; + wire doa_out0, doa_out1, doa_out2, doa_out3, doa_out4, doa_out5, doa_out6, doa_out7; + wire dopa0_out; + + input [10:0] ADDRA; + input [7:0] DIA; + input [0:0] DIPA; + input ENA, CLKA, WEA, SSRA; + + output [7:0] DOB; + output [0:0] DOPB; + reg [7:0] dob_out; + reg [0:0] dopb_out; + wire dob_out0, dob_out1, dob_out2, dob_out3, dob_out4, dob_out5, dob_out6, dob_out7; + wire dopb0_out; + + input [10:0] ADDRB; + input [7:0] DIB; + input [0:0] DIPB; + input ENB, CLKB, WEB, SSRB; + + reg [18431:0] mem; + reg [8:0] count; + reg [1:0] wr_mode_a, wr_mode_b; + + reg [5:0] dmi, dbi; + reg [5:0] pmi, pbi; + + wire [10:0] addra_int; + reg [10:0] addra_reg; + wire [7:0] dia_int; + wire [0:0] dipa_int; + wire ena_int, clka_int, wea_int, ssra_int; + reg ena_reg, wea_reg, ssra_reg; + wire [10:0] addrb_int; + reg [10:0] addrb_reg; + wire [7:0] dib_int; + wire [0:0] dipb_int; + wire enb_int, clkb_int, web_int, ssrb_int; + reg display_flag; + reg enb_reg, web_reg, ssrb_reg; + + time time_clka, time_clkb; + time time_clka_clkb; + time time_clkb_clka; + + reg setup_all_a_b; + reg setup_all_b_a; + reg setup_zero; + reg setup_rf_a_b; + reg setup_rf_b_a; + reg [1:0] data_collision, data_collision_a_b, data_collision_b_a; + reg memory_collision, memory_collision_a_b, memory_collision_b_a; + reg address_collision, address_collision_a_b, address_collision_b_a; + reg change_clka; + reg change_clkb; + + wire [14:0] data_addra_int; + wire [14:0] data_addra_reg; + wire [14:0] data_addrb_int; + wire [14:0] data_addrb_reg; + wire [15:0] parity_addra_int; + wire [15:0] parity_addra_reg; + wire [15:0] parity_addrb_int; + wire [15:0] parity_addrb_reg; + + tri0 GSR = glbl.GSR; + + always @(GSR) + if (GSR) begin + assign doa_out = INIT_A[7:0]; + assign dopa_out = INIT_A[8:8]; + assign dob_out = INIT_B[7:0]; + assign dopb_out = INIT_B[8:8]; + end + else begin + deassign doa_out; + deassign dopa_out; + deassign dob_out; + deassign dopb_out; + end + + buf b_doa_out0 (doa_out0, doa_out[0]); + buf b_doa_out1 (doa_out1, doa_out[1]); + buf b_doa_out2 (doa_out2, doa_out[2]); + buf b_doa_out3 (doa_out3, doa_out[3]); + buf b_doa_out4 (doa_out4, doa_out[4]); + buf b_doa_out5 (doa_out5, doa_out[5]); + buf b_doa_out6 (doa_out6, doa_out[6]); + buf b_doa_out7 (doa_out7, doa_out[7]); + buf b_dopa_out0 (dopa_out0, dopa_out[0]); + buf b_dob_out0 (dob_out0, dob_out[0]); + buf b_dob_out1 (dob_out1, dob_out[1]); + buf b_dob_out2 (dob_out2, dob_out[2]); + buf b_dob_out3 (dob_out3, dob_out[3]); + buf b_dob_out4 (dob_out4, dob_out[4]); + buf b_dob_out5 (dob_out5, dob_out[5]); + buf b_dob_out6 (dob_out6, dob_out[6]); + buf b_dob_out7 (dob_out7, dob_out[7]); + buf b_dopb_out0 (dopb_out0, dopb_out[0]); + + buf b_doa0 (DOA[0], doa_out0); + buf b_doa1 (DOA[1], doa_out1); + buf b_doa2 (DOA[2], doa_out2); + buf b_doa3 (DOA[3], doa_out3); + buf b_doa4 (DOA[4], doa_out4); + buf b_doa5 (DOA[5], doa_out5); + buf b_doa6 (DOA[6], doa_out6); + buf b_doa7 (DOA[7], doa_out7); + buf b_dopa0 (DOPA[0], dopa_out0); + buf b_dob0 (DOB[0], dob_out0); + buf b_dob1 (DOB[1], dob_out1); + buf b_dob2 (DOB[2], dob_out2); + buf b_dob3 (DOB[3], dob_out3); + buf b_dob4 (DOB[4], dob_out4); + buf b_dob5 (DOB[5], dob_out5); + buf b_dob6 (DOB[6], dob_out6); + buf b_dob7 (DOB[7], dob_out7); + buf b_dopb0 (DOPB[0], dopb_out0); + + buf b_addra_0 (addra_int[0], ADDRA[0]); + buf b_addra_1 (addra_int[1], ADDRA[1]); + buf b_addra_2 (addra_int[2], ADDRA[2]); + buf b_addra_3 (addra_int[3], ADDRA[3]); + buf b_addra_4 (addra_int[4], ADDRA[4]); + buf b_addra_5 (addra_int[5], ADDRA[5]); + buf b_addra_6 (addra_int[6], ADDRA[6]); + buf b_addra_7 (addra_int[7], ADDRA[7]); + buf b_addra_8 (addra_int[8], ADDRA[8]); + buf b_addra_9 (addra_int[9], ADDRA[9]); + buf b_addra_10 (addra_int[10], ADDRA[10]); + buf b_dia_0 (dia_int[0], DIA[0]); + buf b_dia_1 (dia_int[1], DIA[1]); + buf b_dia_2 (dia_int[2], DIA[2]); + buf b_dia_3 (dia_int[3], DIA[3]); + buf b_dia_4 (dia_int[4], DIA[4]); + buf b_dia_5 (dia_int[5], DIA[5]); + buf b_dia_6 (dia_int[6], DIA[6]); + buf b_dia_7 (dia_int[7], DIA[7]); + buf b_dipa_0 (dipa_int[0], DIPA[0]); + buf b_ena (ena_int, ENA); + buf b_clka (clka_int, CLKA); + buf b_ssra (ssra_int, SSRA); + buf b_wea (wea_int, WEA); + buf b_addrb_0 (addrb_int[0], ADDRB[0]); + buf b_addrb_1 (addrb_int[1], ADDRB[1]); + buf b_addrb_2 (addrb_int[2], ADDRB[2]); + buf b_addrb_3 (addrb_int[3], ADDRB[3]); + buf b_addrb_4 (addrb_int[4], ADDRB[4]); + buf b_addrb_5 (addrb_int[5], ADDRB[5]); + buf b_addrb_6 (addrb_int[6], ADDRB[6]); + buf b_addrb_7 (addrb_int[7], ADDRB[7]); + buf b_addrb_8 (addrb_int[8], ADDRB[8]); + buf b_addrb_9 (addrb_int[9], ADDRB[9]); + buf b_addrb_10 (addrb_int[10], ADDRB[10]); + buf b_dib_0 (dib_int[0], DIB[0]); + buf b_dib_1 (dib_int[1], DIB[1]); + buf b_dib_2 (dib_int[2], DIB[2]); + buf b_dib_3 (dib_int[3], DIB[3]); + buf b_dib_4 (dib_int[4], DIB[4]); + buf b_dib_5 (dib_int[5], DIB[5]); + buf b_dib_6 (dib_int[6], DIB[6]); + buf b_dib_7 (dib_int[7], DIB[7]); + buf b_dipb_0 (dipb_int[0], DIPB[0]); + buf b_enb (enb_int, ENB); + buf b_clkb (clkb_int, CLKB); + buf b_ssrb (ssrb_int, SSRB); + buf b_web (web_int, WEB); + + initial begin + for (count = 0; count < 256; count = count + 1) begin + mem[count] <= INIT_00[count]; + mem[256 * 1 + count] <= INIT_01[count]; + mem[256 * 2 + count] <= INIT_02[count]; + mem[256 * 3 + count] <= INIT_03[count]; + mem[256 * 4 + count] <= INIT_04[count]; + mem[256 * 5 + count] <= INIT_05[count]; + mem[256 * 6 + count] <= INIT_06[count]; + mem[256 * 7 + count] <= INIT_07[count]; + mem[256 * 8 + count] <= INIT_08[count]; + mem[256 * 9 + count] <= INIT_09[count]; + mem[256 * 10 + count] <= INIT_0A[count]; + mem[256 * 11 + count] <= INIT_0B[count]; + mem[256 * 12 + count] <= INIT_0C[count]; + mem[256 * 13 + count] <= INIT_0D[count]; + mem[256 * 14 + count] <= INIT_0E[count]; + mem[256 * 15 + count] <= INIT_0F[count]; + mem[256 * 16 + count] <= INIT_10[count]; + mem[256 * 17 + count] <= INIT_11[count]; + mem[256 * 18 + count] <= INIT_12[count]; + mem[256 * 19 + count] <= INIT_13[count]; + mem[256 * 20 + count] <= INIT_14[count]; + mem[256 * 21 + count] <= INIT_15[count]; + mem[256 * 22 + count] <= INIT_16[count]; + mem[256 * 23 + count] <= INIT_17[count]; + mem[256 * 24 + count] <= INIT_18[count]; + mem[256 * 25 + count] <= INIT_19[count]; + mem[256 * 26 + count] <= INIT_1A[count]; + mem[256 * 27 + count] <= INIT_1B[count]; + mem[256 * 28 + count] <= INIT_1C[count]; + mem[256 * 29 + count] <= INIT_1D[count]; + mem[256 * 30 + count] <= INIT_1E[count]; + mem[256 * 31 + count] <= INIT_1F[count]; + mem[256 * 32 + count] <= INIT_20[count]; + mem[256 * 33 + count] <= INIT_21[count]; + mem[256 * 34 + count] <= INIT_22[count]; + mem[256 * 35 + count] <= INIT_23[count]; + mem[256 * 36 + count] <= INIT_24[count]; + mem[256 * 37 + count] <= INIT_25[count]; + mem[256 * 38 + count] <= INIT_26[count]; + mem[256 * 39 + count] <= INIT_27[count]; + mem[256 * 40 + count] <= INIT_28[count]; + mem[256 * 41 + count] <= INIT_29[count]; + mem[256 * 42 + count] <= INIT_2A[count]; + mem[256 * 43 + count] <= INIT_2B[count]; + mem[256 * 44 + count] <= INIT_2C[count]; + mem[256 * 45 + count] <= INIT_2D[count]; + mem[256 * 46 + count] <= INIT_2E[count]; + mem[256 * 47 + count] <= INIT_2F[count]; + mem[256 * 48 + count] <= INIT_30[count]; + mem[256 * 49 + count] <= INIT_31[count]; + mem[256 * 50 + count] <= INIT_32[count]; + mem[256 * 51 + count] <= INIT_33[count]; + mem[256 * 52 + count] <= INIT_34[count]; + mem[256 * 53 + count] <= INIT_35[count]; + mem[256 * 54 + count] <= INIT_36[count]; + mem[256 * 55 + count] <= INIT_37[count]; + mem[256 * 56 + count] <= INIT_38[count]; + mem[256 * 57 + count] <= INIT_39[count]; + mem[256 * 58 + count] <= INIT_3A[count]; + mem[256 * 59 + count] <= INIT_3B[count]; + mem[256 * 60 + count] <= INIT_3C[count]; + mem[256 * 61 + count] <= INIT_3D[count]; + mem[256 * 62 + count] <= INIT_3E[count]; + mem[256 * 63 + count] <= INIT_3F[count]; + mem[256 * 64 + count] <= INITP_00[count]; + mem[256 * 65 + count] <= INITP_01[count]; + mem[256 * 66 + count] <= INITP_02[count]; + mem[256 * 67 + count] <= INITP_03[count]; + mem[256 * 68 + count] <= INITP_04[count]; + mem[256 * 69 + count] <= INITP_05[count]; + mem[256 * 70 + count] <= INITP_06[count]; + mem[256 * 71 + count] <= INITP_07[count]; + end + address_collision <= 0; + address_collision_a_b <= 0; + address_collision_b_a <= 0; + change_clka <= 0; + change_clkb <= 0; + data_collision <= 0; + data_collision_a_b <= 0; + data_collision_b_a <= 0; + memory_collision <= 0; + memory_collision_a_b <= 0; + memory_collision_b_a <= 0; + setup_all_a_b <= 0; + setup_all_b_a <= 0; + setup_zero <= 0; + setup_rf_a_b <= 0; + setup_rf_b_a <= 0; + end + + assign data_addra_int = addra_int * 8; + assign data_addra_reg = addra_reg * 8; + assign data_addrb_int = addrb_int * 8; + assign data_addrb_reg = addrb_reg * 8; + assign parity_addra_int = 16384 + addra_int * 1; + assign parity_addra_reg = 16384 + addra_reg * 1; + assign parity_addrb_int = 16384 + addrb_int * 1; + assign parity_addrb_reg = 16384 + addrb_reg * 1; + + + initial begin + + display_flag = 1; + + case (SIM_COLLISION_CHECK) + + "NONE" : begin + assign setup_all_a_b = 1'b0; + assign setup_all_b_a = 1'b0; + assign setup_zero = 1'b0; + assign setup_rf_a_b = 1'b0; + assign setup_rf_b_a = 1'b0; + assign display_flag = 0; + end + "WARNING_ONLY" : begin + assign data_collision = 2'b00; + assign data_collision_a_b = 2'b00; + assign data_collision_b_a = 2'b00; + assign memory_collision = 1'b0; + assign memory_collision_a_b = 1'b0; + assign memory_collision_b_a = 1'b0; + end + "GENERATE_X_ONLY" : begin + assign display_flag = 0; + end + "ALL" : ; + default : begin + $display("Attribute Syntax Error : The Attribute SIM_COLLISION_CHECK on RAMB16_S9_S9 instance %m is set to %s. Legal values for this attribute are ALL, NONE, WARNING_ONLY or GENERATE_X_ONLY.", SIM_COLLISION_CHECK); + $finish; + end + + endcase // case(SIM_COLLISION_CHECK) + + end // initial begin + + + always @(posedge clka_int) begin + time_clka = $time; + #0 time_clkb_clka = time_clka - time_clkb; + change_clka = ~change_clka; + end + + always @(posedge clkb_int) begin + time_clkb = $time; + #0 time_clka_clkb = time_clkb - time_clka; + change_clkb = ~change_clkb; + end + + always @(change_clkb) begin + if ((0 < time_clka_clkb) && (time_clka_clkb < SETUP_ALL)) + setup_all_a_b = 1; + if ((0 < time_clka_clkb) && (time_clka_clkb < SETUP_READ_FIRST)) + setup_rf_a_b = 1; + end + + always @(change_clka) begin + if ((0 < time_clkb_clka) && (time_clkb_clka < SETUP_ALL)) + setup_all_b_a = 1; + if ((0 < time_clkb_clka) && (time_clkb_clka < SETUP_READ_FIRST)) + setup_rf_b_a = 1; + end + + always @(change_clkb or change_clka) begin + if ((time_clkb_clka == 0) && (time_clka_clkb == 0)) + setup_zero = 1; + end + + always @(posedge setup_zero) begin + if ((ena_int == 1) && (wea_int == 1) && + (enb_int == 1) && (web_int == 1) && + (data_addra_int[14:3] == data_addrb_int[14:3])) + memory_collision <= 1; + end + + always @(posedge setup_all_a_b or posedge setup_rf_a_b) begin + if ((ena_reg == 1) && (wea_reg == 1) && + (enb_int == 1) && (web_int == 1) && + (data_addra_reg[14:3] == data_addrb_int[14:3])) + memory_collision_a_b <= 1; + end + + always @(posedge setup_all_b_a or posedge setup_rf_b_a) begin + if ((ena_int == 1) && (wea_int == 1) && + (enb_reg == 1) && (web_reg == 1) && + (data_addra_int[14:3] == data_addrb_reg[14:3])) + memory_collision_b_a <= 1; + end + + always @(posedge setup_all_a_b) begin + if (data_addra_reg[14:3] == data_addrb_int[14:3]) begin + if ((ena_reg == 1) && (enb_int == 1)) begin + case ({wr_mode_a, wr_mode_b, wea_reg, web_int}) + 6'b000011 : begin data_collision_a_b <= 2'b11; display_wa_wb; end + 6'b000111 : begin data_collision_a_b <= 2'b11; display_wa_wb; end + 6'b001011 : begin data_collision_a_b <= 2'b10; display_wa_wb; end +// 6'b010011 : begin data_collision_a_b <= 2'b00; display_wa_wb; end +// 6'b010111 : begin data_collision_a_b <= 2'b00; display_wa_wb; end +// 6'b011011 : begin data_collision_a_b <= 2'b00; display_wa_wb; end + 6'b100011 : begin data_collision_a_b <= 2'b01; display_wa_wb; end + 6'b100111 : begin data_collision_a_b <= 2'b01; display_wa_wb; end + 6'b101011 : begin display_wa_wb; end + 6'b000001 : begin data_collision_a_b <= 2'b10; display_ra_wb; end +// 6'b000101 : begin data_collision_a_b <= 2'b00; display_ra_wb; end + 6'b001001 : begin data_collision_a_b <= 2'b10; display_ra_wb; end + 6'b010001 : begin data_collision_a_b <= 2'b10; display_ra_wb; end +// 6'b010101 : begin data_collision_a_b <= 2'b00; display_ra_wb; end + 6'b011001 : begin data_collision_a_b <= 2'b10; display_ra_wb; end + 6'b100001 : begin data_collision_a_b <= 2'b10; display_ra_wb; end +// 6'b100101 : begin data_collision_a_b <= 2'b00; display_ra_wb; end + 6'b101001 : begin data_collision_a_b <= 2'b10; display_ra_wb; end + 6'b000010 : begin data_collision_a_b <= 2'b01; display_wa_rb; end + 6'b000110 : begin data_collision_a_b <= 2'b01; display_wa_rb; end + 6'b001010 : begin data_collision_a_b <= 2'b01; display_wa_rb; end +// 6'b010010 : begin data_collision_a_b <= 2'b00; display_wa_rb; end +// 6'b010110 : begin data_collision_a_b <= 2'b00; display_wa_rb; end +// 6'b011010 : begin data_collision_a_b <= 2'b00; display_wa_rb; end + 6'b100010 : begin data_collision_a_b <= 2'b01; display_wa_rb; end + 6'b100110 : begin data_collision_a_b <= 2'b01; display_wa_rb; end + 6'b101010 : begin data_collision_a_b <= 2'b01; display_wa_rb; end + endcase + end + end + setup_all_a_b <= 0; + end + + + always @(posedge setup_all_b_a) begin + if (data_addra_int[14:3] == data_addrb_reg[14:3]) begin + if ((ena_int == 1) && (enb_reg == 1)) begin + case ({wr_mode_a, wr_mode_b, wea_int, web_reg}) + 6'b000011 : begin data_collision_b_a <= 2'b11; display_wa_wb; end +// 6'b000111 : begin data_collision_b_a <= 2'b00; display_wa_wb; end + 6'b001011 : begin data_collision_b_a <= 2'b10; display_wa_wb; end + 6'b010011 : begin data_collision_b_a <= 2'b11; display_wa_wb; end +// 6'b010111 : begin data_collision_b_a <= 2'b00; display_wa_wb; end + 6'b011011 : begin data_collision_b_a <= 2'b10; display_wa_wb; end + 6'b100011 : begin data_collision_b_a <= 2'b01; display_wa_wb; end + 6'b100111 : begin data_collision_b_a <= 2'b01; display_wa_wb; end + 6'b101011 : begin display_wa_wb; end + 6'b000001 : begin data_collision_b_a <= 2'b10; display_ra_wb; end + 6'b000101 : begin data_collision_b_a <= 2'b10; display_ra_wb; end + 6'b001001 : begin data_collision_b_a <= 2'b10; display_ra_wb; end + 6'b010001 : begin data_collision_b_a <= 2'b10; display_ra_wb; end + 6'b010101 : begin data_collision_b_a <= 2'b10; display_ra_wb; end + 6'b011001 : begin data_collision_b_a <= 2'b10; display_ra_wb; end + 6'b100001 : begin data_collision_b_a <= 2'b10; display_ra_wb; end + 6'b100101 : begin data_collision_b_a <= 2'b10; display_ra_wb; end + 6'b101001 : begin data_collision_b_a <= 2'b10; display_ra_wb; end + 6'b000010 : begin data_collision_b_a <= 2'b01; display_wa_rb; end + 6'b000110 : begin data_collision_b_a <= 2'b01; display_wa_rb; end + 6'b001010 : begin data_collision_b_a <= 2'b01; display_wa_rb; end +// 6'b010010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end +// 6'b010110 : begin data_collision_b_a <= 2'b00; display_wa_rb; end +// 6'b011010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end + 6'b100010 : begin data_collision_b_a <= 2'b01; display_wa_rb; end + 6'b100110 : begin data_collision_b_a <= 2'b01; display_wa_rb; end + 6'b101010 : begin data_collision_b_a <= 2'b01; display_wa_rb; end + endcase + end + end + setup_all_b_a <= 0; + end + + + always @(posedge setup_zero) begin + if (data_addra_int[14:3] == data_addrb_int[14:3]) begin + if ((ena_int == 1) && (enb_int == 1)) begin + case ({wr_mode_a, wr_mode_b, wea_int, web_int}) + 6'b000011 : begin data_collision <= 2'b11; display_wa_wb; end + 6'b000111 : begin data_collision <= 2'b11; display_wa_wb; end + 6'b001011 : begin data_collision <= 2'b10; display_wa_wb; end + 6'b010011 : begin data_collision <= 2'b11; display_wa_wb; end + 6'b010111 : begin data_collision <= 2'b11; display_wa_wb; end + 6'b011011 : begin data_collision <= 2'b10; display_wa_wb; end + 6'b100011 : begin data_collision <= 2'b01; display_wa_wb; end + 6'b100111 : begin data_collision <= 2'b01; display_wa_wb; end + 6'b101011 : begin display_wa_wb; end + 6'b000001 : begin data_collision <= 2'b10; display_ra_wb; end +// 6'b000101 : begin data_collision <= 2'b00; display_ra_wb; end + 6'b001001 : begin data_collision <= 2'b10; display_ra_wb; end + 6'b010001 : begin data_collision <= 2'b10; display_ra_wb; end +// 6'b010101 : begin data_collision <= 2'b00; display_ra_wb; end + 6'b011001 : begin data_collision <= 2'b10; display_ra_wb; end + 6'b100001 : begin data_collision <= 2'b10; display_ra_wb; end +// 6'b100101 : begin data_collision <= 2'b00; display_ra_wb; end + 6'b101001 : begin data_collision <= 2'b10; display_ra_wb; end + 6'b000010 : begin data_collision <= 2'b01; display_wa_rb; end + 6'b000110 : begin data_collision <= 2'b01; display_wa_rb; end + 6'b001010 : begin data_collision <= 2'b01; display_wa_rb; end +// 6'b010010 : begin data_collision <= 2'b00; display_wa_rb; end +// 6'b010110 : begin data_collision <= 2'b00; display_wa_rb; end +// 6'b011010 : begin data_collision <= 2'b00; display_wa_rb; end + 6'b100010 : begin data_collision <= 2'b01; display_wa_rb; end + 6'b100110 : begin data_collision <= 2'b01; display_wa_rb; end + 6'b101010 : begin data_collision <= 2'b01; display_wa_rb; end + endcase + end + end + setup_zero <= 0; + end + + task display_ra_wb; + begin + if (display_flag) + $display("Memory Collision Error on RAMB16_S9_S9:%m at simulation time %.3f ns\nA read was performed on address %h (hex) of Port A while a write was requested to the same address on Port B. The write will be successful however the read value on Port A is unknown until the next CLKA cycle.", $time/1000.0, addra_int); + end + endtask + + task display_wa_rb; + begin + if (display_flag) + $display("Memory Collision Error on RAMB16_S9_S9:%m at simulation time %.3f ns\nA read was performed on address %h (hex) of Port B while a write was requested to the same address on Port A. The write will be successful however the read value on Port B is unknown until the next CLKB cycle.", $time/1000.0, addrb_int); + end + endtask + + task display_wa_wb; + begin + if (display_flag) + $display("Memory Collision Error on RAMB16_S9_S9:%m at simulation time %.3f ns\nA write was requested to the same address simultaneously at both Port A and Port B of the RAM. The contents written to the RAM at address location %h (hex) of Port A and address location %h (hex) of Port B are unknown.", $time/1000.0, addra_int, addrb_int); + end + endtask + + + always @(posedge setup_rf_a_b) begin + if (data_addra_reg[14:3] == data_addrb_int[14:3]) begin + if ((ena_reg == 1) && (enb_int == 1)) begin + case ({wr_mode_a, wr_mode_b, wea_reg, web_int}) +// 6'b000011 : begin data_collision_a_b <= 2'b00; display_wa_wb; end +// 6'b000111 : begin data_collision_a_b <= 2'b00; display_wa_wb; end +// 6'b001011 : begin data_collision_a_b <= 2'b00; display_wa_wb; end + 6'b010011 : begin data_collision_a_b <= 2'b11; display_wa_wb; end + 6'b010111 : begin data_collision_a_b <= 2'b11; display_wa_wb; end + 6'b011011 : begin data_collision_a_b <= 2'b10; display_wa_wb; end +// 6'b100011 : begin data_collision_a_b <= 2'b00; display_wa_wb; end +// 6'b100111 : begin data_collision_a_b <= 2'b00; display_wa_wb; end +// 6'b101011 : begin data_collision_a_b <= 2'b00; display_wa_wb; end +// 6'b000001 : begin data_collision_a_b <= 2'b00; display_ra_wb; end +// 6'b000101 : begin data_collision_a_b <= 2'b00; display_ra_wb; end +// 6'b001001 : begin data_collision_a_b <= 2'b00; display_ra_wb; end +// 6'b010001 : begin data_collision_a_b <= 2'b00; display_ra_wb; end +// 6'b010101 : begin data_collision_a_b <= 2'b00; display_ra_wb; end +// 6'b011001 : begin data_collision_a_b <= 2'b00; display_ra_wb; end +// 6'b100001 : begin data_collision_a_b <= 2'b00; display_ra_wb; end +// 6'b100101 : begin data_collision_a_b <= 2'b00; display_ra_wb; end +// 6'b101001 : begin data_collision_a_b <= 2'b00; display_ra_wb; end +// 6'b000010 : begin data_collision_a_b <= 2'b00; display_wa_rb; end +// 6'b000110 : begin data_collision_a_b <= 2'b00; display_wa_rb; end +// 6'b001010 : begin data_collision_a_b <= 2'b00; display_wa_rb; end + 6'b010010 : begin data_collision_a_b <= 2'b01; display_wa_rb; end + 6'b010110 : begin data_collision_a_b <= 2'b01; display_wa_rb; end + 6'b011010 : begin data_collision_a_b <= 2'b01; display_wa_rb; end +// 6'b100010 : begin data_collision_a_b <= 2'b00; display_wa_rb; end +// 6'b100110 : begin data_collision_a_b <= 2'b00; display_wa_rb; end +// 6'b101010 : begin data_collision_a_b <= 2'b00; display_wa_rb; end + endcase + end + end + setup_rf_a_b <= 0; + end + + + always @(posedge setup_rf_b_a) begin + if (data_addra_int[14:3] == data_addrb_reg[14:3]) begin + if ((ena_int == 1) && (enb_reg == 1)) begin + case ({wr_mode_a, wr_mode_b, wea_int, web_reg}) +// 6'b000011 : begin data_collision_b_a <= 2'b00; display_wa_wb; end + 6'b000111 : begin data_collision_b_a <= 2'b11; display_wa_wb; end +// 6'b001011 : begin data_collision_b_a <= 2'b00; display_wa_wb; end +// 6'b010011 : begin data_collision_b_a <= 2'b00; display_wa_wb; end + 6'b010111 : begin data_collision_b_a <= 2'b11; display_wa_wb; end +// 6'b011011 : begin data_collision_b_a <= 2'b00; display_wa_wb; end +// 6'b100011 : begin data_collision_b_a <= 2'b00; display_wa_wb; end + 6'b100111 : begin data_collision_b_a <= 2'b01; display_wa_wb; end +// 6'b101011 : begin data_collision_b_a <= 2'b00; display_wa_wb; end +// 6'b000001 : begin data_collision_b_a <= 2'b00; display_ra_wb; end + 6'b000101 : begin data_collision_b_a <= 2'b10; display_ra_wb; end +// 6'b001001 : begin data_collision_b_a <= 2'b00; display_ra_wb; end +// 6'b010001 : begin data_collision_b_a <= 2'b00; display_ra_wb; end + 6'b010101 : begin data_collision_b_a <= 2'b10; display_ra_wb; end +// 6'b011001 : begin data_collision_b_a <= 2'b00; display_ra_wb; end +// 6'b100001 : begin data_collision_b_a <= 2'b00; display_ra_wb; end + 6'b100101 : begin data_collision_b_a <= 2'b10; display_ra_wb; end +// 6'b101001 : begin data_collision_b_a <= 2'b00; display_ra_wb; end +// 6'b000010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end +// 6'b000110 : begin data_collision_b_a <= 2'b00; display_wa_rb; end +// 6'b001010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end +// 6'b010010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end +// 6'b010110 : begin data_collision_b_a <= 2'b00; display_wa_rb; end +// 6'b011010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end +// 6'b100010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end +// 6'b100110 : begin data_collision_b_a <= 2'b00; display_wa_rb; end +// 6'b101010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end + endcase + end + end + setup_rf_b_a <= 0; + end + + + always @(posedge clka_int) begin + addra_reg <= addra_int; + ena_reg <= ena_int; + ssra_reg <= ssra_int; + wea_reg <= wea_int; + end + + always @(posedge clkb_int) begin + addrb_reg <= addrb_int; + enb_reg <= enb_int; + ssrb_reg <= ssrb_int; + web_reg <= web_int; + end + + // Data + always @(posedge memory_collision) begin + for (dmi = 0; dmi < 8; dmi = dmi + 1) begin + mem[data_addra_int + dmi] <= 1'bX; + end + memory_collision <= 0; + end + + always @(posedge memory_collision_a_b) begin + for (dmi = 0; dmi < 8; dmi = dmi + 1) begin + mem[data_addra_reg + dmi] <= 1'bX; + end + memory_collision_a_b <= 0; + end + + always @(posedge memory_collision_b_a) begin + for (dmi = 0; dmi < 8; dmi = dmi + 1) begin + mem[data_addra_int + dmi] <= 1'bX; + end + memory_collision_b_a <= 0; + end + + always @(posedge data_collision[1]) begin + if (ssra_int == 0) begin + doa_out <= 8'bX; + end + data_collision[1] <= 0; + end + + always @(posedge data_collision[0]) begin + if (ssrb_int == 0) begin + dob_out <= 8'bX; + end + data_collision[0] <= 0; + end + + always @(posedge data_collision_a_b[1]) begin + if (ssra_reg == 0) begin + doa_out <= 8'bX; + end + data_collision_a_b[1] <= 0; + end + + always @(posedge data_collision_a_b[0]) begin + if (ssrb_int == 0) begin + dob_out <= 8'bX; + end + data_collision_a_b[0] <= 0; + end + + always @(posedge data_collision_b_a[1]) begin + if (ssra_int == 0) begin + doa_out <= 8'bX; + end + data_collision_b_a[1] <= 0; + end + + always @(posedge data_collision_b_a[0]) begin + if (ssrb_reg == 0) begin + dob_out <= 8'bX; + end + data_collision_b_a[0] <= 0; + end + + // Parity + always @(posedge memory_collision) begin + for (pmi = 0; pmi < 1; pmi = pmi + 1) begin + mem[parity_addra_int + pmi] <= 1'bX; + end + end + + always @(posedge memory_collision_a_b) begin + for (pmi = 0; pmi < 1; pmi = pmi + 1) begin + mem[parity_addra_reg + pmi] <= 1'bX; + end + end + + always @(posedge memory_collision_b_a) begin + for (pmi = 0; pmi < 1; pmi = pmi + 1) begin + mem[parity_addra_int + pmi] <= 1'bX; + end + end + + always @(posedge data_collision[1]) begin + if (ssra_int == 0) begin + dopa_out <= 1'bX; + end + end + + always @(posedge data_collision[0]) begin + if (ssrb_int == 0) begin + dopb_out <= 1'bX; + end + end + + always @(posedge data_collision_a_b[1]) begin + if (ssra_reg == 0) begin + dopa_out <= 1'bX; + end + end + + always @(posedge data_collision_a_b[0]) begin + if (ssrb_int == 0) begin + dopb_out <= 1'bX; + end + end + + always @(posedge data_collision_b_a[1]) begin + if (ssra_int == 0) begin + dopa_out <= 1'bX; + end + end + + always @(posedge data_collision_b_a[0]) begin + if (ssrb_reg == 0) begin + dopb_out <= 1'bX; + end + end + + + initial begin + case (WRITE_MODE_A) + "WRITE_FIRST" : wr_mode_a <= 2'b00; + "READ_FIRST" : wr_mode_a <= 2'b01; + "NO_CHANGE" : wr_mode_a <= 2'b10; + default : begin + $display("Attribute Syntax Error : The Attribute WRITE_MODE_A on RAMB16_S9_S9 instance %m is set to %s. Legal values for this attribute are WRITE_FIRST, READ_FIRST or NO_CHANGE.", WRITE_MODE_A); + $finish; + end + endcase + end + + initial begin + case (WRITE_MODE_B) + "WRITE_FIRST" : wr_mode_b <= 2'b00; + "READ_FIRST" : wr_mode_b <= 2'b01; + "NO_CHANGE" : wr_mode_b <= 2'b10; + default : begin + $display("Attribute Syntax Error : The Attribute WRITE_MODE_B on RAMB16_S9_S9 instance %m is set to %s. Legal values for this attribute are WRITE_FIRST, READ_FIRST or NO_CHANGE.", WRITE_MODE_B); + $finish; + end + endcase + end + + // Port A + always @(posedge clka_int) begin + if (ena_int == 1'b1) begin + if (ssra_int == 1'b1) begin + doa_out[0] <= SRVAL_A[0]; + doa_out[1] <= SRVAL_A[1]; + doa_out[2] <= SRVAL_A[2]; + doa_out[3] <= SRVAL_A[3]; + doa_out[4] <= SRVAL_A[4]; + doa_out[5] <= SRVAL_A[5]; + doa_out[6] <= SRVAL_A[6]; + doa_out[7] <= SRVAL_A[7]; + dopa_out[0] <= SRVAL_A[8]; + end + else begin + if (wea_int == 1'b1) begin + if (wr_mode_a == 2'b00) begin + doa_out <= dia_int; + dopa_out <= dipa_int; + end + else if (wr_mode_a == 2'b01) begin + doa_out[0] <= mem[data_addra_int + 0]; + doa_out[1] <= mem[data_addra_int + 1]; + doa_out[2] <= mem[data_addra_int + 2]; + doa_out[3] <= mem[data_addra_int + 3]; + doa_out[4] <= mem[data_addra_int + 4]; + doa_out[5] <= mem[data_addra_int + 5]; + doa_out[6] <= mem[data_addra_int + 6]; + doa_out[7] <= mem[data_addra_int + 7]; + dopa_out[0] <= mem[parity_addra_int + 0]; + end + end + else begin + doa_out[0] <= mem[data_addra_int + 0]; + doa_out[1] <= mem[data_addra_int + 1]; + doa_out[2] <= mem[data_addra_int + 2]; + doa_out[3] <= mem[data_addra_int + 3]; + doa_out[4] <= mem[data_addra_int + 4]; + doa_out[5] <= mem[data_addra_int + 5]; + doa_out[6] <= mem[data_addra_int + 6]; + doa_out[7] <= mem[data_addra_int + 7]; + dopa_out[0] <= mem[parity_addra_int + 0]; + end + end + end + end + + always @(posedge clka_int) begin + if (ena_int == 1'b1 && wea_int == 1'b1) begin + mem[data_addra_int + 0] <= dia_int[0]; + mem[data_addra_int + 1] <= dia_int[1]; + mem[data_addra_int + 2] <= dia_int[2]; + mem[data_addra_int + 3] <= dia_int[3]; + mem[data_addra_int + 4] <= dia_int[4]; + mem[data_addra_int + 5] <= dia_int[5]; + mem[data_addra_int + 6] <= dia_int[6]; + mem[data_addra_int + 7] <= dia_int[7]; + mem[parity_addra_int + 0] <= dipa_int[0]; + end + end + + // Port B + always @(posedge clkb_int) begin + if (enb_int == 1'b1) begin + if (ssrb_int == 1'b1) begin + dob_out[0] <= SRVAL_B[0]; + dob_out[1] <= SRVAL_B[1]; + dob_out[2] <= SRVAL_B[2]; + dob_out[3] <= SRVAL_B[3]; + dob_out[4] <= SRVAL_B[4]; + dob_out[5] <= SRVAL_B[5]; + dob_out[6] <= SRVAL_B[6]; + dob_out[7] <= SRVAL_B[7]; + dopb_out[0] <= SRVAL_B[8]; + end + else begin + if (web_int == 1'b1) begin + if (wr_mode_b == 2'b00) begin + dob_out <= dib_int; + dopb_out <= dipb_int; + end + else if (wr_mode_b == 2'b01) begin + dob_out[0] <= mem[data_addrb_int + 0]; + dob_out[1] <= mem[data_addrb_int + 1]; + dob_out[2] <= mem[data_addrb_int + 2]; + dob_out[3] <= mem[data_addrb_int + 3]; + dob_out[4] <= mem[data_addrb_int + 4]; + dob_out[5] <= mem[data_addrb_int + 5]; + dob_out[6] <= mem[data_addrb_int + 6]; + dob_out[7] <= mem[data_addrb_int + 7]; + dopb_out[0] <= mem[parity_addrb_int + 0]; + end + end + else begin + dob_out[0] <= mem[data_addrb_int + 0]; + dob_out[1] <= mem[data_addrb_int + 1]; + dob_out[2] <= mem[data_addrb_int + 2]; + dob_out[3] <= mem[data_addrb_int + 3]; + dob_out[4] <= mem[data_addrb_int + 4]; + dob_out[5] <= mem[data_addrb_int + 5]; + dob_out[6] <= mem[data_addrb_int + 6]; + dob_out[7] <= mem[data_addrb_int + 7]; + dopb_out[0] <= mem[parity_addrb_int + 0]; + end + end + end + end + + always @(posedge clkb_int) begin + if (enb_int == 1'b1 && web_int == 1'b1) begin + mem[data_addrb_int + 0] <= dib_int[0]; + mem[data_addrb_int + 1] <= dib_int[1]; + mem[data_addrb_int + 2] <= dib_int[2]; + mem[data_addrb_int + 3] <= dib_int[3]; + mem[data_addrb_int + 4] <= dib_int[4]; + mem[data_addrb_int + 5] <= dib_int[5]; + mem[data_addrb_int + 6] <= dib_int[6]; + mem[data_addrb_int + 7] <= dib_int[7]; + mem[parity_addrb_int + 0] <= dipb_int[0]; + end + end + + specify + (CLKA *> DOA) = (100, 100); + (CLKA *> DOPA) = (100, 100); + (CLKB *> DOB) = (100, 100); + (CLKB *> DOPB) = (100, 100); + endspecify + +endmodule + +`else + +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/RAMB16_S9_S9.v,v 1.10 2007/02/22 01:58:06 wloo Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2005 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Timing Simulation Library Component +// / / 16K-Bit Data and 2K-Bit Parity Dual Port Block RAM +// /___/ /\ Filename : RAMB16_S9_S9.v +// \ \ / \ Timestamp : Thu Mar 10 16:44:01 PST 2005 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 03/10/05 - Initialized outputs. +// 02/21/07 - Fixed parameter SIM_COLLISION_CHECK (CR 433281). +// End Revision + +`timescale 1 ps/1 ps + +module RAMB16_S9_S9 (DOA, DOB, DOPA, DOPB, ADDRA, ADDRB, CLKA, CLKB, DIA, DIB, DIPA, DIPB, ENA, ENB, SSRA, SSRB, WEA, WEB); + + parameter INIT_A = 9'h0; + parameter INIT_B = 9'h0; + parameter SRVAL_A = 9'h0; + parameter SRVAL_B = 9'h0; + parameter WRITE_MODE_A = "WRITE_FIRST"; + parameter WRITE_MODE_B = "WRITE_FIRST"; + parameter SIM_COLLISION_CHECK = "ALL"; + localparam SETUP_ALL = 1000; + localparam SETUP_READ_FIRST = 3000; + + parameter INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + + output [7:0] DOA; + output [0:0] DOPA; + output [7:0] DOB; + output [0:0] DOPB; + + input [10:0] ADDRA; + input [7:0] DIA; + input [0:0] DIPA; + input ENA, CLKA, WEA, SSRA; + input [10:0] ADDRB; + input [7:0] DIB; + input [0:0] DIPB; + input ENB, CLKB, WEB, SSRB; + + reg [7:0] doa_out = INIT_A[7:0]; + reg [0:0] dopa_out = INIT_A[8:8]; + reg [7:0] dob_out = INIT_B[7:0]; + reg [0:0] dopb_out = INIT_B[8:8]; + + reg [7:0] mem [2047:0]; + reg [0:0] memp [2047:0]; + + reg [8:0] count, countp; + reg [1:0] wr_mode_a, wr_mode_b; + + reg [5:0] dmi, dbi; + reg [5:0] pmi, pbi; + + wire [10:0] addra_int; + reg [10:0] addra_reg; + wire [7:0] dia_int; + wire [0:0] dipa_int; + wire ena_int, clka_int, wea_int, ssra_int; + reg ena_reg, wea_reg, ssra_reg; + wire [10:0] addrb_int; + reg [10:0] addrb_reg; + wire [7:0] dib_int; + wire [0:0] dipb_int; + wire enb_int, clkb_int, web_int, ssrb_int; + reg display_flag, output_flag; + reg enb_reg, web_reg, ssrb_reg; + + time time_clka, time_clkb; + time time_clka_clkb; + time time_clkb_clka; + + reg setup_all_a_b; + reg setup_all_b_a; + reg setup_zero; + reg setup_rf_a_b; + reg setup_rf_b_a; + reg [1:0] data_collision, data_collision_a_b, data_collision_b_a; + reg memory_collision, memory_collision_a_b, memory_collision_b_a; + reg change_clka; + reg change_clkb; + + wire [14:0] data_addra_int; + wire [14:0] data_addra_reg; + wire [14:0] data_addrb_int; + wire [14:0] data_addrb_reg; + + wire dia_enable = ena_int && wea_int; + wire dib_enable = enb_int && web_int; + + tri0 GSR = glbl.GSR; + wire gsr_int; + + buf b_gsr (gsr_int, GSR); + + buf b_doa [7:0] (DOA, doa_out); + buf b_dopa [0:0] (DOPA, dopa_out); + buf b_addra [10:0] (addra_int, ADDRA); + buf b_dia [7:0] (dia_int, DIA); + buf b_dipa [0:0] (dipa_int, DIPA); + buf b_ena (ena_int, ENA); + buf b_clka (clka_int, CLKA); + buf b_ssra (ssra_int, SSRA); + buf b_wea (wea_int, WEA); + + buf b_dob [7:0] (DOB, dob_out); + buf b_dopb [0:0] (DOPB, dopb_out); + buf b_addrb [10:0] (addrb_int, ADDRB); + buf b_dib [7:0] (dib_int, DIB); + buf b_dipb [0:0] (dipb_int, DIPB); + buf b_enb (enb_int, ENB); + buf b_clkb (clkb_int, CLKB); + buf b_ssrb (ssrb_int, SSRB); + buf b_web (web_int, WEB); + + + always @(gsr_int) + if (gsr_int) begin + assign {dopa_out, doa_out} = INIT_A; + assign {dopb_out, dob_out} = INIT_B; + end + else begin + deassign doa_out; + deassign dopa_out; + deassign dob_out; + deassign dopb_out; + end + + + initial begin + + for (count = 0; count < 32; count = count + 1) begin + mem[count] = INIT_00[(count * 8) +: 8]; + mem[32 * 1 + count] = INIT_01[(count * 8) +: 8]; + mem[32 * 2 + count] = INIT_02[(count * 8) +: 8]; + mem[32 * 3 + count] = INIT_03[(count * 8) +: 8]; + mem[32 * 4 + count] = INIT_04[(count * 8) +: 8]; + mem[32 * 5 + count] = INIT_05[(count * 8) +: 8]; + mem[32 * 6 + count] = INIT_06[(count * 8) +: 8]; + mem[32 * 7 + count] = INIT_07[(count * 8) +: 8]; + mem[32 * 8 + count] = INIT_08[(count * 8) +: 8]; + mem[32 * 9 + count] = INIT_09[(count * 8) +: 8]; + mem[32 * 10 + count] = INIT_0A[(count * 8) +: 8]; + mem[32 * 11 + count] = INIT_0B[(count * 8) +: 8]; + mem[32 * 12 + count] = INIT_0C[(count * 8) +: 8]; + mem[32 * 13 + count] = INIT_0D[(count * 8) +: 8]; + mem[32 * 14 + count] = INIT_0E[(count * 8) +: 8]; + mem[32 * 15 + count] = INIT_0F[(count * 8) +: 8]; + mem[32 * 16 + count] = INIT_10[(count * 8) +: 8]; + mem[32 * 17 + count] = INIT_11[(count * 8) +: 8]; + mem[32 * 18 + count] = INIT_12[(count * 8) +: 8]; + mem[32 * 19 + count] = INIT_13[(count * 8) +: 8]; + mem[32 * 20 + count] = INIT_14[(count * 8) +: 8]; + mem[32 * 21 + count] = INIT_15[(count * 8) +: 8]; + mem[32 * 22 + count] = INIT_16[(count * 8) +: 8]; + mem[32 * 23 + count] = INIT_17[(count * 8) +: 8]; + mem[32 * 24 + count] = INIT_18[(count * 8) +: 8]; + mem[32 * 25 + count] = INIT_19[(count * 8) +: 8]; + mem[32 * 26 + count] = INIT_1A[(count * 8) +: 8]; + mem[32 * 27 + count] = INIT_1B[(count * 8) +: 8]; + mem[32 * 28 + count] = INIT_1C[(count * 8) +: 8]; + mem[32 * 29 + count] = INIT_1D[(count * 8) +: 8]; + mem[32 * 30 + count] = INIT_1E[(count * 8) +: 8]; + mem[32 * 31 + count] = INIT_1F[(count * 8) +: 8]; + mem[32 * 32 + count] = INIT_20[(count * 8) +: 8]; + mem[32 * 33 + count] = INIT_21[(count * 8) +: 8]; + mem[32 * 34 + count] = INIT_22[(count * 8) +: 8]; + mem[32 * 35 + count] = INIT_23[(count * 8) +: 8]; + mem[32 * 36 + count] = INIT_24[(count * 8) +: 8]; + mem[32 * 37 + count] = INIT_25[(count * 8) +: 8]; + mem[32 * 38 + count] = INIT_26[(count * 8) +: 8]; + mem[32 * 39 + count] = INIT_27[(count * 8) +: 8]; + mem[32 * 40 + count] = INIT_28[(count * 8) +: 8]; + mem[32 * 41 + count] = INIT_29[(count * 8) +: 8]; + mem[32 * 42 + count] = INIT_2A[(count * 8) +: 8]; + mem[32 * 43 + count] = INIT_2B[(count * 8) +: 8]; + mem[32 * 44 + count] = INIT_2C[(count * 8) +: 8]; + mem[32 * 45 + count] = INIT_2D[(count * 8) +: 8]; + mem[32 * 46 + count] = INIT_2E[(count * 8) +: 8]; + mem[32 * 47 + count] = INIT_2F[(count * 8) +: 8]; + mem[32 * 48 + count] = INIT_30[(count * 8) +: 8]; + mem[32 * 49 + count] = INIT_31[(count * 8) +: 8]; + mem[32 * 50 + count] = INIT_32[(count * 8) +: 8]; + mem[32 * 51 + count] = INIT_33[(count * 8) +: 8]; + mem[32 * 52 + count] = INIT_34[(count * 8) +: 8]; + mem[32 * 53 + count] = INIT_35[(count * 8) +: 8]; + mem[32 * 54 + count] = INIT_36[(count * 8) +: 8]; + mem[32 * 55 + count] = INIT_37[(count * 8) +: 8]; + mem[32 * 56 + count] = INIT_38[(count * 8) +: 8]; + mem[32 * 57 + count] = INIT_39[(count * 8) +: 8]; + mem[32 * 58 + count] = INIT_3A[(count * 8) +: 8]; + mem[32 * 59 + count] = INIT_3B[(count * 8) +: 8]; + mem[32 * 60 + count] = INIT_3C[(count * 8) +: 8]; + mem[32 * 61 + count] = INIT_3D[(count * 8) +: 8]; + mem[32 * 62 + count] = INIT_3E[(count * 8) +: 8]; + mem[32 * 63 + count] = INIT_3F[(count * 8) +: 8]; + end + +// initiate parity start + for (countp = 0; countp < 256; countp = countp + 1) begin + memp[countp] = INITP_00[(countp * 1) +: 1]; + memp[256 * 1 + countp] = INITP_01[(countp * 1) +: 1]; + memp[256 * 2 + countp] = INITP_02[(countp * 1) +: 1]; + memp[256 * 3 + countp] = INITP_03[(countp * 1) +: 1]; + memp[256 * 4 + countp] = INITP_04[(countp * 1) +: 1]; + memp[256 * 5 + countp] = INITP_05[(countp * 1) +: 1]; + memp[256 * 6 + countp] = INITP_06[(countp * 1) +: 1]; + memp[256 * 7 + countp] = INITP_07[(countp * 1) +: 1]; + end +// initiate parity end + + change_clka <= 0; + change_clkb <= 0; + data_collision <= 0; + data_collision_a_b <= 0; + data_collision_b_a <= 0; + memory_collision <= 0; + memory_collision_a_b <= 0; + memory_collision_b_a <= 0; + setup_all_a_b <= 0; + setup_all_b_a <= 0; + setup_zero <= 0; + setup_rf_a_b <= 0; + setup_rf_b_a <= 0; + end + + assign data_addra_int = addra_int * 8; + assign data_addra_reg = addra_reg * 8; + assign data_addrb_int = addrb_int * 8; + assign data_addrb_reg = addrb_reg * 8; + + + initial begin + + display_flag = 1; + output_flag = 1; + + case (SIM_COLLISION_CHECK) + + "NONE" : begin + output_flag = 0; + display_flag = 0; + end + "WARNING_ONLY" : output_flag = 0; + "GENERATE_X_ONLY" : display_flag = 0; + "ALL" : ; + + default : begin + $display("Attribute Syntax Error : The Attribute SIM_COLLISION_CHECK on RAMB16_S9_S9 instance %m is set to %s. Legal values for this attribute are ALL, NONE, WARNING_ONLY or GENERATE_X_ONLY.", SIM_COLLISION_CHECK); + $finish; + end + + endcase // case(SIM_COLLISION_CHECK) + + end // initial begin + + + always @(posedge clka_int) begin + if ((output_flag || display_flag)) begin + time_clka = $time; + #0 time_clkb_clka = time_clka - time_clkb; + change_clka = ~change_clka; + end + end + + always @(posedge clkb_int) begin + if ((output_flag || display_flag)) begin + time_clkb = $time; + #0 time_clka_clkb = time_clkb - time_clka; + change_clkb = ~change_clkb; + end + end + + always @(change_clkb) begin + if ((0 < time_clka_clkb) && (time_clka_clkb < SETUP_ALL)) + setup_all_a_b = 1; + if ((0 < time_clka_clkb) && (time_clka_clkb < SETUP_READ_FIRST)) + setup_rf_a_b = 1; + end + + always @(change_clka) begin + if ((0 < time_clkb_clka) && (time_clkb_clka < SETUP_ALL)) + setup_all_b_a = 1; + if ((0 < time_clkb_clka) && (time_clkb_clka < SETUP_READ_FIRST)) + setup_rf_b_a = 1; + end + + always @(change_clkb or change_clka) begin + if ((time_clkb_clka == 0) && (time_clka_clkb == 0)) + setup_zero = 1; + end + + always @(posedge setup_zero) begin + if ((ena_int == 1) && (wea_int == 1) && + (enb_int == 1) && (web_int == 1) && + (data_addra_int[14:3] == data_addrb_int[14:3])) + memory_collision <= 1; + end + + always @(posedge setup_all_a_b or posedge setup_rf_a_b) begin + if ((ena_reg == 1) && (wea_reg == 1) && + (enb_int == 1) && (web_int == 1) && + (data_addra_reg[14:3] == data_addrb_int[14:3])) + memory_collision_a_b <= 1; + end + + always @(posedge setup_all_b_a or posedge setup_rf_b_a) begin + if ((ena_int == 1) && (wea_int == 1) && + (enb_reg == 1) && (web_reg == 1) && + (data_addra_int[14:3] == data_addrb_reg[14:3])) + memory_collision_b_a <= 1; + end + + always @(posedge setup_all_a_b) begin + if (data_addra_reg[14:3] == data_addrb_int[14:3]) begin + if ((ena_reg == 1) && (enb_int == 1)) begin + case ({wr_mode_a, wr_mode_b, wea_reg, web_int}) + 6'b000011 : begin data_collision_a_b <= 2'b11; display_wa_wb; end + 6'b000111 : begin data_collision_a_b <= 2'b11; display_wa_wb; end + 6'b001011 : begin data_collision_a_b <= 2'b10; display_wa_wb; end +// 6'b010011 : begin data_collision_a_b <= 2'b00; display_wa_wb; end +// 6'b010111 : begin data_collision_a_b <= 2'b00; display_wa_wb; end +// 6'b011011 : begin data_collision_a_b <= 2'b00; display_wa_wb; end + 6'b100011 : begin data_collision_a_b <= 2'b01; display_wa_wb; end + 6'b100111 : begin data_collision_a_b <= 2'b01; display_wa_wb; end + 6'b101011 : begin display_wa_wb; end + 6'b000001 : begin data_collision_a_b <= 2'b10; display_ra_wb; end +// 6'b000101 : begin data_collision_a_b <= 2'b00; display_ra_wb; end + 6'b001001 : begin data_collision_a_b <= 2'b10; display_ra_wb; end + 6'b010001 : begin data_collision_a_b <= 2'b10; display_ra_wb; end +// 6'b010101 : begin data_collision_a_b <= 2'b00; display_ra_wb; end + 6'b011001 : begin data_collision_a_b <= 2'b10; display_ra_wb; end + 6'b100001 : begin data_collision_a_b <= 2'b10; display_ra_wb; end +// 6'b100101 : begin data_collision_a_b <= 2'b00; display_ra_wb; end + 6'b101001 : begin data_collision_a_b <= 2'b10; display_ra_wb; end + 6'b000010 : begin data_collision_a_b <= 2'b01; display_wa_rb; end + 6'b000110 : begin data_collision_a_b <= 2'b01; display_wa_rb; end + 6'b001010 : begin data_collision_a_b <= 2'b01; display_wa_rb; end +// 6'b010010 : begin data_collision_a_b <= 2'b00; display_wa_rb; end +// 6'b010110 : begin data_collision_a_b <= 2'b00; display_wa_rb; end +// 6'b011010 : begin data_collision_a_b <= 2'b00; display_wa_rb; end + 6'b100010 : begin data_collision_a_b <= 2'b01; display_wa_rb; end + 6'b100110 : begin data_collision_a_b <= 2'b01; display_wa_rb; end + 6'b101010 : begin data_collision_a_b <= 2'b01; display_wa_rb; end + endcase + end + end + setup_all_a_b <= 0; + end + + + always @(posedge setup_all_b_a) begin + if (data_addra_int[14:3] == data_addrb_reg[14:3]) begin + if ((ena_int == 1) && (enb_reg == 1)) begin + case ({wr_mode_a, wr_mode_b, wea_int, web_reg}) + 6'b000011 : begin data_collision_b_a <= 2'b11; display_wa_wb; end +// 6'b000111 : begin data_collision_b_a <= 2'b00; display_wa_wb; end + 6'b001011 : begin data_collision_b_a <= 2'b10; display_wa_wb; end + 6'b010011 : begin data_collision_b_a <= 2'b11; display_wa_wb; end +// 6'b010111 : begin data_collision_b_a <= 2'b00; display_wa_wb; end + 6'b011011 : begin data_collision_b_a <= 2'b10; display_wa_wb; end + 6'b100011 : begin data_collision_b_a <= 2'b01; display_wa_wb; end + 6'b100111 : begin data_collision_b_a <= 2'b01; display_wa_wb; end + 6'b101011 : begin display_wa_wb; end + 6'b000001 : begin data_collision_b_a <= 2'b10; display_ra_wb; end + 6'b000101 : begin data_collision_b_a <= 2'b10; display_ra_wb; end + 6'b001001 : begin data_collision_b_a <= 2'b10; display_ra_wb; end + 6'b010001 : begin data_collision_b_a <= 2'b10; display_ra_wb; end + 6'b010101 : begin data_collision_b_a <= 2'b10; display_ra_wb; end + 6'b011001 : begin data_collision_b_a <= 2'b10; display_ra_wb; end + 6'b100001 : begin data_collision_b_a <= 2'b10; display_ra_wb; end + 6'b100101 : begin data_collision_b_a <= 2'b10; display_ra_wb; end + 6'b101001 : begin data_collision_b_a <= 2'b10; display_ra_wb; end + 6'b000010 : begin data_collision_b_a <= 2'b01; display_wa_rb; end + 6'b000110 : begin data_collision_b_a <= 2'b01; display_wa_rb; end + 6'b001010 : begin data_collision_b_a <= 2'b01; display_wa_rb; end +// 6'b010010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end +// 6'b010110 : begin data_collision_b_a <= 2'b00; display_wa_rb; end +// 6'b011010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end + 6'b100010 : begin data_collision_b_a <= 2'b01; display_wa_rb; end + 6'b100110 : begin data_collision_b_a <= 2'b01; display_wa_rb; end + 6'b101010 : begin data_collision_b_a <= 2'b01; display_wa_rb; end + endcase + end + end + setup_all_b_a <= 0; + end + + + always @(posedge setup_zero) begin + if (data_addra_int[14:3] == data_addrb_int[14:3]) begin + if ((ena_int == 1) && (enb_int == 1)) begin + case ({wr_mode_a, wr_mode_b, wea_int, web_int}) + 6'b000011 : begin data_collision <= 2'b11; display_wa_wb; end + 6'b000111 : begin data_collision <= 2'b11; display_wa_wb; end + 6'b001011 : begin data_collision <= 2'b10; display_wa_wb; end + 6'b010011 : begin data_collision <= 2'b11; display_wa_wb; end + 6'b010111 : begin data_collision <= 2'b11; display_wa_wb; end + 6'b011011 : begin data_collision <= 2'b10; display_wa_wb; end + 6'b100011 : begin data_collision <= 2'b01; display_wa_wb; end + 6'b100111 : begin data_collision <= 2'b01; display_wa_wb; end + 6'b101011 : begin display_wa_wb; end + 6'b000001 : begin data_collision <= 2'b10; display_ra_wb; end +// 6'b000101 : begin data_collision <= 2'b00; display_ra_wb; end + 6'b001001 : begin data_collision <= 2'b10; display_ra_wb; end + 6'b010001 : begin data_collision <= 2'b10; display_ra_wb; end +// 6'b010101 : begin data_collision <= 2'b00; display_ra_wb; end + 6'b011001 : begin data_collision <= 2'b10; display_ra_wb; end + 6'b100001 : begin data_collision <= 2'b10; display_ra_wb; end +// 6'b100101 : begin data_collision <= 2'b00; display_ra_wb; end + 6'b101001 : begin data_collision <= 2'b10; display_ra_wb; end + 6'b000010 : begin data_collision <= 2'b01; display_wa_rb; end + 6'b000110 : begin data_collision <= 2'b01; display_wa_rb; end + 6'b001010 : begin data_collision <= 2'b01; display_wa_rb; end +// 6'b010010 : begin data_collision <= 2'b00; display_wa_rb; end +// 6'b010110 : begin data_collision <= 2'b00; display_wa_rb; end +// 6'b011010 : begin data_collision <= 2'b00; display_wa_rb; end + 6'b100010 : begin data_collision <= 2'b01; display_wa_rb; end + 6'b100110 : begin data_collision <= 2'b01; display_wa_rb; end + 6'b101010 : begin data_collision <= 2'b01; display_wa_rb; end + endcase + end + end + setup_zero <= 0; + end + + task display_ra_wb; + begin + if (display_flag) + $display("Memory Collision Error on RAMB16_S9_S9:%m at simulation time %.3f ns\nA read was performed on address %h (hex) of Port A while a write was requested to the same address on Port B. The write will be successful however the read value on Port A is unknown until the next CLKA cycle.", $time/1000.0, addra_int); + end + endtask + + task display_wa_rb; + begin + if (display_flag) + $display("Memory Collision Error on RAMB16_S9_S9:%m at simulation time %.3f ns\nA read was performed on address %h (hex) of Port B while a write was requested to the same address on Port A. The write will be successful however the read value on Port B is unknown until the next CLKB cycle.", $time/1000.0, addrb_int); + end + endtask + + task display_wa_wb; + begin + if (display_flag) + $display("Memory Collision Error on RAMB16_S9_S9:%m at simulation time %.3f ns\nA write was requested to the same address simultaneously at both Port A and Port B of the RAM. The contents written to the RAM at address location %h (hex) of Port A and address location %h (hex) of Port B are unknown.", $time/1000.0, addra_int, addrb_int); + end + endtask + + + always @(posedge setup_rf_a_b) begin + if (data_addra_reg[14:3] == data_addrb_int[14:3]) begin + if ((ena_reg == 1) && (enb_int == 1)) begin + case ({wr_mode_a, wr_mode_b, wea_reg, web_int}) +// 6'b000011 : begin data_collision_a_b <= 2'b00; display_wa_wb; end +// 6'b000111 : begin data_collision_a_b <= 2'b00; display_wa_wb; end +// 6'b001011 : begin data_collision_a_b <= 2'b00; display_wa_wb; end + 6'b010011 : begin data_collision_a_b <= 2'b11; display_wa_wb; end + 6'b010111 : begin data_collision_a_b <= 2'b11; display_wa_wb; end + 6'b011011 : begin data_collision_a_b <= 2'b10; display_wa_wb; end +// 6'b100011 : begin data_collision_a_b <= 2'b00; display_wa_wb; end +// 6'b100111 : begin data_collision_a_b <= 2'b00; display_wa_wb; end +// 6'b101011 : begin data_collision_a_b <= 2'b00; display_wa_wb; end +// 6'b000001 : begin data_collision_a_b <= 2'b00; display_ra_wb; end +// 6'b000101 : begin data_collision_a_b <= 2'b00; display_ra_wb; end +// 6'b001001 : begin data_collision_a_b <= 2'b00; display_ra_wb; end +// 6'b010001 : begin data_collision_a_b <= 2'b00; display_ra_wb; end +// 6'b010101 : begin data_collision_a_b <= 2'b00; display_ra_wb; end +// 6'b011001 : begin data_collision_a_b <= 2'b00; display_ra_wb; end +// 6'b100001 : begin data_collision_a_b <= 2'b00; display_ra_wb; end +// 6'b100101 : begin data_collision_a_b <= 2'b00; display_ra_wb; end +// 6'b101001 : begin data_collision_a_b <= 2'b00; display_ra_wb; end +// 6'b000010 : begin data_collision_a_b <= 2'b00; display_wa_rb; end +// 6'b000110 : begin data_collision_a_b <= 2'b00; display_wa_rb; end +// 6'b001010 : begin data_collision_a_b <= 2'b00; display_wa_rb; end + 6'b010010 : begin data_collision_a_b <= 2'b01; display_wa_rb; end + 6'b010110 : begin data_collision_a_b <= 2'b01; display_wa_rb; end + 6'b011010 : begin data_collision_a_b <= 2'b01; display_wa_rb; end +// 6'b100010 : begin data_collision_a_b <= 2'b00; display_wa_rb; end +// 6'b100110 : begin data_collision_a_b <= 2'b00; display_wa_rb; end +// 6'b101010 : begin data_collision_a_b <= 2'b00; display_wa_rb; end + endcase + end + end + setup_rf_a_b <= 0; + end + + + always @(posedge setup_rf_b_a) begin + if (data_addra_int[14:3] == data_addrb_reg[14:3]) begin + if ((ena_int == 1) && (enb_reg == 1)) begin + case ({wr_mode_a, wr_mode_b, wea_int, web_reg}) +// 6'b000011 : begin data_collision_b_a <= 2'b00; display_wa_wb; end + 6'b000111 : begin data_collision_b_a <= 2'b11; display_wa_wb; end +// 6'b001011 : begin data_collision_b_a <= 2'b00; display_wa_wb; end +// 6'b010011 : begin data_collision_b_a <= 2'b00; display_wa_wb; end + 6'b010111 : begin data_collision_b_a <= 2'b11; display_wa_wb; end +// 6'b011011 : begin data_collision_b_a <= 2'b00; display_wa_wb; end +// 6'b100011 : begin data_collision_b_a <= 2'b00; display_wa_wb; end + 6'b100111 : begin data_collision_b_a <= 2'b01; display_wa_wb; end +// 6'b101011 : begin data_collision_b_a <= 2'b00; display_wa_wb; end +// 6'b000001 : begin data_collision_b_a <= 2'b00; display_ra_wb; end + 6'b000101 : begin data_collision_b_a <= 2'b10; display_ra_wb; end +// 6'b001001 : begin data_collision_b_a <= 2'b00; display_ra_wb; end +// 6'b010001 : begin data_collision_b_a <= 2'b00; display_ra_wb; end + 6'b010101 : begin data_collision_b_a <= 2'b10; display_ra_wb; end +// 6'b011001 : begin data_collision_b_a <= 2'b00; display_ra_wb; end +// 6'b100001 : begin data_collision_b_a <= 2'b00; display_ra_wb; end + 6'b100101 : begin data_collision_b_a <= 2'b10; display_ra_wb; end +// 6'b101001 : begin data_collision_b_a <= 2'b00; display_ra_wb; end +// 6'b000010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end +// 6'b000110 : begin data_collision_b_a <= 2'b00; display_wa_rb; end +// 6'b001010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end +// 6'b010010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end +// 6'b010110 : begin data_collision_b_a <= 2'b00; display_wa_rb; end +// 6'b011010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end +// 6'b100010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end +// 6'b100110 : begin data_collision_b_a <= 2'b00; display_wa_rb; end +// 6'b101010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end + endcase + end + end + setup_rf_b_a <= 0; + end + + + always @(posedge clka_int) begin + if ((output_flag || display_flag)) begin + addra_reg <= addra_int; + ena_reg <= ena_int; + ssra_reg <= ssra_int; + wea_reg <= wea_int; + end + end + + always @(posedge clkb_int) begin + if ((output_flag || display_flag)) begin + addrb_reg <= addrb_int; + enb_reg <= enb_int; + ssrb_reg <= ssrb_int; + web_reg <= web_int; + end + end + + + // Data + always @(posedge memory_collision) begin + if ((output_flag || display_flag)) begin + mem[addra_int] <= 8'bx; + memory_collision <= 0; + end + + end + + always @(posedge memory_collision_a_b) begin + if ((output_flag || display_flag)) begin + mem[addra_reg] <= 8'bx; + memory_collision_a_b <= 0; + end + end + + always @(posedge memory_collision_b_a) begin + if ((output_flag || display_flag)) begin + mem[addra_int] <= 8'bx; + memory_collision_b_a <= 0; + end + end + + always @(posedge data_collision[1]) begin + if (ssra_int == 0 && output_flag) begin + doa_out <= #100 8'bX; + end + data_collision[1] <= 0; + end + + always @(posedge data_collision[0]) begin + if (ssrb_int == 0 && output_flag) begin + dob_out <= #100 8'bX; + end + data_collision[0] <= 0; + end + + always @(posedge data_collision_a_b[1]) begin + if (ssra_reg == 0 && output_flag) begin + doa_out <= #100 8'bX; + end + data_collision_a_b[1] <= 0; + end + + always @(posedge data_collision_a_b[0]) begin + if (ssrb_int == 0 && output_flag) begin + dob_out <= #100 8'bX; + end + data_collision_a_b[0] <= 0; + end + + always @(posedge data_collision_b_a[1]) begin + if (ssra_int == 0 && output_flag) begin + doa_out <= #100 8'bX; + end + data_collision_b_a[1] <= 0; + end + + always @(posedge data_collision_b_a[0]) begin + if (ssrb_reg == 0 && output_flag) begin + dob_out <= #100 8'bX; + end + data_collision_b_a[0] <= 0; + end + +// x parity start + always @(posedge memory_collision) begin + if ((output_flag || display_flag)) + memp[addra_int] <= 1'bx; + end + + always @(posedge memory_collision_a_b) begin + if ((output_flag || display_flag)) + memp[addra_reg] <= 1'bx; + end + + always @(posedge memory_collision_b_a) begin + if ((output_flag || display_flag)) + memp[addra_int] <= 1'bx; + end + + always @(posedge data_collision[1]) begin + if (ssra_int == 0 && output_flag) begin + dopa_out <= #100 1'bX; + end + end + + always @(posedge data_collision_a_b[1]) begin + if (ssra_reg == 0 && output_flag) begin + dopa_out <= #100 1'bX; + end + end + + + always @(posedge data_collision_b_a[1]) begin + if (ssra_int == 0 && output_flag) begin + dopa_out <= #100 1'bX; + end + end + + always @(posedge data_collision[0]) begin + if (ssrb_int == 0 && output_flag) begin + dopb_out <= #100 1'bx; + end + end + + always @(posedge data_collision_a_b[0]) begin + if (ssrb_int == 0 && output_flag) begin + dopb_out <= #100 1'bx; + end + end + + always @(posedge data_collision_b_a[0]) begin + if (ssrb_reg == 0 && output_flag) begin + dopb_out <= #100 1'bx; + end + end +// x parity end + + initial begin + case (WRITE_MODE_A) + "WRITE_FIRST" : wr_mode_a <= 2'b00; + "READ_FIRST" : wr_mode_a <= 2'b01; + "NO_CHANGE" : wr_mode_a <= 2'b10; + default : begin + $display("Attribute Syntax Error : The Attribute WRITE_MODE_A on RAMB16_S9_S9 instance %m is set to %s. Legal values for this attribute are WRITE_FIRST, READ_FIRST or NO_CHANGE.", WRITE_MODE_A); + $finish; + end + endcase + end + + initial begin + case (WRITE_MODE_B) + "WRITE_FIRST" : wr_mode_b <= 2'b00; + "READ_FIRST" : wr_mode_b <= 2'b01; + "NO_CHANGE" : wr_mode_b <= 2'b10; + default : begin + $display("Attribute Syntax Error : The Attribute WRITE_MODE_B on RAMB16_S9_S9 instance %m is set to %s. Legal values for this attribute are WRITE_FIRST, READ_FIRST or NO_CHANGE.", WRITE_MODE_B); + $finish; + end + endcase + end + + + // Port A + always @(posedge clka_int) begin + + if (ena_int == 1'b1) begin + + if (ssra_int == 1'b1) begin + {dopa_out, doa_out} <= #100 SRVAL_A; + end + else begin + if (wea_int == 1'b1) begin + if (wr_mode_a == 2'b00) begin + doa_out <= #100 dia_int; + dopa_out <= #100 dipa_int; + end + else if (wr_mode_a == 2'b01) begin + + doa_out <= #100 mem[addra_int]; + dopa_out <= #100 memp[addra_int]; + + end + end + else begin + + doa_out <= #100 mem[addra_int]; + dopa_out <= #100 memp[addra_int]; + + end + end + + // memory + if (wea_int == 1'b1) begin + mem[addra_int] <= dia_int; + memp[addra_int] <= dipa_int; + end + + end + end + + + // Port B + always @(posedge clkb_int) begin + + if (enb_int == 1'b1) begin + + if (ssrb_int == 1'b1) begin + {dopb_out, dob_out} <= #100 SRVAL_B; + end + else begin + if (web_int == 1'b1) begin + if (wr_mode_b == 2'b00) begin + dob_out <= #100 dib_int; + dopb_out <= #100 dipb_int; + end + else if (wr_mode_b == 2'b01) begin + dob_out <= #100 mem[addrb_int]; + dopb_out <= #100 memp[addrb_int]; + end + end + else begin + dob_out <= #100 mem[addrb_int]; + dopb_out <= #100 memp[addrb_int]; + end + end + + // memory + if (web_int == 1'b1) begin + mem[addrb_int] <= dib_int; + memp[addrb_int] <= dipb_int; + end + + end + end + + +endmodule + +`endif diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/RAMB18.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/RAMB18.v new file mode 100644 index 0000000..66775d7 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/RAMB18.v @@ -0,0 +1,289 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/rainier/RAMB18.v,v 1.17 2007/06/15 20:58:40 wloo Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2005 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / 16K-Bit Data and 2K-Bit Parity Dual Port Block RAM +// /___/ /\ Filename : RAMB18.v +// \ \ / \ Timestamp : Tues July 26 16:43:59 PST 2005 +// \___\/\___\ +// +// Revision: +// 07/26/05 - Initial version. +// 01/04/07 - Added support of memory file to initialize memory and parity (CR 431584). +// 03/14/07 - Removed attribute INITP_FILE (CR 436003). +// 04/03/07 - Changed INIT_FILE = "NONE" as default (CR 436812). +// 06/13/07 - Added high performace version of the model. +// End Revision + +`timescale 1 ps/1 ps + +module RAMB18 (DOA, DOB, DOPA, DOPB, + ADDRA, ADDRB, CLKA, CLKB, DIA, DIB, DIPA, DIPB, ENA, ENB, REGCEA, REGCEB, SSRA, SSRB, WEA, WEB); + + parameter integer DOA_REG = 0; + parameter integer DOB_REG = 0; + parameter INITP_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_A = 18'h0; + parameter INIT_B = 18'h0; + parameter INIT_FILE = "NONE"; + parameter integer READ_WIDTH_A = 0; + parameter integer READ_WIDTH_B = 0; + parameter SIM_COLLISION_CHECK = "ALL"; + parameter SIM_MODE = "SAFE"; + parameter SRVAL_A = 18'h0; + parameter SRVAL_B = 18'h0; + parameter WRITE_MODE_A = "WRITE_FIRST"; + parameter WRITE_MODE_B = "WRITE_FIRST"; + parameter integer WRITE_WIDTH_A = 0; + parameter integer WRITE_WIDTH_B = 0; + + localparam SETUP_ALL = 1000; + localparam SETUP_READ_FIRST = 3000; + + output [15:0] DOA; + output [15:0] DOB; + output [1:0] DOPA; + output [1:0] DOPB; + + input ENA, CLKA, SSRA, REGCEA; + input ENB, CLKB, SSRB, REGCEB; + input [13:0] ADDRA; + input [13:0] ADDRB; + input [15:0] DIA; + input [15:0] DIB; + input [1:0] DIPA; + input [1:0] DIPB; + input [1:0] WEA; + input [1:0] WEB; + + tri0 GSR = glbl.GSR; + + wire [7:0] dangle_out8; + wire dangle_out; + wire [1:0] dangle_out2; + wire [5:0] dangle_out6; + wire [15:0] dangle_out16; + wire [47:0] dangle_out48; + + ARAMB36_INTERNAL INT_RAMB (.DIA({48'b0,DIA}), .ENA(ENA), .WEA({4{WEA}}), .SSRA(SSRA), .ADDRA({2'b0,ADDRA[13:0]}), .CLKA(CLKA), .DOA({dangle_out48,DOA}), .DIB({48'b0,DIB}), .ENB(ENB), .WEB({4{WEB}}), .SSRB(SSRB), .ADDRB({2'b0,ADDRB[13:0]}), .CLKB(CLKB), .DOB({dangle_out16,DOB}), .GSR(GSR), .DOPA({dangle_out6,DOPA}), .DOPB({dangle_out2,DOPB}), .DIPA({2'b0,DIPA}), .DIPB({6'b0,DIPB}), .CASCADEOUTLATA(dangle_out), .CASCADEOUTLATB(dangle_out), .CASCADEOUTREGA(dangle_out), .CASCADEOUTREGB(dangle_out), .CASCADEINLATA(1'b0), .CASCADEINLATB(1'b0), .CASCADEINREGA(1'b0), .CASCADEINREGB(1'b0), .REGCEA(REGCEA), .REGCEB(REGCEB), .REGCLKA(CLKA), .REGCLKB(CLKB), .DBITERR(dangle_out), .ECCPARITY(dangle_out8), .SBITERR(dangle_out)); + + defparam INT_RAMB.SIM_MODE = SIM_MODE; + defparam INT_RAMB.BRAM_SIZE = 18; + defparam INT_RAMB.BRAM_MODE = "TRUE_DUAL_PORT"; + defparam INT_RAMB.INIT_A = INIT_A; + defparam INT_RAMB.INIT_B = INIT_B; + defparam INT_RAMB.INIT_FILE = INIT_FILE; + defparam INT_RAMB.SRVAL_A = SRVAL_A; + defparam INT_RAMB.SRVAL_B = SRVAL_B; + defparam INT_RAMB.READ_WIDTH_A = READ_WIDTH_A; + defparam INT_RAMB.READ_WIDTH_B = READ_WIDTH_B; + defparam INT_RAMB.WRITE_WIDTH_A = WRITE_WIDTH_A; + defparam INT_RAMB.WRITE_WIDTH_B = WRITE_WIDTH_B; + defparam INT_RAMB.WRITE_MODE_A = WRITE_MODE_A; + defparam INT_RAMB.WRITE_MODE_B = WRITE_MODE_B; + defparam INT_RAMB.SETUP_ALL = SETUP_ALL; + defparam INT_RAMB.SETUP_READ_FIRST = SETUP_READ_FIRST; + defparam INT_RAMB.SIM_COLLISION_CHECK = SIM_COLLISION_CHECK; + defparam INT_RAMB.EN_ECC_READ = "FALSE"; + defparam INT_RAMB.EN_ECC_SCRUB = "FALSE"; + defparam INT_RAMB.EN_ECC_WRITE = "FALSE"; + defparam INT_RAMB.DOA_REG = DOA_REG; + defparam INT_RAMB.DOB_REG = DOB_REG; + defparam INT_RAMB.INIT_00 = INIT_00; + defparam INT_RAMB.INIT_01 = INIT_01; + defparam INT_RAMB.INIT_02 = INIT_02; + defparam INT_RAMB.INIT_03 = INIT_03; + defparam INT_RAMB.INIT_04 = INIT_04; + defparam INT_RAMB.INIT_05 = INIT_05; + defparam INT_RAMB.INIT_06 = INIT_06; + defparam INT_RAMB.INIT_07 = INIT_07; + defparam INT_RAMB.INIT_08 = INIT_08; + defparam INT_RAMB.INIT_09 = INIT_09; + defparam INT_RAMB.INIT_0A = INIT_0A; + defparam INT_RAMB.INIT_0B = INIT_0B; + defparam INT_RAMB.INIT_0C = INIT_0C; + defparam INT_RAMB.INIT_0D = INIT_0D; + defparam INT_RAMB.INIT_0E = INIT_0E; + defparam INT_RAMB.INIT_0F = INIT_0F; + defparam INT_RAMB.INIT_10 = INIT_10; + defparam INT_RAMB.INIT_11 = INIT_11; + defparam INT_RAMB.INIT_12 = INIT_12; + defparam INT_RAMB.INIT_13 = INIT_13; + defparam INT_RAMB.INIT_14 = INIT_14; + defparam INT_RAMB.INIT_15 = INIT_15; + defparam INT_RAMB.INIT_16 = INIT_16; + defparam INT_RAMB.INIT_17 = INIT_17; + defparam INT_RAMB.INIT_18 = INIT_18; + defparam INT_RAMB.INIT_19 = INIT_19; + defparam INT_RAMB.INIT_1A = INIT_1A; + defparam INT_RAMB.INIT_1B = INIT_1B; + defparam INT_RAMB.INIT_1C = INIT_1C; + defparam INT_RAMB.INIT_1D = INIT_1D; + defparam INT_RAMB.INIT_1E = INIT_1E; + defparam INT_RAMB.INIT_1F = INIT_1F; + defparam INT_RAMB.INIT_20 = INIT_20; + defparam INT_RAMB.INIT_21 = INIT_21; + defparam INT_RAMB.INIT_22 = INIT_22; + defparam INT_RAMB.INIT_23 = INIT_23; + defparam INT_RAMB.INIT_24 = INIT_24; + defparam INT_RAMB.INIT_25 = INIT_25; + defparam INT_RAMB.INIT_26 = INIT_26; + defparam INT_RAMB.INIT_27 = INIT_27; + defparam INT_RAMB.INIT_28 = INIT_28; + defparam INT_RAMB.INIT_29 = INIT_29; + defparam INT_RAMB.INIT_2A = INIT_2A; + defparam INT_RAMB.INIT_2B = INIT_2B; + defparam INT_RAMB.INIT_2C = INIT_2C; + defparam INT_RAMB.INIT_2D = INIT_2D; + defparam INT_RAMB.INIT_2E = INIT_2E; + defparam INT_RAMB.INIT_2F = INIT_2F; + defparam INT_RAMB.INIT_30 = INIT_30; + defparam INT_RAMB.INIT_31 = INIT_31; + defparam INT_RAMB.INIT_32 = INIT_32; + defparam INT_RAMB.INIT_33 = INIT_33; + defparam INT_RAMB.INIT_34 = INIT_34; + defparam INT_RAMB.INIT_35 = INIT_35; + defparam INT_RAMB.INIT_36 = INIT_36; + defparam INT_RAMB.INIT_37 = INIT_37; + defparam INT_RAMB.INIT_38 = INIT_38; + defparam INT_RAMB.INIT_39 = INIT_39; + defparam INT_RAMB.INIT_3A = INIT_3A; + defparam INT_RAMB.INIT_3B = INIT_3B; + defparam INT_RAMB.INIT_3C = INIT_3C; + defparam INT_RAMB.INIT_3D = INIT_3D; + defparam INT_RAMB.INIT_3E = INIT_3E; + defparam INT_RAMB.INIT_3F = INIT_3F; + defparam INT_RAMB.INITP_00 = INITP_00; + defparam INT_RAMB.INITP_01 = INITP_01; + defparam INT_RAMB.INITP_02 = INITP_02; + defparam INT_RAMB.INITP_03 = INITP_03; + defparam INT_RAMB.INITP_04 = INITP_04; + defparam INT_RAMB.INITP_05 = INITP_05; + defparam INT_RAMB.INITP_06 = INITP_06; + defparam INT_RAMB.INITP_07 = INITP_07; + + specify + + (CLKA => DOA[0]) = (100, 100); + (CLKA => DOA[1]) = (100, 100); + (CLKA => DOA[2]) = (100, 100); + (CLKA => DOA[3]) = (100, 100); + (CLKA => DOA[4]) = (100, 100); + (CLKA => DOA[5]) = (100, 100); + (CLKA => DOA[6]) = (100, 100); + (CLKA => DOA[7]) = (100, 100); + (CLKA => DOA[8]) = (100, 100); + (CLKA => DOA[9]) = (100, 100); + (CLKA => DOA[10]) = (100, 100); + (CLKA => DOA[11]) = (100, 100); + (CLKA => DOA[12]) = (100, 100); + (CLKA => DOA[13]) = (100, 100); + (CLKA => DOA[14]) = (100, 100); + (CLKA => DOA[15]) = (100, 100); + (CLKA => DOPA[0]) = (100, 100); + (CLKA => DOPA[1]) = (100, 100); + + (CLKB => DOB[0]) = (100, 100); + (CLKB => DOB[1]) = (100, 100); + (CLKB => DOB[2]) = (100, 100); + (CLKB => DOB[3]) = (100, 100); + (CLKB => DOB[4]) = (100, 100); + (CLKB => DOB[5]) = (100, 100); + (CLKB => DOB[6]) = (100, 100); + (CLKB => DOB[7]) = (100, 100); + (CLKB => DOB[8]) = (100, 100); + (CLKB => DOB[9]) = (100, 100); + (CLKB => DOB[10]) = (100, 100); + (CLKB => DOB[11]) = (100, 100); + (CLKB => DOB[12]) = (100, 100); + (CLKB => DOB[13]) = (100, 100); + (CLKB => DOB[14]) = (100, 100); + (CLKB => DOB[15]) = (100, 100); + (CLKB => DOPB[0]) = (100, 100); + (CLKB => DOPB[1]) = (100, 100); + + specparam PATHPULSE$ = 0; + + endspecify + +endmodule // RAMB18 + + + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/RAMB18E1.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/RAMB18E1.v new file mode 100644 index 0000000..22aff3b --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/RAMB18E1.v @@ -0,0 +1,3565 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/blanc/RAMB18E1.v,v 1.16.24.4.6.1 2010/06/14 22:48:42 wloo Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2008 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / 16K-Bit Data and 2K-Bit Parity Dual Port Block RAM +// /___/ /\ Filename : RAMB18E1.v +// \ \ / \ Timestamp : Tue Feb 26 13:49:08 PST 2008 +// \___\/\___\ +// +// Revision: +// 02/26/08 - Initial version. +// 07/25/08 - Fixed ECC in register mode. (IR 477257) +// 07/30/08 - Updated to support SDP mode with smaller port width <= 18. (IR 477258) +// 11/04/08 - Fixed incorrect output during first clock cycle. (CR 470964) +// 03/11/09 - X's the unused bits of outputs (CR 511363). +// 03/23/09 - Fixed unusual behavior of X's in the unused bits of outputs (CR 513167). +// 04/10/09 - Implemented workaround for NCSim event triggering during initial time (CR 517450). +// 08/03/09 - Updated collision behavior when both clocks are in phase/within 100 ps (CR 522327). +// 08/12/09 - Updated collision address check for none in phase clocks (CR 527010). +// 08/18/09 - Fixed output delay in SDP mode (CR 528259). +// 11/18/09 - Define tasks and functions before calling (CR 532610). +// 12/16/09 - Enhanced memory initialization (CR 540764). +// 03/15/10 - Updated address collision for asynchronous clocks and read first mode (CR 527010). +// 04/01/10 - Fixed clocks detection for collision (CR 552123). +// 05/11/10 - Updated clocks detection for collision (CR 557624). +// - Added attribute RDADDR_COLLISION_HWCONFIG (CR 557971). +// 05/25/10 - Added WRITE_FIRST support in SDP mode (CR 561807). +// 06/03/10 - Added functionality for attribute RDADDR_COLLISION_HWCONFIG (CR 557971). +// End Revision + +`timescale 1 ps / 1 ps + +module RAMB18E1 (DOADO, DOBDO, DOPADOP, DOPBDOP, + ADDRARDADDR, ADDRBWRADDR, CLKARDCLK, CLKBWRCLK, DIADI, DIBDI, DIPADIP, DIPBDIP, ENARDEN, ENBWREN, REGCEAREGCE, REGCEB, RSTRAMARSTRAM, RSTRAMB, RSTREGARSTREG, RSTREGB, WEA, WEBWE); + + parameter integer DOA_REG = 0; + parameter integer DOB_REG = 0; + parameter INITP_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_A = 18'h0; + parameter INIT_B = 18'h0; + parameter INIT_FILE = "NONE"; + parameter RAM_MODE = "TDP"; + parameter RDADDR_COLLISION_HWCONFIG = "DELAYED_WRITE"; + parameter integer READ_WIDTH_A = 0; + parameter integer READ_WIDTH_B = 0; + parameter RSTREG_PRIORITY_A = "RSTREG"; + parameter RSTREG_PRIORITY_B = "RSTREG"; + parameter SIM_COLLISION_CHECK = "ALL"; + parameter SRVAL_A = 18'h0; + parameter SRVAL_B = 18'h0; + parameter WRITE_MODE_A = "WRITE_FIRST"; + parameter WRITE_MODE_B = "WRITE_FIRST"; + parameter integer WRITE_WIDTH_A = 0; + parameter integer WRITE_WIDTH_B = 0; + + localparam SETUP_ALL = 1000; + localparam SETUP_READ_FIRST = 3000; + + output [15:0] DOADO; + output [15:0] DOBDO; + output [1:0] DOPADOP; + output [1:0] DOPBDOP; + + input CLKARDCLK; + input CLKBWRCLK; + input ENARDEN; + input ENBWREN; + input REGCEAREGCE; + input REGCEB; + input RSTRAMARSTRAM; + input RSTRAMB; + input RSTREGARSTREG; + input RSTREGB; + input [13:0] ADDRARDADDR; + input [13:0] ADDRBWRADDR; + input [15:0] DIADI; + input [15:0] DIBDI; + input [1:0] DIPADIP; + input [1:0] DIPBDIP; + input [1:0] WEA; + input [3:0] WEBWE; + + tri0 GSR = glbl.GSR; + + wire [7:0] dangle_out8; + wire [8:0] dangle_out9; + wire dangle_out; + wire [1:0] dangle_out2; + wire [3:0] dangle_out4; + wire [5:0] dangle_out6; + wire [15:0] dangle_out16; + wire [31:0] dangle_out32; + wire [47:0] dangle_out48; + + + // special handle for sdp width = 36 + localparam init_sdp = (READ_WIDTH_A == 36) ? {INIT_B[17:16],INIT_A[17:16],INIT_B[15:0],INIT_A[15:0]} : {INIT_B, INIT_A}; + localparam srval_sdp = (READ_WIDTH_A == 36) ? {SRVAL_B[17:16],SRVAL_A[17:16],SRVAL_B[15:0],SRVAL_A[15:0]} : {SRVAL_B, SRVAL_A}; + + + generate + case (RAM_MODE) + + "TDP" : begin + + RB18_INTERNAL_VLOG #(.RAM_MODE(RAM_MODE), + .INIT_A(INIT_A), + .INIT_B(INIT_B), + .INIT_FILE(INIT_FILE), + .SRVAL_A(SRVAL_A), + .SRVAL_B(SRVAL_B), + .RDADDR_COLLISION_HWCONFIG(RDADDR_COLLISION_HWCONFIG), + .READ_WIDTH_A(READ_WIDTH_A), + .READ_WIDTH_B(READ_WIDTH_B), + .WRITE_WIDTH_A(WRITE_WIDTH_A), + .WRITE_WIDTH_B(WRITE_WIDTH_B), + .WRITE_MODE_A(WRITE_MODE_A), + .WRITE_MODE_B(WRITE_MODE_B), + .SETUP_ALL(SETUP_ALL), + .SETUP_READ_FIRST(SETUP_READ_FIRST), + .SIM_COLLISION_CHECK(SIM_COLLISION_CHECK), + .DOA_REG(DOA_REG), + .DOB_REG(DOB_REG), + .RSTREG_PRIORITY_A(RSTREG_PRIORITY_A), + .RSTREG_PRIORITY_B(RSTREG_PRIORITY_B), + .BRAM_SIZE(18), + .INIT_00(INIT_00), + .INIT_01(INIT_01), + .INIT_02(INIT_02), + .INIT_03(INIT_03), + .INIT_04(INIT_04), + .INIT_05(INIT_05), + .INIT_06(INIT_06), + .INIT_07(INIT_07), + .INIT_08(INIT_08), + .INIT_09(INIT_09), + .INIT_0A(INIT_0A), + .INIT_0B(INIT_0B), + .INIT_0C(INIT_0C), + .INIT_0D(INIT_0D), + .INIT_0E(INIT_0E), + .INIT_0F(INIT_0F), + .INIT_10(INIT_10), + .INIT_11(INIT_11), + .INIT_12(INIT_12), + .INIT_13(INIT_13), + .INIT_14(INIT_14), + .INIT_15(INIT_15), + .INIT_16(INIT_16), + .INIT_17(INIT_17), + .INIT_18(INIT_18), + .INIT_19(INIT_19), + .INIT_1A(INIT_1A), + .INIT_1B(INIT_1B), + .INIT_1C(INIT_1C), + .INIT_1D(INIT_1D), + .INIT_1E(INIT_1E), + .INIT_1F(INIT_1F), + .INIT_20(INIT_20), + .INIT_21(INIT_21), + .INIT_22(INIT_22), + .INIT_23(INIT_23), + .INIT_24(INIT_24), + .INIT_25(INIT_25), + .INIT_26(INIT_26), + .INIT_27(INIT_27), + .INIT_28(INIT_28), + .INIT_29(INIT_29), + .INIT_2A(INIT_2A), + .INIT_2B(INIT_2B), + .INIT_2C(INIT_2C), + .INIT_2D(INIT_2D), + .INIT_2E(INIT_2E), + .INIT_2F(INIT_2F), + .INIT_30(INIT_30), + .INIT_31(INIT_31), + .INIT_32(INIT_32), + .INIT_33(INIT_33), + .INIT_34(INIT_34), + .INIT_35(INIT_35), + .INIT_36(INIT_36), + .INIT_37(INIT_37), + .INIT_38(INIT_38), + .INIT_39(INIT_39), + .INIT_3A(INIT_3A), + .INIT_3B(INIT_3B), + .INIT_3C(INIT_3C), + .INIT_3D(INIT_3D), + .INIT_3E(INIT_3E), + .INIT_3F(INIT_3F), + .INITP_00(INITP_00), + .INITP_01(INITP_01), + .INITP_02(INITP_02), + .INITP_03(INITP_03), + .INITP_04(INITP_04), + .INITP_05(INITP_05), + .INITP_06(INITP_06), + .INITP_07(INITP_07)) + + INT_RAMB_TDP (.ADDRA({2'b0,ADDRARDADDR}), + .ADDRB({2'b0,ADDRBWRADDR}), + .CASCADEINA(1'b0), + .CASCADEINB(1'b0), + .CASCADEOUTA(dangle_out), + .CASCADEOUTB(dangle_out), + .CLKA(CLKARDCLK), + .CLKB(CLKBWRCLK), + .DBITERR(dangle_out), + .DIA({48'b0,DIADI}), + .DIB({48'b0,DIBDI}), + .DIPA({2'b0,DIPADIP}), + .DIPB({6'b0,DIPBDIP}), + .DOA({dangle_out48,DOADO}), + .DOB({dangle_out16,DOBDO}), + .DOPA({dangle_out6,DOPADOP}), + .DOPB({dangle_out2,DOPBDOP}), + .ECCPARITY(dangle_out8), + .ENA(ENARDEN), + .ENB(ENBWREN), + .GSR(GSR), + .INJECTDBITERR(1'b0), + .INJECTSBITERR(1'b0), + .RDADDRECC(dangle_out9), + .REGCEA(REGCEAREGCE), + .REGCEB(REGCEB), + .RSTRAMA(RSTRAMARSTRAM), + .RSTRAMB(RSTRAMB), + .RSTREGA(RSTREGARSTREG), + .RSTREGB(RSTREGB), + .SBITERR(dangle_out), + .WEA({4{WEA}}), + .WEB({2{WEBWE}})); + + end // case: "TDP" + "SDP" : begin + + if (WRITE_WIDTH_B == 36) begin + + RB18_INTERNAL_VLOG #(.RAM_MODE(RAM_MODE), + .INIT_A({36'b0,init_sdp}), + .INIT_B({36'b0,init_sdp}), + .INIT_FILE(INIT_FILE), + .SRVAL_A({36'b0,{srval_sdp}}), + .SRVAL_B({36'b0,{srval_sdp}}), + .RDADDR_COLLISION_HWCONFIG(RDADDR_COLLISION_HWCONFIG), + .READ_WIDTH_A(READ_WIDTH_A), + .READ_WIDTH_B(READ_WIDTH_B), + .WRITE_WIDTH_A(WRITE_WIDTH_A), + .WRITE_WIDTH_B(WRITE_WIDTH_B), + .WRITE_MODE_A(WRITE_MODE_A), + .WRITE_MODE_B(WRITE_MODE_B), + .SETUP_ALL(SETUP_ALL), + .SETUP_READ_FIRST(SETUP_READ_FIRST), + .SIM_COLLISION_CHECK(SIM_COLLISION_CHECK), + .DOA_REG(DOA_REG), + .DOB_REG(DOB_REG), + .RSTREG_PRIORITY_A(RSTREG_PRIORITY_A), + .RSTREG_PRIORITY_B(RSTREG_PRIORITY_B), + .BRAM_SIZE(18), + .INIT_00(INIT_00), + .INIT_01(INIT_01), + .INIT_02(INIT_02), + .INIT_03(INIT_03), + .INIT_04(INIT_04), + .INIT_05(INIT_05), + .INIT_06(INIT_06), + .INIT_07(INIT_07), + .INIT_08(INIT_08), + .INIT_09(INIT_09), + .INIT_0A(INIT_0A), + .INIT_0B(INIT_0B), + .INIT_0C(INIT_0C), + .INIT_0D(INIT_0D), + .INIT_0E(INIT_0E), + .INIT_0F(INIT_0F), + .INIT_10(INIT_10), + .INIT_11(INIT_11), + .INIT_12(INIT_12), + .INIT_13(INIT_13), + .INIT_14(INIT_14), + .INIT_15(INIT_15), + .INIT_16(INIT_16), + .INIT_17(INIT_17), + .INIT_18(INIT_18), + .INIT_19(INIT_19), + .INIT_1A(INIT_1A), + .INIT_1B(INIT_1B), + .INIT_1C(INIT_1C), + .INIT_1D(INIT_1D), + .INIT_1E(INIT_1E), + .INIT_1F(INIT_1F), + .INIT_20(INIT_20), + .INIT_21(INIT_21), + .INIT_22(INIT_22), + .INIT_23(INIT_23), + .INIT_24(INIT_24), + .INIT_25(INIT_25), + .INIT_26(INIT_26), + .INIT_27(INIT_27), + .INIT_28(INIT_28), + .INIT_29(INIT_29), + .INIT_2A(INIT_2A), + .INIT_2B(INIT_2B), + .INIT_2C(INIT_2C), + .INIT_2D(INIT_2D), + .INIT_2E(INIT_2E), + .INIT_2F(INIT_2F), + .INIT_30(INIT_30), + .INIT_31(INIT_31), + .INIT_32(INIT_32), + .INIT_33(INIT_33), + .INIT_34(INIT_34), + .INIT_35(INIT_35), + .INIT_36(INIT_36), + .INIT_37(INIT_37), + .INIT_38(INIT_38), + .INIT_39(INIT_39), + .INIT_3A(INIT_3A), + .INIT_3B(INIT_3B), + .INIT_3C(INIT_3C), + .INIT_3D(INIT_3D), + .INIT_3E(INIT_3E), + .INIT_3F(INIT_3F), + .INITP_00(INITP_00), + .INITP_01(INITP_01), + .INITP_02(INITP_02), + .INITP_03(INITP_03), + .INITP_04(INITP_04), + .INITP_05(INITP_05), + .INITP_06(INITP_06), + .INITP_07(INITP_07)) + + INT_RAMB_SDP (.ADDRA({2'b0,ADDRARDADDR}), + .ADDRB({2'b0,ADDRBWRADDR}), + .CASCADEINA(1'b0), + .CASCADEINB(1'b0), + .CASCADEOUTA(dangle_out), + .CASCADEOUTB(dangle_out), + .CLKA(CLKARDCLK), + .CLKB(CLKBWRCLK), + .DBITERR(dangle_out), + .DIA(64'b0), + .DIB({32'b0,DIBDI,DIADI}), + .DIPA(4'b0), + .DIPB({4'b0,DIPBDIP,DIPADIP}), + .DOA({dangle_out32,DOBDO,DOADO}), + .DOB(dangle_out32), + .DOPA({dangle_out4,DOPBDOP,DOPADOP}), + .DOPB(dangle_out4), + .ECCPARITY(dangle_out8), + .ENA(ENARDEN), + .ENB(ENBWREN), + .GSR(GSR), + .INJECTDBITERR(1'b0), + .INJECTSBITERR(1'b0), + .RDADDRECC(dangle_out9), + .REGCEA(REGCEAREGCE), + .REGCEB(REGCEB), + .RSTRAMA(RSTRAMARSTRAM), + .RSTRAMB(RSTRAMB), + .RSTREGA(RSTREGARSTREG), + .RSTREGB(RSTREGB), + .SBITERR(dangle_out), + .WEA(8'b0), + .WEB({2{WEBWE}})); + + end // if (WRITE_WIDTH_B == 36) + else begin + + RB18_INTERNAL_VLOG #(.RAM_MODE(RAM_MODE), + .INIT_A({36'b0,init_sdp}), + .INIT_B({36'b0,init_sdp}), + .INIT_FILE(INIT_FILE), + .SRVAL_A({36'b0,{srval_sdp}}), + .SRVAL_B({36'b0,{srval_sdp}}), + .RDADDR_COLLISION_HWCONFIG(RDADDR_COLLISION_HWCONFIG), + .READ_WIDTH_A(READ_WIDTH_A), + .READ_WIDTH_B(READ_WIDTH_B), + .WRITE_WIDTH_A(WRITE_WIDTH_A), + .WRITE_WIDTH_B(WRITE_WIDTH_B), + .WRITE_MODE_A(WRITE_MODE_A), + .WRITE_MODE_B(WRITE_MODE_B), + .SETUP_ALL(SETUP_ALL), + .SETUP_READ_FIRST(SETUP_READ_FIRST), + .SIM_COLLISION_CHECK(SIM_COLLISION_CHECK), + .DOA_REG(DOA_REG), + .DOB_REG(DOB_REG), + .RSTREG_PRIORITY_A(RSTREG_PRIORITY_A), + .RSTREG_PRIORITY_B(RSTREG_PRIORITY_B), + .BRAM_SIZE(18), + .INIT_00(INIT_00), + .INIT_01(INIT_01), + .INIT_02(INIT_02), + .INIT_03(INIT_03), + .INIT_04(INIT_04), + .INIT_05(INIT_05), + .INIT_06(INIT_06), + .INIT_07(INIT_07), + .INIT_08(INIT_08), + .INIT_09(INIT_09), + .INIT_0A(INIT_0A), + .INIT_0B(INIT_0B), + .INIT_0C(INIT_0C), + .INIT_0D(INIT_0D), + .INIT_0E(INIT_0E), + .INIT_0F(INIT_0F), + .INIT_10(INIT_10), + .INIT_11(INIT_11), + .INIT_12(INIT_12), + .INIT_13(INIT_13), + .INIT_14(INIT_14), + .INIT_15(INIT_15), + .INIT_16(INIT_16), + .INIT_17(INIT_17), + .INIT_18(INIT_18), + .INIT_19(INIT_19), + .INIT_1A(INIT_1A), + .INIT_1B(INIT_1B), + .INIT_1C(INIT_1C), + .INIT_1D(INIT_1D), + .INIT_1E(INIT_1E), + .INIT_1F(INIT_1F), + .INIT_20(INIT_20), + .INIT_21(INIT_21), + .INIT_22(INIT_22), + .INIT_23(INIT_23), + .INIT_24(INIT_24), + .INIT_25(INIT_25), + .INIT_26(INIT_26), + .INIT_27(INIT_27), + .INIT_28(INIT_28), + .INIT_29(INIT_29), + .INIT_2A(INIT_2A), + .INIT_2B(INIT_2B), + .INIT_2C(INIT_2C), + .INIT_2D(INIT_2D), + .INIT_2E(INIT_2E), + .INIT_2F(INIT_2F), + .INIT_30(INIT_30), + .INIT_31(INIT_31), + .INIT_32(INIT_32), + .INIT_33(INIT_33), + .INIT_34(INIT_34), + .INIT_35(INIT_35), + .INIT_36(INIT_36), + .INIT_37(INIT_37), + .INIT_38(INIT_38), + .INIT_39(INIT_39), + .INIT_3A(INIT_3A), + .INIT_3B(INIT_3B), + .INIT_3C(INIT_3C), + .INIT_3D(INIT_3D), + .INIT_3E(INIT_3E), + .INIT_3F(INIT_3F), + .INITP_00(INITP_00), + .INITP_01(INITP_01), + .INITP_02(INITP_02), + .INITP_03(INITP_03), + .INITP_04(INITP_04), + .INITP_05(INITP_05), + .INITP_06(INITP_06), + .INITP_07(INITP_07)) + + INT_RAMB_SDP (.ADDRA({2'b0,ADDRARDADDR}), + .ADDRB({2'b0,ADDRBWRADDR}), + .CASCADEINA(1'b0), + .CASCADEINB(1'b0), + .CASCADEOUTA(dangle_out), + .CASCADEOUTB(dangle_out), + .CLKA(CLKARDCLK), + .CLKB(CLKBWRCLK), + .DBITERR(dangle_out), + .DIA(64'b0), + .DIB({48'b0,DIBDI}), + .DIPA(4'b0), + .DIPB({6'b0,DIPBDIP}), + .DOA({dangle_out32,DOBDO,DOADO}), + .DOB(dangle_out32), + .DOPA({dangle_out4,DOPBDOP,DOPADOP}), + .DOPB(dangle_out4), + .ECCPARITY(dangle_out8), + .ENA(ENARDEN), + .ENB(ENBWREN), + .GSR(GSR), + .INJECTDBITERR(1'b0), + .INJECTSBITERR(1'b0), + .RDADDRECC(dangle_out9), + .REGCEA(REGCEAREGCE), + .REGCEB(REGCEB), + .RSTRAMA(RSTRAMARSTRAM), + .RSTRAMB(RSTRAMB), + .RSTREGA(RSTREGARSTREG), + .RSTREGB(RSTREGB), + .SBITERR(dangle_out), + .WEA(8'b0), + .WEB({2{WEBWE}})); + end // else: !if(WRITE_WIDTH_B == 36) + + end // case: "SDP" + + endcase // case(RAM_MODE) + endgenerate + + + specify + + (CLKARDCLK => DOADO[0]) = (100, 100); + (CLKARDCLK => DOADO[1]) = (100, 100); + (CLKARDCLK => DOADO[2]) = (100, 100); + (CLKARDCLK => DOADO[3]) = (100, 100); + (CLKARDCLK => DOADO[4]) = (100, 100); + (CLKARDCLK => DOADO[5]) = (100, 100); + (CLKARDCLK => DOADO[6]) = (100, 100); + (CLKARDCLK => DOADO[7]) = (100, 100); + (CLKARDCLK => DOADO[8]) = (100, 100); + (CLKARDCLK => DOADO[9]) = (100, 100); + (CLKARDCLK => DOADO[10]) = (100, 100); + (CLKARDCLK => DOADO[11]) = (100, 100); + (CLKARDCLK => DOADO[12]) = (100, 100); + (CLKARDCLK => DOADO[13]) = (100, 100); + (CLKARDCLK => DOADO[14]) = (100, 100); + (CLKARDCLK => DOADO[15]) = (100, 100); + (CLKARDCLK => DOPADOP[0]) = (100, 100); + (CLKARDCLK => DOPADOP[1]) = (100, 100); + + if (RAM_MODE == "SDP") (CLKARDCLK => DOBDO[0]) = (100, 100); + if (RAM_MODE == "SDP") (CLKARDCLK => DOBDO[1]) = (100, 100); + if (RAM_MODE == "SDP") (CLKARDCLK => DOBDO[2]) = (100, 100); + if (RAM_MODE == "SDP") (CLKARDCLK => DOBDO[3]) = (100, 100); + if (RAM_MODE == "SDP") (CLKARDCLK => DOBDO[4]) = (100, 100); + if (RAM_MODE == "SDP") (CLKARDCLK => DOBDO[5]) = (100, 100); + if (RAM_MODE == "SDP") (CLKARDCLK => DOBDO[6]) = (100, 100); + if (RAM_MODE == "SDP") (CLKARDCLK => DOBDO[7]) = (100, 100); + if (RAM_MODE == "SDP") (CLKARDCLK => DOBDO[8]) = (100, 100); + if (RAM_MODE == "SDP") (CLKARDCLK => DOBDO[9]) = (100, 100); + if (RAM_MODE == "SDP") (CLKARDCLK => DOBDO[10]) = (100, 100); + if (RAM_MODE == "SDP") (CLKARDCLK => DOBDO[11]) = (100, 100); + if (RAM_MODE == "SDP") (CLKARDCLK => DOBDO[12]) = (100, 100); + if (RAM_MODE == "SDP") (CLKARDCLK => DOBDO[13]) = (100, 100); + if (RAM_MODE == "SDP") (CLKARDCLK => DOBDO[14]) = (100, 100); + if (RAM_MODE == "SDP") (CLKARDCLK => DOBDO[15]) = (100, 100); + if (RAM_MODE == "SDP") (CLKARDCLK => DOPBDOP[0]) = (100, 100); + if (RAM_MODE == "SDP") (CLKARDCLK => DOPBDOP[1]) = (100, 100); + + if (RAM_MODE == "TDP") (CLKBWRCLK => DOBDO[0]) = (100, 100); + if (RAM_MODE == "TDP") (CLKBWRCLK => DOBDO[1]) = (100, 100); + if (RAM_MODE == "TDP") (CLKBWRCLK => DOBDO[2]) = (100, 100); + if (RAM_MODE == "TDP") (CLKBWRCLK => DOBDO[3]) = (100, 100); + if (RAM_MODE == "TDP") (CLKBWRCLK => DOBDO[4]) = (100, 100); + if (RAM_MODE == "TDP") (CLKBWRCLK => DOBDO[5]) = (100, 100); + if (RAM_MODE == "TDP") (CLKBWRCLK => DOBDO[6]) = (100, 100); + if (RAM_MODE == "TDP") (CLKBWRCLK => DOBDO[7]) = (100, 100); + if (RAM_MODE == "TDP") (CLKBWRCLK => DOBDO[8]) = (100, 100); + if (RAM_MODE == "TDP") (CLKBWRCLK => DOBDO[9]) = (100, 100); + if (RAM_MODE == "TDP") (CLKBWRCLK => DOBDO[10]) = (100, 100); + if (RAM_MODE == "TDP") (CLKBWRCLK => DOBDO[11]) = (100, 100); + if (RAM_MODE == "TDP") (CLKBWRCLK => DOBDO[12]) = (100, 100); + if (RAM_MODE == "TDP") (CLKBWRCLK => DOBDO[13]) = (100, 100); + if (RAM_MODE == "TDP") (CLKBWRCLK => DOBDO[14]) = (100, 100); + if (RAM_MODE == "TDP") (CLKBWRCLK => DOBDO[15]) = (100, 100); + if (RAM_MODE == "TDP") (CLKBWRCLK => DOPBDOP[0]) = (100, 100); + if (RAM_MODE == "TDP") (CLKBWRCLK => DOPBDOP[1]) = (100, 100); + + specparam PATHPULSE$ = 0; + + endspecify + +endmodule // RAMB18E1 + + +// WARNING !!!: The following model is not an user primitive. +// Please do not modify any part of it. RAMB18E1 may not work properly if do so. +// +`timescale 1 ps/1 ps + +module RB18_INTERNAL_VLOG (CASCADEOUTA, CASCADEOUTB, DBITERR, DOA, DOB, DOPA, DOPB, ECCPARITY, RDADDRECC, SBITERR, + ADDRA, ADDRB, CASCADEINA, CASCADEINB, CLKA, CLKB, DIA, DIB, DIPA, DIPB, ENA, ENB, GSR, INJECTDBITERR, INJECTSBITERR, REGCEA, REGCEB, RSTRAMA, RSTRAMB, RSTREGA, RSTREGB, WEA, WEB); + + output CASCADEOUTA; + output CASCADEOUTB; + output SBITERR, DBITERR; + output [8:0] RDADDRECC; + output [63:0] DOA; + output [31:0] DOB; + output [7:0] DOPA; + output [3:0] DOPB; + output [7:0] ECCPARITY; + + input ENA, CLKA, CASCADEINA, REGCEA; + input ENB, CLKB, CASCADEINB, REGCEB; + input GSR; + input RSTRAMA, RSTRAMB; + input RSTREGA, RSTREGB; + input INJECTDBITERR, INJECTSBITERR; + input [15:0] ADDRA; + input [15:0] ADDRB; + input [63:0] DIA; + input [63:0] DIB; + input [3:0] DIPA; + input [7:0] DIPB; + input [7:0] WEA; + input [7:0] WEB; + + parameter DOA_REG = 0; + parameter DOB_REG = 0; + parameter EN_ECC_READ = "FALSE"; + parameter EN_ECC_WRITE = "FALSE"; + parameter INIT_A = 72'h0; + parameter INIT_B = 72'h0; + parameter RAM_EXTENSION_A = "NONE"; + parameter RAM_EXTENSION_B = "NONE"; + parameter RAM_MODE = "TDP"; + parameter RDADDR_COLLISION_HWCONFIG = "DELAYED_WRITE"; + parameter READ_WIDTH_A = 0; + parameter READ_WIDTH_B = 0; + parameter RSTREG_PRIORITY_A = "RSTREG"; + parameter RSTREG_PRIORITY_B = "RSTREG"; + parameter SETUP_ALL = 1000; + parameter SETUP_READ_FIRST = 3000; + parameter SIM_COLLISION_CHECK = "ALL"; + parameter SRVAL_A = 72'h0; + parameter SRVAL_B = 72'h0; + parameter WRITE_MODE_A = "WRITE_FIRST"; + parameter WRITE_MODE_B = "WRITE_FIRST"; + parameter WRITE_WIDTH_A = 0; + parameter WRITE_WIDTH_B = 0; + parameter INIT_FILE = "NONE"; + + parameter INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_40 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_41 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_42 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_43 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_44 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_45 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_46 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_47 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_48 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_49 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_4A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_4B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_4C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_4D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_4E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_4F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_50 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_51 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_52 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_53 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_54 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_55 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_56 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_57 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_58 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_59 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_5A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_5B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_5C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_5D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_5E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_5F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_60 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_61 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_62 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_63 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_64 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_65 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_66 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_67 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_68 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_69 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_6A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_6B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_6C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_6D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_6E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_6F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_70 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_71 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_72 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_73 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_74 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_75 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_76 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_77 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_78 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_79 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_7A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_7B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_7C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_7D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_7E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_7F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + +// xilinx_internal_parameter on + // WARNING !!!: This model may not work properly if the following parameters are changed. + parameter BRAM_SIZE = 36; +// xilinx_internal_parameter off + + + integer count, countp, init_mult, initp_mult, large_width; + integer count1, countp1, i, i1, i_p, i_mem, init_offset, initp_offset; + integer viol_time = 0; + integer rdaddr_collision_hwconfig_int, rstreg_priority_a_int, rstreg_priority_b_int; + integer ram_mode_int, en_ecc_write_int, en_ecc_read_int; + + reg addra_in_15_reg_bram, addrb_in_15_reg_bram; + reg addra_in_15_reg, addrb_in_15_reg; + reg addra_in_15_reg1, addrb_in_15_reg1; + reg junk1; + reg [1:0] wr_mode_a, wr_mode_b, cascade_a, cascade_b; + reg [63:0] doa_out = 64'b0, doa_buf = 64'b0, doa_outreg = 64'b0, doa_out_out; + reg [31:0] dob_out = 32'b0, dob_buf = 32'b0, dob_outreg = 32'b0, dob_out_out; + reg [3:0] dopb_out = 4'b0, dopb_buf = 4'b0, dopb_outreg = 4'b0, dopb_out_out; + reg [7:0] dopa_out = 8'b0, dopa_buf = 8'b0, dopa_outreg = 8'b0, dopa_out_out; + reg [63:0] doa_out_mux = 64'b0, doa_outreg_mux = 64'b0; + reg [7:0] dopa_out_mux = 8'b0, dopa_outreg_mux = 8'b0; + reg [63:0] dob_out_mux = 64'b0, dob_outreg_mux = 64'b0; + reg [7:0] dopb_out_mux = 8'b0, dopb_outreg_mux = 8'b0; + + reg [7:0] eccparity_out = 8'b0; + reg [7:0] dopr_ecc, syndrome = 8'b0; + reg [7:0] dipb_in_ecc; + reg [71:0] ecc_bit_position; + reg [7:0] dip_ecc, dip_ecc_col, dipa_in_ecc_corrected; + reg [63:0] dib_in_ecc, dib_ecc_col, dia_in_ecc_corrected, di_x = 64'bx; + reg dbiterr_out = 0, sbiterr_out = 0; + reg dbiterr_outreg = 0, sbiterr_outreg = 0; + reg dbiterr_out_out = 0, sbiterr_out_out = 0; + + reg [7:0] wea_reg; + reg enb_reg; + reg [7:0] out_a = 8'b0, out_b = 8'b0, junk, web_reg, web_tmp; + reg outp_a = 1'b0, outp_b = 1'b0, junkp; + reg rising_clka = 1'b0, rising_clkb = 1'b0; + reg [15:0] addra_reg, addrb_reg, addra_tmp, addrb_tmp; + + reg [63:0] dia_reg, dib_reg; + reg [3:0] dipa_reg; + reg [7:0] dipb_reg; + reg [1:0] viol_type = 2'b00, seq = 2'b00; + reg [15:0] addr_tmp; + reg [7:0] we_tmp; + reg col_wr_wr_msg = 1, col_wra_rdb_msg = 1, col_wrb_rda_msg = 1; + reg [7:0] no_col = 8'b0; + reg [8:0] rdaddrecc_out = 9'b0, rdaddrecc_outreg = 9'b0; + reg [8:0] rdaddrecc_out_out = 9'b0; + reg finish_error = 0; + + time time_port_a, time_port_b; + + wire [63:0] dib_in; + wire [63:0] dia_in; + wire [15:0] addra_in, addrb_in; + wire clka_in, clkb_in; + wire [7:0] dipb_in; + wire [3:0] dipa_in; + wire ena_in, enb_in, gsr_in, regcea_in, regceb_in, rstrama_in, rstramb_in; + wire [7:0] wea_in; + wire [7:0] web_in; + wire cascadeina_in, cascadeinb_in; + wire injectdbiterr_in, injectsbiterr_in; + wire rstrega_in, rstregb_in; + wire [15:0] col_addra_reconstruct, col_addrb_reconstruct; + reg [15:0] col_addra_reconstruct_reg, col_addrb_reconstruct_reg; + + wire temp_wire; // trigger NCsim at initial time + assign temp_wire = 1; + + + assign addra_in = ADDRA; + assign addrb_in = ADDRB; + assign clka_in = CLKA; + assign clkb_in = CLKB; + + assign dia_in = DIA; + assign dib_in = DIB; + assign dipa_in = DIPA; + assign dipb_in = DIPB; + assign DOA = doa_out_out; + + assign DOPA = dopa_out_out; + assign DOB = dob_out_out; + assign DOPB = dopb_out_out; + + assign ena_in = ENA; + assign enb_in = ENB; + assign gsr_in = GSR; + assign regcea_in = REGCEA; + assign regceb_in = REGCEB; + assign rstrama_in = RSTRAMA; + assign rstramb_in = RSTRAMB; + assign wea_in = WEA; + assign web_in = WEB; + assign cascadeina_in = CASCADEINA; + assign cascadeinb_in = CASCADEINB; + assign CASCADEOUTA = doa_out_out[0]; + assign CASCADEOUTB = dob_out_out[0]; + assign SBITERR = sbiterr_out_out; + assign DBITERR = dbiterr_out_out; + assign ECCPARITY = eccparity_out; + assign RDADDRECC = rdaddrecc_out_out; + assign injectdbiterr_in = INJECTDBITERR; + assign injectsbiterr_in = INJECTSBITERR; + assign rstrega_in = RSTREGA; + assign rstregb_in = RSTREGB; + + + // Determine memory size + localparam widest_width = (WRITE_WIDTH_A >= WRITE_WIDTH_B && WRITE_WIDTH_A >= READ_WIDTH_A && + WRITE_WIDTH_A >= READ_WIDTH_B) ? WRITE_WIDTH_A : + (WRITE_WIDTH_B >= WRITE_WIDTH_A && WRITE_WIDTH_B >= READ_WIDTH_A && + WRITE_WIDTH_B >= READ_WIDTH_B) ? WRITE_WIDTH_B : + (READ_WIDTH_A >= WRITE_WIDTH_A && READ_WIDTH_A >= WRITE_WIDTH_B && + READ_WIDTH_A >= READ_WIDTH_B) ? READ_WIDTH_A : + (READ_WIDTH_B >= WRITE_WIDTH_A && READ_WIDTH_B >= WRITE_WIDTH_B && + READ_WIDTH_B >= READ_WIDTH_A) ? READ_WIDTH_B : 64; + + localparam wa_width = (WRITE_WIDTH_A == 1) ? 1 : (WRITE_WIDTH_A == 2) ? 2 : (WRITE_WIDTH_A == 4) ? 4 : + (WRITE_WIDTH_A == 9) ? 8 : (WRITE_WIDTH_A == 18) ? 16 : (WRITE_WIDTH_A == 36) ? 32 : + (WRITE_WIDTH_A == 72) ? 64 : 64; + + localparam wb_width = (WRITE_WIDTH_B == 1) ? 1 : (WRITE_WIDTH_B == 2) ? 2 : (WRITE_WIDTH_B == 4) ? 4 : + (WRITE_WIDTH_B == 9) ? 8 : (WRITE_WIDTH_B == 18) ? 16 : (WRITE_WIDTH_B == 36) ? 32 : + (WRITE_WIDTH_B == 72) ? 64 : 64; + + + localparam wa_widthp = (WRITE_WIDTH_A == 9) ? 1 : (WRITE_WIDTH_A == 18) ? 2 : (WRITE_WIDTH_A == 36) ? 4 : + (WRITE_WIDTH_A == 72) ? 8 : 8; + + localparam wb_widthp = (WRITE_WIDTH_B == 9) ? 1 : (WRITE_WIDTH_B == 18) ? 2 : (WRITE_WIDTH_B == 36) ? 4 : + (WRITE_WIDTH_B == 72) ? 8 : 8; + + + localparam ra_width = (READ_WIDTH_A == 1) ? 1 : (READ_WIDTH_A == 2) ? 2 : (READ_WIDTH_A == 4) ? 4 : + (READ_WIDTH_A == 9) ? 8 : (READ_WIDTH_A == 18) ? 16 : (READ_WIDTH_A == 36) ? 32 : + (READ_WIDTH_A == 72) ? 64 : 64; + + localparam rb_width = (READ_WIDTH_B == 1) ? 1 : (READ_WIDTH_B == 2) ? 2 : (READ_WIDTH_B == 4) ? 4 : + (READ_WIDTH_B == 9) ? 8 : (READ_WIDTH_B == 18) ? 16 : (READ_WIDTH_B == 36) ? 32 : + (READ_WIDTH_B == 72) ? 64 : 64; + + + localparam ra_widthp = (READ_WIDTH_A == 9) ? 1 : (READ_WIDTH_A == 18) ? 2 : (READ_WIDTH_A == 36) ? 4 : + (READ_WIDTH_A == 72) ? 8 : 8; + + localparam rb_widthp = (READ_WIDTH_B == 9) ? 1 : (READ_WIDTH_B == 18) ? 2 : (READ_WIDTH_B == 36) ? 4 : + (READ_WIDTH_B == 72) ? 8 : 8; + + localparam col_addr_lsb = (widest_width == 1) ? 0 : (widest_width == 2) ? 1 : (widest_width == 4) ? 2 : + (widest_width == 9) ? 3 : (widest_width == 18) ? 4 : (widest_width == 36) ? 5 : + (widest_width == 72) ? 6 : 0; + + assign col_addra_reconstruct[15:0] = (WRITE_MODE_A == "READ_FIRST" || WRITE_MODE_B == "READ_FIRST") ? + ((BRAM_SIZE == 36) ? {1'b0,addra_in[14:8],2'b0,addra_in[5],4'b0,addra_in[0]} : + (BRAM_SIZE == 18) ? {2'b0,addra_in[13:7],2'b0,addra_in[4],4'b0} : addra_in) : addra_in; + + assign col_addrb_reconstruct[15:0] = (WRITE_MODE_A == "READ_FIRST" || WRITE_MODE_B == "READ_FIRST") ? + ((BRAM_SIZE == 36) ? {1'b0,addrb_in[14:8],2'b0,addrb_in[5],4'b0,addrb_in[0]} : + (BRAM_SIZE == 18) ? {2'b0,addrb_in[13:7],2'b0,addrb_in[4],4'b0} : addrb_in) : addrb_in; + + localparam width = (widest_width == 1) ? 1 : (widest_width == 2) ? 2 : (widest_width == 4) ? 4 : + (widest_width == 9) ? 8 : (widest_width == 18) ? 16 : (widest_width == 36) ? 32 : + (widest_width == 72) ? 64 : 64; + + localparam widthp = (widest_width == 9) ? 1 : (widest_width == 18) ? 2 : (widest_width == 36) ? 4 : + (widest_width == 72) ? 8 : 8; + + + localparam r_addra_lbit_124 = (READ_WIDTH_A == 1) ? 0 : (READ_WIDTH_A == 2) ? 1 : + (READ_WIDTH_A == 4) ? 2 : (READ_WIDTH_A == 9) ? 3 : + (READ_WIDTH_A == 18) ? 4 : (READ_WIDTH_A == 36) ? 5 : + (READ_WIDTH_A == 72) ? 6 : 10; + + localparam r_addrb_lbit_124 = (READ_WIDTH_B == 1) ? 0 : (READ_WIDTH_B == 2) ? 1 : + (READ_WIDTH_B == 4) ? 2 : (READ_WIDTH_B == 9) ? 3 : + (READ_WIDTH_B == 18) ? 4 : (READ_WIDTH_B == 36) ? 5 : + (READ_WIDTH_B == 72) ? 6 : 10; + + localparam addra_lbit_124 = (WRITE_WIDTH_A == 1) ? 0 : (WRITE_WIDTH_A == 2) ? 1 : + (WRITE_WIDTH_A == 4) ? 2 : (WRITE_WIDTH_A == 9) ? 3 : + (WRITE_WIDTH_A == 18) ? 4 : (WRITE_WIDTH_A == 36) ? 5 : + (WRITE_WIDTH_A == 72) ? 6 : 10; + + localparam addrb_lbit_124 = (WRITE_WIDTH_B == 1) ? 0 : (WRITE_WIDTH_B == 2) ? 1 : + (WRITE_WIDTH_B == 4) ? 2 : (WRITE_WIDTH_B == 9) ? 3 : + (WRITE_WIDTH_B == 18) ? 4 : (WRITE_WIDTH_B == 36) ? 5 : + (WRITE_WIDTH_B == 72) ? 6 : 10; + + localparam addra_bit_124 = (WRITE_WIDTH_A == 1 && widest_width == 2) ? 0 : (WRITE_WIDTH_A == 1 && widest_width == 4) ? 1 : + (WRITE_WIDTH_A == 1 && widest_width == 9) ? 2 : (WRITE_WIDTH_A == 1 && widest_width == 18) ? 3 : + (WRITE_WIDTH_A == 1 && widest_width == 36) ? 4 : (WRITE_WIDTH_A == 1 && widest_width == 72) ? 5 : + (WRITE_WIDTH_A == 2 && widest_width == 4) ? 1 : (WRITE_WIDTH_A == 2 && widest_width == 9) ? 2 : + (WRITE_WIDTH_A == 2 && widest_width == 18) ? 3 : (WRITE_WIDTH_A == 2 && widest_width == 36) ? 4 : + (WRITE_WIDTH_A == 2 && widest_width == 72) ? 5 : (WRITE_WIDTH_A == 4 && widest_width == 9) ? 2 : + (WRITE_WIDTH_A == 4 && widest_width == 18) ? 3 : (WRITE_WIDTH_A == 4 && widest_width == 36) ? 4 : + (WRITE_WIDTH_A == 4 && widest_width == 72) ? 5 : 10; + + localparam r_addra_bit_124 = (READ_WIDTH_A == 1 && widest_width == 2) ? 0 : (READ_WIDTH_A == 1 && widest_width == 4) ? 1 : + (READ_WIDTH_A == 1 && widest_width == 9) ? 2 : (READ_WIDTH_A == 1 && widest_width == 18) ? 3 : + (READ_WIDTH_A == 1 && widest_width == 36) ? 4 : (READ_WIDTH_A == 1 && widest_width == 72) ? 5 : + (READ_WIDTH_A == 2 && widest_width == 4) ? 1 : (READ_WIDTH_A == 2 && widest_width == 9) ? 2 : + (READ_WIDTH_A == 2 && widest_width == 18) ? 3 : (READ_WIDTH_A == 2 && widest_width == 36) ? 4 : + (READ_WIDTH_A == 2 && widest_width == 72) ? 5 : (READ_WIDTH_A == 4 && widest_width == 9) ? 2 : + (READ_WIDTH_A == 4 && widest_width == 18) ? 3 : (READ_WIDTH_A == 4 && widest_width == 36) ? 4 : + (READ_WIDTH_A == 4 && widest_width == 72) ? 5 : 10; + + localparam addrb_bit_124 = (WRITE_WIDTH_B == 1 && widest_width == 2) ? 0 : (WRITE_WIDTH_B == 1 && widest_width == 4) ? 1 : + (WRITE_WIDTH_B == 1 && widest_width == 9) ? 2 : (WRITE_WIDTH_B == 1 && widest_width == 18) ? 3 : + (WRITE_WIDTH_B == 1 && widest_width == 36) ? 4 : (WRITE_WIDTH_B == 1 && widest_width == 72) ? 5 : + (WRITE_WIDTH_B == 2 && widest_width == 4) ? 1 : (WRITE_WIDTH_B == 2 && widest_width == 9) ? 2 : + (WRITE_WIDTH_B == 2 && widest_width == 18) ? 3 : (WRITE_WIDTH_B == 2 && widest_width == 36) ? 4 : + (WRITE_WIDTH_B == 2 && widest_width == 72) ? 5 : (WRITE_WIDTH_B == 4 && widest_width == 9) ? 2 : + (WRITE_WIDTH_B == 4 && widest_width == 18) ? 3 : (WRITE_WIDTH_B == 4 && widest_width == 36) ? 4 : + (WRITE_WIDTH_B == 4 && widest_width == 72) ? 5 : 10; + + localparam r_addrb_bit_124 = (READ_WIDTH_B == 1 && widest_width == 2) ? 0 : (READ_WIDTH_B == 1 && widest_width == 4) ? 1 : + (READ_WIDTH_B == 1 && widest_width == 9) ? 2 : (READ_WIDTH_B == 1 && widest_width == 18) ? 3 : + (READ_WIDTH_B == 1 && widest_width == 36) ? 4 : (READ_WIDTH_B == 1 && widest_width == 72) ? 5 : + (READ_WIDTH_B == 2 && widest_width == 4) ? 1 : (READ_WIDTH_B == 2 && widest_width == 9) ? 2 : + (READ_WIDTH_B == 2 && widest_width == 18) ? 3 : (READ_WIDTH_B == 2 && widest_width == 36) ? 4 : + (READ_WIDTH_B == 2 && widest_width == 72) ? 5 : (READ_WIDTH_B == 4 && widest_width == 9) ? 2 : + (READ_WIDTH_B == 4 && widest_width == 18) ? 3 : (READ_WIDTH_B == 4 && widest_width == 36) ? 4 : + (READ_WIDTH_B == 4 && widest_width == 72) ? 5 : 10; + + localparam addra_bit_8 = (WRITE_WIDTH_A == 9 && widest_width == 18) ? 3 : (WRITE_WIDTH_A == 9 && widest_width == 36) ? 4 : + (WRITE_WIDTH_A == 9 && widest_width == 72) ? 5 : 10; + + localparam addra_bit_16 = (WRITE_WIDTH_A == 18 && widest_width == 36) ? 4 : (WRITE_WIDTH_A == 18 && widest_width == 72) ? 5 : 10; + + localparam r_addra_bit_8 = (READ_WIDTH_A == 9 && widest_width == 18) ? 3 : (READ_WIDTH_A == 9 && widest_width == 36) ? 4 : + (READ_WIDTH_A == 9 && widest_width == 72) ? 5 : 10; + + localparam r_addra_bit_16 = (READ_WIDTH_A == 18 && widest_width == 36) ? 4 : (READ_WIDTH_A == 18 && widest_width == 72) ? 5 : 10; + + localparam r_addra_bit_32 = (READ_WIDTH_A == 36 && widest_width == 72) ? 5 : 10; + + localparam addrb_bit_8 = (WRITE_WIDTH_B == 9 && widest_width == 18) ? 3 : (WRITE_WIDTH_B == 9 && widest_width == 36) ? 4 : + (WRITE_WIDTH_B == 9 && widest_width == 72) ? 5 : 10; + + localparam addrb_bit_16 = (WRITE_WIDTH_B == 18 && widest_width == 36) ? 4 : (WRITE_WIDTH_B == 18 && widest_width == 72) ? 5 : 10; + + localparam addrb_bit_32 = (WRITE_WIDTH_B == 36 && widest_width == 72) ? 5 : 10; + + localparam r_addrb_bit_8 = (READ_WIDTH_B == 9 && widest_width == 18) ? 3 : (READ_WIDTH_B == 9 && widest_width == 36) ? 4 : + (READ_WIDTH_B == 9 && widest_width == 72) ? 5 : 10; + + localparam r_addrb_bit_16 = (READ_WIDTH_B == 18 && widest_width == 36) ? 4 : (READ_WIDTH_B == 18 && widest_width == 72) ? 5 : 10; + + localparam r_addrb_bit_32 = (READ_WIDTH_B == 36 && widest_width == 72) ? 5 : 10; + + localparam mem_size1 = (BRAM_SIZE == 18) ? 16384 : (BRAM_SIZE == 36) ? 32768 : 32768; + localparam mem_size2 = (BRAM_SIZE == 18) ? 8192 : (BRAM_SIZE == 36) ? 16384 : 16384; + localparam mem_size4 = (BRAM_SIZE == 18) ? 4096 : (BRAM_SIZE == 36) ? 8192 : 8192; + localparam mem_size9 = (BRAM_SIZE == 18) ? 2048 : (BRAM_SIZE == 36) ? 4096 : 4096; + localparam mem_size18 = (BRAM_SIZE == 18) ? 1024 : (BRAM_SIZE == 36) ? 2048 : 2048; + localparam mem_size36 = (BRAM_SIZE == 18) ? 512 : (BRAM_SIZE == 36) ? 1024 : 1024; + localparam mem_size72 = (BRAM_SIZE == 18) ? 0 : (BRAM_SIZE == 36) ? 512 : 512; + + localparam mem_depth = (widest_width == 1) ? mem_size1 : (widest_width == 2) ? mem_size2 : (widest_width == 4) ? mem_size4 : + (widest_width == 9) ? mem_size9 :(widest_width == 18) ? mem_size18 : (widest_width == 36) ? mem_size36 : + (widest_width == 72) ? mem_size72 : 32768; + + localparam memp_depth = (widest_width == 9) ? mem_size9 :(widest_width == 18) ? mem_size18 : (widest_width == 36) ? mem_size36 : + (widest_width == 72) ? mem_size72 : 4096; + + reg [widest_width-1:0] tmp_mem [mem_depth-1:0]; + + reg [width-1:0] mem [mem_depth-1:0]; + reg [widthp-1:0] memp [memp_depth-1:0]; + + + +/******************************************** task and function **************************************/ + + task task_ram; + + input we; + input [7:0] di; + input dip; + inout [7:0] mem_task; + inout memp_task; + + begin + + if (we == 1'b1) begin + + mem_task = di; + + if (width >= 8) + memp_task = dip; + end + end + + endtask // task_ram + + + task task_ram_col; + + input we_o; + input we; + input [7:0] di; + input dip; + inout [7:0] mem_task; + inout memp_task; + integer i; + + begin + + if (we == 1'b1) begin + + for (i = 0; i < 8; i = i + 1) + if (mem_task[i] !== 1'bx || !(we === we_o && we === 1'b1)) + mem_task[i] = di[i]; + + if (width >= 8 && (memp_task !== 1'bx || !(we === we_o && we === 1'b1))) + memp_task = dip; + + end + end + + endtask // task_ram_col + + + task task_x_buf; + input [1:0] wr_rd_mode; + input integer do_uindex; + input integer do_lindex; + input integer dop_index; + input [63:0] do_ltmp; + inout [63:0] do_tmp; + input [7:0] dop_ltmp; + inout [7:0] dop_tmp; + integer i; + + begin + + if (wr_rd_mode == 2'b01) begin + for (i = do_lindex; i <= do_uindex; i = i + 1) begin + if (do_ltmp[i] === 1'bx) + do_tmp[i] = 1'bx; + end + + if (dop_ltmp[dop_index] === 1'bx) + dop_tmp[dop_index] = 1'bx; + + end // if (wr_rd_mode == 2'b01) + else begin + do_tmp[do_lindex +: 8] = do_ltmp[do_lindex +: 8]; + dop_tmp[dop_index] = dop_ltmp[dop_index]; + + end // else: !if(wr_rd_mode == 2'b01) + end + + endtask // task_x_buf + + + task task_col_wr_ram_a; + + input [1:0] seq; + input [7:0] web_tmp; + input [7:0] wea_tmp; + input [63:0] dia_tmp; + input [7:0] dipa_tmp; + input [15:0] addrb_tmp; + input [15:0] addra_tmp; + + begin + + case (wa_width) + + 1, 2, 4 : begin + if (!(wea_tmp[0] === 1'b1 && web_tmp[0] === 1'b1 && wa_width > wb_width) || seq == 2'b10) begin + if (wa_width >= width) + task_ram_col (web_tmp[0], wea_tmp[0], dia_tmp[wa_width-1:0], 1'b0, mem[addra_tmp[14:addra_lbit_124]], junk1); + else + task_ram_col (web_tmp[0], wea_tmp[0], dia_tmp[wa_width-1:0], 1'b0, mem[addra_tmp[14:addra_bit_124+1]][(addra_tmp[addra_bit_124:addra_lbit_124] * wa_width) +: wa_width], junk1); + + if (seq == 2'b00) + chk_for_col_msg (wea_tmp[0], web_tmp[0], addra_tmp, addrb_tmp); + + end // if (!(wea_tmp[0] === 1'b1 && web_tmp[0] === 1'b1 && wa_width > wb_width) || seq == 2'b10) + end // case: 1, 2, 4 + 8 : begin + if (!(wea_tmp[0] === 1'b1 && web_tmp[0] === 1'b1 && wa_width > wb_width) || seq == 2'b10) begin + if (wa_width >= width) + task_ram_col (web_tmp[0], wea_tmp[0], dia_tmp[7:0], dipa_tmp[0], mem[addra_tmp[14:3]], memp[addra_tmp[14:3]]); + else + task_ram_col (web_tmp[0], wea_tmp[0], dia_tmp[7:0], dipa_tmp[0], mem[addra_tmp[14:addra_bit_8+1]][(addra_tmp[addra_bit_8:3] * 8) +: 8], memp[addra_tmp[14:addra_bit_8+1]][(addra_tmp[addra_bit_8:3] * 1) +: 1]); + + if (seq == 2'b00) + chk_for_col_msg (wea_tmp[0], web_tmp[0], addra_tmp, addrb_tmp); + + end // if (wa_width <= wb_width) + end // case: 8 + 16 : begin + if (!(wea_tmp[0] === 1'b1 && web_tmp[0] === 1'b1 && wa_width > wb_width) || seq == 2'b10) begin + if (wa_width >= width) + task_ram_col (web_tmp[0], wea_tmp[0], dia_tmp[7:0], dipa_tmp[0], mem[addra_tmp[14:4]][0 +: 8], memp[addra_tmp[14:4]][0]); + else + task_ram_col (web_tmp[0], wea_tmp[0], dia_tmp[7:0], dipa_tmp[0], mem[addra_tmp[14:addra_bit_16+1]][(addra_tmp[addra_bit_16:4] * 16) +: 8], memp[addra_tmp[14:addra_bit_16+1]][(addra_tmp[addra_bit_16:4] * 2) +: 1]); + + if (seq == 2'b00) + chk_for_col_msg (wea_tmp[0], web_tmp[0], addra_tmp, addrb_tmp); + + if (wa_width >= width) + task_ram_col (web_tmp[1], wea_tmp[1], dia_tmp[15:8], dipa_tmp[1], mem[addra_tmp[14:4]][8 +: 8], memp[addra_tmp[14:4]][1]); + else + task_ram_col (web_tmp[1], wea_tmp[1], dia_tmp[15:8], dipa_tmp[1], mem[addra_tmp[14:addra_bit_16+1]][((addra_tmp[addra_bit_16:4] * 16) + 8) +: 8], memp[addra_tmp[14:addra_bit_16+1]][((addra_tmp[addra_bit_16:4] * 2) + 1) +: 1]); + + if (seq == 2'b00) + chk_for_col_msg (wea_tmp[1], web_tmp[1], addra_tmp, addrb_tmp); + + end // if (wa_width <= wb_width) + end // case: 16 + 32 : begin + if (!(wea_tmp[0] === 1'b1 && web_tmp[0] === 1'b1 && wa_width > wb_width) || seq == 2'b10) begin + task_ram_col (web_tmp[0], wea_tmp[0], dia_tmp[7:0], dipa_tmp[0], mem[addra_tmp[14:5]][0 +: 8], memp[addra_tmp[14:5]][0]); + if (seq == 2'b00) + chk_for_col_msg (wea_tmp[0], web_tmp[0], addra_tmp, addrb_tmp); + + task_ram_col (web_tmp[1], wea_tmp[1], dia_tmp[15:8], dipa_tmp[1], mem[addra_tmp[14:5]][8 +: 8], memp[addra_tmp[14:5]][1]); + if (seq == 2'b00) + chk_for_col_msg (wea_tmp[1], web_tmp[1], addra_tmp, addrb_tmp); + + task_ram_col (web_tmp[2], wea_tmp[2], dia_tmp[23:16], dipa_tmp[2], mem[addra_tmp[14:5]][16 +: 8], memp[addra_tmp[14:5]][2]); + if (seq == 2'b00) + chk_for_col_msg (wea_tmp[2], web_tmp[2], addra_tmp, addrb_tmp); + + task_ram_col (web_tmp[3], wea_tmp[3], dia_tmp[31:24], dipa_tmp[3], mem[addra_tmp[14:5]][24 +: 8], memp[addra_tmp[14:5]][3]); + if (seq == 2'b00) + chk_for_col_msg (wea_tmp[3], web_tmp[3], addra_tmp, addrb_tmp); + + end // if (wa_width <= wb_width) + end // case: 32 + 64 : ; + + endcase // case(wa_width) + + end + + endtask // task_col_wr_ram_a + + + task task_col_wr_ram_b; + + input [1:0] seq; + input [7:0] wea_tmp; + input [7:0] web_tmp; + input [63:0] dib_tmp; + input [7:0] dipb_tmp; + input [15:0] addra_tmp; + input [15:0] addrb_tmp; + + begin + + case (wb_width) + + 1, 2, 4 : begin + if (!(wea_tmp[0] === 1'b1 && web_tmp[0] === 1'b1 && wb_width > wa_width) || seq == 2'b10) begin + if (wb_width >= width) + task_ram_col (wea_tmp[0], web_tmp[0], dib_tmp[wb_width-1:0], 1'b0, mem[addrb_tmp[14:addrb_lbit_124]], junk1); + else + task_ram_col (wea_tmp[0], web_tmp[0], dib_tmp[wb_width-1:0], 1'b0, mem[addrb_tmp[14:addrb_bit_124+1]][(addrb_tmp[addrb_bit_124:addrb_lbit_124] * wb_width) +: wb_width], junk1); + + if (seq == 2'b00) + chk_for_col_msg (wea_tmp[0], web_tmp[0], addra_tmp, addrb_tmp); + + end // if (wb_width <= wa_width) + end // case: 1, 2, 4 + 8 : begin + if (!(wea_tmp[0] === 1'b1 && web_tmp[0] === 1'b1 && wb_width > wa_width) || seq == 2'b10) begin + if (wb_width >= width) + task_ram_col (wea_tmp[0], web_tmp[0], dib_tmp[7:0], dipb_tmp[0], mem[addrb_tmp[14:3]], memp[addrb_tmp[14:3]]); + else + task_ram_col (wea_tmp[0], web_tmp[0], dib_tmp[7:0], dipb_tmp[0], mem[addrb_tmp[14:addrb_bit_8+1]][(addrb_tmp[addrb_bit_8:3] * 8) +: 8], memp[addrb_tmp[14:addrb_bit_8+1]][(addrb_tmp[addrb_bit_8:3] * 1) +: 1]); + + if (seq == 2'b00) + chk_for_col_msg (wea_tmp[0], web_tmp[0], addra_tmp, addrb_tmp); + + end // if (wb_width <= wa_width) + end // case: 8 + 16 : begin + if (!(wea_tmp[0] === 1'b1 && web_tmp[0] === 1'b1 && wb_width > wa_width) || seq == 2'b10) begin + if (wb_width >= width) + task_ram_col (wea_tmp[0], web_tmp[0], dib_tmp[7:0], dipb_tmp[0], mem[addrb_tmp[14:4]][0 +: 8], memp[addrb_tmp[14:4]][0:0]); + else + task_ram_col (wea_tmp[0], web_tmp[0], dib_tmp[7:0], dipb_tmp[0], mem[addrb_tmp[14:addrb_bit_16+1]][(addrb_tmp[addrb_bit_16:4] * 16) +: 8], memp[addrb_tmp[14:addrb_bit_16+1]][(addrb_tmp[addrb_bit_16:4] * 2) +: 1]); + + if (seq == 2'b00) + chk_for_col_msg (wea_tmp[0], web_tmp[0], addra_tmp, addrb_tmp); + + + if (wb_width >= width) + task_ram_col (wea_tmp[1], web_tmp[1], dib_tmp[15:8], dipb_tmp[1], mem[addrb_tmp[14:4]][8 +: 8], memp[addrb_tmp[14:4]][1:1]); + else + task_ram_col (wea_tmp[1], web_tmp[1], dib_tmp[15:8], dipb_tmp[1], mem[addrb_tmp[14:addrb_bit_16+1]][((addrb_tmp[addrb_bit_16:4] * 16) + 8) +: 8], memp[addrb_tmp[14:addrb_bit_16+1]][((addrb_tmp[addrb_bit_16:4] * 2) + 1) +: 1]); + + if (seq == 2'b00) + chk_for_col_msg (wea_tmp[1], web_tmp[1], addra_tmp, addrb_tmp); + + end // if (!(wea_tmp[0] === 1'b1 && web_tmp[0] === 1'b1 && wb_width > wa_width) || seq == 2'b10) + end // case: 16 + 32 : begin + if (!(wea_tmp[0] === 1'b1 && web_tmp[0] === 1'b1 && wb_width > wa_width) || seq == 2'b10) begin + task_ram_col (wea_tmp[0], web_tmp[0], dib_tmp[7:0], dipb_tmp[0], mem[addrb_tmp[14:5]][0 +: 8], memp[addrb_tmp[14:5]][0:0]); + if (seq == 2'b00) + chk_for_col_msg (wea_tmp[0], web_tmp[0], addra_tmp, addrb_tmp); + + task_ram_col (wea_tmp[1], web_tmp[1], dib_tmp[15:8], dipb_tmp[1], mem[addrb_tmp[14:5]][8 +: 8], memp[addrb_tmp[14:5]][1:1]); + if (seq == 2'b00) + chk_for_col_msg (wea_tmp[1], web_tmp[1], addra_tmp, addrb_tmp); + + task_ram_col (wea_tmp[2], web_tmp[2], dib_tmp[23:16], dipb_tmp[2], mem[addrb_tmp[14:5]][16 +: 8], memp[addrb_tmp[14:5]][2:2]); + if (seq == 2'b00) + chk_for_col_msg (wea_tmp[2], web_tmp[2], addra_tmp, addrb_tmp); + + task_ram_col (wea_tmp[3], web_tmp[3], dib_tmp[31:24], dipb_tmp[3], mem[addrb_tmp[14:5]][24 +: 8], memp[addrb_tmp[14:5]][3:3]); + if (seq == 2'b00) + chk_for_col_msg (wea_tmp[3], web_tmp[3], addra_tmp, addrb_tmp); + + end // if (wb_width <= wa_width) + end // case: 32 + 64 : begin + + task_ram_col (wea_tmp[0], web_tmp[0], dib_tmp[7:0], dipb_tmp[0], mem[addrb_tmp[14:6]][0 +: 8], memp[addrb_tmp[14:6]][0:0]); + if (seq == 2'b00) + chk_for_col_msg (wea_tmp[0], web_tmp[0], addra_tmp, addrb_tmp); + + task_ram_col (wea_tmp[1], web_tmp[1], dib_tmp[15:8], dipb_tmp[1], mem[addrb_tmp[14:6]][8 +: 8], memp[addrb_tmp[14:6]][1:1]); + if (seq == 2'b00) + chk_for_col_msg (wea_tmp[1], web_tmp[1], addra_tmp, addrb_tmp); + + task_ram_col (wea_tmp[2], web_tmp[2], dib_tmp[23:16], dipb_tmp[2], mem[addrb_tmp[14:6]][16 +: 8], memp[addrb_tmp[14:6]][2:2]); + if (seq == 2'b00) + chk_for_col_msg (wea_tmp[2], web_tmp[2], addra_tmp, addrb_tmp); + + task_ram_col (wea_tmp[3], web_tmp[3], dib_tmp[31:24], dipb_tmp[3], mem[addrb_tmp[14:6]][24 +: 8], memp[addrb_tmp[14:6]][3:3]); + if (seq == 2'b00) + chk_for_col_msg (wea_tmp[3], web_tmp[3], addra_tmp, addrb_tmp); + + task_ram_col (wea_tmp[4], web_tmp[4], dib_tmp[39:32], dipb_tmp[4], mem[addrb_tmp[14:6]][32 +: 8], memp[addrb_tmp[14:6]][4:4]); + if (seq == 2'b00) + chk_for_col_msg (wea_tmp[4], web_tmp[4], addra_tmp, addrb_tmp); + + task_ram_col (wea_tmp[5], web_tmp[5], dib_tmp[47:40], dipb_tmp[5], mem[addrb_tmp[14:6]][40 +: 8], memp[addrb_tmp[14:6]][5:5]); + if (seq == 2'b00) + chk_for_col_msg (wea_tmp[5], web_tmp[5], addra_tmp, addrb_tmp); + + task_ram_col (wea_tmp[6], web_tmp[6], dib_tmp[55:48], dipb_tmp[6], mem[addrb_tmp[14:6]][48 +: 8], memp[addrb_tmp[14:6]][6:6]); + if (seq == 2'b00) + chk_for_col_msg (wea_tmp[6], web_tmp[6], addra_tmp, addrb_tmp); + + task_ram_col (wea_tmp[7], web_tmp[7], dib_tmp[63:56], dipb_tmp[7], mem[addrb_tmp[14:6]][56 +: 8], memp[addrb_tmp[14:6]][7:7]); + if (seq == 2'b00) + chk_for_col_msg (wea_tmp[7], web_tmp[7], addra_tmp, addrb_tmp); + + end // case: 64 + + endcase // case(wb_width) + + end + + endtask // task_col_wr_ram_b + + + task task_wr_ram_a; + + input [7:0] wea_tmp; + input [63:0] dia_tmp; + input [7:0] dipa_tmp; + input [15:0] addra_tmp; + + begin + + case (wa_width) + + 1, 2, 4 : begin + + if (wa_width >= width) + task_ram (wea_tmp[0], dia_tmp[wa_width-1:0], 1'b0, mem[addra_tmp[14:addra_lbit_124]], junk1); + else + task_ram (wea_tmp[0], dia_tmp[wa_width-1:0], 1'b0, mem[addra_tmp[14:addra_bit_124+1]][(addra_tmp[addra_bit_124:addra_lbit_124] * wa_width) +: wa_width], junk1); + + end + 8 : begin + + if (wa_width >= width) + task_ram (wea_tmp[0], dia_tmp[7:0], dipa_tmp[0], mem[addra_tmp[14:3]], memp[addra_tmp[14:3]]); + else + task_ram (wea_tmp[0], dia_tmp[7:0], dipa_tmp[0], mem[addra_tmp[14:addra_bit_8+1]][(addra_tmp[addra_bit_8:3] * 8) +: 8], memp[addra_tmp[14:addra_bit_8+1]][(addra_tmp[addra_bit_8:3] * 1) +: 1]); + + end + 16 : begin + + if (wa_width >= width) begin + task_ram (wea_tmp[0], dia_tmp[7:0], dipa_tmp[0], mem[addra_tmp[14:4]][0 +: 8], memp[addra_tmp[14:4]][0:0]); + task_ram (wea_tmp[1], dia_tmp[15:8], dipa_tmp[1], mem[addra_tmp[14:4]][8 +: 8], memp[addra_tmp[14:4]][1:1]); + end + else begin + task_ram (wea_tmp[0], dia_tmp[7:0], dipa_tmp[0], mem[addra_tmp[14:addra_bit_16+1]][(addra_tmp[addra_bit_16:4] * 16) +: 8], memp[addra_tmp[14:addra_bit_16+1]][(addra_tmp[addra_bit_16:4] * 2) +: 1]); + task_ram (wea_tmp[1], dia_tmp[15:8], dipa_tmp[1], mem[addra_tmp[14:addra_bit_16+1]][((addra_tmp[addra_bit_16:4] * 16) + 8) +: 8], memp[addra_tmp[14:addra_bit_16+1]][((addra_tmp[addra_bit_16:4] * 2) + 1) +: 1]); + end // else: !if(wa_width >= wb_width) + + end // case: 16 + 32 : begin + + task_ram (wea_tmp[0], dia_tmp[7:0], dipa_tmp[0], mem[addra_tmp[14:5]][0 +: 8], memp[addra_tmp[14:5]][0:0]); + task_ram (wea_tmp[1], dia_tmp[15:8], dipa_tmp[1], mem[addra_tmp[14:5]][8 +: 8], memp[addra_tmp[14:5]][1:1]); + task_ram (wea_tmp[2], dia_tmp[23:16], dipa_tmp[2], mem[addra_tmp[14:5]][16 +: 8], memp[addra_tmp[14:5]][2:2]); + task_ram (wea_tmp[3], dia_tmp[31:24], dipa_tmp[3], mem[addra_tmp[14:5]][24 +: 8], memp[addra_tmp[14:5]][3:3]); + + end // case: 32 + endcase // case(wa_width) + end + + endtask // task_wr_ram_a + + + task task_wr_ram_b; + + input [7:0] web_tmp; + input [63:0] dib_tmp; + input [7:0] dipb_tmp; + input [15:0] addrb_tmp; + + begin + + case (wb_width) + + 1, 2, 4 : begin + + if (wb_width >= width) + task_ram (web_tmp[0], dib_tmp[wb_width-1:0], 1'b0, mem[addrb_tmp[14:addrb_lbit_124]], junk1); + else + task_ram (web_tmp[0], dib_tmp[wb_width-1:0], 1'b0, mem[addrb_tmp[14:addrb_bit_124+1]][(addrb_tmp[addrb_bit_124:addrb_lbit_124] * wb_width) +: wb_width], junk1); + end + 8 : begin + + if (wb_width >= width) + task_ram (web_tmp[0], dib_tmp[7:0], dipb_tmp[0], mem[addrb_tmp[14:3]], memp[addrb_tmp[14:3]]); + else + task_ram (web_tmp[0], dib_tmp[7:0], dipb_tmp[0], mem[addrb_tmp[14:addrb_bit_8+1]][(addrb_tmp[addrb_bit_8:3] * 8) +: 8], memp[addrb_tmp[14:addrb_bit_8+1]][(addrb_tmp[addrb_bit_8:3] * 1) +: 1]); + + end + 16 : begin + + if (wb_width >= width) begin + task_ram (web_tmp[0], dib_tmp[7:0], dipb_tmp[0], mem[addrb_tmp[14:4]][0 +: 8], memp[addrb_tmp[14:4]][0:0]); + task_ram (web_tmp[1], dib_tmp[15:8], dipb_tmp[1], mem[addrb_tmp[14:4]][8 +: 8], memp[addrb_tmp[14:4]][1:1]); + end + else begin + task_ram (web_tmp[0], dib_tmp[7:0], dipb_tmp[0], mem[addrb_tmp[14:addrb_bit_16+1]][(addrb_tmp[addrb_bit_16:4] * 16) +: 8], memp[addrb_tmp[14:addrb_bit_16+1]][(addrb_tmp[addrb_bit_16:4] * 2) +: 1]); + task_ram (web_tmp[1], dib_tmp[15:8], dipb_tmp[1], mem[addrb_tmp[14:addrb_bit_16+1]][((addrb_tmp[addrb_bit_16:4] * 16) + 8) +: 8], memp[addrb_tmp[14:addrb_bit_16+1]][((addrb_tmp[addrb_bit_16:4] * 2) + 1) +: 1]); + end + + end // case: 16 + 32 : begin + + if (wb_width >= width) begin + task_ram (web_tmp[0], dib_tmp[7:0], dipb_tmp[0], mem[addrb_tmp[14:5]][0 +: 8], memp[addrb_tmp[14:5]][0:0]); + task_ram (web_tmp[1], dib_tmp[15:8], dipb_tmp[1], mem[addrb_tmp[14:5]][8 +: 8], memp[addrb_tmp[14:5]][1:1]); + task_ram (web_tmp[2], dib_tmp[23:16], dipb_tmp[2], mem[addrb_tmp[14:5]][16 +: 8], memp[addrb_tmp[14:5]][2:2]); + task_ram (web_tmp[3], dib_tmp[31:24], dipb_tmp[3], mem[addrb_tmp[14:5]][24 +: 8], memp[addrb_tmp[14:5]][3:3]); + end + else begin + task_ram (web_tmp[0], dib_tmp[7:0], dipb_tmp[0], mem[addrb_tmp[14:addrb_bit_32+1]][(addrb_tmp[addrb_bit_32:5] * 32) +: 8], memp[addrb_tmp[14:addrb_bit_32+1]][(addrb_tmp[addrb_bit_32:5] * 4) +: 1]); + task_ram (web_tmp[1], dib_tmp[15:8], dipb_tmp[1], mem[addrb_tmp[14:addrb_bit_32+1]][((addrb_tmp[addrb_bit_32:5] * 32) + 8) +: 8], memp[addrb_tmp[14:addrb_bit_32+1]][((addrb_tmp[addrb_bit_32:5] * 4) + 1) +: 1]); + task_ram (web_tmp[2], dib_tmp[23:16], dipb_tmp[2], mem[addrb_tmp[14:addrb_bit_32+1]][((addrb_tmp[addrb_bit_32:5] * 32) + 16) +: 8], memp[addrb_tmp[14:addrb_bit_32+1]][((addrb_tmp[addrb_bit_32:5] * 4) + 2) +: 1]); + task_ram (web_tmp[3], dib_tmp[31:24], dipb_tmp[3], mem[addrb_tmp[14:addrb_bit_32+1]][((addrb_tmp[addrb_bit_32:5] * 32) + 24) +: 8], memp[addrb_tmp[14:addrb_bit_32+1]][((addrb_tmp[addrb_bit_32:5] * 4) + 3) +: 1]); + end // else: !if(wb_width >= width) + + end // case: 32 + 64 : begin // only valid with ECC single bit correction for 64 bits + + task_ram (web_tmp[0], dib_tmp[7:0], dipb_tmp[0], mem[addrb_tmp[14:6]][0 +: 8], memp[addrb_tmp[14:6]][0:0]); + task_ram (web_tmp[1], dib_tmp[15:8], dipb_tmp[1], mem[addrb_tmp[14:6]][8 +: 8], memp[addrb_tmp[14:6]][1:1]); + task_ram (web_tmp[2], dib_tmp[23:16], dipb_tmp[2], mem[addrb_tmp[14:6]][16 +: 8], memp[addrb_tmp[14:6]][2:2]); + task_ram (web_tmp[3], dib_tmp[31:24], dipb_tmp[3], mem[addrb_tmp[14:6]][24 +: 8], memp[addrb_tmp[14:6]][3:3]); + task_ram (web_tmp[4], dib_tmp[39:32], dipb_tmp[4], mem[addrb_tmp[14:6]][32 +: 8], memp[addrb_tmp[14:6]][4:4]); + task_ram (web_tmp[5], dib_tmp[47:40], dipb_tmp[5], mem[addrb_tmp[14:6]][40 +: 8], memp[addrb_tmp[14:6]][5:5]); + task_ram (web_tmp[6], dib_tmp[55:48], dipb_tmp[6], mem[addrb_tmp[14:6]][48 +: 8], memp[addrb_tmp[14:6]][6:6]); + task_ram (web_tmp[7], dib_tmp[63:56], dipb_tmp[7], mem[addrb_tmp[14:6]][56 +: 8], memp[addrb_tmp[14:6]][7:7]); + + end // case: 64 + endcase // case(wb_width) + end + + endtask // task_wr_ram_b + + + task task_col_rd_ram_a; + + input [1:0] seq; // 1 is bypass + input [7:0] web_tmp; + input [7:0] wea_tmp; + input [15:0] addra_tmp; + inout [63:0] doa_tmp; + inout [7:0] dopa_tmp; + reg [63:0] doa_ltmp; + reg [7:0] dopa_ltmp; + + begin + + doa_ltmp= 64'b0; + dopa_ltmp= 8'b0; + + case (ra_width) + 1, 2, 4 : begin + + if ((web_tmp[0] === 1'b1 && wea_tmp[0] === 1'b1) || (seq == 2'b01 && web_tmp[0] === 1'b1 && wea_tmp[0] === 1'b0 && viol_type == 2'b10) || (seq == 2'b01 && wr_mode_a != 2'b01 && wr_mode_b != 2'b01) || (seq == 2'b01 && wr_mode_a == 2'b01 && wr_mode_b != 2'b01 && web_tmp[0] === 1'b1) || (seq == 2'b11 && wr_mode_a == 2'b00 && web_tmp[0] !== 1'b1)) begin + if (ra_width >= width) + doa_ltmp = mem[addra_tmp[14:r_addra_lbit_124]]; + else + doa_ltmp = mem[addra_tmp[14:r_addra_bit_124+1]][(addra_tmp[r_addra_bit_124:r_addra_lbit_124] * ra_width) +: ra_width]; + task_x_buf (wr_mode_a, 3, 0, 0, doa_ltmp, doa_tmp, dopa_ltmp, dopa_tmp); + end + end // case: 1, 2, 4 + 8 : begin + + if ((web_tmp[0] === 1'b1 && wea_tmp[0] === 1'b1) || (seq == 2'b01 && web_tmp[0] === 1'b1 && wea_tmp[0] === 1'b0 && viol_type == 2'b10) || (seq == 2'b01 && wr_mode_a != 2'b01 && wr_mode_b != 2'b01) || (seq == 2'b01 && wr_mode_a == 2'b01 && wr_mode_b != 2'b01 && web_tmp[0] === 1'b1) || (seq == 2'b11 && wr_mode_a == 2'b00 && web_tmp[0] !== 1'b1)) begin + if (ra_width >= width) begin + doa_ltmp = mem[addra_tmp[14:3]]; + dopa_ltmp = memp[addra_tmp[14:3]]; + end + else begin + doa_ltmp = mem[addra_tmp[14:r_addra_bit_8+1]][(addra_tmp[r_addra_bit_8:3] * 8) +: 8]; + dopa_ltmp = memp[addra_tmp[14:r_addra_bit_8+1]][(addra_tmp[r_addra_bit_8:3] * 1) +: 1]; + end + + task_x_buf (wr_mode_a, 7, 0, 0, doa_ltmp, doa_tmp, dopa_ltmp, dopa_tmp); + + end + end // case: 8 + 16 : begin + + if ((web_tmp[0] === 1'b1 && wea_tmp[0] === 1'b1) || (seq == 2'b01 && web_tmp[0] === 1'b1 && wea_tmp[0] === 1'b0 && viol_type == 2'b10) || (seq == 2'b01 && wr_mode_a != 2'b01 && wr_mode_b != 2'b01) || (seq == 2'b01 && wr_mode_a == 2'b01 && wr_mode_b != 2'b01 && web_tmp[0] === 1'b1) || (seq == 2'b11 && wr_mode_a == 2'b00 && web_tmp[0] !== 1'b1)) begin + if (ra_width >= width) begin + doa_ltmp[7:0] = mem[addra_tmp[14:4]][7:0]; + dopa_ltmp[0:0] = memp[addra_tmp[14:4]][0:0]; + end + else begin + doa_ltmp[7:0] = mem[addra_tmp[14:r_addra_bit_16+1]][(addra_tmp[r_addra_bit_16:4] * 16) +: 8]; + dopa_ltmp[0:0] = memp[addra_tmp[14:r_addra_bit_16+1]][(addra_tmp[r_addra_bit_16:4] * 2) +: 1]; + end + task_x_buf (wr_mode_a, 7, 0, 0, doa_ltmp, doa_tmp, dopa_ltmp, dopa_tmp); + end + + if ((web_tmp[1] === 1'b1 && wea_tmp[1] === 1'b1) || (seq == 2'b01 && web_tmp[1] === 1'b1 && wea_tmp[1] === 1'b0 && viol_type == 2'b10) || (seq == 2'b01 && wr_mode_a != 2'b01 && wr_mode_b != 2'b01) || (seq == 2'b01 && wr_mode_a == 2'b01 && wr_mode_b != 2'b01 && web_tmp[1] === 1'b1) || (seq == 2'b11 && wr_mode_a == 2'b00 && web_tmp[1] !== 1'b1)) begin + if (ra_width >= width) begin + doa_ltmp[15:8] = mem[addra_tmp[14:4]][15:8]; + dopa_ltmp[1:1] = memp[addra_tmp[14:4]][1:1]; + end + else begin + doa_ltmp[15:8] = mem[addra_tmp[14:r_addra_bit_16+1]][((addra_tmp[r_addra_bit_16:4] * 16) + 8) +: 8]; + dopa_ltmp[1:1] = memp[addra_tmp[14:r_addra_bit_16+1]][((addra_tmp[r_addra_bit_16:4] * 2) + 1) +: 1]; + end + task_x_buf (wr_mode_a, 15, 8, 1, doa_ltmp, doa_tmp, dopa_ltmp, dopa_tmp); + end + + end + 32 : begin + if (ra_width >= width) begin + + if ((web_tmp[0] === 1'b1 && wea_tmp[0] === 1'b1) || (seq == 2'b01 && web_tmp[0] === 1'b1 && wea_tmp[0] === 1'b0 && viol_type == 2'b10) || (seq == 2'b01 && wr_mode_a != 2'b01 && wr_mode_b != 2'b01) || (seq == 2'b01 && wr_mode_a == 2'b01 && wr_mode_b != 2'b01 && web_tmp[0] === 1'b1) || (seq == 2'b11 && wr_mode_a == 2'b00 && web_tmp[0] !== 1'b1)) begin + doa_ltmp[7:0] = mem[addra_tmp[14:5]][7:0]; + dopa_ltmp[0:0] = memp[addra_tmp[14:5]][0:0]; + task_x_buf (wr_mode_a, 7, 0, 0, doa_ltmp, doa_tmp, dopa_ltmp, dopa_tmp); + end + + if ((web_tmp[1] === 1'b1 && wea_tmp[1] === 1'b1) || (seq == 2'b01 && web_tmp[1] === 1'b1 && wea_tmp[1] === 1'b0 && viol_type == 2'b10) || (seq == 2'b01 && wr_mode_a != 2'b01 && wr_mode_b != 2'b01) || (seq == 2'b01 && wr_mode_a == 2'b01 && wr_mode_b != 2'b01 && web_tmp[1] === 1'b1) || (seq == 2'b11 && wr_mode_a == 2'b00 && web_tmp[1] !== 1'b1)) begin + doa_ltmp[15:8] = mem[addra_tmp[14:5]][15:8]; + dopa_ltmp[1:1] = memp[addra_tmp[14:5]][1:1]; + task_x_buf (wr_mode_a, 15, 8, 1, doa_ltmp, doa_tmp, dopa_ltmp, dopa_tmp); + end + + if ((web_tmp[2] === 1'b1 && wea_tmp[2] === 1'b1) || (seq == 2'b01 && web_tmp[2] === 1'b1 && wea_tmp[2] === 1'b0 && viol_type == 2'b10) || (seq == 2'b01 && wr_mode_a != 2'b01 && wr_mode_b != 2'b01) || (seq == 2'b01 && wr_mode_a == 2'b01 && wr_mode_b != 2'b01 && web_tmp[2] === 1'b1) || (seq == 2'b11 && wr_mode_a == 2'b00 && web_tmp[2] !== 1'b1)) begin + doa_ltmp[23:16] = mem[addra_tmp[14:5]][23:16]; + dopa_ltmp[2:2] = memp[addra_tmp[14:5]][2:2]; + task_x_buf (wr_mode_a, 23, 16, 2, doa_ltmp, doa_tmp, dopa_ltmp, dopa_tmp); + end + + if ((web_tmp[3] === 1'b1 && wea_tmp[3] === 1'b1) || (seq == 2'b01 && web_tmp[3] === 1'b1 && wea_tmp[3] === 1'b0 && viol_type == 2'b10) || (seq == 2'b01 && wr_mode_a != 2'b01 && wr_mode_b != 2'b01) || (seq == 2'b01 && wr_mode_a == 2'b01 && wr_mode_b != 2'b01 && web_tmp[3] === 1'b1) || (seq == 2'b11 && wr_mode_a == 2'b00 && web_tmp[3] !== 1'b1)) begin + doa_ltmp[31:24] = mem[addra_tmp[14:5]][31:24]; + dopa_ltmp[3:3] = memp[addra_tmp[14:5]][3:3]; + task_x_buf (wr_mode_a, 31, 24, 3, doa_ltmp, doa_tmp, dopa_ltmp, dopa_tmp); + end + + end // if (ra_width >= width) + end + 64 : begin + + if ((web_tmp[0] === 1'b1 && wea_tmp[0] === 1'b1) || (seq == 2'b01 && web_tmp[0] === 1'b1 && wea_tmp[0] === 1'b0 && viol_type == 2'b10) || (seq == 2'b01 && wr_mode_a != 2'b01 && wr_mode_b != 2'b01) || (seq == 2'b01 && wr_mode_a == 2'b01 && wr_mode_b != 2'b01 && web_tmp[0] === 1'b1) || (seq == 2'b11 && wr_mode_a == 2'b00 && web_tmp[0] !== 1'b1)) begin + doa_ltmp[7:0] = mem[addra_tmp[14:6]][7:0]; + dopa_ltmp[0:0] = memp[addra_tmp[14:6]][0:0]; + task_x_buf (wr_mode_a, 7, 0, 0, doa_ltmp, doa_tmp, dopa_ltmp, dopa_tmp); + end + + if ((web_tmp[1] === 1'b1 && wea_tmp[1] === 1'b1) || (seq == 2'b01 && web_tmp[1] === 1'b1 && wea_tmp[1] === 1'b0 && viol_type == 2'b10) || (seq == 2'b01 && wr_mode_a != 2'b01 && wr_mode_b != 2'b01) || (seq == 2'b01 && wr_mode_a == 2'b01 && wr_mode_b != 2'b01 && web_tmp[1] === 1'b1) || (seq == 2'b11 && wr_mode_a == 2'b00 && web_tmp[1] !== 1'b1)) begin + doa_ltmp[15:8] = mem[addra_tmp[14:6]][15:8]; + dopa_ltmp[1:1] = memp[addra_tmp[14:6]][1:1]; + task_x_buf (wr_mode_a, 15, 8, 1, doa_ltmp, doa_tmp, dopa_ltmp, dopa_tmp); + end + + if ((web_tmp[2] === 1'b1 && wea_tmp[2] === 1'b1) || (seq == 2'b01 && web_tmp[2] === 1'b1 && wea_tmp[2] === 1'b0 && viol_type == 2'b10) || (seq == 2'b01 && wr_mode_a != 2'b01 && wr_mode_b != 2'b01) || (seq == 2'b01 && wr_mode_a == 2'b01 && wr_mode_b != 2'b01 && web_tmp[2] === 1'b1) || (seq == 2'b11 && wr_mode_a == 2'b00 && web_tmp[2] !== 1'b1)) begin + doa_ltmp[23:16] = mem[addra_tmp[14:6]][23:16]; + dopa_ltmp[2:2] = memp[addra_tmp[14:6]][2:2]; + task_x_buf (wr_mode_a, 23, 16, 2, doa_ltmp, doa_tmp, dopa_ltmp, dopa_tmp); + end + + if ((web_tmp[3] === 1'b1 && wea_tmp[3] === 1'b1) || (seq == 2'b01 && web_tmp[3] === 1'b1 && wea_tmp[3] === 1'b0 && viol_type == 2'b10) || (seq == 2'b01 && wr_mode_a != 2'b01 && wr_mode_b != 2'b01) || (seq == 2'b01 && wr_mode_a == 2'b01 && wr_mode_b != 2'b01 && web_tmp[3] === 1'b1) || (seq == 2'b11 && wr_mode_a == 2'b00 && web_tmp[3] !== 1'b1)) begin + doa_ltmp[31:24] = mem[addra_tmp[14:6]][31:24]; + dopa_ltmp[3:3] = memp[addra_tmp[14:6]][3:3]; + task_x_buf (wr_mode_a, 31, 24, 3, doa_ltmp, doa_tmp, dopa_ltmp, dopa_tmp); + end + + if ((web_tmp[4] === 1'b1 && wea_tmp[4] === 1'b1) || (seq == 2'b01 && web_tmp[4] === 1'b1 && wea_tmp[4] === 1'b0 && viol_type == 2'b10) || (seq == 2'b01 && wr_mode_a != 2'b01 && wr_mode_b != 2'b01) || (seq == 2'b01 && wr_mode_a == 2'b01 && wr_mode_b != 2'b01 && web_tmp[4] === 1'b1) || (seq == 2'b11 && wr_mode_a == 2'b00 && web_tmp[4] !== 1'b1)) begin + doa_ltmp[39:32] = mem[addra_tmp[14:6]][39:32]; + dopa_ltmp[4:4] = memp[addra_tmp[14:6]][4:4]; + task_x_buf (wr_mode_a, 39, 32, 4, doa_ltmp, doa_tmp, dopa_ltmp, dopa_tmp); + end + + if ((web_tmp[5] === 1'b1 && wea_tmp[5] === 1'b1) || (seq == 2'b01 && web_tmp[5] === 1'b1 && wea_tmp[5] === 1'b0 && viol_type == 2'b10) || (seq == 2'b01 && wr_mode_a != 2'b01 && wr_mode_b != 2'b01) || (seq == 2'b01 && wr_mode_a == 2'b01 && wr_mode_b != 2'b01 && web_tmp[5] === 1'b1) || (seq == 2'b11 && wr_mode_a == 2'b00 && web_tmp[5] !== 1'b1)) begin + doa_ltmp[47:40] = mem[addra_tmp[14:6]][47:40]; + dopa_ltmp[5:5] = memp[addra_tmp[14:6]][5:5]; + task_x_buf (wr_mode_a, 47, 40, 5, doa_ltmp, doa_tmp, dopa_ltmp, dopa_tmp); + end + + if ((web_tmp[6] === 1'b1 && wea_tmp[6] === 1'b1) || (seq == 2'b01 && web_tmp[6] === 1'b1 && wea_tmp[6] === 1'b0 && viol_type == 2'b10) || (seq == 2'b01 && wr_mode_a != 2'b01 && wr_mode_b != 2'b01) || (seq == 2'b01 && wr_mode_a == 2'b01 && wr_mode_b != 2'b01 && web_tmp[6] === 1'b1) || (seq == 2'b11 && wr_mode_a == 2'b00 && web_tmp[6] !== 1'b1)) begin + doa_ltmp[55:48] = mem[addra_tmp[14:6]][55:48]; + dopa_ltmp[6:6] = memp[addra_tmp[14:6]][6:6]; + task_x_buf (wr_mode_a, 55, 48, 6, doa_ltmp, doa_tmp, dopa_ltmp, dopa_tmp); + end + + if ((web_tmp[7] === 1'b1 && wea_tmp[7] === 1'b1) || (seq == 2'b01 && web_tmp[7] === 1'b1 && wea_tmp[7] === 1'b0 && viol_type == 2'b10) || (seq == 2'b01 && wr_mode_a != 2'b01 && wr_mode_b != 2'b01) || (seq == 2'b01 && wr_mode_a == 2'b01 && wr_mode_b != 2'b01 && web_tmp[7] === 1'b1) || (seq == 2'b11 && wr_mode_a == 2'b00 && web_tmp[7] !== 1'b1)) begin + doa_ltmp[63:56] = mem[addra_tmp[14:6]][63:56]; + dopa_ltmp[7:7] = memp[addra_tmp[14:6]][7:7]; + task_x_buf (wr_mode_a, 63, 56, 7, doa_ltmp, doa_tmp, dopa_ltmp, dopa_tmp); + end + + end + endcase // case(ra_width) + end + endtask // task_col_rd_ram_a + + + task task_col_rd_ram_b; + + input [1:0] seq; // 1 is bypass + input [7:0] wea_tmp; + input [7:0] web_tmp; + input [15:0] addrb_tmp; + inout [63:0] dob_tmp; + inout [7:0] dopb_tmp; + reg [63:0] dob_ltmp; + reg [7:0] dopb_ltmp; + + begin + + dob_ltmp= 64'b0; + dopb_ltmp= 8'b0; + + case (rb_width) + 1, 2, 4 : begin + + if ((web_tmp[0] === 1'b1 && wea_tmp[0] === 1'b1) || (seq == 2'b01 && wea_tmp[0] === 1'b1 && web_tmp[0] === 1'b0 && viol_type == 2'b11) || (seq == 2'b01 && wr_mode_b != 2'b01 && wr_mode_a != 2'b01) || (seq == 2'b01 && wr_mode_b == 2'b01 && wr_mode_a != 2'b01 && wea_tmp[0] === 1'b1) || (seq == 2'b11 && wr_mode_b == 2'b00 && wea_tmp[0] !== 1'b1)) begin + if (rb_width >= width) + dob_ltmp = mem[addrb_tmp[14:r_addrb_lbit_124]]; + else + dob_ltmp = mem[addrb_tmp[14:r_addrb_bit_124+1]][(addrb_tmp[r_addrb_bit_124:r_addrb_lbit_124] * rb_width) +: rb_width]; + + task_x_buf (wr_mode_b, 3, 0, 0, dob_ltmp, dob_tmp, dopb_ltmp, dopb_tmp); + + end + end // case: 1, 2, 4 + 8 : begin + + if ((web_tmp[0] === 1'b1 && wea_tmp[0] === 1'b1) || (seq == 2'b01 && wea_tmp[0] === 1'b1 && web_tmp[0] === 1'b0 && viol_type == 2'b11) || (seq == 2'b01 && wr_mode_b != 2'b01 && wr_mode_a != 2'b01) || (seq == 2'b01 && wr_mode_b == 2'b01 && wr_mode_a != 2'b01 && wea_tmp[0] === 1'b1) || (seq == 2'b11 && wr_mode_b == 2'b00 && wea_tmp[0] !== 1'b1)) begin + + if (rb_width >= width) begin + dob_ltmp = mem[addrb_tmp[14:3]]; + dopb_ltmp = memp[addrb_tmp[14:3]]; + end + else begin + dob_ltmp = mem[addrb_tmp[14:r_addrb_bit_8+1]][(addrb_tmp[r_addrb_bit_8:3] * 8) +: 8]; + dopb_ltmp = memp[addrb_tmp[14:r_addrb_bit_8+1]][(addrb_tmp[r_addrb_bit_8:3] * 1) +: 1]; + end + + task_x_buf (wr_mode_b, 7, 0, 0, dob_ltmp, dob_tmp, dopb_ltmp, dopb_tmp); + + end + end // case: 8 + 16 : begin + + if ((web_tmp[0] === 1'b1 && wea_tmp[0] === 1'b1) || (seq == 2'b01 && wea_tmp[0] === 1'b1 && web_tmp[0] === 1'b0 && viol_type == 2'b11) || (seq == 2'b01 && wr_mode_b != 2'b01 && wr_mode_a != 2'b01) || (seq == 2'b01 && wr_mode_b == 2'b01 && wr_mode_a != 2'b01 && wea_tmp[0] === 1'b1) || (seq == 2'b11 && wr_mode_b == 2'b00 && wea_tmp[0] !== 1'b1)) begin + if (rb_width >= width) begin + dob_ltmp[7:0] = mem[addrb_tmp[14:4]][7:0]; + dopb_ltmp[0:0] = memp[addrb_tmp[14:4]][0:0]; + end + else begin + dob_ltmp[7:0] = mem[addrb_tmp[14:r_addrb_bit_16+1]][(addrb_tmp[r_addrb_bit_16:4] * 16) +: 8]; + dopb_ltmp[0:0] = memp[addrb_tmp[14:r_addrb_bit_16+1]][(addrb_tmp[r_addrb_bit_16:4] * 2) +: 1]; + end + task_x_buf (wr_mode_b, 7, 0, 0, dob_ltmp, dob_tmp, dopb_ltmp, dopb_tmp); + end + + + if ((web_tmp[1] === 1'b1 && wea_tmp[1] === 1'b1) || (seq == 2'b01 && wea_tmp[1] === 1'b1 && web_tmp[1] === 1'b0 && viol_type == 2'b11) || (seq == 2'b01 && wr_mode_b != 2'b01 && wr_mode_a != 2'b01) || (seq == 2'b01 && wr_mode_b == 2'b01 && wr_mode_a != 2'b01 && wea_tmp[1] === 1'b1) || (seq == 2'b11 && wr_mode_b == 2'b00 && wea_tmp[1] !== 1'b1)) begin + + if (rb_width >= width) begin + dob_ltmp[15:8] = mem[addrb_tmp[14:4]][15:8]; + dopb_ltmp[1:1] = memp[addrb_tmp[14:4]][1:1]; + end + else begin + dob_ltmp[15:8] = mem[addrb_tmp[14:r_addrb_bit_16+1]][((addrb_tmp[r_addrb_bit_16:4] * 16) + 8) +: 8]; + dopb_ltmp[1:1] = memp[addrb_tmp[14:r_addrb_bit_16+1]][((addrb_tmp[r_addrb_bit_16:4] * 2) + 1) +: 1]; + end + task_x_buf (wr_mode_b, 15, 8, 1, dob_ltmp, dob_tmp, dopb_ltmp, dopb_tmp); + end + + end + 32 : begin + + if ((web_tmp[0] === 1'b1 && wea_tmp[0] === 1'b1) || (seq == 2'b01 && wea_tmp[0] === 1'b1 && web_tmp[0] === 1'b0 && viol_type == 2'b11) || (seq == 2'b01 && wr_mode_b != 2'b01 && wr_mode_a != 2'b01) || (seq == 2'b01 && wr_mode_b == 2'b01 && wr_mode_a != 2'b01 && wea_tmp[0] === 1'b1) || (seq == 2'b11 && wr_mode_b == 2'b00 && wea_tmp[0] !== 1'b1)) begin + if (rb_width >= width) begin + dob_ltmp[7:0] = mem[addrb_tmp[14:5]][7:0]; + dopb_ltmp[0:0] = memp[addrb_tmp[14:5]][0:0]; + end + else begin + dob_ltmp[7:0] = mem[addrb_tmp[14:r_addrb_bit_32+1]][(addrb_tmp[r_addrb_bit_32:5] * 32) +: 8]; + dopb_ltmp[0:0] = memp[addrb_tmp[14:r_addrb_bit_32+1]][(addrb_tmp[r_addrb_bit_32:5] * 4) +: 1]; + end + task_x_buf (wr_mode_b, 7, 0, 0, dob_ltmp, dob_tmp, dopb_ltmp, dopb_tmp); + end + + + if ((web_tmp[1] === 1'b1 && wea_tmp[1] === 1'b1) || (seq == 2'b01 && wea_tmp[1] === 1'b1 && web_tmp[1] === 1'b0 && viol_type == 2'b11) || (seq == 2'b01 && wr_mode_b != 2'b01 && wr_mode_a != 2'b01) || (seq == 2'b01 && wr_mode_b == 2'b01 && wr_mode_a != 2'b01 && wea_tmp[1] === 1'b1) || (seq == 2'b11 && wr_mode_b == 2'b00 && wea_tmp[1] !== 1'b1)) begin + if (rb_width >= width) begin + dob_ltmp[15:8] = mem[addrb_tmp[14:5]][15:8]; + dopb_ltmp[1:1] = memp[addrb_tmp[14:5]][1:1]; + end + else begin + dob_ltmp[15:8] = mem[addrb_tmp[14:r_addrb_bit_32+1]][((addrb_tmp[r_addrb_bit_32:5] * 32) + 8) +: 8]; + dopb_ltmp[1:1] = memp[addrb_tmp[14:r_addrb_bit_32+1]][((addrb_tmp[r_addrb_bit_32:5] * 4) + 1) +: 1]; + end + task_x_buf (wr_mode_b, 15, 8, 1, dob_ltmp, dob_tmp, dopb_ltmp, dopb_tmp); + end + + + if ((web_tmp[2] === 1'b1 && wea_tmp[2] === 1'b1) || (seq == 2'b01 && wea_tmp[2] === 1'b1 && web_tmp[2] === 1'b0 && viol_type == 2'b11) || (seq == 2'b01 && wr_mode_b != 2'b01 && wr_mode_a != 2'b01) || (seq == 2'b01 && wr_mode_b == 2'b01 && wr_mode_a != 2'b01 && wea_tmp[2] === 1'b1) || (seq == 2'b11 && wr_mode_b == 2'b00 && wea_tmp[2] !== 1'b1)) begin + if (rb_width >= width) begin + dob_ltmp[23:16] = mem[addrb_tmp[14:5]][23:16]; + dopb_ltmp[2:2] = memp[addrb_tmp[14:5]][2:2]; + end + else begin + dob_ltmp[23:16] = mem[addrb_tmp[14:r_addrb_bit_32+1]][((addrb_tmp[r_addrb_bit_32:5] * 32) + 16) +: 8]; + dopb_ltmp[2:2] = memp[addrb_tmp[14:r_addrb_bit_32+1]][((addrb_tmp[r_addrb_bit_32:5] * 4) + 2) +: 1]; + end + task_x_buf (wr_mode_b, 23, 16, 2, dob_ltmp, dob_tmp, dopb_ltmp, dopb_tmp); + end + + + if ((web_tmp[3] === 1'b1 && wea_tmp[3] === 1'b1) || (seq == 2'b01 && wea_tmp[3] === 1'b1 && web_tmp[3] === 1'b0 && viol_type == 2'b11) || (seq == 2'b01 && wr_mode_b != 2'b01 && wr_mode_a != 2'b01) || (seq == 2'b01 && wr_mode_b == 2'b01 && wr_mode_a != 2'b01 && wea_tmp[3] === 1'b1) || (seq == 2'b11 && wr_mode_b == 2'b00 && wea_tmp[3] !== 1'b1)) begin + if (rb_width >= width) begin + dob_ltmp[31:24] = mem[addrb_tmp[14:5]][31:24]; + dopb_ltmp[3:3] = memp[addrb_tmp[14:5]][3:3]; + end + else begin + dob_ltmp[31:24] = mem[addrb_tmp[14:r_addrb_bit_32+1]][((addrb_tmp[r_addrb_bit_32:5] * 32) + 24) +: 8]; + dopb_ltmp[3:3] = memp[addrb_tmp[14:r_addrb_bit_32+1]][((addrb_tmp[r_addrb_bit_32:5] * 4) + 3) +: 1]; + end + task_x_buf (wr_mode_b, 31, 24, 3, dob_ltmp, dob_tmp, dopb_ltmp, dopb_tmp); + end + end + 64 : begin + + if ((web_tmp[0] === 1'b1 && wea_tmp[0] === 1'b1) || (seq == 2'b01 && wea_tmp[0] === 1'b1 && web_tmp[0] === 1'b0 && viol_type == 2'b11) || (seq == 2'b01 && wr_mode_b != 2'b01 && wr_mode_a != 2'b01) || (seq == 2'b01 && wr_mode_b == 2'b01 && wr_mode_a != 2'b01 && wea_tmp[0] === 1'b1) || (seq == 2'b11 && wr_mode_b == 2'b00 && wea_tmp[0] !== 1'b1)) begin + dob_ltmp[7:0] = mem[addrb_tmp[14:6]][7:0]; + dopb_ltmp[0:0] = memp[addrb_tmp[14:6]][0:0]; + task_x_buf (wr_mode_b, 7, 0, 0, dob_ltmp, dob_tmp, dopb_ltmp, dopb_tmp); + end + + if ((web_tmp[1] === 1'b1 && wea_tmp[1] === 1'b1) || (seq == 2'b01 && wea_tmp[1] === 1'b1 && web_tmp[1] === 1'b0 && viol_type == 2'b11) || (seq == 2'b01 && wr_mode_b != 2'b01 && wr_mode_a != 2'b01) || (seq == 2'b01 && wr_mode_b == 2'b01 && wr_mode_a != 2'b01 && wea_tmp[1] === 1'b1) || (seq == 2'b11 && wr_mode_b == 2'b00 && wea_tmp[1] !== 1'b1)) begin + dob_ltmp[15:8] = mem[addrb_tmp[14:6]][15:8]; + dopb_ltmp[1:1] = memp[addrb_tmp[14:6]][1:1]; + task_x_buf (wr_mode_b, 15, 8, 1, dob_ltmp, dob_tmp, dopb_ltmp, dopb_tmp); + end + + if ((web_tmp[2] === 1'b1 && wea_tmp[2] === 1'b1) || (seq == 2'b01 && wea_tmp[2] === 1'b1 && web_tmp[2] === 1'b0 && viol_type == 2'b11) || (seq == 2'b01 && wr_mode_b != 2'b01 && wr_mode_a != 2'b01) || (seq == 2'b01 && wr_mode_b == 2'b01 && wr_mode_a != 2'b01 && wea_tmp[2] === 1'b1) || (seq == 2'b11 && wr_mode_b == 2'b00 && wea_tmp[2] !== 1'b1)) begin + dob_ltmp[23:16] = mem[addrb_tmp[14:6]][23:16]; + dopb_ltmp[2:2] = memp[addrb_tmp[14:6]][2:2]; + task_x_buf (wr_mode_b, 23, 16, 2, dob_ltmp, dob_tmp, dopb_ltmp, dopb_tmp); + end + + if ((web_tmp[3] === 1'b1 && wea_tmp[3] === 1'b1) || (seq == 2'b01 && wea_tmp[3] === 1'b1 && web_tmp[3] === 1'b0 && viol_type == 2'b11) || (seq == 2'b01 && wr_mode_b != 2'b01 && wr_mode_a != 2'b01) || (seq == 2'b01 && wr_mode_b == 2'b01 && wr_mode_a != 2'b01 && wea_tmp[3] === 1'b1) || (seq == 2'b11 && wr_mode_b == 2'b00 && wea_tmp[3] !== 1'b1)) begin + dob_ltmp[31:24] = mem[addrb_tmp[14:6]][31:24]; + dopb_ltmp[3:3] = memp[addrb_tmp[14:6]][3:3]; + task_x_buf (wr_mode_b, 31, 24, 3, dob_ltmp, dob_tmp, dopb_ltmp, dopb_tmp); + end + + if ((web_tmp[4] === 1'b1 && wea_tmp[4] === 1'b1) || (seq == 2'b01 && wea_tmp[4] === 1'b1 && web_tmp[4] === 1'b0 && viol_type == 2'b11) || (seq == 2'b01 && wr_mode_b != 2'b01 && wr_mode_a != 2'b01) || (seq == 2'b01 && wr_mode_b == 2'b01 && wr_mode_a != 2'b01 && wea_tmp[4] === 1'b1) || (seq == 2'b11 && wr_mode_b == 2'b00 && wea_tmp[4] !== 1'b1)) begin + dob_ltmp[39:32] = mem[addrb_tmp[14:6]][39:32]; + dopb_ltmp[4:4] = memp[addrb_tmp[14:6]][4:4]; + task_x_buf (wr_mode_b, 39, 32, 4, dob_ltmp, dob_tmp, dopb_ltmp, dopb_tmp); + end + + if ((web_tmp[5] === 1'b1 && wea_tmp[5] === 1'b1) || (seq == 2'b01 && wea_tmp[5] === 1'b1 && web_tmp[5] === 1'b0 && viol_type == 2'b11) || (seq == 2'b01 && wr_mode_b != 2'b01 && wr_mode_a != 2'b01) || (seq == 2'b01 && wr_mode_b == 2'b01 && wr_mode_a != 2'b01 && wea_tmp[5] === 1'b1) || (seq == 2'b11 && wr_mode_b == 2'b00 && wea_tmp[5] !== 1'b1)) begin + dob_ltmp[47:40] = mem[addrb_tmp[14:6]][47:40]; + dopb_ltmp[5:5] = memp[addrb_tmp[14:6]][5:5]; + task_x_buf (wr_mode_b, 47, 40, 5, dob_ltmp, dob_tmp, dopb_ltmp, dopb_tmp); + end + + if ((web_tmp[6] === 1'b1 && wea_tmp[6] === 1'b1) || (seq == 2'b01 && wea_tmp[6] === 1'b1 && web_tmp[6] === 1'b0 && viol_type == 2'b11) || (seq == 2'b01 && wr_mode_b != 2'b01 && wr_mode_a != 2'b01) || (seq == 2'b01 && wr_mode_b == 2'b01 && wr_mode_a != 2'b01 && wea_tmp[6] === 1'b1) || (seq == 2'b11 && wr_mode_b == 2'b00 && wea_tmp[6] !== 1'b1)) begin + dob_ltmp[55:48] = mem[addrb_tmp[14:6]][55:48]; + dopb_ltmp[6:6] = memp[addrb_tmp[14:6]][6:6]; + task_x_buf (wr_mode_b, 55, 48, 6, dob_ltmp, dob_tmp, dopb_ltmp, dopb_tmp); + end + + if ((web_tmp[7] === 1'b1 && wea_tmp[7] === 1'b1) || (seq == 2'b01 && wea_tmp[7] === 1'b1 && web_tmp[7] === 1'b0 && viol_type == 2'b11) || (seq == 2'b01 && wr_mode_b != 2'b01 && wr_mode_a != 2'b01) || (seq == 2'b01 && wr_mode_b == 2'b01 && wr_mode_a != 2'b01 && wea_tmp[7] === 1'b1) || (seq == 2'b11 && wr_mode_b == 2'b00 && wea_tmp[7] !== 1'b1)) begin + dob_ltmp[63:56] = mem[addrb_tmp[14:6]][63:56]; + dopb_ltmp[7:7] = memp[addrb_tmp[14:6]][7:7]; + task_x_buf (wr_mode_b, 63, 56, 7, dob_ltmp, dob_tmp, dopb_ltmp, dopb_tmp); + end + + end + endcase // case(rb_width) + end + endtask // task_col_rd_ram_b + + + task task_rd_ram_a; + + input [15:0] addra_tmp; + inout [63:0] doa_tmp; + inout [7:0] dopa_tmp; + + begin + + case (ra_width) + 1, 2, 4 : begin + if (ra_width >= width) + doa_tmp = mem[addra_tmp[14:r_addra_lbit_124]]; + + else + doa_tmp = mem[addra_tmp[14:r_addra_bit_124+1]][(addra_tmp[r_addra_bit_124:r_addra_lbit_124] * ra_width) +: ra_width]; + end + 8 : begin + if (ra_width >= width) begin + doa_tmp = mem[addra_tmp[14:3]]; + dopa_tmp = memp[addra_tmp[14:3]]; + end + else begin + doa_tmp = mem[addra_tmp[14:r_addra_bit_8+1]][(addra_tmp[r_addra_bit_8:3] * 8) +: 8]; + dopa_tmp = memp[addra_tmp[14:r_addra_bit_8+1]][(addra_tmp[r_addra_bit_8:3] * 1) +: 1]; + end + end + 16 : begin + if (ra_width >= width) begin + doa_tmp = mem[addra_tmp[14:4]]; + dopa_tmp = memp[addra_tmp[14:4]]; + end + else begin + doa_tmp = mem[addra_tmp[14:r_addra_bit_16+1]][(addra_tmp[r_addra_bit_16:4] * 16) +: 16]; + dopa_tmp = memp[addra_tmp[14:r_addra_bit_16+1]][(addra_tmp[r_addra_bit_16:4] * 2) +: 2]; + end + end + 32 : begin + if (ra_width >= width) begin + doa_tmp = mem[addra_tmp[14:5]]; + dopa_tmp = memp[addra_tmp[14:5]]; + end + else begin + doa_tmp = mem[addra_tmp[14:r_addra_bit_32+1]][(addra_tmp[r_addra_bit_32:5] * 32) +: 32]; + dopa_tmp = memp[addra_tmp[14:r_addra_bit_32+1]][(addra_tmp[r_addra_bit_32:5] * 4) +: 4]; + end + end + 64 : begin + if (ra_width >= width) begin + doa_tmp = mem[addra_tmp[14:6]]; + dopa_tmp = memp[addra_tmp[14:6]]; + end + end + endcase // case(ra_width) + + end + endtask // task_rd_ram_a + + + task task_rd_ram_b; + + input [15:0] addrb_tmp; + inout [31:0] dob_tmp; + inout [3:0] dopb_tmp; + + begin + + case (rb_width) + 1, 2, 4 : begin + if (rb_width >= width) + dob_tmp = mem[addrb_tmp[14:r_addrb_lbit_124]]; + else + dob_tmp = mem[addrb_tmp[14:r_addrb_bit_124+1]][(addrb_tmp[r_addrb_bit_124:r_addrb_lbit_124] * rb_width) +: rb_width]; + end + 8 : begin + if (rb_width >= width) begin + dob_tmp = mem[addrb_tmp[14:3]]; + dopb_tmp = memp[addrb_tmp[14:3]]; + end + else begin + dob_tmp = mem[addrb_tmp[14:r_addrb_bit_8+1]][(addrb_tmp[r_addrb_bit_8:3] * 8) +: 8]; + dopb_tmp = memp[addrb_tmp[14:r_addrb_bit_8+1]][(addrb_tmp[r_addrb_bit_8:3] * 1) +: 1]; + end + end + 16 : begin + if (rb_width >= width) begin + dob_tmp = mem[addrb_tmp[14:4]]; + dopb_tmp = memp[addrb_tmp[14:4]]; + end + else begin + dob_tmp = mem[addrb_tmp[14:r_addrb_bit_16+1]][(addrb_tmp[r_addrb_bit_16:4] * 16) +: 16]; + dopb_tmp = memp[addrb_tmp[14:r_addrb_bit_16+1]][(addrb_tmp[r_addrb_bit_16:4] * 2) +: 2]; + end + end + 32 : begin + dob_tmp = mem[addrb_tmp[14:5]]; + dopb_tmp = memp[addrb_tmp[14:5]]; + end + + endcase + end + endtask // task_rd_ram_b + + + task chk_for_col_msg; + + input wea_tmp; + input web_tmp; + input [15:0] addra_tmp; + input [15:0] addrb_tmp; + + begin + + if ((SIM_COLLISION_CHECK == "ALL" || SIM_COLLISION_CHECK == "WARNING_ONLY") && !(rdaddr_collision_hwconfig_int == 0 && viol_time == 1 && ((wr_mode_b == 2'b01 && web_tmp === 1'b1 && wea_tmp === 1'b0) || (wr_mode_a == 2'b01 && wea_tmp === 1'b1 && web_tmp === 1'b0)))) + + if (wea_tmp === 1'b1 && web_tmp === 1'b1 && col_wr_wr_msg == 1) begin + $display("Memory Collision Error on RB18_INTERNAL_VLOG : %m at simulation time %.3f ns.\nA write was requested to the same address simultaneously at both port A and port B of the RAM. The contents written to the RAM at address location %h (hex) of port A and address location %h (hex) of port B are unknown.", $time/1000.0, addra_tmp, addrb_tmp); + col_wr_wr_msg = 0; + end + + else if (wea_tmp === 1'b1 && web_tmp === 1'b0 && col_wra_rdb_msg == 1) begin + + if ((wr_mode_a == 2'b01 || wr_mode_b == 2'b01) && ((viol_time == 1 && rdaddr_collision_hwconfig_int == 1) || viol_time == 2)) + $display("Memory Collision Error on RB18_INTERNAL_VLOG : %m at simulation time %.3f ns.\nA read was performed on address %h (hex) of port B while a write was requested to the same address on port A. The write will be unsuccessful and the content of the RAM at address location %h (hex) of port A became unknown.", $time/1000.0, addrb_tmp, addra_tmp); + else + $display("Memory Collision Error on RB18_INTERNAL_VLOG : %m at simulation time %.3f ns.\nA read was performed on address %h (hex) of port B while a write was requested to the same address on port A. The write will be successful however the read value on port B is unknown until the next CLKB cycle.", $time/1000.0, addrb_tmp); + + col_wra_rdb_msg = 0; + + end + else if (wea_tmp === 1'b0 && web_tmp === 1'b1 && col_wrb_rda_msg == 1) begin + + if ((wr_mode_a == 2'b01 || wr_mode_b == 2'b01) && ((viol_time == 1 && rdaddr_collision_hwconfig_int == 1) || viol_time == 2)) + $display("Memory Collision Error on RB18_INTERNAL_VLOG : %m at simulation time %.3f ns.\nA read was performed on address %h (hex) of port A while a write was requested to the same address on port B. The write will be unsuccessful and the content of the RAM at address location %h (hex) of port B became unknown.", $time/1000.0, addra_tmp, addrb_tmp); + else + $display("Memory Collision Error on RB18_INTERNAL_VLOG : %m at simulation time %.3f ns.\nA read was performed on address %h (hex) of port A while a write was requested to the same address on port B. The write will be successful however the read value on port A is unknown until the next CLKA cycle.", $time/1000.0, addra_tmp); + + col_wrb_rda_msg = 0; + + end + + end + + endtask // chk_for_col_msg + + + task task_col_ecc_read; + + inout [63:0] do_tmp; + inout [7:0] dop_tmp; + input [15:0] addr_tmp; + + reg [71:0] task_ecc_bit_position; + reg [7:0] task_dopr_ecc, task_syndrome; + reg [63:0] task_di_in_ecc_corrected; + reg [7:0] task_dip_in_ecc_corrected; + + begin + + if (|do_tmp === 1'bx) begin // if there is collision + dbiterr_out <= 1'bx; + sbiterr_out <= 1'bx; + end + else begin + + task_dopr_ecc = fn_dip_ecc(1'b0, do_tmp, dop_tmp); + + task_syndrome = task_dopr_ecc ^ dop_tmp; + + if (task_syndrome !== 0) begin + + if (task_syndrome[7]) begin // dectect single bit error + + task_ecc_bit_position = {do_tmp[63:57], dop_tmp[6], do_tmp[56:26], dop_tmp[5], do_tmp[25:11], dop_tmp[4], do_tmp[10:4], dop_tmp[3], do_tmp[3:1], dop_tmp[2], do_tmp[0], dop_tmp[1:0], dop_tmp[7]}; + + + if (task_syndrome[6:0] > 71) begin + $display ("DRC Error : Simulation halted due Corrupted DIP. To correct this problem, make sure that reliable data is fed to the DIP. The correct Parity must be generated by a Hamming code encoder or encoder in the Block RAM. The output from the model is unreliable if there are more than 2 bit errors. The model doesn't warn if there is sporadic input of more than 2 bit errors due to the limitation in Hamming code."); + $finish; + end + + task_ecc_bit_position[task_syndrome[6:0]] = ~task_ecc_bit_position[task_syndrome[6:0]]; // correct single bit error in the output + + task_di_in_ecc_corrected = {task_ecc_bit_position[71:65], task_ecc_bit_position[63:33], task_ecc_bit_position[31:17], task_ecc_bit_position[15:9], task_ecc_bit_position[7:5], task_ecc_bit_position[3]}; // correct single bit error in the memory + + do_tmp = task_di_in_ecc_corrected; + + task_dip_in_ecc_corrected = {task_ecc_bit_position[0], task_ecc_bit_position[64], task_ecc_bit_position[32], task_ecc_bit_position[16], task_ecc_bit_position[8], task_ecc_bit_position[4], task_ecc_bit_position[2:1]}; // correct single bit error in the parity memory + + dop_tmp = task_dip_in_ecc_corrected; + + dbiterr_out <= 0; + sbiterr_out <= 1; + + end + else if (!task_syndrome[7]) begin // double bit error + sbiterr_out <= 0; + dbiterr_out <= 1; + + end + end // if (task_syndrome !== 0) + else begin + dbiterr_out <= 0; + sbiterr_out <= 0; + + end // else: !if(task_syndrome !== 0) + + end + + end + + endtask // task_col_ecc_read + + + function [7:0] fn_dip_ecc; + + input encode; + input [63:0] di_in; + input [7:0] dip_in; + + begin + + fn_dip_ecc[0] = di_in[0]^di_in[1]^di_in[3]^di_in[4]^di_in[6]^di_in[8] + ^di_in[10]^di_in[11]^di_in[13]^di_in[15]^di_in[17]^di_in[19] + ^di_in[21]^di_in[23]^di_in[25]^di_in[26]^di_in[28] + ^di_in[30]^di_in[32]^di_in[34]^di_in[36]^di_in[38] + ^di_in[40]^di_in[42]^di_in[44]^di_in[46]^di_in[48] + ^di_in[50]^di_in[52]^di_in[54]^di_in[56]^di_in[57]^di_in[59] + ^di_in[61]^di_in[63]; + + fn_dip_ecc[1] = di_in[0]^di_in[2]^di_in[3]^di_in[5]^di_in[6]^di_in[9] + ^di_in[10]^di_in[12]^di_in[13]^di_in[16]^di_in[17] + ^di_in[20]^di_in[21]^di_in[24]^di_in[25]^di_in[27]^di_in[28] + ^di_in[31]^di_in[32]^di_in[35]^di_in[36]^di_in[39] + ^di_in[40]^di_in[43]^di_in[44]^di_in[47]^di_in[48] + ^di_in[51]^di_in[52]^di_in[55]^di_in[56]^di_in[58]^di_in[59] + ^di_in[62]^di_in[63]; + + fn_dip_ecc[2] = di_in[1]^di_in[2]^di_in[3]^di_in[7]^di_in[8]^di_in[9] + ^di_in[10]^di_in[14]^di_in[15]^di_in[16]^di_in[17] + ^di_in[22]^di_in[23]^di_in[24]^di_in[25]^di_in[29] + ^di_in[30]^di_in[31]^di_in[32]^di_in[37]^di_in[38]^di_in[39] + ^di_in[40]^di_in[45]^di_in[46]^di_in[47]^di_in[48] + ^di_in[53]^di_in[54]^di_in[55]^di_in[56] + ^di_in[60]^di_in[61]^di_in[62]^di_in[63]; + + fn_dip_ecc[3] = di_in[4]^di_in[5]^di_in[6]^di_in[7]^di_in[8]^di_in[9] + ^di_in[10]^di_in[18]^di_in[19] + ^di_in[20]^di_in[21]^di_in[22]^di_in[23]^di_in[24]^di_in[25] + ^di_in[33]^di_in[34]^di_in[35]^di_in[36]^di_in[37]^di_in[38]^di_in[39] + ^di_in[40]^di_in[49] + ^di_in[50]^di_in[51]^di_in[52]^di_in[53]^di_in[54]^di_in[55]^di_in[56]; + + fn_dip_ecc[4] = di_in[11]^di_in[12]^di_in[13]^di_in[14]^di_in[15]^di_in[16]^di_in[17]^di_in[18]^di_in[19] + ^di_in[20]^di_in[21]^di_in[22]^di_in[23]^di_in[24]^di_in[25] + ^di_in[41]^di_in[42]^di_in[43]^di_in[44]^di_in[45]^di_in[46]^di_in[47]^di_in[48]^di_in[49] + ^di_in[50]^di_in[51]^di_in[52]^di_in[53]^di_in[54]^di_in[55]^di_in[56]; + + + fn_dip_ecc[5] = di_in[26]^di_in[27]^di_in[28]^di_in[29] + ^di_in[30]^di_in[31]^di_in[32]^di_in[33]^di_in[34]^di_in[35]^di_in[36]^di_in[37]^di_in[38]^di_in[39] + ^di_in[40]^di_in[41]^di_in[42]^di_in[43]^di_in[44]^di_in[45]^di_in[46]^di_in[47]^di_in[48]^di_in[49] + ^di_in[50]^di_in[51]^di_in[52]^di_in[53]^di_in[54]^di_in[55]^di_in[56]; + + fn_dip_ecc[6] = di_in[57]^di_in[58]^di_in[59] + ^di_in[60]^di_in[61]^di_in[62]^di_in[63]; + + if (encode == 1'b1) + + fn_dip_ecc[7] = fn_dip_ecc[0]^fn_dip_ecc[1]^fn_dip_ecc[2]^fn_dip_ecc[3]^fn_dip_ecc[4]^fn_dip_ecc[5]^fn_dip_ecc[6] + ^di_in[0]^di_in[1]^di_in[2]^di_in[3]^di_in[4]^di_in[5]^di_in[6]^di_in[7]^di_in[8]^di_in[9] + ^di_in[10]^di_in[11]^di_in[12]^di_in[13]^di_in[14]^di_in[15]^di_in[16]^di_in[17]^di_in[18]^di_in[19] + ^di_in[20]^di_in[21]^di_in[22]^di_in[23]^di_in[24]^di_in[25]^di_in[26]^di_in[27]^di_in[28]^di_in[29] + ^di_in[30]^di_in[31]^di_in[32]^di_in[33]^di_in[34]^di_in[35]^di_in[36]^di_in[37]^di_in[38]^di_in[39] + ^di_in[40]^di_in[41]^di_in[42]^di_in[43]^di_in[44]^di_in[45]^di_in[46]^di_in[47]^di_in[48]^di_in[49] + ^di_in[50]^di_in[51]^di_in[52]^di_in[53]^di_in[54]^di_in[55]^di_in[56]^di_in[57]^di_in[58]^di_in[59] + ^di_in[60]^di_in[61]^di_in[62]^di_in[63]; + else + fn_dip_ecc[7] = dip_in[0]^dip_in[1]^dip_in[2]^dip_in[3]^dip_in[4]^dip_in[5]^dip_in[6] + ^di_in[0]^di_in[1]^di_in[2]^di_in[3]^di_in[4]^di_in[5]^di_in[6]^di_in[7]^di_in[8]^di_in[9] + ^di_in[10]^di_in[11]^di_in[12]^di_in[13]^di_in[14]^di_in[15]^di_in[16]^di_in[17]^di_in[18]^di_in[19] + ^di_in[20]^di_in[21]^di_in[22]^di_in[23]^di_in[24]^di_in[25]^di_in[26]^di_in[27]^di_in[28]^di_in[29] + ^di_in[30]^di_in[31]^di_in[32]^di_in[33]^di_in[34]^di_in[35]^di_in[36]^di_in[37]^di_in[38]^di_in[39] + ^di_in[40]^di_in[41]^di_in[42]^di_in[43]^di_in[44]^di_in[45]^di_in[46]^di_in[47]^di_in[48]^di_in[49] + ^di_in[50]^di_in[51]^di_in[52]^di_in[53]^di_in[54]^di_in[55]^di_in[56]^di_in[57]^di_in[58]^di_in[59] + ^di_in[60]^di_in[61]^di_in[62]^di_in[63]; + + end + + endfunction // fn_dip_ecc + +/******************************************** END task and function **************************************/ + + + initial begin + + if (INIT_FILE == "NONE") begin // memory initialization from attributes + + init_mult = 256/width; + + for (count = 0; count < init_mult; count = count + 1) begin + + init_offset = count * width; + + mem[count] = INIT_00[init_offset +:width]; + mem[count + (init_mult * 1)] = INIT_01[init_offset +:width]; + mem[count + (init_mult * 2)] = INIT_02[init_offset +:width]; + mem[count + (init_mult * 3)] = INIT_03[init_offset +:width]; + mem[count + (init_mult * 4)] = INIT_04[init_offset +:width]; + mem[count + (init_mult * 5)] = INIT_05[init_offset +:width]; + mem[count + (init_mult * 6)] = INIT_06[init_offset +:width]; + mem[count + (init_mult * 7)] = INIT_07[init_offset +:width]; + mem[count + (init_mult * 8)] = INIT_08[init_offset +:width]; + mem[count + (init_mult * 9)] = INIT_09[init_offset +:width]; + mem[count + (init_mult * 10)] = INIT_0A[init_offset +:width]; + mem[count + (init_mult * 11)] = INIT_0B[init_offset +:width]; + mem[count + (init_mult * 12)] = INIT_0C[init_offset +:width]; + mem[count + (init_mult * 13)] = INIT_0D[init_offset +:width]; + mem[count + (init_mult * 14)] = INIT_0E[init_offset +:width]; + mem[count + (init_mult * 15)] = INIT_0F[init_offset +:width]; + mem[count + (init_mult * 16)] = INIT_10[init_offset +:width]; + mem[count + (init_mult * 17)] = INIT_11[init_offset +:width]; + mem[count + (init_mult * 18)] = INIT_12[init_offset +:width]; + mem[count + (init_mult * 19)] = INIT_13[init_offset +:width]; + mem[count + (init_mult * 20)] = INIT_14[init_offset +:width]; + mem[count + (init_mult * 21)] = INIT_15[init_offset +:width]; + mem[count + (init_mult * 22)] = INIT_16[init_offset +:width]; + mem[count + (init_mult * 23)] = INIT_17[init_offset +:width]; + mem[count + (init_mult * 24)] = INIT_18[init_offset +:width]; + mem[count + (init_mult * 25)] = INIT_19[init_offset +:width]; + mem[count + (init_mult * 26)] = INIT_1A[init_offset +:width]; + mem[count + (init_mult * 27)] = INIT_1B[init_offset +:width]; + mem[count + (init_mult * 28)] = INIT_1C[init_offset +:width]; + mem[count + (init_mult * 29)] = INIT_1D[init_offset +:width]; + mem[count + (init_mult * 30)] = INIT_1E[init_offset +:width]; + mem[count + (init_mult * 31)] = INIT_1F[init_offset +:width]; + mem[count + (init_mult * 32)] = INIT_20[init_offset +:width]; + mem[count + (init_mult * 33)] = INIT_21[init_offset +:width]; + mem[count + (init_mult * 34)] = INIT_22[init_offset +:width]; + mem[count + (init_mult * 35)] = INIT_23[init_offset +:width]; + mem[count + (init_mult * 36)] = INIT_24[init_offset +:width]; + mem[count + (init_mult * 37)] = INIT_25[init_offset +:width]; + mem[count + (init_mult * 38)] = INIT_26[init_offset +:width]; + mem[count + (init_mult * 39)] = INIT_27[init_offset +:width]; + mem[count + (init_mult * 40)] = INIT_28[init_offset +:width]; + mem[count + (init_mult * 41)] = INIT_29[init_offset +:width]; + mem[count + (init_mult * 42)] = INIT_2A[init_offset +:width]; + mem[count + (init_mult * 43)] = INIT_2B[init_offset +:width]; + mem[count + (init_mult * 44)] = INIT_2C[init_offset +:width]; + mem[count + (init_mult * 45)] = INIT_2D[init_offset +:width]; + mem[count + (init_mult * 46)] = INIT_2E[init_offset +:width]; + mem[count + (init_mult * 47)] = INIT_2F[init_offset +:width]; + mem[count + (init_mult * 48)] = INIT_30[init_offset +:width]; + mem[count + (init_mult * 49)] = INIT_31[init_offset +:width]; + mem[count + (init_mult * 50)] = INIT_32[init_offset +:width]; + mem[count + (init_mult * 51)] = INIT_33[init_offset +:width]; + mem[count + (init_mult * 52)] = INIT_34[init_offset +:width]; + mem[count + (init_mult * 53)] = INIT_35[init_offset +:width]; + mem[count + (init_mult * 54)] = INIT_36[init_offset +:width]; + mem[count + (init_mult * 55)] = INIT_37[init_offset +:width]; + mem[count + (init_mult * 56)] = INIT_38[init_offset +:width]; + mem[count + (init_mult * 57)] = INIT_39[init_offset +:width]; + mem[count + (init_mult * 58)] = INIT_3A[init_offset +:width]; + mem[count + (init_mult * 59)] = INIT_3B[init_offset +:width]; + mem[count + (init_mult * 60)] = INIT_3C[init_offset +:width]; + mem[count + (init_mult * 61)] = INIT_3D[init_offset +:width]; + mem[count + (init_mult * 62)] = INIT_3E[init_offset +:width]; + mem[count + (init_mult * 63)] = INIT_3F[init_offset +:width]; + + if (BRAM_SIZE == 36) begin + mem[count + (init_mult * 64)] = INIT_40[init_offset +:width]; + mem[count + (init_mult * 65)] = INIT_41[init_offset +:width]; + mem[count + (init_mult * 66)] = INIT_42[init_offset +:width]; + mem[count + (init_mult * 67)] = INIT_43[init_offset +:width]; + mem[count + (init_mult * 68)] = INIT_44[init_offset +:width]; + mem[count + (init_mult * 69)] = INIT_45[init_offset +:width]; + mem[count + (init_mult * 70)] = INIT_46[init_offset +:width]; + mem[count + (init_mult * 71)] = INIT_47[init_offset +:width]; + mem[count + (init_mult * 72)] = INIT_48[init_offset +:width]; + mem[count + (init_mult * 73)] = INIT_49[init_offset +:width]; + mem[count + (init_mult * 74)] = INIT_4A[init_offset +:width]; + mem[count + (init_mult * 75)] = INIT_4B[init_offset +:width]; + mem[count + (init_mult * 76)] = INIT_4C[init_offset +:width]; + mem[count + (init_mult * 77)] = INIT_4D[init_offset +:width]; + mem[count + (init_mult * 78)] = INIT_4E[init_offset +:width]; + mem[count + (init_mult * 79)] = INIT_4F[init_offset +:width]; + mem[count + (init_mult * 80)] = INIT_50[init_offset +:width]; + mem[count + (init_mult * 81)] = INIT_51[init_offset +:width]; + mem[count + (init_mult * 82)] = INIT_52[init_offset +:width]; + mem[count + (init_mult * 83)] = INIT_53[init_offset +:width]; + mem[count + (init_mult * 84)] = INIT_54[init_offset +:width]; + mem[count + (init_mult * 85)] = INIT_55[init_offset +:width]; + mem[count + (init_mult * 86)] = INIT_56[init_offset +:width]; + mem[count + (init_mult * 87)] = INIT_57[init_offset +:width]; + mem[count + (init_mult * 88)] = INIT_58[init_offset +:width]; + mem[count + (init_mult * 89)] = INIT_59[init_offset +:width]; + mem[count + (init_mult * 90)] = INIT_5A[init_offset +:width]; + mem[count + (init_mult * 91)] = INIT_5B[init_offset +:width]; + mem[count + (init_mult * 92)] = INIT_5C[init_offset +:width]; + mem[count + (init_mult * 93)] = INIT_5D[init_offset +:width]; + mem[count + (init_mult * 94)] = INIT_5E[init_offset +:width]; + mem[count + (init_mult * 95)] = INIT_5F[init_offset +:width]; + mem[count + (init_mult * 96)] = INIT_60[init_offset +:width]; + mem[count + (init_mult * 97)] = INIT_61[init_offset +:width]; + mem[count + (init_mult * 98)] = INIT_62[init_offset +:width]; + mem[count + (init_mult * 99)] = INIT_63[init_offset +:width]; + mem[count + (init_mult * 100)] = INIT_64[init_offset +:width]; + mem[count + (init_mult * 101)] = INIT_65[init_offset +:width]; + mem[count + (init_mult * 102)] = INIT_66[init_offset +:width]; + mem[count + (init_mult * 103)] = INIT_67[init_offset +:width]; + mem[count + (init_mult * 104)] = INIT_68[init_offset +:width]; + mem[count + (init_mult * 105)] = INIT_69[init_offset +:width]; + mem[count + (init_mult * 106)] = INIT_6A[init_offset +:width]; + mem[count + (init_mult * 107)] = INIT_6B[init_offset +:width]; + mem[count + (init_mult * 108)] = INIT_6C[init_offset +:width]; + mem[count + (init_mult * 109)] = INIT_6D[init_offset +:width]; + mem[count + (init_mult * 110)] = INIT_6E[init_offset +:width]; + mem[count + (init_mult * 111)] = INIT_6F[init_offset +:width]; + mem[count + (init_mult * 112)] = INIT_70[init_offset +:width]; + mem[count + (init_mult * 113)] = INIT_71[init_offset +:width]; + mem[count + (init_mult * 114)] = INIT_72[init_offset +:width]; + mem[count + (init_mult * 115)] = INIT_73[init_offset +:width]; + mem[count + (init_mult * 116)] = INIT_74[init_offset +:width]; + mem[count + (init_mult * 117)] = INIT_75[init_offset +:width]; + mem[count + (init_mult * 118)] = INIT_76[init_offset +:width]; + mem[count + (init_mult * 119)] = INIT_77[init_offset +:width]; + mem[count + (init_mult * 120)] = INIT_78[init_offset +:width]; + mem[count + (init_mult * 121)] = INIT_79[init_offset +:width]; + mem[count + (init_mult * 122)] = INIT_7A[init_offset +:width]; + mem[count + (init_mult * 123)] = INIT_7B[init_offset +:width]; + mem[count + (init_mult * 124)] = INIT_7C[init_offset +:width]; + mem[count + (init_mult * 125)] = INIT_7D[init_offset +:width]; + mem[count + (init_mult * 126)] = INIT_7E[init_offset +:width]; + mem[count + (init_mult * 127)] = INIT_7F[init_offset +:width]; + end // if (BRAM_SIZE == 36) + end // for (count = 0; count < init_mult; count = count + 1) + + + + if (width >= 8) begin + + initp_mult = 256/widthp; + + for (countp = 0; countp < initp_mult; countp = countp + 1) begin + + initp_offset = countp * widthp; + + memp[countp] = INITP_00[initp_offset +:widthp]; + memp[countp + (initp_mult * 1)] = INITP_01[initp_offset +:widthp]; + memp[countp + (initp_mult * 2)] = INITP_02[initp_offset +:widthp]; + memp[countp + (initp_mult * 3)] = INITP_03[initp_offset +:widthp]; + memp[countp + (initp_mult * 4)] = INITP_04[initp_offset +:widthp]; + memp[countp + (initp_mult * 5)] = INITP_05[initp_offset +:widthp]; + memp[countp + (initp_mult * 6)] = INITP_06[initp_offset +:widthp]; + memp[countp + (initp_mult * 7)] = INITP_07[initp_offset +:widthp]; + + if (BRAM_SIZE == 36) begin + memp[countp + (initp_mult * 8)] = INITP_08[initp_offset +:widthp]; + memp[countp + (initp_mult * 9)] = INITP_09[initp_offset +:widthp]; + memp[countp + (initp_mult * 10)] = INITP_0A[initp_offset +:widthp]; + memp[countp + (initp_mult * 11)] = INITP_0B[initp_offset +:widthp]; + memp[countp + (initp_mult * 12)] = INITP_0C[initp_offset +:widthp]; + memp[countp + (initp_mult * 13)] = INITP_0D[initp_offset +:widthp]; + memp[countp + (initp_mult * 14)] = INITP_0E[initp_offset +:widthp]; + memp[countp + (initp_mult * 15)] = INITP_0F[initp_offset +:widthp]; + end + end // for (countp = 0; countp < initp_mult; countp = countp + 1) + end // if (width >= 8) + + end // if (INIT_FILE == "NONE") + + else begin // memory initialization from memory file + + $readmemh (INIT_FILE, tmp_mem); + + case (widest_width) + + 1, 2, 4 : for (i_mem = 0; i_mem <= mem_depth; i_mem = i_mem + 1) + mem[i_mem] = tmp_mem [i_mem]; + + 9 : for (i_mem = 0; i_mem <= mem_depth; i_mem = i_mem + 1) begin + mem[i_mem] = tmp_mem[i_mem][0 +: 8]; + memp[i_mem] = tmp_mem[i_mem][8 +: 1]; + end + + 18 : for (i_mem = 0; i_mem <= mem_depth; i_mem = i_mem + 1) begin + mem[i_mem] = tmp_mem[i_mem][0 +: 16]; + memp[i_mem] = tmp_mem[i_mem][16 +: 2]; + end + + 36 : for (i_mem = 0; i_mem <= mem_depth; i_mem = i_mem + 1) begin + mem[i_mem] = tmp_mem[i_mem][0 +: 32]; + memp[i_mem] = tmp_mem[i_mem][32 +: 4]; + end + + 72 : for (i_mem = 0; i_mem <= mem_depth; i_mem = i_mem + 1) begin + mem[i_mem] = tmp_mem[i_mem][0 +: 64]; + memp[i_mem] = tmp_mem[i_mem][64 +: 8]; + end + + endcase // case(widest_width) + + end // else: !if(INIT_FILE == "NONE") + + + case (EN_ECC_WRITE) + "TRUE" : en_ecc_write_int = 1; + "FALSE" : en_ecc_write_int = 0; + default : begin + $display("Attribute Syntax Error : The attribute EN_ECC_WRITE on RB18_INTERNAL_VLOG instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", EN_ECC_WRITE); + finish_error = 1; + end + endcase + + + case (EN_ECC_READ) + "TRUE" : en_ecc_read_int = 1; + "FALSE" : en_ecc_read_int = 0; + default : begin + $display("Attribute Syntax Error : The attribute EN_ECC_READ on RB18_INTERNAL_VLOG instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", EN_ECC_READ); + finish_error = 1; + end + endcase + + + case (RAM_MODE) + "TDP" : begin + ram_mode_int = 1; + + if (en_ecc_write_int == 1) begin + $display("DRC Error : The attribute EN_ECC_WRITE on RB18_INTERNAL_VLOG instance %m is set to %s which requires RAM_MODE = SDP.", EN_ECC_WRITE); + finish_error = 1; + end + + if (en_ecc_read_int == 1) begin + $display("DRC Error : The attribute EN_ECC_READ on RB18_INTERNAL_VLOG instance %m is set to %s which requires RAM_MODE = SDP.", EN_ECC_READ); + finish_error = 1; + end + + end // case: "TDP" + "SDP" : begin + ram_mode_int = 0; + + if ((WRITE_MODE_A != WRITE_MODE_B) || WRITE_MODE_A == "NO_CHANGE" || WRITE_MODE_A == "NO_CHANGE") begin + + $display("DRC Error : Both attributes WRITE_MODE_A and WRITE_MODE_B must be set to READ_FIRST or both attributes must be set to WRITE_FIRST when RAM_MODE = SDP on RB18_INTERNAL_VLOG instance %m."); + + finish_error = 1; + + end + + + if (BRAM_SIZE == 18) begin + if (!(WRITE_WIDTH_B == 36 || READ_WIDTH_A == 36)) begin + + $display("DRC Error : One of the attribute WRITE_WIDTH_B or READ_WIDTH_A must set to 36 when RAM_MODE = SDP."); + + finish_error = 1; + end + end + else begin + + if (!(WRITE_WIDTH_B == 72 || READ_WIDTH_A == 72)) begin + $display("DRC Error : One of the attribute WRITE_WIDTH_B or READ_WIDTH_A must set to 72 when RAM_MODE = SDP."); + finish_error = 1; + end + end // else: !if(BRAM_SIZE == 18) + + end // case: "SDP" + default : begin + $display("Attribute Syntax Error : The attribute RAM_MODE on RB18_INTERNAL_VLOG instance %m is set to %s. Legal values for this attribute are TDP or SDP.", RAM_MODE); + finish_error = 1; + end + endcase + + + case (WRITE_WIDTH_A) + + 0, 1, 2, 4, 9, 18 : ; + 36 : begin + if (BRAM_SIZE == 18 && ram_mode_int == 1) begin + $display("Attribute Syntax Error : The attribute WRITE_WIDTH_A on RB18_INTERNAL_VLOG instance %m is set to %d. Legal values for this attribute are 0, 1, 2, 4, 9 or 18.", WRITE_WIDTH_A); + finish_error = 1; + end + end + 72 : begin + if (BRAM_SIZE == 18) begin + $display("Attribute Syntax Error : The attribute WRITE_WIDTH_A on RB18_INTERNAL_VLOG instance %m is set to %d. Legal values for this attribute are 0, 1, 2, 4, 9 or 18.", WRITE_WIDTH_A); + finish_error = 1; + end + else if (BRAM_SIZE == 36 && ram_mode_int == 1) begin + $display("Attribute Syntax Error : The attribute WRITE_WIDTH_A on RB18_INTERNAL_VLOG instance %m is set to %d. Legal values for this attribute are 0, 1, 2, 4, 9, 18 or 36.", WRITE_WIDTH_A); + finish_error = 1; + end + end + default : begin + if (BRAM_SIZE == 18 && ram_mode_int == 1) begin + $display("Attribute Syntax Error : The attribute WRITE_WIDTH_A on RB18_INTERNAL_VLOG instance %m is set to %d. Legal values for this attribute are 0, 1, 2, 4, 9 or 18.", WRITE_WIDTH_A); + finish_error = 1; + end + else if (BRAM_SIZE == 36 || (BRAM_SIZE == 18 && ram_mode_int == 0)) begin + $display("Attribute Syntax Error : The attribute WRITE_WIDTH_A on RB18_INTERNAL_VLOG instance %m is set to %d. Legal values for this attribute are 0, 1, 2, 4, 9, 18 or 36.", WRITE_WIDTH_A); + finish_error = 1; + end + end + + endcase // case(WRITE_WIDTH_A) + + + case (WRITE_WIDTH_B) + + 0, 1, 2, 4, 9, 18 : ; + 36 : begin + if (BRAM_SIZE == 18 && ram_mode_int == 1) begin + $display("Attribute Syntax Error : The attribute WRITE_WIDTH_B on RB18_INTERNAL_VLOG instance %m is set to %d. Legal values for this attribute are 0, 1, 2, 4, 9 or 18.", WRITE_WIDTH_B); + finish_error = 1; + end + end + 72 : begin + if (BRAM_SIZE == 18) begin + $display("Attribute Syntax Error : The attribute WRITE_WIDTH_B on RB18_INTERNAL_VLOG instance %m is set to %d. Legal values for this attribute are 0, 1, 2, 4, 9 or 18.", WRITE_WIDTH_B); + finish_error = 1; + end + else if (BRAM_SIZE == 36 && ram_mode_int == 1) begin + $display("Attribute Syntax Error : The attribute WRITE_WIDTH_B on RB18_INTERNAL_VLOG instance %m is set to %d. Legal values for this attribute are 0, 1, 2, 4, 9, 18 or 36.", WRITE_WIDTH_B); + finish_error = 1; + end + end + default : begin + if (BRAM_SIZE == 18 && ram_mode_int == 1) begin + $display("Attribute Syntax Error : The attribute WRITE_WIDTH_B on RB18_INTERNAL_VLOG instance %m is set to %d. Legal values for this attribute are 0, 1, 2, 4, 9 or 18.", WRITE_WIDTH_B); + finish_error = 1; + end + else if (BRAM_SIZE == 36 || (BRAM_SIZE == 18 && ram_mode_int == 0)) begin + $display("Attribute Syntax Error : The attribute WRITE_WIDTH_B on RB18_INTERNAL_VLOG instance %m is set to %d. Legal values for this attribute are 0, 1, 2, 4, 9, 18 or 36.", WRITE_WIDTH_B); + finish_error = 1; + end + end + + endcase // case(WRITE_WIDTH_B) + + + case (READ_WIDTH_A) + + 0, 1, 2, 4, 9, 18 : ; + 36 : begin + if (BRAM_SIZE == 18 && ram_mode_int == 1) begin + $display("Attribute Syntax Error : The attribute READ_WIDTH_A on RB18_INTERNAL_VLOG instance %m is set to %d. Legal values for this attribute are 0, 1, 2, 4, 9 or 18.", READ_WIDTH_A); + finish_error = 1; + end + end + 72 : begin + if (BRAM_SIZE == 18) begin + $display("Attribute Syntax Error : The attribute READ_WIDTH_A on RB18_INTERNAL_VLOG instance %m is set to %d. Legal values for this attribute are 0, 1, 2, 4, 9 or 18.", READ_WIDTH_A); + finish_error = 1; + end + else if (BRAM_SIZE == 36 && ram_mode_int == 1) begin + $display("Attribute Syntax Error : The attribute READ_WIDTH_A on RB18_INTERNAL_VLOG instance %m is set to %d. Legal values for this attribute are 0, 1, 2, 4, 9, 18 or 36.", READ_WIDTH_A); + finish_error = 1; + end + end + default : begin + if (BRAM_SIZE == 18 && ram_mode_int == 1) begin + $display("Attribute Syntax Error : The attribute READ_WIDTH_A on RB18_INTERNAL_VLOG instance %m is set to %d. Legal values for this attribute are 0, 1, 2, 4, 9 or 18.", READ_WIDTH_A); + finish_error = 1; + end + else if (BRAM_SIZE == 36 || (BRAM_SIZE == 18 && ram_mode_int == 0)) begin + $display("Attribute Syntax Error : The attribute READ_WIDTH_A on RB18_INTERNAL_VLOG instance %m is set to %d. Legal values for this attribute are 0, 1, 2, 4, 9, 18 or 36.", READ_WIDTH_A); + finish_error = 1; + end + end + + endcase // case(READ_WIDTH_A) + + + case (READ_WIDTH_B) + + 0, 1, 2, 4, 9, 18 : ; + 36 : begin + if (BRAM_SIZE == 18 && ram_mode_int == 1) begin + $display("Attribute Syntax Error : The attribute READ_WIDTH_B on RB18_INTERNAL_VLOG instance %m is set to %d. Legal values for this attribute are 0, 1, 2, 4, 9 or 18.", READ_WIDTH_B); + finish_error = 1; + end + end + 72 : begin + if (BRAM_SIZE == 18) begin + $display("Attribute Syntax Error : The attribute READ_WIDTH_B on RB18_INTERNAL_VLOG instance %m is set to %d. Legal values for this attribute are 0, 1, 2, 4, 9 or 18.", READ_WIDTH_B); + finish_error = 1; + end + else if (BRAM_SIZE == 36 && ram_mode_int == 1) begin + $display("Attribute Syntax Error : The attribute READ_WIDTH_B on RB18_INTERNAL_VLOG instance %m is set to %d. Legal values for this attribute are 0, 1, 2, 4, 9, 18 or 36.", READ_WIDTH_B); + finish_error = 1; + end + end + default : begin + if (BRAM_SIZE == 18 && ram_mode_int == 1) begin + $display("Attribute Syntax Error : The attribute READ_WIDTH_B on RB18_INTERNAL_VLOG instance %m is set to %d. Legal values for this attribute are 0, 1, 2, 4, 9 or 18.", READ_WIDTH_B); + finish_error = 1; + end + else if (BRAM_SIZE == 36 || (BRAM_SIZE == 18 && ram_mode_int == 0)) begin + $display("Attribute Syntax Error : The attribute READ_WIDTH_B on RB18_INTERNAL_VLOG instance %m is set to %d. Legal values for this attribute are 0, 1, 2, 4, 9, 18 or 36.", READ_WIDTH_B); + finish_error = 1; + end + end + + endcase // case(READ_WIDTH_B) + + + if ((RAM_EXTENSION_A == "LOWER" || RAM_EXTENSION_A == "UPPER") && READ_WIDTH_A != 1) begin + $display("Attribute Syntax Error : If attribute RAM_EXTENSION_A on RB18_INTERNAL_VLOG instance %m is set to either LOWER or UPPER, then READ_WIDTH_A has to be set to 1."); + finish_error = 1; + end + + + if ((RAM_EXTENSION_A == "LOWER" || RAM_EXTENSION_A == "UPPER") && WRITE_WIDTH_A != 1) begin + $display("Attribute Syntax Error : If attribute RAM_EXTENSION_A on RB18_INTERNAL_VLOG instance %m is set to either LOWER or UPPER, then WRITE_WIDTH_A has to be set to 1."); + finish_error = 1; + end + + + if ((RAM_EXTENSION_B == "LOWER" || RAM_EXTENSION_B == "UPPER") && READ_WIDTH_B != 1) begin + $display("Attribute Syntax Error : If attribute RAM_EXTENSION_B on RB18_INTERNAL_VLOG instance %m is set to either LOWER or UPPER, then READ_WIDTH_B has to be set to 1."); + finish_error = 1; + end + + + if ((RAM_EXTENSION_B == "LOWER" || RAM_EXTENSION_B == "UPPER") && WRITE_WIDTH_B != 1) begin + $display("Attribute Syntax Error : If attribute RAM_EXTENSION_B on RB18_INTERNAL_VLOG instance %m is set to either LOWER or UPPER, then WRITE_WIDTH_B has to be set to 1."); + finish_error = 1; + end + + + if (READ_WIDTH_A == 0 && READ_WIDTH_B == 0) begin + $display("Attribute Syntax Error : Attributes READ_WIDTH_A and READ_WIDTH_B on RB18_INTERNAL_VLOG instance %m, both can not be 0."); + finish_error = 1; + end + + + case (WRITE_MODE_A) + "WRITE_FIRST" : wr_mode_a = 2'b00; + "READ_FIRST" : wr_mode_a = 2'b01; + "NO_CHANGE" : wr_mode_a = 2'b10; + default : begin + $display("Attribute Syntax Error : The Attribute WRITE_MODE_A on RB18_INTERNAL_VLOG instance %m is set to %s. Legal values for this attribute are WRITE_FIRST, READ_FIRST or NO_CHANGE.", WRITE_MODE_A); + finish_error = 1; + end + endcase + + + case (WRITE_MODE_B) + "WRITE_FIRST" : wr_mode_b = 2'b00; + "READ_FIRST" : wr_mode_b = 2'b01; + "NO_CHANGE" : wr_mode_b = 2'b10; + default : begin + $display("Attribute Syntax Error : The Attribute WRITE_MODE_B on RB18_INTERNAL_VLOG instance %m is set to %s. Legal values for this attribute are WRITE_FIRST, READ_FIRST or NO_CHANGE.", WRITE_MODE_B); + finish_error = 1; + end + endcase + + case (RAM_EXTENSION_A) + "UPPER" : cascade_a = 2'b11; + "LOWER" : cascade_a = 2'b01; + "NONE" : cascade_a = 2'b00; + default : begin + $display("Attribute Syntax Error : The attribute RAM_EXTENSION_A on RB18_INTERNAL_VLOG instance %m is set to %s. Legal values for this attribute are LOWER, NONE or UPPER.", RAM_EXTENSION_A); + finish_error = 1; + end + endcase + + + case (RAM_EXTENSION_B) + "UPPER" : cascade_b = 2'b11; + "LOWER" : cascade_b = 2'b01; + "NONE" : cascade_b = 2'b00; + default : begin + $display("Attribute Syntax Error : The attribute RAM_EXTENSION_B on RB18_INTERNAL_VLOG instance %m is set to %s. Legal values for this attribute are LOWER, NONE or UPPER.", RAM_EXTENSION_B); + finish_error = 1; + end + endcase + + + if ((SIM_COLLISION_CHECK != "ALL") && (SIM_COLLISION_CHECK != "NONE") && (SIM_COLLISION_CHECK != "WARNING_ONLY") && (SIM_COLLISION_CHECK != "GENERATE_X_ONLY")) begin + + $display("Attribute Syntax Error : The attribute SIM_COLLISION_CHECK on RB18_INTERNAL_VLOG instance %m is set to %s. Legal values for this attribute are ALL, NONE, WARNING_ONLY or GENERATE_X_ONLY.", SIM_COLLISION_CHECK); + finish_error = 1; + + end + + + case (RSTREG_PRIORITY_A) + "RSTREG" : rstreg_priority_a_int = 1; + "REGCE" : rstreg_priority_a_int = 0; + default : begin + $display("Attribute Syntax Error : The attribute RSTREG_PRIORITY_A on RB18_INTERNAL_VLOG instance %m is set to %s. Legal values for this attribute are RSTREG or REGCE.", RSTREG_PRIORITY_A); + finish_error = 1; + end + endcase + + + case (RSTREG_PRIORITY_B) + "RSTREG" : rstreg_priority_b_int = 1; + "REGCE" : rstreg_priority_b_int = 0; + default : begin + $display("Attribute Syntax Error : The attribute RSTREG_PRIORITY_B on RB18_INTERNAL_VLOG instance %m is set to %s. Legal values for this attribute are RSTREG or REGCE.", RSTREG_PRIORITY_B); + finish_error = 1; + end + endcase + + + if ((en_ecc_write_int == 1 || en_ecc_read_int == 1) && (WRITE_WIDTH_B != 72 || READ_WIDTH_A != 72)) begin + $display("DRC Error : Attributes WRITE_WIDTH_B and READ_WIDTH_A have to be set to 72 on RB18_INTERNAL_VLOG instance %m when either attribute EN_ECC_WRITE or EN_ECC_READ is set to TRUE."); + finish_error = 1; + end + + + case (RDADDR_COLLISION_HWCONFIG) + "DELAYED_WRITE" : rdaddr_collision_hwconfig_int = 0; + "PERFORMANCE" : rdaddr_collision_hwconfig_int = 1; + default : begin + $display("Attribute Syntax Error : The attribute RDADDR_COLLISION_HWCONFIG on RB18_INTERNAL_VLOG instance %m is set to %s. Legal values for this attribute are DELAYED_WRITE or PERFORMANCE.", RDADDR_COLLISION_HWCONFIG); + finish_error = 1; + end + endcase + + + if (finish_error == 1) + $finish; + + + end // initial begin + + + // GSR + always @(gsr_in) + if (gsr_in) begin + + assign doa_out = INIT_A[0 +: ra_width]; + + if (ra_width >= 8) begin + assign dopa_out = INIT_A[ra_width +: ra_widthp]; + end + + assign dob_out = INIT_B[0 +: rb_width]; + + if (rb_width >= 8) begin + assign dopb_out = INIT_B[rb_width +: rb_widthp]; + end + + assign dbiterr_out = 0; + assign sbiterr_out = 0; + assign rdaddrecc_out = 9'b0; + + end + else begin + deassign doa_out; + deassign dopa_out; + deassign dob_out; + deassign dopb_out; + deassign dbiterr_out; + deassign sbiterr_out; + deassign rdaddrecc_out; + + end + + + // registering signals + always @(posedge clka_in) begin + + rising_clka = 1; + + if (ena_in === 1'b1) begin + time_port_a = $time; + addra_reg = addra_in; + wea_reg = wea_in; + dia_reg = dia_in; + dipa_reg = dipa_in; + col_addra_reconstruct_reg = col_addra_reconstruct; + end + + end + + always @(posedge clkb_in) begin + + rising_clkb = 1; + + if (enb_in === 1'b1) begin + time_port_b = $time; + addrb_reg = addrb_in; + web_reg = web_in; + enb_reg = enb_in; + dib_reg = dib_in; + dipb_reg = dipb_in; + col_addrb_reconstruct_reg = col_addrb_reconstruct; + end + + end // always @ (posedge clkb_in) + + + // CLKA and CLKB + always @(posedge rising_clka or posedge rising_clkb) begin + + // Registering addr[15] for cascade mode + if (rising_clka) + if (cascade_a[1]) + addra_in_15_reg_bram = ~addra_in[15]; + else + addra_in_15_reg_bram = addra_in[15]; + + if (rising_clkb) + if (cascade_b[1]) + addrb_in_15_reg_bram = ~addrb_in[15]; + else + addrb_in_15_reg_bram = addrb_in[15]; + + if ((cascade_a == 2'b00 || (addra_in_15_reg_bram == 1'b0 && cascade_a != 2'b00)) && (cascade_b == 2'b00 || (addrb_in_15_reg_bram == 1'b0 && cascade_b != 2'b00))) begin + +/************************************* Collision starts *****************************************/ + + if (SIM_COLLISION_CHECK != "NONE") begin + + if (gsr_in === 1'b0) begin + + if (time_port_a > time_port_b) begin + + if (time_port_a - time_port_b <= 100) begin + viol_time = 1; + end + else if (time_port_a - time_port_b <= SETUP_READ_FIRST) begin + viol_time = 2; + end + end + else begin + + if (time_port_b - time_port_a <= 100) begin + viol_time = 1; + end + else if (time_port_b - time_port_a <= SETUP_READ_FIRST) begin + viol_time = 2; + end + + end // else: !if(time_port_a > time_port_b) + + + if (ena_in === 1'b0 || enb_in === 1'b0) + viol_time = 0; + + + if ((WRITE_WIDTH_A <= 9 && wea_in[0] === 1'b0) || (WRITE_WIDTH_A == 18 && wea_in[1:0] === 2'b00) || ((WRITE_WIDTH_A == 36 || WRITE_WIDTH_A == 72) && wea_in[3:0] === 4'b0000)) + if ((WRITE_WIDTH_B <= 9 && web_in[0] === 1'b0) || (WRITE_WIDTH_B == 18 && web_in[1:0] === 2'b00) || (WRITE_WIDTH_B == 36 && web_in[3:0] === 4'b0000) || (WRITE_WIDTH_B == 72 && web_in[7:0] === 8'h00)) + viol_time = 0; + + + if (viol_time != 0) begin + + // Clka and clkb rise at the same time + if ((rising_clka && rising_clkb) || viol_time == 1) begin + if (col_addra_reconstruct[15:col_addr_lsb] === col_addrb_reconstruct[15:col_addr_lsb]) begin + + viol_type = 2'b01; + + task_rd_ram_a (addra_in, doa_buf, dopa_buf); + task_rd_ram_b (addrb_in, dob_buf, dopb_buf); + + task_col_wr_ram_a (2'b00, web_in, wea_in, di_x, di_x[7:0], addrb_in, addra_in); + task_col_wr_ram_b (2'b00, wea_in, web_in, di_x, di_x[7:0], addra_in, addrb_in); + + task_col_rd_ram_a (2'b01, web_in, wea_in, addra_in, doa_buf, dopa_buf); + task_col_rd_ram_b (2'b01, wea_in, web_in, addrb_in, dob_buf, dopb_buf); + + task_col_wr_ram_a (2'b10, web_in, wea_in, dia_in, dipa_in, addrb_in, addra_in); + + + // injecting error + dib_ecc_col = dib_in; + + + if (injectdbiterr_in === 1) begin + dib_ecc_col[30] = ~dib_ecc_col[30]; + dib_ecc_col[62] = ~dib_ecc_col[62]; + end + else if (injectsbiterr_in === 1) begin + dib_ecc_col[30] = ~dib_ecc_col[30]; + end + + + if (ram_mode_int == 0 && en_ecc_write_int == 1 && enb_in === 1'b1) begin + + dip_ecc_col = fn_dip_ecc(1'b1, dib_in, dipb_in); + eccparity_out = dip_ecc_col; + task_col_wr_ram_b (2'b10, wea_in, web_in, dib_ecc_col, dip_ecc_col, addra_in, addrb_in); + + end + else + task_col_wr_ram_b (2'b10, wea_in, web_in, dib_ecc_col, dipb_in, addra_in, addrb_in); + + + if (wr_mode_a != 2'b01) + task_col_rd_ram_a (2'b11, web_in, wea_in, addra_in, doa_buf, dopa_buf); + if (wr_mode_b != 2'b01) + task_col_rd_ram_b (2'b11, wea_in, web_in, addrb_in, dob_buf, dopb_buf); + + + if (rdaddr_collision_hwconfig_int == 1 && (wr_mode_a == 2'b01 || wr_mode_b == 2'b01)) begin + task_col_wr_ram_a (2'b10, web_in, wea_in, di_x, di_x[7:0], addrb_in, addra_in); + task_col_wr_ram_b (2'b10, wea_in, web_in, di_x, di_x[7:0], addra_in, addrb_in); + end + + + if (ram_mode_int == 0 && en_ecc_read_int == 1) + task_col_ecc_read (doa_buf, dopa_buf, addra_in); + + + end // if (addra_in[15:col_addr_lsb] === addrb_in[15:col_addr_lsb]) + else + viol_time = 0; + + end // if (rising_clka && rising_clkb) + // Clkb before clka + else if (rising_clka && !rising_clkb) begin + if (col_addra_reconstruct[15:col_addr_lsb] === col_addrb_reconstruct_reg[15:col_addr_lsb]) begin + + viol_type = 2'b10; + + task_rd_ram_a (addra_in, doa_buf, dopa_buf); + + task_col_wr_ram_a (2'b00, web_reg, wea_in, di_x, di_x[7:0], addrb_reg, addra_in); + task_col_wr_ram_b (2'b00, wea_in, web_reg, di_x, di_x[7:0], addra_in, addrb_reg); + + task_col_rd_ram_a (2'b01, web_reg, wea_in, addra_in, doa_buf, dopa_buf); + task_col_rd_ram_b (2'b01, wea_in, web_reg, addrb_reg, dob_buf, dopb_buf); + + task_col_wr_ram_a (2'b10, web_reg, wea_in, dia_in, dipa_in, addrb_reg, addra_in); + + + // injecting error + dib_ecc_col = dib_reg; + + + if (injectdbiterr_in === 1) begin + dib_ecc_col[30] = ~dib_ecc_col[30]; + dib_ecc_col[62] = ~dib_ecc_col[62]; + end + else if (injectsbiterr_in === 1) begin + dib_ecc_col[30] = ~dib_ecc_col[30]; + end + + + if (ram_mode_int == 0 && en_ecc_write_int == 1 && enb_reg === 1'b1) begin + + dip_ecc_col = fn_dip_ecc(1'b1, dib_reg, dipb_reg); + eccparity_out = dip_ecc_col; + task_col_wr_ram_b (2'b10, wea_in, web_reg, dib_ecc_col, dip_ecc_col, addra_in, addrb_reg); + + end + else + task_col_wr_ram_b (2'b10, wea_in, web_reg, dib_ecc_col, dipb_reg, addra_in, addrb_reg); + + + if (wr_mode_a != 2'b01) + task_col_rd_ram_a (2'b11, web_reg, wea_in, addra_in, doa_buf, dopa_buf); + if (wr_mode_b != 2'b01) + task_col_rd_ram_b (2'b11, wea_in, web_reg, addrb_reg, dob_buf, dopb_buf); + + + if (wr_mode_a == 2'b01 || wr_mode_b == 2'b01) begin + task_col_wr_ram_a (2'b10, web_reg, wea_in, di_x, di_x[7:0], addrb_reg, addra_in); + task_col_wr_ram_b (2'b10, wea_in, web_reg, di_x, di_x[7:0], addra_in, addrb_reg); + end + + + if (ram_mode_int == 0 && en_ecc_read_int == 1) + task_col_ecc_read (doa_buf, dopa_buf, addra_in); + + + end // if (addra_in[15:col_addr_lsb] === addrb_reg[15:col_addr_lsb]) + else + viol_time = 0; + + end // if (rising_clka && !rising_clkb) + // Clka before clkb + else if (!rising_clka && rising_clkb) begin + if (col_addra_reconstruct_reg[15:col_addr_lsb] === col_addrb_reconstruct[15:col_addr_lsb]) begin + + viol_type = 2'b11; + + task_rd_ram_b (addrb_in, dob_buf, dopb_buf); + + task_col_wr_ram_a (2'b00, web_in, wea_reg, di_x, di_x[7:0], addrb_in, addra_reg); + task_col_wr_ram_b (2'b00, wea_reg, web_in, di_x, di_x[7:0], addra_reg, addrb_in); + + task_col_rd_ram_a (2'b01, web_in, wea_reg, addra_reg, doa_buf, dopa_buf); + task_col_rd_ram_b (2'b01, wea_reg, web_in, addrb_in, dob_buf, dopb_buf); + + task_col_wr_ram_a (2'b10, web_in, wea_reg, dia_reg, dipa_reg, addrb_in, addra_reg); + + + // injecting error + dib_ecc_col = dib_in; + + + if (injectdbiterr_in === 1) begin + dib_ecc_col[30] = ~dib_ecc_col[30]; + dib_ecc_col[62] = ~dib_ecc_col[62]; + end + else if (injectsbiterr_in === 1) begin + dib_ecc_col[30] = ~dib_ecc_col[30]; + end + + + if (ram_mode_int == 0 && en_ecc_write_int == 1 && enb_in === 1'b1) begin + + dip_ecc_col = fn_dip_ecc(1'b1, dib_in, dipb_in); + eccparity_out = dip_ecc_col; + task_col_wr_ram_b (2'b10, wea_reg, web_in, dib_ecc_col, dip_ecc_col, addra_reg, addrb_in); + + end + else + task_col_wr_ram_b (2'b10, wea_reg, web_in, dib_ecc_col, dipb_in, addra_reg, addrb_in); + + + if (wr_mode_a != 2'b01) + task_col_rd_ram_a (2'b11, web_in, wea_reg, addra_reg, doa_buf, dopa_buf); + if (wr_mode_b != 2'b01) + task_col_rd_ram_b (2'b11, wea_reg, web_in, addrb_in, dob_buf, dopb_buf); + + + if (wr_mode_a == 2'b01 || wr_mode_b == 2'b01) begin + task_col_wr_ram_a (2'b10, web_in, wea_reg, di_x, di_x[7:0], addrb_in, addra_reg); + task_col_wr_ram_b (2'b10, wea_reg, web_in, di_x, di_x[7:0], addra_reg, addrb_in); + end + + + if (ram_mode_int == 0 && en_ecc_read_int == 1) + task_col_ecc_read (doa_buf, dopa_buf, addra_reg); + + + end // if (addra_reg[15:col_addr_lsb] === addrb_in[15:col_addr_lsb]) + else + viol_time = 0; + + end + + end // if (viol_time != 0) + end // if (gsr_in === 1'b0) + + if (SIM_COLLISION_CHECK == "WARNING_ONLY") + viol_time = 0; + + end // if (SIM_COLLISION_CHECK != "NONE") + + +/*************************************** end collision ********************************/ + + end // if ((cascade_a == 2'b00 || (addra_in_15_reg_bram == 1'b0 && cascade_a != 2'b00)) && (cascade_b == 2'b00 || (addrb_in_15_reg_bram == 1'b0 && cascade_b != 2'b00))) + + +/**************************** Port A ****************************************/ + if (rising_clka) begin + + // DRC + if (rstrama_in === 1 && ram_mode_int == 0 && (en_ecc_write_int == 1 || en_ecc_read_int == 1)) + $display("DRC Warning : SET/RESET (RSTRAM) is not supported in ECC mode on RB18_INTERNAL_VLOG instance %m."); + + // end DRC + + + // registering addra_in[15] the second time + if (regcea_in) + addra_in_15_reg1 = addra_in_15_reg; + + + if (ena_in && (wr_mode_a != 2'b10 || wea_in[0] == 0 || rstrama_in == 1'b1)) + if (cascade_a[1]) + addra_in_15_reg = ~addra_in[15]; + else + addra_in_15_reg = addra_in[15]; + + + if (gsr_in == 1'b0 && ena_in == 1'b1 && (cascade_a == 2'b00 || (addra_in_15_reg_bram == 1'b0 && cascade_a != 2'b00))) begin + + // SRVAL + if (rstrama_in === 1'b1) begin + + doa_buf = SRVAL_A[0 +: ra_width]; + doa_out = SRVAL_A[0 +: ra_width]; + + if (ra_width >= 8) begin + dopa_buf = SRVAL_A[ra_width +: ra_widthp]; + dopa_out = SRVAL_A[ra_width +: ra_widthp]; + end + end + + + if (viol_time == 0) begin + + // Read first + if (wr_mode_a == 2'b01 || (ram_mode_int == 0 && en_ecc_read_int == 1)) begin + task_rd_ram_a (addra_in, doa_buf, dopa_buf); + + + // ECC decode + if (ram_mode_int == 0 && en_ecc_read_int == 1) begin + + dopr_ecc = fn_dip_ecc(1'b0, doa_buf, dopa_buf); + + syndrome = dopr_ecc ^ dopa_buf; + + if (syndrome !== 0) begin + + if (syndrome[7]) begin // dectect single bit error + + ecc_bit_position = {doa_buf[63:57], dopa_buf[6], doa_buf[56:26], dopa_buf[5], doa_buf[25:11], dopa_buf[4], doa_buf[10:4], dopa_buf[3], doa_buf[3:1], dopa_buf[2], doa_buf[0], dopa_buf[1:0], dopa_buf[7]}; + + if (syndrome[6:0] > 71) begin + $display ("DRC Error : Simulation halted due Corrupted DIP. To correct this problem, make sure that reliable data is fed to the DIP. The correct Parity must be generated by a Hamming code encoder or encoder in the Block RAM. The output from the model is unreliable if there are more than 2 bit errors. The model doesn't warn if there is sporadic input of more than 2 bit errors due to the limitation in Hamming code."); + $finish; + end + + ecc_bit_position[syndrome[6:0]] = ~ecc_bit_position[syndrome[6:0]]; // correct single bit error in the output + + dia_in_ecc_corrected = {ecc_bit_position[71:65], ecc_bit_position[63:33], ecc_bit_position[31:17], ecc_bit_position[15:9], ecc_bit_position[7:5], ecc_bit_position[3]}; // correct single bit error in the memory + + doa_buf = dia_in_ecc_corrected; + + dipa_in_ecc_corrected = {ecc_bit_position[0], ecc_bit_position[64], ecc_bit_position[32], ecc_bit_position[16], ecc_bit_position[8], ecc_bit_position[4], ecc_bit_position[2:1]}; // correct single bit error in the parity memory + + dopa_buf = dipa_in_ecc_corrected; + + dbiterr_out <= 0; + sbiterr_out <= 1; + + end + else if (!syndrome[7]) begin // double bit error + sbiterr_out <= 0; + dbiterr_out <= 1; + + end + end // if (syndrome !== 0) + else begin + dbiterr_out <= 0; + sbiterr_out <= 0; + + end // else: !if(syndrome !== 0) + + + // output of rdaddrecc + rdaddrecc_out[8:0] <= addra_in[14:6]; + + end // if (ram_mode_int == 0 && en_ecc_read_int == 1) + end // if (wr_mode_a == 2'b01) + + + // Write + task_wr_ram_a (wea_in, dia_in, dipa_in, addra_in); + + // Read if not read first + if (wr_mode_a != 2'b01 && !(ram_mode_int == 0 && en_ecc_read_int == 1)) + task_rd_ram_a (addra_in, doa_buf, dopa_buf); + + end // if (viol_time == 0) + + end // if (gsr_in == 1'b0 && ena_in == 1'b1 && (cascade_a == 2'b00 || (addra_in_15_reg_bram == 1'b0 && cascade_a != 2'b00))) + + end // if (rising_clka) + // end of port A + + +/************************************** port B ***************************************************************/ + if (rising_clkb) begin + + // DRC + if (rstramb_in === 1 && ram_mode_int == 0 && (en_ecc_write_int == 1 || en_ecc_read_int == 1)) + $display("DRC Warning : SET/RESET (RSTRAM) is not supported in ECC mode on RB18_INTERNAL_VLOG instance %m."); + + if (!(en_ecc_write_int == 1 || en_ecc_read_int == 1)) begin + + if (injectsbiterr_in === 1) + $display("DRC Warning : INJECTSBITERR is not supported when neither EN_ECC_WRITE nor EN_ECC_READ = TRUE on RB18_INTERNAL_VLOG instance %m."); + + if (injectdbiterr_in === 1) + $display("DRC Warning : INJECTDBITERR is not supported when neither EN_ECC_WRITE nor EN_ECC_READ = TRUE on RB18_INTERNAL_VLOG instance %m."); + + end + // End DRC + + + if (regceb_in) + addrb_in_15_reg1 = addrb_in_15_reg; + + + if (enb_in && (wr_mode_b != 2'b10 || web_in[0] == 0 || rstramb_in == 1'b1)) + if (cascade_b[1]) + addrb_in_15_reg = ~addrb_in[15]; + else + addrb_in_15_reg = addrb_in[15]; + + + if (gsr_in == 1'b0 && enb_in == 1'b1 && (cascade_b == 2'b00 || (addrb_in_15_reg_bram == 1'b0 && cascade_b != 2'b00))) begin + + // SRVAL + if (rstramb_in === 1'b1) begin + + dob_buf = SRVAL_B[0 +: rb_width]; + dob_out = SRVAL_B[0 +: rb_width]; + + if (rb_width >= 8) begin + dopb_buf = SRVAL_B[rb_width +: rb_widthp]; + dopb_out = SRVAL_B[rb_width +: rb_widthp]; + end + end + + + if (viol_time == 0) begin + + // ECC encode + if (ram_mode_int == 0 && en_ecc_write_int == 1) begin + dip_ecc = fn_dip_ecc(1'b1, dib_in, dipb_in); + eccparity_out = dip_ecc; + dipb_in_ecc = dip_ecc; + end + else + dipb_in_ecc = dipb_in; + + + dib_in_ecc = dib_in; + + + // injecting error + if (injectdbiterr_in === 1) begin // double bit + dib_in_ecc[30] = ~dib_in_ecc[30]; + dib_in_ecc[62] = ~dib_in_ecc[62]; + end + else if (injectsbiterr_in === 1) begin // single bit + dib_in_ecc[30] = ~dib_in_ecc[30]; + end + + + // Read first + if (wr_mode_b == 2'b01 && rstramb_in === 1'b0) + task_rd_ram_b (addrb_in, dob_buf, dopb_buf); + + + // Write + task_wr_ram_b (web_in, dib_in_ecc, dipb_in_ecc, addrb_in); + + + // Read if not read first + if (wr_mode_b != 2'b01 && rstramb_in === 1'b0) + task_rd_ram_b (addrb_in, dob_buf, dopb_buf); + + end // if (viol_time == 0) + + + end // if (gsr_in == 1'b0 && enb_in == 1'b1 && (cascade_b == 2'b00 || addrb_in_15_reg_bram == 1'b0)) + + end // if (rising_clkb) + // end of port B + + + if (gsr_in == 1'b0) begin + + // writing outputs of port A + if (ena_in && (rising_clka || viol_time != 0)) begin + + if (rstrama_in === 1'b0 && (wr_mode_a != 2'b10 || (WRITE_WIDTH_A <= 9 && wea_in[0] === 1'b0) || (WRITE_WIDTH_A == 18 && wea_in[1:0] === 2'b00) || ((WRITE_WIDTH_A == 36 || WRITE_WIDTH_A == 72) && wea_in[3:0] === 4'b0000))) begin + + doa_out <= doa_buf; + + if (ra_width >= 8) + dopa_out <= dopa_buf; + + end + + end + + + // writing outputs of port B + if (enb_in && (rising_clkb || viol_time != 0)) begin + + if (rstramb_in === 1'b0 && (wr_mode_b != 2'b10 || (WRITE_WIDTH_B <= 9 && web_in[0] === 1'b0) || (WRITE_WIDTH_B == 18 && web_in[1:0] === 2'b00) || (WRITE_WIDTH_B == 36 && web_in[3:0] === 4'b0000) || (WRITE_WIDTH_B == 72 && web_in[7:0] === 8'h00))) begin + + dob_out <= dob_buf; + + if (rb_width >= 8) + dopb_out <= dopb_buf; + + end + + end + + end // if (gsr_in == 1'b0) + + + viol_time = 0; + rising_clka = 0; + rising_clkb = 0; + viol_type = 2'b00; + col_wr_wr_msg = 1; + col_wra_rdb_msg = 1; + col_wrb_rda_msg = 1; + + end // always @ (posedge rising_clka or posedge rising_clkb) + + + // ********* Cascade Port A ******** + always @(posedge clka_in or cascadeina_in or addra_in_15_reg or doa_out or dopa_out) begin + + if (cascade_a[1] == 1'b1 && addra_in_15_reg == 1'b1) begin + doa_out_mux[0] = cascadeina_in; + end + else begin + doa_out_mux = doa_out; + + if (ra_width >= 8) + dopa_out_mux = dopa_out; + + end + + end + + // output register mode + always @(posedge clka_in or cascadeina_in or addra_in_15_reg1 or doa_outreg or dopa_outreg) begin + + if (cascade_a[1] == 1'b1 && addra_in_15_reg1 == 1'b1) begin + doa_outreg_mux[0] = cascadeina_in; + end + else begin + doa_outreg_mux = doa_outreg; + + if (ra_width >= 8) + dopa_outreg_mux = dopa_outreg; + + end + + end + + + // ********* Cascade Port B ******** + always @(posedge clkb_in or cascadeinb_in or addrb_in_15_reg or dob_out or dopb_out) begin + + if (cascade_b[1] == 1'b1 && addrb_in_15_reg == 1'b1) begin + dob_out_mux[0] = cascadeinb_in; + end + else begin + dob_out_mux = dob_out; + + if (rb_width >= 8) + dopb_out_mux = dopb_out; + + end + + end + + // output register mode + always @(posedge clkb_in or cascadeinb_in or addrb_in_15_reg1 or dob_outreg or dopb_outreg) begin + + if (cascade_b[1] == 1'b1 && addrb_in_15_reg1 == 1'b1) begin + dob_outreg_mux[0] = cascadeinb_in; + end + else begin + dob_outreg_mux = dob_outreg; + + if (rb_width >= 8) + dopb_outreg_mux = dopb_outreg; + + end + + end // always @ (posedge regclkb_in or cascadeinregb_in or addrb_in_15_reg1 or dob_outreg or dopb_outreg) + + + // ***** Output Registers **** Port A ***** + always @(posedge clka_in or posedge gsr_in) begin + + if (DOA_REG == 1) begin + + if (gsr_in == 1'b1) begin + + rdaddrecc_outreg <= 9'b0; + dbiterr_outreg <= 0; + sbiterr_outreg <= 0; + doa_outreg <= INIT_A[0 +: ra_width]; + + if (ra_width >= 8) + dopa_outreg <= INIT_A[ra_width +: ra_widthp]; + + end + else if (gsr_in == 1'b0) begin + + if (regcea_in === 1'b1) begin + dbiterr_outreg <= dbiterr_out; + sbiterr_outreg <= sbiterr_out; + rdaddrecc_outreg <= rdaddrecc_out; + end + + + if (rstreg_priority_a_int == 0) begin // Virtex5 behavior + + if (regcea_in == 1'b1) begin + if (rstrega_in == 1'b1) begin + + doa_outreg <= SRVAL_A[0 +: ra_width]; + + if (ra_width >= 8) + dopa_outreg <= SRVAL_A[ra_width +: ra_widthp]; + + end + else if (rstrega_in == 1'b0) begin + + doa_outreg <= doa_out; + + if (ra_width >= 8) + dopa_outreg <= dopa_out; + + end + end // if (regcea_in == 1'b1) + + end // if (rstreg_priority_a_int == 1'b0) + else begin + + if (rstrega_in == 1'b1) begin + + doa_outreg <= SRVAL_A[0 +: ra_width]; + + if (ra_width >= 8) + dopa_outreg <= SRVAL_A[ra_width +: ra_widthp]; + + end + + else if (rstrega_in == 1'b0) begin + + if (regcea_in == 1'b1) begin + + doa_outreg <= doa_out; + + if (ra_width >= 8) + dopa_outreg <= dopa_out; + + end + end + end // else: !if(rstreg_priority_a_int == 1'b0) + + end // if (gsr_in == 1'b0) + + end // if (DOA_REG == 1) + + end // always @ (posedge clka_in or posedge gsr_in) + + + always @(temp_wire or doa_out_mux or dopa_out_mux or doa_outreg_mux or dopa_outreg_mux or dbiterr_out or dbiterr_outreg or sbiterr_out or sbiterr_outreg or rdaddrecc_out or rdaddrecc_outreg) begin + + case (DOA_REG) + + 0 : begin + dbiterr_out_out = dbiterr_out; + sbiterr_out_out = sbiterr_out; + rdaddrecc_out_out = rdaddrecc_out; + doa_out_out[0 +: ra_width] = doa_out_mux[0 +: ra_width]; + + if (ra_width >= 8) + dopa_out_out[0 +: ra_widthp] = dopa_out_mux[0 +: ra_widthp]; + + end + 1 : begin + dbiterr_out_out = dbiterr_outreg; + sbiterr_out_out = sbiterr_outreg; + doa_out_out[0 +: ra_width] = doa_outreg_mux[0 +: ra_width]; + rdaddrecc_out_out = rdaddrecc_outreg; + + if (ra_width >= 8) + dopa_out_out[0 +: ra_widthp] = dopa_outreg_mux[0 +: ra_widthp]; + + end + default : begin + $display("Attribute Syntax Error : The attribute DOA_REG on RB18_INTERNAL_VLOG instance %m is set to %2d. Legal values for this attribute are 0 or 1.", DOA_REG); + $finish; + end + + endcase + + end // always @ (doa_out_mux or dopa_out_mux or doa_outreg_mux or dopa_outreg_mux or dbiterr_out or dbiterr_outreg or sbiterr_out or sbiterr_outreg) + + +// ***** Output Registers **** Port B ***** + always @(posedge clkb_in or posedge gsr_in) begin + + if (DOB_REG == 1) begin + + if (gsr_in == 1'b1) begin + + dob_outreg <= INIT_B[0 +: rb_width]; + + if (rb_width >= 8) + dopb_outreg <= INIT_B[rb_width +: rb_widthp]; + + end + else if (gsr_in == 1'b0) begin + + if (rstreg_priority_b_int == 0) begin // Virtex5 behavior + + if (regceb_in == 1'b1) begin + if (rstregb_in == 1'b1) begin + + dob_outreg <= SRVAL_B[0 +: rb_width]; + + if (rb_width >= 8) + dopb_outreg <= SRVAL_B[rb_width +: rb_widthp]; + + end + else if (rstregb_in == 1'b0) begin + + dob_outreg <= dob_out; + + if (rb_width >= 8) + dopb_outreg <= dopb_out; + + end + end // if (regceb_in == 1'b1) + + end // if (rstreg_priority_b_int == 1'b0) + else begin + + if (rstregb_in == 1'b1) begin + + dob_outreg <= SRVAL_B[0 +: rb_width]; + + if (rb_width >= 8) + dopb_outreg <= SRVAL_B[rb_width +: rb_widthp]; + + end + + else if (rstregb_in == 1'b0) begin + + if (regceb_in == 1'b1) begin + + dob_outreg <= dob_out; + + if (rb_width >= 8) + dopb_outreg <= dopb_out; + + end + end + end // else: !if(rstreg_priority_b_int == 1'b0) + + end // if (gsr_in == 1'b0) + + end // if (DOB_REG == 1) + + end // always @ (posedge clkb_in or posedge gsr_in) + + + always @(temp_wire or dob_out_mux or dopb_out_mux or dob_outreg_mux or dopb_outreg_mux) begin + + case (DOB_REG) + + 0 : begin + dob_out_out[0 +: rb_width] = dob_out_mux[0 +: rb_width]; + + if (rb_width >= 8) + dopb_out_out[0 +: rb_widthp] = dopb_out_mux[0 +: rb_widthp]; + end + 1 : begin + dob_out_out[0 +: rb_width] = dob_outreg_mux[0 +: rb_width]; + + if (rb_width >= 8) + dopb_out_out[0 +: rb_widthp] = dopb_outreg_mux[0 +: rb_widthp]; + + end + default : begin + $display("Attribute Syntax Error : The attribute DOB_REG on RB18_INTERNAL_VLOG instance %m is set to %2d. Legal values for this attribute are 0 or 1.", DOB_REG); + $finish; + end + + endcase + + end // always @ (dob_out_mux or dopb_out_mux or dob_outreg_mux or dopb_outreg_mux) + + +endmodule // RB18_INTERNAL_VLOG + +// end of RB18_INTERNAL_VLOG - Note: Not an user primitive diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/RAMB18SDP.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/RAMB18SDP.v new file mode 100644 index 0000000..5fc6fbc --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/RAMB18SDP.v @@ -0,0 +1,273 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/rainier/RAMB18SDP.v,v 1.15 2007/06/15 20:58:40 wloo Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2005 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / 16K-Bit Data and 2K-Bit Parity Block RAM +// /___/ /\ Filename : RAMB18SDP.v +// \ \ / \ Timestamp : Tues July 26 16:43:59 PST 2005 +// \___\/\___\ +// +// Revision: +// 07/26/05 - Initial version. +// 01/04/07 - Added support of memory file to initialize memory and parity (CR 431584). +// 03/14/07 - Removed attribute INITP_FILE (CR 436003). +// 04/03/07 - Changed INIT_FILE = "NONE" as default (CR 436812). +// 06/13/07 - Added high performace version of the model. +// End Revision + +`timescale 1 ps/1 ps + +module RAMB18SDP (DO, DOP, + DI, DIP, RDADDR, RDCLK, RDEN, REGCE, SSR, WE, WRADDR, WRCLK, WREN); + + parameter integer DO_REG = 0; + parameter INIT = 36'h0; + parameter INITP_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_FILE = "NONE"; + parameter SIM_COLLISION_CHECK = "ALL"; + parameter SIM_MODE = "SAFE"; + parameter SRVAL = 36'h0; + + localparam SETUP_ALL = 1000; + localparam SETUP_READ_FIRST = 3000; + + output [31:0] DO; + output [3:0] DOP; + + input RDCLK; + input RDEN; + input REGCE; + input SSR; + input WRCLK; + input WREN; + input [8:0] WRADDR; + input [8:0] RDADDR; + input [31:0] DI; + input [3:0] DIP; + input [3:0] WE; + + tri0 GSR = glbl.GSR; + + wire [7:0] dangle_out8; + wire dangle_out; + wire [3:0] dangle_out4; + wire [31:0] dangle_out32; + + ARAMB36_INTERNAL INT_RAMB (.DIA(64'b0), .ENA(RDEN), .WEA(8'b0), .SSRA(SSR), .ADDRA({2'b0, RDADDR, 5'b0}), .CLKA(RDCLK), .DOA({dangle_out32,DO}), .DIB({32'b0,DI}), .ENB(WREN), .WEB({2{WE}}), .SSRB(1'b0), .ADDRB({2'b0, WRADDR, 5'b0}), .CLKB(WRCLK), .DOB(dangle_out32), .GSR(GSR), .DOPA({dangle_out4,DOP}), .DOPB(dangle_out4), .DIPA(4'b0), .DIPB({4'b0,DIP}), .CASCADEOUTLATA(dangle_out), .CASCADEOUTLATB(dangle_out), .CASCADEOUTREGA(dangle_out), .CASCADEOUTREGB(dangle_out), .CASCADEINLATA(1'b0), .CASCADEINLATB(1'b0), .CASCADEINREGA(1'b0), .CASCADEINREGB(1'b0), .REGCEA(REGCE), .REGCEB(1'b0), .REGCLKA(RDCLK), .REGCLKB(1'b0), .DBITERR(dangle_out), .ECCPARITY(dangle_out8), .SBITERR(dangle_out)); + + defparam INT_RAMB.SIM_MODE = SIM_MODE; + defparam INT_RAMB.BRAM_MODE = "SIMPLE_DUAL_PORT"; + defparam INT_RAMB.BRAM_SIZE = 18; + defparam INT_RAMB.INIT_A = INIT; + defparam INT_RAMB.INIT_B = INIT; + defparam INT_RAMB.INIT_FILE = INIT_FILE; + defparam INT_RAMB.SRVAL_A = SRVAL; + defparam INT_RAMB.SRVAL_B = SRVAL; + defparam INT_RAMB.READ_WIDTH_A = 36; + defparam INT_RAMB.READ_WIDTH_B = 36; + defparam INT_RAMB.WRITE_WIDTH_A = 36; + defparam INT_RAMB.WRITE_WIDTH_B = 36; + defparam INT_RAMB.WRITE_MODE_A = "READ_FIRST"; + defparam INT_RAMB.WRITE_MODE_B = "READ_FIRST"; + defparam INT_RAMB.SETUP_ALL = SETUP_ALL; + defparam INT_RAMB.SETUP_READ_FIRST = SETUP_READ_FIRST; + defparam INT_RAMB.SIM_COLLISION_CHECK = SIM_COLLISION_CHECK; + defparam INT_RAMB.DOA_REG = DO_REG; + defparam INT_RAMB.DOB_REG = DO_REG; + defparam INT_RAMB.INIT_00 = INIT_00; + defparam INT_RAMB.INIT_01 = INIT_01; + defparam INT_RAMB.INIT_02 = INIT_02; + defparam INT_RAMB.INIT_03 = INIT_03; + defparam INT_RAMB.INIT_04 = INIT_04; + defparam INT_RAMB.INIT_05 = INIT_05; + defparam INT_RAMB.INIT_06 = INIT_06; + defparam INT_RAMB.INIT_07 = INIT_07; + defparam INT_RAMB.INIT_08 = INIT_08; + defparam INT_RAMB.INIT_09 = INIT_09; + defparam INT_RAMB.INIT_0A = INIT_0A; + defparam INT_RAMB.INIT_0B = INIT_0B; + defparam INT_RAMB.INIT_0C = INIT_0C; + defparam INT_RAMB.INIT_0D = INIT_0D; + defparam INT_RAMB.INIT_0E = INIT_0E; + defparam INT_RAMB.INIT_0F = INIT_0F; + defparam INT_RAMB.INIT_10 = INIT_10; + defparam INT_RAMB.INIT_11 = INIT_11; + defparam INT_RAMB.INIT_12 = INIT_12; + defparam INT_RAMB.INIT_13 = INIT_13; + defparam INT_RAMB.INIT_14 = INIT_14; + defparam INT_RAMB.INIT_15 = INIT_15; + defparam INT_RAMB.INIT_16 = INIT_16; + defparam INT_RAMB.INIT_17 = INIT_17; + defparam INT_RAMB.INIT_18 = INIT_18; + defparam INT_RAMB.INIT_19 = INIT_19; + defparam INT_RAMB.INIT_1A = INIT_1A; + defparam INT_RAMB.INIT_1B = INIT_1B; + defparam INT_RAMB.INIT_1C = INIT_1C; + defparam INT_RAMB.INIT_1D = INIT_1D; + defparam INT_RAMB.INIT_1E = INIT_1E; + defparam INT_RAMB.INIT_1F = INIT_1F; + defparam INT_RAMB.INIT_20 = INIT_20; + defparam INT_RAMB.INIT_21 = INIT_21; + defparam INT_RAMB.INIT_22 = INIT_22; + defparam INT_RAMB.INIT_23 = INIT_23; + defparam INT_RAMB.INIT_24 = INIT_24; + defparam INT_RAMB.INIT_25 = INIT_25; + defparam INT_RAMB.INIT_26 = INIT_26; + defparam INT_RAMB.INIT_27 = INIT_27; + defparam INT_RAMB.INIT_28 = INIT_28; + defparam INT_RAMB.INIT_29 = INIT_29; + defparam INT_RAMB.INIT_2A = INIT_2A; + defparam INT_RAMB.INIT_2B = INIT_2B; + defparam INT_RAMB.INIT_2C = INIT_2C; + defparam INT_RAMB.INIT_2D = INIT_2D; + defparam INT_RAMB.INIT_2E = INIT_2E; + defparam INT_RAMB.INIT_2F = INIT_2F; + defparam INT_RAMB.INIT_30 = INIT_30; + defparam INT_RAMB.INIT_31 = INIT_31; + defparam INT_RAMB.INIT_32 = INIT_32; + defparam INT_RAMB.INIT_33 = INIT_33; + defparam INT_RAMB.INIT_34 = INIT_34; + defparam INT_RAMB.INIT_35 = INIT_35; + defparam INT_RAMB.INIT_36 = INIT_36; + defparam INT_RAMB.INIT_37 = INIT_37; + defparam INT_RAMB.INIT_38 = INIT_38; + defparam INT_RAMB.INIT_39 = INIT_39; + defparam INT_RAMB.INIT_3A = INIT_3A; + defparam INT_RAMB.INIT_3B = INIT_3B; + defparam INT_RAMB.INIT_3C = INIT_3C; + defparam INT_RAMB.INIT_3D = INIT_3D; + defparam INT_RAMB.INIT_3E = INIT_3E; + defparam INT_RAMB.INIT_3F = INIT_3F; + defparam INT_RAMB.INITP_00 = INITP_00; + defparam INT_RAMB.INITP_01 = INITP_01; + defparam INT_RAMB.INITP_02 = INITP_02; + defparam INT_RAMB.INITP_03 = INITP_03; + defparam INT_RAMB.INITP_04 = INITP_04; + defparam INT_RAMB.INITP_05 = INITP_05; + defparam INT_RAMB.INITP_06 = INITP_06; + defparam INT_RAMB.INITP_07 = INITP_07; + + specify + + (RDCLK => DO[0]) = (100, 100); + (RDCLK => DO[1]) = (100, 100); + (RDCLK => DO[2]) = (100, 100); + (RDCLK => DO[3]) = (100, 100); + (RDCLK => DO[4]) = (100, 100); + (RDCLK => DO[5]) = (100, 100); + (RDCLK => DO[6]) = (100, 100); + (RDCLK => DO[7]) = (100, 100); + (RDCLK => DO[8]) = (100, 100); + (RDCLK => DO[9]) = (100, 100); + (RDCLK => DO[10]) = (100, 100); + (RDCLK => DO[11]) = (100, 100); + (RDCLK => DO[12]) = (100, 100); + (RDCLK => DO[13]) = (100, 100); + (RDCLK => DO[14]) = (100, 100); + (RDCLK => DO[15]) = (100, 100); + (RDCLK => DO[16]) = (100, 100); + (RDCLK => DO[17]) = (100, 100); + (RDCLK => DO[18]) = (100, 100); + (RDCLK => DO[19]) = (100, 100); + (RDCLK => DO[20]) = (100, 100); + (RDCLK => DO[21]) = (100, 100); + (RDCLK => DO[22]) = (100, 100); + (RDCLK => DO[23]) = (100, 100); + (RDCLK => DO[24]) = (100, 100); + (RDCLK => DO[25]) = (100, 100); + (RDCLK => DO[26]) = (100, 100); + (RDCLK => DO[27]) = (100, 100); + (RDCLK => DO[28]) = (100, 100); + (RDCLK => DO[29]) = (100, 100); + (RDCLK => DO[30]) = (100, 100); + (RDCLK => DO[31]) = (100, 100); + (RDCLK => DOP[0]) = (100, 100); + (RDCLK => DOP[1]) = (100, 100); + (RDCLK => DOP[2]) = (100, 100); + (RDCLK => DOP[3]) = (100, 100); + + specparam PATHPULSE$ = 0; + + endspecify + +endmodule // RAMB18SDP + + + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/RAMB32_S64_ECC.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/RAMB32_S64_ECC.v new file mode 100644 index 0000000..d414df0 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/RAMB32_S64_ECC.v @@ -0,0 +1,209 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/virtex4/RAMB32_S64_ECC.v,v 1.8 2006/03/15 01:54:06 wloo Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / RAMB32_S64_ECC +// /___/ /\ Filename : RAMB32_S64_ECC.v +// \ \ / \ Timestamp : Tue Mar 1 14:57:54 PST 2005 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 03/04/05 - Add generic DO_REG and SIM_COLLISION_CHECK to pass to RAMB16. +// Add register to output for the latency. (CR 204569) +// 03/16/05 - Set WRITE_MODE_A and WRITE_MODE_B parameter of RAMB16 to READ_FIRST. +// End Revision + + +`timescale 1 ps / 1 ps + +module RAMB32_S64_ECC ( + DO, + STATUS, + + DI, + RDADDR, + RDCLK, + RDEN, + SSR, + WRADDR, + WRCLK, + WREN +); + +parameter integer DO_REG = 0; +parameter SIM_COLLISION_CHECK = "ALL"; + +output [1:0] STATUS; +output [63:0] DO; + +input RDCLK; +input RDEN; +input SSR; +input WRCLK; +input WREN; +input [63:0] DI; +input [8:0] RDADDR; +input [8:0] WRADDR; + +reg [63:0] DO; +wire [31:0] do_ram16low; +wire [31:0] do_ram16up; +wire [3:0] dopa_ram16low; +wire [3:0] dopa_ram16up; + +reg [31:0] DIB_up; +reg [31:0] DIB_low; +reg [3:0] DIPB_up; +reg [3:0] DIPB_low; + +wire [31:0] DOB_low_open; +wire [3:0] DOPB_low_open; +wire CASCADEOUTA_low_open; +wire CASCADEOUTB_low_open; +wire [31:0] DOB_up_open; +wire [3:0] DOPB_up_open; +wire CASCADEOUTA_up_open; +wire CASCADEOUTB_up_open; + +initial + DO <= 64'b0; + +always @(posedge RDCLK ) + begin + DO[13:0] <= do_ram16low[13:0]; + DO[14] <= dopa_ram16low[1]; + DO[15] <= dopa_ram16low[3]; + DO[29:16] <= do_ram16low[29:16]; + DO[30] <= dopa_ram16low[0]; + DO[31] <= dopa_ram16low[2]; + + DO[32] <= dopa_ram16up[0]; + DO[33] <= dopa_ram16up[2]; + DO[47:34] <= do_ram16up[15:2]; + DO[48] <= dopa_ram16up[1]; + DO[49] <= dopa_ram16up[3]; + DO[63:50] <= do_ram16up[31:18]; + end + +always @(DI) + begin + DIB_low [13:0] <= DI[13:0]; + DIB_low [15:14] <= 2'b00; + DIPB_low[1] <= DI[14]; + DIPB_low[3] <= DI[15]; + DIB_low[29:16] <= DI[29:16]; + DIB_low[31:30] <= 2'b00; + DIPB_low[0] <= DI[30]; + DIPB_low[2] <= DI[31]; + + DIPB_up[0] <= DI[32]; + DIPB_up[2] <= DI[33]; + DIB_up[15:2] <= DI[47:34]; + DIB_up[1:0] <= 2'b00; + DIPB_up[1] <= DI[48]; + DIPB_up[3] <= DI[49]; + DIB_up[17:16] <= 2'b00; + DIB_up[31:18] <= DI[63:50]; + end + + + assign STATUS = 2'b00; + + RAMB16 RAMB16_LOWER ( + .ADDRA ({1'b1, RDADDR, 5'b00000}), + .ADDRB ({1'b1, WRADDR, 5'b00000}), + .DIA (32'b0), + .DIB (DIB_low), + .DIPA (4'b0), + .DIPB (DIPB_low), + .ENA (RDEN), + .ENB (WREN), + .WEA (4'b0), + .WEB (4'b1111), + .SSRA (SSR), + .SSRB (1'b0), + .CLKA (RDCLK), + .CLKB (WRCLK), + .REGCEA (1'b1), + .REGCEB (1'b0), + .CASCADEINA (1'b0), + .CASCADEINB (1'b0), + .DOA (do_ram16low), + .DOB (DOB_low_open), + .DOPA (dopa_ram16low), + .DOPB (DOPB_low_open), + .CASCADEOUTA (CASCADEOUTA_low_open), + .CASCADEOUTB (CASCADEOUTB_low_open) + ); + +defparam RAMB16_LOWER.READ_WIDTH_A = 36; +defparam RAMB16_LOWER.WRITE_WIDTH_A = 36; +defparam RAMB16_LOWER.READ_WIDTH_B = 36; +defparam RAMB16_LOWER.WRITE_WIDTH_B = 36; +defparam RAMB16_LOWER.WRITE_MODE_A = "READ_FIRST"; +defparam RAMB16_LOWER.WRITE_MODE_B = "READ_FIRST"; +defparam RAMB16_LOWER.INIT_A = 36'b0; +defparam RAMB16_LOWER.SRVAL_A = 36'b0; +defparam RAMB16_LOWER.INIT_B = 36'b0; +defparam RAMB16_LOWER.SRVAL_B = 36'b0; +defparam RAMB16_LOWER.DOA_REG = DO_REG; +defparam RAMB16_LOWER.DOB_REG = 0; +defparam RAMB16_LOWER.INVERT_CLK_DOA_REG = "FALSE"; +defparam RAMB16_LOWER.INVERT_CLK_DOB_REG = "FALSE"; +defparam RAMB16_LOWER.RAM_EXTENSION_A = "NONE"; +defparam RAMB16_LOWER.RAM_EXTENSION_B = "NONE"; +defparam RAMB16_LOWER.SIM_COLLISION_CHECK = SIM_COLLISION_CHECK; + + RAMB16 RAMB16_UPPER ( + .ADDRA ({1'b1, RDADDR, 5'b00000}), + .ADDRB ({1'b1, WRADDR, 5'b00000}), + .DIA (32'b0), + .DIB (DIB_up), + .DIPA (4'b0), + .DIPB (DIPB_up), + .ENA (RDEN), + .ENB (WREN), + .WEA (4'b0), + .WEB (4'b1111), + .SSRA (SSR), + .SSRB (1'b0), + .CLKA (RDCLK), + .CLKB (WRCLK), + .REGCEA (1'b1), + .REGCEB (1'b0), + .CASCADEINA (1'b0), + .CASCADEINB (1'b0), + .DOA (do_ram16up), + .DOB (DOB_up_open), + .DOPA (dopa_ram16up), + .DOPB (DOPB_up_open), + .CASCADEOUTA (CASCADEOUTA_up_open), + .CASCADEOUTB (CASCADEOUTB_up_open) + + ); + +defparam RAMB16_UPPER.READ_WIDTH_A = 36; +defparam RAMB16_UPPER.WRITE_WIDTH_A = 36; +defparam RAMB16_UPPER.READ_WIDTH_B = 36; +defparam RAMB16_UPPER.WRITE_WIDTH_B = 36; +defparam RAMB16_UPPER.WRITE_MODE_A = "READ_FIRST"; +defparam RAMB16_UPPER.WRITE_MODE_B = "READ_FIRST"; +defparam RAMB16_UPPER.INIT_A = 36'b0; +defparam RAMB16_UPPER.SRVAL_A = 36'b0; +defparam RAMB16_UPPER.INIT_B = 36'b0; +defparam RAMB16_UPPER.SRVAL_B = 36'b0; +defparam RAMB16_UPPER.DOA_REG = DO_REG; +defparam RAMB16_UPPER.DOB_REG = 0; +defparam RAMB16_UPPER.INVERT_CLK_DOA_REG = "FALSE"; +defparam RAMB16_UPPER.INVERT_CLK_DOB_REG = "FALSE"; +defparam RAMB16_UPPER.RAM_EXTENSION_A = "NONE"; +defparam RAMB16_UPPER.RAM_EXTENSION_B = "NONE"; +defparam RAMB16_UPPER.SIM_COLLISION_CHECK = SIM_COLLISION_CHECK; +endmodule diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/RAMB36.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/RAMB36.v new file mode 100644 index 0000000..9b4c86d --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/RAMB36.v @@ -0,0 +1,481 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/rainier/RAMB36.v,v 1.16 2007/06/15 20:58:41 wloo Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2005 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / 32K-Bit Data and 4K-Bit Parity Dual Port Block RAM +// /___/ /\ Filename : RAMB36.v +// \ \ / \ Timestamp : Tues July 26 16:43:59 PST 2005 +// \___\/\___\ +// +// Revision: +// 07/26/05 - Initial version. +// 01/04/07 - Added support of memory file to initialize memory and parity (CR 431584). +// 03/14/07 - Removed attribute INITP_FILE (CR 436003). +// 04/03/07 - Changed INIT_FILE = "NONE" as default (CR 436812). +// 06/13/07 - Added high performace version of the model. +// End Revision + +`timescale 1 ps/1 ps + +module RAMB36 (CASCADEOUTLATA, CASCADEOUTLATB, CASCADEOUTREGA, CASCADEOUTREGB, DOA, DOB, DOPA, DOPB, + ADDRA, ADDRB, CASCADEINLATA, CASCADEINLATB, CASCADEINREGA, CASCADEINREGB, CLKA, CLKB, DIA, DIB, DIPA, DIPB, ENA, ENB, REGCEA, REGCEB, SSRA, SSRB, WEA, WEB); + + parameter integer DOA_REG = 0; + parameter integer DOB_REG = 0; + parameter INITP_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_40 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_41 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_42 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_43 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_44 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_45 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_46 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_47 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_48 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_49 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_4A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_4B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_4C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_4D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_4E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_4F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_50 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_51 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_52 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_53 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_54 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_55 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_56 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_57 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_58 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_59 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_5A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_5B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_5C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_5D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_5E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_5F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_60 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_61 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_62 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_63 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_64 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_65 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_66 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_67 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_68 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_69 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_6A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_6B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_6C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_6D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_6E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_6F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_70 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_71 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_72 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_73 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_74 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_75 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_76 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_77 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_78 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_79 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_7A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_7B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_7C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_7D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_7E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_7F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_A = 36'h0; + parameter INIT_B = 36'h0; + parameter INIT_FILE = "NONE"; + parameter RAM_EXTENSION_A = "NONE"; + parameter RAM_EXTENSION_B = "NONE"; + parameter integer READ_WIDTH_A = 0; + parameter integer READ_WIDTH_B = 0; + parameter SIM_COLLISION_CHECK = "ALL"; + parameter SIM_MODE = "SAFE"; + parameter SRVAL_A = 36'h0; + parameter SRVAL_B = 36'h0; + parameter WRITE_MODE_A = "WRITE_FIRST"; + parameter WRITE_MODE_B = "WRITE_FIRST"; + parameter integer WRITE_WIDTH_A = 0; + parameter integer WRITE_WIDTH_B = 0; + + localparam SETUP_ALL = 1000; + localparam SETUP_READ_FIRST = 3000; + + output CASCADEOUTLATA, CASCADEOUTREGA; + output CASCADEOUTLATB, CASCADEOUTREGB; + output [31:0] DOA; + output [31:0] DOB; + output [3:0] DOPA; + output [3:0] DOPB; + + input ENA, CLKA, SSRA, CASCADEINLATA, CASCADEINREGA, REGCEA; + input ENB, CLKB, SSRB, CASCADEINLATB, CASCADEINREGB, REGCEB; + input [15:0] ADDRA; + input [15:0] ADDRB; + input [31:0] DIA; + input [31:0] DIB; + input [3:0] DIPA; + input [3:0] DIPB; + input [3:0] WEA; + input [3:0] WEB; + + tri0 GSR = glbl.GSR; + + wire [7:0] dangle_out8; + wire dangle_out; + wire [3:0] dangle_out4; + wire [31:0] dangle_out32; + + ARAMB36_INTERNAL INT_RAMB (.DIA({32'b0,DIA}), .ENA(ENA), .WEA({4'b0,WEA}), .SSRA(SSRA), .ADDRA(ADDRA), .CLKA(CLKA), .DOA({dangle_out32,DOA}), .DIB({32'b0,DIB}), .ENB(ENB), .WEB({4'b0,WEB}), .SSRB(SSRB), .ADDRB(ADDRB), .CLKB(CLKB), .DOB(DOB), .GSR(GSR), .DOPA({dangle_out4,DOPA}), .DOPB(DOPB), .DIPA(DIPA), .DIPB({4'b0,DIPB}), .CASCADEOUTLATA(CASCADEOUTLATA), .CASCADEOUTLATB(CASCADEOUTLATB), .CASCADEOUTREGA(CASCADEOUTREGA), .CASCADEOUTREGB(CASCADEOUTREGB), .CASCADEINLATA(CASCADEINLATA), .CASCADEINLATB(CASCADEINLATB), .CASCADEINREGA(CASCADEINREGA), .CASCADEINREGB(CASCADEINREGB), .REGCEA(REGCEA), .REGCEB(REGCEB), .REGCLKA(CLKA), .REGCLKB(CLKB), .DBITERR(dangle_out), .ECCPARITY(dangle_out8), .SBITERR(dangle_out)); + + defparam INT_RAMB.BRAM_MODE = "TRUE_DUAL_PORT"; + defparam INT_RAMB.INIT_A = INIT_A; + defparam INT_RAMB.INIT_B = INIT_B; + defparam INT_RAMB.INIT_FILE = INIT_FILE; + defparam INT_RAMB.SRVAL_A = SRVAL_A; + defparam INT_RAMB.SRVAL_B = SRVAL_B; + defparam INT_RAMB.READ_WIDTH_A = READ_WIDTH_A; + defparam INT_RAMB.READ_WIDTH_B = READ_WIDTH_B; + defparam INT_RAMB.WRITE_WIDTH_A = WRITE_WIDTH_A; + defparam INT_RAMB.WRITE_WIDTH_B = WRITE_WIDTH_B; + defparam INT_RAMB.WRITE_MODE_A = WRITE_MODE_A; + defparam INT_RAMB.WRITE_MODE_B = WRITE_MODE_B; + defparam INT_RAMB.RAM_EXTENSION_A = RAM_EXTENSION_A; + defparam INT_RAMB.RAM_EXTENSION_B = RAM_EXTENSION_B; + defparam INT_RAMB.SETUP_ALL = SETUP_ALL; + defparam INT_RAMB.SETUP_READ_FIRST = SETUP_READ_FIRST; + defparam INT_RAMB.SIM_COLLISION_CHECK = SIM_COLLISION_CHECK; + defparam INT_RAMB.SIM_MODE = SIM_MODE; + defparam INT_RAMB.EN_ECC_READ = "FALSE"; + defparam INT_RAMB.EN_ECC_SCRUB = "FALSE"; + defparam INT_RAMB.EN_ECC_WRITE = "FALSE"; + defparam INT_RAMB.DOA_REG = DOA_REG; + defparam INT_RAMB.DOB_REG = DOB_REG; + defparam INT_RAMB.INIT_00 = INIT_00; + defparam INT_RAMB.INIT_01 = INIT_01; + defparam INT_RAMB.INIT_02 = INIT_02; + defparam INT_RAMB.INIT_03 = INIT_03; + defparam INT_RAMB.INIT_04 = INIT_04; + defparam INT_RAMB.INIT_05 = INIT_05; + defparam INT_RAMB.INIT_06 = INIT_06; + defparam INT_RAMB.INIT_07 = INIT_07; + defparam INT_RAMB.INIT_08 = INIT_08; + defparam INT_RAMB.INIT_09 = INIT_09; + defparam INT_RAMB.INIT_0A = INIT_0A; + defparam INT_RAMB.INIT_0B = INIT_0B; + defparam INT_RAMB.INIT_0C = INIT_0C; + defparam INT_RAMB.INIT_0D = INIT_0D; + defparam INT_RAMB.INIT_0E = INIT_0E; + defparam INT_RAMB.INIT_0F = INIT_0F; + defparam INT_RAMB.INIT_10 = INIT_10; + defparam INT_RAMB.INIT_11 = INIT_11; + defparam INT_RAMB.INIT_12 = INIT_12; + defparam INT_RAMB.INIT_13 = INIT_13; + defparam INT_RAMB.INIT_14 = INIT_14; + defparam INT_RAMB.INIT_15 = INIT_15; + defparam INT_RAMB.INIT_16 = INIT_16; + defparam INT_RAMB.INIT_17 = INIT_17; + defparam INT_RAMB.INIT_18 = INIT_18; + defparam INT_RAMB.INIT_19 = INIT_19; + defparam INT_RAMB.INIT_1A = INIT_1A; + defparam INT_RAMB.INIT_1B = INIT_1B; + defparam INT_RAMB.INIT_1C = INIT_1C; + defparam INT_RAMB.INIT_1D = INIT_1D; + defparam INT_RAMB.INIT_1E = INIT_1E; + defparam INT_RAMB.INIT_1F = INIT_1F; + defparam INT_RAMB.INIT_20 = INIT_20; + defparam INT_RAMB.INIT_21 = INIT_21; + defparam INT_RAMB.INIT_22 = INIT_22; + defparam INT_RAMB.INIT_23 = INIT_23; + defparam INT_RAMB.INIT_24 = INIT_24; + defparam INT_RAMB.INIT_25 = INIT_25; + defparam INT_RAMB.INIT_26 = INIT_26; + defparam INT_RAMB.INIT_27 = INIT_27; + defparam INT_RAMB.INIT_28 = INIT_28; + defparam INT_RAMB.INIT_29 = INIT_29; + defparam INT_RAMB.INIT_2A = INIT_2A; + defparam INT_RAMB.INIT_2B = INIT_2B; + defparam INT_RAMB.INIT_2C = INIT_2C; + defparam INT_RAMB.INIT_2D = INIT_2D; + defparam INT_RAMB.INIT_2E = INIT_2E; + defparam INT_RAMB.INIT_2F = INIT_2F; + defparam INT_RAMB.INIT_30 = INIT_30; + defparam INT_RAMB.INIT_31 = INIT_31; + defparam INT_RAMB.INIT_32 = INIT_32; + defparam INT_RAMB.INIT_33 = INIT_33; + defparam INT_RAMB.INIT_34 = INIT_34; + defparam INT_RAMB.INIT_35 = INIT_35; + defparam INT_RAMB.INIT_36 = INIT_36; + defparam INT_RAMB.INIT_37 = INIT_37; + defparam INT_RAMB.INIT_38 = INIT_38; + defparam INT_RAMB.INIT_39 = INIT_39; + defparam INT_RAMB.INIT_3A = INIT_3A; + defparam INT_RAMB.INIT_3B = INIT_3B; + defparam INT_RAMB.INIT_3C = INIT_3C; + defparam INT_RAMB.INIT_3D = INIT_3D; + defparam INT_RAMB.INIT_3E = INIT_3E; + defparam INT_RAMB.INIT_3F = INIT_3F; + defparam INT_RAMB.INIT_40 = INIT_40; + defparam INT_RAMB.INIT_41 = INIT_41; + defparam INT_RAMB.INIT_42 = INIT_42; + defparam INT_RAMB.INIT_43 = INIT_43; + defparam INT_RAMB.INIT_44 = INIT_44; + defparam INT_RAMB.INIT_45 = INIT_45; + defparam INT_RAMB.INIT_46 = INIT_46; + defparam INT_RAMB.INIT_47 = INIT_47; + defparam INT_RAMB.INIT_48 = INIT_48; + defparam INT_RAMB.INIT_49 = INIT_49; + defparam INT_RAMB.INIT_4A = INIT_4A; + defparam INT_RAMB.INIT_4B = INIT_4B; + defparam INT_RAMB.INIT_4C = INIT_4C; + defparam INT_RAMB.INIT_4D = INIT_4D; + defparam INT_RAMB.INIT_4E = INIT_4E; + defparam INT_RAMB.INIT_4F = INIT_4F; + defparam INT_RAMB.INIT_50 = INIT_50; + defparam INT_RAMB.INIT_51 = INIT_51; + defparam INT_RAMB.INIT_52 = INIT_52; + defparam INT_RAMB.INIT_53 = INIT_53; + defparam INT_RAMB.INIT_54 = INIT_54; + defparam INT_RAMB.INIT_55 = INIT_55; + defparam INT_RAMB.INIT_56 = INIT_56; + defparam INT_RAMB.INIT_57 = INIT_57; + defparam INT_RAMB.INIT_58 = INIT_58; + defparam INT_RAMB.INIT_59 = INIT_59; + defparam INT_RAMB.INIT_5A = INIT_5A; + defparam INT_RAMB.INIT_5B = INIT_5B; + defparam INT_RAMB.INIT_5C = INIT_5C; + defparam INT_RAMB.INIT_5D = INIT_5D; + defparam INT_RAMB.INIT_5E = INIT_5E; + defparam INT_RAMB.INIT_5F = INIT_5F; + defparam INT_RAMB.INIT_60 = INIT_60; + defparam INT_RAMB.INIT_61 = INIT_61; + defparam INT_RAMB.INIT_62 = INIT_62; + defparam INT_RAMB.INIT_63 = INIT_63; + defparam INT_RAMB.INIT_64 = INIT_64; + defparam INT_RAMB.INIT_65 = INIT_65; + defparam INT_RAMB.INIT_66 = INIT_66; + defparam INT_RAMB.INIT_67 = INIT_67; + defparam INT_RAMB.INIT_68 = INIT_68; + defparam INT_RAMB.INIT_69 = INIT_69; + defparam INT_RAMB.INIT_6A = INIT_6A; + defparam INT_RAMB.INIT_6B = INIT_6B; + defparam INT_RAMB.INIT_6C = INIT_6C; + defparam INT_RAMB.INIT_6D = INIT_6D; + defparam INT_RAMB.INIT_6E = INIT_6E; + defparam INT_RAMB.INIT_6F = INIT_6F; + defparam INT_RAMB.INIT_70 = INIT_70; + defparam INT_RAMB.INIT_71 = INIT_71; + defparam INT_RAMB.INIT_72 = INIT_72; + defparam INT_RAMB.INIT_73 = INIT_73; + defparam INT_RAMB.INIT_74 = INIT_74; + defparam INT_RAMB.INIT_75 = INIT_75; + defparam INT_RAMB.INIT_76 = INIT_76; + defparam INT_RAMB.INIT_77 = INIT_77; + defparam INT_RAMB.INIT_78 = INIT_78; + defparam INT_RAMB.INIT_79 = INIT_79; + defparam INT_RAMB.INIT_7A = INIT_7A; + defparam INT_RAMB.INIT_7B = INIT_7B; + defparam INT_RAMB.INIT_7C = INIT_7C; + defparam INT_RAMB.INIT_7D = INIT_7D; + defparam INT_RAMB.INIT_7E = INIT_7E; + defparam INT_RAMB.INIT_7F = INIT_7F; + defparam INT_RAMB.INITP_00 = INITP_00; + defparam INT_RAMB.INITP_01 = INITP_01; + defparam INT_RAMB.INITP_02 = INITP_02; + defparam INT_RAMB.INITP_03 = INITP_03; + defparam INT_RAMB.INITP_04 = INITP_04; + defparam INT_RAMB.INITP_05 = INITP_05; + defparam INT_RAMB.INITP_06 = INITP_06; + defparam INT_RAMB.INITP_07 = INITP_07; + defparam INT_RAMB.INITP_08 = INITP_08; + defparam INT_RAMB.INITP_09 = INITP_09; + defparam INT_RAMB.INITP_0A = INITP_0A; + defparam INT_RAMB.INITP_0B = INITP_0B; + defparam INT_RAMB.INITP_0C = INITP_0C; + defparam INT_RAMB.INITP_0D = INITP_0D; + defparam INT_RAMB.INITP_0E = INITP_0E; + defparam INT_RAMB.INITP_0F = INITP_0F; + + specify + + (CLKA => DOA[0]) = (100, 100); + (CLKA => DOA[1]) = (100, 100); + (CLKA => DOA[2]) = (100, 100); + (CLKA => DOA[3]) = (100, 100); + (CLKA => DOA[4]) = (100, 100); + (CLKA => DOA[5]) = (100, 100); + (CLKA => DOA[6]) = (100, 100); + (CLKA => DOA[7]) = (100, 100); + (CLKA => DOA[8]) = (100, 100); + (CLKA => DOA[9]) = (100, 100); + (CLKA => DOA[10]) = (100, 100); + (CLKA => DOA[11]) = (100, 100); + (CLKA => DOA[12]) = (100, 100); + (CLKA => DOA[13]) = (100, 100); + (CLKA => DOA[14]) = (100, 100); + (CLKA => DOA[15]) = (100, 100); + (CLKA => DOA[16]) = (100, 100); + (CLKA => DOA[17]) = (100, 100); + (CLKA => DOA[18]) = (100, 100); + (CLKA => DOA[19]) = (100, 100); + (CLKA => DOA[20]) = (100, 100); + (CLKA => DOA[21]) = (100, 100); + (CLKA => DOA[22]) = (100, 100); + (CLKA => DOA[23]) = (100, 100); + (CLKA => DOA[24]) = (100, 100); + (CLKA => DOA[25]) = (100, 100); + (CLKA => DOA[26]) = (100, 100); + (CLKA => DOA[27]) = (100, 100); + (CLKA => DOA[28]) = (100, 100); + (CLKA => DOA[29]) = (100, 100); + (CLKA => DOA[30]) = (100, 100); + (CLKA => DOA[31]) = (100, 100); + (CLKA => DOPA[0]) = (100, 100); + (CLKA => DOPA[1]) = (100, 100); + (CLKA => DOPA[2]) = (100, 100); + (CLKA => DOPA[3]) = (100, 100); + + (CLKB => DOB[0]) = (100, 100); + (CLKB => DOB[1]) = (100, 100); + (CLKB => DOB[2]) = (100, 100); + (CLKB => DOB[3]) = (100, 100); + (CLKB => DOB[4]) = (100, 100); + (CLKB => DOB[5]) = (100, 100); + (CLKB => DOB[6]) = (100, 100); + (CLKB => DOB[7]) = (100, 100); + (CLKB => DOB[8]) = (100, 100); + (CLKB => DOB[9]) = (100, 100); + (CLKB => DOB[10]) = (100, 100); + (CLKB => DOB[11]) = (100, 100); + (CLKB => DOB[12]) = (100, 100); + (CLKB => DOB[13]) = (100, 100); + (CLKB => DOB[14]) = (100, 100); + (CLKB => DOB[15]) = (100, 100); + (CLKB => DOB[16]) = (100, 100); + (CLKB => DOB[17]) = (100, 100); + (CLKB => DOB[18]) = (100, 100); + (CLKB => DOB[19]) = (100, 100); + (CLKB => DOB[20]) = (100, 100); + (CLKB => DOB[21]) = (100, 100); + (CLKB => DOB[22]) = (100, 100); + (CLKB => DOB[23]) = (100, 100); + (CLKB => DOB[24]) = (100, 100); + (CLKB => DOB[25]) = (100, 100); + (CLKB => DOB[26]) = (100, 100); + (CLKB => DOB[27]) = (100, 100); + (CLKB => DOB[28]) = (100, 100); + (CLKB => DOB[29]) = (100, 100); + (CLKB => DOB[30]) = (100, 100); + (CLKB => DOB[31]) = (100, 100); + (CLKB => DOPB[0]) = (100, 100); + (CLKB => DOPB[1]) = (100, 100); + (CLKB => DOPB[2]) = (100, 100); + (CLKB => DOPB[3]) = (100, 100); + + (CASCADEINLATA => DOA[0]) = (0, 0); + (CASCADEINREGA => DOA[0]) = (0, 0); + (CASCADEINLATB => DOB[0]) = (0, 0); + (CASCADEINREGB => DOB[0]) = (0, 0); + (CLKA => CASCADEOUTLATA) = (100, 100); + (CLKA => CASCADEOUTREGA) = (100, 100); + (CLKB => CASCADEOUTLATB) = (100, 100); + (CLKB => CASCADEOUTREGB) = (100, 100); + + specparam PATHPULSE$ = 0; + + endspecify + +endmodule // RAMB36 + + + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/RAMB36E1.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/RAMB36E1.v new file mode 100644 index 0000000..1b1ee1f --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/RAMB36E1.v @@ -0,0 +1,3943 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/blanc/RAMB36E1.v,v 1.17.24.4.6.1 2010/06/14 22:48:43 wloo Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2008 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / 32K-Bit Data and 4K-Bit Parity Dual Port Block RAM +// /___/ /\ Filename : RAMB36E1.v +// \ \ / \ Timestamp : Tue Feb 26 13:49:08 PST 2008 +// \___\/\___\ +// +// Revision: +// 02/26/08 - Initial version. +// 07/25/08 - Fixed ECC in register mode. (IR 477257) +// 07/30/08 - Updated to support SDP mode with smaller port width <= 36. (IR 477258) +// 11/04/08 - Fixed incorrect output during first clock cycle. (CR 470964) +// 11/10/08 - Added DRC for invalid input parity for ECC (CR 482976). +// 11/20/08 - Changed RDADDRECC[12:0] to [8:0] (IR 496907). +// 03/11/09 - X's the unused bits of outputs (CR 511363). +// 03/23/09 - Fixed unusual behavior of X's in the unused bits of outputs (CR 513167). +// 04/10/09 - Implemented workaround for NCSim event triggering during initial time (CR 517450). +// 04/17/09 - Implemented X's in sbiterr and dbiterr outputs during collision in ECC mode (CR 508071). +// 08/03/09 - Updated collision behavior when both clocks are in phase/within 100 ps (CR 522327). +// 08/12/09 - Updated collision address check for none in phase clocks (CR 527010). +// 08/18/09 - Fixed output delay in SDP mode (CR 528259). +// 11/16/09 - Implemented DRC for ADDR[15] in non-cascade mode (CR 535882). +// 11/18/09 - Define tasks and functions before calling (CR 532610). +// 11/24/09 - Undo CR 535882, bitgen or map is going to tie off ADDR[15] instead. +// 12/16/09 - Enhanced memory initialization (CR 540764). +// 03/15/10 - Updated address collision for asynchronous clocks and read first mode (CR 527010). +// 04/01/10 - Fixed clocks detection for collision (CR 552123). +// 05/11/10 - Updated clocks detection for collision (CR 557624). +// - Added attribute RDADDR_COLLISION_HWCONFIG (CR 557971). +// 05/25/10 - Added WRITE_FIRST support in SDP mode (CR 561807). +// 06/03/10 - Added functionality for attribute RDADDR_COLLISION_HWCONFIG (CR 557971). +// End Revision + +`timescale 1 ps/1 ps + +module RAMB36E1 (CASCADEOUTA, CASCADEOUTB, DBITERR, DOADO, DOBDO, DOPADOP, DOPBDOP, ECCPARITY, RDADDRECC, SBITERR, + ADDRARDADDR, ADDRBWRADDR, CASCADEINA, CASCADEINB, CLKARDCLK, CLKBWRCLK, DIADI, DIBDI, DIPADIP, DIPBDIP, ENARDEN, ENBWREN, INJECTDBITERR, INJECTSBITERR, REGCEAREGCE, REGCEB, RSTRAMARSTRAM, RSTRAMB, RSTREGARSTREG, RSTREGB, WEA, WEBWE); + + parameter integer DOA_REG = 0; + parameter integer DOB_REG = 0; + parameter EN_ECC_READ = "FALSE"; + parameter EN_ECC_WRITE = "FALSE"; + parameter INITP_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_40 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_41 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_42 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_43 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_44 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_45 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_46 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_47 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_48 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_49 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_4A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_4B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_4C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_4D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_4E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_4F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_50 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_51 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_52 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_53 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_54 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_55 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_56 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_57 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_58 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_59 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_5A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_5B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_5C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_5D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_5E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_5F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_60 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_61 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_62 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_63 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_64 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_65 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_66 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_67 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_68 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_69 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_6A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_6B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_6C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_6D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_6E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_6F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_70 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_71 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_72 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_73 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_74 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_75 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_76 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_77 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_78 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_79 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_7A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_7B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_7C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_7D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_7E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_7F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_A = 36'h0; + parameter INIT_B = 36'h0; + parameter INIT_FILE = "NONE"; + parameter RAM_EXTENSION_A = "NONE"; + parameter RAM_EXTENSION_B = "NONE"; + parameter RAM_MODE = "TDP"; + parameter RDADDR_COLLISION_HWCONFIG = "DELAYED_WRITE"; + parameter integer READ_WIDTH_A = 0; + parameter integer READ_WIDTH_B = 0; + parameter RSTREG_PRIORITY_A = "RSTREG"; + parameter RSTREG_PRIORITY_B = "RSTREG"; + parameter SIM_COLLISION_CHECK = "ALL"; + parameter SRVAL_A = 36'h0; + parameter SRVAL_B = 36'h0; + parameter WRITE_MODE_A = "WRITE_FIRST"; + parameter WRITE_MODE_B = "WRITE_FIRST"; + parameter integer WRITE_WIDTH_A = 0; + parameter integer WRITE_WIDTH_B = 0; + + localparam SETUP_ALL = 1000; + localparam SETUP_READ_FIRST = 3000; + + output CASCADEOUTA; + output CASCADEOUTB; + output [31:0] DOADO; + output [31:0] DOBDO; + output [3:0] DOPADOP; + output [3:0] DOPBDOP; + output [7:0] ECCPARITY; + output [8:0] RDADDRECC; + output SBITERR, DBITERR; + + input ENARDEN, CLKARDCLK, RSTRAMARSTRAM, RSTREGARSTREG, CASCADEINA, REGCEAREGCE; + input ENBWREN, CLKBWRCLK, RSTRAMB, RSTREGB, CASCADEINB, REGCEB; + input INJECTDBITERR, INJECTSBITERR; + input [15:0] ADDRARDADDR; + input [15:0] ADDRBWRADDR; + input [31:0] DIADI; + input [31:0] DIBDI; + input [3:0] DIPADIP; + input [3:0] DIPBDIP; + input [3:0] WEA; + input [7:0] WEBWE; + + tri0 GSR = glbl.GSR; + + wire [3:0] dangle_out4; + wire [31:0] dangle_out32; + + + // special handle for sdp width = 72 and < 72 + localparam init_sdp = (READ_WIDTH_A == 72) ? {INIT_B[35:32],INIT_A[35:32],INIT_B[31:0],INIT_A[31:0]} : {INIT_B, INIT_A}; + localparam srval_sdp = (READ_WIDTH_A == 72) ? {SRVAL_B[35:32],SRVAL_A[35:32],SRVAL_B[31:0],SRVAL_A[31:0]} : {SRVAL_B, SRVAL_A}; + + + generate + case (RAM_MODE) + + "TDP" : begin + + RB36_INTERNAL_VLOG #(.RAM_MODE(RAM_MODE), + .INIT_A(INIT_A), + .INIT_B(INIT_B), + .INIT_FILE(INIT_FILE), + .SRVAL_A(SRVAL_A), + .SRVAL_B(SRVAL_B), + .READ_WIDTH_A(READ_WIDTH_A), + .READ_WIDTH_B(READ_WIDTH_B), + .WRITE_WIDTH_A(WRITE_WIDTH_A), + .WRITE_WIDTH_B(WRITE_WIDTH_B), + .WRITE_MODE_A(WRITE_MODE_A), + .WRITE_MODE_B(WRITE_MODE_B), + .RAM_EXTENSION_A(RAM_EXTENSION_A), + .RAM_EXTENSION_B(RAM_EXTENSION_B), + .RDADDR_COLLISION_HWCONFIG(RDADDR_COLLISION_HWCONFIG), + .SETUP_ALL(SETUP_ALL), + .SETUP_READ_FIRST(SETUP_READ_FIRST), + .SIM_COLLISION_CHECK(SIM_COLLISION_CHECK), + .EN_ECC_READ(EN_ECC_READ), + .EN_ECC_WRITE(EN_ECC_WRITE), + .DOA_REG(DOA_REG), + .DOB_REG(DOB_REG), + .RSTREG_PRIORITY_A(RSTREG_PRIORITY_A), + .RSTREG_PRIORITY_B(RSTREG_PRIORITY_B), + .INIT_00(INIT_00), + .INIT_01(INIT_01), + .INIT_02(INIT_02), + .INIT_03(INIT_03), + .INIT_04(INIT_04), + .INIT_05(INIT_05), + .INIT_06(INIT_06), + .INIT_07(INIT_07), + .INIT_08(INIT_08), + .INIT_09(INIT_09), + .INIT_0A(INIT_0A), + .INIT_0B(INIT_0B), + .INIT_0C(INIT_0C), + .INIT_0D(INIT_0D), + .INIT_0E(INIT_0E), + .INIT_0F(INIT_0F), + .INIT_10(INIT_10), + .INIT_11(INIT_11), + .INIT_12(INIT_12), + .INIT_13(INIT_13), + .INIT_14(INIT_14), + .INIT_15(INIT_15), + .INIT_16(INIT_16), + .INIT_17(INIT_17), + .INIT_18(INIT_18), + .INIT_19(INIT_19), + .INIT_1A(INIT_1A), + .INIT_1B(INIT_1B), + .INIT_1C(INIT_1C), + .INIT_1D(INIT_1D), + .INIT_1E(INIT_1E), + .INIT_1F(INIT_1F), + .INIT_20(INIT_20), + .INIT_21(INIT_21), + .INIT_22(INIT_22), + .INIT_23(INIT_23), + .INIT_24(INIT_24), + .INIT_25(INIT_25), + .INIT_26(INIT_26), + .INIT_27(INIT_27), + .INIT_28(INIT_28), + .INIT_29(INIT_29), + .INIT_2A(INIT_2A), + .INIT_2B(INIT_2B), + .INIT_2C(INIT_2C), + .INIT_2D(INIT_2D), + .INIT_2E(INIT_2E), + .INIT_2F(INIT_2F), + .INIT_30(INIT_30), + .INIT_31(INIT_31), + .INIT_32(INIT_32), + .INIT_33(INIT_33), + .INIT_34(INIT_34), + .INIT_35(INIT_35), + .INIT_36(INIT_36), + .INIT_37(INIT_37), + .INIT_38(INIT_38), + .INIT_39(INIT_39), + .INIT_3A(INIT_3A), + .INIT_3B(INIT_3B), + .INIT_3C(INIT_3C), + .INIT_3D(INIT_3D), + .INIT_3E(INIT_3E), + .INIT_3F(INIT_3F), + .INIT_40(INIT_40), + .INIT_41(INIT_41), + .INIT_42(INIT_42), + .INIT_43(INIT_43), + .INIT_44(INIT_44), + .INIT_45(INIT_45), + .INIT_46(INIT_46), + .INIT_47(INIT_47), + .INIT_48(INIT_48), + .INIT_49(INIT_49), + .INIT_4A(INIT_4A), + .INIT_4B(INIT_4B), + .INIT_4C(INIT_4C), + .INIT_4D(INIT_4D), + .INIT_4E(INIT_4E), + .INIT_4F(INIT_4F), + .INIT_50(INIT_50), + .INIT_51(INIT_51), + .INIT_52(INIT_52), + .INIT_53(INIT_53), + .INIT_54(INIT_54), + .INIT_55(INIT_55), + .INIT_56(INIT_56), + .INIT_57(INIT_57), + .INIT_58(INIT_58), + .INIT_59(INIT_59), + .INIT_5A(INIT_5A), + .INIT_5B(INIT_5B), + .INIT_5C(INIT_5C), + .INIT_5D(INIT_5D), + .INIT_5E(INIT_5E), + .INIT_5F(INIT_5F), + .INIT_60(INIT_60), + .INIT_61(INIT_61), + .INIT_62(INIT_62), + .INIT_63(INIT_63), + .INIT_64(INIT_64), + .INIT_65(INIT_65), + .INIT_66(INIT_66), + .INIT_67(INIT_67), + .INIT_68(INIT_68), + .INIT_69(INIT_69), + .INIT_6A(INIT_6A), + .INIT_6B(INIT_6B), + .INIT_6C(INIT_6C), + .INIT_6D(INIT_6D), + .INIT_6E(INIT_6E), + .INIT_6F(INIT_6F), + .INIT_70(INIT_70), + .INIT_71(INIT_71), + .INIT_72(INIT_72), + .INIT_73(INIT_73), + .INIT_74(INIT_74), + .INIT_75(INIT_75), + .INIT_76(INIT_76), + .INIT_77(INIT_77), + .INIT_78(INIT_78), + .INIT_79(INIT_79), + .INIT_7A(INIT_7A), + .INIT_7B(INIT_7B), + .INIT_7C(INIT_7C), + .INIT_7D(INIT_7D), + .INIT_7E(INIT_7E), + .INIT_7F(INIT_7F), + .INITP_00(INITP_00), + .INITP_01(INITP_01), + .INITP_02(INITP_02), + .INITP_03(INITP_03), + .INITP_04(INITP_04), + .INITP_05(INITP_05), + .INITP_06(INITP_06), + .INITP_07(INITP_07), + .INITP_08(INITP_08), + .INITP_09(INITP_09), + .INITP_0A(INITP_0A), + .INITP_0B(INITP_0B), + .INITP_0C(INITP_0C), + .INITP_0D(INITP_0D), + .INITP_0E(INITP_0E), + .INITP_0F(INITP_0F)) + + INT_RAMB_TDP (.ADDRA(ADDRARDADDR), + .ADDRB(ADDRBWRADDR), + .CASCADEINA(CASCADEINA), + .CASCADEINB(CASCADEINB), + .CASCADEOUTA(CASCADEOUTA), + .CASCADEOUTB(CASCADEOUTB), + .CLKA(CLKARDCLK), + .CLKB(CLKBWRCLK), + .DBITERR(DBITERR), + .DIA({32'b0,DIADI}), + .DIB({32'b0,DIBDI}), + .DIPA(DIPADIP), + .DIPB({4'b0,DIPBDIP}), + .DOA({dangle_out32,DOADO}), + .DOB(DOBDO), + .DOPA({dangle_out4,DOPADOP}), + .DOPB(DOPBDOP), + .ECCPARITY(ECCPARITY), + .ENA(ENARDEN), + .ENB(ENBWREN), + .GSR(GSR), + .INJECTDBITERR(1'b0), + .INJECTSBITERR(1'b0), + .RDADDRECC(RDADDRECC), + .REGCEA(REGCEAREGCE), + .REGCEB(REGCEB), + .RSTRAMA(RSTRAMARSTRAM), + .RSTRAMB(RSTRAMB), + .RSTREGA(RSTREGARSTREG), + .RSTREGB(RSTREGB), + .SBITERR(SBITERR), + .WEA({2{WEA}}), + .WEB(WEBWE)); + + end // case: "TDP" + "SDP" : begin + + if (WRITE_WIDTH_B == 72) begin + + RB36_INTERNAL_VLOG #(.RAM_MODE(RAM_MODE), + .INIT_A(init_sdp), + .INIT_B(init_sdp), + .INIT_FILE(INIT_FILE), + .SRVAL_A(srval_sdp), + .SRVAL_B(srval_sdp), + .READ_WIDTH_A(READ_WIDTH_A), + .READ_WIDTH_B(READ_WIDTH_B), + .WRITE_WIDTH_A(WRITE_WIDTH_A), + .WRITE_WIDTH_B(WRITE_WIDTH_B), + .WRITE_MODE_A(WRITE_MODE_A), + .WRITE_MODE_B(WRITE_MODE_B), + .RAM_EXTENSION_A(RAM_EXTENSION_A), + .RAM_EXTENSION_B(RAM_EXTENSION_B), + .RDADDR_COLLISION_HWCONFIG(RDADDR_COLLISION_HWCONFIG), + .SETUP_ALL(SETUP_ALL), + .SETUP_READ_FIRST(SETUP_READ_FIRST), + .SIM_COLLISION_CHECK(SIM_COLLISION_CHECK), + .EN_ECC_READ(EN_ECC_READ), + .EN_ECC_WRITE(EN_ECC_WRITE), + .DOA_REG(DOA_REG), + .DOB_REG(DOB_REG), + .RSTREG_PRIORITY_A(RSTREG_PRIORITY_A), + .RSTREG_PRIORITY_B(RSTREG_PRIORITY_B), + .INIT_00(INIT_00), + .INIT_01(INIT_01), + .INIT_02(INIT_02), + .INIT_03(INIT_03), + .INIT_04(INIT_04), + .INIT_05(INIT_05), + .INIT_06(INIT_06), + .INIT_07(INIT_07), + .INIT_08(INIT_08), + .INIT_09(INIT_09), + .INIT_0A(INIT_0A), + .INIT_0B(INIT_0B), + .INIT_0C(INIT_0C), + .INIT_0D(INIT_0D), + .INIT_0E(INIT_0E), + .INIT_0F(INIT_0F), + .INIT_10(INIT_10), + .INIT_11(INIT_11), + .INIT_12(INIT_12), + .INIT_13(INIT_13), + .INIT_14(INIT_14), + .INIT_15(INIT_15), + .INIT_16(INIT_16), + .INIT_17(INIT_17), + .INIT_18(INIT_18), + .INIT_19(INIT_19), + .INIT_1A(INIT_1A), + .INIT_1B(INIT_1B), + .INIT_1C(INIT_1C), + .INIT_1D(INIT_1D), + .INIT_1E(INIT_1E), + .INIT_1F(INIT_1F), + .INIT_20(INIT_20), + .INIT_21(INIT_21), + .INIT_22(INIT_22), + .INIT_23(INIT_23), + .INIT_24(INIT_24), + .INIT_25(INIT_25), + .INIT_26(INIT_26), + .INIT_27(INIT_27), + .INIT_28(INIT_28), + .INIT_29(INIT_29), + .INIT_2A(INIT_2A), + .INIT_2B(INIT_2B), + .INIT_2C(INIT_2C), + .INIT_2D(INIT_2D), + .INIT_2E(INIT_2E), + .INIT_2F(INIT_2F), + .INIT_30(INIT_30), + .INIT_31(INIT_31), + .INIT_32(INIT_32), + .INIT_33(INIT_33), + .INIT_34(INIT_34), + .INIT_35(INIT_35), + .INIT_36(INIT_36), + .INIT_37(INIT_37), + .INIT_38(INIT_38), + .INIT_39(INIT_39), + .INIT_3A(INIT_3A), + .INIT_3B(INIT_3B), + .INIT_3C(INIT_3C), + .INIT_3D(INIT_3D), + .INIT_3E(INIT_3E), + .INIT_3F(INIT_3F), + .INIT_40(INIT_40), + .INIT_41(INIT_41), + .INIT_42(INIT_42), + .INIT_43(INIT_43), + .INIT_44(INIT_44), + .INIT_45(INIT_45), + .INIT_46(INIT_46), + .INIT_47(INIT_47), + .INIT_48(INIT_48), + .INIT_49(INIT_49), + .INIT_4A(INIT_4A), + .INIT_4B(INIT_4B), + .INIT_4C(INIT_4C), + .INIT_4D(INIT_4D), + .INIT_4E(INIT_4E), + .INIT_4F(INIT_4F), + .INIT_50(INIT_50), + .INIT_51(INIT_51), + .INIT_52(INIT_52), + .INIT_53(INIT_53), + .INIT_54(INIT_54), + .INIT_55(INIT_55), + .INIT_56(INIT_56), + .INIT_57(INIT_57), + .INIT_58(INIT_58), + .INIT_59(INIT_59), + .INIT_5A(INIT_5A), + .INIT_5B(INIT_5B), + .INIT_5C(INIT_5C), + .INIT_5D(INIT_5D), + .INIT_5E(INIT_5E), + .INIT_5F(INIT_5F), + .INIT_60(INIT_60), + .INIT_61(INIT_61), + .INIT_62(INIT_62), + .INIT_63(INIT_63), + .INIT_64(INIT_64), + .INIT_65(INIT_65), + .INIT_66(INIT_66), + .INIT_67(INIT_67), + .INIT_68(INIT_68), + .INIT_69(INIT_69), + .INIT_6A(INIT_6A), + .INIT_6B(INIT_6B), + .INIT_6C(INIT_6C), + .INIT_6D(INIT_6D), + .INIT_6E(INIT_6E), + .INIT_6F(INIT_6F), + .INIT_70(INIT_70), + .INIT_71(INIT_71), + .INIT_72(INIT_72), + .INIT_73(INIT_73), + .INIT_74(INIT_74), + .INIT_75(INIT_75), + .INIT_76(INIT_76), + .INIT_77(INIT_77), + .INIT_78(INIT_78), + .INIT_79(INIT_79), + .INIT_7A(INIT_7A), + .INIT_7B(INIT_7B), + .INIT_7C(INIT_7C), + .INIT_7D(INIT_7D), + .INIT_7E(INIT_7E), + .INIT_7F(INIT_7F), + .INITP_00(INITP_00), + .INITP_01(INITP_01), + .INITP_02(INITP_02), + .INITP_03(INITP_03), + .INITP_04(INITP_04), + .INITP_05(INITP_05), + .INITP_06(INITP_06), + .INITP_07(INITP_07), + .INITP_08(INITP_08), + .INITP_09(INITP_09), + .INITP_0A(INITP_0A), + .INITP_0B(INITP_0B), + .INITP_0C(INITP_0C), + .INITP_0D(INITP_0D), + .INITP_0E(INITP_0E), + .INITP_0F(INITP_0F)) + + INT_RAMB_SDP (.ADDRA(ADDRARDADDR), + .ADDRB(ADDRBWRADDR), + .CASCADEINA(CASCADEINA), + .CASCADEINB(CASCADEINB), + .CASCADEOUTA(CASCADEOUTA), + .CASCADEOUTB(CASCADEOUTB), + .CLKA(CLKARDCLK), + .CLKB(CLKBWRCLK), + .DBITERR(DBITERR), + .DIA(64'b0), + .DIB({DIBDI,DIADI}), + .DIPA(4'b0), + .DIPB({DIPBDIP,DIPADIP}), + .DOA({DOBDO,DOADO}), + .DOB(dangle_out32), + .DOPA({DOPBDOP,DOPADOP}), + .DOPB(dangle_out4), + .ECCPARITY(ECCPARITY), + .ENA(ENARDEN), + .ENB(ENBWREN), + .GSR(GSR), + .INJECTDBITERR(INJECTDBITERR), + .INJECTSBITERR(INJECTSBITERR), + .RDADDRECC(RDADDRECC), + .REGCEA(REGCEAREGCE), + .REGCEB(REGCEB), + .RSTRAMA(RSTRAMARSTRAM), + .RSTRAMB(RSTRAMB), + .RSTREGA(RSTREGARSTREG), + .RSTREGB(RSTREGB), + .SBITERR(SBITERR), + .WEA(8'b0), + .WEB(WEBWE)); + + end // if (WRITE_WIDTH_B == 72) + else begin + + RB36_INTERNAL_VLOG #(.RAM_MODE(RAM_MODE), + .INIT_A(init_sdp), + .INIT_B(init_sdp), + .INIT_FILE(INIT_FILE), + .SRVAL_A(srval_sdp), + .SRVAL_B(srval_sdp), + .READ_WIDTH_A(READ_WIDTH_A), + .READ_WIDTH_B(READ_WIDTH_B), + .WRITE_WIDTH_A(WRITE_WIDTH_A), + .WRITE_WIDTH_B(WRITE_WIDTH_B), + .WRITE_MODE_A(WRITE_MODE_A), + .WRITE_MODE_B(WRITE_MODE_B), + .RAM_EXTENSION_A(RAM_EXTENSION_A), + .RAM_EXTENSION_B(RAM_EXTENSION_B), + .RDADDR_COLLISION_HWCONFIG(RDADDR_COLLISION_HWCONFIG), + .SETUP_ALL(SETUP_ALL), + .SETUP_READ_FIRST(SETUP_READ_FIRST), + .SIM_COLLISION_CHECK(SIM_COLLISION_CHECK), + .EN_ECC_READ(EN_ECC_READ), + .EN_ECC_WRITE(EN_ECC_WRITE), + .DOA_REG(DOA_REG), + .DOB_REG(DOB_REG), + .RSTREG_PRIORITY_A(RSTREG_PRIORITY_A), + .RSTREG_PRIORITY_B(RSTREG_PRIORITY_B), + .INIT_00(INIT_00), + .INIT_01(INIT_01), + .INIT_02(INIT_02), + .INIT_03(INIT_03), + .INIT_04(INIT_04), + .INIT_05(INIT_05), + .INIT_06(INIT_06), + .INIT_07(INIT_07), + .INIT_08(INIT_08), + .INIT_09(INIT_09), + .INIT_0A(INIT_0A), + .INIT_0B(INIT_0B), + .INIT_0C(INIT_0C), + .INIT_0D(INIT_0D), + .INIT_0E(INIT_0E), + .INIT_0F(INIT_0F), + .INIT_10(INIT_10), + .INIT_11(INIT_11), + .INIT_12(INIT_12), + .INIT_13(INIT_13), + .INIT_14(INIT_14), + .INIT_15(INIT_15), + .INIT_16(INIT_16), + .INIT_17(INIT_17), + .INIT_18(INIT_18), + .INIT_19(INIT_19), + .INIT_1A(INIT_1A), + .INIT_1B(INIT_1B), + .INIT_1C(INIT_1C), + .INIT_1D(INIT_1D), + .INIT_1E(INIT_1E), + .INIT_1F(INIT_1F), + .INIT_20(INIT_20), + .INIT_21(INIT_21), + .INIT_22(INIT_22), + .INIT_23(INIT_23), + .INIT_24(INIT_24), + .INIT_25(INIT_25), + .INIT_26(INIT_26), + .INIT_27(INIT_27), + .INIT_28(INIT_28), + .INIT_29(INIT_29), + .INIT_2A(INIT_2A), + .INIT_2B(INIT_2B), + .INIT_2C(INIT_2C), + .INIT_2D(INIT_2D), + .INIT_2E(INIT_2E), + .INIT_2F(INIT_2F), + .INIT_30(INIT_30), + .INIT_31(INIT_31), + .INIT_32(INIT_32), + .INIT_33(INIT_33), + .INIT_34(INIT_34), + .INIT_35(INIT_35), + .INIT_36(INIT_36), + .INIT_37(INIT_37), + .INIT_38(INIT_38), + .INIT_39(INIT_39), + .INIT_3A(INIT_3A), + .INIT_3B(INIT_3B), + .INIT_3C(INIT_3C), + .INIT_3D(INIT_3D), + .INIT_3E(INIT_3E), + .INIT_3F(INIT_3F), + .INIT_40(INIT_40), + .INIT_41(INIT_41), + .INIT_42(INIT_42), + .INIT_43(INIT_43), + .INIT_44(INIT_44), + .INIT_45(INIT_45), + .INIT_46(INIT_46), + .INIT_47(INIT_47), + .INIT_48(INIT_48), + .INIT_49(INIT_49), + .INIT_4A(INIT_4A), + .INIT_4B(INIT_4B), + .INIT_4C(INIT_4C), + .INIT_4D(INIT_4D), + .INIT_4E(INIT_4E), + .INIT_4F(INIT_4F), + .INIT_50(INIT_50), + .INIT_51(INIT_51), + .INIT_52(INIT_52), + .INIT_53(INIT_53), + .INIT_54(INIT_54), + .INIT_55(INIT_55), + .INIT_56(INIT_56), + .INIT_57(INIT_57), + .INIT_58(INIT_58), + .INIT_59(INIT_59), + .INIT_5A(INIT_5A), + .INIT_5B(INIT_5B), + .INIT_5C(INIT_5C), + .INIT_5D(INIT_5D), + .INIT_5E(INIT_5E), + .INIT_5F(INIT_5F), + .INIT_60(INIT_60), + .INIT_61(INIT_61), + .INIT_62(INIT_62), + .INIT_63(INIT_63), + .INIT_64(INIT_64), + .INIT_65(INIT_65), + .INIT_66(INIT_66), + .INIT_67(INIT_67), + .INIT_68(INIT_68), + .INIT_69(INIT_69), + .INIT_6A(INIT_6A), + .INIT_6B(INIT_6B), + .INIT_6C(INIT_6C), + .INIT_6D(INIT_6D), + .INIT_6E(INIT_6E), + .INIT_6F(INIT_6F), + .INIT_70(INIT_70), + .INIT_71(INIT_71), + .INIT_72(INIT_72), + .INIT_73(INIT_73), + .INIT_74(INIT_74), + .INIT_75(INIT_75), + .INIT_76(INIT_76), + .INIT_77(INIT_77), + .INIT_78(INIT_78), + .INIT_79(INIT_79), + .INIT_7A(INIT_7A), + .INIT_7B(INIT_7B), + .INIT_7C(INIT_7C), + .INIT_7D(INIT_7D), + .INIT_7E(INIT_7E), + .INIT_7F(INIT_7F), + .INITP_00(INITP_00), + .INITP_01(INITP_01), + .INITP_02(INITP_02), + .INITP_03(INITP_03), + .INITP_04(INITP_04), + .INITP_05(INITP_05), + .INITP_06(INITP_06), + .INITP_07(INITP_07), + .INITP_08(INITP_08), + .INITP_09(INITP_09), + .INITP_0A(INITP_0A), + .INITP_0B(INITP_0B), + .INITP_0C(INITP_0C), + .INITP_0D(INITP_0D), + .INITP_0E(INITP_0E), + .INITP_0F(INITP_0F)) + + INT_RAMB_SDP (.ADDRA(ADDRARDADDR), + .ADDRB(ADDRBWRADDR), + .CASCADEINA(CASCADEINA), + .CASCADEINB(CASCADEINB), + .CASCADEOUTA(CASCADEOUTA), + .CASCADEOUTB(CASCADEOUTB), + .CLKA(CLKARDCLK), + .CLKB(CLKBWRCLK), + .DBITERR(DBITERR), + .DIA(64'b0), + .DIB({32'b0,DIBDI}), + .DIPA(4'b0), + .DIPB({4'b0,DIPBDIP}), + .DOA({DOBDO,DOADO}), + .DOB(dangle_out32), + .DOPA({DOPBDOP,DOPADOP}), + .DOPB(dangle_out4), + .ECCPARITY(ECCPARITY), + .ENA(ENARDEN), + .ENB(ENBWREN), + .GSR(GSR), + .INJECTDBITERR(INJECTDBITERR), + .INJECTSBITERR(INJECTSBITERR), + .RDADDRECC(RDADDRECC), + .REGCEA(REGCEAREGCE), + .REGCEB(REGCEB), + .RSTRAMA(RSTRAMARSTRAM), + .RSTRAMB(RSTRAMB), + .RSTREGA(RSTREGARSTREG), + .RSTREGB(RSTREGB), + .SBITERR(SBITERR), + .WEA(8'b0), + .WEB(WEBWE)); + + end // else: !if(WRITE_WIDTH_B == 72) + + end // case: "SDP" + + endcase // case(RAM_MODE) + endgenerate + + + + specify + + (CLKARDCLK => DOADO[0]) = (100, 100); + (CLKARDCLK => DOADO[1]) = (100, 100); + (CLKARDCLK => DOADO[2]) = (100, 100); + (CLKARDCLK => DOADO[3]) = (100, 100); + (CLKARDCLK => DOADO[4]) = (100, 100); + (CLKARDCLK => DOADO[5]) = (100, 100); + (CLKARDCLK => DOADO[6]) = (100, 100); + (CLKARDCLK => DOADO[7]) = (100, 100); + (CLKARDCLK => DOADO[8]) = (100, 100); + (CLKARDCLK => DOADO[9]) = (100, 100); + (CLKARDCLK => DOADO[10]) = (100, 100); + (CLKARDCLK => DOADO[11]) = (100, 100); + (CLKARDCLK => DOADO[12]) = (100, 100); + (CLKARDCLK => DOADO[13]) = (100, 100); + (CLKARDCLK => DOADO[14]) = (100, 100); + (CLKARDCLK => DOADO[15]) = (100, 100); + (CLKARDCLK => DOADO[16]) = (100, 100); + (CLKARDCLK => DOADO[17]) = (100, 100); + (CLKARDCLK => DOADO[18]) = (100, 100); + (CLKARDCLK => DOADO[19]) = (100, 100); + (CLKARDCLK => DOADO[20]) = (100, 100); + (CLKARDCLK => DOADO[21]) = (100, 100); + (CLKARDCLK => DOADO[22]) = (100, 100); + (CLKARDCLK => DOADO[23]) = (100, 100); + (CLKARDCLK => DOADO[24]) = (100, 100); + (CLKARDCLK => DOADO[25]) = (100, 100); + (CLKARDCLK => DOADO[26]) = (100, 100); + (CLKARDCLK => DOADO[27]) = (100, 100); + (CLKARDCLK => DOADO[28]) = (100, 100); + (CLKARDCLK => DOADO[29]) = (100, 100); + (CLKARDCLK => DOADO[30]) = (100, 100); + (CLKARDCLK => DOADO[31]) = (100, 100); + (CLKARDCLK => DOPADOP[0]) = (100, 100); + (CLKARDCLK => DOPADOP[1]) = (100, 100); + (CLKARDCLK => DOPADOP[2]) = (100, 100); + (CLKARDCLK => DOPADOP[3]) = (100, 100); + (CLKARDCLK => RDADDRECC[0]) = (100, 100); + (CLKARDCLK => RDADDRECC[1]) = (100, 100); + (CLKARDCLK => RDADDRECC[2]) = (100, 100); + (CLKARDCLK => RDADDRECC[3]) = (100, 100); + (CLKARDCLK => RDADDRECC[4]) = (100, 100); + (CLKARDCLK => RDADDRECC[5]) = (100, 100); + (CLKARDCLK => RDADDRECC[6]) = (100, 100); + (CLKARDCLK => RDADDRECC[7]) = (100, 100); + (CLKARDCLK => RDADDRECC[8]) = (100, 100); + (CLKARDCLK => DBITERR) = (100, 100); + (CLKARDCLK => SBITERR) = (100, 100); + + if (RAM_MODE == "SDP") (CLKARDCLK => DOBDO[0]) = (100, 100); + if (RAM_MODE == "SDP") (CLKARDCLK => DOBDO[1]) = (100, 100); + if (RAM_MODE == "SDP") (CLKARDCLK => DOBDO[2]) = (100, 100); + if (RAM_MODE == "SDP") (CLKARDCLK => DOBDO[3]) = (100, 100); + if (RAM_MODE == "SDP") (CLKARDCLK => DOBDO[4]) = (100, 100); + if (RAM_MODE == "SDP") (CLKARDCLK => DOBDO[5]) = (100, 100); + if (RAM_MODE == "SDP") (CLKARDCLK => DOBDO[6]) = (100, 100); + if (RAM_MODE == "SDP") (CLKARDCLK => DOBDO[7]) = (100, 100); + if (RAM_MODE == "SDP") (CLKARDCLK => DOBDO[8]) = (100, 100); + if (RAM_MODE == "SDP") (CLKARDCLK => DOBDO[9]) = (100, 100); + if (RAM_MODE == "SDP") (CLKARDCLK => DOBDO[10]) = (100, 100); + if (RAM_MODE == "SDP") (CLKARDCLK => DOBDO[11]) = (100, 100); + if (RAM_MODE == "SDP") (CLKARDCLK => DOBDO[12]) = (100, 100); + if (RAM_MODE == "SDP") (CLKARDCLK => DOBDO[13]) = (100, 100); + if (RAM_MODE == "SDP") (CLKARDCLK => DOBDO[14]) = (100, 100); + if (RAM_MODE == "SDP") (CLKARDCLK => DOBDO[15]) = (100, 100); + if (RAM_MODE == "SDP") (CLKARDCLK => DOBDO[16]) = (100, 100); + if (RAM_MODE == "SDP") (CLKARDCLK => DOBDO[17]) = (100, 100); + if (RAM_MODE == "SDP") (CLKARDCLK => DOBDO[18]) = (100, 100); + if (RAM_MODE == "SDP") (CLKARDCLK => DOBDO[19]) = (100, 100); + if (RAM_MODE == "SDP") (CLKARDCLK => DOBDO[20]) = (100, 100); + if (RAM_MODE == "SDP") (CLKARDCLK => DOBDO[21]) = (100, 100); + if (RAM_MODE == "SDP") (CLKARDCLK => DOBDO[22]) = (100, 100); + if (RAM_MODE == "SDP") (CLKARDCLK => DOBDO[23]) = (100, 100); + if (RAM_MODE == "SDP") (CLKARDCLK => DOBDO[24]) = (100, 100); + if (RAM_MODE == "SDP") (CLKARDCLK => DOBDO[25]) = (100, 100); + if (RAM_MODE == "SDP") (CLKARDCLK => DOBDO[26]) = (100, 100); + if (RAM_MODE == "SDP") (CLKARDCLK => DOBDO[27]) = (100, 100); + if (RAM_MODE == "SDP") (CLKARDCLK => DOBDO[28]) = (100, 100); + if (RAM_MODE == "SDP") (CLKARDCLK => DOBDO[29]) = (100, 100); + if (RAM_MODE == "SDP") (CLKARDCLK => DOBDO[30]) = (100, 100); + if (RAM_MODE == "SDP") (CLKARDCLK => DOBDO[31]) = (100, 100); + if (RAM_MODE == "SDP") (CLKARDCLK => DOPBDOP[0]) = (100, 100); + if (RAM_MODE == "SDP") (CLKARDCLK => DOPBDOP[1]) = (100, 100); + if (RAM_MODE == "SDP") (CLKARDCLK => DOPBDOP[2]) = (100, 100); + if (RAM_MODE == "SDP") (CLKARDCLK => DOPBDOP[3]) = (100, 100); + + if (RAM_MODE == "TDP") (CLKBWRCLK => DOBDO[0]) = (100, 100); + if (RAM_MODE == "TDP") (CLKBWRCLK => DOBDO[1]) = (100, 100); + if (RAM_MODE == "TDP") (CLKBWRCLK => DOBDO[2]) = (100, 100); + if (RAM_MODE == "TDP") (CLKBWRCLK => DOBDO[3]) = (100, 100); + if (RAM_MODE == "TDP") (CLKBWRCLK => DOBDO[4]) = (100, 100); + if (RAM_MODE == "TDP") (CLKBWRCLK => DOBDO[5]) = (100, 100); + if (RAM_MODE == "TDP") (CLKBWRCLK => DOBDO[6]) = (100, 100); + if (RAM_MODE == "TDP") (CLKBWRCLK => DOBDO[7]) = (100, 100); + if (RAM_MODE == "TDP") (CLKBWRCLK => DOBDO[8]) = (100, 100); + if (RAM_MODE == "TDP") (CLKBWRCLK => DOBDO[9]) = (100, 100); + if (RAM_MODE == "TDP") (CLKBWRCLK => DOBDO[10]) = (100, 100); + if (RAM_MODE == "TDP") (CLKBWRCLK => DOBDO[11]) = (100, 100); + if (RAM_MODE == "TDP") (CLKBWRCLK => DOBDO[12]) = (100, 100); + if (RAM_MODE == "TDP") (CLKBWRCLK => DOBDO[13]) = (100, 100); + if (RAM_MODE == "TDP") (CLKBWRCLK => DOBDO[14]) = (100, 100); + if (RAM_MODE == "TDP") (CLKBWRCLK => DOBDO[15]) = (100, 100); + if (RAM_MODE == "TDP") (CLKBWRCLK => DOBDO[16]) = (100, 100); + if (RAM_MODE == "TDP") (CLKBWRCLK => DOBDO[17]) = (100, 100); + if (RAM_MODE == "TDP") (CLKBWRCLK => DOBDO[18]) = (100, 100); + if (RAM_MODE == "TDP") (CLKBWRCLK => DOBDO[19]) = (100, 100); + if (RAM_MODE == "TDP") (CLKBWRCLK => DOBDO[20]) = (100, 100); + if (RAM_MODE == "TDP") (CLKBWRCLK => DOBDO[21]) = (100, 100); + if (RAM_MODE == "TDP") (CLKBWRCLK => DOBDO[22]) = (100, 100); + if (RAM_MODE == "TDP") (CLKBWRCLK => DOBDO[23]) = (100, 100); + if (RAM_MODE == "TDP") (CLKBWRCLK => DOBDO[24]) = (100, 100); + if (RAM_MODE == "TDP") (CLKBWRCLK => DOBDO[25]) = (100, 100); + if (RAM_MODE == "TDP") (CLKBWRCLK => DOBDO[26]) = (100, 100); + if (RAM_MODE == "TDP") (CLKBWRCLK => DOBDO[27]) = (100, 100); + if (RAM_MODE == "TDP") (CLKBWRCLK => DOBDO[28]) = (100, 100); + if (RAM_MODE == "TDP") (CLKBWRCLK => DOBDO[29]) = (100, 100); + if (RAM_MODE == "TDP") (CLKBWRCLK => DOBDO[30]) = (100, 100); + if (RAM_MODE == "TDP") (CLKBWRCLK => DOBDO[31]) = (100, 100); + if (RAM_MODE == "TDP") (CLKBWRCLK => DOPBDOP[0]) = (100, 100); + if (RAM_MODE == "TDP") (CLKBWRCLK => DOPBDOP[1]) = (100, 100); + if (RAM_MODE == "TDP") (CLKBWRCLK => DOPBDOP[2]) = (100, 100); + if (RAM_MODE == "TDP") (CLKBWRCLK => DOPBDOP[3]) = (100, 100); + + (CLKBWRCLK => ECCPARITY[0]) = (100, 100); + (CLKBWRCLK => ECCPARITY[1]) = (100, 100); + (CLKBWRCLK => ECCPARITY[2]) = (100, 100); + (CLKBWRCLK => ECCPARITY[3]) = (100, 100); + (CLKBWRCLK => ECCPARITY[4]) = (100, 100); + (CLKBWRCLK => ECCPARITY[5]) = (100, 100); + (CLKBWRCLK => ECCPARITY[6]) = (100, 100); + (CLKBWRCLK => ECCPARITY[7]) = (100, 100); + + (CASCADEINA => DOADO[0]) = (0, 0); + (CASCADEINB => DOBDO[0]) = (0, 0); + (CLKARDCLK => CASCADEOUTA) = (100, 100); + (CLKBWRCLK => CASCADEOUTB) = (100, 100); + + specparam PATHPULSE$ = 0; + + endspecify + +endmodule // RAMB36E1 + + +// WARNING !!!: The following model is not an user primitive. +// Please do not modify any part of it. RAMB36E1 may not work properly if do so. +// +`timescale 1 ps/1 ps + +module RB36_INTERNAL_VLOG (CASCADEOUTA, CASCADEOUTB, DBITERR, DOA, DOB, DOPA, DOPB, ECCPARITY, RDADDRECC, SBITERR, + ADDRA, ADDRB, CASCADEINA, CASCADEINB, CLKA, CLKB, DIA, DIB, DIPA, DIPB, ENA, ENB, GSR, INJECTDBITERR, INJECTSBITERR, REGCEA, REGCEB, RSTRAMA, RSTRAMB, RSTREGA, RSTREGB, WEA, WEB); + + output CASCADEOUTA; + output CASCADEOUTB; + output SBITERR, DBITERR; + output [8:0] RDADDRECC; + output [63:0] DOA; + output [31:0] DOB; + output [7:0] DOPA; + output [3:0] DOPB; + output [7:0] ECCPARITY; + + input ENA, CLKA, CASCADEINA, REGCEA; + input ENB, CLKB, CASCADEINB, REGCEB; + input GSR; + input RSTRAMA, RSTRAMB; + input RSTREGA, RSTREGB; + input INJECTDBITERR, INJECTSBITERR; + input [15:0] ADDRA; + input [15:0] ADDRB; + input [63:0] DIA; + input [63:0] DIB; + input [3:0] DIPA; + input [7:0] DIPB; + input [7:0] WEA; + input [7:0] WEB; + + parameter DOA_REG = 0; + parameter DOB_REG = 0; + parameter EN_ECC_READ = "FALSE"; + parameter EN_ECC_WRITE = "FALSE"; + parameter INIT_A = 72'h0; + parameter INIT_B = 72'h0; + parameter RAM_EXTENSION_A = "NONE"; + parameter RAM_EXTENSION_B = "NONE"; + parameter RAM_MODE = "TDP"; + parameter RDADDR_COLLISION_HWCONFIG = "DELAYED_WRITE"; + parameter READ_WIDTH_A = 0; + parameter READ_WIDTH_B = 0; + parameter RSTREG_PRIORITY_A = "RSTREG"; + parameter RSTREG_PRIORITY_B = "RSTREG"; + parameter SETUP_ALL = 1000; + parameter SETUP_READ_FIRST = 3000; + parameter SIM_COLLISION_CHECK = "ALL"; + parameter SRVAL_A = 72'h0; + parameter SRVAL_B = 72'h0; + parameter WRITE_MODE_A = "WRITE_FIRST"; + parameter WRITE_MODE_B = "WRITE_FIRST"; + parameter WRITE_WIDTH_A = 0; + parameter WRITE_WIDTH_B = 0; + parameter INIT_FILE = "NONE"; + + parameter INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_40 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_41 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_42 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_43 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_44 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_45 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_46 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_47 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_48 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_49 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_4A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_4B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_4C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_4D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_4E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_4F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_50 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_51 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_52 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_53 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_54 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_55 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_56 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_57 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_58 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_59 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_5A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_5B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_5C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_5D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_5E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_5F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_60 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_61 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_62 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_63 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_64 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_65 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_66 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_67 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_68 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_69 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_6A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_6B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_6C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_6D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_6E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_6F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_70 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_71 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_72 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_73 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_74 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_75 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_76 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_77 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_78 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_79 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_7A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_7B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_7C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_7D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_7E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_7F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + +// xilinx_internal_parameter on + // WARNING !!!: This model may not work properly if the following parameters are changed. + parameter BRAM_SIZE = 36; +// xilinx_internal_parameter off + + + integer count, countp, init_mult, initp_mult, large_width; + integer count1, countp1, i, i1, i_p, i_mem, init_offset, initp_offset; + integer viol_time = 0; + integer rdaddr_collision_hwconfig_int, rstreg_priority_a_int, rstreg_priority_b_int; + integer ram_mode_int, en_ecc_write_int, en_ecc_read_int; + + reg addra_in_15_reg_bram, addrb_in_15_reg_bram; + reg addra_in_15_reg, addrb_in_15_reg; + reg addra_in_15_reg1, addrb_in_15_reg1; + reg junk1; + reg [1:0] wr_mode_a, wr_mode_b, cascade_a, cascade_b; + reg [63:0] doa_out = 64'b0, doa_buf = 64'b0, doa_outreg = 64'b0, doa_out_out; + reg [31:0] dob_out = 32'b0, dob_buf = 32'b0, dob_outreg = 32'b0, dob_out_out; + reg [3:0] dopb_out = 4'b0, dopb_buf = 4'b0, dopb_outreg = 4'b0, dopb_out_out; + reg [7:0] dopa_out = 8'b0, dopa_buf = 8'b0, dopa_outreg = 8'b0, dopa_out_out; + reg [63:0] doa_out_mux = 64'b0, doa_outreg_mux = 64'b0; + reg [7:0] dopa_out_mux = 8'b0, dopa_outreg_mux = 8'b0; + reg [63:0] dob_out_mux = 64'b0, dob_outreg_mux = 64'b0; + reg [7:0] dopb_out_mux = 8'b0, dopb_outreg_mux = 8'b0; + + reg [7:0] eccparity_out = 8'b0; + reg [7:0] dopr_ecc, syndrome = 8'b0; + reg [7:0] dipb_in_ecc; + reg [71:0] ecc_bit_position; + reg [7:0] dip_ecc, dip_ecc_col, dipa_in_ecc_corrected; + reg [63:0] dib_in_ecc, dib_ecc_col, dia_in_ecc_corrected, di_x = 64'bx; + reg dbiterr_out = 0, sbiterr_out = 0; + reg dbiterr_outreg = 0, sbiterr_outreg = 0; + reg dbiterr_out_out = 0, sbiterr_out_out = 0; + + reg [7:0] wea_reg; + reg enb_reg; + reg [7:0] out_a = 8'b0, out_b = 8'b0, junk, web_reg, web_tmp; + reg outp_a = 1'b0, outp_b = 1'b0, junkp; + reg rising_clka = 1'b0, rising_clkb = 1'b0; + reg [15:0] addra_reg, addrb_reg, addra_tmp, addrb_tmp; + + reg [63:0] dia_reg, dib_reg; + reg [3:0] dipa_reg; + reg [7:0] dipb_reg; + reg [1:0] viol_type = 2'b00, seq = 2'b00; + reg [15:0] addr_tmp; + reg [7:0] we_tmp; + reg col_wr_wr_msg = 1, col_wra_rdb_msg = 1, col_wrb_rda_msg = 1; + reg [7:0] no_col = 8'b0; + reg [8:0] rdaddrecc_out = 9'b0, rdaddrecc_outreg = 9'b0; + reg [8:0] rdaddrecc_out_out = 9'b0; + reg finish_error = 0; + + time time_port_a, time_port_b; + + wire [63:0] dib_in; + wire [63:0] dia_in; + wire [15:0] addra_in, addrb_in; + wire clka_in, clkb_in; + wire [7:0] dipb_in; + wire [3:0] dipa_in; + wire ena_in, enb_in, gsr_in, regcea_in, regceb_in, rstrama_in, rstramb_in; + wire [7:0] wea_in; + wire [7:0] web_in; + wire cascadeina_in, cascadeinb_in; + wire injectdbiterr_in, injectsbiterr_in; + wire rstrega_in, rstregb_in; + wire [15:0] col_addra_reconstruct, col_addrb_reconstruct; + reg [15:0] col_addra_reconstruct_reg, col_addrb_reconstruct_reg; + + wire temp_wire; // trigger NCsim at initial time + assign temp_wire = 1; + + + assign addra_in = ADDRA; + assign addrb_in = ADDRB; + assign clka_in = CLKA; + assign clkb_in = CLKB; + + assign dia_in = DIA; + assign dib_in = DIB; + assign dipa_in = DIPA; + assign dipb_in = DIPB; + assign DOA = doa_out_out; + + assign DOPA = dopa_out_out; + assign DOB = dob_out_out; + assign DOPB = dopb_out_out; + + assign ena_in = ENA; + assign enb_in = ENB; + assign gsr_in = GSR; + assign regcea_in = REGCEA; + assign regceb_in = REGCEB; + assign rstrama_in = RSTRAMA; + assign rstramb_in = RSTRAMB; + assign wea_in = WEA; + assign web_in = WEB; + assign cascadeina_in = CASCADEINA; + assign cascadeinb_in = CASCADEINB; + assign CASCADEOUTA = doa_out_out[0]; + assign CASCADEOUTB = dob_out_out[0]; + assign SBITERR = sbiterr_out_out; + assign DBITERR = dbiterr_out_out; + assign ECCPARITY = eccparity_out; + assign RDADDRECC = rdaddrecc_out_out; + assign injectdbiterr_in = INJECTDBITERR; + assign injectsbiterr_in = INJECTSBITERR; + assign rstrega_in = RSTREGA; + assign rstregb_in = RSTREGB; + + + // Determine memory size + localparam widest_width = (WRITE_WIDTH_A >= WRITE_WIDTH_B && WRITE_WIDTH_A >= READ_WIDTH_A && + WRITE_WIDTH_A >= READ_WIDTH_B) ? WRITE_WIDTH_A : + (WRITE_WIDTH_B >= WRITE_WIDTH_A && WRITE_WIDTH_B >= READ_WIDTH_A && + WRITE_WIDTH_B >= READ_WIDTH_B) ? WRITE_WIDTH_B : + (READ_WIDTH_A >= WRITE_WIDTH_A && READ_WIDTH_A >= WRITE_WIDTH_B && + READ_WIDTH_A >= READ_WIDTH_B) ? READ_WIDTH_A : + (READ_WIDTH_B >= WRITE_WIDTH_A && READ_WIDTH_B >= WRITE_WIDTH_B && + READ_WIDTH_B >= READ_WIDTH_A) ? READ_WIDTH_B : 64; + + localparam wa_width = (WRITE_WIDTH_A == 1) ? 1 : (WRITE_WIDTH_A == 2) ? 2 : (WRITE_WIDTH_A == 4) ? 4 : + (WRITE_WIDTH_A == 9) ? 8 : (WRITE_WIDTH_A == 18) ? 16 : (WRITE_WIDTH_A == 36) ? 32 : + (WRITE_WIDTH_A == 72) ? 64 : 64; + + localparam wb_width = (WRITE_WIDTH_B == 1) ? 1 : (WRITE_WIDTH_B == 2) ? 2 : (WRITE_WIDTH_B == 4) ? 4 : + (WRITE_WIDTH_B == 9) ? 8 : (WRITE_WIDTH_B == 18) ? 16 : (WRITE_WIDTH_B == 36) ? 32 : + (WRITE_WIDTH_B == 72) ? 64 : 64; + + + localparam wa_widthp = (WRITE_WIDTH_A == 9) ? 1 : (WRITE_WIDTH_A == 18) ? 2 : (WRITE_WIDTH_A == 36) ? 4 : + (WRITE_WIDTH_A == 72) ? 8 : 8; + + localparam wb_widthp = (WRITE_WIDTH_B == 9) ? 1 : (WRITE_WIDTH_B == 18) ? 2 : (WRITE_WIDTH_B == 36) ? 4 : + (WRITE_WIDTH_B == 72) ? 8 : 8; + + + localparam ra_width = (READ_WIDTH_A == 1) ? 1 : (READ_WIDTH_A == 2) ? 2 : (READ_WIDTH_A == 4) ? 4 : + (READ_WIDTH_A == 9) ? 8 : (READ_WIDTH_A == 18) ? 16 : (READ_WIDTH_A == 36) ? 32 : + (READ_WIDTH_A == 72) ? 64 : 64; + + localparam rb_width = (READ_WIDTH_B == 1) ? 1 : (READ_WIDTH_B == 2) ? 2 : (READ_WIDTH_B == 4) ? 4 : + (READ_WIDTH_B == 9) ? 8 : (READ_WIDTH_B == 18) ? 16 : (READ_WIDTH_B == 36) ? 32 : + (READ_WIDTH_B == 72) ? 64 : 64; + + + localparam ra_widthp = (READ_WIDTH_A == 9) ? 1 : (READ_WIDTH_A == 18) ? 2 : (READ_WIDTH_A == 36) ? 4 : + (READ_WIDTH_A == 72) ? 8 : 8; + + localparam rb_widthp = (READ_WIDTH_B == 9) ? 1 : (READ_WIDTH_B == 18) ? 2 : (READ_WIDTH_B == 36) ? 4 : + (READ_WIDTH_B == 72) ? 8 : 8; + + localparam col_addr_lsb = (widest_width == 1) ? 0 : (widest_width == 2) ? 1 : (widest_width == 4) ? 2 : + (widest_width == 9) ? 3 : (widest_width == 18) ? 4 : (widest_width == 36) ? 5 : + (widest_width == 72) ? 6 : 0; + + assign col_addra_reconstruct[15:0] = (WRITE_MODE_A == "READ_FIRST" || WRITE_MODE_B == "READ_FIRST") ? + ((BRAM_SIZE == 36) ? {1'b0,addra_in[14:8],2'b0,addra_in[5],4'b0,addra_in[0]} : + (BRAM_SIZE == 18) ? {2'b0,addra_in[13:7],2'b0,addra_in[4],4'b0} : addra_in) : addra_in; + + assign col_addrb_reconstruct[15:0] = (WRITE_MODE_A == "READ_FIRST" || WRITE_MODE_B == "READ_FIRST") ? + ((BRAM_SIZE == 36) ? {1'b0,addrb_in[14:8],2'b0,addrb_in[5],4'b0,addrb_in[0]} : + (BRAM_SIZE == 18) ? {2'b0,addrb_in[13:7],2'b0,addrb_in[4],4'b0} : addrb_in) : addrb_in; + + localparam width = (widest_width == 1) ? 1 : (widest_width == 2) ? 2 : (widest_width == 4) ? 4 : + (widest_width == 9) ? 8 : (widest_width == 18) ? 16 : (widest_width == 36) ? 32 : + (widest_width == 72) ? 64 : 64; + + localparam widthp = (widest_width == 9) ? 1 : (widest_width == 18) ? 2 : (widest_width == 36) ? 4 : + (widest_width == 72) ? 8 : 8; + + + localparam r_addra_lbit_124 = (READ_WIDTH_A == 1) ? 0 : (READ_WIDTH_A == 2) ? 1 : + (READ_WIDTH_A == 4) ? 2 : (READ_WIDTH_A == 9) ? 3 : + (READ_WIDTH_A == 18) ? 4 : (READ_WIDTH_A == 36) ? 5 : + (READ_WIDTH_A == 72) ? 6 : 10; + + localparam r_addrb_lbit_124 = (READ_WIDTH_B == 1) ? 0 : (READ_WIDTH_B == 2) ? 1 : + (READ_WIDTH_B == 4) ? 2 : (READ_WIDTH_B == 9) ? 3 : + (READ_WIDTH_B == 18) ? 4 : (READ_WIDTH_B == 36) ? 5 : + (READ_WIDTH_B == 72) ? 6 : 10; + + localparam addra_lbit_124 = (WRITE_WIDTH_A == 1) ? 0 : (WRITE_WIDTH_A == 2) ? 1 : + (WRITE_WIDTH_A == 4) ? 2 : (WRITE_WIDTH_A == 9) ? 3 : + (WRITE_WIDTH_A == 18) ? 4 : (WRITE_WIDTH_A == 36) ? 5 : + (WRITE_WIDTH_A == 72) ? 6 : 10; + + localparam addrb_lbit_124 = (WRITE_WIDTH_B == 1) ? 0 : (WRITE_WIDTH_B == 2) ? 1 : + (WRITE_WIDTH_B == 4) ? 2 : (WRITE_WIDTH_B == 9) ? 3 : + (WRITE_WIDTH_B == 18) ? 4 : (WRITE_WIDTH_B == 36) ? 5 : + (WRITE_WIDTH_B == 72) ? 6 : 10; + + localparam addra_bit_124 = (WRITE_WIDTH_A == 1 && widest_width == 2) ? 0 : (WRITE_WIDTH_A == 1 && widest_width == 4) ? 1 : + (WRITE_WIDTH_A == 1 && widest_width == 9) ? 2 : (WRITE_WIDTH_A == 1 && widest_width == 18) ? 3 : + (WRITE_WIDTH_A == 1 && widest_width == 36) ? 4 : (WRITE_WIDTH_A == 1 && widest_width == 72) ? 5 : + (WRITE_WIDTH_A == 2 && widest_width == 4) ? 1 : (WRITE_WIDTH_A == 2 && widest_width == 9) ? 2 : + (WRITE_WIDTH_A == 2 && widest_width == 18) ? 3 : (WRITE_WIDTH_A == 2 && widest_width == 36) ? 4 : + (WRITE_WIDTH_A == 2 && widest_width == 72) ? 5 : (WRITE_WIDTH_A == 4 && widest_width == 9) ? 2 : + (WRITE_WIDTH_A == 4 && widest_width == 18) ? 3 : (WRITE_WIDTH_A == 4 && widest_width == 36) ? 4 : + (WRITE_WIDTH_A == 4 && widest_width == 72) ? 5 : 10; + + localparam r_addra_bit_124 = (READ_WIDTH_A == 1 && widest_width == 2) ? 0 : (READ_WIDTH_A == 1 && widest_width == 4) ? 1 : + (READ_WIDTH_A == 1 && widest_width == 9) ? 2 : (READ_WIDTH_A == 1 && widest_width == 18) ? 3 : + (READ_WIDTH_A == 1 && widest_width == 36) ? 4 : (READ_WIDTH_A == 1 && widest_width == 72) ? 5 : + (READ_WIDTH_A == 2 && widest_width == 4) ? 1 : (READ_WIDTH_A == 2 && widest_width == 9) ? 2 : + (READ_WIDTH_A == 2 && widest_width == 18) ? 3 : (READ_WIDTH_A == 2 && widest_width == 36) ? 4 : + (READ_WIDTH_A == 2 && widest_width == 72) ? 5 : (READ_WIDTH_A == 4 && widest_width == 9) ? 2 : + (READ_WIDTH_A == 4 && widest_width == 18) ? 3 : (READ_WIDTH_A == 4 && widest_width == 36) ? 4 : + (READ_WIDTH_A == 4 && widest_width == 72) ? 5 : 10; + + localparam addrb_bit_124 = (WRITE_WIDTH_B == 1 && widest_width == 2) ? 0 : (WRITE_WIDTH_B == 1 && widest_width == 4) ? 1 : + (WRITE_WIDTH_B == 1 && widest_width == 9) ? 2 : (WRITE_WIDTH_B == 1 && widest_width == 18) ? 3 : + (WRITE_WIDTH_B == 1 && widest_width == 36) ? 4 : (WRITE_WIDTH_B == 1 && widest_width == 72) ? 5 : + (WRITE_WIDTH_B == 2 && widest_width == 4) ? 1 : (WRITE_WIDTH_B == 2 && widest_width == 9) ? 2 : + (WRITE_WIDTH_B == 2 && widest_width == 18) ? 3 : (WRITE_WIDTH_B == 2 && widest_width == 36) ? 4 : + (WRITE_WIDTH_B == 2 && widest_width == 72) ? 5 : (WRITE_WIDTH_B == 4 && widest_width == 9) ? 2 : + (WRITE_WIDTH_B == 4 && widest_width == 18) ? 3 : (WRITE_WIDTH_B == 4 && widest_width == 36) ? 4 : + (WRITE_WIDTH_B == 4 && widest_width == 72) ? 5 : 10; + + localparam r_addrb_bit_124 = (READ_WIDTH_B == 1 && widest_width == 2) ? 0 : (READ_WIDTH_B == 1 && widest_width == 4) ? 1 : + (READ_WIDTH_B == 1 && widest_width == 9) ? 2 : (READ_WIDTH_B == 1 && widest_width == 18) ? 3 : + (READ_WIDTH_B == 1 && widest_width == 36) ? 4 : (READ_WIDTH_B == 1 && widest_width == 72) ? 5 : + (READ_WIDTH_B == 2 && widest_width == 4) ? 1 : (READ_WIDTH_B == 2 && widest_width == 9) ? 2 : + (READ_WIDTH_B == 2 && widest_width == 18) ? 3 : (READ_WIDTH_B == 2 && widest_width == 36) ? 4 : + (READ_WIDTH_B == 2 && widest_width == 72) ? 5 : (READ_WIDTH_B == 4 && widest_width == 9) ? 2 : + (READ_WIDTH_B == 4 && widest_width == 18) ? 3 : (READ_WIDTH_B == 4 && widest_width == 36) ? 4 : + (READ_WIDTH_B == 4 && widest_width == 72) ? 5 : 10; + + localparam addra_bit_8 = (WRITE_WIDTH_A == 9 && widest_width == 18) ? 3 : (WRITE_WIDTH_A == 9 && widest_width == 36) ? 4 : + (WRITE_WIDTH_A == 9 && widest_width == 72) ? 5 : 10; + + localparam addra_bit_16 = (WRITE_WIDTH_A == 18 && widest_width == 36) ? 4 : (WRITE_WIDTH_A == 18 && widest_width == 72) ? 5 : 10; + + localparam r_addra_bit_8 = (READ_WIDTH_A == 9 && widest_width == 18) ? 3 : (READ_WIDTH_A == 9 && widest_width == 36) ? 4 : + (READ_WIDTH_A == 9 && widest_width == 72) ? 5 : 10; + + localparam r_addra_bit_16 = (READ_WIDTH_A == 18 && widest_width == 36) ? 4 : (READ_WIDTH_A == 18 && widest_width == 72) ? 5 : 10; + + localparam r_addra_bit_32 = (READ_WIDTH_A == 36 && widest_width == 72) ? 5 : 10; + + localparam addrb_bit_8 = (WRITE_WIDTH_B == 9 && widest_width == 18) ? 3 : (WRITE_WIDTH_B == 9 && widest_width == 36) ? 4 : + (WRITE_WIDTH_B == 9 && widest_width == 72) ? 5 : 10; + + localparam addrb_bit_16 = (WRITE_WIDTH_B == 18 && widest_width == 36) ? 4 : (WRITE_WIDTH_B == 18 && widest_width == 72) ? 5 : 10; + + localparam addrb_bit_32 = (WRITE_WIDTH_B == 36 && widest_width == 72) ? 5 : 10; + + localparam r_addrb_bit_8 = (READ_WIDTH_B == 9 && widest_width == 18) ? 3 : (READ_WIDTH_B == 9 && widest_width == 36) ? 4 : + (READ_WIDTH_B == 9 && widest_width == 72) ? 5 : 10; + + localparam r_addrb_bit_16 = (READ_WIDTH_B == 18 && widest_width == 36) ? 4 : (READ_WIDTH_B == 18 && widest_width == 72) ? 5 : 10; + + localparam r_addrb_bit_32 = (READ_WIDTH_B == 36 && widest_width == 72) ? 5 : 10; + + localparam mem_size1 = (BRAM_SIZE == 18) ? 16384 : (BRAM_SIZE == 36) ? 32768 : 32768; + localparam mem_size2 = (BRAM_SIZE == 18) ? 8192 : (BRAM_SIZE == 36) ? 16384 : 16384; + localparam mem_size4 = (BRAM_SIZE == 18) ? 4096 : (BRAM_SIZE == 36) ? 8192 : 8192; + localparam mem_size9 = (BRAM_SIZE == 18) ? 2048 : (BRAM_SIZE == 36) ? 4096 : 4096; + localparam mem_size18 = (BRAM_SIZE == 18) ? 1024 : (BRAM_SIZE == 36) ? 2048 : 2048; + localparam mem_size36 = (BRAM_SIZE == 18) ? 512 : (BRAM_SIZE == 36) ? 1024 : 1024; + localparam mem_size72 = (BRAM_SIZE == 18) ? 0 : (BRAM_SIZE == 36) ? 512 : 512; + + localparam mem_depth = (widest_width == 1) ? mem_size1 : (widest_width == 2) ? mem_size2 : (widest_width == 4) ? mem_size4 : + (widest_width == 9) ? mem_size9 :(widest_width == 18) ? mem_size18 : (widest_width == 36) ? mem_size36 : + (widest_width == 72) ? mem_size72 : 32768; + + localparam memp_depth = (widest_width == 9) ? mem_size9 :(widest_width == 18) ? mem_size18 : (widest_width == 36) ? mem_size36 : + (widest_width == 72) ? mem_size72 : 4096; + + reg [widest_width-1:0] tmp_mem [mem_depth-1:0]; + + reg [width-1:0] mem [mem_depth-1:0]; + reg [widthp-1:0] memp [memp_depth-1:0]; + + + +/******************************************** task and function **************************************/ + + task task_ram; + + input we; + input [7:0] di; + input dip; + inout [7:0] mem_task; + inout memp_task; + + begin + + if (we == 1'b1) begin + + mem_task = di; + + if (width >= 8) + memp_task = dip; + end + end + + endtask // task_ram + + + task task_ram_col; + + input we_o; + input we; + input [7:0] di; + input dip; + inout [7:0] mem_task; + inout memp_task; + integer i; + + begin + + if (we == 1'b1) begin + + for (i = 0; i < 8; i = i + 1) + if (mem_task[i] !== 1'bx || !(we === we_o && we === 1'b1)) + mem_task[i] = di[i]; + + if (width >= 8 && (memp_task !== 1'bx || !(we === we_o && we === 1'b1))) + memp_task = dip; + + end + end + + endtask // task_ram_col + + + task task_x_buf; + input [1:0] wr_rd_mode; + input integer do_uindex; + input integer do_lindex; + input integer dop_index; + input [63:0] do_ltmp; + inout [63:0] do_tmp; + input [7:0] dop_ltmp; + inout [7:0] dop_tmp; + integer i; + + begin + + if (wr_rd_mode == 2'b01) begin + for (i = do_lindex; i <= do_uindex; i = i + 1) begin + if (do_ltmp[i] === 1'bx) + do_tmp[i] = 1'bx; + end + + if (dop_ltmp[dop_index] === 1'bx) + dop_tmp[dop_index] = 1'bx; + + end // if (wr_rd_mode == 2'b01) + else begin + do_tmp[do_lindex +: 8] = do_ltmp[do_lindex +: 8]; + dop_tmp[dop_index] = dop_ltmp[dop_index]; + + end // else: !if(wr_rd_mode == 2'b01) + end + + endtask // task_x_buf + + + task task_col_wr_ram_a; + + input [1:0] seq; + input [7:0] web_tmp; + input [7:0] wea_tmp; + input [63:0] dia_tmp; + input [7:0] dipa_tmp; + input [15:0] addrb_tmp; + input [15:0] addra_tmp; + + begin + + case (wa_width) + + 1, 2, 4 : begin + if (!(wea_tmp[0] === 1'b1 && web_tmp[0] === 1'b1 && wa_width > wb_width) || seq == 2'b10) begin + if (wa_width >= width) + task_ram_col (web_tmp[0], wea_tmp[0], dia_tmp[wa_width-1:0], 1'b0, mem[addra_tmp[14:addra_lbit_124]], junk1); + else + task_ram_col (web_tmp[0], wea_tmp[0], dia_tmp[wa_width-1:0], 1'b0, mem[addra_tmp[14:addra_bit_124+1]][(addra_tmp[addra_bit_124:addra_lbit_124] * wa_width) +: wa_width], junk1); + + if (seq == 2'b00) + chk_for_col_msg (wea_tmp[0], web_tmp[0], addra_tmp, addrb_tmp); + + end // if (!(wea_tmp[0] === 1'b1 && web_tmp[0] === 1'b1 && wa_width > wb_width) || seq == 2'b10) + end // case: 1, 2, 4 + 8 : begin + if (!(wea_tmp[0] === 1'b1 && web_tmp[0] === 1'b1 && wa_width > wb_width) || seq == 2'b10) begin + if (wa_width >= width) + task_ram_col (web_tmp[0], wea_tmp[0], dia_tmp[7:0], dipa_tmp[0], mem[addra_tmp[14:3]], memp[addra_tmp[14:3]]); + else + task_ram_col (web_tmp[0], wea_tmp[0], dia_tmp[7:0], dipa_tmp[0], mem[addra_tmp[14:addra_bit_8+1]][(addra_tmp[addra_bit_8:3] * 8) +: 8], memp[addra_tmp[14:addra_bit_8+1]][(addra_tmp[addra_bit_8:3] * 1) +: 1]); + + if (seq == 2'b00) + chk_for_col_msg (wea_tmp[0], web_tmp[0], addra_tmp, addrb_tmp); + + end // if (wa_width <= wb_width) + end // case: 8 + 16 : begin + if (!(wea_tmp[0] === 1'b1 && web_tmp[0] === 1'b1 && wa_width > wb_width) || seq == 2'b10) begin + if (wa_width >= width) + task_ram_col (web_tmp[0], wea_tmp[0], dia_tmp[7:0], dipa_tmp[0], mem[addra_tmp[14:4]][0 +: 8], memp[addra_tmp[14:4]][0]); + else + task_ram_col (web_tmp[0], wea_tmp[0], dia_tmp[7:0], dipa_tmp[0], mem[addra_tmp[14:addra_bit_16+1]][(addra_tmp[addra_bit_16:4] * 16) +: 8], memp[addra_tmp[14:addra_bit_16+1]][(addra_tmp[addra_bit_16:4] * 2) +: 1]); + + if (seq == 2'b00) + chk_for_col_msg (wea_tmp[0], web_tmp[0], addra_tmp, addrb_tmp); + + if (wa_width >= width) + task_ram_col (web_tmp[1], wea_tmp[1], dia_tmp[15:8], dipa_tmp[1], mem[addra_tmp[14:4]][8 +: 8], memp[addra_tmp[14:4]][1]); + else + task_ram_col (web_tmp[1], wea_tmp[1], dia_tmp[15:8], dipa_tmp[1], mem[addra_tmp[14:addra_bit_16+1]][((addra_tmp[addra_bit_16:4] * 16) + 8) +: 8], memp[addra_tmp[14:addra_bit_16+1]][((addra_tmp[addra_bit_16:4] * 2) + 1) +: 1]); + + if (seq == 2'b00) + chk_for_col_msg (wea_tmp[1], web_tmp[1], addra_tmp, addrb_tmp); + + end // if (wa_width <= wb_width) + end // case: 16 + 32 : begin + if (!(wea_tmp[0] === 1'b1 && web_tmp[0] === 1'b1 && wa_width > wb_width) || seq == 2'b10) begin + task_ram_col (web_tmp[0], wea_tmp[0], dia_tmp[7:0], dipa_tmp[0], mem[addra_tmp[14:5]][0 +: 8], memp[addra_tmp[14:5]][0]); + if (seq == 2'b00) + chk_for_col_msg (wea_tmp[0], web_tmp[0], addra_tmp, addrb_tmp); + + task_ram_col (web_tmp[1], wea_tmp[1], dia_tmp[15:8], dipa_tmp[1], mem[addra_tmp[14:5]][8 +: 8], memp[addra_tmp[14:5]][1]); + if (seq == 2'b00) + chk_for_col_msg (wea_tmp[1], web_tmp[1], addra_tmp, addrb_tmp); + + task_ram_col (web_tmp[2], wea_tmp[2], dia_tmp[23:16], dipa_tmp[2], mem[addra_tmp[14:5]][16 +: 8], memp[addra_tmp[14:5]][2]); + if (seq == 2'b00) + chk_for_col_msg (wea_tmp[2], web_tmp[2], addra_tmp, addrb_tmp); + + task_ram_col (web_tmp[3], wea_tmp[3], dia_tmp[31:24], dipa_tmp[3], mem[addra_tmp[14:5]][24 +: 8], memp[addra_tmp[14:5]][3]); + if (seq == 2'b00) + chk_for_col_msg (wea_tmp[3], web_tmp[3], addra_tmp, addrb_tmp); + + end // if (wa_width <= wb_width) + end // case: 32 + 64 : ; + + endcase // case(wa_width) + + end + + endtask // task_col_wr_ram_a + + + task task_col_wr_ram_b; + + input [1:0] seq; + input [7:0] wea_tmp; + input [7:0] web_tmp; + input [63:0] dib_tmp; + input [7:0] dipb_tmp; + input [15:0] addra_tmp; + input [15:0] addrb_tmp; + + begin + + case (wb_width) + + 1, 2, 4 : begin + if (!(wea_tmp[0] === 1'b1 && web_tmp[0] === 1'b1 && wb_width > wa_width) || seq == 2'b10) begin + if (wb_width >= width) + task_ram_col (wea_tmp[0], web_tmp[0], dib_tmp[wb_width-1:0], 1'b0, mem[addrb_tmp[14:addrb_lbit_124]], junk1); + else + task_ram_col (wea_tmp[0], web_tmp[0], dib_tmp[wb_width-1:0], 1'b0, mem[addrb_tmp[14:addrb_bit_124+1]][(addrb_tmp[addrb_bit_124:addrb_lbit_124] * wb_width) +: wb_width], junk1); + + if (seq == 2'b00) + chk_for_col_msg (wea_tmp[0], web_tmp[0], addra_tmp, addrb_tmp); + + end // if (wb_width <= wa_width) + end // case: 1, 2, 4 + 8 : begin + if (!(wea_tmp[0] === 1'b1 && web_tmp[0] === 1'b1 && wb_width > wa_width) || seq == 2'b10) begin + if (wb_width >= width) + task_ram_col (wea_tmp[0], web_tmp[0], dib_tmp[7:0], dipb_tmp[0], mem[addrb_tmp[14:3]], memp[addrb_tmp[14:3]]); + else + task_ram_col (wea_tmp[0], web_tmp[0], dib_tmp[7:0], dipb_tmp[0], mem[addrb_tmp[14:addrb_bit_8+1]][(addrb_tmp[addrb_bit_8:3] * 8) +: 8], memp[addrb_tmp[14:addrb_bit_8+1]][(addrb_tmp[addrb_bit_8:3] * 1) +: 1]); + + if (seq == 2'b00) + chk_for_col_msg (wea_tmp[0], web_tmp[0], addra_tmp, addrb_tmp); + + end // if (wb_width <= wa_width) + end // case: 8 + 16 : begin + if (!(wea_tmp[0] === 1'b1 && web_tmp[0] === 1'b1 && wb_width > wa_width) || seq == 2'b10) begin + if (wb_width >= width) + task_ram_col (wea_tmp[0], web_tmp[0], dib_tmp[7:0], dipb_tmp[0], mem[addrb_tmp[14:4]][0 +: 8], memp[addrb_tmp[14:4]][0:0]); + else + task_ram_col (wea_tmp[0], web_tmp[0], dib_tmp[7:0], dipb_tmp[0], mem[addrb_tmp[14:addrb_bit_16+1]][(addrb_tmp[addrb_bit_16:4] * 16) +: 8], memp[addrb_tmp[14:addrb_bit_16+1]][(addrb_tmp[addrb_bit_16:4] * 2) +: 1]); + + if (seq == 2'b00) + chk_for_col_msg (wea_tmp[0], web_tmp[0], addra_tmp, addrb_tmp); + + + if (wb_width >= width) + task_ram_col (wea_tmp[1], web_tmp[1], dib_tmp[15:8], dipb_tmp[1], mem[addrb_tmp[14:4]][8 +: 8], memp[addrb_tmp[14:4]][1:1]); + else + task_ram_col (wea_tmp[1], web_tmp[1], dib_tmp[15:8], dipb_tmp[1], mem[addrb_tmp[14:addrb_bit_16+1]][((addrb_tmp[addrb_bit_16:4] * 16) + 8) +: 8], memp[addrb_tmp[14:addrb_bit_16+1]][((addrb_tmp[addrb_bit_16:4] * 2) + 1) +: 1]); + + if (seq == 2'b00) + chk_for_col_msg (wea_tmp[1], web_tmp[1], addra_tmp, addrb_tmp); + + end // if (!(wea_tmp[0] === 1'b1 && web_tmp[0] === 1'b1 && wb_width > wa_width) || seq == 2'b10) + end // case: 16 + 32 : begin + if (!(wea_tmp[0] === 1'b1 && web_tmp[0] === 1'b1 && wb_width > wa_width) || seq == 2'b10) begin + task_ram_col (wea_tmp[0], web_tmp[0], dib_tmp[7:0], dipb_tmp[0], mem[addrb_tmp[14:5]][0 +: 8], memp[addrb_tmp[14:5]][0:0]); + if (seq == 2'b00) + chk_for_col_msg (wea_tmp[0], web_tmp[0], addra_tmp, addrb_tmp); + + task_ram_col (wea_tmp[1], web_tmp[1], dib_tmp[15:8], dipb_tmp[1], mem[addrb_tmp[14:5]][8 +: 8], memp[addrb_tmp[14:5]][1:1]); + if (seq == 2'b00) + chk_for_col_msg (wea_tmp[1], web_tmp[1], addra_tmp, addrb_tmp); + + task_ram_col (wea_tmp[2], web_tmp[2], dib_tmp[23:16], dipb_tmp[2], mem[addrb_tmp[14:5]][16 +: 8], memp[addrb_tmp[14:5]][2:2]); + if (seq == 2'b00) + chk_for_col_msg (wea_tmp[2], web_tmp[2], addra_tmp, addrb_tmp); + + task_ram_col (wea_tmp[3], web_tmp[3], dib_tmp[31:24], dipb_tmp[3], mem[addrb_tmp[14:5]][24 +: 8], memp[addrb_tmp[14:5]][3:3]); + if (seq == 2'b00) + chk_for_col_msg (wea_tmp[3], web_tmp[3], addra_tmp, addrb_tmp); + + end // if (wb_width <= wa_width) + end // case: 32 + 64 : begin + + task_ram_col (wea_tmp[0], web_tmp[0], dib_tmp[7:0], dipb_tmp[0], mem[addrb_tmp[14:6]][0 +: 8], memp[addrb_tmp[14:6]][0:0]); + if (seq == 2'b00) + chk_for_col_msg (wea_tmp[0], web_tmp[0], addra_tmp, addrb_tmp); + + task_ram_col (wea_tmp[1], web_tmp[1], dib_tmp[15:8], dipb_tmp[1], mem[addrb_tmp[14:6]][8 +: 8], memp[addrb_tmp[14:6]][1:1]); + if (seq == 2'b00) + chk_for_col_msg (wea_tmp[1], web_tmp[1], addra_tmp, addrb_tmp); + + task_ram_col (wea_tmp[2], web_tmp[2], dib_tmp[23:16], dipb_tmp[2], mem[addrb_tmp[14:6]][16 +: 8], memp[addrb_tmp[14:6]][2:2]); + if (seq == 2'b00) + chk_for_col_msg (wea_tmp[2], web_tmp[2], addra_tmp, addrb_tmp); + + task_ram_col (wea_tmp[3], web_tmp[3], dib_tmp[31:24], dipb_tmp[3], mem[addrb_tmp[14:6]][24 +: 8], memp[addrb_tmp[14:6]][3:3]); + if (seq == 2'b00) + chk_for_col_msg (wea_tmp[3], web_tmp[3], addra_tmp, addrb_tmp); + + task_ram_col (wea_tmp[4], web_tmp[4], dib_tmp[39:32], dipb_tmp[4], mem[addrb_tmp[14:6]][32 +: 8], memp[addrb_tmp[14:6]][4:4]); + if (seq == 2'b00) + chk_for_col_msg (wea_tmp[4], web_tmp[4], addra_tmp, addrb_tmp); + + task_ram_col (wea_tmp[5], web_tmp[5], dib_tmp[47:40], dipb_tmp[5], mem[addrb_tmp[14:6]][40 +: 8], memp[addrb_tmp[14:6]][5:5]); + if (seq == 2'b00) + chk_for_col_msg (wea_tmp[5], web_tmp[5], addra_tmp, addrb_tmp); + + task_ram_col (wea_tmp[6], web_tmp[6], dib_tmp[55:48], dipb_tmp[6], mem[addrb_tmp[14:6]][48 +: 8], memp[addrb_tmp[14:6]][6:6]); + if (seq == 2'b00) + chk_for_col_msg (wea_tmp[6], web_tmp[6], addra_tmp, addrb_tmp); + + task_ram_col (wea_tmp[7], web_tmp[7], dib_tmp[63:56], dipb_tmp[7], mem[addrb_tmp[14:6]][56 +: 8], memp[addrb_tmp[14:6]][7:7]); + if (seq == 2'b00) + chk_for_col_msg (wea_tmp[7], web_tmp[7], addra_tmp, addrb_tmp); + + end // case: 64 + + endcase // case(wb_width) + + end + + endtask // task_col_wr_ram_b + + + task task_wr_ram_a; + + input [7:0] wea_tmp; + input [63:0] dia_tmp; + input [7:0] dipa_tmp; + input [15:0] addra_tmp; + + begin + + case (wa_width) + + 1, 2, 4 : begin + + if (wa_width >= width) + task_ram (wea_tmp[0], dia_tmp[wa_width-1:0], 1'b0, mem[addra_tmp[14:addra_lbit_124]], junk1); + else + task_ram (wea_tmp[0], dia_tmp[wa_width-1:0], 1'b0, mem[addra_tmp[14:addra_bit_124+1]][(addra_tmp[addra_bit_124:addra_lbit_124] * wa_width) +: wa_width], junk1); + + end + 8 : begin + + if (wa_width >= width) + task_ram (wea_tmp[0], dia_tmp[7:0], dipa_tmp[0], mem[addra_tmp[14:3]], memp[addra_tmp[14:3]]); + else + task_ram (wea_tmp[0], dia_tmp[7:0], dipa_tmp[0], mem[addra_tmp[14:addra_bit_8+1]][(addra_tmp[addra_bit_8:3] * 8) +: 8], memp[addra_tmp[14:addra_bit_8+1]][(addra_tmp[addra_bit_8:3] * 1) +: 1]); + + end + 16 : begin + + if (wa_width >= width) begin + task_ram (wea_tmp[0], dia_tmp[7:0], dipa_tmp[0], mem[addra_tmp[14:4]][0 +: 8], memp[addra_tmp[14:4]][0:0]); + task_ram (wea_tmp[1], dia_tmp[15:8], dipa_tmp[1], mem[addra_tmp[14:4]][8 +: 8], memp[addra_tmp[14:4]][1:1]); + end + else begin + task_ram (wea_tmp[0], dia_tmp[7:0], dipa_tmp[0], mem[addra_tmp[14:addra_bit_16+1]][(addra_tmp[addra_bit_16:4] * 16) +: 8], memp[addra_tmp[14:addra_bit_16+1]][(addra_tmp[addra_bit_16:4] * 2) +: 1]); + task_ram (wea_tmp[1], dia_tmp[15:8], dipa_tmp[1], mem[addra_tmp[14:addra_bit_16+1]][((addra_tmp[addra_bit_16:4] * 16) + 8) +: 8], memp[addra_tmp[14:addra_bit_16+1]][((addra_tmp[addra_bit_16:4] * 2) + 1) +: 1]); + end // else: !if(wa_width >= wb_width) + + end // case: 16 + 32 : begin + + task_ram (wea_tmp[0], dia_tmp[7:0], dipa_tmp[0], mem[addra_tmp[14:5]][0 +: 8], memp[addra_tmp[14:5]][0:0]); + task_ram (wea_tmp[1], dia_tmp[15:8], dipa_tmp[1], mem[addra_tmp[14:5]][8 +: 8], memp[addra_tmp[14:5]][1:1]); + task_ram (wea_tmp[2], dia_tmp[23:16], dipa_tmp[2], mem[addra_tmp[14:5]][16 +: 8], memp[addra_tmp[14:5]][2:2]); + task_ram (wea_tmp[3], dia_tmp[31:24], dipa_tmp[3], mem[addra_tmp[14:5]][24 +: 8], memp[addra_tmp[14:5]][3:3]); + + end // case: 32 + endcase // case(wa_width) + end + + endtask // task_wr_ram_a + + + task task_wr_ram_b; + + input [7:0] web_tmp; + input [63:0] dib_tmp; + input [7:0] dipb_tmp; + input [15:0] addrb_tmp; + + begin + + case (wb_width) + + 1, 2, 4 : begin + + if (wb_width >= width) + task_ram (web_tmp[0], dib_tmp[wb_width-1:0], 1'b0, mem[addrb_tmp[14:addrb_lbit_124]], junk1); + else + task_ram (web_tmp[0], dib_tmp[wb_width-1:0], 1'b0, mem[addrb_tmp[14:addrb_bit_124+1]][(addrb_tmp[addrb_bit_124:addrb_lbit_124] * wb_width) +: wb_width], junk1); + end + 8 : begin + + if (wb_width >= width) + task_ram (web_tmp[0], dib_tmp[7:0], dipb_tmp[0], mem[addrb_tmp[14:3]], memp[addrb_tmp[14:3]]); + else + task_ram (web_tmp[0], dib_tmp[7:0], dipb_tmp[0], mem[addrb_tmp[14:addrb_bit_8+1]][(addrb_tmp[addrb_bit_8:3] * 8) +: 8], memp[addrb_tmp[14:addrb_bit_8+1]][(addrb_tmp[addrb_bit_8:3] * 1) +: 1]); + + end + 16 : begin + + if (wb_width >= width) begin + task_ram (web_tmp[0], dib_tmp[7:0], dipb_tmp[0], mem[addrb_tmp[14:4]][0 +: 8], memp[addrb_tmp[14:4]][0:0]); + task_ram (web_tmp[1], dib_tmp[15:8], dipb_tmp[1], mem[addrb_tmp[14:4]][8 +: 8], memp[addrb_tmp[14:4]][1:1]); + end + else begin + task_ram (web_tmp[0], dib_tmp[7:0], dipb_tmp[0], mem[addrb_tmp[14:addrb_bit_16+1]][(addrb_tmp[addrb_bit_16:4] * 16) +: 8], memp[addrb_tmp[14:addrb_bit_16+1]][(addrb_tmp[addrb_bit_16:4] * 2) +: 1]); + task_ram (web_tmp[1], dib_tmp[15:8], dipb_tmp[1], mem[addrb_tmp[14:addrb_bit_16+1]][((addrb_tmp[addrb_bit_16:4] * 16) + 8) +: 8], memp[addrb_tmp[14:addrb_bit_16+1]][((addrb_tmp[addrb_bit_16:4] * 2) + 1) +: 1]); + end + + end // case: 16 + 32 : begin + + if (wb_width >= width) begin + task_ram (web_tmp[0], dib_tmp[7:0], dipb_tmp[0], mem[addrb_tmp[14:5]][0 +: 8], memp[addrb_tmp[14:5]][0:0]); + task_ram (web_tmp[1], dib_tmp[15:8], dipb_tmp[1], mem[addrb_tmp[14:5]][8 +: 8], memp[addrb_tmp[14:5]][1:1]); + task_ram (web_tmp[2], dib_tmp[23:16], dipb_tmp[2], mem[addrb_tmp[14:5]][16 +: 8], memp[addrb_tmp[14:5]][2:2]); + task_ram (web_tmp[3], dib_tmp[31:24], dipb_tmp[3], mem[addrb_tmp[14:5]][24 +: 8], memp[addrb_tmp[14:5]][3:3]); + end + else begin + task_ram (web_tmp[0], dib_tmp[7:0], dipb_tmp[0], mem[addrb_tmp[14:addrb_bit_32+1]][(addrb_tmp[addrb_bit_32:5] * 32) +: 8], memp[addrb_tmp[14:addrb_bit_32+1]][(addrb_tmp[addrb_bit_32:5] * 4) +: 1]); + task_ram (web_tmp[1], dib_tmp[15:8], dipb_tmp[1], mem[addrb_tmp[14:addrb_bit_32+1]][((addrb_tmp[addrb_bit_32:5] * 32) + 8) +: 8], memp[addrb_tmp[14:addrb_bit_32+1]][((addrb_tmp[addrb_bit_32:5] * 4) + 1) +: 1]); + task_ram (web_tmp[2], dib_tmp[23:16], dipb_tmp[2], mem[addrb_tmp[14:addrb_bit_32+1]][((addrb_tmp[addrb_bit_32:5] * 32) + 16) +: 8], memp[addrb_tmp[14:addrb_bit_32+1]][((addrb_tmp[addrb_bit_32:5] * 4) + 2) +: 1]); + task_ram (web_tmp[3], dib_tmp[31:24], dipb_tmp[3], mem[addrb_tmp[14:addrb_bit_32+1]][((addrb_tmp[addrb_bit_32:5] * 32) + 24) +: 8], memp[addrb_tmp[14:addrb_bit_32+1]][((addrb_tmp[addrb_bit_32:5] * 4) + 3) +: 1]); + end // else: !if(wb_width >= width) + + end // case: 32 + 64 : begin // only valid with ECC single bit correction for 64 bits + + task_ram (web_tmp[0], dib_tmp[7:0], dipb_tmp[0], mem[addrb_tmp[14:6]][0 +: 8], memp[addrb_tmp[14:6]][0:0]); + task_ram (web_tmp[1], dib_tmp[15:8], dipb_tmp[1], mem[addrb_tmp[14:6]][8 +: 8], memp[addrb_tmp[14:6]][1:1]); + task_ram (web_tmp[2], dib_tmp[23:16], dipb_tmp[2], mem[addrb_tmp[14:6]][16 +: 8], memp[addrb_tmp[14:6]][2:2]); + task_ram (web_tmp[3], dib_tmp[31:24], dipb_tmp[3], mem[addrb_tmp[14:6]][24 +: 8], memp[addrb_tmp[14:6]][3:3]); + task_ram (web_tmp[4], dib_tmp[39:32], dipb_tmp[4], mem[addrb_tmp[14:6]][32 +: 8], memp[addrb_tmp[14:6]][4:4]); + task_ram (web_tmp[5], dib_tmp[47:40], dipb_tmp[5], mem[addrb_tmp[14:6]][40 +: 8], memp[addrb_tmp[14:6]][5:5]); + task_ram (web_tmp[6], dib_tmp[55:48], dipb_tmp[6], mem[addrb_tmp[14:6]][48 +: 8], memp[addrb_tmp[14:6]][6:6]); + task_ram (web_tmp[7], dib_tmp[63:56], dipb_tmp[7], mem[addrb_tmp[14:6]][56 +: 8], memp[addrb_tmp[14:6]][7:7]); + + end // case: 64 + endcase // case(wb_width) + end + + endtask // task_wr_ram_b + + + task task_col_rd_ram_a; + + input [1:0] seq; // 1 is bypass + input [7:0] web_tmp; + input [7:0] wea_tmp; + input [15:0] addra_tmp; + inout [63:0] doa_tmp; + inout [7:0] dopa_tmp; + reg [63:0] doa_ltmp; + reg [7:0] dopa_ltmp; + + begin + + doa_ltmp= 64'b0; + dopa_ltmp= 8'b0; + + case (ra_width) + 1, 2, 4 : begin + + if ((web_tmp[0] === 1'b1 && wea_tmp[0] === 1'b1) || (seq == 2'b01 && web_tmp[0] === 1'b1 && wea_tmp[0] === 1'b0 && viol_type == 2'b10) || (seq == 2'b01 && wr_mode_a != 2'b01 && wr_mode_b != 2'b01) || (seq == 2'b01 && wr_mode_a == 2'b01 && wr_mode_b != 2'b01 && web_tmp[0] === 1'b1) || (seq == 2'b11 && wr_mode_a == 2'b00 && web_tmp[0] !== 1'b1)) begin + if (ra_width >= width) + doa_ltmp = mem[addra_tmp[14:r_addra_lbit_124]]; + else + doa_ltmp = mem[addra_tmp[14:r_addra_bit_124+1]][(addra_tmp[r_addra_bit_124:r_addra_lbit_124] * ra_width) +: ra_width]; + task_x_buf (wr_mode_a, 3, 0, 0, doa_ltmp, doa_tmp, dopa_ltmp, dopa_tmp); + end + end // case: 1, 2, 4 + 8 : begin + + if ((web_tmp[0] === 1'b1 && wea_tmp[0] === 1'b1) || (seq == 2'b01 && web_tmp[0] === 1'b1 && wea_tmp[0] === 1'b0 && viol_type == 2'b10) || (seq == 2'b01 && wr_mode_a != 2'b01 && wr_mode_b != 2'b01) || (seq == 2'b01 && wr_mode_a == 2'b01 && wr_mode_b != 2'b01 && web_tmp[0] === 1'b1) || (seq == 2'b11 && wr_mode_a == 2'b00 && web_tmp[0] !== 1'b1)) begin + if (ra_width >= width) begin + doa_ltmp = mem[addra_tmp[14:3]]; + dopa_ltmp = memp[addra_tmp[14:3]]; + end + else begin + doa_ltmp = mem[addra_tmp[14:r_addra_bit_8+1]][(addra_tmp[r_addra_bit_8:3] * 8) +: 8]; + dopa_ltmp = memp[addra_tmp[14:r_addra_bit_8+1]][(addra_tmp[r_addra_bit_8:3] * 1) +: 1]; + end + + task_x_buf (wr_mode_a, 7, 0, 0, doa_ltmp, doa_tmp, dopa_ltmp, dopa_tmp); + + end + end // case: 8 + 16 : begin + + if ((web_tmp[0] === 1'b1 && wea_tmp[0] === 1'b1) || (seq == 2'b01 && web_tmp[0] === 1'b1 && wea_tmp[0] === 1'b0 && viol_type == 2'b10) || (seq == 2'b01 && wr_mode_a != 2'b01 && wr_mode_b != 2'b01) || (seq == 2'b01 && wr_mode_a == 2'b01 && wr_mode_b != 2'b01 && web_tmp[0] === 1'b1) || (seq == 2'b11 && wr_mode_a == 2'b00 && web_tmp[0] !== 1'b1)) begin + if (ra_width >= width) begin + doa_ltmp[7:0] = mem[addra_tmp[14:4]][7:0]; + dopa_ltmp[0:0] = memp[addra_tmp[14:4]][0:0]; + end + else begin + doa_ltmp[7:0] = mem[addra_tmp[14:r_addra_bit_16+1]][(addra_tmp[r_addra_bit_16:4] * 16) +: 8]; + dopa_ltmp[0:0] = memp[addra_tmp[14:r_addra_bit_16+1]][(addra_tmp[r_addra_bit_16:4] * 2) +: 1]; + end + task_x_buf (wr_mode_a, 7, 0, 0, doa_ltmp, doa_tmp, dopa_ltmp, dopa_tmp); + end + + if ((web_tmp[1] === 1'b1 && wea_tmp[1] === 1'b1) || (seq == 2'b01 && web_tmp[1] === 1'b1 && wea_tmp[1] === 1'b0 && viol_type == 2'b10) || (seq == 2'b01 && wr_mode_a != 2'b01 && wr_mode_b != 2'b01) || (seq == 2'b01 && wr_mode_a == 2'b01 && wr_mode_b != 2'b01 && web_tmp[1] === 1'b1) || (seq == 2'b11 && wr_mode_a == 2'b00 && web_tmp[1] !== 1'b1)) begin + if (ra_width >= width) begin + doa_ltmp[15:8] = mem[addra_tmp[14:4]][15:8]; + dopa_ltmp[1:1] = memp[addra_tmp[14:4]][1:1]; + end + else begin + doa_ltmp[15:8] = mem[addra_tmp[14:r_addra_bit_16+1]][((addra_tmp[r_addra_bit_16:4] * 16) + 8) +: 8]; + dopa_ltmp[1:1] = memp[addra_tmp[14:r_addra_bit_16+1]][((addra_tmp[r_addra_bit_16:4] * 2) + 1) +: 1]; + end + task_x_buf (wr_mode_a, 15, 8, 1, doa_ltmp, doa_tmp, dopa_ltmp, dopa_tmp); + end + + end + 32 : begin + if (ra_width >= width) begin + + if ((web_tmp[0] === 1'b1 && wea_tmp[0] === 1'b1) || (seq == 2'b01 && web_tmp[0] === 1'b1 && wea_tmp[0] === 1'b0 && viol_type == 2'b10) || (seq == 2'b01 && wr_mode_a != 2'b01 && wr_mode_b != 2'b01) || (seq == 2'b01 && wr_mode_a == 2'b01 && wr_mode_b != 2'b01 && web_tmp[0] === 1'b1) || (seq == 2'b11 && wr_mode_a == 2'b00 && web_tmp[0] !== 1'b1)) begin + doa_ltmp[7:0] = mem[addra_tmp[14:5]][7:0]; + dopa_ltmp[0:0] = memp[addra_tmp[14:5]][0:0]; + task_x_buf (wr_mode_a, 7, 0, 0, doa_ltmp, doa_tmp, dopa_ltmp, dopa_tmp); + end + + if ((web_tmp[1] === 1'b1 && wea_tmp[1] === 1'b1) || (seq == 2'b01 && web_tmp[1] === 1'b1 && wea_tmp[1] === 1'b0 && viol_type == 2'b10) || (seq == 2'b01 && wr_mode_a != 2'b01 && wr_mode_b != 2'b01) || (seq == 2'b01 && wr_mode_a == 2'b01 && wr_mode_b != 2'b01 && web_tmp[1] === 1'b1) || (seq == 2'b11 && wr_mode_a == 2'b00 && web_tmp[1] !== 1'b1)) begin + doa_ltmp[15:8] = mem[addra_tmp[14:5]][15:8]; + dopa_ltmp[1:1] = memp[addra_tmp[14:5]][1:1]; + task_x_buf (wr_mode_a, 15, 8, 1, doa_ltmp, doa_tmp, dopa_ltmp, dopa_tmp); + end + + if ((web_tmp[2] === 1'b1 && wea_tmp[2] === 1'b1) || (seq == 2'b01 && web_tmp[2] === 1'b1 && wea_tmp[2] === 1'b0 && viol_type == 2'b10) || (seq == 2'b01 && wr_mode_a != 2'b01 && wr_mode_b != 2'b01) || (seq == 2'b01 && wr_mode_a == 2'b01 && wr_mode_b != 2'b01 && web_tmp[2] === 1'b1) || (seq == 2'b11 && wr_mode_a == 2'b00 && web_tmp[2] !== 1'b1)) begin + doa_ltmp[23:16] = mem[addra_tmp[14:5]][23:16]; + dopa_ltmp[2:2] = memp[addra_tmp[14:5]][2:2]; + task_x_buf (wr_mode_a, 23, 16, 2, doa_ltmp, doa_tmp, dopa_ltmp, dopa_tmp); + end + + if ((web_tmp[3] === 1'b1 && wea_tmp[3] === 1'b1) || (seq == 2'b01 && web_tmp[3] === 1'b1 && wea_tmp[3] === 1'b0 && viol_type == 2'b10) || (seq == 2'b01 && wr_mode_a != 2'b01 && wr_mode_b != 2'b01) || (seq == 2'b01 && wr_mode_a == 2'b01 && wr_mode_b != 2'b01 && web_tmp[3] === 1'b1) || (seq == 2'b11 && wr_mode_a == 2'b00 && web_tmp[3] !== 1'b1)) begin + doa_ltmp[31:24] = mem[addra_tmp[14:5]][31:24]; + dopa_ltmp[3:3] = memp[addra_tmp[14:5]][3:3]; + task_x_buf (wr_mode_a, 31, 24, 3, doa_ltmp, doa_tmp, dopa_ltmp, dopa_tmp); + end + + end // if (ra_width >= width) + end + 64 : begin + + if ((web_tmp[0] === 1'b1 && wea_tmp[0] === 1'b1) || (seq == 2'b01 && web_tmp[0] === 1'b1 && wea_tmp[0] === 1'b0 && viol_type == 2'b10) || (seq == 2'b01 && wr_mode_a != 2'b01 && wr_mode_b != 2'b01) || (seq == 2'b01 && wr_mode_a == 2'b01 && wr_mode_b != 2'b01 && web_tmp[0] === 1'b1) || (seq == 2'b11 && wr_mode_a == 2'b00 && web_tmp[0] !== 1'b1)) begin + doa_ltmp[7:0] = mem[addra_tmp[14:6]][7:0]; + dopa_ltmp[0:0] = memp[addra_tmp[14:6]][0:0]; + task_x_buf (wr_mode_a, 7, 0, 0, doa_ltmp, doa_tmp, dopa_ltmp, dopa_tmp); + end + + if ((web_tmp[1] === 1'b1 && wea_tmp[1] === 1'b1) || (seq == 2'b01 && web_tmp[1] === 1'b1 && wea_tmp[1] === 1'b0 && viol_type == 2'b10) || (seq == 2'b01 && wr_mode_a != 2'b01 && wr_mode_b != 2'b01) || (seq == 2'b01 && wr_mode_a == 2'b01 && wr_mode_b != 2'b01 && web_tmp[1] === 1'b1) || (seq == 2'b11 && wr_mode_a == 2'b00 && web_tmp[1] !== 1'b1)) begin + doa_ltmp[15:8] = mem[addra_tmp[14:6]][15:8]; + dopa_ltmp[1:1] = memp[addra_tmp[14:6]][1:1]; + task_x_buf (wr_mode_a, 15, 8, 1, doa_ltmp, doa_tmp, dopa_ltmp, dopa_tmp); + end + + if ((web_tmp[2] === 1'b1 && wea_tmp[2] === 1'b1) || (seq == 2'b01 && web_tmp[2] === 1'b1 && wea_tmp[2] === 1'b0 && viol_type == 2'b10) || (seq == 2'b01 && wr_mode_a != 2'b01 && wr_mode_b != 2'b01) || (seq == 2'b01 && wr_mode_a == 2'b01 && wr_mode_b != 2'b01 && web_tmp[2] === 1'b1) || (seq == 2'b11 && wr_mode_a == 2'b00 && web_tmp[2] !== 1'b1)) begin + doa_ltmp[23:16] = mem[addra_tmp[14:6]][23:16]; + dopa_ltmp[2:2] = memp[addra_tmp[14:6]][2:2]; + task_x_buf (wr_mode_a, 23, 16, 2, doa_ltmp, doa_tmp, dopa_ltmp, dopa_tmp); + end + + if ((web_tmp[3] === 1'b1 && wea_tmp[3] === 1'b1) || (seq == 2'b01 && web_tmp[3] === 1'b1 && wea_tmp[3] === 1'b0 && viol_type == 2'b10) || (seq == 2'b01 && wr_mode_a != 2'b01 && wr_mode_b != 2'b01) || (seq == 2'b01 && wr_mode_a == 2'b01 && wr_mode_b != 2'b01 && web_tmp[3] === 1'b1) || (seq == 2'b11 && wr_mode_a == 2'b00 && web_tmp[3] !== 1'b1)) begin + doa_ltmp[31:24] = mem[addra_tmp[14:6]][31:24]; + dopa_ltmp[3:3] = memp[addra_tmp[14:6]][3:3]; + task_x_buf (wr_mode_a, 31, 24, 3, doa_ltmp, doa_tmp, dopa_ltmp, dopa_tmp); + end + + if ((web_tmp[4] === 1'b1 && wea_tmp[4] === 1'b1) || (seq == 2'b01 && web_tmp[4] === 1'b1 && wea_tmp[4] === 1'b0 && viol_type == 2'b10) || (seq == 2'b01 && wr_mode_a != 2'b01 && wr_mode_b != 2'b01) || (seq == 2'b01 && wr_mode_a == 2'b01 && wr_mode_b != 2'b01 && web_tmp[4] === 1'b1) || (seq == 2'b11 && wr_mode_a == 2'b00 && web_tmp[4] !== 1'b1)) begin + doa_ltmp[39:32] = mem[addra_tmp[14:6]][39:32]; + dopa_ltmp[4:4] = memp[addra_tmp[14:6]][4:4]; + task_x_buf (wr_mode_a, 39, 32, 4, doa_ltmp, doa_tmp, dopa_ltmp, dopa_tmp); + end + + if ((web_tmp[5] === 1'b1 && wea_tmp[5] === 1'b1) || (seq == 2'b01 && web_tmp[5] === 1'b1 && wea_tmp[5] === 1'b0 && viol_type == 2'b10) || (seq == 2'b01 && wr_mode_a != 2'b01 && wr_mode_b != 2'b01) || (seq == 2'b01 && wr_mode_a == 2'b01 && wr_mode_b != 2'b01 && web_tmp[5] === 1'b1) || (seq == 2'b11 && wr_mode_a == 2'b00 && web_tmp[5] !== 1'b1)) begin + doa_ltmp[47:40] = mem[addra_tmp[14:6]][47:40]; + dopa_ltmp[5:5] = memp[addra_tmp[14:6]][5:5]; + task_x_buf (wr_mode_a, 47, 40, 5, doa_ltmp, doa_tmp, dopa_ltmp, dopa_tmp); + end + + if ((web_tmp[6] === 1'b1 && wea_tmp[6] === 1'b1) || (seq == 2'b01 && web_tmp[6] === 1'b1 && wea_tmp[6] === 1'b0 && viol_type == 2'b10) || (seq == 2'b01 && wr_mode_a != 2'b01 && wr_mode_b != 2'b01) || (seq == 2'b01 && wr_mode_a == 2'b01 && wr_mode_b != 2'b01 && web_tmp[6] === 1'b1) || (seq == 2'b11 && wr_mode_a == 2'b00 && web_tmp[6] !== 1'b1)) begin + doa_ltmp[55:48] = mem[addra_tmp[14:6]][55:48]; + dopa_ltmp[6:6] = memp[addra_tmp[14:6]][6:6]; + task_x_buf (wr_mode_a, 55, 48, 6, doa_ltmp, doa_tmp, dopa_ltmp, dopa_tmp); + end + + if ((web_tmp[7] === 1'b1 && wea_tmp[7] === 1'b1) || (seq == 2'b01 && web_tmp[7] === 1'b1 && wea_tmp[7] === 1'b0 && viol_type == 2'b10) || (seq == 2'b01 && wr_mode_a != 2'b01 && wr_mode_b != 2'b01) || (seq == 2'b01 && wr_mode_a == 2'b01 && wr_mode_b != 2'b01 && web_tmp[7] === 1'b1) || (seq == 2'b11 && wr_mode_a == 2'b00 && web_tmp[7] !== 1'b1)) begin + doa_ltmp[63:56] = mem[addra_tmp[14:6]][63:56]; + dopa_ltmp[7:7] = memp[addra_tmp[14:6]][7:7]; + task_x_buf (wr_mode_a, 63, 56, 7, doa_ltmp, doa_tmp, dopa_ltmp, dopa_tmp); + end + + end + endcase // case(ra_width) + end + endtask // task_col_rd_ram_a + + + task task_col_rd_ram_b; + + input [1:0] seq; // 1 is bypass + input [7:0] wea_tmp; + input [7:0] web_tmp; + input [15:0] addrb_tmp; + inout [63:0] dob_tmp; + inout [7:0] dopb_tmp; + reg [63:0] dob_ltmp; + reg [7:0] dopb_ltmp; + + begin + + dob_ltmp= 64'b0; + dopb_ltmp= 8'b0; + + case (rb_width) + 1, 2, 4 : begin + + if ((web_tmp[0] === 1'b1 && wea_tmp[0] === 1'b1) || (seq == 2'b01 && wea_tmp[0] === 1'b1 && web_tmp[0] === 1'b0 && viol_type == 2'b11) || (seq == 2'b01 && wr_mode_b != 2'b01 && wr_mode_a != 2'b01) || (seq == 2'b01 && wr_mode_b == 2'b01 && wr_mode_a != 2'b01 && wea_tmp[0] === 1'b1) || (seq == 2'b11 && wr_mode_b == 2'b00 && wea_tmp[0] !== 1'b1)) begin + if (rb_width >= width) + dob_ltmp = mem[addrb_tmp[14:r_addrb_lbit_124]]; + else + dob_ltmp = mem[addrb_tmp[14:r_addrb_bit_124+1]][(addrb_tmp[r_addrb_bit_124:r_addrb_lbit_124] * rb_width) +: rb_width]; + + task_x_buf (wr_mode_b, 3, 0, 0, dob_ltmp, dob_tmp, dopb_ltmp, dopb_tmp); + + end + end // case: 1, 2, 4 + 8 : begin + + if ((web_tmp[0] === 1'b1 && wea_tmp[0] === 1'b1) || (seq == 2'b01 && wea_tmp[0] === 1'b1 && web_tmp[0] === 1'b0 && viol_type == 2'b11) || (seq == 2'b01 && wr_mode_b != 2'b01 && wr_mode_a != 2'b01) || (seq == 2'b01 && wr_mode_b == 2'b01 && wr_mode_a != 2'b01 && wea_tmp[0] === 1'b1) || (seq == 2'b11 && wr_mode_b == 2'b00 && wea_tmp[0] !== 1'b1)) begin + + if (rb_width >= width) begin + dob_ltmp = mem[addrb_tmp[14:3]]; + dopb_ltmp = memp[addrb_tmp[14:3]]; + end + else begin + dob_ltmp = mem[addrb_tmp[14:r_addrb_bit_8+1]][(addrb_tmp[r_addrb_bit_8:3] * 8) +: 8]; + dopb_ltmp = memp[addrb_tmp[14:r_addrb_bit_8+1]][(addrb_tmp[r_addrb_bit_8:3] * 1) +: 1]; + end + + task_x_buf (wr_mode_b, 7, 0, 0, dob_ltmp, dob_tmp, dopb_ltmp, dopb_tmp); + + end + end // case: 8 + 16 : begin + + if ((web_tmp[0] === 1'b1 && wea_tmp[0] === 1'b1) || (seq == 2'b01 && wea_tmp[0] === 1'b1 && web_tmp[0] === 1'b0 && viol_type == 2'b11) || (seq == 2'b01 && wr_mode_b != 2'b01 && wr_mode_a != 2'b01) || (seq == 2'b01 && wr_mode_b == 2'b01 && wr_mode_a != 2'b01 && wea_tmp[0] === 1'b1) || (seq == 2'b11 && wr_mode_b == 2'b00 && wea_tmp[0] !== 1'b1)) begin + if (rb_width >= width) begin + dob_ltmp[7:0] = mem[addrb_tmp[14:4]][7:0]; + dopb_ltmp[0:0] = memp[addrb_tmp[14:4]][0:0]; + end + else begin + dob_ltmp[7:0] = mem[addrb_tmp[14:r_addrb_bit_16+1]][(addrb_tmp[r_addrb_bit_16:4] * 16) +: 8]; + dopb_ltmp[0:0] = memp[addrb_tmp[14:r_addrb_bit_16+1]][(addrb_tmp[r_addrb_bit_16:4] * 2) +: 1]; + end + task_x_buf (wr_mode_b, 7, 0, 0, dob_ltmp, dob_tmp, dopb_ltmp, dopb_tmp); + end + + + if ((web_tmp[1] === 1'b1 && wea_tmp[1] === 1'b1) || (seq == 2'b01 && wea_tmp[1] === 1'b1 && web_tmp[1] === 1'b0 && viol_type == 2'b11) || (seq == 2'b01 && wr_mode_b != 2'b01 && wr_mode_a != 2'b01) || (seq == 2'b01 && wr_mode_b == 2'b01 && wr_mode_a != 2'b01 && wea_tmp[1] === 1'b1) || (seq == 2'b11 && wr_mode_b == 2'b00 && wea_tmp[1] !== 1'b1)) begin + + if (rb_width >= width) begin + dob_ltmp[15:8] = mem[addrb_tmp[14:4]][15:8]; + dopb_ltmp[1:1] = memp[addrb_tmp[14:4]][1:1]; + end + else begin + dob_ltmp[15:8] = mem[addrb_tmp[14:r_addrb_bit_16+1]][((addrb_tmp[r_addrb_bit_16:4] * 16) + 8) +: 8]; + dopb_ltmp[1:1] = memp[addrb_tmp[14:r_addrb_bit_16+1]][((addrb_tmp[r_addrb_bit_16:4] * 2) + 1) +: 1]; + end + task_x_buf (wr_mode_b, 15, 8, 1, dob_ltmp, dob_tmp, dopb_ltmp, dopb_tmp); + end + + end + 32 : begin + + if ((web_tmp[0] === 1'b1 && wea_tmp[0] === 1'b1) || (seq == 2'b01 && wea_tmp[0] === 1'b1 && web_tmp[0] === 1'b0 && viol_type == 2'b11) || (seq == 2'b01 && wr_mode_b != 2'b01 && wr_mode_a != 2'b01) || (seq == 2'b01 && wr_mode_b == 2'b01 && wr_mode_a != 2'b01 && wea_tmp[0] === 1'b1) || (seq == 2'b11 && wr_mode_b == 2'b00 && wea_tmp[0] !== 1'b1)) begin + if (rb_width >= width) begin + dob_ltmp[7:0] = mem[addrb_tmp[14:5]][7:0]; + dopb_ltmp[0:0] = memp[addrb_tmp[14:5]][0:0]; + end + else begin + dob_ltmp[7:0] = mem[addrb_tmp[14:r_addrb_bit_32+1]][(addrb_tmp[r_addrb_bit_32:5] * 32) +: 8]; + dopb_ltmp[0:0] = memp[addrb_tmp[14:r_addrb_bit_32+1]][(addrb_tmp[r_addrb_bit_32:5] * 4) +: 1]; + end + task_x_buf (wr_mode_b, 7, 0, 0, dob_ltmp, dob_tmp, dopb_ltmp, dopb_tmp); + end + + + if ((web_tmp[1] === 1'b1 && wea_tmp[1] === 1'b1) || (seq == 2'b01 && wea_tmp[1] === 1'b1 && web_tmp[1] === 1'b0 && viol_type == 2'b11) || (seq == 2'b01 && wr_mode_b != 2'b01 && wr_mode_a != 2'b01) || (seq == 2'b01 && wr_mode_b == 2'b01 && wr_mode_a != 2'b01 && wea_tmp[1] === 1'b1) || (seq == 2'b11 && wr_mode_b == 2'b00 && wea_tmp[1] !== 1'b1)) begin + if (rb_width >= width) begin + dob_ltmp[15:8] = mem[addrb_tmp[14:5]][15:8]; + dopb_ltmp[1:1] = memp[addrb_tmp[14:5]][1:1]; + end + else begin + dob_ltmp[15:8] = mem[addrb_tmp[14:r_addrb_bit_32+1]][((addrb_tmp[r_addrb_bit_32:5] * 32) + 8) +: 8]; + dopb_ltmp[1:1] = memp[addrb_tmp[14:r_addrb_bit_32+1]][((addrb_tmp[r_addrb_bit_32:5] * 4) + 1) +: 1]; + end + task_x_buf (wr_mode_b, 15, 8, 1, dob_ltmp, dob_tmp, dopb_ltmp, dopb_tmp); + end + + + if ((web_tmp[2] === 1'b1 && wea_tmp[2] === 1'b1) || (seq == 2'b01 && wea_tmp[2] === 1'b1 && web_tmp[2] === 1'b0 && viol_type == 2'b11) || (seq == 2'b01 && wr_mode_b != 2'b01 && wr_mode_a != 2'b01) || (seq == 2'b01 && wr_mode_b == 2'b01 && wr_mode_a != 2'b01 && wea_tmp[2] === 1'b1) || (seq == 2'b11 && wr_mode_b == 2'b00 && wea_tmp[2] !== 1'b1)) begin + if (rb_width >= width) begin + dob_ltmp[23:16] = mem[addrb_tmp[14:5]][23:16]; + dopb_ltmp[2:2] = memp[addrb_tmp[14:5]][2:2]; + end + else begin + dob_ltmp[23:16] = mem[addrb_tmp[14:r_addrb_bit_32+1]][((addrb_tmp[r_addrb_bit_32:5] * 32) + 16) +: 8]; + dopb_ltmp[2:2] = memp[addrb_tmp[14:r_addrb_bit_32+1]][((addrb_tmp[r_addrb_bit_32:5] * 4) + 2) +: 1]; + end + task_x_buf (wr_mode_b, 23, 16, 2, dob_ltmp, dob_tmp, dopb_ltmp, dopb_tmp); + end + + + if ((web_tmp[3] === 1'b1 && wea_tmp[3] === 1'b1) || (seq == 2'b01 && wea_tmp[3] === 1'b1 && web_tmp[3] === 1'b0 && viol_type == 2'b11) || (seq == 2'b01 && wr_mode_b != 2'b01 && wr_mode_a != 2'b01) || (seq == 2'b01 && wr_mode_b == 2'b01 && wr_mode_a != 2'b01 && wea_tmp[3] === 1'b1) || (seq == 2'b11 && wr_mode_b == 2'b00 && wea_tmp[3] !== 1'b1)) begin + if (rb_width >= width) begin + dob_ltmp[31:24] = mem[addrb_tmp[14:5]][31:24]; + dopb_ltmp[3:3] = memp[addrb_tmp[14:5]][3:3]; + end + else begin + dob_ltmp[31:24] = mem[addrb_tmp[14:r_addrb_bit_32+1]][((addrb_tmp[r_addrb_bit_32:5] * 32) + 24) +: 8]; + dopb_ltmp[3:3] = memp[addrb_tmp[14:r_addrb_bit_32+1]][((addrb_tmp[r_addrb_bit_32:5] * 4) + 3) +: 1]; + end + task_x_buf (wr_mode_b, 31, 24, 3, dob_ltmp, dob_tmp, dopb_ltmp, dopb_tmp); + end + end + 64 : begin + + if ((web_tmp[0] === 1'b1 && wea_tmp[0] === 1'b1) || (seq == 2'b01 && wea_tmp[0] === 1'b1 && web_tmp[0] === 1'b0 && viol_type == 2'b11) || (seq == 2'b01 && wr_mode_b != 2'b01 && wr_mode_a != 2'b01) || (seq == 2'b01 && wr_mode_b == 2'b01 && wr_mode_a != 2'b01 && wea_tmp[0] === 1'b1) || (seq == 2'b11 && wr_mode_b == 2'b00 && wea_tmp[0] !== 1'b1)) begin + dob_ltmp[7:0] = mem[addrb_tmp[14:6]][7:0]; + dopb_ltmp[0:0] = memp[addrb_tmp[14:6]][0:0]; + task_x_buf (wr_mode_b, 7, 0, 0, dob_ltmp, dob_tmp, dopb_ltmp, dopb_tmp); + end + + if ((web_tmp[1] === 1'b1 && wea_tmp[1] === 1'b1) || (seq == 2'b01 && wea_tmp[1] === 1'b1 && web_tmp[1] === 1'b0 && viol_type == 2'b11) || (seq == 2'b01 && wr_mode_b != 2'b01 && wr_mode_a != 2'b01) || (seq == 2'b01 && wr_mode_b == 2'b01 && wr_mode_a != 2'b01 && wea_tmp[1] === 1'b1) || (seq == 2'b11 && wr_mode_b == 2'b00 && wea_tmp[1] !== 1'b1)) begin + dob_ltmp[15:8] = mem[addrb_tmp[14:6]][15:8]; + dopb_ltmp[1:1] = memp[addrb_tmp[14:6]][1:1]; + task_x_buf (wr_mode_b, 15, 8, 1, dob_ltmp, dob_tmp, dopb_ltmp, dopb_tmp); + end + + if ((web_tmp[2] === 1'b1 && wea_tmp[2] === 1'b1) || (seq == 2'b01 && wea_tmp[2] === 1'b1 && web_tmp[2] === 1'b0 && viol_type == 2'b11) || (seq == 2'b01 && wr_mode_b != 2'b01 && wr_mode_a != 2'b01) || (seq == 2'b01 && wr_mode_b == 2'b01 && wr_mode_a != 2'b01 && wea_tmp[2] === 1'b1) || (seq == 2'b11 && wr_mode_b == 2'b00 && wea_tmp[2] !== 1'b1)) begin + dob_ltmp[23:16] = mem[addrb_tmp[14:6]][23:16]; + dopb_ltmp[2:2] = memp[addrb_tmp[14:6]][2:2]; + task_x_buf (wr_mode_b, 23, 16, 2, dob_ltmp, dob_tmp, dopb_ltmp, dopb_tmp); + end + + if ((web_tmp[3] === 1'b1 && wea_tmp[3] === 1'b1) || (seq == 2'b01 && wea_tmp[3] === 1'b1 && web_tmp[3] === 1'b0 && viol_type == 2'b11) || (seq == 2'b01 && wr_mode_b != 2'b01 && wr_mode_a != 2'b01) || (seq == 2'b01 && wr_mode_b == 2'b01 && wr_mode_a != 2'b01 && wea_tmp[3] === 1'b1) || (seq == 2'b11 && wr_mode_b == 2'b00 && wea_tmp[3] !== 1'b1)) begin + dob_ltmp[31:24] = mem[addrb_tmp[14:6]][31:24]; + dopb_ltmp[3:3] = memp[addrb_tmp[14:6]][3:3]; + task_x_buf (wr_mode_b, 31, 24, 3, dob_ltmp, dob_tmp, dopb_ltmp, dopb_tmp); + end + + if ((web_tmp[4] === 1'b1 && wea_tmp[4] === 1'b1) || (seq == 2'b01 && wea_tmp[4] === 1'b1 && web_tmp[4] === 1'b0 && viol_type == 2'b11) || (seq == 2'b01 && wr_mode_b != 2'b01 && wr_mode_a != 2'b01) || (seq == 2'b01 && wr_mode_b == 2'b01 && wr_mode_a != 2'b01 && wea_tmp[4] === 1'b1) || (seq == 2'b11 && wr_mode_b == 2'b00 && wea_tmp[4] !== 1'b1)) begin + dob_ltmp[39:32] = mem[addrb_tmp[14:6]][39:32]; + dopb_ltmp[4:4] = memp[addrb_tmp[14:6]][4:4]; + task_x_buf (wr_mode_b, 39, 32, 4, dob_ltmp, dob_tmp, dopb_ltmp, dopb_tmp); + end + + if ((web_tmp[5] === 1'b1 && wea_tmp[5] === 1'b1) || (seq == 2'b01 && wea_tmp[5] === 1'b1 && web_tmp[5] === 1'b0 && viol_type == 2'b11) || (seq == 2'b01 && wr_mode_b != 2'b01 && wr_mode_a != 2'b01) || (seq == 2'b01 && wr_mode_b == 2'b01 && wr_mode_a != 2'b01 && wea_tmp[5] === 1'b1) || (seq == 2'b11 && wr_mode_b == 2'b00 && wea_tmp[5] !== 1'b1)) begin + dob_ltmp[47:40] = mem[addrb_tmp[14:6]][47:40]; + dopb_ltmp[5:5] = memp[addrb_tmp[14:6]][5:5]; + task_x_buf (wr_mode_b, 47, 40, 5, dob_ltmp, dob_tmp, dopb_ltmp, dopb_tmp); + end + + if ((web_tmp[6] === 1'b1 && wea_tmp[6] === 1'b1) || (seq == 2'b01 && wea_tmp[6] === 1'b1 && web_tmp[6] === 1'b0 && viol_type == 2'b11) || (seq == 2'b01 && wr_mode_b != 2'b01 && wr_mode_a != 2'b01) || (seq == 2'b01 && wr_mode_b == 2'b01 && wr_mode_a != 2'b01 && wea_tmp[6] === 1'b1) || (seq == 2'b11 && wr_mode_b == 2'b00 && wea_tmp[6] !== 1'b1)) begin + dob_ltmp[55:48] = mem[addrb_tmp[14:6]][55:48]; + dopb_ltmp[6:6] = memp[addrb_tmp[14:6]][6:6]; + task_x_buf (wr_mode_b, 55, 48, 6, dob_ltmp, dob_tmp, dopb_ltmp, dopb_tmp); + end + + if ((web_tmp[7] === 1'b1 && wea_tmp[7] === 1'b1) || (seq == 2'b01 && wea_tmp[7] === 1'b1 && web_tmp[7] === 1'b0 && viol_type == 2'b11) || (seq == 2'b01 && wr_mode_b != 2'b01 && wr_mode_a != 2'b01) || (seq == 2'b01 && wr_mode_b == 2'b01 && wr_mode_a != 2'b01 && wea_tmp[7] === 1'b1) || (seq == 2'b11 && wr_mode_b == 2'b00 && wea_tmp[7] !== 1'b1)) begin + dob_ltmp[63:56] = mem[addrb_tmp[14:6]][63:56]; + dopb_ltmp[7:7] = memp[addrb_tmp[14:6]][7:7]; + task_x_buf (wr_mode_b, 63, 56, 7, dob_ltmp, dob_tmp, dopb_ltmp, dopb_tmp); + end + + end + endcase // case(rb_width) + end + endtask // task_col_rd_ram_b + + + task task_rd_ram_a; + + input [15:0] addra_tmp; + inout [63:0] doa_tmp; + inout [7:0] dopa_tmp; + + begin + + case (ra_width) + 1, 2, 4 : begin + if (ra_width >= width) + doa_tmp = mem[addra_tmp[14:r_addra_lbit_124]]; + + else + doa_tmp = mem[addra_tmp[14:r_addra_bit_124+1]][(addra_tmp[r_addra_bit_124:r_addra_lbit_124] * ra_width) +: ra_width]; + end + 8 : begin + if (ra_width >= width) begin + doa_tmp = mem[addra_tmp[14:3]]; + dopa_tmp = memp[addra_tmp[14:3]]; + end + else begin + doa_tmp = mem[addra_tmp[14:r_addra_bit_8+1]][(addra_tmp[r_addra_bit_8:3] * 8) +: 8]; + dopa_tmp = memp[addra_tmp[14:r_addra_bit_8+1]][(addra_tmp[r_addra_bit_8:3] * 1) +: 1]; + end + end + 16 : begin + if (ra_width >= width) begin + doa_tmp = mem[addra_tmp[14:4]]; + dopa_tmp = memp[addra_tmp[14:4]]; + end + else begin + doa_tmp = mem[addra_tmp[14:r_addra_bit_16+1]][(addra_tmp[r_addra_bit_16:4] * 16) +: 16]; + dopa_tmp = memp[addra_tmp[14:r_addra_bit_16+1]][(addra_tmp[r_addra_bit_16:4] * 2) +: 2]; + end + end + 32 : begin + if (ra_width >= width) begin + doa_tmp = mem[addra_tmp[14:5]]; + dopa_tmp = memp[addra_tmp[14:5]]; + end + else begin + doa_tmp = mem[addra_tmp[14:r_addra_bit_32+1]][(addra_tmp[r_addra_bit_32:5] * 32) +: 32]; + dopa_tmp = memp[addra_tmp[14:r_addra_bit_32+1]][(addra_tmp[r_addra_bit_32:5] * 4) +: 4]; + end + end + 64 : begin + if (ra_width >= width) begin + doa_tmp = mem[addra_tmp[14:6]]; + dopa_tmp = memp[addra_tmp[14:6]]; + end + end + endcase // case(ra_width) + + end + endtask // task_rd_ram_a + + + task task_rd_ram_b; + + input [15:0] addrb_tmp; + inout [31:0] dob_tmp; + inout [3:0] dopb_tmp; + + begin + + case (rb_width) + 1, 2, 4 : begin + if (rb_width >= width) + dob_tmp = mem[addrb_tmp[14:r_addrb_lbit_124]]; + else + dob_tmp = mem[addrb_tmp[14:r_addrb_bit_124+1]][(addrb_tmp[r_addrb_bit_124:r_addrb_lbit_124] * rb_width) +: rb_width]; + end + 8 : begin + if (rb_width >= width) begin + dob_tmp = mem[addrb_tmp[14:3]]; + dopb_tmp = memp[addrb_tmp[14:3]]; + end + else begin + dob_tmp = mem[addrb_tmp[14:r_addrb_bit_8+1]][(addrb_tmp[r_addrb_bit_8:3] * 8) +: 8]; + dopb_tmp = memp[addrb_tmp[14:r_addrb_bit_8+1]][(addrb_tmp[r_addrb_bit_8:3] * 1) +: 1]; + end + end + 16 : begin + if (rb_width >= width) begin + dob_tmp = mem[addrb_tmp[14:4]]; + dopb_tmp = memp[addrb_tmp[14:4]]; + end + else begin + dob_tmp = mem[addrb_tmp[14:r_addrb_bit_16+1]][(addrb_tmp[r_addrb_bit_16:4] * 16) +: 16]; + dopb_tmp = memp[addrb_tmp[14:r_addrb_bit_16+1]][(addrb_tmp[r_addrb_bit_16:4] * 2) +: 2]; + end + end + 32 : begin + dob_tmp = mem[addrb_tmp[14:5]]; + dopb_tmp = memp[addrb_tmp[14:5]]; + end + + endcase + end + endtask // task_rd_ram_b + + + task chk_for_col_msg; + + input wea_tmp; + input web_tmp; + input [15:0] addra_tmp; + input [15:0] addrb_tmp; + + begin + + if ((SIM_COLLISION_CHECK == "ALL" || SIM_COLLISION_CHECK == "WARNING_ONLY") && !(rdaddr_collision_hwconfig_int == 0 && viol_time == 1 && ((wr_mode_b == 2'b01 && web_tmp === 1'b1 && wea_tmp === 1'b0) || (wr_mode_a == 2'b01 && wea_tmp === 1'b1 && web_tmp === 1'b0)))) + + if (wea_tmp === 1'b1 && web_tmp === 1'b1 && col_wr_wr_msg == 1) begin + $display("Memory Collision Error on RB36_INTERNAL_VLOG : %m at simulation time %.3f ns.\nA write was requested to the same address simultaneously at both port A and port B of the RAM. The contents written to the RAM at address location %h (hex) of port A and address location %h (hex) of port B are unknown.", $time/1000.0, addra_tmp, addrb_tmp); + col_wr_wr_msg = 0; + end + + else if (wea_tmp === 1'b1 && web_tmp === 1'b0 && col_wra_rdb_msg == 1) begin + + if ((wr_mode_a == 2'b01 || wr_mode_b == 2'b01) && ((viol_time == 1 && rdaddr_collision_hwconfig_int == 1) || viol_time == 2)) + $display("Memory Collision Error on RB36_INTERNAL_VLOG : %m at simulation time %.3f ns.\nA read was performed on address %h (hex) of port B while a write was requested to the same address on port A. The write will be unsuccessful and the content of the RAM at address location %h (hex) of port A became unknown.", $time/1000.0, addrb_tmp, addra_tmp); + else + $display("Memory Collision Error on RB36_INTERNAL_VLOG : %m at simulation time %.3f ns.\nA read was performed on address %h (hex) of port B while a write was requested to the same address on port A. The write will be successful however the read value on port B is unknown until the next CLKB cycle.", $time/1000.0, addrb_tmp); + + col_wra_rdb_msg = 0; + + end + else if (wea_tmp === 1'b0 && web_tmp === 1'b1 && col_wrb_rda_msg == 1) begin + + if ((wr_mode_a == 2'b01 || wr_mode_b == 2'b01) && ((viol_time == 1 && rdaddr_collision_hwconfig_int == 1) || viol_time == 2)) + $display("Memory Collision Error on RB36_INTERNAL_VLOG : %m at simulation time %.3f ns.\nA read was performed on address %h (hex) of port A while a write was requested to the same address on port B. The write will be unsuccessful and the content of the RAM at address location %h (hex) of port B became unknown.", $time/1000.0, addra_tmp, addrb_tmp); + else + $display("Memory Collision Error on RB36_INTERNAL_VLOG : %m at simulation time %.3f ns.\nA read was performed on address %h (hex) of port A while a write was requested to the same address on port B. The write will be successful however the read value on port A is unknown until the next CLKA cycle.", $time/1000.0, addra_tmp); + + col_wrb_rda_msg = 0; + + end + + end + + endtask // chk_for_col_msg + + + task task_col_ecc_read; + + inout [63:0] do_tmp; + inout [7:0] dop_tmp; + input [15:0] addr_tmp; + + reg [71:0] task_ecc_bit_position; + reg [7:0] task_dopr_ecc, task_syndrome; + reg [63:0] task_di_in_ecc_corrected; + reg [7:0] task_dip_in_ecc_corrected; + + begin + + if (|do_tmp === 1'bx) begin // if there is collision + dbiterr_out <= 1'bx; + sbiterr_out <= 1'bx; + end + else begin + + task_dopr_ecc = fn_dip_ecc(1'b0, do_tmp, dop_tmp); + + task_syndrome = task_dopr_ecc ^ dop_tmp; + + if (task_syndrome !== 0) begin + + if (task_syndrome[7]) begin // dectect single bit error + + task_ecc_bit_position = {do_tmp[63:57], dop_tmp[6], do_tmp[56:26], dop_tmp[5], do_tmp[25:11], dop_tmp[4], do_tmp[10:4], dop_tmp[3], do_tmp[3:1], dop_tmp[2], do_tmp[0], dop_tmp[1:0], dop_tmp[7]}; + + + if (task_syndrome[6:0] > 71) begin + $display ("DRC Error : Simulation halted due Corrupted DIP. To correct this problem, make sure that reliable data is fed to the DIP. The correct Parity must be generated by a Hamming code encoder or encoder in the Block RAM. The output from the model is unreliable if there are more than 2 bit errors. The model doesn't warn if there is sporadic input of more than 2 bit errors due to the limitation in Hamming code."); + $finish; + end + + task_ecc_bit_position[task_syndrome[6:0]] = ~task_ecc_bit_position[task_syndrome[6:0]]; // correct single bit error in the output + + task_di_in_ecc_corrected = {task_ecc_bit_position[71:65], task_ecc_bit_position[63:33], task_ecc_bit_position[31:17], task_ecc_bit_position[15:9], task_ecc_bit_position[7:5], task_ecc_bit_position[3]}; // correct single bit error in the memory + + do_tmp = task_di_in_ecc_corrected; + + task_dip_in_ecc_corrected = {task_ecc_bit_position[0], task_ecc_bit_position[64], task_ecc_bit_position[32], task_ecc_bit_position[16], task_ecc_bit_position[8], task_ecc_bit_position[4], task_ecc_bit_position[2:1]}; // correct single bit error in the parity memory + + dop_tmp = task_dip_in_ecc_corrected; + + dbiterr_out <= 0; + sbiterr_out <= 1; + + end + else if (!task_syndrome[7]) begin // double bit error + sbiterr_out <= 0; + dbiterr_out <= 1; + + end + end // if (task_syndrome !== 0) + else begin + dbiterr_out <= 0; + sbiterr_out <= 0; + + end // else: !if(task_syndrome !== 0) + + end + + end + + endtask // task_col_ecc_read + + + function [7:0] fn_dip_ecc; + + input encode; + input [63:0] di_in; + input [7:0] dip_in; + + begin + + fn_dip_ecc[0] = di_in[0]^di_in[1]^di_in[3]^di_in[4]^di_in[6]^di_in[8] + ^di_in[10]^di_in[11]^di_in[13]^di_in[15]^di_in[17]^di_in[19] + ^di_in[21]^di_in[23]^di_in[25]^di_in[26]^di_in[28] + ^di_in[30]^di_in[32]^di_in[34]^di_in[36]^di_in[38] + ^di_in[40]^di_in[42]^di_in[44]^di_in[46]^di_in[48] + ^di_in[50]^di_in[52]^di_in[54]^di_in[56]^di_in[57]^di_in[59] + ^di_in[61]^di_in[63]; + + fn_dip_ecc[1] = di_in[0]^di_in[2]^di_in[3]^di_in[5]^di_in[6]^di_in[9] + ^di_in[10]^di_in[12]^di_in[13]^di_in[16]^di_in[17] + ^di_in[20]^di_in[21]^di_in[24]^di_in[25]^di_in[27]^di_in[28] + ^di_in[31]^di_in[32]^di_in[35]^di_in[36]^di_in[39] + ^di_in[40]^di_in[43]^di_in[44]^di_in[47]^di_in[48] + ^di_in[51]^di_in[52]^di_in[55]^di_in[56]^di_in[58]^di_in[59] + ^di_in[62]^di_in[63]; + + fn_dip_ecc[2] = di_in[1]^di_in[2]^di_in[3]^di_in[7]^di_in[8]^di_in[9] + ^di_in[10]^di_in[14]^di_in[15]^di_in[16]^di_in[17] + ^di_in[22]^di_in[23]^di_in[24]^di_in[25]^di_in[29] + ^di_in[30]^di_in[31]^di_in[32]^di_in[37]^di_in[38]^di_in[39] + ^di_in[40]^di_in[45]^di_in[46]^di_in[47]^di_in[48] + ^di_in[53]^di_in[54]^di_in[55]^di_in[56] + ^di_in[60]^di_in[61]^di_in[62]^di_in[63]; + + fn_dip_ecc[3] = di_in[4]^di_in[5]^di_in[6]^di_in[7]^di_in[8]^di_in[9] + ^di_in[10]^di_in[18]^di_in[19] + ^di_in[20]^di_in[21]^di_in[22]^di_in[23]^di_in[24]^di_in[25] + ^di_in[33]^di_in[34]^di_in[35]^di_in[36]^di_in[37]^di_in[38]^di_in[39] + ^di_in[40]^di_in[49] + ^di_in[50]^di_in[51]^di_in[52]^di_in[53]^di_in[54]^di_in[55]^di_in[56]; + + fn_dip_ecc[4] = di_in[11]^di_in[12]^di_in[13]^di_in[14]^di_in[15]^di_in[16]^di_in[17]^di_in[18]^di_in[19] + ^di_in[20]^di_in[21]^di_in[22]^di_in[23]^di_in[24]^di_in[25] + ^di_in[41]^di_in[42]^di_in[43]^di_in[44]^di_in[45]^di_in[46]^di_in[47]^di_in[48]^di_in[49] + ^di_in[50]^di_in[51]^di_in[52]^di_in[53]^di_in[54]^di_in[55]^di_in[56]; + + + fn_dip_ecc[5] = di_in[26]^di_in[27]^di_in[28]^di_in[29] + ^di_in[30]^di_in[31]^di_in[32]^di_in[33]^di_in[34]^di_in[35]^di_in[36]^di_in[37]^di_in[38]^di_in[39] + ^di_in[40]^di_in[41]^di_in[42]^di_in[43]^di_in[44]^di_in[45]^di_in[46]^di_in[47]^di_in[48]^di_in[49] + ^di_in[50]^di_in[51]^di_in[52]^di_in[53]^di_in[54]^di_in[55]^di_in[56]; + + fn_dip_ecc[6] = di_in[57]^di_in[58]^di_in[59] + ^di_in[60]^di_in[61]^di_in[62]^di_in[63]; + + if (encode == 1'b1) + + fn_dip_ecc[7] = fn_dip_ecc[0]^fn_dip_ecc[1]^fn_dip_ecc[2]^fn_dip_ecc[3]^fn_dip_ecc[4]^fn_dip_ecc[5]^fn_dip_ecc[6] + ^di_in[0]^di_in[1]^di_in[2]^di_in[3]^di_in[4]^di_in[5]^di_in[6]^di_in[7]^di_in[8]^di_in[9] + ^di_in[10]^di_in[11]^di_in[12]^di_in[13]^di_in[14]^di_in[15]^di_in[16]^di_in[17]^di_in[18]^di_in[19] + ^di_in[20]^di_in[21]^di_in[22]^di_in[23]^di_in[24]^di_in[25]^di_in[26]^di_in[27]^di_in[28]^di_in[29] + ^di_in[30]^di_in[31]^di_in[32]^di_in[33]^di_in[34]^di_in[35]^di_in[36]^di_in[37]^di_in[38]^di_in[39] + ^di_in[40]^di_in[41]^di_in[42]^di_in[43]^di_in[44]^di_in[45]^di_in[46]^di_in[47]^di_in[48]^di_in[49] + ^di_in[50]^di_in[51]^di_in[52]^di_in[53]^di_in[54]^di_in[55]^di_in[56]^di_in[57]^di_in[58]^di_in[59] + ^di_in[60]^di_in[61]^di_in[62]^di_in[63]; + else + fn_dip_ecc[7] = dip_in[0]^dip_in[1]^dip_in[2]^dip_in[3]^dip_in[4]^dip_in[5]^dip_in[6] + ^di_in[0]^di_in[1]^di_in[2]^di_in[3]^di_in[4]^di_in[5]^di_in[6]^di_in[7]^di_in[8]^di_in[9] + ^di_in[10]^di_in[11]^di_in[12]^di_in[13]^di_in[14]^di_in[15]^di_in[16]^di_in[17]^di_in[18]^di_in[19] + ^di_in[20]^di_in[21]^di_in[22]^di_in[23]^di_in[24]^di_in[25]^di_in[26]^di_in[27]^di_in[28]^di_in[29] + ^di_in[30]^di_in[31]^di_in[32]^di_in[33]^di_in[34]^di_in[35]^di_in[36]^di_in[37]^di_in[38]^di_in[39] + ^di_in[40]^di_in[41]^di_in[42]^di_in[43]^di_in[44]^di_in[45]^di_in[46]^di_in[47]^di_in[48]^di_in[49] + ^di_in[50]^di_in[51]^di_in[52]^di_in[53]^di_in[54]^di_in[55]^di_in[56]^di_in[57]^di_in[58]^di_in[59] + ^di_in[60]^di_in[61]^di_in[62]^di_in[63]; + + end + + endfunction // fn_dip_ecc + +/******************************************** END task and function **************************************/ + + + initial begin + + if (INIT_FILE == "NONE") begin // memory initialization from attributes + + init_mult = 256/width; + + for (count = 0; count < init_mult; count = count + 1) begin + + init_offset = count * width; + + mem[count] = INIT_00[init_offset +:width]; + mem[count + (init_mult * 1)] = INIT_01[init_offset +:width]; + mem[count + (init_mult * 2)] = INIT_02[init_offset +:width]; + mem[count + (init_mult * 3)] = INIT_03[init_offset +:width]; + mem[count + (init_mult * 4)] = INIT_04[init_offset +:width]; + mem[count + (init_mult * 5)] = INIT_05[init_offset +:width]; + mem[count + (init_mult * 6)] = INIT_06[init_offset +:width]; + mem[count + (init_mult * 7)] = INIT_07[init_offset +:width]; + mem[count + (init_mult * 8)] = INIT_08[init_offset +:width]; + mem[count + (init_mult * 9)] = INIT_09[init_offset +:width]; + mem[count + (init_mult * 10)] = INIT_0A[init_offset +:width]; + mem[count + (init_mult * 11)] = INIT_0B[init_offset +:width]; + mem[count + (init_mult * 12)] = INIT_0C[init_offset +:width]; + mem[count + (init_mult * 13)] = INIT_0D[init_offset +:width]; + mem[count + (init_mult * 14)] = INIT_0E[init_offset +:width]; + mem[count + (init_mult * 15)] = INIT_0F[init_offset +:width]; + mem[count + (init_mult * 16)] = INIT_10[init_offset +:width]; + mem[count + (init_mult * 17)] = INIT_11[init_offset +:width]; + mem[count + (init_mult * 18)] = INIT_12[init_offset +:width]; + mem[count + (init_mult * 19)] = INIT_13[init_offset +:width]; + mem[count + (init_mult * 20)] = INIT_14[init_offset +:width]; + mem[count + (init_mult * 21)] = INIT_15[init_offset +:width]; + mem[count + (init_mult * 22)] = INIT_16[init_offset +:width]; + mem[count + (init_mult * 23)] = INIT_17[init_offset +:width]; + mem[count + (init_mult * 24)] = INIT_18[init_offset +:width]; + mem[count + (init_mult * 25)] = INIT_19[init_offset +:width]; + mem[count + (init_mult * 26)] = INIT_1A[init_offset +:width]; + mem[count + (init_mult * 27)] = INIT_1B[init_offset +:width]; + mem[count + (init_mult * 28)] = INIT_1C[init_offset +:width]; + mem[count + (init_mult * 29)] = INIT_1D[init_offset +:width]; + mem[count + (init_mult * 30)] = INIT_1E[init_offset +:width]; + mem[count + (init_mult * 31)] = INIT_1F[init_offset +:width]; + mem[count + (init_mult * 32)] = INIT_20[init_offset +:width]; + mem[count + (init_mult * 33)] = INIT_21[init_offset +:width]; + mem[count + (init_mult * 34)] = INIT_22[init_offset +:width]; + mem[count + (init_mult * 35)] = INIT_23[init_offset +:width]; + mem[count + (init_mult * 36)] = INIT_24[init_offset +:width]; + mem[count + (init_mult * 37)] = INIT_25[init_offset +:width]; + mem[count + (init_mult * 38)] = INIT_26[init_offset +:width]; + mem[count + (init_mult * 39)] = INIT_27[init_offset +:width]; + mem[count + (init_mult * 40)] = INIT_28[init_offset +:width]; + mem[count + (init_mult * 41)] = INIT_29[init_offset +:width]; + mem[count + (init_mult * 42)] = INIT_2A[init_offset +:width]; + mem[count + (init_mult * 43)] = INIT_2B[init_offset +:width]; + mem[count + (init_mult * 44)] = INIT_2C[init_offset +:width]; + mem[count + (init_mult * 45)] = INIT_2D[init_offset +:width]; + mem[count + (init_mult * 46)] = INIT_2E[init_offset +:width]; + mem[count + (init_mult * 47)] = INIT_2F[init_offset +:width]; + mem[count + (init_mult * 48)] = INIT_30[init_offset +:width]; + mem[count + (init_mult * 49)] = INIT_31[init_offset +:width]; + mem[count + (init_mult * 50)] = INIT_32[init_offset +:width]; + mem[count + (init_mult * 51)] = INIT_33[init_offset +:width]; + mem[count + (init_mult * 52)] = INIT_34[init_offset +:width]; + mem[count + (init_mult * 53)] = INIT_35[init_offset +:width]; + mem[count + (init_mult * 54)] = INIT_36[init_offset +:width]; + mem[count + (init_mult * 55)] = INIT_37[init_offset +:width]; + mem[count + (init_mult * 56)] = INIT_38[init_offset +:width]; + mem[count + (init_mult * 57)] = INIT_39[init_offset +:width]; + mem[count + (init_mult * 58)] = INIT_3A[init_offset +:width]; + mem[count + (init_mult * 59)] = INIT_3B[init_offset +:width]; + mem[count + (init_mult * 60)] = INIT_3C[init_offset +:width]; + mem[count + (init_mult * 61)] = INIT_3D[init_offset +:width]; + mem[count + (init_mult * 62)] = INIT_3E[init_offset +:width]; + mem[count + (init_mult * 63)] = INIT_3F[init_offset +:width]; + + if (BRAM_SIZE == 36) begin + mem[count + (init_mult * 64)] = INIT_40[init_offset +:width]; + mem[count + (init_mult * 65)] = INIT_41[init_offset +:width]; + mem[count + (init_mult * 66)] = INIT_42[init_offset +:width]; + mem[count + (init_mult * 67)] = INIT_43[init_offset +:width]; + mem[count + (init_mult * 68)] = INIT_44[init_offset +:width]; + mem[count + (init_mult * 69)] = INIT_45[init_offset +:width]; + mem[count + (init_mult * 70)] = INIT_46[init_offset +:width]; + mem[count + (init_mult * 71)] = INIT_47[init_offset +:width]; + mem[count + (init_mult * 72)] = INIT_48[init_offset +:width]; + mem[count + (init_mult * 73)] = INIT_49[init_offset +:width]; + mem[count + (init_mult * 74)] = INIT_4A[init_offset +:width]; + mem[count + (init_mult * 75)] = INIT_4B[init_offset +:width]; + mem[count + (init_mult * 76)] = INIT_4C[init_offset +:width]; + mem[count + (init_mult * 77)] = INIT_4D[init_offset +:width]; + mem[count + (init_mult * 78)] = INIT_4E[init_offset +:width]; + mem[count + (init_mult * 79)] = INIT_4F[init_offset +:width]; + mem[count + (init_mult * 80)] = INIT_50[init_offset +:width]; + mem[count + (init_mult * 81)] = INIT_51[init_offset +:width]; + mem[count + (init_mult * 82)] = INIT_52[init_offset +:width]; + mem[count + (init_mult * 83)] = INIT_53[init_offset +:width]; + mem[count + (init_mult * 84)] = INIT_54[init_offset +:width]; + mem[count + (init_mult * 85)] = INIT_55[init_offset +:width]; + mem[count + (init_mult * 86)] = INIT_56[init_offset +:width]; + mem[count + (init_mult * 87)] = INIT_57[init_offset +:width]; + mem[count + (init_mult * 88)] = INIT_58[init_offset +:width]; + mem[count + (init_mult * 89)] = INIT_59[init_offset +:width]; + mem[count + (init_mult * 90)] = INIT_5A[init_offset +:width]; + mem[count + (init_mult * 91)] = INIT_5B[init_offset +:width]; + mem[count + (init_mult * 92)] = INIT_5C[init_offset +:width]; + mem[count + (init_mult * 93)] = INIT_5D[init_offset +:width]; + mem[count + (init_mult * 94)] = INIT_5E[init_offset +:width]; + mem[count + (init_mult * 95)] = INIT_5F[init_offset +:width]; + mem[count + (init_mult * 96)] = INIT_60[init_offset +:width]; + mem[count + (init_mult * 97)] = INIT_61[init_offset +:width]; + mem[count + (init_mult * 98)] = INIT_62[init_offset +:width]; + mem[count + (init_mult * 99)] = INIT_63[init_offset +:width]; + mem[count + (init_mult * 100)] = INIT_64[init_offset +:width]; + mem[count + (init_mult * 101)] = INIT_65[init_offset +:width]; + mem[count + (init_mult * 102)] = INIT_66[init_offset +:width]; + mem[count + (init_mult * 103)] = INIT_67[init_offset +:width]; + mem[count + (init_mult * 104)] = INIT_68[init_offset +:width]; + mem[count + (init_mult * 105)] = INIT_69[init_offset +:width]; + mem[count + (init_mult * 106)] = INIT_6A[init_offset +:width]; + mem[count + (init_mult * 107)] = INIT_6B[init_offset +:width]; + mem[count + (init_mult * 108)] = INIT_6C[init_offset +:width]; + mem[count + (init_mult * 109)] = INIT_6D[init_offset +:width]; + mem[count + (init_mult * 110)] = INIT_6E[init_offset +:width]; + mem[count + (init_mult * 111)] = INIT_6F[init_offset +:width]; + mem[count + (init_mult * 112)] = INIT_70[init_offset +:width]; + mem[count + (init_mult * 113)] = INIT_71[init_offset +:width]; + mem[count + (init_mult * 114)] = INIT_72[init_offset +:width]; + mem[count + (init_mult * 115)] = INIT_73[init_offset +:width]; + mem[count + (init_mult * 116)] = INIT_74[init_offset +:width]; + mem[count + (init_mult * 117)] = INIT_75[init_offset +:width]; + mem[count + (init_mult * 118)] = INIT_76[init_offset +:width]; + mem[count + (init_mult * 119)] = INIT_77[init_offset +:width]; + mem[count + (init_mult * 120)] = INIT_78[init_offset +:width]; + mem[count + (init_mult * 121)] = INIT_79[init_offset +:width]; + mem[count + (init_mult * 122)] = INIT_7A[init_offset +:width]; + mem[count + (init_mult * 123)] = INIT_7B[init_offset +:width]; + mem[count + (init_mult * 124)] = INIT_7C[init_offset +:width]; + mem[count + (init_mult * 125)] = INIT_7D[init_offset +:width]; + mem[count + (init_mult * 126)] = INIT_7E[init_offset +:width]; + mem[count + (init_mult * 127)] = INIT_7F[init_offset +:width]; + end // if (BRAM_SIZE == 36) + end // for (count = 0; count < init_mult; count = count + 1) + + + + if (width >= 8) begin + + initp_mult = 256/widthp; + + for (countp = 0; countp < initp_mult; countp = countp + 1) begin + + initp_offset = countp * widthp; + + memp[countp] = INITP_00[initp_offset +:widthp]; + memp[countp + (initp_mult * 1)] = INITP_01[initp_offset +:widthp]; + memp[countp + (initp_mult * 2)] = INITP_02[initp_offset +:widthp]; + memp[countp + (initp_mult * 3)] = INITP_03[initp_offset +:widthp]; + memp[countp + (initp_mult * 4)] = INITP_04[initp_offset +:widthp]; + memp[countp + (initp_mult * 5)] = INITP_05[initp_offset +:widthp]; + memp[countp + (initp_mult * 6)] = INITP_06[initp_offset +:widthp]; + memp[countp + (initp_mult * 7)] = INITP_07[initp_offset +:widthp]; + + if (BRAM_SIZE == 36) begin + memp[countp + (initp_mult * 8)] = INITP_08[initp_offset +:widthp]; + memp[countp + (initp_mult * 9)] = INITP_09[initp_offset +:widthp]; + memp[countp + (initp_mult * 10)] = INITP_0A[initp_offset +:widthp]; + memp[countp + (initp_mult * 11)] = INITP_0B[initp_offset +:widthp]; + memp[countp + (initp_mult * 12)] = INITP_0C[initp_offset +:widthp]; + memp[countp + (initp_mult * 13)] = INITP_0D[initp_offset +:widthp]; + memp[countp + (initp_mult * 14)] = INITP_0E[initp_offset +:widthp]; + memp[countp + (initp_mult * 15)] = INITP_0F[initp_offset +:widthp]; + end + end // for (countp = 0; countp < initp_mult; countp = countp + 1) + end // if (width >= 8) + + end // if (INIT_FILE == "NONE") + + else begin // memory initialization from memory file + + $readmemh (INIT_FILE, tmp_mem); + + case (widest_width) + + 1, 2, 4 : for (i_mem = 0; i_mem <= mem_depth; i_mem = i_mem + 1) + mem[i_mem] = tmp_mem [i_mem]; + + 9 : for (i_mem = 0; i_mem <= mem_depth; i_mem = i_mem + 1) begin + mem[i_mem] = tmp_mem[i_mem][0 +: 8]; + memp[i_mem] = tmp_mem[i_mem][8 +: 1]; + end + + 18 : for (i_mem = 0; i_mem <= mem_depth; i_mem = i_mem + 1) begin + mem[i_mem] = tmp_mem[i_mem][0 +: 16]; + memp[i_mem] = tmp_mem[i_mem][16 +: 2]; + end + + 36 : for (i_mem = 0; i_mem <= mem_depth; i_mem = i_mem + 1) begin + mem[i_mem] = tmp_mem[i_mem][0 +: 32]; + memp[i_mem] = tmp_mem[i_mem][32 +: 4]; + end + + 72 : for (i_mem = 0; i_mem <= mem_depth; i_mem = i_mem + 1) begin + mem[i_mem] = tmp_mem[i_mem][0 +: 64]; + memp[i_mem] = tmp_mem[i_mem][64 +: 8]; + end + + endcase // case(widest_width) + + end // else: !if(INIT_FILE == "NONE") + + + case (EN_ECC_WRITE) + "TRUE" : en_ecc_write_int = 1; + "FALSE" : en_ecc_write_int = 0; + default : begin + $display("Attribute Syntax Error : The attribute EN_ECC_WRITE on RB36_INTERNAL_VLOG instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", EN_ECC_WRITE); + finish_error = 1; + end + endcase + + + case (EN_ECC_READ) + "TRUE" : en_ecc_read_int = 1; + "FALSE" : en_ecc_read_int = 0; + default : begin + $display("Attribute Syntax Error : The attribute EN_ECC_READ on RB36_INTERNAL_VLOG instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", EN_ECC_READ); + finish_error = 1; + end + endcase + + + case (RAM_MODE) + "TDP" : begin + ram_mode_int = 1; + + if (en_ecc_write_int == 1) begin + $display("DRC Error : The attribute EN_ECC_WRITE on RB36_INTERNAL_VLOG instance %m is set to %s which requires RAM_MODE = SDP.", EN_ECC_WRITE); + finish_error = 1; + end + + if (en_ecc_read_int == 1) begin + $display("DRC Error : The attribute EN_ECC_READ on RB36_INTERNAL_VLOG instance %m is set to %s which requires RAM_MODE = SDP.", EN_ECC_READ); + finish_error = 1; + end + + end // case: "TDP" + "SDP" : begin + ram_mode_int = 0; + + if ((WRITE_MODE_A != WRITE_MODE_B) || WRITE_MODE_A == "NO_CHANGE" || WRITE_MODE_A == "NO_CHANGE") begin + + $display("DRC Error : Both attributes WRITE_MODE_A and WRITE_MODE_B must be set to READ_FIRST or both attributes must be set to WRITE_FIRST when RAM_MODE = SDP on RB36_INTERNAL_VLOG instance %m."); + + finish_error = 1; + + end + + + if (BRAM_SIZE == 18) begin + if (!(WRITE_WIDTH_B == 36 || READ_WIDTH_A == 36)) begin + + $display("DRC Error : One of the attribute WRITE_WIDTH_B or READ_WIDTH_A must set to 36 when RAM_MODE = SDP."); + + finish_error = 1; + end + end + else begin + + if (!(WRITE_WIDTH_B == 72 || READ_WIDTH_A == 72)) begin + $display("DRC Error : One of the attribute WRITE_WIDTH_B or READ_WIDTH_A must set to 72 when RAM_MODE = SDP."); + finish_error = 1; + end + end // else: !if(BRAM_SIZE == 18) + + end // case: "SDP" + default : begin + $display("Attribute Syntax Error : The attribute RAM_MODE on RB36_INTERNAL_VLOG instance %m is set to %s. Legal values for this attribute are TDP or SDP.", RAM_MODE); + finish_error = 1; + end + endcase + + + case (WRITE_WIDTH_A) + + 0, 1, 2, 4, 9, 18 : ; + 36 : begin + if (BRAM_SIZE == 18 && ram_mode_int == 1) begin + $display("Attribute Syntax Error : The attribute WRITE_WIDTH_A on RB36_INTERNAL_VLOG instance %m is set to %d. Legal values for this attribute are 0, 1, 2, 4, 9 or 18.", WRITE_WIDTH_A); + finish_error = 1; + end + end + 72 : begin + if (BRAM_SIZE == 18) begin + $display("Attribute Syntax Error : The attribute WRITE_WIDTH_A on RB36_INTERNAL_VLOG instance %m is set to %d. Legal values for this attribute are 0, 1, 2, 4, 9 or 18.", WRITE_WIDTH_A); + finish_error = 1; + end + else if (BRAM_SIZE == 36 && ram_mode_int == 1) begin + $display("Attribute Syntax Error : The attribute WRITE_WIDTH_A on RB36_INTERNAL_VLOG instance %m is set to %d. Legal values for this attribute are 0, 1, 2, 4, 9, 18 or 36.", WRITE_WIDTH_A); + finish_error = 1; + end + end + default : begin + if (BRAM_SIZE == 18 && ram_mode_int == 1) begin + $display("Attribute Syntax Error : The attribute WRITE_WIDTH_A on RB36_INTERNAL_VLOG instance %m is set to %d. Legal values for this attribute are 0, 1, 2, 4, 9 or 18.", WRITE_WIDTH_A); + finish_error = 1; + end + else if (BRAM_SIZE == 36 || (BRAM_SIZE == 18 && ram_mode_int == 0)) begin + $display("Attribute Syntax Error : The attribute WRITE_WIDTH_A on RB36_INTERNAL_VLOG instance %m is set to %d. Legal values for this attribute are 0, 1, 2, 4, 9, 18 or 36.", WRITE_WIDTH_A); + finish_error = 1; + end + end + + endcase // case(WRITE_WIDTH_A) + + + case (WRITE_WIDTH_B) + + 0, 1, 2, 4, 9, 18 : ; + 36 : begin + if (BRAM_SIZE == 18 && ram_mode_int == 1) begin + $display("Attribute Syntax Error : The attribute WRITE_WIDTH_B on RB36_INTERNAL_VLOG instance %m is set to %d. Legal values for this attribute are 0, 1, 2, 4, 9 or 18.", WRITE_WIDTH_B); + finish_error = 1; + end + end + 72 : begin + if (BRAM_SIZE == 18) begin + $display("Attribute Syntax Error : The attribute WRITE_WIDTH_B on RB36_INTERNAL_VLOG instance %m is set to %d. Legal values for this attribute are 0, 1, 2, 4, 9 or 18.", WRITE_WIDTH_B); + finish_error = 1; + end + else if (BRAM_SIZE == 36 && ram_mode_int == 1) begin + $display("Attribute Syntax Error : The attribute WRITE_WIDTH_B on RB36_INTERNAL_VLOG instance %m is set to %d. Legal values for this attribute are 0, 1, 2, 4, 9, 18 or 36.", WRITE_WIDTH_B); + finish_error = 1; + end + end + default : begin + if (BRAM_SIZE == 18 && ram_mode_int == 1) begin + $display("Attribute Syntax Error : The attribute WRITE_WIDTH_B on RB36_INTERNAL_VLOG instance %m is set to %d. Legal values for this attribute are 0, 1, 2, 4, 9 or 18.", WRITE_WIDTH_B); + finish_error = 1; + end + else if (BRAM_SIZE == 36 || (BRAM_SIZE == 18 && ram_mode_int == 0)) begin + $display("Attribute Syntax Error : The attribute WRITE_WIDTH_B on RB36_INTERNAL_VLOG instance %m is set to %d. Legal values for this attribute are 0, 1, 2, 4, 9, 18 or 36.", WRITE_WIDTH_B); + finish_error = 1; + end + end + + endcase // case(WRITE_WIDTH_B) + + + case (READ_WIDTH_A) + + 0, 1, 2, 4, 9, 18 : ; + 36 : begin + if (BRAM_SIZE == 18 && ram_mode_int == 1) begin + $display("Attribute Syntax Error : The attribute READ_WIDTH_A on RB36_INTERNAL_VLOG instance %m is set to %d. Legal values for this attribute are 0, 1, 2, 4, 9 or 18.", READ_WIDTH_A); + finish_error = 1; + end + end + 72 : begin + if (BRAM_SIZE == 18) begin + $display("Attribute Syntax Error : The attribute READ_WIDTH_A on RB36_INTERNAL_VLOG instance %m is set to %d. Legal values for this attribute are 0, 1, 2, 4, 9 or 18.", READ_WIDTH_A); + finish_error = 1; + end + else if (BRAM_SIZE == 36 && ram_mode_int == 1) begin + $display("Attribute Syntax Error : The attribute READ_WIDTH_A on RB36_INTERNAL_VLOG instance %m is set to %d. Legal values for this attribute are 0, 1, 2, 4, 9, 18 or 36.", READ_WIDTH_A); + finish_error = 1; + end + end + default : begin + if (BRAM_SIZE == 18 && ram_mode_int == 1) begin + $display("Attribute Syntax Error : The attribute READ_WIDTH_A on RB36_INTERNAL_VLOG instance %m is set to %d. Legal values for this attribute are 0, 1, 2, 4, 9 or 18.", READ_WIDTH_A); + finish_error = 1; + end + else if (BRAM_SIZE == 36 || (BRAM_SIZE == 18 && ram_mode_int == 0)) begin + $display("Attribute Syntax Error : The attribute READ_WIDTH_A on RB36_INTERNAL_VLOG instance %m is set to %d. Legal values for this attribute are 0, 1, 2, 4, 9, 18 or 36.", READ_WIDTH_A); + finish_error = 1; + end + end + + endcase // case(READ_WIDTH_A) + + + case (READ_WIDTH_B) + + 0, 1, 2, 4, 9, 18 : ; + 36 : begin + if (BRAM_SIZE == 18 && ram_mode_int == 1) begin + $display("Attribute Syntax Error : The attribute READ_WIDTH_B on RB36_INTERNAL_VLOG instance %m is set to %d. Legal values for this attribute are 0, 1, 2, 4, 9 or 18.", READ_WIDTH_B); + finish_error = 1; + end + end + 72 : begin + if (BRAM_SIZE == 18) begin + $display("Attribute Syntax Error : The attribute READ_WIDTH_B on RB36_INTERNAL_VLOG instance %m is set to %d. Legal values for this attribute are 0, 1, 2, 4, 9 or 18.", READ_WIDTH_B); + finish_error = 1; + end + else if (BRAM_SIZE == 36 && ram_mode_int == 1) begin + $display("Attribute Syntax Error : The attribute READ_WIDTH_B on RB36_INTERNAL_VLOG instance %m is set to %d. Legal values for this attribute are 0, 1, 2, 4, 9, 18 or 36.", READ_WIDTH_B); + finish_error = 1; + end + end + default : begin + if (BRAM_SIZE == 18 && ram_mode_int == 1) begin + $display("Attribute Syntax Error : The attribute READ_WIDTH_B on RB36_INTERNAL_VLOG instance %m is set to %d. Legal values for this attribute are 0, 1, 2, 4, 9 or 18.", READ_WIDTH_B); + finish_error = 1; + end + else if (BRAM_SIZE == 36 || (BRAM_SIZE == 18 && ram_mode_int == 0)) begin + $display("Attribute Syntax Error : The attribute READ_WIDTH_B on RB36_INTERNAL_VLOG instance %m is set to %d. Legal values for this attribute are 0, 1, 2, 4, 9, 18 or 36.", READ_WIDTH_B); + finish_error = 1; + end + end + + endcase // case(READ_WIDTH_B) + + + if ((RAM_EXTENSION_A == "LOWER" || RAM_EXTENSION_A == "UPPER") && READ_WIDTH_A != 1) begin + $display("Attribute Syntax Error : If attribute RAM_EXTENSION_A on RB36_INTERNAL_VLOG instance %m is set to either LOWER or UPPER, then READ_WIDTH_A has to be set to 1."); + finish_error = 1; + end + + + if ((RAM_EXTENSION_A == "LOWER" || RAM_EXTENSION_A == "UPPER") && WRITE_WIDTH_A != 1) begin + $display("Attribute Syntax Error : If attribute RAM_EXTENSION_A on RB36_INTERNAL_VLOG instance %m is set to either LOWER or UPPER, then WRITE_WIDTH_A has to be set to 1."); + finish_error = 1; + end + + + if ((RAM_EXTENSION_B == "LOWER" || RAM_EXTENSION_B == "UPPER") && READ_WIDTH_B != 1) begin + $display("Attribute Syntax Error : If attribute RAM_EXTENSION_B on RB36_INTERNAL_VLOG instance %m is set to either LOWER or UPPER, then READ_WIDTH_B has to be set to 1."); + finish_error = 1; + end + + + if ((RAM_EXTENSION_B == "LOWER" || RAM_EXTENSION_B == "UPPER") && WRITE_WIDTH_B != 1) begin + $display("Attribute Syntax Error : If attribute RAM_EXTENSION_B on RB36_INTERNAL_VLOG instance %m is set to either LOWER or UPPER, then WRITE_WIDTH_B has to be set to 1."); + finish_error = 1; + end + + + if (READ_WIDTH_A == 0 && READ_WIDTH_B == 0) begin + $display("Attribute Syntax Error : Attributes READ_WIDTH_A and READ_WIDTH_B on RB36_INTERNAL_VLOG instance %m, both can not be 0."); + finish_error = 1; + end + + + case (WRITE_MODE_A) + "WRITE_FIRST" : wr_mode_a = 2'b00; + "READ_FIRST" : wr_mode_a = 2'b01; + "NO_CHANGE" : wr_mode_a = 2'b10; + default : begin + $display("Attribute Syntax Error : The Attribute WRITE_MODE_A on RB36_INTERNAL_VLOG instance %m is set to %s. Legal values for this attribute are WRITE_FIRST, READ_FIRST or NO_CHANGE.", WRITE_MODE_A); + finish_error = 1; + end + endcase + + + case (WRITE_MODE_B) + "WRITE_FIRST" : wr_mode_b = 2'b00; + "READ_FIRST" : wr_mode_b = 2'b01; + "NO_CHANGE" : wr_mode_b = 2'b10; + default : begin + $display("Attribute Syntax Error : The Attribute WRITE_MODE_B on RB36_INTERNAL_VLOG instance %m is set to %s. Legal values for this attribute are WRITE_FIRST, READ_FIRST or NO_CHANGE.", WRITE_MODE_B); + finish_error = 1; + end + endcase + + case (RAM_EXTENSION_A) + "UPPER" : cascade_a = 2'b11; + "LOWER" : cascade_a = 2'b01; + "NONE" : cascade_a = 2'b00; + default : begin + $display("Attribute Syntax Error : The attribute RAM_EXTENSION_A on RB36_INTERNAL_VLOG instance %m is set to %s. Legal values for this attribute are LOWER, NONE or UPPER.", RAM_EXTENSION_A); + finish_error = 1; + end + endcase + + + case (RAM_EXTENSION_B) + "UPPER" : cascade_b = 2'b11; + "LOWER" : cascade_b = 2'b01; + "NONE" : cascade_b = 2'b00; + default : begin + $display("Attribute Syntax Error : The attribute RAM_EXTENSION_B on RB36_INTERNAL_VLOG instance %m is set to %s. Legal values for this attribute are LOWER, NONE or UPPER.", RAM_EXTENSION_B); + finish_error = 1; + end + endcase + + + if ((SIM_COLLISION_CHECK != "ALL") && (SIM_COLLISION_CHECK != "NONE") && (SIM_COLLISION_CHECK != "WARNING_ONLY") && (SIM_COLLISION_CHECK != "GENERATE_X_ONLY")) begin + + $display("Attribute Syntax Error : The attribute SIM_COLLISION_CHECK on RB36_INTERNAL_VLOG instance %m is set to %s. Legal values for this attribute are ALL, NONE, WARNING_ONLY or GENERATE_X_ONLY.", SIM_COLLISION_CHECK); + finish_error = 1; + + end + + + case (RSTREG_PRIORITY_A) + "RSTREG" : rstreg_priority_a_int = 1; + "REGCE" : rstreg_priority_a_int = 0; + default : begin + $display("Attribute Syntax Error : The attribute RSTREG_PRIORITY_A on RB36_INTERNAL_VLOG instance %m is set to %s. Legal values for this attribute are RSTREG or REGCE.", RSTREG_PRIORITY_A); + finish_error = 1; + end + endcase + + + case (RSTREG_PRIORITY_B) + "RSTREG" : rstreg_priority_b_int = 1; + "REGCE" : rstreg_priority_b_int = 0; + default : begin + $display("Attribute Syntax Error : The attribute RSTREG_PRIORITY_B on RB36_INTERNAL_VLOG instance %m is set to %s. Legal values for this attribute are RSTREG or REGCE.", RSTREG_PRIORITY_B); + finish_error = 1; + end + endcase + + + if ((en_ecc_write_int == 1 || en_ecc_read_int == 1) && (WRITE_WIDTH_B != 72 || READ_WIDTH_A != 72)) begin + $display("DRC Error : Attributes WRITE_WIDTH_B and READ_WIDTH_A have to be set to 72 on RB36_INTERNAL_VLOG instance %m when either attribute EN_ECC_WRITE or EN_ECC_READ is set to TRUE."); + finish_error = 1; + end + + + case (RDADDR_COLLISION_HWCONFIG) + "DELAYED_WRITE" : rdaddr_collision_hwconfig_int = 0; + "PERFORMANCE" : rdaddr_collision_hwconfig_int = 1; + default : begin + $display("Attribute Syntax Error : The attribute RDADDR_COLLISION_HWCONFIG on RB36_INTERNAL_VLOG instance %m is set to %s. Legal values for this attribute are DELAYED_WRITE or PERFORMANCE.", RDADDR_COLLISION_HWCONFIG); + finish_error = 1; + end + endcase + + + if (finish_error == 1) + $finish; + + + end // initial begin + + + // GSR + always @(gsr_in) + if (gsr_in) begin + + assign doa_out = INIT_A[0 +: ra_width]; + + if (ra_width >= 8) begin + assign dopa_out = INIT_A[ra_width +: ra_widthp]; + end + + assign dob_out = INIT_B[0 +: rb_width]; + + if (rb_width >= 8) begin + assign dopb_out = INIT_B[rb_width +: rb_widthp]; + end + + assign dbiterr_out = 0; + assign sbiterr_out = 0; + assign rdaddrecc_out = 9'b0; + + end + else begin + deassign doa_out; + deassign dopa_out; + deassign dob_out; + deassign dopb_out; + deassign dbiterr_out; + deassign sbiterr_out; + deassign rdaddrecc_out; + + end + + + // registering signals + always @(posedge clka_in) begin + + rising_clka = 1; + + if (ena_in === 1'b1) begin + time_port_a = $time; + addra_reg = addra_in; + wea_reg = wea_in; + dia_reg = dia_in; + dipa_reg = dipa_in; + col_addra_reconstruct_reg = col_addra_reconstruct; + end + + end + + always @(posedge clkb_in) begin + + rising_clkb = 1; + + if (enb_in === 1'b1) begin + time_port_b = $time; + addrb_reg = addrb_in; + web_reg = web_in; + enb_reg = enb_in; + dib_reg = dib_in; + dipb_reg = dipb_in; + col_addrb_reconstruct_reg = col_addrb_reconstruct; + end + + end // always @ (posedge clkb_in) + + + // CLKA and CLKB + always @(posedge rising_clka or posedge rising_clkb) begin + + // Registering addr[15] for cascade mode + if (rising_clka) + if (cascade_a[1]) + addra_in_15_reg_bram = ~addra_in[15]; + else + addra_in_15_reg_bram = addra_in[15]; + + if (rising_clkb) + if (cascade_b[1]) + addrb_in_15_reg_bram = ~addrb_in[15]; + else + addrb_in_15_reg_bram = addrb_in[15]; + + if ((cascade_a == 2'b00 || (addra_in_15_reg_bram == 1'b0 && cascade_a != 2'b00)) && (cascade_b == 2'b00 || (addrb_in_15_reg_bram == 1'b0 && cascade_b != 2'b00))) begin + +/************************************* Collision starts *****************************************/ + + if (SIM_COLLISION_CHECK != "NONE") begin + + if (gsr_in === 1'b0) begin + + if (time_port_a > time_port_b) begin + + if (time_port_a - time_port_b <= 100) begin + viol_time = 1; + end + else if (time_port_a - time_port_b <= SETUP_READ_FIRST) begin + viol_time = 2; + end + end + else begin + + if (time_port_b - time_port_a <= 100) begin + viol_time = 1; + end + else if (time_port_b - time_port_a <= SETUP_READ_FIRST) begin + viol_time = 2; + end + + end // else: !if(time_port_a > time_port_b) + + + if (ena_in === 1'b0 || enb_in === 1'b0) + viol_time = 0; + + + if ((WRITE_WIDTH_A <= 9 && wea_in[0] === 1'b0) || (WRITE_WIDTH_A == 18 && wea_in[1:0] === 2'b00) || ((WRITE_WIDTH_A == 36 || WRITE_WIDTH_A == 72) && wea_in[3:0] === 4'b0000)) + if ((WRITE_WIDTH_B <= 9 && web_in[0] === 1'b0) || (WRITE_WIDTH_B == 18 && web_in[1:0] === 2'b00) || (WRITE_WIDTH_B == 36 && web_in[3:0] === 4'b0000) || (WRITE_WIDTH_B == 72 && web_in[7:0] === 8'h00)) + viol_time = 0; + + + if (viol_time != 0) begin + + // Clka and clkb rise at the same time + if ((rising_clka && rising_clkb) || viol_time == 1) begin + if (col_addra_reconstruct[15:col_addr_lsb] === col_addrb_reconstruct[15:col_addr_lsb]) begin + + viol_type = 2'b01; + + task_rd_ram_a (addra_in, doa_buf, dopa_buf); + task_rd_ram_b (addrb_in, dob_buf, dopb_buf); + + task_col_wr_ram_a (2'b00, web_in, wea_in, di_x, di_x[7:0], addrb_in, addra_in); + task_col_wr_ram_b (2'b00, wea_in, web_in, di_x, di_x[7:0], addra_in, addrb_in); + + task_col_rd_ram_a (2'b01, web_in, wea_in, addra_in, doa_buf, dopa_buf); + task_col_rd_ram_b (2'b01, wea_in, web_in, addrb_in, dob_buf, dopb_buf); + + task_col_wr_ram_a (2'b10, web_in, wea_in, dia_in, dipa_in, addrb_in, addra_in); + + + // injecting error + dib_ecc_col = dib_in; + + + if (injectdbiterr_in === 1) begin + dib_ecc_col[30] = ~dib_ecc_col[30]; + dib_ecc_col[62] = ~dib_ecc_col[62]; + end + else if (injectsbiterr_in === 1) begin + dib_ecc_col[30] = ~dib_ecc_col[30]; + end + + + if (ram_mode_int == 0 && en_ecc_write_int == 1 && enb_in === 1'b1) begin + + dip_ecc_col = fn_dip_ecc(1'b1, dib_in, dipb_in); + eccparity_out = dip_ecc_col; + task_col_wr_ram_b (2'b10, wea_in, web_in, dib_ecc_col, dip_ecc_col, addra_in, addrb_in); + + end + else + task_col_wr_ram_b (2'b10, wea_in, web_in, dib_ecc_col, dipb_in, addra_in, addrb_in); + + + if (wr_mode_a != 2'b01) + task_col_rd_ram_a (2'b11, web_in, wea_in, addra_in, doa_buf, dopa_buf); + if (wr_mode_b != 2'b01) + task_col_rd_ram_b (2'b11, wea_in, web_in, addrb_in, dob_buf, dopb_buf); + + + if (rdaddr_collision_hwconfig_int == 1 && (wr_mode_a == 2'b01 || wr_mode_b == 2'b01)) begin + task_col_wr_ram_a (2'b10, web_in, wea_in, di_x, di_x[7:0], addrb_in, addra_in); + task_col_wr_ram_b (2'b10, wea_in, web_in, di_x, di_x[7:0], addra_in, addrb_in); + end + + + if (ram_mode_int == 0 && en_ecc_read_int == 1) + task_col_ecc_read (doa_buf, dopa_buf, addra_in); + + + end // if (addra_in[15:col_addr_lsb] === addrb_in[15:col_addr_lsb]) + else + viol_time = 0; + + end // if (rising_clka && rising_clkb) + // Clkb before clka + else if (rising_clka && !rising_clkb) begin + if (col_addra_reconstruct[15:col_addr_lsb] === col_addrb_reconstruct_reg[15:col_addr_lsb]) begin + + viol_type = 2'b10; + + task_rd_ram_a (addra_in, doa_buf, dopa_buf); + + task_col_wr_ram_a (2'b00, web_reg, wea_in, di_x, di_x[7:0], addrb_reg, addra_in); + task_col_wr_ram_b (2'b00, wea_in, web_reg, di_x, di_x[7:0], addra_in, addrb_reg); + + task_col_rd_ram_a (2'b01, web_reg, wea_in, addra_in, doa_buf, dopa_buf); + task_col_rd_ram_b (2'b01, wea_in, web_reg, addrb_reg, dob_buf, dopb_buf); + + task_col_wr_ram_a (2'b10, web_reg, wea_in, dia_in, dipa_in, addrb_reg, addra_in); + + + // injecting error + dib_ecc_col = dib_reg; + + + if (injectdbiterr_in === 1) begin + dib_ecc_col[30] = ~dib_ecc_col[30]; + dib_ecc_col[62] = ~dib_ecc_col[62]; + end + else if (injectsbiterr_in === 1) begin + dib_ecc_col[30] = ~dib_ecc_col[30]; + end + + + if (ram_mode_int == 0 && en_ecc_write_int == 1 && enb_reg === 1'b1) begin + + dip_ecc_col = fn_dip_ecc(1'b1, dib_reg, dipb_reg); + eccparity_out = dip_ecc_col; + task_col_wr_ram_b (2'b10, wea_in, web_reg, dib_ecc_col, dip_ecc_col, addra_in, addrb_reg); + + end + else + task_col_wr_ram_b (2'b10, wea_in, web_reg, dib_ecc_col, dipb_reg, addra_in, addrb_reg); + + + if (wr_mode_a != 2'b01) + task_col_rd_ram_a (2'b11, web_reg, wea_in, addra_in, doa_buf, dopa_buf); + if (wr_mode_b != 2'b01) + task_col_rd_ram_b (2'b11, wea_in, web_reg, addrb_reg, dob_buf, dopb_buf); + + + if (wr_mode_a == 2'b01 || wr_mode_b == 2'b01) begin + task_col_wr_ram_a (2'b10, web_reg, wea_in, di_x, di_x[7:0], addrb_reg, addra_in); + task_col_wr_ram_b (2'b10, wea_in, web_reg, di_x, di_x[7:0], addra_in, addrb_reg); + end + + + if (ram_mode_int == 0 && en_ecc_read_int == 1) + task_col_ecc_read (doa_buf, dopa_buf, addra_in); + + + end // if (addra_in[15:col_addr_lsb] === addrb_reg[15:col_addr_lsb]) + else + viol_time = 0; + + end // if (rising_clka && !rising_clkb) + // Clka before clkb + else if (!rising_clka && rising_clkb) begin + if (col_addra_reconstruct_reg[15:col_addr_lsb] === col_addrb_reconstruct[15:col_addr_lsb]) begin + + viol_type = 2'b11; + + task_rd_ram_b (addrb_in, dob_buf, dopb_buf); + + task_col_wr_ram_a (2'b00, web_in, wea_reg, di_x, di_x[7:0], addrb_in, addra_reg); + task_col_wr_ram_b (2'b00, wea_reg, web_in, di_x, di_x[7:0], addra_reg, addrb_in); + + task_col_rd_ram_a (2'b01, web_in, wea_reg, addra_reg, doa_buf, dopa_buf); + task_col_rd_ram_b (2'b01, wea_reg, web_in, addrb_in, dob_buf, dopb_buf); + + task_col_wr_ram_a (2'b10, web_in, wea_reg, dia_reg, dipa_reg, addrb_in, addra_reg); + + + // injecting error + dib_ecc_col = dib_in; + + + if (injectdbiterr_in === 1) begin + dib_ecc_col[30] = ~dib_ecc_col[30]; + dib_ecc_col[62] = ~dib_ecc_col[62]; + end + else if (injectsbiterr_in === 1) begin + dib_ecc_col[30] = ~dib_ecc_col[30]; + end + + + if (ram_mode_int == 0 && en_ecc_write_int == 1 && enb_in === 1'b1) begin + + dip_ecc_col = fn_dip_ecc(1'b1, dib_in, dipb_in); + eccparity_out = dip_ecc_col; + task_col_wr_ram_b (2'b10, wea_reg, web_in, dib_ecc_col, dip_ecc_col, addra_reg, addrb_in); + + end + else + task_col_wr_ram_b (2'b10, wea_reg, web_in, dib_ecc_col, dipb_in, addra_reg, addrb_in); + + + if (wr_mode_a != 2'b01) + task_col_rd_ram_a (2'b11, web_in, wea_reg, addra_reg, doa_buf, dopa_buf); + if (wr_mode_b != 2'b01) + task_col_rd_ram_b (2'b11, wea_reg, web_in, addrb_in, dob_buf, dopb_buf); + + + if (wr_mode_a == 2'b01 || wr_mode_b == 2'b01) begin + task_col_wr_ram_a (2'b10, web_in, wea_reg, di_x, di_x[7:0], addrb_in, addra_reg); + task_col_wr_ram_b (2'b10, wea_reg, web_in, di_x, di_x[7:0], addra_reg, addrb_in); + end + + + if (ram_mode_int == 0 && en_ecc_read_int == 1) + task_col_ecc_read (doa_buf, dopa_buf, addra_reg); + + + end // if (addra_reg[15:col_addr_lsb] === addrb_in[15:col_addr_lsb]) + else + viol_time = 0; + + end + + end // if (viol_time != 0) + end // if (gsr_in === 1'b0) + + if (SIM_COLLISION_CHECK == "WARNING_ONLY") + viol_time = 0; + + end // if (SIM_COLLISION_CHECK != "NONE") + + +/*************************************** end collision ********************************/ + + end // if ((cascade_a == 2'b00 || (addra_in_15_reg_bram == 1'b0 && cascade_a != 2'b00)) && (cascade_b == 2'b00 || (addrb_in_15_reg_bram == 1'b0 && cascade_b != 2'b00))) + + +/**************************** Port A ****************************************/ + if (rising_clka) begin + + // DRC + if (rstrama_in === 1 && ram_mode_int == 0 && (en_ecc_write_int == 1 || en_ecc_read_int == 1)) + $display("DRC Warning : SET/RESET (RSTRAM) is not supported in ECC mode on RB36_INTERNAL_VLOG instance %m."); + + // end DRC + + + // registering addra_in[15] the second time + if (regcea_in) + addra_in_15_reg1 = addra_in_15_reg; + + + if (ena_in && (wr_mode_a != 2'b10 || wea_in[0] == 0 || rstrama_in == 1'b1)) + if (cascade_a[1]) + addra_in_15_reg = ~addra_in[15]; + else + addra_in_15_reg = addra_in[15]; + + + if (gsr_in == 1'b0 && ena_in == 1'b1 && (cascade_a == 2'b00 || (addra_in_15_reg_bram == 1'b0 && cascade_a != 2'b00))) begin + + // SRVAL + if (rstrama_in === 1'b1) begin + + doa_buf = SRVAL_A[0 +: ra_width]; + doa_out = SRVAL_A[0 +: ra_width]; + + if (ra_width >= 8) begin + dopa_buf = SRVAL_A[ra_width +: ra_widthp]; + dopa_out = SRVAL_A[ra_width +: ra_widthp]; + end + end + + + if (viol_time == 0) begin + + // Read first + if (wr_mode_a == 2'b01 || (ram_mode_int == 0 && en_ecc_read_int == 1)) begin + task_rd_ram_a (addra_in, doa_buf, dopa_buf); + + + // ECC decode + if (ram_mode_int == 0 && en_ecc_read_int == 1) begin + + dopr_ecc = fn_dip_ecc(1'b0, doa_buf, dopa_buf); + + syndrome = dopr_ecc ^ dopa_buf; + + if (syndrome !== 0) begin + + if (syndrome[7]) begin // dectect single bit error + + ecc_bit_position = {doa_buf[63:57], dopa_buf[6], doa_buf[56:26], dopa_buf[5], doa_buf[25:11], dopa_buf[4], doa_buf[10:4], dopa_buf[3], doa_buf[3:1], dopa_buf[2], doa_buf[0], dopa_buf[1:0], dopa_buf[7]}; + + if (syndrome[6:0] > 71) begin + $display ("DRC Error : Simulation halted due Corrupted DIP. To correct this problem, make sure that reliable data is fed to the DIP. The correct Parity must be generated by a Hamming code encoder or encoder in the Block RAM. The output from the model is unreliable if there are more than 2 bit errors. The model doesn't warn if there is sporadic input of more than 2 bit errors due to the limitation in Hamming code."); + $finish; + end + + ecc_bit_position[syndrome[6:0]] = ~ecc_bit_position[syndrome[6:0]]; // correct single bit error in the output + + dia_in_ecc_corrected = {ecc_bit_position[71:65], ecc_bit_position[63:33], ecc_bit_position[31:17], ecc_bit_position[15:9], ecc_bit_position[7:5], ecc_bit_position[3]}; // correct single bit error in the memory + + doa_buf = dia_in_ecc_corrected; + + dipa_in_ecc_corrected = {ecc_bit_position[0], ecc_bit_position[64], ecc_bit_position[32], ecc_bit_position[16], ecc_bit_position[8], ecc_bit_position[4], ecc_bit_position[2:1]}; // correct single bit error in the parity memory + + dopa_buf = dipa_in_ecc_corrected; + + dbiterr_out <= 0; + sbiterr_out <= 1; + + end + else if (!syndrome[7]) begin // double bit error + sbiterr_out <= 0; + dbiterr_out <= 1; + + end + end // if (syndrome !== 0) + else begin + dbiterr_out <= 0; + sbiterr_out <= 0; + + end // else: !if(syndrome !== 0) + + + // output of rdaddrecc + rdaddrecc_out[8:0] <= addra_in[14:6]; + + end // if (ram_mode_int == 0 && en_ecc_read_int == 1) + end // if (wr_mode_a == 2'b01) + + + // Write + task_wr_ram_a (wea_in, dia_in, dipa_in, addra_in); + + // Read if not read first + if (wr_mode_a != 2'b01 && !(ram_mode_int == 0 && en_ecc_read_int == 1)) + task_rd_ram_a (addra_in, doa_buf, dopa_buf); + + end // if (viol_time == 0) + + end // if (gsr_in == 1'b0 && ena_in == 1'b1 && (cascade_a == 2'b00 || (addra_in_15_reg_bram == 1'b0 && cascade_a != 2'b00))) + + end // if (rising_clka) + // end of port A + + +/************************************** port B ***************************************************************/ + if (rising_clkb) begin + + // DRC + if (rstramb_in === 1 && ram_mode_int == 0 && (en_ecc_write_int == 1 || en_ecc_read_int == 1)) + $display("DRC Warning : SET/RESET (RSTRAM) is not supported in ECC mode on RB36_INTERNAL_VLOG instance %m."); + + if (!(en_ecc_write_int == 1 || en_ecc_read_int == 1)) begin + + if (injectsbiterr_in === 1) + $display("DRC Warning : INJECTSBITERR is not supported when neither EN_ECC_WRITE nor EN_ECC_READ = TRUE on RB36_INTERNAL_VLOG instance %m."); + + if (injectdbiterr_in === 1) + $display("DRC Warning : INJECTDBITERR is not supported when neither EN_ECC_WRITE nor EN_ECC_READ = TRUE on RB36_INTERNAL_VLOG instance %m."); + + end + // End DRC + + + if (regceb_in) + addrb_in_15_reg1 = addrb_in_15_reg; + + + if (enb_in && (wr_mode_b != 2'b10 || web_in[0] == 0 || rstramb_in == 1'b1)) + if (cascade_b[1]) + addrb_in_15_reg = ~addrb_in[15]; + else + addrb_in_15_reg = addrb_in[15]; + + + if (gsr_in == 1'b0 && enb_in == 1'b1 && (cascade_b == 2'b00 || (addrb_in_15_reg_bram == 1'b0 && cascade_b != 2'b00))) begin + + // SRVAL + if (rstramb_in === 1'b1) begin + + dob_buf = SRVAL_B[0 +: rb_width]; + dob_out = SRVAL_B[0 +: rb_width]; + + if (rb_width >= 8) begin + dopb_buf = SRVAL_B[rb_width +: rb_widthp]; + dopb_out = SRVAL_B[rb_width +: rb_widthp]; + end + end + + + if (viol_time == 0) begin + + // ECC encode + if (ram_mode_int == 0 && en_ecc_write_int == 1) begin + dip_ecc = fn_dip_ecc(1'b1, dib_in, dipb_in); + eccparity_out = dip_ecc; + dipb_in_ecc = dip_ecc; + end + else + dipb_in_ecc = dipb_in; + + + dib_in_ecc = dib_in; + + + // injecting error + if (injectdbiterr_in === 1) begin // double bit + dib_in_ecc[30] = ~dib_in_ecc[30]; + dib_in_ecc[62] = ~dib_in_ecc[62]; + end + else if (injectsbiterr_in === 1) begin // single bit + dib_in_ecc[30] = ~dib_in_ecc[30]; + end + + + // Read first + if (wr_mode_b == 2'b01 && rstramb_in === 1'b0) + task_rd_ram_b (addrb_in, dob_buf, dopb_buf); + + + // Write + task_wr_ram_b (web_in, dib_in_ecc, dipb_in_ecc, addrb_in); + + + // Read if not read first + if (wr_mode_b != 2'b01 && rstramb_in === 1'b0) + task_rd_ram_b (addrb_in, dob_buf, dopb_buf); + + end // if (viol_time == 0) + + + end // if (gsr_in == 1'b0 && enb_in == 1'b1 && (cascade_b == 2'b00 || addrb_in_15_reg_bram == 1'b0)) + + end // if (rising_clkb) + // end of port B + + + if (gsr_in == 1'b0) begin + + // writing outputs of port A + if (ena_in && (rising_clka || viol_time != 0)) begin + + if (rstrama_in === 1'b0 && (wr_mode_a != 2'b10 || (WRITE_WIDTH_A <= 9 && wea_in[0] === 1'b0) || (WRITE_WIDTH_A == 18 && wea_in[1:0] === 2'b00) || ((WRITE_WIDTH_A == 36 || WRITE_WIDTH_A == 72) && wea_in[3:0] === 4'b0000))) begin + + doa_out <= doa_buf; + + if (ra_width >= 8) + dopa_out <= dopa_buf; + + end + + end + + + // writing outputs of port B + if (enb_in && (rising_clkb || viol_time != 0)) begin + + if (rstramb_in === 1'b0 && (wr_mode_b != 2'b10 || (WRITE_WIDTH_B <= 9 && web_in[0] === 1'b0) || (WRITE_WIDTH_B == 18 && web_in[1:0] === 2'b00) || (WRITE_WIDTH_B == 36 && web_in[3:0] === 4'b0000) || (WRITE_WIDTH_B == 72 && web_in[7:0] === 8'h00))) begin + + dob_out <= dob_buf; + + if (rb_width >= 8) + dopb_out <= dopb_buf; + + end + + end + + end // if (gsr_in == 1'b0) + + + viol_time = 0; + rising_clka = 0; + rising_clkb = 0; + viol_type = 2'b00; + col_wr_wr_msg = 1; + col_wra_rdb_msg = 1; + col_wrb_rda_msg = 1; + + end // always @ (posedge rising_clka or posedge rising_clkb) + + + // ********* Cascade Port A ******** + always @(posedge clka_in or cascadeina_in or addra_in_15_reg or doa_out or dopa_out) begin + + if (cascade_a[1] == 1'b1 && addra_in_15_reg == 1'b1) begin + doa_out_mux[0] = cascadeina_in; + end + else begin + doa_out_mux = doa_out; + + if (ra_width >= 8) + dopa_out_mux = dopa_out; + + end + + end + + // output register mode + always @(posedge clka_in or cascadeina_in or addra_in_15_reg1 or doa_outreg or dopa_outreg) begin + + if (cascade_a[1] == 1'b1 && addra_in_15_reg1 == 1'b1) begin + doa_outreg_mux[0] = cascadeina_in; + end + else begin + doa_outreg_mux = doa_outreg; + + if (ra_width >= 8) + dopa_outreg_mux = dopa_outreg; + + end + + end + + + // ********* Cascade Port B ******** + always @(posedge clkb_in or cascadeinb_in or addrb_in_15_reg or dob_out or dopb_out) begin + + if (cascade_b[1] == 1'b1 && addrb_in_15_reg == 1'b1) begin + dob_out_mux[0] = cascadeinb_in; + end + else begin + dob_out_mux = dob_out; + + if (rb_width >= 8) + dopb_out_mux = dopb_out; + + end + + end + + // output register mode + always @(posedge clkb_in or cascadeinb_in or addrb_in_15_reg1 or dob_outreg or dopb_outreg) begin + + if (cascade_b[1] == 1'b1 && addrb_in_15_reg1 == 1'b1) begin + dob_outreg_mux[0] = cascadeinb_in; + end + else begin + dob_outreg_mux = dob_outreg; + + if (rb_width >= 8) + dopb_outreg_mux = dopb_outreg; + + end + + end // always @ (posedge regclkb_in or cascadeinregb_in or addrb_in_15_reg1 or dob_outreg or dopb_outreg) + + + // ***** Output Registers **** Port A ***** + always @(posedge clka_in or posedge gsr_in) begin + + if (DOA_REG == 1) begin + + if (gsr_in == 1'b1) begin + + rdaddrecc_outreg <= 9'b0; + dbiterr_outreg <= 0; + sbiterr_outreg <= 0; + doa_outreg <= INIT_A[0 +: ra_width]; + + if (ra_width >= 8) + dopa_outreg <= INIT_A[ra_width +: ra_widthp]; + + end + else if (gsr_in == 1'b0) begin + + if (regcea_in === 1'b1) begin + dbiterr_outreg <= dbiterr_out; + sbiterr_outreg <= sbiterr_out; + rdaddrecc_outreg <= rdaddrecc_out; + end + + + if (rstreg_priority_a_int == 0) begin // Virtex5 behavior + + if (regcea_in == 1'b1) begin + if (rstrega_in == 1'b1) begin + + doa_outreg <= SRVAL_A[0 +: ra_width]; + + if (ra_width >= 8) + dopa_outreg <= SRVAL_A[ra_width +: ra_widthp]; + + end + else if (rstrega_in == 1'b0) begin + + doa_outreg <= doa_out; + + if (ra_width >= 8) + dopa_outreg <= dopa_out; + + end + end // if (regcea_in == 1'b1) + + end // if (rstreg_priority_a_int == 1'b0) + else begin + + if (rstrega_in == 1'b1) begin + + doa_outreg <= SRVAL_A[0 +: ra_width]; + + if (ra_width >= 8) + dopa_outreg <= SRVAL_A[ra_width +: ra_widthp]; + + end + + else if (rstrega_in == 1'b0) begin + + if (regcea_in == 1'b1) begin + + doa_outreg <= doa_out; + + if (ra_width >= 8) + dopa_outreg <= dopa_out; + + end + end + end // else: !if(rstreg_priority_a_int == 1'b0) + + end // if (gsr_in == 1'b0) + + end // if (DOA_REG == 1) + + end // always @ (posedge clka_in or posedge gsr_in) + + + always @(temp_wire or doa_out_mux or dopa_out_mux or doa_outreg_mux or dopa_outreg_mux or dbiterr_out or dbiterr_outreg or sbiterr_out or sbiterr_outreg or rdaddrecc_out or rdaddrecc_outreg) begin + + case (DOA_REG) + + 0 : begin + dbiterr_out_out = dbiterr_out; + sbiterr_out_out = sbiterr_out; + rdaddrecc_out_out = rdaddrecc_out; + doa_out_out[0 +: ra_width] = doa_out_mux[0 +: ra_width]; + + if (ra_width >= 8) + dopa_out_out[0 +: ra_widthp] = dopa_out_mux[0 +: ra_widthp]; + + end + 1 : begin + dbiterr_out_out = dbiterr_outreg; + sbiterr_out_out = sbiterr_outreg; + doa_out_out[0 +: ra_width] = doa_outreg_mux[0 +: ra_width]; + rdaddrecc_out_out = rdaddrecc_outreg; + + if (ra_width >= 8) + dopa_out_out[0 +: ra_widthp] = dopa_outreg_mux[0 +: ra_widthp]; + + end + default : begin + $display("Attribute Syntax Error : The attribute DOA_REG on RB36_INTERNAL_VLOG instance %m is set to %2d. Legal values for this attribute are 0 or 1.", DOA_REG); + $finish; + end + + endcase + + end // always @ (doa_out_mux or dopa_out_mux or doa_outreg_mux or dopa_outreg_mux or dbiterr_out or dbiterr_outreg or sbiterr_out or sbiterr_outreg) + + +// ***** Output Registers **** Port B ***** + always @(posedge clkb_in or posedge gsr_in) begin + + if (DOB_REG == 1) begin + + if (gsr_in == 1'b1) begin + + dob_outreg <= INIT_B[0 +: rb_width]; + + if (rb_width >= 8) + dopb_outreg <= INIT_B[rb_width +: rb_widthp]; + + end + else if (gsr_in == 1'b0) begin + + if (rstreg_priority_b_int == 0) begin // Virtex5 behavior + + if (regceb_in == 1'b1) begin + if (rstregb_in == 1'b1) begin + + dob_outreg <= SRVAL_B[0 +: rb_width]; + + if (rb_width >= 8) + dopb_outreg <= SRVAL_B[rb_width +: rb_widthp]; + + end + else if (rstregb_in == 1'b0) begin + + dob_outreg <= dob_out; + + if (rb_width >= 8) + dopb_outreg <= dopb_out; + + end + end // if (regceb_in == 1'b1) + + end // if (rstreg_priority_b_int == 1'b0) + else begin + + if (rstregb_in == 1'b1) begin + + dob_outreg <= SRVAL_B[0 +: rb_width]; + + if (rb_width >= 8) + dopb_outreg <= SRVAL_B[rb_width +: rb_widthp]; + + end + + else if (rstregb_in == 1'b0) begin + + if (regceb_in == 1'b1) begin + + dob_outreg <= dob_out; + + if (rb_width >= 8) + dopb_outreg <= dopb_out; + + end + end + end // else: !if(rstreg_priority_b_int == 1'b0) + + end // if (gsr_in == 1'b0) + + end // if (DOB_REG == 1) + + end // always @ (posedge clkb_in or posedge gsr_in) + + + always @(temp_wire or dob_out_mux or dopb_out_mux or dob_outreg_mux or dopb_outreg_mux) begin + + case (DOB_REG) + + 0 : begin + dob_out_out[0 +: rb_width] = dob_out_mux[0 +: rb_width]; + + if (rb_width >= 8) + dopb_out_out[0 +: rb_widthp] = dopb_out_mux[0 +: rb_widthp]; + end + 1 : begin + dob_out_out[0 +: rb_width] = dob_outreg_mux[0 +: rb_width]; + + if (rb_width >= 8) + dopb_out_out[0 +: rb_widthp] = dopb_outreg_mux[0 +: rb_widthp]; + + end + default : begin + $display("Attribute Syntax Error : The attribute DOB_REG on RB36_INTERNAL_VLOG instance %m is set to %2d. Legal values for this attribute are 0 or 1.", DOB_REG); + $finish; + end + + endcase + + end // always @ (dob_out_mux or dopb_out_mux or dob_outreg_mux or dopb_outreg_mux) + + +endmodule // RB36_INTERNAL_VLOG + +// end of RB36_INTERNAL_VLOG - Note: Not an user primitive diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/RAMB36SDP.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/RAMB36SDP.v new file mode 100644 index 0000000..75ef0a2 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/RAMB36SDP.v @@ -0,0 +1,475 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/rainier/RAMB36SDP.v,v 1.16 2007/06/15 20:58:40 wloo Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2005 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / 32K-Bit Data and 4K-Bit Parity Block RAM +// /___/ /\ Filename : RAMB36SDP.v +// \ \ / \ Timestamp : Tues July 26 16:43:59 PST 2005 +// \___\/\___\ +// +// Revision: +// 07/26/05 - Initial version. +// 01/04/07 - Added support of memory file to initialize memory and parity (CR 431584). +// 03/14/07 - Removed attribute INITP_FILE (CR 436003). +// 04/03/07 - Changed INIT_FILE = "NONE" as default (CR 436812). +// 06/13/07 - Added high performace version of the model. +// End Revision + +`timescale 1 ps/1 ps + +module RAMB36SDP (DBITERR, DO, DOP, ECCPARITY, SBITERR, + DI, DIP, RDADDR, RDCLK, RDEN, REGCE, SSR, WE, WRADDR, WRCLK, WREN); + + parameter integer DO_REG = 0; + parameter EN_ECC_READ = "FALSE"; + parameter EN_ECC_SCRUB = "FALSE"; + parameter EN_ECC_WRITE = "FALSE"; + parameter INIT = 72'h0; + parameter INITP_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_40 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_41 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_42 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_43 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_44 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_45 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_46 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_47 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_48 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_49 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_4A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_4B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_4C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_4D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_4E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_4F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_50 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_51 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_52 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_53 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_54 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_55 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_56 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_57 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_58 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_59 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_5A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_5B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_5C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_5D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_5E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_5F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_60 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_61 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_62 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_63 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_64 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_65 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_66 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_67 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_68 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_69 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_6A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_6B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_6C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_6D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_6E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_6F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_70 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_71 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_72 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_73 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_74 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_75 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_76 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_77 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_78 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_79 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_7A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_7B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_7C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_7D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_7E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_7F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_FILE = "NONE"; + parameter SIM_COLLISION_CHECK = "ALL"; + parameter SIM_MODE = "SAFE"; + parameter SRVAL = 72'h0; + + localparam SETUP_ALL = 1000; + localparam SETUP_READ_FIRST = 3000; + + output DBITERR; + output SBITERR; + output [63:0] DO; + output [7:0] DOP; + output [7:0] ECCPARITY; + + input RDCLK; + input RDEN; + input REGCE; + input SSR; + input WRCLK; + input WREN; + input [8:0] WRADDR; + input [8:0] RDADDR; + input [63:0] DI; + input [7:0] DIP; + input [7:0] WE; + + tri0 GSR = glbl.GSR; + + wire [7:0] dangle_out8; + wire dangle_out; + wire [3:0] dangle_out4; + wire [31:0] dangle_out32; + + localparam BRAM_MODE = (EN_ECC_WRITE == "TRUE" || EN_ECC_READ == "TRUE") ? "ECC" : "SIMPLE_DUAL_PORT"; + + ARAMB36_INTERNAL INT_RAMB (.DIA(64'b0), .ENA(RDEN), .WEA(8'b0), .SSRA(SSR), .ADDRA({1'b0, RDADDR, 6'b0}), .CLKA(RDCLK), .DOA(DO), .DIB(DI), .ENB(WREN), .WEB(WE), .SSRB(1'b0), .ADDRB({1'b0, WRADDR, 6'b0}), .CLKB(WRCLK), .DOB(dangle_out32), .GSR(GSR), .DOPA(DOP), .DOPB(dangle_out4), .DIPA(4'b0), .DIPB(DIP), .CASCADEOUTLATA(dangle_out), .CASCADEOUTLATB(dangle_out), .CASCADEOUTREGA(dangle_out), .CASCADEOUTREGB(dangle_out), .CASCADEINLATA(1'b0), .CASCADEINLATB(1'b0), .CASCADEINREGA(1'b0), .CASCADEINREGB(1'b0), .REGCEA(REGCE), .REGCEB(1'b0), .REGCLKA(RDCLK), .REGCLKB(1'b0), .DBITERR(DBITERR), .ECCPARITY(ECCPARITY), .SBITERR(SBITERR)); + + defparam INT_RAMB.SIM_MODE = SIM_MODE; + defparam INT_RAMB.BRAM_MODE = BRAM_MODE; + defparam INT_RAMB.INIT_A = INIT; + defparam INT_RAMB.INIT_B = INIT; + defparam INT_RAMB.INIT_FILE = INIT_FILE; + defparam INT_RAMB.SRVAL_A = SRVAL; + defparam INT_RAMB.SRVAL_B = SRVAL; + defparam INT_RAMB.READ_WIDTH_A = 72; + defparam INT_RAMB.READ_WIDTH_B = 72; + defparam INT_RAMB.WRITE_WIDTH_A = 72; + defparam INT_RAMB.WRITE_WIDTH_B = 72; + defparam INT_RAMB.WRITE_MODE_A = "READ_FIRST"; + defparam INT_RAMB.WRITE_MODE_B = "READ_FIRST"; + defparam INT_RAMB.RAM_EXTENSION_A = "NONE"; + defparam INT_RAMB.RAM_EXTENSION_B = "NONE"; + defparam INT_RAMB.SETUP_ALL = SETUP_ALL; + defparam INT_RAMB.SETUP_READ_FIRST = SETUP_READ_FIRST; + defparam INT_RAMB.SIM_COLLISION_CHECK = SIM_COLLISION_CHECK; + defparam INT_RAMB.EN_ECC_READ = EN_ECC_READ; + defparam INT_RAMB.EN_ECC_SCRUB = EN_ECC_SCRUB; + defparam INT_RAMB.EN_ECC_WRITE = EN_ECC_WRITE; + defparam INT_RAMB.DOA_REG = DO_REG; + defparam INT_RAMB.DOB_REG = DO_REG; + defparam INT_RAMB.INIT_00 = INIT_00; + defparam INT_RAMB.INIT_01 = INIT_01; + defparam INT_RAMB.INIT_02 = INIT_02; + defparam INT_RAMB.INIT_03 = INIT_03; + defparam INT_RAMB.INIT_04 = INIT_04; + defparam INT_RAMB.INIT_05 = INIT_05; + defparam INT_RAMB.INIT_06 = INIT_06; + defparam INT_RAMB.INIT_07 = INIT_07; + defparam INT_RAMB.INIT_08 = INIT_08; + defparam INT_RAMB.INIT_09 = INIT_09; + defparam INT_RAMB.INIT_0A = INIT_0A; + defparam INT_RAMB.INIT_0B = INIT_0B; + defparam INT_RAMB.INIT_0C = INIT_0C; + defparam INT_RAMB.INIT_0D = INIT_0D; + defparam INT_RAMB.INIT_0E = INIT_0E; + defparam INT_RAMB.INIT_0F = INIT_0F; + defparam INT_RAMB.INIT_10 = INIT_10; + defparam INT_RAMB.INIT_11 = INIT_11; + defparam INT_RAMB.INIT_12 = INIT_12; + defparam INT_RAMB.INIT_13 = INIT_13; + defparam INT_RAMB.INIT_14 = INIT_14; + defparam INT_RAMB.INIT_15 = INIT_15; + defparam INT_RAMB.INIT_16 = INIT_16; + defparam INT_RAMB.INIT_17 = INIT_17; + defparam INT_RAMB.INIT_18 = INIT_18; + defparam INT_RAMB.INIT_19 = INIT_19; + defparam INT_RAMB.INIT_1A = INIT_1A; + defparam INT_RAMB.INIT_1B = INIT_1B; + defparam INT_RAMB.INIT_1C = INIT_1C; + defparam INT_RAMB.INIT_1D = INIT_1D; + defparam INT_RAMB.INIT_1E = INIT_1E; + defparam INT_RAMB.INIT_1F = INIT_1F; + defparam INT_RAMB.INIT_20 = INIT_20; + defparam INT_RAMB.INIT_21 = INIT_21; + defparam INT_RAMB.INIT_22 = INIT_22; + defparam INT_RAMB.INIT_23 = INIT_23; + defparam INT_RAMB.INIT_24 = INIT_24; + defparam INT_RAMB.INIT_25 = INIT_25; + defparam INT_RAMB.INIT_26 = INIT_26; + defparam INT_RAMB.INIT_27 = INIT_27; + defparam INT_RAMB.INIT_28 = INIT_28; + defparam INT_RAMB.INIT_29 = INIT_29; + defparam INT_RAMB.INIT_2A = INIT_2A; + defparam INT_RAMB.INIT_2B = INIT_2B; + defparam INT_RAMB.INIT_2C = INIT_2C; + defparam INT_RAMB.INIT_2D = INIT_2D; + defparam INT_RAMB.INIT_2E = INIT_2E; + defparam INT_RAMB.INIT_2F = INIT_2F; + defparam INT_RAMB.INIT_30 = INIT_30; + defparam INT_RAMB.INIT_31 = INIT_31; + defparam INT_RAMB.INIT_32 = INIT_32; + defparam INT_RAMB.INIT_33 = INIT_33; + defparam INT_RAMB.INIT_34 = INIT_34; + defparam INT_RAMB.INIT_35 = INIT_35; + defparam INT_RAMB.INIT_36 = INIT_36; + defparam INT_RAMB.INIT_37 = INIT_37; + defparam INT_RAMB.INIT_38 = INIT_38; + defparam INT_RAMB.INIT_39 = INIT_39; + defparam INT_RAMB.INIT_3A = INIT_3A; + defparam INT_RAMB.INIT_3B = INIT_3B; + defparam INT_RAMB.INIT_3C = INIT_3C; + defparam INT_RAMB.INIT_3D = INIT_3D; + defparam INT_RAMB.INIT_3E = INIT_3E; + defparam INT_RAMB.INIT_3F = INIT_3F; + defparam INT_RAMB.INIT_40 = INIT_40; + defparam INT_RAMB.INIT_41 = INIT_41; + defparam INT_RAMB.INIT_42 = INIT_42; + defparam INT_RAMB.INIT_43 = INIT_43; + defparam INT_RAMB.INIT_44 = INIT_44; + defparam INT_RAMB.INIT_45 = INIT_45; + defparam INT_RAMB.INIT_46 = INIT_46; + defparam INT_RAMB.INIT_47 = INIT_47; + defparam INT_RAMB.INIT_48 = INIT_48; + defparam INT_RAMB.INIT_49 = INIT_49; + defparam INT_RAMB.INIT_4A = INIT_4A; + defparam INT_RAMB.INIT_4B = INIT_4B; + defparam INT_RAMB.INIT_4C = INIT_4C; + defparam INT_RAMB.INIT_4D = INIT_4D; + defparam INT_RAMB.INIT_4E = INIT_4E; + defparam INT_RAMB.INIT_4F = INIT_4F; + defparam INT_RAMB.INIT_50 = INIT_50; + defparam INT_RAMB.INIT_51 = INIT_51; + defparam INT_RAMB.INIT_52 = INIT_52; + defparam INT_RAMB.INIT_53 = INIT_53; + defparam INT_RAMB.INIT_54 = INIT_54; + defparam INT_RAMB.INIT_55 = INIT_55; + defparam INT_RAMB.INIT_56 = INIT_56; + defparam INT_RAMB.INIT_57 = INIT_57; + defparam INT_RAMB.INIT_58 = INIT_58; + defparam INT_RAMB.INIT_59 = INIT_59; + defparam INT_RAMB.INIT_5A = INIT_5A; + defparam INT_RAMB.INIT_5B = INIT_5B; + defparam INT_RAMB.INIT_5C = INIT_5C; + defparam INT_RAMB.INIT_5D = INIT_5D; + defparam INT_RAMB.INIT_5E = INIT_5E; + defparam INT_RAMB.INIT_5F = INIT_5F; + defparam INT_RAMB.INIT_60 = INIT_60; + defparam INT_RAMB.INIT_61 = INIT_61; + defparam INT_RAMB.INIT_62 = INIT_62; + defparam INT_RAMB.INIT_63 = INIT_63; + defparam INT_RAMB.INIT_64 = INIT_64; + defparam INT_RAMB.INIT_65 = INIT_65; + defparam INT_RAMB.INIT_66 = INIT_66; + defparam INT_RAMB.INIT_67 = INIT_67; + defparam INT_RAMB.INIT_68 = INIT_68; + defparam INT_RAMB.INIT_69 = INIT_69; + defparam INT_RAMB.INIT_6A = INIT_6A; + defparam INT_RAMB.INIT_6B = INIT_6B; + defparam INT_RAMB.INIT_6C = INIT_6C; + defparam INT_RAMB.INIT_6D = INIT_6D; + defparam INT_RAMB.INIT_6E = INIT_6E; + defparam INT_RAMB.INIT_6F = INIT_6F; + defparam INT_RAMB.INIT_70 = INIT_70; + defparam INT_RAMB.INIT_71 = INIT_71; + defparam INT_RAMB.INIT_72 = INIT_72; + defparam INT_RAMB.INIT_73 = INIT_73; + defparam INT_RAMB.INIT_74 = INIT_74; + defparam INT_RAMB.INIT_75 = INIT_75; + defparam INT_RAMB.INIT_76 = INIT_76; + defparam INT_RAMB.INIT_77 = INIT_77; + defparam INT_RAMB.INIT_78 = INIT_78; + defparam INT_RAMB.INIT_79 = INIT_79; + defparam INT_RAMB.INIT_7A = INIT_7A; + defparam INT_RAMB.INIT_7B = INIT_7B; + defparam INT_RAMB.INIT_7C = INIT_7C; + defparam INT_RAMB.INIT_7D = INIT_7D; + defparam INT_RAMB.INIT_7E = INIT_7E; + defparam INT_RAMB.INIT_7F = INIT_7F; + defparam INT_RAMB.INITP_00 = INITP_00; + defparam INT_RAMB.INITP_01 = INITP_01; + defparam INT_RAMB.INITP_02 = INITP_02; + defparam INT_RAMB.INITP_03 = INITP_03; + defparam INT_RAMB.INITP_04 = INITP_04; + defparam INT_RAMB.INITP_05 = INITP_05; + defparam INT_RAMB.INITP_06 = INITP_06; + defparam INT_RAMB.INITP_07 = INITP_07; + defparam INT_RAMB.INITP_08 = INITP_08; + defparam INT_RAMB.INITP_09 = INITP_09; + defparam INT_RAMB.INITP_0A = INITP_0A; + defparam INT_RAMB.INITP_0B = INITP_0B; + defparam INT_RAMB.INITP_0C = INITP_0C; + defparam INT_RAMB.INITP_0D = INITP_0D; + defparam INT_RAMB.INITP_0E = INITP_0E; + defparam INT_RAMB.INITP_0F = INITP_0F; + + specify + + (RDCLK => DO[0]) = (100, 100); + (RDCLK => DO[1]) = (100, 100); + (RDCLK => DO[2]) = (100, 100); + (RDCLK => DO[3]) = (100, 100); + (RDCLK => DO[4]) = (100, 100); + (RDCLK => DO[5]) = (100, 100); + (RDCLK => DO[6]) = (100, 100); + (RDCLK => DO[7]) = (100, 100); + (RDCLK => DO[8]) = (100, 100); + (RDCLK => DO[9]) = (100, 100); + (RDCLK => DO[10]) = (100, 100); + (RDCLK => DO[11]) = (100, 100); + (RDCLK => DO[12]) = (100, 100); + (RDCLK => DO[13]) = (100, 100); + (RDCLK => DO[14]) = (100, 100); + (RDCLK => DO[15]) = (100, 100); + (RDCLK => DO[16]) = (100, 100); + (RDCLK => DO[17]) = (100, 100); + (RDCLK => DO[18]) = (100, 100); + (RDCLK => DO[19]) = (100, 100); + (RDCLK => DO[20]) = (100, 100); + (RDCLK => DO[21]) = (100, 100); + (RDCLK => DO[22]) = (100, 100); + (RDCLK => DO[23]) = (100, 100); + (RDCLK => DO[24]) = (100, 100); + (RDCLK => DO[25]) = (100, 100); + (RDCLK => DO[26]) = (100, 100); + (RDCLK => DO[27]) = (100, 100); + (RDCLK => DO[28]) = (100, 100); + (RDCLK => DO[29]) = (100, 100); + (RDCLK => DO[30]) = (100, 100); + (RDCLK => DO[31]) = (100, 100); + (RDCLK => DO[32]) = (100, 100); + (RDCLK => DO[33]) = (100, 100); + (RDCLK => DO[34]) = (100, 100); + (RDCLK => DO[35]) = (100, 100); + (RDCLK => DO[36]) = (100, 100); + (RDCLK => DO[37]) = (100, 100); + (RDCLK => DO[38]) = (100, 100); + (RDCLK => DO[39]) = (100, 100); + (RDCLK => DO[40]) = (100, 100); + (RDCLK => DO[41]) = (100, 100); + (RDCLK => DO[42]) = (100, 100); + (RDCLK => DO[43]) = (100, 100); + (RDCLK => DO[44]) = (100, 100); + (RDCLK => DO[45]) = (100, 100); + (RDCLK => DO[46]) = (100, 100); + (RDCLK => DO[47]) = (100, 100); + (RDCLK => DO[48]) = (100, 100); + (RDCLK => DO[49]) = (100, 100); + (RDCLK => DO[50]) = (100, 100); + (RDCLK => DO[51]) = (100, 100); + (RDCLK => DO[52]) = (100, 100); + (RDCLK => DO[53]) = (100, 100); + (RDCLK => DO[54]) = (100, 100); + (RDCLK => DO[55]) = (100, 100); + (RDCLK => DO[56]) = (100, 100); + (RDCLK => DO[57]) = (100, 100); + (RDCLK => DO[58]) = (100, 100); + (RDCLK => DO[59]) = (100, 100); + (RDCLK => DO[60]) = (100, 100); + (RDCLK => DO[61]) = (100, 100); + (RDCLK => DO[62]) = (100, 100); + (RDCLK => DO[63]) = (100, 100); + (RDCLK => DOP[0]) = (100, 100); + (RDCLK => DOP[1]) = (100, 100); + (RDCLK => DOP[2]) = (100, 100); + (RDCLK => DOP[3]) = (100, 100); + (RDCLK => DOP[4]) = (100, 100); + (RDCLK => DOP[5]) = (100, 100); + (RDCLK => DOP[6]) = (100, 100); + (RDCLK => DOP[7]) = (100, 100); + (RDCLK => DBITERR) = (100, 100); + (RDCLK => SBITERR) = (100, 100); + (WRCLK => ECCPARITY[0]) = (100, 100); + (WRCLK => ECCPARITY[1]) = (100, 100); + (WRCLK => ECCPARITY[2]) = (100, 100); + (WRCLK => ECCPARITY[3]) = (100, 100); + (WRCLK => ECCPARITY[4]) = (100, 100); + (WRCLK => ECCPARITY[5]) = (100, 100); + (WRCLK => ECCPARITY[6]) = (100, 100); + (WRCLK => ECCPARITY[7]) = (100, 100); + + specparam PATHPULSE$ = 0; + + endspecify + +endmodule // RAMB36SDP + + + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/RAMB36SDP_EXP.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/RAMB36SDP_EXP.v new file mode 100644 index 0000000..8a11855 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/RAMB36SDP_EXP.v @@ -0,0 +1,562 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/rainier/RAMB36SDP_EXP.v,v 1.14 2007/06/15 20:58:40 wloo Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2005 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / 32K-Bit Data and 4K-Bit Parity Block RAM +// /___/ /\ Filename : RAMB36SDP_EXP.v +// \ \ / \ Timestamp : Tues July 26 16:43:59 PST 2005 +// \___\/\___\ +// +// Revision: +// 07/26/05 - Initial version. +// 01/04/07 - Added support of memory file to initialize memory and parity (CR 431584). +// 03/14/07 - Removed attribute INITP_FILE (CR 436003). +// 04/03/07 - Changed INIT_FILE = "NONE" as default (CR 436812). +// 06/13/07 - Added high performace version of the model. +// End Revision + +`timescale 1 ps/1 ps + +module RAMB36SDP_EXP (DBITERR, DO, DOP, ECCPARITY, SBITERR, + DI, DIP, RDADDRL, RDADDRU, RDCLKL, RDCLKU, RDENL, RDENU, RDRCLKL, RDRCLKU, REGCEL, REGCEU, SSRL, SSRU, WEL, WEU, WRADDRL, WRADDRU, WRCLKL, WRCLKU, WRENL, WRENU ); + + parameter integer DO_REG = 0; + parameter EN_ECC_READ = "FALSE"; + parameter EN_ECC_SCRUB = "FALSE"; + parameter EN_ECC_WRITE = "FALSE"; + parameter INIT = 72'h0; + parameter INITP_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_40 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_41 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_42 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_43 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_44 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_45 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_46 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_47 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_48 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_49 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_4A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_4B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_4C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_4D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_4E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_4F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_50 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_51 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_52 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_53 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_54 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_55 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_56 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_57 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_58 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_59 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_5A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_5B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_5C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_5D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_5E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_5F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_60 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_61 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_62 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_63 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_64 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_65 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_66 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_67 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_68 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_69 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_6A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_6B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_6C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_6D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_6E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_6F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_70 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_71 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_72 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_73 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_74 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_75 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_76 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_77 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_78 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_79 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_7A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_7B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_7C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_7D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_7E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_7F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_FILE = "NONE"; + parameter SIM_COLLISION_CHECK = "ALL"; + parameter SIM_MODE = "SAFE"; + parameter SRVAL = 72'h0; + + localparam SETUP_ALL = 1000; + localparam SETUP_READ_FIRST = 3000; + + output DBITERR; + output SBITERR; + output [63:0] DO; + output [7:0] DOP; + output [7:0] ECCPARITY; + + input RDCLKL; + input RDCLKU; + input RDENL; + input RDENU; + input RDRCLKL; + input RDRCLKU; + input REGCEL; + input REGCEU; + input SSRL; + input SSRU; + input WRCLKL; + input WRCLKU; + input WRENL; + input WRENU; + input [14:0] RDADDRU; + input [14:0] WRADDRU; + input [15:0] RDADDRL; + input [15:0] WRADDRL; + input [63:0] DI; + input [7:0] DIP; + input [7:0] WEL; + input [7:0] WEU; + + tri0 GSR = glbl.GSR; + + wire [7:0] dangle_out8; + wire dangle_out; + wire [3:0] dangle_out4; + wire [31:0] dangle_out32; + + localparam BRAM_MODE = (EN_ECC_WRITE == "TRUE" || EN_ECC_READ == "TRUE") ? "ECC" : "SIMPLE_DUAL_PORT"; + + ARAMB36_INTERNAL INT_RAMB (.DIA(64'b0), .ENA(RDENL), .WEA(8'b0), .SSRA(SSRL), .ADDRA(RDADDRL), .CLKA(RDCLKL), .DOA(DO), .DIB(DI), .ENB(WRENL), .WEB(WEL), .SSRB(1'b0), .ADDRB(WRADDRL), .CLKB(WRCLKL), .DOB(dangle_out32), .GSR(GSR), .DOPA(DOP), .DOPB(dangle_out4), .DIPA(4'b0), .DIPB(DIP), .CASCADEOUTLATA(dangle_out), .CASCADEOUTLATB(dangle_out), .CASCADEOUTREGA(dangle_out), .CASCADEOUTREGB(dangle_out), .CASCADEINLATA(1'b0), .CASCADEINLATB(1'b0), .CASCADEINREGA(1'b0), .CASCADEINREGB(1'b0), .REGCEA(REGCEL), .REGCEB(1'b0), .REGCLKA(RDRCLKL), .REGCLKB(1'b0), .DBITERR(DBITERR), .ECCPARITY(ECCPARITY), .SBITERR(SBITERR)); + + defparam INT_RAMB.SIM_MODE = SIM_MODE; + defparam INT_RAMB.BRAM_MODE = BRAM_MODE; + defparam INT_RAMB.INIT_A = INIT; + defparam INT_RAMB.INIT_B = INIT; + defparam INT_RAMB.INIT_FILE = INIT_FILE; + defparam INT_RAMB.SRVAL_A = SRVAL; + defparam INT_RAMB.SRVAL_B = SRVAL; + defparam INT_RAMB.READ_WIDTH_A = 72; + defparam INT_RAMB.READ_WIDTH_B = 72; + defparam INT_RAMB.WRITE_WIDTH_A = 72; + defparam INT_RAMB.WRITE_WIDTH_B = 72; + defparam INT_RAMB.WRITE_MODE_A = "READ_FIRST"; + defparam INT_RAMB.WRITE_MODE_B = "READ_FIRST"; + defparam INT_RAMB.RAM_EXTENSION_A = "NONE"; + defparam INT_RAMB.RAM_EXTENSION_B = "NONE"; + defparam INT_RAMB.SETUP_ALL = SETUP_ALL; + defparam INT_RAMB.SETUP_READ_FIRST = SETUP_READ_FIRST; + defparam INT_RAMB.SIM_COLLISION_CHECK = SIM_COLLISION_CHECK; + defparam INT_RAMB.EN_ECC_READ = EN_ECC_READ; + defparam INT_RAMB.EN_ECC_SCRUB = EN_ECC_SCRUB; + defparam INT_RAMB.EN_ECC_WRITE = EN_ECC_WRITE; + defparam INT_RAMB.DOA_REG = DO_REG; + defparam INT_RAMB.DOB_REG = DO_REG; + defparam INT_RAMB.INIT_00 = INIT_00; + defparam INT_RAMB.INIT_01 = INIT_01; + defparam INT_RAMB.INIT_02 = INIT_02; + defparam INT_RAMB.INIT_03 = INIT_03; + defparam INT_RAMB.INIT_04 = INIT_04; + defparam INT_RAMB.INIT_05 = INIT_05; + defparam INT_RAMB.INIT_06 = INIT_06; + defparam INT_RAMB.INIT_07 = INIT_07; + defparam INT_RAMB.INIT_08 = INIT_08; + defparam INT_RAMB.INIT_09 = INIT_09; + defparam INT_RAMB.INIT_0A = INIT_0A; + defparam INT_RAMB.INIT_0B = INIT_0B; + defparam INT_RAMB.INIT_0C = INIT_0C; + defparam INT_RAMB.INIT_0D = INIT_0D; + defparam INT_RAMB.INIT_0E = INIT_0E; + defparam INT_RAMB.INIT_0F = INIT_0F; + defparam INT_RAMB.INIT_10 = INIT_10; + defparam INT_RAMB.INIT_11 = INIT_11; + defparam INT_RAMB.INIT_12 = INIT_12; + defparam INT_RAMB.INIT_13 = INIT_13; + defparam INT_RAMB.INIT_14 = INIT_14; + defparam INT_RAMB.INIT_15 = INIT_15; + defparam INT_RAMB.INIT_16 = INIT_16; + defparam INT_RAMB.INIT_17 = INIT_17; + defparam INT_RAMB.INIT_18 = INIT_18; + defparam INT_RAMB.INIT_19 = INIT_19; + defparam INT_RAMB.INIT_1A = INIT_1A; + defparam INT_RAMB.INIT_1B = INIT_1B; + defparam INT_RAMB.INIT_1C = INIT_1C; + defparam INT_RAMB.INIT_1D = INIT_1D; + defparam INT_RAMB.INIT_1E = INIT_1E; + defparam INT_RAMB.INIT_1F = INIT_1F; + defparam INT_RAMB.INIT_20 = INIT_20; + defparam INT_RAMB.INIT_21 = INIT_21; + defparam INT_RAMB.INIT_22 = INIT_22; + defparam INT_RAMB.INIT_23 = INIT_23; + defparam INT_RAMB.INIT_24 = INIT_24; + defparam INT_RAMB.INIT_25 = INIT_25; + defparam INT_RAMB.INIT_26 = INIT_26; + defparam INT_RAMB.INIT_27 = INIT_27; + defparam INT_RAMB.INIT_28 = INIT_28; + defparam INT_RAMB.INIT_29 = INIT_29; + defparam INT_RAMB.INIT_2A = INIT_2A; + defparam INT_RAMB.INIT_2B = INIT_2B; + defparam INT_RAMB.INIT_2C = INIT_2C; + defparam INT_RAMB.INIT_2D = INIT_2D; + defparam INT_RAMB.INIT_2E = INIT_2E; + defparam INT_RAMB.INIT_2F = INIT_2F; + defparam INT_RAMB.INIT_30 = INIT_30; + defparam INT_RAMB.INIT_31 = INIT_31; + defparam INT_RAMB.INIT_32 = INIT_32; + defparam INT_RAMB.INIT_33 = INIT_33; + defparam INT_RAMB.INIT_34 = INIT_34; + defparam INT_RAMB.INIT_35 = INIT_35; + defparam INT_RAMB.INIT_36 = INIT_36; + defparam INT_RAMB.INIT_37 = INIT_37; + defparam INT_RAMB.INIT_38 = INIT_38; + defparam INT_RAMB.INIT_39 = INIT_39; + defparam INT_RAMB.INIT_3A = INIT_3A; + defparam INT_RAMB.INIT_3B = INIT_3B; + defparam INT_RAMB.INIT_3C = INIT_3C; + defparam INT_RAMB.INIT_3D = INIT_3D; + defparam INT_RAMB.INIT_3E = INIT_3E; + defparam INT_RAMB.INIT_3F = INIT_3F; + defparam INT_RAMB.INIT_40 = INIT_40; + defparam INT_RAMB.INIT_41 = INIT_41; + defparam INT_RAMB.INIT_42 = INIT_42; + defparam INT_RAMB.INIT_43 = INIT_43; + defparam INT_RAMB.INIT_44 = INIT_44; + defparam INT_RAMB.INIT_45 = INIT_45; + defparam INT_RAMB.INIT_46 = INIT_46; + defparam INT_RAMB.INIT_47 = INIT_47; + defparam INT_RAMB.INIT_48 = INIT_48; + defparam INT_RAMB.INIT_49 = INIT_49; + defparam INT_RAMB.INIT_4A = INIT_4A; + defparam INT_RAMB.INIT_4B = INIT_4B; + defparam INT_RAMB.INIT_4C = INIT_4C; + defparam INT_RAMB.INIT_4D = INIT_4D; + defparam INT_RAMB.INIT_4E = INIT_4E; + defparam INT_RAMB.INIT_4F = INIT_4F; + defparam INT_RAMB.INIT_50 = INIT_50; + defparam INT_RAMB.INIT_51 = INIT_51; + defparam INT_RAMB.INIT_52 = INIT_52; + defparam INT_RAMB.INIT_53 = INIT_53; + defparam INT_RAMB.INIT_54 = INIT_54; + defparam INT_RAMB.INIT_55 = INIT_55; + defparam INT_RAMB.INIT_56 = INIT_56; + defparam INT_RAMB.INIT_57 = INIT_57; + defparam INT_RAMB.INIT_58 = INIT_58; + defparam INT_RAMB.INIT_59 = INIT_59; + defparam INT_RAMB.INIT_5A = INIT_5A; + defparam INT_RAMB.INIT_5B = INIT_5B; + defparam INT_RAMB.INIT_5C = INIT_5C; + defparam INT_RAMB.INIT_5D = INIT_5D; + defparam INT_RAMB.INIT_5E = INIT_5E; + defparam INT_RAMB.INIT_5F = INIT_5F; + defparam INT_RAMB.INIT_60 = INIT_60; + defparam INT_RAMB.INIT_61 = INIT_61; + defparam INT_RAMB.INIT_62 = INIT_62; + defparam INT_RAMB.INIT_63 = INIT_63; + defparam INT_RAMB.INIT_64 = INIT_64; + defparam INT_RAMB.INIT_65 = INIT_65; + defparam INT_RAMB.INIT_66 = INIT_66; + defparam INT_RAMB.INIT_67 = INIT_67; + defparam INT_RAMB.INIT_68 = INIT_68; + defparam INT_RAMB.INIT_69 = INIT_69; + defparam INT_RAMB.INIT_6A = INIT_6A; + defparam INT_RAMB.INIT_6B = INIT_6B; + defparam INT_RAMB.INIT_6C = INIT_6C; + defparam INT_RAMB.INIT_6D = INIT_6D; + defparam INT_RAMB.INIT_6E = INIT_6E; + defparam INT_RAMB.INIT_6F = INIT_6F; + defparam INT_RAMB.INIT_70 = INIT_70; + defparam INT_RAMB.INIT_71 = INIT_71; + defparam INT_RAMB.INIT_72 = INIT_72; + defparam INT_RAMB.INIT_73 = INIT_73; + defparam INT_RAMB.INIT_74 = INIT_74; + defparam INT_RAMB.INIT_75 = INIT_75; + defparam INT_RAMB.INIT_76 = INIT_76; + defparam INT_RAMB.INIT_77 = INIT_77; + defparam INT_RAMB.INIT_78 = INIT_78; + defparam INT_RAMB.INIT_79 = INIT_79; + defparam INT_RAMB.INIT_7A = INIT_7A; + defparam INT_RAMB.INIT_7B = INIT_7B; + defparam INT_RAMB.INIT_7C = INIT_7C; + defparam INT_RAMB.INIT_7D = INIT_7D; + defparam INT_RAMB.INIT_7E = INIT_7E; + defparam INT_RAMB.INIT_7F = INIT_7F; + defparam INT_RAMB.INITP_00 = INITP_00; + defparam INT_RAMB.INITP_01 = INITP_01; + defparam INT_RAMB.INITP_02 = INITP_02; + defparam INT_RAMB.INITP_03 = INITP_03; + defparam INT_RAMB.INITP_04 = INITP_04; + defparam INT_RAMB.INITP_05 = INITP_05; + defparam INT_RAMB.INITP_06 = INITP_06; + defparam INT_RAMB.INITP_07 = INITP_07; + defparam INT_RAMB.INITP_08 = INITP_08; + defparam INT_RAMB.INITP_09 = INITP_09; + defparam INT_RAMB.INITP_0A = INITP_0A; + defparam INT_RAMB.INITP_0B = INITP_0B; + defparam INT_RAMB.INITP_0C = INITP_0C; + defparam INT_RAMB.INITP_0D = INITP_0D; + defparam INT_RAMB.INITP_0E = INITP_0E; + defparam INT_RAMB.INITP_0F = INITP_0F; + + specify + + (RDCLKL => DO[0]) = (100, 100); + (RDCLKL => DO[1]) = (100, 100); + (RDCLKL => DO[2]) = (100, 100); + (RDCLKL => DO[3]) = (100, 100); + (RDCLKL => DO[4]) = (100, 100); + (RDCLKL => DO[5]) = (100, 100); + (RDCLKL => DO[6]) = (100, 100); + (RDCLKL => DO[7]) = (100, 100); + (RDCLKL => DO[8]) = (100, 100); + (RDCLKL => DO[9]) = (100, 100); + (RDCLKL => DO[10]) = (100, 100); + (RDCLKL => DO[11]) = (100, 100); + (RDCLKL => DO[12]) = (100, 100); + (RDCLKL => DO[13]) = (100, 100); + (RDCLKL => DO[14]) = (100, 100); + (RDCLKL => DO[15]) = (100, 100); + (RDCLKL => DO[16]) = (100, 100); + (RDCLKL => DO[17]) = (100, 100); + (RDCLKL => DO[18]) = (100, 100); + (RDCLKL => DO[19]) = (100, 100); + (RDCLKL => DO[20]) = (100, 100); + (RDCLKL => DO[21]) = (100, 100); + (RDCLKL => DO[22]) = (100, 100); + (RDCLKL => DO[23]) = (100, 100); + (RDCLKL => DO[24]) = (100, 100); + (RDCLKL => DO[25]) = (100, 100); + (RDCLKL => DO[26]) = (100, 100); + (RDCLKL => DO[27]) = (100, 100); + (RDCLKL => DO[28]) = (100, 100); + (RDCLKL => DO[29]) = (100, 100); + (RDCLKL => DO[30]) = (100, 100); + (RDCLKL => DO[31]) = (100, 100); + (RDCLKL => DO[32]) = (100, 100); + (RDCLKL => DO[33]) = (100, 100); + (RDCLKL => DO[34]) = (100, 100); + (RDCLKL => DO[35]) = (100, 100); + (RDCLKL => DO[36]) = (100, 100); + (RDCLKL => DO[37]) = (100, 100); + (RDCLKL => DO[38]) = (100, 100); + (RDCLKL => DO[39]) = (100, 100); + (RDCLKL => DO[40]) = (100, 100); + (RDCLKL => DO[41]) = (100, 100); + (RDCLKL => DO[42]) = (100, 100); + (RDCLKL => DO[43]) = (100, 100); + (RDCLKL => DO[44]) = (100, 100); + (RDCLKL => DO[45]) = (100, 100); + (RDCLKL => DO[46]) = (100, 100); + (RDCLKL => DO[47]) = (100, 100); + (RDCLKL => DO[48]) = (100, 100); + (RDCLKL => DO[49]) = (100, 100); + (RDCLKL => DO[50]) = (100, 100); + (RDCLKL => DO[51]) = (100, 100); + (RDCLKL => DO[52]) = (100, 100); + (RDCLKL => DO[53]) = (100, 100); + (RDCLKL => DO[54]) = (100, 100); + (RDCLKL => DO[55]) = (100, 100); + (RDCLKL => DO[56]) = (100, 100); + (RDCLKL => DO[57]) = (100, 100); + (RDCLKL => DO[58]) = (100, 100); + (RDCLKL => DO[59]) = (100, 100); + (RDCLKL => DO[60]) = (100, 100); + (RDCLKL => DO[61]) = (100, 100); + (RDCLKL => DO[62]) = (100, 100); + (RDCLKL => DO[63]) = (100, 100); + (RDCLKL => DOP[0]) = (100, 100); + (RDCLKL => DOP[1]) = (100, 100); + (RDCLKL => DOP[2]) = (100, 100); + (RDCLKL => DOP[3]) = (100, 100); + (RDCLKL => DOP[4]) = (100, 100); + (RDCLKL => DOP[5]) = (100, 100); + (RDCLKL => DOP[6]) = (100, 100); + (RDCLKL => DOP[7]) = (100, 100); + (RDCLKL => DBITERR) = (100, 100); + (RDCLKL => SBITERR) = (100, 100); + + (RDRCLKL => DO[0]) = (100, 100); + (RDRCLKL => DO[1]) = (100, 100); + (RDRCLKL => DO[2]) = (100, 100); + (RDRCLKL => DO[3]) = (100, 100); + (RDRCLKL => DO[4]) = (100, 100); + (RDRCLKL => DO[5]) = (100, 100); + (RDRCLKL => DO[6]) = (100, 100); + (RDRCLKL => DO[7]) = (100, 100); + (RDRCLKL => DO[8]) = (100, 100); + (RDRCLKL => DO[9]) = (100, 100); + (RDRCLKL => DO[10]) = (100, 100); + (RDRCLKL => DO[11]) = (100, 100); + (RDRCLKL => DO[12]) = (100, 100); + (RDRCLKL => DO[13]) = (100, 100); + (RDRCLKL => DO[14]) = (100, 100); + (RDRCLKL => DO[15]) = (100, 100); + (RDRCLKL => DO[16]) = (100, 100); + (RDRCLKL => DO[17]) = (100, 100); + (RDRCLKL => DO[18]) = (100, 100); + (RDRCLKL => DO[19]) = (100, 100); + (RDRCLKL => DO[20]) = (100, 100); + (RDRCLKL => DO[21]) = (100, 100); + (RDRCLKL => DO[22]) = (100, 100); + (RDRCLKL => DO[23]) = (100, 100); + (RDRCLKL => DO[24]) = (100, 100); + (RDRCLKL => DO[25]) = (100, 100); + (RDRCLKL => DO[26]) = (100, 100); + (RDRCLKL => DO[27]) = (100, 100); + (RDRCLKL => DO[28]) = (100, 100); + (RDRCLKL => DO[29]) = (100, 100); + (RDRCLKL => DO[30]) = (100, 100); + (RDRCLKL => DO[31]) = (100, 100); + (RDRCLKL => DO[32]) = (100, 100); + (RDRCLKL => DO[33]) = (100, 100); + (RDRCLKL => DO[34]) = (100, 100); + (RDRCLKL => DO[35]) = (100, 100); + (RDRCLKL => DO[36]) = (100, 100); + (RDRCLKL => DO[37]) = (100, 100); + (RDRCLKL => DO[38]) = (100, 100); + (RDRCLKL => DO[39]) = (100, 100); + (RDRCLKL => DO[40]) = (100, 100); + (RDRCLKL => DO[41]) = (100, 100); + (RDRCLKL => DO[42]) = (100, 100); + (RDRCLKL => DO[43]) = (100, 100); + (RDRCLKL => DO[44]) = (100, 100); + (RDRCLKL => DO[45]) = (100, 100); + (RDRCLKL => DO[46]) = (100, 100); + (RDRCLKL => DO[47]) = (100, 100); + (RDRCLKL => DO[48]) = (100, 100); + (RDRCLKL => DO[49]) = (100, 100); + (RDRCLKL => DO[50]) = (100, 100); + (RDRCLKL => DO[51]) = (100, 100); + (RDRCLKL => DO[52]) = (100, 100); + (RDRCLKL => DO[53]) = (100, 100); + (RDRCLKL => DO[54]) = (100, 100); + (RDRCLKL => DO[55]) = (100, 100); + (RDRCLKL => DO[56]) = (100, 100); + (RDRCLKL => DO[57]) = (100, 100); + (RDRCLKL => DO[58]) = (100, 100); + (RDRCLKL => DO[59]) = (100, 100); + (RDRCLKL => DO[60]) = (100, 100); + (RDRCLKL => DO[61]) = (100, 100); + (RDRCLKL => DO[62]) = (100, 100); + (RDRCLKL => DO[63]) = (100, 100); + (RDRCLKL => DOP[0]) = (100, 100); + (RDRCLKL => DOP[1]) = (100, 100); + (RDRCLKL => DOP[2]) = (100, 100); + (RDRCLKL => DOP[3]) = (100, 100); + (RDRCLKL => DOP[4]) = (100, 100); + (RDRCLKL => DOP[5]) = (100, 100); + (RDRCLKL => DOP[6]) = (100, 100); + (RDRCLKL => DOP[7]) = (100, 100); + (RDRCLKL => DBITERR) = (100, 100); + (RDRCLKL => SBITERR) = (100, 100); + + (WRCLKL => ECCPARITY[0]) = (100, 100); + (WRCLKL => ECCPARITY[1]) = (100, 100); + (WRCLKL => ECCPARITY[2]) = (100, 100); + (WRCLKL => ECCPARITY[3]) = (100, 100); + (WRCLKL => ECCPARITY[4]) = (100, 100); + (WRCLKL => ECCPARITY[5]) = (100, 100); + (WRCLKL => ECCPARITY[6]) = (100, 100); + (WRCLKL => ECCPARITY[7]) = (100, 100); + + specparam PATHPULSE$ = 0; + + endspecify + +endmodule // RAMB36SDP_EXP + + + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/RAMB36_EXP.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/RAMB36_EXP.v new file mode 100644 index 0000000..1c9b784 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/RAMB36_EXP.v @@ -0,0 +1,579 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/rainier/RAMB36_EXP.v,v 1.16 2007/06/15 20:58:40 wloo Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2005 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / 32K-Bit Data and 4K-Bit Parity Dual Port Block RAM +// /___/ /\ Filename : RAMB36_EXP.v +// \ \ / \ Timestamp : Tues July 26 16:43:59 PST 2005 +// \___\/\___\ +// +// Revision: +// 07/26/05 - Initial version. +// 01/04/07 - Added support of memory file to initialize memory and parity (CR 431584). +// 03/14/07 - Removed attribute INITP_FILE (CR 436003). +// 04/03/07 - Changed INIT_FILE = "NONE" as default (CR 436812). +// 06/13/07 - Added high performace version of the model. +// End Revision + +`timescale 1 ps / 1 ps + +module RAMB36_EXP (CASCADEOUTLATA, CASCADEOUTLATB, CASCADEOUTREGA, CASCADEOUTREGB, DOA, DOB, DOPA, DOPB, + ADDRAL, ADDRAU, ADDRBL, ADDRBU, CASCADEINLATA, CASCADEINLATB, CASCADEINREGA, CASCADEINREGB, CLKAL, CLKAU, CLKBL, CLKBU, DIA, DIB, DIPA, DIPB, ENAL, ENAU, ENBL, ENBU, REGCEAL, REGCEAU, REGCEBL, REGCEBU, REGCLKAL, REGCLKAU, REGCLKBL, REGCLKBU, SSRAL, SSRAU, SSRBL, SSRBU, WEAL, WEAU, WEBL, WEBU); + + parameter integer DOA_REG = 0; + parameter integer DOB_REG = 0; + parameter INITP_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_40 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_41 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_42 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_43 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_44 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_45 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_46 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_47 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_48 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_49 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_4A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_4B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_4C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_4D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_4E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_4F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_50 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_51 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_52 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_53 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_54 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_55 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_56 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_57 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_58 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_59 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_5A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_5B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_5C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_5D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_5E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_5F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_60 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_61 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_62 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_63 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_64 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_65 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_66 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_67 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_68 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_69 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_6A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_6B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_6C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_6D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_6E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_6F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_70 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_71 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_72 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_73 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_74 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_75 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_76 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_77 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_78 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_79 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_7A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_7B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_7C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_7D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_7E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_7F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_A = 36'h0; + parameter INIT_B = 36'h0; + parameter INIT_FILE = "NONE"; + parameter RAM_EXTENSION_A = "NONE"; + parameter RAM_EXTENSION_B = "NONE"; + parameter integer READ_WIDTH_A = 0; + parameter integer READ_WIDTH_B = 0; + parameter SIM_COLLISION_CHECK = "ALL"; + parameter SIM_MODE = "SAFE"; + parameter SRVAL_A = 36'h0; + parameter SRVAL_B = 36'h0; + parameter WRITE_MODE_A = "WRITE_FIRST"; + parameter WRITE_MODE_B = "WRITE_FIRST"; + parameter integer WRITE_WIDTH_A = 0; + parameter integer WRITE_WIDTH_B = 0; + + localparam SETUP_ALL = 1000; + localparam SETUP_READ_FIRST = 3000; + + output CASCADEOUTLATA; + output CASCADEOUTLATB; + output CASCADEOUTREGA; + output CASCADEOUTREGB; + output [31:0] DOA; + output [31:0] DOB; + output [3:0] DOPA; + output [3:0] DOPB; + + input [14:0] ADDRAU; + input [14:0] ADDRBU; + input [15:0] ADDRAL; + input [15:0] ADDRBL; + input CASCADEINLATA; + input CASCADEINLATB; + input CASCADEINREGA; + input CASCADEINREGB; + input CLKAL; + input CLKAU; + input CLKBL; + input CLKBU; + input [31:0] DIA; + input [31:0] DIB; + input [3:0] DIPA; + input [3:0] DIPB; + input ENAL; + input ENAU; + input ENBL; + input ENBU; + input REGCEAL; + input REGCEAU; + input REGCEBL; + input REGCEBU; + input REGCLKAL; + input REGCLKAU; + input REGCLKBL; + input REGCLKBU; + input SSRAL; + input SSRAU; + input SSRBL; + input SSRBU; + input [3:0] WEAL; + input [3:0] WEAU; + input [7:0] WEBL; + input [7:0] WEBU; + + tri0 GSR = glbl.GSR; + + wire [7:0] dangle_out8; + wire dangle_out; + wire [3:0] dangle_out4; + wire [31:0] dangle_out32; + + ARAMB36_INTERNAL INT_RAMB (.DIA({32'b0,DIA}), .ENA(ENAL), .WEA({4'b0,WEAL}), .SSRA(SSRAL), .ADDRA(ADDRAL), .CLKA(CLKAL), .DOA({dangle_out32,DOA}), .DIB({32'b0,DIB}), .ENB(ENBL), .WEB(WEBL), .SSRB(SSRBL), .ADDRB(ADDRBL), .CLKB(CLKBL), .DOB(DOB), .GSR(GSR), .DOPA({dangle_out4,DOPA}), .DOPB(DOPB), .DIPA(DIPA), .DIPB({4'b0,DIPB}), .CASCADEOUTLATA(CASCADEOUTLATA), .CASCADEOUTLATB(CASCADEOUTLATB), .CASCADEOUTREGA(CASCADEOUTREGA), .CASCADEOUTREGB(CASCADEOUTREGB), .CASCADEINLATA(CASCADEINLATA), .CASCADEINLATB(CASCADEINLATB), .CASCADEINREGA(CASCADEINREGA), .CASCADEINREGB(CASCADEINREGB), .REGCEA(REGCEAL), .REGCEB(REGCEBL), .REGCLKA(REGCLKAL), .REGCLKB(REGCLKBL), .DBITERR(dangle_out), .ECCPARITY(dangle_out8), .SBITERR(dangle_out)); + + defparam INT_RAMB.SIM_MODE = SIM_MODE; + defparam INT_RAMB.BRAM_MODE = "TRUE_DUAL_PORT"; + defparam INT_RAMB.INIT_A = INIT_A; + defparam INT_RAMB.INIT_B = INIT_B; + defparam INT_RAMB.INIT_FILE = INIT_FILE; + defparam INT_RAMB.SRVAL_A = SRVAL_A; + defparam INT_RAMB.SRVAL_B = SRVAL_B; + defparam INT_RAMB.READ_WIDTH_A = READ_WIDTH_A; + defparam INT_RAMB.READ_WIDTH_B = READ_WIDTH_B; + defparam INT_RAMB.WRITE_WIDTH_A = WRITE_WIDTH_A; + defparam INT_RAMB.WRITE_WIDTH_B = WRITE_WIDTH_B; + defparam INT_RAMB.WRITE_MODE_A = WRITE_MODE_A; + defparam INT_RAMB.WRITE_MODE_B = WRITE_MODE_B; + defparam INT_RAMB.RAM_EXTENSION_A = RAM_EXTENSION_A; + defparam INT_RAMB.RAM_EXTENSION_B = RAM_EXTENSION_B; + defparam INT_RAMB.SETUP_ALL = SETUP_ALL; + defparam INT_RAMB.SETUP_READ_FIRST = SETUP_READ_FIRST; + defparam INT_RAMB.SIM_COLLISION_CHECK = SIM_COLLISION_CHECK; + defparam INT_RAMB.EN_ECC_READ = "FALSE"; + defparam INT_RAMB.EN_ECC_SCRUB = "FALSE"; + defparam INT_RAMB.EN_ECC_WRITE = "FALSE"; + defparam INT_RAMB.DOA_REG = DOA_REG; + defparam INT_RAMB.DOB_REG = DOB_REG; + defparam INT_RAMB.INIT_00 = INIT_00; + defparam INT_RAMB.INIT_01 = INIT_01; + defparam INT_RAMB.INIT_02 = INIT_02; + defparam INT_RAMB.INIT_03 = INIT_03; + defparam INT_RAMB.INIT_04 = INIT_04; + defparam INT_RAMB.INIT_05 = INIT_05; + defparam INT_RAMB.INIT_06 = INIT_06; + defparam INT_RAMB.INIT_07 = INIT_07; + defparam INT_RAMB.INIT_08 = INIT_08; + defparam INT_RAMB.INIT_09 = INIT_09; + defparam INT_RAMB.INIT_0A = INIT_0A; + defparam INT_RAMB.INIT_0B = INIT_0B; + defparam INT_RAMB.INIT_0C = INIT_0C; + defparam INT_RAMB.INIT_0D = INIT_0D; + defparam INT_RAMB.INIT_0E = INIT_0E; + defparam INT_RAMB.INIT_0F = INIT_0F; + defparam INT_RAMB.INIT_10 = INIT_10; + defparam INT_RAMB.INIT_11 = INIT_11; + defparam INT_RAMB.INIT_12 = INIT_12; + defparam INT_RAMB.INIT_13 = INIT_13; + defparam INT_RAMB.INIT_14 = INIT_14; + defparam INT_RAMB.INIT_15 = INIT_15; + defparam INT_RAMB.INIT_16 = INIT_16; + defparam INT_RAMB.INIT_17 = INIT_17; + defparam INT_RAMB.INIT_18 = INIT_18; + defparam INT_RAMB.INIT_19 = INIT_19; + defparam INT_RAMB.INIT_1A = INIT_1A; + defparam INT_RAMB.INIT_1B = INIT_1B; + defparam INT_RAMB.INIT_1C = INIT_1C; + defparam INT_RAMB.INIT_1D = INIT_1D; + defparam INT_RAMB.INIT_1E = INIT_1E; + defparam INT_RAMB.INIT_1F = INIT_1F; + defparam INT_RAMB.INIT_20 = INIT_20; + defparam INT_RAMB.INIT_21 = INIT_21; + defparam INT_RAMB.INIT_22 = INIT_22; + defparam INT_RAMB.INIT_23 = INIT_23; + defparam INT_RAMB.INIT_24 = INIT_24; + defparam INT_RAMB.INIT_25 = INIT_25; + defparam INT_RAMB.INIT_26 = INIT_26; + defparam INT_RAMB.INIT_27 = INIT_27; + defparam INT_RAMB.INIT_28 = INIT_28; + defparam INT_RAMB.INIT_29 = INIT_29; + defparam INT_RAMB.INIT_2A = INIT_2A; + defparam INT_RAMB.INIT_2B = INIT_2B; + defparam INT_RAMB.INIT_2C = INIT_2C; + defparam INT_RAMB.INIT_2D = INIT_2D; + defparam INT_RAMB.INIT_2E = INIT_2E; + defparam INT_RAMB.INIT_2F = INIT_2F; + defparam INT_RAMB.INIT_30 = INIT_30; + defparam INT_RAMB.INIT_31 = INIT_31; + defparam INT_RAMB.INIT_32 = INIT_32; + defparam INT_RAMB.INIT_33 = INIT_33; + defparam INT_RAMB.INIT_34 = INIT_34; + defparam INT_RAMB.INIT_35 = INIT_35; + defparam INT_RAMB.INIT_36 = INIT_36; + defparam INT_RAMB.INIT_37 = INIT_37; + defparam INT_RAMB.INIT_38 = INIT_38; + defparam INT_RAMB.INIT_39 = INIT_39; + defparam INT_RAMB.INIT_3A = INIT_3A; + defparam INT_RAMB.INIT_3B = INIT_3B; + defparam INT_RAMB.INIT_3C = INIT_3C; + defparam INT_RAMB.INIT_3D = INIT_3D; + defparam INT_RAMB.INIT_3E = INIT_3E; + defparam INT_RAMB.INIT_3F = INIT_3F; + defparam INT_RAMB.INIT_40 = INIT_40; + defparam INT_RAMB.INIT_41 = INIT_41; + defparam INT_RAMB.INIT_42 = INIT_42; + defparam INT_RAMB.INIT_43 = INIT_43; + defparam INT_RAMB.INIT_44 = INIT_44; + defparam INT_RAMB.INIT_45 = INIT_45; + defparam INT_RAMB.INIT_46 = INIT_46; + defparam INT_RAMB.INIT_47 = INIT_47; + defparam INT_RAMB.INIT_48 = INIT_48; + defparam INT_RAMB.INIT_49 = INIT_49; + defparam INT_RAMB.INIT_4A = INIT_4A; + defparam INT_RAMB.INIT_4B = INIT_4B; + defparam INT_RAMB.INIT_4C = INIT_4C; + defparam INT_RAMB.INIT_4D = INIT_4D; + defparam INT_RAMB.INIT_4E = INIT_4E; + defparam INT_RAMB.INIT_4F = INIT_4F; + defparam INT_RAMB.INIT_50 = INIT_50; + defparam INT_RAMB.INIT_51 = INIT_51; + defparam INT_RAMB.INIT_52 = INIT_52; + defparam INT_RAMB.INIT_53 = INIT_53; + defparam INT_RAMB.INIT_54 = INIT_54; + defparam INT_RAMB.INIT_55 = INIT_55; + defparam INT_RAMB.INIT_56 = INIT_56; + defparam INT_RAMB.INIT_57 = INIT_57; + defparam INT_RAMB.INIT_58 = INIT_58; + defparam INT_RAMB.INIT_59 = INIT_59; + defparam INT_RAMB.INIT_5A = INIT_5A; + defparam INT_RAMB.INIT_5B = INIT_5B; + defparam INT_RAMB.INIT_5C = INIT_5C; + defparam INT_RAMB.INIT_5D = INIT_5D; + defparam INT_RAMB.INIT_5E = INIT_5E; + defparam INT_RAMB.INIT_5F = INIT_5F; + defparam INT_RAMB.INIT_60 = INIT_60; + defparam INT_RAMB.INIT_61 = INIT_61; + defparam INT_RAMB.INIT_62 = INIT_62; + defparam INT_RAMB.INIT_63 = INIT_63; + defparam INT_RAMB.INIT_64 = INIT_64; + defparam INT_RAMB.INIT_65 = INIT_65; + defparam INT_RAMB.INIT_66 = INIT_66; + defparam INT_RAMB.INIT_67 = INIT_67; + defparam INT_RAMB.INIT_68 = INIT_68; + defparam INT_RAMB.INIT_69 = INIT_69; + defparam INT_RAMB.INIT_6A = INIT_6A; + defparam INT_RAMB.INIT_6B = INIT_6B; + defparam INT_RAMB.INIT_6C = INIT_6C; + defparam INT_RAMB.INIT_6D = INIT_6D; + defparam INT_RAMB.INIT_6E = INIT_6E; + defparam INT_RAMB.INIT_6F = INIT_6F; + defparam INT_RAMB.INIT_70 = INIT_70; + defparam INT_RAMB.INIT_71 = INIT_71; + defparam INT_RAMB.INIT_72 = INIT_72; + defparam INT_RAMB.INIT_73 = INIT_73; + defparam INT_RAMB.INIT_74 = INIT_74; + defparam INT_RAMB.INIT_75 = INIT_75; + defparam INT_RAMB.INIT_76 = INIT_76; + defparam INT_RAMB.INIT_77 = INIT_77; + defparam INT_RAMB.INIT_78 = INIT_78; + defparam INT_RAMB.INIT_79 = INIT_79; + defparam INT_RAMB.INIT_7A = INIT_7A; + defparam INT_RAMB.INIT_7B = INIT_7B; + defparam INT_RAMB.INIT_7C = INIT_7C; + defparam INT_RAMB.INIT_7D = INIT_7D; + defparam INT_RAMB.INIT_7E = INIT_7E; + defparam INT_RAMB.INIT_7F = INIT_7F; + defparam INT_RAMB.INITP_00 = INITP_00; + defparam INT_RAMB.INITP_01 = INITP_01; + defparam INT_RAMB.INITP_02 = INITP_02; + defparam INT_RAMB.INITP_03 = INITP_03; + defparam INT_RAMB.INITP_04 = INITP_04; + defparam INT_RAMB.INITP_05 = INITP_05; + defparam INT_RAMB.INITP_06 = INITP_06; + defparam INT_RAMB.INITP_07 = INITP_07; + defparam INT_RAMB.INITP_08 = INITP_08; + defparam INT_RAMB.INITP_09 = INITP_09; + defparam INT_RAMB.INITP_0A = INITP_0A; + defparam INT_RAMB.INITP_0B = INITP_0B; + defparam INT_RAMB.INITP_0C = INITP_0C; + defparam INT_RAMB.INITP_0D = INITP_0D; + defparam INT_RAMB.INITP_0E = INITP_0E; + defparam INT_RAMB.INITP_0F = INITP_0F; + + specify + + (CASCADEINLATA => DOA[0]) = (0, 0); + (CASCADEINREGA => DOA[0]) = (0, 0); + (CLKAL => DOA[0]) = (100, 100); + (CLKAL => DOA[1]) = (100, 100); + (CLKAL => DOA[2]) = (100, 100); + (CLKAL => DOA[3]) = (100, 100); + (CLKAL => DOA[4]) = (100, 100); + (CLKAL => DOA[5]) = (100, 100); + (CLKAL => DOA[6]) = (100, 100); + (CLKAL => DOA[7]) = (100, 100); + (CLKAL => DOA[8]) = (100, 100); + (CLKAL => DOA[9]) = (100, 100); + (CLKAL => DOA[10]) = (100, 100); + (CLKAL => DOA[11]) = (100, 100); + (CLKAL => DOA[12]) = (100, 100); + (CLKAL => DOA[13]) = (100, 100); + (CLKAL => DOA[14]) = (100, 100); + (CLKAL => DOA[15]) = (100, 100); + (CLKAL => DOA[16]) = (100, 100); + (CLKAL => DOA[17]) = (100, 100); + (CLKAL => DOA[18]) = (100, 100); + (CLKAL => DOA[19]) = (100, 100); + (CLKAL => DOA[20]) = (100, 100); + (CLKAL => DOA[21]) = (100, 100); + (CLKAL => DOA[22]) = (100, 100); + (CLKAL => DOA[23]) = (100, 100); + (CLKAL => DOA[24]) = (100, 100); + (CLKAL => DOA[25]) = (100, 100); + (CLKAL => DOA[26]) = (100, 100); + (CLKAL => DOA[27]) = (100, 100); + (CLKAL => DOA[28]) = (100, 100); + (CLKAL => DOA[29]) = (100, 100); + (CLKAL => DOA[30]) = (100, 100); + (CLKAL => DOA[31]) = (100, 100); + (CLKAL => DOPA[0]) = (100, 100); + (CLKAL => DOPA[1]) = (100, 100); + (CLKAL => DOPA[2]) = (100, 100); + (CLKAL => DOPA[3]) = (100, 100); + + (REGCLKAL => DOA[0]) = (100, 100); + (REGCLKAL => DOA[1]) = (100, 100); + (REGCLKAL => DOA[2]) = (100, 100); + (REGCLKAL => DOA[3]) = (100, 100); + (REGCLKAL => DOA[4]) = (100, 100); + (REGCLKAL => DOA[5]) = (100, 100); + (REGCLKAL => DOA[6]) = (100, 100); + (REGCLKAL => DOA[7]) = (100, 100); + (REGCLKAL => DOA[8]) = (100, 100); + (REGCLKAL => DOA[9]) = (100, 100); + (REGCLKAL => DOA[10]) = (100, 100); + (REGCLKAL => DOA[11]) = (100, 100); + (REGCLKAL => DOA[12]) = (100, 100); + (REGCLKAL => DOA[13]) = (100, 100); + (REGCLKAL => DOA[14]) = (100, 100); + (REGCLKAL => DOA[15]) = (100, 100); + (REGCLKAL => DOA[16]) = (100, 100); + (REGCLKAL => DOA[17]) = (100, 100); + (REGCLKAL => DOA[18]) = (100, 100); + (REGCLKAL => DOA[19]) = (100, 100); + (REGCLKAL => DOA[20]) = (100, 100); + (REGCLKAL => DOA[21]) = (100, 100); + (REGCLKAL => DOA[22]) = (100, 100); + (REGCLKAL => DOA[23]) = (100, 100); + (REGCLKAL => DOA[24]) = (100, 100); + (REGCLKAL => DOA[25]) = (100, 100); + (REGCLKAL => DOA[26]) = (100, 100); + (REGCLKAL => DOA[27]) = (100, 100); + (REGCLKAL => DOA[28]) = (100, 100); + (REGCLKAL => DOA[29]) = (100, 100); + (REGCLKAL => DOA[30]) = (100, 100); + (REGCLKAL => DOA[31]) = (100, 100); + (REGCLKAL => DOPA[0]) = (100, 100); + (REGCLKAL => DOPA[1]) = (100, 100); + (REGCLKAL => DOPA[2]) = (100, 100); + (REGCLKAL => DOPA[3]) = (100, 100); + + (CASCADEINLATB => DOB[0]) = (0, 0); + (CASCADEINREGB => DOB[0]) = (0, 0); + (CLKBL => DOB[0]) = (100, 100); + (CLKBL => DOB[1]) = (100, 100); + (CLKBL => DOB[2]) = (100, 100); + (CLKBL => DOB[3]) = (100, 100); + (CLKBL => DOB[4]) = (100, 100); + (CLKBL => DOB[5]) = (100, 100); + (CLKBL => DOB[6]) = (100, 100); + (CLKBL => DOB[7]) = (100, 100); + (CLKBL => DOB[8]) = (100, 100); + (CLKBL => DOB[9]) = (100, 100); + (CLKBL => DOB[10]) = (100, 100); + (CLKBL => DOB[11]) = (100, 100); + (CLKBL => DOB[12]) = (100, 100); + (CLKBL => DOB[13]) = (100, 100); + (CLKBL => DOB[14]) = (100, 100); + (CLKBL => DOB[15]) = (100, 100); + (CLKBL => DOB[16]) = (100, 100); + (CLKBL => DOB[17]) = (100, 100); + (CLKBL => DOB[18]) = (100, 100); + (CLKBL => DOB[19]) = (100, 100); + (CLKBL => DOB[20]) = (100, 100); + (CLKBL => DOB[21]) = (100, 100); + (CLKBL => DOB[22]) = (100, 100); + (CLKBL => DOB[23]) = (100, 100); + (CLKBL => DOB[24]) = (100, 100); + (CLKBL => DOB[25]) = (100, 100); + (CLKBL => DOB[26]) = (100, 100); + (CLKBL => DOB[27]) = (100, 100); + (CLKBL => DOB[28]) = (100, 100); + (CLKBL => DOB[29]) = (100, 100); + (CLKBL => DOB[30]) = (100, 100); + (CLKBL => DOB[31]) = (100, 100); + (CLKBL => DOPB[0]) = (100, 100); + (CLKBL => DOPB[1]) = (100, 100); + (CLKBL => DOPB[2]) = (100, 100); + (CLKBL => DOPB[3]) = (100, 100); + + (REGCLKBL => DOB[0]) = (100, 100); + (REGCLKBL => DOB[1]) = (100, 100); + (REGCLKBL => DOB[2]) = (100, 100); + (REGCLKBL => DOB[3]) = (100, 100); + (REGCLKBL => DOB[4]) = (100, 100); + (REGCLKBL => DOB[5]) = (100, 100); + (REGCLKBL => DOB[6]) = (100, 100); + (REGCLKBL => DOB[7]) = (100, 100); + (REGCLKBL => DOB[8]) = (100, 100); + (REGCLKBL => DOB[9]) = (100, 100); + (REGCLKBL => DOB[10]) = (100, 100); + (REGCLKBL => DOB[11]) = (100, 100); + (REGCLKBL => DOB[12]) = (100, 100); + (REGCLKBL => DOB[13]) = (100, 100); + (REGCLKBL => DOB[14]) = (100, 100); + (REGCLKBL => DOB[15]) = (100, 100); + (REGCLKBL => DOB[16]) = (100, 100); + (REGCLKBL => DOB[17]) = (100, 100); + (REGCLKBL => DOB[18]) = (100, 100); + (REGCLKBL => DOB[19]) = (100, 100); + (REGCLKBL => DOB[20]) = (100, 100); + (REGCLKBL => DOB[21]) = (100, 100); + (REGCLKBL => DOB[22]) = (100, 100); + (REGCLKBL => DOB[23]) = (100, 100); + (REGCLKBL => DOB[24]) = (100, 100); + (REGCLKBL => DOB[25]) = (100, 100); + (REGCLKBL => DOB[26]) = (100, 100); + (REGCLKBL => DOB[27]) = (100, 100); + (REGCLKBL => DOB[28]) = (100, 100); + (REGCLKBL => DOB[29]) = (100, 100); + (REGCLKBL => DOB[30]) = (100, 100); + (REGCLKBL => DOB[31]) = (100, 100); + (REGCLKBL => DOPB[0]) = (100, 100); + (REGCLKBL => DOPB[1]) = (100, 100); + (REGCLKBL => DOPB[2]) = (100, 100); + (REGCLKBL => DOPB[3]) = (100, 100); + + (CLKAL => CASCADEOUTLATA) = (100, 100); + (REGCLKAL => CASCADEOUTREGA) = (100, 100); + (CLKBL => CASCADEOUTLATB) = (100, 100); + (REGCLKBL => CASCADEOUTREGB) = (100, 100); + specparam PATHPULSE$ = 0; + + endspecify + +endmodule diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/RAMB4_S1.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/RAMB4_S1.v new file mode 100644 index 0000000..f920975 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/RAMB4_S1.v @@ -0,0 +1,277 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/RAMB4_S1.v,v 1.6 2005/03/14 22:54:42 wloo Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2005 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / 4K-Bit Data Single Port Block RAM +// /___/ /\ Filename : RAMB4_S1.v +// \ \ / \ Timestamp : Thu Mar 10 16:43:37 PST 2005 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// End Revision + +`ifdef legacy_model + +`timescale 1 ps / 1 ps + + +module RAMB4_S1 (DO, ADDR, CLK, DI, EN, RST, WE); + + parameter INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + + output [0:0] DO; + reg d0_out; + + input [11:0] ADDR; + input [0:0] DI; + input EN, CLK, WE, RST; + + reg [4095:0] mem; + reg [8:0] count; + + wire [11:0] addr_int; + wire [0:0] di_int; + wire en_int, clk_int, we_int, rst_int; + + tri0 GSR = glbl.GSR; + + always @(GSR) + if (GSR) + begin + assign d0_out = 0; + end + else + begin + deassign d0_out; + end + + buf b_do_out0 (DO[0], d0_out); + buf b_addr_0 (addr_int[0], ADDR[0]); + buf b_addr_1 (addr_int[1], ADDR[1]); + buf b_addr_2 (addr_int[2], ADDR[2]); + buf b_addr_3 (addr_int[3], ADDR[3]); + buf b_addr_4 (addr_int[4], ADDR[4]); + buf b_addr_5 (addr_int[5], ADDR[5]); + buf b_addr_6 (addr_int[6], ADDR[6]); + buf b_addr_7 (addr_int[7], ADDR[7]); + buf b_addr_8 (addr_int[8], ADDR[8]); + buf b_addr_9 (addr_int[9], ADDR[9]); + buf b_addr_10 (addr_int[10], ADDR[10]); + buf b_addr_11 (addr_int[11], ADDR[11]); + buf b_di_0 (di_int[0], DI[0]); + buf b_en (en_int, EN); + buf b_clk (clk_int, CLK); + buf b_we (we_int, WE); + buf b_rst (rst_int, RST); + + initial + begin + for (count = 0; count < 256; count = count + 1) + begin + mem[count] <= INIT_00[count]; + mem[256 * 1 + count] <= INIT_01[count]; + mem[256 * 2 + count] <= INIT_02[count]; + mem[256 * 3 + count] <= INIT_03[count]; + mem[256 * 4 + count] <= INIT_04[count]; + mem[256 * 5 + count] <= INIT_05[count]; + mem[256 * 6 + count] <= INIT_06[count]; + mem[256 * 7 + count] <= INIT_07[count]; + mem[256 * 8 + count] <= INIT_08[count]; + mem[256 * 9 + count] <= INIT_09[count]; + mem[256 * 10 + count] <= INIT_0A[count]; + mem[256 * 11 + count] <= INIT_0B[count]; + mem[256 * 12 + count] <= INIT_0C[count]; + mem[256 * 13 + count] <= INIT_0D[count]; + mem[256 * 14 + count] <= INIT_0E[count]; + mem[256 * 15 + count] <= INIT_0F[count]; + end + end + + always @(posedge clk_int) + begin + if (en_int == 1'b1) + if (rst_int == 1'b1) + begin + d0_out <= 0; + end + else + if (we_int == 1'b1) + begin + d0_out <= di_int[0]; + end + else + begin + d0_out <= mem[addr_int]; + end + end + + always @(posedge clk_int) + begin + if (en_int == 1'b1 && we_int == 1'b1) + begin + mem[addr_int] <= di_int[0]; + end + end + + specify + (CLK *> DO) = (100, 100); + endspecify + +endmodule + +`else + + +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/RAMB4_S1.v,v 1.6 2005/03/14 22:54:42 wloo Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2005 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Timing Simulation Library Component +// / / 16K-Bit Data and 2K-Bit Parity Single Port Block RAM +// /___/ /\ Filename : RAMB4_S1.v +// \ \ / \ Timestamp : Thu Mar 10 16:44:01 PST 2005 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 03/10/05 - Initialized outputs. +// End Revision + +`timescale 1 ps/1 ps + +module RAMB4_S1 (DO, ADDR, CLK, DI, EN, RST, WE); + + parameter INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + + output [0:0] DO; + + input [11:0] ADDR; + input [0:0] DI; + input EN, CLK, WE, RST; + + reg [0:0] do_out = 0; + + reg [0:0] mem [4095:0]; + + reg [8:0] count; + + wire [11:0] addr_int; + wire [0:0] di_int; + wire en_int, clk_int, we_int, rst_int; + + wire di_enable = en_int && we_int; + + tri0 GSR = glbl.GSR; + wire gsr_int; + + buf b_gsr (gsr_int, GSR); + + buf b_do [0:0] (DO, do_out); + buf b_addr [11:0] (addr_int, ADDR); + buf b_di [0:0] (di_int, DI); + buf b_en (en_int, EN); + buf b_clk (clk_int, CLK); + buf b_rst (rst_int, RST); + buf b_we (we_int, WE); + + + always @(gsr_int) + if (gsr_int) begin + assign do_out = 0; + end + else begin + deassign do_out; + end + + + initial begin + + for (count = 0; count < 256; count = count + 1) begin + mem[count] = INIT_00[(count * 1) +: 1]; + mem[256 * 1 + count] = INIT_01[(count * 1) +: 1]; + mem[256 * 2 + count] = INIT_02[(count * 1) +: 1]; + mem[256 * 3 + count] = INIT_03[(count * 1) +: 1]; + mem[256 * 4 + count] = INIT_04[(count * 1) +: 1]; + mem[256 * 5 + count] = INIT_05[(count * 1) +: 1]; + mem[256 * 6 + count] = INIT_06[(count * 1) +: 1]; + mem[256 * 7 + count] = INIT_07[(count * 1) +: 1]; + mem[256 * 8 + count] = INIT_08[(count * 1) +: 1]; + mem[256 * 9 + count] = INIT_09[(count * 1) +: 1]; + mem[256 * 10 + count] = INIT_0A[(count * 1) +: 1]; + mem[256 * 11 + count] = INIT_0B[(count * 1) +: 1]; + mem[256 * 12 + count] = INIT_0C[(count * 1) +: 1]; + mem[256 * 13 + count] = INIT_0D[(count * 1) +: 1]; + mem[256 * 14 + count] = INIT_0E[(count * 1) +: 1]; + mem[256 * 15 + count] = INIT_0F[(count * 1) +: 1]; + end + + end // initial begin + + + always @(posedge clk_int) begin + + if (en_int == 1'b1) begin + + if (rst_int == 1'b1) + do_out <= #100 0; + + else + if (we_int == 1'b1) + do_out <= #100 di_int; + + else + do_out <= #100 mem[addr_int]; + + // memory + if (we_int == 1'b1) + mem[addr_int] <= di_int; + + end + end + + +endmodule + +`endif diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/RAMB4_S16.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/RAMB4_S16.v new file mode 100644 index 0000000..9b72f32 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/RAMB4_S16.v @@ -0,0 +1,393 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/RAMB4_S16.v,v 1.6 2005/03/14 22:54:42 wloo Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2005 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / 4K-Bit Data Single Port Block RAM +// /___/ /\ Filename : RAMB4_S16.v +// \ \ / \ Timestamp : Thu Mar 10 16:43:37 PST 2005 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// End Revision + +`ifdef legacy_model + +`timescale 1 ps / 1 ps + + +module RAMB4_S16 (DO, ADDR, CLK, DI, EN, RST, WE); + + parameter INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + + output [15:0] DO; + reg d0_out, d1_out, d2_out, d3_out, d4_out, d5_out, d6_out, d7_out, d8_out, d9_out, d10_out, d11_out, d12_out, d13_out, d14_out, d15_out; + + input [7:0] ADDR; + input [15:0] DI; + input EN, CLK, WE, RST; + + reg [4095:0] mem; + reg [8:0] count; + + wire [7:0] addr_int; + wire [15:0] di_int; + wire en_int, clk_int, we_int, rst_int; + + tri0 GSR = glbl.GSR; + + always @(GSR) + if (GSR) + begin + assign d0_out = 0; + assign d1_out = 0; + assign d2_out = 0; + assign d3_out = 0; + assign d4_out = 0; + assign d5_out = 0; + assign d6_out = 0; + assign d7_out = 0; + assign d8_out = 0; + assign d9_out = 0; + assign d10_out = 0; + assign d11_out = 0; + assign d12_out = 0; + assign d13_out = 0; + assign d14_out = 0; + assign d15_out = 0; + end + else + begin + deassign d0_out; + deassign d1_out; + deassign d2_out; + deassign d3_out; + deassign d4_out; + deassign d5_out; + deassign d6_out; + deassign d7_out; + deassign d8_out; + deassign d9_out; + deassign d10_out; + deassign d11_out; + deassign d12_out; + deassign d13_out; + deassign d14_out; + deassign d15_out; + end + + buf b_do_out0 (DO[0], d0_out); + buf b_do_out1 (DO[1], d1_out); + buf b_do_out2 (DO[2], d2_out); + buf b_do_out3 (DO[3], d3_out); + buf b_do_out4 (DO[4], d4_out); + buf b_do_out5 (DO[5], d5_out); + buf b_do_out6 (DO[6], d6_out); + buf b_do_out7 (DO[7], d7_out); + buf b_do_out8 (DO[8], d8_out); + buf b_do_out9 (DO[9], d9_out); + buf b_do_out10 (DO[10], d10_out); + buf b_do_out11 (DO[11], d11_out); + buf b_do_out12 (DO[12], d12_out); + buf b_do_out13 (DO[13], d13_out); + buf b_do_out14 (DO[14], d14_out); + buf b_do_out15 (DO[15], d15_out); + buf b_addr_0 (addr_int[0], ADDR[0]); + buf b_addr_1 (addr_int[1], ADDR[1]); + buf b_addr_2 (addr_int[2], ADDR[2]); + buf b_addr_3 (addr_int[3], ADDR[3]); + buf b_addr_4 (addr_int[4], ADDR[4]); + buf b_addr_5 (addr_int[5], ADDR[5]); + buf b_addr_6 (addr_int[6], ADDR[6]); + buf b_addr_7 (addr_int[7], ADDR[7]); + buf b_di_0 (di_int[0], DI[0]); + buf b_di_1 (di_int[1], DI[1]); + buf b_di_2 (di_int[2], DI[2]); + buf b_di_3 (di_int[3], DI[3]); + buf b_di_4 (di_int[4], DI[4]); + buf b_di_5 (di_int[5], DI[5]); + buf b_di_6 (di_int[6], DI[6]); + buf b_di_7 (di_int[7], DI[7]); + buf b_di_8 (di_int[8], DI[8]); + buf b_di_9 (di_int[9], DI[9]); + buf b_di_10 (di_int[10], DI[10]); + buf b_di_11 (di_int[11], DI[11]); + buf b_di_12 (di_int[12], DI[12]); + buf b_di_13 (di_int[13], DI[13]); + buf b_di_14 (di_int[14], DI[14]); + buf b_di_15 (di_int[15], DI[15]); + buf b_en (en_int, EN); + buf b_clk (clk_int, CLK); + buf b_we (we_int, WE); + buf b_rst (rst_int, RST); + + initial + begin + for (count = 0; count < 256; count = count + 1) + begin + mem[count] <= INIT_00[count]; + mem[256 * 1 + count] <= INIT_01[count]; + mem[256 * 2 + count] <= INIT_02[count]; + mem[256 * 3 + count] <= INIT_03[count]; + mem[256 * 4 + count] <= INIT_04[count]; + mem[256 * 5 + count] <= INIT_05[count]; + mem[256 * 6 + count] <= INIT_06[count]; + mem[256 * 7 + count] <= INIT_07[count]; + mem[256 * 8 + count] <= INIT_08[count]; + mem[256 * 9 + count] <= INIT_09[count]; + mem[256 * 10 + count] <= INIT_0A[count]; + mem[256 * 11 + count] <= INIT_0B[count]; + mem[256 * 12 + count] <= INIT_0C[count]; + mem[256 * 13 + count] <= INIT_0D[count]; + mem[256 * 14 + count] <= INIT_0E[count]; + mem[256 * 15 + count] <= INIT_0F[count]; + end + end + + always @(posedge clk_int) + begin + if (en_int == 1'b1) + if (rst_int == 1'b1) + begin + d0_out <= 0; + d1_out <= 0; + d2_out <= 0; + d3_out <= 0; + d4_out <= 0; + d5_out <= 0; + d6_out <= 0; + d7_out <= 0; + d8_out <= 0; + d9_out <= 0; + d10_out <= 0; + d11_out <= 0; + d12_out <= 0; + d13_out <= 0; + d14_out <= 0; + d15_out <= 0; + end + else + if (we_int == 1'b1) + begin + d0_out <= di_int[0]; + d1_out <= di_int[1]; + d2_out <= di_int[2]; + d3_out <= di_int[3]; + d4_out <= di_int[4]; + d5_out <= di_int[5]; + d6_out <= di_int[6]; + d7_out <= di_int[7]; + d8_out <= di_int[8]; + d9_out <= di_int[9]; + d10_out <= di_int[10]; + d11_out <= di_int[11]; + d12_out <= di_int[12]; + d13_out <= di_int[13]; + d14_out <= di_int[14]; + d15_out <= di_int[15]; + end + else + begin + d0_out <= mem[addr_int * 16]; + d1_out <= mem[addr_int * 16 + 1]; + d2_out <= mem[addr_int * 16 + 2]; + d3_out <= mem[addr_int * 16 + 3]; + d4_out <= mem[addr_int * 16 + 4]; + d5_out <= mem[addr_int * 16 + 5]; + d6_out <= mem[addr_int * 16 + 6]; + d7_out <= mem[addr_int * 16 + 7]; + d8_out <= mem[addr_int * 16 + 8]; + d9_out <= mem[addr_int * 16 + 9]; + d10_out <= mem[addr_int * 16 + 10]; + d11_out <= mem[addr_int * 16 + 11]; + d12_out <= mem[addr_int * 16 + 12]; + d13_out <= mem[addr_int * 16 + 13]; + d14_out <= mem[addr_int * 16 + 14]; + d15_out <= mem[addr_int * 16 + 15]; + end + end + + always @(posedge clk_int) + begin + if (en_int == 1'b1 && we_int == 1'b1) + begin + mem[addr_int * 16] <= di_int[0]; + mem[addr_int * 16 + 1] <= di_int[1]; + mem[addr_int * 16 + 2] <= di_int[2]; + mem[addr_int * 16 + 3] <= di_int[3]; + mem[addr_int * 16 + 4] <= di_int[4]; + mem[addr_int * 16 + 5] <= di_int[5]; + mem[addr_int * 16 + 6] <= di_int[6]; + mem[addr_int * 16 + 7] <= di_int[7]; + mem[addr_int * 16 + 8] <= di_int[8]; + mem[addr_int * 16 + 9] <= di_int[9]; + mem[addr_int * 16 + 10] <= di_int[10]; + mem[addr_int * 16 + 11] <= di_int[11]; + mem[addr_int * 16 + 12] <= di_int[12]; + mem[addr_int * 16 + 13] <= di_int[13]; + mem[addr_int * 16 + 14] <= di_int[14]; + mem[addr_int * 16 + 15] <= di_int[15]; + end + end + + specify + (CLK *> DO) = (100, 100); + endspecify + +endmodule + +`else + + +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/RAMB4_S16.v,v 1.6 2005/03/14 22:54:42 wloo Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2005 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Timing Simulation Library Component +// / / 16K-Bit Data and 2K-Bit Parity Single Port Block RAM +// /___/ /\ Filename : RAMB4_S16.v +// \ \ / \ Timestamp : Thu Mar 10 16:44:01 PST 2005 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 03/10/05 - Initialized outputs. +// End Revision + +`timescale 1 ps/1 ps + +module RAMB4_S16 (DO, ADDR, CLK, DI, EN, RST, WE); + + parameter INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + + output [15:0] DO; + + input [7:0] ADDR; + input [15:0] DI; + input EN, CLK, WE, RST; + + reg [15:0] do_out = 0; + + reg [15:0] mem [255:0]; + + reg [8:0] count; + + wire [7:0] addr_int; + wire [15:0] di_int; + wire en_int, clk_int, we_int, rst_int; + + wire di_enable = en_int && we_int; + + tri0 GSR = glbl.GSR; + wire gsr_int; + + buf b_gsr (gsr_int, GSR); + + buf b_do [15:0] (DO, do_out); + buf b_addr [7:0] (addr_int, ADDR); + buf b_di [15:0] (di_int, DI); + buf b_en (en_int, EN); + buf b_clk (clk_int, CLK); + buf b_rst (rst_int, RST); + buf b_we (we_int, WE); + + + always @(gsr_int) + if (gsr_int) begin + assign do_out = 0; + end + else begin + deassign do_out; + end + + + initial begin + + for (count = 0; count < 16; count = count + 1) begin + mem[count] = INIT_00[(count * 16) +: 16]; + mem[16 * 1 + count] = INIT_01[(count * 16) +: 16]; + mem[16 * 2 + count] = INIT_02[(count * 16) +: 16]; + mem[16 * 3 + count] = INIT_03[(count * 16) +: 16]; + mem[16 * 4 + count] = INIT_04[(count * 16) +: 16]; + mem[16 * 5 + count] = INIT_05[(count * 16) +: 16]; + mem[16 * 6 + count] = INIT_06[(count * 16) +: 16]; + mem[16 * 7 + count] = INIT_07[(count * 16) +: 16]; + mem[16 * 8 + count] = INIT_08[(count * 16) +: 16]; + mem[16 * 9 + count] = INIT_09[(count * 16) +: 16]; + mem[16 * 10 + count] = INIT_0A[(count * 16) +: 16]; + mem[16 * 11 + count] = INIT_0B[(count * 16) +: 16]; + mem[16 * 12 + count] = INIT_0C[(count * 16) +: 16]; + mem[16 * 13 + count] = INIT_0D[(count * 16) +: 16]; + mem[16 * 14 + count] = INIT_0E[(count * 16) +: 16]; + mem[16 * 15 + count] = INIT_0F[(count * 16) +: 16]; + end + + end // initial begin + + + always @(posedge clk_int) begin + + if (en_int == 1'b1) begin + + if (rst_int == 1'b1) + do_out <= #100 0; + + else + if (we_int == 1'b1) + do_out <= #100 di_int; + + else + do_out <= #100 mem[addr_int]; + + // memory + if (we_int == 1'b1) + mem[addr_int] <= di_int; + + end + end + + +endmodule + +`endif diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/RAMB4_S16_S16.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/RAMB4_S16_S16.v new file mode 100644 index 0000000..2922279 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/RAMB4_S16_S16.v @@ -0,0 +1,1181 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/RAMB4_S16_S16.v,v 1.9 2007/02/22 01:58:06 wloo Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2005 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / 4K-Bit Data Dual Port Block RAM +// /___/ /\ Filename : RAMB4_S16_S16.v +// \ \ / \ Timestamp : Thu Mar 10 16:43:37 PST 2005 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// End Revision + +`ifdef legacy_model + +`timescale 1 ps / 1 ps + +module RAMB4_S16_S16 (DOA, DOB, ADDRA, ADDRB, CLKA, CLKB, DIA, DIB, ENA, ENB, RSTA, RSTB, WEA, WEB); + + parameter SIM_COLLISION_CHECK = "ALL"; + localparam SETUP_ALL = 100; + + parameter INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + + output [15:0] DOA; + reg [15:0] doa_out; + wire doa_out0, doa_out1, doa_out2, doa_out3, doa_out4, doa_out5, doa_out6, doa_out7, doa_out8, doa_out9, doa_out10, doa_out11, doa_out12, doa_out13, doa_out14, doa_out15; + + input [7:0] ADDRA; + input [15:0] DIA; + input ENA, CLKA, WEA, RSTA; + + output [15:0] DOB; + reg [15:0] dob_out; + wire dob_out0, dob_out1, dob_out2, dob_out3, dob_out4, dob_out5, dob_out6, dob_out7, dob_out8, dob_out9, dob_out10, dob_out11, dob_out12, dob_out13, dob_out14, dob_out15; + + input [7:0] ADDRB; + input [15:0] DIB; + input ENB, CLKB, WEB, RSTB; + + reg [4095:0] mem; + reg [8:0] count; + + reg [5:0] mi, mj, ai, aj, bi, bj, ci, cj, di, dj, ei, ej, fi, fj; + + wire [7:0] addra_int; + reg [7:0] addra_reg; + wire [15:0] dia_int; + wire ena_int, clka_int, wea_int, rsta_int; + reg ena_reg, wea_reg, rsta_reg; + wire [7:0] addrb_int; + reg [7:0] addrb_reg; + wire [15:0] dib_int; + wire enb_int, clkb_int, web_int, rstb_int; + reg enb_reg, web_reg, rstb_reg; + + time time_clka, time_clkb; + time time_clka_clkb; + time time_clkb_clka; + + reg setup_all_a_b; + reg setup_all_b_a; + reg setup_zero; + reg [1:0] data_collision, data_collision_a_b, data_collision_b_a; + reg memory_collision, memory_collision_a_b, memory_collision_b_a; + reg address_collision, address_collision_a_b, address_collision_b_a; + reg change_clka; + reg change_clkb; + + wire [11:0] mem_addra_int; + wire [11:0] mem_addra_reg; + wire [11:0] mem_addrb_int; + wire [11:0] mem_addrb_reg; + + tri0 GSR = glbl.GSR; + + always @(GSR) + if (GSR) begin + assign doa_out = 0; + end + else begin + deassign doa_out; + end + + always @(GSR) + if (GSR) begin + assign dob_out = 0; + end + else begin + deassign dob_out; + end + + buf b_doa_out0 (doa_out0, doa_out[0]); + buf b_doa_out1 (doa_out1, doa_out[1]); + buf b_doa_out2 (doa_out2, doa_out[2]); + buf b_doa_out3 (doa_out3, doa_out[3]); + buf b_doa_out4 (doa_out4, doa_out[4]); + buf b_doa_out5 (doa_out5, doa_out[5]); + buf b_doa_out6 (doa_out6, doa_out[6]); + buf b_doa_out7 (doa_out7, doa_out[7]); + buf b_doa_out8 (doa_out8, doa_out[8]); + buf b_doa_out9 (doa_out9, doa_out[9]); + buf b_doa_out10 (doa_out10, doa_out[10]); + buf b_doa_out11 (doa_out11, doa_out[11]); + buf b_doa_out12 (doa_out12, doa_out[12]); + buf b_doa_out13 (doa_out13, doa_out[13]); + buf b_doa_out14 (doa_out14, doa_out[14]); + buf b_doa_out15 (doa_out15, doa_out[15]); + buf b_dob_out0 (dob_out0, dob_out[0]); + buf b_dob_out1 (dob_out1, dob_out[1]); + buf b_dob_out2 (dob_out2, dob_out[2]); + buf b_dob_out3 (dob_out3, dob_out[3]); + buf b_dob_out4 (dob_out4, dob_out[4]); + buf b_dob_out5 (dob_out5, dob_out[5]); + buf b_dob_out6 (dob_out6, dob_out[6]); + buf b_dob_out7 (dob_out7, dob_out[7]); + buf b_dob_out8 (dob_out8, dob_out[8]); + buf b_dob_out9 (dob_out9, dob_out[9]); + buf b_dob_out10 (dob_out10, dob_out[10]); + buf b_dob_out11 (dob_out11, dob_out[11]); + buf b_dob_out12 (dob_out12, dob_out[12]); + buf b_dob_out13 (dob_out13, dob_out[13]); + buf b_dob_out14 (dob_out14, dob_out[14]); + buf b_dob_out15 (dob_out15, dob_out[15]); + buf b_doa0 (DOA[0], doa_out0); + buf b_doa1 (DOA[1], doa_out1); + buf b_doa2 (DOA[2], doa_out2); + buf b_doa3 (DOA[3], doa_out3); + buf b_doa4 (DOA[4], doa_out4); + buf b_doa5 (DOA[5], doa_out5); + buf b_doa6 (DOA[6], doa_out6); + buf b_doa7 (DOA[7], doa_out7); + buf b_doa8 (DOA[8], doa_out8); + buf b_doa9 (DOA[9], doa_out9); + buf b_doa10 (DOA[10], doa_out10); + buf b_doa11 (DOA[11], doa_out11); + buf b_doa12 (DOA[12], doa_out12); + buf b_doa13 (DOA[13], doa_out13); + buf b_doa14 (DOA[14], doa_out14); + buf b_doa15 (DOA[15], doa_out15); + buf b_dob0 (DOB[0], dob_out0); + buf b_dob1 (DOB[1], dob_out1); + buf b_dob2 (DOB[2], dob_out2); + buf b_dob3 (DOB[3], dob_out3); + buf b_dob4 (DOB[4], dob_out4); + buf b_dob5 (DOB[5], dob_out5); + buf b_dob6 (DOB[6], dob_out6); + buf b_dob7 (DOB[7], dob_out7); + buf b_dob8 (DOB[8], dob_out8); + buf b_dob9 (DOB[9], dob_out9); + buf b_dob10 (DOB[10], dob_out10); + buf b_dob11 (DOB[11], dob_out11); + buf b_dob12 (DOB[12], dob_out12); + buf b_dob13 (DOB[13], dob_out13); + buf b_dob14 (DOB[14], dob_out14); + buf b_dob15 (DOB[15], dob_out15); + buf b_addra_0 (addra_int[0], ADDRA[0]); + buf b_addra_1 (addra_int[1], ADDRA[1]); + buf b_addra_2 (addra_int[2], ADDRA[2]); + buf b_addra_3 (addra_int[3], ADDRA[3]); + buf b_addra_4 (addra_int[4], ADDRA[4]); + buf b_addra_5 (addra_int[5], ADDRA[5]); + buf b_addra_6 (addra_int[6], ADDRA[6]); + buf b_addra_7 (addra_int[7], ADDRA[7]); + buf b_dia_0 (dia_int[0], DIA[0]); + buf b_dia_1 (dia_int[1], DIA[1]); + buf b_dia_2 (dia_int[2], DIA[2]); + buf b_dia_3 (dia_int[3], DIA[3]); + buf b_dia_4 (dia_int[4], DIA[4]); + buf b_dia_5 (dia_int[5], DIA[5]); + buf b_dia_6 (dia_int[6], DIA[6]); + buf b_dia_7 (dia_int[7], DIA[7]); + buf b_dia_8 (dia_int[8], DIA[8]); + buf b_dia_9 (dia_int[9], DIA[9]); + buf b_dia_10 (dia_int[10], DIA[10]); + buf b_dia_11 (dia_int[11], DIA[11]); + buf b_dia_12 (dia_int[12], DIA[12]); + buf b_dia_13 (dia_int[13], DIA[13]); + buf b_dia_14 (dia_int[14], DIA[14]); + buf b_dia_15 (dia_int[15], DIA[15]); + buf b_clka (clka_int, CLKA); + buf b_ena (ena_int, ENA); + buf b_rsta (rsta_int, RSTA); + buf b_wea (wea_int, WEA); + buf b_addrb_0 (addrb_int[0], ADDRB[0]); + buf b_addrb_1 (addrb_int[1], ADDRB[1]); + buf b_addrb_2 (addrb_int[2], ADDRB[2]); + buf b_addrb_3 (addrb_int[3], ADDRB[3]); + buf b_addrb_4 (addrb_int[4], ADDRB[4]); + buf b_addrb_5 (addrb_int[5], ADDRB[5]); + buf b_addrb_6 (addrb_int[6], ADDRB[6]); + buf b_addrb_7 (addrb_int[7], ADDRB[7]); + buf b_dib_0 (dib_int[0], DIB[0]); + buf b_dib_1 (dib_int[1], DIB[1]); + buf b_dib_2 (dib_int[2], DIB[2]); + buf b_dib_3 (dib_int[3], DIB[3]); + buf b_dib_4 (dib_int[4], DIB[4]); + buf b_dib_5 (dib_int[5], DIB[5]); + buf b_dib_6 (dib_int[6], DIB[6]); + buf b_dib_7 (dib_int[7], DIB[7]); + buf b_dib_8 (dib_int[8], DIB[8]); + buf b_dib_9 (dib_int[9], DIB[9]); + buf b_dib_10 (dib_int[10], DIB[10]); + buf b_dib_11 (dib_int[11], DIB[11]); + buf b_dib_12 (dib_int[12], DIB[12]); + buf b_dib_13 (dib_int[13], DIB[13]); + buf b_dib_14 (dib_int[14], DIB[14]); + buf b_dib_15 (dib_int[15], DIB[15]); + buf b_clkb (clkb_int, CLKB); + buf b_enb (enb_int, ENB); + buf b_rstb (rstb_int, RSTB); + buf b_web (web_int, WEB); + + initial begin + for (count = 0; count < 256; count = count + 1) begin + mem[count] <= INIT_00[count]; + mem[256 * 1 + count] <= INIT_01[count]; + mem[256 * 2 + count] <= INIT_02[count]; + mem[256 * 3 + count] <= INIT_03[count]; + mem[256 * 4 + count] <= INIT_04[count]; + mem[256 * 5 + count] <= INIT_05[count]; + mem[256 * 6 + count] <= INIT_06[count]; + mem[256 * 7 + count] <= INIT_07[count]; + mem[256 * 8 + count] <= INIT_08[count]; + mem[256 * 9 + count] <= INIT_09[count]; + mem[256 * 10 + count] <= INIT_0A[count]; + mem[256 * 11 + count] <= INIT_0B[count]; + mem[256 * 12 + count] <= INIT_0C[count]; + mem[256 * 13 + count] <= INIT_0D[count]; + mem[256 * 14 + count] <= INIT_0E[count]; + mem[256 * 15 + count] <= INIT_0F[count]; + end + address_collision <= 0; + address_collision_a_b <= 0; + address_collision_b_a <= 0; + change_clka <= 0; + change_clkb <= 0; + data_collision <= 0; + data_collision_a_b <= 0; + data_collision_b_a <= 0; + memory_collision <= 0; + memory_collision_a_b <= 0; + memory_collision_b_a <= 0; + setup_all_a_b <= 0; + setup_all_b_a <= 0; + setup_zero <= 0; + end + + assign mem_addra_int = addra_int * 16; + assign mem_addra_reg = addra_reg * 16; + assign mem_addrb_int = addrb_int * 16; + assign mem_addrb_reg = addrb_reg * 16; + + + initial begin + + case (SIM_COLLISION_CHECK) + + "NONE" : begin + assign setup_all_a_b = 1'b0; + assign setup_all_b_a = 1'b0; + assign setup_zero = 1'b0; + assign address_collision = 1'b0; + assign address_collision_a_b = 1'b0; + assign address_collision_b_a = 1'b0; + end + "WARNING_ONLY" : begin + assign data_collision = 2'b00; + assign data_collision_a_b = 2'b00; + assign data_collision_b_a = 2'b00; + assign memory_collision = 1'b0; + assign memory_collision_a_b = 1'b0; + assign memory_collision_b_a = 1'b0; + end + "GENERATE_X_ONLY" : begin + assign address_collision = 1'b0; + assign address_collision_a_b = 1'b0; + assign address_collision_b_a = 1'b0; + end + "ALL" : ; + default : begin + $display("Attribute Syntax Error : The Attribute SIM_COLLISION_CHECK on RAMB4_S16_S16 instance %m is set to %s. Legal values for this attribute are ALL, NONE, WARNING_ONLY or GENERATE_X_ONLY.", SIM_COLLISION_CHECK); + $finish; + end + + endcase // case(SIM_COLLISION_CHECK) + + end // initial begin + + + always @(posedge clka_int) begin + time_clka = $time; + #0 time_clkb_clka = time_clka - time_clkb; + change_clka = ~change_clka; + end + + always @(posedge clkb_int) begin + time_clkb = $time; + #0 time_clka_clkb = time_clkb - time_clka; + change_clkb = ~change_clkb; + end + + always @(change_clkb) begin + if ((0 < time_clka_clkb) && (time_clka_clkb < SETUP_ALL)) + setup_all_a_b = 1; + end + + always @(change_clka) begin + if ((0 < time_clkb_clka) && (time_clkb_clka < SETUP_ALL)) + setup_all_b_a = 1; + end + + always @(change_clkb or change_clka) begin + if ((time_clkb_clka == 0) && (time_clka_clkb == 0)) + setup_zero = 1; + end + + always @(posedge setup_zero) begin + if ((ena_int == 1) && (wea_int == 1) && + (enb_int == 1) && (web_int == 1)) + memory_collision <= 1; + end + + always @(posedge setup_all_a_b) begin + if ((ena_reg == 1) && (enb_int == 1)) begin + case ({wea_reg, web_int}) + 6'b11 : begin data_collision_a_b <= 2'b11; display_all_a_b; end + 6'b01 : begin data_collision_a_b <= 2'b10; display_all_a_b; end + 6'b10 : begin data_collision_a_b <= 2'b01; display_all_a_b; end + endcase + end + setup_all_a_b <= 0; + end + + task display_all_a_b; + begin + address_collision_a_b = 1'b0; + for (ci = 0; ci < 16; ci = ci + 16) begin + if ((mem_addra_reg) == (mem_addrb_int + ci)) begin + address_collision_a_b = 1'b1; + end + end + if (address_collision_a_b == 1'b1) + + if (({wea_reg, web_int}) == 2'b11) + $display("Memory Collision Error on RAMB4_S16_S16:%m at simulation time %.3f ns\nA write was requested to the same address simultaneously at both Port A and Port B of the RAM. The contents written to the RAM at address location %h (hex) of Port A and address location %h (hex) of Port B are unknown.", $time/1000.0, addra_int, addrb_int); + + else if (({wea_reg, web_int}) == 2'b01) + $display("Memory Collision Error on RAMB4_S16_S16:%m at simulation time %.3f ns\nA read was performed on address %h (hex) of Port A while a write was requested to the same address on Port B. The write will be successful however the read value on Port A is unknown until the next CLKA cycle.", $time/1000.0, addra_int); + + else if (({wea_reg, web_int}) == 2'b10) + $display("Memory Collision Error on RAMB4_S16_S16:%m at simulation time %.3f ns\nA read was performed on address %h (hex) of Port B while a write was requested to the same address on Port A. The write will be successful however the read value on Port B is unknown until the next CLKB cycle.", $time/1000.0, addrb_int); + + end + endtask + + always @(posedge setup_all_b_a) begin + if ((ena_int == 1) && (enb_reg == 1)) begin + case ({wea_int, web_reg}) + 6'b11 : begin data_collision_b_a <= 2'b11; display_all_b_a; end + 6'b01 : begin data_collision_b_a <= 2'b10; display_all_b_a; end + 6'b10 : begin data_collision_b_a <= 2'b01; display_all_b_a; end + endcase + end + setup_all_b_a <= 0; + end + + task display_all_b_a; + begin + address_collision_b_a = 1'b0; + for (ci = 0; ci < 16; ci = ci + 16) begin + if ((mem_addra_int) == (mem_addrb_reg + ci)) begin + address_collision_b_a = 1'b1; + end + end + if (address_collision_b_a == 1'b1) + + if (({wea_int, web_reg}) == 2'b11) + $display("Memory Collision Error on RAMB4_S16_S16:%m at simulation time %.3f ns\nA write was requested to the same address simultaneously at both Port A and Port B of the RAM. The contents written to the RAM at address location %h (hex) of Port A and address location %h (hex) of Port B are unknown.", $time/1000.0, addra_int, addrb_int); + + else if (({wea_int, web_reg}) == 2'b01) + $display("Memory Collision Error on RAMB4_S16_S16:%m at simulation time %.3f ns\nA read was performed on address %h (hex) of Port A while a write was requested to the same address on Port B. The write will be successful however the read value on Port A is unknown until the next CLKA cycle.", $time/1000.0, addra_int); + + else if (({wea_int, web_reg}) == 2'b10) + $display("Memory Collision Error on RAMB4_S16_S16:%m at simulation time %.3f ns\nA read was performed on address %h (hex) of Port B while a write was requested to the same address on Port A. The write will be successful however the read value on Port B is unknown until the next CLKB cycle.", $time/1000.0, addrb_int); + + end + endtask + + always @(posedge setup_zero) begin + if ((ena_int == 1) && (enb_int == 1)) begin + case ({wea_int, web_int}) + 6'b11 : begin data_collision <= 2'b11; display_zero; end + 6'b01 : begin data_collision <= 2'b10; display_zero; end + 6'b10 : begin data_collision <= 2'b01; display_zero; end + endcase + end + setup_zero <= 0; + end + + task display_zero; + begin + address_collision = 1'b0; + for (ci = 0; ci < 16; ci = ci + 16) begin + if ((mem_addra_int) == (mem_addrb_int + ci)) begin + address_collision = 1'b1; + end + end + if (address_collision == 1'b1) + + if (({wea_int, web_int}) == 2'b11) + $display("Memory Collision Error on RAMB4_S16_S16:%m at simulation time %.3f ns\nA write was requested to the same address simultaneously at both Port A and Port B of the RAM. The contents written to the RAM at address location %h (hex) of Port A and address location %h (hex) of Port B are unknown.", $time/1000.0, addra_int, addrb_int); + + else if (({wea_int, web_int}) == 2'b01) + $display("Memory Collision Error on RAMB4_S16_S16:%m at simulation time %.3f ns\nA read was performed on address %h (hex) of Port A while a write was requested to the same address on Port B. The write will be successful however the read value on Port A is unknown until the next CLKA cycle.", $time/1000.0, addra_int); + + else if (({wea_int, web_int}) == 2'b10) + $display("Memory Collision Error on RAMB4_S16_S16:%m at simulation time %.3f ns\nA read was performed on address %h (hex) of Port B while a write was requested to the same address on Port A. The write will be successful however the read value on Port B is unknown until the next CLKB cycle.", $time/1000.0, addrb_int); + + end + endtask + + always @(posedge clka_int) begin + addra_reg <= addra_int; + ena_reg <= ena_int; + rsta_reg <= rsta_int; + wea_reg <= wea_int; + end + + always @(posedge clkb_int) begin + addrb_reg <= addrb_int; + enb_reg <= enb_int; + rstb_reg <= rstb_int; + web_reg <= web_int; + end + + // Data + always @(posedge memory_collision) begin + for (mi = 0; mi < 16; mi = mi + 16) begin + if ((mem_addra_int) == (mem_addrb_int + mi)) begin + for (mj = 0; mj < 16; mj = mj + 1) begin + mem[mem_addrb_int + mi + mj] <= 1'bX; + end + end + end + memory_collision <= 0; + end + + always @(posedge memory_collision_a_b) begin + for (mi = 0; mi < 16; mi = mi + 16) begin + if ((mem_addra_reg) == (mem_addrb_int + mi)) begin + for (mj = 0; mj < 16; mj = mj + 1) begin + mem[mem_addrb_int + mi + mj] <= 1'bX; + end + end + end + memory_collision_a_b <= 0; + end + + always @(posedge memory_collision_b_a) begin + for (mi = 0; mi < 16; mi = mi + 16) begin + if ((mem_addra_int) == (mem_addrb_reg + mi)) begin + for (mj = 0; mj < 16; mj = mj + 1) begin + mem[mem_addrb_reg + mi + mj] <= 1'bX; + end + end + end + memory_collision_b_a <= 0; + end + + always @(posedge data_collision[1]) begin + if (rsta_int == 0) begin + for (ai = 0; ai < 16; ai = ai + 16) begin + if ((mem_addra_int) == (mem_addrb_int + ai)) begin + doa_out <= 16'bX; + end + end + end + data_collision[1] <= 0; + end + + always @(posedge data_collision[0]) begin + if (rstb_int == 0) begin + for (bi = 0; bi < 16; bi = bi + 16) begin + if ((mem_addra_int) == (mem_addrb_int + bi)) begin + for (bj = 0; bj < 16; bj = bj + 1) begin + dob_out[bi + bj] <= 1'bX; + end + end + end + end + data_collision[0] <= 0; + end + + always @(posedge data_collision_a_b[1]) begin + if (rsta_reg == 0) begin + for (ai = 0; ai < 16; ai = ai + 16) begin + if ((mem_addra_reg) == (mem_addrb_int + ai)) begin + doa_out <= 16'bX; + end + end + end + data_collision_a_b[1] <= 0; + end + + always @(posedge data_collision_a_b[0]) begin + if (rstb_int == 0) begin + for (bi = 0; bi < 16; bi = bi + 16) begin + if ((mem_addra_reg) == (mem_addrb_int + bi)) begin + for (bj = 0; bj < 16; bj = bj + 1) begin + dob_out[bi + bj] <= 1'bX; + end + end + end + end + data_collision_a_b[0] <= 0; + end + + always @(posedge data_collision_b_a[1]) begin + if (rsta_int == 0) begin + for (ai = 0; ai < 16; ai = ai + 16) begin + if ((mem_addra_int) == (mem_addrb_reg + ai)) begin + doa_out <= 16'bX; + end + end + end + data_collision_b_a[1] <= 0; + end + + always @(posedge data_collision_b_a[0]) begin + if (rstb_reg == 0) begin + for (bi = 0; bi < 16; bi = bi + 16) begin + if ((mem_addra_int) == (mem_addrb_reg + bi)) begin + for (bj = 0; bj < 16; bj = bj + 1) begin + dob_out[bi + bj] <= 1'bX; + end + end + end + end + data_collision_b_a[0] <= 0; + end + + + always @(posedge clka_int) begin + if (ena_int == 1'b1) begin + if (rsta_int == 1'b1) begin + doa_out <= 16'b0; + end + else if (wea_int == 0) begin + doa_out[0] <= mem[mem_addra_int + 0]; + doa_out[1] <= mem[mem_addra_int + 1]; + doa_out[2] <= mem[mem_addra_int + 2]; + doa_out[3] <= mem[mem_addra_int + 3]; + doa_out[4] <= mem[mem_addra_int + 4]; + doa_out[5] <= mem[mem_addra_int + 5]; + doa_out[6] <= mem[mem_addra_int + 6]; + doa_out[7] <= mem[mem_addra_int + 7]; + doa_out[8] <= mem[mem_addra_int + 8]; + doa_out[9] <= mem[mem_addra_int + 9]; + doa_out[10] <= mem[mem_addra_int + 10]; + doa_out[11] <= mem[mem_addra_int + 11]; + doa_out[12] <= mem[mem_addra_int + 12]; + doa_out[13] <= mem[mem_addra_int + 13]; + doa_out[14] <= mem[mem_addra_int + 14]; + doa_out[15] <= mem[mem_addra_int + 15]; + end + else begin + doa_out <= dia_int; + end + end + end + + always @(posedge clka_int) begin + if (ena_int == 1'b1 && wea_int == 1'b1) begin + mem[mem_addra_int + 0] <= dia_int[0]; + mem[mem_addra_int + 1] <= dia_int[1]; + mem[mem_addra_int + 2] <= dia_int[2]; + mem[mem_addra_int + 3] <= dia_int[3]; + mem[mem_addra_int + 4] <= dia_int[4]; + mem[mem_addra_int + 5] <= dia_int[5]; + mem[mem_addra_int + 6] <= dia_int[6]; + mem[mem_addra_int + 7] <= dia_int[7]; + mem[mem_addra_int + 8] <= dia_int[8]; + mem[mem_addra_int + 9] <= dia_int[9]; + mem[mem_addra_int + 10] <= dia_int[10]; + mem[mem_addra_int + 11] <= dia_int[11]; + mem[mem_addra_int + 12] <= dia_int[12]; + mem[mem_addra_int + 13] <= dia_int[13]; + mem[mem_addra_int + 14] <= dia_int[14]; + mem[mem_addra_int + 15] <= dia_int[15]; + end + end + + always @(posedge clkb_int) begin + if (enb_int == 1'b1) begin + if (rstb_int == 1'b1) begin + dob_out <= 16'b0; + end + else if (web_int == 0) begin + dob_out[0] <= mem[mem_addrb_int + 0]; + dob_out[1] <= mem[mem_addrb_int + 1]; + dob_out[2] <= mem[mem_addrb_int + 2]; + dob_out[3] <= mem[mem_addrb_int + 3]; + dob_out[4] <= mem[mem_addrb_int + 4]; + dob_out[5] <= mem[mem_addrb_int + 5]; + dob_out[6] <= mem[mem_addrb_int + 6]; + dob_out[7] <= mem[mem_addrb_int + 7]; + dob_out[8] <= mem[mem_addrb_int + 8]; + dob_out[9] <= mem[mem_addrb_int + 9]; + dob_out[10] <= mem[mem_addrb_int + 10]; + dob_out[11] <= mem[mem_addrb_int + 11]; + dob_out[12] <= mem[mem_addrb_int + 12]; + dob_out[13] <= mem[mem_addrb_int + 13]; + dob_out[14] <= mem[mem_addrb_int + 14]; + dob_out[15] <= mem[mem_addrb_int + 15]; + end + else begin + dob_out <= dib_int; + end + end + end + + always @(posedge clkb_int) begin + if (enb_int == 1'b1 && web_int == 1'b1) begin + mem[mem_addrb_int + 0] <= dib_int[0]; + mem[mem_addrb_int + 1] <= dib_int[1]; + mem[mem_addrb_int + 2] <= dib_int[2]; + mem[mem_addrb_int + 3] <= dib_int[3]; + mem[mem_addrb_int + 4] <= dib_int[4]; + mem[mem_addrb_int + 5] <= dib_int[5]; + mem[mem_addrb_int + 6] <= dib_int[6]; + mem[mem_addrb_int + 7] <= dib_int[7]; + mem[mem_addrb_int + 8] <= dib_int[8]; + mem[mem_addrb_int + 9] <= dib_int[9]; + mem[mem_addrb_int + 10] <= dib_int[10]; + mem[mem_addrb_int + 11] <= dib_int[11]; + mem[mem_addrb_int + 12] <= dib_int[12]; + mem[mem_addrb_int + 13] <= dib_int[13]; + mem[mem_addrb_int + 14] <= dib_int[14]; + mem[mem_addrb_int + 15] <= dib_int[15]; + end + end + + specify + (CLKA *> DOA) = (100, 100); + (CLKB *> DOB) = (100, 100); + endspecify + +endmodule + +`else + +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/RAMB4_S16_S16.v,v 1.9 2007/02/22 01:58:06 wloo Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2005 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Timing Simulation Library Component +// / / 16K-Bit Data and 2K-Bit Parity Dual Port Block RAM +// /___/ /\ Filename : RAMB4_S16_S16.v +// \ \ / \ Timestamp : Thu Mar 10 16:44:01 PST 2005 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 03/10/05 - Initialized outputs. +// 02/21/07 - Fixed parameter SIM_COLLISION_CHECK (CR 433281). +// End Revision + +`timescale 1 ps/1 ps + +module RAMB4_S16_S16 (DOA, DOB, ADDRA, ADDRB, CLKA, CLKB, DIA, DIB, ENA, ENB, RSTA, RSTB, WEA, WEB); + + parameter SIM_COLLISION_CHECK = "ALL"; + localparam SETUP_ALL = 100; + + parameter INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + + output [15:0] DOA; + output [15:0] DOB; + + input [7:0] ADDRA; + input [15:0] DIA; + input ENA, CLKA, WEA, RSTA; + input [7:0] ADDRB; + input [15:0] DIB; + input ENB, CLKB, WEB, RSTB; + + reg [15:0] doa_out = 0; + reg [15:0] dob_out = 0; + + reg [15:0] mem [255:0]; + + reg [8:0] count; + + reg [5:0] mi, ai, bi, bj, ci; + + wire [7:0] addra_int; + reg [7:0] addra_reg; + wire [15:0] dia_int; + wire ena_int, clka_int, wea_int, rsta_int; + reg ena_reg, wea_reg, rsta_reg; + wire [7:0] addrb_int; + reg [7:0] addrb_reg; + wire [15:0] dib_int; + wire enb_int, clkb_int, web_int, rstb_int; + reg display_flag, output_flag; + reg enb_reg, web_reg, rstb_reg; + + time time_clka, time_clkb; + time time_clka_clkb; + time time_clkb_clka; + + reg setup_all_a_b; + reg setup_all_b_a; + reg setup_zero; + reg [1:0] data_collision, data_collision_a_b, data_collision_b_a; + reg memory_collision, memory_collision_a_b, memory_collision_b_a; + reg address_collision, address_collision_a_b, address_collision_b_a; + reg change_clka; + reg change_clkb; + + wire [11:0] mem_addra_int; + wire [11:0] mem_addra_reg; + wire [11:0] mem_addrb_int; + wire [11:0] mem_addrb_reg; + + wire dia_enable = ena_int && wea_int; + wire dib_enable = enb_int && web_int; + + tri0 GSR = glbl.GSR; + wire gsr_int; + + buf b_gsr (gsr_int, GSR); + + buf b_doa [15:0] (DOA, doa_out); + buf b_addra [7:0] (addra_int, ADDRA); + buf b_dia [15:0] (dia_int, DIA); + buf b_ena (ena_int, ENA); + buf b_clka (clka_int, CLKA); + buf b_rsta (rsta_int, RSTA); + buf b_wea (wea_int, WEA); + + buf b_dob [15:0] (DOB, dob_out); + buf b_addrb [7:0] (addrb_int, ADDRB); + buf b_dib [15:0] (dib_int, DIB); + buf b_enb (enb_int, ENB); + buf b_clkb (clkb_int, CLKB); + buf b_rstb (rstb_int, RSTB); + buf b_web (web_int, WEB); + + + always @(gsr_int) + if (gsr_int) begin + assign doa_out = 0; + assign dob_out = 0; + end + else begin + deassign doa_out; + deassign dob_out; + end + + + initial begin + + for (count = 0; count < 16; count = count + 1) begin + mem[count] = INIT_00[(count * 16) +: 16]; + mem[16 * 1 + count] = INIT_01[(count * 16) +: 16]; + mem[16 * 2 + count] = INIT_02[(count * 16) +: 16]; + mem[16 * 3 + count] = INIT_03[(count * 16) +: 16]; + mem[16 * 4 + count] = INIT_04[(count * 16) +: 16]; + mem[16 * 5 + count] = INIT_05[(count * 16) +: 16]; + mem[16 * 6 + count] = INIT_06[(count * 16) +: 16]; + mem[16 * 7 + count] = INIT_07[(count * 16) +: 16]; + mem[16 * 8 + count] = INIT_08[(count * 16) +: 16]; + mem[16 * 9 + count] = INIT_09[(count * 16) +: 16]; + mem[16 * 10 + count] = INIT_0A[(count * 16) +: 16]; + mem[16 * 11 + count] = INIT_0B[(count * 16) +: 16]; + mem[16 * 12 + count] = INIT_0C[(count * 16) +: 16]; + mem[16 * 13 + count] = INIT_0D[(count * 16) +: 16]; + mem[16 * 14 + count] = INIT_0E[(count * 16) +: 16]; + mem[16 * 15 + count] = INIT_0F[(count * 16) +: 16]; + end + + change_clka <= 0; + change_clkb <= 0; + data_collision <= 0; + data_collision_a_b <= 0; + data_collision_b_a <= 0; + memory_collision <= 0; + memory_collision_a_b <= 0; + memory_collision_b_a <= 0; + setup_all_a_b <= 0; + setup_all_b_a <= 0; + setup_zero <= 0; + end + + assign mem_addra_int = addra_int * 16; + assign mem_addra_reg = addra_reg * 16; + assign mem_addrb_int = addrb_int * 16; + assign mem_addrb_reg = addrb_reg * 16; + + + initial begin + + display_flag = 1; + output_flag = 1; + + case (SIM_COLLISION_CHECK) + + "NONE" : begin + output_flag = 0; + display_flag = 0; + end + "WARNING_ONLY" : output_flag = 0; + "GENERATE_X_ONLY" : display_flag = 0; + "ALL" : ; + + default : begin + $display("Attribute Syntax Error : The Attribute SIM_COLLISION_CHECK on RAMB4_S16_S16 instance %m is set to %s. Legal values for this attribute are ALL, NONE, WARNING_ONLY or GENERATE_X_ONLY.", SIM_COLLISION_CHECK); + $finish; + end + + endcase // case(SIM_COLLISION_CHECK) + + end // initial begin + + + always @(posedge clka_int) begin + if ((output_flag || display_flag)) begin + time_clka = $time; + #0 time_clkb_clka = time_clka - time_clkb; + change_clka = ~change_clka; + end + end + + always @(posedge clkb_int) begin + if ((output_flag || display_flag)) begin + time_clkb = $time; + #0 time_clka_clkb = time_clkb - time_clka; + change_clkb = ~change_clkb; + end + end + + always @(change_clkb) begin + if ((0 < time_clka_clkb) && (time_clka_clkb < SETUP_ALL)) + setup_all_a_b = 1; + end + + always @(change_clka) begin + if ((0 < time_clkb_clka) && (time_clkb_clka < SETUP_ALL)) + setup_all_b_a = 1; + end + + always @(change_clkb or change_clka) begin + if ((time_clkb_clka == 0) && (time_clka_clkb == 0)) + setup_zero = 1; + end + + always @(posedge setup_zero) begin + if ((ena_int == 1) && (wea_int == 1) && + (enb_int == 1) && (web_int == 1)) + memory_collision <= 1; + end + + always @(posedge setup_all_a_b) begin + if ((ena_reg == 1) && (enb_int == 1)) begin + case ({wea_reg, web_int}) + 6'b11 : begin data_collision_a_b <= 2'b11; display_all_a_b; end + 6'b01 : begin data_collision_a_b <= 2'b10; display_all_a_b; end + 6'b10 : begin data_collision_a_b <= 2'b01; display_all_a_b; end + endcase + end + setup_all_a_b <= 0; + end + + task display_all_a_b; + begin + address_collision_a_b = 1'b0; + for (ci = 0; ci < 16; ci = ci + 16) begin + if ((mem_addra_reg) == (mem_addrb_int + ci)) begin + address_collision_a_b = 1'b1; + end + end + if (address_collision_a_b == 1'b1 && display_flag) + + if (({wea_reg, web_int}) == 2'b11) + $display("Memory Collision Error on RAMB4_S16_S16:%m at simulation time %.3f ns\nA write was requested to the same address simultaneously at both Port A and Port B of the RAM. The contents written to the RAM at address location %h (hex) of Port A and address location %h (hex) of Port B are unknown.", $time/1000.0, addra_int, addrb_int); + + else if (({wea_reg, web_int}) == 2'b01) + $display("Memory Collision Error on RAMB4_S16_S16:%m at simulation time %.3f ns\nA read was performed on address %h (hex) of Port A while a write was requested to the same address on Port B. The write will be successful however the read value on Port A is unknown until the next CLKA cycle.", $time/1000.0, addra_int); + + else if (({wea_reg, web_int}) == 2'b10) + $display("Memory Collision Error on RAMB4_S16_S16:%m at simulation time %.3f ns\nA read was performed on address %h (hex) of Port B while a write was requested to the same address on Port A. The write will be successful however the read value on Port B is unknown until the next CLKB cycle.", $time/1000.0, addrb_int); + + end + endtask + + always @(posedge setup_all_b_a) begin + if ((ena_int == 1) && (enb_reg == 1)) begin + case ({wea_int, web_reg}) + 6'b11 : begin data_collision_b_a <= 2'b11; display_all_b_a; end + 6'b01 : begin data_collision_b_a <= 2'b10; display_all_b_a; end + 6'b10 : begin data_collision_b_a <= 2'b01; display_all_b_a; end + endcase + end + setup_all_b_a <= 0; + end + + task display_all_b_a; + begin + address_collision_b_a = 1'b0; + for (ci = 0; ci < 16; ci = ci + 16) begin + if ((mem_addra_int) == (mem_addrb_reg + ci)) begin + address_collision_b_a = 1'b1; + end + end + if (address_collision_b_a == 1'b1 && display_flag) + + if (({wea_int, web_reg}) == 2'b11) + $display("Memory Collision Error on RAMB4_S16_S16:%m at simulation time %.3f ns\nA write was requested to the same address simultaneously at both Port A and Port B of the RAM. The contents written to the RAM at address location %h (hex) of Port A and address location %h (hex) of Port B are unknown.", $time/1000.0, addra_int, addrb_int); + + else if (({wea_int, web_reg}) == 2'b01) + $display("Memory Collision Error on RAMB4_S16_S16:%m at simulation time %.3f ns\nA read was performed on address %h (hex) of Port A while a write was requested to the same address on Port B. The write will be successful however the read value on Port A is unknown until the next CLKA cycle.", $time/1000.0, addra_int); + + else if (({wea_int, web_reg}) == 2'b10) + $display("Memory Collision Error on RAMB4_S16_S16:%m at simulation time %.3f ns\nA read was performed on address %h (hex) of Port B while a write was requested to the same address on Port A. The write will be successful however the read value on Port B is unknown until the next CLKB cycle.", $time/1000.0, addrb_int); + + end + endtask + + always @(posedge setup_zero) begin + if ((ena_int == 1) && (enb_int == 1)) begin + case ({wea_int, web_int}) + 6'b11 : begin data_collision <= 2'b11; display_zero; end + 6'b01 : begin data_collision <= 2'b10; display_zero; end + 6'b10 : begin data_collision <= 2'b01; display_zero; end + endcase + end + setup_zero <= 0; + end + + task display_zero; + begin + address_collision = 1'b0; + for (ci = 0; ci < 16; ci = ci + 16) begin + if ((mem_addra_int) == (mem_addrb_int + ci)) begin + address_collision = 1'b1; + end + end + if (address_collision == 1'b1 && display_flag) + + if (({wea_int, web_int}) == 2'b11) + $display("Memory Collision Error on RAMB4_S16_S16:%m at simulation time %.3f ns\nA write was requested to the same address simultaneously at both Port A and Port B of the RAM. The contents written to the RAM at address location %h (hex) of Port A and address location %h (hex) of Port B are unknown.", $time/1000.0, addra_int, addrb_int); + + else if (({wea_int, web_int}) == 2'b01) + $display("Memory Collision Error on RAMB4_S16_S16:%m at simulation time %.3f ns\nA read was performed on address %h (hex) of Port A while a write was requested to the same address on Port B. The write will be successful however the read value on Port A is unknown until the next CLKA cycle.", $time/1000.0, addra_int); + + else if (({wea_int, web_int}) == 2'b10) + $display("Memory Collision Error on RAMB4_S16_S16:%m at simulation time %.3f ns\nA read was performed on address %h (hex) of Port B while a write was requested to the same address on Port A. The write will be successful however the read value on Port B is unknown until the next CLKB cycle.", $time/1000.0, addrb_int); + + end + endtask + + always @(posedge clka_int) begin + if ((output_flag || display_flag)) begin + addra_reg <= addra_int; + ena_reg <= ena_int; + rsta_reg <= rsta_int; + wea_reg <= wea_int; + end + end + + always @(posedge clkb_int) begin + if ((output_flag || display_flag)) begin + addrb_reg <= addrb_int; + enb_reg <= enb_int; + rstb_reg <= rstb_int; + web_reg <= web_int; + end + end + + + // Data + always @(posedge memory_collision) begin + if ((output_flag || display_flag)) begin + for (mi = 0; mi < 16; mi = mi + 16) begin + if ((mem_addra_int) == (mem_addrb_int + mi)) begin + mem[addra_int] <= 16'bx; + end + end + memory_collision <= 0; + end + end + + always @(posedge memory_collision_a_b) begin + if ((output_flag || display_flag)) begin + for (mi = 0; mi < 16; mi = mi + 16) begin + if ((mem_addra_reg) == (mem_addrb_int + mi)) begin + mem[addra_reg] <= 16'bx; + end + end + memory_collision_a_b <= 0; + end + end + + always @(posedge memory_collision_b_a) begin + if ((output_flag || display_flag)) begin + for (mi = 0; mi < 16; mi = mi + 16) begin + if ((mem_addra_int) == (mem_addrb_reg + mi)) begin + mem[addra_int] <= 16'bx; + end + end + memory_collision_b_a <= 0; + end + end + + always @(posedge data_collision[1]) begin + if (rsta_int == 0 && output_flag) begin + for (ai = 0; ai < 16; ai = ai + 16) begin + if ((mem_addra_int) == (mem_addrb_int + ai)) begin + doa_out <= #100 16'bX; + end + end + end + data_collision[1] <= 0; + end + + always @(posedge data_collision[0]) begin + if (rstb_int == 0 && output_flag) begin + for (bi = 0; bi < 16; bi = bi + 16) begin + if ((mem_addra_int) == (mem_addrb_int + bi)) begin + for (bj = 0; bj < 16; bj = bj + 1) begin + dob_out[bi + bj] <= #100 1'bX; + end + end + end + end + data_collision[0] <= 0; + end + + always @(posedge data_collision_a_b[1]) begin + if (rsta_reg == 0 && output_flag) begin + for (ai = 0; ai < 16; ai = ai + 16) begin + if ((mem_addra_reg) == (mem_addrb_int + ai)) begin + doa_out <= #100 16'bX; + end + end + end + data_collision_a_b[1] <= 0; + end + + always @(posedge data_collision_a_b[0]) begin + if (rstb_int == 0 && output_flag) begin + for (bi = 0; bi < 16; bi = bi + 16) begin + if ((mem_addra_reg) == (mem_addrb_int + bi)) begin + for (bj = 0; bj < 16; bj = bj + 1) begin + dob_out[bi + bj] <= #100 1'bX; + end + end + end + end + data_collision_a_b[0] <= 0; + end + + always @(posedge data_collision_b_a[1]) begin + if (rsta_int == 0 && output_flag) begin + for (ai = 0; ai < 16; ai = ai + 16) begin + if ((mem_addra_int) == (mem_addrb_reg + ai)) begin + doa_out <= #100 16'bX; + end + end + end + data_collision_b_a[1] <= 0; + end + + always @(posedge data_collision_b_a[0]) begin + if (rstb_reg == 0 && output_flag) begin + for (bi = 0; bi < 16; bi = bi + 16) begin + if ((mem_addra_int) == (mem_addrb_reg + bi)) begin + for (bj = 0; bj < 16; bj = bj + 1) begin + dob_out[bi + bj] <= #100 1'bX; + end + end + end + end + data_collision_b_a[0] <= 0; + end + + + // Port A + always @(posedge clka_int) begin + + if (ena_int == 1'b1) begin + + if (rsta_int == 1'b1) begin + doa_out <= #100 0; + end + else begin + if (wea_int == 1'b1) + doa_out <= #100 dia_int; + else + doa_out <= #100 mem[addra_int]; + end + + // memory + if (wea_int == 1'b1) begin + mem[addra_int] <= dia_int; + end + + end + end + + + // Port B + always @(posedge clkb_int) begin + + if (enb_int == 1'b1) begin + + if (rstb_int == 1'b1) begin + dob_out <= #100 0; + end + else begin + if (web_int == 1'b1) + dob_out <= #100 dib_int; + else + dob_out <= #100 mem[addrb_int]; + end + + // memory + if (web_int == 1'b1) begin + mem[addrb_int] <= dib_int; + end + + end + end + + +endmodule + +`endif diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/RAMB4_S1_S1.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/RAMB4_S1_S1.v new file mode 100644 index 0000000..5a10f07 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/RAMB4_S1_S1.v @@ -0,0 +1,1039 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/RAMB4_S1_S1.v,v 1.9 2007/02/22 01:58:06 wloo Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2005 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / 4K-Bit Data Dual Port Block RAM +// /___/ /\ Filename : RAMB4_S1_S1.v +// \ \ / \ Timestamp : Thu Mar 10 16:43:38 PST 2005 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// End Revision + +`ifdef legacy_model + +`timescale 1 ps / 1 ps + +module RAMB4_S1_S1 (DOA, DOB, ADDRA, ADDRB, CLKA, CLKB, DIA, DIB, ENA, ENB, RSTA, RSTB, WEA, WEB); + + parameter SIM_COLLISION_CHECK = "ALL"; + localparam SETUP_ALL = 100; + + parameter INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + + output [0:0] DOA; + reg [0:0] doa_out; + wire doa_out0; + + input [11:0] ADDRA; + input [0:0] DIA; + input ENA, CLKA, WEA, RSTA; + + output [0:0] DOB; + reg [0:0] dob_out; + wire dob_out0; + + input [11:0] ADDRB; + input [0:0] DIB; + input ENB, CLKB, WEB, RSTB; + + reg [4095:0] mem; + reg [8:0] count; + + reg [5:0] mi, mj, ai, aj, bi, bj, ci, cj, di, dj, ei, ej, fi, fj; + + wire [11:0] addra_int; + reg [11:0] addra_reg; + wire [0:0] dia_int; + wire ena_int, clka_int, wea_int, rsta_int; + reg ena_reg, wea_reg, rsta_reg; + wire [11:0] addrb_int; + reg [11:0] addrb_reg; + wire [0:0] dib_int; + wire enb_int, clkb_int, web_int, rstb_int; + reg enb_reg, web_reg, rstb_reg; + + time time_clka, time_clkb; + time time_clka_clkb; + time time_clkb_clka; + + reg setup_all_a_b; + reg setup_all_b_a; + reg setup_zero; + reg [1:0] data_collision, data_collision_a_b, data_collision_b_a; + reg memory_collision, memory_collision_a_b, memory_collision_b_a; + reg address_collision, address_collision_a_b, address_collision_b_a; + reg change_clka; + reg change_clkb; + + wire [11:0] mem_addra_int; + wire [11:0] mem_addra_reg; + wire [11:0] mem_addrb_int; + wire [11:0] mem_addrb_reg; + + tri0 GSR = glbl.GSR; + + always @(GSR) + if (GSR) begin + assign doa_out = 0; + end + else begin + deassign doa_out; + end + + always @(GSR) + if (GSR) begin + assign dob_out = 0; + end + else begin + deassign dob_out; + end + + buf b_doa_out0 (doa_out0, doa_out[0]); + buf b_dob_out0 (dob_out0, dob_out[0]); + buf b_doa0 (DOA[0], doa_out0); + buf b_dob0 (DOB[0], dob_out0); + buf b_addra_0 (addra_int[0], ADDRA[0]); + buf b_addra_1 (addra_int[1], ADDRA[1]); + buf b_addra_2 (addra_int[2], ADDRA[2]); + buf b_addra_3 (addra_int[3], ADDRA[3]); + buf b_addra_4 (addra_int[4], ADDRA[4]); + buf b_addra_5 (addra_int[5], ADDRA[5]); + buf b_addra_6 (addra_int[6], ADDRA[6]); + buf b_addra_7 (addra_int[7], ADDRA[7]); + buf b_addra_8 (addra_int[8], ADDRA[8]); + buf b_addra_9 (addra_int[9], ADDRA[9]); + buf b_addra_10 (addra_int[10], ADDRA[10]); + buf b_addra_11 (addra_int[11], ADDRA[11]); + buf b_dia_0 (dia_int[0], DIA[0]); + buf b_clka (clka_int, CLKA); + buf b_ena (ena_int, ENA); + buf b_rsta (rsta_int, RSTA); + buf b_wea (wea_int, WEA); + buf b_addrb_0 (addrb_int[0], ADDRB[0]); + buf b_addrb_1 (addrb_int[1], ADDRB[1]); + buf b_addrb_2 (addrb_int[2], ADDRB[2]); + buf b_addrb_3 (addrb_int[3], ADDRB[3]); + buf b_addrb_4 (addrb_int[4], ADDRB[4]); + buf b_addrb_5 (addrb_int[5], ADDRB[5]); + buf b_addrb_6 (addrb_int[6], ADDRB[6]); + buf b_addrb_7 (addrb_int[7], ADDRB[7]); + buf b_addrb_8 (addrb_int[8], ADDRB[8]); + buf b_addrb_9 (addrb_int[9], ADDRB[9]); + buf b_addrb_10 (addrb_int[10], ADDRB[10]); + buf b_addrb_11 (addrb_int[11], ADDRB[11]); + buf b_dib_0 (dib_int[0], DIB[0]); + buf b_clkb (clkb_int, CLKB); + buf b_enb (enb_int, ENB); + buf b_rstb (rstb_int, RSTB); + buf b_web (web_int, WEB); + + initial begin + for (count = 0; count < 256; count = count + 1) begin + mem[count] <= INIT_00[count]; + mem[256 * 1 + count] <= INIT_01[count]; + mem[256 * 2 + count] <= INIT_02[count]; + mem[256 * 3 + count] <= INIT_03[count]; + mem[256 * 4 + count] <= INIT_04[count]; + mem[256 * 5 + count] <= INIT_05[count]; + mem[256 * 6 + count] <= INIT_06[count]; + mem[256 * 7 + count] <= INIT_07[count]; + mem[256 * 8 + count] <= INIT_08[count]; + mem[256 * 9 + count] <= INIT_09[count]; + mem[256 * 10 + count] <= INIT_0A[count]; + mem[256 * 11 + count] <= INIT_0B[count]; + mem[256 * 12 + count] <= INIT_0C[count]; + mem[256 * 13 + count] <= INIT_0D[count]; + mem[256 * 14 + count] <= INIT_0E[count]; + mem[256 * 15 + count] <= INIT_0F[count]; + end + address_collision <= 0; + address_collision_a_b <= 0; + address_collision_b_a <= 0; + change_clka <= 0; + change_clkb <= 0; + data_collision <= 0; + data_collision_a_b <= 0; + data_collision_b_a <= 0; + memory_collision <= 0; + memory_collision_a_b <= 0; + memory_collision_b_a <= 0; + setup_all_a_b <= 0; + setup_all_b_a <= 0; + setup_zero <= 0; + end + + assign mem_addra_int = addra_int * 1; + assign mem_addra_reg = addra_reg * 1; + assign mem_addrb_int = addrb_int * 1; + assign mem_addrb_reg = addrb_reg * 1; + + + initial begin + + case (SIM_COLLISION_CHECK) + + "NONE" : begin + assign setup_all_a_b = 1'b0; + assign setup_all_b_a = 1'b0; + assign setup_zero = 1'b0; + assign address_collision = 1'b0; + assign address_collision_a_b = 1'b0; + assign address_collision_b_a = 1'b0; + end + "WARNING_ONLY" : begin + assign data_collision = 2'b00; + assign data_collision_a_b = 2'b00; + assign data_collision_b_a = 2'b00; + assign memory_collision = 1'b0; + assign memory_collision_a_b = 1'b0; + assign memory_collision_b_a = 1'b0; + end + "GENERATE_X_ONLY" : begin + assign address_collision = 1'b0; + assign address_collision_a_b = 1'b0; + assign address_collision_b_a = 1'b0; + end + "ALL" : ; + default : begin + $display("Attribute Syntax Error : The Attribute SIM_COLLISION_CHECK on RAMB4_S1_S1 instance %m is set to %s. Legal values for this attribute are ALL, NONE, WARNING_ONLY or GENERATE_X_ONLY.", SIM_COLLISION_CHECK); + $finish; + end + + endcase // case(SIM_COLLISION_CHECK) + + end // initial begin + + + always @(posedge clka_int) begin + time_clka = $time; + #0 time_clkb_clka = time_clka - time_clkb; + change_clka = ~change_clka; + end + + always @(posedge clkb_int) begin + time_clkb = $time; + #0 time_clka_clkb = time_clkb - time_clka; + change_clkb = ~change_clkb; + end + + always @(change_clkb) begin + if ((0 < time_clka_clkb) && (time_clka_clkb < SETUP_ALL)) + setup_all_a_b = 1; + end + + always @(change_clka) begin + if ((0 < time_clkb_clka) && (time_clkb_clka < SETUP_ALL)) + setup_all_b_a = 1; + end + + always @(change_clkb or change_clka) begin + if ((time_clkb_clka == 0) && (time_clka_clkb == 0)) + setup_zero = 1; + end + + always @(posedge setup_zero) begin + if ((ena_int == 1) && (wea_int == 1) && + (enb_int == 1) && (web_int == 1)) + memory_collision <= 1; + end + + always @(posedge setup_all_a_b) begin + if ((ena_reg == 1) && (enb_int == 1)) begin + case ({wea_reg, web_int}) + 6'b11 : begin data_collision_a_b <= 2'b11; display_all_a_b; end + 6'b01 : begin data_collision_a_b <= 2'b10; display_all_a_b; end + 6'b10 : begin data_collision_a_b <= 2'b01; display_all_a_b; end + endcase + end + setup_all_a_b <= 0; + end + + task display_all_a_b; + begin + address_collision_a_b = 1'b0; + for (ci = 0; ci < 1; ci = ci + 1) begin + if ((mem_addra_reg) == (mem_addrb_int + ci)) begin + address_collision_a_b = 1'b1; + end + end + if (address_collision_a_b == 1'b1) + + if (({wea_reg, web_int}) == 2'b11) + $display("Memory Collision Error on RAMB4_S1_S1:%m at simulation time %.3f ns\nA write was requested to the same address simultaneously at both Port A and Port B of the RAM. The contents written to the RAM at address location %h (hex) of Port A and address location %h (hex) of Port B are unknown.", $time/1000.0, addra_int, addrb_int); + + else if (({wea_reg, web_int}) == 2'b01) + $display("Memory Collision Error on RAMB4_S1_S1:%m at simulation time %.3f ns\nA read was performed on address %h (hex) of Port A while a write was requested to the same address on Port B. The write will be successful however the read value on Port A is unknown until the next CLKA cycle.", $time/1000.0, addra_int); + + else if (({wea_reg, web_int}) == 2'b10) + $display("Memory Collision Error on RAMB4_S1_S1:%m at simulation time %.3f ns\nA read was performed on address %h (hex) of Port B while a write was requested to the same address on Port A. The write will be successful however the read value on Port B is unknown until the next CLKB cycle.", $time/1000.0, addrb_int); + + end + endtask + + always @(posedge setup_all_b_a) begin + if ((ena_int == 1) && (enb_reg == 1)) begin + case ({wea_int, web_reg}) + 6'b11 : begin data_collision_b_a <= 2'b11; display_all_b_a; end + 6'b01 : begin data_collision_b_a <= 2'b10; display_all_b_a; end + 6'b10 : begin data_collision_b_a <= 2'b01; display_all_b_a; end + endcase + end + setup_all_b_a <= 0; + end + + task display_all_b_a; + begin + address_collision_b_a = 1'b0; + for (ci = 0; ci < 1; ci = ci + 1) begin + if ((mem_addra_int) == (mem_addrb_reg + ci)) begin + address_collision_b_a = 1'b1; + end + end + if (address_collision_b_a == 1'b1) + + if (({wea_int, web_reg}) == 2'b11) + $display("Memory Collision Error on RAMB4_S1_S1:%m at simulation time %.3f ns\nA write was requested to the same address simultaneously at both Port A and Port B of the RAM. The contents written to the RAM at address location %h (hex) of Port A and address location %h (hex) of Port B are unknown.", $time/1000.0, addra_int, addrb_int); + + else if (({wea_int, web_reg}) == 2'b01) + $display("Memory Collision Error on RAMB4_S1_S1:%m at simulation time %.3f ns\nA read was performed on address %h (hex) of Port A while a write was requested to the same address on Port B. The write will be successful however the read value on Port A is unknown until the next CLKA cycle.", $time/1000.0, addra_int); + + else if (({wea_int, web_reg}) == 2'b10) + $display("Memory Collision Error on RAMB4_S1_S1:%m at simulation time %.3f ns\nA read was performed on address %h (hex) of Port B while a write was requested to the same address on Port A. The write will be successful however the read value on Port B is unknown until the next CLKB cycle.", $time/1000.0, addrb_int); + + end + endtask + + always @(posedge setup_zero) begin + if ((ena_int == 1) && (enb_int == 1)) begin + case ({wea_int, web_int}) + 6'b11 : begin data_collision <= 2'b11; display_zero; end + 6'b01 : begin data_collision <= 2'b10; display_zero; end + 6'b10 : begin data_collision <= 2'b01; display_zero; end + endcase + end + setup_zero <= 0; + end + + task display_zero; + begin + address_collision = 1'b0; + for (ci = 0; ci < 1; ci = ci + 1) begin + if ((mem_addra_int) == (mem_addrb_int + ci)) begin + address_collision = 1'b1; + end + end + if (address_collision == 1'b1) + + if (({wea_int, web_int}) == 2'b11) + $display("Memory Collision Error on RAMB4_S1_S1:%m at simulation time %.3f ns\nA write was requested to the same address simultaneously at both Port A and Port B of the RAM. The contents written to the RAM at address location %h (hex) of Port A and address location %h (hex) of Port B are unknown.", $time/1000.0, addra_int, addrb_int); + + else if (({wea_int, web_int}) == 2'b01) + $display("Memory Collision Error on RAMB4_S1_S1:%m at simulation time %.3f ns\nA read was performed on address %h (hex) of Port A while a write was requested to the same address on Port B. The write will be successful however the read value on Port A is unknown until the next CLKA cycle.", $time/1000.0, addra_int); + + else if (({wea_int, web_int}) == 2'b10) + $display("Memory Collision Error on RAMB4_S1_S1:%m at simulation time %.3f ns\nA read was performed on address %h (hex) of Port B while a write was requested to the same address on Port A. The write will be successful however the read value on Port B is unknown until the next CLKB cycle.", $time/1000.0, addrb_int); + + end + endtask + + always @(posedge clka_int) begin + addra_reg <= addra_int; + ena_reg <= ena_int; + rsta_reg <= rsta_int; + wea_reg <= wea_int; + end + + always @(posedge clkb_int) begin + addrb_reg <= addrb_int; + enb_reg <= enb_int; + rstb_reg <= rstb_int; + web_reg <= web_int; + end + + // Data + always @(posedge memory_collision) begin + for (mi = 0; mi < 1; mi = mi + 1) begin + if ((mem_addra_int) == (mem_addrb_int + mi)) begin + for (mj = 0; mj < 1; mj = mj + 1) begin + mem[mem_addrb_int + mi + mj] <= 1'bX; + end + end + end + memory_collision <= 0; + end + + always @(posedge memory_collision_a_b) begin + for (mi = 0; mi < 1; mi = mi + 1) begin + if ((mem_addra_reg) == (mem_addrb_int + mi)) begin + for (mj = 0; mj < 1; mj = mj + 1) begin + mem[mem_addrb_int + mi + mj] <= 1'bX; + end + end + end + memory_collision_a_b <= 0; + end + + always @(posedge memory_collision_b_a) begin + for (mi = 0; mi < 1; mi = mi + 1) begin + if ((mem_addra_int) == (mem_addrb_reg + mi)) begin + for (mj = 0; mj < 1; mj = mj + 1) begin + mem[mem_addrb_reg + mi + mj] <= 1'bX; + end + end + end + memory_collision_b_a <= 0; + end + + always @(posedge data_collision[1]) begin + if (rsta_int == 0) begin + for (ai = 0; ai < 1; ai = ai + 1) begin + if ((mem_addra_int) == (mem_addrb_int + ai)) begin + doa_out <= 1'bX; + end + end + end + data_collision[1] <= 0; + end + + always @(posedge data_collision[0]) begin + if (rstb_int == 0) begin + for (bi = 0; bi < 1; bi = bi + 1) begin + if ((mem_addra_int) == (mem_addrb_int + bi)) begin + for (bj = 0; bj < 1; bj = bj + 1) begin + dob_out[bi + bj] <= 1'bX; + end + end + end + end + data_collision[0] <= 0; + end + + always @(posedge data_collision_a_b[1]) begin + if (rsta_reg == 0) begin + for (ai = 0; ai < 1; ai = ai + 1) begin + if ((mem_addra_reg) == (mem_addrb_int + ai)) begin + doa_out <= 1'bX; + end + end + end + data_collision_a_b[1] <= 0; + end + + always @(posedge data_collision_a_b[0]) begin + if (rstb_int == 0) begin + for (bi = 0; bi < 1; bi = bi + 1) begin + if ((mem_addra_reg) == (mem_addrb_int + bi)) begin + for (bj = 0; bj < 1; bj = bj + 1) begin + dob_out[bi + bj] <= 1'bX; + end + end + end + end + data_collision_a_b[0] <= 0; + end + + always @(posedge data_collision_b_a[1]) begin + if (rsta_int == 0) begin + for (ai = 0; ai < 1; ai = ai + 1) begin + if ((mem_addra_int) == (mem_addrb_reg + ai)) begin + doa_out <= 1'bX; + end + end + end + data_collision_b_a[1] <= 0; + end + + always @(posedge data_collision_b_a[0]) begin + if (rstb_reg == 0) begin + for (bi = 0; bi < 1; bi = bi + 1) begin + if ((mem_addra_int) == (mem_addrb_reg + bi)) begin + for (bj = 0; bj < 1; bj = bj + 1) begin + dob_out[bi + bj] <= 1'bX; + end + end + end + end + data_collision_b_a[0] <= 0; + end + + + always @(posedge clka_int) begin + if (ena_int == 1'b1) begin + if (rsta_int == 1'b1) begin + doa_out <= 1'b0; + end + else if (wea_int == 0) begin + doa_out[0] <= mem[mem_addra_int + 0]; + end + else begin + doa_out <= dia_int; + end + end + end + + always @(posedge clka_int) begin + if (ena_int == 1'b1 && wea_int == 1'b1) begin + mem[mem_addra_int + 0] <= dia_int[0]; + end + end + + always @(posedge clkb_int) begin + if (enb_int == 1'b1) begin + if (rstb_int == 1'b1) begin + dob_out <= 1'b0; + end + else if (web_int == 0) begin + dob_out[0] <= mem[mem_addrb_int + 0]; + end + else begin + dob_out <= dib_int; + end + end + end + + always @(posedge clkb_int) begin + if (enb_int == 1'b1 && web_int == 1'b1) begin + mem[mem_addrb_int + 0] <= dib_int[0]; + end + end + + specify + (CLKA *> DOA) = (100, 100); + (CLKB *> DOB) = (100, 100); + endspecify + +endmodule + +`else + +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/RAMB4_S1_S1.v,v 1.9 2007/02/22 01:58:06 wloo Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2005 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Timing Simulation Library Component +// / / 16K-Bit Data and 2K-Bit Parity Dual Port Block RAM +// /___/ /\ Filename : RAMB4_S1_S1.v +// \ \ / \ Timestamp : Thu Mar 10 16:44:01 PST 2005 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 03/10/05 - Initialized outputs. +// 02/21/07 - Fixed parameter SIM_COLLISION_CHECK (CR 433281). +// End Revision + +`timescale 1 ps/1 ps + +module RAMB4_S1_S1 (DOA, DOB, ADDRA, ADDRB, CLKA, CLKB, DIA, DIB, ENA, ENB, RSTA, RSTB, WEA, WEB); + + parameter SIM_COLLISION_CHECK = "ALL"; + localparam SETUP_ALL = 100; + + parameter INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + + output [0:0] DOA; + output [0:0] DOB; + + input [11:0] ADDRA; + input [0:0] DIA; + input ENA, CLKA, WEA, RSTA; + input [11:0] ADDRB; + input [0:0] DIB; + input ENB, CLKB, WEB, RSTB; + + reg [0:0] doa_out = 0; + reg [0:0] dob_out = 0; + + reg [0:0] mem [4095:0]; + + reg [8:0] count; + + reg [5:0] mi, ai, bi, bj, ci; + + wire [11:0] addra_int; + reg [11:0] addra_reg; + wire [0:0] dia_int; + wire ena_int, clka_int, wea_int, rsta_int; + reg ena_reg, wea_reg, rsta_reg; + wire [11:0] addrb_int; + reg [11:0] addrb_reg; + wire [0:0] dib_int; + wire enb_int, clkb_int, web_int, rstb_int; + reg display_flag, output_flag; + reg enb_reg, web_reg, rstb_reg; + + time time_clka, time_clkb; + time time_clka_clkb; + time time_clkb_clka; + + reg setup_all_a_b; + reg setup_all_b_a; + reg setup_zero; + reg [1:0] data_collision, data_collision_a_b, data_collision_b_a; + reg memory_collision, memory_collision_a_b, memory_collision_b_a; + reg address_collision, address_collision_a_b, address_collision_b_a; + reg change_clka; + reg change_clkb; + + wire [11:0] mem_addra_int; + wire [11:0] mem_addra_reg; + wire [11:0] mem_addrb_int; + wire [11:0] mem_addrb_reg; + + wire dia_enable = ena_int && wea_int; + wire dib_enable = enb_int && web_int; + + tri0 GSR = glbl.GSR; + wire gsr_int; + + buf b_gsr (gsr_int, GSR); + + buf b_doa [0:0] (DOA, doa_out); + buf b_addra [11:0] (addra_int, ADDRA); + buf b_dia [0:0] (dia_int, DIA); + buf b_ena (ena_int, ENA); + buf b_clka (clka_int, CLKA); + buf b_rsta (rsta_int, RSTA); + buf b_wea (wea_int, WEA); + + buf b_dob [0:0] (DOB, dob_out); + buf b_addrb [11:0] (addrb_int, ADDRB); + buf b_dib [0:0] (dib_int, DIB); + buf b_enb (enb_int, ENB); + buf b_clkb (clkb_int, CLKB); + buf b_rstb (rstb_int, RSTB); + buf b_web (web_int, WEB); + + + always @(gsr_int) + if (gsr_int) begin + assign doa_out = 0; + assign dob_out = 0; + end + else begin + deassign doa_out; + deassign dob_out; + end + + + initial begin + + for (count = 0; count < 256; count = count + 1) begin + mem[count] = INIT_00[(count * 1) +: 1]; + mem[256 * 1 + count] = INIT_01[(count * 1) +: 1]; + mem[256 * 2 + count] = INIT_02[(count * 1) +: 1]; + mem[256 * 3 + count] = INIT_03[(count * 1) +: 1]; + mem[256 * 4 + count] = INIT_04[(count * 1) +: 1]; + mem[256 * 5 + count] = INIT_05[(count * 1) +: 1]; + mem[256 * 6 + count] = INIT_06[(count * 1) +: 1]; + mem[256 * 7 + count] = INIT_07[(count * 1) +: 1]; + mem[256 * 8 + count] = INIT_08[(count * 1) +: 1]; + mem[256 * 9 + count] = INIT_09[(count * 1) +: 1]; + mem[256 * 10 + count] = INIT_0A[(count * 1) +: 1]; + mem[256 * 11 + count] = INIT_0B[(count * 1) +: 1]; + mem[256 * 12 + count] = INIT_0C[(count * 1) +: 1]; + mem[256 * 13 + count] = INIT_0D[(count * 1) +: 1]; + mem[256 * 14 + count] = INIT_0E[(count * 1) +: 1]; + mem[256 * 15 + count] = INIT_0F[(count * 1) +: 1]; + end + + change_clka <= 0; + change_clkb <= 0; + data_collision <= 0; + data_collision_a_b <= 0; + data_collision_b_a <= 0; + memory_collision <= 0; + memory_collision_a_b <= 0; + memory_collision_b_a <= 0; + setup_all_a_b <= 0; + setup_all_b_a <= 0; + setup_zero <= 0; + end + + assign mem_addra_int = addra_int * 1; + assign mem_addra_reg = addra_reg * 1; + assign mem_addrb_int = addrb_int * 1; + assign mem_addrb_reg = addrb_reg * 1; + + + initial begin + + display_flag = 1; + output_flag = 1; + + case (SIM_COLLISION_CHECK) + + "NONE" : begin + output_flag = 0; + display_flag = 0; + end + "WARNING_ONLY" : output_flag = 0; + "GENERATE_X_ONLY" : display_flag = 0; + "ALL" : ; + + default : begin + $display("Attribute Syntax Error : The Attribute SIM_COLLISION_CHECK on RAMB4_S1_S1 instance %m is set to %s. Legal values for this attribute are ALL, NONE, WARNING_ONLY or GENERATE_X_ONLY.", SIM_COLLISION_CHECK); + $finish; + end + + endcase // case(SIM_COLLISION_CHECK) + + end // initial begin + + + always @(posedge clka_int) begin + if ((output_flag || display_flag)) begin + time_clka = $time; + #0 time_clkb_clka = time_clka - time_clkb; + change_clka = ~change_clka; + end + end + + always @(posedge clkb_int) begin + if ((output_flag || display_flag)) begin + time_clkb = $time; + #0 time_clka_clkb = time_clkb - time_clka; + change_clkb = ~change_clkb; + end + end + + always @(change_clkb) begin + if ((0 < time_clka_clkb) && (time_clka_clkb < SETUP_ALL)) + setup_all_a_b = 1; + end + + always @(change_clka) begin + if ((0 < time_clkb_clka) && (time_clkb_clka < SETUP_ALL)) + setup_all_b_a = 1; + end + + always @(change_clkb or change_clka) begin + if ((time_clkb_clka == 0) && (time_clka_clkb == 0)) + setup_zero = 1; + end + + always @(posedge setup_zero) begin + if ((ena_int == 1) && (wea_int == 1) && + (enb_int == 1) && (web_int == 1)) + memory_collision <= 1; + end + + always @(posedge setup_all_a_b) begin + if ((ena_reg == 1) && (enb_int == 1)) begin + case ({wea_reg, web_int}) + 6'b11 : begin data_collision_a_b <= 2'b11; display_all_a_b; end + 6'b01 : begin data_collision_a_b <= 2'b10; display_all_a_b; end + 6'b10 : begin data_collision_a_b <= 2'b01; display_all_a_b; end + endcase + end + setup_all_a_b <= 0; + end + + task display_all_a_b; + begin + address_collision_a_b = 1'b0; + for (ci = 0; ci < 1; ci = ci + 1) begin + if ((mem_addra_reg) == (mem_addrb_int + ci)) begin + address_collision_a_b = 1'b1; + end + end + if (address_collision_a_b == 1'b1 && display_flag) + + if (({wea_reg, web_int}) == 2'b11) + $display("Memory Collision Error on RAMB4_S1_S1:%m at simulation time %.3f ns\nA write was requested to the same address simultaneously at both Port A and Port B of the RAM. The contents written to the RAM at address location %h (hex) of Port A and address location %h (hex) of Port B are unknown.", $time/1000.0, addra_int, addrb_int); + + else if (({wea_reg, web_int}) == 2'b01) + $display("Memory Collision Error on RAMB4_S1_S1:%m at simulation time %.3f ns\nA read was performed on address %h (hex) of Port A while a write was requested to the same address on Port B. The write will be successful however the read value on Port A is unknown until the next CLKA cycle.", $time/1000.0, addra_int); + + else if (({wea_reg, web_int}) == 2'b10) + $display("Memory Collision Error on RAMB4_S1_S1:%m at simulation time %.3f ns\nA read was performed on address %h (hex) of Port B while a write was requested to the same address on Port A. The write will be successful however the read value on Port B is unknown until the next CLKB cycle.", $time/1000.0, addrb_int); + + end + endtask + + always @(posedge setup_all_b_a) begin + if ((ena_int == 1) && (enb_reg == 1)) begin + case ({wea_int, web_reg}) + 6'b11 : begin data_collision_b_a <= 2'b11; display_all_b_a; end + 6'b01 : begin data_collision_b_a <= 2'b10; display_all_b_a; end + 6'b10 : begin data_collision_b_a <= 2'b01; display_all_b_a; end + endcase + end + setup_all_b_a <= 0; + end + + task display_all_b_a; + begin + address_collision_b_a = 1'b0; + for (ci = 0; ci < 1; ci = ci + 1) begin + if ((mem_addra_int) == (mem_addrb_reg + ci)) begin + address_collision_b_a = 1'b1; + end + end + if (address_collision_b_a == 1'b1 && display_flag) + + if (({wea_int, web_reg}) == 2'b11) + $display("Memory Collision Error on RAMB4_S1_S1:%m at simulation time %.3f ns\nA write was requested to the same address simultaneously at both Port A and Port B of the RAM. The contents written to the RAM at address location %h (hex) of Port A and address location %h (hex) of Port B are unknown.", $time/1000.0, addra_int, addrb_int); + + else if (({wea_int, web_reg}) == 2'b01) + $display("Memory Collision Error on RAMB4_S1_S1:%m at simulation time %.3f ns\nA read was performed on address %h (hex) of Port A while a write was requested to the same address on Port B. The write will be successful however the read value on Port A is unknown until the next CLKA cycle.", $time/1000.0, addra_int); + + else if (({wea_int, web_reg}) == 2'b10) + $display("Memory Collision Error on RAMB4_S1_S1:%m at simulation time %.3f ns\nA read was performed on address %h (hex) of Port B while a write was requested to the same address on Port A. The write will be successful however the read value on Port B is unknown until the next CLKB cycle.", $time/1000.0, addrb_int); + + end + endtask + + always @(posedge setup_zero) begin + if ((ena_int == 1) && (enb_int == 1)) begin + case ({wea_int, web_int}) + 6'b11 : begin data_collision <= 2'b11; display_zero; end + 6'b01 : begin data_collision <= 2'b10; display_zero; end + 6'b10 : begin data_collision <= 2'b01; display_zero; end + endcase + end + setup_zero <= 0; + end + + task display_zero; + begin + address_collision = 1'b0; + for (ci = 0; ci < 1; ci = ci + 1) begin + if ((mem_addra_int) == (mem_addrb_int + ci)) begin + address_collision = 1'b1; + end + end + if (address_collision == 1'b1 && display_flag) + + if (({wea_int, web_int}) == 2'b11) + $display("Memory Collision Error on RAMB4_S1_S1:%m at simulation time %.3f ns\nA write was requested to the same address simultaneously at both Port A and Port B of the RAM. The contents written to the RAM at address location %h (hex) of Port A and address location %h (hex) of Port B are unknown.", $time/1000.0, addra_int, addrb_int); + + else if (({wea_int, web_int}) == 2'b01) + $display("Memory Collision Error on RAMB4_S1_S1:%m at simulation time %.3f ns\nA read was performed on address %h (hex) of Port A while a write was requested to the same address on Port B. The write will be successful however the read value on Port A is unknown until the next CLKA cycle.", $time/1000.0, addra_int); + + else if (({wea_int, web_int}) == 2'b10) + $display("Memory Collision Error on RAMB4_S1_S1:%m at simulation time %.3f ns\nA read was performed on address %h (hex) of Port B while a write was requested to the same address on Port A. The write will be successful however the read value on Port B is unknown until the next CLKB cycle.", $time/1000.0, addrb_int); + + end + endtask + + always @(posedge clka_int) begin + if ((output_flag || display_flag)) begin + addra_reg <= addra_int; + ena_reg <= ena_int; + rsta_reg <= rsta_int; + wea_reg <= wea_int; + end + end + + always @(posedge clkb_int) begin + if ((output_flag || display_flag)) begin + addrb_reg <= addrb_int; + enb_reg <= enb_int; + rstb_reg <= rstb_int; + web_reg <= web_int; + end + end + + + // Data + always @(posedge memory_collision) begin + if ((output_flag || display_flag)) begin + for (mi = 0; mi < 1; mi = mi + 1) begin + if ((mem_addra_int) == (mem_addrb_int + mi)) begin + mem[addra_int] <= 1'bx; + end + end + memory_collision <= 0; + end + end + + always @(posedge memory_collision_a_b) begin + if ((output_flag || display_flag)) begin + for (mi = 0; mi < 1; mi = mi + 1) begin + if ((mem_addra_reg) == (mem_addrb_int + mi)) begin + mem[addra_reg] <= 1'bx; + end + end + memory_collision_a_b <= 0; + end + end + + always @(posedge memory_collision_b_a) begin + if ((output_flag || display_flag)) begin + for (mi = 0; mi < 1; mi = mi + 1) begin + if ((mem_addra_int) == (mem_addrb_reg + mi)) begin + mem[addra_int] <= 1'bx; + end + end + memory_collision_b_a <= 0; + end + end + + always @(posedge data_collision[1]) begin + if (rsta_int == 0 && output_flag) begin + for (ai = 0; ai < 1; ai = ai + 1) begin + if ((mem_addra_int) == (mem_addrb_int + ai)) begin + doa_out <= #100 1'bX; + end + end + end + data_collision[1] <= 0; + end + + always @(posedge data_collision[0]) begin + if (rstb_int == 0 && output_flag) begin + for (bi = 0; bi < 1; bi = bi + 1) begin + if ((mem_addra_int) == (mem_addrb_int + bi)) begin + for (bj = 0; bj < 1; bj = bj + 1) begin + dob_out[bi + bj] <= #100 1'bX; + end + end + end + end + data_collision[0] <= 0; + end + + always @(posedge data_collision_a_b[1]) begin + if (rsta_reg == 0 && output_flag) begin + for (ai = 0; ai < 1; ai = ai + 1) begin + if ((mem_addra_reg) == (mem_addrb_int + ai)) begin + doa_out <= #100 1'bX; + end + end + end + data_collision_a_b[1] <= 0; + end + + always @(posedge data_collision_a_b[0]) begin + if (rstb_int == 0 && output_flag) begin + for (bi = 0; bi < 1; bi = bi + 1) begin + if ((mem_addra_reg) == (mem_addrb_int + bi)) begin + for (bj = 0; bj < 1; bj = bj + 1) begin + dob_out[bi + bj] <= #100 1'bX; + end + end + end + end + data_collision_a_b[0] <= 0; + end + + always @(posedge data_collision_b_a[1]) begin + if (rsta_int == 0 && output_flag) begin + for (ai = 0; ai < 1; ai = ai + 1) begin + if ((mem_addra_int) == (mem_addrb_reg + ai)) begin + doa_out <= #100 1'bX; + end + end + end + data_collision_b_a[1] <= 0; + end + + always @(posedge data_collision_b_a[0]) begin + if (rstb_reg == 0 && output_flag) begin + for (bi = 0; bi < 1; bi = bi + 1) begin + if ((mem_addra_int) == (mem_addrb_reg + bi)) begin + for (bj = 0; bj < 1; bj = bj + 1) begin + dob_out[bi + bj] <= #100 1'bX; + end + end + end + end + data_collision_b_a[0] <= 0; + end + + + // Port A + always @(posedge clka_int) begin + + if (ena_int == 1'b1) begin + + if (rsta_int == 1'b1) begin + doa_out <= #100 0; + end + else begin + if (wea_int == 1'b1) + doa_out <= #100 dia_int; + else + doa_out <= #100 mem[addra_int]; + end + + // memory + if (wea_int == 1'b1) begin + mem[addra_int] <= dia_int; + end + + end + end + + + // Port B + always @(posedge clkb_int) begin + + if (enb_int == 1'b1) begin + + if (rstb_int == 1'b1) begin + dob_out <= #100 0; + end + else begin + if (web_int == 1'b1) + dob_out <= #100 dib_int; + else + dob_out <= #100 mem[addrb_int]; + end + + // memory + if (web_int == 1'b1) begin + mem[addrb_int] <= dib_int; + end + + end + end + + +endmodule + +`endif diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/RAMB4_S1_S16.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/RAMB4_S1_S16.v new file mode 100644 index 0000000..b74bbab --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/RAMB4_S1_S16.v @@ -0,0 +1,1110 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/RAMB4_S1_S16.v,v 1.9 2007/02/22 01:58:06 wloo Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2005 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / 4K-Bit Data Dual Port Block RAM +// /___/ /\ Filename : RAMB4_S1_S16.v +// \ \ / \ Timestamp : Thu Mar 10 16:43:38 PST 2005 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// End Revision + +`ifdef legacy_model + +`timescale 1 ps / 1 ps + +module RAMB4_S1_S16 (DOA, DOB, ADDRA, ADDRB, CLKA, CLKB, DIA, DIB, ENA, ENB, RSTA, RSTB, WEA, WEB); + + parameter SIM_COLLISION_CHECK = "ALL"; + localparam SETUP_ALL = 100; + + parameter INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + + output [0:0] DOA; + reg [0:0] doa_out; + wire doa_out0; + + input [11:0] ADDRA; + input [0:0] DIA; + input ENA, CLKA, WEA, RSTA; + + output [15:0] DOB; + reg [15:0] dob_out; + wire dob_out0, dob_out1, dob_out2, dob_out3, dob_out4, dob_out5, dob_out6, dob_out7, dob_out8, dob_out9, dob_out10, dob_out11, dob_out12, dob_out13, dob_out14, dob_out15; + + input [7:0] ADDRB; + input [15:0] DIB; + input ENB, CLKB, WEB, RSTB; + + reg [4095:0] mem; + reg [8:0] count; + + reg [5:0] mi, mj, ai, aj, bi, bj, ci, cj, di, dj, ei, ej, fi, fj; + + wire [11:0] addra_int; + reg [11:0] addra_reg; + wire [0:0] dia_int; + wire ena_int, clka_int, wea_int, rsta_int; + reg ena_reg, wea_reg, rsta_reg; + wire [7:0] addrb_int; + reg [7:0] addrb_reg; + wire [15:0] dib_int; + wire enb_int, clkb_int, web_int, rstb_int; + reg enb_reg, web_reg, rstb_reg; + + time time_clka, time_clkb; + time time_clka_clkb; + time time_clkb_clka; + + reg setup_all_a_b; + reg setup_all_b_a; + reg setup_zero; + reg [1:0] data_collision, data_collision_a_b, data_collision_b_a; + reg memory_collision, memory_collision_a_b, memory_collision_b_a; + reg address_collision, address_collision_a_b, address_collision_b_a; + reg change_clka; + reg change_clkb; + + wire [11:0] mem_addra_int; + wire [11:0] mem_addra_reg; + wire [11:0] mem_addrb_int; + wire [11:0] mem_addrb_reg; + + tri0 GSR = glbl.GSR; + + always @(GSR) + if (GSR) begin + assign doa_out = 0; + end + else begin + deassign doa_out; + end + + always @(GSR) + if (GSR) begin + assign dob_out = 0; + end + else begin + deassign dob_out; + end + + buf b_doa_out0 (doa_out0, doa_out[0]); + buf b_dob_out0 (dob_out0, dob_out[0]); + buf b_dob_out1 (dob_out1, dob_out[1]); + buf b_dob_out2 (dob_out2, dob_out[2]); + buf b_dob_out3 (dob_out3, dob_out[3]); + buf b_dob_out4 (dob_out4, dob_out[4]); + buf b_dob_out5 (dob_out5, dob_out[5]); + buf b_dob_out6 (dob_out6, dob_out[6]); + buf b_dob_out7 (dob_out7, dob_out[7]); + buf b_dob_out8 (dob_out8, dob_out[8]); + buf b_dob_out9 (dob_out9, dob_out[9]); + buf b_dob_out10 (dob_out10, dob_out[10]); + buf b_dob_out11 (dob_out11, dob_out[11]); + buf b_dob_out12 (dob_out12, dob_out[12]); + buf b_dob_out13 (dob_out13, dob_out[13]); + buf b_dob_out14 (dob_out14, dob_out[14]); + buf b_dob_out15 (dob_out15, dob_out[15]); + buf b_doa0 (DOA[0], doa_out0); + buf b_dob0 (DOB[0], dob_out0); + buf b_dob1 (DOB[1], dob_out1); + buf b_dob2 (DOB[2], dob_out2); + buf b_dob3 (DOB[3], dob_out3); + buf b_dob4 (DOB[4], dob_out4); + buf b_dob5 (DOB[5], dob_out5); + buf b_dob6 (DOB[6], dob_out6); + buf b_dob7 (DOB[7], dob_out7); + buf b_dob8 (DOB[8], dob_out8); + buf b_dob9 (DOB[9], dob_out9); + buf b_dob10 (DOB[10], dob_out10); + buf b_dob11 (DOB[11], dob_out11); + buf b_dob12 (DOB[12], dob_out12); + buf b_dob13 (DOB[13], dob_out13); + buf b_dob14 (DOB[14], dob_out14); + buf b_dob15 (DOB[15], dob_out15); + buf b_addra_0 (addra_int[0], ADDRA[0]); + buf b_addra_1 (addra_int[1], ADDRA[1]); + buf b_addra_2 (addra_int[2], ADDRA[2]); + buf b_addra_3 (addra_int[3], ADDRA[3]); + buf b_addra_4 (addra_int[4], ADDRA[4]); + buf b_addra_5 (addra_int[5], ADDRA[5]); + buf b_addra_6 (addra_int[6], ADDRA[6]); + buf b_addra_7 (addra_int[7], ADDRA[7]); + buf b_addra_8 (addra_int[8], ADDRA[8]); + buf b_addra_9 (addra_int[9], ADDRA[9]); + buf b_addra_10 (addra_int[10], ADDRA[10]); + buf b_addra_11 (addra_int[11], ADDRA[11]); + buf b_dia_0 (dia_int[0], DIA[0]); + buf b_clka (clka_int, CLKA); + buf b_ena (ena_int, ENA); + buf b_rsta (rsta_int, RSTA); + buf b_wea (wea_int, WEA); + buf b_addrb_0 (addrb_int[0], ADDRB[0]); + buf b_addrb_1 (addrb_int[1], ADDRB[1]); + buf b_addrb_2 (addrb_int[2], ADDRB[2]); + buf b_addrb_3 (addrb_int[3], ADDRB[3]); + buf b_addrb_4 (addrb_int[4], ADDRB[4]); + buf b_addrb_5 (addrb_int[5], ADDRB[5]); + buf b_addrb_6 (addrb_int[6], ADDRB[6]); + buf b_addrb_7 (addrb_int[7], ADDRB[7]); + buf b_dib_0 (dib_int[0], DIB[0]); + buf b_dib_1 (dib_int[1], DIB[1]); + buf b_dib_2 (dib_int[2], DIB[2]); + buf b_dib_3 (dib_int[3], DIB[3]); + buf b_dib_4 (dib_int[4], DIB[4]); + buf b_dib_5 (dib_int[5], DIB[5]); + buf b_dib_6 (dib_int[6], DIB[6]); + buf b_dib_7 (dib_int[7], DIB[7]); + buf b_dib_8 (dib_int[8], DIB[8]); + buf b_dib_9 (dib_int[9], DIB[9]); + buf b_dib_10 (dib_int[10], DIB[10]); + buf b_dib_11 (dib_int[11], DIB[11]); + buf b_dib_12 (dib_int[12], DIB[12]); + buf b_dib_13 (dib_int[13], DIB[13]); + buf b_dib_14 (dib_int[14], DIB[14]); + buf b_dib_15 (dib_int[15], DIB[15]); + buf b_clkb (clkb_int, CLKB); + buf b_enb (enb_int, ENB); + buf b_rstb (rstb_int, RSTB); + buf b_web (web_int, WEB); + + initial begin + for (count = 0; count < 256; count = count + 1) begin + mem[count] <= INIT_00[count]; + mem[256 * 1 + count] <= INIT_01[count]; + mem[256 * 2 + count] <= INIT_02[count]; + mem[256 * 3 + count] <= INIT_03[count]; + mem[256 * 4 + count] <= INIT_04[count]; + mem[256 * 5 + count] <= INIT_05[count]; + mem[256 * 6 + count] <= INIT_06[count]; + mem[256 * 7 + count] <= INIT_07[count]; + mem[256 * 8 + count] <= INIT_08[count]; + mem[256 * 9 + count] <= INIT_09[count]; + mem[256 * 10 + count] <= INIT_0A[count]; + mem[256 * 11 + count] <= INIT_0B[count]; + mem[256 * 12 + count] <= INIT_0C[count]; + mem[256 * 13 + count] <= INIT_0D[count]; + mem[256 * 14 + count] <= INIT_0E[count]; + mem[256 * 15 + count] <= INIT_0F[count]; + end + address_collision <= 0; + address_collision_a_b <= 0; + address_collision_b_a <= 0; + change_clka <= 0; + change_clkb <= 0; + data_collision <= 0; + data_collision_a_b <= 0; + data_collision_b_a <= 0; + memory_collision <= 0; + memory_collision_a_b <= 0; + memory_collision_b_a <= 0; + setup_all_a_b <= 0; + setup_all_b_a <= 0; + setup_zero <= 0; + end + + assign mem_addra_int = addra_int * 1; + assign mem_addra_reg = addra_reg * 1; + assign mem_addrb_int = addrb_int * 16; + assign mem_addrb_reg = addrb_reg * 16; + + + initial begin + + case (SIM_COLLISION_CHECK) + + "NONE" : begin + assign setup_all_a_b = 1'b0; + assign setup_all_b_a = 1'b0; + assign setup_zero = 1'b0; + assign address_collision = 1'b0; + assign address_collision_a_b = 1'b0; + assign address_collision_b_a = 1'b0; + end + "WARNING_ONLY" : begin + assign data_collision = 2'b00; + assign data_collision_a_b = 2'b00; + assign data_collision_b_a = 2'b00; + assign memory_collision = 1'b0; + assign memory_collision_a_b = 1'b0; + assign memory_collision_b_a = 1'b0; + end + "GENERATE_X_ONLY" : begin + assign address_collision = 1'b0; + assign address_collision_a_b = 1'b0; + assign address_collision_b_a = 1'b0; + end + "ALL" : ; + default : begin + $display("Attribute Syntax Error : The Attribute SIM_COLLISION_CHECK on RAMB4_S1_S16 instance %m is set to %s. Legal values for this attribute are ALL, NONE, WARNING_ONLY or GENERATE_X_ONLY.", SIM_COLLISION_CHECK); + $finish; + end + + endcase // case(SIM_COLLISION_CHECK) + + end // initial begin + + + always @(posedge clka_int) begin + time_clka = $time; + #0 time_clkb_clka = time_clka - time_clkb; + change_clka = ~change_clka; + end + + always @(posedge clkb_int) begin + time_clkb = $time; + #0 time_clka_clkb = time_clkb - time_clka; + change_clkb = ~change_clkb; + end + + always @(change_clkb) begin + if ((0 < time_clka_clkb) && (time_clka_clkb < SETUP_ALL)) + setup_all_a_b = 1; + end + + always @(change_clka) begin + if ((0 < time_clkb_clka) && (time_clkb_clka < SETUP_ALL)) + setup_all_b_a = 1; + end + + always @(change_clkb or change_clka) begin + if ((time_clkb_clka == 0) && (time_clka_clkb == 0)) + setup_zero = 1; + end + + always @(posedge setup_zero) begin + if ((ena_int == 1) && (wea_int == 1) && + (enb_int == 1) && (web_int == 1)) + memory_collision <= 1; + end + + always @(posedge setup_all_a_b) begin + if ((ena_reg == 1) && (enb_int == 1)) begin + case ({wea_reg, web_int}) + 6'b11 : begin data_collision_a_b <= 2'b11; display_all_a_b; end + 6'b01 : begin data_collision_a_b <= 2'b10; display_all_a_b; end + 6'b10 : begin data_collision_a_b <= 2'b01; display_all_a_b; end + endcase + end + setup_all_a_b <= 0; + end + + task display_all_a_b; + begin + address_collision_a_b = 1'b0; + for (ci = 0; ci < 16; ci = ci + 1) begin + if ((mem_addra_reg) == (mem_addrb_int + ci)) begin + address_collision_a_b = 1'b1; + end + end + if (address_collision_a_b == 1'b1) + + if (({wea_reg, web_int}) == 2'b11) + $display("Memory Collision Error on RAMB4_S1_S16:%m at simulation time %.3f ns\nA write was requested to the same address simultaneously at both Port A and Port B of the RAM. The contents written to the RAM at address location %h (hex) of Port A and address location %h (hex) of Port B are unknown.", $time/1000.0, addra_int, addrb_int); + + else if (({wea_reg, web_int}) == 2'b01) + $display("Memory Collision Error on RAMB4_S1_S16:%m at simulation time %.3f ns\nA read was performed on address %h (hex) of Port A while a write was requested to the same address on Port B. The write will be successful however the read value on Port A is unknown until the next CLKA cycle.", $time/1000.0, addra_int); + + else if (({wea_reg, web_int}) == 2'b10) + $display("Memory Collision Error on RAMB4_S1_S16:%m at simulation time %.3f ns\nA read was performed on address %h (hex) of Port B while a write was requested to the same address on Port A. The write will be successful however the read value on Port B is unknown until the next CLKB cycle.", $time/1000.0, addrb_int); + + end + endtask + + always @(posedge setup_all_b_a) begin + if ((ena_int == 1) && (enb_reg == 1)) begin + case ({wea_int, web_reg}) + 6'b11 : begin data_collision_b_a <= 2'b11; display_all_b_a; end + 6'b01 : begin data_collision_b_a <= 2'b10; display_all_b_a; end + 6'b10 : begin data_collision_b_a <= 2'b01; display_all_b_a; end + endcase + end + setup_all_b_a <= 0; + end + + task display_all_b_a; + begin + address_collision_b_a = 1'b0; + for (ci = 0; ci < 16; ci = ci + 1) begin + if ((mem_addra_int) == (mem_addrb_reg + ci)) begin + address_collision_b_a = 1'b1; + end + end + if (address_collision_b_a == 1'b1) + + if (({wea_int, web_reg}) == 2'b11) + $display("Memory Collision Error on RAMB4_S1_S16:%m at simulation time %.3f ns\nA write was requested to the same address simultaneously at both Port A and Port B of the RAM. The contents written to the RAM at address location %h (hex) of Port A and address location %h (hex) of Port B are unknown.", $time/1000.0, addra_int, addrb_int); + + else if (({wea_int, web_reg}) == 2'b01) + $display("Memory Collision Error on RAMB4_S1_S16:%m at simulation time %.3f ns\nA read was performed on address %h (hex) of Port A while a write was requested to the same address on Port B. The write will be successful however the read value on Port A is unknown until the next CLKA cycle.", $time/1000.0, addra_int); + + else if (({wea_int, web_reg}) == 2'b10) + $display("Memory Collision Error on RAMB4_S1_S16:%m at simulation time %.3f ns\nA read was performed on address %h (hex) of Port B while a write was requested to the same address on Port A. The write will be successful however the read value on Port B is unknown until the next CLKB cycle.", $time/1000.0, addrb_int); + + end + endtask + + always @(posedge setup_zero) begin + if ((ena_int == 1) && (enb_int == 1)) begin + case ({wea_int, web_int}) + 6'b11 : begin data_collision <= 2'b11; display_zero; end + 6'b01 : begin data_collision <= 2'b10; display_zero; end + 6'b10 : begin data_collision <= 2'b01; display_zero; end + endcase + end + setup_zero <= 0; + end + + task display_zero; + begin + address_collision = 1'b0; + for (ci = 0; ci < 16; ci = ci + 1) begin + if ((mem_addra_int) == (mem_addrb_int + ci)) begin + address_collision = 1'b1; + end + end + if (address_collision == 1'b1) + + if (({wea_int, web_int}) == 2'b11) + $display("Memory Collision Error on RAMB4_S1_S16:%m at simulation time %.3f ns\nA write was requested to the same address simultaneously at both Port A and Port B of the RAM. The contents written to the RAM at address location %h (hex) of Port A and address location %h (hex) of Port B are unknown.", $time/1000.0, addra_int, addrb_int); + + else if (({wea_int, web_int}) == 2'b01) + $display("Memory Collision Error on RAMB4_S1_S16:%m at simulation time %.3f ns\nA read was performed on address %h (hex) of Port A while a write was requested to the same address on Port B. The write will be successful however the read value on Port A is unknown until the next CLKA cycle.", $time/1000.0, addra_int); + + else if (({wea_int, web_int}) == 2'b10) + $display("Memory Collision Error on RAMB4_S1_S16:%m at simulation time %.3f ns\nA read was performed on address %h (hex) of Port B while a write was requested to the same address on Port A. The write will be successful however the read value on Port B is unknown until the next CLKB cycle.", $time/1000.0, addrb_int); + + end + endtask + + always @(posedge clka_int) begin + addra_reg <= addra_int; + ena_reg <= ena_int; + rsta_reg <= rsta_int; + wea_reg <= wea_int; + end + + always @(posedge clkb_int) begin + addrb_reg <= addrb_int; + enb_reg <= enb_int; + rstb_reg <= rstb_int; + web_reg <= web_int; + end + + // Data + always @(posedge memory_collision) begin + for (mi = 0; mi < 16; mi = mi + 1) begin + if ((mem_addra_int) == (mem_addrb_int + mi)) begin + for (mj = 0; mj < 1; mj = mj + 1) begin + mem[mem_addrb_int + mi + mj] <= 1'bX; + end + end + end + memory_collision <= 0; + end + + always @(posedge memory_collision_a_b) begin + for (mi = 0; mi < 16; mi = mi + 1) begin + if ((mem_addra_reg) == (mem_addrb_int + mi)) begin + for (mj = 0; mj < 1; mj = mj + 1) begin + mem[mem_addrb_int + mi + mj] <= 1'bX; + end + end + end + memory_collision_a_b <= 0; + end + + always @(posedge memory_collision_b_a) begin + for (mi = 0; mi < 16; mi = mi + 1) begin + if ((mem_addra_int) == (mem_addrb_reg + mi)) begin + for (mj = 0; mj < 1; mj = mj + 1) begin + mem[mem_addrb_reg + mi + mj] <= 1'bX; + end + end + end + memory_collision_b_a <= 0; + end + + always @(posedge data_collision[1]) begin + if (rsta_int == 0) begin + for (ai = 0; ai < 16; ai = ai + 1) begin + if ((mem_addra_int) == (mem_addrb_int + ai)) begin + doa_out <= 1'bX; + end + end + end + data_collision[1] <= 0; + end + + always @(posedge data_collision[0]) begin + if (rstb_int == 0) begin + for (bi = 0; bi < 16; bi = bi + 1) begin + if ((mem_addra_int) == (mem_addrb_int + bi)) begin + for (bj = 0; bj < 1; bj = bj + 1) begin + dob_out[bi + bj] <= 1'bX; + end + end + end + end + data_collision[0] <= 0; + end + + always @(posedge data_collision_a_b[1]) begin + if (rsta_reg == 0) begin + for (ai = 0; ai < 16; ai = ai + 1) begin + if ((mem_addra_reg) == (mem_addrb_int + ai)) begin + doa_out <= 1'bX; + end + end + end + data_collision_a_b[1] <= 0; + end + + always @(posedge data_collision_a_b[0]) begin + if (rstb_int == 0) begin + for (bi = 0; bi < 16; bi = bi + 1) begin + if ((mem_addra_reg) == (mem_addrb_int + bi)) begin + for (bj = 0; bj < 1; bj = bj + 1) begin + dob_out[bi + bj] <= 1'bX; + end + end + end + end + data_collision_a_b[0] <= 0; + end + + always @(posedge data_collision_b_a[1]) begin + if (rsta_int == 0) begin + for (ai = 0; ai < 16; ai = ai + 1) begin + if ((mem_addra_int) == (mem_addrb_reg + ai)) begin + doa_out <= 1'bX; + end + end + end + data_collision_b_a[1] <= 0; + end + + always @(posedge data_collision_b_a[0]) begin + if (rstb_reg == 0) begin + for (bi = 0; bi < 16; bi = bi + 1) begin + if ((mem_addra_int) == (mem_addrb_reg + bi)) begin + for (bj = 0; bj < 1; bj = bj + 1) begin + dob_out[bi + bj] <= 1'bX; + end + end + end + end + data_collision_b_a[0] <= 0; + end + + + always @(posedge clka_int) begin + if (ena_int == 1'b1) begin + if (rsta_int == 1'b1) begin + doa_out <= 1'b0; + end + else if (wea_int == 0) begin + doa_out[0] <= mem[mem_addra_int + 0]; + end + else begin + doa_out <= dia_int; + end + end + end + + always @(posedge clka_int) begin + if (ena_int == 1'b1 && wea_int == 1'b1) begin + mem[mem_addra_int + 0] <= dia_int[0]; + end + end + + always @(posedge clkb_int) begin + if (enb_int == 1'b1) begin + if (rstb_int == 1'b1) begin + dob_out <= 16'b0; + end + else if (web_int == 0) begin + dob_out[0] <= mem[mem_addrb_int + 0]; + dob_out[1] <= mem[mem_addrb_int + 1]; + dob_out[2] <= mem[mem_addrb_int + 2]; + dob_out[3] <= mem[mem_addrb_int + 3]; + dob_out[4] <= mem[mem_addrb_int + 4]; + dob_out[5] <= mem[mem_addrb_int + 5]; + dob_out[6] <= mem[mem_addrb_int + 6]; + dob_out[7] <= mem[mem_addrb_int + 7]; + dob_out[8] <= mem[mem_addrb_int + 8]; + dob_out[9] <= mem[mem_addrb_int + 9]; + dob_out[10] <= mem[mem_addrb_int + 10]; + dob_out[11] <= mem[mem_addrb_int + 11]; + dob_out[12] <= mem[mem_addrb_int + 12]; + dob_out[13] <= mem[mem_addrb_int + 13]; + dob_out[14] <= mem[mem_addrb_int + 14]; + dob_out[15] <= mem[mem_addrb_int + 15]; + end + else begin + dob_out <= dib_int; + end + end + end + + always @(posedge clkb_int) begin + if (enb_int == 1'b1 && web_int == 1'b1) begin + mem[mem_addrb_int + 0] <= dib_int[0]; + mem[mem_addrb_int + 1] <= dib_int[1]; + mem[mem_addrb_int + 2] <= dib_int[2]; + mem[mem_addrb_int + 3] <= dib_int[3]; + mem[mem_addrb_int + 4] <= dib_int[4]; + mem[mem_addrb_int + 5] <= dib_int[5]; + mem[mem_addrb_int + 6] <= dib_int[6]; + mem[mem_addrb_int + 7] <= dib_int[7]; + mem[mem_addrb_int + 8] <= dib_int[8]; + mem[mem_addrb_int + 9] <= dib_int[9]; + mem[mem_addrb_int + 10] <= dib_int[10]; + mem[mem_addrb_int + 11] <= dib_int[11]; + mem[mem_addrb_int + 12] <= dib_int[12]; + mem[mem_addrb_int + 13] <= dib_int[13]; + mem[mem_addrb_int + 14] <= dib_int[14]; + mem[mem_addrb_int + 15] <= dib_int[15]; + end + end + + specify + (CLKA *> DOA) = (100, 100); + (CLKB *> DOB) = (100, 100); + endspecify + +endmodule + +`else + +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/RAMB4_S1_S16.v,v 1.9 2007/02/22 01:58:06 wloo Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2005 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Timing Simulation Library Component +// / / 16K-Bit Data and 2K-Bit Parity Dual Port Block RAM +// /___/ /\ Filename : RAMB4_S1_S16.v +// \ \ / \ Timestamp : Thu Mar 10 16:44:01 PST 2005 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 03/10/05 - Initialized outputs. +// 02/21/07 - Fixed parameter SIM_COLLISION_CHECK (CR 433281). +// End Revision + +`timescale 1 ps/1 ps + +module RAMB4_S1_S16 (DOA, DOB, ADDRA, ADDRB, CLKA, CLKB, DIA, DIB, ENA, ENB, RSTA, RSTB, WEA, WEB); + + parameter SIM_COLLISION_CHECK = "ALL"; + localparam SETUP_ALL = 100; + + parameter INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + + output [0:0] DOA; + output [15:0] DOB; + + input [11:0] ADDRA; + input [0:0] DIA; + input ENA, CLKA, WEA, RSTA; + input [7:0] ADDRB; + input [15:0] DIB; + input ENB, CLKB, WEB, RSTB; + + reg [0:0] doa_out = 0; + reg [15:0] dob_out = 0; + + reg [15:0] mem [255:0]; + + reg [8:0] count; + + reg [5:0] mi, ai, bi, bj, ci; + + wire [11:0] addra_int; + reg [11:0] addra_reg; + wire [0:0] dia_int; + wire ena_int, clka_int, wea_int, rsta_int; + reg ena_reg, wea_reg, rsta_reg; + wire [7:0] addrb_int; + reg [7:0] addrb_reg; + wire [15:0] dib_int; + wire enb_int, clkb_int, web_int, rstb_int; + reg display_flag, output_flag; + reg enb_reg, web_reg, rstb_reg; + + time time_clka, time_clkb; + time time_clka_clkb; + time time_clkb_clka; + + reg setup_all_a_b; + reg setup_all_b_a; + reg setup_zero; + reg [1:0] data_collision, data_collision_a_b, data_collision_b_a; + reg memory_collision, memory_collision_a_b, memory_collision_b_a; + reg address_collision, address_collision_a_b, address_collision_b_a; + reg change_clka; + reg change_clkb; + + wire [11:0] mem_addra_int; + wire [11:0] mem_addra_reg; + wire [11:0] mem_addrb_int; + wire [11:0] mem_addrb_reg; + + wire dia_enable = ena_int && wea_int; + wire dib_enable = enb_int && web_int; + + tri0 GSR = glbl.GSR; + wire gsr_int; + + buf b_gsr (gsr_int, GSR); + + buf b_doa [0:0] (DOA, doa_out); + buf b_addra [11:0] (addra_int, ADDRA); + buf b_dia [0:0] (dia_int, DIA); + buf b_ena (ena_int, ENA); + buf b_clka (clka_int, CLKA); + buf b_rsta (rsta_int, RSTA); + buf b_wea (wea_int, WEA); + + buf b_dob [15:0] (DOB, dob_out); + buf b_addrb [7:0] (addrb_int, ADDRB); + buf b_dib [15:0] (dib_int, DIB); + buf b_enb (enb_int, ENB); + buf b_clkb (clkb_int, CLKB); + buf b_rstb (rstb_int, RSTB); + buf b_web (web_int, WEB); + + + always @(gsr_int) + if (gsr_int) begin + assign doa_out = 0; + assign dob_out = 0; + end + else begin + deassign doa_out; + deassign dob_out; + end + + + initial begin + + for (count = 0; count < 16; count = count + 1) begin + mem[count] = INIT_00[(count * 16) +: 16]; + mem[16 * 1 + count] = INIT_01[(count * 16) +: 16]; + mem[16 * 2 + count] = INIT_02[(count * 16) +: 16]; + mem[16 * 3 + count] = INIT_03[(count * 16) +: 16]; + mem[16 * 4 + count] = INIT_04[(count * 16) +: 16]; + mem[16 * 5 + count] = INIT_05[(count * 16) +: 16]; + mem[16 * 6 + count] = INIT_06[(count * 16) +: 16]; + mem[16 * 7 + count] = INIT_07[(count * 16) +: 16]; + mem[16 * 8 + count] = INIT_08[(count * 16) +: 16]; + mem[16 * 9 + count] = INIT_09[(count * 16) +: 16]; + mem[16 * 10 + count] = INIT_0A[(count * 16) +: 16]; + mem[16 * 11 + count] = INIT_0B[(count * 16) +: 16]; + mem[16 * 12 + count] = INIT_0C[(count * 16) +: 16]; + mem[16 * 13 + count] = INIT_0D[(count * 16) +: 16]; + mem[16 * 14 + count] = INIT_0E[(count * 16) +: 16]; + mem[16 * 15 + count] = INIT_0F[(count * 16) +: 16]; + end + + change_clka <= 0; + change_clkb <= 0; + data_collision <= 0; + data_collision_a_b <= 0; + data_collision_b_a <= 0; + memory_collision <= 0; + memory_collision_a_b <= 0; + memory_collision_b_a <= 0; + setup_all_a_b <= 0; + setup_all_b_a <= 0; + setup_zero <= 0; + end + + assign mem_addra_int = addra_int * 1; + assign mem_addra_reg = addra_reg * 1; + assign mem_addrb_int = addrb_int * 16; + assign mem_addrb_reg = addrb_reg * 16; + + + initial begin + + display_flag = 1; + output_flag = 1; + + case (SIM_COLLISION_CHECK) + + "NONE" : begin + output_flag = 0; + display_flag = 0; + end + "WARNING_ONLY" : output_flag = 0; + "GENERATE_X_ONLY" : display_flag = 0; + "ALL" : ; + + default : begin + $display("Attribute Syntax Error : The Attribute SIM_COLLISION_CHECK on RAMB4_S1_S16 instance %m is set to %s. Legal values for this attribute are ALL, NONE, WARNING_ONLY or GENERATE_X_ONLY.", SIM_COLLISION_CHECK); + $finish; + end + + endcase // case(SIM_COLLISION_CHECK) + + end // initial begin + + + always @(posedge clka_int) begin + if ((output_flag || display_flag)) begin + time_clka = $time; + #0 time_clkb_clka = time_clka - time_clkb; + change_clka = ~change_clka; + end + end + + always @(posedge clkb_int) begin + if ((output_flag || display_flag)) begin + time_clkb = $time; + #0 time_clka_clkb = time_clkb - time_clka; + change_clkb = ~change_clkb; + end + end + + always @(change_clkb) begin + if ((0 < time_clka_clkb) && (time_clka_clkb < SETUP_ALL)) + setup_all_a_b = 1; + end + + always @(change_clka) begin + if ((0 < time_clkb_clka) && (time_clkb_clka < SETUP_ALL)) + setup_all_b_a = 1; + end + + always @(change_clkb or change_clka) begin + if ((time_clkb_clka == 0) && (time_clka_clkb == 0)) + setup_zero = 1; + end + + always @(posedge setup_zero) begin + if ((ena_int == 1) && (wea_int == 1) && + (enb_int == 1) && (web_int == 1)) + memory_collision <= 1; + end + + always @(posedge setup_all_a_b) begin + if ((ena_reg == 1) && (enb_int == 1)) begin + case ({wea_reg, web_int}) + 6'b11 : begin data_collision_a_b <= 2'b11; display_all_a_b; end + 6'b01 : begin data_collision_a_b <= 2'b10; display_all_a_b; end + 6'b10 : begin data_collision_a_b <= 2'b01; display_all_a_b; end + endcase + end + setup_all_a_b <= 0; + end + + task display_all_a_b; + begin + address_collision_a_b = 1'b0; + for (ci = 0; ci < 16; ci = ci + 1) begin + if ((mem_addra_reg) == (mem_addrb_int + ci)) begin + address_collision_a_b = 1'b1; + end + end + if (address_collision_a_b == 1'b1 && display_flag) + + if (({wea_reg, web_int}) == 2'b11) + $display("Memory Collision Error on RAMB4_S1_S16:%m at simulation time %.3f ns\nA write was requested to the same address simultaneously at both Port A and Port B of the RAM. The contents written to the RAM at address location %h (hex) of Port A and address location %h (hex) of Port B are unknown.", $time/1000.0, addra_int, addrb_int); + + else if (({wea_reg, web_int}) == 2'b01) + $display("Memory Collision Error on RAMB4_S1_S16:%m at simulation time %.3f ns\nA read was performed on address %h (hex) of Port A while a write was requested to the same address on Port B. The write will be successful however the read value on Port A is unknown until the next CLKA cycle.", $time/1000.0, addra_int); + + else if (({wea_reg, web_int}) == 2'b10) + $display("Memory Collision Error on RAMB4_S1_S16:%m at simulation time %.3f ns\nA read was performed on address %h (hex) of Port B while a write was requested to the same address on Port A. The write will be successful however the read value on Port B is unknown until the next CLKB cycle.", $time/1000.0, addrb_int); + + end + endtask + + always @(posedge setup_all_b_a) begin + if ((ena_int == 1) && (enb_reg == 1)) begin + case ({wea_int, web_reg}) + 6'b11 : begin data_collision_b_a <= 2'b11; display_all_b_a; end + 6'b01 : begin data_collision_b_a <= 2'b10; display_all_b_a; end + 6'b10 : begin data_collision_b_a <= 2'b01; display_all_b_a; end + endcase + end + setup_all_b_a <= 0; + end + + task display_all_b_a; + begin + address_collision_b_a = 1'b0; + for (ci = 0; ci < 16; ci = ci + 1) begin + if ((mem_addra_int) == (mem_addrb_reg + ci)) begin + address_collision_b_a = 1'b1; + end + end + if (address_collision_b_a == 1'b1 && display_flag) + + if (({wea_int, web_reg}) == 2'b11) + $display("Memory Collision Error on RAMB4_S1_S16:%m at simulation time %.3f ns\nA write was requested to the same address simultaneously at both Port A and Port B of the RAM. The contents written to the RAM at address location %h (hex) of Port A and address location %h (hex) of Port B are unknown.", $time/1000.0, addra_int, addrb_int); + + else if (({wea_int, web_reg}) == 2'b01) + $display("Memory Collision Error on RAMB4_S1_S16:%m at simulation time %.3f ns\nA read was performed on address %h (hex) of Port A while a write was requested to the same address on Port B. The write will be successful however the read value on Port A is unknown until the next CLKA cycle.", $time/1000.0, addra_int); + + else if (({wea_int, web_reg}) == 2'b10) + $display("Memory Collision Error on RAMB4_S1_S16:%m at simulation time %.3f ns\nA read was performed on address %h (hex) of Port B while a write was requested to the same address on Port A. The write will be successful however the read value on Port B is unknown until the next CLKB cycle.", $time/1000.0, addrb_int); + + end + endtask + + always @(posedge setup_zero) begin + if ((ena_int == 1) && (enb_int == 1)) begin + case ({wea_int, web_int}) + 6'b11 : begin data_collision <= 2'b11; display_zero; end + 6'b01 : begin data_collision <= 2'b10; display_zero; end + 6'b10 : begin data_collision <= 2'b01; display_zero; end + endcase + end + setup_zero <= 0; + end + + task display_zero; + begin + address_collision = 1'b0; + for (ci = 0; ci < 16; ci = ci + 1) begin + if ((mem_addra_int) == (mem_addrb_int + ci)) begin + address_collision = 1'b1; + end + end + if (address_collision == 1'b1 && display_flag) + + if (({wea_int, web_int}) == 2'b11) + $display("Memory Collision Error on RAMB4_S1_S16:%m at simulation time %.3f ns\nA write was requested to the same address simultaneously at both Port A and Port B of the RAM. The contents written to the RAM at address location %h (hex) of Port A and address location %h (hex) of Port B are unknown.", $time/1000.0, addra_int, addrb_int); + + else if (({wea_int, web_int}) == 2'b01) + $display("Memory Collision Error on RAMB4_S1_S16:%m at simulation time %.3f ns\nA read was performed on address %h (hex) of Port A while a write was requested to the same address on Port B. The write will be successful however the read value on Port A is unknown until the next CLKA cycle.", $time/1000.0, addra_int); + + else if (({wea_int, web_int}) == 2'b10) + $display("Memory Collision Error on RAMB4_S1_S16:%m at simulation time %.3f ns\nA read was performed on address %h (hex) of Port B while a write was requested to the same address on Port A. The write will be successful however the read value on Port B is unknown until the next CLKB cycle.", $time/1000.0, addrb_int); + + end + endtask + + always @(posedge clka_int) begin + if ((output_flag || display_flag)) begin + addra_reg <= addra_int; + ena_reg <= ena_int; + rsta_reg <= rsta_int; + wea_reg <= wea_int; + end + end + + always @(posedge clkb_int) begin + if ((output_flag || display_flag)) begin + addrb_reg <= addrb_int; + enb_reg <= enb_int; + rstb_reg <= rstb_int; + web_reg <= web_int; + end + end + + + // Data + always @(posedge memory_collision) begin + if ((output_flag || display_flag)) begin + for (mi = 0; mi < 16; mi = mi + 1) begin + if ((mem_addra_int) == (mem_addrb_int + mi)) begin + mem[addra_int[11:4]][addra_int[3:0] * 1 +: 1] <= 1'bx; + end + end + memory_collision <= 0; + end + end + + always @(posedge memory_collision_a_b) begin + if ((output_flag || display_flag)) begin + for (mi = 0; mi < 16; mi = mi + 1) begin + if ((mem_addra_reg) == (mem_addrb_int + mi)) begin + mem[addra_reg[11:4]][addra_reg[3:0] * 1 +: 1] <= 1'bx; + end + end + memory_collision_a_b <= 0; + end + end + + always @(posedge memory_collision_b_a) begin + if ((output_flag || display_flag)) begin + for (mi = 0; mi < 16; mi = mi + 1) begin + if ((mem_addra_int) == (mem_addrb_reg + mi)) begin + mem[addra_int[11:4]][addra_int[3:0] * 1 +: 1] <= 1'bx; + end + end + memory_collision_b_a <= 0; + end + end + + always @(posedge data_collision[1]) begin + if (rsta_int == 0 && output_flag) begin + for (ai = 0; ai < 16; ai = ai + 1) begin + if ((mem_addra_int) == (mem_addrb_int + ai)) begin + doa_out <= #100 1'bX; + end + end + end + data_collision[1] <= 0; + end + + always @(posedge data_collision[0]) begin + if (rstb_int == 0 && output_flag) begin + for (bi = 0; bi < 16; bi = bi + 1) begin + if ((mem_addra_int) == (mem_addrb_int + bi)) begin + for (bj = 0; bj < 1; bj = bj + 1) begin + dob_out[bi + bj] <= #100 1'bX; + end + end + end + end + data_collision[0] <= 0; + end + + always @(posedge data_collision_a_b[1]) begin + if (rsta_reg == 0 && output_flag) begin + for (ai = 0; ai < 16; ai = ai + 1) begin + if ((mem_addra_reg) == (mem_addrb_int + ai)) begin + doa_out <= #100 1'bX; + end + end + end + data_collision_a_b[1] <= 0; + end + + always @(posedge data_collision_a_b[0]) begin + if (rstb_int == 0 && output_flag) begin + for (bi = 0; bi < 16; bi = bi + 1) begin + if ((mem_addra_reg) == (mem_addrb_int + bi)) begin + for (bj = 0; bj < 1; bj = bj + 1) begin + dob_out[bi + bj] <= #100 1'bX; + end + end + end + end + data_collision_a_b[0] <= 0; + end + + always @(posedge data_collision_b_a[1]) begin + if (rsta_int == 0 && output_flag) begin + for (ai = 0; ai < 16; ai = ai + 1) begin + if ((mem_addra_int) == (mem_addrb_reg + ai)) begin + doa_out <= #100 1'bX; + end + end + end + data_collision_b_a[1] <= 0; + end + + always @(posedge data_collision_b_a[0]) begin + if (rstb_reg == 0 && output_flag) begin + for (bi = 0; bi < 16; bi = bi + 1) begin + if ((mem_addra_int) == (mem_addrb_reg + bi)) begin + for (bj = 0; bj < 1; bj = bj + 1) begin + dob_out[bi + bj] <= #100 1'bX; + end + end + end + end + data_collision_b_a[0] <= 0; + end + + + // Port A + always @(posedge clka_int) begin + + if (ena_int == 1'b1) begin + + if (rsta_int == 1'b1) begin + doa_out <= #100 0; + end + else begin + if (wea_int == 1'b1) + doa_out <= #100 dia_int; + else + doa_out <= #100 mem[addra_int[11:4]][addra_int[3:0] * 1 +: 1]; + end + + // memory + if (wea_int == 1'b1) begin + mem[addra_int[11:4]][addra_int[3:0] * 1 +: 1] <= dia_int; + end + + end + end + + + // Port B + always @(posedge clkb_int) begin + + if (enb_int == 1'b1) begin + + if (rstb_int == 1'b1) begin + dob_out <= #100 0; + end + else begin + if (web_int == 1'b1) + dob_out <= #100 dib_int; + else + dob_out <= #100 mem[addrb_int]; + end + + // memory + if (web_int == 1'b1) begin + mem[addrb_int] <= dib_int; + end + + end + end + + +endmodule + +`endif diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/RAMB4_S1_S2.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/RAMB4_S1_S2.v new file mode 100644 index 0000000..f09c39a --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/RAMB4_S1_S2.v @@ -0,0 +1,1043 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/RAMB4_S1_S2.v,v 1.9 2007/02/22 01:58:06 wloo Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2005 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / 4K-Bit Data Dual Port Block RAM +// /___/ /\ Filename : RAMB4_S1_S2.v +// \ \ / \ Timestamp : Thu Mar 10 16:43:38 PST 2005 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// End Revision + +`ifdef legacy_model + +`timescale 1 ps / 1 ps + +module RAMB4_S1_S2 (DOA, DOB, ADDRA, ADDRB, CLKA, CLKB, DIA, DIB, ENA, ENB, RSTA, RSTB, WEA, WEB); + + parameter SIM_COLLISION_CHECK = "ALL"; + localparam SETUP_ALL = 100; + + parameter INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + + output [0:0] DOA; + reg [0:0] doa_out; + wire doa_out0; + + input [11:0] ADDRA; + input [0:0] DIA; + input ENA, CLKA, WEA, RSTA; + + output [1:0] DOB; + reg [1:0] dob_out; + wire dob_out0, dob_out1; + + input [10:0] ADDRB; + input [1:0] DIB; + input ENB, CLKB, WEB, RSTB; + + reg [4095:0] mem; + reg [8:0] count; + + reg [5:0] mi, mj, ai, aj, bi, bj, ci, cj, di, dj, ei, ej, fi, fj; + + wire [11:0] addra_int; + reg [11:0] addra_reg; + wire [0:0] dia_int; + wire ena_int, clka_int, wea_int, rsta_int; + reg ena_reg, wea_reg, rsta_reg; + wire [10:0] addrb_int; + reg [10:0] addrb_reg; + wire [1:0] dib_int; + wire enb_int, clkb_int, web_int, rstb_int; + reg enb_reg, web_reg, rstb_reg; + + time time_clka, time_clkb; + time time_clka_clkb; + time time_clkb_clka; + + reg setup_all_a_b; + reg setup_all_b_a; + reg setup_zero; + reg [1:0] data_collision, data_collision_a_b, data_collision_b_a; + reg memory_collision, memory_collision_a_b, memory_collision_b_a; + reg address_collision, address_collision_a_b, address_collision_b_a; + reg change_clka; + reg change_clkb; + + wire [11:0] mem_addra_int; + wire [11:0] mem_addra_reg; + wire [11:0] mem_addrb_int; + wire [11:0] mem_addrb_reg; + + tri0 GSR = glbl.GSR; + + always @(GSR) + if (GSR) begin + assign doa_out = 0; + end + else begin + deassign doa_out; + end + + always @(GSR) + if (GSR) begin + assign dob_out = 0; + end + else begin + deassign dob_out; + end + + buf b_doa_out0 (doa_out0, doa_out[0]); + buf b_dob_out0 (dob_out0, dob_out[0]); + buf b_dob_out1 (dob_out1, dob_out[1]); + buf b_doa0 (DOA[0], doa_out0); + buf b_dob0 (DOB[0], dob_out0); + buf b_dob1 (DOB[1], dob_out1); + buf b_addra_0 (addra_int[0], ADDRA[0]); + buf b_addra_1 (addra_int[1], ADDRA[1]); + buf b_addra_2 (addra_int[2], ADDRA[2]); + buf b_addra_3 (addra_int[3], ADDRA[3]); + buf b_addra_4 (addra_int[4], ADDRA[4]); + buf b_addra_5 (addra_int[5], ADDRA[5]); + buf b_addra_6 (addra_int[6], ADDRA[6]); + buf b_addra_7 (addra_int[7], ADDRA[7]); + buf b_addra_8 (addra_int[8], ADDRA[8]); + buf b_addra_9 (addra_int[9], ADDRA[9]); + buf b_addra_10 (addra_int[10], ADDRA[10]); + buf b_addra_11 (addra_int[11], ADDRA[11]); + buf b_dia_0 (dia_int[0], DIA[0]); + buf b_clka (clka_int, CLKA); + buf b_ena (ena_int, ENA); + buf b_rsta (rsta_int, RSTA); + buf b_wea (wea_int, WEA); + buf b_addrb_0 (addrb_int[0], ADDRB[0]); + buf b_addrb_1 (addrb_int[1], ADDRB[1]); + buf b_addrb_2 (addrb_int[2], ADDRB[2]); + buf b_addrb_3 (addrb_int[3], ADDRB[3]); + buf b_addrb_4 (addrb_int[4], ADDRB[4]); + buf b_addrb_5 (addrb_int[5], ADDRB[5]); + buf b_addrb_6 (addrb_int[6], ADDRB[6]); + buf b_addrb_7 (addrb_int[7], ADDRB[7]); + buf b_addrb_8 (addrb_int[8], ADDRB[8]); + buf b_addrb_9 (addrb_int[9], ADDRB[9]); + buf b_addrb_10 (addrb_int[10], ADDRB[10]); + buf b_dib_0 (dib_int[0], DIB[0]); + buf b_dib_1 (dib_int[1], DIB[1]); + buf b_clkb (clkb_int, CLKB); + buf b_enb (enb_int, ENB); + buf b_rstb (rstb_int, RSTB); + buf b_web (web_int, WEB); + + initial begin + for (count = 0; count < 256; count = count + 1) begin + mem[count] <= INIT_00[count]; + mem[256 * 1 + count] <= INIT_01[count]; + mem[256 * 2 + count] <= INIT_02[count]; + mem[256 * 3 + count] <= INIT_03[count]; + mem[256 * 4 + count] <= INIT_04[count]; + mem[256 * 5 + count] <= INIT_05[count]; + mem[256 * 6 + count] <= INIT_06[count]; + mem[256 * 7 + count] <= INIT_07[count]; + mem[256 * 8 + count] <= INIT_08[count]; + mem[256 * 9 + count] <= INIT_09[count]; + mem[256 * 10 + count] <= INIT_0A[count]; + mem[256 * 11 + count] <= INIT_0B[count]; + mem[256 * 12 + count] <= INIT_0C[count]; + mem[256 * 13 + count] <= INIT_0D[count]; + mem[256 * 14 + count] <= INIT_0E[count]; + mem[256 * 15 + count] <= INIT_0F[count]; + end + address_collision <= 0; + address_collision_a_b <= 0; + address_collision_b_a <= 0; + change_clka <= 0; + change_clkb <= 0; + data_collision <= 0; + data_collision_a_b <= 0; + data_collision_b_a <= 0; + memory_collision <= 0; + memory_collision_a_b <= 0; + memory_collision_b_a <= 0; + setup_all_a_b <= 0; + setup_all_b_a <= 0; + setup_zero <= 0; + end + + assign mem_addra_int = addra_int * 1; + assign mem_addra_reg = addra_reg * 1; + assign mem_addrb_int = addrb_int * 2; + assign mem_addrb_reg = addrb_reg * 2; + + + initial begin + + case (SIM_COLLISION_CHECK) + + "NONE" : begin + assign setup_all_a_b = 1'b0; + assign setup_all_b_a = 1'b0; + assign setup_zero = 1'b0; + assign address_collision = 1'b0; + assign address_collision_a_b = 1'b0; + assign address_collision_b_a = 1'b0; + end + "WARNING_ONLY" : begin + assign data_collision = 2'b00; + assign data_collision_a_b = 2'b00; + assign data_collision_b_a = 2'b00; + assign memory_collision = 1'b0; + assign memory_collision_a_b = 1'b0; + assign memory_collision_b_a = 1'b0; + end + "GENERATE_X_ONLY" : begin + assign address_collision = 1'b0; + assign address_collision_a_b = 1'b0; + assign address_collision_b_a = 1'b0; + end + "ALL" : ; + default : begin + $display("Attribute Syntax Error : The Attribute SIM_COLLISION_CHECK on RAMB4_S1_S2 instance %m is set to %s. Legal values for this attribute are ALL, NONE, WARNING_ONLY or GENERATE_X_ONLY.", SIM_COLLISION_CHECK); + $finish; + end + + endcase // case(SIM_COLLISION_CHECK) + + end // initial begin + + + always @(posedge clka_int) begin + time_clka = $time; + #0 time_clkb_clka = time_clka - time_clkb; + change_clka = ~change_clka; + end + + always @(posedge clkb_int) begin + time_clkb = $time; + #0 time_clka_clkb = time_clkb - time_clka; + change_clkb = ~change_clkb; + end + + always @(change_clkb) begin + if ((0 < time_clka_clkb) && (time_clka_clkb < SETUP_ALL)) + setup_all_a_b = 1; + end + + always @(change_clka) begin + if ((0 < time_clkb_clka) && (time_clkb_clka < SETUP_ALL)) + setup_all_b_a = 1; + end + + always @(change_clkb or change_clka) begin + if ((time_clkb_clka == 0) && (time_clka_clkb == 0)) + setup_zero = 1; + end + + always @(posedge setup_zero) begin + if ((ena_int == 1) && (wea_int == 1) && + (enb_int == 1) && (web_int == 1)) + memory_collision <= 1; + end + + always @(posedge setup_all_a_b) begin + if ((ena_reg == 1) && (enb_int == 1)) begin + case ({wea_reg, web_int}) + 6'b11 : begin data_collision_a_b <= 2'b11; display_all_a_b; end + 6'b01 : begin data_collision_a_b <= 2'b10; display_all_a_b; end + 6'b10 : begin data_collision_a_b <= 2'b01; display_all_a_b; end + endcase + end + setup_all_a_b <= 0; + end + + task display_all_a_b; + begin + address_collision_a_b = 1'b0; + for (ci = 0; ci < 2; ci = ci + 1) begin + if ((mem_addra_reg) == (mem_addrb_int + ci)) begin + address_collision_a_b = 1'b1; + end + end + if (address_collision_a_b == 1'b1) + + if (({wea_reg, web_int}) == 2'b11) + $display("Memory Collision Error on RAMB4_S1_S2:%m at simulation time %.3f ns\nA write was requested to the same address simultaneously at both Port A and Port B of the RAM. The contents written to the RAM at address location %h (hex) of Port A and address location %h (hex) of Port B are unknown.", $time/1000.0, addra_int, addrb_int); + + else if (({wea_reg, web_int}) == 2'b01) + $display("Memory Collision Error on RAMB4_S1_S2:%m at simulation time %.3f ns\nA read was performed on address %h (hex) of Port A while a write was requested to the same address on Port B. The write will be successful however the read value on Port A is unknown until the next CLKA cycle.", $time/1000.0, addra_int); + + else if (({wea_reg, web_int}) == 2'b10) + $display("Memory Collision Error on RAMB4_S1_S2:%m at simulation time %.3f ns\nA read was performed on address %h (hex) of Port B while a write was requested to the same address on Port A. The write will be successful however the read value on Port B is unknown until the next CLKB cycle.", $time/1000.0, addrb_int); + + end + endtask + + always @(posedge setup_all_b_a) begin + if ((ena_int == 1) && (enb_reg == 1)) begin + case ({wea_int, web_reg}) + 6'b11 : begin data_collision_b_a <= 2'b11; display_all_b_a; end + 6'b01 : begin data_collision_b_a <= 2'b10; display_all_b_a; end + 6'b10 : begin data_collision_b_a <= 2'b01; display_all_b_a; end + endcase + end + setup_all_b_a <= 0; + end + + task display_all_b_a; + begin + address_collision_b_a = 1'b0; + for (ci = 0; ci < 2; ci = ci + 1) begin + if ((mem_addra_int) == (mem_addrb_reg + ci)) begin + address_collision_b_a = 1'b1; + end + end + if (address_collision_b_a == 1'b1) + + if (({wea_int, web_reg}) == 2'b11) + $display("Memory Collision Error on RAMB4_S1_S2:%m at simulation time %.3f ns\nA write was requested to the same address simultaneously at both Port A and Port B of the RAM. The contents written to the RAM at address location %h (hex) of Port A and address location %h (hex) of Port B are unknown.", $time/1000.0, addra_int, addrb_int); + + else if (({wea_int, web_reg}) == 2'b01) + $display("Memory Collision Error on RAMB4_S1_S2:%m at simulation time %.3f ns\nA read was performed on address %h (hex) of Port A while a write was requested to the same address on Port B. The write will be successful however the read value on Port A is unknown until the next CLKA cycle.", $time/1000.0, addra_int); + + else if (({wea_int, web_reg}) == 2'b10) + $display("Memory Collision Error on RAMB4_S1_S2:%m at simulation time %.3f ns\nA read was performed on address %h (hex) of Port B while a write was requested to the same address on Port A. The write will be successful however the read value on Port B is unknown until the next CLKB cycle.", $time/1000.0, addrb_int); + + end + endtask + + always @(posedge setup_zero) begin + if ((ena_int == 1) && (enb_int == 1)) begin + case ({wea_int, web_int}) + 6'b11 : begin data_collision <= 2'b11; display_zero; end + 6'b01 : begin data_collision <= 2'b10; display_zero; end + 6'b10 : begin data_collision <= 2'b01; display_zero; end + endcase + end + setup_zero <= 0; + end + + task display_zero; + begin + address_collision = 1'b0; + for (ci = 0; ci < 2; ci = ci + 1) begin + if ((mem_addra_int) == (mem_addrb_int + ci)) begin + address_collision = 1'b1; + end + end + if (address_collision == 1'b1) + + if (({wea_int, web_int}) == 2'b11) + $display("Memory Collision Error on RAMB4_S1_S2:%m at simulation time %.3f ns\nA write was requested to the same address simultaneously at both Port A and Port B of the RAM. The contents written to the RAM at address location %h (hex) of Port A and address location %h (hex) of Port B are unknown.", $time/1000.0, addra_int, addrb_int); + + else if (({wea_int, web_int}) == 2'b01) + $display("Memory Collision Error on RAMB4_S1_S2:%m at simulation time %.3f ns\nA read was performed on address %h (hex) of Port A while a write was requested to the same address on Port B. The write will be successful however the read value on Port A is unknown until the next CLKA cycle.", $time/1000.0, addra_int); + + else if (({wea_int, web_int}) == 2'b10) + $display("Memory Collision Error on RAMB4_S1_S2:%m at simulation time %.3f ns\nA read was performed on address %h (hex) of Port B while a write was requested to the same address on Port A. The write will be successful however the read value on Port B is unknown until the next CLKB cycle.", $time/1000.0, addrb_int); + + end + endtask + + always @(posedge clka_int) begin + addra_reg <= addra_int; + ena_reg <= ena_int; + rsta_reg <= rsta_int; + wea_reg <= wea_int; + end + + always @(posedge clkb_int) begin + addrb_reg <= addrb_int; + enb_reg <= enb_int; + rstb_reg <= rstb_int; + web_reg <= web_int; + end + + // Data + always @(posedge memory_collision) begin + for (mi = 0; mi < 2; mi = mi + 1) begin + if ((mem_addra_int) == (mem_addrb_int + mi)) begin + for (mj = 0; mj < 1; mj = mj + 1) begin + mem[mem_addrb_int + mi + mj] <= 1'bX; + end + end + end + memory_collision <= 0; + end + + always @(posedge memory_collision_a_b) begin + for (mi = 0; mi < 2; mi = mi + 1) begin + if ((mem_addra_reg) == (mem_addrb_int + mi)) begin + for (mj = 0; mj < 1; mj = mj + 1) begin + mem[mem_addrb_int + mi + mj] <= 1'bX; + end + end + end + memory_collision_a_b <= 0; + end + + always @(posedge memory_collision_b_a) begin + for (mi = 0; mi < 2; mi = mi + 1) begin + if ((mem_addra_int) == (mem_addrb_reg + mi)) begin + for (mj = 0; mj < 1; mj = mj + 1) begin + mem[mem_addrb_reg + mi + mj] <= 1'bX; + end + end + end + memory_collision_b_a <= 0; + end + + always @(posedge data_collision[1]) begin + if (rsta_int == 0) begin + for (ai = 0; ai < 2; ai = ai + 1) begin + if ((mem_addra_int) == (mem_addrb_int + ai)) begin + doa_out <= 1'bX; + end + end + end + data_collision[1] <= 0; + end + + always @(posedge data_collision[0]) begin + if (rstb_int == 0) begin + for (bi = 0; bi < 2; bi = bi + 1) begin + if ((mem_addra_int) == (mem_addrb_int + bi)) begin + for (bj = 0; bj < 1; bj = bj + 1) begin + dob_out[bi + bj] <= 1'bX; + end + end + end + end + data_collision[0] <= 0; + end + + always @(posedge data_collision_a_b[1]) begin + if (rsta_reg == 0) begin + for (ai = 0; ai < 2; ai = ai + 1) begin + if ((mem_addra_reg) == (mem_addrb_int + ai)) begin + doa_out <= 1'bX; + end + end + end + data_collision_a_b[1] <= 0; + end + + always @(posedge data_collision_a_b[0]) begin + if (rstb_int == 0) begin + for (bi = 0; bi < 2; bi = bi + 1) begin + if ((mem_addra_reg) == (mem_addrb_int + bi)) begin + for (bj = 0; bj < 1; bj = bj + 1) begin + dob_out[bi + bj] <= 1'bX; + end + end + end + end + data_collision_a_b[0] <= 0; + end + + always @(posedge data_collision_b_a[1]) begin + if (rsta_int == 0) begin + for (ai = 0; ai < 2; ai = ai + 1) begin + if ((mem_addra_int) == (mem_addrb_reg + ai)) begin + doa_out <= 1'bX; + end + end + end + data_collision_b_a[1] <= 0; + end + + always @(posedge data_collision_b_a[0]) begin + if (rstb_reg == 0) begin + for (bi = 0; bi < 2; bi = bi + 1) begin + if ((mem_addra_int) == (mem_addrb_reg + bi)) begin + for (bj = 0; bj < 1; bj = bj + 1) begin + dob_out[bi + bj] <= 1'bX; + end + end + end + end + data_collision_b_a[0] <= 0; + end + + + always @(posedge clka_int) begin + if (ena_int == 1'b1) begin + if (rsta_int == 1'b1) begin + doa_out <= 1'b0; + end + else if (wea_int == 0) begin + doa_out[0] <= mem[mem_addra_int + 0]; + end + else begin + doa_out <= dia_int; + end + end + end + + always @(posedge clka_int) begin + if (ena_int == 1'b1 && wea_int == 1'b1) begin + mem[mem_addra_int + 0] <= dia_int[0]; + end + end + + always @(posedge clkb_int) begin + if (enb_int == 1'b1) begin + if (rstb_int == 1'b1) begin + dob_out <= 2'b0; + end + else if (web_int == 0) begin + dob_out[0] <= mem[mem_addrb_int + 0]; + dob_out[1] <= mem[mem_addrb_int + 1]; + end + else begin + dob_out <= dib_int; + end + end + end + + always @(posedge clkb_int) begin + if (enb_int == 1'b1 && web_int == 1'b1) begin + mem[mem_addrb_int + 0] <= dib_int[0]; + mem[mem_addrb_int + 1] <= dib_int[1]; + end + end + + specify + (CLKA *> DOA) = (100, 100); + (CLKB *> DOB) = (100, 100); + endspecify + +endmodule + +`else + +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/RAMB4_S1_S2.v,v 1.9 2007/02/22 01:58:06 wloo Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2005 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Timing Simulation Library Component +// / / 16K-Bit Data and 2K-Bit Parity Dual Port Block RAM +// /___/ /\ Filename : RAMB4_S1_S2.v +// \ \ / \ Timestamp : Thu Mar 10 16:44:01 PST 2005 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 03/10/05 - Initialized outputs. +// 02/21/07 - Fixed parameter SIM_COLLISION_CHECK (CR 433281). +// End Revision + +`timescale 1 ps/1 ps + +module RAMB4_S1_S2 (DOA, DOB, ADDRA, ADDRB, CLKA, CLKB, DIA, DIB, ENA, ENB, RSTA, RSTB, WEA, WEB); + + parameter SIM_COLLISION_CHECK = "ALL"; + localparam SETUP_ALL = 100; + + parameter INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + + output [0:0] DOA; + output [1:0] DOB; + + input [11:0] ADDRA; + input [0:0] DIA; + input ENA, CLKA, WEA, RSTA; + input [10:0] ADDRB; + input [1:0] DIB; + input ENB, CLKB, WEB, RSTB; + + reg [0:0] doa_out = 0; + reg [1:0] dob_out = 0; + + reg [1:0] mem [2047:0]; + + reg [8:0] count; + + reg [5:0] mi, ai, bi, bj, ci; + + wire [11:0] addra_int; + reg [11:0] addra_reg; + wire [0:0] dia_int; + wire ena_int, clka_int, wea_int, rsta_int; + reg ena_reg, wea_reg, rsta_reg; + wire [10:0] addrb_int; + reg [10:0] addrb_reg; + wire [1:0] dib_int; + wire enb_int, clkb_int, web_int, rstb_int; + reg display_flag, output_flag; + reg enb_reg, web_reg, rstb_reg; + + time time_clka, time_clkb; + time time_clka_clkb; + time time_clkb_clka; + + reg setup_all_a_b; + reg setup_all_b_a; + reg setup_zero; + reg [1:0] data_collision, data_collision_a_b, data_collision_b_a; + reg memory_collision, memory_collision_a_b, memory_collision_b_a; + reg address_collision, address_collision_a_b, address_collision_b_a; + reg change_clka; + reg change_clkb; + + wire [11:0] mem_addra_int; + wire [11:0] mem_addra_reg; + wire [11:0] mem_addrb_int; + wire [11:0] mem_addrb_reg; + + wire dia_enable = ena_int && wea_int; + wire dib_enable = enb_int && web_int; + + tri0 GSR = glbl.GSR; + wire gsr_int; + + buf b_gsr (gsr_int, GSR); + + buf b_doa [0:0] (DOA, doa_out); + buf b_addra [11:0] (addra_int, ADDRA); + buf b_dia [0:0] (dia_int, DIA); + buf b_ena (ena_int, ENA); + buf b_clka (clka_int, CLKA); + buf b_rsta (rsta_int, RSTA); + buf b_wea (wea_int, WEA); + + buf b_dob [1:0] (DOB, dob_out); + buf b_addrb [10:0] (addrb_int, ADDRB); + buf b_dib [1:0] (dib_int, DIB); + buf b_enb (enb_int, ENB); + buf b_clkb (clkb_int, CLKB); + buf b_rstb (rstb_int, RSTB); + buf b_web (web_int, WEB); + + + always @(gsr_int) + if (gsr_int) begin + assign doa_out = 0; + assign dob_out = 0; + end + else begin + deassign doa_out; + deassign dob_out; + end + + + initial begin + + for (count = 0; count < 128; count = count + 1) begin + mem[count] = INIT_00[(count * 2) +: 2]; + mem[128 * 1 + count] = INIT_01[(count * 2) +: 2]; + mem[128 * 2 + count] = INIT_02[(count * 2) +: 2]; + mem[128 * 3 + count] = INIT_03[(count * 2) +: 2]; + mem[128 * 4 + count] = INIT_04[(count * 2) +: 2]; + mem[128 * 5 + count] = INIT_05[(count * 2) +: 2]; + mem[128 * 6 + count] = INIT_06[(count * 2) +: 2]; + mem[128 * 7 + count] = INIT_07[(count * 2) +: 2]; + mem[128 * 8 + count] = INIT_08[(count * 2) +: 2]; + mem[128 * 9 + count] = INIT_09[(count * 2) +: 2]; + mem[128 * 10 + count] = INIT_0A[(count * 2) +: 2]; + mem[128 * 11 + count] = INIT_0B[(count * 2) +: 2]; + mem[128 * 12 + count] = INIT_0C[(count * 2) +: 2]; + mem[128 * 13 + count] = INIT_0D[(count * 2) +: 2]; + mem[128 * 14 + count] = INIT_0E[(count * 2) +: 2]; + mem[128 * 15 + count] = INIT_0F[(count * 2) +: 2]; + end + + change_clka <= 0; + change_clkb <= 0; + data_collision <= 0; + data_collision_a_b <= 0; + data_collision_b_a <= 0; + memory_collision <= 0; + memory_collision_a_b <= 0; + memory_collision_b_a <= 0; + setup_all_a_b <= 0; + setup_all_b_a <= 0; + setup_zero <= 0; + end + + assign mem_addra_int = addra_int * 1; + assign mem_addra_reg = addra_reg * 1; + assign mem_addrb_int = addrb_int * 2; + assign mem_addrb_reg = addrb_reg * 2; + + + initial begin + + display_flag = 1; + output_flag = 1; + + case (SIM_COLLISION_CHECK) + + "NONE" : begin + output_flag = 0; + display_flag = 0; + end + "WARNING_ONLY" : output_flag = 0; + "GENERATE_X_ONLY" : display_flag = 0; + "ALL" : ; + + default : begin + $display("Attribute Syntax Error : The Attribute SIM_COLLISION_CHECK on RAMB4_S1_S2 instance %m is set to %s. Legal values for this attribute are ALL, NONE, WARNING_ONLY or GENERATE_X_ONLY.", SIM_COLLISION_CHECK); + $finish; + end + + endcase // case(SIM_COLLISION_CHECK) + + end // initial begin + + + always @(posedge clka_int) begin + if ((output_flag || display_flag)) begin + time_clka = $time; + #0 time_clkb_clka = time_clka - time_clkb; + change_clka = ~change_clka; + end + end + + always @(posedge clkb_int) begin + if ((output_flag || display_flag)) begin + time_clkb = $time; + #0 time_clka_clkb = time_clkb - time_clka; + change_clkb = ~change_clkb; + end + end + + always @(change_clkb) begin + if ((0 < time_clka_clkb) && (time_clka_clkb < SETUP_ALL)) + setup_all_a_b = 1; + end + + always @(change_clka) begin + if ((0 < time_clkb_clka) && (time_clkb_clka < SETUP_ALL)) + setup_all_b_a = 1; + end + + always @(change_clkb or change_clka) begin + if ((time_clkb_clka == 0) && (time_clka_clkb == 0)) + setup_zero = 1; + end + + always @(posedge setup_zero) begin + if ((ena_int == 1) && (wea_int == 1) && + (enb_int == 1) && (web_int == 1)) + memory_collision <= 1; + end + + always @(posedge setup_all_a_b) begin + if ((ena_reg == 1) && (enb_int == 1)) begin + case ({wea_reg, web_int}) + 6'b11 : begin data_collision_a_b <= 2'b11; display_all_a_b; end + 6'b01 : begin data_collision_a_b <= 2'b10; display_all_a_b; end + 6'b10 : begin data_collision_a_b <= 2'b01; display_all_a_b; end + endcase + end + setup_all_a_b <= 0; + end + + task display_all_a_b; + begin + address_collision_a_b = 1'b0; + for (ci = 0; ci < 2; ci = ci + 1) begin + if ((mem_addra_reg) == (mem_addrb_int + ci)) begin + address_collision_a_b = 1'b1; + end + end + if (address_collision_a_b == 1'b1 && display_flag) + + if (({wea_reg, web_int}) == 2'b11) + $display("Memory Collision Error on RAMB4_S1_S2:%m at simulation time %.3f ns\nA write was requested to the same address simultaneously at both Port A and Port B of the RAM. The contents written to the RAM at address location %h (hex) of Port A and address location %h (hex) of Port B are unknown.", $time/1000.0, addra_int, addrb_int); + + else if (({wea_reg, web_int}) == 2'b01) + $display("Memory Collision Error on RAMB4_S1_S2:%m at simulation time %.3f ns\nA read was performed on address %h (hex) of Port A while a write was requested to the same address on Port B. The write will be successful however the read value on Port A is unknown until the next CLKA cycle.", $time/1000.0, addra_int); + + else if (({wea_reg, web_int}) == 2'b10) + $display("Memory Collision Error on RAMB4_S1_S2:%m at simulation time %.3f ns\nA read was performed on address %h (hex) of Port B while a write was requested to the same address on Port A. The write will be successful however the read value on Port B is unknown until the next CLKB cycle.", $time/1000.0, addrb_int); + + end + endtask + + always @(posedge setup_all_b_a) begin + if ((ena_int == 1) && (enb_reg == 1)) begin + case ({wea_int, web_reg}) + 6'b11 : begin data_collision_b_a <= 2'b11; display_all_b_a; end + 6'b01 : begin data_collision_b_a <= 2'b10; display_all_b_a; end + 6'b10 : begin data_collision_b_a <= 2'b01; display_all_b_a; end + endcase + end + setup_all_b_a <= 0; + end + + task display_all_b_a; + begin + address_collision_b_a = 1'b0; + for (ci = 0; ci < 2; ci = ci + 1) begin + if ((mem_addra_int) == (mem_addrb_reg + ci)) begin + address_collision_b_a = 1'b1; + end + end + if (address_collision_b_a == 1'b1 && display_flag) + + if (({wea_int, web_reg}) == 2'b11) + $display("Memory Collision Error on RAMB4_S1_S2:%m at simulation time %.3f ns\nA write was requested to the same address simultaneously at both Port A and Port B of the RAM. The contents written to the RAM at address location %h (hex) of Port A and address location %h (hex) of Port B are unknown.", $time/1000.0, addra_int, addrb_int); + + else if (({wea_int, web_reg}) == 2'b01) + $display("Memory Collision Error on RAMB4_S1_S2:%m at simulation time %.3f ns\nA read was performed on address %h (hex) of Port A while a write was requested to the same address on Port B. The write will be successful however the read value on Port A is unknown until the next CLKA cycle.", $time/1000.0, addra_int); + + else if (({wea_int, web_reg}) == 2'b10) + $display("Memory Collision Error on RAMB4_S1_S2:%m at simulation time %.3f ns\nA read was performed on address %h (hex) of Port B while a write was requested to the same address on Port A. The write will be successful however the read value on Port B is unknown until the next CLKB cycle.", $time/1000.0, addrb_int); + + end + endtask + + always @(posedge setup_zero) begin + if ((ena_int == 1) && (enb_int == 1)) begin + case ({wea_int, web_int}) + 6'b11 : begin data_collision <= 2'b11; display_zero; end + 6'b01 : begin data_collision <= 2'b10; display_zero; end + 6'b10 : begin data_collision <= 2'b01; display_zero; end + endcase + end + setup_zero <= 0; + end + + task display_zero; + begin + address_collision = 1'b0; + for (ci = 0; ci < 2; ci = ci + 1) begin + if ((mem_addra_int) == (mem_addrb_int + ci)) begin + address_collision = 1'b1; + end + end + if (address_collision == 1'b1 && display_flag) + + if (({wea_int, web_int}) == 2'b11) + $display("Memory Collision Error on RAMB4_S1_S2:%m at simulation time %.3f ns\nA write was requested to the same address simultaneously at both Port A and Port B of the RAM. The contents written to the RAM at address location %h (hex) of Port A and address location %h (hex) of Port B are unknown.", $time/1000.0, addra_int, addrb_int); + + else if (({wea_int, web_int}) == 2'b01) + $display("Memory Collision Error on RAMB4_S1_S2:%m at simulation time %.3f ns\nA read was performed on address %h (hex) of Port A while a write was requested to the same address on Port B. The write will be successful however the read value on Port A is unknown until the next CLKA cycle.", $time/1000.0, addra_int); + + else if (({wea_int, web_int}) == 2'b10) + $display("Memory Collision Error on RAMB4_S1_S2:%m at simulation time %.3f ns\nA read was performed on address %h (hex) of Port B while a write was requested to the same address on Port A. The write will be successful however the read value on Port B is unknown until the next CLKB cycle.", $time/1000.0, addrb_int); + + end + endtask + + always @(posedge clka_int) begin + if ((output_flag || display_flag)) begin + addra_reg <= addra_int; + ena_reg <= ena_int; + rsta_reg <= rsta_int; + wea_reg <= wea_int; + end + end + + always @(posedge clkb_int) begin + if ((output_flag || display_flag)) begin + addrb_reg <= addrb_int; + enb_reg <= enb_int; + rstb_reg <= rstb_int; + web_reg <= web_int; + end + end + + + // Data + always @(posedge memory_collision) begin + if ((output_flag || display_flag)) begin + for (mi = 0; mi < 2; mi = mi + 1) begin + if ((mem_addra_int) == (mem_addrb_int + mi)) begin + mem[addra_int[11:1]][addra_int[0:0] * 1 +: 1] <= 1'bx; + end + end + memory_collision <= 0; + end + end + + always @(posedge memory_collision_a_b) begin + if ((output_flag || display_flag)) begin + for (mi = 0; mi < 2; mi = mi + 1) begin + if ((mem_addra_reg) == (mem_addrb_int + mi)) begin + mem[addra_reg[11:1]][addra_reg[0:0] * 1 +: 1] <= 1'bx; + end + end + memory_collision_a_b <= 0; + end + end + + always @(posedge memory_collision_b_a) begin + if ((output_flag || display_flag)) begin + for (mi = 0; mi < 2; mi = mi + 1) begin + if ((mem_addra_int) == (mem_addrb_reg + mi)) begin + mem[addra_int[11:1]][addra_int[0:0] * 1 +: 1] <= 1'bx; + end + end + memory_collision_b_a <= 0; + end + end + + always @(posedge data_collision[1]) begin + if (rsta_int == 0 && output_flag) begin + for (ai = 0; ai < 2; ai = ai + 1) begin + if ((mem_addra_int) == (mem_addrb_int + ai)) begin + doa_out <= #100 1'bX; + end + end + end + data_collision[1] <= 0; + end + + always @(posedge data_collision[0]) begin + if (rstb_int == 0 && output_flag) begin + for (bi = 0; bi < 2; bi = bi + 1) begin + if ((mem_addra_int) == (mem_addrb_int + bi)) begin + for (bj = 0; bj < 1; bj = bj + 1) begin + dob_out[bi + bj] <= #100 1'bX; + end + end + end + end + data_collision[0] <= 0; + end + + always @(posedge data_collision_a_b[1]) begin + if (rsta_reg == 0 && output_flag) begin + for (ai = 0; ai < 2; ai = ai + 1) begin + if ((mem_addra_reg) == (mem_addrb_int + ai)) begin + doa_out <= #100 1'bX; + end + end + end + data_collision_a_b[1] <= 0; + end + + always @(posedge data_collision_a_b[0]) begin + if (rstb_int == 0 && output_flag) begin + for (bi = 0; bi < 2; bi = bi + 1) begin + if ((mem_addra_reg) == (mem_addrb_int + bi)) begin + for (bj = 0; bj < 1; bj = bj + 1) begin + dob_out[bi + bj] <= #100 1'bX; + end + end + end + end + data_collision_a_b[0] <= 0; + end + + always @(posedge data_collision_b_a[1]) begin + if (rsta_int == 0 && output_flag) begin + for (ai = 0; ai < 2; ai = ai + 1) begin + if ((mem_addra_int) == (mem_addrb_reg + ai)) begin + doa_out <= #100 1'bX; + end + end + end + data_collision_b_a[1] <= 0; + end + + always @(posedge data_collision_b_a[0]) begin + if (rstb_reg == 0 && output_flag) begin + for (bi = 0; bi < 2; bi = bi + 1) begin + if ((mem_addra_int) == (mem_addrb_reg + bi)) begin + for (bj = 0; bj < 1; bj = bj + 1) begin + dob_out[bi + bj] <= #100 1'bX; + end + end + end + end + data_collision_b_a[0] <= 0; + end + + + // Port A + always @(posedge clka_int) begin + + if (ena_int == 1'b1) begin + + if (rsta_int == 1'b1) begin + doa_out <= #100 0; + end + else begin + if (wea_int == 1'b1) + doa_out <= #100 dia_int; + else + doa_out <= #100 mem[addra_int[11:1]][addra_int[0:0] * 1 +: 1]; + end + + // memory + if (wea_int == 1'b1) begin + mem[addra_int[11:1]][addra_int[0:0] * 1 +: 1] <= dia_int; + end + + end + end + + + // Port B + always @(posedge clkb_int) begin + + if (enb_int == 1'b1) begin + + if (rstb_int == 1'b1) begin + dob_out <= #100 0; + end + else begin + if (web_int == 1'b1) + dob_out <= #100 dib_int; + else + dob_out <= #100 mem[addrb_int]; + end + + // memory + if (web_int == 1'b1) begin + mem[addrb_int] <= dib_int; + end + + end + end + + +endmodule + +`endif diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/RAMB4_S1_S4.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/RAMB4_S1_S4.v new file mode 100644 index 0000000..a43ce1d --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/RAMB4_S1_S4.v @@ -0,0 +1,1052 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/RAMB4_S1_S4.v,v 1.9 2007/02/22 01:58:06 wloo Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2005 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / 4K-Bit Data Dual Port Block RAM +// /___/ /\ Filename : RAMB4_S1_S4.v +// \ \ / \ Timestamp : Thu Mar 10 16:43:38 PST 2005 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// End Revision + +`ifdef legacy_model + +`timescale 1 ps / 1 ps + +module RAMB4_S1_S4 (DOA, DOB, ADDRA, ADDRB, CLKA, CLKB, DIA, DIB, ENA, ENB, RSTA, RSTB, WEA, WEB); + + parameter SIM_COLLISION_CHECK = "ALL"; + localparam SETUP_ALL = 100; + + parameter INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + + output [0:0] DOA; + reg [0:0] doa_out; + wire doa_out0; + + input [11:0] ADDRA; + input [0:0] DIA; + input ENA, CLKA, WEA, RSTA; + + output [3:0] DOB; + reg [3:0] dob_out; + wire dob_out0, dob_out1, dob_out2, dob_out3; + + input [9:0] ADDRB; + input [3:0] DIB; + input ENB, CLKB, WEB, RSTB; + + reg [4095:0] mem; + reg [8:0] count; + + reg [5:0] mi, mj, ai, aj, bi, bj, ci, cj, di, dj, ei, ej, fi, fj; + + wire [11:0] addra_int; + reg [11:0] addra_reg; + wire [0:0] dia_int; + wire ena_int, clka_int, wea_int, rsta_int; + reg ena_reg, wea_reg, rsta_reg; + wire [9:0] addrb_int; + reg [9:0] addrb_reg; + wire [3:0] dib_int; + wire enb_int, clkb_int, web_int, rstb_int; + reg enb_reg, web_reg, rstb_reg; + + time time_clka, time_clkb; + time time_clka_clkb; + time time_clkb_clka; + + reg setup_all_a_b; + reg setup_all_b_a; + reg setup_zero; + reg [1:0] data_collision, data_collision_a_b, data_collision_b_a; + reg memory_collision, memory_collision_a_b, memory_collision_b_a; + reg address_collision, address_collision_a_b, address_collision_b_a; + reg change_clka; + reg change_clkb; + + wire [11:0] mem_addra_int; + wire [11:0] mem_addra_reg; + wire [11:0] mem_addrb_int; + wire [11:0] mem_addrb_reg; + + tri0 GSR = glbl.GSR; + + always @(GSR) + if (GSR) begin + assign doa_out = 0; + end + else begin + deassign doa_out; + end + + always @(GSR) + if (GSR) begin + assign dob_out = 0; + end + else begin + deassign dob_out; + end + + buf b_doa_out0 (doa_out0, doa_out[0]); + buf b_dob_out0 (dob_out0, dob_out[0]); + buf b_dob_out1 (dob_out1, dob_out[1]); + buf b_dob_out2 (dob_out2, dob_out[2]); + buf b_dob_out3 (dob_out3, dob_out[3]); + buf b_doa0 (DOA[0], doa_out0); + buf b_dob0 (DOB[0], dob_out0); + buf b_dob1 (DOB[1], dob_out1); + buf b_dob2 (DOB[2], dob_out2); + buf b_dob3 (DOB[3], dob_out3); + buf b_addra_0 (addra_int[0], ADDRA[0]); + buf b_addra_1 (addra_int[1], ADDRA[1]); + buf b_addra_2 (addra_int[2], ADDRA[2]); + buf b_addra_3 (addra_int[3], ADDRA[3]); + buf b_addra_4 (addra_int[4], ADDRA[4]); + buf b_addra_5 (addra_int[5], ADDRA[5]); + buf b_addra_6 (addra_int[6], ADDRA[6]); + buf b_addra_7 (addra_int[7], ADDRA[7]); + buf b_addra_8 (addra_int[8], ADDRA[8]); + buf b_addra_9 (addra_int[9], ADDRA[9]); + buf b_addra_10 (addra_int[10], ADDRA[10]); + buf b_addra_11 (addra_int[11], ADDRA[11]); + buf b_dia_0 (dia_int[0], DIA[0]); + buf b_clka (clka_int, CLKA); + buf b_ena (ena_int, ENA); + buf b_rsta (rsta_int, RSTA); + buf b_wea (wea_int, WEA); + buf b_addrb_0 (addrb_int[0], ADDRB[0]); + buf b_addrb_1 (addrb_int[1], ADDRB[1]); + buf b_addrb_2 (addrb_int[2], ADDRB[2]); + buf b_addrb_3 (addrb_int[3], ADDRB[3]); + buf b_addrb_4 (addrb_int[4], ADDRB[4]); + buf b_addrb_5 (addrb_int[5], ADDRB[5]); + buf b_addrb_6 (addrb_int[6], ADDRB[6]); + buf b_addrb_7 (addrb_int[7], ADDRB[7]); + buf b_addrb_8 (addrb_int[8], ADDRB[8]); + buf b_addrb_9 (addrb_int[9], ADDRB[9]); + buf b_dib_0 (dib_int[0], DIB[0]); + buf b_dib_1 (dib_int[1], DIB[1]); + buf b_dib_2 (dib_int[2], DIB[2]); + buf b_dib_3 (dib_int[3], DIB[3]); + buf b_clkb (clkb_int, CLKB); + buf b_enb (enb_int, ENB); + buf b_rstb (rstb_int, RSTB); + buf b_web (web_int, WEB); + + initial begin + for (count = 0; count < 256; count = count + 1) begin + mem[count] <= INIT_00[count]; + mem[256 * 1 + count] <= INIT_01[count]; + mem[256 * 2 + count] <= INIT_02[count]; + mem[256 * 3 + count] <= INIT_03[count]; + mem[256 * 4 + count] <= INIT_04[count]; + mem[256 * 5 + count] <= INIT_05[count]; + mem[256 * 6 + count] <= INIT_06[count]; + mem[256 * 7 + count] <= INIT_07[count]; + mem[256 * 8 + count] <= INIT_08[count]; + mem[256 * 9 + count] <= INIT_09[count]; + mem[256 * 10 + count] <= INIT_0A[count]; + mem[256 * 11 + count] <= INIT_0B[count]; + mem[256 * 12 + count] <= INIT_0C[count]; + mem[256 * 13 + count] <= INIT_0D[count]; + mem[256 * 14 + count] <= INIT_0E[count]; + mem[256 * 15 + count] <= INIT_0F[count]; + end + address_collision <= 0; + address_collision_a_b <= 0; + address_collision_b_a <= 0; + change_clka <= 0; + change_clkb <= 0; + data_collision <= 0; + data_collision_a_b <= 0; + data_collision_b_a <= 0; + memory_collision <= 0; + memory_collision_a_b <= 0; + memory_collision_b_a <= 0; + setup_all_a_b <= 0; + setup_all_b_a <= 0; + setup_zero <= 0; + end + + assign mem_addra_int = addra_int * 1; + assign mem_addra_reg = addra_reg * 1; + assign mem_addrb_int = addrb_int * 4; + assign mem_addrb_reg = addrb_reg * 4; + + + initial begin + + case (SIM_COLLISION_CHECK) + + "NONE" : begin + assign setup_all_a_b = 1'b0; + assign setup_all_b_a = 1'b0; + assign setup_zero = 1'b0; + assign address_collision = 1'b0; + assign address_collision_a_b = 1'b0; + assign address_collision_b_a = 1'b0; + end + "WARNING_ONLY" : begin + assign data_collision = 2'b00; + assign data_collision_a_b = 2'b00; + assign data_collision_b_a = 2'b00; + assign memory_collision = 1'b0; + assign memory_collision_a_b = 1'b0; + assign memory_collision_b_a = 1'b0; + end + "GENERATE_X_ONLY" : begin + assign address_collision = 1'b0; + assign address_collision_a_b = 1'b0; + assign address_collision_b_a = 1'b0; + end + "ALL" : ; + default : begin + $display("Attribute Syntax Error : The Attribute SIM_COLLISION_CHECK on RAMB4_S1_S4 instance %m is set to %s. Legal values for this attribute are ALL, NONE, WARNING_ONLY or GENERATE_X_ONLY.", SIM_COLLISION_CHECK); + $finish; + end + + endcase // case(SIM_COLLISION_CHECK) + + end // initial begin + + + always @(posedge clka_int) begin + time_clka = $time; + #0 time_clkb_clka = time_clka - time_clkb; + change_clka = ~change_clka; + end + + always @(posedge clkb_int) begin + time_clkb = $time; + #0 time_clka_clkb = time_clkb - time_clka; + change_clkb = ~change_clkb; + end + + always @(change_clkb) begin + if ((0 < time_clka_clkb) && (time_clka_clkb < SETUP_ALL)) + setup_all_a_b = 1; + end + + always @(change_clka) begin + if ((0 < time_clkb_clka) && (time_clkb_clka < SETUP_ALL)) + setup_all_b_a = 1; + end + + always @(change_clkb or change_clka) begin + if ((time_clkb_clka == 0) && (time_clka_clkb == 0)) + setup_zero = 1; + end + + always @(posedge setup_zero) begin + if ((ena_int == 1) && (wea_int == 1) && + (enb_int == 1) && (web_int == 1)) + memory_collision <= 1; + end + + always @(posedge setup_all_a_b) begin + if ((ena_reg == 1) && (enb_int == 1)) begin + case ({wea_reg, web_int}) + 6'b11 : begin data_collision_a_b <= 2'b11; display_all_a_b; end + 6'b01 : begin data_collision_a_b <= 2'b10; display_all_a_b; end + 6'b10 : begin data_collision_a_b <= 2'b01; display_all_a_b; end + endcase + end + setup_all_a_b <= 0; + end + + task display_all_a_b; + begin + address_collision_a_b = 1'b0; + for (ci = 0; ci < 4; ci = ci + 1) begin + if ((mem_addra_reg) == (mem_addrb_int + ci)) begin + address_collision_a_b = 1'b1; + end + end + if (address_collision_a_b == 1'b1) + + if (({wea_reg, web_int}) == 2'b11) + $display("Memory Collision Error on RAMB4_S1_S4:%m at simulation time %.3f ns\nA write was requested to the same address simultaneously at both Port A and Port B of the RAM. The contents written to the RAM at address location %h (hex) of Port A and address location %h (hex) of Port B are unknown.", $time/1000.0, addra_int, addrb_int); + + else if (({wea_reg, web_int}) == 2'b01) + $display("Memory Collision Error on RAMB4_S1_S4:%m at simulation time %.3f ns\nA read was performed on address %h (hex) of Port A while a write was requested to the same address on Port B. The write will be successful however the read value on Port A is unknown until the next CLKA cycle.", $time/1000.0, addra_int); + + else if (({wea_reg, web_int}) == 2'b10) + $display("Memory Collision Error on RAMB4_S1_S4:%m at simulation time %.3f ns\nA read was performed on address %h (hex) of Port B while a write was requested to the same address on Port A. The write will be successful however the read value on Port B is unknown until the next CLKB cycle.", $time/1000.0, addrb_int); + + end + endtask + + always @(posedge setup_all_b_a) begin + if ((ena_int == 1) && (enb_reg == 1)) begin + case ({wea_int, web_reg}) + 6'b11 : begin data_collision_b_a <= 2'b11; display_all_b_a; end + 6'b01 : begin data_collision_b_a <= 2'b10; display_all_b_a; end + 6'b10 : begin data_collision_b_a <= 2'b01; display_all_b_a; end + endcase + end + setup_all_b_a <= 0; + end + + task display_all_b_a; + begin + address_collision_b_a = 1'b0; + for (ci = 0; ci < 4; ci = ci + 1) begin + if ((mem_addra_int) == (mem_addrb_reg + ci)) begin + address_collision_b_a = 1'b1; + end + end + if (address_collision_b_a == 1'b1) + + if (({wea_int, web_reg}) == 2'b11) + $display("Memory Collision Error on RAMB4_S1_S4:%m at simulation time %.3f ns\nA write was requested to the same address simultaneously at both Port A and Port B of the RAM. The contents written to the RAM at address location %h (hex) of Port A and address location %h (hex) of Port B are unknown.", $time/1000.0, addra_int, addrb_int); + + else if (({wea_int, web_reg}) == 2'b01) + $display("Memory Collision Error on RAMB4_S1_S4:%m at simulation time %.3f ns\nA read was performed on address %h (hex) of Port A while a write was requested to the same address on Port B. The write will be successful however the read value on Port A is unknown until the next CLKA cycle.", $time/1000.0, addra_int); + + else if (({wea_int, web_reg}) == 2'b10) + $display("Memory Collision Error on RAMB4_S1_S4:%m at simulation time %.3f ns\nA read was performed on address %h (hex) of Port B while a write was requested to the same address on Port A. The write will be successful however the read value on Port B is unknown until the next CLKB cycle.", $time/1000.0, addrb_int); + + end + endtask + + always @(posedge setup_zero) begin + if ((ena_int == 1) && (enb_int == 1)) begin + case ({wea_int, web_int}) + 6'b11 : begin data_collision <= 2'b11; display_zero; end + 6'b01 : begin data_collision <= 2'b10; display_zero; end + 6'b10 : begin data_collision <= 2'b01; display_zero; end + endcase + end + setup_zero <= 0; + end + + task display_zero; + begin + address_collision = 1'b0; + for (ci = 0; ci < 4; ci = ci + 1) begin + if ((mem_addra_int) == (mem_addrb_int + ci)) begin + address_collision = 1'b1; + end + end + if (address_collision == 1'b1) + + if (({wea_int, web_int}) == 2'b11) + $display("Memory Collision Error on RAMB4_S1_S4:%m at simulation time %.3f ns\nA write was requested to the same address simultaneously at both Port A and Port B of the RAM. The contents written to the RAM at address location %h (hex) of Port A and address location %h (hex) of Port B are unknown.", $time/1000.0, addra_int, addrb_int); + + else if (({wea_int, web_int}) == 2'b01) + $display("Memory Collision Error on RAMB4_S1_S4:%m at simulation time %.3f ns\nA read was performed on address %h (hex) of Port A while a write was requested to the same address on Port B. The write will be successful however the read value on Port A is unknown until the next CLKA cycle.", $time/1000.0, addra_int); + + else if (({wea_int, web_int}) == 2'b10) + $display("Memory Collision Error on RAMB4_S1_S4:%m at simulation time %.3f ns\nA read was performed on address %h (hex) of Port B while a write was requested to the same address on Port A. The write will be successful however the read value on Port B is unknown until the next CLKB cycle.", $time/1000.0, addrb_int); + + end + endtask + + always @(posedge clka_int) begin + addra_reg <= addra_int; + ena_reg <= ena_int; + rsta_reg <= rsta_int; + wea_reg <= wea_int; + end + + always @(posedge clkb_int) begin + addrb_reg <= addrb_int; + enb_reg <= enb_int; + rstb_reg <= rstb_int; + web_reg <= web_int; + end + + // Data + always @(posedge memory_collision) begin + for (mi = 0; mi < 4; mi = mi + 1) begin + if ((mem_addra_int) == (mem_addrb_int + mi)) begin + for (mj = 0; mj < 1; mj = mj + 1) begin + mem[mem_addrb_int + mi + mj] <= 1'bX; + end + end + end + memory_collision <= 0; + end + + always @(posedge memory_collision_a_b) begin + for (mi = 0; mi < 4; mi = mi + 1) begin + if ((mem_addra_reg) == (mem_addrb_int + mi)) begin + for (mj = 0; mj < 1; mj = mj + 1) begin + mem[mem_addrb_int + mi + mj] <= 1'bX; + end + end + end + memory_collision_a_b <= 0; + end + + always @(posedge memory_collision_b_a) begin + for (mi = 0; mi < 4; mi = mi + 1) begin + if ((mem_addra_int) == (mem_addrb_reg + mi)) begin + for (mj = 0; mj < 1; mj = mj + 1) begin + mem[mem_addrb_reg + mi + mj] <= 1'bX; + end + end + end + memory_collision_b_a <= 0; + end + + always @(posedge data_collision[1]) begin + if (rsta_int == 0) begin + for (ai = 0; ai < 4; ai = ai + 1) begin + if ((mem_addra_int) == (mem_addrb_int + ai)) begin + doa_out <= 1'bX; + end + end + end + data_collision[1] <= 0; + end + + always @(posedge data_collision[0]) begin + if (rstb_int == 0) begin + for (bi = 0; bi < 4; bi = bi + 1) begin + if ((mem_addra_int) == (mem_addrb_int + bi)) begin + for (bj = 0; bj < 1; bj = bj + 1) begin + dob_out[bi + bj] <= 1'bX; + end + end + end + end + data_collision[0] <= 0; + end + + always @(posedge data_collision_a_b[1]) begin + if (rsta_reg == 0) begin + for (ai = 0; ai < 4; ai = ai + 1) begin + if ((mem_addra_reg) == (mem_addrb_int + ai)) begin + doa_out <= 1'bX; + end + end + end + data_collision_a_b[1] <= 0; + end + + always @(posedge data_collision_a_b[0]) begin + if (rstb_int == 0) begin + for (bi = 0; bi < 4; bi = bi + 1) begin + if ((mem_addra_reg) == (mem_addrb_int + bi)) begin + for (bj = 0; bj < 1; bj = bj + 1) begin + dob_out[bi + bj] <= 1'bX; + end + end + end + end + data_collision_a_b[0] <= 0; + end + + always @(posedge data_collision_b_a[1]) begin + if (rsta_int == 0) begin + for (ai = 0; ai < 4; ai = ai + 1) begin + if ((mem_addra_int) == (mem_addrb_reg + ai)) begin + doa_out <= 1'bX; + end + end + end + data_collision_b_a[1] <= 0; + end + + always @(posedge data_collision_b_a[0]) begin + if (rstb_reg == 0) begin + for (bi = 0; bi < 4; bi = bi + 1) begin + if ((mem_addra_int) == (mem_addrb_reg + bi)) begin + for (bj = 0; bj < 1; bj = bj + 1) begin + dob_out[bi + bj] <= 1'bX; + end + end + end + end + data_collision_b_a[0] <= 0; + end + + + always @(posedge clka_int) begin + if (ena_int == 1'b1) begin + if (rsta_int == 1'b1) begin + doa_out <= 1'b0; + end + else if (wea_int == 0) begin + doa_out[0] <= mem[mem_addra_int + 0]; + end + else begin + doa_out <= dia_int; + end + end + end + + always @(posedge clka_int) begin + if (ena_int == 1'b1 && wea_int == 1'b1) begin + mem[mem_addra_int + 0] <= dia_int[0]; + end + end + + always @(posedge clkb_int) begin + if (enb_int == 1'b1) begin + if (rstb_int == 1'b1) begin + dob_out <= 4'b0; + end + else if (web_int == 0) begin + dob_out[0] <= mem[mem_addrb_int + 0]; + dob_out[1] <= mem[mem_addrb_int + 1]; + dob_out[2] <= mem[mem_addrb_int + 2]; + dob_out[3] <= mem[mem_addrb_int + 3]; + end + else begin + dob_out <= dib_int; + end + end + end + + always @(posedge clkb_int) begin + if (enb_int == 1'b1 && web_int == 1'b1) begin + mem[mem_addrb_int + 0] <= dib_int[0]; + mem[mem_addrb_int + 1] <= dib_int[1]; + mem[mem_addrb_int + 2] <= dib_int[2]; + mem[mem_addrb_int + 3] <= dib_int[3]; + end + end + + specify + (CLKA *> DOA) = (100, 100); + (CLKB *> DOB) = (100, 100); + endspecify + +endmodule + +`else + +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/RAMB4_S1_S4.v,v 1.9 2007/02/22 01:58:06 wloo Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2005 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Timing Simulation Library Component +// / / 16K-Bit Data and 2K-Bit Parity Dual Port Block RAM +// /___/ /\ Filename : RAMB4_S1_S4.v +// \ \ / \ Timestamp : Thu Mar 10 16:44:01 PST 2005 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 03/10/05 - Initialized outputs. +// 02/21/07 - Fixed parameter SIM_COLLISION_CHECK (CR 433281). +// End Revision + +`timescale 1 ps/1 ps + +module RAMB4_S1_S4 (DOA, DOB, ADDRA, ADDRB, CLKA, CLKB, DIA, DIB, ENA, ENB, RSTA, RSTB, WEA, WEB); + + parameter SIM_COLLISION_CHECK = "ALL"; + localparam SETUP_ALL = 100; + + parameter INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + + output [0:0] DOA; + output [3:0] DOB; + + input [11:0] ADDRA; + input [0:0] DIA; + input ENA, CLKA, WEA, RSTA; + input [9:0] ADDRB; + input [3:0] DIB; + input ENB, CLKB, WEB, RSTB; + + reg [0:0] doa_out = 0; + reg [3:0] dob_out = 0; + + reg [3:0] mem [1023:0]; + + reg [8:0] count; + + reg [5:0] mi, ai, bi, bj, ci; + + wire [11:0] addra_int; + reg [11:0] addra_reg; + wire [0:0] dia_int; + wire ena_int, clka_int, wea_int, rsta_int; + reg ena_reg, wea_reg, rsta_reg; + wire [9:0] addrb_int; + reg [9:0] addrb_reg; + wire [3:0] dib_int; + wire enb_int, clkb_int, web_int, rstb_int; + reg display_flag, output_flag; + reg enb_reg, web_reg, rstb_reg; + + time time_clka, time_clkb; + time time_clka_clkb; + time time_clkb_clka; + + reg setup_all_a_b; + reg setup_all_b_a; + reg setup_zero; + reg [1:0] data_collision, data_collision_a_b, data_collision_b_a; + reg memory_collision, memory_collision_a_b, memory_collision_b_a; + reg address_collision, address_collision_a_b, address_collision_b_a; + reg change_clka; + reg change_clkb; + + wire [11:0] mem_addra_int; + wire [11:0] mem_addra_reg; + wire [11:0] mem_addrb_int; + wire [11:0] mem_addrb_reg; + + wire dia_enable = ena_int && wea_int; + wire dib_enable = enb_int && web_int; + + tri0 GSR = glbl.GSR; + wire gsr_int; + + buf b_gsr (gsr_int, GSR); + + buf b_doa [0:0] (DOA, doa_out); + buf b_addra [11:0] (addra_int, ADDRA); + buf b_dia [0:0] (dia_int, DIA); + buf b_ena (ena_int, ENA); + buf b_clka (clka_int, CLKA); + buf b_rsta (rsta_int, RSTA); + buf b_wea (wea_int, WEA); + + buf b_dob [3:0] (DOB, dob_out); + buf b_addrb [9:0] (addrb_int, ADDRB); + buf b_dib [3:0] (dib_int, DIB); + buf b_enb (enb_int, ENB); + buf b_clkb (clkb_int, CLKB); + buf b_rstb (rstb_int, RSTB); + buf b_web (web_int, WEB); + + + always @(gsr_int) + if (gsr_int) begin + assign doa_out = 0; + assign dob_out = 0; + end + else begin + deassign doa_out; + deassign dob_out; + end + + + initial begin + + for (count = 0; count < 64; count = count + 1) begin + mem[count] = INIT_00[(count * 4) +: 4]; + mem[64 * 1 + count] = INIT_01[(count * 4) +: 4]; + mem[64 * 2 + count] = INIT_02[(count * 4) +: 4]; + mem[64 * 3 + count] = INIT_03[(count * 4) +: 4]; + mem[64 * 4 + count] = INIT_04[(count * 4) +: 4]; + mem[64 * 5 + count] = INIT_05[(count * 4) +: 4]; + mem[64 * 6 + count] = INIT_06[(count * 4) +: 4]; + mem[64 * 7 + count] = INIT_07[(count * 4) +: 4]; + mem[64 * 8 + count] = INIT_08[(count * 4) +: 4]; + mem[64 * 9 + count] = INIT_09[(count * 4) +: 4]; + mem[64 * 10 + count] = INIT_0A[(count * 4) +: 4]; + mem[64 * 11 + count] = INIT_0B[(count * 4) +: 4]; + mem[64 * 12 + count] = INIT_0C[(count * 4) +: 4]; + mem[64 * 13 + count] = INIT_0D[(count * 4) +: 4]; + mem[64 * 14 + count] = INIT_0E[(count * 4) +: 4]; + mem[64 * 15 + count] = INIT_0F[(count * 4) +: 4]; + end + + change_clka <= 0; + change_clkb <= 0; + data_collision <= 0; + data_collision_a_b <= 0; + data_collision_b_a <= 0; + memory_collision <= 0; + memory_collision_a_b <= 0; + memory_collision_b_a <= 0; + setup_all_a_b <= 0; + setup_all_b_a <= 0; + setup_zero <= 0; + end + + assign mem_addra_int = addra_int * 1; + assign mem_addra_reg = addra_reg * 1; + assign mem_addrb_int = addrb_int * 4; + assign mem_addrb_reg = addrb_reg * 4; + + + initial begin + + display_flag = 1; + output_flag = 1; + + case (SIM_COLLISION_CHECK) + + "NONE" : begin + output_flag = 0; + display_flag = 0; + end + "WARNING_ONLY" : output_flag = 0; + "GENERATE_X_ONLY" : display_flag = 0; + "ALL" : ; + + default : begin + $display("Attribute Syntax Error : The Attribute SIM_COLLISION_CHECK on RAMB4_S1_S4 instance %m is set to %s. Legal values for this attribute are ALL, NONE, WARNING_ONLY or GENERATE_X_ONLY.", SIM_COLLISION_CHECK); + $finish; + end + + endcase // case(SIM_COLLISION_CHECK) + + end // initial begin + + + always @(posedge clka_int) begin + if ((output_flag || display_flag)) begin + time_clka = $time; + #0 time_clkb_clka = time_clka - time_clkb; + change_clka = ~change_clka; + end + end + + always @(posedge clkb_int) begin + if ((output_flag || display_flag)) begin + time_clkb = $time; + #0 time_clka_clkb = time_clkb - time_clka; + change_clkb = ~change_clkb; + end + end + + always @(change_clkb) begin + if ((0 < time_clka_clkb) && (time_clka_clkb < SETUP_ALL)) + setup_all_a_b = 1; + end + + always @(change_clka) begin + if ((0 < time_clkb_clka) && (time_clkb_clka < SETUP_ALL)) + setup_all_b_a = 1; + end + + always @(change_clkb or change_clka) begin + if ((time_clkb_clka == 0) && (time_clka_clkb == 0)) + setup_zero = 1; + end + + always @(posedge setup_zero) begin + if ((ena_int == 1) && (wea_int == 1) && + (enb_int == 1) && (web_int == 1)) + memory_collision <= 1; + end + + always @(posedge setup_all_a_b) begin + if ((ena_reg == 1) && (enb_int == 1)) begin + case ({wea_reg, web_int}) + 6'b11 : begin data_collision_a_b <= 2'b11; display_all_a_b; end + 6'b01 : begin data_collision_a_b <= 2'b10; display_all_a_b; end + 6'b10 : begin data_collision_a_b <= 2'b01; display_all_a_b; end + endcase + end + setup_all_a_b <= 0; + end + + task display_all_a_b; + begin + address_collision_a_b = 1'b0; + for (ci = 0; ci < 4; ci = ci + 1) begin + if ((mem_addra_reg) == (mem_addrb_int + ci)) begin + address_collision_a_b = 1'b1; + end + end + if (address_collision_a_b == 1'b1 && display_flag) + + if (({wea_reg, web_int}) == 2'b11) + $display("Memory Collision Error on RAMB4_S1_S4:%m at simulation time %.3f ns\nA write was requested to the same address simultaneously at both Port A and Port B of the RAM. The contents written to the RAM at address location %h (hex) of Port A and address location %h (hex) of Port B are unknown.", $time/1000.0, addra_int, addrb_int); + + else if (({wea_reg, web_int}) == 2'b01) + $display("Memory Collision Error on RAMB4_S1_S4:%m at simulation time %.3f ns\nA read was performed on address %h (hex) of Port A while a write was requested to the same address on Port B. The write will be successful however the read value on Port A is unknown until the next CLKA cycle.", $time/1000.0, addra_int); + + else if (({wea_reg, web_int}) == 2'b10) + $display("Memory Collision Error on RAMB4_S1_S4:%m at simulation time %.3f ns\nA read was performed on address %h (hex) of Port B while a write was requested to the same address on Port A. The write will be successful however the read value on Port B is unknown until the next CLKB cycle.", $time/1000.0, addrb_int); + + end + endtask + + always @(posedge setup_all_b_a) begin + if ((ena_int == 1) && (enb_reg == 1)) begin + case ({wea_int, web_reg}) + 6'b11 : begin data_collision_b_a <= 2'b11; display_all_b_a; end + 6'b01 : begin data_collision_b_a <= 2'b10; display_all_b_a; end + 6'b10 : begin data_collision_b_a <= 2'b01; display_all_b_a; end + endcase + end + setup_all_b_a <= 0; + end + + task display_all_b_a; + begin + address_collision_b_a = 1'b0; + for (ci = 0; ci < 4; ci = ci + 1) begin + if ((mem_addra_int) == (mem_addrb_reg + ci)) begin + address_collision_b_a = 1'b1; + end + end + if (address_collision_b_a == 1'b1 && display_flag) + + if (({wea_int, web_reg}) == 2'b11) + $display("Memory Collision Error on RAMB4_S1_S4:%m at simulation time %.3f ns\nA write was requested to the same address simultaneously at both Port A and Port B of the RAM. The contents written to the RAM at address location %h (hex) of Port A and address location %h (hex) of Port B are unknown.", $time/1000.0, addra_int, addrb_int); + + else if (({wea_int, web_reg}) == 2'b01) + $display("Memory Collision Error on RAMB4_S1_S4:%m at simulation time %.3f ns\nA read was performed on address %h (hex) of Port A while a write was requested to the same address on Port B. The write will be successful however the read value on Port A is unknown until the next CLKA cycle.", $time/1000.0, addra_int); + + else if (({wea_int, web_reg}) == 2'b10) + $display("Memory Collision Error on RAMB4_S1_S4:%m at simulation time %.3f ns\nA read was performed on address %h (hex) of Port B while a write was requested to the same address on Port A. The write will be successful however the read value on Port B is unknown until the next CLKB cycle.", $time/1000.0, addrb_int); + + end + endtask + + always @(posedge setup_zero) begin + if ((ena_int == 1) && (enb_int == 1)) begin + case ({wea_int, web_int}) + 6'b11 : begin data_collision <= 2'b11; display_zero; end + 6'b01 : begin data_collision <= 2'b10; display_zero; end + 6'b10 : begin data_collision <= 2'b01; display_zero; end + endcase + end + setup_zero <= 0; + end + + task display_zero; + begin + address_collision = 1'b0; + for (ci = 0; ci < 4; ci = ci + 1) begin + if ((mem_addra_int) == (mem_addrb_int + ci)) begin + address_collision = 1'b1; + end + end + if (address_collision == 1'b1 && display_flag) + + if (({wea_int, web_int}) == 2'b11) + $display("Memory Collision Error on RAMB4_S1_S4:%m at simulation time %.3f ns\nA write was requested to the same address simultaneously at both Port A and Port B of the RAM. The contents written to the RAM at address location %h (hex) of Port A and address location %h (hex) of Port B are unknown.", $time/1000.0, addra_int, addrb_int); + + else if (({wea_int, web_int}) == 2'b01) + $display("Memory Collision Error on RAMB4_S1_S4:%m at simulation time %.3f ns\nA read was performed on address %h (hex) of Port A while a write was requested to the same address on Port B. The write will be successful however the read value on Port A is unknown until the next CLKA cycle.", $time/1000.0, addra_int); + + else if (({wea_int, web_int}) == 2'b10) + $display("Memory Collision Error on RAMB4_S1_S4:%m at simulation time %.3f ns\nA read was performed on address %h (hex) of Port B while a write was requested to the same address on Port A. The write will be successful however the read value on Port B is unknown until the next CLKB cycle.", $time/1000.0, addrb_int); + + end + endtask + + always @(posedge clka_int) begin + if ((output_flag || display_flag)) begin + addra_reg <= addra_int; + ena_reg <= ena_int; + rsta_reg <= rsta_int; + wea_reg <= wea_int; + end + end + + always @(posedge clkb_int) begin + if ((output_flag || display_flag)) begin + addrb_reg <= addrb_int; + enb_reg <= enb_int; + rstb_reg <= rstb_int; + web_reg <= web_int; + end + end + + + // Data + always @(posedge memory_collision) begin + if ((output_flag || display_flag)) begin + for (mi = 0; mi < 4; mi = mi + 1) begin + if ((mem_addra_int) == (mem_addrb_int + mi)) begin + mem[addra_int[11:2]][addra_int[1:0] * 1 +: 1] <= 1'bx; + end + end + memory_collision <= 0; + end + end + + always @(posedge memory_collision_a_b) begin + if ((output_flag || display_flag)) begin + for (mi = 0; mi < 4; mi = mi + 1) begin + if ((mem_addra_reg) == (mem_addrb_int + mi)) begin + mem[addra_reg[11:2]][addra_reg[1:0] * 1 +: 1] <= 1'bx; + end + end + memory_collision_a_b <= 0; + end + end + + always @(posedge memory_collision_b_a) begin + if ((output_flag || display_flag)) begin + for (mi = 0; mi < 4; mi = mi + 1) begin + if ((mem_addra_int) == (mem_addrb_reg + mi)) begin + mem[addra_int[11:2]][addra_int[1:0] * 1 +: 1] <= 1'bx; + end + end + memory_collision_b_a <= 0; + end + end + + always @(posedge data_collision[1]) begin + if (rsta_int == 0 && output_flag) begin + for (ai = 0; ai < 4; ai = ai + 1) begin + if ((mem_addra_int) == (mem_addrb_int + ai)) begin + doa_out <= #100 1'bX; + end + end + end + data_collision[1] <= 0; + end + + always @(posedge data_collision[0]) begin + if (rstb_int == 0 && output_flag) begin + for (bi = 0; bi < 4; bi = bi + 1) begin + if ((mem_addra_int) == (mem_addrb_int + bi)) begin + for (bj = 0; bj < 1; bj = bj + 1) begin + dob_out[bi + bj] <= #100 1'bX; + end + end + end + end + data_collision[0] <= 0; + end + + always @(posedge data_collision_a_b[1]) begin + if (rsta_reg == 0 && output_flag) begin + for (ai = 0; ai < 4; ai = ai + 1) begin + if ((mem_addra_reg) == (mem_addrb_int + ai)) begin + doa_out <= #100 1'bX; + end + end + end + data_collision_a_b[1] <= 0; + end + + always @(posedge data_collision_a_b[0]) begin + if (rstb_int == 0 && output_flag) begin + for (bi = 0; bi < 4; bi = bi + 1) begin + if ((mem_addra_reg) == (mem_addrb_int + bi)) begin + for (bj = 0; bj < 1; bj = bj + 1) begin + dob_out[bi + bj] <= #100 1'bX; + end + end + end + end + data_collision_a_b[0] <= 0; + end + + always @(posedge data_collision_b_a[1]) begin + if (rsta_int == 0 && output_flag) begin + for (ai = 0; ai < 4; ai = ai + 1) begin + if ((mem_addra_int) == (mem_addrb_reg + ai)) begin + doa_out <= #100 1'bX; + end + end + end + data_collision_b_a[1] <= 0; + end + + always @(posedge data_collision_b_a[0]) begin + if (rstb_reg == 0 && output_flag) begin + for (bi = 0; bi < 4; bi = bi + 1) begin + if ((mem_addra_int) == (mem_addrb_reg + bi)) begin + for (bj = 0; bj < 1; bj = bj + 1) begin + dob_out[bi + bj] <= #100 1'bX; + end + end + end + end + data_collision_b_a[0] <= 0; + end + + + // Port A + always @(posedge clka_int) begin + + if (ena_int == 1'b1) begin + + if (rsta_int == 1'b1) begin + doa_out <= #100 0; + end + else begin + if (wea_int == 1'b1) + doa_out <= #100 dia_int; + else + doa_out <= #100 mem[addra_int[11:2]][addra_int[1:0] * 1 +: 1]; + end + + // memory + if (wea_int == 1'b1) begin + mem[addra_int[11:2]][addra_int[1:0] * 1 +: 1] <= dia_int; + end + + end + end + + + // Port B + always @(posedge clkb_int) begin + + if (enb_int == 1'b1) begin + + if (rstb_int == 1'b1) begin + dob_out <= #100 0; + end + else begin + if (web_int == 1'b1) + dob_out <= #100 dib_int; + else + dob_out <= #100 mem[addrb_int]; + end + + // memory + if (web_int == 1'b1) begin + mem[addrb_int] <= dib_int; + end + + end + end + + +endmodule + +`endif diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/RAMB4_S1_S8.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/RAMB4_S1_S8.v new file mode 100644 index 0000000..3b060fa --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/RAMB4_S1_S8.v @@ -0,0 +1,1071 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/RAMB4_S1_S8.v,v 1.9 2007/02/22 01:58:06 wloo Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2005 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / 4K-Bit Data Dual Port Block RAM +// /___/ /\ Filename : RAMB4_S1_S8.v +// \ \ / \ Timestamp : Thu Mar 10 16:43:38 PST 2005 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// End Revision + +`ifdef legacy_model + +`timescale 1 ps / 1 ps + +module RAMB4_S1_S8 (DOA, DOB, ADDRA, ADDRB, CLKA, CLKB, DIA, DIB, ENA, ENB, RSTA, RSTB, WEA, WEB); + + parameter SIM_COLLISION_CHECK = "ALL"; + localparam SETUP_ALL = 100; + + parameter INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + + output [0:0] DOA; + reg [0:0] doa_out; + wire doa_out0; + + input [11:0] ADDRA; + input [0:0] DIA; + input ENA, CLKA, WEA, RSTA; + + output [7:0] DOB; + reg [7:0] dob_out; + wire dob_out0, dob_out1, dob_out2, dob_out3, dob_out4, dob_out5, dob_out6, dob_out7; + + input [8:0] ADDRB; + input [7:0] DIB; + input ENB, CLKB, WEB, RSTB; + + reg [4095:0] mem; + reg [8:0] count; + + reg [5:0] mi, mj, ai, aj, bi, bj, ci, cj, di, dj, ei, ej, fi, fj; + + wire [11:0] addra_int; + reg [11:0] addra_reg; + wire [0:0] dia_int; + wire ena_int, clka_int, wea_int, rsta_int; + reg ena_reg, wea_reg, rsta_reg; + wire [8:0] addrb_int; + reg [8:0] addrb_reg; + wire [7:0] dib_int; + wire enb_int, clkb_int, web_int, rstb_int; + reg enb_reg, web_reg, rstb_reg; + + time time_clka, time_clkb; + time time_clka_clkb; + time time_clkb_clka; + + reg setup_all_a_b; + reg setup_all_b_a; + reg setup_zero; + reg [1:0] data_collision, data_collision_a_b, data_collision_b_a; + reg memory_collision, memory_collision_a_b, memory_collision_b_a; + reg address_collision, address_collision_a_b, address_collision_b_a; + reg change_clka; + reg change_clkb; + + wire [11:0] mem_addra_int; + wire [11:0] mem_addra_reg; + wire [11:0] mem_addrb_int; + wire [11:0] mem_addrb_reg; + + tri0 GSR = glbl.GSR; + + always @(GSR) + if (GSR) begin + assign doa_out = 0; + end + else begin + deassign doa_out; + end + + always @(GSR) + if (GSR) begin + assign dob_out = 0; + end + else begin + deassign dob_out; + end + + buf b_doa_out0 (doa_out0, doa_out[0]); + buf b_dob_out0 (dob_out0, dob_out[0]); + buf b_dob_out1 (dob_out1, dob_out[1]); + buf b_dob_out2 (dob_out2, dob_out[2]); + buf b_dob_out3 (dob_out3, dob_out[3]); + buf b_dob_out4 (dob_out4, dob_out[4]); + buf b_dob_out5 (dob_out5, dob_out[5]); + buf b_dob_out6 (dob_out6, dob_out[6]); + buf b_dob_out7 (dob_out7, dob_out[7]); + buf b_doa0 (DOA[0], doa_out0); + buf b_dob0 (DOB[0], dob_out0); + buf b_dob1 (DOB[1], dob_out1); + buf b_dob2 (DOB[2], dob_out2); + buf b_dob3 (DOB[3], dob_out3); + buf b_dob4 (DOB[4], dob_out4); + buf b_dob5 (DOB[5], dob_out5); + buf b_dob6 (DOB[6], dob_out6); + buf b_dob7 (DOB[7], dob_out7); + buf b_addra_0 (addra_int[0], ADDRA[0]); + buf b_addra_1 (addra_int[1], ADDRA[1]); + buf b_addra_2 (addra_int[2], ADDRA[2]); + buf b_addra_3 (addra_int[3], ADDRA[3]); + buf b_addra_4 (addra_int[4], ADDRA[4]); + buf b_addra_5 (addra_int[5], ADDRA[5]); + buf b_addra_6 (addra_int[6], ADDRA[6]); + buf b_addra_7 (addra_int[7], ADDRA[7]); + buf b_addra_8 (addra_int[8], ADDRA[8]); + buf b_addra_9 (addra_int[9], ADDRA[9]); + buf b_addra_10 (addra_int[10], ADDRA[10]); + buf b_addra_11 (addra_int[11], ADDRA[11]); + buf b_dia_0 (dia_int[0], DIA[0]); + buf b_clka (clka_int, CLKA); + buf b_ena (ena_int, ENA); + buf b_rsta (rsta_int, RSTA); + buf b_wea (wea_int, WEA); + buf b_addrb_0 (addrb_int[0], ADDRB[0]); + buf b_addrb_1 (addrb_int[1], ADDRB[1]); + buf b_addrb_2 (addrb_int[2], ADDRB[2]); + buf b_addrb_3 (addrb_int[3], ADDRB[3]); + buf b_addrb_4 (addrb_int[4], ADDRB[4]); + buf b_addrb_5 (addrb_int[5], ADDRB[5]); + buf b_addrb_6 (addrb_int[6], ADDRB[6]); + buf b_addrb_7 (addrb_int[7], ADDRB[7]); + buf b_addrb_8 (addrb_int[8], ADDRB[8]); + buf b_dib_0 (dib_int[0], DIB[0]); + buf b_dib_1 (dib_int[1], DIB[1]); + buf b_dib_2 (dib_int[2], DIB[2]); + buf b_dib_3 (dib_int[3], DIB[3]); + buf b_dib_4 (dib_int[4], DIB[4]); + buf b_dib_5 (dib_int[5], DIB[5]); + buf b_dib_6 (dib_int[6], DIB[6]); + buf b_dib_7 (dib_int[7], DIB[7]); + buf b_clkb (clkb_int, CLKB); + buf b_enb (enb_int, ENB); + buf b_rstb (rstb_int, RSTB); + buf b_web (web_int, WEB); + + initial begin + for (count = 0; count < 256; count = count + 1) begin + mem[count] <= INIT_00[count]; + mem[256 * 1 + count] <= INIT_01[count]; + mem[256 * 2 + count] <= INIT_02[count]; + mem[256 * 3 + count] <= INIT_03[count]; + mem[256 * 4 + count] <= INIT_04[count]; + mem[256 * 5 + count] <= INIT_05[count]; + mem[256 * 6 + count] <= INIT_06[count]; + mem[256 * 7 + count] <= INIT_07[count]; + mem[256 * 8 + count] <= INIT_08[count]; + mem[256 * 9 + count] <= INIT_09[count]; + mem[256 * 10 + count] <= INIT_0A[count]; + mem[256 * 11 + count] <= INIT_0B[count]; + mem[256 * 12 + count] <= INIT_0C[count]; + mem[256 * 13 + count] <= INIT_0D[count]; + mem[256 * 14 + count] <= INIT_0E[count]; + mem[256 * 15 + count] <= INIT_0F[count]; + end + address_collision <= 0; + address_collision_a_b <= 0; + address_collision_b_a <= 0; + change_clka <= 0; + change_clkb <= 0; + data_collision <= 0; + data_collision_a_b <= 0; + data_collision_b_a <= 0; + memory_collision <= 0; + memory_collision_a_b <= 0; + memory_collision_b_a <= 0; + setup_all_a_b <= 0; + setup_all_b_a <= 0; + setup_zero <= 0; + end + + assign mem_addra_int = addra_int * 1; + assign mem_addra_reg = addra_reg * 1; + assign mem_addrb_int = addrb_int * 8; + assign mem_addrb_reg = addrb_reg * 8; + + + initial begin + + case (SIM_COLLISION_CHECK) + + "NONE" : begin + assign setup_all_a_b = 1'b0; + assign setup_all_b_a = 1'b0; + assign setup_zero = 1'b0; + assign address_collision = 1'b0; + assign address_collision_a_b = 1'b0; + assign address_collision_b_a = 1'b0; + end + "WARNING_ONLY" : begin + assign data_collision = 2'b00; + assign data_collision_a_b = 2'b00; + assign data_collision_b_a = 2'b00; + assign memory_collision = 1'b0; + assign memory_collision_a_b = 1'b0; + assign memory_collision_b_a = 1'b0; + end + "GENERATE_X_ONLY" : begin + assign address_collision = 1'b0; + assign address_collision_a_b = 1'b0; + assign address_collision_b_a = 1'b0; + end + "ALL" : ; + default : begin + $display("Attribute Syntax Error : The Attribute SIM_COLLISION_CHECK on RAMB4_S1_S8 instance %m is set to %s. Legal values for this attribute are ALL, NONE, WARNING_ONLY or GENERATE_X_ONLY.", SIM_COLLISION_CHECK); + $finish; + end + + endcase // case(SIM_COLLISION_CHECK) + + end // initial begin + + + always @(posedge clka_int) begin + time_clka = $time; + #0 time_clkb_clka = time_clka - time_clkb; + change_clka = ~change_clka; + end + + always @(posedge clkb_int) begin + time_clkb = $time; + #0 time_clka_clkb = time_clkb - time_clka; + change_clkb = ~change_clkb; + end + + always @(change_clkb) begin + if ((0 < time_clka_clkb) && (time_clka_clkb < SETUP_ALL)) + setup_all_a_b = 1; + end + + always @(change_clka) begin + if ((0 < time_clkb_clka) && (time_clkb_clka < SETUP_ALL)) + setup_all_b_a = 1; + end + + always @(change_clkb or change_clka) begin + if ((time_clkb_clka == 0) && (time_clka_clkb == 0)) + setup_zero = 1; + end + + always @(posedge setup_zero) begin + if ((ena_int == 1) && (wea_int == 1) && + (enb_int == 1) && (web_int == 1)) + memory_collision <= 1; + end + + always @(posedge setup_all_a_b) begin + if ((ena_reg == 1) && (enb_int == 1)) begin + case ({wea_reg, web_int}) + 6'b11 : begin data_collision_a_b <= 2'b11; display_all_a_b; end + 6'b01 : begin data_collision_a_b <= 2'b10; display_all_a_b; end + 6'b10 : begin data_collision_a_b <= 2'b01; display_all_a_b; end + endcase + end + setup_all_a_b <= 0; + end + + task display_all_a_b; + begin + address_collision_a_b = 1'b0; + for (ci = 0; ci < 8; ci = ci + 1) begin + if ((mem_addra_reg) == (mem_addrb_int + ci)) begin + address_collision_a_b = 1'b1; + end + end + if (address_collision_a_b == 1'b1) + + if (({wea_reg, web_int}) == 2'b11) + $display("Memory Collision Error on RAMB4_S1_S8:%m at simulation time %.3f ns\nA write was requested to the same address simultaneously at both Port A and Port B of the RAM. The contents written to the RAM at address location %h (hex) of Port A and address location %h (hex) of Port B are unknown.", $time/1000.0, addra_int, addrb_int); + + else if (({wea_reg, web_int}) == 2'b01) + $display("Memory Collision Error on RAMB4_S1_S8:%m at simulation time %.3f ns\nA read was performed on address %h (hex) of Port A while a write was requested to the same address on Port B. The write will be successful however the read value on Port A is unknown until the next CLKA cycle.", $time/1000.0, addra_int); + + else if (({wea_reg, web_int}) == 2'b10) + $display("Memory Collision Error on RAMB4_S1_S8:%m at simulation time %.3f ns\nA read was performed on address %h (hex) of Port B while a write was requested to the same address on Port A. The write will be successful however the read value on Port B is unknown until the next CLKB cycle.", $time/1000.0, addrb_int); + + end + endtask + + always @(posedge setup_all_b_a) begin + if ((ena_int == 1) && (enb_reg == 1)) begin + case ({wea_int, web_reg}) + 6'b11 : begin data_collision_b_a <= 2'b11; display_all_b_a; end + 6'b01 : begin data_collision_b_a <= 2'b10; display_all_b_a; end + 6'b10 : begin data_collision_b_a <= 2'b01; display_all_b_a; end + endcase + end + setup_all_b_a <= 0; + end + + task display_all_b_a; + begin + address_collision_b_a = 1'b0; + for (ci = 0; ci < 8; ci = ci + 1) begin + if ((mem_addra_int) == (mem_addrb_reg + ci)) begin + address_collision_b_a = 1'b1; + end + end + if (address_collision_b_a == 1'b1) + + if (({wea_int, web_reg}) == 2'b11) + $display("Memory Collision Error on RAMB4_S1_S8:%m at simulation time %.3f ns\nA write was requested to the same address simultaneously at both Port A and Port B of the RAM. The contents written to the RAM at address location %h (hex) of Port A and address location %h (hex) of Port B are unknown.", $time/1000.0, addra_int, addrb_int); + + else if (({wea_int, web_reg}) == 2'b01) + $display("Memory Collision Error on RAMB4_S1_S8:%m at simulation time %.3f ns\nA read was performed on address %h (hex) of Port A while a write was requested to the same address on Port B. The write will be successful however the read value on Port A is unknown until the next CLKA cycle.", $time/1000.0, addra_int); + + else if (({wea_int, web_reg}) == 2'b10) + $display("Memory Collision Error on RAMB4_S1_S8:%m at simulation time %.3f ns\nA read was performed on address %h (hex) of Port B while a write was requested to the same address on Port A. The write will be successful however the read value on Port B is unknown until the next CLKB cycle.", $time/1000.0, addrb_int); + + end + endtask + + always @(posedge setup_zero) begin + if ((ena_int == 1) && (enb_int == 1)) begin + case ({wea_int, web_int}) + 6'b11 : begin data_collision <= 2'b11; display_zero; end + 6'b01 : begin data_collision <= 2'b10; display_zero; end + 6'b10 : begin data_collision <= 2'b01; display_zero; end + endcase + end + setup_zero <= 0; + end + + task display_zero; + begin + address_collision = 1'b0; + for (ci = 0; ci < 8; ci = ci + 1) begin + if ((mem_addra_int) == (mem_addrb_int + ci)) begin + address_collision = 1'b1; + end + end + if (address_collision == 1'b1) + + if (({wea_int, web_int}) == 2'b11) + $display("Memory Collision Error on RAMB4_S1_S8:%m at simulation time %.3f ns\nA write was requested to the same address simultaneously at both Port A and Port B of the RAM. The contents written to the RAM at address location %h (hex) of Port A and address location %h (hex) of Port B are unknown.", $time/1000.0, addra_int, addrb_int); + + else if (({wea_int, web_int}) == 2'b01) + $display("Memory Collision Error on RAMB4_S1_S8:%m at simulation time %.3f ns\nA read was performed on address %h (hex) of Port A while a write was requested to the same address on Port B. The write will be successful however the read value on Port A is unknown until the next CLKA cycle.", $time/1000.0, addra_int); + + else if (({wea_int, web_int}) == 2'b10) + $display("Memory Collision Error on RAMB4_S1_S8:%m at simulation time %.3f ns\nA read was performed on address %h (hex) of Port B while a write was requested to the same address on Port A. The write will be successful however the read value on Port B is unknown until the next CLKB cycle.", $time/1000.0, addrb_int); + + end + endtask + + always @(posedge clka_int) begin + addra_reg <= addra_int; + ena_reg <= ena_int; + rsta_reg <= rsta_int; + wea_reg <= wea_int; + end + + always @(posedge clkb_int) begin + addrb_reg <= addrb_int; + enb_reg <= enb_int; + rstb_reg <= rstb_int; + web_reg <= web_int; + end + + // Data + always @(posedge memory_collision) begin + for (mi = 0; mi < 8; mi = mi + 1) begin + if ((mem_addra_int) == (mem_addrb_int + mi)) begin + for (mj = 0; mj < 1; mj = mj + 1) begin + mem[mem_addrb_int + mi + mj] <= 1'bX; + end + end + end + memory_collision <= 0; + end + + always @(posedge memory_collision_a_b) begin + for (mi = 0; mi < 8; mi = mi + 1) begin + if ((mem_addra_reg) == (mem_addrb_int + mi)) begin + for (mj = 0; mj < 1; mj = mj + 1) begin + mem[mem_addrb_int + mi + mj] <= 1'bX; + end + end + end + memory_collision_a_b <= 0; + end + + always @(posedge memory_collision_b_a) begin + for (mi = 0; mi < 8; mi = mi + 1) begin + if ((mem_addra_int) == (mem_addrb_reg + mi)) begin + for (mj = 0; mj < 1; mj = mj + 1) begin + mem[mem_addrb_reg + mi + mj] <= 1'bX; + end + end + end + memory_collision_b_a <= 0; + end + + always @(posedge data_collision[1]) begin + if (rsta_int == 0) begin + for (ai = 0; ai < 8; ai = ai + 1) begin + if ((mem_addra_int) == (mem_addrb_int + ai)) begin + doa_out <= 1'bX; + end + end + end + data_collision[1] <= 0; + end + + always @(posedge data_collision[0]) begin + if (rstb_int == 0) begin + for (bi = 0; bi < 8; bi = bi + 1) begin + if ((mem_addra_int) == (mem_addrb_int + bi)) begin + for (bj = 0; bj < 1; bj = bj + 1) begin + dob_out[bi + bj] <= 1'bX; + end + end + end + end + data_collision[0] <= 0; + end + + always @(posedge data_collision_a_b[1]) begin + if (rsta_reg == 0) begin + for (ai = 0; ai < 8; ai = ai + 1) begin + if ((mem_addra_reg) == (mem_addrb_int + ai)) begin + doa_out <= 1'bX; + end + end + end + data_collision_a_b[1] <= 0; + end + + always @(posedge data_collision_a_b[0]) begin + if (rstb_int == 0) begin + for (bi = 0; bi < 8; bi = bi + 1) begin + if ((mem_addra_reg) == (mem_addrb_int + bi)) begin + for (bj = 0; bj < 1; bj = bj + 1) begin + dob_out[bi + bj] <= 1'bX; + end + end + end + end + data_collision_a_b[0] <= 0; + end + + always @(posedge data_collision_b_a[1]) begin + if (rsta_int == 0) begin + for (ai = 0; ai < 8; ai = ai + 1) begin + if ((mem_addra_int) == (mem_addrb_reg + ai)) begin + doa_out <= 1'bX; + end + end + end + data_collision_b_a[1] <= 0; + end + + always @(posedge data_collision_b_a[0]) begin + if (rstb_reg == 0) begin + for (bi = 0; bi < 8; bi = bi + 1) begin + if ((mem_addra_int) == (mem_addrb_reg + bi)) begin + for (bj = 0; bj < 1; bj = bj + 1) begin + dob_out[bi + bj] <= 1'bX; + end + end + end + end + data_collision_b_a[0] <= 0; + end + + + always @(posedge clka_int) begin + if (ena_int == 1'b1) begin + if (rsta_int == 1'b1) begin + doa_out <= 1'b0; + end + else if (wea_int == 0) begin + doa_out[0] <= mem[mem_addra_int + 0]; + end + else begin + doa_out <= dia_int; + end + end + end + + always @(posedge clka_int) begin + if (ena_int == 1'b1 && wea_int == 1'b1) begin + mem[mem_addra_int + 0] <= dia_int[0]; + end + end + + always @(posedge clkb_int) begin + if (enb_int == 1'b1) begin + if (rstb_int == 1'b1) begin + dob_out <= 8'b0; + end + else if (web_int == 0) begin + dob_out[0] <= mem[mem_addrb_int + 0]; + dob_out[1] <= mem[mem_addrb_int + 1]; + dob_out[2] <= mem[mem_addrb_int + 2]; + dob_out[3] <= mem[mem_addrb_int + 3]; + dob_out[4] <= mem[mem_addrb_int + 4]; + dob_out[5] <= mem[mem_addrb_int + 5]; + dob_out[6] <= mem[mem_addrb_int + 6]; + dob_out[7] <= mem[mem_addrb_int + 7]; + end + else begin + dob_out <= dib_int; + end + end + end + + always @(posedge clkb_int) begin + if (enb_int == 1'b1 && web_int == 1'b1) begin + mem[mem_addrb_int + 0] <= dib_int[0]; + mem[mem_addrb_int + 1] <= dib_int[1]; + mem[mem_addrb_int + 2] <= dib_int[2]; + mem[mem_addrb_int + 3] <= dib_int[3]; + mem[mem_addrb_int + 4] <= dib_int[4]; + mem[mem_addrb_int + 5] <= dib_int[5]; + mem[mem_addrb_int + 6] <= dib_int[6]; + mem[mem_addrb_int + 7] <= dib_int[7]; + end + end + + specify + (CLKA *> DOA) = (100, 100); + (CLKB *> DOB) = (100, 100); + endspecify + +endmodule + +`else + +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/RAMB4_S1_S8.v,v 1.9 2007/02/22 01:58:06 wloo Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2005 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Timing Simulation Library Component +// / / 16K-Bit Data and 2K-Bit Parity Dual Port Block RAM +// /___/ /\ Filename : RAMB4_S1_S8.v +// \ \ / \ Timestamp : Thu Mar 10 16:44:01 PST 2005 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 03/10/05 - Initialized outputs. +// 02/21/07 - Fixed parameter SIM_COLLISION_CHECK (CR 433281). +// End Revision + +`timescale 1 ps/1 ps + +module RAMB4_S1_S8 (DOA, DOB, ADDRA, ADDRB, CLKA, CLKB, DIA, DIB, ENA, ENB, RSTA, RSTB, WEA, WEB); + + parameter SIM_COLLISION_CHECK = "ALL"; + localparam SETUP_ALL = 100; + + parameter INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + + output [0:0] DOA; + output [7:0] DOB; + + input [11:0] ADDRA; + input [0:0] DIA; + input ENA, CLKA, WEA, RSTA; + input [8:0] ADDRB; + input [7:0] DIB; + input ENB, CLKB, WEB, RSTB; + + reg [0:0] doa_out = 0; + reg [7:0] dob_out = 0; + + reg [7:0] mem [511:0]; + + reg [8:0] count; + + reg [5:0] mi, ai, bi, bj, ci; + + wire [11:0] addra_int; + reg [11:0] addra_reg; + wire [0:0] dia_int; + wire ena_int, clka_int, wea_int, rsta_int; + reg ena_reg, wea_reg, rsta_reg; + wire [8:0] addrb_int; + reg [8:0] addrb_reg; + wire [7:0] dib_int; + wire enb_int, clkb_int, web_int, rstb_int; + reg display_flag, output_flag; + reg enb_reg, web_reg, rstb_reg; + + time time_clka, time_clkb; + time time_clka_clkb; + time time_clkb_clka; + + reg setup_all_a_b; + reg setup_all_b_a; + reg setup_zero; + reg [1:0] data_collision, data_collision_a_b, data_collision_b_a; + reg memory_collision, memory_collision_a_b, memory_collision_b_a; + reg address_collision, address_collision_a_b, address_collision_b_a; + reg change_clka; + reg change_clkb; + + wire [11:0] mem_addra_int; + wire [11:0] mem_addra_reg; + wire [11:0] mem_addrb_int; + wire [11:0] mem_addrb_reg; + + wire dia_enable = ena_int && wea_int; + wire dib_enable = enb_int && web_int; + + tri0 GSR = glbl.GSR; + wire gsr_int; + + buf b_gsr (gsr_int, GSR); + + buf b_doa [0:0] (DOA, doa_out); + buf b_addra [11:0] (addra_int, ADDRA); + buf b_dia [0:0] (dia_int, DIA); + buf b_ena (ena_int, ENA); + buf b_clka (clka_int, CLKA); + buf b_rsta (rsta_int, RSTA); + buf b_wea (wea_int, WEA); + + buf b_dob [7:0] (DOB, dob_out); + buf b_addrb [8:0] (addrb_int, ADDRB); + buf b_dib [7:0] (dib_int, DIB); + buf b_enb (enb_int, ENB); + buf b_clkb (clkb_int, CLKB); + buf b_rstb (rstb_int, RSTB); + buf b_web (web_int, WEB); + + + always @(gsr_int) + if (gsr_int) begin + assign doa_out = 0; + assign dob_out = 0; + end + else begin + deassign doa_out; + deassign dob_out; + end + + + initial begin + + for (count = 0; count < 32; count = count + 1) begin + mem[count] = INIT_00[(count * 8) +: 8]; + mem[32 * 1 + count] = INIT_01[(count * 8) +: 8]; + mem[32 * 2 + count] = INIT_02[(count * 8) +: 8]; + mem[32 * 3 + count] = INIT_03[(count * 8) +: 8]; + mem[32 * 4 + count] = INIT_04[(count * 8) +: 8]; + mem[32 * 5 + count] = INIT_05[(count * 8) +: 8]; + mem[32 * 6 + count] = INIT_06[(count * 8) +: 8]; + mem[32 * 7 + count] = INIT_07[(count * 8) +: 8]; + mem[32 * 8 + count] = INIT_08[(count * 8) +: 8]; + mem[32 * 9 + count] = INIT_09[(count * 8) +: 8]; + mem[32 * 10 + count] = INIT_0A[(count * 8) +: 8]; + mem[32 * 11 + count] = INIT_0B[(count * 8) +: 8]; + mem[32 * 12 + count] = INIT_0C[(count * 8) +: 8]; + mem[32 * 13 + count] = INIT_0D[(count * 8) +: 8]; + mem[32 * 14 + count] = INIT_0E[(count * 8) +: 8]; + mem[32 * 15 + count] = INIT_0F[(count * 8) +: 8]; + end + + change_clka <= 0; + change_clkb <= 0; + data_collision <= 0; + data_collision_a_b <= 0; + data_collision_b_a <= 0; + memory_collision <= 0; + memory_collision_a_b <= 0; + memory_collision_b_a <= 0; + setup_all_a_b <= 0; + setup_all_b_a <= 0; + setup_zero <= 0; + end + + assign mem_addra_int = addra_int * 1; + assign mem_addra_reg = addra_reg * 1; + assign mem_addrb_int = addrb_int * 8; + assign mem_addrb_reg = addrb_reg * 8; + + + initial begin + + display_flag = 1; + output_flag = 1; + + case (SIM_COLLISION_CHECK) + + "NONE" : begin + output_flag = 0; + display_flag = 0; + end + "WARNING_ONLY" : output_flag = 0; + "GENERATE_X_ONLY" : display_flag = 0; + "ALL" : ; + + default : begin + $display("Attribute Syntax Error : The Attribute SIM_COLLISION_CHECK on RAMB4_S1_S8 instance %m is set to %s. Legal values for this attribute are ALL, NONE, WARNING_ONLY or GENERATE_X_ONLY.", SIM_COLLISION_CHECK); + $finish; + end + + endcase // case(SIM_COLLISION_CHECK) + + end // initial begin + + + always @(posedge clka_int) begin + if ((output_flag || display_flag)) begin + time_clka = $time; + #0 time_clkb_clka = time_clka - time_clkb; + change_clka = ~change_clka; + end + end + + always @(posedge clkb_int) begin + if ((output_flag || display_flag)) begin + time_clkb = $time; + #0 time_clka_clkb = time_clkb - time_clka; + change_clkb = ~change_clkb; + end + end + + always @(change_clkb) begin + if ((0 < time_clka_clkb) && (time_clka_clkb < SETUP_ALL)) + setup_all_a_b = 1; + end + + always @(change_clka) begin + if ((0 < time_clkb_clka) && (time_clkb_clka < SETUP_ALL)) + setup_all_b_a = 1; + end + + always @(change_clkb or change_clka) begin + if ((time_clkb_clka == 0) && (time_clka_clkb == 0)) + setup_zero = 1; + end + + always @(posedge setup_zero) begin + if ((ena_int == 1) && (wea_int == 1) && + (enb_int == 1) && (web_int == 1)) + memory_collision <= 1; + end + + always @(posedge setup_all_a_b) begin + if ((ena_reg == 1) && (enb_int == 1)) begin + case ({wea_reg, web_int}) + 6'b11 : begin data_collision_a_b <= 2'b11; display_all_a_b; end + 6'b01 : begin data_collision_a_b <= 2'b10; display_all_a_b; end + 6'b10 : begin data_collision_a_b <= 2'b01; display_all_a_b; end + endcase + end + setup_all_a_b <= 0; + end + + task display_all_a_b; + begin + address_collision_a_b = 1'b0; + for (ci = 0; ci < 8; ci = ci + 1) begin + if ((mem_addra_reg) == (mem_addrb_int + ci)) begin + address_collision_a_b = 1'b1; + end + end + if (address_collision_a_b == 1'b1 && display_flag) + + if (({wea_reg, web_int}) == 2'b11) + $display("Memory Collision Error on RAMB4_S1_S8:%m at simulation time %.3f ns\nA write was requested to the same address simultaneously at both Port A and Port B of the RAM. The contents written to the RAM at address location %h (hex) of Port A and address location %h (hex) of Port B are unknown.", $time/1000.0, addra_int, addrb_int); + + else if (({wea_reg, web_int}) == 2'b01) + $display("Memory Collision Error on RAMB4_S1_S8:%m at simulation time %.3f ns\nA read was performed on address %h (hex) of Port A while a write was requested to the same address on Port B. The write will be successful however the read value on Port A is unknown until the next CLKA cycle.", $time/1000.0, addra_int); + + else if (({wea_reg, web_int}) == 2'b10) + $display("Memory Collision Error on RAMB4_S1_S8:%m at simulation time %.3f ns\nA read was performed on address %h (hex) of Port B while a write was requested to the same address on Port A. The write will be successful however the read value on Port B is unknown until the next CLKB cycle.", $time/1000.0, addrb_int); + + end + endtask + + always @(posedge setup_all_b_a) begin + if ((ena_int == 1) && (enb_reg == 1)) begin + case ({wea_int, web_reg}) + 6'b11 : begin data_collision_b_a <= 2'b11; display_all_b_a; end + 6'b01 : begin data_collision_b_a <= 2'b10; display_all_b_a; end + 6'b10 : begin data_collision_b_a <= 2'b01; display_all_b_a; end + endcase + end + setup_all_b_a <= 0; + end + + task display_all_b_a; + begin + address_collision_b_a = 1'b0; + for (ci = 0; ci < 8; ci = ci + 1) begin + if ((mem_addra_int) == (mem_addrb_reg + ci)) begin + address_collision_b_a = 1'b1; + end + end + if (address_collision_b_a == 1'b1 && display_flag) + + if (({wea_int, web_reg}) == 2'b11) + $display("Memory Collision Error on RAMB4_S1_S8:%m at simulation time %.3f ns\nA write was requested to the same address simultaneously at both Port A and Port B of the RAM. The contents written to the RAM at address location %h (hex) of Port A and address location %h (hex) of Port B are unknown.", $time/1000.0, addra_int, addrb_int); + + else if (({wea_int, web_reg}) == 2'b01) + $display("Memory Collision Error on RAMB4_S1_S8:%m at simulation time %.3f ns\nA read was performed on address %h (hex) of Port A while a write was requested to the same address on Port B. The write will be successful however the read value on Port A is unknown until the next CLKA cycle.", $time/1000.0, addra_int); + + else if (({wea_int, web_reg}) == 2'b10) + $display("Memory Collision Error on RAMB4_S1_S8:%m at simulation time %.3f ns\nA read was performed on address %h (hex) of Port B while a write was requested to the same address on Port A. The write will be successful however the read value on Port B is unknown until the next CLKB cycle.", $time/1000.0, addrb_int); + + end + endtask + + always @(posedge setup_zero) begin + if ((ena_int == 1) && (enb_int == 1)) begin + case ({wea_int, web_int}) + 6'b11 : begin data_collision <= 2'b11; display_zero; end + 6'b01 : begin data_collision <= 2'b10; display_zero; end + 6'b10 : begin data_collision <= 2'b01; display_zero; end + endcase + end + setup_zero <= 0; + end + + task display_zero; + begin + address_collision = 1'b0; + for (ci = 0; ci < 8; ci = ci + 1) begin + if ((mem_addra_int) == (mem_addrb_int + ci)) begin + address_collision = 1'b1; + end + end + if (address_collision == 1'b1 && display_flag) + + if (({wea_int, web_int}) == 2'b11) + $display("Memory Collision Error on RAMB4_S1_S8:%m at simulation time %.3f ns\nA write was requested to the same address simultaneously at both Port A and Port B of the RAM. The contents written to the RAM at address location %h (hex) of Port A and address location %h (hex) of Port B are unknown.", $time/1000.0, addra_int, addrb_int); + + else if (({wea_int, web_int}) == 2'b01) + $display("Memory Collision Error on RAMB4_S1_S8:%m at simulation time %.3f ns\nA read was performed on address %h (hex) of Port A while a write was requested to the same address on Port B. The write will be successful however the read value on Port A is unknown until the next CLKA cycle.", $time/1000.0, addra_int); + + else if (({wea_int, web_int}) == 2'b10) + $display("Memory Collision Error on RAMB4_S1_S8:%m at simulation time %.3f ns\nA read was performed on address %h (hex) of Port B while a write was requested to the same address on Port A. The write will be successful however the read value on Port B is unknown until the next CLKB cycle.", $time/1000.0, addrb_int); + + end + endtask + + always @(posedge clka_int) begin + if ((output_flag || display_flag)) begin + addra_reg <= addra_int; + ena_reg <= ena_int; + rsta_reg <= rsta_int; + wea_reg <= wea_int; + end + end + + always @(posedge clkb_int) begin + if ((output_flag || display_flag)) begin + addrb_reg <= addrb_int; + enb_reg <= enb_int; + rstb_reg <= rstb_int; + web_reg <= web_int; + end + end + + + // Data + always @(posedge memory_collision) begin + if ((output_flag || display_flag)) begin + for (mi = 0; mi < 8; mi = mi + 1) begin + if ((mem_addra_int) == (mem_addrb_int + mi)) begin + mem[addra_int[11:3]][addra_int[2:0] * 1 +: 1] <= 1'bx; + end + end + memory_collision <= 0; + end + end + + always @(posedge memory_collision_a_b) begin + if ((output_flag || display_flag)) begin + for (mi = 0; mi < 8; mi = mi + 1) begin + if ((mem_addra_reg) == (mem_addrb_int + mi)) begin + mem[addra_reg[11:3]][addra_reg[2:0] * 1 +: 1] <= 1'bx; + end + end + memory_collision_a_b <= 0; + end + end + + always @(posedge memory_collision_b_a) begin + if ((output_flag || display_flag)) begin + for (mi = 0; mi < 8; mi = mi + 1) begin + if ((mem_addra_int) == (mem_addrb_reg + mi)) begin + mem[addra_int[11:3]][addra_int[2:0] * 1 +: 1] <= 1'bx; + end + end + memory_collision_b_a <= 0; + end + end + + always @(posedge data_collision[1]) begin + if (rsta_int == 0 && output_flag) begin + for (ai = 0; ai < 8; ai = ai + 1) begin + if ((mem_addra_int) == (mem_addrb_int + ai)) begin + doa_out <= #100 1'bX; + end + end + end + data_collision[1] <= 0; + end + + always @(posedge data_collision[0]) begin + if (rstb_int == 0 && output_flag) begin + for (bi = 0; bi < 8; bi = bi + 1) begin + if ((mem_addra_int) == (mem_addrb_int + bi)) begin + for (bj = 0; bj < 1; bj = bj + 1) begin + dob_out[bi + bj] <= #100 1'bX; + end + end + end + end + data_collision[0] <= 0; + end + + always @(posedge data_collision_a_b[1]) begin + if (rsta_reg == 0 && output_flag) begin + for (ai = 0; ai < 8; ai = ai + 1) begin + if ((mem_addra_reg) == (mem_addrb_int + ai)) begin + doa_out <= #100 1'bX; + end + end + end + data_collision_a_b[1] <= 0; + end + + always @(posedge data_collision_a_b[0]) begin + if (rstb_int == 0 && output_flag) begin + for (bi = 0; bi < 8; bi = bi + 1) begin + if ((mem_addra_reg) == (mem_addrb_int + bi)) begin + for (bj = 0; bj < 1; bj = bj + 1) begin + dob_out[bi + bj] <= #100 1'bX; + end + end + end + end + data_collision_a_b[0] <= 0; + end + + always @(posedge data_collision_b_a[1]) begin + if (rsta_int == 0 && output_flag) begin + for (ai = 0; ai < 8; ai = ai + 1) begin + if ((mem_addra_int) == (mem_addrb_reg + ai)) begin + doa_out <= #100 1'bX; + end + end + end + data_collision_b_a[1] <= 0; + end + + always @(posedge data_collision_b_a[0]) begin + if (rstb_reg == 0 && output_flag) begin + for (bi = 0; bi < 8; bi = bi + 1) begin + if ((mem_addra_int) == (mem_addrb_reg + bi)) begin + for (bj = 0; bj < 1; bj = bj + 1) begin + dob_out[bi + bj] <= #100 1'bX; + end + end + end + end + data_collision_b_a[0] <= 0; + end + + + // Port A + always @(posedge clka_int) begin + + if (ena_int == 1'b1) begin + + if (rsta_int == 1'b1) begin + doa_out <= #100 0; + end + else begin + if (wea_int == 1'b1) + doa_out <= #100 dia_int; + else + doa_out <= #100 mem[addra_int[11:3]][addra_int[2:0] * 1 +: 1]; + end + + // memory + if (wea_int == 1'b1) begin + mem[addra_int[11:3]][addra_int[2:0] * 1 +: 1] <= dia_int; + end + + end + end + + + // Port B + always @(posedge clkb_int) begin + + if (enb_int == 1'b1) begin + + if (rstb_int == 1'b1) begin + dob_out <= #100 0; + end + else begin + if (web_int == 1'b1) + dob_out <= #100 dib_int; + else + dob_out <= #100 mem[addrb_int]; + end + + // memory + if (web_int == 1'b1) begin + mem[addrb_int] <= dib_int; + end + + end + end + + +endmodule + +`endif diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/RAMB4_S2.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/RAMB4_S2.v new file mode 100644 index 0000000..1f53067 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/RAMB4_S2.v @@ -0,0 +1,284 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/RAMB4_S2.v,v 1.6 2005/03/14 22:54:42 wloo Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2005 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / 4K-Bit Data Single Port Block RAM +// /___/ /\ Filename : RAMB4_S2.v +// \ \ / \ Timestamp : Thu Mar 10 16:43:38 PST 2005 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// End Revision + +`ifdef legacy_model + +`timescale 1 ps / 1 ps + + +module RAMB4_S2 (DO, ADDR, CLK, DI, EN, RST, WE); + + parameter INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + + output [1:0] DO; + reg d0_out, d1_out; + + input [10:0] ADDR; + input [1:0] DI; + input EN, CLK, WE, RST; + + reg [4095:0] mem; + reg [8:0] count; + + wire [10:0] addr_int; + wire [1:0] di_int; + wire en_int, clk_int, we_int, rst_int; + + tri0 GSR = glbl.GSR; + + always @(GSR) + if (GSR) + begin + assign d0_out = 0; + assign d1_out = 0; + end + else + begin + deassign d0_out; + deassign d1_out; + end + + buf b_do_out0 (DO[0], d0_out); + buf b_do_out1 (DO[1], d1_out); + buf b_addr_0 (addr_int[0], ADDR[0]); + buf b_addr_1 (addr_int[1], ADDR[1]); + buf b_addr_2 (addr_int[2], ADDR[2]); + buf b_addr_3 (addr_int[3], ADDR[3]); + buf b_addr_4 (addr_int[4], ADDR[4]); + buf b_addr_5 (addr_int[5], ADDR[5]); + buf b_addr_6 (addr_int[6], ADDR[6]); + buf b_addr_7 (addr_int[7], ADDR[7]); + buf b_addr_8 (addr_int[8], ADDR[8]); + buf b_addr_9 (addr_int[9], ADDR[9]); + buf b_addr_10 (addr_int[10], ADDR[10]); + buf b_di_0 (di_int[0], DI[0]); + buf b_di_1 (di_int[1], DI[1]); + buf b_en (en_int, EN); + buf b_clk (clk_int, CLK); + buf b_we (we_int, WE); + buf b_rst (rst_int, RST); + + initial + begin + for (count = 0; count < 256; count = count + 1) + begin + mem[count] <= INIT_00[count]; + mem[256 * 1 + count] <= INIT_01[count]; + mem[256 * 2 + count] <= INIT_02[count]; + mem[256 * 3 + count] <= INIT_03[count]; + mem[256 * 4 + count] <= INIT_04[count]; + mem[256 * 5 + count] <= INIT_05[count]; + mem[256 * 6 + count] <= INIT_06[count]; + mem[256 * 7 + count] <= INIT_07[count]; + mem[256 * 8 + count] <= INIT_08[count]; + mem[256 * 9 + count] <= INIT_09[count]; + mem[256 * 10 + count] <= INIT_0A[count]; + mem[256 * 11 + count] <= INIT_0B[count]; + mem[256 * 12 + count] <= INIT_0C[count]; + mem[256 * 13 + count] <= INIT_0D[count]; + mem[256 * 14 + count] <= INIT_0E[count]; + mem[256 * 15 + count] <= INIT_0F[count]; + end + end + + always @(posedge clk_int) + begin + if (en_int == 1'b1) + if (rst_int == 1'b1) + begin + d0_out <= 0; + d1_out <= 0; + end + else + if (we_int == 1'b1) + begin + d0_out <= di_int[0]; + d1_out <= di_int[1]; + end + else + begin + d0_out <= mem[addr_int * 2]; + d1_out <= mem[addr_int * 2 + 1]; + end + end + + always @(posedge clk_int) + begin + if (en_int == 1'b1 && we_int == 1'b1) + begin + mem[addr_int * 2] <= di_int[0]; + mem[addr_int * 2 + 1] <= di_int[1]; + end + end + + specify + (CLK *> DO) = (100, 100); + endspecify + +endmodule + +`else + + +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/RAMB4_S2.v,v 1.6 2005/03/14 22:54:42 wloo Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2005 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Timing Simulation Library Component +// / / 16K-Bit Data and 2K-Bit Parity Single Port Block RAM +// /___/ /\ Filename : RAMB4_S2.v +// \ \ / \ Timestamp : Thu Mar 10 16:44:01 PST 2005 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 03/10/05 - Initialized outputs. +// End Revision + +`timescale 1 ps/1 ps + +module RAMB4_S2 (DO, ADDR, CLK, DI, EN, RST, WE); + + parameter INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + + output [1:0] DO; + + input [10:0] ADDR; + input [1:0] DI; + input EN, CLK, WE, RST; + + reg [1:0] do_out = 0; + + reg [1:0] mem [2047:0]; + + reg [8:0] count; + + wire [10:0] addr_int; + wire [1:0] di_int; + wire en_int, clk_int, we_int, rst_int; + + wire di_enable = en_int && we_int; + + tri0 GSR = glbl.GSR; + wire gsr_int; + + buf b_gsr (gsr_int, GSR); + + buf b_do [1:0] (DO, do_out); + buf b_addr [10:0] (addr_int, ADDR); + buf b_di [1:0] (di_int, DI); + buf b_en (en_int, EN); + buf b_clk (clk_int, CLK); + buf b_rst (rst_int, RST); + buf b_we (we_int, WE); + + + always @(gsr_int) + if (gsr_int) begin + assign do_out = 0; + end + else begin + deassign do_out; + end + + + initial begin + + for (count = 0; count < 128; count = count + 1) begin + mem[count] = INIT_00[(count * 2) +: 2]; + mem[128 * 1 + count] = INIT_01[(count * 2) +: 2]; + mem[128 * 2 + count] = INIT_02[(count * 2) +: 2]; + mem[128 * 3 + count] = INIT_03[(count * 2) +: 2]; + mem[128 * 4 + count] = INIT_04[(count * 2) +: 2]; + mem[128 * 5 + count] = INIT_05[(count * 2) +: 2]; + mem[128 * 6 + count] = INIT_06[(count * 2) +: 2]; + mem[128 * 7 + count] = INIT_07[(count * 2) +: 2]; + mem[128 * 8 + count] = INIT_08[(count * 2) +: 2]; + mem[128 * 9 + count] = INIT_09[(count * 2) +: 2]; + mem[128 * 10 + count] = INIT_0A[(count * 2) +: 2]; + mem[128 * 11 + count] = INIT_0B[(count * 2) +: 2]; + mem[128 * 12 + count] = INIT_0C[(count * 2) +: 2]; + mem[128 * 13 + count] = INIT_0D[(count * 2) +: 2]; + mem[128 * 14 + count] = INIT_0E[(count * 2) +: 2]; + mem[128 * 15 + count] = INIT_0F[(count * 2) +: 2]; + end + + end // initial begin + + + always @(posedge clk_int) begin + + if (en_int == 1'b1) begin + + if (rst_int == 1'b1) + do_out <= #100 0; + + else + if (we_int == 1'b1) + do_out <= #100 di_int; + + else + do_out <= #100 mem[addr_int]; + + // memory + if (we_int == 1'b1) + mem[addr_int] <= di_int; + + end + end + + +endmodule + +`endif diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/RAMB4_S2_S16.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/RAMB4_S2_S16.v new file mode 100644 index 0000000..3db5a4f --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/RAMB4_S2_S16.v @@ -0,0 +1,1114 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/RAMB4_S2_S16.v,v 1.9 2007/02/22 01:58:06 wloo Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2005 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / 4K-Bit Data Dual Port Block RAM +// /___/ /\ Filename : RAMB4_S2_S16.v +// \ \ / \ Timestamp : Thu Mar 10 16:43:38 PST 2005 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// End Revision + +`ifdef legacy_model + +`timescale 1 ps / 1 ps + +module RAMB4_S2_S16 (DOA, DOB, ADDRA, ADDRB, CLKA, CLKB, DIA, DIB, ENA, ENB, RSTA, RSTB, WEA, WEB); + + parameter SIM_COLLISION_CHECK = "ALL"; + localparam SETUP_ALL = 100; + + parameter INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + + output [1:0] DOA; + reg [1:0] doa_out; + wire doa_out0, doa_out1; + + input [10:0] ADDRA; + input [1:0] DIA; + input ENA, CLKA, WEA, RSTA; + + output [15:0] DOB; + reg [15:0] dob_out; + wire dob_out0, dob_out1, dob_out2, dob_out3, dob_out4, dob_out5, dob_out6, dob_out7, dob_out8, dob_out9, dob_out10, dob_out11, dob_out12, dob_out13, dob_out14, dob_out15; + + input [7:0] ADDRB; + input [15:0] DIB; + input ENB, CLKB, WEB, RSTB; + + reg [4095:0] mem; + reg [8:0] count; + + reg [5:0] mi, mj, ai, aj, bi, bj, ci, cj, di, dj, ei, ej, fi, fj; + + wire [10:0] addra_int; + reg [10:0] addra_reg; + wire [1:0] dia_int; + wire ena_int, clka_int, wea_int, rsta_int; + reg ena_reg, wea_reg, rsta_reg; + wire [7:0] addrb_int; + reg [7:0] addrb_reg; + wire [15:0] dib_int; + wire enb_int, clkb_int, web_int, rstb_int; + reg enb_reg, web_reg, rstb_reg; + + time time_clka, time_clkb; + time time_clka_clkb; + time time_clkb_clka; + + reg setup_all_a_b; + reg setup_all_b_a; + reg setup_zero; + reg [1:0] data_collision, data_collision_a_b, data_collision_b_a; + reg memory_collision, memory_collision_a_b, memory_collision_b_a; + reg address_collision, address_collision_a_b, address_collision_b_a; + reg change_clka; + reg change_clkb; + + wire [11:0] mem_addra_int; + wire [11:0] mem_addra_reg; + wire [11:0] mem_addrb_int; + wire [11:0] mem_addrb_reg; + + tri0 GSR = glbl.GSR; + + always @(GSR) + if (GSR) begin + assign doa_out = 0; + end + else begin + deassign doa_out; + end + + always @(GSR) + if (GSR) begin + assign dob_out = 0; + end + else begin + deassign dob_out; + end + + buf b_doa_out0 (doa_out0, doa_out[0]); + buf b_doa_out1 (doa_out1, doa_out[1]); + buf b_dob_out0 (dob_out0, dob_out[0]); + buf b_dob_out1 (dob_out1, dob_out[1]); + buf b_dob_out2 (dob_out2, dob_out[2]); + buf b_dob_out3 (dob_out3, dob_out[3]); + buf b_dob_out4 (dob_out4, dob_out[4]); + buf b_dob_out5 (dob_out5, dob_out[5]); + buf b_dob_out6 (dob_out6, dob_out[6]); + buf b_dob_out7 (dob_out7, dob_out[7]); + buf b_dob_out8 (dob_out8, dob_out[8]); + buf b_dob_out9 (dob_out9, dob_out[9]); + buf b_dob_out10 (dob_out10, dob_out[10]); + buf b_dob_out11 (dob_out11, dob_out[11]); + buf b_dob_out12 (dob_out12, dob_out[12]); + buf b_dob_out13 (dob_out13, dob_out[13]); + buf b_dob_out14 (dob_out14, dob_out[14]); + buf b_dob_out15 (dob_out15, dob_out[15]); + buf b_doa0 (DOA[0], doa_out0); + buf b_doa1 (DOA[1], doa_out1); + buf b_dob0 (DOB[0], dob_out0); + buf b_dob1 (DOB[1], dob_out1); + buf b_dob2 (DOB[2], dob_out2); + buf b_dob3 (DOB[3], dob_out3); + buf b_dob4 (DOB[4], dob_out4); + buf b_dob5 (DOB[5], dob_out5); + buf b_dob6 (DOB[6], dob_out6); + buf b_dob7 (DOB[7], dob_out7); + buf b_dob8 (DOB[8], dob_out8); + buf b_dob9 (DOB[9], dob_out9); + buf b_dob10 (DOB[10], dob_out10); + buf b_dob11 (DOB[11], dob_out11); + buf b_dob12 (DOB[12], dob_out12); + buf b_dob13 (DOB[13], dob_out13); + buf b_dob14 (DOB[14], dob_out14); + buf b_dob15 (DOB[15], dob_out15); + buf b_addra_0 (addra_int[0], ADDRA[0]); + buf b_addra_1 (addra_int[1], ADDRA[1]); + buf b_addra_2 (addra_int[2], ADDRA[2]); + buf b_addra_3 (addra_int[3], ADDRA[3]); + buf b_addra_4 (addra_int[4], ADDRA[4]); + buf b_addra_5 (addra_int[5], ADDRA[5]); + buf b_addra_6 (addra_int[6], ADDRA[6]); + buf b_addra_7 (addra_int[7], ADDRA[7]); + buf b_addra_8 (addra_int[8], ADDRA[8]); + buf b_addra_9 (addra_int[9], ADDRA[9]); + buf b_addra_10 (addra_int[10], ADDRA[10]); + buf b_dia_0 (dia_int[0], DIA[0]); + buf b_dia_1 (dia_int[1], DIA[1]); + buf b_clka (clka_int, CLKA); + buf b_ena (ena_int, ENA); + buf b_rsta (rsta_int, RSTA); + buf b_wea (wea_int, WEA); + buf b_addrb_0 (addrb_int[0], ADDRB[0]); + buf b_addrb_1 (addrb_int[1], ADDRB[1]); + buf b_addrb_2 (addrb_int[2], ADDRB[2]); + buf b_addrb_3 (addrb_int[3], ADDRB[3]); + buf b_addrb_4 (addrb_int[4], ADDRB[4]); + buf b_addrb_5 (addrb_int[5], ADDRB[5]); + buf b_addrb_6 (addrb_int[6], ADDRB[6]); + buf b_addrb_7 (addrb_int[7], ADDRB[7]); + buf b_dib_0 (dib_int[0], DIB[0]); + buf b_dib_1 (dib_int[1], DIB[1]); + buf b_dib_2 (dib_int[2], DIB[2]); + buf b_dib_3 (dib_int[3], DIB[3]); + buf b_dib_4 (dib_int[4], DIB[4]); + buf b_dib_5 (dib_int[5], DIB[5]); + buf b_dib_6 (dib_int[6], DIB[6]); + buf b_dib_7 (dib_int[7], DIB[7]); + buf b_dib_8 (dib_int[8], DIB[8]); + buf b_dib_9 (dib_int[9], DIB[9]); + buf b_dib_10 (dib_int[10], DIB[10]); + buf b_dib_11 (dib_int[11], DIB[11]); + buf b_dib_12 (dib_int[12], DIB[12]); + buf b_dib_13 (dib_int[13], DIB[13]); + buf b_dib_14 (dib_int[14], DIB[14]); + buf b_dib_15 (dib_int[15], DIB[15]); + buf b_clkb (clkb_int, CLKB); + buf b_enb (enb_int, ENB); + buf b_rstb (rstb_int, RSTB); + buf b_web (web_int, WEB); + + initial begin + for (count = 0; count < 256; count = count + 1) begin + mem[count] <= INIT_00[count]; + mem[256 * 1 + count] <= INIT_01[count]; + mem[256 * 2 + count] <= INIT_02[count]; + mem[256 * 3 + count] <= INIT_03[count]; + mem[256 * 4 + count] <= INIT_04[count]; + mem[256 * 5 + count] <= INIT_05[count]; + mem[256 * 6 + count] <= INIT_06[count]; + mem[256 * 7 + count] <= INIT_07[count]; + mem[256 * 8 + count] <= INIT_08[count]; + mem[256 * 9 + count] <= INIT_09[count]; + mem[256 * 10 + count] <= INIT_0A[count]; + mem[256 * 11 + count] <= INIT_0B[count]; + mem[256 * 12 + count] <= INIT_0C[count]; + mem[256 * 13 + count] <= INIT_0D[count]; + mem[256 * 14 + count] <= INIT_0E[count]; + mem[256 * 15 + count] <= INIT_0F[count]; + end + address_collision <= 0; + address_collision_a_b <= 0; + address_collision_b_a <= 0; + change_clka <= 0; + change_clkb <= 0; + data_collision <= 0; + data_collision_a_b <= 0; + data_collision_b_a <= 0; + memory_collision <= 0; + memory_collision_a_b <= 0; + memory_collision_b_a <= 0; + setup_all_a_b <= 0; + setup_all_b_a <= 0; + setup_zero <= 0; + end + + assign mem_addra_int = addra_int * 2; + assign mem_addra_reg = addra_reg * 2; + assign mem_addrb_int = addrb_int * 16; + assign mem_addrb_reg = addrb_reg * 16; + + + initial begin + + case (SIM_COLLISION_CHECK) + + "NONE" : begin + assign setup_all_a_b = 1'b0; + assign setup_all_b_a = 1'b0; + assign setup_zero = 1'b0; + assign address_collision = 1'b0; + assign address_collision_a_b = 1'b0; + assign address_collision_b_a = 1'b0; + end + "WARNING_ONLY" : begin + assign data_collision = 2'b00; + assign data_collision_a_b = 2'b00; + assign data_collision_b_a = 2'b00; + assign memory_collision = 1'b0; + assign memory_collision_a_b = 1'b0; + assign memory_collision_b_a = 1'b0; + end + "GENERATE_X_ONLY" : begin + assign address_collision = 1'b0; + assign address_collision_a_b = 1'b0; + assign address_collision_b_a = 1'b0; + end + "ALL" : ; + default : begin + $display("Attribute Syntax Error : The Attribute SIM_COLLISION_CHECK on RAMB4_S2_S16 instance %m is set to %s. Legal values for this attribute are ALL, NONE, WARNING_ONLY or GENERATE_X_ONLY.", SIM_COLLISION_CHECK); + $finish; + end + + endcase // case(SIM_COLLISION_CHECK) + + end // initial begin + + + always @(posedge clka_int) begin + time_clka = $time; + #0 time_clkb_clka = time_clka - time_clkb; + change_clka = ~change_clka; + end + + always @(posedge clkb_int) begin + time_clkb = $time; + #0 time_clka_clkb = time_clkb - time_clka; + change_clkb = ~change_clkb; + end + + always @(change_clkb) begin + if ((0 < time_clka_clkb) && (time_clka_clkb < SETUP_ALL)) + setup_all_a_b = 1; + end + + always @(change_clka) begin + if ((0 < time_clkb_clka) && (time_clkb_clka < SETUP_ALL)) + setup_all_b_a = 1; + end + + always @(change_clkb or change_clka) begin + if ((time_clkb_clka == 0) && (time_clka_clkb == 0)) + setup_zero = 1; + end + + always @(posedge setup_zero) begin + if ((ena_int == 1) && (wea_int == 1) && + (enb_int == 1) && (web_int == 1)) + memory_collision <= 1; + end + + always @(posedge setup_all_a_b) begin + if ((ena_reg == 1) && (enb_int == 1)) begin + case ({wea_reg, web_int}) + 6'b11 : begin data_collision_a_b <= 2'b11; display_all_a_b; end + 6'b01 : begin data_collision_a_b <= 2'b10; display_all_a_b; end + 6'b10 : begin data_collision_a_b <= 2'b01; display_all_a_b; end + endcase + end + setup_all_a_b <= 0; + end + + task display_all_a_b; + begin + address_collision_a_b = 1'b0; + for (ci = 0; ci < 16; ci = ci + 2) begin + if ((mem_addra_reg) == (mem_addrb_int + ci)) begin + address_collision_a_b = 1'b1; + end + end + if (address_collision_a_b == 1'b1) + + if (({wea_reg, web_int}) == 2'b11) + $display("Memory Collision Error on RAMB4_S2_S16:%m at simulation time %.3f ns\nA write was requested to the same address simultaneously at both Port A and Port B of the RAM. The contents written to the RAM at address location %h (hex) of Port A and address location %h (hex) of Port B are unknown.", $time/1000.0, addra_int, addrb_int); + + else if (({wea_reg, web_int}) == 2'b01) + $display("Memory Collision Error on RAMB4_S2_S16:%m at simulation time %.3f ns\nA read was performed on address %h (hex) of Port A while a write was requested to the same address on Port B. The write will be successful however the read value on Port A is unknown until the next CLKA cycle.", $time/1000.0, addra_int); + + else if (({wea_reg, web_int}) == 2'b10) + $display("Memory Collision Error on RAMB4_S2_S16:%m at simulation time %.3f ns\nA read was performed on address %h (hex) of Port B while a write was requested to the same address on Port A. The write will be successful however the read value on Port B is unknown until the next CLKB cycle.", $time/1000.0, addrb_int); + + end + endtask + + always @(posedge setup_all_b_a) begin + if ((ena_int == 1) && (enb_reg == 1)) begin + case ({wea_int, web_reg}) + 6'b11 : begin data_collision_b_a <= 2'b11; display_all_b_a; end + 6'b01 : begin data_collision_b_a <= 2'b10; display_all_b_a; end + 6'b10 : begin data_collision_b_a <= 2'b01; display_all_b_a; end + endcase + end + setup_all_b_a <= 0; + end + + task display_all_b_a; + begin + address_collision_b_a = 1'b0; + for (ci = 0; ci < 16; ci = ci + 2) begin + if ((mem_addra_int) == (mem_addrb_reg + ci)) begin + address_collision_b_a = 1'b1; + end + end + if (address_collision_b_a == 1'b1) + + if (({wea_int, web_reg}) == 2'b11) + $display("Memory Collision Error on RAMB4_S2_S16:%m at simulation time %.3f ns\nA write was requested to the same address simultaneously at both Port A and Port B of the RAM. The contents written to the RAM at address location %h (hex) of Port A and address location %h (hex) of Port B are unknown.", $time/1000.0, addra_int, addrb_int); + + else if (({wea_int, web_reg}) == 2'b01) + $display("Memory Collision Error on RAMB4_S2_S16:%m at simulation time %.3f ns\nA read was performed on address %h (hex) of Port A while a write was requested to the same address on Port B. The write will be successful however the read value on Port A is unknown until the next CLKA cycle.", $time/1000.0, addra_int); + + else if (({wea_int, web_reg}) == 2'b10) + $display("Memory Collision Error on RAMB4_S2_S16:%m at simulation time %.3f ns\nA read was performed on address %h (hex) of Port B while a write was requested to the same address on Port A. The write will be successful however the read value on Port B is unknown until the next CLKB cycle.", $time/1000.0, addrb_int); + + end + endtask + + always @(posedge setup_zero) begin + if ((ena_int == 1) && (enb_int == 1)) begin + case ({wea_int, web_int}) + 6'b11 : begin data_collision <= 2'b11; display_zero; end + 6'b01 : begin data_collision <= 2'b10; display_zero; end + 6'b10 : begin data_collision <= 2'b01; display_zero; end + endcase + end + setup_zero <= 0; + end + + task display_zero; + begin + address_collision = 1'b0; + for (ci = 0; ci < 16; ci = ci + 2) begin + if ((mem_addra_int) == (mem_addrb_int + ci)) begin + address_collision = 1'b1; + end + end + if (address_collision == 1'b1) + + if (({wea_int, web_int}) == 2'b11) + $display("Memory Collision Error on RAMB4_S2_S16:%m at simulation time %.3f ns\nA write was requested to the same address simultaneously at both Port A and Port B of the RAM. The contents written to the RAM at address location %h (hex) of Port A and address location %h (hex) of Port B are unknown.", $time/1000.0, addra_int, addrb_int); + + else if (({wea_int, web_int}) == 2'b01) + $display("Memory Collision Error on RAMB4_S2_S16:%m at simulation time %.3f ns\nA read was performed on address %h (hex) of Port A while a write was requested to the same address on Port B. The write will be successful however the read value on Port A is unknown until the next CLKA cycle.", $time/1000.0, addra_int); + + else if (({wea_int, web_int}) == 2'b10) + $display("Memory Collision Error on RAMB4_S2_S16:%m at simulation time %.3f ns\nA read was performed on address %h (hex) of Port B while a write was requested to the same address on Port A. The write will be successful however the read value on Port B is unknown until the next CLKB cycle.", $time/1000.0, addrb_int); + + end + endtask + + always @(posedge clka_int) begin + addra_reg <= addra_int; + ena_reg <= ena_int; + rsta_reg <= rsta_int; + wea_reg <= wea_int; + end + + always @(posedge clkb_int) begin + addrb_reg <= addrb_int; + enb_reg <= enb_int; + rstb_reg <= rstb_int; + web_reg <= web_int; + end + + // Data + always @(posedge memory_collision) begin + for (mi = 0; mi < 16; mi = mi + 2) begin + if ((mem_addra_int) == (mem_addrb_int + mi)) begin + for (mj = 0; mj < 2; mj = mj + 1) begin + mem[mem_addrb_int + mi + mj] <= 1'bX; + end + end + end + memory_collision <= 0; + end + + always @(posedge memory_collision_a_b) begin + for (mi = 0; mi < 16; mi = mi + 2) begin + if ((mem_addra_reg) == (mem_addrb_int + mi)) begin + for (mj = 0; mj < 2; mj = mj + 1) begin + mem[mem_addrb_int + mi + mj] <= 1'bX; + end + end + end + memory_collision_a_b <= 0; + end + + always @(posedge memory_collision_b_a) begin + for (mi = 0; mi < 16; mi = mi + 2) begin + if ((mem_addra_int) == (mem_addrb_reg + mi)) begin + for (mj = 0; mj < 2; mj = mj + 1) begin + mem[mem_addrb_reg + mi + mj] <= 1'bX; + end + end + end + memory_collision_b_a <= 0; + end + + always @(posedge data_collision[1]) begin + if (rsta_int == 0) begin + for (ai = 0; ai < 16; ai = ai + 2) begin + if ((mem_addra_int) == (mem_addrb_int + ai)) begin + doa_out <= 2'bX; + end + end + end + data_collision[1] <= 0; + end + + always @(posedge data_collision[0]) begin + if (rstb_int == 0) begin + for (bi = 0; bi < 16; bi = bi + 2) begin + if ((mem_addra_int) == (mem_addrb_int + bi)) begin + for (bj = 0; bj < 2; bj = bj + 1) begin + dob_out[bi + bj] <= 1'bX; + end + end + end + end + data_collision[0] <= 0; + end + + always @(posedge data_collision_a_b[1]) begin + if (rsta_reg == 0) begin + for (ai = 0; ai < 16; ai = ai + 2) begin + if ((mem_addra_reg) == (mem_addrb_int + ai)) begin + doa_out <= 2'bX; + end + end + end + data_collision_a_b[1] <= 0; + end + + always @(posedge data_collision_a_b[0]) begin + if (rstb_int == 0) begin + for (bi = 0; bi < 16; bi = bi + 2) begin + if ((mem_addra_reg) == (mem_addrb_int + bi)) begin + for (bj = 0; bj < 2; bj = bj + 1) begin + dob_out[bi + bj] <= 1'bX; + end + end + end + end + data_collision_a_b[0] <= 0; + end + + always @(posedge data_collision_b_a[1]) begin + if (rsta_int == 0) begin + for (ai = 0; ai < 16; ai = ai + 2) begin + if ((mem_addra_int) == (mem_addrb_reg + ai)) begin + doa_out <= 2'bX; + end + end + end + data_collision_b_a[1] <= 0; + end + + always @(posedge data_collision_b_a[0]) begin + if (rstb_reg == 0) begin + for (bi = 0; bi < 16; bi = bi + 2) begin + if ((mem_addra_int) == (mem_addrb_reg + bi)) begin + for (bj = 0; bj < 2; bj = bj + 1) begin + dob_out[bi + bj] <= 1'bX; + end + end + end + end + data_collision_b_a[0] <= 0; + end + + + always @(posedge clka_int) begin + if (ena_int == 1'b1) begin + if (rsta_int == 1'b1) begin + doa_out <= 2'b0; + end + else if (wea_int == 0) begin + doa_out[0] <= mem[mem_addra_int + 0]; + doa_out[1] <= mem[mem_addra_int + 1]; + end + else begin + doa_out <= dia_int; + end + end + end + + always @(posedge clka_int) begin + if (ena_int == 1'b1 && wea_int == 1'b1) begin + mem[mem_addra_int + 0] <= dia_int[0]; + mem[mem_addra_int + 1] <= dia_int[1]; + end + end + + always @(posedge clkb_int) begin + if (enb_int == 1'b1) begin + if (rstb_int == 1'b1) begin + dob_out <= 16'b0; + end + else if (web_int == 0) begin + dob_out[0] <= mem[mem_addrb_int + 0]; + dob_out[1] <= mem[mem_addrb_int + 1]; + dob_out[2] <= mem[mem_addrb_int + 2]; + dob_out[3] <= mem[mem_addrb_int + 3]; + dob_out[4] <= mem[mem_addrb_int + 4]; + dob_out[5] <= mem[mem_addrb_int + 5]; + dob_out[6] <= mem[mem_addrb_int + 6]; + dob_out[7] <= mem[mem_addrb_int + 7]; + dob_out[8] <= mem[mem_addrb_int + 8]; + dob_out[9] <= mem[mem_addrb_int + 9]; + dob_out[10] <= mem[mem_addrb_int + 10]; + dob_out[11] <= mem[mem_addrb_int + 11]; + dob_out[12] <= mem[mem_addrb_int + 12]; + dob_out[13] <= mem[mem_addrb_int + 13]; + dob_out[14] <= mem[mem_addrb_int + 14]; + dob_out[15] <= mem[mem_addrb_int + 15]; + end + else begin + dob_out <= dib_int; + end + end + end + + always @(posedge clkb_int) begin + if (enb_int == 1'b1 && web_int == 1'b1) begin + mem[mem_addrb_int + 0] <= dib_int[0]; + mem[mem_addrb_int + 1] <= dib_int[1]; + mem[mem_addrb_int + 2] <= dib_int[2]; + mem[mem_addrb_int + 3] <= dib_int[3]; + mem[mem_addrb_int + 4] <= dib_int[4]; + mem[mem_addrb_int + 5] <= dib_int[5]; + mem[mem_addrb_int + 6] <= dib_int[6]; + mem[mem_addrb_int + 7] <= dib_int[7]; + mem[mem_addrb_int + 8] <= dib_int[8]; + mem[mem_addrb_int + 9] <= dib_int[9]; + mem[mem_addrb_int + 10] <= dib_int[10]; + mem[mem_addrb_int + 11] <= dib_int[11]; + mem[mem_addrb_int + 12] <= dib_int[12]; + mem[mem_addrb_int + 13] <= dib_int[13]; + mem[mem_addrb_int + 14] <= dib_int[14]; + mem[mem_addrb_int + 15] <= dib_int[15]; + end + end + + specify + (CLKA *> DOA) = (100, 100); + (CLKB *> DOB) = (100, 100); + endspecify + +endmodule + +`else + +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/RAMB4_S2_S16.v,v 1.9 2007/02/22 01:58:06 wloo Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2005 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Timing Simulation Library Component +// / / 16K-Bit Data and 2K-Bit Parity Dual Port Block RAM +// /___/ /\ Filename : RAMB4_S2_S16.v +// \ \ / \ Timestamp : Thu Mar 10 16:44:01 PST 2005 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 03/10/05 - Initialized outputs. +// 02/21/07 - Fixed parameter SIM_COLLISION_CHECK (CR 433281). +// End Revision + +`timescale 1 ps/1 ps + +module RAMB4_S2_S16 (DOA, DOB, ADDRA, ADDRB, CLKA, CLKB, DIA, DIB, ENA, ENB, RSTA, RSTB, WEA, WEB); + + parameter SIM_COLLISION_CHECK = "ALL"; + localparam SETUP_ALL = 100; + + parameter INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + + output [1:0] DOA; + output [15:0] DOB; + + input [10:0] ADDRA; + input [1:0] DIA; + input ENA, CLKA, WEA, RSTA; + input [7:0] ADDRB; + input [15:0] DIB; + input ENB, CLKB, WEB, RSTB; + + reg [1:0] doa_out = 0; + reg [15:0] dob_out = 0; + + reg [15:0] mem [255:0]; + + reg [8:0] count; + + reg [5:0] mi, ai, bi, bj, ci; + + wire [10:0] addra_int; + reg [10:0] addra_reg; + wire [1:0] dia_int; + wire ena_int, clka_int, wea_int, rsta_int; + reg ena_reg, wea_reg, rsta_reg; + wire [7:0] addrb_int; + reg [7:0] addrb_reg; + wire [15:0] dib_int; + wire enb_int, clkb_int, web_int, rstb_int; + reg display_flag, output_flag; + reg enb_reg, web_reg, rstb_reg; + + time time_clka, time_clkb; + time time_clka_clkb; + time time_clkb_clka; + + reg setup_all_a_b; + reg setup_all_b_a; + reg setup_zero; + reg [1:0] data_collision, data_collision_a_b, data_collision_b_a; + reg memory_collision, memory_collision_a_b, memory_collision_b_a; + reg address_collision, address_collision_a_b, address_collision_b_a; + reg change_clka; + reg change_clkb; + + wire [11:0] mem_addra_int; + wire [11:0] mem_addra_reg; + wire [11:0] mem_addrb_int; + wire [11:0] mem_addrb_reg; + + wire dia_enable = ena_int && wea_int; + wire dib_enable = enb_int && web_int; + + tri0 GSR = glbl.GSR; + wire gsr_int; + + buf b_gsr (gsr_int, GSR); + + buf b_doa [1:0] (DOA, doa_out); + buf b_addra [10:0] (addra_int, ADDRA); + buf b_dia [1:0] (dia_int, DIA); + buf b_ena (ena_int, ENA); + buf b_clka (clka_int, CLKA); + buf b_rsta (rsta_int, RSTA); + buf b_wea (wea_int, WEA); + + buf b_dob [15:0] (DOB, dob_out); + buf b_addrb [7:0] (addrb_int, ADDRB); + buf b_dib [15:0] (dib_int, DIB); + buf b_enb (enb_int, ENB); + buf b_clkb (clkb_int, CLKB); + buf b_rstb (rstb_int, RSTB); + buf b_web (web_int, WEB); + + + always @(gsr_int) + if (gsr_int) begin + assign doa_out = 0; + assign dob_out = 0; + end + else begin + deassign doa_out; + deassign dob_out; + end + + + initial begin + + for (count = 0; count < 16; count = count + 1) begin + mem[count] = INIT_00[(count * 16) +: 16]; + mem[16 * 1 + count] = INIT_01[(count * 16) +: 16]; + mem[16 * 2 + count] = INIT_02[(count * 16) +: 16]; + mem[16 * 3 + count] = INIT_03[(count * 16) +: 16]; + mem[16 * 4 + count] = INIT_04[(count * 16) +: 16]; + mem[16 * 5 + count] = INIT_05[(count * 16) +: 16]; + mem[16 * 6 + count] = INIT_06[(count * 16) +: 16]; + mem[16 * 7 + count] = INIT_07[(count * 16) +: 16]; + mem[16 * 8 + count] = INIT_08[(count * 16) +: 16]; + mem[16 * 9 + count] = INIT_09[(count * 16) +: 16]; + mem[16 * 10 + count] = INIT_0A[(count * 16) +: 16]; + mem[16 * 11 + count] = INIT_0B[(count * 16) +: 16]; + mem[16 * 12 + count] = INIT_0C[(count * 16) +: 16]; + mem[16 * 13 + count] = INIT_0D[(count * 16) +: 16]; + mem[16 * 14 + count] = INIT_0E[(count * 16) +: 16]; + mem[16 * 15 + count] = INIT_0F[(count * 16) +: 16]; + end + + change_clka <= 0; + change_clkb <= 0; + data_collision <= 0; + data_collision_a_b <= 0; + data_collision_b_a <= 0; + memory_collision <= 0; + memory_collision_a_b <= 0; + memory_collision_b_a <= 0; + setup_all_a_b <= 0; + setup_all_b_a <= 0; + setup_zero <= 0; + end + + assign mem_addra_int = addra_int * 2; + assign mem_addra_reg = addra_reg * 2; + assign mem_addrb_int = addrb_int * 16; + assign mem_addrb_reg = addrb_reg * 16; + + + initial begin + + display_flag = 1; + output_flag = 1; + + case (SIM_COLLISION_CHECK) + + "NONE" : begin + output_flag = 0; + display_flag = 0; + end + "WARNING_ONLY" : output_flag = 0; + "GENERATE_X_ONLY" : display_flag = 0; + "ALL" : ; + + default : begin + $display("Attribute Syntax Error : The Attribute SIM_COLLISION_CHECK on RAMB4_S2_S16 instance %m is set to %s. Legal values for this attribute are ALL, NONE, WARNING_ONLY or GENERATE_X_ONLY.", SIM_COLLISION_CHECK); + $finish; + end + + endcase // case(SIM_COLLISION_CHECK) + + end // initial begin + + + always @(posedge clka_int) begin + if ((output_flag || display_flag)) begin + time_clka = $time; + #0 time_clkb_clka = time_clka - time_clkb; + change_clka = ~change_clka; + end + end + + always @(posedge clkb_int) begin + if ((output_flag || display_flag)) begin + time_clkb = $time; + #0 time_clka_clkb = time_clkb - time_clka; + change_clkb = ~change_clkb; + end + end + + always @(change_clkb) begin + if ((0 < time_clka_clkb) && (time_clka_clkb < SETUP_ALL)) + setup_all_a_b = 1; + end + + always @(change_clka) begin + if ((0 < time_clkb_clka) && (time_clkb_clka < SETUP_ALL)) + setup_all_b_a = 1; + end + + always @(change_clkb or change_clka) begin + if ((time_clkb_clka == 0) && (time_clka_clkb == 0)) + setup_zero = 1; + end + + always @(posedge setup_zero) begin + if ((ena_int == 1) && (wea_int == 1) && + (enb_int == 1) && (web_int == 1)) + memory_collision <= 1; + end + + always @(posedge setup_all_a_b) begin + if ((ena_reg == 1) && (enb_int == 1)) begin + case ({wea_reg, web_int}) + 6'b11 : begin data_collision_a_b <= 2'b11; display_all_a_b; end + 6'b01 : begin data_collision_a_b <= 2'b10; display_all_a_b; end + 6'b10 : begin data_collision_a_b <= 2'b01; display_all_a_b; end + endcase + end + setup_all_a_b <= 0; + end + + task display_all_a_b; + begin + address_collision_a_b = 1'b0; + for (ci = 0; ci < 16; ci = ci + 2) begin + if ((mem_addra_reg) == (mem_addrb_int + ci)) begin + address_collision_a_b = 1'b1; + end + end + if (address_collision_a_b == 1'b1 && display_flag) + + if (({wea_reg, web_int}) == 2'b11) + $display("Memory Collision Error on RAMB4_S2_S16:%m at simulation time %.3f ns\nA write was requested to the same address simultaneously at both Port A and Port B of the RAM. The contents written to the RAM at address location %h (hex) of Port A and address location %h (hex) of Port B are unknown.", $time/1000.0, addra_int, addrb_int); + + else if (({wea_reg, web_int}) == 2'b01) + $display("Memory Collision Error on RAMB4_S2_S16:%m at simulation time %.3f ns\nA read was performed on address %h (hex) of Port A while a write was requested to the same address on Port B. The write will be successful however the read value on Port A is unknown until the next CLKA cycle.", $time/1000.0, addra_int); + + else if (({wea_reg, web_int}) == 2'b10) + $display("Memory Collision Error on RAMB4_S2_S16:%m at simulation time %.3f ns\nA read was performed on address %h (hex) of Port B while a write was requested to the same address on Port A. The write will be successful however the read value on Port B is unknown until the next CLKB cycle.", $time/1000.0, addrb_int); + + end + endtask + + always @(posedge setup_all_b_a) begin + if ((ena_int == 1) && (enb_reg == 1)) begin + case ({wea_int, web_reg}) + 6'b11 : begin data_collision_b_a <= 2'b11; display_all_b_a; end + 6'b01 : begin data_collision_b_a <= 2'b10; display_all_b_a; end + 6'b10 : begin data_collision_b_a <= 2'b01; display_all_b_a; end + endcase + end + setup_all_b_a <= 0; + end + + task display_all_b_a; + begin + address_collision_b_a = 1'b0; + for (ci = 0; ci < 16; ci = ci + 2) begin + if ((mem_addra_int) == (mem_addrb_reg + ci)) begin + address_collision_b_a = 1'b1; + end + end + if (address_collision_b_a == 1'b1 && display_flag) + + if (({wea_int, web_reg}) == 2'b11) + $display("Memory Collision Error on RAMB4_S2_S16:%m at simulation time %.3f ns\nA write was requested to the same address simultaneously at both Port A and Port B of the RAM. The contents written to the RAM at address location %h (hex) of Port A and address location %h (hex) of Port B are unknown.", $time/1000.0, addra_int, addrb_int); + + else if (({wea_int, web_reg}) == 2'b01) + $display("Memory Collision Error on RAMB4_S2_S16:%m at simulation time %.3f ns\nA read was performed on address %h (hex) of Port A while a write was requested to the same address on Port B. The write will be successful however the read value on Port A is unknown until the next CLKA cycle.", $time/1000.0, addra_int); + + else if (({wea_int, web_reg}) == 2'b10) + $display("Memory Collision Error on RAMB4_S2_S16:%m at simulation time %.3f ns\nA read was performed on address %h (hex) of Port B while a write was requested to the same address on Port A. The write will be successful however the read value on Port B is unknown until the next CLKB cycle.", $time/1000.0, addrb_int); + + end + endtask + + always @(posedge setup_zero) begin + if ((ena_int == 1) && (enb_int == 1)) begin + case ({wea_int, web_int}) + 6'b11 : begin data_collision <= 2'b11; display_zero; end + 6'b01 : begin data_collision <= 2'b10; display_zero; end + 6'b10 : begin data_collision <= 2'b01; display_zero; end + endcase + end + setup_zero <= 0; + end + + task display_zero; + begin + address_collision = 1'b0; + for (ci = 0; ci < 16; ci = ci + 2) begin + if ((mem_addra_int) == (mem_addrb_int + ci)) begin + address_collision = 1'b1; + end + end + if (address_collision == 1'b1 && display_flag) + + if (({wea_int, web_int}) == 2'b11) + $display("Memory Collision Error on RAMB4_S2_S16:%m at simulation time %.3f ns\nA write was requested to the same address simultaneously at both Port A and Port B of the RAM. The contents written to the RAM at address location %h (hex) of Port A and address location %h (hex) of Port B are unknown.", $time/1000.0, addra_int, addrb_int); + + else if (({wea_int, web_int}) == 2'b01) + $display("Memory Collision Error on RAMB4_S2_S16:%m at simulation time %.3f ns\nA read was performed on address %h (hex) of Port A while a write was requested to the same address on Port B. The write will be successful however the read value on Port A is unknown until the next CLKA cycle.", $time/1000.0, addra_int); + + else if (({wea_int, web_int}) == 2'b10) + $display("Memory Collision Error on RAMB4_S2_S16:%m at simulation time %.3f ns\nA read was performed on address %h (hex) of Port B while a write was requested to the same address on Port A. The write will be successful however the read value on Port B is unknown until the next CLKB cycle.", $time/1000.0, addrb_int); + + end + endtask + + always @(posedge clka_int) begin + if ((output_flag || display_flag)) begin + addra_reg <= addra_int; + ena_reg <= ena_int; + rsta_reg <= rsta_int; + wea_reg <= wea_int; + end + end + + always @(posedge clkb_int) begin + if ((output_flag || display_flag)) begin + addrb_reg <= addrb_int; + enb_reg <= enb_int; + rstb_reg <= rstb_int; + web_reg <= web_int; + end + end + + + // Data + always @(posedge memory_collision) begin + if ((output_flag || display_flag)) begin + for (mi = 0; mi < 16; mi = mi + 2) begin + if ((mem_addra_int) == (mem_addrb_int + mi)) begin + mem[addra_int[10:3]][addra_int[2:0] * 2 +: 2] <= 2'bx; + end + end + memory_collision <= 0; + end + end + + always @(posedge memory_collision_a_b) begin + if ((output_flag || display_flag)) begin + for (mi = 0; mi < 16; mi = mi + 2) begin + if ((mem_addra_reg) == (mem_addrb_int + mi)) begin + mem[addra_reg[10:3]][addra_reg[2:0] * 2 +: 2] <= 2'bx; + end + end + memory_collision_a_b <= 0; + end + end + + always @(posedge memory_collision_b_a) begin + if ((output_flag || display_flag)) begin + for (mi = 0; mi < 16; mi = mi + 2) begin + if ((mem_addra_int) == (mem_addrb_reg + mi)) begin + mem[addra_int[10:3]][addra_int[2:0] * 2 +: 2] <= 2'bx; + end + end + memory_collision_b_a <= 0; + end + end + + always @(posedge data_collision[1]) begin + if (rsta_int == 0 && output_flag) begin + for (ai = 0; ai < 16; ai = ai + 2) begin + if ((mem_addra_int) == (mem_addrb_int + ai)) begin + doa_out <= #100 2'bX; + end + end + end + data_collision[1] <= 0; + end + + always @(posedge data_collision[0]) begin + if (rstb_int == 0 && output_flag) begin + for (bi = 0; bi < 16; bi = bi + 2) begin + if ((mem_addra_int) == (mem_addrb_int + bi)) begin + for (bj = 0; bj < 2; bj = bj + 1) begin + dob_out[bi + bj] <= #100 1'bX; + end + end + end + end + data_collision[0] <= 0; + end + + always @(posedge data_collision_a_b[1]) begin + if (rsta_reg == 0 && output_flag) begin + for (ai = 0; ai < 16; ai = ai + 2) begin + if ((mem_addra_reg) == (mem_addrb_int + ai)) begin + doa_out <= #100 2'bX; + end + end + end + data_collision_a_b[1] <= 0; + end + + always @(posedge data_collision_a_b[0]) begin + if (rstb_int == 0 && output_flag) begin + for (bi = 0; bi < 16; bi = bi + 2) begin + if ((mem_addra_reg) == (mem_addrb_int + bi)) begin + for (bj = 0; bj < 2; bj = bj + 1) begin + dob_out[bi + bj] <= #100 1'bX; + end + end + end + end + data_collision_a_b[0] <= 0; + end + + always @(posedge data_collision_b_a[1]) begin + if (rsta_int == 0 && output_flag) begin + for (ai = 0; ai < 16; ai = ai + 2) begin + if ((mem_addra_int) == (mem_addrb_reg + ai)) begin + doa_out <= #100 2'bX; + end + end + end + data_collision_b_a[1] <= 0; + end + + always @(posedge data_collision_b_a[0]) begin + if (rstb_reg == 0 && output_flag) begin + for (bi = 0; bi < 16; bi = bi + 2) begin + if ((mem_addra_int) == (mem_addrb_reg + bi)) begin + for (bj = 0; bj < 2; bj = bj + 1) begin + dob_out[bi + bj] <= #100 1'bX; + end + end + end + end + data_collision_b_a[0] <= 0; + end + + + // Port A + always @(posedge clka_int) begin + + if (ena_int == 1'b1) begin + + if (rsta_int == 1'b1) begin + doa_out <= #100 0; + end + else begin + if (wea_int == 1'b1) + doa_out <= #100 dia_int; + else + doa_out <= #100 mem[addra_int[10:3]][addra_int[2:0] * 2 +: 2]; + end + + // memory + if (wea_int == 1'b1) begin + mem[addra_int[10:3]][addra_int[2:0] * 2 +: 2] <= dia_int; + end + + end + end + + + // Port B + always @(posedge clkb_int) begin + + if (enb_int == 1'b1) begin + + if (rstb_int == 1'b1) begin + dob_out <= #100 0; + end + else begin + if (web_int == 1'b1) + dob_out <= #100 dib_int; + else + dob_out <= #100 mem[addrb_int]; + end + + // memory + if (web_int == 1'b1) begin + mem[addrb_int] <= dib_int; + end + + end + end + + +endmodule + +`endif diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/RAMB4_S2_S2.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/RAMB4_S2_S2.v new file mode 100644 index 0000000..69c080f --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/RAMB4_S2_S2.v @@ -0,0 +1,1047 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/RAMB4_S2_S2.v,v 1.9 2007/02/22 01:58:06 wloo Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2005 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / 4K-Bit Data Dual Port Block RAM +// /___/ /\ Filename : RAMB4_S2_S2.v +// \ \ / \ Timestamp : Thu Mar 10 16:43:38 PST 2005 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// End Revision + +`ifdef legacy_model + +`timescale 1 ps / 1 ps + +module RAMB4_S2_S2 (DOA, DOB, ADDRA, ADDRB, CLKA, CLKB, DIA, DIB, ENA, ENB, RSTA, RSTB, WEA, WEB); + + parameter SIM_COLLISION_CHECK = "ALL"; + localparam SETUP_ALL = 100; + + parameter INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + + output [1:0] DOA; + reg [1:0] doa_out; + wire doa_out0, doa_out1; + + input [10:0] ADDRA; + input [1:0] DIA; + input ENA, CLKA, WEA, RSTA; + + output [1:0] DOB; + reg [1:0] dob_out; + wire dob_out0, dob_out1; + + input [10:0] ADDRB; + input [1:0] DIB; + input ENB, CLKB, WEB, RSTB; + + reg [4095:0] mem; + reg [8:0] count; + + reg [5:0] mi, mj, ai, aj, bi, bj, ci, cj, di, dj, ei, ej, fi, fj; + + wire [10:0] addra_int; + reg [10:0] addra_reg; + wire [1:0] dia_int; + wire ena_int, clka_int, wea_int, rsta_int; + reg ena_reg, wea_reg, rsta_reg; + wire [10:0] addrb_int; + reg [10:0] addrb_reg; + wire [1:0] dib_int; + wire enb_int, clkb_int, web_int, rstb_int; + reg enb_reg, web_reg, rstb_reg; + + time time_clka, time_clkb; + time time_clka_clkb; + time time_clkb_clka; + + reg setup_all_a_b; + reg setup_all_b_a; + reg setup_zero; + reg [1:0] data_collision, data_collision_a_b, data_collision_b_a; + reg memory_collision, memory_collision_a_b, memory_collision_b_a; + reg address_collision, address_collision_a_b, address_collision_b_a; + reg change_clka; + reg change_clkb; + + wire [11:0] mem_addra_int; + wire [11:0] mem_addra_reg; + wire [11:0] mem_addrb_int; + wire [11:0] mem_addrb_reg; + + tri0 GSR = glbl.GSR; + + always @(GSR) + if (GSR) begin + assign doa_out = 0; + end + else begin + deassign doa_out; + end + + always @(GSR) + if (GSR) begin + assign dob_out = 0; + end + else begin + deassign dob_out; + end + + buf b_doa_out0 (doa_out0, doa_out[0]); + buf b_doa_out1 (doa_out1, doa_out[1]); + buf b_dob_out0 (dob_out0, dob_out[0]); + buf b_dob_out1 (dob_out1, dob_out[1]); + buf b_doa0 (DOA[0], doa_out0); + buf b_doa1 (DOA[1], doa_out1); + buf b_dob0 (DOB[0], dob_out0); + buf b_dob1 (DOB[1], dob_out1); + buf b_addra_0 (addra_int[0], ADDRA[0]); + buf b_addra_1 (addra_int[1], ADDRA[1]); + buf b_addra_2 (addra_int[2], ADDRA[2]); + buf b_addra_3 (addra_int[3], ADDRA[3]); + buf b_addra_4 (addra_int[4], ADDRA[4]); + buf b_addra_5 (addra_int[5], ADDRA[5]); + buf b_addra_6 (addra_int[6], ADDRA[6]); + buf b_addra_7 (addra_int[7], ADDRA[7]); + buf b_addra_8 (addra_int[8], ADDRA[8]); + buf b_addra_9 (addra_int[9], ADDRA[9]); + buf b_addra_10 (addra_int[10], ADDRA[10]); + buf b_dia_0 (dia_int[0], DIA[0]); + buf b_dia_1 (dia_int[1], DIA[1]); + buf b_clka (clka_int, CLKA); + buf b_ena (ena_int, ENA); + buf b_rsta (rsta_int, RSTA); + buf b_wea (wea_int, WEA); + buf b_addrb_0 (addrb_int[0], ADDRB[0]); + buf b_addrb_1 (addrb_int[1], ADDRB[1]); + buf b_addrb_2 (addrb_int[2], ADDRB[2]); + buf b_addrb_3 (addrb_int[3], ADDRB[3]); + buf b_addrb_4 (addrb_int[4], ADDRB[4]); + buf b_addrb_5 (addrb_int[5], ADDRB[5]); + buf b_addrb_6 (addrb_int[6], ADDRB[6]); + buf b_addrb_7 (addrb_int[7], ADDRB[7]); + buf b_addrb_8 (addrb_int[8], ADDRB[8]); + buf b_addrb_9 (addrb_int[9], ADDRB[9]); + buf b_addrb_10 (addrb_int[10], ADDRB[10]); + buf b_dib_0 (dib_int[0], DIB[0]); + buf b_dib_1 (dib_int[1], DIB[1]); + buf b_clkb (clkb_int, CLKB); + buf b_enb (enb_int, ENB); + buf b_rstb (rstb_int, RSTB); + buf b_web (web_int, WEB); + + initial begin + for (count = 0; count < 256; count = count + 1) begin + mem[count] <= INIT_00[count]; + mem[256 * 1 + count] <= INIT_01[count]; + mem[256 * 2 + count] <= INIT_02[count]; + mem[256 * 3 + count] <= INIT_03[count]; + mem[256 * 4 + count] <= INIT_04[count]; + mem[256 * 5 + count] <= INIT_05[count]; + mem[256 * 6 + count] <= INIT_06[count]; + mem[256 * 7 + count] <= INIT_07[count]; + mem[256 * 8 + count] <= INIT_08[count]; + mem[256 * 9 + count] <= INIT_09[count]; + mem[256 * 10 + count] <= INIT_0A[count]; + mem[256 * 11 + count] <= INIT_0B[count]; + mem[256 * 12 + count] <= INIT_0C[count]; + mem[256 * 13 + count] <= INIT_0D[count]; + mem[256 * 14 + count] <= INIT_0E[count]; + mem[256 * 15 + count] <= INIT_0F[count]; + end + address_collision <= 0; + address_collision_a_b <= 0; + address_collision_b_a <= 0; + change_clka <= 0; + change_clkb <= 0; + data_collision <= 0; + data_collision_a_b <= 0; + data_collision_b_a <= 0; + memory_collision <= 0; + memory_collision_a_b <= 0; + memory_collision_b_a <= 0; + setup_all_a_b <= 0; + setup_all_b_a <= 0; + setup_zero <= 0; + end + + assign mem_addra_int = addra_int * 2; + assign mem_addra_reg = addra_reg * 2; + assign mem_addrb_int = addrb_int * 2; + assign mem_addrb_reg = addrb_reg * 2; + + + initial begin + + case (SIM_COLLISION_CHECK) + + "NONE" : begin + assign setup_all_a_b = 1'b0; + assign setup_all_b_a = 1'b0; + assign setup_zero = 1'b0; + assign address_collision = 1'b0; + assign address_collision_a_b = 1'b0; + assign address_collision_b_a = 1'b0; + end + "WARNING_ONLY" : begin + assign data_collision = 2'b00; + assign data_collision_a_b = 2'b00; + assign data_collision_b_a = 2'b00; + assign memory_collision = 1'b0; + assign memory_collision_a_b = 1'b0; + assign memory_collision_b_a = 1'b0; + end + "GENERATE_X_ONLY" : begin + assign address_collision = 1'b0; + assign address_collision_a_b = 1'b0; + assign address_collision_b_a = 1'b0; + end + "ALL" : ; + default : begin + $display("Attribute Syntax Error : The Attribute SIM_COLLISION_CHECK on RAMB4_S2_S2 instance %m is set to %s. Legal values for this attribute are ALL, NONE, WARNING_ONLY or GENERATE_X_ONLY.", SIM_COLLISION_CHECK); + $finish; + end + + endcase // case(SIM_COLLISION_CHECK) + + end // initial begin + + + always @(posedge clka_int) begin + time_clka = $time; + #0 time_clkb_clka = time_clka - time_clkb; + change_clka = ~change_clka; + end + + always @(posedge clkb_int) begin + time_clkb = $time; + #0 time_clka_clkb = time_clkb - time_clka; + change_clkb = ~change_clkb; + end + + always @(change_clkb) begin + if ((0 < time_clka_clkb) && (time_clka_clkb < SETUP_ALL)) + setup_all_a_b = 1; + end + + always @(change_clka) begin + if ((0 < time_clkb_clka) && (time_clkb_clka < SETUP_ALL)) + setup_all_b_a = 1; + end + + always @(change_clkb or change_clka) begin + if ((time_clkb_clka == 0) && (time_clka_clkb == 0)) + setup_zero = 1; + end + + always @(posedge setup_zero) begin + if ((ena_int == 1) && (wea_int == 1) && + (enb_int == 1) && (web_int == 1)) + memory_collision <= 1; + end + + always @(posedge setup_all_a_b) begin + if ((ena_reg == 1) && (enb_int == 1)) begin + case ({wea_reg, web_int}) + 6'b11 : begin data_collision_a_b <= 2'b11; display_all_a_b; end + 6'b01 : begin data_collision_a_b <= 2'b10; display_all_a_b; end + 6'b10 : begin data_collision_a_b <= 2'b01; display_all_a_b; end + endcase + end + setup_all_a_b <= 0; + end + + task display_all_a_b; + begin + address_collision_a_b = 1'b0; + for (ci = 0; ci < 2; ci = ci + 2) begin + if ((mem_addra_reg) == (mem_addrb_int + ci)) begin + address_collision_a_b = 1'b1; + end + end + if (address_collision_a_b == 1'b1) + + if (({wea_reg, web_int}) == 2'b11) + $display("Memory Collision Error on RAMB4_S2_S2:%m at simulation time %.3f ns\nA write was requested to the same address simultaneously at both Port A and Port B of the RAM. The contents written to the RAM at address location %h (hex) of Port A and address location %h (hex) of Port B are unknown.", $time/1000.0, addra_int, addrb_int); + + else if (({wea_reg, web_int}) == 2'b01) + $display("Memory Collision Error on RAMB4_S2_S2:%m at simulation time %.3f ns\nA read was performed on address %h (hex) of Port A while a write was requested to the same address on Port B. The write will be successful however the read value on Port A is unknown until the next CLKA cycle.", $time/1000.0, addra_int); + + else if (({wea_reg, web_int}) == 2'b10) + $display("Memory Collision Error on RAMB4_S2_S2:%m at simulation time %.3f ns\nA read was performed on address %h (hex) of Port B while a write was requested to the same address on Port A. The write will be successful however the read value on Port B is unknown until the next CLKB cycle.", $time/1000.0, addrb_int); + + end + endtask + + always @(posedge setup_all_b_a) begin + if ((ena_int == 1) && (enb_reg == 1)) begin + case ({wea_int, web_reg}) + 6'b11 : begin data_collision_b_a <= 2'b11; display_all_b_a; end + 6'b01 : begin data_collision_b_a <= 2'b10; display_all_b_a; end + 6'b10 : begin data_collision_b_a <= 2'b01; display_all_b_a; end + endcase + end + setup_all_b_a <= 0; + end + + task display_all_b_a; + begin + address_collision_b_a = 1'b0; + for (ci = 0; ci < 2; ci = ci + 2) begin + if ((mem_addra_int) == (mem_addrb_reg + ci)) begin + address_collision_b_a = 1'b1; + end + end + if (address_collision_b_a == 1'b1) + + if (({wea_int, web_reg}) == 2'b11) + $display("Memory Collision Error on RAMB4_S2_S2:%m at simulation time %.3f ns\nA write was requested to the same address simultaneously at both Port A and Port B of the RAM. The contents written to the RAM at address location %h (hex) of Port A and address location %h (hex) of Port B are unknown.", $time/1000.0, addra_int, addrb_int); + + else if (({wea_int, web_reg}) == 2'b01) + $display("Memory Collision Error on RAMB4_S2_S2:%m at simulation time %.3f ns\nA read was performed on address %h (hex) of Port A while a write was requested to the same address on Port B. The write will be successful however the read value on Port A is unknown until the next CLKA cycle.", $time/1000.0, addra_int); + + else if (({wea_int, web_reg}) == 2'b10) + $display("Memory Collision Error on RAMB4_S2_S2:%m at simulation time %.3f ns\nA read was performed on address %h (hex) of Port B while a write was requested to the same address on Port A. The write will be successful however the read value on Port B is unknown until the next CLKB cycle.", $time/1000.0, addrb_int); + + end + endtask + + always @(posedge setup_zero) begin + if ((ena_int == 1) && (enb_int == 1)) begin + case ({wea_int, web_int}) + 6'b11 : begin data_collision <= 2'b11; display_zero; end + 6'b01 : begin data_collision <= 2'b10; display_zero; end + 6'b10 : begin data_collision <= 2'b01; display_zero; end + endcase + end + setup_zero <= 0; + end + + task display_zero; + begin + address_collision = 1'b0; + for (ci = 0; ci < 2; ci = ci + 2) begin + if ((mem_addra_int) == (mem_addrb_int + ci)) begin + address_collision = 1'b1; + end + end + if (address_collision == 1'b1) + + if (({wea_int, web_int}) == 2'b11) + $display("Memory Collision Error on RAMB4_S2_S2:%m at simulation time %.3f ns\nA write was requested to the same address simultaneously at both Port A and Port B of the RAM. The contents written to the RAM at address location %h (hex) of Port A and address location %h (hex) of Port B are unknown.", $time/1000.0, addra_int, addrb_int); + + else if (({wea_int, web_int}) == 2'b01) + $display("Memory Collision Error on RAMB4_S2_S2:%m at simulation time %.3f ns\nA read was performed on address %h (hex) of Port A while a write was requested to the same address on Port B. The write will be successful however the read value on Port A is unknown until the next CLKA cycle.", $time/1000.0, addra_int); + + else if (({wea_int, web_int}) == 2'b10) + $display("Memory Collision Error on RAMB4_S2_S2:%m at simulation time %.3f ns\nA read was performed on address %h (hex) of Port B while a write was requested to the same address on Port A. The write will be successful however the read value on Port B is unknown until the next CLKB cycle.", $time/1000.0, addrb_int); + + end + endtask + + always @(posedge clka_int) begin + addra_reg <= addra_int; + ena_reg <= ena_int; + rsta_reg <= rsta_int; + wea_reg <= wea_int; + end + + always @(posedge clkb_int) begin + addrb_reg <= addrb_int; + enb_reg <= enb_int; + rstb_reg <= rstb_int; + web_reg <= web_int; + end + + // Data + always @(posedge memory_collision) begin + for (mi = 0; mi < 2; mi = mi + 2) begin + if ((mem_addra_int) == (mem_addrb_int + mi)) begin + for (mj = 0; mj < 2; mj = mj + 1) begin + mem[mem_addrb_int + mi + mj] <= 1'bX; + end + end + end + memory_collision <= 0; + end + + always @(posedge memory_collision_a_b) begin + for (mi = 0; mi < 2; mi = mi + 2) begin + if ((mem_addra_reg) == (mem_addrb_int + mi)) begin + for (mj = 0; mj < 2; mj = mj + 1) begin + mem[mem_addrb_int + mi + mj] <= 1'bX; + end + end + end + memory_collision_a_b <= 0; + end + + always @(posedge memory_collision_b_a) begin + for (mi = 0; mi < 2; mi = mi + 2) begin + if ((mem_addra_int) == (mem_addrb_reg + mi)) begin + for (mj = 0; mj < 2; mj = mj + 1) begin + mem[mem_addrb_reg + mi + mj] <= 1'bX; + end + end + end + memory_collision_b_a <= 0; + end + + always @(posedge data_collision[1]) begin + if (rsta_int == 0) begin + for (ai = 0; ai < 2; ai = ai + 2) begin + if ((mem_addra_int) == (mem_addrb_int + ai)) begin + doa_out <= 2'bX; + end + end + end + data_collision[1] <= 0; + end + + always @(posedge data_collision[0]) begin + if (rstb_int == 0) begin + for (bi = 0; bi < 2; bi = bi + 2) begin + if ((mem_addra_int) == (mem_addrb_int + bi)) begin + for (bj = 0; bj < 2; bj = bj + 1) begin + dob_out[bi + bj] <= 1'bX; + end + end + end + end + data_collision[0] <= 0; + end + + always @(posedge data_collision_a_b[1]) begin + if (rsta_reg == 0) begin + for (ai = 0; ai < 2; ai = ai + 2) begin + if ((mem_addra_reg) == (mem_addrb_int + ai)) begin + doa_out <= 2'bX; + end + end + end + data_collision_a_b[1] <= 0; + end + + always @(posedge data_collision_a_b[0]) begin + if (rstb_int == 0) begin + for (bi = 0; bi < 2; bi = bi + 2) begin + if ((mem_addra_reg) == (mem_addrb_int + bi)) begin + for (bj = 0; bj < 2; bj = bj + 1) begin + dob_out[bi + bj] <= 1'bX; + end + end + end + end + data_collision_a_b[0] <= 0; + end + + always @(posedge data_collision_b_a[1]) begin + if (rsta_int == 0) begin + for (ai = 0; ai < 2; ai = ai + 2) begin + if ((mem_addra_int) == (mem_addrb_reg + ai)) begin + doa_out <= 2'bX; + end + end + end + data_collision_b_a[1] <= 0; + end + + always @(posedge data_collision_b_a[0]) begin + if (rstb_reg == 0) begin + for (bi = 0; bi < 2; bi = bi + 2) begin + if ((mem_addra_int) == (mem_addrb_reg + bi)) begin + for (bj = 0; bj < 2; bj = bj + 1) begin + dob_out[bi + bj] <= 1'bX; + end + end + end + end + data_collision_b_a[0] <= 0; + end + + + always @(posedge clka_int) begin + if (ena_int == 1'b1) begin + if (rsta_int == 1'b1) begin + doa_out <= 2'b0; + end + else if (wea_int == 0) begin + doa_out[0] <= mem[mem_addra_int + 0]; + doa_out[1] <= mem[mem_addra_int + 1]; + end + else begin + doa_out <= dia_int; + end + end + end + + always @(posedge clka_int) begin + if (ena_int == 1'b1 && wea_int == 1'b1) begin + mem[mem_addra_int + 0] <= dia_int[0]; + mem[mem_addra_int + 1] <= dia_int[1]; + end + end + + always @(posedge clkb_int) begin + if (enb_int == 1'b1) begin + if (rstb_int == 1'b1) begin + dob_out <= 2'b0; + end + else if (web_int == 0) begin + dob_out[0] <= mem[mem_addrb_int + 0]; + dob_out[1] <= mem[mem_addrb_int + 1]; + end + else begin + dob_out <= dib_int; + end + end + end + + always @(posedge clkb_int) begin + if (enb_int == 1'b1 && web_int == 1'b1) begin + mem[mem_addrb_int + 0] <= dib_int[0]; + mem[mem_addrb_int + 1] <= dib_int[1]; + end + end + + specify + (CLKA *> DOA) = (100, 100); + (CLKB *> DOB) = (100, 100); + endspecify + +endmodule + +`else + +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/RAMB4_S2_S2.v,v 1.9 2007/02/22 01:58:06 wloo Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2005 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Timing Simulation Library Component +// / / 16K-Bit Data and 2K-Bit Parity Dual Port Block RAM +// /___/ /\ Filename : RAMB4_S2_S2.v +// \ \ / \ Timestamp : Thu Mar 10 16:44:01 PST 2005 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 03/10/05 - Initialized outputs. +// 02/21/07 - Fixed parameter SIM_COLLISION_CHECK (CR 433281). +// End Revision + +`timescale 1 ps/1 ps + +module RAMB4_S2_S2 (DOA, DOB, ADDRA, ADDRB, CLKA, CLKB, DIA, DIB, ENA, ENB, RSTA, RSTB, WEA, WEB); + + parameter SIM_COLLISION_CHECK = "ALL"; + localparam SETUP_ALL = 100; + + parameter INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + + output [1:0] DOA; + output [1:0] DOB; + + input [10:0] ADDRA; + input [1:0] DIA; + input ENA, CLKA, WEA, RSTA; + input [10:0] ADDRB; + input [1:0] DIB; + input ENB, CLKB, WEB, RSTB; + + reg [1:0] doa_out = 0; + reg [1:0] dob_out = 0; + + reg [1:0] mem [2047:0]; + + reg [8:0] count; + + reg [5:0] mi, ai, bi, bj, ci; + + wire [10:0] addra_int; + reg [10:0] addra_reg; + wire [1:0] dia_int; + wire ena_int, clka_int, wea_int, rsta_int; + reg ena_reg, wea_reg, rsta_reg; + wire [10:0] addrb_int; + reg [10:0] addrb_reg; + wire [1:0] dib_int; + wire enb_int, clkb_int, web_int, rstb_int; + reg display_flag, output_flag; + reg enb_reg, web_reg, rstb_reg; + + time time_clka, time_clkb; + time time_clka_clkb; + time time_clkb_clka; + + reg setup_all_a_b; + reg setup_all_b_a; + reg setup_zero; + reg [1:0] data_collision, data_collision_a_b, data_collision_b_a; + reg memory_collision, memory_collision_a_b, memory_collision_b_a; + reg address_collision, address_collision_a_b, address_collision_b_a; + reg change_clka; + reg change_clkb; + + wire [11:0] mem_addra_int; + wire [11:0] mem_addra_reg; + wire [11:0] mem_addrb_int; + wire [11:0] mem_addrb_reg; + + wire dia_enable = ena_int && wea_int; + wire dib_enable = enb_int && web_int; + + tri0 GSR = glbl.GSR; + wire gsr_int; + + buf b_gsr (gsr_int, GSR); + + buf b_doa [1:0] (DOA, doa_out); + buf b_addra [10:0] (addra_int, ADDRA); + buf b_dia [1:0] (dia_int, DIA); + buf b_ena (ena_int, ENA); + buf b_clka (clka_int, CLKA); + buf b_rsta (rsta_int, RSTA); + buf b_wea (wea_int, WEA); + + buf b_dob [1:0] (DOB, dob_out); + buf b_addrb [10:0] (addrb_int, ADDRB); + buf b_dib [1:0] (dib_int, DIB); + buf b_enb (enb_int, ENB); + buf b_clkb (clkb_int, CLKB); + buf b_rstb (rstb_int, RSTB); + buf b_web (web_int, WEB); + + + always @(gsr_int) + if (gsr_int) begin + assign doa_out = 0; + assign dob_out = 0; + end + else begin + deassign doa_out; + deassign dob_out; + end + + + initial begin + + for (count = 0; count < 128; count = count + 1) begin + mem[count] = INIT_00[(count * 2) +: 2]; + mem[128 * 1 + count] = INIT_01[(count * 2) +: 2]; + mem[128 * 2 + count] = INIT_02[(count * 2) +: 2]; + mem[128 * 3 + count] = INIT_03[(count * 2) +: 2]; + mem[128 * 4 + count] = INIT_04[(count * 2) +: 2]; + mem[128 * 5 + count] = INIT_05[(count * 2) +: 2]; + mem[128 * 6 + count] = INIT_06[(count * 2) +: 2]; + mem[128 * 7 + count] = INIT_07[(count * 2) +: 2]; + mem[128 * 8 + count] = INIT_08[(count * 2) +: 2]; + mem[128 * 9 + count] = INIT_09[(count * 2) +: 2]; + mem[128 * 10 + count] = INIT_0A[(count * 2) +: 2]; + mem[128 * 11 + count] = INIT_0B[(count * 2) +: 2]; + mem[128 * 12 + count] = INIT_0C[(count * 2) +: 2]; + mem[128 * 13 + count] = INIT_0D[(count * 2) +: 2]; + mem[128 * 14 + count] = INIT_0E[(count * 2) +: 2]; + mem[128 * 15 + count] = INIT_0F[(count * 2) +: 2]; + end + + change_clka <= 0; + change_clkb <= 0; + data_collision <= 0; + data_collision_a_b <= 0; + data_collision_b_a <= 0; + memory_collision <= 0; + memory_collision_a_b <= 0; + memory_collision_b_a <= 0; + setup_all_a_b <= 0; + setup_all_b_a <= 0; + setup_zero <= 0; + end + + assign mem_addra_int = addra_int * 2; + assign mem_addra_reg = addra_reg * 2; + assign mem_addrb_int = addrb_int * 2; + assign mem_addrb_reg = addrb_reg * 2; + + + initial begin + + display_flag = 1; + output_flag = 1; + + case (SIM_COLLISION_CHECK) + + "NONE" : begin + output_flag = 0; + display_flag = 0; + end + "WARNING_ONLY" : output_flag = 0; + "GENERATE_X_ONLY" : display_flag = 0; + "ALL" : ; + + default : begin + $display("Attribute Syntax Error : The Attribute SIM_COLLISION_CHECK on RAMB4_S2_S2 instance %m is set to %s. Legal values for this attribute are ALL, NONE, WARNING_ONLY or GENERATE_X_ONLY.", SIM_COLLISION_CHECK); + $finish; + end + + endcase // case(SIM_COLLISION_CHECK) + + end // initial begin + + + always @(posedge clka_int) begin + if ((output_flag || display_flag)) begin + time_clka = $time; + #0 time_clkb_clka = time_clka - time_clkb; + change_clka = ~change_clka; + end + end + + always @(posedge clkb_int) begin + if ((output_flag || display_flag)) begin + time_clkb = $time; + #0 time_clka_clkb = time_clkb - time_clka; + change_clkb = ~change_clkb; + end + end + + always @(change_clkb) begin + if ((0 < time_clka_clkb) && (time_clka_clkb < SETUP_ALL)) + setup_all_a_b = 1; + end + + always @(change_clka) begin + if ((0 < time_clkb_clka) && (time_clkb_clka < SETUP_ALL)) + setup_all_b_a = 1; + end + + always @(change_clkb or change_clka) begin + if ((time_clkb_clka == 0) && (time_clka_clkb == 0)) + setup_zero = 1; + end + + always @(posedge setup_zero) begin + if ((ena_int == 1) && (wea_int == 1) && + (enb_int == 1) && (web_int == 1)) + memory_collision <= 1; + end + + always @(posedge setup_all_a_b) begin + if ((ena_reg == 1) && (enb_int == 1)) begin + case ({wea_reg, web_int}) + 6'b11 : begin data_collision_a_b <= 2'b11; display_all_a_b; end + 6'b01 : begin data_collision_a_b <= 2'b10; display_all_a_b; end + 6'b10 : begin data_collision_a_b <= 2'b01; display_all_a_b; end + endcase + end + setup_all_a_b <= 0; + end + + task display_all_a_b; + begin + address_collision_a_b = 1'b0; + for (ci = 0; ci < 2; ci = ci + 2) begin + if ((mem_addra_reg) == (mem_addrb_int + ci)) begin + address_collision_a_b = 1'b1; + end + end + if (address_collision_a_b == 1'b1 && display_flag) + + if (({wea_reg, web_int}) == 2'b11) + $display("Memory Collision Error on RAMB4_S2_S2:%m at simulation time %.3f ns\nA write was requested to the same address simultaneously at both Port A and Port B of the RAM. The contents written to the RAM at address location %h (hex) of Port A and address location %h (hex) of Port B are unknown.", $time/1000.0, addra_int, addrb_int); + + else if (({wea_reg, web_int}) == 2'b01) + $display("Memory Collision Error on RAMB4_S2_S2:%m at simulation time %.3f ns\nA read was performed on address %h (hex) of Port A while a write was requested to the same address on Port B. The write will be successful however the read value on Port A is unknown until the next CLKA cycle.", $time/1000.0, addra_int); + + else if (({wea_reg, web_int}) == 2'b10) + $display("Memory Collision Error on RAMB4_S2_S2:%m at simulation time %.3f ns\nA read was performed on address %h (hex) of Port B while a write was requested to the same address on Port A. The write will be successful however the read value on Port B is unknown until the next CLKB cycle.", $time/1000.0, addrb_int); + + end + endtask + + always @(posedge setup_all_b_a) begin + if ((ena_int == 1) && (enb_reg == 1)) begin + case ({wea_int, web_reg}) + 6'b11 : begin data_collision_b_a <= 2'b11; display_all_b_a; end + 6'b01 : begin data_collision_b_a <= 2'b10; display_all_b_a; end + 6'b10 : begin data_collision_b_a <= 2'b01; display_all_b_a; end + endcase + end + setup_all_b_a <= 0; + end + + task display_all_b_a; + begin + address_collision_b_a = 1'b0; + for (ci = 0; ci < 2; ci = ci + 2) begin + if ((mem_addra_int) == (mem_addrb_reg + ci)) begin + address_collision_b_a = 1'b1; + end + end + if (address_collision_b_a == 1'b1 && display_flag) + + if (({wea_int, web_reg}) == 2'b11) + $display("Memory Collision Error on RAMB4_S2_S2:%m at simulation time %.3f ns\nA write was requested to the same address simultaneously at both Port A and Port B of the RAM. The contents written to the RAM at address location %h (hex) of Port A and address location %h (hex) of Port B are unknown.", $time/1000.0, addra_int, addrb_int); + + else if (({wea_int, web_reg}) == 2'b01) + $display("Memory Collision Error on RAMB4_S2_S2:%m at simulation time %.3f ns\nA read was performed on address %h (hex) of Port A while a write was requested to the same address on Port B. The write will be successful however the read value on Port A is unknown until the next CLKA cycle.", $time/1000.0, addra_int); + + else if (({wea_int, web_reg}) == 2'b10) + $display("Memory Collision Error on RAMB4_S2_S2:%m at simulation time %.3f ns\nA read was performed on address %h (hex) of Port B while a write was requested to the same address on Port A. The write will be successful however the read value on Port B is unknown until the next CLKB cycle.", $time/1000.0, addrb_int); + + end + endtask + + always @(posedge setup_zero) begin + if ((ena_int == 1) && (enb_int == 1)) begin + case ({wea_int, web_int}) + 6'b11 : begin data_collision <= 2'b11; display_zero; end + 6'b01 : begin data_collision <= 2'b10; display_zero; end + 6'b10 : begin data_collision <= 2'b01; display_zero; end + endcase + end + setup_zero <= 0; + end + + task display_zero; + begin + address_collision = 1'b0; + for (ci = 0; ci < 2; ci = ci + 2) begin + if ((mem_addra_int) == (mem_addrb_int + ci)) begin + address_collision = 1'b1; + end + end + if (address_collision == 1'b1 && display_flag) + + if (({wea_int, web_int}) == 2'b11) + $display("Memory Collision Error on RAMB4_S2_S2:%m at simulation time %.3f ns\nA write was requested to the same address simultaneously at both Port A and Port B of the RAM. The contents written to the RAM at address location %h (hex) of Port A and address location %h (hex) of Port B are unknown.", $time/1000.0, addra_int, addrb_int); + + else if (({wea_int, web_int}) == 2'b01) + $display("Memory Collision Error on RAMB4_S2_S2:%m at simulation time %.3f ns\nA read was performed on address %h (hex) of Port A while a write was requested to the same address on Port B. The write will be successful however the read value on Port A is unknown until the next CLKA cycle.", $time/1000.0, addra_int); + + else if (({wea_int, web_int}) == 2'b10) + $display("Memory Collision Error on RAMB4_S2_S2:%m at simulation time %.3f ns\nA read was performed on address %h (hex) of Port B while a write was requested to the same address on Port A. The write will be successful however the read value on Port B is unknown until the next CLKB cycle.", $time/1000.0, addrb_int); + + end + endtask + + always @(posedge clka_int) begin + if ((output_flag || display_flag)) begin + addra_reg <= addra_int; + ena_reg <= ena_int; + rsta_reg <= rsta_int; + wea_reg <= wea_int; + end + end + + always @(posedge clkb_int) begin + if ((output_flag || display_flag)) begin + addrb_reg <= addrb_int; + enb_reg <= enb_int; + rstb_reg <= rstb_int; + web_reg <= web_int; + end + end + + + // Data + always @(posedge memory_collision) begin + if ((output_flag || display_flag)) begin + for (mi = 0; mi < 2; mi = mi + 2) begin + if ((mem_addra_int) == (mem_addrb_int + mi)) begin + mem[addra_int] <= 2'bx; + end + end + memory_collision <= 0; + end + end + + always @(posedge memory_collision_a_b) begin + if ((output_flag || display_flag)) begin + for (mi = 0; mi < 2; mi = mi + 2) begin + if ((mem_addra_reg) == (mem_addrb_int + mi)) begin + mem[addra_reg] <= 2'bx; + end + end + memory_collision_a_b <= 0; + end + end + + always @(posedge memory_collision_b_a) begin + if ((output_flag || display_flag)) begin + for (mi = 0; mi < 2; mi = mi + 2) begin + if ((mem_addra_int) == (mem_addrb_reg + mi)) begin + mem[addra_int] <= 2'bx; + end + end + memory_collision_b_a <= 0; + end + end + + always @(posedge data_collision[1]) begin + if (rsta_int == 0 && output_flag) begin + for (ai = 0; ai < 2; ai = ai + 2) begin + if ((mem_addra_int) == (mem_addrb_int + ai)) begin + doa_out <= #100 2'bX; + end + end + end + data_collision[1] <= 0; + end + + always @(posedge data_collision[0]) begin + if (rstb_int == 0 && output_flag) begin + for (bi = 0; bi < 2; bi = bi + 2) begin + if ((mem_addra_int) == (mem_addrb_int + bi)) begin + for (bj = 0; bj < 2; bj = bj + 1) begin + dob_out[bi + bj] <= #100 1'bX; + end + end + end + end + data_collision[0] <= 0; + end + + always @(posedge data_collision_a_b[1]) begin + if (rsta_reg == 0 && output_flag) begin + for (ai = 0; ai < 2; ai = ai + 2) begin + if ((mem_addra_reg) == (mem_addrb_int + ai)) begin + doa_out <= #100 2'bX; + end + end + end + data_collision_a_b[1] <= 0; + end + + always @(posedge data_collision_a_b[0]) begin + if (rstb_int == 0 && output_flag) begin + for (bi = 0; bi < 2; bi = bi + 2) begin + if ((mem_addra_reg) == (mem_addrb_int + bi)) begin + for (bj = 0; bj < 2; bj = bj + 1) begin + dob_out[bi + bj] <= #100 1'bX; + end + end + end + end + data_collision_a_b[0] <= 0; + end + + always @(posedge data_collision_b_a[1]) begin + if (rsta_int == 0 && output_flag) begin + for (ai = 0; ai < 2; ai = ai + 2) begin + if ((mem_addra_int) == (mem_addrb_reg + ai)) begin + doa_out <= #100 2'bX; + end + end + end + data_collision_b_a[1] <= 0; + end + + always @(posedge data_collision_b_a[0]) begin + if (rstb_reg == 0 && output_flag) begin + for (bi = 0; bi < 2; bi = bi + 2) begin + if ((mem_addra_int) == (mem_addrb_reg + bi)) begin + for (bj = 0; bj < 2; bj = bj + 1) begin + dob_out[bi + bj] <= #100 1'bX; + end + end + end + end + data_collision_b_a[0] <= 0; + end + + + // Port A + always @(posedge clka_int) begin + + if (ena_int == 1'b1) begin + + if (rsta_int == 1'b1) begin + doa_out <= #100 0; + end + else begin + if (wea_int == 1'b1) + doa_out <= #100 dia_int; + else + doa_out <= #100 mem[addra_int]; + end + + // memory + if (wea_int == 1'b1) begin + mem[addra_int] <= dia_int; + end + + end + end + + + // Port B + always @(posedge clkb_int) begin + + if (enb_int == 1'b1) begin + + if (rstb_int == 1'b1) begin + dob_out <= #100 0; + end + else begin + if (web_int == 1'b1) + dob_out <= #100 dib_int; + else + dob_out <= #100 mem[addrb_int]; + end + + // memory + if (web_int == 1'b1) begin + mem[addrb_int] <= dib_int; + end + + end + end + + +endmodule + +`endif diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/RAMB4_S2_S4.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/RAMB4_S2_S4.v new file mode 100644 index 0000000..a1093ea --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/RAMB4_S2_S4.v @@ -0,0 +1,1056 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/RAMB4_S2_S4.v,v 1.9 2007/02/22 01:58:06 wloo Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2005 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / 4K-Bit Data Dual Port Block RAM +// /___/ /\ Filename : RAMB4_S2_S4.v +// \ \ / \ Timestamp : Thu Mar 10 16:43:38 PST 2005 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// End Revision + +`ifdef legacy_model + +`timescale 1 ps / 1 ps + +module RAMB4_S2_S4 (DOA, DOB, ADDRA, ADDRB, CLKA, CLKB, DIA, DIB, ENA, ENB, RSTA, RSTB, WEA, WEB); + + parameter SIM_COLLISION_CHECK = "ALL"; + localparam SETUP_ALL = 100; + + parameter INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + + output [1:0] DOA; + reg [1:0] doa_out; + wire doa_out0, doa_out1; + + input [10:0] ADDRA; + input [1:0] DIA; + input ENA, CLKA, WEA, RSTA; + + output [3:0] DOB; + reg [3:0] dob_out; + wire dob_out0, dob_out1, dob_out2, dob_out3; + + input [9:0] ADDRB; + input [3:0] DIB; + input ENB, CLKB, WEB, RSTB; + + reg [4095:0] mem; + reg [8:0] count; + + reg [5:0] mi, mj, ai, aj, bi, bj, ci, cj, di, dj, ei, ej, fi, fj; + + wire [10:0] addra_int; + reg [10:0] addra_reg; + wire [1:0] dia_int; + wire ena_int, clka_int, wea_int, rsta_int; + reg ena_reg, wea_reg, rsta_reg; + wire [9:0] addrb_int; + reg [9:0] addrb_reg; + wire [3:0] dib_int; + wire enb_int, clkb_int, web_int, rstb_int; + reg enb_reg, web_reg, rstb_reg; + + time time_clka, time_clkb; + time time_clka_clkb; + time time_clkb_clka; + + reg setup_all_a_b; + reg setup_all_b_a; + reg setup_zero; + reg [1:0] data_collision, data_collision_a_b, data_collision_b_a; + reg memory_collision, memory_collision_a_b, memory_collision_b_a; + reg address_collision, address_collision_a_b, address_collision_b_a; + reg change_clka; + reg change_clkb; + + wire [11:0] mem_addra_int; + wire [11:0] mem_addra_reg; + wire [11:0] mem_addrb_int; + wire [11:0] mem_addrb_reg; + + tri0 GSR = glbl.GSR; + + always @(GSR) + if (GSR) begin + assign doa_out = 0; + end + else begin + deassign doa_out; + end + + always @(GSR) + if (GSR) begin + assign dob_out = 0; + end + else begin + deassign dob_out; + end + + buf b_doa_out0 (doa_out0, doa_out[0]); + buf b_doa_out1 (doa_out1, doa_out[1]); + buf b_dob_out0 (dob_out0, dob_out[0]); + buf b_dob_out1 (dob_out1, dob_out[1]); + buf b_dob_out2 (dob_out2, dob_out[2]); + buf b_dob_out3 (dob_out3, dob_out[3]); + buf b_doa0 (DOA[0], doa_out0); + buf b_doa1 (DOA[1], doa_out1); + buf b_dob0 (DOB[0], dob_out0); + buf b_dob1 (DOB[1], dob_out1); + buf b_dob2 (DOB[2], dob_out2); + buf b_dob3 (DOB[3], dob_out3); + buf b_addra_0 (addra_int[0], ADDRA[0]); + buf b_addra_1 (addra_int[1], ADDRA[1]); + buf b_addra_2 (addra_int[2], ADDRA[2]); + buf b_addra_3 (addra_int[3], ADDRA[3]); + buf b_addra_4 (addra_int[4], ADDRA[4]); + buf b_addra_5 (addra_int[5], ADDRA[5]); + buf b_addra_6 (addra_int[6], ADDRA[6]); + buf b_addra_7 (addra_int[7], ADDRA[7]); + buf b_addra_8 (addra_int[8], ADDRA[8]); + buf b_addra_9 (addra_int[9], ADDRA[9]); + buf b_addra_10 (addra_int[10], ADDRA[10]); + buf b_dia_0 (dia_int[0], DIA[0]); + buf b_dia_1 (dia_int[1], DIA[1]); + buf b_clka (clka_int, CLKA); + buf b_ena (ena_int, ENA); + buf b_rsta (rsta_int, RSTA); + buf b_wea (wea_int, WEA); + buf b_addrb_0 (addrb_int[0], ADDRB[0]); + buf b_addrb_1 (addrb_int[1], ADDRB[1]); + buf b_addrb_2 (addrb_int[2], ADDRB[2]); + buf b_addrb_3 (addrb_int[3], ADDRB[3]); + buf b_addrb_4 (addrb_int[4], ADDRB[4]); + buf b_addrb_5 (addrb_int[5], ADDRB[5]); + buf b_addrb_6 (addrb_int[6], ADDRB[6]); + buf b_addrb_7 (addrb_int[7], ADDRB[7]); + buf b_addrb_8 (addrb_int[8], ADDRB[8]); + buf b_addrb_9 (addrb_int[9], ADDRB[9]); + buf b_dib_0 (dib_int[0], DIB[0]); + buf b_dib_1 (dib_int[1], DIB[1]); + buf b_dib_2 (dib_int[2], DIB[2]); + buf b_dib_3 (dib_int[3], DIB[3]); + buf b_clkb (clkb_int, CLKB); + buf b_enb (enb_int, ENB); + buf b_rstb (rstb_int, RSTB); + buf b_web (web_int, WEB); + + initial begin + for (count = 0; count < 256; count = count + 1) begin + mem[count] <= INIT_00[count]; + mem[256 * 1 + count] <= INIT_01[count]; + mem[256 * 2 + count] <= INIT_02[count]; + mem[256 * 3 + count] <= INIT_03[count]; + mem[256 * 4 + count] <= INIT_04[count]; + mem[256 * 5 + count] <= INIT_05[count]; + mem[256 * 6 + count] <= INIT_06[count]; + mem[256 * 7 + count] <= INIT_07[count]; + mem[256 * 8 + count] <= INIT_08[count]; + mem[256 * 9 + count] <= INIT_09[count]; + mem[256 * 10 + count] <= INIT_0A[count]; + mem[256 * 11 + count] <= INIT_0B[count]; + mem[256 * 12 + count] <= INIT_0C[count]; + mem[256 * 13 + count] <= INIT_0D[count]; + mem[256 * 14 + count] <= INIT_0E[count]; + mem[256 * 15 + count] <= INIT_0F[count]; + end + address_collision <= 0; + address_collision_a_b <= 0; + address_collision_b_a <= 0; + change_clka <= 0; + change_clkb <= 0; + data_collision <= 0; + data_collision_a_b <= 0; + data_collision_b_a <= 0; + memory_collision <= 0; + memory_collision_a_b <= 0; + memory_collision_b_a <= 0; + setup_all_a_b <= 0; + setup_all_b_a <= 0; + setup_zero <= 0; + end + + assign mem_addra_int = addra_int * 2; + assign mem_addra_reg = addra_reg * 2; + assign mem_addrb_int = addrb_int * 4; + assign mem_addrb_reg = addrb_reg * 4; + + + initial begin + + case (SIM_COLLISION_CHECK) + + "NONE" : begin + assign setup_all_a_b = 1'b0; + assign setup_all_b_a = 1'b0; + assign setup_zero = 1'b0; + assign address_collision = 1'b0; + assign address_collision_a_b = 1'b0; + assign address_collision_b_a = 1'b0; + end + "WARNING_ONLY" : begin + assign data_collision = 2'b00; + assign data_collision_a_b = 2'b00; + assign data_collision_b_a = 2'b00; + assign memory_collision = 1'b0; + assign memory_collision_a_b = 1'b0; + assign memory_collision_b_a = 1'b0; + end + "GENERATE_X_ONLY" : begin + assign address_collision = 1'b0; + assign address_collision_a_b = 1'b0; + assign address_collision_b_a = 1'b0; + end + "ALL" : ; + default : begin + $display("Attribute Syntax Error : The Attribute SIM_COLLISION_CHECK on RAMB4_S2_S4 instance %m is set to %s. Legal values for this attribute are ALL, NONE, WARNING_ONLY or GENERATE_X_ONLY.", SIM_COLLISION_CHECK); + $finish; + end + + endcase // case(SIM_COLLISION_CHECK) + + end // initial begin + + + always @(posedge clka_int) begin + time_clka = $time; + #0 time_clkb_clka = time_clka - time_clkb; + change_clka = ~change_clka; + end + + always @(posedge clkb_int) begin + time_clkb = $time; + #0 time_clka_clkb = time_clkb - time_clka; + change_clkb = ~change_clkb; + end + + always @(change_clkb) begin + if ((0 < time_clka_clkb) && (time_clka_clkb < SETUP_ALL)) + setup_all_a_b = 1; + end + + always @(change_clka) begin + if ((0 < time_clkb_clka) && (time_clkb_clka < SETUP_ALL)) + setup_all_b_a = 1; + end + + always @(change_clkb or change_clka) begin + if ((time_clkb_clka == 0) && (time_clka_clkb == 0)) + setup_zero = 1; + end + + always @(posedge setup_zero) begin + if ((ena_int == 1) && (wea_int == 1) && + (enb_int == 1) && (web_int == 1)) + memory_collision <= 1; + end + + always @(posedge setup_all_a_b) begin + if ((ena_reg == 1) && (enb_int == 1)) begin + case ({wea_reg, web_int}) + 6'b11 : begin data_collision_a_b <= 2'b11; display_all_a_b; end + 6'b01 : begin data_collision_a_b <= 2'b10; display_all_a_b; end + 6'b10 : begin data_collision_a_b <= 2'b01; display_all_a_b; end + endcase + end + setup_all_a_b <= 0; + end + + task display_all_a_b; + begin + address_collision_a_b = 1'b0; + for (ci = 0; ci < 4; ci = ci + 2) begin + if ((mem_addra_reg) == (mem_addrb_int + ci)) begin + address_collision_a_b = 1'b1; + end + end + if (address_collision_a_b == 1'b1) + + if (({wea_reg, web_int}) == 2'b11) + $display("Memory Collision Error on RAMB4_S2_S4:%m at simulation time %.3f ns\nA write was requested to the same address simultaneously at both Port A and Port B of the RAM. The contents written to the RAM at address location %h (hex) of Port A and address location %h (hex) of Port B are unknown.", $time/1000.0, addra_int, addrb_int); + + else if (({wea_reg, web_int}) == 2'b01) + $display("Memory Collision Error on RAMB4_S2_S4:%m at simulation time %.3f ns\nA read was performed on address %h (hex) of Port A while a write was requested to the same address on Port B. The write will be successful however the read value on Port A is unknown until the next CLKA cycle.", $time/1000.0, addra_int); + + else if (({wea_reg, web_int}) == 2'b10) + $display("Memory Collision Error on RAMB4_S2_S4:%m at simulation time %.3f ns\nA read was performed on address %h (hex) of Port B while a write was requested to the same address on Port A. The write will be successful however the read value on Port B is unknown until the next CLKB cycle.", $time/1000.0, addrb_int); + + end + endtask + + always @(posedge setup_all_b_a) begin + if ((ena_int == 1) && (enb_reg == 1)) begin + case ({wea_int, web_reg}) + 6'b11 : begin data_collision_b_a <= 2'b11; display_all_b_a; end + 6'b01 : begin data_collision_b_a <= 2'b10; display_all_b_a; end + 6'b10 : begin data_collision_b_a <= 2'b01; display_all_b_a; end + endcase + end + setup_all_b_a <= 0; + end + + task display_all_b_a; + begin + address_collision_b_a = 1'b0; + for (ci = 0; ci < 4; ci = ci + 2) begin + if ((mem_addra_int) == (mem_addrb_reg + ci)) begin + address_collision_b_a = 1'b1; + end + end + if (address_collision_b_a == 1'b1) + + if (({wea_int, web_reg}) == 2'b11) + $display("Memory Collision Error on RAMB4_S2_S4:%m at simulation time %.3f ns\nA write was requested to the same address simultaneously at both Port A and Port B of the RAM. The contents written to the RAM at address location %h (hex) of Port A and address location %h (hex) of Port B are unknown.", $time/1000.0, addra_int, addrb_int); + + else if (({wea_int, web_reg}) == 2'b01) + $display("Memory Collision Error on RAMB4_S2_S4:%m at simulation time %.3f ns\nA read was performed on address %h (hex) of Port A while a write was requested to the same address on Port B. The write will be successful however the read value on Port A is unknown until the next CLKA cycle.", $time/1000.0, addra_int); + + else if (({wea_int, web_reg}) == 2'b10) + $display("Memory Collision Error on RAMB4_S2_S4:%m at simulation time %.3f ns\nA read was performed on address %h (hex) of Port B while a write was requested to the same address on Port A. The write will be successful however the read value on Port B is unknown until the next CLKB cycle.", $time/1000.0, addrb_int); + + end + endtask + + always @(posedge setup_zero) begin + if ((ena_int == 1) && (enb_int == 1)) begin + case ({wea_int, web_int}) + 6'b11 : begin data_collision <= 2'b11; display_zero; end + 6'b01 : begin data_collision <= 2'b10; display_zero; end + 6'b10 : begin data_collision <= 2'b01; display_zero; end + endcase + end + setup_zero <= 0; + end + + task display_zero; + begin + address_collision = 1'b0; + for (ci = 0; ci < 4; ci = ci + 2) begin + if ((mem_addra_int) == (mem_addrb_int + ci)) begin + address_collision = 1'b1; + end + end + if (address_collision == 1'b1) + + if (({wea_int, web_int}) == 2'b11) + $display("Memory Collision Error on RAMB4_S2_S4:%m at simulation time %.3f ns\nA write was requested to the same address simultaneously at both Port A and Port B of the RAM. The contents written to the RAM at address location %h (hex) of Port A and address location %h (hex) of Port B are unknown.", $time/1000.0, addra_int, addrb_int); + + else if (({wea_int, web_int}) == 2'b01) + $display("Memory Collision Error on RAMB4_S2_S4:%m at simulation time %.3f ns\nA read was performed on address %h (hex) of Port A while a write was requested to the same address on Port B. The write will be successful however the read value on Port A is unknown until the next CLKA cycle.", $time/1000.0, addra_int); + + else if (({wea_int, web_int}) == 2'b10) + $display("Memory Collision Error on RAMB4_S2_S4:%m at simulation time %.3f ns\nA read was performed on address %h (hex) of Port B while a write was requested to the same address on Port A. The write will be successful however the read value on Port B is unknown until the next CLKB cycle.", $time/1000.0, addrb_int); + + end + endtask + + always @(posedge clka_int) begin + addra_reg <= addra_int; + ena_reg <= ena_int; + rsta_reg <= rsta_int; + wea_reg <= wea_int; + end + + always @(posedge clkb_int) begin + addrb_reg <= addrb_int; + enb_reg <= enb_int; + rstb_reg <= rstb_int; + web_reg <= web_int; + end + + // Data + always @(posedge memory_collision) begin + for (mi = 0; mi < 4; mi = mi + 2) begin + if ((mem_addra_int) == (mem_addrb_int + mi)) begin + for (mj = 0; mj < 2; mj = mj + 1) begin + mem[mem_addrb_int + mi + mj] <= 1'bX; + end + end + end + memory_collision <= 0; + end + + always @(posedge memory_collision_a_b) begin + for (mi = 0; mi < 4; mi = mi + 2) begin + if ((mem_addra_reg) == (mem_addrb_int + mi)) begin + for (mj = 0; mj < 2; mj = mj + 1) begin + mem[mem_addrb_int + mi + mj] <= 1'bX; + end + end + end + memory_collision_a_b <= 0; + end + + always @(posedge memory_collision_b_a) begin + for (mi = 0; mi < 4; mi = mi + 2) begin + if ((mem_addra_int) == (mem_addrb_reg + mi)) begin + for (mj = 0; mj < 2; mj = mj + 1) begin + mem[mem_addrb_reg + mi + mj] <= 1'bX; + end + end + end + memory_collision_b_a <= 0; + end + + always @(posedge data_collision[1]) begin + if (rsta_int == 0) begin + for (ai = 0; ai < 4; ai = ai + 2) begin + if ((mem_addra_int) == (mem_addrb_int + ai)) begin + doa_out <= 2'bX; + end + end + end + data_collision[1] <= 0; + end + + always @(posedge data_collision[0]) begin + if (rstb_int == 0) begin + for (bi = 0; bi < 4; bi = bi + 2) begin + if ((mem_addra_int) == (mem_addrb_int + bi)) begin + for (bj = 0; bj < 2; bj = bj + 1) begin + dob_out[bi + bj] <= 1'bX; + end + end + end + end + data_collision[0] <= 0; + end + + always @(posedge data_collision_a_b[1]) begin + if (rsta_reg == 0) begin + for (ai = 0; ai < 4; ai = ai + 2) begin + if ((mem_addra_reg) == (mem_addrb_int + ai)) begin + doa_out <= 2'bX; + end + end + end + data_collision_a_b[1] <= 0; + end + + always @(posedge data_collision_a_b[0]) begin + if (rstb_int == 0) begin + for (bi = 0; bi < 4; bi = bi + 2) begin + if ((mem_addra_reg) == (mem_addrb_int + bi)) begin + for (bj = 0; bj < 2; bj = bj + 1) begin + dob_out[bi + bj] <= 1'bX; + end + end + end + end + data_collision_a_b[0] <= 0; + end + + always @(posedge data_collision_b_a[1]) begin + if (rsta_int == 0) begin + for (ai = 0; ai < 4; ai = ai + 2) begin + if ((mem_addra_int) == (mem_addrb_reg + ai)) begin + doa_out <= 2'bX; + end + end + end + data_collision_b_a[1] <= 0; + end + + always @(posedge data_collision_b_a[0]) begin + if (rstb_reg == 0) begin + for (bi = 0; bi < 4; bi = bi + 2) begin + if ((mem_addra_int) == (mem_addrb_reg + bi)) begin + for (bj = 0; bj < 2; bj = bj + 1) begin + dob_out[bi + bj] <= 1'bX; + end + end + end + end + data_collision_b_a[0] <= 0; + end + + + always @(posedge clka_int) begin + if (ena_int == 1'b1) begin + if (rsta_int == 1'b1) begin + doa_out <= 2'b0; + end + else if (wea_int == 0) begin + doa_out[0] <= mem[mem_addra_int + 0]; + doa_out[1] <= mem[mem_addra_int + 1]; + end + else begin + doa_out <= dia_int; + end + end + end + + always @(posedge clka_int) begin + if (ena_int == 1'b1 && wea_int == 1'b1) begin + mem[mem_addra_int + 0] <= dia_int[0]; + mem[mem_addra_int + 1] <= dia_int[1]; + end + end + + always @(posedge clkb_int) begin + if (enb_int == 1'b1) begin + if (rstb_int == 1'b1) begin + dob_out <= 4'b0; + end + else if (web_int == 0) begin + dob_out[0] <= mem[mem_addrb_int + 0]; + dob_out[1] <= mem[mem_addrb_int + 1]; + dob_out[2] <= mem[mem_addrb_int + 2]; + dob_out[3] <= mem[mem_addrb_int + 3]; + end + else begin + dob_out <= dib_int; + end + end + end + + always @(posedge clkb_int) begin + if (enb_int == 1'b1 && web_int == 1'b1) begin + mem[mem_addrb_int + 0] <= dib_int[0]; + mem[mem_addrb_int + 1] <= dib_int[1]; + mem[mem_addrb_int + 2] <= dib_int[2]; + mem[mem_addrb_int + 3] <= dib_int[3]; + end + end + + specify + (CLKA *> DOA) = (100, 100); + (CLKB *> DOB) = (100, 100); + endspecify + +endmodule + +`else + +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/RAMB4_S2_S4.v,v 1.9 2007/02/22 01:58:06 wloo Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2005 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Timing Simulation Library Component +// / / 16K-Bit Data and 2K-Bit Parity Dual Port Block RAM +// /___/ /\ Filename : RAMB4_S2_S4.v +// \ \ / \ Timestamp : Thu Mar 10 16:44:01 PST 2005 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 03/10/05 - Initialized outputs. +// 02/21/07 - Fixed parameter SIM_COLLISION_CHECK (CR 433281). +// End Revision + +`timescale 1 ps/1 ps + +module RAMB4_S2_S4 (DOA, DOB, ADDRA, ADDRB, CLKA, CLKB, DIA, DIB, ENA, ENB, RSTA, RSTB, WEA, WEB); + + parameter SIM_COLLISION_CHECK = "ALL"; + localparam SETUP_ALL = 100; + + parameter INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + + output [1:0] DOA; + output [3:0] DOB; + + input [10:0] ADDRA; + input [1:0] DIA; + input ENA, CLKA, WEA, RSTA; + input [9:0] ADDRB; + input [3:0] DIB; + input ENB, CLKB, WEB, RSTB; + + reg [1:0] doa_out = 0; + reg [3:0] dob_out = 0; + + reg [3:0] mem [1023:0]; + + reg [8:0] count; + + reg [5:0] mi, ai, bi, bj, ci; + + wire [10:0] addra_int; + reg [10:0] addra_reg; + wire [1:0] dia_int; + wire ena_int, clka_int, wea_int, rsta_int; + reg ena_reg, wea_reg, rsta_reg; + wire [9:0] addrb_int; + reg [9:0] addrb_reg; + wire [3:0] dib_int; + wire enb_int, clkb_int, web_int, rstb_int; + reg display_flag, output_flag; + reg enb_reg, web_reg, rstb_reg; + + time time_clka, time_clkb; + time time_clka_clkb; + time time_clkb_clka; + + reg setup_all_a_b; + reg setup_all_b_a; + reg setup_zero; + reg [1:0] data_collision, data_collision_a_b, data_collision_b_a; + reg memory_collision, memory_collision_a_b, memory_collision_b_a; + reg address_collision, address_collision_a_b, address_collision_b_a; + reg change_clka; + reg change_clkb; + + wire [11:0] mem_addra_int; + wire [11:0] mem_addra_reg; + wire [11:0] mem_addrb_int; + wire [11:0] mem_addrb_reg; + + wire dia_enable = ena_int && wea_int; + wire dib_enable = enb_int && web_int; + + tri0 GSR = glbl.GSR; + wire gsr_int; + + buf b_gsr (gsr_int, GSR); + + buf b_doa [1:0] (DOA, doa_out); + buf b_addra [10:0] (addra_int, ADDRA); + buf b_dia [1:0] (dia_int, DIA); + buf b_ena (ena_int, ENA); + buf b_clka (clka_int, CLKA); + buf b_rsta (rsta_int, RSTA); + buf b_wea (wea_int, WEA); + + buf b_dob [3:0] (DOB, dob_out); + buf b_addrb [9:0] (addrb_int, ADDRB); + buf b_dib [3:0] (dib_int, DIB); + buf b_enb (enb_int, ENB); + buf b_clkb (clkb_int, CLKB); + buf b_rstb (rstb_int, RSTB); + buf b_web (web_int, WEB); + + + always @(gsr_int) + if (gsr_int) begin + assign doa_out = 0; + assign dob_out = 0; + end + else begin + deassign doa_out; + deassign dob_out; + end + + + initial begin + + for (count = 0; count < 64; count = count + 1) begin + mem[count] = INIT_00[(count * 4) +: 4]; + mem[64 * 1 + count] = INIT_01[(count * 4) +: 4]; + mem[64 * 2 + count] = INIT_02[(count * 4) +: 4]; + mem[64 * 3 + count] = INIT_03[(count * 4) +: 4]; + mem[64 * 4 + count] = INIT_04[(count * 4) +: 4]; + mem[64 * 5 + count] = INIT_05[(count * 4) +: 4]; + mem[64 * 6 + count] = INIT_06[(count * 4) +: 4]; + mem[64 * 7 + count] = INIT_07[(count * 4) +: 4]; + mem[64 * 8 + count] = INIT_08[(count * 4) +: 4]; + mem[64 * 9 + count] = INIT_09[(count * 4) +: 4]; + mem[64 * 10 + count] = INIT_0A[(count * 4) +: 4]; + mem[64 * 11 + count] = INIT_0B[(count * 4) +: 4]; + mem[64 * 12 + count] = INIT_0C[(count * 4) +: 4]; + mem[64 * 13 + count] = INIT_0D[(count * 4) +: 4]; + mem[64 * 14 + count] = INIT_0E[(count * 4) +: 4]; + mem[64 * 15 + count] = INIT_0F[(count * 4) +: 4]; + end + + change_clka <= 0; + change_clkb <= 0; + data_collision <= 0; + data_collision_a_b <= 0; + data_collision_b_a <= 0; + memory_collision <= 0; + memory_collision_a_b <= 0; + memory_collision_b_a <= 0; + setup_all_a_b <= 0; + setup_all_b_a <= 0; + setup_zero <= 0; + end + + assign mem_addra_int = addra_int * 2; + assign mem_addra_reg = addra_reg * 2; + assign mem_addrb_int = addrb_int * 4; + assign mem_addrb_reg = addrb_reg * 4; + + + initial begin + + display_flag = 1; + output_flag = 1; + + case (SIM_COLLISION_CHECK) + + "NONE" : begin + output_flag = 0; + display_flag = 0; + end + "WARNING_ONLY" : output_flag = 0; + "GENERATE_X_ONLY" : display_flag = 0; + "ALL" : ; + + default : begin + $display("Attribute Syntax Error : The Attribute SIM_COLLISION_CHECK on RAMB4_S2_S4 instance %m is set to %s. Legal values for this attribute are ALL, NONE, WARNING_ONLY or GENERATE_X_ONLY.", SIM_COLLISION_CHECK); + $finish; + end + + endcase // case(SIM_COLLISION_CHECK) + + end // initial begin + + + always @(posedge clka_int) begin + if ((output_flag || display_flag)) begin + time_clka = $time; + #0 time_clkb_clka = time_clka - time_clkb; + change_clka = ~change_clka; + end + end + + always @(posedge clkb_int) begin + if ((output_flag || display_flag)) begin + time_clkb = $time; + #0 time_clka_clkb = time_clkb - time_clka; + change_clkb = ~change_clkb; + end + end + + always @(change_clkb) begin + if ((0 < time_clka_clkb) && (time_clka_clkb < SETUP_ALL)) + setup_all_a_b = 1; + end + + always @(change_clka) begin + if ((0 < time_clkb_clka) && (time_clkb_clka < SETUP_ALL)) + setup_all_b_a = 1; + end + + always @(change_clkb or change_clka) begin + if ((time_clkb_clka == 0) && (time_clka_clkb == 0)) + setup_zero = 1; + end + + always @(posedge setup_zero) begin + if ((ena_int == 1) && (wea_int == 1) && + (enb_int == 1) && (web_int == 1)) + memory_collision <= 1; + end + + always @(posedge setup_all_a_b) begin + if ((ena_reg == 1) && (enb_int == 1)) begin + case ({wea_reg, web_int}) + 6'b11 : begin data_collision_a_b <= 2'b11; display_all_a_b; end + 6'b01 : begin data_collision_a_b <= 2'b10; display_all_a_b; end + 6'b10 : begin data_collision_a_b <= 2'b01; display_all_a_b; end + endcase + end + setup_all_a_b <= 0; + end + + task display_all_a_b; + begin + address_collision_a_b = 1'b0; + for (ci = 0; ci < 4; ci = ci + 2) begin + if ((mem_addra_reg) == (mem_addrb_int + ci)) begin + address_collision_a_b = 1'b1; + end + end + if (address_collision_a_b == 1'b1 && display_flag) + + if (({wea_reg, web_int}) == 2'b11) + $display("Memory Collision Error on RAMB4_S2_S4:%m at simulation time %.3f ns\nA write was requested to the same address simultaneously at both Port A and Port B of the RAM. The contents written to the RAM at address location %h (hex) of Port A and address location %h (hex) of Port B are unknown.", $time/1000.0, addra_int, addrb_int); + + else if (({wea_reg, web_int}) == 2'b01) + $display("Memory Collision Error on RAMB4_S2_S4:%m at simulation time %.3f ns\nA read was performed on address %h (hex) of Port A while a write was requested to the same address on Port B. The write will be successful however the read value on Port A is unknown until the next CLKA cycle.", $time/1000.0, addra_int); + + else if (({wea_reg, web_int}) == 2'b10) + $display("Memory Collision Error on RAMB4_S2_S4:%m at simulation time %.3f ns\nA read was performed on address %h (hex) of Port B while a write was requested to the same address on Port A. The write will be successful however the read value on Port B is unknown until the next CLKB cycle.", $time/1000.0, addrb_int); + + end + endtask + + always @(posedge setup_all_b_a) begin + if ((ena_int == 1) && (enb_reg == 1)) begin + case ({wea_int, web_reg}) + 6'b11 : begin data_collision_b_a <= 2'b11; display_all_b_a; end + 6'b01 : begin data_collision_b_a <= 2'b10; display_all_b_a; end + 6'b10 : begin data_collision_b_a <= 2'b01; display_all_b_a; end + endcase + end + setup_all_b_a <= 0; + end + + task display_all_b_a; + begin + address_collision_b_a = 1'b0; + for (ci = 0; ci < 4; ci = ci + 2) begin + if ((mem_addra_int) == (mem_addrb_reg + ci)) begin + address_collision_b_a = 1'b1; + end + end + if (address_collision_b_a == 1'b1 && display_flag) + + if (({wea_int, web_reg}) == 2'b11) + $display("Memory Collision Error on RAMB4_S2_S4:%m at simulation time %.3f ns\nA write was requested to the same address simultaneously at both Port A and Port B of the RAM. The contents written to the RAM at address location %h (hex) of Port A and address location %h (hex) of Port B are unknown.", $time/1000.0, addra_int, addrb_int); + + else if (({wea_int, web_reg}) == 2'b01) + $display("Memory Collision Error on RAMB4_S2_S4:%m at simulation time %.3f ns\nA read was performed on address %h (hex) of Port A while a write was requested to the same address on Port B. The write will be successful however the read value on Port A is unknown until the next CLKA cycle.", $time/1000.0, addra_int); + + else if (({wea_int, web_reg}) == 2'b10) + $display("Memory Collision Error on RAMB4_S2_S4:%m at simulation time %.3f ns\nA read was performed on address %h (hex) of Port B while a write was requested to the same address on Port A. The write will be successful however the read value on Port B is unknown until the next CLKB cycle.", $time/1000.0, addrb_int); + + end + endtask + + always @(posedge setup_zero) begin + if ((ena_int == 1) && (enb_int == 1)) begin + case ({wea_int, web_int}) + 6'b11 : begin data_collision <= 2'b11; display_zero; end + 6'b01 : begin data_collision <= 2'b10; display_zero; end + 6'b10 : begin data_collision <= 2'b01; display_zero; end + endcase + end + setup_zero <= 0; + end + + task display_zero; + begin + address_collision = 1'b0; + for (ci = 0; ci < 4; ci = ci + 2) begin + if ((mem_addra_int) == (mem_addrb_int + ci)) begin + address_collision = 1'b1; + end + end + if (address_collision == 1'b1 && display_flag) + + if (({wea_int, web_int}) == 2'b11) + $display("Memory Collision Error on RAMB4_S2_S4:%m at simulation time %.3f ns\nA write was requested to the same address simultaneously at both Port A and Port B of the RAM. The contents written to the RAM at address location %h (hex) of Port A and address location %h (hex) of Port B are unknown.", $time/1000.0, addra_int, addrb_int); + + else if (({wea_int, web_int}) == 2'b01) + $display("Memory Collision Error on RAMB4_S2_S4:%m at simulation time %.3f ns\nA read was performed on address %h (hex) of Port A while a write was requested to the same address on Port B. The write will be successful however the read value on Port A is unknown until the next CLKA cycle.", $time/1000.0, addra_int); + + else if (({wea_int, web_int}) == 2'b10) + $display("Memory Collision Error on RAMB4_S2_S4:%m at simulation time %.3f ns\nA read was performed on address %h (hex) of Port B while a write was requested to the same address on Port A. The write will be successful however the read value on Port B is unknown until the next CLKB cycle.", $time/1000.0, addrb_int); + + end + endtask + + always @(posedge clka_int) begin + if ((output_flag || display_flag)) begin + addra_reg <= addra_int; + ena_reg <= ena_int; + rsta_reg <= rsta_int; + wea_reg <= wea_int; + end + end + + always @(posedge clkb_int) begin + if ((output_flag || display_flag)) begin + addrb_reg <= addrb_int; + enb_reg <= enb_int; + rstb_reg <= rstb_int; + web_reg <= web_int; + end + end + + + // Data + always @(posedge memory_collision) begin + if ((output_flag || display_flag)) begin + for (mi = 0; mi < 4; mi = mi + 2) begin + if ((mem_addra_int) == (mem_addrb_int + mi)) begin + mem[addra_int[10:1]][addra_int[0:0] * 2 +: 2] <= 2'bx; + end + end + memory_collision <= 0; + end + end + + always @(posedge memory_collision_a_b) begin + if ((output_flag || display_flag)) begin + for (mi = 0; mi < 4; mi = mi + 2) begin + if ((mem_addra_reg) == (mem_addrb_int + mi)) begin + mem[addra_reg[10:1]][addra_reg[0:0] * 2 +: 2] <= 2'bx; + end + end + memory_collision_a_b <= 0; + end + end + + always @(posedge memory_collision_b_a) begin + if ((output_flag || display_flag)) begin + for (mi = 0; mi < 4; mi = mi + 2) begin + if ((mem_addra_int) == (mem_addrb_reg + mi)) begin + mem[addra_int[10:1]][addra_int[0:0] * 2 +: 2] <= 2'bx; + end + end + memory_collision_b_a <= 0; + end + end + + always @(posedge data_collision[1]) begin + if (rsta_int == 0 && output_flag) begin + for (ai = 0; ai < 4; ai = ai + 2) begin + if ((mem_addra_int) == (mem_addrb_int + ai)) begin + doa_out <= #100 2'bX; + end + end + end + data_collision[1] <= 0; + end + + always @(posedge data_collision[0]) begin + if (rstb_int == 0 && output_flag) begin + for (bi = 0; bi < 4; bi = bi + 2) begin + if ((mem_addra_int) == (mem_addrb_int + bi)) begin + for (bj = 0; bj < 2; bj = bj + 1) begin + dob_out[bi + bj] <= #100 1'bX; + end + end + end + end + data_collision[0] <= 0; + end + + always @(posedge data_collision_a_b[1]) begin + if (rsta_reg == 0 && output_flag) begin + for (ai = 0; ai < 4; ai = ai + 2) begin + if ((mem_addra_reg) == (mem_addrb_int + ai)) begin + doa_out <= #100 2'bX; + end + end + end + data_collision_a_b[1] <= 0; + end + + always @(posedge data_collision_a_b[0]) begin + if (rstb_int == 0 && output_flag) begin + for (bi = 0; bi < 4; bi = bi + 2) begin + if ((mem_addra_reg) == (mem_addrb_int + bi)) begin + for (bj = 0; bj < 2; bj = bj + 1) begin + dob_out[bi + bj] <= #100 1'bX; + end + end + end + end + data_collision_a_b[0] <= 0; + end + + always @(posedge data_collision_b_a[1]) begin + if (rsta_int == 0 && output_flag) begin + for (ai = 0; ai < 4; ai = ai + 2) begin + if ((mem_addra_int) == (mem_addrb_reg + ai)) begin + doa_out <= #100 2'bX; + end + end + end + data_collision_b_a[1] <= 0; + end + + always @(posedge data_collision_b_a[0]) begin + if (rstb_reg == 0 && output_flag) begin + for (bi = 0; bi < 4; bi = bi + 2) begin + if ((mem_addra_int) == (mem_addrb_reg + bi)) begin + for (bj = 0; bj < 2; bj = bj + 1) begin + dob_out[bi + bj] <= #100 1'bX; + end + end + end + end + data_collision_b_a[0] <= 0; + end + + + // Port A + always @(posedge clka_int) begin + + if (ena_int == 1'b1) begin + + if (rsta_int == 1'b1) begin + doa_out <= #100 0; + end + else begin + if (wea_int == 1'b1) + doa_out <= #100 dia_int; + else + doa_out <= #100 mem[addra_int[10:1]][addra_int[0:0] * 2 +: 2]; + end + + // memory + if (wea_int == 1'b1) begin + mem[addra_int[10:1]][addra_int[0:0] * 2 +: 2] <= dia_int; + end + + end + end + + + // Port B + always @(posedge clkb_int) begin + + if (enb_int == 1'b1) begin + + if (rstb_int == 1'b1) begin + dob_out <= #100 0; + end + else begin + if (web_int == 1'b1) + dob_out <= #100 dib_int; + else + dob_out <= #100 mem[addrb_int]; + end + + // memory + if (web_int == 1'b1) begin + mem[addrb_int] <= dib_int; + end + + end + end + + +endmodule + +`endif diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/RAMB4_S2_S8.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/RAMB4_S2_S8.v new file mode 100644 index 0000000..414c2be --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/RAMB4_S2_S8.v @@ -0,0 +1,1075 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/RAMB4_S2_S8.v,v 1.9 2007/02/22 01:58:06 wloo Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2005 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / 4K-Bit Data Dual Port Block RAM +// /___/ /\ Filename : RAMB4_S2_S8.v +// \ \ / \ Timestamp : Thu Mar 10 16:43:38 PST 2005 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// End Revision + +`ifdef legacy_model + +`timescale 1 ps / 1 ps + +module RAMB4_S2_S8 (DOA, DOB, ADDRA, ADDRB, CLKA, CLKB, DIA, DIB, ENA, ENB, RSTA, RSTB, WEA, WEB); + + parameter SIM_COLLISION_CHECK = "ALL"; + localparam SETUP_ALL = 100; + + parameter INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + + output [1:0] DOA; + reg [1:0] doa_out; + wire doa_out0, doa_out1; + + input [10:0] ADDRA; + input [1:0] DIA; + input ENA, CLKA, WEA, RSTA; + + output [7:0] DOB; + reg [7:0] dob_out; + wire dob_out0, dob_out1, dob_out2, dob_out3, dob_out4, dob_out5, dob_out6, dob_out7; + + input [8:0] ADDRB; + input [7:0] DIB; + input ENB, CLKB, WEB, RSTB; + + reg [4095:0] mem; + reg [8:0] count; + + reg [5:0] mi, mj, ai, aj, bi, bj, ci, cj, di, dj, ei, ej, fi, fj; + + wire [10:0] addra_int; + reg [10:0] addra_reg; + wire [1:0] dia_int; + wire ena_int, clka_int, wea_int, rsta_int; + reg ena_reg, wea_reg, rsta_reg; + wire [8:0] addrb_int; + reg [8:0] addrb_reg; + wire [7:0] dib_int; + wire enb_int, clkb_int, web_int, rstb_int; + reg enb_reg, web_reg, rstb_reg; + + time time_clka, time_clkb; + time time_clka_clkb; + time time_clkb_clka; + + reg setup_all_a_b; + reg setup_all_b_a; + reg setup_zero; + reg [1:0] data_collision, data_collision_a_b, data_collision_b_a; + reg memory_collision, memory_collision_a_b, memory_collision_b_a; + reg address_collision, address_collision_a_b, address_collision_b_a; + reg change_clka; + reg change_clkb; + + wire [11:0] mem_addra_int; + wire [11:0] mem_addra_reg; + wire [11:0] mem_addrb_int; + wire [11:0] mem_addrb_reg; + + tri0 GSR = glbl.GSR; + + always @(GSR) + if (GSR) begin + assign doa_out = 0; + end + else begin + deassign doa_out; + end + + always @(GSR) + if (GSR) begin + assign dob_out = 0; + end + else begin + deassign dob_out; + end + + buf b_doa_out0 (doa_out0, doa_out[0]); + buf b_doa_out1 (doa_out1, doa_out[1]); + buf b_dob_out0 (dob_out0, dob_out[0]); + buf b_dob_out1 (dob_out1, dob_out[1]); + buf b_dob_out2 (dob_out2, dob_out[2]); + buf b_dob_out3 (dob_out3, dob_out[3]); + buf b_dob_out4 (dob_out4, dob_out[4]); + buf b_dob_out5 (dob_out5, dob_out[5]); + buf b_dob_out6 (dob_out6, dob_out[6]); + buf b_dob_out7 (dob_out7, dob_out[7]); + buf b_doa0 (DOA[0], doa_out0); + buf b_doa1 (DOA[1], doa_out1); + buf b_dob0 (DOB[0], dob_out0); + buf b_dob1 (DOB[1], dob_out1); + buf b_dob2 (DOB[2], dob_out2); + buf b_dob3 (DOB[3], dob_out3); + buf b_dob4 (DOB[4], dob_out4); + buf b_dob5 (DOB[5], dob_out5); + buf b_dob6 (DOB[6], dob_out6); + buf b_dob7 (DOB[7], dob_out7); + buf b_addra_0 (addra_int[0], ADDRA[0]); + buf b_addra_1 (addra_int[1], ADDRA[1]); + buf b_addra_2 (addra_int[2], ADDRA[2]); + buf b_addra_3 (addra_int[3], ADDRA[3]); + buf b_addra_4 (addra_int[4], ADDRA[4]); + buf b_addra_5 (addra_int[5], ADDRA[5]); + buf b_addra_6 (addra_int[6], ADDRA[6]); + buf b_addra_7 (addra_int[7], ADDRA[7]); + buf b_addra_8 (addra_int[8], ADDRA[8]); + buf b_addra_9 (addra_int[9], ADDRA[9]); + buf b_addra_10 (addra_int[10], ADDRA[10]); + buf b_dia_0 (dia_int[0], DIA[0]); + buf b_dia_1 (dia_int[1], DIA[1]); + buf b_clka (clka_int, CLKA); + buf b_ena (ena_int, ENA); + buf b_rsta (rsta_int, RSTA); + buf b_wea (wea_int, WEA); + buf b_addrb_0 (addrb_int[0], ADDRB[0]); + buf b_addrb_1 (addrb_int[1], ADDRB[1]); + buf b_addrb_2 (addrb_int[2], ADDRB[2]); + buf b_addrb_3 (addrb_int[3], ADDRB[3]); + buf b_addrb_4 (addrb_int[4], ADDRB[4]); + buf b_addrb_5 (addrb_int[5], ADDRB[5]); + buf b_addrb_6 (addrb_int[6], ADDRB[6]); + buf b_addrb_7 (addrb_int[7], ADDRB[7]); + buf b_addrb_8 (addrb_int[8], ADDRB[8]); + buf b_dib_0 (dib_int[0], DIB[0]); + buf b_dib_1 (dib_int[1], DIB[1]); + buf b_dib_2 (dib_int[2], DIB[2]); + buf b_dib_3 (dib_int[3], DIB[3]); + buf b_dib_4 (dib_int[4], DIB[4]); + buf b_dib_5 (dib_int[5], DIB[5]); + buf b_dib_6 (dib_int[6], DIB[6]); + buf b_dib_7 (dib_int[7], DIB[7]); + buf b_clkb (clkb_int, CLKB); + buf b_enb (enb_int, ENB); + buf b_rstb (rstb_int, RSTB); + buf b_web (web_int, WEB); + + initial begin + for (count = 0; count < 256; count = count + 1) begin + mem[count] <= INIT_00[count]; + mem[256 * 1 + count] <= INIT_01[count]; + mem[256 * 2 + count] <= INIT_02[count]; + mem[256 * 3 + count] <= INIT_03[count]; + mem[256 * 4 + count] <= INIT_04[count]; + mem[256 * 5 + count] <= INIT_05[count]; + mem[256 * 6 + count] <= INIT_06[count]; + mem[256 * 7 + count] <= INIT_07[count]; + mem[256 * 8 + count] <= INIT_08[count]; + mem[256 * 9 + count] <= INIT_09[count]; + mem[256 * 10 + count] <= INIT_0A[count]; + mem[256 * 11 + count] <= INIT_0B[count]; + mem[256 * 12 + count] <= INIT_0C[count]; + mem[256 * 13 + count] <= INIT_0D[count]; + mem[256 * 14 + count] <= INIT_0E[count]; + mem[256 * 15 + count] <= INIT_0F[count]; + end + address_collision <= 0; + address_collision_a_b <= 0; + address_collision_b_a <= 0; + change_clka <= 0; + change_clkb <= 0; + data_collision <= 0; + data_collision_a_b <= 0; + data_collision_b_a <= 0; + memory_collision <= 0; + memory_collision_a_b <= 0; + memory_collision_b_a <= 0; + setup_all_a_b <= 0; + setup_all_b_a <= 0; + setup_zero <= 0; + end + + assign mem_addra_int = addra_int * 2; + assign mem_addra_reg = addra_reg * 2; + assign mem_addrb_int = addrb_int * 8; + assign mem_addrb_reg = addrb_reg * 8; + + + initial begin + + case (SIM_COLLISION_CHECK) + + "NONE" : begin + assign setup_all_a_b = 1'b0; + assign setup_all_b_a = 1'b0; + assign setup_zero = 1'b0; + assign address_collision = 1'b0; + assign address_collision_a_b = 1'b0; + assign address_collision_b_a = 1'b0; + end + "WARNING_ONLY" : begin + assign data_collision = 2'b00; + assign data_collision_a_b = 2'b00; + assign data_collision_b_a = 2'b00; + assign memory_collision = 1'b0; + assign memory_collision_a_b = 1'b0; + assign memory_collision_b_a = 1'b0; + end + "GENERATE_X_ONLY" : begin + assign address_collision = 1'b0; + assign address_collision_a_b = 1'b0; + assign address_collision_b_a = 1'b0; + end + "ALL" : ; + default : begin + $display("Attribute Syntax Error : The Attribute SIM_COLLISION_CHECK on RAMB4_S2_S8 instance %m is set to %s. Legal values for this attribute are ALL, NONE, WARNING_ONLY or GENERATE_X_ONLY.", SIM_COLLISION_CHECK); + $finish; + end + + endcase // case(SIM_COLLISION_CHECK) + + end // initial begin + + + always @(posedge clka_int) begin + time_clka = $time; + #0 time_clkb_clka = time_clka - time_clkb; + change_clka = ~change_clka; + end + + always @(posedge clkb_int) begin + time_clkb = $time; + #0 time_clka_clkb = time_clkb - time_clka; + change_clkb = ~change_clkb; + end + + always @(change_clkb) begin + if ((0 < time_clka_clkb) && (time_clka_clkb < SETUP_ALL)) + setup_all_a_b = 1; + end + + always @(change_clka) begin + if ((0 < time_clkb_clka) && (time_clkb_clka < SETUP_ALL)) + setup_all_b_a = 1; + end + + always @(change_clkb or change_clka) begin + if ((time_clkb_clka == 0) && (time_clka_clkb == 0)) + setup_zero = 1; + end + + always @(posedge setup_zero) begin + if ((ena_int == 1) && (wea_int == 1) && + (enb_int == 1) && (web_int == 1)) + memory_collision <= 1; + end + + always @(posedge setup_all_a_b) begin + if ((ena_reg == 1) && (enb_int == 1)) begin + case ({wea_reg, web_int}) + 6'b11 : begin data_collision_a_b <= 2'b11; display_all_a_b; end + 6'b01 : begin data_collision_a_b <= 2'b10; display_all_a_b; end + 6'b10 : begin data_collision_a_b <= 2'b01; display_all_a_b; end + endcase + end + setup_all_a_b <= 0; + end + + task display_all_a_b; + begin + address_collision_a_b = 1'b0; + for (ci = 0; ci < 8; ci = ci + 2) begin + if ((mem_addra_reg) == (mem_addrb_int + ci)) begin + address_collision_a_b = 1'b1; + end + end + if (address_collision_a_b == 1'b1) + + if (({wea_reg, web_int}) == 2'b11) + $display("Memory Collision Error on RAMB4_S2_S8:%m at simulation time %.3f ns\nA write was requested to the same address simultaneously at both Port A and Port B of the RAM. The contents written to the RAM at address location %h (hex) of Port A and address location %h (hex) of Port B are unknown.", $time/1000.0, addra_int, addrb_int); + + else if (({wea_reg, web_int}) == 2'b01) + $display("Memory Collision Error on RAMB4_S2_S8:%m at simulation time %.3f ns\nA read was performed on address %h (hex) of Port A while a write was requested to the same address on Port B. The write will be successful however the read value on Port A is unknown until the next CLKA cycle.", $time/1000.0, addra_int); + + else if (({wea_reg, web_int}) == 2'b10) + $display("Memory Collision Error on RAMB4_S2_S8:%m at simulation time %.3f ns\nA read was performed on address %h (hex) of Port B while a write was requested to the same address on Port A. The write will be successful however the read value on Port B is unknown until the next CLKB cycle.", $time/1000.0, addrb_int); + + end + endtask + + always @(posedge setup_all_b_a) begin + if ((ena_int == 1) && (enb_reg == 1)) begin + case ({wea_int, web_reg}) + 6'b11 : begin data_collision_b_a <= 2'b11; display_all_b_a; end + 6'b01 : begin data_collision_b_a <= 2'b10; display_all_b_a; end + 6'b10 : begin data_collision_b_a <= 2'b01; display_all_b_a; end + endcase + end + setup_all_b_a <= 0; + end + + task display_all_b_a; + begin + address_collision_b_a = 1'b0; + for (ci = 0; ci < 8; ci = ci + 2) begin + if ((mem_addra_int) == (mem_addrb_reg + ci)) begin + address_collision_b_a = 1'b1; + end + end + if (address_collision_b_a == 1'b1) + + if (({wea_int, web_reg}) == 2'b11) + $display("Memory Collision Error on RAMB4_S2_S8:%m at simulation time %.3f ns\nA write was requested to the same address simultaneously at both Port A and Port B of the RAM. The contents written to the RAM at address location %h (hex) of Port A and address location %h (hex) of Port B are unknown.", $time/1000.0, addra_int, addrb_int); + + else if (({wea_int, web_reg}) == 2'b01) + $display("Memory Collision Error on RAMB4_S2_S8:%m at simulation time %.3f ns\nA read was performed on address %h (hex) of Port A while a write was requested to the same address on Port B. The write will be successful however the read value on Port A is unknown until the next CLKA cycle.", $time/1000.0, addra_int); + + else if (({wea_int, web_reg}) == 2'b10) + $display("Memory Collision Error on RAMB4_S2_S8:%m at simulation time %.3f ns\nA read was performed on address %h (hex) of Port B while a write was requested to the same address on Port A. The write will be successful however the read value on Port B is unknown until the next CLKB cycle.", $time/1000.0, addrb_int); + + end + endtask + + always @(posedge setup_zero) begin + if ((ena_int == 1) && (enb_int == 1)) begin + case ({wea_int, web_int}) + 6'b11 : begin data_collision <= 2'b11; display_zero; end + 6'b01 : begin data_collision <= 2'b10; display_zero; end + 6'b10 : begin data_collision <= 2'b01; display_zero; end + endcase + end + setup_zero <= 0; + end + + task display_zero; + begin + address_collision = 1'b0; + for (ci = 0; ci < 8; ci = ci + 2) begin + if ((mem_addra_int) == (mem_addrb_int + ci)) begin + address_collision = 1'b1; + end + end + if (address_collision == 1'b1) + + if (({wea_int, web_int}) == 2'b11) + $display("Memory Collision Error on RAMB4_S2_S8:%m at simulation time %.3f ns\nA write was requested to the same address simultaneously at both Port A and Port B of the RAM. The contents written to the RAM at address location %h (hex) of Port A and address location %h (hex) of Port B are unknown.", $time/1000.0, addra_int, addrb_int); + + else if (({wea_int, web_int}) == 2'b01) + $display("Memory Collision Error on RAMB4_S2_S8:%m at simulation time %.3f ns\nA read was performed on address %h (hex) of Port A while a write was requested to the same address on Port B. The write will be successful however the read value on Port A is unknown until the next CLKA cycle.", $time/1000.0, addra_int); + + else if (({wea_int, web_int}) == 2'b10) + $display("Memory Collision Error on RAMB4_S2_S8:%m at simulation time %.3f ns\nA read was performed on address %h (hex) of Port B while a write was requested to the same address on Port A. The write will be successful however the read value on Port B is unknown until the next CLKB cycle.", $time/1000.0, addrb_int); + + end + endtask + + always @(posedge clka_int) begin + addra_reg <= addra_int; + ena_reg <= ena_int; + rsta_reg <= rsta_int; + wea_reg <= wea_int; + end + + always @(posedge clkb_int) begin + addrb_reg <= addrb_int; + enb_reg <= enb_int; + rstb_reg <= rstb_int; + web_reg <= web_int; + end + + // Data + always @(posedge memory_collision) begin + for (mi = 0; mi < 8; mi = mi + 2) begin + if ((mem_addra_int) == (mem_addrb_int + mi)) begin + for (mj = 0; mj < 2; mj = mj + 1) begin + mem[mem_addrb_int + mi + mj] <= 1'bX; + end + end + end + memory_collision <= 0; + end + + always @(posedge memory_collision_a_b) begin + for (mi = 0; mi < 8; mi = mi + 2) begin + if ((mem_addra_reg) == (mem_addrb_int + mi)) begin + for (mj = 0; mj < 2; mj = mj + 1) begin + mem[mem_addrb_int + mi + mj] <= 1'bX; + end + end + end + memory_collision_a_b <= 0; + end + + always @(posedge memory_collision_b_a) begin + for (mi = 0; mi < 8; mi = mi + 2) begin + if ((mem_addra_int) == (mem_addrb_reg + mi)) begin + for (mj = 0; mj < 2; mj = mj + 1) begin + mem[mem_addrb_reg + mi + mj] <= 1'bX; + end + end + end + memory_collision_b_a <= 0; + end + + always @(posedge data_collision[1]) begin + if (rsta_int == 0) begin + for (ai = 0; ai < 8; ai = ai + 2) begin + if ((mem_addra_int) == (mem_addrb_int + ai)) begin + doa_out <= 2'bX; + end + end + end + data_collision[1] <= 0; + end + + always @(posedge data_collision[0]) begin + if (rstb_int == 0) begin + for (bi = 0; bi < 8; bi = bi + 2) begin + if ((mem_addra_int) == (mem_addrb_int + bi)) begin + for (bj = 0; bj < 2; bj = bj + 1) begin + dob_out[bi + bj] <= 1'bX; + end + end + end + end + data_collision[0] <= 0; + end + + always @(posedge data_collision_a_b[1]) begin + if (rsta_reg == 0) begin + for (ai = 0; ai < 8; ai = ai + 2) begin + if ((mem_addra_reg) == (mem_addrb_int + ai)) begin + doa_out <= 2'bX; + end + end + end + data_collision_a_b[1] <= 0; + end + + always @(posedge data_collision_a_b[0]) begin + if (rstb_int == 0) begin + for (bi = 0; bi < 8; bi = bi + 2) begin + if ((mem_addra_reg) == (mem_addrb_int + bi)) begin + for (bj = 0; bj < 2; bj = bj + 1) begin + dob_out[bi + bj] <= 1'bX; + end + end + end + end + data_collision_a_b[0] <= 0; + end + + always @(posedge data_collision_b_a[1]) begin + if (rsta_int == 0) begin + for (ai = 0; ai < 8; ai = ai + 2) begin + if ((mem_addra_int) == (mem_addrb_reg + ai)) begin + doa_out <= 2'bX; + end + end + end + data_collision_b_a[1] <= 0; + end + + always @(posedge data_collision_b_a[0]) begin + if (rstb_reg == 0) begin + for (bi = 0; bi < 8; bi = bi + 2) begin + if ((mem_addra_int) == (mem_addrb_reg + bi)) begin + for (bj = 0; bj < 2; bj = bj + 1) begin + dob_out[bi + bj] <= 1'bX; + end + end + end + end + data_collision_b_a[0] <= 0; + end + + + always @(posedge clka_int) begin + if (ena_int == 1'b1) begin + if (rsta_int == 1'b1) begin + doa_out <= 2'b0; + end + else if (wea_int == 0) begin + doa_out[0] <= mem[mem_addra_int + 0]; + doa_out[1] <= mem[mem_addra_int + 1]; + end + else begin + doa_out <= dia_int; + end + end + end + + always @(posedge clka_int) begin + if (ena_int == 1'b1 && wea_int == 1'b1) begin + mem[mem_addra_int + 0] <= dia_int[0]; + mem[mem_addra_int + 1] <= dia_int[1]; + end + end + + always @(posedge clkb_int) begin + if (enb_int == 1'b1) begin + if (rstb_int == 1'b1) begin + dob_out <= 8'b0; + end + else if (web_int == 0) begin + dob_out[0] <= mem[mem_addrb_int + 0]; + dob_out[1] <= mem[mem_addrb_int + 1]; + dob_out[2] <= mem[mem_addrb_int + 2]; + dob_out[3] <= mem[mem_addrb_int + 3]; + dob_out[4] <= mem[mem_addrb_int + 4]; + dob_out[5] <= mem[mem_addrb_int + 5]; + dob_out[6] <= mem[mem_addrb_int + 6]; + dob_out[7] <= mem[mem_addrb_int + 7]; + end + else begin + dob_out <= dib_int; + end + end + end + + always @(posedge clkb_int) begin + if (enb_int == 1'b1 && web_int == 1'b1) begin + mem[mem_addrb_int + 0] <= dib_int[0]; + mem[mem_addrb_int + 1] <= dib_int[1]; + mem[mem_addrb_int + 2] <= dib_int[2]; + mem[mem_addrb_int + 3] <= dib_int[3]; + mem[mem_addrb_int + 4] <= dib_int[4]; + mem[mem_addrb_int + 5] <= dib_int[5]; + mem[mem_addrb_int + 6] <= dib_int[6]; + mem[mem_addrb_int + 7] <= dib_int[7]; + end + end + + specify + (CLKA *> DOA) = (100, 100); + (CLKB *> DOB) = (100, 100); + endspecify + +endmodule + +`else + +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/RAMB4_S2_S8.v,v 1.9 2007/02/22 01:58:06 wloo Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2005 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Timing Simulation Library Component +// / / 16K-Bit Data and 2K-Bit Parity Dual Port Block RAM +// /___/ /\ Filename : RAMB4_S2_S8.v +// \ \ / \ Timestamp : Thu Mar 10 16:44:01 PST 2005 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 03/10/05 - Initialized outputs. +// 02/21/07 - Fixed parameter SIM_COLLISION_CHECK (CR 433281). +// End Revision + +`timescale 1 ps/1 ps + +module RAMB4_S2_S8 (DOA, DOB, ADDRA, ADDRB, CLKA, CLKB, DIA, DIB, ENA, ENB, RSTA, RSTB, WEA, WEB); + + parameter SIM_COLLISION_CHECK = "ALL"; + localparam SETUP_ALL = 100; + + parameter INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + + output [1:0] DOA; + output [7:0] DOB; + + input [10:0] ADDRA; + input [1:0] DIA; + input ENA, CLKA, WEA, RSTA; + input [8:0] ADDRB; + input [7:0] DIB; + input ENB, CLKB, WEB, RSTB; + + reg [1:0] doa_out = 0; + reg [7:0] dob_out = 0; + + reg [7:0] mem [511:0]; + + reg [8:0] count; + + reg [5:0] mi, ai, bi, bj, ci; + + wire [10:0] addra_int; + reg [10:0] addra_reg; + wire [1:0] dia_int; + wire ena_int, clka_int, wea_int, rsta_int; + reg ena_reg, wea_reg, rsta_reg; + wire [8:0] addrb_int; + reg [8:0] addrb_reg; + wire [7:0] dib_int; + wire enb_int, clkb_int, web_int, rstb_int; + reg display_flag, output_flag; + reg enb_reg, web_reg, rstb_reg; + + time time_clka, time_clkb; + time time_clka_clkb; + time time_clkb_clka; + + reg setup_all_a_b; + reg setup_all_b_a; + reg setup_zero; + reg [1:0] data_collision, data_collision_a_b, data_collision_b_a; + reg memory_collision, memory_collision_a_b, memory_collision_b_a; + reg address_collision, address_collision_a_b, address_collision_b_a; + reg change_clka; + reg change_clkb; + + wire [11:0] mem_addra_int; + wire [11:0] mem_addra_reg; + wire [11:0] mem_addrb_int; + wire [11:0] mem_addrb_reg; + + wire dia_enable = ena_int && wea_int; + wire dib_enable = enb_int && web_int; + + tri0 GSR = glbl.GSR; + wire gsr_int; + + buf b_gsr (gsr_int, GSR); + + buf b_doa [1:0] (DOA, doa_out); + buf b_addra [10:0] (addra_int, ADDRA); + buf b_dia [1:0] (dia_int, DIA); + buf b_ena (ena_int, ENA); + buf b_clka (clka_int, CLKA); + buf b_rsta (rsta_int, RSTA); + buf b_wea (wea_int, WEA); + + buf b_dob [7:0] (DOB, dob_out); + buf b_addrb [8:0] (addrb_int, ADDRB); + buf b_dib [7:0] (dib_int, DIB); + buf b_enb (enb_int, ENB); + buf b_clkb (clkb_int, CLKB); + buf b_rstb (rstb_int, RSTB); + buf b_web (web_int, WEB); + + + always @(gsr_int) + if (gsr_int) begin + assign doa_out = 0; + assign dob_out = 0; + end + else begin + deassign doa_out; + deassign dob_out; + end + + + initial begin + + for (count = 0; count < 32; count = count + 1) begin + mem[count] = INIT_00[(count * 8) +: 8]; + mem[32 * 1 + count] = INIT_01[(count * 8) +: 8]; + mem[32 * 2 + count] = INIT_02[(count * 8) +: 8]; + mem[32 * 3 + count] = INIT_03[(count * 8) +: 8]; + mem[32 * 4 + count] = INIT_04[(count * 8) +: 8]; + mem[32 * 5 + count] = INIT_05[(count * 8) +: 8]; + mem[32 * 6 + count] = INIT_06[(count * 8) +: 8]; + mem[32 * 7 + count] = INIT_07[(count * 8) +: 8]; + mem[32 * 8 + count] = INIT_08[(count * 8) +: 8]; + mem[32 * 9 + count] = INIT_09[(count * 8) +: 8]; + mem[32 * 10 + count] = INIT_0A[(count * 8) +: 8]; + mem[32 * 11 + count] = INIT_0B[(count * 8) +: 8]; + mem[32 * 12 + count] = INIT_0C[(count * 8) +: 8]; + mem[32 * 13 + count] = INIT_0D[(count * 8) +: 8]; + mem[32 * 14 + count] = INIT_0E[(count * 8) +: 8]; + mem[32 * 15 + count] = INIT_0F[(count * 8) +: 8]; + end + + change_clka <= 0; + change_clkb <= 0; + data_collision <= 0; + data_collision_a_b <= 0; + data_collision_b_a <= 0; + memory_collision <= 0; + memory_collision_a_b <= 0; + memory_collision_b_a <= 0; + setup_all_a_b <= 0; + setup_all_b_a <= 0; + setup_zero <= 0; + end + + assign mem_addra_int = addra_int * 2; + assign mem_addra_reg = addra_reg * 2; + assign mem_addrb_int = addrb_int * 8; + assign mem_addrb_reg = addrb_reg * 8; + + + initial begin + + display_flag = 1; + output_flag = 1; + + case (SIM_COLLISION_CHECK) + + "NONE" : begin + output_flag = 0; + display_flag = 0; + end + "WARNING_ONLY" : output_flag = 0; + "GENERATE_X_ONLY" : display_flag = 0; + "ALL" : ; + + default : begin + $display("Attribute Syntax Error : The Attribute SIM_COLLISION_CHECK on RAMB4_S2_S8 instance %m is set to %s. Legal values for this attribute are ALL, NONE, WARNING_ONLY or GENERATE_X_ONLY.", SIM_COLLISION_CHECK); + $finish; + end + + endcase // case(SIM_COLLISION_CHECK) + + end // initial begin + + + always @(posedge clka_int) begin + if ((output_flag || display_flag)) begin + time_clka = $time; + #0 time_clkb_clka = time_clka - time_clkb; + change_clka = ~change_clka; + end + end + + always @(posedge clkb_int) begin + if ((output_flag || display_flag)) begin + time_clkb = $time; + #0 time_clka_clkb = time_clkb - time_clka; + change_clkb = ~change_clkb; + end + end + + always @(change_clkb) begin + if ((0 < time_clka_clkb) && (time_clka_clkb < SETUP_ALL)) + setup_all_a_b = 1; + end + + always @(change_clka) begin + if ((0 < time_clkb_clka) && (time_clkb_clka < SETUP_ALL)) + setup_all_b_a = 1; + end + + always @(change_clkb or change_clka) begin + if ((time_clkb_clka == 0) && (time_clka_clkb == 0)) + setup_zero = 1; + end + + always @(posedge setup_zero) begin + if ((ena_int == 1) && (wea_int == 1) && + (enb_int == 1) && (web_int == 1)) + memory_collision <= 1; + end + + always @(posedge setup_all_a_b) begin + if ((ena_reg == 1) && (enb_int == 1)) begin + case ({wea_reg, web_int}) + 6'b11 : begin data_collision_a_b <= 2'b11; display_all_a_b; end + 6'b01 : begin data_collision_a_b <= 2'b10; display_all_a_b; end + 6'b10 : begin data_collision_a_b <= 2'b01; display_all_a_b; end + endcase + end + setup_all_a_b <= 0; + end + + task display_all_a_b; + begin + address_collision_a_b = 1'b0; + for (ci = 0; ci < 8; ci = ci + 2) begin + if ((mem_addra_reg) == (mem_addrb_int + ci)) begin + address_collision_a_b = 1'b1; + end + end + if (address_collision_a_b == 1'b1 && display_flag) + + if (({wea_reg, web_int}) == 2'b11) + $display("Memory Collision Error on RAMB4_S2_S8:%m at simulation time %.3f ns\nA write was requested to the same address simultaneously at both Port A and Port B of the RAM. The contents written to the RAM at address location %h (hex) of Port A and address location %h (hex) of Port B are unknown.", $time/1000.0, addra_int, addrb_int); + + else if (({wea_reg, web_int}) == 2'b01) + $display("Memory Collision Error on RAMB4_S2_S8:%m at simulation time %.3f ns\nA read was performed on address %h (hex) of Port A while a write was requested to the same address on Port B. The write will be successful however the read value on Port A is unknown until the next CLKA cycle.", $time/1000.0, addra_int); + + else if (({wea_reg, web_int}) == 2'b10) + $display("Memory Collision Error on RAMB4_S2_S8:%m at simulation time %.3f ns\nA read was performed on address %h (hex) of Port B while a write was requested to the same address on Port A. The write will be successful however the read value on Port B is unknown until the next CLKB cycle.", $time/1000.0, addrb_int); + + end + endtask + + always @(posedge setup_all_b_a) begin + if ((ena_int == 1) && (enb_reg == 1)) begin + case ({wea_int, web_reg}) + 6'b11 : begin data_collision_b_a <= 2'b11; display_all_b_a; end + 6'b01 : begin data_collision_b_a <= 2'b10; display_all_b_a; end + 6'b10 : begin data_collision_b_a <= 2'b01; display_all_b_a; end + endcase + end + setup_all_b_a <= 0; + end + + task display_all_b_a; + begin + address_collision_b_a = 1'b0; + for (ci = 0; ci < 8; ci = ci + 2) begin + if ((mem_addra_int) == (mem_addrb_reg + ci)) begin + address_collision_b_a = 1'b1; + end + end + if (address_collision_b_a == 1'b1 && display_flag) + + if (({wea_int, web_reg}) == 2'b11) + $display("Memory Collision Error on RAMB4_S2_S8:%m at simulation time %.3f ns\nA write was requested to the same address simultaneously at both Port A and Port B of the RAM. The contents written to the RAM at address location %h (hex) of Port A and address location %h (hex) of Port B are unknown.", $time/1000.0, addra_int, addrb_int); + + else if (({wea_int, web_reg}) == 2'b01) + $display("Memory Collision Error on RAMB4_S2_S8:%m at simulation time %.3f ns\nA read was performed on address %h (hex) of Port A while a write was requested to the same address on Port B. The write will be successful however the read value on Port A is unknown until the next CLKA cycle.", $time/1000.0, addra_int); + + else if (({wea_int, web_reg}) == 2'b10) + $display("Memory Collision Error on RAMB4_S2_S8:%m at simulation time %.3f ns\nA read was performed on address %h (hex) of Port B while a write was requested to the same address on Port A. The write will be successful however the read value on Port B is unknown until the next CLKB cycle.", $time/1000.0, addrb_int); + + end + endtask + + always @(posedge setup_zero) begin + if ((ena_int == 1) && (enb_int == 1)) begin + case ({wea_int, web_int}) + 6'b11 : begin data_collision <= 2'b11; display_zero; end + 6'b01 : begin data_collision <= 2'b10; display_zero; end + 6'b10 : begin data_collision <= 2'b01; display_zero; end + endcase + end + setup_zero <= 0; + end + + task display_zero; + begin + address_collision = 1'b0; + for (ci = 0; ci < 8; ci = ci + 2) begin + if ((mem_addra_int) == (mem_addrb_int + ci)) begin + address_collision = 1'b1; + end + end + if (address_collision == 1'b1 && display_flag) + + if (({wea_int, web_int}) == 2'b11) + $display("Memory Collision Error on RAMB4_S2_S8:%m at simulation time %.3f ns\nA write was requested to the same address simultaneously at both Port A and Port B of the RAM. The contents written to the RAM at address location %h (hex) of Port A and address location %h (hex) of Port B are unknown.", $time/1000.0, addra_int, addrb_int); + + else if (({wea_int, web_int}) == 2'b01) + $display("Memory Collision Error on RAMB4_S2_S8:%m at simulation time %.3f ns\nA read was performed on address %h (hex) of Port A while a write was requested to the same address on Port B. The write will be successful however the read value on Port A is unknown until the next CLKA cycle.", $time/1000.0, addra_int); + + else if (({wea_int, web_int}) == 2'b10) + $display("Memory Collision Error on RAMB4_S2_S8:%m at simulation time %.3f ns\nA read was performed on address %h (hex) of Port B while a write was requested to the same address on Port A. The write will be successful however the read value on Port B is unknown until the next CLKB cycle.", $time/1000.0, addrb_int); + + end + endtask + + always @(posedge clka_int) begin + if ((output_flag || display_flag)) begin + addra_reg <= addra_int; + ena_reg <= ena_int; + rsta_reg <= rsta_int; + wea_reg <= wea_int; + end + end + + always @(posedge clkb_int) begin + if ((output_flag || display_flag)) begin + addrb_reg <= addrb_int; + enb_reg <= enb_int; + rstb_reg <= rstb_int; + web_reg <= web_int; + end + end + + + // Data + always @(posedge memory_collision) begin + if ((output_flag || display_flag)) begin + for (mi = 0; mi < 8; mi = mi + 2) begin + if ((mem_addra_int) == (mem_addrb_int + mi)) begin + mem[addra_int[10:2]][addra_int[1:0] * 2 +: 2] <= 2'bx; + end + end + memory_collision <= 0; + end + end + + always @(posedge memory_collision_a_b) begin + if ((output_flag || display_flag)) begin + for (mi = 0; mi < 8; mi = mi + 2) begin + if ((mem_addra_reg) == (mem_addrb_int + mi)) begin + mem[addra_reg[10:2]][addra_reg[1:0] * 2 +: 2] <= 2'bx; + end + end + memory_collision_a_b <= 0; + end + end + + always @(posedge memory_collision_b_a) begin + if ((output_flag || display_flag)) begin + for (mi = 0; mi < 8; mi = mi + 2) begin + if ((mem_addra_int) == (mem_addrb_reg + mi)) begin + mem[addra_int[10:2]][addra_int[1:0] * 2 +: 2] <= 2'bx; + end + end + memory_collision_b_a <= 0; + end + end + + always @(posedge data_collision[1]) begin + if (rsta_int == 0 && output_flag) begin + for (ai = 0; ai < 8; ai = ai + 2) begin + if ((mem_addra_int) == (mem_addrb_int + ai)) begin + doa_out <= #100 2'bX; + end + end + end + data_collision[1] <= 0; + end + + always @(posedge data_collision[0]) begin + if (rstb_int == 0 && output_flag) begin + for (bi = 0; bi < 8; bi = bi + 2) begin + if ((mem_addra_int) == (mem_addrb_int + bi)) begin + for (bj = 0; bj < 2; bj = bj + 1) begin + dob_out[bi + bj] <= #100 1'bX; + end + end + end + end + data_collision[0] <= 0; + end + + always @(posedge data_collision_a_b[1]) begin + if (rsta_reg == 0 && output_flag) begin + for (ai = 0; ai < 8; ai = ai + 2) begin + if ((mem_addra_reg) == (mem_addrb_int + ai)) begin + doa_out <= #100 2'bX; + end + end + end + data_collision_a_b[1] <= 0; + end + + always @(posedge data_collision_a_b[0]) begin + if (rstb_int == 0 && output_flag) begin + for (bi = 0; bi < 8; bi = bi + 2) begin + if ((mem_addra_reg) == (mem_addrb_int + bi)) begin + for (bj = 0; bj < 2; bj = bj + 1) begin + dob_out[bi + bj] <= #100 1'bX; + end + end + end + end + data_collision_a_b[0] <= 0; + end + + always @(posedge data_collision_b_a[1]) begin + if (rsta_int == 0 && output_flag) begin + for (ai = 0; ai < 8; ai = ai + 2) begin + if ((mem_addra_int) == (mem_addrb_reg + ai)) begin + doa_out <= #100 2'bX; + end + end + end + data_collision_b_a[1] <= 0; + end + + always @(posedge data_collision_b_a[0]) begin + if (rstb_reg == 0 && output_flag) begin + for (bi = 0; bi < 8; bi = bi + 2) begin + if ((mem_addra_int) == (mem_addrb_reg + bi)) begin + for (bj = 0; bj < 2; bj = bj + 1) begin + dob_out[bi + bj] <= #100 1'bX; + end + end + end + end + data_collision_b_a[0] <= 0; + end + + + // Port A + always @(posedge clka_int) begin + + if (ena_int == 1'b1) begin + + if (rsta_int == 1'b1) begin + doa_out <= #100 0; + end + else begin + if (wea_int == 1'b1) + doa_out <= #100 dia_int; + else + doa_out <= #100 mem[addra_int[10:2]][addra_int[1:0] * 2 +: 2]; + end + + // memory + if (wea_int == 1'b1) begin + mem[addra_int[10:2]][addra_int[1:0] * 2 +: 2] <= dia_int; + end + + end + end + + + // Port B + always @(posedge clkb_int) begin + + if (enb_int == 1'b1) begin + + if (rstb_int == 1'b1) begin + dob_out <= #100 0; + end + else begin + if (web_int == 1'b1) + dob_out <= #100 dib_int; + else + dob_out <= #100 mem[addrb_int]; + end + + // memory + if (web_int == 1'b1) begin + mem[addrb_int] <= dib_int; + end + + end + end + + +endmodule + +`endif diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/RAMB4_S4.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/RAMB4_S4.v new file mode 100644 index 0000000..4fb552d --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/RAMB4_S4.v @@ -0,0 +1,299 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/RAMB4_S4.v,v 1.6 2005/03/14 22:54:42 wloo Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2005 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / 4K-Bit Data Single Port Block RAM +// /___/ /\ Filename : RAMB4_S4.v +// \ \ / \ Timestamp : Thu Mar 10 16:43:39 PST 2005 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// End Revision + +`ifdef legacy_model + +`timescale 1 ps / 1 ps + + +module RAMB4_S4 (DO, ADDR, CLK, DI, EN, RST, WE); + + parameter INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + + output [3:0] DO; + reg d0_out, d1_out, d2_out, d3_out; + + input [9:0] ADDR; + input [3:0] DI; + input EN, CLK, WE, RST; + + reg [4095:0] mem; + reg [8:0] count; + + wire [9:0] addr_int; + wire [3:0] di_int; + wire en_int, clk_int, we_int, rst_int; + + tri0 GSR = glbl.GSR; + + always @(GSR) + if (GSR) + begin + assign d0_out = 0; + assign d1_out = 0; + assign d2_out = 0; + assign d3_out = 0; + end + else + begin + deassign d0_out; + deassign d1_out; + deassign d2_out; + deassign d3_out; + end + + buf b_do_out0 (DO[0], d0_out); + buf b_do_out1 (DO[1], d1_out); + buf b_do_out2 (DO[2], d2_out); + buf b_do_out3 (DO[3], d3_out); + buf b_addr_0 (addr_int[0], ADDR[0]); + buf b_addr_1 (addr_int[1], ADDR[1]); + buf b_addr_2 (addr_int[2], ADDR[2]); + buf b_addr_3 (addr_int[3], ADDR[3]); + buf b_addr_4 (addr_int[4], ADDR[4]); + buf b_addr_5 (addr_int[5], ADDR[5]); + buf b_addr_6 (addr_int[6], ADDR[6]); + buf b_addr_7 (addr_int[7], ADDR[7]); + buf b_addr_8 (addr_int[8], ADDR[8]); + buf b_addr_9 (addr_int[9], ADDR[9]); + buf b_di_0 (di_int[0], DI[0]); + buf b_di_1 (di_int[1], DI[1]); + buf b_di_2 (di_int[2], DI[2]); + buf b_di_3 (di_int[3], DI[3]); + buf b_en (en_int, EN); + buf b_clk (clk_int, CLK); + buf b_we (we_int, WE); + buf b_rst (rst_int, RST); + + initial + begin + for (count = 0; count < 256; count = count + 1) + begin + mem[count] <= INIT_00[count]; + mem[256 * 1 + count] <= INIT_01[count]; + mem[256 * 2 + count] <= INIT_02[count]; + mem[256 * 3 + count] <= INIT_03[count]; + mem[256 * 4 + count] <= INIT_04[count]; + mem[256 * 5 + count] <= INIT_05[count]; + mem[256 * 6 + count] <= INIT_06[count]; + mem[256 * 7 + count] <= INIT_07[count]; + mem[256 * 8 + count] <= INIT_08[count]; + mem[256 * 9 + count] <= INIT_09[count]; + mem[256 * 10 + count] <= INIT_0A[count]; + mem[256 * 11 + count] <= INIT_0B[count]; + mem[256 * 12 + count] <= INIT_0C[count]; + mem[256 * 13 + count] <= INIT_0D[count]; + mem[256 * 14 + count] <= INIT_0E[count]; + mem[256 * 15 + count] <= INIT_0F[count]; + end + end + + always @(posedge clk_int) + begin + if (en_int == 1'b1) + if (rst_int == 1'b1) + begin + d0_out <= 0; + d1_out <= 0; + d2_out <= 0; + d3_out <= 0; + end + else + if (we_int == 1'b1) + begin + d0_out <= di_int[0]; + d1_out <= di_int[1]; + d2_out <= di_int[2]; + d3_out <= di_int[3]; + end + else + begin + d0_out <= mem[addr_int * 4]; + d1_out <= mem[addr_int * 4 + 1]; + d2_out <= mem[addr_int * 4 + 2]; + d3_out <= mem[addr_int * 4 + 3]; + end + end + + always @(posedge clk_int) + begin + if (en_int == 1'b1 && we_int == 1'b1) + begin + mem[addr_int * 4] <= di_int[0]; + mem[addr_int * 4 + 1] <= di_int[1]; + mem[addr_int * 4 + 2] <= di_int[2]; + mem[addr_int * 4 + 3] <= di_int[3]; + end + end + + specify + (CLK *> DO) = (100, 100); + endspecify + +endmodule + +`else + + +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/RAMB4_S4.v,v 1.6 2005/03/14 22:54:42 wloo Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2005 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Timing Simulation Library Component +// / / 16K-Bit Data and 2K-Bit Parity Single Port Block RAM +// /___/ /\ Filename : RAMB4_S4.v +// \ \ / \ Timestamp : Thu Mar 10 16:44:01 PST 2005 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 03/10/05 - Initialized outputs. +// End Revision + +`timescale 1 ps/1 ps + +module RAMB4_S4 (DO, ADDR, CLK, DI, EN, RST, WE); + + parameter INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + + output [3:0] DO; + + input [9:0] ADDR; + input [3:0] DI; + input EN, CLK, WE, RST; + + reg [3:0] do_out = 0; + + reg [3:0] mem [1023:0]; + + reg [8:0] count; + + wire [9:0] addr_int; + wire [3:0] di_int; + wire en_int, clk_int, we_int, rst_int; + + wire di_enable = en_int && we_int; + + tri0 GSR = glbl.GSR; + wire gsr_int; + + buf b_gsr (gsr_int, GSR); + + buf b_do [3:0] (DO, do_out); + buf b_addr [9:0] (addr_int, ADDR); + buf b_di [3:0] (di_int, DI); + buf b_en (en_int, EN); + buf b_clk (clk_int, CLK); + buf b_rst (rst_int, RST); + buf b_we (we_int, WE); + + + always @(gsr_int) + if (gsr_int) begin + assign do_out = 0; + end + else begin + deassign do_out; + end + + + initial begin + + for (count = 0; count < 64; count = count + 1) begin + mem[count] = INIT_00[(count * 4) +: 4]; + mem[64 * 1 + count] = INIT_01[(count * 4) +: 4]; + mem[64 * 2 + count] = INIT_02[(count * 4) +: 4]; + mem[64 * 3 + count] = INIT_03[(count * 4) +: 4]; + mem[64 * 4 + count] = INIT_04[(count * 4) +: 4]; + mem[64 * 5 + count] = INIT_05[(count * 4) +: 4]; + mem[64 * 6 + count] = INIT_06[(count * 4) +: 4]; + mem[64 * 7 + count] = INIT_07[(count * 4) +: 4]; + mem[64 * 8 + count] = INIT_08[(count * 4) +: 4]; + mem[64 * 9 + count] = INIT_09[(count * 4) +: 4]; + mem[64 * 10 + count] = INIT_0A[(count * 4) +: 4]; + mem[64 * 11 + count] = INIT_0B[(count * 4) +: 4]; + mem[64 * 12 + count] = INIT_0C[(count * 4) +: 4]; + mem[64 * 13 + count] = INIT_0D[(count * 4) +: 4]; + mem[64 * 14 + count] = INIT_0E[(count * 4) +: 4]; + mem[64 * 15 + count] = INIT_0F[(count * 4) +: 4]; + end + + end // initial begin + + + always @(posedge clk_int) begin + + if (en_int == 1'b1) begin + + if (rst_int == 1'b1) + do_out <= #100 0; + + else + if (we_int == 1'b1) + do_out <= #100 di_int; + + else + do_out <= #100 mem[addr_int]; + + // memory + if (we_int == 1'b1) + mem[addr_int] <= di_int; + + end + end + + +endmodule + +`endif diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/RAMB4_S4_S16.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/RAMB4_S4_S16.v new file mode 100644 index 0000000..abe622a --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/RAMB4_S4_S16.v @@ -0,0 +1,1123 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/RAMB4_S4_S16.v,v 1.9 2007/02/22 01:58:06 wloo Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2005 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / 4K-Bit Data Dual Port Block RAM +// /___/ /\ Filename : RAMB4_S4_S16.v +// \ \ / \ Timestamp : Thu Mar 10 16:43:39 PST 2005 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// End Revision + +`ifdef legacy_model + +`timescale 1 ps / 1 ps + +module RAMB4_S4_S16 (DOA, DOB, ADDRA, ADDRB, CLKA, CLKB, DIA, DIB, ENA, ENB, RSTA, RSTB, WEA, WEB); + + parameter SIM_COLLISION_CHECK = "ALL"; + localparam SETUP_ALL = 100; + + parameter INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + + output [3:0] DOA; + reg [3:0] doa_out; + wire doa_out0, doa_out1, doa_out2, doa_out3; + + input [9:0] ADDRA; + input [3:0] DIA; + input ENA, CLKA, WEA, RSTA; + + output [15:0] DOB; + reg [15:0] dob_out; + wire dob_out0, dob_out1, dob_out2, dob_out3, dob_out4, dob_out5, dob_out6, dob_out7, dob_out8, dob_out9, dob_out10, dob_out11, dob_out12, dob_out13, dob_out14, dob_out15; + + input [7:0] ADDRB; + input [15:0] DIB; + input ENB, CLKB, WEB, RSTB; + + reg [4095:0] mem; + reg [8:0] count; + + reg [5:0] mi, mj, ai, aj, bi, bj, ci, cj, di, dj, ei, ej, fi, fj; + + wire [9:0] addra_int; + reg [9:0] addra_reg; + wire [3:0] dia_int; + wire ena_int, clka_int, wea_int, rsta_int; + reg ena_reg, wea_reg, rsta_reg; + wire [7:0] addrb_int; + reg [7:0] addrb_reg; + wire [15:0] dib_int; + wire enb_int, clkb_int, web_int, rstb_int; + reg enb_reg, web_reg, rstb_reg; + + time time_clka, time_clkb; + time time_clka_clkb; + time time_clkb_clka; + + reg setup_all_a_b; + reg setup_all_b_a; + reg setup_zero; + reg [1:0] data_collision, data_collision_a_b, data_collision_b_a; + reg memory_collision, memory_collision_a_b, memory_collision_b_a; + reg address_collision, address_collision_a_b, address_collision_b_a; + reg change_clka; + reg change_clkb; + + wire [11:0] mem_addra_int; + wire [11:0] mem_addra_reg; + wire [11:0] mem_addrb_int; + wire [11:0] mem_addrb_reg; + + tri0 GSR = glbl.GSR; + + always @(GSR) + if (GSR) begin + assign doa_out = 0; + end + else begin + deassign doa_out; + end + + always @(GSR) + if (GSR) begin + assign dob_out = 0; + end + else begin + deassign dob_out; + end + + buf b_doa_out0 (doa_out0, doa_out[0]); + buf b_doa_out1 (doa_out1, doa_out[1]); + buf b_doa_out2 (doa_out2, doa_out[2]); + buf b_doa_out3 (doa_out3, doa_out[3]); + buf b_dob_out0 (dob_out0, dob_out[0]); + buf b_dob_out1 (dob_out1, dob_out[1]); + buf b_dob_out2 (dob_out2, dob_out[2]); + buf b_dob_out3 (dob_out3, dob_out[3]); + buf b_dob_out4 (dob_out4, dob_out[4]); + buf b_dob_out5 (dob_out5, dob_out[5]); + buf b_dob_out6 (dob_out6, dob_out[6]); + buf b_dob_out7 (dob_out7, dob_out[7]); + buf b_dob_out8 (dob_out8, dob_out[8]); + buf b_dob_out9 (dob_out9, dob_out[9]); + buf b_dob_out10 (dob_out10, dob_out[10]); + buf b_dob_out11 (dob_out11, dob_out[11]); + buf b_dob_out12 (dob_out12, dob_out[12]); + buf b_dob_out13 (dob_out13, dob_out[13]); + buf b_dob_out14 (dob_out14, dob_out[14]); + buf b_dob_out15 (dob_out15, dob_out[15]); + buf b_doa0 (DOA[0], doa_out0); + buf b_doa1 (DOA[1], doa_out1); + buf b_doa2 (DOA[2], doa_out2); + buf b_doa3 (DOA[3], doa_out3); + buf b_dob0 (DOB[0], dob_out0); + buf b_dob1 (DOB[1], dob_out1); + buf b_dob2 (DOB[2], dob_out2); + buf b_dob3 (DOB[3], dob_out3); + buf b_dob4 (DOB[4], dob_out4); + buf b_dob5 (DOB[5], dob_out5); + buf b_dob6 (DOB[6], dob_out6); + buf b_dob7 (DOB[7], dob_out7); + buf b_dob8 (DOB[8], dob_out8); + buf b_dob9 (DOB[9], dob_out9); + buf b_dob10 (DOB[10], dob_out10); + buf b_dob11 (DOB[11], dob_out11); + buf b_dob12 (DOB[12], dob_out12); + buf b_dob13 (DOB[13], dob_out13); + buf b_dob14 (DOB[14], dob_out14); + buf b_dob15 (DOB[15], dob_out15); + buf b_addra_0 (addra_int[0], ADDRA[0]); + buf b_addra_1 (addra_int[1], ADDRA[1]); + buf b_addra_2 (addra_int[2], ADDRA[2]); + buf b_addra_3 (addra_int[3], ADDRA[3]); + buf b_addra_4 (addra_int[4], ADDRA[4]); + buf b_addra_5 (addra_int[5], ADDRA[5]); + buf b_addra_6 (addra_int[6], ADDRA[6]); + buf b_addra_7 (addra_int[7], ADDRA[7]); + buf b_addra_8 (addra_int[8], ADDRA[8]); + buf b_addra_9 (addra_int[9], ADDRA[9]); + buf b_dia_0 (dia_int[0], DIA[0]); + buf b_dia_1 (dia_int[1], DIA[1]); + buf b_dia_2 (dia_int[2], DIA[2]); + buf b_dia_3 (dia_int[3], DIA[3]); + buf b_clka (clka_int, CLKA); + buf b_ena (ena_int, ENA); + buf b_rsta (rsta_int, RSTA); + buf b_wea (wea_int, WEA); + buf b_addrb_0 (addrb_int[0], ADDRB[0]); + buf b_addrb_1 (addrb_int[1], ADDRB[1]); + buf b_addrb_2 (addrb_int[2], ADDRB[2]); + buf b_addrb_3 (addrb_int[3], ADDRB[3]); + buf b_addrb_4 (addrb_int[4], ADDRB[4]); + buf b_addrb_5 (addrb_int[5], ADDRB[5]); + buf b_addrb_6 (addrb_int[6], ADDRB[6]); + buf b_addrb_7 (addrb_int[7], ADDRB[7]); + buf b_dib_0 (dib_int[0], DIB[0]); + buf b_dib_1 (dib_int[1], DIB[1]); + buf b_dib_2 (dib_int[2], DIB[2]); + buf b_dib_3 (dib_int[3], DIB[3]); + buf b_dib_4 (dib_int[4], DIB[4]); + buf b_dib_5 (dib_int[5], DIB[5]); + buf b_dib_6 (dib_int[6], DIB[6]); + buf b_dib_7 (dib_int[7], DIB[7]); + buf b_dib_8 (dib_int[8], DIB[8]); + buf b_dib_9 (dib_int[9], DIB[9]); + buf b_dib_10 (dib_int[10], DIB[10]); + buf b_dib_11 (dib_int[11], DIB[11]); + buf b_dib_12 (dib_int[12], DIB[12]); + buf b_dib_13 (dib_int[13], DIB[13]); + buf b_dib_14 (dib_int[14], DIB[14]); + buf b_dib_15 (dib_int[15], DIB[15]); + buf b_clkb (clkb_int, CLKB); + buf b_enb (enb_int, ENB); + buf b_rstb (rstb_int, RSTB); + buf b_web (web_int, WEB); + + initial begin + for (count = 0; count < 256; count = count + 1) begin + mem[count] <= INIT_00[count]; + mem[256 * 1 + count] <= INIT_01[count]; + mem[256 * 2 + count] <= INIT_02[count]; + mem[256 * 3 + count] <= INIT_03[count]; + mem[256 * 4 + count] <= INIT_04[count]; + mem[256 * 5 + count] <= INIT_05[count]; + mem[256 * 6 + count] <= INIT_06[count]; + mem[256 * 7 + count] <= INIT_07[count]; + mem[256 * 8 + count] <= INIT_08[count]; + mem[256 * 9 + count] <= INIT_09[count]; + mem[256 * 10 + count] <= INIT_0A[count]; + mem[256 * 11 + count] <= INIT_0B[count]; + mem[256 * 12 + count] <= INIT_0C[count]; + mem[256 * 13 + count] <= INIT_0D[count]; + mem[256 * 14 + count] <= INIT_0E[count]; + mem[256 * 15 + count] <= INIT_0F[count]; + end + address_collision <= 0; + address_collision_a_b <= 0; + address_collision_b_a <= 0; + change_clka <= 0; + change_clkb <= 0; + data_collision <= 0; + data_collision_a_b <= 0; + data_collision_b_a <= 0; + memory_collision <= 0; + memory_collision_a_b <= 0; + memory_collision_b_a <= 0; + setup_all_a_b <= 0; + setup_all_b_a <= 0; + setup_zero <= 0; + end + + assign mem_addra_int = addra_int * 4; + assign mem_addra_reg = addra_reg * 4; + assign mem_addrb_int = addrb_int * 16; + assign mem_addrb_reg = addrb_reg * 16; + + + initial begin + + case (SIM_COLLISION_CHECK) + + "NONE" : begin + assign setup_all_a_b = 1'b0; + assign setup_all_b_a = 1'b0; + assign setup_zero = 1'b0; + assign address_collision = 1'b0; + assign address_collision_a_b = 1'b0; + assign address_collision_b_a = 1'b0; + end + "WARNING_ONLY" : begin + assign data_collision = 2'b00; + assign data_collision_a_b = 2'b00; + assign data_collision_b_a = 2'b00; + assign memory_collision = 1'b0; + assign memory_collision_a_b = 1'b0; + assign memory_collision_b_a = 1'b0; + end + "GENERATE_X_ONLY" : begin + assign address_collision = 1'b0; + assign address_collision_a_b = 1'b0; + assign address_collision_b_a = 1'b0; + end + "ALL" : ; + default : begin + $display("Attribute Syntax Error : The Attribute SIM_COLLISION_CHECK on RAMB4_S4_S16 instance %m is set to %s. Legal values for this attribute are ALL, NONE, WARNING_ONLY or GENERATE_X_ONLY.", SIM_COLLISION_CHECK); + $finish; + end + + endcase // case(SIM_COLLISION_CHECK) + + end // initial begin + + + always @(posedge clka_int) begin + time_clka = $time; + #0 time_clkb_clka = time_clka - time_clkb; + change_clka = ~change_clka; + end + + always @(posedge clkb_int) begin + time_clkb = $time; + #0 time_clka_clkb = time_clkb - time_clka; + change_clkb = ~change_clkb; + end + + always @(change_clkb) begin + if ((0 < time_clka_clkb) && (time_clka_clkb < SETUP_ALL)) + setup_all_a_b = 1; + end + + always @(change_clka) begin + if ((0 < time_clkb_clka) && (time_clkb_clka < SETUP_ALL)) + setup_all_b_a = 1; + end + + always @(change_clkb or change_clka) begin + if ((time_clkb_clka == 0) && (time_clka_clkb == 0)) + setup_zero = 1; + end + + always @(posedge setup_zero) begin + if ((ena_int == 1) && (wea_int == 1) && + (enb_int == 1) && (web_int == 1)) + memory_collision <= 1; + end + + always @(posedge setup_all_a_b) begin + if ((ena_reg == 1) && (enb_int == 1)) begin + case ({wea_reg, web_int}) + 6'b11 : begin data_collision_a_b <= 2'b11; display_all_a_b; end + 6'b01 : begin data_collision_a_b <= 2'b10; display_all_a_b; end + 6'b10 : begin data_collision_a_b <= 2'b01; display_all_a_b; end + endcase + end + setup_all_a_b <= 0; + end + + task display_all_a_b; + begin + address_collision_a_b = 1'b0; + for (ci = 0; ci < 16; ci = ci + 4) begin + if ((mem_addra_reg) == (mem_addrb_int + ci)) begin + address_collision_a_b = 1'b1; + end + end + if (address_collision_a_b == 1'b1) + + if (({wea_reg, web_int}) == 2'b11) + $display("Memory Collision Error on RAMB4_S4_S16:%m at simulation time %.3f ns\nA write was requested to the same address simultaneously at both Port A and Port B of the RAM. The contents written to the RAM at address location %h (hex) of Port A and address location %h (hex) of Port B are unknown.", $time/1000.0, addra_int, addrb_int); + + else if (({wea_reg, web_int}) == 2'b01) + $display("Memory Collision Error on RAMB4_S4_S16:%m at simulation time %.3f ns\nA read was performed on address %h (hex) of Port A while a write was requested to the same address on Port B. The write will be successful however the read value on Port A is unknown until the next CLKA cycle.", $time/1000.0, addra_int); + + else if (({wea_reg, web_int}) == 2'b10) + $display("Memory Collision Error on RAMB4_S4_S16:%m at simulation time %.3f ns\nA read was performed on address %h (hex) of Port B while a write was requested to the same address on Port A. The write will be successful however the read value on Port B is unknown until the next CLKB cycle.", $time/1000.0, addrb_int); + + end + endtask + + always @(posedge setup_all_b_a) begin + if ((ena_int == 1) && (enb_reg == 1)) begin + case ({wea_int, web_reg}) + 6'b11 : begin data_collision_b_a <= 2'b11; display_all_b_a; end + 6'b01 : begin data_collision_b_a <= 2'b10; display_all_b_a; end + 6'b10 : begin data_collision_b_a <= 2'b01; display_all_b_a; end + endcase + end + setup_all_b_a <= 0; + end + + task display_all_b_a; + begin + address_collision_b_a = 1'b0; + for (ci = 0; ci < 16; ci = ci + 4) begin + if ((mem_addra_int) == (mem_addrb_reg + ci)) begin + address_collision_b_a = 1'b1; + end + end + if (address_collision_b_a == 1'b1) + + if (({wea_int, web_reg}) == 2'b11) + $display("Memory Collision Error on RAMB4_S4_S16:%m at simulation time %.3f ns\nA write was requested to the same address simultaneously at both Port A and Port B of the RAM. The contents written to the RAM at address location %h (hex) of Port A and address location %h (hex) of Port B are unknown.", $time/1000.0, addra_int, addrb_int); + + else if (({wea_int, web_reg}) == 2'b01) + $display("Memory Collision Error on RAMB4_S4_S16:%m at simulation time %.3f ns\nA read was performed on address %h (hex) of Port A while a write was requested to the same address on Port B. The write will be successful however the read value on Port A is unknown until the next CLKA cycle.", $time/1000.0, addra_int); + + else if (({wea_int, web_reg}) == 2'b10) + $display("Memory Collision Error on RAMB4_S4_S16:%m at simulation time %.3f ns\nA read was performed on address %h (hex) of Port B while a write was requested to the same address on Port A. The write will be successful however the read value on Port B is unknown until the next CLKB cycle.", $time/1000.0, addrb_int); + + end + endtask + + always @(posedge setup_zero) begin + if ((ena_int == 1) && (enb_int == 1)) begin + case ({wea_int, web_int}) + 6'b11 : begin data_collision <= 2'b11; display_zero; end + 6'b01 : begin data_collision <= 2'b10; display_zero; end + 6'b10 : begin data_collision <= 2'b01; display_zero; end + endcase + end + setup_zero <= 0; + end + + task display_zero; + begin + address_collision = 1'b0; + for (ci = 0; ci < 16; ci = ci + 4) begin + if ((mem_addra_int) == (mem_addrb_int + ci)) begin + address_collision = 1'b1; + end + end + if (address_collision == 1'b1) + + if (({wea_int, web_int}) == 2'b11) + $display("Memory Collision Error on RAMB4_S4_S16:%m at simulation time %.3f ns\nA write was requested to the same address simultaneously at both Port A and Port B of the RAM. The contents written to the RAM at address location %h (hex) of Port A and address location %h (hex) of Port B are unknown.", $time/1000.0, addra_int, addrb_int); + + else if (({wea_int, web_int}) == 2'b01) + $display("Memory Collision Error on RAMB4_S4_S16:%m at simulation time %.3f ns\nA read was performed on address %h (hex) of Port A while a write was requested to the same address on Port B. The write will be successful however the read value on Port A is unknown until the next CLKA cycle.", $time/1000.0, addra_int); + + else if (({wea_int, web_int}) == 2'b10) + $display("Memory Collision Error on RAMB4_S4_S16:%m at simulation time %.3f ns\nA read was performed on address %h (hex) of Port B while a write was requested to the same address on Port A. The write will be successful however the read value on Port B is unknown until the next CLKB cycle.", $time/1000.0, addrb_int); + + end + endtask + + always @(posedge clka_int) begin + addra_reg <= addra_int; + ena_reg <= ena_int; + rsta_reg <= rsta_int; + wea_reg <= wea_int; + end + + always @(posedge clkb_int) begin + addrb_reg <= addrb_int; + enb_reg <= enb_int; + rstb_reg <= rstb_int; + web_reg <= web_int; + end + + // Data + always @(posedge memory_collision) begin + for (mi = 0; mi < 16; mi = mi + 4) begin + if ((mem_addra_int) == (mem_addrb_int + mi)) begin + for (mj = 0; mj < 4; mj = mj + 1) begin + mem[mem_addrb_int + mi + mj] <= 1'bX; + end + end + end + memory_collision <= 0; + end + + always @(posedge memory_collision_a_b) begin + for (mi = 0; mi < 16; mi = mi + 4) begin + if ((mem_addra_reg) == (mem_addrb_int + mi)) begin + for (mj = 0; mj < 4; mj = mj + 1) begin + mem[mem_addrb_int + mi + mj] <= 1'bX; + end + end + end + memory_collision_a_b <= 0; + end + + always @(posedge memory_collision_b_a) begin + for (mi = 0; mi < 16; mi = mi + 4) begin + if ((mem_addra_int) == (mem_addrb_reg + mi)) begin + for (mj = 0; mj < 4; mj = mj + 1) begin + mem[mem_addrb_reg + mi + mj] <= 1'bX; + end + end + end + memory_collision_b_a <= 0; + end + + always @(posedge data_collision[1]) begin + if (rsta_int == 0) begin + for (ai = 0; ai < 16; ai = ai + 4) begin + if ((mem_addra_int) == (mem_addrb_int + ai)) begin + doa_out <= 4'bX; + end + end + end + data_collision[1] <= 0; + end + + always @(posedge data_collision[0]) begin + if (rstb_int == 0) begin + for (bi = 0; bi < 16; bi = bi + 4) begin + if ((mem_addra_int) == (mem_addrb_int + bi)) begin + for (bj = 0; bj < 4; bj = bj + 1) begin + dob_out[bi + bj] <= 1'bX; + end + end + end + end + data_collision[0] <= 0; + end + + always @(posedge data_collision_a_b[1]) begin + if (rsta_reg == 0) begin + for (ai = 0; ai < 16; ai = ai + 4) begin + if ((mem_addra_reg) == (mem_addrb_int + ai)) begin + doa_out <= 4'bX; + end + end + end + data_collision_a_b[1] <= 0; + end + + always @(posedge data_collision_a_b[0]) begin + if (rstb_int == 0) begin + for (bi = 0; bi < 16; bi = bi + 4) begin + if ((mem_addra_reg) == (mem_addrb_int + bi)) begin + for (bj = 0; bj < 4; bj = bj + 1) begin + dob_out[bi + bj] <= 1'bX; + end + end + end + end + data_collision_a_b[0] <= 0; + end + + always @(posedge data_collision_b_a[1]) begin + if (rsta_int == 0) begin + for (ai = 0; ai < 16; ai = ai + 4) begin + if ((mem_addra_int) == (mem_addrb_reg + ai)) begin + doa_out <= 4'bX; + end + end + end + data_collision_b_a[1] <= 0; + end + + always @(posedge data_collision_b_a[0]) begin + if (rstb_reg == 0) begin + for (bi = 0; bi < 16; bi = bi + 4) begin + if ((mem_addra_int) == (mem_addrb_reg + bi)) begin + for (bj = 0; bj < 4; bj = bj + 1) begin + dob_out[bi + bj] <= 1'bX; + end + end + end + end + data_collision_b_a[0] <= 0; + end + + + always @(posedge clka_int) begin + if (ena_int == 1'b1) begin + if (rsta_int == 1'b1) begin + doa_out <= 4'b0; + end + else if (wea_int == 0) begin + doa_out[0] <= mem[mem_addra_int + 0]; + doa_out[1] <= mem[mem_addra_int + 1]; + doa_out[2] <= mem[mem_addra_int + 2]; + doa_out[3] <= mem[mem_addra_int + 3]; + end + else begin + doa_out <= dia_int; + end + end + end + + always @(posedge clka_int) begin + if (ena_int == 1'b1 && wea_int == 1'b1) begin + mem[mem_addra_int + 0] <= dia_int[0]; + mem[mem_addra_int + 1] <= dia_int[1]; + mem[mem_addra_int + 2] <= dia_int[2]; + mem[mem_addra_int + 3] <= dia_int[3]; + end + end + + always @(posedge clkb_int) begin + if (enb_int == 1'b1) begin + if (rstb_int == 1'b1) begin + dob_out <= 16'b0; + end + else if (web_int == 0) begin + dob_out[0] <= mem[mem_addrb_int + 0]; + dob_out[1] <= mem[mem_addrb_int + 1]; + dob_out[2] <= mem[mem_addrb_int + 2]; + dob_out[3] <= mem[mem_addrb_int + 3]; + dob_out[4] <= mem[mem_addrb_int + 4]; + dob_out[5] <= mem[mem_addrb_int + 5]; + dob_out[6] <= mem[mem_addrb_int + 6]; + dob_out[7] <= mem[mem_addrb_int + 7]; + dob_out[8] <= mem[mem_addrb_int + 8]; + dob_out[9] <= mem[mem_addrb_int + 9]; + dob_out[10] <= mem[mem_addrb_int + 10]; + dob_out[11] <= mem[mem_addrb_int + 11]; + dob_out[12] <= mem[mem_addrb_int + 12]; + dob_out[13] <= mem[mem_addrb_int + 13]; + dob_out[14] <= mem[mem_addrb_int + 14]; + dob_out[15] <= mem[mem_addrb_int + 15]; + end + else begin + dob_out <= dib_int; + end + end + end + + always @(posedge clkb_int) begin + if (enb_int == 1'b1 && web_int == 1'b1) begin + mem[mem_addrb_int + 0] <= dib_int[0]; + mem[mem_addrb_int + 1] <= dib_int[1]; + mem[mem_addrb_int + 2] <= dib_int[2]; + mem[mem_addrb_int + 3] <= dib_int[3]; + mem[mem_addrb_int + 4] <= dib_int[4]; + mem[mem_addrb_int + 5] <= dib_int[5]; + mem[mem_addrb_int + 6] <= dib_int[6]; + mem[mem_addrb_int + 7] <= dib_int[7]; + mem[mem_addrb_int + 8] <= dib_int[8]; + mem[mem_addrb_int + 9] <= dib_int[9]; + mem[mem_addrb_int + 10] <= dib_int[10]; + mem[mem_addrb_int + 11] <= dib_int[11]; + mem[mem_addrb_int + 12] <= dib_int[12]; + mem[mem_addrb_int + 13] <= dib_int[13]; + mem[mem_addrb_int + 14] <= dib_int[14]; + mem[mem_addrb_int + 15] <= dib_int[15]; + end + end + + specify + (CLKA *> DOA) = (100, 100); + (CLKB *> DOB) = (100, 100); + endspecify + +endmodule + +`else + +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/RAMB4_S4_S16.v,v 1.9 2007/02/22 01:58:06 wloo Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2005 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Timing Simulation Library Component +// / / 16K-Bit Data and 2K-Bit Parity Dual Port Block RAM +// /___/ /\ Filename : RAMB4_S4_S16.v +// \ \ / \ Timestamp : Thu Mar 10 16:44:01 PST 2005 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 03/10/05 - Initialized outputs. +// 02/21/07 - Fixed parameter SIM_COLLISION_CHECK (CR 433281). +// End Revision + +`timescale 1 ps/1 ps + +module RAMB4_S4_S16 (DOA, DOB, ADDRA, ADDRB, CLKA, CLKB, DIA, DIB, ENA, ENB, RSTA, RSTB, WEA, WEB); + + parameter SIM_COLLISION_CHECK = "ALL"; + localparam SETUP_ALL = 100; + + parameter INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + + output [3:0] DOA; + output [15:0] DOB; + + input [9:0] ADDRA; + input [3:0] DIA; + input ENA, CLKA, WEA, RSTA; + input [7:0] ADDRB; + input [15:0] DIB; + input ENB, CLKB, WEB, RSTB; + + reg [3:0] doa_out = 0; + reg [15:0] dob_out = 0; + + reg [15:0] mem [255:0]; + + reg [8:0] count; + + reg [5:0] mi, ai, bi, bj, ci; + + wire [9:0] addra_int; + reg [9:0] addra_reg; + wire [3:0] dia_int; + wire ena_int, clka_int, wea_int, rsta_int; + reg ena_reg, wea_reg, rsta_reg; + wire [7:0] addrb_int; + reg [7:0] addrb_reg; + wire [15:0] dib_int; + wire enb_int, clkb_int, web_int, rstb_int; + reg display_flag, output_flag; + reg enb_reg, web_reg, rstb_reg; + + time time_clka, time_clkb; + time time_clka_clkb; + time time_clkb_clka; + + reg setup_all_a_b; + reg setup_all_b_a; + reg setup_zero; + reg [1:0] data_collision, data_collision_a_b, data_collision_b_a; + reg memory_collision, memory_collision_a_b, memory_collision_b_a; + reg address_collision, address_collision_a_b, address_collision_b_a; + reg change_clka; + reg change_clkb; + + wire [11:0] mem_addra_int; + wire [11:0] mem_addra_reg; + wire [11:0] mem_addrb_int; + wire [11:0] mem_addrb_reg; + + wire dia_enable = ena_int && wea_int; + wire dib_enable = enb_int && web_int; + + tri0 GSR = glbl.GSR; + wire gsr_int; + + buf b_gsr (gsr_int, GSR); + + buf b_doa [3:0] (DOA, doa_out); + buf b_addra [9:0] (addra_int, ADDRA); + buf b_dia [3:0] (dia_int, DIA); + buf b_ena (ena_int, ENA); + buf b_clka (clka_int, CLKA); + buf b_rsta (rsta_int, RSTA); + buf b_wea (wea_int, WEA); + + buf b_dob [15:0] (DOB, dob_out); + buf b_addrb [7:0] (addrb_int, ADDRB); + buf b_dib [15:0] (dib_int, DIB); + buf b_enb (enb_int, ENB); + buf b_clkb (clkb_int, CLKB); + buf b_rstb (rstb_int, RSTB); + buf b_web (web_int, WEB); + + + always @(gsr_int) + if (gsr_int) begin + assign doa_out = 0; + assign dob_out = 0; + end + else begin + deassign doa_out; + deassign dob_out; + end + + + initial begin + + for (count = 0; count < 16; count = count + 1) begin + mem[count] = INIT_00[(count * 16) +: 16]; + mem[16 * 1 + count] = INIT_01[(count * 16) +: 16]; + mem[16 * 2 + count] = INIT_02[(count * 16) +: 16]; + mem[16 * 3 + count] = INIT_03[(count * 16) +: 16]; + mem[16 * 4 + count] = INIT_04[(count * 16) +: 16]; + mem[16 * 5 + count] = INIT_05[(count * 16) +: 16]; + mem[16 * 6 + count] = INIT_06[(count * 16) +: 16]; + mem[16 * 7 + count] = INIT_07[(count * 16) +: 16]; + mem[16 * 8 + count] = INIT_08[(count * 16) +: 16]; + mem[16 * 9 + count] = INIT_09[(count * 16) +: 16]; + mem[16 * 10 + count] = INIT_0A[(count * 16) +: 16]; + mem[16 * 11 + count] = INIT_0B[(count * 16) +: 16]; + mem[16 * 12 + count] = INIT_0C[(count * 16) +: 16]; + mem[16 * 13 + count] = INIT_0D[(count * 16) +: 16]; + mem[16 * 14 + count] = INIT_0E[(count * 16) +: 16]; + mem[16 * 15 + count] = INIT_0F[(count * 16) +: 16]; + end + + change_clka <= 0; + change_clkb <= 0; + data_collision <= 0; + data_collision_a_b <= 0; + data_collision_b_a <= 0; + memory_collision <= 0; + memory_collision_a_b <= 0; + memory_collision_b_a <= 0; + setup_all_a_b <= 0; + setup_all_b_a <= 0; + setup_zero <= 0; + end + + assign mem_addra_int = addra_int * 4; + assign mem_addra_reg = addra_reg * 4; + assign mem_addrb_int = addrb_int * 16; + assign mem_addrb_reg = addrb_reg * 16; + + + initial begin + + display_flag = 1; + output_flag = 1; + + case (SIM_COLLISION_CHECK) + + "NONE" : begin + output_flag = 0; + display_flag = 0; + end + "WARNING_ONLY" : output_flag = 0; + "GENERATE_X_ONLY" : display_flag = 0; + "ALL" : ; + + default : begin + $display("Attribute Syntax Error : The Attribute SIM_COLLISION_CHECK on RAMB4_S4_S16 instance %m is set to %s. Legal values for this attribute are ALL, NONE, WARNING_ONLY or GENERATE_X_ONLY.", SIM_COLLISION_CHECK); + $finish; + end + + endcase // case(SIM_COLLISION_CHECK) + + end // initial begin + + + always @(posedge clka_int) begin + if ((output_flag || display_flag)) begin + time_clka = $time; + #0 time_clkb_clka = time_clka - time_clkb; + change_clka = ~change_clka; + end + end + + always @(posedge clkb_int) begin + if ((output_flag || display_flag)) begin + time_clkb = $time; + #0 time_clka_clkb = time_clkb - time_clka; + change_clkb = ~change_clkb; + end + end + + always @(change_clkb) begin + if ((0 < time_clka_clkb) && (time_clka_clkb < SETUP_ALL)) + setup_all_a_b = 1; + end + + always @(change_clka) begin + if ((0 < time_clkb_clka) && (time_clkb_clka < SETUP_ALL)) + setup_all_b_a = 1; + end + + always @(change_clkb or change_clka) begin + if ((time_clkb_clka == 0) && (time_clka_clkb == 0)) + setup_zero = 1; + end + + always @(posedge setup_zero) begin + if ((ena_int == 1) && (wea_int == 1) && + (enb_int == 1) && (web_int == 1)) + memory_collision <= 1; + end + + always @(posedge setup_all_a_b) begin + if ((ena_reg == 1) && (enb_int == 1)) begin + case ({wea_reg, web_int}) + 6'b11 : begin data_collision_a_b <= 2'b11; display_all_a_b; end + 6'b01 : begin data_collision_a_b <= 2'b10; display_all_a_b; end + 6'b10 : begin data_collision_a_b <= 2'b01; display_all_a_b; end + endcase + end + setup_all_a_b <= 0; + end + + task display_all_a_b; + begin + address_collision_a_b = 1'b0; + for (ci = 0; ci < 16; ci = ci + 4) begin + if ((mem_addra_reg) == (mem_addrb_int + ci)) begin + address_collision_a_b = 1'b1; + end + end + if (address_collision_a_b == 1'b1 && display_flag) + + if (({wea_reg, web_int}) == 2'b11) + $display("Memory Collision Error on RAMB4_S4_S16:%m at simulation time %.3f ns\nA write was requested to the same address simultaneously at both Port A and Port B of the RAM. The contents written to the RAM at address location %h (hex) of Port A and address location %h (hex) of Port B are unknown.", $time/1000.0, addra_int, addrb_int); + + else if (({wea_reg, web_int}) == 2'b01) + $display("Memory Collision Error on RAMB4_S4_S16:%m at simulation time %.3f ns\nA read was performed on address %h (hex) of Port A while a write was requested to the same address on Port B. The write will be successful however the read value on Port A is unknown until the next CLKA cycle.", $time/1000.0, addra_int); + + else if (({wea_reg, web_int}) == 2'b10) + $display("Memory Collision Error on RAMB4_S4_S16:%m at simulation time %.3f ns\nA read was performed on address %h (hex) of Port B while a write was requested to the same address on Port A. The write will be successful however the read value on Port B is unknown until the next CLKB cycle.", $time/1000.0, addrb_int); + + end + endtask + + always @(posedge setup_all_b_a) begin + if ((ena_int == 1) && (enb_reg == 1)) begin + case ({wea_int, web_reg}) + 6'b11 : begin data_collision_b_a <= 2'b11; display_all_b_a; end + 6'b01 : begin data_collision_b_a <= 2'b10; display_all_b_a; end + 6'b10 : begin data_collision_b_a <= 2'b01; display_all_b_a; end + endcase + end + setup_all_b_a <= 0; + end + + task display_all_b_a; + begin + address_collision_b_a = 1'b0; + for (ci = 0; ci < 16; ci = ci + 4) begin + if ((mem_addra_int) == (mem_addrb_reg + ci)) begin + address_collision_b_a = 1'b1; + end + end + if (address_collision_b_a == 1'b1 && display_flag) + + if (({wea_int, web_reg}) == 2'b11) + $display("Memory Collision Error on RAMB4_S4_S16:%m at simulation time %.3f ns\nA write was requested to the same address simultaneously at both Port A and Port B of the RAM. The contents written to the RAM at address location %h (hex) of Port A and address location %h (hex) of Port B are unknown.", $time/1000.0, addra_int, addrb_int); + + else if (({wea_int, web_reg}) == 2'b01) + $display("Memory Collision Error on RAMB4_S4_S16:%m at simulation time %.3f ns\nA read was performed on address %h (hex) of Port A while a write was requested to the same address on Port B. The write will be successful however the read value on Port A is unknown until the next CLKA cycle.", $time/1000.0, addra_int); + + else if (({wea_int, web_reg}) == 2'b10) + $display("Memory Collision Error on RAMB4_S4_S16:%m at simulation time %.3f ns\nA read was performed on address %h (hex) of Port B while a write was requested to the same address on Port A. The write will be successful however the read value on Port B is unknown until the next CLKB cycle.", $time/1000.0, addrb_int); + + end + endtask + + always @(posedge setup_zero) begin + if ((ena_int == 1) && (enb_int == 1)) begin + case ({wea_int, web_int}) + 6'b11 : begin data_collision <= 2'b11; display_zero; end + 6'b01 : begin data_collision <= 2'b10; display_zero; end + 6'b10 : begin data_collision <= 2'b01; display_zero; end + endcase + end + setup_zero <= 0; + end + + task display_zero; + begin + address_collision = 1'b0; + for (ci = 0; ci < 16; ci = ci + 4) begin + if ((mem_addra_int) == (mem_addrb_int + ci)) begin + address_collision = 1'b1; + end + end + if (address_collision == 1'b1 && display_flag) + + if (({wea_int, web_int}) == 2'b11) + $display("Memory Collision Error on RAMB4_S4_S16:%m at simulation time %.3f ns\nA write was requested to the same address simultaneously at both Port A and Port B of the RAM. The contents written to the RAM at address location %h (hex) of Port A and address location %h (hex) of Port B are unknown.", $time/1000.0, addra_int, addrb_int); + + else if (({wea_int, web_int}) == 2'b01) + $display("Memory Collision Error on RAMB4_S4_S16:%m at simulation time %.3f ns\nA read was performed on address %h (hex) of Port A while a write was requested to the same address on Port B. The write will be successful however the read value on Port A is unknown until the next CLKA cycle.", $time/1000.0, addra_int); + + else if (({wea_int, web_int}) == 2'b10) + $display("Memory Collision Error on RAMB4_S4_S16:%m at simulation time %.3f ns\nA read was performed on address %h (hex) of Port B while a write was requested to the same address on Port A. The write will be successful however the read value on Port B is unknown until the next CLKB cycle.", $time/1000.0, addrb_int); + + end + endtask + + always @(posedge clka_int) begin + if ((output_flag || display_flag)) begin + addra_reg <= addra_int; + ena_reg <= ena_int; + rsta_reg <= rsta_int; + wea_reg <= wea_int; + end + end + + always @(posedge clkb_int) begin + if ((output_flag || display_flag)) begin + addrb_reg <= addrb_int; + enb_reg <= enb_int; + rstb_reg <= rstb_int; + web_reg <= web_int; + end + end + + + // Data + always @(posedge memory_collision) begin + if ((output_flag || display_flag)) begin + for (mi = 0; mi < 16; mi = mi + 4) begin + if ((mem_addra_int) == (mem_addrb_int + mi)) begin + mem[addra_int[9:2]][addra_int[1:0] * 4 +: 4] <= 4'bx; + end + end + memory_collision <= 0; + end + end + + always @(posedge memory_collision_a_b) begin + if ((output_flag || display_flag)) begin + for (mi = 0; mi < 16; mi = mi + 4) begin + if ((mem_addra_reg) == (mem_addrb_int + mi)) begin + mem[addra_reg[9:2]][addra_reg[1:0] * 4 +: 4] <= 4'bx; + end + end + memory_collision_a_b <= 0; + end + end + + always @(posedge memory_collision_b_a) begin + if ((output_flag || display_flag)) begin + for (mi = 0; mi < 16; mi = mi + 4) begin + if ((mem_addra_int) == (mem_addrb_reg + mi)) begin + mem[addra_int[9:2]][addra_int[1:0] * 4 +: 4] <= 4'bx; + end + end + memory_collision_b_a <= 0; + end + end + + always @(posedge data_collision[1]) begin + if (rsta_int == 0 && output_flag) begin + for (ai = 0; ai < 16; ai = ai + 4) begin + if ((mem_addra_int) == (mem_addrb_int + ai)) begin + doa_out <= #100 4'bX; + end + end + end + data_collision[1] <= 0; + end + + always @(posedge data_collision[0]) begin + if (rstb_int == 0 && output_flag) begin + for (bi = 0; bi < 16; bi = bi + 4) begin + if ((mem_addra_int) == (mem_addrb_int + bi)) begin + for (bj = 0; bj < 4; bj = bj + 1) begin + dob_out[bi + bj] <= #100 1'bX; + end + end + end + end + data_collision[0] <= 0; + end + + always @(posedge data_collision_a_b[1]) begin + if (rsta_reg == 0 && output_flag) begin + for (ai = 0; ai < 16; ai = ai + 4) begin + if ((mem_addra_reg) == (mem_addrb_int + ai)) begin + doa_out <= #100 4'bX; + end + end + end + data_collision_a_b[1] <= 0; + end + + always @(posedge data_collision_a_b[0]) begin + if (rstb_int == 0 && output_flag) begin + for (bi = 0; bi < 16; bi = bi + 4) begin + if ((mem_addra_reg) == (mem_addrb_int + bi)) begin + for (bj = 0; bj < 4; bj = bj + 1) begin + dob_out[bi + bj] <= #100 1'bX; + end + end + end + end + data_collision_a_b[0] <= 0; + end + + always @(posedge data_collision_b_a[1]) begin + if (rsta_int == 0 && output_flag) begin + for (ai = 0; ai < 16; ai = ai + 4) begin + if ((mem_addra_int) == (mem_addrb_reg + ai)) begin + doa_out <= #100 4'bX; + end + end + end + data_collision_b_a[1] <= 0; + end + + always @(posedge data_collision_b_a[0]) begin + if (rstb_reg == 0 && output_flag) begin + for (bi = 0; bi < 16; bi = bi + 4) begin + if ((mem_addra_int) == (mem_addrb_reg + bi)) begin + for (bj = 0; bj < 4; bj = bj + 1) begin + dob_out[bi + bj] <= #100 1'bX; + end + end + end + end + data_collision_b_a[0] <= 0; + end + + + // Port A + always @(posedge clka_int) begin + + if (ena_int == 1'b1) begin + + if (rsta_int == 1'b1) begin + doa_out <= #100 0; + end + else begin + if (wea_int == 1'b1) + doa_out <= #100 dia_int; + else + doa_out <= #100 mem[addra_int[9:2]][addra_int[1:0] * 4 +: 4]; + end + + // memory + if (wea_int == 1'b1) begin + mem[addra_int[9:2]][addra_int[1:0] * 4 +: 4] <= dia_int; + end + + end + end + + + // Port B + always @(posedge clkb_int) begin + + if (enb_int == 1'b1) begin + + if (rstb_int == 1'b1) begin + dob_out <= #100 0; + end + else begin + if (web_int == 1'b1) + dob_out <= #100 dib_int; + else + dob_out <= #100 mem[addrb_int]; + end + + // memory + if (web_int == 1'b1) begin + mem[addrb_int] <= dib_int; + end + + end + end + + +endmodule + +`endif diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/RAMB4_S4_S4.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/RAMB4_S4_S4.v new file mode 100644 index 0000000..3fbaf7f --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/RAMB4_S4_S4.v @@ -0,0 +1,1065 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/RAMB4_S4_S4.v,v 1.9 2007/02/22 01:58:06 wloo Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2005 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / 4K-Bit Data Dual Port Block RAM +// /___/ /\ Filename : RAMB4_S4_S4.v +// \ \ / \ Timestamp : Thu Mar 10 16:43:39 PST 2005 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// End Revision + +`ifdef legacy_model + +`timescale 1 ps / 1 ps + +module RAMB4_S4_S4 (DOA, DOB, ADDRA, ADDRB, CLKA, CLKB, DIA, DIB, ENA, ENB, RSTA, RSTB, WEA, WEB); + + parameter SIM_COLLISION_CHECK = "ALL"; + localparam SETUP_ALL = 100; + + parameter INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + + output [3:0] DOA; + reg [3:0] doa_out; + wire doa_out0, doa_out1, doa_out2, doa_out3; + + input [9:0] ADDRA; + input [3:0] DIA; + input ENA, CLKA, WEA, RSTA; + + output [3:0] DOB; + reg [3:0] dob_out; + wire dob_out0, dob_out1, dob_out2, dob_out3; + + input [9:0] ADDRB; + input [3:0] DIB; + input ENB, CLKB, WEB, RSTB; + + reg [4095:0] mem; + reg [8:0] count; + + reg [5:0] mi, mj, ai, aj, bi, bj, ci, cj, di, dj, ei, ej, fi, fj; + + wire [9:0] addra_int; + reg [9:0] addra_reg; + wire [3:0] dia_int; + wire ena_int, clka_int, wea_int, rsta_int; + reg ena_reg, wea_reg, rsta_reg; + wire [9:0] addrb_int; + reg [9:0] addrb_reg; + wire [3:0] dib_int; + wire enb_int, clkb_int, web_int, rstb_int; + reg enb_reg, web_reg, rstb_reg; + + time time_clka, time_clkb; + time time_clka_clkb; + time time_clkb_clka; + + reg setup_all_a_b; + reg setup_all_b_a; + reg setup_zero; + reg [1:0] data_collision, data_collision_a_b, data_collision_b_a; + reg memory_collision, memory_collision_a_b, memory_collision_b_a; + reg address_collision, address_collision_a_b, address_collision_b_a; + reg change_clka; + reg change_clkb; + + wire [11:0] mem_addra_int; + wire [11:0] mem_addra_reg; + wire [11:0] mem_addrb_int; + wire [11:0] mem_addrb_reg; + + tri0 GSR = glbl.GSR; + + always @(GSR) + if (GSR) begin + assign doa_out = 0; + end + else begin + deassign doa_out; + end + + always @(GSR) + if (GSR) begin + assign dob_out = 0; + end + else begin + deassign dob_out; + end + + buf b_doa_out0 (doa_out0, doa_out[0]); + buf b_doa_out1 (doa_out1, doa_out[1]); + buf b_doa_out2 (doa_out2, doa_out[2]); + buf b_doa_out3 (doa_out3, doa_out[3]); + buf b_dob_out0 (dob_out0, dob_out[0]); + buf b_dob_out1 (dob_out1, dob_out[1]); + buf b_dob_out2 (dob_out2, dob_out[2]); + buf b_dob_out3 (dob_out3, dob_out[3]); + buf b_doa0 (DOA[0], doa_out0); + buf b_doa1 (DOA[1], doa_out1); + buf b_doa2 (DOA[2], doa_out2); + buf b_doa3 (DOA[3], doa_out3); + buf b_dob0 (DOB[0], dob_out0); + buf b_dob1 (DOB[1], dob_out1); + buf b_dob2 (DOB[2], dob_out2); + buf b_dob3 (DOB[3], dob_out3); + buf b_addra_0 (addra_int[0], ADDRA[0]); + buf b_addra_1 (addra_int[1], ADDRA[1]); + buf b_addra_2 (addra_int[2], ADDRA[2]); + buf b_addra_3 (addra_int[3], ADDRA[3]); + buf b_addra_4 (addra_int[4], ADDRA[4]); + buf b_addra_5 (addra_int[5], ADDRA[5]); + buf b_addra_6 (addra_int[6], ADDRA[6]); + buf b_addra_7 (addra_int[7], ADDRA[7]); + buf b_addra_8 (addra_int[8], ADDRA[8]); + buf b_addra_9 (addra_int[9], ADDRA[9]); + buf b_dia_0 (dia_int[0], DIA[0]); + buf b_dia_1 (dia_int[1], DIA[1]); + buf b_dia_2 (dia_int[2], DIA[2]); + buf b_dia_3 (dia_int[3], DIA[3]); + buf b_clka (clka_int, CLKA); + buf b_ena (ena_int, ENA); + buf b_rsta (rsta_int, RSTA); + buf b_wea (wea_int, WEA); + buf b_addrb_0 (addrb_int[0], ADDRB[0]); + buf b_addrb_1 (addrb_int[1], ADDRB[1]); + buf b_addrb_2 (addrb_int[2], ADDRB[2]); + buf b_addrb_3 (addrb_int[3], ADDRB[3]); + buf b_addrb_4 (addrb_int[4], ADDRB[4]); + buf b_addrb_5 (addrb_int[5], ADDRB[5]); + buf b_addrb_6 (addrb_int[6], ADDRB[6]); + buf b_addrb_7 (addrb_int[7], ADDRB[7]); + buf b_addrb_8 (addrb_int[8], ADDRB[8]); + buf b_addrb_9 (addrb_int[9], ADDRB[9]); + buf b_dib_0 (dib_int[0], DIB[0]); + buf b_dib_1 (dib_int[1], DIB[1]); + buf b_dib_2 (dib_int[2], DIB[2]); + buf b_dib_3 (dib_int[3], DIB[3]); + buf b_clkb (clkb_int, CLKB); + buf b_enb (enb_int, ENB); + buf b_rstb (rstb_int, RSTB); + buf b_web (web_int, WEB); + + initial begin + for (count = 0; count < 256; count = count + 1) begin + mem[count] <= INIT_00[count]; + mem[256 * 1 + count] <= INIT_01[count]; + mem[256 * 2 + count] <= INIT_02[count]; + mem[256 * 3 + count] <= INIT_03[count]; + mem[256 * 4 + count] <= INIT_04[count]; + mem[256 * 5 + count] <= INIT_05[count]; + mem[256 * 6 + count] <= INIT_06[count]; + mem[256 * 7 + count] <= INIT_07[count]; + mem[256 * 8 + count] <= INIT_08[count]; + mem[256 * 9 + count] <= INIT_09[count]; + mem[256 * 10 + count] <= INIT_0A[count]; + mem[256 * 11 + count] <= INIT_0B[count]; + mem[256 * 12 + count] <= INIT_0C[count]; + mem[256 * 13 + count] <= INIT_0D[count]; + mem[256 * 14 + count] <= INIT_0E[count]; + mem[256 * 15 + count] <= INIT_0F[count]; + end + address_collision <= 0; + address_collision_a_b <= 0; + address_collision_b_a <= 0; + change_clka <= 0; + change_clkb <= 0; + data_collision <= 0; + data_collision_a_b <= 0; + data_collision_b_a <= 0; + memory_collision <= 0; + memory_collision_a_b <= 0; + memory_collision_b_a <= 0; + setup_all_a_b <= 0; + setup_all_b_a <= 0; + setup_zero <= 0; + end + + assign mem_addra_int = addra_int * 4; + assign mem_addra_reg = addra_reg * 4; + assign mem_addrb_int = addrb_int * 4; + assign mem_addrb_reg = addrb_reg * 4; + + + initial begin + + case (SIM_COLLISION_CHECK) + + "NONE" : begin + assign setup_all_a_b = 1'b0; + assign setup_all_b_a = 1'b0; + assign setup_zero = 1'b0; + assign address_collision = 1'b0; + assign address_collision_a_b = 1'b0; + assign address_collision_b_a = 1'b0; + end + "WARNING_ONLY" : begin + assign data_collision = 2'b00; + assign data_collision_a_b = 2'b00; + assign data_collision_b_a = 2'b00; + assign memory_collision = 1'b0; + assign memory_collision_a_b = 1'b0; + assign memory_collision_b_a = 1'b0; + end + "GENERATE_X_ONLY" : begin + assign address_collision = 1'b0; + assign address_collision_a_b = 1'b0; + assign address_collision_b_a = 1'b0; + end + "ALL" : ; + default : begin + $display("Attribute Syntax Error : The Attribute SIM_COLLISION_CHECK on RAMB4_S4_S4 instance %m is set to %s. Legal values for this attribute are ALL, NONE, WARNING_ONLY or GENERATE_X_ONLY.", SIM_COLLISION_CHECK); + $finish; + end + + endcase // case(SIM_COLLISION_CHECK) + + end // initial begin + + + always @(posedge clka_int) begin + time_clka = $time; + #0 time_clkb_clka = time_clka - time_clkb; + change_clka = ~change_clka; + end + + always @(posedge clkb_int) begin + time_clkb = $time; + #0 time_clka_clkb = time_clkb - time_clka; + change_clkb = ~change_clkb; + end + + always @(change_clkb) begin + if ((0 < time_clka_clkb) && (time_clka_clkb < SETUP_ALL)) + setup_all_a_b = 1; + end + + always @(change_clka) begin + if ((0 < time_clkb_clka) && (time_clkb_clka < SETUP_ALL)) + setup_all_b_a = 1; + end + + always @(change_clkb or change_clka) begin + if ((time_clkb_clka == 0) && (time_clka_clkb == 0)) + setup_zero = 1; + end + + always @(posedge setup_zero) begin + if ((ena_int == 1) && (wea_int == 1) && + (enb_int == 1) && (web_int == 1)) + memory_collision <= 1; + end + + always @(posedge setup_all_a_b) begin + if ((ena_reg == 1) && (enb_int == 1)) begin + case ({wea_reg, web_int}) + 6'b11 : begin data_collision_a_b <= 2'b11; display_all_a_b; end + 6'b01 : begin data_collision_a_b <= 2'b10; display_all_a_b; end + 6'b10 : begin data_collision_a_b <= 2'b01; display_all_a_b; end + endcase + end + setup_all_a_b <= 0; + end + + task display_all_a_b; + begin + address_collision_a_b = 1'b0; + for (ci = 0; ci < 4; ci = ci + 4) begin + if ((mem_addra_reg) == (mem_addrb_int + ci)) begin + address_collision_a_b = 1'b1; + end + end + if (address_collision_a_b == 1'b1) + + if (({wea_reg, web_int}) == 2'b11) + $display("Memory Collision Error on RAMB4_S4_S4:%m at simulation time %.3f ns\nA write was requested to the same address simultaneously at both Port A and Port B of the RAM. The contents written to the RAM at address location %h (hex) of Port A and address location %h (hex) of Port B are unknown.", $time/1000.0, addra_int, addrb_int); + + else if (({wea_reg, web_int}) == 2'b01) + $display("Memory Collision Error on RAMB4_S4_S4:%m at simulation time %.3f ns\nA read was performed on address %h (hex) of Port A while a write was requested to the same address on Port B. The write will be successful however the read value on Port A is unknown until the next CLKA cycle.", $time/1000.0, addra_int); + + else if (({wea_reg, web_int}) == 2'b10) + $display("Memory Collision Error on RAMB4_S4_S4:%m at simulation time %.3f ns\nA read was performed on address %h (hex) of Port B while a write was requested to the same address on Port A. The write will be successful however the read value on Port B is unknown until the next CLKB cycle.", $time/1000.0, addrb_int); + + end + endtask + + always @(posedge setup_all_b_a) begin + if ((ena_int == 1) && (enb_reg == 1)) begin + case ({wea_int, web_reg}) + 6'b11 : begin data_collision_b_a <= 2'b11; display_all_b_a; end + 6'b01 : begin data_collision_b_a <= 2'b10; display_all_b_a; end + 6'b10 : begin data_collision_b_a <= 2'b01; display_all_b_a; end + endcase + end + setup_all_b_a <= 0; + end + + task display_all_b_a; + begin + address_collision_b_a = 1'b0; + for (ci = 0; ci < 4; ci = ci + 4) begin + if ((mem_addra_int) == (mem_addrb_reg + ci)) begin + address_collision_b_a = 1'b1; + end + end + if (address_collision_b_a == 1'b1) + + if (({wea_int, web_reg}) == 2'b11) + $display("Memory Collision Error on RAMB4_S4_S4:%m at simulation time %.3f ns\nA write was requested to the same address simultaneously at both Port A and Port B of the RAM. The contents written to the RAM at address location %h (hex) of Port A and address location %h (hex) of Port B are unknown.", $time/1000.0, addra_int, addrb_int); + + else if (({wea_int, web_reg}) == 2'b01) + $display("Memory Collision Error on RAMB4_S4_S4:%m at simulation time %.3f ns\nA read was performed on address %h (hex) of Port A while a write was requested to the same address on Port B. The write will be successful however the read value on Port A is unknown until the next CLKA cycle.", $time/1000.0, addra_int); + + else if (({wea_int, web_reg}) == 2'b10) + $display("Memory Collision Error on RAMB4_S4_S4:%m at simulation time %.3f ns\nA read was performed on address %h (hex) of Port B while a write was requested to the same address on Port A. The write will be successful however the read value on Port B is unknown until the next CLKB cycle.", $time/1000.0, addrb_int); + + end + endtask + + always @(posedge setup_zero) begin + if ((ena_int == 1) && (enb_int == 1)) begin + case ({wea_int, web_int}) + 6'b11 : begin data_collision <= 2'b11; display_zero; end + 6'b01 : begin data_collision <= 2'b10; display_zero; end + 6'b10 : begin data_collision <= 2'b01; display_zero; end + endcase + end + setup_zero <= 0; + end + + task display_zero; + begin + address_collision = 1'b0; + for (ci = 0; ci < 4; ci = ci + 4) begin + if ((mem_addra_int) == (mem_addrb_int + ci)) begin + address_collision = 1'b1; + end + end + if (address_collision == 1'b1) + + if (({wea_int, web_int}) == 2'b11) + $display("Memory Collision Error on RAMB4_S4_S4:%m at simulation time %.3f ns\nA write was requested to the same address simultaneously at both Port A and Port B of the RAM. The contents written to the RAM at address location %h (hex) of Port A and address location %h (hex) of Port B are unknown.", $time/1000.0, addra_int, addrb_int); + + else if (({wea_int, web_int}) == 2'b01) + $display("Memory Collision Error on RAMB4_S4_S4:%m at simulation time %.3f ns\nA read was performed on address %h (hex) of Port A while a write was requested to the same address on Port B. The write will be successful however the read value on Port A is unknown until the next CLKA cycle.", $time/1000.0, addra_int); + + else if (({wea_int, web_int}) == 2'b10) + $display("Memory Collision Error on RAMB4_S4_S4:%m at simulation time %.3f ns\nA read was performed on address %h (hex) of Port B while a write was requested to the same address on Port A. The write will be successful however the read value on Port B is unknown until the next CLKB cycle.", $time/1000.0, addrb_int); + + end + endtask + + always @(posedge clka_int) begin + addra_reg <= addra_int; + ena_reg <= ena_int; + rsta_reg <= rsta_int; + wea_reg <= wea_int; + end + + always @(posedge clkb_int) begin + addrb_reg <= addrb_int; + enb_reg <= enb_int; + rstb_reg <= rstb_int; + web_reg <= web_int; + end + + // Data + always @(posedge memory_collision) begin + for (mi = 0; mi < 4; mi = mi + 4) begin + if ((mem_addra_int) == (mem_addrb_int + mi)) begin + for (mj = 0; mj < 4; mj = mj + 1) begin + mem[mem_addrb_int + mi + mj] <= 1'bX; + end + end + end + memory_collision <= 0; + end + + always @(posedge memory_collision_a_b) begin + for (mi = 0; mi < 4; mi = mi + 4) begin + if ((mem_addra_reg) == (mem_addrb_int + mi)) begin + for (mj = 0; mj < 4; mj = mj + 1) begin + mem[mem_addrb_int + mi + mj] <= 1'bX; + end + end + end + memory_collision_a_b <= 0; + end + + always @(posedge memory_collision_b_a) begin + for (mi = 0; mi < 4; mi = mi + 4) begin + if ((mem_addra_int) == (mem_addrb_reg + mi)) begin + for (mj = 0; mj < 4; mj = mj + 1) begin + mem[mem_addrb_reg + mi + mj] <= 1'bX; + end + end + end + memory_collision_b_a <= 0; + end + + always @(posedge data_collision[1]) begin + if (rsta_int == 0) begin + for (ai = 0; ai < 4; ai = ai + 4) begin + if ((mem_addra_int) == (mem_addrb_int + ai)) begin + doa_out <= 4'bX; + end + end + end + data_collision[1] <= 0; + end + + always @(posedge data_collision[0]) begin + if (rstb_int == 0) begin + for (bi = 0; bi < 4; bi = bi + 4) begin + if ((mem_addra_int) == (mem_addrb_int + bi)) begin + for (bj = 0; bj < 4; bj = bj + 1) begin + dob_out[bi + bj] <= 1'bX; + end + end + end + end + data_collision[0] <= 0; + end + + always @(posedge data_collision_a_b[1]) begin + if (rsta_reg == 0) begin + for (ai = 0; ai < 4; ai = ai + 4) begin + if ((mem_addra_reg) == (mem_addrb_int + ai)) begin + doa_out <= 4'bX; + end + end + end + data_collision_a_b[1] <= 0; + end + + always @(posedge data_collision_a_b[0]) begin + if (rstb_int == 0) begin + for (bi = 0; bi < 4; bi = bi + 4) begin + if ((mem_addra_reg) == (mem_addrb_int + bi)) begin + for (bj = 0; bj < 4; bj = bj + 1) begin + dob_out[bi + bj] <= 1'bX; + end + end + end + end + data_collision_a_b[0] <= 0; + end + + always @(posedge data_collision_b_a[1]) begin + if (rsta_int == 0) begin + for (ai = 0; ai < 4; ai = ai + 4) begin + if ((mem_addra_int) == (mem_addrb_reg + ai)) begin + doa_out <= 4'bX; + end + end + end + data_collision_b_a[1] <= 0; + end + + always @(posedge data_collision_b_a[0]) begin + if (rstb_reg == 0) begin + for (bi = 0; bi < 4; bi = bi + 4) begin + if ((mem_addra_int) == (mem_addrb_reg + bi)) begin + for (bj = 0; bj < 4; bj = bj + 1) begin + dob_out[bi + bj] <= 1'bX; + end + end + end + end + data_collision_b_a[0] <= 0; + end + + + always @(posedge clka_int) begin + if (ena_int == 1'b1) begin + if (rsta_int == 1'b1) begin + doa_out <= 4'b0; + end + else if (wea_int == 0) begin + doa_out[0] <= mem[mem_addra_int + 0]; + doa_out[1] <= mem[mem_addra_int + 1]; + doa_out[2] <= mem[mem_addra_int + 2]; + doa_out[3] <= mem[mem_addra_int + 3]; + end + else begin + doa_out <= dia_int; + end + end + end + + always @(posedge clka_int) begin + if (ena_int == 1'b1 && wea_int == 1'b1) begin + mem[mem_addra_int + 0] <= dia_int[0]; + mem[mem_addra_int + 1] <= dia_int[1]; + mem[mem_addra_int + 2] <= dia_int[2]; + mem[mem_addra_int + 3] <= dia_int[3]; + end + end + + always @(posedge clkb_int) begin + if (enb_int == 1'b1) begin + if (rstb_int == 1'b1) begin + dob_out <= 4'b0; + end + else if (web_int == 0) begin + dob_out[0] <= mem[mem_addrb_int + 0]; + dob_out[1] <= mem[mem_addrb_int + 1]; + dob_out[2] <= mem[mem_addrb_int + 2]; + dob_out[3] <= mem[mem_addrb_int + 3]; + end + else begin + dob_out <= dib_int; + end + end + end + + always @(posedge clkb_int) begin + if (enb_int == 1'b1 && web_int == 1'b1) begin + mem[mem_addrb_int + 0] <= dib_int[0]; + mem[mem_addrb_int + 1] <= dib_int[1]; + mem[mem_addrb_int + 2] <= dib_int[2]; + mem[mem_addrb_int + 3] <= dib_int[3]; + end + end + + specify + (CLKA *> DOA) = (100, 100); + (CLKB *> DOB) = (100, 100); + endspecify + +endmodule + +`else + +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/RAMB4_S4_S4.v,v 1.9 2007/02/22 01:58:06 wloo Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2005 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Timing Simulation Library Component +// / / 16K-Bit Data and 2K-Bit Parity Dual Port Block RAM +// /___/ /\ Filename : RAMB4_S4_S4.v +// \ \ / \ Timestamp : Thu Mar 10 16:44:01 PST 2005 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 03/10/05 - Initialized outputs. +// 02/21/07 - Fixed parameter SIM_COLLISION_CHECK (CR 433281). +// End Revision + +`timescale 1 ps/1 ps + +module RAMB4_S4_S4 (DOA, DOB, ADDRA, ADDRB, CLKA, CLKB, DIA, DIB, ENA, ENB, RSTA, RSTB, WEA, WEB); + + parameter SIM_COLLISION_CHECK = "ALL"; + localparam SETUP_ALL = 100; + + parameter INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + + output [3:0] DOA; + output [3:0] DOB; + + input [9:0] ADDRA; + input [3:0] DIA; + input ENA, CLKA, WEA, RSTA; + input [9:0] ADDRB; + input [3:0] DIB; + input ENB, CLKB, WEB, RSTB; + + reg [3:0] doa_out = 0; + reg [3:0] dob_out = 0; + + reg [3:0] mem [1023:0]; + + reg [8:0] count; + + reg [5:0] mi, ai, bi, bj, ci; + + wire [9:0] addra_int; + reg [9:0] addra_reg; + wire [3:0] dia_int; + wire ena_int, clka_int, wea_int, rsta_int; + reg ena_reg, wea_reg, rsta_reg; + wire [9:0] addrb_int; + reg [9:0] addrb_reg; + wire [3:0] dib_int; + wire enb_int, clkb_int, web_int, rstb_int; + reg display_flag, output_flag; + reg enb_reg, web_reg, rstb_reg; + + time time_clka, time_clkb; + time time_clka_clkb; + time time_clkb_clka; + + reg setup_all_a_b; + reg setup_all_b_a; + reg setup_zero; + reg [1:0] data_collision, data_collision_a_b, data_collision_b_a; + reg memory_collision, memory_collision_a_b, memory_collision_b_a; + reg address_collision, address_collision_a_b, address_collision_b_a; + reg change_clka; + reg change_clkb; + + wire [11:0] mem_addra_int; + wire [11:0] mem_addra_reg; + wire [11:0] mem_addrb_int; + wire [11:0] mem_addrb_reg; + + wire dia_enable = ena_int && wea_int; + wire dib_enable = enb_int && web_int; + + tri0 GSR = glbl.GSR; + wire gsr_int; + + buf b_gsr (gsr_int, GSR); + + buf b_doa [3:0] (DOA, doa_out); + buf b_addra [9:0] (addra_int, ADDRA); + buf b_dia [3:0] (dia_int, DIA); + buf b_ena (ena_int, ENA); + buf b_clka (clka_int, CLKA); + buf b_rsta (rsta_int, RSTA); + buf b_wea (wea_int, WEA); + + buf b_dob [3:0] (DOB, dob_out); + buf b_addrb [9:0] (addrb_int, ADDRB); + buf b_dib [3:0] (dib_int, DIB); + buf b_enb (enb_int, ENB); + buf b_clkb (clkb_int, CLKB); + buf b_rstb (rstb_int, RSTB); + buf b_web (web_int, WEB); + + + always @(gsr_int) + if (gsr_int) begin + assign doa_out = 0; + assign dob_out = 0; + end + else begin + deassign doa_out; + deassign dob_out; + end + + + initial begin + + for (count = 0; count < 64; count = count + 1) begin + mem[count] = INIT_00[(count * 4) +: 4]; + mem[64 * 1 + count] = INIT_01[(count * 4) +: 4]; + mem[64 * 2 + count] = INIT_02[(count * 4) +: 4]; + mem[64 * 3 + count] = INIT_03[(count * 4) +: 4]; + mem[64 * 4 + count] = INIT_04[(count * 4) +: 4]; + mem[64 * 5 + count] = INIT_05[(count * 4) +: 4]; + mem[64 * 6 + count] = INIT_06[(count * 4) +: 4]; + mem[64 * 7 + count] = INIT_07[(count * 4) +: 4]; + mem[64 * 8 + count] = INIT_08[(count * 4) +: 4]; + mem[64 * 9 + count] = INIT_09[(count * 4) +: 4]; + mem[64 * 10 + count] = INIT_0A[(count * 4) +: 4]; + mem[64 * 11 + count] = INIT_0B[(count * 4) +: 4]; + mem[64 * 12 + count] = INIT_0C[(count * 4) +: 4]; + mem[64 * 13 + count] = INIT_0D[(count * 4) +: 4]; + mem[64 * 14 + count] = INIT_0E[(count * 4) +: 4]; + mem[64 * 15 + count] = INIT_0F[(count * 4) +: 4]; + end + + change_clka <= 0; + change_clkb <= 0; + data_collision <= 0; + data_collision_a_b <= 0; + data_collision_b_a <= 0; + memory_collision <= 0; + memory_collision_a_b <= 0; + memory_collision_b_a <= 0; + setup_all_a_b <= 0; + setup_all_b_a <= 0; + setup_zero <= 0; + end + + assign mem_addra_int = addra_int * 4; + assign mem_addra_reg = addra_reg * 4; + assign mem_addrb_int = addrb_int * 4; + assign mem_addrb_reg = addrb_reg * 4; + + + initial begin + + display_flag = 1; + output_flag = 1; + + case (SIM_COLLISION_CHECK) + + "NONE" : begin + output_flag = 0; + display_flag = 0; + end + "WARNING_ONLY" : output_flag = 0; + "GENERATE_X_ONLY" : display_flag = 0; + "ALL" : ; + + default : begin + $display("Attribute Syntax Error : The Attribute SIM_COLLISION_CHECK on RAMB4_S4_S4 instance %m is set to %s. Legal values for this attribute are ALL, NONE, WARNING_ONLY or GENERATE_X_ONLY.", SIM_COLLISION_CHECK); + $finish; + end + + endcase // case(SIM_COLLISION_CHECK) + + end // initial begin + + + always @(posedge clka_int) begin + if ((output_flag || display_flag)) begin + time_clka = $time; + #0 time_clkb_clka = time_clka - time_clkb; + change_clka = ~change_clka; + end + end + + always @(posedge clkb_int) begin + if ((output_flag || display_flag)) begin + time_clkb = $time; + #0 time_clka_clkb = time_clkb - time_clka; + change_clkb = ~change_clkb; + end + end + + always @(change_clkb) begin + if ((0 < time_clka_clkb) && (time_clka_clkb < SETUP_ALL)) + setup_all_a_b = 1; + end + + always @(change_clka) begin + if ((0 < time_clkb_clka) && (time_clkb_clka < SETUP_ALL)) + setup_all_b_a = 1; + end + + always @(change_clkb or change_clka) begin + if ((time_clkb_clka == 0) && (time_clka_clkb == 0)) + setup_zero = 1; + end + + always @(posedge setup_zero) begin + if ((ena_int == 1) && (wea_int == 1) && + (enb_int == 1) && (web_int == 1)) + memory_collision <= 1; + end + + always @(posedge setup_all_a_b) begin + if ((ena_reg == 1) && (enb_int == 1)) begin + case ({wea_reg, web_int}) + 6'b11 : begin data_collision_a_b <= 2'b11; display_all_a_b; end + 6'b01 : begin data_collision_a_b <= 2'b10; display_all_a_b; end + 6'b10 : begin data_collision_a_b <= 2'b01; display_all_a_b; end + endcase + end + setup_all_a_b <= 0; + end + + task display_all_a_b; + begin + address_collision_a_b = 1'b0; + for (ci = 0; ci < 4; ci = ci + 4) begin + if ((mem_addra_reg) == (mem_addrb_int + ci)) begin + address_collision_a_b = 1'b1; + end + end + if (address_collision_a_b == 1'b1 && display_flag) + + if (({wea_reg, web_int}) == 2'b11) + $display("Memory Collision Error on RAMB4_S4_S4:%m at simulation time %.3f ns\nA write was requested to the same address simultaneously at both Port A and Port B of the RAM. The contents written to the RAM at address location %h (hex) of Port A and address location %h (hex) of Port B are unknown.", $time/1000.0, addra_int, addrb_int); + + else if (({wea_reg, web_int}) == 2'b01) + $display("Memory Collision Error on RAMB4_S4_S4:%m at simulation time %.3f ns\nA read was performed on address %h (hex) of Port A while a write was requested to the same address on Port B. The write will be successful however the read value on Port A is unknown until the next CLKA cycle.", $time/1000.0, addra_int); + + else if (({wea_reg, web_int}) == 2'b10) + $display("Memory Collision Error on RAMB4_S4_S4:%m at simulation time %.3f ns\nA read was performed on address %h (hex) of Port B while a write was requested to the same address on Port A. The write will be successful however the read value on Port B is unknown until the next CLKB cycle.", $time/1000.0, addrb_int); + + end + endtask + + always @(posedge setup_all_b_a) begin + if ((ena_int == 1) && (enb_reg == 1)) begin + case ({wea_int, web_reg}) + 6'b11 : begin data_collision_b_a <= 2'b11; display_all_b_a; end + 6'b01 : begin data_collision_b_a <= 2'b10; display_all_b_a; end + 6'b10 : begin data_collision_b_a <= 2'b01; display_all_b_a; end + endcase + end + setup_all_b_a <= 0; + end + + task display_all_b_a; + begin + address_collision_b_a = 1'b0; + for (ci = 0; ci < 4; ci = ci + 4) begin + if ((mem_addra_int) == (mem_addrb_reg + ci)) begin + address_collision_b_a = 1'b1; + end + end + if (address_collision_b_a == 1'b1 && display_flag) + + if (({wea_int, web_reg}) == 2'b11) + $display("Memory Collision Error on RAMB4_S4_S4:%m at simulation time %.3f ns\nA write was requested to the same address simultaneously at both Port A and Port B of the RAM. The contents written to the RAM at address location %h (hex) of Port A and address location %h (hex) of Port B are unknown.", $time/1000.0, addra_int, addrb_int); + + else if (({wea_int, web_reg}) == 2'b01) + $display("Memory Collision Error on RAMB4_S4_S4:%m at simulation time %.3f ns\nA read was performed on address %h (hex) of Port A while a write was requested to the same address on Port B. The write will be successful however the read value on Port A is unknown until the next CLKA cycle.", $time/1000.0, addra_int); + + else if (({wea_int, web_reg}) == 2'b10) + $display("Memory Collision Error on RAMB4_S4_S4:%m at simulation time %.3f ns\nA read was performed on address %h (hex) of Port B while a write was requested to the same address on Port A. The write will be successful however the read value on Port B is unknown until the next CLKB cycle.", $time/1000.0, addrb_int); + + end + endtask + + always @(posedge setup_zero) begin + if ((ena_int == 1) && (enb_int == 1)) begin + case ({wea_int, web_int}) + 6'b11 : begin data_collision <= 2'b11; display_zero; end + 6'b01 : begin data_collision <= 2'b10; display_zero; end + 6'b10 : begin data_collision <= 2'b01; display_zero; end + endcase + end + setup_zero <= 0; + end + + task display_zero; + begin + address_collision = 1'b0; + for (ci = 0; ci < 4; ci = ci + 4) begin + if ((mem_addra_int) == (mem_addrb_int + ci)) begin + address_collision = 1'b1; + end + end + if (address_collision == 1'b1 && display_flag) + + if (({wea_int, web_int}) == 2'b11) + $display("Memory Collision Error on RAMB4_S4_S4:%m at simulation time %.3f ns\nA write was requested to the same address simultaneously at both Port A and Port B of the RAM. The contents written to the RAM at address location %h (hex) of Port A and address location %h (hex) of Port B are unknown.", $time/1000.0, addra_int, addrb_int); + + else if (({wea_int, web_int}) == 2'b01) + $display("Memory Collision Error on RAMB4_S4_S4:%m at simulation time %.3f ns\nA read was performed on address %h (hex) of Port A while a write was requested to the same address on Port B. The write will be successful however the read value on Port A is unknown until the next CLKA cycle.", $time/1000.0, addra_int); + + else if (({wea_int, web_int}) == 2'b10) + $display("Memory Collision Error on RAMB4_S4_S4:%m at simulation time %.3f ns\nA read was performed on address %h (hex) of Port B while a write was requested to the same address on Port A. The write will be successful however the read value on Port B is unknown until the next CLKB cycle.", $time/1000.0, addrb_int); + + end + endtask + + always @(posedge clka_int) begin + if ((output_flag || display_flag)) begin + addra_reg <= addra_int; + ena_reg <= ena_int; + rsta_reg <= rsta_int; + wea_reg <= wea_int; + end + end + + always @(posedge clkb_int) begin + if ((output_flag || display_flag)) begin + addrb_reg <= addrb_int; + enb_reg <= enb_int; + rstb_reg <= rstb_int; + web_reg <= web_int; + end + end + + + // Data + always @(posedge memory_collision) begin + if ((output_flag || display_flag)) begin + for (mi = 0; mi < 4; mi = mi + 4) begin + if ((mem_addra_int) == (mem_addrb_int + mi)) begin + mem[addra_int] <= 4'bx; + end + end + memory_collision <= 0; + end + end + + always @(posedge memory_collision_a_b) begin + if ((output_flag || display_flag)) begin + for (mi = 0; mi < 4; mi = mi + 4) begin + if ((mem_addra_reg) == (mem_addrb_int + mi)) begin + mem[addra_reg] <= 4'bx; + end + end + memory_collision_a_b <= 0; + end + end + + always @(posedge memory_collision_b_a) begin + if ((output_flag || display_flag)) begin + for (mi = 0; mi < 4; mi = mi + 4) begin + if ((mem_addra_int) == (mem_addrb_reg + mi)) begin + mem[addra_int] <= 4'bx; + end + end + memory_collision_b_a <= 0; + end + end + + always @(posedge data_collision[1]) begin + if (rsta_int == 0 && output_flag) begin + for (ai = 0; ai < 4; ai = ai + 4) begin + if ((mem_addra_int) == (mem_addrb_int + ai)) begin + doa_out <= #100 4'bX; + end + end + end + data_collision[1] <= 0; + end + + always @(posedge data_collision[0]) begin + if (rstb_int == 0 && output_flag) begin + for (bi = 0; bi < 4; bi = bi + 4) begin + if ((mem_addra_int) == (mem_addrb_int + bi)) begin + for (bj = 0; bj < 4; bj = bj + 1) begin + dob_out[bi + bj] <= #100 1'bX; + end + end + end + end + data_collision[0] <= 0; + end + + always @(posedge data_collision_a_b[1]) begin + if (rsta_reg == 0 && output_flag) begin + for (ai = 0; ai < 4; ai = ai + 4) begin + if ((mem_addra_reg) == (mem_addrb_int + ai)) begin + doa_out <= #100 4'bX; + end + end + end + data_collision_a_b[1] <= 0; + end + + always @(posedge data_collision_a_b[0]) begin + if (rstb_int == 0 && output_flag) begin + for (bi = 0; bi < 4; bi = bi + 4) begin + if ((mem_addra_reg) == (mem_addrb_int + bi)) begin + for (bj = 0; bj < 4; bj = bj + 1) begin + dob_out[bi + bj] <= #100 1'bX; + end + end + end + end + data_collision_a_b[0] <= 0; + end + + always @(posedge data_collision_b_a[1]) begin + if (rsta_int == 0 && output_flag) begin + for (ai = 0; ai < 4; ai = ai + 4) begin + if ((mem_addra_int) == (mem_addrb_reg + ai)) begin + doa_out <= #100 4'bX; + end + end + end + data_collision_b_a[1] <= 0; + end + + always @(posedge data_collision_b_a[0]) begin + if (rstb_reg == 0 && output_flag) begin + for (bi = 0; bi < 4; bi = bi + 4) begin + if ((mem_addra_int) == (mem_addrb_reg + bi)) begin + for (bj = 0; bj < 4; bj = bj + 1) begin + dob_out[bi + bj] <= #100 1'bX; + end + end + end + end + data_collision_b_a[0] <= 0; + end + + + // Port A + always @(posedge clka_int) begin + + if (ena_int == 1'b1) begin + + if (rsta_int == 1'b1) begin + doa_out <= #100 0; + end + else begin + if (wea_int == 1'b1) + doa_out <= #100 dia_int; + else + doa_out <= #100 mem[addra_int]; + end + + // memory + if (wea_int == 1'b1) begin + mem[addra_int] <= dia_int; + end + + end + end + + + // Port B + always @(posedge clkb_int) begin + + if (enb_int == 1'b1) begin + + if (rstb_int == 1'b1) begin + dob_out <= #100 0; + end + else begin + if (web_int == 1'b1) + dob_out <= #100 dib_int; + else + dob_out <= #100 mem[addrb_int]; + end + + // memory + if (web_int == 1'b1) begin + mem[addrb_int] <= dib_int; + end + + end + end + + +endmodule + +`endif diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/RAMB4_S4_S8.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/RAMB4_S4_S8.v new file mode 100644 index 0000000..1b744e5 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/RAMB4_S4_S8.v @@ -0,0 +1,1084 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/RAMB4_S4_S8.v,v 1.9 2007/02/22 01:58:06 wloo Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2005 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / 4K-Bit Data Dual Port Block RAM +// /___/ /\ Filename : RAMB4_S4_S8.v +// \ \ / \ Timestamp : Thu Mar 10 16:43:39 PST 2005 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// End Revision + +`ifdef legacy_model + +`timescale 1 ps / 1 ps + +module RAMB4_S4_S8 (DOA, DOB, ADDRA, ADDRB, CLKA, CLKB, DIA, DIB, ENA, ENB, RSTA, RSTB, WEA, WEB); + + parameter SIM_COLLISION_CHECK = "ALL"; + localparam SETUP_ALL = 100; + + parameter INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + + output [3:0] DOA; + reg [3:0] doa_out; + wire doa_out0, doa_out1, doa_out2, doa_out3; + + input [9:0] ADDRA; + input [3:0] DIA; + input ENA, CLKA, WEA, RSTA; + + output [7:0] DOB; + reg [7:0] dob_out; + wire dob_out0, dob_out1, dob_out2, dob_out3, dob_out4, dob_out5, dob_out6, dob_out7; + + input [8:0] ADDRB; + input [7:0] DIB; + input ENB, CLKB, WEB, RSTB; + + reg [4095:0] mem; + reg [8:0] count; + + reg [5:0] mi, mj, ai, aj, bi, bj, ci, cj, di, dj, ei, ej, fi, fj; + + wire [9:0] addra_int; + reg [9:0] addra_reg; + wire [3:0] dia_int; + wire ena_int, clka_int, wea_int, rsta_int; + reg ena_reg, wea_reg, rsta_reg; + wire [8:0] addrb_int; + reg [8:0] addrb_reg; + wire [7:0] dib_int; + wire enb_int, clkb_int, web_int, rstb_int; + reg enb_reg, web_reg, rstb_reg; + + time time_clka, time_clkb; + time time_clka_clkb; + time time_clkb_clka; + + reg setup_all_a_b; + reg setup_all_b_a; + reg setup_zero; + reg [1:0] data_collision, data_collision_a_b, data_collision_b_a; + reg memory_collision, memory_collision_a_b, memory_collision_b_a; + reg address_collision, address_collision_a_b, address_collision_b_a; + reg change_clka; + reg change_clkb; + + wire [11:0] mem_addra_int; + wire [11:0] mem_addra_reg; + wire [11:0] mem_addrb_int; + wire [11:0] mem_addrb_reg; + + tri0 GSR = glbl.GSR; + + always @(GSR) + if (GSR) begin + assign doa_out = 0; + end + else begin + deassign doa_out; + end + + always @(GSR) + if (GSR) begin + assign dob_out = 0; + end + else begin + deassign dob_out; + end + + buf b_doa_out0 (doa_out0, doa_out[0]); + buf b_doa_out1 (doa_out1, doa_out[1]); + buf b_doa_out2 (doa_out2, doa_out[2]); + buf b_doa_out3 (doa_out3, doa_out[3]); + buf b_dob_out0 (dob_out0, dob_out[0]); + buf b_dob_out1 (dob_out1, dob_out[1]); + buf b_dob_out2 (dob_out2, dob_out[2]); + buf b_dob_out3 (dob_out3, dob_out[3]); + buf b_dob_out4 (dob_out4, dob_out[4]); + buf b_dob_out5 (dob_out5, dob_out[5]); + buf b_dob_out6 (dob_out6, dob_out[6]); + buf b_dob_out7 (dob_out7, dob_out[7]); + buf b_doa0 (DOA[0], doa_out0); + buf b_doa1 (DOA[1], doa_out1); + buf b_doa2 (DOA[2], doa_out2); + buf b_doa3 (DOA[3], doa_out3); + buf b_dob0 (DOB[0], dob_out0); + buf b_dob1 (DOB[1], dob_out1); + buf b_dob2 (DOB[2], dob_out2); + buf b_dob3 (DOB[3], dob_out3); + buf b_dob4 (DOB[4], dob_out4); + buf b_dob5 (DOB[5], dob_out5); + buf b_dob6 (DOB[6], dob_out6); + buf b_dob7 (DOB[7], dob_out7); + buf b_addra_0 (addra_int[0], ADDRA[0]); + buf b_addra_1 (addra_int[1], ADDRA[1]); + buf b_addra_2 (addra_int[2], ADDRA[2]); + buf b_addra_3 (addra_int[3], ADDRA[3]); + buf b_addra_4 (addra_int[4], ADDRA[4]); + buf b_addra_5 (addra_int[5], ADDRA[5]); + buf b_addra_6 (addra_int[6], ADDRA[6]); + buf b_addra_7 (addra_int[7], ADDRA[7]); + buf b_addra_8 (addra_int[8], ADDRA[8]); + buf b_addra_9 (addra_int[9], ADDRA[9]); + buf b_dia_0 (dia_int[0], DIA[0]); + buf b_dia_1 (dia_int[1], DIA[1]); + buf b_dia_2 (dia_int[2], DIA[2]); + buf b_dia_3 (dia_int[3], DIA[3]); + buf b_clka (clka_int, CLKA); + buf b_ena (ena_int, ENA); + buf b_rsta (rsta_int, RSTA); + buf b_wea (wea_int, WEA); + buf b_addrb_0 (addrb_int[0], ADDRB[0]); + buf b_addrb_1 (addrb_int[1], ADDRB[1]); + buf b_addrb_2 (addrb_int[2], ADDRB[2]); + buf b_addrb_3 (addrb_int[3], ADDRB[3]); + buf b_addrb_4 (addrb_int[4], ADDRB[4]); + buf b_addrb_5 (addrb_int[5], ADDRB[5]); + buf b_addrb_6 (addrb_int[6], ADDRB[6]); + buf b_addrb_7 (addrb_int[7], ADDRB[7]); + buf b_addrb_8 (addrb_int[8], ADDRB[8]); + buf b_dib_0 (dib_int[0], DIB[0]); + buf b_dib_1 (dib_int[1], DIB[1]); + buf b_dib_2 (dib_int[2], DIB[2]); + buf b_dib_3 (dib_int[3], DIB[3]); + buf b_dib_4 (dib_int[4], DIB[4]); + buf b_dib_5 (dib_int[5], DIB[5]); + buf b_dib_6 (dib_int[6], DIB[6]); + buf b_dib_7 (dib_int[7], DIB[7]); + buf b_clkb (clkb_int, CLKB); + buf b_enb (enb_int, ENB); + buf b_rstb (rstb_int, RSTB); + buf b_web (web_int, WEB); + + initial begin + for (count = 0; count < 256; count = count + 1) begin + mem[count] <= INIT_00[count]; + mem[256 * 1 + count] <= INIT_01[count]; + mem[256 * 2 + count] <= INIT_02[count]; + mem[256 * 3 + count] <= INIT_03[count]; + mem[256 * 4 + count] <= INIT_04[count]; + mem[256 * 5 + count] <= INIT_05[count]; + mem[256 * 6 + count] <= INIT_06[count]; + mem[256 * 7 + count] <= INIT_07[count]; + mem[256 * 8 + count] <= INIT_08[count]; + mem[256 * 9 + count] <= INIT_09[count]; + mem[256 * 10 + count] <= INIT_0A[count]; + mem[256 * 11 + count] <= INIT_0B[count]; + mem[256 * 12 + count] <= INIT_0C[count]; + mem[256 * 13 + count] <= INIT_0D[count]; + mem[256 * 14 + count] <= INIT_0E[count]; + mem[256 * 15 + count] <= INIT_0F[count]; + end + address_collision <= 0; + address_collision_a_b <= 0; + address_collision_b_a <= 0; + change_clka <= 0; + change_clkb <= 0; + data_collision <= 0; + data_collision_a_b <= 0; + data_collision_b_a <= 0; + memory_collision <= 0; + memory_collision_a_b <= 0; + memory_collision_b_a <= 0; + setup_all_a_b <= 0; + setup_all_b_a <= 0; + setup_zero <= 0; + end + + assign mem_addra_int = addra_int * 4; + assign mem_addra_reg = addra_reg * 4; + assign mem_addrb_int = addrb_int * 8; + assign mem_addrb_reg = addrb_reg * 8; + + + initial begin + + case (SIM_COLLISION_CHECK) + + "NONE" : begin + assign setup_all_a_b = 1'b0; + assign setup_all_b_a = 1'b0; + assign setup_zero = 1'b0; + assign address_collision = 1'b0; + assign address_collision_a_b = 1'b0; + assign address_collision_b_a = 1'b0; + end + "WARNING_ONLY" : begin + assign data_collision = 2'b00; + assign data_collision_a_b = 2'b00; + assign data_collision_b_a = 2'b00; + assign memory_collision = 1'b0; + assign memory_collision_a_b = 1'b0; + assign memory_collision_b_a = 1'b0; + end + "GENERATE_X_ONLY" : begin + assign address_collision = 1'b0; + assign address_collision_a_b = 1'b0; + assign address_collision_b_a = 1'b0; + end + "ALL" : ; + default : begin + $display("Attribute Syntax Error : The Attribute SIM_COLLISION_CHECK on RAMB4_S4_S8 instance %m is set to %s. Legal values for this attribute are ALL, NONE, WARNING_ONLY or GENERATE_X_ONLY.", SIM_COLLISION_CHECK); + $finish; + end + + endcase // case(SIM_COLLISION_CHECK) + + end // initial begin + + + always @(posedge clka_int) begin + time_clka = $time; + #0 time_clkb_clka = time_clka - time_clkb; + change_clka = ~change_clka; + end + + always @(posedge clkb_int) begin + time_clkb = $time; + #0 time_clka_clkb = time_clkb - time_clka; + change_clkb = ~change_clkb; + end + + always @(change_clkb) begin + if ((0 < time_clka_clkb) && (time_clka_clkb < SETUP_ALL)) + setup_all_a_b = 1; + end + + always @(change_clka) begin + if ((0 < time_clkb_clka) && (time_clkb_clka < SETUP_ALL)) + setup_all_b_a = 1; + end + + always @(change_clkb or change_clka) begin + if ((time_clkb_clka == 0) && (time_clka_clkb == 0)) + setup_zero = 1; + end + + always @(posedge setup_zero) begin + if ((ena_int == 1) && (wea_int == 1) && + (enb_int == 1) && (web_int == 1)) + memory_collision <= 1; + end + + always @(posedge setup_all_a_b) begin + if ((ena_reg == 1) && (enb_int == 1)) begin + case ({wea_reg, web_int}) + 6'b11 : begin data_collision_a_b <= 2'b11; display_all_a_b; end + 6'b01 : begin data_collision_a_b <= 2'b10; display_all_a_b; end + 6'b10 : begin data_collision_a_b <= 2'b01; display_all_a_b; end + endcase + end + setup_all_a_b <= 0; + end + + task display_all_a_b; + begin + address_collision_a_b = 1'b0; + for (ci = 0; ci < 8; ci = ci + 4) begin + if ((mem_addra_reg) == (mem_addrb_int + ci)) begin + address_collision_a_b = 1'b1; + end + end + if (address_collision_a_b == 1'b1) + + if (({wea_reg, web_int}) == 2'b11) + $display("Memory Collision Error on RAMB4_S4_S8:%m at simulation time %.3f ns\nA write was requested to the same address simultaneously at both Port A and Port B of the RAM. The contents written to the RAM at address location %h (hex) of Port A and address location %h (hex) of Port B are unknown.", $time/1000.0, addra_int, addrb_int); + + else if (({wea_reg, web_int}) == 2'b01) + $display("Memory Collision Error on RAMB4_S4_S8:%m at simulation time %.3f ns\nA read was performed on address %h (hex) of Port A while a write was requested to the same address on Port B. The write will be successful however the read value on Port A is unknown until the next CLKA cycle.", $time/1000.0, addra_int); + + else if (({wea_reg, web_int}) == 2'b10) + $display("Memory Collision Error on RAMB4_S4_S8:%m at simulation time %.3f ns\nA read was performed on address %h (hex) of Port B while a write was requested to the same address on Port A. The write will be successful however the read value on Port B is unknown until the next CLKB cycle.", $time/1000.0, addrb_int); + + end + endtask + + always @(posedge setup_all_b_a) begin + if ((ena_int == 1) && (enb_reg == 1)) begin + case ({wea_int, web_reg}) + 6'b11 : begin data_collision_b_a <= 2'b11; display_all_b_a; end + 6'b01 : begin data_collision_b_a <= 2'b10; display_all_b_a; end + 6'b10 : begin data_collision_b_a <= 2'b01; display_all_b_a; end + endcase + end + setup_all_b_a <= 0; + end + + task display_all_b_a; + begin + address_collision_b_a = 1'b0; + for (ci = 0; ci < 8; ci = ci + 4) begin + if ((mem_addra_int) == (mem_addrb_reg + ci)) begin + address_collision_b_a = 1'b1; + end + end + if (address_collision_b_a == 1'b1) + + if (({wea_int, web_reg}) == 2'b11) + $display("Memory Collision Error on RAMB4_S4_S8:%m at simulation time %.3f ns\nA write was requested to the same address simultaneously at both Port A and Port B of the RAM. The contents written to the RAM at address location %h (hex) of Port A and address location %h (hex) of Port B are unknown.", $time/1000.0, addra_int, addrb_int); + + else if (({wea_int, web_reg}) == 2'b01) + $display("Memory Collision Error on RAMB4_S4_S8:%m at simulation time %.3f ns\nA read was performed on address %h (hex) of Port A while a write was requested to the same address on Port B. The write will be successful however the read value on Port A is unknown until the next CLKA cycle.", $time/1000.0, addra_int); + + else if (({wea_int, web_reg}) == 2'b10) + $display("Memory Collision Error on RAMB4_S4_S8:%m at simulation time %.3f ns\nA read was performed on address %h (hex) of Port B while a write was requested to the same address on Port A. The write will be successful however the read value on Port B is unknown until the next CLKB cycle.", $time/1000.0, addrb_int); + + end + endtask + + always @(posedge setup_zero) begin + if ((ena_int == 1) && (enb_int == 1)) begin + case ({wea_int, web_int}) + 6'b11 : begin data_collision <= 2'b11; display_zero; end + 6'b01 : begin data_collision <= 2'b10; display_zero; end + 6'b10 : begin data_collision <= 2'b01; display_zero; end + endcase + end + setup_zero <= 0; + end + + task display_zero; + begin + address_collision = 1'b0; + for (ci = 0; ci < 8; ci = ci + 4) begin + if ((mem_addra_int) == (mem_addrb_int + ci)) begin + address_collision = 1'b1; + end + end + if (address_collision == 1'b1) + + if (({wea_int, web_int}) == 2'b11) + $display("Memory Collision Error on RAMB4_S4_S8:%m at simulation time %.3f ns\nA write was requested to the same address simultaneously at both Port A and Port B of the RAM. The contents written to the RAM at address location %h (hex) of Port A and address location %h (hex) of Port B are unknown.", $time/1000.0, addra_int, addrb_int); + + else if (({wea_int, web_int}) == 2'b01) + $display("Memory Collision Error on RAMB4_S4_S8:%m at simulation time %.3f ns\nA read was performed on address %h (hex) of Port A while a write was requested to the same address on Port B. The write will be successful however the read value on Port A is unknown until the next CLKA cycle.", $time/1000.0, addra_int); + + else if (({wea_int, web_int}) == 2'b10) + $display("Memory Collision Error on RAMB4_S4_S8:%m at simulation time %.3f ns\nA read was performed on address %h (hex) of Port B while a write was requested to the same address on Port A. The write will be successful however the read value on Port B is unknown until the next CLKB cycle.", $time/1000.0, addrb_int); + + end + endtask + + always @(posedge clka_int) begin + addra_reg <= addra_int; + ena_reg <= ena_int; + rsta_reg <= rsta_int; + wea_reg <= wea_int; + end + + always @(posedge clkb_int) begin + addrb_reg <= addrb_int; + enb_reg <= enb_int; + rstb_reg <= rstb_int; + web_reg <= web_int; + end + + // Data + always @(posedge memory_collision) begin + for (mi = 0; mi < 8; mi = mi + 4) begin + if ((mem_addra_int) == (mem_addrb_int + mi)) begin + for (mj = 0; mj < 4; mj = mj + 1) begin + mem[mem_addrb_int + mi + mj] <= 1'bX; + end + end + end + memory_collision <= 0; + end + + always @(posedge memory_collision_a_b) begin + for (mi = 0; mi < 8; mi = mi + 4) begin + if ((mem_addra_reg) == (mem_addrb_int + mi)) begin + for (mj = 0; mj < 4; mj = mj + 1) begin + mem[mem_addrb_int + mi + mj] <= 1'bX; + end + end + end + memory_collision_a_b <= 0; + end + + always @(posedge memory_collision_b_a) begin + for (mi = 0; mi < 8; mi = mi + 4) begin + if ((mem_addra_int) == (mem_addrb_reg + mi)) begin + for (mj = 0; mj < 4; mj = mj + 1) begin + mem[mem_addrb_reg + mi + mj] <= 1'bX; + end + end + end + memory_collision_b_a <= 0; + end + + always @(posedge data_collision[1]) begin + if (rsta_int == 0) begin + for (ai = 0; ai < 8; ai = ai + 4) begin + if ((mem_addra_int) == (mem_addrb_int + ai)) begin + doa_out <= 4'bX; + end + end + end + data_collision[1] <= 0; + end + + always @(posedge data_collision[0]) begin + if (rstb_int == 0) begin + for (bi = 0; bi < 8; bi = bi + 4) begin + if ((mem_addra_int) == (mem_addrb_int + bi)) begin + for (bj = 0; bj < 4; bj = bj + 1) begin + dob_out[bi + bj] <= 1'bX; + end + end + end + end + data_collision[0] <= 0; + end + + always @(posedge data_collision_a_b[1]) begin + if (rsta_reg == 0) begin + for (ai = 0; ai < 8; ai = ai + 4) begin + if ((mem_addra_reg) == (mem_addrb_int + ai)) begin + doa_out <= 4'bX; + end + end + end + data_collision_a_b[1] <= 0; + end + + always @(posedge data_collision_a_b[0]) begin + if (rstb_int == 0) begin + for (bi = 0; bi < 8; bi = bi + 4) begin + if ((mem_addra_reg) == (mem_addrb_int + bi)) begin + for (bj = 0; bj < 4; bj = bj + 1) begin + dob_out[bi + bj] <= 1'bX; + end + end + end + end + data_collision_a_b[0] <= 0; + end + + always @(posedge data_collision_b_a[1]) begin + if (rsta_int == 0) begin + for (ai = 0; ai < 8; ai = ai + 4) begin + if ((mem_addra_int) == (mem_addrb_reg + ai)) begin + doa_out <= 4'bX; + end + end + end + data_collision_b_a[1] <= 0; + end + + always @(posedge data_collision_b_a[0]) begin + if (rstb_reg == 0) begin + for (bi = 0; bi < 8; bi = bi + 4) begin + if ((mem_addra_int) == (mem_addrb_reg + bi)) begin + for (bj = 0; bj < 4; bj = bj + 1) begin + dob_out[bi + bj] <= 1'bX; + end + end + end + end + data_collision_b_a[0] <= 0; + end + + + always @(posedge clka_int) begin + if (ena_int == 1'b1) begin + if (rsta_int == 1'b1) begin + doa_out <= 4'b0; + end + else if (wea_int == 0) begin + doa_out[0] <= mem[mem_addra_int + 0]; + doa_out[1] <= mem[mem_addra_int + 1]; + doa_out[2] <= mem[mem_addra_int + 2]; + doa_out[3] <= mem[mem_addra_int + 3]; + end + else begin + doa_out <= dia_int; + end + end + end + + always @(posedge clka_int) begin + if (ena_int == 1'b1 && wea_int == 1'b1) begin + mem[mem_addra_int + 0] <= dia_int[0]; + mem[mem_addra_int + 1] <= dia_int[1]; + mem[mem_addra_int + 2] <= dia_int[2]; + mem[mem_addra_int + 3] <= dia_int[3]; + end + end + + always @(posedge clkb_int) begin + if (enb_int == 1'b1) begin + if (rstb_int == 1'b1) begin + dob_out <= 8'b0; + end + else if (web_int == 0) begin + dob_out[0] <= mem[mem_addrb_int + 0]; + dob_out[1] <= mem[mem_addrb_int + 1]; + dob_out[2] <= mem[mem_addrb_int + 2]; + dob_out[3] <= mem[mem_addrb_int + 3]; + dob_out[4] <= mem[mem_addrb_int + 4]; + dob_out[5] <= mem[mem_addrb_int + 5]; + dob_out[6] <= mem[mem_addrb_int + 6]; + dob_out[7] <= mem[mem_addrb_int + 7]; + end + else begin + dob_out <= dib_int; + end + end + end + + always @(posedge clkb_int) begin + if (enb_int == 1'b1 && web_int == 1'b1) begin + mem[mem_addrb_int + 0] <= dib_int[0]; + mem[mem_addrb_int + 1] <= dib_int[1]; + mem[mem_addrb_int + 2] <= dib_int[2]; + mem[mem_addrb_int + 3] <= dib_int[3]; + mem[mem_addrb_int + 4] <= dib_int[4]; + mem[mem_addrb_int + 5] <= dib_int[5]; + mem[mem_addrb_int + 6] <= dib_int[6]; + mem[mem_addrb_int + 7] <= dib_int[7]; + end + end + + specify + (CLKA *> DOA) = (100, 100); + (CLKB *> DOB) = (100, 100); + endspecify + +endmodule + +`else + +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/RAMB4_S4_S8.v,v 1.9 2007/02/22 01:58:06 wloo Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2005 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Timing Simulation Library Component +// / / 16K-Bit Data and 2K-Bit Parity Dual Port Block RAM +// /___/ /\ Filename : RAMB4_S4_S8.v +// \ \ / \ Timestamp : Thu Mar 10 16:44:01 PST 2005 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 03/10/05 - Initialized outputs. +// 02/21/07 - Fixed parameter SIM_COLLISION_CHECK (CR 433281). +// End Revision + +`timescale 1 ps/1 ps + +module RAMB4_S4_S8 (DOA, DOB, ADDRA, ADDRB, CLKA, CLKB, DIA, DIB, ENA, ENB, RSTA, RSTB, WEA, WEB); + + parameter SIM_COLLISION_CHECK = "ALL"; + localparam SETUP_ALL = 100; + + parameter INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + + output [3:0] DOA; + output [7:0] DOB; + + input [9:0] ADDRA; + input [3:0] DIA; + input ENA, CLKA, WEA, RSTA; + input [8:0] ADDRB; + input [7:0] DIB; + input ENB, CLKB, WEB, RSTB; + + reg [3:0] doa_out = 0; + reg [7:0] dob_out = 0; + + reg [7:0] mem [511:0]; + + reg [8:0] count; + + reg [5:0] mi, ai, bi, bj, ci; + + wire [9:0] addra_int; + reg [9:0] addra_reg; + wire [3:0] dia_int; + wire ena_int, clka_int, wea_int, rsta_int; + reg ena_reg, wea_reg, rsta_reg; + wire [8:0] addrb_int; + reg [8:0] addrb_reg; + wire [7:0] dib_int; + wire enb_int, clkb_int, web_int, rstb_int; + reg display_flag, output_flag; + reg enb_reg, web_reg, rstb_reg; + + time time_clka, time_clkb; + time time_clka_clkb; + time time_clkb_clka; + + reg setup_all_a_b; + reg setup_all_b_a; + reg setup_zero; + reg [1:0] data_collision, data_collision_a_b, data_collision_b_a; + reg memory_collision, memory_collision_a_b, memory_collision_b_a; + reg address_collision, address_collision_a_b, address_collision_b_a; + reg change_clka; + reg change_clkb; + + wire [11:0] mem_addra_int; + wire [11:0] mem_addra_reg; + wire [11:0] mem_addrb_int; + wire [11:0] mem_addrb_reg; + + wire dia_enable = ena_int && wea_int; + wire dib_enable = enb_int && web_int; + + tri0 GSR = glbl.GSR; + wire gsr_int; + + buf b_gsr (gsr_int, GSR); + + buf b_doa [3:0] (DOA, doa_out); + buf b_addra [9:0] (addra_int, ADDRA); + buf b_dia [3:0] (dia_int, DIA); + buf b_ena (ena_int, ENA); + buf b_clka (clka_int, CLKA); + buf b_rsta (rsta_int, RSTA); + buf b_wea (wea_int, WEA); + + buf b_dob [7:0] (DOB, dob_out); + buf b_addrb [8:0] (addrb_int, ADDRB); + buf b_dib [7:0] (dib_int, DIB); + buf b_enb (enb_int, ENB); + buf b_clkb (clkb_int, CLKB); + buf b_rstb (rstb_int, RSTB); + buf b_web (web_int, WEB); + + + always @(gsr_int) + if (gsr_int) begin + assign doa_out = 0; + assign dob_out = 0; + end + else begin + deassign doa_out; + deassign dob_out; + end + + + initial begin + + for (count = 0; count < 32; count = count + 1) begin + mem[count] = INIT_00[(count * 8) +: 8]; + mem[32 * 1 + count] = INIT_01[(count * 8) +: 8]; + mem[32 * 2 + count] = INIT_02[(count * 8) +: 8]; + mem[32 * 3 + count] = INIT_03[(count * 8) +: 8]; + mem[32 * 4 + count] = INIT_04[(count * 8) +: 8]; + mem[32 * 5 + count] = INIT_05[(count * 8) +: 8]; + mem[32 * 6 + count] = INIT_06[(count * 8) +: 8]; + mem[32 * 7 + count] = INIT_07[(count * 8) +: 8]; + mem[32 * 8 + count] = INIT_08[(count * 8) +: 8]; + mem[32 * 9 + count] = INIT_09[(count * 8) +: 8]; + mem[32 * 10 + count] = INIT_0A[(count * 8) +: 8]; + mem[32 * 11 + count] = INIT_0B[(count * 8) +: 8]; + mem[32 * 12 + count] = INIT_0C[(count * 8) +: 8]; + mem[32 * 13 + count] = INIT_0D[(count * 8) +: 8]; + mem[32 * 14 + count] = INIT_0E[(count * 8) +: 8]; + mem[32 * 15 + count] = INIT_0F[(count * 8) +: 8]; + end + + change_clka <= 0; + change_clkb <= 0; + data_collision <= 0; + data_collision_a_b <= 0; + data_collision_b_a <= 0; + memory_collision <= 0; + memory_collision_a_b <= 0; + memory_collision_b_a <= 0; + setup_all_a_b <= 0; + setup_all_b_a <= 0; + setup_zero <= 0; + end + + assign mem_addra_int = addra_int * 4; + assign mem_addra_reg = addra_reg * 4; + assign mem_addrb_int = addrb_int * 8; + assign mem_addrb_reg = addrb_reg * 8; + + + initial begin + + display_flag = 1; + output_flag = 1; + + case (SIM_COLLISION_CHECK) + + "NONE" : begin + output_flag = 0; + display_flag = 0; + end + "WARNING_ONLY" : output_flag = 0; + "GENERATE_X_ONLY" : display_flag = 0; + "ALL" : ; + + default : begin + $display("Attribute Syntax Error : The Attribute SIM_COLLISION_CHECK on RAMB4_S4_S8 instance %m is set to %s. Legal values for this attribute are ALL, NONE, WARNING_ONLY or GENERATE_X_ONLY.", SIM_COLLISION_CHECK); + $finish; + end + + endcase // case(SIM_COLLISION_CHECK) + + end // initial begin + + + always @(posedge clka_int) begin + if ((output_flag || display_flag)) begin + time_clka = $time; + #0 time_clkb_clka = time_clka - time_clkb; + change_clka = ~change_clka; + end + end + + always @(posedge clkb_int) begin + if ((output_flag || display_flag)) begin + time_clkb = $time; + #0 time_clka_clkb = time_clkb - time_clka; + change_clkb = ~change_clkb; + end + end + + always @(change_clkb) begin + if ((0 < time_clka_clkb) && (time_clka_clkb < SETUP_ALL)) + setup_all_a_b = 1; + end + + always @(change_clka) begin + if ((0 < time_clkb_clka) && (time_clkb_clka < SETUP_ALL)) + setup_all_b_a = 1; + end + + always @(change_clkb or change_clka) begin + if ((time_clkb_clka == 0) && (time_clka_clkb == 0)) + setup_zero = 1; + end + + always @(posedge setup_zero) begin + if ((ena_int == 1) && (wea_int == 1) && + (enb_int == 1) && (web_int == 1)) + memory_collision <= 1; + end + + always @(posedge setup_all_a_b) begin + if ((ena_reg == 1) && (enb_int == 1)) begin + case ({wea_reg, web_int}) + 6'b11 : begin data_collision_a_b <= 2'b11; display_all_a_b; end + 6'b01 : begin data_collision_a_b <= 2'b10; display_all_a_b; end + 6'b10 : begin data_collision_a_b <= 2'b01; display_all_a_b; end + endcase + end + setup_all_a_b <= 0; + end + + task display_all_a_b; + begin + address_collision_a_b = 1'b0; + for (ci = 0; ci < 8; ci = ci + 4) begin + if ((mem_addra_reg) == (mem_addrb_int + ci)) begin + address_collision_a_b = 1'b1; + end + end + if (address_collision_a_b == 1'b1 && display_flag) + + if (({wea_reg, web_int}) == 2'b11) + $display("Memory Collision Error on RAMB4_S4_S8:%m at simulation time %.3f ns\nA write was requested to the same address simultaneously at both Port A and Port B of the RAM. The contents written to the RAM at address location %h (hex) of Port A and address location %h (hex) of Port B are unknown.", $time/1000.0, addra_int, addrb_int); + + else if (({wea_reg, web_int}) == 2'b01) + $display("Memory Collision Error on RAMB4_S4_S8:%m at simulation time %.3f ns\nA read was performed on address %h (hex) of Port A while a write was requested to the same address on Port B. The write will be successful however the read value on Port A is unknown until the next CLKA cycle.", $time/1000.0, addra_int); + + else if (({wea_reg, web_int}) == 2'b10) + $display("Memory Collision Error on RAMB4_S4_S8:%m at simulation time %.3f ns\nA read was performed on address %h (hex) of Port B while a write was requested to the same address on Port A. The write will be successful however the read value on Port B is unknown until the next CLKB cycle.", $time/1000.0, addrb_int); + + end + endtask + + always @(posedge setup_all_b_a) begin + if ((ena_int == 1) && (enb_reg == 1)) begin + case ({wea_int, web_reg}) + 6'b11 : begin data_collision_b_a <= 2'b11; display_all_b_a; end + 6'b01 : begin data_collision_b_a <= 2'b10; display_all_b_a; end + 6'b10 : begin data_collision_b_a <= 2'b01; display_all_b_a; end + endcase + end + setup_all_b_a <= 0; + end + + task display_all_b_a; + begin + address_collision_b_a = 1'b0; + for (ci = 0; ci < 8; ci = ci + 4) begin + if ((mem_addra_int) == (mem_addrb_reg + ci)) begin + address_collision_b_a = 1'b1; + end + end + if (address_collision_b_a == 1'b1 && display_flag) + + if (({wea_int, web_reg}) == 2'b11) + $display("Memory Collision Error on RAMB4_S4_S8:%m at simulation time %.3f ns\nA write was requested to the same address simultaneously at both Port A and Port B of the RAM. The contents written to the RAM at address location %h (hex) of Port A and address location %h (hex) of Port B are unknown.", $time/1000.0, addra_int, addrb_int); + + else if (({wea_int, web_reg}) == 2'b01) + $display("Memory Collision Error on RAMB4_S4_S8:%m at simulation time %.3f ns\nA read was performed on address %h (hex) of Port A while a write was requested to the same address on Port B. The write will be successful however the read value on Port A is unknown until the next CLKA cycle.", $time/1000.0, addra_int); + + else if (({wea_int, web_reg}) == 2'b10) + $display("Memory Collision Error on RAMB4_S4_S8:%m at simulation time %.3f ns\nA read was performed on address %h (hex) of Port B while a write was requested to the same address on Port A. The write will be successful however the read value on Port B is unknown until the next CLKB cycle.", $time/1000.0, addrb_int); + + end + endtask + + always @(posedge setup_zero) begin + if ((ena_int == 1) && (enb_int == 1)) begin + case ({wea_int, web_int}) + 6'b11 : begin data_collision <= 2'b11; display_zero; end + 6'b01 : begin data_collision <= 2'b10; display_zero; end + 6'b10 : begin data_collision <= 2'b01; display_zero; end + endcase + end + setup_zero <= 0; + end + + task display_zero; + begin + address_collision = 1'b0; + for (ci = 0; ci < 8; ci = ci + 4) begin + if ((mem_addra_int) == (mem_addrb_int + ci)) begin + address_collision = 1'b1; + end + end + if (address_collision == 1'b1 && display_flag) + + if (({wea_int, web_int}) == 2'b11) + $display("Memory Collision Error on RAMB4_S4_S8:%m at simulation time %.3f ns\nA write was requested to the same address simultaneously at both Port A and Port B of the RAM. The contents written to the RAM at address location %h (hex) of Port A and address location %h (hex) of Port B are unknown.", $time/1000.0, addra_int, addrb_int); + + else if (({wea_int, web_int}) == 2'b01) + $display("Memory Collision Error on RAMB4_S4_S8:%m at simulation time %.3f ns\nA read was performed on address %h (hex) of Port A while a write was requested to the same address on Port B. The write will be successful however the read value on Port A is unknown until the next CLKA cycle.", $time/1000.0, addra_int); + + else if (({wea_int, web_int}) == 2'b10) + $display("Memory Collision Error on RAMB4_S4_S8:%m at simulation time %.3f ns\nA read was performed on address %h (hex) of Port B while a write was requested to the same address on Port A. The write will be successful however the read value on Port B is unknown until the next CLKB cycle.", $time/1000.0, addrb_int); + + end + endtask + + always @(posedge clka_int) begin + if ((output_flag || display_flag)) begin + addra_reg <= addra_int; + ena_reg <= ena_int; + rsta_reg <= rsta_int; + wea_reg <= wea_int; + end + end + + always @(posedge clkb_int) begin + if ((output_flag || display_flag)) begin + addrb_reg <= addrb_int; + enb_reg <= enb_int; + rstb_reg <= rstb_int; + web_reg <= web_int; + end + end + + + // Data + always @(posedge memory_collision) begin + if ((output_flag || display_flag)) begin + for (mi = 0; mi < 8; mi = mi + 4) begin + if ((mem_addra_int) == (mem_addrb_int + mi)) begin + mem[addra_int[9:1]][addra_int[0:0] * 4 +: 4] <= 4'bx; + end + end + memory_collision <= 0; + end + end + + always @(posedge memory_collision_a_b) begin + if ((output_flag || display_flag)) begin + for (mi = 0; mi < 8; mi = mi + 4) begin + if ((mem_addra_reg) == (mem_addrb_int + mi)) begin + mem[addra_reg[9:1]][addra_reg[0:0] * 4 +: 4] <= 4'bx; + end + end + memory_collision_a_b <= 0; + end + end + + always @(posedge memory_collision_b_a) begin + if ((output_flag || display_flag)) begin + for (mi = 0; mi < 8; mi = mi + 4) begin + if ((mem_addra_int) == (mem_addrb_reg + mi)) begin + mem[addra_int[9:1]][addra_int[0:0] * 4 +: 4] <= 4'bx; + end + end + memory_collision_b_a <= 0; + end + end + + always @(posedge data_collision[1]) begin + if (rsta_int == 0 && output_flag) begin + for (ai = 0; ai < 8; ai = ai + 4) begin + if ((mem_addra_int) == (mem_addrb_int + ai)) begin + doa_out <= #100 4'bX; + end + end + end + data_collision[1] <= 0; + end + + always @(posedge data_collision[0]) begin + if (rstb_int == 0 && output_flag) begin + for (bi = 0; bi < 8; bi = bi + 4) begin + if ((mem_addra_int) == (mem_addrb_int + bi)) begin + for (bj = 0; bj < 4; bj = bj + 1) begin + dob_out[bi + bj] <= #100 1'bX; + end + end + end + end + data_collision[0] <= 0; + end + + always @(posedge data_collision_a_b[1]) begin + if (rsta_reg == 0 && output_flag) begin + for (ai = 0; ai < 8; ai = ai + 4) begin + if ((mem_addra_reg) == (mem_addrb_int + ai)) begin + doa_out <= #100 4'bX; + end + end + end + data_collision_a_b[1] <= 0; + end + + always @(posedge data_collision_a_b[0]) begin + if (rstb_int == 0 && output_flag) begin + for (bi = 0; bi < 8; bi = bi + 4) begin + if ((mem_addra_reg) == (mem_addrb_int + bi)) begin + for (bj = 0; bj < 4; bj = bj + 1) begin + dob_out[bi + bj] <= #100 1'bX; + end + end + end + end + data_collision_a_b[0] <= 0; + end + + always @(posedge data_collision_b_a[1]) begin + if (rsta_int == 0 && output_flag) begin + for (ai = 0; ai < 8; ai = ai + 4) begin + if ((mem_addra_int) == (mem_addrb_reg + ai)) begin + doa_out <= #100 4'bX; + end + end + end + data_collision_b_a[1] <= 0; + end + + always @(posedge data_collision_b_a[0]) begin + if (rstb_reg == 0 && output_flag) begin + for (bi = 0; bi < 8; bi = bi + 4) begin + if ((mem_addra_int) == (mem_addrb_reg + bi)) begin + for (bj = 0; bj < 4; bj = bj + 1) begin + dob_out[bi + bj] <= #100 1'bX; + end + end + end + end + data_collision_b_a[0] <= 0; + end + + + // Port A + always @(posedge clka_int) begin + + if (ena_int == 1'b1) begin + + if (rsta_int == 1'b1) begin + doa_out <= #100 0; + end + else begin + if (wea_int == 1'b1) + doa_out <= #100 dia_int; + else + doa_out <= #100 mem[addra_int[9:1]][addra_int[0:0] * 4 +: 4]; + end + + // memory + if (wea_int == 1'b1) begin + mem[addra_int[9:1]][addra_int[0:0] * 4 +: 4] <= dia_int; + end + + end + end + + + // Port B + always @(posedge clkb_int) begin + + if (enb_int == 1'b1) begin + + if (rstb_int == 1'b1) begin + dob_out <= #100 0; + end + else begin + if (web_int == 1'b1) + dob_out <= #100 dib_int; + else + dob_out <= #100 mem[addrb_int]; + end + + // memory + if (web_int == 1'b1) begin + mem[addrb_int] <= dib_int; + end + + end + end + + +endmodule + +`endif diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/RAMB4_S8.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/RAMB4_S8.v new file mode 100644 index 0000000..a678941 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/RAMB4_S8.v @@ -0,0 +1,330 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/RAMB4_S8.v,v 1.6 2005/03/14 22:54:42 wloo Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2005 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / 4K-Bit Data Single Port Block RAM +// /___/ /\ Filename : RAMB4_S8.v +// \ \ / \ Timestamp : Thu Mar 10 16:43:39 PST 2005 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// End Revision + +`ifdef legacy_model + +`timescale 1 ps / 1 ps + + +module RAMB4_S8 (DO, ADDR, CLK, DI, EN, RST, WE); + + parameter INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + + output [7:0] DO; + reg d0_out, d1_out, d2_out, d3_out, d4_out, d5_out, d6_out, d7_out; + + input [8:0] ADDR; + input [7:0] DI; + input EN, CLK, WE, RST; + + reg [4095:0] mem; + reg [8:0] count; + + wire [8:0] addr_int; + wire [7:0] di_int; + wire en_int, clk_int, we_int, rst_int; + + tri0 GSR = glbl.GSR; + + always @(GSR) + if (GSR) + begin + assign d0_out = 0; + assign d1_out = 0; + assign d2_out = 0; + assign d3_out = 0; + assign d4_out = 0; + assign d5_out = 0; + assign d6_out = 0; + assign d7_out = 0; + end + else + begin + deassign d0_out; + deassign d1_out; + deassign d2_out; + deassign d3_out; + deassign d4_out; + deassign d5_out; + deassign d6_out; + deassign d7_out; + end + + buf b_do_out0 (DO[0], d0_out); + buf b_do_out1 (DO[1], d1_out); + buf b_do_out2 (DO[2], d2_out); + buf b_do_out3 (DO[3], d3_out); + buf b_do_out4 (DO[4], d4_out); + buf b_do_out5 (DO[5], d5_out); + buf b_do_out6 (DO[6], d6_out); + buf b_do_out7 (DO[7], d7_out); + buf b_addr_0 (addr_int[0], ADDR[0]); + buf b_addr_1 (addr_int[1], ADDR[1]); + buf b_addr_2 (addr_int[2], ADDR[2]); + buf b_addr_3 (addr_int[3], ADDR[3]); + buf b_addr_4 (addr_int[4], ADDR[4]); + buf b_addr_5 (addr_int[5], ADDR[5]); + buf b_addr_6 (addr_int[6], ADDR[6]); + buf b_addr_7 (addr_int[7], ADDR[7]); + buf b_addr_8 (addr_int[8], ADDR[8]); + buf b_di_0 (di_int[0], DI[0]); + buf b_di_1 (di_int[1], DI[1]); + buf b_di_2 (di_int[2], DI[2]); + buf b_di_3 (di_int[3], DI[3]); + buf b_di_4 (di_int[4], DI[4]); + buf b_di_5 (di_int[5], DI[5]); + buf b_di_6 (di_int[6], DI[6]); + buf b_di_7 (di_int[7], DI[7]); + buf b_en (en_int, EN); + buf b_clk (clk_int, CLK); + buf b_we (we_int, WE); + buf b_rst (rst_int, RST); + + initial + begin + for (count = 0; count < 256; count = count + 1) + begin + mem[count] <= INIT_00[count]; + mem[256 * 1 + count] <= INIT_01[count]; + mem[256 * 2 + count] <= INIT_02[count]; + mem[256 * 3 + count] <= INIT_03[count]; + mem[256 * 4 + count] <= INIT_04[count]; + mem[256 * 5 + count] <= INIT_05[count]; + mem[256 * 6 + count] <= INIT_06[count]; + mem[256 * 7 + count] <= INIT_07[count]; + mem[256 * 8 + count] <= INIT_08[count]; + mem[256 * 9 + count] <= INIT_09[count]; + mem[256 * 10 + count] <= INIT_0A[count]; + mem[256 * 11 + count] <= INIT_0B[count]; + mem[256 * 12 + count] <= INIT_0C[count]; + mem[256 * 13 + count] <= INIT_0D[count]; + mem[256 * 14 + count] <= INIT_0E[count]; + mem[256 * 15 + count] <= INIT_0F[count]; + end + end + + always @(posedge clk_int) + begin + if (en_int == 1'b1) + if (rst_int == 1'b1) + begin + d0_out <= 0; + d1_out <= 0; + d2_out <= 0; + d3_out <= 0; + d4_out <= 0; + d5_out <= 0; + d6_out <= 0; + d7_out <= 0; + end + else + if (we_int == 1'b1) + begin + d0_out <= di_int[0]; + d1_out <= di_int[1]; + d2_out <= di_int[2]; + d3_out <= di_int[3]; + d4_out <= di_int[4]; + d5_out <= di_int[5]; + d6_out <= di_int[6]; + d7_out <= di_int[7]; + end + else + begin + d0_out <= mem[addr_int * 8]; + d1_out <= mem[addr_int * 8 + 1]; + d2_out <= mem[addr_int * 8 + 2]; + d3_out <= mem[addr_int * 8 + 3]; + d4_out <= mem[addr_int * 8 + 4]; + d5_out <= mem[addr_int * 8 + 5]; + d6_out <= mem[addr_int * 8 + 6]; + d7_out <= mem[addr_int * 8 + 7]; + end + end + + always @(posedge clk_int) + begin + if (en_int == 1'b1 && we_int == 1'b1) + begin + mem[addr_int * 8] <= di_int[0]; + mem[addr_int * 8 + 1] <= di_int[1]; + mem[addr_int * 8 + 2] <= di_int[2]; + mem[addr_int * 8 + 3] <= di_int[3]; + mem[addr_int * 8 + 4] <= di_int[4]; + mem[addr_int * 8 + 5] <= di_int[5]; + mem[addr_int * 8 + 6] <= di_int[6]; + mem[addr_int * 8 + 7] <= di_int[7]; + end + end + + specify + (CLK *> DO) = (100, 100); + endspecify + +endmodule + +`else + + +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/RAMB4_S8.v,v 1.6 2005/03/14 22:54:42 wloo Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2005 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Timing Simulation Library Component +// / / 16K-Bit Data and 2K-Bit Parity Single Port Block RAM +// /___/ /\ Filename : RAMB4_S8.v +// \ \ / \ Timestamp : Thu Mar 10 16:44:01 PST 2005 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 03/10/05 - Initialized outputs. +// End Revision + +`timescale 1 ps/1 ps + +module RAMB4_S8 (DO, ADDR, CLK, DI, EN, RST, WE); + + parameter INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + + output [7:0] DO; + + input [8:0] ADDR; + input [7:0] DI; + input EN, CLK, WE, RST; + + reg [7:0] do_out = 0; + + reg [7:0] mem [511:0]; + + reg [8:0] count; + + wire [8:0] addr_int; + wire [7:0] di_int; + wire en_int, clk_int, we_int, rst_int; + + wire di_enable = en_int && we_int; + + tri0 GSR = glbl.GSR; + wire gsr_int; + + buf b_gsr (gsr_int, GSR); + + buf b_do [7:0] (DO, do_out); + buf b_addr [8:0] (addr_int, ADDR); + buf b_di [7:0] (di_int, DI); + buf b_en (en_int, EN); + buf b_clk (clk_int, CLK); + buf b_rst (rst_int, RST); + buf b_we (we_int, WE); + + + always @(gsr_int) + if (gsr_int) begin + assign do_out = 0; + end + else begin + deassign do_out; + end + + + initial begin + + for (count = 0; count < 32; count = count + 1) begin + mem[count] = INIT_00[(count * 8) +: 8]; + mem[32 * 1 + count] = INIT_01[(count * 8) +: 8]; + mem[32 * 2 + count] = INIT_02[(count * 8) +: 8]; + mem[32 * 3 + count] = INIT_03[(count * 8) +: 8]; + mem[32 * 4 + count] = INIT_04[(count * 8) +: 8]; + mem[32 * 5 + count] = INIT_05[(count * 8) +: 8]; + mem[32 * 6 + count] = INIT_06[(count * 8) +: 8]; + mem[32 * 7 + count] = INIT_07[(count * 8) +: 8]; + mem[32 * 8 + count] = INIT_08[(count * 8) +: 8]; + mem[32 * 9 + count] = INIT_09[(count * 8) +: 8]; + mem[32 * 10 + count] = INIT_0A[(count * 8) +: 8]; + mem[32 * 11 + count] = INIT_0B[(count * 8) +: 8]; + mem[32 * 12 + count] = INIT_0C[(count * 8) +: 8]; + mem[32 * 13 + count] = INIT_0D[(count * 8) +: 8]; + mem[32 * 14 + count] = INIT_0E[(count * 8) +: 8]; + mem[32 * 15 + count] = INIT_0F[(count * 8) +: 8]; + end + + end // initial begin + + + always @(posedge clk_int) begin + + if (en_int == 1'b1) begin + + if (rst_int == 1'b1) + do_out <= #100 0; + + else + if (we_int == 1'b1) + do_out <= #100 di_int; + + else + do_out <= #100 mem[addr_int]; + + // memory + if (we_int == 1'b1) + mem[addr_int] <= di_int; + + end + end + + +endmodule + +`endif diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/RAMB4_S8_S16.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/RAMB4_S8_S16.v new file mode 100644 index 0000000..d933ef9 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/RAMB4_S8_S16.v @@ -0,0 +1,1143 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/RAMB4_S8_S16.v,v 1.9 2007/02/22 01:58:06 wloo Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2005 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / 4K-Bit Data Dual Port Block RAM +// /___/ /\ Filename : RAMB4_S8_S16.v +// \ \ / \ Timestamp : Thu Mar 10 16:43:39 PST 2005 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. + +// End Revision + +`ifdef legacy_model + +`timescale 1 ps / 1 ps + +module RAMB4_S8_S16 (DOA, DOB, ADDRA, ADDRB, CLKA, CLKB, DIA, DIB, ENA, ENB, RSTA, RSTB, WEA, WEB); + + parameter SIM_COLLISION_CHECK = "ALL"; + localparam SETUP_ALL = 100; + + parameter INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + + output [7:0] DOA; + reg [7:0] doa_out; + wire doa_out0, doa_out1, doa_out2, doa_out3, doa_out4, doa_out5, doa_out6, doa_out7; + + input [8:0] ADDRA; + input [7:0] DIA; + input ENA, CLKA, WEA, RSTA; + + output [15:0] DOB; + reg [15:0] dob_out; + wire dob_out0, dob_out1, dob_out2, dob_out3, dob_out4, dob_out5, dob_out6, dob_out7, dob_out8, dob_out9, dob_out10, dob_out11, dob_out12, dob_out13, dob_out14, dob_out15; + + input [7:0] ADDRB; + input [15:0] DIB; + input ENB, CLKB, WEB, RSTB; + + reg [4095:0] mem; + reg [8:0] count; + + reg [5:0] mi, mj, ai, aj, bi, bj, ci, cj, di, dj, ei, ej, fi, fj; + + wire [8:0] addra_int; + reg [8:0] addra_reg; + wire [7:0] dia_int; + wire ena_int, clka_int, wea_int, rsta_int; + reg ena_reg, wea_reg, rsta_reg; + wire [7:0] addrb_int; + reg [7:0] addrb_reg; + wire [15:0] dib_int; + wire enb_int, clkb_int, web_int, rstb_int; + reg enb_reg, web_reg, rstb_reg; + + time time_clka, time_clkb; + time time_clka_clkb; + time time_clkb_clka; + + reg setup_all_a_b; + reg setup_all_b_a; + reg setup_zero; + reg [1:0] data_collision, data_collision_a_b, data_collision_b_a; + reg memory_collision, memory_collision_a_b, memory_collision_b_a; + reg address_collision, address_collision_a_b, address_collision_b_a; + reg change_clka; + reg change_clkb; + + wire [11:0] mem_addra_int; + wire [11:0] mem_addra_reg; + wire [11:0] mem_addrb_int; + wire [11:0] mem_addrb_reg; + + tri0 GSR = glbl.GSR; + + always @(GSR) + if (GSR) begin + assign doa_out = 0; + end + else begin + deassign doa_out; + end + + always @(GSR) + if (GSR) begin + assign dob_out = 0; + end + else begin + deassign dob_out; + end + + buf b_doa_out0 (doa_out0, doa_out[0]); + buf b_doa_out1 (doa_out1, doa_out[1]); + buf b_doa_out2 (doa_out2, doa_out[2]); + buf b_doa_out3 (doa_out3, doa_out[3]); + buf b_doa_out4 (doa_out4, doa_out[4]); + buf b_doa_out5 (doa_out5, doa_out[5]); + buf b_doa_out6 (doa_out6, doa_out[6]); + buf b_doa_out7 (doa_out7, doa_out[7]); + buf b_dob_out0 (dob_out0, dob_out[0]); + buf b_dob_out1 (dob_out1, dob_out[1]); + buf b_dob_out2 (dob_out2, dob_out[2]); + buf b_dob_out3 (dob_out3, dob_out[3]); + buf b_dob_out4 (dob_out4, dob_out[4]); + buf b_dob_out5 (dob_out5, dob_out[5]); + buf b_dob_out6 (dob_out6, dob_out[6]); + buf b_dob_out7 (dob_out7, dob_out[7]); + buf b_dob_out8 (dob_out8, dob_out[8]); + buf b_dob_out9 (dob_out9, dob_out[9]); + buf b_dob_out10 (dob_out10, dob_out[10]); + buf b_dob_out11 (dob_out11, dob_out[11]); + buf b_dob_out12 (dob_out12, dob_out[12]); + buf b_dob_out13 (dob_out13, dob_out[13]); + buf b_dob_out14 (dob_out14, dob_out[14]); + buf b_dob_out15 (dob_out15, dob_out[15]); + buf b_doa0 (DOA[0], doa_out0); + buf b_doa1 (DOA[1], doa_out1); + buf b_doa2 (DOA[2], doa_out2); + buf b_doa3 (DOA[3], doa_out3); + buf b_doa4 (DOA[4], doa_out4); + buf b_doa5 (DOA[5], doa_out5); + buf b_doa6 (DOA[6], doa_out6); + buf b_doa7 (DOA[7], doa_out7); + buf b_dob0 (DOB[0], dob_out0); + buf b_dob1 (DOB[1], dob_out1); + buf b_dob2 (DOB[2], dob_out2); + buf b_dob3 (DOB[3], dob_out3); + buf b_dob4 (DOB[4], dob_out4); + buf b_dob5 (DOB[5], dob_out5); + buf b_dob6 (DOB[6], dob_out6); + buf b_dob7 (DOB[7], dob_out7); + buf b_dob8 (DOB[8], dob_out8); + buf b_dob9 (DOB[9], dob_out9); + buf b_dob10 (DOB[10], dob_out10); + buf b_dob11 (DOB[11], dob_out11); + buf b_dob12 (DOB[12], dob_out12); + buf b_dob13 (DOB[13], dob_out13); + buf b_dob14 (DOB[14], dob_out14); + buf b_dob15 (DOB[15], dob_out15); + buf b_addra_0 (addra_int[0], ADDRA[0]); + buf b_addra_1 (addra_int[1], ADDRA[1]); + buf b_addra_2 (addra_int[2], ADDRA[2]); + buf b_addra_3 (addra_int[3], ADDRA[3]); + buf b_addra_4 (addra_int[4], ADDRA[4]); + buf b_addra_5 (addra_int[5], ADDRA[5]); + buf b_addra_6 (addra_int[6], ADDRA[6]); + buf b_addra_7 (addra_int[7], ADDRA[7]); + buf b_addra_8 (addra_int[8], ADDRA[8]); + buf b_dia_0 (dia_int[0], DIA[0]); + buf b_dia_1 (dia_int[1], DIA[1]); + buf b_dia_2 (dia_int[2], DIA[2]); + buf b_dia_3 (dia_int[3], DIA[3]); + buf b_dia_4 (dia_int[4], DIA[4]); + buf b_dia_5 (dia_int[5], DIA[5]); + buf b_dia_6 (dia_int[6], DIA[6]); + buf b_dia_7 (dia_int[7], DIA[7]); + buf b_clka (clka_int, CLKA); + buf b_ena (ena_int, ENA); + buf b_rsta (rsta_int, RSTA); + buf b_wea (wea_int, WEA); + buf b_addrb_0 (addrb_int[0], ADDRB[0]); + buf b_addrb_1 (addrb_int[1], ADDRB[1]); + buf b_addrb_2 (addrb_int[2], ADDRB[2]); + buf b_addrb_3 (addrb_int[3], ADDRB[3]); + buf b_addrb_4 (addrb_int[4], ADDRB[4]); + buf b_addrb_5 (addrb_int[5], ADDRB[5]); + buf b_addrb_6 (addrb_int[6], ADDRB[6]); + buf b_addrb_7 (addrb_int[7], ADDRB[7]); + buf b_dib_0 (dib_int[0], DIB[0]); + buf b_dib_1 (dib_int[1], DIB[1]); + buf b_dib_2 (dib_int[2], DIB[2]); + buf b_dib_3 (dib_int[3], DIB[3]); + buf b_dib_4 (dib_int[4], DIB[4]); + buf b_dib_5 (dib_int[5], DIB[5]); + buf b_dib_6 (dib_int[6], DIB[6]); + buf b_dib_7 (dib_int[7], DIB[7]); + buf b_dib_8 (dib_int[8], DIB[8]); + buf b_dib_9 (dib_int[9], DIB[9]); + buf b_dib_10 (dib_int[10], DIB[10]); + buf b_dib_11 (dib_int[11], DIB[11]); + buf b_dib_12 (dib_int[12], DIB[12]); + buf b_dib_13 (dib_int[13], DIB[13]); + buf b_dib_14 (dib_int[14], DIB[14]); + buf b_dib_15 (dib_int[15], DIB[15]); + buf b_clkb (clkb_int, CLKB); + buf b_enb (enb_int, ENB); + buf b_rstb (rstb_int, RSTB); + buf b_web (web_int, WEB); + + initial begin + for (count = 0; count < 256; count = count + 1) begin + mem[count] <= INIT_00[count]; + mem[256 * 1 + count] <= INIT_01[count]; + mem[256 * 2 + count] <= INIT_02[count]; + mem[256 * 3 + count] <= INIT_03[count]; + mem[256 * 4 + count] <= INIT_04[count]; + mem[256 * 5 + count] <= INIT_05[count]; + mem[256 * 6 + count] <= INIT_06[count]; + mem[256 * 7 + count] <= INIT_07[count]; + mem[256 * 8 + count] <= INIT_08[count]; + mem[256 * 9 + count] <= INIT_09[count]; + mem[256 * 10 + count] <= INIT_0A[count]; + mem[256 * 11 + count] <= INIT_0B[count]; + mem[256 * 12 + count] <= INIT_0C[count]; + mem[256 * 13 + count] <= INIT_0D[count]; + mem[256 * 14 + count] <= INIT_0E[count]; + mem[256 * 15 + count] <= INIT_0F[count]; + end + address_collision <= 0; + address_collision_a_b <= 0; + address_collision_b_a <= 0; + change_clka <= 0; + change_clkb <= 0; + data_collision <= 0; + data_collision_a_b <= 0; + data_collision_b_a <= 0; + memory_collision <= 0; + memory_collision_a_b <= 0; + memory_collision_b_a <= 0; + setup_all_a_b <= 0; + setup_all_b_a <= 0; + setup_zero <= 0; + end + + assign mem_addra_int = addra_int * 8; + assign mem_addra_reg = addra_reg * 8; + assign mem_addrb_int = addrb_int * 16; + assign mem_addrb_reg = addrb_reg * 16; + + + initial begin + + case (SIM_COLLISION_CHECK) + + "NONE" : begin + assign setup_all_a_b = 1'b0; + assign setup_all_b_a = 1'b0; + assign setup_zero = 1'b0; + assign address_collision = 1'b0; + assign address_collision_a_b = 1'b0; + assign address_collision_b_a = 1'b0; + end + "WARNING_ONLY" : begin + assign data_collision = 2'b00; + assign data_collision_a_b = 2'b00; + assign data_collision_b_a = 2'b00; + assign memory_collision = 1'b0; + assign memory_collision_a_b = 1'b0; + assign memory_collision_b_a = 1'b0; + end + "GENERATE_X_ONLY" : begin + assign address_collision = 1'b0; + assign address_collision_a_b = 1'b0; + assign address_collision_b_a = 1'b0; + end + "ALL" : ; + default : begin + $display("Attribute Syntax Error : The Attribute SIM_COLLISION_CHECK on RAMB4_S8_S16 instance %m is set to %s. Legal values for this attribute are ALL, NONE, WARNING_ONLY or GENERATE_X_ONLY.", SIM_COLLISION_CHECK); + $finish; + end + + endcase // case(SIM_COLLISION_CHECK) + + end // initial begin + + + always @(posedge clka_int) begin + time_clka = $time; + #0 time_clkb_clka = time_clka - time_clkb; + change_clka = ~change_clka; + end + + always @(posedge clkb_int) begin + time_clkb = $time; + #0 time_clka_clkb = time_clkb - time_clka; + change_clkb = ~change_clkb; + end + + always @(change_clkb) begin + if ((0 < time_clka_clkb) && (time_clka_clkb < SETUP_ALL)) + setup_all_a_b = 1; + end + + always @(change_clka) begin + if ((0 < time_clkb_clka) && (time_clkb_clka < SETUP_ALL)) + setup_all_b_a = 1; + end + + always @(change_clkb or change_clka) begin + if ((time_clkb_clka == 0) && (time_clka_clkb == 0)) + setup_zero = 1; + end + + always @(posedge setup_zero) begin + if ((ena_int == 1) && (wea_int == 1) && + (enb_int == 1) && (web_int == 1)) + memory_collision <= 1; + end + + always @(posedge setup_all_a_b) begin + if ((ena_reg == 1) && (enb_int == 1)) begin + case ({wea_reg, web_int}) + 6'b11 : begin data_collision_a_b <= 2'b11; display_all_a_b; end + 6'b01 : begin data_collision_a_b <= 2'b10; display_all_a_b; end + 6'b10 : begin data_collision_a_b <= 2'b01; display_all_a_b; end + endcase + end + setup_all_a_b <= 0; + end + + task display_all_a_b; + begin + address_collision_a_b = 1'b0; + for (ci = 0; ci < 16; ci = ci + 8) begin + if ((mem_addra_reg) == (mem_addrb_int + ci)) begin + address_collision_a_b = 1'b1; + end + end + if (address_collision_a_b == 1'b1) + + if (({wea_reg, web_int}) == 2'b11) + $display("Memory Collision Error on RAMB4_S8_S16:%m at simulation time %.3f ns\nA write was requested to the same address simultaneously at both Port A and Port B of the RAM. The contents written to the RAM at address location %h (hex) of Port A and address location %h (hex) of Port B are unknown.", $time/1000.0, addra_int, addrb_int); + + else if (({wea_reg, web_int}) == 2'b01) + $display("Memory Collision Error on RAMB4_S8_S16:%m at simulation time %.3f ns\nA read was performed on address %h (hex) of Port A while a write was requested to the same address on Port B. The write will be successful however the read value on Port A is unknown until the next CLKA cycle.", $time/1000.0, addra_int); + + else if (({wea_reg, web_int}) == 2'b10) + $display("Memory Collision Error on RAMB4_S8_S16:%m at simulation time %.3f ns\nA read was performed on address %h (hex) of Port B while a write was requested to the same address on Port A. The write will be successful however the read value on Port B is unknown until the next CLKB cycle.", $time/1000.0, addrb_int); + + end + endtask + + always @(posedge setup_all_b_a) begin + if ((ena_int == 1) && (enb_reg == 1)) begin + case ({wea_int, web_reg}) + 6'b11 : begin data_collision_b_a <= 2'b11; display_all_b_a; end + 6'b01 : begin data_collision_b_a <= 2'b10; display_all_b_a; end + 6'b10 : begin data_collision_b_a <= 2'b01; display_all_b_a; end + endcase + end + setup_all_b_a <= 0; + end + + task display_all_b_a; + begin + address_collision_b_a = 1'b0; + for (ci = 0; ci < 16; ci = ci + 8) begin + if ((mem_addra_int) == (mem_addrb_reg + ci)) begin + address_collision_b_a = 1'b1; + end + end + if (address_collision_b_a == 1'b1) + + if (({wea_int, web_reg}) == 2'b11) + $display("Memory Collision Error on RAMB4_S8_S16:%m at simulation time %.3f ns\nA write was requested to the same address simultaneously at both Port A and Port B of the RAM. The contents written to the RAM at address location %h (hex) of Port A and address location %h (hex) of Port B are unknown.", $time/1000.0, addra_int, addrb_int); + + else if (({wea_int, web_reg}) == 2'b01) + $display("Memory Collision Error on RAMB4_S8_S16:%m at simulation time %.3f ns\nA read was performed on address %h (hex) of Port A while a write was requested to the same address on Port B. The write will be successful however the read value on Port A is unknown until the next CLKA cycle.", $time/1000.0, addra_int); + + else if (({wea_int, web_reg}) == 2'b10) + $display("Memory Collision Error on RAMB4_S8_S16:%m at simulation time %.3f ns\nA read was performed on address %h (hex) of Port B while a write was requested to the same address on Port A. The write will be successful however the read value on Port B is unknown until the next CLKB cycle.", $time/1000.0, addrb_int); + + end + endtask + + always @(posedge setup_zero) begin + if ((ena_int == 1) && (enb_int == 1)) begin + case ({wea_int, web_int}) + 6'b11 : begin data_collision <= 2'b11; display_zero; end + 6'b01 : begin data_collision <= 2'b10; display_zero; end + 6'b10 : begin data_collision <= 2'b01; display_zero; end + endcase + end + setup_zero <= 0; + end + + task display_zero; + begin + address_collision = 1'b0; + for (ci = 0; ci < 16; ci = ci + 8) begin + if ((mem_addra_int) == (mem_addrb_int + ci)) begin + address_collision = 1'b1; + end + end + if (address_collision == 1'b1) + + if (({wea_int, web_int}) == 2'b11) + $display("Memory Collision Error on RAMB4_S8_S16:%m at simulation time %.3f ns\nA write was requested to the same address simultaneously at both Port A and Port B of the RAM. The contents written to the RAM at address location %h (hex) of Port A and address location %h (hex) of Port B are unknown.", $time/1000.0, addra_int, addrb_int); + + else if (({wea_int, web_int}) == 2'b01) + $display("Memory Collision Error on RAMB4_S8_S16:%m at simulation time %.3f ns\nA read was performed on address %h (hex) of Port A while a write was requested to the same address on Port B. The write will be successful however the read value on Port A is unknown until the next CLKA cycle.", $time/1000.0, addra_int); + + else if (({wea_int, web_int}) == 2'b10) + $display("Memory Collision Error on RAMB4_S8_S16:%m at simulation time %.3f ns\nA read was performed on address %h (hex) of Port B while a write was requested to the same address on Port A. The write will be successful however the read value on Port B is unknown until the next CLKB cycle.", $time/1000.0, addrb_int); + + end + endtask + + always @(posedge clka_int) begin + addra_reg <= addra_int; + ena_reg <= ena_int; + rsta_reg <= rsta_int; + wea_reg <= wea_int; + end + + always @(posedge clkb_int) begin + addrb_reg <= addrb_int; + enb_reg <= enb_int; + rstb_reg <= rstb_int; + web_reg <= web_int; + end + + // Data + always @(posedge memory_collision) begin + for (mi = 0; mi < 16; mi = mi + 8) begin + if ((mem_addra_int) == (mem_addrb_int + mi)) begin + for (mj = 0; mj < 8; mj = mj + 1) begin + mem[mem_addrb_int + mi + mj] <= 1'bX; + end + end + end + memory_collision <= 0; + end + + always @(posedge memory_collision_a_b) begin + for (mi = 0; mi < 16; mi = mi + 8) begin + if ((mem_addra_reg) == (mem_addrb_int + mi)) begin + for (mj = 0; mj < 8; mj = mj + 1) begin + mem[mem_addrb_int + mi + mj] <= 1'bX; + end + end + end + memory_collision_a_b <= 0; + end + + always @(posedge memory_collision_b_a) begin + for (mi = 0; mi < 16; mi = mi + 8) begin + if ((mem_addra_int) == (mem_addrb_reg + mi)) begin + for (mj = 0; mj < 8; mj = mj + 1) begin + mem[mem_addrb_reg + mi + mj] <= 1'bX; + end + end + end + memory_collision_b_a <= 0; + end + + always @(posedge data_collision[1]) begin + if (rsta_int == 0) begin + for (ai = 0; ai < 16; ai = ai + 8) begin + if ((mem_addra_int) == (mem_addrb_int + ai)) begin + doa_out <= 8'bX; + end + end + end + data_collision[1] <= 0; + end + + always @(posedge data_collision[0]) begin + if (rstb_int == 0) begin + for (bi = 0; bi < 16; bi = bi + 8) begin + if ((mem_addra_int) == (mem_addrb_int + bi)) begin + for (bj = 0; bj < 8; bj = bj + 1) begin + dob_out[bi + bj] <= 1'bX; + end + end + end + end + data_collision[0] <= 0; + end + + always @(posedge data_collision_a_b[1]) begin + if (rsta_reg == 0) begin + for (ai = 0; ai < 16; ai = ai + 8) begin + if ((mem_addra_reg) == (mem_addrb_int + ai)) begin + doa_out <= 8'bX; + end + end + end + data_collision_a_b[1] <= 0; + end + + always @(posedge data_collision_a_b[0]) begin + if (rstb_int == 0) begin + for (bi = 0; bi < 16; bi = bi + 8) begin + if ((mem_addra_reg) == (mem_addrb_int + bi)) begin + for (bj = 0; bj < 8; bj = bj + 1) begin + dob_out[bi + bj] <= 1'bX; + end + end + end + end + data_collision_a_b[0] <= 0; + end + + always @(posedge data_collision_b_a[1]) begin + if (rsta_int == 0) begin + for (ai = 0; ai < 16; ai = ai + 8) begin + if ((mem_addra_int) == (mem_addrb_reg + ai)) begin + doa_out <= 8'bX; + end + end + end + data_collision_b_a[1] <= 0; + end + + always @(posedge data_collision_b_a[0]) begin + if (rstb_reg == 0) begin + for (bi = 0; bi < 16; bi = bi + 8) begin + if ((mem_addra_int) == (mem_addrb_reg + bi)) begin + for (bj = 0; bj < 8; bj = bj + 1) begin + dob_out[bi + bj] <= 1'bX; + end + end + end + end + data_collision_b_a[0] <= 0; + end + + + always @(posedge clka_int) begin + if (ena_int == 1'b1) begin + if (rsta_int == 1'b1) begin + doa_out <= 8'b0; + end + else if (wea_int == 0) begin + doa_out[0] <= mem[mem_addra_int + 0]; + doa_out[1] <= mem[mem_addra_int + 1]; + doa_out[2] <= mem[mem_addra_int + 2]; + doa_out[3] <= mem[mem_addra_int + 3]; + doa_out[4] <= mem[mem_addra_int + 4]; + doa_out[5] <= mem[mem_addra_int + 5]; + doa_out[6] <= mem[mem_addra_int + 6]; + doa_out[7] <= mem[mem_addra_int + 7]; + end + else begin + doa_out <= dia_int; + end + end + end + + always @(posedge clka_int) begin + if (ena_int == 1'b1 && wea_int == 1'b1) begin + mem[mem_addra_int + 0] <= dia_int[0]; + mem[mem_addra_int + 1] <= dia_int[1]; + mem[mem_addra_int + 2] <= dia_int[2]; + mem[mem_addra_int + 3] <= dia_int[3]; + mem[mem_addra_int + 4] <= dia_int[4]; + mem[mem_addra_int + 5] <= dia_int[5]; + mem[mem_addra_int + 6] <= dia_int[6]; + mem[mem_addra_int + 7] <= dia_int[7]; + end + end + + always @(posedge clkb_int) begin + if (enb_int == 1'b1) begin + if (rstb_int == 1'b1) begin + dob_out <= 16'b0; + end + else if (web_int == 0) begin + dob_out[0] <= mem[mem_addrb_int + 0]; + dob_out[1] <= mem[mem_addrb_int + 1]; + dob_out[2] <= mem[mem_addrb_int + 2]; + dob_out[3] <= mem[mem_addrb_int + 3]; + dob_out[4] <= mem[mem_addrb_int + 4]; + dob_out[5] <= mem[mem_addrb_int + 5]; + dob_out[6] <= mem[mem_addrb_int + 6]; + dob_out[7] <= mem[mem_addrb_int + 7]; + dob_out[8] <= mem[mem_addrb_int + 8]; + dob_out[9] <= mem[mem_addrb_int + 9]; + dob_out[10] <= mem[mem_addrb_int + 10]; + dob_out[11] <= mem[mem_addrb_int + 11]; + dob_out[12] <= mem[mem_addrb_int + 12]; + dob_out[13] <= mem[mem_addrb_int + 13]; + dob_out[14] <= mem[mem_addrb_int + 14]; + dob_out[15] <= mem[mem_addrb_int + 15]; + end + else begin + dob_out <= dib_int; + end + end + end + + always @(posedge clkb_int) begin + if (enb_int == 1'b1 && web_int == 1'b1) begin + mem[mem_addrb_int + 0] <= dib_int[0]; + mem[mem_addrb_int + 1] <= dib_int[1]; + mem[mem_addrb_int + 2] <= dib_int[2]; + mem[mem_addrb_int + 3] <= dib_int[3]; + mem[mem_addrb_int + 4] <= dib_int[4]; + mem[mem_addrb_int + 5] <= dib_int[5]; + mem[mem_addrb_int + 6] <= dib_int[6]; + mem[mem_addrb_int + 7] <= dib_int[7]; + mem[mem_addrb_int + 8] <= dib_int[8]; + mem[mem_addrb_int + 9] <= dib_int[9]; + mem[mem_addrb_int + 10] <= dib_int[10]; + mem[mem_addrb_int + 11] <= dib_int[11]; + mem[mem_addrb_int + 12] <= dib_int[12]; + mem[mem_addrb_int + 13] <= dib_int[13]; + mem[mem_addrb_int + 14] <= dib_int[14]; + mem[mem_addrb_int + 15] <= dib_int[15]; + end + end + + specify + (CLKA *> DOA) = (100, 100); + (CLKB *> DOB) = (100, 100); + endspecify + +endmodule + +`else + +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/RAMB4_S8_S16.v,v 1.9 2007/02/22 01:58:06 wloo Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2005 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Timing Simulation Library Component +// / / 16K-Bit Data and 2K-Bit Parity Dual Port Block RAM +// /___/ /\ Filename : RAMB4_S8_S16.v +// \ \ / \ Timestamp : Thu Mar 10 16:44:01 PST 2005 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 03/10/05 - Initialized outputs. +// 02/21/07 - Fixed parameter SIM_COLLISION_CHECK (CR 433281). +// End Revision + +`timescale 1 ps/1 ps + +module RAMB4_S8_S16 (DOA, DOB, ADDRA, ADDRB, CLKA, CLKB, DIA, DIB, ENA, ENB, RSTA, RSTB, WEA, WEB); + + parameter SIM_COLLISION_CHECK = "ALL"; + localparam SETUP_ALL = 100; + + parameter INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + + output [7:0] DOA; + output [15:0] DOB; + + input [8:0] ADDRA; + input [7:0] DIA; + input ENA, CLKA, WEA, RSTA; + input [7:0] ADDRB; + input [15:0] DIB; + input ENB, CLKB, WEB, RSTB; + + reg [7:0] doa_out = 0; + reg [15:0] dob_out = 0; + + reg [15:0] mem [255:0]; + + reg [8:0] count; + + reg [5:0] mi, ai, bi, bj, ci; + + wire [8:0] addra_int; + reg [8:0] addra_reg; + wire [7:0] dia_int; + wire ena_int, clka_int, wea_int, rsta_int; + reg ena_reg, wea_reg, rsta_reg; + wire [7:0] addrb_int; + reg [7:0] addrb_reg; + wire [15:0] dib_int; + wire enb_int, clkb_int, web_int, rstb_int; + reg display_flag, output_flag; + reg enb_reg, web_reg, rstb_reg; + + time time_clka, time_clkb; + time time_clka_clkb; + time time_clkb_clka; + + reg setup_all_a_b; + reg setup_all_b_a; + reg setup_zero; + reg [1:0] data_collision, data_collision_a_b, data_collision_b_a; + reg memory_collision, memory_collision_a_b, memory_collision_b_a; + reg address_collision, address_collision_a_b, address_collision_b_a; + reg change_clka; + reg change_clkb; + + wire [11:0] mem_addra_int; + wire [11:0] mem_addra_reg; + wire [11:0] mem_addrb_int; + wire [11:0] mem_addrb_reg; + + wire dia_enable = ena_int && wea_int; + wire dib_enable = enb_int && web_int; + + tri0 GSR = glbl.GSR; + wire gsr_int; + + buf b_gsr (gsr_int, GSR); + + buf b_doa [7:0] (DOA, doa_out); + buf b_addra [8:0] (addra_int, ADDRA); + buf b_dia [7:0] (dia_int, DIA); + buf b_ena (ena_int, ENA); + buf b_clka (clka_int, CLKA); + buf b_rsta (rsta_int, RSTA); + buf b_wea (wea_int, WEA); + + buf b_dob [15:0] (DOB, dob_out); + buf b_addrb [7:0] (addrb_int, ADDRB); + buf b_dib [15:0] (dib_int, DIB); + buf b_enb (enb_int, ENB); + buf b_clkb (clkb_int, CLKB); + buf b_rstb (rstb_int, RSTB); + buf b_web (web_int, WEB); + + + always @(gsr_int) + if (gsr_int) begin + assign doa_out = 0; + assign dob_out = 0; + end + else begin + deassign doa_out; + deassign dob_out; + end + + + initial begin + + for (count = 0; count < 16; count = count + 1) begin + mem[count] = INIT_00[(count * 16) +: 16]; + mem[16 * 1 + count] = INIT_01[(count * 16) +: 16]; + mem[16 * 2 + count] = INIT_02[(count * 16) +: 16]; + mem[16 * 3 + count] = INIT_03[(count * 16) +: 16]; + mem[16 * 4 + count] = INIT_04[(count * 16) +: 16]; + mem[16 * 5 + count] = INIT_05[(count * 16) +: 16]; + mem[16 * 6 + count] = INIT_06[(count * 16) +: 16]; + mem[16 * 7 + count] = INIT_07[(count * 16) +: 16]; + mem[16 * 8 + count] = INIT_08[(count * 16) +: 16]; + mem[16 * 9 + count] = INIT_09[(count * 16) +: 16]; + mem[16 * 10 + count] = INIT_0A[(count * 16) +: 16]; + mem[16 * 11 + count] = INIT_0B[(count * 16) +: 16]; + mem[16 * 12 + count] = INIT_0C[(count * 16) +: 16]; + mem[16 * 13 + count] = INIT_0D[(count * 16) +: 16]; + mem[16 * 14 + count] = INIT_0E[(count * 16) +: 16]; + mem[16 * 15 + count] = INIT_0F[(count * 16) +: 16]; + end + + change_clka <= 0; + change_clkb <= 0; + data_collision <= 0; + data_collision_a_b <= 0; + data_collision_b_a <= 0; + memory_collision <= 0; + memory_collision_a_b <= 0; + memory_collision_b_a <= 0; + setup_all_a_b <= 0; + setup_all_b_a <= 0; + setup_zero <= 0; + end + + assign mem_addra_int = addra_int * 8; + assign mem_addra_reg = addra_reg * 8; + assign mem_addrb_int = addrb_int * 16; + assign mem_addrb_reg = addrb_reg * 16; + + + initial begin + + display_flag = 1; + output_flag = 1; + + case (SIM_COLLISION_CHECK) + + "NONE" : begin + output_flag = 0; + display_flag = 0; + end + "WARNING_ONLY" : output_flag = 0; + "GENERATE_X_ONLY" : display_flag = 0; + "ALL" : ; + + default : begin + $display("Attribute Syntax Error : The Attribute SIM_COLLISION_CHECK on RAMB4_S8_S16 instance %m is set to %s. Legal values for this attribute are ALL, NONE, WARNING_ONLY or GENERATE_X_ONLY.", SIM_COLLISION_CHECK); + $finish; + end + + endcase // case(SIM_COLLISION_CHECK) + + end // initial begin + + + always @(posedge clka_int) begin + if ((output_flag || display_flag)) begin + time_clka = $time; + #0 time_clkb_clka = time_clka - time_clkb; + change_clka = ~change_clka; + end + end + + always @(posedge clkb_int) begin + if ((output_flag || display_flag)) begin + time_clkb = $time; + #0 time_clka_clkb = time_clkb - time_clka; + change_clkb = ~change_clkb; + end + end + + always @(change_clkb) begin + if ((0 < time_clka_clkb) && (time_clka_clkb < SETUP_ALL)) + setup_all_a_b = 1; + end + + always @(change_clka) begin + if ((0 < time_clkb_clka) && (time_clkb_clka < SETUP_ALL)) + setup_all_b_a = 1; + end + + always @(change_clkb or change_clka) begin + if ((time_clkb_clka == 0) && (time_clka_clkb == 0)) + setup_zero = 1; + end + + always @(posedge setup_zero) begin + if ((ena_int == 1) && (wea_int == 1) && + (enb_int == 1) && (web_int == 1)) + memory_collision <= 1; + end + + always @(posedge setup_all_a_b) begin + if ((ena_reg == 1) && (enb_int == 1)) begin + case ({wea_reg, web_int}) + 6'b11 : begin data_collision_a_b <= 2'b11; display_all_a_b; end + 6'b01 : begin data_collision_a_b <= 2'b10; display_all_a_b; end + 6'b10 : begin data_collision_a_b <= 2'b01; display_all_a_b; end + endcase + end + setup_all_a_b <= 0; + end + + task display_all_a_b; + begin + address_collision_a_b = 1'b0; + for (ci = 0; ci < 16; ci = ci + 8) begin + if ((mem_addra_reg) == (mem_addrb_int + ci)) begin + address_collision_a_b = 1'b1; + end + end + if (address_collision_a_b == 1'b1 && display_flag) + + if (({wea_reg, web_int}) == 2'b11) + $display("Memory Collision Error on RAMB4_S8_S16:%m at simulation time %.3f ns\nA write was requested to the same address simultaneously at both Port A and Port B of the RAM. The contents written to the RAM at address location %h (hex) of Port A and address location %h (hex) of Port B are unknown.", $time/1000.0, addra_int, addrb_int); + + else if (({wea_reg, web_int}) == 2'b01) + $display("Memory Collision Error on RAMB4_S8_S16:%m at simulation time %.3f ns\nA read was performed on address %h (hex) of Port A while a write was requested to the same address on Port B. The write will be successful however the read value on Port A is unknown until the next CLKA cycle.", $time/1000.0, addra_int); + + else if (({wea_reg, web_int}) == 2'b10) + $display("Memory Collision Error on RAMB4_S8_S16:%m at simulation time %.3f ns\nA read was performed on address %h (hex) of Port B while a write was requested to the same address on Port A. The write will be successful however the read value on Port B is unknown until the next CLKB cycle.", $time/1000.0, addrb_int); + + end + endtask + + always @(posedge setup_all_b_a) begin + if ((ena_int == 1) && (enb_reg == 1)) begin + case ({wea_int, web_reg}) + 6'b11 : begin data_collision_b_a <= 2'b11; display_all_b_a; end + 6'b01 : begin data_collision_b_a <= 2'b10; display_all_b_a; end + 6'b10 : begin data_collision_b_a <= 2'b01; display_all_b_a; end + endcase + end + setup_all_b_a <= 0; + end + + task display_all_b_a; + begin + address_collision_b_a = 1'b0; + for (ci = 0; ci < 16; ci = ci + 8) begin + if ((mem_addra_int) == (mem_addrb_reg + ci)) begin + address_collision_b_a = 1'b1; + end + end + if (address_collision_b_a == 1'b1 && display_flag) + + if (({wea_int, web_reg}) == 2'b11) + $display("Memory Collision Error on RAMB4_S8_S16:%m at simulation time %.3f ns\nA write was requested to the same address simultaneously at both Port A and Port B of the RAM. The contents written to the RAM at address location %h (hex) of Port A and address location %h (hex) of Port B are unknown.", $time/1000.0, addra_int, addrb_int); + + else if (({wea_int, web_reg}) == 2'b01) + $display("Memory Collision Error on RAMB4_S8_S16:%m at simulation time %.3f ns\nA read was performed on address %h (hex) of Port A while a write was requested to the same address on Port B. The write will be successful however the read value on Port A is unknown until the next CLKA cycle.", $time/1000.0, addra_int); + + else if (({wea_int, web_reg}) == 2'b10) + $display("Memory Collision Error on RAMB4_S8_S16:%m at simulation time %.3f ns\nA read was performed on address %h (hex) of Port B while a write was requested to the same address on Port A. The write will be successful however the read value on Port B is unknown until the next CLKB cycle.", $time/1000.0, addrb_int); + + end + endtask + + always @(posedge setup_zero) begin + if ((ena_int == 1) && (enb_int == 1)) begin + case ({wea_int, web_int}) + 6'b11 : begin data_collision <= 2'b11; display_zero; end + 6'b01 : begin data_collision <= 2'b10; display_zero; end + 6'b10 : begin data_collision <= 2'b01; display_zero; end + endcase + end + setup_zero <= 0; + end + + task display_zero; + begin + address_collision = 1'b0; + for (ci = 0; ci < 16; ci = ci + 8) begin + if ((mem_addra_int) == (mem_addrb_int + ci)) begin + address_collision = 1'b1; + end + end + if (address_collision == 1'b1 && display_flag) + + if (({wea_int, web_int}) == 2'b11) + $display("Memory Collision Error on RAMB4_S8_S16:%m at simulation time %.3f ns\nA write was requested to the same address simultaneously at both Port A and Port B of the RAM. The contents written to the RAM at address location %h (hex) of Port A and address location %h (hex) of Port B are unknown.", $time/1000.0, addra_int, addrb_int); + + else if (({wea_int, web_int}) == 2'b01) + $display("Memory Collision Error on RAMB4_S8_S16:%m at simulation time %.3f ns\nA read was performed on address %h (hex) of Port A while a write was requested to the same address on Port B. The write will be successful however the read value on Port A is unknown until the next CLKA cycle.", $time/1000.0, addra_int); + + else if (({wea_int, web_int}) == 2'b10) + $display("Memory Collision Error on RAMB4_S8_S16:%m at simulation time %.3f ns\nA read was performed on address %h (hex) of Port B while a write was requested to the same address on Port A. The write will be successful however the read value on Port B is unknown until the next CLKB cycle.", $time/1000.0, addrb_int); + + end + endtask + + always @(posedge clka_int) begin + if ((output_flag || display_flag)) begin + addra_reg <= addra_int; + ena_reg <= ena_int; + rsta_reg <= rsta_int; + wea_reg <= wea_int; + end + end + + always @(posedge clkb_int) begin + if ((output_flag || display_flag)) begin + addrb_reg <= addrb_int; + enb_reg <= enb_int; + rstb_reg <= rstb_int; + web_reg <= web_int; + end + end + + + // Data + always @(posedge memory_collision) begin + if ((output_flag || display_flag)) begin + for (mi = 0; mi < 16; mi = mi + 8) begin + if ((mem_addra_int) == (mem_addrb_int + mi)) begin + mem[addra_int[8:1]][addra_int[0:0] * 8 +: 8] <= 8'bx; + end + end + memory_collision <= 0; + end + end + + always @(posedge memory_collision_a_b) begin + if ((output_flag || display_flag)) begin + for (mi = 0; mi < 16; mi = mi + 8) begin + if ((mem_addra_reg) == (mem_addrb_int + mi)) begin + mem[addra_reg[8:1]][addra_reg[0:0] * 8 +: 8] <= 8'bx; + end + end + memory_collision_a_b <= 0; + end + end + + always @(posedge memory_collision_b_a) begin + if ((output_flag || display_flag)) begin + for (mi = 0; mi < 16; mi = mi + 8) begin + if ((mem_addra_int) == (mem_addrb_reg + mi)) begin + mem[addra_int[8:1]][addra_int[0:0] * 8 +: 8] <= 8'bx; + end + end + memory_collision_b_a <= 0; + end + end + + always @(posedge data_collision[1]) begin + if (rsta_int == 0 && output_flag) begin + for (ai = 0; ai < 16; ai = ai + 8) begin + if ((mem_addra_int) == (mem_addrb_int + ai)) begin + doa_out <= #100 8'bX; + end + end + end + data_collision[1] <= 0; + end + + always @(posedge data_collision[0]) begin + if (rstb_int == 0 && output_flag) begin + for (bi = 0; bi < 16; bi = bi + 8) begin + if ((mem_addra_int) == (mem_addrb_int + bi)) begin + for (bj = 0; bj < 8; bj = bj + 1) begin + dob_out[bi + bj] <= #100 1'bX; + end + end + end + end + data_collision[0] <= 0; + end + + always @(posedge data_collision_a_b[1]) begin + if (rsta_reg == 0 && output_flag) begin + for (ai = 0; ai < 16; ai = ai + 8) begin + if ((mem_addra_reg) == (mem_addrb_int + ai)) begin + doa_out <= #100 8'bX; + end + end + end + data_collision_a_b[1] <= 0; + end + + always @(posedge data_collision_a_b[0]) begin + if (rstb_int == 0 && output_flag) begin + for (bi = 0; bi < 16; bi = bi + 8) begin + if ((mem_addra_reg) == (mem_addrb_int + bi)) begin + for (bj = 0; bj < 8; bj = bj + 1) begin + dob_out[bi + bj] <= #100 1'bX; + end + end + end + end + data_collision_a_b[0] <= 0; + end + + always @(posedge data_collision_b_a[1]) begin + if (rsta_int == 0 && output_flag) begin + for (ai = 0; ai < 16; ai = ai + 8) begin + if ((mem_addra_int) == (mem_addrb_reg + ai)) begin + doa_out <= #100 8'bX; + end + end + end + data_collision_b_a[1] <= 0; + end + + always @(posedge data_collision_b_a[0]) begin + if (rstb_reg == 0 && output_flag) begin + for (bi = 0; bi < 16; bi = bi + 8) begin + if ((mem_addra_int) == (mem_addrb_reg + bi)) begin + for (bj = 0; bj < 8; bj = bj + 1) begin + dob_out[bi + bj] <= #100 1'bX; + end + end + end + end + data_collision_b_a[0] <= 0; + end + + + // Port A + always @(posedge clka_int) begin + + if (ena_int == 1'b1) begin + + if (rsta_int == 1'b1) begin + doa_out <= #100 0; + end + else begin + if (wea_int == 1'b1) + doa_out <= #100 dia_int; + else + doa_out <= #100 mem[addra_int[8:1]][addra_int[0:0] * 8 +: 8]; + end + + // memory + if (wea_int == 1'b1) begin + mem[addra_int[8:1]][addra_int[0:0] * 8 +: 8] <= dia_int; + end + + end + end + + + // Port B + always @(posedge clkb_int) begin + + if (enb_int == 1'b1) begin + + if (rstb_int == 1'b1) begin + dob_out <= #100 0; + end + else begin + if (web_int == 1'b1) + dob_out <= #100 dib_int; + else + dob_out <= #100 mem[addrb_int]; + end + + // memory + if (web_int == 1'b1) begin + mem[addrb_int] <= dib_int; + end + + end + end + + +endmodule + +`endif diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/RAMB4_S8_S8.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/RAMB4_S8_S8.v new file mode 100644 index 0000000..ce682ea --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/RAMB4_S8_S8.v @@ -0,0 +1,1103 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/RAMB4_S8_S8.v,v 1.9 2007/02/22 01:58:06 wloo Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2005 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / 4K-Bit Data Dual Port Block RAM +// /___/ /\ Filename : RAMB4_S8_S8.v +// \ \ / \ Timestamp : Thu Mar 10 16:43:39 PST 2005 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// End Revision + +`ifdef legacy_model + +`timescale 1 ps / 1 ps + +module RAMB4_S8_S8 (DOA, DOB, ADDRA, ADDRB, CLKA, CLKB, DIA, DIB, ENA, ENB, RSTA, RSTB, WEA, WEB); + + parameter SIM_COLLISION_CHECK = "ALL"; + localparam SETUP_ALL = 100; + + parameter INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + + output [7:0] DOA; + reg [7:0] doa_out; + wire doa_out0, doa_out1, doa_out2, doa_out3, doa_out4, doa_out5, doa_out6, doa_out7; + + input [8:0] ADDRA; + input [7:0] DIA; + input ENA, CLKA, WEA, RSTA; + + output [7:0] DOB; + reg [7:0] dob_out; + wire dob_out0, dob_out1, dob_out2, dob_out3, dob_out4, dob_out5, dob_out6, dob_out7; + + input [8:0] ADDRB; + input [7:0] DIB; + input ENB, CLKB, WEB, RSTB; + + reg [4095:0] mem; + reg [8:0] count; + + reg [5:0] mi, mj, ai, aj, bi, bj, ci, cj, di, dj, ei, ej, fi, fj; + + wire [8:0] addra_int; + reg [8:0] addra_reg; + wire [7:0] dia_int; + wire ena_int, clka_int, wea_int, rsta_int; + reg ena_reg, wea_reg, rsta_reg; + wire [8:0] addrb_int; + reg [8:0] addrb_reg; + wire [7:0] dib_int; + wire enb_int, clkb_int, web_int, rstb_int; + reg enb_reg, web_reg, rstb_reg; + + time time_clka, time_clkb; + time time_clka_clkb; + time time_clkb_clka; + + reg setup_all_a_b; + reg setup_all_b_a; + reg setup_zero; + reg [1:0] data_collision, data_collision_a_b, data_collision_b_a; + reg memory_collision, memory_collision_a_b, memory_collision_b_a; + reg address_collision, address_collision_a_b, address_collision_b_a; + reg change_clka; + reg change_clkb; + + wire [11:0] mem_addra_int; + wire [11:0] mem_addra_reg; + wire [11:0] mem_addrb_int; + wire [11:0] mem_addrb_reg; + + tri0 GSR = glbl.GSR; + + always @(GSR) + if (GSR) begin + assign doa_out = 0; + end + else begin + deassign doa_out; + end + + always @(GSR) + if (GSR) begin + assign dob_out = 0; + end + else begin + deassign dob_out; + end + + buf b_doa_out0 (doa_out0, doa_out[0]); + buf b_doa_out1 (doa_out1, doa_out[1]); + buf b_doa_out2 (doa_out2, doa_out[2]); + buf b_doa_out3 (doa_out3, doa_out[3]); + buf b_doa_out4 (doa_out4, doa_out[4]); + buf b_doa_out5 (doa_out5, doa_out[5]); + buf b_doa_out6 (doa_out6, doa_out[6]); + buf b_doa_out7 (doa_out7, doa_out[7]); + buf b_dob_out0 (dob_out0, dob_out[0]); + buf b_dob_out1 (dob_out1, dob_out[1]); + buf b_dob_out2 (dob_out2, dob_out[2]); + buf b_dob_out3 (dob_out3, dob_out[3]); + buf b_dob_out4 (dob_out4, dob_out[4]); + buf b_dob_out5 (dob_out5, dob_out[5]); + buf b_dob_out6 (dob_out6, dob_out[6]); + buf b_dob_out7 (dob_out7, dob_out[7]); + buf b_doa0 (DOA[0], doa_out0); + buf b_doa1 (DOA[1], doa_out1); + buf b_doa2 (DOA[2], doa_out2); + buf b_doa3 (DOA[3], doa_out3); + buf b_doa4 (DOA[4], doa_out4); + buf b_doa5 (DOA[5], doa_out5); + buf b_doa6 (DOA[6], doa_out6); + buf b_doa7 (DOA[7], doa_out7); + buf b_dob0 (DOB[0], dob_out0); + buf b_dob1 (DOB[1], dob_out1); + buf b_dob2 (DOB[2], dob_out2); + buf b_dob3 (DOB[3], dob_out3); + buf b_dob4 (DOB[4], dob_out4); + buf b_dob5 (DOB[5], dob_out5); + buf b_dob6 (DOB[6], dob_out6); + buf b_dob7 (DOB[7], dob_out7); + buf b_addra_0 (addra_int[0], ADDRA[0]); + buf b_addra_1 (addra_int[1], ADDRA[1]); + buf b_addra_2 (addra_int[2], ADDRA[2]); + buf b_addra_3 (addra_int[3], ADDRA[3]); + buf b_addra_4 (addra_int[4], ADDRA[4]); + buf b_addra_5 (addra_int[5], ADDRA[5]); + buf b_addra_6 (addra_int[6], ADDRA[6]); + buf b_addra_7 (addra_int[7], ADDRA[7]); + buf b_addra_8 (addra_int[8], ADDRA[8]); + buf b_dia_0 (dia_int[0], DIA[0]); + buf b_dia_1 (dia_int[1], DIA[1]); + buf b_dia_2 (dia_int[2], DIA[2]); + buf b_dia_3 (dia_int[3], DIA[3]); + buf b_dia_4 (dia_int[4], DIA[4]); + buf b_dia_5 (dia_int[5], DIA[5]); + buf b_dia_6 (dia_int[6], DIA[6]); + buf b_dia_7 (dia_int[7], DIA[7]); + buf b_clka (clka_int, CLKA); + buf b_ena (ena_int, ENA); + buf b_rsta (rsta_int, RSTA); + buf b_wea (wea_int, WEA); + buf b_addrb_0 (addrb_int[0], ADDRB[0]); + buf b_addrb_1 (addrb_int[1], ADDRB[1]); + buf b_addrb_2 (addrb_int[2], ADDRB[2]); + buf b_addrb_3 (addrb_int[3], ADDRB[3]); + buf b_addrb_4 (addrb_int[4], ADDRB[4]); + buf b_addrb_5 (addrb_int[5], ADDRB[5]); + buf b_addrb_6 (addrb_int[6], ADDRB[6]); + buf b_addrb_7 (addrb_int[7], ADDRB[7]); + buf b_addrb_8 (addrb_int[8], ADDRB[8]); + buf b_dib_0 (dib_int[0], DIB[0]); + buf b_dib_1 (dib_int[1], DIB[1]); + buf b_dib_2 (dib_int[2], DIB[2]); + buf b_dib_3 (dib_int[3], DIB[3]); + buf b_dib_4 (dib_int[4], DIB[4]); + buf b_dib_5 (dib_int[5], DIB[5]); + buf b_dib_6 (dib_int[6], DIB[6]); + buf b_dib_7 (dib_int[7], DIB[7]); + buf b_clkb (clkb_int, CLKB); + buf b_enb (enb_int, ENB); + buf b_rstb (rstb_int, RSTB); + buf b_web (web_int, WEB); + + initial begin + for (count = 0; count < 256; count = count + 1) begin + mem[count] <= INIT_00[count]; + mem[256 * 1 + count] <= INIT_01[count]; + mem[256 * 2 + count] <= INIT_02[count]; + mem[256 * 3 + count] <= INIT_03[count]; + mem[256 * 4 + count] <= INIT_04[count]; + mem[256 * 5 + count] <= INIT_05[count]; + mem[256 * 6 + count] <= INIT_06[count]; + mem[256 * 7 + count] <= INIT_07[count]; + mem[256 * 8 + count] <= INIT_08[count]; + mem[256 * 9 + count] <= INIT_09[count]; + mem[256 * 10 + count] <= INIT_0A[count]; + mem[256 * 11 + count] <= INIT_0B[count]; + mem[256 * 12 + count] <= INIT_0C[count]; + mem[256 * 13 + count] <= INIT_0D[count]; + mem[256 * 14 + count] <= INIT_0E[count]; + mem[256 * 15 + count] <= INIT_0F[count]; + end + address_collision <= 0; + address_collision_a_b <= 0; + address_collision_b_a <= 0; + change_clka <= 0; + change_clkb <= 0; + data_collision <= 0; + data_collision_a_b <= 0; + data_collision_b_a <= 0; + memory_collision <= 0; + memory_collision_a_b <= 0; + memory_collision_b_a <= 0; + setup_all_a_b <= 0; + setup_all_b_a <= 0; + setup_zero <= 0; + end + + assign mem_addra_int = addra_int * 8; + assign mem_addra_reg = addra_reg * 8; + assign mem_addrb_int = addrb_int * 8; + assign mem_addrb_reg = addrb_reg * 8; + + + initial begin + + case (SIM_COLLISION_CHECK) + + "NONE" : begin + assign setup_all_a_b = 1'b0; + assign setup_all_b_a = 1'b0; + assign setup_zero = 1'b0; + assign address_collision = 1'b0; + assign address_collision_a_b = 1'b0; + assign address_collision_b_a = 1'b0; + end + "WARNING_ONLY" : begin + assign data_collision = 2'b00; + assign data_collision_a_b = 2'b00; + assign data_collision_b_a = 2'b00; + assign memory_collision = 1'b0; + assign memory_collision_a_b = 1'b0; + assign memory_collision_b_a = 1'b0; + end + "GENERATE_X_ONLY" : begin + assign address_collision = 1'b0; + assign address_collision_a_b = 1'b0; + assign address_collision_b_a = 1'b0; + end + "ALL" : ; + default : begin + $display("Attribute Syntax Error : The Attribute SIM_COLLISION_CHECK on RAMB4_S8_S8 instance %m is set to %s. Legal values for this attribute are ALL, NONE, WARNING_ONLY or GENERATE_X_ONLY.", SIM_COLLISION_CHECK); + $finish; + end + + endcase // case(SIM_COLLISION_CHECK) + + end // initial begin + + + always @(posedge clka_int) begin + time_clka = $time; + #0 time_clkb_clka = time_clka - time_clkb; + change_clka = ~change_clka; + end + + always @(posedge clkb_int) begin + time_clkb = $time; + #0 time_clka_clkb = time_clkb - time_clka; + change_clkb = ~change_clkb; + end + + always @(change_clkb) begin + if ((0 < time_clka_clkb) && (time_clka_clkb < SETUP_ALL)) + setup_all_a_b = 1; + end + + always @(change_clka) begin + if ((0 < time_clkb_clka) && (time_clkb_clka < SETUP_ALL)) + setup_all_b_a = 1; + end + + always @(change_clkb or change_clka) begin + if ((time_clkb_clka == 0) && (time_clka_clkb == 0)) + setup_zero = 1; + end + + always @(posedge setup_zero) begin + if ((ena_int == 1) && (wea_int == 1) && + (enb_int == 1) && (web_int == 1)) + memory_collision <= 1; + end + + always @(posedge setup_all_a_b) begin + if ((ena_reg == 1) && (enb_int == 1)) begin + case ({wea_reg, web_int}) + 6'b11 : begin data_collision_a_b <= 2'b11; display_all_a_b; end + 6'b01 : begin data_collision_a_b <= 2'b10; display_all_a_b; end + 6'b10 : begin data_collision_a_b <= 2'b01; display_all_a_b; end + endcase + end + setup_all_a_b <= 0; + end + + task display_all_a_b; + begin + address_collision_a_b = 1'b0; + for (ci = 0; ci < 8; ci = ci + 8) begin + if ((mem_addra_reg) == (mem_addrb_int + ci)) begin + address_collision_a_b = 1'b1; + end + end + if (address_collision_a_b == 1'b1) + + if (({wea_reg, web_int}) == 2'b11) + $display("Memory Collision Error on RAMB4_S8_S8:%m at simulation time %.3f ns\nA write was requested to the same address simultaneously at both Port A and Port B of the RAM. The contents written to the RAM at address location %h (hex) of Port A and address location %h (hex) of Port B are unknown.", $time/1000.0, addra_int, addrb_int); + + else if (({wea_reg, web_int}) == 2'b01) + $display("Memory Collision Error on RAMB4_S8_S8:%m at simulation time %.3f ns\nA read was performed on address %h (hex) of Port A while a write was requested to the same address on Port B. The write will be successful however the read value on Port A is unknown until the next CLKA cycle.", $time/1000.0, addra_int); + + else if (({wea_reg, web_int}) == 2'b10) + $display("Memory Collision Error on RAMB4_S8_S8:%m at simulation time %.3f ns\nA read was performed on address %h (hex) of Port B while a write was requested to the same address on Port A. The write will be successful however the read value on Port B is unknown until the next CLKB cycle.", $time/1000.0, addrb_int); + + end + endtask + + always @(posedge setup_all_b_a) begin + if ((ena_int == 1) && (enb_reg == 1)) begin + case ({wea_int, web_reg}) + 6'b11 : begin data_collision_b_a <= 2'b11; display_all_b_a; end + 6'b01 : begin data_collision_b_a <= 2'b10; display_all_b_a; end + 6'b10 : begin data_collision_b_a <= 2'b01; display_all_b_a; end + endcase + end + setup_all_b_a <= 0; + end + + task display_all_b_a; + begin + address_collision_b_a = 1'b0; + for (ci = 0; ci < 8; ci = ci + 8) begin + if ((mem_addra_int) == (mem_addrb_reg + ci)) begin + address_collision_b_a = 1'b1; + end + end + if (address_collision_b_a == 1'b1) + + if (({wea_int, web_reg}) == 2'b11) + $display("Memory Collision Error on RAMB4_S8_S8:%m at simulation time %.3f ns\nA write was requested to the same address simultaneously at both Port A and Port B of the RAM. The contents written to the RAM at address location %h (hex) of Port A and address location %h (hex) of Port B are unknown.", $time/1000.0, addra_int, addrb_int); + + else if (({wea_int, web_reg}) == 2'b01) + $display("Memory Collision Error on RAMB4_S8_S8:%m at simulation time %.3f ns\nA read was performed on address %h (hex) of Port A while a write was requested to the same address on Port B. The write will be successful however the read value on Port A is unknown until the next CLKA cycle.", $time/1000.0, addra_int); + + else if (({wea_int, web_reg}) == 2'b10) + $display("Memory Collision Error on RAMB4_S8_S8:%m at simulation time %.3f ns\nA read was performed on address %h (hex) of Port B while a write was requested to the same address on Port A. The write will be successful however the read value on Port B is unknown until the next CLKB cycle.", $time/1000.0, addrb_int); + + end + endtask + + always @(posedge setup_zero) begin + if ((ena_int == 1) && (enb_int == 1)) begin + case ({wea_int, web_int}) + 6'b11 : begin data_collision <= 2'b11; display_zero; end + 6'b01 : begin data_collision <= 2'b10; display_zero; end + 6'b10 : begin data_collision <= 2'b01; display_zero; end + endcase + end + setup_zero <= 0; + end + + task display_zero; + begin + address_collision = 1'b0; + for (ci = 0; ci < 8; ci = ci + 8) begin + if ((mem_addra_int) == (mem_addrb_int + ci)) begin + address_collision = 1'b1; + end + end + if (address_collision == 1'b1) + + if (({wea_int, web_int}) == 2'b11) + $display("Memory Collision Error on RAMB4_S8_S8:%m at simulation time %.3f ns\nA write was requested to the same address simultaneously at both Port A and Port B of the RAM. The contents written to the RAM at address location %h (hex) of Port A and address location %h (hex) of Port B are unknown.", $time/1000.0, addra_int, addrb_int); + + else if (({wea_int, web_int}) == 2'b01) + $display("Memory Collision Error on RAMB4_S8_S8:%m at simulation time %.3f ns\nA read was performed on address %h (hex) of Port A while a write was requested to the same address on Port B. The write will be successful however the read value on Port A is unknown until the next CLKA cycle.", $time/1000.0, addra_int); + + else if (({wea_int, web_int}) == 2'b10) + $display("Memory Collision Error on RAMB4_S8_S8:%m at simulation time %.3f ns\nA read was performed on address %h (hex) of Port B while a write was requested to the same address on Port A. The write will be successful however the read value on Port B is unknown until the next CLKB cycle.", $time/1000.0, addrb_int); + + end + endtask + + always @(posedge clka_int) begin + addra_reg <= addra_int; + ena_reg <= ena_int; + rsta_reg <= rsta_int; + wea_reg <= wea_int; + end + + always @(posedge clkb_int) begin + addrb_reg <= addrb_int; + enb_reg <= enb_int; + rstb_reg <= rstb_int; + web_reg <= web_int; + end + + // Data + always @(posedge memory_collision) begin + for (mi = 0; mi < 8; mi = mi + 8) begin + if ((mem_addra_int) == (mem_addrb_int + mi)) begin + for (mj = 0; mj < 8; mj = mj + 1) begin + mem[mem_addrb_int + mi + mj] <= 1'bX; + end + end + end + memory_collision <= 0; + end + + always @(posedge memory_collision_a_b) begin + for (mi = 0; mi < 8; mi = mi + 8) begin + if ((mem_addra_reg) == (mem_addrb_int + mi)) begin + for (mj = 0; mj < 8; mj = mj + 1) begin + mem[mem_addrb_int + mi + mj] <= 1'bX; + end + end + end + memory_collision_a_b <= 0; + end + + always @(posedge memory_collision_b_a) begin + for (mi = 0; mi < 8; mi = mi + 8) begin + if ((mem_addra_int) == (mem_addrb_reg + mi)) begin + for (mj = 0; mj < 8; mj = mj + 1) begin + mem[mem_addrb_reg + mi + mj] <= 1'bX; + end + end + end + memory_collision_b_a <= 0; + end + + always @(posedge data_collision[1]) begin + if (rsta_int == 0) begin + for (ai = 0; ai < 8; ai = ai + 8) begin + if ((mem_addra_int) == (mem_addrb_int + ai)) begin + doa_out <= 8'bX; + end + end + end + data_collision[1] <= 0; + end + + always @(posedge data_collision[0]) begin + if (rstb_int == 0) begin + for (bi = 0; bi < 8; bi = bi + 8) begin + if ((mem_addra_int) == (mem_addrb_int + bi)) begin + for (bj = 0; bj < 8; bj = bj + 1) begin + dob_out[bi + bj] <= 1'bX; + end + end + end + end + data_collision[0] <= 0; + end + + always @(posedge data_collision_a_b[1]) begin + if (rsta_reg == 0) begin + for (ai = 0; ai < 8; ai = ai + 8) begin + if ((mem_addra_reg) == (mem_addrb_int + ai)) begin + doa_out <= 8'bX; + end + end + end + data_collision_a_b[1] <= 0; + end + + always @(posedge data_collision_a_b[0]) begin + if (rstb_int == 0) begin + for (bi = 0; bi < 8; bi = bi + 8) begin + if ((mem_addra_reg) == (mem_addrb_int + bi)) begin + for (bj = 0; bj < 8; bj = bj + 1) begin + dob_out[bi + bj] <= 1'bX; + end + end + end + end + data_collision_a_b[0] <= 0; + end + + always @(posedge data_collision_b_a[1]) begin + if (rsta_int == 0) begin + for (ai = 0; ai < 8; ai = ai + 8) begin + if ((mem_addra_int) == (mem_addrb_reg + ai)) begin + doa_out <= 8'bX; + end + end + end + data_collision_b_a[1] <= 0; + end + + always @(posedge data_collision_b_a[0]) begin + if (rstb_reg == 0) begin + for (bi = 0; bi < 8; bi = bi + 8) begin + if ((mem_addra_int) == (mem_addrb_reg + bi)) begin + for (bj = 0; bj < 8; bj = bj + 1) begin + dob_out[bi + bj] <= 1'bX; + end + end + end + end + data_collision_b_a[0] <= 0; + end + + + always @(posedge clka_int) begin + if (ena_int == 1'b1) begin + if (rsta_int == 1'b1) begin + doa_out <= 8'b0; + end + else if (wea_int == 0) begin + doa_out[0] <= mem[mem_addra_int + 0]; + doa_out[1] <= mem[mem_addra_int + 1]; + doa_out[2] <= mem[mem_addra_int + 2]; + doa_out[3] <= mem[mem_addra_int + 3]; + doa_out[4] <= mem[mem_addra_int + 4]; + doa_out[5] <= mem[mem_addra_int + 5]; + doa_out[6] <= mem[mem_addra_int + 6]; + doa_out[7] <= mem[mem_addra_int + 7]; + end + else begin + doa_out <= dia_int; + end + end + end + + always @(posedge clka_int) begin + if (ena_int == 1'b1 && wea_int == 1'b1) begin + mem[mem_addra_int + 0] <= dia_int[0]; + mem[mem_addra_int + 1] <= dia_int[1]; + mem[mem_addra_int + 2] <= dia_int[2]; + mem[mem_addra_int + 3] <= dia_int[3]; + mem[mem_addra_int + 4] <= dia_int[4]; + mem[mem_addra_int + 5] <= dia_int[5]; + mem[mem_addra_int + 6] <= dia_int[6]; + mem[mem_addra_int + 7] <= dia_int[7]; + end + end + + always @(posedge clkb_int) begin + if (enb_int == 1'b1) begin + if (rstb_int == 1'b1) begin + dob_out <= 8'b0; + end + else if (web_int == 0) begin + dob_out[0] <= mem[mem_addrb_int + 0]; + dob_out[1] <= mem[mem_addrb_int + 1]; + dob_out[2] <= mem[mem_addrb_int + 2]; + dob_out[3] <= mem[mem_addrb_int + 3]; + dob_out[4] <= mem[mem_addrb_int + 4]; + dob_out[5] <= mem[mem_addrb_int + 5]; + dob_out[6] <= mem[mem_addrb_int + 6]; + dob_out[7] <= mem[mem_addrb_int + 7]; + end + else begin + dob_out <= dib_int; + end + end + end + + always @(posedge clkb_int) begin + if (enb_int == 1'b1 && web_int == 1'b1) begin + mem[mem_addrb_int + 0] <= dib_int[0]; + mem[mem_addrb_int + 1] <= dib_int[1]; + mem[mem_addrb_int + 2] <= dib_int[2]; + mem[mem_addrb_int + 3] <= dib_int[3]; + mem[mem_addrb_int + 4] <= dib_int[4]; + mem[mem_addrb_int + 5] <= dib_int[5]; + mem[mem_addrb_int + 6] <= dib_int[6]; + mem[mem_addrb_int + 7] <= dib_int[7]; + end + end + + specify + (CLKA *> DOA) = (100, 100); + (CLKB *> DOB) = (100, 100); + endspecify + +endmodule + +`else + +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/RAMB4_S8_S8.v,v 1.9 2007/02/22 01:58:06 wloo Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2005 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Timing Simulation Library Component +// / / 16K-Bit Data and 2K-Bit Parity Dual Port Block RAM +// /___/ /\ Filename : RAMB4_S8_S8.v +// \ \ / \ Timestamp : Thu Mar 10 16:44:01 PST 2005 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 03/10/05 - Initialized outputs. +// 02/21/07 - Fixed parameter SIM_COLLISION_CHECK (CR 433281). +// End Revision + +`timescale 1 ps/1 ps + +module RAMB4_S8_S8 (DOA, DOB, ADDRA, ADDRB, CLKA, CLKB, DIA, DIB, ENA, ENB, RSTA, RSTB, WEA, WEB); + + parameter SIM_COLLISION_CHECK = "ALL"; + localparam SETUP_ALL = 100; + + parameter INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + + output [7:0] DOA; + output [7:0] DOB; + + input [8:0] ADDRA; + input [7:0] DIA; + input ENA, CLKA, WEA, RSTA; + input [8:0] ADDRB; + input [7:0] DIB; + input ENB, CLKB, WEB, RSTB; + + reg [7:0] doa_out = 0; + reg [7:0] dob_out = 0; + + reg [7:0] mem [511:0]; + + reg [8:0] count; + + reg [5:0] mi, ai, bi, bj, ci; + + wire [8:0] addra_int; + reg [8:0] addra_reg; + wire [7:0] dia_int; + wire ena_int, clka_int, wea_int, rsta_int; + reg ena_reg, wea_reg, rsta_reg; + wire [8:0] addrb_int; + reg [8:0] addrb_reg; + wire [7:0] dib_int; + wire enb_int, clkb_int, web_int, rstb_int; + reg display_flag, output_flag; + reg enb_reg, web_reg, rstb_reg; + + time time_clka, time_clkb; + time time_clka_clkb; + time time_clkb_clka; + + reg setup_all_a_b; + reg setup_all_b_a; + reg setup_zero; + reg [1:0] data_collision, data_collision_a_b, data_collision_b_a; + reg memory_collision, memory_collision_a_b, memory_collision_b_a; + reg address_collision, address_collision_a_b, address_collision_b_a; + reg change_clka; + reg change_clkb; + + wire [11:0] mem_addra_int; + wire [11:0] mem_addra_reg; + wire [11:0] mem_addrb_int; + wire [11:0] mem_addrb_reg; + + wire dia_enable = ena_int && wea_int; + wire dib_enable = enb_int && web_int; + + tri0 GSR = glbl.GSR; + wire gsr_int; + + buf b_gsr (gsr_int, GSR); + + buf b_doa [7:0] (DOA, doa_out); + buf b_addra [8:0] (addra_int, ADDRA); + buf b_dia [7:0] (dia_int, DIA); + buf b_ena (ena_int, ENA); + buf b_clka (clka_int, CLKA); + buf b_rsta (rsta_int, RSTA); + buf b_wea (wea_int, WEA); + + buf b_dob [7:0] (DOB, dob_out); + buf b_addrb [8:0] (addrb_int, ADDRB); + buf b_dib [7:0] (dib_int, DIB); + buf b_enb (enb_int, ENB); + buf b_clkb (clkb_int, CLKB); + buf b_rstb (rstb_int, RSTB); + buf b_web (web_int, WEB); + + + always @(gsr_int) + if (gsr_int) begin + assign doa_out = 0; + assign dob_out = 0; + end + else begin + deassign doa_out; + deassign dob_out; + end + + + initial begin + + for (count = 0; count < 32; count = count + 1) begin + mem[count] = INIT_00[(count * 8) +: 8]; + mem[32 * 1 + count] = INIT_01[(count * 8) +: 8]; + mem[32 * 2 + count] = INIT_02[(count * 8) +: 8]; + mem[32 * 3 + count] = INIT_03[(count * 8) +: 8]; + mem[32 * 4 + count] = INIT_04[(count * 8) +: 8]; + mem[32 * 5 + count] = INIT_05[(count * 8) +: 8]; + mem[32 * 6 + count] = INIT_06[(count * 8) +: 8]; + mem[32 * 7 + count] = INIT_07[(count * 8) +: 8]; + mem[32 * 8 + count] = INIT_08[(count * 8) +: 8]; + mem[32 * 9 + count] = INIT_09[(count * 8) +: 8]; + mem[32 * 10 + count] = INIT_0A[(count * 8) +: 8]; + mem[32 * 11 + count] = INIT_0B[(count * 8) +: 8]; + mem[32 * 12 + count] = INIT_0C[(count * 8) +: 8]; + mem[32 * 13 + count] = INIT_0D[(count * 8) +: 8]; + mem[32 * 14 + count] = INIT_0E[(count * 8) +: 8]; + mem[32 * 15 + count] = INIT_0F[(count * 8) +: 8]; + end + + change_clka <= 0; + change_clkb <= 0; + data_collision <= 0; + data_collision_a_b <= 0; + data_collision_b_a <= 0; + memory_collision <= 0; + memory_collision_a_b <= 0; + memory_collision_b_a <= 0; + setup_all_a_b <= 0; + setup_all_b_a <= 0; + setup_zero <= 0; + end + + assign mem_addra_int = addra_int * 8; + assign mem_addra_reg = addra_reg * 8; + assign mem_addrb_int = addrb_int * 8; + assign mem_addrb_reg = addrb_reg * 8; + + + initial begin + + display_flag = 1; + output_flag = 1; + + case (SIM_COLLISION_CHECK) + + "NONE" : begin + output_flag = 0; + display_flag = 0; + end + "WARNING_ONLY" : output_flag = 0; + "GENERATE_X_ONLY" : display_flag = 0; + "ALL" : ; + + default : begin + $display("Attribute Syntax Error : The Attribute SIM_COLLISION_CHECK on RAMB4_S8_S8 instance %m is set to %s. Legal values for this attribute are ALL, NONE, WARNING_ONLY or GENERATE_X_ONLY.", SIM_COLLISION_CHECK); + $finish; + end + + endcase // case(SIM_COLLISION_CHECK) + + end // initial begin + + + always @(posedge clka_int) begin + if ((output_flag || display_flag)) begin + time_clka = $time; + #0 time_clkb_clka = time_clka - time_clkb; + change_clka = ~change_clka; + end + end + + always @(posedge clkb_int) begin + if ((output_flag || display_flag)) begin + time_clkb = $time; + #0 time_clka_clkb = time_clkb - time_clka; + change_clkb = ~change_clkb; + end + end + + always @(change_clkb) begin + if ((0 < time_clka_clkb) && (time_clka_clkb < SETUP_ALL)) + setup_all_a_b = 1; + end + + always @(change_clka) begin + if ((0 < time_clkb_clka) && (time_clkb_clka < SETUP_ALL)) + setup_all_b_a = 1; + end + + always @(change_clkb or change_clka) begin + if ((time_clkb_clka == 0) && (time_clka_clkb == 0)) + setup_zero = 1; + end + + always @(posedge setup_zero) begin + if ((ena_int == 1) && (wea_int == 1) && + (enb_int == 1) && (web_int == 1)) + memory_collision <= 1; + end + + always @(posedge setup_all_a_b) begin + if ((ena_reg == 1) && (enb_int == 1)) begin + case ({wea_reg, web_int}) + 6'b11 : begin data_collision_a_b <= 2'b11; display_all_a_b; end + 6'b01 : begin data_collision_a_b <= 2'b10; display_all_a_b; end + 6'b10 : begin data_collision_a_b <= 2'b01; display_all_a_b; end + endcase + end + setup_all_a_b <= 0; + end + + task display_all_a_b; + begin + address_collision_a_b = 1'b0; + for (ci = 0; ci < 8; ci = ci + 8) begin + if ((mem_addra_reg) == (mem_addrb_int + ci)) begin + address_collision_a_b = 1'b1; + end + end + if (address_collision_a_b == 1'b1 && display_flag) + + if (({wea_reg, web_int}) == 2'b11) + $display("Memory Collision Error on RAMB4_S8_S8:%m at simulation time %.3f ns\nA write was requested to the same address simultaneously at both Port A and Port B of the RAM. The contents written to the RAM at address location %h (hex) of Port A and address location %h (hex) of Port B are unknown.", $time/1000.0, addra_int, addrb_int); + + else if (({wea_reg, web_int}) == 2'b01) + $display("Memory Collision Error on RAMB4_S8_S8:%m at simulation time %.3f ns\nA read was performed on address %h (hex) of Port A while a write was requested to the same address on Port B. The write will be successful however the read value on Port A is unknown until the next CLKA cycle.", $time/1000.0, addra_int); + + else if (({wea_reg, web_int}) == 2'b10) + $display("Memory Collision Error on RAMB4_S8_S8:%m at simulation time %.3f ns\nA read was performed on address %h (hex) of Port B while a write was requested to the same address on Port A. The write will be successful however the read value on Port B is unknown until the next CLKB cycle.", $time/1000.0, addrb_int); + + end + endtask + + always @(posedge setup_all_b_a) begin + if ((ena_int == 1) && (enb_reg == 1)) begin + case ({wea_int, web_reg}) + 6'b11 : begin data_collision_b_a <= 2'b11; display_all_b_a; end + 6'b01 : begin data_collision_b_a <= 2'b10; display_all_b_a; end + 6'b10 : begin data_collision_b_a <= 2'b01; display_all_b_a; end + endcase + end + setup_all_b_a <= 0; + end + + task display_all_b_a; + begin + address_collision_b_a = 1'b0; + for (ci = 0; ci < 8; ci = ci + 8) begin + if ((mem_addra_int) == (mem_addrb_reg + ci)) begin + address_collision_b_a = 1'b1; + end + end + if (address_collision_b_a == 1'b1 && display_flag) + + if (({wea_int, web_reg}) == 2'b11) + $display("Memory Collision Error on RAMB4_S8_S8:%m at simulation time %.3f ns\nA write was requested to the same address simultaneously at both Port A and Port B of the RAM. The contents written to the RAM at address location %h (hex) of Port A and address location %h (hex) of Port B are unknown.", $time/1000.0, addra_int, addrb_int); + + else if (({wea_int, web_reg}) == 2'b01) + $display("Memory Collision Error on RAMB4_S8_S8:%m at simulation time %.3f ns\nA read was performed on address %h (hex) of Port A while a write was requested to the same address on Port B. The write will be successful however the read value on Port A is unknown until the next CLKA cycle.", $time/1000.0, addra_int); + + else if (({wea_int, web_reg}) == 2'b10) + $display("Memory Collision Error on RAMB4_S8_S8:%m at simulation time %.3f ns\nA read was performed on address %h (hex) of Port B while a write was requested to the same address on Port A. The write will be successful however the read value on Port B is unknown until the next CLKB cycle.", $time/1000.0, addrb_int); + + end + endtask + + always @(posedge setup_zero) begin + if ((ena_int == 1) && (enb_int == 1)) begin + case ({wea_int, web_int}) + 6'b11 : begin data_collision <= 2'b11; display_zero; end + 6'b01 : begin data_collision <= 2'b10; display_zero; end + 6'b10 : begin data_collision <= 2'b01; display_zero; end + endcase + end + setup_zero <= 0; + end + + task display_zero; + begin + address_collision = 1'b0; + for (ci = 0; ci < 8; ci = ci + 8) begin + if ((mem_addra_int) == (mem_addrb_int + ci)) begin + address_collision = 1'b1; + end + end + if (address_collision == 1'b1 && display_flag) + + if (({wea_int, web_int}) == 2'b11) + $display("Memory Collision Error on RAMB4_S8_S8:%m at simulation time %.3f ns\nA write was requested to the same address simultaneously at both Port A and Port B of the RAM. The contents written to the RAM at address location %h (hex) of Port A and address location %h (hex) of Port B are unknown.", $time/1000.0, addra_int, addrb_int); + + else if (({wea_int, web_int}) == 2'b01) + $display("Memory Collision Error on RAMB4_S8_S8:%m at simulation time %.3f ns\nA read was performed on address %h (hex) of Port A while a write was requested to the same address on Port B. The write will be successful however the read value on Port A is unknown until the next CLKA cycle.", $time/1000.0, addra_int); + + else if (({wea_int, web_int}) == 2'b10) + $display("Memory Collision Error on RAMB4_S8_S8:%m at simulation time %.3f ns\nA read was performed on address %h (hex) of Port B while a write was requested to the same address on Port A. The write will be successful however the read value on Port B is unknown until the next CLKB cycle.", $time/1000.0, addrb_int); + + end + endtask + + always @(posedge clka_int) begin + if ((output_flag || display_flag)) begin + addra_reg <= addra_int; + ena_reg <= ena_int; + rsta_reg <= rsta_int; + wea_reg <= wea_int; + end + end + + always @(posedge clkb_int) begin + if ((output_flag || display_flag)) begin + addrb_reg <= addrb_int; + enb_reg <= enb_int; + rstb_reg <= rstb_int; + web_reg <= web_int; + end + end + + + // Data + always @(posedge memory_collision) begin + if ((output_flag || display_flag)) begin + for (mi = 0; mi < 8; mi = mi + 8) begin + if ((mem_addra_int) == (mem_addrb_int + mi)) begin + mem[addra_int] <= 8'bx; + end + end + memory_collision <= 0; + end + end + + always @(posedge memory_collision_a_b) begin + if ((output_flag || display_flag)) begin + for (mi = 0; mi < 8; mi = mi + 8) begin + if ((mem_addra_reg) == (mem_addrb_int + mi)) begin + mem[addra_reg] <= 8'bx; + end + end + memory_collision_a_b <= 0; + end + end + + always @(posedge memory_collision_b_a) begin + if ((output_flag || display_flag)) begin + for (mi = 0; mi < 8; mi = mi + 8) begin + if ((mem_addra_int) == (mem_addrb_reg + mi)) begin + mem[addra_int] <= 8'bx; + end + end + memory_collision_b_a <= 0; + end + end + + always @(posedge data_collision[1]) begin + if (rsta_int == 0 && output_flag) begin + for (ai = 0; ai < 8; ai = ai + 8) begin + if ((mem_addra_int) == (mem_addrb_int + ai)) begin + doa_out <= #100 8'bX; + end + end + end + data_collision[1] <= 0; + end + + always @(posedge data_collision[0]) begin + if (rstb_int == 0 && output_flag) begin + for (bi = 0; bi < 8; bi = bi + 8) begin + if ((mem_addra_int) == (mem_addrb_int + bi)) begin + for (bj = 0; bj < 8; bj = bj + 1) begin + dob_out[bi + bj] <= #100 1'bX; + end + end + end + end + data_collision[0] <= 0; + end + + always @(posedge data_collision_a_b[1]) begin + if (rsta_reg == 0 && output_flag) begin + for (ai = 0; ai < 8; ai = ai + 8) begin + if ((mem_addra_reg) == (mem_addrb_int + ai)) begin + doa_out <= #100 8'bX; + end + end + end + data_collision_a_b[1] <= 0; + end + + always @(posedge data_collision_a_b[0]) begin + if (rstb_int == 0 && output_flag) begin + for (bi = 0; bi < 8; bi = bi + 8) begin + if ((mem_addra_reg) == (mem_addrb_int + bi)) begin + for (bj = 0; bj < 8; bj = bj + 1) begin + dob_out[bi + bj] <= #100 1'bX; + end + end + end + end + data_collision_a_b[0] <= 0; + end + + always @(posedge data_collision_b_a[1]) begin + if (rsta_int == 0 && output_flag) begin + for (ai = 0; ai < 8; ai = ai + 8) begin + if ((mem_addra_int) == (mem_addrb_reg + ai)) begin + doa_out <= #100 8'bX; + end + end + end + data_collision_b_a[1] <= 0; + end + + always @(posedge data_collision_b_a[0]) begin + if (rstb_reg == 0 && output_flag) begin + for (bi = 0; bi < 8; bi = bi + 8) begin + if ((mem_addra_int) == (mem_addrb_reg + bi)) begin + for (bj = 0; bj < 8; bj = bj + 1) begin + dob_out[bi + bj] <= #100 1'bX; + end + end + end + end + data_collision_b_a[0] <= 0; + end + + + // Port A + always @(posedge clka_int) begin + + if (ena_int == 1'b1) begin + + if (rsta_int == 1'b1) begin + doa_out <= #100 0; + end + else begin + if (wea_int == 1'b1) + doa_out <= #100 dia_int; + else + doa_out <= #100 mem[addra_int]; + end + + // memory + if (wea_int == 1'b1) begin + mem[addra_int] <= dia_int; + end + + end + end + + + // Port B + always @(posedge clkb_int) begin + + if (enb_int == 1'b1) begin + + if (rstb_int == 1'b1) begin + dob_out <= #100 0; + end + else begin + if (web_int == 1'b1) + dob_out <= #100 dib_int; + else + dob_out <= #100 mem[addrb_int]; + end + + // memory + if (web_int == 1'b1) begin + mem[addrb_int] <= dib_int; + end + + end + end + + +endmodule + +`endif diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/RAMB8BWER.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/RAMB8BWER.v new file mode 100644 index 0000000..ab064c9 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/RAMB8BWER.v @@ -0,0 +1,1885 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/stan/RAMB8BWER.v,v 1.19.4.2 2010/03/29 22:55:35 wloo Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2008 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ + // / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component 8K-Bit Data and +// / / 1K-Bit Parity Dual Port Block RAM. +// /___/ /\ Filename : RAMB8BWER.v +// \ \ / \ Timestamp : Tue Apr 29 17:59:57 PDT 2008 +// \___\/\___\ +// +// Revision: +// 04/29/08 - Initial version. +// 11/04/08 - Fixed incorrect output during first clock cycle (CR 470964). +// 11/19/08 - Fixed EN_RSTRAM_A/B = FALSE. (IR 497199) +// 12/10/08 - Fixed REGCE in output register (IR 499078). Fixed problem caused by IR 497199. +// 01/26/09 - Update reset behavior (IR 500935). +// 02/19/09 - Fixed asychronous reset in register mode (IR 506208). +// 03/10/09 - X's the unused bits of outputs (CR 511363). +// 03/24/09 - Fixed unusual behavior of X's in the unused bits of outputs (CR 513167). +// 09/22/09 - Fixed SRVAL in SDP mode (CR 532416). +// 12/16/09 - Enhanced memory initialization (CR 540764). +// 02/25/10 - Added DRC of DATA_WIDTH_A/B = 36 is required for SDP mode (CR 550329). +// 03/15/10 - Updated address collision for asynchronous clocks and read first mode (CR 547447). +// - Fixed DRC for SDP mode (CR 552920). +// 03/17/10 - Removed INIT_FILE support (CR 553511). +// End Revision + +`timescale 1 ps/1 ps + +module RAMB8BWER (DOADO, DOBDO, DOPADOP, DOPBDOP, + ADDRAWRADDR, ADDRBRDADDR, CLKAWRCLK, CLKBRDCLK, DIADI, DIBDI, DIPADIP, DIPBDIP, ENAWREN, ENBRDEN, REGCEA, REGCEBREGCE, RSTA, RSTBRST, WEAWEL, WEBWEU); + + output [15:0] DOADO; + output [15:0] DOBDO; + output [1:0] DOPADOP; + output [1:0] DOPBDOP; + + input [12:0] ADDRAWRADDR; + input [12:0] ADDRBRDADDR; + input CLKAWRCLK; + input CLKBRDCLK; + input [15:0] DIADI; + input [15:0] DIBDI; + input [1:0] DIPADIP; + input [1:0] DIPBDIP; + input ENAWREN; + input ENBRDEN; + input REGCEA; + input REGCEBREGCE; + input RSTA; + input RSTBRST; + input [1:0] WEAWEL; + input [1:0] WEBWEU; + + parameter integer DATA_WIDTH_A = 0; + parameter integer DATA_WIDTH_B = 0; + parameter integer DOA_REG = 0; + parameter integer DOB_REG = 0; + parameter EN_RSTRAM_A = "TRUE"; + parameter EN_RSTRAM_B = "TRUE"; + parameter INITP_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_A = 18'h0; + parameter INIT_B = 18'h0; + parameter INIT_FILE = "NONE"; + parameter RAM_MODE = "TDP"; + parameter RSTTYPE = "SYNC"; + parameter RST_PRIORITY_A = "SR"; + parameter RST_PRIORITY_B = "SR"; + parameter SETUP_ALL = 1000; + parameter SETUP_READ_FIRST = 3000; + parameter SIM_COLLISION_CHECK = "ALL"; + parameter SRVAL_A = 18'h0; + parameter SRVAL_B = 18'h0; + parameter WRITE_MODE_A = "WRITE_FIRST"; + parameter WRITE_MODE_B = "WRITE_FIRST"; + + + wire [15:0] addrawraddr_in, addrbrdaddr_in; + wire [12:0] col_addra_reconstruct, col_addrb_reconstruct; + reg [12:0] col_addra_reconstruct_reg, col_addrb_reconstruct_reg; + + localparam widest_width = (DATA_WIDTH_A >= DATA_WIDTH_B) ? DATA_WIDTH_A : DATA_WIDTH_B; + + localparam a_width = (DATA_WIDTH_A == 1) ? 1 : (DATA_WIDTH_A == 2) ? 2 : (DATA_WIDTH_A == 4) ? 4 : + (DATA_WIDTH_A == 9) ? 8 : (DATA_WIDTH_A == 18) ? 16 : (DATA_WIDTH_A == 36) ? 32 : 32; + + localparam b_width = (DATA_WIDTH_B == 1) ? 1 : (DATA_WIDTH_B == 2) ? 2 : (DATA_WIDTH_B == 4) ? 4 : + (DATA_WIDTH_B == 9) ? 8 : (DATA_WIDTH_B == 18) ? 16 : (DATA_WIDTH_B == 36) ? 32 : 32; + + localparam a_widthp = (DATA_WIDTH_A == 9) ? 1 : (DATA_WIDTH_A == 18) ? 2 : (DATA_WIDTH_A == 36) ? 4 : 4; + + localparam b_widthp = (DATA_WIDTH_B == 9) ? 1 : (DATA_WIDTH_B == 18) ? 2 : (DATA_WIDTH_B == 36) ? 4 : 4; + + localparam col_addr_lsb = (widest_width == 1) ? 0 : (widest_width == 2) ? 1 : (widest_width == 4) ? 2 : + (widest_width == 9) ? 3 : (widest_width == 18) ? 4 : (widest_width == 36) ? 5 : 0; + + assign col_addra_reconstruct[12:0] = (WRITE_MODE_A == "READ_FIRST" || WRITE_MODE_B == "READ_FIRST") ? + ({addrawraddr_in[12:6],1'b0,addrawraddr_in[4],4'b0}) : addrawraddr_in[12:0]; + + assign col_addrb_reconstruct[12:0] = (WRITE_MODE_A == "READ_FIRST" || WRITE_MODE_B == "READ_FIRST") ? + ({addrbrdaddr_in[12:6],1'b0,addrbrdaddr_in[4],4'b0}) : addrbrdaddr_in[12:0]; + + localparam width = (widest_width == 1) ? 1 : (widest_width == 2) ? 2 : (widest_width == 4) ? 4 : + (widest_width == 9) ? 8 : (widest_width == 18) ? 16 : (widest_width == 36) ? 32 : 32; + + localparam widthp = (widest_width == 9) ? 1 : (widest_width == 18) ? 2 : (widest_width == 36) ? 4 : 4; + + localparam addrawraddr_lbit_124 = (DATA_WIDTH_A == 1) ? 0 : (DATA_WIDTH_A == 2) ? 1 : + (DATA_WIDTH_A == 4) ? 2 : (DATA_WIDTH_A == 9) ? 3 : + (DATA_WIDTH_A == 18) ? 4 : (DATA_WIDTH_A == 36) ? 5 : 5; + + localparam addrbrdaddr_lbit_124 = (DATA_WIDTH_B == 1) ? 0 : (DATA_WIDTH_B == 2) ? 1 : + (DATA_WIDTH_B == 4) ? 2 : (DATA_WIDTH_B == 9) ? 3 : + (DATA_WIDTH_B == 18) ? 4 : (DATA_WIDTH_B == 36) ? 5 : 5; + + localparam addrawraddr_bit_124 = (DATA_WIDTH_A == 1 && widest_width == 2) ? 0 : (DATA_WIDTH_A == 1 && widest_width == 4) ? 1 : + (DATA_WIDTH_A == 1 && widest_width == 9) ? 2 : (DATA_WIDTH_A == 1 && widest_width == 18) ? 3 : + (DATA_WIDTH_A == 1 && widest_width == 36) ? 4 : (DATA_WIDTH_A == 2 && widest_width == 4) ? 1 : + (DATA_WIDTH_A == 2 && widest_width == 9) ? 2 : (DATA_WIDTH_A == 2 && widest_width == 18) ? 3 : + (DATA_WIDTH_A == 2 && widest_width == 36) ? 4 : (DATA_WIDTH_A == 4 && widest_width == 9) ? 2 : + (DATA_WIDTH_A == 4 && widest_width == 18) ? 3 : (DATA_WIDTH_A == 4 && widest_width == 36) ? 4 : 5; + + localparam addrbrdaddr_bit_124 = (DATA_WIDTH_B == 1 && widest_width == 2) ? 0 : (DATA_WIDTH_B == 1 && widest_width == 4) ? 1 : + (DATA_WIDTH_B == 1 && widest_width == 9) ? 2 : (DATA_WIDTH_B == 1 && widest_width == 18) ? 3 : + (DATA_WIDTH_B == 1 && widest_width == 36) ? 4 : (DATA_WIDTH_B == 2 && widest_width == 4) ? 1 : + (DATA_WIDTH_B == 2 && widest_width == 9) ? 2 : (DATA_WIDTH_B == 2 && widest_width == 18) ? 3 : + (DATA_WIDTH_B == 2 && widest_width == 36) ? 4 : (DATA_WIDTH_B == 4 && widest_width == 9) ? 2 : + (DATA_WIDTH_B == 4 && widest_width == 18) ? 3 : (DATA_WIDTH_B == 4 && widest_width == 36) ? 4 : 5; + + localparam addrawraddr_bit_8 = (DATA_WIDTH_A == 9 && widest_width == 18) ? 3 : (DATA_WIDTH_A == 9 && widest_width == 36) ? 4 : 4; + + localparam addrawraddr_bit_16 = 4; // There is only 36 larger than 18 + + localparam addrbrdaddr_bit_8 = (DATA_WIDTH_B == 9 && widest_width == 18) ? 3 : (DATA_WIDTH_B == 9 && widest_width == 36) ? 4 : 4; + + localparam addrbrdaddr_bit_16 = 4; // There is only 36 larger than 18 + + + localparam mem_depth = (widest_width == 1) ? 8192 : (widest_width == 2) ? 4096 : (widest_width == 4) ? 2048 : + (widest_width == 9) ? 1024 :(widest_width == 18) ? 512 : (widest_width == 36) ? 256 : 8192; + + localparam memp_depth = (widest_width == 9) ? 1024 :(widest_width == 18) ? 512 : (widest_width == 36) ? 256 : 1024; + + localparam INIT_A_int = (RAM_MODE == "SDP" && DATA_WIDTH_A == 36) ? + {INIT_B[17:16],INIT_A[17:16],INIT_B[15:0],INIT_A[15:0]} : INIT_A; + localparam INIT_B_int = (RAM_MODE == "SDP" && DATA_WIDTH_B == 36) ? + {INIT_B[17:16],INIT_A[17:16],INIT_B[15:0],INIT_A[15:0]} : INIT_B; + localparam SRVAL_A_int = (RAM_MODE == "SDP" && DATA_WIDTH_A == 36) ? + {SRVAL_B[17:16],SRVAL_A[17:16],SRVAL_B[15:0],SRVAL_A[15:0]} : SRVAL_A; + localparam SRVAL_B_int = (RAM_MODE == "SDP" && DATA_WIDTH_B == 36) ? + {SRVAL_B[17:16],SRVAL_A[17:16],SRVAL_B[15:0],SRVAL_A[15:0]} : SRVAL_B; + + reg [widest_width-1:0] tmp_mem [mem_depth-1:0]; + + reg [width-1:0] mem [mem_depth-1:0]; + reg [widthp-1:0] memp [memp_depth-1:0]; + + integer count, countp, init_mult, initp_mult, large_width; + integer count1, countp1, i, i1, i_p, i_mem, init_offset, initp_offset; + + reg tmp1; + reg [1:0] wr_mode_a, wr_mode_b; + + reg [31:0] doado_out, doado_buf, doado_outreg, doado_out_out; + reg [31:0] dobdo_out, dobdo_buf, dobdo_outreg, dobdo_out_out; + reg [3:0] dopbdop_out, dopbdop_buf, dopbdop_outreg, dopbdop_out_out; + reg [3:0] dopadop_out, dopadop_buf, dopadop_outreg, dopadop_out_out; + + reg [63:0] di_x = 64'bx; + + reg [7:0] weawel_reg; + reg enbrden_reg; + reg [7:0] webweu_reg, webweu_tmp; + reg rising_clkawrclk = 1'b0, rising_clkbrdclk = 1'b0; + reg [15:0] addrawraddr_reg, addrbrdaddr_reg, addrawraddr_tmp, addrbrdaddr_tmp; + + reg [63:0] diadi_reg, dibdi_reg; + reg [3:0] dipadip_reg; + reg [7:0] dipbdip_reg; + reg [1:0] viol_type = 2'b00, seq = 2'b00; + reg [15:0] addr_tmp; + reg [7:0] we_tmp; + integer viol_time = 0; + reg col_wr_wr_msg = 1, col_wra_rdb_msg = 1, col_wrb_rda_msg = 1; + reg finish_error = 0; + + time curr_time, prev_time; + + wire [15:0] dibdi_in; + wire [15:0] diadi_in; + wire clkawrclk_in, clkbrdclk_in; + + wire [1:0] dipbdip_in; + wire [1:0] dipadip_in; + wire enawren_in, enbrden_in, regcea_in, regcebregce_in, rsta_in, rstbrst_in; + wire [1:0] weawel_in; + wire [1:0] webweu_in; + + wire [a_width-1:0] diadi_int; + wire [b_width-1:0] dibdi_int; + wire [a_widthp-1:0] dipadip_int; + wire [b_widthp-1:0] dipbdip_int; + wire [3:0] weawel_int, webweu_int; + + wire [15:0] doado_out_port, dobdo_out_port; + wire [1:0] dopadop_out_port, dopbdop_out_port; + + integer ram_mode_int = 0, rsttype_int = 0; + + tri0 gsr_in = glbl.GSR; + + assign addrawraddr_in = {3'b000, ADDRAWRADDR}; + assign addrbrdaddr_in = {3'b000, ADDRBRDADDR}; + assign clkawrclk_in = CLKAWRCLK; + assign clkbrdclk_in = CLKBRDCLK; + + assign diadi_in = DIADI; + assign dibdi_in = DIBDI; + assign dipadip_in = DIPADIP; + assign dipbdip_in = DIPBDIP; + assign DOADO = doado_out_port; + assign DOPADOP = dopadop_out_port; + assign DOBDO = dobdo_out_port; + assign DOPBDOP = dopbdop_out_port; + + assign enawren_in = ENAWREN; + assign enbrden_in = ENBRDEN; + assign regcea_in = REGCEA; + assign regcebregce_in = REGCEBREGCE; + assign rsta_in = RSTA; + assign rstbrst_in = RSTBRST; + assign weawel_in = WEAWEL; + assign webweu_in = WEBWEU; + + + generate + case (RAM_MODE) + "TDP" : begin + assign dibdi_int = dibdi_in; + assign diadi_int = diadi_in; // 16 + assign dipbdip_int = dipbdip_in; // 2 + assign dipadip_int = dipadip_in; + assign doado_out_port = doado_out_out; + assign dobdo_out_port = dobdo_out_out; + assign dopadop_out_port = dopadop_out_out; + assign dopbdop_out_port = dopbdop_out_out; + assign webweu_int = webweu_in; + assign weawel_int = weawel_in; //2 + end + "SDP" : begin + assign dibdi_int = 32'b0; + assign diadi_int = {dibdi_in, diadi_in}; // 32 + assign dipbdip_int = 4'b0; + assign dipadip_int = {dipbdip_in, dipadip_in}; // 4 + assign doado_out_port = dobdo_out_out[15:0]; + assign dobdo_out_port = dobdo_out_out[31:16]; + assign dopadop_out_port = dopbdop_out_out[1:0]; + assign dopbdop_out_port = dopbdop_out_out[3:2]; + assign webweu_int = 4'b0; + assign weawel_int = {webweu_in, weawel_in}; // 4 + end + + endcase + endgenerate + + + initial begin + + if (INIT_FILE == "NONE") begin + + init_mult = 256/width; + + for (count = 0; count < init_mult; count = count + 1) begin + + init_offset = count * width; + + mem[count] = INIT_00[init_offset +:width]; + mem[count + (init_mult * 1)] = INIT_01[init_offset +:width]; + mem[count + (init_mult * 2)] = INIT_02[init_offset +:width]; + mem[count + (init_mult * 3)] = INIT_03[init_offset +:width]; + mem[count + (init_mult * 4)] = INIT_04[init_offset +:width]; + mem[count + (init_mult * 5)] = INIT_05[init_offset +:width]; + mem[count + (init_mult * 6)] = INIT_06[init_offset +:width]; + mem[count + (init_mult * 7)] = INIT_07[init_offset +:width]; + mem[count + (init_mult * 8)] = INIT_08[init_offset +:width]; + mem[count + (init_mult * 9)] = INIT_09[init_offset +:width]; + mem[count + (init_mult * 10)] = INIT_0A[init_offset +:width]; + mem[count + (init_mult * 11)] = INIT_0B[init_offset +:width]; + mem[count + (init_mult * 12)] = INIT_0C[init_offset +:width]; + mem[count + (init_mult * 13)] = INIT_0D[init_offset +:width]; + mem[count + (init_mult * 14)] = INIT_0E[init_offset +:width]; + mem[count + (init_mult * 15)] = INIT_0F[init_offset +:width]; + mem[count + (init_mult * 16)] = INIT_10[init_offset +:width]; + mem[count + (init_mult * 17)] = INIT_11[init_offset +:width]; + mem[count + (init_mult * 18)] = INIT_12[init_offset +:width]; + mem[count + (init_mult * 19)] = INIT_13[init_offset +:width]; + mem[count + (init_mult * 20)] = INIT_14[init_offset +:width]; + mem[count + (init_mult * 21)] = INIT_15[init_offset +:width]; + mem[count + (init_mult * 22)] = INIT_16[init_offset +:width]; + mem[count + (init_mult * 23)] = INIT_17[init_offset +:width]; + mem[count + (init_mult * 24)] = INIT_18[init_offset +:width]; + mem[count + (init_mult * 25)] = INIT_19[init_offset +:width]; + mem[count + (init_mult * 26)] = INIT_1A[init_offset +:width]; + mem[count + (init_mult * 27)] = INIT_1B[init_offset +:width]; + mem[count + (init_mult * 28)] = INIT_1C[init_offset +:width]; + mem[count + (init_mult * 29)] = INIT_1D[init_offset +:width]; + mem[count + (init_mult * 30)] = INIT_1E[init_offset +:width]; + mem[count + (init_mult * 31)] = INIT_1F[init_offset +:width]; + end // for (count = 0; count < init_mult; count = count + 1) + + + if (width >= 8) begin + + initp_mult = 256/widthp; + + for (countp = 0; countp < initp_mult; countp = countp + 1) begin + + initp_offset = countp * widthp; + + memp[countp] = INITP_00[initp_offset +:widthp]; + memp[countp + (initp_mult * 1)] = INITP_01[initp_offset +:widthp]; + memp[countp + (initp_mult * 2)] = INITP_02[initp_offset +:widthp]; + memp[countp + (initp_mult * 3)] = INITP_03[initp_offset +:widthp]; + + end // for (countp = 0; countp < initp_mult; countp = countp + 1) + end // if (width >= 8) + + end // if (INIT_FILE == "NONE") + + else begin + + $readmemh (INIT_FILE, tmp_mem); + + case (widest_width) + + 1, 2, 4 : for (i_mem = 0; i_mem <= mem_depth; i_mem = i_mem + 1) + mem[i_mem] = tmp_mem [i_mem]; + + 9 : for (i_mem = 0; i_mem <= mem_depth; i_mem = i_mem + 1) begin + mem[i_mem] = tmp_mem[i_mem][0 +: 8]; + memp[i_mem] = tmp_mem[i_mem][8 +: 1]; + end + + 18 : for (i_mem = 0; i_mem <= mem_depth; i_mem = i_mem + 1) begin + mem[i_mem] = tmp_mem[i_mem][0 +: 16]; + memp[i_mem] = tmp_mem[i_mem][16 +: 2]; + end + + 36 : for (i_mem = 0; i_mem <= mem_depth; i_mem = i_mem + 1) begin + mem[i_mem] = tmp_mem[i_mem][0 +: 32]; + memp[i_mem] = tmp_mem[i_mem][32 +: 4]; + end + + endcase // case(widest_width) + + end // else: !if(INIT_FILE == "NONE") + + + if (INIT_FILE != "NONE") begin + $display("DRC Error : The INIT_FILE attribute on RAMB8BWER instance %m is set to %s. Currently, initializing memory contents of this component via an external file is not supported. Please set this attribute to the default value of NONE and specify any initialization of this component via the INIT_xx attributes.", INIT_FILE); + finish_error = 1; + end + + + case (DATA_WIDTH_A) + + 0, 1, 2, 4, 9, 18: ; + 36: begin + if (RAM_MODE != "SDP") begin + $display("DRC error : The attribute DATA_WIDTH_A = 36 requires RAM_MODE set to SDP on RAMB8BWER instance %m."); + finish_error = 1; + end + end + default : begin + $display("Attribute Syntax Error : The attribute DATA_WIDTH_A on RAMB8BWER instance %m is set to %d. Legal values for this attribute are 0, 1, 2, 4, 9, 18 or 36.", DATA_WIDTH_A); + finish_error = 1; + end + + endcase // case(DATA_WIDTH_A) + + + case (DATA_WIDTH_B) + + 0, 1, 2, 4, 9, 18: ; + 36: begin + if (RAM_MODE != "SDP") begin + $display("DRC error : The attribute DATA_WIDTH_B = 36 requires RAM_MODE set to SDP on RAMB8BWER instance %m."); + finish_error = 1; + end + end + default : begin + $display("Attribute Syntax Error : The attribute DATA_WIDTH_B on RAMB8BWER instance %m is set to %d. Legal values for this attribute are 0, 1, 2, 4, 9, 18 or 36.", DATA_WIDTH_B); + finish_error = 1; + end + + endcase // case(DATA_WIDTH_B) + + + if (DATA_WIDTH_A == 0 && DATA_WIDTH_B == 0) begin + $display("Attribute Syntax Error : Attributes DATA_WIDTH_A and DATA_WIDTH_B on RAMB8BWER instance %m, both can not be 0."); + finish_error = 1; + end + + + case (WRITE_MODE_A) + "WRITE_FIRST" : wr_mode_a <= 2'b00; + "READ_FIRST" : wr_mode_a <= 2'b01; + "NO_CHANGE" : wr_mode_a <= 2'b10; + default : begin + $display("Attribute Syntax Error : The Attribute WRITE_MODE_A on RAMB8BWER instance %m is set to %s. Legal values for this attribute are WRITE_FIRST, READ_FIRST or NO_CHANGE.", WRITE_MODE_A); + finish_error = 1; + end + endcase + + + case (WRITE_MODE_B) + "WRITE_FIRST" : wr_mode_b <= 2'b00; + "READ_FIRST" : wr_mode_b <= 2'b01; + "NO_CHANGE" : wr_mode_b <= 2'b10; + default : begin + $display("Attribute Syntax Error : The Attribute WRITE_MODE_B on RAMB8BWER instance %m is set to %s. Legal values for this attribute are WRITE_FIRST, READ_FIRST or NO_CHANGE.", WRITE_MODE_B); + finish_error = 1; + end + endcase + + + if ((SIM_COLLISION_CHECK != "ALL") && (SIM_COLLISION_CHECK != "NONE") && (SIM_COLLISION_CHECK != "WARNING_ONLY") && (SIM_COLLISION_CHECK != "GENERATE_X_ONLY")) begin + + $display("Attribute Syntax Error : The attribute SIM_COLLISION_CHECK on RAMB8BWER instance %m is set to %s. Legal values for this attribute are ALL, NONE, WARNING_ONLY or GENERATE_X_ONLY.", SIM_COLLISION_CHECK); + finish_error = 1; + + end + + + case (RAM_MODE) + "TDP" : ram_mode_int <= 0; + "SDP" : begin + ram_mode_int <= 1; + + if (DATA_WIDTH_A != 36 || DATA_WIDTH_B != 36) begin + $display("DRC error : DATA_WIDTH_A is set to %d and DATA_WIDTH_B is set to %d when RAM_MODE is set to SDP. DATA_WIDTH_A and DATA_WIDTH_B are required to be set to 36 in simple dual port mode on RAMB8BWER instance %m.", DATA_WIDTH_A, DATA_WIDTH_B); + finish_error = 1; + end + end + default : begin + $display("Attribute Syntax Error : The attribute RAM_MODE on RAMB8BWER instance %m is set to %s. Legal values for this attribute are SDP or TDP.", RAM_MODE); + finish_error = 1; + end + endcase // case(RAM_MODE) + + + case (RSTTYPE) + "SYNC" : rsttype_int <= 0; + "ASYNC" : rsttype_int <= 1; + default : begin + $display("Attribute Syntax Error : The attribute RSTTYPE on RAMB8BWER instance %m is set to %s. Legal values for this attribute are ASYNC or SYNC.", RSTTYPE); + finish_error = 1; + end + endcase // case(RSTTYPE) + + + if (RAM_MODE == "SDP" && WRITE_MODE_A != "READ_FIRST") begin + $display("DRC Error : The attribute WRITE_MODE_A must set to READ_FIRST when RAM_MODE = SDP on RAMB8BWER instance %m."); + finish_error = 1; + end + + + if (RAM_MODE == "SDP" && WRITE_MODE_B != "READ_FIRST") begin + $display("DRC Error : The attribute WRITE_MODE_B must set to READ_FIRST when RAM_MODE = SDP on RAMB8BWER instance %m."); + finish_error = 1; + end + + + if ((EN_RSTRAM_A != "TRUE") && (EN_RSTRAM_A != "FALSE")) begin + $display("Attribute Syntax Error : The attribute EN_RSTRAM_A on RAMB8BWER instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", EN_RSTRAM_A); + finish_error = 1; + end + + + if ((EN_RSTRAM_B != "TRUE") && (EN_RSTRAM_B != "FALSE")) begin + $display("Attribute Syntax Error : The attribute EN_RSTRAM_B on RAMB8BWER instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", EN_RSTRAM_B); + finish_error = 1; + end + + + if ((RST_PRIORITY_A != "SR") && (RST_PRIORITY_A != "CE")) begin + $display("Attribute Syntax Error : The attribute RST_PRIORITY_A on RAMB8BWER instance %m is set to %s. Legal values for this attribute are CE or SR.", RST_PRIORITY_A); + finish_error = 1; + end + + + if ((RST_PRIORITY_A != "SR") && (RST_PRIORITY_A != "CE")) begin + $display("Attribute Syntax Error : The attribute RST_PRIORITY_A on RAMB8BWER instance %m is set to %s. Legal values for this attribute are CE or SR.", RST_PRIORITY_A); + finish_error = 1; + end + + + if (finish_error == 1) + $finish; + + + end // initial begin + + + always @(gsr_in) + if (gsr_in) begin + + assign doado_out = INIT_A_int[0 +: a_width]; + + if (a_width >= 8) begin + assign dopadop_out = INIT_A_int[a_width +: a_widthp]; + end + + assign dobdo_out = INIT_B_int[0 +: b_width]; + + if (b_width >= 8) begin + assign dopbdop_out = INIT_B_int[b_width +: b_widthp]; + end + + end + else begin + deassign doado_out; + deassign dopadop_out; + deassign dobdo_out; + deassign dopbdop_out; + end + + + always @(rsta_in or enawren_in or regcea_in) begin + + if (rsttype_int == 1 && gsr_in == 1'b0 && rsta_in === 1'b1) begin // async reset + + // reset latch regardless DOA_REG + if (((enawren_in == 1'b1 && RST_PRIORITY_A == "CE") || RST_PRIORITY_A == "SR") && EN_RSTRAM_A == "TRUE") begin + + assign doado_buf = SRVAL_A_int[0 +: a_width]; + assign doado_out = SRVAL_A_int[0 +: a_width]; + + if (a_width >= 8) begin + assign dopadop_buf = SRVAL_A_int[a_width +: a_widthp]; + assign dopadop_out = SRVAL_A_int[a_width +: a_widthp]; + end + end + + + if (DOA_REG == 1) begin + + if ((regcea_in == 1'b1 && RST_PRIORITY_A == "CE") || RST_PRIORITY_A == "SR") begin + assign doado_outreg = SRVAL_A_int[0 +: a_width]; + + if (a_width >= 8) + assign dopadop_outreg = SRVAL_A_int[a_width +: a_widthp]; + + end + end + end // if (rsttype_int == 1 && gsr_in == 1'b0 && rsta_in === 1'b1) + else if (rsta_in === 1'b0) begin + + deassign doado_buf; + deassign doado_out; + deassign dopadop_buf; + deassign dopadop_out; + deassign doado_outreg; + deassign dopadop_outreg; + + end + + end // always @ (rsta_in or enawren_in or regcea_in) + + + always @(rstbrst_in or enbrden_in or regcebregce_in) begin + + if (rsttype_int == 1 && gsr_in == 1'b0 && rstbrst_in === 1'b1) begin + + // reset latch regardless DOB_REG + if (((enbrden_in == 1'b1 && RST_PRIORITY_B == "CE") || RST_PRIORITY_B == "SR") && EN_RSTRAM_B == "TRUE") begin + + assign dobdo_buf = SRVAL_B_int[0 +: b_width]; + assign dobdo_out = SRVAL_B_int[0 +: b_width]; + + if (b_width >= 8) begin + assign dopbdop_buf = SRVAL_B_int[b_width +: b_widthp]; + assign dopbdop_out = SRVAL_B_int[b_width +: b_widthp]; + end + end + + + if (DOB_REG == 1) begin + + if ((regcebregce_in == 1'b1 && RST_PRIORITY_B == "CE") || RST_PRIORITY_B == "SR") begin + assign dobdo_outreg = SRVAL_B_int[0 +: b_width]; + + if (b_width >= 8) + assign dopbdop_outreg = SRVAL_B_int[b_width +: b_widthp]; + + end + end + end // if (rsttype_int == 1 && gsr_in == 1'b0 && rstbrst_in === 1'b1) + else if (rstbrst_in == 1'b0) begin + + deassign dobdo_buf; + deassign dobdo_out; + deassign dopbdop_buf; + deassign dopbdop_out; + deassign dobdo_outreg; + deassign dopbdop_outreg; + + end + + end // always @ (rstbrst_in or enbrden_in or regcebregce_in) + + + always @(posedge clkawrclk_in) begin + + rising_clkawrclk = 1; + + if (enawren_in === 1'b1) begin + prev_time = curr_time; + curr_time = $time; + addrawraddr_reg = addrawraddr_in; + weawel_reg = weawel_int; + diadi_reg = diadi_int; + dipadip_reg = dipadip_int; + col_addra_reconstruct_reg = col_addra_reconstruct; + end + + end + + always @(posedge clkbrdclk_in) begin + + rising_clkbrdclk = 1; + + if (enbrden_in === 1'b1) begin + prev_time = curr_time; + curr_time = $time; + addrbrdaddr_reg = addrbrdaddr_in; + webweu_reg = webweu_int; + enbrden_reg = enbrden_in; + dibdi_reg = dibdi_int; + dipbdip_reg = dipbdip_int; + col_addrb_reconstruct_reg = col_addrb_reconstruct; + end + + end // always @ (posedge clkbrdclk_in) + + + always @(posedge rising_clkawrclk or posedge rising_clkbrdclk) begin + + +/************************************* Collision starts *****************************************/ + + if (SIM_COLLISION_CHECK != "NONE") begin + + if (gsr_in === 1'b0) begin + if (curr_time - prev_time <= 100) begin + viol_time = 1; + end + else if (curr_time - prev_time <= SETUP_READ_FIRST) begin + viol_time = 2; + end + + + if (enawren_in === 1'b0 || enbrden_in === 1'b0) + viol_time = 0; + + + if ((DATA_WIDTH_A <= 9 && weawel_int[0] === 1'b0) || (DATA_WIDTH_A == 18 && weawel_int[1:0] === 2'b00) || (DATA_WIDTH_A == 36 && weawel_int[3:0] === 4'b0000)) + if ((DATA_WIDTH_B <= 9 && webweu_int[0] === 1'b0) || (DATA_WIDTH_B == 18 && webweu_int[1:0] === 2'b00) || (DATA_WIDTH_B == 36 && webweu_int[3:0] === 4'b0000)) + viol_time = 0; + + + if (viol_time != 0) begin + + if ((rising_clkawrclk && rising_clkbrdclk) || viol_time == 1) begin + if (addrawraddr_in[12:col_addr_lsb] === addrbrdaddr_in[12:col_addr_lsb]) begin + + viol_type = 2'b01; + + task_rd_ram_a (addrawraddr_in, doado_buf, dopadop_buf); + task_rd_ram_b (addrbrdaddr_in, dobdo_buf, dopbdop_buf); + + task_col_wr_ram_a (2'b00, webweu_int, weawel_int, di_x, di_x[7:0], addrbrdaddr_in, addrawraddr_in); + task_col_wr_ram_b (2'b00, weawel_int, webweu_int, di_x, di_x[7:0], addrawraddr_in, addrbrdaddr_in); + + task_col_rd_ram_a (2'b01, webweu_int, weawel_int, addrawraddr_in, doado_buf, dopadop_buf); + task_col_rd_ram_b (2'b01, weawel_int, webweu_int, addrbrdaddr_in, dobdo_buf, dopbdop_buf); + + task_col_wr_ram_a (2'b10, webweu_int, weawel_int, diadi_int, dipadip_int, addrbrdaddr_in, addrawraddr_in); + task_col_wr_ram_b (2'b10, weawel_int, webweu_int, dibdi_int, dipbdip_int, addrawraddr_in, addrbrdaddr_in); + + if (wr_mode_a != 2'b01) + task_col_rd_ram_a (2'b11, webweu_int, weawel_int, addrawraddr_in, doado_buf, dopadop_buf); + if (wr_mode_b != 2'b01) + task_col_rd_ram_b (2'b11, weawel_int, webweu_int, addrbrdaddr_in, dobdo_buf, dopbdop_buf); + + end // if (addrawraddr_in[12:col_addr_lsb] === addrbrdaddr_in[12:col_addr_lsb]) + else + viol_time = 0; + + end + else if (rising_clkawrclk && !rising_clkbrdclk) begin + if (col_addra_reconstruct[12:col_addr_lsb] === col_addrb_reconstruct_reg[12:col_addr_lsb]) begin + + viol_type = 2'b10; + + task_rd_ram_a (addrawraddr_in, doado_buf, dopadop_buf); + + task_col_wr_ram_a (2'b00, webweu_reg, weawel_int, di_x, di_x[7:0], addrbrdaddr_reg, addrawraddr_in); + task_col_wr_ram_b (2'b00, weawel_int, webweu_reg, di_x, di_x[7:0], addrawraddr_in, addrbrdaddr_reg); + + task_col_rd_ram_a (2'b01, webweu_reg, weawel_int, addrawraddr_in, doado_buf, dopadop_buf); + task_col_rd_ram_b (2'b01, weawel_int, webweu_reg, addrbrdaddr_reg, dobdo_buf, dopbdop_buf); + + task_col_wr_ram_a (2'b10, webweu_reg, weawel_int, diadi_int, dipadip_int, addrbrdaddr_reg, addrawraddr_in); + task_col_wr_ram_b (2'b10, weawel_int, webweu_reg, dibdi_reg, dipbdip_reg, addrawraddr_in, addrbrdaddr_reg); + + if (wr_mode_a != 2'b01) + task_col_rd_ram_a (2'b11, webweu_reg, weawel_int, addrawraddr_in, doado_buf, dopadop_buf); + if (wr_mode_b != 2'b01) + task_col_rd_ram_b (2'b11, weawel_int, webweu_reg, addrbrdaddr_reg, dobdo_buf, dopbdop_buf); + + if (wr_mode_a == 2'b01 || wr_mode_b == 2'b01) begin + task_col_wr_ram_a (2'b10, webweu_reg, weawel_int, di_x, di_x[7:0], addrbrdaddr_reg, addrawraddr_in); + task_col_wr_ram_b (2'b10, weawel_int, webweu_reg, di_x, di_x[7:0], addrawraddr_in, addrbrdaddr_reg); + end + + end // if (addrawraddr_in[12:col_addr_lsb] === addrbrdaddr_reg[12:col_addr_lsb]) + else + viol_time = 0; + + end + else if (!rising_clkawrclk && rising_clkbrdclk) begin + if (col_addra_reconstruct_reg[12:col_addr_lsb] === col_addrb_reconstruct[12:col_addr_lsb]) begin + + viol_type = 2'b11; + + task_rd_ram_b (addrbrdaddr_in, dobdo_buf, dopbdop_buf); + + task_col_wr_ram_a (2'b00, webweu_int, weawel_reg, di_x, di_x[7:0], addrbrdaddr_in, addrawraddr_reg); + task_col_wr_ram_b (2'b00, weawel_reg, webweu_int, di_x, di_x[7:0], addrawraddr_reg, addrbrdaddr_in); + + task_col_rd_ram_a (2'b01, webweu_int, weawel_reg, addrawraddr_reg, doado_buf, dopadop_buf); + task_col_rd_ram_b (2'b01, weawel_reg, webweu_int, addrbrdaddr_in, dobdo_buf, dopbdop_buf); + + task_col_wr_ram_a (2'b10, webweu_int, weawel_reg, diadi_reg, dipadip_reg, addrbrdaddr_in, addrawraddr_reg); + task_col_wr_ram_b (2'b10, weawel_reg, webweu_int, dibdi_int, dipbdip_int, addrawraddr_reg, addrbrdaddr_in); + + if (wr_mode_a != 2'b01) + task_col_rd_ram_a (2'b11, webweu_int, weawel_reg, addrawraddr_reg, doado_buf, dopadop_buf); + if (wr_mode_b != 2'b01) + task_col_rd_ram_b (2'b11, weawel_reg, webweu_int, addrbrdaddr_in, dobdo_buf, dopbdop_buf); + + if (wr_mode_a == 2'b01 || wr_mode_b == 2'b01) begin + task_col_wr_ram_a (2'b10, webweu_int, weawel_reg, di_x, di_x[7:0], addrbrdaddr_in, addrawraddr_reg); + task_col_wr_ram_b (2'b10, weawel_reg, webweu_int, di_x, di_x[7:0], addrawraddr_reg, addrbrdaddr_in); + end + + + end // if (addrawraddr_reg[12:col_addr_lsb] === addrbrdaddr_in[12:col_addr_lsb]) + else + viol_time = 0; + + end + + end // if (viol_time != 0) + end // if (gsr_in === 1'b0) + + if (SIM_COLLISION_CHECK == "WARNING_ONLY") + viol_time = 0; + + end // if (SIM_COLLISION_CHECK != "NONE") + + +/*************************************** end collision ********************************/ + + + if (gsr_in == 1'b0) begin + +/**************************** Port A ****************************************/ + if (rising_clkawrclk) begin + + if ((enawren_in == 1'b1 && RST_PRIORITY_A == "CE") || RST_PRIORITY_A == "SR") begin + + if (rsta_in == 1'b1 && EN_RSTRAM_A == "TRUE") begin // sync reset + doado_buf = SRVAL_A_int[0 +: a_width]; + doado_out = SRVAL_A_int[0 +: a_width]; + + if (a_width >= 8) begin + dopadop_buf = SRVAL_A_int[a_width +: a_widthp]; + dopadop_out = SRVAL_A_int[a_width +: a_widthp]; + end + end + + + if (viol_time == 0) begin + + if (wr_mode_a == 2'b01 && (rsta_in === 1'b0 || EN_RSTRAM_A == "FALSE")) // read_first + task_rd_ram_a (addrawraddr_in, doado_buf, dopadop_buf); + + + if (enawren_in == 1'b1) + task_wr_ram_a (weawel_int, diadi_int, dipadip_int, addrawraddr_in); // write + + + if (wr_mode_a != 2'b01 && (rsta_in === 1'b0 || EN_RSTRAM_A == "FALSE")) // !read_first + task_rd_ram_a (addrawraddr_in, doado_buf, dopadop_buf); + + end // if (viol_time == 0) + + end // if ((enawren_in == 1'b1 && RST_PRIORITY_A == "CE") || RST_PRIORITY_A == "SR") + + end // if (rising_clkawrclk) + // end of port A + + +/************************************** port B ***************************************************************/ + if (rising_clkbrdclk) begin + + if ((enbrden_in == 1'b1 && RST_PRIORITY_B == "CE") || RST_PRIORITY_B == "SR") begin + if (rstbrst_in == 1'b1 && EN_RSTRAM_B == "TRUE") begin + + dobdo_buf = SRVAL_B_int[0 +: b_width]; + dobdo_out = SRVAL_B_int[0 +: b_width]; + + if (b_width >= 8) begin + dopbdop_buf = SRVAL_B_int[b_width +: b_widthp]; + dopbdop_out = SRVAL_B_int[b_width +: b_widthp]; + end + + end + + + if (viol_time == 0) begin + + if (wr_mode_b == 2'b01 && (rstbrst_in === 1'b0 || EN_RSTRAM_B == "FALSE")) // read_first + task_rd_ram_b (addrbrdaddr_in, dobdo_buf, dopbdop_buf); + + + if (enbrden_in == 1'b1) + task_wr_ram_b (webweu_int, dibdi_int, dipbdip_int, addrbrdaddr_in); // write + + + if (wr_mode_b != 2'b01 && (rstbrst_in === 1'b0 || EN_RSTRAM_B == "FALSE")) // !read_first + task_rd_ram_b (addrbrdaddr_in, dobdo_buf, dopbdop_buf); + + end // if (viol_time == 0) + + end // if ((enbrden_in == 1'b1 && RST_PRIORITY_B == "CE") || RST_PRIORITY_B == "SR") + + end // if (rising_clkbrdclk) + // end of port B + + + // writing outputs of port A + if (enawren_in && (rising_clkawrclk || viol_time != 0)) begin + + if ((rsta_in === 1'b0 || EN_RSTRAM_A == "FALSE") && (wr_mode_a != 2'b10 || (DATA_WIDTH_A <= 9 && weawel_int[0] === 1'b0) || (DATA_WIDTH_A == 18 && weawel_int[1:0] === 2'b00) || (DATA_WIDTH_A == 36 && weawel_int[3:0] === 4'b0000))) begin + + doado_out <= doado_buf; + + if (a_width >= 8) + dopadop_out <= dopadop_buf; + + end + + end + + + // writing outputs of port B + if (enbrden_in && (rising_clkbrdclk || viol_time != 0)) begin + + if ((rstbrst_in === 1'b0 || EN_RSTRAM_B == "FALSE") && (wr_mode_b != 2'b10 || (DATA_WIDTH_B <= 9 && webweu_int[0] === 1'b0) || (DATA_WIDTH_B == 18 && webweu_int[1:0] === 2'b00) || (DATA_WIDTH_B == 36 && webweu_int[3:0] === 4'b0000))) begin + + dobdo_out <= dobdo_buf; + + if (b_width >= 8) + dopbdop_out <= dopbdop_buf; + + end + + end + + end // if (gsr_in == 1'b0) + + + viol_time = 0; + rising_clkawrclk = 0; + rising_clkbrdclk = 0; + viol_type = 2'b00; + col_wr_wr_msg = 1; + col_wra_rdb_msg = 1; + col_wrb_rda_msg = 1; + + + end // always @ (posedge rising_clkawrclk or posedge rising_clkbrdclk) + + + // ***** Output Registers **** Port A ***** + always @(posedge clkawrclk_in or posedge gsr_in) begin + + if (DOA_REG == 1) begin + + if (gsr_in == 1'b1) begin + + doado_outreg <= INIT_A_int[0 +: a_width]; + + if (a_width >= 8) + dopadop_outreg <= INIT_A_int[a_width +: a_widthp]; + + end + else if (gsr_in == 1'b0) begin + + if (RST_PRIORITY_A == "CE") begin + if (regcea_in == 1'b1) begin + + if (rsta_in === 1'b1) begin + + doado_outreg <= SRVAL_A_int[0 +: a_width]; + + if (a_width >= 8) + dopadop_outreg <= SRVAL_A_int[a_width +: a_widthp]; + + end + else if (rsta_in === 1'b0) begin + + doado_outreg <= doado_out; + + if (a_width >= 8) + dopadop_outreg <= dopadop_out; + + end + + end + end // if (RST_PRIORITY_A == "CE") + else begin + + if (rsta_in === 1'b1) begin + + doado_outreg <= SRVAL_A_int[0 +: a_width]; + + if (a_width >= 8) + dopadop_outreg <= SRVAL_A_int[a_width +: a_widthp]; + + end + else if (rsta_in === 1'b0) begin + + if (regcea_in == 1'b1) begin + + doado_outreg <= doado_out; + + if (a_width >= 8) + dopadop_outreg <= dopadop_out; + + end + + end + + end + + end // if (gsr_in == 1'b0) + + end // if (DOA_REG == 1) + + end // always @ (posedge clkawrclk_in or posedge gsr_in) + + + always @(doado_out or dopadop_out or doado_outreg or dopadop_outreg) begin + + case (DOA_REG) + + 0 : begin + doado_out_out[0 +: a_width] = doado_out[0 +: a_width]; + + if (a_width >= 8) + dopadop_out_out[0 +: a_widthp] = dopadop_out[0 +: a_widthp]; + + end + 1 : begin + doado_out_out[0 +: a_width] = doado_outreg[0 +: a_width]; + + if (a_width >= 8) + dopadop_out_out[0 +: a_widthp] = dopadop_outreg[0 +: a_widthp]; + + end + default : begin + $display("Attribute Syntax Error : The attribute DOA_REG on RAMB8BWER instance %m is set to %2d. Legal values for this attribute are 0 or 1.", DOA_REG); + $finish; + end + + endcase + + end // always @ (doado_out or dopadop_out or doado_outreg or dopadop_outreg) + + +// ***** Output Registers **** Port B ***** + always @(posedge clkbrdclk_in or posedge gsr_in) begin + + if (DOB_REG == 1) begin + + if (gsr_in == 1'b1) begin + + dobdo_outreg <= INIT_B_int[0 +: b_width]; + + if (b_width >= 8) + dopbdop_outreg <= INIT_B_int[b_width +: b_widthp]; + + end + else if (gsr_in == 1'b0) begin + + if (RST_PRIORITY_B == "CE") begin + + if (regcebregce_in == 1'b1) begin + if (rstbrst_in === 1'b1) begin + + dobdo_outreg <= SRVAL_B_int[0 +: b_width]; + + if (b_width >= 8) + dopbdop_outreg <= SRVAL_B_int[b_width +: b_widthp]; + + end + else if (rstbrst_in === 1'b0) begin + + dobdo_outreg <= dobdo_out; + + if (b_width >= 8) + dopbdop_outreg <= dopbdop_out; + + end + + end + + end // if (RST_PRIORITY_B == "CE") + else begin + + if (rstbrst_in === 1'b1) begin + + dobdo_outreg <= SRVAL_B_int[0 +: b_width]; + + if (b_width >= 8) + dopbdop_outreg <= SRVAL_B_int[b_width +: b_widthp]; + + end + else if (rstbrst_in === 1'b0) begin + + if (regcebregce_in == 1'b1) begin + + dobdo_outreg <= dobdo_out; + + if (b_width >= 8) + dopbdop_outreg <= dopbdop_out; + + end + + end + + end // else: !if(RST_PRIORITY_B == "CE") + + end // if (gsr_in == 1'b0) + + end // if (DOB_REG == 1) + + end // always @ (posedge clkbrdclk_in or posedge gsr_in) + + + always @(dobdo_out or dopbdop_out or dobdo_outreg or dopbdop_outreg) begin + + case (DOB_REG) + + 0 : begin + dobdo_out_out[0 +: b_width] = dobdo_out[0 +: b_width]; + + if (b_width >= 8) + dopbdop_out_out[0 +: b_widthp] = dopbdop_out[0 +: b_widthp]; + + end + 1 : begin + dobdo_out_out[0 +: b_width] = dobdo_outreg[0 +: b_width]; + + if (b_width >= 8) + dopbdop_out_out[0 +: b_widthp] = dopbdop_outreg[0 +: b_widthp]; + + end + default : begin + $display("Attribute Syntax Error : The attribute DOB_REG on RAMB8BWER instance %m is set to %2d. Legal values for this attribute are 0 or 1.", DOB_REG); + $finish; + end + + endcase + + end // always @ (dobdo_out or dopbdop_out or dobdo_outreg or dopbdop_outreg) + + +/******************************************** task and function **************************************/ + + task task_ram; + + input we; + input [7:0] di; + input dip; + inout [7:0] mem_task; + inout memp_task; + + begin + + if (we == 1'b1) begin + + mem_task = di; + + if (width >= 8) + memp_task = dip; + end + end + + endtask // task_ram + + + task task_ram_col; + + input we_o; + input we; + input [7:0] di; + input dip; + inout [7:0] mem_task; + inout memp_task; + integer i; + + begin + + if (we == 1'b1) begin + + for (i = 0; i < 8; i = i + 1) + if (mem_task[i] !== 1'bx || !(we === we_o && we === 1'b1)) + mem_task[i] = di[i]; + + if (width >= 8 && (memp_task !== 1'bx || !(we === we_o && we === 1'b1))) + memp_task = dip; + + end + end + + endtask // task_ram_col + + + task task_x_buf; + input [1:0] wr_rd_mode; + input integer do_uindex; + input integer do_lindex; + input integer dop_index; + input [63:0] do_ltmp; + inout [63:0] do_tmp; + input [7:0] dop_ltmp; + inout [7:0] dop_tmp; + integer i; + + begin + + if (wr_rd_mode == 2'b01) begin + for (i = do_lindex; i <= do_uindex; i = i + 1) begin + if (do_ltmp[i] === 1'bx) + do_tmp[i] = 1'bx; + end + + if (dop_ltmp[dop_index] === 1'bx) + dop_tmp[dop_index] = 1'bx; + + end // if (wr_rd_mode == 2'b01) + else begin + do_tmp[do_lindex +: 8] = do_ltmp[do_lindex +: 8]; + dop_tmp[dop_index] = dop_ltmp[dop_index]; + + end // else: !if(wr_rd_mode == 2'b01) + end + + endtask // task_x_buf + + + task task_col_wr_ram_a; + + input [1:0] seq; + input [7:0] webweu_tmp; + input [7:0] weawel_tmp; + input [63:0] diadi_tmp; + input [7:0] dipadip_tmp; + input [15:0] addrbrdaddr_tmp; + input [15:0] addrawraddr_tmp; + + begin + + case (a_width) + + 1, 2, 4 : begin + if (!(weawel_tmp[0] === 1'b1 && webweu_tmp[0] === 1'b1 && a_width > b_width) || seq == 2'b10) begin + if (a_width >= width) + task_ram_col (webweu_tmp[0], weawel_tmp[0], diadi_tmp[a_width-1:0], 1'b0, mem[addrawraddr_tmp[14:addrawraddr_lbit_124]], tmp1); + else + task_ram_col (webweu_tmp[0], weawel_tmp[0], diadi_tmp[a_width-1:0], 1'b0, mem[addrawraddr_tmp[14:addrawraddr_bit_124+1]][(addrawraddr_tmp[addrawraddr_bit_124:addrawraddr_lbit_124] * a_width) +: a_width], tmp1); + + if (seq == 2'b00) + chk_for_col_msg (weawel_tmp[0], webweu_tmp[0], addrawraddr_tmp, addrbrdaddr_tmp); + + end // if (!(weawel_tmp[0] === 1'b1 && webweu_tmp[0] === 1'b1 && a_width > b_width) || seq == 2'b10) + end // case: 1, 2, 4 + 8 : begin + if (!(weawel_tmp[0] === 1'b1 && webweu_tmp[0] === 1'b1 && a_width > b_width) || seq == 2'b10) begin + if (a_width >= width) + task_ram_col (webweu_tmp[0], weawel_tmp[0], diadi_tmp[7:0], dipadip_tmp[0], mem[addrawraddr_tmp[14:3]], memp[addrawraddr_tmp[14:3]]); + else + task_ram_col (webweu_tmp[0], weawel_tmp[0], diadi_tmp[7:0], dipadip_tmp[0], mem[addrawraddr_tmp[14:addrawraddr_bit_8+1]][(addrawraddr_tmp[addrawraddr_bit_8:3] * 8) +: 8], memp[addrawraddr_tmp[14:addrawraddr_bit_8+1]][(addrawraddr_tmp[addrawraddr_bit_8:3] * 1) +: 1]); + + if (seq == 2'b00) + chk_for_col_msg (weawel_tmp[0], webweu_tmp[0], addrawraddr_tmp, addrbrdaddr_tmp); + + end // if (a_width <= b_width) + end // case: 8 + 16 : begin + if (!(weawel_tmp[0] === 1'b1 && webweu_tmp[0] === 1'b1 && a_width > b_width) || seq == 2'b10) begin + if (a_width >= width) + task_ram_col (webweu_tmp[0], weawel_tmp[0], diadi_tmp[7:0], dipadip_tmp[0], mem[addrawraddr_tmp[14:4]][0 +: 8], memp[addrawraddr_tmp[14:4]][0]); + else + task_ram_col (webweu_tmp[0], weawel_tmp[0], diadi_tmp[7:0], dipadip_tmp[0], mem[addrawraddr_tmp[14:addrawraddr_bit_16+1]][(addrawraddr_tmp[addrawraddr_bit_16:4] * 16) +: 8], memp[addrawraddr_tmp[14:addrawraddr_bit_16+1]][(addrawraddr_tmp[addrawraddr_bit_16:4] * 2) +: 1]); + + if (seq == 2'b00) + chk_for_col_msg (weawel_tmp[0], webweu_tmp[0], addrawraddr_tmp, addrbrdaddr_tmp); + + if (a_width >= width) + task_ram_col (webweu_tmp[1], weawel_tmp[1], diadi_tmp[15:8], dipadip_tmp[1], mem[addrawraddr_tmp[14:4]][8 +: 8], memp[addrawraddr_tmp[14:4]][1]); + else + task_ram_col (webweu_tmp[1], weawel_tmp[1], diadi_tmp[15:8], dipadip_tmp[1], mem[addrawraddr_tmp[14:addrawraddr_bit_16+1]][((addrawraddr_tmp[addrawraddr_bit_16:4] * 16) + 8) +: 8], memp[addrawraddr_tmp[14:addrawraddr_bit_16+1]][((addrawraddr_tmp[addrawraddr_bit_16:4] * 2) + 1) +: 1]); + + if (seq == 2'b00) + chk_for_col_msg (weawel_tmp[1], webweu_tmp[1], addrawraddr_tmp, addrbrdaddr_tmp); + + end // if (a_width <= b_width) + end // case: 16 + 32 : begin + if (!(weawel_tmp[0] === 1'b1 && webweu_tmp[0] === 1'b1 && a_width > b_width) || seq == 2'b10) begin + task_ram_col (webweu_tmp[0], weawel_tmp[0], diadi_tmp[7:0], dipadip_tmp[0], mem[addrawraddr_tmp[14:5]][0 +: 8], memp[addrawraddr_tmp[14:5]][0]); + if (seq == 2'b00) + chk_for_col_msg (weawel_tmp[0], webweu_tmp[0], addrawraddr_tmp, addrbrdaddr_tmp); + + task_ram_col (webweu_tmp[1], weawel_tmp[1], diadi_tmp[15:8], dipadip_tmp[1], mem[addrawraddr_tmp[14:5]][8 +: 8], memp[addrawraddr_tmp[14:5]][1]); + if (seq == 2'b00) + chk_for_col_msg (weawel_tmp[1], webweu_tmp[1], addrawraddr_tmp, addrbrdaddr_tmp); + + task_ram_col (webweu_tmp[2], weawel_tmp[2], diadi_tmp[23:16], dipadip_tmp[2], mem[addrawraddr_tmp[14:5]][16 +: 8], memp[addrawraddr_tmp[14:5]][2]); + if (seq == 2'b00) + chk_for_col_msg (weawel_tmp[2], webweu_tmp[2], addrawraddr_tmp, addrbrdaddr_tmp); + + task_ram_col (webweu_tmp[3], weawel_tmp[3], diadi_tmp[31:24], dipadip_tmp[3], mem[addrawraddr_tmp[14:5]][24 +: 8], memp[addrawraddr_tmp[14:5]][3]); + if (seq == 2'b00) + chk_for_col_msg (weawel_tmp[3], webweu_tmp[3], addrawraddr_tmp, addrbrdaddr_tmp); + + end // if (a_width <= b_width) + end // case: 32 + + endcase // case(a_width) + + end + + endtask // task_col_wr_ram_a + + + task task_col_wr_ram_b; + + input [1:0] seq; + input [7:0] weawel_tmp; + input [7:0] webweu_tmp; + input [63:0] dibdi_tmp; + input [7:0] dipbdip_tmp; + input [15:0] addrawraddr_tmp; + input [15:0] addrbrdaddr_tmp; + + begin + + case (b_width) + + 1, 2, 4 : begin + if (!(weawel_tmp[0] === 1'b1 && webweu_tmp[0] === 1'b1 && b_width > a_width) || seq == 2'b10) begin + if (b_width >= width) + task_ram_col (weawel_tmp[0], webweu_tmp[0], dibdi_tmp[b_width-1:0], 1'b0, mem[addrbrdaddr_tmp[14:addrbrdaddr_lbit_124]], tmp1); + else + task_ram_col (weawel_tmp[0], webweu_tmp[0], dibdi_tmp[b_width-1:0], 1'b0, mem[addrbrdaddr_tmp[14:addrbrdaddr_bit_124+1]][(addrbrdaddr_tmp[addrbrdaddr_bit_124:addrbrdaddr_lbit_124] * b_width) +: b_width], tmp1); + + if (seq == 2'b00) + chk_for_col_msg (weawel_tmp[0], webweu_tmp[0], addrawraddr_tmp, addrbrdaddr_tmp); + + end // if (b_width <= a_width) + end // case: 1, 2, 4 + 8 : begin + if (!(weawel_tmp[0] === 1'b1 && webweu_tmp[0] === 1'b1 && b_width > a_width) || seq == 2'b10) begin + if (b_width >= width) + task_ram_col (weawel_tmp[0], webweu_tmp[0], dibdi_tmp[7:0], dipbdip_tmp[0], mem[addrbrdaddr_tmp[14:3]], memp[addrbrdaddr_tmp[14:3]]); + else + task_ram_col (weawel_tmp[0], webweu_tmp[0], dibdi_tmp[7:0], dipbdip_tmp[0], mem[addrbrdaddr_tmp[14:addrbrdaddr_bit_8+1]][(addrbrdaddr_tmp[addrbrdaddr_bit_8:3] * 8) +: 8], memp[addrbrdaddr_tmp[14:addrbrdaddr_bit_8+1]][(addrbrdaddr_tmp[addrbrdaddr_bit_8:3] * 1) +: 1]); + + if (seq == 2'b00) + chk_for_col_msg (weawel_tmp[0], webweu_tmp[0], addrawraddr_tmp, addrbrdaddr_tmp); + + end // if (b_width <= a_width) + end // case: 8 + 16 : begin + if (!(weawel_tmp[0] === 1'b1 && webweu_tmp[0] === 1'b1 && b_width > a_width) || seq == 2'b10) begin + if (b_width >= width) + task_ram_col (weawel_tmp[0], webweu_tmp[0], dibdi_tmp[7:0], dipbdip_tmp[0], mem[addrbrdaddr_tmp[14:4]][0 +: 8], memp[addrbrdaddr_tmp[14:4]][0:0]); + else + task_ram_col (weawel_tmp[0], webweu_tmp[0], dibdi_tmp[7:0], dipbdip_tmp[0], mem[addrbrdaddr_tmp[14:addrbrdaddr_bit_16+1]][(addrbrdaddr_tmp[addrbrdaddr_bit_16:4] * 16) +: 8], memp[addrbrdaddr_tmp[14:addrbrdaddr_bit_16+1]][(addrbrdaddr_tmp[addrbrdaddr_bit_16:4] * 2) +: 1]); + + if (seq == 2'b00) + chk_for_col_msg (weawel_tmp[0], webweu_tmp[0], addrawraddr_tmp, addrbrdaddr_tmp); + + + if (b_width >= width) + task_ram_col (weawel_tmp[1], webweu_tmp[1], dibdi_tmp[15:8], dipbdip_tmp[1], mem[addrbrdaddr_tmp[14:4]][8 +: 8], memp[addrbrdaddr_tmp[14:4]][1:1]); + else + task_ram_col (weawel_tmp[1], webweu_tmp[1], dibdi_tmp[15:8], dipbdip_tmp[1], mem[addrbrdaddr_tmp[14:addrbrdaddr_bit_16+1]][((addrbrdaddr_tmp[addrbrdaddr_bit_16:4] * 16) + 8) +: 8], memp[addrbrdaddr_tmp[14:addrbrdaddr_bit_16+1]][((addrbrdaddr_tmp[addrbrdaddr_bit_16:4] * 2) + 1) +: 1]); + + if (seq == 2'b00) + chk_for_col_msg (weawel_tmp[1], webweu_tmp[1], addrawraddr_tmp, addrbrdaddr_tmp); + + end // if (!(weawel_tmp[0] === 1'b1 && webweu_tmp[0] === 1'b1 && b_width > a_width) || seq == 2'b10) + end // case: 16 + 32 : begin + if (!(weawel_tmp[0] === 1'b1 && webweu_tmp[0] === 1'b1 && b_width > a_width) || seq == 2'b10) begin + task_ram_col (weawel_tmp[0], webweu_tmp[0], dibdi_tmp[7:0], dipbdip_tmp[0], mem[addrbrdaddr_tmp[14:5]][0 +: 8], memp[addrbrdaddr_tmp[14:5]][0:0]); + if (seq == 2'b00) + chk_for_col_msg (weawel_tmp[0], webweu_tmp[0], addrawraddr_tmp, addrbrdaddr_tmp); + + task_ram_col (weawel_tmp[1], webweu_tmp[1], dibdi_tmp[15:8], dipbdip_tmp[1], mem[addrbrdaddr_tmp[14:5]][8 +: 8], memp[addrbrdaddr_tmp[14:5]][1:1]); + if (seq == 2'b00) + chk_for_col_msg (weawel_tmp[1], webweu_tmp[1], addrawraddr_tmp, addrbrdaddr_tmp); + + task_ram_col (weawel_tmp[2], webweu_tmp[2], dibdi_tmp[23:16], dipbdip_tmp[2], mem[addrbrdaddr_tmp[14:5]][16 +: 8], memp[addrbrdaddr_tmp[14:5]][2:2]); + if (seq == 2'b00) + chk_for_col_msg (weawel_tmp[2], webweu_tmp[2], addrawraddr_tmp, addrbrdaddr_tmp); + + task_ram_col (weawel_tmp[3], webweu_tmp[3], dibdi_tmp[31:24], dipbdip_tmp[3], mem[addrbrdaddr_tmp[14:5]][24 +: 8], memp[addrbrdaddr_tmp[14:5]][3:3]); + if (seq == 2'b00) + chk_for_col_msg (weawel_tmp[3], webweu_tmp[3], addrawraddr_tmp, addrbrdaddr_tmp); + + end // if (b_width <= a_width) + end // case: 32 + + endcase // case(b_width) + + end + + endtask // task_col_wr_ram_b + + + task task_wr_ram_a; + + input [7:0] weawel_tmp; + input [63:0] diadi_tmp; + input [7:0] dipadip_tmp; + input [15:0] addrawraddr_tmp; + + begin + + case (a_width) + + 1, 2, 4 : begin + + if (a_width >= width) + task_ram (weawel_tmp[0], diadi_tmp[a_width-1:0], 1'b0, mem[addrawraddr_tmp[14:addrawraddr_lbit_124]], tmp1); + else + task_ram (weawel_tmp[0], diadi_tmp[a_width-1:0], 1'b0, mem[addrawraddr_tmp[14:addrawraddr_bit_124+1]][(addrawraddr_tmp[addrawraddr_bit_124:addrawraddr_lbit_124] * a_width) +: a_width], tmp1); + + end + 8 : begin + + if (a_width >= width) + task_ram (weawel_tmp[0], diadi_tmp[7:0], dipadip_tmp[0], mem[addrawraddr_tmp[14:3]], memp[addrawraddr_tmp[14:3]]); + else + task_ram (weawel_tmp[0], diadi_tmp[7:0], dipadip_tmp[0], mem[addrawraddr_tmp[14:addrawraddr_bit_8+1]][(addrawraddr_tmp[addrawraddr_bit_8:3] * 8) +: 8], memp[addrawraddr_tmp[14:addrawraddr_bit_8+1]][(addrawraddr_tmp[addrawraddr_bit_8:3] * 1) +: 1]); + + end + 16 : begin + + if (a_width >= width) begin + task_ram (weawel_tmp[0], diadi_tmp[7:0], dipadip_tmp[0], mem[addrawraddr_tmp[14:4]][0 +: 8], memp[addrawraddr_tmp[14:4]][0:0]); + task_ram (weawel_tmp[1], diadi_tmp[15:8], dipadip_tmp[1], mem[addrawraddr_tmp[14:4]][8 +: 8], memp[addrawraddr_tmp[14:4]][1:1]); + end + else begin + task_ram (weawel_tmp[0], diadi_tmp[7:0], dipadip_tmp[0], mem[addrawraddr_tmp[14:addrawraddr_bit_16+1]][(addrawraddr_tmp[addrawraddr_bit_16:4] * 16) +: 8], memp[addrawraddr_tmp[14:addrawraddr_bit_16+1]][(addrawraddr_tmp[addrawraddr_bit_16:4] * 2) +: 1]); + task_ram (weawel_tmp[1], diadi_tmp[15:8], dipadip_tmp[1], mem[addrawraddr_tmp[14:addrawraddr_bit_16+1]][((addrawraddr_tmp[addrawraddr_bit_16:4] * 16) + 8) +: 8], memp[addrawraddr_tmp[14:addrawraddr_bit_16+1]][((addrawraddr_tmp[addrawraddr_bit_16:4] * 2) + 1) +: 1]); + end // else: !if(a_width >= b_width) + + end // case: 16 + 32 : begin + + task_ram (weawel_tmp[0], diadi_tmp[7:0], dipadip_tmp[0], mem[addrawraddr_tmp[14:5]][0 +: 8], memp[addrawraddr_tmp[14:5]][0:0]); + task_ram (weawel_tmp[1], diadi_tmp[15:8], dipadip_tmp[1], mem[addrawraddr_tmp[14:5]][8 +: 8], memp[addrawraddr_tmp[14:5]][1:1]); + task_ram (weawel_tmp[2], diadi_tmp[23:16], dipadip_tmp[2], mem[addrawraddr_tmp[14:5]][16 +: 8], memp[addrawraddr_tmp[14:5]][2:2]); + task_ram (weawel_tmp[3], diadi_tmp[31:24], dipadip_tmp[3], mem[addrawraddr_tmp[14:5]][24 +: 8], memp[addrawraddr_tmp[14:5]][3:3]); + + end // case: 32 + endcase // case(a_width) + end + + endtask // task_wr_ram_a + + + task task_wr_ram_b; + + input [7:0] webweu_tmp; + input [63:0] dibdi_tmp; + input [7:0] dipbdip_tmp; + input [15:0] addrbrdaddr_tmp; + + begin + + case (b_width) + + 1, 2, 4 : begin + + if (b_width >= width) + task_ram (webweu_tmp[0], dibdi_tmp[b_width-1:0], 1'b0, mem[addrbrdaddr_tmp[14:addrbrdaddr_lbit_124]], tmp1); + else + task_ram (webweu_tmp[0], dibdi_tmp[b_width-1:0], 1'b0, mem[addrbrdaddr_tmp[14:addrbrdaddr_bit_124+1]][(addrbrdaddr_tmp[addrbrdaddr_bit_124:addrbrdaddr_lbit_124] * b_width) +: b_width], tmp1); + end + 8 : begin + + if (b_width >= width) + task_ram (webweu_tmp[0], dibdi_tmp[7:0], dipbdip_tmp[0], mem[addrbrdaddr_tmp[14:3]], memp[addrbrdaddr_tmp[14:3]]); + else + task_ram (webweu_tmp[0], dibdi_tmp[7:0], dipbdip_tmp[0], mem[addrbrdaddr_tmp[14:addrbrdaddr_bit_8+1]][(addrbrdaddr_tmp[addrbrdaddr_bit_8:3] * 8) +: 8], memp[addrbrdaddr_tmp[14:addrbrdaddr_bit_8+1]][(addrbrdaddr_tmp[addrbrdaddr_bit_8:3] * 1) +: 1]); + + end + 16 : begin + + if (b_width >= width) begin + task_ram (webweu_tmp[0], dibdi_tmp[7:0], dipbdip_tmp[0], mem[addrbrdaddr_tmp[14:4]][0 +: 8], memp[addrbrdaddr_tmp[14:4]][0:0]); + task_ram (webweu_tmp[1], dibdi_tmp[15:8], dipbdip_tmp[1], mem[addrbrdaddr_tmp[14:4]][8 +: 8], memp[addrbrdaddr_tmp[14:4]][1:1]); + end + else begin + task_ram (webweu_tmp[0], dibdi_tmp[7:0], dipbdip_tmp[0], mem[addrbrdaddr_tmp[14:addrbrdaddr_bit_16+1]][(addrbrdaddr_tmp[addrbrdaddr_bit_16:4] * 16) +: 8], memp[addrbrdaddr_tmp[14:addrbrdaddr_bit_16+1]][(addrbrdaddr_tmp[addrbrdaddr_bit_16:4] * 2) +: 1]); + task_ram (webweu_tmp[1], dibdi_tmp[15:8], dipbdip_tmp[1], mem[addrbrdaddr_tmp[14:addrbrdaddr_bit_16+1]][((addrbrdaddr_tmp[addrbrdaddr_bit_16:4] * 16) + 8) +: 8], memp[addrbrdaddr_tmp[14:addrbrdaddr_bit_16+1]][((addrbrdaddr_tmp[addrbrdaddr_bit_16:4] * 2) + 1) +: 1]); + end + + end // case: 16 + 32 : begin + + task_ram (webweu_tmp[0], dibdi_tmp[7:0], dipbdip_tmp[0], mem[addrbrdaddr_tmp[14:5]][0 +: 8], memp[addrbrdaddr_tmp[14:5]][0:0]); + task_ram (webweu_tmp[1], dibdi_tmp[15:8], dipbdip_tmp[1], mem[addrbrdaddr_tmp[14:5]][8 +: 8], memp[addrbrdaddr_tmp[14:5]][1:1]); + task_ram (webweu_tmp[2], dibdi_tmp[23:16], dipbdip_tmp[2], mem[addrbrdaddr_tmp[14:5]][16 +: 8], memp[addrbrdaddr_tmp[14:5]][2:2]); + task_ram (webweu_tmp[3], dibdi_tmp[31:24], dipbdip_tmp[3], mem[addrbrdaddr_tmp[14:5]][24 +: 8], memp[addrbrdaddr_tmp[14:5]][3:3]); + + end // case: 32 + endcase // case(b_width) + end + + endtask // task_wr_ram_b + + + task task_col_rd_ram_a; + + input [1:0] seq; // 1 is bypass + input [7:0] webweu_tmp; + input [7:0] weawel_tmp; + input [15:0] addrawraddr_tmp; + inout [63:0] doado_tmp; + inout [7:0] dopadop_tmp; + reg [63:0] doado_ltmp; + reg [7:0] dopadop_ltmp; + + begin + + doado_ltmp= 64'b0; + dopadop_ltmp= 8'b0; + + case (a_width) + 1, 2, 4 : begin + + if ((webweu_tmp[0] === 1'b1 && weawel_tmp[0] === 1'b1) || (seq == 2'b01 && webweu_tmp[0] === 1'b1 && weawel_tmp[0] === 1'b0 && viol_type == 2'b10) || (seq == 2'b01 && wr_mode_a != 2'b01 && wr_mode_b != 2'b01) || (seq == 2'b01 && wr_mode_a == 2'b01 && wr_mode_b != 2'b01 && webweu_tmp[0] === 1'b1) || (seq == 2'b11 && wr_mode_a == 2'b00 && webweu_tmp[0] !== 1'b1)) begin + if (a_width >= width) + doado_ltmp = mem[addrawraddr_tmp[14:addrawraddr_lbit_124]]; + else + doado_ltmp = mem[addrawraddr_tmp[14:addrawraddr_bit_124+1]][(addrawraddr_tmp[addrawraddr_bit_124:addrawraddr_lbit_124] * a_width) +: a_width]; + task_x_buf (wr_mode_a, 3, 0, 0, doado_ltmp, doado_tmp, dopadop_ltmp, dopadop_tmp); + end + end // case: 1, 2, 4 + 8 : begin + + if ((webweu_tmp[0] === 1'b1 && weawel_tmp[0] === 1'b1) || (seq == 2'b01 && webweu_tmp[0] === 1'b1 && weawel_tmp[0] === 1'b0 && viol_type == 2'b10) || (seq == 2'b01 && wr_mode_a != 2'b01 && wr_mode_b != 2'b01) || (seq == 2'b01 && wr_mode_a == 2'b01 && wr_mode_b != 2'b01 && webweu_tmp[0] === 1'b1) || (seq == 2'b11 && wr_mode_a == 2'b00 && webweu_tmp[0] !== 1'b1)) begin + if (a_width >= width) begin + doado_ltmp = mem[addrawraddr_tmp[14:3]]; + dopadop_ltmp = memp[addrawraddr_tmp[14:3]]; + end + else begin + doado_ltmp = mem[addrawraddr_tmp[14:addrawraddr_bit_8+1]][(addrawraddr_tmp[addrawraddr_bit_8:3] * 8) +: 8]; + dopadop_ltmp = memp[addrawraddr_tmp[14:addrawraddr_bit_8+1]][(addrawraddr_tmp[addrawraddr_bit_8:3] * 1) +: 1]; + end + + task_x_buf (wr_mode_a, 7, 0, 0, doado_ltmp, doado_tmp, dopadop_ltmp, dopadop_tmp); + + end + end // case: 8 + 16 : begin + + if ((webweu_tmp[0] === 1'b1 && weawel_tmp[0] === 1'b1) || (seq == 2'b01 && webweu_tmp[0] === 1'b1 && weawel_tmp[0] === 1'b0 && viol_type == 2'b10) || (seq == 2'b01 && wr_mode_a != 2'b01 && wr_mode_b != 2'b01) || (seq == 2'b01 && wr_mode_a == 2'b01 && wr_mode_b != 2'b01 && webweu_tmp[0] === 1'b1) || (seq == 2'b11 && wr_mode_a == 2'b00 && webweu_tmp[0] !== 1'b1)) begin + if (a_width >= width) begin + doado_ltmp[7:0] = mem[addrawraddr_tmp[14:4]][7:0]; + dopadop_ltmp[0:0] = memp[addrawraddr_tmp[14:4]][0:0]; + end + else begin + doado_ltmp[7:0] = mem[addrawraddr_tmp[14:addrawraddr_bit_16+1]][(addrawraddr_tmp[addrawraddr_bit_16:4] * 16) +: 8]; + dopadop_ltmp[0:0] = memp[addrawraddr_tmp[14:addrawraddr_bit_16+1]][(addrawraddr_tmp[addrawraddr_bit_16:4] * 2) +: 1]; + end + task_x_buf (wr_mode_a, 7, 0, 0, doado_ltmp, doado_tmp, dopadop_ltmp, dopadop_tmp); + end + + if ((webweu_tmp[1] === 1'b1 && weawel_tmp[1] === 1'b1) || (seq == 2'b01 && webweu_tmp[1] === 1'b1 && weawel_tmp[1] === 1'b0 && viol_type == 2'b10) || (seq == 2'b01 && wr_mode_a != 2'b01 && wr_mode_b != 2'b01) || (seq == 2'b01 && wr_mode_a == 2'b01 && wr_mode_b != 2'b01 && webweu_tmp[1] === 1'b1) || (seq == 2'b11 && wr_mode_a == 2'b00 && webweu_tmp[1] !== 1'b1)) begin + if (a_width >= width) begin + doado_ltmp[15:8] = mem[addrawraddr_tmp[14:4]][15:8]; + dopadop_ltmp[1:1] = memp[addrawraddr_tmp[14:4]][1:1]; + end + else begin + doado_ltmp[15:8] = mem[addrawraddr_tmp[14:addrawraddr_bit_16+1]][((addrawraddr_tmp[addrawraddr_bit_16:4] * 16) + 8) +: 8]; + dopadop_ltmp[1:1] = memp[addrawraddr_tmp[14:addrawraddr_bit_16+1]][((addrawraddr_tmp[addrawraddr_bit_16:4] * 2) + 1) +: 1]; + end + task_x_buf (wr_mode_a, 15, 8, 1, doado_ltmp, doado_tmp, dopadop_ltmp, dopadop_tmp); + end + + end + 32 : begin + if (a_width >= width) begin + + if ((webweu_tmp[0] === 1'b1 && weawel_tmp[0] === 1'b1) || (seq == 2'b01 && webweu_tmp[0] === 1'b1 && weawel_tmp[0] === 1'b0 && viol_type == 2'b10) || (seq == 2'b01 && wr_mode_a != 2'b01 && wr_mode_b != 2'b01) || (seq == 2'b01 && wr_mode_a == 2'b01 && wr_mode_b != 2'b01 && webweu_tmp[0] === 1'b1) || (seq == 2'b11 && wr_mode_a == 2'b00 && webweu_tmp[0] !== 1'b1)) begin + doado_ltmp[7:0] = mem[addrawraddr_tmp[14:5]][7:0]; + dopadop_ltmp[0:0] = memp[addrawraddr_tmp[14:5]][0:0]; + task_x_buf (wr_mode_a, 7, 0, 0, doado_ltmp, doado_tmp, dopadop_ltmp, dopadop_tmp); + end + + if ((webweu_tmp[1] === 1'b1 && weawel_tmp[1] === 1'b1) || (seq == 2'b01 && webweu_tmp[1] === 1'b1 && weawel_tmp[1] === 1'b0 && viol_type == 2'b10) || (seq == 2'b01 && wr_mode_a != 2'b01 && wr_mode_b != 2'b01) || (seq == 2'b01 && wr_mode_a == 2'b01 && wr_mode_b != 2'b01 && webweu_tmp[1] === 1'b1) || (seq == 2'b11 && wr_mode_a == 2'b00 && webweu_tmp[1] !== 1'b1)) begin + doado_ltmp[15:8] = mem[addrawraddr_tmp[14:5]][15:8]; + dopadop_ltmp[1:1] = memp[addrawraddr_tmp[14:5]][1:1]; + task_x_buf (wr_mode_a, 15, 8, 1, doado_ltmp, doado_tmp, dopadop_ltmp, dopadop_tmp); + end + + if ((webweu_tmp[2] === 1'b1 && weawel_tmp[2] === 1'b1) || (seq == 2'b01 && webweu_tmp[2] === 1'b1 && weawel_tmp[2] === 1'b0 && viol_type == 2'b10) || (seq == 2'b01 && wr_mode_a != 2'b01 && wr_mode_b != 2'b01) || (seq == 2'b01 && wr_mode_a == 2'b01 && wr_mode_b != 2'b01 && webweu_tmp[2] === 1'b1) || (seq == 2'b11 && wr_mode_a == 2'b00 && webweu_tmp[2] !== 1'b1)) begin + doado_ltmp[23:16] = mem[addrawraddr_tmp[14:5]][23:16]; + dopadop_ltmp[2:2] = memp[addrawraddr_tmp[14:5]][2:2]; + task_x_buf (wr_mode_a, 23, 16, 2, doado_ltmp, doado_tmp, dopadop_ltmp, dopadop_tmp); + end + + if ((webweu_tmp[3] === 1'b1 && weawel_tmp[3] === 1'b1) || (seq == 2'b01 && webweu_tmp[3] === 1'b1 && weawel_tmp[3] === 1'b0 && viol_type == 2'b10) || (seq == 2'b01 && wr_mode_a != 2'b01 && wr_mode_b != 2'b01) || (seq == 2'b01 && wr_mode_a == 2'b01 && wr_mode_b != 2'b01 && webweu_tmp[3] === 1'b1) || (seq == 2'b11 && wr_mode_a == 2'b00 && webweu_tmp[3] !== 1'b1)) begin + doado_ltmp[31:24] = mem[addrawraddr_tmp[14:5]][31:24]; + dopadop_ltmp[3:3] = memp[addrawraddr_tmp[14:5]][3:3]; + task_x_buf (wr_mode_a, 31, 24, 3, doado_ltmp, doado_tmp, dopadop_ltmp, dopadop_tmp); + end + + end // if (a_width >= width) + end + + endcase // case(a_width) + end + endtask // task_col_rd_ram_a + + + task task_col_rd_ram_b; + + input [1:0] seq; // 1 is bypass + input [7:0] weawel_tmp; + input [7:0] webweu_tmp; + input [15:0] addrbrdaddr_tmp; + inout [63:0] dobdo_tmp; + inout [7:0] dopbdop_tmp; + reg [63:0] dobdo_ltmp; + reg [7:0] dopbdop_ltmp; + + begin + + dobdo_ltmp= 64'b0; + dopbdop_ltmp= 8'b0; + + case (b_width) + 1, 2, 4 : begin + + if ((webweu_tmp[0] === 1'b1 && weawel_tmp[0] === 1'b1) || (seq == 2'b01 && weawel_tmp[0] === 1'b1 && webweu_tmp[0] === 1'b0 && viol_type == 2'b11) || (seq == 2'b01 && wr_mode_b != 2'b01 && wr_mode_a != 2'b01) || (seq == 2'b01 && wr_mode_b == 2'b01 && wr_mode_a != 2'b01 && weawel_tmp[0] === 1'b1) || (seq == 2'b11 && wr_mode_b == 2'b00 && weawel_tmp[0] !== 1'b1)) begin + if (b_width >= width) + dobdo_ltmp = mem[addrbrdaddr_tmp[14:addrbrdaddr_lbit_124]]; + else + dobdo_ltmp = mem[addrbrdaddr_tmp[14:addrbrdaddr_bit_124+1]][(addrbrdaddr_tmp[addrbrdaddr_bit_124:addrbrdaddr_lbit_124] * b_width) +: b_width]; + + task_x_buf (wr_mode_b, 3, 0, 0, dobdo_ltmp, dobdo_tmp, dopbdop_ltmp, dopbdop_tmp); + + end + end // case: 1, 2, 4 + 8 : begin + + if ((webweu_tmp[0] === 1'b1 && weawel_tmp[0] === 1'b1) || (seq == 2'b01 && weawel_tmp[0] === 1'b1 && webweu_tmp[0] === 1'b0 && viol_type == 2'b11) || (seq == 2'b01 && wr_mode_b != 2'b01 && wr_mode_a != 2'b01) || (seq == 2'b01 && wr_mode_b == 2'b01 && wr_mode_a != 2'b01 && weawel_tmp[0] === 1'b1) || (seq == 2'b11 && wr_mode_b == 2'b00 && weawel_tmp[0] !== 1'b1)) begin + + if (b_width >= width) begin + dobdo_ltmp = mem[addrbrdaddr_tmp[14:3]]; + dopbdop_ltmp = memp[addrbrdaddr_tmp[14:3]]; + end + else begin + dobdo_ltmp = mem[addrbrdaddr_tmp[14:addrbrdaddr_bit_8+1]][(addrbrdaddr_tmp[addrbrdaddr_bit_8:3] * 8) +: 8]; + dopbdop_ltmp = memp[addrbrdaddr_tmp[14:addrbrdaddr_bit_8+1]][(addrbrdaddr_tmp[addrbrdaddr_bit_8:3] * 1) +: 1]; + end + + task_x_buf (wr_mode_b, 7, 0, 0, dobdo_ltmp, dobdo_tmp, dopbdop_ltmp, dopbdop_tmp); + + end + end // case: 8 + 16 : begin + + if ((webweu_tmp[0] === 1'b1 && weawel_tmp[0] === 1'b1) || (seq == 2'b01 && weawel_tmp[0] === 1'b1 && webweu_tmp[0] === 1'b0 && viol_type == 2'b11) || (seq == 2'b01 && wr_mode_b != 2'b01 && wr_mode_a != 2'b01) || (seq == 2'b01 && wr_mode_b == 2'b01 && wr_mode_a != 2'b01 && weawel_tmp[0] === 1'b1) || (seq == 2'b11 && wr_mode_b == 2'b00 && weawel_tmp[0] !== 1'b1)) begin + if (b_width >= width) begin + dobdo_ltmp[7:0] = mem[addrbrdaddr_tmp[14:4]][7:0]; + dopbdop_ltmp[0:0] = memp[addrbrdaddr_tmp[14:4]][0:0]; + end + else begin + dobdo_ltmp[7:0] = mem[addrbrdaddr_tmp[14:addrbrdaddr_bit_16+1]][(addrbrdaddr_tmp[addrbrdaddr_bit_16:4] * 16) +: 8]; + dopbdop_ltmp[0:0] = memp[addrbrdaddr_tmp[14:addrbrdaddr_bit_16+1]][(addrbrdaddr_tmp[addrbrdaddr_bit_16:4] * 2) +: 1]; + end + task_x_buf (wr_mode_b, 7, 0, 0, dobdo_ltmp, dobdo_tmp, dopbdop_ltmp, dopbdop_tmp); + end + + + if ((webweu_tmp[1] === 1'b1 && weawel_tmp[1] === 1'b1) || (seq == 2'b01 && weawel_tmp[1] === 1'b1 && webweu_tmp[1] === 1'b0 && viol_type == 2'b11) || (seq == 2'b01 && wr_mode_b != 2'b01 && wr_mode_a != 2'b01) || (seq == 2'b01 && wr_mode_b == 2'b01 && wr_mode_a != 2'b01 && weawel_tmp[1] === 1'b1) || (seq == 2'b11 && wr_mode_b == 2'b00 && weawel_tmp[1] !== 1'b1)) begin + + if (b_width >= width) begin + dobdo_ltmp[15:8] = mem[addrbrdaddr_tmp[14:4]][15:8]; + dopbdop_ltmp[1:1] = memp[addrbrdaddr_tmp[14:4]][1:1]; + end + else begin + dobdo_ltmp[15:8] = mem[addrbrdaddr_tmp[14:addrbrdaddr_bit_16+1]][((addrbrdaddr_tmp[addrbrdaddr_bit_16:4] * 16) + 8) +: 8]; + dopbdop_ltmp[1:1] = memp[addrbrdaddr_tmp[14:addrbrdaddr_bit_16+1]][((addrbrdaddr_tmp[addrbrdaddr_bit_16:4] * 2) + 1) +: 1]; + end + task_x_buf (wr_mode_b, 15, 8, 1, dobdo_ltmp, dobdo_tmp, dopbdop_ltmp, dopbdop_tmp); + end + + end + 32 : begin + if (b_width >= width) begin + + if ((webweu_tmp[0] === 1'b1 && weawel_tmp[0] === 1'b1) || (seq == 2'b01 && weawel_tmp[0] === 1'b1 && webweu_tmp[0] === 1'b0 && viol_type == 2'b11) || (seq == 2'b01 && wr_mode_b != 2'b01 && wr_mode_a != 2'b01) || (seq == 2'b01 && wr_mode_b == 2'b01 && wr_mode_a != 2'b01 && weawel_tmp[0] === 1'b1) || (seq == 2'b11 && wr_mode_b == 2'b00 && weawel_tmp[0] !== 1'b1)) begin + dobdo_ltmp[7:0] = mem[addrbrdaddr_tmp[14:5]][7:0]; + dopbdop_ltmp[0:0] = memp[addrbrdaddr_tmp[14:5]][0:0]; + task_x_buf (wr_mode_b, 7, 0, 0, dobdo_ltmp, dobdo_tmp, dopbdop_ltmp, dopbdop_tmp); + end + + if ((webweu_tmp[1] === 1'b1 && weawel_tmp[1] === 1'b1) || (seq == 2'b01 && weawel_tmp[1] === 1'b1 && webweu_tmp[1] === 1'b0 && viol_type == 2'b11) || (seq == 2'b01 && wr_mode_b != 2'b01 && wr_mode_a != 2'b01) || (seq == 2'b01 && wr_mode_b == 2'b01 && wr_mode_a != 2'b01 && weawel_tmp[1] === 1'b1) || (seq == 2'b11 && wr_mode_b == 2'b00 && weawel_tmp[1] !== 1'b1)) begin + dobdo_ltmp[15:8] = mem[addrbrdaddr_tmp[14:5]][15:8]; + dopbdop_ltmp[1:1] = memp[addrbrdaddr_tmp[14:5]][1:1]; + task_x_buf (wr_mode_b, 15, 8, 1, dobdo_ltmp, dobdo_tmp, dopbdop_ltmp, dopbdop_tmp); + end + + if ((webweu_tmp[2] === 1'b1 && weawel_tmp[2] === 1'b1) || (seq == 2'b01 && weawel_tmp[2] === 1'b1 && webweu_tmp[2] === 1'b0 && viol_type == 2'b11) || (seq == 2'b01 && wr_mode_b != 2'b01 && wr_mode_a != 2'b01) || (seq == 2'b01 && wr_mode_b == 2'b01 && wr_mode_a != 2'b01 && weawel_tmp[2] === 1'b1) || (seq == 2'b11 && wr_mode_b == 2'b00 && weawel_tmp[2] !== 1'b1)) begin + dobdo_ltmp[23:16] = mem[addrbrdaddr_tmp[14:5]][23:16]; + dopbdop_ltmp[2:2] = memp[addrbrdaddr_tmp[14:5]][2:2]; + task_x_buf (wr_mode_b, 23, 16, 2, dobdo_ltmp, dobdo_tmp, dopbdop_ltmp, dopbdop_tmp); + end + + if ((webweu_tmp[3] === 1'b1 && weawel_tmp[3] === 1'b1) || (seq == 2'b01 && weawel_tmp[3] === 1'b1 && webweu_tmp[3] === 1'b0 && viol_type == 2'b11) || (seq == 2'b01 && wr_mode_b != 2'b01 && wr_mode_a != 2'b01) || (seq == 2'b01 && wr_mode_b == 2'b01 && wr_mode_a != 2'b01 && weawel_tmp[3] === 1'b1) || (seq == 2'b11 && wr_mode_b == 2'b00 && weawel_tmp[3] !== 1'b1)) begin + dobdo_ltmp[31:24] = mem[addrbrdaddr_tmp[14:5]][31:24]; + dopbdop_ltmp[3:3] = memp[addrbrdaddr_tmp[14:5]][3:3]; + task_x_buf (wr_mode_b, 31, 24, 3, dobdo_ltmp, dobdo_tmp, dopbdop_ltmp, dopbdop_tmp); + end + + end // if (b_width >= width) + end + + endcase // case(b_width) + end + endtask // task_col_rd_ram_b + + + task task_rd_ram_a; + + input [15:0] addrawraddr_tmp; + inout [63:0] doado_tmp; + inout [7:0] dopadop_tmp; + + begin + + case (a_width) + 1, 2, 4 : begin + if (a_width >= width) + doado_tmp = mem[addrawraddr_tmp[14:addrawraddr_lbit_124]]; + + else + doado_tmp = mem[addrawraddr_tmp[14:addrawraddr_bit_124+1]][(addrawraddr_tmp[addrawraddr_bit_124:addrawraddr_lbit_124] * a_width) +: a_width]; + end + 8 : begin + if (a_width >= width) begin + doado_tmp = mem[addrawraddr_tmp[14:3]]; + dopadop_tmp = memp[addrawraddr_tmp[14:3]]; + end + else begin + doado_tmp = mem[addrawraddr_tmp[14:addrawraddr_bit_8+1]][(addrawraddr_tmp[addrawraddr_bit_8:3] * 8) +: 8]; + dopadop_tmp = memp[addrawraddr_tmp[14:addrawraddr_bit_8+1]][(addrawraddr_tmp[addrawraddr_bit_8:3] * 1) +: 1]; + end + end + 16 : begin + if (a_width >= width) begin + doado_tmp = mem[addrawraddr_tmp[14:4]]; + dopadop_tmp = memp[addrawraddr_tmp[14:4]]; + end + else begin + doado_tmp = mem[addrawraddr_tmp[14:addrawraddr_bit_16+1]][(addrawraddr_tmp[addrawraddr_bit_16:4] * 16) +: 16]; + dopadop_tmp = memp[addrawraddr_tmp[14:addrawraddr_bit_16+1]][(addrawraddr_tmp[addrawraddr_bit_16:4] * 2) +: 2]; + end + end + 32 : begin + if (a_width >= width) begin + doado_tmp = mem[addrawraddr_tmp[14:5]]; + dopadop_tmp = memp[addrawraddr_tmp[14:5]]; + end + end + + endcase // case(a_width) + + end + endtask // task_rd_ram_a + + + task task_rd_ram_b; + + input [15:0] addrbrdaddr_tmp; + inout [31:0] dobdo_tmp; + inout [3:0] dopbdop_tmp; + + begin + + case (b_width) + 1, 2, 4 : begin + if (b_width >= width) + dobdo_tmp = mem[addrbrdaddr_tmp[14:addrbrdaddr_lbit_124]]; + else + dobdo_tmp = mem[addrbrdaddr_tmp[14:addrbrdaddr_bit_124+1]][(addrbrdaddr_tmp[addrbrdaddr_bit_124:addrbrdaddr_lbit_124] * b_width) +: b_width]; + end + 8 : begin + if (b_width >= width) begin + dobdo_tmp = mem[addrbrdaddr_tmp[14:3]]; + dopbdop_tmp = memp[addrbrdaddr_tmp[14:3]]; + end + else begin + dobdo_tmp = mem[addrbrdaddr_tmp[14:addrbrdaddr_bit_8+1]][(addrbrdaddr_tmp[addrbrdaddr_bit_8:3] * 8) +: 8]; + dopbdop_tmp = memp[addrbrdaddr_tmp[14:addrbrdaddr_bit_8+1]][(addrbrdaddr_tmp[addrbrdaddr_bit_8:3] * 1) +: 1]; + end + end + 16 : begin + if (b_width >= width) begin + dobdo_tmp = mem[addrbrdaddr_tmp[14:4]]; + dopbdop_tmp = memp[addrbrdaddr_tmp[14:4]]; + end + else begin + dobdo_tmp = mem[addrbrdaddr_tmp[14:addrbrdaddr_bit_16+1]][(addrbrdaddr_tmp[addrbrdaddr_bit_16:4] * 16) +: 16]; + dopbdop_tmp = memp[addrbrdaddr_tmp[14:addrbrdaddr_bit_16+1]][(addrbrdaddr_tmp[addrbrdaddr_bit_16:4] * 2) +: 2]; + end + end + 32 : begin + dobdo_tmp = mem[addrbrdaddr_tmp[14:5]]; + dopbdop_tmp = memp[addrbrdaddr_tmp[14:5]]; + end + + endcase + end + endtask // task_rd_ram_b + + + task chk_for_col_msg; + + input weawel_tmp; + input webweu_tmp; + input [15:0] addrawraddr_tmp; + input [15:0] addrbrdaddr_tmp; + + begin + + if ((SIM_COLLISION_CHECK == "ALL" || SIM_COLLISION_CHECK == "WARNING_ONLY") && !(((wr_mode_b == 2'b01 && webweu_tmp === 1'b1 && weawel_tmp === 1'b0) && viol_time == 1) || ((wr_mode_a == 2'b01 && weawel_tmp === 1'b1 && webweu_tmp === 1'b0) && viol_time == 1))) + + if (weawel_tmp === 1'b1 && webweu_tmp === 1'b1 && col_wr_wr_msg == 1) begin + $display("Memory Collision Error on RAMB8BWER : %m at simulation time %.3f ns.\nA write was requested to the same address simultaneously at both port A and port B of the RAM. The contents written to the RAM at address location %h (hex) of port A and address location %h (hex) of port B are unknown.", $time/1000.0, addrawraddr_tmp, addrbrdaddr_tmp); + col_wr_wr_msg = 0; + end + + else if (weawel_tmp === 1'b1 && webweu_tmp === 1'b0 && col_wra_rdb_msg == 1) begin + + if ((wr_mode_a == 2'b01 || wr_mode_b == 2'b01) && viol_time == 2) + $display("Memory Collision Error on RAMB8BWER : %m at simulation time %.3f ns.\nA read was performed on address %h (hex) of port B while a write was requested to the same address on port A. The write will be unsuccessful and the content of the RAM at address location %h (hex) of port A became unknown.", $time/1000.0, addrbrdaddr_tmp, addrawraddr_tmp); + else + $display("Memory Collision Error on RAMB8BWER : %m at simulation time %.3f ns.\nA read was performed on address %h (hex) of port B while a write was requested to the same address on port A. The write will be successful however the read value on port B is unknown until the next CLKBRDCLK cycle.", $time/1000.0, addrbrdaddr_tmp); + col_wra_rdb_msg = 0; + end + + else if (weawel_tmp === 1'b0 && webweu_tmp === 1'b1 && col_wrb_rda_msg == 1) begin + + if ((wr_mode_a == 2'b01 || wr_mode_b == 2'b01) && viol_time == 2) + $display("Memory Collision Error on RAMB8BWER : %m at simulation time %.3f ns.\nA read was performed on address %h (hex) of port A while a write was requested to the same address on port B. The write will be unsuccessful and the content of the RAM at address location %h (hex) of port B became unknown.", $time/1000.0, addrawraddr_tmp, addrbrdaddr_tmp); + else + $display("Memory Collision Error on RAMB8BWER : %m at simulation time %.3f ns.\nA read was performed on address %h (hex) of port A while a write was requested to the same address on port B. The write will be successful however the read value on port A is unknown until the next CLKAWRCLK cycle.", $time/1000.0, addrawraddr_tmp); + col_wrb_rda_msg = 0; + end + + end + + endtask // chk_for_col_msg + specify + + (CLKAWRCLK => DOADO[0]) = (100, 100); + (CLKAWRCLK => DOADO[1]) = (100, 100); + (CLKAWRCLK => DOADO[2]) = (100, 100); + (CLKAWRCLK => DOADO[3]) = (100, 100); + (CLKAWRCLK => DOADO[4]) = (100, 100); + (CLKAWRCLK => DOADO[5]) = (100, 100); + (CLKAWRCLK => DOADO[6]) = (100, 100); + (CLKAWRCLK => DOADO[7]) = (100, 100); + (CLKAWRCLK => DOADO[8]) = (100, 100); + (CLKAWRCLK => DOADO[9]) = (100, 100); + (CLKAWRCLK => DOADO[10]) = (100, 100); + (CLKAWRCLK => DOADO[11]) = (100, 100); + (CLKAWRCLK => DOADO[12]) = (100, 100); + (CLKAWRCLK => DOADO[13]) = (100, 100); + (CLKAWRCLK => DOADO[14]) = (100, 100); + (CLKAWRCLK => DOADO[15]) = (100, 100); + (CLKAWRCLK => DOPADOP[0]) = (100, 100); + (CLKAWRCLK => DOPADOP[1]) = (100, 100); + (CLKBRDCLK => DOBDO[0]) = (100, 100); + (CLKBRDCLK => DOBDO[1]) = (100, 100); + (CLKBRDCLK => DOBDO[2]) = (100, 100); + (CLKBRDCLK => DOBDO[3]) = (100, 100); + (CLKBRDCLK => DOBDO[4]) = (100, 100); + (CLKBRDCLK => DOBDO[5]) = (100, 100); + (CLKBRDCLK => DOBDO[6]) = (100, 100); + (CLKBRDCLK => DOBDO[7]) = (100, 100); + (CLKBRDCLK => DOBDO[8]) = (100, 100); + (CLKBRDCLK => DOBDO[9]) = (100, 100); + (CLKBRDCLK => DOBDO[10]) = (100, 100); + (CLKBRDCLK => DOBDO[11]) = (100, 100); + (CLKBRDCLK => DOBDO[12]) = (100, 100); + (CLKBRDCLK => DOBDO[13]) = (100, 100); + (CLKBRDCLK => DOBDO[14]) = (100, 100); + (CLKBRDCLK => DOBDO[15]) = (100, 100); + (CLKBRDCLK => DOPBDOP[0]) = (100, 100); + (CLKBRDCLK => DOPBDOP[1]) = (100, 100); + + specparam PATHPULSE$ = 0; + + endspecify + + +endmodule // RAMB8BWER diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/ROM128X1.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/ROM128X1.v new file mode 100644 index 0000000..f9e2928 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/ROM128X1.v @@ -0,0 +1,41 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/ROM128X1.v,v 1.9 2007/05/23 21:43:44 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / 128-Deep by 1-Wide ROM +// /___/ /\ Filename : ROM128X1.v +// \ \ / \ Timestamp : Thu Mar 25 16:43:39 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 02/04/05 - Rev 0.0.1 Remove input/output bufs; Remove for-loop in initial block; +// 05/23/07 - Changed timescale to 1 ps / 1 ps. + +`timescale 1 ps / 1 ps + + +module ROM128X1 (O, A0, A1, A2, A3, A4, A5, A6); + + parameter INIT = 128'h00000000000000000000000000000000; + + output O; + + input A0, A1, A2, A3, A4, A5, A6; + + reg [127:0] mem; + + initial + mem = INIT; + + assign O = mem[{A6, A5, A4, A3, A2, A1, A0}]; + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/ROM16X1.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/ROM16X1.v new file mode 100644 index 0000000..ec45469 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/ROM16X1.v @@ -0,0 +1,41 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/ROM16X1.v,v 1.9 2007/05/23 21:43:44 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / 16-Deep by 1-Wide ROM +// /___/ /\ Filename : ROM16X1.v +// \ \ / \ Timestamp : Thu Mar 25 16:43:39 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 02/04/05 - Rev 0.0.1 Remove input/output bufs; Remove for-loop in initial block; +// 05/23/07 - Changed timescale to 1 ps / 1 ps. + +`timescale 1 ps / 1 ps + + +module ROM16X1 (O, A0, A1, A2, A3); + + parameter INIT = 16'h0000; + + output O; + + input A0, A1, A2, A3; + + reg [15:0] mem; + + initial + mem = INIT; + + assign O = mem[{A3, A2, A1, A0}]; + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/ROM256X1.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/ROM256X1.v new file mode 100644 index 0000000..92d2d34 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/ROM256X1.v @@ -0,0 +1,41 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/ROM256X1.v,v 1.9 2007/05/23 21:43:44 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / 256-Deep by 1-Wide ROM +// /___/ /\ Filename : ROM256X1.v +// \ \ / \ Timestamp : Thu Mar 25 16:43:39 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 02/04/05 - Rev 0.0.1 Remove input/output bufs; Remove for-loop in initial block; +// 05/23/07 - Changed timescale to 1 ps / 1 ps. + +`timescale 1 ps / 1 ps + + +module ROM256X1 (O, A0, A1, A2, A3, A4, A5, A6, A7); + + parameter INIT = 256'h0000000000000000000000000000000000000000000000000000000000000000; + + output O; + + input A0, A1, A2, A3, A4, A5, A6, A7; + + reg [255:0] mem; + + initial + mem = INIT; + + assign O = mem[{A7, A6, A5, A4, A3, A2, A1, A0}]; + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/ROM32X1.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/ROM32X1.v new file mode 100644 index 0000000..813bcec --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/ROM32X1.v @@ -0,0 +1,41 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/ROM32X1.v,v 1.9 2007/05/23 21:43:44 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / 32-Deep by 1-Wide ROM +// /___/ /\ Filename : ROM32X1.v +// \ \ / \ Timestamp : Thu Mar 25 16:43:40 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 02/04/05 - Rev 0.0.1 Remove input/output bufs; Remove for-loop in initial block; +// 05/23/07 - Changed timescale to 1 ps / 1 ps. + +`timescale 1 ps / 1 ps + + +module ROM32X1 (O, A0, A1, A2, A3, A4); + + parameter INIT = 32'h00000000; + + output O; + + input A0, A1, A2, A3, A4; + + reg [31:0] mem; + + initial + mem = INIT; + + assign O = mem[{A4, A3, A2, A1, A0}]; + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/ROM64X1.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/ROM64X1.v new file mode 100644 index 0000000..923ac6f --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/ROM64X1.v @@ -0,0 +1,41 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/ROM64X1.v,v 1.9 2007/05/23 21:43:44 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / 64-Deep by 1-Wide ROM +// /___/ /\ Filename : ROM64X1.v +// \ \ / \ Timestamp : Thu Mar 25 16:43:40 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 02/04/05 - Rev 0.0.1 Remove input/output bufs; Remove for-loop in initial block; +// 05/23/07 - Changed timescale to 1 ps / 1 ps. + +`timescale 1 ps / 1 ps + + +module ROM64X1 (O, A0, A1, A2, A3, A4, A5); + + parameter INIT = 64'h0000000000000000; + + output O; + + input A0, A1, A2, A3, A4, A5; + + reg [63:0] mem; + + initial + mem = INIT; + + assign O = mem[{A5, A4, A3, A2, A1, A0}]; + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/SIM_CONFIG_S3A.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/SIM_CONFIG_S3A.v new file mode 100644 index 0000000..c970099 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/SIM_CONFIG_S3A.v @@ -0,0 +1,950 @@ +// Copyright (c) 1995/2005 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Function Simulation Library Component +// / / Configuration Simulation Model +// /___/ /\ Filename : SIM_CONFIG_S3A.v +// \ \ / \ Timestamp : +// \___\/\___\ +// +// Revision: +// 09/20/06 - Initial version of configuration simulation model for Spartan3A. +// 01/04/07 - Add downcont to skip type2 data. +// 01/05/07 - Add INITB output function. +// 01/15/07 - Modify GSR, GTS and GWE generation. +// 01/18/07 - Change startup state machine running after DESYNC command. +// 02/01/07 - PROGB low pulse less than 300 ns will not cause reset. +// 02/06/07 - Make INITB to open-drain output. +// 02/08/07 - Add power on reset por_b; +// 02/20/07 - Check ID when receive bit[15:0]. +// 02/27/07 - Compare bit31-4 of ID register. +// Add CRC calculation for Type 2 data. +// 03/01/07 - stop downcont when CS_b high. +// 03/06/07 - DONE delay startup sequence. +// 03/13/07 -Remove BUSY. +// 03/23/07 - Remove CRC reg from CRC calculation. +// 04/24/07 - Data valid for 4 cycles after RDWR high for readback. +// 04/25/07 - Add two cycle delay to readback to match hardware. +// 06/04/07 - Add wire declaration to internal signal. +// 06/19/07 - Add LOC parameter to simprim model (CR441956). +// End Revision +//////////////////////////////////////////////////////////////////////////////// + +`timescale 1 ps / 1 ps + +module SIM_CONFIG_S3A ( + CSOB, + DONE, + CCLK, + D, + DCMLOCK, + CSIB, + INITB, + M, + PROGB, + RDWRB + ); + + output CSOB; + inout DONE; + input CCLK; + input DCMLOCK; + input CSIB; + inout [7:0] D; + inout INITB; + input [2:0] M; + input PROGB; + input RDWRB; + + parameter DEVICE_ID = 32'h0; + + localparam cfg_Tprog = 300000; // min PROG must be low, 300 ns + localparam cfg_Tpl = 100000; // max program latency us. + localparam STARTUP_PH0 = 3'b000; + localparam STARTUP_PH1 = 3'b001; + localparam STARTUP_PH2 = 3'b010; + localparam STARTUP_PH3 = 3'b011; + localparam STARTUP_PH4 = 3'b100; + localparam STARTUP_PH5 = 3'b101; + localparam STARTUP_PH6 = 3'b110; + localparam STARTUP_PH7 = 3'b111; + + wire GSR, GTS, GWE; + wire cclk_in, csi_b_in, init_b_in, prog_b_in, rdwr_b_in; + wire crc_err_flag_tot; + reg crc_err_flag_reg = 0; + reg mode_sample_flag = 0; + reg init_b_p = 1; + reg done_o = 0; + tri1 p_up; + + triand (weak1, strong0) INITB=(mode_sample_flag) ? ~crc_err_flag_tot : init_b_p; + triand (weak1, strong0) DONE=done_o; + + assign DONE = p_up; + assign INITB = p_up; + + wire done_in; + reg por_b; + wire [2:0] m_in; + reg [2:0] mode_pin_in = 3'b0; + wire [7:0] d_in, d_out; + + assign glbl.GSR = GSR; + assign glbl.GTS = GTS; +// assign glbl.GWE = GWE; + wire csbo_b_out, dcm_locked ; + wire d_out_en, init_b_t, prog_b_t, crc_rst; + + buf buf_cso (CSOB, csbo_b_out); + buf buf_cclk (cclk_in, CCLK); + buf buf_dcm (dcm_locked, DCMLOCK); + buf buf_csi (csi_b_in, CSIB); + + buf buf_din[7:0] (d_in, D); + bufif1 buf_dout[7:0] (D, d_out, d_out_en); + + buf buf_init (init_b_in, INITB); + buf buf_m_0 (m_in[0], M[0]); + buf buf_m_1 (m_in[1], M[1]); + buf buf_m_2 (m_in[2], M[2]); + buf buf_prog (prog_b_in, PROGB); + buf buf_rw (rdwr_b_in, RDWRB); + + time prog_pulse_low_edge = 0; + time prog_pulse_low = 0; + integer wr_cnt = 0; + reg [4:0] conti_data_cnt = 5'b0; + reg [5:0] rd_data_cnt = 6'b0; + integer abort_cnt = 0; + reg [4:0] csbo_cnt = 0; + reg csbo_flag = 0; + reg [15:0] pack_in_reg = 16'b0; + reg [5:0] reg_addr; + reg [5:0] rd_reg_addr; + reg new_data_in_flag = 0; + reg wr_flag = 0; + reg rd_flag = 0; + reg cmd_wr_flag = 0; + reg cmd_rd_flag = 0; + reg bus_sync_flag = 0; + reg csi_sync = 0; + reg rd_sw_en = 0; + reg conti_data_flag = 0; + reg conti_data_flag_set = 0; + reg [2:0] st_state = STARTUP_PH0; + reg startup_begin_flag = 0; + reg startup_end_flag = 0; + reg cmd_reg_new_flag = 0; + reg far_maj_min_flag = 0; + reg crc_reset = 0; + reg crc_ck = 0; + reg crc_err_flag = 0; + wire crc_en, desync_flag; + reg [21:0] crc_curr = 22'b0; + reg [21:0] crc_new = 22'b0; + reg [21:0] crc_input = 22'b0; + reg gwe_out = 0; + reg gts_out = 1; + reg [7:0] d_o = 8'h0; + reg [7:0] outbus = 8'h0; + reg reboot_set = 0; + reg gsr_set = 0; + reg gts_usr_b = 1; + reg done_pin_drv = 0; + reg crc_bypass = 0; + reg reset_on_err = 0; + reg sync_timeout = 0; + reg [31:0] crc_reg, idcode_reg, idcode_tmp; + reg [15:0] far_maj_reg, far_min_reg, fdri_reg, fdro_reg; + reg [15:0] ctl_reg; + reg [4:0] cmd_reg; + reg [15:0] general1_reg; + reg [15:0] mask_reg, lout_reg, cor1_reg, cor2_reg, pwrdn_reg, flr_reg; + reg [15:0] snowplow_reg, hc_opt_reg, csbo_reg, general2_reg, mode_reg; + reg [15:0] pu_gwe_reg, pu_gts_reg, mfwr_reg, cclk_freq_reg, seu_opt_reg; + reg [31:0] exp_sign_reg, rdbk_sign_reg; + + reg shutdown_set = 0; + reg desynch_set = 0; + reg [2:0] done_cycle_reg = 3'b100, gts_cycle_reg = 3'b101, gwe_cycle_reg=3'b110; + reg [2:0] nx_st_state = 3'b000; + reg ghigh_b = 0; + reg eos_startup = 0; + reg startup_set = 0; + reg [1:0] startup_set_pulse = 2'b0; + reg abort_out_en; + reg [7:0] tmp_byte; + reg id_error_flag = 0; + reg iprog_b = 1; + reg abort_flag_wr = 0; + reg abort_flag_rd = 0; + reg [7:0] abort_status = 8'b0; + reg persist_en = 0; + reg rst_sync = 0; + reg abort_dis = 0; + reg [2:0] lock_cycle_reg = 3'b0; + reg rbcrc_no_pin = 0; + reg abort_flag_rst = 0; + reg gsr_st_out = 1; + reg gsr_cmd_out = 0; + reg d_o_en = 0; + wire [15:0] stat_reg; + wire rst_intl, rw_en, gsr_out; + wire cfgerr_b_flag; + wire abort_flag; + reg [27:0] downcont = 28'b0; + reg type2_flag = 0; + reg rst_en=1, prog_b_a=1; + + initial begin + if (DEVICE_ID == 32'h0) begin + $display("Attribute Error : The attribute DEVICE_ID on SIM_CONFIG_S3A instance %m is not set."); +// $finish; + end + end + + + assign GSR = gsr_out; + assign GTS = gts_out; + assign GWE = gwe_out; + assign csbo_b_out = (csbo_flag== 1) ? 0 : 1; + assign cfgerr_b_flag = rw_en & ~crc_err_flag_tot; + assign crc_err_flag_tot = id_error_flag | crc_err_flag_reg; + assign d_out = (abort_out_en ) ? abort_status : outbus; + assign d_out_en = d_o_en; + assign crc_en = 1; + assign done_in = DONE; + + + always @(abort_out_en or csi_b_in or rdwr_b_in or rd_flag) + if (abort_out_en) + d_o_en = 1; + else + d_o_en = rdwr_b_in & ~csi_b_in & rd_flag; + + assign init_b_t = init_b_in; + + always @( negedge prog_b_in) begin + rst_en = 0; + rst_en <= #cfg_Tprog 1; + end + + always @( posedge rst_en or posedge prog_b_in ) + if (rst_en) begin + if (prog_b_in == 0 ) + init_b_p <= 0; + else + init_b_p <= #(cfg_Tpl) 1; + end + + always @( rst_en or prog_b_in or prog_pulse_low) + if (rst_en) begin + if (prog_pulse_low==cfg_Tprog) begin + prog_b_a = 0; + prog_b_a <= #500 1; + end + else + prog_b_a = prog_b_in; + end + else + prog_b_a = 1; + + initial begin + por_b = 0; + por_b = #400000 1; + end + + assign prog_b_t = prog_b_a & iprog_b & por_b; + + assign rst_intl = (prog_b_t==0 ) ? 0 : 1; + + + always @(posedge init_b_t or negedge prog_b_t) + if (prog_b_t==0) + mode_sample_flag <= 0; + else if (init_b_t && mode_sample_flag == 0) begin + if (prog_b_t) begin + mode_pin_in <= m_in; + mode_sample_flag <= #1 1; + if (m_in != 3'b110) begin + $display("Error: input M is %h. Only Slave SelectMAP mode M=110 supported on SIM_CONFIG_S3A instance %m.", m_in); +// $finish; + end + end + else if ($time != 0) + $display("Error: PROGB is not high when INITB goes high on SIM_CONFIG_S3A instance %m at time %t.", $time); + end + + always @(m_in) + if (mode_sample_flag == 1 && persist_en == 1) + $display("Error : Mode pine M[2:0] changed after rising edge of INITB on SIM_CONFIG_S3A instance %m at time %t.", $time); + + always @(posedge prog_b_in or negedge prog_b_in) + if (prog_b_in ==0) + prog_pulse_low_edge <= $time; + else if (prog_b_in == 1 && $time > 0) begin + prog_pulse_low = $time - prog_pulse_low_edge; + if (prog_pulse_low < cfg_Tprog ) + $display("Error: Low time of PROGB is less than required minimum Tprogram time %d on SIM_CONFIG_S3A instance %m at time %t.", cfg_Tprog, $time); + end + + assign rw_en = (mode_sample_flag == 1 && csi_b_in ==0) ? 1 : 0; + assign desync_flag = ~rst_intl | desynch_set | crc_err_flag | id_error_flag; + + always @(posedge cclk_in) + csi_sync <= csi_b_in; + + always @(posedge cclk_in or negedge rdwr_b_in) + if (rdwr_b_in ==0) + rd_sw_en <= 0; + else begin + if (csi_sync == 1 && rdwr_b_in ==1) + rd_sw_en <= 1; + end + + always @(posedge cclk_in or posedge desync_flag) + if (desync_flag) begin + pack_in_reg <= 16'b0; + new_data_in_flag <= 0; + bus_sync_flag <= 0; + wr_cnt <= 0; + wr_flag <= 0; + rd_flag <= 0; + end + else begin + if (rw_en == 1 ) begin + if (rdwr_b_in == 0) begin + wr_flag <= 1; + rd_flag <= 0; + tmp_byte = bit_revers8(d_in[7:0]); + if (bus_sync_flag == 0) begin + if (pack_in_reg[7:0] == 8'hAA && tmp_byte == 8'h99) begin + bus_sync_flag <= 1; + new_data_in_flag <= 0; + wr_cnt <= 0; + end + else begin + pack_in_reg[7:0] <= tmp_byte; + end + end + else begin + if (wr_cnt == 0) begin + pack_in_reg[15:8] <= tmp_byte; + new_data_in_flag <= 0; + wr_cnt <= 1; + end + else if (wr_cnt == 1) begin + pack_in_reg[7:0] <= tmp_byte; + new_data_in_flag <= 1; + wr_cnt <= 0; + end + end + end + else begin //rdwr_b_in = 1 + wr_flag <= 0; + new_data_in_flag <= 0; + if (rd_sw_en ==1) + rd_flag <= 1; + end + end + else begin //rw_en = 0 + wr_flag <= 0; + rd_flag <= 0; + new_data_in_flag <= 0; + end + end + + always @(negedge cclk_in or negedge rst_intl) + if (rst_intl == 0) begin + conti_data_flag <= 0; + conti_data_cnt <= 5'b0; + cmd_wr_flag <= 0; + cmd_rd_flag <= 0; + id_error_flag <= 0; + far_maj_min_flag <= 0; + cmd_reg_new_flag <= 0; + crc_curr <= 22'b0; + crc_ck <= 0; + csbo_cnt <= 0; + csbo_flag <= 0; + downcont <= 28'b0; + rd_data_cnt <= 0; + end + else begin + if (crc_reset == 1 ) begin + crc_reg <= 32'b0; + exp_sign_reg <= 32'b0; + crc_ck <= 0; + crc_curr <= 22'b0; + end + if (desynch_set || crc_err_flag==1) begin + conti_data_flag <= 0; + conti_data_cnt <= 5'b0; + cmd_wr_flag <= 0; + cmd_rd_flag <= 0; + far_maj_min_flag <= 0; + cmd_reg_new_flag <= 0; + crc_ck <= 0; + csbo_cnt <= 0; + csbo_flag <= 0; + downcont <= 28'b0; + rd_data_cnt <= 0; + end + + if (new_data_in_flag==1 && wr_flag==1) begin + if (conti_data_flag == 1 ) begin + if (type2_flag == 0) begin + case (reg_addr) + 6'b000000 : if (conti_data_cnt==5'b00001) begin + crc_reg[15:0] <= pack_in_reg; + crc_ck <= 1; + end + else if (conti_data_cnt==5'b00010) begin + crc_reg[31:16] <= pack_in_reg; + crc_ck <= 0; + end + 6'b000001 : if (conti_data_cnt==5'b00010) begin + far_maj_reg <= pack_in_reg; + far_maj_min_flag <=1; + end + else if (conti_data_cnt==5'b00001) begin + if (far_maj_min_flag ==1) begin + far_min_reg <= pack_in_reg; + far_maj_min_flag <= 0; + end + else + far_maj_reg <= pack_in_reg; + end + 6'b000010 : far_min_reg <= pack_in_reg; + 6'b000011 : fdri_reg <= pack_in_reg; + 6'b000101 : cmd_reg <= pack_in_reg[4:0]; + 6'b000110 : ctl_reg <= (pack_in_reg & ~mask_reg) | (ctl_reg & mask_reg); + 6'b000111 : mask_reg <= pack_in_reg; + 6'b001001 : lout_reg <= pack_in_reg; + 6'b001010 : cor1_reg <= pack_in_reg; + 6'b001011 : cor2_reg <= pack_in_reg; + 6'b001100 : pwrdn_reg <= pack_in_reg; + 6'b001101 : flr_reg <= pack_in_reg; + 6'b001110 : + if (conti_data_cnt==5'b00001) begin + idcode_reg[15:0] <= pack_in_reg; + idcode_tmp = {idcode_reg[31:16], pack_in_reg}; + if (idcode_tmp[27:0] != DEVICE_ID[27:0]) begin + id_error_flag <= 1; + $display("Error : written value to IDCODE register is %h which does not match DEVICE ID %h on SIM_CONFIG_S3A instance %m at time %t.", idcode_tmp, DEVICE_ID, $time); + end + else + id_error_flag <= 0; + end + else if (conti_data_cnt==5'b00010) + idcode_reg[31:16] <= pack_in_reg; + + 6'b001111 : snowplow_reg <= pack_in_reg; + 6'b010000 : hc_opt_reg <= pack_in_reg; + 6'b010010 : begin +// csbo_reg <= pack_in_reg; +// csbo_cnt <= pack_in_reg[4:0]; +// csbo_flag <= 1; + end + 6'b010011 : general1_reg <= pack_in_reg; + 6'b010100 : general2_reg <= pack_in_reg; + 6'b010101 : mode_reg <= pack_in_reg; + 6'b010110 : pu_gwe_reg <= pack_in_reg; + 6'b010111 : pu_gts_reg <= pack_in_reg; + 6'b011000 : mfwr_reg <= pack_in_reg; + 6'b011001 : cclk_freq_reg <= pack_in_reg; + 6'b011010 : seu_opt_reg <= pack_in_reg; + 6'b011011 : if (conti_data_cnt==5'b00001) + exp_sign_reg[15:0] <= pack_in_reg; + else if (conti_data_cnt==5'b00010) + exp_sign_reg[31:16] <= pack_in_reg; + endcase + + if (reg_addr == 6'b000101) + cmd_reg_new_flag <= 1; + else + cmd_reg_new_flag <= 0; + + if (crc_en == 1) begin + if (reg_addr == 6'h05 && pack_in_reg[4:0] == 5'b00111) + crc_curr[21:0] = 22'b0; + else begin + if (reg_addr != 6'h04 && reg_addr != 6'h08 && reg_addr != 6'h1c && + reg_addr != 6'h09 && reg_addr != 6'h12 && reg_addr != 6'h00) begin + crc_input[21:0] = {reg_addr[5:0], pack_in_reg}; + crc_new[21:0] = crc_next(crc_curr, crc_input); + crc_curr[21:0] <= crc_new; + end + end + end + end + else begin // type2_flag + if (conti_data_cnt ==2) + downcont[27:16] <= pack_in_reg[11:0]; + else if (conti_data_cnt ==1) + downcont[15:0] <= pack_in_reg; + end + + if (conti_data_cnt <= 5'b00001) begin + conti_data_cnt <= 5'b0; + type2_flag <= 0; + end + else + conti_data_cnt <= conti_data_cnt - 1; + end + else begin //if (conti_data_flag == 0 ) + if ( downcont >= 1) begin + if (crc_en == 1) begin + crc_input[21:0] = {6'b000011, pack_in_reg}; //FDRI address plus data + crc_new[21:0] = crc_next(crc_curr, crc_input); + crc_curr[21:0] <= crc_new; + end + end + + if (pack_in_reg[15:13] == 3'b010 && downcont == 0 ) begin +// $display("Warning : only Type 1 Packet supported on SIM_CONFIG_S3A instance %m at time %t.", $time); + cmd_wr_flag <= 0; + type2_flag <= 1; + conti_data_flag <= 1; + conti_data_cnt <= 5'b00010; + end + else if (pack_in_reg[15:13] == 3'b001) begin + if (pack_in_reg[12:11] == 2'b01 && downcont == 0) begin + if (pack_in_reg[4:0] != 5'b0) begin + cmd_rd_flag <= 1; + cmd_wr_flag <= 0; +// rd_data_cnt <= {pack_in_reg[4:0], 1'b0}; + rd_data_cnt <= 6'b000100; + conti_data_cnt <= 5'b0; + conti_data_flag = 0; + rd_reg_addr <= pack_in_reg[10:5]; + end + end + else if (pack_in_reg[12:11] == 2'b10 && downcont == 0) begin + if (pack_in_reg[15:5] == 11'b00110010010) begin // csbo reg + csbo_reg <= pack_in_reg; + csbo_cnt = pack_in_reg[4:0]; + csbo_flag <= 1; + conti_data_flag = 0; + reg_addr <= pack_in_reg[10:5]; + cmd_wr_flag <= 1; + conti_data_cnt <= 5'b0; + end + else if (pack_in_reg[4:0] != 5'b0 ) begin + cmd_wr_flag <= 1; + conti_data_flag <= 1; + conti_data_cnt <= pack_in_reg[4:0]; + reg_addr <= pack_in_reg[10:5]; + end + end + else begin + cmd_wr_flag <= 0; + conti_data_flag <= 0; + conti_data_cnt <= 5'b0; + end + end + cmd_reg_new_flag <= 0; + crc_ck <= 0; + end // if (conti_data_flag == 0 ) + + if (csbo_cnt != 0 ) begin + if (csbo_flag) + csbo_cnt <= csbo_cnt - 1; + end + else + csbo_flag <= 0; + + if (conti_data_cnt == 5'b00001 ) + conti_data_flag <= 0; + + end + + if (rw_en ==1) begin + if (rd_data_cnt == 1) begin + rd_data_cnt <= 0; + end + else if (rd_data_cnt == 0 && rd_flag) + cmd_rd_flag <= 0; + else if (cmd_rd_flag && rd_flag) + rd_data_cnt <= rd_data_cnt - 1; + + if (downcont >= 1 && conti_data_flag == 0 && new_data_in_flag == 1 && wr_flag == 1) + downcont <= downcont - 1; + end + end + + always @(posedge cclk_in or negedge rst_intl) + if (rst_intl ==0) begin + outbus <= 8'b0; + end + else begin + if (cmd_rd_flag == 1 && rdwr_b_in == 1 && csi_b_in == 0) begin + case (rd_reg_addr) + 6'b000000 : if (rd_data_cnt==1) + outbus <= crc_reg[7:0]; + else if (rd_data_cnt==2) + outbus <= crc_reg[15:8]; + else if (rd_data_cnt==6'b000011) + outbus <= crc_reg[23:16]; + else if (rd_data_cnt==6'b000100) + outbus <= crc_reg[31:24]; + 6'b001000 : if (rd_data_cnt==1) + outbus <= stat_reg[7:0]; + else if (rd_data_cnt==2) + outbus <= stat_reg[15:8]; + else if (rd_data_cnt==3) + outbus <= stat_reg[7:0]; + else if (rd_data_cnt==4) + outbus <= stat_reg[15:8]; + 6'b001110 : if (rd_data_cnt==1) + outbus <= idcode_reg[7:0]; + else if (rd_data_cnt==2) + outbus <= idcode_reg[15:8]; + else if (rd_data_cnt==3) + outbus <= idcode_reg[23:16]; + else if (rd_data_cnt==4) + outbus <= idcode_reg[31:24]; + 6'b011011 : if (rd_data_cnt==1) + outbus <= exp_sign_reg[7:0]; + else if (rd_data_cnt==2) + outbus <= exp_sign_reg[15:8]; + else if (rd_data_cnt==3) + outbus <= exp_sign_reg[23:16]; + else if (rd_data_cnt==4) + outbus <= exp_sign_reg[31:24]; + endcase + end + else + outbus <= 8'b0; + end + + + + assign crc_rst = crc_reset | ~rst_intl; + + always @(posedge cclk_in or posedge crc_rst ) + if (crc_rst) + crc_err_flag <= 0; + else + if (crc_ck) begin + if (crc_bypass) begin + if (crc_reg[31:0] != 32'h9876defc) + crc_err_flag <= 1; + else + crc_err_flag <= 0; + end + else begin + if (crc_curr[21:0] != crc_reg[21:0]) + crc_err_flag <= 1; + else + crc_err_flag <= 0; + end + end + else + crc_err_flag <= 0; + + always @(posedge crc_err_flag or negedge rst_intl or posedge bus_sync_flag) + if (rst_intl == 0) + crc_err_flag_reg <= 0; + else if (crc_err_flag == 1) + crc_err_flag_reg <= 1; + else + crc_err_flag_reg <= 0; + + always @(posedge cclk_in or negedge rst_intl) + if (rst_intl ==0) begin + startup_set <= 0; + crc_reset <= 0; + gsr_set <= 0; + shutdown_set <= 0; + desynch_set <= 0; + reboot_set <= 0; + ghigh_b <= 0; + end + else begin + if (cmd_reg_new_flag ==1) begin + if (cmd_reg == 5'b00011) + ghigh_b <= 1; + else if (cmd_reg == 5'b01000) + ghigh_b <= 0; + + if (cmd_reg == 5'b00101) + startup_set <= 1; + if (cmd_reg == 5'b00111) + crc_reset <= 1; + if (cmd_reg == 5'b01010) + gsr_set <= 1; + if (cmd_reg == 5'b01011) + shutdown_set <= 1; + if (cmd_reg == 5'b01101) + desynch_set <= 1; + if (cmd_reg == 5'b01110) + reboot_set <= 1; + end + else begin + startup_set <= 0; + crc_reset <= 0; + gsr_set <= 0; + shutdown_set <= 0; + desynch_set <= 0; + reboot_set <= 0; + end + end + + + always @(posedge startup_set or posedge desynch_set or negedge rw_en ) + if (rw_en == 0) + startup_set_pulse <= 2'b0; + else begin + if (startup_set_pulse == 2'b00 && startup_set ==1) + startup_set_pulse <= 2'b01; + else if (desynch_set == 1 && startup_set_pulse == 2'b01) begin + startup_set_pulse <= 2'b11; + @(posedge cclk_in ) + startup_set_pulse <= 2'b00; + end + end + always @(ctl_reg) begin + if (ctl_reg[3] == 1) + persist_en = 1; + else + persist_en = 0; + + if (ctl_reg[0] == 1) + gts_usr_b = 1; + else + gts_usr_b = 0; + end + + always @(cor1_reg) + begin + if (cor1_reg[2] ==1) + done_pin_drv = 1; + else + done_pin_drv = 0; + + if (cor1_reg[4] == 1) + crc_bypass = 1; + else + crc_bypass = 0; + end + + always @(cor2_reg) begin + if (cor2_reg[15] ==1) + reset_on_err = 1; + else + reset_on_err = 0; + + done_cycle_reg = cor2_reg[11:9]; + lock_cycle_reg = cor2_reg[8:6]; + gts_cycle_reg = cor2_reg[5:3]; + gwe_cycle_reg = cor2_reg[2:0]; + end + + + assign stat_reg[15] = sync_timeout; + assign stat_reg[14] = 0; + assign stat_reg[13] = DONE; + assign stat_reg[12] = INITB; + assign stat_reg[11:9] = mode_pin_in; + assign stat_reg[8:6] = 3'b0; + assign stat_reg[5] = ghigh_b; + assign stat_reg[4] = gwe_out; + assign stat_reg[3] = gts_out; + assign stat_reg[2] = dcm_locked; + assign stat_reg[1] = id_error_flag; + assign stat_reg[0] = crc_err_flag_reg; + + + always @(posedge cclk_in or negedge rst_intl) + if (rst_intl == 0) begin + st_state <= STARTUP_PH0; + startup_begin_flag <= 0; + startup_end_flag <= 0; + end + else begin + if (nx_st_state == STARTUP_PH1) begin + startup_begin_flag <= 1; + startup_end_flag <= 0; + end + else if (st_state == STARTUP_PH7) begin + startup_end_flag <= 1; + startup_begin_flag <= 0; + end + if (lock_cycle_reg == 3'b111 || dcm_locked == 1 || st_state != lock_cycle_reg) begin + st_state <= nx_st_state; + end + else + st_state <= st_state; + end + + always @(st_state or startup_set_pulse or DONE ) + if (( st_state == done_cycle_reg) && (DONE != 0) || ( st_state != done_cycle_reg)) + case (st_state) + STARTUP_PH0 : if (startup_set_pulse == 2'b11 ) + nx_st_state = STARTUP_PH1; + else + nx_st_state = STARTUP_PH0; + STARTUP_PH1 : nx_st_state = STARTUP_PH2; + + STARTUP_PH2 : nx_st_state = STARTUP_PH3; + + STARTUP_PH3 : nx_st_state = STARTUP_PH4; + + STARTUP_PH4 : nx_st_state = STARTUP_PH5; + + STARTUP_PH5 : nx_st_state = STARTUP_PH6; + + STARTUP_PH6 : nx_st_state = STARTUP_PH7; + + STARTUP_PH7 : nx_st_state = STARTUP_PH0; + endcase + + always @(posedge cclk_in or negedge rst_intl ) + if (rst_intl == 0) begin + gwe_out <= 0; + gts_out <= 1; + eos_startup <= 0; + gsr_st_out <= 1; + done_o <= 0; + end + else begin + + if ((nx_st_state == done_cycle_reg) || (st_state == done_cycle_reg)) + if (DONE != 0 || done_pin_drv == 1) + done_o <= 1'b1; + else + done_o <= 1'bz; + + if (nx_st_state == gwe_cycle_reg) begin + gwe_out <= 1; + end + + if (nx_st_state == gts_cycle_reg) begin + gts_out <= 0; + end + + if (nx_st_state == STARTUP_PH6) + gsr_st_out <= 0; + + if (nx_st_state == STARTUP_PH7) + eos_startup <= 1; + + end + + + assign gsr_out = gsr_st_out | gsr_cmd_out; + + always @(posedge rdwr_b_in or negedge rst_intl or + posedge abort_flag_rst or posedge csi_b_in) + if (rst_intl==0 || abort_flag_rst==1 || csi_b_in == 1) + abort_flag_wr <= 0; + else + if (abort_dis == 0 && csi_b_in == 0) begin + if ($time != 0) begin + abort_flag_wr <= 1; + $display(" Warning : RDWRB changes when CS_B low, which causes Configuration abort on SIM_CONFIG_S3A instance %m at time %t.", $time); + end + end + else + abort_flag_wr <= 0; + + always @( negedge rdwr_b_in or negedge rst_intl or posedge abort_flag_rst or posedge csi_b_in) + if (rst_intl==0 || csi_b_in == 1 || abort_flag_rst==1) + abort_flag_rd <= 0; + else + if (abort_dis == 0 && csi_b_in == 0) begin + if ($time != 0) begin + abort_flag_rd <= 1; + $display(" Warning : RDWRB changes when CS_B low, which causes Configuration abort on SIM_CONFIG_S3A instance %m at time %t.", $time); + end + end + else + abort_flag_rd <= 0; + + assign abort_flag = abort_flag_wr | abort_flag_rd; + + + always @(posedge cclk_in or negedge rst_intl) + if (rst_intl == 0) begin + abort_cnt <= 0; + abort_out_en <= 0; + end + else begin + if ( abort_flag ==1 ) begin + if (abort_cnt < 4) begin + abort_cnt <= abort_cnt + 1; + abort_out_en <= 1; + end + else + abort_flag_rst <= 1; + end + else begin + abort_cnt <= 0; + abort_out_en <= 0; + abort_flag_rst <= 0; + end + + if (abort_cnt== 0) + abort_status <= {cfgerr_b_flag, bus_sync_flag, 1'b0, 1'b1, 4'b1111}; + else if (abort_cnt== 1) + abort_status <= {cfgerr_b_flag, 1'b1, 1'b0, 1'b0, 4'b1111}; + else if (abort_cnt== 2) + abort_status <= {cfgerr_b_flag, 1'b0, 1'b0, 1'b0, 4'b1111}; + else if (abort_cnt== 3) + abort_status <= {cfgerr_b_flag, 1'b0, 1'b0, 1'b1, 4'b1111}; + + end + + + +function [21:0] crc_next; + input [21:0] crc_curr; + input [21:0] crc_input; + integer i_crc; + begin + for(i_crc = 21; i_crc > 15; i_crc=i_crc -1) + crc_next[i_crc] = crc_curr[i_crc-1] ^ crc_input[i_crc]; + + crc_next[15] = crc_curr[14] ^ crc_input[15] ^ crc_curr[21]; + + for(i_crc = 14; i_crc > 12; i_crc=i_crc -1) + crc_next[i_crc] = crc_curr[i_crc-1] ^ crc_input[i_crc]; + + crc_next[12] = crc_curr[11] ^ crc_input[12] ^ crc_curr[21]; + + for(i_crc = 11; i_crc > 7; i_crc=i_crc -1) + crc_next[i_crc] = crc_curr[i_crc-1] ^ crc_input[i_crc]; + + crc_next[7] = crc_curr[6] ^ crc_input[7] ^ crc_curr[21]; + + for(i_crc = 6; i_crc > 0; i_crc=i_crc -1) + crc_next[i_crc] = crc_curr[i_crc-1] ^ crc_input[i_crc]; + + crc_next[0] = crc_input[0] ^ crc_curr[21]; + + end +endfunction + +function [7:0] bit_revers8; + input [7:0] din8; + begin + bit_revers8[0] = din8[7]; + bit_revers8[1] = din8[6]; + bit_revers8[2] = din8[5]; + bit_revers8[3] = din8[4]; + bit_revers8[4] = din8[3]; + bit_revers8[5] = din8[2]; + bit_revers8[6] = din8[1]; + bit_revers8[7] = din8[0]; + end +endfunction + + + +endmodule diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/SIM_CONFIG_S3A_SERIAL.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/SIM_CONFIG_S3A_SERIAL.v new file mode 100644 index 0000000..d512243 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/SIM_CONFIG_S3A_SERIAL.v @@ -0,0 +1,770 @@ +// Copyright (c) 1995/2005 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Function Simulation Library Component +// / / Configuration Simulation Model +// /___/ /\ Filename : SIM_CONFIG_S3A_SERIAL.v +// \ \ / \ Timestamp : +// \___\/\___\ +// +// Revision: +// 03/02/09 - Initial version of serial configuration simulation model for +// Spartan3A. +// End Revision +//////////////////////////////////////////////////////////////////////////////// + +`timescale 1 ps / 1 ps + +module SIM_CONFIG_S3A_SERIAL ( + DONE, + CCLK, + DIN, + INITB, + M, + PROGB + ); + + inout DONE; + input CCLK; + input DIN; + inout INITB; + input [2:0] M; + input PROGB; + + parameter DEVICE_ID = 32'h0; + + localparam cfg_Tprog = 300000; // min PROG must be low, 300 ns + localparam cfg_Tpl = 100000; // max program latency us. + localparam STARTUP_PH0 = 3'b000; + localparam STARTUP_PH1 = 3'b001; + localparam STARTUP_PH2 = 3'b010; + localparam STARTUP_PH3 = 3'b011; + localparam STARTUP_PH4 = 3'b100; + localparam STARTUP_PH5 = 3'b101; + localparam STARTUP_PH6 = 3'b110; + localparam STARTUP_PH7 = 3'b111; + + wire GSR, GTS, GWE; + wire cclk_in, init_b_in, prog_b_in; + wire crc_err_flag_tot; + reg crc_err_flag_reg = 0; + reg mode_sample_flag = 0; + reg init_b_p = 1; + reg done_o = 0; + tri1 p_up; + + triand (weak1, strong0) INITB=(mode_sample_flag) ? ~crc_err_flag_tot : init_b_p; + triand (weak1, strong0) DONE=done_o; + + assign DONE = p_up; + assign INITB = p_up; + + wire done_in; + reg por_b; + wire [2:0] m_in; + reg [2:0] mode_pin_in = 3'b0; + wire [7:0] d_in, d_out; + + assign glbl.GSR = GSR; + assign glbl.GTS = GTS; +// assign glbl.GWE = GWE; + wire d_out_en, init_b_t, prog_b_t, crc_rst; + + buf buf_cclk (cclk_in, CCLK); + buf buf_din (ds_in, DIN); +// buf buf_dout (DOUT, ds_out); + buf buf_init (init_b_in, INITB); + buf buf_m_0 (m_in[0], M[0]); + buf buf_m_1 (m_in[1], M[1]); + buf buf_m_2 (m_in[2], M[2]); + buf buf_prog (prog_b_in, PROGB); + + time prog_pulse_low_edge = 0; + time prog_pulse_low = 0; + integer wr_cnt = 0; + reg [4:0] csbo_cnt = 5'b0; + reg csbo_flag = 0; + reg dcm_locked = 1; + reg [4:0] conti_data_cnt = 5'b0; + reg [5:0] rd_data_cnt = 6'b0; + wire [15:0] stat_reg; + reg [15:0] pack_in_reg = 16'b0; + reg [5:0] reg_addr; + reg [5:0] rd_reg_addr; + reg new_data_in_flag = 0; + reg wr_flag = 1; + reg rd_flag = 0; + reg cmd_wr_flag = 0; + reg cmd_rd_flag = 0; + reg bus_sync_flag = 0; + reg rd_sw_en = 0; + reg conti_data_flag = 0; + reg conti_data_flag_set = 0; + reg [2:0] st_state = STARTUP_PH0; + reg startup_begin_flag = 0; + reg startup_end_flag = 0; + reg cmd_reg_new_flag = 0; + reg far_maj_min_flag = 0; + reg crc_reset = 0; + reg crc_ck = 0; + reg crc_err_flag = 0; + wire crc_en, desync_flag; + reg [21:0] crc_curr = 22'b0; + reg [21:0] crc_new = 22'b0; + reg [21:0] crc_input = 22'b0; + reg gwe_out = 0; + reg gts_out = 1; + reg reboot_set = 0; + reg gsr_set = 0; + reg gts_usr_b = 1; + reg done_pin_drv = 0; + reg crc_bypass = 0; + reg reset_on_err = 0; + reg sync_timeout = 0; + reg [31:0] crc_reg, idcode_reg, idcode_tmp; + reg [15:0] far_maj_reg, far_min_reg, fdri_reg, fdro_reg; + reg [15:0] ctl_reg; + reg [4:0] cmd_reg; + reg [15:0] general1_reg; + reg [15:0] mask_reg, lout_reg, cor1_reg, cor2_reg, pwrdn_reg, flr_reg; + reg [15:0] snowplow_reg, hc_opt_reg, csbo_reg, general2_reg, mode_reg; + reg [15:0] pu_gwe_reg, pu_gts_reg, mfwr_reg, cclk_freq_reg, seu_opt_reg; + reg [31:0] exp_sign_reg, rdbk_sign_reg; + + reg shutdown_set = 0; + reg desynch_set = 0; + reg [2:0] done_cycle_reg = 3'b100, gts_cycle_reg = 3'b101, gwe_cycle_reg=3'b110; + reg [2:0] nx_st_state = 3'b000; + reg ghigh_b = 0; + reg eos_startup = 0; + reg startup_set = 0; + reg [1:0] startup_set_pulse = 2'b0; + reg [7:0] tmp_byte; + reg id_error_flag = 0; + reg iprog_b = 1; + reg persist_en = 0; + reg rst_sync = 0; + reg [2:0] lock_cycle_reg = 3'b0; + reg rbcrc_no_pin = 0; + reg gsr_st_out = 1; + reg gsr_cmd_out = 0; + wire rst_intl, rw_en, gsr_out; + wire cfgerr_b_flag; + reg [27:0] downcont = 28'b0; + reg type2_flag = 0; + reg rst_en=1, prog_b_a=1; + reg [15:0] tmp_dword1, tmp_dword2; + integer wr_bit_addr; + + initial begin + if (DEVICE_ID == 32'h0) begin + $display("Attribute Error : The attribute DEVICE_ID on SIM_CONFIG_S3A_SERIAL instance %m is not set."); +// $finish; + end + end + + + assign GSR = gsr_out; + assign GTS = gts_out; + assign GWE = gwe_out; + assign cfgerr_b_flag = rw_en & ~crc_err_flag_tot; + assign crc_err_flag_tot = id_error_flag | crc_err_flag_reg; + assign crc_en = 1; + assign done_in = DONE; + + assign init_b_t = init_b_in; + + always @( negedge prog_b_in) begin + rst_en = 0; + rst_en <= #cfg_Tprog 1; + end + + always @( posedge rst_en or posedge prog_b_in ) + if (rst_en) begin + if (prog_b_in == 0 ) + init_b_p <= 0; + else + init_b_p <= #(cfg_Tpl) 1; + end + + always @( rst_en or prog_b_in or prog_pulse_low) + if (rst_en) begin + if (prog_pulse_low==cfg_Tprog) begin + prog_b_a = 0; + prog_b_a <= #500 1; + end + else + prog_b_a = prog_b_in; + end + else + prog_b_a = 1; + + initial begin + por_b = 0; + por_b = #400000 1; + end + + assign prog_b_t = prog_b_a & iprog_b & por_b; + + assign rst_intl = (prog_b_t==0 ) ? 0 : 1; + + + always @(posedge init_b_t or negedge prog_b_t) + if (prog_b_t==0) + mode_sample_flag <= 0; + else if (init_b_t && mode_sample_flag == 0) begin + if (prog_b_t) begin + mode_pin_in <= m_in; + mode_sample_flag <= #1 1; + if (m_in != 3'b111) begin + $display("Error: input M is %h. Only Slave Serial mode M=111 supported on SIM_CONFIG_S3A_SERIAL instance %m.", m_in); +// $finish; + end + end + else if ($time != 0) + $display("Error: PROGB is not high when INITB goes high on SIM_CONFIG_S3A_SERIAL instance %m at time %t.", $time); + end + + always @(m_in) + if (mode_sample_flag == 1 && persist_en == 1) + $display("Error : Mode pine M[2:0] changed after rising edge of INITB on SIM_CONFIG_S3A_SERIAL instance %m at time %t.", $time); + + always @(posedge prog_b_in or negedge prog_b_in) + if (prog_b_in ==0) + prog_pulse_low_edge <= $time; + else if (prog_b_in == 1 && $time > 0) begin + prog_pulse_low = $time - prog_pulse_low_edge; + if (prog_pulse_low < cfg_Tprog ) + $display("Error: Low time of PROGB is less than required minimum Tprogram time %d on SIM_CONFIG_S3A_SERIAL instance %m at time %t.", cfg_Tprog, $time); + end + +// assign rw_en = (mode_sample_flag == 1 ) ? 1 : 0; + assign rw_en = (mode_sample_flag == 1 && done_o === 0) ? 1 : 0; + assign desync_flag = ~rst_intl | desynch_set | crc_err_flag | id_error_flag; + + always @(posedge cclk_in or posedge desync_flag) + if (desync_flag) begin + pack_in_reg <= 16'b0; + new_data_in_flag <= 0; + bus_sync_flag <= 0; + wr_cnt <= 0; + wr_flag <= 1; + tmp_dword1 <= 16'b0; + tmp_dword2 <= 16'b0; + end + else begin + if (rw_en == 1 ) begin + if (bus_sync_flag == 0) begin + tmp_dword1 = {tmp_dword2[14:0], ds_in}; + if (tmp_dword1[15:0] == 16'hAA99) begin + bus_sync_flag <= 1; + new_data_in_flag <= 0; + tmp_dword2 <= 16'b0; + pack_in_reg <= 16'b0; + wr_cnt <= 0; + end + else begin + tmp_dword2 <= tmp_dword1; + end + end + else begin + pack_in_reg <= {pack_in_reg[14:0], ds_in}; + if (wr_cnt == 15) begin + new_data_in_flag <= 1; + wr_cnt <= 0; + end + else begin + new_data_in_flag <= 0; + wr_cnt <= wr_cnt + 1; + end + end + end + else begin //rw_en = 0 + new_data_in_flag <= 0; + end + end + + always @(negedge cclk_in or negedge rst_intl) + if (rst_intl == 0) begin + conti_data_flag <= 0; + conti_data_cnt <= 5'b0; + cmd_wr_flag <= 0; + cmd_rd_flag <= 0; + id_error_flag <= 0; + far_maj_min_flag <= 0; + cmd_reg_new_flag <= 0; + crc_curr <= 22'b0; + crc_ck <= 0; + csbo_cnt <= 0; + csbo_flag <= 0; + downcont <= 28'b0; + rd_data_cnt <= 0; + end + else begin + if (crc_reset == 1 ) begin + crc_reg <= 32'b0; + exp_sign_reg <= 32'b0; + crc_ck <= 0; + crc_curr <= 22'b0; + end + if (desynch_set || crc_err_flag==1) begin + conti_data_flag <= 0; + conti_data_cnt <= 5'b0; + cmd_wr_flag <= 0; + cmd_rd_flag <= 0; + far_maj_min_flag <= 0; + cmd_reg_new_flag <= 0; + crc_ck <= 0; + csbo_cnt <= 0; + csbo_flag <= 0; + downcont <= 28'b0; + rd_data_cnt <= 0; + end + + if (new_data_in_flag==1 && wr_flag==1) begin + if (conti_data_flag == 1 ) begin + if (type2_flag == 0) begin + case (reg_addr) + 6'b000000 : if (conti_data_cnt==5'b00001) begin + crc_reg[15:0] <= pack_in_reg; + crc_ck <= 1; + end + else if (conti_data_cnt==5'b00010) begin + crc_reg[31:16] <= pack_in_reg; + crc_ck <= 0; + end + 6'b000001 : if (conti_data_cnt==5'b00010) begin + far_maj_reg <= pack_in_reg; + far_maj_min_flag <=1; + end + else if (conti_data_cnt==5'b00001) begin + if (far_maj_min_flag ==1) begin + far_min_reg <= pack_in_reg; + far_maj_min_flag <= 0; + end + else + far_maj_reg <= pack_in_reg; + end + 6'b000010 : far_min_reg <= pack_in_reg; + 6'b000011 : fdri_reg <= pack_in_reg; + 6'b000101 : cmd_reg <= pack_in_reg[4:0]; + 6'b000110 : ctl_reg <= (pack_in_reg & ~mask_reg) | (ctl_reg & mask_reg); + 6'b000111 : mask_reg <= pack_in_reg; + 6'b001001 : lout_reg <= pack_in_reg; + 6'b001010 : cor1_reg <= pack_in_reg; + 6'b001011 : cor2_reg <= pack_in_reg; + 6'b001100 : pwrdn_reg <= pack_in_reg; + 6'b001101 : flr_reg <= pack_in_reg; + 6'b001110 : + if (conti_data_cnt==5'b00001) begin + idcode_reg[15:0] <= pack_in_reg; + idcode_tmp = {idcode_reg[31:16], pack_in_reg}; + if (idcode_tmp[27:0] != DEVICE_ID[27:0]) begin + id_error_flag <= 1; + $display("Error : written value to IDCODE register is %h which does not match DEVICE ID %h on SIM_CONFIG_S3A_SERIAL instance %m at time %t.", idcode_tmp, DEVICE_ID, $time); + end + else + id_error_flag <= 0; + end + else if (conti_data_cnt==5'b00010) + idcode_reg[31:16] <= pack_in_reg; + + 6'b001111 : snowplow_reg <= pack_in_reg; + 6'b010000 : hc_opt_reg <= pack_in_reg; + 6'b010010 : begin +// csbo_reg <= pack_in_reg; +// csbo_cnt <= pack_in_reg[4:0]; + end + 6'b010011 : general1_reg <= pack_in_reg; + 6'b010100 : general2_reg <= pack_in_reg; + 6'b010101 : mode_reg <= pack_in_reg; + 6'b010110 : pu_gwe_reg <= pack_in_reg; + 6'b010111 : pu_gts_reg <= pack_in_reg; + 6'b011000 : mfwr_reg <= pack_in_reg; + 6'b011001 : cclk_freq_reg <= pack_in_reg; + 6'b011010 : seu_opt_reg <= pack_in_reg; + 6'b011011 : if (conti_data_cnt==5'b00001) + exp_sign_reg[15:0] <= pack_in_reg; + else if (conti_data_cnt==5'b00010) + exp_sign_reg[31:16] <= pack_in_reg; + endcase + + if (reg_addr == 6'b000101) + cmd_reg_new_flag <= 1; + else + cmd_reg_new_flag <= 0; + + if (crc_en == 1) begin + if (reg_addr == 6'h05 && pack_in_reg[4:0] == 5'b00111) + crc_curr[21:0] = 22'b0; + else begin + if (reg_addr != 6'h04 && reg_addr != 6'h08 && reg_addr != 6'h1c && + reg_addr != 6'h09 && reg_addr != 6'h12 && reg_addr != 6'h00) begin + crc_input[21:0] = {reg_addr[5:0], pack_in_reg}; + crc_new[21:0] = crc_next(crc_curr, crc_input); + crc_curr[21:0] <= crc_new; + end + end + end + end + else begin // type2_flag + if (conti_data_cnt ==2) + downcont[27:16] <= pack_in_reg[11:0]; + else if (conti_data_cnt ==1) + downcont[15:0] <= pack_in_reg; + end + + if (conti_data_cnt <= 5'b00001) begin + conti_data_cnt <= 5'b0; + type2_flag <= 0; + end + else + conti_data_cnt <= conti_data_cnt - 1; + end + else begin //if (conti_data_flag == 0 ) + if ( downcont >= 1) begin + if (crc_en == 1) begin + crc_input[21:0] = {6'b000011, pack_in_reg}; //FDRI address plus data + crc_new[21:0] = crc_next(crc_curr, crc_input); + crc_curr[21:0] <= crc_new; + end + end + + if (pack_in_reg[15:13] != 3'b001 && downcont == 0 ) begin +// $display("Warning : only Type 1 Packet supported on SIM_CONFIG_S3A_SERIAL instance %m at time %t.", $time); + cmd_wr_flag <= 0; + type2_flag <= 1; + conti_data_flag <= 1; + conti_data_cnt <= 5'b00010; + end + else begin + if (pack_in_reg[12:11] == 2'b01 && downcont == 0) begin + if (pack_in_reg[4:0] != 5'b0) begin + cmd_rd_flag <= 1; + cmd_wr_flag <= 0; +// rd_data_cnt <= {pack_in_reg[4:0], 1'b0}; + rd_data_cnt <= 6'b000100; + conti_data_cnt <= 5'b0; + conti_data_flag = 0; + rd_reg_addr <= pack_in_reg[10:5]; + end + end + else if (pack_in_reg[12:11] == 2'b10 && downcont == 0) begin + if (pack_in_reg[15:5] == 11'b00110010010) begin // csbo reg + csbo_reg <= pack_in_reg; + csbo_cnt = pack_in_reg[4:0]; + csbo_flag <= 1; + conti_data_flag = 0; + reg_addr <= pack_in_reg[10:5]; + cmd_wr_flag <= 1; + conti_data_cnt <= 5'b0; + end + else if (pack_in_reg[4:0] != 5'b0 ) begin + cmd_wr_flag <= 1; + conti_data_flag <= 1; + conti_data_cnt <= pack_in_reg[4:0]; + reg_addr <= pack_in_reg[10:5]; + end + end + else begin + cmd_wr_flag <= 0; + conti_data_flag <= 0; + conti_data_cnt <= 5'b0; + end + end + cmd_reg_new_flag <= 0; + crc_ck <= 0; + end // if (conti_data_flag == 0 ) + + if (csbo_cnt != 0 ) begin + if (csbo_flag) + csbo_cnt <= csbo_cnt - 1; + end + else + csbo_flag <= 0; + + if (conti_data_cnt == 5'b00001 ) + conti_data_flag <= 0; + + end + + if (rw_en ==1) begin + if (rd_data_cnt == 1) begin + rd_data_cnt <= 0; + end + else if (rd_data_cnt == 0 && rd_flag) + cmd_rd_flag <= 0; + else if (cmd_rd_flag && rd_flag) + rd_data_cnt <= rd_data_cnt - 1; + + if (downcont >= 1 && conti_data_flag == 0 && new_data_in_flag == 1 && wr_flag == 1) + downcont <= downcont - 1; + end + if (crc_ck) + crc_ck <= 0; + end + + assign crc_rst = crc_reset | ~rst_intl; + + always @(posedge cclk_in or posedge crc_rst ) + if (crc_rst) + crc_err_flag <= 0; + else + if (crc_ck) begin + if (crc_bypass) begin + if (crc_reg[31:0] != 32'h9876defc) + crc_err_flag <= 1; + else + crc_err_flag <= 0; + end + else begin + if (crc_curr[21:0] != crc_reg[21:0]) + crc_err_flag <= 1; + else + crc_err_flag <= 0; + end + end + else + crc_err_flag <= 0; + + always @(posedge crc_err_flag or negedge rst_intl or posedge bus_sync_flag) + if (rst_intl == 0) + crc_err_flag_reg <= 0; + else if (crc_err_flag == 1) + crc_err_flag_reg <= 1; + else + crc_err_flag_reg <= 0; + + always @(posedge cclk_in or negedge rst_intl) + if (rst_intl ==0) begin + startup_set <= 0; + crc_reset <= 0; + gsr_set <= 0; + shutdown_set <= 0; + desynch_set <= 0; + reboot_set <= 0; + ghigh_b <= 0; + end + else begin + if (cmd_reg_new_flag ==1) begin + if (cmd_reg == 5'b00011) + ghigh_b <= 1; + else if (cmd_reg == 5'b01000) + ghigh_b <= 0; + + if (cmd_reg == 5'b00101) + startup_set <= 1; + if (cmd_reg == 5'b00111) + crc_reset <= 1; + if (cmd_reg == 5'b01010) + gsr_set <= 1; + if (cmd_reg == 5'b01011) + shutdown_set <= 1; + if (cmd_reg == 5'b01101) + desynch_set <= 1; + if (cmd_reg == 5'b01110) + reboot_set <= 1; + end + else begin + startup_set <= 0; + crc_reset <= 0; + gsr_set <= 0; + shutdown_set <= 0; + desynch_set <= 0; + reboot_set <= 0; + end + end + + + always @(posedge startup_set or posedge desynch_set or negedge rw_en ) + if (rw_en == 0) + startup_set_pulse <= 2'b0; + else begin + if (startup_set_pulse == 2'b00 && startup_set ==1) + startup_set_pulse <= 2'b01; + else if (desynch_set == 1 && startup_set_pulse == 2'b01) begin + startup_set_pulse <= 2'b11; + @(posedge cclk_in ) + startup_set_pulse <= 2'b00; + end + end + always @(ctl_reg) begin + if (ctl_reg[3] == 1) + persist_en = 1; + else + persist_en = 0; + + if (ctl_reg[0] == 1) + gts_usr_b = 1; + else + gts_usr_b = 0; + end + + always @(cor1_reg) + begin + if (cor1_reg[2] ==1) + done_pin_drv = 1; + else + done_pin_drv = 0; + + if (cor1_reg[4] == 1) + crc_bypass = 1; + else + crc_bypass = 0; + end + + always @(cor2_reg) begin + if (cor2_reg[15] ==1) + reset_on_err = 1; + else + reset_on_err = 0; + + done_cycle_reg = cor2_reg[11:9]; + lock_cycle_reg = cor2_reg[8:6]; + gts_cycle_reg = cor2_reg[5:3]; + gwe_cycle_reg = cor2_reg[2:0]; + end + + + assign stat_reg[15] = sync_timeout; + assign stat_reg[14] = 0; + assign stat_reg[13] = DONE; + assign stat_reg[12] = INITB; + assign stat_reg[11:9] = mode_pin_in; + assign stat_reg[8:6] = 3'b0; + assign stat_reg[5] = ghigh_b; + assign stat_reg[4] = gwe_out; + assign stat_reg[3] = gts_out; + assign stat_reg[2] = dcm_locked; + assign stat_reg[1] = id_error_flag; + assign stat_reg[0] = crc_err_flag_reg; + + + always @(posedge cclk_in or negedge rst_intl) + if (rst_intl == 0) begin + st_state <= STARTUP_PH0; + startup_begin_flag <= 0; + startup_end_flag <= 0; + end + else begin + if (nx_st_state == STARTUP_PH1) begin + startup_begin_flag <= 1; + startup_end_flag <= 0; + end + else if (st_state == STARTUP_PH7) begin + startup_end_flag <= 1; + startup_begin_flag <= 0; + end + if (lock_cycle_reg == 3'b111 || dcm_locked == 1 || st_state != lock_cycle_reg) begin + st_state <= nx_st_state; + end + else + st_state <= st_state; + end + + always @(st_state or startup_set_pulse or DONE ) + if (( st_state == done_cycle_reg) && (DONE != 0) || ( st_state != done_cycle_reg)) + case (st_state) + STARTUP_PH0 : if (startup_set_pulse == 2'b11 ) + nx_st_state = STARTUP_PH1; + else + nx_st_state = STARTUP_PH0; + STARTUP_PH1 : nx_st_state = STARTUP_PH2; + + STARTUP_PH2 : nx_st_state = STARTUP_PH3; + + STARTUP_PH3 : nx_st_state = STARTUP_PH4; + + STARTUP_PH4 : nx_st_state = STARTUP_PH5; + + STARTUP_PH5 : nx_st_state = STARTUP_PH6; + + STARTUP_PH6 : nx_st_state = STARTUP_PH7; + + STARTUP_PH7 : nx_st_state = STARTUP_PH0; + endcase + + always @(posedge cclk_in or negedge rst_intl ) + if (rst_intl == 0) begin + gwe_out <= 0; + gts_out <= 1; + eos_startup <= 0; + gsr_st_out <= 1; + done_o <= 0; + end + else begin + + if ((nx_st_state == done_cycle_reg) || (st_state == done_cycle_reg)) + if (DONE != 0 || done_pin_drv == 1) + done_o <= 1'b1; + else + done_o <= 1'bz; + + if (nx_st_state == gwe_cycle_reg) begin + gwe_out <= 1; + end + + if (nx_st_state == gts_cycle_reg) begin + gts_out <= 0; + end + + if (nx_st_state == STARTUP_PH6) + gsr_st_out <= 0; + + if (nx_st_state == STARTUP_PH7) + eos_startup <= 1; + + end + + + assign gsr_out = gsr_st_out | gsr_cmd_out; + +function [21:0] crc_next; + input [21:0] crc_curr; + input [21:0] crc_input; + integer i_crc; + begin + for(i_crc = 21; i_crc > 15; i_crc=i_crc -1) + crc_next[i_crc] = crc_curr[i_crc-1] ^ crc_input[i_crc]; + + crc_next[15] = crc_curr[14] ^ crc_input[15] ^ crc_curr[21]; + + for(i_crc = 14; i_crc > 12; i_crc=i_crc -1) + crc_next[i_crc] = crc_curr[i_crc-1] ^ crc_input[i_crc]; + + crc_next[12] = crc_curr[11] ^ crc_input[12] ^ crc_curr[21]; + + for(i_crc = 11; i_crc > 7; i_crc=i_crc -1) + crc_next[i_crc] = crc_curr[i_crc-1] ^ crc_input[i_crc]; + + crc_next[7] = crc_curr[6] ^ crc_input[7] ^ crc_curr[21]; + + for(i_crc = 6; i_crc > 0; i_crc=i_crc -1) + crc_next[i_crc] = crc_curr[i_crc-1] ^ crc_input[i_crc]; + + crc_next[0] = crc_input[0] ^ crc_curr[21]; + + end +endfunction + +function [7:0] bit_revers8; + input [7:0] din8; + begin + bit_revers8[0] = din8[7]; + bit_revers8[1] = din8[6]; + bit_revers8[2] = din8[5]; + bit_revers8[3] = din8[4]; + bit_revers8[4] = din8[3]; + bit_revers8[5] = din8[2]; + bit_revers8[6] = din8[1]; + bit_revers8[7] = din8[0]; + end +endfunction + + + +endmodule diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/SIM_CONFIG_S6.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/SIM_CONFIG_S6.v new file mode 100644 index 0000000..dd50760 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/SIM_CONFIG_S6.v @@ -0,0 +1,1329 @@ +// Copyright (c) 1995/2005 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Function Simulation Library Component +// / / Configuration Simulation Model +// /___/ /\ Filename : SIM_CONFIG_S6.v +// \ \ / \ Timestamp : +// \___\/\___\ +// +// Revision: +// 03/12/09 - Spartan6 configuration simulation model based on Spartan3A. +// 09/17/09 - Remove DCMLOCK pin (CR530867) +// 10/02/09 - Not write to frame out file after icap_init_done=1 (CR535320) +// 11/25/09 - Fix CRC (CR538766) +// 12/17/09 - Allow ICAP use without RBT file (CR537437) +// 01/12/10 - Reverse bits for readback (CR544212) +// 02/04/10 - Support MMCM lock wait function (CR547918) +// 02/24/10 - Change Tprog to 500 ns (CR550552) +// - desync when icap initial done. (CR551856) +// 03/03/10 - set mode_sample_flag to 0 when mode pin set wrong (CR552316) +// 03/10/10 - Not check crc when icap initial time (553387) +// 05/19/10 - Not reset startup_set_pulse when rw_en=0 (CR559852) +// End Revision +//////////////////////////////////////////////////////////////////////////////// + +`timescale 1 ps / 1 ps + +module SIM_CONFIG_S6 ( + BUSY, + CSOB, + DONE, + CCLK, + D, + CSIB, + INITB, + M, + PROGB, + RDWRB + ); + + output BUSY; + output CSOB; + inout DONE; + input CCLK; + input CSIB; + inout [15:0] D; + inout INITB; + input [1:0] M; + input PROGB; + input RDWRB; + + parameter DEVICE_ID = 32'h0; + parameter ICAP_SUPPORT = "FALSE"; + + localparam FRAME_RBT_OUT_FILENAME = "frame_data_s6_rbt_out.txt"; + localparam cfg_Tprog = 500000; // min PROG must be low, 300 ns + localparam cfg_Tpl = 100000; // max program latency us. + localparam STARTUP_PH0 = 3'b000; + localparam STARTUP_PH1 = 3'b001; + localparam STARTUP_PH2 = 3'b010; + localparam STARTUP_PH3 = 3'b011; + localparam STARTUP_PH4 = 3'b100; + localparam STARTUP_PH5 = 3'b101; + localparam STARTUP_PH6 = 3'b110; + localparam STARTUP_PH7 = 3'b111; + + wire GSR, GTS, GWE; + wire cclk_in, csi_b_in, init_b_in, prog_b_in, rdwr_b_in; + wire crc_err_flag_tot; + reg crc_err_flag_reg = 0; + reg mode_sample_flag = 0; + reg init_b_p = 1; + reg done_o = 0; + reg busy_o = 0; + wire busy_out; + tri1 p_up; + integer frame_data_fd; + reg frame_data_wen = 0; + + triand (weak1, strong0) INITB=(mode_sample_flag) ? ~crc_err_flag_tot : init_b_p; + triand (weak1, strong0) DONE=done_o; + + assign DONE = p_up; + assign INITB = p_up; + + wire done_in; + reg por_b; + wire [1:0] m_in; + reg [2:0] mode_pin_in = 3'b0; + wire [15:0] d_in, d_out; + + assign glbl.GSR = GSR; + assign glbl.GTS = GTS; +// assign glbl.GWE = GWE; + wire csbo_b_out ; + wire pll_locked; + wire d_out_en, init_b_t, prog_b_t, crc_rst; + reg icap_clr = 0; + + buf buf_busy (BUSY, busy_out); + buf buf_cso (CSOB, csbo_b_out); + buf buf_cclk (cclk_in, CCLK); + buf buf_csi (csi_b_in, CSIB); + + buf buf_din[15:0] (d_in, D); + bufif1 buf_dout[15:0] (D, d_out, d_out_en); + + buf buf_init (init_b_in, INITB); + buf buf_m_0 (m_in[0], M[0]); + buf buf_m_1 (m_in[1], M[1]); + buf buf_prog (prog_b_in, PROGB); + buf buf_rw (rdwr_b_in, RDWRB); + + time prog_pulse_low_edge = 0; + time prog_pulse_low = 0; + integer wr_cnt = 0; + reg [4:0] conti_data_cnt = 5'b0; + reg [5:0] rd_data_cnt = 6'b0; + integer abort_cnt = 0; + reg [4:0] csbo_cnt = 0; + reg csbo_flag = 0; + reg [15:0] pack_in_reg = 16'b0; + reg [5:0] reg_addr; + reg [5:0] rd_reg_addr; + reg new_data_in_flag = 0; + reg wr_flag = 0; + reg rd_flag = 0; + reg cmd_wr_flag = 0; + reg cmd_rd_flag = 0; + reg bus_sync_flag = 0; + reg [1:0] buswidth_tmp = 2'b00; + wire [1:0] buswidth; + reg csi_sync = 0; + reg rd_sw_en = 0; + reg conti_data_flag = 0; + reg conti_data_flag_set = 0; + reg [2:0] st_state = STARTUP_PH0; + reg startup_begin_flag = 0; + reg startup_end_flag = 0; + reg cmd_reg_new_flag = 0; + reg far_maj_min_flag = 0; + reg crc_reset = 0; + reg crc_ck = 0; + reg crc_err_flag = 0; + wire crc_en, desync_flag; + reg [21:0] crc_curr = 22'b0; + reg [21:0] crc_new = 22'b0; + reg [21:0] crc_input = 22'b0; + reg gwe_out = 0; + reg gts_out = 1; + reg [15:0] d_o = 16'h0; + reg [15:0] outbus = 16'h0; + reg [15:0] outbus1 = 16'h0; + reg reboot_set = 0; + reg gsr_set = 0; + reg gts_usr_b = 1; + reg done_pin_drv = 0; + reg crc_bypass = 0; + reg reset_on_err = 0; + reg sync_timeout = 0; + reg [31:0] crc_reg, idcode_reg, idcode_tmp; + reg [15:0] far_maj_reg, far_min_reg, fdri_reg, fdro_reg, cwdt_reg; + reg [15:0] ctl_reg = 8'b10000001; + reg [4:0] cmd_reg; + reg [15:0] general1_reg; + reg [15:0] mask_reg = 8'b0; + reg [15:0] lout_reg, flr_reg; + reg [15:0] cor1_reg = 16'b0x11011100000000; + reg [15:0] cor2_reg = 16'b0000100111101110; + reg [15:0] pwrdn_reg = 16'bx00010001000x001; + reg [15:0] snowplow_reg, hc_opt_reg, csbo_reg, general2_reg, mode_reg; + reg [15:0] general3_reg, general4_reg, general5_reg; + reg [15:0] eye_mask_reg, cbc_reg, seu_reg, bootsts_reg; + reg [15:0] pu_gwe_reg, pu_gts_reg, mfwr_reg, cclk_freq_reg, seu_opt_reg; + reg [31:0] exp_sign_reg, rdbk_sign_reg; + + reg shutdown_set = 0; + reg desynch_set = 0; + reg icap_desynch = 0; + reg [2:0] done_cycle_reg = 3'b100, gts_cycle_reg = 3'b101, gwe_cycle_reg=3'b110; + reg [2:0] nx_st_state = 3'b000; + reg ghigh_b = 0; + reg eos_startup = 0; + reg startup_set = 0; + reg [1:0] startup_set_pulse = 2'b0; + reg abort_out_en; + reg [7:0] tmp_byte, tmp_byte1, tmp_byte2, tmp_byte3, tmp_byte4; + reg [7:0] tmp_byte5, tmp_byte6, tmp_byte7; + reg [15:0] tmp_word, ctl_reg_tmp; + reg id_error_flag = 0; + reg iprog_b = 1; + reg [15:0] abort_status = 16'b0; + reg persist_en = 0; + reg rst_sync = 0; + reg abort_dis = 0; + reg [2:0] lock_cycle_reg = 3'b0; + reg rbcrc_no_pin = 0; + reg abort_flag_rst = 0; + reg gsr_st_out = 1; + reg gsr_cmd_out = 0; + reg d_o_en = 0; + wire [15:0] stat_reg; + wire rst_intl, rw_en, gsr_out; + wire cfgerr_b_flag; + wire abort_flag; + reg abort_flag_wr = 0; + reg abort_flag_rd = 0; + reg [27:0] downcont = 28'b0; + reg type2_flag = 0; + reg rst_en=1, prog_b_a=1; + reg icap_on = 0; + reg [1:0] icap_bw = 2'b10; + reg icap_init_done = 0; + reg icap_init_done_dly = 0; + + initial begin + if (DEVICE_ID == 32'h0 && icap_on == 0) begin + $display("Attribute Error : The attribute DEVICE_ID on SIM_CONFIG_S6 instance %m is not set."); + end + + case (ICAP_SUPPORT) + "FALSE" : icap_on = 0; + "TRUE" : icap_on = 1; + default : icap_on = 0; + endcase + + if (ICAP_SUPPORT == "TRUE") begin + frame_data_fd = $fopen(FRAME_RBT_OUT_FILENAME, "w"); + if (frame_data_fd != 0) begin + frame_data_wen = 1; + end + end + else begin + frame_data_wen = 0; + end + + end + + + assign GSR = gsr_out; + assign GTS = gts_out; + assign GWE = gwe_out; + assign busy_out = busy_o; + assign csbo_b_out = (csbo_flag== 1) ? 0 : 1; + assign cfgerr_b_flag = rw_en & ~crc_err_flag_tot; + assign crc_err_flag_tot = id_error_flag | crc_err_flag_reg; + assign d_out = (abort_out_en ) ? abort_status : outbus1; + assign d_out_en = d_o_en; + assign crc_en = (icap_init_done) ? 0 : 1; + assign done_in = DONE; + assign pll_locked = (glbl.PLL_LOCKG === 0) ? 0 : 1; + + always @(outbus) begin + outbus1[7:0] = bit_revers8(outbus[7:0]); + outbus1[15:8] = bit_revers8(outbus[15:8]); + end + + + always @(csi_b_in or abort_flag) + if (csi_b_in) + busy_o = 1'b1; + else + if (abort_flag) + busy_o = 1'b1; + else begin + @(posedge cclk_in); + @(posedge cclk_in); + @(posedge cclk_in) + busy_o = 1'b0; + end + + always @(abort_out_en or csi_b_in or rdwr_b_in or rd_flag ) + if (abort_out_en) + d_o_en = 1; + else + d_o_en = rdwr_b_in & ~csi_b_in & rd_flag; + + + assign init_b_t = init_b_in; + + always @( negedge prog_b_in) begin + rst_en = 0; + rst_en <= #cfg_Tprog 1; + end + + always @( posedge rst_en or posedge prog_b_in ) + if (rst_en) begin + if (prog_b_in == 0 ) + init_b_p <= 0; + else + init_b_p <= #(cfg_Tpl) 1; + end + + always @( rst_en or prog_b_in or prog_pulse_low) + if (rst_en) begin + if (prog_pulse_low==cfg_Tprog) begin + prog_b_a = 0; + prog_b_a <= #500 1; + end + else + prog_b_a = prog_b_in; + end + else + prog_b_a = 1; + + initial begin + por_b = 0; + por_b = #400000 1; + end + + assign prog_b_t = prog_b_a & iprog_b & por_b; + + assign rst_intl = (prog_b_t==0 ) ? 0 : 1; + + + always @( init_b_t or prog_b_t) + if (prog_b_t == 0) + mode_sample_flag <= 0; + else if (init_b_t && mode_sample_flag == 0) begin + if (prog_b_t == 1) begin + mode_pin_in <= m_in; + if (m_in !== 2'b10) begin + mode_sample_flag <= 0; + if ( icap_on == 0) + $display("Error: input M is %h. Only Slave SelectMAP mode M=10 supported on SIM_CONFIG_S6 instance %m.", m_in); + end + else + mode_sample_flag <= #1 1; + end + end + + always @(posedge init_b_t ) + if (prog_b_t != 1) begin + if ($time != 0 && icap_on == 0) + $display("Error: PROGB is not high when INITB goes high on SIM_CONFIG_S6 instance %m at time %t.", $time); + end + + always @(m_in) + if (mode_sample_flag == 1 && persist_en == 1 && icap_on == 0) + $display("Error : Mode pine M[2:0] changed after rising edge of INITB on SIM_CONFIG_S6 instance %m at time %t.", $time); + + always @(posedge prog_b_in or negedge prog_b_in) + if (prog_b_in ==0) + prog_pulse_low_edge <= $time; + else if (prog_b_in == 1 && $time > 0) begin + prog_pulse_low = $time - prog_pulse_low_edge; + if (prog_pulse_low < cfg_Tprog && icap_on == 0) + $display("Error: Low time of PROGB is less than required minimum Tprogram time %d on SIM_CONFIG_S6 instance %m at time %t.", cfg_Tprog, $time); + end + + assign rw_en = (mode_sample_flag == 1 && csi_b_in ==0) ? 1 : 0; + assign desync_flag = ~rst_intl | desynch_set | crc_err_flag | id_error_flag + | icap_desynch; + assign buswidth[1:0] = (icap_on == 1 && icap_init_done == 1) ? icap_bw[1:0] : buswidth_tmp[1:0]; + + + always @(posedge eos_startup ) + if (icap_on == 1) begin + $fclose(frame_data_fd); + icap_init_done <= 1; + @(posedge cclk_in); + @(posedge cclk_in) + if (icap_init_done_dly == 0) + icap_desynch <= 1; + @(posedge cclk_in); + @(posedge cclk_in) begin + icap_desynch <= 0; + icap_init_done_dly <= 1; + end + end + + always @(posedge cclk_in) + csi_sync <= csi_b_in; + + always @(posedge cclk_in or negedge rdwr_b_in) + if (rdwr_b_in ==0) + rd_sw_en <= 0; + else begin + if (csi_sync == 1 && rdwr_b_in ==1) + rd_sw_en <= 1; + end + + always @(posedge cclk_in or posedge desync_flag or posedge csi_b_in) + if (desync_flag == 1 ) begin + pack_in_reg <= 16'b0; + new_data_in_flag <= 0; + bus_sync_flag <= 0; + buswidth_tmp <= 2'b00; + wr_cnt <= 0; + wr_flag <= 0; + rd_flag <= 0; + end + else if (icap_init_done == 1 && csi_b_in == 1 && rdwr_b_in == 0) begin + pack_in_reg <= 32'b0; + new_data_in_flag <= 0; + wr_cnt <= 0; + end + else begin + if (icap_clr == 1) begin + pack_in_reg <= 16'b0; + new_data_in_flag <= 0; + wr_cnt <= 0; + wr_flag <= 0; + rd_flag <= 0; + end + else if (rw_en == 1 ) begin + if (rdwr_b_in == 0) begin + wr_flag <= 1; + rd_flag <= 0; + if (bus_sync_flag == 0) begin + tmp_byte = bit_revers8(d_in[7:0]); + tmp_byte1 = bit_revers8(d_in[15:8]); + if (tmp_byte3 == 8'hAA && tmp_byte2 == 8'h99 && + tmp_byte1 == 8'h55 && tmp_byte == 8'h66) begin + bus_sync_flag <= 1; + new_data_in_flag <= 0; + buswidth_tmp <= 2'b10; + wr_cnt <= 0; + end + else if (tmp_byte6 == 8'hAA && tmp_byte4 == 8'h99 && + tmp_byte2 == 8'h55 && tmp_byte == 8'h66) begin + bus_sync_flag <= 1; + new_data_in_flag <= 0; + buswidth_tmp <= 2'b01; + wr_cnt <= 0; + end + else begin + tmp_byte7 <= tmp_byte5; + tmp_byte6 <= tmp_byte4; + tmp_byte5 <= tmp_byte3; + tmp_byte4 <= tmp_byte2; + tmp_byte3 <= tmp_byte1; + tmp_byte2 <= tmp_byte; + end + end + else begin + if (buswidth == 2'b01) begin + tmp_byte = bit_revers8(d_in[7:0]); + if (wr_cnt == 0) begin + pack_in_reg[15:8] <= tmp_byte; + new_data_in_flag <= 0; + wr_cnt <= 1; + end + else if (wr_cnt == 1) begin + pack_in_reg[7:0] <= tmp_byte; + new_data_in_flag <= 1; + wr_cnt <= 0; + end + end + else if (buswidth == 2'b10) begin + tmp_word = {bit_revers8(d_in[15:8]), bit_revers8(d_in[7:0])}; + pack_in_reg[15:0] <= tmp_word; + new_data_in_flag <= 1; + end + end + end + else begin //rdwr_b_in = 1 + wr_flag <= 0; + new_data_in_flag <= 0; + if (rd_sw_en ==1) + rd_flag <= 1; + end + end + else begin //rw_en = 0 + wr_flag <= 0; + rd_flag <= 0; + new_data_in_flag <= 0; + end + end + + always @(negedge cclk_in or negedge rst_intl) + if (rst_intl == 0) begin + conti_data_flag <= 0; + conti_data_cnt <= 5'b0; + cmd_wr_flag <= 0; + cmd_rd_flag <= 0; + id_error_flag <= 0; + far_maj_min_flag <= 0; + cmd_reg_new_flag <= 0; + crc_curr <= 22'b0; + crc_ck <= 0; + csbo_cnt <= 0; + csbo_flag <= 0; + downcont <= 28'b0; + rd_data_cnt <= 0; + end + else begin + if (icap_clr == 1) begin + conti_data_flag <= 0; + conti_data_cnt <= 5'b0; + cmd_wr_flag <= 0; + cmd_rd_flag <= 0; + id_error_flag <= 0; + far_maj_min_flag <= 0; + cmd_reg_new_flag <= 0; + crc_ck <= 0; + csbo_cnt <= 0; + csbo_flag <= 0; + downcont <= 28'b0; + rd_data_cnt <= 0; + end + + if (crc_reset == 1 ) begin + crc_reg <= 32'b0; + exp_sign_reg <= 32'b0; + crc_ck <= 0; + crc_curr <= 22'b0; + end + if (desynch_set || icap_desynch == 1 || crc_err_flag==1) begin + conti_data_flag <= 0; + conti_data_cnt <= 5'b0; + cmd_wr_flag <= 0; + cmd_rd_flag <= 0; + far_maj_min_flag <= 0; + cmd_reg_new_flag <= 0; + crc_ck <= 0; + csbo_cnt <= 0; + csbo_flag <= 0; + downcont <= 28'b0; + rd_data_cnt <= 0; + end + + if (new_data_in_flag==1 && wr_flag==1) begin + if (conti_data_flag == 1 ) begin + if (type2_flag == 0) begin + case (reg_addr) + 6'b000000 : if (conti_data_cnt==5'b00001) begin + crc_reg[15:0] <= pack_in_reg; + crc_ck <= 1; + end + else if (conti_data_cnt==5'b00010) begin + crc_reg[31:16] <= pack_in_reg; + crc_ck <= 0; + end + 6'b000001 : if (conti_data_cnt==5'b00010) begin + far_maj_reg <= pack_in_reg; + far_maj_min_flag <=1; + end + else if (conti_data_cnt==5'b00001) begin + if (far_maj_min_flag ==1) begin + far_min_reg <= pack_in_reg; + far_maj_min_flag <= 0; + end + else + far_maj_reg <= pack_in_reg; + end + 6'b000010 : far_min_reg <= pack_in_reg; + 6'b000011 : fdri_reg <= pack_in_reg; + 6'b000101 : cmd_reg <= pack_in_reg[4:0]; + 6'b000110 : begin + ctl_reg_tmp = (pack_in_reg & ~mask_reg) | (ctl_reg & mask_reg); + ctl_reg <= {8'b0, ctl_reg_tmp[7:0]}; + end + 6'b000111 : mask_reg <= pack_in_reg; + 6'b001001 : lout_reg <= pack_in_reg; + 6'b001010 : cor1_reg <= pack_in_reg; + 6'b001011 : cor2_reg <= pack_in_reg; + 6'b001100 : pwrdn_reg <= pack_in_reg; + 6'b001101 : flr_reg <= pack_in_reg; + 6'b001110 : + if (conti_data_cnt==5'b00001) begin + idcode_reg[15:0] <= pack_in_reg; + idcode_tmp = {idcode_reg[31:16], pack_in_reg}; + if (idcode_tmp[27:0] != DEVICE_ID[27:0]) begin + id_error_flag <= 1; + if (icap_on == 0) + $display("Error : written value to IDCODE register is %h which does not match DEVICE ID %h on SIM_CONFIG_S6 instance %m at time %t.", idcode_tmp, DEVICE_ID, $time); + else + $display("Error : written value to IDCODE register is %h which does not match DEVICE ID %h on ICAP_SPARTAN6 instance %m at time %t.", idcode_tmp, DEVICE_ID, $time); + end + else + id_error_flag <= 0; + end + else if (conti_data_cnt==5'b00010) + idcode_reg[31:16] <= pack_in_reg; + + 6'b001111 : cwdt_reg <= pack_in_reg; + 6'b010000 : hc_opt_reg[6:0] <= pack_in_reg[6:0]; + 6'b010010 : begin +// csbo_reg <= pack_in_reg; +// csbo_cnt <= pack_in_reg[4:0]; +// csbo_flag <= 1; + end + 6'b010011 : general1_reg <= pack_in_reg; + 6'b010100 : general2_reg <= pack_in_reg; + 6'b010101 : general3_reg <= pack_in_reg; + 6'b010110 : general4_reg <= pack_in_reg; + 6'b010111 : general5_reg <= pack_in_reg; + 6'b011000 : mode_reg <= pack_in_reg; + 6'b011001 : pu_gwe_reg <= pack_in_reg; + 6'b011010 : pu_gts_reg <= pack_in_reg; + 6'b011011 : mfwr_reg <= pack_in_reg; + 6'b011100 : cclk_freq_reg <= pack_in_reg; + 6'b011101 : seu_opt_reg <= pack_in_reg; + 6'b011110 : if (conti_data_cnt==5'b00001) + exp_sign_reg[15:0] <= pack_in_reg; + else if (conti_data_cnt==5'b00010) + exp_sign_reg[31:16] <= pack_in_reg; + 6'b011111 : if (conti_data_cnt==5'b00001) + rdbk_sign_reg[15:0] <= pack_in_reg; + else if (conti_data_cnt==5'b00010) + rdbk_sign_reg[31:16] <= pack_in_reg; + 6'b100001 : eye_mask_reg <= pack_in_reg; + 6'b100010 : cbc_reg <= pack_in_reg; + endcase + + if (reg_addr == 6'b000101) + cmd_reg_new_flag <= 1; + else + cmd_reg_new_flag <= 0; + + if (crc_en == 1) begin + if (reg_addr == 6'h05 && pack_in_reg[4:0] == 5'b00111) + crc_curr[21:0] = 22'b0; + else begin + if (reg_addr != 6'h04 && reg_addr != 6'h08 && reg_addr != 6'h09 && + reg_addr != 6'h12 && reg_addr != 6'h1f && + reg_addr != 6'h20 && reg_addr != 6'h00) begin + crc_input[21:0] = {reg_addr[5:0], pack_in_reg}; + crc_new[21:0] = crc_next(crc_curr, crc_input); + crc_curr[21:0] <= crc_new; + end + end + end + end + else begin // type2_flag + if (conti_data_cnt ==2) + downcont[27:16] <= pack_in_reg[11:0]; + else if (conti_data_cnt ==1) + downcont[15:0] <= pack_in_reg; + end + + if (conti_data_cnt <= 5'b00001) begin + conti_data_cnt <= 5'b0; + type2_flag <= 0; + end + else + conti_data_cnt <= conti_data_cnt - 1; + end + else begin //if (conti_data_flag == 0 ) + if ( downcont >= 1) begin + if (crc_en == 1) begin + crc_input[21:0] = {6'b000011, pack_in_reg}; //FDRI address plus data + crc_new[21:0] = crc_next(crc_curr, crc_input); + crc_curr[21:0] <= crc_new; + end + if (frame_data_wen == 1 && icap_init_done == 0) begin + $fwriteh(frame_data_fd, pack_in_reg); + $fwriteh(frame_data_fd, "\n"); + end + end + + if (pack_in_reg[15:13] == 3'b010 && downcont == 0 ) begin + cmd_wr_flag <= 0; + type2_flag <= 1; + conti_data_flag <= 1; + conti_data_cnt <= 5'b00010; + end + else if (pack_in_reg[15:13] == 3'b001) begin + if (pack_in_reg[12:11] == 2'b01 && downcont == 0) begin + if (pack_in_reg[4:0] != 5'b0) begin + cmd_rd_flag <= 1; + cmd_wr_flag <= 0; +// rd_data_cnt <= {pack_in_reg[4:0], 1'b0}; + rd_data_cnt <= 6'b000010; + conti_data_cnt <= 5'b0; + conti_data_flag = 0; + rd_reg_addr <= pack_in_reg[10:5]; + end + end + else if (pack_in_reg[12:11] == 2'b10 && downcont == 0) begin + if (pack_in_reg[15:5] == 11'b00110010010) begin // csbo reg + csbo_reg <= pack_in_reg; + csbo_cnt = pack_in_reg[4:0]; + csbo_flag <= 1; + conti_data_flag = 0; + reg_addr <= pack_in_reg[10:5]; + cmd_wr_flag <= 1; + conti_data_cnt <= 5'b0; + end + else begin + if (pack_in_reg[4:0] != 5'b0 ) begin + cmd_wr_flag <= 1; + conti_data_flag <= 1; + conti_data_cnt <= pack_in_reg[4:0]; + reg_addr <= pack_in_reg[10:5]; + end + else begin + cmd_wr_flag <= 1; + conti_data_flag <= 0; + conti_data_cnt <= 0; + reg_addr <= pack_in_reg[10:5]; + end + end + end + else begin + cmd_wr_flag <= 0; + conti_data_flag <= 0; + conti_data_cnt <= 5'b0; + end + end + cmd_reg_new_flag <= 0; + crc_ck <= 0; + end // if (conti_data_flag == 0 ) + + if (csbo_cnt != 0 ) begin + if (csbo_flag) + csbo_cnt <= csbo_cnt - 1; + end + else + csbo_flag <= 0; + + if (conti_data_cnt == 5'b00001 ) + conti_data_flag <= 0; + + end + + if (rw_en ==1) begin + if (rd_data_cnt == 1) begin + rd_data_cnt <= 0; + end + else if (rd_data_cnt == 0 && rd_flag) + cmd_rd_flag <= 0; + else if (cmd_rd_flag && rd_flag) + rd_data_cnt <= rd_data_cnt - 1; + + if (downcont >= 1 && conti_data_flag == 0 && new_data_in_flag == 1 && wr_flag == 1) + downcont <= downcont - 1; + end + + if (crc_ck== 1 || icap_init_done == 0) + crc_ck <= 0; + end + + always @(posedge cclk_in or negedge rst_intl) + if (rst_intl ==0) begin + outbus <= 16'b0; + end + else begin + if (cmd_rd_flag == 1 && rdwr_b_in == 1 && csi_b_in == 0) begin + case (rd_reg_addr) + 6'b000101 : if (buswidth == 2'b01) begin + outbus[15:8] <= 8'b0; + if (rd_data_cnt==1) + outbus[7:0] <= {3'b0, cmd_reg[4:0]}; + end + else if (buswidth == 2'b10) begin + if (rd_data_cnt==1) + outbus <= {11'b0, cmd_reg[4:0]}; + end + 6'b000110 : if (buswidth == 2'b01) begin + outbus[15:8] <= 8'b0; + if (rd_data_cnt==1) + outbus[7:0] <= ctl_reg[7:0]; + end + else if (buswidth == 2'b10) begin + if (rd_data_cnt==1) + outbus <= {8'b0, ctl_reg[7:0]}; + end + 6'b000111 : if (buswidth == 2'b01) begin + outbus[15:8] <= 8'b0; + if (rd_data_cnt==1) + outbus[7:0] <= mask_reg[7:0]; + end + else if (buswidth == 2'b10) begin + if (rd_data_cnt==1) + outbus <= {8'b0, mask_reg[7:0]}; + end + 6'b001000 : if (buswidth == 2'b01) begin + outbus[15:8] <= 8'b0; + if (rd_data_cnt==1) + outbus[7:0] <= stat_reg[7:0]; + else if (rd_data_cnt==2) + outbus[7:0] <= stat_reg[15:8]; + else if (rd_data_cnt==3) + outbus[7:0] <= stat_reg[7:0]; + else if (rd_data_cnt==4) + outbus[7:0] <= stat_reg[15:8]; + end + else if (buswidth == 2'b10) begin + if (rd_data_cnt==1) + outbus <= stat_reg[15:0]; + end + 6'b001010 : if (buswidth == 2'b01) begin + outbus[15:8] <= 8'b0; + if (rd_data_cnt==1) + outbus[7:0] <= cor1_reg[7:0]; + else if (rd_data_cnt==2) + outbus[7:0] <= cor1_reg[15:8]; + end + else if (buswidth == 2'b10) begin + if (rd_data_cnt==1) + outbus <= cor1_reg[15:0]; + end + 6'b001011 : if (buswidth == 2'b01) begin + outbus[15:8] <= 8'b0; + if (rd_data_cnt==1) + outbus[7:0] <= cor2_reg[7:0]; + else if (rd_data_cnt==2) + outbus[7:0] <= cor2_reg[15:8]; + end + else if (buswidth == 2'b10) begin + if (rd_data_cnt==1) + outbus <= cor2_reg[15:0]; + end + 6'b001100 : if (buswidth == 2'b01) begin + outbus[15:8] <= 8'b0; + if (rd_data_cnt==1) + outbus[7:0] <= pwrdn_reg[7:0]; + else if (rd_data_cnt==2) + outbus[7:0] <= pwrdn_reg[15:8]; + end + else if (buswidth == 2'b10) begin + if (rd_data_cnt==1) + outbus <= pwrdn_reg[15:0]; + end + 6'b001110 : if (buswidth == 2'b01) begin + outbus[15:8] <= 8'b0; + if (rd_data_cnt==1) + outbus[7:0] <= DEVICE_ID[7:0]; + else if (rd_data_cnt==2) + outbus[7:0] <= DEVICE_ID[15:8]; + else if (rd_data_cnt==3) + outbus[7:0] <= DEVICE_ID[23:16]; + else if (rd_data_cnt==4) + outbus[7:0] <= DEVICE_ID[31:24]; + end + else if (buswidth == 2'b10) begin + if (rd_data_cnt==1) + outbus <= DEVICE_ID[15:0]; + else if (rd_data_cnt==2) + outbus <= DEVICE_ID[31:16]; + end + 6'b001111 : if (buswidth == 2'b01) begin + outbus[15:8] <= 8'b0; + if (rd_data_cnt==1) + outbus[7:0] <= cwdt_reg[7:0]; + else if (rd_data_cnt==2) + outbus[7:0] <= cwdt_reg[15:8]; + end + else if (buswidth == 2'b10) begin + if (rd_data_cnt==1) + outbus <= cwdt_reg[15:0]; + end + 6'b010000 : if (buswidth == 2'b01) begin + outbus[15:8] <= 8'b0; + if (rd_data_cnt==1) + outbus[7:0] <= {2'b0, hc_opt_reg[5:0]}; + end + else if (buswidth == 2'b10) begin + if (rd_data_cnt==1) + outbus <= {10'b0, hc_opt_reg[5:0]}; + end + 6'b010011 : if (buswidth == 2'b01) begin + outbus[15:8] <= 8'b0; + if (rd_data_cnt==1) + outbus[7:0] <= general1_reg[7:0]; + else if (rd_data_cnt==2) + outbus[7:0] <= general1_reg[15:8]; + end + else if (buswidth == 2'b10) begin + if (rd_data_cnt==1) + outbus <= general1_reg; + end + 6'b010100 : if (buswidth == 2'b01) begin + outbus[15:8] <= 8'b0; + if (rd_data_cnt==1) + outbus[7:0] <= general2_reg[7:0]; + else if (rd_data_cnt==2) + outbus[7:0] <= general2_reg[15:8]; + end + else if (buswidth == 2'b10) begin + if (rd_data_cnt==1) + outbus <= general2_reg; + end + 6'b010101 : if (buswidth == 2'b01) begin + outbus[15:8] <= 8'b0; + if (rd_data_cnt==1) + outbus[7:0] <= general3_reg[7:0]; + else if (rd_data_cnt==2) + outbus[7:0] <= general3_reg[15:8]; + end + else if (buswidth == 2'b10) begin + if (rd_data_cnt==1) + outbus <= general3_reg; + end + 6'b010110 : if (buswidth == 2'b01) begin + outbus[15:8] <= 8'b0; + if (rd_data_cnt==1) + outbus[7:0] <= general4_reg[7:0]; + else if (rd_data_cnt==2) + outbus[7:0] <= general4_reg[15:8]; + end + else if (buswidth == 2'b10) begin + if (rd_data_cnt==1) + outbus <= general4_reg; + end + 6'b010111 : if (buswidth == 2'b01) begin + outbus[15:8] <= 8'b0; + if (rd_data_cnt==1) + outbus[7:0] <= general5_reg[7:0]; + else if (rd_data_cnt==2) + outbus[7:0] <= general5_reg[15:8]; + end + else if (buswidth == 2'b10) begin + if (rd_data_cnt==1) + outbus <= general5_reg; + end + 6'b011000 : if (buswidth == 2'b01) begin + outbus[15:8] <= 8'b0; + if (rd_data_cnt==1) + outbus[7:0] <= mode_reg[7:0]; + else if (rd_data_cnt==2) + outbus[7:0] <= mode_reg[15:8]; + end + else if (buswidth == 2'b10) begin + if (rd_data_cnt==1) + outbus <= mode_reg; + end + 6'b011101 : if (buswidth == 2'b01) begin + outbus[15:8] <= 8'b0; + if (rd_data_cnt==1) + outbus[7:0] <= seu_reg[7:0]; + else if (rd_data_cnt==2) + outbus[7:0] <= seu_reg[15:8]; + end + else if (buswidth == 2'b10) begin + if (rd_data_cnt==1) + outbus <= seu_reg; + end + 6'b011110 : if (buswidth == 2'b01) begin + outbus[15:8] <= 8'b0; + if (rd_data_cnt==1) + outbus[7:0] <= exp_sign_reg[7:0]; + else if (rd_data_cnt==2) + outbus[7:0] <= exp_sign_reg[15:8]; + else if (rd_data_cnt==3) + outbus[7:0] <= exp_sign_reg[23:16]; + else if (rd_data_cnt==4) + outbus[7:0] <= exp_sign_reg[31:24]; + end + else if (buswidth == 2'b10) begin + if (rd_data_cnt==1) + outbus <= exp_sign_reg[15:0]; + else if (rd_data_cnt==2) + outbus <= exp_sign_reg[31:16]; + end + 6'b011111 : if (buswidth == 2'b01) begin + outbus[15:8] <= 8'b0; + if (rd_data_cnt==1) + outbus[7:0] <= rdbk_sign_reg[7:0]; + else if (rd_data_cnt==2) + outbus[7:0] <= rdbk_sign_reg[15:8]; + else if (rd_data_cnt==3) + outbus[7:0] <= rdbk_sign_reg[23:16]; + else if (rd_data_cnt==4) + outbus[7:0] <= rdbk_sign_reg[31:24]; + end + else if (buswidth == 2'b10) begin + if (rd_data_cnt==1) + outbus <= rdbk_sign_reg[15:0]; + else if (rd_data_cnt==2) + outbus <= rdbk_sign_reg[31:16]; + end + 6'b100000 : if (buswidth == 2'b01) begin + outbus[15:8] <= 8'b0; + if (rd_data_cnt==1) + outbus[7:0] <= bootsts_reg[7:0]; + else if (rd_data_cnt==2) + outbus[7:0] <= bootsts_reg[15:8]; + end + else if (buswidth == 2'b10) begin + if (rd_data_cnt==1) + outbus <= bootsts_reg; + end + 6'b100001 : if (buswidth == 2'b01) begin + outbus[15:8] <= 8'b0; + if (rd_data_cnt==1) + outbus[7:0] <= eye_mask_reg[7:0]; + end + else if (buswidth == 2'b10) begin + if (rd_data_cnt==1) + outbus <= {8'b0, eye_mask_reg[7:0]}; + end + + endcase + end + else + outbus <= 16'b0; + end + + + + assign crc_rst = crc_reset | ~rst_intl; + + always @(posedge cclk_in or posedge crc_rst ) + if (crc_rst) + crc_err_flag <= 0; + else + if (crc_ck) begin + if (crc_bypass) begin + if (crc_reg[31:0] != 32'h9876defc) + crc_err_flag <= 1; + else + crc_err_flag <= 0; + end + else begin + if (crc_curr[21:0] != crc_reg[21:0]) + crc_err_flag <= 1; + else + crc_err_flag <= 0; + end + end + else + crc_err_flag <= 0; + + always @(posedge crc_err_flag or negedge rst_intl or posedge bus_sync_flag) + if (rst_intl == 0) + crc_err_flag_reg <= 0; + else if (crc_err_flag == 1) + crc_err_flag_reg <= 1; + else + crc_err_flag_reg <= 0; + + always @(posedge cclk_in or negedge rst_intl) + if (rst_intl ==0) begin + startup_set <= 0; + crc_reset <= 0; + gsr_set <= 0; + shutdown_set <= 0; + desynch_set <= 0; + reboot_set <= 0; + ghigh_b <= 0; + end + else begin + if (cmd_reg_new_flag ==1) begin + if (cmd_reg == 5'b00011) + ghigh_b <= 1; + else if (cmd_reg == 5'b01000) + ghigh_b <= 0; + + if (cmd_reg == 5'b00101) + startup_set <= 1; + if (cmd_reg == 5'b00111) + crc_reset <= 1; + if (cmd_reg == 5'b01010) + gsr_set <= 1; + if (cmd_reg == 5'b01011) + shutdown_set <= 1; + if (cmd_reg == 5'b01101) + desynch_set <= 1; + if (cmd_reg == 5'b01110) + reboot_set <= 1; + end + else begin + startup_set <= 0; + crc_reset <= 0; + gsr_set <= 0; + shutdown_set <= 0; + desynch_set <= 0; + reboot_set <= 0; + end + end + + + always @(posedge startup_set or posedge desynch_set or negedge rw_en ) + if (rw_en == 1) + begin + if (startup_set_pulse == 2'b00 && startup_set ==1) begin + if (icap_on == 0) + startup_set_pulse <= 2'b01; + else begin + startup_set_pulse <= 2'b11; + @(posedge cclk_in ) + startup_set_pulse <= 2'b00; + end + end + else if (desynch_set == 1 && startup_set_pulse == 2'b01) begin + startup_set_pulse <= 2'b11; + @(posedge cclk_in ) + startup_set_pulse <= 2'b00; + end + end + + always @(ctl_reg) begin + if (ctl_reg[3] == 1) + persist_en = 1; + else + persist_en = 0; + + if (ctl_reg[0] == 1) + gts_usr_b = 1; + else + gts_usr_b = 0; + end + + always @(cor1_reg) + begin + if (cor1_reg[2] ==1) + done_pin_drv = 1; + else + done_pin_drv = 0; + + if (cor1_reg[4] == 1) + crc_bypass = 1; + else + crc_bypass = 0; + end + + always @(cor2_reg) begin + if (cor2_reg[15] ==1) + reset_on_err = 1; + else + reset_on_err = 0; + + done_cycle_reg = cor2_reg[11:9]; + lock_cycle_reg = cor2_reg[8:6]; + gts_cycle_reg = cor2_reg[5:3]; + gwe_cycle_reg = cor2_reg[2:0]; + end + + + assign stat_reg[15] = sync_timeout; + assign stat_reg[14] = 0; + assign stat_reg[13] = DONE; + assign stat_reg[12] = INITB; + assign stat_reg[11:9] = {1'b0, mode_pin_in}; + assign stat_reg[8:6] = 3'b0; + assign stat_reg[5] = ghigh_b; + assign stat_reg[4] = gwe_out; + assign stat_reg[3] = gts_out; + assign stat_reg[2] = 1'bx; + assign stat_reg[1] = id_error_flag; + assign stat_reg[0] = crc_err_flag_reg; + + + always @(posedge cclk_in or negedge rst_intl) + if (rst_intl == 0) begin + st_state <= STARTUP_PH0; + startup_begin_flag <= 0; + startup_end_flag <= 0; + end + else begin + if (nx_st_state == STARTUP_PH1) begin + startup_begin_flag <= 1; + startup_end_flag <= 0; + end + else if (st_state == STARTUP_PH7) begin + startup_end_flag <= 1; + startup_begin_flag <= 0; + end + if (lock_cycle_reg == 3'b111 || pll_locked == 1 || (st_state != lock_cycle_reg && pll_locked == 0)) begin + st_state <= nx_st_state; + end + else + st_state <= st_state; + end + + always @(st_state or startup_set_pulse or DONE ) + if (( st_state == done_cycle_reg) && (DONE != 0) || ( st_state != done_cycle_reg)) + case (st_state) + STARTUP_PH0 : if (startup_set_pulse == 2'b11 ) + nx_st_state = STARTUP_PH1; + else + nx_st_state = STARTUP_PH0; + STARTUP_PH1 : nx_st_state = STARTUP_PH2; + + STARTUP_PH2 : nx_st_state = STARTUP_PH3; + + STARTUP_PH3 : nx_st_state = STARTUP_PH4; + + STARTUP_PH4 : nx_st_state = STARTUP_PH5; + + STARTUP_PH5 : nx_st_state = STARTUP_PH6; + + STARTUP_PH6 : nx_st_state = STARTUP_PH7; + + STARTUP_PH7 : nx_st_state = STARTUP_PH0; + endcase + + always @(posedge cclk_in or negedge rst_intl ) + if (rst_intl == 0) begin + gwe_out <= 0; + gts_out <= 1; + eos_startup <= 0; + gsr_st_out <= 1; + done_o <= 0; + end + else begin + + if ((nx_st_state == done_cycle_reg) || (st_state == done_cycle_reg)) + if (DONE != 0 || done_pin_drv == 1) + done_o <= 1'b1; + else + done_o <= 1'bz; + + if (nx_st_state == gwe_cycle_reg) begin + gwe_out <= 1; + end + + if (nx_st_state == gts_cycle_reg) begin + gts_out <= 0; + end + + if (nx_st_state == STARTUP_PH6) + gsr_st_out <= 0; + + if (nx_st_state == STARTUP_PH7) + eos_startup <= 1; + + end + + + assign gsr_out = gsr_st_out | gsr_cmd_out; + + always @(posedge rdwr_b_in or negedge rst_intl or + posedge abort_flag_rst or posedge csi_b_in) + if (rst_intl==0 || abort_flag_rst==1 || csi_b_in == 1) + abort_flag_wr <= 0; + else + if (abort_dis == 0 && csi_b_in == 0) begin + if ($time != 0) begin + abort_flag_wr <= 1; + if (icap_on == 0) + $display(" Warning : RDWRB changes when CS_B low, which causes Configuration abort on SIM_CONFIG_S6 instance %m at time %t.", $time); + end + end + else + abort_flag_wr <= 0; + + always @( negedge rdwr_b_in or negedge rst_intl or posedge abort_flag_rst or posedge csi_b_in) + if (rst_intl==0 || csi_b_in == 1 || abort_flag_rst==1) + abort_flag_rd <= 0; + else + if (abort_dis == 0 && csi_b_in == 0) begin + if ($time != 0) begin + abort_flag_rd <= 1; + if (icap_on == 0) + $display(" Warning : RDWRB changes when CS_B low, which causes Configuration abort on SIM_CONFIG_S6 instance %m at time %t.", $time); + end + end + else + abort_flag_rd <= 0; + + assign abort_flag = abort_flag_wr | abort_flag_rd; + + + always @(posedge cclk_in or negedge rst_intl) + if (rst_intl == 0) begin + abort_cnt <= 0; + abort_out_en <= 0; + end + else begin + if ( abort_flag ==1 ) begin + if (abort_cnt < 4) begin + abort_cnt <= abort_cnt + 1; + abort_out_en <= 1; + end + else + abort_flag_rst <= 1; + end + else begin + abort_cnt <= 0; + abort_out_en <= 0; + abort_flag_rst <= 0; + end + + if (abort_cnt== 0) + abort_status <= {cfgerr_b_flag, bus_sync_flag, 1'b0, 1'b1, 12'b1111}; + else if (abort_cnt== 1) + abort_status <= {cfgerr_b_flag, 1'b1, 1'b0, 1'b0, 12'b1111}; + else if (abort_cnt== 2) + abort_status <= {cfgerr_b_flag, 1'b0, 1'b0, 1'b0, 12'b1111}; + else if (abort_cnt== 3) + abort_status <= {cfgerr_b_flag, 1'b0, 1'b0, 1'b1, 12'b1111}; + + end + + + +function [21:0] crc_next; + input [21:0] crc_curr; + input [21:0] crc_input; + integer i_crc; + begin + for(i_crc = 21; i_crc > 15; i_crc=i_crc -1) + crc_next[i_crc] = crc_curr[i_crc-1] ^ crc_input[i_crc]; + + crc_next[15] = crc_curr[14] ^ crc_input[15] ^ crc_curr[21]; + + for(i_crc = 14; i_crc > 12; i_crc=i_crc -1) + crc_next[i_crc] = crc_curr[i_crc-1] ^ crc_input[i_crc]; + + crc_next[12] = crc_curr[11] ^ crc_input[12] ^ crc_curr[21]; + + for(i_crc = 11; i_crc > 7; i_crc=i_crc -1) + crc_next[i_crc] = crc_curr[i_crc-1] ^ crc_input[i_crc]; + + crc_next[7] = crc_curr[6] ^ crc_input[7] ^ crc_curr[21]; + + for(i_crc = 6; i_crc > 0; i_crc=i_crc -1) + crc_next[i_crc] = crc_curr[i_crc-1] ^ crc_input[i_crc]; + + crc_next[0] = crc_input[0] ^ crc_curr[21]; + + end +endfunction + +function [7:0] bit_revers8; + input [7:0] din8; + begin + bit_revers8[0] = din8[7]; + bit_revers8[1] = din8[6]; + bit_revers8[2] = din8[5]; + bit_revers8[3] = din8[4]; + bit_revers8[4] = din8[3]; + bit_revers8[5] = din8[2]; + bit_revers8[6] = din8[1]; + bit_revers8[7] = din8[0]; + end +endfunction + + + +endmodule diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/SIM_CONFIG_S6_SERIAL.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/SIM_CONFIG_S6_SERIAL.v new file mode 100644 index 0000000..9e2843b --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/SIM_CONFIG_S6_SERIAL.v @@ -0,0 +1,831 @@ +// Copyright (c) 1995/2005 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Function Simulation Library Component +// / / Configuration Simulation Model +// /___/ /\ Filename : SIM_CONFIG_S6_SERIAL.v +// \ \ / \ Timestamp : +// \___\/\___\ +// +// Revision: +// 03/22/09 - Initial version of serial configuration simulation model for +// Spartann6. +// 11/25/09 - Fix CRC (CR538766) +// 02/24/10 - Change Tprog to 500 ns (CR550552) +// 03/03/10 - set mode_sample_flag to 0 when mode pin set wrong (CR552316) +// End Revision +//////////////////////////////////////////////////////////////////////////////// + +`timescale 1 ps / 1 ps + +module SIM_CONFIG_S6_SERIAL ( + DONE, + CCLK, + DIN, + INITB, + M, + PROGB + ); + + inout DONE; + input CCLK; + input DIN; + inout INITB; + input [1:0] M; + input PROGB; + + parameter DEVICE_ID = 32'h0; + + localparam cfg_Tprog = 500000; // min PROG must be low, 300 ns + localparam cfg_Tpl = 100000; // max program latency us. + localparam STARTUP_PH0 = 3'b000; + localparam STARTUP_PH1 = 3'b001; + localparam STARTUP_PH2 = 3'b010; + localparam STARTUP_PH3 = 3'b011; + localparam STARTUP_PH4 = 3'b100; + localparam STARTUP_PH5 = 3'b101; + localparam STARTUP_PH6 = 3'b110; + localparam STARTUP_PH7 = 3'b111; + + wire GSR, GTS, GWE; + wire cclk_in; + wire init_b_in; + wire prog_b_in; + wire crc_err_flag_tot; + reg crc_err_flag_reg = 0; + reg mode_sample_flag = 0; + reg init_b_p = 1; + reg done_o = 0; + tri1 p_up; + + triand (weak1, strong0) INITB=(mode_sample_flag) ? ~crc_err_flag_tot : init_b_p; + triand (weak1, strong0) DONE=done_o; + + assign DONE = p_up; + assign INITB = p_up; + + wire done_in; + reg por_b; + wire [1:0] m_in; + reg [2:0] mode_pin_in = 3'b0; + wire [15:0] d_in; + wire [15:0] d_out; + + assign glbl.GSR = GSR; + assign glbl.GTS = GTS; +// assign glbl.GWE = GWE; + wire d_out_en; + wire init_b_t; + wire prog_b_t; + wire crc_rst; + + buf buf_cclk (cclk_in, CCLK); + + buf buf_din (ds_in, DIN); +// buf buf_dout (DOUT, ds_out); + buf buf_init (init_b_in, INITB); + buf buf_m_0 (m_in[0], M[0]); + buf buf_m_1 (m_in[1], M[1]); + buf buf_prog (prog_b_in, PROGB); + + time prog_pulse_low_edge = 0; + time prog_pulse_low = 0; + integer wr_cnt = 0; + reg [4:0] csbo_cnt = 5'b0; + reg csbo_flag = 0; + reg dcm_locked = 1; + reg [4:0] conti_data_cnt = 5'b0; + reg [5:0] rd_data_cnt = 6'b0; + reg [15:0] pack_in_reg = 16'b0; + reg [5:0] reg_addr; + reg [5:0] rd_reg_addr; + reg new_data_in_flag = 0; + reg wr_flag = 1; + reg rd_flag = 0; + reg cmd_wr_flag = 0; + reg cmd_rd_flag = 0; + reg bus_sync_flag = 0; + reg [1:0] buswidth = 2'b00; + reg rd_sw_en = 0; + reg conti_data_flag = 0; + reg conti_data_flag_set = 0; + reg [2:0] st_state = STARTUP_PH0; + reg startup_begin_flag = 0; + reg startup_end_flag = 0; + reg cmd_reg_new_flag = 0; + reg far_maj_min_flag = 0; + reg crc_reset = 0; + reg crc_ck = 0; + reg crc_err_flag = 0; + wire crc_en, desync_flag; + reg [21:0] crc_curr = 22'b0; + reg [21:0] crc_new = 22'b0; + reg [21:0] crc_input = 22'b0; + reg gwe_out = 0; + reg gts_out = 1; + reg reboot_set = 0; + reg gsr_set = 0; + reg gts_usr_b = 1; + reg done_pin_drv = 0; + reg crc_bypass = 0; + reg reset_on_err = 0; + reg sync_timeout = 0; + reg [31:0] crc_reg, idcode_reg, idcode_tmp; + reg [15:0] far_maj_reg; + reg [15:0] far_min_reg; + reg [15:0] fdri_reg; + reg [15:0] fdro_reg; + reg [15:0] cwdt_reg; + reg [15:0] ctl_reg = 8'b10000001; + reg [4:0] cmd_reg; + reg [15:0] general1_reg; + reg [15:0] mask_reg = 8'b0; + reg [15:0] lout_reg, flr_reg; + reg [15:0] cor1_reg = 16'b0x11011100000000; + reg [15:0] cor2_reg = 16'b0000100111101110; + reg [15:0] pwrdn_reg = 16'bx00010001000x001; + reg [15:0] snowplow_reg; + reg [15:0] hc_opt_reg; + reg [15:0] csbo_reg; + reg [15:0] general2_reg; + reg [15:0] mode_reg; + reg [15:0] general3_reg; + reg [15:0] general4_reg; + reg [15:0] general5_reg; + reg [15:0] eye_mask_reg; + reg [15:0] cbc_reg; + reg [15:0] seu_reg; + reg [15:0] bootsts_reg; + reg [15:0] pu_gwe_reg; + reg [15:0] pu_gts_reg; + reg [15:0] mfwr_reg; + reg [15:0] cclk_freq_reg; + reg [15:0] seu_opt_reg; + reg [31:0] exp_sign_reg; + reg [15:0] rdbk_sign_reg; + + reg shutdown_set = 0; + reg desynch_set = 0; + reg [2:0] done_cycle_reg = 3'b100; + reg [2:0] gts_cycle_reg = 3'b101; + reg [2:0] gwe_cycle_reg=3'b110; + reg [2:0] nx_st_state = 3'b000; + reg ghigh_b = 0; + reg eos_startup = 0; + reg startup_set = 0; + reg [1:0] startup_set_pulse = 2'b0; + reg [7:0] tmp_byte; + reg [7:0] tmp_byte1; + reg [7:0] tmp_byte2; + reg [7:0] tmp_byte3; + reg [7:0] tmp_byte4; + reg [7:0] tmp_byte5; + reg [7:0] tmp_byte6; + reg [7:0] tmp_byte7; + reg [15:0] tmp_word; + reg [7:0] ctl_reg_tmp; + reg id_error_flag = 0; + reg iprog_b = 1; + reg persist_en = 0; + reg rst_sync = 0; + reg [2:0] lock_cycle_reg = 3'b0; + reg rbcrc_no_pin = 0; + reg gsr_st_out = 1; + reg gsr_cmd_out = 0; + wire [15:0] stat_reg; + wire rst_intl; + wire rw_en; + wire gsr_out; + wire cfgerr_b_flag; + reg [27:0] downcont = 28'b0; + reg type2_flag = 0; + reg rst_en=1, prog_b_a=1; + reg [31:0] tmp_dword1; + reg [31:0] tmp_dword2; + integer wr_bit_addr; + + initial begin + if (DEVICE_ID == 32'h0) begin + $display("Attribute Error : The attribute DEVICE_ID on SIM_CONFIG_S6_SERIAL instance %m is not set."); + end + end + + + assign GSR = gsr_out; + assign GTS = gts_out; + assign GWE = gwe_out; + assign cfgerr_b_flag = rw_en & ~crc_err_flag_tot; + assign crc_err_flag_tot = id_error_flag | crc_err_flag_reg; + assign crc_en = 1; + assign done_in = DONE; + + assign init_b_t = init_b_in; + + always @( negedge prog_b_in) begin + rst_en = 0; + rst_en <= #cfg_Tprog 1; + end + + always @( posedge rst_en or posedge prog_b_in ) + if (rst_en == 1) begin + if (prog_b_in == 0 ) + init_b_p <= 0; + else + init_b_p <= #(cfg_Tpl) 1; + end + + always @( rst_en or prog_b_in or prog_pulse_low) + if (rst_en == 1) begin + if (prog_pulse_low == cfg_Tprog) begin + prog_b_a = 0; + prog_b_a <= #500 1; + end + else + prog_b_a = prog_b_in; + end + else + prog_b_a = 1; + + initial begin + por_b = 0; + por_b = #400000 1; + end + + assign prog_b_t = prog_b_a & iprog_b & por_b; + + assign rst_intl = (prog_b_t == 0 ) ? 0 : 1; + + + always @( init_b_t or prog_b_t) + if (prog_b_t == 0) + mode_sample_flag <= 0; + else if (init_b_t && mode_sample_flag == 0) begin + if (prog_b_t == 1) begin + mode_pin_in <= m_in; + if (m_in != 2'b11) begin + mode_sample_flag <= 0; + $display("Error: input M is %h. Only Slave Serial mode M=11 supported on SIM_CONFIG_S6_SERIAL instance %m.", m_in); + end + else + mode_sample_flag <= #1 1; + end + end + + always @(posedge init_b_t ) + if (prog_b_t != 1) begin + if ($time != 0 ) + $display("Error: PROGB is not high when INITB goes high on SIM_CONFIG_S6_SERIAL instance %m at time %t.", $time); + end + + always @(m_in) + if (mode_sample_flag == 1 && persist_en == 1) + $display("Error : Mode pine M[2:0] changed after rising edge of INITB on SIM_CONFIG_S6_SERIAL instance %m at time %t.", $time); + + always @(posedge prog_b_in or negedge prog_b_in) + if (prog_b_in == 0) + prog_pulse_low_edge <= $time; + else if (prog_b_in == 1 && $time > 0) begin + prog_pulse_low = $time - prog_pulse_low_edge; + if (prog_pulse_low < cfg_Tprog ) + $display("Error: Low time of PROGB is less than required minimum Tprogram time %d on SIM_CONFIG_S6_SERIAL instance %m at time %t.", cfg_Tprog, $time); + end + + assign rw_en = (mode_sample_flag == 1 && done_o === 0) ? 1 : 0; + assign desync_flag = ~rst_intl | desynch_set | crc_err_flag | id_error_flag; + + always @(posedge cclk_in or posedge desync_flag) + if (desync_flag == 1) begin + pack_in_reg <= 16'b0; + new_data_in_flag <= 0; + bus_sync_flag <= 0; + wr_cnt <= 0; + wr_flag <= 1; + tmp_dword1 <= 32'b0; + tmp_dword2 <= 32'b0; + end + else begin + if (rw_en == 1 ) begin + if (bus_sync_flag == 0) begin + tmp_dword1 = { tmp_dword2[30:0], ds_in}; + if (tmp_dword1[31:0] == 32'hAA995566) begin + bus_sync_flag <= 1; + new_data_in_flag <= 0; + tmp_dword2 <= 32'b0; + pack_in_reg <= 16'b0; + wr_cnt <= 0; + end + else begin + tmp_dword2 <= tmp_dword1; + end + end + else begin + pack_in_reg <= {pack_in_reg[14:0], ds_in}; + if (wr_cnt == 15) begin + new_data_in_flag <= 1; + wr_cnt <= 0; + end + else begin + new_data_in_flag <= 0; + wr_cnt <= wr_cnt + 1; + end + end + end + else begin //rw_en = 0 + new_data_in_flag <= 0; + end + end + + always @(negedge cclk_in or negedge rst_intl) + if (rst_intl == 0) begin + conti_data_flag <= 0; + conti_data_cnt <= 5'b0; + cmd_wr_flag <= 0; + cmd_rd_flag <= 0; + id_error_flag <= 0; + far_maj_min_flag <= 0; + cmd_reg_new_flag <= 0; + crc_curr <= 22'b0; + crc_ck <= 0; + csbo_cnt <= 0; + csbo_flag <= 0; + downcont <= 28'b0; + rd_data_cnt <= 0; + end + else begin + if (crc_reset == 1 ) begin + crc_reg <= 32'b0; + exp_sign_reg <= 32'b0; + crc_ck <= 0; + crc_curr <= 22'b0; + end + if (desynch_set == 1 || crc_err_flag==1) begin + conti_data_flag <= 0; + conti_data_cnt <= 5'b0; + cmd_wr_flag <= 0; + cmd_rd_flag <= 0; + far_maj_min_flag <= 0; + cmd_reg_new_flag <= 0; + crc_ck <= 0; + csbo_cnt <= 0; + csbo_flag <= 0; + downcont <= 28'b0; + rd_data_cnt <= 0; + end + + if (new_data_in_flag == 1 && wr_flag == 1) begin + if (conti_data_flag == 1 ) begin + if (type2_flag == 0) begin + case (reg_addr) + 6'b000000 : if (conti_data_cnt == 5'b00001) begin + crc_reg[15:0] <= pack_in_reg; + crc_ck <= 1; + end + else if (conti_data_cnt == 5'b00010) begin + crc_reg[31:16] <= pack_in_reg; + crc_ck <= 0; + end + 6'b000001 : if (conti_data_cnt == 5'b00010) begin + far_maj_reg <= pack_in_reg; + far_maj_min_flag <=1; + end + else if (conti_data_cnt == 5'b00001) begin + if (far_maj_min_flag ==1) begin + far_min_reg <= pack_in_reg; + far_maj_min_flag <= 0; + end + else + far_maj_reg <= pack_in_reg; + end + 6'b000010 : far_min_reg <= pack_in_reg; + 6'b000011 : fdri_reg <= pack_in_reg; + 6'b000101 : cmd_reg <= pack_in_reg[4:0]; + 6'b000110 : begin + ctl_reg_tmp = (pack_in_reg & ~mask_reg) | (ctl_reg & mask_reg); + ctl_reg <= {8'b0, ctl_reg_tmp[7:0]}; + end + 6'b000111 : mask_reg <= pack_in_reg; + 6'b001001 : lout_reg <= pack_in_reg; + 6'b001010 : cor1_reg <= pack_in_reg; + 6'b001011 : cor2_reg <= pack_in_reg; + 6'b001100 : pwrdn_reg <= pack_in_reg; + 6'b001101 : flr_reg <= pack_in_reg; + 6'b001110 : + if (conti_data_cnt == 5'b00001) begin + idcode_reg[15:0] <= pack_in_reg; + idcode_tmp = {idcode_reg[31:16], pack_in_reg}; + if (idcode_tmp[27:0] != DEVICE_ID[27:0]) begin + id_error_flag <= 1; + $display("Error : written value to IDCODE register is %h which does not match DEVICE ID %h on SIM_CONFIG_S6_SERIAL instance %m at time %t.", idcode_tmp, DEVICE_ID, $time); + end + else + id_error_flag <= 0; + end + else if (conti_data_cnt == 5'b00010) + idcode_reg[31:16] <= pack_in_reg; + + 6'b001111 : cwdt_reg <= pack_in_reg; + 6'b010000 : hc_opt_reg[6:0] <= pack_in_reg[6:0]; + 6'b010011 : general1_reg <= pack_in_reg; + 6'b010100 : general2_reg <= pack_in_reg; + 6'b010101 : general3_reg <= pack_in_reg; + 6'b010110 : general4_reg <= pack_in_reg; + 6'b010111 : general5_reg <= pack_in_reg; + 6'b011000 : mode_reg <= pack_in_reg; + 6'b011001 : pu_gwe_reg <= pack_in_reg; + 6'b011010 : pu_gts_reg <= pack_in_reg; + 6'b011011 : mfwr_reg <= pack_in_reg; + 6'b011100 : cclk_freq_reg <= pack_in_reg; + 6'b011101 : seu_opt_reg <= pack_in_reg; + 6'b011110 : if (conti_data_cnt == 5'b00001) + exp_sign_reg[15:0] <= pack_in_reg; + else if (conti_data_cnt == 5'b00010) + exp_sign_reg[31:16] <= pack_in_reg; + 6'b011111 : if (conti_data_cnt == 5'b00001) + rdbk_sign_reg[15:0] <= pack_in_reg; + else if (conti_data_cnt == 5'b00010) + rdbk_sign_reg[31:16] <= pack_in_reg; + 6'b100001 : eye_mask_reg <= pack_in_reg; + 6'b100010 : cbc_reg <= pack_in_reg; + endcase + + if (reg_addr == 6'b000101) + cmd_reg_new_flag <= 1; + else + cmd_reg_new_flag <= 0; + + if (crc_en == 1) begin + if (reg_addr == 6'h05 && pack_in_reg[4:0] == 5'b00111) + crc_curr[21:0] = 22'b0; + else begin + if (reg_addr != 6'h04 && reg_addr != 6'h08 && reg_addr != 6'h09 && + reg_addr != 6'h12 && reg_addr != 6'h1f && + reg_addr != 6'h20 && reg_addr != 6'h00) begin + + crc_input[21:0] = {reg_addr[5:0], pack_in_reg}; + crc_new[21:0] = crc_next(crc_curr, crc_input); + crc_curr[21:0] <= crc_new; + end + end + end + end + else begin // type2_flag + if (conti_data_cnt == 2) + downcont[27:16] <= pack_in_reg[11:0]; + else if (conti_data_cnt ==1) + downcont[15:0] <= pack_in_reg; + end + + if (conti_data_cnt <= 5'b00001) begin + conti_data_cnt <= 5'b0; + type2_flag <= 0; + end + else + conti_data_cnt <= conti_data_cnt - 1; + end + else begin //if (conti_data_flag == 0 ) + if ( downcont >= 1) begin + if (crc_en == 1) begin + crc_input[21:0] = {6'b000011, pack_in_reg}; //FDRI address plus data + crc_new[21:0] = crc_next(crc_curr, crc_input); + crc_curr[21:0] <= crc_new; + end + end + + if (pack_in_reg[15:13] == 3'b010 && downcont == 0 ) begin +// $display("Warning : only Type 1 Packet supported on SIM_CONFIG_S6_SERIAL instance %m at time %t.", $time); + cmd_wr_flag <= 0; + type2_flag <= 1; + conti_data_flag <= 1; + conti_data_cnt <= 5'b00010; + end + else if (pack_in_reg[15:13] == 3'b001 ) begin + if (pack_in_reg[12:11] == 2'b01 && downcont == 0) begin + if (pack_in_reg[4:0] != 5'b0) begin + cmd_rd_flag <= 1; + cmd_wr_flag <= 0; +// rd_data_cnt <= {pack_in_reg[4:0], 1'b0}; + rd_data_cnt <= 6'b000100; + conti_data_cnt <= 5'b0; + conti_data_flag = 0; + rd_reg_addr <= pack_in_reg[10:5]; + end + end + else if (pack_in_reg[12:11] == 2'b10 && downcont == 0) begin + if (pack_in_reg[15:5] == 11'b00110010010) begin // csbo reg + csbo_reg <= pack_in_reg; + csbo_cnt = pack_in_reg[4:0]; + csbo_flag <= 1; + conti_data_flag = 0; + reg_addr <= pack_in_reg[10:5]; + cmd_wr_flag <= 1; + conti_data_cnt <= 5'b0; + end + else if (pack_in_reg[4:0] != 5'b0 ) begin + cmd_wr_flag <= 1; + conti_data_flag <= 1; + conti_data_cnt <= pack_in_reg[4:0]; + reg_addr <= pack_in_reg[10:5]; + end + end + else begin + cmd_wr_flag <= 0; + conti_data_flag <= 0; + conti_data_cnt <= 5'b0; + end + end + cmd_reg_new_flag <= 0; + crc_ck <= 0; + end // if (conti_data_flag == 0 ) + + if (csbo_cnt != 0 ) begin + if (csbo_flag) + csbo_cnt <= csbo_cnt - 1; + end + else + csbo_flag <= 0; + + if (conti_data_cnt == 5'b00001 ) + conti_data_flag <= 0; + + end + + if (rw_en == 1) begin + if (rd_data_cnt == 1) begin + rd_data_cnt <= 0; + end + else if (rd_data_cnt == 0 && rd_flag == 1) + cmd_rd_flag <= 0; + else if (cmd_rd_flag == 1 && rd_flag == 1) + rd_data_cnt <= rd_data_cnt - 1; + + if (downcont >= 1 && conti_data_flag == 0 && new_data_in_flag == 1 && wr_flag == 1) + downcont <= downcont - 1; + end + if (crc_ck == 1) + crc_ck <= 0; + end + + assign crc_rst = crc_reset | ~rst_intl; + + always @(posedge cclk_in or posedge crc_rst ) + if (crc_rst == 1) + crc_err_flag <= 0; + else + if (crc_ck == 1) begin + if (crc_bypass == 1) begin + if (crc_reg[31:0] != 32'h9876defc) + crc_err_flag <= 1; + else + crc_err_flag <= 0; + end + else begin + if (crc_curr[21:0] != crc_reg[21:0]) + crc_err_flag <= 1; + else + crc_err_flag <= 0; + end + end + else + crc_err_flag <= 0; + + always @(posedge crc_err_flag or negedge rst_intl or posedge bus_sync_flag) + if (rst_intl == 0) + crc_err_flag_reg <= 0; + else if (crc_err_flag == 1) + crc_err_flag_reg <= 1; + else + crc_err_flag_reg <= 0; + + always @(posedge cclk_in or negedge rst_intl) + if (rst_intl == 0) begin + startup_set <= 0; + crc_reset <= 0; + gsr_set <= 0; + shutdown_set <= 0; + desynch_set <= 0; + reboot_set <= 0; + ghigh_b <= 0; + end + else begin + if (cmd_reg_new_flag == 1) begin + if (cmd_reg == 5'b00011) + ghigh_b <= 1; + else if (cmd_reg == 5'b01000) + ghigh_b <= 0; + + if (cmd_reg == 5'b00101) + startup_set <= 1; + if (cmd_reg == 5'b00111) + crc_reset <= 1; + if (cmd_reg == 5'b01010) + gsr_set <= 1; + if (cmd_reg == 5'b01011) + shutdown_set <= 1; + if (cmd_reg == 5'b01101) + desynch_set <= 1; + if (cmd_reg == 5'b01110) + reboot_set <= 1; + end + else begin + startup_set <= 0; + crc_reset <= 0; + gsr_set <= 0; + shutdown_set <= 0; + desynch_set <= 0; + reboot_set <= 0; + end + end + + + always @(posedge startup_set or posedge desynch_set or negedge rw_en ) + if (rw_en == 0) + startup_set_pulse <= 2'b0; + else begin + if (startup_set_pulse == 2'b00 && startup_set ==1) + startup_set_pulse <= 2'b01; + else if (desynch_set == 1 && startup_set_pulse == 2'b01) begin + startup_set_pulse <= 2'b11; + @(posedge cclk_in ) + startup_set_pulse <= 2'b00; + end + end + always @(ctl_reg) begin + if (ctl_reg[3] == 1) + persist_en = 1; + else + persist_en = 0; + + if (ctl_reg[0] == 1) + gts_usr_b = 1; + else + gts_usr_b = 0; + end + + always @(cor1_reg) + begin + if (cor1_reg[2] ==1) + done_pin_drv = 1; + else + done_pin_drv = 0; + + if (cor1_reg[4] == 1) + crc_bypass = 1; + else + crc_bypass = 0; + end + + always @(cor2_reg) begin + if (cor2_reg[15] ==1) + reset_on_err = 1; + else + reset_on_err = 0; + + done_cycle_reg = cor2_reg[11:9]; + lock_cycle_reg = cor2_reg[8:6]; + gts_cycle_reg = cor2_reg[5:3]; + gwe_cycle_reg = cor2_reg[2:0]; + end + + + assign stat_reg[15] = sync_timeout; + assign stat_reg[14] = 0; + assign stat_reg[13] = DONE; + assign stat_reg[12] = INITB; + assign stat_reg[11:9] = {1'b0, mode_pin_in}; + assign stat_reg[8:6] = 3'b0; + assign stat_reg[5] = ghigh_b; + assign stat_reg[4] = gwe_out; + assign stat_reg[3] = gts_out; + assign stat_reg[2] = 1'bx; + assign stat_reg[1] = id_error_flag; + assign stat_reg[0] = crc_err_flag_reg; + + + always @(posedge cclk_in or negedge rst_intl) + if (rst_intl == 0) begin + st_state <= STARTUP_PH0; + startup_begin_flag <= 0; + startup_end_flag <= 0; + end + else begin + if (nx_st_state == STARTUP_PH1) begin + startup_begin_flag <= 1; + startup_end_flag <= 0; + end + else if (st_state == STARTUP_PH7) begin + startup_end_flag <= 1; + startup_begin_flag <= 0; + end + if (lock_cycle_reg == 3'b111 || dcm_locked == 1 || st_state != lock_cycle_reg) begin + st_state <= nx_st_state; + end + else + st_state <= st_state; + end + + always @(st_state or startup_set_pulse or DONE ) + if (( st_state == done_cycle_reg) && (DONE != 0) || ( st_state != done_cycle_reg)) + case (st_state) + STARTUP_PH0 : if (startup_set_pulse == 2'b11 ) + nx_st_state = STARTUP_PH1; + else + nx_st_state = STARTUP_PH0; + STARTUP_PH1 : nx_st_state = STARTUP_PH2; + + STARTUP_PH2 : nx_st_state = STARTUP_PH3; + + STARTUP_PH3 : nx_st_state = STARTUP_PH4; + + STARTUP_PH4 : nx_st_state = STARTUP_PH5; + + STARTUP_PH5 : nx_st_state = STARTUP_PH6; + + STARTUP_PH6 : nx_st_state = STARTUP_PH7; + + STARTUP_PH7 : nx_st_state = STARTUP_PH0; + endcase + + always @(posedge cclk_in or negedge rst_intl ) + if (rst_intl == 0) begin + gwe_out <= 0; + gts_out <= 1; + eos_startup <= 0; + gsr_st_out <= 1; + done_o <= 0; + end + else begin + + if ((nx_st_state == done_cycle_reg) || (st_state == done_cycle_reg)) + if (DONE != 0 || done_pin_drv == 1) + done_o <= 1'b1; + else + done_o <= 1'bz; + + if (nx_st_state == gwe_cycle_reg) begin + gwe_out <= 1; + end + + if (nx_st_state == gts_cycle_reg) begin + gts_out <= 0; + end + + if (nx_st_state == STARTUP_PH6) + gsr_st_out <= 0; + + if (nx_st_state == STARTUP_PH7) + eos_startup <= 1; + + end + + + assign gsr_out = gsr_st_out | gsr_cmd_out; + +function [21:0] crc_next; + input [21:0] crc_curr; + input [21:0] crc_input; + integer i_crc; + begin + for(i_crc = 21; i_crc > 15; i_crc=i_crc -1) + crc_next[i_crc] = crc_curr[i_crc-1] ^ crc_input[i_crc]; + + crc_next[15] = crc_curr[14] ^ crc_input[15] ^ crc_curr[21]; + + for(i_crc = 14; i_crc > 12; i_crc=i_crc -1) + crc_next[i_crc] = crc_curr[i_crc-1] ^ crc_input[i_crc]; + + crc_next[12] = crc_curr[11] ^ crc_input[12] ^ crc_curr[21]; + + for(i_crc = 11; i_crc > 7; i_crc=i_crc -1) + crc_next[i_crc] = crc_curr[i_crc-1] ^ crc_input[i_crc]; + + crc_next[7] = crc_curr[6] ^ crc_input[7] ^ crc_curr[21]; + + for(i_crc = 6; i_crc > 0; i_crc=i_crc -1) + crc_next[i_crc] = crc_curr[i_crc-1] ^ crc_input[i_crc]; + + crc_next[0] = crc_input[0] ^ crc_curr[21]; + + end +endfunction + +function [7:0] bit_revers8; + input [7:0] din8; + begin + bit_revers8[0] = din8[7]; + bit_revers8[1] = din8[6]; + bit_revers8[2] = din8[5]; + bit_revers8[3] = din8[4]; + bit_revers8[4] = din8[3]; + bit_revers8[5] = din8[2]; + bit_revers8[6] = din8[1]; + bit_revers8[7] = din8[0]; + end +endfunction + + + +endmodule diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/SIM_CONFIG_V5.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/SIM_CONFIG_V5.v new file mode 100644 index 0000000..1958646 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/SIM_CONFIG_V5.v @@ -0,0 +1,1223 @@ +////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2005 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Function Simulation Library Component +// / / Configuration Simulation Model +// /___/ /\ Filename : SIM_CONFIG_V5.v +// \ \ / \ Timestamp : +// \___\/\___\ +// +// Revision: +// 07/10/06 - Initial version. +// 01/04/07 - Add downcont to skip type2 data. +// 01/05/07 - Add INITB output function. +// 01/15/07 - Modify GSR, GTS and GWE generation. +// 01/18/07 - Change startup state machine running after DESYNC command. +// 02/01/07 - PROGB low pulse less than 300 ns will not cause reset. +// Make INITB output before mode pin sampled. +// 02/06/07 - Make INITB to open-drain output. +// 02/08/07 - Use bit_revers8 for 16 bit mode by swaping bytely. +// Add power on reset por_b; +// 02/20/07 - Generate INITB out for iprob_b also. Add INITB pin strength. +// 04/18/07 - Remove _ from port name. +// 06/04/07 - Add wire declaration to internal signal. +// 06/19/07 - Add LOC parameter to simprim model (CR 441956). +// 07/30/07 - reset init_b_out when iprob_b high for internal reset. +// 07/15/08 - Change readback data from byte to same as write width.(CR477214) +// 01/12/10 - Reverse bits for readback (CR544212) +// 05/19/10 - Not reset startup_set_pulse when rw_en=0 (CR559852) +// End Revision +//////////////////////////////////////////////////////////////////////////////// + +`timescale 1 ps / 1 ps + +module SIM_CONFIG_V5 ( BUSY, + CSOB, + DONE, + CCLK, + CSB, + D, + DCMLOCK, + INITB, + M, + PROGB, + RDWRB + ); + + output BUSY; + output CSOB; + inout DONE; + input CCLK; + input CSB; + inout [31:0] D; + input DCMLOCK; + inout INITB; + input [2:0] M; + input PROGB; + input RDWRB; + + parameter DEVICE_ID = 32'h0; + + localparam cfg_Tprog = 300000; // min PROG must be low, 300 ns + localparam cfg_Tpl = 100000; // max program latency us. + localparam STARTUP_PH0 = 3'b000; + localparam STARTUP_PH1 = 3'b001; + localparam STARTUP_PH2 = 3'b010; + localparam STARTUP_PH3 = 3'b011; + localparam STARTUP_PH4 = 3'b100; + localparam STARTUP_PH5 = 3'b101; + localparam STARTUP_PH6 = 3'b110; + localparam STARTUP_PH7 = 3'b111; + +// tri0 GSR, GTS, GWE; + wire GSR; + wire GTS; + wire GWE; + wire cclk_in; + wire init_b_in; + wire prog_b_in; + wire rdwr_b_in; + reg init_b_out = 1; + reg done_o = 0; + + tri1 p_up; + + reg por_b; + wire [2:0] m_in; + wire [31:0] d_in, d_out; + wire busy_out; + wire cso_b_out; + wire csi_b_in; + wire d_out_en; + wire dcm_locked; + wire init_b_t; + wire prog_b_t; + wire bus_en; + wire desync_flag; + wire crc_rst; + + assign DONE = p_up; + assign INITB = p_up; + assign glbl.GSR = GSR; + assign glbl.GTS = GTS; + + buf buf_busy (BUSY, busy_out); + buf buf_cso (CSOB, cso_b_out); + buf buf_cclk (cclk_in, CCLK); + buf buf_cs (csi_b_in, CSB); + + buf buf_din[31:0] (d_in, D); + bufif1 buf_dout[31:0] (D, d_out, d_out_en); + buf buf_dcm (dcm_locked, DCMLOCK); + + buf buf_init (init_b_in, INITB); + buf buf_m_0 (m_in[0], M[0]); + buf buf_m_1 (m_in[1], M[1]); + buf buf_m_2 (m_in[2], M[2]); + buf buf_prog (prog_b_in, PROGB); + buf buf_rw (rdwr_b_in, RDWRB); + + time prog_pulse_low_edge = 0; + time prog_pulse_low = 0; + reg mode_sample_flag = 0; + reg buswid_flag_init = 0; + reg buswid_flag = 0; + reg [1:0] buswidth = 2'b00; + reg [31:0] pack_in_reg = 32'b0; + reg [4:0] reg_addr; + reg new_data_in_flag = 0; + reg wr_flag = 0; + reg rd_flag = 0; + reg cmd_wr_flag = 0; + reg cmd_reg_new_flag = 0; + reg cmd_rd_flag = 0; + reg bus_sync_flag = 0; + reg conti_data_flag = 0; + integer wr_cnt = 0; + integer conti_data_cnt = 0; + integer rd_data_cnt = 0; + integer abort_cnt = 0; + reg [2:0] st_state = STARTUP_PH0; + reg startup_begin_flag = 0; + reg startup_end_flag = 0; + reg crc_ck = 0; + reg crc_err_flag = 0; + wire crc_err_flag_tot; + reg crc_err_flag_reg = 0; + wire crc_en; + reg [31:0] crc_curr = 32'b0; + reg [31:0] crc_new = 32'b0; + reg [36:0] crc_input = 32'b0; + reg gwe_out = 0; + reg gts_out = 1; + reg [31:0] d_o = 32'h0; + reg [31:0] outbus = 32'h0; + reg [31:0] outbus1 = 32'h0; + reg busy_o = 0; + reg [31:0] tmp_val1, tmp_val2; + reg [31:0] ctl0_reg = 32'bx0xxxxxxxxxxxxxxxxxxx001x0000xx1; + reg [31:0] cor0_reg = 32'b00000x0000000000x011111111101100; + reg [31:0] cor1_reg = 32'b0; + reg [31:0] wbstar_reg = 32'b0; + reg [31:0] timer_reg = 32'b0; + reg [31:0] bootsts_reg = 32'b0; + reg [31:0] crc_reg; + reg [31:0] far_reg; + reg [31:0] fdri_reg; + reg [31:0] mask_reg; + reg [31:0] lout_reg; + reg [31:0] mfwr_reg; + reg [31:0] cbc_reg; + reg [31:0] idcode_reg; + reg [31:0] csob_reg; + reg [31:0] ctl1_reg; + reg [31:0] axss_reg; + reg [4:0] cmd_reg; + reg [2:0] mode_pin_in = 3'b0; + reg [2:0] mode_reg; + reg crc_reset = 0; + reg gsr_set = 0; + reg gts_usr_b = 1; + reg done_pin_drv = 0; + + reg shutdown_set = 0; + reg desynch_set = 0; + reg [2:0] done_cycle_reg; + reg [2:0] gts_cycle_reg; + reg [2:0] gwe_cycle_reg; + reg init_pin; + reg init_rst = 0; + reg init_complete; + reg [2:0] nx_st_state = 3'b000; + reg ghigh_b = 0; + reg gts_cfg_b = 0; + reg eos_startup = 0; + reg startup_set = 0; + reg [1:0] startup_set_pulse = 2'b0; + reg abort_out_en = 0; + reg [31:0] tmp_dword; + reg [15:0] tmp_word; + reg [7:0] tmp_byte; + reg id_error_flag = 0; + reg iprog_b = 1; + reg i_init_b_cmd = 1; + reg i_init_b = 0; + reg [7:0] abort_status = 8'b0; + reg persist_en = 0; + reg rst_sync = 0; + reg abort_dis = 0; + reg [2:0] lock_cycle_reg = 3'b0; + reg rbcrc_no_pin = 0; + reg abort_flag_rst = 0; + reg gsr_st_out = 1; + reg gsr_cmd_out = 0; + reg gsr_cmd_out_pulse = 0; + reg d_o_en = 0; + wire [31:0] stat_reg; + wire rst_intl; + wire rw_en; + wire gsr_out; + wire cfgerr_b_flag; + reg abort_flag_wr = 0; + reg abort_flag_rd = 0; + wire abort_flag; + integer downcont_cnt = 0; +// reg rst_en = 1; + reg rst_en = 0; + reg prog_b_a = 1; + reg csbo_flag = 0; + reg crc_bypass = 0; + reg csi_sync = 0; + reg rd_sw_en = 0; + integer csbo_cnt = 0; + reg [4:0] rd_reg_addr = 5'b0; + + triand (weak1, strong0) INITB=(mode_sample_flag) ? ~crc_err_flag_tot : init_b_out; + triand (weak1, strong0) DONE=done_o; + + initial begin + if (DEVICE_ID == 32'h0) begin + $display("Attribute Error : The attribute DEVICE_ID on SIM_CONFIG_V5 instance %m is not set."); + $finish; + end + end + + + assign GSR = gsr_out; + assign GTS = gts_out; + assign GWE = gwe_out; + assign busy_out = busy_o; + assign cfgerr_b_flag = rw_en & ~crc_err_flag_tot; + assign crc_err_flag_tot = id_error_flag | crc_err_flag_reg; + assign d_out[7:0] = (abort_out_en ) ? abort_status : outbus1[7:0]; + assign d_out[31:8] = (abort_out_en ) ? 24'b0 : outbus1[31:8]; + assign d_out_en = d_o_en; + assign cso_b_out = (csbo_flag== 1) ? 0 : 1; + assign crc_en = 1; + + always @(outbus) begin + outbus1[7:0] = bit_revers8(outbus[7:0]); + outbus1[15:8] = bit_revers8(outbus[15:8]); + outbus1[23:16] = bit_revers8(outbus[23:16]); + outbus1[31:24] = bit_revers8(outbus[31:24]); + end + + always @(csi_b_in or abort_flag) + if (csi_b_in) + busy_o = 1'b1; + else + if (abort_flag) + busy_o = 1'b1; + else + busy_o = 1'b0; + + always @(abort_out_en or csi_b_in or rdwr_b_in && rd_flag ) + if (abort_out_en) + d_o_en = 1; + else + d_o_en = rdwr_b_in & ~csi_b_in & rd_flag; + + + assign init_b_t = init_b_in & i_init_b_cmd; + + always @( negedge prog_b_in) begin + rst_en = 0; + rst_en <= #cfg_Tprog 1; + end + + always @( rst_en or init_rst or prog_b_in or iprog_b ) + if (init_rst) + init_b_out <= 0; + else begin + if ((prog_b_in == 0 ) && (rst_en == 1) || (iprog_b == 0)) + init_b_out <= 0; + else if ((prog_b_in == 1 ) && (rst_en == 1) || (iprog_b == 1)) + init_b_out <= #(cfg_Tpl) 1; + end + + always @(posedge id_error_flag) begin + init_rst <= 1; + init_rst <= #cfg_Tprog 0; + end + + always @( rst_en or prog_b_in or prog_pulse_low) + if (rst_en) begin + if (prog_pulse_low==cfg_Tprog) begin + prog_b_a = 0; + prog_b_a <= #500 1; + end + else + prog_b_a = prog_b_in; + end + else + prog_b_a = 1; + + initial begin + por_b = 0; + por_b = #400000 1; + end + + assign prog_b_t = prog_b_a & iprog_b & por_b; + + assign rst_intl = (prog_b_t==0 ) ? 0 : 1; + + always @(posedge init_b_t or negedge prog_b_t) + if (prog_b_t==0) + mode_sample_flag <= 0; + else if (init_b_t && mode_sample_flag == 0) begin + if (prog_b_t) begin + mode_pin_in <= m_in; + mode_sample_flag <= #1 1; + if (m_in != 3'b110) begin + $display("Error: input M is %h. Only Slave SelectMAP mode M=110 supported on SIM_CONFIG_V5 instance %m.", m_in); + end + end + else if ($time != 0) + $display("Error: PROGB is not high when INITB goes high on SIM_CONFIG_V5 instance %m at time %t.", $time); + end + + always @(m_in) + if (mode_sample_flag == 1 && persist_en == 1) + $display("Error : Mode pine M[2:0] changed after rising edge of INITB on SIM_CONFIG_V5 instance %m at time %t.", $time); + + always @(posedge prog_b_in or negedge prog_b_in) + if (prog_b_in ==0) + prog_pulse_low_edge <= $time; + else if (prog_b_in == 1 && $time > 0) begin + prog_pulse_low = $time - prog_pulse_low_edge; + if (prog_pulse_low < cfg_Tprog ) + $display("Error: Low time of PROGB is less than required minimum Tprogram time %d on SIM_CONFIG_V5 instance %m at time %t.", cfg_Tprog, $time); + end + + assign bus_en = (mode_sample_flag == 1 && csi_b_in ==0) ? 1 : 0; + + always @(posedge cclk_in or negedge rst_intl) + if (rst_intl ==0) begin + buswid_flag_init <= 0; + buswid_flag <= 0; + buswidth <= 2'b00; + end + else + if (buswid_flag == 0) begin + if (bus_en==1 && rdwr_b_in == 0) begin + tmp_byte = bit_revers8(d_in[7:0]); + if (buswid_flag_init == 0) begin + if (tmp_byte == 8'hBB) +// if (tmp_byte == 8'hDD) + buswid_flag_init <= 1; + end + else begin + if (tmp_byte == 8'h11) begin + buswid_flag <= 1; + buswidth <= 2'b01; + end + else if (tmp_byte == 8'h22) begin + buswid_flag <= 1; + buswidth <= 2'b10; + end + else if (tmp_byte == 8'h44) begin + buswid_flag <= 1; + buswidth <= 2'b11; + end + else begin + buswid_flag <= 0; + buswidth <= 2'b00; + buswid_flag_init <= 0; + $display("Error : BUS Width Auto Dection did not find 0x11 or 0x22 or 0x44 on D[7:0] followed 0xBB on SIM_CONFIG_V5 instance %m at time %t.", $time); + $finish; + end + end + end + end + + assign rw_en = (bus_en == 1 && buswid_flag == 1) ? 1 : 0; + assign desync_flag = ~rst_intl | desynch_set | crc_err_flag | id_error_flag; + + always @(posedge cclk_in) + csi_sync <= csi_b_in; + + always @(posedge cclk_in or negedge rdwr_b_in) + if (rdwr_b_in ==0) + rd_sw_en <= 0; + else begin + if (csi_sync == 1 && rdwr_b_in ==1) + rd_sw_en <= 1; + end + + always @(posedge cclk_in or posedge desync_flag) + if (desync_flag == 1) begin + pack_in_reg <= 32'b0; + new_data_in_flag <= 0; + bus_sync_flag <= 0; + wr_cnt <= 0; + wr_flag <= 0; + rd_flag <= 0; + end + else begin + if (rw_en == 1 ) begin + if (rdwr_b_in == 0) begin + wr_flag <= 1; + rd_flag <= 0; + if (buswidth == 2'b01) begin + tmp_byte = bit_revers8(d_in[7:0]); + if (bus_sync_flag == 0) begin + if (pack_in_reg[23:16] == 8'hAA && pack_in_reg[15:8] == 8'h99 + && pack_in_reg[7:0] == 8'h55 && tmp_byte == 8'h66) begin + bus_sync_flag <= 1; + new_data_in_flag <= 0; + wr_cnt <= 0; + end + else begin + pack_in_reg[31:24] <= pack_in_reg[23:16]; + pack_in_reg[23:16] <= pack_in_reg[15:8]; + pack_in_reg[15:8] <= pack_in_reg[7:0]; + pack_in_reg[7:0] <= tmp_byte; + end + end + else begin + if (wr_cnt == 0) begin + pack_in_reg[31:24] <= tmp_byte; + new_data_in_flag <= 0; + wr_cnt <= 1; + end + else if (wr_cnt == 1) begin + pack_in_reg[23:16] <= tmp_byte; + new_data_in_flag <= 0; + wr_cnt <= 2; + end + else if (wr_cnt == 2) begin + pack_in_reg[15:8] <= tmp_byte; + new_data_in_flag <= 0; + wr_cnt <= 3; + end + else if (wr_cnt == 3) begin + pack_in_reg[7:0] <= tmp_byte; + new_data_in_flag <= 1; + wr_cnt <= 0; + end + end + end + else if (buswidth == 2'b10) begin + tmp_word = {bit_revers8(d_in[15:8]), bit_revers8(d_in[7:0])}; + if (bus_sync_flag == 0) begin + if (pack_in_reg[15:0] == 16'hAA99 && tmp_word ==16'h5566) begin + wr_cnt <= 0; + bus_sync_flag <= 1; + new_data_in_flag <= 0; + end + else begin + pack_in_reg[31:16] <= pack_in_reg[15:0]; + pack_in_reg[15:0] <= tmp_word; + new_data_in_flag <= 0; + wr_cnt <= 0; + end + end + else begin + if (wr_cnt == 0) begin + pack_in_reg[31:16] <= tmp_word; + new_data_in_flag <= 0; + wr_cnt <= 1; + end + else if (wr_cnt == 1) begin + pack_in_reg[15:0] <= tmp_word; + new_data_in_flag <= 1; + wr_cnt <= 0; + end + end + end + else if (buswidth == 2'b11 ) begin + tmp_dword = {bit_revers8(d_in[31:24]), bit_revers8(d_in[23:16]), bit_revers8(d_in[15:8]), + bit_revers8(d_in[7:0])}; + pack_in_reg[31:0] <= tmp_dword; + if (bus_sync_flag == 0) begin + if (tmp_dword == 32'hAA995566) begin + bus_sync_flag <= 1; + new_data_in_flag <= 0; + end + end + else begin + pack_in_reg[31:0] <= tmp_dword; + new_data_in_flag <= 1; + end + end + end + else begin + wr_flag <= 0; + new_data_in_flag <= 0; + if (rd_sw_en ==1) + rd_flag <= 1; + end + end + else begin + wr_flag <= 0; + rd_flag <= 0; + new_data_in_flag <= 0; + end + end + + always @(negedge cclk_in or negedge rst_intl) + if (rst_intl ==0) begin + conti_data_flag <= 0; + conti_data_cnt <= 0; + cmd_wr_flag <= 0; + cmd_rd_flag <= 0; + id_error_flag <= 0; + crc_curr <= 32'b0; + crc_ck <= 0; + csbo_cnt <= 0; + csbo_flag <= 0; + downcont_cnt <= 0; + rd_data_cnt <= 0; + end + else begin + if (crc_reset == 1 ) begin + crc_reg <= 32'b0; + crc_ck <= 0; + crc_curr <= 32'b0; + end + if (crc_ck == 1) + crc_curr <= 32'b0; + + if (desynch_set || crc_err_flag==1) begin + conti_data_flag <= 0; + conti_data_cnt <= 0; + cmd_wr_flag <= 0; + cmd_rd_flag <= 0; + cmd_reg_new_flag <= 0; + crc_ck <= 0; + csbo_cnt <= 0; + csbo_flag <= 0; + downcont_cnt <= 0; + rd_data_cnt <= 0; + end + + + if (new_data_in_flag==1 && wr_flag==1) begin + if (conti_data_flag == 1 ) begin + case (reg_addr) + 5'b00000 : begin + crc_reg <= pack_in_reg; + crc_ck <= 1; + end + 5'b00001 : far_reg <= pack_in_reg; + 5'b00010 : fdri_reg <= pack_in_reg; + 5'b00100 : cmd_reg <= pack_in_reg[4:0]; + 5'b00101 : ctl0_reg <= (pack_in_reg & mask_reg) | (ctl0_reg & ~mask_reg); + 5'b00110 : mask_reg <= pack_in_reg; + 5'b01000 : lout_reg <= pack_in_reg; + 5'b01001 : cor0_reg <= pack_in_reg; + 5'b01010 : mfwr_reg <= pack_in_reg; +// 5'b01101 : cbc_reg <= pack_in_reg; + 5'b01100 : begin + idcode_reg <= pack_in_reg; + if (pack_in_reg[27:0] != DEVICE_ID[27:0]) begin + id_error_flag <= 1; + $display("Error : written value to IDCODE register is %h which does not match DEVICE ID %h on SIM_CONFIG_V5 instance %m at time %t.", pack_in_reg, DEVICE_ID, $time); + end + else + id_error_flag <= 0; + end + 5'b01101 : axss_reg <= pack_in_reg; + 5'b01110 : cor1_reg <= pack_in_reg; + 5'b01111 : csob_reg <= pack_in_reg; + 5'b10000 : wbstar_reg <= pack_in_reg; + 5'b10001 : timer_reg <= pack_in_reg; + 5'b11000 : ctl1_reg <= (pack_in_reg & mask_reg) | (ctl1_reg & ~mask_reg); + endcase + + if (reg_addr != 5'b00000) + crc_ck <= 0; + + if (reg_addr == 5'b00100) + cmd_reg_new_flag <= 1; + else + cmd_reg_new_flag <= 0; + + if (crc_en == 1) begin + if (reg_addr == 5'h04 && pack_in_reg[4:0] == 5'b00111) + crc_curr[31:0] = 32'b0; + else begin + if ( reg_addr != 5'h03 && reg_addr != 5'h07 && reg_addr != 5'h16 && + reg_addr != 5'h08 && reg_addr != 5'h00) begin + crc_input[36:0] = {reg_addr, pack_in_reg}; + crc_new[31:0] = bcc_next(crc_curr, crc_input); + crc_curr[31:0] <= crc_new; + end + end + end + + if (conti_data_cnt <= 1) begin + conti_data_cnt <= 0; + end + else + conti_data_cnt <= conti_data_cnt - 1; + end + else if (conti_data_flag == 0 ) begin + if ( downcont_cnt >= 1) begin + if (crc_en == 1) begin + crc_input[36:0] = {5'b00010, pack_in_reg}; + crc_new[31:0] = bcc_next(crc_curr, crc_input); + crc_curr[31:0] <= crc_new; + end + end + + if (pack_in_reg[31:29] == 3'b010 && downcont_cnt == 0 ) begin +// $display("Warning : only Type 1 Packet supported on SIM_CONFIG_V5 instance %m at time %t.", $time); + cmd_rd_flag <= 0; + cmd_wr_flag <= 0; + conti_data_flag <= 0; + conti_data_cnt <= 0; + downcont_cnt <= pack_in_reg[26:0]; + end + else if (pack_in_reg[31:29] == 3'b001) begin // type 1 package + if (pack_in_reg[28:27] == 2'b01 && downcont_cnt == 0) begin + if (pack_in_reg[10:0] != 10'b0) begin + cmd_rd_flag <= 1; + cmd_wr_flag <= 0; + rd_data_cnt <= pack_in_reg[10:0]; + rd_data_cnt <= 4; +// if (buswidth == 2'b01) +// rd_data_cnt <= 4; +// else if (buswidth == 2'b10) +// rd_data_cnt <= 2; +// else if (buswidth == 2'b11) +// rd_data_cnt <= 1; + conti_data_cnt <= 0; + conti_data_flag <= 0; + rd_reg_addr <= pack_in_reg[17:13]; + end + end + else if (pack_in_reg[28:27] == 2'b10 && downcont_cnt == 0) begin + if (pack_in_reg[17:13] == 5'b01111) begin // csbo reg + csob_reg <= pack_in_reg; + csbo_cnt = pack_in_reg[10:0]; + csbo_flag <= 1; + conti_data_flag = 0; + reg_addr <= pack_in_reg[17:13]; + cmd_wr_flag <= 1; + conti_data_cnt <= 5'b0; + end + else if (pack_in_reg[10:0] != 10'b0) begin + cmd_rd_flag <= 0; + cmd_wr_flag <= 1; + conti_data_flag <= 1; + conti_data_cnt <= pack_in_reg[10:0]; + reg_addr <= pack_in_reg[17:13]; + end + end + else begin + cmd_wr_flag <= 0; + conti_data_flag <= 0; + conti_data_cnt <= 0; + end + end + cmd_reg_new_flag <= 0; + crc_ck <= 0; + end // if (conti_data_flag == 0 ) + if (csbo_cnt != 0 ) begin + if (csbo_flag == 1) + csbo_cnt <= csbo_cnt - 1; + end + else + csbo_flag <= 0; + + if (conti_data_cnt == 5'b00001 ) + conti_data_flag <= 0; + + end + + if (rw_en ==1) begin + if (rd_data_cnt == 1 && rd_flag == 1) + rd_data_cnt <= 0; + else if (rd_data_cnt == 0 && rd_flag == 1) + cmd_rd_flag <= 0; + else if (cmd_rd_flag ==1 && rd_flag == 1) + rd_data_cnt <= rd_data_cnt - 1; + + if (downcont_cnt >= 1 && conti_data_flag == 0 && new_data_in_flag == 1 && wr_flag == 1) + downcont_cnt <= downcont_cnt - 1; + end + + if (crc_ck) + crc_ck <= 0; + end + + + always @(posedge cclk_in or negedge rst_intl) + if (rst_intl ==0) begin + outbus <= 32'b0; + end + else begin + if (cmd_rd_flag == 1 && rdwr_b_in == 1 && csi_b_in == 0) begin + case (rd_reg_addr) + 5'b00000 : if (buswidth == 2'b01) begin + outbus[31:8] <= 24'b0; + if (rd_data_cnt==1) + outbus[7:0] <= crc_reg[7:0]; + else if (rd_data_cnt==2) + outbus[7:0] <= crc_reg[15:8]; + else if (rd_data_cnt==3) + outbus[7:0] <= crc_reg[23:16]; + else if (rd_data_cnt==4) + outbus[7:0] <= crc_reg[31:24]; + end + else if (buswidth == 2'b10) begin + outbus[31:16] <= 16'b0; + if (rd_data_cnt==1) + outbus[15:0] <= crc_reg[15:0]; + else if (rd_data_cnt==2) + outbus[15:0] <= crc_reg[31:16]; + else if (rd_data_cnt==3) + outbus[15:0] <= 16'h00FF; + else if (rd_data_cnt==4) + outbus[15:0] <= 16'h00FF; + end + else if (buswidth == 2'b11) begin + if (rd_data_cnt==1) + outbus <= crc_reg; + else if (rd_data_cnt==2) + outbus <= 32'h000000FF; + else if (rd_data_cnt==3) + outbus <= 32'h000000FF; + else if (rd_data_cnt==4) + outbus <= 32'h000000FF; + end + + 5'b00111 : if (buswidth == 2'b01) begin + outbus[31:8] <= 24'b0; + if (rd_data_cnt==1) + outbus[7:0] <= stat_reg[7:0]; + else if (rd_data_cnt==2) + outbus[7:0] <= stat_reg[15:8]; + else if (rd_data_cnt==3) + outbus[7:0] <= stat_reg[23:16]; + else if (rd_data_cnt==4) + outbus[7:0] <= stat_reg[31:24]; + end + else if (buswidth == 2'b10) begin + outbus[31:16] <= 16'b0; + if (rd_data_cnt==1) + outbus[15:0] <= stat_reg[15:0]; + else if (rd_data_cnt==2) + outbus[15:0] <= stat_reg[31:16]; + else if (rd_data_cnt==3) + outbus[15:0] <= 16'h00FF; + else if (rd_data_cnt==4) + outbus[15:0] <= 16'h00FF; + end + else if (buswidth == 2'b11) begin + if (rd_data_cnt==1) + outbus <= stat_reg; + else if (rd_data_cnt==2) + outbus <= 32'h000000FF; + else if (rd_data_cnt==3) + outbus <= 32'h000000FF; + else if (rd_data_cnt==4) + outbus <= 32'h000000FF; + end + 5'b01100 : if (buswidth == 2'b01) begin + outbus[31:8] <= 24'b0; + if (rd_data_cnt==1) + outbus[7:0] <= idcode_reg[7:0]; + else if (rd_data_cnt==2) + outbus[7:0] <= idcode_reg[15:8]; + else if (rd_data_cnt==3) + outbus[7:0] <= idcode_reg[23:16]; + else if (rd_data_cnt==4) + outbus[7:0] <= idcode_reg[31:24]; + end + else if (buswidth == 2'b10) begin + outbus[31:16] <= 16'b0; + if (rd_data_cnt==1) + outbus[15:0] <= idcode_reg[15:0]; + else if (rd_data_cnt==2) + outbus[15:0] <= idcode_reg[31:16]; + else if (rd_data_cnt==3) + outbus[15:0] <= 16'h00FF; + else if (rd_data_cnt==4) + outbus[15:0] <= 16'h00FF; + end + else if (buswidth == 2'b11) begin + if (rd_data_cnt==1) + outbus <= idcode_reg; + else if (rd_data_cnt==2) + outbus <= 32'h000000FF; + else if (rd_data_cnt==3) + outbus <= 32'h000000FF; + else if (rd_data_cnt==4) + outbus <= 32'h000000FF; + end + endcase + end + else + outbus <= 32'b0; + end + + + + assign crc_rst = crc_reset | ~rst_intl; + + always @(posedge cclk_in or posedge crc_rst ) + if (crc_rst) + crc_err_flag <= 0; + else + if (crc_ck) begin + if (crc_bypass) begin + if (crc_reg[15:0] != 16'hdefc) + crc_err_flag <= 1; + else + crc_err_flag <= 0; + end + else begin + if (crc_curr[31:0] != crc_reg[31:0]) + crc_err_flag <= 1; + else + crc_err_flag <= 0; + end + end + else + crc_err_flag <= 0; + + always @(posedge crc_err_flag or negedge rst_intl or posedge bus_sync_flag) + if (rst_intl == 0) + crc_err_flag_reg <= 0; + else if (crc_err_flag == 1) + crc_err_flag_reg <= 1; + else + crc_err_flag_reg <= 0; + + always @(posedge cclk_in or negedge rst_intl) + if (rst_intl ==0) begin + startup_set <= 0; + crc_reset <= 0; + gsr_cmd_out <= 0; + shutdown_set <= 0; + desynch_set <= 0; + ghigh_b <= 0; + end + else begin + if (cmd_reg_new_flag ==1) begin + if (cmd_reg == 5'b00011) + ghigh_b <= 1; + else if (cmd_reg == 5'b01000) + ghigh_b <= 0; + + if (cmd_reg == 5'b00101) + startup_set <= 1; + + if (cmd_reg == 5'b00111) + crc_reset <= 1; + + if (cmd_reg == 5'b01010) + gsr_cmd_out <= 1; + + if (cmd_reg == 5'b01011) + shutdown_set <= 1; + + if (cmd_reg == 5'b01101) + desynch_set <= 1; + + if (cmd_reg == 5'b01111) begin + iprog_b <= 0; + i_init_b_cmd <= 0; + iprog_b <= #cfg_Tprog 1; + i_init_b_cmd <=#(cfg_Tprog + cfg_Tpl) 1; + end + end + else begin + startup_set <= 0; + crc_reset <= 0; + gsr_cmd_out <= 0; + shutdown_set <= 0; + desynch_set <= 0; + end + end + + always @(posedge startup_set or posedge desynch_set or rw_en ) + if (rw_en == 1) +// startup_set_pulse <= 2'b0; +// else begin + begin + if (startup_set_pulse == 2'b00 && startup_set ==1) + startup_set_pulse <= 2'b01; + else if (desynch_set == 1 && startup_set_pulse == 2'b01) begin + startup_set_pulse <= 2'b11; + @(posedge cclk_in ) + startup_set_pulse <= 2'b00; + end + end + + always @(posedge gsr_cmd_out or rw_en) + if (rw_en == 1) +// gsr_cmd_out_pulse <= 0; +// else begin + begin + gsr_cmd_out_pulse <= 1; + @(posedge cclk_in ); + @(posedge cclk_in ) + gsr_cmd_out_pulse <= 0; + end + + always @(ctl0_reg) begin + if (ctl0_reg[9] == 1) + abort_dis = 1; + else + abort_dis = 0; + + if (ctl0_reg[3] == 1) + persist_en = 1; + else + persist_en = 0; + + if (ctl0_reg[0] == 1) + gts_usr_b = 1; + else + gts_usr_b = 0; + end + + always @(cor0_reg) + begin + done_cycle_reg = cor0_reg[14:12]; + lock_cycle_reg = cor0_reg[8:6]; + gts_cycle_reg = cor0_reg[5:3]; + gwe_cycle_reg = cor0_reg[2:0]; + + if (cor0_reg[24] == 1'b1) + done_pin_drv = 1; + else + done_pin_drv = 0; + + if (cor0_reg[28] == 1'b1) + crc_bypass = 1; + else + crc_bypass = 0; + end + + always @(cor1_reg) + rbcrc_no_pin = cor1_reg[8]; + + + assign stat_reg[26:25] = buswidth; + assign stat_reg[20:18] = st_state; + assign stat_reg[16] = 1'b0; + assign stat_reg[15] = id_error_flag; + assign stat_reg[14] = DONE; + assign stat_reg[13] = (done_o !== 0) ? 1 : 0; + assign stat_reg[12] = INITB; + assign stat_reg[11] = mode_sample_flag; + assign stat_reg[10:8] = mode_pin_in; + assign stat_reg[7] = ghigh_b; + assign stat_reg[6] = gwe_out; + assign stat_reg[5] = gts_cfg_b; + assign stat_reg[4] = eos_startup; + assign stat_reg[3] = 1'bx; + assign stat_reg[2] = dcm_locked; + assign stat_reg[1] = 1'bx; + assign stat_reg[0] = crc_err_flag_reg; + + + always @(posedge cclk_in or negedge rst_intl) + if (rst_intl == 0) begin + st_state <= STARTUP_PH0; + startup_begin_flag <= 0; + startup_end_flag <= 0; + end + else begin + if (nx_st_state == STARTUP_PH1) begin + startup_begin_flag <= 1; + startup_end_flag <= 0; + end + else if (st_state == STARTUP_PH7) begin + startup_end_flag <= 1; + startup_begin_flag <= 0; + end + if (lock_cycle_reg == 3'b111 || dcm_locked == 1 || st_state != lock_cycle_reg ) begin + st_state <= nx_st_state; + end + else + st_state <= st_state; + end + + always @(st_state or startup_set_pulse or DONE ) +// if ( st_state == (done_cycle_reg + 1) && (DONE == 0) ) +// nx_st_state = done_cycle_reg + 1; +// else + if (((st_state == done_cycle_reg) && (DONE != 0)) || (st_state != done_cycle_reg)) + case (st_state) + STARTUP_PH0 : if (startup_set_pulse == 2'b11 ) + nx_st_state = STARTUP_PH1; + else + nx_st_state = STARTUP_PH0; + STARTUP_PH1 : nx_st_state = STARTUP_PH2; + + STARTUP_PH2 : nx_st_state = STARTUP_PH3; + + STARTUP_PH3 : nx_st_state = STARTUP_PH4; + + STARTUP_PH4 : nx_st_state = STARTUP_PH5; + + STARTUP_PH5 : nx_st_state = STARTUP_PH6; + + STARTUP_PH6 : nx_st_state = STARTUP_PH7; + + STARTUP_PH7 : nx_st_state = STARTUP_PH0; + endcase + + always @(posedge cclk_in or negedge rst_intl ) + if (rst_intl == 0) begin + gwe_out <= 0; + gts_out <= 1; + eos_startup <= 0; + gsr_st_out <= 1; + done_o <= 0; + end +// else if (startup_begin_flag == 1) begin + else begin + + if (nx_st_state == done_cycle_reg) begin + if (DONE != 0 || done_pin_drv == 1) + done_o <= 1'b1; + else + done_o <= 1'bz; + end + else begin + if (DONE != 0) + done_o <= 1; + end + + if (st_state == gwe_cycle_reg && DONE != 0) + gwe_out <= 1; + + if (st_state == gts_cycle_reg && DONE != 0) + gts_out <= 0; + + if (st_state == STARTUP_PH6 && DONE != 0) + gsr_st_out <= 0; + + if (st_state == STARTUP_PH7 && DONE != 0) + eos_startup <= 1; + + end + + assign gsr_out = gsr_st_out | gsr_cmd_out; + + always @(posedge rdwr_b_in or negedge rst_intl or + posedge abort_flag_rst or posedge csi_b_in) + if (rst_intl==0 || abort_flag_rst==1 || csi_b_in == 1) + abort_flag_wr <= 0; + else + if (abort_dis == 0 && csi_b_in == 0) begin + if ($time != 0) begin + abort_flag_wr <= 1; + $display(" Warning : RDWRB changes when CSB low, which causes Configuration abort on SIM_CONFIG_V5 instance %m at time %t.", $time); + end + end + else + abort_flag_wr <= 0; + + always @( negedge rdwr_b_in or negedge rst_intl or posedge abort_flag_rst or posedge csi_b_in) + if (rst_intl==0 || csi_b_in == 1 || abort_flag_rst==1) + abort_flag_rd <= 0; + else + if (abort_dis == 0 && csi_b_in == 0) begin + if ($time != 0) begin + abort_flag_rd <= 1; + $display(" Warning : RDWRB changes when CSB low, which causes Configuration abort on SIM_CONFIG_V5 instance %m at time %t.", $time); + end + end + else + abort_flag_rd <= 0; + + assign abort_flag = abort_flag_wr | abort_flag_rd; + + + always @(posedge cclk_in or negedge rst_intl) + if (rst_intl == 0) begin + abort_cnt <= 0; + abort_out_en <= 0; + end + else begin + if ( abort_flag ==1 ) begin + if (abort_cnt < 4) begin + abort_cnt <= abort_cnt + 1; + abort_out_en <= 1; + end + else + abort_flag_rst <= 1; + end + else begin + abort_cnt <= 0; + abort_out_en <= 0; + abort_flag_rst <= 0; + end + + if (abort_cnt== 0) + abort_status <= {cfgerr_b_flag, bus_sync_flag, 1'b0, 1'b1, 4'b1111}; + else if (abort_cnt== 1) + abort_status <= {cfgerr_b_flag, 1'b1, 1'b0, 1'b0, 4'b1111}; + else if (abort_cnt== 2) + abort_status <= {cfgerr_b_flag, 1'b0, 1'b0, 1'b0, 4'b1111}; + else if (abort_cnt== 3) + abort_status <= {cfgerr_b_flag, 1'b0, 1'b0, 1'b1, 4'b1111}; + + end + + +function [31:0] bcc_next; + input [31:0] bcc; + input [36:0] in; +reg [31:0] x; +reg [36:0] m; +begin + m = in; + x = in[31:0] ^ bcc; + + bcc_next[31] = m[32]^m[36]^x[31]^x[30]^x[29]^x[28]^x[27]^x[24]^x[20]^x[19]^x[18]^x[15]^x[13]^x[11]^x[10]^x[9]^x[8]^x[6]^x[5]^x[1]^x[0]; + + bcc_next[30] = m[35]^x[31]^x[30]^x[29]^x[28]^x[27]^x[26]^x[23]^x[19]^x[18]^x[17]^x[14]^x[12]^x[10]^x[9]^x[8]^x[7]^x[5]^x[4]^x[0]; + + bcc_next[29] = m[34]^x[30]^x[29]^x[28]^x[27]^x[26]^x[25]^x[22]^x[18]^x[17]^x[16]^x[13]^x[11]^x[9]^x[8]^x[7]^x[6]^x[4]^x[3]; + + bcc_next[28] = m[33]^x[29]^x[28]^x[27]^x[26]^x[25]^x[24]^x[21]^x[17]^x[16]^x[15]^x[12]^x[10]^x[8]^x[7]^x[6]^x[5]^x[3]^x[2]; + + bcc_next[27] = m[32]^x[28]^x[27]^x[26]^x[25]^x[24]^x[23]^x[20]^x[16]^x[15]^x[14]^x[11]^x[9]^x[7]^x[6]^x[5]^x[4]^x[2]^x[1]; + + bcc_next[26] = x[31]^x[27]^x[26]^x[25]^x[24]^x[23]^x[22]^x[19]^x[15]^x[14]^x[13]^x[10]^x[8]^x[6]^x[5]^x[4]^x[3]^x[1]^x[0]; + + bcc_next[25] = m[32]^m[36]^x[31]^x[29]^x[28]^x[27]^x[26]^x[25]^x[23]^x[22]^x[21]^x[20]^x[19]^x[15]^x[14]^x[12]^x[11]^x[10]^x[8]^x[7]^x[6]^x[4]^x[3]^x[2]^x[1]; + + bcc_next[24] = m[35]^x[31]^x[30]^x[28]^x[27]^x[26]^x[25]^x[24]^x[22]^x[21]^x[20]^x[19]^x[18]^x[14]^x[13]^x[11]^x[10]^x[9]^x[7]^x[6]^x[5]^x[3]^x[2]^x[1]^x[0]; + + bcc_next[23] = m[32]^m[34]^m[36]^x[31]^x[28]^x[26]^x[25]^x[23]^x[21]^x[17]^x[15]^x[12]^x[11]^x[4]^x[2]; + + bcc_next[22] = m[32]^m[33]^m[35]^m[36]^x[29]^x[28]^x[25]^x[22]^x[19]^x[18]^x[16]^x[15]^x[14]^x[13]^x[9]^x[8]^x[6]^x[5]^x[3]^x[0]; + + bcc_next[21] = m[34]^m[35]^m[36]^x[30]^x[29]^x[21]^x[20]^x[19]^x[17]^x[14]^x[12]^x[11]^x[10]^x[9]^x[7]^x[6]^x[4]^x[2]^x[1]^x[0]; + + bcc_next[20] = m[32]^m[33]^m[34]^m[35]^m[36]^x[31]^x[30]^x[27]^x[24]^x[16]^x[15]^x[3]; + + bcc_next[19] = m[32]^m[33]^m[34]^m[35]^x[31]^x[30]^x[29]^x[26]^x[23]^x[15]^x[14]^x[2]; + + bcc_next[18] = m[33]^m[34]^m[36]^x[27]^x[25]^x[24]^x[22]^x[20]^x[19]^x[18]^x[15]^x[14]^x[11]^x[10]^x[9]^x[8]^x[6]^x[5]^x[0]; + + bcc_next[17] = m[33]^m[35]^m[36]^x[31]^x[30]^x[29]^x[28]^x[27]^x[26]^x[23]^x[21]^x[20]^x[17]^x[15]^x[14]^x[11]^x[7]^x[6]^x[4]^x[1]^x[0]; + + bcc_next[16] = m[32]^m[34]^m[35]^x[30]^x[29]^x[28]^x[27]^x[26]^x[25]^x[22]^x[20]^x[19]^x[16]^x[14]^x[13]^x[10]^x[6]^x[5]^x[3]^x[0]; + + bcc_next[15] = m[33]^m[34]^x[31]^x[29]^x[28]^x[27]^x[26]^x[25]^x[24]^x[21]^x[19]^x[18]^x[15]^x[13]^x[12]^x[9]^x[5]^x[4]^x[2]; + + bcc_next[14] = m[32]^m[33]^x[30]^x[28]^x[27]^x[26]^x[25]^x[24]^x[23]^x[20]^x[18]^x[17]^x[14]^x[12]^x[11]^x[8]^x[4]^x[3]^x[1]; + + bcc_next[13] = m[36]^x[30]^x[28]^x[26]^x[25]^x[23]^x[22]^x[20]^x[18]^x[17]^x[16]^x[15]^x[9]^x[8]^x[7]^x[6]^x[5]^x[3]^x[2]^x[1]; + + bcc_next[12] = m[32]^m[35]^m[36]^x[31]^x[30]^x[28]^x[25]^x[22]^x[21]^x[20]^x[18]^x[17]^x[16]^x[14]^x[13]^x[11]^x[10]^x[9]^x[7]^x[4]^x[2]; + + bcc_next[11] = m[32]^m[34]^m[35]^m[36]^x[28]^x[21]^x[18]^x[17]^x[16]^x[12]^x[11]^x[5]^x[3]^x[0]; + + bcc_next[10] = m[33]^m[34]^m[35]^x[31]^x[27]^x[20]^x[17]^x[16]^x[15]^x[11]^x[10]^x[4]^x[2]; + + bcc_next[9] = m[33]^m[34]^m[36]^x[31]^x[29]^x[28]^x[27]^x[26]^x[24]^x[20]^x[18]^x[16]^x[14]^x[13]^x[11]^x[8]^x[6]^x[5]^x[3]^x[0]; + + bcc_next[8] = m[33]^m[35]^m[36]^x[31]^x[29]^x[26]^x[25]^x[24]^x[23]^x[20]^x[18]^x[17]^x[12]^x[11]^x[9]^x[8]^x[7]^x[6]^x[4]^x[2]^x[1]^x[0]; + + bcc_next[7] = m[32]^m[34]^m[35]^x[30]^x[28]^x[25]^x[24]^x[23]^x[22]^x[19]^x[17]^x[16]^x[11]^x[10]^x[8]^x[7]^x[6]^x[5]^x[3]^x[1]^x[0]; + + bcc_next[6] = m[32]^m[33]^m[34]^m[36]^x[30]^x[28]^x[23]^x[22]^x[21]^x[20]^x[19]^x[16]^x[13]^x[11]^x[8]^x[7]^x[4]^x[2]^x[1]; + + bcc_next[5] = m[33]^m[35]^m[36]^x[30]^x[28]^x[24]^x[22]^x[21]^x[13]^x[12]^x[11]^x[9]^x[8]^x[7]^x[5]^x[3]; + + bcc_next[4] = m[34]^m[35]^m[36]^x[31]^x[30]^x[28]^x[24]^x[23]^x[21]^x[19]^x[18]^x[15]^x[13]^x[12]^x[9]^x[7]^x[5]^x[4]^x[2]^x[1]^x[0]; + + bcc_next[3] = m[32]^m[33]^m[34]^m[35]^m[36]^x[31]^x[28]^x[24]^x[23]^x[22]^x[19]^x[17]^x[15]^x[14]^x[13]^x[12]^x[10]^x[9]^x[5]^x[4]^x[3]; + + bcc_next[2] = m[32]^m[33]^m[34]^m[35]^x[31]^x[30]^x[27]^x[23]^x[22]^x[21]^x[18]^x[16]^x[14]^x[13]^x[12]^x[11]^x[9]^x[8]^x[4]^x[3]^x[2]; + + bcc_next[1] = m[32]^m[33]^m[34]^x[31]^x[30]^x[29]^x[26]^x[22]^x[21]^x[20]^x[17]^x[15]^x[13]^x[12]^x[11]^x[10]^x[8]^x[7]^x[3]^x[2]^x[1]; + + bcc_next[0] = m[32]^m[33]^x[31]^x[30]^x[29]^x[28]^x[25]^x[21]^x[20]^x[19]^x[16]^x[14]^x[12]^x[11]^x[10]^x[9]^x[7]^x[6]^x[2]^x[1]^x[0]; + +end +endfunction + +function [7:0] bit_revers8; + input [7:0] din8; + begin + bit_revers8[0] = din8[7]; + bit_revers8[1] = din8[6]; + bit_revers8[2] = din8[5]; + bit_revers8[3] = din8[4]; + bit_revers8[4] = din8[3]; + bit_revers8[5] = din8[2]; + bit_revers8[6] = din8[1]; + bit_revers8[7] = din8[0]; + end +endfunction + + + +endmodule diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/SIM_CONFIG_V5_SERIAL.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/SIM_CONFIG_V5_SERIAL.v new file mode 100644 index 0000000..1fea09c --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/SIM_CONFIG_V5_SERIAL.v @@ -0,0 +1,838 @@ +////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2005 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Function Simulation Library Component +// / / Configuration Simulation Model +// /___/ /\ Filename : SIM_CONFIG_V5_SERIAL.v +// \ \ / \ Timestamp : +// \___\/\___\ +// +// Revision: +// 03/23/09 - Initial version. +// End Revision +//////////////////////////////////////////////////////////////////////////////// + +`timescale 1 ps / 1 ps + +module SIM_CONFIG_V5_SERIAL ( + DONE, + DOUT, + CCLK, + DIN, + INITB, + M, + PROGB + ); + + inout DONE; + output DOUT; + input CCLK; + input DIN; + inout INITB; + input [2:0] M; + input PROGB; + + parameter DEVICE_ID = 32'h0; + + localparam cfg_Tprog = 300000; // min PROG must be low, 300 ns + localparam cfg_Tpl = 100000; // max program latency us. + localparam STARTUP_PH0 = 3'b000; + localparam STARTUP_PH1 = 3'b001; + localparam STARTUP_PH2 = 3'b010; + localparam STARTUP_PH3 = 3'b011; + localparam STARTUP_PH4 = 3'b100; + localparam STARTUP_PH5 = 3'b101; + localparam STARTUP_PH6 = 3'b110; + localparam STARTUP_PH7 = 3'b111; + +// tri0 GSR, GTS, GWE; + wire GSR; + wire GTS; + wire GWE; + wire cclk_in; + wire init_b_in; + wire prog_b_in; + reg init_b_out = 1; + reg done_o = 0; + + tri1 p_up; + + reg por_b; + wire [2:0] m_in; + wire init_b_t; + wire prog_b_t; + wire bus_en; + wire desync_flag; + wire crc_rst; + + assign DONE = p_up; + assign INITB = p_up; + assign glbl.GSR = GSR; + assign glbl.GTS = GTS; + + buf buf_cclk (cclk_in, CCLK); + + buf buf_din (ds_in, DIN); + buf buf_dout (DOUT, ds_out); + + buf buf_init (init_b_in, INITB); + buf buf_m_0 (m_in[0], M[0]); + buf buf_m_1 (m_in[1], M[1]); + buf buf_m_2 (m_in[2], M[2]); + buf buf_prog (prog_b_in, PROGB); + + time prog_pulse_low_edge = 0; + time prog_pulse_low = 0; + reg mode_sample_flag = 0; + reg [31:0] pack_in_reg = 32'b0; + reg [4:0] reg_addr; + reg new_data_in_flag = 0; + reg wr_flag = 1; + integer wr_bit_addr = 0; + reg rd_flag = 0; + reg cmd_wr_flag = 0; + reg cmd_reg_new_flag = 0; + reg cmd_rd_flag = 0; + reg bus_sync_flag = 0; + reg conti_data_flag = 0; + integer wr_cnt = 0; + integer conti_data_cnt = 0; + integer rd_data_cnt = 0; + reg [2:0] st_state = STARTUP_PH0; + reg startup_begin_flag = 0; + reg startup_end_flag = 0; + reg crc_ck = 0; + reg crc_err_flag = 0; + wire crc_err_flag_tot; + reg crc_err_flag_reg = 0; + wire crc_en; + reg [31:0] crc_curr = 32'b0; + reg [31:0] crc_new = 32'b0; + reg [36:0] crc_input = 32'b0; + reg gwe_out = 0; + reg gts_out = 1; + reg [31:0] tmp_dword1, tmp_dword2; + reg [31:0] tmp_val1, tmp_val2; + reg [31:0] ctl0_reg = 32'bx0xxxxxxxxxxxxxxxxxxx001x0000xx1; + reg [31:0] cor0_reg = 32'b00000x0000000000x011111111101100; + reg [31:0] cor1_reg = 32'b0; + reg [31:0] wbstar_reg = 32'b0; + reg [31:0] timer_reg = 32'b0; + reg [31:0] bootsts_reg = 32'b0; + reg [31:0] crc_reg; + reg [31:0] far_reg; + reg [31:0] fdri_reg; + reg [31:0] mask_reg; + reg [31:0] lout_reg; + reg [31:0] mfwr_reg; + reg [31:0] cbc_reg; + reg [31:0] idcode_reg; + reg [31:0] csob_reg; + reg [31:0] ctl1_reg; + reg [31:0] axss_reg; + reg [4:0] cmd_reg; + reg [2:0] mode_pin_in = 3'b0; + reg [2:0] mode_reg; + reg crc_reset = 0; + reg gsr_set = 0; + reg gts_usr_b = 1; + reg done_pin_drv = 0; + + reg shutdown_set = 0; + reg desynch_set = 0; + reg [2:0] done_cycle_reg; + reg [2:0] gts_cycle_reg; + reg [2:0] gwe_cycle_reg; + reg init_pin; + reg init_rst = 0; + reg init_complete; + reg [2:0] nx_st_state = 3'b000; + reg ghigh_b = 0; + reg gts_cfg_b = 0; + reg eos_startup = 0; + reg startup_set = 0; + reg [1:0] startup_set_pulse = 2'b0; + reg id_error_flag = 0; + reg iprog_b = 1; + reg i_init_b_cmd = 1; + reg i_init_b = 0; + reg persist_en = 0; + reg rst_sync = 0; + reg [2:0] lock_cycle_reg = 3'b0; + reg rbcrc_no_pin = 0; + reg gsr_st_out = 1; + reg gsr_cmd_out = 0; + reg gsr_cmd_out_pulse = 0; + reg d_o_en = 0; + wire [31:0] stat_reg; + wire rst_intl; + wire rw_en; + wire gsr_out; + wire cfgerr_b_flag; + integer downcont_cnt = 0; + reg rst_en = 0; + reg prog_b_a = 1; + reg csbo_flag = 0; + reg crc_bypass = 0; + reg csi_sync = 0; + reg rd_sw_en = 0; + integer csbo_cnt = 0; + reg [4:0] rd_reg_addr = 5'b0; + reg dcm_locked = 1; + reg abort_dis = 0; + + triand (weak1, strong0) INITB=(mode_sample_flag) ? ~crc_err_flag_tot : init_b_out; + triand (weak1, strong0) DONE=done_o; + + initial begin + if (DEVICE_ID == 32'h0) begin + $display("Attribute Error : The attribute DEVICE_ID on SIM_CONFIG_V5_SERIAL instance %m is not set."); + $finish; + end + end + + + assign GSR = gsr_out; + assign GTS = gts_out; + assign GWE = gwe_out; + assign ds_out = 1; + assign cfgerr_b_flag = rw_en & ~crc_err_flag_tot; + assign crc_err_flag_tot = id_error_flag | crc_err_flag_reg; + assign crc_en = 1; + + assign init_b_t = init_b_in & i_init_b_cmd; + + always @( negedge prog_b_in) begin + rst_en = 0; + rst_en <= #cfg_Tprog 1; + end + + always @( rst_en or init_rst or prog_b_in or iprog_b ) + if (init_rst) + init_b_out <= 0; + else begin + if ((prog_b_in == 0 ) && (rst_en == 1) || (iprog_b == 0)) + init_b_out <= 0; + else if ((prog_b_in == 1 ) && (rst_en == 1) || (iprog_b == 1)) + init_b_out <= #(cfg_Tpl) 1; + end + + always @(posedge id_error_flag) begin + init_rst <= 1; + init_rst <= #cfg_Tprog 0; + end + + always @( rst_en or prog_b_in or prog_pulse_low) + if (rst_en) begin + if (prog_pulse_low==cfg_Tprog) begin + prog_b_a = 0; + prog_b_a <= #500 1; + end + else + prog_b_a = prog_b_in; + end + else + prog_b_a = 1; + + initial begin + por_b = 0; + por_b = #400000 1; + end + + assign prog_b_t = prog_b_a & iprog_b & por_b; + + assign rst_intl = (prog_b_t==0 ) ? 0 : 1; + + always @(posedge init_b_t or negedge prog_b_t) + if (prog_b_t==0) + mode_sample_flag <= 0; + else if (init_b_t && mode_sample_flag == 0) begin + if (prog_b_t) begin + mode_pin_in <= m_in; + mode_sample_flag <= #1 1; + if (m_in != 3'b110) begin + $display("Error: input M is %h. Only Slave Serial mode M=111 supported on SIM_CONFIG_V5_SERIAL instance %m.", m_in); + end + end + else if ($time != 0) + $display("Error: PROGB is not high when INITB goes high on SIM_CONFIG_V5_SERIAL instance %m at time %t.", $time); + end + + always @(m_in) + if (mode_sample_flag == 1 && persist_en == 1) + $display("Error : Mode pine M[2:0] changed after rising edge of INITB on SIM_CONFIG_V5_SERIAL instance %m at time %t.", $time); + + always @(posedge prog_b_in or negedge prog_b_in) + if (prog_b_in ==0) + prog_pulse_low_edge <= $time; + else if (prog_b_in == 1 && $time > 0) begin + prog_pulse_low = $time - prog_pulse_low_edge; + if (prog_pulse_low < cfg_Tprog ) + $display("Error: Low time of PROGB is less than required minimum Tprogram time %d on SIM_CONFIG_V5_SERIAL instance %m at time %t.", cfg_Tprog, $time); + end + + assign bus_en = (mode_sample_flag == 1 ) ? 1 : 0; + assign rw_en = (bus_en == 1 && done_o === 0) ? 1 : 0; + assign desync_flag = ~rst_intl | desynch_set | crc_err_flag | id_error_flag; + + always @(posedge cclk_in or posedge desync_flag) + if (desync_flag == 1) begin + pack_in_reg <= 32'b0; + new_data_in_flag <= 0; + bus_sync_flag <= 0; + wr_cnt <= 0; + wr_flag <= 1; + tmp_dword1 <= 32'b0; + tmp_dword2 <= 32'b0; + rd_flag <= 0; + end + else begin + if (rw_en == 1 ) begin + if (bus_sync_flag == 0) begin + tmp_dword1 = {tmp_dword2[30:0], ds_in}; + if (tmp_dword1 == 32'hAA995566) begin + bus_sync_flag <= 1; + new_data_in_flag <= 0; + tmp_dword2 <= 32'b0; + pack_in_reg <= 32'b0; + wr_cnt <= 0; + end + else begin + tmp_dword2 <= tmp_dword1; + end + end + else begin + pack_in_reg <= {pack_in_reg[30:0], ds_in}; + if (wr_cnt == 31) begin + wr_cnt <= 0; + new_data_in_flag <= 1; + end + else begin + wr_cnt <= wr_cnt + 1; + new_data_in_flag <= 0; + end + end + end + else begin + new_data_in_flag <= 0; + end + end + + always @(negedge cclk_in or negedge rst_intl) + if (rst_intl ==0) begin + conti_data_flag <= 0; + conti_data_cnt <= 0; + cmd_wr_flag <= 0; + cmd_rd_flag <= 0; + id_error_flag <= 0; + crc_curr <= 32'b0; + crc_ck <= 0; + csbo_cnt <= 0; + csbo_flag <= 0; + downcont_cnt <= 0; + rd_data_cnt <= 0; + end + else begin + if (crc_reset == 1 ) begin + crc_reg <= 32'b0; + crc_ck <= 0; + crc_curr <= 32'b0; + end + if (crc_ck == 1) + crc_curr <= 32'b0; + + if (desynch_set || crc_err_flag==1) begin + conti_data_flag <= 0; + conti_data_cnt <= 0; + cmd_wr_flag <= 0; + cmd_rd_flag <= 0; + cmd_reg_new_flag <= 0; + crc_ck <= 0; + csbo_cnt <= 0; + csbo_flag <= 0; + downcont_cnt <= 0; + rd_data_cnt <= 0; + end + + + if (new_data_in_flag==1 && wr_flag==1) begin + if (conti_data_flag == 1 ) begin + case (reg_addr) + 5'b00000 : begin + crc_reg <= pack_in_reg; + crc_ck <= 1; + end + 5'b00001 : far_reg <= pack_in_reg; + 5'b00010 : fdri_reg <= pack_in_reg; + 5'b00100 : cmd_reg <= pack_in_reg[4:0]; + 5'b00101 : ctl0_reg <= (pack_in_reg & mask_reg) | (ctl0_reg & ~mask_reg); + 5'b00110 : mask_reg <= pack_in_reg; + 5'b01000 : lout_reg <= pack_in_reg; + 5'b01001 : cor0_reg <= pack_in_reg; + 5'b01010 : mfwr_reg <= pack_in_reg; +// 5'b01101 : cbc_reg <= pack_in_reg; + 5'b01100 : begin + idcode_reg <= pack_in_reg; + if (pack_in_reg[27:0] != DEVICE_ID[27:0]) begin + id_error_flag <= 1; + $display("Error : written value to IDCODE register is %h which does not match DEVICE ID %h on SIM_CONFIG_V5_SERIAL instance %m at time %t.", pack_in_reg, DEVICE_ID, $time); + end + else + id_error_flag <= 0; + end + 5'b01101 : axss_reg <= pack_in_reg; + 5'b01110 : cor1_reg <= pack_in_reg; + 5'b01111 : csob_reg <= pack_in_reg; + 5'b10000 : wbstar_reg <= pack_in_reg; + 5'b10001 : timer_reg <= pack_in_reg; + 5'b11000 : ctl1_reg <= (pack_in_reg & mask_reg) | (ctl1_reg & ~mask_reg); + endcase + + if (reg_addr != 5'b00000) + crc_ck <= 0; + + if (reg_addr == 5'b00100) + cmd_reg_new_flag <= 1; + else + cmd_reg_new_flag <= 0; + + if (crc_en == 1) begin + if (reg_addr == 5'h04 && pack_in_reg[4:0] == 5'b00111) + crc_curr[31:0] = 32'b0; + else begin + if ( reg_addr != 5'h03 && reg_addr != 5'h07 && reg_addr != 5'h16 && + reg_addr != 5'h08 && reg_addr != 5'h00) begin + crc_input[36:0] = {reg_addr, pack_in_reg}; + crc_new[31:0] = bcc_next(crc_curr, crc_input); + crc_curr[31:0] <= crc_new; + end + end + end + + if (conti_data_cnt <= 1) begin + conti_data_cnt <= 0; + end + else + conti_data_cnt <= conti_data_cnt - 1; + end + else if (conti_data_flag == 0 ) begin + if ( downcont_cnt >= 1) begin + if (crc_en == 1) begin + crc_input[36:0] = {5'b00010, pack_in_reg}; + crc_new[31:0] = bcc_next(crc_curr, crc_input); + crc_curr[31:0] <= crc_new; + end + end + + if (pack_in_reg[31:29] == 3'b010 && downcont_cnt == 0 ) begin +// $display("Warning : only Type 1 Packet supported on SIM_CONFIG_V5_SERIAL instance %m at time %t.", $time); + cmd_rd_flag <= 0; + cmd_wr_flag <= 0; + conti_data_flag <= 0; + conti_data_cnt <= 0; + downcont_cnt <= pack_in_reg[26:0]; + end + else if (pack_in_reg[31:29] == 3'b001) begin // type 1 package + if (pack_in_reg[28:27] == 2'b01 && downcont_cnt == 0) begin + if (pack_in_reg[10:0] != 10'b0) begin + cmd_rd_flag <= 1; + cmd_wr_flag <= 0; + rd_data_cnt <= pack_in_reg[10:0]; + rd_data_cnt <= 4; + conti_data_cnt <= 0; + conti_data_flag <= 0; + rd_reg_addr <= pack_in_reg[17:13]; + end + end + else if (pack_in_reg[28:27] == 2'b10 && downcont_cnt == 0) begin + if (pack_in_reg[17:13] == 5'b01111) begin // csbo reg + csob_reg <= pack_in_reg; + csbo_cnt = pack_in_reg[10:0]; + csbo_flag <= 1; + conti_data_flag = 0; + reg_addr <= pack_in_reg[17:13]; + cmd_wr_flag <= 1; + conti_data_cnt <= 5'b0; + end + else if (pack_in_reg[10:0] != 10'b0) begin + cmd_rd_flag <= 0; + cmd_wr_flag <= 1; + conti_data_flag <= 1; + conti_data_cnt <= pack_in_reg[10:0]; + reg_addr <= pack_in_reg[17:13]; + end + end + else begin + cmd_wr_flag <= 0; + conti_data_flag <= 0; + conti_data_cnt <= 0; + end + end + cmd_reg_new_flag <= 0; + crc_ck <= 0; + end // if (conti_data_flag == 0 ) + if (csbo_cnt != 0 ) begin + if (csbo_flag == 1) + csbo_cnt <= csbo_cnt - 1; + end + else + csbo_flag <= 0; + + if (conti_data_cnt == 5'b00001 ) + conti_data_flag <= 0; + + end + + if (rw_en ==1) begin + if (rd_data_cnt == 1 && rd_flag == 1) + rd_data_cnt <= 0; + else if (rd_data_cnt == 0 && rd_flag == 1) + cmd_rd_flag <= 0; + else if (cmd_rd_flag ==1 && rd_flag == 1) + rd_data_cnt <= rd_data_cnt - 1; + + if (downcont_cnt >= 1 && conti_data_flag == 0 && new_data_in_flag == 1 && wr_flag == 1) + downcont_cnt <= downcont_cnt - 1; + end + + if (crc_ck) + crc_ck <= 0; + end + + assign crc_rst = crc_reset | ~rst_intl; + + always @(posedge cclk_in or posedge crc_rst ) + if (crc_rst) + crc_err_flag <= 0; + else + if (crc_ck) begin + if (crc_bypass) begin + if (crc_reg[15:0] != 16'hdefc) + crc_err_flag <= 1; + else + crc_err_flag <= 0; + end + else begin + if (crc_curr[31:0] != crc_reg[31:0]) + crc_err_flag <= 1; + else + crc_err_flag <= 0; + end + end + else + crc_err_flag <= 0; + + always @(posedge crc_err_flag or negedge rst_intl or posedge bus_sync_flag) + if (rst_intl == 0) + crc_err_flag_reg <= 0; + else if (crc_err_flag == 1) + crc_err_flag_reg <= 1; + else + crc_err_flag_reg <= 0; + + always @(posedge cclk_in or negedge rst_intl) + if (rst_intl ==0) begin + startup_set <= 0; + crc_reset <= 0; + gsr_cmd_out <= 0; + shutdown_set <= 0; + desynch_set <= 0; + ghigh_b <= 0; + end + else begin + if (cmd_reg_new_flag ==1) begin + if (cmd_reg == 5'b00011) + ghigh_b <= 1; + else if (cmd_reg == 5'b01000) + ghigh_b <= 0; + + if (cmd_reg == 5'b00101) + startup_set <= 1; + + if (cmd_reg == 5'b00111) + crc_reset <= 1; + + if (cmd_reg == 5'b01010) + gsr_cmd_out <= 1; + + if (cmd_reg == 5'b01011) + shutdown_set <= 1; + + if (cmd_reg == 5'b01101) + desynch_set <= 1; + + if (cmd_reg == 5'b01111) begin + iprog_b <= 0; + i_init_b_cmd <= 0; + iprog_b <= #cfg_Tprog 1; + i_init_b_cmd <=#(cfg_Tprog + cfg_Tpl) 1; + end + end + else begin + startup_set <= 0; + crc_reset <= 0; + gsr_cmd_out <= 0; + shutdown_set <= 0; + desynch_set <= 0; + end + end + + always @(posedge startup_set or posedge desynch_set or negedge rw_en ) + if (rw_en == 0) + startup_set_pulse <= 2'b0; + else begin + if (startup_set_pulse == 2'b00 && startup_set ==1) + startup_set_pulse <= 2'b01; + else if (desynch_set == 1 && startup_set_pulse == 2'b01) begin + startup_set_pulse <= 2'b11; + @(posedge cclk_in ) + startup_set_pulse <= 2'b00; + end + end + + always @(posedge gsr_cmd_out or negedge rw_en) + if (rw_en == 0) + gsr_cmd_out_pulse <= 0; + else begin + gsr_cmd_out_pulse <= 1; + @(posedge cclk_in ); + @(posedge cclk_in ) + gsr_cmd_out_pulse <= 0; + end + + always @(ctl0_reg) begin + if (ctl0_reg[9] == 1) + abort_dis = 1; + else + abort_dis = 0; + + if (ctl0_reg[3] == 1) + persist_en = 1; + else + persist_en = 0; + + if (ctl0_reg[0] == 1) + gts_usr_b = 1; + else + gts_usr_b = 0; + end + + always @(cor0_reg) + begin + done_cycle_reg = cor0_reg[14:12]; + lock_cycle_reg = cor0_reg[8:6]; + gts_cycle_reg = cor0_reg[5:3]; + gwe_cycle_reg = cor0_reg[2:0]; + + if (cor0_reg[24] == 1'b1) + done_pin_drv = 1; + else + done_pin_drv = 0; + + if (cor0_reg[28] == 1'b1) + crc_bypass = 1; + else + crc_bypass = 0; + end + + always @(cor1_reg) + rbcrc_no_pin = cor1_reg[8]; + + + assign stat_reg[26:25] = 2'b00; + assign stat_reg[20:18] = st_state; + assign stat_reg[16] = 1'b0; + assign stat_reg[15] = id_error_flag; + assign stat_reg[14] = DONE; + assign stat_reg[13] = (done_o !== 0) ? 1 : 0; + assign stat_reg[12] = INITB; + assign stat_reg[11] = mode_sample_flag; + assign stat_reg[10:8] = mode_pin_in; + assign stat_reg[7] = ghigh_b; + assign stat_reg[6] = gwe_out; + assign stat_reg[5] = gts_cfg_b; + assign stat_reg[4] = eos_startup; + assign stat_reg[3] = 1'bx; + assign stat_reg[2] = dcm_locked; + assign stat_reg[1] = 1'bx; + assign stat_reg[0] = crc_err_flag_reg; + + + always @(posedge cclk_in or negedge rst_intl) + if (rst_intl == 0) begin + st_state <= STARTUP_PH0; + startup_begin_flag <= 0; + startup_end_flag <= 0; + end + else begin + if (nx_st_state == STARTUP_PH1) begin + startup_begin_flag <= 1; + startup_end_flag <= 0; + end + else if (st_state == STARTUP_PH7) begin + startup_end_flag <= 1; + startup_begin_flag <= 0; + end + if (lock_cycle_reg == 3'b111 || dcm_locked == 1 || st_state != lock_cycle_reg ) begin + st_state <= nx_st_state; + end + else + st_state <= st_state; + end + + always @(st_state or startup_set_pulse or DONE ) + if (((st_state == done_cycle_reg) && (DONE != 0)) || (st_state != done_cycle_reg)) + case (st_state) + STARTUP_PH0 : if (startup_set_pulse == 2'b11 ) + nx_st_state = STARTUP_PH1; + else + nx_st_state = STARTUP_PH0; + STARTUP_PH1 : nx_st_state = STARTUP_PH2; + + STARTUP_PH2 : nx_st_state = STARTUP_PH3; + + STARTUP_PH3 : nx_st_state = STARTUP_PH4; + + STARTUP_PH4 : nx_st_state = STARTUP_PH5; + + STARTUP_PH5 : nx_st_state = STARTUP_PH6; + + STARTUP_PH6 : nx_st_state = STARTUP_PH7; + + STARTUP_PH7 : nx_st_state = STARTUP_PH0; + endcase + + always @(posedge cclk_in or negedge rst_intl ) + if (rst_intl == 0) begin + gwe_out <= 0; + gts_out <= 1; + eos_startup <= 0; + gsr_st_out <= 1; + done_o <= 0; + end + else begin + if (nx_st_state == done_cycle_reg) begin + if (DONE != 0 || done_pin_drv == 1) + done_o <= 1'b1; + else + done_o <= 1'bz; + end + else begin + if (DONE != 0) + done_o <= 1; + end + + if (st_state == gwe_cycle_reg && DONE != 0) + gwe_out <= 1; + + if (st_state == gts_cycle_reg && DONE != 0) + gts_out <= 0; + + if (st_state == STARTUP_PH6 && DONE != 0) + gsr_st_out <= 0; + + if (st_state == STARTUP_PH7 && DONE != 0) + eos_startup <= 1; + + end + + assign gsr_out = gsr_st_out | gsr_cmd_out; + +function [31:0] bcc_next; + input [31:0] bcc; + input [36:0] in; +reg [31:0] x; +reg [36:0] m; +begin + m = in; + x = in[31:0] ^ bcc; + + bcc_next[31] = m[32]^m[36]^x[31]^x[30]^x[29]^x[28]^x[27]^x[24]^x[20]^x[19]^x[18]^x[15]^x[13]^x[11]^x[10]^x[9]^x[8]^x[6]^x[5]^x[1]^x[0]; + + bcc_next[30] = m[35]^x[31]^x[30]^x[29]^x[28]^x[27]^x[26]^x[23]^x[19]^x[18]^x[17]^x[14]^x[12]^x[10]^x[9]^x[8]^x[7]^x[5]^x[4]^x[0]; + + bcc_next[29] = m[34]^x[30]^x[29]^x[28]^x[27]^x[26]^x[25]^x[22]^x[18]^x[17]^x[16]^x[13]^x[11]^x[9]^x[8]^x[7]^x[6]^x[4]^x[3]; + + bcc_next[28] = m[33]^x[29]^x[28]^x[27]^x[26]^x[25]^x[24]^x[21]^x[17]^x[16]^x[15]^x[12]^x[10]^x[8]^x[7]^x[6]^x[5]^x[3]^x[2]; + + bcc_next[27] = m[32]^x[28]^x[27]^x[26]^x[25]^x[24]^x[23]^x[20]^x[16]^x[15]^x[14]^x[11]^x[9]^x[7]^x[6]^x[5]^x[4]^x[2]^x[1]; + + bcc_next[26] = x[31]^x[27]^x[26]^x[25]^x[24]^x[23]^x[22]^x[19]^x[15]^x[14]^x[13]^x[10]^x[8]^x[6]^x[5]^x[4]^x[3]^x[1]^x[0]; + + bcc_next[25] = m[32]^m[36]^x[31]^x[29]^x[28]^x[27]^x[26]^x[25]^x[23]^x[22]^x[21]^x[20]^x[19]^x[15]^x[14]^x[12]^x[11]^x[10]^x[8]^x[7]^x[6]^x[4]^x[3]^x[2]^x[1]; + + bcc_next[24] = m[35]^x[31]^x[30]^x[28]^x[27]^x[26]^x[25]^x[24]^x[22]^x[21]^x[20]^x[19]^x[18]^x[14]^x[13]^x[11]^x[10]^x[9]^x[7]^x[6]^x[5]^x[3]^x[2]^x[1]^x[0]; + + bcc_next[23] = m[32]^m[34]^m[36]^x[31]^x[28]^x[26]^x[25]^x[23]^x[21]^x[17]^x[15]^x[12]^x[11]^x[4]^x[2]; + + bcc_next[22] = m[32]^m[33]^m[35]^m[36]^x[29]^x[28]^x[25]^x[22]^x[19]^x[18]^x[16]^x[15]^x[14]^x[13]^x[9]^x[8]^x[6]^x[5]^x[3]^x[0]; + + bcc_next[21] = m[34]^m[35]^m[36]^x[30]^x[29]^x[21]^x[20]^x[19]^x[17]^x[14]^x[12]^x[11]^x[10]^x[9]^x[7]^x[6]^x[4]^x[2]^x[1]^x[0]; + + bcc_next[20] = m[32]^m[33]^m[34]^m[35]^m[36]^x[31]^x[30]^x[27]^x[24]^x[16]^x[15]^x[3]; + + bcc_next[19] = m[32]^m[33]^m[34]^m[35]^x[31]^x[30]^x[29]^x[26]^x[23]^x[15]^x[14]^x[2]; + + bcc_next[18] = m[33]^m[34]^m[36]^x[27]^x[25]^x[24]^x[22]^x[20]^x[19]^x[18]^x[15]^x[14]^x[11]^x[10]^x[9]^x[8]^x[6]^x[5]^x[0]; + + bcc_next[17] = m[33]^m[35]^m[36]^x[31]^x[30]^x[29]^x[28]^x[27]^x[26]^x[23]^x[21]^x[20]^x[17]^x[15]^x[14]^x[11]^x[7]^x[6]^x[4]^x[1]^x[0]; + + bcc_next[16] = m[32]^m[34]^m[35]^x[30]^x[29]^x[28]^x[27]^x[26]^x[25]^x[22]^x[20]^x[19]^x[16]^x[14]^x[13]^x[10]^x[6]^x[5]^x[3]^x[0]; + + bcc_next[15] = m[33]^m[34]^x[31]^x[29]^x[28]^x[27]^x[26]^x[25]^x[24]^x[21]^x[19]^x[18]^x[15]^x[13]^x[12]^x[9]^x[5]^x[4]^x[2]; + + bcc_next[14] = m[32]^m[33]^x[30]^x[28]^x[27]^x[26]^x[25]^x[24]^x[23]^x[20]^x[18]^x[17]^x[14]^x[12]^x[11]^x[8]^x[4]^x[3]^x[1]; + + bcc_next[13] = m[36]^x[30]^x[28]^x[26]^x[25]^x[23]^x[22]^x[20]^x[18]^x[17]^x[16]^x[15]^x[9]^x[8]^x[7]^x[6]^x[5]^x[3]^x[2]^x[1]; + + bcc_next[12] = m[32]^m[35]^m[36]^x[31]^x[30]^x[28]^x[25]^x[22]^x[21]^x[20]^x[18]^x[17]^x[16]^x[14]^x[13]^x[11]^x[10]^x[9]^x[7]^x[4]^x[2]; + + bcc_next[11] = m[32]^m[34]^m[35]^m[36]^x[28]^x[21]^x[18]^x[17]^x[16]^x[12]^x[11]^x[5]^x[3]^x[0]; + + bcc_next[10] = m[33]^m[34]^m[35]^x[31]^x[27]^x[20]^x[17]^x[16]^x[15]^x[11]^x[10]^x[4]^x[2]; + + bcc_next[9] = m[33]^m[34]^m[36]^x[31]^x[29]^x[28]^x[27]^x[26]^x[24]^x[20]^x[18]^x[16]^x[14]^x[13]^x[11]^x[8]^x[6]^x[5]^x[3]^x[0]; + + bcc_next[8] = m[33]^m[35]^m[36]^x[31]^x[29]^x[26]^x[25]^x[24]^x[23]^x[20]^x[18]^x[17]^x[12]^x[11]^x[9]^x[8]^x[7]^x[6]^x[4]^x[2]^x[1]^x[0]; + + bcc_next[7] = m[32]^m[34]^m[35]^x[30]^x[28]^x[25]^x[24]^x[23]^x[22]^x[19]^x[17]^x[16]^x[11]^x[10]^x[8]^x[7]^x[6]^x[5]^x[3]^x[1]^x[0]; + + bcc_next[6] = m[32]^m[33]^m[34]^m[36]^x[30]^x[28]^x[23]^x[22]^x[21]^x[20]^x[19]^x[16]^x[13]^x[11]^x[8]^x[7]^x[4]^x[2]^x[1]; + + bcc_next[5] = m[33]^m[35]^m[36]^x[30]^x[28]^x[24]^x[22]^x[21]^x[13]^x[12]^x[11]^x[9]^x[8]^x[7]^x[5]^x[3]; + + bcc_next[4] = m[34]^m[35]^m[36]^x[31]^x[30]^x[28]^x[24]^x[23]^x[21]^x[19]^x[18]^x[15]^x[13]^x[12]^x[9]^x[7]^x[5]^x[4]^x[2]^x[1]^x[0]; + + bcc_next[3] = m[32]^m[33]^m[34]^m[35]^m[36]^x[31]^x[28]^x[24]^x[23]^x[22]^x[19]^x[17]^x[15]^x[14]^x[13]^x[12]^x[10]^x[9]^x[5]^x[4]^x[3]; + + bcc_next[2] = m[32]^m[33]^m[34]^m[35]^x[31]^x[30]^x[27]^x[23]^x[22]^x[21]^x[18]^x[16]^x[14]^x[13]^x[12]^x[11]^x[9]^x[8]^x[4]^x[3]^x[2]; + + bcc_next[1] = m[32]^m[33]^m[34]^x[31]^x[30]^x[29]^x[26]^x[22]^x[21]^x[20]^x[17]^x[15]^x[13]^x[12]^x[11]^x[10]^x[8]^x[7]^x[3]^x[2]^x[1]; + + bcc_next[0] = m[32]^m[33]^x[31]^x[30]^x[29]^x[28]^x[25]^x[21]^x[20]^x[19]^x[16]^x[14]^x[12]^x[11]^x[10]^x[9]^x[7]^x[6]^x[2]^x[1]^x[0]; + +end +endfunction + +function [7:0] bit_revers8; + input [7:0] din8; + begin + bit_revers8[0] = din8[7]; + bit_revers8[1] = din8[6]; + bit_revers8[2] = din8[5]; + bit_revers8[3] = din8[4]; + bit_revers8[4] = din8[3]; + bit_revers8[5] = din8[2]; + bit_revers8[6] = din8[1]; + bit_revers8[7] = din8[0]; + end +endfunction + + + +endmodule diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/SIM_CONFIG_V6.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/SIM_CONFIG_V6.v new file mode 100644 index 0000000..b41cf5f --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/SIM_CONFIG_V6.v @@ -0,0 +1,1398 @@ +////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2005 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Function Simulation Library Component +// / / Configuration Simulation Model +// /___/ /\ Filename : SIM_CONFIG_V6.v +// \ \ / \ Timestamp : +// \___\/\___\ +// +// Revision: +// 12/16/08 - Registers update and readback timing change from V5 version. +// 04/09/09 - Add ICAP support. +// 09/17/09 - Remove DCMLOCK pin (CR530867) +// 10/02/09 - Not write to frame out file after icap_init_done=1 (CR535320) +// 11/25/09 - Fix CRC (CR538766) +// 12/17/09 - Allow ICAP use without RBT file (CR537437) +// 01/04/10 - Remove cbc_reg from readback (543490). +// 01/12/10 - Reverse bits for readback (CR544212) +// 01/22/10 - Check abort condition with clock edge (CR545788) +// 02/04/10 - Support MMCM lock wait function (CR547918) +// 03/03/10 - set mode_sample_flag to 0 when mode pin set wrong (CR552316) +// 03/10/10 - Not check crc when icap initial time (CR553387) +// 05/19/10 - Not reset startup_set_pulse when rw_en=0 (CR559852) +// End Revision +//////////////////////////////////////////////////////////////////////////////// + +`timescale 1 ps / 1 ps + +module SIM_CONFIG_V6 ( BUSY, + CSOB, + DONE, + CCLK, + CSB, + D, + INITB, + M, + PROGB, + RDWRB + ); + + output BUSY; + output CSOB; + inout DONE; + input CCLK; + input CSB; + inout [31:0] D; + inout INITB; + input [2:0] M; + input PROGB; + input RDWRB; + + parameter DEVICE_ID = 32'h0; + parameter ICAP_SUPPORT = "FALSE"; + parameter ICAP_WIDTH = "X8"; + + localparam FRAME_RBT_OUT_FILENAME = "frame_data_v6_rbt_out.txt"; + localparam cfg_Tprog = 300000; // min PROG must be low, 300 ns + localparam cfg_Tpl = 100000; // max program latency us. + localparam STARTUP_PH0 = 3'b000; + localparam STARTUP_PH1 = 3'b001; + localparam STARTUP_PH2 = 3'b010; + localparam STARTUP_PH3 = 3'b011; + localparam STARTUP_PH4 = 3'b100; + localparam STARTUP_PH5 = 3'b101; + localparam STARTUP_PH6 = 3'b110; + localparam STARTUP_PH7 = 3'b111; + +// tri0 GSR, GTS, GWE; + wire GSR; + wire GTS; + wire GWE; + wire cclk_in; + wire init_b_in; + wire prog_b_in; + wire rdwr_b_in; + reg rdwr_b_in1; + reg checka_en = 0; + reg init_b_out = 1; + reg done_o = 0; + integer frame_data_fd; + integer farn = 0; + reg frame_data_wen = 0; + + tri1 p_up; + + reg por_b; + wire [2:0] m_in; + wire [31:0] d_in; + wire [31:0] d_out; + wire busy_out; + wire cso_b_out; + wire csi_b_in; + wire d_out_en; + wire pll_locked; + reg pll_lockwt; + wire init_b_t; + wire prog_b_t; + wire bus_en; + wire desync_flag; + wire crc_rst; + reg crc_bypass = 0; + reg icap_on = 0; + reg icap_clr = 0; + reg icap_sync = 0; + reg icap_desynch = 0; + reg icap_init_done = 0; + reg icap_init_done_dly = 0; + wire desynch_set1; + reg [1:0] icap_bw = 2'b00; + + assign DONE = p_up; + assign INITB = p_up; + assign glbl.GSR = GSR; + assign glbl.GTS = GTS; + assign pll_locked = (glbl.PLL_LOCKG === 0) ? 0 : 1; + + buf buf_busy (BUSY, busy_out); + buf buf_cso (CSOB, cso_b_out); + buf buf_cclk (cclk_in, CCLK); + buf buf_cs (csi_b_in, CSB); + + buf buf_din[31:0] (d_in, D); + bufif1 buf_dout[31:0] (D, d_out, d_out_en); + + buf buf_init (init_b_in, INITB); + buf buf_m_0 (m_in[0], M[0]); + buf buf_m_1 (m_in[1], M[1]); + buf buf_m_2 (m_in[2], M[2]); + buf buf_prog (prog_b_in, PROGB); + buf buf_rw (rdwr_b_in, RDWRB); + + time prog_pulse_low_edge = 0; + time prog_pulse_low = 0; + reg mode_sample_flag = 0; + reg buswid_flag_init = 0; + reg buswid_flag = 0; + wire [1:0] buswidth; + reg [1:0] buswidth_tmp = 2'b00; + reg [31:0] pack_in_reg = 32'b0; + reg [4:0] reg_addr; + reg new_data_in_flag = 0; + reg wr_flag = 0; + reg rd_flag = 0; + reg cmd_wr_flag = 0; + reg cmd_reg_new_flag = 0; + reg cmd_rd_flag = 0; + reg bus_sync_flag = 0; + reg conti_data_flag = 0; + integer wr_cnt = 0; + integer conti_data_cnt = 0; + integer rd_data_cnt = 0; + integer abort_cnt = 0; + reg [2:0] st_state = STARTUP_PH0; + reg startup_begin_flag = 0; + reg startup_end_flag = 0; + reg crc_ck = 0; + reg crc_err_flag = 0; + wire crc_err_flag_tot; + reg crc_err_flag_reg = 0; + wire crc_en; + reg [31:0] crc_curr = 32'b0; + reg [31:0] crc_new = 32'b0; + reg [36:0] crc_input = 32'b0; + reg [31:0] rbcrc_curr = 32'b0; + reg [31:0] rbcrc_new = 32'b0; + reg [36:0] rbcrc_input = 32'b0; + reg gwe_out = 0; + reg gts_out = 1; + reg [31:0] d_o = 32'h0; + reg [31:0] outbus = 32'h0; + reg [31:0] outbus_dly = 32'h0; + reg [31:0] outbus_dly1 = 32'h0; + reg busy_o = 0; + reg [31:0] tmp_val1; + reg [31:0] tmp_val2; + reg [31:0] crc_reg; + reg [31:0] far_reg; + reg [31:0] far_addr; + reg [31:0] fdri_reg; + reg [31:0] fdro_reg; + reg [4:0] cmd_reg; + reg [31:0] ctl0_reg = 32'b000xxxxxxxxxxxxxx000000100000xx1; + reg [31:0] mask_reg; + wire [31:0] stat_reg; + reg [31:0] lout_reg; + reg [31:0] cor0_reg = 32'b00000000000000000011111111101100; + reg [31:0] mfwr_reg; + reg [31:0] cbc_reg; + reg [31:0] idcode_reg; + reg [31:0] axss_reg; + reg [31:0] cor1_reg = 32'b0; + reg [31:0] csob_reg; + reg [31:0] wbstar_reg = 32'b0; + reg [31:0] timer_reg = 32'b0; + reg [31:0] rbcrc_hw_reg; + reg [31:0] rbcrc_sw_reg; + reg [31:0] rbcrc_live_reg; + reg [31:0] efar_reg; + reg [31:0] bootsts_reg = 32'b0; + reg [31:0] ctl1_reg = 32'b0; + reg [2:0] mode_pin_in = 3'b0; + reg [2:0] mode_reg; + reg crc_reset = 0; + reg gsr_set = 0; + reg gts_usr_b = 1; + reg done_pin_drv = 0; + + reg shutdown_set = 0; + reg desynch_set = 0; + reg [2:0] done_cycle_reg; + reg [2:0] gts_cycle_reg; + reg [2:0] gwe_cycle_reg; + reg init_pin; + reg init_rst = 0; + reg init_complete; + reg [2:0] nx_st_state = 3'b000; + reg ghigh_b = 0; + reg gts_cfg_b = 0; + reg eos_startup = 0; + reg startup_set = 0; + reg [1:0] startup_set_pulse = 2'b0; + reg abort_out_en = 0; + reg [31:0] tmp_dword; + reg [15:0] tmp_word; + reg [7:0] tmp_byte; + reg id_error_flag = 0; + reg iprog_b = 1; + reg i_init_b_cmd = 1; + reg i_init_b = 0; + reg [7:0] abort_status = 8'b0; + reg persist_en = 0; + reg rst_sync = 0; + reg abort_dis = 0; + reg [2:0] lock_cycle_reg = 3'b0; + reg rbcrc_no_pin = 0; + reg abort_flag_rst = 0; + reg gsr_st_out = 1; + reg gsr_cmd_out = 0; + reg gsr_cmd_out_pulse = 0; + reg d_o_en = 0; + wire rst_intl; + wire rw_en; + wire gsr_out; + wire cfgerr_b_flag; + reg abort_flag; + integer downcont_cnt = 0; +// reg rst_en = 1; + reg rst_en = 0; + reg prog_b_a = 1; + reg csbo_flag = 0; + reg rd_sw_en = 0; + integer csbo_cnt = 0; + reg [4:0] rd_reg_addr = 5'b0; + reg done_release = 0; + + triand (weak1, strong0) INITB=(mode_sample_flag) ? ~crc_err_flag_tot : init_b_out; + triand (weak1, strong0) DONE= done_o; + + initial begin + + case (ICAP_SUPPORT) + "FALSE" : icap_on = 0; + "TRUE" : icap_on = 1; + default : icap_on = 0; + endcase + + if (DEVICE_ID == 32'h0 && icap_on == 0) begin + $display("Attribute Error : The attribute DEVICE_ID on SIM_CONFIG_V6 instance %m is not set."); + end + + if (ICAP_SUPPORT == "TRUE") begin + case (ICAP_WIDTH) + "X8" : icap_bw = 2'b01; + "X16" : icap_bw = 2'b10; + "X32" : icap_bw = 2'b11; + default : icap_bw = 2'b01; + endcase + + frame_data_fd = $fopen(FRAME_RBT_OUT_FILENAME, "w"); + if (frame_data_fd != 0) begin + frame_data_wen = 1; + $fwriteh(frame_data_fd, "frame_address frame_data readback_crc_value\n"); + end + end + else begin + icap_bw = 2'b00; + frame_data_wen = 0; + end + + icap_sync = 0; + + end + + + assign GSR = gsr_out; + assign GTS = gts_out; + assign GWE = gwe_out; + assign busy_out = busy_o; + assign cfgerr_b_flag = rw_en & ~crc_err_flag_tot; + assign crc_err_flag_tot = id_error_flag | crc_err_flag_reg; +// assign d_out[7:0] = (abort_out_en ) ? abort_status : outbus_dly[7:0]; + assign d_out[7:0] = (abort_out_en ) ? abort_status : outbus[7:0]; + assign d_out[31:8] = (abort_out_en ) ? 24'b0 : outbus_dly[31:8]; + assign d_out_en = d_o_en; + assign cso_b_out = (csbo_flag== 1) ? 0 : 1; + assign crc_en = (icap_init_done) ? 0 : 1; + + + always @(posedge cclk_in) begin + outbus_dly <= outbus_dly1; + outbus_dly1 <= outbus; + end + + + always @(csi_b_in or abort_flag) + if (csi_b_in == 1) + busy_o = 1'b1; + else + if (abort_flag == 1) + busy_o = 1'b1; + else begin + @(posedge cclk_in); + @(posedge cclk_in); + @(posedge cclk_in) + busy_o = 1'b0; + end + + always @(abort_out_en or csi_b_in or rdwr_b_in && rd_flag ) + if (abort_out_en == 1) + d_o_en = 1; + else + d_o_en = rdwr_b_in & ~csi_b_in & rd_flag; + + + assign init_b_t = init_b_in & i_init_b_cmd; + + always @( negedge prog_b_in) begin + rst_en = 0; + rst_en <= #cfg_Tprog 1; + end + + always @( rst_en or init_rst or prog_b_in or iprog_b ) + if (icap_on == 0) begin + if (init_rst == 1) + init_b_out <= 0; + else begin + if ((prog_b_in == 0 ) && (rst_en == 1) || (iprog_b == 0)) + init_b_out <= 0; + else if ((prog_b_in == 1 ) && (rst_en == 1) || (iprog_b == 1)) + init_b_out <= #(cfg_Tpl) 1; + end + end + + always @(posedge id_error_flag) begin + init_rst <= 1; + init_rst <= #cfg_Tprog 0; + end + + always @( rst_en or prog_b_in or prog_pulse_low) + if (rst_en == 1) begin + if (prog_pulse_low==cfg_Tprog) begin + prog_b_a = 0; + prog_b_a <= #500 1; + end + else + prog_b_a = prog_b_in; + end + else + prog_b_a = 1; + + initial begin + por_b = 0; + por_b = #400000 1; + end + + assign prog_b_t = prog_b_a & iprog_b & por_b; + + assign rst_intl = (prog_b_t==0 ) ? 0 : 1; + + always @( init_b_t or prog_b_t) + if (prog_b_t == 0) + mode_sample_flag <= 0; + else if (init_b_t && mode_sample_flag == 0) begin + if (prog_b_t == 1) begin + mode_pin_in <= m_in; + if (m_in !== 3'b110) begin + mode_sample_flag <= 0; + if ( icap_on == 0) + $display("Error: input M is %h. Only Slave SelectMAP mode M=110 supported on SIM_CONFIG_V6 instance %m.", m_in); + end + else + mode_sample_flag <= #1 1; + end + end + + always @(posedge init_b_t ) + if (prog_b_t != 1) begin + if ($time != 0 && icap_on == 0) + $display("Error: PROGB is not high when INITB goes high on SIM_CONFIG_V6 instance %m at time %t.", $time); + end + + always @(m_in) + if (mode_sample_flag == 1 && persist_en == 1 && icap_on == 0) + $display("Error : Mode pine M[2:0] changed after rising edge of INITB on SIM_CONFIG_V6 instance %m at time %t.", $time); + + always @(posedge prog_b_in or negedge prog_b_in) + if (prog_b_in == 0) + prog_pulse_low_edge <= $time; + else if (prog_b_in == 1 && $time > 0) begin + prog_pulse_low = $time - prog_pulse_low_edge; + if (prog_pulse_low < cfg_Tprog && icap_on == 0) + $display("Error: Low time of PROGB is less than required minimum Tprogram time %d on SIM_CONFIG_V6 instance %m at time %t.", cfg_Tprog, $time); + end + + assign bus_en = (mode_sample_flag == 1 && csi_b_in ==0) ? 1 : 0; + + always @(posedge cclk_in or negedge rst_intl or posedge desynch_set1) + if (rst_intl == 0 || desynch_set1 == 1) begin + buswid_flag_init <= 0; + buswid_flag <= 0; + buswidth_tmp <= 2'b00; + end + else + if (buswid_flag == 0) begin + if (bus_en == 1 && rdwr_b_in == 0) begin + tmp_byte = bit_revers8(d_in[7:0]); + if (buswid_flag_init == 0) begin + if (tmp_byte == 8'hBB) + buswid_flag_init <= 1; + end + else begin + if (tmp_byte == 8'h11) begin + buswid_flag <= 1; + buswidth_tmp <= 2'b01; + end + else if (tmp_byte == 8'h22) begin + buswid_flag <= 1; + buswidth_tmp <= 2'b10; + end + else if (tmp_byte == 8'h44) begin + buswid_flag <= 1; + buswidth_tmp <= 2'b11; + end + else begin + buswid_flag <= 0; + buswidth_tmp <= 2'b00; + buswid_flag_init <= 0; + if (icap_on == 0) + $display("Error : BUS Width Auto Dection did not find 0x11 or 0x22 or 0x44 on D[7:0] followed 0xBB on SIM_CONFIG_V6 instance %m at time %t.", $time); + else + $display("Error : BUS Width Auto Dection did not find 0x11 or 0x22 or 0x44 on dix[7:0] followed 0xBB on ICAP_VIRTEX6 instance %m at time %t.", $time); + + end + end + end + end + + assign buswidth[1:0] = (icap_on == 1 && icap_init_done == 1) ? icap_bw[1:0] : buswidth_tmp[1:0]; + assign rw_en_tmp = (bus_en == 1 ) ? 1 : 0; +// assign rw_en = (((icap_on == 0 || icap_init_done == 0) && buswid_flag == 1) || icap_init_done == 1) ? rw_en_tmp : 0; + assign rw_en = ( buswid_flag == 1) ? rw_en_tmp : 0; + assign desynch_set1 = desynch_set | icap_desynch; + assign desync_flag = ~rst_intl | desynch_set1 | crc_err_flag | id_error_flag; + + always @(posedge eos_startup) + if (icap_on == 1) begin + $fclose(frame_data_fd); + icap_init_done <= 1; + @(posedge cclk_in); + @(posedge cclk_in) + if (icap_init_done_dly == 0) + icap_desynch <= 1; + @(posedge cclk_in); + @(posedge cclk_in) begin + icap_desynch <= 0; + icap_init_done_dly <= 1; + end + @(posedge cclk_in); + @(posedge cclk_in); + @(posedge cclk_in); + end + else begin + icap_clr <= 0; + icap_desynch <= 0; + end + + always @(posedge cclk_in or negedge rdwr_b_in) + if (rdwr_b_in == 0) + rd_sw_en <= 0; + else begin + if (csi_b_in == 1 && rdwr_b_in ==1) + rd_sw_en <= 1; + end + + always @(posedge cclk_in or posedge desync_flag or posedge csi_b_in) + if (desync_flag == 1 ) begin + pack_in_reg <= 32'b0; + new_data_in_flag <= 0; + bus_sync_flag <= 0; + wr_cnt <= 0; + wr_flag <= 0; + rd_flag <= 0; + end + else if (icap_init_done == 1 && csi_b_in == 1 && rdwr_b_in == 0) begin + pack_in_reg <= 32'b0; + new_data_in_flag <= 0; + wr_cnt <= 0; + end + else begin + if (icap_clr == 1) begin + pack_in_reg <= 32'b0; + new_data_in_flag <= 0; + wr_cnt <= 0; + wr_flag <= 0; + rd_flag <= 0; + end + else if (rw_en == 1 ) begin + if (rdwr_b_in == 0) begin + wr_flag <= 1; + rd_flag <= 0; + if (buswidth == 2'b01 || (icap_sync == 1 && bus_sync_flag == 0)) begin + tmp_byte = bit_revers8(d_in[7:0]); + if (bus_sync_flag == 0) begin + if (pack_in_reg[23:16] == 8'hAA && pack_in_reg[15:8] == 8'h99 + && pack_in_reg[7:0] == 8'h55 && tmp_byte == 8'h66) begin + bus_sync_flag <= 1; + new_data_in_flag <= 0; + wr_cnt <= 0; + end + else begin + pack_in_reg[31:24] <= pack_in_reg[23:16]; + pack_in_reg[23:16] <= pack_in_reg[15:8]; + pack_in_reg[15:8] <= pack_in_reg[7:0]; + pack_in_reg[7:0] <= tmp_byte; + end + end + else begin + if (wr_cnt == 0) begin + pack_in_reg[31:24] <= tmp_byte; + new_data_in_flag <= 0; + wr_cnt <= 1; + end + else if (wr_cnt == 1) begin + pack_in_reg[23:16] <= tmp_byte; + new_data_in_flag <= 0; + wr_cnt <= 2; + end + else if (wr_cnt == 2) begin + pack_in_reg[15:8] <= tmp_byte; + new_data_in_flag <= 0; + wr_cnt <= 3; + end + else if (wr_cnt == 3) begin + pack_in_reg[7:0] <= tmp_byte; + new_data_in_flag <= 1; + wr_cnt <= 0; + end + end + end + else if (buswidth == 2'b10) begin + tmp_word = {bit_revers8(d_in[15:8]), bit_revers8(d_in[7:0])}; + if (bus_sync_flag == 0) begin + if (pack_in_reg[15:0] == 16'hAA99 && tmp_word ==16'h5566) begin + wr_cnt <= 0; + bus_sync_flag <= 1; + new_data_in_flag <= 0; + end + else begin + pack_in_reg[31:16] <= pack_in_reg[15:0]; + pack_in_reg[15:0] <= tmp_word; + new_data_in_flag <= 0; + wr_cnt <= 0; + end + end + else begin + if (wr_cnt == 0) begin + pack_in_reg[31:16] <= tmp_word; + new_data_in_flag <= 0; + wr_cnt <= 1; + end + else if (wr_cnt == 1) begin + pack_in_reg[15:0] <= tmp_word; + new_data_in_flag <= 1; + wr_cnt <= 0; + end + end + end + else if (buswidth == 2'b11 ) begin + tmp_dword = {bit_revers8(d_in[31:24]), bit_revers8(d_in[23:16]), bit_revers8(d_in[15:8]), + bit_revers8(d_in[7:0])}; + pack_in_reg[31:0] <= tmp_dword; + if (bus_sync_flag == 0) begin + if (tmp_dword == 32'hAA995566) begin + bus_sync_flag <= 1; + new_data_in_flag <= 0; + end + end + else begin + pack_in_reg[31:0] <= tmp_dword; + new_data_in_flag <= 1; + end + end + end + else begin + wr_flag <= 0; + new_data_in_flag <= 0; + if (rd_sw_en ==1) + rd_flag <= 1; + end + end + else begin + wr_flag <= 0; + rd_flag <= 0; + new_data_in_flag <= 0; + end + end + + always @(negedge cclk_in or negedge rst_intl) + if (rst_intl == 0) begin + conti_data_flag <= 0; + conti_data_cnt <= 0; + cmd_wr_flag <= 0; + cmd_rd_flag <= 0; + id_error_flag <= 0; + crc_curr <= 32'b0; + crc_ck <= 0; + csbo_cnt <= 0; + csbo_flag <= 0; + downcont_cnt <= 0; + rd_data_cnt <= 0; + end + else begin + if (icap_clr == 1) begin + conti_data_flag <= 0; + conti_data_cnt <= 0; + cmd_wr_flag <= 0; + cmd_rd_flag <= 0; + id_error_flag <= 0; + crc_curr <= 32'b0; + crc_ck <= 0; + csbo_cnt <= 0; + csbo_flag <= 0; + downcont_cnt <= 0; + rd_data_cnt <= 0; + end + if (crc_reset == 1 ) begin + crc_reg <= 32'b0; + crc_ck <= 0; + crc_curr <= 32'b0; + end + if (crc_ck == 1) + crc_curr <= 32'b0; + + if (desynch_set1 == 1 || crc_err_flag == 1) begin + conti_data_flag <= 0; + conti_data_cnt <= 0; + cmd_wr_flag <= 0; + cmd_rd_flag <= 0; + cmd_reg_new_flag <= 0; + crc_ck <= 0; + csbo_cnt <= 0; + csbo_flag <= 0; + downcont_cnt <= 0; + rd_data_cnt <= 0; + end + + if (new_data_in_flag == 1 && wr_flag == 1) begin + if (conti_data_flag == 1 ) begin + case (reg_addr) + 5'b00000 : begin + crc_reg <= pack_in_reg; + crc_ck <= 1; + end + 5'b00001 : far_reg <= pack_in_reg; + 5'b00010 : fdri_reg <= pack_in_reg; + 5'b00100 : cmd_reg <= pack_in_reg[4:0]; + 5'b00101 : ctl0_reg <= (pack_in_reg & mask_reg) | (ctl0_reg & ~mask_reg); + 5'b00110 : mask_reg <= pack_in_reg; + 5'b01000 : lout_reg <= pack_in_reg; + 5'b01001 : cor0_reg <= pack_in_reg; + 5'b01010 : mfwr_reg <= pack_in_reg; + 5'b01011 : cbc_reg <= pack_in_reg; + 5'b01100 : begin + idcode_reg <= pack_in_reg; + if (pack_in_reg[27:0] != DEVICE_ID[27:0]) begin + id_error_flag <= 1; + if (icap_on == 0) + $display("Error : written value to IDCODE register is %h which does not match DEVICE ID %h on SIM_CONFIG_V6 instance %m at time %t.", pack_in_reg, DEVICE_ID, $time); + else + $display("Error : written value to IDCODE register is %h which does not match DEVICE ID %h on ICAP_VIRTEX6 instance %m at time %t.", pack_in_reg, DEVICE_ID, $time); + end + else + id_error_flag <= 0; + end + 5'b01101 : axss_reg <= pack_in_reg; + 5'b01110 : cor1_reg <= pack_in_reg; + 5'b01111 : csob_reg <= pack_in_reg; + 5'b10000 : wbstar_reg <= pack_in_reg; + 5'b10001 : timer_reg <= pack_in_reg; + 5'b10011 : rbcrc_sw_reg <= pack_in_reg; + 5'b11000 : ctl1_reg <= (pack_in_reg & mask_reg) | (ctl1_reg & ~mask_reg); + endcase + + if (reg_addr != 5'b00000) + crc_ck <= 0; + + if (reg_addr == 5'b00100) + cmd_reg_new_flag <= 1; + else + cmd_reg_new_flag <= 0; + + if (crc_en == 1) begin + if (reg_addr == 5'h04 && pack_in_reg[4:0] == 5'b00111) + crc_curr[31:0] = 32'b0; + else begin + if ( reg_addr != 5'h0f && reg_addr != 5'h12 && reg_addr != 5'h14 + && reg_addr != 5'h15 && reg_addr != 5'h16 && reg_addr != 5'h00) begin + crc_input[36:0] = {reg_addr, pack_in_reg}; + crc_new[31:0] = bcc_next(crc_curr, crc_input); + crc_curr[31:0] <= crc_new; + end + end + end + + if (conti_data_cnt <= 1) begin + conti_data_cnt <= 0; + end + else + conti_data_cnt <= conti_data_cnt - 1; + end + else if (conti_data_flag == 0 ) begin + if ( downcont_cnt >= 1) begin + if (crc_en == 1) begin + crc_input[36:0] = {5'b00010, pack_in_reg}; + crc_new[31:0] = bcc_next(crc_curr, crc_input); + crc_curr[31:0] <= crc_new; + end + if (farn <= 80) + farn <= farn + 1; + else begin + far_addr <= far_addr + 1; + farn <= 0; + end + if (frame_data_wen == 1 && icap_init_done == 0) begin + rbcrc_input[36:0] = {5'b00011, pack_in_reg}; + rbcrc_new[31:0] = bcc_next(rbcrc_curr, rbcrc_input); + rbcrc_curr[31:0] <= rbcrc_new; + $fwriteh(frame_data_fd, far_addr); + $fwriteh(frame_data_fd, "\t"); + $fwriteh(frame_data_fd, pack_in_reg); + $fwriteh(frame_data_fd, "\t"); + $fwriteh(frame_data_fd, rbcrc_new); + $fwriteh(frame_data_fd, "\n"); + end + end + + if (pack_in_reg[31:29] == 3'b010 && downcont_cnt == 0 ) begin + cmd_rd_flag <= 0; + cmd_wr_flag <= 0; + conti_data_flag <= 0; + conti_data_cnt <= 0; + downcont_cnt <= pack_in_reg[26:0]; + far_addr <= far_reg; + end + else if (pack_in_reg[31:29] == 3'b001) begin // type 1 package + if (pack_in_reg[28:27] == 2'b01 && downcont_cnt == 0) begin + if (pack_in_reg[10:0] != 10'b0) begin + cmd_rd_flag <= 1; + cmd_wr_flag <= 0; + rd_data_cnt <= 4; + conti_data_cnt <= 0; + conti_data_flag <= 0; + rd_reg_addr <= pack_in_reg[17:13]; + end + end + else if (pack_in_reg[28:27] == 2'b10 && downcont_cnt == 0) begin + if (pack_in_reg[17:13] == 5'b01111) begin // csbo reg + csob_reg <= pack_in_reg; + csbo_cnt = pack_in_reg[10:0]; + csbo_flag <= 1; + conti_data_flag = 0; + reg_addr <= pack_in_reg[17:13]; + cmd_wr_flag <= 1; + conti_data_cnt <= 5'b0; + end + else begin + if (pack_in_reg[10:0] != 10'b0) begin + cmd_rd_flag <= 0; + cmd_wr_flag <= 1; + conti_data_flag <= 1; + conti_data_cnt <= pack_in_reg[10:0]; + reg_addr <= pack_in_reg[17:13]; + end + else begin + cmd_rd_flag <= 0; + cmd_wr_flag <= 1; + conti_data_flag <= 0; + conti_data_cnt <= 0; + reg_addr <= pack_in_reg[17:13]; + end + end + end + else begin + cmd_wr_flag <= 0; + conti_data_flag <= 0; + conti_data_cnt <= 0; + end + end + cmd_reg_new_flag <= 0; + crc_ck <= 0; + end // if (conti_data_flag == 0 ) + if (csbo_cnt != 0 ) begin + if (csbo_flag == 1) + csbo_cnt <= csbo_cnt - 1; + end + else + csbo_flag <= 0; + + if (conti_data_cnt == 5'b00001 ) + conti_data_flag <= 0; + + end + + if (rw_en == 1) begin + if (rd_data_cnt == 1 && rd_flag == 1) + rd_data_cnt <= 0; + else if (rd_data_cnt == 0 && rd_flag == 1) + cmd_rd_flag <= 0; + else if (cmd_rd_flag ==1 && rd_flag == 1) + rd_data_cnt <= rd_data_cnt - 1; + + if (downcont_cnt >= 1 && conti_data_flag == 0 && new_data_in_flag == 1 && wr_flag == 1) + downcont_cnt <= downcont_cnt - 1; + end + + if (crc_ck == 1 || icap_init_done == 0) + crc_ck <= 0; + end + + + always @(posedge cclk_in or negedge rst_intl) + if (rst_intl == 0) begin + outbus <= 32'b0; + end + else begin + if (cmd_rd_flag == 1 && rdwr_b_in == 1 && csi_b_in == 0) begin + case (rd_reg_addr) + 5'b00000 : if (buswidth == 2'b01) + rdbk_byte(crc_reg); + else if (buswidth == 2'b10) + rdbk_wd(crc_reg); + else if (buswidth == 2'b11) + rdbk_2wd(crc_reg); + 5'b00001 : if (buswidth == 2'b01) + rdbk_byte(far_reg); + else if (buswidth == 2'b10) + rdbk_wd(far_reg); + else if (buswidth == 2'b11) + rdbk_2wd(far_reg); + 5'b00011 : if (buswidth == 2'b01) + rdbk_byte(fdro_reg); + else if (buswidth == 2'b10) + rdbk_wd(fdro_reg); + else if (buswidth == 2'b11) + rdbk_2wd(fdro_reg); + 5'b00100 : if (buswidth == 2'b01) + rdbk_byte(cmd_reg); + else if (buswidth == 2'b10) + rdbk_wd(cmd_reg); + else if (buswidth == 2'b11) + rdbk_2wd(cmd_reg); + 5'b00101 : if (buswidth == 2'b01) + rdbk_byte(ctl0_reg); + else if (buswidth == 2'b10) + rdbk_wd(ctl0_reg); + else if (buswidth == 2'b11) + rdbk_2wd(ctl0_reg); + 5'b00110 : if (buswidth == 2'b01) + rdbk_byte(mask_reg); + else if (buswidth == 2'b10) + rdbk_wd(mask_reg); + else if (buswidth == 2'b11) + rdbk_2wd(mask_reg); + 5'b00111 : if (buswidth == 2'b01) + rdbk_byte(stat_reg); + else if (buswidth == 2'b10) + rdbk_wd(stat_reg); + else if (buswidth == 2'b11) + rdbk_2wd(stat_reg); + 5'b01001 : if (buswidth == 2'b01) + rdbk_byte(cor0_reg); + else if (buswidth == 2'b10) + rdbk_wd(cor0_reg); + else if (buswidth == 2'b11) + rdbk_2wd(cor0_reg); + 5'b01100 : if (buswidth == 2'b01) + rdbk_byte(DEVICE_ID); + else if (buswidth == 2'b10) + rdbk_wd(DEVICE_ID); + else if (buswidth == 2'b11) + rdbk_2wd(DEVICE_ID); + 5'b01101 : if (buswidth == 2'b01) + rdbk_byte(axss_reg); + else if (buswidth == 2'b10) + rdbk_wd(axss_reg); + else if (buswidth == 2'b11) + rdbk_2wd(axss_reg); + 5'b01110 : if (buswidth == 2'b01) + rdbk_byte(cor1_reg); + else if (buswidth == 2'b10) + rdbk_wd(cor1_reg); + else if (buswidth == 2'b11) + rdbk_2wd(cor1_reg); + 5'b10000 : if (buswidth == 2'b01) + rdbk_byte(wbstar_reg); + else if (buswidth == 2'b10) + rdbk_wd(wbstar_reg); + else if (buswidth == 2'b11) + rdbk_2wd(wbstar_reg); + 5'b10001 : if (buswidth == 2'b01) + rdbk_byte(timer_reg); + else if (buswidth == 2'b10) + rdbk_wd(timer_reg); + else if (buswidth == 2'b11) + rdbk_2wd(timer_reg); + 5'b10010 : if (buswidth == 2'b01) + rdbk_byte(rbcrc_hw_reg); + else if (buswidth == 2'b10) + rdbk_wd(rbcrc_hw_reg); + else if (buswidth == 2'b11) + rdbk_2wd(rbcrc_hw_reg); + 5'b10011 : if (buswidth == 2'b01) + rdbk_byte(rbcrc_sw_reg); + else if (buswidth == 2'b10) + rdbk_wd(rbcrc_sw_reg); + else if (buswidth == 2'b11) + rdbk_2wd(rbcrc_sw_reg); + 5'b10100 : if (buswidth == 2'b01) + rdbk_byte(rbcrc_live_reg); + else if (buswidth == 2'b10) + rdbk_wd(rbcrc_live_reg); + else if (buswidth == 2'b11) + rdbk_2wd(rbcrc_live_reg); + 5'b10101 : if (buswidth == 2'b01) + rdbk_byte(efar_reg); + else if (buswidth == 2'b10) + rdbk_wd(efar_reg); + else if (buswidth == 2'b11) + rdbk_2wd(efar_reg); + 5'b10110 : if (buswidth == 2'b01) + rdbk_byte(bootsts_reg); + else if (buswidth == 2'b10) + rdbk_wd(bootsts_reg); + else if (buswidth == 2'b11) + rdbk_2wd(bootsts_reg); + 5'b11000 : if (buswidth == 2'b01) + rdbk_byte(ctl1_reg); + else if (buswidth == 2'b10) + rdbk_wd(ctl1_reg); + else if (buswidth == 2'b11) + rdbk_2wd(ctl1_reg); + endcase + end + else + outbus <= 32'b0; + end + + + + assign crc_rst = crc_reset | ~rst_intl; + + always @(posedge cclk_in or posedge crc_rst ) + if (crc_rst == 1) + crc_err_flag <= 0; + else + if (crc_ck == 1) begin + if (crc_curr[31:0] != crc_reg[31:0]) + crc_err_flag <= 1; + else + crc_err_flag <= 0; + end + else + crc_err_flag <= 0; + + always @(posedge crc_err_flag or negedge rst_intl or posedge bus_sync_flag) + if (rst_intl == 0) + crc_err_flag_reg <= 0; + else if (crc_err_flag == 1) + crc_err_flag_reg <= 1; + else + crc_err_flag_reg <= 0; + + always @(posedge cclk_in or negedge rst_intl) + if (rst_intl == 0) begin + startup_set <= 0; + crc_reset <= 0; + gsr_cmd_out <= 0; + shutdown_set <= 0; + desynch_set <= 0; + ghigh_b <= 0; + end + else begin + if (cmd_reg_new_flag == 1) begin + if (cmd_reg == 5'b00011) + ghigh_b <= 1; + else if (cmd_reg == 5'b01000) + ghigh_b <= 0; + + if (cmd_reg == 5'b00101) + startup_set <= 1; + + if (cmd_reg == 5'b00111) + crc_reset <= 1; + + if (cmd_reg == 5'b01010) + gsr_cmd_out <= 1; + + if (cmd_reg == 5'b01011) + shutdown_set <= 1; + + if (cmd_reg == 5'b01101) + desynch_set <= 1; + + if (cmd_reg == 5'b01111) begin + iprog_b <= 0; + i_init_b_cmd <= 0; + iprog_b <= #cfg_Tprog 1; + i_init_b_cmd <=#(cfg_Tprog + cfg_Tpl) 1; + end + end + else begin + startup_set <= 0; + crc_reset <= 0; + gsr_cmd_out <= 0; + shutdown_set <= 0; + desynch_set <= 0; + end + end + + always @(posedge startup_set or posedge desynch_set or negedge rw_en ) + if (rw_en == 1) + begin + if (startup_set_pulse == 2'b00 && startup_set ==1) begin + if (icap_on == 0) + startup_set_pulse <= 2'b01; + else begin + startup_set_pulse <= 2'b11; + @(posedge cclk_in ) + startup_set_pulse <= 2'b00; + end + end + else if (desynch_set == 1 && startup_set_pulse == 2'b01) begin + startup_set_pulse <= 2'b11; + @(posedge cclk_in ) + startup_set_pulse <= 2'b00; + end + end + + always @(posedge gsr_cmd_out or negedge rw_en) + if (rw_en == 1) + begin + gsr_cmd_out_pulse <= 1; + @(posedge cclk_in ); + @(posedge cclk_in ) + gsr_cmd_out_pulse <= 0; + end + + always @(ctl0_reg) begin + if (ctl0_reg[9] == 1) + abort_dis = 1; + else + abort_dis = 0; + + if (ctl0_reg[3] == 1) + persist_en = 1; + else + persist_en = 0; + + if (ctl0_reg[0] == 1) + gts_usr_b = 1; + else + gts_usr_b = 0; + end + + always @(cor0_reg) + begin + done_cycle_reg = cor0_reg[14:12]; + lock_cycle_reg = cor0_reg[8:6]; + gts_cycle_reg = cor0_reg[5:3]; + gwe_cycle_reg = cor0_reg[2:0]; + + if (cor0_reg[24] == 1'b1) + done_pin_drv = 1; + else + done_pin_drv = 0; + + if (cor0_reg[28] == 1'b1) + crc_bypass = 1; + else + crc_bypass = 0; + end + + always @(cor1_reg) + rbcrc_no_pin = cor1_reg[8]; + + assign stat_reg[31:27] = 5'b000x0; + assign stat_reg[26:25] = buswidth; + assign stat_reg[24:21] = 4'bxxx0; + assign stat_reg[20:18] = st_state; + assign stat_reg[17] = 1'b0; + assign stat_reg[16] = 1'b0; + assign stat_reg[15] = id_error_flag; + assign stat_reg[14] = DONE; + assign stat_reg[13] = (done_o !== 0) ? 1 : 0; + assign stat_reg[12] = INITB; + assign stat_reg[11] = mode_sample_flag; + assign stat_reg[10:8] = mode_pin_in; + assign stat_reg[7] = ghigh_b; + assign stat_reg[6] = gwe_out; + assign stat_reg[5] = gts_cfg_b; + assign stat_reg[4] = eos_startup; + assign stat_reg[3] = 1'b1; + assign stat_reg[2] = pll_locked; + assign stat_reg[1] = 1'b0; + assign stat_reg[0] = crc_err_flag_reg; + + + always @(posedge cclk_in or negedge rst_intl) + if (rst_intl == 0) begin + st_state <= STARTUP_PH0; + startup_begin_flag <= 0; + startup_end_flag <= 0; + end + else begin + if (nx_st_state == STARTUP_PH1) begin + startup_begin_flag <= 1; + startup_end_flag <= 0; + end + else if (st_state == STARTUP_PH7) begin + startup_end_flag <= 1; + startup_begin_flag <= 0; + end + if ((lock_cycle_reg == 3'b111) || (pll_locked == 1) || (pll_locked == 0 && st_state != lock_cycle_reg)) begin + st_state <= nx_st_state; + end + else + st_state <= st_state; + end + + always @(st_state or startup_set_pulse or DONE ) begin + + if (((st_state == done_cycle_reg) && (DONE !== 0)) || (st_state != done_cycle_reg)) + case (st_state) + STARTUP_PH0 : if (startup_set_pulse == 2'b11 ) + nx_st_state = STARTUP_PH1; + else + nx_st_state = STARTUP_PH0; + STARTUP_PH1 : nx_st_state = STARTUP_PH2; + + STARTUP_PH2 : nx_st_state = STARTUP_PH3; + + STARTUP_PH3 : nx_st_state = STARTUP_PH4; + + STARTUP_PH4 : nx_st_state = STARTUP_PH5; + + STARTUP_PH5 : nx_st_state = STARTUP_PH6; + + STARTUP_PH6 : nx_st_state = STARTUP_PH7; + + STARTUP_PH7 : nx_st_state = STARTUP_PH0; + endcase + end + + always @(posedge cclk_in or negedge rst_intl ) + if (rst_intl == 0) begin + gwe_out <= 0; + gts_out <= 1; + eos_startup <= 0; + gsr_st_out <= 1; + done_o <= 0; + end + else begin + + if (nx_st_state == done_cycle_reg || st_state == done_cycle_reg) begin + if (DONE !== 0 || done_pin_drv == 1) + done_o <= 1'b1; + else + done_o <= 1'bz; + end + + if (st_state == gwe_cycle_reg) + gwe_out <= 1; + + if (st_state == gts_cycle_reg ) + gts_out <= 0; + + if (st_state == STARTUP_PH6 ) + gsr_st_out <= 0; + + if (st_state == STARTUP_PH7 ) + eos_startup <= 1; + + end + + assign gsr_out = gsr_st_out | gsr_cmd_out; + + always @(posedge cclk_in or negedge rst_intl or + posedge abort_flag_rst or posedge csi_b_in) + if (rst_intl == 0 || abort_flag_rst == 1 || csi_b_in == 1) begin + abort_flag <= 0; + checka_en <= 0; + rdwr_b_in1 <= rdwr_b_in; + end + else begin + if ( abort_dis == 0 && csi_b_in == 0) begin + if ((rdwr_b_in1 != rdwr_b_in) && checka_en != 0) begin + abort_flag <= 1; + if (icap_on == 0) + $display(" Warning : RDWRB changes when CSB low, which causes Configuration abort on SIM_CONFIG_V6 instance %m at time %t.", $time); + end + end + else + abort_flag <= 0; + + rdwr_b_in1 <= rdwr_b_in; + checka_en <= 1; + end + + always @(posedge abort_flag) + begin + abort_out_en <= 1; + abort_status <= {cfgerr_b_flag, bus_sync_flag, 1'b0, 1'b1, 4'b1111}; + @(posedge cclk_in) + abort_status <= {cfgerr_b_flag, 1'b1, 1'b0, 1'b0, 4'b1111}; + @(posedge cclk_in) + abort_status <= {cfgerr_b_flag, 1'b0, 1'b0, 1'b0, 4'b1111}; + @(posedge cclk_in) + abort_status <= {cfgerr_b_flag, 1'b0, 1'b0, 1'b1, 4'b1111}; + @(posedge cclk_in) begin + abort_out_en <= 0; + abort_flag_rst <= 1; + end + @(posedge cclk_in) + abort_flag_rst <= 0; + end + + +function [31:0] bcc_next; + input [31:0] bcc; + input [36:0] in; +reg [31:0] x; +reg [36:0] m; +begin + m = in; + x = in[31:0] ^ bcc; + + bcc_next[31] = m[32]^m[36]^x[31]^x[30]^x[29]^x[28]^x[27]^x[24]^x[20]^x[19]^x[18]^x[15]^x[13]^x[11]^x[10]^x[9]^x[8]^x[6]^x[5]^x[1]^x[0]; + + bcc_next[30] = m[35]^x[31]^x[30]^x[29]^x[28]^x[27]^x[26]^x[23]^x[19]^x[18]^x[17]^x[14]^x[12]^x[10]^x[9]^x[8]^x[7]^x[5]^x[4]^x[0]; + + bcc_next[29] = m[34]^x[30]^x[29]^x[28]^x[27]^x[26]^x[25]^x[22]^x[18]^x[17]^x[16]^x[13]^x[11]^x[9]^x[8]^x[7]^x[6]^x[4]^x[3]; + + bcc_next[28] = m[33]^x[29]^x[28]^x[27]^x[26]^x[25]^x[24]^x[21]^x[17]^x[16]^x[15]^x[12]^x[10]^x[8]^x[7]^x[6]^x[5]^x[3]^x[2]; + + bcc_next[27] = m[32]^x[28]^x[27]^x[26]^x[25]^x[24]^x[23]^x[20]^x[16]^x[15]^x[14]^x[11]^x[9]^x[7]^x[6]^x[5]^x[4]^x[2]^x[1]; + + bcc_next[26] = x[31]^x[27]^x[26]^x[25]^x[24]^x[23]^x[22]^x[19]^x[15]^x[14]^x[13]^x[10]^x[8]^x[6]^x[5]^x[4]^x[3]^x[1]^x[0]; + + bcc_next[25] = m[32]^m[36]^x[31]^x[29]^x[28]^x[27]^x[26]^x[25]^x[23]^x[22]^x[21]^x[20]^x[19]^x[15]^x[14]^x[12]^x[11]^x[10]^x[8]^x[7]^x[6]^x[4]^x[3]^x[2]^x[1]; + + bcc_next[24] = m[35]^x[31]^x[30]^x[28]^x[27]^x[26]^x[25]^x[24]^x[22]^x[21]^x[20]^x[19]^x[18]^x[14]^x[13]^x[11]^x[10]^x[9]^x[7]^x[6]^x[5]^x[3]^x[2]^x[1]^x[0]; + + bcc_next[23] = m[32]^m[34]^m[36]^x[31]^x[28]^x[26]^x[25]^x[23]^x[21]^x[17]^x[15]^x[12]^x[11]^x[4]^x[2]; + + bcc_next[22] = m[32]^m[33]^m[35]^m[36]^x[29]^x[28]^x[25]^x[22]^x[19]^x[18]^x[16]^x[15]^x[14]^x[13]^x[9]^x[8]^x[6]^x[5]^x[3]^x[0]; + + bcc_next[21] = m[34]^m[35]^m[36]^x[30]^x[29]^x[21]^x[20]^x[19]^x[17]^x[14]^x[12]^x[11]^x[10]^x[9]^x[7]^x[6]^x[4]^x[2]^x[1]^x[0]; + + bcc_next[20] = m[32]^m[33]^m[34]^m[35]^m[36]^x[31]^x[30]^x[27]^x[24]^x[16]^x[15]^x[3]; + + bcc_next[19] = m[32]^m[33]^m[34]^m[35]^x[31]^x[30]^x[29]^x[26]^x[23]^x[15]^x[14]^x[2]; + + bcc_next[18] = m[33]^m[34]^m[36]^x[27]^x[25]^x[24]^x[22]^x[20]^x[19]^x[18]^x[15]^x[14]^x[11]^x[10]^x[9]^x[8]^x[6]^x[5]^x[0]; + + bcc_next[17] = m[33]^m[35]^m[36]^x[31]^x[30]^x[29]^x[28]^x[27]^x[26]^x[23]^x[21]^x[20]^x[17]^x[15]^x[14]^x[11]^x[7]^x[6]^x[4]^x[1]^x[0]; + + bcc_next[16] = m[32]^m[34]^m[35]^x[30]^x[29]^x[28]^x[27]^x[26]^x[25]^x[22]^x[20]^x[19]^x[16]^x[14]^x[13]^x[10]^x[6]^x[5]^x[3]^x[0]; + + bcc_next[15] = m[33]^m[34]^x[31]^x[29]^x[28]^x[27]^x[26]^x[25]^x[24]^x[21]^x[19]^x[18]^x[15]^x[13]^x[12]^x[9]^x[5]^x[4]^x[2]; + + bcc_next[14] = m[32]^m[33]^x[30]^x[28]^x[27]^x[26]^x[25]^x[24]^x[23]^x[20]^x[18]^x[17]^x[14]^x[12]^x[11]^x[8]^x[4]^x[3]^x[1]; + + bcc_next[13] = m[36]^x[30]^x[28]^x[26]^x[25]^x[23]^x[22]^x[20]^x[18]^x[17]^x[16]^x[15]^x[9]^x[8]^x[7]^x[6]^x[5]^x[3]^x[2]^x[1]; + + bcc_next[12] = m[32]^m[35]^m[36]^x[31]^x[30]^x[28]^x[25]^x[22]^x[21]^x[20]^x[18]^x[17]^x[16]^x[14]^x[13]^x[11]^x[10]^x[9]^x[7]^x[4]^x[2]; + + bcc_next[11] = m[32]^m[34]^m[35]^m[36]^x[28]^x[21]^x[18]^x[17]^x[16]^x[12]^x[11]^x[5]^x[3]^x[0]; + + bcc_next[10] = m[33]^m[34]^m[35]^x[31]^x[27]^x[20]^x[17]^x[16]^x[15]^x[11]^x[10]^x[4]^x[2]; + + bcc_next[9] = m[33]^m[34]^m[36]^x[31]^x[29]^x[28]^x[27]^x[26]^x[24]^x[20]^x[18]^x[16]^x[14]^x[13]^x[11]^x[8]^x[6]^x[5]^x[3]^x[0]; + + bcc_next[8] = m[33]^m[35]^m[36]^x[31]^x[29]^x[26]^x[25]^x[24]^x[23]^x[20]^x[18]^x[17]^x[12]^x[11]^x[9]^x[8]^x[7]^x[6]^x[4]^x[2]^x[1]^x[0]; + + bcc_next[7] = m[32]^m[34]^m[35]^x[30]^x[28]^x[25]^x[24]^x[23]^x[22]^x[19]^x[17]^x[16]^x[11]^x[10]^x[8]^x[7]^x[6]^x[5]^x[3]^x[1]^x[0]; + + bcc_next[6] = m[32]^m[33]^m[34]^m[36]^x[30]^x[28]^x[23]^x[22]^x[21]^x[20]^x[19]^x[16]^x[13]^x[11]^x[8]^x[7]^x[4]^x[2]^x[1]; + + bcc_next[5] = m[33]^m[35]^m[36]^x[30]^x[28]^x[24]^x[22]^x[21]^x[13]^x[12]^x[11]^x[9]^x[8]^x[7]^x[5]^x[3]; + + bcc_next[4] = m[34]^m[35]^m[36]^x[31]^x[30]^x[28]^x[24]^x[23]^x[21]^x[19]^x[18]^x[15]^x[13]^x[12]^x[9]^x[7]^x[5]^x[4]^x[2]^x[1]^x[0]; + + bcc_next[3] = m[32]^m[33]^m[34]^m[35]^m[36]^x[31]^x[28]^x[24]^x[23]^x[22]^x[19]^x[17]^x[15]^x[14]^x[13]^x[12]^x[10]^x[9]^x[5]^x[4]^x[3]; + + bcc_next[2] = m[32]^m[33]^m[34]^m[35]^x[31]^x[30]^x[27]^x[23]^x[22]^x[21]^x[18]^x[16]^x[14]^x[13]^x[12]^x[11]^x[9]^x[8]^x[4]^x[3]^x[2]; + + bcc_next[1] = m[32]^m[33]^m[34]^x[31]^x[30]^x[29]^x[26]^x[22]^x[21]^x[20]^x[17]^x[15]^x[13]^x[12]^x[11]^x[10]^x[8]^x[7]^x[3]^x[2]^x[1]; + + bcc_next[0] = m[32]^m[33]^x[31]^x[30]^x[29]^x[28]^x[25]^x[21]^x[20]^x[19]^x[16]^x[14]^x[12]^x[11]^x[10]^x[9]^x[7]^x[6]^x[2]^x[1]^x[0]; + +end +endfunction + +function [7:0] bit_revers8; + input [7:0] din8; + begin + bit_revers8[0] = din8[7]; + bit_revers8[1] = din8[6]; + bit_revers8[2] = din8[5]; + bit_revers8[3] = din8[4]; + bit_revers8[4] = din8[3]; + bit_revers8[5] = din8[2]; + bit_revers8[6] = din8[1]; + bit_revers8[7] = din8[0]; + end +endfunction + +task rdbk_byte; + input [31:0] rdbk_reg; + begin + outbus[31:8] <= 24'b0; + if (rd_data_cnt==1) + outbus[7:0] <= bit_revers8(rdbk_reg[7:0]); + else if (rd_data_cnt==2) + outbus[7:0] <= bit_revers8(rdbk_reg[15:8]); + else if (rd_data_cnt==3) + outbus[7:0] <= bit_revers8(rdbk_reg[23:16]); + else if (rd_data_cnt==4) + outbus[7:0] <= bit_revers8(rdbk_reg[31:24]); + end +endtask + +task rdbk_wd; + input [31:0] rdbk_reg; + begin + outbus[31:16] <= 16'b0; + if (rd_data_cnt==1) + outbus[15:0] <= 16'b0; + else if (rd_data_cnt==2) + outbus[15:0] <= 16'b0; + else if (rd_data_cnt==3) begin + outbus[7:0] <= bit_revers8(rdbk_reg[7:0]); + outbus[15:8] <= bit_revers8(rdbk_reg[15:8]); + end + else if (rd_data_cnt==4) begin + outbus[7:0] <= bit_revers8(rdbk_reg[23:16]); + outbus[15:8] <= bit_revers8(rdbk_reg[31:16]); + end + end +endtask + +task rdbk_2wd; + input [31:0] rdbk_reg; + begin + if (rd_data_cnt==1) + outbus <= 32'b0; + else if (rd_data_cnt==2) + outbus <= 32'b0; + else if (rd_data_cnt==3) + outbus <= 32'b0; + else if (rd_data_cnt==4) begin + outbus[7:0] <= bit_revers8(rdbk_reg[7:0]); + outbus[15:8] <= bit_revers8(rdbk_reg[15:8]); + outbus[23:16] <= bit_revers8(rdbk_reg[23:16]); + outbus[31:24] <= bit_revers8(rdbk_reg[31:24]); + end + end +endtask + + + + +endmodule diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/SIM_CONFIG_V6_SERIAL.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/SIM_CONFIG_V6_SERIAL.v new file mode 100644 index 0000000..f4a5844 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/SIM_CONFIG_V6_SERIAL.v @@ -0,0 +1,851 @@ +////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2005 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Function Simulation Library Component +// / / Configuration Simulation Model +// /___/ /\ Filename : SIM_CONFIG_V6_SERIAL.v +// \ \ / \ Timestamp : +// \___\/\___\ +// +// Revision: +// 01/20/09 - Initial version for serial configuration simulation model. +// 11/25/09 - Fix CRC (CR538766) +// 03/03/10 - set mode_sample_flag to 0 when mode pin set wrong (CR552316) +// End Revision +//////////////////////////////////////////////////////////////////////////////// + +`timescale 1 ps / 1 ps + +module SIM_CONFIG_V6_SERIAL ( + DONE, + DOUT, + CCLK, + DIN, + INITB, + M, + PROGB + ); + + inout DONE; + output DOUT; + input CCLK; + input DIN; + inout INITB; + input [2:0] M; + input PROGB; + + parameter DEVICE_ID = 32'h0; + + localparam cfg_Tprog = 300000; // min PROG must be low, 300 ns + localparam cfg_Tpl = 100000; // max program latency us. + localparam STARTUP_PH0 = 3'b000; + localparam STARTUP_PH1 = 3'b001; + localparam STARTUP_PH2 = 3'b010; + localparam STARTUP_PH3 = 3'b011; + localparam STARTUP_PH4 = 3'b100; + localparam STARTUP_PH5 = 3'b101; + localparam STARTUP_PH6 = 3'b110; + localparam STARTUP_PH7 = 3'b111; + + wire GSR; + wire GTS; + wire GWE; + wire cclk_in; + wire init_b_in; + wire prog_b_in; + reg init_b_out = 1; + reg done_o = 0; + + tri1 p_up; + + reg por_b; + wire [2:0] m_in; + wire [31:0] d_int; + wire [31:0] d_out; + wire init_b_t; + wire prog_b_t; + wire bus_en; + wire desync_flag; + wire crc_rst; + reg crc_bypass = 0; + + assign DONE = p_up; + assign INITB = p_up; + assign glbl.GSR = GSR; + assign glbl.GTS = GTS; + + buf buf_cclk (cclk_in, CCLK); + + buf buf_din (ds_in, DIN); + buf buf_dout (DOUT, ds_out); + + buf buf_init (init_b_in, INITB); + buf buf_m_0 (m_in[0], M[0]); + buf buf_m_1 (m_in[1], M[1]); + buf buf_m_2 (m_in[2], M[2]); + buf buf_prog (prog_b_in, PROGB); + + time prog_pulse_low_edge = 0; + time prog_pulse_low = 0; + reg mode_sample_flag = 0; + reg [31:0] pack_in_reg = 32'b0; + reg [4:0] reg_addr; + reg new_data_in_flag = 0; + reg wr_flag = 1; + integer wr_bit_addr = 0; + reg rd_flag = 0; + reg cmd_rd_flag = 0; + reg cmd_wr_flag = 0; + reg cmd_reg_new_flag = 0; + reg bus_sync_flag = 0; + reg conti_data_flag = 0; + integer wr_cnt = 0; + integer rd_data_cnt = 0; + integer conti_data_cnt = 0; + reg [2:0] st_state = STARTUP_PH0; + reg startup_begin_flag = 0; + reg startup_end_flag = 0; + reg crc_ck = 0; + reg crc_err_flag = 0; + wire crc_err_flag_tot; + reg crc_err_flag_reg = 0; + wire crc_en; + reg [31:0] crc_curr = 32'b0; + reg [31:0] crc_new = 32'b0; + reg [36:0] crc_input = 32'b0; + reg gwe_out = 0; + reg gts_out = 1; + reg [31:0] tmp_val1; + reg [31:0] tmp_val2; + reg [31:0] crc_reg; + reg [31:0] far_reg; + reg [31:0] fdri_reg; + reg [31:0] fdro_reg; + reg [4:0] cmd_reg; + reg [31:0] ctl0_reg = 32'b000xxxxxxxxxxxxxx000000100000xx1; + reg [31:0] mask_reg; + wire [31:0] stat_reg; + reg [31:0] lout_reg; + reg [31:0] cor0_reg = 32'b00000000000000000011111111101100; + reg [31:0] mfwr_reg; + reg [31:0] cbc_reg; + reg [31:0] idcode_reg; + reg [31:0] axss_reg; + reg [31:0] cor1_reg = 32'b0; + reg [31:0] csob_reg; + reg [31:0] wbstar_reg = 32'b0; + reg [31:0] timer_reg = 32'b0; + reg [31:0] rbcrc_hw_reg; + reg [31:0] rbcrc_sw_reg; + reg [31:0] rbcrc_live_reg; + reg [31:0] efar_reg; + reg [31:0] bootsts_reg = 32'b0; + reg [31:0] ctl1_reg = 32'b0; + reg [2:0] mode_pin_in = 3'b0; + reg [2:0] mode_reg; + reg crc_reset = 0; + reg gsr_set = 0; + reg gts_usr_b = 1; + reg done_pin_drv = 0; + + reg shutdown_set = 0; + reg desynch_set = 0; + reg [2:0] done_cycle_reg; + reg [2:0] gts_cycle_reg; + reg [2:0] gwe_cycle_reg; + reg init_pin; + reg init_rst = 0; + reg init_complete; + reg [2:0] nx_st_state = 3'b000; + reg ghigh_b = 0; + reg gts_cfg_b = 0; + reg eos_startup = 0; + reg startup_set = 0; + reg [1:0] startup_set_pulse = 2'b0; + reg [31:0] tmp_dword1; + reg [31:0] tmp_dword2; + reg id_error_flag = 0; + reg iprog_b = 1; + reg i_init_b_cmd = 1; + reg i_init_b = 0; + reg persist_en = 0; + reg rst_sync = 0; + reg [2:0] lock_cycle_reg = 3'b0; + reg rbcrc_no_pin = 0; + reg gsr_st_out = 1; + reg gsr_cmd_out = 0; + reg gsr_cmd_out_pulse = 0; + reg d_o_en = 0; + wire rst_intl; + wire rw_en; + wire gsr_out; + wire cfgerr_b_flag; + integer downcont_cnt = 0; + reg rst_en = 0; + reg prog_b_a = 1; + reg csbo_flag = 0; + reg csi_sync = 0; + reg rd_sw_en = 0; + integer csbo_cnt = 0; + reg [4:0] rd_reg_addr = 5'b0; + reg dcm_locked = 1; + reg abort_dis = 0; + reg buswidth = 2'b00; + + + triand (weak1, strong0) INITB=(mode_sample_flag) ? ~crc_err_flag_tot : init_b_out; + triand (weak1, strong0) DONE=done_o; + + initial begin + if (DEVICE_ID == 32'h0) begin + $display("Attribute Error : The attribute DEVICE_ID on SIM_CONFIG_V6_SERIAL instance %m is not set."); + $finish; + end + end + + + assign GSR = gsr_out; + assign GTS = gts_out; + assign GWE = gwe_out; + assign cfgerr_b_flag = rw_en & ~crc_err_flag_tot; + assign crc_err_flag_tot = id_error_flag | crc_err_flag_reg; + assign ds_out = 1; + assign crc_en = 1; + + assign init_b_t = init_b_in & i_init_b_cmd; + + always @( negedge prog_b_in) begin + rst_en = 0; + rst_en <= #cfg_Tprog 1; + end + + always @( rst_en or init_rst or prog_b_in or iprog_b ) + if (init_rst == 1) + init_b_out <= 0; + else begin + if ((prog_b_in == 0 ) && (rst_en == 1) || (iprog_b == 0)) + init_b_out <= 0; + else if ((prog_b_in == 1 ) && (rst_en == 1) || (iprog_b == 1)) + init_b_out <= #(cfg_Tpl) 1; + end + + always @(posedge id_error_flag) begin + init_rst <= 1; + init_rst <= #cfg_Tprog 0; + end + + always @( rst_en or prog_b_in or prog_pulse_low) + if (rst_en == 1) begin + if (prog_pulse_low == cfg_Tprog) begin + prog_b_a = 0; + prog_b_a <= #500 1; + end + else + prog_b_a = prog_b_in; + end + else + prog_b_a = 1; + + initial begin + por_b = 0; + por_b = #400000 1; + end + + assign prog_b_t = prog_b_a & iprog_b & por_b; + + assign rst_intl = (prog_b_t==0 ) ? 0 : 1; + + always @( init_b_t or prog_b_t) + if (prog_b_t == 0) + mode_sample_flag <= 0; + else if (init_b_t && mode_sample_flag == 0) begin + if (prog_b_t == 1) begin + mode_pin_in <= m_in; + if (m_in != 3'b111) begin + mode_sample_flag <= 0; + $display("Error: input M is %h. Only Slave Serial mode M=111 supported on SIM_CONFIG_V6_SERIAL instance %m.", m_in); + end + else + mode_sample_flag <= #1 1; + end + end + + always @(posedge init_b_t ) + if (prog_b_t != 1) begin + if ($time != 0 ) + $display("Error: PROGB is not high when INITB goes high on SIM_CONFIG_V6_SERIAL instance %m at time %t.", $time); + end + + always @(m_in) + if (mode_sample_flag == 1 && persist_en == 1) + $display("Error : Mode pine M[2:0] changed after rising edge of INITB on SIM_CONFIG_V6_SERIAL instance %m at time %t.", $time); + + always @(posedge prog_b_in or negedge prog_b_in) + if (prog_b_in == 0) + prog_pulse_low_edge <= $time; + else if (prog_b_in == 1 && $time > 0) begin + prog_pulse_low = $time - prog_pulse_low_edge; + if (prog_pulse_low < cfg_Tprog ) + $display("Error: Low time of PROGB is less than required minimum Tprogram time %d on SIM_CONFIG_V6_SERIAL instance %m at time %t.", cfg_Tprog, $time); + end + + assign bus_en = (mode_sample_flag == 1 ) ? 1 : 0; + assign rw_en = (bus_en == 1 && done_o === 0) ? 1 : 0; + assign desync_flag = ~rst_intl | desynch_set | crc_err_flag | id_error_flag; + + always @(posedge cclk_in or posedge desync_flag) + if (desync_flag == 1) begin + pack_in_reg <= 32'b0; + new_data_in_flag <= 0; + wr_cnt <= 0; + wr_flag <= 1; + tmp_dword1 <= 32'b0; + tmp_dword2 <= 32'b0; + bus_sync_flag <= 0; + end + else begin + if (rw_en == 1 ) begin + if (bus_sync_flag == 0) begin + tmp_dword1 = {tmp_dword2[30:0], ds_in}; + if (tmp_dword1 == 32'hAA995566) begin + bus_sync_flag <= 1; + new_data_in_flag <= 0; + tmp_dword2 <= 32'b0; + pack_in_reg <= 32'b0; + wr_cnt <= 0; + end + else begin + tmp_dword2 <= tmp_dword1; + end + end + else begin + pack_in_reg <= {pack_in_reg[30:0], ds_in}; + if (wr_cnt == 31) begin + wr_cnt <= 0; + new_data_in_flag <= 1; + end + else begin + wr_cnt <= wr_cnt + 1; + new_data_in_flag <= 0; + end + end + end + else begin + new_data_in_flag <= 0; + end + end + + always @(negedge cclk_in or negedge rst_intl) + if (rst_intl ==0) begin + conti_data_flag <= 0; + conti_data_cnt <= 0; + cmd_wr_flag <= 0; + cmd_rd_flag <= 0; + id_error_flag <= 0; + crc_curr <= 32'b0; + crc_ck <= 0; + csbo_cnt <= 0; + csbo_flag <= 0; + downcont_cnt <= 0; + rd_data_cnt <= 0; + end + else begin + if (crc_reset == 1 ) begin + crc_reg <= 32'b0; + crc_ck <= 0; + crc_curr <= 32'b0; + end + if (crc_ck == 1) + crc_curr <= 32'b0; + + if (desynch_set == 1 || crc_err_flag == 1) begin + conti_data_flag <= 0; + conti_data_cnt <= 0; + cmd_wr_flag <= 0; + cmd_rd_flag <= 0; + cmd_reg_new_flag <= 0; + crc_ck <= 0; + csbo_cnt <= 0; + csbo_flag <= 0; + downcont_cnt <= 0; + rd_data_cnt <= 0; + end + + + if (new_data_in_flag == 1 && wr_flag == 1) begin + if (conti_data_flag == 1 ) begin + case (reg_addr) + 5'b00000 : begin + crc_reg <= pack_in_reg; + crc_ck <= 1; + end + 5'b00001 : far_reg <= pack_in_reg; + 5'b00010 : fdri_reg <= pack_in_reg; + 5'b00100 : cmd_reg <= pack_in_reg[4:0]; + 5'b00101 : ctl0_reg <= (pack_in_reg & mask_reg) | (ctl0_reg & ~mask_reg); + 5'b00110 : mask_reg <= pack_in_reg; + 5'b01000 : lout_reg <= pack_in_reg; + 5'b01001 : cor0_reg <= pack_in_reg; + 5'b01010 : mfwr_reg <= pack_in_reg; + 5'b01011 : cbc_reg <= pack_in_reg; + 5'b01100 : begin + idcode_reg <= pack_in_reg; + if (pack_in_reg[27:0] != DEVICE_ID[27:0]) begin + id_error_flag <= 1; + $display("Error : written value to IDCODE register is %h which does not match DEVICE ID %h on SIM_CONFIG_V6_SERIAL instance %m at time %t.", pack_in_reg, DEVICE_ID, $time); + end + else + id_error_flag <= 0; + end + 5'b01101 : axss_reg <= pack_in_reg; + 5'b01110 : cor1_reg <= pack_in_reg; + 5'b01111 : csob_reg <= pack_in_reg; + 5'b10000 : wbstar_reg <= pack_in_reg; + 5'b10001 : timer_reg <= pack_in_reg; + 5'b10011 : rbcrc_sw_reg <= pack_in_reg; + 5'b11000 : ctl1_reg <= (pack_in_reg & mask_reg) | (ctl1_reg & ~mask_reg); + endcase + + if (reg_addr != 5'b00000) + crc_ck <= 0; + + if (reg_addr == 5'b00100) + cmd_reg_new_flag <= 1; + else + cmd_reg_new_flag <= 0; + + if (crc_en == 1) begin + if (reg_addr == 5'h04 && pack_in_reg[4:0] == 5'b00111) + crc_curr[31:0] = 32'b0; + else begin + if ( reg_addr != 5'h0f && reg_addr != 5'h12 && reg_addr != 5'h14 + && reg_addr != 5'h15 && reg_addr != 5'h16 && reg_addr != 5'h00) begin + + crc_input[36:0] = {reg_addr, pack_in_reg}; + crc_new[31:0] = bcc_next(crc_curr, crc_input); + crc_curr[31:0] <= crc_new; + end + end + end + + if (conti_data_cnt <= 1) begin + conti_data_cnt <= 0; + end + else + conti_data_cnt <= conti_data_cnt - 1; + end + else if (conti_data_flag == 0 ) begin + if ( downcont_cnt >= 1) begin + if (crc_en == 1) begin + crc_input[36:0] = {5'b00010, pack_in_reg}; + crc_new[31:0] = bcc_next(crc_curr, crc_input); + crc_curr[31:0] <= crc_new; + end + end + + if (pack_in_reg[31:29] == 3'b010 && downcont_cnt == 0 ) begin + cmd_rd_flag <= 0; + cmd_wr_flag <= 0; + conti_data_flag <= 0; + conti_data_cnt <= 0; + downcont_cnt <= pack_in_reg[26:0]; + end + else if (pack_in_reg[31:29] == 3'b001) begin // type 1 package + if (pack_in_reg[28:27] == 2'b01 && downcont_cnt == 0) begin + if (pack_in_reg[10:0] != 10'b0) begin + cmd_rd_flag <= 1; + cmd_wr_flag <= 0; + rd_data_cnt <= 4; + conti_data_cnt <= 0; + conti_data_flag <= 0; + rd_reg_addr <= pack_in_reg[17:13]; + end + end + else if (pack_in_reg[28:27] == 2'b10 && downcont_cnt == 0) begin + if (pack_in_reg[17:13] == 5'b01111) begin // csbo reg + csob_reg <= pack_in_reg; + csbo_cnt = pack_in_reg[10:0]; + csbo_flag <= 1; + conti_data_flag = 0; + reg_addr <= pack_in_reg[17:13]; + cmd_wr_flag <= 1; + conti_data_cnt <= 5'b0; + end + else if (pack_in_reg[10:0] != 10'b0) begin + cmd_rd_flag <= 0; + cmd_wr_flag <= 1; + conti_data_flag <= 1; + conti_data_cnt <= pack_in_reg[10:0]; + reg_addr <= pack_in_reg[17:13]; + end + end + else begin + cmd_wr_flag <= 0; + conti_data_flag <= 0; + conti_data_cnt <= 0; + end + end + cmd_reg_new_flag <= 0; + crc_ck <= 0; + end // if (conti_data_flag == 0 ) + if (csbo_cnt != 0 ) begin + if (csbo_flag == 1) + csbo_cnt <= csbo_cnt - 1; + end + else + csbo_flag <= 0; + + if (conti_data_cnt == 5'b00001 ) + conti_data_flag <= 0; + + end + + if (rw_en == 1) begin + if (rd_data_cnt == 1 && rd_flag == 1) + rd_data_cnt <= 0; + else if (rd_data_cnt == 0 && rd_flag == 1) + cmd_rd_flag <= 0; + else if (cmd_rd_flag == 1 && rd_flag == 1) + rd_data_cnt <= rd_data_cnt - 1; + + if (downcont_cnt >= 1 && conti_data_flag == 0 && new_data_in_flag == 1 && wr_flag == 1) + downcont_cnt <= downcont_cnt - 1; + end + + if (crc_ck == 1) + crc_ck <= 0; + end + + + assign crc_rst = crc_reset | ~rst_intl; + + always @(posedge cclk_in or posedge crc_rst ) + if (crc_rst == 1) + crc_err_flag <= 0; + else + if (crc_ck == 1) begin + if (crc_curr[31:0] != crc_reg[31:0]) + crc_err_flag <= 1; + else + crc_err_flag <= 0; + end + else + crc_err_flag <= 0; + + always @(posedge crc_err_flag or negedge rst_intl or posedge bus_sync_flag) + if (rst_intl == 0) + crc_err_flag_reg <= 0; + else if (crc_err_flag == 1) + crc_err_flag_reg <= 1; + else + crc_err_flag_reg <= 0; + + always @(posedge cclk_in or negedge rst_intl) + if (rst_intl == 0) begin + startup_set <= 0; + crc_reset <= 0; + gsr_cmd_out <= 0; + shutdown_set <= 0; + desynch_set <= 0; + ghigh_b <= 0; + end + else begin + if (cmd_reg_new_flag ==1) begin + if (cmd_reg == 5'b00011) + ghigh_b <= 1; + else if (cmd_reg == 5'b01000) + ghigh_b <= 0; + + if (cmd_reg == 5'b00101) + startup_set <= 1; + + if (cmd_reg == 5'b00111) + crc_reset <= 1; + + if (cmd_reg == 5'b01010) + gsr_cmd_out <= 1; + + if (cmd_reg == 5'b01011) + shutdown_set <= 1; + + if (cmd_reg == 5'b01101) + desynch_set <= 1; + + if (cmd_reg == 5'b01111) begin + iprog_b <= 0; + i_init_b_cmd <= 0; + iprog_b <= #cfg_Tprog 1; + i_init_b_cmd <=#(cfg_Tprog + cfg_Tpl) 1; + end + end + else begin + startup_set <= 0; + crc_reset <= 0; + gsr_cmd_out <= 0; + shutdown_set <= 0; + desynch_set <= 0; + end + end + + always @(posedge startup_set or posedge desynch_set or negedge rw_en ) + if (rw_en == 0) + startup_set_pulse <= 2'b0; + else begin + if (startup_set_pulse == 2'b00 && startup_set ==1) + startup_set_pulse <= 2'b01; + else if (desynch_set == 1 && startup_set_pulse == 2'b01) begin + startup_set_pulse <= 2'b11; + @(posedge cclk_in ) + startup_set_pulse <= 2'b00; + end + end + + always @(posedge gsr_cmd_out or negedge rw_en) + if (rw_en == 0) + gsr_cmd_out_pulse <= 0; + else begin + gsr_cmd_out_pulse <= 1; + @(posedge cclk_in ); + @(posedge cclk_in ) + gsr_cmd_out_pulse <= 0; + end + + always @(ctl0_reg) begin + if (ctl0_reg[9] == 1) + abort_dis = 1; + else + abort_dis = 0; + + if (ctl0_reg[3] == 1) + persist_en = 1; + else + persist_en = 0; + + if (ctl0_reg[0] == 1) + gts_usr_b = 1; + else + gts_usr_b = 0; + end + + always @(cor0_reg) + begin + done_cycle_reg = cor0_reg[14:12]; + lock_cycle_reg = cor0_reg[8:6]; + gts_cycle_reg = cor0_reg[5:3]; + gwe_cycle_reg = cor0_reg[2:0]; + + if (cor0_reg[24] == 1'b1) + done_pin_drv = 1; + else + done_pin_drv = 0; + + if (cor0_reg[28] == 1'b1) + crc_bypass = 1; + else + crc_bypass = 0; + end + + always @(cor1_reg) + rbcrc_no_pin = cor1_reg[8]; + + assign stat_reg[31:27] = 5'b000x0; + assign stat_reg[26:25] = buswidth; + assign stat_reg[24:21] = 4'bxxx0; + assign stat_reg[20:18] = st_state; + assign stat_reg[17] = 1'b0; + assign stat_reg[16] = 1'b0; + assign stat_reg[15] = id_error_flag; + assign stat_reg[14] = DONE; + assign stat_reg[13] = (done_o !== 0) ? 1 : 0; + assign stat_reg[12] = INITB; + assign stat_reg[11] = mode_sample_flag; + assign stat_reg[10:8] = mode_pin_in; + assign stat_reg[7] = ghigh_b; + assign stat_reg[6] = gwe_out; + assign stat_reg[5] = gts_cfg_b; + assign stat_reg[4] = eos_startup; + assign stat_reg[3] = 1'b1; + assign stat_reg[2] = dcm_locked; + assign stat_reg[1] = 1'b0; + assign stat_reg[0] = crc_err_flag_reg; + + + always @(posedge cclk_in or negedge rst_intl) + if (rst_intl == 0) begin + st_state <= STARTUP_PH0; + startup_begin_flag <= 0; + startup_end_flag <= 0; + end + else begin + if (nx_st_state == STARTUP_PH1) begin + startup_begin_flag <= 1; + startup_end_flag <= 0; + end + else if (st_state == STARTUP_PH7) begin + startup_end_flag <= 1; + startup_begin_flag <= 0; + end + if (lock_cycle_reg == 3'b111 || dcm_locked == 1 || st_state != lock_cycle_reg ) begin + st_state <= nx_st_state; + end + else + st_state <= st_state; + end + + always @(st_state or startup_set_pulse or DONE ) + if (((st_state == done_cycle_reg) && (DONE != 0)) || (st_state != done_cycle_reg)) + case (st_state) + STARTUP_PH0 : if (startup_set_pulse == 2'b11 ) + nx_st_state = STARTUP_PH1; + else + nx_st_state = STARTUP_PH0; + STARTUP_PH1 : nx_st_state = STARTUP_PH2; + + STARTUP_PH2 : nx_st_state = STARTUP_PH3; + + STARTUP_PH3 : nx_st_state = STARTUP_PH4; + + STARTUP_PH4 : nx_st_state = STARTUP_PH5; + + STARTUP_PH5 : nx_st_state = STARTUP_PH6; + + STARTUP_PH6 : nx_st_state = STARTUP_PH7; + + STARTUP_PH7 : nx_st_state = STARTUP_PH0; + endcase + + always @(posedge cclk_in or negedge rst_intl ) + if (rst_intl == 0) begin + gwe_out <= 0; + gts_out <= 1; + eos_startup <= 0; + gsr_st_out <= 1; + done_o <= 0; + end + else begin + + if (nx_st_state == done_cycle_reg) begin + if (DONE != 0 || done_pin_drv == 1) + done_o <= 1'b1; + else + done_o <= 1'bz; + end + else begin + if (DONE != 0) + done_o <= 1; + end + + if (st_state == gwe_cycle_reg && DONE != 0) + gwe_out <= 1; + + if (st_state == gts_cycle_reg && DONE != 0) + gts_out <= 0; + + if (st_state == STARTUP_PH6 && DONE != 0) + gsr_st_out <= 0; + + if (st_state == STARTUP_PH7 && DONE != 0) + eos_startup <= 1; + + end + + assign gsr_out = gsr_st_out | gsr_cmd_out; + + +function [31:0] bcc_next; + input [31:0] bcc; + input [36:0] in; +reg [31:0] x; +reg [36:0] m; +begin + m = in; + x = in[31:0] ^ bcc; + + bcc_next[31] = m[32]^m[36]^x[31]^x[30]^x[29]^x[28]^x[27]^x[24]^x[20]^x[19]^x[18]^x[15]^x[13]^x[11]^x[10]^x[9]^x[8]^x[6]^x[5]^x[1]^x[0]; + + bcc_next[30] = m[35]^x[31]^x[30]^x[29]^x[28]^x[27]^x[26]^x[23]^x[19]^x[18]^x[17]^x[14]^x[12]^x[10]^x[9]^x[8]^x[7]^x[5]^x[4]^x[0]; + + bcc_next[29] = m[34]^x[30]^x[29]^x[28]^x[27]^x[26]^x[25]^x[22]^x[18]^x[17]^x[16]^x[13]^x[11]^x[9]^x[8]^x[7]^x[6]^x[4]^x[3]; + + bcc_next[28] = m[33]^x[29]^x[28]^x[27]^x[26]^x[25]^x[24]^x[21]^x[17]^x[16]^x[15]^x[12]^x[10]^x[8]^x[7]^x[6]^x[5]^x[3]^x[2]; + + bcc_next[27] = m[32]^x[28]^x[27]^x[26]^x[25]^x[24]^x[23]^x[20]^x[16]^x[15]^x[14]^x[11]^x[9]^x[7]^x[6]^x[5]^x[4]^x[2]^x[1]; + + bcc_next[26] = x[31]^x[27]^x[26]^x[25]^x[24]^x[23]^x[22]^x[19]^x[15]^x[14]^x[13]^x[10]^x[8]^x[6]^x[5]^x[4]^x[3]^x[1]^x[0]; + + bcc_next[25] = m[32]^m[36]^x[31]^x[29]^x[28]^x[27]^x[26]^x[25]^x[23]^x[22]^x[21]^x[20]^x[19]^x[15]^x[14]^x[12]^x[11]^x[10]^x[8]^x[7]^x[6]^x[4]^x[3]^x[2]^x[1]; + + bcc_next[24] = m[35]^x[31]^x[30]^x[28]^x[27]^x[26]^x[25]^x[24]^x[22]^x[21]^x[20]^x[19]^x[18]^x[14]^x[13]^x[11]^x[10]^x[9]^x[7]^x[6]^x[5]^x[3]^x[2]^x[1]^x[0]; + + bcc_next[23] = m[32]^m[34]^m[36]^x[31]^x[28]^x[26]^x[25]^x[23]^x[21]^x[17]^x[15]^x[12]^x[11]^x[4]^x[2]; + + bcc_next[22] = m[32]^m[33]^m[35]^m[36]^x[29]^x[28]^x[25]^x[22]^x[19]^x[18]^x[16]^x[15]^x[14]^x[13]^x[9]^x[8]^x[6]^x[5]^x[3]^x[0]; + + bcc_next[21] = m[34]^m[35]^m[36]^x[30]^x[29]^x[21]^x[20]^x[19]^x[17]^x[14]^x[12]^x[11]^x[10]^x[9]^x[7]^x[6]^x[4]^x[2]^x[1]^x[0]; + + bcc_next[20] = m[32]^m[33]^m[34]^m[35]^m[36]^x[31]^x[30]^x[27]^x[24]^x[16]^x[15]^x[3]; + + bcc_next[19] = m[32]^m[33]^m[34]^m[35]^x[31]^x[30]^x[29]^x[26]^x[23]^x[15]^x[14]^x[2]; + + bcc_next[18] = m[33]^m[34]^m[36]^x[27]^x[25]^x[24]^x[22]^x[20]^x[19]^x[18]^x[15]^x[14]^x[11]^x[10]^x[9]^x[8]^x[6]^x[5]^x[0]; + + bcc_next[17] = m[33]^m[35]^m[36]^x[31]^x[30]^x[29]^x[28]^x[27]^x[26]^x[23]^x[21]^x[20]^x[17]^x[15]^x[14]^x[11]^x[7]^x[6]^x[4]^x[1]^x[0]; + + bcc_next[16] = m[32]^m[34]^m[35]^x[30]^x[29]^x[28]^x[27]^x[26]^x[25]^x[22]^x[20]^x[19]^x[16]^x[14]^x[13]^x[10]^x[6]^x[5]^x[3]^x[0]; + + bcc_next[15] = m[33]^m[34]^x[31]^x[29]^x[28]^x[27]^x[26]^x[25]^x[24]^x[21]^x[19]^x[18]^x[15]^x[13]^x[12]^x[9]^x[5]^x[4]^x[2]; + + bcc_next[14] = m[32]^m[33]^x[30]^x[28]^x[27]^x[26]^x[25]^x[24]^x[23]^x[20]^x[18]^x[17]^x[14]^x[12]^x[11]^x[8]^x[4]^x[3]^x[1]; + + bcc_next[13] = m[36]^x[30]^x[28]^x[26]^x[25]^x[23]^x[22]^x[20]^x[18]^x[17]^x[16]^x[15]^x[9]^x[8]^x[7]^x[6]^x[5]^x[3]^x[2]^x[1]; + + bcc_next[12] = m[32]^m[35]^m[36]^x[31]^x[30]^x[28]^x[25]^x[22]^x[21]^x[20]^x[18]^x[17]^x[16]^x[14]^x[13]^x[11]^x[10]^x[9]^x[7]^x[4]^x[2]; + + bcc_next[11] = m[32]^m[34]^m[35]^m[36]^x[28]^x[21]^x[18]^x[17]^x[16]^x[12]^x[11]^x[5]^x[3]^x[0]; + + bcc_next[10] = m[33]^m[34]^m[35]^x[31]^x[27]^x[20]^x[17]^x[16]^x[15]^x[11]^x[10]^x[4]^x[2]; + + bcc_next[9] = m[33]^m[34]^m[36]^x[31]^x[29]^x[28]^x[27]^x[26]^x[24]^x[20]^x[18]^x[16]^x[14]^x[13]^x[11]^x[8]^x[6]^x[5]^x[3]^x[0]; + + bcc_next[8] = m[33]^m[35]^m[36]^x[31]^x[29]^x[26]^x[25]^x[24]^x[23]^x[20]^x[18]^x[17]^x[12]^x[11]^x[9]^x[8]^x[7]^x[6]^x[4]^x[2]^x[1]^x[0]; + + bcc_next[7] = m[32]^m[34]^m[35]^x[30]^x[28]^x[25]^x[24]^x[23]^x[22]^x[19]^x[17]^x[16]^x[11]^x[10]^x[8]^x[7]^x[6]^x[5]^x[3]^x[1]^x[0]; + + bcc_next[6] = m[32]^m[33]^m[34]^m[36]^x[30]^x[28]^x[23]^x[22]^x[21]^x[20]^x[19]^x[16]^x[13]^x[11]^x[8]^x[7]^x[4]^x[2]^x[1]; + + bcc_next[5] = m[33]^m[35]^m[36]^x[30]^x[28]^x[24]^x[22]^x[21]^x[13]^x[12]^x[11]^x[9]^x[8]^x[7]^x[5]^x[3]; + + bcc_next[4] = m[34]^m[35]^m[36]^x[31]^x[30]^x[28]^x[24]^x[23]^x[21]^x[19]^x[18]^x[15]^x[13]^x[12]^x[9]^x[7]^x[5]^x[4]^x[2]^x[1]^x[0]; + + bcc_next[3] = m[32]^m[33]^m[34]^m[35]^m[36]^x[31]^x[28]^x[24]^x[23]^x[22]^x[19]^x[17]^x[15]^x[14]^x[13]^x[12]^x[10]^x[9]^x[5]^x[4]^x[3]; + + bcc_next[2] = m[32]^m[33]^m[34]^m[35]^x[31]^x[30]^x[27]^x[23]^x[22]^x[21]^x[18]^x[16]^x[14]^x[13]^x[12]^x[11]^x[9]^x[8]^x[4]^x[3]^x[2]; + + bcc_next[1] = m[32]^m[33]^m[34]^x[31]^x[30]^x[29]^x[26]^x[22]^x[21]^x[20]^x[17]^x[15]^x[13]^x[12]^x[11]^x[10]^x[8]^x[7]^x[3]^x[2]^x[1]; + + bcc_next[0] = m[32]^m[33]^x[31]^x[30]^x[29]^x[28]^x[25]^x[21]^x[20]^x[19]^x[16]^x[14]^x[12]^x[11]^x[10]^x[9]^x[7]^x[6]^x[2]^x[1]^x[0]; + +end +endfunction + +function [7:0] bit_revers8; + input [7:0] din8; + begin + bit_revers8[0] = din8[7]; + bit_revers8[1] = din8[6]; + bit_revers8[2] = din8[5]; + bit_revers8[3] = din8[4]; + bit_revers8[4] = din8[3]; + bit_revers8[5] = din8[2]; + bit_revers8[6] = din8[1]; + bit_revers8[7] = din8[0]; + end +endfunction + + +endmodule diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/SPI_ACCESS.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/SPI_ACCESS.v new file mode 100644 index 0000000..8875229 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/SPI_ACCESS.v @@ -0,0 +1,1409 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/trilogy/SPI_ACCESS.v,v 1.17 2009/08/27 18:57:33 robh Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2008 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Internal logic access to the Serial Peripheral Interface (SPI) PROM data +// /___/ /\ Filename : SPI_ACCESS.v +// \ \ / \ Timestamp : Mon Oct 8 8:49:22 PDT 2007 +// \___\/\___\ +// +// +// Revision: +// 10/08/07 - Initial version. +// 07/09/08 - CR476247 - shorten simulation delays. +// 08/10/09 - CR529331 - update write_data (1) to write_data (buffer_number) +// End Revision +/////////////////////////////////////////////////////////////////////////////// + +`timescale 1 ps / 1 ps + +module SPI_ACCESS ( + MISO, + CLK, + CSB, + MOSI +); + +parameter SIM_DELAY_TYPE = "SCALED"; // ACCURATE means enforce spec timing delays + // SCALED means shorted delays for faster sim +parameter SIM_DEVICE = "3S1400AN"; +parameter SIM_FACTORY_ID = 512'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; // Security Register Bytes[64:127] +parameter SIM_USER_ID = 512'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF; // Security Register Bytes[0:63] +parameter SIM_MEM_FILE = "NONE"; // Memory pre-load + +/******************************************************************** +Port Declaration: +********************************************************************/ +output MISO; + +input CLK; +input CSB; +input MOSI; + +reg MISO_out = 1'b1; +wire CLK_in,CSB_in,MOSI_in; + +/************************************************************************* +Device localparam : +*************************************************************************/ +localparam BINARY_OPT = 1'b0; // 1 means binary page size + // 0 means default +// these are left alone +real tDIS = 0; +real tV = 0; +real tcs = 50e3; // spec for CSB high pulse width 50 ns +real tSPICLKH = 68e2; +real tSPICLKL = 68e2; +// scaled sim delays. not constant scale factors. reasonable numbers +real tCOMP = (SIM_DELAY_TYPE != "SCALED") ? 400e6 : 500e3; // spec tCOMP 400 us buffer to page compare k +real tXFR = (SIM_DELAY_TYPE != "SCALED") ? 400e6 : 500e3; // spec tXFR 400 us buffer to page transfer k +real tPEP = (SIM_DELAY_TYPE != "SCALED") ? 40e9 : 2500e3; // spec tPEP 40 ms page erase and program k +real tP = (SIM_DELAY_TYPE != "SCALED") ? 6e9 : 1000e3; // spec tP 6 ms program k +real tPE = (SIM_DELAY_TYPE != "SCALED") ? 35e9 : 1000e3; // spec tPE 32 ms page erase k +real tSE = (SIM_DELAY_TYPE != "SCALED") ? 500e9 : 4000e3; // spec tSE 5s sector erase k +real tVCSL = (SIM_DELAY_TYPE != "SCALED") ? 50e3 : 50e3; // spec tVCSL 50 us CS after Vcc > Vccmin k +real tPUW = (SIM_DELAY_TYPE != "SCALED") ? 50e3: 50e3; // spec tPUW 20 ms background op after Vcc k + +localparam Tper = 15152; +localparam Tper33 = 30304; +localparam name = "SPI_ACCESS"; + +reg force_continue =1'b0; // flag to force continue -- for model testing + +/*********** Status bits: ***********/ +localparam STATUS2 = 1; +localparam STATUS3 = (SIM_DEVICE == "3S50AN") ? 1 : + (SIM_DEVICE == "3S200AN") ? 1 : + (SIM_DEVICE == "3S400AN") ? 1 : + (SIM_DEVICE == "3S700AN") ? 0 : + (SIM_DEVICE == "3S1400AN")? 1 : 1; + +localparam STATUS4 = (SIM_DEVICE == "3S50AN") ? 0 : + (SIM_DEVICE == "3S200AN") ? 1 : + (SIM_DEVICE == "3S400AN") ? 1 : + (SIM_DEVICE == "3S700AN") ? 0 : + (SIM_DEVICE == "3S1400AN")? 0 : 0; + +localparam STATUS5 = (SIM_DEVICE == "3S50AN") ? 0 : + (SIM_DEVICE == "3S200AN") ? 0 : + (SIM_DEVICE == "3S400AN") ? 0 : + (SIM_DEVICE == "3S700AN") ? 1 : + (SIM_DEVICE == "3S1400AN")? 1 :1; + +/*********** no of pages: ***********/ +localparam PAGES = (SIM_DEVICE == "3S50AN") ? 512 : + (SIM_DEVICE == "3S200AN") ? 2048 : + (SIM_DEVICE == "3S400AN") ? 2048 : + (SIM_DEVICE == "3S700AN") ? 4096 : + (SIM_DEVICE == "3S1400AN")? 4096 : 4096; + +/*********** no of pages per sector: ***********/ +localparam PAGE_PER_SECTOR = (SIM_DEVICE == "3S50AN") ? 128 : + (SIM_DEVICE == "3S200AN") ? 256 : + (SIM_DEVICE == "3S400AN") ? 256 : + (SIM_DEVICE == "3S700AN") ? 256 : + (SIM_DEVICE == "3S1400AN")? 256 : 256; + +/*********** no of sectors: ***********/ +localparam SECTORS = (SIM_DEVICE == "3S50AN") ? 4 : + (SIM_DEVICE == "3S200AN") ? 8 : + (SIM_DEVICE == "3S400AN") ? 8 : + (SIM_DEVICE == "3S700AN") ? 16 : + (SIM_DEVICE == "3S1400AN")? 16 : 16; + +/*********** no of bytes per page: ***********/ +localparam PAGESIZE = (SIM_DEVICE == "3S50AN") ? (264 - (BINARY_OPT * 8)) : + (SIM_DEVICE == "3S200AN") ? (264 - (BINARY_OPT * 8)) : + (SIM_DEVICE == "3S400AN") ? (264 - (BINARY_OPT * 8)) : + (SIM_DEVICE == "3S700AN") ? (264 - (BINARY_OPT * 8)) : + (SIM_DEVICE == "3S1400AN")? (528 - (BINARY_OPT * 16)): + (528 - (BINARY_OPT * 16)); + +/*********** no of bytes: ***********/ +localparam MEMSIZE = PAGESIZE * PAGES; + +/*********** no of buffers: ***********/ +localparam BUFFERS = (SIM_DEVICE == "3S50AN") ? 1 : + (SIM_DEVICE == "3S200AN") ? 2 : + (SIM_DEVICE == "3S400AN") ? 2 : + (SIM_DEVICE == "3S700AN") ? 2 : + (SIM_DEVICE == "3S1400AN")? 2 : 2; + +/*********** no of bits needed to access a byte within a page: ***********/ +localparam BADDRESS = (SIM_DEVICE == "3S50AN") ? (9 - (BINARY_OPT * 1)) : + (SIM_DEVICE == "3S200AN") ? (9 - (BINARY_OPT * 1)) : + (SIM_DEVICE == "3S400AN") ? (9 - (BINARY_OPT * 1)) : + (SIM_DEVICE == "3S700AN") ? (9 - (BINARY_OPT * 1)) : + (SIM_DEVICE == "3S1400AN")? (10 - (BINARY_OPT * 1)): + (10 - (BINARY_OPT * 1)); + +/*********** no of bits needed to access a page: ***********/ +localparam PADDRESS = (SIM_DEVICE == "3S50AN") ? 9 : + (SIM_DEVICE == "3S200AN") ? 11 : + (SIM_DEVICE == "3S400AN") ? 11 : + (SIM_DEVICE == "3S700AN") ? 12 : + (SIM_DEVICE == "3S1400AN")? 12 : 12; + +/*********** no of bits needed to access a sector: ***********/ +localparam SADDRESS = (SIM_DEVICE == "3S50AN") ? 2 : + (SIM_DEVICE == "3S200AN") ? 3 : + (SIM_DEVICE == "3S400AN") ? 3 : + (SIM_DEVICE == "3S700AN") ? 4 : + (SIM_DEVICE == "3S1400AN")? 4 : 4; + +/*********** Manufacturer ID: ***********/ +localparam [31:0] MAN_ID = (SIM_DEVICE == "3S50AN") ? 32'h1F_22_00_00 : + (SIM_DEVICE == "3S200AN") ? 32'h1F_24_00_00 : + (SIM_DEVICE == "3S400AN") ? 32'h1F_24_00_00 : + (SIM_DEVICE == "3S700AN") ? 32'h1F_25_00_00 : + (SIM_DEVICE == "3S1400AN")? 32'h1F_26_00_00 : + 32'h1F_26_00_00; + + +/********************************************************************** +Memory & Registers PreLoading Parameters: +============================= +These parameters are related to Memory and Registers Preloading. +Memory, Sector Protection Register, Sector Lock-down Register and +Security Register can be preloaded, in Hex format. + +To pre-load Memory (in Hex format), define parameter +SIM_MEM_FILE = , where is the name of +the pre-load file. +If SIM_MEM_FILE = "", the Memory is initialized to Erased state (all data = FF). +If the memory is initialized, the status of all pages will be Not-Erased. + +To pre-load Security Register (only the User Programmable Bytes 0 to 63), +define parameter SECURITY = , where is the name +of the pre-load file. +If SECURITY = "", the register is initialized to erased state (all data = FF). + +The Factory Programmed Bytes 64 to 127 are always initialized by defining +param FACTORY = "factory.txt". As the Factory Programmed Bytes are +accessible to the user for read, a sample of "factory.txt" file +needs to be included in the Verilog Model directory. +**********************************************************************/ + +/********* Memory And Access Related Declarations *****************/ +reg [7:0] memory [MEMSIZE-1:0] ; +reg [7:0] buffer1 [PAGESIZE-1:0] ; //Buffer 1 +reg [7:0] buffer2 [PAGESIZE-1:0] ; //Buffer 2 +reg [SADDRESS-1:0] sector; // sector address +reg [PADDRESS-1:0] page ; // page address +reg [BADDRESS-1:0] byte_add ; // byte address +reg [PAGES-1:0] page_status; // 0 means page-erased, otherwise not erased +reg [7:0] status ; // status reg +reg [7:0] factory_reg[63:0]; // factory programmed security register +reg [7:0] security_reg[63:0]; // security register +reg security_flag; // 0 means that security register has not been programmed yet +reg soft_prot_enabled; // 1 means that software sectro protection is enabled + +/********* Registers to track the current operation of the device ********/ +reg status_read; +reg updating_buffer1; +reg updating_buffer2; +reg updating_memory; +reg comparing; +reg compare_value; +reg erasing_page; +reg erasing_sector; + + +/******** Other variables/registers/events ******************/ +reg [7:0] read_data; // temp. register in which data is read-in +reg [7:0] temp_reg1; // temp. register to store temporary data +reg [7:0] temp_reg2; // temp. register to store temporary data +reg [PADDRESS-1:0] temp_page; // temp register to store page-address +reg SO_reg = 1'b1 ; +reg SO_on ; +reg RDYBSY_reg; +reg mem_initialized; +reg binary_page; +reg foreground_op_enable; +reg background_op_enable; +reg per_flag=0; +reg test_33mhz = 1'b0; +reg skip; // reg to denote whether or no an extra clock needs to be skipped. + // This skipping is needed only for Inactive Clock Low. + +reg [8*45:1] cmd_name=" Initialize "; +reg [8*5:1] cycle_mode="idle "; + +wire RDY_BUSYB; +integer i, j; +integer page_boundary_low; +integer page_boundary_high; +integer current_address; +integer mem_no; // this will keep track of the actual memory to be used. +integer arr_rd_dummybyte; +integer buff_rd_dummybyte; +integer buffer_number; // number of the buffer to operate on +integer erase_flag; // Flags whether is erase is selected +reg clk_err=0; +reg clk_err_h=0; +reg clk_err_l=0; +reg clk_err33=0; +reg csb_err=0; +reg backgnd_while_busy_err=0; +time LastSignalRise = 0; +time last_csb_rise=0; +time LastSignalFall = 0; +time clk_low = 0; + +/********* Drive SO ***********************/ +bufif1 (RDY_BUSYB, RDYBSY_reg, 1'b0); //RDYBUSYB will be driven only if RDYBSY_reg is High + +/********* Events to trigger some task based on opcode ***********/ +event MMCAR ; // Continuous Array Read +event MIR ; // Manufacturer ID Read +event MMPTBT ; // Main Memory Page To Buffer Transfer +event MMPTBC ; // Main Memory Page To Buffer 1 Compare +event BW; // Buffer 1 Write +event BTMMPP; // Buffer To Main Memory Page Prog with or without Built-In Erase +event PE ; // Page Erase +event SE ; // Sector Erase +event MMPPB ; // Main Memory Page Prog. Through Buffer 1 +event SR ; // Status Register Read +event SRP ; // Security Register Program +event SRR ; // Security Register Read + +buf b_miso (MISO,MISO_out); +buf b_clk (CLK_in,CLK); +buf b_csb (CSB_in,CSB); +buf b_mosi (MOSI_in,MOSI); + +initial // Check for attribute syntax +begin + #1 + if (SIM_DELAY_TYPE !="SCALED"&&SIM_DELAY_TYPE!="ACCURATE") begin + $display ("Attribute Syntax Error : SIM_DELAY_TYPE in %s The legal values for this attribute are SCALED OR ACCURATE",name); + if (!force_continue) $finish; + end + if (SIM_DEVICE != "3S50AN" && SIM_DEVICE != "3S200AN" && SIM_DEVICE != "3S400AN" && SIM_DEVICE != "3S700AN" && SIM_DEVICE != "3S1400AN") begin + $display ("Attribute Syntax Error : SIM_DEVICE in %s The legal values for this attribute are 3S50AN or 3S200AN or 3S400AN or 3S700AN or 3S1400AN",name); + if (!force_continue) $finish; + end +end + +/********* Initialize **********************/ +initial +begin + // start with erased state + // Memory Initialization + for (j=0; j=0; i = i-1) + begin + @(posedge CLK_in); + read_data[i] = MOSI_in; + end +end +endtask + + +/* compute_address is a task to compute the current address, +as well as obtain the page boundaries */ + +task compute_address; + +integer i; +begin + page_boundary_low = page * PAGESIZE; + page_boundary_high = page_boundary_low + (PAGESIZE - 1); + current_address = page_boundary_low + byte_add; + mem_no = 10; +end +endtask + + +/* task read_out_array is to read from main Memory, either in +Continuous Mode, or, in Burst Mode */ + +task read_out_array ; + +integer i; +integer temp_high; +integer temp_low; +integer temp_add; +begin + temp_high = page_boundary_high; + temp_low = page_boundary_low; + temp_add = current_address; + temp_reg1 = memory [temp_add]; + i = 7; + while (CSB_in == 1'b0) // continue transmitting, while, CSB_in is Low + begin : CONTINUE_READING + @(negedge CLK_in) ; + #tV SO_reg = temp_reg1[i]; + SO_on = 1'b1; + if (i == 0) + begin + temp_add = temp_add + 1; // next byte + i = 7; + if (temp_add >= MEMSIZE) + begin + temp_add = 0; // Note that rollover occurs at end of memory, + temp_high = PAGESIZE - 1; // and not at the end of the page + temp_low = 0; + end + if (temp_add > temp_high) // going to next page + begin + temp_high = temp_high + PAGESIZE; + temp_low = temp_low + PAGESIZE; + end + temp_reg1 = memory [temp_add]; + end + else + i = i - 1; // next bit + end // reading over, because CSB_in has gone high +end +endtask + + +/* transfer_to_buffer will transfer data into a buffer from a page of +main memory */ + +task transfer_to_buffer ; +input buf_type; +input low; + +integer buf_type; +integer low; +integer i,k; + +begin + // Intentionally written this way: i.e. the for loop is within all if. + // Writing in alternative way would cause shorter code, but, significant + // increase in simulation time. + if (buf_type == 1) + for (i=0 ; i < PAGESIZE; i = i+1) + buffer1[i] = memory[low+i]; + else if (buf_type == 2) + for (i=0 ; i < PAGESIZE; i = i+1) + buffer2[i] = memory[low+i]; +end +endtask + + +/* compare_with_buffer will compare data into a buffer against a page of +main memory */ + +task compare_with_buffer ; +input buf_type; +input low; +output status; + +integer buf_type; +integer low; +integer i, k; +reg [7:0] tmp1, tmp2; +reg status; +begin + status = 1'b0; + if (buf_type == 1) + for (i=0 ; i < PAGESIZE; i = i+1) + begin : LOOP1 + tmp1 = memory[low+i]; + tmp2 = buffer1[i]; + for (k=0; k < 8; k = k+1) + if (tmp1[k] !== tmp2[k]) + begin // detected miscompare. No need for further comparison + status = 1'b1; + disable LOOP1; + end + end + else if (buf_type == 2) + for (i=0 ; i < PAGESIZE; i = i+1) + begin : LOOP2 + tmp1 = memory[low+i]; + tmp2 = buffer2[i]; + for (k=0; k < 8; k = k+1) + if (tmp1[k] !== tmp2[k]) + begin // detected miscompare. No need for further comparison + status = 1'b1; + disable LOOP2; + end + end +end +endtask + + +/* write_data will gat data from MOSI_in, and, write into device */ + +task write_data ; + +input buf_type; +integer buf_type; +integer i; +begin + while (CSB_in == 1'b0) + begin + for (i=7; i>=0; i=i-1) + begin + @(posedge CLK_in); + temp_reg1[i] = MOSI_in; + end // Complete byte recvd. Now transfer the byte to memory/buffer + if (buf_type == 1) // Buffer 1 + buffer1[current_address] = temp_reg1; + else + if (buf_type == 2) // Buffer 2 + buffer2[current_address] = temp_reg1; + current_address = current_address + 1; + if (current_address > page_boundary_high) + current_address = page_boundary_low; + end // continue writing. Note that parts of a byte will not be written. +end +endtask + + +/* read_out_reg will read the output on SO pin. It can read contents of +protection, lock-down or security registers*/ + +task read_out_reg ; +input reg_type; +input add; +input high; + +integer reg_type; +integer add; +integer high; +integer i; + +begin + if (reg_type == 23) // Security Register + temp_reg1 = security_reg [add]; + i = 7; + while (CSB_in == 1'b0) // continue transmitting, while, CSB_in is Low + begin : CONTINUE_READING + @(negedge CLK_in) ; + #tV SO_reg = temp_reg1[i]; + SO_on = 1'b1; + if (i == 0) + begin + add = add + 1; // next byte + i = 7; + if (add > high) + temp_reg1 = 8'hxx; + else + if (reg_type == 23) + if (add < 64) + temp_reg1 = security_reg [add]; + else + temp_reg1 = factory_reg [add-64]; + end + else + i = i - 1; // next bit + end // reading over, because CSB_in has gone high +end +endtask + + +/* write_to_memory will transfer data from a buffer into a page of +main memory */ + +task write_to_memory ; +input buf_type; +input low; + +integer buf_type; +integer low; + +integer i; +begin + if (buf_type == 1) + for (i=0 ; i < PAGESIZE; i = i+1) + memory[low+i] = buffer1[i]; + else if (buf_type == 2) + for (i=0 ; i < PAGESIZE; i = i+1) + memory[low+i] = buffer2[i]; + page_status[page] = 1'b1; // this page is now not erased +end +endtask + + +/* erase_page will erase a page of main memory */ + +task erase_page ; +input low; +integer low; +integer i; +begin + for (i=0 ; i < PAGESIZE; i = i+1) + memory[low+i] = 8'hff; + page_status[page] = 1'b0; // this page is now erased +end +endtask + +//////////////////////////////////////////////////////////////////////////////////// +////////////////////////// Main routine ////////////////////////////////////////// +always @(negedge CSB_in) // the device will now become active +begin : get_opcode + if (CLK_in == 1'b0) + begin + skip = 1'b1; + cycle_mode = "MODE0"; // CSB_in asserted while clock low, SPI terminology + // not supported by model + end + else + begin + skip = 1'b0; + cycle_mode = "MODE3"; // CBS asserted while clock high, SPI terminology + // If the opcode is related to SPI Mode 0/3, no skipping is needed. So, skip + // will be reset to "0". + // If opcode is related to Inactive Clock Low/high, skipping might or might + // not be needed, depending on the value of CLK at negedge of CSB_in. So, in + // such situations, skip will retain its value. + end + get_data; // get opcode here + if (foreground_op_enable == 1'b0) // No foreground or background opcode accepted + $display ("DRC Error : In %s no opcode is allowed: %f delay is required before device can be selected", name, tVCSL); + else if (cycle_mode != "MODE3") begin // wrong access mode + $display ("DRC Error : In %s at time: %d must drive CSB_in LOW while CLK is HIGH.", name, $time); + if (!force_continue) $finish; + end + else begin + case (read_data) // based on opcode, trigger an action + 8'h03 : begin + cmd_name="Main Memory Continuous Array Read"; + if (RDYBSY_reg == 1'b0) begin // device is already busy + $display ("DRC Error : In %s at time: %d device is busy. Command is not allowed", name, $time); + backgnd_while_busy_err=1; + if (!force_continue) $finish; + end + else begin + skip = 1'b0; + arr_rd_dummybyte = 0; + -> MMCAR ; // Main Memory Continuous Array Read + end + end + 8'h0B : begin + cmd_name="Main Memory Continuous Array Read"; + if (RDYBSY_reg == 1'b0) begin // device is already busy + $display ("DRC Error : In %s at time: %d device is busy. Command is not allowed", name, $time); + backgnd_while_busy_err=1; + if (!force_continue) $finish; + end + else begin + skip = 1'b0; + arr_rd_dummybyte = 1; + -> MMCAR ; // Main Memory Continuous Array Read + end + end + 8'h53 : begin + cmd_name="Main Memory Page To Buffer 1 Transfer"; + if (background_op_enable == 1'b0) + $display ("DRC Error : In %s write operations are not allowed before %f delay", name, tPUW); + else if (RDYBSY_reg == 1'b0) begin // device is already busy + $display ("DRC Error : In %s at time: %d device is busy. Command is not allowed", name, $time); + backgnd_while_busy_err=1; + if (!force_continue) $finish; + end + else begin + buffer_number=1; + -> MMPTBT ; // Main Memory Page To Buffer 1 Transfer + end + end + 8'h55 : begin + cmd_name="Main Memory Page To Buffer 2 Transfer"; + if (BUFFERS == 1) + $display ("DRC Error : In %s opcode %h is not offered in device %s", name, read_data,SIM_DEVICE); + else if (background_op_enable == 1'b0) + $display ("DRC Error : In %s write operations are not allowed before %f delay", name, tPUW); + else if (RDYBSY_reg == 1'b0) begin // device is already busy + $display ("DRC Error : In %s at time: %d device is busy. Command is not allowed", name, $time); + backgnd_while_busy_err=1; + if (!force_continue) $finish; + end + else begin + buffer_number=2; + -> MMPTBT ; // Main Memory Page To Buffer 2 Transfer + end + end + 8'h60 : begin + cmd_name="Main Memory Page To Buffer 1 Compare"; + if (background_op_enable == 1'b0) + $display ("DRC Error : In %s write operations are not allowed before %f delay", name, tPUW); + else if (RDYBSY_reg == 1'b0) begin // device is already busy + $display ("DRC Error : In %s at time: %d device is busy. Command is not allowed", name, $time); + backgnd_while_busy_err=1; + if (!force_continue) $finish; + end + else begin + buffer_number=1; + -> MMPTBC ; // Main Memory Page To Buffer 1 Compare + end + end + 8'h61 : begin + cmd_name="Main Memory Page To Buffer 2 Compare"; + if (BUFFERS == 1) + $display ("DRC Error : In %s opcode %h is not offered in device %s", name, read_data,SIM_DEVICE); + else if (background_op_enable == 1'b0) + $display ("DRC Error : In %s write operations are not allowed before %f delay", name, tPUW); + else if (RDYBSY_reg == 1'b0) begin // device is already busy + $display ("DRC Error : In %s at time: %d device is busy. Command is not allowed", name, $time); + backgnd_while_busy_err=1; + if (!force_continue) $finish; + end + else begin + buffer_number=2; + -> MMPTBC ; // Main Memory Page To Buffer 2 Compare + end + end + 8'h84 : begin + cmd_name="Buffer 1 Write"; + buffer_number=1; + -> BW ; // Buffer 1 Write + end + 8'h87 : begin + cmd_name="Buffer 2 Write"; + if (BUFFERS == 1) + $display ("DRC Error : In %s opcode %h is not offered in device %s", name, read_data, SIM_DEVICE); + else begin + buffer_number=2; + -> BW ; // Buffer 2 Write + end + end + 8'h83 : begin + cmd_name="Buffer 1 To Main Memory Page Prog With Erase"; + if (background_op_enable == 1'b0) + $display ("DRC Error : In %s write operations are not allowed before %f delay", name, tPUW); + else if (RDYBSY_reg == 1'b0) begin // device is already busy + $display ("DRC Error : In %s at time: %d device is busy. Command is not allowed", name, $time); + backgnd_while_busy_err=1; + if (!force_continue) $finish; + end + else begin + erase_flag=1; + buffer_number=1; + -> BTMMPP ; // Buffer 1 To Main Memory Page Prog + end + end + 8'h86 : begin + cmd_name="Buffer 2 To Main Memory Page Prog With Erase"; + if (BUFFERS == 1) + $display ("DRC Error : In %s opcode %h is not offered in device %s", name, read_data,SIM_DEVICE); + else if (background_op_enable == 1'b0) + $display ("DRC Error : In %s write operations are not allowed before %f delay", name, tPUW); + else if (RDYBSY_reg == 1'b0) begin // device is already busy + $display ("DRC Error : In %s at time: %d device is busy. Command is not allowed", name, $time); + backgnd_while_busy_err=1; + if (!force_continue) $finish; + end + else begin + erase_flag=1; + buffer_number=2; + -> BTMMPP ; // Buffer 2 To Main Memory Page Prog + end + end + 8'h88 : begin + cmd_name="Buffer 1 To Main Memory Page Prog"; + if (background_op_enable == 1'b0) + $display ("DRC Error : In %s write operations are not allowed before %f delay", name, tPUW); + else if (RDYBSY_reg == 1'b0) begin // device is already busy + $display ("DRC Error : In %s at time: %d device is busy. Command is not allowed", name, $time); + backgnd_while_busy_err=1; + if (!force_continue) $finish; + end + else begin + erase_flag=0; + buffer_number=1; + -> BTMMPP ; // Buffer 1 To Main Memory Page Prog + end + end + 8'h89 : begin + cmd_name="Buffer 2 To Main Memory Page Prog"; + if (BUFFERS == 1) + $display ("DRC Error : In %s opcode %h is not offered in device %s", name, read_data,SIM_DEVICE); + else if (background_op_enable == 1'b0) + $display ("DRC Error : In %s write operations are not allowed before %f delay", name, tPUW); + else if (RDYBSY_reg == 1'b0) begin // device is already busy + $display ("DRC Error : In %s at time: %d device is busy. Command is not allowed", name, $time); + backgnd_while_busy_err=1; + if (!force_continue) $finish; + end + else begin + erase_flag=0; + buffer_number=2; + -> BTMMPP ; // Buffer 2 To Main Memory Page Prog + end + end + 8'h81 : begin + cmd_name="Page Erase"; + if (background_op_enable == 1'b0) + $display ("DRC Error : In %s write operations are not allowed before %f delay", name, tPUW); + else if (RDYBSY_reg == 1'b0) begin // device is already busy + $display ("DRC Error : In %s at time: %d device is busy. Command is not allowed", name, $time); + backgnd_while_busy_err=1; + if (!force_continue) $finish; + end + else begin + -> PE ; // Page Erase + end + end + 8'h82 : begin + cmd_name="Main Memory Page Prog. Through Buffer 1"; + if (background_op_enable == 1'b0) + $display ("DRC Error : In %s write operations are not allowed before %f delay", name, tPUW); + else if (RDYBSY_reg == 1'b0) begin // device is already busy + $display ("DRC Error : In %s at time: %d device is busy. Command is not allowed", name, $time); + backgnd_while_busy_err=1; + if (!force_continue) $finish; + end + else begin + buffer_number=1; + -> MMPPB ; // Main Memory Page Prog. Through Buffer 1 + end + end + 8'h7C : begin + cmd_name="Sector Erase"; + if (background_op_enable == 1'b0) + $display ("DRC Error : In %s write operations are not allowed before %f delay", name, tPUW); + else if (RDYBSY_reg == 1'b0) begin // device is already busy + $display ("DRC Error : In %s at time: %d device is busy. Command is not allowed", name, $time); + backgnd_while_busy_err=1; + if (!force_continue) $finish; + end + else + -> SE ; // Sector Erase + end + 8'h85 : begin + cmd_name="Main Memory Page Prog. Through Buffer 2"; + if (BUFFERS == 1) + $display ("DRC Error : In %s opcode %h is not offered in device %s", name, read_data,SIM_DEVICE); + else if (background_op_enable == 1'b0) + $display ("DRC Error : In %s write operations are not allowed before %f delay", name, tPUW); + else if (RDYBSY_reg == 1'b0) begin // device is already busy + $display ("DRC Error : In %s at time: %d device is busy. Command is not allowed", name, $time); + backgnd_while_busy_err=1; + if (!force_continue) $finish; + end + else begin + buffer_number=2; + -> MMPPB ; // Main Memory Page Prog. Through Buffer 2 + end + end + 8'hd7 : begin + cmd_name="Status Register Read"; + skip = 1'b0; + -> SR ; // Status Register Read + end + 8'h9F : begin + cmd_name="Manufacturer ID Read"; + skip = 1'b0; + -> MIR ; // Manufacturer ID Read + end + 8'h9B : begin + cmd_name="Security Register Program"; + if (background_op_enable == 1'b0) + $display ("DRC Error : In %s write operations are not allowed before %f delay", name, tPUW); + else if (RDYBSY_reg == 1'b0) begin // device is already busy + $display ("DRC Error : In %s at time: %d device is busy. Command is not allowed", name, $time); + backgnd_while_busy_err=1; + if (!force_continue) $finish; + end + else + -> SRP ; // 4-byte command starting with 9B + end + 8'h77 : begin + cmd_name="Security Register Read"; + if (RDYBSY_reg == 1'b0) begin // device is already busy + $display ("DRC Error : In %s at time: %d device is busy. Command is not allowed", name, $time); + backgnd_while_busy_err=1; + if (!force_continue) $finish; + end + else + -> SRR ; // Security Register Read + end + default : $display ("DRC Error : In %s unrecognized opcode %h", name, read_data); + endcase + end +end + + +/******* Main Memory Continuous Read ********************/ + +always @(MMCAR) +begin : MMCAR_ + if (arr_rd_dummybyte == 0) + test_33mhz =1; + // if it comes here, means, the above if was false. + get_data; + temp_reg1[7:0] = read_data [7:0]; + get_data; + // Now that the two bytes have been obtained, distribute it + // within PageAddress and byte-address, according to + // the parameters. + comp_page_addr; + comp_byte_addr; + + // next 8 bits always contain byte-address[7:0], and, so is + // not dependent on parameters + get_data; + byte_add[7:0] = read_data[7:0]; + for (j=0; j 0) + j = j-1; + else + j = 7; + SO_reg=status[j]; + SO_on = 1'b1; + SO_reg = status[j]; + end // output next bit on next falling edge of CLK + status_read = 1'b0; // status_reg read is over +end + +always @(SO_on,SO_reg) +begin + if (SO_on == 1) + MISO_out = SO_reg; + else + MISO_out = 1; +end + + +/******* Security Register Program *******/ + +always @(SRP) +begin : SRP_ + cmd_name="Security Register Program"; + temp_reg1[7:0] = 8'h00; + for (j=0;j<3; j=j+1) // 4 byte command test for 3 00 bytes + begin + get_data; + if ( read_data != 'h00) + begin + $display ("DRC Error : In %s this 4 byte opcode starting 9B with is not offered ", name); + disable SRP_; + end + end + current_address = 0; + page_boundary_low = 0; + page_boundary_high = 63; //rm changed from 64 for wrap sooner + write_data (1); // this will write to buffer + // it will proceed to next step, when, posedge of CSB_in. + // This is complicated, and, hence, explained here: + // At posedge of CSB_in, the write_data will get disabled. + // At this time, writing to buffer needs to stop, and, + // writing into memory should start. + + RDYBSY_reg = 1'b0; // device is busy + status[7] = 1'b0; + // Program security_reg + if (security_flag == 0) // Security Register has not been programmed before + begin + for (j=0 ; j < 64; j = j+1) + security_reg[j] = buffer1[j]; + // Update security_flag; + security_flag = 1'b1; + #tP RDYBSY_reg = 1'b1; // device is now ready + status[7] = 1'b1; + end + else + begin + $display ("DRC Error : In %s at time %d Security Register can only be programmed once", name, $time); + if (!force_continue) $finish; + RDYBSY_reg = 1'b1; // device is now ready + status[7] = 1'b1; + end +end + + +/********* Manufacturing ID Read ********************/ + +always @(MIR) +begin: MIR_ + j = 32; + if (skip == 1'b1) + @(posedge CLK_in); // skip one CLK + while (CSB_in == 1'b0) + begin + @(negedge CLK_in); + #tV ; + if (j > 0) + begin + j = j-1; + SO_reg=MAN_ID[j]; + SO_on = 1'b1; + SO_reg = MAN_ID[j]; + end + else if (j == 0) + begin + SO_on = 1'b1; + SO_reg = 1'bx; + end + end // output next bit on next falling edge of CLK +end + + +/******* Security Register Read ********************/ + +always @(SRR) +begin : SRR_ + get_data; // these 24 bits are dont-care, + get_data; // and so have been discarded. + get_data; + if (skip == 1'b1) + @(posedge CLK_in); // skip one CLK + read_out_reg (23, 0, 127); +end + + +/******** Posedge CSB_in. Stop all reading, recvng. commands/addresses etc. *********/ + +always @(posedge CSB_in) +begin + backgnd_while_busy_err = 1'b0; + disable MMCAR_; // MMCAR will stop, if CSB_in goes high + disable BW_; // BW will stop, if CSB_in goes high + disable SR_; // Status reading should stop. + status_read = 1'b0; + disable MIR_; // MIR will stop, if CSB_in goes high + disable SRR_ ; // SRR will stop, if CSB_in goes high + disable read_out_array; + disable get_data; // Stop data retrieval + disable write_data; // Stop writing to buffers, NOW + test_33mhz =0; + cycle_mode = "idle"; + #tDIS SO_on = 1'b0; // SO is now in high-impedance +end + +always @(posedge CSB_in or negedge CSB_in) +begin + if ((($time - last_csb_rise) < tcs ) && ($time > tcs) && !CSB_in) begin // check CSB_in high violation on negedge + $display("DRC Error : In %s CSB high violation at %t Minimum Width allowed : %3.1f ns ", name, $time, tcs/1000); + csb_err <=1; + end + if (CSB_in) begin // get the time for the start of a high pulse + last_csb_rise <=$time; + csb_err <=0; + end +end + +/******** Frequency Test *********/ + +always @(posedge CLK_in or negedge CLK_in) + begin + if ((($time - LastSignalRise) < tSPICLKH ) && ($time > Tper) && !clk_err_h ) begin // check clock high violation + $display("DRC Error : In %s High violation at %t Minimum Width allowed : %3.1f ns ", name, $time, tSPICLKH/1000); + clk_err_h <=1; + end + if (($time > Tper) && ($time - LastSignalFall < tSPICLKL)&& !clk_err_l)begin //check for clock low violation + $display("DRC Error : In %s Low violation at %t Minimum Width allowed : %3.1f ns ", name, $time, tSPICLKL/1000); + clk_err_l <=1; + end + if ((((CLK_in && $time -LastSignalRise < Tper) && $time > Tper))&& !clk_err) begin // check for max frequency violation + $display("DRC Error : Clock Frequency Exceeds Maximum in %s model at time %t.", name, $time); + clk_err<=1; + end + if ((((CLK_in && $time -LastSignalRise < Tper33) && $time > Tper33)) && !clk_err33 && test_33mhz) begin // check for 33 MHz frequency violation + $display ("DRC Error : In %s at : %4.2f this op code is not allowed above 33 Mhz",name ,$time); + clk_err33<=1; + end + if ((($time - LastSignalRise) > tSPICLKH ) && !CLK_in ) // check if clock high violation is gone + clk_err_h <=0; + if ((($time - LastSignalFall) > tSPICLKL ) && CLK_in ) // check if clock low violation is gone + clk_err_l <=0; + if (CLK_in && ($time -LastSignalRise > Tper)) // check if max frequency violation is gone + clk_err <=0; + if ((CLK_in && ($time -LastSignalRise > Tper33))||!test_33mhz) // check if 33 MHz max frequency violation is gone + clk_err33 <=0; + if (CLK_in == 1 ) // save edge time for next iteration + LastSignalRise <= $time; + else + LastSignalFall <= $time; + end + + specify + + if (!CSB)(CLK => MISO) = (100:100:100, 100:100:100); + if ( CSB)(CSB => MISO) = (0:0:0, 0:0:0); + + specparam PATHPULSE$ = 0; + + endspecify + + + +endmodule diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/SRL16.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/SRL16.v new file mode 100644 index 0000000..86b9ef8 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/SRL16.v @@ -0,0 +1,51 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/SRL16.v,v 1.8 2007/05/23 21:43:44 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / 16-Bit Shift Register Look-Up-Table +// /___/ /\ Filename : SRL16.v +// \ \ / \ Timestamp : Thu Mar 25 16:43:40 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. + +`timescale 1 ps / 1 ps + + +module SRL16 (Q, A0, A1, A2, A3, CLK, D); + + parameter INIT = 16'h0000; + + output Q; + + input A0, A1, A2, A3, CLK, D; + + reg [15:0] data; + + + assign Q = data[{A3, A2, A1, A0}]; + + initial + begin + assign data = INIT; + while (CLK === 1'b1 || CLK===1'bX) + #10; + deassign data; + end + + + always @(posedge CLK) + begin + {data[15:0]} <= #100 {data[14:0], D}; + end + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/SRL16E.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/SRL16E.v new file mode 100644 index 0000000..ac59009 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/SRL16E.v @@ -0,0 +1,52 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/SRL16E.v,v 1.8 2007/05/23 21:43:44 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / 16-Bit Shift Register Look-Up-Table with Clock Enable +// /___/ /\ Filename : SRL16E.v +// \ \ / \ Timestamp : Thu Mar 25 16:43:40 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. + +`timescale 1 ps / 1 ps + + +module SRL16E (Q, A0, A1, A2, A3, CE, CLK, D); + + parameter INIT = 16'h0000; + + output Q; + + input A0, A1, A2, A3, CE, CLK, D; + + reg [15:0] data; + + + assign Q = data[{A3, A2, A1, A0}]; + + initial + begin + assign data = INIT; + while (CLK === 1'b1 || CLK===1'bX) + #10; + deassign data; + end + + always @(posedge CLK) + begin + if (CE == 1'b1) begin + {data[15:0]} <= #100 {data[14:0], D}; + end + end + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/SRL16E_1.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/SRL16E_1.v new file mode 100644 index 0000000..654f8aa --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/SRL16E_1.v @@ -0,0 +1,55 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/SRL16E_1.v,v 1.8 2007/05/23 21:43:44 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / 16-Bit Shift Register Look-Up-Table with Clock Enable and Negative-Edge Clock +// /___/ /\ Filename : SRL16E_1.v +// \ \ / \ Timestamp : Thu Mar 25 16:43:40 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. + +`timescale 1 ps / 1 ps + + +module SRL16E_1 (Q, A0, A1, A2, A3, CE, CLK, D); + + parameter INIT = 16'h0000; + + output Q; + + input A0, A1, A2, A3, CE, CLK, D; + + reg [15:0] data; + wire clk_; + + + assign Q = data[{A3, A2, A1, A0}]; + assign clk_ = ~CLK; + + initial + begin + assign data = INIT; + while (clk_ === 1'b1 || clk_===1'bX) + #10; + deassign data; + end + + + always @(posedge clk_) + begin + if (CE == 1'b1) begin + {data[15:0]} <= #100 {data[14:0], D}; + end + end + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/SRL16_1.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/SRL16_1.v new file mode 100644 index 0000000..ac3ff44 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/SRL16_1.v @@ -0,0 +1,53 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/SRL16_1.v,v 1.8 2007/05/23 21:43:44 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / 16-Bit Shift Register Look-Up-Table with Negative-Edge Clock +// /___/ /\ Filename : SRL16_1.v +// \ \ / \ Timestamp : Thu Mar 25 16:43:40 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. + +`timescale 1 ps / 1 ps + + +module SRL16_1 (Q, A0, A1, A2, A3, CLK, D); + + parameter INIT = 16'h0000; + + output Q; + + input A0, A1, A2, A3, CLK, D; + + reg [15:0] data; + wire clk_; + + + assign Q = data[{A3, A2, A1, A0}]; + assign clk_ = ~CLK; + + initial + begin + assign data = INIT; + while (clk_ === 1'b1 || clk_ === 1'bX) + #10; + deassign data; + end + + + always @(posedge clk_) + begin + {data[15:0]} <= #100 {data[14:0], D}; + end + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/SRLC16.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/SRLC16.v new file mode 100644 index 0000000..e0497fc --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/SRLC16.v @@ -0,0 +1,60 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/SRLC16.v,v 1.7 2007/05/23 21:43:44 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / 16-Bit Shift Register Look-Up-Table with Carry +// /___/ /\ Filename : SRLC16.v +// \ \ / \ Timestamp : Thu Mar 25 16:43:40 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Added wire declaration for internal signals. + +`timescale 1 ps / 1 ps + + +module SRLC16 (Q, Q15, A0, A1, A2, A3, CLK, D); + + parameter INIT = 16'h0000; + + output Q, Q15; + + input A0, A1, A2, A3, CLK, D; + + reg [15:0] data; + wire [3:0] addr; + wire q_int; + wire q15_int; + + buf b_a3 (addr[3], A3); + buf b_a2 (addr[2], A2); + buf b_a1 (addr[1], A1); + buf b_a0 (addr[0], A0); + + buf b_q_int (q_int, data[addr]); + buf b_q (Q, q_int); + buf b_q15_int (q15_int, data[15]); + buf b_q15 (Q15, q15_int); + + initial + begin + assign data = INIT; + while (CLK === 1'b1 || CLK===1'bX) + #10; + deassign data; + end + + always @(posedge CLK) begin + {data[15:0]} <= #100 {data[14:0], D}; + end + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/SRLC16E.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/SRLC16E.v new file mode 100644 index 0000000..202f1d9 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/SRLC16E.v @@ -0,0 +1,62 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/SRLC16E.v,v 1.7 2007/05/23 21:43:44 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / 16-Bit Shift Register Look-Up-Table with Carry and Clock Enable +// /___/ /\ Filename : SRLC16E.v +// \ \ / \ Timestamp : Thu Mar 25 16:43:40 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Added wire declaration for internal signals. + +`timescale 1 ps / 1 ps + + +module SRLC16E (Q, Q15, A0, A1, A2, A3, CE, CLK, D); + + parameter INIT = 16'h0000; + + output Q, Q15; + + input A0, A1, A2, A3, CE, CLK, D; + + reg [15:0] data; + wire [3:0] addr; + wire q_int; + wire q15_int; + + buf b_a3 (addr[3], A3); + buf b_a2 (addr[2], A2); + buf b_a1 (addr[1], A1); + buf b_a0 (addr[0], A0); + + buf b_q_int (q_int, data[addr]); + buf b_q (Q, q_int); + buf b_q15_int (q15_int, data[15]); + buf b_q15 (Q15, q15_int); + + initial + begin + assign data = INIT; + while (CLK === 1'b1 || CLK===1'bX) + #10; + deassign data; + end + + always @(posedge CLK) begin + if (CE == 1'b1) begin + {data[15:0]} <= #100 {data[14:0], D}; + end + end + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/SRLC16E_1.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/SRLC16E_1.v new file mode 100644 index 0000000..abd8083 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/SRLC16E_1.v @@ -0,0 +1,66 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/SRLC16E_1.v,v 1.7 2007/05/23 21:43:44 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / 16-Bit Shift Register Look-Up-Table with Carry, Clock Enable and Negative-Edge Clock +// /___/ /\ Filename : SRLC16E_1.v +// \ \ / \ Timestamp : Thu Mar 25 16:43:40 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Added wire declaration for internal signals. + +`timescale 1 ps / 1 ps + + +module SRLC16E_1 (Q, Q15, A0, A1, A2, A3, CE, CLK, D); + + parameter INIT = 16'h0000; + + output Q, Q15; + + input A0, A1, A2, A3, CE, CLK, D; + + reg [15:0] data; + wire [3:0] addr; + wire clk_; + wire q_int; + wire q15_int; + + buf b_a3 (addr[3], A3); + buf b_a2 (addr[2], A2); + buf b_a1 (addr[1], A1); + buf b_a0 (addr[0], A0); + + buf b_q_int (q_int, data[addr]); + buf b_q (Q, q_int); + buf b_q15_int (q15_int, data[15]); + buf b_q15 (Q15, q15_int); + + not i_c (clk_, CLK); + + initial + begin + assign data = INIT; + while (clk_ === 1'b1 || clk_ === 1'bX) + #10; + deassign data; + end + + + always @(posedge clk_) begin + if (CE == 1'b1) begin + {data[15:0]} <= #100 {data[14:0], D}; + end + end + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/SRLC16_1.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/SRLC16_1.v new file mode 100644 index 0000000..3bfadfc --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/SRLC16_1.v @@ -0,0 +1,64 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/SRLC16_1.v,v 1.7 2007/05/23 21:43:44 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / 16-Bit Shift Register Look-Up-Table with Carry and Negative-Edge Clock +// /___/ /\ Filename : SRLC16_1.v +// \ \ / \ Timestamp : Thu Mar 25 16:43:40 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Added wire declaration for internal signals. + +`timescale 1 ps / 1 ps + + +module SRLC16_1 (Q, Q15, A0, A1, A2, A3, CLK, D); + + parameter INIT = 16'h0000; + + output Q, Q15; + + input A0, A1, A2, A3, CLK, D; + + reg [15:0] data; + wire [3:0] addr; + wire clk_; + wire q_int; + wire q15_int; + + buf b_a3 (addr[3], A3); + buf b_a2 (addr[2], A2); + buf b_a1 (addr[1], A1); + buf b_a0 (addr[0], A0); + + buf b_q_int (q_int, data[addr]); + buf b_q (Q, q_int); + buf b_q15_int (q15_int, data[15]); + buf b_q15 (Q15, q15_int); + + not i_c (clk_, CLK); + + initial + begin + assign data = INIT; + while (clk_ === 1'b1 || clk_ ===1'bX) + #10; + deassign data; + end + + + always @(posedge clk_) begin + {data[15:0]} <= #100 {data[14:0], D}; + end + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/SRLC32E.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/SRLC32E.v new file mode 100644 index 0000000..1d90e4a --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/SRLC32E.v @@ -0,0 +1,53 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/rainier/SRLC32E.v,v 1.3 2010/01/06 00:48:06 yanx Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / 32-Bit Shift Register Look-Up-Table with Carry and Clock Enable +// /___/ /\ Filename : SRLC32E.v +// \ \ / \ Timestamp : Thu Mar 25 16:43:40 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/15/05 - Initial version. +// End Revision + +`timescale 1 ps / 1 ps + + +module SRLC32E (Q, Q31, A, CE, CLK, D); + + parameter INIT = 32'h00000000; + + output Q; + output Q31; + + input [4:0] A; + input CE, CLK, D; + + reg [31:0] data; + + + assign Q = data[A]; + assign Q31 = data[31]; + + initial + begin + assign data = INIT; + while (CLK === 1'b1 || CLK===1'bX) + #10; + deassign data; + end + + always @(posedge CLK) + if (CE == 1'b1) + data <= #100 {data[30:0], D}; + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/STARTUP_FPGACORE.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/STARTUP_FPGACORE.v new file mode 100644 index 0000000..c3b6538 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/STARTUP_FPGACORE.v @@ -0,0 +1,32 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/STARTUP_FPGACORE.v,v 1.5 2007/05/23 21:43:44 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / User Interface to Global Clock, Reset and 3-State Controls for FPGACORE +// /___/ /\ Filename : STARTUP_FPGACORE.v +// \ \ / \ Timestamp : Thu Mar 25 16:43:41 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. + +`timescale 1 ps / 1 ps + + +module STARTUP_FPGACORE (CLK, GSR); + + input CLK, GSR; + + tri0 GSR; + + assign glbl.GSR = GSR; + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/STARTUP_SPARTAN3.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/STARTUP_SPARTAN3.v new file mode 100644 index 0000000..e2f116f --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/STARTUP_SPARTAN3.v @@ -0,0 +1,33 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/STARTUP_SPARTAN3.v,v 1.5 2007/05/23 21:43:44 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / User Interface to Global Clock, Reset and 3-State Controls for SPARTAN3 +// /___/ /\ Filename : STARTUP_SPARTAN3.v +// \ \ / \ Timestamp : Thu Mar 25 16:43:41 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. + +`timescale 1 ps / 1 ps + + +module STARTUP_SPARTAN3 (CLK, GSR, GTS); + + input CLK, GSR, GTS; + + tri0 GSR, GTS; + + assign glbl.GSR = GSR; + assign glbl.GTS = GTS; + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/STARTUP_SPARTAN3A.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/STARTUP_SPARTAN3A.v new file mode 100644 index 0000000..b78ba9c --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/STARTUP_SPARTAN3A.v @@ -0,0 +1,31 @@ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / User Interface to Global Clock, Reset and 3-State Controls for SPARTAN3A +// /___/ /\ Filename : STARTUP_SPARTAN3A.v +// \ \ / \ Timestamp : Fri Jul 1 14:45:00 PDT 2005 +// \___\/\___\ +// +// Revision: +// 07/01/05 - Initial version. +// End Revision + +`timescale 1 ps / 1 ps + + +module STARTUP_SPARTAN3A (CLK, GSR, GTS); + + input CLK, GSR, GTS; + + tri0 GSR, GTS; + + assign glbl.GSR = GSR; + assign glbl.GTS = GTS; + +endmodule diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/STARTUP_SPARTAN3E.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/STARTUP_SPARTAN3E.v new file mode 100644 index 0000000..5b07c37 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/STARTUP_SPARTAN3E.v @@ -0,0 +1,55 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/spartan4/STARTUP_SPARTAN3E.v,v 1.4 2004/09/04 00:05:53 wloo Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / User Interface to Global Clock, Reset and 3-State Controls for SPARTAN3E +// /___/ /\ Filename : STARTUP_SPARTAN3E.v +// \ \ / \ Timestamp : Thu Mar 25 16:43:41 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. + +`timescale 1 ns / 1 ps + +module STARTUP_SPARTAN3E (CLK, GSR, GTS, MBT); + + input CLK, GSR, GTS, MBT; + + tri0 GSR, GTS; + + reg disable_mbt = 0; + time init_time, min_time; + + assign glbl.GSR = GSR; + assign glbl.GTS = GTS; + + // only the first valid active low MBT ( > 300ns) will put out the message + always @(MBT) begin + + if (!disable_mbt) begin + + if (MBT == 1'b0) begin + if ($time != 0) + init_time = $time; + end + else if (MBT == 1'b1) begin + min_time = $time - init_time; + if (min_time >= 300) begin + $display ("Soft Boot has been initiated."); + disable_mbt = 1; + end + end + + end // if (!disable_mbt) + + end // always @ (MBT) + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/STARTUP_SPARTAN6.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/STARTUP_SPARTAN6.v new file mode 100644 index 0000000..4c072c0 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/STARTUP_SPARTAN6.v @@ -0,0 +1,61 @@ +/////////////////////////////////////////////////////// +// Copyright (c) 1995/2006 Xilinx Inc. +// All Right Reserved. +/////////////////////////////////////////////////////// +// +// ____ ___ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : +// / / +// /__/ /\ Filename : STARTUP_SPARTAN6.v +// \ \ / \ +// \__\/\__ \ +// +// Revision: 1.0 +// 10/30/09 - CR 537641 -- Added CFGMCLK functionality. +// End Revision + +`timescale 1 ps / 1 ps + +module STARTUP_SPARTAN6 ( + CFGCLK, + CFGMCLK, + EOS, + CLK, + GSR, + GTS, + KEYCLEARB +); + + output CFGCLK; + output CFGMCLK; + output EOS; + + input CLK; + input GSR; + input GTS; + input KEYCLEARB; + + tri0 GSR, GTS; + + time CFGMCLK_PERIOD = 20000; + reg cfgmclk_out; + + initial begin + cfgmclk_out = 0; + forever #(CFGMCLK_PERIOD/2.0) cfgmclk_out = !cfgmclk_out; + end + + assign CFGMCLK = cfgmclk_out; + + assign glbl.GSR = GSR; + assign glbl.GTS = GTS; + + specify + specparam PATHPULSE$ = 0; + endspecify + + +endmodule diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/STARTUP_VIRTEX4.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/STARTUP_VIRTEX4.v new file mode 100644 index 0000000..d166151 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/STARTUP_VIRTEX4.v @@ -0,0 +1,43 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/virtex4/STARTUP_VIRTEX4.v,v 1.4 2007/06/06 22:14:07 fphillip Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / User Interface to Global Clock, Reset and 3-State Controls for VIRTEX4 +// /___/ /\ Filename : STARTUP_VIRTEX4.v +// \ \ / \ Timestamp : Thu Mar 25 16:43:52 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 06/06/07 - Fixed timescale values +// End Revision + + +`timescale 1 ps / 1 ps + + +module STARTUP_VIRTEX4 (EOS, CLK, GSR, GTS, USRCCLKO, USRCCLKTS, USRDONEO, USRDONETS); + + output EOS; + + input CLK; + input GSR; + input GTS; + input USRCCLKO; + input USRCCLKTS; + input USRDONEO; + input USRDONETS; + + tri0 GSR, GTS; + + assign glbl.GSR = GSR; + assign glbl.GTS = GTS; + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/STARTUP_VIRTEX5.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/STARTUP_VIRTEX5.v new file mode 100644 index 0000000..e540543 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/STARTUP_VIRTEX5.v @@ -0,0 +1,70 @@ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / User Interface to Global Clock, Reset and 3-State Controls for VIRTEX5 +// /___/ /\ Filename : STARTUP_VIRTEX5.v +// \ \ / \ Timestamp : Thu Jul 21 13:42:30 PDT 2005 +// \___\/\___\ +// +// Revision: +// 07/21/05 - Initial version. +// 10/30/09 - CR 537429 -- Added CFGMCLK functionality. +// End Revision + +`timescale 1 ps / 1 ps + +module STARTUP_VIRTEX5 ( + CFGCLK, + CFGMCLK, + DINSPI, + EOS, + TCKSPI, + CLK, + GSR, + GTS, + USRCCLKO, + USRCCLKTS, + USRDONEO, + USRDONETS +); + +output CFGCLK; +output CFGMCLK; +output DINSPI; +output EOS; +output TCKSPI; + +input CLK; +input GSR; +input GTS; +input USRCCLKO; +input USRCCLKTS; +input USRDONEO; +input USRDONETS; + +tri0 GSR, GTS; + + assign glbl.GSR = GSR; + assign glbl.GTS = GTS; + + time CFGMCLK_PERIOD = 10000; + + reg cfgmclk_out; + + initial begin + cfgmclk_out = 0; + forever #(CFGMCLK_PERIOD) cfgmclk_out = !cfgmclk_out; + end + + assign CFGMCLK = cfgmclk_out; +specify + specparam PATHPULSE$ = 0; +endspecify + +endmodule diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/STARTUP_VIRTEX6.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/STARTUP_VIRTEX6.v new file mode 100644 index 0000000..ccdb304 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/STARTUP_VIRTEX6.v @@ -0,0 +1,76 @@ +/////////////////////////////////////////////////////// +// Copyright (c) 1995/2006 Xilinx Inc. +// All Right Reserved. +/////////////////////////////////////////////////////// +// +// ____ ___ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : +// / / +// /__/ /\ Filename : STARTUP_VIRTEX6.v +// \ \ / \ +// \__\/\__ \ +// +// 10/30/09 - CR 537641 -- Added CFGMCLK functionality. +// End Revision + +`timescale 1 ps / 1 ps + +module STARTUP_VIRTEX6 ( + CFGCLK, + CFGMCLK, + DINSPI, + EOS, + PREQ, + TCKSPI, + CLK, + GSR, + GTS, + KEYCLEARB, + PACK, + USRCCLKO, + USRCCLKTS, + USRDONEO, + USRDONETS +); + parameter PROG_USR = "FALSE"; + + output CFGCLK; + output CFGMCLK; + output DINSPI; + output EOS; + output PREQ; + output TCKSPI; + + input CLK; + input GSR; + input GTS; + input KEYCLEARB; + input PACK; + input USRCCLKO; + input USRCCLKTS; + input USRDONEO; + input USRDONETS; + + tri0 GSR, GTS; + + assign glbl.GSR = GSR; + assign glbl.GTS = GTS; + time CFGMCLK_PERIOD = 20000; + + reg cfgmclk_out; + + initial begin + cfgmclk_out = 0; + forever #(CFGMCLK_PERIOD/2.0) cfgmclk_out = !cfgmclk_out; + end + + assign CFGMCLK = cfgmclk_out; + + specify + specparam PATHPULSE$ = 0; + endspecify + +endmodule diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/SUSPEND_SYNC.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/SUSPEND_SYNC.v new file mode 100644 index 0000000..0c656d2 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/SUSPEND_SYNC.v @@ -0,0 +1,31 @@ +/////////////////////////////////////////////////////// +// Copyright (c) 1995/2006 Xilinx Inc. +// All Right Reserved. +/////////////////////////////////////////////////////// +// +// ____ ___ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : +// / / +// /__/ /\ Filename : SUSPEND_SYNC.v +// \ \ / \ +// \__\/\__ \ +// +/////////////////////////////////////////////////////// + +`timescale 1 ps / 1 ps + +module SUSPEND_SYNC ( + SREQ, + CLK, + SACK +); + + output SREQ; + + input CLK; + input SACK; + +endmodule diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/SYSMON.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/SYSMON.v new file mode 100644 index 0000000..5c9a3b4 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/SYSMON.v @@ -0,0 +1,2059 @@ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2005 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Function Simulation Library Component +// / / System Monitor +// /___/ /\ Filename : SYSMON.v +// \ \ / \ Timestamp : +// \___\/\___\ +// +// Revision: +// 06/15/04 - Initial version. +// 09/16/05 - Updated according to HW Usage Documents. +// 01/06/06 - Modified to match HW waveform for HW test cases. +// 03/08/06 - Add intial to internal signals. (BT1044) +// - add parameter type (CR 226003) +// 05/19/06 - align with vhdl model. (CR231777). +// 08/30/06 - GSR only reset DRP port (CR 422678). +// 09/06/06 - Add internal 1 ns reset at time 0 (CR422678). +// 09/14/06 - Match vhdl model (CR 424061). +// 09/26/06 - Update error messages; Make unipolar same as bipolar for external channels; +// - extend file reader one_line register to 600 characters etc. (CR426629). +// 10/30/06 - Match HW timing (CR 428185) +// 12/13/06 - Reset eoc_out_temp1 when calibration channel (CR430923) +// Change INIT_42 to 0800h (CR 429642). +// 06/04/07 - Add wire declaration to internal signal. +// 07/17/07 - Add SIM_DEVICE attribute allow clock divider lower to 2 for MBLANC. +// 04/01/08 - Remove setup/hold check for CONVST. (CR470708) +// 04/15/08 - DEN need toggled and can not just pull high (CR471205). +// 05/07/08 - Add negative setup/hold support (CR468872) +// 05/26/08 - Add vector range to parameter align with yaml. +// 09/02/08 - Change MBLANC to VIRTEX6. +// 10/09/08 - Change OT temperature max from 120 degree to 125 degree. (CR491781) +// 02/12/09 - Add V6 changes. +// 05/21/09 - Remove alarm bits from status_reg (CR522721) +// End Revision + + +`timescale 1ps / 1ps +//`define EOFile -1 + +module SYSMON ( + ALM, + BUSY, + CHANNEL, + DO, + DRDY, + EOC, + EOS, + JTAGBUSY, + JTAGLOCKED, + JTAGMODIFIED, + OT, + CONVST, + CONVSTCLK, + DADDR, + DCLK, + DEN, + DI, + DWE, + RESET, + VAUXN, + VAUXP, + VN, + VP + +); + +output BUSY; +output DRDY; +output EOC; +output EOS; +output JTAGBUSY; +output JTAGLOCKED; +output JTAGMODIFIED; +output OT; +output [15:0] DO; +output [2:0] ALM; +output [4:0] CHANNEL; + +input CONVST; +input CONVSTCLK; +input DCLK; +input DEN; +input DWE; +input RESET; +input VN; +input VP; +input [15:0] DI; +input [15:0] VAUXN; +input [15:0] VAUXP; +input [6:0] DADDR; + + parameter [15:0] INIT_40 = 16'h0; + parameter [15:0] INIT_41 = 16'h0; + parameter [15:0] INIT_42 = 16'h0800; + parameter [15:0] INIT_43 = 16'h0; + parameter [15:0] INIT_44 = 16'h0; + parameter [15:0] INIT_45 = 16'h0; + parameter [15:0] INIT_46 = 16'h0; + parameter [15:0] INIT_47 = 16'h0; + parameter [15:0] INIT_48 = 16'h0; + parameter [15:0] INIT_49 = 16'h0; + parameter [15:0] INIT_4A = 16'h0; + parameter [15:0] INIT_4B = 16'h0; + parameter [15:0] INIT_4C = 16'h0; + parameter [15:0] INIT_4D = 16'h0; + parameter [15:0] INIT_4E = 16'h0; + parameter [15:0] INIT_4F = 16'h0; + parameter [15:0] INIT_50 = 16'h0; + parameter [15:0] INIT_51 = 16'h0; + parameter [15:0] INIT_52 = 16'h0; + parameter [15:0] INIT_53 = 16'h0; + parameter [15:0] INIT_54 = 16'h0; + parameter [15:0] INIT_55 = 16'h0; + parameter [15:0] INIT_56 = 16'h0; + parameter [15:0] INIT_57 = 16'h0; + parameter SIM_DEVICE = "VIRTEX5"; + parameter SIM_MONITOR_FILE = "design.txt"; + + + localparam INIT_STATE = 0, + SINGLE_SEQ_STATE = 1, + ACQ_STATE = 2, + CONV_STATE = 3, + END_STATE = 5, + RST_STATE = 6; + + time time_out, prev_time_out; + + integer temperature_index = -1, time_index = -1, vccaux_index = -1; + integer vccint_index = -1, vn_index = -1, vp_index = -1; + integer vauxp_idx0 = -1, vauxn_idx0 = -1; + integer vauxp_idx1 = -1, vauxn_idx1 = -1; + integer vauxp_idx2 = -1, vauxn_idx2 = -1; + integer vauxp_idx3 = -1, vauxn_idx3 = -1; + integer vauxp_idx4 = -1, vauxn_idx4 = -1; + integer vauxp_idx5 = -1, vauxn_idx5 = -1; + integer vauxp_idx6 = -1, vauxn_idx6 = -1; + integer vauxp_idx7 = -1, vauxn_idx7 = -1; + integer vauxp_idx8 = -1, vauxn_idx8 = -1; + integer vauxp_idx9 = -1, vauxn_idx9 = -1; + integer vauxp_idx10 = -1, vauxn_idx10 = -1; + integer vauxp_idx11 = -1, vauxn_idx11 = -1; + integer vauxp_idx12 = -1, vauxn_idx12 = -1; + integer vauxp_idx13 = -1, vauxn_idx13 = -1; + integer vauxp_idx14 = -1, vauxn_idx14 = -1; + integer vauxp_idx15 = -1, vauxn_idx15 = -1; + integer char_1, char_2, fs, fd; + integer num_arg, num_val; + integer clk_count, seq_count; + integer seq_status_avg, acq_count; + integer conv_avg_count [31:0]; + integer conv_acc [31:0]; + integer conv_result_int; + integer conv_time, conv_count, conv_time_cal, conv_time_cal_1; + integer h, i, j, k, l, m, n, p; + integer file_line; + +// string + reg [8*12:1] label0, label1, label2, label3, label4, label5, label6, label7, label8, label9, label10, label11, label12, label13, label14, label15, label16, label17, label18, label19, label20, label21, label22, label23, label24, label25, label26, label27, label28, label29, label30, label31, label32, label33, label34, label35, label36, label37, label38, label39; + reg [8*600:1] one_line; + reg [8*12:1] label [40:0]; + reg [8*12:1] tmp_label; + reg end_of_file; + + real column_real0, column_real1, column_real2, column_real3, column_real4, column_real5, column_real6, column_real7, column_real8, column_real9, column_real10, column_real11, column_real12, column_real13, column_real14, column_real15, column_real16, column_real17, column_real18, column_real19, column_real20, column_real21, column_real22, column_real23, column_real24, column_real25, column_real26, column_real27, column_real28, column_real29, column_real30, column_real31, column_real32, column_real33, column_real34, column_real35, column_real36, column_real37, column_real38, column_real39; + +// array of real numbers +// real column_real [39:0]; + reg [63:0] column_real [39:0]; + reg [63:0] chan_val [31:0]; + reg [63:0] chan_val_tmp [31:0]; + reg [63:0] chan_valn [31:0]; + reg [63:0] chan_valn_tmp [31:0]; + reg [63:0] analog_in_diff [31:0]; + reg [63:0] analog_in_uni [31:0]; + reg [63:0] analog_comm_in [31:0]; + + real chan_val_p_tmp, chan_val_n_tmp; + real analog_mux_in, analog_in_tmp, analog_comm_in_tmp, analog_in_comm; + real adc_temp_result, adc_intpwr_result; + real adc_ext_result; + + reg sim_device_int; + reg seq_reset, seq_reset_dly, seq_reset_flag, seq_reset_flag_dly; + reg soft_reset = 0; + reg en_data_flag; + reg first_cal_chan; + reg seq_en; + reg seq_en_dly; + wire [15:0] status_reg; + reg [15:0] ot_limit_reg = 16'hCA00; + reg [15:0] ot_sf_limit_low_reg = 16'hAE40; + reg [23:0] conv_acc_vec; + reg [15:0] conv_result; + reg [15:0] conv_result_reg, conv_acc_result; + wire [7:0] curr_clkdiv_sel; + reg [2:0] alarm_out_reg; + reg [4:0] curr_chan, curr_chan_lat; + reg [2:0] adc_state, next_state; + reg conv_start, conv_end; + reg eos_en, eos_tmp_en; + reg drdy_out, drdy_out_tmp1, drdy_out_tmp2, drdy_out_tmp3, drdy_out_tmp4; + reg ot_out_reg; + reg [15:0] do_out; + reg [15:0] do_out_rdtmp; + reg [15:0] data_reg [39:0]; + reg [15:0] dr_sram [111:64]; + reg sysclk, adcclk_tmp; + wire adcclk; + reg [1:0] curr_seq1_0, curr_seq1_0_lat; + reg curr_e_c, curr_b_u, curr_acq; + reg seq_count_en; + reg [4:0] acq_chan; + reg acq_b_u; + reg adc_s1_flag, acq_acqsel; + wire acq_e_c; + reg acq_e_c_tmp5, acq_e_c_tmp6; + reg [1:0] curr_avg_set; + reg eoc_en, eoc_en_delay; + reg eoc_out_tmp, eos_out_tmp; + reg eoc_out_tmp1, eos_out_tmp1; + reg eoc_out, eos_out; + reg busy_r, busy_r_rst; + reg busy_sync1, busy_sync2; + wire busy_sync_fall, busy_sync_rise; + reg notifier, notifier_do; + reg [4:0] channel_out; + reg rst_lock, rst_lock_early; + reg sim_file_flag; + reg [6:0] daddr_in_lat; + reg [15:0] init40h_tmp, init41h_tmp, init42h_tmp, init4eh_tmp; + reg [2:0] alarm_out; + reg ot_out; + reg [15:0] curr_seq; + reg busy_out, busy_rst, busy_conv, busy_out_tmp, busy_seq_rst; + reg [1:0] seq1_0, seq_bits; + reg ot_en, alarm_update, drp_update, cal_chan_update; + reg [2:0] alarm_en; + reg [4:0] scon_tmp; + wire [15:0] seq_chan_reg1, seq_chan_reg2, seq_acq_reg1, seq_acq_reg2; + wire [15:0] seq_avg_reg1, seq_avg_reg2, seq_du_reg1, seq_du_reg2; + reg [15:0] cfg_reg1_init; + + reg [4:0] seq_curr_i; + integer busy_rst_cnt; + integer si, seq_num; + integer seq_mem [32:0]; + + wire rst_in, adc_convst; + wire [15:0] cfg_reg0; + wire [15:0] cfg_reg1; + wire [15:0] cfg_reg2; + wire [15:0] di_in; + wire [6:0] daddr_in; + wire [15:0] tmp_data_reg_out, tmp_dr_sram_out; + wire convst_in; + wire rst_in_not_seq; + wire adcclk_div1; + wire gsr_in; + wire convst_raw_in, convstclk_in, dclk_in, den_in, rst_input, dwe_in; + wire DCLK_dly, DEN_dly, DWE_dly; + wire [6:0] DADDR_dly; + wire [15:0] DI_dly; + + tri0 GSR = glbl.GSR; + + assign #100 BUSY = busy_out; + assign #100 DRDY = drdy_out; + assign #100 EOC = eoc_out; + assign #100 EOS = eos_out; + assign #100 OT = ot_out; + assign #100 DO = do_out; + assign #100 CHANNEL = channel_out; + assign #100 ALM = alarm_out; + + assign convst_raw_in = CONVST; + assign convstclk_in = CONVSTCLK; + assign dclk_in = DCLK; + assign den_in = DEN; + assign rst_input = RESET; + assign dwe_in = DWE; + assign di_in = DI; + assign daddr_in = DADDR; + assign gsr_in = GSR; + assign convst_in = (convst_raw_in===1 || convstclk_in===1) ? 1: 0; + assign JTAGLOCKED = 0; + assign JTAGMODIFIED = 0; + assign JTAGBUSY = 0; + + initial begin + + init40h_tmp = INIT_40; + init41h_tmp = INIT_41; + init42h_tmp = INIT_42; + init4eh_tmp = INIT_4E; + + if ((init41h_tmp[13:12]==2'b11) && (init40h_tmp[8]==1) && (init40h_tmp[4:0] != 5'b00011) && (init40h_tmp[4:0] < 5'b10000)) + $display(" Attribute Syntax warning : The attribute INIT_40 on SYSMON instance %m is set to %x. Bit[8] of this attribute must be set to 0. Long acquistion mode is only allowed for external channels", INIT_40); + + if ((init41h_tmp[13:12]!=2'b11) && (init4eh_tmp[10:0]!=11'b0) && (init4eh_tmp[15:12]!=4'b0)) + $display(" Attribute Syntax warning : The attribute INIT_4E on SYSMON instance %m is set to %x. Bit[15:12] and bit[10:0] of this attribute must be set to 0. Long acquistion mode is only allowed for external channels", INIT_4E); + + if ((init41h_tmp[13:12]==2'b11) && (init40h_tmp[9]==1) && (init40h_tmp[4:0] != 5'b00011) && (init40h_tmp[4:0] < 5'b10000)) + $display(" Attribute Syntax warning : The attribute INIT_40 on SYSMON instance %m is set to %x. Bit[9] of this attribute must be set to 0. Event mode timing can only be used with external channels, and only in single channel mode.", INIT_40); + + if ((init41h_tmp[13:12]==2'b11) && (init40h_tmp[13:12]!=2'b00) && (INIT_48 != 16'h0000) && (INIT_49 != 16'h0000)) + $display(" Attribute Syntax warning : INIT_48 and INIT_49 are %x and %x on SYSMON instance %m. Those attributes must be set to 0000h in single channel mode and averaging enabled.", INIT_48, INIT_49); + + if (init42h_tmp[1:0] != 2'b00) + $display(" Attribute Syntax Error : The attribute INIT_42 on SYSMON instance %m is set to %x. Bit[1:0] of this attribute must be set to 0h.", INIT_42); + + if (SIM_DEVICE == "VIRTEX6") begin + sim_device_int = 1; + if (init42h_tmp[15:8] < 8'b00000010) begin + $display(" Attribute Syntax Error : The attribute INIT_42 on SYSMON instance %m is set to %x. Bit[15:8] of this attribute is the ADC Clock divider and must be equal or greater than 2. ", INIT_42); + $finish; + end + end + else begin + sim_device_int = 0; + if (init42h_tmp[15:8] < 8'b00001000) begin + $display(" Attribute Syntax Error : The attribute INIT_42 on SYSMON instance %m is set to %x. Bit[15:8] of this attribute is the ADC Clock divider and must be equal or greater than 8. ", INIT_42); + $finish; + end + end + + if (INIT_43 != 16'h0) + $display(" Warning : The attribute INIT_43 on SYSMON instance %m is set to %x. This must be set to 0000h.", INIT_43); + + if (INIT_44 != 16'h0) + $display(" Warning : The attribute INIT_44 on SYSMON instance %m is set to %x. This must be set to 0000h.", INIT_44); + + if (INIT_45 != 16'h0) + $display(" Warning : The attribute INIT_45 on SYSMON instance %m is set to %x. This must be set to 0000h.", INIT_45); + + if (INIT_46 != 16'h0) + $display(" Warning : The attribute INIT_46 on SYSMON instance %m is set to %x. This must be set to 0000h.", INIT_46); + + if (INIT_47 != 16'h0) + $display(" Warning : The attribute INIT_47 on SYSMON instance %m is set to %x. This must be set to 0000h.", INIT_47); + + end + + initial begin + dr_sram[7'h40] = INIT_40; + dr_sram[7'h41] = INIT_41; + dr_sram[7'h42] = INIT_42; + dr_sram[7'h43] = INIT_43; + dr_sram[7'h44] = INIT_44; + dr_sram[7'h45] = INIT_45; + dr_sram[7'h46] = INIT_46; + dr_sram[7'h47] = INIT_47; + dr_sram[7'h48] = INIT_48; + dr_sram[7'h49] = INIT_49; + dr_sram[7'h4A] = INIT_4A; + dr_sram[7'h4B] = INIT_4B; + dr_sram[7'h4C] = INIT_4C; + dr_sram[7'h4D] = INIT_4D; + dr_sram[7'h4E] = INIT_4E; + dr_sram[7'h4F] = INIT_4F; + dr_sram[7'h50] = INIT_50; + dr_sram[7'h51] = INIT_51; + dr_sram[7'h52] = INIT_52; + dr_sram[7'h53] = INIT_53; + dr_sram[7'h54] = INIT_54; + dr_sram[7'h55] = INIT_55; + dr_sram[7'h56] = INIT_56; + dr_sram[7'h57] = INIT_57; + + + end // initial begin + +// read input file + initial begin + char_1 = 0; + char_2 = 0; + time_out = 0; + sim_file_flag = 0; + file_line = -1; + end_of_file = 0; + fd = $fopen(SIM_MONITOR_FILE, "r"); + if (fd == 0) + begin + $display(" *** Warning: The analog data file %s for SYSMON instance %m was not found. Use the SIM_MONITOR_FILE parameter to specify the analog data file name or use the default name: design.txt.\n", SIM_MONITOR_FILE); + sim_file_flag = 1; + end + + if (sim_file_flag == 0) begin + while (end_of_file==0) begin + file_line = file_line + 1; + char_1 = $fgetc (fd); + char_2 = $fgetc (fd); +// if(char_2==`EOFile) + if(char_2== -1) + end_of_file = 1; + else begin + + // Ignore Comments + if ((char_1 == "/" & char_2 == "/") | char_1 == "#" | (char_1 == "-" & char_2 == "-")) begin + + fs = $ungetc (char_2, fd); + fs = $ungetc (char_1, fd); + fs = $fgets (one_line, fd); + + end + // Getting labels + else if ((char_1 == "T" & char_2 == "I" ) || + (char_1 == "T" & char_2 == "i" ) || + (char_1 == "t" & char_2 == "i" ) || (char_1 == "t" & char_2 == "I" )) begin + + fs = $ungetc (char_2, fd); + fs = $ungetc (char_1, fd); + fs = $fgets (one_line, fd); + + num_arg = $sscanf (one_line, "%s %s %s %s %s %s %s %s %s %s %s %s %s %s %s %s %s %s %s %s %s %s %s %s %s %s %s %s %s %s %s %s %s %s %s %s %s %s %s %s", label0, label1, label2, label3, label4, label5, label6, label7, label8, label9, label10, label11, label12, label13, label14, label15, label16, label17, label18, label19, label20, label21, label22, label23, label24, label25, label26, label27, label28, label29, label30,label31, label32, label33, label34, label35, label36, label37, label38, label39); + + label[0] = label0; + label[1] = label1; + label[2] = label2; + label[3] = label3; + label[4] = label4; + label[5] = label5; + label[6] = label6; + label[7] = label7; + label[8] = label8; + label[9] = label9; + label[10] = label10; + label[11] = label11; + label[12] = label12; + label[13] = label13; + label[14] = label14; + label[15] = label15; + label[16] = label16; + label[17] = label17; + label[18] = label18; + label[19] = label19; + label[20] = label20; + label[21] = label21; + label[22] = label22; + label[23] = label23; + label[24] = label24; + label[25] = label25; + label[26] = label26; + label[27] = label27; + label[28] = label28; + label[29] = label29; + label[30] = label30; + label[31] = label31; + label[32] = label32; + label[33] = label33; + label[34] = label34; + label[35] = label35; + label[36] = label36; + label[37] = label37; + label[38] = label38; + label[39] = label39; + + for (m = 0; m < num_arg; m = m +1) begin + tmp_label = 96'b0; + tmp_label = to_upcase_label(label[m]); + case (tmp_label) + + "TEMP" : temperature_index = m; + "TIME" : time_index = m; + "VCCAUX" : vccaux_index = m; + "VCCINT" : vccint_index = m; + "VN" : vn_index = m; + "VAUXN[0]" : vauxn_idx0 = m; + "VAUXN[1]" : vauxn_idx1 = m; + "VAUXN[2]" : vauxn_idx2 = m; + "VAUXN[3]" : vauxn_idx3 = m; + "VAUXN[4]" : vauxn_idx4 = m; + "VAUXN[5]" : vauxn_idx5 = m; + "VAUXN[6]" : vauxn_idx6 = m; + "VAUXN[7]" : vauxn_idx7 = m; + "VAUXN[8]" : vauxn_idx8 = m; + "VAUXN[9]" : vauxn_idx9 = m; + "VAUXN[10]" : vauxn_idx10 = m; + "VAUXN[11]" : vauxn_idx11 = m; + "VAUXN[12]" : vauxn_idx12 = m; + "VAUXN[13]" : vauxn_idx13 = m; + "VAUXN[14]" : vauxn_idx14 = m; + "VAUXN[15]" : vauxn_idx15 = m; + "VP" : vp_index = m; + "VAUXP[0]" : vauxp_idx0 = m; + "VAUXP[1]" : vauxp_idx1 = m; + "VAUXP[2]" : vauxp_idx2 = m; + "VAUXP[3]" : vauxp_idx3 = m; + "VAUXP[4]" : vauxp_idx4 = m; + "VAUXP[5]" : vauxp_idx5 = m; + "VAUXP[6]" : vauxp_idx6 = m; + "VAUXP[7]" : vauxp_idx7 = m; + "VAUXP[8]" : vauxp_idx8 = m; + "VAUXP[9]" : vauxp_idx9 = m; + "VAUXP[10]" : vauxp_idx10 = m; + "VAUXP[11]" : vauxp_idx11 = m; + "VAUXP[12]" : vauxp_idx12 = m; + "VAUXP[13]" : vauxp_idx13 = m; + "VAUXP[14]" : vauxp_idx14 = m; + "VAUXP[15]" : vauxp_idx15 = m; + default : begin + $display("Analog Data File Error : The channel name %s is invalid in the input file for SYSMON instance %m.", tmp_label); + infile_format; + end + endcase + + end // for (m = 0; m < num_arg; m = m +1) + + end + // Getting column values + else if (char_1 == "0" | char_1 == "1" | char_1 == "2" | char_1 == "3" | char_1 == "4" | char_1 == "5" | char_1 == "6" | char_1 == "7" | char_1 == "8" | char_1 == "9") begin + + fs = $ungetc (char_2, fd); + fs = $ungetc (char_1, fd); + fs = $fgets (one_line, fd); + + column_real0 = 0.0; + column_real1 = 0.0; + column_real2 = 0.0; + column_real3 = 0.0; + column_real4 = 0.0; + column_real5 = 0.0; + column_real6 = 0.0; + column_real7 = 0.0; + column_real8 = 0.0; + column_real9 = 0.0; + column_real10 = 0.0; + column_real11 = 0.0; + column_real12 = 0.0; + column_real13 = 0.0; + column_real14 = 0.0; + column_real15 = 0.0; + column_real16 = 0.0; + column_real17 = 0.0; + column_real18 = 0.0; + column_real19 = 0.0; + column_real20 = 0.0; + column_real21 = 0.0; + column_real22 = 0.0; + column_real23 = 0.0; + column_real24 = 0.0; + column_real25 = 0.0; + column_real26 = 0.0; + column_real27 = 0.0; + column_real28 = 0.0; + column_real29 = 0.0; + column_real30 = 0.0; + column_real31 = 0.0; + column_real32 = 0.0; + column_real33 = 0.0; + column_real34 = 0.0; + column_real35 = 0.0; + column_real36 = 0.0; + column_real37 = 0.0; + column_real38 = 0.0; + column_real39 = 0.0; + + num_val = $sscanf (one_line, "%f %f %f %f %f %f %f %f %f %f %f %f %f %f %f %f %f %f %f %f %f %f %f %f %f %f %f %f %f %f %f %f %f %f %f %f %f %f %f %f", column_real0, column_real1, column_real2, column_real3, column_real4, column_real5, column_real6, column_real7, column_real8, column_real9, column_real10, column_real11, column_real12, column_real13, column_real14, column_real15, column_real16, column_real17, column_real18, column_real19, column_real20, column_real21, column_real22, column_real23, column_real24, column_real25, column_real26, column_real27, column_real28, column_real29, column_real30, column_real31, column_real32, column_real33, column_real34, column_real35, column_real36, column_real37, column_real38, column_real39); + + column_real[0] = $realtobits(column_real0); + column_real[1] = $realtobits(column_real1); + column_real[2] = $realtobits(column_real2); + column_real[3] = $realtobits(column_real3); + column_real[4] = $realtobits(column_real4); + column_real[5] = $realtobits(column_real5); + column_real[6] = $realtobits(column_real6); + column_real[7] = $realtobits(column_real7); + column_real[8] = $realtobits(column_real8); + column_real[9] = $realtobits(column_real9); + column_real[10] = $realtobits(column_real10); + column_real[11] = $realtobits(column_real11); + column_real[12] = $realtobits(column_real12); + column_real[13] = $realtobits(column_real13); + column_real[14] = $realtobits(column_real14); + column_real[15] = $realtobits(column_real15); + column_real[16] = $realtobits(column_real16); + column_real[17] = $realtobits(column_real17); + column_real[18] = $realtobits(column_real18); + column_real[19] = $realtobits(column_real19); + column_real[20] = $realtobits(column_real20); + column_real[21] = $realtobits(column_real21); + column_real[22] = $realtobits(column_real22); + column_real[23] = $realtobits(column_real23); + column_real[24] = $realtobits(column_real24); + column_real[25] = $realtobits(column_real25); + column_real[26] = $realtobits(column_real26); + column_real[27] = $realtobits(column_real27); + column_real[28] = $realtobits(column_real28); + column_real[29] = $realtobits(column_real29); + column_real[30] = $realtobits(column_real30); + column_real[31] = $realtobits(column_real31); + column_real[32] = $realtobits(column_real32); + column_real[33] = $realtobits(column_real33); + column_real[34] = $realtobits(column_real34); + column_real[35] = $realtobits(column_real35); + column_real[36] = $realtobits(column_real36); + column_real[37] = $realtobits(column_real37); + column_real[38] = $realtobits(column_real38); + column_real[39] = $realtobits(column_real39); + + chan_val[0] = column_real[temperature_index]; + chan_val[1] = column_real[vccint_index]; + chan_val[2] = column_real[vccaux_index]; + chan_val[3] = column_real[vp_index]; + chan_val[16] = column_real[vauxp_idx0]; + chan_val[17] = column_real[vauxp_idx1]; + chan_val[18] = column_real[vauxp_idx2]; + chan_val[19] = column_real[vauxp_idx3]; + chan_val[20] = column_real[vauxp_idx4]; + chan_val[21] = column_real[vauxp_idx5]; + chan_val[22] = column_real[vauxp_idx6]; + chan_val[23] = column_real[vauxp_idx7]; + chan_val[24] = column_real[vauxp_idx8]; + chan_val[25] = column_real[vauxp_idx9]; + chan_val[26] = column_real[vauxp_idx10]; + chan_val[27] = column_real[vauxp_idx11]; + chan_val[28] = column_real[vauxp_idx12]; + chan_val[29] = column_real[vauxp_idx13]; + chan_val[30] = column_real[vauxp_idx14]; + chan_val[31] = column_real[vauxp_idx15]; + + chan_valn[3] = column_real[vn_index]; + chan_valn[16] = column_real[vauxn_idx0]; + chan_valn[17] = column_real[vauxn_idx1]; + chan_valn[18] = column_real[vauxn_idx2]; + chan_valn[19] = column_real[vauxn_idx3]; + chan_valn[20] = column_real[vauxn_idx4]; + chan_valn[21] = column_real[vauxn_idx5]; + chan_valn[22] = column_real[vauxn_idx6]; + chan_valn[23] = column_real[vauxn_idx7]; + chan_valn[24] = column_real[vauxn_idx8]; + chan_valn[25] = column_real[vauxn_idx9]; + chan_valn[26] = column_real[vauxn_idx10]; + chan_valn[27] = column_real[vauxn_idx11]; + chan_valn[28] = column_real[vauxn_idx12]; + chan_valn[29] = column_real[vauxn_idx13]; + chan_valn[30] = column_real[vauxn_idx14]; + chan_valn[31] = column_real[vauxn_idx15]; + + + // identify columns + if (time_index != -1) begin + + prev_time_out = time_out; + time_out = $bitstoreal(column_real[time_index]); + + if (prev_time_out > time_out) begin + + $display("Analog Data File Error : Time value %f is invalid in the input file for SYSMON instance %m. Time value should increase.", time_out); + infile_format; + end + + end + else begin + + $display("Analog Data File Error : No TIME label is found in the analog data file for SYSMON instance %m."); + infile_format; + $finish; + end + + # ((time_out - prev_time_out) * 1000); + + for (p = 0; p < 32; p = p + 1) begin + // assign to real before minus - to work around a bug in modelsim + chan_val_tmp[p] = chan_val[p]; + chan_valn_tmp[p] = chan_valn[p]; + analog_in_tmp = $bitstoreal(chan_val[p]) - $bitstoreal(chan_valn[p]); + analog_in_diff[p] = $realtobits(analog_in_tmp); + analog_in_uni[p] = chan_val[p]; + + end + + end // if (char_1 == "0" | char_1 == "9") + // Ignore any non-comment, label + else begin + + fs = $ungetc (char_2, fd); + fs = $ungetc (char_1, fd); + fs = $fgets (one_line, fd); + + end + + end + end // while (end_file == 0) + end // if (sim_file_flag == 0) + end // initial begin + + task infile_format; + begin + $display("\n***** SYSMON Simulation Analog Data File Format *****\n"); + $display("NAME: design.txt or user file name passed with parameter/generic SIM_MONITOR_FILE\n"); + $display("FORMAT: First line is header line. Valid column name are: TIME TEMP VCCINT VCCAUX VP VN VAUXP[0] VAUXN[0] ..... \n"); + $display("TIME must be in first column.\n"); + $display("Time value need to be integer in ns scale.\n"); + $display("Analog value need to be real and must contain a decimal point '.' , e.g. 0.0, 3.0\n"); + $display("Each line including header line can not have extra space after the last character/digit.\n"); + $display("Each data line must have same number of columns as the header line.\n"); + $display("Comment line start with -- or //\n"); + $display("Example:\n"); + $display("TIME TEMP VCCINT VP VN VAUXP[0] VAUXN[0]\n"); + $display("000 125.6 1.0 0.7 0.4 0.3 0.6\n"); + $display("200 25.6 0.8 0.5 0.3 0.8 0.2\n"); + end + endtask //task infile_format + + function [12*8:1] to_upcase_label; + input [12*8:1] in_label; + reg [8:1] tmp_reg; + begin + + for (i=0; i< 12; i=i+1) begin + + for (j=1; j<=8; j= j+1) + tmp_reg[j] = in_label[i*8+j]; + + if ((tmp_reg >96) && (tmp_reg<123)) + tmp_reg = tmp_reg -32; + + for (j=1; j<=8; j= j+1) + to_upcase_label[i*8+j] = tmp_reg[j]; + + end + end + endfunction + +// end read input file + +// Check if (Vp+Vn)/2 = 0.5 +/- 100 mv, unipolar only + always @( posedge busy_r ) + begin + if (acq_b_u == 0 && rst_in == 0 && ((acq_chan == 3) || (acq_chan >= 16 && acq_chan <= 31))) begin + chan_val_p_tmp = $bitstoreal(chan_val_tmp[acq_chan]); + chan_val_n_tmp = $bitstoreal(chan_valn_tmp[acq_chan]); + + if ( chan_val_n_tmp > chan_val_p_tmp) + $display("Input File Warning: The N input for external channel %x must be smaller than P input when in unipolar mode (P=%0.2f N=%0.2f) for SYSMON instance %m at %.3f ns.", acq_chan, chan_val_p_tmp, chan_val_n_tmp, $time/1000.0); + if ( chan_val_n_tmp > 0.5 || chan_val_n_tmp < 0.0) + $display("Input File Warning: The range of N input for external channel %x should be between 0V to 0.5V when in unipolar mode (N=%0.2f) for SYSMON instance %m at %.3f ns.", acq_chan, chan_val_n_tmp, $time/1000.0); + end + end + + reg seq_reset_busy_out = 0; + wire rst_in_out; + + always @(posedge dclk_in or posedge rst_in_out) + if (rst_in_out) begin + busy_rst <= 1; + rst_lock <= 1; + rst_lock_early <= 1; + busy_rst_cnt <= 0; + end + else begin + if (rst_lock == 1) begin + if (busy_rst_cnt < 29) begin + busy_rst_cnt <= busy_rst_cnt + 1; + if ( busy_rst_cnt == 26) + rst_lock_early <= 0; + end + else begin + busy_rst <= 0; + rst_lock = 0; + end + end + end + + initial begin + busy_out = 0; + busy_rst = 0; + busy_conv = 0; + busy_seq_rst = 0; + busy_out_tmp = 0; + end + + always @(busy_rst or busy_conv or rst_lock) + if (rst_lock) + busy_out = busy_rst; + else + busy_out = busy_conv; + + always @(posedge dclk_in or posedge rst_in) + if (rst_in) begin + busy_conv <= 0; + cal_chan_update <= 0; + end + else begin + if (seq_reset_flag == 1 && curr_clkdiv_sel <= 8'h03) begin + busy_conv <= busy_seq_rst; + end + else if (busy_sync_fall) + busy_conv <= 0; + else if (busy_sync_rise) + busy_conv <= 1; + + if (conv_count == 21 && curr_chan == 5'b01000) + cal_chan_update <= 1; + else + cal_chan_update <= 0; + end + + always @(posedge dclk_in or rst_lock) + if (rst_lock) begin + busy_sync1 <= 0; + busy_sync2 <= 0; + end + else begin + busy_sync1 <= busy_r; + busy_sync2 <= busy_sync1; + end + + assign busy_sync_fall = (busy_r == 0 && busy_sync1 == 1) ? 1 : 0; + assign busy_sync_rise = (busy_sync1 == 1 && busy_sync2 == 0 ) ? 1 : 0; + + always @(negedge busy_out or posedge busy_r) + if (seq_reset_flag == 1 && seq1_0 == 2'b00 && curr_clkdiv_sel <= 8'h03) begin + @(posedge dclk_in); + @(posedge dclk_in); + @(posedge dclk_in); + @(posedge dclk_in); + @(posedge dclk_in) + busy_seq_rst <= 1; + end + else if (seq_reset_flag == 1 && seq1_0 != 2'b00 && curr_clkdiv_sel <= 8'h03) begin + @(posedge dclk_in); + @(posedge dclk_in); + @(posedge dclk_in); + @(posedge dclk_in); + @(posedge dclk_in) + @(posedge dclk_in) + @(posedge dclk_in) + busy_seq_rst <= 1; + end + else + busy_seq_rst <= 0; + + + always @(negedge busy_out or posedge busy_out or posedge rst_in_out or posedge cal_chan_update) + if (rst_in_out) + channel_out <= 5'b0; + else if (busy_out ==1 && (cal_chan_update == 1) ) + channel_out <= 5'b01000; + else if (busy_out == 0) begin + channel_out <= curr_chan; + curr_chan_lat <= curr_chan; + end + + +// START double latch rst_in + + reg rst_in1_tmp5; + reg rst_in2_tmp5; + reg rst_in1_tmp6; + reg rst_in2_tmp6; + reg int_rst; + wire rst_input_t; + wire rst_in2; + + initial begin + int_rst = 1; + @(posedge dclk_in) + @(posedge dclk_in) + int_rst <= 0; + end + + initial begin + rst_in1_tmp5 = 0; + rst_in2_tmp5 = 0; + rst_in1_tmp6 = 0; + rst_in2_tmp6 = 0; + end + + assign #1 rst_input_t = rst_input | int_rst | soft_reset; + + always@(posedge dclk_in or posedge rst_input_t) + if (sim_device_int == 0) begin + if (rst_input_t) begin + rst_in2_tmp5 <= 1; + rst_in1_tmp5 <= 1; + end + else begin + rst_in2_tmp5 <= rst_in1_tmp5; + rst_in1_tmp5 <= rst_input_t; + end + end + + + always@(posedge adcclk or posedge rst_input_t) + if (sim_device_int == 1) begin + if (rst_input_t) begin + rst_in2_tmp6 <= 1; + rst_in1_tmp6 <= 1; + end + else begin + rst_in2_tmp6 <= rst_in1_tmp6; + rst_in1_tmp6 <= rst_input_t; + end + end + + + assign rst_in2 = (sim_device_int == 1) ? rst_in2_tmp6 : rst_in2_tmp5; + assign #10 rst_in_not_seq = rst_in2; + assign rst_in = rst_in_not_seq | seq_reset_dly; + assign rst_in_out = rst_in_not_seq | seq_reset_busy_out; + + + always @(posedge seq_reset) begin + @(posedge dclk_in); + @(posedge dclk_in) + seq_reset_dly <= 1; + @(posedge dclk_in); + @(negedge dclk_in) + seq_reset_busy_out <= 1; + @(posedge dclk_in) + @(posedge dclk_in) + @(posedge dclk_in) begin + seq_reset_dly <= 0; + seq_reset_busy_out <= 0; + end + end + + always @(posedge seq_reset_dly or posedge busy_r) + if (seq_reset_dly) + seq_reset_flag <= 1; + else + seq_reset_flag <= 0; + + always @(posedge seq_reset_flag or posedge busy_out) + if (seq_reset_flag) + seq_reset_flag_dly <= 1; + else + seq_reset_flag_dly <= 0; + + always @(posedge busy_out ) + if (seq_reset_flag_dly == 1 && acq_chan == 5'b01000 && seq1_0 == 2'b00) + first_cal_chan <= 1; + else + first_cal_chan <= 0; + + + + initial begin + conv_time = 18; //minus 3 + conv_time_cal_1 = 70; + conv_time_cal = 70; + sysclk = 0; + adcclk_tmp = 0; + seq_count = 1; + eos_en = 0; + eos_tmp_en = 0; + clk_count = -1; + acq_acqsel = 0; + acq_e_c_tmp6 = 0; + acq_e_c_tmp5 = 0; + eoc_en = 0; + eoc_en_delay = 0; + rst_lock = 0; + rst_lock_early = 0; + alarm_update = 0; + drp_update = 0; + cal_chan_update = 0; + adc_state = CONV_STATE; + scon_tmp = 5'b0; + busy_r = 0; + busy_r_rst = 0; + busy_sync1 = 0; + busy_sync2 = 0; + conv_count = 0; + conv_end = 0; + seq_status_avg = 0; + for (i = 0; i <=20; i = i +1) + begin + conv_avg_count[i] = 0; + conv_acc[j] = 0; + end + adc_s1_flag = 0; + for (k = 0; k <= 31; k = k + 1) + data_reg[k] = 16'b0; + + seq_count_en = 0; + eos_out_tmp = 0; + eoc_out_tmp = 0; + eos_out_tmp1 = 0; + eoc_out_tmp1 = 0; + eos_out = 0; + eoc_out = 0; + curr_avg_set = 2'b0; + curr_e_c = 0; + curr_b_u = 0; + curr_acq = 0; + curr_seq1_0 = 2'b0; + curr_seq1_0_lat = 2'b0; + seq1_0 = 2'b0; + daddr_in_lat = 7'b0; + data_reg[32] = 16'b0; + data_reg[33] = 16'b0; + data_reg[34] = 16'b0; + data_reg[35] = 16'b0; + data_reg[36] = 16'b1111111111111111; + data_reg[37] = 16'b1111111111111111; + data_reg[38] = 16'b1111111111111111; + data_reg[39] = 16'b1111111111111111; + ot_out_reg = 0; + ot_out = 0; + alarm_out_reg = 3'b0; + alarm_out = 3'b0; + curr_chan = 5'b0; + curr_chan_lat = 5'b0; + busy_out = 0; + busy_out_tmp = 0; + curr_seq = 16'b0; + seq_num = 0; + seq_reset_flag_dly = 0; + seq_reset_flag = 0; + seq_reset_dly = 0; + ot_en = 1; + alarm_en = 3'b111; + do_out_rdtmp = 16'b0; + acq_chan = 5'b0; + acq_b_u = 0; + conv_result_int = 0; + conv_result = 0; + conv_result_reg = 0; + end + + +// state machine + always @(posedge adcclk or posedge rst_in or sim_file_flag) begin + if (sim_file_flag == 1'b1) + adc_state <= INIT_STATE; + else if (rst_in == 1'b1 || rst_lock_early == 1) + adc_state <= INIT_STATE; + else if (rst_in == 1'b0) + adc_state <= next_state; + end + + always @(adc_state or eos_en or conv_start or conv_end or curr_seq1_0_lat) begin + + case (adc_state) + INIT_STATE : next_state = ACQ_STATE; + + ACQ_STATE : if (conv_start) + next_state = CONV_STATE; + else + next_state = ACQ_STATE; + + CONV_STATE : if (conv_end) + next_state = END_STATE; + else + next_state = CONV_STATE; + + END_STATE : if (curr_seq1_0_lat == 2'b01) begin + if (eos_en) + next_state = SINGLE_SEQ_STATE; + else + next_state = ACQ_STATE; + end + else + next_state = ACQ_STATE; + + SINGLE_SEQ_STATE : next_state = INIT_STATE; + + default : next_state = INIT_STATE; + + endcase // case(adc_state) + + end + +// end state machine + + +// DRPORT - SRAM + + initial begin + drdy_out = 0; + drdy_out_tmp1 = 0; + drdy_out_tmp2 = 0; + drdy_out_tmp3 = 0; + drdy_out_tmp4 = 0; + en_data_flag = 0; + do_out = 16'b0; + seq_reset = 0; + cfg_reg1_init = INIT_41; + seq_en = 0; + seq_en_dly = 0; + seq_en <= #20 (cfg_reg1_init[13:12] != 2'b11 ) ? 1 : 0; + seq_en <= #150 0; + end + + always @(posedge drdy_out_tmp3 or posedge gsr_in) + if (gsr_in == 1) + drdy_out <= 0; + else begin + @(posedge dclk_in) + drdy_out <= 1; + @(posedge dclk_in) + drdy_out <= 0; + end + + always @(posedge dclk_in or posedge gsr_in) + + if (gsr_in == 1) begin + drdy_out <= 0; + daddr_in_lat <= 7'b0; + do_out <= 16'b0; + end + else begin + if (den_in == 1) begin + if (drdy_out_tmp1 == 0) begin + drdy_out_tmp1 <= 1'b1; + en_data_flag = 1; + daddr_in_lat <= daddr_in; + end + else begin + if (daddr_in != daddr_in_lat) + $display("Warning : input pin DEN on SYSMON instance %m at time %.3f ns can not continue set to high. Need wait DRDY high and then set DEN high again.", $time/1000.0); + end + end + else + drdy_out_tmp1 <= 0; + + drdy_out_tmp2 <= drdy_out_tmp1; + drdy_out_tmp3 <= drdy_out_tmp2; + drdy_out_tmp4 <= drdy_out_tmp3; + + if (drdy_out_tmp1 == 1) + en_data_flag = 0; + + if (drdy_out_tmp3 == 1) + do_out <= do_out_rdtmp; + + if (sim_device_int == 1) begin + if (den_in == 1 && (daddr_in >7'h58 || (daddr_in >= 7'h27 && daddr_in < 7'h3F))) + $display("Invalid Input Warning : The DADDR %x to SYSMON instance %m at time %.3f ns is accessing an undefined location. The data in this location is invalid.", daddr_in, $time/1000.0); + end + else begin + if (den_in == 1 && (daddr_in >7'h58 || (daddr_in >= 7'h0d && daddr_in <= 7'h0f) + || (daddr_in >= 7'h27 && daddr_in <= 7'h3F))) + $display("Invalid Input Warning : The DADDR %x to SYSMON instance %m at time %.3f ns is accessing an undefined location. The data in this location is invalid.", daddr_in, $time/1000.0); + end + +// write all available daddr addresses + + if (dwe_in == 1'b1 && en_data_flag == 1) begin + + dr_sram[daddr_in] <= di_in; + + if (sim_device_int == 1) begin + if (daddr_in == 7'h03) + soft_reset <= 1; + + if ( daddr_in == 7'h53) begin + if (di_in[3:0] == 4'b0011) + ot_limit_reg[15:4] <= di_in[15:4]; + else + ot_limit_reg <= 16'hCA00; + end + end + + if (sim_device_int == 1) begin + if ( daddr_in == 7'h42 && (di_in[2:0] !=3'b000)) + $display(" Invalid Input Error : The DI bit[2:0] %x at DADDR %x on SYSMON instance %m at %.3f ns is invalid. These must be set to 000.", di_in[2:0], daddr_in, $time/1000.0); + end + else begin + if ( daddr_in == 7'h42 && (di_in[1:0] !=2'b00)) + $display(" Invalid Input Error : The DI bit[1:0] %x at DADDR %x on SYSMON instance %m at %.3f ns is invalid. These must be set to 00.", di_in[1:0], daddr_in, $time/1000.0); + end + + if (sim_device_int == 0) begin + if (daddr_in == 7'h42 && (di_in[15:8] < 8'b00001000)) begin + $display(" Invalid Input Error : The DI bit[15:8] %x at DADDR %x on SYSMON instance %m at %.3f ns is invalid. Bit[15:8] of Control Register 42h is the ADC Clock divider and must be equal or greater than 8. ", di_in[15:8], daddr_in, $time/1000.0); + $finish; + end + end + + if ( daddr_in >= 7'h43 && daddr_in <= 7'h47 && (di_in[15:0] != 16'h0000)) + $display(" Invalid Input Error : The DI value %x at DADDR %x of SYSMON instance %m at %.3f ns is invalid. These must be set to 0000h.", di_in, daddr_in, $time/1000.0); + + if ((daddr_in == 7'h40) && (di_in[4:0] == 5'b00110 || di_in[4:0] == 5'b00111 + || (di_in[4:0] >= 5'b01010 && di_in[4:0] <= 5'b01111))) + $display("Invalid Input Warning : The DI bit4:0] at address DADDR %x to SYSMON instance %m at %.3f ns is %h, which is invalid analog channel.", daddr_in, $time/1000.0, di_in[4:0]); + + if (daddr_in == 7'h40) begin + if ((cfg_reg1[13:12]==2'b11) && (di_in[8]==1) && (di_in[4:0] != 5'b00011) && (di_in[4:0] < 5'b10000)) + $display(" Invalid Input warning : The DI value is %x at DADDR %x on SYSMON instance %m at %.3f ns. Bit[8] of DI must be set to 0. Long acquistion mode is only allowed for external channels", di_in, daddr_in, $time/1000.0); + + if ((cfg_reg1[13:12]==2'b11) && (di_in[9]==1) && (di_in[4:0] != 5'b00011) && (di_in[4:0] < 5'b10000)) + $display(" Invalid Input warning : The DI value is %x at DADDR %x on SYSMON instance %m at %.3f ns. Bit[9] of DI must be set to 0. Event mode timing can only be used with external channels", di_in, daddr_in, $time/1000.0); + + if ((cfg_reg1[13:12]==2'b11) && (di_in[13:12]!=2'b00) && (seq_chan_reg1 != 16'h0000) && (seq_chan_reg2 != 16'h0000)) + $display(" Invalid Input warning : The Control Regiter 48h and 49h are %x and %x on SYSMON instance %m at %.3f ns. Those registers should be set to 0000h in single channel mode and averaging enabled.", seq_chan_reg1, seq_chan_reg2, $time/1000.0); + + end + + if (daddr_in == 7'h41 && en_data_flag == 1) begin + if ((di_in[13:12]==2'b11) && (cfg_reg0[8]==1) && (cfg_reg0[4:0] != 5'b00011) && (cfg_reg0[4:0] < 5'b10000)) + $display(" Invalid Input warning : The Control Regiter 40h value is %x on SYSMON instance %m at %.3f ns. Bit[8] of Control Regiter 40h must be set to 0. Long acquistion mode is only allowed for external channels", cfg_reg0, $time/1000.0); + + if ((di_in[13:12]==2'b11) && (cfg_reg0[9]==1) && (cfg_reg0[4:0] != 5'b00011) && (cfg_reg0[4:0] < 5'b10000)) + $display(" Invalid Input warning : The Control Regiter 40h value is %x on SYSMON instance %m at %.3f ns. Bit[9] of Control Regiter 40h must be set to 0. Event mode timing can only be used with external channels", cfg_reg0, $time/1000.0); + + if ((di_in[13:12]!=2'b11) && (seq_acq_reg1[10:0]!=11'b0) && (seq_acq_reg1[15:12]!=4'b0)) + $display(" Invalid Input warning : The Control Regiter 4Eh value is %x on SYSMON instance %m at %.3f ns. Bit[15:12] and bit[10:0] of this register must be set to 0. Long acquistion mode is only allowed for external channels", seq_acq_reg1, $time/1000.0); + + if ((di_in[13:12]==2'b11) && (cfg_reg0[13:12]!=2'b00) && (seq_chan_reg1 != 16'h0000) && (seq_chan_reg2 != 16'h0000)) + $display(" Invalid Input warning : The Control Regiter 48h and 49h are %x and %x on SYSMON instance %m at %.3f ns. Those registers should be set to 0000h in single channel mode and averaging enabled.", seq_chan_reg1, seq_chan_reg2, $time/1000.0); + + end + + if (daddr_in == 7'h41 && en_data_flag == 1) begin + if (den_in == 1'b1 && dwe_in == 1'b1) begin + if (di_in[13:12] != cfg_reg1[13:12]) + seq_reset <= 1'b1; + else + seq_reset <= 1'b0; + + if (di_in[13:12] != 2'b11 ) + seq_en <= 1'b1; + else + seq_en <= 1'b0; + end + else begin + seq_reset <= 1'b0; + seq_en <= 1'b0; + end + end +// else begin +// seq_reset <= 0; +// seq_en <= 0; +// end // if (daddr_in == 7'h41) + end // dwe ==1 + + if (seq_en == 1) + seq_en <= 1'b0; + if (seq_reset == 1) + seq_reset <= 1'b0; + if (soft_reset == 1) + soft_reset <= 0; + + end // if (gsr == 1) + + +// DO bus data out + + + assign tmp_dr_sram_out = ( daddr_in_lat >= 7'h40 && daddr_in_lat <= 7'h57) ? + dr_sram[daddr_in_lat] : 16'b0; + +// assign status_reg = {12'b0, ot_out, alarm_out[2:0]}; + assign status_reg = {12'b0, ot_out, 3'b000}; + + assign tmp_data_reg_out = (daddr_in_lat >= 7'h00 && daddr_in_lat <= 7'h26) ? + data_reg[daddr_in_lat] : 16'b0; + + always @( daddr_in_lat or tmp_data_reg_out or tmp_dr_sram_out or status_reg ) begin + if ((daddr_in_lat >7'h58 || (daddr_in_lat>= 7'h0d && daddr_in_lat <= 7'h0f) + || (daddr_in_lat >= 7'h27 && daddr_in_lat < 7'h3F))) begin + do_out_rdtmp = 16'bx; + end + + if (daddr_in_lat == 7'h3F) begin + if (sim_device_int == 1) + do_out_rdtmp = status_reg; + else + do_out_rdtmp = 16'bx; + end + + if ((daddr_in_lat >= 7'h00 && daddr_in_lat <= 7'h0C) || + (daddr_in_lat >= 7'h10 && daddr_in_lat <= 7'h26)) + do_out_rdtmp = tmp_data_reg_out; + else if (daddr_in_lat >= 7'h40 && daddr_in_lat <= 7'h57) + do_out_rdtmp = tmp_dr_sram_out; + end + +// end DRP RAM + + + assign cfg_reg0 = dr_sram[7'h40]; + assign cfg_reg1 = dr_sram[7'h41]; + assign cfg_reg2 = dr_sram[7'h42]; + assign seq_chan_reg1 = dr_sram[7'h48]; + assign seq_chan_reg2 = dr_sram[7'h49]; + assign seq_avg_reg1 = dr_sram[7'h4A]; + assign seq_avg_reg2 = dr_sram[7'h4B]; + assign seq_du_reg1 = dr_sram[7'h4C]; + assign seq_du_reg2 = dr_sram[7'h4D]; + assign seq_acq_reg1 = dr_sram[7'h4E]; + assign seq_acq_reg2 = dr_sram[7'h4F]; + + always @(cfg_reg1) + seq1_0 = cfg_reg1[13:12]; + + always @(posedge drp_update or posedge rst_in) + begin + if (rst_in) begin + @(posedge dclk_in) + @(posedge dclk_in) + seq_bits = seq1_0; + end + else + seq_bits = curr_seq1_0; + + if (seq_bits == 2'b00) begin + alarm_en <= 3'b000; + ot_en <= 1; + end + else begin + ot_en <= ~cfg_reg1[0]; + alarm_en <= ~cfg_reg1[3:1]; + end + end + +// end DRPORT - sram + +// Clock divider, generate and adcclk + + always @(posedge dclk_in) + sysclk <= ~sysclk; + + always @(posedge dclk_in) + if (curr_clkdiv_sel > 8'b00000010 ) begin + if (clk_count >= curr_clkdiv_sel - 1) + clk_count = 0; + else + clk_count = clk_count + 1; + + if (clk_count > (curr_clkdiv_sel/2) - 1) + adcclk_tmp <= 1; + else + adcclk_tmp <= 0; + end + else + adcclk_tmp <= ~adcclk_tmp; + + assign curr_clkdiv_sel = cfg_reg2[15:8]; + assign adcclk_div1 = (curr_clkdiv_sel > 8'b00000010) ? 0 : 1; + assign adcclk = (adcclk_div1) ? ~sysclk : adcclk_tmp; + +// end clock divider + +// latch configuration registers + wire [15:0] cfg_reg0_seq, cfg_reg0_adc; + reg [15:0] cfg_reg0_seq_tmp5, cfg_reg0_adc_tmp5; + reg [15:0] cfg_reg0_seq_tmp6, cfg_reg0_adc_tmp6; + reg [1:0] acq_avg; + + always @( seq1_0 or adc_s1_flag or curr_seq or cfg_reg0_adc or rst_in) begin + if ((seq1_0 == 2'b01 && adc_s1_flag == 0) || seq1_0 == 2'b10) begin + acq_acqsel = curr_seq[8]; + end + else if (seq1_0 == 2'b11) begin + acq_acqsel = cfg_reg0_adc [8]; + end + else begin +// acq_e_c = 0; + acq_acqsel = 0; + end + + if (rst_in == 0) begin + if (seq1_0 != 2'b11 && adc_s1_flag == 0) begin + acq_avg = curr_seq[13:12]; + acq_chan = curr_seq[4:0]; + acq_b_u = curr_seq[10]; + end + else begin + acq_avg = cfg_reg0_adc[13:12]; + acq_chan = cfg_reg0_adc[4:0]; + acq_b_u = cfg_reg0_adc[10]; + end + end + end + + reg single_chan_conv_end; + reg [3:0] conv_end_reg_read; + reg busy_reg_read; + reg first_after_reset_tmp5; + reg first_after_reset_tmp6; + + always@(posedge adcclk or posedge rst_in) + begin + if(rst_in) conv_end_reg_read <= 4'b0; + else conv_end_reg_read <= {conv_end_reg_read[2:0], single_chan_conv_end | conv_end}; + end + + always@(posedge DCLK or posedge rst_in) + begin + if(rst_in) busy_reg_read <= 1; + else busy_reg_read <= ~conv_end_reg_read[2]; + end + + assign cfg_reg0_adc = (sim_device_int == 1) ? cfg_reg0_adc_tmp6 : cfg_reg0_adc_tmp5; + assign cfg_reg0_seq = (sim_device_int == 1) ? cfg_reg0_seq_tmp6 : cfg_reg0_seq_tmp5; + assign acq_e_c = (sim_device_int == 1) ? acq_e_c_tmp6 : acq_e_c_tmp5; + + always @(negedge busy_reg_read or rst_in) + if (sim_device_int == 0) begin + if(rst_in) begin + cfg_reg0_seq_tmp5 <= 16'b0; + cfg_reg0_adc_tmp5 <= 16'b0; + acq_e_c_tmp5 <= 0; + first_after_reset_tmp5 <= 1; + end + else begin + repeat(3) @(posedge DCLK); + if(first_after_reset_tmp5) begin + first_after_reset_tmp5<=0; + cfg_reg0_adc_tmp5 <= cfg_reg0; + cfg_reg0_seq_tmp5 <= cfg_reg0; + end + else begin + cfg_reg0_adc_tmp5 <= cfg_reg0_seq; + cfg_reg0_seq_tmp5 <= cfg_reg0; + end + acq_e_c_tmp5 <= cfg_reg0[9]; + end + end + + always @(negedge busy_out or rst_in) + if (sim_device_int == 1) begin + if(rst_in) begin + cfg_reg0_seq_tmp6 <= 16'b0; + cfg_reg0_adc_tmp6 <= 16'b0; + acq_e_c_tmp6 <= 0; + first_after_reset_tmp6 <= 1; + end + else begin + repeat(3) @(posedge DCLK); + if(first_after_reset_tmp6) begin + first_after_reset_tmp6<=0; + cfg_reg0_adc_tmp6 <= cfg_reg0; + cfg_reg0_seq_tmp6 <= cfg_reg0; + end + else begin + cfg_reg0_adc_tmp6 <= cfg_reg0_seq; + cfg_reg0_seq_tmp6 <= cfg_reg0; + end + acq_e_c_tmp6 <= cfg_reg0[9]; + end + end + + always @(posedge conv_start or posedge busy_r_rst or posedge rst_in) + if (rst_in ==1) + busy_r <= 0; + else if (conv_start && rst_lock == 0) + busy_r <= 1; + else if (busy_r_rst) + busy_r <= 0; + + always @(negedge busy_out ) + if (adc_s1_flag == 1) + curr_seq1_0 <= 2'b00; + else + curr_seq1_0 <= seq1_0; + + always @(posedge conv_start or posedge rst_in ) begin + if (rst_in == 1) begin + analog_mux_in <= 0.0; + curr_chan <= 5'b0; + end + else begin + if ((acq_chan == 5'b00011) || (acq_chan >= 5'b10000 && acq_chan <= 5'b11111)) + analog_mux_in <= $bitstoreal(analog_in_diff[acq_chan]); + else + analog_mux_in <= $bitstoreal(analog_in_uni[acq_chan]); + + curr_chan <= acq_chan; + curr_seq1_0_lat <= curr_seq1_0; + + + if (acq_chan == 5'b00110 || acq_chan == 5'b00111 || (acq_chan >= 5'b01010 && acq_chan <= 5'b01111)) + $display("Invalid Input Warning : The analog channel %x to SYSMON instance %m at %.3f ns is invalid.", acq_chan, $time/1000.0); + + + if ((seq1_0 == 2'b01 && adc_s1_flag == 0) || seq1_0 == 2'b10 || seq1_0 == 2'b00) begin + + curr_avg_set <= curr_seq[13:12]; + curr_b_u <= curr_seq[10]; + curr_e_c <= 0; + curr_acq <= curr_seq[8]; + end + else begin + curr_avg_set <= acq_avg; + curr_b_u <= acq_b_u; + curr_e_c <= cfg_reg0[9]; + curr_acq <= cfg_reg0[8]; + end + + end // if (rst_in == 0) + + end // always @ (posedge conv_start or posedge rst_in) + + +// end latch configuration registers + +// sequence control + + always @(seq_en ) + seq_en_dly <= #1 seq_en; + + + always @(posedge seq_en_dly) + if (seq1_0 == 2'b01 || seq1_0 == 2'b10) begin + seq_num = 0; + for (si=0; si<= 15; si=si+1) begin + if (seq_chan_reg1[si] ==1) begin + seq_num = seq_num + 1; + seq_mem[seq_num] = si; + end + end + for (si=16; si<= 31; si=si+1) begin + if (seq_chan_reg2[si-16] ==1) begin + seq_num = seq_num + 1; + seq_mem[seq_num] = si; + end + end + end + else if (seq1_0 == 2'b00) begin + seq_num = 4; + seq_mem[1] = 0; + seq_mem[2] = 8; + seq_mem[3] = 9; + seq_mem[4] = 10; + end + + + always @( seq_count or negedge seq_en_dly) begin + seq_curr_i = seq_mem[seq_count]; + curr_seq = 16'b0; + if (seq_curr_i >= 0 && seq_curr_i <= 15) begin + curr_seq [2:0] = seq_curr_i[2:0]; + curr_seq [4:3] = 2'b01; + curr_seq [8] = seq_acq_reg1[seq_curr_i]; + curr_seq [10] = seq_du_reg1[seq_curr_i]; + + if (seq1_0 == 2'b00) + curr_seq [13:12] = 2'b01; + else if (seq_avg_reg1[seq_curr_i] == 1) + curr_seq [13:12] = cfg_reg0[13:12]; + else + curr_seq [13:12] = 2'b00; + + if (seq_curr_i >= 0 && seq_curr_i <=7) + curr_seq [4:3] = 2'b01; + else + curr_seq [4:3] = 2'b00; + end + else if (seq_curr_i >= 16 && seq_curr_i <= 31) begin + curr_seq [4:0] = seq_curr_i; + curr_seq [8] = seq_acq_reg2[seq_curr_i - 16]; + curr_seq [10] = seq_du_reg2[seq_curr_i - 16]; + if (seq_avg_reg2[seq_curr_i - 16] == 1) + curr_seq [13:12] = cfg_reg0[13:12]; + else + curr_seq [13:12] = 2'b00; + end + end + + always @(posedge adcclk or posedge rst_in) + if (rst_in == 1) begin + seq_count <= 1; + eos_en <= 0; + end + else begin + if ((seq_count == seq_num ) && (adc_state == CONV_STATE && next_state == END_STATE) && (curr_seq1_0_lat != 2'b11) && rst_lock == 0) + eos_tmp_en <= 1; + else + eos_tmp_en <= 0; + + if (eos_tmp_en == 1 && seq_status_avg == 0 ) // delay by 1 adcclk + eos_en <= 1; + else + eos_en <= 0; + + + if (eos_tmp_en == 1 || curr_seq1_0_lat == 2'b11 ) + seq_count <= 1; + else if (seq_count_en == 1) begin + if (seq_count >= 32) + seq_count <= 1; + else + seq_count <= seq_count +1; + end + + end // else: !if(rst_in == 1) + +// end sequence control + +// Acquisition + reg first_acq; + reg shorten_acq; + wire busy_out_dly; + + assign #10 busy_out_dly = busy_out; + + always @(adc_state or posedge rst_in or first_acq) + begin + if(rst_in) shorten_acq = 0; + else if(busy_out_dly==0 && adc_state==ACQ_STATE && first_acq==1) + shorten_acq = 1; + else + shorten_acq = 0; + end + + + always @(posedge adcclk or posedge rst_in) + if (rst_in == 1) begin + acq_count <= 1; + first_acq <=1; + end + else begin + if (adc_state == ACQ_STATE && rst_lock == 0 && (acq_e_c==0)) begin + first_acq <= 0; + + if (acq_acqsel == 1) begin + if (acq_count <= 11) + acq_count <= acq_count + 1 + shorten_acq; + end + else begin + if (acq_count <= 4) + acq_count <= acq_count + 1 + shorten_acq; + end // else: !if(acq_acqsel == 1) + + if (next_state == CONV_STATE) + if ((acq_acqsel == 1 && acq_count < 10) || (acq_acqsel == 0 && acq_count < 4)) + $display ("Warning: Acquisition time is not long enough for SYSMON instance %m at time %t.", $time); + end // if (adc_state == ACQ_STATE) + else + acq_count <= (first_acq) ? 1 : 0; + + end // if (rst_in == 0) + +// continuous mode + reg conv_start_cont; + wire reset_conv_start; + wire conv_start_sel; + + always @(adc_state or acq_acqsel or acq_count) + if (adc_state == ACQ_STATE) begin + if (rst_lock == 0) begin + if ( ((seq_reset_flag == 0 || (seq_reset_flag == 1 && curr_clkdiv_sel > 8'h03)) + && ( (acq_acqsel == 1 && acq_count > 10) || (acq_acqsel == 0 && acq_count > 4)) ) ) + conv_start_cont = 1; + else + conv_start_cont = 0; + end + end // if (adc_state == ACQ_STATE) + else + conv_start_cont = 0; + + assign conv_start_sel = (acq_e_c) ? convst_in : conv_start_cont; + + assign reset_conv_start = rst_in | (conv_count==2); + + always@(posedge conv_start_sel or posedge reset_conv_start) + begin + if(reset_conv_start) conv_start <= 0; + else conv_start <= 1; + end + + +// end acquisition + +// Conversion + always @(adc_state or next_state or curr_chan or analog_mux_in or curr_b_u) begin + + if ((adc_state == CONV_STATE && next_state == END_STATE) || adc_state == END_STATE) begin + if (curr_chan == 0) begin // temperature conversion + adc_temp_result = (analog_mux_in + 273.0) * 0.001984226*65536; + if (adc_temp_result >= 65535.0) + conv_result_int = 65535; + else if (adc_temp_result < 0.0) + conv_result_int = 0; + else begin + conv_result_int = $rtoi(adc_temp_result); + if (adc_temp_result - conv_result_int > 0.9999) + conv_result_int = conv_result_int + 1; + end + end + else if (curr_chan == 1 || curr_chan == 2) begin // internal power conversion + adc_intpwr_result = analog_mux_in * 65536.0 / 3.0; + if (adc_intpwr_result >= 65535.0) + conv_result_int = 65535; + else if (adc_intpwr_result < 0.0) + conv_result_int = 0; + else begin + conv_result_int = $rtoi(adc_intpwr_result); + if (adc_intpwr_result - conv_result_int > 0.9999) + conv_result_int = conv_result_int + 1; + end + end + else if (curr_chan == 3 || (curr_chan >=16 && curr_chan <= 31)) begin + + adc_ext_result = (analog_mux_in) * 65536.0; + if (curr_b_u == 1) begin + if (adc_ext_result > 32767.0) + conv_result_int = 32767; + else if (adc_ext_result < -32768.0) + conv_result_int = -32768; + else begin + conv_result_int = $rtoi(adc_ext_result); + if (adc_ext_result - conv_result_int > 0.9999) + conv_result_int = conv_result_int + 1; + end + end + else begin + if (adc_ext_result > 65535.0) + conv_result_int = 65535; + else if (adc_ext_result < 0.0) + conv_result_int = 0; + else begin + conv_result_int = $rtoi(adc_ext_result); + if (adc_ext_result - conv_result_int > 0.9999) + conv_result_int = conv_result_int + 1; + end + end + end + else begin + conv_result_int = 0; + end + end + + conv_result = conv_result_int; + + end // always @ ( adc_state or curr_chan or analog_mux_in, curr_b_u) + + reg busy_r_rst_done; + + always @(posedge adcclk or posedge rst_in) + if (rst_in == 1) begin + conv_count <= 6; + conv_end <= 0; + seq_status_avg <= 0; + busy_r_rst <= 0; + busy_r_rst_done <= 0; + for (i = 0; i <=31; i = i +1) + conv_avg_count[i] <= 0; // array of integer + single_chan_conv_end <= 0; + end + else begin + if(adc_state == ACQ_STATE) + begin + if(busy_r_rst_done == 0) busy_r_rst <= 1; + else busy_r_rst <= 0; + busy_r_rst_done <= 1; + end + + if (adc_state == ACQ_STATE && conv_start == 1) begin + conv_count <= 0; + conv_end <= 0; + end + else if (adc_state == CONV_STATE ) begin + busy_r_rst_done <= 0; + + conv_count = conv_count + 1; + + if ((curr_chan != 5'b01000 ) && (conv_count == conv_time ) || + (curr_chan == 5'b01000 ) && (conv_count == conv_time_cal_1 ) && (first_cal_chan==1) + || (curr_chan == 5'b01000 ) && (conv_count == conv_time_cal) && (first_cal_chan == 0)) + conv_end <= 1; + else + conv_end <= 0; + end + else begin + conv_end <= 0; + conv_count <= 0; + end + // jmcgrath - to model the behaviour correctly when a cal chanel is being converted + // an signal to signify the conversion has ended must be produced - this is for single channel mode + single_chan_conv_end <= 0; + if( (conv_count == conv_time) || (conv_count == 44)) + single_chan_conv_end <= 1; + + + if (adc_state == CONV_STATE && next_state == END_STATE && rst_lock == 0) begin + case (curr_avg_set) + 2'b00 : begin + eoc_en <= 1; + conv_avg_count[curr_chan] <= 0; + end + 2'b01 : begin + if (conv_avg_count[curr_chan] == 15) begin + eoc_en <= 1; + conv_avg_count[curr_chan] <= 0; + seq_status_avg <= seq_status_avg - 1; + end + else begin + eoc_en <= 0; + if (conv_avg_count[curr_chan] == 0) + seq_status_avg <= seq_status_avg + 1; + + conv_avg_count[curr_chan] <= conv_avg_count[curr_chan] + 1; + end + end + 2'b10 : begin + if (conv_avg_count[curr_chan] == 63) begin + eoc_en <= 1; + conv_avg_count[curr_chan] <= 0; + seq_status_avg <= seq_status_avg - 1; + end + else begin + eoc_en <= 0; + if (conv_avg_count[curr_chan] == 0) + seq_status_avg <= seq_status_avg + 1; + + conv_avg_count[curr_chan] <= conv_avg_count[curr_chan] + 1; + end + end + 2'b11 : begin + if (conv_avg_count[curr_chan] == 255) begin + eoc_en <= 1; + conv_avg_count[curr_chan] <= 0; + seq_status_avg <= seq_status_avg - 1; + end + else begin + eoc_en <= 0; + if (conv_avg_count[curr_chan] == 0) + seq_status_avg <= seq_status_avg + 1; + + conv_avg_count[curr_chan] <= conv_avg_count[curr_chan] + 1; + end + end + default : eoc_en <= 0; + endcase // case(curr_avg_set) + end // if (adc_state == CONV_STATE && next_state == END_STATE) + else + eoc_en <= 0; + + if (adc_state == END_STATE) + conv_result_reg <= conv_result; + + end // if (rst_in == 0) + +// end conversion + + +// average + always @(adc_state or conv_acc[curr_chan]) + if (adc_state == END_STATE ) + // no signed or unsigned differences for bit vector conv_acc_vec + conv_acc_vec = conv_acc[curr_chan]; + else + conv_acc_vec = 24'b00000000000000000000; + + + always @(posedge adcclk or posedge rst_in) + if (rst_in == 1) begin + for (j = 0; j <= 31; j = j + 1) + conv_acc[j] <= 0; + conv_acc_result <= 16'b0000000000000000; + end + else begin + if (adc_state == CONV_STATE && next_state == END_STATE) begin + if (curr_avg_set != 2'b00 && rst_lock != 1) + conv_acc[curr_chan] <= conv_acc[curr_chan] + conv_result_int; + else + conv_acc[curr_chan] <= 0; + end + else if (eoc_en == 1) begin + case (curr_avg_set) + 2'b00 : conv_acc_result <= 16'b0000000000000000; + 2'b01 : conv_acc_result <= conv_acc_vec[19:4]; + 2'b10 : conv_acc_result <= conv_acc_vec[21:6]; + 2'b11 : conv_acc_result <= conv_acc_vec[23:8]; + endcase // case(curr_avg_set) + + conv_acc[curr_chan] <= 0; + + end // if (eoc_en == 1) + end // if (rst_in == 0) + +// end average + +// single sequence + always @(posedge adcclk or posedge rst_in) + if (rst_in == 1) + adc_s1_flag <= 0; + else + if (adc_state == SINGLE_SEQ_STATE) + adc_s1_flag <= 1; + +// end state + always @(posedge adcclk or posedge rst_in) + if (rst_in == 1) begin + seq_count_en <= 0; + eos_out_tmp <= 0; + eoc_out_tmp <= 0; + end + else begin + if ((adc_state == CONV_STATE && next_state == END_STATE) && (curr_seq1_0_lat != 2'b11) && (rst_lock == 0)) + seq_count_en <= 1; + else + seq_count_en <= 0; + + if (rst_lock == 0) begin + eos_out_tmp <= eos_en; + eoc_en_delay <= eoc_en; + eoc_out_tmp <= eoc_en_delay; + end + else begin + eos_out_tmp <= 0; + eoc_en_delay <= 0; + eoc_out_tmp <= 0; + end + end + + always @(posedge eoc_out or posedge rst_in_not_seq) + if (rst_in_not_seq == 1) begin + for (k = 32; k <= 39; k = k + 1) + if (k >= 36) + data_reg[k] <= 16'b1111111111111111; + else + data_reg[k] <= 16'b0000000000000000; + end + else + if ( rst_lock == 0) begin + if ((curr_chan >= 0 && curr_chan <= 3) || (curr_chan >= 16 && curr_chan <= 31)) begin + if (curr_avg_set == 2'b00) + data_reg[curr_chan] <= conv_result_reg; + else + data_reg[curr_chan] <= conv_acc_result; + end + if (curr_chan == 4) + data_reg[curr_chan] <= 16'hD555; + if (curr_chan == 5) + data_reg[curr_chan] <= 16'h0000; + + if (curr_chan == 0 || curr_chan == 1 || curr_chan == 2) begin + if (curr_avg_set == 2'b00) begin + if (conv_result_reg > data_reg[32 + curr_chan]) + data_reg[32 + curr_chan] <= conv_result_reg; + if (conv_result_reg < data_reg[36 + curr_chan]) + data_reg[36 + curr_chan] <= conv_result_reg; + end + else begin + if (conv_acc_result > data_reg[32 + curr_chan]) + data_reg[32 + curr_chan] <= conv_acc_result; + if (conv_acc_result < data_reg[36 + curr_chan]) + data_reg[36 + curr_chan] <= conv_acc_result; + end + end + end + + reg [15:0] data_written; + always @(negedge busy_r or posedge rst_in_not_seq) + if (rst_in_not_seq) + data_written <= 16'b0; + else begin + if (curr_avg_set == 2'b00) data_written <= conv_result_reg; + else data_written <= conv_acc_result; + end + + + reg [3:0] op_count=15; + reg busy_out_sync; + wire busy_out_low_edge; + +// eos and eoc + + always @( posedge eoc_out_tmp or posedge eoc_out or posedge rst_in) + if (rst_in ==1) + eoc_out_tmp1 <= 0; + else if ( eoc_out ==1) + eoc_out_tmp1 <= 0; + else if ( eoc_out_tmp == 1) begin + if (curr_chan != 5'b01000) + eoc_out_tmp1 <= 1; + else + eoc_out_tmp1 <= 0; + end + + always @( posedge eos_out_tmp or posedge eos_out or posedge rst_in) + if (rst_in ==1) + eos_out_tmp1 <= 0; + else if ( eos_out ==1) + eos_out_tmp1 <= 0; + else if ( eos_out_tmp == 1) + eos_out_tmp1 <= 1; + + assign busy_out_low_edge = (busy_out==0 && busy_out_sync==1) ? 1 : 0; + + always @( posedge dclk_in or posedge rst_in) + begin + + if (rst_in) begin + op_count <= 15; + busy_out_sync <= 0; + end + + drp_update <= 0; + alarm_update <= 0; + eoc_out <= 0; + eos_out <= 0; + if(rst_in==0) + begin + busy_out_sync <= busy_out; + if(op_count==3) drp_update <= 1; + if(op_count==5 && eoc_out_tmp1==1) alarm_update <=1; + if(op_count==9 ) eoc_out <= eoc_out_tmp1; + if(op_count==9) eos_out <= eos_out_tmp1; + if (busy_out_low_edge==1 ) + op_count <= 0; + else if(op_count < 15) op_count <= op_count +1; + end + end + +// end eos and eoc + +// alarm + + always @( posedge alarm_update or posedge rst_in_not_seq ) + if (rst_in_not_seq == 1) begin + ot_out_reg <= 0; + alarm_out_reg <= 3'b0; + end + else + if (rst_lock == 0) begin + + if (curr_chan_lat == 0) begin + if (data_written >= ot_limit_reg) + ot_out_reg <= 1; + else if (((data_written < dr_sram[7'h57]) && curr_seq1_0_lat != 2'b00) || + (curr_seq1_0_lat ==2'b00 && (data_written < ot_sf_limit_low_reg))) + ot_out_reg <= 0; + + if (data_written > dr_sram[7'h50]) + alarm_out_reg[0] <= 1; + else if (data_written < dr_sram[7'h54]) + alarm_out_reg[0] <= 0; + end + + if (curr_chan_lat == 1) begin + if (data_written > dr_sram[7'h51] || data_written < dr_sram[7'h55]) + alarm_out_reg[1] <= 1; + else + alarm_out_reg[1] <= 0; + end + + if (curr_chan_lat == 2) begin + if (data_written > dr_sram[7'h52] || data_written < dr_sram[7'h56]) + alarm_out_reg[2] <= 1; + else + alarm_out_reg[2] <= 0; + end + end // always + + always @(ot_out_reg or ot_en or alarm_out_reg or alarm_en) + begin + ot_out = ot_out_reg & ot_en; + alarm_out = alarm_out_reg & alarm_en; + end + +// end alarm + + +endmodule diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/TBLOCK.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/TBLOCK.v new file mode 100644 index 0000000..a376e01 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/TBLOCK.v @@ -0,0 +1,26 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/TBLOCK.v,v 1.5 2007/05/23 21:43:44 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / +// /___/ /\ Filename : TBLOCK.v +// \ \ / \ Timestamp : Thu Mar 25 16:43:41 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. + +`timescale 1 ps / 1 ps + + +module TBLOCK (); + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/TEMAC.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/TEMAC.v new file mode 100644 index 0000000..8abcbb9 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/TEMAC.v @@ -0,0 +1,1848 @@ +/////////////////////////////////////////////////////////// +// Copyright (c) 1995/2006 Xilinx Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////// +// +// ____ ___ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Tri-Mode Ethernet MAC +// /__/ /\ Filename : TEMAC.v +// \ \ / \ Timestamp : Thu Dec 8 2005 +// \__\/\__ \ +// +// Revision: +// 12/08/05 - Initial version. +// 01/09/06 - Added case statement, specify block +// 02/06/06 - pinTime updates +// 02/23/06 - Updated Header +// 03/27/06 - Updated TEMAC smartmodel to version number 00.002 for following changes +// CR#224695 - +// 1. TEMAC smartmodel 16 bit client interface problem. +// 2. Compiled smartmodel with `delay_mode_zero directive +// CR#226083 - +// 1. Loopback attributes don't work in Verilog TEMAC smartmodel. +// CR#224695 - +// 1 . Added 50 ps input delay to all inputs(except clocks) going into temac swift model +// 04/11/06 - CR#228762 - Added some missing path delays to timing block. +// 04/27/06 - CR#230105 - Fixed connectivity for CLK +// 05/23/06 - CR#231962 - Add buffers for connectivity +// 06/22/06 - CR#233879 - Add parameter bus range +// 09/15/06 - CR#423162 - Timing updates +// 10/26/06 - - replaced zero_delay with CLK_DELAY to be consistent with writers (PPC440 update) +// 06/08/07 - CR#440717 - Add localparam EMAC0MIITXCLK_DELAY & EMAC1MIITXCLK_DELAY +// 08/28/07 - CR#447575 - Path Delay updates due to pinDev/pinTime updates +// End Revision +/////////////////////////////////////////////////////////// + +`timescale 1 ps / 1 ps + +module TEMAC ( + DCRHOSTDONEIR, + EMAC0CLIENTANINTERRUPT, + EMAC0CLIENTRXBADFRAME, + EMAC0CLIENTRXCLIENTCLKOUT, + EMAC0CLIENTRXD, + EMAC0CLIENTRXDVLD, + EMAC0CLIENTRXDVLDMSW, + EMAC0CLIENTRXFRAMEDROP, + EMAC0CLIENTRXGOODFRAME, + EMAC0CLIENTRXSTATS, + EMAC0CLIENTRXSTATSBYTEVLD, + EMAC0CLIENTRXSTATSVLD, + EMAC0CLIENTTXACK, + EMAC0CLIENTTXCLIENTCLKOUT, + EMAC0CLIENTTXCOLLISION, + EMAC0CLIENTTXRETRANSMIT, + EMAC0CLIENTTXSTATS, + EMAC0CLIENTTXSTATSBYTEVLD, + EMAC0CLIENTTXSTATSVLD, + EMAC0PHYENCOMMAALIGN, + EMAC0PHYLOOPBACKMSB, + EMAC0PHYMCLKOUT, + EMAC0PHYMDOUT, + EMAC0PHYMDTRI, + EMAC0PHYMGTRXRESET, + EMAC0PHYMGTTXRESET, + EMAC0PHYPOWERDOWN, + EMAC0PHYSYNCACQSTATUS, + EMAC0PHYTXCHARDISPMODE, + EMAC0PHYTXCHARDISPVAL, + EMAC0PHYTXCHARISK, + EMAC0PHYTXCLK, + EMAC0PHYTXD, + EMAC0PHYTXEN, + EMAC0PHYTXER, + EMAC0PHYTXGMIIMIICLKOUT, + EMAC0SPEEDIS10100, + EMAC1CLIENTANINTERRUPT, + EMAC1CLIENTRXBADFRAME, + EMAC1CLIENTRXCLIENTCLKOUT, + EMAC1CLIENTRXD, + EMAC1CLIENTRXDVLD, + EMAC1CLIENTRXDVLDMSW, + EMAC1CLIENTRXFRAMEDROP, + EMAC1CLIENTRXGOODFRAME, + EMAC1CLIENTRXSTATS, + EMAC1CLIENTRXSTATSBYTEVLD, + EMAC1CLIENTRXSTATSVLD, + EMAC1CLIENTTXACK, + EMAC1CLIENTTXCLIENTCLKOUT, + EMAC1CLIENTTXCOLLISION, + EMAC1CLIENTTXRETRANSMIT, + EMAC1CLIENTTXSTATS, + EMAC1CLIENTTXSTATSBYTEVLD, + EMAC1CLIENTTXSTATSVLD, + EMAC1PHYENCOMMAALIGN, + EMAC1PHYLOOPBACKMSB, + EMAC1PHYMCLKOUT, + EMAC1PHYMDOUT, + EMAC1PHYMDTRI, + EMAC1PHYMGTRXRESET, + EMAC1PHYMGTTXRESET, + EMAC1PHYPOWERDOWN, + EMAC1PHYSYNCACQSTATUS, + EMAC1PHYTXCHARDISPMODE, + EMAC1PHYTXCHARDISPVAL, + EMAC1PHYTXCHARISK, + EMAC1PHYTXCLK, + EMAC1PHYTXD, + EMAC1PHYTXEN, + EMAC1PHYTXER, + EMAC1PHYTXGMIIMIICLKOUT, + EMAC1SPEEDIS10100, + EMACDCRACK, + EMACDCRDBUS, + HOSTMIIMRDY, + HOSTRDDATA, + + CLIENTEMAC0DCMLOCKED, + CLIENTEMAC0PAUSEREQ, + CLIENTEMAC0PAUSEVAL, + CLIENTEMAC0RXCLIENTCLKIN, + CLIENTEMAC0TXCLIENTCLKIN, + CLIENTEMAC0TXD, + CLIENTEMAC0TXDVLD, + CLIENTEMAC0TXDVLDMSW, + CLIENTEMAC0TXFIRSTBYTE, + CLIENTEMAC0TXIFGDELAY, + CLIENTEMAC0TXUNDERRUN, + CLIENTEMAC1DCMLOCKED, + CLIENTEMAC1PAUSEREQ, + CLIENTEMAC1PAUSEVAL, + CLIENTEMAC1RXCLIENTCLKIN, + CLIENTEMAC1TXCLIENTCLKIN, + CLIENTEMAC1TXD, + CLIENTEMAC1TXDVLD, + CLIENTEMAC1TXDVLDMSW, + CLIENTEMAC1TXFIRSTBYTE, + CLIENTEMAC1TXIFGDELAY, + CLIENTEMAC1TXUNDERRUN, + DCREMACABUS, + DCREMACCLK, + DCREMACDBUS, + DCREMACENABLE, + DCREMACREAD, + DCREMACWRITE, + HOSTADDR, + HOSTCLK, + HOSTEMAC1SEL, + HOSTMIIMSEL, + HOSTOPCODE, + HOSTREQ, + HOSTWRDATA, + PHYEMAC0COL, + PHYEMAC0CRS, + PHYEMAC0GTXCLK, + PHYEMAC0MCLKIN, + PHYEMAC0MDIN, + PHYEMAC0MIITXCLK, + PHYEMAC0PHYAD, + PHYEMAC0RXBUFERR, + PHYEMAC0RXBUFSTATUS, + PHYEMAC0RXCHARISCOMMA, + PHYEMAC0RXCHARISK, + PHYEMAC0RXCHECKINGCRC, + PHYEMAC0RXCLK, + PHYEMAC0RXCLKCORCNT, + PHYEMAC0RXCOMMADET, + PHYEMAC0RXD, + PHYEMAC0RXDISPERR, + PHYEMAC0RXDV, + PHYEMAC0RXER, + PHYEMAC0RXLOSSOFSYNC, + PHYEMAC0RXNOTINTABLE, + PHYEMAC0RXRUNDISP, + PHYEMAC0SIGNALDET, + PHYEMAC0TXBUFERR, + PHYEMAC0TXGMIIMIICLKIN, + PHYEMAC1COL, + PHYEMAC1CRS, + PHYEMAC1GTXCLK, + PHYEMAC1MCLKIN, + PHYEMAC1MDIN, + PHYEMAC1MIITXCLK, + PHYEMAC1PHYAD, + PHYEMAC1RXBUFERR, + PHYEMAC1RXBUFSTATUS, + PHYEMAC1RXCHARISCOMMA, + PHYEMAC1RXCHARISK, + PHYEMAC1RXCHECKINGCRC, + PHYEMAC1RXCLK, + PHYEMAC1RXCLKCORCNT, + PHYEMAC1RXCOMMADET, + PHYEMAC1RXD, + PHYEMAC1RXDISPERR, + PHYEMAC1RXDV, + PHYEMAC1RXER, + PHYEMAC1RXLOSSOFSYNC, + PHYEMAC1RXNOTINTABLE, + PHYEMAC1RXRUNDISP, + PHYEMAC1SIGNALDET, + PHYEMAC1TXBUFERR, + PHYEMAC1TXGMIIMIICLKIN, + RESET + +); + + +parameter EMAC0_1000BASEX_ENABLE = "FALSE"; +parameter EMAC0_ADDRFILTER_ENABLE = "FALSE"; +parameter EMAC0_BYTEPHY = "FALSE"; +parameter EMAC0_CONFIGVEC_79 = "FALSE"; +parameter EMAC0_GTLOOPBACK = "FALSE"; +parameter EMAC0_HOST_ENABLE = "FALSE"; +parameter EMAC0_LTCHECK_DISABLE = "FALSE"; +parameter EMAC0_MDIO_ENABLE = "FALSE"; +parameter EMAC0_PHYINITAUTONEG_ENABLE = "FALSE"; +parameter EMAC0_PHYISOLATE = "FALSE"; +parameter EMAC0_PHYLOOPBACKMSB = "FALSE"; +parameter EMAC0_PHYPOWERDOWN = "FALSE"; +parameter EMAC0_PHYRESET = "FALSE"; +parameter EMAC0_RGMII_ENABLE = "FALSE"; +parameter EMAC0_RX16BITCLIENT_ENABLE = "FALSE"; +parameter EMAC0_RXFLOWCTRL_ENABLE = "FALSE"; +parameter EMAC0_RXHALFDUPLEX = "FALSE"; +parameter EMAC0_RXINBANDFCS_ENABLE = "FALSE"; +parameter EMAC0_RXJUMBOFRAME_ENABLE = "FALSE"; +parameter EMAC0_RXRESET = "FALSE"; +parameter EMAC0_RXVLAN_ENABLE = "FALSE"; +parameter EMAC0_RX_ENABLE = "FALSE"; +parameter EMAC0_SGMII_ENABLE = "FALSE"; +parameter EMAC0_SPEED_LSB = "FALSE"; +parameter EMAC0_SPEED_MSB = "FALSE"; +parameter EMAC0_TX16BITCLIENT_ENABLE = "FALSE"; +parameter EMAC0_TXFLOWCTRL_ENABLE = "FALSE"; +parameter EMAC0_TXHALFDUPLEX = "FALSE"; +parameter EMAC0_TXIFGADJUST_ENABLE = "FALSE"; +parameter EMAC0_TXINBANDFCS_ENABLE = "FALSE"; +parameter EMAC0_TXJUMBOFRAME_ENABLE = "FALSE"; +parameter EMAC0_TXRESET = "FALSE"; +parameter EMAC0_TXVLAN_ENABLE = "FALSE"; +parameter EMAC0_TX_ENABLE = "FALSE"; +parameter EMAC0_UNIDIRECTION_ENABLE = "FALSE"; +parameter EMAC0_USECLKEN = "FALSE"; +parameter EMAC1_1000BASEX_ENABLE = "FALSE"; +parameter EMAC1_ADDRFILTER_ENABLE = "FALSE"; +parameter EMAC1_BYTEPHY = "FALSE"; +parameter EMAC1_CONFIGVEC_79 = "FALSE"; +parameter EMAC1_GTLOOPBACK = "FALSE"; +parameter EMAC1_HOST_ENABLE = "FALSE"; +parameter EMAC1_LTCHECK_DISABLE = "FALSE"; +parameter EMAC1_MDIO_ENABLE = "FALSE"; +parameter EMAC1_PHYINITAUTONEG_ENABLE = "FALSE"; +parameter EMAC1_PHYISOLATE = "FALSE"; +parameter EMAC1_PHYLOOPBACKMSB = "FALSE"; +parameter EMAC1_PHYPOWERDOWN = "FALSE"; +parameter EMAC1_PHYRESET = "FALSE"; +parameter EMAC1_RGMII_ENABLE = "FALSE"; +parameter EMAC1_RX16BITCLIENT_ENABLE = "FALSE"; +parameter EMAC1_RXFLOWCTRL_ENABLE = "FALSE"; +parameter EMAC1_RXHALFDUPLEX = "FALSE"; +parameter EMAC1_RXINBANDFCS_ENABLE = "FALSE"; +parameter EMAC1_RXJUMBOFRAME_ENABLE = "FALSE"; +parameter EMAC1_RXRESET = "FALSE"; +parameter EMAC1_RXVLAN_ENABLE = "FALSE"; +parameter EMAC1_RX_ENABLE = "FALSE"; +parameter EMAC1_SGMII_ENABLE = "FALSE"; +parameter EMAC1_SPEED_LSB = "FALSE"; +parameter EMAC1_SPEED_MSB = "FALSE"; +parameter EMAC1_TX16BITCLIENT_ENABLE = "FALSE"; +parameter EMAC1_TXFLOWCTRL_ENABLE = "FALSE"; +parameter EMAC1_TXHALFDUPLEX = "FALSE"; +parameter EMAC1_TXIFGADJUST_ENABLE = "FALSE"; +parameter EMAC1_TXINBANDFCS_ENABLE = "FALSE"; +parameter EMAC1_TXJUMBOFRAME_ENABLE = "FALSE"; +parameter EMAC1_TXRESET = "FALSE"; +parameter EMAC1_TXVLAN_ENABLE = "FALSE"; +parameter EMAC1_TX_ENABLE = "FALSE"; +parameter EMAC1_UNIDIRECTION_ENABLE = "FALSE"; +parameter EMAC1_USECLKEN = "FALSE"; +parameter [0:7] EMAC0_DCRBASEADDR = 8'h00; +parameter [0:7] EMAC1_DCRBASEADDR = 8'h00; +parameter [47:0] EMAC0_PAUSEADDR = 48'h000000000000; +parameter [47:0] EMAC0_UNICASTADDR = 48'h000000000000; +parameter [47:0] EMAC1_PAUSEADDR = 48'h000000000000; +parameter [47:0] EMAC1_UNICASTADDR = 48'h000000000000; +parameter [8:0] EMAC0_LINKTIMERVAL = 9'h000; +parameter [8:0] EMAC1_LINKTIMERVAL = 9'h000; + +localparam in_delay = 50; +localparam out_delay = 0; +localparam CLK_DELAY = 0; +// Separate MIITXCLK delays are used to allow EMAC0/1 configuration to modes other than 16-bit client +localparam EMAC0MIITXCLK_DELAY = (EMAC0_TX16BITCLIENT_ENABLE == "TRUE") ? 25 : CLK_DELAY; +localparam EMAC1MIITXCLK_DELAY = (EMAC1_TX16BITCLIENT_ENABLE == "TRUE") ? 25 : CLK_DELAY; + +output DCRHOSTDONEIR; +output EMAC0CLIENTANINTERRUPT; +output EMAC0CLIENTRXBADFRAME; +output EMAC0CLIENTRXCLIENTCLKOUT; +output EMAC0CLIENTRXDVLD; +output EMAC0CLIENTRXDVLDMSW; +output EMAC0CLIENTRXFRAMEDROP; +output EMAC0CLIENTRXGOODFRAME; +output EMAC0CLIENTRXSTATSBYTEVLD; +output EMAC0CLIENTRXSTATSVLD; +output EMAC0CLIENTTXACK; +output EMAC0CLIENTTXCLIENTCLKOUT; +output EMAC0CLIENTTXCOLLISION; +output EMAC0CLIENTTXRETRANSMIT; +output EMAC0CLIENTTXSTATS; +output EMAC0CLIENTTXSTATSBYTEVLD; +output EMAC0CLIENTTXSTATSVLD; +output EMAC0PHYENCOMMAALIGN; +output EMAC0PHYLOOPBACKMSB; +output EMAC0PHYMCLKOUT; +output EMAC0PHYMDOUT; +output EMAC0PHYMDTRI; +output EMAC0PHYMGTRXRESET; +output EMAC0PHYMGTTXRESET; +output EMAC0PHYPOWERDOWN; +output EMAC0PHYSYNCACQSTATUS; +output EMAC0PHYTXCHARDISPMODE; +output EMAC0PHYTXCHARDISPVAL; +output EMAC0PHYTXCHARISK; +output EMAC0PHYTXCLK; +output EMAC0PHYTXEN; +output EMAC0PHYTXER; +output EMAC0PHYTXGMIIMIICLKOUT; +output EMAC0SPEEDIS10100; +output EMAC1CLIENTANINTERRUPT; +output EMAC1CLIENTRXBADFRAME; +output EMAC1CLIENTRXCLIENTCLKOUT; +output EMAC1CLIENTRXDVLD; +output EMAC1CLIENTRXDVLDMSW; +output EMAC1CLIENTRXFRAMEDROP; +output EMAC1CLIENTRXGOODFRAME; +output EMAC1CLIENTRXSTATSBYTEVLD; +output EMAC1CLIENTRXSTATSVLD; +output EMAC1CLIENTTXACK; +output EMAC1CLIENTTXCLIENTCLKOUT; +output EMAC1CLIENTTXCOLLISION; +output EMAC1CLIENTTXRETRANSMIT; +output EMAC1CLIENTTXSTATS; +output EMAC1CLIENTTXSTATSBYTEVLD; +output EMAC1CLIENTTXSTATSVLD; +output EMAC1PHYENCOMMAALIGN; +output EMAC1PHYLOOPBACKMSB; +output EMAC1PHYMCLKOUT; +output EMAC1PHYMDOUT; +output EMAC1PHYMDTRI; +output EMAC1PHYMGTRXRESET; +output EMAC1PHYMGTTXRESET; +output EMAC1PHYPOWERDOWN; +output EMAC1PHYSYNCACQSTATUS; +output EMAC1PHYTXCHARDISPMODE; +output EMAC1PHYTXCHARDISPVAL; +output EMAC1PHYTXCHARISK; +output EMAC1PHYTXCLK; +output EMAC1PHYTXEN; +output EMAC1PHYTXER; +output EMAC1PHYTXGMIIMIICLKOUT; +output EMAC1SPEEDIS10100; +output EMACDCRACK; +output HOSTMIIMRDY; +output [0:31] EMACDCRDBUS; +output [15:0] EMAC0CLIENTRXD; +output [15:0] EMAC1CLIENTRXD; +output [31:0] HOSTRDDATA; +output [6:0] EMAC0CLIENTRXSTATS; +output [6:0] EMAC1CLIENTRXSTATS; +output [7:0] EMAC0PHYTXD; +output [7:0] EMAC1PHYTXD; + +input CLIENTEMAC0DCMLOCKED; +input CLIENTEMAC0PAUSEREQ; +input CLIENTEMAC0RXCLIENTCLKIN; +input CLIENTEMAC0TXCLIENTCLKIN; +input CLIENTEMAC0TXDVLD; +input CLIENTEMAC0TXDVLDMSW; +input CLIENTEMAC0TXFIRSTBYTE; +input CLIENTEMAC0TXUNDERRUN; +input CLIENTEMAC1DCMLOCKED; +input CLIENTEMAC1PAUSEREQ; +input CLIENTEMAC1RXCLIENTCLKIN; +input CLIENTEMAC1TXCLIENTCLKIN; +input CLIENTEMAC1TXDVLD; +input CLIENTEMAC1TXDVLDMSW; +input CLIENTEMAC1TXFIRSTBYTE; +input CLIENTEMAC1TXUNDERRUN; +input DCREMACCLK; +input DCREMACENABLE; +input DCREMACREAD; +input DCREMACWRITE; +input HOSTCLK; +input HOSTEMAC1SEL; +input HOSTMIIMSEL; +input HOSTREQ; +input PHYEMAC0COL; +input PHYEMAC0CRS; +input PHYEMAC0GTXCLK; +input PHYEMAC0MCLKIN; +input PHYEMAC0MDIN; +input PHYEMAC0MIITXCLK; +input PHYEMAC0RXBUFERR; +input PHYEMAC0RXCHARISCOMMA; +input PHYEMAC0RXCHARISK; +input PHYEMAC0RXCHECKINGCRC; +input PHYEMAC0RXCLK; +input PHYEMAC0RXCOMMADET; +input PHYEMAC0RXDISPERR; +input PHYEMAC0RXDV; +input PHYEMAC0RXER; +input PHYEMAC0RXNOTINTABLE; +input PHYEMAC0RXRUNDISP; +input PHYEMAC0SIGNALDET; +input PHYEMAC0TXBUFERR; +input PHYEMAC0TXGMIIMIICLKIN; +input PHYEMAC1COL; +input PHYEMAC1CRS; +input PHYEMAC1GTXCLK; +input PHYEMAC1MCLKIN; +input PHYEMAC1MDIN; +input PHYEMAC1MIITXCLK; +input PHYEMAC1RXBUFERR; +input PHYEMAC1RXCHARISCOMMA; +input PHYEMAC1RXCHARISK; +input PHYEMAC1RXCHECKINGCRC; +input PHYEMAC1RXCLK; +input PHYEMAC1RXCOMMADET; +input PHYEMAC1RXDISPERR; +input PHYEMAC1RXDV; +input PHYEMAC1RXER; +input PHYEMAC1RXNOTINTABLE; +input PHYEMAC1RXRUNDISP; +input PHYEMAC1SIGNALDET; +input PHYEMAC1TXBUFERR; +input PHYEMAC1TXGMIIMIICLKIN; +input RESET; +input [0:31] DCREMACDBUS; +input [0:9] DCREMACABUS; +input [15:0] CLIENTEMAC0PAUSEVAL; +input [15:0] CLIENTEMAC0TXD; +input [15:0] CLIENTEMAC1PAUSEVAL; +input [15:0] CLIENTEMAC1TXD; +input [1:0] HOSTOPCODE; +input [1:0] PHYEMAC0RXBUFSTATUS; +input [1:0] PHYEMAC0RXLOSSOFSYNC; +input [1:0] PHYEMAC1RXBUFSTATUS; +input [1:0] PHYEMAC1RXLOSSOFSYNC; +input [2:0] PHYEMAC0RXCLKCORCNT; +input [2:0] PHYEMAC1RXCLKCORCNT; +input [31:0] HOSTWRDATA; +input [4:0] PHYEMAC0PHYAD; +input [4:0] PHYEMAC1PHYAD; +input [7:0] CLIENTEMAC0TXIFGDELAY; +input [7:0] CLIENTEMAC1TXIFGDELAY; +input [7:0] PHYEMAC0RXD; +input [7:0] PHYEMAC1RXD; +input [9:0] HOSTADDR; + +reg EMAC0_1000BASEX_ENABLE_BINARY; +reg EMAC0_ADDRFILTER_ENABLE_BINARY; +reg EMAC0_BYTEPHY_BINARY; +reg EMAC0_CONFIGVEC_79_BINARY; +reg EMAC0_GTLOOPBACK_BINARY; +reg EMAC0_HOST_ENABLE_BINARY; +reg EMAC0_LTCHECK_DISABLE_BINARY; +reg EMAC0_MDIO_ENABLE_BINARY; +reg EMAC0_PHYINITAUTONEG_ENABLE_BINARY; +reg EMAC0_PHYISOLATE_BINARY; +reg EMAC0_PHYLOOPBACKMSB_BINARY; +reg EMAC0_PHYPOWERDOWN_BINARY; +reg EMAC0_PHYRESET_BINARY; +reg EMAC0_RGMII_ENABLE_BINARY; +reg EMAC0_RX16BITCLIENT_ENABLE_BINARY; +reg EMAC0_RXFLOWCTRL_ENABLE_BINARY; +reg EMAC0_RXHALFDUPLEX_BINARY; +reg EMAC0_RXINBANDFCS_ENABLE_BINARY; +reg EMAC0_RXJUMBOFRAME_ENABLE_BINARY; +reg EMAC0_RXRESET_BINARY; +reg EMAC0_RXVLAN_ENABLE_BINARY; +reg EMAC0_RX_ENABLE_BINARY; +reg EMAC0_SGMII_ENABLE_BINARY; +reg EMAC0_SPEED_LSB_BINARY; +reg EMAC0_SPEED_MSB_BINARY; +reg EMAC0_TX16BITCLIENT_ENABLE_BINARY; +reg EMAC0_TXFLOWCTRL_ENABLE_BINARY; +reg EMAC0_TXHALFDUPLEX_BINARY; +reg EMAC0_TXIFGADJUST_ENABLE_BINARY; +reg EMAC0_TXINBANDFCS_ENABLE_BINARY; +reg EMAC0_TXJUMBOFRAME_ENABLE_BINARY; +reg EMAC0_TXRESET_BINARY; +reg EMAC0_TXVLAN_ENABLE_BINARY; +reg EMAC0_TX_ENABLE_BINARY; +reg EMAC0_UNIDIRECTION_ENABLE_BINARY; +reg EMAC0_USECLKEN_BINARY; +reg EMAC1_1000BASEX_ENABLE_BINARY; +reg EMAC1_ADDRFILTER_ENABLE_BINARY; +reg EMAC1_BYTEPHY_BINARY; +reg EMAC1_CONFIGVEC_79_BINARY; +reg EMAC1_GTLOOPBACK_BINARY; +reg EMAC1_HOST_ENABLE_BINARY; +reg EMAC1_LTCHECK_DISABLE_BINARY; +reg EMAC1_MDIO_ENABLE_BINARY; +reg EMAC1_PHYINITAUTONEG_ENABLE_BINARY; +reg EMAC1_PHYISOLATE_BINARY; +reg EMAC1_PHYLOOPBACKMSB_BINARY; +reg EMAC1_PHYPOWERDOWN_BINARY; +reg EMAC1_PHYRESET_BINARY; +reg EMAC1_RGMII_ENABLE_BINARY; +reg EMAC1_RX16BITCLIENT_ENABLE_BINARY; +reg EMAC1_RXFLOWCTRL_ENABLE_BINARY; +reg EMAC1_RXHALFDUPLEX_BINARY; +reg EMAC1_RXINBANDFCS_ENABLE_BINARY; +reg EMAC1_RXJUMBOFRAME_ENABLE_BINARY; +reg EMAC1_RXRESET_BINARY; +reg EMAC1_RXVLAN_ENABLE_BINARY; +reg EMAC1_RX_ENABLE_BINARY; +reg EMAC1_SGMII_ENABLE_BINARY; +reg EMAC1_SPEED_LSB_BINARY; +reg EMAC1_SPEED_MSB_BINARY; +reg EMAC1_TX16BITCLIENT_ENABLE_BINARY; +reg EMAC1_TXFLOWCTRL_ENABLE_BINARY; +reg EMAC1_TXHALFDUPLEX_BINARY; +reg EMAC1_TXIFGADJUST_ENABLE_BINARY; +reg EMAC1_TXINBANDFCS_ENABLE_BINARY; +reg EMAC1_TXJUMBOFRAME_ENABLE_BINARY; +reg EMAC1_TXRESET_BINARY; +reg EMAC1_TXVLAN_ENABLE_BINARY; +reg EMAC1_TX_ENABLE_BINARY; +reg EMAC1_UNIDIRECTION_ENABLE_BINARY; +reg EMAC1_USECLKEN_BINARY; + +initial begin + case (EMAC0_RXHALFDUPLEX) + "FALSE" : EMAC0_RXHALFDUPLEX_BINARY = 1'b0; + "TRUE" : EMAC0_RXHALFDUPLEX_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute EMAC0_RXHALFDUPLEX on TEMAC instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", EMAC0_RXHALFDUPLEX); + $finish; + end + endcase + + case (EMAC0_RXVLAN_ENABLE) + "FALSE" : EMAC0_RXVLAN_ENABLE_BINARY = 1'b0; + "TRUE" : EMAC0_RXVLAN_ENABLE_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute EMAC0_RXVLAN_ENABLE on TEMAC instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", EMAC0_RXVLAN_ENABLE); + $finish; + end + endcase + + case (EMAC0_RX_ENABLE) + "FALSE" : EMAC0_RX_ENABLE_BINARY = 1'b0; + "TRUE" : EMAC0_RX_ENABLE_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute EMAC0_RX_ENABLE on TEMAC instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", EMAC0_RX_ENABLE); + $finish; + end + endcase + + case (EMAC0_RXINBANDFCS_ENABLE) + "FALSE" : EMAC0_RXINBANDFCS_ENABLE_BINARY = 1'b0; + "TRUE" : EMAC0_RXINBANDFCS_ENABLE_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute EMAC0_RXINBANDFCS_ENABLE on TEMAC instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", EMAC0_RXINBANDFCS_ENABLE); + $finish; + end + endcase + + case (EMAC0_RXJUMBOFRAME_ENABLE) + "FALSE" : EMAC0_RXJUMBOFRAME_ENABLE_BINARY = 1'b0; + "TRUE" : EMAC0_RXJUMBOFRAME_ENABLE_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute EMAC0_RXJUMBOFRAME_ENABLE on TEMAC instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", EMAC0_RXJUMBOFRAME_ENABLE); + $finish; + end + endcase + + case (EMAC0_RXRESET) + "FALSE" : EMAC0_RXRESET_BINARY = 1'b0; + "TRUE" : EMAC0_RXRESET_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute EMAC0_RXRESET on TEMAC instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", EMAC0_RXRESET); + $finish; + end + endcase + + case (EMAC0_TXIFGADJUST_ENABLE) + "FALSE" : EMAC0_TXIFGADJUST_ENABLE_BINARY = 1'b0; + "TRUE" : EMAC0_TXIFGADJUST_ENABLE_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute EMAC0_TXIFGADJUST_ENABLE on TEMAC instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", EMAC0_TXIFGADJUST_ENABLE); + $finish; + end + endcase + + case (EMAC0_TXHALFDUPLEX) + "FALSE" : EMAC0_TXHALFDUPLEX_BINARY = 1'b0; + "TRUE" : EMAC0_TXHALFDUPLEX_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute EMAC0_TXHALFDUPLEX on TEMAC instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", EMAC0_TXHALFDUPLEX); + $finish; + end + endcase + + case (EMAC0_TXVLAN_ENABLE) + "FALSE" : EMAC0_TXVLAN_ENABLE_BINARY = 1'b0; + "TRUE" : EMAC0_TXVLAN_ENABLE_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute EMAC0_TXVLAN_ENABLE on TEMAC instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", EMAC0_TXVLAN_ENABLE); + $finish; + end + endcase + + case (EMAC0_TX_ENABLE) + "FALSE" : EMAC0_TX_ENABLE_BINARY = 1'b0; + "TRUE" : EMAC0_TX_ENABLE_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute EMAC0_TX_ENABLE on TEMAC instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", EMAC0_TX_ENABLE); + $finish; + end + endcase + + case (EMAC0_TXINBANDFCS_ENABLE) + "FALSE" : EMAC0_TXINBANDFCS_ENABLE_BINARY = 1'b0; + "TRUE" : EMAC0_TXINBANDFCS_ENABLE_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute EMAC0_TXINBANDFCS_ENABLE on TEMAC instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", EMAC0_TXINBANDFCS_ENABLE); + $finish; + end + endcase + + case (EMAC0_TXJUMBOFRAME_ENABLE) + "FALSE" : EMAC0_TXJUMBOFRAME_ENABLE_BINARY = 1'b0; + "TRUE" : EMAC0_TXJUMBOFRAME_ENABLE_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute EMAC0_TXJUMBOFRAME_ENABLE on TEMAC instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", EMAC0_TXJUMBOFRAME_ENABLE); + $finish; + end + endcase + + case (EMAC0_TXRESET) + "FALSE" : EMAC0_TXRESET_BINARY = 1'b0; + "TRUE" : EMAC0_TXRESET_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute EMAC0_TXRESET on TEMAC instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", EMAC0_TXRESET); + $finish; + end + endcase + + case (EMAC0_TXFLOWCTRL_ENABLE) + "FALSE" : EMAC0_TXFLOWCTRL_ENABLE_BINARY = 1'b0; + "TRUE" : EMAC0_TXFLOWCTRL_ENABLE_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute EMAC0_TXFLOWCTRL_ENABLE on TEMAC instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", EMAC0_TXFLOWCTRL_ENABLE); + $finish; + end + endcase + + case (EMAC0_RXFLOWCTRL_ENABLE) + "FALSE" : EMAC0_RXFLOWCTRL_ENABLE_BINARY = 1'b0; + "TRUE" : EMAC0_RXFLOWCTRL_ENABLE_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute EMAC0_RXFLOWCTRL_ENABLE on TEMAC instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", EMAC0_RXFLOWCTRL_ENABLE); + $finish; + end + endcase + + case (EMAC0_LTCHECK_DISABLE) + "FALSE" : EMAC0_LTCHECK_DISABLE_BINARY = 1'b0; + "TRUE" : EMAC0_LTCHECK_DISABLE_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute EMAC0_LTCHECK_DISABLE on TEMAC instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", EMAC0_LTCHECK_DISABLE); + $finish; + end + endcase + + case (EMAC0_ADDRFILTER_ENABLE) + "FALSE" : EMAC0_ADDRFILTER_ENABLE_BINARY = 1'b0; + "TRUE" : EMAC0_ADDRFILTER_ENABLE_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute EMAC0_ADDRFILTER_ENABLE on TEMAC instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", EMAC0_ADDRFILTER_ENABLE); + $finish; + end + endcase + + case (EMAC0_RX16BITCLIENT_ENABLE) + "FALSE" : EMAC0_RX16BITCLIENT_ENABLE_BINARY = 1'b0; + "TRUE" : EMAC0_RX16BITCLIENT_ENABLE_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute EMAC0_RX16BITCLIENT_ENABLE on TEMAC instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", EMAC0_RX16BITCLIENT_ENABLE); + $finish; + end + endcase + + case (EMAC0_TX16BITCLIENT_ENABLE) + "FALSE" : EMAC0_TX16BITCLIENT_ENABLE_BINARY = 1'b0; + "TRUE" : EMAC0_TX16BITCLIENT_ENABLE_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute EMAC0_TX16BITCLIENT_ENABLE on TEMAC instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", EMAC0_TX16BITCLIENT_ENABLE); + $finish; + end + endcase + + case (EMAC0_HOST_ENABLE) + "FALSE" : EMAC0_HOST_ENABLE_BINARY = 1'b0; + "TRUE" : EMAC0_HOST_ENABLE_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute EMAC0_HOST_ENABLE on TEMAC instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", EMAC0_HOST_ENABLE); + $finish; + end + endcase + + case (EMAC0_1000BASEX_ENABLE) + "FALSE" : EMAC0_1000BASEX_ENABLE_BINARY = 1'b0; + "TRUE" : EMAC0_1000BASEX_ENABLE_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute EMAC0_1000BASEX_ENABLE on TEMAC instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", EMAC0_1000BASEX_ENABLE); + $finish; + end + endcase + + case (EMAC0_SGMII_ENABLE) + "FALSE" : EMAC0_SGMII_ENABLE_BINARY = 1'b0; + "TRUE" : EMAC0_SGMII_ENABLE_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute EMAC0_SGMII_ENABLE on TEMAC instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", EMAC0_SGMII_ENABLE); + $finish; + end + endcase + + case (EMAC0_RGMII_ENABLE) + "FALSE" : EMAC0_RGMII_ENABLE_BINARY = 1'b0; + "TRUE" : EMAC0_RGMII_ENABLE_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute EMAC0_RGMII_ENABLE on TEMAC instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", EMAC0_RGMII_ENABLE); + $finish; + end + endcase + + case (EMAC0_SPEED_LSB) + "FALSE" : EMAC0_SPEED_LSB_BINARY = 1'b0; + "TRUE" : EMAC0_SPEED_LSB_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute EMAC0_SPEED_LSB on TEMAC instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", EMAC0_SPEED_LSB); + $finish; + end + endcase + + case (EMAC0_SPEED_MSB) + "FALSE" : EMAC0_SPEED_MSB_BINARY = 1'b0; + "TRUE" : EMAC0_SPEED_MSB_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute EMAC0_SPEED_MSB on TEMAC instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", EMAC0_SPEED_MSB); + $finish; + end + endcase + + case (EMAC0_MDIO_ENABLE) + "FALSE" : EMAC0_MDIO_ENABLE_BINARY = 1'b0; + "TRUE" : EMAC0_MDIO_ENABLE_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute EMAC0_MDIO_ENABLE on TEMAC instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", EMAC0_MDIO_ENABLE); + $finish; + end + endcase + + case (EMAC0_PHYLOOPBACKMSB) + "FALSE" : EMAC0_PHYLOOPBACKMSB_BINARY = 1'b0; + "TRUE" : EMAC0_PHYLOOPBACKMSB_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute EMAC0_PHYLOOPBACKMSB on TEMAC instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", EMAC0_PHYLOOPBACKMSB); + $finish; + end + endcase + + case (EMAC0_PHYPOWERDOWN) + "FALSE" : EMAC0_PHYPOWERDOWN_BINARY = 1'b0; + "TRUE" : EMAC0_PHYPOWERDOWN_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute EMAC0_PHYPOWERDOWN on TEMAC instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", EMAC0_PHYPOWERDOWN); + $finish; + end + endcase + + case (EMAC0_PHYISOLATE) + "FALSE" : EMAC0_PHYISOLATE_BINARY = 1'b0; + "TRUE" : EMAC0_PHYISOLATE_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute EMAC0_PHYISOLATE on TEMAC instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", EMAC0_PHYISOLATE); + $finish; + end + endcase + + case (EMAC0_PHYINITAUTONEG_ENABLE) + "FALSE" : EMAC0_PHYINITAUTONEG_ENABLE_BINARY = 1'b0; + "TRUE" : EMAC0_PHYINITAUTONEG_ENABLE_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute EMAC0_PHYINITAUTONEG_ENABLE on TEMAC instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", EMAC0_PHYINITAUTONEG_ENABLE); + $finish; + end + endcase + + case (EMAC0_PHYRESET) + "FALSE" : EMAC0_PHYRESET_BINARY = 1'b0; + "TRUE" : EMAC0_PHYRESET_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute EMAC0_PHYRESET on TEMAC instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", EMAC0_PHYRESET); + $finish; + end + endcase + + case (EMAC0_CONFIGVEC_79) + "FALSE" : EMAC0_CONFIGVEC_79_BINARY = 1'b0; + "TRUE" : EMAC0_CONFIGVEC_79_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute EMAC0_CONFIGVEC_79 on TEMAC instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", EMAC0_CONFIGVEC_79); + $finish; + end + endcase + + case (EMAC0_UNIDIRECTION_ENABLE) + "FALSE" : EMAC0_UNIDIRECTION_ENABLE_BINARY = 1'b0; + "TRUE" : EMAC0_UNIDIRECTION_ENABLE_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute EMAC0_UNIDIRECTION_ENABLE on TEMAC instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", EMAC0_UNIDIRECTION_ENABLE); + $finish; + end + endcase + + case (EMAC0_GTLOOPBACK) + "FALSE" : EMAC0_GTLOOPBACK_BINARY = 1'b0; + "TRUE" : EMAC0_GTLOOPBACK_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute EMAC0_GTLOOPBACK on TEMAC instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", EMAC0_GTLOOPBACK); + $finish; + end + endcase + + case (EMAC0_BYTEPHY) + "FALSE" : EMAC0_BYTEPHY_BINARY = 1'b0; + "TRUE" : EMAC0_BYTEPHY_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute EMAC0_BYTEPHY on TEMAC instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", EMAC0_BYTEPHY); + $finish; + end + endcase + + case (EMAC0_USECLKEN) + "FALSE" : EMAC0_USECLKEN_BINARY = 1'b0; + "TRUE" : EMAC0_USECLKEN_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute EMAC0_USECLKEN on TEMAC instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", EMAC0_USECLKEN); + $finish; + end + endcase + + case (EMAC1_RXHALFDUPLEX) + "FALSE" : EMAC1_RXHALFDUPLEX_BINARY = 1'b0; + "TRUE" : EMAC1_RXHALFDUPLEX_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute EMAC1_RXHALFDUPLEX on TEMAC instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", EMAC1_RXHALFDUPLEX); + $finish; + end + endcase + + case (EMAC1_RXVLAN_ENABLE) + "FALSE" : EMAC1_RXVLAN_ENABLE_BINARY = 1'b0; + "TRUE" : EMAC1_RXVLAN_ENABLE_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute EMAC1_RXVLAN_ENABLE on TEMAC instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", EMAC1_RXVLAN_ENABLE); + $finish; + end + endcase + + case (EMAC1_RX_ENABLE) + "FALSE" : EMAC1_RX_ENABLE_BINARY = 1'b0; + "TRUE" : EMAC1_RX_ENABLE_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute EMAC1_RX_ENABLE on TEMAC instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", EMAC1_RX_ENABLE); + $finish; + end + endcase + + case (EMAC1_RXINBANDFCS_ENABLE) + "FALSE" : EMAC1_RXINBANDFCS_ENABLE_BINARY = 1'b0; + "TRUE" : EMAC1_RXINBANDFCS_ENABLE_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute EMAC1_RXINBANDFCS_ENABLE on TEMAC instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", EMAC1_RXINBANDFCS_ENABLE); + $finish; + end + endcase + + case (EMAC1_RXJUMBOFRAME_ENABLE) + "FALSE" : EMAC1_RXJUMBOFRAME_ENABLE_BINARY = 1'b0; + "TRUE" : EMAC1_RXJUMBOFRAME_ENABLE_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute EMAC1_RXJUMBOFRAME_ENABLE on TEMAC instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", EMAC1_RXJUMBOFRAME_ENABLE); + $finish; + end + endcase + + case (EMAC1_RXRESET) + "FALSE" : EMAC1_RXRESET_BINARY = 1'b0; + "TRUE" : EMAC1_RXRESET_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute EMAC1_RXRESET on TEMAC instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", EMAC1_RXRESET); + $finish; + end + endcase + + case (EMAC1_TXIFGADJUST_ENABLE) + "FALSE" : EMAC1_TXIFGADJUST_ENABLE_BINARY = 1'b0; + "TRUE" : EMAC1_TXIFGADJUST_ENABLE_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute EMAC1_TXIFGADJUST_ENABLE on TEMAC instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", EMAC1_TXIFGADJUST_ENABLE); + $finish; + end + endcase + + case (EMAC1_TXHALFDUPLEX) + "FALSE" : EMAC1_TXHALFDUPLEX_BINARY = 1'b0; + "TRUE" : EMAC1_TXHALFDUPLEX_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute EMAC1_TXHALFDUPLEX on TEMAC instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", EMAC1_TXHALFDUPLEX); + $finish; + end + endcase + + case (EMAC1_TXVLAN_ENABLE) + "FALSE" : EMAC1_TXVLAN_ENABLE_BINARY = 1'b0; + "TRUE" : EMAC1_TXVLAN_ENABLE_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute EMAC1_TXVLAN_ENABLE on TEMAC instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", EMAC1_TXVLAN_ENABLE); + $finish; + end + endcase + + case (EMAC1_TX_ENABLE) + "FALSE" : EMAC1_TX_ENABLE_BINARY = 1'b0; + "TRUE" : EMAC1_TX_ENABLE_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute EMAC1_TX_ENABLE on TEMAC instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", EMAC1_TX_ENABLE); + $finish; + end + endcase + + case (EMAC1_TXINBANDFCS_ENABLE) + "FALSE" : EMAC1_TXINBANDFCS_ENABLE_BINARY = 1'b0; + "TRUE" : EMAC1_TXINBANDFCS_ENABLE_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute EMAC1_TXINBANDFCS_ENABLE on TEMAC instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", EMAC1_TXINBANDFCS_ENABLE); + $finish; + end + endcase + + case (EMAC1_TXJUMBOFRAME_ENABLE) + "FALSE" : EMAC1_TXJUMBOFRAME_ENABLE_BINARY = 1'b0; + "TRUE" : EMAC1_TXJUMBOFRAME_ENABLE_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute EMAC1_TXJUMBOFRAME_ENABLE on TEMAC instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", EMAC1_TXJUMBOFRAME_ENABLE); + $finish; + end + endcase + + case (EMAC1_TXRESET) + "FALSE" : EMAC1_TXRESET_BINARY = 1'b0; + "TRUE" : EMAC1_TXRESET_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute EMAC1_TXRESET on TEMAC instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", EMAC1_TXRESET); + $finish; + end + endcase + + case (EMAC1_TXFLOWCTRL_ENABLE) + "FALSE" : EMAC1_TXFLOWCTRL_ENABLE_BINARY = 1'b0; + "TRUE" : EMAC1_TXFLOWCTRL_ENABLE_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute EMAC1_TXFLOWCTRL_ENABLE on TEMAC instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", EMAC1_TXFLOWCTRL_ENABLE); + $finish; + end + endcase + + case (EMAC1_RXFLOWCTRL_ENABLE) + "FALSE" : EMAC1_RXFLOWCTRL_ENABLE_BINARY = 1'b0; + "TRUE" : EMAC1_RXFLOWCTRL_ENABLE_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute EMAC1_RXFLOWCTRL_ENABLE on TEMAC instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", EMAC1_RXFLOWCTRL_ENABLE); + $finish; + end + endcase + + case (EMAC1_LTCHECK_DISABLE) + "FALSE" : EMAC1_LTCHECK_DISABLE_BINARY = 1'b0; + "TRUE" : EMAC1_LTCHECK_DISABLE_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute EMAC1_LTCHECK_DISABLE on TEMAC instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", EMAC1_LTCHECK_DISABLE); + $finish; + end + endcase + + case (EMAC1_ADDRFILTER_ENABLE) + "FALSE" : EMAC1_ADDRFILTER_ENABLE_BINARY = 1'b0; + "TRUE" : EMAC1_ADDRFILTER_ENABLE_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute EMAC1_ADDRFILTER_ENABLE on TEMAC instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", EMAC1_ADDRFILTER_ENABLE); + $finish; + end + endcase + + case (EMAC1_RX16BITCLIENT_ENABLE) + "FALSE" : EMAC1_RX16BITCLIENT_ENABLE_BINARY = 1'b0; + "TRUE" : EMAC1_RX16BITCLIENT_ENABLE_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute EMAC1_RX16BITCLIENT_ENABLE on TEMAC instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", EMAC1_RX16BITCLIENT_ENABLE); + $finish; + end + endcase + + case (EMAC1_TX16BITCLIENT_ENABLE) + "FALSE" : EMAC1_TX16BITCLIENT_ENABLE_BINARY = 1'b0; + "TRUE" : EMAC1_TX16BITCLIENT_ENABLE_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute EMAC1_TX16BITCLIENT_ENABLE on TEMAC instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", EMAC1_TX16BITCLIENT_ENABLE); + $finish; + end + endcase + + case (EMAC1_HOST_ENABLE) + "FALSE" : EMAC1_HOST_ENABLE_BINARY = 1'b0; + "TRUE" : EMAC1_HOST_ENABLE_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute EMAC1_HOST_ENABLE on TEMAC instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", EMAC1_HOST_ENABLE); + $finish; + end + endcase + + case (EMAC1_1000BASEX_ENABLE) + "FALSE" : EMAC1_1000BASEX_ENABLE_BINARY = 1'b0; + "TRUE" : EMAC1_1000BASEX_ENABLE_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute EMAC1_1000BASEX_ENABLE on TEMAC instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", EMAC1_1000BASEX_ENABLE); + $finish; + end + endcase + + case (EMAC1_SGMII_ENABLE) + "FALSE" : EMAC1_SGMII_ENABLE_BINARY = 1'b0; + "TRUE" : EMAC1_SGMII_ENABLE_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute EMAC1_SGMII_ENABLE on TEMAC instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", EMAC1_SGMII_ENABLE); + $finish; + end + endcase + + case (EMAC1_RGMII_ENABLE) + "FALSE" : EMAC1_RGMII_ENABLE_BINARY = 1'b0; + "TRUE" : EMAC1_RGMII_ENABLE_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute EMAC1_RGMII_ENABLE on TEMAC instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", EMAC1_RGMII_ENABLE); + $finish; + end + endcase + + case (EMAC1_SPEED_LSB) + "FALSE" : EMAC1_SPEED_LSB_BINARY = 1'b0; + "TRUE" : EMAC1_SPEED_LSB_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute EMAC1_SPEED_LSB on TEMAC instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", EMAC1_SPEED_LSB); + $finish; + end + endcase + + case (EMAC1_SPEED_MSB) + "FALSE" : EMAC1_SPEED_MSB_BINARY = 1'b0; + "TRUE" : EMAC1_SPEED_MSB_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute EMAC1_SPEED_MSB on TEMAC instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", EMAC1_SPEED_MSB); + $finish; + end + endcase + + case (EMAC1_MDIO_ENABLE) + "FALSE" : EMAC1_MDIO_ENABLE_BINARY = 1'b0; + "TRUE" : EMAC1_MDIO_ENABLE_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute EMAC1_MDIO_ENABLE on TEMAC instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", EMAC1_MDIO_ENABLE); + $finish; + end + endcase + + case (EMAC1_PHYLOOPBACKMSB) + "FALSE" : EMAC1_PHYLOOPBACKMSB_BINARY = 1'b0; + "TRUE" : EMAC1_PHYLOOPBACKMSB_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute EMAC1_PHYLOOPBACKMSB on TEMAC instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", EMAC1_PHYLOOPBACKMSB); + $finish; + end + endcase + + case (EMAC1_PHYPOWERDOWN) + "FALSE" : EMAC1_PHYPOWERDOWN_BINARY = 1'b0; + "TRUE" : EMAC1_PHYPOWERDOWN_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute EMAC1_PHYPOWERDOWN on TEMAC instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", EMAC1_PHYPOWERDOWN); + $finish; + end + endcase + + case (EMAC1_PHYISOLATE) + "FALSE" : EMAC1_PHYISOLATE_BINARY = 1'b0; + "TRUE" : EMAC1_PHYISOLATE_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute EMAC1_PHYISOLATE on TEMAC instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", EMAC1_PHYISOLATE); + $finish; + end + endcase + + case (EMAC1_PHYINITAUTONEG_ENABLE) + "FALSE" : EMAC1_PHYINITAUTONEG_ENABLE_BINARY = 1'b0; + "TRUE" : EMAC1_PHYINITAUTONEG_ENABLE_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute EMAC1_PHYINITAUTONEG_ENABLE on TEMAC instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", EMAC1_PHYINITAUTONEG_ENABLE); + $finish; + end + endcase + + case (EMAC1_PHYRESET) + "FALSE" : EMAC1_PHYRESET_BINARY = 1'b0; + "TRUE" : EMAC1_PHYRESET_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute EMAC1_PHYRESET on TEMAC instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", EMAC1_PHYRESET); + $finish; + end + endcase + + case (EMAC1_CONFIGVEC_79) + "FALSE" : EMAC1_CONFIGVEC_79_BINARY = 1'b0; + "TRUE" : EMAC1_CONFIGVEC_79_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute EMAC1_CONFIGVEC_79 on TEMAC instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", EMAC1_CONFIGVEC_79); + $finish; + end + endcase + + case (EMAC1_UNIDIRECTION_ENABLE) + "FALSE" : EMAC1_UNIDIRECTION_ENABLE_BINARY = 1'b0; + "TRUE" : EMAC1_UNIDIRECTION_ENABLE_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute EMAC1_UNIDIRECTION_ENABLE on TEMAC instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", EMAC1_UNIDIRECTION_ENABLE); + $finish; + end + endcase + + case (EMAC1_GTLOOPBACK) + "FALSE" : EMAC1_GTLOOPBACK_BINARY = 1'b0; + "TRUE" : EMAC1_GTLOOPBACK_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute EMAC1_GTLOOPBACK on TEMAC instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", EMAC1_GTLOOPBACK); + $finish; + end + endcase + + case (EMAC1_BYTEPHY) + "FALSE" : EMAC1_BYTEPHY_BINARY = 1'b0; + "TRUE" : EMAC1_BYTEPHY_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute EMAC1_BYTEPHY on TEMAC instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", EMAC1_BYTEPHY); + $finish; + end + endcase + + case (EMAC1_USECLKEN) + "FALSE" : EMAC1_USECLKEN_BINARY = 1'b0; + "TRUE" : EMAC1_USECLKEN_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute EMAC1_USECLKEN on TEMAC instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", EMAC1_USECLKEN); + $finish; + end + endcase + +end + +wire DCRHOSTDONEIR_delay; +wire EMAC0CLIENTANINTERRUPT_delay; +wire EMAC0CLIENTRXBADFRAME_delay; +wire EMAC0CLIENTRXCLIENTCLKOUT_delay; +wire EMAC0CLIENTRXDVLDMSW_delay; +wire EMAC0CLIENTRXDVLD_delay; +wire EMAC0CLIENTRXFRAMEDROP_delay; +wire EMAC0CLIENTRXGOODFRAME_delay; +wire EMAC0CLIENTRXSTATSBYTEVLD_delay; +wire EMAC0CLIENTRXSTATSVLD_delay; +wire EMAC0CLIENTTXACK_delay; +wire EMAC0CLIENTTXCLIENTCLKOUT_delay; +wire EMAC0CLIENTTXCOLLISION_delay; +wire EMAC0CLIENTTXRETRANSMIT_delay; +wire EMAC0CLIENTTXSTATSBYTEVLD_delay; +wire EMAC0CLIENTTXSTATSVLD_delay; +wire EMAC0CLIENTTXSTATS_delay; +wire EMAC0PHYENCOMMAALIGN_delay; +wire EMAC0PHYLOOPBACKMSB_delay; +wire EMAC0PHYMCLKOUT_delay; +wire EMAC0PHYMDOUT_delay; +wire EMAC0PHYMDTRI_delay; +wire EMAC0PHYMGTRXRESET_delay; +wire EMAC0PHYMGTTXRESET_delay; +wire EMAC0PHYPOWERDOWN_delay; +wire EMAC0PHYSYNCACQSTATUS_delay; +wire EMAC0PHYTXCHARDISPMODE_delay; +wire EMAC0PHYTXCHARDISPVAL_delay; +wire EMAC0PHYTXCHARISK_delay; +wire EMAC0PHYTXCLK_delay; +wire EMAC0PHYTXEN_delay; +wire EMAC0PHYTXER_delay; +wire EMAC0PHYTXGMIIMIICLKOUT_delay; +wire EMAC0SPEEDIS10100_delay; +wire EMAC1CLIENTANINTERRUPT_delay; +wire EMAC1CLIENTRXBADFRAME_delay; +wire EMAC1CLIENTRXCLIENTCLKOUT_delay; +wire EMAC1CLIENTRXDVLDMSW_delay; +wire EMAC1CLIENTRXDVLD_delay; +wire EMAC1CLIENTRXFRAMEDROP_delay; +wire EMAC1CLIENTRXGOODFRAME_delay; +wire EMAC1CLIENTRXSTATSBYTEVLD_delay; +wire EMAC1CLIENTRXSTATSVLD_delay; +wire EMAC1CLIENTTXACK_delay; +wire EMAC1CLIENTTXCLIENTCLKOUT_delay; +wire EMAC1CLIENTTXCOLLISION_delay; +wire EMAC1CLIENTTXRETRANSMIT_delay; +wire EMAC1CLIENTTXSTATSBYTEVLD_delay; +wire EMAC1CLIENTTXSTATSVLD_delay; +wire EMAC1CLIENTTXSTATS_delay; +wire EMAC1PHYENCOMMAALIGN_delay; +wire EMAC1PHYLOOPBACKMSB_delay; +wire EMAC1PHYMCLKOUT_delay; +wire EMAC1PHYMDOUT_delay; +wire EMAC1PHYMDTRI_delay; +wire EMAC1PHYMGTRXRESET_delay; +wire EMAC1PHYMGTTXRESET_delay; +wire EMAC1PHYPOWERDOWN_delay; +wire EMAC1PHYSYNCACQSTATUS_delay; +wire EMAC1PHYTXCHARDISPMODE_delay; +wire EMAC1PHYTXCHARDISPVAL_delay; +wire EMAC1PHYTXCHARISK_delay; +wire EMAC1PHYTXCLK_delay; +wire EMAC1PHYTXEN_delay; +wire EMAC1PHYTXER_delay; +wire EMAC1PHYTXGMIIMIICLKOUT_delay; +wire EMAC1SPEEDIS10100_delay; +wire EMACDCRACK_delay; +wire HOSTMIIMRDY_delay; +wire [0:31] EMACDCRDBUS_delay; +wire [15:0] EMAC0CLIENTRXD_delay; +wire [15:0] EMAC1CLIENTRXD_delay; +wire [31:0] HOSTRDDATA_delay; +wire [6:0] EMAC0CLIENTRXSTATS_delay; +wire [6:0] EMAC1CLIENTRXSTATS_delay; +wire [7:0] EMAC0PHYTXD_delay; +wire [7:0] EMAC1PHYTXD_delay; + +wire CLIENTEMAC0DCMLOCKED_delay; +wire CLIENTEMAC0PAUSEREQ_delay; +wire CLIENTEMAC0RXCLIENTCLKIN_delay; +wire CLIENTEMAC0TXCLIENTCLKIN_delay; +wire CLIENTEMAC0TXDVLDMSW_delay; +wire CLIENTEMAC0TXDVLD_delay; +wire CLIENTEMAC0TXFIRSTBYTE_delay; +wire CLIENTEMAC0TXUNDERRUN_delay; +wire CLIENTEMAC1DCMLOCKED_delay; +wire CLIENTEMAC1PAUSEREQ_delay; +wire CLIENTEMAC1RXCLIENTCLKIN_delay; +wire CLIENTEMAC1TXCLIENTCLKIN_delay; +wire CLIENTEMAC1TXDVLDMSW_delay; +wire CLIENTEMAC1TXDVLD_delay; +wire CLIENTEMAC1TXFIRSTBYTE_delay; +wire CLIENTEMAC1TXUNDERRUN_delay; +wire DCREMACCLK_delay; +wire DCREMACENABLE_delay; +wire DCREMACREAD_delay; +wire DCREMACWRITE_delay; +wire HOSTCLK_delay; +wire HOSTEMAC1SEL_delay; +wire HOSTMIIMSEL_delay; +wire HOSTREQ_delay; +wire PHYEMAC0COL_delay; +wire PHYEMAC0CRS_delay; +wire PHYEMAC0GTXCLK_delay; +wire PHYEMAC0MCLKIN_delay; +wire PHYEMAC0MDIN_delay; +wire PHYEMAC0MIITXCLK_delay; +wire PHYEMAC0RXBUFERR_delay; +wire PHYEMAC0RXCHARISCOMMA_delay; +wire PHYEMAC0RXCHARISK_delay; +wire PHYEMAC0RXCHECKINGCRC_delay; +wire PHYEMAC0RXCLK_delay; +wire PHYEMAC0RXCOMMADET_delay; +wire PHYEMAC0RXDISPERR_delay; +wire PHYEMAC0RXDV_delay; +wire PHYEMAC0RXER_delay; +wire PHYEMAC0RXNOTINTABLE_delay; +wire PHYEMAC0RXRUNDISP_delay; +wire PHYEMAC0SIGNALDET_delay; +wire PHYEMAC0TXBUFERR_delay; +wire PHYEMAC0TXGMIIMIICLKIN_delay; +wire PHYEMAC1COL_delay; +wire PHYEMAC1CRS_delay; +wire PHYEMAC1GTXCLK_delay; +wire PHYEMAC1MCLKIN_delay; +wire PHYEMAC1MDIN_delay; +wire PHYEMAC1MIITXCLK_delay; +wire PHYEMAC1RXBUFERR_delay; +wire PHYEMAC1RXCHARISCOMMA_delay; +wire PHYEMAC1RXCHARISK_delay; +wire PHYEMAC1RXCHECKINGCRC_delay; +wire PHYEMAC1RXCLK_delay; +wire PHYEMAC1RXCOMMADET_delay; +wire PHYEMAC1RXDISPERR_delay; +wire PHYEMAC1RXDV_delay; +wire PHYEMAC1RXER_delay; +wire PHYEMAC1RXNOTINTABLE_delay; +wire PHYEMAC1RXRUNDISP_delay; +wire PHYEMAC1SIGNALDET_delay; +wire PHYEMAC1TXBUFERR_delay; +wire PHYEMAC1TXGMIIMIICLKIN_delay; +wire RESET_delay; +wire [0:31] DCREMACDBUS_delay; +wire [0:9] DCREMACABUS_delay; +wire [15:0] CLIENTEMAC0PAUSEVAL_delay; +wire [15:0] CLIENTEMAC0TXD_delay; +wire [15:0] CLIENTEMAC1PAUSEVAL_delay; +wire [15:0] CLIENTEMAC1TXD_delay; +wire [1:0] HOSTOPCODE_delay; +wire [1:0] PHYEMAC0RXBUFSTATUS_delay; +wire [1:0] PHYEMAC0RXLOSSOFSYNC_delay; +wire [1:0] PHYEMAC1RXBUFSTATUS_delay; +wire [1:0] PHYEMAC1RXLOSSOFSYNC_delay; +wire [2:0] PHYEMAC0RXCLKCORCNT_delay; +wire [2:0] PHYEMAC1RXCLKCORCNT_delay; +wire [31:0] HOSTWRDATA_delay; +wire [4:0] PHYEMAC0PHYAD_delay; +wire [4:0] PHYEMAC1PHYAD_delay; +wire [7:0] CLIENTEMAC0TXIFGDELAY_delay; +wire [7:0] CLIENTEMAC1TXIFGDELAY_delay; +wire [7:0] PHYEMAC0RXD_delay; +wire [7:0] PHYEMAC1RXD_delay; +wire [9:0] HOSTADDR_delay; + +assign #(CLK_DELAY) EMAC0CLIENTRXCLIENTCLKOUT = EMAC0CLIENTRXCLIENTCLKOUT_delay; +assign #(CLK_DELAY) EMAC0CLIENTTXCLIENTCLKOUT = EMAC0CLIENTTXCLIENTCLKOUT_delay; +assign #(CLK_DELAY) EMAC0PHYMCLKOUT = EMAC0PHYMCLKOUT_delay; +assign #(CLK_DELAY) EMAC0PHYTXCLK = EMAC0PHYTXCLK_delay; +assign #(CLK_DELAY) EMAC0PHYTXGMIIMIICLKOUT = EMAC0PHYTXGMIIMIICLKOUT_delay; +assign #(CLK_DELAY) EMAC1CLIENTRXCLIENTCLKOUT = EMAC1CLIENTRXCLIENTCLKOUT_delay; +assign #(CLK_DELAY) EMAC1CLIENTTXCLIENTCLKOUT = EMAC1CLIENTTXCLIENTCLKOUT_delay; +assign #(CLK_DELAY) EMAC1PHYMCLKOUT = EMAC1PHYMCLKOUT_delay; +assign #(CLK_DELAY) EMAC1PHYTXCLK = EMAC1PHYTXCLK_delay; +assign #(CLK_DELAY) EMAC1PHYTXGMIIMIICLKOUT = EMAC1PHYTXGMIIMIICLKOUT_delay; + +assign #(out_delay) DCRHOSTDONEIR = DCRHOSTDONEIR_delay; +assign #(out_delay) EMAC0CLIENTANINTERRUPT = EMAC0CLIENTANINTERRUPT_delay; +assign #(out_delay) EMAC0CLIENTRXBADFRAME = EMAC0CLIENTRXBADFRAME_delay; +assign #(out_delay) EMAC0CLIENTRXD = EMAC0CLIENTRXD_delay; +assign #(out_delay) EMAC0CLIENTRXDVLD = EMAC0CLIENTRXDVLD_delay; +assign #(out_delay) EMAC0CLIENTRXDVLDMSW = EMAC0CLIENTRXDVLDMSW_delay; +assign #(out_delay) EMAC0CLIENTRXFRAMEDROP = EMAC0CLIENTRXFRAMEDROP_delay; +assign #(out_delay) EMAC0CLIENTRXGOODFRAME = EMAC0CLIENTRXGOODFRAME_delay; +assign #(out_delay) EMAC0CLIENTRXSTATS = EMAC0CLIENTRXSTATS_delay; +assign #(out_delay) EMAC0CLIENTRXSTATSBYTEVLD = EMAC0CLIENTRXSTATSBYTEVLD_delay; +assign #(out_delay) EMAC0CLIENTRXSTATSVLD = EMAC0CLIENTRXSTATSVLD_delay; +assign #(out_delay) EMAC0CLIENTTXACK = EMAC0CLIENTTXACK_delay; +assign #(out_delay) EMAC0CLIENTTXCOLLISION = EMAC0CLIENTTXCOLLISION_delay; +assign #(out_delay) EMAC0CLIENTTXRETRANSMIT = EMAC0CLIENTTXRETRANSMIT_delay; +assign #(out_delay) EMAC0CLIENTTXSTATS = EMAC0CLIENTTXSTATS_delay; +assign #(out_delay) EMAC0CLIENTTXSTATSBYTEVLD = EMAC0CLIENTTXSTATSBYTEVLD_delay; +assign #(out_delay) EMAC0CLIENTTXSTATSVLD = EMAC0CLIENTTXSTATSVLD_delay; +assign #(out_delay) EMAC0PHYENCOMMAALIGN = EMAC0PHYENCOMMAALIGN_delay; +assign #(out_delay) EMAC0PHYLOOPBACKMSB = EMAC0PHYLOOPBACKMSB_delay; +assign #(out_delay) EMAC0PHYMDOUT = EMAC0PHYMDOUT_delay; +assign #(out_delay) EMAC0PHYMDTRI = EMAC0PHYMDTRI_delay; +assign #(out_delay) EMAC0PHYMGTRXRESET = EMAC0PHYMGTRXRESET_delay; +assign #(out_delay) EMAC0PHYMGTTXRESET = EMAC0PHYMGTTXRESET_delay; +assign #(out_delay) EMAC0PHYPOWERDOWN = EMAC0PHYPOWERDOWN_delay; +assign #(out_delay) EMAC0PHYSYNCACQSTATUS = EMAC0PHYSYNCACQSTATUS_delay; +assign #(out_delay) EMAC0PHYTXCHARDISPMODE = EMAC0PHYTXCHARDISPMODE_delay; +assign #(out_delay) EMAC0PHYTXCHARDISPVAL = EMAC0PHYTXCHARDISPVAL_delay; +assign #(out_delay) EMAC0PHYTXCHARISK = EMAC0PHYTXCHARISK_delay; +assign #(out_delay) EMAC0PHYTXD = EMAC0PHYTXD_delay; +assign #(out_delay) EMAC0PHYTXEN = EMAC0PHYTXEN_delay; +assign #(out_delay) EMAC0PHYTXER = EMAC0PHYTXER_delay; +assign #(out_delay) EMAC0SPEEDIS10100 = EMAC0SPEEDIS10100_delay; +assign #(out_delay) EMAC1CLIENTANINTERRUPT = EMAC1CLIENTANINTERRUPT_delay; +assign #(out_delay) EMAC1CLIENTRXBADFRAME = EMAC1CLIENTRXBADFRAME_delay; +assign #(out_delay) EMAC1CLIENTRXD = EMAC1CLIENTRXD_delay; +assign #(out_delay) EMAC1CLIENTRXDVLD = EMAC1CLIENTRXDVLD_delay; +assign #(out_delay) EMAC1CLIENTRXDVLDMSW = EMAC1CLIENTRXDVLDMSW_delay; +assign #(out_delay) EMAC1CLIENTRXFRAMEDROP = EMAC1CLIENTRXFRAMEDROP_delay; +assign #(out_delay) EMAC1CLIENTRXGOODFRAME = EMAC1CLIENTRXGOODFRAME_delay; +assign #(out_delay) EMAC1CLIENTRXSTATS = EMAC1CLIENTRXSTATS_delay; +assign #(out_delay) EMAC1CLIENTRXSTATSBYTEVLD = EMAC1CLIENTRXSTATSBYTEVLD_delay; +assign #(out_delay) EMAC1CLIENTRXSTATSVLD = EMAC1CLIENTRXSTATSVLD_delay; +assign #(out_delay) EMAC1CLIENTTXACK = EMAC1CLIENTTXACK_delay; +assign #(out_delay) EMAC1CLIENTTXCOLLISION = EMAC1CLIENTTXCOLLISION_delay; +assign #(out_delay) EMAC1CLIENTTXRETRANSMIT = EMAC1CLIENTTXRETRANSMIT_delay; +assign #(out_delay) EMAC1CLIENTTXSTATS = EMAC1CLIENTTXSTATS_delay; +assign #(out_delay) EMAC1CLIENTTXSTATSBYTEVLD = EMAC1CLIENTTXSTATSBYTEVLD_delay; +assign #(out_delay) EMAC1CLIENTTXSTATSVLD = EMAC1CLIENTTXSTATSVLD_delay; +assign #(out_delay) EMAC1PHYENCOMMAALIGN = EMAC1PHYENCOMMAALIGN_delay; +assign #(out_delay) EMAC1PHYLOOPBACKMSB = EMAC1PHYLOOPBACKMSB_delay; +assign #(out_delay) EMAC1PHYMDOUT = EMAC1PHYMDOUT_delay; +assign #(out_delay) EMAC1PHYMDTRI = EMAC1PHYMDTRI_delay; +assign #(out_delay) EMAC1PHYMGTRXRESET = EMAC1PHYMGTRXRESET_delay; +assign #(out_delay) EMAC1PHYMGTTXRESET = EMAC1PHYMGTTXRESET_delay; +assign #(out_delay) EMAC1PHYPOWERDOWN = EMAC1PHYPOWERDOWN_delay; +assign #(out_delay) EMAC1PHYSYNCACQSTATUS = EMAC1PHYSYNCACQSTATUS_delay; +assign #(out_delay) EMAC1PHYTXCHARDISPMODE = EMAC1PHYTXCHARDISPMODE_delay; +assign #(out_delay) EMAC1PHYTXCHARDISPVAL = EMAC1PHYTXCHARDISPVAL_delay; +assign #(out_delay) EMAC1PHYTXCHARISK = EMAC1PHYTXCHARISK_delay; +assign #(out_delay) EMAC1PHYTXD = EMAC1PHYTXD_delay; +assign #(out_delay) EMAC1PHYTXEN = EMAC1PHYTXEN_delay; +assign #(out_delay) EMAC1PHYTXER = EMAC1PHYTXER_delay; +assign #(out_delay) EMAC1SPEEDIS10100 = EMAC1SPEEDIS10100_delay; +assign #(out_delay) EMACDCRACK = EMACDCRACK_delay; +assign #(out_delay) EMACDCRDBUS = EMACDCRDBUS_delay; +assign #(out_delay) HOSTMIIMRDY = HOSTMIIMRDY_delay; +assign #(out_delay) HOSTRDDATA = HOSTRDDATA_delay; + +assign #(CLK_DELAY) CLIENTEMAC0RXCLIENTCLKIN_delay = CLIENTEMAC0RXCLIENTCLKIN; +assign #(CLK_DELAY) CLIENTEMAC0TXCLIENTCLKIN_delay = CLIENTEMAC0TXCLIENTCLKIN; +assign #(CLK_DELAY) CLIENTEMAC1RXCLIENTCLKIN_delay = CLIENTEMAC1RXCLIENTCLKIN; +assign #(CLK_DELAY) CLIENTEMAC1TXCLIENTCLKIN_delay = CLIENTEMAC1TXCLIENTCLKIN; +assign #(CLK_DELAY) DCREMACCLK_delay = DCREMACCLK; +assign #(CLK_DELAY) HOSTCLK_delay = HOSTCLK; +assign #(CLK_DELAY) PHYEMAC0GTXCLK_delay = PHYEMAC0GTXCLK; +assign #(CLK_DELAY) PHYEMAC0MCLKIN_delay = PHYEMAC0MCLKIN; +assign #(EMAC0MIITXCLK_DELAY) PHYEMAC0MIITXCLK_delay = PHYEMAC0MIITXCLK; +assign #(CLK_DELAY) PHYEMAC0RXCLK_delay = PHYEMAC0RXCLK; +assign #(CLK_DELAY) PHYEMAC0TXGMIIMIICLKIN_delay = PHYEMAC0TXGMIIMIICLKIN; +assign #(CLK_DELAY) PHYEMAC1GTXCLK_delay = PHYEMAC1GTXCLK; +assign #(CLK_DELAY) PHYEMAC1MCLKIN_delay = PHYEMAC1MCLKIN; +assign #(EMAC1MIITXCLK_DELAY) PHYEMAC1MIITXCLK_delay = PHYEMAC1MIITXCLK; +assign #(CLK_DELAY) PHYEMAC1RXCLK_delay = PHYEMAC1RXCLK; +assign #(CLK_DELAY) PHYEMAC1TXGMIIMIICLKIN_delay = PHYEMAC1TXGMIIMIICLKIN; + +assign #(in_delay) CLIENTEMAC0DCMLOCKED_delay = CLIENTEMAC0DCMLOCKED; +assign #(in_delay) CLIENTEMAC0PAUSEREQ_delay = CLIENTEMAC0PAUSEREQ; +assign #(in_delay) CLIENTEMAC0PAUSEVAL_delay = CLIENTEMAC0PAUSEVAL; +assign #(in_delay) CLIENTEMAC0TXDVLDMSW_delay = CLIENTEMAC0TXDVLDMSW; +assign #(in_delay) CLIENTEMAC0TXDVLD_delay = CLIENTEMAC0TXDVLD; +assign #(in_delay) CLIENTEMAC0TXD_delay = CLIENTEMAC0TXD; +assign #(in_delay) CLIENTEMAC0TXFIRSTBYTE_delay = CLIENTEMAC0TXFIRSTBYTE; +assign #(in_delay) CLIENTEMAC0TXIFGDELAY_delay = CLIENTEMAC0TXIFGDELAY; +assign #(in_delay) CLIENTEMAC0TXUNDERRUN_delay = CLIENTEMAC0TXUNDERRUN; +assign #(in_delay) CLIENTEMAC1DCMLOCKED_delay = CLIENTEMAC1DCMLOCKED; +assign #(in_delay) CLIENTEMAC1PAUSEREQ_delay = CLIENTEMAC1PAUSEREQ; +assign #(in_delay) CLIENTEMAC1PAUSEVAL_delay = CLIENTEMAC1PAUSEVAL; +assign #(in_delay) CLIENTEMAC1TXDVLDMSW_delay = CLIENTEMAC1TXDVLDMSW; +assign #(in_delay) CLIENTEMAC1TXDVLD_delay = CLIENTEMAC1TXDVLD; +assign #(in_delay) CLIENTEMAC1TXD_delay = CLIENTEMAC1TXD; +assign #(in_delay) CLIENTEMAC1TXFIRSTBYTE_delay = CLIENTEMAC1TXFIRSTBYTE; +assign #(in_delay) CLIENTEMAC1TXIFGDELAY_delay = CLIENTEMAC1TXIFGDELAY; +assign #(in_delay) CLIENTEMAC1TXUNDERRUN_delay = CLIENTEMAC1TXUNDERRUN; +assign #(in_delay) DCREMACABUS_delay = DCREMACABUS; +assign #(in_delay) DCREMACDBUS_delay = DCREMACDBUS; +assign #(in_delay) DCREMACENABLE_delay = DCREMACENABLE; +assign #(in_delay) DCREMACREAD_delay = DCREMACREAD; +assign #(in_delay) DCREMACWRITE_delay = DCREMACWRITE; +assign #(in_delay) HOSTADDR_delay = HOSTADDR; +assign #(in_delay) HOSTEMAC1SEL_delay = HOSTEMAC1SEL; +assign #(in_delay) HOSTMIIMSEL_delay = HOSTMIIMSEL; +assign #(in_delay) HOSTOPCODE_delay = HOSTOPCODE; +assign #(in_delay) HOSTREQ_delay = HOSTREQ; +assign #(in_delay) HOSTWRDATA_delay = HOSTWRDATA; +assign #(in_delay) PHYEMAC0COL_delay = PHYEMAC0COL; +assign #(in_delay) PHYEMAC0CRS_delay = PHYEMAC0CRS; +assign #(in_delay) PHYEMAC0MDIN_delay = PHYEMAC0MDIN; +assign #(in_delay) PHYEMAC0PHYAD_delay = PHYEMAC0PHYAD; +assign #(in_delay) PHYEMAC0RXBUFERR_delay = PHYEMAC0RXBUFERR; +assign #(in_delay) PHYEMAC0RXBUFSTATUS_delay = PHYEMAC0RXBUFSTATUS; +assign #(in_delay) PHYEMAC0RXCHARISCOMMA_delay = PHYEMAC0RXCHARISCOMMA; +assign #(in_delay) PHYEMAC0RXCHARISK_delay = PHYEMAC0RXCHARISK; +assign #(in_delay) PHYEMAC0RXCHECKINGCRC_delay = PHYEMAC0RXCHECKINGCRC; +assign #(in_delay) PHYEMAC0RXCLKCORCNT_delay = PHYEMAC0RXCLKCORCNT; +assign #(in_delay) PHYEMAC0RXCOMMADET_delay = PHYEMAC0RXCOMMADET; +assign #(in_delay) PHYEMAC0RXDISPERR_delay = PHYEMAC0RXDISPERR; +assign #(in_delay) PHYEMAC0RXDV_delay = PHYEMAC0RXDV; +assign #(in_delay) PHYEMAC0RXD_delay = PHYEMAC0RXD; +assign #(in_delay) PHYEMAC0RXER_delay = PHYEMAC0RXER; +assign #(in_delay) PHYEMAC0RXLOSSOFSYNC_delay = PHYEMAC0RXLOSSOFSYNC; +assign #(in_delay) PHYEMAC0RXNOTINTABLE_delay = PHYEMAC0RXNOTINTABLE; +assign #(in_delay) PHYEMAC0RXRUNDISP_delay = PHYEMAC0RXRUNDISP; +assign #(in_delay) PHYEMAC0SIGNALDET_delay = PHYEMAC0SIGNALDET; +assign #(in_delay) PHYEMAC0TXBUFERR_delay = PHYEMAC0TXBUFERR; +assign #(in_delay) PHYEMAC1COL_delay = PHYEMAC1COL; +assign #(in_delay) PHYEMAC1CRS_delay = PHYEMAC1CRS; +assign #(in_delay) PHYEMAC1MDIN_delay = PHYEMAC1MDIN; +assign #(in_delay) PHYEMAC1PHYAD_delay = PHYEMAC1PHYAD; +assign #(in_delay) PHYEMAC1RXBUFERR_delay = PHYEMAC1RXBUFERR; +assign #(in_delay) PHYEMAC1RXBUFSTATUS_delay = PHYEMAC1RXBUFSTATUS; +assign #(in_delay) PHYEMAC1RXCHARISCOMMA_delay = PHYEMAC1RXCHARISCOMMA; +assign #(in_delay) PHYEMAC1RXCHARISK_delay = PHYEMAC1RXCHARISK; +assign #(in_delay) PHYEMAC1RXCHECKINGCRC_delay = PHYEMAC1RXCHECKINGCRC; +assign #(in_delay) PHYEMAC1RXCLKCORCNT_delay = PHYEMAC1RXCLKCORCNT; +assign #(in_delay) PHYEMAC1RXCOMMADET_delay = PHYEMAC1RXCOMMADET; +assign #(in_delay) PHYEMAC1RXDISPERR_delay = PHYEMAC1RXDISPERR; +assign #(in_delay) PHYEMAC1RXDV_delay = PHYEMAC1RXDV; +assign #(in_delay) PHYEMAC1RXD_delay = PHYEMAC1RXD; +assign #(in_delay) PHYEMAC1RXER_delay = PHYEMAC1RXER; +assign #(in_delay) PHYEMAC1RXLOSSOFSYNC_delay = PHYEMAC1RXLOSSOFSYNC; +assign #(in_delay) PHYEMAC1RXNOTINTABLE_delay = PHYEMAC1RXNOTINTABLE; +assign #(in_delay) PHYEMAC1RXRUNDISP_delay = PHYEMAC1RXRUNDISP; +assign #(in_delay) PHYEMAC1SIGNALDET_delay = PHYEMAC1SIGNALDET; +assign #(in_delay) PHYEMAC1TXBUFERR_delay = PHYEMAC1TXBUFERR; +assign #(in_delay) RESET_delay = RESET; + +TEMAC_SWIFT temac_swift_1 ( + .EMAC0_1000BASEX_ENABLE (EMAC0_1000BASEX_ENABLE_BINARY), + .EMAC0_ADDRFILTER_ENABLE (EMAC0_ADDRFILTER_ENABLE_BINARY), + .EMAC0_BYTEPHY (EMAC0_BYTEPHY_BINARY), + .EMAC0_CONFIGVEC_79 (EMAC0_CONFIGVEC_79_BINARY), + .EMAC0_DCRBASEADDR (EMAC0_DCRBASEADDR), + .EMAC0_GTLOOPBACK (EMAC0_GTLOOPBACK_BINARY), + .EMAC0_HOST_ENABLE (EMAC0_HOST_ENABLE_BINARY), + .EMAC0_LINKTIMERVAL (EMAC0_LINKTIMERVAL), + .EMAC0_LTCHECK_DISABLE (EMAC0_LTCHECK_DISABLE_BINARY), + .EMAC0_MDIO_ENABLE (EMAC0_MDIO_ENABLE_BINARY), + .EMAC0_PAUSEADDR (EMAC0_PAUSEADDR), + .EMAC0_PHYINITAUTONEG_ENABLE (EMAC0_PHYINITAUTONEG_ENABLE_BINARY), + .EMAC0_PHYISOLATE (EMAC0_PHYISOLATE_BINARY), + .EMAC0_PHYLOOPBACKMSB (EMAC0_PHYLOOPBACKMSB_BINARY), + .EMAC0_PHYPOWERDOWN (EMAC0_PHYPOWERDOWN_BINARY), + .EMAC0_PHYRESET (EMAC0_PHYRESET_BINARY), + .EMAC0_RGMII_ENABLE (EMAC0_RGMII_ENABLE_BINARY), + .EMAC0_RX16BITCLIENT_ENABLE (EMAC0_RX16BITCLIENT_ENABLE_BINARY), + .EMAC0_RXFLOWCTRL_ENABLE (EMAC0_RXFLOWCTRL_ENABLE_BINARY), + .EMAC0_RXHALFDUPLEX (EMAC0_RXHALFDUPLEX_BINARY), + .EMAC0_RXINBANDFCS_ENABLE (EMAC0_RXINBANDFCS_ENABLE_BINARY), + .EMAC0_RXJUMBOFRAME_ENABLE (EMAC0_RXJUMBOFRAME_ENABLE_BINARY), + .EMAC0_RXRESET (EMAC0_RXRESET_BINARY), + .EMAC0_RXVLAN_ENABLE (EMAC0_RXVLAN_ENABLE_BINARY), + .EMAC0_RX_ENABLE (EMAC0_RX_ENABLE_BINARY), + .EMAC0_SGMII_ENABLE (EMAC0_SGMII_ENABLE_BINARY), + .EMAC0_SPEED_LSB (EMAC0_SPEED_LSB_BINARY), + .EMAC0_SPEED_MSB (EMAC0_SPEED_MSB_BINARY), + .EMAC0_TX16BITCLIENT_ENABLE (EMAC0_TX16BITCLIENT_ENABLE_BINARY), + .EMAC0_TXFLOWCTRL_ENABLE (EMAC0_TXFLOWCTRL_ENABLE_BINARY), + .EMAC0_TXHALFDUPLEX (EMAC0_TXHALFDUPLEX_BINARY), + .EMAC0_TXIFGADJUST_ENABLE (EMAC0_TXIFGADJUST_ENABLE_BINARY), + .EMAC0_TXINBANDFCS_ENABLE (EMAC0_TXINBANDFCS_ENABLE_BINARY), + .EMAC0_TXJUMBOFRAME_ENABLE (EMAC0_TXJUMBOFRAME_ENABLE_BINARY), + .EMAC0_TXRESET (EMAC0_TXRESET_BINARY), + .EMAC0_TXVLAN_ENABLE (EMAC0_TXVLAN_ENABLE_BINARY), + .EMAC0_TX_ENABLE (EMAC0_TX_ENABLE_BINARY), + .EMAC0_UNICASTADDR (EMAC0_UNICASTADDR), + .EMAC0_UNIDIRECTION_ENABLE (EMAC0_UNIDIRECTION_ENABLE_BINARY), + .EMAC0_USECLKEN (EMAC0_USECLKEN_BINARY), + .EMAC1_1000BASEX_ENABLE (EMAC1_1000BASEX_ENABLE_BINARY), + .EMAC1_ADDRFILTER_ENABLE (EMAC1_ADDRFILTER_ENABLE_BINARY), + .EMAC1_BYTEPHY (EMAC1_BYTEPHY_BINARY), + .EMAC1_CONFIGVEC_79 (EMAC1_CONFIGVEC_79_BINARY), + .EMAC1_DCRBASEADDR (EMAC1_DCRBASEADDR), + .EMAC1_GTLOOPBACK (EMAC1_GTLOOPBACK_BINARY), + .EMAC1_HOST_ENABLE (EMAC1_HOST_ENABLE_BINARY), + .EMAC1_LINKTIMERVAL (EMAC1_LINKTIMERVAL), + .EMAC1_LTCHECK_DISABLE (EMAC1_LTCHECK_DISABLE_BINARY), + .EMAC1_MDIO_ENABLE (EMAC1_MDIO_ENABLE_BINARY), + .EMAC1_PAUSEADDR (EMAC1_PAUSEADDR), + .EMAC1_PHYINITAUTONEG_ENABLE (EMAC1_PHYINITAUTONEG_ENABLE_BINARY), + .EMAC1_PHYISOLATE (EMAC1_PHYISOLATE_BINARY), + .EMAC1_PHYLOOPBACKMSB (EMAC1_PHYLOOPBACKMSB_BINARY), + .EMAC1_PHYPOWERDOWN (EMAC1_PHYPOWERDOWN_BINARY), + .EMAC1_PHYRESET (EMAC1_PHYRESET_BINARY), + .EMAC1_RGMII_ENABLE (EMAC1_RGMII_ENABLE_BINARY), + .EMAC1_RX16BITCLIENT_ENABLE (EMAC1_RX16BITCLIENT_ENABLE_BINARY), + .EMAC1_RXFLOWCTRL_ENABLE (EMAC1_RXFLOWCTRL_ENABLE_BINARY), + .EMAC1_RXHALFDUPLEX (EMAC1_RXHALFDUPLEX_BINARY), + .EMAC1_RXINBANDFCS_ENABLE (EMAC1_RXINBANDFCS_ENABLE_BINARY), + .EMAC1_RXJUMBOFRAME_ENABLE (EMAC1_RXJUMBOFRAME_ENABLE_BINARY), + .EMAC1_RXRESET (EMAC1_RXRESET_BINARY), + .EMAC1_RXVLAN_ENABLE (EMAC1_RXVLAN_ENABLE_BINARY), + .EMAC1_RX_ENABLE (EMAC1_RX_ENABLE_BINARY), + .EMAC1_SGMII_ENABLE (EMAC1_SGMII_ENABLE_BINARY), + .EMAC1_SPEED_LSB (EMAC1_SPEED_LSB_BINARY), + .EMAC1_SPEED_MSB (EMAC1_SPEED_MSB_BINARY), + .EMAC1_TX16BITCLIENT_ENABLE (EMAC1_TX16BITCLIENT_ENABLE_BINARY), + .EMAC1_TXFLOWCTRL_ENABLE (EMAC1_TXFLOWCTRL_ENABLE_BINARY), + .EMAC1_TXHALFDUPLEX (EMAC1_TXHALFDUPLEX_BINARY), + .EMAC1_TXIFGADJUST_ENABLE (EMAC1_TXIFGADJUST_ENABLE_BINARY), + .EMAC1_TXINBANDFCS_ENABLE (EMAC1_TXINBANDFCS_ENABLE_BINARY), + .EMAC1_TXJUMBOFRAME_ENABLE (EMAC1_TXJUMBOFRAME_ENABLE_BINARY), + .EMAC1_TXRESET (EMAC1_TXRESET_BINARY), + .EMAC1_TXVLAN_ENABLE (EMAC1_TXVLAN_ENABLE_BINARY), + .EMAC1_TX_ENABLE (EMAC1_TX_ENABLE_BINARY), + .EMAC1_UNICASTADDR (EMAC1_UNICASTADDR), + .EMAC1_UNIDIRECTION_ENABLE (EMAC1_UNIDIRECTION_ENABLE_BINARY), + .EMAC1_USECLKEN (EMAC1_USECLKEN_BINARY), + + .DCRHOSTDONEIR (DCRHOSTDONEIR_delay), + .EMAC0CLIENTANINTERRUPT (EMAC0CLIENTANINTERRUPT_delay), + .EMAC0CLIENTRXBADFRAME (EMAC0CLIENTRXBADFRAME_delay), + .EMAC0CLIENTRXCLIENTCLKOUT (EMAC0CLIENTRXCLIENTCLKOUT_delay), + .EMAC0CLIENTRXD (EMAC0CLIENTRXD_delay), + .EMAC0CLIENTRXDVLD (EMAC0CLIENTRXDVLD_delay), + .EMAC0CLIENTRXDVLDMSW (EMAC0CLIENTRXDVLDMSW_delay), + .EMAC0CLIENTRXFRAMEDROP (EMAC0CLIENTRXFRAMEDROP_delay), + .EMAC0CLIENTRXGOODFRAME (EMAC0CLIENTRXGOODFRAME_delay), + .EMAC0CLIENTRXSTATS (EMAC0CLIENTRXSTATS_delay), + .EMAC0CLIENTRXSTATSBYTEVLD (EMAC0CLIENTRXSTATSBYTEVLD_delay), + .EMAC0CLIENTRXSTATSVLD (EMAC0CLIENTRXSTATSVLD_delay), + .EMAC0CLIENTTXACK (EMAC0CLIENTTXACK_delay), + .EMAC0CLIENTTXCLIENTCLKOUT (EMAC0CLIENTTXCLIENTCLKOUT_delay), + .EMAC0CLIENTTXCOLLISION (EMAC0CLIENTTXCOLLISION_delay), + .EMAC0CLIENTTXRETRANSMIT (EMAC0CLIENTTXRETRANSMIT_delay), + .EMAC0CLIENTTXSTATS (EMAC0CLIENTTXSTATS_delay), + .EMAC0CLIENTTXSTATSBYTEVLD (EMAC0CLIENTTXSTATSBYTEVLD_delay), + .EMAC0CLIENTTXSTATSVLD (EMAC0CLIENTTXSTATSVLD_delay), + .EMAC0PHYENCOMMAALIGN (EMAC0PHYENCOMMAALIGN_delay), + .EMAC0PHYLOOPBACKMSB (EMAC0PHYLOOPBACKMSB_delay), + .EMAC0PHYMCLKOUT (EMAC0PHYMCLKOUT_delay), + .EMAC0PHYMDOUT (EMAC0PHYMDOUT_delay), + .EMAC0PHYMDTRI (EMAC0PHYMDTRI_delay), + .EMAC0PHYMGTRXRESET (EMAC0PHYMGTRXRESET_delay), + .EMAC0PHYMGTTXRESET (EMAC0PHYMGTTXRESET_delay), + .EMAC0PHYPOWERDOWN (EMAC0PHYPOWERDOWN_delay), + .EMAC0PHYSYNCACQSTATUS (EMAC0PHYSYNCACQSTATUS_delay), + .EMAC0PHYTXCHARDISPMODE (EMAC0PHYTXCHARDISPMODE_delay), + .EMAC0PHYTXCHARDISPVAL (EMAC0PHYTXCHARDISPVAL_delay), + .EMAC0PHYTXCHARISK (EMAC0PHYTXCHARISK_delay), + .EMAC0PHYTXCLK (EMAC0PHYTXCLK_delay), + .EMAC0PHYTXD (EMAC0PHYTXD_delay), + .EMAC0PHYTXEN (EMAC0PHYTXEN_delay), + .EMAC0PHYTXER (EMAC0PHYTXER_delay), + .EMAC0PHYTXGMIIMIICLKOUT (EMAC0PHYTXGMIIMIICLKOUT_delay), + .EMAC0SPEEDIS10100 (EMAC0SPEEDIS10100_delay), + .EMAC1CLIENTANINTERRUPT (EMAC1CLIENTANINTERRUPT_delay), + .EMAC1CLIENTRXBADFRAME (EMAC1CLIENTRXBADFRAME_delay), + .EMAC1CLIENTRXCLIENTCLKOUT (EMAC1CLIENTRXCLIENTCLKOUT_delay), + .EMAC1CLIENTRXD (EMAC1CLIENTRXD_delay), + .EMAC1CLIENTRXDVLD (EMAC1CLIENTRXDVLD_delay), + .EMAC1CLIENTRXDVLDMSW (EMAC1CLIENTRXDVLDMSW_delay), + .EMAC1CLIENTRXFRAMEDROP (EMAC1CLIENTRXFRAMEDROP_delay), + .EMAC1CLIENTRXGOODFRAME (EMAC1CLIENTRXGOODFRAME_delay), + .EMAC1CLIENTRXSTATS (EMAC1CLIENTRXSTATS_delay), + .EMAC1CLIENTRXSTATSBYTEVLD (EMAC1CLIENTRXSTATSBYTEVLD_delay), + .EMAC1CLIENTRXSTATSVLD (EMAC1CLIENTRXSTATSVLD_delay), + .EMAC1CLIENTTXACK (EMAC1CLIENTTXACK_delay), + .EMAC1CLIENTTXCLIENTCLKOUT (EMAC1CLIENTTXCLIENTCLKOUT_delay), + .EMAC1CLIENTTXCOLLISION (EMAC1CLIENTTXCOLLISION_delay), + .EMAC1CLIENTTXRETRANSMIT (EMAC1CLIENTTXRETRANSMIT_delay), + .EMAC1CLIENTTXSTATS (EMAC1CLIENTTXSTATS_delay), + .EMAC1CLIENTTXSTATSBYTEVLD (EMAC1CLIENTTXSTATSBYTEVLD_delay), + .EMAC1CLIENTTXSTATSVLD (EMAC1CLIENTTXSTATSVLD_delay), + .EMAC1PHYENCOMMAALIGN (EMAC1PHYENCOMMAALIGN_delay), + .EMAC1PHYLOOPBACKMSB (EMAC1PHYLOOPBACKMSB_delay), + .EMAC1PHYMCLKOUT (EMAC1PHYMCLKOUT_delay), + .EMAC1PHYMDOUT (EMAC1PHYMDOUT_delay), + .EMAC1PHYMDTRI (EMAC1PHYMDTRI_delay), + .EMAC1PHYMGTRXRESET (EMAC1PHYMGTRXRESET_delay), + .EMAC1PHYMGTTXRESET (EMAC1PHYMGTTXRESET_delay), + .EMAC1PHYPOWERDOWN (EMAC1PHYPOWERDOWN_delay), + .EMAC1PHYSYNCACQSTATUS (EMAC1PHYSYNCACQSTATUS_delay), + .EMAC1PHYTXCHARDISPMODE (EMAC1PHYTXCHARDISPMODE_delay), + .EMAC1PHYTXCHARDISPVAL (EMAC1PHYTXCHARDISPVAL_delay), + .EMAC1PHYTXCHARISK (EMAC1PHYTXCHARISK_delay), + .EMAC1PHYTXCLK (EMAC1PHYTXCLK_delay), + .EMAC1PHYTXD (EMAC1PHYTXD_delay), + .EMAC1PHYTXEN (EMAC1PHYTXEN_delay), + .EMAC1PHYTXER (EMAC1PHYTXER_delay), + .EMAC1PHYTXGMIIMIICLKOUT (EMAC1PHYTXGMIIMIICLKOUT_delay), + .EMAC1SPEEDIS10100 (EMAC1SPEEDIS10100_delay), + .EMACDCRACK (EMACDCRACK_delay), + .EMACDCRDBUS (EMACDCRDBUS_delay), + .HOSTMIIMRDY (HOSTMIIMRDY_delay), + .HOSTRDDATA (HOSTRDDATA_delay), + + .CLIENTEMAC0DCMLOCKED (CLIENTEMAC0DCMLOCKED_delay), + .CLIENTEMAC0PAUSEREQ (CLIENTEMAC0PAUSEREQ_delay), + .CLIENTEMAC0PAUSEVAL (CLIENTEMAC0PAUSEVAL_delay), + .CLIENTEMAC0RXCLIENTCLKIN (CLIENTEMAC0RXCLIENTCLKIN_delay), + .CLIENTEMAC0TXCLIENTCLKIN (CLIENTEMAC0TXCLIENTCLKIN_delay), + .CLIENTEMAC0TXD (CLIENTEMAC0TXD_delay), + .CLIENTEMAC0TXDVLD (CLIENTEMAC0TXDVLD_delay), + .CLIENTEMAC0TXDVLDMSW (CLIENTEMAC0TXDVLDMSW_delay), + .CLIENTEMAC0TXFIRSTBYTE (CLIENTEMAC0TXFIRSTBYTE_delay), + .CLIENTEMAC0TXIFGDELAY (CLIENTEMAC0TXIFGDELAY_delay), + .CLIENTEMAC0TXUNDERRUN (CLIENTEMAC0TXUNDERRUN_delay), + .CLIENTEMAC1DCMLOCKED (CLIENTEMAC1DCMLOCKED_delay), + .CLIENTEMAC1PAUSEREQ (CLIENTEMAC1PAUSEREQ_delay), + .CLIENTEMAC1PAUSEVAL (CLIENTEMAC1PAUSEVAL_delay), + .CLIENTEMAC1RXCLIENTCLKIN (CLIENTEMAC1RXCLIENTCLKIN_delay), + .CLIENTEMAC1TXCLIENTCLKIN (CLIENTEMAC1TXCLIENTCLKIN_delay), + .CLIENTEMAC1TXD (CLIENTEMAC1TXD_delay), + .CLIENTEMAC1TXDVLD (CLIENTEMAC1TXDVLD_delay), + .CLIENTEMAC1TXDVLDMSW (CLIENTEMAC1TXDVLDMSW_delay), + .CLIENTEMAC1TXFIRSTBYTE (CLIENTEMAC1TXFIRSTBYTE_delay), + .CLIENTEMAC1TXIFGDELAY (CLIENTEMAC1TXIFGDELAY_delay), + .CLIENTEMAC1TXUNDERRUN (CLIENTEMAC1TXUNDERRUN_delay), + .DCREMACABUS (DCREMACABUS_delay), + .DCREMACCLK (DCREMACCLK_delay), + .DCREMACDBUS (DCREMACDBUS_delay), + .DCREMACENABLE (DCREMACENABLE_delay), + .DCREMACREAD (DCREMACREAD_delay), + .DCREMACWRITE (DCREMACWRITE_delay), + .HOSTADDR (HOSTADDR_delay), + .HOSTCLK (HOSTCLK_delay), + .HOSTEMAC1SEL (HOSTEMAC1SEL_delay), + .HOSTMIIMSEL (HOSTMIIMSEL_delay), + .HOSTOPCODE (HOSTOPCODE_delay), + .HOSTREQ (HOSTREQ_delay), + .HOSTWRDATA (HOSTWRDATA_delay), + .PHYEMAC0COL (PHYEMAC0COL_delay), + .PHYEMAC0CRS (PHYEMAC0CRS_delay), + .PHYEMAC0GTXCLK (PHYEMAC0GTXCLK_delay), + .PHYEMAC0MCLKIN (PHYEMAC0MCLKIN_delay), + .PHYEMAC0MDIN (PHYEMAC0MDIN_delay), + .PHYEMAC0MIITXCLK (PHYEMAC0MIITXCLK_delay), + .PHYEMAC0PHYAD (PHYEMAC0PHYAD_delay), + .PHYEMAC0RXBUFERR (PHYEMAC0RXBUFERR_delay), + .PHYEMAC0RXBUFSTATUS (PHYEMAC0RXBUFSTATUS_delay), + .PHYEMAC0RXCHARISCOMMA (PHYEMAC0RXCHARISCOMMA_delay), + .PHYEMAC0RXCHARISK (PHYEMAC0RXCHARISK_delay), + .PHYEMAC0RXCHECKINGCRC (PHYEMAC0RXCHECKINGCRC_delay), + .PHYEMAC0RXCLK (PHYEMAC0RXCLK_delay), + .PHYEMAC0RXCLKCORCNT (PHYEMAC0RXCLKCORCNT_delay), + .PHYEMAC0RXCOMMADET (PHYEMAC0RXCOMMADET_delay), + .PHYEMAC0RXD (PHYEMAC0RXD_delay), + .PHYEMAC0RXDISPERR (PHYEMAC0RXDISPERR_delay), + .PHYEMAC0RXDV (PHYEMAC0RXDV_delay), + .PHYEMAC0RXER (PHYEMAC0RXER_delay), + .PHYEMAC0RXLOSSOFSYNC (PHYEMAC0RXLOSSOFSYNC_delay), + .PHYEMAC0RXNOTINTABLE (PHYEMAC0RXNOTINTABLE_delay), + .PHYEMAC0RXRUNDISP (PHYEMAC0RXRUNDISP_delay), + .PHYEMAC0SIGNALDET (PHYEMAC0SIGNALDET_delay), + .PHYEMAC0TXBUFERR (PHYEMAC0TXBUFERR_delay), + .PHYEMAC0TXGMIIMIICLKIN (PHYEMAC0TXGMIIMIICLKIN_delay), + .PHYEMAC1COL (PHYEMAC1COL_delay), + .PHYEMAC1CRS (PHYEMAC1CRS_delay), + .PHYEMAC1GTXCLK (PHYEMAC1GTXCLK_delay), + .PHYEMAC1MCLKIN (PHYEMAC1MCLKIN_delay), + .PHYEMAC1MDIN (PHYEMAC1MDIN_delay), + .PHYEMAC1MIITXCLK (PHYEMAC1MIITXCLK_delay), + .PHYEMAC1PHYAD (PHYEMAC1PHYAD_delay), + .PHYEMAC1RXBUFERR (PHYEMAC1RXBUFERR_delay), + .PHYEMAC1RXBUFSTATUS (PHYEMAC1RXBUFSTATUS_delay), + .PHYEMAC1RXCHARISCOMMA (PHYEMAC1RXCHARISCOMMA_delay), + .PHYEMAC1RXCHARISK (PHYEMAC1RXCHARISK_delay), + .PHYEMAC1RXCHECKINGCRC (PHYEMAC1RXCHECKINGCRC_delay), + .PHYEMAC1RXCLK (PHYEMAC1RXCLK_delay), + .PHYEMAC1RXCLKCORCNT (PHYEMAC1RXCLKCORCNT_delay), + .PHYEMAC1RXCOMMADET (PHYEMAC1RXCOMMADET_delay), + .PHYEMAC1RXD (PHYEMAC1RXD_delay), + .PHYEMAC1RXDISPERR (PHYEMAC1RXDISPERR_delay), + .PHYEMAC1RXDV (PHYEMAC1RXDV_delay), + .PHYEMAC1RXER (PHYEMAC1RXER_delay), + .PHYEMAC1RXLOSSOFSYNC (PHYEMAC1RXLOSSOFSYNC_delay), + .PHYEMAC1RXNOTINTABLE (PHYEMAC1RXNOTINTABLE_delay), + .PHYEMAC1RXRUNDISP (PHYEMAC1RXRUNDISP_delay), + .PHYEMAC1SIGNALDET (PHYEMAC1SIGNALDET_delay), + .PHYEMAC1TXBUFERR (PHYEMAC1TXBUFERR_delay), + .PHYEMAC1TXGMIIMIICLKIN (PHYEMAC1TXGMIIMIICLKIN_delay), + .RESET (RESET_delay) +); + +specify + (CLIENTEMAC0RXCLIENTCLKIN => EMAC0CLIENTRXBADFRAME) = (100, 100); + (CLIENTEMAC0RXCLIENTCLKIN => EMAC0CLIENTRXCLIENTCLKOUT) = (100, 100); + (CLIENTEMAC0RXCLIENTCLKIN => EMAC0CLIENTRXD) = (100, 100); + (CLIENTEMAC0RXCLIENTCLKIN => EMAC0CLIENTRXDVLD) = (100, 100); + (CLIENTEMAC0RXCLIENTCLKIN => EMAC0CLIENTRXDVLDMSW) = (100, 100); + (CLIENTEMAC0RXCLIENTCLKIN => EMAC0CLIENTRXFRAMEDROP) = (100, 100); + (CLIENTEMAC0RXCLIENTCLKIN => EMAC0CLIENTRXGOODFRAME) = (100, 100); + (CLIENTEMAC0RXCLIENTCLKIN => EMAC0CLIENTRXSTATS) = (100, 100); + (CLIENTEMAC0RXCLIENTCLKIN => EMAC0CLIENTRXSTATSBYTEVLD) = (100, 100); + (CLIENTEMAC0RXCLIENTCLKIN => EMAC0CLIENTRXSTATSVLD) = (100, 100); + (CLIENTEMAC0TXCLIENTCLKIN => EMAC0CLIENTTXACK) = (100, 100); + (CLIENTEMAC0TXCLIENTCLKIN => EMAC0CLIENTTXCOLLISION) = (100, 100); + (CLIENTEMAC0TXCLIENTCLKIN => EMAC0CLIENTTXRETRANSMIT) = (100, 100); + (CLIENTEMAC0TXCLIENTCLKIN => EMAC0CLIENTTXSTATS) = (100, 100); + (CLIENTEMAC0TXCLIENTCLKIN => EMAC0CLIENTTXSTATSBYTEVLD) = (100, 100); + (CLIENTEMAC0TXCLIENTCLKIN => EMAC0CLIENTTXSTATSVLD) = (100, 100); + (CLIENTEMAC1RXCLIENTCLKIN => EMAC1CLIENTRXBADFRAME) = (100, 100); + (CLIENTEMAC1RXCLIENTCLKIN => EMAC1CLIENTRXCLIENTCLKOUT) = (100, 100); + (CLIENTEMAC1RXCLIENTCLKIN => EMAC1CLIENTRXD) = (100, 100); + (CLIENTEMAC1RXCLIENTCLKIN => EMAC1CLIENTRXDVLD) = (100, 100); + (CLIENTEMAC1RXCLIENTCLKIN => EMAC1CLIENTRXDVLDMSW) = (100, 100); + (CLIENTEMAC1RXCLIENTCLKIN => EMAC1CLIENTRXFRAMEDROP) = (100, 100); + (CLIENTEMAC1RXCLIENTCLKIN => EMAC1CLIENTRXGOODFRAME) = (100, 100); + (CLIENTEMAC1RXCLIENTCLKIN => EMAC1CLIENTRXSTATS) = (100, 100); + (CLIENTEMAC1RXCLIENTCLKIN => EMAC1CLIENTRXSTATSBYTEVLD) = (100, 100); + (CLIENTEMAC1RXCLIENTCLKIN => EMAC1CLIENTRXSTATSVLD) = (100, 100); + (CLIENTEMAC1TXCLIENTCLKIN => EMAC1CLIENTTXACK) = (100, 100); + (CLIENTEMAC1TXCLIENTCLKIN => EMAC1CLIENTTXCOLLISION) = (100, 100); + (CLIENTEMAC1TXCLIENTCLKIN => EMAC1CLIENTTXRETRANSMIT) = (100, 100); + (CLIENTEMAC1TXCLIENTCLKIN => EMAC1CLIENTTXSTATS) = (100, 100); + (CLIENTEMAC1TXCLIENTCLKIN => EMAC1CLIENTTXSTATSBYTEVLD) = (100, 100); + (CLIENTEMAC1TXCLIENTCLKIN => EMAC1CLIENTTXSTATSVLD) = (100, 100); + (DCREMACCLK => EMACDCRACK) = (100, 100); + (DCREMACCLK => EMACDCRDBUS) = (100, 100); + (HOSTCLK => DCRHOSTDONEIR) = (100, 100); + (HOSTCLK => EMAC0PHYMCLKOUT) = (100, 100); + (HOSTCLK => EMAC0PHYMDOUT) = (100, 100); + (HOSTCLK => EMAC0PHYMDTRI) = (100, 100); + (HOSTCLK => EMAC0SPEEDIS10100) = (100, 100); + (HOSTCLK => EMAC1PHYMCLKOUT) = (100, 100); + (HOSTCLK => EMAC1PHYMDOUT) = (100, 100); + (HOSTCLK => EMAC1PHYMDTRI) = (100, 100); + (HOSTCLK => EMAC1SPEEDIS10100) = (100, 100); + (HOSTCLK => HOSTMIIMRDY) = (100, 100); + (HOSTCLK => HOSTRDDATA) = (100, 100); + (PHYEMAC0GTXCLK => EMAC0CLIENTANINTERRUPT) = (100, 100); + (PHYEMAC0GTXCLK => EMAC0PHYENCOMMAALIGN) = (100, 100); + (PHYEMAC0GTXCLK => EMAC0PHYLOOPBACKMSB) = (100, 100); + (PHYEMAC0GTXCLK => EMAC0PHYMGTRXRESET) = (100, 100); + (PHYEMAC0GTXCLK => EMAC0PHYMGTTXRESET) = (100, 100); + (PHYEMAC0GTXCLK => EMAC0PHYPOWERDOWN) = (100, 100); + (PHYEMAC0GTXCLK => EMAC0PHYSYNCACQSTATUS) = (100, 100); + (PHYEMAC0GTXCLK => EMAC0PHYTXCHARDISPMODE) = (100, 100); + (PHYEMAC0GTXCLK => EMAC0PHYTXCHARDISPVAL) = (100, 100); + (PHYEMAC0GTXCLK => EMAC0PHYTXCHARISK) = (100, 100); + (PHYEMAC0GTXCLK => EMAC0PHYTXCLK) = (100, 100); + (PHYEMAC0GTXCLK => EMAC0PHYTXD) = (100, 100); + (PHYEMAC0GTXCLK => EMAC0PHYTXEN) = (100, 100); + (PHYEMAC0GTXCLK => EMAC0PHYTXER) = (100, 100); + (PHYEMAC0GTXCLK => EMAC0PHYTXGMIIMIICLKOUT) = (100, 100); + (PHYEMAC0TXGMIIMIICLKIN => EMAC0CLIENTTXCLIENTCLKOUT) = (100, 100); + (PHYEMAC1GTXCLK => EMAC1CLIENTANINTERRUPT) = (100, 100); + (PHYEMAC1GTXCLK => EMAC1PHYENCOMMAALIGN) = (100, 100); + (PHYEMAC1GTXCLK => EMAC1PHYLOOPBACKMSB) = (100, 100); + (PHYEMAC1GTXCLK => EMAC1PHYMGTRXRESET) = (100, 100); + (PHYEMAC1GTXCLK => EMAC1PHYMGTTXRESET) = (100, 100); + (PHYEMAC1GTXCLK => EMAC1PHYPOWERDOWN) = (100, 100); + (PHYEMAC1GTXCLK => EMAC1PHYSYNCACQSTATUS) = (100, 100); + (PHYEMAC1GTXCLK => EMAC1PHYTXCHARDISPMODE) = (100, 100); + (PHYEMAC1GTXCLK => EMAC1PHYTXCHARDISPVAL) = (100, 100); + (PHYEMAC1GTXCLK => EMAC1PHYTXCHARISK) = (100, 100); + (PHYEMAC1GTXCLK => EMAC1PHYTXCLK) = (100, 100); + (PHYEMAC1GTXCLK => EMAC1PHYTXD) = (100, 100); + (PHYEMAC1GTXCLK => EMAC1PHYTXEN) = (100, 100); + (PHYEMAC1GTXCLK => EMAC1PHYTXER) = (100, 100); + (PHYEMAC1GTXCLK => EMAC1PHYTXGMIIMIICLKOUT) = (100, 100); + (PHYEMAC1TXGMIIMIICLKIN => EMAC1CLIENTTXCLIENTCLKOUT) = (100, 100); + specparam PATHPULSE$ = 0; +endspecify +endmodule diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/TEMAC_SINGLE.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/TEMAC_SINGLE.v new file mode 100644 index 0000000..e6b55c6 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/TEMAC_SINGLE.v @@ -0,0 +1,1169 @@ +/////////////////////////////////////////////////////// +// Copyright (c) 2009 Xilinx Inc. +// All Right Reserved. +/////////////////////////////////////////////////////// +// +// ____ ___ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / : Tri-Mode Ethernet MAC +// /__/ /\ Filename : TEMAC_SINGLE.v +// \ \ / \ +// \__\/\__ \ +// +// Revision: +// 11/05/07 - CR453443 - Initial version. +// 05/30/08 - CR1014 - Added parameter +// 08/05/08 - CR1014 - EMAC_DCRBASEADDR updated from [7:0] to [0:7] +// 08/25/08 - CR1014 - SWIFT instantiation replaced by B_TEMAC_SINGLE. Added case statement, assign statement for buffers. +// 09/16/08 - CR1014 - Added specify block +// 09/23/08 - CR490337 - assign buffer updates _delay to delay_ +// - specify block updates to bit & buses +// 10/13/08 - CR492334 - update TEMAC_SINGLE_INST to B_TEMAC_SINGLE_INST +// 11/11/08 - CR493972 - Add SIM_VERSION +// 01/27/09 - CR505569 - Writer update +// 04/03/09 - CR515882 - Fix for 16 bit client mode +// 09/01/09 - CR532335 - Delay YML update, specify block update +/////////////////////////////////////////////////////// + +`timescale 1 ps / 1 ps + +module TEMAC_SINGLE ( + DCRHOSTDONEIR, + EMACCLIENTANINTERRUPT, + EMACCLIENTRXBADFRAME, + EMACCLIENTRXCLIENTCLKOUT, + EMACCLIENTRXD, + EMACCLIENTRXDVLD, + EMACCLIENTRXDVLDMSW, + EMACCLIENTRXFRAMEDROP, + EMACCLIENTRXGOODFRAME, + EMACCLIENTRXSTATS, + EMACCLIENTRXSTATSBYTEVLD, + EMACCLIENTRXSTATSVLD, + EMACCLIENTTXACK, + EMACCLIENTTXCLIENTCLKOUT, + EMACCLIENTTXCOLLISION, + EMACCLIENTTXRETRANSMIT, + EMACCLIENTTXSTATS, + EMACCLIENTTXSTATSBYTEVLD, + EMACCLIENTTXSTATSVLD, + EMACDCRACK, + EMACDCRDBUS, + EMACPHYENCOMMAALIGN, + EMACPHYLOOPBACKMSB, + EMACPHYMCLKOUT, + EMACPHYMDOUT, + EMACPHYMDTRI, + EMACPHYMGTRXRESET, + EMACPHYMGTTXRESET, + EMACPHYPOWERDOWN, + EMACPHYSYNCACQSTATUS, + EMACPHYTXCHARDISPMODE, + EMACPHYTXCHARDISPVAL, + EMACPHYTXCHARISK, + EMACPHYTXCLK, + EMACPHYTXD, + EMACPHYTXEN, + EMACPHYTXER, + EMACPHYTXGMIIMIICLKOUT, + EMACSPEEDIS10100, + HOSTMIIMRDY, + HOSTRDDATA, + CLIENTEMACDCMLOCKED, + CLIENTEMACPAUSEREQ, + CLIENTEMACPAUSEVAL, + CLIENTEMACRXCLIENTCLKIN, + CLIENTEMACTXCLIENTCLKIN, + CLIENTEMACTXD, + CLIENTEMACTXDVLD, + CLIENTEMACTXDVLDMSW, + CLIENTEMACTXFIRSTBYTE, + CLIENTEMACTXIFGDELAY, + CLIENTEMACTXUNDERRUN, + DCREMACABUS, + DCREMACCLK, + DCREMACDBUS, + DCREMACENABLE, + DCREMACREAD, + DCREMACWRITE, + HOSTADDR, + HOSTCLK, + HOSTMIIMSEL, + HOSTOPCODE, + HOSTREQ, + HOSTWRDATA, + PHYEMACCOL, + PHYEMACCRS, + PHYEMACGTXCLK, + PHYEMACMCLKIN, + PHYEMACMDIN, + PHYEMACMIITXCLK, + PHYEMACPHYAD, + PHYEMACRXBUFSTATUS, + PHYEMACRXCHARISCOMMA, + PHYEMACRXCHARISK, + PHYEMACRXCLK, + PHYEMACRXCLKCORCNT, + PHYEMACRXD, + PHYEMACRXDISPERR, + PHYEMACRXDV, + PHYEMACRXER, + PHYEMACRXNOTINTABLE, + PHYEMACRXRUNDISP, + PHYEMACSIGNALDET, + PHYEMACTXBUFERR, + PHYEMACTXGMIIMIICLKIN, + RESET +); + + parameter EMAC_1000BASEX_ENABLE = "FALSE"; + parameter EMAC_ADDRFILTER_ENABLE = "FALSE"; + parameter EMAC_BYTEPHY = "FALSE"; + parameter EMAC_CTRLLENCHECK_DISABLE = "FALSE"; + parameter [0:7] EMAC_DCRBASEADDR = 8'h00; + parameter EMAC_GTLOOPBACK = "FALSE"; + parameter EMAC_HOST_ENABLE = "FALSE"; + parameter [8:0] EMAC_LINKTIMERVAL = 9'h000; + parameter EMAC_LTCHECK_DISABLE = "FALSE"; + parameter EMAC_MDIO_ENABLE = "FALSE"; + parameter EMAC_MDIO_IGNORE_PHYADZERO = "FALSE"; + parameter [47:0] EMAC_PAUSEADDR = 48'h000000000000; + parameter EMAC_PHYINITAUTONEG_ENABLE = "FALSE"; + parameter EMAC_PHYISOLATE = "FALSE"; + parameter EMAC_PHYLOOPBACKMSB = "FALSE"; + parameter EMAC_PHYPOWERDOWN = "FALSE"; + parameter EMAC_PHYRESET = "FALSE"; + parameter EMAC_RGMII_ENABLE = "FALSE"; + parameter EMAC_RX16BITCLIENT_ENABLE = "FALSE"; + parameter EMAC_RXFLOWCTRL_ENABLE = "FALSE"; + parameter EMAC_RXHALFDUPLEX = "FALSE"; + parameter EMAC_RXINBANDFCS_ENABLE = "FALSE"; + parameter EMAC_RXJUMBOFRAME_ENABLE = "FALSE"; + parameter EMAC_RXRESET = "FALSE"; + parameter EMAC_RXVLAN_ENABLE = "FALSE"; + parameter EMAC_RX_ENABLE = "TRUE"; + parameter EMAC_SGMII_ENABLE = "FALSE"; + parameter EMAC_SPEED_LSB = "FALSE"; + parameter EMAC_SPEED_MSB = "FALSE"; + parameter EMAC_TX16BITCLIENT_ENABLE = "FALSE"; + parameter EMAC_TXFLOWCTRL_ENABLE = "FALSE"; + parameter EMAC_TXHALFDUPLEX = "FALSE"; + parameter EMAC_TXIFGADJUST_ENABLE = "FALSE"; + parameter EMAC_TXINBANDFCS_ENABLE = "FALSE"; + parameter EMAC_TXJUMBOFRAME_ENABLE = "FALSE"; + parameter EMAC_TXRESET = "FALSE"; + parameter EMAC_TXVLAN_ENABLE = "FALSE"; + parameter EMAC_TX_ENABLE = "TRUE"; + parameter [47:0] EMAC_UNICASTADDR = 48'h000000000000; + parameter EMAC_UNIDIRECTION_ENABLE = "FALSE"; + parameter EMAC_USECLKEN = "FALSE"; + parameter SIM_VERSION = "1.0"; + + localparam in_delay = 50; + localparam out_delay = 0; + localparam INCLK_DELAY = 0; + localparam OUTCLK_DELAY = 0; + + localparam EMACMIITXCLK_DELAY = (EMAC_TX16BITCLIENT_ENABLE == "TRUE") ? 25: INCLK_DELAY; + + output DCRHOSTDONEIR; + output EMACCLIENTANINTERRUPT; + output EMACCLIENTRXBADFRAME; + output EMACCLIENTRXCLIENTCLKOUT; + output EMACCLIENTRXDVLD; + output EMACCLIENTRXDVLDMSW; + output EMACCLIENTRXFRAMEDROP; + output EMACCLIENTRXGOODFRAME; + output EMACCLIENTRXSTATSBYTEVLD; + output EMACCLIENTRXSTATSVLD; + output EMACCLIENTTXACK; + output EMACCLIENTTXCLIENTCLKOUT; + output EMACCLIENTTXCOLLISION; + output EMACCLIENTTXRETRANSMIT; + output EMACCLIENTTXSTATS; + output EMACCLIENTTXSTATSBYTEVLD; + output EMACCLIENTTXSTATSVLD; + output EMACDCRACK; + output EMACPHYENCOMMAALIGN; + output EMACPHYLOOPBACKMSB; + output EMACPHYMCLKOUT; + output EMACPHYMDOUT; + output EMACPHYMDTRI; + output EMACPHYMGTRXRESET; + output EMACPHYMGTTXRESET; + output EMACPHYPOWERDOWN; + output EMACPHYSYNCACQSTATUS; + output EMACPHYTXCHARDISPMODE; + output EMACPHYTXCHARDISPVAL; + output EMACPHYTXCHARISK; + output EMACPHYTXCLK; + output EMACPHYTXEN; + output EMACPHYTXER; + output EMACPHYTXGMIIMIICLKOUT; + output EMACSPEEDIS10100; + output HOSTMIIMRDY; + output [0:31] EMACDCRDBUS; + output [15:0] EMACCLIENTRXD; + output [31:0] HOSTRDDATA; + output [6:0] EMACCLIENTRXSTATS; + output [7:0] EMACPHYTXD; + + input CLIENTEMACDCMLOCKED; + input CLIENTEMACPAUSEREQ; + input CLIENTEMACRXCLIENTCLKIN; + input CLIENTEMACTXCLIENTCLKIN; + input CLIENTEMACTXDVLD; + input CLIENTEMACTXDVLDMSW; + input CLIENTEMACTXFIRSTBYTE; + input CLIENTEMACTXUNDERRUN; + input DCREMACCLK; + input DCREMACENABLE; + input DCREMACREAD; + input DCREMACWRITE; + input HOSTCLK; + input HOSTMIIMSEL; + input HOSTREQ; + input PHYEMACCOL; + input PHYEMACCRS; + input PHYEMACGTXCLK; + input PHYEMACMCLKIN; + input PHYEMACMDIN; + input PHYEMACMIITXCLK; + input PHYEMACRXCHARISCOMMA; + input PHYEMACRXCHARISK; + input PHYEMACRXCLK; + input PHYEMACRXDISPERR; + input PHYEMACRXDV; + input PHYEMACRXER; + input PHYEMACRXNOTINTABLE; + input PHYEMACRXRUNDISP; + input PHYEMACSIGNALDET; + input PHYEMACTXBUFERR; + input PHYEMACTXGMIIMIICLKIN; + input RESET; + input [0:31] DCREMACDBUS; + input [0:9] DCREMACABUS; + input [15:0] CLIENTEMACPAUSEVAL; + input [15:0] CLIENTEMACTXD; + input [1:0] HOSTOPCODE; + input [1:0] PHYEMACRXBUFSTATUS; + input [2:0] PHYEMACRXCLKCORCNT; + input [31:0] HOSTWRDATA; + input [4:0] PHYEMACPHYAD; + input [7:0] CLIENTEMACTXIFGDELAY; + input [7:0] PHYEMACRXD; + input [9:0] HOSTADDR; + + reg EMAC_1000BASEX_ENABLE_BINARY; + reg EMAC_ADDRFILTER_ENABLE_BINARY; + reg EMAC_BYTEPHY_BINARY; + reg EMAC_CTRLLENCHECK_DISABLE_BINARY; + reg EMAC_GTLOOPBACK_BINARY; + reg EMAC_HOST_ENABLE_BINARY; + reg EMAC_LTCHECK_DISABLE_BINARY; + reg EMAC_MDIO_ENABLE_BINARY; + reg EMAC_MDIO_IGNORE_PHYADZERO_BINARY; + reg EMAC_PHYINITAUTONEG_ENABLE_BINARY; + reg EMAC_PHYISOLATE_BINARY; + reg EMAC_PHYLOOPBACKMSB_BINARY; + reg EMAC_PHYPOWERDOWN_BINARY; + reg EMAC_PHYRESET_BINARY; + reg EMAC_RGMII_ENABLE_BINARY; + reg EMAC_RX16BITCLIENT_ENABLE_BINARY; + reg EMAC_RXFLOWCTRL_ENABLE_BINARY; + reg EMAC_RXHALFDUPLEX_BINARY; + reg EMAC_RXINBANDFCS_ENABLE_BINARY; + reg EMAC_RXJUMBOFRAME_ENABLE_BINARY; + reg EMAC_RXRESET_BINARY; + reg EMAC_RXVLAN_ENABLE_BINARY; + reg EMAC_RX_ENABLE_BINARY; + reg EMAC_SGMII_ENABLE_BINARY; + reg EMAC_SPEED_LSB_BINARY; + reg EMAC_SPEED_MSB_BINARY; + reg EMAC_TX16BITCLIENT_ENABLE_BINARY; + reg EMAC_TXFLOWCTRL_ENABLE_BINARY; + reg EMAC_TXHALFDUPLEX_BINARY; + reg EMAC_TXIFGADJUST_ENABLE_BINARY; + reg EMAC_TXINBANDFCS_ENABLE_BINARY; + reg EMAC_TXJUMBOFRAME_ENABLE_BINARY; + reg EMAC_TXRESET_BINARY; + reg EMAC_TXVLAN_ENABLE_BINARY; + reg EMAC_TX_ENABLE_BINARY; + reg EMAC_UNIDIRECTION_ENABLE_BINARY; + reg EMAC_USECLKEN_BINARY; + reg SIM_VERSION_BINARY; + + tri0 GSR = glbl.GSR; + + initial begin + case (EMAC_1000BASEX_ENABLE) + "FALSE" : EMAC_1000BASEX_ENABLE_BINARY = 1'b0; + "TRUE" : EMAC_1000BASEX_ENABLE_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute EMAC_1000BASEX_ENABLE on TEMAC_SINGLE instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", EMAC_1000BASEX_ENABLE); + $finish; + end + endcase + + case (EMAC_ADDRFILTER_ENABLE) + "FALSE" : EMAC_ADDRFILTER_ENABLE_BINARY = 1'b0; + "TRUE" : EMAC_ADDRFILTER_ENABLE_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute EMAC_ADDRFILTER_ENABLE on TEMAC_SINGLE instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", EMAC_ADDRFILTER_ENABLE); + $finish; + end + endcase + + case (EMAC_BYTEPHY) + "FALSE" : EMAC_BYTEPHY_BINARY = 1'b0; + "TRUE" : EMAC_BYTEPHY_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute EMAC_BYTEPHY on TEMAC_SINGLE instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", EMAC_BYTEPHY); + $finish; + end + endcase + + case (EMAC_CTRLLENCHECK_DISABLE) + "FALSE" : EMAC_CTRLLENCHECK_DISABLE_BINARY = 1'b0; + "TRUE" : EMAC_CTRLLENCHECK_DISABLE_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute EMAC_CTRLLENCHECK_DISABLE on TEMAC_SINGLE instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", EMAC_CTRLLENCHECK_DISABLE); + $finish; + end + endcase + + case (EMAC_GTLOOPBACK) + "FALSE" : EMAC_GTLOOPBACK_BINARY = 1'b0; + "TRUE" : EMAC_GTLOOPBACK_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute EMAC_GTLOOPBACK on TEMAC_SINGLE instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", EMAC_GTLOOPBACK); + $finish; + end + endcase + + case (EMAC_HOST_ENABLE) + "FALSE" : EMAC_HOST_ENABLE_BINARY = 1'b0; + "TRUE" : EMAC_HOST_ENABLE_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute EMAC_HOST_ENABLE on TEMAC_SINGLE instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", EMAC_HOST_ENABLE); + $finish; + end + endcase + + case (EMAC_LTCHECK_DISABLE) + "FALSE" : EMAC_LTCHECK_DISABLE_BINARY = 1'b0; + "TRUE" : EMAC_LTCHECK_DISABLE_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute EMAC_LTCHECK_DISABLE on TEMAC_SINGLE instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", EMAC_LTCHECK_DISABLE); + $finish; + end + endcase + + case (EMAC_MDIO_ENABLE) + "FALSE" : EMAC_MDIO_ENABLE_BINARY = 1'b0; + "TRUE" : EMAC_MDIO_ENABLE_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute EMAC_MDIO_ENABLE on TEMAC_SINGLE instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", EMAC_MDIO_ENABLE); + $finish; + end + endcase + + case (EMAC_MDIO_IGNORE_PHYADZERO) + "FALSE" : EMAC_MDIO_IGNORE_PHYADZERO_BINARY = 1'b0; + "TRUE" : EMAC_MDIO_IGNORE_PHYADZERO_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute EMAC_MDIO_IGNORE_PHYADZERO on TEMAC_SINGLE instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", EMAC_MDIO_IGNORE_PHYADZERO); + $finish; + end + endcase + + case (EMAC_PHYINITAUTONEG_ENABLE) + "FALSE" : EMAC_PHYINITAUTONEG_ENABLE_BINARY = 1'b0; + "TRUE" : EMAC_PHYINITAUTONEG_ENABLE_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute EMAC_PHYINITAUTONEG_ENABLE on TEMAC_SINGLE instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", EMAC_PHYINITAUTONEG_ENABLE); + $finish; + end + endcase + + case (EMAC_PHYISOLATE) + "FALSE" : EMAC_PHYISOLATE_BINARY = 1'b0; + "TRUE" : EMAC_PHYISOLATE_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute EMAC_PHYISOLATE on TEMAC_SINGLE instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", EMAC_PHYISOLATE); + $finish; + end + endcase + + case (EMAC_PHYLOOPBACKMSB) + "FALSE" : EMAC_PHYLOOPBACKMSB_BINARY = 1'b0; + "TRUE" : EMAC_PHYLOOPBACKMSB_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute EMAC_PHYLOOPBACKMSB on TEMAC_SINGLE instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", EMAC_PHYLOOPBACKMSB); + $finish; + end + endcase + + case (EMAC_PHYPOWERDOWN) + "FALSE" : EMAC_PHYPOWERDOWN_BINARY = 1'b0; + "TRUE" : EMAC_PHYPOWERDOWN_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute EMAC_PHYPOWERDOWN on TEMAC_SINGLE instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", EMAC_PHYPOWERDOWN); + $finish; + end + endcase + + case (EMAC_PHYRESET) + "FALSE" : EMAC_PHYRESET_BINARY = 1'b0; + "TRUE" : EMAC_PHYRESET_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute EMAC_PHYRESET on TEMAC_SINGLE instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", EMAC_PHYRESET); + $finish; + end + endcase + + case (EMAC_RGMII_ENABLE) + "FALSE" : EMAC_RGMII_ENABLE_BINARY = 1'b0; + "TRUE" : EMAC_RGMII_ENABLE_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute EMAC_RGMII_ENABLE on TEMAC_SINGLE instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", EMAC_RGMII_ENABLE); + $finish; + end + endcase + + case (EMAC_RX16BITCLIENT_ENABLE) + "FALSE" : EMAC_RX16BITCLIENT_ENABLE_BINARY = 1'b0; + "TRUE" : EMAC_RX16BITCLIENT_ENABLE_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute EMAC_RX16BITCLIENT_ENABLE on TEMAC_SINGLE instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", EMAC_RX16BITCLIENT_ENABLE); + $finish; + end + endcase + + case (EMAC_RXFLOWCTRL_ENABLE) + "FALSE" : EMAC_RXFLOWCTRL_ENABLE_BINARY = 1'b0; + "TRUE" : EMAC_RXFLOWCTRL_ENABLE_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute EMAC_RXFLOWCTRL_ENABLE on TEMAC_SINGLE instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", EMAC_RXFLOWCTRL_ENABLE); + $finish; + end + endcase + + case (EMAC_RXHALFDUPLEX) + "FALSE" : EMAC_RXHALFDUPLEX_BINARY = 1'b0; + "TRUE" : EMAC_RXHALFDUPLEX_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute EMAC_RXHALFDUPLEX on TEMAC_SINGLE instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", EMAC_RXHALFDUPLEX); + $finish; + end + endcase + + case (EMAC_RXINBANDFCS_ENABLE) + "FALSE" : EMAC_RXINBANDFCS_ENABLE_BINARY = 1'b0; + "TRUE" : EMAC_RXINBANDFCS_ENABLE_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute EMAC_RXINBANDFCS_ENABLE on TEMAC_SINGLE instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", EMAC_RXINBANDFCS_ENABLE); + $finish; + end + endcase + + case (EMAC_RXJUMBOFRAME_ENABLE) + "FALSE" : EMAC_RXJUMBOFRAME_ENABLE_BINARY = 1'b0; + "TRUE" : EMAC_RXJUMBOFRAME_ENABLE_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute EMAC_RXJUMBOFRAME_ENABLE on TEMAC_SINGLE instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", EMAC_RXJUMBOFRAME_ENABLE); + $finish; + end + endcase + + case (EMAC_RXRESET) + "FALSE" : EMAC_RXRESET_BINARY = 1'b0; + "TRUE" : EMAC_RXRESET_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute EMAC_RXRESET on TEMAC_SINGLE instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", EMAC_RXRESET); + $finish; + end + endcase + + case (EMAC_RXVLAN_ENABLE) + "FALSE" : EMAC_RXVLAN_ENABLE_BINARY = 1'b0; + "TRUE" : EMAC_RXVLAN_ENABLE_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute EMAC_RXVLAN_ENABLE on TEMAC_SINGLE instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", EMAC_RXVLAN_ENABLE); + $finish; + end + endcase + + case (EMAC_RX_ENABLE) + "FALSE" : EMAC_RX_ENABLE_BINARY = 1'b0; + "TRUE" : EMAC_RX_ENABLE_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute EMAC_RX_ENABLE on TEMAC_SINGLE instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", EMAC_RX_ENABLE); + $finish; + end + endcase + + case (EMAC_SGMII_ENABLE) + "FALSE" : EMAC_SGMII_ENABLE_BINARY = 1'b0; + "TRUE" : EMAC_SGMII_ENABLE_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute EMAC_SGMII_ENABLE on TEMAC_SINGLE instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", EMAC_SGMII_ENABLE); + $finish; + end + endcase + + case (EMAC_SPEED_LSB) + "FALSE" : EMAC_SPEED_LSB_BINARY = 1'b0; + "TRUE" : EMAC_SPEED_LSB_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute EMAC_SPEED_LSB on TEMAC_SINGLE instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", EMAC_SPEED_LSB); + $finish; + end + endcase + + case (EMAC_SPEED_MSB) + "FALSE" : EMAC_SPEED_MSB_BINARY = 1'b0; + "TRUE" : EMAC_SPEED_MSB_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute EMAC_SPEED_MSB on TEMAC_SINGLE instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", EMAC_SPEED_MSB); + $finish; + end + endcase + + case (EMAC_TX16BITCLIENT_ENABLE) + "FALSE" : EMAC_TX16BITCLIENT_ENABLE_BINARY = 1'b0; + "TRUE" : EMAC_TX16BITCLIENT_ENABLE_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute EMAC_TX16BITCLIENT_ENABLE on TEMAC_SINGLE instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", EMAC_TX16BITCLIENT_ENABLE); + $finish; + end + endcase + + case (EMAC_TXFLOWCTRL_ENABLE) + "FALSE" : EMAC_TXFLOWCTRL_ENABLE_BINARY = 1'b0; + "TRUE" : EMAC_TXFLOWCTRL_ENABLE_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute EMAC_TXFLOWCTRL_ENABLE on TEMAC_SINGLE instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", EMAC_TXFLOWCTRL_ENABLE); + $finish; + end + endcase + + case (EMAC_TXHALFDUPLEX) + "FALSE" : EMAC_TXHALFDUPLEX_BINARY = 1'b0; + "TRUE" : EMAC_TXHALFDUPLEX_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute EMAC_TXHALFDUPLEX on TEMAC_SINGLE instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", EMAC_TXHALFDUPLEX); + $finish; + end + endcase + + case (EMAC_TXIFGADJUST_ENABLE) + "FALSE" : EMAC_TXIFGADJUST_ENABLE_BINARY = 1'b0; + "TRUE" : EMAC_TXIFGADJUST_ENABLE_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute EMAC_TXIFGADJUST_ENABLE on TEMAC_SINGLE instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", EMAC_TXIFGADJUST_ENABLE); + $finish; + end + endcase + + case (EMAC_TXINBANDFCS_ENABLE) + "FALSE" : EMAC_TXINBANDFCS_ENABLE_BINARY = 1'b0; + "TRUE" : EMAC_TXINBANDFCS_ENABLE_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute EMAC_TXINBANDFCS_ENABLE on TEMAC_SINGLE instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", EMAC_TXINBANDFCS_ENABLE); + $finish; + end + endcase + + case (EMAC_TXJUMBOFRAME_ENABLE) + "FALSE" : EMAC_TXJUMBOFRAME_ENABLE_BINARY = 1'b0; + "TRUE" : EMAC_TXJUMBOFRAME_ENABLE_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute EMAC_TXJUMBOFRAME_ENABLE on TEMAC_SINGLE instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", EMAC_TXJUMBOFRAME_ENABLE); + $finish; + end + endcase + + case (EMAC_TXRESET) + "FALSE" : EMAC_TXRESET_BINARY = 1'b0; + "TRUE" : EMAC_TXRESET_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute EMAC_TXRESET on TEMAC_SINGLE instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", EMAC_TXRESET); + $finish; + end + endcase + + case (EMAC_TXVLAN_ENABLE) + "FALSE" : EMAC_TXVLAN_ENABLE_BINARY = 1'b0; + "TRUE" : EMAC_TXVLAN_ENABLE_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute EMAC_TXVLAN_ENABLE on TEMAC_SINGLE instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", EMAC_TXVLAN_ENABLE); + $finish; + end + endcase + + case (EMAC_TX_ENABLE) + "FALSE" : EMAC_TX_ENABLE_BINARY = 1'b0; + "TRUE" : EMAC_TX_ENABLE_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute EMAC_TX_ENABLE on TEMAC_SINGLE instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", EMAC_TX_ENABLE); + $finish; + end + endcase + + case (EMAC_UNIDIRECTION_ENABLE) + "FALSE" : EMAC_UNIDIRECTION_ENABLE_BINARY = 1'b0; + "TRUE" : EMAC_UNIDIRECTION_ENABLE_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute EMAC_UNIDIRECTION_ENABLE on TEMAC_SINGLE instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", EMAC_UNIDIRECTION_ENABLE); + $finish; + end + endcase + + case (EMAC_USECLKEN) + "FALSE" : EMAC_USECLKEN_BINARY = 1'b0; + "TRUE" : EMAC_USECLKEN_BINARY = 1'b1; + default : begin + $display("Attribute Syntax Error : The Attribute EMAC_USECLKEN on TEMAC_SINGLE instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", EMAC_USECLKEN); + $finish; + end + endcase + + end + + wire [0:31] delay_EMACDCRDBUS; + wire [15:0] delay_EMACCLIENTRXD; + wire [31:0] delay_HOSTRDDATA; + wire [6:0] delay_EMACCLIENTRXSTATS; + wire [7:0] delay_EMACPHYTXD; + wire delay_DCRHOSTDONEIR; + wire delay_EMACCLIENTANINTERRUPT; + wire delay_EMACCLIENTRXBADFRAME; + wire delay_EMACCLIENTRXCLIENTCLKOUT; + wire delay_EMACCLIENTRXDVLD; + wire delay_EMACCLIENTRXDVLDMSW; + wire delay_EMACCLIENTRXFRAMEDROP; + wire delay_EMACCLIENTRXGOODFRAME; + wire delay_EMACCLIENTRXSTATSBYTEVLD; + wire delay_EMACCLIENTRXSTATSVLD; + wire delay_EMACCLIENTTXACK; + wire delay_EMACCLIENTTXCLIENTCLKOUT; + wire delay_EMACCLIENTTXCOLLISION; + wire delay_EMACCLIENTTXRETRANSMIT; + wire delay_EMACCLIENTTXSTATS; + wire delay_EMACCLIENTTXSTATSBYTEVLD; + wire delay_EMACCLIENTTXSTATSVLD; + wire delay_EMACDCRACK; + wire delay_EMACPHYENCOMMAALIGN; + wire delay_EMACPHYLOOPBACKMSB; + wire delay_EMACPHYMCLKOUT; + wire delay_EMACPHYMDOUT; + wire delay_EMACPHYMDTRI; + wire delay_EMACPHYMGTRXRESET; + wire delay_EMACPHYMGTTXRESET; + wire delay_EMACPHYPOWERDOWN; + wire delay_EMACPHYSYNCACQSTATUS; + wire delay_EMACPHYTXCHARDISPMODE; + wire delay_EMACPHYTXCHARDISPVAL; + wire delay_EMACPHYTXCHARISK; + wire delay_EMACPHYTXCLK; + wire delay_EMACPHYTXEN; + wire delay_EMACPHYTXER; + wire delay_EMACPHYTXGMIIMIICLKOUT; + wire delay_EMACSPEEDIS10100; + wire delay_HOSTMIIMRDY; + + wire [0:31] delay_DCREMACDBUS; + wire [0:9] delay_DCREMACABUS; + wire [15:0] delay_CLIENTEMACPAUSEVAL; + wire [15:0] delay_CLIENTEMACTXD; + wire [1:0] delay_HOSTOPCODE; + wire [1:0] delay_PHYEMACRXBUFSTATUS; + wire [2:0] delay_PHYEMACRXCLKCORCNT; + wire [31:0] delay_HOSTWRDATA; + wire [4:0] delay_PHYEMACPHYAD; + wire [7:0] delay_CLIENTEMACTXIFGDELAY; + wire [7:0] delay_PHYEMACRXD; + wire [9:0] delay_HOSTADDR; + wire delay_CLIENTEMACDCMLOCKED; + wire delay_CLIENTEMACPAUSEREQ; + wire delay_CLIENTEMACRXCLIENTCLKIN; + wire delay_CLIENTEMACTXCLIENTCLKIN; + wire delay_CLIENTEMACTXDVLD; + wire delay_CLIENTEMACTXDVLDMSW; + wire delay_CLIENTEMACTXFIRSTBYTE; + wire delay_CLIENTEMACTXUNDERRUN; + wire delay_DCREMACCLK; + wire delay_DCREMACENABLE; + wire delay_DCREMACREAD; + wire delay_DCREMACWRITE; + wire delay_HOSTCLK; + wire delay_HOSTMIIMSEL; + wire delay_HOSTREQ; + wire delay_PHYEMACCOL; + wire delay_PHYEMACCRS; + wire delay_PHYEMACGTXCLK; + wire delay_PHYEMACMCLKIN; + wire delay_PHYEMACMDIN; + wire delay_PHYEMACMIITXCLK; + wire delay_PHYEMACRXCHARISCOMMA; + wire delay_PHYEMACRXCHARISK; + wire delay_PHYEMACRXCLK; + wire delay_PHYEMACRXDISPERR; + wire delay_PHYEMACRXDV; + wire delay_PHYEMACRXER; + wire delay_PHYEMACRXNOTINTABLE; + wire delay_PHYEMACRXRUNDISP; + wire delay_PHYEMACSIGNALDET; + wire delay_PHYEMACTXBUFERR; + wire delay_PHYEMACTXGMIIMIICLKIN; + wire delay_RESET; + + + assign #(out_delay) DCRHOSTDONEIR = delay_DCRHOSTDONEIR; + assign #(out_delay) EMACCLIENTANINTERRUPT = delay_EMACCLIENTANINTERRUPT; + assign #(out_delay) EMACCLIENTRXBADFRAME = delay_EMACCLIENTRXBADFRAME; + assign #(out_delay) EMACCLIENTRXCLIENTCLKOUT = delay_EMACCLIENTRXCLIENTCLKOUT; + assign #(out_delay) EMACCLIENTRXD = delay_EMACCLIENTRXD; + assign #(out_delay) EMACCLIENTRXDVLD = delay_EMACCLIENTRXDVLD; + assign #(out_delay) EMACCLIENTRXDVLDMSW = delay_EMACCLIENTRXDVLDMSW; + assign #(out_delay) EMACCLIENTRXFRAMEDROP = delay_EMACCLIENTRXFRAMEDROP; + assign #(out_delay) EMACCLIENTRXGOODFRAME = delay_EMACCLIENTRXGOODFRAME; + assign #(out_delay) EMACCLIENTRXSTATS = delay_EMACCLIENTRXSTATS; + assign #(out_delay) EMACCLIENTRXSTATSBYTEVLD = delay_EMACCLIENTRXSTATSBYTEVLD; + assign #(out_delay) EMACCLIENTRXSTATSVLD = delay_EMACCLIENTRXSTATSVLD; + assign #(out_delay) EMACCLIENTTXACK = delay_EMACCLIENTTXACK; + assign #(out_delay) EMACCLIENTTXCLIENTCLKOUT = delay_EMACCLIENTTXCLIENTCLKOUT; + assign #(out_delay) EMACCLIENTTXCOLLISION = delay_EMACCLIENTTXCOLLISION; + assign #(out_delay) EMACCLIENTTXRETRANSMIT = delay_EMACCLIENTTXRETRANSMIT; + assign #(out_delay) EMACCLIENTTXSTATS = delay_EMACCLIENTTXSTATS; + assign #(out_delay) EMACCLIENTTXSTATSBYTEVLD = delay_EMACCLIENTTXSTATSBYTEVLD; + assign #(out_delay) EMACCLIENTTXSTATSVLD = delay_EMACCLIENTTXSTATSVLD; + assign #(out_delay) EMACDCRACK = delay_EMACDCRACK; + assign #(out_delay) EMACDCRDBUS = delay_EMACDCRDBUS; + assign #(out_delay) EMACPHYENCOMMAALIGN = delay_EMACPHYENCOMMAALIGN; + assign #(out_delay) EMACPHYLOOPBACKMSB = delay_EMACPHYLOOPBACKMSB; + assign #(out_delay) EMACPHYMCLKOUT = delay_EMACPHYMCLKOUT; + assign #(out_delay) EMACPHYMDOUT = delay_EMACPHYMDOUT; + assign #(out_delay) EMACPHYMDTRI = delay_EMACPHYMDTRI; + assign #(out_delay) EMACPHYMGTRXRESET = delay_EMACPHYMGTRXRESET; + assign #(out_delay) EMACPHYMGTTXRESET = delay_EMACPHYMGTTXRESET; + assign #(out_delay) EMACPHYPOWERDOWN = delay_EMACPHYPOWERDOWN; + assign #(out_delay) EMACPHYSYNCACQSTATUS = delay_EMACPHYSYNCACQSTATUS; + assign #(out_delay) EMACPHYTXCHARDISPMODE = delay_EMACPHYTXCHARDISPMODE; + assign #(out_delay) EMACPHYTXCHARDISPVAL = delay_EMACPHYTXCHARDISPVAL; + assign #(out_delay) EMACPHYTXCHARISK = delay_EMACPHYTXCHARISK; + assign #(out_delay) EMACPHYTXCLK = delay_EMACPHYTXCLK; + assign #(out_delay) EMACPHYTXD = delay_EMACPHYTXD; + assign #(out_delay) EMACPHYTXEN = delay_EMACPHYTXEN; + assign #(out_delay) EMACPHYTXER = delay_EMACPHYTXER; + assign #(out_delay) EMACPHYTXGMIIMIICLKOUT = delay_EMACPHYTXGMIIMIICLKOUT; + assign #(out_delay) EMACSPEEDIS10100 = delay_EMACSPEEDIS10100; + assign #(out_delay) HOSTMIIMRDY = delay_HOSTMIIMRDY; + assign #(out_delay) HOSTRDDATA = delay_HOSTRDDATA; + + + assign #(INCLK_DELAY) delay_CLIENTEMACRXCLIENTCLKIN = CLIENTEMACRXCLIENTCLKIN; + assign #(INCLK_DELAY) delay_CLIENTEMACTXCLIENTCLKIN = CLIENTEMACTXCLIENTCLKIN; + assign #(INCLK_DELAY) delay_DCREMACCLK = DCREMACCLK; + assign #(INCLK_DELAY) delay_HOSTCLK = HOSTCLK; + assign #(INCLK_DELAY) delay_PHYEMACGTXCLK = PHYEMACGTXCLK; + assign #(INCLK_DELAY) delay_PHYEMACMCLKIN = PHYEMACMCLKIN; + assign #(EMACMIITXCLK_DELAY) delay_PHYEMACMIITXCLK = PHYEMACMIITXCLK; + assign #(INCLK_DELAY) delay_PHYEMACRXCLK = PHYEMACRXCLK; + assign #(INCLK_DELAY) delay_PHYEMACTXGMIIMIICLKIN = PHYEMACTXGMIIMIICLKIN; + + assign #(in_delay) delay_CLIENTEMACDCMLOCKED = CLIENTEMACDCMLOCKED; + assign #(in_delay) delay_CLIENTEMACPAUSEREQ = CLIENTEMACPAUSEREQ; + assign #(in_delay) delay_CLIENTEMACPAUSEVAL = CLIENTEMACPAUSEVAL; + assign #(in_delay) delay_CLIENTEMACTXD = CLIENTEMACTXD; + assign #(in_delay) delay_CLIENTEMACTXDVLD = CLIENTEMACTXDVLD; + assign #(in_delay) delay_CLIENTEMACTXDVLDMSW = CLIENTEMACTXDVLDMSW; + assign #(in_delay) delay_CLIENTEMACTXFIRSTBYTE = CLIENTEMACTXFIRSTBYTE; + assign #(in_delay) delay_CLIENTEMACTXIFGDELAY = CLIENTEMACTXIFGDELAY; + assign #(in_delay) delay_CLIENTEMACTXUNDERRUN = CLIENTEMACTXUNDERRUN; + assign #(in_delay) delay_DCREMACABUS = DCREMACABUS; + assign #(in_delay) delay_DCREMACDBUS = DCREMACDBUS; + assign #(in_delay) delay_DCREMACENABLE = DCREMACENABLE; + assign #(in_delay) delay_DCREMACREAD = DCREMACREAD; + assign #(in_delay) delay_DCREMACWRITE = DCREMACWRITE; + assign #(in_delay) delay_HOSTADDR = HOSTADDR; + assign #(in_delay) delay_HOSTMIIMSEL = HOSTMIIMSEL; + assign #(in_delay) delay_HOSTOPCODE = HOSTOPCODE; + assign #(in_delay) delay_HOSTREQ = HOSTREQ; + assign #(in_delay) delay_HOSTWRDATA = HOSTWRDATA; + assign #(in_delay) delay_PHYEMACCOL = PHYEMACCOL; + assign #(in_delay) delay_PHYEMACCRS = PHYEMACCRS; + assign #(in_delay) delay_PHYEMACMDIN = PHYEMACMDIN; + assign #(in_delay) delay_PHYEMACPHYAD = PHYEMACPHYAD; + assign #(in_delay) delay_PHYEMACRXBUFSTATUS = PHYEMACRXBUFSTATUS; + assign #(in_delay) delay_PHYEMACRXCHARISCOMMA = PHYEMACRXCHARISCOMMA; + assign #(in_delay) delay_PHYEMACRXCHARISK = PHYEMACRXCHARISK; + assign #(in_delay) delay_PHYEMACRXCLKCORCNT = PHYEMACRXCLKCORCNT; + assign #(in_delay) delay_PHYEMACRXD = PHYEMACRXD; + assign #(in_delay) delay_PHYEMACRXDISPERR = PHYEMACRXDISPERR; + assign #(in_delay) delay_PHYEMACRXDV = PHYEMACRXDV; + assign #(in_delay) delay_PHYEMACRXER = PHYEMACRXER; + assign #(in_delay) delay_PHYEMACRXNOTINTABLE = PHYEMACRXNOTINTABLE; + assign #(in_delay) delay_PHYEMACRXRUNDISP = PHYEMACRXRUNDISP; + assign #(in_delay) delay_PHYEMACSIGNALDET = PHYEMACSIGNALDET; + assign #(in_delay) delay_PHYEMACTXBUFERR = PHYEMACTXBUFERR; + assign #(in_delay) delay_RESET = RESET; + + B_TEMAC_SINGLE #( + .EMAC_1000BASEX_ENABLE (EMAC_1000BASEX_ENABLE), + .EMAC_ADDRFILTER_ENABLE (EMAC_ADDRFILTER_ENABLE), + .EMAC_BYTEPHY (EMAC_BYTEPHY), + .EMAC_CTRLLENCHECK_DISABLE (EMAC_CTRLLENCHECK_DISABLE), + .EMAC_DCRBASEADDR (EMAC_DCRBASEADDR), + .EMAC_GTLOOPBACK (EMAC_GTLOOPBACK), + .EMAC_HOST_ENABLE (EMAC_HOST_ENABLE), + .EMAC_LINKTIMERVAL (EMAC_LINKTIMERVAL), + .EMAC_LTCHECK_DISABLE (EMAC_LTCHECK_DISABLE), + .EMAC_MDIO_ENABLE (EMAC_MDIO_ENABLE), + .EMAC_MDIO_IGNORE_PHYADZERO (EMAC_MDIO_IGNORE_PHYADZERO), + .EMAC_PAUSEADDR (EMAC_PAUSEADDR), + .EMAC_PHYINITAUTONEG_ENABLE (EMAC_PHYINITAUTONEG_ENABLE), + .EMAC_PHYISOLATE (EMAC_PHYISOLATE), + .EMAC_PHYLOOPBACKMSB (EMAC_PHYLOOPBACKMSB), + .EMAC_PHYPOWERDOWN (EMAC_PHYPOWERDOWN), + .EMAC_PHYRESET (EMAC_PHYRESET), + .EMAC_RGMII_ENABLE (EMAC_RGMII_ENABLE), + .EMAC_RX16BITCLIENT_ENABLE (EMAC_RX16BITCLIENT_ENABLE), + .EMAC_RXFLOWCTRL_ENABLE (EMAC_RXFLOWCTRL_ENABLE), + .EMAC_RXHALFDUPLEX (EMAC_RXHALFDUPLEX), + .EMAC_RXINBANDFCS_ENABLE (EMAC_RXINBANDFCS_ENABLE), + .EMAC_RXJUMBOFRAME_ENABLE (EMAC_RXJUMBOFRAME_ENABLE), + .EMAC_RXRESET (EMAC_RXRESET), + .EMAC_RXVLAN_ENABLE (EMAC_RXVLAN_ENABLE), + .EMAC_RX_ENABLE (EMAC_RX_ENABLE), + .EMAC_SGMII_ENABLE (EMAC_SGMII_ENABLE), + .EMAC_SPEED_LSB (EMAC_SPEED_LSB), + .EMAC_SPEED_MSB (EMAC_SPEED_MSB), + .EMAC_TX16BITCLIENT_ENABLE (EMAC_TX16BITCLIENT_ENABLE), + .EMAC_TXFLOWCTRL_ENABLE (EMAC_TXFLOWCTRL_ENABLE), + .EMAC_TXHALFDUPLEX (EMAC_TXHALFDUPLEX), + .EMAC_TXIFGADJUST_ENABLE (EMAC_TXIFGADJUST_ENABLE), + .EMAC_TXINBANDFCS_ENABLE (EMAC_TXINBANDFCS_ENABLE), + .EMAC_TXJUMBOFRAME_ENABLE (EMAC_TXJUMBOFRAME_ENABLE), + .EMAC_TXRESET (EMAC_TXRESET), + .EMAC_TXVLAN_ENABLE (EMAC_TXVLAN_ENABLE), + .EMAC_TX_ENABLE (EMAC_TX_ENABLE), + .EMAC_UNICASTADDR (EMAC_UNICASTADDR), + .EMAC_UNIDIRECTION_ENABLE (EMAC_UNIDIRECTION_ENABLE), + .EMAC_USECLKEN (EMAC_USECLKEN)) + + + B_TEMAC_SINGLE_INST( + .DCRHOSTDONEIR (delay_DCRHOSTDONEIR), + .EMACCLIENTANINTERRUPT (delay_EMACCLIENTANINTERRUPT), + .EMACCLIENTRXBADFRAME (delay_EMACCLIENTRXBADFRAME), + .EMACCLIENTRXCLIENTCLKOUT (delay_EMACCLIENTRXCLIENTCLKOUT), + .EMACCLIENTRXD (delay_EMACCLIENTRXD), + .EMACCLIENTRXDVLD (delay_EMACCLIENTRXDVLD), + .EMACCLIENTRXDVLDMSW (delay_EMACCLIENTRXDVLDMSW), + .EMACCLIENTRXFRAMEDROP (delay_EMACCLIENTRXFRAMEDROP), + .EMACCLIENTRXGOODFRAME (delay_EMACCLIENTRXGOODFRAME), + .EMACCLIENTRXSTATS (delay_EMACCLIENTRXSTATS), + .EMACCLIENTRXSTATSBYTEVLD (delay_EMACCLIENTRXSTATSBYTEVLD), + .EMACCLIENTRXSTATSVLD (delay_EMACCLIENTRXSTATSVLD), + .EMACCLIENTTXACK (delay_EMACCLIENTTXACK), + .EMACCLIENTTXCLIENTCLKOUT (delay_EMACCLIENTTXCLIENTCLKOUT), + .EMACCLIENTTXCOLLISION (delay_EMACCLIENTTXCOLLISION), + .EMACCLIENTTXRETRANSMIT (delay_EMACCLIENTTXRETRANSMIT), + .EMACCLIENTTXSTATS (delay_EMACCLIENTTXSTATS), + .EMACCLIENTTXSTATSBYTEVLD (delay_EMACCLIENTTXSTATSBYTEVLD), + .EMACCLIENTTXSTATSVLD (delay_EMACCLIENTTXSTATSVLD), + .EMACDCRACK (delay_EMACDCRACK), + .EMACDCRDBUS (delay_EMACDCRDBUS), + .EMACPHYENCOMMAALIGN (delay_EMACPHYENCOMMAALIGN), + .EMACPHYLOOPBACKMSB (delay_EMACPHYLOOPBACKMSB), + .EMACPHYMCLKOUT (delay_EMACPHYMCLKOUT), + .EMACPHYMDOUT (delay_EMACPHYMDOUT), + .EMACPHYMDTRI (delay_EMACPHYMDTRI), + .EMACPHYMGTRXRESET (delay_EMACPHYMGTRXRESET), + .EMACPHYMGTTXRESET (delay_EMACPHYMGTTXRESET), + .EMACPHYPOWERDOWN (delay_EMACPHYPOWERDOWN), + .EMACPHYSYNCACQSTATUS (delay_EMACPHYSYNCACQSTATUS), + .EMACPHYTXCHARDISPMODE (delay_EMACPHYTXCHARDISPMODE), + .EMACPHYTXCHARDISPVAL (delay_EMACPHYTXCHARDISPVAL), + .EMACPHYTXCHARISK (delay_EMACPHYTXCHARISK), + .EMACPHYTXCLK (delay_EMACPHYTXCLK), + .EMACPHYTXD (delay_EMACPHYTXD), + .EMACPHYTXEN (delay_EMACPHYTXEN), + .EMACPHYTXER (delay_EMACPHYTXER), + .EMACPHYTXGMIIMIICLKOUT (delay_EMACPHYTXGMIIMIICLKOUT), + .EMACSPEEDIS10100 (delay_EMACSPEEDIS10100), + .HOSTMIIMRDY (delay_HOSTMIIMRDY), + .HOSTRDDATA (delay_HOSTRDDATA), + .CLIENTEMACDCMLOCKED (delay_CLIENTEMACDCMLOCKED), + .CLIENTEMACPAUSEREQ (delay_CLIENTEMACPAUSEREQ), + .CLIENTEMACPAUSEVAL (delay_CLIENTEMACPAUSEVAL), + .CLIENTEMACRXCLIENTCLKIN (delay_CLIENTEMACRXCLIENTCLKIN), + .CLIENTEMACTXCLIENTCLKIN (delay_CLIENTEMACTXCLIENTCLKIN), + .CLIENTEMACTXD (delay_CLIENTEMACTXD), + .CLIENTEMACTXDVLD (delay_CLIENTEMACTXDVLD), + .CLIENTEMACTXDVLDMSW (delay_CLIENTEMACTXDVLDMSW), + .CLIENTEMACTXFIRSTBYTE (delay_CLIENTEMACTXFIRSTBYTE), + .CLIENTEMACTXIFGDELAY (delay_CLIENTEMACTXIFGDELAY), + .CLIENTEMACTXUNDERRUN (delay_CLIENTEMACTXUNDERRUN), + .DCREMACABUS (delay_DCREMACABUS), + .DCREMACCLK (delay_DCREMACCLK), + .DCREMACDBUS (delay_DCREMACDBUS), + .DCREMACENABLE (delay_DCREMACENABLE), + .DCREMACREAD (delay_DCREMACREAD), + .DCREMACWRITE (delay_DCREMACWRITE), + .HOSTADDR (delay_HOSTADDR), + .HOSTCLK (delay_HOSTCLK), + .HOSTMIIMSEL (delay_HOSTMIIMSEL), + .HOSTOPCODE (delay_HOSTOPCODE), + .HOSTREQ (delay_HOSTREQ), + .HOSTWRDATA (delay_HOSTWRDATA), + .PHYEMACCOL (delay_PHYEMACCOL), + .PHYEMACCRS (delay_PHYEMACCRS), + .PHYEMACGTXCLK (delay_PHYEMACGTXCLK), + .PHYEMACMCLKIN (delay_PHYEMACMCLKIN), + .PHYEMACMDIN (delay_PHYEMACMDIN), + .PHYEMACMIITXCLK (delay_PHYEMACMIITXCLK), + .PHYEMACPHYAD (delay_PHYEMACPHYAD), + .PHYEMACRXBUFSTATUS (delay_PHYEMACRXBUFSTATUS), + .PHYEMACRXCHARISCOMMA (delay_PHYEMACRXCHARISCOMMA), + .PHYEMACRXCHARISK (delay_PHYEMACRXCHARISK), + .PHYEMACRXCLK (delay_PHYEMACRXCLK), + .PHYEMACRXCLKCORCNT (delay_PHYEMACRXCLKCORCNT), + .PHYEMACRXD (delay_PHYEMACRXD), + .PHYEMACRXDISPERR (delay_PHYEMACRXDISPERR), + .PHYEMACRXDV (delay_PHYEMACRXDV), + .PHYEMACRXER (delay_PHYEMACRXER), + .PHYEMACRXNOTINTABLE (delay_PHYEMACRXNOTINTABLE), + .PHYEMACRXRUNDISP (delay_PHYEMACRXRUNDISP), + .PHYEMACSIGNALDET (delay_PHYEMACSIGNALDET), + .PHYEMACTXBUFERR (delay_PHYEMACTXBUFERR), + .PHYEMACTXGMIIMIICLKIN (delay_PHYEMACTXGMIIMIICLKIN), + .RESET (delay_RESET), + .GSR(GSR) + ); + + specify + ( CLIENTEMACRXCLIENTCLKIN => EMACCLIENTRXBADFRAME) = (100, 100); + ( CLIENTEMACRXCLIENTCLKIN => EMACCLIENTRXCLIENTCLKOUT) = (100, 100); + ( CLIENTEMACRXCLIENTCLKIN => EMACCLIENTRXDVLD) = (100, 100); + ( CLIENTEMACRXCLIENTCLKIN => EMACCLIENTRXDVLDMSW) = (100, 100); + ( CLIENTEMACRXCLIENTCLKIN => EMACCLIENTRXD[0]) = (100, 100); + ( CLIENTEMACRXCLIENTCLKIN => EMACCLIENTRXD[10]) = (100, 100); + ( CLIENTEMACRXCLIENTCLKIN => EMACCLIENTRXD[11]) = (100, 100); + ( CLIENTEMACRXCLIENTCLKIN => EMACCLIENTRXD[12]) = (100, 100); + ( CLIENTEMACRXCLIENTCLKIN => EMACCLIENTRXD[13]) = (100, 100); + ( CLIENTEMACRXCLIENTCLKIN => EMACCLIENTRXD[14]) = (100, 100); + ( CLIENTEMACRXCLIENTCLKIN => EMACCLIENTRXD[15]) = (100, 100); + ( CLIENTEMACRXCLIENTCLKIN => EMACCLIENTRXD[1]) = (100, 100); + ( CLIENTEMACRXCLIENTCLKIN => EMACCLIENTRXD[2]) = (100, 100); + ( CLIENTEMACRXCLIENTCLKIN => EMACCLIENTRXD[3]) = (100, 100); + ( CLIENTEMACRXCLIENTCLKIN => EMACCLIENTRXD[4]) = (100, 100); + ( CLIENTEMACRXCLIENTCLKIN => EMACCLIENTRXD[5]) = (100, 100); + ( CLIENTEMACRXCLIENTCLKIN => EMACCLIENTRXD[6]) = (100, 100); + ( CLIENTEMACRXCLIENTCLKIN => EMACCLIENTRXD[7]) = (100, 100); + ( CLIENTEMACRXCLIENTCLKIN => EMACCLIENTRXD[8]) = (100, 100); + ( CLIENTEMACRXCLIENTCLKIN => EMACCLIENTRXD[9]) = (100, 100); + ( CLIENTEMACRXCLIENTCLKIN => EMACCLIENTRXFRAMEDROP) = (100, 100); + ( CLIENTEMACRXCLIENTCLKIN => EMACCLIENTRXGOODFRAME) = (100, 100); + ( CLIENTEMACRXCLIENTCLKIN => EMACCLIENTRXSTATSBYTEVLD) = (100, 100); + ( CLIENTEMACRXCLIENTCLKIN => EMACCLIENTRXSTATSVLD) = (100, 100); + ( CLIENTEMACRXCLIENTCLKIN => EMACCLIENTRXSTATS[0]) = (100, 100); + ( CLIENTEMACRXCLIENTCLKIN => EMACCLIENTRXSTATS[1]) = (100, 100); + ( CLIENTEMACRXCLIENTCLKIN => EMACCLIENTRXSTATS[2]) = (100, 100); + ( CLIENTEMACRXCLIENTCLKIN => EMACCLIENTRXSTATS[3]) = (100, 100); + ( CLIENTEMACRXCLIENTCLKIN => EMACCLIENTRXSTATS[4]) = (100, 100); + ( CLIENTEMACRXCLIENTCLKIN => EMACCLIENTRXSTATS[5]) = (100, 100); + ( CLIENTEMACRXCLIENTCLKIN => EMACCLIENTRXSTATS[6]) = (100, 100); + ( CLIENTEMACTXCLIENTCLKIN => EMACCLIENTTXACK) = (100, 100); + ( CLIENTEMACTXCLIENTCLKIN => EMACCLIENTTXCOLLISION) = (100, 100); + ( CLIENTEMACTXCLIENTCLKIN => EMACCLIENTTXRETRANSMIT) = (100, 100); + ( CLIENTEMACTXCLIENTCLKIN => EMACCLIENTTXSTATS) = (100, 100); + ( CLIENTEMACTXCLIENTCLKIN => EMACCLIENTTXSTATSBYTEVLD) = (100, 100); + ( CLIENTEMACTXCLIENTCLKIN => EMACCLIENTTXSTATSVLD) = (100, 100); + ( DCREMACCLK => DCRHOSTDONEIR) = (100, 100); + ( DCREMACCLK => EMACDCRACK) = (100, 100); + ( DCREMACCLK => EMACDCRDBUS[0]) = (100, 100); + ( DCREMACCLK => EMACDCRDBUS[10]) = (100, 100); + ( DCREMACCLK => EMACDCRDBUS[11]) = (100, 100); + ( DCREMACCLK => EMACDCRDBUS[12]) = (100, 100); + ( DCREMACCLK => EMACDCRDBUS[13]) = (100, 100); + ( DCREMACCLK => EMACDCRDBUS[14]) = (100, 100); + ( DCREMACCLK => EMACDCRDBUS[15]) = (100, 100); + ( DCREMACCLK => EMACDCRDBUS[16]) = (100, 100); + ( DCREMACCLK => EMACDCRDBUS[17]) = (100, 100); + ( DCREMACCLK => EMACDCRDBUS[18]) = (100, 100); + ( DCREMACCLK => EMACDCRDBUS[19]) = (100, 100); + ( DCREMACCLK => EMACDCRDBUS[1]) = (100, 100); + ( DCREMACCLK => EMACDCRDBUS[20]) = (100, 100); + ( DCREMACCLK => EMACDCRDBUS[21]) = (100, 100); + ( DCREMACCLK => EMACDCRDBUS[22]) = (100, 100); + ( DCREMACCLK => EMACDCRDBUS[23]) = (100, 100); + ( DCREMACCLK => EMACDCRDBUS[24]) = (100, 100); + ( DCREMACCLK => EMACDCRDBUS[25]) = (100, 100); + ( DCREMACCLK => EMACDCRDBUS[26]) = (100, 100); + ( DCREMACCLK => EMACDCRDBUS[27]) = (100, 100); + ( DCREMACCLK => EMACDCRDBUS[28]) = (100, 100); + ( DCREMACCLK => EMACDCRDBUS[29]) = (100, 100); + ( DCREMACCLK => EMACDCRDBUS[2]) = (100, 100); + ( DCREMACCLK => EMACDCRDBUS[30]) = (100, 100); + ( DCREMACCLK => EMACDCRDBUS[31]) = (100, 100); + ( DCREMACCLK => EMACDCRDBUS[3]) = (100, 100); + ( DCREMACCLK => EMACDCRDBUS[4]) = (100, 100); + ( DCREMACCLK => EMACDCRDBUS[5]) = (100, 100); + ( DCREMACCLK => EMACDCRDBUS[6]) = (100, 100); + ( DCREMACCLK => EMACDCRDBUS[7]) = (100, 100); + ( DCREMACCLK => EMACDCRDBUS[8]) = (100, 100); + ( DCREMACCLK => EMACDCRDBUS[9]) = (100, 100); + ( HOSTCLK => EMACPHYMCLKOUT) = (100, 100); + ( HOSTCLK => EMACPHYMDOUT) = (100, 100); + ( HOSTCLK => EMACPHYMDTRI) = (100, 100); + ( HOSTCLK => EMACSPEEDIS10100) = (100, 100); + ( HOSTCLK => HOSTMIIMRDY) = (100, 100); + ( HOSTCLK => HOSTRDDATA[0]) = (100, 100); + ( HOSTCLK => HOSTRDDATA[10]) = (100, 100); + ( HOSTCLK => HOSTRDDATA[11]) = (100, 100); + ( HOSTCLK => HOSTRDDATA[12]) = (100, 100); + ( HOSTCLK => HOSTRDDATA[13]) = (100, 100); + ( HOSTCLK => HOSTRDDATA[14]) = (100, 100); + ( HOSTCLK => HOSTRDDATA[15]) = (100, 100); + ( HOSTCLK => HOSTRDDATA[16]) = (100, 100); + ( HOSTCLK => HOSTRDDATA[17]) = (100, 100); + ( HOSTCLK => HOSTRDDATA[18]) = (100, 100); + ( HOSTCLK => HOSTRDDATA[19]) = (100, 100); + ( HOSTCLK => HOSTRDDATA[1]) = (100, 100); + ( HOSTCLK => HOSTRDDATA[20]) = (100, 100); + ( HOSTCLK => HOSTRDDATA[21]) = (100, 100); + ( HOSTCLK => HOSTRDDATA[22]) = (100, 100); + ( HOSTCLK => HOSTRDDATA[23]) = (100, 100); + ( HOSTCLK => HOSTRDDATA[24]) = (100, 100); + ( HOSTCLK => HOSTRDDATA[25]) = (100, 100); + ( HOSTCLK => HOSTRDDATA[26]) = (100, 100); + ( HOSTCLK => HOSTRDDATA[27]) = (100, 100); + ( HOSTCLK => HOSTRDDATA[28]) = (100, 100); + ( HOSTCLK => HOSTRDDATA[29]) = (100, 100); + ( HOSTCLK => HOSTRDDATA[2]) = (100, 100); + ( HOSTCLK => HOSTRDDATA[30]) = (100, 100); + ( HOSTCLK => HOSTRDDATA[31]) = (100, 100); + ( HOSTCLK => HOSTRDDATA[3]) = (100, 100); + ( HOSTCLK => HOSTRDDATA[4]) = (100, 100); + ( HOSTCLK => HOSTRDDATA[5]) = (100, 100); + ( HOSTCLK => HOSTRDDATA[6]) = (100, 100); + ( HOSTCLK => HOSTRDDATA[7]) = (100, 100); + ( HOSTCLK => HOSTRDDATA[8]) = (100, 100); + ( HOSTCLK => HOSTRDDATA[9]) = (100, 100); + ( PHYEMACGTXCLK => EMACCLIENTANINTERRUPT) = (100, 100); + ( PHYEMACGTXCLK => EMACCLIENTRXCLIENTCLKOUT) = (100, 100); + ( PHYEMACGTXCLK => EMACCLIENTTXCLIENTCLKOUT) = (100, 100); + ( PHYEMACGTXCLK => EMACPHYENCOMMAALIGN) = (100, 100); + ( PHYEMACGTXCLK => EMACPHYLOOPBACKMSB) = (100, 100); + ( PHYEMACGTXCLK => EMACPHYMGTRXRESET) = (100, 100); + ( PHYEMACGTXCLK => EMACPHYMGTTXRESET) = (100, 100); + ( PHYEMACGTXCLK => EMACPHYPOWERDOWN) = (100, 100); + ( PHYEMACGTXCLK => EMACPHYSYNCACQSTATUS) = (100, 100); + ( PHYEMACGTXCLK => EMACPHYTXCHARDISPMODE) = (100, 100); + ( PHYEMACGTXCLK => EMACPHYTXCHARDISPVAL) = (100, 100); + ( PHYEMACGTXCLK => EMACPHYTXCHARISK) = (100, 100); + ( PHYEMACGTXCLK => EMACPHYTXCLK) = (100, 100); + ( PHYEMACGTXCLK => EMACPHYTXD[0]) = (100, 100); + ( PHYEMACGTXCLK => EMACPHYTXD[1]) = (100, 100); + ( PHYEMACGTXCLK => EMACPHYTXD[2]) = (100, 100); + ( PHYEMACGTXCLK => EMACPHYTXD[3]) = (100, 100); + ( PHYEMACGTXCLK => EMACPHYTXD[4]) = (100, 100); + ( PHYEMACGTXCLK => EMACPHYTXD[5]) = (100, 100); + ( PHYEMACGTXCLK => EMACPHYTXD[6]) = (100, 100); + ( PHYEMACGTXCLK => EMACPHYTXD[7]) = (100, 100); + ( PHYEMACGTXCLK => EMACPHYTXEN) = (100, 100); + ( PHYEMACGTXCLK => EMACPHYTXER) = (100, 100); + ( PHYEMACGTXCLK => EMACPHYTXGMIIMIICLKOUT) = (100, 100); + ( PHYEMACMCLKIN => EMACPHYMCLKOUT) = (100, 100); + ( PHYEMACMCLKIN => EMACPHYMDOUT) = (100, 100); + ( PHYEMACMCLKIN => EMACPHYMDTRI) = (100, 100); + ( PHYEMACMIITXCLK => EMACCLIENTRXBADFRAME) = (100, 100); + ( PHYEMACMIITXCLK => EMACCLIENTRXCLIENTCLKOUT) = (100, 100); + ( PHYEMACMIITXCLK => EMACCLIENTRXDVLD) = (100, 100); + ( PHYEMACMIITXCLK => EMACCLIENTRXDVLDMSW) = (100, 100); + ( PHYEMACMIITXCLK => EMACCLIENTRXD[0]) = (100, 100); + ( PHYEMACMIITXCLK => EMACCLIENTRXD[10]) = (100, 100); + ( PHYEMACMIITXCLK => EMACCLIENTRXD[11]) = (100, 100); + ( PHYEMACMIITXCLK => EMACCLIENTRXD[12]) = (100, 100); + ( PHYEMACMIITXCLK => EMACCLIENTRXD[13]) = (100, 100); + ( PHYEMACMIITXCLK => EMACCLIENTRXD[14]) = (100, 100); + ( PHYEMACMIITXCLK => EMACCLIENTRXD[15]) = (100, 100); + ( PHYEMACMIITXCLK => EMACCLIENTRXD[1]) = (100, 100); + ( PHYEMACMIITXCLK => EMACCLIENTRXD[2]) = (100, 100); + ( PHYEMACMIITXCLK => EMACCLIENTRXD[3]) = (100, 100); + ( PHYEMACMIITXCLK => EMACCLIENTRXD[4]) = (100, 100); + ( PHYEMACMIITXCLK => EMACCLIENTRXD[5]) = (100, 100); + ( PHYEMACMIITXCLK => EMACCLIENTRXD[6]) = (100, 100); + ( PHYEMACMIITXCLK => EMACCLIENTRXD[7]) = (100, 100); + ( PHYEMACMIITXCLK => EMACCLIENTRXD[8]) = (100, 100); + ( PHYEMACMIITXCLK => EMACCLIENTRXD[9]) = (100, 100); + ( PHYEMACMIITXCLK => EMACCLIENTRXFRAMEDROP) = (100, 100); + ( PHYEMACMIITXCLK => EMACCLIENTRXGOODFRAME) = (100, 100); + ( PHYEMACMIITXCLK => EMACCLIENTTXACK) = (100, 100); + ( PHYEMACMIITXCLK => EMACCLIENTTXCLIENTCLKOUT) = (100, 100); + ( PHYEMACMIITXCLK => EMACCLIENTTXCOLLISION) = (100, 100); + ( PHYEMACMIITXCLK => EMACCLIENTTXRETRANSMIT) = (100, 100); + ( PHYEMACMIITXCLK => EMACPHYTXGMIIMIICLKOUT) = (100, 100); + ( PHYEMACRXCLK => EMACCLIENTRXBADFRAME) = (100, 100); + ( PHYEMACRXCLK => EMACCLIENTRXCLIENTCLKOUT) = (100, 100); + ( PHYEMACRXCLK => EMACCLIENTRXDVLD) = (100, 100); + ( PHYEMACRXCLK => EMACCLIENTRXDVLDMSW) = (100, 100); + ( PHYEMACRXCLK => EMACCLIENTRXD[0]) = (100, 100); + ( PHYEMACRXCLK => EMACCLIENTRXD[10]) = (100, 100); + ( PHYEMACRXCLK => EMACCLIENTRXD[11]) = (100, 100); + ( PHYEMACRXCLK => EMACCLIENTRXD[12]) = (100, 100); + ( PHYEMACRXCLK => EMACCLIENTRXD[13]) = (100, 100); + ( PHYEMACRXCLK => EMACCLIENTRXD[14]) = (100, 100); + ( PHYEMACRXCLK => EMACCLIENTRXD[15]) = (100, 100); + ( PHYEMACRXCLK => EMACCLIENTRXD[1]) = (100, 100); + ( PHYEMACRXCLK => EMACCLIENTRXD[2]) = (100, 100); + ( PHYEMACRXCLK => EMACCLIENTRXD[3]) = (100, 100); + ( PHYEMACRXCLK => EMACCLIENTRXD[4]) = (100, 100); + ( PHYEMACRXCLK => EMACCLIENTRXD[5]) = (100, 100); + ( PHYEMACRXCLK => EMACCLIENTRXD[6]) = (100, 100); + ( PHYEMACRXCLK => EMACCLIENTRXD[7]) = (100, 100); + ( PHYEMACRXCLK => EMACCLIENTRXD[8]) = (100, 100); + ( PHYEMACRXCLK => EMACCLIENTRXD[9]) = (100, 100); + ( PHYEMACRXCLK => EMACCLIENTRXFRAMEDROP) = (100, 100); + ( PHYEMACRXCLK => EMACCLIENTRXGOODFRAME) = (100, 100); + ( PHYEMACRXCLK => EMACCLIENTRXSTATSBYTEVLD) = (100, 100); + ( PHYEMACRXCLK => EMACCLIENTRXSTATSVLD) = (100, 100); + ( PHYEMACRXCLK => EMACCLIENTRXSTATS[0]) = (100, 100); + ( PHYEMACRXCLK => EMACCLIENTRXSTATS[1]) = (100, 100); + ( PHYEMACRXCLK => EMACCLIENTRXSTATS[2]) = (100, 100); + ( PHYEMACRXCLK => EMACCLIENTRXSTATS[3]) = (100, 100); + ( PHYEMACRXCLK => EMACCLIENTRXSTATS[4]) = (100, 100); + ( PHYEMACRXCLK => EMACCLIENTRXSTATS[5]) = (100, 100); + ( PHYEMACRXCLK => EMACCLIENTRXSTATS[6]) = (100, 100); + ( PHYEMACTXGMIIMIICLKIN => EMACCLIENTTXACK) = (100, 100); + ( PHYEMACTXGMIIMIICLKIN => EMACCLIENTTXCLIENTCLKOUT) = (100, 100); + ( PHYEMACTXGMIIMIICLKIN => EMACCLIENTTXCOLLISION) = (100, 100); + ( PHYEMACTXGMIIMIICLKIN => EMACCLIENTTXRETRANSMIT) = (100, 100); + ( PHYEMACTXGMIIMIICLKIN => EMACCLIENTTXSTATS) = (100, 100); + ( PHYEMACTXGMIIMIICLKIN => EMACCLIENTTXSTATSBYTEVLD) = (100, 100); + ( PHYEMACTXGMIIMIICLKIN => EMACCLIENTTXSTATSVLD) = (100, 100); + ( PHYEMACTXGMIIMIICLKIN => EMACPHYSYNCACQSTATUS) = (100, 100); + ( PHYEMACTXGMIIMIICLKIN => EMACPHYTXCHARDISPMODE) = (100, 100); + ( PHYEMACTXGMIIMIICLKIN => EMACPHYTXCHARDISPVAL) = (100, 100); + ( PHYEMACTXGMIIMIICLKIN => EMACPHYTXCHARISK) = (100, 100); + ( PHYEMACTXGMIIMIICLKIN => EMACPHYTXCLK) = (100, 100); + ( PHYEMACTXGMIIMIICLKIN => EMACPHYTXD[0]) = (100, 100); + ( PHYEMACTXGMIIMIICLKIN => EMACPHYTXD[1]) = (100, 100); + ( PHYEMACTXGMIIMIICLKIN => EMACPHYTXD[2]) = (100, 100); + ( PHYEMACTXGMIIMIICLKIN => EMACPHYTXD[3]) = (100, 100); + ( PHYEMACTXGMIIMIICLKIN => EMACPHYTXD[4]) = (100, 100); + ( PHYEMACTXGMIIMIICLKIN => EMACPHYTXD[5]) = (100, 100); + ( PHYEMACTXGMIIMIICLKIN => EMACPHYTXD[6]) = (100, 100); + ( PHYEMACTXGMIIMIICLKIN => EMACPHYTXD[7]) = (100, 100); + ( PHYEMACTXGMIIMIICLKIN => EMACPHYTXEN) = (100, 100); + ( PHYEMACTXGMIIMIICLKIN => EMACPHYTXER) = (100, 100); + + specparam PATHPULSE$ = 0; + endspecify +endmodule diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/TIMEGRP.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/TIMEGRP.v new file mode 100644 index 0000000..c439ae0 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/TIMEGRP.v @@ -0,0 +1,26 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/TIMEGRP.v,v 1.5 2007/05/23 21:43:44 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / +// /___/ /\ Filename : TIMEGRP.v +// \ \ / \ Timestamp : Thu Mar 25 16:43:41 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. + +`timescale 1 ps / 1 ps + + +module TIMEGRP (); + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/TIMESPEC.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/TIMESPEC.v new file mode 100644 index 0000000..bb2a98b --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/TIMESPEC.v @@ -0,0 +1,26 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/TIMESPEC.v,v 1.5 2007/05/23 21:43:44 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / +// /___/ /\ Filename : TIMESPEC.v +// \ \ / \ Timestamp : Thu Mar 25 16:43:41 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. + +`timescale 1 ps / 1 ps + + +module TIMESPEC (); + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/USR_ACCESS_VIRTEX4.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/USR_ACCESS_VIRTEX4.v new file mode 100644 index 0000000..5da5ed4 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/USR_ACCESS_VIRTEX4.v @@ -0,0 +1,28 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/virtex4/USR_ACCESS_VIRTEX4.v,v 1.4 2007/06/06 22:14:07 fphillip Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / +// /___/ /\ Filename : USR_ACCESS_VIRTEX4.v +// \ \ / \ Timestamp : Thu Mar 25 16:43:52 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 06/06/07 - Fixed timescale values +// End Revision + +`timescale 100 ps / 10 ps + +module USR_ACCESS_VIRTEX4 (DATA, DATAVALID); + + output [31:0] DATA; + output DATAVALID; + +endmodule // USR_ACCESS_VIRTEX4 diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/USR_ACCESS_VIRTEX5.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/USR_ACCESS_VIRTEX5.v new file mode 100644 index 0000000..ba2d8e9 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/USR_ACCESS_VIRTEX5.v @@ -0,0 +1,35 @@ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / +// /___/ /\ Filename : USR_ACCESS_VIRTEX5.v +// \ \ / \ Timestamp : Thu Jul 21 13:42:30 PDT 2005 +// \___\/\___\ +// +// Revision: +// 07/21/05 - Initial version. +// End Revision + +`timescale 1 ps / 1 ps + +module USR_ACCESS_VIRTEX5 ( + CFGCLK, + DATA, + DATAVALID +); + +output CFGCLK; +output DATAVALID; +output [31:0] DATA; + +specify + specparam PATHPULSE$ = 0; +endspecify + +endmodule diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/USR_ACCESS_VIRTEX6.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/USR_ACCESS_VIRTEX6.v new file mode 100644 index 0000000..f31388d --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/USR_ACCESS_VIRTEX6.v @@ -0,0 +1,32 @@ +/////////////////////////////////////////////////////// +// Copyright (c) 1995/2006 Xilinx Inc. +// All Right Reserved. +/////////////////////////////////////////////////////// +// +// ____ ___ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : +// / / +// /__/ /\ Filename : USR_ACCESS_VIRTEX6.v +// \ \ / \ +// \__\/\__ \ +// +// Revision: 1.0 +/////////////////////////////////////////////////////// + +`timescale 1 ps / 1 ps + +module USR_ACCESS_VIRTEX6 ( + CFGCLK, + DATA, + DATAVALID +); + + output CFGCLK; + output DATAVALID; + output [31:0] DATA; + + +endmodule diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/VCC.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/VCC.v new file mode 100644 index 0000000..676c222 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/VCC.v @@ -0,0 +1,30 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/VCC.v,v 1.5 2007/05/23 21:43:44 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / VCC Connection +// /___/ /\ Filename : VCC.v +// \ \ / \ Timestamp : Thu Mar 25 16:43:41 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. + +`timescale 1 ps / 1 ps + + +module VCC(P); + + output P; + + assign P = 1'b1; + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/XNOR2.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/XNOR2.v new file mode 100644 index 0000000..dbacc69 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/XNOR2.v @@ -0,0 +1,33 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/XNOR2.v,v 1.6 2007/05/23 21:43:44 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / 2-input XNOR Gate +// /___/ /\ Filename : XNOR2.v +// \ \ / \ Timestamp : Thu Mar 25 16:43:41 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. + +`timescale 1 ps / 1 ps + + +module XNOR2 (O, I0, I1); + + output O; + + input I0, I1; + + xnor X1 (O, I0, I1); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/XNOR3.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/XNOR3.v new file mode 100644 index 0000000..c90a553 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/XNOR3.v @@ -0,0 +1,33 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/XNOR3.v,v 1.6 2007/05/23 21:43:44 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / 3-input XNOR Gate +// /___/ /\ Filename : XNOR3.v +// \ \ / \ Timestamp : Thu Mar 25 16:43:42 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. + +`timescale 1 ps / 1 ps + + +module XNOR3 (O, I0, I1, I2); + + output O; + + input I0, I1, I2; + + xnor X1 (O, I0, I1, I2); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/XNOR4.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/XNOR4.v new file mode 100644 index 0000000..602487b --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/XNOR4.v @@ -0,0 +1,33 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/XNOR4.v,v 1.6 2007/05/23 21:43:44 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / 4-input XNOR Gate +// /___/ /\ Filename : XNOR4.v +// \ \ / \ Timestamp : Thu Mar 25 16:43:42 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. + +`timescale 1 ps / 1 ps + + +module XNOR4 (O, I0, I1, I2, I3); + + output O; + + input I0, I1, I2, I3; + + xnor X1 (O, I0, I1, I2, I3); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/XNOR5.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/XNOR5.v new file mode 100644 index 0000000..7c5026b --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/XNOR5.v @@ -0,0 +1,33 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/XNOR5.v,v 1.6 2007/05/23 21:43:44 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / 5-input XNOR Gate +// /___/ /\ Filename : XNOR5.v +// \ \ / \ Timestamp : Thu Mar 25 16:43:42 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. + +`timescale 1 ps / 1 ps + + +module XNOR5 (O, I0, I1, I2, I3, I4); + + output O; + + input I0, I1, I2, I3, I4; + + xnor X1 (O, I0, I1, I2, I3, I4); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/XOR2.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/XOR2.v new file mode 100644 index 0000000..73a291f --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/XOR2.v @@ -0,0 +1,33 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/XOR2.v,v 1.6 2007/05/23 21:43:44 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / 2-input XOR Gate +// /___/ /\ Filename : XOR2.v +// \ \ / \ Timestamp : Thu Mar 25 16:43:42 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. + +`timescale 1 ps / 1 ps + + +module XOR2 (O, I0, I1); + + output O; + + input I0, I1; + + xor X1 (O, I0, I1); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/XOR3.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/XOR3.v new file mode 100644 index 0000000..acc3a0a --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/XOR3.v @@ -0,0 +1,33 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/XOR3.v,v 1.6 2007/05/23 21:43:44 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / 3-input XOR Gate +// /___/ /\ Filename : XOR3.v +// \ \ / \ Timestamp : Thu Mar 25 16:43:42 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. + +`timescale 1 ps / 1 ps + + +module XOR3 (O, I0, I1, I2); + + output O; + + input I0, I1, I2; + + xor X1 (O, I0, I1, I2); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/XOR4.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/XOR4.v new file mode 100644 index 0000000..2079928 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/XOR4.v @@ -0,0 +1,33 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/XOR4.v,v 1.6 2007/05/23 21:43:44 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / 4-input XOR Gate +// /___/ /\ Filename : XOR4.v +// \ \ / \ Timestamp : Thu Mar 25 16:43:42 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. + +`timescale 1 ps / 1 ps + + +module XOR4 (O, I0, I1, I2, I3); + + output O; + + input I0, I1, I2, I3; + + xor X1 (O, I0, I1, I2, I3); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/XOR5.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/XOR5.v new file mode 100644 index 0000000..77dbda1 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/XOR5.v @@ -0,0 +1,33 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/XOR5.v,v 1.6 2007/05/23 21:43:44 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / 5-input XOR Gate +// /___/ /\ Filename : XOR5.v +// \ \ / \ Timestamp : Thu Mar 25 16:43:42 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. + +`timescale 1 ps / 1 ps + + +module XOR5 (O, I0, I1, I2, I3, I4); + + output O; + + input I0, I1, I2, I3, I4; + + xor X1 (O, I0, I1, I2, I3, I4); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/XORCY.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/XORCY.v new file mode 100644 index 0000000..6493869 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/XORCY.v @@ -0,0 +1,33 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/XORCY.v,v 1.6 2007/05/23 21:43:44 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / XOR for Carry Logic with General Output +// /___/ /\ Filename : XORCY.v +// \ \ / \ Timestamp : Thu Mar 25 16:43:42 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. + +`timescale 1 ps / 1 ps + + +module XORCY (O, CI, LI); + + output O; + + input CI, LI; + + xor X1 (O, CI, LI); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/XORCY_D.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/XORCY_D.v new file mode 100644 index 0000000..9430b87 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/XORCY_D.v @@ -0,0 +1,34 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/XORCY_D.v,v 1.6 2007/05/23 21:43:44 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / XOR for Carry Logic with Dual Output +// /___/ /\ Filename : XORCY_D.v +// \ \ / \ Timestamp : Thu Mar 25 16:43:42 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. + +`timescale 1 ps / 1 ps + + +module XORCY_D (LO, O, CI, LI); + + output LO, O; + + input CI, LI; + + xor X1 (O, CI, LI); + xor X2 (LO, CI, LI); + + +endmodule + diff --git a/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/XORCY_L.v b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/XORCY_L.v new file mode 100644 index 0000000..8afa221 --- /dev/null +++ b/verilog/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/XORCY_L.v @@ -0,0 +1,33 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/XORCY_L.v,v 1.6 2007/05/23 21:43:44 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / XOR for Carry Logic with Local Output +// /___/ /\ Filename : XORCY_L.v +// \ \ / \ Timestamp : Thu Mar 25 16:43:42 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 05/23/07 - Changed timescale to 1 ps / 1 ps. + +`timescale 1 ps / 1 ps + + +module XORCY_L (LO, CI, LI); + + output LO; + + input CI, LI; + + xor X1 (LO, CI, LI); + + +endmodule + diff --git a/verilog/atan_lut.coe b/verilog/atan_lut.coe new file mode 100644 index 0000000..d764cb3 --- /dev/null +++ b/verilog/atan_lut.coe @@ -0,0 +1,258 @@ +memory_initialization_radix=2; +memory_initialization_vector= +000000000, +000000010, +000000100, +000000110, +000001000, +000001010, +000001100, +000001110, +000010000, +000010010, +000010100, +000010110, +000011000, +000011010, +000011100, +000011110, +000100000, +000100010, +000100100, +000100110, +000101000, +000101010, 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+011000111, +011001001, +011001011, +011001100, +011001110, +011010000, +011010001, +011010011, +011010101, +011010111, +011011000, +011011010, +011011011, +011011101, +011011111, +011100000, +011100010, +011100100, +011100101, +011100111, +011101001, +011101010, +011101100, +011101101, +011101111, +011110001, +011110010, +011110100, +011110101, +011110111, +011111000, +011111010, +011111100, +011111101, +011111111, +100000000, +100000010, +100000011, +100000101, +100000110, +100001000, +100001001, +100001011, +100001100, +100001110, +100001111, +100010001, +100010010, +100010100, +100010101, +100010111, +100011000, +100011010, +100011011, +100011101, +100011110, +100011111, +100100001, +100100010, +100100100, +100100101, +100100111, +100101000, +100101001, +100101011, +100101100, +100101110, +100101111, +100110000, +100110010, +100110011, +100110100, +100110110, +100110111, +100111000, +100111010, +100111011, +100111100, +100111110, +100111111, +101000000, +101000010, +101000011, +101000100, +101000110, +101000111, +101001000, +101001001, +101001011, +101001100, +101001101, +101001111, +101010000, +101010001, +101010010, +101010100, +101010101, +101010110, +101010111, +101011000, +101011010, +101011011, +101011100, +101011101, +101011111, +101100000, +101100001, +101100010, +101100011, +101100100, +101100110, +101100111, +101101000, +101101001, +101101010, +101101011, +101101101, +101101110, +101101111, +101110000, +101110001, +101110010, +101110011, +101110101, +101110110, +101110111, +101111000, +101111001, +101111010, +101111011, +101111100, +101111101, +101111110, +101111111, +110000001, +110000010, +110000011, +110000100, +110000101, +110000110, +110000111, +110001000, +110001001, +110001010, +110001011, +110001100, +110001101, +110001110, +110001111, +110010000, +110010001; \ No newline at end of file diff --git a/verilog/atan_lut.mif b/verilog/atan_lut.mif new file mode 100644 index 0000000..66f443f --- /dev/null +++ b/verilog/atan_lut.mif @@ -0,0 +1,256 @@ +000000000 +000000010 +000000100 +000000110 +000001000 +000001010 +000001100 +000001110 +000010000 +000010010 +000010100 +000010110 +000011000 +000011010 +000011100 +000011110 +000100000 +000100010 +000100100 +000100110 +000101000 +000101010 +000101100 +000101110 +000110000 +000110010 +000110100 +000110110 +000111000 +000111010 +000111100 +000111110 +001000000 +001000010 +001000100 +001000110 +001001000 +001001001 +001001011 +001001101 +001001111 +001010001 +001010011 +001010101 +001010111 +001011001 +001011011 +001011101 +001011111 +001100001 +001100011 +001100101 +001100111 +001101001 +001101010 +001101100 +001101110 +001110000 +001110010 +001110100 +001110110 +001111000 +001111010 +001111100 +001111101 +001111111 +010000001 +010000011 +010000101 +010000111 +010001001 +010001011 +010001100 +010001110 +010010000 +010010010 +010010100 +010010110 +010010111 +010011001 +010011011 +010011101 +010011111 +010100001 +010100010 +010100100 +010100110 +010101000 +010101010 +010101011 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+100111011 +100111100 +100111110 +100111111 +101000000 +101000010 +101000011 +101000100 +101000110 +101000111 +101001000 +101001001 +101001011 +101001100 +101001101 +101001111 +101010000 +101010001 +101010010 +101010100 +101010101 +101010110 +101010111 +101011000 +101011010 +101011011 +101011100 +101011101 +101011111 +101100000 +101100001 +101100010 +101100011 +101100100 +101100110 +101100111 +101101000 +101101001 +101101010 +101101011 +101101101 +101101110 +101101111 +101110000 +101110001 +101110010 +101110011 +101110101 +101110110 +101110111 +101111000 +101111001 +101111010 +101111011 +101111100 +101111101 +101111110 +101111111 +110000001 +110000010 +110000011 +110000100 +110000101 +110000110 +110000111 +110001000 +110001001 +110001010 +110001011 +110001100 +110001101 +110001110 +110001111 +110010000 +110010001 diff --git a/verilog/atan_lut.v b/verilog/atan_lut.v new file mode 100644 index 0000000..899f884 --- /dev/null +++ b/verilog/atan_lut.v @@ -0,0 +1,21 @@ +`include "common_defs.v" + +/* +* Output: atan(addr/1024.0)*2048 +* Delay: 1 cycle +*/ +module atan_lut ( + input clka, + input [`ATAN_LUT_LEN_SHIFT-1:0] addra, + output reg [`ATAN_LUT_SCALE_SHIFT-1:0] douta +); + +reg [`ATAN_LUT_SCALE_SHIFT-1:0] ram [0:(1<<`ATAN_LUT_LEN_SHIFT)-1]; +initial begin + $readmemb("./atan_lut.mif", ram); +end + +always @(posedge clka) begin + douta <= ram[addra]; +end +endmodule diff --git a/verilog/bits_to_bytes.v b/verilog/bits_to_bytes.v new file mode 100644 index 0000000..c510ed3 --- /dev/null +++ b/verilog/bits_to_bytes.v @@ -0,0 +1,37 @@ +module bits_to_bytes +( + input clock, + input enable, + input reset, + + input bit_in, + input input_strobe, + + output reg [7:0] byte_out, + output reg output_strobe +); + +reg [7:0] bit_buf; +reg [2:0] addr; + +always @(posedge clock) begin + if (reset) begin + addr <= 0; + bit_buf <= 0; + byte_out <= 0; + output_strobe <= 0; + end else if (enable & input_strobe) begin + bit_buf[7] <= bit_in; + bit_buf[6:0] <= bit_buf[7:1]; + addr <= addr + 1; + if (addr == 7) begin + byte_out <= {bit_in, bit_buf[7:1]}; + output_strobe <= 1; + end else begin + output_strobe <= 0; + end + end else begin + output_strobe <= 0; + end +end +endmodule diff --git a/verilog/calc_mean.v b/verilog/calc_mean.v new file mode 100644 index 0000000..d0b79df --- /dev/null +++ b/verilog/calc_mean.v @@ -0,0 +1,46 @@ +module calc_mean +( + input clock, + input enable, + input reset, + + input signed [15:0] a, + input signed [15:0] b, + input sign, + input input_strobe, + + output reg signed [15:0] c, + output reg output_strobe +); + +reg signed [15:0] aa; +reg signed [15:0] bb; +reg signed [15:0] cc; + +reg [1:0] delay; +reg [1:0] sign_stage; + +always @(posedge clock) begin + if (reset) begin + aa <= 0; + bb <= 0; + cc <= 0; + c <= 0; + output_strobe <= 0; + delay <= 0; + end else if (enable) begin + delay[0] <= input_strobe; + delay[1] <= delay[0]; + output_strobe <= delay[1]; + sign_stage[1] <= sign_stage[0]; + sign_stage[0] <= sign; + + aa <= a>>>1; + bb <= b>>>1; + cc <= aa + bb; + c <= sign_stage[1]? ~cc+1: cc; + end +end + +endmodule + diff --git a/verilog/common_defs.v b/verilog/common_defs.v new file mode 100644 index 0000000..86b26d1 --- /dev/null +++ b/verilog/common_defs.v @@ -0,0 +1,9 @@ +`define ATAN_LUT_LEN_SHIFT 8 +// changing this requires changing PI definition in common_params.v accordingly +`define ATAN_LUT_SCALE_SHIFT 9 + +`define ROTATE_LUT_LEN_SHIFT `ATAN_LUT_SCALE_SHIFT +`define ROTATE_LUT_SCALE_SHIFT 11 + + +`define CONS_SCALE_SHIFT 10 diff --git a/verilog/common_params.v b/verilog/common_params.v new file mode 100644 index 0000000..1392a70 --- /dev/null +++ b/verilog/common_params.v @@ -0,0 +1,94 @@ +////////////////////////////////////////////////////////////////////////// +// JAM FILTER STATUS +////////////////////////////////////////////////////////////////////////// +localparam FILTER_NO_MATCH = 0; +localparam FILTER_MATCH_PASS = 1; +localparam FILTER_MATCH_JAM = 2; +localparam FILTER_MATCH_JAM_ACK = 3; +localparam FILTER_RATIO_PASS = 4; +localparam FILTER_RATIO_JAM = 5; + + +////////////////////////////////////////////////////////////////////////// +// PI DEFINITION +////////////////////////////////////////////////////////////////////////// +// localparam PI = 3217; // = PI*(1<<`ATAN_LUT_SCALE_SHIFT) +// localparam PI = 3217*2; // = PI*(1<<`ATAN_LUT_SCALE_SHIFT) +localparam PI = 1608; // = PI*(1<<`ATAN_LUT_SCALE_SHIFT) +localparam DOUBLE_PI = PI<<1; +localparam PI_2 = PI>>1; +localparam PI_4 = PI>>2; +localparam PI_3_4 = PI_2 + PI_4; + + +////////////////////////////////////////////////////////////////////////// +// USER REG DEFINITION +////////////////////////////////////////////////////////////////////////// +localparam SR_JAMMER_ENABLE = 1; +localparam SR_JAMMER_RESET = 2; + +// power trigger +localparam SR_POWER_THRES = 3; +localparam SR_POWER_WINDOW = 4; +localparam SR_SKIP_SAMPLE = 5; + +// sync short +localparam SR_MIN_PLATEAU = 6; + +// filter +localparam SR_RATE_FILTER = 7; +localparam SR_LEN_FILTER = 8; +localparam SR_HEADER_FILTER = 9; +localparam SR_HEADER_LEN = 10; +localparam SR_JAM_POLICY = 11; + +localparam SR_JAM_SIGNAL = 12; + +////////////////////////////////////////////////////////////////////////// +// DOT11 STATE MACHINE +////////////////////////////////////////////////////////////////////////// +localparam S_WAIT_POWER_TRIGGER = 0; +localparam S_SYNC_SHORT = 1; +localparam S_SYNC_LONG = 2; +localparam S_DECODE_SIGNAL = 3; +localparam S_CHECK_SIGNAL = 4; +localparam S_DETECT_HT = 5; +localparam S_HT_SIGNAL = 6; +localparam S_CHECK_HT_SIG_CRC = 7; +localparam S_CHECK_HT_SIG = 8; +localparam S_HT_STS = 9; +localparam S_HT_LTS = 10; +localparam S_DECODE_DATA = 11; +localparam S_SIGNAL_ERROR = 12; +localparam S_HT_SIG_ERROR = 13; +localparam S_DECODE_DONE = 14; + + +////////////////////////////////////////////////////////////////////////// +// DOT11 STATUS CODE +////////////////////////////////////////////////////////////////////////// +// same value may have different meaning depend on the state +localparam E_OK = 0; + +// errors in SIGNAL +localparam E_PARITY_FAIL = 1; +localparam E_UNSUPPORTED_RATE = 2; +localparam E_WRONG_RSVD = 3; +localparam E_WRONG_TAIL = 4; + +// erros in HT-SIGNAL +localparam E_UNSUPPORTED_MCS = 1; +localparam E_UNSUPPORTED_CBW = 2; +localparam E_HT_WRONG_RSVD = 3; +localparam E_UNSUPPORTED_STBC = 4; +localparam E_UNSUPPORTED_FEC = 5; +localparam E_UNSUPPORTED_SGI = 6; +localparam E_UNSUPPORTED_SPATIAL = 7; +localparam E_HT_WRONG_TAIL = 8; +localparam E_WRONG_CRC = 9; + +// fcs error +localparam E_WRONG_FCS = 1; + + +localparam EXPECTED_FCS = 32'hc704dd7b; diff --git a/verilog/complex_mult.v b/verilog/complex_mult.v new file mode 100644 index 0000000..82d1495 --- /dev/null +++ b/verilog/complex_mult.v @@ -0,0 +1,67 @@ +module complex_mult +( + input clock, + input enable, + input reset, + + input [15:0] a_i, + input [15:0] a_q, + input [15:0] b_i, + input [15:0] b_q, + input input_strobe, + + output reg [31:0] p_i, + output reg [31:0] p_q, + output output_strobe +); + +localparam DELAY = 4; +reg [DELAY-1:0] delay; + +reg [15:0] ar; +reg [15:0] ai; +reg [15:0] br; +reg [15:0] bi; + +wire [31:0] prod_i; +wire [31:0] prod_q; + +complex_multiplier mult_inst ( + .clk(clock), + .ar(ar), + .ai(ai), + .br(br), + .bi(bi), + .pr(prod_i), + .pi(prod_q) +); + +delayT #(.DATA_WIDTH(1), .DELAY(5)) stb_delay_inst ( + .clock(clock), + .reset(reset), + + .data_in(input_strobe), + .data_out(output_strobe) +); + +always @(posedge clock) begin + if (reset) begin + ar <= 0; + ai <= 0; + br <= 0; + bi <= 0; + p_i <= 0; + p_q <= 0; + delay <= 0; + end else if (enable) begin + ar <= a_i; + ai <= a_q; + br <= b_i; + bi <= b_q; + + p_i <= prod_i; + p_q <= prod_q; + end +end + +endmodule diff --git a/verilog/complex_to_mag.v b/verilog/complex_to_mag.v new file mode 100644 index 0000000..935de2a --- /dev/null +++ b/verilog/complex_to_mag.v @@ -0,0 +1,56 @@ +module complex_to_mag +#( + parameter DATA_WIDTH = 16 +) +( + input clock, + input enable, + input reset, + + input signed [DATA_WIDTH-1:0] i, + input signed [DATA_WIDTH-1:0] q, + input input_strobe, + + output reg [DATA_WIDTH-1:0] mag, + output reg mag_stb +); + +reg stage1; +reg stage2; + +reg [DATA_WIDTH-1:0] abs_i; +reg [DATA_WIDTH-1:0] abs_q; + +reg [DATA_WIDTH-1:0] max; +reg[ DATA_WIDTH-1:0] min; + +// http://dspguru.com/dsp/tricks/magnitude-estimator +// alpha = 1, beta = 1/4 +// avg err 0.006 +always @(posedge clock) begin + if (reset) begin + mag <= 0; + mag_stb <=0; + abs_i <= 0; + abs_q <= 0; + max <= 0; + min <= 0; + stage1 <= 0; + stage2 <= 0; + end else if (enable) begin + stage1 <= input_strobe; + abs_i <= i[DATA_WIDTH-1]? (~i+1): i; + abs_q <= q[DATA_WIDTH-1]? (~q+1): q; + + stage2 <= stage1; + max <= abs_i > abs_q? abs_i: abs_q; + min <= abs_i > abs_q? abs_q: abs_i; + + mag <= max + (min>>2); + mag_stb <= stage2; + end else begin + mag_stb <= 0; + end +end + +endmodule diff --git a/verilog/complex_to_mag_sq.v b/verilog/complex_to_mag_sq.v new file mode 100644 index 0000000..af6d2b2 --- /dev/null +++ b/verilog/complex_to_mag_sq.v @@ -0,0 +1,47 @@ +module complex_to_mag_sq ( + input clock, + input enable, + input reset, + + input signed [15:0] i, + input signed [15:0] q, + input input_strobe, + + output [31:0] mag_sq, + output mag_sq_strobe +); + +reg valid_in; +reg [15:0] input_i; +reg [15:0] input_q; +reg [15:0] input_q_neg; + +complex_mult mult_inst ( + .clock(clock), + .reset(reset), + .enable(enable), + + .a_i(input_i), + .a_q(input_q), + .b_i(input_i), + .b_q(input_q_neg), + .input_strobe(valid_in), + + .p_i(mag_sq), + .output_strobe(mag_sq_strobe) +); + +always @(posedge clock) begin + if (reset) begin + input_i <= 0; + input_q <= 0; + input_q_neg <= 0; + valid_in <= 0; + end else if (enable) begin + valid_in <= input_strobe; + input_i <= i; + input_q <= q; + input_q_neg <= ~q+1; + end +end +endmodule diff --git a/verilog/coregen/atan_lut.v b/verilog/coregen/atan_lut.v new file mode 100644 index 0000000..94ee9fa --- /dev/null +++ b/verilog/coregen/atan_lut.v @@ -0,0 +1,137 @@ +/******************************************************************************* +* This file is owned and controlled by Xilinx and must be used * +* solely for design, simulation, implementation and creation of * +* design files limited to Xilinx devices or technologies. Use * +* with non-Xilinx devices or technologies is expressly prohibited * +* and immediately terminates your license. * +* * +* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" * +* SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR * +* XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION * +* AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION * +* OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS * +* IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, * +* AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE * +* FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY * +* WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE * +* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR * +* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF * +* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS * +* FOR A PARTICULAR PURPOSE. * +* * +* Xilinx products are not intended for use in life support * +* appliances, devices, or systems. Use in such applications are * +* expressly prohibited. * +* * +* (c) Copyright 1995-2009 Xilinx, Inc. * +* All rights reserved. * +*******************************************************************************/ +// The synthesis directives "translate_off/translate_on" specified below are +// supported by Xilinx, Mentor Graphics and Synplicity synthesis +// tools. Ensure they are correct for your synthesis tool(s). + +// You must compile the wrapper file atan_lut.v when simulating +// the core, atan_lut. When compiling the wrapper file, be sure to +// reference the XilinxCoreLib Verilog simulation library. For detailed +// instructions, please refer to the "CORE Generator Help". + +`timescale 1ns/1ps + +module atan_lut( + clka, + addra, + douta); + + +input clka; +input [7 : 0] addra; +output [8 : 0] douta; + +// synthesis translate_off + + BLK_MEM_GEN_V4_2 #( + .C_ADDRA_WIDTH(8), + .C_ADDRB_WIDTH(8), + .C_ALGORITHM(1), + .C_BYTE_SIZE(9), + .C_COMMON_CLK(0), + .C_DEFAULT_DATA("0"), + .C_DISABLE_WARN_BHV_COLL(0), + .C_DISABLE_WARN_BHV_RANGE(0), + .C_FAMILY("spartan3"), + .C_HAS_ENA(0), + .C_HAS_ENB(0), + .C_HAS_INJECTERR(0), + .C_HAS_MEM_OUTPUT_REGS_A(0), + .C_HAS_MEM_OUTPUT_REGS_B(0), + .C_HAS_MUX_OUTPUT_REGS_A(0), + .C_HAS_MUX_OUTPUT_REGS_B(0), + .C_HAS_REGCEA(0), + .C_HAS_REGCEB(0), + .C_HAS_RSTA(0), + .C_HAS_RSTB(0), + .C_HAS_SOFTECC_INPUT_REGS_A(0), + .C_HAS_SOFTECC_OUTPUT_REGS_B(0), + .C_INITA_VAL("0"), + .C_INITB_VAL("0"), + .C_INIT_FILE_NAME("atan_lut.mif"), + .C_LOAD_INIT_FILE(1), + .C_MEM_TYPE(3), + .C_MUX_PIPELINE_STAGES(0), + .C_PRIM_TYPE(1), + .C_READ_DEPTH_A(256), + .C_READ_DEPTH_B(256), + .C_READ_WIDTH_A(9), + .C_READ_WIDTH_B(9), + .C_RSTRAM_A(0), + .C_RSTRAM_B(0), + .C_RST_PRIORITY_A("CE"), + .C_RST_PRIORITY_B("CE"), + .C_RST_TYPE("SYNC"), + .C_SIM_COLLISION_CHECK("ALL"), + .C_USE_BYTE_WEA(0), + .C_USE_BYTE_WEB(0), + .C_USE_DEFAULT_DATA(0), + .C_USE_ECC(0), + .C_USE_SOFTECC(0), + .C_WEA_WIDTH(1), + .C_WEB_WIDTH(1), + .C_WRITE_DEPTH_A(256), + .C_WRITE_DEPTH_B(256), + .C_WRITE_MODE_A("WRITE_FIRST"), + .C_WRITE_MODE_B("WRITE_FIRST"), + .C_WRITE_WIDTH_A(9), + .C_WRITE_WIDTH_B(9), + .C_XDEVICEFAMILY("spartan3adsp")) + inst ( + .CLKA(clka), + .ADDRA(addra), + .DOUTA(douta), + .RSTA(), + .ENA(), + .REGCEA(), + .WEA(), + .DINA(), + .CLKB(), + .RSTB(), + .ENB(), + .REGCEB(), + .WEB(), + .ADDRB(), + .DINB(), + .DOUTB(), + .INJECTSBITERR(), + .INJECTDBITERR(), + .SBITERR(), + .DBITERR(), + .RDADDRECC()); + + +// synthesis translate_on + +// XST black box declaration +// box_type "black_box" +// synthesis attribute box_type of atan_lut is "black_box" + +endmodule + diff --git a/verilog/coregen/complex_multiplier.v b/verilog/coregen/complex_multiplier.v new file mode 100644 index 0000000..7a5653f --- /dev/null +++ b/verilog/coregen/complex_multiplier.v @@ -0,0 +1,867 @@ +//////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved. +//////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor: Xilinx +// \ \ \/ Version: M.63c +// \ \ Application: netgen +// / / Filename: complex_multiplier.v +// /___/ /\ Timestamp: Tue Aug 23 11:23:16 2016 +// \ \ / \ +// \___\/\___\ +// +// Command : -intstyle ise -w -sim -ofmt verilog ./tmp/_cg/complex_multiplier.ngc ./tmp/_cg/complex_multiplier.v +// Device : 3sd3400afg676-5 +// Input file : ./tmp/_cg/complex_multiplier.ngc +// Output file : ./tmp/_cg/complex_multiplier.v +// # of Modules : 1 +// Design Name : complex_multiplier +// Xilinx : /opt/Xilinx/12.2/ISE_DS/ISE/ +// +// Purpose: +// This verilog netlist is a verification model and uses simulation +// primitives which may not represent the true implementation of the +// device, however the netlist is functionally correct and should not +// be modified. This file cannot be synthesized and should only be used +// with supported simulation tools. +// +// Reference: +// Command Line Tools User Guide, Chapter 23 and Synthesis and Simulation Design Guide, Chapter 6 +// +//////////////////////////////////////////////////////////////////////////////// + +`timescale 1 ns/1 ps + +module complex_multiplier ( + clk, ai, bi, ar, br, pi, pr +)/* synthesis syn_black_box syn_noprune=1 */; + input clk; + input [15 : 0] ai; + input [15 : 0] bi; + input [15 : 0] ar; + input [15 : 0] br; + output [31 : 0] pi; + output [31 : 0] pr; + + // synthesis translate_off + + wire \blk00000003/sig000000a4 ; + wire \blk00000003/sig000000a3 ; + wire \blk00000003/sig000000a2 ; + wire \blk00000003/sig000000a1 ; + wire \blk00000003/sig000000a0 ; + wire \blk00000003/sig0000009f ; + wire \blk00000003/sig0000009e ; + wire \blk00000003/sig0000009d ; + wire \blk00000003/sig0000009c ; + wire \blk00000003/sig0000009b ; + wire \blk00000003/sig0000009a ; + wire \blk00000003/sig00000099 ; + wire \blk00000003/sig00000098 ; + wire \blk00000003/sig00000097 ; + wire \blk00000003/sig00000096 ; + wire \blk00000003/sig00000095 ; + wire \blk00000003/sig00000094 ; + wire \blk00000003/sig00000093 ; + wire \blk00000003/sig00000092 ; + wire \blk00000003/sig00000091 ; + wire \blk00000003/sig00000090 ; + wire \blk00000003/sig0000008f ; + wire \blk00000003/sig0000008e ; + wire \blk00000003/sig0000008d ; + wire \blk00000003/sig0000008c ; + wire \blk00000003/sig0000008b ; + wire \blk00000003/sig0000008a ; + wire \blk00000003/sig00000089 ; + wire \blk00000003/sig00000088 ; + wire \blk00000003/sig00000087 ; + wire \blk00000003/sig00000086 ; + wire \blk00000003/sig00000085 ; + wire \blk00000003/sig00000084 ; + wire \blk00000003/sig00000083 ; + wire \blk00000003/sig00000082 ; + wire NLW_blk00000001_P_UNCONNECTED; + wire NLW_blk00000002_G_UNCONNECTED; + wire \NLW_blk00000003/blk00000008_CARRYOUT_UNCONNECTED ; + wire \NLW_blk00000003/blk00000008_P<47>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000008_P<46>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000008_P<45>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000008_P<44>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000008_P<43>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000008_P<42>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000008_P<41>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000008_P<40>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000008_P<39>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000008_P<38>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000008_P<37>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000008_P<36>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000008_P<35>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000008_P<34>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000008_P<33>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000008_P<32>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000008_PCOUT<47>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000008_PCOUT<46>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000008_PCOUT<45>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000008_PCOUT<44>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000008_PCOUT<43>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000008_PCOUT<42>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000008_PCOUT<41>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000008_PCOUT<40>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000008_PCOUT<39>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000008_PCOUT<38>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000008_PCOUT<37>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000008_PCOUT<36>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000008_PCOUT<35>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000008_PCOUT<34>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000008_PCOUT<33>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000008_PCOUT<32>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000008_PCOUT<31>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000008_PCOUT<30>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000008_PCOUT<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000008_PCOUT<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000008_PCOUT<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000008_PCOUT<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000008_PCOUT<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000008_PCOUT<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000008_PCOUT<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000008_PCOUT<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000008_PCOUT<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000008_PCOUT<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000008_PCOUT<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000008_PCOUT<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000008_PCOUT<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000008_PCOUT<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000008_PCOUT<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000008_PCOUT<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000008_PCOUT<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000008_PCOUT<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000008_PCOUT<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000008_PCOUT<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000008_PCOUT<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000008_PCOUT<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000008_PCOUT<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000008_PCOUT<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000008_PCOUT<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000008_PCOUT<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000008_PCOUT<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000008_PCOUT<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000008_PCOUT<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000008_PCOUT<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000008_BCOUT<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000008_BCOUT<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000008_BCOUT<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000008_BCOUT<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000008_BCOUT<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000008_BCOUT<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000008_BCOUT<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000008_BCOUT<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000008_BCOUT<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000008_BCOUT<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000008_BCOUT<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000008_BCOUT<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000008_BCOUT<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000008_BCOUT<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000008_BCOUT<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000008_BCOUT<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000008_BCOUT<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000008_BCOUT<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_CARRYOUT_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_P<47>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_P<46>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_P<45>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_P<44>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_P<43>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_P<42>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_P<41>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_P<40>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_P<39>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_P<38>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_P<37>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_P<36>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_P<35>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_P<34>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_P<32>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_PCOUT<47>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_PCOUT<46>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_PCOUT<45>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_PCOUT<44>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_PCOUT<43>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_PCOUT<42>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_PCOUT<41>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_PCOUT<40>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_PCOUT<39>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_PCOUT<38>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_PCOUT<37>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_PCOUT<36>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_PCOUT<35>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_PCOUT<34>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_PCOUT<33>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_PCOUT<32>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_PCOUT<31>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_PCOUT<30>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_PCOUT<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_PCOUT<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_PCOUT<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_PCOUT<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_PCOUT<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_PCOUT<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_PCOUT<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_PCOUT<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_PCOUT<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_PCOUT<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_PCOUT<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_PCOUT<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_PCOUT<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_PCOUT<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_PCOUT<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_PCOUT<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_PCOUT<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_PCOUT<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_PCOUT<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_PCOUT<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_PCOUT<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_PCOUT<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_PCOUT<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_PCOUT<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_PCOUT<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_PCOUT<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_PCOUT<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_PCOUT<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_PCOUT<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_PCOUT<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_BCOUT<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_BCOUT<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_BCOUT<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_BCOUT<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_BCOUT<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_BCOUT<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_BCOUT<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_BCOUT<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_BCOUT<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_BCOUT<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_BCOUT<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_BCOUT<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_BCOUT<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_BCOUT<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_BCOUT<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_BCOUT<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_BCOUT<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000007_BCOUT<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_CARRYOUT_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_P<47>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_P<46>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_P<45>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_P<44>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_P<43>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_P<42>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_P<41>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_P<40>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_P<39>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_P<38>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_P<37>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_P<36>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_P<35>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_P<34>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_P<33>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_P<32>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_PCOUT<47>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_PCOUT<46>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_PCOUT<45>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_PCOUT<44>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_PCOUT<43>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_PCOUT<42>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_PCOUT<41>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_PCOUT<40>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_PCOUT<39>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_PCOUT<38>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_PCOUT<37>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_PCOUT<36>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_PCOUT<35>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_PCOUT<34>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_PCOUT<33>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_PCOUT<32>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_PCOUT<31>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_PCOUT<30>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_PCOUT<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_PCOUT<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_PCOUT<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_PCOUT<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_PCOUT<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_PCOUT<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_PCOUT<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_PCOUT<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_PCOUT<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_PCOUT<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_PCOUT<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_PCOUT<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_PCOUT<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_PCOUT<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_PCOUT<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_PCOUT<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_PCOUT<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_PCOUT<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_PCOUT<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_PCOUT<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_PCOUT<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_PCOUT<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_PCOUT<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_PCOUT<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_PCOUT<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_PCOUT<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_PCOUT<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_PCOUT<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_PCOUT<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_PCOUT<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_BCOUT<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_BCOUT<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_BCOUT<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_BCOUT<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_BCOUT<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_BCOUT<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_BCOUT<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_BCOUT<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_BCOUT<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_BCOUT<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_BCOUT<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_BCOUT<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_BCOUT<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_BCOUT<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_BCOUT<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_BCOUT<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_BCOUT<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000006_BCOUT<0>_UNCONNECTED ; + wire [15 : 0] ar_0; + wire [15 : 0] ai_1; + wire [15 : 0] br_2; + wire [15 : 0] bi_3; + wire [31 : 0] pr_4; + wire [31 : 0] pi_5; + assign + ai_1[15] = ai[15], + ai_1[14] = ai[14], + ai_1[13] = ai[13], + ai_1[12] = ai[12], + ai_1[11] = ai[11], + ai_1[10] = ai[10], + ai_1[9] = ai[9], + ai_1[8] = ai[8], + ai_1[7] = ai[7], + ai_1[6] = ai[6], + ai_1[5] = ai[5], + ai_1[4] = ai[4], + ai_1[3] = ai[3], + ai_1[2] = ai[2], + ai_1[1] = ai[1], + ai_1[0] = ai[0], + bi_3[15] = bi[15], + bi_3[14] = bi[14], + bi_3[13] = bi[13], + bi_3[12] = bi[12], + bi_3[11] = bi[11], + bi_3[10] = bi[10], + bi_3[9] = bi[9], + bi_3[8] = bi[8], + bi_3[7] = bi[7], + bi_3[6] = bi[6], + bi_3[5] = bi[5], + bi_3[4] = bi[4], + bi_3[3] = bi[3], + bi_3[2] = bi[2], + bi_3[1] = bi[1], + bi_3[0] = bi[0], + ar_0[15] = ar[15], + ar_0[14] = ar[14], + ar_0[13] = ar[13], + ar_0[12] = ar[12], + ar_0[11] = ar[11], + ar_0[10] = ar[10], + ar_0[9] = ar[9], + ar_0[8] = ar[8], + ar_0[7] = ar[7], + ar_0[6] = ar[6], + ar_0[5] = ar[5], + ar_0[4] = ar[4], + ar_0[3] = ar[3], + ar_0[2] = ar[2], + ar_0[1] = ar[1], + ar_0[0] = ar[0], + br_2[15] = br[15], + br_2[14] = br[14], + br_2[13] = br[13], + br_2[12] = br[12], + br_2[11] = br[11], + br_2[10] = br[10], + br_2[9] = br[9], + br_2[8] = br[8], + br_2[7] = br[7], + br_2[6] = br[6], + br_2[5] = br[5], + br_2[4] = br[4], + br_2[3] = br[3], + br_2[2] = br[2], + br_2[1] = br[1], + br_2[0] = br[0], + pi[31] = pi_5[31], + pi[30] = pi_5[30], + pi[29] = pi_5[29], + pi[28] = pi_5[28], + pi[27] = pi_5[27], + pi[26] = pi_5[26], + pi[25] = pi_5[25], + pi[24] = pi_5[24], + pi[23] = pi_5[23], + pi[22] = pi_5[22], + pi[21] = pi_5[21], + pi[20] = pi_5[20], + pi[19] = pi_5[19], + pi[18] = pi_5[18], + pi[17] = pi_5[17], + pi[16] = pi_5[16], + pi[15] = pi_5[15], + pi[14] = pi_5[14], + pi[13] = pi_5[13], + pi[12] = pi_5[12], + pi[11] = pi_5[11], + pi[10] = pi_5[10], + pi[9] = pi_5[9], + pi[8] = pi_5[8], + pi[7] = pi_5[7], + pi[6] = pi_5[6], + pi[5] = pi_5[5], + pi[4] = pi_5[4], + pi[3] = pi_5[3], + pi[2] = pi_5[2], + pi[1] = pi_5[1], + pi[0] = pi_5[0], + pr[31] = pr_4[31], + pr[30] = pr_4[30], + pr[29] = pr_4[29], + pr[28] = pr_4[28], + pr[27] = pr_4[27], + pr[26] = pr_4[26], + pr[25] = pr_4[25], + pr[24] = pr_4[24], + pr[23] = pr_4[23], + pr[22] = pr_4[22], + pr[21] = pr_4[21], + pr[20] = pr_4[20], + pr[19] = pr_4[19], + pr[18] = pr_4[18], + pr[17] = pr_4[17], + pr[16] = pr_4[16], + pr[15] = pr_4[15], + pr[14] = pr_4[14], + pr[13] = pr_4[13], + pr[12] = pr_4[12], + pr[11] = pr_4[11], + pr[10] = pr_4[10], + pr[9] = pr_4[9], + pr[8] = pr_4[8], + pr[7] = pr_4[7], + pr[6] = pr_4[6], + pr[5] = pr_4[5], + pr[4] = pr_4[4], + pr[3] = pr_4[3], + pr[2] = pr_4[2], + pr[1] = pr_4[1], + pr[0] = pr_4[0]; + VCC blk00000001 ( + .P(NLW_blk00000001_P_UNCONNECTED) + ); + GND blk00000002 ( + .G(NLW_blk00000002_G_UNCONNECTED) + ); + DSP48A #( + .A0REG ( 0 ), + .A1REG ( 1 ), + .B0REG ( 0 ), + .B1REG ( 1 ), + .CARRYINREG ( 0 ), + .CARRYINSEL ( "OPMODE5" ), + .CREG ( 0 ), + .DREG ( 0 ), + .MREG ( 1 ), + .OPMODEREG ( 0 ), + .PREG ( 1 ), + .RSTTYPE ( "SYNC" )) + \blk00000003/blk00000008 ( + .CARRYIN(\blk00000003/sig00000082 ), + .CARRYOUT(\NLW_blk00000003/blk00000008_CARRYOUT_UNCONNECTED ), + .CLK(clk), + .RSTA(\blk00000003/sig00000082 ), + .RSTB(\blk00000003/sig00000082 ), + .RSTM(\blk00000003/sig00000082 ), + .RSTP(\blk00000003/sig00000082 ), + .RSTC(\blk00000003/sig00000082 ), + .RSTD(\blk00000003/sig00000082 ), + .RSTCARRYIN(\blk00000003/sig00000082 ), + .RSTOPMODE(\blk00000003/sig00000082 ), + .CEA(\blk00000003/sig00000083 ), + .CEB(\blk00000003/sig00000083 ), + .CEM(\blk00000003/sig00000083 ), + .CEP(\blk00000003/sig00000083 ), + .CEC(\blk00000003/sig00000082 ), + .CED(\blk00000003/sig00000082 ), + .CECARRYIN(\blk00000003/sig00000082 ), + .CEOPMODE(\blk00000003/sig00000082 ), + .A({ai_1[15], ai_1[15], ai_1[15], ai_1[14], ai_1[13], ai_1[12], ai_1[11], ai_1[10], ai_1[9], ai_1[8], ai_1[7], ai_1[6], ai_1[5], ai_1[4], ai_1[3] +, ai_1[2], ai_1[1], ai_1[0]}), + .B({br_2[15], br_2[15], br_2[15], br_2[14], br_2[13], br_2[12], br_2[11], br_2[10], br_2[9], br_2[8], br_2[7], br_2[6], br_2[5], br_2[4], br_2[3] +, br_2[2], br_2[1], br_2[0]}), + .D({bi_3[15], bi_3[15], bi_3[15], bi_3[14], bi_3[13], bi_3[12], bi_3[11], bi_3[10], bi_3[9], bi_3[8], bi_3[7], bi_3[6], bi_3[5], bi_3[4], bi_3[3] +, bi_3[2], bi_3[1], bi_3[0]}), + .C({\blk00000003/sig00000084 , \blk00000003/sig00000084 , \blk00000003/sig00000084 , \blk00000003/sig00000084 , \blk00000003/sig00000084 , +\blk00000003/sig00000084 , \blk00000003/sig00000084 , \blk00000003/sig00000084 , \blk00000003/sig00000084 , \blk00000003/sig00000084 , +\blk00000003/sig00000084 , \blk00000003/sig00000084 , \blk00000003/sig00000084 , \blk00000003/sig00000084 , \blk00000003/sig00000084 , +\blk00000003/sig00000084 , \blk00000003/sig00000085 , \blk00000003/sig00000086 , \blk00000003/sig00000087 , \blk00000003/sig00000088 , +\blk00000003/sig00000089 , \blk00000003/sig0000008a , \blk00000003/sig0000008b , \blk00000003/sig0000008c , \blk00000003/sig0000008d , +\blk00000003/sig0000008e , \blk00000003/sig0000008f , \blk00000003/sig00000090 , \blk00000003/sig00000091 , \blk00000003/sig00000092 , +\blk00000003/sig00000093 , \blk00000003/sig00000094 , \blk00000003/sig00000095 , \blk00000003/sig00000096 , \blk00000003/sig00000097 , +\blk00000003/sig00000098 , \blk00000003/sig00000099 , \blk00000003/sig0000009a , \blk00000003/sig0000009b , \blk00000003/sig0000009c , +\blk00000003/sig0000009d , \blk00000003/sig0000009e , \blk00000003/sig0000009f , \blk00000003/sig000000a0 , \blk00000003/sig000000a1 , +\blk00000003/sig000000a2 , \blk00000003/sig000000a3 , \blk00000003/sig000000a4 }), + .P({\NLW_blk00000003/blk00000008_P<47>_UNCONNECTED , \NLW_blk00000003/blk00000008_P<46>_UNCONNECTED , +\NLW_blk00000003/blk00000008_P<45>_UNCONNECTED , \NLW_blk00000003/blk00000008_P<44>_UNCONNECTED , \NLW_blk00000003/blk00000008_P<43>_UNCONNECTED , +\NLW_blk00000003/blk00000008_P<42>_UNCONNECTED , \NLW_blk00000003/blk00000008_P<41>_UNCONNECTED , \NLW_blk00000003/blk00000008_P<40>_UNCONNECTED , +\NLW_blk00000003/blk00000008_P<39>_UNCONNECTED , \NLW_blk00000003/blk00000008_P<38>_UNCONNECTED , \NLW_blk00000003/blk00000008_P<37>_UNCONNECTED , +\NLW_blk00000003/blk00000008_P<36>_UNCONNECTED , \NLW_blk00000003/blk00000008_P<35>_UNCONNECTED , \NLW_blk00000003/blk00000008_P<34>_UNCONNECTED , +\NLW_blk00000003/blk00000008_P<33>_UNCONNECTED , \NLW_blk00000003/blk00000008_P<32>_UNCONNECTED , pr_4[31], pr_4[30], pr_4[29], pr_4[28], pr_4[27], +pr_4[26], pr_4[25], pr_4[24], pr_4[23], pr_4[22], pr_4[21], pr_4[20], pr_4[19], pr_4[18], pr_4[17], pr_4[16], pr_4[15], pr_4[14], pr_4[13], pr_4[12], +pr_4[11], pr_4[10], pr_4[9], pr_4[8], pr_4[7], pr_4[6], pr_4[5], pr_4[4], pr_4[3], pr_4[2], pr_4[1], pr_4[0]}), + .OPMODE({\blk00000003/sig00000083 , \blk00000003/sig00000082 , \blk00000003/sig00000082 , \blk00000003/sig00000083 , \blk00000003/sig00000083 , +\blk00000003/sig00000083 , \blk00000003/sig00000082 , \blk00000003/sig00000083 }), + .PCIN({\blk00000003/sig00000082 , \blk00000003/sig00000082 , \blk00000003/sig00000082 , \blk00000003/sig00000082 , \blk00000003/sig00000082 , +\blk00000003/sig00000082 , \blk00000003/sig00000082 , \blk00000003/sig00000082 , \blk00000003/sig00000082 , \blk00000003/sig00000082 , +\blk00000003/sig00000082 , \blk00000003/sig00000082 , \blk00000003/sig00000082 , \blk00000003/sig00000082 , \blk00000003/sig00000082 , +\blk00000003/sig00000082 , \blk00000003/sig00000082 , \blk00000003/sig00000082 , \blk00000003/sig00000082 , \blk00000003/sig00000082 , +\blk00000003/sig00000082 , \blk00000003/sig00000082 , \blk00000003/sig00000082 , \blk00000003/sig00000082 , \blk00000003/sig00000082 , +\blk00000003/sig00000082 , \blk00000003/sig00000082 , \blk00000003/sig00000082 , \blk00000003/sig00000082 , \blk00000003/sig00000082 , +\blk00000003/sig00000082 , \blk00000003/sig00000082 , \blk00000003/sig00000082 , \blk00000003/sig00000082 , \blk00000003/sig00000082 , +\blk00000003/sig00000082 , \blk00000003/sig00000082 , \blk00000003/sig00000082 , \blk00000003/sig00000082 , \blk00000003/sig00000082 , +\blk00000003/sig00000082 , \blk00000003/sig00000082 , \blk00000003/sig00000082 , \blk00000003/sig00000082 , \blk00000003/sig00000082 , +\blk00000003/sig00000082 , \blk00000003/sig00000082 , \blk00000003/sig00000082 }), + .PCOUT({\NLW_blk00000003/blk00000008_PCOUT<47>_UNCONNECTED , \NLW_blk00000003/blk00000008_PCOUT<46>_UNCONNECTED , +\NLW_blk00000003/blk00000008_PCOUT<45>_UNCONNECTED , \NLW_blk00000003/blk00000008_PCOUT<44>_UNCONNECTED , +\NLW_blk00000003/blk00000008_PCOUT<43>_UNCONNECTED , \NLW_blk00000003/blk00000008_PCOUT<42>_UNCONNECTED , +\NLW_blk00000003/blk00000008_PCOUT<41>_UNCONNECTED , \NLW_blk00000003/blk00000008_PCOUT<40>_UNCONNECTED , +\NLW_blk00000003/blk00000008_PCOUT<39>_UNCONNECTED , \NLW_blk00000003/blk00000008_PCOUT<38>_UNCONNECTED , +\NLW_blk00000003/blk00000008_PCOUT<37>_UNCONNECTED , \NLW_blk00000003/blk00000008_PCOUT<36>_UNCONNECTED , +\NLW_blk00000003/blk00000008_PCOUT<35>_UNCONNECTED , \NLW_blk00000003/blk00000008_PCOUT<34>_UNCONNECTED , +\NLW_blk00000003/blk00000008_PCOUT<33>_UNCONNECTED , \NLW_blk00000003/blk00000008_PCOUT<32>_UNCONNECTED , +\NLW_blk00000003/blk00000008_PCOUT<31>_UNCONNECTED , \NLW_blk00000003/blk00000008_PCOUT<30>_UNCONNECTED , +\NLW_blk00000003/blk00000008_PCOUT<29>_UNCONNECTED , \NLW_blk00000003/blk00000008_PCOUT<28>_UNCONNECTED , +\NLW_blk00000003/blk00000008_PCOUT<27>_UNCONNECTED , \NLW_blk00000003/blk00000008_PCOUT<26>_UNCONNECTED , +\NLW_blk00000003/blk00000008_PCOUT<25>_UNCONNECTED , \NLW_blk00000003/blk00000008_PCOUT<24>_UNCONNECTED , +\NLW_blk00000003/blk00000008_PCOUT<23>_UNCONNECTED , \NLW_blk00000003/blk00000008_PCOUT<22>_UNCONNECTED , +\NLW_blk00000003/blk00000008_PCOUT<21>_UNCONNECTED , \NLW_blk00000003/blk00000008_PCOUT<20>_UNCONNECTED , +\NLW_blk00000003/blk00000008_PCOUT<19>_UNCONNECTED , \NLW_blk00000003/blk00000008_PCOUT<18>_UNCONNECTED , +\NLW_blk00000003/blk00000008_PCOUT<17>_UNCONNECTED , \NLW_blk00000003/blk00000008_PCOUT<16>_UNCONNECTED , +\NLW_blk00000003/blk00000008_PCOUT<15>_UNCONNECTED , \NLW_blk00000003/blk00000008_PCOUT<14>_UNCONNECTED , +\NLW_blk00000003/blk00000008_PCOUT<13>_UNCONNECTED , \NLW_blk00000003/blk00000008_PCOUT<12>_UNCONNECTED , +\NLW_blk00000003/blk00000008_PCOUT<11>_UNCONNECTED , \NLW_blk00000003/blk00000008_PCOUT<10>_UNCONNECTED , +\NLW_blk00000003/blk00000008_PCOUT<9>_UNCONNECTED , \NLW_blk00000003/blk00000008_PCOUT<8>_UNCONNECTED , +\NLW_blk00000003/blk00000008_PCOUT<7>_UNCONNECTED , \NLW_blk00000003/blk00000008_PCOUT<6>_UNCONNECTED , +\NLW_blk00000003/blk00000008_PCOUT<5>_UNCONNECTED , \NLW_blk00000003/blk00000008_PCOUT<4>_UNCONNECTED , +\NLW_blk00000003/blk00000008_PCOUT<3>_UNCONNECTED , \NLW_blk00000003/blk00000008_PCOUT<2>_UNCONNECTED , +\NLW_blk00000003/blk00000008_PCOUT<1>_UNCONNECTED , \NLW_blk00000003/blk00000008_PCOUT<0>_UNCONNECTED }), + .BCOUT({\NLW_blk00000003/blk00000008_BCOUT<17>_UNCONNECTED , \NLW_blk00000003/blk00000008_BCOUT<16>_UNCONNECTED , +\NLW_blk00000003/blk00000008_BCOUT<15>_UNCONNECTED , \NLW_blk00000003/blk00000008_BCOUT<14>_UNCONNECTED , +\NLW_blk00000003/blk00000008_BCOUT<13>_UNCONNECTED , \NLW_blk00000003/blk00000008_BCOUT<12>_UNCONNECTED , +\NLW_blk00000003/blk00000008_BCOUT<11>_UNCONNECTED , \NLW_blk00000003/blk00000008_BCOUT<10>_UNCONNECTED , +\NLW_blk00000003/blk00000008_BCOUT<9>_UNCONNECTED , \NLW_blk00000003/blk00000008_BCOUT<8>_UNCONNECTED , +\NLW_blk00000003/blk00000008_BCOUT<7>_UNCONNECTED , \NLW_blk00000003/blk00000008_BCOUT<6>_UNCONNECTED , +\NLW_blk00000003/blk00000008_BCOUT<5>_UNCONNECTED , \NLW_blk00000003/blk00000008_BCOUT<4>_UNCONNECTED , +\NLW_blk00000003/blk00000008_BCOUT<3>_UNCONNECTED , \NLW_blk00000003/blk00000008_BCOUT<2>_UNCONNECTED , +\NLW_blk00000003/blk00000008_BCOUT<1>_UNCONNECTED , \NLW_blk00000003/blk00000008_BCOUT<0>_UNCONNECTED }) + ); + DSP48A #( + .A0REG ( 0 ), + .A1REG ( 1 ), + .B0REG ( 0 ), + .B1REG ( 1 ), + .CARRYINREG ( 0 ), + .CARRYINSEL ( "OPMODE5" ), + .CREG ( 0 ), + .DREG ( 0 ), + .MREG ( 0 ), + .OPMODEREG ( 0 ), + .PREG ( 1 ), + .RSTTYPE ( "SYNC" )) + \blk00000003/blk00000007 ( + .CARRYIN(\blk00000003/sig00000082 ), + .CARRYOUT(\NLW_blk00000003/blk00000007_CARRYOUT_UNCONNECTED ), + .CLK(clk), + .RSTA(\blk00000003/sig00000082 ), + .RSTB(\blk00000003/sig00000082 ), + .RSTM(\blk00000003/sig00000082 ), + .RSTP(\blk00000003/sig00000082 ), + .RSTC(\blk00000003/sig00000082 ), + .RSTD(\blk00000003/sig00000082 ), + .RSTCARRYIN(\blk00000003/sig00000082 ), + .RSTOPMODE(\blk00000003/sig00000082 ), + .CEA(\blk00000003/sig00000083 ), + .CEB(\blk00000003/sig00000083 ), + .CEM(\blk00000003/sig00000082 ), + .CEP(\blk00000003/sig00000083 ), + .CEC(\blk00000003/sig00000082 ), + .CED(\blk00000003/sig00000082 ), + .CECARRYIN(\blk00000003/sig00000082 ), + .CEOPMODE(\blk00000003/sig00000082 ), + .A({br_2[15], br_2[15], br_2[15], br_2[14], br_2[13], br_2[12], br_2[11], br_2[10], br_2[9], br_2[8], br_2[7], br_2[6], br_2[5], br_2[4], br_2[3] +, br_2[2], br_2[1], br_2[0]}), + .B({ar_0[15], ar_0[15], ar_0[15], ar_0[14], ar_0[13], ar_0[12], ar_0[11], ar_0[10], ar_0[9], ar_0[8], ar_0[7], ar_0[6], ar_0[5], ar_0[4], ar_0[3] +, ar_0[2], ar_0[1], ar_0[0]}), + .D({ai_1[15], ai_1[15], ai_1[15], ai_1[14], ai_1[13], ai_1[12], ai_1[11], ai_1[10], ai_1[9], ai_1[8], ai_1[7], ai_1[6], ai_1[5], ai_1[4], ai_1[3] +, ai_1[2], ai_1[1], ai_1[0]}), + .C({\blk00000003/sig00000082 , \blk00000003/sig00000082 , \blk00000003/sig00000082 , \blk00000003/sig00000082 , \blk00000003/sig00000082 , +\blk00000003/sig00000082 , \blk00000003/sig00000082 , \blk00000003/sig00000082 , \blk00000003/sig00000082 , \blk00000003/sig00000082 , +\blk00000003/sig00000082 , \blk00000003/sig00000082 , \blk00000003/sig00000082 , \blk00000003/sig00000082 , \blk00000003/sig00000082 , +\blk00000003/sig00000082 , \blk00000003/sig00000082 , \blk00000003/sig00000082 , \blk00000003/sig00000082 , \blk00000003/sig00000082 , +\blk00000003/sig00000082 , \blk00000003/sig00000082 , \blk00000003/sig00000082 , \blk00000003/sig00000082 , \blk00000003/sig00000082 , +\blk00000003/sig00000082 , \blk00000003/sig00000082 , \blk00000003/sig00000082 , \blk00000003/sig00000082 , \blk00000003/sig00000082 , +\blk00000003/sig00000082 , \blk00000003/sig00000082 , \blk00000003/sig00000082 , \blk00000003/sig00000082 , \blk00000003/sig00000082 , +\blk00000003/sig00000082 , \blk00000003/sig00000082 , \blk00000003/sig00000082 , \blk00000003/sig00000082 , \blk00000003/sig00000082 , +\blk00000003/sig00000082 , \blk00000003/sig00000082 , \blk00000003/sig00000082 , \blk00000003/sig00000082 , \blk00000003/sig00000082 , +\blk00000003/sig00000082 , \blk00000003/sig00000082 , \blk00000003/sig00000082 }), + .P({\NLW_blk00000003/blk00000007_P<47>_UNCONNECTED , \NLW_blk00000003/blk00000007_P<46>_UNCONNECTED , +\NLW_blk00000003/blk00000007_P<45>_UNCONNECTED , \NLW_blk00000003/blk00000007_P<44>_UNCONNECTED , \NLW_blk00000003/blk00000007_P<43>_UNCONNECTED , +\NLW_blk00000003/blk00000007_P<42>_UNCONNECTED , \NLW_blk00000003/blk00000007_P<41>_UNCONNECTED , \NLW_blk00000003/blk00000007_P<40>_UNCONNECTED , +\NLW_blk00000003/blk00000007_P<39>_UNCONNECTED , \NLW_blk00000003/blk00000007_P<38>_UNCONNECTED , \NLW_blk00000003/blk00000007_P<37>_UNCONNECTED , +\NLW_blk00000003/blk00000007_P<36>_UNCONNECTED , \NLW_blk00000003/blk00000007_P<35>_UNCONNECTED , \NLW_blk00000003/blk00000007_P<34>_UNCONNECTED , +\blk00000003/sig00000084 , \NLW_blk00000003/blk00000007_P<32>_UNCONNECTED , \blk00000003/sig00000085 , \blk00000003/sig00000086 , +\blk00000003/sig00000087 , \blk00000003/sig00000088 , \blk00000003/sig00000089 , \blk00000003/sig0000008a , \blk00000003/sig0000008b , +\blk00000003/sig0000008c , \blk00000003/sig0000008d , \blk00000003/sig0000008e , \blk00000003/sig0000008f , \blk00000003/sig00000090 , +\blk00000003/sig00000091 , \blk00000003/sig00000092 , \blk00000003/sig00000093 , \blk00000003/sig00000094 , \blk00000003/sig00000095 , +\blk00000003/sig00000096 , \blk00000003/sig00000097 , \blk00000003/sig00000098 , \blk00000003/sig00000099 , \blk00000003/sig0000009a , +\blk00000003/sig0000009b , \blk00000003/sig0000009c , \blk00000003/sig0000009d , \blk00000003/sig0000009e , \blk00000003/sig0000009f , +\blk00000003/sig000000a0 , \blk00000003/sig000000a1 , \blk00000003/sig000000a2 , \blk00000003/sig000000a3 , \blk00000003/sig000000a4 }), + .OPMODE({\blk00000003/sig00000082 , \blk00000003/sig00000082 , \blk00000003/sig00000082 , \blk00000003/sig00000083 , \blk00000003/sig00000083 , +\blk00000003/sig00000083 , \blk00000003/sig00000082 , \blk00000003/sig00000083 }), + .PCIN({\blk00000003/sig00000082 , \blk00000003/sig00000082 , \blk00000003/sig00000082 , \blk00000003/sig00000082 , \blk00000003/sig00000082 , +\blk00000003/sig00000082 , \blk00000003/sig00000082 , \blk00000003/sig00000082 , \blk00000003/sig00000082 , \blk00000003/sig00000082 , +\blk00000003/sig00000082 , \blk00000003/sig00000082 , \blk00000003/sig00000082 , \blk00000003/sig00000082 , \blk00000003/sig00000082 , +\blk00000003/sig00000082 , \blk00000003/sig00000082 , \blk00000003/sig00000082 , \blk00000003/sig00000082 , \blk00000003/sig00000082 , +\blk00000003/sig00000082 , \blk00000003/sig00000082 , \blk00000003/sig00000082 , \blk00000003/sig00000082 , \blk00000003/sig00000082 , +\blk00000003/sig00000082 , \blk00000003/sig00000082 , \blk00000003/sig00000082 , \blk00000003/sig00000082 , \blk00000003/sig00000082 , +\blk00000003/sig00000082 , \blk00000003/sig00000082 , \blk00000003/sig00000082 , \blk00000003/sig00000082 , \blk00000003/sig00000082 , +\blk00000003/sig00000082 , \blk00000003/sig00000082 , \blk00000003/sig00000082 , \blk00000003/sig00000082 , \blk00000003/sig00000082 , +\blk00000003/sig00000082 , \blk00000003/sig00000082 , \blk00000003/sig00000082 , \blk00000003/sig00000082 , \blk00000003/sig00000082 , +\blk00000003/sig00000082 , \blk00000003/sig00000082 , \blk00000003/sig00000082 }), + .PCOUT({\NLW_blk00000003/blk00000007_PCOUT<47>_UNCONNECTED , \NLW_blk00000003/blk00000007_PCOUT<46>_UNCONNECTED , +\NLW_blk00000003/blk00000007_PCOUT<45>_UNCONNECTED , \NLW_blk00000003/blk00000007_PCOUT<44>_UNCONNECTED , +\NLW_blk00000003/blk00000007_PCOUT<43>_UNCONNECTED , \NLW_blk00000003/blk00000007_PCOUT<42>_UNCONNECTED , +\NLW_blk00000003/blk00000007_PCOUT<41>_UNCONNECTED , \NLW_blk00000003/blk00000007_PCOUT<40>_UNCONNECTED , +\NLW_blk00000003/blk00000007_PCOUT<39>_UNCONNECTED , \NLW_blk00000003/blk00000007_PCOUT<38>_UNCONNECTED , +\NLW_blk00000003/blk00000007_PCOUT<37>_UNCONNECTED , \NLW_blk00000003/blk00000007_PCOUT<36>_UNCONNECTED , +\NLW_blk00000003/blk00000007_PCOUT<35>_UNCONNECTED , \NLW_blk00000003/blk00000007_PCOUT<34>_UNCONNECTED , +\NLW_blk00000003/blk00000007_PCOUT<33>_UNCONNECTED , \NLW_blk00000003/blk00000007_PCOUT<32>_UNCONNECTED , +\NLW_blk00000003/blk00000007_PCOUT<31>_UNCONNECTED , \NLW_blk00000003/blk00000007_PCOUT<30>_UNCONNECTED , +\NLW_blk00000003/blk00000007_PCOUT<29>_UNCONNECTED , \NLW_blk00000003/blk00000007_PCOUT<28>_UNCONNECTED , +\NLW_blk00000003/blk00000007_PCOUT<27>_UNCONNECTED , \NLW_blk00000003/blk00000007_PCOUT<26>_UNCONNECTED , +\NLW_blk00000003/blk00000007_PCOUT<25>_UNCONNECTED , \NLW_blk00000003/blk00000007_PCOUT<24>_UNCONNECTED , +\NLW_blk00000003/blk00000007_PCOUT<23>_UNCONNECTED , \NLW_blk00000003/blk00000007_PCOUT<22>_UNCONNECTED , +\NLW_blk00000003/blk00000007_PCOUT<21>_UNCONNECTED , \NLW_blk00000003/blk00000007_PCOUT<20>_UNCONNECTED , +\NLW_blk00000003/blk00000007_PCOUT<19>_UNCONNECTED , \NLW_blk00000003/blk00000007_PCOUT<18>_UNCONNECTED , +\NLW_blk00000003/blk00000007_PCOUT<17>_UNCONNECTED , \NLW_blk00000003/blk00000007_PCOUT<16>_UNCONNECTED , +\NLW_blk00000003/blk00000007_PCOUT<15>_UNCONNECTED , \NLW_blk00000003/blk00000007_PCOUT<14>_UNCONNECTED , +\NLW_blk00000003/blk00000007_PCOUT<13>_UNCONNECTED , \NLW_blk00000003/blk00000007_PCOUT<12>_UNCONNECTED , +\NLW_blk00000003/blk00000007_PCOUT<11>_UNCONNECTED , \NLW_blk00000003/blk00000007_PCOUT<10>_UNCONNECTED , +\NLW_blk00000003/blk00000007_PCOUT<9>_UNCONNECTED , \NLW_blk00000003/blk00000007_PCOUT<8>_UNCONNECTED , +\NLW_blk00000003/blk00000007_PCOUT<7>_UNCONNECTED , \NLW_blk00000003/blk00000007_PCOUT<6>_UNCONNECTED , +\NLW_blk00000003/blk00000007_PCOUT<5>_UNCONNECTED , \NLW_blk00000003/blk00000007_PCOUT<4>_UNCONNECTED , +\NLW_blk00000003/blk00000007_PCOUT<3>_UNCONNECTED , \NLW_blk00000003/blk00000007_PCOUT<2>_UNCONNECTED , +\NLW_blk00000003/blk00000007_PCOUT<1>_UNCONNECTED , \NLW_blk00000003/blk00000007_PCOUT<0>_UNCONNECTED }), + .BCOUT({\NLW_blk00000003/blk00000007_BCOUT<17>_UNCONNECTED , \NLW_blk00000003/blk00000007_BCOUT<16>_UNCONNECTED , +\NLW_blk00000003/blk00000007_BCOUT<15>_UNCONNECTED , \NLW_blk00000003/blk00000007_BCOUT<14>_UNCONNECTED , +\NLW_blk00000003/blk00000007_BCOUT<13>_UNCONNECTED , \NLW_blk00000003/blk00000007_BCOUT<12>_UNCONNECTED , +\NLW_blk00000003/blk00000007_BCOUT<11>_UNCONNECTED , \NLW_blk00000003/blk00000007_BCOUT<10>_UNCONNECTED , +\NLW_blk00000003/blk00000007_BCOUT<9>_UNCONNECTED , \NLW_blk00000003/blk00000007_BCOUT<8>_UNCONNECTED , +\NLW_blk00000003/blk00000007_BCOUT<7>_UNCONNECTED , \NLW_blk00000003/blk00000007_BCOUT<6>_UNCONNECTED , +\NLW_blk00000003/blk00000007_BCOUT<5>_UNCONNECTED , \NLW_blk00000003/blk00000007_BCOUT<4>_UNCONNECTED , +\NLW_blk00000003/blk00000007_BCOUT<3>_UNCONNECTED , \NLW_blk00000003/blk00000007_BCOUT<2>_UNCONNECTED , +\NLW_blk00000003/blk00000007_BCOUT<1>_UNCONNECTED , \NLW_blk00000003/blk00000007_BCOUT<0>_UNCONNECTED }) + ); + DSP48A #( + .A0REG ( 0 ), + .A1REG ( 1 ), + .B0REG ( 0 ), + .B1REG ( 1 ), + .CARRYINREG ( 0 ), + .CARRYINSEL ( "OPMODE5" ), + .CREG ( 0 ), + .DREG ( 0 ), + .MREG ( 1 ), + .OPMODEREG ( 0 ), + .PREG ( 1 ), + .RSTTYPE ( "SYNC" )) + \blk00000003/blk00000006 ( + .CARRYIN(\blk00000003/sig00000082 ), + .CARRYOUT(\NLW_blk00000003/blk00000006_CARRYOUT_UNCONNECTED ), + .CLK(clk), + .RSTA(\blk00000003/sig00000082 ), + .RSTB(\blk00000003/sig00000082 ), + .RSTM(\blk00000003/sig00000082 ), + .RSTP(\blk00000003/sig00000082 ), + .RSTC(\blk00000003/sig00000082 ), + .RSTD(\blk00000003/sig00000082 ), + .RSTCARRYIN(\blk00000003/sig00000082 ), + .RSTOPMODE(\blk00000003/sig00000082 ), + .CEA(\blk00000003/sig00000083 ), + .CEB(\blk00000003/sig00000083 ), + .CEM(\blk00000003/sig00000083 ), + .CEP(\blk00000003/sig00000083 ), + .CEC(\blk00000003/sig00000082 ), + .CED(\blk00000003/sig00000082 ), + .CECARRYIN(\blk00000003/sig00000082 ), + .CEOPMODE(\blk00000003/sig00000082 ), + .A({ar_0[15], ar_0[15], ar_0[15], ar_0[14], ar_0[13], ar_0[12], ar_0[11], ar_0[10], ar_0[9], ar_0[8], ar_0[7], ar_0[6], ar_0[5], ar_0[4], ar_0[3] +, ar_0[2], ar_0[1], ar_0[0]}), + .B({br_2[15], br_2[15], br_2[15], br_2[14], br_2[13], br_2[12], br_2[11], br_2[10], br_2[9], br_2[8], br_2[7], br_2[6], br_2[5], br_2[4], br_2[3] +, br_2[2], br_2[1], br_2[0]}), + .D({bi_3[15], bi_3[15], bi_3[15], bi_3[14], bi_3[13], bi_3[12], bi_3[11], bi_3[10], bi_3[9], bi_3[8], bi_3[7], bi_3[6], bi_3[5], bi_3[4], bi_3[3] +, bi_3[2], bi_3[1], bi_3[0]}), + .C({\blk00000003/sig00000084 , \blk00000003/sig00000084 , \blk00000003/sig00000084 , \blk00000003/sig00000084 , \blk00000003/sig00000084 , +\blk00000003/sig00000084 , \blk00000003/sig00000084 , \blk00000003/sig00000084 , \blk00000003/sig00000084 , \blk00000003/sig00000084 , +\blk00000003/sig00000084 , \blk00000003/sig00000084 , \blk00000003/sig00000084 , \blk00000003/sig00000084 , \blk00000003/sig00000084 , +\blk00000003/sig00000084 , \blk00000003/sig00000085 , \blk00000003/sig00000086 , \blk00000003/sig00000087 , \blk00000003/sig00000088 , +\blk00000003/sig00000089 , \blk00000003/sig0000008a , \blk00000003/sig0000008b , \blk00000003/sig0000008c , \blk00000003/sig0000008d , +\blk00000003/sig0000008e , \blk00000003/sig0000008f , \blk00000003/sig00000090 , \blk00000003/sig00000091 , \blk00000003/sig00000092 , +\blk00000003/sig00000093 , \blk00000003/sig00000094 , \blk00000003/sig00000095 , \blk00000003/sig00000096 , \blk00000003/sig00000097 , +\blk00000003/sig00000098 , \blk00000003/sig00000099 , \blk00000003/sig0000009a , \blk00000003/sig0000009b , \blk00000003/sig0000009c , +\blk00000003/sig0000009d , \blk00000003/sig0000009e , \blk00000003/sig0000009f , \blk00000003/sig000000a0 , \blk00000003/sig000000a1 , +\blk00000003/sig000000a2 , \blk00000003/sig000000a3 , \blk00000003/sig000000a4 }), + .P({\NLW_blk00000003/blk00000006_P<47>_UNCONNECTED , \NLW_blk00000003/blk00000006_P<46>_UNCONNECTED , +\NLW_blk00000003/blk00000006_P<45>_UNCONNECTED , \NLW_blk00000003/blk00000006_P<44>_UNCONNECTED , \NLW_blk00000003/blk00000006_P<43>_UNCONNECTED , +\NLW_blk00000003/blk00000006_P<42>_UNCONNECTED , \NLW_blk00000003/blk00000006_P<41>_UNCONNECTED , \NLW_blk00000003/blk00000006_P<40>_UNCONNECTED , +\NLW_blk00000003/blk00000006_P<39>_UNCONNECTED , \NLW_blk00000003/blk00000006_P<38>_UNCONNECTED , \NLW_blk00000003/blk00000006_P<37>_UNCONNECTED , +\NLW_blk00000003/blk00000006_P<36>_UNCONNECTED , \NLW_blk00000003/blk00000006_P<35>_UNCONNECTED , \NLW_blk00000003/blk00000006_P<34>_UNCONNECTED , +\NLW_blk00000003/blk00000006_P<33>_UNCONNECTED , \NLW_blk00000003/blk00000006_P<32>_UNCONNECTED , pi_5[31], pi_5[30], pi_5[29], pi_5[28], pi_5[27], +pi_5[26], pi_5[25], pi_5[24], pi_5[23], pi_5[22], pi_5[21], pi_5[20], pi_5[19], pi_5[18], pi_5[17], pi_5[16], pi_5[15], pi_5[14], pi_5[13], pi_5[12], +pi_5[11], pi_5[10], pi_5[9], pi_5[8], pi_5[7], pi_5[6], pi_5[5], pi_5[4], pi_5[3], pi_5[2], pi_5[1], pi_5[0]}), + .OPMODE({\blk00000003/sig00000082 , \blk00000003/sig00000083 , \blk00000003/sig00000082 , \blk00000003/sig00000083 , \blk00000003/sig00000083 , +\blk00000003/sig00000083 , \blk00000003/sig00000082 , \blk00000003/sig00000083 }), + .PCIN({\blk00000003/sig00000082 , \blk00000003/sig00000082 , \blk00000003/sig00000082 , \blk00000003/sig00000082 , \blk00000003/sig00000082 , +\blk00000003/sig00000082 , \blk00000003/sig00000082 , \blk00000003/sig00000082 , \blk00000003/sig00000082 , \blk00000003/sig00000082 , +\blk00000003/sig00000082 , \blk00000003/sig00000082 , \blk00000003/sig00000082 , \blk00000003/sig00000082 , \blk00000003/sig00000082 , +\blk00000003/sig00000082 , \blk00000003/sig00000082 , \blk00000003/sig00000082 , \blk00000003/sig00000082 , \blk00000003/sig00000082 , +\blk00000003/sig00000082 , \blk00000003/sig00000082 , \blk00000003/sig00000082 , \blk00000003/sig00000082 , \blk00000003/sig00000082 , +\blk00000003/sig00000082 , \blk00000003/sig00000082 , \blk00000003/sig00000082 , \blk00000003/sig00000082 , \blk00000003/sig00000082 , +\blk00000003/sig00000082 , \blk00000003/sig00000082 , \blk00000003/sig00000082 , \blk00000003/sig00000082 , \blk00000003/sig00000082 , +\blk00000003/sig00000082 , \blk00000003/sig00000082 , \blk00000003/sig00000082 , \blk00000003/sig00000082 , \blk00000003/sig00000082 , +\blk00000003/sig00000082 , \blk00000003/sig00000082 , \blk00000003/sig00000082 , \blk00000003/sig00000082 , \blk00000003/sig00000082 , +\blk00000003/sig00000082 , \blk00000003/sig00000082 , \blk00000003/sig00000082 }), + .PCOUT({\NLW_blk00000003/blk00000006_PCOUT<47>_UNCONNECTED , \NLW_blk00000003/blk00000006_PCOUT<46>_UNCONNECTED , +\NLW_blk00000003/blk00000006_PCOUT<45>_UNCONNECTED , \NLW_blk00000003/blk00000006_PCOUT<44>_UNCONNECTED , +\NLW_blk00000003/blk00000006_PCOUT<43>_UNCONNECTED , \NLW_blk00000003/blk00000006_PCOUT<42>_UNCONNECTED , +\NLW_blk00000003/blk00000006_PCOUT<41>_UNCONNECTED , \NLW_blk00000003/blk00000006_PCOUT<40>_UNCONNECTED , +\NLW_blk00000003/blk00000006_PCOUT<39>_UNCONNECTED , \NLW_blk00000003/blk00000006_PCOUT<38>_UNCONNECTED , +\NLW_blk00000003/blk00000006_PCOUT<37>_UNCONNECTED , \NLW_blk00000003/blk00000006_PCOUT<36>_UNCONNECTED , +\NLW_blk00000003/blk00000006_PCOUT<35>_UNCONNECTED , \NLW_blk00000003/blk00000006_PCOUT<34>_UNCONNECTED , +\NLW_blk00000003/blk00000006_PCOUT<33>_UNCONNECTED , \NLW_blk00000003/blk00000006_PCOUT<32>_UNCONNECTED , +\NLW_blk00000003/blk00000006_PCOUT<31>_UNCONNECTED , \NLW_blk00000003/blk00000006_PCOUT<30>_UNCONNECTED , +\NLW_blk00000003/blk00000006_PCOUT<29>_UNCONNECTED , \NLW_blk00000003/blk00000006_PCOUT<28>_UNCONNECTED , +\NLW_blk00000003/blk00000006_PCOUT<27>_UNCONNECTED , \NLW_blk00000003/blk00000006_PCOUT<26>_UNCONNECTED , +\NLW_blk00000003/blk00000006_PCOUT<25>_UNCONNECTED , \NLW_blk00000003/blk00000006_PCOUT<24>_UNCONNECTED , +\NLW_blk00000003/blk00000006_PCOUT<23>_UNCONNECTED , \NLW_blk00000003/blk00000006_PCOUT<22>_UNCONNECTED , +\NLW_blk00000003/blk00000006_PCOUT<21>_UNCONNECTED , \NLW_blk00000003/blk00000006_PCOUT<20>_UNCONNECTED , +\NLW_blk00000003/blk00000006_PCOUT<19>_UNCONNECTED , \NLW_blk00000003/blk00000006_PCOUT<18>_UNCONNECTED , +\NLW_blk00000003/blk00000006_PCOUT<17>_UNCONNECTED , \NLW_blk00000003/blk00000006_PCOUT<16>_UNCONNECTED , +\NLW_blk00000003/blk00000006_PCOUT<15>_UNCONNECTED , \NLW_blk00000003/blk00000006_PCOUT<14>_UNCONNECTED , +\NLW_blk00000003/blk00000006_PCOUT<13>_UNCONNECTED , \NLW_blk00000003/blk00000006_PCOUT<12>_UNCONNECTED , +\NLW_blk00000003/blk00000006_PCOUT<11>_UNCONNECTED , \NLW_blk00000003/blk00000006_PCOUT<10>_UNCONNECTED , +\NLW_blk00000003/blk00000006_PCOUT<9>_UNCONNECTED , \NLW_blk00000003/blk00000006_PCOUT<8>_UNCONNECTED , +\NLW_blk00000003/blk00000006_PCOUT<7>_UNCONNECTED , \NLW_blk00000003/blk00000006_PCOUT<6>_UNCONNECTED , +\NLW_blk00000003/blk00000006_PCOUT<5>_UNCONNECTED , \NLW_blk00000003/blk00000006_PCOUT<4>_UNCONNECTED , +\NLW_blk00000003/blk00000006_PCOUT<3>_UNCONNECTED , \NLW_blk00000003/blk00000006_PCOUT<2>_UNCONNECTED , +\NLW_blk00000003/blk00000006_PCOUT<1>_UNCONNECTED , \NLW_blk00000003/blk00000006_PCOUT<0>_UNCONNECTED }), + .BCOUT({\NLW_blk00000003/blk00000006_BCOUT<17>_UNCONNECTED , \NLW_blk00000003/blk00000006_BCOUT<16>_UNCONNECTED , +\NLW_blk00000003/blk00000006_BCOUT<15>_UNCONNECTED , \NLW_blk00000003/blk00000006_BCOUT<14>_UNCONNECTED , +\NLW_blk00000003/blk00000006_BCOUT<13>_UNCONNECTED , \NLW_blk00000003/blk00000006_BCOUT<12>_UNCONNECTED , +\NLW_blk00000003/blk00000006_BCOUT<11>_UNCONNECTED , \NLW_blk00000003/blk00000006_BCOUT<10>_UNCONNECTED , +\NLW_blk00000003/blk00000006_BCOUT<9>_UNCONNECTED , \NLW_blk00000003/blk00000006_BCOUT<8>_UNCONNECTED , +\NLW_blk00000003/blk00000006_BCOUT<7>_UNCONNECTED , \NLW_blk00000003/blk00000006_BCOUT<6>_UNCONNECTED , +\NLW_blk00000003/blk00000006_BCOUT<5>_UNCONNECTED , \NLW_blk00000003/blk00000006_BCOUT<4>_UNCONNECTED , +\NLW_blk00000003/blk00000006_BCOUT<3>_UNCONNECTED , \NLW_blk00000003/blk00000006_BCOUT<2>_UNCONNECTED , +\NLW_blk00000003/blk00000006_BCOUT<1>_UNCONNECTED , \NLW_blk00000003/blk00000006_BCOUT<0>_UNCONNECTED }) + ); + VCC \blk00000003/blk00000005 ( + .P(\blk00000003/sig00000083 ) + ); + GND \blk00000003/blk00000004 ( + .G(\blk00000003/sig00000082 ) + ); + +// synthesis translate_on + +endmodule + +// synthesis translate_off + +`ifndef GLBL +`define GLBL + +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (weak1, weak0) GSR = GSR_int; + assign (weak1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + +endmodule + +`endif + +// synthesis translate_on diff --git a/verilog/coregen/deinter_lut.v b/verilog/coregen/deinter_lut.v new file mode 100644 index 0000000..c9a6a0d --- /dev/null +++ b/verilog/coregen/deinter_lut.v @@ -0,0 +1,137 @@ +/******************************************************************************* +* This file is owned and controlled by Xilinx and must be used * +* solely for design, simulation, implementation and creation of * +* design files limited to Xilinx devices or technologies. Use * +* with non-Xilinx devices or technologies is expressly prohibited * +* and immediately terminates your license. * +* * +* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" * +* SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR * +* XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION * +* AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION * +* OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS * +* IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, * +* AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE * +* FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY * +* WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE * +* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR * +* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF * +* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS * +* FOR A PARTICULAR PURPOSE. * +* * +* Xilinx products are not intended for use in life support * +* appliances, devices, or systems. Use in such applications are * +* expressly prohibited. * +* * +* (c) Copyright 1995-2009 Xilinx, Inc. * +* All rights reserved. * +*******************************************************************************/ +// The synthesis directives "translate_off/translate_on" specified below are +// supported by Xilinx, Mentor Graphics and Synplicity synthesis +// tools. Ensure they are correct for your synthesis tool(s). + +// You must compile the wrapper file deinter_lut.v when simulating +// the core, deinter_lut. When compiling the wrapper file, be sure to +// reference the XilinxCoreLib Verilog simulation library. For detailed +// instructions, please refer to the "CORE Generator Help". + +`timescale 1ns/1ps + +module deinter_lut( + clka, + addra, + douta); + + +input clka; +input [10 : 0] addra; +output [21 : 0] douta; + +// synthesis translate_off + + BLK_MEM_GEN_V4_2 #( + .C_ADDRA_WIDTH(11), + .C_ADDRB_WIDTH(11), + .C_ALGORITHM(1), + .C_BYTE_SIZE(9), + .C_COMMON_CLK(0), + .C_DEFAULT_DATA("0"), + .C_DISABLE_WARN_BHV_COLL(0), + .C_DISABLE_WARN_BHV_RANGE(0), + .C_FAMILY("spartan3"), + .C_HAS_ENA(0), + .C_HAS_ENB(0), + .C_HAS_INJECTERR(0), + .C_HAS_MEM_OUTPUT_REGS_A(0), + .C_HAS_MEM_OUTPUT_REGS_B(0), + .C_HAS_MUX_OUTPUT_REGS_A(0), + .C_HAS_MUX_OUTPUT_REGS_B(0), + .C_HAS_REGCEA(0), + .C_HAS_REGCEB(0), + .C_HAS_RSTA(0), + .C_HAS_RSTB(0), + .C_HAS_SOFTECC_INPUT_REGS_A(0), + .C_HAS_SOFTECC_OUTPUT_REGS_B(0), + .C_INITA_VAL("0"), + .C_INITB_VAL("0"), + .C_INIT_FILE_NAME("deinter_lut.mif"), + .C_LOAD_INIT_FILE(1), + .C_MEM_TYPE(3), + .C_MUX_PIPELINE_STAGES(0), + .C_PRIM_TYPE(1), + .C_READ_DEPTH_A(2048), + .C_READ_DEPTH_B(2048), + .C_READ_WIDTH_A(22), + .C_READ_WIDTH_B(22), + .C_RSTRAM_A(0), + .C_RSTRAM_B(0), + .C_RST_PRIORITY_A("CE"), + .C_RST_PRIORITY_B("CE"), + .C_RST_TYPE("SYNC"), + .C_SIM_COLLISION_CHECK("ALL"), + .C_USE_BYTE_WEA(0), + .C_USE_BYTE_WEB(0), + .C_USE_DEFAULT_DATA(0), + .C_USE_ECC(0), + .C_USE_SOFTECC(0), + .C_WEA_WIDTH(1), + .C_WEB_WIDTH(1), + .C_WRITE_DEPTH_A(2048), + .C_WRITE_DEPTH_B(2048), + .C_WRITE_MODE_A("WRITE_FIRST"), + .C_WRITE_MODE_B("WRITE_FIRST"), + .C_WRITE_WIDTH_A(22), + .C_WRITE_WIDTH_B(22), + .C_XDEVICEFAMILY("spartan3adsp")) + inst ( + .CLKA(clka), + .ADDRA(addra), + .DOUTA(douta), + .RSTA(), + .ENA(), + .REGCEA(), + .WEA(), + .DINA(), + .CLKB(), + .RSTB(), + .ENB(), + .REGCEB(), + .WEB(), + .ADDRB(), + .DINB(), + .DOUTB(), + .INJECTSBITERR(), + .INJECTDBITERR(), + .SBITERR(), + .DBITERR(), + .RDADDRECC()); + + +// synthesis translate_on + +// XST black box declaration +// box_type "black_box" +// synthesis attribute box_type of deinter_lut is "black_box" + +endmodule + diff --git a/verilog/coregen/div_gen_v3_0.v b/verilog/coregen/div_gen_v3_0.v new file mode 100644 index 0000000..b974aab --- /dev/null +++ b/verilog/coregen/div_gen_v3_0.v @@ -0,0 +1,74279 @@ +//////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved. +//////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor: Xilinx +// \ \ \/ Version: M.63c +// \ \ Application: netgen +// / / Filename: div_gen_v3_0.v +// /___/ /\ Timestamp: Thu Sep 15 14:36:34 2016 +// \ \ / \ +// \___\/\___\ +// +// Command : -intstyle ise -w -sim -ofmt verilog ./tmp/_cg/div_gen_v3_0.ngc ./tmp/_cg/div_gen_v3_0.v +// Device : 3sd3400afg676-5 +// Input file : ./tmp/_cg/div_gen_v3_0.ngc +// Output file : ./tmp/_cg/div_gen_v3_0.v +// # of Modules : 1 +// Design Name : div_gen_v3_0 +// Xilinx : /opt/Xilinx/12.2/ISE_DS/ISE/ +// +// Purpose: +// This verilog netlist is a verification model and uses simulation +// primitives which may not represent the true implementation of the +// device, however the netlist is functionally correct and should not +// be modified. This file cannot be synthesized and should only be used +// with supported simulation tools. +// +// Reference: +// Command Line Tools User Guide, Chapter 23 and Synthesis and Simulation Design Guide, Chapter 6 +// +//////////////////////////////////////////////////////////////////////////////// + +`timescale 1 ns/1 ps + +module div_gen_v3_0 ( + rfd, clk, dividend, quotient, divisor, fractional +)/* synthesis syn_black_box syn_noprune=1 */; + output rfd; + input clk; + input [31 : 0] dividend; + output [31 : 0] quotient; + input [23 : 0] divisor; + output [23 : 0] fractional; + + // synthesis translate_off + + wire NlwRenamedSig_OI_rfd; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].divisor_gen.divisor_dc1.del_divisor_msbs/Mshreg_opt_has_pipe.first_q_1_5794 ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].divisor_gen.divisor_dc1.del_divisor_msbs/Mshreg_opt_has_pipe.first_q_2_5793 ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].divisor_gen.divisor_dc1.del_divisor_msbs/Mshreg_opt_has_pipe.first_q_0_5792 ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].divisor_gen.divisor_dc1.del_divisor_msbs/Mshreg_opt_has_pipe.first_q_3_5791 ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].divisor_gen.divisor_dc1.del_divisor_msbs/Mshreg_opt_has_pipe.first_q_4_5790 ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].divisor_gen.divisor_dc1.del_divisor_msbs/Mshreg_opt_has_pipe.first_q_5_5789 ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].divisor_gen.divisor_dc1.del_divisor_msbs/Mshreg_opt_has_pipe.first_q_6_5788 ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].divisor_gen.divisor_dc1.del_divisor_msbs/Mshreg_opt_has_pipe.first_q_8_5787 ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].divisor_gen.divisor_dc1.del_divisor_msbs/Mshreg_opt_has_pipe.first_q_9_5786 ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].divisor_gen.divisor_dc1.del_divisor_msbs/Mshreg_opt_has_pipe.first_q_7_5785 ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].divisor_gen.divisor_dc1.del_divisor_msbs/Mshreg_opt_has_pipe.first_q_10_5784 ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].divisor_gen.divisor_dc1.del_divisor_msbs/Mshreg_opt_has_pipe.first_q_11_5783 ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].divisor_gen.divisor_dc1.del_divisor_msbs/Mshreg_opt_has_pipe.first_q_12_5782 ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].divisor_gen.divisor_dc1.del_divisor_msbs/Mshreg_opt_has_pipe.first_q_13_5781 ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].divisor_gen.divisor_dc1.del_divisor_msbs/Mshreg_opt_has_pipe.first_q_15_5780 ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].divisor_gen.divisor_dc1.del_divisor_msbs/Mshreg_opt_has_pipe.first_q_16_5779 ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].divisor_gen.divisor_dc1.del_divisor_msbs/Mshreg_opt_has_pipe.first_q_14_5778 ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].divisor_gen.divisor_dc1.del_divisor_msbs/Mshreg_opt_has_pipe.first_q_17_5777 ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].divisor_gen.divisor_dc1.del_divisor_msbs/Mshreg_opt_has_pipe.first_q_18_5776 ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].divisor_gen.divisor_dc1.del_divisor_msbs/Mshreg_opt_has_pipe.first_q_19_5775 ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].divisor_gen.divisor_dc1.del_divisor_msbs/Mshreg_opt_has_pipe.first_q_20_5774 ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].divisor_gen.divisor_dc1.del_divisor_msbs/Mshreg_opt_has_pipe.first_q_21_5773 ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].divisor_gen.divisor_dc1.del_divisor_msbs/Mshreg_opt_has_pipe.first_q_22_5772 ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].divisor_gen.divisor_dc1.del_divisor_msbs/Mshreg_opt_has_pipe.first_q_23_5771 ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].num_stages.numerator_gen.del_numer/Mshreg_opt_has_pipe.first_q_0_5770 ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].num_stages.numerator_gen.del_numer/Mshreg_opt_has_pipe.first_q_1_5769 ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].num_stages.numerator_gen.del_numer/Mshreg_opt_has_pipe.first_q_2_5768 ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].num_stages.numerator_gen.del_numer/Mshreg_opt_has_pipe.first_q_3_5767 ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].num_stages.numerator_gen.del_numer/Mshreg_opt_has_pipe.first_q_4_5766 ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].num_stages.numerator_gen.del_numer/Mshreg_opt_has_pipe.first_q_6_5765 ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].num_stages.numerator_gen.del_numer/Mshreg_opt_has_pipe.first_q_7_5764 ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].num_stages.numerator_gen.del_numer/Mshreg_opt_has_pipe.first_q_5_5763 ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].num_stages.numerator_gen.del_numer/Mshreg_opt_has_pipe.first_q_8_5762 ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].num_stages.numerator_gen.del_numer/Mshreg_opt_has_pipe.first_q_9_5761 ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].num_stages.numerator_gen.del_numer/Mshreg_opt_has_pipe.first_q_10_5760 ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].num_stages.numerator_gen.del_numer/Mshreg_opt_has_pipe.first_q_11_5759 ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].num_stages.numerator_gen.del_numer/Mshreg_opt_has_pipe.first_q_13_5758 ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].num_stages.numerator_gen.del_numer/Mshreg_opt_has_pipe.first_q_14_5757 ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].num_stages.numerator_gen.del_numer/Mshreg_opt_has_pipe.first_q_12_5756 ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].num_stages.numerator_gen.del_numer/Mshreg_opt_has_pipe.first_q_15_5755 ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].num_stages.numerator_gen.del_numer/Mshreg_opt_has_pipe.first_q_16_5754 ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].num_stages.numerator_gen.del_numer/Mshreg_opt_has_pipe.first_q_17_5753 ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].num_stages.numerator_gen.del_numer/Mshreg_opt_has_pipe.first_q_18_5752 ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].num_stages.numerator_gen.del_numer/Mshreg_opt_has_pipe.first_q_20_5751 ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].num_stages.numerator_gen.del_numer/Mshreg_opt_has_pipe.first_q_21_5750 ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].num_stages.numerator_gen.del_numer/Mshreg_opt_has_pipe.first_q_19_5749 ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].num_stages.numerator_gen.del_numer/Mshreg_opt_has_pipe.first_q_22_5748 ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].num_stages.numerator_gen.del_numer/Mshreg_opt_has_pipe.first_q_23_5747 ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].num_stages.numerator_gen.del_numer/Mshreg_opt_has_pipe.first_q_24_5746 ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].num_stages.numerator_gen.del_numer/Mshreg_opt_has_pipe.first_q_25_5745 ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].num_stages.numerator_gen.del_numer/Mshreg_opt_has_pipe.first_q_26_5744 ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].num_stages.numerator_gen.del_numer/Mshreg_opt_has_pipe.first_q_27_5743 ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].num_stages.numerator_gen.del_numer/Mshreg_opt_has_pipe.first_q_28_5742 ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].num_stages.numerator_gen.del_numer/Mshreg_opt_has_pipe.first_q_29_5741 ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].num_stages.numerator_gen.del_numer/Mshreg_opt_has_pipe.first_q_30_5740 ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].num_stages.numerator_gen.del_numer/Mshreg_opt_has_pipe.first_q_31_5739 ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sign_pipeline.sign_pipe/Mshreg_opt_has_pipe.pipe_32_0_1_5738 ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sign_pipeline.sign_pipe/Mshreg_opt_has_pipe.pipe_32_0_0_5737 ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sign_pipeline.sign_pipe/Mshreg_opt_has_pipe.pipe_32_1_1_5736 ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sign_pipeline.sign_pipe/Mshreg_opt_has_pipe.pipe_32_1_0_5735 ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sign_pipeline.sign_pipe/opt_has_pipe.pipe_33_0_4_5734 ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sign_pipeline.sign_pipe/opt_has_pipe.pipe_33_0_3_5733 ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sign_pipeline.sign_pipe/opt_has_pipe.pipe_33_1_2_5732 ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sign_pipeline.sign_pipe/opt_has_pipe.pipe_33_0_2_5731 ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sign_pipeline.sign_pipe/opt_has_pipe.pipe_33_1_4_5730 ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sign_pipeline.sign_pipe/opt_has_pipe.pipe_33_1_3_5729 ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24>_0 ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24>_0 ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24>_0 ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sign_pipeline.sign_pipe/opt_has_pipe.pipe_33_1_1_5725 ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sign_pipeline.sign_pipe/opt_has_pipe.pipe_33_0_1_5724 ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.remd_not_fract.cmp_remd/twos_comp/Madd_s_i_cy<0>_rt_5722 ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/quot_det ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.cmp_quot/twos_comp/Madd_s_i_cy<0>_rt_5650 ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/remd_output.adsu_sel2/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q_c_out.i_simple.add_q_cout.q_c_outreg/opt_has_pipe.first_q ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24>_0 ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<0> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<1> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<2> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<3> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<4> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<5> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<6> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<7> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<8> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<9> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<10> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<11> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<12> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<13> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<14> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<15> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<16> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<17> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<18> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<19> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<20> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<21> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<22> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<23> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<24> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<25> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<26> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<27> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<28> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<29> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<30> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<0> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<1> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<2> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<3> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<4> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<5> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<6> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<7> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<8> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<9> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<10> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<11> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<12> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<13> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<14> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<15> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<16> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<17> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<18> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<19> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<20> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<21> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<22> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<23> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<24> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<25> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<26> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<27> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<28> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<29> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<0> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<1> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<2> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<3> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<4> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<5> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<6> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<7> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<8> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<9> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<10> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<11> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<12> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<13> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<14> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<15> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<16> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<17> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<18> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<19> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<20> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<21> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<22> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<23> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<24> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<25> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<26> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<27> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<28> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<0> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<1> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<2> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<3> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<4> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<5> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<6> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<7> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<8> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<9> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<10> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<11> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<12> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<13> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<14> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<15> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<16> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<17> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<18> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<19> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<20> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<21> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<22> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<23> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<24> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<25> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<26> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<27> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<0> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<1> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<2> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<3> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<4> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<5> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<6> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<7> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<8> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<9> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<10> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<11> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<12> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<13> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<14> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<15> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<16> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<17> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<18> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<19> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<20> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<21> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<22> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<23> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<24> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<25> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<26> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<0> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<1> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<2> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<3> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<4> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<5> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<6> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<7> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<8> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<9> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<10> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<11> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<12> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<13> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<14> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<15> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<16> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<17> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<18> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<19> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<20> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<21> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<22> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<23> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<24> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<25> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<0> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<1> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<2> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<3> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<4> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<5> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<6> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<7> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<8> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<9> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<10> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<11> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<12> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<13> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<14> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<15> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<16> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<17> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<18> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<19> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<20> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<21> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<22> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<0> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<1> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<2> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<3> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<4> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<5> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<6> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<7> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<0> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<1> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<2> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<3> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<4> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<5> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<6> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<7> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<8> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<9> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<10> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<11> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<12> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<13> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<14> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<15> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<16> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<17> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<18> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<19> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<20> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<21> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<0> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<1> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<2> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<3> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<4> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<5> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<6> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<7> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<8> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<0> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<1> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<2> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<3> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<4> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<5> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<6> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<7> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<8> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<9> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<10> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<11> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<12> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<13> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<14> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<15> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<16> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<17> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<18> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<19> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<20> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<0> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<1> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<2> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<3> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<4> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<5> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<6> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<7> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<8> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<9> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<0> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<1> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<2> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<3> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<4> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<5> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<6> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<7> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<8> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<9> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<10> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<11> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<12> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<13> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<14> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<15> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<16> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<17> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<18> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<19> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<0> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<1> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<2> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<3> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<4> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<5> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<6> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<7> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<8> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<9> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<10> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<0> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<1> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<2> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<3> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<4> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<5> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<6> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<7> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<8> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<9> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<10> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<11> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<12> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<13> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<14> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<15> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<16> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<17> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<18> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<0> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<1> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<2> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<3> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<4> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<5> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<6> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<7> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<8> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<9> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<10> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<11> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<0> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<1> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<2> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<3> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<4> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<5> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<6> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<7> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<8> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<9> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<10> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<11> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<12> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<13> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<14> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<15> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<16> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<17> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<0> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<1> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<2> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<3> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<4> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<5> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<6> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<7> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<8> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<9> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<10> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<11> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<12> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<0> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<1> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<2> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<3> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<4> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<5> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<6> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<7> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<8> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<9> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<10> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<11> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<12> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<13> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<14> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<15> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<16> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<0> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<1> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<2> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<3> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<4> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<5> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<6> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<7> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<8> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<9> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<10> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<11> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<12> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<13> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<0> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<1> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<2> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<3> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<4> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<5> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<6> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<7> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<8> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<9> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<10> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<11> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<12> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<13> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<14> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<15> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<0> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<1> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<2> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<3> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<4> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<5> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<6> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<7> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<8> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<9> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<10> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<11> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<12> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<13> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<14> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<0> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<1> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<2> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<3> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<4> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<5> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<6> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<7> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<8> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<9> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<10> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<11> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<12> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<13> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<14> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<0> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<1> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<2> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<3> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<4> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<5> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<6> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<7> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<8> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<9> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<10> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<11> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<12> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<13> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<14> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<15> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<0> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<1> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<2> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<3> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<4> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<5> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<6> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<7> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<8> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<9> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<10> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<11> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<12> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<13> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<0> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<1> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<2> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<3> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<4> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<5> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<6> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<7> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<8> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<9> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<10> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<11> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<12> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<13> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<14> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<15> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<16> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<0> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<1> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<2> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<3> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<4> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<5> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<6> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<7> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<8> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<9> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<10> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<11> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<12> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<0> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<1> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<2> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<3> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<4> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<5> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<6> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<7> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<8> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<9> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<10> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<11> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<12> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<13> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<14> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<15> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<16> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<17> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<0> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<1> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<2> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<3> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<4> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<5> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<6> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<7> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<8> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<9> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<10> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<11> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<0> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<1> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<2> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<3> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<4> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<5> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<6> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<7> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<8> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<9> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<10> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<11> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<12> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<13> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<14> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<15> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<16> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<17> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<18> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<0> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<1> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<2> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<3> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<4> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<5> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<6> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<7> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<8> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<9> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<10> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<0> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<1> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<2> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<3> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<4> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<5> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<6> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<7> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<8> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<9> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<10> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<11> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<12> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<13> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<14> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<15> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<16> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<17> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<18> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<19> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<0> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<1> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<2> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<3> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<4> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<5> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<6> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<7> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<8> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<9> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<0> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<1> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<2> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<3> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<4> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<5> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<6> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<7> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<8> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<9> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<10> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<11> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<12> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<13> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<14> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<15> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<16> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<17> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<18> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<19> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<20> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<0> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<1> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<2> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<3> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<4> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<5> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<6> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<7> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<8> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<0> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<1> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<2> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<3> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<4> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<5> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<6> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<7> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<8> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<9> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<10> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<11> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<12> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<13> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<14> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<15> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<16> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<17> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<18> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<19> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<20> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<21> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<0> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<1> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<2> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<3> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<4> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<5> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<6> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<7> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<0> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<1> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<2> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<3> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<4> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<5> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<6> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<7> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<8> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<9> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<10> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<11> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<12> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<13> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<14> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<15> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<16> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<17> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<18> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<19> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<20> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<21> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<22> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<0> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<1> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<2> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<3> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<4> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<5> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<6> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<7> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<8> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<9> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<10> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<11> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<12> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<13> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<14> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<15> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<16> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<17> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<18> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<19> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<20> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<21> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<22> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<23> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<0> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<1> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<2> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<3> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<4> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<5> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<6> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<7> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<8> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<9> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<10> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<11> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<12> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<13> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<14> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<15> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<16> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<17> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<18> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<19> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<20> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<21> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<22> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<23> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<24> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<0> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<1> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<2> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<3> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<4> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<5> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<6> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<7> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<8> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<9> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<10> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<11> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<12> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<13> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<14> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<15> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<16> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<17> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<18> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<19> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<20> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<21> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<22> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<23> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<24> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<25> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<0> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<1> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<2> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<3> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<4> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<5> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<6> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<7> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<8> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<9> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<10> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<11> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<12> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<13> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<14> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<15> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<16> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<17> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<18> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<19> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<20> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<21> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<22> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<23> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<24> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<25> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<26> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<0> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<1> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<2> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<3> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<4> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<5> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<6> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<7> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<8> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<9> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<10> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<11> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<12> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<13> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<14> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<15> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<16> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<17> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<18> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<19> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<20> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<21> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<22> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<23> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<24> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<25> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<26> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<27> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<0> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<1> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<2> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<3> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<4> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<5> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<6> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<7> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<8> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<9> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<10> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<11> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<12> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<13> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<14> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<15> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<16> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<17> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<18> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<19> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<20> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<21> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<22> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<23> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<24> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<25> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<26> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<27> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<28> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<0> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<0> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<1> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<1> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<2> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<2> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<3> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<3> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<4> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<4> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<5> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<5> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<6> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<6> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<7> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<7> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<8> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<8> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<9> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<9> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<10> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<10> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<11> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<11> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<12> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<12> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<13> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<13> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<14> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<14> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<15> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<15> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<16> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<16> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<17> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<17> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<18> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<18> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<19> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<19> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<20> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<20> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<21> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<21> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<22> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<22> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<23> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<23> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<24> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<24> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<25> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<25> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<26> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<26> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<27> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<27> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<28> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<28> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<29> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<29> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<30> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<0> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<1> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<0> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<2> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<1> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<3> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<2> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<4> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<3> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<5> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<4> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<6> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<5> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<7> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<6> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<8> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<7> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<9> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<8> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<10> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<9> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<11> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<10> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<12> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<11> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<13> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<12> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<14> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<13> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<15> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<14> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<16> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<15> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<17> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<16> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<18> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<17> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<19> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<18> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<20> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<19> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<21> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<20> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<22> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<21> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<23> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<22> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<24> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<23> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<0> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<1> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<2> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<3> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<4> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<5> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<6> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<7> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<8> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<9> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<10> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<11> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<12> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<13> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<14> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<15> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<16> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<17> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<18> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<19> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<20> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<21> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<22> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<23> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q_c_out.i_simple.add_q_cout.q_c_outreg/opt_has_pipe.first_q ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<0> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<0> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<24> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<23> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<0> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<1> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<2> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<3> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<4> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<5> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<6> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<7> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<8> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<9> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<10> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<11> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<12> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<13> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<14> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<15> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<16> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<17> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<18> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<19> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<20> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<21> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<22> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<1> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<1> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<0> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<2> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<2> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<1> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<3> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<3> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<2> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<4> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<4> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<3> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<5> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<5> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<4> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<6> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<6> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<5> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<7> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<7> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<6> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<8> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<8> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<7> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<9> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<9> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<8> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<10> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<10> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<9> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<11> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<11> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<10> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<12> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<12> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<11> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<13> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<13> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<12> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<14> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<14> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<13> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<15> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<15> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<14> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<16> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<16> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<15> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<17> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<17> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<16> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<18> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<18> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<17> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<19> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<19> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<18> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<20> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<20> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<19> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<21> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<21> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<20> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<22> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<22> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<21> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<23> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<23> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<22> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<24> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<24> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<23> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q_c_out.i_simple.add_q_cout.q_c_outreg/opt_has_pipe.first_q ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<0> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<0> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<24> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<23> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<0> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<1> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<2> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<3> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<4> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<5> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<6> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<7> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<8> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<9> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<10> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<11> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<12> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<13> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<14> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<15> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<16> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<17> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<18> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<19> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<20> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<21> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<22> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<1> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<1> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<0> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<2> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<2> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<1> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<3> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<3> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<2> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<4> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<4> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<3> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<5> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<5> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<4> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<6> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<6> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<5> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<7> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<7> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<6> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<8> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<8> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<7> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<9> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<9> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<8> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<10> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<10> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<9> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<11> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<11> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<10> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<12> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<12> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<11> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<13> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<13> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<12> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<14> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<14> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<13> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<15> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<15> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<14> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<16> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<16> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<15> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<17> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<17> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<16> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<18> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<18> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<17> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<19> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<19> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<18> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<20> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<20> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<19> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<21> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<21> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<20> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<22> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<22> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<21> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<23> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<23> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<22> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<24> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<24> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<23> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q_c_out.i_simple.add_q_cout.q_c_outreg/opt_has_pipe.first_q ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<0> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<0> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<24> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<23> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<0> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<1> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<2> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<3> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<4> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<5> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<6> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<7> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<8> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<9> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<10> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<11> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<12> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<13> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<14> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<15> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<16> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<17> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<18> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<19> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<20> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<21> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<22> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<1> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<1> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<0> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<2> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<2> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<1> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<3> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<3> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<2> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<4> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<4> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<3> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<5> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<5> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<4> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<6> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<6> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<5> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<7> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<7> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<6> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<8> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<8> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<7> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<9> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<9> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<8> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<10> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<10> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<9> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<11> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<11> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<10> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<12> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<12> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<11> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<13> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<13> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<12> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<14> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<14> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<13> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<15> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<15> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<14> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<16> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<16> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<15> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<17> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<17> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<16> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<18> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<18> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<17> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<19> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<19> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<18> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<20> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<20> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<19> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<21> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<21> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<20> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<22> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<22> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<21> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<23> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<23> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<22> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<24> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<24> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<23> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q_c_out.i_simple.add_q_cout.q_c_outreg/opt_has_pipe.first_q ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<0> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<0> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<24> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<23> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<0> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<1> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<2> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<3> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<4> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<5> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<6> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<7> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<8> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<9> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<10> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<11> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<12> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<13> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<14> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<15> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<16> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<17> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<18> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<19> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<20> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<21> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<22> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<1> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<1> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<0> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<2> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<2> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<1> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<3> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<3> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<2> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<4> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<4> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<3> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<5> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<5> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<4> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<6> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<6> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<5> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<7> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<7> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<6> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<8> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<8> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<7> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<9> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<9> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<8> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<10> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<10> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<9> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<11> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<11> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<10> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<12> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<12> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<11> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<13> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<13> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<12> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<14> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<14> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<13> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<15> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<15> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<14> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<16> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<16> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<15> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<17> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<17> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<16> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<18> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<18> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<17> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<19> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<19> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<18> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<20> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<20> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<19> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<21> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<21> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<20> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<22> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<22> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<21> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<23> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<23> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<22> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<24> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<24> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<23> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q_c_out.i_simple.add_q_cout.q_c_outreg/opt_has_pipe.first_q ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<0> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<0> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<24> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<23> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<0> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<1> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<2> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<3> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<4> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<5> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<6> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<7> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<8> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<9> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<10> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<11> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<12> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<13> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<14> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<15> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<16> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<17> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<18> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<19> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<20> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<21> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<22> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<1> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<1> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<0> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<2> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<2> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<1> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<3> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<3> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<2> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<4> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<4> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<3> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<5> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<5> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<4> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<6> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<6> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<5> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<7> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<7> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<6> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<8> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<8> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<7> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<9> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<9> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<8> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<10> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<10> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<9> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<11> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<11> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<10> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<12> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<12> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<11> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<13> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<13> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<12> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<14> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<14> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<13> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<15> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<15> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<14> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<16> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<16> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<15> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<17> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<17> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<16> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<18> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<18> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<17> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<19> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<19> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<18> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<20> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<20> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<19> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<21> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<21> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<20> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<22> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<22> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<21> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<23> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<23> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<22> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<24> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<24> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<23> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q_c_out.i_simple.add_q_cout.q_c_outreg/opt_has_pipe.first_q ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<0> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<0> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<24> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<23> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<0> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<1> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<2> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<3> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<4> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<5> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<6> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<7> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<8> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<9> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<10> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<11> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<12> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<13> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<14> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<15> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<16> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<17> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<18> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<19> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<20> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<21> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<22> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<1> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<1> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<0> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<2> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<2> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<1> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<3> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<3> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<2> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<4> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<4> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<3> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<5> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<5> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<4> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<6> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<6> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<5> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<7> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<7> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<6> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<8> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<8> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<7> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<9> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<9> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<8> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<10> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<10> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<9> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<11> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<11> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<10> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<12> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<12> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<11> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<13> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<13> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<12> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<14> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<14> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<13> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<15> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<15> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<14> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<16> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<16> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<15> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<17> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<17> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<16> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<18> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<18> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<17> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<19> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<19> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<18> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<20> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<20> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<19> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<21> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<21> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<20> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<22> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<22> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<21> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<23> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<23> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<22> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<24> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<24> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<23> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q_c_out.i_simple.add_q_cout.q_c_outreg/opt_has_pipe.first_q ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<0> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<0> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<24> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<23> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<0> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<1> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<2> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<3> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<4> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<5> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<6> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<7> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<8> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<9> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<10> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<11> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<12> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<13> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<14> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<15> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<16> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<17> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<18> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<19> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<20> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<21> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<22> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<1> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<1> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<0> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<2> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<2> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<1> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<3> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<3> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<2> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<4> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<4> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<3> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<5> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<5> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<4> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<6> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<6> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<5> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<7> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<7> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<6> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<8> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<8> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<7> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<9> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<9> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<8> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<10> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<10> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<9> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<11> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<11> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<10> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<12> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<12> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<11> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<13> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<13> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<12> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<14> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<14> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<13> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<15> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<15> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<14> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<16> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<16> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<15> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<17> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<17> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<16> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<18> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<18> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<17> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<19> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<19> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<18> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<20> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<20> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<19> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<21> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<21> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<20> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<22> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<22> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<21> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<23> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<23> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<22> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<24> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<24> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<23> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q_c_out.i_simple.add_q_cout.q_c_outreg/opt_has_pipe.first_q ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<7> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<0> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<0> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<24> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<23> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<0> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<1> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<2> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<3> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<4> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<5> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<6> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<7> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<8> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<9> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<10> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<11> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<12> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<13> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<14> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<15> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<16> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<17> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<18> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<19> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<20> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<21> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<22> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<1> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<1> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<0> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<2> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<2> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<1> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<3> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<3> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<2> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<4> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<4> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<3> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<5> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<5> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<4> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<6> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<6> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<5> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<7> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<7> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<6> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<8> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<8> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<7> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<9> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<9> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<8> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<10> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<10> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<9> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<11> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<11> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<10> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<12> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<12> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<11> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<13> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<13> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<12> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<14> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<14> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<13> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<15> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<15> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<14> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<16> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<16> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<15> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<17> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<17> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<16> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<18> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<18> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<17> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<19> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<19> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<18> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<20> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<20> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<19> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<21> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<21> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<20> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<22> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<22> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<21> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<23> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<23> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<22> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<24> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<24> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<23> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q_c_out.i_simple.add_q_cout.q_c_outreg/opt_has_pipe.first_q ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<8> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<0> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<0> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<24> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<23> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<0> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<1> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<2> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<3> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<4> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<5> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<6> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<7> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<8> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<9> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<10> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<11> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<12> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<13> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<14> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<15> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<16> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<17> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<18> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<19> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<20> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<21> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<22> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<1> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<1> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<0> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<2> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<2> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<1> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<3> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<3> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<2> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<4> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<4> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<3> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<5> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<5> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<4> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<6> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<6> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<5> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<7> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<7> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<6> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<8> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<8> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<7> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<9> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<9> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<8> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<10> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<10> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<9> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<11> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<11> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<10> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<12> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<12> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<11> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<13> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<13> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<12> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<14> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<14> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<13> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<15> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<15> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<14> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<16> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<16> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<15> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<17> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<17> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<16> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<18> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<18> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<17> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<19> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<19> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<18> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<20> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<20> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<19> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<21> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<21> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<20> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<22> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<22> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<21> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<23> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<23> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<22> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<24> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<24> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<23> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q_c_out.i_simple.add_q_cout.q_c_outreg/opt_has_pipe.first_q ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<9> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<0> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<0> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<24> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<23> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<0> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<1> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<2> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<3> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<4> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<5> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<6> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<7> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<8> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<9> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<10> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<11> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<12> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<13> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<14> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<15> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<16> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<17> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<18> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<19> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<20> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<21> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<22> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<1> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<1> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<0> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<2> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<2> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<1> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<3> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<3> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<2> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<4> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<4> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<3> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<5> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<5> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<4> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<6> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<6> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<5> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<7> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<7> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<6> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<8> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<8> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<7> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<9> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<9> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<8> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<10> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<10> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<9> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<11> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<11> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<10> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<12> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<12> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<11> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<13> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<13> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<12> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<14> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<14> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<13> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<15> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<15> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<14> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<16> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<16> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<15> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<17> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<17> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<16> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<18> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<18> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<17> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<19> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<19> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<18> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<20> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<20> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<19> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<21> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<21> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<20> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<22> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<22> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<21> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<23> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<23> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<22> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<24> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<24> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<23> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q_c_out.i_simple.add_q_cout.q_c_outreg/opt_has_pipe.first_q ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<10> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<0> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<0> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<24> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<23> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<0> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<1> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<2> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<3> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<4> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<5> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<6> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<7> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<8> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<9> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<10> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<11> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<12> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<13> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<14> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<15> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<16> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<17> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<18> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<19> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<20> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<21> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<22> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<1> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<1> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<0> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<2> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<2> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<1> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<3> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<3> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<2> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<4> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<4> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<3> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<5> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<5> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<4> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<6> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<6> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<5> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<7> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<7> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<6> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<8> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<8> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<7> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<9> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<9> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<8> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<10> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<10> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<9> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<11> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<11> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<10> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<12> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<12> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<11> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<13> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<13> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<12> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<14> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<14> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<13> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<15> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<15> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<14> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<16> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<16> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<15> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<17> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<17> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<16> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<18> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<18> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<17> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<19> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<19> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<18> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<20> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<20> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<19> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<21> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<21> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<20> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<22> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<22> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<21> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<23> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<23> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<22> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<24> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<24> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<23> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q_c_out.i_simple.add_q_cout.q_c_outreg/opt_has_pipe.first_q ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<11> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<0> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<0> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<24> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<23> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<0> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<1> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<2> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<3> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<4> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<5> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<6> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<7> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<8> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<9> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<10> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<11> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<12> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<13> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<14> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<15> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<16> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<17> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<18> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<19> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<20> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<21> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<22> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<1> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<1> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<0> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<2> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<2> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<1> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<3> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<3> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<2> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<4> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<4> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<3> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<5> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<5> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<4> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<6> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<6> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<5> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<7> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<7> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<6> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<8> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<8> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<7> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<9> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<9> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<8> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<10> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<10> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<9> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<11> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<11> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<10> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<12> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<12> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<11> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<13> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<13> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<12> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<14> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<14> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<13> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<15> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<15> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<14> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<16> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<16> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<15> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<17> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<17> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<16> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<18> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<18> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<17> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<19> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<19> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<18> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<20> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<20> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<19> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<21> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<21> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<20> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<22> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<22> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<21> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<23> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<23> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<22> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<24> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<24> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<23> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q_c_out.i_simple.add_q_cout.q_c_outreg/opt_has_pipe.first_q ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<12> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<0> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<0> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<24> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<23> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<0> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<1> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<2> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<3> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<4> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<5> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<6> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<7> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<8> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<9> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<10> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<11> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<12> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<13> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<14> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<15> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<16> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<17> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<18> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<19> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<20> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<21> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<22> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<1> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<1> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<0> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<2> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<2> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<1> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<3> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<3> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<2> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<4> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<4> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<3> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<5> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<5> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<4> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<6> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<6> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<5> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<7> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<7> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<6> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<8> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<8> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<7> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<9> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<9> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<8> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<10> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<10> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<9> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<11> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<11> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<10> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<12> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<12> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<11> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<13> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<13> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<12> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<14> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<14> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<13> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<15> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<15> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<14> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<16> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<16> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<15> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<17> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<17> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<16> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<18> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<18> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<17> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<19> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<19> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<18> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<20> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<20> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<19> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<21> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<21> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<20> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<22> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<22> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<21> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<23> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<23> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<22> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<24> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<24> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<23> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q_c_out.i_simple.add_q_cout.q_c_outreg/opt_has_pipe.first_q ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<13> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<0> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<0> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<24> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<23> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<0> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<1> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<2> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<3> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<4> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<5> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<6> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<7> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<8> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<9> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<10> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<11> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<12> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<13> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<14> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<15> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<16> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<17> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<18> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<19> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<20> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<21> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<22> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<1> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<1> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<0> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<2> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<2> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<1> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<3> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<3> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<2> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<4> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<4> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<3> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<5> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<5> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<4> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<6> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<6> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<5> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<7> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<7> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<6> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<8> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<8> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<7> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<9> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<9> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<8> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<10> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<10> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<9> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<11> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<11> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<10> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<12> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<12> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<11> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<13> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<13> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<12> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<14> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<14> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<13> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<15> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<15> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<14> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<16> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<16> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<15> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<17> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<17> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<16> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<18> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<18> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<17> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<19> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<19> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<18> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<20> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<20> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<19> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<21> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<21> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<20> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<22> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<22> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<21> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<23> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<23> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<22> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<24> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<24> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<23> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q_c_out.i_simple.add_q_cout.q_c_outreg/opt_has_pipe.first_q ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<14> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<0> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<0> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<24> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<23> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<0> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<1> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<2> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<3> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<4> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<5> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<6> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<7> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<8> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<9> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<10> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<11> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<12> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<13> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<14> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<15> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<16> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<17> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<18> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<19> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<20> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<21> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<22> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<1> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<1> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<0> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<2> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<2> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<1> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<3> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<3> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<2> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<4> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<4> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<3> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<5> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<5> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<4> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<6> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<6> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<5> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<7> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<7> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<6> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<8> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<8> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<7> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<9> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<9> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<8> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<10> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<10> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<9> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<11> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<11> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<10> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<12> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<12> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<11> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<13> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<13> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<12> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<14> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<14> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<13> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<15> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<15> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<14> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<16> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<16> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<15> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<17> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<17> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<16> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<18> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<18> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<17> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<19> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<19> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<18> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<20> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<20> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<19> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<21> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<21> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<20> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<22> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<22> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<21> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<23> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<23> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<22> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<24> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<24> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<23> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q_c_out.i_simple.add_q_cout.q_c_outreg/opt_has_pipe.first_q ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<15> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<0> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<0> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<24> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<23> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<0> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<1> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<2> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<3> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<4> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<5> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<6> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<7> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<8> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<9> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<10> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<11> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<12> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<13> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<14> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<15> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<16> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<17> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<18> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<19> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<20> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<21> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<22> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<1> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<1> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<0> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<2> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<2> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<1> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<3> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<3> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<2> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<4> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<4> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<3> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<5> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<5> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<4> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<6> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<6> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<5> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<7> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<7> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<6> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<8> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<8> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<7> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<9> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<9> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<8> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<10> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<10> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<9> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<11> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<11> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<10> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<12> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<12> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<11> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<13> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<13> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<12> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<14> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<14> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<13> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<15> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<15> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<14> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<16> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<16> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<15> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<17> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<17> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<16> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<18> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<18> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<17> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<19> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<19> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<18> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<20> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<20> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<19> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<21> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<21> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<20> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<22> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<22> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<21> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<23> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<23> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<22> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<24> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<24> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<23> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q_c_out.i_simple.add_q_cout.q_c_outreg/opt_has_pipe.first_q ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<16> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<0> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<0> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<24> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<23> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<0> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<1> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<2> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<3> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<4> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<5> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<6> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<7> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<8> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<9> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<10> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<11> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<12> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<13> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<14> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<15> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<16> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<17> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<18> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<19> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<20> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<21> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<22> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<1> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<1> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<0> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<2> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<2> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<1> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<3> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<3> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<2> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<4> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<4> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<3> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<5> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<5> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<4> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<6> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<6> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<5> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<7> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<7> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<6> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<8> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<8> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<7> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<9> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<9> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<8> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<10> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<10> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<9> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<11> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<11> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<10> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<12> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<12> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<11> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<13> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<13> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<12> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<14> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<14> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<13> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<15> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<15> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<14> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<16> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<16> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<15> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<17> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<17> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<16> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<18> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<18> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<17> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<19> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<19> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<18> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<20> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<20> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<19> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<21> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<21> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<20> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<22> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<22> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<21> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<23> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<23> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<22> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<24> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<24> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<23> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q_c_out.i_simple.add_q_cout.q_c_outreg/opt_has_pipe.first_q ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<17> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<0> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<0> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<24> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<23> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<0> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<1> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<2> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<3> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<4> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<5> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<6> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<7> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<8> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<9> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<10> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<11> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<12> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<13> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<14> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<15> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<16> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<17> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<18> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<19> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<20> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<21> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<22> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<1> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<1> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<0> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<2> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<2> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<1> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<3> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<3> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<2> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<4> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<4> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<3> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<5> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<5> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<4> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<6> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<6> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<5> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<7> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<7> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<6> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<8> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<8> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<7> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<9> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<9> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<8> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<10> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<10> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<9> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<11> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<11> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<10> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<12> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<12> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<11> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<13> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<13> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<12> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<14> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<14> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<13> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<15> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<15> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<14> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<16> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<16> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<15> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<17> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<17> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<16> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<18> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<18> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<17> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<19> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<19> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<18> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<20> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<20> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<19> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<21> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<21> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<20> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<22> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<22> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<21> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<23> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<23> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<22> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<24> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<24> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<23> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q_c_out.i_simple.add_q_cout.q_c_outreg/opt_has_pipe.first_q ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<18> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<0> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<0> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<24> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<23> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<0> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<1> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<2> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<3> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<4> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<5> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<6> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<7> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<8> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<9> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<10> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<11> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<12> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<13> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<14> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<15> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<16> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<17> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<18> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<19> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<20> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<21> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<22> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<1> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<1> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<0> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<2> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<2> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<1> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<3> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<3> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<2> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<4> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<4> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<3> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<5> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<5> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<4> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<6> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<6> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<5> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<7> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<7> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<6> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<8> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<8> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<7> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<9> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<9> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<8> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<10> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<10> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<9> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<11> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<11> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<10> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<12> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<12> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<11> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<13> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<13> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<12> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<14> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<14> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<13> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<15> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<15> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<14> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<16> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<16> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<15> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<17> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<17> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<16> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<18> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<18> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<17> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<19> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<19> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<18> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<20> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<20> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<19> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<21> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<21> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<20> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<22> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<22> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<21> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<23> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<23> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<22> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<24> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<24> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<23> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q_c_out.i_simple.add_q_cout.q_c_outreg/opt_has_pipe.first_q ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<19> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<0> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<0> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<24> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<23> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<0> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<1> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<2> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<3> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<4> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<5> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<6> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<7> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<8> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<9> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<10> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<11> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<12> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<13> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<14> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<15> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<16> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<17> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<18> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<19> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<20> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<21> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<22> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<1> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<1> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<0> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<2> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<2> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<1> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<3> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<3> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<2> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<4> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<4> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<3> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<5> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<5> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<4> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<6> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<6> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<5> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<7> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<7> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<6> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<8> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<8> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<7> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<9> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<9> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<8> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<10> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<10> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<9> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<11> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<11> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<10> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<12> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<12> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<11> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<13> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<13> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<12> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<14> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<14> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<13> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<15> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<15> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<14> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<16> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<16> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<15> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<17> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<17> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<16> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<18> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<18> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<17> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<19> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<19> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<18> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<20> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<20> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<19> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<21> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<21> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<20> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<22> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<22> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<21> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<23> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<23> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<22> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<24> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<24> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<23> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q_c_out.i_simple.add_q_cout.q_c_outreg/opt_has_pipe.first_q ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<20> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<0> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<0> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<24> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<23> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<0> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<1> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<2> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<3> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<4> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<5> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<6> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<7> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<8> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<9> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<10> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<11> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<12> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<13> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<14> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<15> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<16> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<17> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<18> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<19> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<20> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<21> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<22> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<1> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<1> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<0> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<2> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<2> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<1> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<3> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<3> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<2> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<4> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<4> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<3> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<5> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<5> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<4> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<6> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<6> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<5> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<7> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<7> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<6> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<8> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<8> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<7> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<9> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<9> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<8> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<10> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<10> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<9> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<11> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<11> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<10> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<12> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<12> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<11> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<13> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<13> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<12> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<14> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<14> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<13> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<15> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<15> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<14> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<16> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<16> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<15> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<17> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<17> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<16> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<18> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<18> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<17> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<19> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<19> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<18> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<20> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<20> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<19> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<21> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<21> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<20> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<22> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<22> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<21> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<23> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<23> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<22> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<24> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<24> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<23> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q_c_out.i_simple.add_q_cout.q_c_outreg/opt_has_pipe.first_q ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<21> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<0> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<0> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<24> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<23> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<0> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<1> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<2> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<3> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<4> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<5> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<6> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<7> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<8> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<9> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<10> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<11> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<12> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<13> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<14> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<15> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<16> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<17> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<18> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<19> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<20> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<21> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<22> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<1> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<1> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<0> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<2> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<2> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<1> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<3> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<3> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<2> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<4> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<4> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<3> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<5> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<5> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<4> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<6> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<6> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<5> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<7> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<7> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<6> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<8> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<8> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<7> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<9> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<9> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<8> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<10> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<10> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<9> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<11> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<11> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<10> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<12> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<12> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<11> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<13> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<13> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<12> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<14> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<14> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<13> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<15> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<15> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<14> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<16> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<16> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<15> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<17> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<17> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<16> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<18> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<18> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<17> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<19> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<19> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<18> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<20> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<20> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<19> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<21> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<21> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<20> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<22> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<22> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<21> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<23> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<23> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<22> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<24> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<24> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<23> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q_c_out.i_simple.add_q_cout.q_c_outreg/opt_has_pipe.first_q ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<22> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<0> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<0> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<24> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<23> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<0> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<1> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<2> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<3> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<4> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<5> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<6> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<7> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<8> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<9> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<10> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<11> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<12> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<13> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<14> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<15> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<16> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<17> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<18> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<19> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<20> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<21> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<22> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<1> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<1> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<0> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<2> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<2> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<1> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<3> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<3> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<2> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<4> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<4> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<3> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<5> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<5> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<4> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<6> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<6> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<5> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<7> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<7> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<6> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<8> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<8> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<7> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<9> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<9> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<8> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<10> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<10> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<9> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<11> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<11> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<10> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<12> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<12> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<11> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<13> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<13> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<12> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<14> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<14> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<13> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<15> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<15> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<14> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<16> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<16> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<15> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<17> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<17> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<16> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<18> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<18> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<17> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<19> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<19> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<18> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<20> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<20> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<19> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<21> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<21> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<20> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<22> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<22> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<21> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<23> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<23> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<22> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<24> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<24> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<23> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q_c_out.i_simple.add_q_cout.q_c_outreg/opt_has_pipe.first_q ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<23> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<0> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<0> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<24> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<23> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<0> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<1> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<2> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<3> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<4> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<5> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<6> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<7> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<8> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<9> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<10> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<11> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<12> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<13> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<14> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<15> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<16> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<17> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<18> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<19> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<20> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<21> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<22> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<1> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<1> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<0> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<2> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<2> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<1> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<3> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<3> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<2> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<4> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<4> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<3> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<5> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<5> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<4> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<6> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<6> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<5> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<7> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<7> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<6> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<8> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<8> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<7> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<9> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<9> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<8> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<10> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<10> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<9> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<11> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<11> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<10> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<12> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<12> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<11> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<13> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<13> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<12> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<14> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<14> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<13> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<15> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<15> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<14> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<16> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<16> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<15> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<17> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<17> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<16> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<18> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<18> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<17> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<19> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<19> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<18> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<20> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<20> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<19> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<21> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<21> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<20> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<22> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<22> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<21> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<23> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<23> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<22> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<24> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<24> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<23> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q_c_out.i_simple.add_q_cout.q_c_outreg/opt_has_pipe.first_q ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<24> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<0> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<0> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<24> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<23> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<0> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<1> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<2> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<3> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<4> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<5> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<6> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<7> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<8> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<9> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<10> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<11> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<12> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<13> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<14> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<15> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<16> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<17> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<18> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<19> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<20> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<21> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<22> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<1> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<1> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<0> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<2> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<2> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<1> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<3> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<3> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<2> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<4> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<4> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<3> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<5> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<5> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<4> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<6> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<6> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<5> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<7> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<7> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<6> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<8> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<8> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<7> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<9> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<9> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<8> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<10> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<10> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<9> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<11> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<11> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<10> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<12> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<12> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<11> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<13> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<13> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<12> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<14> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<14> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<13> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<15> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<15> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<14> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<16> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<16> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<15> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<17> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<17> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<16> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<18> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<18> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<17> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<19> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<19> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<18> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<20> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<20> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<19> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<21> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<21> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<20> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<22> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<22> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<21> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<23> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<23> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<22> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<24> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<24> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<23> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q_c_out.i_simple.add_q_cout.q_c_outreg/opt_has_pipe.first_q ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<25> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<0> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<0> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<24> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<23> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<0> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<1> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<2> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<3> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<4> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<5> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<6> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<7> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<8> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<9> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<10> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<11> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<12> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<13> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<14> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<15> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<16> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<17> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<18> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<19> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<20> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<21> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<22> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<1> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<1> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<0> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<2> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<2> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<1> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<3> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<3> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<2> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<4> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<4> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<3> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<5> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<5> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<4> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<6> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<6> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<5> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<7> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<7> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<6> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<8> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<8> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<7> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<9> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<9> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<8> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<10> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<10> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<9> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<11> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<11> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<10> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<12> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<12> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<11> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<13> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<13> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<12> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<14> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<14> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<13> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<15> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<15> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<14> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<16> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<16> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<15> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<17> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<17> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<16> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<18> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<18> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<17> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<19> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<19> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<18> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<20> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<20> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<19> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<21> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<21> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<20> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<22> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<22> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<21> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<23> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<23> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<22> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<24> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<24> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<23> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q_c_out.i_simple.add_q_cout.q_c_outreg/opt_has_pipe.first_q ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<26> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<0> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<0> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<24> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<23> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<0> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<1> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<2> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<3> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<4> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<5> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<6> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<7> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<8> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<9> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<10> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<11> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<12> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<13> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<14> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<15> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<16> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<17> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<18> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<19> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<20> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<21> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<22> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<1> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<1> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<0> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<2> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<2> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<1> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<3> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<3> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<2> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<4> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<4> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<3> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<5> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<5> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<4> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<6> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<6> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<5> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<7> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<7> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<6> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<8> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<8> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<7> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<9> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<9> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<8> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<10> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<10> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<9> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<11> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<11> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<10> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<12> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<12> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<11> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<13> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<13> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<12> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<14> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<14> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<13> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<15> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<15> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<14> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<16> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<16> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<15> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<17> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<17> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<16> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<18> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<18> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<17> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<19> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<19> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<18> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<20> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<20> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<19> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<21> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<21> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<20> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<22> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<22> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<21> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<23> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<23> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<22> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<24> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<24> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<23> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q_c_out.i_simple.add_q_cout.q_c_outreg/opt_has_pipe.first_q ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<27> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<0> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<0> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<24> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<23> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<0> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<1> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<2> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<3> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<4> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<5> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<6> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<7> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<8> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<9> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<10> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<11> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<12> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<13> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<14> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<15> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<16> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<17> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<18> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<19> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<20> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<21> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<22> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<1> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<1> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<0> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<2> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<2> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<1> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<3> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<3> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<2> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<4> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<4> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<3> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<5> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<5> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<4> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<6> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<6> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<5> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<7> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<7> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<6> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<8> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<8> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<7> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<9> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<9> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<8> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<10> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<10> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<9> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<11> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<11> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<10> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<12> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<12> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<11> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<13> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<13> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<12> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<14> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<14> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<13> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<15> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<15> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<14> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<16> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<16> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<15> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<17> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<17> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<16> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<18> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<18> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<17> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<19> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<19> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<18> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<20> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<20> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<19> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<21> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<21> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<20> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<22> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<22> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<21> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<23> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<23> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<22> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<24> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<24> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<23> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q_c_out.i_simple.add_q_cout.q_c_outreg/opt_has_pipe.first_q ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<28> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<0> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<0> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<24> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<23> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<0> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<1> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<2> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<3> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<4> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<5> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<6> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<7> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<8> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<9> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<10> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<11> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<12> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<13> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<14> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<15> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<16> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<17> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<18> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<19> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<20> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<21> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<22> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<1> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<1> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<0> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<2> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<2> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<1> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<3> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<3> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<2> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<4> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<4> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<3> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<5> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<5> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<4> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<6> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<6> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<5> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<7> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<7> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<6> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<8> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<8> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<7> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<9> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<9> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<8> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<10> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<10> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<9> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<11> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<11> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<10> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<12> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<12> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<11> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<13> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<13> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<12> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<14> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<14> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<13> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<15> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<15> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<14> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<16> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<16> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<15> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<17> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<17> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<16> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<18> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<18> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<17> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<19> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<19> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<18> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<20> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<20> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<19> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<21> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<21> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<20> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<22> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<22> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<21> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<23> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<23> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<22> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<24> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<24> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<23> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q_c_out.i_simple.add_q_cout.q_c_outreg/opt_has_pipe.first_q ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<29> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<0> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<0> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<24> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<23> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<0> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<1> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<2> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<3> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<4> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<5> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<6> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<7> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<8> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<9> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<10> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<11> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<12> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<13> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<14> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<15> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<16> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<17> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<18> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<19> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<20> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<21> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<22> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<1> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<1> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<0> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<2> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<2> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<1> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<3> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<3> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<2> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<4> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<4> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<3> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<5> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<5> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<4> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<6> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<6> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<5> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<7> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<7> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<6> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<8> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<8> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<7> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<9> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<9> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<8> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<10> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<10> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<9> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<11> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<11> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<10> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<12> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<12> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<11> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<13> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<13> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<12> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<14> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<14> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<13> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<15> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<15> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<14> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<16> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<16> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<15> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<17> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<17> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<16> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<18> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<18> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<17> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<19> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<19> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<18> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<20> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<20> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<19> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<21> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<21> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<20> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<22> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<22> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<21> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<23> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<23> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<22> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<24> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<24> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<23> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q_c_out.i_simple.add_q_cout.q_c_outreg/opt_has_pipe.first_q ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<30> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<0> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<0> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<24> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<23> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<0> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<1> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<2> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<3> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<4> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<5> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<6> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<7> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<8> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<9> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<10> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<11> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<12> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<13> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<14> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<15> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<16> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<17> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<18> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<19> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<20> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<21> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<22> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<1> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<1> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<0> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<2> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<2> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<1> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<3> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<3> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<2> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<4> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<4> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<3> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<5> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<5> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<4> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<6> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<6> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<5> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<7> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<7> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<6> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<8> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<8> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<7> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<9> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<9> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<8> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<10> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<10> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<9> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<11> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<11> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<10> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<12> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<12> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<11> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<13> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<13> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<12> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<14> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<14> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<13> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<15> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<15> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<14> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<16> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<16> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<15> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<17> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<17> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<16> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<18> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<18> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<17> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<19> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<19> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<18> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<20> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<20> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<19> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<21> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<21> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<20> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<22> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<22> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<21> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<23> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<23> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<22> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<24> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<24> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<23> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q_c_out.i_simple.add_q_cout.q_c_outreg/opt_has_pipe.first_q ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<31> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<0> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<0> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<24> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<1> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<1> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<0> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<2> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<2> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<1> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<3> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<3> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<2> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<4> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<4> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<3> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<5> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<5> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<4> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<6> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<6> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<5> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<7> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<7> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<6> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<8> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<8> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<7> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<9> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<9> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<8> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<10> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<10> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<9> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<11> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<11> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<10> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<12> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<12> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<11> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<13> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<13> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<12> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<14> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<14> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<13> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<15> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<15> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<14> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<16> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<16> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<15> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<17> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<17> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<16> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<18> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<18> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<17> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<19> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<19> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<18> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<20> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<20> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<19> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<21> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<21> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<20> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<22> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<22> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<21> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<23> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<23> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<22> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<24> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<23> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<0> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<1> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<2> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<3> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<4> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<5> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<6> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<7> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<8> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<9> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<10> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<11> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<12> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<13> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<14> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<15> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<16> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<17> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<18> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<19> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<20> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<21> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<22> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<23> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<0> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<1> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<2> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<3> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<4> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<5> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<6> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<7> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<8> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<9> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<10> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<11> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<12> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<13> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<14> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<15> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<16> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<17> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<18> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<19> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<20> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<21> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<22> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<23> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<0> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<1> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<2> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<3> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<4> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<5> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<6> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<7> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<8> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<9> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<10> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<11> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<12> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<13> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<14> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<15> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<16> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<17> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<18> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<19> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<20> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<21> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<22> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<23> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<0> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<1> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<2> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<3> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<4> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<5> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<6> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<7> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<8> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<9> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<10> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<11> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<12> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<13> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<14> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<15> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<16> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<17> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<18> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<19> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<20> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<21> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<22> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<23> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<0> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<1> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<2> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<3> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<4> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<5> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<6> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<7> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<8> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<9> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<10> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<11> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<12> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<13> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<14> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<15> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<16> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<17> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<18> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<19> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<20> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<21> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<22> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<23> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<0> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<1> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<2> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<3> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<4> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<5> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<6> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<7> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<8> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<9> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<10> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<11> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<12> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<13> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<14> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<15> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<16> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<17> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<18> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<19> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<20> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<21> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<22> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<23> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<0> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<1> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<2> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<3> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<4> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<5> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<6> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<7> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<8> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<9> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<10> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<11> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<12> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<13> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<14> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<15> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<16> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<17> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<18> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<19> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<20> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<21> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<22> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<23> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<0> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<1> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<2> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<3> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<4> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<5> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<6> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<7> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<8> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<9> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<10> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<11> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<12> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<13> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<14> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<15> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<16> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<17> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<18> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<19> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<20> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<21> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<22> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<23> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<0> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<1> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<2> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<3> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<4> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<5> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<6> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<7> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<8> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<9> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<10> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<11> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<12> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<13> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<14> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<15> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<16> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<17> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<18> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<19> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<20> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<21> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<22> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<23> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<0> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<1> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<2> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<3> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<4> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<5> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<6> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<7> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<8> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<9> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<10> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<11> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<12> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<13> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<14> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<15> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<16> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<17> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<18> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<19> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<20> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<21> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<22> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<23> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<0> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<1> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<2> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<3> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<4> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<5> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<6> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<7> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<8> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<9> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<10> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<11> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<12> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<13> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<14> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<15> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<16> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<17> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<18> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<19> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<20> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<21> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<22> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<23> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<0> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<1> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<2> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<3> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<4> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<5> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<6> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<7> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<8> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<9> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<10> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<11> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<12> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<13> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<14> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<15> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<16> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<17> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<18> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<19> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<20> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<21> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<22> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<23> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<0> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<1> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<2> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<3> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<4> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<5> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<6> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<7> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<8> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<9> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<10> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<11> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<12> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<13> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<14> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<15> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<16> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<17> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<18> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<19> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<20> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<21> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<22> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<23> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<0> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<1> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<2> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<3> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<4> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<5> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<6> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<7> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<8> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<9> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<10> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<11> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<12> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<13> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<14> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<15> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<16> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<17> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<18> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<19> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<20> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<21> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<22> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<23> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<0> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<1> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<2> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<3> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<4> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<5> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<6> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<7> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<8> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<9> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<10> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<11> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<12> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<13> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<14> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<15> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<16> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<17> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<18> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<19> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<20> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<21> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<22> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<23> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<0> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<1> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<2> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<3> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<4> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<5> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<6> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<7> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<8> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<9> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<10> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<11> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<12> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<13> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<14> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<15> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<16> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<17> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<18> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<19> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<20> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<21> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<22> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<23> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<0> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<1> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<2> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<3> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<4> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<5> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<6> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<7> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<8> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<9> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<10> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<11> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<12> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<13> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<14> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<15> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<16> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<17> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<18> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<19> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<20> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<21> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<22> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<23> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<0> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<1> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<2> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<3> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<4> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<5> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<6> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<7> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<8> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<9> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<10> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<11> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<12> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<13> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<14> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<15> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<16> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<17> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<18> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<19> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<20> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<21> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<22> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<23> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<0> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<1> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<2> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<3> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<4> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<5> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<6> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<7> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<8> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<9> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<10> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<11> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<12> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<13> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<14> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<15> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<16> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<17> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<18> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<19> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<20> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<21> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<22> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<23> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<0> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<1> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<2> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<3> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<4> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<5> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<6> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<7> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<8> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<9> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<10> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<11> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<12> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<13> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<14> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<15> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<16> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<17> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<18> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<19> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<20> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<21> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<22> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<23> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<0> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<1> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<2> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<3> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<4> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<5> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<6> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<7> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<8> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<9> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<10> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<11> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<12> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<13> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<14> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<15> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<16> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<17> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<18> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<19> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<20> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<21> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<22> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<23> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<0> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<1> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<2> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<3> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<4> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<5> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<6> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<7> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<8> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<9> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<10> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<11> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<12> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<13> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<14> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<15> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<16> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<17> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<18> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<19> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<20> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<21> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<22> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<23> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<0> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<1> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<2> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<3> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<4> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<5> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<6> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<7> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<8> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<9> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<10> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<11> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<12> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<13> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<14> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<15> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<16> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<17> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<18> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<19> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<20> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<21> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<22> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<23> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<0> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<1> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<2> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<3> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<4> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<5> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<6> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<7> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<8> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<9> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<10> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<11> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<12> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<13> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<14> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<15> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<16> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<17> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<18> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<19> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<20> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<21> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<22> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<23> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<0> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<1> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<2> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<3> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<4> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<5> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<6> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<7> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<8> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<9> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<10> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<11> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<12> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<13> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<14> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<15> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<16> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<17> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<18> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<19> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<20> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<21> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<22> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<23> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<0> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<1> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<2> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<3> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<4> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<5> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<6> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<7> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<8> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<9> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<10> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<11> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<12> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<13> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<14> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<15> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<16> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<17> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<18> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<19> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<20> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<21> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<22> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<23> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<0> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<1> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<2> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<3> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<4> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<5> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<6> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<7> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<8> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<9> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<10> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<11> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<12> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<13> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<14> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<15> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<16> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<17> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<18> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<19> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<20> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<21> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<22> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<23> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<0> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<1> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<2> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<3> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<4> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<5> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<6> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<7> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<8> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<9> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<10> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<11> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<12> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<13> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<14> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<15> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<16> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<17> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<18> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<19> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<20> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<21> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<22> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<23> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<0> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<1> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<2> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<3> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<4> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<5> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<6> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<7> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<8> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<9> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<10> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<11> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<12> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<13> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<14> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<15> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<16> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<17> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<18> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<19> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<20> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<21> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<22> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<23> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<0> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<1> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<2> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<3> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<4> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<5> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<6> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<7> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<8> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<9> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<10> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<11> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<12> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<13> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<14> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<15> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<16> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<17> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<18> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<19> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<20> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<21> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<22> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<23> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<0> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<1> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<2> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<3> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<4> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<5> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<6> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<7> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<8> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<9> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<10> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<11> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<12> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<13> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<14> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<15> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<16> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<17> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<18> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<19> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<20> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<21> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<22> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<23> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<0> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<1> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<2> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<3> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<4> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<5> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<6> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<7> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<8> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<9> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<10> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<11> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<12> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<13> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<14> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<15> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<16> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<17> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<18> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<19> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<20> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<21> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<22> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<23> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].adder_gen.reg_req.adsu_mod/inv_o ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<1> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<0> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<2> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<1> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<0> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<3> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<2> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<1> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<0> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<4> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<3> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<2> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<1> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<0> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<6> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<5> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<5> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<4> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<4> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<3> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<3> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<2> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<2> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<1> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<1> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<0> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<0> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<6> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<6> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<5> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<4> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<3> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<2> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<1> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<0> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<5> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<5> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<4> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<3> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<2> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<1> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<0> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<4> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<4> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<3> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<2> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<1> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<0> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<3> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<3> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<2> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<1> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<0> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<2> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<2> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<1> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<0> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<1> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<1> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<0> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<0> ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_divisor/twos_comp/Madd_s_i_cy<0>_rt_281 ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_dividend/twos_comp/Madd_s_i_cy<0>_rt_211 ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sign_pipeline.msb_divisor_sync/opt_has_pipe.first_q ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sign_pipeline.msb_dividend_sync/opt_has_pipe.first_q ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sign_pipeline.msb_divisor_start/opt_has_pipe.first_q ; + wire \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sign_pipeline.msb_dividend_start/opt_has_pipe.first_q ; + wire \BU2/divide_by_zero ; + wire NLW_VCC_P_UNCONNECTED; + wire NLW_GND_G_UNCONNECTED; + wire \NLW_BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sign_pipeline.sign_pipe/Mshreg_opt_has_pipe.pipe_32_0_0_Q_UNCONNECTED ; + wire \NLW_BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sign_pipeline.sign_pipe/Mshreg_opt_has_pipe.pipe_32_1_0_Q_UNCONNECTED ; + wire [31 : 0] dividend_2; + wire [23 : 0] divisor_3; + wire [31 : 0] quotient_4; + wire [23 : 0] fractional_5; + wire [23 : 0] \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.remd_not_fract.cmp_remd/twos_comp/s_i ; + wire [23 : 1] \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.remd_not_fract.cmp_remd/twos_comp/simp_addp_a ; + wire [22 : 0] \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.remd_not_fract.cmp_remd/twos_comp/Madd_s_i_cy ; + wire [31 : 0] \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.cmp_quot/twos_comp/s_i ; + wire [31 : 1] \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.cmp_quot/twos_comp/simp_addp_a ; + wire [30 : 0] \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.cmp_quot/twos_comp/Madd_s_i_cy ; + wire [24 : 0] \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/remd_output.adsu_sel2/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q ; + wire [24 : 0] \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/remd_output.adsu_sel2/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.di ; + wire [24 : 0] \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/remd_output.adsu_sel2/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple ; + wire [23 : 0] \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/remd_output.adsu_sel2/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum ; + wire [24 : 0] \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/remd_output.adsu_sel2/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple ; + wire [30 : 0] \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/inv_o ; + wire [23 : 0] \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/final_div.del_end_divisor/opt_has_pipe.first_q ; + wire [31 : 0] \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/reg_quot_out.reg_quot/opt_has_pipe.first_q ; + wire [31 : 1] \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/qpi ; + wire [1 : 0] \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sign_pipeline.sign_pipe/opt_has_pipe.first_q ; + wire [1 : 0] \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sign_pipeline.sign_pipe/opt_has_pipe.pipe_33 ; + wire [1 : 0] \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sign_pipeline.sign_pipe/opt_has_pipe.pipe_32 ; + wire [23 : 0] \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_divisor/twos_comp/s_i ; + wire [22 : 1] \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_divisor/twos_comp/simp_addp_a ; + wire [22 : 0] \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_divisor/twos_comp/Madd_s_i_cy ; + wire [31 : 0] \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_dividend/twos_comp/s_i ; + wire [30 : 1] \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_dividend/twos_comp/simp_addp_a ; + wire [30 : 0] \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_dividend/twos_comp/Madd_s_i_cy ; + assign + dividend_2[31] = dividend[31], + dividend_2[30] = dividend[30], + dividend_2[29] = dividend[29], + dividend_2[28] = dividend[28], + dividend_2[27] = dividend[27], + dividend_2[26] = dividend[26], + dividend_2[25] = dividend[25], + dividend_2[24] = dividend[24], + dividend_2[23] = dividend[23], + dividend_2[22] = dividend[22], + dividend_2[21] = dividend[21], + dividend_2[20] = dividend[20], + dividend_2[19] = dividend[19], + dividend_2[18] = dividend[18], + dividend_2[17] = dividend[17], + dividend_2[16] = dividend[16], + dividend_2[15] = dividend[15], + dividend_2[14] = dividend[14], + dividend_2[13] = dividend[13], + dividend_2[12] = dividend[12], + dividend_2[11] = dividend[11], + dividend_2[10] = dividend[10], + dividend_2[9] = dividend[9], + dividend_2[8] = dividend[8], + dividend_2[7] = dividend[7], + dividend_2[6] = dividend[6], + dividend_2[5] = dividend[5], + dividend_2[4] = dividend[4], + dividend_2[3] = dividend[3], + dividend_2[2] = dividend[2], + dividend_2[1] = dividend[1], + dividend_2[0] = dividend[0], + quotient[31] = quotient_4[31], + quotient[30] = quotient_4[30], + quotient[29] = quotient_4[29], + quotient[28] = quotient_4[28], + quotient[27] = quotient_4[27], + quotient[26] = quotient_4[26], + quotient[25] = quotient_4[25], + quotient[24] = quotient_4[24], + quotient[23] = quotient_4[23], + quotient[22] = quotient_4[22], + quotient[21] = quotient_4[21], + quotient[20] = quotient_4[20], + quotient[19] = quotient_4[19], + quotient[18] = quotient_4[18], + quotient[17] = quotient_4[17], + quotient[16] = quotient_4[16], + quotient[15] = quotient_4[15], + quotient[14] = quotient_4[14], + quotient[13] = quotient_4[13], + quotient[12] = quotient_4[12], + quotient[11] = quotient_4[11], + quotient[10] = quotient_4[10], + quotient[9] = quotient_4[9], + quotient[8] = quotient_4[8], + quotient[7] = quotient_4[7], + quotient[6] = quotient_4[6], + quotient[5] = quotient_4[5], + quotient[4] = quotient_4[4], + quotient[3] = quotient_4[3], + quotient[2] = quotient_4[2], + quotient[1] = quotient_4[1], + quotient[0] = quotient_4[0], + divisor_3[23] = divisor[23], + divisor_3[22] = divisor[22], + divisor_3[21] = divisor[21], + divisor_3[20] = divisor[20], + divisor_3[19] = divisor[19], + divisor_3[18] = divisor[18], + divisor_3[17] = divisor[17], + divisor_3[16] = divisor[16], + divisor_3[15] = divisor[15], + divisor_3[14] = divisor[14], + divisor_3[13] = divisor[13], + divisor_3[12] = divisor[12], + divisor_3[11] = divisor[11], + divisor_3[10] = divisor[10], + divisor_3[9] = divisor[9], + divisor_3[8] = divisor[8], + divisor_3[7] = divisor[7], + divisor_3[6] = divisor[6], + divisor_3[5] = divisor[5], + divisor_3[4] = divisor[4], + divisor_3[3] = divisor[3], + divisor_3[2] = divisor[2], + divisor_3[1] = divisor[1], + divisor_3[0] = divisor[0], + rfd = NlwRenamedSig_OI_rfd, + fractional[23] = fractional_5[23], + fractional[22] = fractional_5[22], + fractional[21] = fractional_5[21], + fractional[20] = fractional_5[20], + fractional[19] = fractional_5[19], + fractional[18] = fractional_5[18], + fractional[17] = fractional_5[17], + fractional[16] = fractional_5[16], + fractional[15] = fractional_5[15], + fractional[14] = fractional_5[14], + fractional[13] = fractional_5[13], + fractional[12] = fractional_5[12], + fractional[11] = fractional_5[11], + fractional[10] = fractional_5[10], + fractional[9] = fractional_5[9], + fractional[8] = fractional_5[8], + fractional[7] = fractional_5[7], + fractional[6] = fractional_5[6], + fractional[5] = fractional_5[5], + fractional[4] = fractional_5[4], + fractional[3] = fractional_5[3], + fractional[2] = fractional_5[2], + fractional[1] = fractional_5[1], + fractional[0] = fractional_5[0]; + VCC VCC_0 ( + .P(NLW_VCC_P_UNCONNECTED) + ); + GND GND_1 ( + .G(NLW_GND_G_UNCONNECTED) + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_1 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].divisor_gen.divisor_dc1.del_divisor_msbs/Mshreg_opt_has_pipe.first_q_1_5794 ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<1> ) + + ); + SRL16 #( + .INIT ( 16'h0000 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].divisor_gen.divisor_dc1.del_divisor_msbs/Mshreg_opt_has_pipe.first_q_1 ( + .A0(\BU2/divide_by_zero ), + .A1(\BU2/divide_by_zero ), + .A2(\BU2/divide_by_zero ), + .A3(\BU2/divide_by_zero ), + .CLK(clk), + .D(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_divisor/twos_comp/s_i [1]), + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].divisor_gen.divisor_dc1.del_divisor_msbs/Mshreg_opt_has_pipe.first_q_1_5794 ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_2 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].divisor_gen.divisor_dc1.del_divisor_msbs/Mshreg_opt_has_pipe.first_q_2_5793 ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<2> ) + + ); + SRL16 #( + .INIT ( 16'h0000 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].divisor_gen.divisor_dc1.del_divisor_msbs/Mshreg_opt_has_pipe.first_q_2 ( + .A0(\BU2/divide_by_zero ), + .A1(\BU2/divide_by_zero ), + .A2(\BU2/divide_by_zero ), + .A3(\BU2/divide_by_zero ), + .CLK(clk), + .D(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_divisor/twos_comp/s_i [2]), + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].divisor_gen.divisor_dc1.del_divisor_msbs/Mshreg_opt_has_pipe.first_q_2_5793 ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_0 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].divisor_gen.divisor_dc1.del_divisor_msbs/Mshreg_opt_has_pipe.first_q_0_5792 ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<0> ) + + ); + SRL16 #( + .INIT ( 16'h0001 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].divisor_gen.divisor_dc1.del_divisor_msbs/Mshreg_opt_has_pipe.first_q_0 ( + .A0(\BU2/divide_by_zero ), + .A1(\BU2/divide_by_zero ), + .A2(\BU2/divide_by_zero ), + .A3(\BU2/divide_by_zero ), + .CLK(clk), + .D(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_divisor/twos_comp/s_i [0]), + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].divisor_gen.divisor_dc1.del_divisor_msbs/Mshreg_opt_has_pipe.first_q_0_5792 ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_3 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].divisor_gen.divisor_dc1.del_divisor_msbs/Mshreg_opt_has_pipe.first_q_3_5791 ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<3> ) + + ); + SRL16 #( + .INIT ( 16'h0000 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].divisor_gen.divisor_dc1.del_divisor_msbs/Mshreg_opt_has_pipe.first_q_3 ( + .A0(\BU2/divide_by_zero ), + .A1(\BU2/divide_by_zero ), + .A2(\BU2/divide_by_zero ), + .A3(\BU2/divide_by_zero ), + .CLK(clk), + .D(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_divisor/twos_comp/s_i [3]), + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].divisor_gen.divisor_dc1.del_divisor_msbs/Mshreg_opt_has_pipe.first_q_3_5791 ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_4 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].divisor_gen.divisor_dc1.del_divisor_msbs/Mshreg_opt_has_pipe.first_q_4_5790 ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<4> ) + + ); + SRL16 #( + .INIT ( 16'h0000 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].divisor_gen.divisor_dc1.del_divisor_msbs/Mshreg_opt_has_pipe.first_q_4 ( + .A0(\BU2/divide_by_zero ), + .A1(\BU2/divide_by_zero ), + .A2(\BU2/divide_by_zero ), + .A3(\BU2/divide_by_zero ), + .CLK(clk), + .D(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_divisor/twos_comp/s_i [4]), + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].divisor_gen.divisor_dc1.del_divisor_msbs/Mshreg_opt_has_pipe.first_q_4_5790 ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_5 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].divisor_gen.divisor_dc1.del_divisor_msbs/Mshreg_opt_has_pipe.first_q_5_5789 ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<5> ) + + ); + SRL16 #( + .INIT ( 16'h0000 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].divisor_gen.divisor_dc1.del_divisor_msbs/Mshreg_opt_has_pipe.first_q_5 ( + .A0(\BU2/divide_by_zero ), + .A1(\BU2/divide_by_zero ), + .A2(\BU2/divide_by_zero ), + .A3(\BU2/divide_by_zero ), + .CLK(clk), + .D(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_divisor/twos_comp/s_i [5]), + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].divisor_gen.divisor_dc1.del_divisor_msbs/Mshreg_opt_has_pipe.first_q_5_5789 ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_6 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].divisor_gen.divisor_dc1.del_divisor_msbs/Mshreg_opt_has_pipe.first_q_6_5788 ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<6> ) + + ); + SRL16 #( + .INIT ( 16'h0000 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].divisor_gen.divisor_dc1.del_divisor_msbs/Mshreg_opt_has_pipe.first_q_6 ( + .A0(\BU2/divide_by_zero ), + .A1(\BU2/divide_by_zero ), + .A2(\BU2/divide_by_zero ), + .A3(\BU2/divide_by_zero ), + .CLK(clk), + .D(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_divisor/twos_comp/s_i [6]), + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].divisor_gen.divisor_dc1.del_divisor_msbs/Mshreg_opt_has_pipe.first_q_6_5788 ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_8 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].divisor_gen.divisor_dc1.del_divisor_msbs/Mshreg_opt_has_pipe.first_q_8_5787 ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<8> ) + + ); + SRL16 #( + .INIT ( 16'h0000 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].divisor_gen.divisor_dc1.del_divisor_msbs/Mshreg_opt_has_pipe.first_q_8 ( + .A0(\BU2/divide_by_zero ), + .A1(\BU2/divide_by_zero ), + .A2(\BU2/divide_by_zero ), + .A3(\BU2/divide_by_zero ), + .CLK(clk), + .D(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_divisor/twos_comp/s_i [8]), + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].divisor_gen.divisor_dc1.del_divisor_msbs/Mshreg_opt_has_pipe.first_q_8_5787 ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_9 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].divisor_gen.divisor_dc1.del_divisor_msbs/Mshreg_opt_has_pipe.first_q_9_5786 ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<9> ) + + ); + SRL16 #( + .INIT ( 16'h0000 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].divisor_gen.divisor_dc1.del_divisor_msbs/Mshreg_opt_has_pipe.first_q_9 ( + .A0(\BU2/divide_by_zero ), + .A1(\BU2/divide_by_zero ), + .A2(\BU2/divide_by_zero ), + .A3(\BU2/divide_by_zero ), + .CLK(clk), + .D(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_divisor/twos_comp/s_i [9]), + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].divisor_gen.divisor_dc1.del_divisor_msbs/Mshreg_opt_has_pipe.first_q_9_5786 ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_7 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].divisor_gen.divisor_dc1.del_divisor_msbs/Mshreg_opt_has_pipe.first_q_7_5785 ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<7> ) + + ); + SRL16 #( + .INIT ( 16'h0000 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].divisor_gen.divisor_dc1.del_divisor_msbs/Mshreg_opt_has_pipe.first_q_7 ( + .A0(\BU2/divide_by_zero ), + .A1(\BU2/divide_by_zero ), + .A2(\BU2/divide_by_zero ), + .A3(\BU2/divide_by_zero ), + .CLK(clk), + .D(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_divisor/twos_comp/s_i [7]), + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].divisor_gen.divisor_dc1.del_divisor_msbs/Mshreg_opt_has_pipe.first_q_7_5785 ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_10 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].divisor_gen.divisor_dc1.del_divisor_msbs/Mshreg_opt_has_pipe.first_q_10_5784 ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<10> ) + + ); + SRL16 #( + .INIT ( 16'h0000 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].divisor_gen.divisor_dc1.del_divisor_msbs/Mshreg_opt_has_pipe.first_q_10 ( + .A0(\BU2/divide_by_zero ), + .A1(\BU2/divide_by_zero ), + .A2(\BU2/divide_by_zero ), + .A3(\BU2/divide_by_zero ), + .CLK(clk), + .D(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_divisor/twos_comp/s_i [10]), + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].divisor_gen.divisor_dc1.del_divisor_msbs/Mshreg_opt_has_pipe.first_q_10_5784 ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_11 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].divisor_gen.divisor_dc1.del_divisor_msbs/Mshreg_opt_has_pipe.first_q_11_5783 ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<11> ) + + ); + SRL16 #( + .INIT ( 16'h0000 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].divisor_gen.divisor_dc1.del_divisor_msbs/Mshreg_opt_has_pipe.first_q_11 ( + .A0(\BU2/divide_by_zero ), + .A1(\BU2/divide_by_zero ), + .A2(\BU2/divide_by_zero ), + .A3(\BU2/divide_by_zero ), + .CLK(clk), + .D(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_divisor/twos_comp/s_i [11]), + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].divisor_gen.divisor_dc1.del_divisor_msbs/Mshreg_opt_has_pipe.first_q_11_5783 ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_12 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].divisor_gen.divisor_dc1.del_divisor_msbs/Mshreg_opt_has_pipe.first_q_12_5782 ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<12> ) + + ); + SRL16 #( + .INIT ( 16'h0000 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].divisor_gen.divisor_dc1.del_divisor_msbs/Mshreg_opt_has_pipe.first_q_12 ( + .A0(\BU2/divide_by_zero ), + .A1(\BU2/divide_by_zero ), + .A2(\BU2/divide_by_zero ), + .A3(\BU2/divide_by_zero ), + .CLK(clk), + .D(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_divisor/twos_comp/s_i [12]), + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].divisor_gen.divisor_dc1.del_divisor_msbs/Mshreg_opt_has_pipe.first_q_12_5782 ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_13 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].divisor_gen.divisor_dc1.del_divisor_msbs/Mshreg_opt_has_pipe.first_q_13_5781 ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<13> ) + + ); + SRL16 #( + .INIT ( 16'h0000 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].divisor_gen.divisor_dc1.del_divisor_msbs/Mshreg_opt_has_pipe.first_q_13 ( + .A0(\BU2/divide_by_zero ), + .A1(\BU2/divide_by_zero ), + .A2(\BU2/divide_by_zero ), + .A3(\BU2/divide_by_zero ), + .CLK(clk), + .D(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_divisor/twos_comp/s_i [13]), + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].divisor_gen.divisor_dc1.del_divisor_msbs/Mshreg_opt_has_pipe.first_q_13_5781 ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_15 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].divisor_gen.divisor_dc1.del_divisor_msbs/Mshreg_opt_has_pipe.first_q_15_5780 ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<15> ) + + ); + SRL16 #( + .INIT ( 16'h0000 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].divisor_gen.divisor_dc1.del_divisor_msbs/Mshreg_opt_has_pipe.first_q_15 ( + .A0(\BU2/divide_by_zero ), + .A1(\BU2/divide_by_zero ), + .A2(\BU2/divide_by_zero ), + .A3(\BU2/divide_by_zero ), + .CLK(clk), + .D(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_divisor/twos_comp/s_i [15]), + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].divisor_gen.divisor_dc1.del_divisor_msbs/Mshreg_opt_has_pipe.first_q_15_5780 ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_16 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].divisor_gen.divisor_dc1.del_divisor_msbs/Mshreg_opt_has_pipe.first_q_16_5779 ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<16> ) + + ); + SRL16 #( + .INIT ( 16'h0000 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].divisor_gen.divisor_dc1.del_divisor_msbs/Mshreg_opt_has_pipe.first_q_16 ( + .A0(\BU2/divide_by_zero ), + .A1(\BU2/divide_by_zero ), + .A2(\BU2/divide_by_zero ), + .A3(\BU2/divide_by_zero ), + .CLK(clk), + .D(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_divisor/twos_comp/s_i [16]), + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].divisor_gen.divisor_dc1.del_divisor_msbs/Mshreg_opt_has_pipe.first_q_16_5779 ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_14 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].divisor_gen.divisor_dc1.del_divisor_msbs/Mshreg_opt_has_pipe.first_q_14_5778 ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<14> ) + + ); + SRL16 #( + .INIT ( 16'h0000 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].divisor_gen.divisor_dc1.del_divisor_msbs/Mshreg_opt_has_pipe.first_q_14 ( + .A0(\BU2/divide_by_zero ), + .A1(\BU2/divide_by_zero ), + .A2(\BU2/divide_by_zero ), + .A3(\BU2/divide_by_zero ), + .CLK(clk), + .D(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_divisor/twos_comp/s_i [14]), + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].divisor_gen.divisor_dc1.del_divisor_msbs/Mshreg_opt_has_pipe.first_q_14_5778 ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_17 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].divisor_gen.divisor_dc1.del_divisor_msbs/Mshreg_opt_has_pipe.first_q_17_5777 ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<17> ) + + ); + SRL16 #( + .INIT ( 16'h0000 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].divisor_gen.divisor_dc1.del_divisor_msbs/Mshreg_opt_has_pipe.first_q_17 ( + .A0(\BU2/divide_by_zero ), + .A1(\BU2/divide_by_zero ), + .A2(\BU2/divide_by_zero ), + .A3(\BU2/divide_by_zero ), + .CLK(clk), + .D(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_divisor/twos_comp/s_i [17]), + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].divisor_gen.divisor_dc1.del_divisor_msbs/Mshreg_opt_has_pipe.first_q_17_5777 ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_18 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].divisor_gen.divisor_dc1.del_divisor_msbs/Mshreg_opt_has_pipe.first_q_18_5776 ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<18> ) + + ); + SRL16 #( + .INIT ( 16'h0000 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].divisor_gen.divisor_dc1.del_divisor_msbs/Mshreg_opt_has_pipe.first_q_18 ( + .A0(\BU2/divide_by_zero ), + .A1(\BU2/divide_by_zero ), + .A2(\BU2/divide_by_zero ), + .A3(\BU2/divide_by_zero ), + .CLK(clk), + .D(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_divisor/twos_comp/s_i [18]), + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].divisor_gen.divisor_dc1.del_divisor_msbs/Mshreg_opt_has_pipe.first_q_18_5776 ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_19 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].divisor_gen.divisor_dc1.del_divisor_msbs/Mshreg_opt_has_pipe.first_q_19_5775 ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<19> ) + + ); + SRL16 #( + .INIT ( 16'h0000 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].divisor_gen.divisor_dc1.del_divisor_msbs/Mshreg_opt_has_pipe.first_q_19 ( + .A0(\BU2/divide_by_zero ), + .A1(\BU2/divide_by_zero ), + .A2(\BU2/divide_by_zero ), + .A3(\BU2/divide_by_zero ), + .CLK(clk), + .D(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_divisor/twos_comp/s_i [19]), + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].divisor_gen.divisor_dc1.del_divisor_msbs/Mshreg_opt_has_pipe.first_q_19_5775 ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_20 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].divisor_gen.divisor_dc1.del_divisor_msbs/Mshreg_opt_has_pipe.first_q_20_5774 ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<20> ) + + ); + SRL16 #( + .INIT ( 16'h0000 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].divisor_gen.divisor_dc1.del_divisor_msbs/Mshreg_opt_has_pipe.first_q_20 ( + .A0(\BU2/divide_by_zero ), + .A1(\BU2/divide_by_zero ), + .A2(\BU2/divide_by_zero ), + .A3(\BU2/divide_by_zero ), + .CLK(clk), + .D(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_divisor/twos_comp/s_i [20]), + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].divisor_gen.divisor_dc1.del_divisor_msbs/Mshreg_opt_has_pipe.first_q_20_5774 ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_21 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].divisor_gen.divisor_dc1.del_divisor_msbs/Mshreg_opt_has_pipe.first_q_21_5773 ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<21> ) + + ); + SRL16 #( + .INIT ( 16'h0000 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].divisor_gen.divisor_dc1.del_divisor_msbs/Mshreg_opt_has_pipe.first_q_21 ( + .A0(\BU2/divide_by_zero ), + .A1(\BU2/divide_by_zero ), + .A2(\BU2/divide_by_zero ), + .A3(\BU2/divide_by_zero ), + .CLK(clk), + .D(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_divisor/twos_comp/s_i [21]), + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].divisor_gen.divisor_dc1.del_divisor_msbs/Mshreg_opt_has_pipe.first_q_21_5773 ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_22 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].divisor_gen.divisor_dc1.del_divisor_msbs/Mshreg_opt_has_pipe.first_q_22_5772 ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<22> ) + + ); + SRL16 #( + .INIT ( 16'h0000 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].divisor_gen.divisor_dc1.del_divisor_msbs/Mshreg_opt_has_pipe.first_q_22 ( + .A0(\BU2/divide_by_zero ), + .A1(\BU2/divide_by_zero ), + .A2(\BU2/divide_by_zero ), + .A3(\BU2/divide_by_zero ), + .CLK(clk), + .D(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_divisor/twos_comp/s_i [22]), + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].divisor_gen.divisor_dc1.del_divisor_msbs/Mshreg_opt_has_pipe.first_q_22_5772 ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_23 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].divisor_gen.divisor_dc1.del_divisor_msbs/Mshreg_opt_has_pipe.first_q_23_5771 ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<23> ) + + ); + SRL16 #( + .INIT ( 16'h0000 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].divisor_gen.divisor_dc1.del_divisor_msbs/Mshreg_opt_has_pipe.first_q_23 ( + .A0(\BU2/divide_by_zero ), + .A1(\BU2/divide_by_zero ), + .A2(\BU2/divide_by_zero ), + .A3(\BU2/divide_by_zero ), + .CLK(clk), + .D(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_divisor/twos_comp/s_i [23]), + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].divisor_gen.divisor_dc1.del_divisor_msbs/Mshreg_opt_has_pipe.first_q_23_5771 ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q_0 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].num_stages.numerator_gen.del_numer/Mshreg_opt_has_pipe.first_q_0_5770 ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<0> ) + + ); + SRL16 #( + .INIT ( 16'h0000 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].num_stages.numerator_gen.del_numer/Mshreg_opt_has_pipe.first_q_0 ( + .A0(\BU2/divide_by_zero ), + .A1(\BU2/divide_by_zero ), + .A2(\BU2/divide_by_zero ), + .A3(\BU2/divide_by_zero ), + .CLK(clk), + .D(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_dividend/twos_comp/s_i [0]), + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].num_stages.numerator_gen.del_numer/Mshreg_opt_has_pipe.first_q_0_5770 ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q_1 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].num_stages.numerator_gen.del_numer/Mshreg_opt_has_pipe.first_q_1_5769 ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<1> ) + + ); + SRL16 #( + .INIT ( 16'h0000 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].num_stages.numerator_gen.del_numer/Mshreg_opt_has_pipe.first_q_1 ( + .A0(\BU2/divide_by_zero ), + .A1(\BU2/divide_by_zero ), + .A2(\BU2/divide_by_zero ), + .A3(\BU2/divide_by_zero ), + .CLK(clk), + .D(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_dividend/twos_comp/s_i [1]), + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].num_stages.numerator_gen.del_numer/Mshreg_opt_has_pipe.first_q_1_5769 ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q_2 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].num_stages.numerator_gen.del_numer/Mshreg_opt_has_pipe.first_q_2_5768 ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<2> ) + + ); + SRL16 #( + .INIT ( 16'h0000 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].num_stages.numerator_gen.del_numer/Mshreg_opt_has_pipe.first_q_2 ( + .A0(\BU2/divide_by_zero ), + .A1(\BU2/divide_by_zero ), + .A2(\BU2/divide_by_zero ), + .A3(\BU2/divide_by_zero ), + .CLK(clk), + .D(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_dividend/twos_comp/s_i [2]), + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].num_stages.numerator_gen.del_numer/Mshreg_opt_has_pipe.first_q_2_5768 ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q_3 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].num_stages.numerator_gen.del_numer/Mshreg_opt_has_pipe.first_q_3_5767 ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<3> ) + + ); + SRL16 #( + .INIT ( 16'h0000 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].num_stages.numerator_gen.del_numer/Mshreg_opt_has_pipe.first_q_3 ( + .A0(\BU2/divide_by_zero ), + .A1(\BU2/divide_by_zero ), + .A2(\BU2/divide_by_zero ), + .A3(\BU2/divide_by_zero ), + .CLK(clk), + .D(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_dividend/twos_comp/s_i [3]), + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].num_stages.numerator_gen.del_numer/Mshreg_opt_has_pipe.first_q_3_5767 ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q_4 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].num_stages.numerator_gen.del_numer/Mshreg_opt_has_pipe.first_q_4_5766 ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<4> ) + + ); + SRL16 #( + .INIT ( 16'h0000 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].num_stages.numerator_gen.del_numer/Mshreg_opt_has_pipe.first_q_4 ( + .A0(\BU2/divide_by_zero ), + .A1(\BU2/divide_by_zero ), + .A2(\BU2/divide_by_zero ), + .A3(\BU2/divide_by_zero ), + .CLK(clk), + .D(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_dividend/twos_comp/s_i [4]), + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].num_stages.numerator_gen.del_numer/Mshreg_opt_has_pipe.first_q_4_5766 ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q_6 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].num_stages.numerator_gen.del_numer/Mshreg_opt_has_pipe.first_q_6_5765 ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<6> ) + + ); + SRL16 #( + .INIT ( 16'h0000 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].num_stages.numerator_gen.del_numer/Mshreg_opt_has_pipe.first_q_6 ( + .A0(\BU2/divide_by_zero ), + .A1(\BU2/divide_by_zero ), + .A2(\BU2/divide_by_zero ), + .A3(\BU2/divide_by_zero ), + .CLK(clk), + .D(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_dividend/twos_comp/s_i [6]), + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].num_stages.numerator_gen.del_numer/Mshreg_opt_has_pipe.first_q_6_5765 ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q_7 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].num_stages.numerator_gen.del_numer/Mshreg_opt_has_pipe.first_q_7_5764 ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<7> ) + + ); + SRL16 #( + .INIT ( 16'h0000 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].num_stages.numerator_gen.del_numer/Mshreg_opt_has_pipe.first_q_7 ( + .A0(\BU2/divide_by_zero ), + .A1(\BU2/divide_by_zero ), + .A2(\BU2/divide_by_zero ), + .A3(\BU2/divide_by_zero ), + .CLK(clk), + .D(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_dividend/twos_comp/s_i [7]), + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].num_stages.numerator_gen.del_numer/Mshreg_opt_has_pipe.first_q_7_5764 ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q_5 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].num_stages.numerator_gen.del_numer/Mshreg_opt_has_pipe.first_q_5_5763 ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<5> ) + + ); + SRL16 #( + .INIT ( 16'h0000 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].num_stages.numerator_gen.del_numer/Mshreg_opt_has_pipe.first_q_5 ( + .A0(\BU2/divide_by_zero ), + .A1(\BU2/divide_by_zero ), + .A2(\BU2/divide_by_zero ), + .A3(\BU2/divide_by_zero ), + .CLK(clk), + .D(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_dividend/twos_comp/s_i [5]), + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].num_stages.numerator_gen.del_numer/Mshreg_opt_has_pipe.first_q_5_5763 ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q_8 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].num_stages.numerator_gen.del_numer/Mshreg_opt_has_pipe.first_q_8_5762 ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<8> ) + + ); + SRL16 #( + .INIT ( 16'h0000 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].num_stages.numerator_gen.del_numer/Mshreg_opt_has_pipe.first_q_8 ( + .A0(\BU2/divide_by_zero ), + .A1(\BU2/divide_by_zero ), + .A2(\BU2/divide_by_zero ), + .A3(\BU2/divide_by_zero ), + .CLK(clk), + .D(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_dividend/twos_comp/s_i [8]), + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].num_stages.numerator_gen.del_numer/Mshreg_opt_has_pipe.first_q_8_5762 ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q_9 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].num_stages.numerator_gen.del_numer/Mshreg_opt_has_pipe.first_q_9_5761 ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<9> ) + + ); + SRL16 #( + .INIT ( 16'h0000 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].num_stages.numerator_gen.del_numer/Mshreg_opt_has_pipe.first_q_9 ( + .A0(\BU2/divide_by_zero ), + .A1(\BU2/divide_by_zero ), + .A2(\BU2/divide_by_zero ), + .A3(\BU2/divide_by_zero ), + .CLK(clk), + .D(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_dividend/twos_comp/s_i [9]), + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].num_stages.numerator_gen.del_numer/Mshreg_opt_has_pipe.first_q_9_5761 ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q_10 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].num_stages.numerator_gen.del_numer/Mshreg_opt_has_pipe.first_q_10_5760 ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<10> ) + + ); + SRL16 #( + .INIT ( 16'h0000 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].num_stages.numerator_gen.del_numer/Mshreg_opt_has_pipe.first_q_10 ( + .A0(\BU2/divide_by_zero ), + .A1(\BU2/divide_by_zero ), + .A2(\BU2/divide_by_zero ), + .A3(\BU2/divide_by_zero ), + .CLK(clk), + .D(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_dividend/twos_comp/s_i [10]), + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].num_stages.numerator_gen.del_numer/Mshreg_opt_has_pipe.first_q_10_5760 ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q_11 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].num_stages.numerator_gen.del_numer/Mshreg_opt_has_pipe.first_q_11_5759 ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<11> ) + + ); + SRL16 #( + .INIT ( 16'h0000 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].num_stages.numerator_gen.del_numer/Mshreg_opt_has_pipe.first_q_11 ( + .A0(\BU2/divide_by_zero ), + .A1(\BU2/divide_by_zero ), + .A2(\BU2/divide_by_zero ), + .A3(\BU2/divide_by_zero ), + .CLK(clk), + .D(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_dividend/twos_comp/s_i [11]), + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].num_stages.numerator_gen.del_numer/Mshreg_opt_has_pipe.first_q_11_5759 ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q_13 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].num_stages.numerator_gen.del_numer/Mshreg_opt_has_pipe.first_q_13_5758 ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<13> ) + + ); + SRL16 #( + .INIT ( 16'h0000 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].num_stages.numerator_gen.del_numer/Mshreg_opt_has_pipe.first_q_13 ( + .A0(\BU2/divide_by_zero ), + .A1(\BU2/divide_by_zero ), + .A2(\BU2/divide_by_zero ), + .A3(\BU2/divide_by_zero ), + .CLK(clk), + .D(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_dividend/twos_comp/s_i [13]), + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].num_stages.numerator_gen.del_numer/Mshreg_opt_has_pipe.first_q_13_5758 ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q_14 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].num_stages.numerator_gen.del_numer/Mshreg_opt_has_pipe.first_q_14_5757 ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<14> ) + + ); + SRL16 #( + .INIT ( 16'h0000 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].num_stages.numerator_gen.del_numer/Mshreg_opt_has_pipe.first_q_14 ( + .A0(\BU2/divide_by_zero ), + .A1(\BU2/divide_by_zero ), + .A2(\BU2/divide_by_zero ), + .A3(\BU2/divide_by_zero ), + .CLK(clk), + .D(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_dividend/twos_comp/s_i [14]), + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].num_stages.numerator_gen.del_numer/Mshreg_opt_has_pipe.first_q_14_5757 ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q_12 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].num_stages.numerator_gen.del_numer/Mshreg_opt_has_pipe.first_q_12_5756 ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<12> ) + + ); + SRL16 #( + .INIT ( 16'h0000 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].num_stages.numerator_gen.del_numer/Mshreg_opt_has_pipe.first_q_12 ( + .A0(\BU2/divide_by_zero ), + .A1(\BU2/divide_by_zero ), + .A2(\BU2/divide_by_zero ), + .A3(\BU2/divide_by_zero ), + .CLK(clk), + .D(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_dividend/twos_comp/s_i [12]), + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].num_stages.numerator_gen.del_numer/Mshreg_opt_has_pipe.first_q_12_5756 ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q_15 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].num_stages.numerator_gen.del_numer/Mshreg_opt_has_pipe.first_q_15_5755 ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<15> ) + + ); + SRL16 #( + .INIT ( 16'h0000 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].num_stages.numerator_gen.del_numer/Mshreg_opt_has_pipe.first_q_15 ( + .A0(\BU2/divide_by_zero ), + .A1(\BU2/divide_by_zero ), + .A2(\BU2/divide_by_zero ), + .A3(\BU2/divide_by_zero ), + .CLK(clk), + .D(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_dividend/twos_comp/s_i [15]), + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].num_stages.numerator_gen.del_numer/Mshreg_opt_has_pipe.first_q_15_5755 ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q_16 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].num_stages.numerator_gen.del_numer/Mshreg_opt_has_pipe.first_q_16_5754 ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<16> ) + + ); + SRL16 #( + .INIT ( 16'h0000 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].num_stages.numerator_gen.del_numer/Mshreg_opt_has_pipe.first_q_16 ( + .A0(\BU2/divide_by_zero ), + .A1(\BU2/divide_by_zero ), + .A2(\BU2/divide_by_zero ), + .A3(\BU2/divide_by_zero ), + .CLK(clk), + .D(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_dividend/twos_comp/s_i [16]), + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].num_stages.numerator_gen.del_numer/Mshreg_opt_has_pipe.first_q_16_5754 ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q_17 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].num_stages.numerator_gen.del_numer/Mshreg_opt_has_pipe.first_q_17_5753 ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<17> ) + + ); + SRL16 #( + .INIT ( 16'h0000 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].num_stages.numerator_gen.del_numer/Mshreg_opt_has_pipe.first_q_17 ( + .A0(\BU2/divide_by_zero ), + .A1(\BU2/divide_by_zero ), + .A2(\BU2/divide_by_zero ), + .A3(\BU2/divide_by_zero ), + .CLK(clk), + .D(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_dividend/twos_comp/s_i [17]), + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].num_stages.numerator_gen.del_numer/Mshreg_opt_has_pipe.first_q_17_5753 ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q_18 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].num_stages.numerator_gen.del_numer/Mshreg_opt_has_pipe.first_q_18_5752 ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<18> ) + + ); + SRL16 #( + .INIT ( 16'h0000 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].num_stages.numerator_gen.del_numer/Mshreg_opt_has_pipe.first_q_18 ( + .A0(\BU2/divide_by_zero ), + .A1(\BU2/divide_by_zero ), + .A2(\BU2/divide_by_zero ), + .A3(\BU2/divide_by_zero ), + .CLK(clk), + .D(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_dividend/twos_comp/s_i [18]), + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].num_stages.numerator_gen.del_numer/Mshreg_opt_has_pipe.first_q_18_5752 ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q_20 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].num_stages.numerator_gen.del_numer/Mshreg_opt_has_pipe.first_q_20_5751 ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<20> ) + + ); + SRL16 #( + .INIT ( 16'h0000 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].num_stages.numerator_gen.del_numer/Mshreg_opt_has_pipe.first_q_20 ( + .A0(\BU2/divide_by_zero ), + .A1(\BU2/divide_by_zero ), + .A2(\BU2/divide_by_zero ), + .A3(\BU2/divide_by_zero ), + .CLK(clk), + .D(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_dividend/twos_comp/s_i [20]), + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].num_stages.numerator_gen.del_numer/Mshreg_opt_has_pipe.first_q_20_5751 ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q_21 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].num_stages.numerator_gen.del_numer/Mshreg_opt_has_pipe.first_q_21_5750 ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<21> ) + + ); + SRL16 #( + .INIT ( 16'h0000 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].num_stages.numerator_gen.del_numer/Mshreg_opt_has_pipe.first_q_21 ( + .A0(\BU2/divide_by_zero ), + .A1(\BU2/divide_by_zero ), + .A2(\BU2/divide_by_zero ), + .A3(\BU2/divide_by_zero ), + .CLK(clk), + .D(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_dividend/twos_comp/s_i [21]), + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].num_stages.numerator_gen.del_numer/Mshreg_opt_has_pipe.first_q_21_5750 ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q_19 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].num_stages.numerator_gen.del_numer/Mshreg_opt_has_pipe.first_q_19_5749 ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<19> ) + + ); + SRL16 #( + .INIT ( 16'h0000 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].num_stages.numerator_gen.del_numer/Mshreg_opt_has_pipe.first_q_19 ( + .A0(\BU2/divide_by_zero ), + .A1(\BU2/divide_by_zero ), + .A2(\BU2/divide_by_zero ), + .A3(\BU2/divide_by_zero ), + .CLK(clk), + .D(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_dividend/twos_comp/s_i [19]), + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].num_stages.numerator_gen.del_numer/Mshreg_opt_has_pipe.first_q_19_5749 ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q_22 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].num_stages.numerator_gen.del_numer/Mshreg_opt_has_pipe.first_q_22_5748 ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<22> ) + + ); + SRL16 #( + .INIT ( 16'h0000 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].num_stages.numerator_gen.del_numer/Mshreg_opt_has_pipe.first_q_22 ( + .A0(\BU2/divide_by_zero ), + .A1(\BU2/divide_by_zero ), + .A2(\BU2/divide_by_zero ), + .A3(\BU2/divide_by_zero ), + .CLK(clk), + .D(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_dividend/twos_comp/s_i [22]), + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].num_stages.numerator_gen.del_numer/Mshreg_opt_has_pipe.first_q_22_5748 ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q_23 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].num_stages.numerator_gen.del_numer/Mshreg_opt_has_pipe.first_q_23_5747 ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<23> ) + + ); + SRL16 #( + .INIT ( 16'h0000 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].num_stages.numerator_gen.del_numer/Mshreg_opt_has_pipe.first_q_23 ( + .A0(\BU2/divide_by_zero ), + .A1(\BU2/divide_by_zero ), + .A2(\BU2/divide_by_zero ), + .A3(\BU2/divide_by_zero ), + .CLK(clk), + .D(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_dividend/twos_comp/s_i [23]), + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].num_stages.numerator_gen.del_numer/Mshreg_opt_has_pipe.first_q_23_5747 ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q_24 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].num_stages.numerator_gen.del_numer/Mshreg_opt_has_pipe.first_q_24_5746 ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<24> ) + + ); + SRL16 #( + .INIT ( 16'h0000 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].num_stages.numerator_gen.del_numer/Mshreg_opt_has_pipe.first_q_24 ( + .A0(\BU2/divide_by_zero ), + .A1(\BU2/divide_by_zero ), + .A2(\BU2/divide_by_zero ), + .A3(\BU2/divide_by_zero ), + .CLK(clk), + .D(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_dividend/twos_comp/s_i [24]), + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].num_stages.numerator_gen.del_numer/Mshreg_opt_has_pipe.first_q_24_5746 ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q_25 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].num_stages.numerator_gen.del_numer/Mshreg_opt_has_pipe.first_q_25_5745 ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<25> ) + + ); + SRL16 #( + .INIT ( 16'h0000 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].num_stages.numerator_gen.del_numer/Mshreg_opt_has_pipe.first_q_25 ( + .A0(\BU2/divide_by_zero ), + .A1(\BU2/divide_by_zero ), + .A2(\BU2/divide_by_zero ), + .A3(\BU2/divide_by_zero ), + .CLK(clk), + .D(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_dividend/twos_comp/s_i [25]), + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].num_stages.numerator_gen.del_numer/Mshreg_opt_has_pipe.first_q_25_5745 ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q_26 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].num_stages.numerator_gen.del_numer/Mshreg_opt_has_pipe.first_q_26_5744 ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<26> ) + + ); + SRL16 #( + .INIT ( 16'h0000 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].num_stages.numerator_gen.del_numer/Mshreg_opt_has_pipe.first_q_26 ( + .A0(\BU2/divide_by_zero ), + .A1(\BU2/divide_by_zero ), + .A2(\BU2/divide_by_zero ), + .A3(\BU2/divide_by_zero ), + .CLK(clk), + .D(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_dividend/twos_comp/s_i [26]), + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].num_stages.numerator_gen.del_numer/Mshreg_opt_has_pipe.first_q_26_5744 ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q_27 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].num_stages.numerator_gen.del_numer/Mshreg_opt_has_pipe.first_q_27_5743 ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<27> ) + + ); + SRL16 #( + .INIT ( 16'h0000 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].num_stages.numerator_gen.del_numer/Mshreg_opt_has_pipe.first_q_27 ( + .A0(\BU2/divide_by_zero ), + .A1(\BU2/divide_by_zero ), + .A2(\BU2/divide_by_zero ), + .A3(\BU2/divide_by_zero ), + .CLK(clk), + .D(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_dividend/twos_comp/s_i [27]), + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].num_stages.numerator_gen.del_numer/Mshreg_opt_has_pipe.first_q_27_5743 ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q_28 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].num_stages.numerator_gen.del_numer/Mshreg_opt_has_pipe.first_q_28_5742 ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<28> ) + + ); + SRL16 #( + .INIT ( 16'h0000 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].num_stages.numerator_gen.del_numer/Mshreg_opt_has_pipe.first_q_28 ( + .A0(\BU2/divide_by_zero ), + .A1(\BU2/divide_by_zero ), + .A2(\BU2/divide_by_zero ), + .A3(\BU2/divide_by_zero ), + .CLK(clk), + .D(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_dividend/twos_comp/s_i [28]), + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].num_stages.numerator_gen.del_numer/Mshreg_opt_has_pipe.first_q_28_5742 ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q_29 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].num_stages.numerator_gen.del_numer/Mshreg_opt_has_pipe.first_q_29_5741 ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<29> ) + + ); + SRL16 #( + .INIT ( 16'h0000 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].num_stages.numerator_gen.del_numer/Mshreg_opt_has_pipe.first_q_29 ( + .A0(\BU2/divide_by_zero ), + .A1(\BU2/divide_by_zero ), + .A2(\BU2/divide_by_zero ), + .A3(\BU2/divide_by_zero ), + .CLK(clk), + .D(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_dividend/twos_comp/s_i [29]), + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].num_stages.numerator_gen.del_numer/Mshreg_opt_has_pipe.first_q_29_5741 ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q_30 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].num_stages.numerator_gen.del_numer/Mshreg_opt_has_pipe.first_q_30_5740 ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<30> ) + + ); + SRL16 #( + .INIT ( 16'h0000 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].num_stages.numerator_gen.del_numer/Mshreg_opt_has_pipe.first_q_30 ( + .A0(\BU2/divide_by_zero ), + .A1(\BU2/divide_by_zero ), + .A2(\BU2/divide_by_zero ), + .A3(\BU2/divide_by_zero ), + .CLK(clk), + .D(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_dividend/twos_comp/s_i [30]), + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].num_stages.numerator_gen.del_numer/Mshreg_opt_has_pipe.first_q_30_5740 ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q_31 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].num_stages.numerator_gen.del_numer/Mshreg_opt_has_pipe.first_q_31_5739 ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<31> ) + + ); + SRL16 #( + .INIT ( 16'h0000 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].num_stages.numerator_gen.del_numer/Mshreg_opt_has_pipe.first_q_31 ( + .A0(\BU2/divide_by_zero ), + .A1(\BU2/divide_by_zero ), + .A2(\BU2/divide_by_zero ), + .A3(\BU2/divide_by_zero ), + .CLK(clk), + .D(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_dividend/twos_comp/s_i [31]), + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].num_stages.numerator_gen.del_numer/Mshreg_opt_has_pipe.first_q_31_5739 ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sign_pipeline.sign_pipe/opt_has_pipe.pipe_32_0 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sign_pipeline.sign_pipe/Mshreg_opt_has_pipe.pipe_32_0_1_5738 ), + .Q(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sign_pipeline.sign_pipe/opt_has_pipe.pipe_32 [0]) + ); + SRL16 #( + .INIT ( 16'h0000 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sign_pipeline.sign_pipe/Mshreg_opt_has_pipe.pipe_32_0_1 ( + .A0(NlwRenamedSig_OI_rfd), + .A1(\BU2/divide_by_zero ), + .A2(NlwRenamedSig_OI_rfd), + .A3(NlwRenamedSig_OI_rfd), + .CLK(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sign_pipeline.sign_pipe/Mshreg_opt_has_pipe.pipe_32_0_0_5737 ), + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sign_pipeline.sign_pipe/Mshreg_opt_has_pipe.pipe_32_0_1_5738 ) + ); + SRLC16 #( + .INIT ( 16'h0000 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sign_pipeline.sign_pipe/Mshreg_opt_has_pipe.pipe_32_0_0 ( + .A0(NlwRenamedSig_OI_rfd), + .A1(NlwRenamedSig_OI_rfd), + .A2(NlwRenamedSig_OI_rfd), + .A3(NlwRenamedSig_OI_rfd), + .CLK(clk), + .D(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sign_pipeline.sign_pipe/opt_has_pipe.first_q [0]), + .Q +(\NLW_BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sign_pipeline.sign_pipe/Mshreg_opt_has_pipe.pipe_32_0_0_Q_UNCONNECTED ) +, + .Q15 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sign_pipeline.sign_pipe/Mshreg_opt_has_pipe.pipe_32_0_0_5737 ) + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sign_pipeline.sign_pipe/opt_has_pipe.pipe_32_1 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sign_pipeline.sign_pipe/Mshreg_opt_has_pipe.pipe_32_1_1_5736 ), + .Q(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sign_pipeline.sign_pipe/opt_has_pipe.pipe_32 [1]) + ); + SRL16 #( + .INIT ( 16'h0000 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sign_pipeline.sign_pipe/Mshreg_opt_has_pipe.pipe_32_1_1 ( + .A0(NlwRenamedSig_OI_rfd), + .A1(\BU2/divide_by_zero ), + .A2(NlwRenamedSig_OI_rfd), + .A3(NlwRenamedSig_OI_rfd), + .CLK(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sign_pipeline.sign_pipe/Mshreg_opt_has_pipe.pipe_32_1_0_5735 ), + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sign_pipeline.sign_pipe/Mshreg_opt_has_pipe.pipe_32_1_1_5736 ) + ); + SRLC16 #( + .INIT ( 16'h0000 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sign_pipeline.sign_pipe/Mshreg_opt_has_pipe.pipe_32_1_0 ( + .A0(NlwRenamedSig_OI_rfd), + .A1(NlwRenamedSig_OI_rfd), + .A2(NlwRenamedSig_OI_rfd), + .A3(NlwRenamedSig_OI_rfd), + .CLK(clk), + .D(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sign_pipeline.sign_pipe/opt_has_pipe.first_q [1]), + .Q +(\NLW_BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sign_pipeline.sign_pipe/Mshreg_opt_has_pipe.pipe_32_1_0_Q_UNCONNECTED ) +, + .Q15 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sign_pipeline.sign_pipe/Mshreg_opt_has_pipe.pipe_32_1_0_5735 ) + ); + INV + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<9>1_INV_0 ( + .I +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<9> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<9> ) + + ); + INV + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<8>1_INV_0 ( + .I +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<8> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<8> ) + + ); + INV + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<7>1_INV_0 ( + .I +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<7> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<7> ) + + ); + INV + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<6>1_INV_0 ( + .I +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<6> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<6> ) + + ); + INV + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<5>1_INV_0 ( + .I +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<5> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<5> ) + + ); + INV + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<4>1_INV_0 ( + .I +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<4> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<4> ) + + ); + INV + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<3>1_INV_0 ( + .I +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<3> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<3> ) + + ); + INV + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<2>1_INV_0 ( + .I +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<2> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<2> ) + + ); + INV + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<23>1_INV_0 ( + .I +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<23> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<23> ) + + ); + INV + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<22>1_INV_0 ( + .I +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<22> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<22> ) + + ); + INV + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<21>1_INV_0 ( + .I +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<21> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<21> ) + + ); + INV + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<20>1_INV_0 ( + .I +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<20> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<20> ) + + ); + INV + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<1>1_INV_0 ( + .I +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<1> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<1> ) + + ); + INV + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<19>1_INV_0 ( + .I +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<19> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<19> ) + + ); + INV + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<18>1_INV_0 ( + .I +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<18> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<18> ) + + ); + INV + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<17>1_INV_0 ( + .I +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<17> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<17> ) + + ); + INV + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<16>1_INV_0 ( + .I +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<16> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<16> ) + + ); + INV + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<15>1_INV_0 ( + .I +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<15> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<15> ) + + ); + INV + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<14>1_INV_0 ( + .I +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<14> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<14> ) + + ); + INV + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<13>1_INV_0 ( + .I +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<13> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<13> ) + + ); + INV + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<12>1_INV_0 ( + .I +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<12> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<12> ) + + ); + INV + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<11>1_INV_0 ( + .I +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<11> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<11> ) + + ); + INV + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<10>1_INV_0 ( + .I +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<10> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<10> ) + + ); + INV \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/qpi<31>1_INV_0 ( + .I +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<30> ) +, + .O(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/qpi [31]) + ); + INV \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/qpi<30>1_INV_0 ( + .I +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<29> ) +, + .O(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/qpi [30]) + ); + INV \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/qpi<29>1_INV_0 ( + .I +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<28> ) +, + .O(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/qpi [29]) + ); + INV \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/qpi<28>1_INV_0 ( + .I +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<27> ) +, + .O(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/qpi [28]) + ); + INV \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/qpi<27>1_INV_0 ( + .I +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<26> ) +, + .O(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/qpi [27]) + ); + INV \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/qpi<26>1_INV_0 ( + .I +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<25> ) +, + .O(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/qpi [26]) + ); + INV \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/qpi<25>1_INV_0 ( + .I +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<24> ) +, + .O(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/qpi [25]) + ); + INV \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/qpi<24>1_INV_0 ( + .I +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<23> ) +, + .O(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/qpi [24]) + ); + INV \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/qpi<23>1_INV_0 ( + .I +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<22> ) +, + .O(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/qpi [23]) + ); + INV \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/qpi<22>1_INV_0 ( + .I +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<21> ) +, + .O(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/qpi [22]) + ); + INV \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/qpi<21>1_INV_0 ( + .I +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<20> ) +, + .O(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/qpi [21]) + ); + INV \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/qpi<20>1_INV_0 ( + .I +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<19> ) +, + .O(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/qpi [20]) + ); + INV \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/qpi<19>1_INV_0 ( + .I +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<18> ) +, + .O(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/qpi [19]) + ); + INV \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/qpi<18>1_INV_0 ( + .I +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<17> ) +, + .O(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/qpi [18]) + ); + INV \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/qpi<17>1_INV_0 ( + .I +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<16> ) +, + .O(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/qpi [17]) + ); + INV \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/qpi<16>1_INV_0 ( + .I +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<15> ) +, + .O(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/qpi [16]) + ); + INV \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/qpi<15>1_INV_0 ( + .I +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<14> ) +, + .O(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/qpi [15]) + ); + INV \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/qpi<14>1_INV_0 ( + .I +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<13> ) +, + .O(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/qpi [14]) + ); + INV \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/qpi<13>1_INV_0 ( + .I +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<12> ) +, + .O(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/qpi [13]) + ); + INV \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/qpi<12>1_INV_0 ( + .I +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<11> ) +, + .O(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/qpi [12]) + ); + INV \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/qpi<11>1_INV_0 ( + .I +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<10> ) +, + .O(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/qpi [11]) + ); + INV \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/qpi<10>1_INV_0 ( + .I +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<9> ) +, + .O(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/qpi [10]) + ); + INV \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/qpi<9>1_INV_0 ( + .I +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<8> ) +, + .O(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/qpi [9]) + ); + INV \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/qpi<8>1_INV_0 ( + .I +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<7> ) +, + .O(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/qpi [8]) + ); + INV \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/qpi<7>1_INV_0 ( + .I +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<6> ) +, + .O(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/qpi [7]) + ); + INV \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/qpi<6>1_INV_0 ( + .I +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<5> ) +, + .O(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/qpi [6]) + ); + INV \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/qpi<5>1_INV_0 ( + .I +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<4> ) +, + .O(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/qpi [5]) + ); + INV \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/qpi<4>1_INV_0 ( + .I +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<3> ) +, + .O(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/qpi [4]) + ); + INV \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/qpi<3>1_INV_0 ( + .I +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<2> ) +, + .O(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/qpi [3]) + ); + INV \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/qpi<2>1_INV_0 ( + .I +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<1> ) +, + .O(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/qpi [2]) + ); + INV \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/qpi<1>1_INV_0 ( + .I +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<0> ) +, + .O(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/qpi [1]) + ); + INV + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].adder_gen.reg_req.adsu_mod/inv_o1_INV_0 ( + .I +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/inv_o [30]) + ); + INV + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].adder_gen.reg_req.adsu_mod/inv_o1_INV_0 ( + .I +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/inv_o [29]) + ); + INV + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].adder_gen.reg_req.adsu_mod/inv_o1_INV_0 ( + .I +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/inv_o [28]) + ); + INV + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].adder_gen.reg_req.adsu_mod/inv_o1_INV_0 ( + .I +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/inv_o [27]) + ); + INV + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].adder_gen.reg_req.adsu_mod/inv_o1_INV_0 ( + .I +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/inv_o [26]) + ); + INV + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].adder_gen.reg_req.adsu_mod/inv_o1_INV_0 ( + .I +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/inv_o [25]) + ); + INV + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].adder_gen.reg_req.adsu_mod/inv_o1_INV_0 ( + .I +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/inv_o [24]) + ); + INV + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].adder_gen.reg_req.adsu_mod/inv_o1_INV_0 ( + .I +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/inv_o [23]) + ); + INV + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].adder_gen.reg_req.adsu_mod/inv_o1_INV_0 ( + .I +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/inv_o [22]) + ); + INV + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].adder_gen.reg_req.adsu_mod/inv_o1_INV_0 ( + .I +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/inv_o [21]) + ); + INV + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].adder_gen.reg_req.adsu_mod/inv_o1_INV_0 ( + .I +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/inv_o [20]) + ); + INV + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].adder_gen.reg_req.adsu_mod/inv_o1_INV_0 ( + .I +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/inv_o [19]) + ); + INV + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].adder_gen.reg_req.adsu_mod/inv_o1_INV_0 ( + .I +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/inv_o [18]) + ); + INV + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].adder_gen.reg_req.adsu_mod/inv_o1_INV_0 ( + .I +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/inv_o [17]) + ); + INV + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].adder_gen.reg_req.adsu_mod/inv_o1_INV_0 ( + .I +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/inv_o [16]) + ); + INV + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].adder_gen.reg_req.adsu_mod/inv_o1_INV_0 ( + .I +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/inv_o [15]) + ); + INV + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].adder_gen.reg_req.adsu_mod/inv_o1_INV_0 ( + .I +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/inv_o [14]) + ); + INV + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].adder_gen.reg_req.adsu_mod/inv_o1_INV_0 ( + .I +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/inv_o [13]) + ); + INV + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].adder_gen.reg_req.adsu_mod/inv_o1_INV_0 ( + .I +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/inv_o [12]) + ); + INV + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].adder_gen.reg_req.adsu_mod/inv_o1_INV_0 ( + .I +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/inv_o [11]) + ); + INV + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].adder_gen.reg_req.adsu_mod/inv_o1_INV_0 ( + .I +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/inv_o [10]) + ); + INV + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].adder_gen.reg_req.adsu_mod/inv_o1_INV_0 ( + .I +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/inv_o [9]) + ); + INV + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].adder_gen.reg_req.adsu_mod/inv_o1_INV_0 ( + .I +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/inv_o [8]) + ); + INV + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].adder_gen.reg_req.adsu_mod/inv_o1_INV_0 ( + .I +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/inv_o [7]) + ); + INV + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].adder_gen.reg_req.adsu_mod/inv_o1_INV_0 ( + .I +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/inv_o [6]) + ); + INV + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].adder_gen.reg_req.adsu_mod/inv_o1_INV_0 ( + .I +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/inv_o [5]) + ); + INV + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].adder_gen.reg_req.adsu_mod/inv_o1_INV_0 ( + .I +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/inv_o [4]) + ); + INV + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].adder_gen.reg_req.adsu_mod/inv_o1_INV_0 ( + .I +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/inv_o [3]) + ); + INV + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].adder_gen.reg_req.adsu_mod/inv_o1_INV_0 ( + .I +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24>_0 ) +, + .O(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/inv_o [2]) + ); + INV + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].adder_gen.reg_req.adsu_mod/inv_o1_INV_0 ( + .I +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24>_0 ) +, + .O(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/inv_o [1]) + ); + INV + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].adder_gen.reg_req.adsu_mod/inv_o1_INV_0 ( + .I +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24>_0 ) +, + .O(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/inv_o [0]) + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_24_1 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<24> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24>_0 ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sign_pipeline.sign_pipe/opt_has_pipe.pipe_33_0_4 ( + .C(clk), + .D(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sign_pipeline.sign_pipe/opt_has_pipe.pipe_32 [0]), + .Q(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sign_pipeline.sign_pipe/opt_has_pipe.pipe_33_0_4_5734 ) + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sign_pipeline.sign_pipe/opt_has_pipe.pipe_33_1_4 ( + .C(clk), + .D(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sign_pipeline.sign_pipe/opt_has_pipe.pipe_32 [1]), + .Q(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sign_pipeline.sign_pipe/opt_has_pipe.pipe_33_1_4_5730 ) + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_24_1 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<24> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24>_0 ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sign_pipeline.sign_pipe/opt_has_pipe.pipe_33_1_3 ( + .C(clk), + .D(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sign_pipeline.sign_pipe/opt_has_pipe.pipe_32 [1]), + .Q(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sign_pipeline.sign_pipe/opt_has_pipe.pipe_33_1_3_5729 ) + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_24_1 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<24> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24>_0 ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sign_pipeline.sign_pipe/opt_has_pipe.pipe_33_0_3 ( + .C(clk), + .D(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sign_pipeline.sign_pipe/opt_has_pipe.pipe_32 [0]), + .Q(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sign_pipeline.sign_pipe/opt_has_pipe.pipe_33_0_3_5733 ) + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_24_1 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<24> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24>_0 ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sign_pipeline.sign_pipe/opt_has_pipe.pipe_33_0_2 ( + .C(clk), + .D(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sign_pipeline.sign_pipe/opt_has_pipe.pipe_32 [0]), + .Q(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sign_pipeline.sign_pipe/opt_has_pipe.pipe_33_0_2_5731 ) + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sign_pipeline.sign_pipe/opt_has_pipe.pipe_33_1_2 ( + .C(clk), + .D(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sign_pipeline.sign_pipe/opt_has_pipe.pipe_32 [1]), + .Q(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sign_pipeline.sign_pipe/opt_has_pipe.pipe_33_1_2_5732 ) + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sign_pipeline.sign_pipe/opt_has_pipe.pipe_33_0_1 ( + .C(clk), + .D(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sign_pipeline.sign_pipe/opt_has_pipe.pipe_32 [0]), + .Q(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sign_pipeline.sign_pipe/opt_has_pipe.pipe_33_0_1_5724 ) + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sign_pipeline.sign_pipe/opt_has_pipe.pipe_33_1_1 ( + .C(clk), + .D(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sign_pipeline.sign_pipe/opt_has_pipe.pipe_32 [1]), + .Q(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sign_pipeline.sign_pipe/opt_has_pipe.pipe_33_1_1_5725 ) + ); + LUT1 #( + .INIT ( 2'h2 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.remd_not_fract.cmp_remd/twos_comp/Madd_s_i_cy<0>_rt ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/remd_output.adsu_sel2/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q [0]) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.remd_not_fract.cmp_remd/twos_comp/Madd_s_i_cy<0>_rt_5722 ) + + ); + LUT1 #( + .INIT ( 2'h2 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.cmp_quot/twos_comp/Madd_s_i_cy<0>_rt ( + .I0(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/reg_quot_out.reg_quot/opt_has_pipe.first_q [0]), + .O(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.cmp_quot/twos_comp/Madd_s_i_cy<0>_rt_5650 ) + ); + LUT1 #( + .INIT ( 2'h2 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_divisor/twos_comp/Madd_s_i_cy<0>_rt ( + .I0(divisor_3[0]), + .O(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_divisor/twos_comp/Madd_s_i_cy<0>_rt_281 ) + ); + LUT1 #( + .INIT ( 2'h2 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_dividend/twos_comp/Madd_s_i_cy<0>_rt ( + .I0(dividend_2[0]), + .O(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_dividend/twos_comp/Madd_s_i_cy<0>_rt_211 ) + ); + LUT3 #( + .INIT ( 8'h96 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.cmp_quot/twos_comp/Mmux_simp_addp_a251 ( + .I0(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/reg_quot_out.reg_quot/opt_has_pipe.first_q [31]) +, + .I1(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sign_pipeline.sign_pipe/opt_has_pipe.pipe_33 [0]), + .I2(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sign_pipeline.sign_pipe/opt_has_pipe.pipe_33 [1]), + .O(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.cmp_quot/twos_comp/simp_addp_a [31]) + ); + LUT3 #( + .INIT ( 8'h96 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.cmp_quot/twos_comp/Mmux_simp_addp_a241 ( + .I0(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/reg_quot_out.reg_quot/opt_has_pipe.first_q [30]) +, + .I1(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sign_pipeline.sign_pipe/opt_has_pipe.pipe_33 [0]), + .I2(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sign_pipeline.sign_pipe/opt_has_pipe.pipe_33 [1]), + .O(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.cmp_quot/twos_comp/simp_addp_a [30]) + ); + LUT3 #( + .INIT ( 8'h96 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.cmp_quot/twos_comp/Mmux_simp_addp_a221 ( + .I0(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/reg_quot_out.reg_quot/opt_has_pipe.first_q [29]) +, + .I1(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sign_pipeline.sign_pipe/opt_has_pipe.pipe_33 [0]), + .I2(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sign_pipeline.sign_pipe/opt_has_pipe.pipe_33 [1]), + .O(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.cmp_quot/twos_comp/simp_addp_a [29]) + ); + LUT3 #( + .INIT ( 8'h96 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.cmp_quot/twos_comp/Mmux_simp_addp_a211 ( + .I0(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/reg_quot_out.reg_quot/opt_has_pipe.first_q [28]) +, + .I1(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sign_pipeline.sign_pipe/opt_has_pipe.pipe_33 [0]), + .I2(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sign_pipeline.sign_pipe/opt_has_pipe.pipe_33 [1]), + .O(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.cmp_quot/twos_comp/simp_addp_a [28]) + ); + LUT3 #( + .INIT ( 8'h96 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.cmp_quot/twos_comp/Mmux_simp_addp_a201 ( + .I0(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/reg_quot_out.reg_quot/opt_has_pipe.first_q [27]) +, + .I1(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sign_pipeline.sign_pipe/opt_has_pipe.pipe_33 [0]), + .I2(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sign_pipeline.sign_pipe/opt_has_pipe.pipe_33 [1]), + .O(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.cmp_quot/twos_comp/simp_addp_a [27]) + ); + LUT3 #( + .INIT ( 8'h96 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.cmp_quot/twos_comp/Mmux_simp_addp_a191 ( + .I0(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/reg_quot_out.reg_quot/opt_has_pipe.first_q [26]) +, + .I1(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sign_pipeline.sign_pipe/opt_has_pipe.pipe_33 [0]), + .I2(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sign_pipeline.sign_pipe/opt_has_pipe.pipe_33 [1]), + .O(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.cmp_quot/twos_comp/simp_addp_a [26]) + ); + LUT3 #( + .INIT ( 8'h96 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.cmp_quot/twos_comp/Mmux_simp_addp_a181 ( + .I0(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/reg_quot_out.reg_quot/opt_has_pipe.first_q [25]) +, + .I1(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sign_pipeline.sign_pipe/opt_has_pipe.pipe_33 [0]), + .I2(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sign_pipeline.sign_pipe/opt_has_pipe.pipe_33 [1]), + .O(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.cmp_quot/twos_comp/simp_addp_a [25]) + ); + LUT3 #( + .INIT ( 8'h96 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.cmp_quot/twos_comp/Mmux_simp_addp_a171 ( + .I0(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/reg_quot_out.reg_quot/opt_has_pipe.first_q [24]) +, + .I1(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sign_pipeline.sign_pipe/opt_has_pipe.pipe_33 [0]), + .I2(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sign_pipeline.sign_pipe/opt_has_pipe.pipe_33 [1]), + .O(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.cmp_quot/twos_comp/simp_addp_a [24]) + ); + LUT3 #( + .INIT ( 8'h96 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.cmp_quot/twos_comp/Mmux_simp_addp_a161 ( + .I0(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/reg_quot_out.reg_quot/opt_has_pipe.first_q [23]) +, + .I1(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sign_pipeline.sign_pipe/opt_has_pipe.pipe_33 [0]), + .I2(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sign_pipeline.sign_pipe/opt_has_pipe.pipe_33 [1]), + .O(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.cmp_quot/twos_comp/simp_addp_a [23]) + ); + LUT3 #( + .INIT ( 8'h96 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.cmp_quot/twos_comp/Mmux_simp_addp_a151 ( + .I0(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/reg_quot_out.reg_quot/opt_has_pipe.first_q [22]) +, + .I1(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sign_pipeline.sign_pipe/opt_has_pipe.pipe_33 [0]), + .I2(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sign_pipeline.sign_pipe/opt_has_pipe.pipe_33 [1]), + .O(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.cmp_quot/twos_comp/simp_addp_a [22]) + ); + LUT3 #( + .INIT ( 8'h96 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.cmp_quot/twos_comp/Mmux_simp_addp_a141 ( + .I0(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/reg_quot_out.reg_quot/opt_has_pipe.first_q [21]) +, + .I1(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sign_pipeline.sign_pipe/opt_has_pipe.pipe_33 [0]), + .I2(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sign_pipeline.sign_pipe/opt_has_pipe.pipe_33 [1]), + .O(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.cmp_quot/twos_comp/simp_addp_a [21]) + ); + LUT3 #( + .INIT ( 8'h96 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.cmp_quot/twos_comp/Mmux_simp_addp_a131 ( + .I0(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/reg_quot_out.reg_quot/opt_has_pipe.first_q [20]) +, + .I1(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sign_pipeline.sign_pipe/opt_has_pipe.pipe_33 [0]), + .I2(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sign_pipeline.sign_pipe/opt_has_pipe.pipe_33 [1]), + .O(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.cmp_quot/twos_comp/simp_addp_a [20]) + ); + LUT3 #( + .INIT ( 8'h96 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.cmp_quot/twos_comp/Mmux_simp_addp_a111 ( + .I0(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/reg_quot_out.reg_quot/opt_has_pipe.first_q [19]) +, + .I1(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sign_pipeline.sign_pipe/opt_has_pipe.pipe_33 [0]), + .I2(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sign_pipeline.sign_pipe/opt_has_pipe.pipe_33 [1]), + .O(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.cmp_quot/twos_comp/simp_addp_a [19]) + ); + LUT3 #( + .INIT ( 8'h96 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.cmp_quot/twos_comp/Mmux_simp_addp_a101 ( + .I0(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/reg_quot_out.reg_quot/opt_has_pipe.first_q [18]) +, + .I1(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sign_pipeline.sign_pipe/opt_has_pipe.pipe_33 [0]), + .I2(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sign_pipeline.sign_pipe/opt_has_pipe.pipe_33 [1]), + .O(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.cmp_quot/twos_comp/simp_addp_a [18]) + ); + LUT3 #( + .INIT ( 8'h96 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.cmp_quot/twos_comp/Mmux_simp_addp_a91 ( + .I0(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/reg_quot_out.reg_quot/opt_has_pipe.first_q [17]) +, + .I1(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sign_pipeline.sign_pipe/opt_has_pipe.pipe_33 [0]), + .I2(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sign_pipeline.sign_pipe/opt_has_pipe.pipe_33 [1]), + .O(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.cmp_quot/twos_comp/simp_addp_a [17]) + ); + LUT3 #( + .INIT ( 8'h96 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.cmp_quot/twos_comp/Mmux_simp_addp_a81 ( + .I0(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/reg_quot_out.reg_quot/opt_has_pipe.first_q [16]) +, + .I1(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sign_pipeline.sign_pipe/opt_has_pipe.pipe_33 [0]), + .I2(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sign_pipeline.sign_pipe/opt_has_pipe.pipe_33 [1]), + .O(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.cmp_quot/twos_comp/simp_addp_a [16]) + ); + LUT3 #( + .INIT ( 8'h96 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.cmp_quot/twos_comp/Mmux_simp_addp_a71 ( + .I0(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/reg_quot_out.reg_quot/opt_has_pipe.first_q [15]) +, + .I1(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sign_pipeline.sign_pipe/opt_has_pipe.pipe_33 [0]), + .I2(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sign_pipeline.sign_pipe/opt_has_pipe.pipe_33 [1]), + .O(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.cmp_quot/twos_comp/simp_addp_a [15]) + ); + LUT3 #( + .INIT ( 8'h96 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.cmp_quot/twos_comp/Mmux_simp_addp_a61 ( + .I0(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/reg_quot_out.reg_quot/opt_has_pipe.first_q [14]) +, + .I1(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sign_pipeline.sign_pipe/opt_has_pipe.pipe_33 [0]), + .I2(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sign_pipeline.sign_pipe/opt_has_pipe.pipe_33 [1]), + .O(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.cmp_quot/twos_comp/simp_addp_a [14]) + ); + LUT3 #( + .INIT ( 8'h96 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.cmp_quot/twos_comp/Mmux_simp_addp_a51 ( + .I0(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/reg_quot_out.reg_quot/opt_has_pipe.first_q [13]) +, + .I1(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sign_pipeline.sign_pipe/opt_has_pipe.pipe_33_1_4_5730 ), + .I2(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sign_pipeline.sign_pipe/opt_has_pipe.pipe_33 [0]), + .O(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.cmp_quot/twos_comp/simp_addp_a [13]) + ); + LUT3 #( + .INIT ( 8'h96 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.cmp_quot/twos_comp/Mmux_simp_addp_a41 ( + .I0(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/reg_quot_out.reg_quot/opt_has_pipe.first_q [12]) +, + .I1(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sign_pipeline.sign_pipe/opt_has_pipe.pipe_33_1_4_5730 ), + .I2(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sign_pipeline.sign_pipe/opt_has_pipe.pipe_33 [0]), + .O(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.cmp_quot/twos_comp/simp_addp_a [12]) + ); + LUT3 #( + .INIT ( 8'h96 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.cmp_quot/twos_comp/Mmux_simp_addp_a35 ( + .I0(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/reg_quot_out.reg_quot/opt_has_pipe.first_q [11]) +, + .I1(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sign_pipeline.sign_pipe/opt_has_pipe.pipe_33_0_4_5734 ), + .I2(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sign_pipeline.sign_pipe/opt_has_pipe.pipe_33_1_4_5730 ), + .O(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.cmp_quot/twos_comp/simp_addp_a [11]) + ); + LUT3 #( + .INIT ( 8'h96 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.cmp_quot/twos_comp/Mmux_simp_addp_a26 ( + .I0(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/reg_quot_out.reg_quot/opt_has_pipe.first_q [10]) +, + .I1(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sign_pipeline.sign_pipe/opt_has_pipe.pipe_33_0_4_5734 ), + .I2(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sign_pipeline.sign_pipe/opt_has_pipe.pipe_33_1_4_5730 ), + .O(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.cmp_quot/twos_comp/simp_addp_a [10]) + ); + LUT3 #( + .INIT ( 8'h96 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.cmp_quot/twos_comp/Mmux_simp_addp_a341 ( + .I0(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/reg_quot_out.reg_quot/opt_has_pipe.first_q [9]), + .I1(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sign_pipeline.sign_pipe/opt_has_pipe.pipe_33_0_3_5733 ), + .I2(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sign_pipeline.sign_pipe/opt_has_pipe.pipe_33_1_3_5729 ), + .O(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.cmp_quot/twos_comp/simp_addp_a [9]) + ); + LUT3 #( + .INIT ( 8'h96 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.cmp_quot/twos_comp/Mmux_simp_addp_a331 ( + .I0(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/reg_quot_out.reg_quot/opt_has_pipe.first_q [8]), + .I1(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sign_pipeline.sign_pipe/opt_has_pipe.pipe_33_0_3_5733 ), + .I2(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sign_pipeline.sign_pipe/opt_has_pipe.pipe_33_1_3_5729 ), + .O(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.cmp_quot/twos_comp/simp_addp_a [8]) + ); + LUT3 #( + .INIT ( 8'h96 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.cmp_quot/twos_comp/Mmux_simp_addp_a321 ( + .I0(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/reg_quot_out.reg_quot/opt_has_pipe.first_q [7]), + .I1(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sign_pipeline.sign_pipe/opt_has_pipe.pipe_33_0_3_5733 ), + .I2(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sign_pipeline.sign_pipe/opt_has_pipe.pipe_33_1_3_5729 ), + .O(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.cmp_quot/twos_comp/simp_addp_a [7]) + ); + LUT3 #( + .INIT ( 8'h96 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.cmp_quot/twos_comp/Mmux_simp_addp_a311 ( + .I0(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/reg_quot_out.reg_quot/opt_has_pipe.first_q [6]), + .I1(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sign_pipeline.sign_pipe/opt_has_pipe.pipe_33_0_3_5733 ), + .I2(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sign_pipeline.sign_pipe/opt_has_pipe.pipe_33_1_3_5729 ), + .O(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.cmp_quot/twos_comp/simp_addp_a [6]) + ); + LUT3 #( + .INIT ( 8'h96 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.cmp_quot/twos_comp/Mmux_simp_addp_a301 ( + .I0(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/reg_quot_out.reg_quot/opt_has_pipe.first_q [5]), + .I1(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sign_pipeline.sign_pipe/opt_has_pipe.pipe_33_0_2_5731 ), + .I2(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sign_pipeline.sign_pipe/opt_has_pipe.pipe_33_1_2_5732 ), + .O(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.cmp_quot/twos_comp/simp_addp_a [5]) + ); + LUT3 #( + .INIT ( 8'h96 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.cmp_quot/twos_comp/Mmux_simp_addp_a291 ( + .I0(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/reg_quot_out.reg_quot/opt_has_pipe.first_q [4]), + .I1(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sign_pipeline.sign_pipe/opt_has_pipe.pipe_33_0_2_5731 ), + .I2(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sign_pipeline.sign_pipe/opt_has_pipe.pipe_33_1_2_5732 ), + .O(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.cmp_quot/twos_comp/simp_addp_a [4]) + ); + LUT3 #( + .INIT ( 8'h96 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.cmp_quot/twos_comp/Mmux_simp_addp_a281 ( + .I0(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/reg_quot_out.reg_quot/opt_has_pipe.first_q [3]), + .I1(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sign_pipeline.sign_pipe/opt_has_pipe.pipe_33_0_2_5731 ), + .I2(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sign_pipeline.sign_pipe/opt_has_pipe.pipe_33_1_2_5732 ), + .O(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.cmp_quot/twos_comp/simp_addp_a [3]) + ); + LUT3 #( + .INIT ( 8'h96 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.cmp_quot/twos_comp/Mmux_simp_addp_a231 ( + .I0(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/reg_quot_out.reg_quot/opt_has_pipe.first_q [2]), + .I1(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sign_pipeline.sign_pipe/opt_has_pipe.pipe_33_0_2_5731 ), + .I2(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sign_pipeline.sign_pipe/opt_has_pipe.pipe_33_1_2_5732 ), + .O(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.cmp_quot/twos_comp/simp_addp_a [2]) + ); + LUT3 #( + .INIT ( 8'h96 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.cmp_quot/twos_comp/Mmux_simp_addp_a121 ( + .I0(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/reg_quot_out.reg_quot/opt_has_pipe.first_q [1]), + .I1(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sign_pipeline.sign_pipe/opt_has_pipe.pipe_33_0_2_5731 ), + .I2(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sign_pipeline.sign_pipe/opt_has_pipe.pipe_33_1_2_5732 ), + .O(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.cmp_quot/twos_comp/simp_addp_a [1]) + ); + LUT2 #( + .INIT ( 4'h6 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.remd_not_fract.cmp_remd/twos_comp/Mmux_simp_addp_a261 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/remd_output.adsu_sel2/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q [9]) +, + .I1(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sign_pipeline.sign_pipe/opt_has_pipe.pipe_33 [1]), + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.remd_not_fract.cmp_remd/twos_comp/simp_addp_a [9]) + ); + LUT2 #( + .INIT ( 4'h6 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.remd_not_fract.cmp_remd/twos_comp/Mmux_simp_addp_a251 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/remd_output.adsu_sel2/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q [8]) +, + .I1(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sign_pipeline.sign_pipe/opt_has_pipe.pipe_33 [1]), + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.remd_not_fract.cmp_remd/twos_comp/simp_addp_a [8]) + ); + LUT2 #( + .INIT ( 4'h6 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.remd_not_fract.cmp_remd/twos_comp/Mmux_simp_addp_a241 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/remd_output.adsu_sel2/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q [7]) +, + .I1(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sign_pipeline.sign_pipe/opt_has_pipe.pipe_33 [1]), + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.remd_not_fract.cmp_remd/twos_comp/simp_addp_a [7]) + ); + LUT2 #( + .INIT ( 4'h6 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.remd_not_fract.cmp_remd/twos_comp/Mmux_simp_addp_a231 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/remd_output.adsu_sel2/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q [6]) +, + .I1(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sign_pipeline.sign_pipe/opt_has_pipe.pipe_33_1_4_5730 ), + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.remd_not_fract.cmp_remd/twos_comp/simp_addp_a [6]) + ); + LUT2 #( + .INIT ( 4'h6 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.remd_not_fract.cmp_remd/twos_comp/Mmux_simp_addp_a221 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/remd_output.adsu_sel2/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q [5]) +, + .I1(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sign_pipeline.sign_pipe/opt_has_pipe.pipe_33_1_4_5730 ), + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.remd_not_fract.cmp_remd/twos_comp/simp_addp_a [5]) + ); + LUT2 #( + .INIT ( 4'h6 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.remd_not_fract.cmp_remd/twos_comp/Mmux_simp_addp_a211 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/remd_output.adsu_sel2/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q [4]) +, + .I1(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sign_pipeline.sign_pipe/opt_has_pipe.pipe_33_1_4_5730 ), + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.remd_not_fract.cmp_remd/twos_comp/simp_addp_a [4]) + ); + LUT2 #( + .INIT ( 4'h6 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.remd_not_fract.cmp_remd/twos_comp/Mmux_simp_addp_a201 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/remd_output.adsu_sel2/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q [3]) +, + .I1(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sign_pipeline.sign_pipe/opt_has_pipe.pipe_33_1_4_5730 ), + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.remd_not_fract.cmp_remd/twos_comp/simp_addp_a [3]) + ); + LUT2 #( + .INIT ( 4'h6 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.remd_not_fract.cmp_remd/twos_comp/Mmux_simp_addp_a191 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/remd_output.adsu_sel2/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q [2]) +, + .I1(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sign_pipeline.sign_pipe/opt_has_pipe.pipe_33_1_3_5729 ), + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.remd_not_fract.cmp_remd/twos_comp/simp_addp_a [2]) + ); + LUT2 #( + .INIT ( 4'h6 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.remd_not_fract.cmp_remd/twos_comp/Mmux_simp_addp_a161 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/remd_output.adsu_sel2/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q [23]) +, + .I1(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sign_pipeline.sign_pipe/opt_has_pipe.pipe_33 [1]), + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.remd_not_fract.cmp_remd/twos_comp/simp_addp_a [23]) + ); + LUT2 #( + .INIT ( 4'h6 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.remd_not_fract.cmp_remd/twos_comp/Mmux_simp_addp_a151 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/remd_output.adsu_sel2/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q [22]) +, + .I1(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sign_pipeline.sign_pipe/opt_has_pipe.pipe_33 [1]), + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.remd_not_fract.cmp_remd/twos_comp/simp_addp_a [22]) + ); + LUT2 #( + .INIT ( 4'h6 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.remd_not_fract.cmp_remd/twos_comp/Mmux_simp_addp_a141 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/remd_output.adsu_sel2/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q [21]) +, + .I1(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sign_pipeline.sign_pipe/opt_has_pipe.pipe_33 [1]), + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.remd_not_fract.cmp_remd/twos_comp/simp_addp_a [21]) + ); + LUT2 #( + .INIT ( 4'h6 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.remd_not_fract.cmp_remd/twos_comp/Mmux_simp_addp_a131 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/remd_output.adsu_sel2/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q [20]) +, + .I1(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sign_pipeline.sign_pipe/opt_has_pipe.pipe_33 [1]), + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.remd_not_fract.cmp_remd/twos_comp/simp_addp_a [20]) + ); + LUT2 #( + .INIT ( 4'h6 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.remd_not_fract.cmp_remd/twos_comp/Mmux_simp_addp_a121 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/remd_output.adsu_sel2/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q [1]) +, + .I1(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sign_pipeline.sign_pipe/opt_has_pipe.pipe_33_1_3_5729 ), + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.remd_not_fract.cmp_remd/twos_comp/simp_addp_a [1]) + ); + LUT2 #( + .INIT ( 4'h6 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.remd_not_fract.cmp_remd/twos_comp/Mmux_simp_addp_a111 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/remd_output.adsu_sel2/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q [19]) +, + .I1(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sign_pipeline.sign_pipe/opt_has_pipe.pipe_33 [1]), + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.remd_not_fract.cmp_remd/twos_comp/simp_addp_a [19]) + ); + LUT2 #( + .INIT ( 4'h6 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.remd_not_fract.cmp_remd/twos_comp/Mmux_simp_addp_a101 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/remd_output.adsu_sel2/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q [18]) +, + .I1(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sign_pipeline.sign_pipe/opt_has_pipe.pipe_33 [1]), + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.remd_not_fract.cmp_remd/twos_comp/simp_addp_a [18]) + ); + LUT2 #( + .INIT ( 4'h6 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.remd_not_fract.cmp_remd/twos_comp/Mmux_simp_addp_a91 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/remd_output.adsu_sel2/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q [17]) +, + .I1(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sign_pipeline.sign_pipe/opt_has_pipe.pipe_33 [1]), + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.remd_not_fract.cmp_remd/twos_comp/simp_addp_a [17]) + ); + LUT2 #( + .INIT ( 4'h6 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.remd_not_fract.cmp_remd/twos_comp/Mmux_simp_addp_a81 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/remd_output.adsu_sel2/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q [16]) +, + .I1(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sign_pipeline.sign_pipe/opt_has_pipe.pipe_33 [1]), + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.remd_not_fract.cmp_remd/twos_comp/simp_addp_a [16]) + ); + LUT2 #( + .INIT ( 4'h6 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.remd_not_fract.cmp_remd/twos_comp/Mmux_simp_addp_a71 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/remd_output.adsu_sel2/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q [15]) +, + .I1(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sign_pipeline.sign_pipe/opt_has_pipe.pipe_33 [1]), + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.remd_not_fract.cmp_remd/twos_comp/simp_addp_a [15]) + ); + LUT2 #( + .INIT ( 4'h6 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.remd_not_fract.cmp_remd/twos_comp/Mmux_simp_addp_a61 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/remd_output.adsu_sel2/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q [14]) +, + .I1(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sign_pipeline.sign_pipe/opt_has_pipe.pipe_33 [1]), + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.remd_not_fract.cmp_remd/twos_comp/simp_addp_a [14]) + ); + LUT2 #( + .INIT ( 4'h6 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.remd_not_fract.cmp_remd/twos_comp/Mmux_simp_addp_a51 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/remd_output.adsu_sel2/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q [13]) +, + .I1(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sign_pipeline.sign_pipe/opt_has_pipe.pipe_33 [1]), + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.remd_not_fract.cmp_remd/twos_comp/simp_addp_a [13]) + ); + LUT2 #( + .INIT ( 4'h6 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.remd_not_fract.cmp_remd/twos_comp/Mmux_simp_addp_a41 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/remd_output.adsu_sel2/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q [12]) +, + .I1(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sign_pipeline.sign_pipe/opt_has_pipe.pipe_33 [1]), + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.remd_not_fract.cmp_remd/twos_comp/simp_addp_a [12]) + ); + LUT2 #( + .INIT ( 4'h6 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.remd_not_fract.cmp_remd/twos_comp/Mmux_simp_addp_a31 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/remd_output.adsu_sel2/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q [11]) +, + .I1(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sign_pipeline.sign_pipe/opt_has_pipe.pipe_33 [1]), + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.remd_not_fract.cmp_remd/twos_comp/simp_addp_a [11]) + ); + LUT2 #( + .INIT ( 4'h6 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.remd_not_fract.cmp_remd/twos_comp/Mmux_simp_addp_a27 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/remd_output.adsu_sel2/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q [10]) +, + .I1(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sign_pipeline.sign_pipe/opt_has_pipe.pipe_33 [1]), + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.remd_not_fract.cmp_remd/twos_comp/simp_addp_a [10]) + ); + LUT3 #( + .INIT ( 8'h6A )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/remd_output.adsu_sel2/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/Mmux_i_simple_model.halfsum251 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<9> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/final_div.del_end_divisor/opt_has_pipe.first_q [9]), + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24>_0 ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/remd_output.adsu_sel2/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum [9]) + + ); + LUT3 #( + .INIT ( 8'h6A )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/remd_output.adsu_sel2/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/Mmux_i_simple_model.halfsum241 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<8> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/final_div.del_end_divisor/opt_has_pipe.first_q [8]), + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24>_0 ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/remd_output.adsu_sel2/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum [8]) + + ); + LUT3 #( + .INIT ( 8'h6A )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/remd_output.adsu_sel2/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/Mmux_i_simple_model.halfsum231 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<7> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/final_div.del_end_divisor/opt_has_pipe.first_q [7]), + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24>_0 ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/remd_output.adsu_sel2/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum [7]) + + ); + LUT3 #( + .INIT ( 8'h6A )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/remd_output.adsu_sel2/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/Mmux_i_simple_model.halfsum221 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<6> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/final_div.del_end_divisor/opt_has_pipe.first_q [6]), + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24>_0 ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/remd_output.adsu_sel2/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum [6]) + + ); + LUT3 #( + .INIT ( 8'h6A )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/remd_output.adsu_sel2/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/Mmux_i_simple_model.halfsum211 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<5> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/final_div.del_end_divisor/opt_has_pipe.first_q [5]), + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24>_0 ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/remd_output.adsu_sel2/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum [5]) + + ); + LUT3 #( + .INIT ( 8'h6A )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/remd_output.adsu_sel2/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/Mmux_i_simple_model.halfsum201 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<4> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/final_div.del_end_divisor/opt_has_pipe.first_q [4]), + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24>_0 ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/remd_output.adsu_sel2/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum [4]) + + ); + LUT3 #( + .INIT ( 8'h6A )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/remd_output.adsu_sel2/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/Mmux_i_simple_model.halfsum191 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<3> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/final_div.del_end_divisor/opt_has_pipe.first_q [3]), + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24>_0 ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/remd_output.adsu_sel2/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum [3]) + + ); + LUT3 #( + .INIT ( 8'h6A )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/remd_output.adsu_sel2/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/Mmux_i_simple_model.halfsum181 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<2> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/final_div.del_end_divisor/opt_has_pipe.first_q [2]), + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24>_0 ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/remd_output.adsu_sel2/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum [2]) + + ); + LUT3 #( + .INIT ( 8'h6A )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/remd_output.adsu_sel2/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/Mmux_i_simple_model.halfsum161 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<23> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/final_div.del_end_divisor/opt_has_pipe.first_q [23]), + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/remd_output.adsu_sel2/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum [23]) + + ); + LUT3 #( + .INIT ( 8'h6A )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/remd_output.adsu_sel2/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/Mmux_i_simple_model.halfsum151 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<22> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/final_div.del_end_divisor/opt_has_pipe.first_q [22]), + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/remd_output.adsu_sel2/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum [22]) + + ); + LUT3 #( + .INIT ( 8'h6A )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/remd_output.adsu_sel2/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/Mmux_i_simple_model.halfsum141 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<21> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/final_div.del_end_divisor/opt_has_pipe.first_q [21]), + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/remd_output.adsu_sel2/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum [21]) + + ); + LUT3 #( + .INIT ( 8'h6A )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/remd_output.adsu_sel2/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/Mmux_i_simple_model.halfsum131 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<20> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/final_div.del_end_divisor/opt_has_pipe.first_q [20]), + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/remd_output.adsu_sel2/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum [20]) + + ); + LUT3 #( + .INIT ( 8'h6A )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/remd_output.adsu_sel2/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/Mmux_i_simple_model.halfsum121 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<1> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/final_div.del_end_divisor/opt_has_pipe.first_q [1]), + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24>_0 ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/remd_output.adsu_sel2/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum [1]) + + ); + LUT3 #( + .INIT ( 8'h6A )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/remd_output.adsu_sel2/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/Mmux_i_simple_model.halfsum111 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<19> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/final_div.del_end_divisor/opt_has_pipe.first_q [19]), + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/remd_output.adsu_sel2/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum [19]) + + ); + LUT3 #( + .INIT ( 8'h6A )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/remd_output.adsu_sel2/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/Mmux_i_simple_model.halfsum101 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<18> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/final_div.del_end_divisor/opt_has_pipe.first_q [18]), + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/remd_output.adsu_sel2/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum [18]) + + ); + LUT3 #( + .INIT ( 8'h6A )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/remd_output.adsu_sel2/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/Mmux_i_simple_model.halfsum91 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<17> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/final_div.del_end_divisor/opt_has_pipe.first_q [17]), + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/remd_output.adsu_sel2/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum [17]) + + ); + LUT3 #( + .INIT ( 8'h6A )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/remd_output.adsu_sel2/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/Mmux_i_simple_model.halfsum81 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<16> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/final_div.del_end_divisor/opt_has_pipe.first_q [16]), + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/remd_output.adsu_sel2/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum [16]) + + ); + LUT3 #( + .INIT ( 8'h6A )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/remd_output.adsu_sel2/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/Mmux_i_simple_model.halfsum71 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<15> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/final_div.del_end_divisor/opt_has_pipe.first_q [15]), + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/remd_output.adsu_sel2/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum [15]) + + ); + LUT3 #( + .INIT ( 8'h6A )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/remd_output.adsu_sel2/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/Mmux_i_simple_model.halfsum61 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<14> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/final_div.del_end_divisor/opt_has_pipe.first_q [14]), + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/remd_output.adsu_sel2/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum [14]) + + ); + LUT3 #( + .INIT ( 8'h6A )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/remd_output.adsu_sel2/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/Mmux_i_simple_model.halfsum51 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<13> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/final_div.del_end_divisor/opt_has_pipe.first_q [13]), + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/remd_output.adsu_sel2/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum [13]) + + ); + LUT3 #( + .INIT ( 8'h6A )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/remd_output.adsu_sel2/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/Mmux_i_simple_model.halfsum41 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<12> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/final_div.del_end_divisor/opt_has_pipe.first_q [12]), + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/remd_output.adsu_sel2/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum [12]) + + ); + LUT3 #( + .INIT ( 8'h6A )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/remd_output.adsu_sel2/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/Mmux_i_simple_model.halfsum31 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<11> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/final_div.del_end_divisor/opt_has_pipe.first_q [11]), + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/remd_output.adsu_sel2/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum [11]) + + ); + LUT3 #( + .INIT ( 8'h6A )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/remd_output.adsu_sel2/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/Mmux_i_simple_model.halfsum26 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<10> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/final_div.del_end_divisor/opt_has_pipe.first_q [10]), + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24>_0 ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/remd_output.adsu_sel2/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum [10]) + + ); + LUT3 #( + .INIT ( 8'h6A )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/remd_output.adsu_sel2/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/Mmux_i_simple_model.halfsum17 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<0> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/final_div.del_end_divisor/opt_has_pipe.first_q [0]), + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24>_0 ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/remd_output.adsu_sel2/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum [0]) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<9>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<8> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<9> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<9> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<8>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<7> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<8> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<8> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<7>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<6> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<7> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<7> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<6>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<5> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<6> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<6> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<5>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<4> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<5> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<5> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<4>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<3> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<4> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<4> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<3>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<2> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<3> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<3> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<2>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<1> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<2> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<2> ) + + ); + LUT2 #( + .INIT ( 4'h9 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<24>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<23> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<24> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<23>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<22> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<23> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<23> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<22>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<21> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<22> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<22> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<21>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<20> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<21> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<21> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<20>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<19> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<20> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<20> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<1>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<0> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<1> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<1> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<19>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<18> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<19> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<19> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<18>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<17> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<18> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<18> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<17>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<16> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<17> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<17> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<16>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<15> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<16> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<16> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<15>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<14> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<15> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<15> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<14>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<13> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<14> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<14> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<13>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<12> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<13> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<13> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<12>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<11> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<12> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<12> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<11>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<10> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<11> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<11> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<10>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<9> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<10> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<10> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<0>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<0> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<0> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<9>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<8> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<9> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<9> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<8>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<7> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<8> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<8> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<7>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<6> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<7> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<7> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<6>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<5> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<6> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<6> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<5>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<4> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<5> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<5> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<4>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<3> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<4> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<4> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<3>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<2> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<3> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<3> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<2>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<1> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<2> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<2> ) + + ); + LUT2 #( + .INIT ( 4'h9 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<24>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<23> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<24> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<23>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<22> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<23> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<23> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<22>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<21> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<22> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<22> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<21>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<20> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<21> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<21> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<20>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<19> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<20> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<20> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<1>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<0> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<1> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<1> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<19>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<18> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<19> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<19> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<18>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<17> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<18> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<18> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<17>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<16> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<17> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<17> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<16>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<15> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<16> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<16> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<15>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<14> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<15> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<15> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<14>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<13> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<14> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<14> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<13>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<12> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<13> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<13> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<12>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<11> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<12> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<12> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<11>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<10> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<11> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<11> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<10>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<9> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<10> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<10> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<0>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<1> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<0> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<0> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<9>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<8> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<9> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<9> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<8>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<7> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<8> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<8> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<7>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<6> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<7> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<7> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<6>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<5> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<6> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<6> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<5>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<4> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<5> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<5> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<4>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<3> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<4> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<4> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<3>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<2> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<3> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<3> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<2>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<1> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<2> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<2> ) + + ); + LUT2 #( + .INIT ( 4'h9 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<24>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<23> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<24> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<23>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<22> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<23> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<23> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<22>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<21> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<22> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<22> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<21>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<20> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<21> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<21> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<20>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<19> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<20> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<20> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<1>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<0> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<1> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<1> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<19>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<18> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<19> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<19> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<18>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<17> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<18> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<18> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<17>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<16> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<17> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<17> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<16>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<15> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<16> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<16> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<15>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<14> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<15> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<15> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<14>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<13> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<14> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<14> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<13>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<12> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<13> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<13> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<12>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<11> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<12> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<12> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<11>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<10> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<11> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<11> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<10>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<9> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<10> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<10> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<0>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<2> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<0> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<0> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<9>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<8> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<9> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<9> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<8>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<7> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<8> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<8> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<7>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<6> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<7> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<7> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<6>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<5> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<6> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<6> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<5>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<4> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<5> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<5> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<4>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<3> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<4> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<4> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<3>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<2> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<3> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<3> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<2>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<1> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<2> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<2> ) + + ); + LUT2 #( + .INIT ( 4'h9 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<24>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<23> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<24> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<23>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<22> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<23> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<23> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<22>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<21> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<22> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<22> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<21>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<20> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<21> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<21> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<20>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<19> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<20> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<20> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<1>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<0> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<1> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<1> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<19>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<18> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<19> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<19> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<18>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<17> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<18> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<18> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<17>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<16> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<17> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<17> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<16>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<15> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<16> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<16> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<15>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<14> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<15> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<15> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<14>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<13> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<14> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<14> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<13>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<12> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<13> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<13> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<12>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<11> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<12> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<12> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<11>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<10> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<11> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<11> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<10>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<9> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<10> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<10> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<0>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<3> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<0> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<0> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<9>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<8> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<9> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<9> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<8>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<7> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<8> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<8> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<7>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<6> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<7> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<7> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<6>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<5> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<6> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<6> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<5>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<4> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<5> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<5> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<4>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<3> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<4> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<4> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<3>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<2> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<3> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<3> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<2>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<1> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<2> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<2> ) + + ); + LUT2 #( + .INIT ( 4'h9 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<24>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<23> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<24> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<23>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<22> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<23> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<23> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<22>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<21> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<22> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<22> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<21>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<20> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<21> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<21> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<20>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<19> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<20> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<20> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<1>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<0> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<1> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<1> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<19>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<18> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<19> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<19> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<18>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<17> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<18> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<18> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<17>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<16> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<17> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<17> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<16>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<15> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<16> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<16> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<15>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<14> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<15> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<15> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<14>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<13> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<14> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<14> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<13>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<12> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<13> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<13> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<12>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<11> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<12> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<12> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<11>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<10> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<11> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<11> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<10>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<9> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<10> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<10> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<0>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<4> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<0> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<0> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<9>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<8> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<9> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<9> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<8>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<7> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<8> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<8> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<7>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<6> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<7> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<7> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<6>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<5> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<6> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<6> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<5>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<4> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<5> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<5> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<4>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<3> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<4> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<4> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<3>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<2> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<3> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<3> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<2>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<1> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<2> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<2> ) + + ); + LUT2 #( + .INIT ( 4'h9 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<24>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<23> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<24> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<23>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<22> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<23> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<23> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<22>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<21> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<22> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<22> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<21>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<20> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<21> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<21> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<20>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<19> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<20> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<20> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<1>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<0> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<1> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<1> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<19>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<18> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<19> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<19> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<18>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<17> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<18> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<18> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<17>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<16> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<17> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<17> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<16>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<15> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<16> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<16> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<15>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<14> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<15> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<15> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<14>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<13> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<14> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<14> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<13>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<12> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<13> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<13> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<12>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<11> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<12> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<12> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<11>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<10> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<11> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<11> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<10>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<9> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<10> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<10> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<0>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<5> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<0> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<0> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<9>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<8> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<9> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<9> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<8>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<7> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<8> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<8> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<7>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<6> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<7> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<7> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<6>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<5> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<6> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<6> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<5>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<4> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<5> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<5> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<4>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<3> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<4> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<4> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<3>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<2> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<3> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<3> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<2>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<1> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<2> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<2> ) + + ); + LUT2 #( + .INIT ( 4'h9 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<24>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<23> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<24> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<23>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<22> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<23> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<23> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<22>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<21> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<22> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<22> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<21>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<20> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<21> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<21> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<20>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<19> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<20> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<20> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<1>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<0> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<1> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<1> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<19>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<18> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<19> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<19> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<18>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<17> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<18> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<18> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<17>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<16> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<17> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<17> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<16>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<15> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<16> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<16> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<15>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<14> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<15> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<15> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<14>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<13> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<14> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<14> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<13>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<12> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<13> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<13> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<12>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<11> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<12> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<12> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<11>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<10> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<11> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<11> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<10>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<9> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<10> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<10> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<0>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<6> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<0> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<0> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<9>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<8> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<9> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<9> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<8>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<7> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<8> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<8> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<7>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<6> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<7> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<7> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<6>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<5> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<6> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<6> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<5>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<4> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<5> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<5> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<4>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<3> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<4> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<4> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<3>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<2> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<3> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<3> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<2>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<1> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<2> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<2> ) + + ); + LUT2 #( + .INIT ( 4'h9 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<24>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<23> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<24> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<23>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<22> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<23> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<23> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<22>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<21> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<22> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<22> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<21>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<20> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<21> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<21> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<20>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<19> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<20> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<20> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<1>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<0> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<1> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<1> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<19>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<18> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<19> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<19> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<18>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<17> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<18> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<18> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<17>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<16> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<17> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<17> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<16>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<15> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<16> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<16> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<15>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<14> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<15> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<15> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<14>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<13> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<14> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<14> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<13>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<12> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<13> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<13> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<12>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<11> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<12> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<12> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<11>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<10> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<11> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<11> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<10>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<9> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<10> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<10> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<0>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<7> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<0> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<0> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<9>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<8> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<9> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<9> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<8>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<7> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<8> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<8> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<7>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<6> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<7> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<7> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<6>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<5> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<6> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<6> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<5>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<4> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<5> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<5> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<4>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<3> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<4> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<4> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<3>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<2> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<3> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<3> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<2>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<1> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<2> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<2> ) + + ); + LUT2 #( + .INIT ( 4'h9 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<24>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<23> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<24> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<23>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<22> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<23> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<23> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<22>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<21> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<22> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<22> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<21>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<20> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<21> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<21> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<20>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<19> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<20> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<20> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<1>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<0> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<1> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<1> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<19>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<18> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<19> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<19> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<18>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<17> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<18> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<18> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<17>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<16> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<17> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<17> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<16>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<15> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<16> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<16> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<15>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<14> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<15> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<15> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<14>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<13> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<14> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<14> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<13>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<12> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<13> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<13> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<12>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<11> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<12> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<12> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<11>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<10> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<11> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<11> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<10>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<9> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<10> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<10> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<0>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<8> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<0> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<0> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<9>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<8> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<9> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<9> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<8>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<7> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<8> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<8> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<7>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<6> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<7> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<7> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<6>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<5> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<6> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<6> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<5>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<4> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<5> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<5> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<4>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<3> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<4> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<4> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<3>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<2> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<3> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<3> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<2>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<1> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<2> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<2> ) + + ); + LUT2 #( + .INIT ( 4'h9 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<24>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<23> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<24> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<23>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<22> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<23> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<23> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<22>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<21> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<22> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<22> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<21>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<20> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<21> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<21> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<20>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<19> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<20> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<20> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<1>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<0> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<1> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<1> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<19>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<18> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<19> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<19> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<18>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<17> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<18> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<18> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<17>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<16> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<17> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<17> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<16>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<15> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<16> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<16> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<15>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<14> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<15> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<15> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<14>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<13> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<14> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<14> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<13>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<12> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<13> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<13> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<12>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<11> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<12> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<12> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<11>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<10> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<11> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<11> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<10>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<9> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<10> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<10> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<0>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<9> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<0> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<0> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<9>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<8> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<9> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<9> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<8>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<7> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<8> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<8> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<7>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<6> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<7> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<7> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<6>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<5> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<6> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<6> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<5>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<4> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<5> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<5> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<4>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<3> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<4> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<4> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<3>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<2> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<3> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<3> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<2>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<1> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<2> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<2> ) + + ); + LUT2 #( + .INIT ( 4'h9 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<24>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<23> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<24> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<23>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<22> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<23> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<23> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<22>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<21> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<22> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<22> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<21>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<20> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<21> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<21> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<20>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<19> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<20> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<20> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<1>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<0> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<1> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<1> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<19>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<18> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<19> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<19> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<18>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<17> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<18> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<18> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<17>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<16> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<17> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<17> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<16>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<15> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<16> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<16> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<15>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<14> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<15> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<15> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<14>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<13> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<14> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<14> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<13>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<12> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<13> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<13> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<12>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<11> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<12> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<12> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<11>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<10> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<11> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<11> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<10>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<9> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<10> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<10> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<0>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<10> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<0> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<0> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<9>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<8> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<9> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<9> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<8>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<7> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<8> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<8> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<7>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<6> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<7> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<7> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<6>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<5> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<6> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<6> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<5>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<4> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<5> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<5> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<4>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<3> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<4> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<4> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<3>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<2> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<3> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<3> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<2>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<1> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<2> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<2> ) + + ); + LUT2 #( + .INIT ( 4'h9 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<24>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<23> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<24> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<23>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<22> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<23> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<23> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<22>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<21> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<22> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<22> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<21>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<20> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<21> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<21> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<20>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<19> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<20> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<20> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<1>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<0> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<1> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<1> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<19>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<18> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<19> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<19> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<18>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<17> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<18> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<18> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<17>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<16> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<17> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<17> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<16>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<15> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<16> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<16> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<15>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<14> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<15> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<15> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<14>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<13> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<14> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<14> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<13>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<12> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<13> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<13> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<12>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<11> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<12> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<12> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<11>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<10> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<11> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<11> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<10>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<9> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<10> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<10> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<0>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<11> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<0> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<0> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<9>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<8> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<9> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<9> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<8>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<7> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<8> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<8> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<7>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<6> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<7> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<7> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<6>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<5> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<6> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<6> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<5>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<4> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<5> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<5> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<4>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<3> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<4> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<4> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<3>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<2> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<3> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<3> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<2>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<1> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<2> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<2> ) + + ); + LUT2 #( + .INIT ( 4'h9 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<24>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<23> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<24> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<23>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<22> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<23> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<23> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<22>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<21> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<22> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<22> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<21>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<20> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<21> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<21> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<20>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<19> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<20> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<20> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<1>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<0> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<1> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<1> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<19>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<18> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<19> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<19> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<18>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<17> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<18> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<18> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<17>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<16> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<17> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<17> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<16>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<15> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<16> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<16> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<15>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<14> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<15> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<15> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<14>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<13> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<14> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<14> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<13>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<12> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<13> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<13> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<12>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<11> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<12> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<12> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<11>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<10> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<11> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<11> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<10>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<9> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<10> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<10> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<0>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<12> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<0> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<0> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<9>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<8> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<9> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<9> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<8>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<7> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<8> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<8> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<7>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<6> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<7> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<7> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<6>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<5> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<6> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<6> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<5>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<4> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<5> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<5> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<4>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<3> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<4> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<4> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<3>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<2> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<3> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<3> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<2>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<1> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<2> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<2> ) + + ); + LUT2 #( + .INIT ( 4'h9 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<24>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<23> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<24> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<23>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<22> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<23> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<23> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<22>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<21> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<22> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<22> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<21>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<20> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<21> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<21> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<20>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<19> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<20> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<20> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<1>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<0> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<1> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<1> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<19>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<18> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<19> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<19> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<18>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<17> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<18> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<18> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<17>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<16> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<17> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<17> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<16>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<15> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<16> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<16> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<15>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<14> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<15> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<15> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<14>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<13> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<14> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<14> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<13>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<12> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<13> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<13> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<12>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<11> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<12> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<12> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<11>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<10> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<11> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<11> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<10>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<9> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<10> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<10> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<0>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<13> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<0> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<0> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<9>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<8> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<9> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<9> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<8>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<7> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<8> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<8> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<7>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<6> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<7> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<7> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<6>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<5> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<6> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<6> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<5>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<4> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<5> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<5> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<4>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<3> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<4> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<4> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<3>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<2> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<3> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<3> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<2>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<1> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<2> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<2> ) + + ); + LUT2 #( + .INIT ( 4'h9 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<24>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<23> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<24> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<23>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<22> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<23> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<23> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<22>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<21> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<22> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<22> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<21>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<20> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<21> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<21> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<20>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<19> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<20> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<20> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<1>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<0> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<1> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<1> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<19>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<18> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<19> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<19> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<18>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<17> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<18> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<18> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<17>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<16> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<17> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<17> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<16>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<15> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<16> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<16> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<15>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<14> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<15> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<15> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<14>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<13> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<14> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<14> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<13>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<12> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<13> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<13> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<12>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<11> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<12> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<12> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<11>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<10> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<11> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<11> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<10>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<9> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<10> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<10> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<0>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<14> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<0> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<0> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<9>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<8> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<9> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<9> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<8>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<7> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<8> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<8> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<7>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<6> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<7> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<7> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<6>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<5> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<6> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<6> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<5>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<4> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<5> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<5> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<4>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<3> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<4> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<4> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<3>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<2> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<3> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<3> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<2>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<1> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<2> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<2> ) + + ); + LUT2 #( + .INIT ( 4'h9 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<24>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<23> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<24> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<23>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<22> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<23> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<23> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<22>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<21> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<22> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<22> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<21>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<20> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<21> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<21> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<20>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<19> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<20> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<20> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<1>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<0> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<1> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<1> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<19>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<18> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<19> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<19> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<18>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<17> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<18> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<18> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<17>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<16> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<17> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<17> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<16>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<15> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<16> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<16> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<15>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<14> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<15> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<15> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<14>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<13> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<14> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<14> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<13>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<12> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<13> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<13> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<12>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<11> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<12> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<12> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<11>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<10> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<11> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<11> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<10>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<9> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<10> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<10> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<0>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<15> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<0> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<0> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<9>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<8> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<9> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<9> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<8>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<7> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<8> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<8> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<7>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<6> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<7> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<7> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<6>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<5> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<6> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<6> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<5>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<4> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<5> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<5> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<4>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<3> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<4> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<4> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<3>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<2> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<3> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<3> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<2>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<1> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<2> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<2> ) + + ); + LUT2 #( + .INIT ( 4'h9 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<24>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<23> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<24> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<23>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<22> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<23> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<23> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<22>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<21> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<22> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<22> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<21>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<20> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<21> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<21> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<20>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<19> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<20> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<20> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<1>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<0> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<1> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<1> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<19>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<18> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<19> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<19> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<18>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<17> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<18> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<18> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<17>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<16> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<17> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<17> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<16>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<15> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<16> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<16> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<15>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<14> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<15> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<15> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<14>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<13> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<14> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<14> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<13>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<12> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<13> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<13> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<12>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<11> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<12> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<12> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<11>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<10> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<11> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<11> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<10>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<9> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<10> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<10> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<0>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<16> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<0> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<0> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<9>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<8> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<9> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<9> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<8>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<7> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<8> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<8> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<7>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<6> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<7> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<7> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<6>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<5> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<6> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<6> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<5>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<4> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<5> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<5> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<4>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<3> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<4> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<4> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<3>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<2> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<3> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<3> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<2>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<1> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<2> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<2> ) + + ); + LUT2 #( + .INIT ( 4'h9 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<24>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<23> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<24> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<23>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<22> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<23> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<23> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<22>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<21> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<22> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<22> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<21>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<20> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<21> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<21> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<20>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<19> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<20> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<20> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<1>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<0> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<1> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<1> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<19>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<18> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<19> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<19> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<18>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<17> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<18> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<18> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<17>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<16> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<17> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<17> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<16>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<15> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<16> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<16> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<15>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<14> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<15> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<15> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<14>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<13> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<14> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<14> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<13>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<12> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<13> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<13> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<12>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<11> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<12> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<12> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<11>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<10> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<11> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<11> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<10>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<9> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<10> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<10> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<0>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<17> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<0> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<0> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<9>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<8> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<9> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<9> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<8>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<7> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<8> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<8> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<7>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<6> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<7> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<7> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<6>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<5> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<6> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<6> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<5>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<4> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<5> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<5> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<4>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<3> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<4> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<4> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<3>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<2> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<3> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<3> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<2>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<1> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<2> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<2> ) + + ); + LUT2 #( + .INIT ( 4'h9 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<24>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<23> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<24> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<23>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<22> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<23> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<23> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<22>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<21> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<22> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<22> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<21>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<20> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<21> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<21> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<20>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<19> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<20> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<20> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<1>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<0> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<1> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<1> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<19>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<18> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<19> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<19> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<18>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<17> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<18> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<18> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<17>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<16> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<17> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<17> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<16>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<15> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<16> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<16> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<15>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<14> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<15> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<15> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<14>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<13> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<14> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<14> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<13>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<12> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<13> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<13> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<12>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<11> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<12> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<12> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<11>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<10> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<11> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<11> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<10>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<9> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<10> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<10> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<0>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<18> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<0> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<0> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<9>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<8> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<9> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<9> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<8>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<7> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<8> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<8> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<7>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<6> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<7> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<7> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<6>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<5> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<6> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<6> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<5>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<4> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<5> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<5> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<4>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<3> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<4> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<4> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<3>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<2> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<3> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<3> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<2>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<1> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<2> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<2> ) + + ); + LUT2 #( + .INIT ( 4'h9 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<24>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<23> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<24> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<23>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<22> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<23> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<23> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<22>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<21> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<22> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<22> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<21>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<20> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<21> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<21> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<20>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<19> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<20> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<20> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<1>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<0> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<1> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<1> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<19>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<18> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<19> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<19> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<18>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<17> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<18> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<18> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<17>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<16> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<17> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<17> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<16>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<15> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<16> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<16> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<15>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<14> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<15> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<15> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<14>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<13> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<14> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<14> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<13>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<12> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<13> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<13> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<12>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<11> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<12> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<12> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<11>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<10> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<11> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<11> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<10>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<9> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<10> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<10> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<0>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<19> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<0> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<0> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<9>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<8> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<9> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<9> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<8>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<7> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<8> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<8> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<7>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<6> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<7> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<7> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<6>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<5> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<6> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<6> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<5>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<4> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<5> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<5> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<4>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<3> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<4> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<4> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<3>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<2> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<3> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<3> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<2>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<1> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<2> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<2> ) + + ); + LUT2 #( + .INIT ( 4'h9 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<24>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<23> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<24> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<23>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<22> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<23> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<23> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<22>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<21> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<22> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<22> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<21>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<20> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<21> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<21> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<20>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<19> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<20> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<20> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<1>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<0> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<1> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<1> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<19>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<18> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<19> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<19> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<18>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<17> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<18> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<18> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<17>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<16> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<17> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<17> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<16>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<15> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<16> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<16> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<15>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<14> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<15> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<15> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<14>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<13> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<14> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<14> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<13>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<12> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<13> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<13> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<12>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<11> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<12> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<12> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<11>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<10> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<11> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<11> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<10>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<9> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<10> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<10> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<0>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<20> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<0> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<0> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<9>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<8> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<9> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<9> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<8>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<7> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<8> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<8> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<7>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<6> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<7> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<7> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<6>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<5> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<6> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<6> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<5>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<4> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<5> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<5> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<4>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<3> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<4> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<4> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<3>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<2> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<3> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<3> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<2>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<1> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<2> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<2> ) + + ); + LUT2 #( + .INIT ( 4'h9 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<24>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<23> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<24> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<23>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<22> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<23> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<23> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<22>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<21> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<22> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<22> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<21>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<20> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<21> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<21> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<20>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<19> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<20> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<20> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<1>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<0> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<1> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<1> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<19>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<18> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<19> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<19> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<18>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<17> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<18> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<18> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<17>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<16> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<17> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<17> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<16>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<15> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<16> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<16> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<15>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<14> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<15> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<15> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<14>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<13> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<14> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<14> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<13>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<12> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<13> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<13> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<12>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<11> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<12> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<12> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<11>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<10> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<11> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<11> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<10>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<9> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<10> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<10> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<0>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<21> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<0> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<0> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<9>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<8> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<9> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<9> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<8>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<7> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<8> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<8> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<7>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<6> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<7> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<7> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<6>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<5> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<6> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<6> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<5>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<4> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<5> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<5> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<4>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<3> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<4> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<4> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<3>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<2> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<3> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<3> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<2>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<1> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<2> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<2> ) + + ); + LUT2 #( + .INIT ( 4'h9 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<24>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<23> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<24> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<23>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<22> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<23> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<23> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<22>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<21> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<22> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<22> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<21>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<20> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<21> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<21> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<20>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<19> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<20> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<20> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<1>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<0> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<1> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<1> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<19>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<18> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<19> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<19> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<18>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<17> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<18> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<18> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<17>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<16> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<17> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<17> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<16>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<15> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<16> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<16> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<15>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<14> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<15> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<15> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<14>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<13> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<14> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<14> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<13>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<12> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<13> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<13> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<12>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<11> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<12> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<12> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<11>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<10> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<11> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<11> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<10>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<9> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<10> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<10> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<0>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<22> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<0> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<0> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<9>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<8> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<9> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<9> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<8>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<7> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<8> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<8> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<7>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<6> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<7> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<7> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<6>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<5> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<6> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<6> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<5>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<4> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<5> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<5> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<4>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<3> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<4> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<4> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<3>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<2> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<3> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<3> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<2>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<1> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<2> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<2> ) + + ); + LUT2 #( + .INIT ( 4'h9 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<24>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<23> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<24> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<23>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<22> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<23> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<23> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<22>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<21> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<22> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<22> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<21>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<20> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<21> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<21> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<20>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<19> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<20> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<20> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<1>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<0> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<1> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<1> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<19>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<18> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<19> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<19> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<18>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<17> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<18> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<18> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<17>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<16> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<17> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<17> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<16>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<15> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<16> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<16> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<15>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<14> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<15> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<15> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<14>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<13> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<14> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<14> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<13>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<12> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<13> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<13> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<12>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<11> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<12> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<12> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<11>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<10> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<11> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<11> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<10>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<9> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<10> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<10> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<0>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<23> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<0> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<0> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<9>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<8> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<9> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<9> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<8>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<7> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<8> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<8> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<7>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<6> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<7> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<7> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<6>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<5> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<6> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<6> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<5>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<4> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<5> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<5> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<4>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<3> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<4> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<4> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<3>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<2> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<3> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<3> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<2>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<1> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<2> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<2> ) + + ); + LUT2 #( + .INIT ( 4'h9 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<24>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<23> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<24> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<23>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<22> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<23> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<23> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<22>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<21> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<22> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<22> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<21>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<20> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<21> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<21> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<20>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<19> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<20> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<20> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<1>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<0> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<1> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<1> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<19>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<18> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<19> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<19> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<18>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<17> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<18> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<18> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<17>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<16> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<17> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<17> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<16>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<15> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<16> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<16> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<15>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<14> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<15> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<15> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<14>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<13> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<14> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<14> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<13>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<12> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<13> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<13> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<12>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<11> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<12> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<12> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<11>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<10> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<11> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<11> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<10>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<9> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<10> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<10> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<0>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<24> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<0> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<0> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<9>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<8> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<9> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<9> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<8>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<7> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<8> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<8> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<7>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<6> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<7> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<7> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<6>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<5> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<6> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<6> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<5>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<4> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<5> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<5> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<4>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<3> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<4> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<4> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<3>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<2> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<3> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<3> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<2>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<1> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<2> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<2> ) + + ); + LUT2 #( + .INIT ( 4'h9 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<24>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<23> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<24> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<23>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<22> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<23> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<23> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<22>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<21> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<22> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<22> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<21>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<20> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<21> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<21> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<20>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<19> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<20> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<20> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<1>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<0> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<1> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<1> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<19>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<18> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<19> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<19> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<18>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<17> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<18> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<18> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<17>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<16> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<17> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<17> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<16>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<15> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<16> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<16> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<15>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<14> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<15> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<15> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<14>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<13> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<14> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<14> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<13>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<12> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<13> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<13> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<12>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<11> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<12> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<12> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<11>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<10> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<11> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<11> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<10>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<9> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<10> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<10> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<0>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<25> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<0> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<0> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<9>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<8> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<9> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<9> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<8>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<7> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<8> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<8> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<7>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<6> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<7> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<7> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<6>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<5> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<6> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<6> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<5>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<4> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<5> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<5> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<4>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<3> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<4> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<4> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<3>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<2> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<3> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<3> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<2>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<1> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<2> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<2> ) + + ); + LUT2 #( + .INIT ( 4'h9 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<24>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<23> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<24> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<23>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<22> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<23> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<23> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<22>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<21> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<22> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<22> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<21>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<20> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<21> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<21> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<20>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<19> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<20> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<20> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<1>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<0> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<1> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<1> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<19>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<18> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<19> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<19> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<18>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<17> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<18> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<18> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<17>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<16> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<17> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<17> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<16>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<15> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<16> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<16> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<15>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<14> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<15> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<15> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<14>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<13> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<14> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<14> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<13>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<12> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<13> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<13> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<12>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<11> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<12> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<12> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<11>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<10> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<11> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<11> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<10>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<9> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<10> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<10> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<0>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<26> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<0> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<0> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<9>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<8> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<9> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<9> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<8>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<7> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<8> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<8> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<7>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<6> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<7> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<7> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<6>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<5> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<6> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<6> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<5>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<4> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<5> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<5> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<4>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<3> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<4> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<4> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<3>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<2> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<3> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<3> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<2>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<1> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<2> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<2> ) + + ); + LUT2 #( + .INIT ( 4'h9 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<24>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<23> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<24> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<23>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<22> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<23> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<23> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<22>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<21> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<22> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<22> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<21>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<20> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<21> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<21> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<20>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<19> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<20> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<20> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<1>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<0> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<1> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<1> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<19>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<18> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<19> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<19> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<18>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<17> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<18> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<18> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<17>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<16> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<17> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<17> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<16>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<15> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<16> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<16> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<15>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<14> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<15> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<15> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<14>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<13> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<14> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<14> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<13>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<12> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<13> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<13> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<12>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<11> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<12> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<12> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<11>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<10> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<11> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<11> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<10>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<9> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<10> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<10> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<0>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<27> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<0> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<0> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<9>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<8> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<9> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<9> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<8>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<7> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<8> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<8> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<7>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<6> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<7> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<7> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<6>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<5> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<6> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<6> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<5>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<4> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<5> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<5> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<4>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<3> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<4> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<4> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<3>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<2> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<3> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24>_0 ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<3> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<2>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<1> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<2> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24>_0 ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<2> ) + + ); + LUT2 #( + .INIT ( 4'h9 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<24>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<23> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<24> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<23>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<22> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<23> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<23> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<22>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<21> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<22> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<22> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<21>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<20> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<21> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<21> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<20>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<19> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<20> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<20> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<1>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<0> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<1> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24>_0 ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<1> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<19>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<18> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<19> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<19> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<18>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<17> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<18> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<18> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<17>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<16> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<17> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<17> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<16>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<15> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<16> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<16> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<15>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<14> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<15> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<15> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<14>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<13> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<14> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<14> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<13>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<12> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<13> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<13> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<12>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<11> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<12> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<12> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<11>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<10> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<11> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<11> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<10>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<9> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<10> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<10> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<0>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<28> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<0> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24>_0 ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<0> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<9>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<8> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<9> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<9> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<8>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<7> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<8> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<8> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<7>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<6> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<7> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<7> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<6>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<5> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<6> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<6> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<5>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<4> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<5> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<5> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<4>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<3> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<4> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<4> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<3>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<2> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<3> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24>_0 ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<3> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<2>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<1> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<2> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24>_0 ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<2> ) + + ); + LUT2 #( + .INIT ( 4'h9 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<24>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<23> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<24> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<23>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<22> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<23> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<23> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<22>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<21> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<22> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<22> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<21>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<20> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<21> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<21> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<20>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<19> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<20> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<20> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<1>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<0> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<1> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24>_0 ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<1> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<19>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<18> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<19> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<19> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<18>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<17> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<18> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<18> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<17>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<16> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<17> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<17> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<16>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<15> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<16> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<16> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<15>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<14> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<15> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<15> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<14>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<13> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<14> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<14> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<13>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<12> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<13> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<13> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<12>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<11> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<12> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<12> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<11>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<10> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<11> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<11> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<10>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<9> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<10> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<10> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<0>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<29> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<0> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24>_0 ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<0> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<9>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<8> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<9> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<9> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<8>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<7> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<8> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<8> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<7>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<6> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<7> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<7> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<6>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<5> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<6> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<6> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<5>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<4> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<5> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<5> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<4>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<3> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<4> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<4> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<3>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<2> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<3> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24>_0 ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<3> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<2>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<1> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<2> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24>_0 ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<2> ) + + ); + LUT2 #( + .INIT ( 4'h9 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<24>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<23> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<24> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<23>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<22> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<23> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<23> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<22>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<21> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<22> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<22> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<21>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<20> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<21> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<21> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<20>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<19> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<20> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<20> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<1>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<0> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<1> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24>_0 ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<1> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<19>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<18> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<19> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<19> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<18>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<17> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<18> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<18> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<17>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<16> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<17> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<17> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<16>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<15> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<16> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<16> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<15>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<14> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<15> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<15> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<14>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<13> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<14> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<14> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<13>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<12> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<13> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<13> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<12>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<11> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<12> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<12> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<11>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<10> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<11> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<11> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<10>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<9> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<10> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<10> ) + + ); + LUT3 #( + .INIT ( 8'h69 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<0>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<30> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<0> ) +, + .I2 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24>_0 ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<0> ) + + ); + LUT2 #( + .INIT ( 4'h9 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<0>1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<31> ) +, + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<0> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<0> ) + + ); + LUT1 #( + .INIT ( 2'h1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].adder_gen.reg_req.adsu_mod/inv_o1 ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .O(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].adder_gen.reg_req.adsu_mod/inv_o ) + ); + LUT2 #( + .INIT ( 4'h6 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_divisor/twos_comp/Mmux_simp_addp_a251 ( + .I0(divisor_3[9]), + .I1(divisor_3[23]), + .O(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_divisor/twos_comp/simp_addp_a [9]) + ); + LUT2 #( + .INIT ( 4'h6 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_divisor/twos_comp/Mmux_simp_addp_a241 ( + .I0(divisor_3[8]), + .I1(divisor_3[23]), + .O(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_divisor/twos_comp/simp_addp_a [8]) + ); + LUT2 #( + .INIT ( 4'h6 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_divisor/twos_comp/Mmux_simp_addp_a231 ( + .I0(divisor_3[7]), + .I1(divisor_3[23]), + .O(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_divisor/twos_comp/simp_addp_a [7]) + ); + LUT2 #( + .INIT ( 4'h6 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_divisor/twos_comp/Mmux_simp_addp_a221 ( + .I0(divisor_3[6]), + .I1(divisor_3[23]), + .O(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_divisor/twos_comp/simp_addp_a [6]) + ); + LUT2 #( + .INIT ( 4'h6 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_divisor/twos_comp/Mmux_simp_addp_a211 ( + .I0(divisor_3[5]), + .I1(divisor_3[23]), + .O(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_divisor/twos_comp/simp_addp_a [5]) + ); + LUT2 #( + .INIT ( 4'h6 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_divisor/twos_comp/Mmux_simp_addp_a201 ( + .I0(divisor_3[4]), + .I1(divisor_3[23]), + .O(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_divisor/twos_comp/simp_addp_a [4]) + ); + LUT2 #( + .INIT ( 4'h6 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_divisor/twos_comp/Mmux_simp_addp_a191 ( + .I0(divisor_3[3]), + .I1(divisor_3[23]), + .O(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_divisor/twos_comp/simp_addp_a [3]) + ); + LUT2 #( + .INIT ( 4'h6 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_divisor/twos_comp/Mmux_simp_addp_a181 ( + .I0(divisor_3[2]), + .I1(divisor_3[23]), + .O(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_divisor/twos_comp/simp_addp_a [2]) + ); + LUT2 #( + .INIT ( 4'h6 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_divisor/twos_comp/Mmux_simp_addp_a151 ( + .I0(divisor_3[22]), + .I1(divisor_3[23]), + .O(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_divisor/twos_comp/simp_addp_a [22]) + ); + LUT2 #( + .INIT ( 4'h6 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_divisor/twos_comp/Mmux_simp_addp_a141 ( + .I0(divisor_3[21]), + .I1(divisor_3[23]), + .O(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_divisor/twos_comp/simp_addp_a [21]) + ); + LUT2 #( + .INIT ( 4'h6 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_divisor/twos_comp/Mmux_simp_addp_a131 ( + .I0(divisor_3[20]), + .I1(divisor_3[23]), + .O(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_divisor/twos_comp/simp_addp_a [20]) + ); + LUT2 #( + .INIT ( 4'h6 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_divisor/twos_comp/Mmux_simp_addp_a121 ( + .I0(divisor_3[1]), + .I1(divisor_3[23]), + .O(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_divisor/twos_comp/simp_addp_a [1]) + ); + LUT2 #( + .INIT ( 4'h6 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_divisor/twos_comp/Mmux_simp_addp_a111 ( + .I0(divisor_3[19]), + .I1(divisor_3[23]), + .O(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_divisor/twos_comp/simp_addp_a [19]) + ); + LUT2 #( + .INIT ( 4'h6 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_divisor/twos_comp/Mmux_simp_addp_a101 ( + .I0(divisor_3[18]), + .I1(divisor_3[23]), + .O(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_divisor/twos_comp/simp_addp_a [18]) + ); + LUT2 #( + .INIT ( 4'h6 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_divisor/twos_comp/Mmux_simp_addp_a91 ( + .I0(divisor_3[17]), + .I1(divisor_3[23]), + .O(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_divisor/twos_comp/simp_addp_a [17]) + ); + LUT2 #( + .INIT ( 4'h6 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_divisor/twos_comp/Mmux_simp_addp_a81 ( + .I0(divisor_3[16]), + .I1(divisor_3[23]), + .O(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_divisor/twos_comp/simp_addp_a [16]) + ); + LUT2 #( + .INIT ( 4'h6 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_divisor/twos_comp/Mmux_simp_addp_a71 ( + .I0(divisor_3[15]), + .I1(divisor_3[23]), + .O(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_divisor/twos_comp/simp_addp_a [15]) + ); + LUT2 #( + .INIT ( 4'h6 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_divisor/twos_comp/Mmux_simp_addp_a61 ( + .I0(divisor_3[14]), + .I1(divisor_3[23]), + .O(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_divisor/twos_comp/simp_addp_a [14]) + ); + LUT2 #( + .INIT ( 4'h6 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_divisor/twos_comp/Mmux_simp_addp_a51 ( + .I0(divisor_3[13]), + .I1(divisor_3[23]), + .O(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_divisor/twos_comp/simp_addp_a [13]) + ); + LUT2 #( + .INIT ( 4'h6 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_divisor/twos_comp/Mmux_simp_addp_a41 ( + .I0(divisor_3[12]), + .I1(divisor_3[23]), + .O(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_divisor/twos_comp/simp_addp_a [12]) + ); + LUT2 #( + .INIT ( 4'h6 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_divisor/twos_comp/Mmux_simp_addp_a31 ( + .I0(divisor_3[11]), + .I1(divisor_3[23]), + .O(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_divisor/twos_comp/simp_addp_a [11]) + ); + LUT2 #( + .INIT ( 4'h6 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_divisor/twos_comp/Mmux_simp_addp_a26 ( + .I0(divisor_3[10]), + .I1(divisor_3[23]), + .O(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_divisor/twos_comp/simp_addp_a [10]) + ); + LUT2 #( + .INIT ( 4'h6 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_dividend/twos_comp/Mmux_simp_addp_a331 ( + .I0(dividend_2[9]), + .I1(dividend_2[31]), + .O(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_dividend/twos_comp/simp_addp_a [9]) + ); + LUT2 #( + .INIT ( 4'h6 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_dividend/twos_comp/Mmux_simp_addp_a321 ( + .I0(dividend_2[8]), + .I1(dividend_2[31]), + .O(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_dividend/twos_comp/simp_addp_a [8]) + ); + LUT2 #( + .INIT ( 4'h6 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_dividend/twos_comp/Mmux_simp_addp_a311 ( + .I0(dividend_2[7]), + .I1(dividend_2[31]), + .O(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_dividend/twos_comp/simp_addp_a [7]) + ); + LUT2 #( + .INIT ( 4'h6 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_dividend/twos_comp/Mmux_simp_addp_a301 ( + .I0(dividend_2[6]), + .I1(dividend_2[31]), + .O(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_dividend/twos_comp/simp_addp_a [6]) + ); + LUT2 #( + .INIT ( 4'h6 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_dividend/twos_comp/Mmux_simp_addp_a291 ( + .I0(dividend_2[5]), + .I1(dividend_2[31]), + .O(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_dividend/twos_comp/simp_addp_a [5]) + ); + LUT2 #( + .INIT ( 4'h6 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_dividend/twos_comp/Mmux_simp_addp_a281 ( + .I0(dividend_2[4]), + .I1(dividend_2[31]), + .O(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_dividend/twos_comp/simp_addp_a [4]) + ); + LUT2 #( + .INIT ( 4'h6 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_dividend/twos_comp/Mmux_simp_addp_a271 ( + .I0(dividend_2[3]), + .I1(dividend_2[31]), + .O(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_dividend/twos_comp/simp_addp_a [3]) + ); + LUT2 #( + .INIT ( 4'h6 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_dividend/twos_comp/Mmux_simp_addp_a241 ( + .I0(dividend_2[30]), + .I1(dividend_2[31]), + .O(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_dividend/twos_comp/simp_addp_a [30]) + ); + LUT2 #( + .INIT ( 4'h6 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_dividend/twos_comp/Mmux_simp_addp_a231 ( + .I0(dividend_2[2]), + .I1(dividend_2[31]), + .O(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_dividend/twos_comp/simp_addp_a [2]) + ); + LUT2 #( + .INIT ( 4'h6 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_dividend/twos_comp/Mmux_simp_addp_a221 ( + .I0(dividend_2[29]), + .I1(dividend_2[31]), + .O(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_dividend/twos_comp/simp_addp_a [29]) + ); + LUT2 #( + .INIT ( 4'h6 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_dividend/twos_comp/Mmux_simp_addp_a211 ( + .I0(dividend_2[28]), + .I1(dividend_2[31]), + .O(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_dividend/twos_comp/simp_addp_a [28]) + ); + LUT2 #( + .INIT ( 4'h6 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_dividend/twos_comp/Mmux_simp_addp_a201 ( + .I0(dividend_2[27]), + .I1(dividend_2[31]), + .O(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_dividend/twos_comp/simp_addp_a [27]) + ); + LUT2 #( + .INIT ( 4'h6 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_dividend/twos_comp/Mmux_simp_addp_a191 ( + .I0(dividend_2[26]), + .I1(dividend_2[31]), + .O(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_dividend/twos_comp/simp_addp_a [26]) + ); + LUT2 #( + .INIT ( 4'h6 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_dividend/twos_comp/Mmux_simp_addp_a181 ( + .I0(dividend_2[25]), + .I1(dividend_2[31]), + .O(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_dividend/twos_comp/simp_addp_a [25]) + ); + LUT2 #( + .INIT ( 4'h6 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_dividend/twos_comp/Mmux_simp_addp_a171 ( + .I0(dividend_2[24]), + .I1(dividend_2[31]), + .O(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_dividend/twos_comp/simp_addp_a [24]) + ); + LUT2 #( + .INIT ( 4'h6 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_dividend/twos_comp/Mmux_simp_addp_a161 ( + .I0(dividend_2[23]), + .I1(dividend_2[31]), + .O(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_dividend/twos_comp/simp_addp_a [23]) + ); + LUT2 #( + .INIT ( 4'h6 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_dividend/twos_comp/Mmux_simp_addp_a151 ( + .I0(dividend_2[22]), + .I1(dividend_2[31]), + .O(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_dividend/twos_comp/simp_addp_a [22]) + ); + LUT2 #( + .INIT ( 4'h6 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_dividend/twos_comp/Mmux_simp_addp_a141 ( + .I0(dividend_2[21]), + .I1(dividend_2[31]), + .O(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_dividend/twos_comp/simp_addp_a [21]) + ); + LUT2 #( + .INIT ( 4'h6 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_dividend/twos_comp/Mmux_simp_addp_a131 ( + .I0(dividend_2[20]), + .I1(dividend_2[31]), + .O(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_dividend/twos_comp/simp_addp_a [20]) + ); + LUT2 #( + .INIT ( 4'h6 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_dividend/twos_comp/Mmux_simp_addp_a121 ( + .I0(dividend_2[1]), + .I1(dividend_2[31]), + .O(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_dividend/twos_comp/simp_addp_a [1]) + ); + LUT2 #( + .INIT ( 4'h6 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_dividend/twos_comp/Mmux_simp_addp_a111 ( + .I0(dividend_2[19]), + .I1(dividend_2[31]), + .O(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_dividend/twos_comp/simp_addp_a [19]) + ); + LUT2 #( + .INIT ( 4'h6 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_dividend/twos_comp/Mmux_simp_addp_a101 ( + .I0(dividend_2[18]), + .I1(dividend_2[31]), + .O(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_dividend/twos_comp/simp_addp_a [18]) + ); + LUT2 #( + .INIT ( 4'h6 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_dividend/twos_comp/Mmux_simp_addp_a91 ( + .I0(dividend_2[17]), + .I1(dividend_2[31]), + .O(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_dividend/twos_comp/simp_addp_a [17]) + ); + LUT2 #( + .INIT ( 4'h6 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_dividend/twos_comp/Mmux_simp_addp_a81 ( + .I0(dividend_2[16]), + .I1(dividend_2[31]), + .O(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_dividend/twos_comp/simp_addp_a [16]) + ); + LUT2 #( + .INIT ( 4'h6 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_dividend/twos_comp/Mmux_simp_addp_a71 ( + .I0(dividend_2[15]), + .I1(dividend_2[31]), + .O(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_dividend/twos_comp/simp_addp_a [15]) + ); + LUT2 #( + .INIT ( 4'h6 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_dividend/twos_comp/Mmux_simp_addp_a61 ( + .I0(dividend_2[14]), + .I1(dividend_2[31]), + .O(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_dividend/twos_comp/simp_addp_a [14]) + ); + LUT2 #( + .INIT ( 4'h6 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_dividend/twos_comp/Mmux_simp_addp_a51 ( + .I0(dividend_2[13]), + .I1(dividend_2[31]), + .O(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_dividend/twos_comp/simp_addp_a [13]) + ); + LUT2 #( + .INIT ( 4'h6 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_dividend/twos_comp/Mmux_simp_addp_a41 ( + .I0(dividend_2[12]), + .I1(dividend_2[31]), + .O(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_dividend/twos_comp/simp_addp_a [12]) + ); + LUT2 #( + .INIT ( 4'h6 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_dividend/twos_comp/Mmux_simp_addp_a34 ( + .I0(dividend_2[11]), + .I1(dividend_2[31]), + .O(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_dividend/twos_comp/simp_addp_a [11]) + ); + LUT2 #( + .INIT ( 4'h6 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_dividend/twos_comp/Mmux_simp_addp_a25 ( + .I0(dividend_2[10]), + .I1(dividend_2[31]), + .O(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_dividend/twos_comp/simp_addp_a [10]) + ); + LUT2 #( + .INIT ( 4'h6 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/Mxor_quot_det_xo<0>1 ( + .I0(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sign_pipeline.sign_pipe/opt_has_pipe.pipe_33_0_1_5724 ), + .I1(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sign_pipeline.sign_pipe/opt_has_pipe.pipe_33_1_1_5725 ), + .O(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/quot_det ) + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.remd_not_fract.cmp_remd/twos_comp/q_i_0 ( + .C(clk), + .D(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.remd_not_fract.cmp_remd/twos_comp/s_i [0]), + .Q(fractional_5[0]) + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.remd_not_fract.cmp_remd/twos_comp/q_i_1 ( + .C(clk), + .D(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.remd_not_fract.cmp_remd/twos_comp/s_i [1]), + .Q(fractional_5[1]) + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.remd_not_fract.cmp_remd/twos_comp/q_i_2 ( + .C(clk), + .D(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.remd_not_fract.cmp_remd/twos_comp/s_i [2]), + .Q(fractional_5[2]) + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.remd_not_fract.cmp_remd/twos_comp/q_i_3 ( + .C(clk), + .D(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.remd_not_fract.cmp_remd/twos_comp/s_i [3]), + .Q(fractional_5[3]) + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.remd_not_fract.cmp_remd/twos_comp/q_i_4 ( + .C(clk), + .D(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.remd_not_fract.cmp_remd/twos_comp/s_i [4]), + .Q(fractional_5[4]) + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.remd_not_fract.cmp_remd/twos_comp/q_i_5 ( + .C(clk), + .D(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.remd_not_fract.cmp_remd/twos_comp/s_i [5]), + .Q(fractional_5[5]) + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.remd_not_fract.cmp_remd/twos_comp/q_i_6 ( + .C(clk), + .D(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.remd_not_fract.cmp_remd/twos_comp/s_i [6]), + .Q(fractional_5[6]) + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.remd_not_fract.cmp_remd/twos_comp/q_i_7 ( + .C(clk), + .D(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.remd_not_fract.cmp_remd/twos_comp/s_i [7]), + .Q(fractional_5[7]) + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.remd_not_fract.cmp_remd/twos_comp/q_i_8 ( + .C(clk), + .D(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.remd_not_fract.cmp_remd/twos_comp/s_i [8]), + .Q(fractional_5[8]) + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.remd_not_fract.cmp_remd/twos_comp/q_i_9 ( + .C(clk), + .D(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.remd_not_fract.cmp_remd/twos_comp/s_i [9]), + .Q(fractional_5[9]) + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.remd_not_fract.cmp_remd/twos_comp/q_i_10 ( + .C(clk), + .D(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.remd_not_fract.cmp_remd/twos_comp/s_i [10]), + .Q(fractional_5[10]) + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.remd_not_fract.cmp_remd/twos_comp/q_i_11 ( + .C(clk), + .D(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.remd_not_fract.cmp_remd/twos_comp/s_i [11]), + .Q(fractional_5[11]) + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.remd_not_fract.cmp_remd/twos_comp/q_i_12 ( + .C(clk), + .D(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.remd_not_fract.cmp_remd/twos_comp/s_i [12]), + .Q(fractional_5[12]) + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.remd_not_fract.cmp_remd/twos_comp/q_i_13 ( + .C(clk), + .D(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.remd_not_fract.cmp_remd/twos_comp/s_i [13]), + .Q(fractional_5[13]) + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.remd_not_fract.cmp_remd/twos_comp/q_i_14 ( + .C(clk), + .D(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.remd_not_fract.cmp_remd/twos_comp/s_i [14]), + .Q(fractional_5[14]) + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.remd_not_fract.cmp_remd/twos_comp/q_i_15 ( + .C(clk), + .D(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.remd_not_fract.cmp_remd/twos_comp/s_i [15]), + .Q(fractional_5[15]) + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.remd_not_fract.cmp_remd/twos_comp/q_i_16 ( + .C(clk), + .D(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.remd_not_fract.cmp_remd/twos_comp/s_i [16]), + .Q(fractional_5[16]) + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.remd_not_fract.cmp_remd/twos_comp/q_i_17 ( + .C(clk), + .D(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.remd_not_fract.cmp_remd/twos_comp/s_i [17]), + .Q(fractional_5[17]) + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.remd_not_fract.cmp_remd/twos_comp/q_i_18 ( + .C(clk), + .D(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.remd_not_fract.cmp_remd/twos_comp/s_i [18]), + .Q(fractional_5[18]) + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.remd_not_fract.cmp_remd/twos_comp/q_i_19 ( + .C(clk), + .D(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.remd_not_fract.cmp_remd/twos_comp/s_i [19]), + .Q(fractional_5[19]) + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.remd_not_fract.cmp_remd/twos_comp/q_i_20 ( + .C(clk), + .D(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.remd_not_fract.cmp_remd/twos_comp/s_i [20]), + .Q(fractional_5[20]) + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.remd_not_fract.cmp_remd/twos_comp/q_i_21 ( + .C(clk), + .D(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.remd_not_fract.cmp_remd/twos_comp/s_i [21]), + .Q(fractional_5[21]) + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.remd_not_fract.cmp_remd/twos_comp/q_i_22 ( + .C(clk), + .D(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.remd_not_fract.cmp_remd/twos_comp/s_i [22]), + .Q(fractional_5[22]) + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.remd_not_fract.cmp_remd/twos_comp/q_i_23 ( + .C(clk), + .D(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.remd_not_fract.cmp_remd/twos_comp/s_i [23]), + .Q(fractional_5[23]) + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.remd_not_fract.cmp_remd/twos_comp/Madd_s_i_cy<0> ( + .CI(\BU2/divide_by_zero ), + .DI(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sign_pipeline.sign_pipe/opt_has_pipe.pipe_33 [1]), + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.remd_not_fract.cmp_remd/twos_comp/Madd_s_i_cy<0>_rt_5722 ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.remd_not_fract.cmp_remd/twos_comp/Madd_s_i_cy [0]) + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.remd_not_fract.cmp_remd/twos_comp/Madd_s_i_xor<0> ( + .CI(\BU2/divide_by_zero ), + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.remd_not_fract.cmp_remd/twos_comp/Madd_s_i_cy<0>_rt_5722 ) +, + .O(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.remd_not_fract.cmp_remd/twos_comp/s_i [0]) + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.remd_not_fract.cmp_remd/twos_comp/Madd_s_i_cy<1> ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.remd_not_fract.cmp_remd/twos_comp/Madd_s_i_cy [0]), + .DI(\BU2/divide_by_zero ), + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.remd_not_fract.cmp_remd/twos_comp/simp_addp_a [1]), + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.remd_not_fract.cmp_remd/twos_comp/Madd_s_i_cy [1]) + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.remd_not_fract.cmp_remd/twos_comp/Madd_s_i_xor<1> ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.remd_not_fract.cmp_remd/twos_comp/Madd_s_i_cy [0]), + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.remd_not_fract.cmp_remd/twos_comp/simp_addp_a [1]), + .O(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.remd_not_fract.cmp_remd/twos_comp/s_i [1]) + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.remd_not_fract.cmp_remd/twos_comp/Madd_s_i_cy<2> ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.remd_not_fract.cmp_remd/twos_comp/Madd_s_i_cy [1]), + .DI(\BU2/divide_by_zero ), + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.remd_not_fract.cmp_remd/twos_comp/simp_addp_a [2]), + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.remd_not_fract.cmp_remd/twos_comp/Madd_s_i_cy [2]) + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.remd_not_fract.cmp_remd/twos_comp/Madd_s_i_xor<2> ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.remd_not_fract.cmp_remd/twos_comp/Madd_s_i_cy [1]), + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.remd_not_fract.cmp_remd/twos_comp/simp_addp_a [2]), + .O(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.remd_not_fract.cmp_remd/twos_comp/s_i [2]) + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.remd_not_fract.cmp_remd/twos_comp/Madd_s_i_cy<3> ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.remd_not_fract.cmp_remd/twos_comp/Madd_s_i_cy [2]), + .DI(\BU2/divide_by_zero ), + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.remd_not_fract.cmp_remd/twos_comp/simp_addp_a [3]), + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.remd_not_fract.cmp_remd/twos_comp/Madd_s_i_cy [3]) + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.remd_not_fract.cmp_remd/twos_comp/Madd_s_i_xor<3> ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.remd_not_fract.cmp_remd/twos_comp/Madd_s_i_cy [2]), + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.remd_not_fract.cmp_remd/twos_comp/simp_addp_a [3]), + .O(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.remd_not_fract.cmp_remd/twos_comp/s_i [3]) + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.remd_not_fract.cmp_remd/twos_comp/Madd_s_i_cy<4> ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.remd_not_fract.cmp_remd/twos_comp/Madd_s_i_cy [3]), + .DI(\BU2/divide_by_zero ), + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.remd_not_fract.cmp_remd/twos_comp/simp_addp_a [4]), + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.remd_not_fract.cmp_remd/twos_comp/Madd_s_i_cy [4]) + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.remd_not_fract.cmp_remd/twos_comp/Madd_s_i_xor<4> ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.remd_not_fract.cmp_remd/twos_comp/Madd_s_i_cy [3]), + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.remd_not_fract.cmp_remd/twos_comp/simp_addp_a [4]), + .O(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.remd_not_fract.cmp_remd/twos_comp/s_i [4]) + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.remd_not_fract.cmp_remd/twos_comp/Madd_s_i_cy<5> ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.remd_not_fract.cmp_remd/twos_comp/Madd_s_i_cy [4]), + .DI(\BU2/divide_by_zero ), + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.remd_not_fract.cmp_remd/twos_comp/simp_addp_a [5]), + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.remd_not_fract.cmp_remd/twos_comp/Madd_s_i_cy [5]) + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.remd_not_fract.cmp_remd/twos_comp/Madd_s_i_xor<5> ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.remd_not_fract.cmp_remd/twos_comp/Madd_s_i_cy [4]), + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.remd_not_fract.cmp_remd/twos_comp/simp_addp_a [5]), + .O(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.remd_not_fract.cmp_remd/twos_comp/s_i [5]) + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.remd_not_fract.cmp_remd/twos_comp/Madd_s_i_cy<6> ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.remd_not_fract.cmp_remd/twos_comp/Madd_s_i_cy [5]), + .DI(\BU2/divide_by_zero ), + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.remd_not_fract.cmp_remd/twos_comp/simp_addp_a [6]), + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.remd_not_fract.cmp_remd/twos_comp/Madd_s_i_cy [6]) + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.remd_not_fract.cmp_remd/twos_comp/Madd_s_i_xor<6> ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.remd_not_fract.cmp_remd/twos_comp/Madd_s_i_cy [5]), + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.remd_not_fract.cmp_remd/twos_comp/simp_addp_a [6]), + .O(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.remd_not_fract.cmp_remd/twos_comp/s_i [6]) + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.remd_not_fract.cmp_remd/twos_comp/Madd_s_i_cy<7> ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.remd_not_fract.cmp_remd/twos_comp/Madd_s_i_cy [6]), + .DI(\BU2/divide_by_zero ), + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.remd_not_fract.cmp_remd/twos_comp/simp_addp_a [7]), + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.remd_not_fract.cmp_remd/twos_comp/Madd_s_i_cy [7]) + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.remd_not_fract.cmp_remd/twos_comp/Madd_s_i_xor<7> ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.remd_not_fract.cmp_remd/twos_comp/Madd_s_i_cy [6]), + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.remd_not_fract.cmp_remd/twos_comp/simp_addp_a [7]), + .O(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.remd_not_fract.cmp_remd/twos_comp/s_i [7]) + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.remd_not_fract.cmp_remd/twos_comp/Madd_s_i_cy<8> ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.remd_not_fract.cmp_remd/twos_comp/Madd_s_i_cy [7]), + .DI(\BU2/divide_by_zero ), + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.remd_not_fract.cmp_remd/twos_comp/simp_addp_a [8]), + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.remd_not_fract.cmp_remd/twos_comp/Madd_s_i_cy [8]) + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.remd_not_fract.cmp_remd/twos_comp/Madd_s_i_xor<8> ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.remd_not_fract.cmp_remd/twos_comp/Madd_s_i_cy [7]), + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.remd_not_fract.cmp_remd/twos_comp/simp_addp_a [8]), + .O(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.remd_not_fract.cmp_remd/twos_comp/s_i [8]) + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.remd_not_fract.cmp_remd/twos_comp/Madd_s_i_cy<9> ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.remd_not_fract.cmp_remd/twos_comp/Madd_s_i_cy [8]), + .DI(\BU2/divide_by_zero ), + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.remd_not_fract.cmp_remd/twos_comp/simp_addp_a [9]), + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.remd_not_fract.cmp_remd/twos_comp/Madd_s_i_cy [9]) + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.remd_not_fract.cmp_remd/twos_comp/Madd_s_i_xor<9> ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.remd_not_fract.cmp_remd/twos_comp/Madd_s_i_cy [8]), + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.remd_not_fract.cmp_remd/twos_comp/simp_addp_a [9]), + .O(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.remd_not_fract.cmp_remd/twos_comp/s_i [9]) + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.remd_not_fract.cmp_remd/twos_comp/Madd_s_i_cy<10> ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.remd_not_fract.cmp_remd/twos_comp/Madd_s_i_cy [9]), + .DI(\BU2/divide_by_zero ), + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.remd_not_fract.cmp_remd/twos_comp/simp_addp_a [10]), + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.remd_not_fract.cmp_remd/twos_comp/Madd_s_i_cy [10]) + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.remd_not_fract.cmp_remd/twos_comp/Madd_s_i_xor<10> ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.remd_not_fract.cmp_remd/twos_comp/Madd_s_i_cy [9]), + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.remd_not_fract.cmp_remd/twos_comp/simp_addp_a [10]), + .O(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.remd_not_fract.cmp_remd/twos_comp/s_i [10]) + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.remd_not_fract.cmp_remd/twos_comp/Madd_s_i_cy<11> ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.remd_not_fract.cmp_remd/twos_comp/Madd_s_i_cy [10]), + .DI(\BU2/divide_by_zero ), + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.remd_not_fract.cmp_remd/twos_comp/simp_addp_a [11]), + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.remd_not_fract.cmp_remd/twos_comp/Madd_s_i_cy [11]) + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.remd_not_fract.cmp_remd/twos_comp/Madd_s_i_xor<11> ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.remd_not_fract.cmp_remd/twos_comp/Madd_s_i_cy [10]), + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.remd_not_fract.cmp_remd/twos_comp/simp_addp_a [11]), + .O(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.remd_not_fract.cmp_remd/twos_comp/s_i [11]) + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.remd_not_fract.cmp_remd/twos_comp/Madd_s_i_cy<12> ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.remd_not_fract.cmp_remd/twos_comp/Madd_s_i_cy [11]), + .DI(\BU2/divide_by_zero ), + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.remd_not_fract.cmp_remd/twos_comp/simp_addp_a [12]), + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.remd_not_fract.cmp_remd/twos_comp/Madd_s_i_cy [12]) + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.remd_not_fract.cmp_remd/twos_comp/Madd_s_i_xor<12> ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.remd_not_fract.cmp_remd/twos_comp/Madd_s_i_cy [11]), + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.remd_not_fract.cmp_remd/twos_comp/simp_addp_a [12]), + .O(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.remd_not_fract.cmp_remd/twos_comp/s_i [12]) + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.remd_not_fract.cmp_remd/twos_comp/Madd_s_i_cy<13> ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.remd_not_fract.cmp_remd/twos_comp/Madd_s_i_cy [12]), + .DI(\BU2/divide_by_zero ), + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.remd_not_fract.cmp_remd/twos_comp/simp_addp_a [13]), + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.remd_not_fract.cmp_remd/twos_comp/Madd_s_i_cy [13]) + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.remd_not_fract.cmp_remd/twos_comp/Madd_s_i_xor<13> ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.remd_not_fract.cmp_remd/twos_comp/Madd_s_i_cy [12]), + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.remd_not_fract.cmp_remd/twos_comp/simp_addp_a [13]), + .O(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.remd_not_fract.cmp_remd/twos_comp/s_i [13]) + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.remd_not_fract.cmp_remd/twos_comp/Madd_s_i_cy<14> ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.remd_not_fract.cmp_remd/twos_comp/Madd_s_i_cy [13]), + .DI(\BU2/divide_by_zero ), + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.remd_not_fract.cmp_remd/twos_comp/simp_addp_a [14]), + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.remd_not_fract.cmp_remd/twos_comp/Madd_s_i_cy [14]) + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.remd_not_fract.cmp_remd/twos_comp/Madd_s_i_xor<14> ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.remd_not_fract.cmp_remd/twos_comp/Madd_s_i_cy [13]), + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.remd_not_fract.cmp_remd/twos_comp/simp_addp_a [14]), + .O(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.remd_not_fract.cmp_remd/twos_comp/s_i [14]) + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.remd_not_fract.cmp_remd/twos_comp/Madd_s_i_cy<15> ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.remd_not_fract.cmp_remd/twos_comp/Madd_s_i_cy [14]), + .DI(\BU2/divide_by_zero ), + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.remd_not_fract.cmp_remd/twos_comp/simp_addp_a [15]), + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.remd_not_fract.cmp_remd/twos_comp/Madd_s_i_cy [15]) + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.remd_not_fract.cmp_remd/twos_comp/Madd_s_i_xor<15> ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.remd_not_fract.cmp_remd/twos_comp/Madd_s_i_cy [14]), + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.remd_not_fract.cmp_remd/twos_comp/simp_addp_a [15]), + .O(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.remd_not_fract.cmp_remd/twos_comp/s_i [15]) + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.remd_not_fract.cmp_remd/twos_comp/Madd_s_i_cy<16> ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.remd_not_fract.cmp_remd/twos_comp/Madd_s_i_cy [15]), + .DI(\BU2/divide_by_zero ), + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.remd_not_fract.cmp_remd/twos_comp/simp_addp_a [16]), + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.remd_not_fract.cmp_remd/twos_comp/Madd_s_i_cy [16]) + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.remd_not_fract.cmp_remd/twos_comp/Madd_s_i_xor<16> ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.remd_not_fract.cmp_remd/twos_comp/Madd_s_i_cy [15]), + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.remd_not_fract.cmp_remd/twos_comp/simp_addp_a [16]), + .O(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.remd_not_fract.cmp_remd/twos_comp/s_i [16]) + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.remd_not_fract.cmp_remd/twos_comp/Madd_s_i_cy<17> ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.remd_not_fract.cmp_remd/twos_comp/Madd_s_i_cy [16]), + .DI(\BU2/divide_by_zero ), + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.remd_not_fract.cmp_remd/twos_comp/simp_addp_a [17]), + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.remd_not_fract.cmp_remd/twos_comp/Madd_s_i_cy [17]) + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.remd_not_fract.cmp_remd/twos_comp/Madd_s_i_xor<17> ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.remd_not_fract.cmp_remd/twos_comp/Madd_s_i_cy [16]), + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.remd_not_fract.cmp_remd/twos_comp/simp_addp_a [17]), + .O(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.remd_not_fract.cmp_remd/twos_comp/s_i [17]) + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.remd_not_fract.cmp_remd/twos_comp/Madd_s_i_cy<18> ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.remd_not_fract.cmp_remd/twos_comp/Madd_s_i_cy [17]), + .DI(\BU2/divide_by_zero ), + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.remd_not_fract.cmp_remd/twos_comp/simp_addp_a [18]), + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.remd_not_fract.cmp_remd/twos_comp/Madd_s_i_cy [18]) + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.remd_not_fract.cmp_remd/twos_comp/Madd_s_i_xor<18> ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.remd_not_fract.cmp_remd/twos_comp/Madd_s_i_cy [17]), + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.remd_not_fract.cmp_remd/twos_comp/simp_addp_a [18]), + .O(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.remd_not_fract.cmp_remd/twos_comp/s_i [18]) + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.remd_not_fract.cmp_remd/twos_comp/Madd_s_i_cy<19> ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.remd_not_fract.cmp_remd/twos_comp/Madd_s_i_cy [18]), + .DI(\BU2/divide_by_zero ), + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.remd_not_fract.cmp_remd/twos_comp/simp_addp_a [19]), + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.remd_not_fract.cmp_remd/twos_comp/Madd_s_i_cy [19]) + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.remd_not_fract.cmp_remd/twos_comp/Madd_s_i_xor<19> ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.remd_not_fract.cmp_remd/twos_comp/Madd_s_i_cy [18]), + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.remd_not_fract.cmp_remd/twos_comp/simp_addp_a [19]), + .O(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.remd_not_fract.cmp_remd/twos_comp/s_i [19]) + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.remd_not_fract.cmp_remd/twos_comp/Madd_s_i_cy<20> ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.remd_not_fract.cmp_remd/twos_comp/Madd_s_i_cy [19]), + .DI(\BU2/divide_by_zero ), + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.remd_not_fract.cmp_remd/twos_comp/simp_addp_a [20]), + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.remd_not_fract.cmp_remd/twos_comp/Madd_s_i_cy [20]) + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.remd_not_fract.cmp_remd/twos_comp/Madd_s_i_xor<20> ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.remd_not_fract.cmp_remd/twos_comp/Madd_s_i_cy [19]), + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.remd_not_fract.cmp_remd/twos_comp/simp_addp_a [20]), + .O(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.remd_not_fract.cmp_remd/twos_comp/s_i [20]) + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.remd_not_fract.cmp_remd/twos_comp/Madd_s_i_cy<21> ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.remd_not_fract.cmp_remd/twos_comp/Madd_s_i_cy [20]), + .DI(\BU2/divide_by_zero ), + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.remd_not_fract.cmp_remd/twos_comp/simp_addp_a [21]), + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.remd_not_fract.cmp_remd/twos_comp/Madd_s_i_cy [21]) + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.remd_not_fract.cmp_remd/twos_comp/Madd_s_i_xor<21> ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.remd_not_fract.cmp_remd/twos_comp/Madd_s_i_cy [20]), + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.remd_not_fract.cmp_remd/twos_comp/simp_addp_a [21]), + .O(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.remd_not_fract.cmp_remd/twos_comp/s_i [21]) + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.remd_not_fract.cmp_remd/twos_comp/Madd_s_i_cy<22> ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.remd_not_fract.cmp_remd/twos_comp/Madd_s_i_cy [21]), + .DI(\BU2/divide_by_zero ), + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.remd_not_fract.cmp_remd/twos_comp/simp_addp_a [22]), + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.remd_not_fract.cmp_remd/twos_comp/Madd_s_i_cy [22]) + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.remd_not_fract.cmp_remd/twos_comp/Madd_s_i_xor<22> ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.remd_not_fract.cmp_remd/twos_comp/Madd_s_i_cy [21]), + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.remd_not_fract.cmp_remd/twos_comp/simp_addp_a [22]), + .O(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.remd_not_fract.cmp_remd/twos_comp/s_i [22]) + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.remd_not_fract.cmp_remd/twos_comp/Madd_s_i_xor<23> ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.remd_not_fract.cmp_remd/twos_comp/Madd_s_i_cy [22]), + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.remd_not_fract.cmp_remd/twos_comp/simp_addp_a [23]), + .O(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.remd_not_fract.cmp_remd/twos_comp/s_i [23]) + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.cmp_quot/twos_comp/q_i_0 ( + .C(clk), + .D(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.cmp_quot/twos_comp/s_i [0]), + .Q(quotient_4[0]) + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.cmp_quot/twos_comp/q_i_1 ( + .C(clk), + .D(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.cmp_quot/twos_comp/s_i [1]), + .Q(quotient_4[1]) + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.cmp_quot/twos_comp/q_i_2 ( + .C(clk), + .D(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.cmp_quot/twos_comp/s_i [2]), + .Q(quotient_4[2]) + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.cmp_quot/twos_comp/q_i_3 ( + .C(clk), + .D(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.cmp_quot/twos_comp/s_i [3]), + .Q(quotient_4[3]) + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.cmp_quot/twos_comp/q_i_4 ( + .C(clk), + .D(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.cmp_quot/twos_comp/s_i [4]), + .Q(quotient_4[4]) + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.cmp_quot/twos_comp/q_i_5 ( + .C(clk), + .D(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.cmp_quot/twos_comp/s_i [5]), + .Q(quotient_4[5]) + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.cmp_quot/twos_comp/q_i_6 ( + .C(clk), + .D(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.cmp_quot/twos_comp/s_i [6]), + .Q(quotient_4[6]) + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.cmp_quot/twos_comp/q_i_7 ( + .C(clk), + .D(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.cmp_quot/twos_comp/s_i [7]), + .Q(quotient_4[7]) + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.cmp_quot/twos_comp/q_i_8 ( + .C(clk), + .D(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.cmp_quot/twos_comp/s_i [8]), + .Q(quotient_4[8]) + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.cmp_quot/twos_comp/q_i_9 ( + .C(clk), + .D(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.cmp_quot/twos_comp/s_i [9]), + .Q(quotient_4[9]) + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.cmp_quot/twos_comp/q_i_10 ( + .C(clk), + .D(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.cmp_quot/twos_comp/s_i [10]), + .Q(quotient_4[10]) + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.cmp_quot/twos_comp/q_i_11 ( + .C(clk), + .D(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.cmp_quot/twos_comp/s_i [11]), + .Q(quotient_4[11]) + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.cmp_quot/twos_comp/q_i_12 ( + .C(clk), + .D(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.cmp_quot/twos_comp/s_i [12]), + .Q(quotient_4[12]) + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.cmp_quot/twos_comp/q_i_13 ( + .C(clk), + .D(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.cmp_quot/twos_comp/s_i [13]), + .Q(quotient_4[13]) + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.cmp_quot/twos_comp/q_i_14 ( + .C(clk), + .D(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.cmp_quot/twos_comp/s_i [14]), + .Q(quotient_4[14]) + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.cmp_quot/twos_comp/q_i_15 ( + .C(clk), + .D(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.cmp_quot/twos_comp/s_i [15]), + .Q(quotient_4[15]) + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.cmp_quot/twos_comp/q_i_16 ( + .C(clk), + .D(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.cmp_quot/twos_comp/s_i [16]), + .Q(quotient_4[16]) + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.cmp_quot/twos_comp/q_i_17 ( + .C(clk), + .D(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.cmp_quot/twos_comp/s_i [17]), + .Q(quotient_4[17]) + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.cmp_quot/twos_comp/q_i_18 ( + .C(clk), + .D(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.cmp_quot/twos_comp/s_i [18]), + .Q(quotient_4[18]) + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.cmp_quot/twos_comp/q_i_19 ( + .C(clk), + .D(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.cmp_quot/twos_comp/s_i [19]), + .Q(quotient_4[19]) + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.cmp_quot/twos_comp/q_i_20 ( + .C(clk), + .D(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.cmp_quot/twos_comp/s_i [20]), + .Q(quotient_4[20]) + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.cmp_quot/twos_comp/q_i_21 ( + .C(clk), + .D(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.cmp_quot/twos_comp/s_i [21]), + .Q(quotient_4[21]) + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.cmp_quot/twos_comp/q_i_22 ( + .C(clk), + .D(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.cmp_quot/twos_comp/s_i [22]), + .Q(quotient_4[22]) + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.cmp_quot/twos_comp/q_i_23 ( + .C(clk), + .D(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.cmp_quot/twos_comp/s_i [23]), + .Q(quotient_4[23]) + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.cmp_quot/twos_comp/q_i_24 ( + .C(clk), + .D(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.cmp_quot/twos_comp/s_i [24]), + .Q(quotient_4[24]) + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.cmp_quot/twos_comp/q_i_25 ( + .C(clk), + .D(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.cmp_quot/twos_comp/s_i [25]), + .Q(quotient_4[25]) + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.cmp_quot/twos_comp/q_i_26 ( + .C(clk), + .D(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.cmp_quot/twos_comp/s_i [26]), + .Q(quotient_4[26]) + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.cmp_quot/twos_comp/q_i_27 ( + .C(clk), + .D(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.cmp_quot/twos_comp/s_i [27]), + .Q(quotient_4[27]) + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.cmp_quot/twos_comp/q_i_28 ( + .C(clk), + .D(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.cmp_quot/twos_comp/s_i [28]), + .Q(quotient_4[28]) + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.cmp_quot/twos_comp/q_i_29 ( + .C(clk), + .D(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.cmp_quot/twos_comp/s_i [29]), + .Q(quotient_4[29]) + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.cmp_quot/twos_comp/q_i_30 ( + .C(clk), + .D(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.cmp_quot/twos_comp/s_i [30]), + .Q(quotient_4[30]) + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.cmp_quot/twos_comp/q_i_31 ( + .C(clk), + .D(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.cmp_quot/twos_comp/s_i [31]), + .Q(quotient_4[31]) + ); + MUXCY \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.cmp_quot/twos_comp/Madd_s_i_cy<0> ( + .CI(\BU2/divide_by_zero ), + .DI(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/quot_det ), + .S(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.cmp_quot/twos_comp/Madd_s_i_cy<0>_rt_5650 ), + .O(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.cmp_quot/twos_comp/Madd_s_i_cy [0]) + ); + XORCY \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.cmp_quot/twos_comp/Madd_s_i_xor<0> ( + .CI(\BU2/divide_by_zero ), + .LI(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.cmp_quot/twos_comp/Madd_s_i_cy<0>_rt_5650 ), + .O(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.cmp_quot/twos_comp/s_i [0]) + ); + MUXCY \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.cmp_quot/twos_comp/Madd_s_i_cy<1> ( + .CI(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.cmp_quot/twos_comp/Madd_s_i_cy [0]), + .DI(\BU2/divide_by_zero ), + .S(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.cmp_quot/twos_comp/simp_addp_a [1]), + .O(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.cmp_quot/twos_comp/Madd_s_i_cy [1]) + ); + XORCY \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.cmp_quot/twos_comp/Madd_s_i_xor<1> ( + .CI(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.cmp_quot/twos_comp/Madd_s_i_cy [0]), + .LI(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.cmp_quot/twos_comp/simp_addp_a [1]), + .O(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.cmp_quot/twos_comp/s_i [1]) + ); + MUXCY \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.cmp_quot/twos_comp/Madd_s_i_cy<2> ( + .CI(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.cmp_quot/twos_comp/Madd_s_i_cy [1]), + .DI(\BU2/divide_by_zero ), + .S(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.cmp_quot/twos_comp/simp_addp_a [2]), + .O(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.cmp_quot/twos_comp/Madd_s_i_cy [2]) + ); + XORCY \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.cmp_quot/twos_comp/Madd_s_i_xor<2> ( + .CI(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.cmp_quot/twos_comp/Madd_s_i_cy [1]), + .LI(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.cmp_quot/twos_comp/simp_addp_a [2]), + .O(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.cmp_quot/twos_comp/s_i [2]) + ); + MUXCY \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.cmp_quot/twos_comp/Madd_s_i_cy<3> ( + .CI(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.cmp_quot/twos_comp/Madd_s_i_cy [2]), + .DI(\BU2/divide_by_zero ), + .S(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.cmp_quot/twos_comp/simp_addp_a [3]), + .O(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.cmp_quot/twos_comp/Madd_s_i_cy [3]) + ); + XORCY \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.cmp_quot/twos_comp/Madd_s_i_xor<3> ( + .CI(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.cmp_quot/twos_comp/Madd_s_i_cy [2]), + .LI(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.cmp_quot/twos_comp/simp_addp_a [3]), + .O(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.cmp_quot/twos_comp/s_i [3]) + ); + MUXCY \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.cmp_quot/twos_comp/Madd_s_i_cy<4> ( + .CI(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.cmp_quot/twos_comp/Madd_s_i_cy [3]), + .DI(\BU2/divide_by_zero ), + .S(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.cmp_quot/twos_comp/simp_addp_a [4]), + .O(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.cmp_quot/twos_comp/Madd_s_i_cy [4]) + ); + XORCY \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.cmp_quot/twos_comp/Madd_s_i_xor<4> ( + .CI(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.cmp_quot/twos_comp/Madd_s_i_cy [3]), + .LI(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.cmp_quot/twos_comp/simp_addp_a [4]), + .O(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.cmp_quot/twos_comp/s_i [4]) + ); + MUXCY \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.cmp_quot/twos_comp/Madd_s_i_cy<5> ( + .CI(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.cmp_quot/twos_comp/Madd_s_i_cy [4]), + .DI(\BU2/divide_by_zero ), + .S(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.cmp_quot/twos_comp/simp_addp_a [5]), + .O(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.cmp_quot/twos_comp/Madd_s_i_cy [5]) + ); + XORCY \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.cmp_quot/twos_comp/Madd_s_i_xor<5> ( + .CI(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.cmp_quot/twos_comp/Madd_s_i_cy [4]), + .LI(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.cmp_quot/twos_comp/simp_addp_a [5]), + .O(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.cmp_quot/twos_comp/s_i [5]) + ); + MUXCY \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.cmp_quot/twos_comp/Madd_s_i_cy<6> ( + .CI(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.cmp_quot/twos_comp/Madd_s_i_cy [5]), + .DI(\BU2/divide_by_zero ), + .S(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.cmp_quot/twos_comp/simp_addp_a [6]), + .O(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.cmp_quot/twos_comp/Madd_s_i_cy [6]) + ); + XORCY \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.cmp_quot/twos_comp/Madd_s_i_xor<6> ( + .CI(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.cmp_quot/twos_comp/Madd_s_i_cy [5]), + .LI(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.cmp_quot/twos_comp/simp_addp_a [6]), + .O(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.cmp_quot/twos_comp/s_i [6]) + ); + MUXCY \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.cmp_quot/twos_comp/Madd_s_i_cy<7> ( + .CI(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.cmp_quot/twos_comp/Madd_s_i_cy [6]), + .DI(\BU2/divide_by_zero ), + .S(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.cmp_quot/twos_comp/simp_addp_a [7]), + .O(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.cmp_quot/twos_comp/Madd_s_i_cy [7]) + ); + XORCY \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.cmp_quot/twos_comp/Madd_s_i_xor<7> ( + .CI(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.cmp_quot/twos_comp/Madd_s_i_cy [6]), + .LI(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.cmp_quot/twos_comp/simp_addp_a [7]), + .O(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.cmp_quot/twos_comp/s_i [7]) + ); + MUXCY \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.cmp_quot/twos_comp/Madd_s_i_cy<8> ( + .CI(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.cmp_quot/twos_comp/Madd_s_i_cy [7]), + .DI(\BU2/divide_by_zero ), + .S(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.cmp_quot/twos_comp/simp_addp_a [8]), + .O(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.cmp_quot/twos_comp/Madd_s_i_cy [8]) + ); + XORCY \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.cmp_quot/twos_comp/Madd_s_i_xor<8> ( + .CI(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.cmp_quot/twos_comp/Madd_s_i_cy [7]), + .LI(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.cmp_quot/twos_comp/simp_addp_a [8]), + .O(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.cmp_quot/twos_comp/s_i [8]) + ); + MUXCY \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.cmp_quot/twos_comp/Madd_s_i_cy<9> ( + .CI(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.cmp_quot/twos_comp/Madd_s_i_cy [8]), + .DI(\BU2/divide_by_zero ), + .S(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.cmp_quot/twos_comp/simp_addp_a [9]), + .O(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.cmp_quot/twos_comp/Madd_s_i_cy [9]) + ); + XORCY \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.cmp_quot/twos_comp/Madd_s_i_xor<9> ( + .CI(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.cmp_quot/twos_comp/Madd_s_i_cy [8]), + .LI(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.cmp_quot/twos_comp/simp_addp_a [9]), + .O(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.cmp_quot/twos_comp/s_i [9]) + ); + MUXCY \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.cmp_quot/twos_comp/Madd_s_i_cy<10> ( + .CI(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.cmp_quot/twos_comp/Madd_s_i_cy [9]), + .DI(\BU2/divide_by_zero ), + .S(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.cmp_quot/twos_comp/simp_addp_a [10]), + .O(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.cmp_quot/twos_comp/Madd_s_i_cy [10]) + ); + XORCY \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.cmp_quot/twos_comp/Madd_s_i_xor<10> ( + .CI(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.cmp_quot/twos_comp/Madd_s_i_cy [9]), + .LI(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.cmp_quot/twos_comp/simp_addp_a [10]), + .O(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.cmp_quot/twos_comp/s_i [10]) + ); + MUXCY \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.cmp_quot/twos_comp/Madd_s_i_cy<11> ( + .CI(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.cmp_quot/twos_comp/Madd_s_i_cy [10]), + .DI(\BU2/divide_by_zero ), + .S(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.cmp_quot/twos_comp/simp_addp_a [11]), + .O(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.cmp_quot/twos_comp/Madd_s_i_cy [11]) + ); + XORCY \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.cmp_quot/twos_comp/Madd_s_i_xor<11> ( + .CI(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.cmp_quot/twos_comp/Madd_s_i_cy [10]), + .LI(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.cmp_quot/twos_comp/simp_addp_a [11]), + .O(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.cmp_quot/twos_comp/s_i [11]) + ); + MUXCY \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.cmp_quot/twos_comp/Madd_s_i_cy<12> ( + .CI(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.cmp_quot/twos_comp/Madd_s_i_cy [11]), + .DI(\BU2/divide_by_zero ), + .S(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.cmp_quot/twos_comp/simp_addp_a [12]), + .O(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.cmp_quot/twos_comp/Madd_s_i_cy [12]) + ); + XORCY \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.cmp_quot/twos_comp/Madd_s_i_xor<12> ( + .CI(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.cmp_quot/twos_comp/Madd_s_i_cy [11]), + .LI(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.cmp_quot/twos_comp/simp_addp_a [12]), + .O(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.cmp_quot/twos_comp/s_i [12]) + ); + MUXCY \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.cmp_quot/twos_comp/Madd_s_i_cy<13> ( + .CI(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.cmp_quot/twos_comp/Madd_s_i_cy [12]), + .DI(\BU2/divide_by_zero ), + .S(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.cmp_quot/twos_comp/simp_addp_a [13]), + .O(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.cmp_quot/twos_comp/Madd_s_i_cy [13]) + ); + XORCY \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.cmp_quot/twos_comp/Madd_s_i_xor<13> ( + .CI(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.cmp_quot/twos_comp/Madd_s_i_cy [12]), + .LI(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.cmp_quot/twos_comp/simp_addp_a [13]), + .O(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.cmp_quot/twos_comp/s_i [13]) + ); + MUXCY \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.cmp_quot/twos_comp/Madd_s_i_cy<14> ( + .CI(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.cmp_quot/twos_comp/Madd_s_i_cy [13]), + .DI(\BU2/divide_by_zero ), + .S(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.cmp_quot/twos_comp/simp_addp_a [14]), + .O(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.cmp_quot/twos_comp/Madd_s_i_cy [14]) + ); + XORCY \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.cmp_quot/twos_comp/Madd_s_i_xor<14> ( + .CI(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.cmp_quot/twos_comp/Madd_s_i_cy [13]), + .LI(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.cmp_quot/twos_comp/simp_addp_a [14]), + .O(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.cmp_quot/twos_comp/s_i [14]) + ); + MUXCY \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.cmp_quot/twos_comp/Madd_s_i_cy<15> ( + .CI(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.cmp_quot/twos_comp/Madd_s_i_cy [14]), + .DI(\BU2/divide_by_zero ), + .S(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.cmp_quot/twos_comp/simp_addp_a [15]), + .O(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.cmp_quot/twos_comp/Madd_s_i_cy [15]) + ); + XORCY \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.cmp_quot/twos_comp/Madd_s_i_xor<15> ( + .CI(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.cmp_quot/twos_comp/Madd_s_i_cy [14]), + .LI(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.cmp_quot/twos_comp/simp_addp_a [15]), + .O(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.cmp_quot/twos_comp/s_i [15]) + ); + MUXCY \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.cmp_quot/twos_comp/Madd_s_i_cy<16> ( + .CI(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.cmp_quot/twos_comp/Madd_s_i_cy [15]), + .DI(\BU2/divide_by_zero ), + .S(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.cmp_quot/twos_comp/simp_addp_a [16]), + .O(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.cmp_quot/twos_comp/Madd_s_i_cy [16]) + ); + XORCY \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.cmp_quot/twos_comp/Madd_s_i_xor<16> ( + .CI(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.cmp_quot/twos_comp/Madd_s_i_cy [15]), + .LI(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.cmp_quot/twos_comp/simp_addp_a [16]), + .O(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.cmp_quot/twos_comp/s_i [16]) + ); + MUXCY \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.cmp_quot/twos_comp/Madd_s_i_cy<17> ( + .CI(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.cmp_quot/twos_comp/Madd_s_i_cy [16]), + .DI(\BU2/divide_by_zero ), + .S(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.cmp_quot/twos_comp/simp_addp_a [17]), + .O(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.cmp_quot/twos_comp/Madd_s_i_cy [17]) + ); + XORCY \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.cmp_quot/twos_comp/Madd_s_i_xor<17> ( + .CI(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.cmp_quot/twos_comp/Madd_s_i_cy [16]), + .LI(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.cmp_quot/twos_comp/simp_addp_a [17]), + .O(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.cmp_quot/twos_comp/s_i [17]) + ); + MUXCY \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.cmp_quot/twos_comp/Madd_s_i_cy<18> ( + .CI(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.cmp_quot/twos_comp/Madd_s_i_cy [17]), + .DI(\BU2/divide_by_zero ), + .S(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.cmp_quot/twos_comp/simp_addp_a [18]), + .O(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.cmp_quot/twos_comp/Madd_s_i_cy [18]) + ); + XORCY \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.cmp_quot/twos_comp/Madd_s_i_xor<18> ( + .CI(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.cmp_quot/twos_comp/Madd_s_i_cy [17]), + .LI(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.cmp_quot/twos_comp/simp_addp_a [18]), + .O(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.cmp_quot/twos_comp/s_i [18]) + ); + MUXCY \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.cmp_quot/twos_comp/Madd_s_i_cy<19> ( + .CI(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.cmp_quot/twos_comp/Madd_s_i_cy [18]), + .DI(\BU2/divide_by_zero ), + .S(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.cmp_quot/twos_comp/simp_addp_a [19]), + .O(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.cmp_quot/twos_comp/Madd_s_i_cy [19]) + ); + XORCY \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.cmp_quot/twos_comp/Madd_s_i_xor<19> ( + .CI(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.cmp_quot/twos_comp/Madd_s_i_cy [18]), + .LI(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.cmp_quot/twos_comp/simp_addp_a [19]), + .O(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.cmp_quot/twos_comp/s_i [19]) + ); + MUXCY \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.cmp_quot/twos_comp/Madd_s_i_cy<20> ( + .CI(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.cmp_quot/twos_comp/Madd_s_i_cy [19]), + .DI(\BU2/divide_by_zero ), + .S(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.cmp_quot/twos_comp/simp_addp_a [20]), + .O(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.cmp_quot/twos_comp/Madd_s_i_cy [20]) + ); + XORCY \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.cmp_quot/twos_comp/Madd_s_i_xor<20> ( + .CI(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.cmp_quot/twos_comp/Madd_s_i_cy [19]), + .LI(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.cmp_quot/twos_comp/simp_addp_a [20]), + .O(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.cmp_quot/twos_comp/s_i [20]) + ); + MUXCY \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.cmp_quot/twos_comp/Madd_s_i_cy<21> ( + .CI(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.cmp_quot/twos_comp/Madd_s_i_cy [20]), + .DI(\BU2/divide_by_zero ), + .S(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.cmp_quot/twos_comp/simp_addp_a [21]), + .O(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.cmp_quot/twos_comp/Madd_s_i_cy [21]) + ); + XORCY \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.cmp_quot/twos_comp/Madd_s_i_xor<21> ( + .CI(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.cmp_quot/twos_comp/Madd_s_i_cy [20]), + .LI(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.cmp_quot/twos_comp/simp_addp_a [21]), + .O(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.cmp_quot/twos_comp/s_i [21]) + ); + MUXCY \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.cmp_quot/twos_comp/Madd_s_i_cy<22> ( + .CI(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.cmp_quot/twos_comp/Madd_s_i_cy [21]), + .DI(\BU2/divide_by_zero ), + .S(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.cmp_quot/twos_comp/simp_addp_a [22]), + .O(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.cmp_quot/twos_comp/Madd_s_i_cy [22]) + ); + XORCY \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.cmp_quot/twos_comp/Madd_s_i_xor<22> ( + .CI(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.cmp_quot/twos_comp/Madd_s_i_cy [21]), + .LI(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.cmp_quot/twos_comp/simp_addp_a [22]), + .O(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.cmp_quot/twos_comp/s_i [22]) + ); + MUXCY \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.cmp_quot/twos_comp/Madd_s_i_cy<23> ( + .CI(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.cmp_quot/twos_comp/Madd_s_i_cy [22]), + .DI(\BU2/divide_by_zero ), + .S(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.cmp_quot/twos_comp/simp_addp_a [23]), + .O(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.cmp_quot/twos_comp/Madd_s_i_cy [23]) + ); + XORCY \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.cmp_quot/twos_comp/Madd_s_i_xor<23> ( + .CI(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.cmp_quot/twos_comp/Madd_s_i_cy [22]), + .LI(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.cmp_quot/twos_comp/simp_addp_a [23]), + .O(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.cmp_quot/twos_comp/s_i [23]) + ); + MUXCY \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.cmp_quot/twos_comp/Madd_s_i_cy<24> ( + .CI(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.cmp_quot/twos_comp/Madd_s_i_cy [23]), + .DI(\BU2/divide_by_zero ), + .S(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.cmp_quot/twos_comp/simp_addp_a [24]), + .O(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.cmp_quot/twos_comp/Madd_s_i_cy [24]) + ); + XORCY \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.cmp_quot/twos_comp/Madd_s_i_xor<24> ( + .CI(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.cmp_quot/twos_comp/Madd_s_i_cy [23]), + .LI(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.cmp_quot/twos_comp/simp_addp_a [24]), + .O(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.cmp_quot/twos_comp/s_i [24]) + ); + MUXCY \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.cmp_quot/twos_comp/Madd_s_i_cy<25> ( + .CI(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.cmp_quot/twos_comp/Madd_s_i_cy [24]), + .DI(\BU2/divide_by_zero ), + .S(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.cmp_quot/twos_comp/simp_addp_a [25]), + .O(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.cmp_quot/twos_comp/Madd_s_i_cy [25]) + ); + XORCY \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.cmp_quot/twos_comp/Madd_s_i_xor<25> ( + .CI(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.cmp_quot/twos_comp/Madd_s_i_cy [24]), + .LI(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.cmp_quot/twos_comp/simp_addp_a [25]), + .O(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.cmp_quot/twos_comp/s_i [25]) + ); + MUXCY \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.cmp_quot/twos_comp/Madd_s_i_cy<26> ( + .CI(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.cmp_quot/twos_comp/Madd_s_i_cy [25]), + .DI(\BU2/divide_by_zero ), + .S(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.cmp_quot/twos_comp/simp_addp_a [26]), + .O(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.cmp_quot/twos_comp/Madd_s_i_cy [26]) + ); + XORCY \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.cmp_quot/twos_comp/Madd_s_i_xor<26> ( + .CI(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.cmp_quot/twos_comp/Madd_s_i_cy [25]), + .LI(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.cmp_quot/twos_comp/simp_addp_a [26]), + .O(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.cmp_quot/twos_comp/s_i [26]) + ); + MUXCY \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.cmp_quot/twos_comp/Madd_s_i_cy<27> ( + .CI(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.cmp_quot/twos_comp/Madd_s_i_cy [26]), + .DI(\BU2/divide_by_zero ), + .S(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.cmp_quot/twos_comp/simp_addp_a [27]), + .O(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.cmp_quot/twos_comp/Madd_s_i_cy [27]) + ); + XORCY \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.cmp_quot/twos_comp/Madd_s_i_xor<27> ( + .CI(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.cmp_quot/twos_comp/Madd_s_i_cy [26]), + .LI(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.cmp_quot/twos_comp/simp_addp_a [27]), + .O(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.cmp_quot/twos_comp/s_i [27]) + ); + MUXCY \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.cmp_quot/twos_comp/Madd_s_i_cy<28> ( + .CI(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.cmp_quot/twos_comp/Madd_s_i_cy [27]), + .DI(\BU2/divide_by_zero ), + .S(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.cmp_quot/twos_comp/simp_addp_a [28]), + .O(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.cmp_quot/twos_comp/Madd_s_i_cy [28]) + ); + XORCY \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.cmp_quot/twos_comp/Madd_s_i_xor<28> ( + .CI(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.cmp_quot/twos_comp/Madd_s_i_cy [27]), + .LI(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.cmp_quot/twos_comp/simp_addp_a [28]), + .O(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.cmp_quot/twos_comp/s_i [28]) + ); + MUXCY \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.cmp_quot/twos_comp/Madd_s_i_cy<29> ( + .CI(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.cmp_quot/twos_comp/Madd_s_i_cy [28]), + .DI(\BU2/divide_by_zero ), + .S(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.cmp_quot/twos_comp/simp_addp_a [29]), + .O(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.cmp_quot/twos_comp/Madd_s_i_cy [29]) + ); + XORCY \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.cmp_quot/twos_comp/Madd_s_i_xor<29> ( + .CI(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.cmp_quot/twos_comp/Madd_s_i_cy [28]), + .LI(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.cmp_quot/twos_comp/simp_addp_a [29]), + .O(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.cmp_quot/twos_comp/s_i [29]) + ); + MUXCY \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.cmp_quot/twos_comp/Madd_s_i_cy<30> ( + .CI(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.cmp_quot/twos_comp/Madd_s_i_cy [29]), + .DI(\BU2/divide_by_zero ), + .S(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.cmp_quot/twos_comp/simp_addp_a [30]), + .O(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.cmp_quot/twos_comp/Madd_s_i_cy [30]) + ); + XORCY \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.cmp_quot/twos_comp/Madd_s_i_xor<30> ( + .CI(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.cmp_quot/twos_comp/Madd_s_i_cy [29]), + .LI(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.cmp_quot/twos_comp/simp_addp_a [30]), + .O(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.cmp_quot/twos_comp/s_i [30]) + ); + XORCY \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.cmp_quot/twos_comp/Madd_s_i_xor<31> ( + .CI(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.cmp_quot/twos_comp/Madd_s_i_cy [30]), + .LI(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.cmp_quot/twos_comp/simp_addp_a [31]), + .O(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/signed_output.cmp_quot/twos_comp/s_i [31]) + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/remd_output.adsu_sel2/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_0 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/remd_output.adsu_sel2/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple [0]) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/remd_output.adsu_sel2/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q [0]) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/remd_output.adsu_sel2/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_1 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/remd_output.adsu_sel2/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple [1]) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/remd_output.adsu_sel2/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q [1]) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/remd_output.adsu_sel2/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_2 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/remd_output.adsu_sel2/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple [2]) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/remd_output.adsu_sel2/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q [2]) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/remd_output.adsu_sel2/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_3 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/remd_output.adsu_sel2/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple [3]) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/remd_output.adsu_sel2/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q [3]) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/remd_output.adsu_sel2/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_4 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/remd_output.adsu_sel2/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple [4]) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/remd_output.adsu_sel2/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q [4]) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/remd_output.adsu_sel2/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_5 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/remd_output.adsu_sel2/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple [5]) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/remd_output.adsu_sel2/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q [5]) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/remd_output.adsu_sel2/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_6 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/remd_output.adsu_sel2/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple [6]) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/remd_output.adsu_sel2/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q [6]) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/remd_output.adsu_sel2/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_7 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/remd_output.adsu_sel2/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple [7]) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/remd_output.adsu_sel2/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q [7]) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/remd_output.adsu_sel2/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_8 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/remd_output.adsu_sel2/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple [8]) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/remd_output.adsu_sel2/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q [8]) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/remd_output.adsu_sel2/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_9 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/remd_output.adsu_sel2/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple [9]) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/remd_output.adsu_sel2/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q [9]) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/remd_output.adsu_sel2/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_10 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/remd_output.adsu_sel2/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple [10]) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/remd_output.adsu_sel2/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q [10]) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/remd_output.adsu_sel2/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_11 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/remd_output.adsu_sel2/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple [11]) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/remd_output.adsu_sel2/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q [11]) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/remd_output.adsu_sel2/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_12 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/remd_output.adsu_sel2/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple [12]) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/remd_output.adsu_sel2/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q [12]) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/remd_output.adsu_sel2/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_13 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/remd_output.adsu_sel2/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple [13]) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/remd_output.adsu_sel2/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q [13]) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/remd_output.adsu_sel2/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_14 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/remd_output.adsu_sel2/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple [14]) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/remd_output.adsu_sel2/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q [14]) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/remd_output.adsu_sel2/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_15 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/remd_output.adsu_sel2/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple [15]) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/remd_output.adsu_sel2/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q [15]) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/remd_output.adsu_sel2/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_16 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/remd_output.adsu_sel2/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple [16]) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/remd_output.adsu_sel2/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q [16]) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/remd_output.adsu_sel2/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_17 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/remd_output.adsu_sel2/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple [17]) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/remd_output.adsu_sel2/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q [17]) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/remd_output.adsu_sel2/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_18 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/remd_output.adsu_sel2/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple [18]) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/remd_output.adsu_sel2/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q [18]) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/remd_output.adsu_sel2/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_19 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/remd_output.adsu_sel2/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple [19]) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/remd_output.adsu_sel2/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q [19]) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/remd_output.adsu_sel2/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_20 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/remd_output.adsu_sel2/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple [20]) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/remd_output.adsu_sel2/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q [20]) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/remd_output.adsu_sel2/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_21 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/remd_output.adsu_sel2/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple [21]) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/remd_output.adsu_sel2/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q [21]) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/remd_output.adsu_sel2/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_22 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/remd_output.adsu_sel2/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple [22]) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/remd_output.adsu_sel2/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q [22]) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/remd_output.adsu_sel2/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_23 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/remd_output.adsu_sel2/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple [23]) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/remd_output.adsu_sel2/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q [23]) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/remd_output.adsu_sel2/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_24 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/remd_output.adsu_sel2/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple [24]) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/remd_output.adsu_sel2/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q [24]) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/remd_output.adsu_sel2/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q_c_out.i_simple.add_q_cout.q_c_outreg/opt_has_pipe.first_q_0 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/remd_output.adsu_sel2/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple [24]) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/remd_output.adsu_sel2/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q_c_out.i_simple.add_q_cout.q_c_outreg/opt_has_pipe.first_q ) + + ); + MULT_AND + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/remd_output.adsu_sel2/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_bypass.i_bypass_other.i_di_b_variable.i_gt_1.multandgen[0].carrymultand ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/final_div.del_end_divisor/opt_has_pipe.first_q [0]), + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24>_0 ) +, + .LO +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/remd_output.adsu_sel2/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.di [0]) + + ); + MULT_AND + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/remd_output.adsu_sel2/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_bypass.i_bypass_other.i_di_b_variable.i_gt_1.multandgen[1].carrymultand ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/final_div.del_end_divisor/opt_has_pipe.first_q [1]), + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24>_0 ) +, + .LO +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/remd_output.adsu_sel2/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.di [1]) + + ); + MULT_AND + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/remd_output.adsu_sel2/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_bypass.i_bypass_other.i_di_b_variable.i_gt_1.multandgen[2].carrymultand ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/final_div.del_end_divisor/opt_has_pipe.first_q [2]), + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24>_0 ) +, + .LO +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/remd_output.adsu_sel2/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.di [2]) + + ); + MULT_AND + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/remd_output.adsu_sel2/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_bypass.i_bypass_other.i_di_b_variable.i_gt_1.multandgen[3].carrymultand ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/final_div.del_end_divisor/opt_has_pipe.first_q [3]), + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24>_0 ) +, + .LO +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/remd_output.adsu_sel2/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.di [3]) + + ); + MULT_AND + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/remd_output.adsu_sel2/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_bypass.i_bypass_other.i_di_b_variable.i_gt_1.multandgen[4].carrymultand ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/final_div.del_end_divisor/opt_has_pipe.first_q [4]), + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24>_0 ) +, + .LO +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/remd_output.adsu_sel2/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.di [4]) + + ); + MULT_AND + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/remd_output.adsu_sel2/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_bypass.i_bypass_other.i_di_b_variable.i_gt_1.multandgen[5].carrymultand ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/final_div.del_end_divisor/opt_has_pipe.first_q [5]), + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24>_0 ) +, + .LO +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/remd_output.adsu_sel2/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.di [5]) + + ); + MULT_AND + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/remd_output.adsu_sel2/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_bypass.i_bypass_other.i_di_b_variable.i_gt_1.multandgen[6].carrymultand ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/final_div.del_end_divisor/opt_has_pipe.first_q [6]), + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24>_0 ) +, + .LO +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/remd_output.adsu_sel2/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.di [6]) + + ); + MULT_AND + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/remd_output.adsu_sel2/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_bypass.i_bypass_other.i_di_b_variable.i_gt_1.multandgen[7].carrymultand ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/final_div.del_end_divisor/opt_has_pipe.first_q [7]), + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24>_0 ) +, + .LO +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/remd_output.adsu_sel2/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.di [7]) + + ); + MULT_AND + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/remd_output.adsu_sel2/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_bypass.i_bypass_other.i_di_b_variable.i_gt_1.multandgen[8].carrymultand ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/final_div.del_end_divisor/opt_has_pipe.first_q [8]), + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24>_0 ) +, + .LO +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/remd_output.adsu_sel2/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.di [8]) + + ); + MULT_AND + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/remd_output.adsu_sel2/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_bypass.i_bypass_other.i_di_b_variable.i_gt_1.multandgen[9].carrymultand ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/final_div.del_end_divisor/opt_has_pipe.first_q [9]), + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24>_0 ) +, + .LO +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/remd_output.adsu_sel2/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.di [9]) + + ); + MULT_AND + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/remd_output.adsu_sel2/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_bypass.i_bypass_other.i_di_b_variable.i_gt_1.multandgen[10].carrymultand ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/final_div.del_end_divisor/opt_has_pipe.first_q [10]), + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24>_0 ) +, + .LO +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/remd_output.adsu_sel2/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.di [10]) + + ); + MULT_AND + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/remd_output.adsu_sel2/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_bypass.i_bypass_other.i_di_b_variable.i_gt_1.multandgen[11].carrymultand ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/final_div.del_end_divisor/opt_has_pipe.first_q [11]), + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .LO +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/remd_output.adsu_sel2/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.di [11]) + + ); + MULT_AND + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/remd_output.adsu_sel2/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_bypass.i_bypass_other.i_di_b_variable.i_gt_1.multandgen[12].carrymultand ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/final_div.del_end_divisor/opt_has_pipe.first_q [12]), + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .LO +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/remd_output.adsu_sel2/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.di [12]) + + ); + MULT_AND + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/remd_output.adsu_sel2/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_bypass.i_bypass_other.i_di_b_variable.i_gt_1.multandgen[13].carrymultand ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/final_div.del_end_divisor/opt_has_pipe.first_q [13]), + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .LO +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/remd_output.adsu_sel2/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.di [13]) + + ); + MULT_AND + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/remd_output.adsu_sel2/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_bypass.i_bypass_other.i_di_b_variable.i_gt_1.multandgen[14].carrymultand ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/final_div.del_end_divisor/opt_has_pipe.first_q [14]), + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .LO +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/remd_output.adsu_sel2/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.di [14]) + + ); + MULT_AND + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/remd_output.adsu_sel2/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_bypass.i_bypass_other.i_di_b_variable.i_gt_1.multandgen[15].carrymultand ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/final_div.del_end_divisor/opt_has_pipe.first_q [15]), + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .LO +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/remd_output.adsu_sel2/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.di [15]) + + ); + MULT_AND + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/remd_output.adsu_sel2/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_bypass.i_bypass_other.i_di_b_variable.i_gt_1.multandgen[16].carrymultand ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/final_div.del_end_divisor/opt_has_pipe.first_q [16]), + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .LO +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/remd_output.adsu_sel2/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.di [16]) + + ); + MULT_AND + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/remd_output.adsu_sel2/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_bypass.i_bypass_other.i_di_b_variable.i_gt_1.multandgen[17].carrymultand ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/final_div.del_end_divisor/opt_has_pipe.first_q [17]), + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .LO +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/remd_output.adsu_sel2/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.di [17]) + + ); + MULT_AND + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/remd_output.adsu_sel2/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_bypass.i_bypass_other.i_di_b_variable.i_gt_1.multandgen[18].carrymultand ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/final_div.del_end_divisor/opt_has_pipe.first_q [18]), + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .LO +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/remd_output.adsu_sel2/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.di [18]) + + ); + MULT_AND + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/remd_output.adsu_sel2/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_bypass.i_bypass_other.i_di_b_variable.i_gt_1.multandgen[19].carrymultand ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/final_div.del_end_divisor/opt_has_pipe.first_q [19]), + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .LO +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/remd_output.adsu_sel2/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.di [19]) + + ); + MULT_AND + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/remd_output.adsu_sel2/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_bypass.i_bypass_other.i_di_b_variable.i_gt_1.multandgen[20].carrymultand ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/final_div.del_end_divisor/opt_has_pipe.first_q [20]), + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .LO +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/remd_output.adsu_sel2/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.di [20]) + + ); + MULT_AND + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/remd_output.adsu_sel2/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_bypass.i_bypass_other.i_di_b_variable.i_gt_1.multandgen[21].carrymultand ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/final_div.del_end_divisor/opt_has_pipe.first_q [21]), + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .LO +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/remd_output.adsu_sel2/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.di [21]) + + ); + MULT_AND + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/remd_output.adsu_sel2/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_bypass.i_bypass_other.i_di_b_variable.i_gt_1.multandgen[22].carrymultand ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/final_div.del_end_divisor/opt_has_pipe.first_q [22]), + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .LO +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/remd_output.adsu_sel2/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.di [22]) + + ); + MULT_AND + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/remd_output.adsu_sel2/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_bypass.i_bypass_other.i_di_b_variable.i_gt_1.multandgen[23].carrymultand ( + .I0 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/final_div.del_end_divisor/opt_has_pipe.first_q [23]), + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .LO +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/remd_output.adsu_sel2/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.di [23]) + + ); + MULT_AND + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/remd_output.adsu_sel2/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_bypass.i_bypass_other.i_di_b_variable.multandtop.carrymultand ( + .I0(\BU2/divide_by_zero ), + .I1 +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .LO +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/remd_output.adsu_sel2/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.di [24]) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/remd_output.adsu_sel2/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_need_mux.carrymux0 ( + .CI(\BU2/divide_by_zero ), + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/remd_output.adsu_sel2/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.di [0]) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/remd_output.adsu_sel2/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum [0]) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/remd_output.adsu_sel2/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple [0]) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/remd_output.adsu_sel2/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.carryxor0 ( + .CI(\BU2/divide_by_zero ), + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/remd_output.adsu_sel2/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum [0]) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/remd_output.adsu_sel2/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple [0]) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/remd_output.adsu_sel2/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[1].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/remd_output.adsu_sel2/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple [0]) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/remd_output.adsu_sel2/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.di [1]) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/remd_output.adsu_sel2/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum [1]) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/remd_output.adsu_sel2/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple [1]) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/remd_output.adsu_sel2/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[2].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/remd_output.adsu_sel2/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple [1]) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/remd_output.adsu_sel2/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.di [2]) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/remd_output.adsu_sel2/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum [2]) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/remd_output.adsu_sel2/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple [2]) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/remd_output.adsu_sel2/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[3].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/remd_output.adsu_sel2/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple [2]) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/remd_output.adsu_sel2/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.di [3]) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/remd_output.adsu_sel2/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum [3]) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/remd_output.adsu_sel2/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple [3]) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/remd_output.adsu_sel2/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[4].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/remd_output.adsu_sel2/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple [3]) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/remd_output.adsu_sel2/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.di [4]) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/remd_output.adsu_sel2/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum [4]) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/remd_output.adsu_sel2/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple [4]) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/remd_output.adsu_sel2/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[5].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/remd_output.adsu_sel2/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple [4]) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/remd_output.adsu_sel2/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.di [5]) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/remd_output.adsu_sel2/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum [5]) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/remd_output.adsu_sel2/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple [5]) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/remd_output.adsu_sel2/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[6].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/remd_output.adsu_sel2/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple [5]) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/remd_output.adsu_sel2/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.di [6]) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/remd_output.adsu_sel2/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum [6]) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/remd_output.adsu_sel2/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple [6]) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/remd_output.adsu_sel2/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[7].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/remd_output.adsu_sel2/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple [6]) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/remd_output.adsu_sel2/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.di [7]) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/remd_output.adsu_sel2/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum [7]) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/remd_output.adsu_sel2/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple [7]) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/remd_output.adsu_sel2/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[8].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/remd_output.adsu_sel2/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple [7]) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/remd_output.adsu_sel2/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.di [8]) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/remd_output.adsu_sel2/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum [8]) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/remd_output.adsu_sel2/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple [8]) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/remd_output.adsu_sel2/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[9].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/remd_output.adsu_sel2/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple [8]) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/remd_output.adsu_sel2/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.di [9]) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/remd_output.adsu_sel2/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum [9]) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/remd_output.adsu_sel2/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple [9]) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/remd_output.adsu_sel2/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[10].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/remd_output.adsu_sel2/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple [9]) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/remd_output.adsu_sel2/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.di [10]) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/remd_output.adsu_sel2/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum [10]) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/remd_output.adsu_sel2/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple [10]) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/remd_output.adsu_sel2/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[11].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/remd_output.adsu_sel2/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple [10]) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/remd_output.adsu_sel2/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.di [11]) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/remd_output.adsu_sel2/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum [11]) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/remd_output.adsu_sel2/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple [11]) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/remd_output.adsu_sel2/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[12].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/remd_output.adsu_sel2/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple [11]) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/remd_output.adsu_sel2/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.di [12]) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/remd_output.adsu_sel2/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum [12]) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/remd_output.adsu_sel2/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple [12]) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/remd_output.adsu_sel2/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[13].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/remd_output.adsu_sel2/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple [12]) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/remd_output.adsu_sel2/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.di [13]) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/remd_output.adsu_sel2/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum [13]) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/remd_output.adsu_sel2/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple [13]) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/remd_output.adsu_sel2/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[14].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/remd_output.adsu_sel2/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple [13]) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/remd_output.adsu_sel2/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.di [14]) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/remd_output.adsu_sel2/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum [14]) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/remd_output.adsu_sel2/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple [14]) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/remd_output.adsu_sel2/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[15].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/remd_output.adsu_sel2/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple [14]) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/remd_output.adsu_sel2/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.di [15]) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/remd_output.adsu_sel2/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum [15]) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/remd_output.adsu_sel2/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple [15]) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/remd_output.adsu_sel2/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[16].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/remd_output.adsu_sel2/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple [15]) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/remd_output.adsu_sel2/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.di [16]) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/remd_output.adsu_sel2/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum [16]) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/remd_output.adsu_sel2/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple [16]) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/remd_output.adsu_sel2/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[17].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/remd_output.adsu_sel2/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple [16]) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/remd_output.adsu_sel2/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.di [17]) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/remd_output.adsu_sel2/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum [17]) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/remd_output.adsu_sel2/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple [17]) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/remd_output.adsu_sel2/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[18].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/remd_output.adsu_sel2/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple [17]) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/remd_output.adsu_sel2/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.di [18]) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/remd_output.adsu_sel2/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum [18]) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/remd_output.adsu_sel2/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple [18]) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/remd_output.adsu_sel2/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[19].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/remd_output.adsu_sel2/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple [18]) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/remd_output.adsu_sel2/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.di [19]) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/remd_output.adsu_sel2/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum [19]) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/remd_output.adsu_sel2/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple [19]) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/remd_output.adsu_sel2/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[20].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/remd_output.adsu_sel2/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple [19]) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/remd_output.adsu_sel2/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.di [20]) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/remd_output.adsu_sel2/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum [20]) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/remd_output.adsu_sel2/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple [20]) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/remd_output.adsu_sel2/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[21].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/remd_output.adsu_sel2/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple [20]) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/remd_output.adsu_sel2/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.di [21]) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/remd_output.adsu_sel2/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum [21]) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/remd_output.adsu_sel2/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple [21]) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/remd_output.adsu_sel2/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[22].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/remd_output.adsu_sel2/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple [21]) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/remd_output.adsu_sel2/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.di [22]) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/remd_output.adsu_sel2/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum [22]) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/remd_output.adsu_sel2/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple [22]) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/remd_output.adsu_sel2/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[23].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/remd_output.adsu_sel2/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple [22]) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/remd_output.adsu_sel2/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.di [23]) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/remd_output.adsu_sel2/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum [23]) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/remd_output.adsu_sel2/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple [23]) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/remd_output.adsu_sel2/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.muxtop.carrymuxtop ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/remd_output.adsu_sel2/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple [23]) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/remd_output.adsu_sel2/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.di [24]) +, + .S(\BU2/divide_by_zero ), + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/remd_output.adsu_sel2/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple [24]) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/remd_output.adsu_sel2/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carryxortop ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/remd_output.adsu_sel2/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple [23]) +, + .LI(\BU2/divide_by_zero ), + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/remd_output.adsu_sel2/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple [24]) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/remd_output.adsu_sel2/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[1].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/remd_output.adsu_sel2/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple [0]) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/remd_output.adsu_sel2/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum [1]) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/remd_output.adsu_sel2/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple [1]) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/remd_output.adsu_sel2/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[2].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/remd_output.adsu_sel2/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple [1]) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/remd_output.adsu_sel2/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum [2]) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/remd_output.adsu_sel2/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple [2]) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/remd_output.adsu_sel2/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[3].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/remd_output.adsu_sel2/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple [2]) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/remd_output.adsu_sel2/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum [3]) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/remd_output.adsu_sel2/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple [3]) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/remd_output.adsu_sel2/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[4].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/remd_output.adsu_sel2/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple [3]) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/remd_output.adsu_sel2/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum [4]) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/remd_output.adsu_sel2/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple [4]) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/remd_output.adsu_sel2/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[5].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/remd_output.adsu_sel2/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple [4]) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/remd_output.adsu_sel2/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum [5]) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/remd_output.adsu_sel2/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple [5]) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/remd_output.adsu_sel2/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[6].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/remd_output.adsu_sel2/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple [5]) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/remd_output.adsu_sel2/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum [6]) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/remd_output.adsu_sel2/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple [6]) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/remd_output.adsu_sel2/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[7].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/remd_output.adsu_sel2/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple [6]) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/remd_output.adsu_sel2/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum [7]) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/remd_output.adsu_sel2/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple [7]) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/remd_output.adsu_sel2/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[8].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/remd_output.adsu_sel2/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple [7]) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/remd_output.adsu_sel2/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum [8]) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/remd_output.adsu_sel2/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple [8]) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/remd_output.adsu_sel2/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[9].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/remd_output.adsu_sel2/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple [8]) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/remd_output.adsu_sel2/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum [9]) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/remd_output.adsu_sel2/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple [9]) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/remd_output.adsu_sel2/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[10].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/remd_output.adsu_sel2/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple [9]) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/remd_output.adsu_sel2/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum [10]) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/remd_output.adsu_sel2/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple [10]) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/remd_output.adsu_sel2/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[11].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/remd_output.adsu_sel2/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple [10]) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/remd_output.adsu_sel2/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum [11]) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/remd_output.adsu_sel2/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple [11]) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/remd_output.adsu_sel2/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[12].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/remd_output.adsu_sel2/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple [11]) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/remd_output.adsu_sel2/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum [12]) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/remd_output.adsu_sel2/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple [12]) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/remd_output.adsu_sel2/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[13].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/remd_output.adsu_sel2/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple [12]) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/remd_output.adsu_sel2/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum [13]) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/remd_output.adsu_sel2/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple [13]) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/remd_output.adsu_sel2/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[14].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/remd_output.adsu_sel2/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple [13]) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/remd_output.adsu_sel2/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum [14]) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/remd_output.adsu_sel2/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple [14]) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/remd_output.adsu_sel2/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[15].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/remd_output.adsu_sel2/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple [14]) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/remd_output.adsu_sel2/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum [15]) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/remd_output.adsu_sel2/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple [15]) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/remd_output.adsu_sel2/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[16].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/remd_output.adsu_sel2/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple [15]) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/remd_output.adsu_sel2/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum [16]) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/remd_output.adsu_sel2/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple [16]) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/remd_output.adsu_sel2/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[17].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/remd_output.adsu_sel2/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple [16]) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/remd_output.adsu_sel2/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum [17]) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/remd_output.adsu_sel2/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple [17]) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/remd_output.adsu_sel2/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[18].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/remd_output.adsu_sel2/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple [17]) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/remd_output.adsu_sel2/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum [18]) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/remd_output.adsu_sel2/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple [18]) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/remd_output.adsu_sel2/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[19].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/remd_output.adsu_sel2/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple [18]) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/remd_output.adsu_sel2/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum [19]) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/remd_output.adsu_sel2/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple [19]) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/remd_output.adsu_sel2/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[20].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/remd_output.adsu_sel2/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple [19]) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/remd_output.adsu_sel2/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum [20]) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/remd_output.adsu_sel2/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple [20]) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/remd_output.adsu_sel2/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[21].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/remd_output.adsu_sel2/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple [20]) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/remd_output.adsu_sel2/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum [21]) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/remd_output.adsu_sel2/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple [21]) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/remd_output.adsu_sel2/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[22].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/remd_output.adsu_sel2/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple [21]) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/remd_output.adsu_sel2/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum [22]) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/remd_output.adsu_sel2/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple [22]) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/remd_output.adsu_sel2/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[23].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/remd_output.adsu_sel2/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple [22]) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/remd_output.adsu_sel2/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum [23]) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/remd_output.adsu_sel2/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple [23]) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q_0 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<0> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q_1 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<0> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<1> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q_2 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<1> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<2> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q_3 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<2> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<3> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q_4 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<3> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<4> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q_5 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<4> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<5> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q_6 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<5> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<6> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q_7 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<6> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<7> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q_8 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<7> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<8> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q_9 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<8> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<9> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q_10 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<9> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<10> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q_11 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<10> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<11> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q_12 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<11> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<12> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q_13 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<12> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<13> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q_14 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<13> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<14> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q_15 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<14> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<15> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q_16 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<15> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<16> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q_17 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<16> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<17> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q_18 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<17> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<18> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q_19 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<18> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<19> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q_20 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<19> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<20> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q_21 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<20> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<21> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q_22 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<21> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<22> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q_23 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<22> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<23> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q_24 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<23> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<24> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q_25 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<24> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<25> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q_26 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<25> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<26> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q_27 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<26> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<27> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q_28 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<27> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<28> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q_29 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<28> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<29> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q_30 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<29> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<30> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q_0 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<0> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q_1 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<0> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<1> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q_2 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<1> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<2> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q_3 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<2> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<3> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q_4 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<3> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<4> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q_5 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<4> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<5> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q_6 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<5> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<6> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q_7 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<6> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<7> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q_8 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<7> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<8> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q_9 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<8> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<9> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q_10 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<9> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<10> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q_11 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<10> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<11> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q_12 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<11> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<12> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q_13 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<12> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<13> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q_14 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<13> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<14> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q_15 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<14> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<15> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q_16 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<15> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<16> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q_17 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<16> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<17> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q_18 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<17> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<18> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q_19 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<18> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<19> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q_20 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<19> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<20> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q_21 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<20> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<21> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q_22 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<21> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<22> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q_23 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<22> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<23> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q_24 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<23> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<24> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q_25 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<24> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<25> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q_26 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<25> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<26> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q_27 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<26> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<27> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q_28 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<27> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<28> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q_29 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<28> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<29> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q_0 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<0> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q_1 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<0> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<1> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q_2 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<1> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<2> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q_3 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<2> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<3> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q_4 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<3> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<4> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q_5 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<4> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<5> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q_6 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<5> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<6> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q_7 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<6> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<7> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q_8 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<7> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<8> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q_9 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<8> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<9> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q_10 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<9> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<10> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q_11 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<10> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<11> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q_12 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<11> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<12> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q_13 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<12> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<13> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q_14 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<13> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<14> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q_15 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<14> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<15> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q_16 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<15> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<16> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q_17 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<16> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<17> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q_18 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<17> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<18> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q_19 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<18> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<19> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q_20 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<19> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<20> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q_21 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<20> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<21> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q_22 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<21> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<22> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q_23 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<22> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<23> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q_24 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<23> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<24> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q_25 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<24> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<25> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q_26 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<25> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<26> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q_27 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<26> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<27> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q_28 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<27> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<28> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q_0 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<0> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q_1 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<0> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<1> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q_2 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<1> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<2> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q_3 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<2> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<3> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q_4 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<3> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<4> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q_5 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<4> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<5> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q_6 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<5> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<6> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q_7 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<6> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<7> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q_8 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<7> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<8> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q_9 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<8> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<9> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q_10 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<9> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<10> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q_11 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<10> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<11> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q_12 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<11> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<12> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q_13 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<12> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<13> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q_14 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<13> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<14> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q_15 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<14> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<15> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q_16 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<15> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<16> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q_17 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<16> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<17> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q_18 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<17> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<18> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q_19 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<18> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<19> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q_20 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<19> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<20> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q_21 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<20> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<21> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q_22 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<21> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<22> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q_23 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<22> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<23> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q_24 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<23> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<24> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q_25 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<24> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<25> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q_26 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<25> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<26> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q_27 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<26> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<27> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q_0 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<0> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q_1 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<0> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<1> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q_2 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<1> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<2> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q_3 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<2> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<3> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q_4 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<3> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<4> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q_5 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<4> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<5> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q_6 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<5> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<6> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q_7 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<6> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<7> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q_8 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<7> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<8> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q_9 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<8> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<9> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q_10 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<9> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<10> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q_11 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<10> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<11> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q_12 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<11> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<12> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q_13 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<12> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<13> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q_14 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<13> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<14> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q_15 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<14> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<15> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q_16 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<15> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<16> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q_17 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<16> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<17> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q_18 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<17> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<18> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q_19 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<18> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<19> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q_20 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<19> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<20> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q_21 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<20> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<21> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q_22 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<21> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<22> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q_23 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<22> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<23> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q_24 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<23> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<24> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q_25 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<24> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<25> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q_26 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<25> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<26> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q_0 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<0> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q_1 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<0> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<1> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q_2 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<1> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<2> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q_3 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<2> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<3> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q_4 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<3> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<4> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q_5 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<4> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<5> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q_6 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<5> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<6> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q_7 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<6> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<7> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q_8 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<7> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<8> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q_9 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<8> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<9> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q_10 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<9> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<10> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q_11 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<10> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<11> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q_12 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<11> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<12> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q_13 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<12> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<13> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q_14 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<13> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<14> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q_15 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<14> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<15> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q_16 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<15> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<16> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q_17 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<16> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<17> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q_18 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<17> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<18> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q_19 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<18> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<19> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q_20 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<19> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<20> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q_21 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<20> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<21> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q_22 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<21> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<22> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q_23 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<22> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<23> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q_24 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<23> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<24> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q_25 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<24> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<25> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q_0 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<0> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q_1 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<0> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<1> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q_2 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<1> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<2> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q_3 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<2> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<3> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q_4 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<3> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<4> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q_5 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<4> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<5> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q_6 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<5> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<6> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q_7 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<6> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<7> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q_8 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<7> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<8> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q_9 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<8> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<9> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q_10 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<9> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<10> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q_11 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<10> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<11> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q_12 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<11> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<12> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q_13 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<12> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<13> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q_14 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<13> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<14> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q_15 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<14> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<15> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q_16 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<15> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<16> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q_17 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<16> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<17> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q_18 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<17> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<18> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q_19 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<18> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<19> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q_20 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<19> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<20> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q_21 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<20> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<21> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q_22 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<21> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<22> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q_23 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<22> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<23> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q_0 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<0> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<0> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q_1 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<1> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<1> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q_2 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<2> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<2> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q_3 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<3> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<3> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q_4 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<4> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<4> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q_5 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<5> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<5> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q_6 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<6> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<6> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q_7 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<7> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<7> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q_0 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<0> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q_1 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<0> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<1> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q_2 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<1> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<2> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q_3 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<2> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<3> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q_4 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<3> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<4> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q_5 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<4> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<5> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q_6 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<5> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<6> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q_7 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<6> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<7> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q_8 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<7> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<8> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q_9 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<8> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<9> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q_10 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<9> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<10> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q_11 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<10> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<11> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q_12 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<11> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<12> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q_13 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<12> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<13> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q_14 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<13> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<14> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q_15 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<14> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<15> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q_16 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<15> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<16> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q_17 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<16> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<17> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q_18 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<17> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<18> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q_19 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<18> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<19> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q_20 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<19> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<20> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q_21 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<20> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<21> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q_22 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<21> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<22> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q_0 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<0> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<0> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q_1 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<1> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<1> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q_2 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<2> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<2> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q_3 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<3> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<3> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q_4 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<4> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<4> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q_5 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<5> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<5> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q_6 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<6> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<6> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q_7 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<7> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<7> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q_8 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<8> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<8> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q_0 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<0> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q_1 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<0> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<1> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q_2 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<1> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<2> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q_3 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<2> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<3> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q_4 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<3> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<4> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q_5 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<4> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<5> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q_6 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<5> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<6> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q_7 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<6> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<7> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q_8 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<7> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<8> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q_9 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<8> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<9> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q_10 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<9> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<10> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q_11 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<10> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<11> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q_12 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<11> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<12> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q_13 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<12> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<13> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q_14 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<13> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<14> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q_15 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<14> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<15> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q_16 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<15> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<16> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q_17 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<16> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<17> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q_18 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<17> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<18> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q_19 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<18> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<19> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q_20 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<19> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<20> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q_21 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<20> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<21> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q_0 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<0> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<0> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q_1 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<1> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<1> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q_2 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<2> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<2> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q_3 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<3> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<3> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q_4 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<4> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<4> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q_5 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<5> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<5> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q_6 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<6> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<6> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q_7 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<7> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<7> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q_8 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<8> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<8> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q_9 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<9> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<9> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q_0 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<0> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q_1 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<0> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<1> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q_2 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<1> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<2> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q_3 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<2> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<3> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q_4 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<3> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<4> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q_5 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<4> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<5> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q_6 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<5> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<6> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q_7 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<6> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<7> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q_8 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<7> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<8> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q_9 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<8> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<9> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q_10 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<9> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<10> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q_11 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<10> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<11> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q_12 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<11> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<12> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q_13 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<12> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<13> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q_14 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<13> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<14> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q_15 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<14> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<15> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q_16 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<15> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<16> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q_17 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<16> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<17> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q_18 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<17> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<18> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q_19 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<18> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<19> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q_20 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<19> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<20> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q_0 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<0> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<0> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q_1 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<1> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<1> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q_2 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<2> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<2> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q_3 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<3> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<3> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q_4 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<4> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<4> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q_5 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<5> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<5> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q_6 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<6> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<6> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q_7 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<7> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<7> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q_8 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<8> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<8> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q_9 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<9> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<9> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q_10 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<10> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<10> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q_0 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<0> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q_1 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<0> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<1> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q_2 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<1> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<2> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q_3 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<2> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<3> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q_4 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<3> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<4> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q_5 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<4> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<5> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q_6 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<5> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<6> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q_7 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<6> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<7> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q_8 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<7> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<8> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q_9 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<8> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<9> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q_10 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<9> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<10> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q_11 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<10> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<11> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q_12 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<11> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<12> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q_13 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<12> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<13> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q_14 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<13> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<14> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q_15 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<14> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<15> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q_16 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<15> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<16> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q_17 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<16> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<17> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q_18 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<17> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<18> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q_19 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<18> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<19> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q_0 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<0> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<0> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q_1 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<1> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<1> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q_2 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<2> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<2> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q_3 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<3> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<3> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q_4 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<4> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<4> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q_5 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<5> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<5> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q_6 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<6> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<6> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q_7 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<7> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<7> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q_8 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<8> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<8> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q_9 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<9> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<9> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q_10 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<10> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<10> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q_11 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<11> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<11> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q_0 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<0> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q_1 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<0> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<1> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q_2 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<1> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<2> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q_3 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<2> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<3> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q_4 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<3> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<4> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q_5 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<4> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<5> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q_6 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<5> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<6> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q_7 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<6> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<7> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q_8 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<7> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<8> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q_9 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<8> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<9> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q_10 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<9> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<10> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q_11 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<10> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<11> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q_12 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<11> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<12> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q_13 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<12> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<13> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q_14 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<13> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<14> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q_15 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<14> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<15> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q_16 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<15> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<16> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q_17 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<16> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<17> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q_18 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<17> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<18> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q_0 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<0> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<0> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q_1 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<1> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<1> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q_2 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<2> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<2> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q_3 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<3> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<3> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q_4 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<4> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<4> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q_5 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<5> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<5> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q_6 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<6> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<6> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q_7 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<7> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<7> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q_8 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<8> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<8> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q_9 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<9> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<9> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q_10 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<10> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<10> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q_11 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<11> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<11> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q_12 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<12> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<12> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q_0 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<0> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q_1 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<0> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<1> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q_2 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<1> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<2> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q_3 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<2> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<3> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q_4 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<3> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<4> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q_5 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<4> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<5> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q_6 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<5> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<6> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q_7 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<6> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<7> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q_8 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<7> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<8> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q_9 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<8> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<9> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q_10 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<9> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<10> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q_11 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<10> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<11> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q_12 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<11> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<12> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q_13 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<12> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<13> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q_14 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<13> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<14> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q_15 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<14> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<15> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q_16 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<15> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<16> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q_17 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<16> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<17> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q_0 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<0> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<0> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q_1 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<1> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<1> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q_2 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<2> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<2> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q_3 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<3> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<3> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q_4 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<4> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<4> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q_5 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<5> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<5> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q_6 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<6> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<6> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q_7 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<7> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<7> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q_8 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<8> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<8> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q_9 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<9> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<9> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q_10 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<10> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<10> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q_11 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<11> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<11> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q_12 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<12> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<12> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q_13 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<13> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<13> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q_0 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<0> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q_1 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<0> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<1> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q_2 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<1> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<2> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q_3 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<2> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<3> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q_4 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<3> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<4> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q_5 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<4> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<5> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q_6 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<5> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<6> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q_7 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<6> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<7> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q_8 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<7> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<8> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q_9 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<8> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<9> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q_10 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<9> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<10> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q_11 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<10> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<11> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q_12 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<11> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<12> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q_13 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<12> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<13> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q_14 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<13> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<14> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q_15 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<14> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<15> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q_16 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<15> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<16> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q_0 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<0> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<0> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q_1 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<1> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<1> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q_2 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<2> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<2> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q_3 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<3> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<3> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q_4 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<4> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<4> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q_5 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<5> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<5> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q_6 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<6> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<6> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q_7 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<7> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<7> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q_8 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<8> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<8> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q_9 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<9> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<9> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q_10 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<10> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<10> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q_11 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<11> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<11> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q_12 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<12> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<12> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q_13 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<13> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<13> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q_14 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<14> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<14> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q_0 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<0> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q_1 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<0> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<1> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q_2 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<1> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<2> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q_3 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<2> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<3> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q_4 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<3> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<4> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q_5 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<4> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<5> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q_6 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<5> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<6> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q_7 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<6> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<7> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q_8 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<7> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<8> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q_9 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<8> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<9> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q_10 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<9> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<10> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q_11 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<10> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<11> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q_12 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<11> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<12> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q_13 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<12> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<13> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q_14 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<13> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<14> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q_15 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<14> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<15> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q_0 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<0> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<0> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q_1 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<1> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<1> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q_2 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<2> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<2> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q_3 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<3> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<3> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q_4 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<4> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<4> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q_5 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<5> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<5> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q_6 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<6> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<6> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q_7 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<7> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<7> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q_8 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<8> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<8> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q_9 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<9> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<9> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q_10 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<10> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<10> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q_11 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<11> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<11> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q_12 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<12> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<12> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q_13 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<13> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<13> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q_14 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<14> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<14> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q_15 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<15> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<15> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q_0 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<0> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q_1 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<0> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<1> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q_2 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<1> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<2> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q_3 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<2> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<3> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q_4 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<3> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<4> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q_5 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<4> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<5> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q_6 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<5> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<6> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q_7 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<6> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<7> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q_8 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<7> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<8> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q_9 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<8> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<9> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q_10 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<9> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<10> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q_11 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<10> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<11> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q_12 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<11> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<12> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q_13 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<12> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<13> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q_14 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<13> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<14> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q_0 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<0> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<0> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q_1 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<1> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<1> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q_2 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<2> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<2> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q_3 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<3> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<3> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q_4 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<4> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<4> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q_5 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<5> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<5> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q_6 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<6> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<6> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q_7 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<7> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<7> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q_8 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<8> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<8> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q_9 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<9> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<9> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q_10 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<10> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<10> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q_11 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<11> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<11> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q_12 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<12> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<12> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q_13 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<13> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<13> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q_14 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<14> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<14> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q_15 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<15> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<15> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q_16 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<16> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<16> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q_0 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<0> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q_1 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<0> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<1> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q_2 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<1> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<2> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q_3 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<2> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<3> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q_4 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<3> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<4> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q_5 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<4> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<5> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q_6 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<5> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<6> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q_7 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<6> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<7> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q_8 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<7> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<8> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q_9 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<8> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<9> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q_10 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<9> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<10> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q_11 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<10> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<11> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q_12 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<11> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<12> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q_13 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<12> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<13> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q_0 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<0> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<0> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q_1 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<1> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<1> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q_2 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<2> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<2> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q_3 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<3> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<3> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q_4 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<4> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<4> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q_5 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<5> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<5> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q_6 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<6> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<6> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q_7 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<7> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<7> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q_8 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<8> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<8> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q_9 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<9> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<9> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q_10 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<10> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<10> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q_11 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<11> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<11> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q_12 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<12> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<12> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q_13 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<13> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<13> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q_14 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<14> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<14> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q_15 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<15> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<15> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q_16 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<16> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<16> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q_17 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<17> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<17> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q_0 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<0> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q_1 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<0> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<1> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q_2 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<1> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<2> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q_3 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<2> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<3> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q_4 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<3> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<4> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q_5 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<4> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<5> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q_6 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<5> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<6> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q_7 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<6> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<7> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q_8 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<7> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<8> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q_9 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<8> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<9> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q_10 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<9> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<10> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q_11 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<10> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<11> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q_12 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<11> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<12> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q_0 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<0> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<0> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q_1 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<1> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<1> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q_2 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<2> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<2> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q_3 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<3> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<3> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q_4 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<4> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<4> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q_5 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<5> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<5> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q_6 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<6> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<6> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q_7 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<7> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<7> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q_8 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<8> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<8> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q_9 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<9> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<9> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q_10 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<10> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<10> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q_11 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<11> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<11> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q_12 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<12> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<12> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q_13 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<13> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<13> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q_14 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<14> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<14> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q_15 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<15> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<15> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q_16 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<16> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<16> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q_17 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<17> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<17> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q_18 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<18> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<18> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q_0 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<0> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q_1 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<0> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<1> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q_2 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<1> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<2> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q_3 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<2> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<3> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q_4 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<3> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<4> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q_5 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<4> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<5> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q_6 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<5> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<6> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q_7 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<6> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<7> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q_8 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<7> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<8> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q_9 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<8> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<9> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q_10 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<9> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<10> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q_11 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<10> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<11> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q_0 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<0> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<0> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q_1 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<1> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<1> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q_2 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<2> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<2> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q_3 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<3> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<3> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q_4 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<4> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<4> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q_5 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<5> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<5> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q_6 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<6> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<6> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q_7 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<7> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<7> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q_8 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<8> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<8> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q_9 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<9> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<9> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q_10 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<10> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<10> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q_11 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<11> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<11> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q_12 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<12> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<12> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q_13 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<13> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<13> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q_14 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<14> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<14> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q_15 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<15> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<15> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q_16 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<16> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<16> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q_17 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<17> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<17> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q_18 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<18> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<18> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q_19 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<19> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<19> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q_0 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<0> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q_1 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<0> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<1> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q_2 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<1> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<2> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q_3 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<2> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<3> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q_4 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<3> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<4> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q_5 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<4> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<5> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q_6 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<5> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<6> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q_7 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<6> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<7> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q_8 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<7> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<8> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q_9 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<8> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<9> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q_10 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<9> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<10> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q_0 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<0> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<0> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q_1 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<1> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<1> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q_2 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<2> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<2> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q_3 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<3> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<3> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q_4 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<4> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<4> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q_5 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<5> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<5> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q_6 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<6> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<6> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q_7 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<7> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<7> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q_8 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<8> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<8> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q_9 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<9> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<9> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q_10 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<10> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<10> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q_11 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<11> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<11> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q_12 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<12> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<12> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q_13 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<13> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<13> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q_14 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<14> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<14> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q_15 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<15> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<15> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q_16 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<16> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<16> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q_17 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<17> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<17> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q_18 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<18> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<18> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q_19 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<19> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<19> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q_20 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<20> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<20> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q_0 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<0> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q_1 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<0> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<1> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q_2 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<1> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<2> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q_3 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<2> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<3> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q_4 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<3> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<4> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q_5 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<4> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<5> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q_6 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<5> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<6> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q_7 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<6> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<7> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q_8 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<7> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<8> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q_9 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<8> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<9> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q_0 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<0> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<0> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q_1 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<1> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<1> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q_2 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<2> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<2> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q_3 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<3> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<3> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q_4 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<4> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<4> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q_5 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<5> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<5> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q_6 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<6> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<6> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q_7 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<7> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<7> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q_8 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<8> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<8> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q_9 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<9> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<9> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q_10 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<10> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<10> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q_11 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<11> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<11> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q_12 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<12> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<12> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q_13 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<13> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<13> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q_14 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<14> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<14> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q_15 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<15> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<15> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q_16 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<16> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<16> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q_17 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<17> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<17> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q_18 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<18> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<18> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q_19 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<19> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<19> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q_20 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<20> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<20> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q_21 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<21> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<21> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q_0 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<0> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q_1 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<0> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<1> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q_2 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<1> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<2> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q_3 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<2> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<3> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q_4 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<3> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<4> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q_5 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<4> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<5> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q_6 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<5> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<6> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q_7 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<6> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<7> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q_8 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<7> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<8> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q_0 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<0> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<0> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q_1 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<1> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<1> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q_2 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<2> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<2> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q_3 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<3> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<3> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q_4 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<4> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<4> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q_5 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<5> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<5> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q_6 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<6> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<6> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q_7 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<7> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<7> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q_8 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<8> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<8> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q_9 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<9> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<9> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q_10 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<10> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<10> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q_11 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<11> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<11> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q_12 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<12> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<12> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q_13 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<13> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<13> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q_14 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<14> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<14> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q_15 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<15> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<15> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q_16 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<16> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<16> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q_17 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<17> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<17> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q_18 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<18> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<18> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q_19 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<19> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<19> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q_20 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<20> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<20> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q_21 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<21> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<21> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q_22 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<22> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<22> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q_0 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<0> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q_1 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<0> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<1> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q_2 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<1> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<2> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q_3 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<2> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<3> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q_4 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<3> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<4> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q_5 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<4> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<5> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q_6 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<5> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<6> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q_7 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<6> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<7> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q_0 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<0> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<0> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q_1 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<1> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<1> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q_2 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<2> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<2> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q_3 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<3> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<3> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q_4 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<4> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<4> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q_5 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<5> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<5> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q_6 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<6> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<6> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q_7 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<7> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<7> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q_8 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<8> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<8> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q_9 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<9> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<9> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q_10 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<10> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<10> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q_11 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<11> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<11> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q_12 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<12> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<12> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q_13 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<13> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<13> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q_14 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<14> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<14> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q_15 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<15> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<15> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q_16 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<16> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<16> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q_17 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<17> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<17> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q_18 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<18> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<18> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q_19 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<19> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<19> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q_20 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<20> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<20> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q_21 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<21> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<21> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q_22 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<22> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<22> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q_23 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<23> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<23> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q_0 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<0> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<0> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q_1 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<1> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<1> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q_2 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<2> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<2> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q_3 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<3> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<3> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q_4 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<4> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<4> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q_5 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<5> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<5> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q_6 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<6> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<6> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q_7 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<7> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<7> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q_8 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<8> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<8> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q_9 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<9> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<9> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q_10 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<10> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<10> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q_11 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<11> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<11> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q_12 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<12> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<12> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q_13 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<13> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<13> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q_14 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<14> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<14> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q_15 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<15> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<15> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q_16 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<16> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<16> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q_17 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<17> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<17> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q_18 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<18> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<18> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q_19 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<19> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<19> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q_20 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<20> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<20> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q_21 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<21> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<21> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q_22 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<22> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<22> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q_23 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<23> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<23> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q_24 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<24> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<24> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q_0 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<0> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<0> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q_1 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<1> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<1> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q_2 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<2> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<2> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q_3 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<3> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<3> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q_4 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<4> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<4> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q_5 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<5> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<5> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q_6 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<6> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<6> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q_7 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<7> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<7> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q_8 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<8> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<8> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q_9 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<9> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<9> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q_10 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<10> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<10> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q_11 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<11> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<11> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q_12 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<12> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<12> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q_13 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<13> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<13> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q_14 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<14> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<14> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q_15 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<15> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<15> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q_16 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<16> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<16> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q_17 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<17> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<17> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q_18 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<18> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<18> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q_19 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<19> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<19> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q_20 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<20> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<20> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q_21 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<21> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<21> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q_22 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<22> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<22> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q_23 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<23> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<23> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q_24 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<24> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<24> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q_25 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<25> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<25> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q_0 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<0> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<0> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q_1 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<1> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<1> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q_2 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<2> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<2> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q_3 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<3> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<3> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q_4 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<4> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<4> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q_5 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<5> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<5> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q_6 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<6> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<6> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q_7 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<7> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<7> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q_8 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<8> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<8> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q_9 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<9> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<9> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q_10 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<10> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<10> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q_11 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<11> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<11> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q_12 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<12> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<12> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q_13 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<13> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<13> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q_14 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<14> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<14> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q_15 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<15> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<15> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q_16 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<16> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<16> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q_17 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<17> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<17> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q_18 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<18> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<18> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q_19 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<19> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<19> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q_20 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<20> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<20> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q_21 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<21> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<21> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q_22 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<22> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<22> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q_23 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<23> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<23> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q_24 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<24> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<24> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q_25 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<25> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<25> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q_26 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<26> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<26> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q_0 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<0> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<0> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q_1 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<1> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<1> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q_2 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<2> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<2> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q_3 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<3> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<3> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q_4 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<4> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<4> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q_5 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<5> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<5> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q_6 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<6> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<6> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q_7 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<7> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<7> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q_8 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<8> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<8> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q_9 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<9> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<9> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q_10 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<10> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<10> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q_11 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<11> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<11> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q_12 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<12> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<12> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q_13 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<13> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<13> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q_14 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<14> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<14> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q_15 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<15> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<15> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q_16 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<16> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<16> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q_17 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<17> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<17> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q_18 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<18> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<18> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q_19 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<19> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<19> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q_20 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<20> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<20> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q_21 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<21> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<21> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q_22 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<22> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<22> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q_23 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<23> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<23> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q_24 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<24> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<24> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q_25 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<25> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<25> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q_26 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<26> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<26> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q_27 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<27> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<27> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q_0 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<0> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<0> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q_1 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<1> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<1> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q_2 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<2> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<2> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q_3 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<3> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<3> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q_4 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<4> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<4> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q_5 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<5> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<5> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q_6 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<6> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<6> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q_7 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<7> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<7> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q_8 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<8> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<8> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q_9 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<9> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<9> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q_10 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<10> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<10> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q_11 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<11> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<11> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q_12 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<12> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<12> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q_13 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<13> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<13> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q_14 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<14> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<14> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q_15 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<15> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<15> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q_16 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<16> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<16> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q_17 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<17> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<17> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q_18 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<18> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<18> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q_19 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<19> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<19> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q_20 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<20> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<20> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q_21 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<21> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<21> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q_22 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<22> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<22> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q_23 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<23> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<23> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q_24 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<24> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<24> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q_25 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<25> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<25> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q_26 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<26> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<26> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q_27 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<27> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<27> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q_28 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<28> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<28> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q_0 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<0> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<0> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q_1 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<1> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<1> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q_2 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<2> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<2> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q_3 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<3> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<3> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q_4 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<4> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<4> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q_5 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<5> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<5> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q_6 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<6> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<6> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q_7 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<7> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<7> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q_8 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<8> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<8> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q_9 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<9> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<9> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q_10 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<10> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<10> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q_11 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<11> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<11> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q_12 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<12> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<12> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q_13 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<13> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<13> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q_14 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<14> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<14> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q_15 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<15> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<15> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q_16 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<16> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<16> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q_17 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<17> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<17> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q_18 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<18> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<18> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q_19 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<19> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<19> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q_20 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<20> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<20> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q_21 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<21> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<21> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q_22 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<22> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<22> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q_23 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<23> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<23> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q_24 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<24> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<24> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q_25 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<25> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<25> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q_26 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<26> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<26> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q_27 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<27> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<27> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q_28 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<28> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<28> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q_29 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<29> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<29> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q_0 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<0> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<0> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q_1 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<1> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<1> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q_2 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<2> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<2> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q_3 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<3> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<3> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q_4 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<4> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<4> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q_5 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<5> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<5> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q_6 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<6> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<6> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q_7 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<7> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<7> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q_8 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<8> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<8> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q_9 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<9> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<9> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q_10 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<10> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<10> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q_11 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<11> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<11> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q_12 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<12> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<12> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q_13 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<13> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<13> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q_14 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<14> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<14> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q_15 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<15> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<15> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q_16 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<16> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<16> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q_17 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<17> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<17> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q_18 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<18> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<18> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q_19 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<19> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<19> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q_20 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<20> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<20> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q_21 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<21> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<21> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q_22 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<22> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<22> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q_23 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<23> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<23> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q_24 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<24> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<24> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q_25 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<25> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<25> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q_26 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<26> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<26> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q_27 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<27> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<27> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q_28 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<28> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<28> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q_29 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<29> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<29> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q_30 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<30> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<30> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q_0 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<0> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q_1 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<0> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<1> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q_2 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<1> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<2> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q_3 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<2> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<3> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q_4 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<3> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<4> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q_5 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<4> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<5> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q_6 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<5> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<6> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q_7 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<6> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<7> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q_8 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<7> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<8> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q_9 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<8> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<9> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q_10 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<9> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<10> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q_11 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<10> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<11> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q_12 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<11> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<12> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q_13 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<12> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<13> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q_14 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<13> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<14> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q_15 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<14> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<15> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q_16 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<15> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<16> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q_17 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<16> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<17> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q_18 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<17> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<18> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q_19 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<18> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<19> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q_20 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<19> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<20> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q_21 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<20> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<21> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q_22 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<21> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<22> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q_23 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<22> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<23> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q_24 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<23> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<24> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_0 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<0> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<0> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_1 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<1> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<1> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_2 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<2> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<2> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_3 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<3> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<3> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_4 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<4> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<4> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_5 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<5> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<5> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_6 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<6> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<6> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_7 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<7> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<7> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_8 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<8> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<8> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_9 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<9> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<9> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_10 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<10> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<10> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_11 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<11> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<11> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_12 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<12> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<12> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_13 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<13> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<13> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_14 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<14> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<14> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_15 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<15> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<15> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_16 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<16> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<16> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_17 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<17> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<17> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_18 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<18> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<18> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_19 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<19> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<19> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_20 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<20> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<20> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_21 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<21> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<21> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_22 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<22> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<22> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_23 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<23> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<23> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_24 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<24> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_0 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<0> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<0> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_1 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<1> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<1> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_2 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<2> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<2> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_3 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<3> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<3> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_4 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<4> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<4> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_5 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<5> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<5> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_6 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<6> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<6> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_7 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<7> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<7> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_8 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<8> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<8> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_9 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<9> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<9> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_10 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<10> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<10> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_11 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<11> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<11> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_12 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<12> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<12> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_13 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<13> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<13> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_14 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<14> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<14> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_15 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<15> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<15> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_16 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<16> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<16> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_17 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<17> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<17> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_18 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<18> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<18> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_19 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<19> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<19> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_20 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<20> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<20> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_21 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<21> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<21> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_22 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<22> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<22> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_23 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<23> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<23> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_24 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<24> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_0 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<0> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<0> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_1 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<1> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<1> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_2 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<2> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<2> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_3 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<3> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<3> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_4 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<4> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<4> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_5 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<5> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<5> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_6 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<6> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<6> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_7 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<7> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<7> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_8 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<8> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<8> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_9 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<9> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<9> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_10 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<10> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<10> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_11 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<11> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<11> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_12 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<12> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<12> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_13 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<13> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<13> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_14 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<14> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<14> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_15 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<15> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<15> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_16 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<16> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<16> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_17 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<17> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<17> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_18 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<18> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<18> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_19 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<19> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<19> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_20 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<20> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<20> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_21 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<21> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<21> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_22 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<22> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<22> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_23 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<23> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<23> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_24 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<24> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_0 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<0> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<0> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_1 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<1> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<1> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_2 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<2> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<2> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_3 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<3> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<3> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_4 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<4> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<4> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_5 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<5> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<5> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_6 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<6> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<6> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_7 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<7> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<7> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_8 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<8> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<8> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_9 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<9> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<9> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_10 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<10> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<10> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_11 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<11> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<11> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_12 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<12> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<12> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_13 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<13> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<13> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_14 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<14> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<14> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_15 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<15> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<15> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_16 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<16> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<16> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_17 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<17> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<17> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_18 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<18> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<18> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_19 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<19> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<19> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_20 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<20> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<20> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_21 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<21> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<21> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_22 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<22> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<22> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_23 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<23> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<23> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_24 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<24> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_0 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<0> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<0> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_1 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<1> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<1> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_2 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<2> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<2> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_3 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<3> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<3> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_4 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<4> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<4> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_5 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<5> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<5> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_6 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<6> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<6> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_7 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<7> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<7> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_8 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<8> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<8> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_9 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<9> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<9> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_10 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<10> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<10> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_11 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<11> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<11> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_12 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<12> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<12> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_13 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<13> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<13> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_14 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<14> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<14> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_15 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<15> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<15> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_16 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<16> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<16> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_17 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<17> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<17> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_18 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<18> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<18> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_19 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<19> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<19> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_20 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<20> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<20> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_21 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<21> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<21> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_22 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<22> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<22> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_23 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<23> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<23> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_24 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<24> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_0 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<0> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<0> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_1 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<1> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<1> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_2 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<2> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<2> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_3 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<3> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<3> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_4 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<4> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<4> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_5 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<5> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<5> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_6 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<6> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<6> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_7 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<7> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<7> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_8 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<8> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<8> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_9 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<9> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<9> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_10 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<10> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<10> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_11 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<11> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<11> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_12 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<12> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<12> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_13 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<13> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<13> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_14 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<14> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<14> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_15 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<15> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<15> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_16 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<16> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<16> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_17 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<17> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<17> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_18 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<18> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<18> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_19 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<19> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<19> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_20 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<20> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<20> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_21 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<21> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<21> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_22 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<22> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<22> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_23 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<23> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<23> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_24 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<24> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_0 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<0> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<0> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_1 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<1> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<1> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_2 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<2> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<2> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_3 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<3> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<3> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_4 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<4> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<4> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_5 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<5> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<5> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_6 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<6> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<6> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_7 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<7> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<7> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_8 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<8> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<8> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_9 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<9> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<9> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_10 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<10> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<10> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_11 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<11> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<11> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_12 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<12> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<12> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_13 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<13> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<13> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_14 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<14> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<14> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_15 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<15> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<15> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_16 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<16> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<16> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_17 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<17> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<17> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_18 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<18> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<18> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_19 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<19> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<19> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_20 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<20> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<20> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_21 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<21> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<21> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_22 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<22> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<22> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_23 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<23> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<23> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_24 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<24> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_0 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<0> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<0> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_1 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<1> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<1> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_2 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<2> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<2> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_3 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<3> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<3> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_4 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<4> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<4> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_5 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<5> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<5> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_6 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<6> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<6> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_7 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<7> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<7> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_8 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<8> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<8> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_9 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<9> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<9> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_10 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<10> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<10> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_11 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<11> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<11> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_12 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<12> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<12> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_13 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<13> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<13> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_14 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<14> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<14> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_15 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<15> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<15> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_16 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<16> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<16> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_17 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<17> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<17> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_18 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<18> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<18> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_19 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<19> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<19> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_20 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<20> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<20> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_21 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<21> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<21> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_22 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<22> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<22> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_23 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<23> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<23> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_24 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<24> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_0 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<0> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<0> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_1 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<1> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<1> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_2 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<2> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<2> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_3 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<3> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<3> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_4 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<4> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<4> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_5 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<5> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<5> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_6 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<6> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<6> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_7 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<7> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<7> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_8 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<8> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<8> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_9 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<9> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<9> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_10 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<10> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<10> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_11 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<11> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<11> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_12 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<12> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<12> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_13 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<13> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<13> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_14 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<14> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<14> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_15 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<15> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<15> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_16 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<16> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<16> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_17 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<17> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<17> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_18 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<18> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<18> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_19 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<19> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<19> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_20 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<20> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<20> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_21 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<21> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<21> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_22 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<22> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<22> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_23 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<23> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<23> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_24 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<24> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_0 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<0> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<0> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_1 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<1> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<1> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_2 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<2> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<2> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_3 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<3> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<3> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_4 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<4> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<4> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_5 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<5> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<5> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_6 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<6> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<6> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_7 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<7> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<7> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_8 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<8> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<8> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_9 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<9> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<9> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_10 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<10> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<10> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_11 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<11> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<11> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_12 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<12> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<12> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_13 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<13> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<13> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_14 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<14> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<14> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_15 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<15> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<15> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_16 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<16> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<16> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_17 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<17> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<17> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_18 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<18> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<18> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_19 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<19> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<19> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_20 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<20> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<20> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_21 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<21> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<21> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_22 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<22> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<22> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_23 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<23> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<23> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_24 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<24> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_0 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<0> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<0> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_1 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<1> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<1> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_2 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<2> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<2> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_3 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<3> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<3> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_4 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<4> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<4> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_5 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<5> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<5> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_6 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<6> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<6> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_7 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<7> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<7> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_8 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<8> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<8> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_9 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<9> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<9> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_10 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<10> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<10> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_11 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<11> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<11> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_12 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<12> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<12> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_13 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<13> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<13> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_14 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<14> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<14> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_15 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<15> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<15> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_16 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<16> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<16> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_17 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<17> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<17> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_18 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<18> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<18> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_19 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<19> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<19> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_20 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<20> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<20> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_21 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<21> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<21> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_22 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<22> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<22> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_23 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<23> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<23> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_24 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<24> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_0 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<0> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<0> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_1 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<1> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<1> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_2 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<2> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<2> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_3 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<3> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<3> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_4 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<4> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<4> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_5 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<5> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<5> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_6 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<6> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<6> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_7 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<7> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<7> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_8 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<8> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<8> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_9 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<9> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<9> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_10 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<10> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<10> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_11 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<11> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<11> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_12 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<12> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<12> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_13 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<13> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<13> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_14 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<14> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<14> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_15 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<15> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<15> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_16 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<16> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<16> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_17 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<17> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<17> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_18 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<18> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<18> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_19 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<19> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<19> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_20 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<20> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<20> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_21 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<21> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<21> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_22 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<22> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<22> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_23 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<23> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<23> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_24 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<24> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_0 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<0> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<0> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_1 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<1> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<1> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_2 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<2> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<2> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_3 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<3> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<3> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_4 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<4> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<4> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_5 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<5> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<5> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_6 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<6> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<6> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_7 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<7> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<7> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_8 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<8> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<8> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_9 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<9> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<9> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_10 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<10> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<10> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_11 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<11> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<11> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_12 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<12> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<12> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_13 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<13> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<13> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_14 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<14> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<14> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_15 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<15> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<15> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_16 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<16> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<16> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_17 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<17> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<17> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_18 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<18> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<18> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_19 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<19> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<19> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_20 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<20> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<20> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_21 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<21> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<21> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_22 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<22> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<22> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_23 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<23> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<23> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_24 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<24> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_0 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<0> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<0> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_1 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<1> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<1> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_2 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<2> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<2> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_3 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<3> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<3> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_4 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<4> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<4> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_5 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<5> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<5> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_6 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<6> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<6> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_7 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<7> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<7> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_8 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<8> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<8> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_9 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<9> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<9> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_10 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<10> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<10> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_11 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<11> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<11> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_12 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<12> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<12> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_13 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<13> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<13> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_14 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<14> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<14> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_15 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<15> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<15> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_16 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<16> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<16> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_17 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<17> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<17> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_18 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<18> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<18> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_19 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<19> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<19> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_20 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<20> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<20> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_21 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<21> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<21> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_22 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<22> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<22> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_23 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<23> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<23> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_24 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<24> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_0 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<0> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<0> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_1 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<1> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<1> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_2 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<2> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<2> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_3 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<3> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<3> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_4 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<4> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<4> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_5 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<5> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<5> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_6 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<6> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<6> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_7 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<7> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<7> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_8 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<8> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<8> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_9 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<9> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<9> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_10 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<10> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<10> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_11 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<11> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<11> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_12 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<12> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<12> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_13 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<13> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<13> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_14 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<14> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<14> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_15 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<15> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<15> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_16 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<16> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<16> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_17 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<17> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<17> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_18 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<18> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<18> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_19 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<19> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<19> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_20 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<20> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<20> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_21 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<21> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<21> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_22 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<22> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<22> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_23 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<23> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<23> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_24 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<24> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_0 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<0> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<0> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_1 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<1> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<1> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_2 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<2> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<2> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_3 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<3> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<3> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_4 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<4> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<4> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_5 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<5> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<5> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_6 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<6> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<6> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_7 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<7> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<7> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_8 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<8> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<8> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_9 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<9> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<9> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_10 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<10> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<10> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_11 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<11> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<11> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_12 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<12> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<12> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_13 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<13> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<13> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_14 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<14> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<14> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_15 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<15> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<15> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_16 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<16> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<16> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_17 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<17> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<17> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_18 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<18> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<18> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_19 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<19> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<19> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_20 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<20> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<20> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_21 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<21> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<21> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_22 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<22> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<22> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_23 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<23> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<23> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_24 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<24> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_0 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<0> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<0> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_1 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<1> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<1> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_2 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<2> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<2> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_3 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<3> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<3> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_4 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<4> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<4> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_5 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<5> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<5> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_6 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<6> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<6> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_7 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<7> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<7> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_8 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<8> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<8> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_9 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<9> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<9> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_10 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<10> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<10> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_11 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<11> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<11> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_12 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<12> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<12> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_13 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<13> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<13> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_14 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<14> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<14> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_15 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<15> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<15> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_16 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<16> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<16> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_17 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<17> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<17> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_18 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<18> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<18> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_19 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<19> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<19> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_20 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<20> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<20> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_21 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<21> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<21> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_22 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<22> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<22> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_23 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<23> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<23> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_24 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<24> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_0 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<0> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<0> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_1 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<1> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<1> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_2 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<2> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<2> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_3 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<3> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<3> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_4 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<4> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<4> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_5 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<5> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<5> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_6 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<6> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<6> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_7 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<7> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<7> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_8 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<8> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<8> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_9 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<9> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<9> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_10 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<10> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<10> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_11 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<11> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<11> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_12 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<12> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<12> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_13 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<13> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<13> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_14 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<14> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<14> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_15 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<15> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<15> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_16 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<16> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<16> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_17 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<17> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<17> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_18 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<18> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<18> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_19 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<19> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<19> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_20 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<20> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<20> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_21 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<21> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<21> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_22 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<22> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<22> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_23 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<23> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<23> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_24 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<24> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_0 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<0> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<0> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_1 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<1> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<1> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_2 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<2> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<2> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_3 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<3> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<3> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_4 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<4> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<4> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_5 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<5> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<5> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_6 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<6> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<6> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_7 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<7> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<7> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_8 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<8> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<8> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_9 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<9> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<9> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_10 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<10> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<10> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_11 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<11> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<11> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_12 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<12> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<12> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_13 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<13> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<13> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_14 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<14> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<14> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_15 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<15> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<15> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_16 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<16> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<16> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_17 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<17> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<17> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_18 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<18> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<18> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_19 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<19> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<19> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_20 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<20> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<20> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_21 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<21> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<21> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_22 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<22> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<22> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_23 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<23> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<23> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_24 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<24> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_0 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<0> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<0> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_1 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<1> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<1> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_2 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<2> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<2> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_3 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<3> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<3> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_4 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<4> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<4> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_5 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<5> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<5> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_6 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<6> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<6> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_7 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<7> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<7> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_8 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<8> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<8> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_9 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<9> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<9> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_10 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<10> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<10> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_11 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<11> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<11> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_12 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<12> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<12> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_13 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<13> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<13> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_14 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<14> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<14> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_15 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<15> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<15> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_16 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<16> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<16> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_17 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<17> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<17> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_18 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<18> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<18> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_19 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<19> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<19> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_20 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<20> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<20> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_21 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<21> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<21> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_22 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<22> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<22> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_23 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<23> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<23> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_24 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<24> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_0 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<0> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<0> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_1 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<1> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<1> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_2 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<2> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<2> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_3 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<3> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<3> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_4 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<4> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<4> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_5 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<5> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<5> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_6 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<6> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<6> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_7 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<7> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<7> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_8 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<8> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<8> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_9 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<9> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<9> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_10 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<10> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<10> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_11 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<11> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<11> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_12 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<12> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<12> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_13 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<13> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<13> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_14 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<14> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<14> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_15 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<15> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<15> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_16 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<16> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<16> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_17 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<17> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<17> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_18 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<18> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<18> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_19 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<19> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<19> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_20 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<20> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<20> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_21 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<21> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<21> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_22 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<22> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<22> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_23 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<23> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<23> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_24 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<24> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_0 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<0> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<0> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_1 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<1> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<1> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_2 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<2> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<2> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_3 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<3> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<3> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_4 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<4> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<4> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_5 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<5> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<5> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_6 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<6> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<6> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_7 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<7> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<7> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_8 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<8> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<8> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_9 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<9> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<9> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_10 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<10> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<10> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_11 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<11> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<11> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_12 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<12> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<12> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_13 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<13> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<13> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_14 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<14> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<14> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_15 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<15> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<15> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_16 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<16> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<16> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_17 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<17> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<17> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_18 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<18> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<18> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_19 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<19> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<19> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_20 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<20> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<20> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_21 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<21> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<21> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_22 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<22> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<22> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_23 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<23> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<23> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_24 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<24> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_0 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<0> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<0> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_1 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<1> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<1> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_2 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<2> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<2> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_3 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<3> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<3> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_4 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<4> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<4> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_5 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<5> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<5> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_6 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<6> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<6> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_7 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<7> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<7> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_8 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<8> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<8> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_9 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<9> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<9> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_10 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<10> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<10> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_11 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<11> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<11> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_12 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<12> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<12> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_13 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<13> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<13> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_14 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<14> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<14> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_15 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<15> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<15> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_16 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<16> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<16> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_17 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<17> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<17> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_18 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<18> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<18> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_19 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<19> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<19> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_20 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<20> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<20> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_21 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<21> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<21> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_22 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<22> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<22> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_23 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<23> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<23> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_24 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<24> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_0 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<0> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<0> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_1 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<1> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<1> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_2 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<2> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<2> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_3 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<3> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<3> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_4 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<4> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<4> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_5 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<5> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<5> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_6 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<6> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<6> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_7 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<7> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<7> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_8 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<8> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<8> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_9 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<9> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<9> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_10 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<10> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<10> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_11 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<11> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<11> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_12 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<12> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<12> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_13 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<13> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<13> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_14 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<14> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<14> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_15 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<15> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<15> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_16 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<16> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<16> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_17 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<17> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<17> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_18 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<18> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<18> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_19 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<19> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<19> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_20 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<20> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<20> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_21 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<21> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<21> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_22 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<22> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<22> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_23 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<23> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<23> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_24 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<24> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_0 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<0> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<0> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_1 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<1> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<1> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_2 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<2> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<2> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_3 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<3> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<3> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_4 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<4> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<4> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_5 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<5> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<5> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_6 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<6> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<6> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_7 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<7> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<7> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_8 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<8> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<8> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_9 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<9> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<9> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_10 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<10> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<10> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_11 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<11> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<11> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_12 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<12> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<12> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_13 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<13> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<13> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_14 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<14> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<14> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_15 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<15> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<15> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_16 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<16> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<16> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_17 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<17> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<17> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_18 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<18> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<18> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_19 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<19> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<19> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_20 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<20> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<20> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_21 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<21> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<21> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_22 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<22> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<22> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_23 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<23> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<23> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_24 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<24> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_0 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<0> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<0> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_1 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<1> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<1> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_2 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<2> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<2> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_3 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<3> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<3> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_4 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<4> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<4> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_5 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<5> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<5> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_6 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<6> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<6> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_7 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<7> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<7> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_8 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<8> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<8> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_9 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<9> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<9> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_10 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<10> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<10> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_11 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<11> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<11> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_12 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<12> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<12> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_13 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<13> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<13> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_14 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<14> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<14> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_15 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<15> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<15> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_16 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<16> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<16> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_17 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<17> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<17> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_18 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<18> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<18> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_19 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<19> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<19> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_20 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<20> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<20> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_21 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<21> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<21> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_22 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<22> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<22> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_23 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<23> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<23> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_24 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<24> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_0 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<0> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<0> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_1 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<1> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<1> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_2 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<2> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<2> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_3 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<3> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<3> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_4 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<4> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<4> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_5 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<5> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<5> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_6 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<6> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<6> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_7 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<7> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<7> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_8 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<8> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<8> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_9 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<9> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<9> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_10 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<10> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<10> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_11 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<11> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<11> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_12 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<12> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<12> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_13 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<13> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<13> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_14 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<14> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<14> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_15 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<15> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<15> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_16 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<16> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<16> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_17 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<17> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<17> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_18 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<18> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<18> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_19 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<19> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<19> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_20 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<20> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<20> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_21 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<21> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<21> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_22 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<22> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<22> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_23 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<23> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<23> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_24 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<24> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_0 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<0> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<0> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_1 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<1> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<1> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_2 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<2> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<2> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_3 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<3> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<3> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_4 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<4> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<4> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_5 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<5> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<5> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_6 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<6> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<6> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_7 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<7> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<7> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_8 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<8> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<8> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_9 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<9> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<9> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_10 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<10> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<10> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_11 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<11> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<11> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_12 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<12> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<12> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_13 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<13> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<13> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_14 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<14> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<14> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_15 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<15> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<15> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_16 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<16> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<16> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_17 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<17> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<17> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_18 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<18> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<18> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_19 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<19> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<19> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_20 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<20> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<20> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_21 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<21> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<21> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_22 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<22> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<22> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_23 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<23> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<23> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_24 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<24> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_0 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<0> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<0> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_1 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<1> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<1> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_2 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<2> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<2> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_3 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<3> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<3> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_4 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<4> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<4> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_5 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<5> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<5> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_6 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<6> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<6> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_7 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<7> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<7> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_8 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<8> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<8> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_9 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<9> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<9> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_10 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<10> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<10> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_11 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<11> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<11> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_12 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<12> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<12> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_13 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<13> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<13> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_14 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<14> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<14> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_15 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<15> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<15> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_16 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<16> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<16> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_17 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<17> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<17> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_18 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<18> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<18> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_19 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<19> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<19> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_20 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<20> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<20> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_21 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<21> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<21> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_22 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<22> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<22> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_23 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<23> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<23> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_24 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<24> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_0 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<0> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<0> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_1 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<1> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<1> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_2 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<2> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<2> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_3 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<3> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<3> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_4 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<4> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<4> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_5 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<5> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<5> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_6 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<6> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<6> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_7 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<7> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<7> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_8 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<8> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<8> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_9 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<9> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<9> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_10 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<10> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<10> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_11 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<11> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<11> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_12 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<12> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<12> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_13 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<13> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<13> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_14 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<14> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<14> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_15 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<15> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<15> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_16 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<16> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<16> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_17 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<17> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<17> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_18 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<18> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<18> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_19 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<19> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<19> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_20 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<20> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<20> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_21 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<21> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<21> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_22 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<22> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<22> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_23 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<23> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<23> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_24 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<24> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_0 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<0> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<0> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_1 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<1> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<1> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_2 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<2> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<2> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_3 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<3> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<3> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_4 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<4> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<4> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_5 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<5> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<5> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_6 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<6> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<6> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_7 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<7> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<7> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_8 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<8> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<8> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_9 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<9> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<9> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_10 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<10> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<10> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_11 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<11> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<11> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_12 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<12> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<12> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_13 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<13> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<13> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_14 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<14> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<14> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_15 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<15> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<15> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_16 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<16> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<16> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_17 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<17> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<17> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_18 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<18> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<18> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_19 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<19> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<19> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_20 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<20> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<20> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_21 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<21> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<21> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_22 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<22> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<22> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_23 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<23> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<23> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_24 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<24> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_0 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<0> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<0> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_1 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<1> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<1> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_2 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<2> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<2> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_3 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<3> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<3> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_4 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<4> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<4> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_5 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<5> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<5> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_6 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<6> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<6> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_7 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<7> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<7> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_8 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<8> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<8> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_9 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<9> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<9> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_10 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<10> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<10> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_11 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<11> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<11> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_12 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<12> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<12> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_13 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<13> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<13> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_14 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<14> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<14> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_15 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<15> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<15> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_16 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<16> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<16> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_17 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<17> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<17> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_18 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<18> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<18> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_19 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<19> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<19> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_20 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<20> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<20> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_21 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<21> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<21> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_22 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<22> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<22> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_23 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<23> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<23> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q_24 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<24> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q_c_out.i_simple.add_q_cout.q_c_outreg/opt_has_pipe.first_q_0 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<24> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q_c_out.i_simple.add_q_cout.q_c_outreg/opt_has_pipe.first_q ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_need_mux.carrymux0 ( + .CI(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/inv_o [30]), + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<0> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<0> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.carryxor0 ( + .CI(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/inv_o [30]), + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<0> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<0> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.muxtop.carrymuxtop ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<23> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<23> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<24> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[1].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<0> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<0> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<1> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<1> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[2].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<1> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<1> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<2> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<2> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[3].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<2> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<2> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<3> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<3> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[4].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<3> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<3> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<4> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<4> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[5].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<4> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<4> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<5> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<5> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[6].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<5> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<5> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<6> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<6> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[7].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<6> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<6> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<7> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<7> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[8].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<7> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<7> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<8> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<8> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[9].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<8> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<8> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<9> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<9> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[10].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<9> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<9> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<10> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<10> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[11].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<10> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<10> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<11> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<11> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[12].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<11> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<11> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<12> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<12> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[13].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<12> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<12> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<13> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<13> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[14].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<13> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<13> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<14> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<14> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[15].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<14> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<14> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<15> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<15> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[16].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<15> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<15> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<16> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<16> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[17].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<16> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<16> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<17> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<17> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[18].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<17> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<17> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<18> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<18> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[19].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<18> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<18> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<19> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<19> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[20].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<19> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<19> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<20> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<20> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[21].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<20> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<20> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<21> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<21> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[22].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<21> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<21> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<22> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<22> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[23].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<22> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<22> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<23> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<23> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[1].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<0> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<1> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<1> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[2].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<1> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<2> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<2> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[3].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<2> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<3> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<3> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[4].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<3> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<4> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<4> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[5].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<4> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<5> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<5> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[6].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<5> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<6> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<6> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[7].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<6> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<7> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<7> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[8].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<7> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<8> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<8> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[9].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<8> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<9> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<9> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[10].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<9> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<10> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<10> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[11].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<10> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<11> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<11> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[12].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<11> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<12> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<12> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[13].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<12> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<13> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<13> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[14].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<13> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<14> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<14> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[15].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<14> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<15> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<15> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[16].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<15> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<16> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<16> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[17].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<16> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<17> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<17> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[18].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<17> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<18> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<18> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[19].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<18> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<19> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<19> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[20].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<19> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<20> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<20> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[21].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<20> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<21> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<21> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[22].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<21> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<22> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<22> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[23].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<22> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<23> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<23> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carryxortop ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<23> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<24> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q_c_out.i_simple.add_q_cout.q_c_outreg/opt_has_pipe.first_q_0 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<24> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q_c_out.i_simple.add_q_cout.q_c_outreg/opt_has_pipe.first_q ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_need_mux.carrymux0 ( + .CI(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/inv_o [29]), + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<1> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<0> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<0> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.carryxor0 ( + .CI(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/inv_o [29]), + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<0> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<0> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.muxtop.carrymuxtop ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<23> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<23> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<24> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[1].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<0> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<0> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<1> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<1> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[2].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<1> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<1> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<2> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<2> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[3].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<2> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<2> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<3> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<3> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[4].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<3> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<3> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<4> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<4> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[5].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<4> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<4> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<5> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<5> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[6].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<5> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<5> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<6> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<6> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[7].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<6> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<6> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<7> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<7> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[8].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<7> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<7> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<8> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<8> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[9].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<8> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<8> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<9> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<9> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[10].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<9> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<9> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<10> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<10> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[11].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<10> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<10> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<11> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<11> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[12].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<11> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<11> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<12> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<12> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[13].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<12> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<12> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<13> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<13> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[14].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<13> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<13> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<14> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<14> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[15].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<14> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<14> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<15> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<15> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[16].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<15> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<15> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<16> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<16> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[17].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<16> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<16> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<17> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<17> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[18].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<17> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<17> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<18> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<18> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[19].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<18> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<18> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<19> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<19> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[20].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<19> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<19> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<20> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<20> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[21].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<20> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<20> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<21> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<21> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[22].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<21> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<21> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<22> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<22> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[23].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<22> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<22> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<23> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<23> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[1].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<0> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<1> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<1> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[2].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<1> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<2> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<2> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[3].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<2> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<3> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<3> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[4].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<3> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<4> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<4> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[5].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<4> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<5> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<5> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[6].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<5> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<6> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<6> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[7].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<6> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<7> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<7> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[8].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<7> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<8> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<8> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[9].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<8> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<9> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<9> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[10].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<9> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<10> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<10> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[11].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<10> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<11> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<11> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[12].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<11> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<12> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<12> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[13].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<12> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<13> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<13> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[14].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<13> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<14> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<14> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[15].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<14> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<15> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<15> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[16].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<15> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<16> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<16> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[17].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<16> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<17> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<17> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[18].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<17> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<18> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<18> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[19].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<18> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<19> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<19> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[20].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<19> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<20> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<20> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[21].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<20> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<21> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<21> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[22].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<21> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<22> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<22> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[23].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<22> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<23> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<23> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carryxortop ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<23> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<24> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q_c_out.i_simple.add_q_cout.q_c_outreg/opt_has_pipe.first_q_0 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<24> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q_c_out.i_simple.add_q_cout.q_c_outreg/opt_has_pipe.first_q ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_need_mux.carrymux0 ( + .CI(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/inv_o [28]), + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<2> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<0> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<0> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.carryxor0 ( + .CI(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/inv_o [28]), + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<0> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<0> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.muxtop.carrymuxtop ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<23> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<23> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<24> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[1].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<0> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<0> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<1> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<1> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[2].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<1> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<1> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<2> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<2> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[3].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<2> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<2> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<3> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<3> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[4].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<3> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<3> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<4> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<4> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[5].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<4> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<4> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<5> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<5> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[6].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<5> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<5> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<6> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<6> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[7].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<6> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<6> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<7> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<7> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[8].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<7> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<7> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<8> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<8> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[9].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<8> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<8> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<9> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<9> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[10].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<9> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<9> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<10> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<10> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[11].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<10> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<10> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<11> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<11> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[12].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<11> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<11> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<12> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<12> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[13].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<12> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<12> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<13> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<13> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[14].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<13> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<13> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<14> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<14> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[15].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<14> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<14> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<15> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<15> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[16].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<15> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<15> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<16> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<16> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[17].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<16> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<16> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<17> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<17> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[18].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<17> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<17> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<18> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<18> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[19].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<18> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<18> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<19> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<19> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[20].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<19> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<19> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<20> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<20> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[21].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<20> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<20> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<21> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<21> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[22].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<21> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<21> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<22> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<22> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[23].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<22> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<22> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<23> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<23> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[1].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<0> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<1> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<1> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[2].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<1> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<2> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<2> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[3].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<2> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<3> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<3> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[4].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<3> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<4> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<4> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[5].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<4> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<5> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<5> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[6].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<5> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<6> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<6> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[7].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<6> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<7> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<7> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[8].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<7> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<8> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<8> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[9].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<8> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<9> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<9> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[10].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<9> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<10> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<10> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[11].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<10> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<11> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<11> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[12].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<11> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<12> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<12> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[13].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<12> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<13> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<13> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[14].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<13> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<14> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<14> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[15].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<14> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<15> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<15> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[16].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<15> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<16> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<16> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[17].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<16> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<17> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<17> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[18].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<17> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<18> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<18> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[19].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<18> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<19> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<19> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[20].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<19> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<20> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<20> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[21].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<20> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<21> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<21> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[22].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<21> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<22> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<22> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[23].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<22> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<23> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<23> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carryxortop ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<23> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<24> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q_c_out.i_simple.add_q_cout.q_c_outreg/opt_has_pipe.first_q_0 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<24> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q_c_out.i_simple.add_q_cout.q_c_outreg/opt_has_pipe.first_q ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_need_mux.carrymux0 ( + .CI(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/inv_o [27]), + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<3> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<0> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<0> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.carryxor0 ( + .CI(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/inv_o [27]), + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<0> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<0> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.muxtop.carrymuxtop ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<23> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<23> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<24> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[1].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<0> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<0> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<1> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<1> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[2].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<1> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<1> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<2> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<2> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[3].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<2> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<2> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<3> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<3> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[4].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<3> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<3> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<4> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<4> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[5].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<4> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<4> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<5> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<5> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[6].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<5> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<5> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<6> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<6> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[7].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<6> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<6> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<7> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<7> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[8].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<7> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<7> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<8> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<8> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[9].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<8> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<8> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<9> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<9> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[10].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<9> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<9> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<10> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<10> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[11].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<10> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<10> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<11> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<11> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[12].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<11> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<11> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<12> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<12> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[13].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<12> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<12> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<13> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<13> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[14].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<13> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<13> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<14> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<14> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[15].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<14> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<14> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<15> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<15> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[16].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<15> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<15> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<16> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<16> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[17].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<16> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<16> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<17> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<17> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[18].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<17> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<17> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<18> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<18> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[19].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<18> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<18> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<19> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<19> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[20].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<19> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<19> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<20> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<20> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[21].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<20> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<20> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<21> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<21> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[22].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<21> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<21> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<22> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<22> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[23].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<22> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<22> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<23> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<23> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[1].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<0> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<1> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<1> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[2].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<1> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<2> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<2> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[3].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<2> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<3> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<3> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[4].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<3> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<4> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<4> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[5].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<4> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<5> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<5> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[6].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<5> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<6> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<6> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[7].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<6> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<7> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<7> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[8].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<7> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<8> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<8> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[9].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<8> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<9> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<9> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[10].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<9> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<10> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<10> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[11].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<10> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<11> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<11> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[12].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<11> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<12> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<12> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[13].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<12> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<13> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<13> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[14].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<13> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<14> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<14> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[15].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<14> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<15> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<15> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[16].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<15> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<16> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<16> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[17].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<16> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<17> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<17> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[18].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<17> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<18> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<18> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[19].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<18> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<19> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<19> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[20].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<19> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<20> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<20> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[21].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<20> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<21> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<21> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[22].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<21> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<22> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<22> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[23].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<22> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<23> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<23> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carryxortop ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<23> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<24> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q_c_out.i_simple.add_q_cout.q_c_outreg/opt_has_pipe.first_q_0 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<24> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q_c_out.i_simple.add_q_cout.q_c_outreg/opt_has_pipe.first_q ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_need_mux.carrymux0 ( + .CI(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/inv_o [26]), + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<4> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<0> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<0> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.carryxor0 ( + .CI(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/inv_o [26]), + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<0> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<0> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.muxtop.carrymuxtop ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<23> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<23> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<24> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[1].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<0> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<0> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<1> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<1> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[2].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<1> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<1> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<2> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<2> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[3].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<2> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<2> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<3> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<3> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[4].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<3> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<3> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<4> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<4> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[5].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<4> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<4> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<5> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<5> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[6].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<5> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<5> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<6> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<6> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[7].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<6> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<6> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<7> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<7> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[8].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<7> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<7> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<8> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<8> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[9].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<8> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<8> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<9> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<9> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[10].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<9> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<9> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<10> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<10> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[11].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<10> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<10> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<11> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<11> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[12].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<11> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<11> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<12> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<12> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[13].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<12> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<12> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<13> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<13> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[14].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<13> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<13> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<14> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<14> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[15].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<14> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<14> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<15> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<15> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[16].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<15> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<15> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<16> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<16> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[17].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<16> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<16> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<17> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<17> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[18].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<17> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<17> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<18> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<18> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[19].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<18> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<18> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<19> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<19> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[20].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<19> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<19> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<20> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<20> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[21].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<20> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<20> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<21> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<21> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[22].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<21> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<21> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<22> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<22> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[23].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<22> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<22> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<23> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<23> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[1].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<0> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<1> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<1> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[2].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<1> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<2> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<2> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[3].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<2> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<3> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<3> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[4].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<3> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<4> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<4> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[5].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<4> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<5> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<5> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[6].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<5> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<6> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<6> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[7].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<6> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<7> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<7> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[8].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<7> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<8> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<8> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[9].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<8> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<9> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<9> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[10].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<9> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<10> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<10> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[11].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<10> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<11> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<11> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[12].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<11> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<12> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<12> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[13].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<12> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<13> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<13> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[14].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<13> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<14> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<14> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[15].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<14> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<15> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<15> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[16].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<15> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<16> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<16> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[17].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<16> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<17> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<17> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[18].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<17> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<18> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<18> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[19].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<18> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<19> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<19> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[20].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<19> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<20> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<20> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[21].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<20> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<21> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<21> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[22].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<21> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<22> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<22> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[23].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<22> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<23> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<23> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carryxortop ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<23> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<24> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q_c_out.i_simple.add_q_cout.q_c_outreg/opt_has_pipe.first_q_0 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<24> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q_c_out.i_simple.add_q_cout.q_c_outreg/opt_has_pipe.first_q ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_need_mux.carrymux0 ( + .CI(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/inv_o [25]), + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<5> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<0> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<0> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.carryxor0 ( + .CI(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/inv_o [25]), + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<0> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<0> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.muxtop.carrymuxtop ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<23> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<23> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<24> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[1].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<0> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<0> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<1> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<1> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[2].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<1> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<1> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<2> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<2> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[3].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<2> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<2> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<3> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<3> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[4].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<3> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<3> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<4> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<4> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[5].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<4> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<4> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<5> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<5> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[6].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<5> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<5> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<6> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<6> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[7].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<6> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<6> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<7> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<7> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[8].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<7> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<7> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<8> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<8> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[9].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<8> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<8> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<9> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<9> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[10].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<9> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<9> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<10> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<10> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[11].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<10> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<10> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<11> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<11> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[12].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<11> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<11> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<12> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<12> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[13].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<12> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<12> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<13> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<13> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[14].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<13> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<13> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<14> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<14> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[15].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<14> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<14> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<15> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<15> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[16].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<15> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<15> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<16> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<16> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[17].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<16> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<16> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<17> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<17> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[18].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<17> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<17> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<18> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<18> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[19].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<18> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<18> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<19> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<19> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[20].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<19> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<19> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<20> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<20> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[21].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<20> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<20> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<21> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<21> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[22].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<21> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<21> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<22> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<22> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[23].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<22> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<22> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<23> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<23> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[1].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<0> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<1> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<1> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[2].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<1> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<2> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<2> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[3].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<2> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<3> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<3> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[4].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<3> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<4> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<4> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[5].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<4> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<5> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<5> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[6].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<5> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<6> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<6> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[7].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<6> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<7> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<7> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[8].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<7> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<8> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<8> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[9].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<8> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<9> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<9> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[10].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<9> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<10> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<10> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[11].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<10> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<11> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<11> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[12].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<11> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<12> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<12> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[13].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<12> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<13> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<13> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[14].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<13> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<14> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<14> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[15].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<14> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<15> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<15> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[16].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<15> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<16> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<16> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[17].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<16> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<17> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<17> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[18].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<17> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<18> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<18> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[19].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<18> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<19> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<19> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[20].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<19> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<20> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<20> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[21].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<20> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<21> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<21> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[22].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<21> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<22> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<22> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[23].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<22> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<23> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<23> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carryxortop ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<23> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<24> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q_c_out.i_simple.add_q_cout.q_c_outreg/opt_has_pipe.first_q_0 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<24> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q_c_out.i_simple.add_q_cout.q_c_outreg/opt_has_pipe.first_q ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_need_mux.carrymux0 ( + .CI(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/inv_o [24]), + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<6> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<0> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<0> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.carryxor0 ( + .CI(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/inv_o [24]), + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<0> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<0> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.muxtop.carrymuxtop ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<23> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<23> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<24> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[1].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<0> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<0> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<1> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<1> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[2].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<1> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<1> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<2> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<2> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[3].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<2> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<2> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<3> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<3> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[4].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<3> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<3> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<4> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<4> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[5].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<4> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<4> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<5> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<5> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[6].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<5> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<5> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<6> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<6> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[7].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<6> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<6> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<7> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<7> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[8].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<7> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<7> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<8> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<8> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[9].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<8> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<8> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<9> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<9> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[10].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<9> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<9> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<10> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<10> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[11].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<10> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<10> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<11> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<11> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[12].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<11> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<11> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<12> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<12> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[13].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<12> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<12> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<13> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<13> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[14].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<13> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<13> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<14> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<14> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[15].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<14> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<14> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<15> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<15> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[16].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<15> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<15> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<16> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<16> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[17].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<16> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<16> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<17> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<17> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[18].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<17> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<17> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<18> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<18> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[19].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<18> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<18> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<19> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<19> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[20].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<19> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<19> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<20> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<20> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[21].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<20> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<20> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<21> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<21> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[22].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<21> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<21> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<22> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<22> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[23].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<22> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<22> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<23> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<23> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[1].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<0> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<1> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<1> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[2].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<1> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<2> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<2> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[3].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<2> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<3> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<3> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[4].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<3> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<4> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<4> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[5].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<4> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<5> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<5> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[6].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<5> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<6> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<6> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[7].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<6> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<7> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<7> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[8].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<7> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<8> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<8> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[9].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<8> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<9> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<9> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[10].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<9> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<10> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<10> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[11].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<10> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<11> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<11> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[12].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<11> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<12> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<12> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[13].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<12> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<13> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<13> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[14].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<13> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<14> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<14> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[15].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<14> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<15> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<15> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[16].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<15> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<16> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<16> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[17].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<16> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<17> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<17> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[18].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<17> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<18> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<18> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[19].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<18> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<19> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<19> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[20].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<19> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<20> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<20> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[21].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<20> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<21> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<21> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[22].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<21> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<22> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<22> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[23].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<22> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<23> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<23> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carryxortop ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<23> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<24> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q_c_out.i_simple.add_q_cout.q_c_outreg/opt_has_pipe.first_q_0 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<24> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q_c_out.i_simple.add_q_cout.q_c_outreg/opt_has_pipe.first_q ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_need_mux.carrymux0 ( + .CI(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/inv_o [23]), + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<7> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<0> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<0> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.carryxor0 ( + .CI(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/inv_o [23]), + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<0> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<0> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.muxtop.carrymuxtop ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<23> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<23> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<24> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[1].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<0> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<0> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<1> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<1> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[2].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<1> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<1> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<2> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<2> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[3].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<2> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<2> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<3> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<3> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[4].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<3> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<3> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<4> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<4> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[5].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<4> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<4> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<5> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<5> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[6].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<5> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<5> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<6> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<6> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[7].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<6> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<6> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<7> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<7> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[8].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<7> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<7> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<8> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<8> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[9].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<8> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<8> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<9> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<9> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[10].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<9> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<9> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<10> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<10> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[11].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<10> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<10> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<11> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<11> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[12].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<11> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<11> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<12> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<12> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[13].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<12> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<12> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<13> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<13> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[14].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<13> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<13> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<14> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<14> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[15].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<14> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<14> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<15> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<15> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[16].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<15> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<15> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<16> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<16> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[17].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<16> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<16> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<17> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<17> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[18].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<17> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<17> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<18> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<18> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[19].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<18> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<18> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<19> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<19> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[20].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<19> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<19> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<20> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<20> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[21].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<20> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<20> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<21> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<21> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[22].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<21> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<21> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<22> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<22> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[23].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<22> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<22> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<23> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<23> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[1].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<0> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<1> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<1> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[2].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<1> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<2> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<2> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[3].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<2> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<3> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<3> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[4].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<3> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<4> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<4> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[5].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<4> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<5> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<5> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[6].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<5> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<6> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<6> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[7].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<6> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<7> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<7> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[8].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<7> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<8> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<8> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[9].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<8> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<9> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<9> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[10].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<9> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<10> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<10> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[11].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<10> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<11> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<11> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[12].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<11> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<12> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<12> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[13].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<12> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<13> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<13> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[14].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<13> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<14> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<14> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[15].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<14> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<15> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<15> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[16].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<15> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<16> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<16> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[17].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<16> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<17> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<17> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[18].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<17> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<18> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<18> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[19].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<18> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<19> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<19> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[20].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<19> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<20> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<20> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[21].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<20> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<21> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<21> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[22].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<21> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<22> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<22> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[23].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<22> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<23> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<23> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carryxortop ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<23> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<24> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q_c_out.i_simple.add_q_cout.q_c_outreg/opt_has_pipe.first_q_0 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<24> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q_c_out.i_simple.add_q_cout.q_c_outreg/opt_has_pipe.first_q ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_need_mux.carrymux0 ( + .CI(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/inv_o [22]), + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<8> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<0> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<0> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.carryxor0 ( + .CI(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/inv_o [22]), + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<0> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<0> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.muxtop.carrymuxtop ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<23> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<23> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<24> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[1].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<0> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<0> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<1> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<1> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[2].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<1> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<1> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<2> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<2> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[3].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<2> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<2> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<3> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<3> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[4].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<3> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<3> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<4> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<4> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[5].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<4> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<4> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<5> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<5> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[6].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<5> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<5> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<6> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<6> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[7].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<6> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<6> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<7> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<7> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[8].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<7> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<7> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<8> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<8> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[9].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<8> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<8> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<9> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<9> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[10].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<9> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<9> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<10> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<10> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[11].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<10> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<10> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<11> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<11> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[12].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<11> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<11> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<12> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<12> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[13].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<12> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<12> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<13> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<13> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[14].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<13> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<13> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<14> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<14> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[15].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<14> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<14> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<15> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<15> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[16].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<15> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<15> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<16> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<16> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[17].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<16> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<16> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<17> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<17> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[18].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<17> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<17> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<18> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<18> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[19].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<18> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<18> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<19> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<19> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[20].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<19> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<19> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<20> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<20> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[21].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<20> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<20> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<21> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<21> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[22].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<21> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<21> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<22> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<22> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[23].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<22> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<22> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<23> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<23> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[1].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<0> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<1> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<1> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[2].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<1> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<2> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<2> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[3].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<2> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<3> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<3> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[4].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<3> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<4> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<4> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[5].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<4> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<5> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<5> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[6].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<5> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<6> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<6> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[7].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<6> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<7> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<7> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[8].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<7> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<8> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<8> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[9].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<8> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<9> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<9> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[10].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<9> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<10> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<10> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[11].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<10> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<11> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<11> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[12].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<11> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<12> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<12> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[13].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<12> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<13> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<13> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[14].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<13> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<14> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<14> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[15].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<14> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<15> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<15> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[16].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<15> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<16> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<16> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[17].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<16> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<17> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<17> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[18].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<17> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<18> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<18> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[19].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<18> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<19> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<19> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[20].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<19> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<20> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<20> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[21].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<20> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<21> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<21> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[22].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<21> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<22> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<22> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[23].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<22> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<23> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<23> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carryxortop ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<23> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<24> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q_c_out.i_simple.add_q_cout.q_c_outreg/opt_has_pipe.first_q_0 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<24> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q_c_out.i_simple.add_q_cout.q_c_outreg/opt_has_pipe.first_q ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_need_mux.carrymux0 ( + .CI(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/inv_o [21]), + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<9> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<0> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<0> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.carryxor0 ( + .CI(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/inv_o [21]), + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<0> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<0> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.muxtop.carrymuxtop ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<23> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<23> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<24> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[1].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<0> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<0> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<1> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<1> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[2].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<1> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<1> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<2> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<2> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[3].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<2> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<2> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<3> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<3> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[4].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<3> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<3> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<4> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<4> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[5].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<4> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<4> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<5> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<5> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[6].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<5> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<5> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<6> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<6> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[7].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<6> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<6> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<7> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<7> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[8].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<7> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<7> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<8> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<8> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[9].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<8> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<8> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<9> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<9> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[10].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<9> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<9> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<10> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<10> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[11].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<10> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<10> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<11> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<11> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[12].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<11> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<11> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<12> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<12> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[13].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<12> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<12> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<13> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<13> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[14].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<13> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<13> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<14> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<14> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[15].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<14> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<14> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<15> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<15> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[16].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<15> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<15> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<16> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<16> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[17].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<16> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<16> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<17> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<17> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[18].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<17> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<17> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<18> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<18> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[19].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<18> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<18> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<19> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<19> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[20].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<19> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<19> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<20> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<20> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[21].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<20> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<20> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<21> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<21> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[22].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<21> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<21> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<22> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<22> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[23].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<22> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<22> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<23> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<23> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[1].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<0> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<1> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<1> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[2].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<1> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<2> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<2> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[3].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<2> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<3> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<3> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[4].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<3> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<4> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<4> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[5].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<4> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<5> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<5> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[6].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<5> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<6> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<6> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[7].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<6> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<7> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<7> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[8].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<7> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<8> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<8> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[9].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<8> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<9> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<9> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[10].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<9> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<10> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<10> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[11].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<10> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<11> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<11> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[12].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<11> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<12> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<12> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[13].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<12> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<13> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<13> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[14].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<13> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<14> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<14> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[15].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<14> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<15> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<15> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[16].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<15> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<16> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<16> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[17].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<16> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<17> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<17> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[18].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<17> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<18> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<18> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[19].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<18> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<19> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<19> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[20].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<19> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<20> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<20> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[21].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<20> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<21> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<21> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[22].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<21> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<22> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<22> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[23].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<22> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<23> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<23> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carryxortop ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<23> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<24> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q_c_out.i_simple.add_q_cout.q_c_outreg/opt_has_pipe.first_q_0 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<24> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q_c_out.i_simple.add_q_cout.q_c_outreg/opt_has_pipe.first_q ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_need_mux.carrymux0 ( + .CI(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/inv_o [20]), + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<10> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<0> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<0> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.carryxor0 ( + .CI(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/inv_o [20]), + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<0> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<0> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.muxtop.carrymuxtop ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<23> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<23> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<24> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[1].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<0> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<0> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<1> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<1> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[2].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<1> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<1> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<2> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<2> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[3].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<2> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<2> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<3> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<3> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[4].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<3> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<3> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<4> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<4> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[5].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<4> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<4> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<5> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<5> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[6].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<5> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<5> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<6> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<6> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[7].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<6> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<6> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<7> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<7> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[8].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<7> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<7> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<8> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<8> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[9].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<8> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<8> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<9> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<9> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[10].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<9> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<9> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<10> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<10> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[11].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<10> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<10> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<11> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<11> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[12].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<11> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<11> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<12> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<12> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[13].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<12> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<12> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<13> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<13> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[14].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<13> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<13> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<14> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<14> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[15].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<14> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<14> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<15> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<15> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[16].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<15> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<15> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<16> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<16> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[17].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<16> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<16> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<17> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<17> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[18].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<17> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<17> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<18> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<18> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[19].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<18> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<18> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<19> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<19> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[20].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<19> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<19> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<20> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<20> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[21].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<20> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<20> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<21> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<21> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[22].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<21> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<21> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<22> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<22> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[23].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<22> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<22> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<23> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<23> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[1].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<0> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<1> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<1> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[2].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<1> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<2> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<2> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[3].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<2> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<3> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<3> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[4].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<3> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<4> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<4> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[5].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<4> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<5> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<5> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[6].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<5> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<6> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<6> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[7].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<6> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<7> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<7> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[8].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<7> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<8> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<8> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[9].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<8> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<9> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<9> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[10].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<9> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<10> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<10> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[11].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<10> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<11> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<11> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[12].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<11> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<12> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<12> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[13].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<12> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<13> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<13> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[14].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<13> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<14> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<14> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[15].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<14> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<15> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<15> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[16].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<15> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<16> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<16> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[17].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<16> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<17> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<17> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[18].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<17> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<18> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<18> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[19].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<18> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<19> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<19> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[20].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<19> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<20> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<20> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[21].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<20> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<21> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<21> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[22].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<21> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<22> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<22> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[23].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<22> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<23> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<23> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carryxortop ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<23> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<24> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q_c_out.i_simple.add_q_cout.q_c_outreg/opt_has_pipe.first_q_0 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<24> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q_c_out.i_simple.add_q_cout.q_c_outreg/opt_has_pipe.first_q ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_need_mux.carrymux0 ( + .CI(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/inv_o [19]), + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<11> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<0> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<0> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.carryxor0 ( + .CI(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/inv_o [19]), + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<0> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<0> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.muxtop.carrymuxtop ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<23> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<23> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<24> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[1].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<0> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<0> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<1> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<1> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[2].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<1> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<1> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<2> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<2> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[3].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<2> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<2> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<3> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<3> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[4].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<3> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<3> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<4> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<4> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[5].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<4> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<4> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<5> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<5> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[6].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<5> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<5> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<6> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<6> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[7].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<6> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<6> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<7> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<7> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[8].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<7> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<7> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<8> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<8> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[9].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<8> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<8> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<9> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<9> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[10].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<9> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<9> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<10> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<10> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[11].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<10> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<10> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<11> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<11> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[12].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<11> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<11> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<12> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<12> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[13].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<12> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<12> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<13> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<13> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[14].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<13> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<13> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<14> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<14> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[15].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<14> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<14> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<15> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<15> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[16].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<15> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<15> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<16> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<16> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[17].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<16> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<16> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<17> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<17> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[18].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<17> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<17> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<18> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<18> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[19].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<18> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<18> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<19> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<19> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[20].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<19> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<19> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<20> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<20> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[21].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<20> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<20> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<21> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<21> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[22].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<21> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<21> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<22> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<22> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[23].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<22> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<22> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<23> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<23> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[1].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<0> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<1> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<1> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[2].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<1> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<2> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<2> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[3].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<2> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<3> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<3> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[4].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<3> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<4> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<4> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[5].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<4> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<5> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<5> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[6].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<5> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<6> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<6> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[7].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<6> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<7> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<7> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[8].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<7> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<8> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<8> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[9].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<8> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<9> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<9> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[10].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<9> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<10> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<10> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[11].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<10> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<11> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<11> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[12].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<11> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<12> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<12> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[13].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<12> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<13> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<13> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[14].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<13> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<14> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<14> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[15].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<14> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<15> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<15> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[16].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<15> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<16> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<16> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[17].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<16> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<17> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<17> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[18].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<17> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<18> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<18> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[19].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<18> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<19> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<19> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[20].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<19> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<20> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<20> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[21].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<20> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<21> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<21> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[22].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<21> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<22> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<22> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[23].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<22> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<23> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<23> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carryxortop ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<23> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<24> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q_c_out.i_simple.add_q_cout.q_c_outreg/opt_has_pipe.first_q_0 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<24> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q_c_out.i_simple.add_q_cout.q_c_outreg/opt_has_pipe.first_q ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_need_mux.carrymux0 ( + .CI(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/inv_o [18]), + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<12> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<0> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<0> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.carryxor0 ( + .CI(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/inv_o [18]), + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<0> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<0> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.muxtop.carrymuxtop ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<23> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<23> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<24> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[1].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<0> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<0> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<1> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<1> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[2].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<1> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<1> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<2> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<2> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[3].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<2> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<2> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<3> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<3> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[4].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<3> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<3> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<4> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<4> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[5].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<4> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<4> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<5> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<5> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[6].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<5> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<5> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<6> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<6> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[7].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<6> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<6> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<7> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<7> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[8].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<7> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<7> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<8> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<8> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[9].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<8> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<8> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<9> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<9> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[10].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<9> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<9> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<10> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<10> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[11].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<10> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<10> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<11> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<11> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[12].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<11> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<11> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<12> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<12> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[13].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<12> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<12> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<13> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<13> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[14].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<13> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<13> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<14> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<14> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[15].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<14> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<14> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<15> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<15> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[16].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<15> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<15> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<16> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<16> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[17].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<16> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<16> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<17> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<17> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[18].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<17> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<17> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<18> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<18> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[19].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<18> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<18> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<19> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<19> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[20].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<19> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<19> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<20> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<20> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[21].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<20> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<20> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<21> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<21> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[22].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<21> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<21> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<22> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<22> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[23].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<22> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<22> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<23> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<23> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[1].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<0> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<1> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<1> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[2].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<1> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<2> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<2> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[3].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<2> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<3> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<3> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[4].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<3> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<4> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<4> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[5].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<4> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<5> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<5> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[6].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<5> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<6> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<6> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[7].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<6> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<7> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<7> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[8].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<7> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<8> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<8> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[9].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<8> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<9> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<9> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[10].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<9> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<10> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<10> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[11].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<10> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<11> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<11> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[12].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<11> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<12> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<12> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[13].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<12> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<13> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<13> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[14].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<13> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<14> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<14> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[15].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<14> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<15> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<15> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[16].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<15> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<16> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<16> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[17].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<16> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<17> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<17> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[18].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<17> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<18> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<18> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[19].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<18> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<19> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<19> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[20].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<19> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<20> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<20> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[21].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<20> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<21> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<21> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[22].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<21> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<22> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<22> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[23].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<22> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<23> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<23> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carryxortop ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<23> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<24> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q_c_out.i_simple.add_q_cout.q_c_outreg/opt_has_pipe.first_q_0 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<24> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q_c_out.i_simple.add_q_cout.q_c_outreg/opt_has_pipe.first_q ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_need_mux.carrymux0 ( + .CI(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/inv_o [17]), + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<13> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<0> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<0> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.carryxor0 ( + .CI(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/inv_o [17]), + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<0> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<0> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.muxtop.carrymuxtop ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<23> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<23> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<24> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[1].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<0> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<0> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<1> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<1> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[2].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<1> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<1> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<2> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<2> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[3].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<2> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<2> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<3> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<3> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[4].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<3> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<3> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<4> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<4> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[5].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<4> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<4> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<5> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<5> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[6].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<5> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<5> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<6> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<6> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[7].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<6> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<6> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<7> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<7> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[8].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<7> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<7> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<8> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<8> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[9].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<8> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<8> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<9> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<9> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[10].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<9> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<9> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<10> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<10> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[11].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<10> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<10> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<11> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<11> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[12].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<11> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<11> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<12> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<12> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[13].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<12> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<12> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<13> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<13> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[14].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<13> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<13> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<14> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<14> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[15].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<14> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<14> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<15> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<15> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[16].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<15> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<15> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<16> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<16> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[17].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<16> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<16> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<17> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<17> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[18].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<17> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<17> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<18> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<18> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[19].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<18> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<18> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<19> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<19> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[20].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<19> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<19> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<20> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<20> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[21].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<20> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<20> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<21> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<21> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[22].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<21> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<21> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<22> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<22> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[23].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<22> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<22> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<23> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<23> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[1].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<0> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<1> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<1> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[2].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<1> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<2> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<2> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[3].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<2> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<3> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<3> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[4].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<3> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<4> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<4> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[5].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<4> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<5> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<5> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[6].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<5> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<6> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<6> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[7].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<6> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<7> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<7> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[8].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<7> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<8> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<8> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[9].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<8> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<9> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<9> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[10].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<9> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<10> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<10> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[11].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<10> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<11> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<11> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[12].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<11> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<12> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<12> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[13].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<12> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<13> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<13> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[14].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<13> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<14> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<14> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[15].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<14> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<15> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<15> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[16].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<15> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<16> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<16> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[17].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<16> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<17> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<17> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[18].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<17> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<18> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<18> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[19].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<18> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<19> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<19> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[20].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<19> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<20> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<20> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[21].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<20> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<21> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<21> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[22].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<21> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<22> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<22> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[23].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<22> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<23> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<23> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carryxortop ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<23> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<24> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q_c_out.i_simple.add_q_cout.q_c_outreg/opt_has_pipe.first_q_0 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<24> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q_c_out.i_simple.add_q_cout.q_c_outreg/opt_has_pipe.first_q ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_need_mux.carrymux0 ( + .CI(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/inv_o [16]), + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<14> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<0> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<0> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.carryxor0 ( + .CI(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/inv_o [16]), + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<0> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<0> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.muxtop.carrymuxtop ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<23> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<23> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<24> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[1].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<0> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<0> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<1> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<1> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[2].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<1> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<1> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<2> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<2> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[3].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<2> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<2> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<3> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<3> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[4].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<3> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<3> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<4> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<4> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[5].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<4> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<4> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<5> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<5> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[6].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<5> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<5> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<6> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<6> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[7].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<6> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<6> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<7> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<7> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[8].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<7> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<7> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<8> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<8> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[9].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<8> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<8> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<9> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<9> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[10].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<9> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<9> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<10> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<10> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[11].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<10> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<10> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<11> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<11> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[12].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<11> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<11> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<12> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<12> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[13].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<12> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<12> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<13> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<13> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[14].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<13> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<13> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<14> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<14> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[15].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<14> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<14> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<15> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<15> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[16].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<15> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<15> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<16> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<16> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[17].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<16> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<16> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<17> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<17> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[18].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<17> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<17> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<18> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<18> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[19].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<18> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<18> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<19> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<19> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[20].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<19> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<19> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<20> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<20> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[21].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<20> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<20> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<21> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<21> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[22].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<21> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<21> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<22> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<22> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[23].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<22> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<22> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<23> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<23> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[1].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<0> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<1> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<1> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[2].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<1> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<2> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<2> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[3].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<2> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<3> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<3> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[4].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<3> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<4> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<4> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[5].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<4> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<5> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<5> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[6].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<5> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<6> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<6> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[7].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<6> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<7> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<7> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[8].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<7> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<8> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<8> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[9].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<8> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<9> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<9> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[10].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<9> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<10> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<10> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[11].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<10> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<11> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<11> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[12].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<11> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<12> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<12> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[13].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<12> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<13> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<13> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[14].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<13> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<14> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<14> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[15].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<14> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<15> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<15> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[16].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<15> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<16> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<16> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[17].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<16> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<17> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<17> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[18].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<17> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<18> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<18> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[19].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<18> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<19> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<19> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[20].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<19> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<20> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<20> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[21].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<20> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<21> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<21> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[22].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<21> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<22> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<22> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[23].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<22> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<23> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<23> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carryxortop ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<23> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<24> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q_c_out.i_simple.add_q_cout.q_c_outreg/opt_has_pipe.first_q_0 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<24> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q_c_out.i_simple.add_q_cout.q_c_outreg/opt_has_pipe.first_q ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_need_mux.carrymux0 ( + .CI(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/inv_o [15]), + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<15> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<0> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<0> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.carryxor0 ( + .CI(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/inv_o [15]), + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<0> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<0> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.muxtop.carrymuxtop ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<23> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<23> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<24> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[1].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<0> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<0> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<1> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<1> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[2].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<1> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<1> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<2> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<2> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[3].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<2> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<2> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<3> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<3> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[4].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<3> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<3> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<4> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<4> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[5].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<4> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<4> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<5> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<5> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[6].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<5> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<5> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<6> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<6> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[7].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<6> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<6> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<7> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<7> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[8].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<7> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<7> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<8> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<8> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[9].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<8> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<8> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<9> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<9> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[10].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<9> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<9> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<10> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<10> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[11].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<10> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<10> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<11> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<11> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[12].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<11> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<11> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<12> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<12> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[13].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<12> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<12> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<13> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<13> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[14].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<13> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<13> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<14> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<14> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[15].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<14> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<14> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<15> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<15> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[16].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<15> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<15> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<16> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<16> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[17].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<16> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<16> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<17> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<17> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[18].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<17> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<17> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<18> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<18> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[19].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<18> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<18> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<19> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<19> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[20].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<19> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<19> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<20> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<20> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[21].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<20> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<20> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<21> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<21> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[22].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<21> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<21> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<22> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<22> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[23].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<22> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<22> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<23> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<23> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[1].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<0> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<1> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<1> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[2].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<1> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<2> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<2> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[3].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<2> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<3> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<3> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[4].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<3> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<4> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<4> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[5].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<4> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<5> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<5> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[6].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<5> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<6> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<6> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[7].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<6> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<7> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<7> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[8].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<7> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<8> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<8> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[9].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<8> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<9> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<9> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[10].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<9> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<10> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<10> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[11].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<10> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<11> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<11> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[12].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<11> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<12> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<12> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[13].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<12> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<13> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<13> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[14].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<13> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<14> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<14> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[15].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<14> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<15> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<15> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[16].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<15> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<16> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<16> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[17].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<16> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<17> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<17> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[18].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<17> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<18> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<18> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[19].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<18> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<19> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<19> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[20].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<19> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<20> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<20> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[21].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<20> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<21> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<21> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[22].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<21> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<22> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<22> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[23].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<22> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<23> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<23> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carryxortop ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<23> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<24> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q_c_out.i_simple.add_q_cout.q_c_outreg/opt_has_pipe.first_q_0 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<24> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q_c_out.i_simple.add_q_cout.q_c_outreg/opt_has_pipe.first_q ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_need_mux.carrymux0 ( + .CI(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/inv_o [14]), + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<16> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<0> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<0> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.carryxor0 ( + .CI(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/inv_o [14]), + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<0> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<0> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.muxtop.carrymuxtop ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<23> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<23> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<24> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[1].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<0> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<0> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<1> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<1> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[2].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<1> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<1> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<2> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<2> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[3].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<2> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<2> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<3> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<3> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[4].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<3> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<3> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<4> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<4> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[5].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<4> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<4> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<5> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<5> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[6].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<5> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<5> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<6> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<6> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[7].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<6> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<6> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<7> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<7> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[8].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<7> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<7> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<8> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<8> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[9].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<8> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<8> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<9> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<9> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[10].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<9> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<9> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<10> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<10> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[11].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<10> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<10> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<11> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<11> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[12].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<11> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<11> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<12> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<12> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[13].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<12> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<12> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<13> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<13> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[14].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<13> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<13> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<14> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<14> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[15].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<14> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<14> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<15> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<15> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[16].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<15> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<15> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<16> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<16> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[17].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<16> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<16> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<17> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<17> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[18].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<17> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<17> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<18> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<18> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[19].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<18> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<18> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<19> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<19> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[20].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<19> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<19> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<20> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<20> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[21].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<20> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<20> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<21> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<21> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[22].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<21> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<21> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<22> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<22> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[23].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<22> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<22> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<23> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<23> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[1].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<0> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<1> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<1> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[2].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<1> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<2> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<2> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[3].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<2> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<3> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<3> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[4].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<3> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<4> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<4> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[5].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<4> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<5> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<5> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[6].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<5> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<6> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<6> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[7].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<6> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<7> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<7> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[8].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<7> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<8> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<8> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[9].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<8> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<9> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<9> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[10].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<9> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<10> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<10> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[11].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<10> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<11> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<11> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[12].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<11> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<12> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<12> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[13].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<12> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<13> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<13> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[14].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<13> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<14> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<14> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[15].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<14> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<15> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<15> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[16].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<15> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<16> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<16> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[17].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<16> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<17> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<17> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[18].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<17> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<18> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<18> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[19].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<18> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<19> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<19> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[20].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<19> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<20> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<20> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[21].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<20> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<21> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<21> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[22].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<21> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<22> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<22> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[23].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<22> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<23> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<23> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carryxortop ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<23> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<24> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q_c_out.i_simple.add_q_cout.q_c_outreg/opt_has_pipe.first_q_0 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<24> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q_c_out.i_simple.add_q_cout.q_c_outreg/opt_has_pipe.first_q ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_need_mux.carrymux0 ( + .CI(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/inv_o [13]), + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<17> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<0> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<0> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.carryxor0 ( + .CI(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/inv_o [13]), + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<0> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<0> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.muxtop.carrymuxtop ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<23> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<23> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<24> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[1].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<0> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<0> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<1> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<1> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[2].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<1> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<1> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<2> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<2> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[3].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<2> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<2> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<3> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<3> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[4].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<3> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<3> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<4> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<4> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[5].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<4> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<4> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<5> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<5> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[6].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<5> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<5> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<6> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<6> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[7].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<6> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<6> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<7> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<7> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[8].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<7> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<7> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<8> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<8> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[9].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<8> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<8> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<9> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<9> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[10].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<9> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<9> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<10> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<10> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[11].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<10> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<10> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<11> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<11> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[12].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<11> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<11> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<12> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<12> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[13].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<12> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<12> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<13> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<13> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[14].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<13> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<13> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<14> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<14> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[15].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<14> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<14> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<15> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<15> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[16].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<15> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<15> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<16> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<16> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[17].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<16> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<16> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<17> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<17> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[18].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<17> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<17> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<18> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<18> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[19].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<18> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<18> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<19> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<19> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[20].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<19> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<19> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<20> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<20> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[21].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<20> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<20> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<21> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<21> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[22].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<21> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<21> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<22> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<22> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[23].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<22> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<22> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<23> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<23> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[1].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<0> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<1> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<1> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[2].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<1> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<2> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<2> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[3].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<2> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<3> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<3> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[4].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<3> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<4> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<4> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[5].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<4> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<5> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<5> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[6].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<5> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<6> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<6> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[7].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<6> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<7> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<7> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[8].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<7> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<8> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<8> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[9].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<8> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<9> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<9> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[10].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<9> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<10> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<10> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[11].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<10> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<11> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<11> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[12].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<11> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<12> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<12> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[13].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<12> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<13> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<13> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[14].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<13> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<14> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<14> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[15].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<14> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<15> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<15> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[16].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<15> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<16> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<16> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[17].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<16> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<17> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<17> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[18].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<17> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<18> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<18> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[19].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<18> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<19> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<19> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[20].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<19> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<20> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<20> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[21].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<20> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<21> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<21> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[22].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<21> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<22> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<22> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[23].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<22> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<23> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<23> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carryxortop ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<23> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<24> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q_c_out.i_simple.add_q_cout.q_c_outreg/opt_has_pipe.first_q_0 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<24> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q_c_out.i_simple.add_q_cout.q_c_outreg/opt_has_pipe.first_q ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_need_mux.carrymux0 ( + .CI(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/inv_o [12]), + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<18> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<0> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<0> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.carryxor0 ( + .CI(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/inv_o [12]), + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<0> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<0> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.muxtop.carrymuxtop ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<23> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<23> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<24> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[1].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<0> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<0> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<1> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<1> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[2].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<1> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<1> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<2> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<2> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[3].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<2> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<2> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<3> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<3> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[4].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<3> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<3> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<4> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<4> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[5].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<4> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<4> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<5> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<5> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[6].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<5> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<5> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<6> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<6> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[7].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<6> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<6> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<7> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<7> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[8].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<7> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<7> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<8> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<8> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[9].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<8> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<8> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<9> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<9> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[10].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<9> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<9> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<10> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<10> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[11].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<10> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<10> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<11> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<11> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[12].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<11> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<11> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<12> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<12> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[13].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<12> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<12> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<13> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<13> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[14].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<13> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<13> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<14> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<14> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[15].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<14> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<14> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<15> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<15> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[16].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<15> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<15> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<16> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<16> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[17].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<16> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<16> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<17> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<17> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[18].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<17> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<17> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<18> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<18> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[19].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<18> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<18> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<19> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<19> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[20].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<19> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<19> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<20> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<20> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[21].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<20> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<20> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<21> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<21> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[22].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<21> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<21> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<22> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<22> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[23].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<22> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<22> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<23> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<23> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[1].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<0> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<1> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<1> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[2].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<1> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<2> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<2> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[3].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<2> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<3> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<3> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[4].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<3> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<4> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<4> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[5].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<4> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<5> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<5> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[6].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<5> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<6> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<6> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[7].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<6> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<7> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<7> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[8].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<7> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<8> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<8> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[9].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<8> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<9> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<9> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[10].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<9> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<10> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<10> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[11].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<10> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<11> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<11> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[12].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<11> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<12> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<12> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[13].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<12> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<13> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<13> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[14].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<13> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<14> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<14> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[15].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<14> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<15> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<15> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[16].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<15> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<16> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<16> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[17].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<16> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<17> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<17> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[18].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<17> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<18> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<18> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[19].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<18> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<19> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<19> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[20].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<19> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<20> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<20> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[21].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<20> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<21> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<21> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[22].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<21> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<22> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<22> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[23].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<22> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<23> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<23> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carryxortop ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<23> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<24> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q_c_out.i_simple.add_q_cout.q_c_outreg/opt_has_pipe.first_q_0 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<24> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q_c_out.i_simple.add_q_cout.q_c_outreg/opt_has_pipe.first_q ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_need_mux.carrymux0 ( + .CI(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/inv_o [11]), + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<19> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<0> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<0> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.carryxor0 ( + .CI(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/inv_o [11]), + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<0> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<0> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.muxtop.carrymuxtop ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<23> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<23> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<24> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[1].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<0> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<0> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<1> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<1> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[2].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<1> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<1> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<2> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<2> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[3].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<2> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<2> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<3> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<3> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[4].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<3> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<3> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<4> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<4> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[5].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<4> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<4> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<5> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<5> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[6].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<5> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<5> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<6> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<6> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[7].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<6> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<6> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<7> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<7> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[8].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<7> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<7> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<8> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<8> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[9].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<8> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<8> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<9> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<9> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[10].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<9> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<9> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<10> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<10> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[11].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<10> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<10> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<11> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<11> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[12].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<11> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<11> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<12> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<12> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[13].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<12> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<12> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<13> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<13> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[14].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<13> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<13> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<14> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<14> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[15].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<14> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<14> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<15> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<15> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[16].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<15> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<15> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<16> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<16> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[17].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<16> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<16> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<17> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<17> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[18].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<17> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<17> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<18> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<18> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[19].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<18> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<18> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<19> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<19> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[20].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<19> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<19> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<20> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<20> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[21].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<20> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<20> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<21> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<21> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[22].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<21> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<21> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<22> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<22> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[23].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<22> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<22> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<23> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<23> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[1].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<0> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<1> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<1> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[2].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<1> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<2> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<2> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[3].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<2> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<3> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<3> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[4].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<3> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<4> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<4> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[5].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<4> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<5> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<5> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[6].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<5> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<6> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<6> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[7].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<6> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<7> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<7> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[8].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<7> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<8> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<8> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[9].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<8> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<9> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<9> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[10].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<9> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<10> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<10> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[11].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<10> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<11> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<11> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[12].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<11> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<12> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<12> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[13].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<12> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<13> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<13> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[14].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<13> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<14> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<14> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[15].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<14> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<15> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<15> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[16].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<15> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<16> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<16> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[17].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<16> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<17> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<17> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[18].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<17> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<18> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<18> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[19].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<18> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<19> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<19> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[20].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<19> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<20> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<20> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[21].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<20> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<21> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<21> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[22].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<21> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<22> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<22> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[23].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<22> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<23> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<23> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carryxortop ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<23> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<24> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q_c_out.i_simple.add_q_cout.q_c_outreg/opt_has_pipe.first_q_0 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<24> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q_c_out.i_simple.add_q_cout.q_c_outreg/opt_has_pipe.first_q ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_need_mux.carrymux0 ( + .CI(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/inv_o [10]), + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<20> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<0> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<0> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.carryxor0 ( + .CI(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/inv_o [10]), + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<0> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<0> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.muxtop.carrymuxtop ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<23> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<23> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<24> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[1].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<0> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<0> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<1> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<1> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[2].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<1> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<1> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<2> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<2> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[3].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<2> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<2> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<3> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<3> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[4].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<3> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<3> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<4> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<4> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[5].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<4> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<4> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<5> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<5> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[6].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<5> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<5> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<6> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<6> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[7].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<6> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<6> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<7> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<7> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[8].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<7> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<7> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<8> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<8> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[9].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<8> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<8> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<9> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<9> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[10].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<9> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<9> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<10> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<10> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[11].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<10> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<10> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<11> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<11> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[12].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<11> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<11> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<12> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<12> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[13].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<12> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<12> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<13> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<13> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[14].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<13> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<13> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<14> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<14> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[15].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<14> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<14> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<15> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<15> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[16].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<15> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<15> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<16> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<16> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[17].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<16> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<16> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<17> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<17> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[18].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<17> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<17> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<18> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<18> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[19].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<18> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<18> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<19> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<19> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[20].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<19> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<19> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<20> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<20> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[21].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<20> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<20> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<21> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<21> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[22].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<21> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<21> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<22> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<22> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[23].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<22> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<22> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<23> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<23> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[1].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<0> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<1> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<1> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[2].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<1> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<2> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<2> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[3].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<2> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<3> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<3> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[4].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<3> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<4> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<4> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[5].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<4> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<5> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<5> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[6].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<5> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<6> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<6> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[7].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<6> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<7> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<7> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[8].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<7> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<8> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<8> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[9].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<8> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<9> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<9> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[10].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<9> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<10> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<10> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[11].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<10> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<11> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<11> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[12].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<11> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<12> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<12> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[13].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<12> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<13> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<13> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[14].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<13> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<14> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<14> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[15].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<14> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<15> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<15> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[16].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<15> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<16> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<16> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[17].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<16> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<17> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<17> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[18].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<17> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<18> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<18> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[19].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<18> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<19> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<19> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[20].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<19> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<20> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<20> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[21].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<20> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<21> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<21> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[22].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<21> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<22> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<22> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[23].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<22> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<23> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<23> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carryxortop ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<23> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<24> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q_c_out.i_simple.add_q_cout.q_c_outreg/opt_has_pipe.first_q_0 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<24> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q_c_out.i_simple.add_q_cout.q_c_outreg/opt_has_pipe.first_q ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_need_mux.carrymux0 ( + .CI(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/inv_o [9]), + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<21> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<0> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<0> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.carryxor0 ( + .CI(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/inv_o [9]), + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<0> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<0> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.muxtop.carrymuxtop ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<23> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<23> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<24> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[1].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<0> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<0> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<1> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<1> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[2].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<1> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<1> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<2> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<2> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[3].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<2> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<2> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<3> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<3> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[4].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<3> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<3> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<4> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<4> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[5].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<4> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<4> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<5> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<5> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[6].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<5> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<5> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<6> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<6> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[7].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<6> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<6> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<7> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<7> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[8].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<7> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<7> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<8> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<8> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[9].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<8> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<8> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<9> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<9> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[10].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<9> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<9> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<10> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<10> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[11].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<10> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<10> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<11> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<11> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[12].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<11> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<11> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<12> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<12> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[13].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<12> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<12> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<13> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<13> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[14].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<13> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<13> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<14> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<14> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[15].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<14> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<14> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<15> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<15> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[16].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<15> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<15> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<16> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<16> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[17].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<16> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<16> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<17> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<17> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[18].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<17> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<17> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<18> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<18> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[19].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<18> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<18> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<19> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<19> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[20].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<19> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<19> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<20> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<20> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[21].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<20> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<20> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<21> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<21> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[22].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<21> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<21> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<22> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<22> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[23].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<22> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<22> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<23> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<23> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[1].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<0> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<1> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<1> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[2].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<1> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<2> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<2> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[3].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<2> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<3> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<3> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[4].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<3> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<4> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<4> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[5].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<4> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<5> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<5> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[6].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<5> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<6> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<6> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[7].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<6> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<7> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<7> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[8].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<7> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<8> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<8> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[9].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<8> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<9> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<9> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[10].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<9> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<10> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<10> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[11].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<10> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<11> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<11> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[12].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<11> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<12> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<12> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[13].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<12> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<13> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<13> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[14].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<13> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<14> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<14> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[15].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<14> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<15> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<15> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[16].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<15> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<16> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<16> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[17].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<16> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<17> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<17> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[18].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<17> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<18> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<18> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[19].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<18> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<19> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<19> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[20].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<19> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<20> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<20> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[21].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<20> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<21> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<21> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[22].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<21> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<22> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<22> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[23].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<22> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<23> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<23> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carryxortop ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<23> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<24> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q_c_out.i_simple.add_q_cout.q_c_outreg/opt_has_pipe.first_q_0 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<24> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q_c_out.i_simple.add_q_cout.q_c_outreg/opt_has_pipe.first_q ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_need_mux.carrymux0 ( + .CI(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/inv_o [8]), + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<22> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<0> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<0> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.carryxor0 ( + .CI(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/inv_o [8]), + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<0> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<0> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.muxtop.carrymuxtop ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<23> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<23> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<24> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[1].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<0> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<0> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<1> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<1> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[2].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<1> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<1> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<2> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<2> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[3].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<2> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<2> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<3> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<3> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[4].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<3> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<3> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<4> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<4> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[5].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<4> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<4> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<5> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<5> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[6].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<5> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<5> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<6> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<6> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[7].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<6> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<6> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<7> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<7> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[8].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<7> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<7> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<8> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<8> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[9].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<8> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<8> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<9> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<9> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[10].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<9> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<9> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<10> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<10> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[11].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<10> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<10> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<11> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<11> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[12].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<11> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<11> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<12> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<12> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[13].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<12> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<12> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<13> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<13> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[14].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<13> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<13> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<14> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<14> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[15].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<14> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<14> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<15> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<15> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[16].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<15> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<15> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<16> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<16> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[17].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<16> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<16> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<17> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<17> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[18].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<17> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<17> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<18> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<18> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[19].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<18> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<18> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<19> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<19> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[20].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<19> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<19> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<20> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<20> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[21].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<20> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<20> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<21> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<21> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[22].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<21> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<21> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<22> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<22> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[23].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<22> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<22> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<23> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<23> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[1].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<0> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<1> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<1> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[2].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<1> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<2> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<2> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[3].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<2> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<3> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<3> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[4].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<3> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<4> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<4> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[5].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<4> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<5> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<5> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[6].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<5> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<6> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<6> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[7].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<6> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<7> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<7> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[8].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<7> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<8> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<8> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[9].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<8> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<9> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<9> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[10].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<9> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<10> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<10> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[11].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<10> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<11> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<11> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[12].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<11> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<12> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<12> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[13].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<12> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<13> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<13> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[14].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<13> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<14> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<14> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[15].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<14> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<15> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<15> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[16].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<15> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<16> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<16> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[17].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<16> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<17> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<17> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[18].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<17> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<18> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<18> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[19].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<18> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<19> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<19> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[20].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<19> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<20> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<20> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[21].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<20> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<21> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<21> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[22].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<21> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<22> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<22> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[23].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<22> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<23> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<23> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carryxortop ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<23> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<24> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q_c_out.i_simple.add_q_cout.q_c_outreg/opt_has_pipe.first_q_0 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<24> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q_c_out.i_simple.add_q_cout.q_c_outreg/opt_has_pipe.first_q ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_need_mux.carrymux0 ( + .CI(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/inv_o [7]), + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<23> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<0> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<0> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.carryxor0 ( + .CI(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/inv_o [7]), + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<0> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<0> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.muxtop.carrymuxtop ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<23> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<23> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<24> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[1].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<0> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<0> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<1> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<1> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[2].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<1> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<1> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<2> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<2> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[3].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<2> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<2> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<3> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<3> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[4].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<3> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<3> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<4> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<4> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[5].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<4> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<4> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<5> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<5> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[6].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<5> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<5> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<6> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<6> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[7].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<6> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<6> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<7> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<7> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[8].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<7> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<7> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<8> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<8> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[9].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<8> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<8> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<9> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<9> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[10].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<9> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<9> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<10> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<10> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[11].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<10> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<10> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<11> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<11> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[12].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<11> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<11> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<12> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<12> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[13].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<12> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<12> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<13> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<13> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[14].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<13> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<13> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<14> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<14> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[15].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<14> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<14> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<15> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<15> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[16].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<15> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<15> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<16> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<16> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[17].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<16> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<16> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<17> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<17> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[18].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<17> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<17> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<18> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<18> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[19].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<18> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<18> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<19> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<19> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[20].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<19> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<19> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<20> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<20> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[21].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<20> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<20> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<21> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<21> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[22].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<21> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<21> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<22> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<22> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[23].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<22> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<22> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<23> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<23> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[1].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<0> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<1> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<1> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[2].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<1> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<2> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<2> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[3].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<2> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<3> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<3> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[4].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<3> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<4> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<4> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[5].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<4> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<5> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<5> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[6].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<5> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<6> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<6> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[7].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<6> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<7> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<7> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[8].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<7> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<8> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<8> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[9].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<8> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<9> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<9> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[10].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<9> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<10> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<10> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[11].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<10> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<11> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<11> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[12].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<11> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<12> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<12> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[13].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<12> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<13> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<13> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[14].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<13> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<14> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<14> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[15].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<14> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<15> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<15> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[16].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<15> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<16> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<16> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[17].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<16> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<17> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<17> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[18].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<17> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<18> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<18> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[19].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<18> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<19> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<19> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[20].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<19> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<20> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<20> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[21].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<20> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<21> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<21> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[22].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<21> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<22> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<22> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[23].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<22> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<23> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<23> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carryxortop ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<23> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<24> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q_c_out.i_simple.add_q_cout.q_c_outreg/opt_has_pipe.first_q_0 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<24> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q_c_out.i_simple.add_q_cout.q_c_outreg/opt_has_pipe.first_q ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_need_mux.carrymux0 ( + .CI(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/inv_o [6]), + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<24> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<0> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<0> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.carryxor0 ( + .CI(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/inv_o [6]), + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<0> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<0> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.muxtop.carrymuxtop ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<23> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<23> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<24> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[1].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<0> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<0> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<1> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<1> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[2].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<1> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<1> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<2> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<2> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[3].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<2> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<2> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<3> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<3> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[4].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<3> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<3> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<4> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<4> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[5].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<4> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<4> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<5> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<5> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[6].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<5> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<5> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<6> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<6> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[7].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<6> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<6> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<7> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<7> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[8].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<7> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<7> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<8> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<8> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[9].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<8> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<8> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<9> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<9> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[10].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<9> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<9> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<10> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<10> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[11].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<10> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<10> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<11> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<11> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[12].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<11> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<11> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<12> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<12> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[13].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<12> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<12> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<13> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<13> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[14].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<13> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<13> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<14> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<14> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[15].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<14> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<14> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<15> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<15> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[16].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<15> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<15> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<16> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<16> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[17].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<16> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<16> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<17> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<17> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[18].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<17> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<17> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<18> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<18> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[19].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<18> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<18> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<19> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<19> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[20].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<19> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<19> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<20> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<20> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[21].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<20> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<20> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<21> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<21> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[22].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<21> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<21> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<22> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<22> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[23].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<22> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<22> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<23> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<23> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[1].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<0> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<1> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<1> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[2].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<1> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<2> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<2> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[3].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<2> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<3> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<3> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[4].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<3> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<4> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<4> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[5].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<4> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<5> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<5> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[6].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<5> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<6> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<6> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[7].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<6> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<7> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<7> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[8].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<7> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<8> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<8> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[9].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<8> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<9> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<9> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[10].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<9> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<10> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<10> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[11].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<10> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<11> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<11> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[12].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<11> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<12> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<12> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[13].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<12> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<13> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<13> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[14].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<13> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<14> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<14> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[15].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<14> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<15> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<15> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[16].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<15> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<16> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<16> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[17].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<16> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<17> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<17> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[18].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<17> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<18> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<18> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[19].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<18> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<19> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<19> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[20].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<19> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<20> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<20> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[21].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<20> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<21> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<21> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[22].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<21> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<22> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<22> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[23].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<22> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<23> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<23> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carryxortop ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<23> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<24> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q_c_out.i_simple.add_q_cout.q_c_outreg/opt_has_pipe.first_q_0 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<24> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q_c_out.i_simple.add_q_cout.q_c_outreg/opt_has_pipe.first_q ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_need_mux.carrymux0 ( + .CI(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/inv_o [5]), + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<25> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<0> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<0> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.carryxor0 ( + .CI(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/inv_o [5]), + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<0> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<0> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.muxtop.carrymuxtop ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<23> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<23> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<24> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[1].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<0> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<0> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<1> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<1> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[2].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<1> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<1> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<2> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<2> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[3].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<2> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<2> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<3> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<3> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[4].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<3> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<3> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<4> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<4> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[5].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<4> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<4> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<5> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<5> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[6].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<5> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<5> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<6> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<6> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[7].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<6> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<6> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<7> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<7> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[8].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<7> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<7> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<8> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<8> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[9].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<8> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<8> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<9> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<9> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[10].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<9> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<9> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<10> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<10> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[11].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<10> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<10> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<11> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<11> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[12].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<11> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<11> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<12> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<12> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[13].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<12> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<12> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<13> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<13> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[14].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<13> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<13> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<14> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<14> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[15].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<14> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<14> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<15> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<15> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[16].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<15> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<15> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<16> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<16> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[17].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<16> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<16> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<17> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<17> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[18].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<17> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<17> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<18> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<18> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[19].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<18> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<18> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<19> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<19> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[20].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<19> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<19> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<20> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<20> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[21].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<20> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<20> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<21> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<21> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[22].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<21> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<21> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<22> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<22> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[23].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<22> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<22> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<23> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<23> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[1].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<0> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<1> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<1> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[2].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<1> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<2> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<2> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[3].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<2> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<3> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<3> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[4].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<3> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<4> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<4> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[5].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<4> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<5> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<5> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[6].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<5> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<6> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<6> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[7].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<6> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<7> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<7> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[8].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<7> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<8> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<8> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[9].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<8> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<9> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<9> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[10].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<9> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<10> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<10> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[11].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<10> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<11> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<11> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[12].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<11> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<12> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<12> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[13].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<12> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<13> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<13> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[14].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<13> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<14> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<14> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[15].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<14> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<15> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<15> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[16].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<15> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<16> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<16> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[17].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<16> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<17> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<17> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[18].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<17> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<18> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<18> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[19].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<18> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<19> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<19> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[20].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<19> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<20> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<20> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[21].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<20> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<21> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<21> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[22].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<21> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<22> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<22> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[23].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<22> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<23> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<23> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carryxortop ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<23> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<24> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q_c_out.i_simple.add_q_cout.q_c_outreg/opt_has_pipe.first_q_0 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<24> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q_c_out.i_simple.add_q_cout.q_c_outreg/opt_has_pipe.first_q ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_need_mux.carrymux0 ( + .CI(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/inv_o [4]), + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<26> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<0> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<0> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.carryxor0 ( + .CI(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/inv_o [4]), + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<0> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<0> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.muxtop.carrymuxtop ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<23> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<23> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<24> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[1].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<0> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<0> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<1> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<1> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[2].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<1> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<1> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<2> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<2> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[3].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<2> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<2> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<3> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<3> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[4].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<3> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<3> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<4> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<4> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[5].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<4> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<4> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<5> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<5> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[6].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<5> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<5> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<6> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<6> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[7].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<6> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<6> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<7> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<7> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[8].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<7> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<7> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<8> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<8> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[9].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<8> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<8> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<9> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<9> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[10].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<9> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<9> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<10> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<10> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[11].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<10> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<10> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<11> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<11> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[12].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<11> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<11> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<12> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<12> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[13].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<12> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<12> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<13> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<13> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[14].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<13> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<13> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<14> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<14> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[15].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<14> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<14> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<15> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<15> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[16].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<15> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<15> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<16> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<16> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[17].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<16> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<16> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<17> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<17> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[18].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<17> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<17> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<18> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<18> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[19].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<18> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<18> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<19> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<19> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[20].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<19> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<19> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<20> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<20> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[21].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<20> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<20> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<21> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<21> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[22].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<21> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<21> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<22> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<22> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[23].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<22> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<22> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<23> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<23> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[1].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<0> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<1> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<1> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[2].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<1> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<2> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<2> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[3].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<2> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<3> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<3> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[4].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<3> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<4> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<4> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[5].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<4> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<5> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<5> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[6].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<5> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<6> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<6> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[7].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<6> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<7> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<7> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[8].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<7> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<8> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<8> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[9].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<8> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<9> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<9> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[10].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<9> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<10> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<10> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[11].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<10> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<11> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<11> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[12].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<11> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<12> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<12> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[13].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<12> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<13> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<13> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[14].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<13> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<14> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<14> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[15].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<14> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<15> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<15> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[16].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<15> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<16> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<16> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[17].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<16> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<17> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<17> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[18].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<17> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<18> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<18> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[19].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<18> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<19> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<19> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[20].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<19> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<20> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<20> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[21].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<20> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<21> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<21> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[22].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<21> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<22> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<22> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[23].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<22> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<23> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<23> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carryxortop ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<23> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<24> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q_c_out.i_simple.add_q_cout.q_c_outreg/opt_has_pipe.first_q_0 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<24> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q_c_out.i_simple.add_q_cout.q_c_outreg/opt_has_pipe.first_q ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_need_mux.carrymux0 ( + .CI(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/inv_o [3]), + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<27> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<0> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<0> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.carryxor0 ( + .CI(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/inv_o [3]), + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<0> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<0> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.muxtop.carrymuxtop ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<23> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<23> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<24> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[1].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<0> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<0> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<1> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<1> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[2].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<1> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<1> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<2> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<2> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[3].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<2> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<2> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<3> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<3> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[4].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<3> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<3> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<4> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<4> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[5].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<4> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<4> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<5> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<5> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[6].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<5> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<5> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<6> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<6> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[7].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<6> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<6> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<7> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<7> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[8].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<7> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<7> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<8> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<8> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[9].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<8> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<8> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<9> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<9> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[10].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<9> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<9> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<10> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<10> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[11].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<10> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<10> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<11> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<11> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[12].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<11> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<11> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<12> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<12> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[13].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<12> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<12> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<13> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<13> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[14].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<13> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<13> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<14> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<14> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[15].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<14> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<14> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<15> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<15> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[16].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<15> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<15> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<16> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<16> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[17].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<16> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<16> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<17> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<17> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[18].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<17> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<17> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<18> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<18> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[19].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<18> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<18> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<19> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<19> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[20].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<19> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<19> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<20> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<20> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[21].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<20> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<20> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<21> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<21> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[22].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<21> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<21> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<22> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<22> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[23].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<22> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<22> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<23> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<23> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[1].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<0> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<1> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<1> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[2].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<1> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<2> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<2> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[3].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<2> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<3> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<3> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[4].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<3> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<4> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<4> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[5].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<4> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<5> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<5> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[6].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<5> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<6> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<6> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[7].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<6> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<7> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<7> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[8].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<7> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<8> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<8> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[9].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<8> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<9> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<9> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[10].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<9> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<10> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<10> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[11].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<10> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<11> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<11> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[12].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<11> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<12> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<12> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[13].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<12> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<13> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<13> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[14].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<13> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<14> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<14> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[15].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<14> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<15> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<15> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[16].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<15> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<16> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<16> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[17].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<16> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<17> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<17> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[18].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<17> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<18> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<18> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[19].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<18> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<19> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<19> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[20].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<19> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<20> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<20> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[21].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<20> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<21> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<21> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[22].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<21> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<22> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<22> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[23].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<22> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<23> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<23> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carryxortop ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<23> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<24> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q_c_out.i_simple.add_q_cout.q_c_outreg/opt_has_pipe.first_q_0 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<24> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q_c_out.i_simple.add_q_cout.q_c_outreg/opt_has_pipe.first_q ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_need_mux.carrymux0 ( + .CI(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/inv_o [2]), + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<28> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<0> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<0> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.carryxor0 ( + .CI(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/inv_o [2]), + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<0> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<0> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.muxtop.carrymuxtop ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<23> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<23> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<24> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[1].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<0> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<0> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<1> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<1> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[2].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<1> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<1> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<2> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<2> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[3].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<2> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<2> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<3> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<3> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[4].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<3> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<3> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<4> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<4> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[5].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<4> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<4> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<5> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<5> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[6].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<5> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<5> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<6> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<6> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[7].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<6> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<6> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<7> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<7> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[8].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<7> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<7> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<8> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<8> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[9].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<8> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<8> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<9> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<9> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[10].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<9> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<9> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<10> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<10> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[11].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<10> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<10> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<11> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<11> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[12].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<11> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<11> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<12> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<12> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[13].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<12> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<12> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<13> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<13> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[14].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<13> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<13> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<14> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<14> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[15].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<14> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<14> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<15> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<15> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[16].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<15> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<15> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<16> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<16> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[17].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<16> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<16> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<17> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<17> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[18].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<17> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<17> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<18> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<18> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[19].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<18> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<18> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<19> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<19> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[20].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<19> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<19> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<20> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<20> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[21].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<20> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<20> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<21> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<21> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[22].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<21> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<21> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<22> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<22> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[23].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<22> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<22> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<23> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<23> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[1].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<0> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<1> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<1> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[2].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<1> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<2> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<2> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[3].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<2> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<3> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<3> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[4].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<3> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<4> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<4> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[5].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<4> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<5> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<5> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[6].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<5> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<6> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<6> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[7].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<6> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<7> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<7> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[8].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<7> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<8> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<8> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[9].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<8> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<9> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<9> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[10].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<9> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<10> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<10> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[11].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<10> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<11> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<11> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[12].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<11> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<12> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<12> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[13].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<12> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<13> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<13> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[14].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<13> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<14> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<14> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[15].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<14> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<15> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<15> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[16].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<15> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<16> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<16> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[17].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<16> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<17> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<17> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[18].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<17> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<18> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<18> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[19].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<18> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<19> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<19> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[20].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<19> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<20> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<20> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[21].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<20> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<21> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<21> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[22].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<21> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<22> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<22> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[23].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<22> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<23> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<23> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carryxortop ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<23> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<24> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q_c_out.i_simple.add_q_cout.q_c_outreg/opt_has_pipe.first_q_0 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<24> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q_c_out.i_simple.add_q_cout.q_c_outreg/opt_has_pipe.first_q ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_need_mux.carrymux0 ( + .CI(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/inv_o [1]), + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<29> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<0> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<0> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.carryxor0 ( + .CI(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/inv_o [1]), + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<0> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<0> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.muxtop.carrymuxtop ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<23> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<23> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<24> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[1].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<0> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<0> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<1> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<1> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[2].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<1> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<1> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<2> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<2> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[3].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<2> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<2> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<3> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<3> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[4].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<3> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<3> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<4> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<4> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[5].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<4> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<4> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<5> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<5> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[6].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<5> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<5> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<6> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<6> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[7].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<6> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<6> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<7> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<7> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[8].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<7> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<7> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<8> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<8> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[9].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<8> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<8> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<9> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<9> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[10].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<9> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<9> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<10> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<10> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[11].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<10> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<10> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<11> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<11> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[12].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<11> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<11> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<12> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<12> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[13].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<12> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<12> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<13> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<13> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[14].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<13> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<13> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<14> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<14> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[15].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<14> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<14> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<15> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<15> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[16].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<15> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<15> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<16> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<16> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[17].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<16> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<16> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<17> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<17> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[18].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<17> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<17> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<18> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<18> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[19].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<18> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<18> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<19> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<19> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[20].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<19> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<19> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<20> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<20> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[21].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<20> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<20> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<21> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<21> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[22].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<21> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<21> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<22> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<22> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[23].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<22> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<22> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<23> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<23> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[1].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<0> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<1> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<1> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[2].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<1> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<2> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<2> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[3].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<2> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<3> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<3> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[4].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<3> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<4> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<4> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[5].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<4> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<5> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<5> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[6].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<5> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<6> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<6> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[7].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<6> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<7> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<7> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[8].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<7> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<8> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<8> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[9].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<8> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<9> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<9> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[10].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<9> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<10> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<10> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[11].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<10> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<11> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<11> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[12].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<11> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<12> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<12> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[13].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<12> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<13> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<13> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[14].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<13> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<14> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<14> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[15].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<14> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<15> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<15> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[16].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<15> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<16> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<16> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[17].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<16> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<17> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<17> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[18].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<17> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<18> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<18> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[19].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<18> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<19> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<19> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[20].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<19> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<20> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<20> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[21].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<20> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<21> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<21> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[22].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<21> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<22> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<22> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[23].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<22> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<23> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<23> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carryxortop ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<23> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<24> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q_c_out.i_simple.add_q_cout.q_c_outreg/opt_has_pipe.first_q_0 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<24> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q_c_out.i_simple.add_q_cout.q_c_outreg/opt_has_pipe.first_q ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_need_mux.carrymux0 ( + .CI(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/inv_o [0]), + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<30> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<0> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<0> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.carryxor0 ( + .CI(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/inv_o [0]), + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<0> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<0> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.muxtop.carrymuxtop ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<23> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<23> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<24> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[1].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<0> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<0> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<1> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<1> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[2].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<1> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<1> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<2> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<2> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[3].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<2> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<2> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<3> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<3> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[4].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<3> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<3> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<4> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<4> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[5].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<4> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<4> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<5> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<5> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[6].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<5> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<5> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<6> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<6> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[7].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<6> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<6> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<7> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<7> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[8].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<7> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<7> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<8> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<8> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[9].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<8> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<8> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<9> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<9> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[10].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<9> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<9> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<10> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<10> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[11].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<10> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<10> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<11> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<11> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[12].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<11> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<11> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<12> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<12> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[13].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<12> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<12> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<13> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<13> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[14].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<13> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<13> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<14> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<14> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[15].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<14> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<14> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<15> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<15> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[16].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<15> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<15> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<16> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<16> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[17].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<16> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<16> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<17> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<17> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[18].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<17> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<17> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<18> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<18> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[19].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<18> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<18> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<19> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<19> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[20].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<19> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<19> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<20> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<20> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[21].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<20> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<20> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<21> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<21> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[22].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<21> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<21> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<22> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<22> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[23].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<22> ) +, + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<22> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<23> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<23> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[1].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<0> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<1> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<1> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[2].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<1> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<2> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<2> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[3].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<2> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<3> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<3> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[4].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<3> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<4> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<4> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[5].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<4> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<5> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<5> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[6].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<5> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<6> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<6> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[7].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<6> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<7> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<7> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[8].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<7> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<8> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<8> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[9].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<8> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<9> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<9> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[10].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<9> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<10> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<10> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[11].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<10> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<11> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<11> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[12].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<11> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<12> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<12> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[13].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<12> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<13> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<13> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[14].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<13> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<14> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<14> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[15].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<14> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<15> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<15> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[16].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<15> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<16> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<16> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[17].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<16> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<17> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<17> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[18].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<17> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<18> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<18> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[19].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<18> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<19> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<19> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[20].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<19> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<20> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<20> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[21].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<20> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<21> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<21> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[22].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<21> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<22> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<22> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[23].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<22> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<23> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<23> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carryxortop ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<23> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<24> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<24> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q_c_out.i_simple.add_q_cout.q_c_outreg/opt_has_pipe.first_q_0 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<24> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q_c_out.i_simple.add_q_cout.q_c_outreg/opt_has_pipe.first_q ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_need_mux.carrymux0 ( + .CI(NlwRenamedSig_OI_rfd), + .DI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<31> ) +, + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<0> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<0> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.carryxor0 ( + .CI(NlwRenamedSig_OI_rfd), + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<0> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<0> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.muxtop.carrymuxtop ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<23> ) +, + .DI(\BU2/divide_by_zero ), + .S(NlwRenamedSig_OI_rfd), + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<24> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[1].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<0> ) +, + .DI(\BU2/divide_by_zero ), + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<1> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<1> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[2].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<1> ) +, + .DI(\BU2/divide_by_zero ), + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<2> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<2> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[3].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<2> ) +, + .DI(\BU2/divide_by_zero ), + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<3> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<3> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[4].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<3> ) +, + .DI(\BU2/divide_by_zero ), + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<4> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<4> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[5].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<4> ) +, + .DI(\BU2/divide_by_zero ), + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<5> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<5> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[6].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<5> ) +, + .DI(\BU2/divide_by_zero ), + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<6> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<6> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[7].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<6> ) +, + .DI(\BU2/divide_by_zero ), + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<7> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<7> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[8].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<7> ) +, + .DI(\BU2/divide_by_zero ), + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<8> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<8> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[9].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<8> ) +, + .DI(\BU2/divide_by_zero ), + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<9> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<9> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[10].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<9> ) +, + .DI(\BU2/divide_by_zero ), + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<10> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<10> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[11].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<10> ) +, + .DI(\BU2/divide_by_zero ), + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<11> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<11> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[12].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<11> ) +, + .DI(\BU2/divide_by_zero ), + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<12> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<12> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[13].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<12> ) +, + .DI(\BU2/divide_by_zero ), + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<13> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<13> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[14].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<13> ) +, + .DI(\BU2/divide_by_zero ), + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<14> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<14> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[15].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<14> ) +, + .DI(\BU2/divide_by_zero ), + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<15> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<15> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[16].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<15> ) +, + .DI(\BU2/divide_by_zero ), + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<16> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<16> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[17].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<16> ) +, + .DI(\BU2/divide_by_zero ), + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<17> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<17> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[18].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<17> ) +, + .DI(\BU2/divide_by_zero ), + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<18> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<18> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[19].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<18> ) +, + .DI(\BU2/divide_by_zero ), + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<19> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<19> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[20].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<19> ) +, + .DI(\BU2/divide_by_zero ), + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<20> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<20> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[21].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<20> ) +, + .DI(\BU2/divide_by_zero ), + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<21> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<21> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[22].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<21> ) +, + .DI(\BU2/divide_by_zero ), + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<22> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<22> ) + + ); + MUXCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[23].carrymux ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<22> ) +, + .DI(\BU2/divide_by_zero ), + .S +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<23> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<23> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[1].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<0> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<1> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<1> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[2].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<1> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<2> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<2> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[3].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<2> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<3> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<3> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[4].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<3> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<4> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<4> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[5].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<4> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<5> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<5> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[6].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<5> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<6> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<6> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[7].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<6> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<7> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<7> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[8].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<7> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<8> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<8> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[9].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<8> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<9> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<9> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[10].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<9> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<10> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<10> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[11].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<10> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<11> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<11> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[12].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<11> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<12> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<12> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[13].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<12> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<13> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<13> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[14].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<13> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<14> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<14> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[15].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<14> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<15> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<15> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[16].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<15> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<16> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<16> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[17].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<16> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<17> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<17> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[18].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<17> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<18> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<18> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[19].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<18> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<19> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<19> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[20].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<19> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<20> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<20> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[21].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<20> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<21> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<21> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[22].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<21> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<22> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<22> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[23].carryxor ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<22> ) +, + .LI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.halfsum<23> ) +, + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<23> ) + + ); + XORCY + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carryxortop ( + .CI +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple<23> ) +, + .LI(NlwRenamedSig_OI_rfd), + .O +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/sum_simple<24> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_0 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<0> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<0> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_1 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<1> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<1> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_2 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<2> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<2> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_3 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<3> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<3> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_4 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<4> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<4> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_5 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<5> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<5> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_6 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<6> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<6> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_7 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<7> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<7> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_8 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<8> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<8> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_9 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<9> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<9> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_10 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<10> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<10> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_11 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<11> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<11> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_12 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<12> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<12> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_13 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<13> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<13> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_14 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<14> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<14> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_15 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<15> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<15> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_16 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<16> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<16> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_17 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<17> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<17> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_18 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<18> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<18> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_19 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<19> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<19> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_20 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<20> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<20> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_21 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<21> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<21> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_22 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<22> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<22> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_23 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<23> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<23> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_0 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<0> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<0> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_1 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<1> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<1> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_2 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<2> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<2> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_3 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<3> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<3> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_4 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<4> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<4> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_5 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<5> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<5> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_6 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<6> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<6> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_7 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<7> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<7> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_8 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<8> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<8> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_9 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<9> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<9> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_10 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<10> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<10> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_11 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<11> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<11> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_12 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<12> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<12> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_13 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<13> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<13> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_14 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<14> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<14> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_15 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<15> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<15> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_16 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<16> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<16> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_17 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<17> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<17> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_18 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<18> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<18> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_19 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<19> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<19> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_20 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<20> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<20> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_21 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<21> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<21> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_22 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<22> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<22> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_23 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<23> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<23> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_0 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<0> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<0> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_1 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<1> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<1> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_2 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<2> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<2> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_3 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<3> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<3> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_4 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<4> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<4> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_5 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<5> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<5> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_6 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<6> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<6> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_7 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<7> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<7> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_8 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<8> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<8> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_9 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<9> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<9> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_10 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<10> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<10> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_11 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<11> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<11> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_12 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<12> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<12> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_13 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<13> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<13> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_14 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<14> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<14> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_15 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<15> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<15> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_16 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<16> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<16> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_17 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<17> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<17> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_18 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<18> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<18> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_19 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<19> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<19> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_20 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<20> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<20> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_21 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<21> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<21> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_22 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<22> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<22> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_23 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<23> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<23> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_0 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<0> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<0> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_1 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<1> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<1> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_2 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<2> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<2> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_3 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<3> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<3> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_4 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<4> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<4> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_5 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<5> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<5> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_6 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<6> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<6> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_7 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<7> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<7> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_8 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<8> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<8> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_9 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<9> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<9> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_10 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<10> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<10> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_11 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<11> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<11> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_12 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<12> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<12> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_13 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<13> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<13> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_14 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<14> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<14> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_15 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<15> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<15> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_16 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<16> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<16> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_17 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<17> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<17> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_18 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<18> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<18> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_19 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<19> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<19> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_20 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<20> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<20> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_21 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<21> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<21> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_22 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<22> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<22> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_23 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<23> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<23> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_0 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<0> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<0> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_1 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<1> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<1> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_2 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<2> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<2> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_3 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<3> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<3> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_4 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<4> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<4> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_5 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<5> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<5> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_6 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<6> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<6> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_7 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<7> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<7> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_8 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<8> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<8> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_9 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<9> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<9> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_10 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<10> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<10> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_11 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<11> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<11> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_12 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<12> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<12> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_13 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<13> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<13> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_14 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<14> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<14> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_15 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<15> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<15> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_16 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<16> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<16> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_17 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<17> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<17> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_18 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<18> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<18> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_19 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<19> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<19> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_20 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<20> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<20> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_21 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<21> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<21> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_22 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<22> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<22> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_23 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<23> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<23> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_0 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<0> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<0> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_1 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<1> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<1> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_2 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<2> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<2> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_3 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<3> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<3> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_4 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<4> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<4> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_5 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<5> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<5> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_6 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<6> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<6> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_7 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<7> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<7> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_8 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<8> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<8> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_9 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<9> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<9> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_10 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<10> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<10> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_11 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<11> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<11> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_12 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<12> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<12> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_13 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<13> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<13> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_14 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<14> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<14> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_15 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<15> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<15> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_16 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<16> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<16> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_17 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<17> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<17> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_18 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<18> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<18> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_19 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<19> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<19> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_20 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<20> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<20> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_21 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<21> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<21> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_22 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<22> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<22> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_23 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<23> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<23> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_0 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<0> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<0> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_1 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<1> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<1> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_2 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<2> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<2> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_3 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<3> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<3> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_4 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<4> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<4> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_5 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<5> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<5> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_6 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<6> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<6> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_7 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<7> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<7> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_8 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<8> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<8> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_9 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<9> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<9> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_10 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<10> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<10> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_11 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<11> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<11> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_12 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<12> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<12> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_13 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<13> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<13> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_14 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<14> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<14> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_15 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<15> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<15> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_16 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<16> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<16> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_17 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<17> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<17> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_18 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<18> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<18> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_19 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<19> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<19> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_20 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<20> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<20> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_21 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<21> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<21> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_22 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<22> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<22> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_23 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<23> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<23> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_0 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<0> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<0> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_1 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<1> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<1> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_2 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<2> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<2> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_3 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<3> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<3> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_4 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<4> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<4> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_5 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<5> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<5> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_6 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<6> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<6> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_7 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<7> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<7> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_8 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<8> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<8> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_9 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<9> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<9> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_10 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<10> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<10> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_11 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<11> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<11> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_12 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<12> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<12> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_13 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<13> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<13> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_14 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<14> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<14> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_15 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<15> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<15> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_16 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<16> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<16> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_17 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<17> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<17> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_18 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<18> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<18> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_19 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<19> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<19> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_20 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<20> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<20> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_21 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<21> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<21> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_22 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<22> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<22> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_23 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<23> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<23> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_0 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<0> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<0> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_1 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<1> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<1> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_2 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<2> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<2> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_3 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<3> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<3> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_4 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<4> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<4> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_5 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<5> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<5> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_6 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<6> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<6> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_7 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<7> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<7> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_8 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<8> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<8> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_9 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<9> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<9> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_10 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<10> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<10> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_11 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<11> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<11> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_12 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<12> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<12> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_13 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<13> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<13> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_14 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<14> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<14> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_15 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<15> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<15> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_16 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<16> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<16> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_17 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<17> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<17> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_18 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<18> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<18> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_19 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<19> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<19> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_20 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<20> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<20> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_21 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<21> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<21> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_22 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<22> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<22> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_23 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[8].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<23> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<23> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_0 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<0> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<0> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_1 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<1> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<1> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_2 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<2> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<2> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_3 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<3> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<3> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_4 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<4> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<4> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_5 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<5> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<5> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_6 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<6> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<6> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_7 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<7> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<7> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_8 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<8> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<8> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_9 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<9> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<9> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_10 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<10> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<10> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_11 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<11> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<11> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_12 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<12> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<12> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_13 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<13> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<13> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_14 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<14> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<14> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_15 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<15> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<15> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_16 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<16> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<16> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_17 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<17> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<17> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_18 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<18> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<18> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_19 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<19> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<19> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_20 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<20> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<20> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_21 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<21> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<21> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_22 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<22> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<22> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_23 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[9].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<23> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<23> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_0 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<0> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<0> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_1 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<1> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<1> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_2 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<2> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<2> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_3 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<3> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<3> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_4 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<4> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<4> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_5 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<5> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<5> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_6 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<6> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<6> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_7 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<7> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<7> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_8 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<8> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<8> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_9 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<9> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<9> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_10 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<10> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<10> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_11 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<11> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<11> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_12 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<12> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<12> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_13 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<13> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<13> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_14 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<14> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<14> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_15 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<15> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<15> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_16 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<16> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<16> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_17 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<17> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<17> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_18 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<18> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<18> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_19 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<19> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<19> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_20 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<20> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<20> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_21 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<21> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<21> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_22 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<22> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<22> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_23 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[10].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<23> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<23> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_0 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<0> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<0> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_1 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<1> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<1> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_2 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<2> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<2> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_3 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<3> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<3> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_4 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<4> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<4> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_5 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<5> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<5> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_6 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<6> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<6> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_7 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<7> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<7> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_8 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<8> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<8> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_9 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<9> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<9> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_10 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<10> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<10> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_11 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<11> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<11> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_12 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<12> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<12> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_13 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<13> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<13> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_14 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<14> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<14> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_15 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<15> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<15> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_16 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<16> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<16> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_17 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<17> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<17> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_18 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<18> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<18> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_19 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<19> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<19> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_20 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<20> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<20> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_21 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<21> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<21> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_22 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<22> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<22> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_23 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[11].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<23> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<23> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_0 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<0> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<0> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_1 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<1> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<1> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_2 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<2> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<2> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_3 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<3> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<3> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_4 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<4> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<4> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_5 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<5> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<5> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_6 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<6> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<6> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_7 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<7> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<7> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_8 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<8> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<8> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_9 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<9> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<9> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_10 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<10> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<10> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_11 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<11> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<11> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_12 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<12> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<12> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_13 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<13> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<13> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_14 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<14> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<14> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_15 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<15> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<15> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_16 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<16> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<16> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_17 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<17> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<17> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_18 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<18> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<18> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_19 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<19> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<19> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_20 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<20> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<20> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_21 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<21> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<21> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_22 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<22> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<22> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_23 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[12].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<23> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<23> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_0 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<0> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<0> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_1 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<1> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<1> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_2 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<2> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<2> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_3 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<3> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<3> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_4 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<4> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<4> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_5 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<5> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<5> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_6 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<6> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<6> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_7 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<7> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<7> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_8 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<8> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<8> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_9 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<9> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<9> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_10 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<10> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<10> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_11 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<11> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<11> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_12 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<12> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<12> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_13 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<13> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<13> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_14 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<14> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<14> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_15 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<15> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<15> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_16 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<16> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<16> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_17 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<17> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<17> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_18 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<18> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<18> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_19 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<19> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<19> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_20 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<20> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<20> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_21 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<21> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<21> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_22 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<22> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<22> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_23 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[13].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<23> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<23> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_0 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<0> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<0> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_1 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<1> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<1> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_2 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<2> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<2> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_3 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<3> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<3> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_4 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<4> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<4> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_5 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<5> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<5> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_6 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<6> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<6> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_7 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<7> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<7> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_8 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<8> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<8> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_9 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<9> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<9> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_10 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<10> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<10> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_11 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<11> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<11> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_12 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<12> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<12> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_13 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<13> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<13> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_14 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<14> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<14> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_15 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<15> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<15> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_16 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<16> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<16> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_17 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<17> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<17> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_18 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<18> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<18> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_19 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<19> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<19> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_20 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<20> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<20> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_21 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<21> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<21> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_22 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<22> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<22> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_23 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[14].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<23> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<23> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_0 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<0> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<0> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_1 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<1> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<1> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_2 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<2> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<2> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_3 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<3> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<3> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_4 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<4> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<4> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_5 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<5> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<5> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_6 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<6> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<6> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_7 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<7> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<7> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_8 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<8> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<8> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_9 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<9> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<9> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_10 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<10> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<10> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_11 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<11> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<11> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_12 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<12> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<12> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_13 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<13> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<13> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_14 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<14> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<14> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_15 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<15> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<15> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_16 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<16> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<16> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_17 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<17> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<17> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_18 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<18> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<18> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_19 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<19> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<19> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_20 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<20> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<20> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_21 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<21> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<21> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_22 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<22> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<22> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_23 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[15].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<23> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<23> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_0 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<0> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<0> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_1 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<1> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<1> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_2 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<2> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<2> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_3 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<3> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<3> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_4 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<4> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<4> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_5 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<5> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<5> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_6 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<6> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<6> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_7 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<7> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<7> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_8 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<8> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<8> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_9 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<9> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<9> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_10 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<10> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<10> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_11 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<11> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<11> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_12 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<12> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<12> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_13 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<13> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<13> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_14 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<14> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<14> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_15 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<15> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<15> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_16 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<16> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<16> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_17 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<17> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<17> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_18 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<18> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<18> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_19 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<19> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<19> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_20 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<20> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<20> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_21 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<21> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<21> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_22 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<22> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<22> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_23 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[16].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<23> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<23> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_0 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<0> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<0> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_1 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<1> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<1> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_2 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<2> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<2> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_3 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<3> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<3> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_4 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<4> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<4> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_5 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<5> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<5> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_6 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<6> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<6> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_7 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<7> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<7> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_8 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<8> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<8> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_9 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<9> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<9> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_10 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<10> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<10> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_11 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<11> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<11> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_12 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<12> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<12> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_13 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<13> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<13> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_14 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<14> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<14> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_15 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<15> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<15> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_16 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<16> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<16> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_17 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<17> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<17> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_18 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<18> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<18> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_19 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<19> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<19> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_20 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<20> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<20> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_21 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<21> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<21> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_22 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<22> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<22> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_23 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[17].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<23> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<23> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_0 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<0> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<0> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_1 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<1> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<1> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_2 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<2> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<2> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_3 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<3> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<3> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_4 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<4> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<4> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_5 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<5> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<5> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_6 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<6> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<6> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_7 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<7> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<7> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_8 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<8> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<8> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_9 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<9> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<9> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_10 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<10> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<10> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_11 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<11> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<11> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_12 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<12> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<12> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_13 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<13> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<13> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_14 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<14> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<14> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_15 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<15> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<15> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_16 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<16> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<16> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_17 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<17> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<17> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_18 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<18> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<18> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_19 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<19> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<19> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_20 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<20> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<20> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_21 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<21> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<21> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_22 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<22> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<22> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_23 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[18].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<23> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<23> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_0 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<0> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<0> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_1 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<1> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<1> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_2 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<2> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<2> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_3 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<3> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<3> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_4 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<4> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<4> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_5 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<5> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<5> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_6 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<6> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<6> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_7 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<7> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<7> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_8 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<8> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<8> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_9 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<9> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<9> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_10 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<10> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<10> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_11 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<11> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<11> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_12 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<12> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<12> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_13 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<13> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<13> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_14 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<14> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<14> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_15 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<15> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<15> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_16 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<16> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<16> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_17 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<17> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<17> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_18 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<18> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<18> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_19 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<19> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<19> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_20 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<20> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<20> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_21 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<21> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<21> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_22 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<22> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<22> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_23 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[19].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<23> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<23> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_0 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<0> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<0> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_1 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<1> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<1> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_2 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<2> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<2> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_3 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<3> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<3> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_4 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<4> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<4> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_5 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<5> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<5> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_6 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<6> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<6> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_7 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<7> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<7> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_8 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<8> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<8> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_9 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<9> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<9> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_10 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<10> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<10> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_11 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<11> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<11> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_12 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<12> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<12> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_13 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<13> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<13> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_14 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<14> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<14> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_15 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<15> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<15> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_16 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<16> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<16> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_17 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<17> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<17> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_18 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<18> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<18> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_19 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<19> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<19> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_20 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<20> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<20> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_21 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<21> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<21> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_22 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<22> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<22> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_23 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[20].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<23> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<23> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_0 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<0> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<0> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_1 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<1> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<1> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_2 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<2> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<2> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_3 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<3> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<3> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_4 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<4> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<4> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_5 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<5> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<5> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_6 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<6> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<6> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_7 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<7> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<7> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_8 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<8> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<8> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_9 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<9> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<9> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_10 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<10> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<10> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_11 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<11> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<11> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_12 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<12> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<12> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_13 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<13> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<13> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_14 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<14> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<14> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_15 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<15> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<15> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_16 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<16> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<16> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_17 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<17> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<17> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_18 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<18> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<18> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_19 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<19> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<19> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_20 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<20> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<20> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_21 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<21> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<21> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_22 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<22> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<22> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_23 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[21].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<23> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<23> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_0 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<0> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<0> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_1 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<1> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<1> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_2 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<2> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<2> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_3 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<3> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<3> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_4 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<4> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<4> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_5 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<5> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<5> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_6 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<6> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<6> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_7 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<7> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<7> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_8 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<8> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<8> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_9 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<9> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<9> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_10 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<10> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<10> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_11 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<11> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<11> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_12 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<12> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<12> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_13 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<13> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<13> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_14 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<14> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<14> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_15 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<15> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<15> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_16 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<16> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<16> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_17 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<17> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<17> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_18 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<18> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<18> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_19 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<19> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<19> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_20 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<20> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<20> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_21 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<21> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<21> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_22 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<22> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<22> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_23 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[22].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<23> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<23> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_0 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<0> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<0> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_1 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<1> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<1> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_2 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<2> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<2> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_3 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<3> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<3> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_4 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<4> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<4> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_5 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<5> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<5> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_6 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<6> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<6> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_7 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<7> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<7> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_8 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<8> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<8> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_9 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<9> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<9> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_10 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<10> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<10> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_11 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<11> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<11> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_12 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<12> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<12> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_13 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<13> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<13> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_14 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<14> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<14> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_15 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<15> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<15> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_16 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<16> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<16> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_17 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<17> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<17> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_18 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<18> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<18> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_19 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<19> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<19> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_20 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<20> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<20> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_21 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<21> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<21> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_22 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<22> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<22> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_23 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[23].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<23> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<23> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_0 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<0> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<0> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_1 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<1> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<1> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_2 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<2> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<2> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_3 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<3> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<3> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_4 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<4> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<4> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_5 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<5> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<5> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_6 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<6> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<6> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_7 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<7> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<7> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_8 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<8> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<8> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_9 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<9> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<9> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_10 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<10> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<10> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_11 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<11> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<11> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_12 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<12> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<12> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_13 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<13> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<13> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_14 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<14> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<14> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_15 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<15> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<15> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_16 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<16> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<16> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_17 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<17> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<17> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_18 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<18> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<18> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_19 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<19> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<19> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_20 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<20> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<20> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_21 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<21> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<21> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_22 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<22> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<22> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_23 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<23> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<23> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_0 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<0> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<0> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_1 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<1> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<1> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_2 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<2> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<2> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_3 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<3> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<3> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_4 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<4> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<4> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_5 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<5> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<5> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_6 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<6> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<6> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_7 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<7> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<7> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_8 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<8> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<8> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_9 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<9> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<9> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_10 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<10> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<10> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_11 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<11> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<11> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_12 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<12> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<12> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_13 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<13> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<13> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_14 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<14> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<14> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_15 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<15> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<15> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_16 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<16> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<16> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_17 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<17> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<17> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_18 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<18> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<18> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_19 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<19> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<19> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_20 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<20> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<20> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_21 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<21> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<21> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_22 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<22> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<22> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_23 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<23> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<23> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_0 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<0> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<0> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_1 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<1> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<1> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_2 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<2> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<2> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_3 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<3> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<3> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_4 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<4> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<4> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_5 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<5> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<5> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_6 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<6> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<6> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_7 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<7> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<7> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_8 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<8> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<8> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_9 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<9> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<9> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_10 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<10> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<10> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_11 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<11> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<11> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_12 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<12> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<12> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_13 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<13> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<13> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_14 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<14> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<14> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_15 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<15> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<15> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_16 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<16> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<16> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_17 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<17> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<17> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_18 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<18> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<18> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_19 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<19> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<19> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_20 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<20> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<20> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_21 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<21> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<21> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_22 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<22> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<22> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_23 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<23> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<23> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_0 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<0> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<0> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_1 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<1> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<1> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_2 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<2> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<2> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_3 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<3> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<3> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_4 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<4> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<4> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_5 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<5> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<5> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_6 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<6> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<6> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_7 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<7> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<7> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_8 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<8> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<8> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_9 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<9> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<9> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_10 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<10> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<10> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_11 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<11> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<11> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_12 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<12> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<12> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_13 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<13> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<13> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_14 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<14> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<14> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_15 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<15> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<15> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_16 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<16> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<16> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_17 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<17> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<17> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_18 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<18> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<18> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_19 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<19> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<19> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_20 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<20> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<20> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_21 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<21> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<21> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_22 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<22> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<22> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_23 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<23> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<23> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_0 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<0> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<0> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_1 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<1> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<1> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_2 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<2> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<2> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_3 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<3> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<3> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_4 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<4> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<4> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_5 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<5> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<5> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_6 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<6> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<6> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_7 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<7> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<7> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_8 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<8> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<8> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_9 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<9> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<9> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_10 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<10> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<10> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_11 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<11> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<11> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_12 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<12> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<12> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_13 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<13> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<13> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_14 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<14> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<14> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_15 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<15> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<15> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_16 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<16> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<16> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_17 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<17> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<17> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_18 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<18> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<18> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_19 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<19> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<19> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_20 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<20> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<20> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_21 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<21> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<21> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_22 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<22> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<22> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_23 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<23> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<23> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_0 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<0> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<0> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_1 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<1> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<1> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_2 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<2> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<2> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_3 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<3> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<3> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_4 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<4> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<4> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_5 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<5> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<5> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_6 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<6> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<6> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_7 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<7> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<7> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_8 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<8> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<8> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_9 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<9> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<9> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_10 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<10> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<10> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_11 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<11> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<11> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_12 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<12> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<12> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_13 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<13> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<13> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_14 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<14> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<14> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_15 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<15> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<15> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_16 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<16> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<16> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_17 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<17> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<17> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_18 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<18> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<18> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_19 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<19> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<19> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_20 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<20> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<20> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_21 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<21> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<21> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_22 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<22> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<22> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_23 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<23> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<23> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_0 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<0> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<0> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_1 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<1> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<1> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_2 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<2> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<2> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_3 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<3> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<3> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_4 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<4> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<4> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_5 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<5> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<5> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_6 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<6> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<6> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_7 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<7> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<7> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_8 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<8> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<8> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_9 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<9> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<9> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_10 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<10> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<10> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_11 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<11> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<11> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_12 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<12> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<12> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_13 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<13> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<13> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_14 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<14> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<14> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_15 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<15> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<15> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_16 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<16> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<16> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_17 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<17> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<17> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_18 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<18> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<18> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_19 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<19> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<19> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_20 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<20> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<20> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_21 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<21> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<21> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_22 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<22> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<22> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q_23 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<23> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<23> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/final_div.del_end_divisor/opt_has_pipe.first_q_0 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<0> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/final_div.del_end_divisor/opt_has_pipe.first_q [0]) + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/final_div.del_end_divisor/opt_has_pipe.first_q_1 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<1> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/final_div.del_end_divisor/opt_has_pipe.first_q [1]) + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/final_div.del_end_divisor/opt_has_pipe.first_q_2 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<2> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/final_div.del_end_divisor/opt_has_pipe.first_q [2]) + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/final_div.del_end_divisor/opt_has_pipe.first_q_3 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<3> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/final_div.del_end_divisor/opt_has_pipe.first_q [3]) + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/final_div.del_end_divisor/opt_has_pipe.first_q_4 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<4> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/final_div.del_end_divisor/opt_has_pipe.first_q [4]) + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/final_div.del_end_divisor/opt_has_pipe.first_q_5 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<5> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/final_div.del_end_divisor/opt_has_pipe.first_q [5]) + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/final_div.del_end_divisor/opt_has_pipe.first_q_6 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<6> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/final_div.del_end_divisor/opt_has_pipe.first_q [6]) + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/final_div.del_end_divisor/opt_has_pipe.first_q_7 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<7> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/final_div.del_end_divisor/opt_has_pipe.first_q [7]) + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/final_div.del_end_divisor/opt_has_pipe.first_q_8 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<8> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/final_div.del_end_divisor/opt_has_pipe.first_q [8]) + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/final_div.del_end_divisor/opt_has_pipe.first_q_9 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<9> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/final_div.del_end_divisor/opt_has_pipe.first_q [9]) + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/final_div.del_end_divisor/opt_has_pipe.first_q_10 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<10> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/final_div.del_end_divisor/opt_has_pipe.first_q [10]) + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/final_div.del_end_divisor/opt_has_pipe.first_q_11 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<11> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/final_div.del_end_divisor/opt_has_pipe.first_q [11]) + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/final_div.del_end_divisor/opt_has_pipe.first_q_12 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<12> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/final_div.del_end_divisor/opt_has_pipe.first_q [12]) + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/final_div.del_end_divisor/opt_has_pipe.first_q_13 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<13> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/final_div.del_end_divisor/opt_has_pipe.first_q [13]) + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/final_div.del_end_divisor/opt_has_pipe.first_q_14 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<14> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/final_div.del_end_divisor/opt_has_pipe.first_q [14]) + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/final_div.del_end_divisor/opt_has_pipe.first_q_15 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<15> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/final_div.del_end_divisor/opt_has_pipe.first_q [15]) + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/final_div.del_end_divisor/opt_has_pipe.first_q_16 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<16> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/final_div.del_end_divisor/opt_has_pipe.first_q [16]) + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/final_div.del_end_divisor/opt_has_pipe.first_q_17 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<17> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/final_div.del_end_divisor/opt_has_pipe.first_q [17]) + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/final_div.del_end_divisor/opt_has_pipe.first_q_18 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<18> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/final_div.del_end_divisor/opt_has_pipe.first_q [18]) + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/final_div.del_end_divisor/opt_has_pipe.first_q_19 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<19> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/final_div.del_end_divisor/opt_has_pipe.first_q [19]) + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/final_div.del_end_divisor/opt_has_pipe.first_q_20 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<20> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/final_div.del_end_divisor/opt_has_pipe.first_q [20]) + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/final_div.del_end_divisor/opt_has_pipe.first_q_21 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<21> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/final_div.del_end_divisor/opt_has_pipe.first_q [21]) + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/final_div.del_end_divisor/opt_has_pipe.first_q_22 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<22> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/final_div.del_end_divisor/opt_has_pipe.first_q [22]) + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/final_div.del_end_divisor/opt_has_pipe.first_q_23 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].divisor_gen.divisor_dc1.del_divisor_msbs/opt_has_pipe.first_q<23> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/final_div.del_end_divisor/opt_has_pipe.first_q [23]) + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/reg_quot_out.reg_quot/opt_has_pipe.first_q_0 ( + .C(clk), + .D(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].adder_gen.reg_req.adsu_mod/inv_o ), + .Q(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/reg_quot_out.reg_quot/opt_has_pipe.first_q [0]) + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/reg_quot_out.reg_quot/opt_has_pipe.first_q_1 ( + .C(clk), + .D(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/qpi [1]), + .Q(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/reg_quot_out.reg_quot/opt_has_pipe.first_q [1]) + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/reg_quot_out.reg_quot/opt_has_pipe.first_q_2 ( + .C(clk), + .D(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/qpi [2]), + .Q(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/reg_quot_out.reg_quot/opt_has_pipe.first_q [2]) + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/reg_quot_out.reg_quot/opt_has_pipe.first_q_3 ( + .C(clk), + .D(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/qpi [3]), + .Q(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/reg_quot_out.reg_quot/opt_has_pipe.first_q [3]) + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/reg_quot_out.reg_quot/opt_has_pipe.first_q_4 ( + .C(clk), + .D(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/qpi [4]), + .Q(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/reg_quot_out.reg_quot/opt_has_pipe.first_q [4]) + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/reg_quot_out.reg_quot/opt_has_pipe.first_q_5 ( + .C(clk), + .D(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/qpi [5]), + .Q(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/reg_quot_out.reg_quot/opt_has_pipe.first_q [5]) + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/reg_quot_out.reg_quot/opt_has_pipe.first_q_6 ( + .C(clk), + .D(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/qpi [6]), + .Q(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/reg_quot_out.reg_quot/opt_has_pipe.first_q [6]) + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/reg_quot_out.reg_quot/opt_has_pipe.first_q_7 ( + .C(clk), + .D(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/qpi [7]), + .Q(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/reg_quot_out.reg_quot/opt_has_pipe.first_q [7]) + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/reg_quot_out.reg_quot/opt_has_pipe.first_q_8 ( + .C(clk), + .D(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/qpi [8]), + .Q(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/reg_quot_out.reg_quot/opt_has_pipe.first_q [8]) + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/reg_quot_out.reg_quot/opt_has_pipe.first_q_9 ( + .C(clk), + .D(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/qpi [9]), + .Q(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/reg_quot_out.reg_quot/opt_has_pipe.first_q [9]) + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/reg_quot_out.reg_quot/opt_has_pipe.first_q_10 ( + .C(clk), + .D(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/qpi [10]), + .Q(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/reg_quot_out.reg_quot/opt_has_pipe.first_q [10]) + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/reg_quot_out.reg_quot/opt_has_pipe.first_q_11 ( + .C(clk), + .D(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/qpi [11]), + .Q(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/reg_quot_out.reg_quot/opt_has_pipe.first_q [11]) + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/reg_quot_out.reg_quot/opt_has_pipe.first_q_12 ( + .C(clk), + .D(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/qpi [12]), + .Q(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/reg_quot_out.reg_quot/opt_has_pipe.first_q [12]) + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/reg_quot_out.reg_quot/opt_has_pipe.first_q_13 ( + .C(clk), + .D(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/qpi [13]), + .Q(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/reg_quot_out.reg_quot/opt_has_pipe.first_q [13]) + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/reg_quot_out.reg_quot/opt_has_pipe.first_q_14 ( + .C(clk), + .D(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/qpi [14]), + .Q(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/reg_quot_out.reg_quot/opt_has_pipe.first_q [14]) + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/reg_quot_out.reg_quot/opt_has_pipe.first_q_15 ( + .C(clk), + .D(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/qpi [15]), + .Q(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/reg_quot_out.reg_quot/opt_has_pipe.first_q [15]) + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/reg_quot_out.reg_quot/opt_has_pipe.first_q_16 ( + .C(clk), + .D(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/qpi [16]), + .Q(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/reg_quot_out.reg_quot/opt_has_pipe.first_q [16]) + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/reg_quot_out.reg_quot/opt_has_pipe.first_q_17 ( + .C(clk), + .D(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/qpi [17]), + .Q(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/reg_quot_out.reg_quot/opt_has_pipe.first_q [17]) + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/reg_quot_out.reg_quot/opt_has_pipe.first_q_18 ( + .C(clk), + .D(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/qpi [18]), + .Q(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/reg_quot_out.reg_quot/opt_has_pipe.first_q [18]) + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/reg_quot_out.reg_quot/opt_has_pipe.first_q_19 ( + .C(clk), + .D(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/qpi [19]), + .Q(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/reg_quot_out.reg_quot/opt_has_pipe.first_q [19]) + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/reg_quot_out.reg_quot/opt_has_pipe.first_q_20 ( + .C(clk), + .D(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/qpi [20]), + .Q(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/reg_quot_out.reg_quot/opt_has_pipe.first_q [20]) + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/reg_quot_out.reg_quot/opt_has_pipe.first_q_21 ( + .C(clk), + .D(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/qpi [21]), + .Q(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/reg_quot_out.reg_quot/opt_has_pipe.first_q [21]) + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/reg_quot_out.reg_quot/opt_has_pipe.first_q_22 ( + .C(clk), + .D(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/qpi [22]), + .Q(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/reg_quot_out.reg_quot/opt_has_pipe.first_q [22]) + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/reg_quot_out.reg_quot/opt_has_pipe.first_q_23 ( + .C(clk), + .D(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/qpi [23]), + .Q(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/reg_quot_out.reg_quot/opt_has_pipe.first_q [23]) + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/reg_quot_out.reg_quot/opt_has_pipe.first_q_24 ( + .C(clk), + .D(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/qpi [24]), + .Q(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/reg_quot_out.reg_quot/opt_has_pipe.first_q [24]) + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/reg_quot_out.reg_quot/opt_has_pipe.first_q_25 ( + .C(clk), + .D(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/qpi [25]), + .Q(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/reg_quot_out.reg_quot/opt_has_pipe.first_q [25]) + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/reg_quot_out.reg_quot/opt_has_pipe.first_q_26 ( + .C(clk), + .D(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/qpi [26]), + .Q(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/reg_quot_out.reg_quot/opt_has_pipe.first_q [26]) + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/reg_quot_out.reg_quot/opt_has_pipe.first_q_27 ( + .C(clk), + .D(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/qpi [27]), + .Q(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/reg_quot_out.reg_quot/opt_has_pipe.first_q [27]) + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/reg_quot_out.reg_quot/opt_has_pipe.first_q_28 ( + .C(clk), + .D(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/qpi [28]), + .Q(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/reg_quot_out.reg_quot/opt_has_pipe.first_q [28]) + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/reg_quot_out.reg_quot/opt_has_pipe.first_q_29 ( + .C(clk), + .D(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/qpi [29]), + .Q(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/reg_quot_out.reg_quot/opt_has_pipe.first_q [29]) + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/reg_quot_out.reg_quot/opt_has_pipe.first_q_30 ( + .C(clk), + .D(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/qpi [30]), + .Q(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/reg_quot_out.reg_quot/opt_has_pipe.first_q [30]) + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/reg_quot_out.reg_quot/opt_has_pipe.first_q_31 ( + .C(clk), + .D(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/qpi [31]), + .Q(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/reg_quot_out.reg_quot/opt_has_pipe.first_q [31]) + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q_0 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<0> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[31].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q_0 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[0].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q_1 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<1> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q_0 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[1].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<0> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q_2 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<1> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<2> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q_1 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<0> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<1> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q_0 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[2].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<0> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q_3 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<2> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<3> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q_2 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<1> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<2> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q_1 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<0> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<1> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q_0 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[3].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<0> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q_4 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<3> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<4> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q_3 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<2> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<3> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q_2 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<1> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<2> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q_1 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<0> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<1> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q_0 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[4].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<0> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q_5 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<4> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<5> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q_4 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<3> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<4> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q_3 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<2> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<3> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q_2 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<1> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<2> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q_1 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<0> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<1> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q_0 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[5].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<0> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q_6 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<5> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<6> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q_5 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<4> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<5> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q_4 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<3> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<4> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q_3 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<2> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<3> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q_2 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<1> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<2> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q_1 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<0> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<1> ) + + ); + FD #( + .INIT ( 1'b1 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q_0 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[6].adder_gen.reg_req.adsu_mod/add1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/opt_has_pipe.first_q<24> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[7].quot_gen.quot_reg.quot_out/opt_has_pipe.first_q<0> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q_6 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<6> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<6> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q_5 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<5> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<5> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q_4 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<4> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<4> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q_3 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<3> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<3> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q_2 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<2> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<2> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q_1 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<1> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<1> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q_0 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[24].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<0> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<0> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q_5 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<5> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<5> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q_4 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<4> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<4> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q_3 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<3> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<3> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q_2 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<2> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<2> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q_1 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<1> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<1> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q_0 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[25].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<0> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<0> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q_4 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<4> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<4> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q_3 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<3> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<3> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q_2 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<2> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<2> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q_1 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<1> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<1> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q_0 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[26].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<0> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<0> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q_3 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<3> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<3> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q_2 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<2> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<2> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q_1 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<1> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<1> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q_0 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[27].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<0> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<0> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q_2 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<2> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<2> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q_1 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<1> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<1> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q_0 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[28].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<0> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<0> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q_1 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<1> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<1> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q_0 ( + .C(clk), + .D +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[29].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<0> ) +, + .Q +(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/divider_blk/div_loop[30].num_stages.numerator_gen.del_numer/opt_has_pipe.first_q<0> ) + + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sign_pipeline.sign_pipe/opt_has_pipe.first_q_0 ( + .C(clk), + .D(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sign_pipeline.msb_divisor_sync/opt_has_pipe.first_q ), + .Q(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sign_pipeline.sign_pipe/opt_has_pipe.first_q [0]) + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sign_pipeline.sign_pipe/opt_has_pipe.first_q_1 ( + .C(clk), + .D(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sign_pipeline.msb_dividend_sync/opt_has_pipe.first_q ), + .Q(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sign_pipeline.sign_pipe/opt_has_pipe.first_q [1]) + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sign_pipeline.sign_pipe/opt_has_pipe.pipe_33_0 ( + .C(clk), + .D(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sign_pipeline.sign_pipe/opt_has_pipe.pipe_32 [0]), + .Q(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sign_pipeline.sign_pipe/opt_has_pipe.pipe_33 [0]) + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sign_pipeline.sign_pipe/opt_has_pipe.pipe_33_1 ( + .C(clk), + .D(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sign_pipeline.sign_pipe/opt_has_pipe.pipe_32 [1]), + .Q(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sign_pipeline.sign_pipe/opt_has_pipe.pipe_33 [1]) + ); + MUXCY \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_divisor/twos_comp/Madd_s_i_cy<0> ( + .CI(\BU2/divide_by_zero ), + .DI(divisor_3[23]), + .S(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_divisor/twos_comp/Madd_s_i_cy<0>_rt_281 ), + .O(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_divisor/twos_comp/Madd_s_i_cy [0]) + ); + XORCY \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_divisor/twos_comp/Madd_s_i_xor<0> ( + .CI(\BU2/divide_by_zero ), + .LI(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_divisor/twos_comp/Madd_s_i_cy<0>_rt_281 ), + .O(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_divisor/twos_comp/s_i [0]) + ); + MUXCY \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_divisor/twos_comp/Madd_s_i_cy<1> ( + .CI(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_divisor/twos_comp/Madd_s_i_cy [0]), + .DI(\BU2/divide_by_zero ), + .S(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_divisor/twos_comp/simp_addp_a [1]), + .O(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_divisor/twos_comp/Madd_s_i_cy [1]) + ); + XORCY \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_divisor/twos_comp/Madd_s_i_xor<1> ( + .CI(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_divisor/twos_comp/Madd_s_i_cy [0]), + .LI(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_divisor/twos_comp/simp_addp_a [1]), + .O(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_divisor/twos_comp/s_i [1]) + ); + MUXCY \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_divisor/twos_comp/Madd_s_i_cy<2> ( + .CI(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_divisor/twos_comp/Madd_s_i_cy [1]), + .DI(\BU2/divide_by_zero ), + .S(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_divisor/twos_comp/simp_addp_a [2]), + .O(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_divisor/twos_comp/Madd_s_i_cy [2]) + ); + XORCY \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_divisor/twos_comp/Madd_s_i_xor<2> ( + .CI(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_divisor/twos_comp/Madd_s_i_cy [1]), + .LI(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_divisor/twos_comp/simp_addp_a [2]), + .O(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_divisor/twos_comp/s_i [2]) + ); + MUXCY \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_divisor/twos_comp/Madd_s_i_cy<3> ( + .CI(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_divisor/twos_comp/Madd_s_i_cy [2]), + .DI(\BU2/divide_by_zero ), + .S(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_divisor/twos_comp/simp_addp_a [3]), + .O(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_divisor/twos_comp/Madd_s_i_cy [3]) + ); + XORCY \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_divisor/twos_comp/Madd_s_i_xor<3> ( + .CI(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_divisor/twos_comp/Madd_s_i_cy [2]), + .LI(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_divisor/twos_comp/simp_addp_a [3]), + .O(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_divisor/twos_comp/s_i [3]) + ); + MUXCY \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_divisor/twos_comp/Madd_s_i_cy<4> ( + .CI(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_divisor/twos_comp/Madd_s_i_cy [3]), + .DI(\BU2/divide_by_zero ), + .S(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_divisor/twos_comp/simp_addp_a [4]), + .O(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_divisor/twos_comp/Madd_s_i_cy [4]) + ); + XORCY \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_divisor/twos_comp/Madd_s_i_xor<4> ( + .CI(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_divisor/twos_comp/Madd_s_i_cy [3]), + .LI(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_divisor/twos_comp/simp_addp_a [4]), + .O(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_divisor/twos_comp/s_i [4]) + ); + MUXCY \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_divisor/twos_comp/Madd_s_i_cy<5> ( + .CI(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_divisor/twos_comp/Madd_s_i_cy [4]), + .DI(\BU2/divide_by_zero ), + .S(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_divisor/twos_comp/simp_addp_a [5]), + .O(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_divisor/twos_comp/Madd_s_i_cy [5]) + ); + XORCY \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_divisor/twos_comp/Madd_s_i_xor<5> ( + .CI(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_divisor/twos_comp/Madd_s_i_cy [4]), + .LI(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_divisor/twos_comp/simp_addp_a [5]), + .O(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_divisor/twos_comp/s_i [5]) + ); + MUXCY \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_divisor/twos_comp/Madd_s_i_cy<6> ( + .CI(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_divisor/twos_comp/Madd_s_i_cy [5]), + .DI(\BU2/divide_by_zero ), + .S(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_divisor/twos_comp/simp_addp_a [6]), + .O(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_divisor/twos_comp/Madd_s_i_cy [6]) + ); + XORCY \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_divisor/twos_comp/Madd_s_i_xor<6> ( + .CI(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_divisor/twos_comp/Madd_s_i_cy [5]), + .LI(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_divisor/twos_comp/simp_addp_a [6]), + .O(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_divisor/twos_comp/s_i [6]) + ); + MUXCY \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_divisor/twos_comp/Madd_s_i_cy<7> ( + .CI(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_divisor/twos_comp/Madd_s_i_cy [6]), + .DI(\BU2/divide_by_zero ), + .S(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_divisor/twos_comp/simp_addp_a [7]), + .O(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_divisor/twos_comp/Madd_s_i_cy [7]) + ); + XORCY \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_divisor/twos_comp/Madd_s_i_xor<7> ( + .CI(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_divisor/twos_comp/Madd_s_i_cy [6]), + .LI(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_divisor/twos_comp/simp_addp_a [7]), + .O(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_divisor/twos_comp/s_i [7]) + ); + MUXCY \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_divisor/twos_comp/Madd_s_i_cy<8> ( + .CI(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_divisor/twos_comp/Madd_s_i_cy [7]), + .DI(\BU2/divide_by_zero ), + .S(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_divisor/twos_comp/simp_addp_a [8]), + .O(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_divisor/twos_comp/Madd_s_i_cy [8]) + ); + XORCY \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_divisor/twos_comp/Madd_s_i_xor<8> ( + .CI(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_divisor/twos_comp/Madd_s_i_cy [7]), + .LI(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_divisor/twos_comp/simp_addp_a [8]), + .O(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_divisor/twos_comp/s_i [8]) + ); + MUXCY \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_divisor/twos_comp/Madd_s_i_cy<9> ( + .CI(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_divisor/twos_comp/Madd_s_i_cy [8]), + .DI(\BU2/divide_by_zero ), + .S(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_divisor/twos_comp/simp_addp_a [9]), + .O(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_divisor/twos_comp/Madd_s_i_cy [9]) + ); + XORCY \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_divisor/twos_comp/Madd_s_i_xor<9> ( + .CI(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_divisor/twos_comp/Madd_s_i_cy [8]), + .LI(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_divisor/twos_comp/simp_addp_a [9]), + .O(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_divisor/twos_comp/s_i [9]) + ); + MUXCY \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_divisor/twos_comp/Madd_s_i_cy<10> ( + .CI(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_divisor/twos_comp/Madd_s_i_cy [9]), + .DI(\BU2/divide_by_zero ), + .S(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_divisor/twos_comp/simp_addp_a [10]), + .O(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_divisor/twos_comp/Madd_s_i_cy [10]) + ); + XORCY \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_divisor/twos_comp/Madd_s_i_xor<10> ( + .CI(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_divisor/twos_comp/Madd_s_i_cy [9]), + .LI(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_divisor/twos_comp/simp_addp_a [10]), + .O(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_divisor/twos_comp/s_i [10]) + ); + MUXCY \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_divisor/twos_comp/Madd_s_i_cy<11> ( + .CI(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_divisor/twos_comp/Madd_s_i_cy [10]), + .DI(\BU2/divide_by_zero ), + .S(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_divisor/twos_comp/simp_addp_a [11]), + .O(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_divisor/twos_comp/Madd_s_i_cy [11]) + ); + XORCY \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_divisor/twos_comp/Madd_s_i_xor<11> ( + .CI(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_divisor/twos_comp/Madd_s_i_cy [10]), + .LI(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_divisor/twos_comp/simp_addp_a [11]), + .O(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_divisor/twos_comp/s_i [11]) + ); + MUXCY \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_divisor/twos_comp/Madd_s_i_cy<12> ( + .CI(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_divisor/twos_comp/Madd_s_i_cy [11]), + .DI(\BU2/divide_by_zero ), + .S(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_divisor/twos_comp/simp_addp_a [12]), + .O(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_divisor/twos_comp/Madd_s_i_cy [12]) + ); + XORCY \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_divisor/twos_comp/Madd_s_i_xor<12> ( + .CI(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_divisor/twos_comp/Madd_s_i_cy [11]), + .LI(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_divisor/twos_comp/simp_addp_a [12]), + .O(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_divisor/twos_comp/s_i [12]) + ); + MUXCY \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_divisor/twos_comp/Madd_s_i_cy<13> ( + .CI(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_divisor/twos_comp/Madd_s_i_cy [12]), + .DI(\BU2/divide_by_zero ), + .S(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_divisor/twos_comp/simp_addp_a [13]), + .O(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_divisor/twos_comp/Madd_s_i_cy [13]) + ); + XORCY \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_divisor/twos_comp/Madd_s_i_xor<13> ( + .CI(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_divisor/twos_comp/Madd_s_i_cy [12]), + .LI(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_divisor/twos_comp/simp_addp_a [13]), + .O(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_divisor/twos_comp/s_i [13]) + ); + MUXCY \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_divisor/twos_comp/Madd_s_i_cy<14> ( + .CI(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_divisor/twos_comp/Madd_s_i_cy [13]), + .DI(\BU2/divide_by_zero ), + .S(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_divisor/twos_comp/simp_addp_a [14]), + .O(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_divisor/twos_comp/Madd_s_i_cy [14]) + ); + XORCY \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_divisor/twos_comp/Madd_s_i_xor<14> ( + .CI(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_divisor/twos_comp/Madd_s_i_cy [13]), + .LI(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_divisor/twos_comp/simp_addp_a [14]), + .O(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_divisor/twos_comp/s_i [14]) + ); + MUXCY \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_divisor/twos_comp/Madd_s_i_cy<15> ( + .CI(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_divisor/twos_comp/Madd_s_i_cy [14]), + .DI(\BU2/divide_by_zero ), + .S(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_divisor/twos_comp/simp_addp_a [15]), + .O(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_divisor/twos_comp/Madd_s_i_cy [15]) + ); + XORCY \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_divisor/twos_comp/Madd_s_i_xor<15> ( + .CI(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_divisor/twos_comp/Madd_s_i_cy [14]), + .LI(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_divisor/twos_comp/simp_addp_a [15]), + .O(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_divisor/twos_comp/s_i [15]) + ); + MUXCY \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_divisor/twos_comp/Madd_s_i_cy<16> ( + .CI(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_divisor/twos_comp/Madd_s_i_cy [15]), + .DI(\BU2/divide_by_zero ), + .S(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_divisor/twos_comp/simp_addp_a [16]), + .O(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_divisor/twos_comp/Madd_s_i_cy [16]) + ); + XORCY \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_divisor/twos_comp/Madd_s_i_xor<16> ( + .CI(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_divisor/twos_comp/Madd_s_i_cy [15]), + .LI(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_divisor/twos_comp/simp_addp_a [16]), + .O(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_divisor/twos_comp/s_i [16]) + ); + MUXCY \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_divisor/twos_comp/Madd_s_i_cy<17> ( + .CI(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_divisor/twos_comp/Madd_s_i_cy [16]), + .DI(\BU2/divide_by_zero ), + .S(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_divisor/twos_comp/simp_addp_a [17]), + .O(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_divisor/twos_comp/Madd_s_i_cy [17]) + ); + XORCY \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_divisor/twos_comp/Madd_s_i_xor<17> ( + .CI(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_divisor/twos_comp/Madd_s_i_cy [16]), + .LI(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_divisor/twos_comp/simp_addp_a [17]), + .O(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_divisor/twos_comp/s_i [17]) + ); + MUXCY \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_divisor/twos_comp/Madd_s_i_cy<18> ( + .CI(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_divisor/twos_comp/Madd_s_i_cy [17]), + .DI(\BU2/divide_by_zero ), + .S(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_divisor/twos_comp/simp_addp_a [18]), + .O(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_divisor/twos_comp/Madd_s_i_cy [18]) + ); + XORCY \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_divisor/twos_comp/Madd_s_i_xor<18> ( + .CI(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_divisor/twos_comp/Madd_s_i_cy [17]), + .LI(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_divisor/twos_comp/simp_addp_a [18]), + .O(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_divisor/twos_comp/s_i [18]) + ); + MUXCY \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_divisor/twos_comp/Madd_s_i_cy<19> ( + .CI(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_divisor/twos_comp/Madd_s_i_cy [18]), + .DI(\BU2/divide_by_zero ), + .S(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_divisor/twos_comp/simp_addp_a [19]), + .O(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_divisor/twos_comp/Madd_s_i_cy [19]) + ); + XORCY \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_divisor/twos_comp/Madd_s_i_xor<19> ( + .CI(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_divisor/twos_comp/Madd_s_i_cy [18]), + .LI(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_divisor/twos_comp/simp_addp_a [19]), + .O(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_divisor/twos_comp/s_i [19]) + ); + MUXCY \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_divisor/twos_comp/Madd_s_i_cy<20> ( + .CI(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_divisor/twos_comp/Madd_s_i_cy [19]), + .DI(\BU2/divide_by_zero ), + .S(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_divisor/twos_comp/simp_addp_a [20]), + .O(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_divisor/twos_comp/Madd_s_i_cy [20]) + ); + XORCY \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_divisor/twos_comp/Madd_s_i_xor<20> ( + .CI(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_divisor/twos_comp/Madd_s_i_cy [19]), + .LI(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_divisor/twos_comp/simp_addp_a [20]), + .O(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_divisor/twos_comp/s_i [20]) + ); + MUXCY \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_divisor/twos_comp/Madd_s_i_cy<21> ( + .CI(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_divisor/twos_comp/Madd_s_i_cy [20]), + .DI(\BU2/divide_by_zero ), + .S(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_divisor/twos_comp/simp_addp_a [21]), + .O(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_divisor/twos_comp/Madd_s_i_cy [21]) + ); + XORCY \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_divisor/twos_comp/Madd_s_i_xor<21> ( + .CI(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_divisor/twos_comp/Madd_s_i_cy [20]), + .LI(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_divisor/twos_comp/simp_addp_a [21]), + .O(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_divisor/twos_comp/s_i [21]) + ); + MUXCY \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_divisor/twos_comp/Madd_s_i_cy<22> ( + .CI(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_divisor/twos_comp/Madd_s_i_cy [21]), + .DI(\BU2/divide_by_zero ), + .S(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_divisor/twos_comp/simp_addp_a [22]), + .O(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_divisor/twos_comp/Madd_s_i_cy [22]) + ); + XORCY \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_divisor/twos_comp/Madd_s_i_xor<22> ( + .CI(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_divisor/twos_comp/Madd_s_i_cy [21]), + .LI(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_divisor/twos_comp/simp_addp_a [22]), + .O(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_divisor/twos_comp/s_i [22]) + ); + XORCY \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_divisor/twos_comp/Madd_s_i_xor<23> ( + .CI(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_divisor/twos_comp/Madd_s_i_cy [22]), + .LI(\BU2/divide_by_zero ), + .O(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_divisor/twos_comp/s_i [23]) + ); + MUXCY \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_dividend/twos_comp/Madd_s_i_cy<0> ( + .CI(\BU2/divide_by_zero ), + .DI(dividend_2[31]), + .S(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_dividend/twos_comp/Madd_s_i_cy<0>_rt_211 ), + .O(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_dividend/twos_comp/Madd_s_i_cy [0]) + ); + XORCY \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_dividend/twos_comp/Madd_s_i_xor<0> ( + .CI(\BU2/divide_by_zero ), + .LI(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_dividend/twos_comp/Madd_s_i_cy<0>_rt_211 ), + .O(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_dividend/twos_comp/s_i [0]) + ); + MUXCY \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_dividend/twos_comp/Madd_s_i_cy<1> ( + .CI(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_dividend/twos_comp/Madd_s_i_cy [0]), + .DI(\BU2/divide_by_zero ), + .S(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_dividend/twos_comp/simp_addp_a [1]), + .O(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_dividend/twos_comp/Madd_s_i_cy [1]) + ); + XORCY \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_dividend/twos_comp/Madd_s_i_xor<1> ( + .CI(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_dividend/twos_comp/Madd_s_i_cy [0]), + .LI(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_dividend/twos_comp/simp_addp_a [1]), + .O(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_dividend/twos_comp/s_i [1]) + ); + MUXCY \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_dividend/twos_comp/Madd_s_i_cy<2> ( + .CI(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_dividend/twos_comp/Madd_s_i_cy [1]), + .DI(\BU2/divide_by_zero ), + .S(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_dividend/twos_comp/simp_addp_a [2]), + .O(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_dividend/twos_comp/Madd_s_i_cy [2]) + ); + XORCY \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_dividend/twos_comp/Madd_s_i_xor<2> ( + .CI(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_dividend/twos_comp/Madd_s_i_cy [1]), + .LI(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_dividend/twos_comp/simp_addp_a [2]), + .O(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_dividend/twos_comp/s_i [2]) + ); + MUXCY \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_dividend/twos_comp/Madd_s_i_cy<3> ( + .CI(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_dividend/twos_comp/Madd_s_i_cy [2]), + .DI(\BU2/divide_by_zero ), + .S(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_dividend/twos_comp/simp_addp_a [3]), + .O(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_dividend/twos_comp/Madd_s_i_cy [3]) + ); + XORCY \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_dividend/twos_comp/Madd_s_i_xor<3> ( + .CI(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_dividend/twos_comp/Madd_s_i_cy [2]), + .LI(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_dividend/twos_comp/simp_addp_a [3]), + .O(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_dividend/twos_comp/s_i [3]) + ); + MUXCY \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_dividend/twos_comp/Madd_s_i_cy<4> ( + .CI(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_dividend/twos_comp/Madd_s_i_cy [3]), + .DI(\BU2/divide_by_zero ), + .S(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_dividend/twos_comp/simp_addp_a [4]), + .O(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_dividend/twos_comp/Madd_s_i_cy [4]) + ); + XORCY \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_dividend/twos_comp/Madd_s_i_xor<4> ( + .CI(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_dividend/twos_comp/Madd_s_i_cy [3]), + .LI(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_dividend/twos_comp/simp_addp_a [4]), + .O(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_dividend/twos_comp/s_i [4]) + ); + MUXCY \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_dividend/twos_comp/Madd_s_i_cy<5> ( + .CI(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_dividend/twos_comp/Madd_s_i_cy [4]), + .DI(\BU2/divide_by_zero ), + .S(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_dividend/twos_comp/simp_addp_a [5]), + .O(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_dividend/twos_comp/Madd_s_i_cy [5]) + ); + XORCY \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_dividend/twos_comp/Madd_s_i_xor<5> ( + .CI(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_dividend/twos_comp/Madd_s_i_cy [4]), + .LI(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_dividend/twos_comp/simp_addp_a [5]), + .O(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_dividend/twos_comp/s_i [5]) + ); + MUXCY \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_dividend/twos_comp/Madd_s_i_cy<6> ( + .CI(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_dividend/twos_comp/Madd_s_i_cy [5]), + .DI(\BU2/divide_by_zero ), + .S(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_dividend/twos_comp/simp_addp_a [6]), + .O(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_dividend/twos_comp/Madd_s_i_cy [6]) + ); + XORCY \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_dividend/twos_comp/Madd_s_i_xor<6> ( + .CI(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_dividend/twos_comp/Madd_s_i_cy [5]), + .LI(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_dividend/twos_comp/simp_addp_a [6]), + .O(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_dividend/twos_comp/s_i [6]) + ); + MUXCY \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_dividend/twos_comp/Madd_s_i_cy<7> ( + .CI(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_dividend/twos_comp/Madd_s_i_cy [6]), + .DI(\BU2/divide_by_zero ), + .S(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_dividend/twos_comp/simp_addp_a [7]), + .O(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_dividend/twos_comp/Madd_s_i_cy [7]) + ); + XORCY \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_dividend/twos_comp/Madd_s_i_xor<7> ( + .CI(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_dividend/twos_comp/Madd_s_i_cy [6]), + .LI(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_dividend/twos_comp/simp_addp_a [7]), + .O(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_dividend/twos_comp/s_i [7]) + ); + MUXCY \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_dividend/twos_comp/Madd_s_i_cy<8> ( + .CI(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_dividend/twos_comp/Madd_s_i_cy [7]), + .DI(\BU2/divide_by_zero ), + .S(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_dividend/twos_comp/simp_addp_a [8]), + .O(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_dividend/twos_comp/Madd_s_i_cy [8]) + ); + XORCY \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_dividend/twos_comp/Madd_s_i_xor<8> ( + .CI(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_dividend/twos_comp/Madd_s_i_cy [7]), + .LI(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_dividend/twos_comp/simp_addp_a [8]), + .O(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_dividend/twos_comp/s_i [8]) + ); + MUXCY \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_dividend/twos_comp/Madd_s_i_cy<9> ( + .CI(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_dividend/twos_comp/Madd_s_i_cy [8]), + .DI(\BU2/divide_by_zero ), + .S(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_dividend/twos_comp/simp_addp_a [9]), + .O(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_dividend/twos_comp/Madd_s_i_cy [9]) + ); + XORCY \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_dividend/twos_comp/Madd_s_i_xor<9> ( + .CI(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_dividend/twos_comp/Madd_s_i_cy [8]), + .LI(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_dividend/twos_comp/simp_addp_a [9]), + .O(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_dividend/twos_comp/s_i [9]) + ); + MUXCY \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_dividend/twos_comp/Madd_s_i_cy<10> ( + .CI(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_dividend/twos_comp/Madd_s_i_cy [9]), + .DI(\BU2/divide_by_zero ), + .S(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_dividend/twos_comp/simp_addp_a [10]), + .O(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_dividend/twos_comp/Madd_s_i_cy [10]) + ); + XORCY \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_dividend/twos_comp/Madd_s_i_xor<10> ( + .CI(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_dividend/twos_comp/Madd_s_i_cy [9]), + .LI(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_dividend/twos_comp/simp_addp_a [10]), + .O(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_dividend/twos_comp/s_i [10]) + ); + MUXCY \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_dividend/twos_comp/Madd_s_i_cy<11> ( + .CI(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_dividend/twos_comp/Madd_s_i_cy [10]), + .DI(\BU2/divide_by_zero ), + .S(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_dividend/twos_comp/simp_addp_a [11]), + .O(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_dividend/twos_comp/Madd_s_i_cy [11]) + ); + XORCY \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_dividend/twos_comp/Madd_s_i_xor<11> ( + .CI(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_dividend/twos_comp/Madd_s_i_cy [10]), + .LI(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_dividend/twos_comp/simp_addp_a [11]), + .O(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_dividend/twos_comp/s_i [11]) + ); + MUXCY \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_dividend/twos_comp/Madd_s_i_cy<12> ( + .CI(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_dividend/twos_comp/Madd_s_i_cy [11]), + .DI(\BU2/divide_by_zero ), + .S(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_dividend/twos_comp/simp_addp_a [12]), + .O(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_dividend/twos_comp/Madd_s_i_cy [12]) + ); + XORCY \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_dividend/twos_comp/Madd_s_i_xor<12> ( + .CI(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_dividend/twos_comp/Madd_s_i_cy [11]), + .LI(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_dividend/twos_comp/simp_addp_a [12]), + .O(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_dividend/twos_comp/s_i [12]) + ); + MUXCY \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_dividend/twos_comp/Madd_s_i_cy<13> ( + .CI(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_dividend/twos_comp/Madd_s_i_cy [12]), + .DI(\BU2/divide_by_zero ), + .S(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_dividend/twos_comp/simp_addp_a [13]), + .O(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_dividend/twos_comp/Madd_s_i_cy [13]) + ); + XORCY \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_dividend/twos_comp/Madd_s_i_xor<13> ( + .CI(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_dividend/twos_comp/Madd_s_i_cy [12]), + .LI(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_dividend/twos_comp/simp_addp_a [13]), + .O(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_dividend/twos_comp/s_i [13]) + ); + MUXCY \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_dividend/twos_comp/Madd_s_i_cy<14> ( + .CI(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_dividend/twos_comp/Madd_s_i_cy [13]), + .DI(\BU2/divide_by_zero ), + .S(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_dividend/twos_comp/simp_addp_a [14]), + .O(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_dividend/twos_comp/Madd_s_i_cy [14]) + ); + XORCY \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_dividend/twos_comp/Madd_s_i_xor<14> ( + .CI(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_dividend/twos_comp/Madd_s_i_cy [13]), + .LI(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_dividend/twos_comp/simp_addp_a [14]), + .O(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_dividend/twos_comp/s_i [14]) + ); + MUXCY \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_dividend/twos_comp/Madd_s_i_cy<15> ( + .CI(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_dividend/twos_comp/Madd_s_i_cy [14]), + .DI(\BU2/divide_by_zero ), + .S(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_dividend/twos_comp/simp_addp_a [15]), + .O(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_dividend/twos_comp/Madd_s_i_cy [15]) + ); + XORCY \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_dividend/twos_comp/Madd_s_i_xor<15> ( + .CI(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_dividend/twos_comp/Madd_s_i_cy [14]), + .LI(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_dividend/twos_comp/simp_addp_a [15]), + .O(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_dividend/twos_comp/s_i [15]) + ); + MUXCY \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_dividend/twos_comp/Madd_s_i_cy<16> ( + .CI(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_dividend/twos_comp/Madd_s_i_cy [15]), + .DI(\BU2/divide_by_zero ), + .S(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_dividend/twos_comp/simp_addp_a [16]), + .O(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_dividend/twos_comp/Madd_s_i_cy [16]) + ); + XORCY \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_dividend/twos_comp/Madd_s_i_xor<16> ( + .CI(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_dividend/twos_comp/Madd_s_i_cy [15]), + .LI(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_dividend/twos_comp/simp_addp_a [16]), + .O(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_dividend/twos_comp/s_i [16]) + ); + MUXCY \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_dividend/twos_comp/Madd_s_i_cy<17> ( + .CI(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_dividend/twos_comp/Madd_s_i_cy [16]), + .DI(\BU2/divide_by_zero ), + .S(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_dividend/twos_comp/simp_addp_a [17]), + .O(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_dividend/twos_comp/Madd_s_i_cy [17]) + ); + XORCY \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_dividend/twos_comp/Madd_s_i_xor<17> ( + .CI(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_dividend/twos_comp/Madd_s_i_cy [16]), + .LI(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_dividend/twos_comp/simp_addp_a [17]), + .O(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_dividend/twos_comp/s_i [17]) + ); + MUXCY \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_dividend/twos_comp/Madd_s_i_cy<18> ( + .CI(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_dividend/twos_comp/Madd_s_i_cy [17]), + .DI(\BU2/divide_by_zero ), + .S(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_dividend/twos_comp/simp_addp_a [18]), + .O(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_dividend/twos_comp/Madd_s_i_cy [18]) + ); + XORCY \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_dividend/twos_comp/Madd_s_i_xor<18> ( + .CI(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_dividend/twos_comp/Madd_s_i_cy [17]), + .LI(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_dividend/twos_comp/simp_addp_a [18]), + .O(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_dividend/twos_comp/s_i [18]) + ); + MUXCY \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_dividend/twos_comp/Madd_s_i_cy<19> ( + .CI(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_dividend/twos_comp/Madd_s_i_cy [18]), + .DI(\BU2/divide_by_zero ), + .S(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_dividend/twos_comp/simp_addp_a [19]), + .O(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_dividend/twos_comp/Madd_s_i_cy [19]) + ); + XORCY \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_dividend/twos_comp/Madd_s_i_xor<19> ( + .CI(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_dividend/twos_comp/Madd_s_i_cy [18]), + .LI(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_dividend/twos_comp/simp_addp_a [19]), + .O(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_dividend/twos_comp/s_i [19]) + ); + MUXCY \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_dividend/twos_comp/Madd_s_i_cy<20> ( + .CI(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_dividend/twos_comp/Madd_s_i_cy [19]), + .DI(\BU2/divide_by_zero ), + .S(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_dividend/twos_comp/simp_addp_a [20]), + .O(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_dividend/twos_comp/Madd_s_i_cy [20]) + ); + XORCY \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_dividend/twos_comp/Madd_s_i_xor<20> ( + .CI(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_dividend/twos_comp/Madd_s_i_cy [19]), + .LI(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_dividend/twos_comp/simp_addp_a [20]), + .O(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_dividend/twos_comp/s_i [20]) + ); + MUXCY \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_dividend/twos_comp/Madd_s_i_cy<21> ( + .CI(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_dividend/twos_comp/Madd_s_i_cy [20]), + .DI(\BU2/divide_by_zero ), + .S(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_dividend/twos_comp/simp_addp_a [21]), + .O(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_dividend/twos_comp/Madd_s_i_cy [21]) + ); + XORCY \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_dividend/twos_comp/Madd_s_i_xor<21> ( + .CI(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_dividend/twos_comp/Madd_s_i_cy [20]), + .LI(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_dividend/twos_comp/simp_addp_a [21]), + .O(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_dividend/twos_comp/s_i [21]) + ); + MUXCY \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_dividend/twos_comp/Madd_s_i_cy<22> ( + .CI(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_dividend/twos_comp/Madd_s_i_cy [21]), + .DI(\BU2/divide_by_zero ), + .S(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_dividend/twos_comp/simp_addp_a [22]), + .O(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_dividend/twos_comp/Madd_s_i_cy [22]) + ); + XORCY \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_dividend/twos_comp/Madd_s_i_xor<22> ( + .CI(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_dividend/twos_comp/Madd_s_i_cy [21]), + .LI(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_dividend/twos_comp/simp_addp_a [22]), + .O(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_dividend/twos_comp/s_i [22]) + ); + MUXCY \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_dividend/twos_comp/Madd_s_i_cy<23> ( + .CI(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_dividend/twos_comp/Madd_s_i_cy [22]), + .DI(\BU2/divide_by_zero ), + .S(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_dividend/twos_comp/simp_addp_a [23]), + .O(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_dividend/twos_comp/Madd_s_i_cy [23]) + ); + XORCY \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_dividend/twos_comp/Madd_s_i_xor<23> ( + .CI(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_dividend/twos_comp/Madd_s_i_cy [22]), + .LI(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_dividend/twos_comp/simp_addp_a [23]), + .O(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_dividend/twos_comp/s_i [23]) + ); + MUXCY \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_dividend/twos_comp/Madd_s_i_cy<24> ( + .CI(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_dividend/twos_comp/Madd_s_i_cy [23]), + .DI(\BU2/divide_by_zero ), + .S(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_dividend/twos_comp/simp_addp_a [24]), + .O(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_dividend/twos_comp/Madd_s_i_cy [24]) + ); + XORCY \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_dividend/twos_comp/Madd_s_i_xor<24> ( + .CI(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_dividend/twos_comp/Madd_s_i_cy [23]), + .LI(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_dividend/twos_comp/simp_addp_a [24]), + .O(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_dividend/twos_comp/s_i [24]) + ); + MUXCY \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_dividend/twos_comp/Madd_s_i_cy<25> ( + .CI(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_dividend/twos_comp/Madd_s_i_cy [24]), + .DI(\BU2/divide_by_zero ), + .S(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_dividend/twos_comp/simp_addp_a [25]), + .O(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_dividend/twos_comp/Madd_s_i_cy [25]) + ); + XORCY \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_dividend/twos_comp/Madd_s_i_xor<25> ( + .CI(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_dividend/twos_comp/Madd_s_i_cy [24]), + .LI(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_dividend/twos_comp/simp_addp_a [25]), + .O(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_dividend/twos_comp/s_i [25]) + ); + MUXCY \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_dividend/twos_comp/Madd_s_i_cy<26> ( + .CI(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_dividend/twos_comp/Madd_s_i_cy [25]), + .DI(\BU2/divide_by_zero ), + .S(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_dividend/twos_comp/simp_addp_a [26]), + .O(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_dividend/twos_comp/Madd_s_i_cy [26]) + ); + XORCY \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_dividend/twos_comp/Madd_s_i_xor<26> ( + .CI(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_dividend/twos_comp/Madd_s_i_cy [25]), + .LI(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_dividend/twos_comp/simp_addp_a [26]), + .O(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_dividend/twos_comp/s_i [26]) + ); + MUXCY \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_dividend/twos_comp/Madd_s_i_cy<27> ( + .CI(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_dividend/twos_comp/Madd_s_i_cy [26]), + .DI(\BU2/divide_by_zero ), + .S(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_dividend/twos_comp/simp_addp_a [27]), + .O(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_dividend/twos_comp/Madd_s_i_cy [27]) + ); + XORCY \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_dividend/twos_comp/Madd_s_i_xor<27> ( + .CI(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_dividend/twos_comp/Madd_s_i_cy [26]), + .LI(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_dividend/twos_comp/simp_addp_a [27]), + .O(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_dividend/twos_comp/s_i [27]) + ); + MUXCY \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_dividend/twos_comp/Madd_s_i_cy<28> ( + .CI(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_dividend/twos_comp/Madd_s_i_cy [27]), + .DI(\BU2/divide_by_zero ), + .S(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_dividend/twos_comp/simp_addp_a [28]), + .O(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_dividend/twos_comp/Madd_s_i_cy [28]) + ); + XORCY \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_dividend/twos_comp/Madd_s_i_xor<28> ( + .CI(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_dividend/twos_comp/Madd_s_i_cy [27]), + .LI(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_dividend/twos_comp/simp_addp_a [28]), + .O(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_dividend/twos_comp/s_i [28]) + ); + MUXCY \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_dividend/twos_comp/Madd_s_i_cy<29> ( + .CI(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_dividend/twos_comp/Madd_s_i_cy [28]), + .DI(\BU2/divide_by_zero ), + .S(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_dividend/twos_comp/simp_addp_a [29]), + .O(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_dividend/twos_comp/Madd_s_i_cy [29]) + ); + XORCY \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_dividend/twos_comp/Madd_s_i_xor<29> ( + .CI(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_dividend/twos_comp/Madd_s_i_cy [28]), + .LI(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_dividend/twos_comp/simp_addp_a [29]), + .O(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_dividend/twos_comp/s_i [29]) + ); + MUXCY \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_dividend/twos_comp/Madd_s_i_cy<30> ( + .CI(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_dividend/twos_comp/Madd_s_i_cy [29]), + .DI(\BU2/divide_by_zero ), + .S(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_dividend/twos_comp/simp_addp_a [30]), + .O(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_dividend/twos_comp/Madd_s_i_cy [30]) + ); + XORCY \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_dividend/twos_comp/Madd_s_i_xor<30> ( + .CI(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_dividend/twos_comp/Madd_s_i_cy [29]), + .LI(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_dividend/twos_comp/simp_addp_a [30]), + .O(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_dividend/twos_comp/s_i [30]) + ); + XORCY \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_dividend/twos_comp/Madd_s_i_xor<31> ( + .CI(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_dividend/twos_comp/Madd_s_i_cy [30]), + .LI(\BU2/divide_by_zero ), + .O(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sgned_input.cmp_dividend/twos_comp/s_i [31]) + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sign_pipeline.msb_divisor_sync/opt_has_pipe.first_q_0 ( + .C(clk), + .D(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sign_pipeline.msb_divisor_start/opt_has_pipe.first_q ), + .Q(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sign_pipeline.msb_divisor_sync/opt_has_pipe.first_q ) + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sign_pipeline.msb_dividend_sync/opt_has_pipe.first_q_0 ( + .C(clk), + .D(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sign_pipeline.msb_dividend_start/opt_has_pipe.first_q ), + .Q(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sign_pipeline.msb_dividend_sync/opt_has_pipe.first_q ) + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sign_pipeline.msb_divisor_start/opt_has_pipe.first_q_0 ( + .C(clk), + .D(divisor_3[23]), + .Q(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sign_pipeline.msb_divisor_start/opt_has_pipe.first_q ) + ); + FD #( + .INIT ( 1'b0 )) + \BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sign_pipeline.msb_dividend_start/opt_has_pipe.first_q_0 ( + .C(clk), + .D(dividend_2[31]), + .Q(\BU2/U0/i_synth_opt.i_nonzero_fract.i_synth/i_algo_r2_nr.i_sdivider/I_SYNTH_MODEL/sign_pipeline.msb_dividend_start/opt_has_pipe.first_q ) + ); + VCC \BU2/XST_VCC ( + .P(NlwRenamedSig_OI_rfd) + ); + GND \BU2/XST_GND ( + .G(\BU2/divide_by_zero ) + ); + +// synthesis translate_on + +endmodule + +// synthesis translate_off + +`ifndef GLBL +`define GLBL + +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (weak1, weak0) GSR = GSR_int; + assign (weak1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + +endmodule + +`endif + +// synthesis translate_on diff --git a/verilog/coregen/rot_lut.v b/verilog/coregen/rot_lut.v new file mode 100644 index 0000000..20f3b22 --- /dev/null +++ b/verilog/coregen/rot_lut.v @@ -0,0 +1,143 @@ +/******************************************************************************* +* This file is owned and controlled by Xilinx and must be used * +* solely for design, simulation, implementation and creation of * +* design files limited to Xilinx devices or technologies. Use * +* with non-Xilinx devices or technologies is expressly prohibited * +* and immediately terminates your license. * +* * +* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" * +* SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR * +* XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION * +* AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION * +* OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS * +* IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, * +* AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE * +* FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY * +* WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE * +* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR * +* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF * +* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS * +* FOR A PARTICULAR PURPOSE. * +* * +* Xilinx products are not intended for use in life support * +* appliances, devices, or systems. Use in such applications are * +* expressly prohibited. * +* * +* (c) Copyright 1995-2009 Xilinx, Inc. * +* All rights reserved. * +*******************************************************************************/ +// The synthesis directives "translate_off/translate_on" specified below are +// supported by Xilinx, Mentor Graphics and Synplicity synthesis +// tools. Ensure they are correct for your synthesis tool(s). + +// You must compile the wrapper file rot_lut.v when simulating +// the core, rot_lut. When compiling the wrapper file, be sure to +// reference the XilinxCoreLib Verilog simulation library. For detailed +// instructions, please refer to the "CORE Generator Help". + +`timescale 1ns/1ps + +module rot_lut( + clka, + addra, + douta, + clkb, + addrb, + doutb); + + +input clka; +input [8 : 0] addra; +output [31 : 0] douta; +input clkb; +input [8 : 0] addrb; +output [31 : 0] doutb; + +// synthesis translate_off + + BLK_MEM_GEN_V4_2 #( + .C_ADDRA_WIDTH(9), + .C_ADDRB_WIDTH(9), + .C_ALGORITHM(1), + .C_BYTE_SIZE(9), + .C_COMMON_CLK(1), + .C_DEFAULT_DATA("0"), + .C_DISABLE_WARN_BHV_COLL(0), + .C_DISABLE_WARN_BHV_RANGE(0), + .C_FAMILY("spartan3"), + .C_HAS_ENA(0), + .C_HAS_ENB(0), + .C_HAS_INJECTERR(0), + .C_HAS_MEM_OUTPUT_REGS_A(0), + .C_HAS_MEM_OUTPUT_REGS_B(0), + .C_HAS_MUX_OUTPUT_REGS_A(0), + .C_HAS_MUX_OUTPUT_REGS_B(0), + .C_HAS_REGCEA(0), + .C_HAS_REGCEB(0), + .C_HAS_RSTA(0), + .C_HAS_RSTB(0), + .C_HAS_SOFTECC_INPUT_REGS_A(0), + .C_HAS_SOFTECC_OUTPUT_REGS_B(0), + .C_INITA_VAL("0"), + .C_INITB_VAL("0"), + .C_INIT_FILE_NAME("rot_lut.mif"), + .C_LOAD_INIT_FILE(1), + .C_MEM_TYPE(4), + .C_MUX_PIPELINE_STAGES(0), + .C_PRIM_TYPE(1), + .C_READ_DEPTH_A(512), + .C_READ_DEPTH_B(512), + .C_READ_WIDTH_A(32), + .C_READ_WIDTH_B(32), + .C_RSTRAM_A(0), + .C_RSTRAM_B(0), + .C_RST_PRIORITY_A("CE"), + .C_RST_PRIORITY_B("CE"), + .C_RST_TYPE("SYNC"), + .C_SIM_COLLISION_CHECK("ALL"), + .C_USE_BYTE_WEA(0), + .C_USE_BYTE_WEB(0), + .C_USE_DEFAULT_DATA(0), + .C_USE_ECC(0), + .C_USE_SOFTECC(0), + .C_WEA_WIDTH(1), + .C_WEB_WIDTH(1), + .C_WRITE_DEPTH_A(512), + .C_WRITE_DEPTH_B(512), + .C_WRITE_MODE_A("WRITE_FIRST"), + .C_WRITE_MODE_B("WRITE_FIRST"), + .C_WRITE_WIDTH_A(32), + .C_WRITE_WIDTH_B(32), + .C_XDEVICEFAMILY("spartan3adsp")) + inst ( + .CLKA(clka), + .ADDRA(addra), + .DOUTA(douta), + .CLKB(clkb), + .ADDRB(addrb), + .DOUTB(doutb), + .RSTA(), + .ENA(), + .REGCEA(), + .WEA(), + .DINA(), + .RSTB(), + .ENB(), + .REGCEB(), + .WEB(), + .DINB(), + .INJECTSBITERR(), + .INJECTDBITERR(), + .SBITERR(), + .DBITERR(), + .RDADDRECC()); + + +// synthesis translate_on + +// XST black box declaration +// box_type "black_box" +// synthesis attribute box_type of rot_lut is "black_box" + +endmodule + diff --git a/verilog/coregen/viterbi_v7_0.v b/verilog/coregen/viterbi_v7_0.v new file mode 100644 index 0000000..c41d6f8 --- /dev/null +++ b/verilog/coregen/viterbi_v7_0.v @@ -0,0 +1,68243 @@ +//////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved. +//////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor: Xilinx +// \ \ \/ Version: M.63c +// \ \ Application: netgen +// / / Filename: viterbi_v7_0.v +// /___/ /\ Timestamp: Sat Oct 29 17:54:17 2016 +// \ \ / \ +// \___\/\___\ +// +// Command : -intstyle ise -w -sim -ofmt verilog ./tmp/_cg/viterbi_v7_0.ngc ./tmp/_cg/viterbi_v7_0.v +// Device : 3sd3400afg676-5 +// Input file : ./tmp/_cg/viterbi_v7_0.ngc +// Output file : ./tmp/_cg/viterbi_v7_0.v +// # of Modules : 1 +// Design Name : viterbi_v7_0 +// Xilinx : /opt/Xilinx/12.2/ISE_DS/ISE/ +// +// Purpose: +// This verilog netlist is a verification model and uses simulation +// primitives which may not represent the true implementation of the +// device, however the netlist is functionally correct and should not +// be modified. This file cannot be synthesized and should only be used +// with supported simulation tools. +// +// Reference: +// Command Line Tools User Guide, Chapter 23 and Synthesis and Simulation Design Guide, Chapter 6 +// +//////////////////////////////////////////////////////////////////////////////// + +`timescale 1 ns/1 ps + +module viterbi_v7_0 ( + sclr, ce, rdy, clk, data_out, erase, data_in0, data_in1 +)/* synthesis syn_black_box syn_noprune=1 */; + input sclr; + input ce; + output rdy; + input clk; + output data_out; + input [1 : 0] erase; + input [2 : 0] data_in0; + input [2 : 0] data_in1; + + // synthesis translate_off + + wire \blk00000003/sig00000084 ; + wire \blk00000003/sig00000083 ; + wire \blk00000003/sig00000082 ; + wire \blk00000003/sig00000081 ; + wire \blk00000003/sig00000080 ; + wire \blk00000003/sig0000007f ; + wire \blk00000003/sig0000007e ; + wire \blk00000003/sig0000007d ; + wire \blk00000003/sig0000007c ; + wire \blk00000003/sig0000007b ; + wire \blk00000003/sig0000007a ; + wire \blk00000003/sig00000079 ; + wire \blk00000003/sig00000078 ; + wire \blk00000003/sig00000077 ; + wire \blk00000003/sig00000076 ; + wire \blk00000003/sig00000075 ; + wire \blk00000003/sig00000074 ; + wire \blk00000003/sig00000073 ; + wire \blk00000003/sig00000072 ; + wire \blk00000003/sig00000071 ; + wire \blk00000003/sig00000070 ; + wire \blk00000003/sig0000006f ; + wire \blk00000003/sig0000006e ; + wire \blk00000003/sig0000006d ; + wire \blk00000003/sig0000006c ; + wire \blk00000003/sig0000006b ; + wire \blk00000003/sig0000006a ; + wire \blk00000003/sig00000069 ; + wire \blk00000003/sig00000068 ; + wire \blk00000003/sig00000067 ; + wire \blk00000003/sig00000066 ; + wire \blk00000003/sig00000065 ; + wire \blk00000003/sig00000064 ; + wire \blk00000003/sig00000063 ; + wire \blk00000003/sig00000062 ; + wire \blk00000003/sig00000061 ; + wire \blk00000003/sig0000005e ; + wire \blk00000003/sig0000005d ; + wire \blk00000003/sig0000005c ; + wire \blk00000003/sig0000005b ; + wire \blk00000003/sig0000005a ; + wire \blk00000003/sig00000059 ; + wire \blk00000003/sig00000058 ; + wire \blk00000003/sig00000057 ; + wire \blk00000003/sig00000056 ; + wire \blk00000003/sig00000055 ; + wire \blk00000003/sig00000054 ; + wire \blk00000003/sig00000053 ; + wire \blk00000003/sig00000052 ; + wire \blk00000003/sig00000051 ; + wire \blk00000003/sig00000050 ; + wire \blk00000003/sig0000004f ; + wire \blk00000003/sig0000004e ; + wire \blk00000003/sig0000004d ; + wire \blk00000003/sig0000004c ; + wire \blk00000003/sig0000004b ; + wire \blk00000003/sig0000004a ; + wire \blk00000003/sig00000049 ; + wire \blk00000003/sig00000048 ; + wire \blk00000003/sig00000047 ; + wire \blk00000003/sig00000046 ; + wire \blk00000003/sig00000045 ; + wire \blk00000003/sig00000044 ; + wire \blk00000003/sig00000043 ; + wire \blk00000003/sig00000042 ; + wire \blk00000003/sig00000041 ; + wire \blk00000003/sig00000040 ; + wire \blk00000003/sig0000003f ; + wire \blk00000003/sig0000003e ; + wire \blk00000003/sig0000003d ; + wire \blk00000003/sig0000003c ; + wire \blk00000003/sig0000003b ; + wire \blk00000003/sig0000003a ; + wire \blk00000003/sig00000039 ; + wire \blk00000003/sig00000038 ; + wire \blk00000003/sig00000037 ; + wire \blk00000003/sig00000036 ; + wire \blk00000003/sig00000035 ; + wire \blk00000003/sig00000034 ; + wire \blk00000003/sig00000016 ; + wire \blk00000003/sig00000010 ; + wire \blk00000003/sig0000000e ; + wire \blk00000003/sig0000000c ; + wire \blk00000003/sig0000000b ; + wire \blk00000003/sig00000001 ; + wire \blk00000003/blk00000004/sig000021d1 ; + wire \blk00000003/blk00000004/sig000021d0 ; + wire \blk00000003/blk00000004/sig000021cf ; + wire \blk00000003/blk00000004/sig000021ce ; + wire \blk00000003/blk00000004/sig000021cd ; + wire \blk00000003/blk00000004/sig000021cc ; + wire \blk00000003/blk00000004/sig000021cb ; + wire \blk00000003/blk00000004/sig000021ca ; + wire \blk00000003/blk00000004/sig000021c9 ; + wire \blk00000003/blk00000004/sig000021c8 ; + wire \blk00000003/blk00000004/sig000021c7 ; + wire \blk00000003/blk00000004/sig000021c6 ; + wire \blk00000003/blk00000004/sig000021c5 ; + wire \blk00000003/blk00000004/sig000021c4 ; + wire \blk00000003/blk00000004/sig000021c3 ; + wire \blk00000003/blk00000004/sig000021c2 ; + wire \blk00000003/blk00000004/sig000021c1 ; + wire \blk00000003/blk00000004/sig000021c0 ; + wire \blk00000003/blk00000004/sig000021bf ; + wire \blk00000003/blk00000004/sig000021be ; + wire \blk00000003/blk00000004/sig000021bd ; + wire \blk00000003/blk00000004/sig000021bc ; + wire \blk00000003/blk00000004/sig000021bb ; + wire \blk00000003/blk00000004/sig000021ba ; + wire \blk00000003/blk00000004/sig000021b9 ; + wire \blk00000003/blk00000004/sig000021b8 ; + wire \blk00000003/blk00000004/sig000021b7 ; + wire \blk00000003/blk00000004/sig000021b6 ; + wire \blk00000003/blk00000004/sig000021b5 ; + wire \blk00000003/blk00000004/sig000021b4 ; + wire \blk00000003/blk00000004/sig000021b3 ; + wire \blk00000003/blk00000004/sig000021b2 ; + wire \blk00000003/blk00000004/sig000021b1 ; + wire \blk00000003/blk00000004/sig000021b0 ; + wire \blk00000003/blk00000004/sig000021af ; + wire \blk00000003/blk00000004/sig000021ae ; + wire \blk00000003/blk00000004/sig000021ad ; + wire \blk00000003/blk00000004/sig000021ac ; + wire \blk00000003/blk00000004/sig000021ab ; + wire \blk00000003/blk00000004/sig000021aa ; + wire \blk00000003/blk00000004/sig000021a9 ; + wire \blk00000003/blk00000004/sig000021a8 ; + wire \blk00000003/blk00000004/sig000021a7 ; + wire \blk00000003/blk00000004/sig000021a6 ; + wire \blk00000003/blk00000004/sig000021a5 ; + wire \blk00000003/blk00000004/sig000021a4 ; + wire \blk00000003/blk00000004/sig000021a3 ; + wire \blk00000003/blk00000004/sig000021a2 ; + wire \blk00000003/blk00000004/sig000021a1 ; + wire \blk00000003/blk00000004/sig000021a0 ; + wire \blk00000003/blk00000004/sig0000219f ; + wire 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\NLW_blk00000003/blk00000004/blk0000202d_DOA<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000004/blk0000202d_DOA<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000004/blk0000202d_DOA<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000004/blk0000202d_DOA<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000004/blk0000202d_DOA<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000004/blk0000202d_DOB<31>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000004/blk0000202d_DOB<30>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000004/blk0000202d_DOB<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000004/blk0000202d_DOB<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000004/blk0000202d_DOB<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000004/blk0000202d_DOB<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000004/blk0000202d_DOB<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000004/blk0000202d_DOB<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000004/blk0000202d_DOB<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000004/blk0000202d_DOB<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000004/blk0000202d_DOB<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000004/blk0000202d_DOB<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000004/blk0000202d_DOB<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000004/blk0000202d_DOB<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000004/blk0000202d_DOB<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000004/blk0000202d_DOB<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000004/blk0000202d_DOB<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000004/blk0000202d_DOB<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000004/blk0000202d_DOB<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000004/blk0000202d_DOB<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000004/blk0000202d_DOPA<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000004/blk0000202d_DOPA<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000004/blk0000202d_DOPA<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000004/blk0000202d_DOPA<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000004/blk0000202d_DOPB<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000004/blk0000202d_DOPB<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000004/blk0000202d_DOPB<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000004/blk0000202d_DOPB<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000004/blk0000202c_DOA<31>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000004/blk0000202c_DOA<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000004/blk0000202c_DOA<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000004/blk0000202c_DOA<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000004/blk0000202c_DOB<31>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000004/blk0000202c_DOB<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000004/blk0000202c_DOB<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000004/blk0000202c_DOB<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000004/blk0000202c_DOPA<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000004/blk0000202c_DOPA<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000004/blk0000202c_DOPA<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000004/blk0000202c_DOPA<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000004/blk0000202c_DOPB<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000004/blk0000202c_DOPB<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000004/blk0000202c_DOPB<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000004/blk0000202c_DOPB<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000004/blk0000202a_DOA<31>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000004/blk0000202a_DOA<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000004/blk0000202a_DOA<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000004/blk0000202a_DOA<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000004/blk0000202a_DOB<31>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000004/blk0000202a_DOB<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000004/blk0000202a_DOB<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000004/blk0000202a_DOB<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000004/blk0000202a_DOPA<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000004/blk0000202a_DOPA<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000004/blk0000202a_DOPA<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000004/blk0000202a_DOPA<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000004/blk0000202a_DOPB<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000004/blk0000202a_DOPB<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000004/blk0000202a_DOPB<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000004/blk0000202a_DOPB<0>_UNCONNECTED ; + wire [2 : 0] data_in0_0; + wire [2 : 0] data_in1_1; + wire [1 : 0] erase_2; + assign + erase_2[1] = erase[1], + erase_2[0] = erase[0], + data_in0_0[2] = data_in0[2], + data_in0_0[1] = data_in0[1], + data_in0_0[0] = data_in0[0], + data_in1_1[2] = data_in1[2], + data_in1_1[1] = data_in1[1], + data_in1_1[0] = data_in1[0]; + VCC blk00000001 ( + .P(NLW_blk00000001_P_UNCONNECTED) + ); + GND blk00000002 ( + .G(NLW_blk00000002_G_UNCONNECTED) + ); + RAMB16BWER #( + .DATA_WIDTH_A ( 36 ), + .DATA_WIDTH_B ( 36 ), + .DOA_REG ( 0 ), + .DOB_REG ( 0 ), + .EN_RSTRAM_A ( "TRUE" ), + .EN_RSTRAM_B ( "TRUE" ), + .INIT_A ( 36'h000000000 ), + .INIT_B ( 36'h000000000 ), + .INITP_00 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INITP_01 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INITP_02 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INITP_03 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INITP_04 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INITP_05 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .WRITE_MODE_B ( "READ_FIRST" ), + .SRVAL_A ( 36'h000000000 ), + .INIT_00 ( 256'h0405040600030404050105000407000205030504000105020507050605050000 ), + .INIT_01 ( 256'h0301030200070300030503040303000603070400000503060403040204010004 ), + .INIT_02 ( 256'h0105010601030104020102000107010202030204010102020207020602050100 ), + .INIT_03 ( 256'h0001000201070000000500040003010600070100010500060103010201010104 ), + .INIT_04 ( 256'h0405040602030404050105000407020205030504020105020507050605050200 ), + .INIT_05 ( 256'h0301030202070300030503040303020603070400020503060403040204010204 ), + .INIT_06 ( 256'h0105010603030104020102000107030202030204030102020207020602050300 ), + .INIT_07 ( 256'h0001000203070000000500040003030600070100030500060103010201010304 ), + .INIT_08 ( 256'h0405040604030404050105000407040205030504040105020507050605050400 ), + .INIT_09 ( 256'h0301030204070300030503040303040603070400040503060403040204010404 ), + .INIT_0A ( 256'h0105010605030104020102000107050202030204050102020207020602050500 ), + .INIT_0B ( 256'h0001000205070000000500040003050600070100050500060103010201010504 ), + .INIT_0C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_0D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_0E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_0F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_10 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_11 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_12 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_13 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_14 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_15 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_16 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_17 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_18 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_19 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_1A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_1B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_1C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_1D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_1E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_1F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_20 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_21 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_22 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_23 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_24 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_25 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_26 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_27 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_28 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_29 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_2A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_2B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_2C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_2D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_2E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_2F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_30 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_31 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_32 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_33 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_34 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_35 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_36 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_37 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_38 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_39 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_3A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_3B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_3C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_3D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_3E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_3F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_FILE ( "NONE" ), + .RSTTYPE ( "SYNC" ), + .RST_PRIORITY_A ( "CE" ), + .RST_PRIORITY_B ( "CE" ), + .SIM_COLLISION_CHECK ( "ALL" ), + .SIM_DEVICE ( "SPARTAN3ADSP" ), + .INITP_06 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INITP_07 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .WRITE_MODE_A ( "READ_FIRST" ), + .SRVAL_B ( 36'h000000000 )) + \blk00000003/blk00000004/blk0000202d ( + .CLKA(clk), + .CLKB(clk), + .ENA(ce), + .ENB(ce), + .RSTA(\blk00000003/sig00000001 ), + .RSTB(\blk00000003/sig00000001 ), + .REGCEA(\blk00000003/sig00000001 ), + .REGCEB(\blk00000003/sig00000001 ), + .ADDRA({\blk00000003/sig00000001 , \blk00000003/sig00000001 , \blk00000003/blk00000004/sig000002b3 , \blk00000003/blk00000004/sig000002b5 , +\blk00000003/blk00000004/sig000002b7 , \blk00000003/blk00000004/sig000002b9 , \blk00000003/blk00000004/sig000002bb , +\blk00000003/blk00000004/sig000002bd , \blk00000003/sig00000001 , \blk00000003/sig00000001 , \blk00000003/sig00000001 , \blk00000003/sig00000001 , +\blk00000003/sig00000001 , \blk00000003/sig00000001 }), + .ADDRB({\blk00000003/sig00000001 , \blk00000003/sig00000001 , \blk00000003/blk00000004/sig000002b3 , \blk00000003/blk00000004/sig000002b5 , +\blk00000003/blk00000004/sig000002b7 , \blk00000003/blk00000004/sig000002b9 , \blk00000003/blk00000004/sig000002bb , +\blk00000003/blk00000004/sig000002bd , \blk00000003/blk00000004/sig00000093 , \blk00000003/sig00000001 , \blk00000003/sig00000001 , +\blk00000003/sig00000001 , \blk00000003/sig00000001 , \blk00000003/sig00000001 }), + .DIA({\blk00000003/sig00000001 , \blk00000003/sig00000001 , \blk00000003/sig00000001 , \blk00000003/sig00000001 , \blk00000003/sig00000001 , +\blk00000003/sig00000001 , \blk00000003/sig00000001 , \blk00000003/sig00000001 , \blk00000003/sig00000001 , \blk00000003/sig00000001 , +\blk00000003/sig00000001 , \blk00000003/sig00000001 , \blk00000003/sig00000001 , \blk00000003/sig00000001 , \blk00000003/sig00000001 , +\blk00000003/sig00000001 , \blk00000003/sig00000001 , \blk00000003/sig00000001 , \blk00000003/sig00000001 , \blk00000003/sig00000001 , +\blk00000003/sig00000001 , \blk00000003/sig00000001 , \blk00000003/sig00000001 , \blk00000003/sig00000001 , \blk00000003/sig00000001 , +\blk00000003/sig00000001 , \blk00000003/sig00000001 , \blk00000003/sig00000001 , \blk00000003/sig00000001 , \blk00000003/sig00000001 , +\blk00000003/sig00000001 , \blk00000003/sig00000001 }), + .DIB({\blk00000003/sig00000001 , \blk00000003/sig00000001 , \blk00000003/sig00000001 , \blk00000003/sig00000001 , \blk00000003/sig00000001 , +\blk00000003/sig00000001 , \blk00000003/sig00000001 , \blk00000003/sig00000001 , \blk00000003/sig00000001 , \blk00000003/sig00000001 , +\blk00000003/sig00000001 , \blk00000003/sig00000001 , \blk00000003/sig00000001 , \blk00000003/sig00000001 , \blk00000003/sig00000001 , +\blk00000003/sig00000001 , \blk00000003/sig00000001 , \blk00000003/sig00000001 , \blk00000003/sig00000001 , \blk00000003/sig00000001 , +\blk00000003/sig00000001 , \blk00000003/sig00000001 , \blk00000003/sig00000001 , \blk00000003/sig00000001 , \blk00000003/sig00000001 , +\blk00000003/sig00000001 , \blk00000003/sig00000001 , \blk00000003/sig00000001 , \blk00000003/sig00000001 , \blk00000003/sig00000001 , +\blk00000003/sig00000001 , \blk00000003/sig00000001 }), + .DIPA({\blk00000003/sig00000001 , \blk00000003/sig00000001 , \blk00000003/sig00000001 , \blk00000003/sig00000001 }), + .DIPB({\blk00000003/sig00000001 , \blk00000003/sig00000001 , \blk00000003/sig00000001 , \blk00000003/sig00000001 }), + .WEA({\blk00000003/sig00000001 , \blk00000003/sig00000001 , \blk00000003/sig00000001 , \blk00000003/sig00000001 }), + .WEB({\blk00000003/sig00000001 , \blk00000003/sig00000001 , \blk00000003/sig00000001 , \blk00000003/sig00000001 }), + .DOA({\NLW_blk00000003/blk00000004/blk0000202d_DOA<31>_UNCONNECTED , \NLW_blk00000003/blk00000004/blk0000202d_DOA<30>_UNCONNECTED , +\NLW_blk00000003/blk00000004/blk0000202d_DOA<29>_UNCONNECTED , \NLW_blk00000003/blk00000004/blk0000202d_DOA<28>_UNCONNECTED , +\NLW_blk00000003/blk00000004/blk0000202d_DOA<27>_UNCONNECTED , \blk00000003/blk00000004/sig00001adf , \blk00000003/blk00000004/sig00001ade , +\blk00000003/blk00000004/sig00001add , \NLW_blk00000003/blk00000004/blk0000202d_DOA<23>_UNCONNECTED , +\NLW_blk00000003/blk00000004/blk0000202d_DOA<22>_UNCONNECTED , \NLW_blk00000003/blk00000004/blk0000202d_DOA<21>_UNCONNECTED , +\NLW_blk00000003/blk00000004/blk0000202d_DOA<20>_UNCONNECTED , \NLW_blk00000003/blk00000004/blk0000202d_DOA<19>_UNCONNECTED , +\blk00000003/blk00000004/sig00001adc , \blk00000003/blk00000004/sig00001adb , \blk00000003/blk00000004/sig00001ada , +\NLW_blk00000003/blk00000004/blk0000202d_DOA<15>_UNCONNECTED , \NLW_blk00000003/blk00000004/blk0000202d_DOA<14>_UNCONNECTED , +\NLW_blk00000003/blk00000004/blk0000202d_DOA<13>_UNCONNECTED , \NLW_blk00000003/blk00000004/blk0000202d_DOA<12>_UNCONNECTED , +\NLW_blk00000003/blk00000004/blk0000202d_DOA<11>_UNCONNECTED , \blk00000003/blk00000004/sig00001ae5 , \blk00000003/blk00000004/sig00001ae4 , +\blk00000003/blk00000004/sig00001ae3 , \NLW_blk00000003/blk00000004/blk0000202d_DOA<7>_UNCONNECTED , +\NLW_blk00000003/blk00000004/blk0000202d_DOA<6>_UNCONNECTED , \NLW_blk00000003/blk00000004/blk0000202d_DOA<5>_UNCONNECTED , +\NLW_blk00000003/blk00000004/blk0000202d_DOA<4>_UNCONNECTED , \NLW_blk00000003/blk00000004/blk0000202d_DOA<3>_UNCONNECTED , +\blk00000003/blk00000004/sig00001ae2 , \blk00000003/blk00000004/sig00001ae1 , \blk00000003/blk00000004/sig00001ae0 }), + .DOB({\NLW_blk00000003/blk00000004/blk0000202d_DOB<31>_UNCONNECTED , \NLW_blk00000003/blk00000004/blk0000202d_DOB<30>_UNCONNECTED , +\NLW_blk00000003/blk00000004/blk0000202d_DOB<29>_UNCONNECTED , \NLW_blk00000003/blk00000004/blk0000202d_DOB<28>_UNCONNECTED , +\NLW_blk00000003/blk00000004/blk0000202d_DOB<27>_UNCONNECTED , \blk00000003/blk00000004/sig00001ad3 , \blk00000003/blk00000004/sig00001ad2 , +\blk00000003/blk00000004/sig00001ad1 , \NLW_blk00000003/blk00000004/blk0000202d_DOB<23>_UNCONNECTED , +\NLW_blk00000003/blk00000004/blk0000202d_DOB<22>_UNCONNECTED , \NLW_blk00000003/blk00000004/blk0000202d_DOB<21>_UNCONNECTED , +\NLW_blk00000003/blk00000004/blk0000202d_DOB<20>_UNCONNECTED , \NLW_blk00000003/blk00000004/blk0000202d_DOB<19>_UNCONNECTED , +\blk00000003/blk00000004/sig00001ad0 , \blk00000003/blk00000004/sig00001acf , \blk00000003/blk00000004/sig00001ace , +\NLW_blk00000003/blk00000004/blk0000202d_DOB<15>_UNCONNECTED , \NLW_blk00000003/blk00000004/blk0000202d_DOB<14>_UNCONNECTED , +\NLW_blk00000003/blk00000004/blk0000202d_DOB<13>_UNCONNECTED , \NLW_blk00000003/blk00000004/blk0000202d_DOB<12>_UNCONNECTED , +\NLW_blk00000003/blk00000004/blk0000202d_DOB<11>_UNCONNECTED , \blk00000003/blk00000004/sig00001ad9 , \blk00000003/blk00000004/sig00001ad8 , +\blk00000003/blk00000004/sig00001ad7 , \NLW_blk00000003/blk00000004/blk0000202d_DOB<7>_UNCONNECTED , +\NLW_blk00000003/blk00000004/blk0000202d_DOB<6>_UNCONNECTED , \NLW_blk00000003/blk00000004/blk0000202d_DOB<5>_UNCONNECTED , +\NLW_blk00000003/blk00000004/blk0000202d_DOB<4>_UNCONNECTED , \NLW_blk00000003/blk00000004/blk0000202d_DOB<3>_UNCONNECTED , +\blk00000003/blk00000004/sig00001ad6 , \blk00000003/blk00000004/sig00001ad5 , \blk00000003/blk00000004/sig00001ad4 }), + .DOPA({\NLW_blk00000003/blk00000004/blk0000202d_DOPA<3>_UNCONNECTED , \NLW_blk00000003/blk00000004/blk0000202d_DOPA<2>_UNCONNECTED , +\NLW_blk00000003/blk00000004/blk0000202d_DOPA<1>_UNCONNECTED , \NLW_blk00000003/blk00000004/blk0000202d_DOPA<0>_UNCONNECTED }), + .DOPB({\NLW_blk00000003/blk00000004/blk0000202d_DOPB<3>_UNCONNECTED , \NLW_blk00000003/blk00000004/blk0000202d_DOPB<2>_UNCONNECTED , +\NLW_blk00000003/blk00000004/blk0000202d_DOPB<1>_UNCONNECTED , \NLW_blk00000003/blk00000004/blk0000202d_DOPB<0>_UNCONNECTED }) + ); + RAMB16BWER #( + .DATA_WIDTH_A ( 36 ), + .DATA_WIDTH_B ( 36 ), + .DOA_REG ( 0 ), + .DOB_REG ( 0 ), + .EN_RSTRAM_A ( "TRUE" ), + .EN_RSTRAM_B ( "TRUE" ), + .INIT_A ( 36'h000000000 ), + .INIT_B ( 36'h000000000 ), + .INITP_00 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INITP_01 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INITP_02 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INITP_03 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INITP_04 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INITP_05 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .WRITE_MODE_B ( "READ_FIRST" ), + .SRVAL_A ( 36'h000000000 ), + .INIT_00 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_01 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_02 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_03 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_04 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_05 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_06 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_07 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_08 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_09 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_0A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_0B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_0C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_0D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_0E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_0F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_10 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_11 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_12 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_13 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_14 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_15 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_16 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_17 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_18 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_19 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_1A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_1B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_1C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_1D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_1E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_1F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_20 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_21 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_22 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_23 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_24 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_25 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_26 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_27 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_28 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_29 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_2A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_2B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_2C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_2D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_2E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_2F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_30 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_31 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_32 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_33 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_34 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_35 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_36 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_37 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_38 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_39 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_3A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_3B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_3C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_3D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_3E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_3F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_FILE ( "NONE" ), + .RSTTYPE ( "SYNC" ), + .RST_PRIORITY_A ( "CE" ), + .RST_PRIORITY_B ( "CE" ), + .SIM_COLLISION_CHECK ( "ALL" ), + .SIM_DEVICE ( "SPARTAN3ADSP" ), + .INITP_06 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INITP_07 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .WRITE_MODE_A ( "READ_FIRST" ), + .SRVAL_B ( 36'h000000000 )) + \blk00000003/blk00000004/blk0000202c ( + .CLKA(clk), + .CLKB(clk), + .ENA(ce), + .ENB(ce), + .RSTA(\blk00000003/sig00000001 ), + .RSTB(\blk00000003/sig00000001 ), + .REGCEA(\blk00000003/sig00000001 ), + .REGCEB(\blk00000003/sig00000001 ), + .ADDRA({\blk00000003/sig00000001 , \blk00000003/sig00000001 , \blk00000003/sig00000001 , \blk00000003/blk00000004/sig00000269 , +\blk00000003/blk00000004/sig00000267 , \blk00000003/blk00000004/sig00000265 , \blk00000003/blk00000004/sig00000263 , +\blk00000003/blk00000004/sig00000261 , \blk00000003/blk00000004/sig0000025f , \blk00000003/sig00000001 , \blk00000003/sig00000001 , +\blk00000003/sig00000001 , \blk00000003/sig00000001 , \blk00000003/sig00000001 }), + .ADDRB({\blk00000003/sig00000001 , \blk00000003/sig00000001 , \blk00000003/sig00000001 , \blk00000003/blk00000004/sig00000275 , +\blk00000003/blk00000004/sig00000273 , \blk00000003/blk00000004/sig00000271 , \blk00000003/blk00000004/sig0000026f , +\blk00000003/blk00000004/sig0000026d , \blk00000003/blk00000004/sig0000026b , \blk00000003/sig00000001 , \blk00000003/sig00000001 , +\blk00000003/sig00000001 , \blk00000003/sig00000001 , \blk00000003/sig00000001 }), + .DIA({\blk00000003/sig00000001 , \blk00000003/blk00000004/sig00000243 , \blk00000003/blk00000004/sig00000241 , +\blk00000003/blk00000004/sig0000023f , \blk00000003/blk00000004/sig0000023d , \blk00000003/blk00000004/sig0000023b , +\blk00000003/blk00000004/sig00000239 , \blk00000003/blk00000004/sig00000237 , \blk00000003/sig00000001 , \blk00000003/blk00000004/sig00000235 , +\blk00000003/blk00000004/sig00000233 , \blk00000003/blk00000004/sig00000231 , \blk00000003/blk00000004/sig0000022f , +\blk00000003/blk00000004/sig0000022d , \blk00000003/blk00000004/sig0000022b , \blk00000003/blk00000004/sig00000229 , \blk00000003/sig00000001 , +\blk00000003/blk00000004/sig00000227 , \blk00000003/blk00000004/sig00000225 , \blk00000003/blk00000004/sig00000223 , +\blk00000003/blk00000004/sig00000221 , \blk00000003/blk00000004/sig0000021f , \blk00000003/blk00000004/sig0000021d , +\blk00000003/blk00000004/sig0000021b , \blk00000003/sig00000001 , \blk00000003/blk00000004/sig00000219 , \blk00000003/blk00000004/sig00000217 , +\blk00000003/blk00000004/sig00000215 , \blk00000003/blk00000004/sig00000213 , \blk00000003/blk00000004/sig00000211 , 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\blk00000003/sig00000001 , \blk00000003/sig00000001 , \blk00000003/sig00000001 }), + .DIPB({\blk00000003/sig00000001 , \blk00000003/sig00000001 , \blk00000003/sig00000001 , \blk00000003/sig00000001 }), + .WEA({\blk00000003/blk00000004/sig0000025d , \blk00000003/blk00000004/sig0000025d , \blk00000003/blk00000004/sig0000025d , +\blk00000003/blk00000004/sig0000025d }), + .WEB({\blk00000003/sig00000001 , \blk00000003/sig00000001 , \blk00000003/sig00000001 , \blk00000003/sig00000001 }), + .DOA({\NLW_blk00000003/blk00000004/blk0000202c_DOA<31>_UNCONNECTED , \blk00000003/blk00000004/sig00001d16 , \blk00000003/blk00000004/sig00001d1b +, \blk00000003/blk00000004/sig00001d20 , \blk00000003/blk00000004/sig00001d25 , \blk00000003/blk00000004/sig00001d2a , +\blk00000003/blk00000004/sig00001d2f , \blk00000003/blk00000004/sig00001ce9 , \NLW_blk00000003/blk00000004/blk0000202c_DOA<23>_UNCONNECTED , +\blk00000003/blk00000004/sig00001cee , \blk00000003/blk00000004/sig00001cf3 , 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\blk00000003/blk00000004/sig00001b1b +, \blk00000003/blk00000004/sig00001b20 , \blk00000003/blk00000004/sig00001b25 , \blk00000003/blk00000004/sig00001b2a , +\blk00000003/blk00000004/sig00001b2f , \blk00000003/blk00000004/sig00001ae9 , \NLW_blk00000003/blk00000004/blk0000202c_DOB<23>_UNCONNECTED , +\blk00000003/blk00000004/sig00001aee , \blk00000003/blk00000004/sig00001af3 , \blk00000003/blk00000004/sig00001af8 , +\blk00000003/blk00000004/sig00001afd , \blk00000003/blk00000004/sig00001b02 , \blk00000003/blk00000004/sig00001b07 , +\blk00000003/blk00000004/sig00001b0c , \NLW_blk00000003/blk00000004/blk0000202c_DOB<15>_UNCONNECTED , \blk00000003/blk00000004/sig00001b11 , +\blk00000003/blk00000004/sig00001b34 , \blk00000003/blk00000004/sig00001b66 , \blk00000003/blk00000004/sig00001b6b , +\blk00000003/blk00000004/sig00001b70 , \blk00000003/blk00000004/sig00001b75 , \blk00000003/blk00000004/sig00001b7a , +\NLW_blk00000003/blk00000004/blk0000202c_DOB<7>_UNCONNECTED , \blk00000003/blk00000004/sig00001b7f , \blk00000003/blk00000004/sig00001b39 , +\blk00000003/blk00000004/sig00001b3e , \blk00000003/blk00000004/sig00001b43 , \blk00000003/blk00000004/sig00001b48 , +\blk00000003/blk00000004/sig00001b4d , \blk00000003/blk00000004/sig00001b52 }), + .DOPA({\NLW_blk00000003/blk00000004/blk0000202c_DOPA<3>_UNCONNECTED , \NLW_blk00000003/blk00000004/blk0000202c_DOPA<2>_UNCONNECTED , +\NLW_blk00000003/blk00000004/blk0000202c_DOPA<1>_UNCONNECTED , \NLW_blk00000003/blk00000004/blk0000202c_DOPA<0>_UNCONNECTED }), + .DOPB({\NLW_blk00000003/blk00000004/blk0000202c_DOPB<3>_UNCONNECTED , \NLW_blk00000003/blk00000004/blk0000202c_DOPB<2>_UNCONNECTED , +\NLW_blk00000003/blk00000004/blk0000202c_DOPB<1>_UNCONNECTED , \NLW_blk00000003/blk00000004/blk0000202c_DOPB<0>_UNCONNECTED }) + ); + RAMB16BWER #( + .DATA_WIDTH_A ( 36 ), + .DATA_WIDTH_B ( 36 ), + .DOA_REG ( 0 ), + .DOB_REG ( 0 ), + .EN_RSTRAM_A ( "TRUE" ), + .EN_RSTRAM_B ( "TRUE" ), + .INIT_A ( 36'h000000000 ), + .INIT_B ( 36'h000000000 ), + .INITP_00 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INITP_01 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INITP_02 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INITP_03 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INITP_04 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INITP_05 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .WRITE_MODE_B ( "READ_FIRST" ), + .SRVAL_A ( 36'h000000000 ), + .INIT_00 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_01 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_02 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_03 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_04 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_05 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_06 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_07 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_08 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_09 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_0A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_0B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_0C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_0D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_0E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_0F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_10 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_11 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_12 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_13 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_14 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_15 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_16 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_17 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_18 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_19 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_1A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_1B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_1C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_1D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_1E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_1F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_20 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_21 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_22 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_23 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_24 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_25 ( 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256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_31 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_32 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_33 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_34 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_35 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_36 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_37 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_38 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_39 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_3A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_3B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_3C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_3D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_3E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_3F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_FILE ( "NONE" ), + .RSTTYPE ( "SYNC" ), + .RST_PRIORITY_A ( "CE" ), + .RST_PRIORITY_B ( "CE" ), + .SIM_COLLISION_CHECK ( "ALL" ), + .SIM_DEVICE ( "SPARTAN3ADSP" ), + .INITP_06 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INITP_07 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .WRITE_MODE_A ( "READ_FIRST" ), + .SRVAL_B ( 36'h000000000 )) + \blk00000003/blk00000004/blk0000202b ( + .CLKA(clk), + .CLKB(clk), + .ENA(ce), + .ENB(ce), + .RSTA(\blk00000003/sig00000001 ), + .RSTB(\blk00000003/sig00000001 ), + .REGCEA(\blk00000003/sig00000001 ), + .REGCEB(\blk00000003/sig00000001 ), + .ADDRA({\blk00000003/sig00000001 , \blk00000003/sig00000001 , \blk00000003/sig00000001 , \blk00000003/blk00000004/sig00000269 , +\blk00000003/blk00000004/sig00000267 , \blk00000003/blk00000004/sig00000265 , \blk00000003/blk00000004/sig00000263 , +\blk00000003/blk00000004/sig00000261 , \blk00000003/blk00000004/sig0000025f , \blk00000003/sig00000001 , \blk00000003/sig00000001 , +\blk00000003/sig00000001 , \blk00000003/sig00000001 , \blk00000003/sig00000001 }), + .ADDRB({\blk00000003/sig00000001 , \blk00000003/sig00000001 , \blk00000003/sig00000001 , \blk00000003/blk00000004/sig00000275 , +\blk00000003/blk00000004/sig00000273 , \blk00000003/blk00000004/sig00000271 , \blk00000003/blk00000004/sig0000026f , +\blk00000003/blk00000004/sig0000026d , \blk00000003/blk00000004/sig0000026b , \blk00000003/sig00000001 , \blk00000003/sig00000001 , +\blk00000003/sig00000001 , \blk00000003/sig00000001 , \blk00000003/sig00000001 }), + .DIA({\blk00000003/blk00000004/sig00000209 , \blk00000003/blk00000004/sig00000207 , \blk00000003/blk00000004/sig00000205 , +\blk00000003/blk00000004/sig00000203 , \blk00000003/blk00000004/sig00000201 , \blk00000003/blk00000004/sig000001ff , +\blk00000003/blk00000004/sig000001fd , \blk00000003/blk00000004/sig000001fb , \blk00000003/blk00000004/sig000001f7 , +\blk00000003/blk00000004/sig000001f5 , \blk00000003/blk00000004/sig000001f3 , \blk00000003/blk00000004/sig000001f1 , +\blk00000003/blk00000004/sig000001ef , \blk00000003/blk00000004/sig000001ed , \blk00000003/blk00000004/sig000001eb , +\blk00000003/blk00000004/sig000001e9 , \blk00000003/blk00000004/sig000001e5 , \blk00000003/blk00000004/sig000001e3 , +\blk00000003/blk00000004/sig000001e1 , \blk00000003/blk00000004/sig000001df , \blk00000003/blk00000004/sig000001dd , +\blk00000003/blk00000004/sig000001db , \blk00000003/blk00000004/sig000001d9 , \blk00000003/blk00000004/sig000001d7 , +\blk00000003/blk00000004/sig000001d3 , \blk00000003/blk00000004/sig000001d1 , \blk00000003/blk00000004/sig000001cf , +\blk00000003/blk00000004/sig000001cd , \blk00000003/blk00000004/sig000001cb , \blk00000003/blk00000004/sig000001c9 , +\blk00000003/blk00000004/sig000001c7 , \blk00000003/blk00000004/sig000001c5 }), + .DIB({\blk00000003/sig00000001 , \blk00000003/sig00000001 , \blk00000003/sig00000001 , \blk00000003/sig00000001 , \blk00000003/sig00000001 , +\blk00000003/sig00000001 , \blk00000003/sig00000001 , \blk00000003/sig00000001 , \blk00000003/sig00000001 , \blk00000003/sig00000001 , +\blk00000003/sig00000001 , \blk00000003/sig00000001 , \blk00000003/sig00000001 , \blk00000003/sig00000001 , \blk00000003/sig00000001 , +\blk00000003/sig00000001 , \blk00000003/sig00000001 , \blk00000003/sig00000001 , \blk00000003/sig00000001 , \blk00000003/sig00000001 , +\blk00000003/sig00000001 , \blk00000003/sig00000001 , \blk00000003/sig00000001 , \blk00000003/sig00000001 , \blk00000003/sig00000001 , +\blk00000003/sig00000001 , \blk00000003/sig00000001 , \blk00000003/sig00000001 , \blk00000003/sig00000001 , \blk00000003/sig00000001 , +\blk00000003/sig00000001 , \blk00000003/sig00000001 }), + .DIPA({\blk00000003/blk00000004/sig0000020b , \blk00000003/blk00000004/sig000001f9 , \blk00000003/blk00000004/sig000001e7 , +\blk00000003/blk00000004/sig000001d5 }), + .DIPB({\blk00000003/sig00000001 , \blk00000003/sig00000001 , \blk00000003/sig00000001 , \blk00000003/sig00000001 }), + .WEA({\blk00000003/blk00000004/sig0000025d , \blk00000003/blk00000004/sig0000025d , \blk00000003/blk00000004/sig0000025d , +\blk00000003/blk00000004/sig0000025d }), + .WEB({\blk00000003/sig00000001 , \blk00000003/sig00000001 , \blk00000003/sig00000001 , \blk00000003/sig00000001 }), + .DOA({\blk00000003/blk00000004/sig00001d5c , \blk00000003/blk00000004/sig00001d61 , \blk00000003/blk00000004/sig00001d84 , +\blk00000003/blk00000004/sig00001db6 , \blk00000003/blk00000004/sig00001dbb , \blk00000003/blk00000004/sig00001dc0 , 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\blk00000003/blk00000004/sig00001e24 }), + .DOB({\blk00000003/blk00000004/sig00001b5c , \blk00000003/blk00000004/sig00001b61 , \blk00000003/blk00000004/sig00001b84 , +\blk00000003/blk00000004/sig00001bb6 , \blk00000003/blk00000004/sig00001bbb , \blk00000003/blk00000004/sig00001bc0 , +\blk00000003/blk00000004/sig00001bc5 , \blk00000003/blk00000004/sig00001bca , \blk00000003/blk00000004/sig00001b89 , +\blk00000003/blk00000004/sig00001b8e , \blk00000003/blk00000004/sig00001b93 , \blk00000003/blk00000004/sig00001b98 , +\blk00000003/blk00000004/sig00001b9d , \blk00000003/blk00000004/sig00001ba2 , \blk00000003/blk00000004/sig00001ba7 , +\blk00000003/blk00000004/sig00001bac , \blk00000003/blk00000004/sig00001bd4 , \blk00000003/blk00000004/sig00001c06 , +\blk00000003/blk00000004/sig00001c0b , \blk00000003/blk00000004/sig00001c10 , \blk00000003/blk00000004/sig00001c15 , +\blk00000003/blk00000004/sig00001c1a , \blk00000003/blk00000004/sig00001c1f , \blk00000003/blk00000004/sig00001bd9 , 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256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INITP_02 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INITP_03 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INITP_04 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INITP_05 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .WRITE_MODE_B ( "READ_FIRST" ), + .SRVAL_A ( 36'h000000000 ), + .INIT_00 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_01 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_02 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_03 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_04 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_05 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), 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256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_12 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_13 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_14 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_15 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_16 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_17 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_18 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_19 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_1A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_1B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_1C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_1D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_1E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_1F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_20 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_21 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_22 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_23 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_24 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_25 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_26 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_27 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_28 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_29 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_2A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_2B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_2C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_2D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_2E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_2F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_30 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_31 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_32 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_33 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_34 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_35 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_36 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_37 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_38 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_39 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_3A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_3B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_3C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_3D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_3E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_3F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_FILE ( "NONE" ), + .RSTTYPE ( "SYNC" ), + .RST_PRIORITY_A ( "CE" ), + .RST_PRIORITY_B ( "CE" ), + .SIM_COLLISION_CHECK ( "ALL" ), + .SIM_DEVICE ( "SPARTAN3ADSP" ), + .INITP_06 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INITP_07 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .WRITE_MODE_A ( "READ_FIRST" ), + .SRVAL_B ( 36'h000000000 )) + \blk00000003/blk00000004/blk0000202a ( + .CLKA(clk), + .CLKB(clk), + .ENA(ce), + .ENB(ce), + .RSTA(\blk00000003/sig00000001 ), + .RSTB(\blk00000003/sig00000001 ), + .REGCEA(\blk00000003/sig00000001 ), + .REGCEB(\blk00000003/sig00000001 ), + .ADDRA({\blk00000003/sig00000001 , \blk00000003/sig00000001 , \blk00000003/sig00000001 , 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.I0(\blk00000003/blk00000004/sig000002fc ), + .I1(\blk00000003/blk00000004/sig000002f6 ), + .I2(\blk00000003/blk00000004/sig000002fe ), + .O(\blk00000003/blk00000004/sig0000033b ) + ); + LUT3 #( + .INIT ( 8'hC9 )) + \blk00000003/blk00000004/blk00001f88 ( + .I0(\blk00000003/blk00000004/sig000002f4 ), + .I1(\blk00000003/blk00000004/sig000002fa ), + .I2(\blk00000003/blk00000004/sig00000300 ), + .O(\blk00000003/blk00000004/sig0000034c ) + ); + LUT3 #( + .INIT ( 8'hC9 )) + \blk00000003/blk00000004/blk00001f87 ( + .I0(\blk00000003/blk00000004/sig000002fa ), + .I1(\blk00000003/blk00000004/sig000002f4 ), + .I2(\blk00000003/blk00000004/sig000002fe ), + .O(\blk00000003/blk00000004/sig0000033e ) + ); + LUT3 #( + .INIT ( 8'hC9 )) + \blk00000003/blk00000004/blk00001f86 ( + .I0(\blk00000003/blk00000004/sig000002f2 ), + .I1(\blk00000003/blk00000004/sig000002f8 ), + .I2(\blk00000003/blk00000004/sig00000300 ), + .O(\blk00000003/blk00000004/sig0000034d ) + ); + LUT3 #( + .INIT ( 8'hC9 )) + \blk00000003/blk00000004/blk00001f85 ( + .I0(\blk00000003/blk00000004/sig000002f8 ), + .I1(\blk00000003/blk00000004/sig000002f2 ), + .I2(\blk00000003/blk00000004/sig000002fe ), + .O(\blk00000003/blk00000004/sig0000033f ) + ); + LUT4 #( + .INIT ( 16'h0536 )) + \blk00000003/blk00000004/blk00001f84 ( + .I0(\blk00000003/blk00000004/sig000002fc ), + .I1(\blk00000003/blk00000004/sig000002f6 ), + .I2(\blk00000003/blk00000004/sig000002fe ), + .I3(\blk00000003/blk00000004/sig00000300 ), + .O(\blk00000003/blk00000004/sig0000032a ) + ); + LUT4 #( + .INIT ( 16'h0536 )) + \blk00000003/blk00000004/blk00001f83 ( + .I0(\blk00000003/blk00000004/sig000002fa ), + .I1(\blk00000003/blk00000004/sig000002f4 ), + .I2(\blk00000003/blk00000004/sig000002fe ), + .I3(\blk00000003/blk00000004/sig00000300 ), + .O(\blk00000003/blk00000004/sig0000032e ) + ); + LUT4 #( + .INIT ( 16'h0536 )) + \blk00000003/blk00000004/blk00001f82 ( + .I0(\blk00000003/blk00000004/sig000002f8 ), + .I1(\blk00000003/blk00000004/sig000002f2 ), + .I2(\blk00000003/blk00000004/sig000002fe ), + .I3(\blk00000003/blk00000004/sig00000300 ), + .O(\blk00000003/blk00000004/sig00000330 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000004/blk00001f81 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig0000028c ), + .I2(\blk00000003/blk00000004/sig00000285 ), + .I3(\blk00000003/blk00000004/sig0000027e ), + .O(\blk00000003/blk00000004/sig000002ac ) + ); + LUT4 #( + .INIT ( 16'h1441 )) + \blk00000003/blk00000004/blk00001f80 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00000645 ), + .I2(\blk00000003/blk00000004/sig0000064b ), + .I3(\blk00000003/blk00000004/sig00001acc ), + .O(\blk00000003/blk00000004/sig0000073e ) + ); + LUT4 #( + .INIT ( 16'h1441 )) + \blk00000003/blk00000004/blk00001f7f ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig000005cd ), + .I2(\blk00000003/blk00000004/sig000005d3 ), + .I3(\blk00000003/blk00000004/sig00001aca ), + .O(\blk00000003/blk00000004/sig0000072a ) + ); + LUT4 #( + .INIT ( 16'h1441 )) + \blk00000003/blk00000004/blk00001f7e ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig000005c1 ), + .I2(\blk00000003/blk00000004/sig000005c7 ), + .I3(\blk00000003/blk00000004/sig00001ac8 ), + .O(\blk00000003/blk00000004/sig00000728 ) + ); + LUT4 #( + .INIT ( 16'h1441 )) + \blk00000003/blk00000004/blk00001f7d ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig000005b5 ), + .I2(\blk00000003/blk00000004/sig000005bb ), + .I3(\blk00000003/blk00000004/sig00001ac6 ), + .O(\blk00000003/blk00000004/sig00000726 ) + ); + LUT4 #( + .INIT ( 16'h1441 )) + \blk00000003/blk00000004/blk00001f7c ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig000005a9 ), + .I2(\blk00000003/blk00000004/sig000005af ), + .I3(\blk00000003/blk00000004/sig00001ac4 ), + .O(\blk00000003/blk00000004/sig00000724 ) + ); + LUT4 #( + .INIT ( 16'h1441 )) + \blk00000003/blk00000004/blk00001f7b ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig0000059d ), + .I2(\blk00000003/blk00000004/sig000005a3 ), + .I3(\blk00000003/blk00000004/sig00001ac2 ), + .O(\blk00000003/blk00000004/sig00000722 ) + ); + LUT4 #( + .INIT ( 16'h1441 )) + \blk00000003/blk00000004/blk00001f7a ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00000591 ), + .I2(\blk00000003/blk00000004/sig00000597 ), + .I3(\blk00000003/blk00000004/sig00001ac0 ), + .O(\blk00000003/blk00000004/sig00000720 ) + ); + LUT4 #( + .INIT ( 16'h1441 )) + \blk00000003/blk00000004/blk00001f79 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00000585 ), + .I2(\blk00000003/blk00000004/sig0000058b ), + .I3(\blk00000003/blk00000004/sig00001abe ), + .O(\blk00000003/blk00000004/sig0000071e ) + ); + LUT4 #( + .INIT ( 16'h1441 )) + \blk00000003/blk00000004/blk00001f78 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00000579 ), + .I2(\blk00000003/blk00000004/sig0000057f ), + .I3(\blk00000003/blk00000004/sig00001abc ), + .O(\blk00000003/blk00000004/sig0000071c ) + ); + LUT4 #( + .INIT ( 16'h1441 )) + \blk00000003/blk00000004/blk00001f77 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig0000056d ), + .I2(\blk00000003/blk00000004/sig00000573 ), + .I3(\blk00000003/blk00000004/sig00001aba ), + .O(\blk00000003/blk00000004/sig0000071a ) + ); + LUT4 #( + .INIT ( 16'h1441 )) + \blk00000003/blk00000004/blk00001f76 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00000561 ), + .I2(\blk00000003/blk00000004/sig00000567 ), + .I3(\blk00000003/blk00000004/sig00001ab8 ), + .O(\blk00000003/blk00000004/sig00000718 ) + ); + LUT4 #( + .INIT ( 16'h1441 )) + \blk00000003/blk00000004/blk00001f75 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00000639 ), + .I2(\blk00000003/blk00000004/sig0000063f ), + .I3(\blk00000003/blk00000004/sig00001ab6 ), + .O(\blk00000003/blk00000004/sig0000073c ) + ); + LUT4 #( + .INIT ( 16'h1441 )) + \blk00000003/blk00000004/blk00001f74 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00000555 ), + .I2(\blk00000003/blk00000004/sig0000055b ), + .I3(\blk00000003/blk00000004/sig00001ab4 ), + .O(\blk00000003/blk00000004/sig00000716 ) + ); + LUT4 #( + .INIT ( 16'h1441 )) + \blk00000003/blk00000004/blk00001f73 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00000549 ), + .I2(\blk00000003/blk00000004/sig0000054f ), + .I3(\blk00000003/blk00000004/sig00001ab2 ), + .O(\blk00000003/blk00000004/sig00000714 ) + ); + LUT4 #( + .INIT ( 16'h1441 )) + \blk00000003/blk00000004/blk00001f72 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig0000053d ), + .I2(\blk00000003/blk00000004/sig00000543 ), + .I3(\blk00000003/blk00000004/sig00001ab0 ), + .O(\blk00000003/blk00000004/sig00000712 ) + ); + LUT4 #( + .INIT ( 16'h1441 )) + \blk00000003/blk00000004/blk00001f71 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00000531 ), + .I2(\blk00000003/blk00000004/sig00000537 ), + .I3(\blk00000003/blk00000004/sig00001aae ), + .O(\blk00000003/blk00000004/sig00000710 ) + ); + LUT4 #( + .INIT ( 16'h1441 )) + \blk00000003/blk00000004/blk00001f70 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00000525 ), + .I2(\blk00000003/blk00000004/sig0000052b ), + .I3(\blk00000003/blk00000004/sig00001aac ), + .O(\blk00000003/blk00000004/sig0000070e ) + ); + LUT4 #( + .INIT ( 16'h1441 )) + \blk00000003/blk00000004/blk00001f6f ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00000519 ), + .I2(\blk00000003/blk00000004/sig0000051f ), + .I3(\blk00000003/blk00000004/sig00001aaa ), + .O(\blk00000003/blk00000004/sig0000070c ) + ); + LUT4 #( + .INIT ( 16'h1441 )) + \blk00000003/blk00000004/blk00001f6e ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig0000050d ), + .I2(\blk00000003/blk00000004/sig00000513 ), + .I3(\blk00000003/blk00000004/sig00001aa8 ), + .O(\blk00000003/blk00000004/sig0000070a ) + ); + LUT4 #( + .INIT ( 16'h1441 )) + \blk00000003/blk00000004/blk00001f6d ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00000501 ), + .I2(\blk00000003/blk00000004/sig00000507 ), + .I3(\blk00000003/blk00000004/sig00001aa6 ), + .O(\blk00000003/blk00000004/sig00000708 ) + ); + LUT4 #( + .INIT ( 16'h1441 )) + \blk00000003/blk00000004/blk00001f6c ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig000004f5 ), + .I2(\blk00000003/blk00000004/sig000004fb ), + .I3(\blk00000003/blk00000004/sig00001aa4 ), + .O(\blk00000003/blk00000004/sig00000706 ) + ); + LUT4 #( + .INIT ( 16'h1441 )) + \blk00000003/blk00000004/blk00001f6b ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig000004e9 ), + .I2(\blk00000003/blk00000004/sig000004ef ), + .I3(\blk00000003/blk00000004/sig00001aa2 ), + .O(\blk00000003/blk00000004/sig00000704 ) + ); + LUT4 #( + .INIT ( 16'h1441 )) + \blk00000003/blk00000004/blk00001f6a ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig0000062d ), + .I2(\blk00000003/blk00000004/sig00000633 ), + .I3(\blk00000003/blk00000004/sig00001aa0 ), + .O(\blk00000003/blk00000004/sig0000073a ) + ); + LUT4 #( + .INIT ( 16'h1441 )) + \blk00000003/blk00000004/blk00001f69 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig000004dd ), + .I2(\blk00000003/blk00000004/sig000004e3 ), + .I3(\blk00000003/blk00000004/sig00001a9e ), + .O(\blk00000003/blk00000004/sig00000702 ) + ); + LUT4 #( + .INIT ( 16'h1441 )) + \blk00000003/blk00000004/blk00001f68 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig000004d1 ), + .I2(\blk00000003/blk00000004/sig000004d7 ), + .I3(\blk00000003/blk00000004/sig00001a9c ), + .O(\blk00000003/blk00000004/sig00000700 ) + ); + LUT4 #( + .INIT ( 16'h1441 )) + \blk00000003/blk00000004/blk00001f67 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00000621 ), + .I2(\blk00000003/blk00000004/sig00000627 ), + .I3(\blk00000003/blk00000004/sig00001a9a ), + .O(\blk00000003/blk00000004/sig00000738 ) + ); + LUT4 #( + .INIT ( 16'h1441 )) + \blk00000003/blk00000004/blk00001f66 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00000615 ), + .I2(\blk00000003/blk00000004/sig0000061b ), + .I3(\blk00000003/blk00000004/sig00001a98 ), + .O(\blk00000003/blk00000004/sig00000736 ) + ); + LUT4 #( + .INIT ( 16'h1441 )) + \blk00000003/blk00000004/blk00001f65 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00000609 ), + .I2(\blk00000003/blk00000004/sig0000060f ), + .I3(\blk00000003/blk00000004/sig00001a96 ), + .O(\blk00000003/blk00000004/sig00000734 ) + ); + LUT4 #( + .INIT ( 16'h1441 )) + \blk00000003/blk00000004/blk00001f64 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig000005fd ), + .I2(\blk00000003/blk00000004/sig00000603 ), + .I3(\blk00000003/blk00000004/sig00001a94 ), + .O(\blk00000003/blk00000004/sig00000732 ) + ); + LUT4 #( + .INIT ( 16'h1441 )) + \blk00000003/blk00000004/blk00001f63 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig000005f1 ), + .I2(\blk00000003/blk00000004/sig000005f7 ), + .I3(\blk00000003/blk00000004/sig00001a92 ), + .O(\blk00000003/blk00000004/sig00000730 ) + ); + LUT4 #( + .INIT ( 16'h1441 )) + \blk00000003/blk00000004/blk00001f62 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig000005e5 ), + .I2(\blk00000003/blk00000004/sig000005eb ), + .I3(\blk00000003/blk00000004/sig00001a90 ), + .O(\blk00000003/blk00000004/sig0000072e ) + ); + LUT4 #( + .INIT ( 16'h1441 )) + \blk00000003/blk00000004/blk00001f61 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig000005d9 ), + .I2(\blk00000003/blk00000004/sig000005df ), + .I3(\blk00000003/blk00000004/sig00001a8e ), + .O(\blk00000003/blk00000004/sig0000072c ) + ); + LUT4 #( + .INIT ( 16'h1441 )) + \blk00000003/blk00000004/blk00001f60 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig000004c5 ), + .I2(\blk00000003/blk00000004/sig000004cb ), + .I3(\blk00000003/blk00000004/sig00001a8c ), + .O(\blk00000003/blk00000004/sig000006fe ) + ); + LUT4 #( + .INIT ( 16'h1441 )) + \blk00000003/blk00000004/blk00001f5f ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig0000044d ), + .I2(\blk00000003/blk00000004/sig00000453 ), + .I3(\blk00000003/blk00000004/sig00001a8a ), + .O(\blk00000003/blk00000004/sig000006d6 ) + ); + LUT4 #( + .INIT ( 16'h1441 )) + \blk00000003/blk00000004/blk00001f5e ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00000441 ), + .I2(\blk00000003/blk00000004/sig00000447 ), + .I3(\blk00000003/blk00000004/sig00001a88 ), + .O(\blk00000003/blk00000004/sig000006d2 ) + ); + LUT4 #( + .INIT ( 16'h1441 )) + \blk00000003/blk00000004/blk00001f5d ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00000435 ), + .I2(\blk00000003/blk00000004/sig0000043b ), + .I3(\blk00000003/blk00000004/sig00001a86 ), + .O(\blk00000003/blk00000004/sig000006ce ) + ); + LUT4 #( + .INIT ( 16'h1441 )) + \blk00000003/blk00000004/blk00001f5c ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00000429 ), + .I2(\blk00000003/blk00000004/sig0000042f ), + .I3(\blk00000003/blk00000004/sig00001a84 ), + .O(\blk00000003/blk00000004/sig000006ca ) + ); + LUT4 #( + .INIT ( 16'h1441 )) + \blk00000003/blk00000004/blk00001f5b ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig0000041d ), + .I2(\blk00000003/blk00000004/sig00000423 ), + .I3(\blk00000003/blk00000004/sig00001a82 ), + .O(\blk00000003/blk00000004/sig000006c6 ) + ); + LUT4 #( + .INIT ( 16'h1441 )) + \blk00000003/blk00000004/blk00001f5a ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00000411 ), + .I2(\blk00000003/blk00000004/sig00000417 ), + .I3(\blk00000003/blk00000004/sig00001a80 ), + .O(\blk00000003/blk00000004/sig000006c2 ) + ); + LUT4 #( + .INIT ( 16'h1441 )) + \blk00000003/blk00000004/blk00001f59 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig000004b9 ), + .I2(\blk00000003/blk00000004/sig000004bf ), + .I3(\blk00000003/blk00000004/sig00001a7e ), + .O(\blk00000003/blk00000004/sig000006fa ) + ); + LUT4 #( + .INIT ( 16'h1441 )) + \blk00000003/blk00000004/blk00001f58 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig000004ad ), + .I2(\blk00000003/blk00000004/sig000004b3 ), + .I3(\blk00000003/blk00000004/sig00001a7c ), + .O(\blk00000003/blk00000004/sig000006f6 ) + ); + LUT4 #( + .INIT ( 16'h1441 )) + \blk00000003/blk00000004/blk00001f57 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig000004a1 ), + .I2(\blk00000003/blk00000004/sig000004a7 ), + .I3(\blk00000003/blk00000004/sig00001a7a ), + .O(\blk00000003/blk00000004/sig000006f2 ) + ); + LUT4 #( + .INIT ( 16'h1441 )) + \blk00000003/blk00000004/blk00001f56 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00000495 ), + .I2(\blk00000003/blk00000004/sig0000049b ), + .I3(\blk00000003/blk00000004/sig00001a78 ), + .O(\blk00000003/blk00000004/sig000006ee ) + ); + LUT4 #( + .INIT ( 16'h1441 )) + \blk00000003/blk00000004/blk00001f55 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00000489 ), + .I2(\blk00000003/blk00000004/sig0000048f ), + .I3(\blk00000003/blk00000004/sig00001a76 ), + .O(\blk00000003/blk00000004/sig000006ea ) + ); + LUT4 #( + .INIT ( 16'h1441 )) + \blk00000003/blk00000004/blk00001f54 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig0000047d ), + .I2(\blk00000003/blk00000004/sig00000483 ), + .I3(\blk00000003/blk00000004/sig00001a74 ), + .O(\blk00000003/blk00000004/sig000006e6 ) + ); + LUT4 #( + .INIT ( 16'h1441 )) + \blk00000003/blk00000004/blk00001f53 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00000471 ), + .I2(\blk00000003/blk00000004/sig00000477 ), + .I3(\blk00000003/blk00000004/sig00001a72 ), + .O(\blk00000003/blk00000004/sig000006e2 ) + ); + LUT4 #( + .INIT ( 16'h1441 )) + \blk00000003/blk00000004/blk00001f52 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00000465 ), + .I2(\blk00000003/blk00000004/sig0000046b ), + .I3(\blk00000003/blk00000004/sig00001a70 ), + .O(\blk00000003/blk00000004/sig000006de ) + ); + LUT4 #( + .INIT ( 16'h1441 )) + \blk00000003/blk00000004/blk00001f51 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00000459 ), + .I2(\blk00000003/blk00000004/sig0000045f ), + .I3(\blk00000003/blk00000004/sig00001a6e ), + .O(\blk00000003/blk00000004/sig000006da ) + ); + LUT4 #( + .INIT ( 16'h1441 )) + \blk00000003/blk00000004/blk00001f50 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00000405 ), + .I2(\blk00000003/blk00000004/sig0000040b ), + .I3(\blk00000003/blk00000004/sig00001a6c ), + .O(\blk00000003/blk00000004/sig000006be ) + ); + LUT4 #( + .INIT ( 16'h1441 )) + \blk00000003/blk00000004/blk00001f4f ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig000003f9 ), + .I2(\blk00000003/blk00000004/sig000003ff ), + .I3(\blk00000003/blk00000004/sig00001a6a ), + .O(\blk00000003/blk00000004/sig000006b8 ) + ); + LUT4 #( + .INIT ( 16'h1441 )) + \blk00000003/blk00000004/blk00001f4e ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig000003ed ), + .I2(\blk00000003/blk00000004/sig000003f3 ), + .I3(\blk00000003/blk00000004/sig00001a68 ), + .O(\blk00000003/blk00000004/sig000006b2 ) + ); + LUT4 #( + .INIT ( 16'h1441 )) + \blk00000003/blk00000004/blk00001f4d ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig000003e1 ), + .I2(\blk00000003/blk00000004/sig000003e7 ), + .I3(\blk00000003/blk00000004/sig00001a66 ), + .O(\blk00000003/blk00000004/sig000006ac ) + ); + LUT4 #( + .INIT ( 16'h1441 )) + \blk00000003/blk00000004/blk00001f4c ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig000003d5 ), + .I2(\blk00000003/blk00000004/sig000003db ), + .I3(\blk00000003/blk00000004/sig00001a64 ), + .O(\blk00000003/blk00000004/sig000006a6 ) + ); + LUT4 #( + .INIT ( 16'h1441 )) + \blk00000003/blk00000004/blk00001f4b ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig000003c9 ), + .I2(\blk00000003/blk00000004/sig000003cf ), + .I3(\blk00000003/blk00000004/sig00001a62 ), + .O(\blk00000003/blk00000004/sig000006a0 ) + ); + LUT4 #( + .INIT ( 16'h1441 )) + \blk00000003/blk00000004/blk00001f4a ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig000003bd ), + .I2(\blk00000003/blk00000004/sig000003c3 ), + .I3(\blk00000003/blk00000004/sig00001a60 ), + .O(\blk00000003/blk00000004/sig0000069a ) + ); + LUT4 #( + .INIT ( 16'h1441 )) + \blk00000003/blk00000004/blk00001f49 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig000003b1 ), + .I2(\blk00000003/blk00000004/sig000003b7 ), + .I3(\blk00000003/blk00000004/sig00001a5e ), + .O(\blk00000003/blk00000004/sig00000694 ) + ); + LUT4 #( + .INIT ( 16'h1441 )) + \blk00000003/blk00000004/blk00001f48 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig000003a5 ), + .I2(\blk00000003/blk00000004/sig000003ab ), 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.I1(\blk00000003/blk00000004/sig00001c75 ), + .I2(\blk00000003/blk00000004/sig0000214e ), + .O(\blk00000003/blk00000004/sig00002158 ) + ); + LUT3 #( + .INIT ( 8'hAC )) + \blk00000003/blk00000004/blk00001ea8 ( + .I0(\blk00000003/blk00000004/sig00001c39 ), + .I1(\blk00000003/blk00000004/sig00001c3c ), + .I2(\blk00000003/blk00000004/sig0000214e ), + .O(\blk00000003/blk00000004/sig00002157 ) + ); + LUT3 #( + .INIT ( 8'hAC )) + \blk00000003/blk00000004/blk00001ea7 ( + .I0(\blk00000003/blk00000004/sig00001c78 ), + .I1(\blk00000003/blk00000004/sig00001c7b ), + .I2(\blk00000003/blk00000004/sig0000214e ), + .O(\blk00000003/blk00000004/sig00002156 ) + ); + LUT3 #( + .INIT ( 8'hAC )) + \blk00000003/blk00000004/blk00001ea6 ( + .I0(\blk00000003/blk00000004/sig00001c33 ), + .I1(\blk00000003/blk00000004/sig00001c36 ), + .I2(\blk00000003/blk00000004/sig0000214e ), + .O(\blk00000003/blk00000004/sig00002155 ) + ); + LUT3 #( + .INIT ( 8'hAC )) + \blk00000003/blk00000004/blk00001ea5 ( + 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.O(\blk00000003/blk00000004/sig00002148 ) + ); + LUT3 #( + .INIT ( 8'hAC )) + \blk00000003/blk00000004/blk00001e99 ( + .I0(\blk00000003/blk00000004/sig00001cd2 ), + .I1(\blk00000003/blk00000004/sig00001cd5 ), + .I2(\blk00000003/blk00000004/sig00002134 ), + .O(\blk00000003/blk00000004/sig00002147 ) + ); + LUT3 #( + .INIT ( 8'hAC )) + \blk00000003/blk00000004/blk00001e98 ( + .I0(\blk00000003/blk00000004/sig00001c99 ), + .I1(\blk00000003/blk00000004/sig00001c9c ), + .I2(\blk00000003/blk00000004/sig00002134 ), + .O(\blk00000003/blk00000004/sig00002146 ) + ); + LUT3 #( + .INIT ( 8'hAC )) + \blk00000003/blk00000004/blk00001e97 ( + .I0(\blk00000003/blk00000004/sig00001cd8 ), + .I1(\blk00000003/blk00000004/sig00001cdb ), + .I2(\blk00000003/blk00000004/sig00002134 ), + .O(\blk00000003/blk00000004/sig00002145 ) + ); + LUT3 #( + .INIT ( 8'hAC )) + \blk00000003/blk00000004/blk00001e96 ( + .I0(\blk00000003/blk00000004/sig00001c9f ), + .I1(\blk00000003/blk00000004/sig00001cb4 ), + .I2(\blk00000003/blk00000004/sig00002134 ), + .O(\blk00000003/blk00000004/sig00002144 ) + ); + LUT3 #( + .INIT ( 8'hAC )) + \blk00000003/blk00000004/blk00001e95 ( + .I0(\blk00000003/blk00000004/sig00001c87 ), + .I1(\blk00000003/blk00000004/sig00001c8a ), + .I2(\blk00000003/blk00000004/sig00002134 ), + .O(\blk00000003/blk00000004/sig00002143 ) + ); + LUT3 #( + .INIT ( 8'hAC )) + \blk00000003/blk00000004/blk00001e94 ( + .I0(\blk00000003/blk00000004/sig00001c93 ), + .I1(\blk00000003/blk00000004/sig00001c96 ), + .I2(\blk00000003/blk00000004/sig00002134 ), + .O(\blk00000003/blk00000004/sig00002142 ) + ); + LUT3 #( + .INIT ( 8'hAC )) + \blk00000003/blk00000004/blk00001e93 ( + .I0(\blk00000003/blk00000004/sig00001ca8 ), + .I1(\blk00000003/blk00000004/sig00001cab ), + .I2(\blk00000003/blk00000004/sig00002134 ), + .O(\blk00000003/blk00000004/sig00002141 ) + ); + LUT3 #( + .INIT ( 8'hAC )) + \blk00000003/blk00000004/blk00001e92 ( + .I0(\blk00000003/blk00000004/sig00001ca2 ), + .I1(\blk00000003/blk00000004/sig00001ca5 ), + .I2(\blk00000003/blk00000004/sig00002134 ), + .O(\blk00000003/blk00000004/sig00002140 ) + ); + LUT3 #( + .INIT ( 8'hAC )) + \blk00000003/blk00000004/blk00001e91 ( + .I0(\blk00000003/blk00000004/sig00001c8d ), + .I1(\blk00000003/blk00000004/sig00001c90 ), + .I2(\blk00000003/blk00000004/sig00002134 ), + .O(\blk00000003/blk00000004/sig0000213f ) + ); + LUT3 #( + .INIT ( 8'hE4 )) + \blk00000003/blk00000004/blk00001e90 ( + .I0(\blk00000003/blk00000004/sig00000186 ), + .I1(\blk00000003/blk00000004/sig0000212f ), + .I2(\blk00000003/blk00000004/sig00002131 ), + .O(\blk00000003/blk00000004/sig0000213e ) + ); + LUT3 #( + .INIT ( 8'hAC )) + \blk00000003/blk00000004/blk00001e8f ( + .I0(\blk00000003/blk00000004/sig00001cae ), + .I1(\blk00000003/blk00000004/sig00001cb1 ), + .I2(\blk00000003/blk00000004/sig00002134 ), + .O(\blk00000003/blk00000004/sig0000213d ) + ); + LUT4 #( + .INIT ( 16'h5044 )) + \blk00000003/blk00000004/blk00001e8e ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig0000028d ), + .I2(\blk00000003/blk00000004/sig00000294 ), + .I3(\blk00000003/blk00000004/sig0000029b ), + .O(\blk00000003/blk00000004/sig000002ad ) + ); + LUT4 #( + .INIT ( 16'h8A80 )) + \blk00000003/blk00000004/blk00001e8d ( + .I0(\blk00000003/blk00000004/sig00001ae8 ), + .I1(\blk00000003/blk00000004/sig00000651 ), + .I2(\blk00000003/blk00000004/sig000002a5 ), + .I3(\blk00000003/blk00000004/sig00002129 ), + .O(\blk00000003/blk00000004/sig0000212c ) + ); + LUT3 #( + .INIT ( 8'h07 )) + \blk00000003/blk00000004/blk00001e8c ( + .I0(\blk00000003/blk00000004/sig000019d3 ), + .I1(\blk00000003/blk00000004/sig000019bf ), + .I2(\blk00000003/blk00000004/sig000019bd ), + .O(\blk00000003/blk00000004/sig00002128 ) + ); + LUT3 #( + .INIT ( 8'h07 )) + \blk00000003/blk00000004/blk00001e8b ( + .I0(\blk00000003/blk00000004/sig000019d3 ), + .I1(\blk00000003/blk00000004/sig000019bf ), + .I2(\blk00000003/blk00000004/sig000019d1 ), + .O(\blk00000003/blk00000004/sig00002127 ) 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.I2(\blk00000003/blk00000004/sig00000959 ), + .O(\blk00000003/blk00000004/sig00001ead ) + ); + LUT3 #( + .INIT ( 8'h15 )) + \blk00000003/blk00000004/blk00001ba2 ( + .I0(\blk00000003/blk00000004/sig000008ea ), + .I1(\blk00000003/blk00000004/sig000008fb ), + .I2(\blk00000003/blk00000004/sig0000090f ), + .O(\blk00000003/blk00000004/sig00001ea2 ) + ); + LUT3 #( + .INIT ( 8'h15 )) + \blk00000003/blk00000004/blk00001ba1 ( + .I0(\blk00000003/blk00000004/sig000008fe ), + .I1(\blk00000003/blk00000004/sig000008fb ), + .I2(\blk00000003/blk00000004/sig0000090f ), + .O(\blk00000003/blk00000004/sig00001ea1 ) + ); + LUT3 #( + .INIT ( 8'h15 )) + \blk00000003/blk00000004/blk00001ba0 ( + .I0(\blk00000003/blk00000004/sig000008a0 ), + .I1(\blk00000003/blk00000004/sig000008b1 ), + .I2(\blk00000003/blk00000004/sig000008c5 ), + .O(\blk00000003/blk00000004/sig00001e96 ) + ); + LUT3 #( + .INIT ( 8'h15 )) + \blk00000003/blk00000004/blk00001b9f ( + .I0(\blk00000003/blk00000004/sig000008b4 ), + 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.I0(\blk00000003/blk00000004/sig0000088d ), + .O(\blk00000003/blk00000004/sig00000952 ) + ); + LUT1 #( + .INIT ( 2'h2 )) + \blk00000003/blk00000004/blk00001b0d ( + .I0(\blk00000003/blk00000004/sig000011cd ), + .O(\blk00000003/blk00000004/sig0000093e ) + ); + LUT1 #( + .INIT ( 2'h2 )) + \blk00000003/blk00000004/blk00001b0c ( + .I0(\blk00000003/blk00000004/sig0000083f ), + .O(\blk00000003/blk00000004/sig00000908 ) + ); + LUT1 #( + .INIT ( 2'h2 )) + \blk00000003/blk00000004/blk00001b0b ( + .I0(\blk00000003/blk00000004/sig00001183 ), + .O(\blk00000003/blk00000004/sig000008f4 ) + ); + LUT1 #( + .INIT ( 2'h2 )) + \blk00000003/blk00000004/blk00001b0a ( + .I0(\blk00000003/blk00000004/sig0000083f ), + .O(\blk00000003/blk00000004/sig000008be ) + ); + LUT1 #( + .INIT ( 2'h2 )) + \blk00000003/blk00000004/blk00001b09 ( + .I0(\blk00000003/blk00000004/sig00001183 ), + .O(\blk00000003/blk00000004/sig000008aa ) + ); + LUT1 #( + .INIT ( 2'h2 )) + \blk00000003/blk00000004/blk00001b08 ( + .I0(\blk00000003/blk00000004/sig000007e1 ), + .O(\blk00000003/blk00000004/sig00000874 ) + ); + LUT1 #( + .INIT ( 2'h2 )) + \blk00000003/blk00000004/blk00001b07 ( + .I0(\blk00000003/blk00000004/sig00001139 ), + .O(\blk00000003/blk00000004/sig0000085c ) + ); + LUT1 #( + .INIT ( 2'h2 )) + \blk00000003/blk00000004/blk00001b06 ( + .I0(\blk00000003/blk00000004/sig000007e1 ), + .O(\blk00000003/blk00000004/sig0000081a ) + ); + LUT1 #( + .INIT ( 2'h2 )) + \blk00000003/blk00000004/blk00001b05 ( + .I0(\blk00000003/blk00000004/sig00001139 ), + .O(\blk00000003/blk00000004/sig00000802 ) + ); + LUT1 #( + .INIT ( 2'h2 )) + \blk00000003/blk00000004/blk00001b04 ( + .I0(\blk00000003/blk00000004/sig00000793 ), + .O(\blk00000003/blk00000004/sig000007c8 ) + ); + LUT1 #( + .INIT ( 2'h2 )) + \blk00000003/blk00000004/blk00001b03 ( + .I0(\blk00000003/blk00000004/sig000010ef ), + .O(\blk00000003/blk00000004/sig000007b0 ) + ); + LUT1 #( + .INIT ( 2'h2 )) + \blk00000003/blk00000004/blk00001b02 ( + .I0(\blk00000003/blk00000004/sig00000793 ), + .O(\blk00000003/blk00000004/sig0000076e ) + ); + LUT1 #( + .INIT ( 2'h2 )) + \blk00000003/blk00000004/blk00001b01 ( + .I0(\blk00000003/blk00000004/sig000010ef ), + .O(\blk00000003/blk00000004/sig00000756 ) + ); + LUT1 #( + .INIT ( 2'h2 )) + \blk00000003/blk00000004/blk00001b00 ( + .I0(\blk00000003/blk00000004/sig000002df ), + .O(\blk00000003/blk00000004/sig000002e6 ) + ); + LUT1 #( + .INIT ( 2'h2 )) + \blk00000003/blk00000004/blk00001aff ( + .I0(\blk00000003/blk00000004/sig000002dd ), + .O(\blk00000003/blk00000004/sig000002e3 ) + ); + LUT1 #( + .INIT ( 2'h2 )) + \blk00000003/blk00000004/blk00001afe ( + .I0(\blk00000003/blk00000004/sig000002cf ), + .O(\blk00000003/blk00000004/sig000002d6 ) + ); + LUT1 #( + .INIT ( 2'h2 )) + \blk00000003/blk00000004/blk00001afd ( + .I0(\blk00000003/blk00000004/sig000002cd ), + .O(\blk00000003/blk00000004/sig000002d3 ) + ); + LUT1 #( + .INIT ( 2'h2 )) + \blk00000003/blk00000004/blk00001afc ( + .I0(\blk00000003/blk00000004/sig000002bb ), + .O(\blk00000003/blk00000004/sig000002c6 ) + ); + LUT1 #( + .INIT ( 2'h2 )) + \blk00000003/blk00000004/blk00001afb ( + .I0(\blk00000003/blk00000004/sig000002b9 ), + .O(\blk00000003/blk00000004/sig000002c4 ) + ); + LUT1 #( + .INIT ( 2'h2 )) + \blk00000003/blk00000004/blk00001afa ( + .I0(\blk00000003/blk00000004/sig000002b7 ), + .O(\blk00000003/blk00000004/sig000002c2 ) + ); + LUT1 #( + .INIT ( 2'h2 )) + \blk00000003/blk00000004/blk00001af9 ( + .I0(\blk00000003/blk00000004/sig000002b5 ), + .O(\blk00000003/blk00000004/sig000002bf ) + ); + LUT1 #( + .INIT ( 2'h2 )) + \blk00000003/blk00000004/blk00001af8 ( + .I0(\blk00000003/blk00000004/sig000000b5 ), + .O(\blk00000003/blk00000004/sig000000c2 ) + ); + LUT1 #( + .INIT ( 2'h2 )) + \blk00000003/blk00000004/blk00001af7 ( + .I0(\blk00000003/blk00000004/sig000000b3 ), + .O(\blk00000003/blk00000004/sig000000c0 ) + ); + LUT1 #( + .INIT ( 2'h2 )) + \blk00000003/blk00000004/blk00001af6 ( + .I0(\blk00000003/blk00000004/sig000000b1 ), + .O(\blk00000003/blk00000004/sig000000be ) + ); + LUT1 #( + .INIT ( 2'h2 )) + \blk00000003/blk00000004/blk00001af5 ( + .I0(\blk00000003/blk00000004/sig000000af ), + .O(\blk00000003/blk00000004/sig000000bc ) + ); + LUT1 #( + .INIT ( 2'h2 )) + \blk00000003/blk00000004/blk00001af4 ( + .I0(\blk00000003/blk00000004/sig000000ad ), + .O(\blk00000003/blk00000004/sig000000b9 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk00001af3 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig0000213c ), + .Q(\blk00000003/blk00000004/sig00001a46 ) + ); + LUT2 #( + .INIT ( 4'h1 )) + \blk00000003/blk00000004/blk00001af2 ( + .I0(\blk00000003/blk00000004/sig000002e1 ), + .I1(\blk00000003/blk00000004/sig00001a47 ), + .O(\blk00000003/blk00000004/sig0000213b ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk00001af1 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig0000213b ), + .Q(\blk00000003/blk00000004/sig00001a42 ) + ); + LUT2 #( + .INIT ( 4'h1 )) + \blk00000003/blk00000004/blk00001af0 ( + .I0(\blk00000003/blk00000004/sig000002d1 ), + .I1(\blk00000003/blk00000004/sig00001a48 ), + .O(\blk00000003/blk00000004/sig0000213a ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk00001aef ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig0000213a ), + .Q(\blk00000003/blk00000004/sig00001a45 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk00001aee ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig00002139 ), + .Q(\blk00000003/blk00000004/sig0000028c ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk00001aed ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig00002137 ), + .Q(\blk00000003/blk00000004/sig00002138 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk00001aec ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig00002135 ), + .Q(\blk00000003/blk00000004/sig00002136 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk00001aeb ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig00002133 ), + .Q(\blk00000003/blk00000004/sig00002134 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk00001aea ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig00002132 ), + .Q(\blk00000003/blk00000004/sig0000019b ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk00001ae9 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig00002130 ), + .Q(\blk00000003/blk00000004/sig00002131 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk00001ae8 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig0000212e ), + .Q(\blk00000003/blk00000004/sig0000212f ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk00000004/blk00001ae7 ( + .I0(\blk00000003/blk00000004/sig00001a4a ), + .I1(\blk00000003/blk00000004/sig00001a4b ), + .O(\blk00000003/blk00000004/sig0000212d ) + ); + FDS #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk00001ae6 ( + .C(clk), + .D(\blk00000003/blk00000004/sig0000212d ), + .S(\blk00000003/blk00000004/sig00001a49 ), + .Q(\blk00000003/blk00000004/sig00001a43 ) + ); + FDS #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk00001ae5 ( + .C(clk), + .D(\blk00000003/blk00000004/sig00001d18 ), + .S(\blk00000003/blk00000004/sig00001d15 ), + .Q(\blk00000003/blk00000004/sig00001d14 ) + ); + FDS #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk00001ae4 ( + .C(clk), + .D(\blk00000003/blk00000004/sig00001d1d ), + .S(\blk00000003/blk00000004/sig00001d1a ), + .Q(\blk00000003/blk00000004/sig00001d19 ) + ); + FDS #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk00001ae3 ( + .C(clk), + .D(\blk00000003/blk00000004/sig00001d22 ), + .S(\blk00000003/blk00000004/sig00001d1f ), + .Q(\blk00000003/blk00000004/sig00001d1e ) + ); + FDS #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk00001ae2 ( + .C(clk), + .D(\blk00000003/blk00000004/sig00001d27 ), + .S(\blk00000003/blk00000004/sig00001d24 ), + .Q(\blk00000003/blk00000004/sig00001d23 ) + ); + FDS #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk00001ae1 ( + .C(clk), + .D(\blk00000003/blk00000004/sig00001d2c ), + .S(\blk00000003/blk00000004/sig00001d29 ), + .Q(\blk00000003/blk00000004/sig00001d28 ) + ); + FDS #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk00001ae0 ( + .C(clk), + .D(\blk00000003/blk00000004/sig00001d31 ), + .S(\blk00000003/blk00000004/sig00001d2e ), + .Q(\blk00000003/blk00000004/sig00001d2d ) + ); + FDS #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk00001adf ( + .C(clk), + .D(\blk00000003/blk00000004/sig00001ceb ), + .S(\blk00000003/blk00000004/sig00001ce8 ), + .Q(\blk00000003/blk00000004/sig00001ce7 ) + ); + FDS #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk00001ade ( + .C(clk), + .D(\blk00000003/blk00000004/sig00001cf0 ), + .S(\blk00000003/blk00000004/sig00001ced ), + .Q(\blk00000003/blk00000004/sig00001cec ) + ); + FDS #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk00001add ( + .C(clk), + .D(\blk00000003/blk00000004/sig00001cf5 ), + .S(\blk00000003/blk00000004/sig00001cf2 ), + .Q(\blk00000003/blk00000004/sig00001cf1 ) + ); + FDS #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk00001adc ( + .C(clk), + .D(\blk00000003/blk00000004/sig00001cfa ), + .S(\blk00000003/blk00000004/sig00001cf7 ), + .Q(\blk00000003/blk00000004/sig00001cf6 ) + ); + FDS #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk00001adb ( + .C(clk), + .D(\blk00000003/blk00000004/sig00001cff ), + .S(\blk00000003/blk00000004/sig00001cfc ), + .Q(\blk00000003/blk00000004/sig00001cfb ) + ); + FDS #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk00001ada ( + .C(clk), + .D(\blk00000003/blk00000004/sig00001d04 ), + .S(\blk00000003/blk00000004/sig00001d01 ), + .Q(\blk00000003/blk00000004/sig00001d00 ) + ); + FDS #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk00001ad9 ( + .C(clk), + .D(\blk00000003/blk00000004/sig00001d09 ), + .S(\blk00000003/blk00000004/sig00001d06 ), + .Q(\blk00000003/blk00000004/sig00001d05 ) + ); + FDS #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk00001ad8 ( + .C(clk), + .D(\blk00000003/blk00000004/sig00001d0e ), + .S(\blk00000003/blk00000004/sig00001d0b ), + .Q(\blk00000003/blk00000004/sig00001d0a ) + ); + FDS #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk00001ad7 ( + .C(clk), + .D(\blk00000003/blk00000004/sig00001d13 ), + .S(\blk00000003/blk00000004/sig00001d10 ), + .Q(\blk00000003/blk00000004/sig00001d0f ) + ); + FDS #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk00001ad6 ( + .C(clk), + .D(\blk00000003/blk00000004/sig00001d36 ), + .S(\blk00000003/blk00000004/sig00001d33 ), + .Q(\blk00000003/blk00000004/sig00001d32 ) + ); + FDS #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk00001ad5 ( + .C(clk), + .D(\blk00000003/blk00000004/sig00001d68 ), + .S(\blk00000003/blk00000004/sig00001d65 ), + .Q(\blk00000003/blk00000004/sig00001d64 ) + ); + FDS #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk00001ad4 ( + .C(clk), + .D(\blk00000003/blk00000004/sig00001d6d ), + .S(\blk00000003/blk00000004/sig00001d6a ), + .Q(\blk00000003/blk00000004/sig00001d69 ) + ); + FDS #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk00001ad3 ( + .C(clk), + .D(\blk00000003/blk00000004/sig00001d72 ), + .S(\blk00000003/blk00000004/sig00001d6f ), + .Q(\blk00000003/blk00000004/sig00001d6e ) + ); + FDS #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk00001ad2 ( + .C(clk), + .D(\blk00000003/blk00000004/sig00001d77 ), + .S(\blk00000003/blk00000004/sig00001d74 ), + .Q(\blk00000003/blk00000004/sig00001d73 ) + ); + FDS #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk00001ad1 ( + .C(clk), + .D(\blk00000003/blk00000004/sig00001d7c ), + .S(\blk00000003/blk00000004/sig00001d79 ), + .Q(\blk00000003/blk00000004/sig00001d78 ) + ); + FDS #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk00001ad0 ( + .C(clk), + .D(\blk00000003/blk00000004/sig00001d81 ), + .S(\blk00000003/blk00000004/sig00001d7e ), + .Q(\blk00000003/blk00000004/sig00001d7d ) + ); + FDS #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk00001acf ( + .C(clk), + .D(\blk00000003/blk00000004/sig00001d3b ), + .S(\blk00000003/blk00000004/sig00001d38 ), + .Q(\blk00000003/blk00000004/sig00001d37 ) + ); + FDS #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk00001ace ( + .C(clk), + .D(\blk00000003/blk00000004/sig00001d40 ), + .S(\blk00000003/blk00000004/sig00001d3d ), + .Q(\blk00000003/blk00000004/sig00001d3c ) + ); + FDS #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk00001acd ( + .C(clk), + .D(\blk00000003/blk00000004/sig00001d45 ), + .S(\blk00000003/blk00000004/sig00001d42 ), + .Q(\blk00000003/blk00000004/sig00001d41 ) + ); + FDS #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk00001acc ( + .C(clk), + .D(\blk00000003/blk00000004/sig00001d4a ), + .S(\blk00000003/blk00000004/sig00001d47 ), + .Q(\blk00000003/blk00000004/sig00001d46 ) + ); + FDS #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk00001acb ( + .C(clk), + .D(\blk00000003/blk00000004/sig00001d4f ), + .S(\blk00000003/blk00000004/sig00001d4c ), + .Q(\blk00000003/blk00000004/sig00001d4b ) + ); + FDS #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk00001aca ( + .C(clk), + .D(\blk00000003/blk00000004/sig00001d54 ), + .S(\blk00000003/blk00000004/sig00001d51 ), + .Q(\blk00000003/blk00000004/sig00001d50 ) + ); + FDS #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk00001ac9 ( + .C(clk), + .D(\blk00000003/blk00000004/sig00001d59 ), + .S(\blk00000003/blk00000004/sig00001d56 ), + .Q(\blk00000003/blk00000004/sig00001d55 ) + ); + FDS #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk00001ac8 ( + .C(clk), + .D(\blk00000003/blk00000004/sig00001d5e ), + .S(\blk00000003/blk00000004/sig00001d5b ), + .Q(\blk00000003/blk00000004/sig00001d5a ) + ); + FDS #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk00001ac7 ( + .C(clk), + .D(\blk00000003/blk00000004/sig00001d63 ), + .S(\blk00000003/blk00000004/sig00001d60 ), + .Q(\blk00000003/blk00000004/sig00001d5f ) + ); + FDS #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk00001ac6 ( + .C(clk), + .D(\blk00000003/blk00000004/sig00001d86 ), + .S(\blk00000003/blk00000004/sig00001d83 ), + .Q(\blk00000003/blk00000004/sig00001d82 ) + ); + FDS #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk00001ac5 ( + .C(clk), + .D(\blk00000003/blk00000004/sig00001db8 ), + .S(\blk00000003/blk00000004/sig00001db5 ), + .Q(\blk00000003/blk00000004/sig00001db4 ) + ); + FDS #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk00001ac4 ( + .C(clk), + .D(\blk00000003/blk00000004/sig00001dbd ), + .S(\blk00000003/blk00000004/sig00001dba ), + .Q(\blk00000003/blk00000004/sig00001db9 ) + ); + FDS #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk00001ac3 ( + .C(clk), + .D(\blk00000003/blk00000004/sig00001dc2 ), + .S(\blk00000003/blk00000004/sig00001dbf ), + .Q(\blk00000003/blk00000004/sig00001dbe ) + ); + FDS #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk00001ac2 ( + .C(clk), + .D(\blk00000003/blk00000004/sig00001dc7 ), + .S(\blk00000003/blk00000004/sig00001dc4 ), + .Q(\blk00000003/blk00000004/sig00001dc3 ) + ); + FDS #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk00001ac1 ( + .C(clk), + .D(\blk00000003/blk00000004/sig00001dcc ), + .S(\blk00000003/blk00000004/sig00001dc9 ), + .Q(\blk00000003/blk00000004/sig00001dc8 ) + ); + FDS #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk00001ac0 ( + .C(clk), + .D(\blk00000003/blk00000004/sig00001dd1 ), + .S(\blk00000003/blk00000004/sig00001dce ), + .Q(\blk00000003/blk00000004/sig00001dcd ) + ); + FDS #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk00001abf ( + .C(clk), + .D(\blk00000003/blk00000004/sig00001d8b ), + .S(\blk00000003/blk00000004/sig00001d88 ), + .Q(\blk00000003/blk00000004/sig00001d87 ) + ); + FDS #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk00001abe ( + .C(clk), + .D(\blk00000003/blk00000004/sig00001d90 ), + .S(\blk00000003/blk00000004/sig00001d8d ), + .Q(\blk00000003/blk00000004/sig00001d8c ) + ); + FDS #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk00001abd ( + .C(clk), + .D(\blk00000003/blk00000004/sig00001d95 ), + .S(\blk00000003/blk00000004/sig00001d92 ), + .Q(\blk00000003/blk00000004/sig00001d91 ) + ); + FDS #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk00001abc ( + .C(clk), + .D(\blk00000003/blk00000004/sig00001d9a ), + .S(\blk00000003/blk00000004/sig00001d97 ), + .Q(\blk00000003/blk00000004/sig00001d96 ) + ); + FDS #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk00001abb ( + .C(clk), + .D(\blk00000003/blk00000004/sig00001d9f ), + .S(\blk00000003/blk00000004/sig00001d9c ), + .Q(\blk00000003/blk00000004/sig00001d9b ) + ); + FDS #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk00001aba ( + .C(clk), + .D(\blk00000003/blk00000004/sig00001da4 ), + .S(\blk00000003/blk00000004/sig00001da1 ), + .Q(\blk00000003/blk00000004/sig00001da0 ) + ); + FDS #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk00001ab9 ( + .C(clk), + .D(\blk00000003/blk00000004/sig00001da9 ), + .S(\blk00000003/blk00000004/sig00001da6 ), + .Q(\blk00000003/blk00000004/sig00001da5 ) + ); + FDS #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk00001ab8 ( + .C(clk), + .D(\blk00000003/blk00000004/sig00001dae ), + .S(\blk00000003/blk00000004/sig00001dab ), + .Q(\blk00000003/blk00000004/sig00001daa ) + ); + FDS #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk00001ab7 ( + .C(clk), + .D(\blk00000003/blk00000004/sig00001db3 ), + .S(\blk00000003/blk00000004/sig00001db0 ), + .Q(\blk00000003/blk00000004/sig00001daf ) + ); + FDS #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk00001ab6 ( + .C(clk), + .D(\blk00000003/blk00000004/sig00001dd6 ), + .S(\blk00000003/blk00000004/sig00001dd3 ), + .Q(\blk00000003/blk00000004/sig00001dd2 ) + ); + FDS #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk00001ab5 ( + .C(clk), + .D(\blk00000003/blk00000004/sig00001e08 ), + .S(\blk00000003/blk00000004/sig00001e05 ), + .Q(\blk00000003/blk00000004/sig00001e04 ) + ); + FDS #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk00001ab4 ( + .C(clk), + .D(\blk00000003/blk00000004/sig00001e0d ), + .S(\blk00000003/blk00000004/sig00001e0a ), + .Q(\blk00000003/blk00000004/sig00001e09 ) + ); + FDS #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk00001ab3 ( + .C(clk), + .D(\blk00000003/blk00000004/sig00001e12 ), + .S(\blk00000003/blk00000004/sig00001e0f ), + .Q(\blk00000003/blk00000004/sig00001e0e ) + ); + FDS #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk00001ab2 ( + .C(clk), + .D(\blk00000003/blk00000004/sig00001e17 ), + .S(\blk00000003/blk00000004/sig00001e14 ), + .Q(\blk00000003/blk00000004/sig00001e13 ) + ); + FDS #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk00001ab1 ( + .C(clk), + .D(\blk00000003/blk00000004/sig00001e1c ), + .S(\blk00000003/blk00000004/sig00001e19 ), + .Q(\blk00000003/blk00000004/sig00001e18 ) + ); + FDS #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk00001ab0 ( + .C(clk), + .D(\blk00000003/blk00000004/sig00001e21 ), + .S(\blk00000003/blk00000004/sig00001e1e ), + .Q(\blk00000003/blk00000004/sig00001e1d ) + ); + FDS #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk00001aaf ( + .C(clk), + .D(\blk00000003/blk00000004/sig00001ddb ), + .S(\blk00000003/blk00000004/sig00001dd8 ), + .Q(\blk00000003/blk00000004/sig00001dd7 ) + ); + FDS #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk00001aae ( + .C(clk), + .D(\blk00000003/blk00000004/sig00001de0 ), + .S(\blk00000003/blk00000004/sig00001ddd ), + .Q(\blk00000003/blk00000004/sig00001ddc ) + ); + FDS #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk00001aad ( + .C(clk), + .D(\blk00000003/blk00000004/sig00001de5 ), + .S(\blk00000003/blk00000004/sig00001de2 ), + .Q(\blk00000003/blk00000004/sig00001de1 ) + ); + FDS #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk00001aac ( + .C(clk), + .D(\blk00000003/blk00000004/sig00001dea ), + .S(\blk00000003/blk00000004/sig00001de7 ), + .Q(\blk00000003/blk00000004/sig00001de6 ) + ); + FDS #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk00001aab ( + .C(clk), + .D(\blk00000003/blk00000004/sig00001def ), + .S(\blk00000003/blk00000004/sig00001dec ), + .Q(\blk00000003/blk00000004/sig00001deb ) + ); + FDS #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk00001aaa ( + .C(clk), + .D(\blk00000003/blk00000004/sig00001df4 ), + .S(\blk00000003/blk00000004/sig00001df1 ), + .Q(\blk00000003/blk00000004/sig00001df0 ) + ); + FDS #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk00001aa9 ( + .C(clk), + .D(\blk00000003/blk00000004/sig00001df9 ), + .S(\blk00000003/blk00000004/sig00001df6 ), + .Q(\blk00000003/blk00000004/sig00001df5 ) + ); + FDS #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk00001aa8 ( + .C(clk), + .D(\blk00000003/blk00000004/sig00001dfe ), + .S(\blk00000003/blk00000004/sig00001dfb ), + .Q(\blk00000003/blk00000004/sig00001dfa ) + ); + FDS #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk00001aa7 ( + .C(clk), + .D(\blk00000003/blk00000004/sig00001e03 ), + .S(\blk00000003/blk00000004/sig00001e00 ), + .Q(\blk00000003/blk00000004/sig00001dff ) + ); + FDS #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk00001aa6 ( + .C(clk), + .D(\blk00000003/blk00000004/sig00001e26 ), + .S(\blk00000003/blk00000004/sig00001e23 ), + .Q(\blk00000003/blk00000004/sig00001e22 ) + ); + FDS #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk00001aa5 ( + .C(clk), + .D(\blk00000003/blk00000004/sig00001b18 ), + .S(\blk00000003/blk00000004/sig00001b15 ), + .Q(\blk00000003/blk00000004/sig00001b14 ) + ); + FDS #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk00001aa4 ( + .C(clk), + .D(\blk00000003/blk00000004/sig00001b1d ), + .S(\blk00000003/blk00000004/sig00001b1a ), + .Q(\blk00000003/blk00000004/sig00001b19 ) + ); + FDS #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk00001aa3 ( + .C(clk), + .D(\blk00000003/blk00000004/sig00001b22 ), + .S(\blk00000003/blk00000004/sig00001b1f ), + .Q(\blk00000003/blk00000004/sig00001b1e ) + ); + FDS #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk00001aa2 ( + .C(clk), + .D(\blk00000003/blk00000004/sig00001b27 ), + .S(\blk00000003/blk00000004/sig00001b24 ), + .Q(\blk00000003/blk00000004/sig00001b23 ) + ); + FDS #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk00001aa1 ( + .C(clk), + .D(\blk00000003/blk00000004/sig00001b2c ), + .S(\blk00000003/blk00000004/sig00001b29 ), + .Q(\blk00000003/blk00000004/sig00001b28 ) + ); + FDS #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk00001aa0 ( + .C(clk), + .D(\blk00000003/blk00000004/sig00001b31 ), + .S(\blk00000003/blk00000004/sig00001b2e ), + .Q(\blk00000003/blk00000004/sig00001b2d ) + ); + FDS #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk00001a9f ( + .C(clk), + .D(\blk00000003/blk00000004/sig00001aeb ), + .S(\blk00000003/blk00000004/sig00001ae7 ), + .Q(\blk00000003/blk00000004/sig00001ae6 ) + ); + FDS #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk00001a9e ( + .C(clk), + .D(\blk00000003/blk00000004/sig00001af0 ), + .S(\blk00000003/blk00000004/sig00001aed ), + .Q(\blk00000003/blk00000004/sig00001aec ) + ); + FDS #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk00001a9d ( + .C(clk), + .D(\blk00000003/blk00000004/sig00001af5 ), + .S(\blk00000003/blk00000004/sig00001af2 ), + .Q(\blk00000003/blk00000004/sig00001af1 ) + ); + FDS #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk00001a9c ( + .C(clk), + .D(\blk00000003/blk00000004/sig00001afa ), + .S(\blk00000003/blk00000004/sig00001af7 ), + .Q(\blk00000003/blk00000004/sig00001af6 ) + ); + FDS #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk00001a9b ( + .C(clk), + .D(\blk00000003/blk00000004/sig00001aff ), + .S(\blk00000003/blk00000004/sig00001afc ), + .Q(\blk00000003/blk00000004/sig00001afb ) + ); + FDS #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk00001a9a ( + .C(clk), + .D(\blk00000003/blk00000004/sig00001b04 ), + .S(\blk00000003/blk00000004/sig00001b01 ), + .Q(\blk00000003/blk00000004/sig00001b00 ) + ); + FDS #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk00001a99 ( + .C(clk), + .D(\blk00000003/blk00000004/sig00001b09 ), + .S(\blk00000003/blk00000004/sig00001b06 ), + .Q(\blk00000003/blk00000004/sig00001b05 ) + ); + FDS #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk00001a98 ( + .C(clk), + .D(\blk00000003/blk00000004/sig00001b0e ), + .S(\blk00000003/blk00000004/sig00001b0b ), + .Q(\blk00000003/blk00000004/sig00001b0a ) + ); + FDS #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk00001a97 ( + .C(clk), + .D(\blk00000003/blk00000004/sig00001b13 ), + .S(\blk00000003/blk00000004/sig00001b10 ), + .Q(\blk00000003/blk00000004/sig00001b0f ) + ); + FDS #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk00001a96 ( + .C(clk), + .D(\blk00000003/blk00000004/sig00001b36 ), + .S(\blk00000003/blk00000004/sig00001b33 ), + .Q(\blk00000003/blk00000004/sig00001b32 ) + ); + FDS #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk00001a95 ( + .C(clk), + .D(\blk00000003/blk00000004/sig00001b68 ), + .S(\blk00000003/blk00000004/sig00001b65 ), + .Q(\blk00000003/blk00000004/sig00001b64 ) + ); + FDS #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk00001a94 ( + .C(clk), + .D(\blk00000003/blk00000004/sig00001b6d ), + .S(\blk00000003/blk00000004/sig00001b6a ), + .Q(\blk00000003/blk00000004/sig00001b69 ) + ); + FDS #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk00001a93 ( + .C(clk), + .D(\blk00000003/blk00000004/sig00001b72 ), + .S(\blk00000003/blk00000004/sig00001b6f ), + .Q(\blk00000003/blk00000004/sig00001b6e ) + ); + FDS #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk00001a92 ( + .C(clk), + .D(\blk00000003/blk00000004/sig00001b77 ), + .S(\blk00000003/blk00000004/sig00001b74 ), + .Q(\blk00000003/blk00000004/sig00001b73 ) + ); + FDS #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk00001a91 ( + .C(clk), + .D(\blk00000003/blk00000004/sig00001b7c ), + .S(\blk00000003/blk00000004/sig00001b79 ), + .Q(\blk00000003/blk00000004/sig00001b78 ) + ); + FDS #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk00001a90 ( + .C(clk), + .D(\blk00000003/blk00000004/sig00001b81 ), + .S(\blk00000003/blk00000004/sig00001b7e ), + .Q(\blk00000003/blk00000004/sig00001b7d ) + ); + FDS #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk00001a8f ( + .C(clk), + .D(\blk00000003/blk00000004/sig00001b3b ), + .S(\blk00000003/blk00000004/sig00001b38 ), + .Q(\blk00000003/blk00000004/sig00001b37 ) + ); + FDS #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk00001a8e ( + .C(clk), + .D(\blk00000003/blk00000004/sig00001b40 ), + .S(\blk00000003/blk00000004/sig00001b3d ), + .Q(\blk00000003/blk00000004/sig00001b3c ) + ); + FDS #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk00001a8d ( + .C(clk), + .D(\blk00000003/blk00000004/sig00001b45 ), + .S(\blk00000003/blk00000004/sig00001b42 ), + .Q(\blk00000003/blk00000004/sig00001b41 ) + ); + FDS #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk00001a8c ( + .C(clk), + .D(\blk00000003/blk00000004/sig00001b4a ), + .S(\blk00000003/blk00000004/sig00001b47 ), + .Q(\blk00000003/blk00000004/sig00001b46 ) + ); + FDS #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk00001a8b ( + .C(clk), + .D(\blk00000003/blk00000004/sig00001b4f ), + .S(\blk00000003/blk00000004/sig00001b4c ), + .Q(\blk00000003/blk00000004/sig00001b4b ) + ); + FDS #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk00001a8a ( + .C(clk), + .D(\blk00000003/blk00000004/sig00001b54 ), + .S(\blk00000003/blk00000004/sig00001b51 ), + .Q(\blk00000003/blk00000004/sig00001b50 ) + ); + FDS #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk00001a89 ( + .C(clk), + .D(\blk00000003/blk00000004/sig00001b59 ), + .S(\blk00000003/blk00000004/sig00001b56 ), + .Q(\blk00000003/blk00000004/sig00001b55 ) + ); + FDS #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk00001a88 ( + .C(clk), + .D(\blk00000003/blk00000004/sig00001b5e ), + .S(\blk00000003/blk00000004/sig00001b5b ), + .Q(\blk00000003/blk00000004/sig00001b5a ) + ); + FDS #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk00001a87 ( + .C(clk), + .D(\blk00000003/blk00000004/sig00001b63 ), + .S(\blk00000003/blk00000004/sig00001b60 ), + .Q(\blk00000003/blk00000004/sig00001b5f ) + ); + FDS #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk00001a86 ( + .C(clk), + .D(\blk00000003/blk00000004/sig00001b86 ), + .S(\blk00000003/blk00000004/sig00001b83 ), + .Q(\blk00000003/blk00000004/sig00001b82 ) + ); + FDS #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk00001a85 ( + .C(clk), + .D(\blk00000003/blk00000004/sig00001bb8 ), + .S(\blk00000003/blk00000004/sig00001bb5 ), + .Q(\blk00000003/blk00000004/sig00001bb4 ) + ); + FDS #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk00001a84 ( + .C(clk), + .D(\blk00000003/blk00000004/sig00001bbd ), + .S(\blk00000003/blk00000004/sig00001bba ), + .Q(\blk00000003/blk00000004/sig00001bb9 ) + ); + FDS #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk00001a83 ( + .C(clk), + .D(\blk00000003/blk00000004/sig00001bc2 ), + .S(\blk00000003/blk00000004/sig00001bbf ), + .Q(\blk00000003/blk00000004/sig00001bbe ) + ); + FDS #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk00001a82 ( + .C(clk), + .D(\blk00000003/blk00000004/sig00001bc7 ), + .S(\blk00000003/blk00000004/sig00001bc4 ), + .Q(\blk00000003/blk00000004/sig00001bc3 ) + ); + FDS #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk00001a81 ( + .C(clk), + .D(\blk00000003/blk00000004/sig00001bcc ), + .S(\blk00000003/blk00000004/sig00001bc9 ), + .Q(\blk00000003/blk00000004/sig00001bc8 ) + ); + FDS #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk00001a80 ( + .C(clk), + .D(\blk00000003/blk00000004/sig00001bd1 ), + .S(\blk00000003/blk00000004/sig00001bce ), + .Q(\blk00000003/blk00000004/sig00001bcd ) + ); + FDS #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk00001a7f ( + .C(clk), + .D(\blk00000003/blk00000004/sig00001b8b ), + .S(\blk00000003/blk00000004/sig00001b88 ), + .Q(\blk00000003/blk00000004/sig00001b87 ) + ); + FDS #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk00001a7e ( + .C(clk), + .D(\blk00000003/blk00000004/sig00001b90 ), + .S(\blk00000003/blk00000004/sig00001b8d ), + .Q(\blk00000003/blk00000004/sig00001b8c ) + ); + FDS #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk00001a7d ( + .C(clk), + .D(\blk00000003/blk00000004/sig00001b95 ), + .S(\blk00000003/blk00000004/sig00001b92 ), + .Q(\blk00000003/blk00000004/sig00001b91 ) + ); + FDS #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk00001a7c ( + .C(clk), + .D(\blk00000003/blk00000004/sig00001b9a ), + .S(\blk00000003/blk00000004/sig00001b97 ), + .Q(\blk00000003/blk00000004/sig00001b96 ) + ); + FDS #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk00001a7b ( + .C(clk), + .D(\blk00000003/blk00000004/sig00001b9f ), + .S(\blk00000003/blk00000004/sig00001b9c ), + .Q(\blk00000003/blk00000004/sig00001b9b ) + ); + FDS #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk00001a7a ( + .C(clk), + .D(\blk00000003/blk00000004/sig00001ba4 ), + .S(\blk00000003/blk00000004/sig00001ba1 ), + .Q(\blk00000003/blk00000004/sig00001ba0 ) + ); + FDS #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk00001a79 ( + .C(clk), + .D(\blk00000003/blk00000004/sig00001ba9 ), + .S(\blk00000003/blk00000004/sig00001ba6 ), + .Q(\blk00000003/blk00000004/sig00001ba5 ) + ); + FDS #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk00001a78 ( + .C(clk), + .D(\blk00000003/blk00000004/sig00001bae ), + .S(\blk00000003/blk00000004/sig00001bab ), + .Q(\blk00000003/blk00000004/sig00001baa ) + ); + FDS #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk00001a77 ( + .C(clk), + .D(\blk00000003/blk00000004/sig00001bb3 ), + .S(\blk00000003/blk00000004/sig00001bb0 ), + .Q(\blk00000003/blk00000004/sig00001baf ) + ); + FDS #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk00001a76 ( + .C(clk), + .D(\blk00000003/blk00000004/sig00001bd6 ), + .S(\blk00000003/blk00000004/sig00001bd3 ), + .Q(\blk00000003/blk00000004/sig00001bd2 ) + ); + FDS #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk00001a75 ( + .C(clk), + .D(\blk00000003/blk00000004/sig00001c08 ), + .S(\blk00000003/blk00000004/sig00001c05 ), + .Q(\blk00000003/blk00000004/sig00001c04 ) + ); + FDS #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk00001a74 ( + .C(clk), + .D(\blk00000003/blk00000004/sig00001c0d ), + .S(\blk00000003/blk00000004/sig00001c0a ), + .Q(\blk00000003/blk00000004/sig00001c09 ) + ); + FDS #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk00001a73 ( + .C(clk), + .D(\blk00000003/blk00000004/sig00001c12 ), + .S(\blk00000003/blk00000004/sig00001c0f ), + .Q(\blk00000003/blk00000004/sig00001c0e ) + ); + FDS #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk00001a72 ( + .C(clk), + .D(\blk00000003/blk00000004/sig00001c17 ), + .S(\blk00000003/blk00000004/sig00001c14 ), + .Q(\blk00000003/blk00000004/sig00001c13 ) + ); + FDS #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk00001a71 ( + .C(clk), + .D(\blk00000003/blk00000004/sig00001c1c ), + .S(\blk00000003/blk00000004/sig00001c19 ), + .Q(\blk00000003/blk00000004/sig00001c18 ) + ); + FDS #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk00001a70 ( + .C(clk), + .D(\blk00000003/blk00000004/sig00001c21 ), + .S(\blk00000003/blk00000004/sig00001c1e ), + .Q(\blk00000003/blk00000004/sig00001c1d ) + ); + FDS #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk00001a6f ( + .C(clk), + .D(\blk00000003/blk00000004/sig00001bdb ), + .S(\blk00000003/blk00000004/sig00001bd8 ), + .Q(\blk00000003/blk00000004/sig00001bd7 ) + ); + FDS #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk00001a6e ( + .C(clk), + .D(\blk00000003/blk00000004/sig00001be0 ), + .S(\blk00000003/blk00000004/sig00001bdd ), + .Q(\blk00000003/blk00000004/sig00001bdc ) + ); + FDS #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk00001a6d ( + .C(clk), + .D(\blk00000003/blk00000004/sig00001be5 ), + .S(\blk00000003/blk00000004/sig00001be2 ), + .Q(\blk00000003/blk00000004/sig00001be1 ) + ); + FDS #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk00001a6c ( + .C(clk), + .D(\blk00000003/blk00000004/sig00001bea ), + .S(\blk00000003/blk00000004/sig00001be7 ), + .Q(\blk00000003/blk00000004/sig00001be6 ) + ); + FDS #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk00001a6b ( + .C(clk), + .D(\blk00000003/blk00000004/sig00001bef ), + .S(\blk00000003/blk00000004/sig00001bec ), + .Q(\blk00000003/blk00000004/sig00001beb ) + ); + FDS #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk00001a6a ( + .C(clk), + .D(\blk00000003/blk00000004/sig00001bf4 ), + .S(\blk00000003/blk00000004/sig00001bf1 ), + .Q(\blk00000003/blk00000004/sig00001bf0 ) + ); + FDS #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk00001a69 ( + .C(clk), + .D(\blk00000003/blk00000004/sig00001bf9 ), + .S(\blk00000003/blk00000004/sig00001bf6 ), + .Q(\blk00000003/blk00000004/sig00001bf5 ) + ); + FDS #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk00001a68 ( + .C(clk), + .D(\blk00000003/blk00000004/sig00001bfe ), + .S(\blk00000003/blk00000004/sig00001bfb ), + .Q(\blk00000003/blk00000004/sig00001bfa ) + ); + FDS #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk00001a67 ( + .C(clk), + .D(\blk00000003/blk00000004/sig00001c03 ), + .S(\blk00000003/blk00000004/sig00001c00 ), + .Q(\blk00000003/blk00000004/sig00001bff ) + ); + FDS #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk00001a66 ( + .C(clk), + .D(\blk00000003/blk00000004/sig00001c26 ), + .S(\blk00000003/blk00000004/sig00001c23 ), + .Q(\blk00000003/blk00000004/sig00001c22 ) + ); + FDS #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk00001a65 ( + .C(clk), + .D(\blk00000003/blk00000004/sig00001c44 ), + .S(\blk00000003/blk00000004/sig00001c43 ), + .Q(\blk00000003/blk00000004/sig00001c42 ) + ); + FDS #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk00001a64 ( + .C(clk), + .D(\blk00000003/blk00000004/sig00001c47 ), + .S(\blk00000003/blk00000004/sig00001c46 ), + .Q(\blk00000003/blk00000004/sig00001c45 ) + ); + FDS #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk00001a63 ( + .C(clk), + .D(\blk00000003/blk00000004/sig00001c4a ), + .S(\blk00000003/blk00000004/sig00001c49 ), + .Q(\blk00000003/blk00000004/sig00001c48 ) + ); + FDS #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk00001a62 ( + .C(clk), + .D(\blk00000003/blk00000004/sig00001c4d ), + .S(\blk00000003/blk00000004/sig00001c4c ), + .Q(\blk00000003/blk00000004/sig00001c4b ) + ); + FDS #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk00001a61 ( + .C(clk), + .D(\blk00000003/blk00000004/sig00001c50 ), + .S(\blk00000003/blk00000004/sig00001c4f ), + .Q(\blk00000003/blk00000004/sig00001c4e ) + ); + FDS #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk00001a60 ( + .C(clk), + .D(\blk00000003/blk00000004/sig00001c53 ), + .S(\blk00000003/blk00000004/sig00001c52 ), + .Q(\blk00000003/blk00000004/sig00001c51 ) + ); + FDS #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk00001a5f ( + .C(clk), + .D(\blk00000003/blk00000004/sig00001c29 ), + .S(\blk00000003/blk00000004/sig00001c28 ), + .Q(\blk00000003/blk00000004/sig00001c27 ) + ); + FDS #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk00001a5e ( + .C(clk), + .D(\blk00000003/blk00000004/sig00001c2c ), + .S(\blk00000003/blk00000004/sig00001c2b ), + .Q(\blk00000003/blk00000004/sig00001c2a ) + ); + FDS #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk00001a5d ( + .C(clk), + .D(\blk00000003/blk00000004/sig00001c2f ), + .S(\blk00000003/blk00000004/sig00001c2e ), + .Q(\blk00000003/blk00000004/sig00001c2d ) + ); + FDS #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk00001a5c ( + .C(clk), + .D(\blk00000003/blk00000004/sig00001c32 ), + .S(\blk00000003/blk00000004/sig00001c31 ), + .Q(\blk00000003/blk00000004/sig00001c30 ) + ); + FDS #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk00001a5b ( + .C(clk), + .D(\blk00000003/blk00000004/sig00001c35 ), + .S(\blk00000003/blk00000004/sig00001c34 ), + .Q(\blk00000003/blk00000004/sig00001c33 ) + ); + FDS #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk00001a5a ( + .C(clk), + .D(\blk00000003/blk00000004/sig00001c38 ), + .S(\blk00000003/blk00000004/sig00001c37 ), + .Q(\blk00000003/blk00000004/sig00001c36 ) + ); + FDS #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk00001a59 ( + .C(clk), + .D(\blk00000003/blk00000004/sig00001c3b ), + .S(\blk00000003/blk00000004/sig00001c3a ), + .Q(\blk00000003/blk00000004/sig00001c39 ) + ); + FDS #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk00001a58 ( + .C(clk), + .D(\blk00000003/blk00000004/sig00001c3e ), + .S(\blk00000003/blk00000004/sig00001c3d ), + .Q(\blk00000003/blk00000004/sig00001c3c ) + ); + FDS #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk00001a57 ( + .C(clk), + .D(\blk00000003/blk00000004/sig00001c41 ), + .S(\blk00000003/blk00000004/sig00001c40 ), + .Q(\blk00000003/blk00000004/sig00001c3f ) + ); + FDS #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk00001a56 ( + .C(clk), + .D(\blk00000003/blk00000004/sig00001c56 ), + .S(\blk00000003/blk00000004/sig00001c55 ), + .Q(\blk00000003/blk00000004/sig00001c54 ) + ); + FDS #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk00001a55 ( + .C(clk), + .D(\blk00000003/blk00000004/sig00001c74 ), + .S(\blk00000003/blk00000004/sig00001c73 ), + .Q(\blk00000003/blk00000004/sig00001c72 ) + ); + FDS #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk00001a54 ( + .C(clk), + .D(\blk00000003/blk00000004/sig00001c77 ), + .S(\blk00000003/blk00000004/sig00001c76 ), + .Q(\blk00000003/blk00000004/sig00001c75 ) + ); + FDS #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk00001a53 ( + .C(clk), + .D(\blk00000003/blk00000004/sig00001c7a ), + .S(\blk00000003/blk00000004/sig00001c79 ), + .Q(\blk00000003/blk00000004/sig00001c78 ) + ); + FDS #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk00001a52 ( + .C(clk), + .D(\blk00000003/blk00000004/sig00001c7d ), + .S(\blk00000003/blk00000004/sig00001c7c ), + .Q(\blk00000003/blk00000004/sig00001c7b ) + ); + FDS #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk00001a51 ( + .C(clk), + .D(\blk00000003/blk00000004/sig00001c80 ), + .S(\blk00000003/blk00000004/sig00001c7f ), + .Q(\blk00000003/blk00000004/sig00001c7e ) + ); + FDS #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk00001a50 ( + .C(clk), + .D(\blk00000003/blk00000004/sig00001c83 ), + .S(\blk00000003/blk00000004/sig00001c82 ), + .Q(\blk00000003/blk00000004/sig00001c81 ) + ); + FDS #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk00001a4f ( + .C(clk), + .D(\blk00000003/blk00000004/sig00001c59 ), + .S(\blk00000003/blk00000004/sig00001c58 ), + .Q(\blk00000003/blk00000004/sig00001c57 ) + ); + FDS #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk00001a4e ( + .C(clk), + .D(\blk00000003/blk00000004/sig00001c5c ), + .S(\blk00000003/blk00000004/sig00001c5b ), + .Q(\blk00000003/blk00000004/sig00001c5a ) + ); + FDS #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk00001a4d ( + .C(clk), + .D(\blk00000003/blk00000004/sig00001c5f ), + .S(\blk00000003/blk00000004/sig00001c5e ), + .Q(\blk00000003/blk00000004/sig00001c5d ) + ); + FDS #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk00001a4c ( + .C(clk), + .D(\blk00000003/blk00000004/sig00001c62 ), + .S(\blk00000003/blk00000004/sig00001c61 ), + .Q(\blk00000003/blk00000004/sig00001c60 ) + ); + FDS #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk00001a4b ( + .C(clk), + .D(\blk00000003/blk00000004/sig00001c65 ), + .S(\blk00000003/blk00000004/sig00001c64 ), + .Q(\blk00000003/blk00000004/sig00001c63 ) + ); + FDS #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk00001a4a ( + .C(clk), + .D(\blk00000003/blk00000004/sig00001c68 ), + .S(\blk00000003/blk00000004/sig00001c67 ), + .Q(\blk00000003/blk00000004/sig00001c66 ) + ); + FDS #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk00001a49 ( + .C(clk), + .D(\blk00000003/blk00000004/sig00001c6b ), + .S(\blk00000003/blk00000004/sig00001c6a ), + .Q(\blk00000003/blk00000004/sig00001c69 ) + ); + FDS #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk00001a48 ( + .C(clk), + .D(\blk00000003/blk00000004/sig00001c6e ), + .S(\blk00000003/blk00000004/sig00001c6d ), + .Q(\blk00000003/blk00000004/sig00001c6c ) + ); + FDS #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk00001a47 ( + .C(clk), + .D(\blk00000003/blk00000004/sig00001c71 ), + .S(\blk00000003/blk00000004/sig00001c70 ), + .Q(\blk00000003/blk00000004/sig00001c6f ) + ); + FDS #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk00001a46 ( + .C(clk), + .D(\blk00000003/blk00000004/sig00001c86 ), + .S(\blk00000003/blk00000004/sig00001c85 ), + .Q(\blk00000003/blk00000004/sig00001c84 ) + ); + FDS #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk00001a45 ( + .C(clk), + .D(\blk00000003/blk00000004/sig00001ca4 ), + .S(\blk00000003/blk00000004/sig00001ca3 ), + .Q(\blk00000003/blk00000004/sig00001ca2 ) + ); + FDS #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk00001a44 ( + .C(clk), + .D(\blk00000003/blk00000004/sig00001ca7 ), + .S(\blk00000003/blk00000004/sig00001ca6 ), + .Q(\blk00000003/blk00000004/sig00001ca5 ) + ); + FDS #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk00001a43 ( + .C(clk), + .D(\blk00000003/blk00000004/sig00001caa ), + .S(\blk00000003/blk00000004/sig00001ca9 ), + .Q(\blk00000003/blk00000004/sig00001ca8 ) + ); + FDS #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk00001a42 ( + .C(clk), + .D(\blk00000003/blk00000004/sig00001cad ), + .S(\blk00000003/blk00000004/sig00001cac ), + .Q(\blk00000003/blk00000004/sig00001cab ) + ); + FDS #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk00001a41 ( + .C(clk), + .D(\blk00000003/blk00000004/sig00001cb0 ), + .S(\blk00000003/blk00000004/sig00001caf ), + .Q(\blk00000003/blk00000004/sig00001cae ) + ); + FDS #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk00001a40 ( + .C(clk), + .D(\blk00000003/blk00000004/sig00001cb3 ), + .S(\blk00000003/blk00000004/sig00001cb2 ), + .Q(\blk00000003/blk00000004/sig00001cb1 ) + ); + FDS #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk00001a3f ( + .C(clk), + .D(\blk00000003/blk00000004/sig00001c89 ), + .S(\blk00000003/blk00000004/sig00001c88 ), + .Q(\blk00000003/blk00000004/sig00001c87 ) + ); + FDS #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk00001a3e ( + .C(clk), + .D(\blk00000003/blk00000004/sig00001c8c ), + .S(\blk00000003/blk00000004/sig00001c8b ), + .Q(\blk00000003/blk00000004/sig00001c8a ) + ); + FDS #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk00001a3d ( + .C(clk), + .D(\blk00000003/blk00000004/sig00001c8f ), + .S(\blk00000003/blk00000004/sig00001c8e ), + .Q(\blk00000003/blk00000004/sig00001c8d ) + ); + FDS #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk00001a3c ( + .C(clk), + .D(\blk00000003/blk00000004/sig00001c92 ), + .S(\blk00000003/blk00000004/sig00001c91 ), + .Q(\blk00000003/blk00000004/sig00001c90 ) + ); + FDS #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk00001a3b ( + .C(clk), + .D(\blk00000003/blk00000004/sig00001c95 ), + .S(\blk00000003/blk00000004/sig00001c94 ), + .Q(\blk00000003/blk00000004/sig00001c93 ) + ); + FDS #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk00001a3a ( + .C(clk), + .D(\blk00000003/blk00000004/sig00001c98 ), + .S(\blk00000003/blk00000004/sig00001c97 ), + .Q(\blk00000003/blk00000004/sig00001c96 ) + ); + FDS #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk00001a39 ( + .C(clk), + .D(\blk00000003/blk00000004/sig00001c9b ), + .S(\blk00000003/blk00000004/sig00001c9a ), + .Q(\blk00000003/blk00000004/sig00001c99 ) + ); + FDS #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk00001a38 ( + .C(clk), + .D(\blk00000003/blk00000004/sig00001c9e ), + .S(\blk00000003/blk00000004/sig00001c9d ), + .Q(\blk00000003/blk00000004/sig00001c9c ) + ); + FDS #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk00001a37 ( + .C(clk), + .D(\blk00000003/blk00000004/sig00001ca1 ), + .S(\blk00000003/blk00000004/sig00001ca0 ), + .Q(\blk00000003/blk00000004/sig00001c9f ) + ); + FDS #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk00001a36 ( + .C(clk), + .D(\blk00000003/blk00000004/sig00001cb6 ), + .S(\blk00000003/blk00000004/sig00001cb5 ), + .Q(\blk00000003/blk00000004/sig00001cb4 ) + ); + FDS #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk00001a35 ( + .C(clk), + .D(\blk00000003/blk00000004/sig00001cd4 ), + .S(\blk00000003/blk00000004/sig00001cd3 ), + .Q(\blk00000003/blk00000004/sig00001cd2 ) + ); + FDS #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk00001a34 ( + .C(clk), + .D(\blk00000003/blk00000004/sig00001cd7 ), + .S(\blk00000003/blk00000004/sig00001cd6 ), + .Q(\blk00000003/blk00000004/sig00001cd5 ) + ); + FDS #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk00001a33 ( + .C(clk), + .D(\blk00000003/blk00000004/sig00001cda ), + .S(\blk00000003/blk00000004/sig00001cd9 ), + .Q(\blk00000003/blk00000004/sig00001cd8 ) + ); + FDS #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk00001a32 ( + .C(clk), + .D(\blk00000003/blk00000004/sig00001cdd ), + .S(\blk00000003/blk00000004/sig00001cdc ), + .Q(\blk00000003/blk00000004/sig00001cdb ) + ); + FDS #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk00001a31 ( + .C(clk), + .D(\blk00000003/blk00000004/sig00001ce0 ), + .S(\blk00000003/blk00000004/sig00001cdf ), + .Q(\blk00000003/blk00000004/sig00001cde ) + ); + FDS #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk00001a30 ( + .C(clk), + .D(\blk00000003/blk00000004/sig00001ce3 ), + .S(\blk00000003/blk00000004/sig00001ce2 ), + .Q(\blk00000003/blk00000004/sig00001ce1 ) + ); + FDS #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk00001a2f ( + .C(clk), + .D(\blk00000003/blk00000004/sig00001cb9 ), + .S(\blk00000003/blk00000004/sig00001cb8 ), + .Q(\blk00000003/blk00000004/sig00001cb7 ) + ); + FDS #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk00001a2e ( + .C(clk), + .D(\blk00000003/blk00000004/sig00001cbc ), + .S(\blk00000003/blk00000004/sig00001cbb ), + .Q(\blk00000003/blk00000004/sig00001cba ) + ); + FDS #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk00001a2d ( + .C(clk), + .D(\blk00000003/blk00000004/sig00001cbf ), + .S(\blk00000003/blk00000004/sig00001cbe ), + .Q(\blk00000003/blk00000004/sig00001cbd ) + ); + FDS #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk00001a2c ( + .C(clk), + .D(\blk00000003/blk00000004/sig00001cc2 ), + .S(\blk00000003/blk00000004/sig00001cc1 ), + .Q(\blk00000003/blk00000004/sig00001cc0 ) + ); + FDS #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk00001a2b ( + .C(clk), + .D(\blk00000003/blk00000004/sig00001cc5 ), + .S(\blk00000003/blk00000004/sig00001cc4 ), + .Q(\blk00000003/blk00000004/sig00001cc3 ) + ); + FDS #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk00001a2a ( + .C(clk), + .D(\blk00000003/blk00000004/sig00001cc8 ), + .S(\blk00000003/blk00000004/sig00001cc7 ), + .Q(\blk00000003/blk00000004/sig00001cc6 ) + ); + FDS #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk00001a29 ( + .C(clk), + .D(\blk00000003/blk00000004/sig00001ccb ), + .S(\blk00000003/blk00000004/sig00001cca ), + .Q(\blk00000003/blk00000004/sig00001cc9 ) + ); + FDS #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk00001a28 ( + .C(clk), + .D(\blk00000003/blk00000004/sig00001cce ), + .S(\blk00000003/blk00000004/sig00001ccd ), + .Q(\blk00000003/blk00000004/sig00001ccc ) + ); + FDS #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk00001a27 ( + .C(clk), + .D(\blk00000003/blk00000004/sig00001cd1 ), + .S(\blk00000003/blk00000004/sig00001cd0 ), + .Q(\blk00000003/blk00000004/sig00001ccf ) + ); + FDS #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk00001a26 ( + .C(clk), + .D(\blk00000003/blk00000004/sig00001ce6 ), + .S(\blk00000003/blk00000004/sig00001ce5 ), + .Q(\blk00000003/blk00000004/sig00001ce4 ) + ); + FDS #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk00001a25 ( + .C(clk), + .D(\blk00000003/blk00000004/sig0000212c ), + .S(\blk00000003/blk00000004/sig00001e28 ), + .Q(\blk00000003/blk00000004/sig0000027d ) + ); + FDS #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk00001a24 ( + .C(clk), + .D(\blk00000003/blk00000004/sig0000212b ), + .S(\blk00000003/blk00000004/sig00001e27 ), + .Q(\blk00000003/blk00000004/sig00000278 ) + ); + FDS #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk00001a23 ( + .C(clk), + .D(\blk00000003/blk00000004/sig0000212a ), + .S(\blk00000003/blk00000004/sig00001a4c ), + .Q(\blk00000003/blk00000004/sig00001a44 ) + ); + LUT3 #( + .INIT ( 8'hE4 )) + \blk00000003/blk00000004/blk00001a22 ( + .I0(\blk00000003/blk00000004/sig0000028c ), + .I1(\blk00000003/blk00000004/sig0000027e ), + .I2(\blk00000003/blk00000004/sig00000285 ), + .O(\blk00000003/blk00000004/sig0000029b ) + ); + LUT3 #( + .INIT ( 8'hAC )) + \blk00000003/blk00000004/blk00001a21 ( + .I0(\blk00000003/blk00000004/sig00000294 ), + .I1(\blk00000003/blk00000004/sig0000028d ), + .I2(\blk00000003/blk00000004/sig0000029b ), + .O(\blk00000003/blk00000004/sig00002129 ) + ); + LUT4 #( + .INIT ( 16'h0511 )) + \blk00000003/blk00000004/blk00001a20 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00002127 ), + .I2(\blk00000003/blk00000004/sig00002128 ), + .I3(\blk00000003/blk00000004/sig000019e1 ), + .O(\blk00000003/blk00000004/sig000019e2 ) + ); + LUT4 #( + .INIT ( 16'h0511 )) + \blk00000003/blk00000004/blk00001a1f ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00002125 ), + .I2(\blk00000003/blk00000004/sig00002126 ), + .I3(\blk00000003/blk00000004/sig000019e1 ), + .O(\blk00000003/blk00000004/sig000019e4 ) + ); + LUT4 #( + .INIT ( 16'h0511 )) + \blk00000003/blk00000004/blk00001a1e ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00002123 ), + .I2(\blk00000003/blk00000004/sig00002124 ), + .I3(\blk00000003/blk00000004/sig000019e1 ), + .O(\blk00000003/blk00000004/sig000019e6 ) + ); + LUT4 #( + .INIT ( 16'h0511 )) + \blk00000003/blk00000004/blk00001a1d ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00002121 ), + .I2(\blk00000003/blk00000004/sig00002122 ), + .I3(\blk00000003/blk00000004/sig000019e1 ), + .O(\blk00000003/blk00000004/sig000019e8 ) + ); + LUT4 #( + .INIT ( 16'h0511 )) + \blk00000003/blk00000004/blk00001a1c ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig0000211f ), + .I2(\blk00000003/blk00000004/sig00002120 ), + .I3(\blk00000003/blk00000004/sig000019e1 ), + .O(\blk00000003/blk00000004/sig000019ea ) + ); + LUT4 #( + .INIT ( 16'h0511 )) + \blk00000003/blk00000004/blk00001a1b ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig0000211d ), + .I2(\blk00000003/blk00000004/sig0000211e ), + .I3(\blk00000003/blk00000004/sig000019e1 ), + .O(\blk00000003/blk00000004/sig000019ec ) + ); + LUT4 #( + .INIT ( 16'h0511 )) + \blk00000003/blk00000004/blk00001a1a ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig0000211b ), + .I2(\blk00000003/blk00000004/sig0000211c ), + .I3(\blk00000003/blk00000004/sig000016fd ), + .O(\blk00000003/blk00000004/sig000016fe ) + ); + LUT4 #( + .INIT ( 16'h0511 )) + \blk00000003/blk00000004/blk00001a19 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00002119 ), + .I2(\blk00000003/blk00000004/sig0000211a ), + .I3(\blk00000003/blk00000004/sig000016fd ), + .O(\blk00000003/blk00000004/sig00001700 ) + ); + LUT4 #( + .INIT ( 16'h0511 )) + \blk00000003/blk00000004/blk00001a18 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00002117 ), + .I2(\blk00000003/blk00000004/sig00002118 ), + .I3(\blk00000003/blk00000004/sig000016fd ), + .O(\blk00000003/blk00000004/sig00001702 ) + ); + LUT4 #( + .INIT ( 16'h0511 )) + \blk00000003/blk00000004/blk00001a17 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00002115 ), + .I2(\blk00000003/blk00000004/sig00002116 ), + .I3(\blk00000003/blk00000004/sig000016fd ), + .O(\blk00000003/blk00000004/sig00001704 ) + ); + LUT4 #( + .INIT ( 16'h0511 )) + \blk00000003/blk00000004/blk00001a16 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00002113 ), + .I2(\blk00000003/blk00000004/sig00002114 ), + .I3(\blk00000003/blk00000004/sig000016fd ), + .O(\blk00000003/blk00000004/sig00001706 ) + ); + LUT4 #( + .INIT ( 16'h0511 )) + \blk00000003/blk00000004/blk00001a15 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00002111 ), + .I2(\blk00000003/blk00000004/sig00002112 ), + .I3(\blk00000003/blk00000004/sig000016fd ), + .O(\blk00000003/blk00000004/sig00001708 ) + ); + LUT4 #( + .INIT ( 16'h0511 )) + \blk00000003/blk00000004/blk00001a14 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig0000210f ), + .I2(\blk00000003/blk00000004/sig00002110 ), + .I3(\blk00000003/blk00000004/sig000016b3 ), + .O(\blk00000003/blk00000004/sig000016b4 ) + ); + LUT4 #( + .INIT ( 16'h0511 )) + \blk00000003/blk00000004/blk00001a13 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig0000210d ), + .I2(\blk00000003/blk00000004/sig0000210e ), + .I3(\blk00000003/blk00000004/sig000016b3 ), + .O(\blk00000003/blk00000004/sig000016b6 ) + ); + LUT4 #( + .INIT ( 16'h0511 )) + \blk00000003/blk00000004/blk00001a12 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig0000210b ), + .I2(\blk00000003/blk00000004/sig0000210c ), + .I3(\blk00000003/blk00000004/sig000016b3 ), + .O(\blk00000003/blk00000004/sig000016b8 ) + ); + LUT4 #( + .INIT ( 16'h0511 )) + \blk00000003/blk00000004/blk00001a11 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00002109 ), + .I2(\blk00000003/blk00000004/sig0000210a ), + .I3(\blk00000003/blk00000004/sig000016b3 ), + .O(\blk00000003/blk00000004/sig000016ba ) + ); + LUT4 #( + .INIT ( 16'h0511 )) + \blk00000003/blk00000004/blk00001a10 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00002107 ), + .I2(\blk00000003/blk00000004/sig00002108 ), + .I3(\blk00000003/blk00000004/sig000016b3 ), + .O(\blk00000003/blk00000004/sig000016bc ) + ); + LUT4 #( + .INIT ( 16'h0511 )) + \blk00000003/blk00000004/blk00001a0f ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00002105 ), + .I2(\blk00000003/blk00000004/sig00002106 ), + .I3(\blk00000003/blk00000004/sig000016b3 ), + .O(\blk00000003/blk00000004/sig000016be ) + ); + LUT4 #( + .INIT ( 16'h0511 )) + \blk00000003/blk00000004/blk00001a0e ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00002103 ), + .I2(\blk00000003/blk00000004/sig00002104 ), + .I3(\blk00000003/blk00000004/sig00001669 ), + .O(\blk00000003/blk00000004/sig0000166a ) + ); + LUT4 #( + .INIT ( 16'h0511 )) + \blk00000003/blk00000004/blk00001a0d ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00002101 ), + .I2(\blk00000003/blk00000004/sig00002102 ), + .I3(\blk00000003/blk00000004/sig00001669 ), + .O(\blk00000003/blk00000004/sig0000166c ) + ); + LUT4 #( + .INIT ( 16'h0511 )) + \blk00000003/blk00000004/blk00001a0c ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig000020ff ), + .I2(\blk00000003/blk00000004/sig00002100 ), + .I3(\blk00000003/blk00000004/sig00001669 ), + .O(\blk00000003/blk00000004/sig0000166e ) + ); + LUT4 #( + .INIT ( 16'h0511 )) + \blk00000003/blk00000004/blk00001a0b ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig000020fd ), + .I2(\blk00000003/blk00000004/sig000020fe ), + .I3(\blk00000003/blk00000004/sig00001669 ), + .O(\blk00000003/blk00000004/sig00001670 ) + ); + LUT4 #( + .INIT ( 16'h0511 )) + \blk00000003/blk00000004/blk00001a0a ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig000020fb ), + .I2(\blk00000003/blk00000004/sig000020fc ), + .I3(\blk00000003/blk00000004/sig00001669 ), + .O(\blk00000003/blk00000004/sig00001672 ) + ); + LUT4 #( + .INIT ( 16'h0511 )) + \blk00000003/blk00000004/blk00001a09 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig000020f9 ), + .I2(\blk00000003/blk00000004/sig000020fa ), + .I3(\blk00000003/blk00000004/sig00001669 ), + .O(\blk00000003/blk00000004/sig00001674 ) + ); + LUT4 #( + .INIT ( 16'h0511 )) + \blk00000003/blk00000004/blk00001a08 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig000020f7 ), + .I2(\blk00000003/blk00000004/sig000020f8 ), + .I3(\blk00000003/blk00000004/sig0000161f ), + .O(\blk00000003/blk00000004/sig00001620 ) + ); + LUT4 #( + .INIT ( 16'h0511 )) + \blk00000003/blk00000004/blk00001a07 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig000020f5 ), + .I2(\blk00000003/blk00000004/sig000020f6 ), + .I3(\blk00000003/blk00000004/sig0000161f ), + .O(\blk00000003/blk00000004/sig00001622 ) + ); + LUT4 #( + .INIT ( 16'h0511 )) + \blk00000003/blk00000004/blk00001a06 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig000020f3 ), + .I2(\blk00000003/blk00000004/sig000020f4 ), + .I3(\blk00000003/blk00000004/sig0000161f ), + .O(\blk00000003/blk00000004/sig00001624 ) + ); + LUT4 #( + .INIT ( 16'h0511 )) + \blk00000003/blk00000004/blk00001a05 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig000020f1 ), + .I2(\blk00000003/blk00000004/sig000020f2 ), + .I3(\blk00000003/blk00000004/sig0000161f ), + .O(\blk00000003/blk00000004/sig00001626 ) + ); + LUT4 #( + .INIT ( 16'h0511 )) + \blk00000003/blk00000004/blk00001a04 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig000020ef ), + .I2(\blk00000003/blk00000004/sig000020f0 ), + .I3(\blk00000003/blk00000004/sig0000161f ), + .O(\blk00000003/blk00000004/sig00001628 ) + ); + LUT4 #( + .INIT ( 16'h0511 )) + \blk00000003/blk00000004/blk00001a03 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig000020ed ), + .I2(\blk00000003/blk00000004/sig000020ee ), + .I3(\blk00000003/blk00000004/sig0000161f ), + .O(\blk00000003/blk00000004/sig0000162a ) + ); + LUT4 #( + .INIT ( 16'h0511 )) + \blk00000003/blk00000004/blk00001a02 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig000020eb ), + .I2(\blk00000003/blk00000004/sig000020ec ), + .I3(\blk00000003/blk00000004/sig000015d5 ), + .O(\blk00000003/blk00000004/sig000015d6 ) + ); + LUT4 #( + .INIT ( 16'h0511 )) + \blk00000003/blk00000004/blk00001a01 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig000020e9 ), + .I2(\blk00000003/blk00000004/sig000020ea ), + .I3(\blk00000003/blk00000004/sig000015d5 ), + .O(\blk00000003/blk00000004/sig000015d8 ) + ); + LUT4 #( + .INIT ( 16'h0511 )) + \blk00000003/blk00000004/blk00001a00 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig000020e7 ), + .I2(\blk00000003/blk00000004/sig000020e8 ), + .I3(\blk00000003/blk00000004/sig000015d5 ), + .O(\blk00000003/blk00000004/sig000015da ) + ); + LUT4 #( + .INIT ( 16'h0511 )) + \blk00000003/blk00000004/blk000019ff ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig000020e5 ), + .I2(\blk00000003/blk00000004/sig000020e6 ), + .I3(\blk00000003/blk00000004/sig000015d5 ), + .O(\blk00000003/blk00000004/sig000015dc ) + ); + LUT4 #( + .INIT ( 16'h0511 )) + \blk00000003/blk00000004/blk000019fe ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig000020e3 ), + .I2(\blk00000003/blk00000004/sig000020e4 ), + .I3(\blk00000003/blk00000004/sig000015d5 ), + .O(\blk00000003/blk00000004/sig000015de ) + ); + LUT4 #( + .INIT ( 16'h0511 )) + \blk00000003/blk00000004/blk000019fd ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig000020e1 ), + .I2(\blk00000003/blk00000004/sig000020e2 ), + .I3(\blk00000003/blk00000004/sig000015d5 ), + .O(\blk00000003/blk00000004/sig000015e0 ) + ); + LUT4 #( + .INIT ( 16'h0511 )) + \blk00000003/blk00000004/blk000019fc ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig000020df ), + .I2(\blk00000003/blk00000004/sig000020e0 ), + .I3(\blk00000003/blk00000004/sig0000158b ), + .O(\blk00000003/blk00000004/sig0000158c ) + ); + LUT4 #( + .INIT ( 16'h0511 )) + \blk00000003/blk00000004/blk000019fb ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig000020dd ), + .I2(\blk00000003/blk00000004/sig000020de ), + .I3(\blk00000003/blk00000004/sig0000158b ), + .O(\blk00000003/blk00000004/sig0000158e ) + ); + LUT4 #( + .INIT ( 16'h0511 )) + \blk00000003/blk00000004/blk000019fa ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig000020db ), + .I2(\blk00000003/blk00000004/sig000020dc ), + .I3(\blk00000003/blk00000004/sig0000158b ), + .O(\blk00000003/blk00000004/sig00001590 ) + ); + LUT4 #( + .INIT ( 16'h0511 )) + \blk00000003/blk00000004/blk000019f9 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig000020d9 ), + .I2(\blk00000003/blk00000004/sig000020da ), + .I3(\blk00000003/blk00000004/sig0000158b ), + .O(\blk00000003/blk00000004/sig00001592 ) + ); + LUT4 #( + .INIT ( 16'h0511 )) + \blk00000003/blk00000004/blk000019f8 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig000020d7 ), + .I2(\blk00000003/blk00000004/sig000020d8 ), + .I3(\blk00000003/blk00000004/sig0000158b ), + .O(\blk00000003/blk00000004/sig00001594 ) + ); + LUT4 #( + .INIT ( 16'h0511 )) + \blk00000003/blk00000004/blk000019f7 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig000020d5 ), + .I2(\blk00000003/blk00000004/sig000020d6 ), + .I3(\blk00000003/blk00000004/sig0000158b ), + .O(\blk00000003/blk00000004/sig00001596 ) + ); + LUT4 #( + .INIT ( 16'h0511 )) + \blk00000003/blk00000004/blk000019f6 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig000020d3 ), + .I2(\blk00000003/blk00000004/sig000020d4 ), + .I3(\blk00000003/blk00000004/sig00001541 ), + .O(\blk00000003/blk00000004/sig00001542 ) + ); + LUT4 #( + .INIT ( 16'h0511 )) + \blk00000003/blk00000004/blk000019f5 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig000020d1 ), + .I2(\blk00000003/blk00000004/sig000020d2 ), + .I3(\blk00000003/blk00000004/sig00001541 ), + .O(\blk00000003/blk00000004/sig00001544 ) + ); + LUT4 #( + .INIT ( 16'h0511 )) + \blk00000003/blk00000004/blk000019f4 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig000020cf ), + .I2(\blk00000003/blk00000004/sig000020d0 ), + .I3(\blk00000003/blk00000004/sig00001541 ), + .O(\blk00000003/blk00000004/sig00001546 ) + ); + LUT4 #( + .INIT ( 16'h0511 )) + \blk00000003/blk00000004/blk000019f3 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig000020cd ), + .I2(\blk00000003/blk00000004/sig000020ce ), + .I3(\blk00000003/blk00000004/sig00001541 ), + .O(\blk00000003/blk00000004/sig00001548 ) + ); + LUT4 #( + .INIT ( 16'h0511 )) + \blk00000003/blk00000004/blk000019f2 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig000020cb ), + .I2(\blk00000003/blk00000004/sig000020cc ), + .I3(\blk00000003/blk00000004/sig00001541 ), + .O(\blk00000003/blk00000004/sig0000154a ) + ); + LUT4 #( + .INIT ( 16'h0511 )) + \blk00000003/blk00000004/blk000019f1 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig000020c9 ), + .I2(\blk00000003/blk00000004/sig000020ca ), + .I3(\blk00000003/blk00000004/sig00001541 ), + .O(\blk00000003/blk00000004/sig0000154c ) + ); + LUT4 #( + .INIT ( 16'h0511 )) + \blk00000003/blk00000004/blk000019f0 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig000020c7 ), + .I2(\blk00000003/blk00000004/sig000020c8 ), + .I3(\blk00000003/blk00000004/sig000014f7 ), + .O(\blk00000003/blk00000004/sig000014f8 ) + ); + LUT4 #( + .INIT ( 16'h0511 )) + \blk00000003/blk00000004/blk000019ef ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig000020c5 ), + .I2(\blk00000003/blk00000004/sig000020c6 ), + .I3(\blk00000003/blk00000004/sig000014f7 ), + .O(\blk00000003/blk00000004/sig000014fa ) + ); + LUT4 #( + .INIT ( 16'h0511 )) + \blk00000003/blk00000004/blk000019ee ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig000020c3 ), + .I2(\blk00000003/blk00000004/sig000020c4 ), + .I3(\blk00000003/blk00000004/sig000014f7 ), + .O(\blk00000003/blk00000004/sig000014fc ) + ); + LUT4 #( + .INIT ( 16'h0511 )) + \blk00000003/blk00000004/blk000019ed ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig000020c1 ), + .I2(\blk00000003/blk00000004/sig000020c2 ), + .I3(\blk00000003/blk00000004/sig000014f7 ), + .O(\blk00000003/blk00000004/sig000014fe ) + ); + LUT4 #( + .INIT ( 16'h0511 )) + \blk00000003/blk00000004/blk000019ec ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig000020bf ), + .I2(\blk00000003/blk00000004/sig000020c0 ), + .I3(\blk00000003/blk00000004/sig000014f7 ), + .O(\blk00000003/blk00000004/sig00001500 ) + ); + LUT4 #( + .INIT ( 16'h0511 )) + \blk00000003/blk00000004/blk000019eb ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig000020bd ), + .I2(\blk00000003/blk00000004/sig000020be ), + .I3(\blk00000003/blk00000004/sig000014f7 ), + .O(\blk00000003/blk00000004/sig00001502 ) + ); + LUT4 #( + .INIT ( 16'h0511 )) + \blk00000003/blk00000004/blk000019ea ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig000020bb ), + .I2(\blk00000003/blk00000004/sig000020bc ), + .I3(\blk00000003/blk00000004/sig000014ad ), + .O(\blk00000003/blk00000004/sig000014ae ) + ); + LUT4 #( + .INIT ( 16'h0511 )) + \blk00000003/blk00000004/blk000019e9 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig000020b9 ), + .I2(\blk00000003/blk00000004/sig000020ba ), + .I3(\blk00000003/blk00000004/sig000014ad ), + .O(\blk00000003/blk00000004/sig000014b0 ) + ); + LUT4 #( + .INIT ( 16'h0511 )) + \blk00000003/blk00000004/blk000019e8 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig000020b7 ), + .I2(\blk00000003/blk00000004/sig000020b8 ), + .I3(\blk00000003/blk00000004/sig000014ad ), + .O(\blk00000003/blk00000004/sig000014b2 ) + ); + LUT4 #( + .INIT ( 16'h0511 )) + \blk00000003/blk00000004/blk000019e7 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig000020b5 ), + .I2(\blk00000003/blk00000004/sig000020b6 ), + .I3(\blk00000003/blk00000004/sig000014ad ), + .O(\blk00000003/blk00000004/sig000014b4 ) + ); + LUT4 #( + .INIT ( 16'h0511 )) + \blk00000003/blk00000004/blk000019e6 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig000020b3 ), + .I2(\blk00000003/blk00000004/sig000020b4 ), + .I3(\blk00000003/blk00000004/sig000014ad ), + .O(\blk00000003/blk00000004/sig000014b6 ) + ); + LUT4 #( + .INIT ( 16'h0511 )) + \blk00000003/blk00000004/blk000019e5 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig000020b1 ), + .I2(\blk00000003/blk00000004/sig000020b2 ), + .I3(\blk00000003/blk00000004/sig000014ad ), + .O(\blk00000003/blk00000004/sig000014b8 ) + ); + LUT4 #( + .INIT ( 16'h0511 )) + \blk00000003/blk00000004/blk000019e4 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig000020af ), + .I2(\blk00000003/blk00000004/sig000020b0 ), + .I3(\blk00000003/blk00000004/sig00001463 ), + .O(\blk00000003/blk00000004/sig00001464 ) + ); + LUT4 #( + .INIT ( 16'h0511 )) + \blk00000003/blk00000004/blk000019e3 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig000020ad ), + .I2(\blk00000003/blk00000004/sig000020ae ), + .I3(\blk00000003/blk00000004/sig00001463 ), + .O(\blk00000003/blk00000004/sig00001466 ) + ); + LUT4 #( + .INIT ( 16'h0511 )) + \blk00000003/blk00000004/blk000019e2 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig000020ab ), + .I2(\blk00000003/blk00000004/sig000020ac ), + .I3(\blk00000003/blk00000004/sig00001463 ), + .O(\blk00000003/blk00000004/sig00001468 ) + ); + LUT4 #( + .INIT ( 16'h0511 )) + \blk00000003/blk00000004/blk000019e1 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig000020a9 ), + .I2(\blk00000003/blk00000004/sig000020aa ), + .I3(\blk00000003/blk00000004/sig00001463 ), + .O(\blk00000003/blk00000004/sig0000146a ) + ); + LUT4 #( + .INIT ( 16'h0511 )) + \blk00000003/blk00000004/blk000019e0 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig000020a7 ), + .I2(\blk00000003/blk00000004/sig000020a8 ), + .I3(\blk00000003/blk00000004/sig00001463 ), + .O(\blk00000003/blk00000004/sig0000146c ) + ); + LUT4 #( + .INIT ( 16'h0511 )) + \blk00000003/blk00000004/blk000019df ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig000020a5 ), + .I2(\blk00000003/blk00000004/sig000020a6 ), + .I3(\blk00000003/blk00000004/sig00001463 ), + .O(\blk00000003/blk00000004/sig0000146e ) + ); + LUT4 #( + .INIT ( 16'h0511 )) + \blk00000003/blk00000004/blk000019de ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig000020a3 ), + .I2(\blk00000003/blk00000004/sig000020a4 ), + .I3(\blk00000003/blk00000004/sig00001997 ), + .O(\blk00000003/blk00000004/sig00001998 ) + ); + LUT4 #( + .INIT ( 16'h0511 )) + \blk00000003/blk00000004/blk000019dd ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig000020a1 ), + .I2(\blk00000003/blk00000004/sig000020a2 ), + .I3(\blk00000003/blk00000004/sig00001997 ), + .O(\blk00000003/blk00000004/sig0000199a ) + ); + LUT4 #( + .INIT ( 16'h0511 )) + \blk00000003/blk00000004/blk000019dc ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig0000209f ), + .I2(\blk00000003/blk00000004/sig000020a0 ), + .I3(\blk00000003/blk00000004/sig00001997 ), + .O(\blk00000003/blk00000004/sig0000199c ) + ); + LUT4 #( + .INIT ( 16'h0511 )) + \blk00000003/blk00000004/blk000019db ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig0000209d ), + .I2(\blk00000003/blk00000004/sig0000209e ), + .I3(\blk00000003/blk00000004/sig00001997 ), + .O(\blk00000003/blk00000004/sig0000199e ) + ); + LUT4 #( + .INIT ( 16'h0511 )) + \blk00000003/blk00000004/blk000019da ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig0000209b ), + .I2(\blk00000003/blk00000004/sig0000209c ), + .I3(\blk00000003/blk00000004/sig00001997 ), + .O(\blk00000003/blk00000004/sig000019a0 ) + ); + LUT4 #( + .INIT ( 16'h0511 )) + \blk00000003/blk00000004/blk000019d9 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00002099 ), + .I2(\blk00000003/blk00000004/sig0000209a ), + .I3(\blk00000003/blk00000004/sig00001997 ), + .O(\blk00000003/blk00000004/sig000019a2 ) + ); + LUT4 #( + .INIT ( 16'h0511 )) + \blk00000003/blk00000004/blk000019d8 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00002097 ), + .I2(\blk00000003/blk00000004/sig00002098 ), + .I3(\blk00000003/blk00000004/sig00001419 ), + .O(\blk00000003/blk00000004/sig0000141a ) + ); + LUT4 #( + .INIT ( 16'h0511 )) + \blk00000003/blk00000004/blk000019d7 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00002095 ), + .I2(\blk00000003/blk00000004/sig00002096 ), + .I3(\blk00000003/blk00000004/sig00001419 ), + .O(\blk00000003/blk00000004/sig0000141c ) + ); + LUT4 #( + .INIT ( 16'h0511 )) + \blk00000003/blk00000004/blk000019d6 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00002093 ), + .I2(\blk00000003/blk00000004/sig00002094 ), + .I3(\blk00000003/blk00000004/sig00001419 ), + .O(\blk00000003/blk00000004/sig0000141e ) + ); + LUT4 #( + .INIT ( 16'h0511 )) + \blk00000003/blk00000004/blk000019d5 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00002091 ), + .I2(\blk00000003/blk00000004/sig00002092 ), + .I3(\blk00000003/blk00000004/sig00001419 ), + .O(\blk00000003/blk00000004/sig00001420 ) + ); + LUT4 #( + .INIT ( 16'h0511 )) + \blk00000003/blk00000004/blk000019d4 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig0000208f ), + .I2(\blk00000003/blk00000004/sig00002090 ), + .I3(\blk00000003/blk00000004/sig00001419 ), + .O(\blk00000003/blk00000004/sig00001422 ) + ); + LUT4 #( + .INIT ( 16'h0511 )) + \blk00000003/blk00000004/blk000019d3 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig0000208d ), + .I2(\blk00000003/blk00000004/sig0000208e ), + .I3(\blk00000003/blk00000004/sig00001419 ), + .O(\blk00000003/blk00000004/sig00001424 ) + ); + LUT4 #( + .INIT ( 16'h0511 )) + \blk00000003/blk00000004/blk000019d2 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig0000208b ), + .I2(\blk00000003/blk00000004/sig0000208c ), + .I3(\blk00000003/blk00000004/sig000013cf ), + .O(\blk00000003/blk00000004/sig000013d0 ) + ); + LUT4 #( + .INIT ( 16'h0511 )) + \blk00000003/blk00000004/blk000019d1 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00002089 ), + .I2(\blk00000003/blk00000004/sig0000208a ), + .I3(\blk00000003/blk00000004/sig000013cf ), + .O(\blk00000003/blk00000004/sig000013d2 ) + ); + LUT4 #( + .INIT ( 16'h0511 )) + \blk00000003/blk00000004/blk000019d0 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00002087 ), + .I2(\blk00000003/blk00000004/sig00002088 ), + .I3(\blk00000003/blk00000004/sig000013cf ), + .O(\blk00000003/blk00000004/sig000013d4 ) + ); + LUT4 #( + .INIT ( 16'h0511 )) + \blk00000003/blk00000004/blk000019cf ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00002085 ), + .I2(\blk00000003/blk00000004/sig00002086 ), + .I3(\blk00000003/blk00000004/sig000013cf ), + .O(\blk00000003/blk00000004/sig000013d6 ) + ); + LUT4 #( + .INIT ( 16'h0511 )) + \blk00000003/blk00000004/blk000019ce ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00002083 ), + .I2(\blk00000003/blk00000004/sig00002084 ), + .I3(\blk00000003/blk00000004/sig000013cf ), + .O(\blk00000003/blk00000004/sig000013d8 ) + ); + LUT4 #( + .INIT ( 16'h0511 )) + \blk00000003/blk00000004/blk000019cd ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00002081 ), + .I2(\blk00000003/blk00000004/sig00002082 ), + .I3(\blk00000003/blk00000004/sig000013cf ), + .O(\blk00000003/blk00000004/sig000013da ) + ); + LUT4 #( + .INIT ( 16'h0511 )) + \blk00000003/blk00000004/blk000019cc ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig0000207f ), + .I2(\blk00000003/blk00000004/sig00002080 ), + .I3(\blk00000003/blk00000004/sig00001385 ), + .O(\blk00000003/blk00000004/sig00001386 ) + ); + LUT4 #( + .INIT ( 16'h0511 )) + \blk00000003/blk00000004/blk000019cb ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig0000207d ), + .I2(\blk00000003/blk00000004/sig0000207e ), + .I3(\blk00000003/blk00000004/sig00001385 ), + .O(\blk00000003/blk00000004/sig00001388 ) + ); + LUT4 #( + .INIT ( 16'h0511 )) + \blk00000003/blk00000004/blk000019ca ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig0000207b ), + .I2(\blk00000003/blk00000004/sig0000207c ), + .I3(\blk00000003/blk00000004/sig00001385 ), + .O(\blk00000003/blk00000004/sig0000138a ) + ); + LUT4 #( + .INIT ( 16'h0511 )) + \blk00000003/blk00000004/blk000019c9 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00002079 ), + .I2(\blk00000003/blk00000004/sig0000207a ), + .I3(\blk00000003/blk00000004/sig00001385 ), + .O(\blk00000003/blk00000004/sig0000138c ) + ); + LUT4 #( + .INIT ( 16'h0511 )) + \blk00000003/blk00000004/blk000019c8 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00002077 ), + .I2(\blk00000003/blk00000004/sig00002078 ), + .I3(\blk00000003/blk00000004/sig00001385 ), + .O(\blk00000003/blk00000004/sig0000138e ) + ); + LUT4 #( + .INIT ( 16'h0511 )) + \blk00000003/blk00000004/blk000019c7 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00002075 ), + .I2(\blk00000003/blk00000004/sig00002076 ), + .I3(\blk00000003/blk00000004/sig00001385 ), + .O(\blk00000003/blk00000004/sig00001390 ) + ); + LUT4 #( + .INIT ( 16'h0511 )) + \blk00000003/blk00000004/blk000019c6 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00002073 ), + .I2(\blk00000003/blk00000004/sig00002074 ), + .I3(\blk00000003/blk00000004/sig0000133b ), + .O(\blk00000003/blk00000004/sig0000133c ) + ); + LUT4 #( + .INIT ( 16'h0511 )) + \blk00000003/blk00000004/blk000019c5 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00002071 ), + .I2(\blk00000003/blk00000004/sig00002072 ), + .I3(\blk00000003/blk00000004/sig0000133b ), + .O(\blk00000003/blk00000004/sig0000133e ) + ); + LUT4 #( + .INIT ( 16'h0511 )) + \blk00000003/blk00000004/blk000019c4 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig0000206f ), + .I2(\blk00000003/blk00000004/sig00002070 ), + .I3(\blk00000003/blk00000004/sig0000133b ), + .O(\blk00000003/blk00000004/sig00001340 ) + ); + LUT4 #( + .INIT ( 16'h0511 )) + \blk00000003/blk00000004/blk000019c3 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig0000206d ), + .I2(\blk00000003/blk00000004/sig0000206e ), + .I3(\blk00000003/blk00000004/sig0000133b ), + .O(\blk00000003/blk00000004/sig00001342 ) + ); + LUT4 #( + .INIT ( 16'h0511 )) + \blk00000003/blk00000004/blk000019c2 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig0000206b ), + .I2(\blk00000003/blk00000004/sig0000206c ), + .I3(\blk00000003/blk00000004/sig0000133b ), + .O(\blk00000003/blk00000004/sig00001344 ) + ); + LUT4 #( + .INIT ( 16'h0511 )) + \blk00000003/blk00000004/blk000019c1 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00002069 ), + .I2(\blk00000003/blk00000004/sig0000206a ), + .I3(\blk00000003/blk00000004/sig0000133b ), + .O(\blk00000003/blk00000004/sig00001346 ) + ); + LUT4 #( + .INIT ( 16'h0511 )) + \blk00000003/blk00000004/blk000019c0 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00002067 ), + .I2(\blk00000003/blk00000004/sig00002068 ), + .I3(\blk00000003/blk00000004/sig000012f1 ), + .O(\blk00000003/blk00000004/sig000012f2 ) + ); + LUT4 #( + .INIT ( 16'h0511 )) + \blk00000003/blk00000004/blk000019bf ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00002065 ), + .I2(\blk00000003/blk00000004/sig00002066 ), + .I3(\blk00000003/blk00000004/sig000012f1 ), + .O(\blk00000003/blk00000004/sig000012f4 ) + ); + LUT4 #( + .INIT ( 16'h0511 )) + \blk00000003/blk00000004/blk000019be ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00002063 ), + .I2(\blk00000003/blk00000004/sig00002064 ), + .I3(\blk00000003/blk00000004/sig000012f1 ), + .O(\blk00000003/blk00000004/sig000012f6 ) + ); + LUT4 #( + .INIT ( 16'h0511 )) + \blk00000003/blk00000004/blk000019bd ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00002061 ), + .I2(\blk00000003/blk00000004/sig00002062 ), + .I3(\blk00000003/blk00000004/sig000012f1 ), + .O(\blk00000003/blk00000004/sig000012f8 ) + ); + LUT4 #( + .INIT ( 16'h0511 )) + \blk00000003/blk00000004/blk000019bc ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig0000205f ), + .I2(\blk00000003/blk00000004/sig00002060 ), + .I3(\blk00000003/blk00000004/sig000012f1 ), + .O(\blk00000003/blk00000004/sig000012fa ) + ); + LUT4 #( + .INIT ( 16'h0511 )) + \blk00000003/blk00000004/blk000019bb ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig0000205d ), + .I2(\blk00000003/blk00000004/sig0000205e ), + .I3(\blk00000003/blk00000004/sig000012f1 ), + .O(\blk00000003/blk00000004/sig000012fc ) + ); + LUT4 #( + .INIT ( 16'h0511 )) + \blk00000003/blk00000004/blk000019ba ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig0000205b ), + .I2(\blk00000003/blk00000004/sig0000205c ), + .I3(\blk00000003/blk00000004/sig000012a7 ), + .O(\blk00000003/blk00000004/sig000012a8 ) + ); + LUT4 #( + .INIT ( 16'h0511 )) + \blk00000003/blk00000004/blk000019b9 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00002059 ), + .I2(\blk00000003/blk00000004/sig0000205a ), + .I3(\blk00000003/blk00000004/sig000012a7 ), + .O(\blk00000003/blk00000004/sig000012aa ) + ); + LUT4 #( + .INIT ( 16'h0511 )) + \blk00000003/blk00000004/blk000019b8 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00002057 ), + .I2(\blk00000003/blk00000004/sig00002058 ), + .I3(\blk00000003/blk00000004/sig000012a7 ), + .O(\blk00000003/blk00000004/sig000012ac ) + ); + LUT4 #( + .INIT ( 16'h0511 )) + \blk00000003/blk00000004/blk000019b7 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00002055 ), + .I2(\blk00000003/blk00000004/sig00002056 ), + .I3(\blk00000003/blk00000004/sig000012a7 ), + .O(\blk00000003/blk00000004/sig000012ae ) + ); + LUT4 #( + .INIT ( 16'h0511 )) + \blk00000003/blk00000004/blk000019b6 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00002053 ), + .I2(\blk00000003/blk00000004/sig00002054 ), + .I3(\blk00000003/blk00000004/sig000012a7 ), + .O(\blk00000003/blk00000004/sig000012b0 ) + ); + LUT4 #( + .INIT ( 16'h0511 )) + \blk00000003/blk00000004/blk000019b5 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00002051 ), + .I2(\blk00000003/blk00000004/sig00002052 ), + .I3(\blk00000003/blk00000004/sig000012a7 ), + .O(\blk00000003/blk00000004/sig000012b2 ) + ); + LUT4 #( + .INIT ( 16'h0511 )) + \blk00000003/blk00000004/blk000019b4 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig0000204f ), + .I2(\blk00000003/blk00000004/sig00002050 ), + .I3(\blk00000003/blk00000004/sig0000125d ), + .O(\blk00000003/blk00000004/sig0000125e ) + ); + LUT4 #( + .INIT ( 16'h0511 )) + \blk00000003/blk00000004/blk000019b3 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig0000204d ), + .I2(\blk00000003/blk00000004/sig0000204e ), + .I3(\blk00000003/blk00000004/sig0000125d ), + .O(\blk00000003/blk00000004/sig00001260 ) + ); + LUT4 #( + .INIT ( 16'h0511 )) + \blk00000003/blk00000004/blk000019b2 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig0000204b ), + .I2(\blk00000003/blk00000004/sig0000204c ), + .I3(\blk00000003/blk00000004/sig0000125d ), + .O(\blk00000003/blk00000004/sig00001262 ) + ); + LUT4 #( + .INIT ( 16'h0511 )) + \blk00000003/blk00000004/blk000019b1 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00002049 ), + .I2(\blk00000003/blk00000004/sig0000204a ), + .I3(\blk00000003/blk00000004/sig0000125d ), + .O(\blk00000003/blk00000004/sig00001264 ) + ); + LUT4 #( + .INIT ( 16'h0511 )) + \blk00000003/blk00000004/blk000019b0 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00002047 ), + .I2(\blk00000003/blk00000004/sig00002048 ), + .I3(\blk00000003/blk00000004/sig0000125d ), + .O(\blk00000003/blk00000004/sig00001266 ) + ); + LUT4 #( + .INIT ( 16'h0511 )) + \blk00000003/blk00000004/blk000019af ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00002045 ), + .I2(\blk00000003/blk00000004/sig00002046 ), + .I3(\blk00000003/blk00000004/sig0000125d ), + .O(\blk00000003/blk00000004/sig00001268 ) + ); + LUT4 #( + .INIT ( 16'h0511 )) + \blk00000003/blk00000004/blk000019ae ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00002043 ), + .I2(\blk00000003/blk00000004/sig00002044 ), + .I3(\blk00000003/blk00000004/sig00001213 ), + .O(\blk00000003/blk00000004/sig00001214 ) + ); + LUT4 #( + .INIT ( 16'h0511 )) + \blk00000003/blk00000004/blk000019ad ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00002041 ), + .I2(\blk00000003/blk00000004/sig00002042 ), + .I3(\blk00000003/blk00000004/sig00001213 ), + .O(\blk00000003/blk00000004/sig00001216 ) + ); + LUT4 #( + .INIT ( 16'h0511 )) + \blk00000003/blk00000004/blk000019ac ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig0000203f ), + .I2(\blk00000003/blk00000004/sig00002040 ), + .I3(\blk00000003/blk00000004/sig00001213 ), + .O(\blk00000003/blk00000004/sig00001218 ) + ); + LUT4 #( + .INIT ( 16'h0511 )) + \blk00000003/blk00000004/blk000019ab ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig0000203d ), + .I2(\blk00000003/blk00000004/sig0000203e ), + .I3(\blk00000003/blk00000004/sig00001213 ), + .O(\blk00000003/blk00000004/sig0000121a ) + ); + LUT4 #( + .INIT ( 16'h0511 )) + \blk00000003/blk00000004/blk000019aa ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig0000203b ), + .I2(\blk00000003/blk00000004/sig0000203c ), + .I3(\blk00000003/blk00000004/sig00001213 ), + .O(\blk00000003/blk00000004/sig0000121c ) + ); + LUT4 #( + .INIT ( 16'h0511 )) + \blk00000003/blk00000004/blk000019a9 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00002039 ), + .I2(\blk00000003/blk00000004/sig0000203a ), + .I3(\blk00000003/blk00000004/sig00001213 ), + .O(\blk00000003/blk00000004/sig0000121e ) + ); + LUT4 #( + .INIT ( 16'h0511 )) + \blk00000003/blk00000004/blk000019a8 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00002037 ), + .I2(\blk00000003/blk00000004/sig00002038 ), + .I3(\blk00000003/blk00000004/sig000011c9 ), + .O(\blk00000003/blk00000004/sig000011ca ) + ); + LUT4 #( + .INIT ( 16'h0511 )) + \blk00000003/blk00000004/blk000019a7 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00002035 ), + .I2(\blk00000003/blk00000004/sig00002036 ), + .I3(\blk00000003/blk00000004/sig000011c9 ), + .O(\blk00000003/blk00000004/sig000011cc ) + ); + LUT4 #( + .INIT ( 16'h0511 )) + \blk00000003/blk00000004/blk000019a6 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00002033 ), + .I2(\blk00000003/blk00000004/sig00002034 ), + .I3(\blk00000003/blk00000004/sig000011c9 ), + .O(\blk00000003/blk00000004/sig000011ce ) + ); + LUT4 #( + .INIT ( 16'h0511 )) + \blk00000003/blk00000004/blk000019a5 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00002031 ), + .I2(\blk00000003/blk00000004/sig00002032 ), + .I3(\blk00000003/blk00000004/sig000011c9 ), + .O(\blk00000003/blk00000004/sig000011d0 ) + ); + LUT4 #( + .INIT ( 16'h0511 )) + \blk00000003/blk00000004/blk000019a4 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig0000202f ), + .I2(\blk00000003/blk00000004/sig00002030 ), + .I3(\blk00000003/blk00000004/sig000011c9 ), + .O(\blk00000003/blk00000004/sig000011d2 ) + ); + LUT4 #( + .INIT ( 16'h0511 )) + \blk00000003/blk00000004/blk000019a3 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig0000202d ), + .I2(\blk00000003/blk00000004/sig0000202e ), + .I3(\blk00000003/blk00000004/sig000011c9 ), + .O(\blk00000003/blk00000004/sig000011d4 ) + ); + LUT4 #( + .INIT ( 16'h0511 )) + \blk00000003/blk00000004/blk000019a2 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig0000202b ), + .I2(\blk00000003/blk00000004/sig0000202c ), + .I3(\blk00000003/blk00000004/sig0000117f ), + .O(\blk00000003/blk00000004/sig00001180 ) + ); + LUT4 #( + .INIT ( 16'h0511 )) + \blk00000003/blk00000004/blk000019a1 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00002029 ), + .I2(\blk00000003/blk00000004/sig0000202a ), + .I3(\blk00000003/blk00000004/sig0000117f ), + .O(\blk00000003/blk00000004/sig00001182 ) + ); + LUT4 #( + .INIT ( 16'h0511 )) + \blk00000003/blk00000004/blk000019a0 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00002027 ), + .I2(\blk00000003/blk00000004/sig00002028 ), + .I3(\blk00000003/blk00000004/sig0000117f ), + .O(\blk00000003/blk00000004/sig00001184 ) + ); + LUT4 #( + .INIT ( 16'h0511 )) + \blk00000003/blk00000004/blk0000199f ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00002025 ), + .I2(\blk00000003/blk00000004/sig00002026 ), + .I3(\blk00000003/blk00000004/sig0000117f ), + .O(\blk00000003/blk00000004/sig00001186 ) + ); + LUT4 #( + .INIT ( 16'h0511 )) + \blk00000003/blk00000004/blk0000199e ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00002023 ), + .I2(\blk00000003/blk00000004/sig00002024 ), + .I3(\blk00000003/blk00000004/sig0000117f ), + .O(\blk00000003/blk00000004/sig00001188 ) + ); + LUT4 #( + .INIT ( 16'h0511 )) + \blk00000003/blk00000004/blk0000199d ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00002021 ), + .I2(\blk00000003/blk00000004/sig00002022 ), + .I3(\blk00000003/blk00000004/sig0000117f ), + .O(\blk00000003/blk00000004/sig0000118a ) + ); + LUT4 #( + .INIT ( 16'h0511 )) + \blk00000003/blk00000004/blk0000199c ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig0000201f ), + .I2(\blk00000003/blk00000004/sig00002020 ), + .I3(\blk00000003/blk00000004/sig0000194d ), + .O(\blk00000003/blk00000004/sig0000194e ) + ); + LUT4 #( + .INIT ( 16'h0511 )) + \blk00000003/blk00000004/blk0000199b ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig0000201d ), + .I2(\blk00000003/blk00000004/sig0000201e ), + .I3(\blk00000003/blk00000004/sig0000194d ), + .O(\blk00000003/blk00000004/sig00001950 ) + ); + LUT4 #( + .INIT ( 16'h0511 )) + \blk00000003/blk00000004/blk0000199a ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig0000201b ), + .I2(\blk00000003/blk00000004/sig0000201c ), + .I3(\blk00000003/blk00000004/sig0000194d ), + .O(\blk00000003/blk00000004/sig00001952 ) + ); + LUT4 #( + .INIT ( 16'h0511 )) + \blk00000003/blk00000004/blk00001999 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00002019 ), + .I2(\blk00000003/blk00000004/sig0000201a ), + .I3(\blk00000003/blk00000004/sig0000194d ), + .O(\blk00000003/blk00000004/sig00001954 ) + ); + LUT4 #( + .INIT ( 16'h0511 )) + \blk00000003/blk00000004/blk00001998 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00002017 ), + .I2(\blk00000003/blk00000004/sig00002018 ), + .I3(\blk00000003/blk00000004/sig0000194d ), + .O(\blk00000003/blk00000004/sig00001956 ) + ); + LUT4 #( + .INIT ( 16'h0511 )) + \blk00000003/blk00000004/blk00001997 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00002015 ), + .I2(\blk00000003/blk00000004/sig00002016 ), + .I3(\blk00000003/blk00000004/sig0000194d ), + .O(\blk00000003/blk00000004/sig00001958 ) + ); + LUT4 #( + .INIT ( 16'h0511 )) + \blk00000003/blk00000004/blk00001996 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00002013 ), + .I2(\blk00000003/blk00000004/sig00002014 ), + .I3(\blk00000003/blk00000004/sig00001135 ), + .O(\blk00000003/blk00000004/sig00001136 ) + ); + LUT4 #( + .INIT ( 16'h0511 )) + \blk00000003/blk00000004/blk00001995 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00002011 ), + .I2(\blk00000003/blk00000004/sig00002012 ), + .I3(\blk00000003/blk00000004/sig00001135 ), + .O(\blk00000003/blk00000004/sig00001138 ) + ); + LUT4 #( + .INIT ( 16'h0511 )) + \blk00000003/blk00000004/blk00001994 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig0000200f ), + .I2(\blk00000003/blk00000004/sig00002010 ), + .I3(\blk00000003/blk00000004/sig00001135 ), + .O(\blk00000003/blk00000004/sig0000113a ) + ); + LUT4 #( + .INIT ( 16'h0511 )) + \blk00000003/blk00000004/blk00001993 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig0000200d ), + .I2(\blk00000003/blk00000004/sig0000200e ), + .I3(\blk00000003/blk00000004/sig00001135 ), + .O(\blk00000003/blk00000004/sig0000113c ) + ); + LUT4 #( + .INIT ( 16'h0511 )) + \blk00000003/blk00000004/blk00001992 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig0000200b ), + .I2(\blk00000003/blk00000004/sig0000200c ), + .I3(\blk00000003/blk00000004/sig00001135 ), + .O(\blk00000003/blk00000004/sig0000113e ) + ); + LUT4 #( + .INIT ( 16'h0511 )) + \blk00000003/blk00000004/blk00001991 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00002009 ), + .I2(\blk00000003/blk00000004/sig0000200a ), + .I3(\blk00000003/blk00000004/sig00001135 ), + .O(\blk00000003/blk00000004/sig00001140 ) + ); + LUT4 #( + .INIT ( 16'h0511 )) + \blk00000003/blk00000004/blk00001990 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00002007 ), + .I2(\blk00000003/blk00000004/sig00002008 ), + .I3(\blk00000003/blk00000004/sig000010eb ), + .O(\blk00000003/blk00000004/sig000010ec ) + ); + LUT4 #( + .INIT ( 16'h0511 )) + \blk00000003/blk00000004/blk0000198f ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00002005 ), + .I2(\blk00000003/blk00000004/sig00002006 ), + .I3(\blk00000003/blk00000004/sig000010eb ), + .O(\blk00000003/blk00000004/sig000010ee ) + ); + LUT4 #( + .INIT ( 16'h0511 )) + \blk00000003/blk00000004/blk0000198e ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00002003 ), + .I2(\blk00000003/blk00000004/sig00002004 ), + .I3(\blk00000003/blk00000004/sig000010eb ), + .O(\blk00000003/blk00000004/sig000010f0 ) + ); + LUT4 #( + .INIT ( 16'h0511 )) + \blk00000003/blk00000004/blk0000198d ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00002001 ), + .I2(\blk00000003/blk00000004/sig00002002 ), + .I3(\blk00000003/blk00000004/sig000010eb ), + .O(\blk00000003/blk00000004/sig000010f2 ) + ); + LUT4 #( + .INIT ( 16'h0511 )) + \blk00000003/blk00000004/blk0000198c ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00001fff ), + .I2(\blk00000003/blk00000004/sig00002000 ), + .I3(\blk00000003/blk00000004/sig000010eb ), + .O(\blk00000003/blk00000004/sig000010f4 ) + ); + LUT4 #( + .INIT ( 16'h0511 )) + \blk00000003/blk00000004/blk0000198b ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00001ffd ), + .I2(\blk00000003/blk00000004/sig00001ffe ), + .I3(\blk00000003/blk00000004/sig000010eb ), + .O(\blk00000003/blk00000004/sig000010f6 ) + ); + LUT4 #( + .INIT ( 16'h0511 )) + \blk00000003/blk00000004/blk0000198a ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00001ffb ), + .I2(\blk00000003/blk00000004/sig00001ffc ), + .I3(\blk00000003/blk00000004/sig000010a1 ), + .O(\blk00000003/blk00000004/sig000010a2 ) + ); + LUT4 #( + .INIT ( 16'h0511 )) + \blk00000003/blk00000004/blk00001989 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00001ff9 ), + .I2(\blk00000003/blk00000004/sig00001ffa ), + .I3(\blk00000003/blk00000004/sig000010a1 ), + .O(\blk00000003/blk00000004/sig000010a4 ) + ); + LUT4 #( + .INIT ( 16'h0511 )) + \blk00000003/blk00000004/blk00001988 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00001ff7 ), + .I2(\blk00000003/blk00000004/sig00001ff8 ), + .I3(\blk00000003/blk00000004/sig000010a1 ), + .O(\blk00000003/blk00000004/sig000010a6 ) + ); + LUT4 #( + .INIT ( 16'h0511 )) + \blk00000003/blk00000004/blk00001987 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00001ff5 ), + .I2(\blk00000003/blk00000004/sig00001ff6 ), + .I3(\blk00000003/blk00000004/sig000010a1 ), + .O(\blk00000003/blk00000004/sig000010a8 ) + ); + LUT4 #( + .INIT ( 16'h0511 )) + \blk00000003/blk00000004/blk00001986 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00001ff3 ), + .I2(\blk00000003/blk00000004/sig00001ff4 ), + .I3(\blk00000003/blk00000004/sig000010a1 ), + .O(\blk00000003/blk00000004/sig000010aa ) + ); + LUT4 #( + .INIT ( 16'h0511 )) + \blk00000003/blk00000004/blk00001985 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00001ff1 ), + .I2(\blk00000003/blk00000004/sig00001ff2 ), + .I3(\blk00000003/blk00000004/sig000010a1 ), + .O(\blk00000003/blk00000004/sig000010ac ) + ); + LUT4 #( + .INIT ( 16'h0511 )) + \blk00000003/blk00000004/blk00001984 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00001fef ), + .I2(\blk00000003/blk00000004/sig00001ff0 ), + .I3(\blk00000003/blk00000004/sig00001057 ), + .O(\blk00000003/blk00000004/sig00001058 ) + ); + LUT4 #( + .INIT ( 16'h0511 )) + \blk00000003/blk00000004/blk00001983 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00001fed ), + .I2(\blk00000003/blk00000004/sig00001fee ), + .I3(\blk00000003/blk00000004/sig00001057 ), + .O(\blk00000003/blk00000004/sig0000105a ) + ); + LUT4 #( + .INIT ( 16'h0511 )) + \blk00000003/blk00000004/blk00001982 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00001feb ), + .I2(\blk00000003/blk00000004/sig00001fec ), + .I3(\blk00000003/blk00000004/sig00001057 ), + .O(\blk00000003/blk00000004/sig0000105c ) + ); + LUT4 #( + .INIT ( 16'h0511 )) + \blk00000003/blk00000004/blk00001981 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00001fe9 ), + .I2(\blk00000003/blk00000004/sig00001fea ), + .I3(\blk00000003/blk00000004/sig00001057 ), + .O(\blk00000003/blk00000004/sig0000105e ) + ); + LUT4 #( + .INIT ( 16'h0511 )) + \blk00000003/blk00000004/blk00001980 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00001fe7 ), + .I2(\blk00000003/blk00000004/sig00001fe8 ), + .I3(\blk00000003/blk00000004/sig00001057 ), + .O(\blk00000003/blk00000004/sig00001060 ) + ); + LUT4 #( + .INIT ( 16'h0511 )) + \blk00000003/blk00000004/blk0000197f ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00001fe5 ), + .I2(\blk00000003/blk00000004/sig00001fe6 ), + .I3(\blk00000003/blk00000004/sig00001057 ), + .O(\blk00000003/blk00000004/sig00001062 ) + ); + LUT4 #( + .INIT ( 16'h0511 )) + \blk00000003/blk00000004/blk0000197e ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00001fe3 ), + .I2(\blk00000003/blk00000004/sig00001fe4 ), + .I3(\blk00000003/blk00000004/sig0000100d ), + .O(\blk00000003/blk00000004/sig0000100e ) + ); + LUT4 #( + .INIT ( 16'h0511 )) + \blk00000003/blk00000004/blk0000197d ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00001fe1 ), + .I2(\blk00000003/blk00000004/sig00001fe2 ), + .I3(\blk00000003/blk00000004/sig0000100d ), + .O(\blk00000003/blk00000004/sig00001010 ) + ); + LUT4 #( + .INIT ( 16'h0511 )) + \blk00000003/blk00000004/blk0000197c ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00001fdf ), + .I2(\blk00000003/blk00000004/sig00001fe0 ), + .I3(\blk00000003/blk00000004/sig0000100d ), + .O(\blk00000003/blk00000004/sig00001012 ) + ); + LUT4 #( + .INIT ( 16'h0511 )) + \blk00000003/blk00000004/blk0000197b ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00001fdd ), + .I2(\blk00000003/blk00000004/sig00001fde ), + .I3(\blk00000003/blk00000004/sig0000100d ), + .O(\blk00000003/blk00000004/sig00001014 ) + ); + LUT4 #( + .INIT ( 16'h0511 )) + \blk00000003/blk00000004/blk0000197a ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00001fdb ), + .I2(\blk00000003/blk00000004/sig00001fdc ), + .I3(\blk00000003/blk00000004/sig0000100d ), + .O(\blk00000003/blk00000004/sig00001016 ) + ); + LUT4 #( + .INIT ( 16'h0511 )) + \blk00000003/blk00000004/blk00001979 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00001fd9 ), + .I2(\blk00000003/blk00000004/sig00001fda ), + .I3(\blk00000003/blk00000004/sig0000100d ), + .O(\blk00000003/blk00000004/sig00001018 ) + ); + LUT4 #( + .INIT ( 16'h0511 )) + \blk00000003/blk00000004/blk00001978 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00001fd7 ), + .I2(\blk00000003/blk00000004/sig00001fd8 ), + .I3(\blk00000003/blk00000004/sig00000fc3 ), + .O(\blk00000003/blk00000004/sig00000fc4 ) + ); + LUT4 #( + .INIT ( 16'h0511 )) + \blk00000003/blk00000004/blk00001977 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00001fd5 ), + .I2(\blk00000003/blk00000004/sig00001fd6 ), + .I3(\blk00000003/blk00000004/sig00000fc3 ), + .O(\blk00000003/blk00000004/sig00000fc6 ) + ); + LUT4 #( + .INIT ( 16'h0511 )) + \blk00000003/blk00000004/blk00001976 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00001fd3 ), + .I2(\blk00000003/blk00000004/sig00001fd4 ), + .I3(\blk00000003/blk00000004/sig00000fc3 ), + .O(\blk00000003/blk00000004/sig00000fc8 ) + ); + LUT4 #( + .INIT ( 16'h0511 )) + \blk00000003/blk00000004/blk00001975 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00001fd1 ), + .I2(\blk00000003/blk00000004/sig00001fd2 ), + .I3(\blk00000003/blk00000004/sig00000fc3 ), + .O(\blk00000003/blk00000004/sig00000fca ) + ); + LUT4 #( + .INIT ( 16'h0511 )) + \blk00000003/blk00000004/blk00001974 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00001fcf ), + .I2(\blk00000003/blk00000004/sig00001fd0 ), + .I3(\blk00000003/blk00000004/sig00000fc3 ), + .O(\blk00000003/blk00000004/sig00000fcc ) + ); + LUT4 #( + .INIT ( 16'h0511 )) + \blk00000003/blk00000004/blk00001973 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00001fcd ), + .I2(\blk00000003/blk00000004/sig00001fce ), + .I3(\blk00000003/blk00000004/sig00000fc3 ), + .O(\blk00000003/blk00000004/sig00000fce ) + ); + LUT4 #( + .INIT ( 16'h0511 )) + \blk00000003/blk00000004/blk00001972 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00001fcb ), + .I2(\blk00000003/blk00000004/sig00001fcc ), + .I3(\blk00000003/blk00000004/sig00000f79 ), + .O(\blk00000003/blk00000004/sig00000f7a ) + ); + LUT4 #( + .INIT ( 16'h0511 )) + \blk00000003/blk00000004/blk00001971 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00001fc9 ), + .I2(\blk00000003/blk00000004/sig00001fca ), + .I3(\blk00000003/blk00000004/sig00000f79 ), + .O(\blk00000003/blk00000004/sig00000f7c ) + ); + LUT4 #( + .INIT ( 16'h0511 )) + \blk00000003/blk00000004/blk00001970 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00001fc7 ), + .I2(\blk00000003/blk00000004/sig00001fc8 ), + .I3(\blk00000003/blk00000004/sig00000f79 ), + .O(\blk00000003/blk00000004/sig00000f7e ) + ); + LUT4 #( + .INIT ( 16'h0511 )) + \blk00000003/blk00000004/blk0000196f ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00001fc5 ), + .I2(\blk00000003/blk00000004/sig00001fc6 ), + .I3(\blk00000003/blk00000004/sig00000f79 ), + .O(\blk00000003/blk00000004/sig00000f80 ) + ); + LUT4 #( + .INIT ( 16'h0511 )) + \blk00000003/blk00000004/blk0000196e ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00001fc3 ), + .I2(\blk00000003/blk00000004/sig00001fc4 ), + .I3(\blk00000003/blk00000004/sig00000f79 ), + .O(\blk00000003/blk00000004/sig00000f82 ) + ); + LUT4 #( + .INIT ( 16'h0511 )) + \blk00000003/blk00000004/blk0000196d ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00001fc1 ), + .I2(\blk00000003/blk00000004/sig00001fc2 ), + .I3(\blk00000003/blk00000004/sig00000f79 ), + .O(\blk00000003/blk00000004/sig00000f84 ) + ); + LUT4 #( + .INIT ( 16'h0511 )) + \blk00000003/blk00000004/blk0000196c ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00001fbf ), + .I2(\blk00000003/blk00000004/sig00001fc0 ), + .I3(\blk00000003/blk00000004/sig00000f2f ), + .O(\blk00000003/blk00000004/sig00000f30 ) + ); + LUT4 #( + .INIT ( 16'h0511 )) + \blk00000003/blk00000004/blk0000196b ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00001fbd ), + .I2(\blk00000003/blk00000004/sig00001fbe ), + .I3(\blk00000003/blk00000004/sig00000f2f ), + .O(\blk00000003/blk00000004/sig00000f32 ) + ); + LUT4 #( + .INIT ( 16'h0511 )) + \blk00000003/blk00000004/blk0000196a ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00001fbb ), + .I2(\blk00000003/blk00000004/sig00001fbc ), + .I3(\blk00000003/blk00000004/sig00000f2f ), + .O(\blk00000003/blk00000004/sig00000f34 ) + ); + LUT4 #( + .INIT ( 16'h0511 )) + \blk00000003/blk00000004/blk00001969 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00001fb9 ), + .I2(\blk00000003/blk00000004/sig00001fba ), + .I3(\blk00000003/blk00000004/sig00000f2f ), + .O(\blk00000003/blk00000004/sig00000f36 ) + ); + LUT4 #( + .INIT ( 16'h0511 )) + \blk00000003/blk00000004/blk00001968 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00001fb7 ), + .I2(\blk00000003/blk00000004/sig00001fb8 ), + .I3(\blk00000003/blk00000004/sig00000f2f ), + .O(\blk00000003/blk00000004/sig00000f38 ) + ); + LUT4 #( + .INIT ( 16'h0511 )) + \blk00000003/blk00000004/blk00001967 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00001fb5 ), + .I2(\blk00000003/blk00000004/sig00001fb6 ), + .I3(\blk00000003/blk00000004/sig00000f2f ), + .O(\blk00000003/blk00000004/sig00000f3a ) + ); + LUT4 #( + .INIT ( 16'h0511 )) + \blk00000003/blk00000004/blk00001966 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00001fb3 ), + .I2(\blk00000003/blk00000004/sig00001fb4 ), + .I3(\blk00000003/blk00000004/sig00000ee5 ), + .O(\blk00000003/blk00000004/sig00000ee6 ) + ); + LUT4 #( + .INIT ( 16'h0511 )) + \blk00000003/blk00000004/blk00001965 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00001fb1 ), + .I2(\blk00000003/blk00000004/sig00001fb2 ), + .I3(\blk00000003/blk00000004/sig00000ee5 ), + .O(\blk00000003/blk00000004/sig00000ee8 ) + ); + LUT4 #( + .INIT ( 16'h0511 )) + \blk00000003/blk00000004/blk00001964 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00001faf ), + .I2(\blk00000003/blk00000004/sig00001fb0 ), + .I3(\blk00000003/blk00000004/sig00000ee5 ), + .O(\blk00000003/blk00000004/sig00000eea ) + ); + LUT4 #( + .INIT ( 16'h0511 )) + \blk00000003/blk00000004/blk00001963 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00001fad ), + .I2(\blk00000003/blk00000004/sig00001fae ), + .I3(\blk00000003/blk00000004/sig00000ee5 ), + .O(\blk00000003/blk00000004/sig00000eec ) + ); + LUT4 #( + .INIT ( 16'h0511 )) + \blk00000003/blk00000004/blk00001962 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00001fab ), + .I2(\blk00000003/blk00000004/sig00001fac ), + .I3(\blk00000003/blk00000004/sig00000ee5 ), + .O(\blk00000003/blk00000004/sig00000eee ) + ); + LUT4 #( + .INIT ( 16'h0511 )) + \blk00000003/blk00000004/blk00001961 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00001fa9 ), + .I2(\blk00000003/blk00000004/sig00001faa ), + .I3(\blk00000003/blk00000004/sig00000ee5 ), + .O(\blk00000003/blk00000004/sig00000ef0 ) + ); + LUT4 #( + .INIT ( 16'h0511 )) + \blk00000003/blk00000004/blk00001960 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00001fa7 ), + .I2(\blk00000003/blk00000004/sig00001fa8 ), + .I3(\blk00000003/blk00000004/sig00000e9b ), + .O(\blk00000003/blk00000004/sig00000e9c ) + ); + LUT4 #( + .INIT ( 16'h0511 )) + \blk00000003/blk00000004/blk0000195f ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00001fa5 ), + .I2(\blk00000003/blk00000004/sig00001fa6 ), + .I3(\blk00000003/blk00000004/sig00000e9b ), + .O(\blk00000003/blk00000004/sig00000e9e ) + ); + LUT4 #( + .INIT ( 16'h0511 )) + \blk00000003/blk00000004/blk0000195e ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00001fa3 ), + .I2(\blk00000003/blk00000004/sig00001fa4 ), + .I3(\blk00000003/blk00000004/sig00000e9b ), + .O(\blk00000003/blk00000004/sig00000ea0 ) + ); + LUT4 #( + .INIT ( 16'h0511 )) + \blk00000003/blk00000004/blk0000195d ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00001fa1 ), + .I2(\blk00000003/blk00000004/sig00001fa2 ), + .I3(\blk00000003/blk00000004/sig00000e9b ), + .O(\blk00000003/blk00000004/sig00000ea2 ) + ); + LUT4 #( + .INIT ( 16'h0511 )) + \blk00000003/blk00000004/blk0000195c ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00001f9f ), + .I2(\blk00000003/blk00000004/sig00001fa0 ), + .I3(\blk00000003/blk00000004/sig00000e9b ), + .O(\blk00000003/blk00000004/sig00000ea4 ) + ); + LUT4 #( + .INIT ( 16'h0511 )) + \blk00000003/blk00000004/blk0000195b ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00001f9d ), + .I2(\blk00000003/blk00000004/sig00001f9e ), + .I3(\blk00000003/blk00000004/sig00000e9b ), + .O(\blk00000003/blk00000004/sig00000ea6 ) + ); + LUT4 #( + .INIT ( 16'h0511 )) + \blk00000003/blk00000004/blk0000195a ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00001f9b ), + .I2(\blk00000003/blk00000004/sig00001f9c ), + .I3(\blk00000003/blk00000004/sig00001903 ), + .O(\blk00000003/blk00000004/sig00001904 ) + ); + LUT4 #( + .INIT ( 16'h0511 )) + \blk00000003/blk00000004/blk00001959 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00001f99 ), + .I2(\blk00000003/blk00000004/sig00001f9a ), + .I3(\blk00000003/blk00000004/sig00001903 ), + .O(\blk00000003/blk00000004/sig00001906 ) + ); + LUT4 #( + .INIT ( 16'h0511 )) + \blk00000003/blk00000004/blk00001958 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00001f97 ), + .I2(\blk00000003/blk00000004/sig00001f98 ), + .I3(\blk00000003/blk00000004/sig00001903 ), + .O(\blk00000003/blk00000004/sig00001908 ) + ); + LUT4 #( + .INIT ( 16'h0511 )) + \blk00000003/blk00000004/blk00001957 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00001f95 ), + .I2(\blk00000003/blk00000004/sig00001f96 ), + .I3(\blk00000003/blk00000004/sig00001903 ), + .O(\blk00000003/blk00000004/sig0000190a ) + ); + LUT4 #( + .INIT ( 16'h0511 )) + \blk00000003/blk00000004/blk00001956 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00001f93 ), + .I2(\blk00000003/blk00000004/sig00001f94 ), + .I3(\blk00000003/blk00000004/sig00001903 ), + .O(\blk00000003/blk00000004/sig0000190c ) + ); + LUT4 #( + .INIT ( 16'h0511 )) + \blk00000003/blk00000004/blk00001955 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00001f91 ), + .I2(\blk00000003/blk00000004/sig00001f92 ), + .I3(\blk00000003/blk00000004/sig00001903 ), + .O(\blk00000003/blk00000004/sig0000190e ) + ); + LUT4 #( + .INIT ( 16'h0511 )) + \blk00000003/blk00000004/blk00001954 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00001f8f ), + .I2(\blk00000003/blk00000004/sig00001f90 ), + .I3(\blk00000003/blk00000004/sig00000e51 ), + .O(\blk00000003/blk00000004/sig00000e52 ) + ); + LUT4 #( + .INIT ( 16'h0511 )) + \blk00000003/blk00000004/blk00001953 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00001f8d ), + .I2(\blk00000003/blk00000004/sig00001f8e ), + .I3(\blk00000003/blk00000004/sig00000e51 ), + .O(\blk00000003/blk00000004/sig00000e54 ) + ); + LUT4 #( + .INIT ( 16'h0511 )) + \blk00000003/blk00000004/blk00001952 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00001f8b ), + .I2(\blk00000003/blk00000004/sig00001f8c ), + .I3(\blk00000003/blk00000004/sig00000e51 ), + .O(\blk00000003/blk00000004/sig00000e56 ) + ); + LUT4 #( + .INIT ( 16'h0511 )) + \blk00000003/blk00000004/blk00001951 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00001f89 ), + .I2(\blk00000003/blk00000004/sig00001f8a ), + .I3(\blk00000003/blk00000004/sig00000e51 ), + .O(\blk00000003/blk00000004/sig00000e58 ) + ); + LUT4 #( + .INIT ( 16'h0511 )) + \blk00000003/blk00000004/blk00001950 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00001f87 ), + .I2(\blk00000003/blk00000004/sig00001f88 ), + .I3(\blk00000003/blk00000004/sig00000e51 ), + .O(\blk00000003/blk00000004/sig00000e5a ) + ); + LUT4 #( + .INIT ( 16'h0511 )) + \blk00000003/blk00000004/blk0000194f ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00001f85 ), + .I2(\blk00000003/blk00000004/sig00001f86 ), + .I3(\blk00000003/blk00000004/sig00000e51 ), + .O(\blk00000003/blk00000004/sig00000e5c ) + ); + LUT4 #( + .INIT ( 16'h0511 )) + \blk00000003/blk00000004/blk0000194e ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00001f83 ), + .I2(\blk00000003/blk00000004/sig00001f84 ), + .I3(\blk00000003/blk00000004/sig00000e07 ), + .O(\blk00000003/blk00000004/sig00000e08 ) + ); + LUT4 #( + .INIT ( 16'h0511 )) + \blk00000003/blk00000004/blk0000194d ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00001f81 ), + .I2(\blk00000003/blk00000004/sig00001f82 ), + .I3(\blk00000003/blk00000004/sig00000e07 ), + .O(\blk00000003/blk00000004/sig00000e0a ) + ); + LUT4 #( + .INIT ( 16'h0511 )) + \blk00000003/blk00000004/blk0000194c ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00001f7f ), + .I2(\blk00000003/blk00000004/sig00001f80 ), + .I3(\blk00000003/blk00000004/sig00000e07 ), + .O(\blk00000003/blk00000004/sig00000e0c ) + ); + LUT4 #( + .INIT ( 16'h0511 )) + \blk00000003/blk00000004/blk0000194b ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00001f7d ), + .I2(\blk00000003/blk00000004/sig00001f7e ), + .I3(\blk00000003/blk00000004/sig00000e07 ), + .O(\blk00000003/blk00000004/sig00000e0e ) + ); + LUT4 #( + .INIT ( 16'h0511 )) + \blk00000003/blk00000004/blk0000194a ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00001f7b ), + .I2(\blk00000003/blk00000004/sig00001f7c ), + .I3(\blk00000003/blk00000004/sig00000e07 ), + .O(\blk00000003/blk00000004/sig00000e10 ) + ); + LUT4 #( + .INIT ( 16'h0511 )) + \blk00000003/blk00000004/blk00001949 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00001f79 ), + .I2(\blk00000003/blk00000004/sig00001f7a ), + .I3(\blk00000003/blk00000004/sig00000e07 ), + .O(\blk00000003/blk00000004/sig00000e12 ) + ); + LUT4 #( + .INIT ( 16'h0511 )) + \blk00000003/blk00000004/blk00001948 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00001f77 ), + .I2(\blk00000003/blk00000004/sig00001f78 ), + .I3(\blk00000003/blk00000004/sig00000dbd ), + .O(\blk00000003/blk00000004/sig00000dbe ) + ); + LUT4 #( + .INIT ( 16'h0511 )) + \blk00000003/blk00000004/blk00001947 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00001f75 ), + .I2(\blk00000003/blk00000004/sig00001f76 ), + .I3(\blk00000003/blk00000004/sig00000dbd ), + .O(\blk00000003/blk00000004/sig00000dc0 ) + ); + LUT4 #( + .INIT ( 16'h0511 )) + \blk00000003/blk00000004/blk00001946 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00001f73 ), + .I2(\blk00000003/blk00000004/sig00001f74 ), + .I3(\blk00000003/blk00000004/sig00000dbd ), + .O(\blk00000003/blk00000004/sig00000dc2 ) + ); + LUT4 #( + .INIT ( 16'h0511 )) + \blk00000003/blk00000004/blk00001945 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00001f71 ), + .I2(\blk00000003/blk00000004/sig00001f72 ), + .I3(\blk00000003/blk00000004/sig00000dbd ), + .O(\blk00000003/blk00000004/sig00000dc4 ) + ); + LUT4 #( + .INIT ( 16'h0511 )) + \blk00000003/blk00000004/blk00001944 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00001f6f ), + .I2(\blk00000003/blk00000004/sig00001f70 ), + .I3(\blk00000003/blk00000004/sig00000dbd ), + .O(\blk00000003/blk00000004/sig00000dc6 ) + ); + LUT4 #( + .INIT ( 16'h0511 )) + \blk00000003/blk00000004/blk00001943 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00001f6d ), + .I2(\blk00000003/blk00000004/sig00001f6e ), + .I3(\blk00000003/blk00000004/sig00000dbd ), + .O(\blk00000003/blk00000004/sig00000dc8 ) + ); + LUT4 #( + .INIT ( 16'h0511 )) + \blk00000003/blk00000004/blk00001942 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00001f6b ), + .I2(\blk00000003/blk00000004/sig00001f6c ), + .I3(\blk00000003/blk00000004/sig00000d73 ), + .O(\blk00000003/blk00000004/sig00000d74 ) + ); + LUT4 #( + .INIT ( 16'h0511 )) + \blk00000003/blk00000004/blk00001941 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00001f69 ), + .I2(\blk00000003/blk00000004/sig00001f6a ), + .I3(\blk00000003/blk00000004/sig00000d73 ), + .O(\blk00000003/blk00000004/sig00000d76 ) + ); + LUT4 #( + .INIT ( 16'h0511 )) + \blk00000003/blk00000004/blk00001940 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00001f67 ), + .I2(\blk00000003/blk00000004/sig00001f68 ), + .I3(\blk00000003/blk00000004/sig00000d73 ), + .O(\blk00000003/blk00000004/sig00000d78 ) + ); + LUT4 #( + .INIT ( 16'h0511 )) + \blk00000003/blk00000004/blk0000193f ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00001f65 ), + .I2(\blk00000003/blk00000004/sig00001f66 ), + .I3(\blk00000003/blk00000004/sig00000d73 ), + .O(\blk00000003/blk00000004/sig00000d7a ) + ); + LUT4 #( + .INIT ( 16'h0511 )) + \blk00000003/blk00000004/blk0000193e ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00001f63 ), + .I2(\blk00000003/blk00000004/sig00001f64 ), + .I3(\blk00000003/blk00000004/sig00000d73 ), + .O(\blk00000003/blk00000004/sig00000d7c ) + ); + LUT4 #( + .INIT ( 16'h0511 )) + \blk00000003/blk00000004/blk0000193d ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00001f61 ), + .I2(\blk00000003/blk00000004/sig00001f62 ), + .I3(\blk00000003/blk00000004/sig00000d73 ), + .O(\blk00000003/blk00000004/sig00000d7e ) + ); + LUT4 #( + .INIT ( 16'h0511 )) + \blk00000003/blk00000004/blk0000193c ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00001f5f ), + .I2(\blk00000003/blk00000004/sig00001f60 ), + .I3(\blk00000003/blk00000004/sig00000d29 ), + .O(\blk00000003/blk00000004/sig00000d2a ) + ); + LUT4 #( + .INIT ( 16'h0511 )) + \blk00000003/blk00000004/blk0000193b ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00001f5d ), + .I2(\blk00000003/blk00000004/sig00001f5e ), + .I3(\blk00000003/blk00000004/sig00000d29 ), + .O(\blk00000003/blk00000004/sig00000d2c ) + ); + LUT4 #( + .INIT ( 16'h0511 )) + \blk00000003/blk00000004/blk0000193a ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00001f5b ), + .I2(\blk00000003/blk00000004/sig00001f5c ), + .I3(\blk00000003/blk00000004/sig00000d29 ), + .O(\blk00000003/blk00000004/sig00000d2e ) + ); + LUT4 #( + .INIT ( 16'h0511 )) + \blk00000003/blk00000004/blk00001939 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00001f59 ), + .I2(\blk00000003/blk00000004/sig00001f5a ), + .I3(\blk00000003/blk00000004/sig00000d29 ), + .O(\blk00000003/blk00000004/sig00000d30 ) + ); + LUT4 #( + .INIT ( 16'h0511 )) + \blk00000003/blk00000004/blk00001938 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00001f57 ), + .I2(\blk00000003/blk00000004/sig00001f58 ), + .I3(\blk00000003/blk00000004/sig00000d29 ), + .O(\blk00000003/blk00000004/sig00000d32 ) + ); + LUT4 #( + .INIT ( 16'h0511 )) + \blk00000003/blk00000004/blk00001937 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00001f55 ), + .I2(\blk00000003/blk00000004/sig00001f56 ), + .I3(\blk00000003/blk00000004/sig00000d29 ), + .O(\blk00000003/blk00000004/sig00000d34 ) + ); + LUT4 #( + .INIT ( 16'h0511 )) + \blk00000003/blk00000004/blk00001936 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00001f53 ), + .I2(\blk00000003/blk00000004/sig00001f54 ), + .I3(\blk00000003/blk00000004/sig00000cdf ), + .O(\blk00000003/blk00000004/sig00000ce0 ) + ); + LUT4 #( + .INIT ( 16'h0511 )) + \blk00000003/blk00000004/blk00001935 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00001f51 ), + .I2(\blk00000003/blk00000004/sig00001f52 ), + .I3(\blk00000003/blk00000004/sig00000cdf ), + .O(\blk00000003/blk00000004/sig00000ce2 ) + ); + LUT4 #( + .INIT ( 16'h0511 )) + \blk00000003/blk00000004/blk00001934 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00001f4f ), + .I2(\blk00000003/blk00000004/sig00001f50 ), + .I3(\blk00000003/blk00000004/sig00000cdf ), + .O(\blk00000003/blk00000004/sig00000ce4 ) + ); + LUT4 #( + .INIT ( 16'h0511 )) + \blk00000003/blk00000004/blk00001933 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00001f4d ), + .I2(\blk00000003/blk00000004/sig00001f4e ), + .I3(\blk00000003/blk00000004/sig00000cdf ), + .O(\blk00000003/blk00000004/sig00000ce6 ) + ); + LUT4 #( + .INIT ( 16'h0511 )) + \blk00000003/blk00000004/blk00001932 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00001f4b ), + .I2(\blk00000003/blk00000004/sig00001f4c ), + .I3(\blk00000003/blk00000004/sig00000cdf ), + .O(\blk00000003/blk00000004/sig00000ce8 ) + ); + LUT4 #( + .INIT ( 16'h0511 )) + \blk00000003/blk00000004/blk00001931 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00001f49 ), + .I2(\blk00000003/blk00000004/sig00001f4a ), + .I3(\blk00000003/blk00000004/sig00000cdf ), + .O(\blk00000003/blk00000004/sig00000cea ) + ); + LUT4 #( + .INIT ( 16'h0511 )) + \blk00000003/blk00000004/blk00001930 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00001f47 ), + .I2(\blk00000003/blk00000004/sig00001f48 ), + .I3(\blk00000003/blk00000004/sig00000c95 ), + .O(\blk00000003/blk00000004/sig00000c96 ) + ); + LUT4 #( + .INIT ( 16'h0511 )) + \blk00000003/blk00000004/blk0000192f ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00001f45 ), + .I2(\blk00000003/blk00000004/sig00001f46 ), + .I3(\blk00000003/blk00000004/sig00000c95 ), + .O(\blk00000003/blk00000004/sig00000c98 ) + ); + LUT4 #( + .INIT ( 16'h0511 )) + \blk00000003/blk00000004/blk0000192e ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00001f43 ), + .I2(\blk00000003/blk00000004/sig00001f44 ), + .I3(\blk00000003/blk00000004/sig00000c95 ), + .O(\blk00000003/blk00000004/sig00000c9a ) + ); + LUT4 #( + .INIT ( 16'h0511 )) + \blk00000003/blk00000004/blk0000192d ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00001f41 ), + .I2(\blk00000003/blk00000004/sig00001f42 ), + .I3(\blk00000003/blk00000004/sig00000c95 ), + .O(\blk00000003/blk00000004/sig00000c9c ) + ); + LUT4 #( + .INIT ( 16'h0511 )) + \blk00000003/blk00000004/blk0000192c ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00001f3f ), + .I2(\blk00000003/blk00000004/sig00001f40 ), + .I3(\blk00000003/blk00000004/sig00000c95 ), + .O(\blk00000003/blk00000004/sig00000c9e ) + ); + LUT4 #( + .INIT ( 16'h0511 )) + \blk00000003/blk00000004/blk0000192b ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00001f3d ), + .I2(\blk00000003/blk00000004/sig00001f3e ), + .I3(\blk00000003/blk00000004/sig00000c95 ), + .O(\blk00000003/blk00000004/sig00000ca0 ) + ); + LUT4 #( + .INIT ( 16'h0511 )) + \blk00000003/blk00000004/blk0000192a ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00001f3b ), + .I2(\blk00000003/blk00000004/sig00001f3c ), + .I3(\blk00000003/blk00000004/sig00000c4b ), + .O(\blk00000003/blk00000004/sig00000c4c ) + ); + LUT4 #( + .INIT ( 16'h0511 )) + \blk00000003/blk00000004/blk00001929 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00001f39 ), + .I2(\blk00000003/blk00000004/sig00001f3a ), + .I3(\blk00000003/blk00000004/sig00000c4b ), + .O(\blk00000003/blk00000004/sig00000c4e ) + ); + LUT4 #( + .INIT ( 16'h0511 )) + \blk00000003/blk00000004/blk00001928 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00001f37 ), + .I2(\blk00000003/blk00000004/sig00001f38 ), + .I3(\blk00000003/blk00000004/sig00000c4b ), + .O(\blk00000003/blk00000004/sig00000c50 ) + ); + LUT4 #( + .INIT ( 16'h0511 )) + \blk00000003/blk00000004/blk00001927 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00001f35 ), + .I2(\blk00000003/blk00000004/sig00001f36 ), + .I3(\blk00000003/blk00000004/sig00000c4b ), + .O(\blk00000003/blk00000004/sig00000c52 ) + ); + LUT4 #( + .INIT ( 16'h0511 )) + \blk00000003/blk00000004/blk00001926 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00001f33 ), + .I2(\blk00000003/blk00000004/sig00001f34 ), + .I3(\blk00000003/blk00000004/sig00000c4b ), + .O(\blk00000003/blk00000004/sig00000c54 ) + ); + LUT4 #( + .INIT ( 16'h0511 )) + \blk00000003/blk00000004/blk00001925 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00001f31 ), + .I2(\blk00000003/blk00000004/sig00001f32 ), + .I3(\blk00000003/blk00000004/sig00000c4b ), + .O(\blk00000003/blk00000004/sig00000c56 ) + ); + LUT4 #( + .INIT ( 16'h0511 )) + \blk00000003/blk00000004/blk00001924 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00001f2f ), + .I2(\blk00000003/blk00000004/sig00001f30 ), + .I3(\blk00000003/blk00000004/sig00000c01 ), + .O(\blk00000003/blk00000004/sig00000c02 ) + ); + LUT4 #( + .INIT ( 16'h0511 )) + \blk00000003/blk00000004/blk00001923 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00001f2d ), + .I2(\blk00000003/blk00000004/sig00001f2e ), + .I3(\blk00000003/blk00000004/sig00000c01 ), + .O(\blk00000003/blk00000004/sig00000c04 ) + ); + LUT4 #( + .INIT ( 16'h0511 )) + \blk00000003/blk00000004/blk00001922 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00001f2b ), + .I2(\blk00000003/blk00000004/sig00001f2c ), + .I3(\blk00000003/blk00000004/sig00000c01 ), + .O(\blk00000003/blk00000004/sig00000c06 ) + ); + LUT4 #( + .INIT ( 16'h0511 )) + \blk00000003/blk00000004/blk00001921 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00001f29 ), + .I2(\blk00000003/blk00000004/sig00001f2a ), + .I3(\blk00000003/blk00000004/sig00000c01 ), + .O(\blk00000003/blk00000004/sig00000c08 ) + ); + LUT4 #( + .INIT ( 16'h0511 )) + \blk00000003/blk00000004/blk00001920 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00001f27 ), + .I2(\blk00000003/blk00000004/sig00001f28 ), + .I3(\blk00000003/blk00000004/sig00000c01 ), + .O(\blk00000003/blk00000004/sig00000c0a ) + ); + LUT4 #( + .INIT ( 16'h0511 )) + \blk00000003/blk00000004/blk0000191f ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00001f25 ), + .I2(\blk00000003/blk00000004/sig00001f26 ), + .I3(\blk00000003/blk00000004/sig00000c01 ), + .O(\blk00000003/blk00000004/sig00000c0c ) + ); + LUT4 #( + .INIT ( 16'h0511 )) + \blk00000003/blk00000004/blk0000191e ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00001f23 ), + .I2(\blk00000003/blk00000004/sig00001f24 ), + .I3(\blk00000003/blk00000004/sig00000bb7 ), + .O(\blk00000003/blk00000004/sig00000bb8 ) + ); + LUT4 #( + .INIT ( 16'h0511 )) + \blk00000003/blk00000004/blk0000191d ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00001f21 ), + .I2(\blk00000003/blk00000004/sig00001f22 ), + .I3(\blk00000003/blk00000004/sig00000bb7 ), + .O(\blk00000003/blk00000004/sig00000bba ) + ); + LUT4 #( + .INIT ( 16'h0511 )) + \blk00000003/blk00000004/blk0000191c ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00001f1f ), + .I2(\blk00000003/blk00000004/sig00001f20 ), + .I3(\blk00000003/blk00000004/sig00000bb7 ), + .O(\blk00000003/blk00000004/sig00000bbc ) + ); + LUT4 #( + .INIT ( 16'h0511 )) + \blk00000003/blk00000004/blk0000191b ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00001f1d ), + .I2(\blk00000003/blk00000004/sig00001f1e ), + .I3(\blk00000003/blk00000004/sig00000bb7 ), + .O(\blk00000003/blk00000004/sig00000bbe ) + ); + LUT4 #( + .INIT ( 16'h0511 )) + \blk00000003/blk00000004/blk0000191a ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00001f1b ), + .I2(\blk00000003/blk00000004/sig00001f1c ), + .I3(\blk00000003/blk00000004/sig00000bb7 ), + .O(\blk00000003/blk00000004/sig00000bc0 ) + ); + LUT4 #( + .INIT ( 16'h0511 )) + \blk00000003/blk00000004/blk00001919 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00001f19 ), + .I2(\blk00000003/blk00000004/sig00001f1a ), + .I3(\blk00000003/blk00000004/sig00000bb7 ), + .O(\blk00000003/blk00000004/sig00000bc2 ) + ); + LUT4 #( + .INIT ( 16'h0511 )) + \blk00000003/blk00000004/blk00001918 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00001f17 ), + .I2(\blk00000003/blk00000004/sig00001f18 ), + .I3(\blk00000003/blk00000004/sig000018b9 ), + .O(\blk00000003/blk00000004/sig000018ba ) + ); + LUT4 #( + .INIT ( 16'h0511 )) + \blk00000003/blk00000004/blk00001917 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00001f15 ), + .I2(\blk00000003/blk00000004/sig00001f16 ), + .I3(\blk00000003/blk00000004/sig000018b9 ), + .O(\blk00000003/blk00000004/sig000018bc ) + ); + LUT4 #( + .INIT ( 16'h0511 )) + \blk00000003/blk00000004/blk00001916 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00001f13 ), + .I2(\blk00000003/blk00000004/sig00001f14 ), + .I3(\blk00000003/blk00000004/sig000018b9 ), + .O(\blk00000003/blk00000004/sig000018be ) + ); + LUT4 #( + .INIT ( 16'h0511 )) + \blk00000003/blk00000004/blk00001915 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00001f11 ), + .I2(\blk00000003/blk00000004/sig00001f12 ), + .I3(\blk00000003/blk00000004/sig000018b9 ), + .O(\blk00000003/blk00000004/sig000018c0 ) + ); + LUT4 #( + .INIT ( 16'h0511 )) + \blk00000003/blk00000004/blk00001914 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00001f0f ), + .I2(\blk00000003/blk00000004/sig00001f10 ), + .I3(\blk00000003/blk00000004/sig000018b9 ), + .O(\blk00000003/blk00000004/sig000018c2 ) + ); + LUT4 #( + .INIT ( 16'h0511 )) + \blk00000003/blk00000004/blk00001913 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00001f0d ), + .I2(\blk00000003/blk00000004/sig00001f0e ), + .I3(\blk00000003/blk00000004/sig000018b9 ), + .O(\blk00000003/blk00000004/sig000018c4 ) + ); + LUT4 #( + .INIT ( 16'h0511 )) + \blk00000003/blk00000004/blk00001912 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00001f0b ), + .I2(\blk00000003/blk00000004/sig00001f0c ), + .I3(\blk00000003/blk00000004/sig00000b6d ), + .O(\blk00000003/blk00000004/sig00000b6e ) + ); + LUT4 #( + .INIT ( 16'h0511 )) + \blk00000003/blk00000004/blk00001911 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00001f09 ), + .I2(\blk00000003/blk00000004/sig00001f0a ), + .I3(\blk00000003/blk00000004/sig00000b6d ), + .O(\blk00000003/blk00000004/sig00000b70 ) + ); + LUT4 #( + .INIT ( 16'h0511 )) + \blk00000003/blk00000004/blk00001910 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00001f07 ), + .I2(\blk00000003/blk00000004/sig00001f08 ), + .I3(\blk00000003/blk00000004/sig00000b6d ), + .O(\blk00000003/blk00000004/sig00000b72 ) + ); + LUT4 #( + .INIT ( 16'h0511 )) + \blk00000003/blk00000004/blk0000190f ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00001f05 ), + .I2(\blk00000003/blk00000004/sig00001f06 ), + .I3(\blk00000003/blk00000004/sig00000b6d ), + .O(\blk00000003/blk00000004/sig00000b74 ) + ); + LUT4 #( + .INIT ( 16'h0511 )) + \blk00000003/blk00000004/blk0000190e ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00001f03 ), + .I2(\blk00000003/blk00000004/sig00001f04 ), + .I3(\blk00000003/blk00000004/sig00000b6d ), + .O(\blk00000003/blk00000004/sig00000b76 ) + ); + LUT4 #( + .INIT ( 16'h0511 )) + \blk00000003/blk00000004/blk0000190d ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00001f01 ), + .I2(\blk00000003/blk00000004/sig00001f02 ), + .I3(\blk00000003/blk00000004/sig00000b6d ), + .O(\blk00000003/blk00000004/sig00000b78 ) + ); + LUT4 #( + .INIT ( 16'h0511 )) + \blk00000003/blk00000004/blk0000190c ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00001eff ), + .I2(\blk00000003/blk00000004/sig00001f00 ), + .I3(\blk00000003/blk00000004/sig00000b23 ), + .O(\blk00000003/blk00000004/sig00000b24 ) + ); + LUT4 #( + .INIT ( 16'h0511 )) + \blk00000003/blk00000004/blk0000190b ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00001efd ), + .I2(\blk00000003/blk00000004/sig00001efe ), + .I3(\blk00000003/blk00000004/sig00000b23 ), + .O(\blk00000003/blk00000004/sig00000b26 ) + ); + LUT4 #( + .INIT ( 16'h0511 )) + \blk00000003/blk00000004/blk0000190a ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00001efb ), + .I2(\blk00000003/blk00000004/sig00001efc ), + .I3(\blk00000003/blk00000004/sig00000b23 ), + .O(\blk00000003/blk00000004/sig00000b28 ) + ); + LUT4 #( + .INIT ( 16'h0511 )) + \blk00000003/blk00000004/blk00001909 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00001ef9 ), + .I2(\blk00000003/blk00000004/sig00001efa ), + .I3(\blk00000003/blk00000004/sig00000b23 ), + .O(\blk00000003/blk00000004/sig00000b2a ) + ); + LUT4 #( + .INIT ( 16'h0511 )) + \blk00000003/blk00000004/blk00001908 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00001ef7 ), + .I2(\blk00000003/blk00000004/sig00001ef8 ), + .I3(\blk00000003/blk00000004/sig00000b23 ), + .O(\blk00000003/blk00000004/sig00000b2c ) + ); + LUT4 #( + .INIT ( 16'h0511 )) + \blk00000003/blk00000004/blk00001907 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00001ef5 ), + .I2(\blk00000003/blk00000004/sig00001ef6 ), + .I3(\blk00000003/blk00000004/sig00000b23 ), + .O(\blk00000003/blk00000004/sig00000b2e ) + ); + LUT4 #( + .INIT ( 16'h0511 )) + \blk00000003/blk00000004/blk00001906 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00001ef3 ), + .I2(\blk00000003/blk00000004/sig00001ef4 ), + .I3(\blk00000003/blk00000004/sig00000ad9 ), + .O(\blk00000003/blk00000004/sig00000ada ) + ); + LUT4 #( + .INIT ( 16'h0511 )) + \blk00000003/blk00000004/blk00001905 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00001ef1 ), + .I2(\blk00000003/blk00000004/sig00001ef2 ), + .I3(\blk00000003/blk00000004/sig00000ad9 ), + .O(\blk00000003/blk00000004/sig00000adc ) + ); + LUT4 #( + .INIT ( 16'h0511 )) + \blk00000003/blk00000004/blk00001904 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00001eef ), + .I2(\blk00000003/blk00000004/sig00001ef0 ), + .I3(\blk00000003/blk00000004/sig00000ad9 ), + .O(\blk00000003/blk00000004/sig00000ade ) + ); + LUT4 #( + .INIT ( 16'h0511 )) + \blk00000003/blk00000004/blk00001903 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00001eed ), + .I2(\blk00000003/blk00000004/sig00001eee ), + .I3(\blk00000003/blk00000004/sig00000ad9 ), + .O(\blk00000003/blk00000004/sig00000ae0 ) + ); + LUT4 #( + .INIT ( 16'h0511 )) + \blk00000003/blk00000004/blk00001902 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00001eeb ), + .I2(\blk00000003/blk00000004/sig00001eec ), + .I3(\blk00000003/blk00000004/sig00000ad9 ), + .O(\blk00000003/blk00000004/sig00000ae2 ) + ); + LUT4 #( + .INIT ( 16'h0511 )) + \blk00000003/blk00000004/blk00001901 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00001ee9 ), + .I2(\blk00000003/blk00000004/sig00001eea ), + .I3(\blk00000003/blk00000004/sig00000ad9 ), + .O(\blk00000003/blk00000004/sig00000ae4 ) + ); + LUT4 #( + .INIT ( 16'h0511 )) + \blk00000003/blk00000004/blk00001900 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00001ee7 ), + .I2(\blk00000003/blk00000004/sig00001ee8 ), + .I3(\blk00000003/blk00000004/sig00000a8f ), + .O(\blk00000003/blk00000004/sig00000a90 ) + ); + LUT4 #( + .INIT ( 16'h0511 )) + \blk00000003/blk00000004/blk000018ff ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00001ee5 ), + .I2(\blk00000003/blk00000004/sig00001ee6 ), + .I3(\blk00000003/blk00000004/sig00000a8f ), + .O(\blk00000003/blk00000004/sig00000a92 ) + ); + LUT4 #( + .INIT ( 16'h0511 )) + \blk00000003/blk00000004/blk000018fe ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00001ee3 ), + .I2(\blk00000003/blk00000004/sig00001ee4 ), + .I3(\blk00000003/blk00000004/sig00000a8f ), + .O(\blk00000003/blk00000004/sig00000a94 ) + ); + LUT4 #( + .INIT ( 16'h0511 )) + \blk00000003/blk00000004/blk000018fd ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00001ee1 ), + .I2(\blk00000003/blk00000004/sig00001ee2 ), + .I3(\blk00000003/blk00000004/sig00000a8f ), + .O(\blk00000003/blk00000004/sig00000a96 ) + ); + LUT4 #( + .INIT ( 16'h0511 )) + \blk00000003/blk00000004/blk000018fc ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00001edf ), + .I2(\blk00000003/blk00000004/sig00001ee0 ), + .I3(\blk00000003/blk00000004/sig00000a8f ), + .O(\blk00000003/blk00000004/sig00000a98 ) + ); + LUT4 #( + .INIT ( 16'h0511 )) + \blk00000003/blk00000004/blk000018fb ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00001edd ), + .I2(\blk00000003/blk00000004/sig00001ede ), + .I3(\blk00000003/blk00000004/sig00000a8f ), + .O(\blk00000003/blk00000004/sig00000a9a ) + ); + LUT4 #( + .INIT ( 16'h0511 )) + \blk00000003/blk00000004/blk000018fa ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00001edb ), + .I2(\blk00000003/blk00000004/sig00001edc ), + .I3(\blk00000003/blk00000004/sig00000a45 ), + .O(\blk00000003/blk00000004/sig00000a46 ) + ); + LUT4 #( + .INIT ( 16'h0511 )) + \blk00000003/blk00000004/blk000018f9 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00001ed9 ), + .I2(\blk00000003/blk00000004/sig00001eda ), + .I3(\blk00000003/blk00000004/sig00000a45 ), + .O(\blk00000003/blk00000004/sig00000a48 ) + ); + LUT4 #( + .INIT ( 16'h0511 )) + \blk00000003/blk00000004/blk000018f8 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00001ed7 ), + .I2(\blk00000003/blk00000004/sig00001ed8 ), + .I3(\blk00000003/blk00000004/sig00000a45 ), + .O(\blk00000003/blk00000004/sig00000a4a ) + ); + LUT4 #( + .INIT ( 16'h0511 )) + \blk00000003/blk00000004/blk000018f7 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00001ed5 ), + .I2(\blk00000003/blk00000004/sig00001ed6 ), + .I3(\blk00000003/blk00000004/sig00000a45 ), + .O(\blk00000003/blk00000004/sig00000a4c ) + ); + LUT4 #( + .INIT ( 16'h0511 )) + \blk00000003/blk00000004/blk000018f6 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00001ed3 ), + .I2(\blk00000003/blk00000004/sig00001ed4 ), + .I3(\blk00000003/blk00000004/sig00000a45 ), + .O(\blk00000003/blk00000004/sig00000a4e ) + ); + LUT4 #( + .INIT ( 16'h0511 )) + \blk00000003/blk00000004/blk000018f5 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00001ed1 ), + .I2(\blk00000003/blk00000004/sig00001ed2 ), + .I3(\blk00000003/blk00000004/sig00000a45 ), + .O(\blk00000003/blk00000004/sig00000a50 ) + ); + LUT4 #( + .INIT ( 16'h0511 )) + \blk00000003/blk00000004/blk000018f4 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00001ecf ), + .I2(\blk00000003/blk00000004/sig00001ed0 ), + .I3(\blk00000003/blk00000004/sig000009fb ), + .O(\blk00000003/blk00000004/sig000009fc ) + ); + LUT4 #( + .INIT ( 16'h0511 )) + \blk00000003/blk00000004/blk000018f3 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00001ecd ), + .I2(\blk00000003/blk00000004/sig00001ece ), + .I3(\blk00000003/blk00000004/sig000009fb ), + .O(\blk00000003/blk00000004/sig000009fe ) + ); + LUT4 #( + .INIT ( 16'h0511 )) + \blk00000003/blk00000004/blk000018f2 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00001ecb ), + .I2(\blk00000003/blk00000004/sig00001ecc ), + .I3(\blk00000003/blk00000004/sig000009fb ), + .O(\blk00000003/blk00000004/sig00000a00 ) + ); + LUT4 #( + .INIT ( 16'h0511 )) + \blk00000003/blk00000004/blk000018f1 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00001ec9 ), + .I2(\blk00000003/blk00000004/sig00001eca ), + .I3(\blk00000003/blk00000004/sig000009fb ), + .O(\blk00000003/blk00000004/sig00000a02 ) + ); + LUT4 #( + .INIT ( 16'h0511 )) + \blk00000003/blk00000004/blk000018f0 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00001ec7 ), + .I2(\blk00000003/blk00000004/sig00001ec8 ), + .I3(\blk00000003/blk00000004/sig000009fb ), + .O(\blk00000003/blk00000004/sig00000a04 ) + ); + LUT4 #( + .INIT ( 16'h0511 )) + \blk00000003/blk00000004/blk000018ef ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00001ec5 ), + .I2(\blk00000003/blk00000004/sig00001ec6 ), + .I3(\blk00000003/blk00000004/sig000009fb ), + .O(\blk00000003/blk00000004/sig00000a06 ) + ); + LUT4 #( + .INIT ( 16'h0511 )) + \blk00000003/blk00000004/blk000018ee ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00001ec3 ), + .I2(\blk00000003/blk00000004/sig00001ec4 ), + .I3(\blk00000003/blk00000004/sig000009b1 ), + .O(\blk00000003/blk00000004/sig000009b2 ) + ); + LUT4 #( + .INIT ( 16'h0511 )) + \blk00000003/blk00000004/blk000018ed ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00001ec1 ), + .I2(\blk00000003/blk00000004/sig00001ec2 ), + .I3(\blk00000003/blk00000004/sig000009b1 ), + .O(\blk00000003/blk00000004/sig000009b4 ) + ); + LUT4 #( + .INIT ( 16'h0511 )) + \blk00000003/blk00000004/blk000018ec ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00001ebf ), + .I2(\blk00000003/blk00000004/sig00001ec0 ), + .I3(\blk00000003/blk00000004/sig000009b1 ), + .O(\blk00000003/blk00000004/sig000009b6 ) + ); + LUT4 #( + .INIT ( 16'h0511 )) + \blk00000003/blk00000004/blk000018eb ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00001ebd ), + .I2(\blk00000003/blk00000004/sig00001ebe ), + .I3(\blk00000003/blk00000004/sig000009b1 ), + .O(\blk00000003/blk00000004/sig000009b8 ) + ); + LUT4 #( + .INIT ( 16'h0511 )) + \blk00000003/blk00000004/blk000018ea ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00001ebb ), + .I2(\blk00000003/blk00000004/sig00001ebc ), + .I3(\blk00000003/blk00000004/sig000009b1 ), + .O(\blk00000003/blk00000004/sig000009ba ) + ); + LUT4 #( + .INIT ( 16'h0511 )) + \blk00000003/blk00000004/blk000018e9 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00001eb9 ), + .I2(\blk00000003/blk00000004/sig00001eba ), + .I3(\blk00000003/blk00000004/sig000009b1 ), + .O(\blk00000003/blk00000004/sig000009bc ) + ); + LUT4 #( + .INIT ( 16'h0511 )) + \blk00000003/blk00000004/blk000018e8 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00001eb7 ), + .I2(\blk00000003/blk00000004/sig00001eb8 ), + .I3(\blk00000003/blk00000004/sig00000967 ), + .O(\blk00000003/blk00000004/sig00000968 ) + ); + LUT4 #( + .INIT ( 16'h0511 )) + \blk00000003/blk00000004/blk000018e7 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00001eb5 ), + .I2(\blk00000003/blk00000004/sig00001eb6 ), + .I3(\blk00000003/blk00000004/sig00000967 ), + .O(\blk00000003/blk00000004/sig0000096a ) + ); + LUT4 #( + .INIT ( 16'h0511 )) + \blk00000003/blk00000004/blk000018e6 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00001eb3 ), + .I2(\blk00000003/blk00000004/sig00001eb4 ), + .I3(\blk00000003/blk00000004/sig00000967 ), + .O(\blk00000003/blk00000004/sig0000096c ) + ); + LUT4 #( + .INIT ( 16'h0511 )) + \blk00000003/blk00000004/blk000018e5 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00001eb1 ), + .I2(\blk00000003/blk00000004/sig00001eb2 ), + .I3(\blk00000003/blk00000004/sig00000967 ), + .O(\blk00000003/blk00000004/sig0000096e ) + ); + LUT4 #( + .INIT ( 16'h0511 )) + \blk00000003/blk00000004/blk000018e4 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00001eaf ), + .I2(\blk00000003/blk00000004/sig00001eb0 ), + .I3(\blk00000003/blk00000004/sig00000967 ), + .O(\blk00000003/blk00000004/sig00000970 ) + ); + LUT4 #( + .INIT ( 16'h0511 )) + \blk00000003/blk00000004/blk000018e3 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00001ead ), + .I2(\blk00000003/blk00000004/sig00001eae ), + .I3(\blk00000003/blk00000004/sig00000967 ), + .O(\blk00000003/blk00000004/sig00000972 ) + ); + LUT4 #( + .INIT ( 16'h0511 )) + \blk00000003/blk00000004/blk000018e2 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00001eab ), + .I2(\blk00000003/blk00000004/sig00001eac ), + .I3(\blk00000003/blk00000004/sig0000091d ), + .O(\blk00000003/blk00000004/sig0000091e ) + ); + LUT4 #( + .INIT ( 16'h0511 )) + \blk00000003/blk00000004/blk000018e1 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00001ea9 ), + .I2(\blk00000003/blk00000004/sig00001eaa ), + .I3(\blk00000003/blk00000004/sig0000091d ), + .O(\blk00000003/blk00000004/sig00000920 ) + ); + LUT4 #( + .INIT ( 16'h0511 )) + \blk00000003/blk00000004/blk000018e0 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00001ea7 ), + .I2(\blk00000003/blk00000004/sig00001ea8 ), + .I3(\blk00000003/blk00000004/sig0000091d ), + .O(\blk00000003/blk00000004/sig00000922 ) + ); + LUT4 #( + .INIT ( 16'h0511 )) + \blk00000003/blk00000004/blk000018df ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00001ea5 ), + .I2(\blk00000003/blk00000004/sig00001ea6 ), + .I3(\blk00000003/blk00000004/sig0000091d ), + .O(\blk00000003/blk00000004/sig00000924 ) + ); + LUT4 #( + .INIT ( 16'h0511 )) + \blk00000003/blk00000004/blk000018de ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00001ea3 ), + .I2(\blk00000003/blk00000004/sig00001ea4 ), + .I3(\blk00000003/blk00000004/sig0000091d ), + .O(\blk00000003/blk00000004/sig00000926 ) + ); + LUT4 #( + .INIT ( 16'h0511 )) + \blk00000003/blk00000004/blk000018dd ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00001ea1 ), + .I2(\blk00000003/blk00000004/sig00001ea2 ), + .I3(\blk00000003/blk00000004/sig0000091d ), + .O(\blk00000003/blk00000004/sig00000928 ) + ); + LUT4 #( + .INIT ( 16'h0511 )) + \blk00000003/blk00000004/blk000018dc ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00001e9f ), + .I2(\blk00000003/blk00000004/sig00001ea0 ), + .I3(\blk00000003/blk00000004/sig000008d3 ), + .O(\blk00000003/blk00000004/sig000008d4 ) + ); + LUT4 #( + .INIT ( 16'h0511 )) + \blk00000003/blk00000004/blk000018db ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00001e9d ), + .I2(\blk00000003/blk00000004/sig00001e9e ), + .I3(\blk00000003/blk00000004/sig000008d3 ), + .O(\blk00000003/blk00000004/sig000008d6 ) + ); + LUT4 #( + .INIT ( 16'h0511 )) + \blk00000003/blk00000004/blk000018da ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00001e9b ), + .I2(\blk00000003/blk00000004/sig00001e9c ), + .I3(\blk00000003/blk00000004/sig000008d3 ), + .O(\blk00000003/blk00000004/sig000008d8 ) + ); + LUT4 #( + .INIT ( 16'h0511 )) + \blk00000003/blk00000004/blk000018d9 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00001e99 ), + .I2(\blk00000003/blk00000004/sig00001e9a ), + .I3(\blk00000003/blk00000004/sig000008d3 ), + .O(\blk00000003/blk00000004/sig000008da ) + ); + LUT4 #( + .INIT ( 16'h0511 )) + \blk00000003/blk00000004/blk000018d8 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00001e97 ), + .I2(\blk00000003/blk00000004/sig00001e98 ), + .I3(\blk00000003/blk00000004/sig000008d3 ), + .O(\blk00000003/blk00000004/sig000008dc ) + ); + LUT4 #( + .INIT ( 16'h0511 )) + \blk00000003/blk00000004/blk000018d7 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00001e95 ), + .I2(\blk00000003/blk00000004/sig00001e96 ), + .I3(\blk00000003/blk00000004/sig000008d3 ), + .O(\blk00000003/blk00000004/sig000008de ) + ); + LUT4 #( + .INIT ( 16'h0511 )) + \blk00000003/blk00000004/blk000018d6 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00001e93 ), + .I2(\blk00000003/blk00000004/sig00001e94 ), + .I3(\blk00000003/blk00000004/sig0000186f ), + .O(\blk00000003/blk00000004/sig00001870 ) + ); + LUT4 #( + .INIT ( 16'h0511 )) + \blk00000003/blk00000004/blk000018d5 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00001e91 ), + .I2(\blk00000003/blk00000004/sig00001e92 ), + .I3(\blk00000003/blk00000004/sig0000186f ), + .O(\blk00000003/blk00000004/sig00001872 ) + ); + LUT4 #( + .INIT ( 16'h0511 )) + \blk00000003/blk00000004/blk000018d4 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00001e8f ), + .I2(\blk00000003/blk00000004/sig00001e90 ), + .I3(\blk00000003/blk00000004/sig0000186f ), + .O(\blk00000003/blk00000004/sig00001874 ) + ); + LUT4 #( + .INIT ( 16'h0511 )) + \blk00000003/blk00000004/blk000018d3 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00001e8d ), + .I2(\blk00000003/blk00000004/sig00001e8e ), + .I3(\blk00000003/blk00000004/sig0000186f ), + .O(\blk00000003/blk00000004/sig00001876 ) + ); + LUT4 #( + .INIT ( 16'h0511 )) + \blk00000003/blk00000004/blk000018d2 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00001e8b ), + .I2(\blk00000003/blk00000004/sig00001e8c ), + .I3(\blk00000003/blk00000004/sig0000186f ), + .O(\blk00000003/blk00000004/sig00001878 ) + ); + LUT4 #( + .INIT ( 16'h0511 )) + \blk00000003/blk00000004/blk000018d1 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00001e89 ), + .I2(\blk00000003/blk00000004/sig00001e8a ), + .I3(\blk00000003/blk00000004/sig0000186f ), + .O(\blk00000003/blk00000004/sig0000187a ) + ); + LUT4 #( + .INIT ( 16'h0511 )) + \blk00000003/blk00000004/blk000018d0 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00001e87 ), + .I2(\blk00000003/blk00000004/sig00001e88 ), + .I3(\blk00000003/blk00000004/sig00000889 ), + .O(\blk00000003/blk00000004/sig0000088a ) + ); + LUT4 #( + .INIT ( 16'h0511 )) + \blk00000003/blk00000004/blk000018cf ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00001e85 ), + .I2(\blk00000003/blk00000004/sig00001e86 ), + .I3(\blk00000003/blk00000004/sig00000889 ), + .O(\blk00000003/blk00000004/sig0000088c ) + ); + LUT4 #( + .INIT ( 16'h0511 )) + \blk00000003/blk00000004/blk000018ce ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00001e83 ), + .I2(\blk00000003/blk00000004/sig00001e84 ), + .I3(\blk00000003/blk00000004/sig00000889 ), + .O(\blk00000003/blk00000004/sig0000088e ) + ); + LUT4 #( + .INIT ( 16'h0511 )) + \blk00000003/blk00000004/blk000018cd ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00001e81 ), + .I2(\blk00000003/blk00000004/sig00001e82 ), + .I3(\blk00000003/blk00000004/sig00000889 ), + .O(\blk00000003/blk00000004/sig00000890 ) + ); + LUT4 #( + .INIT ( 16'h0511 )) + \blk00000003/blk00000004/blk000018cc ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00001e7f ), + .I2(\blk00000003/blk00000004/sig00001e80 ), + .I3(\blk00000003/blk00000004/sig00000889 ), + .O(\blk00000003/blk00000004/sig00000892 ) + ); + LUT4 #( + .INIT ( 16'h0511 )) + \blk00000003/blk00000004/blk000018cb ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00001e7d ), + .I2(\blk00000003/blk00000004/sig00001e7e ), + .I3(\blk00000003/blk00000004/sig00000889 ), + .O(\blk00000003/blk00000004/sig00000894 ) + ); + LUT4 #( + .INIT ( 16'h0511 )) + \blk00000003/blk00000004/blk000018ca ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00001e7b ), + .I2(\blk00000003/blk00000004/sig00001e7c ), + .I3(\blk00000003/blk00000004/sig0000082f ), + .O(\blk00000003/blk00000004/sig0000083c ) + ); + LUT4 #( + .INIT ( 16'h0511 )) + \blk00000003/blk00000004/blk000018c9 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00001e79 ), + .I2(\blk00000003/blk00000004/sig00001e7a ), + .I3(\blk00000003/blk00000004/sig0000082f ), + .O(\blk00000003/blk00000004/sig0000083e ) + ); + LUT4 #( + .INIT ( 16'h0511 )) + \blk00000003/blk00000004/blk000018c8 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00001e77 ), + .I2(\blk00000003/blk00000004/sig00001e78 ), + .I3(\blk00000003/blk00000004/sig0000082f ), + .O(\blk00000003/blk00000004/sig00000840 ) + ); + LUT4 #( + .INIT ( 16'h0511 )) + \blk00000003/blk00000004/blk000018c7 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00001e75 ), + .I2(\blk00000003/blk00000004/sig00001e76 ), + .I3(\blk00000003/blk00000004/sig0000082f ), + .O(\blk00000003/blk00000004/sig00000842 ) + ); + LUT4 #( + .INIT ( 16'h0511 )) + \blk00000003/blk00000004/blk000018c6 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00001e73 ), + .I2(\blk00000003/blk00000004/sig00001e74 ), + .I3(\blk00000003/blk00000004/sig0000082f ), + .O(\blk00000003/blk00000004/sig00000844 ) + ); + LUT4 #( + .INIT ( 16'h0511 )) + \blk00000003/blk00000004/blk000018c5 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00001e71 ), + .I2(\blk00000003/blk00000004/sig00001e72 ), + .I3(\blk00000003/blk00000004/sig0000082f ), + .O(\blk00000003/blk00000004/sig00000846 ) + ); + LUT4 #( + .INIT ( 16'h0511 )) + \blk00000003/blk00000004/blk000018c4 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00001e6f ), + .I2(\blk00000003/blk00000004/sig00001e70 ), + .I3(\blk00000003/blk00000004/sig000007dd ), + .O(\blk00000003/blk00000004/sig000007de ) + ); + LUT4 #( + .INIT ( 16'h0511 )) + \blk00000003/blk00000004/blk000018c3 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00001e6d ), + .I2(\blk00000003/blk00000004/sig00001e6e ), + .I3(\blk00000003/blk00000004/sig000007dd ), + .O(\blk00000003/blk00000004/sig000007e0 ) + ); + LUT4 #( + .INIT ( 16'h0511 )) + \blk00000003/blk00000004/blk000018c2 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00001e6b ), + .I2(\blk00000003/blk00000004/sig00001e6c ), + .I3(\blk00000003/blk00000004/sig000007dd ), + .O(\blk00000003/blk00000004/sig000007e2 ) + ); + LUT4 #( + .INIT ( 16'h0511 )) + \blk00000003/blk00000004/blk000018c1 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00001e69 ), + .I2(\blk00000003/blk00000004/sig00001e6a ), + .I3(\blk00000003/blk00000004/sig000007dd ), + .O(\blk00000003/blk00000004/sig000007e4 ) + ); + LUT4 #( + .INIT ( 16'h0511 )) + \blk00000003/blk00000004/blk000018c0 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00001e67 ), + .I2(\blk00000003/blk00000004/sig00001e68 ), + .I3(\blk00000003/blk00000004/sig000007dd ), + .O(\blk00000003/blk00000004/sig000007e6 ) + ); + LUT4 #( + .INIT ( 16'h0511 )) + \blk00000003/blk00000004/blk000018bf ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00001e65 ), + .I2(\blk00000003/blk00000004/sig00001e66 ), + .I3(\blk00000003/blk00000004/sig000007dd ), + .O(\blk00000003/blk00000004/sig000007e8 ) + ); + LUT4 #( + .INIT ( 16'h0511 )) + \blk00000003/blk00000004/blk000018be ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00001e63 ), + .I2(\blk00000003/blk00000004/sig00001e64 ), + .I3(\blk00000003/blk00000004/sig00000783 ), + .O(\blk00000003/blk00000004/sig00000790 ) + ); + LUT4 #( + .INIT ( 16'h0511 )) + \blk00000003/blk00000004/blk000018bd ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00001e61 ), + .I2(\blk00000003/blk00000004/sig00001e62 ), + .I3(\blk00000003/blk00000004/sig00000783 ), + .O(\blk00000003/blk00000004/sig00000792 ) + ); + LUT4 #( + .INIT ( 16'h0511 )) + \blk00000003/blk00000004/blk000018bc ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00001e5f ), + .I2(\blk00000003/blk00000004/sig00001e60 ), + .I3(\blk00000003/blk00000004/sig00000783 ), + .O(\blk00000003/blk00000004/sig00000794 ) + ); + LUT4 #( + .INIT ( 16'h0511 )) + \blk00000003/blk00000004/blk000018bb ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00001e5d ), + .I2(\blk00000003/blk00000004/sig00001e5e ), + .I3(\blk00000003/blk00000004/sig00000783 ), + .O(\blk00000003/blk00000004/sig00000796 ) + ); + LUT4 #( + .INIT ( 16'h0511 )) + \blk00000003/blk00000004/blk000018ba ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00001e5b ), + .I2(\blk00000003/blk00000004/sig00001e5c ), + .I3(\blk00000003/blk00000004/sig00000783 ), + .O(\blk00000003/blk00000004/sig00000798 ) + ); + LUT4 #( + .INIT ( 16'h0511 )) + \blk00000003/blk00000004/blk000018b9 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00001e59 ), + .I2(\blk00000003/blk00000004/sig00001e5a ), + .I3(\blk00000003/blk00000004/sig00000783 ), + .O(\blk00000003/blk00000004/sig0000079a ) + ); + LUT4 #( + .INIT ( 16'h0511 )) + \blk00000003/blk00000004/blk000018b8 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00001e57 ), + .I2(\blk00000003/blk00000004/sig00001e58 ), + .I3(\blk00000003/blk00000004/sig00001825 ), + .O(\blk00000003/blk00000004/sig00001826 ) + ); + LUT4 #( + .INIT ( 16'h0511 )) + \blk00000003/blk00000004/blk000018b7 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00001e55 ), + .I2(\blk00000003/blk00000004/sig00001e56 ), + .I3(\blk00000003/blk00000004/sig00001825 ), + .O(\blk00000003/blk00000004/sig00001828 ) + ); + LUT4 #( + .INIT ( 16'h0511 )) + \blk00000003/blk00000004/blk000018b6 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00001e53 ), + .I2(\blk00000003/blk00000004/sig00001e54 ), + .I3(\blk00000003/blk00000004/sig00001825 ), + .O(\blk00000003/blk00000004/sig0000182a ) + ); + LUT4 #( + .INIT ( 16'h0511 )) + \blk00000003/blk00000004/blk000018b5 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00001e51 ), + .I2(\blk00000003/blk00000004/sig00001e52 ), + .I3(\blk00000003/blk00000004/sig00001825 ), + .O(\blk00000003/blk00000004/sig0000182c ) + ); + LUT4 #( + .INIT ( 16'h0511 )) + \blk00000003/blk00000004/blk000018b4 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00001e4f ), + .I2(\blk00000003/blk00000004/sig00001e50 ), + .I3(\blk00000003/blk00000004/sig00001825 ), + .O(\blk00000003/blk00000004/sig0000182e ) + ); + LUT4 #( + .INIT ( 16'h0511 )) + \blk00000003/blk00000004/blk000018b3 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00001e4d ), + .I2(\blk00000003/blk00000004/sig00001e4e ), + .I3(\blk00000003/blk00000004/sig00001825 ), + .O(\blk00000003/blk00000004/sig00001830 ) + ); + LUT4 #( + .INIT ( 16'h0511 )) + \blk00000003/blk00000004/blk000018b2 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00001e4b ), + .I2(\blk00000003/blk00000004/sig00001e4c ), + .I3(\blk00000003/blk00000004/sig000017db ), + .O(\blk00000003/blk00000004/sig000017dc ) + ); + LUT4 #( + .INIT ( 16'h0511 )) + \blk00000003/blk00000004/blk000018b1 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00001e49 ), + .I2(\blk00000003/blk00000004/sig00001e4a ), + .I3(\blk00000003/blk00000004/sig000017db ), + .O(\blk00000003/blk00000004/sig000017de ) + ); + LUT4 #( + .INIT ( 16'h0511 )) + \blk00000003/blk00000004/blk000018b0 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00001e47 ), + .I2(\blk00000003/blk00000004/sig00001e48 ), + .I3(\blk00000003/blk00000004/sig000017db ), + .O(\blk00000003/blk00000004/sig000017e0 ) + ); + LUT4 #( + .INIT ( 16'h0511 )) + \blk00000003/blk00000004/blk000018af ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00001e45 ), + .I2(\blk00000003/blk00000004/sig00001e46 ), + .I3(\blk00000003/blk00000004/sig000017db ), + .O(\blk00000003/blk00000004/sig000017e2 ) + ); + LUT4 #( + .INIT ( 16'h0511 )) + \blk00000003/blk00000004/blk000018ae ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00001e43 ), + .I2(\blk00000003/blk00000004/sig00001e44 ), + .I3(\blk00000003/blk00000004/sig000017db ), + .O(\blk00000003/blk00000004/sig000017e4 ) + ); + LUT4 #( + .INIT ( 16'h0511 )) + \blk00000003/blk00000004/blk000018ad ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00001e41 ), + .I2(\blk00000003/blk00000004/sig00001e42 ), + .I3(\blk00000003/blk00000004/sig000017db ), + .O(\blk00000003/blk00000004/sig000017e6 ) + ); + LUT4 #( + .INIT ( 16'h0511 )) + \blk00000003/blk00000004/blk000018ac ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00001e3f ), + .I2(\blk00000003/blk00000004/sig00001e40 ), + .I3(\blk00000003/blk00000004/sig00001791 ), + .O(\blk00000003/blk00000004/sig00001792 ) + ); + LUT4 #( + .INIT ( 16'h0511 )) + \blk00000003/blk00000004/blk000018ab ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00001e3d ), + .I2(\blk00000003/blk00000004/sig00001e3e ), + .I3(\blk00000003/blk00000004/sig00001791 ), + .O(\blk00000003/blk00000004/sig00001794 ) + ); + LUT4 #( + .INIT ( 16'h0511 )) + \blk00000003/blk00000004/blk000018aa ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00001e3b ), + .I2(\blk00000003/blk00000004/sig00001e3c ), + .I3(\blk00000003/blk00000004/sig00001791 ), + .O(\blk00000003/blk00000004/sig00001796 ) + ); + LUT4 #( + .INIT ( 16'h0511 )) + \blk00000003/blk00000004/blk000018a9 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00001e39 ), + .I2(\blk00000003/blk00000004/sig00001e3a ), + .I3(\blk00000003/blk00000004/sig00001791 ), + .O(\blk00000003/blk00000004/sig00001798 ) + ); + LUT4 #( + .INIT ( 16'h0511 )) + \blk00000003/blk00000004/blk000018a8 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00001e37 ), + .I2(\blk00000003/blk00000004/sig00001e38 ), + .I3(\blk00000003/blk00000004/sig00001791 ), + .O(\blk00000003/blk00000004/sig0000179a ) + ); + LUT4 #( + .INIT ( 16'h0511 )) + \blk00000003/blk00000004/blk000018a7 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00001e35 ), + .I2(\blk00000003/blk00000004/sig00001e36 ), + .I3(\blk00000003/blk00000004/sig00001791 ), + .O(\blk00000003/blk00000004/sig0000179c ) + ); + LUT4 #( + .INIT ( 16'h0511 )) + \blk00000003/blk00000004/blk000018a6 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00001e33 ), + .I2(\blk00000003/blk00000004/sig00001e34 ), + .I3(\blk00000003/blk00000004/sig00001747 ), + .O(\blk00000003/blk00000004/sig00001748 ) + ); + LUT4 #( + .INIT ( 16'h0511 )) + \blk00000003/blk00000004/blk000018a5 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00001e31 ), + .I2(\blk00000003/blk00000004/sig00001e32 ), + .I3(\blk00000003/blk00000004/sig00001747 ), + .O(\blk00000003/blk00000004/sig0000174a ) + ); + LUT4 #( + .INIT ( 16'h0511 )) + \blk00000003/blk00000004/blk000018a4 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00001e2f ), + .I2(\blk00000003/blk00000004/sig00001e30 ), + .I3(\blk00000003/blk00000004/sig00001747 ), + .O(\blk00000003/blk00000004/sig0000174c ) + ); + LUT4 #( + .INIT ( 16'h0511 )) + \blk00000003/blk00000004/blk000018a3 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00001e2d ), + .I2(\blk00000003/blk00000004/sig00001e2e ), + .I3(\blk00000003/blk00000004/sig00001747 ), + .O(\blk00000003/blk00000004/sig0000174e ) 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.I0(\blk00000003/blk00000004/sig000002b0 ), + .I1(\blk00000003/blk00000004/sig00001ded ), + .I2(\blk00000003/blk00000004/sig00001ae8 ), + .I3(\blk00000003/blk00000004/sig00001dee ), + .O(\blk00000003/blk00000004/sig00001def ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \blk00000003/blk00000004/blk00001407 ( + .I0(ce), + .I1(\blk00000003/blk00000004/sig00001deb ), + .O(\blk00000003/blk00000004/sig00001dec ) + ); + LUT4 #( + .INIT ( 16'hE040 )) + \blk00000003/blk00000004/blk00001406 ( + .I0(\blk00000003/blk00000004/sig000002b0 ), + .I1(\blk00000003/blk00000004/sig00001de8 ), + .I2(\blk00000003/blk00000004/sig00001ae8 ), + .I3(\blk00000003/blk00000004/sig00001de9 ), + .O(\blk00000003/blk00000004/sig00001dea ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \blk00000003/blk00000004/blk00001405 ( + .I0(ce), + .I1(\blk00000003/blk00000004/sig00001de6 ), + .O(\blk00000003/blk00000004/sig00001de7 ) + ); + LUT4 #( + .INIT ( 16'hE040 )) + \blk00000003/blk00000004/blk00001404 ( + .I0(\blk00000003/blk00000004/sig000002b0 ), + .I1(\blk00000003/blk00000004/sig00001de3 ), + .I2(\blk00000003/blk00000004/sig00001ae8 ), + .I3(\blk00000003/blk00000004/sig00001de4 ), + .O(\blk00000003/blk00000004/sig00001de5 ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \blk00000003/blk00000004/blk00001403 ( + .I0(ce), + .I1(\blk00000003/blk00000004/sig00001de1 ), + .O(\blk00000003/blk00000004/sig00001de2 ) + ); + LUT4 #( + .INIT ( 16'hE040 )) + \blk00000003/blk00000004/blk00001402 ( + .I0(\blk00000003/blk00000004/sig000002b0 ), + .I1(\blk00000003/blk00000004/sig00001dde ), + .I2(\blk00000003/blk00000004/sig00001ae8 ), + .I3(\blk00000003/blk00000004/sig00001ddf ), + .O(\blk00000003/blk00000004/sig00001de0 ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \blk00000003/blk00000004/blk00001401 ( + .I0(ce), + .I1(\blk00000003/blk00000004/sig00001ddc ), + .O(\blk00000003/blk00000004/sig00001ddd ) + ); + LUT4 #( + .INIT ( 16'hE040 )) + \blk00000003/blk00000004/blk00001400 ( + .I0(\blk00000003/blk00000004/sig000002b0 ), + .I1(\blk00000003/blk00000004/sig00001dd9 ), + .I2(\blk00000003/blk00000004/sig00001ae8 ), + .I3(\blk00000003/blk00000004/sig00001dda ), + .O(\blk00000003/blk00000004/sig00001ddb ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \blk00000003/blk00000004/blk000013ff ( + .I0(ce), + .I1(\blk00000003/blk00000004/sig00001dd7 ), + .O(\blk00000003/blk00000004/sig00001dd8 ) + ); + LUT4 #( + .INIT ( 16'hE040 )) + \blk00000003/blk00000004/blk000013fe ( + .I0(\blk00000003/blk00000004/sig000002b0 ), + .I1(\blk00000003/blk00000004/sig00001dd4 ), + .I2(\blk00000003/blk00000004/sig00001ae8 ), + .I3(\blk00000003/blk00000004/sig00001dd5 ), + .O(\blk00000003/blk00000004/sig00001dd6 ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \blk00000003/blk00000004/blk000013fd ( + .I0(ce), + .I1(\blk00000003/blk00000004/sig00001dd2 ), + .O(\blk00000003/blk00000004/sig00001dd3 ) + ); + LUT4 #( + .INIT ( 16'hE040 )) + \blk00000003/blk00000004/blk000013fc ( + .I0(\blk00000003/blk00000004/sig000002b0 ), + .I1(\blk00000003/blk00000004/sig00001dcf ), + .I2(\blk00000003/blk00000004/sig00001ae8 ), + .I3(\blk00000003/blk00000004/sig00001dd0 ), + .O(\blk00000003/blk00000004/sig00001dd1 ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \blk00000003/blk00000004/blk000013fb ( + .I0(ce), + .I1(\blk00000003/blk00000004/sig00001dcd ), + .O(\blk00000003/blk00000004/sig00001dce ) + ); + LUT4 #( + .INIT ( 16'hE040 )) + \blk00000003/blk00000004/blk000013fa ( + .I0(\blk00000003/blk00000004/sig000002b0 ), + .I1(\blk00000003/blk00000004/sig00001dca ), + .I2(\blk00000003/blk00000004/sig00001ae8 ), + .I3(\blk00000003/blk00000004/sig00001dcb ), + .O(\blk00000003/blk00000004/sig00001dcc ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \blk00000003/blk00000004/blk000013f9 ( + .I0(ce), + .I1(\blk00000003/blk00000004/sig00001dc8 ), + .O(\blk00000003/blk00000004/sig00001dc9 ) + ); + LUT4 #( + .INIT ( 16'hE040 )) + \blk00000003/blk00000004/blk000013f8 ( + .I0(\blk00000003/blk00000004/sig000002b0 ), + .I1(\blk00000003/blk00000004/sig00001dc5 ), + .I2(\blk00000003/blk00000004/sig00001ae8 ), + .I3(\blk00000003/blk00000004/sig00001dc6 ), + .O(\blk00000003/blk00000004/sig00001dc7 ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \blk00000003/blk00000004/blk000013f7 ( + .I0(ce), + .I1(\blk00000003/blk00000004/sig00001dc3 ), + .O(\blk00000003/blk00000004/sig00001dc4 ) + ); + LUT4 #( + .INIT ( 16'hE040 )) + \blk00000003/blk00000004/blk000013f6 ( + .I0(\blk00000003/blk00000004/sig000002b0 ), + .I1(\blk00000003/blk00000004/sig00001dc0 ), + .I2(\blk00000003/blk00000004/sig00001ae8 ), + .I3(\blk00000003/blk00000004/sig00001dc1 ), + .O(\blk00000003/blk00000004/sig00001dc2 ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \blk00000003/blk00000004/blk000013f5 ( + .I0(ce), + .I1(\blk00000003/blk00000004/sig00001dbe ), + .O(\blk00000003/blk00000004/sig00001dbf ) + ); + LUT4 #( + .INIT ( 16'hE040 )) + \blk00000003/blk00000004/blk000013f4 ( + .I0(\blk00000003/blk00000004/sig000002b0 ), + .I1(\blk00000003/blk00000004/sig00001dbb ), + .I2(\blk00000003/blk00000004/sig00001ae8 ), + .I3(\blk00000003/blk00000004/sig00001dbc ), + .O(\blk00000003/blk00000004/sig00001dbd ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \blk00000003/blk00000004/blk000013f3 ( + .I0(ce), + .I1(\blk00000003/blk00000004/sig00001db9 ), + .O(\blk00000003/blk00000004/sig00001dba ) + ); + LUT4 #( + .INIT ( 16'hE040 )) + \blk00000003/blk00000004/blk000013f2 ( + .I0(\blk00000003/blk00000004/sig000002b0 ), + .I1(\blk00000003/blk00000004/sig00001db6 ), + .I2(\blk00000003/blk00000004/sig00001ae8 ), + .I3(\blk00000003/blk00000004/sig00001db7 ), + .O(\blk00000003/blk00000004/sig00001db8 ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \blk00000003/blk00000004/blk000013f1 ( + .I0(ce), + .I1(\blk00000003/blk00000004/sig00001db4 ), + .O(\blk00000003/blk00000004/sig00001db5 ) + ); + LUT4 #( + .INIT ( 16'hE040 )) + \blk00000003/blk00000004/blk000013f0 ( + .I0(\blk00000003/blk00000004/sig000002b0 ), + .I1(\blk00000003/blk00000004/sig00001db1 ), + .I2(\blk00000003/blk00000004/sig00001ae8 ), + .I3(\blk00000003/blk00000004/sig00001db2 ), + .O(\blk00000003/blk00000004/sig00001db3 ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \blk00000003/blk00000004/blk000013ef ( + .I0(ce), + .I1(\blk00000003/blk00000004/sig00001daf ), + .O(\blk00000003/blk00000004/sig00001db0 ) + ); + LUT4 #( + .INIT ( 16'hE040 )) + \blk00000003/blk00000004/blk000013ee ( + .I0(\blk00000003/blk00000004/sig000002b0 ), + .I1(\blk00000003/blk00000004/sig00001dac ), + .I2(\blk00000003/blk00000004/sig00001ae8 ), + .I3(\blk00000003/blk00000004/sig00001dad ), + .O(\blk00000003/blk00000004/sig00001dae ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \blk00000003/blk00000004/blk000013ed ( + .I0(ce), + .I1(\blk00000003/blk00000004/sig00001daa ), + .O(\blk00000003/blk00000004/sig00001dab ) + ); + LUT4 #( + .INIT ( 16'hE040 )) + \blk00000003/blk00000004/blk000013ec ( + .I0(\blk00000003/blk00000004/sig000002b0 ), + .I1(\blk00000003/blk00000004/sig00001da7 ), + .I2(\blk00000003/blk00000004/sig00001ae8 ), + .I3(\blk00000003/blk00000004/sig00001da8 ), + .O(\blk00000003/blk00000004/sig00001da9 ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \blk00000003/blk00000004/blk000013eb ( + .I0(ce), + .I1(\blk00000003/blk00000004/sig00001da5 ), + .O(\blk00000003/blk00000004/sig00001da6 ) + ); + LUT4 #( + .INIT ( 16'hE040 )) + \blk00000003/blk00000004/blk000013ea ( + .I0(\blk00000003/blk00000004/sig000002b0 ), + .I1(\blk00000003/blk00000004/sig00001da2 ), + .I2(\blk00000003/blk00000004/sig00001ae8 ), + .I3(\blk00000003/blk00000004/sig00001da3 ), + .O(\blk00000003/blk00000004/sig00001da4 ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \blk00000003/blk00000004/blk000013e9 ( + .I0(ce), + .I1(\blk00000003/blk00000004/sig00001da0 ), + .O(\blk00000003/blk00000004/sig00001da1 ) + ); + LUT4 #( + .INIT ( 16'hE040 )) + \blk00000003/blk00000004/blk000013e8 ( + .I0(\blk00000003/blk00000004/sig000002b0 ), + .I1(\blk00000003/blk00000004/sig00001d9d ), + .I2(\blk00000003/blk00000004/sig00001ae8 ), + .I3(\blk00000003/blk00000004/sig00001d9e ), + .O(\blk00000003/blk00000004/sig00001d9f ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \blk00000003/blk00000004/blk000013e7 ( + .I0(ce), + .I1(\blk00000003/blk00000004/sig00001d9b ), + .O(\blk00000003/blk00000004/sig00001d9c ) + ); + LUT4 #( + .INIT ( 16'hE040 )) + \blk00000003/blk00000004/blk000013e6 ( + .I0(\blk00000003/blk00000004/sig000002b0 ), + .I1(\blk00000003/blk00000004/sig00001d98 ), + .I2(\blk00000003/blk00000004/sig00001ae8 ), + .I3(\blk00000003/blk00000004/sig00001d99 ), + .O(\blk00000003/blk00000004/sig00001d9a ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \blk00000003/blk00000004/blk000013e5 ( + .I0(ce), + .I1(\blk00000003/blk00000004/sig00001d96 ), + .O(\blk00000003/blk00000004/sig00001d97 ) + ); + LUT4 #( + .INIT ( 16'hE040 )) + \blk00000003/blk00000004/blk000013e4 ( + .I0(\blk00000003/blk00000004/sig000002b0 ), + .I1(\blk00000003/blk00000004/sig00001d93 ), + .I2(\blk00000003/blk00000004/sig00001ae8 ), + .I3(\blk00000003/blk00000004/sig00001d94 ), + .O(\blk00000003/blk00000004/sig00001d95 ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \blk00000003/blk00000004/blk000013e3 ( + .I0(ce), + .I1(\blk00000003/blk00000004/sig00001d91 ), + .O(\blk00000003/blk00000004/sig00001d92 ) + ); + LUT4 #( + .INIT ( 16'hE040 )) + \blk00000003/blk00000004/blk000013e2 ( + .I0(\blk00000003/blk00000004/sig000002b0 ), + .I1(\blk00000003/blk00000004/sig00001d8e ), + .I2(\blk00000003/blk00000004/sig00001ae8 ), + .I3(\blk00000003/blk00000004/sig00001d8f ), + .O(\blk00000003/blk00000004/sig00001d90 ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \blk00000003/blk00000004/blk000013e1 ( + .I0(ce), + .I1(\blk00000003/blk00000004/sig00001d8c ), + .O(\blk00000003/blk00000004/sig00001d8d ) + ); + LUT4 #( + .INIT ( 16'hE040 )) + \blk00000003/blk00000004/blk000013e0 ( + .I0(\blk00000003/blk00000004/sig000002b0 ), + .I1(\blk00000003/blk00000004/sig00001d89 ), + .I2(\blk00000003/blk00000004/sig00001ae8 ), + .I3(\blk00000003/blk00000004/sig00001d8a ), + .O(\blk00000003/blk00000004/sig00001d8b ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \blk00000003/blk00000004/blk000013df ( + .I0(ce), + .I1(\blk00000003/blk00000004/sig00001d87 ), + .O(\blk00000003/blk00000004/sig00001d88 ) + ); + LUT4 #( + .INIT ( 16'hE040 )) + \blk00000003/blk00000004/blk000013de ( + .I0(\blk00000003/blk00000004/sig000002b0 ), + .I1(\blk00000003/blk00000004/sig00001d84 ), + .I2(\blk00000003/blk00000004/sig00001ae8 ), + .I3(\blk00000003/blk00000004/sig00001d85 ), + .O(\blk00000003/blk00000004/sig00001d86 ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \blk00000003/blk00000004/blk000013dd ( + .I0(ce), + .I1(\blk00000003/blk00000004/sig00001d82 ), + .O(\blk00000003/blk00000004/sig00001d83 ) + ); + LUT4 #( + .INIT ( 16'hE040 )) + \blk00000003/blk00000004/blk000013dc ( + .I0(\blk00000003/blk00000004/sig000002b0 ), + .I1(\blk00000003/blk00000004/sig00001d7f ), + .I2(\blk00000003/blk00000004/sig00001ae8 ), + .I3(\blk00000003/blk00000004/sig00001d80 ), + .O(\blk00000003/blk00000004/sig00001d81 ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \blk00000003/blk00000004/blk000013db ( + .I0(ce), + .I1(\blk00000003/blk00000004/sig00001d7d ), + .O(\blk00000003/blk00000004/sig00001d7e ) + ); + LUT4 #( + .INIT ( 16'hE040 )) + \blk00000003/blk00000004/blk000013da ( + .I0(\blk00000003/blk00000004/sig000002b0 ), + .I1(\blk00000003/blk00000004/sig00001d7a ), + .I2(\blk00000003/blk00000004/sig00001ae8 ), + .I3(\blk00000003/blk00000004/sig00001d7b ), + .O(\blk00000003/blk00000004/sig00001d7c ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \blk00000003/blk00000004/blk000013d9 ( + .I0(ce), + .I1(\blk00000003/blk00000004/sig00001d78 ), + .O(\blk00000003/blk00000004/sig00001d79 ) + ); + LUT4 #( + .INIT ( 16'hE040 )) + \blk00000003/blk00000004/blk000013d8 ( + .I0(\blk00000003/blk00000004/sig000002b0 ), + .I1(\blk00000003/blk00000004/sig00001d75 ), + .I2(\blk00000003/blk00000004/sig00001ae8 ), + .I3(\blk00000003/blk00000004/sig00001d76 ), + .O(\blk00000003/blk00000004/sig00001d77 ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \blk00000003/blk00000004/blk000013d7 ( + .I0(ce), + .I1(\blk00000003/blk00000004/sig00001d73 ), + .O(\blk00000003/blk00000004/sig00001d74 ) + ); + LUT4 #( + .INIT ( 16'hE040 )) + \blk00000003/blk00000004/blk000013d6 ( + .I0(\blk00000003/blk00000004/sig000002b0 ), + .I1(\blk00000003/blk00000004/sig00001d70 ), + .I2(\blk00000003/blk00000004/sig00001ae8 ), + .I3(\blk00000003/blk00000004/sig00001d71 ), + .O(\blk00000003/blk00000004/sig00001d72 ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \blk00000003/blk00000004/blk000013d5 ( + .I0(ce), + .I1(\blk00000003/blk00000004/sig00001d6e ), + .O(\blk00000003/blk00000004/sig00001d6f ) + ); + LUT4 #( + .INIT ( 16'hE040 )) + \blk00000003/blk00000004/blk000013d4 ( + .I0(\blk00000003/blk00000004/sig000002b0 ), + .I1(\blk00000003/blk00000004/sig00001d6b ), + .I2(\blk00000003/blk00000004/sig00001ae8 ), + .I3(\blk00000003/blk00000004/sig00001d6c ), + .O(\blk00000003/blk00000004/sig00001d6d ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \blk00000003/blk00000004/blk000013d3 ( + .I0(ce), + .I1(\blk00000003/blk00000004/sig00001d69 ), + .O(\blk00000003/blk00000004/sig00001d6a ) + ); + LUT4 #( + .INIT ( 16'hE040 )) + \blk00000003/blk00000004/blk000013d2 ( + .I0(\blk00000003/blk00000004/sig000002b0 ), + .I1(\blk00000003/blk00000004/sig00001d66 ), + .I2(\blk00000003/blk00000004/sig00001ae8 ), + .I3(\blk00000003/blk00000004/sig00001d67 ), + .O(\blk00000003/blk00000004/sig00001d68 ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \blk00000003/blk00000004/blk000013d1 ( + .I0(ce), + .I1(\blk00000003/blk00000004/sig00001d64 ), + .O(\blk00000003/blk00000004/sig00001d65 ) + ); + LUT4 #( + .INIT ( 16'hE040 )) + \blk00000003/blk00000004/blk000013d0 ( + .I0(\blk00000003/blk00000004/sig000002b0 ), + .I1(\blk00000003/blk00000004/sig00001d61 ), + .I2(\blk00000003/blk00000004/sig00001ae8 ), + .I3(\blk00000003/blk00000004/sig00001d62 ), + .O(\blk00000003/blk00000004/sig00001d63 ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \blk00000003/blk00000004/blk000013cf ( + .I0(ce), + .I1(\blk00000003/blk00000004/sig00001d5f ), + .O(\blk00000003/blk00000004/sig00001d60 ) + ); + LUT4 #( + .INIT ( 16'hE040 )) + \blk00000003/blk00000004/blk000013ce ( + .I0(\blk00000003/blk00000004/sig000002b0 ), + .I1(\blk00000003/blk00000004/sig00001d5c ), + .I2(\blk00000003/blk00000004/sig00001ae8 ), + .I3(\blk00000003/blk00000004/sig00001d5d ), + .O(\blk00000003/blk00000004/sig00001d5e ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \blk00000003/blk00000004/blk000013cd ( + .I0(ce), + .I1(\blk00000003/blk00000004/sig00001d5a ), + .O(\blk00000003/blk00000004/sig00001d5b ) + ); + LUT4 #( + .INIT ( 16'hE040 )) + \blk00000003/blk00000004/blk000013cc ( + .I0(\blk00000003/blk00000004/sig000002b0 ), + .I1(\blk00000003/blk00000004/sig00001d57 ), + .I2(\blk00000003/blk00000004/sig00001ae8 ), + .I3(\blk00000003/blk00000004/sig00001d58 ), + .O(\blk00000003/blk00000004/sig00001d59 ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \blk00000003/blk00000004/blk000013cb ( + .I0(ce), + .I1(\blk00000003/blk00000004/sig00001d55 ), + .O(\blk00000003/blk00000004/sig00001d56 ) + ); + LUT4 #( + .INIT ( 16'hE040 )) + \blk00000003/blk00000004/blk000013ca ( + .I0(\blk00000003/blk00000004/sig000002b0 ), + .I1(\blk00000003/blk00000004/sig00001d52 ), + .I2(\blk00000003/blk00000004/sig00001ae8 ), + .I3(\blk00000003/blk00000004/sig00001d53 ), + .O(\blk00000003/blk00000004/sig00001d54 ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \blk00000003/blk00000004/blk000013c9 ( + .I0(ce), + .I1(\blk00000003/blk00000004/sig00001d50 ), + .O(\blk00000003/blk00000004/sig00001d51 ) + ); + LUT4 #( + .INIT ( 16'hE040 )) + \blk00000003/blk00000004/blk000013c8 ( + .I0(\blk00000003/blk00000004/sig000002b0 ), + .I1(\blk00000003/blk00000004/sig00001d4d ), + .I2(\blk00000003/blk00000004/sig00001ae8 ), + .I3(\blk00000003/blk00000004/sig00001d4e ), + .O(\blk00000003/blk00000004/sig00001d4f ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \blk00000003/blk00000004/blk000013c7 ( + .I0(ce), + .I1(\blk00000003/blk00000004/sig00001d4b ), + .O(\blk00000003/blk00000004/sig00001d4c ) + ); + LUT4 #( + .INIT ( 16'hE040 )) + \blk00000003/blk00000004/blk000013c6 ( + .I0(\blk00000003/blk00000004/sig000002b0 ), + .I1(\blk00000003/blk00000004/sig00001d48 ), + .I2(\blk00000003/blk00000004/sig00001ae8 ), + .I3(\blk00000003/blk00000004/sig00001d49 ), + .O(\blk00000003/blk00000004/sig00001d4a ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \blk00000003/blk00000004/blk000013c5 ( + .I0(ce), + .I1(\blk00000003/blk00000004/sig00001d46 ), + .O(\blk00000003/blk00000004/sig00001d47 ) + ); + LUT4 #( + .INIT ( 16'hE040 )) + \blk00000003/blk00000004/blk000013c4 ( + .I0(\blk00000003/blk00000004/sig000002b0 ), + .I1(\blk00000003/blk00000004/sig00001d43 ), + .I2(\blk00000003/blk00000004/sig00001ae8 ), + .I3(\blk00000003/blk00000004/sig00001d44 ), + .O(\blk00000003/blk00000004/sig00001d45 ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \blk00000003/blk00000004/blk000013c3 ( + .I0(ce), + .I1(\blk00000003/blk00000004/sig00001d41 ), + .O(\blk00000003/blk00000004/sig00001d42 ) + ); + LUT4 #( + .INIT ( 16'hE040 )) + \blk00000003/blk00000004/blk000013c2 ( + .I0(\blk00000003/blk00000004/sig000002b0 ), + .I1(\blk00000003/blk00000004/sig00001d3e ), + .I2(\blk00000003/blk00000004/sig00001ae8 ), + .I3(\blk00000003/blk00000004/sig00001d3f ), + .O(\blk00000003/blk00000004/sig00001d40 ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \blk00000003/blk00000004/blk000013c1 ( + .I0(ce), + .I1(\blk00000003/blk00000004/sig00001d3c ), + .O(\blk00000003/blk00000004/sig00001d3d ) + ); + LUT4 #( + .INIT ( 16'hE040 )) + \blk00000003/blk00000004/blk000013c0 ( + .I0(\blk00000003/blk00000004/sig000002b0 ), + .I1(\blk00000003/blk00000004/sig00001d39 ), + .I2(\blk00000003/blk00000004/sig00001ae8 ), + .I3(\blk00000003/blk00000004/sig00001d3a ), + .O(\blk00000003/blk00000004/sig00001d3b ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \blk00000003/blk00000004/blk000013bf ( + .I0(ce), + .I1(\blk00000003/blk00000004/sig00001d37 ), + .O(\blk00000003/blk00000004/sig00001d38 ) + ); + LUT4 #( + .INIT ( 16'hE040 )) + \blk00000003/blk00000004/blk000013be ( + .I0(\blk00000003/blk00000004/sig000002b0 ), + .I1(\blk00000003/blk00000004/sig00001d34 ), + .I2(\blk00000003/blk00000004/sig00001ae8 ), + .I3(\blk00000003/blk00000004/sig00001d35 ), + .O(\blk00000003/blk00000004/sig00001d36 ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \blk00000003/blk00000004/blk000013bd ( + .I0(ce), + .I1(\blk00000003/blk00000004/sig00001d32 ), + .O(\blk00000003/blk00000004/sig00001d33 ) + ); + LUT4 #( + .INIT ( 16'hE040 )) + \blk00000003/blk00000004/blk000013bc ( + .I0(\blk00000003/blk00000004/sig000002b0 ), + .I1(\blk00000003/blk00000004/sig00001d2f ), + .I2(\blk00000003/blk00000004/sig00001ae8 ), + .I3(\blk00000003/blk00000004/sig00001d30 ), + .O(\blk00000003/blk00000004/sig00001d31 ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \blk00000003/blk00000004/blk000013bb ( + .I0(ce), + .I1(\blk00000003/blk00000004/sig00001d2d ), + .O(\blk00000003/blk00000004/sig00001d2e ) + ); + LUT4 #( + .INIT ( 16'hE040 )) + \blk00000003/blk00000004/blk000013ba ( + .I0(\blk00000003/blk00000004/sig000002b0 ), + .I1(\blk00000003/blk00000004/sig00001d2a ), + .I2(\blk00000003/blk00000004/sig00001ae8 ), + .I3(\blk00000003/blk00000004/sig00001d2b ), + .O(\blk00000003/blk00000004/sig00001d2c ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \blk00000003/blk00000004/blk000013b9 ( + .I0(ce), + .I1(\blk00000003/blk00000004/sig00001d28 ), + .O(\blk00000003/blk00000004/sig00001d29 ) + ); + LUT4 #( + .INIT ( 16'hE040 )) + \blk00000003/blk00000004/blk000013b8 ( + .I0(\blk00000003/blk00000004/sig000002b0 ), + .I1(\blk00000003/blk00000004/sig00001d25 ), + .I2(\blk00000003/blk00000004/sig00001ae8 ), + .I3(\blk00000003/blk00000004/sig00001d26 ), + .O(\blk00000003/blk00000004/sig00001d27 ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \blk00000003/blk00000004/blk000013b7 ( + .I0(ce), + .I1(\blk00000003/blk00000004/sig00001d23 ), + .O(\blk00000003/blk00000004/sig00001d24 ) + ); + LUT4 #( + .INIT ( 16'hE040 )) + \blk00000003/blk00000004/blk000013b6 ( + .I0(\blk00000003/blk00000004/sig000002b0 ), + .I1(\blk00000003/blk00000004/sig00001d20 ), + .I2(\blk00000003/blk00000004/sig00001ae8 ), + .I3(\blk00000003/blk00000004/sig00001d21 ), + .O(\blk00000003/blk00000004/sig00001d22 ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \blk00000003/blk00000004/blk000013b5 ( + .I0(ce), + .I1(\blk00000003/blk00000004/sig00001d1e ), + .O(\blk00000003/blk00000004/sig00001d1f ) + ); + LUT4 #( + .INIT ( 16'hE040 )) + \blk00000003/blk00000004/blk000013b4 ( + .I0(\blk00000003/blk00000004/sig000002b0 ), + .I1(\blk00000003/blk00000004/sig00001d1b ), + .I2(\blk00000003/blk00000004/sig00001ae8 ), + .I3(\blk00000003/blk00000004/sig00001d1c ), + .O(\blk00000003/blk00000004/sig00001d1d ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \blk00000003/blk00000004/blk000013b3 ( + .I0(ce), + .I1(\blk00000003/blk00000004/sig00001d19 ), + .O(\blk00000003/blk00000004/sig00001d1a ) + ); + LUT4 #( + .INIT ( 16'hE040 )) + \blk00000003/blk00000004/blk000013b2 ( + .I0(\blk00000003/blk00000004/sig000002b0 ), + .I1(\blk00000003/blk00000004/sig00001d16 ), + .I2(\blk00000003/blk00000004/sig00001ae8 ), + .I3(\blk00000003/blk00000004/sig00001d17 ), + .O(\blk00000003/blk00000004/sig00001d18 ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \blk00000003/blk00000004/blk000013b1 ( + .I0(ce), + .I1(\blk00000003/blk00000004/sig00001d14 ), + .O(\blk00000003/blk00000004/sig00001d15 ) + ); + LUT4 #( + .INIT ( 16'hE040 )) + \blk00000003/blk00000004/blk000013b0 ( + .I0(\blk00000003/blk00000004/sig000002b0 ), + .I1(\blk00000003/blk00000004/sig00001d11 ), + .I2(\blk00000003/blk00000004/sig00001ae8 ), + .I3(\blk00000003/blk00000004/sig00001d12 ), + .O(\blk00000003/blk00000004/sig00001d13 ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \blk00000003/blk00000004/blk000013af ( + .I0(ce), + .I1(\blk00000003/blk00000004/sig00001d0f ), + .O(\blk00000003/blk00000004/sig00001d10 ) + ); + LUT4 #( + .INIT ( 16'hE040 )) + \blk00000003/blk00000004/blk000013ae ( + .I0(\blk00000003/blk00000004/sig000002b0 ), + .I1(\blk00000003/blk00000004/sig00001d0c ), + .I2(\blk00000003/blk00000004/sig00001ae8 ), + .I3(\blk00000003/blk00000004/sig00001d0d ), + .O(\blk00000003/blk00000004/sig00001d0e ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \blk00000003/blk00000004/blk000013ad ( + .I0(ce), + .I1(\blk00000003/blk00000004/sig00001d0a ), + .O(\blk00000003/blk00000004/sig00001d0b ) + ); + LUT4 #( + .INIT ( 16'hE040 )) + \blk00000003/blk00000004/blk000013ac ( + .I0(\blk00000003/blk00000004/sig000002b0 ), + .I1(\blk00000003/blk00000004/sig00001d07 ), + .I2(\blk00000003/blk00000004/sig00001ae8 ), + .I3(\blk00000003/blk00000004/sig00001d08 ), + .O(\blk00000003/blk00000004/sig00001d09 ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \blk00000003/blk00000004/blk000013ab ( + .I0(ce), + .I1(\blk00000003/blk00000004/sig00001d05 ), + .O(\blk00000003/blk00000004/sig00001d06 ) + ); + LUT4 #( + .INIT ( 16'hE040 )) + \blk00000003/blk00000004/blk000013aa ( + .I0(\blk00000003/blk00000004/sig000002b0 ), + .I1(\blk00000003/blk00000004/sig00001d02 ), + .I2(\blk00000003/blk00000004/sig00001ae8 ), + .I3(\blk00000003/blk00000004/sig00001d03 ), + .O(\blk00000003/blk00000004/sig00001d04 ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \blk00000003/blk00000004/blk000013a9 ( + .I0(ce), + .I1(\blk00000003/blk00000004/sig00001d00 ), + .O(\blk00000003/blk00000004/sig00001d01 ) + ); + LUT4 #( + .INIT ( 16'hE040 )) + \blk00000003/blk00000004/blk000013a8 ( + .I0(\blk00000003/blk00000004/sig000002b0 ), + .I1(\blk00000003/blk00000004/sig00001cfd ), + .I2(\blk00000003/blk00000004/sig00001ae8 ), + .I3(\blk00000003/blk00000004/sig00001cfe ), + .O(\blk00000003/blk00000004/sig00001cff ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \blk00000003/blk00000004/blk000013a7 ( + .I0(ce), + .I1(\blk00000003/blk00000004/sig00001cfb ), + .O(\blk00000003/blk00000004/sig00001cfc ) + ); + LUT4 #( + .INIT ( 16'hE040 )) + \blk00000003/blk00000004/blk000013a6 ( + .I0(\blk00000003/blk00000004/sig000002b0 ), + .I1(\blk00000003/blk00000004/sig00001cf8 ), + .I2(\blk00000003/blk00000004/sig00001ae8 ), + .I3(\blk00000003/blk00000004/sig00001cf9 ), + .O(\blk00000003/blk00000004/sig00001cfa ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \blk00000003/blk00000004/blk000013a5 ( + .I0(ce), + .I1(\blk00000003/blk00000004/sig00001cf6 ), + .O(\blk00000003/blk00000004/sig00001cf7 ) + ); + LUT4 #( + .INIT ( 16'hE040 )) + \blk00000003/blk00000004/blk000013a4 ( + .I0(\blk00000003/blk00000004/sig000002b0 ), + .I1(\blk00000003/blk00000004/sig00001cf3 ), + .I2(\blk00000003/blk00000004/sig00001ae8 ), + .I3(\blk00000003/blk00000004/sig00001cf4 ), + .O(\blk00000003/blk00000004/sig00001cf5 ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \blk00000003/blk00000004/blk000013a3 ( + .I0(ce), + .I1(\blk00000003/blk00000004/sig00001cf1 ), + .O(\blk00000003/blk00000004/sig00001cf2 ) + ); + LUT4 #( + .INIT ( 16'hE040 )) + \blk00000003/blk00000004/blk000013a2 ( + .I0(\blk00000003/blk00000004/sig000002b0 ), + .I1(\blk00000003/blk00000004/sig00001cee ), + .I2(\blk00000003/blk00000004/sig00001ae8 ), + .I3(\blk00000003/blk00000004/sig00001cef ), + .O(\blk00000003/blk00000004/sig00001cf0 ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \blk00000003/blk00000004/blk000013a1 ( + .I0(ce), + .I1(\blk00000003/blk00000004/sig00001cec ), + .O(\blk00000003/blk00000004/sig00001ced ) + ); + LUT4 #( + .INIT ( 16'hE040 )) + \blk00000003/blk00000004/blk000013a0 ( + .I0(\blk00000003/blk00000004/sig000002b0 ), + .I1(\blk00000003/blk00000004/sig00001ce9 ), + .I2(\blk00000003/blk00000004/sig00001ae8 ), + .I3(\blk00000003/blk00000004/sig00001cea ), + .O(\blk00000003/blk00000004/sig00001ceb ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \blk00000003/blk00000004/blk0000139f ( + .I0(ce), + .I1(\blk00000003/blk00000004/sig00001ce7 ), + .O(\blk00000003/blk00000004/sig00001ce8 ) + ); + LUT4 #( + .INIT ( 16'hE040 )) + \blk00000003/blk00000004/blk0000139e ( + .I0(\blk00000003/blk00000004/sig000002b0 ), + .I1(\blk00000003/blk00000004/sig00001c24 ), + .I2(\blk00000003/blk00000004/sig00001ae8 ), + .I3(\blk00000003/blk00000004/sig00001c25 ), + .O(\blk00000003/blk00000004/sig00001ce6 ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \blk00000003/blk00000004/blk0000139d ( + .I0(ce), + .I1(\blk00000003/blk00000004/sig00001ce4 ), + .O(\blk00000003/blk00000004/sig00001ce5 ) + ); + LUT4 #( + .INIT ( 16'hE040 )) + \blk00000003/blk00000004/blk0000139c ( + .I0(\blk00000003/blk00000004/sig000002b0 ), + .I1(\blk00000003/blk00000004/sig00001c1f ), + .I2(\blk00000003/blk00000004/sig00001ae8 ), + .I3(\blk00000003/blk00000004/sig00001c20 ), + .O(\blk00000003/blk00000004/sig00001ce3 ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \blk00000003/blk00000004/blk0000139b ( + .I0(ce), + .I1(\blk00000003/blk00000004/sig00001ce1 ), + .O(\blk00000003/blk00000004/sig00001ce2 ) + ); + LUT4 #( + .INIT ( 16'hE040 )) + \blk00000003/blk00000004/blk0000139a ( + .I0(\blk00000003/blk00000004/sig000002b0 ), + .I1(\blk00000003/blk00000004/sig00001c1a ), + .I2(\blk00000003/blk00000004/sig00001ae8 ), + .I3(\blk00000003/blk00000004/sig00001c1b ), + .O(\blk00000003/blk00000004/sig00001ce0 ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \blk00000003/blk00000004/blk00001399 ( + .I0(ce), + .I1(\blk00000003/blk00000004/sig00001cde ), + .O(\blk00000003/blk00000004/sig00001cdf ) + ); + LUT4 #( + .INIT ( 16'hE040 )) + \blk00000003/blk00000004/blk00001398 ( + .I0(\blk00000003/blk00000004/sig000002b0 ), + .I1(\blk00000003/blk00000004/sig00001c15 ), + .I2(\blk00000003/blk00000004/sig00001ae8 ), + .I3(\blk00000003/blk00000004/sig00001c16 ), + .O(\blk00000003/blk00000004/sig00001cdd ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \blk00000003/blk00000004/blk00001397 ( + .I0(ce), + .I1(\blk00000003/blk00000004/sig00001cdb ), + .O(\blk00000003/blk00000004/sig00001cdc ) + ); + LUT4 #( + .INIT ( 16'hE040 )) + \blk00000003/blk00000004/blk00001396 ( + .I0(\blk00000003/blk00000004/sig000002b0 ), + .I1(\blk00000003/blk00000004/sig00001c10 ), + .I2(\blk00000003/blk00000004/sig00001ae8 ), + .I3(\blk00000003/blk00000004/sig00001c11 ), + .O(\blk00000003/blk00000004/sig00001cda ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \blk00000003/blk00000004/blk00001395 ( + .I0(ce), + .I1(\blk00000003/blk00000004/sig00001cd8 ), + .O(\blk00000003/blk00000004/sig00001cd9 ) + ); + LUT4 #( + .INIT ( 16'hE040 )) + \blk00000003/blk00000004/blk00001394 ( + .I0(\blk00000003/blk00000004/sig000002b0 ), + .I1(\blk00000003/blk00000004/sig00001c0b ), + .I2(\blk00000003/blk00000004/sig00001ae8 ), + .I3(\blk00000003/blk00000004/sig00001c0c ), + .O(\blk00000003/blk00000004/sig00001cd7 ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \blk00000003/blk00000004/blk00001393 ( + .I0(ce), + .I1(\blk00000003/blk00000004/sig00001cd5 ), + .O(\blk00000003/blk00000004/sig00001cd6 ) + ); + LUT4 #( + .INIT ( 16'hE040 )) + \blk00000003/blk00000004/blk00001392 ( + .I0(\blk00000003/blk00000004/sig000002b0 ), + .I1(\blk00000003/blk00000004/sig00001c06 ), + .I2(\blk00000003/blk00000004/sig00001ae8 ), + .I3(\blk00000003/blk00000004/sig00001c07 ), + .O(\blk00000003/blk00000004/sig00001cd4 ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \blk00000003/blk00000004/blk00001391 ( + .I0(ce), + .I1(\blk00000003/blk00000004/sig00001cd2 ), + .O(\blk00000003/blk00000004/sig00001cd3 ) + ); + LUT4 #( + .INIT ( 16'hE040 )) + \blk00000003/blk00000004/blk00001390 ( + .I0(\blk00000003/blk00000004/sig000002b0 ), + .I1(\blk00000003/blk00000004/sig00001c01 ), + .I2(\blk00000003/blk00000004/sig00001ae8 ), + .I3(\blk00000003/blk00000004/sig00001c02 ), + .O(\blk00000003/blk00000004/sig00001cd1 ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \blk00000003/blk00000004/blk0000138f ( + .I0(ce), + .I1(\blk00000003/blk00000004/sig00001ccf ), + .O(\blk00000003/blk00000004/sig00001cd0 ) + ); + LUT4 #( + .INIT ( 16'hE040 )) + \blk00000003/blk00000004/blk0000138e ( + .I0(\blk00000003/blk00000004/sig000002b0 ), + .I1(\blk00000003/blk00000004/sig00001bfc ), + .I2(\blk00000003/blk00000004/sig00001ae8 ), + .I3(\blk00000003/blk00000004/sig00001bfd ), + .O(\blk00000003/blk00000004/sig00001cce ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \blk00000003/blk00000004/blk0000138d ( + .I0(ce), + .I1(\blk00000003/blk00000004/sig00001ccc ), + .O(\blk00000003/blk00000004/sig00001ccd ) + ); + LUT4 #( + .INIT ( 16'hE040 )) + \blk00000003/blk00000004/blk0000138c ( + .I0(\blk00000003/blk00000004/sig000002b0 ), + .I1(\blk00000003/blk00000004/sig00001bf7 ), + .I2(\blk00000003/blk00000004/sig00001ae8 ), + .I3(\blk00000003/blk00000004/sig00001bf8 ), + .O(\blk00000003/blk00000004/sig00001ccb ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \blk00000003/blk00000004/blk0000138b ( + .I0(ce), + .I1(\blk00000003/blk00000004/sig00001cc9 ), + .O(\blk00000003/blk00000004/sig00001cca ) + ); + LUT4 #( + .INIT ( 16'hE040 )) + \blk00000003/blk00000004/blk0000138a ( + .I0(\blk00000003/blk00000004/sig000002b0 ), + .I1(\blk00000003/blk00000004/sig00001bf2 ), + .I2(\blk00000003/blk00000004/sig00001ae8 ), + .I3(\blk00000003/blk00000004/sig00001bf3 ), + .O(\blk00000003/blk00000004/sig00001cc8 ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \blk00000003/blk00000004/blk00001389 ( + .I0(ce), + .I1(\blk00000003/blk00000004/sig00001cc6 ), + .O(\blk00000003/blk00000004/sig00001cc7 ) + ); + LUT4 #( + .INIT ( 16'hE040 )) + \blk00000003/blk00000004/blk00001388 ( + .I0(\blk00000003/blk00000004/sig000002b0 ), + .I1(\blk00000003/blk00000004/sig00001bed ), + .I2(\blk00000003/blk00000004/sig00001ae8 ), + .I3(\blk00000003/blk00000004/sig00001bee ), + .O(\blk00000003/blk00000004/sig00001cc5 ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \blk00000003/blk00000004/blk00001387 ( + .I0(ce), + .I1(\blk00000003/blk00000004/sig00001cc3 ), + .O(\blk00000003/blk00000004/sig00001cc4 ) + ); + LUT4 #( + .INIT ( 16'hE040 )) + \blk00000003/blk00000004/blk00001386 ( + .I0(\blk00000003/blk00000004/sig000002b0 ), + .I1(\blk00000003/blk00000004/sig00001be8 ), + .I2(\blk00000003/blk00000004/sig00001ae8 ), + .I3(\blk00000003/blk00000004/sig00001be9 ), + .O(\blk00000003/blk00000004/sig00001cc2 ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \blk00000003/blk00000004/blk00001385 ( + .I0(ce), + .I1(\blk00000003/blk00000004/sig00001cc0 ), + .O(\blk00000003/blk00000004/sig00001cc1 ) + ); + LUT4 #( + .INIT ( 16'hE040 )) + \blk00000003/blk00000004/blk00001384 ( + .I0(\blk00000003/blk00000004/sig000002b0 ), + .I1(\blk00000003/blk00000004/sig00001be3 ), + .I2(\blk00000003/blk00000004/sig00001ae8 ), + .I3(\blk00000003/blk00000004/sig00001be4 ), + .O(\blk00000003/blk00000004/sig00001cbf ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \blk00000003/blk00000004/blk00001383 ( + .I0(ce), + .I1(\blk00000003/blk00000004/sig00001cbd ), + .O(\blk00000003/blk00000004/sig00001cbe ) + ); + LUT4 #( + .INIT ( 16'hE040 )) + \blk00000003/blk00000004/blk00001382 ( + .I0(\blk00000003/blk00000004/sig000002b0 ), + .I1(\blk00000003/blk00000004/sig00001bde ), + .I2(\blk00000003/blk00000004/sig00001ae8 ), + .I3(\blk00000003/blk00000004/sig00001bdf ), + .O(\blk00000003/blk00000004/sig00001cbc ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \blk00000003/blk00000004/blk00001381 ( + .I0(ce), + .I1(\blk00000003/blk00000004/sig00001cba ), + .O(\blk00000003/blk00000004/sig00001cbb ) + ); + LUT4 #( + .INIT ( 16'hE040 )) + \blk00000003/blk00000004/blk00001380 ( + .I0(\blk00000003/blk00000004/sig000002b0 ), + .I1(\blk00000003/blk00000004/sig00001bd9 ), + .I2(\blk00000003/blk00000004/sig00001ae8 ), + .I3(\blk00000003/blk00000004/sig00001bda ), + .O(\blk00000003/blk00000004/sig00001cb9 ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \blk00000003/blk00000004/blk0000137f ( + .I0(ce), + .I1(\blk00000003/blk00000004/sig00001cb7 ), + .O(\blk00000003/blk00000004/sig00001cb8 ) + ); + LUT4 #( + .INIT ( 16'hE040 )) + \blk00000003/blk00000004/blk0000137e ( + .I0(\blk00000003/blk00000004/sig000002b0 ), + .I1(\blk00000003/blk00000004/sig00001bd4 ), + .I2(\blk00000003/blk00000004/sig00001ae8 ), + .I3(\blk00000003/blk00000004/sig00001bd5 ), + .O(\blk00000003/blk00000004/sig00001cb6 ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \blk00000003/blk00000004/blk0000137d ( + .I0(ce), + .I1(\blk00000003/blk00000004/sig00001cb4 ), + .O(\blk00000003/blk00000004/sig00001cb5 ) + ); + LUT4 #( + .INIT ( 16'hE040 )) + \blk00000003/blk00000004/blk0000137c ( + .I0(\blk00000003/blk00000004/sig000002b0 ), + .I1(\blk00000003/blk00000004/sig00001bcf ), + .I2(\blk00000003/blk00000004/sig00001ae8 ), + .I3(\blk00000003/blk00000004/sig00001bd0 ), + .O(\blk00000003/blk00000004/sig00001cb3 ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \blk00000003/blk00000004/blk0000137b ( + .I0(ce), + .I1(\blk00000003/blk00000004/sig00001cb1 ), + .O(\blk00000003/blk00000004/sig00001cb2 ) + ); + LUT4 #( + .INIT ( 16'hE040 )) + \blk00000003/blk00000004/blk0000137a ( + .I0(\blk00000003/blk00000004/sig000002b0 ), + .I1(\blk00000003/blk00000004/sig00001bca ), + .I2(\blk00000003/blk00000004/sig00001ae8 ), + .I3(\blk00000003/blk00000004/sig00001bcb ), + .O(\blk00000003/blk00000004/sig00001cb0 ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \blk00000003/blk00000004/blk00001379 ( + .I0(ce), + .I1(\blk00000003/blk00000004/sig00001cae ), + .O(\blk00000003/blk00000004/sig00001caf ) + ); + LUT4 #( + .INIT ( 16'hE040 )) + \blk00000003/blk00000004/blk00001378 ( + .I0(\blk00000003/blk00000004/sig000002b0 ), + .I1(\blk00000003/blk00000004/sig00001bc5 ), + .I2(\blk00000003/blk00000004/sig00001ae8 ), + .I3(\blk00000003/blk00000004/sig00001bc6 ), + .O(\blk00000003/blk00000004/sig00001cad ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \blk00000003/blk00000004/blk00001377 ( + .I0(ce), + .I1(\blk00000003/blk00000004/sig00001cab ), + .O(\blk00000003/blk00000004/sig00001cac ) + ); + LUT4 #( + .INIT ( 16'hE040 )) + \blk00000003/blk00000004/blk00001376 ( + .I0(\blk00000003/blk00000004/sig000002b0 ), + .I1(\blk00000003/blk00000004/sig00001bc0 ), + .I2(\blk00000003/blk00000004/sig00001ae8 ), + .I3(\blk00000003/blk00000004/sig00001bc1 ), + .O(\blk00000003/blk00000004/sig00001caa ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \blk00000003/blk00000004/blk00001375 ( + .I0(ce), + .I1(\blk00000003/blk00000004/sig00001ca8 ), + .O(\blk00000003/blk00000004/sig00001ca9 ) + ); + LUT4 #( + .INIT ( 16'hE040 )) + \blk00000003/blk00000004/blk00001374 ( + .I0(\blk00000003/blk00000004/sig000002b0 ), + .I1(\blk00000003/blk00000004/sig00001bbb ), + .I2(\blk00000003/blk00000004/sig00001ae8 ), + .I3(\blk00000003/blk00000004/sig00001bbc ), + .O(\blk00000003/blk00000004/sig00001ca7 ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \blk00000003/blk00000004/blk00001373 ( + .I0(ce), + .I1(\blk00000003/blk00000004/sig00001ca5 ), + .O(\blk00000003/blk00000004/sig00001ca6 ) + ); + LUT4 #( + .INIT ( 16'hE040 )) + \blk00000003/blk00000004/blk00001372 ( + .I0(\blk00000003/blk00000004/sig000002b0 ), + .I1(\blk00000003/blk00000004/sig00001bb6 ), + .I2(\blk00000003/blk00000004/sig00001ae8 ), + .I3(\blk00000003/blk00000004/sig00001bb7 ), + .O(\blk00000003/blk00000004/sig00001ca4 ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \blk00000003/blk00000004/blk00001371 ( + .I0(ce), + .I1(\blk00000003/blk00000004/sig00001ca2 ), + .O(\blk00000003/blk00000004/sig00001ca3 ) + ); + LUT4 #( + .INIT ( 16'hE040 )) + \blk00000003/blk00000004/blk00001370 ( + .I0(\blk00000003/blk00000004/sig000002b0 ), + .I1(\blk00000003/blk00000004/sig00001bb1 ), + .I2(\blk00000003/blk00000004/sig00001ae8 ), + .I3(\blk00000003/blk00000004/sig00001bb2 ), + .O(\blk00000003/blk00000004/sig00001ca1 ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \blk00000003/blk00000004/blk0000136f ( + .I0(ce), + .I1(\blk00000003/blk00000004/sig00001c9f ), + .O(\blk00000003/blk00000004/sig00001ca0 ) + ); + LUT4 #( + .INIT ( 16'hE040 )) + \blk00000003/blk00000004/blk0000136e ( + .I0(\blk00000003/blk00000004/sig000002b0 ), + .I1(\blk00000003/blk00000004/sig00001bac ), + .I2(\blk00000003/blk00000004/sig00001ae8 ), + .I3(\blk00000003/blk00000004/sig00001bad ), + .O(\blk00000003/blk00000004/sig00001c9e ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \blk00000003/blk00000004/blk0000136d ( + .I0(ce), + .I1(\blk00000003/blk00000004/sig00001c9c ), + .O(\blk00000003/blk00000004/sig00001c9d ) + ); + LUT4 #( + .INIT ( 16'hE040 )) + \blk00000003/blk00000004/blk0000136c ( + .I0(\blk00000003/blk00000004/sig000002b0 ), + .I1(\blk00000003/blk00000004/sig00001ba7 ), + .I2(\blk00000003/blk00000004/sig00001ae8 ), + .I3(\blk00000003/blk00000004/sig00001ba8 ), + .O(\blk00000003/blk00000004/sig00001c9b ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \blk00000003/blk00000004/blk0000136b ( + .I0(ce), + .I1(\blk00000003/blk00000004/sig00001c99 ), + .O(\blk00000003/blk00000004/sig00001c9a ) + ); + LUT4 #( + .INIT ( 16'hE040 )) + \blk00000003/blk00000004/blk0000136a ( + .I0(\blk00000003/blk00000004/sig000002b0 ), + .I1(\blk00000003/blk00000004/sig00001ba2 ), + .I2(\blk00000003/blk00000004/sig00001ae8 ), + .I3(\blk00000003/blk00000004/sig00001ba3 ), + .O(\blk00000003/blk00000004/sig00001c98 ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \blk00000003/blk00000004/blk00001369 ( + .I0(ce), + .I1(\blk00000003/blk00000004/sig00001c96 ), + .O(\blk00000003/blk00000004/sig00001c97 ) + ); + LUT4 #( + .INIT ( 16'hE040 )) + \blk00000003/blk00000004/blk00001368 ( + .I0(\blk00000003/blk00000004/sig000002b0 ), + .I1(\blk00000003/blk00000004/sig00001b9d ), + .I2(\blk00000003/blk00000004/sig00001ae8 ), + .I3(\blk00000003/blk00000004/sig00001b9e ), + .O(\blk00000003/blk00000004/sig00001c95 ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \blk00000003/blk00000004/blk00001367 ( + .I0(ce), + .I1(\blk00000003/blk00000004/sig00001c93 ), + .O(\blk00000003/blk00000004/sig00001c94 ) + ); + LUT4 #( + .INIT ( 16'hE040 )) + \blk00000003/blk00000004/blk00001366 ( + .I0(\blk00000003/blk00000004/sig000002b0 ), + .I1(\blk00000003/blk00000004/sig00001b98 ), + .I2(\blk00000003/blk00000004/sig00001ae8 ), + .I3(\blk00000003/blk00000004/sig00001b99 ), + .O(\blk00000003/blk00000004/sig00001c92 ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \blk00000003/blk00000004/blk00001365 ( + .I0(ce), + .I1(\blk00000003/blk00000004/sig00001c90 ), + .O(\blk00000003/blk00000004/sig00001c91 ) + ); + LUT4 #( + .INIT ( 16'hE040 )) + \blk00000003/blk00000004/blk00001364 ( + .I0(\blk00000003/blk00000004/sig000002b0 ), + .I1(\blk00000003/blk00000004/sig00001b93 ), + .I2(\blk00000003/blk00000004/sig00001ae8 ), + .I3(\blk00000003/blk00000004/sig00001b94 ), + .O(\blk00000003/blk00000004/sig00001c8f ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \blk00000003/blk00000004/blk00001363 ( + .I0(ce), + .I1(\blk00000003/blk00000004/sig00001c8d ), + .O(\blk00000003/blk00000004/sig00001c8e ) + ); + LUT4 #( + .INIT ( 16'hE040 )) + \blk00000003/blk00000004/blk00001362 ( + .I0(\blk00000003/blk00000004/sig000002b0 ), + .I1(\blk00000003/blk00000004/sig00001b8e ), + .I2(\blk00000003/blk00000004/sig00001ae8 ), + .I3(\blk00000003/blk00000004/sig00001b8f ), + .O(\blk00000003/blk00000004/sig00001c8c ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \blk00000003/blk00000004/blk00001361 ( + .I0(ce), + .I1(\blk00000003/blk00000004/sig00001c8a ), + .O(\blk00000003/blk00000004/sig00001c8b ) + ); + LUT4 #( + .INIT ( 16'hE040 )) + \blk00000003/blk00000004/blk00001360 ( + .I0(\blk00000003/blk00000004/sig000002b0 ), + .I1(\blk00000003/blk00000004/sig00001b89 ), + .I2(\blk00000003/blk00000004/sig00001ae8 ), + .I3(\blk00000003/blk00000004/sig00001b8a ), + .O(\blk00000003/blk00000004/sig00001c89 ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \blk00000003/blk00000004/blk0000135f ( + .I0(ce), + .I1(\blk00000003/blk00000004/sig00001c87 ), + .O(\blk00000003/blk00000004/sig00001c88 ) + ); + LUT4 #( + .INIT ( 16'hE040 )) + \blk00000003/blk00000004/blk0000135e ( + .I0(\blk00000003/blk00000004/sig000002b0 ), + .I1(\blk00000003/blk00000004/sig00001b84 ), + .I2(\blk00000003/blk00000004/sig00001ae8 ), + .I3(\blk00000003/blk00000004/sig00001b85 ), + .O(\blk00000003/blk00000004/sig00001c86 ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \blk00000003/blk00000004/blk0000135d ( + .I0(ce), + .I1(\blk00000003/blk00000004/sig00001c84 ), + .O(\blk00000003/blk00000004/sig00001c85 ) + ); + LUT4 #( + .INIT ( 16'hE040 )) + \blk00000003/blk00000004/blk0000135c ( + .I0(\blk00000003/blk00000004/sig000002b0 ), + .I1(\blk00000003/blk00000004/sig00001b7f ), + .I2(\blk00000003/blk00000004/sig00001ae8 ), + .I3(\blk00000003/blk00000004/sig00001b80 ), + .O(\blk00000003/blk00000004/sig00001c83 ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \blk00000003/blk00000004/blk0000135b ( + .I0(ce), + .I1(\blk00000003/blk00000004/sig00001c81 ), + .O(\blk00000003/blk00000004/sig00001c82 ) + ); + LUT4 #( + .INIT ( 16'hE040 )) + \blk00000003/blk00000004/blk0000135a ( + .I0(\blk00000003/blk00000004/sig000002b0 ), + .I1(\blk00000003/blk00000004/sig00001b7a ), + .I2(\blk00000003/blk00000004/sig00001ae8 ), + .I3(\blk00000003/blk00000004/sig00001b7b ), + .O(\blk00000003/blk00000004/sig00001c80 ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \blk00000003/blk00000004/blk00001359 ( + .I0(ce), + .I1(\blk00000003/blk00000004/sig00001c7e ), + .O(\blk00000003/blk00000004/sig00001c7f ) + ); + LUT4 #( + .INIT ( 16'hE040 )) + \blk00000003/blk00000004/blk00001358 ( + .I0(\blk00000003/blk00000004/sig000002b0 ), + .I1(\blk00000003/blk00000004/sig00001b75 ), + .I2(\blk00000003/blk00000004/sig00001ae8 ), + .I3(\blk00000003/blk00000004/sig00001b76 ), + .O(\blk00000003/blk00000004/sig00001c7d ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \blk00000003/blk00000004/blk00001357 ( + .I0(ce), + .I1(\blk00000003/blk00000004/sig00001c7b ), + .O(\blk00000003/blk00000004/sig00001c7c ) + ); + LUT4 #( + .INIT ( 16'hE040 )) + \blk00000003/blk00000004/blk00001356 ( + .I0(\blk00000003/blk00000004/sig000002b0 ), + .I1(\blk00000003/blk00000004/sig00001b70 ), + .I2(\blk00000003/blk00000004/sig00001ae8 ), + .I3(\blk00000003/blk00000004/sig00001b71 ), + .O(\blk00000003/blk00000004/sig00001c7a ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \blk00000003/blk00000004/blk00001355 ( + .I0(ce), + .I1(\blk00000003/blk00000004/sig00001c78 ), + .O(\blk00000003/blk00000004/sig00001c79 ) + ); + LUT4 #( + .INIT ( 16'hE040 )) + \blk00000003/blk00000004/blk00001354 ( + .I0(\blk00000003/blk00000004/sig000002b0 ), + .I1(\blk00000003/blk00000004/sig00001b6b ), + .I2(\blk00000003/blk00000004/sig00001ae8 ), + .I3(\blk00000003/blk00000004/sig00001b6c ), + .O(\blk00000003/blk00000004/sig00001c77 ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \blk00000003/blk00000004/blk00001353 ( + .I0(ce), + .I1(\blk00000003/blk00000004/sig00001c75 ), + .O(\blk00000003/blk00000004/sig00001c76 ) + ); + LUT4 #( + .INIT ( 16'hE040 )) + \blk00000003/blk00000004/blk00001352 ( + .I0(\blk00000003/blk00000004/sig000002b0 ), + .I1(\blk00000003/blk00000004/sig00001b66 ), + .I2(\blk00000003/blk00000004/sig00001ae8 ), + .I3(\blk00000003/blk00000004/sig00001b67 ), + .O(\blk00000003/blk00000004/sig00001c74 ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \blk00000003/blk00000004/blk00001351 ( + .I0(ce), + .I1(\blk00000003/blk00000004/sig00001c72 ), + .O(\blk00000003/blk00000004/sig00001c73 ) + ); + LUT4 #( + .INIT ( 16'hE040 )) + \blk00000003/blk00000004/blk00001350 ( + .I0(\blk00000003/blk00000004/sig000002b0 ), + .I1(\blk00000003/blk00000004/sig00001b61 ), + .I2(\blk00000003/blk00000004/sig00001ae8 ), + .I3(\blk00000003/blk00000004/sig00001b62 ), + .O(\blk00000003/blk00000004/sig00001c71 ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \blk00000003/blk00000004/blk0000134f ( + .I0(ce), + .I1(\blk00000003/blk00000004/sig00001c6f ), + .O(\blk00000003/blk00000004/sig00001c70 ) + ); + LUT4 #( + .INIT ( 16'hE040 )) + \blk00000003/blk00000004/blk0000134e ( + .I0(\blk00000003/blk00000004/sig000002b0 ), + .I1(\blk00000003/blk00000004/sig00001b5c ), + .I2(\blk00000003/blk00000004/sig00001ae8 ), + .I3(\blk00000003/blk00000004/sig00001b5d ), + .O(\blk00000003/blk00000004/sig00001c6e ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \blk00000003/blk00000004/blk0000134d ( + .I0(ce), + .I1(\blk00000003/blk00000004/sig00001c6c ), + .O(\blk00000003/blk00000004/sig00001c6d ) + ); + LUT4 #( + .INIT ( 16'hE040 )) + \blk00000003/blk00000004/blk0000134c ( + .I0(\blk00000003/blk00000004/sig000002b0 ), + .I1(\blk00000003/blk00000004/sig00001b57 ), + .I2(\blk00000003/blk00000004/sig00001ae8 ), + .I3(\blk00000003/blk00000004/sig00001b58 ), + .O(\blk00000003/blk00000004/sig00001c6b ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \blk00000003/blk00000004/blk0000134b ( + .I0(ce), + .I1(\blk00000003/blk00000004/sig00001c69 ), + .O(\blk00000003/blk00000004/sig00001c6a ) + ); + LUT4 #( + .INIT ( 16'hE040 )) + \blk00000003/blk00000004/blk0000134a ( + .I0(\blk00000003/blk00000004/sig000002b0 ), + .I1(\blk00000003/blk00000004/sig00001b52 ), + .I2(\blk00000003/blk00000004/sig00001ae8 ), + .I3(\blk00000003/blk00000004/sig00001b53 ), + .O(\blk00000003/blk00000004/sig00001c68 ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \blk00000003/blk00000004/blk00001349 ( + .I0(ce), + .I1(\blk00000003/blk00000004/sig00001c66 ), + .O(\blk00000003/blk00000004/sig00001c67 ) + ); + LUT4 #( + .INIT ( 16'hE040 )) + \blk00000003/blk00000004/blk00001348 ( + .I0(\blk00000003/blk00000004/sig000002b0 ), + .I1(\blk00000003/blk00000004/sig00001b4d ), + .I2(\blk00000003/blk00000004/sig00001ae8 ), + .I3(\blk00000003/blk00000004/sig00001b4e ), + .O(\blk00000003/blk00000004/sig00001c65 ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \blk00000003/blk00000004/blk00001347 ( + .I0(ce), + .I1(\blk00000003/blk00000004/sig00001c63 ), + .O(\blk00000003/blk00000004/sig00001c64 ) + ); + LUT4 #( + .INIT ( 16'hE040 )) + \blk00000003/blk00000004/blk00001346 ( + .I0(\blk00000003/blk00000004/sig000002b0 ), + .I1(\blk00000003/blk00000004/sig00001b48 ), + .I2(\blk00000003/blk00000004/sig00001ae8 ), + .I3(\blk00000003/blk00000004/sig00001b49 ), + .O(\blk00000003/blk00000004/sig00001c62 ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \blk00000003/blk00000004/blk00001345 ( + .I0(ce), + .I1(\blk00000003/blk00000004/sig00001c60 ), + .O(\blk00000003/blk00000004/sig00001c61 ) + ); + LUT4 #( + .INIT ( 16'hE040 )) + \blk00000003/blk00000004/blk00001344 ( + .I0(\blk00000003/blk00000004/sig000002b0 ), + .I1(\blk00000003/blk00000004/sig00001b43 ), + .I2(\blk00000003/blk00000004/sig00001ae8 ), + .I3(\blk00000003/blk00000004/sig00001b44 ), + .O(\blk00000003/blk00000004/sig00001c5f ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \blk00000003/blk00000004/blk00001343 ( + .I0(ce), + .I1(\blk00000003/blk00000004/sig00001c5d ), + .O(\blk00000003/blk00000004/sig00001c5e ) + ); + LUT4 #( + .INIT ( 16'hE040 )) + \blk00000003/blk00000004/blk00001342 ( + .I0(\blk00000003/blk00000004/sig000002b0 ), + .I1(\blk00000003/blk00000004/sig00001b3e ), + .I2(\blk00000003/blk00000004/sig00001ae8 ), + .I3(\blk00000003/blk00000004/sig00001b3f ), + .O(\blk00000003/blk00000004/sig00001c5c ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \blk00000003/blk00000004/blk00001341 ( + .I0(ce), + .I1(\blk00000003/blk00000004/sig00001c5a ), + .O(\blk00000003/blk00000004/sig00001c5b ) + ); + LUT4 #( + .INIT ( 16'hE040 )) + \blk00000003/blk00000004/blk00001340 ( + .I0(\blk00000003/blk00000004/sig000002b0 ), + .I1(\blk00000003/blk00000004/sig00001b39 ), + .I2(\blk00000003/blk00000004/sig00001ae8 ), + .I3(\blk00000003/blk00000004/sig00001b3a ), + .O(\blk00000003/blk00000004/sig00001c59 ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \blk00000003/blk00000004/blk0000133f ( + .I0(ce), + .I1(\blk00000003/blk00000004/sig00001c57 ), + .O(\blk00000003/blk00000004/sig00001c58 ) + ); + LUT4 #( + .INIT ( 16'hE040 )) + \blk00000003/blk00000004/blk0000133e ( + .I0(\blk00000003/blk00000004/sig000002b0 ), + .I1(\blk00000003/blk00000004/sig00001b34 ), + .I2(\blk00000003/blk00000004/sig00001ae8 ), + .I3(\blk00000003/blk00000004/sig00001b35 ), + .O(\blk00000003/blk00000004/sig00001c56 ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \blk00000003/blk00000004/blk0000133d ( + .I0(ce), + .I1(\blk00000003/blk00000004/sig00001c54 ), + .O(\blk00000003/blk00000004/sig00001c55 ) + ); + LUT4 #( + .INIT ( 16'hE040 )) + \blk00000003/blk00000004/blk0000133c ( + .I0(\blk00000003/blk00000004/sig000002b0 ), + .I1(\blk00000003/blk00000004/sig00001b2f ), + .I2(\blk00000003/blk00000004/sig00001ae8 ), + .I3(\blk00000003/blk00000004/sig00001b30 ), + .O(\blk00000003/blk00000004/sig00001c53 ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \blk00000003/blk00000004/blk0000133b ( + .I0(ce), + .I1(\blk00000003/blk00000004/sig00001c51 ), + .O(\blk00000003/blk00000004/sig00001c52 ) + ); + LUT4 #( + .INIT ( 16'hE040 )) + \blk00000003/blk00000004/blk0000133a ( + .I0(\blk00000003/blk00000004/sig000002b0 ), + .I1(\blk00000003/blk00000004/sig00001b2a ), + .I2(\blk00000003/blk00000004/sig00001ae8 ), + .I3(\blk00000003/blk00000004/sig00001b2b ), + .O(\blk00000003/blk00000004/sig00001c50 ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \blk00000003/blk00000004/blk00001339 ( + .I0(ce), + .I1(\blk00000003/blk00000004/sig00001c4e ), + .O(\blk00000003/blk00000004/sig00001c4f ) + ); + LUT4 #( + .INIT ( 16'hE040 )) + \blk00000003/blk00000004/blk00001338 ( + .I0(\blk00000003/blk00000004/sig000002b0 ), + .I1(\blk00000003/blk00000004/sig00001b25 ), + .I2(\blk00000003/blk00000004/sig00001ae8 ), + .I3(\blk00000003/blk00000004/sig00001b26 ), + .O(\blk00000003/blk00000004/sig00001c4d ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \blk00000003/blk00000004/blk00001337 ( + .I0(ce), + .I1(\blk00000003/blk00000004/sig00001c4b ), + .O(\blk00000003/blk00000004/sig00001c4c ) + ); + LUT4 #( + .INIT ( 16'hE040 )) + \blk00000003/blk00000004/blk00001336 ( + .I0(\blk00000003/blk00000004/sig000002b0 ), + .I1(\blk00000003/blk00000004/sig00001b20 ), + .I2(\blk00000003/blk00000004/sig00001ae8 ), + .I3(\blk00000003/blk00000004/sig00001b21 ), + .O(\blk00000003/blk00000004/sig00001c4a ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \blk00000003/blk00000004/blk00001335 ( + .I0(ce), + .I1(\blk00000003/blk00000004/sig00001c48 ), + .O(\blk00000003/blk00000004/sig00001c49 ) + ); + LUT4 #( + .INIT ( 16'hE040 )) + \blk00000003/blk00000004/blk00001334 ( + .I0(\blk00000003/blk00000004/sig000002b0 ), + .I1(\blk00000003/blk00000004/sig00001b1b ), + .I2(\blk00000003/blk00000004/sig00001ae8 ), + .I3(\blk00000003/blk00000004/sig00001b1c ), + .O(\blk00000003/blk00000004/sig00001c47 ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \blk00000003/blk00000004/blk00001333 ( + .I0(ce), + .I1(\blk00000003/blk00000004/sig00001c45 ), + .O(\blk00000003/blk00000004/sig00001c46 ) + ); + LUT4 #( + .INIT ( 16'hE040 )) + \blk00000003/blk00000004/blk00001332 ( + .I0(\blk00000003/blk00000004/sig000002b0 ), + .I1(\blk00000003/blk00000004/sig00001b16 ), + .I2(\blk00000003/blk00000004/sig00001ae8 ), + .I3(\blk00000003/blk00000004/sig00001b17 ), + .O(\blk00000003/blk00000004/sig00001c44 ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \blk00000003/blk00000004/blk00001331 ( + .I0(ce), + .I1(\blk00000003/blk00000004/sig00001c42 ), + .O(\blk00000003/blk00000004/sig00001c43 ) + ); + LUT4 #( + .INIT ( 16'hE040 )) + \blk00000003/blk00000004/blk00001330 ( + .I0(\blk00000003/blk00000004/sig000002b0 ), + .I1(\blk00000003/blk00000004/sig00001b11 ), + .I2(\blk00000003/blk00000004/sig00001ae8 ), + .I3(\blk00000003/blk00000004/sig00001b12 ), + .O(\blk00000003/blk00000004/sig00001c41 ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \blk00000003/blk00000004/blk0000132f ( + .I0(ce), + .I1(\blk00000003/blk00000004/sig00001c3f ), + .O(\blk00000003/blk00000004/sig00001c40 ) + ); + LUT4 #( + .INIT ( 16'hE040 )) + \blk00000003/blk00000004/blk0000132e ( + .I0(\blk00000003/blk00000004/sig000002b0 ), + .I1(\blk00000003/blk00000004/sig00001b0c ), + .I2(\blk00000003/blk00000004/sig00001ae8 ), + .I3(\blk00000003/blk00000004/sig00001b0d ), + .O(\blk00000003/blk00000004/sig00001c3e ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \blk00000003/blk00000004/blk0000132d ( + .I0(ce), + .I1(\blk00000003/blk00000004/sig00001c3c ), + .O(\blk00000003/blk00000004/sig00001c3d ) + ); + LUT4 #( + .INIT ( 16'hE040 )) + \blk00000003/blk00000004/blk0000132c ( + .I0(\blk00000003/blk00000004/sig000002b0 ), + .I1(\blk00000003/blk00000004/sig00001b07 ), + .I2(\blk00000003/blk00000004/sig00001ae8 ), + .I3(\blk00000003/blk00000004/sig00001b08 ), + .O(\blk00000003/blk00000004/sig00001c3b ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \blk00000003/blk00000004/blk0000132b ( + .I0(ce), + .I1(\blk00000003/blk00000004/sig00001c39 ), + .O(\blk00000003/blk00000004/sig00001c3a ) + ); + LUT4 #( + .INIT ( 16'hE040 )) + \blk00000003/blk00000004/blk0000132a ( + .I0(\blk00000003/blk00000004/sig000002b0 ), + .I1(\blk00000003/blk00000004/sig00001b02 ), + .I2(\blk00000003/blk00000004/sig00001ae8 ), + .I3(\blk00000003/blk00000004/sig00001b03 ), + .O(\blk00000003/blk00000004/sig00001c38 ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \blk00000003/blk00000004/blk00001329 ( + .I0(ce), + .I1(\blk00000003/blk00000004/sig00001c36 ), + .O(\blk00000003/blk00000004/sig00001c37 ) + ); + LUT4 #( + .INIT ( 16'hE040 )) + \blk00000003/blk00000004/blk00001328 ( + .I0(\blk00000003/blk00000004/sig000002b0 ), + .I1(\blk00000003/blk00000004/sig00001afd ), + .I2(\blk00000003/blk00000004/sig00001ae8 ), + .I3(\blk00000003/blk00000004/sig00001afe ), + .O(\blk00000003/blk00000004/sig00001c35 ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \blk00000003/blk00000004/blk00001327 ( + .I0(ce), + .I1(\blk00000003/blk00000004/sig00001c33 ), + .O(\blk00000003/blk00000004/sig00001c34 ) + ); + LUT4 #( + .INIT ( 16'hE040 )) + \blk00000003/blk00000004/blk00001326 ( + .I0(\blk00000003/blk00000004/sig000002b0 ), + .I1(\blk00000003/blk00000004/sig00001af8 ), + .I2(\blk00000003/blk00000004/sig00001ae8 ), + .I3(\blk00000003/blk00000004/sig00001af9 ), + .O(\blk00000003/blk00000004/sig00001c32 ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \blk00000003/blk00000004/blk00001325 ( + .I0(ce), + .I1(\blk00000003/blk00000004/sig00001c30 ), + .O(\blk00000003/blk00000004/sig00001c31 ) + ); + LUT4 #( + .INIT ( 16'hE040 )) + \blk00000003/blk00000004/blk00001324 ( + .I0(\blk00000003/blk00000004/sig000002b0 ), + .I1(\blk00000003/blk00000004/sig00001af3 ), + .I2(\blk00000003/blk00000004/sig00001ae8 ), + .I3(\blk00000003/blk00000004/sig00001af4 ), + .O(\blk00000003/blk00000004/sig00001c2f ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \blk00000003/blk00000004/blk00001323 ( + .I0(ce), + .I1(\blk00000003/blk00000004/sig00001c2d ), + .O(\blk00000003/blk00000004/sig00001c2e ) + ); + LUT4 #( + .INIT ( 16'hE040 )) + \blk00000003/blk00000004/blk00001322 ( + .I0(\blk00000003/blk00000004/sig000002b0 ), + .I1(\blk00000003/blk00000004/sig00001aee ), + .I2(\blk00000003/blk00000004/sig00001ae8 ), + .I3(\blk00000003/blk00000004/sig00001aef ), + .O(\blk00000003/blk00000004/sig00001c2c ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \blk00000003/blk00000004/blk00001321 ( + .I0(ce), + .I1(\blk00000003/blk00000004/sig00001c2a ), + .O(\blk00000003/blk00000004/sig00001c2b ) + ); + LUT4 #( + .INIT ( 16'hE040 )) + \blk00000003/blk00000004/blk00001320 ( + .I0(\blk00000003/blk00000004/sig000002b0 ), + .I1(\blk00000003/blk00000004/sig00001ae9 ), + .I2(\blk00000003/blk00000004/sig00001ae8 ), + .I3(\blk00000003/blk00000004/sig00001aea ), + .O(\blk00000003/blk00000004/sig00001c29 ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \blk00000003/blk00000004/blk0000131f ( + .I0(ce), + .I1(\blk00000003/blk00000004/sig00001c27 ), + .O(\blk00000003/blk00000004/sig00001c28 ) + ); + LUT4 #( + .INIT ( 16'hE040 )) + \blk00000003/blk00000004/blk0000131e ( + .I0(\blk00000003/blk00000004/sig000002ab ), + .I1(\blk00000003/blk00000004/sig00001c24 ), + .I2(\blk00000003/blk00000004/sig00001ae8 ), + .I3(\blk00000003/blk00000004/sig00001c25 ), + .O(\blk00000003/blk00000004/sig00001c26 ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \blk00000003/blk00000004/blk0000131d ( + .I0(ce), + .I1(\blk00000003/blk00000004/sig00001c22 ), + .O(\blk00000003/blk00000004/sig00001c23 ) + ); + LUT4 #( + .INIT ( 16'hE040 )) + \blk00000003/blk00000004/blk0000131c ( + .I0(\blk00000003/blk00000004/sig000002ab ), + .I1(\blk00000003/blk00000004/sig00001c1f ), + .I2(\blk00000003/blk00000004/sig00001ae8 ), + .I3(\blk00000003/blk00000004/sig00001c20 ), + .O(\blk00000003/blk00000004/sig00001c21 ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \blk00000003/blk00000004/blk0000131b ( + .I0(ce), + .I1(\blk00000003/blk00000004/sig00001c1d ), + .O(\blk00000003/blk00000004/sig00001c1e ) + ); + LUT4 #( + .INIT ( 16'hE040 )) + \blk00000003/blk00000004/blk0000131a ( + .I0(\blk00000003/blk00000004/sig000002ab ), + .I1(\blk00000003/blk00000004/sig00001c1a ), + .I2(\blk00000003/blk00000004/sig00001ae8 ), + .I3(\blk00000003/blk00000004/sig00001c1b ), + .O(\blk00000003/blk00000004/sig00001c1c ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \blk00000003/blk00000004/blk00001319 ( + .I0(ce), + .I1(\blk00000003/blk00000004/sig00001c18 ), + .O(\blk00000003/blk00000004/sig00001c19 ) + ); + LUT4 #( + .INIT ( 16'hE040 )) + \blk00000003/blk00000004/blk00001318 ( + .I0(\blk00000003/blk00000004/sig000002ab ), + .I1(\blk00000003/blk00000004/sig00001c15 ), + .I2(\blk00000003/blk00000004/sig00001ae8 ), + .I3(\blk00000003/blk00000004/sig00001c16 ), + .O(\blk00000003/blk00000004/sig00001c17 ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \blk00000003/blk00000004/blk00001317 ( + .I0(ce), + .I1(\blk00000003/blk00000004/sig00001c13 ), + .O(\blk00000003/blk00000004/sig00001c14 ) + ); + LUT4 #( + .INIT ( 16'hE040 )) + \blk00000003/blk00000004/blk00001316 ( + .I0(\blk00000003/blk00000004/sig000002ab ), + .I1(\blk00000003/blk00000004/sig00001c10 ), + .I2(\blk00000003/blk00000004/sig00001ae8 ), + .I3(\blk00000003/blk00000004/sig00001c11 ), + .O(\blk00000003/blk00000004/sig00001c12 ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \blk00000003/blk00000004/blk00001315 ( + .I0(ce), + .I1(\blk00000003/blk00000004/sig00001c0e ), + .O(\blk00000003/blk00000004/sig00001c0f ) + ); + LUT4 #( + .INIT ( 16'hE040 )) + \blk00000003/blk00000004/blk00001314 ( + .I0(\blk00000003/blk00000004/sig000002ab ), + .I1(\blk00000003/blk00000004/sig00001c0b ), + .I2(\blk00000003/blk00000004/sig00001ae8 ), + .I3(\blk00000003/blk00000004/sig00001c0c ), + .O(\blk00000003/blk00000004/sig00001c0d ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \blk00000003/blk00000004/blk00001313 ( + .I0(ce), + .I1(\blk00000003/blk00000004/sig00001c09 ), + .O(\blk00000003/blk00000004/sig00001c0a ) + ); + LUT4 #( + .INIT ( 16'hE040 )) + \blk00000003/blk00000004/blk00001312 ( + .I0(\blk00000003/blk00000004/sig000002ab ), + .I1(\blk00000003/blk00000004/sig00001c06 ), + .I2(\blk00000003/blk00000004/sig00001ae8 ), + .I3(\blk00000003/blk00000004/sig00001c07 ), + .O(\blk00000003/blk00000004/sig00001c08 ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \blk00000003/blk00000004/blk00001311 ( + .I0(ce), + .I1(\blk00000003/blk00000004/sig00001c04 ), + .O(\blk00000003/blk00000004/sig00001c05 ) + ); + LUT4 #( + .INIT ( 16'hE040 )) + \blk00000003/blk00000004/blk00001310 ( + .I0(\blk00000003/blk00000004/sig000002ab ), + .I1(\blk00000003/blk00000004/sig00001c01 ), + .I2(\blk00000003/blk00000004/sig00001ae8 ), + .I3(\blk00000003/blk00000004/sig00001c02 ), + .O(\blk00000003/blk00000004/sig00001c03 ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \blk00000003/blk00000004/blk0000130f ( + .I0(ce), + .I1(\blk00000003/blk00000004/sig00001bff ), + .O(\blk00000003/blk00000004/sig00001c00 ) + ); + LUT4 #( + .INIT ( 16'hE040 )) + \blk00000003/blk00000004/blk0000130e ( + .I0(\blk00000003/blk00000004/sig000002ab ), + .I1(\blk00000003/blk00000004/sig00001bfc ), + .I2(\blk00000003/blk00000004/sig00001ae8 ), + .I3(\blk00000003/blk00000004/sig00001bfd ), + .O(\blk00000003/blk00000004/sig00001bfe ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \blk00000003/blk00000004/blk0000130d ( + .I0(ce), + .I1(\blk00000003/blk00000004/sig00001bfa ), + .O(\blk00000003/blk00000004/sig00001bfb ) + ); + LUT4 #( + .INIT ( 16'hE040 )) + \blk00000003/blk00000004/blk0000130c ( + .I0(\blk00000003/blk00000004/sig000002ab ), + .I1(\blk00000003/blk00000004/sig00001bf7 ), + .I2(\blk00000003/blk00000004/sig00001ae8 ), + .I3(\blk00000003/blk00000004/sig00001bf8 ), + .O(\blk00000003/blk00000004/sig00001bf9 ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \blk00000003/blk00000004/blk0000130b ( + .I0(ce), + .I1(\blk00000003/blk00000004/sig00001bf5 ), + .O(\blk00000003/blk00000004/sig00001bf6 ) + ); + LUT4 #( + .INIT ( 16'hE040 )) + \blk00000003/blk00000004/blk0000130a ( + .I0(\blk00000003/blk00000004/sig000002ab ), + .I1(\blk00000003/blk00000004/sig00001bf2 ), + .I2(\blk00000003/blk00000004/sig00001ae8 ), + .I3(\blk00000003/blk00000004/sig00001bf3 ), + .O(\blk00000003/blk00000004/sig00001bf4 ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \blk00000003/blk00000004/blk00001309 ( + .I0(ce), + .I1(\blk00000003/blk00000004/sig00001bf0 ), + .O(\blk00000003/blk00000004/sig00001bf1 ) + ); + LUT4 #( + .INIT ( 16'hE040 )) + \blk00000003/blk00000004/blk00001308 ( + .I0(\blk00000003/blk00000004/sig000002ab ), + .I1(\blk00000003/blk00000004/sig00001bed ), + .I2(\blk00000003/blk00000004/sig00001ae8 ), + .I3(\blk00000003/blk00000004/sig00001bee ), + .O(\blk00000003/blk00000004/sig00001bef ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \blk00000003/blk00000004/blk00001307 ( + .I0(ce), + .I1(\blk00000003/blk00000004/sig00001beb ), + .O(\blk00000003/blk00000004/sig00001bec ) + ); + LUT4 #( + .INIT ( 16'hE040 )) + \blk00000003/blk00000004/blk00001306 ( + .I0(\blk00000003/blk00000004/sig000002ab ), + .I1(\blk00000003/blk00000004/sig00001be8 ), + .I2(\blk00000003/blk00000004/sig00001ae8 ), + .I3(\blk00000003/blk00000004/sig00001be9 ), + .O(\blk00000003/blk00000004/sig00001bea ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \blk00000003/blk00000004/blk00001305 ( + .I0(ce), + .I1(\blk00000003/blk00000004/sig00001be6 ), + .O(\blk00000003/blk00000004/sig00001be7 ) + ); + LUT4 #( + .INIT ( 16'hE040 )) + \blk00000003/blk00000004/blk00001304 ( + .I0(\blk00000003/blk00000004/sig000002ab ), + .I1(\blk00000003/blk00000004/sig00001be3 ), + .I2(\blk00000003/blk00000004/sig00001ae8 ), + .I3(\blk00000003/blk00000004/sig00001be4 ), + .O(\blk00000003/blk00000004/sig00001be5 ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \blk00000003/blk00000004/blk00001303 ( + .I0(ce), + .I1(\blk00000003/blk00000004/sig00001be1 ), + .O(\blk00000003/blk00000004/sig00001be2 ) + ); + LUT4 #( + .INIT ( 16'hE040 )) + \blk00000003/blk00000004/blk00001302 ( + .I0(\blk00000003/blk00000004/sig000002ab ), + .I1(\blk00000003/blk00000004/sig00001bde ), + .I2(\blk00000003/blk00000004/sig00001ae8 ), + .I3(\blk00000003/blk00000004/sig00001bdf ), + .O(\blk00000003/blk00000004/sig00001be0 ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \blk00000003/blk00000004/blk00001301 ( + .I0(ce), + .I1(\blk00000003/blk00000004/sig00001bdc ), + .O(\blk00000003/blk00000004/sig00001bdd ) + ); + LUT4 #( + .INIT ( 16'hE040 )) + \blk00000003/blk00000004/blk00001300 ( + .I0(\blk00000003/blk00000004/sig000002ab ), + .I1(\blk00000003/blk00000004/sig00001bd9 ), + .I2(\blk00000003/blk00000004/sig00001ae8 ), + .I3(\blk00000003/blk00000004/sig00001bda ), + .O(\blk00000003/blk00000004/sig00001bdb ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \blk00000003/blk00000004/blk000012ff ( + .I0(ce), + .I1(\blk00000003/blk00000004/sig00001bd7 ), + .O(\blk00000003/blk00000004/sig00001bd8 ) + ); + LUT4 #( + .INIT ( 16'hE040 )) + \blk00000003/blk00000004/blk000012fe ( + .I0(\blk00000003/blk00000004/sig000002ab ), + .I1(\blk00000003/blk00000004/sig00001bd4 ), + .I2(\blk00000003/blk00000004/sig00001ae8 ), + .I3(\blk00000003/blk00000004/sig00001bd5 ), + .O(\blk00000003/blk00000004/sig00001bd6 ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \blk00000003/blk00000004/blk000012fd ( + .I0(ce), + .I1(\blk00000003/blk00000004/sig00001bd2 ), + .O(\blk00000003/blk00000004/sig00001bd3 ) + ); + LUT4 #( + .INIT ( 16'hE040 )) + \blk00000003/blk00000004/blk000012fc ( + .I0(\blk00000003/blk00000004/sig000002ab ), + .I1(\blk00000003/blk00000004/sig00001bcf ), + .I2(\blk00000003/blk00000004/sig00001ae8 ), + .I3(\blk00000003/blk00000004/sig00001bd0 ), + .O(\blk00000003/blk00000004/sig00001bd1 ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \blk00000003/blk00000004/blk000012fb ( + .I0(ce), + .I1(\blk00000003/blk00000004/sig00001bcd ), + .O(\blk00000003/blk00000004/sig00001bce ) + ); + LUT4 #( + .INIT ( 16'hE040 )) + \blk00000003/blk00000004/blk000012fa ( + .I0(\blk00000003/blk00000004/sig000002ab ), + .I1(\blk00000003/blk00000004/sig00001bca ), + .I2(\blk00000003/blk00000004/sig00001ae8 ), + .I3(\blk00000003/blk00000004/sig00001bcb ), + .O(\blk00000003/blk00000004/sig00001bcc ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \blk00000003/blk00000004/blk000012f9 ( + .I0(ce), + .I1(\blk00000003/blk00000004/sig00001bc8 ), + .O(\blk00000003/blk00000004/sig00001bc9 ) + ); + LUT4 #( + .INIT ( 16'hE040 )) + \blk00000003/blk00000004/blk000012f8 ( + .I0(\blk00000003/blk00000004/sig000002ab ), + .I1(\blk00000003/blk00000004/sig00001bc5 ), + .I2(\blk00000003/blk00000004/sig00001ae8 ), + .I3(\blk00000003/blk00000004/sig00001bc6 ), + .O(\blk00000003/blk00000004/sig00001bc7 ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \blk00000003/blk00000004/blk000012f7 ( + .I0(ce), + .I1(\blk00000003/blk00000004/sig00001bc3 ), + .O(\blk00000003/blk00000004/sig00001bc4 ) + ); + LUT4 #( + .INIT ( 16'hE040 )) + \blk00000003/blk00000004/blk000012f6 ( + .I0(\blk00000003/blk00000004/sig000002ab ), + .I1(\blk00000003/blk00000004/sig00001bc0 ), + .I2(\blk00000003/blk00000004/sig00001ae8 ), + .I3(\blk00000003/blk00000004/sig00001bc1 ), + .O(\blk00000003/blk00000004/sig00001bc2 ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \blk00000003/blk00000004/blk000012f5 ( + .I0(ce), + .I1(\blk00000003/blk00000004/sig00001bbe ), + .O(\blk00000003/blk00000004/sig00001bbf ) + ); + LUT4 #( + .INIT ( 16'hE040 )) + \blk00000003/blk00000004/blk000012f4 ( + .I0(\blk00000003/blk00000004/sig000002ab ), + .I1(\blk00000003/blk00000004/sig00001bbb ), + .I2(\blk00000003/blk00000004/sig00001ae8 ), + .I3(\blk00000003/blk00000004/sig00001bbc ), + .O(\blk00000003/blk00000004/sig00001bbd ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \blk00000003/blk00000004/blk000012f3 ( + .I0(ce), + .I1(\blk00000003/blk00000004/sig00001bb9 ), + .O(\blk00000003/blk00000004/sig00001bba ) + ); + LUT4 #( + .INIT ( 16'hE040 )) + \blk00000003/blk00000004/blk000012f2 ( + .I0(\blk00000003/blk00000004/sig000002ab ), + .I1(\blk00000003/blk00000004/sig00001bb6 ), + .I2(\blk00000003/blk00000004/sig00001ae8 ), + .I3(\blk00000003/blk00000004/sig00001bb7 ), + .O(\blk00000003/blk00000004/sig00001bb8 ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \blk00000003/blk00000004/blk000012f1 ( + .I0(ce), + .I1(\blk00000003/blk00000004/sig00001bb4 ), + .O(\blk00000003/blk00000004/sig00001bb5 ) + ); + LUT4 #( + .INIT ( 16'hE040 )) + \blk00000003/blk00000004/blk000012f0 ( + .I0(\blk00000003/blk00000004/sig000002ab ), + .I1(\blk00000003/blk00000004/sig00001bb1 ), + .I2(\blk00000003/blk00000004/sig00001ae8 ), + .I3(\blk00000003/blk00000004/sig00001bb2 ), + .O(\blk00000003/blk00000004/sig00001bb3 ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \blk00000003/blk00000004/blk000012ef ( + .I0(ce), + .I1(\blk00000003/blk00000004/sig00001baf ), + .O(\blk00000003/blk00000004/sig00001bb0 ) + ); + LUT4 #( + .INIT ( 16'hE040 )) + \blk00000003/blk00000004/blk000012ee ( + .I0(\blk00000003/blk00000004/sig000002ab ), + .I1(\blk00000003/blk00000004/sig00001bac ), + .I2(\blk00000003/blk00000004/sig00001ae8 ), + .I3(\blk00000003/blk00000004/sig00001bad ), + .O(\blk00000003/blk00000004/sig00001bae ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \blk00000003/blk00000004/blk000012ed ( + .I0(ce), + .I1(\blk00000003/blk00000004/sig00001baa ), + .O(\blk00000003/blk00000004/sig00001bab ) + ); + LUT4 #( + .INIT ( 16'hE040 )) + \blk00000003/blk00000004/blk000012ec ( + .I0(\blk00000003/blk00000004/sig000002ab ), + .I1(\blk00000003/blk00000004/sig00001ba7 ), + .I2(\blk00000003/blk00000004/sig00001ae8 ), + .I3(\blk00000003/blk00000004/sig00001ba8 ), + .O(\blk00000003/blk00000004/sig00001ba9 ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \blk00000003/blk00000004/blk000012eb ( + .I0(ce), + .I1(\blk00000003/blk00000004/sig00001ba5 ), + .O(\blk00000003/blk00000004/sig00001ba6 ) + ); + LUT4 #( + .INIT ( 16'hE040 )) + \blk00000003/blk00000004/blk000012ea ( + .I0(\blk00000003/blk00000004/sig000002ab ), + .I1(\blk00000003/blk00000004/sig00001ba2 ), + .I2(\blk00000003/blk00000004/sig00001ae8 ), + .I3(\blk00000003/blk00000004/sig00001ba3 ), + .O(\blk00000003/blk00000004/sig00001ba4 ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \blk00000003/blk00000004/blk000012e9 ( + .I0(ce), + .I1(\blk00000003/blk00000004/sig00001ba0 ), + .O(\blk00000003/blk00000004/sig00001ba1 ) + ); + LUT4 #( + .INIT ( 16'hE040 )) + \blk00000003/blk00000004/blk000012e8 ( + .I0(\blk00000003/blk00000004/sig000002ab ), + .I1(\blk00000003/blk00000004/sig00001b9d ), + .I2(\blk00000003/blk00000004/sig00001ae8 ), + .I3(\blk00000003/blk00000004/sig00001b9e ), + .O(\blk00000003/blk00000004/sig00001b9f ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \blk00000003/blk00000004/blk000012e7 ( + .I0(ce), + .I1(\blk00000003/blk00000004/sig00001b9b ), + .O(\blk00000003/blk00000004/sig00001b9c ) + ); + LUT4 #( + .INIT ( 16'hE040 )) + \blk00000003/blk00000004/blk000012e6 ( + .I0(\blk00000003/blk00000004/sig000002ab ), + .I1(\blk00000003/blk00000004/sig00001b98 ), + .I2(\blk00000003/blk00000004/sig00001ae8 ), + .I3(\blk00000003/blk00000004/sig00001b99 ), + .O(\blk00000003/blk00000004/sig00001b9a ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \blk00000003/blk00000004/blk000012e5 ( + .I0(ce), + .I1(\blk00000003/blk00000004/sig00001b96 ), + .O(\blk00000003/blk00000004/sig00001b97 ) + ); + LUT4 #( + .INIT ( 16'hE040 )) + \blk00000003/blk00000004/blk000012e4 ( + .I0(\blk00000003/blk00000004/sig000002ab ), + .I1(\blk00000003/blk00000004/sig00001b93 ), + .I2(\blk00000003/blk00000004/sig00001ae8 ), + .I3(\blk00000003/blk00000004/sig00001b94 ), + .O(\blk00000003/blk00000004/sig00001b95 ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \blk00000003/blk00000004/blk000012e3 ( + .I0(ce), + .I1(\blk00000003/blk00000004/sig00001b91 ), + .O(\blk00000003/blk00000004/sig00001b92 ) + ); + LUT4 #( + .INIT ( 16'hE040 )) + \blk00000003/blk00000004/blk000012e2 ( + .I0(\blk00000003/blk00000004/sig000002ab ), + .I1(\blk00000003/blk00000004/sig00001b8e ), + .I2(\blk00000003/blk00000004/sig00001ae8 ), + .I3(\blk00000003/blk00000004/sig00001b8f ), + .O(\blk00000003/blk00000004/sig00001b90 ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \blk00000003/blk00000004/blk000012e1 ( + .I0(ce), + .I1(\blk00000003/blk00000004/sig00001b8c ), + .O(\blk00000003/blk00000004/sig00001b8d ) + ); + LUT4 #( + .INIT ( 16'hE040 )) + \blk00000003/blk00000004/blk000012e0 ( + .I0(\blk00000003/blk00000004/sig000002ab ), + .I1(\blk00000003/blk00000004/sig00001b89 ), + .I2(\blk00000003/blk00000004/sig00001ae8 ), + .I3(\blk00000003/blk00000004/sig00001b8a ), + .O(\blk00000003/blk00000004/sig00001b8b ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \blk00000003/blk00000004/blk000012df ( + .I0(ce), + .I1(\blk00000003/blk00000004/sig00001b87 ), + .O(\blk00000003/blk00000004/sig00001b88 ) + ); + LUT4 #( + .INIT ( 16'hE040 )) + \blk00000003/blk00000004/blk000012de ( + .I0(\blk00000003/blk00000004/sig000002ab ), + .I1(\blk00000003/blk00000004/sig00001b84 ), + .I2(\blk00000003/blk00000004/sig00001ae8 ), + .I3(\blk00000003/blk00000004/sig00001b85 ), + .O(\blk00000003/blk00000004/sig00001b86 ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \blk00000003/blk00000004/blk000012dd ( + .I0(ce), + .I1(\blk00000003/blk00000004/sig00001b82 ), + .O(\blk00000003/blk00000004/sig00001b83 ) + ); + LUT4 #( + .INIT ( 16'hE040 )) + \blk00000003/blk00000004/blk000012dc ( + .I0(\blk00000003/blk00000004/sig000002ab ), + .I1(\blk00000003/blk00000004/sig00001b7f ), + .I2(\blk00000003/blk00000004/sig00001ae8 ), + .I3(\blk00000003/blk00000004/sig00001b80 ), + .O(\blk00000003/blk00000004/sig00001b81 ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \blk00000003/blk00000004/blk000012db ( + .I0(ce), + .I1(\blk00000003/blk00000004/sig00001b7d ), + .O(\blk00000003/blk00000004/sig00001b7e ) + ); + LUT4 #( + .INIT ( 16'hE040 )) + \blk00000003/blk00000004/blk000012da ( + .I0(\blk00000003/blk00000004/sig000002ab ), + .I1(\blk00000003/blk00000004/sig00001b7a ), + .I2(\blk00000003/blk00000004/sig00001ae8 ), + .I3(\blk00000003/blk00000004/sig00001b7b ), + .O(\blk00000003/blk00000004/sig00001b7c ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \blk00000003/blk00000004/blk000012d9 ( + .I0(ce), + .I1(\blk00000003/blk00000004/sig00001b78 ), + .O(\blk00000003/blk00000004/sig00001b79 ) + ); + LUT4 #( + .INIT ( 16'hE040 )) + \blk00000003/blk00000004/blk000012d8 ( + .I0(\blk00000003/blk00000004/sig000002ab ), + .I1(\blk00000003/blk00000004/sig00001b75 ), + .I2(\blk00000003/blk00000004/sig00001ae8 ), + .I3(\blk00000003/blk00000004/sig00001b76 ), + .O(\blk00000003/blk00000004/sig00001b77 ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \blk00000003/blk00000004/blk000012d7 ( + .I0(ce), + .I1(\blk00000003/blk00000004/sig00001b73 ), + .O(\blk00000003/blk00000004/sig00001b74 ) + ); + LUT4 #( + .INIT ( 16'hE040 )) + \blk00000003/blk00000004/blk000012d6 ( + .I0(\blk00000003/blk00000004/sig000002ab ), + .I1(\blk00000003/blk00000004/sig00001b70 ), + .I2(\blk00000003/blk00000004/sig00001ae8 ), + .I3(\blk00000003/blk00000004/sig00001b71 ), + .O(\blk00000003/blk00000004/sig00001b72 ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \blk00000003/blk00000004/blk000012d5 ( + .I0(ce), + .I1(\blk00000003/blk00000004/sig00001b6e ), + .O(\blk00000003/blk00000004/sig00001b6f ) + ); + LUT4 #( + .INIT ( 16'hE040 )) + \blk00000003/blk00000004/blk000012d4 ( + .I0(\blk00000003/blk00000004/sig000002ab ), + .I1(\blk00000003/blk00000004/sig00001b6b ), + .I2(\blk00000003/blk00000004/sig00001ae8 ), + .I3(\blk00000003/blk00000004/sig00001b6c ), + .O(\blk00000003/blk00000004/sig00001b6d ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \blk00000003/blk00000004/blk000012d3 ( + .I0(ce), + .I1(\blk00000003/blk00000004/sig00001b69 ), + .O(\blk00000003/blk00000004/sig00001b6a ) + ); + LUT4 #( + .INIT ( 16'hE040 )) + \blk00000003/blk00000004/blk000012d2 ( + .I0(\blk00000003/blk00000004/sig000002ab ), + .I1(\blk00000003/blk00000004/sig00001b66 ), + .I2(\blk00000003/blk00000004/sig00001ae8 ), + .I3(\blk00000003/blk00000004/sig00001b67 ), + .O(\blk00000003/blk00000004/sig00001b68 ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \blk00000003/blk00000004/blk000012d1 ( + .I0(ce), + .I1(\blk00000003/blk00000004/sig00001b64 ), + .O(\blk00000003/blk00000004/sig00001b65 ) + ); + LUT4 #( + .INIT ( 16'hE040 )) + \blk00000003/blk00000004/blk000012d0 ( + .I0(\blk00000003/blk00000004/sig000002ab ), + .I1(\blk00000003/blk00000004/sig00001b61 ), + .I2(\blk00000003/blk00000004/sig00001ae8 ), + .I3(\blk00000003/blk00000004/sig00001b62 ), + .O(\blk00000003/blk00000004/sig00001b63 ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \blk00000003/blk00000004/blk000012cf ( + .I0(ce), + .I1(\blk00000003/blk00000004/sig00001b5f ), + .O(\blk00000003/blk00000004/sig00001b60 ) + ); + LUT4 #( + .INIT ( 16'hE040 )) + \blk00000003/blk00000004/blk000012ce ( + .I0(\blk00000003/blk00000004/sig000002ab ), + .I1(\blk00000003/blk00000004/sig00001b5c ), + .I2(\blk00000003/blk00000004/sig00001ae8 ), + .I3(\blk00000003/blk00000004/sig00001b5d ), + .O(\blk00000003/blk00000004/sig00001b5e ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \blk00000003/blk00000004/blk000012cd ( + .I0(ce), + .I1(\blk00000003/blk00000004/sig00001b5a ), + .O(\blk00000003/blk00000004/sig00001b5b ) + ); + LUT4 #( + .INIT ( 16'hE040 )) + \blk00000003/blk00000004/blk000012cc ( + .I0(\blk00000003/blk00000004/sig000002ab ), + .I1(\blk00000003/blk00000004/sig00001b57 ), + .I2(\blk00000003/blk00000004/sig00001ae8 ), + .I3(\blk00000003/blk00000004/sig00001b58 ), + .O(\blk00000003/blk00000004/sig00001b59 ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \blk00000003/blk00000004/blk000012cb ( + .I0(ce), + .I1(\blk00000003/blk00000004/sig00001b55 ), + .O(\blk00000003/blk00000004/sig00001b56 ) + ); + LUT4 #( + .INIT ( 16'hE040 )) + \blk00000003/blk00000004/blk000012ca ( + .I0(\blk00000003/blk00000004/sig000002ab ), + .I1(\blk00000003/blk00000004/sig00001b52 ), + .I2(\blk00000003/blk00000004/sig00001ae8 ), + .I3(\blk00000003/blk00000004/sig00001b53 ), + .O(\blk00000003/blk00000004/sig00001b54 ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \blk00000003/blk00000004/blk000012c9 ( + .I0(ce), + .I1(\blk00000003/blk00000004/sig00001b50 ), + .O(\blk00000003/blk00000004/sig00001b51 ) + ); + LUT4 #( + .INIT ( 16'hE040 )) + \blk00000003/blk00000004/blk000012c8 ( + .I0(\blk00000003/blk00000004/sig000002ab ), + .I1(\blk00000003/blk00000004/sig00001b4d ), + .I2(\blk00000003/blk00000004/sig00001ae8 ), + .I3(\blk00000003/blk00000004/sig00001b4e ), + .O(\blk00000003/blk00000004/sig00001b4f ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \blk00000003/blk00000004/blk000012c7 ( + .I0(ce), + .I1(\blk00000003/blk00000004/sig00001b4b ), + .O(\blk00000003/blk00000004/sig00001b4c ) + ); + LUT4 #( + .INIT ( 16'hE040 )) + \blk00000003/blk00000004/blk000012c6 ( + .I0(\blk00000003/blk00000004/sig000002ab ), + .I1(\blk00000003/blk00000004/sig00001b48 ), + .I2(\blk00000003/blk00000004/sig00001ae8 ), + .I3(\blk00000003/blk00000004/sig00001b49 ), + .O(\blk00000003/blk00000004/sig00001b4a ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \blk00000003/blk00000004/blk000012c5 ( + .I0(ce), + .I1(\blk00000003/blk00000004/sig00001b46 ), + .O(\blk00000003/blk00000004/sig00001b47 ) + ); + LUT4 #( + .INIT ( 16'hE040 )) + \blk00000003/blk00000004/blk000012c4 ( + .I0(\blk00000003/blk00000004/sig000002ab ), + .I1(\blk00000003/blk00000004/sig00001b43 ), + .I2(\blk00000003/blk00000004/sig00001ae8 ), + .I3(\blk00000003/blk00000004/sig00001b44 ), + .O(\blk00000003/blk00000004/sig00001b45 ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \blk00000003/blk00000004/blk000012c3 ( + .I0(ce), + .I1(\blk00000003/blk00000004/sig00001b41 ), + .O(\blk00000003/blk00000004/sig00001b42 ) + ); + LUT4 #( + .INIT ( 16'hE040 )) + \blk00000003/blk00000004/blk000012c2 ( + .I0(\blk00000003/blk00000004/sig000002ab ), + .I1(\blk00000003/blk00000004/sig00001b3e ), + .I2(\blk00000003/blk00000004/sig00001ae8 ), + .I3(\blk00000003/blk00000004/sig00001b3f ), + .O(\blk00000003/blk00000004/sig00001b40 ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \blk00000003/blk00000004/blk000012c1 ( + .I0(ce), + .I1(\blk00000003/blk00000004/sig00001b3c ), + .O(\blk00000003/blk00000004/sig00001b3d ) + ); + LUT4 #( + .INIT ( 16'hE040 )) + \blk00000003/blk00000004/blk000012c0 ( + .I0(\blk00000003/blk00000004/sig000002ab ), + .I1(\blk00000003/blk00000004/sig00001b39 ), + .I2(\blk00000003/blk00000004/sig00001ae8 ), + .I3(\blk00000003/blk00000004/sig00001b3a ), + .O(\blk00000003/blk00000004/sig00001b3b ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \blk00000003/blk00000004/blk000012bf ( + .I0(ce), + .I1(\blk00000003/blk00000004/sig00001b37 ), + .O(\blk00000003/blk00000004/sig00001b38 ) + ); + LUT4 #( + .INIT ( 16'hE040 )) + \blk00000003/blk00000004/blk000012be ( + .I0(\blk00000003/blk00000004/sig000002ab ), + .I1(\blk00000003/blk00000004/sig00001b34 ), + .I2(\blk00000003/blk00000004/sig00001ae8 ), + .I3(\blk00000003/blk00000004/sig00001b35 ), + .O(\blk00000003/blk00000004/sig00001b36 ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \blk00000003/blk00000004/blk000012bd ( + .I0(ce), + .I1(\blk00000003/blk00000004/sig00001b32 ), + .O(\blk00000003/blk00000004/sig00001b33 ) + ); + LUT4 #( + .INIT ( 16'hE040 )) + \blk00000003/blk00000004/blk000012bc ( + .I0(\blk00000003/blk00000004/sig000002ab ), + .I1(\blk00000003/blk00000004/sig00001b2f ), + .I2(\blk00000003/blk00000004/sig00001ae8 ), + .I3(\blk00000003/blk00000004/sig00001b30 ), + .O(\blk00000003/blk00000004/sig00001b31 ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \blk00000003/blk00000004/blk000012bb ( + .I0(ce), + .I1(\blk00000003/blk00000004/sig00001b2d ), + .O(\blk00000003/blk00000004/sig00001b2e ) + ); + LUT4 #( + .INIT ( 16'hE040 )) + \blk00000003/blk00000004/blk000012ba ( + .I0(\blk00000003/blk00000004/sig000002ab ), + .I1(\blk00000003/blk00000004/sig00001b2a ), + .I2(\blk00000003/blk00000004/sig00001ae8 ), + .I3(\blk00000003/blk00000004/sig00001b2b ), + .O(\blk00000003/blk00000004/sig00001b2c ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \blk00000003/blk00000004/blk000012b9 ( + .I0(ce), + .I1(\blk00000003/blk00000004/sig00001b28 ), + .O(\blk00000003/blk00000004/sig00001b29 ) + ); + LUT4 #( + .INIT ( 16'hE040 )) + \blk00000003/blk00000004/blk000012b8 ( + .I0(\blk00000003/blk00000004/sig000002ab ), + .I1(\blk00000003/blk00000004/sig00001b25 ), + .I2(\blk00000003/blk00000004/sig00001ae8 ), + .I3(\blk00000003/blk00000004/sig00001b26 ), + .O(\blk00000003/blk00000004/sig00001b27 ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \blk00000003/blk00000004/blk000012b7 ( + .I0(ce), + .I1(\blk00000003/blk00000004/sig00001b23 ), + .O(\blk00000003/blk00000004/sig00001b24 ) + ); + LUT4 #( + .INIT ( 16'hE040 )) + \blk00000003/blk00000004/blk000012b6 ( + .I0(\blk00000003/blk00000004/sig000002ab ), + .I1(\blk00000003/blk00000004/sig00001b20 ), + .I2(\blk00000003/blk00000004/sig00001ae8 ), + .I3(\blk00000003/blk00000004/sig00001b21 ), + .O(\blk00000003/blk00000004/sig00001b22 ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \blk00000003/blk00000004/blk000012b5 ( + .I0(ce), + .I1(\blk00000003/blk00000004/sig00001b1e ), + .O(\blk00000003/blk00000004/sig00001b1f ) + ); + LUT4 #( + .INIT ( 16'hE040 )) + \blk00000003/blk00000004/blk000012b4 ( + .I0(\blk00000003/blk00000004/sig000002ab ), + .I1(\blk00000003/blk00000004/sig00001b1b ), + .I2(\blk00000003/blk00000004/sig00001ae8 ), + .I3(\blk00000003/blk00000004/sig00001b1c ), + .O(\blk00000003/blk00000004/sig00001b1d ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \blk00000003/blk00000004/blk000012b3 ( + .I0(ce), + .I1(\blk00000003/blk00000004/sig00001b19 ), + .O(\blk00000003/blk00000004/sig00001b1a ) + ); + LUT4 #( + .INIT ( 16'hE040 )) + \blk00000003/blk00000004/blk000012b2 ( + .I0(\blk00000003/blk00000004/sig000002ab ), + .I1(\blk00000003/blk00000004/sig00001b16 ), + .I2(\blk00000003/blk00000004/sig00001ae8 ), + .I3(\blk00000003/blk00000004/sig00001b17 ), + .O(\blk00000003/blk00000004/sig00001b18 ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \blk00000003/blk00000004/blk000012b1 ( + .I0(ce), + .I1(\blk00000003/blk00000004/sig00001b14 ), + .O(\blk00000003/blk00000004/sig00001b15 ) + ); + LUT4 #( + .INIT ( 16'hE040 )) + \blk00000003/blk00000004/blk000012b0 ( + .I0(\blk00000003/blk00000004/sig000002ab ), + .I1(\blk00000003/blk00000004/sig00001b11 ), + .I2(\blk00000003/blk00000004/sig00001ae8 ), + .I3(\blk00000003/blk00000004/sig00001b12 ), + .O(\blk00000003/blk00000004/sig00001b13 ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \blk00000003/blk00000004/blk000012af ( + .I0(ce), + .I1(\blk00000003/blk00000004/sig00001b0f ), + .O(\blk00000003/blk00000004/sig00001b10 ) + ); + LUT4 #( + .INIT ( 16'hE040 )) + \blk00000003/blk00000004/blk000012ae ( + .I0(\blk00000003/blk00000004/sig000002ab ), + .I1(\blk00000003/blk00000004/sig00001b0c ), + .I2(\blk00000003/blk00000004/sig00001ae8 ), + .I3(\blk00000003/blk00000004/sig00001b0d ), + .O(\blk00000003/blk00000004/sig00001b0e ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \blk00000003/blk00000004/blk000012ad ( + .I0(ce), + .I1(\blk00000003/blk00000004/sig00001b0a ), + .O(\blk00000003/blk00000004/sig00001b0b ) + ); + LUT4 #( + .INIT ( 16'hE040 )) + \blk00000003/blk00000004/blk000012ac ( + .I0(\blk00000003/blk00000004/sig000002ab ), + .I1(\blk00000003/blk00000004/sig00001b07 ), + .I2(\blk00000003/blk00000004/sig00001ae8 ), + .I3(\blk00000003/blk00000004/sig00001b08 ), + .O(\blk00000003/blk00000004/sig00001b09 ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \blk00000003/blk00000004/blk000012ab ( + .I0(ce), + .I1(\blk00000003/blk00000004/sig00001b05 ), + .O(\blk00000003/blk00000004/sig00001b06 ) + ); + LUT4 #( + .INIT ( 16'hE040 )) + \blk00000003/blk00000004/blk000012aa ( + .I0(\blk00000003/blk00000004/sig000002ab ), + .I1(\blk00000003/blk00000004/sig00001b02 ), + .I2(\blk00000003/blk00000004/sig00001ae8 ), + .I3(\blk00000003/blk00000004/sig00001b03 ), + .O(\blk00000003/blk00000004/sig00001b04 ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \blk00000003/blk00000004/blk000012a9 ( + .I0(ce), + .I1(\blk00000003/blk00000004/sig00001b00 ), + .O(\blk00000003/blk00000004/sig00001b01 ) + ); + LUT4 #( + .INIT ( 16'hE040 )) + \blk00000003/blk00000004/blk000012a8 ( + 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.I0(\blk00000003/blk00000004/sig000002ab ), + .I1(\blk00000003/blk00000004/sig00001af3 ), + .I2(\blk00000003/blk00000004/sig00001ae8 ), + .I3(\blk00000003/blk00000004/sig00001af4 ), + .O(\blk00000003/blk00000004/sig00001af5 ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \blk00000003/blk00000004/blk000012a3 ( + .I0(ce), + .I1(\blk00000003/blk00000004/sig00001af1 ), + .O(\blk00000003/blk00000004/sig00001af2 ) + ); + LUT4 #( + .INIT ( 16'hE040 )) + \blk00000003/blk00000004/blk000012a2 ( + .I0(\blk00000003/blk00000004/sig000002ab ), + .I1(\blk00000003/blk00000004/sig00001aee ), + .I2(\blk00000003/blk00000004/sig00001ae8 ), + .I3(\blk00000003/blk00000004/sig00001aef ), + .O(\blk00000003/blk00000004/sig00001af0 ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \blk00000003/blk00000004/blk000012a1 ( + .I0(ce), + .I1(\blk00000003/blk00000004/sig00001aec ), + .O(\blk00000003/blk00000004/sig00001aed ) + ); + LUT4 #( + .INIT ( 16'hE040 )) + \blk00000003/blk00000004/blk000012a0 ( + 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.I3(\blk00000003/blk00000004/sig000005cf ), + .O(\blk00000003/blk00000004/sig00001aca ) + ); + LUT4 #( + .INIT ( 16'hDF45 )) + \blk00000003/blk00000004/blk00001280 ( + .I0(\blk00000003/blk00000004/sig000005c9 ), + .I1(\blk00000003/blk00000004/sig000005c5 ), + .I2(\blk00000003/blk00000004/sig000005cb ), + .I3(\blk00000003/blk00000004/sig000005c3 ), + .O(\blk00000003/blk00000004/sig00001ac8 ) + ); + LUT4 #( + .INIT ( 16'hDF45 )) + \blk00000003/blk00000004/blk0000127f ( + .I0(\blk00000003/blk00000004/sig000005bd ), + .I1(\blk00000003/blk00000004/sig000005b9 ), + .I2(\blk00000003/blk00000004/sig000005bf ), + .I3(\blk00000003/blk00000004/sig000005b7 ), + .O(\blk00000003/blk00000004/sig00001ac6 ) + ); + LUT4 #( + .INIT ( 16'hDF45 )) + \blk00000003/blk00000004/blk0000127e ( + .I0(\blk00000003/blk00000004/sig000005b1 ), + .I1(\blk00000003/blk00000004/sig000005ad ), + .I2(\blk00000003/blk00000004/sig000005b3 ), + .I3(\blk00000003/blk00000004/sig000005ab ), + .O(\blk00000003/blk00000004/sig00001ac4 ) + ); + LUT4 #( + .INIT ( 16'hDF45 )) + \blk00000003/blk00000004/blk0000127d ( + .I0(\blk00000003/blk00000004/sig000005a5 ), + .I1(\blk00000003/blk00000004/sig000005a1 ), + .I2(\blk00000003/blk00000004/sig000005a7 ), + .I3(\blk00000003/blk00000004/sig0000059f ), + .O(\blk00000003/blk00000004/sig00001ac2 ) + ); + LUT4 #( + .INIT ( 16'hDF45 )) + \blk00000003/blk00000004/blk0000127c ( + .I0(\blk00000003/blk00000004/sig00000599 ), + .I1(\blk00000003/blk00000004/sig00000595 ), + .I2(\blk00000003/blk00000004/sig0000059b ), + .I3(\blk00000003/blk00000004/sig00000593 ), + .O(\blk00000003/blk00000004/sig00001ac0 ) + ); + LUT4 #( + .INIT ( 16'hDF45 )) + \blk00000003/blk00000004/blk0000127b ( + .I0(\blk00000003/blk00000004/sig0000058d ), + .I1(\blk00000003/blk00000004/sig00000589 ), + .I2(\blk00000003/blk00000004/sig0000058f ), + .I3(\blk00000003/blk00000004/sig00000587 ), + .O(\blk00000003/blk00000004/sig00001abe ) + ); + LUT4 #( + .INIT ( 16'hDF45 )) + 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.I2(\blk00000003/blk00000004/sig00000547 ), + .I3(\blk00000003/blk00000004/sig0000053f ), + .O(\blk00000003/blk00000004/sig00001ab0 ) + ); + LUT4 #( + .INIT ( 16'hDF45 )) + \blk00000003/blk00000004/blk00001273 ( + .I0(\blk00000003/blk00000004/sig00000539 ), + .I1(\blk00000003/blk00000004/sig00000535 ), + .I2(\blk00000003/blk00000004/sig0000053b ), + .I3(\blk00000003/blk00000004/sig00000533 ), + .O(\blk00000003/blk00000004/sig00001aae ) + ); + LUT4 #( + .INIT ( 16'hDF45 )) + \blk00000003/blk00000004/blk00001272 ( + .I0(\blk00000003/blk00000004/sig0000052d ), + .I1(\blk00000003/blk00000004/sig00000529 ), + .I2(\blk00000003/blk00000004/sig0000052f ), + .I3(\blk00000003/blk00000004/sig00000527 ), + .O(\blk00000003/blk00000004/sig00001aac ) + ); + LUT4 #( + .INIT ( 16'hDF45 )) + \blk00000003/blk00000004/blk00001271 ( + .I0(\blk00000003/blk00000004/sig00000521 ), + .I1(\blk00000003/blk00000004/sig0000051d ), + .I2(\blk00000003/blk00000004/sig00000523 ), + .I3(\blk00000003/blk00000004/sig0000051b ), + .O(\blk00000003/blk00000004/sig00001aaa ) + ); + LUT4 #( + .INIT ( 16'hDF45 )) + \blk00000003/blk00000004/blk00001270 ( + .I0(\blk00000003/blk00000004/sig00000515 ), + .I1(\blk00000003/blk00000004/sig00000511 ), + .I2(\blk00000003/blk00000004/sig00000517 ), + .I3(\blk00000003/blk00000004/sig0000050f ), + .O(\blk00000003/blk00000004/sig00001aa8 ) + ); + LUT4 #( + .INIT ( 16'hDF45 )) + \blk00000003/blk00000004/blk0000126f ( + .I0(\blk00000003/blk00000004/sig00000509 ), + .I1(\blk00000003/blk00000004/sig00000505 ), + .I2(\blk00000003/blk00000004/sig0000050b ), + .I3(\blk00000003/blk00000004/sig00000503 ), + .O(\blk00000003/blk00000004/sig00001aa6 ) + ); + LUT4 #( + .INIT ( 16'hDF45 )) + \blk00000003/blk00000004/blk0000126e ( + .I0(\blk00000003/blk00000004/sig000004fd ), + .I1(\blk00000003/blk00000004/sig000004f9 ), + .I2(\blk00000003/blk00000004/sig000004ff ), + .I3(\blk00000003/blk00000004/sig000004f7 ), + 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\blk00000003/blk00000004/blk0000125a ( + .I0(\blk00000003/blk00000004/sig000004b5 ), + .I1(\blk00000003/blk00000004/sig000004b1 ), + .I2(\blk00000003/blk00000004/sig000004b7 ), + .I3(\blk00000003/blk00000004/sig000004af ), + .O(\blk00000003/blk00000004/sig00001a7c ) + ); + LUT4 #( + .INIT ( 16'hDF45 )) + \blk00000003/blk00000004/blk00001259 ( + .I0(\blk00000003/blk00000004/sig000004a9 ), + .I1(\blk00000003/blk00000004/sig000004a5 ), + .I2(\blk00000003/blk00000004/sig000004ab ), + .I3(\blk00000003/blk00000004/sig000004a3 ), + .O(\blk00000003/blk00000004/sig00001a7a ) + ); + LUT4 #( + .INIT ( 16'hDF45 )) + \blk00000003/blk00000004/blk00001258 ( + .I0(\blk00000003/blk00000004/sig0000049d ), + .I1(\blk00000003/blk00000004/sig00000499 ), + .I2(\blk00000003/blk00000004/sig0000049f ), + .I3(\blk00000003/blk00000004/sig00000497 ), + .O(\blk00000003/blk00000004/sig00001a78 ) + ); + LUT4 #( + .INIT ( 16'hDF45 )) + \blk00000003/blk00000004/blk00001257 ( + .I0(\blk00000003/blk00000004/sig00000491 ), + .I1(\blk00000003/blk00000004/sig0000048d ), + .I2(\blk00000003/blk00000004/sig00000493 ), + .I3(\blk00000003/blk00000004/sig0000048b ), + .O(\blk00000003/blk00000004/sig00001a76 ) + ); + LUT4 #( + .INIT ( 16'hDF45 )) + \blk00000003/blk00000004/blk00001256 ( + .I0(\blk00000003/blk00000004/sig00000485 ), + .I1(\blk00000003/blk00000004/sig00000481 ), + .I2(\blk00000003/blk00000004/sig00000487 ), + .I3(\blk00000003/blk00000004/sig0000047f ), + .O(\blk00000003/blk00000004/sig00001a74 ) + ); + LUT4 #( + .INIT ( 16'hDF45 )) + \blk00000003/blk00000004/blk00001255 ( + .I0(\blk00000003/blk00000004/sig00000479 ), + .I1(\blk00000003/blk00000004/sig00000475 ), + .I2(\blk00000003/blk00000004/sig0000047b ), + .I3(\blk00000003/blk00000004/sig00000473 ), + .O(\blk00000003/blk00000004/sig00001a72 ) + ); + LUT4 #( + .INIT ( 16'hDF45 )) + \blk00000003/blk00000004/blk00001254 ( + .I0(\blk00000003/blk00000004/sig0000046d ), + .I1(\blk00000003/blk00000004/sig00000469 ), + .I2(\blk00000003/blk00000004/sig0000046f ), + .I3(\blk00000003/blk00000004/sig00000467 ), + .O(\blk00000003/blk00000004/sig00001a70 ) + ); + LUT4 #( + .INIT ( 16'hDF45 )) + \blk00000003/blk00000004/blk00001253 ( + .I0(\blk00000003/blk00000004/sig00000461 ), + .I1(\blk00000003/blk00000004/sig0000045d ), + .I2(\blk00000003/blk00000004/sig00000463 ), + .I3(\blk00000003/blk00000004/sig0000045b ), + .O(\blk00000003/blk00000004/sig00001a6e ) + ); + LUT4 #( + .INIT ( 16'hDF45 )) + \blk00000003/blk00000004/blk00001252 ( + .I0(\blk00000003/blk00000004/sig0000040d ), + .I1(\blk00000003/blk00000004/sig00000409 ), + .I2(\blk00000003/blk00000004/sig0000040f ), + .I3(\blk00000003/blk00000004/sig00000407 ), + .O(\blk00000003/blk00000004/sig00001a6c ) + ); + LUT4 #( + .INIT ( 16'hDF45 )) + \blk00000003/blk00000004/blk00001251 ( + .I0(\blk00000003/blk00000004/sig00000401 ), + .I1(\blk00000003/blk00000004/sig000003fd ), + .I2(\blk00000003/blk00000004/sig00000403 ), + .I3(\blk00000003/blk00000004/sig000003fb ), + .O(\blk00000003/blk00000004/sig00001a6a ) + ); + LUT4 #( + .INIT ( 16'hDF45 )) + \blk00000003/blk00000004/blk00001250 ( + .I0(\blk00000003/blk00000004/sig000003f5 ), + .I1(\blk00000003/blk00000004/sig000003f1 ), + .I2(\blk00000003/blk00000004/sig000003f7 ), + .I3(\blk00000003/blk00000004/sig000003ef ), + .O(\blk00000003/blk00000004/sig00001a68 ) + ); + LUT4 #( + .INIT ( 16'hDF45 )) + \blk00000003/blk00000004/blk0000124f ( + .I0(\blk00000003/blk00000004/sig000003e9 ), + .I1(\blk00000003/blk00000004/sig000003e5 ), + .I2(\blk00000003/blk00000004/sig000003eb ), + .I3(\blk00000003/blk00000004/sig000003e3 ), + .O(\blk00000003/blk00000004/sig00001a66 ) + ); + LUT4 #( + .INIT ( 16'hDF45 )) + \blk00000003/blk00000004/blk0000124e ( + .I0(\blk00000003/blk00000004/sig000003dd ), + .I1(\blk00000003/blk00000004/sig000003d9 ), + .I2(\blk00000003/blk00000004/sig000003df ), + .I3(\blk00000003/blk00000004/sig000003d7 ), + .O(\blk00000003/blk00000004/sig00001a64 ) + ); + LUT4 #( + .INIT ( 16'hDF45 )) + \blk00000003/blk00000004/blk0000124d ( + .I0(\blk00000003/blk00000004/sig000003d1 ), + .I1(\blk00000003/blk00000004/sig000003cd ), + .I2(\blk00000003/blk00000004/sig000003d3 ), + .I3(\blk00000003/blk00000004/sig000003cb ), + .O(\blk00000003/blk00000004/sig00001a62 ) + ); + LUT4 #( + .INIT ( 16'hDF45 )) + \blk00000003/blk00000004/blk0000124c ( + .I0(\blk00000003/blk00000004/sig000003c5 ), + .I1(\blk00000003/blk00000004/sig000003c1 ), + .I2(\blk00000003/blk00000004/sig000003c7 ), + .I3(\blk00000003/blk00000004/sig000003bf ), + .O(\blk00000003/blk00000004/sig00001a60 ) + ); + LUT4 #( + .INIT ( 16'hDF45 )) + \blk00000003/blk00000004/blk0000124b ( + .I0(\blk00000003/blk00000004/sig000003b9 ), + .I1(\blk00000003/blk00000004/sig000003b5 ), + .I2(\blk00000003/blk00000004/sig000003bb ), + .I3(\blk00000003/blk00000004/sig000003b3 ), + .O(\blk00000003/blk00000004/sig00001a5e ) + ); + LUT4 #( + .INIT ( 16'hDF45 )) + \blk00000003/blk00000004/blk0000124a ( + .I0(\blk00000003/blk00000004/sig000003ad ), + .I1(\blk00000003/blk00000004/sig000003a9 ), + .I2(\blk00000003/blk00000004/sig000003af ), + .I3(\blk00000003/blk00000004/sig000003a7 ), + .O(\blk00000003/blk00000004/sig00001a5c ) + ); + LUT4 #( + .INIT ( 16'hDF45 )) + \blk00000003/blk00000004/blk00001249 ( + .I0(\blk00000003/blk00000004/sig000003a1 ), + .I1(\blk00000003/blk00000004/sig0000039d ), + .I2(\blk00000003/blk00000004/sig000003a3 ), + .I3(\blk00000003/blk00000004/sig0000039b ), + .O(\blk00000003/blk00000004/sig00001a5a ) + ); + LUT4 #( + .INIT ( 16'hDF45 )) + \blk00000003/blk00000004/blk00001248 ( + .I0(\blk00000003/blk00000004/sig00000395 ), + .I1(\blk00000003/blk00000004/sig00000391 ), + .I2(\blk00000003/blk00000004/sig00000397 ), + .I3(\blk00000003/blk00000004/sig0000038f ), + .O(\blk00000003/blk00000004/sig00001a58 ) + ); + LUT4 #( + .INIT ( 16'hDF45 )) + \blk00000003/blk00000004/blk00001247 ( + .I0(\blk00000003/blk00000004/sig00000389 ), + .I1(\blk00000003/blk00000004/sig00000385 ), + .I2(\blk00000003/blk00000004/sig0000038b ), + .I3(\blk00000003/blk00000004/sig00000383 ), + .O(\blk00000003/blk00000004/sig00001a56 ) + ); + LUT4 #( + .INIT ( 16'hDF45 )) + \blk00000003/blk00000004/blk00001246 ( + .I0(\blk00000003/blk00000004/sig0000037d ), + .I1(\blk00000003/blk00000004/sig00000379 ), + .I2(\blk00000003/blk00000004/sig0000037f ), + .I3(\blk00000003/blk00000004/sig00000377 ), + .O(\blk00000003/blk00000004/sig00001a54 ) + ); + LUT4 #( + .INIT ( 16'hDF45 )) + \blk00000003/blk00000004/blk00001245 ( + .I0(\blk00000003/blk00000004/sig00000371 ), + .I1(\blk00000003/blk00000004/sig0000036d ), + .I2(\blk00000003/blk00000004/sig00000373 ), + .I3(\blk00000003/blk00000004/sig0000036b ), + .O(\blk00000003/blk00000004/sig00001a52 ) + ); + LUT4 #( + .INIT ( 16'hDF45 )) + \blk00000003/blk00000004/blk00001244 ( + .I0(\blk00000003/blk00000004/sig00000365 ), + .I1(\blk00000003/blk00000004/sig00000361 ), + .I2(\blk00000003/blk00000004/sig00000367 ), + .I3(\blk00000003/blk00000004/sig0000035f ), + .O(\blk00000003/blk00000004/sig00001a50 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000004/blk00001243 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00001acd ), + .I2(\blk00000003/blk00000004/sig00000645 ), + .I3(\blk00000003/blk00000004/sig0000064b ), + .O(\blk00000003/blk00000004/sig000004ca ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000004/blk00001242 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00001acd ), + .I2(\blk00000003/blk00000004/sig00000647 ), + .I3(\blk00000003/blk00000004/sig0000064d ), + .O(\blk00000003/blk00000004/sig000004cc ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000004/blk00001241 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00001acd ), + .I2(\blk00000003/blk00000004/sig00000649 ), + .I3(\blk00000003/blk00000004/sig0000064f ), + .O(\blk00000003/blk00000004/sig000004ce ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000004/blk00001240 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00001acb ), + .I2(\blk00000003/blk00000004/sig000005cd ), + .I3(\blk00000003/blk00000004/sig000005d3 ), + .O(\blk00000003/blk00000004/sig0000048e ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000004/blk0000123f ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00001acb ), + .I2(\blk00000003/blk00000004/sig000005cf ), + .I3(\blk00000003/blk00000004/sig000005d5 ), + .O(\blk00000003/blk00000004/sig00000490 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000004/blk0000123e ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00001acb ), + .I2(\blk00000003/blk00000004/sig000005d1 ), + .I3(\blk00000003/blk00000004/sig000005d7 ), + .O(\blk00000003/blk00000004/sig00000492 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000004/blk0000123d ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00001ac9 ), + .I2(\blk00000003/blk00000004/sig000005c1 ), + .I3(\blk00000003/blk00000004/sig000005c7 ), + .O(\blk00000003/blk00000004/sig00000488 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000004/blk0000123c ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00001ac9 ), + .I2(\blk00000003/blk00000004/sig000005c3 ), + .I3(\blk00000003/blk00000004/sig000005c9 ), + .O(\blk00000003/blk00000004/sig0000048a ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000004/blk0000123b ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00001ac9 ), + .I2(\blk00000003/blk00000004/sig000005c5 ), + .I3(\blk00000003/blk00000004/sig000005cb ), + .O(\blk00000003/blk00000004/sig0000048c ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000004/blk0000123a ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00001ac7 ), + .I2(\blk00000003/blk00000004/sig000005b5 ), + .I3(\blk00000003/blk00000004/sig000005bb ), + .O(\blk00000003/blk00000004/sig00000482 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000004/blk00001239 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00001ac7 ), + .I2(\blk00000003/blk00000004/sig000005b7 ), + .I3(\blk00000003/blk00000004/sig000005bd ), + .O(\blk00000003/blk00000004/sig00000484 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000004/blk00001238 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00001ac7 ), + .I2(\blk00000003/blk00000004/sig000005b9 ), + .I3(\blk00000003/blk00000004/sig000005bf ), + .O(\blk00000003/blk00000004/sig00000486 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000004/blk00001237 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00001ac5 ), + .I2(\blk00000003/blk00000004/sig000005a9 ), + .I3(\blk00000003/blk00000004/sig000005af ), + .O(\blk00000003/blk00000004/sig0000047c ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000004/blk00001236 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00001ac5 ), + .I2(\blk00000003/blk00000004/sig000005ab ), + .I3(\blk00000003/blk00000004/sig000005b1 ), + .O(\blk00000003/blk00000004/sig0000047e ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000004/blk00001235 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00001ac5 ), + .I2(\blk00000003/blk00000004/sig000005ad ), + .I3(\blk00000003/blk00000004/sig000005b3 ), + .O(\blk00000003/blk00000004/sig00000480 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000004/blk00001234 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00001ac3 ), + .I2(\blk00000003/blk00000004/sig0000059d ), + .I3(\blk00000003/blk00000004/sig000005a3 ), + .O(\blk00000003/blk00000004/sig00000476 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000004/blk00001233 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00001ac3 ), + .I2(\blk00000003/blk00000004/sig0000059f ), + .I3(\blk00000003/blk00000004/sig000005a5 ), + .O(\blk00000003/blk00000004/sig00000478 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000004/blk00001232 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00001ac3 ), + .I2(\blk00000003/blk00000004/sig000005a1 ), + .I3(\blk00000003/blk00000004/sig000005a7 ), + .O(\blk00000003/blk00000004/sig0000047a ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000004/blk00001231 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00001ac1 ), + .I2(\blk00000003/blk00000004/sig00000591 ), + .I3(\blk00000003/blk00000004/sig00000597 ), + .O(\blk00000003/blk00000004/sig00000470 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000004/blk00001230 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00001ac1 ), + .I2(\blk00000003/blk00000004/sig00000593 ), + .I3(\blk00000003/blk00000004/sig00000599 ), + .O(\blk00000003/blk00000004/sig00000472 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000004/blk0000122f ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00001ac1 ), + .I2(\blk00000003/blk00000004/sig00000595 ), + .I3(\blk00000003/blk00000004/sig0000059b ), + .O(\blk00000003/blk00000004/sig00000474 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000004/blk0000122e ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00001abf ), + .I2(\blk00000003/blk00000004/sig00000585 ), + .I3(\blk00000003/blk00000004/sig0000058b ), + .O(\blk00000003/blk00000004/sig0000046a ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000004/blk0000122d ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00001abf ), + .I2(\blk00000003/blk00000004/sig00000587 ), + .I3(\blk00000003/blk00000004/sig0000058d ), + .O(\blk00000003/blk00000004/sig0000046c ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000004/blk0000122c ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00001abf ), + .I2(\blk00000003/blk00000004/sig00000589 ), + .I3(\blk00000003/blk00000004/sig0000058f ), + .O(\blk00000003/blk00000004/sig0000046e ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000004/blk0000122b ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00001abd ), + .I2(\blk00000003/blk00000004/sig00000579 ), + .I3(\blk00000003/blk00000004/sig0000057f ), + .O(\blk00000003/blk00000004/sig00000464 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000004/blk0000122a ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00001abd ), + .I2(\blk00000003/blk00000004/sig0000057b ), + .I3(\blk00000003/blk00000004/sig00000581 ), + .O(\blk00000003/blk00000004/sig00000466 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000004/blk00001229 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00001abd ), + .I2(\blk00000003/blk00000004/sig0000057d ), + .I3(\blk00000003/blk00000004/sig00000583 ), + .O(\blk00000003/blk00000004/sig00000468 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000004/blk00001228 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00001abb ), + .I2(\blk00000003/blk00000004/sig0000056d ), + .I3(\blk00000003/blk00000004/sig00000573 ), + .O(\blk00000003/blk00000004/sig0000045e ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000004/blk00001227 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00001abb ), + .I2(\blk00000003/blk00000004/sig0000056f ), + .I3(\blk00000003/blk00000004/sig00000575 ), + .O(\blk00000003/blk00000004/sig00000460 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000004/blk00001226 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00001abb ), + .I2(\blk00000003/blk00000004/sig00000571 ), + .I3(\blk00000003/blk00000004/sig00000577 ), + .O(\blk00000003/blk00000004/sig00000462 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000004/blk00001225 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00001ab9 ), + .I2(\blk00000003/blk00000004/sig00000561 ), + .I3(\blk00000003/blk00000004/sig00000567 ), + .O(\blk00000003/blk00000004/sig00000458 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000004/blk00001224 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00001ab9 ), + .I2(\blk00000003/blk00000004/sig00000563 ), + .I3(\blk00000003/blk00000004/sig00000569 ), + .O(\blk00000003/blk00000004/sig0000045a ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000004/blk00001223 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00001ab9 ), + .I2(\blk00000003/blk00000004/sig00000565 ), + .I3(\blk00000003/blk00000004/sig0000056b ), + .O(\blk00000003/blk00000004/sig0000045c ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000004/blk00001222 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00001ab7 ), + .I2(\blk00000003/blk00000004/sig00000639 ), + .I3(\blk00000003/blk00000004/sig0000063f ), + .O(\blk00000003/blk00000004/sig000004c4 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000004/blk00001221 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00001ab7 ), + .I2(\blk00000003/blk00000004/sig0000063b ), + .I3(\blk00000003/blk00000004/sig00000641 ), + .O(\blk00000003/blk00000004/sig000004c6 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000004/blk00001220 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00001ab7 ), + .I2(\blk00000003/blk00000004/sig0000063d ), + .I3(\blk00000003/blk00000004/sig00000643 ), + .O(\blk00000003/blk00000004/sig000004c8 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000004/blk0000121f ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00001ab5 ), + .I2(\blk00000003/blk00000004/sig00000555 ), + .I3(\blk00000003/blk00000004/sig0000055b ), + .O(\blk00000003/blk00000004/sig00000452 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000004/blk0000121e ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00001ab5 ), + .I2(\blk00000003/blk00000004/sig00000557 ), + .I3(\blk00000003/blk00000004/sig0000055d ), + .O(\blk00000003/blk00000004/sig00000454 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000004/blk0000121d ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00001ab5 ), + .I2(\blk00000003/blk00000004/sig00000559 ), + .I3(\blk00000003/blk00000004/sig0000055f ), + .O(\blk00000003/blk00000004/sig00000456 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000004/blk0000121c ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00001ab3 ), + .I2(\blk00000003/blk00000004/sig00000549 ), + .I3(\blk00000003/blk00000004/sig0000054f ), + .O(\blk00000003/blk00000004/sig0000044c ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000004/blk0000121b ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00001ab3 ), + .I2(\blk00000003/blk00000004/sig0000054b ), + .I3(\blk00000003/blk00000004/sig00000551 ), + .O(\blk00000003/blk00000004/sig0000044e ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000004/blk0000121a ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00001ab3 ), + .I2(\blk00000003/blk00000004/sig0000054d ), + .I3(\blk00000003/blk00000004/sig00000553 ), + .O(\blk00000003/blk00000004/sig00000450 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000004/blk00001219 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00001ab1 ), + .I2(\blk00000003/blk00000004/sig0000053d ), + .I3(\blk00000003/blk00000004/sig00000543 ), + .O(\blk00000003/blk00000004/sig00000446 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000004/blk00001218 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00001ab1 ), + .I2(\blk00000003/blk00000004/sig0000053f ), + .I3(\blk00000003/blk00000004/sig00000545 ), + .O(\blk00000003/blk00000004/sig00000448 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000004/blk00001217 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00001ab1 ), + .I2(\blk00000003/blk00000004/sig00000541 ), + .I3(\blk00000003/blk00000004/sig00000547 ), + .O(\blk00000003/blk00000004/sig0000044a ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000004/blk00001216 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00001aaf ), + .I2(\blk00000003/blk00000004/sig00000531 ), + .I3(\blk00000003/blk00000004/sig00000537 ), + .O(\blk00000003/blk00000004/sig00000440 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000004/blk00001215 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00001aaf ), + .I2(\blk00000003/blk00000004/sig00000533 ), + .I3(\blk00000003/blk00000004/sig00000539 ), + .O(\blk00000003/blk00000004/sig00000442 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000004/blk00001214 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00001aaf ), + .I2(\blk00000003/blk00000004/sig00000535 ), + .I3(\blk00000003/blk00000004/sig0000053b ), + .O(\blk00000003/blk00000004/sig00000444 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000004/blk00001213 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00001aad ), + .I2(\blk00000003/blk00000004/sig00000525 ), + .I3(\blk00000003/blk00000004/sig0000052b ), + .O(\blk00000003/blk00000004/sig0000043a ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000004/blk00001212 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00001aad ), + .I2(\blk00000003/blk00000004/sig00000527 ), + .I3(\blk00000003/blk00000004/sig0000052d ), + .O(\blk00000003/blk00000004/sig0000043c ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000004/blk00001211 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00001aad ), + .I2(\blk00000003/blk00000004/sig00000529 ), + .I3(\blk00000003/blk00000004/sig0000052f ), + .O(\blk00000003/blk00000004/sig0000043e ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000004/blk00001210 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00001aab ), + .I2(\blk00000003/blk00000004/sig00000519 ), + .I3(\blk00000003/blk00000004/sig0000051f ), + .O(\blk00000003/blk00000004/sig00000434 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000004/blk0000120f ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00001aab ), + .I2(\blk00000003/blk00000004/sig0000051b ), + .I3(\blk00000003/blk00000004/sig00000521 ), + .O(\blk00000003/blk00000004/sig00000436 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000004/blk0000120e ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00001aab ), + .I2(\blk00000003/blk00000004/sig0000051d ), + .I3(\blk00000003/blk00000004/sig00000523 ), + .O(\blk00000003/blk00000004/sig00000438 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000004/blk0000120d ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00001aa9 ), + .I2(\blk00000003/blk00000004/sig0000050d ), + .I3(\blk00000003/blk00000004/sig00000513 ), + .O(\blk00000003/blk00000004/sig0000042e ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000004/blk0000120c ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00001aa9 ), + .I2(\blk00000003/blk00000004/sig0000050f ), + .I3(\blk00000003/blk00000004/sig00000515 ), + .O(\blk00000003/blk00000004/sig00000430 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000004/blk0000120b ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00001aa9 ), + .I2(\blk00000003/blk00000004/sig00000511 ), + .I3(\blk00000003/blk00000004/sig00000517 ), + .O(\blk00000003/blk00000004/sig00000432 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000004/blk0000120a ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00001aa7 ), + .I2(\blk00000003/blk00000004/sig00000501 ), + .I3(\blk00000003/blk00000004/sig00000507 ), + .O(\blk00000003/blk00000004/sig00000428 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000004/blk00001209 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00001aa7 ), + .I2(\blk00000003/blk00000004/sig00000503 ), + .I3(\blk00000003/blk00000004/sig00000509 ), + .O(\blk00000003/blk00000004/sig0000042a ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000004/blk00001208 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00001aa7 ), + .I2(\blk00000003/blk00000004/sig00000505 ), + .I3(\blk00000003/blk00000004/sig0000050b ), + .O(\blk00000003/blk00000004/sig0000042c ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000004/blk00001207 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00001aa5 ), + .I2(\blk00000003/blk00000004/sig000004f5 ), + .I3(\blk00000003/blk00000004/sig000004fb ), + .O(\blk00000003/blk00000004/sig00000422 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000004/blk00001206 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00001aa5 ), + .I2(\blk00000003/blk00000004/sig000004f7 ), + .I3(\blk00000003/blk00000004/sig000004fd ), + .O(\blk00000003/blk00000004/sig00000424 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000004/blk00001205 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00001aa5 ), + .I2(\blk00000003/blk00000004/sig000004f9 ), + .I3(\blk00000003/blk00000004/sig000004ff ), + .O(\blk00000003/blk00000004/sig00000426 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000004/blk00001204 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00001aa3 ), + .I2(\blk00000003/blk00000004/sig000004e9 ), + .I3(\blk00000003/blk00000004/sig000004ef ), + .O(\blk00000003/blk00000004/sig0000041c ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000004/blk00001203 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00001aa3 ), + .I2(\blk00000003/blk00000004/sig000004eb ), + .I3(\blk00000003/blk00000004/sig000004f1 ), + .O(\blk00000003/blk00000004/sig0000041e ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000004/blk00001202 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00001aa3 ), + .I2(\blk00000003/blk00000004/sig000004ed ), + .I3(\blk00000003/blk00000004/sig000004f3 ), + .O(\blk00000003/blk00000004/sig00000420 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000004/blk00001201 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00001aa1 ), + .I2(\blk00000003/blk00000004/sig0000062d ), + .I3(\blk00000003/blk00000004/sig00000633 ), + .O(\blk00000003/blk00000004/sig000004be ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000004/blk00001200 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00001aa1 ), + .I2(\blk00000003/blk00000004/sig0000062f ), + .I3(\blk00000003/blk00000004/sig00000635 ), + .O(\blk00000003/blk00000004/sig000004c0 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000004/blk000011ff ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00001aa1 ), + .I2(\blk00000003/blk00000004/sig00000631 ), + .I3(\blk00000003/blk00000004/sig00000637 ), + .O(\blk00000003/blk00000004/sig000004c2 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000004/blk000011fe ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00001a9f ), + .I2(\blk00000003/blk00000004/sig000004dd ), + .I3(\blk00000003/blk00000004/sig000004e3 ), + .O(\blk00000003/blk00000004/sig00000416 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000004/blk000011fd ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00001a9f ), + .I2(\blk00000003/blk00000004/sig000004df ), + .I3(\blk00000003/blk00000004/sig000004e5 ), + .O(\blk00000003/blk00000004/sig00000418 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000004/blk000011fc ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00001a9f ), + .I2(\blk00000003/blk00000004/sig000004e1 ), + .I3(\blk00000003/blk00000004/sig000004e7 ), + .O(\blk00000003/blk00000004/sig0000041a ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000004/blk000011fb ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00001a9d ), + .I2(\blk00000003/blk00000004/sig000004d1 ), + .I3(\blk00000003/blk00000004/sig000004d7 ), + .O(\blk00000003/blk00000004/sig00000410 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000004/blk000011fa ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00001a9d ), + .I2(\blk00000003/blk00000004/sig000004d3 ), + .I3(\blk00000003/blk00000004/sig000004d9 ), + .O(\blk00000003/blk00000004/sig00000412 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000004/blk000011f9 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00001a9d ), + .I2(\blk00000003/blk00000004/sig000004d5 ), + .I3(\blk00000003/blk00000004/sig000004db ), + .O(\blk00000003/blk00000004/sig00000414 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000004/blk000011f8 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00001a9b ), + .I2(\blk00000003/blk00000004/sig00000621 ), + .I3(\blk00000003/blk00000004/sig00000627 ), + .O(\blk00000003/blk00000004/sig000004b8 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000004/blk000011f7 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00001a9b ), + .I2(\blk00000003/blk00000004/sig00000623 ), + .I3(\blk00000003/blk00000004/sig00000629 ), + .O(\blk00000003/blk00000004/sig000004ba ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000004/blk000011f6 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00001a9b ), + .I2(\blk00000003/blk00000004/sig00000625 ), + .I3(\blk00000003/blk00000004/sig0000062b ), + .O(\blk00000003/blk00000004/sig000004bc ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000004/blk000011f5 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00001a99 ), + .I2(\blk00000003/blk00000004/sig00000615 ), + .I3(\blk00000003/blk00000004/sig0000061b ), + .O(\blk00000003/blk00000004/sig000004b2 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000004/blk000011f4 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00001a99 ), + .I2(\blk00000003/blk00000004/sig00000617 ), + .I3(\blk00000003/blk00000004/sig0000061d ), + .O(\blk00000003/blk00000004/sig000004b4 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000004/blk000011f3 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00001a99 ), + .I2(\blk00000003/blk00000004/sig00000619 ), + .I3(\blk00000003/blk00000004/sig0000061f ), + .O(\blk00000003/blk00000004/sig000004b6 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000004/blk000011f2 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00001a97 ), + .I2(\blk00000003/blk00000004/sig00000609 ), + .I3(\blk00000003/blk00000004/sig0000060f ), + .O(\blk00000003/blk00000004/sig000004ac ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000004/blk000011f1 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00001a97 ), + .I2(\blk00000003/blk00000004/sig0000060b ), + .I3(\blk00000003/blk00000004/sig00000611 ), + .O(\blk00000003/blk00000004/sig000004ae ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000004/blk000011f0 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00001a97 ), + .I2(\blk00000003/blk00000004/sig0000060d ), + .I3(\blk00000003/blk00000004/sig00000613 ), + .O(\blk00000003/blk00000004/sig000004b0 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000004/blk000011ef ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00001a95 ), + .I2(\blk00000003/blk00000004/sig000005fd ), + .I3(\blk00000003/blk00000004/sig00000603 ), + .O(\blk00000003/blk00000004/sig000004a6 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000004/blk000011ee ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00001a95 ), + .I2(\blk00000003/blk00000004/sig000005ff ), + .I3(\blk00000003/blk00000004/sig00000605 ), + .O(\blk00000003/blk00000004/sig000004a8 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000004/blk000011ed ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00001a95 ), + .I2(\blk00000003/blk00000004/sig00000601 ), + .I3(\blk00000003/blk00000004/sig00000607 ), + .O(\blk00000003/blk00000004/sig000004aa ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000004/blk000011ec ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00001a93 ), + .I2(\blk00000003/blk00000004/sig000005f1 ), + .I3(\blk00000003/blk00000004/sig000005f7 ), + .O(\blk00000003/blk00000004/sig000004a0 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000004/blk000011eb ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00001a93 ), + .I2(\blk00000003/blk00000004/sig000005f3 ), + .I3(\blk00000003/blk00000004/sig000005f9 ), + .O(\blk00000003/blk00000004/sig000004a2 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000004/blk000011ea ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00001a93 ), + .I2(\blk00000003/blk00000004/sig000005f5 ), + .I3(\blk00000003/blk00000004/sig000005fb ), + .O(\blk00000003/blk00000004/sig000004a4 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000004/blk000011e9 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00001a91 ), + .I2(\blk00000003/blk00000004/sig000005e5 ), + .I3(\blk00000003/blk00000004/sig000005eb ), + .O(\blk00000003/blk00000004/sig0000049a ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000004/blk000011e8 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00001a91 ), + .I2(\blk00000003/blk00000004/sig000005e7 ), + .I3(\blk00000003/blk00000004/sig000005ed ), + .O(\blk00000003/blk00000004/sig0000049c ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000004/blk000011e7 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00001a91 ), + .I2(\blk00000003/blk00000004/sig000005e9 ), + .I3(\blk00000003/blk00000004/sig000005ef ), + .O(\blk00000003/blk00000004/sig0000049e ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000004/blk000011e6 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00001a8f ), + .I2(\blk00000003/blk00000004/sig000005d9 ), + .I3(\blk00000003/blk00000004/sig000005df ), + .O(\blk00000003/blk00000004/sig00000494 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000004/blk000011e5 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00001a8f ), + .I2(\blk00000003/blk00000004/sig000005db ), + .I3(\blk00000003/blk00000004/sig000005e1 ), + .O(\blk00000003/blk00000004/sig00000496 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000004/blk000011e4 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00001a8f ), + .I2(\blk00000003/blk00000004/sig000005dd ), + .I3(\blk00000003/blk00000004/sig000005e3 ), + .O(\blk00000003/blk00000004/sig00000498 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000004/blk000011e3 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00001a8d ), + .I2(\blk00000003/blk00000004/sig0000073d ), + .I3(\blk00000003/blk00000004/sig0000073f ), + .O(\blk00000003/blk00000004/sig000006fc ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000004/blk000011e2 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00001a8d ), + .I2(\blk00000003/blk00000004/sig000004c5 ), + .I3(\blk00000003/blk00000004/sig000004cb ), + .O(\blk00000003/blk00000004/sig0000040a ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000004/blk000011e1 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00001a8d ), + .I2(\blk00000003/blk00000004/sig000004c7 ), + .I3(\blk00000003/blk00000004/sig000004cd ), + .O(\blk00000003/blk00000004/sig0000040c ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000004/blk000011e0 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00001a8d ), + .I2(\blk00000003/blk00000004/sig000004c9 ), + .I3(\blk00000003/blk00000004/sig000004cf ), + .O(\blk00000003/blk00000004/sig0000040e ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000004/blk000011df ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00001a8b ), + .I2(\blk00000003/blk00000004/sig00000715 ), + .I3(\blk00000003/blk00000004/sig00000717 ), + .O(\blk00000003/blk00000004/sig000006d4 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000004/blk000011de ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00001a8b ), + .I2(\blk00000003/blk00000004/sig0000044d ), + .I3(\blk00000003/blk00000004/sig00000453 ), + .O(\blk00000003/blk00000004/sig000003ce ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000004/blk000011dd ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00001a8b ), + .I2(\blk00000003/blk00000004/sig0000044f ), + .I3(\blk00000003/blk00000004/sig00000455 ), + .O(\blk00000003/blk00000004/sig000003d0 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000004/blk000011dc ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00001a8b ), + .I2(\blk00000003/blk00000004/sig00000451 ), + .I3(\blk00000003/blk00000004/sig00000457 ), + .O(\blk00000003/blk00000004/sig000003d2 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000004/blk000011db ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00001a89 ), + .I2(\blk00000003/blk00000004/sig00000711 ), + .I3(\blk00000003/blk00000004/sig00000713 ), + .O(\blk00000003/blk00000004/sig000006d0 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000004/blk000011da ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00001a89 ), + .I2(\blk00000003/blk00000004/sig00000441 ), + .I3(\blk00000003/blk00000004/sig00000447 ), + .O(\blk00000003/blk00000004/sig000003c8 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000004/blk000011d9 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00001a89 ), + .I2(\blk00000003/blk00000004/sig00000443 ), + .I3(\blk00000003/blk00000004/sig00000449 ), + .O(\blk00000003/blk00000004/sig000003ca ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000004/blk000011d8 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00001a89 ), + .I2(\blk00000003/blk00000004/sig00000445 ), + .I3(\blk00000003/blk00000004/sig0000044b ), + .O(\blk00000003/blk00000004/sig000003cc ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000004/blk000011d7 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00001a87 ), + .I2(\blk00000003/blk00000004/sig0000070d ), + .I3(\blk00000003/blk00000004/sig0000070f ), + .O(\blk00000003/blk00000004/sig000006cc ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000004/blk000011d6 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00001a87 ), + .I2(\blk00000003/blk00000004/sig00000435 ), + .I3(\blk00000003/blk00000004/sig0000043b ), + .O(\blk00000003/blk00000004/sig000003c2 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000004/blk000011d5 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00001a87 ), + .I2(\blk00000003/blk00000004/sig00000437 ), + .I3(\blk00000003/blk00000004/sig0000043d ), + .O(\blk00000003/blk00000004/sig000003c4 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000004/blk000011d4 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00001a87 ), + .I2(\blk00000003/blk00000004/sig00000439 ), + .I3(\blk00000003/blk00000004/sig0000043f ), + .O(\blk00000003/blk00000004/sig000003c6 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000004/blk000011d3 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00001a85 ), + .I2(\blk00000003/blk00000004/sig00000709 ), + .I3(\blk00000003/blk00000004/sig0000070b ), + .O(\blk00000003/blk00000004/sig000006c8 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000004/blk000011d2 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00001a85 ), + .I2(\blk00000003/blk00000004/sig00000429 ), + .I3(\blk00000003/blk00000004/sig0000042f ), + .O(\blk00000003/blk00000004/sig000003bc ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000004/blk000011d1 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00001a85 ), + .I2(\blk00000003/blk00000004/sig0000042b ), + .I3(\blk00000003/blk00000004/sig00000431 ), + .O(\blk00000003/blk00000004/sig000003be ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000004/blk000011d0 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00001a85 ), + .I2(\blk00000003/blk00000004/sig0000042d ), + .I3(\blk00000003/blk00000004/sig00000433 ), + .O(\blk00000003/blk00000004/sig000003c0 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000004/blk000011cf ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00001a83 ), + .I2(\blk00000003/blk00000004/sig00000705 ), + .I3(\blk00000003/blk00000004/sig00000707 ), + .O(\blk00000003/blk00000004/sig000006c4 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000004/blk000011ce ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00001a83 ), + .I2(\blk00000003/blk00000004/sig0000041d ), + .I3(\blk00000003/blk00000004/sig00000423 ), + .O(\blk00000003/blk00000004/sig000003b6 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000004/blk000011cd ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00001a83 ), + .I2(\blk00000003/blk00000004/sig0000041f ), + .I3(\blk00000003/blk00000004/sig00000425 ), + .O(\blk00000003/blk00000004/sig000003b8 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000004/blk000011cc ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00001a83 ), + .I2(\blk00000003/blk00000004/sig00000421 ), + .I3(\blk00000003/blk00000004/sig00000427 ), + .O(\blk00000003/blk00000004/sig000003ba ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000004/blk000011cb ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00001a81 ), + .I2(\blk00000003/blk00000004/sig00000701 ), + .I3(\blk00000003/blk00000004/sig00000703 ), + .O(\blk00000003/blk00000004/sig000006c0 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000004/blk000011ca ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00001a81 ), + .I2(\blk00000003/blk00000004/sig00000411 ), + .I3(\blk00000003/blk00000004/sig00000417 ), + .O(\blk00000003/blk00000004/sig000003b0 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000004/blk000011c9 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00001a81 ), + .I2(\blk00000003/blk00000004/sig00000413 ), + .I3(\blk00000003/blk00000004/sig00000419 ), + .O(\blk00000003/blk00000004/sig000003b2 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000004/blk000011c8 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00001a81 ), + .I2(\blk00000003/blk00000004/sig00000415 ), + .I3(\blk00000003/blk00000004/sig0000041b ), + .O(\blk00000003/blk00000004/sig000003b4 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000004/blk000011c7 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00001a7f ), + .I2(\blk00000003/blk00000004/sig00000739 ), + .I3(\blk00000003/blk00000004/sig0000073b ), + .O(\blk00000003/blk00000004/sig000006f8 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000004/blk000011c6 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00001a7f ), + .I2(\blk00000003/blk00000004/sig000004b9 ), + .I3(\blk00000003/blk00000004/sig000004bf ), + .O(\blk00000003/blk00000004/sig00000404 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000004/blk000011c5 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00001a7f ), + .I2(\blk00000003/blk00000004/sig000004bb ), + .I3(\blk00000003/blk00000004/sig000004c1 ), + .O(\blk00000003/blk00000004/sig00000406 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000004/blk000011c4 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00001a7f ), + .I2(\blk00000003/blk00000004/sig000004bd ), + .I3(\blk00000003/blk00000004/sig000004c3 ), + .O(\blk00000003/blk00000004/sig00000408 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000004/blk000011c3 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00001a7d ), + .I2(\blk00000003/blk00000004/sig00000735 ), + .I3(\blk00000003/blk00000004/sig00000737 ), + .O(\blk00000003/blk00000004/sig000006f4 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000004/blk000011c2 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00001a7d ), + .I2(\blk00000003/blk00000004/sig000004ad ), + .I3(\blk00000003/blk00000004/sig000004b3 ), + .O(\blk00000003/blk00000004/sig000003fe ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000004/blk000011c1 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00001a7d ), + .I2(\blk00000003/blk00000004/sig000004af ), + .I3(\blk00000003/blk00000004/sig000004b5 ), + .O(\blk00000003/blk00000004/sig00000400 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000004/blk000011c0 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00001a7d ), + .I2(\blk00000003/blk00000004/sig000004b1 ), + .I3(\blk00000003/blk00000004/sig000004b7 ), + .O(\blk00000003/blk00000004/sig00000402 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000004/blk000011bf ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00001a7b ), + .I2(\blk00000003/blk00000004/sig00000731 ), + .I3(\blk00000003/blk00000004/sig00000733 ), + .O(\blk00000003/blk00000004/sig000006f0 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000004/blk000011be ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00001a7b ), + .I2(\blk00000003/blk00000004/sig000004a1 ), + .I3(\blk00000003/blk00000004/sig000004a7 ), + .O(\blk00000003/blk00000004/sig000003f8 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000004/blk000011bd ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00001a7b ), + .I2(\blk00000003/blk00000004/sig000004a3 ), + .I3(\blk00000003/blk00000004/sig000004a9 ), + .O(\blk00000003/blk00000004/sig000003fa ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000004/blk000011bc ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00001a7b ), + .I2(\blk00000003/blk00000004/sig000004a5 ), + .I3(\blk00000003/blk00000004/sig000004ab ), + .O(\blk00000003/blk00000004/sig000003fc ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000004/blk000011bb ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00001a79 ), + .I2(\blk00000003/blk00000004/sig0000072d ), + .I3(\blk00000003/blk00000004/sig0000072f ), + .O(\blk00000003/blk00000004/sig000006ec ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000004/blk000011ba ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00001a79 ), + .I2(\blk00000003/blk00000004/sig00000495 ), + .I3(\blk00000003/blk00000004/sig0000049b ), + .O(\blk00000003/blk00000004/sig000003f2 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000004/blk000011b9 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00001a79 ), + .I2(\blk00000003/blk00000004/sig00000497 ), + .I3(\blk00000003/blk00000004/sig0000049d ), + .O(\blk00000003/blk00000004/sig000003f4 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000004/blk000011b8 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00001a79 ), + .I2(\blk00000003/blk00000004/sig00000499 ), + .I3(\blk00000003/blk00000004/sig0000049f ), + .O(\blk00000003/blk00000004/sig000003f6 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000004/blk000011b7 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00001a77 ), + .I2(\blk00000003/blk00000004/sig00000729 ), + .I3(\blk00000003/blk00000004/sig0000072b ), + .O(\blk00000003/blk00000004/sig000006e8 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000004/blk000011b6 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00001a77 ), + .I2(\blk00000003/blk00000004/sig00000489 ), + .I3(\blk00000003/blk00000004/sig0000048f ), + .O(\blk00000003/blk00000004/sig000003ec ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000004/blk000011b5 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00001a77 ), + .I2(\blk00000003/blk00000004/sig0000048b ), + .I3(\blk00000003/blk00000004/sig00000491 ), + .O(\blk00000003/blk00000004/sig000003ee ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000004/blk000011b4 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00001a77 ), + .I2(\blk00000003/blk00000004/sig0000048d ), + .I3(\blk00000003/blk00000004/sig00000493 ), + .O(\blk00000003/blk00000004/sig000003f0 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000004/blk000011b3 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00001a75 ), + .I2(\blk00000003/blk00000004/sig00000725 ), + .I3(\blk00000003/blk00000004/sig00000727 ), + .O(\blk00000003/blk00000004/sig000006e4 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000004/blk000011b2 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00001a75 ), + .I2(\blk00000003/blk00000004/sig0000047d ), + .I3(\blk00000003/blk00000004/sig00000483 ), + .O(\blk00000003/blk00000004/sig000003e6 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000004/blk000011b1 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00001a75 ), + .I2(\blk00000003/blk00000004/sig0000047f ), + .I3(\blk00000003/blk00000004/sig00000485 ), + .O(\blk00000003/blk00000004/sig000003e8 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000004/blk000011b0 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00001a75 ), + .I2(\blk00000003/blk00000004/sig00000481 ), + .I3(\blk00000003/blk00000004/sig00000487 ), + .O(\blk00000003/blk00000004/sig000003ea ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000004/blk000011af ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00001a73 ), + .I2(\blk00000003/blk00000004/sig00000721 ), + .I3(\blk00000003/blk00000004/sig00000723 ), + .O(\blk00000003/blk00000004/sig000006e0 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000004/blk000011ae ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00001a73 ), + .I2(\blk00000003/blk00000004/sig00000471 ), + .I3(\blk00000003/blk00000004/sig00000477 ), + .O(\blk00000003/blk00000004/sig000003e0 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000004/blk000011ad ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00001a73 ), + .I2(\blk00000003/blk00000004/sig00000473 ), + .I3(\blk00000003/blk00000004/sig00000479 ), + .O(\blk00000003/blk00000004/sig000003e2 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000004/blk000011ac ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00001a73 ), + .I2(\blk00000003/blk00000004/sig00000475 ), + .I3(\blk00000003/blk00000004/sig0000047b ), + .O(\blk00000003/blk00000004/sig000003e4 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000004/blk000011ab ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00001a71 ), + .I2(\blk00000003/blk00000004/sig0000071d ), + .I3(\blk00000003/blk00000004/sig0000071f ), + .O(\blk00000003/blk00000004/sig000006dc ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000004/blk000011aa ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00001a71 ), + .I2(\blk00000003/blk00000004/sig00000465 ), + .I3(\blk00000003/blk00000004/sig0000046b ), + .O(\blk00000003/blk00000004/sig000003da ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000004/blk000011a9 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00001a71 ), + .I2(\blk00000003/blk00000004/sig00000467 ), + .I3(\blk00000003/blk00000004/sig0000046d ), + .O(\blk00000003/blk00000004/sig000003dc ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000004/blk000011a8 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00001a71 ), + .I2(\blk00000003/blk00000004/sig00000469 ), + .I3(\blk00000003/blk00000004/sig0000046f ), + .O(\blk00000003/blk00000004/sig000003de ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000004/blk000011a7 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00001a6f ), + .I2(\blk00000003/blk00000004/sig00000719 ), + .I3(\blk00000003/blk00000004/sig0000071b ), + .O(\blk00000003/blk00000004/sig000006d8 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000004/blk000011a6 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00001a6f ), + .I2(\blk00000003/blk00000004/sig00000459 ), + .I3(\blk00000003/blk00000004/sig0000045f ), + .O(\blk00000003/blk00000004/sig000003d4 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000004/blk000011a5 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00001a6f ), + .I2(\blk00000003/blk00000004/sig0000045b ), + .I3(\blk00000003/blk00000004/sig00000461 ), + .O(\blk00000003/blk00000004/sig000003d6 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000004/blk000011a4 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00001a6f ), + .I2(\blk00000003/blk00000004/sig0000045d ), + .I3(\blk00000003/blk00000004/sig00000463 ), + .O(\blk00000003/blk00000004/sig000003d8 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000004/blk000011a3 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00001a6d ), + .I2(\blk00000003/blk00000004/sig000006f9 ), + .I3(\blk00000003/blk00000004/sig000006fd ), + .O(\blk00000003/blk00000004/sig000006bc ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000004/blk000011a2 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00001a6d ), + .I2(\blk00000003/blk00000004/sig000006fb ), + .I3(\blk00000003/blk00000004/sig000006ff ), + .O(\blk00000003/blk00000004/sig000006ba ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000004/blk000011a1 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00001a6d ), + .I2(\blk00000003/blk00000004/sig00000405 ), + .I3(\blk00000003/blk00000004/sig0000040b ), + .O(\blk00000003/blk00000004/sig000003aa ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000004/blk000011a0 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00001a6d ), + .I2(\blk00000003/blk00000004/sig00000407 ), + .I3(\blk00000003/blk00000004/sig0000040d ), + .O(\blk00000003/blk00000004/sig000003ac ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000004/blk0000119f ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00001a6d ), + .I2(\blk00000003/blk00000004/sig00000409 ), + .I3(\blk00000003/blk00000004/sig0000040f ), + .O(\blk00000003/blk00000004/sig000003ae ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000004/blk0000119e ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00001a6b ), + .I2(\blk00000003/blk00000004/sig000006f1 ), + .I3(\blk00000003/blk00000004/sig000006f5 ), + .O(\blk00000003/blk00000004/sig000006b6 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000004/blk0000119d ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00001a6b ), + .I2(\blk00000003/blk00000004/sig000006f3 ), + .I3(\blk00000003/blk00000004/sig000006f7 ), + .O(\blk00000003/blk00000004/sig000006b4 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000004/blk0000119c ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00001a6b ), + .I2(\blk00000003/blk00000004/sig000003f9 ), + .I3(\blk00000003/blk00000004/sig000003ff ), + .O(\blk00000003/blk00000004/sig000003a4 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000004/blk0000119b ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00001a6b ), + .I2(\blk00000003/blk00000004/sig000003fb ), + .I3(\blk00000003/blk00000004/sig00000401 ), + .O(\blk00000003/blk00000004/sig000003a6 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000004/blk0000119a ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00001a6b ), + .I2(\blk00000003/blk00000004/sig000003fd ), + .I3(\blk00000003/blk00000004/sig00000403 ), + .O(\blk00000003/blk00000004/sig000003a8 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000004/blk00001199 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00001a69 ), + .I2(\blk00000003/blk00000004/sig000006e9 ), + .I3(\blk00000003/blk00000004/sig000006ed ), + .O(\blk00000003/blk00000004/sig000006b0 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000004/blk00001198 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00001a69 ), + .I2(\blk00000003/blk00000004/sig000006eb ), + .I3(\blk00000003/blk00000004/sig000006ef ), + .O(\blk00000003/blk00000004/sig000006ae ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000004/blk00001197 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00001a69 ), + .I2(\blk00000003/blk00000004/sig000003ed ), + .I3(\blk00000003/blk00000004/sig000003f3 ), + .O(\blk00000003/blk00000004/sig0000039e ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000004/blk00001196 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00001a69 ), + .I2(\blk00000003/blk00000004/sig000003ef ), + .I3(\blk00000003/blk00000004/sig000003f5 ), + .O(\blk00000003/blk00000004/sig000003a0 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000004/blk00001195 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00001a69 ), + .I2(\blk00000003/blk00000004/sig000003f1 ), + .I3(\blk00000003/blk00000004/sig000003f7 ), + .O(\blk00000003/blk00000004/sig000003a2 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000004/blk00001194 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00001a67 ), + .I2(\blk00000003/blk00000004/sig000006e1 ), + .I3(\blk00000003/blk00000004/sig000006e5 ), + .O(\blk00000003/blk00000004/sig000006aa ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000004/blk00001193 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00001a67 ), + .I2(\blk00000003/blk00000004/sig000006e3 ), + .I3(\blk00000003/blk00000004/sig000006e7 ), + .O(\blk00000003/blk00000004/sig000006a8 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000004/blk00001192 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00001a67 ), + .I2(\blk00000003/blk00000004/sig000003e1 ), + .I3(\blk00000003/blk00000004/sig000003e7 ), + .O(\blk00000003/blk00000004/sig00000398 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000004/blk00001191 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00001a67 ), + .I2(\blk00000003/blk00000004/sig000003e3 ), + .I3(\blk00000003/blk00000004/sig000003e9 ), + .O(\blk00000003/blk00000004/sig0000039a ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000004/blk00001190 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00001a67 ), + .I2(\blk00000003/blk00000004/sig000003e5 ), + .I3(\blk00000003/blk00000004/sig000003eb ), + .O(\blk00000003/blk00000004/sig0000039c ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000004/blk0000118f ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00001a65 ), + .I2(\blk00000003/blk00000004/sig000006d9 ), + .I3(\blk00000003/blk00000004/sig000006dd ), + .O(\blk00000003/blk00000004/sig000006a4 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000004/blk0000118e ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00001a65 ), + .I2(\blk00000003/blk00000004/sig000006db ), + .I3(\blk00000003/blk00000004/sig000006df ), + .O(\blk00000003/blk00000004/sig000006a2 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000004/blk0000118d ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00001a65 ), + .I2(\blk00000003/blk00000004/sig000003d5 ), + .I3(\blk00000003/blk00000004/sig000003db ), + .O(\blk00000003/blk00000004/sig00000392 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000004/blk0000118c ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00001a65 ), + .I2(\blk00000003/blk00000004/sig000003d7 ), + .I3(\blk00000003/blk00000004/sig000003dd ), + .O(\blk00000003/blk00000004/sig00000394 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000004/blk0000118b ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00001a65 ), + .I2(\blk00000003/blk00000004/sig000003d9 ), + .I3(\blk00000003/blk00000004/sig000003df ), + .O(\blk00000003/blk00000004/sig00000396 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000004/blk0000118a ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00001a63 ), + .I2(\blk00000003/blk00000004/sig000006d1 ), + .I3(\blk00000003/blk00000004/sig000006d5 ), + .O(\blk00000003/blk00000004/sig0000069e ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000004/blk00001189 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00001a63 ), + .I2(\blk00000003/blk00000004/sig000006d3 ), + .I3(\blk00000003/blk00000004/sig000006d7 ), + .O(\blk00000003/blk00000004/sig0000069c ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000004/blk00001188 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00001a63 ), + .I2(\blk00000003/blk00000004/sig000003c9 ), + .I3(\blk00000003/blk00000004/sig000003cf ), + .O(\blk00000003/blk00000004/sig0000038c ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000004/blk00001187 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00001a63 ), + .I2(\blk00000003/blk00000004/sig000003cb ), + .I3(\blk00000003/blk00000004/sig000003d1 ), + .O(\blk00000003/blk00000004/sig0000038e ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000004/blk00001186 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00001a63 ), + .I2(\blk00000003/blk00000004/sig000003cd ), + .I3(\blk00000003/blk00000004/sig000003d3 ), + .O(\blk00000003/blk00000004/sig00000390 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000004/blk00001185 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00001a61 ), + .I2(\blk00000003/blk00000004/sig000006c9 ), + .I3(\blk00000003/blk00000004/sig000006cd ), + .O(\blk00000003/blk00000004/sig00000698 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000004/blk00001184 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00001a61 ), + .I2(\blk00000003/blk00000004/sig000006cb ), + .I3(\blk00000003/blk00000004/sig000006cf ), + .O(\blk00000003/blk00000004/sig00000696 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000004/blk00001183 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00001a61 ), + .I2(\blk00000003/blk00000004/sig000003bd ), + .I3(\blk00000003/blk00000004/sig000003c3 ), + .O(\blk00000003/blk00000004/sig00000386 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000004/blk00001182 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00001a61 ), + .I2(\blk00000003/blk00000004/sig000003bf ), + .I3(\blk00000003/blk00000004/sig000003c5 ), + .O(\blk00000003/blk00000004/sig00000388 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000004/blk00001181 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00001a61 ), + .I2(\blk00000003/blk00000004/sig000003c1 ), + .I3(\blk00000003/blk00000004/sig000003c7 ), + .O(\blk00000003/blk00000004/sig0000038a ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000004/blk00001180 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00001a5f ), + .I2(\blk00000003/blk00000004/sig000006c1 ), + .I3(\blk00000003/blk00000004/sig000006c5 ), + .O(\blk00000003/blk00000004/sig00000692 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000004/blk0000117f ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00001a5f ), + .I2(\blk00000003/blk00000004/sig000006c3 ), + .I3(\blk00000003/blk00000004/sig000006c7 ), + .O(\blk00000003/blk00000004/sig00000690 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000004/blk0000117e ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00001a5f ), + .I2(\blk00000003/blk00000004/sig000003b1 ), + .I3(\blk00000003/blk00000004/sig000003b7 ), + .O(\blk00000003/blk00000004/sig00000380 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000004/blk0000117d ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00001a5f ), + .I2(\blk00000003/blk00000004/sig000003b3 ), + .I3(\blk00000003/blk00000004/sig000003b9 ), + .O(\blk00000003/blk00000004/sig00000382 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000004/blk0000117c ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00001a5f ), + .I2(\blk00000003/blk00000004/sig000003b5 ), + .I3(\blk00000003/blk00000004/sig000003bb ), + .O(\blk00000003/blk00000004/sig00000384 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000004/blk0000117b ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00001a5d ), + .I2(\blk00000003/blk00000004/sig000006b7 ), + .I3(\blk00000003/blk00000004/sig000006bd ), + .O(\blk00000003/blk00000004/sig0000068c ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000004/blk0000117a ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00001a5d ), + .I2(\blk00000003/blk00000004/sig000006b5 ), + .I3(\blk00000003/blk00000004/sig000006bb ), + .O(\blk00000003/blk00000004/sig0000068a ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000004/blk00001179 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00001a5d ), + .I2(\blk00000003/blk00000004/sig000006b9 ), + .I3(\blk00000003/blk00000004/sig000006bf ), + .O(\blk00000003/blk00000004/sig00000688 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000004/blk00001178 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00001a5d ), + .I2(\blk00000003/blk00000004/sig000003a5 ), + .I3(\blk00000003/blk00000004/sig000003ab ), + .O(\blk00000003/blk00000004/sig0000037a ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000004/blk00001177 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00001a5d ), + .I2(\blk00000003/blk00000004/sig000003a7 ), + .I3(\blk00000003/blk00000004/sig000003ad ), + .O(\blk00000003/blk00000004/sig0000037c ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000004/blk00001176 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00001a5d ), + .I2(\blk00000003/blk00000004/sig000003a9 ), + .I3(\blk00000003/blk00000004/sig000003af ), + .O(\blk00000003/blk00000004/sig0000037e ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000004/blk00001175 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00001a5b ), + .I2(\blk00000003/blk00000004/sig000006ab ), + .I3(\blk00000003/blk00000004/sig000006b1 ), + .O(\blk00000003/blk00000004/sig00000684 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000004/blk00001174 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00001a5b ), + .I2(\blk00000003/blk00000004/sig000006a9 ), + .I3(\blk00000003/blk00000004/sig000006af ), + .O(\blk00000003/blk00000004/sig00000682 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000004/blk00001173 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00001a5b ), + .I2(\blk00000003/blk00000004/sig000006ad ), + .I3(\blk00000003/blk00000004/sig000006b3 ), + .O(\blk00000003/blk00000004/sig00000680 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000004/blk00001172 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00001a5b ), + .I2(\blk00000003/blk00000004/sig00000399 ), + .I3(\blk00000003/blk00000004/sig0000039f ), + .O(\blk00000003/blk00000004/sig00000374 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000004/blk00001171 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00001a5b ), + .I2(\blk00000003/blk00000004/sig0000039b ), + .I3(\blk00000003/blk00000004/sig000003a1 ), + .O(\blk00000003/blk00000004/sig00000376 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000004/blk00001170 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00001a5b ), + .I2(\blk00000003/blk00000004/sig0000039d ), + .I3(\blk00000003/blk00000004/sig000003a3 ), + .O(\blk00000003/blk00000004/sig00000378 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000004/blk0000116f ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00001a59 ), + .I2(\blk00000003/blk00000004/sig0000069f ), + .I3(\blk00000003/blk00000004/sig000006a5 ), + .O(\blk00000003/blk00000004/sig0000067c ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000004/blk0000116e ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00001a59 ), + .I2(\blk00000003/blk00000004/sig0000069d ), + .I3(\blk00000003/blk00000004/sig000006a3 ), + .O(\blk00000003/blk00000004/sig0000067a ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000004/blk0000116d ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00001a59 ), + .I2(\blk00000003/blk00000004/sig000006a1 ), + .I3(\blk00000003/blk00000004/sig000006a7 ), + .O(\blk00000003/blk00000004/sig00000678 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000004/blk0000116c ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00001a59 ), + .I2(\blk00000003/blk00000004/sig0000038d ), + .I3(\blk00000003/blk00000004/sig00000393 ), + .O(\blk00000003/blk00000004/sig0000036e ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000004/blk0000116b ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00001a59 ), + .I2(\blk00000003/blk00000004/sig0000038f ), + .I3(\blk00000003/blk00000004/sig00000395 ), + .O(\blk00000003/blk00000004/sig00000370 ) + ); + LUT4 #( + .INIT ( 16'h5140 )) + \blk00000003/blk00000004/blk0000116a ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00001a59 ), + .I2(\blk00000003/blk00000004/sig00000391 ), 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LUT3 #( + .INIT ( 8'h69 )) + \blk00000003/blk00000004/blk0000111e ( + .I0(\blk00000003/blk00000004/sig000003ed ), + .I1(\blk00000003/blk00000004/sig000003f3 ), + .I2(\blk00000003/blk00000004/sig00001a68 ), + .O(\blk00000003/blk00000004/sig00001a69 ) + ); + LUT3 #( + .INIT ( 8'h69 )) + \blk00000003/blk00000004/blk0000111d ( + .I0(\blk00000003/blk00000004/sig000003e1 ), + .I1(\blk00000003/blk00000004/sig000003e7 ), + .I2(\blk00000003/blk00000004/sig00001a66 ), + .O(\blk00000003/blk00000004/sig00001a67 ) + ); + LUT3 #( + .INIT ( 8'h69 )) + \blk00000003/blk00000004/blk0000111c ( + .I0(\blk00000003/blk00000004/sig000003d5 ), + .I1(\blk00000003/blk00000004/sig000003db ), + .I2(\blk00000003/blk00000004/sig00001a64 ), + .O(\blk00000003/blk00000004/sig00001a65 ) + ); + LUT3 #( + .INIT ( 8'h69 )) + \blk00000003/blk00000004/blk0000111b ( + .I0(\blk00000003/blk00000004/sig000003c9 ), + .I1(\blk00000003/blk00000004/sig000003cf ), + .I2(\blk00000003/blk00000004/sig00001a62 ), + .O(\blk00000003/blk00000004/sig00001a63 ) + ); + LUT3 #( + .INIT ( 8'h69 )) + \blk00000003/blk00000004/blk0000111a ( + .I0(\blk00000003/blk00000004/sig000003bd ), + .I1(\blk00000003/blk00000004/sig000003c3 ), + .I2(\blk00000003/blk00000004/sig00001a60 ), + .O(\blk00000003/blk00000004/sig00001a61 ) + ); + LUT3 #( + .INIT ( 8'h69 )) + \blk00000003/blk00000004/blk00001119 ( + .I0(\blk00000003/blk00000004/sig000003b1 ), + .I1(\blk00000003/blk00000004/sig000003b7 ), + .I2(\blk00000003/blk00000004/sig00001a5e ), + .O(\blk00000003/blk00000004/sig00001a5f ) + ); + LUT3 #( + .INIT ( 8'h69 )) + \blk00000003/blk00000004/blk00001118 ( + .I0(\blk00000003/blk00000004/sig000003a5 ), + .I1(\blk00000003/blk00000004/sig000003ab ), + .I2(\blk00000003/blk00000004/sig00001a5c ), + .O(\blk00000003/blk00000004/sig00001a5d ) + ); + LUT3 #( + .INIT ( 8'h69 )) + \blk00000003/blk00000004/blk00001117 ( + .I0(\blk00000003/blk00000004/sig00000399 ), + .I1(\blk00000003/blk00000004/sig0000039f ), + .I2(\blk00000003/blk00000004/sig00001a5a ), + .O(\blk00000003/blk00000004/sig00001a5b ) + ); + LUT3 #( + .INIT ( 8'h69 )) + \blk00000003/blk00000004/blk00001116 ( + .I0(\blk00000003/blk00000004/sig0000038d ), + .I1(\blk00000003/blk00000004/sig00000393 ), + .I2(\blk00000003/blk00000004/sig00001a58 ), + .O(\blk00000003/blk00000004/sig00001a59 ) + ); + LUT3 #( + .INIT ( 8'h69 )) + \blk00000003/blk00000004/blk00001115 ( + .I0(\blk00000003/blk00000004/sig00000381 ), + .I1(\blk00000003/blk00000004/sig00000387 ), + .I2(\blk00000003/blk00000004/sig00001a56 ), + .O(\blk00000003/blk00000004/sig00001a57 ) + ); + LUT3 #( + .INIT ( 8'h69 )) + \blk00000003/blk00000004/blk00001114 ( + .I0(\blk00000003/blk00000004/sig00000375 ), + .I1(\blk00000003/blk00000004/sig0000037b ), + .I2(\blk00000003/blk00000004/sig00001a54 ), + .O(\blk00000003/blk00000004/sig00001a55 ) + ); + LUT3 #( + .INIT ( 8'h69 )) + \blk00000003/blk00000004/blk00001113 ( + .I0(\blk00000003/blk00000004/sig00000369 ), + .I1(\blk00000003/blk00000004/sig0000036f ), + .I2(\blk00000003/blk00000004/sig00001a52 ), + .O(\blk00000003/blk00000004/sig00001a53 ) + ); + LUT3 #( + .INIT ( 8'h69 )) + \blk00000003/blk00000004/blk00001112 ( + .I0(\blk00000003/blk00000004/sig0000035d ), + .I1(\blk00000003/blk00000004/sig00000363 ), + .I2(\blk00000003/blk00000004/sig00001a50 ), + .O(\blk00000003/blk00000004/sig00001a51 ) + ); + LUT2 #( + .INIT ( 4'h6 )) + \blk00000003/blk00000004/blk00001111 ( + .I0(\blk00000003/blk00000004/sig000002f8 ), + .I1(\blk00000003/blk00000004/sig000002f2 ), + .O(\blk00000003/blk00000004/sig0000035b ) + ); + LUT2 #( + .INIT ( 4'h6 )) + \blk00000003/blk00000004/blk00001110 ( + .I0(\blk00000003/blk00000004/sig000002fa ), + .I1(\blk00000003/blk00000004/sig000002f4 ), + .O(\blk00000003/blk00000004/sig0000035a ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk00000004/blk0000110f ( + .I0(\blk00000003/blk00000004/sig00000192 ), + .I1(ce), + .O(\blk00000003/blk00000004/sig000001c1 ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk00000004/blk0000110e ( + .I0(\blk00000003/blk00000004/sig00000194 ), + .I1(ce), + .O(\blk00000003/blk00000004/sig000001b1 ) + ); + LUT2 #( + .INIT ( 4'h6 )) + \blk00000003/blk00000004/blk0000110d ( + .I0(\blk00000003/blk00000004/sig000002fc ), + .I1(\blk00000003/blk00000004/sig000002f6 ), + .O(\blk00000003/blk00000004/sig00000357 ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \blk00000003/blk00000004/blk0000110c ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00001a4f ), + .O(\blk00000003/blk00000004/sig000000cb ) + ); + LUT4 #( + .INIT ( 16'h0002 )) + \blk00000003/blk00000004/blk0000110b ( + .I0(\blk00000003/blk00000004/sig000000ab ), + .I1(\blk00000003/blk00000004/sig000000ad ), + .I2(\blk00000003/blk00000004/sig000000af ), + .I3(\blk00000003/blk00000004/sig000000b1 ), + .O(\blk00000003/blk00000004/sig00001a4e ) + ); + LUT3 #( + .INIT ( 8'h04 )) + \blk00000003/blk00000004/blk0000110a ( + .I0(sclr), + .I1(ce), + .I2(\blk00000003/blk00000004/sig000000b7 ), + .O(\blk00000003/blk00000004/sig00001a4d ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \blk00000003/blk00000004/blk00001109 ( + .I0(ce), + .I1(\blk00000003/blk00000004/sig00001a44 ), + .O(\blk00000003/blk00000004/sig00001a4c ) + ); + LUT4 #( + .INIT ( 16'h0800 )) + \blk00000003/blk00000004/blk00001108 ( + .I0(\blk00000003/blk00000004/sig000002b7 ), + .I1(\blk00000003/blk00000004/sig000002bb ), + .I2(\blk00000003/blk00000004/sig000002b5 ), + .I3(\blk00000003/blk00000004/sig000002b9 ), + .O(\blk00000003/blk00000004/sig00001a4b ) + ); + LUT4 #( + .INIT ( 16'h0008 )) + \blk00000003/blk00000004/blk00001107 ( + .I0(\blk00000003/blk00000004/sig000002b3 ), + .I1(ce), + .I2(sclr), + .I3(\blk00000003/blk00000004/sig000002bd ), + .O(\blk00000003/blk00000004/sig00001a4a ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \blk00000003/blk00000004/blk00001106 ( + .I0(ce), + .I1(\blk00000003/blk00000004/sig00001a43 ), + .O(\blk00000003/blk00000004/sig00001a49 ) + ); + LUT4 #( + .INIT ( 16'hFEFF )) + \blk00000003/blk00000004/blk00001105 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig000002cd ), + .I2(\blk00000003/blk00000004/sig000002cb ), + .I3(\blk00000003/blk00000004/sig000002cf ), + .O(\blk00000003/blk00000004/sig00001a48 ) + ); + LUT4 #( + .INIT ( 16'hFBFF )) + \blk00000003/blk00000004/blk00001104 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig000002df ), + .I2(\blk00000003/blk00000004/sig000002dd ), + .I3(\blk00000003/blk00000004/sig000002db ), + .O(\blk00000003/blk00000004/sig00001a47 ) + ); + LUT3 #( + .INIT ( 8'hA8 )) + \blk00000003/blk00000004/blk00001103 ( + .I0(ce), + .I1(sclr), + .I2(\blk00000003/blk00000004/sig00001a44 ), + .O(\blk00000003/blk00000004/sig000000aa ) + ); + LUT3 #( + .INIT ( 8'hA8 )) + \blk00000003/blk00000004/blk00001102 ( + .I0(ce), + .I1(sclr), + .I2(\blk00000003/blk00000004/sig00001a46 ), + .O(\blk00000003/blk00000004/sig000002ea ) + ); + LUT3 #( + .INIT ( 8'hA8 )) + \blk00000003/blk00000004/blk00001101 ( + .I0(ce), + .I1(sclr), + .I2(\blk00000003/blk00000004/sig00001a45 ), + .O(\blk00000003/blk00000004/sig000002ca ) + ); + LUT3 #( + .INIT ( 8'hA8 )) + \blk00000003/blk00000004/blk00001100 ( + .I0(ce), + .I1(sclr), + .I2(\blk00000003/blk00000004/sig00001a42 ), + .O(\blk00000003/blk00000004/sig000002da ) + ); + LUT3 #( + .INIT ( 8'hA8 )) + \blk00000003/blk00000004/blk000010ff ( + .I0(ce), + .I1(sclr), + .I2(\blk00000003/blk00000004/sig00001a43 ), + .O(\blk00000003/blk00000004/sig000002b2 ) + ); + LUT4 #( + .INIT ( 16'h019D )) + \blk00000003/blk00000004/blk000010fe ( + .I0(\blk00000003/blk00000004/sig000002dd ), + .I1(\blk00000003/blk00000004/sig000002df ), + .I2(\blk00000003/blk00000004/sig000002e1 ), + .I3(\blk00000003/blk00000004/sig000002db ), + .O(\blk00000003/blk00000004/sig0000019d ) + ); + LUT4 #( + .INIT ( 16'h1001 )) + \blk00000003/blk00000004/blk000010fd ( + .I0(\blk00000003/blk00000004/sig000000a5 ), + .I1(sclr), + .I2(\blk00000003/blk00000004/sig000000a1 ), + .I3(\blk00000003/blk00000004/sig0000009d ), + .O(\blk00000003/blk00000004/sig000002f1 ) + ); + LUT4 #( + .INIT ( 16'h1001 )) + \blk00000003/blk00000004/blk000010fc ( + .I0(\blk00000003/blk00000004/sig000000a5 ), + .I1(sclr), + .I2(\blk00000003/blk00000004/sig0000009f ), + .I3(\blk00000003/blk00000004/sig0000009d ), + .O(\blk00000003/blk00000004/sig000002f3 ) + ); + LUT4 #( + .INIT ( 16'h1001 )) + \blk00000003/blk00000004/blk000010fb ( + .I0(\blk00000003/blk00000004/sig000000a3 ), + .I1(sclr), + .I2(\blk00000003/blk00000004/sig0000009b ), + .I3(\blk00000003/blk00000004/sig00000097 ), + .O(\blk00000003/blk00000004/sig000002f7 ) + ); + LUT4 #( + .INIT ( 16'h1001 )) + \blk00000003/blk00000004/blk000010fa ( + .I0(\blk00000003/blk00000004/sig000000a3 ), + .I1(sclr), + .I2(\blk00000003/blk00000004/sig00000099 ), + .I3(\blk00000003/blk00000004/sig00000097 ), + .O(\blk00000003/blk00000004/sig000002f9 ) + ); + LUT4 #( + .INIT ( 16'h3020 )) + \blk00000003/blk00000004/blk000010f9 ( + .I0(\blk00000003/blk00000004/sig000000a7 ), + .I1(sclr), + .I2(ce), + .I3(\blk00000003/blk00000004/sig00001a44 ), + .O(\blk00000003/blk00000004/sig000000a8 ) + ); + LUT4 #( + .INIT ( 16'h0800 )) + \blk00000003/blk00000004/blk000010f8 ( + .I0(\blk00000003/blk00000004/sig000019fe ), + .I1(\blk00000003/blk00000004/sig000019f7 ), + .I2(\blk00000003/blk00000004/sig00001a0d ), + .I3(\blk00000003/blk00000004/sig00001a11 ), + .O(\blk00000003/blk00000004/sig000019f4 ) + ); + LUT3 #( + .INIT ( 8'hC6 )) + \blk00000003/blk00000004/blk000010f7 ( + .I0(\blk00000003/blk00000004/sig00001a11 ), + .I1(\blk00000003/blk00000004/sig00001a0f ), + .I2(\blk00000003/blk00000004/sig000019fe ), + .O(\blk00000003/blk00000004/sig00001a10 ) + ); + LUT3 #( + .INIT ( 8'h14 )) + \blk00000003/blk00000004/blk000010f6 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig000000ca ), + .I2(\blk00000003/blk00000004/sig000000ce ), + .O(\blk00000003/blk00000004/sig000000c9 ) + ); + LUT3 #( + .INIT ( 8'h54 )) + \blk00000003/blk00000004/blk000010f5 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00001a44 ), + .I2(\blk00000003/blk00000004/sig000000a7 ), + .O(\blk00000003/blk00000004/sig000000a6 ) + ); + LUT3 #( + .INIT ( 8'h04 )) + \blk00000003/blk00000004/blk000010f4 ( + .I0(\blk00000003/blk00000004/sig000000a5 ), + .I1(\blk00000003/blk00000004/sig0000009d ), + .I2(sclr), + .O(\blk00000003/blk00000004/sig000002f5 ) + ); + LUT3 #( + .INIT ( 8'h04 )) + \blk00000003/blk00000004/blk000010f3 ( + .I0(\blk00000003/blk00000004/sig000000a3 ), + .I1(\blk00000003/blk00000004/sig00000097 ), + .I2(sclr), + .O(\blk00000003/blk00000004/sig000002fb ) + ); + LUT3 #( + .INIT ( 8'hF2 )) + \blk00000003/blk00000004/blk000010f2 ( + .I0(\blk00000003/blk00000004/sig000019fd ), + .I1(\blk00000003/blk00000004/sig00001a0d ), + .I2(\blk00000003/blk00000004/sig000019f3 ), + .O(\blk00000003/blk00000004/sig000019f2 ) + ); + LUT3 #( + .INIT ( 8'hF8 )) + \blk00000003/blk00000004/blk000010f1 ( + .I0(\blk00000003/blk00000004/sig00001a11 ), + .I1(\blk00000003/blk00000004/sig000019fe ), + .I2(\blk00000003/blk00000004/sig00001a0d ), + .O(\blk00000003/blk00000004/sig00001a0c ) + ); + LUT3 #( + .INIT ( 8'h08 )) + \blk00000003/blk00000004/blk000010f0 ( + .I0(\blk00000003/blk00000004/sig000001a2 ), + .I1(\blk00000003/blk00000004/sig000000ca ), + .I2(sclr), + .O(\blk00000003/blk00000004/sig0000018b ) + ); + LUT3 #( + .INIT ( 8'h04 )) + \blk00000003/blk00000004/blk000010ef ( + .I0(\blk00000003/blk00000004/sig000000ca ), + .I1(\blk00000003/blk00000004/sig000001a2 ), + .I2(sclr), + .O(\blk00000003/blk00000004/sig00000189 ) + ); + LUT3 #( + .INIT ( 8'h15 )) + \blk00000003/blk00000004/blk000010ee ( + .I0(\blk00000003/blk00000004/sig000002db ), + .I1(\blk00000003/blk00000004/sig000002df ), + .I2(\blk00000003/blk00000004/sig000002dd ), + .O(\blk00000003/blk00000004/sig0000019f ) + ); + LUT3 #( + .INIT ( 8'h01 )) + \blk00000003/blk00000004/blk000010ed ( + .I0(\blk00000003/blk00000004/sig00001a43 ), + .I1(\blk00000003/blk00000004/sig000002b0 ), + .I2(sclr), + .O(\blk00000003/blk00000004/sig000002af ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \blk00000003/blk00000004/blk000010ec ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig000019f1 ), + .O(\blk00000003/blk00000004/sig000019ee ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \blk00000003/blk00000004/blk000010eb ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig000019ab ), + .O(\blk00000003/blk00000004/sig000019a8 ) + ); + LUT2 #( + .INIT ( 4'h1 )) + \blk00000003/blk00000004/blk000010ea ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig000019ef ), + .O(\blk00000003/blk00000004/sig000019aa ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \blk00000003/blk00000004/blk000010e9 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig0000170d ), + .O(\blk00000003/blk00000004/sig0000170a ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \blk00000003/blk00000004/blk000010e8 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig000016c7 ), + .O(\blk00000003/blk00000004/sig000016c4 ) + ); + LUT2 #( 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), + .O(\blk00000003/blk00000004/sig00001630 ) + ); + LUT2 #( + .INIT ( 4'h1 )) + \blk00000003/blk00000004/blk000010e1 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00001677 ), + .O(\blk00000003/blk00000004/sig00001632 ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \blk00000003/blk00000004/blk000010e0 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig0000162f ), + .O(\blk00000003/blk00000004/sig0000162c ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \blk00000003/blk00000004/blk000010df ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig000015e9 ), + .O(\blk00000003/blk00000004/sig000015e6 ) + ); + LUT2 #( + .INIT ( 4'h1 )) + \blk00000003/blk00000004/blk000010de ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig0000162d ), + .O(\blk00000003/blk00000004/sig000015e8 ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \blk00000003/blk00000004/blk000010dd ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig000015e5 ), + .O(\blk00000003/blk00000004/sig000015e2 ) + ); + LUT2 #( + .INIT ( 4'h4 )) + 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.O(\blk00000003/blk00000004/sig0000154e ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \blk00000003/blk00000004/blk000010d6 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig0000150b ), + .O(\blk00000003/blk00000004/sig00001508 ) + ); + LUT2 #( + .INIT ( 4'h1 )) + \blk00000003/blk00000004/blk000010d5 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig0000154f ), + .O(\blk00000003/blk00000004/sig0000150a ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \blk00000003/blk00000004/blk000010d4 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00001507 ), + .O(\blk00000003/blk00000004/sig00001504 ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \blk00000003/blk00000004/blk000010d3 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig000014c1 ), + .O(\blk00000003/blk00000004/sig000014be ) + ); + LUT2 #( + .INIT ( 4'h1 )) + \blk00000003/blk00000004/blk000010d2 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00001505 ), + .O(\blk00000003/blk00000004/sig000014c0 ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \blk00000003/blk00000004/blk000010d1 ( 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#( + .INIT ( 4'h4 )) + \blk00000003/blk00000004/blk000010cb ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig000019a7 ), + .O(\blk00000003/blk00000004/sig000019a4 ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \blk00000003/blk00000004/blk000010ca ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00001961 ), + .O(\blk00000003/blk00000004/sig0000195e ) + ); + LUT2 #( + .INIT ( 4'h1 )) + \blk00000003/blk00000004/blk000010c9 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig000019a5 ), + .O(\blk00000003/blk00000004/sig00001960 ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \blk00000003/blk00000004/blk000010c8 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00001429 ), + .O(\blk00000003/blk00000004/sig00001426 ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \blk00000003/blk00000004/blk000010c7 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig000013e3 ), + .O(\blk00000003/blk00000004/sig000013e0 ) + ); + LUT2 #( + .INIT ( 4'h1 )) + \blk00000003/blk00000004/blk000010c6 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00001427 ), + .O(\blk00000003/blk00000004/sig000013e2 ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \blk00000003/blk00000004/blk000010c5 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig000013df ), + .O(\blk00000003/blk00000004/sig000013dc ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \blk00000003/blk00000004/blk000010c4 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00001399 ), + .O(\blk00000003/blk00000004/sig00001396 ) + ); + LUT2 #( + .INIT ( 4'h1 )) + \blk00000003/blk00000004/blk000010c3 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig000013dd ), + .O(\blk00000003/blk00000004/sig00001398 ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \blk00000003/blk00000004/blk000010c2 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00001395 ), + .O(\blk00000003/blk00000004/sig00001392 ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \blk00000003/blk00000004/blk000010c1 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig0000134f ), + .O(\blk00000003/blk00000004/sig0000134c ) + ); + LUT2 #( + .INIT ( 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#( + .INIT ( 4'h4 )) + \blk00000003/blk00000004/blk000010af ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00001193 ), + .O(\blk00000003/blk00000004/sig00001190 ) + ); + LUT2 #( + .INIT ( 4'h1 )) + \blk00000003/blk00000004/blk000010ae ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig000011d7 ), + .O(\blk00000003/blk00000004/sig00001192 ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \blk00000003/blk00000004/blk000010ad ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig0000118f ), + .O(\blk00000003/blk00000004/sig0000118c ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \blk00000003/blk00000004/blk000010ac ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00001149 ), + .O(\blk00000003/blk00000004/sig00001146 ) + ); + LUT2 #( + .INIT ( 4'h1 )) + \blk00000003/blk00000004/blk000010ab ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig0000118d ), + .O(\blk00000003/blk00000004/sig00001148 ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \blk00000003/blk00000004/blk000010aa ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig0000195d ), + .O(\blk00000003/blk00000004/sig0000195a ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \blk00000003/blk00000004/blk000010a9 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00001917 ), + .O(\blk00000003/blk00000004/sig00001914 ) + ); + LUT2 #( + .INIT ( 4'h1 )) + \blk00000003/blk00000004/blk000010a8 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig0000195b ), + .O(\blk00000003/blk00000004/sig00001916 ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \blk00000003/blk00000004/blk000010a7 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00001145 ), + .O(\blk00000003/blk00000004/sig00001142 ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \blk00000003/blk00000004/blk000010a6 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig000010ff ), + .O(\blk00000003/blk00000004/sig000010fc ) + ); + LUT2 #( + .INIT ( 4'h1 )) + \blk00000003/blk00000004/blk000010a5 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00001143 ), + .O(\blk00000003/blk00000004/sig000010fe ) + ); + LUT2 #( + .INIT ( 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#( + .INIT ( 4'h1 )) + \blk00000003/blk00000004/blk00001093 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00000f87 ), + .O(\blk00000003/blk00000004/sig00000f42 ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \blk00000003/blk00000004/blk00001092 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00000f3f ), + .O(\blk00000003/blk00000004/sig00000f3c ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \blk00000003/blk00000004/blk00001091 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00000ef9 ), + .O(\blk00000003/blk00000004/sig00000ef6 ) + ); + LUT2 #( + .INIT ( 4'h1 )) + \blk00000003/blk00000004/blk00001090 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00000f3d ), + .O(\blk00000003/blk00000004/sig00000ef8 ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \blk00000003/blk00000004/blk0000108f ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00000ef5 ), + .O(\blk00000003/blk00000004/sig00000ef2 ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \blk00000003/blk00000004/blk0000108e ( + .I0(sclr), + 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#( + .INIT ( 4'h4 )) + \blk00000003/blk00000004/blk00001077 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00000cef ), + .O(\blk00000003/blk00000004/sig00000cec ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \blk00000003/blk00000004/blk00001076 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00000ca9 ), + .O(\blk00000003/blk00000004/sig00000ca6 ) + ); + LUT2 #( + .INIT ( 4'h1 )) + \blk00000003/blk00000004/blk00001075 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00000ced ), + .O(\blk00000003/blk00000004/sig00000ca8 ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \blk00000003/blk00000004/blk00001074 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00000ca5 ), + .O(\blk00000003/blk00000004/sig00000ca2 ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \blk00000003/blk00000004/blk00001073 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00000c5f ), + .O(\blk00000003/blk00000004/sig00000c5c ) + ); + LUT2 #( + .INIT ( 4'h1 )) + \blk00000003/blk00000004/blk00001072 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00000ca3 ), + .O(\blk00000003/blk00000004/sig00000c5e ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \blk00000003/blk00000004/blk00001071 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00000c5b ), + .O(\blk00000003/blk00000004/sig00000c58 ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \blk00000003/blk00000004/blk00001070 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00000c15 ), + .O(\blk00000003/blk00000004/sig00000c12 ) + ); + LUT2 #( + .INIT ( 4'h1 )) + \blk00000003/blk00000004/blk0000106f ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00000c59 ), + .O(\blk00000003/blk00000004/sig00000c14 ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \blk00000003/blk00000004/blk0000106e ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00000c11 ), + .O(\blk00000003/blk00000004/sig00000c0e ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \blk00000003/blk00000004/blk0000106d ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00000bcb ), + .O(\blk00000003/blk00000004/sig00000bc8 ) + ); + LUT2 #( + .INIT ( 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#( + .INIT ( 4'h4 )) + \blk00000003/blk00000004/blk0000105b ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00000a59 ), + .O(\blk00000003/blk00000004/sig00000a56 ) + ); + LUT2 #( + .INIT ( 4'h1 )) + \blk00000003/blk00000004/blk0000105a ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00000a9d ), + .O(\blk00000003/blk00000004/sig00000a58 ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \blk00000003/blk00000004/blk00001059 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00000a55 ), + .O(\blk00000003/blk00000004/sig00000a52 ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \blk00000003/blk00000004/blk00001058 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00000a0f ), + .O(\blk00000003/blk00000004/sig00000a0c ) + ); + LUT2 #( + .INIT ( 4'h1 )) + \blk00000003/blk00000004/blk00001057 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00000a53 ), + .O(\blk00000003/blk00000004/sig00000a0e ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \blk00000003/blk00000004/blk00001056 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00000a0b ), + .O(\blk00000003/blk00000004/sig00000a08 ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \blk00000003/blk00000004/blk00001055 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig000009c5 ), + .O(\blk00000003/blk00000004/sig000009c2 ) + ); + LUT2 #( + .INIT ( 4'h1 )) + \blk00000003/blk00000004/blk00001054 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00000a09 ), + .O(\blk00000003/blk00000004/sig000009c4 ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \blk00000003/blk00000004/blk00001053 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig000009c1 ), + .O(\blk00000003/blk00000004/sig000009be ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \blk00000003/blk00000004/blk00001052 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig0000097b ), + .O(\blk00000003/blk00000004/sig00000978 ) + ); + LUT2 #( + .INIT ( 4'h1 )) + \blk00000003/blk00000004/blk00001051 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig000009bf ), + .O(\blk00000003/blk00000004/sig0000097a ) + ); + LUT2 #( + .INIT ( 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#( + .INIT ( 4'h1 )) + \blk00000003/blk00000004/blk0000103f ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00000849 ), + .O(\blk00000003/blk00000004/sig000007f0 ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \blk00000003/blk00000004/blk0000103e ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig000007ed ), + .O(\blk00000003/blk00000004/sig000007ea ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \blk00000003/blk00000004/blk0000103d ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig000007a3 ), + .O(\blk00000003/blk00000004/sig000007a0 ) + ); + LUT2 #( + .INIT ( 4'h1 )) + \blk00000003/blk00000004/blk0000103c ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig000007eb ), + .O(\blk00000003/blk00000004/sig000007a2 ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \blk00000003/blk00000004/blk0000103b ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig0000079f ), + .O(\blk00000003/blk00000004/sig0000079c ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \blk00000003/blk00000004/blk0000103a ( + .I0(sclr), + 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#( + .INIT ( 4'h4 )) + \blk00000003/blk00000004/blk00001023 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00000302 ), + .O(\blk00000003/blk00000004/sig00000784 ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \blk00000003/blk00000004/blk00001022 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00000304 ), + .O(\blk00000003/blk00000004/sig00000786 ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \blk00000003/blk00000004/blk00001021 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00000306 ), + .O(\blk00000003/blk00000004/sig00000788 ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \blk00000003/blk00000004/blk00001020 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00000308 ), + .O(\blk00000003/blk00000004/sig0000078a ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \blk00000003/blk00000004/blk0000101f ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00001757 ), + .O(\blk00000003/blk00000004/sig00001754 ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \blk00000003/blk00000004/blk0000101e ( + .I0(sclr), + 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.O(\blk00000003/blk00000004/sig00000317 ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \blk00000003/blk00000004/blk00001012 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00000333 ), + .O(\blk00000003/blk00000004/sig00000309 ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \blk00000003/blk00000004/blk00001011 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00000335 ), + .O(\blk00000003/blk00000004/sig0000030b ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \blk00000003/blk00000004/blk00001010 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00000337 ), + .O(\blk00000003/blk00000004/sig0000030d ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \blk00000003/blk00000004/blk0000100f ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00000339 ), + .O(\blk00000003/blk00000004/sig0000030f ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \blk00000003/blk00000004/blk0000100e ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00000322 ), + .O(\blk00000003/blk00000004/sig00000301 ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \blk00000003/blk00000004/blk0000100d ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00000324 ), + .O(\blk00000003/blk00000004/sig00000303 ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \blk00000003/blk00000004/blk0000100c ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00000326 ), + .O(\blk00000003/blk00000004/sig00000305 ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \blk00000003/blk00000004/blk0000100b ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00000328 ), + .O(\blk00000003/blk00000004/sig00000307 ) + ); + LUT2 #( + .INIT ( 4'h1 )) + \blk00000003/blk00000004/blk0000100a ( + .I0(\blk00000003/blk00000004/sig000019f7 ), + .I1(\blk00000003/blk00000004/sig000019fb ), + .O(\blk00000003/blk00000004/sig000019f6 ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \blk00000003/blk00000004/blk00001009 ( + .I0(\blk00000003/blk00000004/sig000019fb ), + .I1(\blk00000003/blk00000004/sig000019f7 ), + .O(\blk00000003/blk00000004/sig000019fa ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \blk00000003/blk00000004/blk00001008 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig000000cc ), + .O(\blk00000003/blk00000004/sig00001a20 ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \blk00000003/blk00000004/blk00001007 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00000743 ), + .O(\blk00000003/blk00000004/sig0000014f ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \blk00000003/blk00000004/blk00001006 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00000a57 ), + .O(\blk00000003/blk00000004/sig0000013b ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \blk00000003/blk00000004/blk00001005 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00000aa1 ), + .O(\blk00000003/blk00000004/sig00000139 ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \blk00000003/blk00000004/blk00001004 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00000aeb ), + .O(\blk00000003/blk00000004/sig00000137 ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \blk00000003/blk00000004/blk00001003 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00000b35 ), + .O(\blk00000003/blk00000004/sig00000135 ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \blk00000003/blk00000004/blk00001002 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00000b7f ), + .O(\blk00000003/blk00000004/sig00000133 ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \blk00000003/blk00000004/blk00001001 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00000bc9 ), + .O(\blk00000003/blk00000004/sig00000131 ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \blk00000003/blk00000004/blk00001000 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00000c13 ), + .O(\blk00000003/blk00000004/sig0000012f ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \blk00000003/blk00000004/blk00000fff ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00000c5d ), + .O(\blk00000003/blk00000004/sig0000012d ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \blk00000003/blk00000004/blk00000ffe ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00000ca7 ), + .O(\blk00000003/blk00000004/sig0000012b ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \blk00000003/blk00000004/blk00000ffd ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00000cf1 ), + .O(\blk00000003/blk00000004/sig00000129 ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \blk00000003/blk00000004/blk00000ffc ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig000007a1 ), + .O(\blk00000003/blk00000004/sig0000014d ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \blk00000003/blk00000004/blk00000ffb ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00000d3b ), + .O(\blk00000003/blk00000004/sig00000127 ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \blk00000003/blk00000004/blk00000ffa ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00000d85 ), + .O(\blk00000003/blk00000004/sig00000125 ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \blk00000003/blk00000004/blk00000ff9 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00000dcf ), + .O(\blk00000003/blk00000004/sig00000123 ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \blk00000003/blk00000004/blk00000ff8 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00000e19 ), + .O(\blk00000003/blk00000004/sig00000121 ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \blk00000003/blk00000004/blk00000ff7 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00000e63 ), + .O(\blk00000003/blk00000004/sig0000011f ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \blk00000003/blk00000004/blk00000ff6 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00000ead ), + .O(\blk00000003/blk00000004/sig0000011d ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \blk00000003/blk00000004/blk00000ff5 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00000ef7 ), + .O(\blk00000003/blk00000004/sig0000011b ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \blk00000003/blk00000004/blk00000ff4 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00000f41 ), + .O(\blk00000003/blk00000004/sig00000119 ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \blk00000003/blk00000004/blk00000ff3 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00000f8b ), + .O(\blk00000003/blk00000004/sig00000117 ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \blk00000003/blk00000004/blk00000ff2 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00000fd5 ), + .O(\blk00000003/blk00000004/sig00000115 ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \blk00000003/blk00000004/blk00000ff1 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig000007ef ), + .O(\blk00000003/blk00000004/sig0000014b ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \blk00000003/blk00000004/blk00000ff0 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig0000101f ), + .O(\blk00000003/blk00000004/sig00000113 ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \blk00000003/blk00000004/blk00000fef ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00001069 ), + .O(\blk00000003/blk00000004/sig00000111 ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \blk00000003/blk00000004/blk00000fee ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig000010b3 ), + .O(\blk00000003/blk00000004/sig0000010f ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \blk00000003/blk00000004/blk00000fed ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig000010fd ), + .O(\blk00000003/blk00000004/sig0000010d ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \blk00000003/blk00000004/blk00000fec ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00001147 ), + .O(\blk00000003/blk00000004/sig0000010b ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \blk00000003/blk00000004/blk00000feb ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00001191 ), + .O(\blk00000003/blk00000004/sig00000109 ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \blk00000003/blk00000004/blk00000fea ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig000011db ), + .O(\blk00000003/blk00000004/sig00000107 ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \blk00000003/blk00000004/blk00000fe9 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00001225 ), + .O(\blk00000003/blk00000004/sig00000105 ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \blk00000003/blk00000004/blk00000fe8 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig0000126f ), + .O(\blk00000003/blk00000004/sig00000103 ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \blk00000003/blk00000004/blk00000fe7 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig000012b9 ), + .O(\blk00000003/blk00000004/sig00000101 ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \blk00000003/blk00000004/blk00000fe6 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig0000084d ), + .O(\blk00000003/blk00000004/sig00000149 ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \blk00000003/blk00000004/blk00000fe5 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00001303 ), + .O(\blk00000003/blk00000004/sig000000ff ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \blk00000003/blk00000004/blk00000fe4 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig0000134d ), + .O(\blk00000003/blk00000004/sig000000fd ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \blk00000003/blk00000004/blk00000fe3 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00001397 ), + .O(\blk00000003/blk00000004/sig000000fb ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \blk00000003/blk00000004/blk00000fe2 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig000013e1 ), + .O(\blk00000003/blk00000004/sig000000f9 ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \blk00000003/blk00000004/blk00000fe1 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig0000142b ), + .O(\blk00000003/blk00000004/sig000000f7 ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \blk00000003/blk00000004/blk00000fe0 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00001475 ), + .O(\blk00000003/blk00000004/sig000000f5 ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \blk00000003/blk00000004/blk00000fdf ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig000014bf ), + .O(\blk00000003/blk00000004/sig000000f3 ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \blk00000003/blk00000004/blk00000fde ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00001509 ), + .O(\blk00000003/blk00000004/sig000000f1 ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \blk00000003/blk00000004/blk00000fdd ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00001553 ), + .O(\blk00000003/blk00000004/sig000000ef ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \blk00000003/blk00000004/blk00000fdc ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig0000159d ), + .O(\blk00000003/blk00000004/sig000000ed ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \blk00000003/blk00000004/blk00000fdb ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig0000089b ), + .O(\blk00000003/blk00000004/sig00000147 ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \blk00000003/blk00000004/blk00000fda ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig000015e7 ), + .O(\blk00000003/blk00000004/sig000000eb ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \blk00000003/blk00000004/blk00000fd9 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00001631 ), + .O(\blk00000003/blk00000004/sig000000e9 ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \blk00000003/blk00000004/blk00000fd8 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig0000167b ), + .O(\blk00000003/blk00000004/sig000000e7 ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \blk00000003/blk00000004/blk00000fd7 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig000016c5 ), + .O(\blk00000003/blk00000004/sig000000e5 ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \blk00000003/blk00000004/blk00000fd6 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig0000170f ), + .O(\blk00000003/blk00000004/sig000000e3 ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \blk00000003/blk00000004/blk00000fd5 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00001759 ), + .O(\blk00000003/blk00000004/sig000000e1 ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \blk00000003/blk00000004/blk00000fd4 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig000017a3 ), + .O(\blk00000003/blk00000004/sig000000df ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \blk00000003/blk00000004/blk00000fd3 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig000017ed ), + .O(\blk00000003/blk00000004/sig000000dd ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \blk00000003/blk00000004/blk00000fd2 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00001837 ), + .O(\blk00000003/blk00000004/sig000000db ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \blk00000003/blk00000004/blk00000fd1 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00001881 ), + .O(\blk00000003/blk00000004/sig000000d9 ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \blk00000003/blk00000004/blk00000fd0 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig000008e5 ), + .O(\blk00000003/blk00000004/sig00000145 ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \blk00000003/blk00000004/blk00000fcf ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig000018cb ), + .O(\blk00000003/blk00000004/sig000000d7 ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \blk00000003/blk00000004/blk00000fce ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00001915 ), + .O(\blk00000003/blk00000004/sig000000d5 ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \blk00000003/blk00000004/blk00000fcd ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig0000195f ), + .O(\blk00000003/blk00000004/sig000000d3 ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \blk00000003/blk00000004/blk00000fcc ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig000019a9 ), + .O(\blk00000003/blk00000004/sig000000d1 ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \blk00000003/blk00000004/blk00000fcb ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig0000092f ), + .O(\blk00000003/blk00000004/sig00000143 ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \blk00000003/blk00000004/blk00000fca ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00000979 ), + .O(\blk00000003/blk00000004/sig00000141 ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \blk00000003/blk00000004/blk00000fc9 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig000009c3 ), + .O(\blk00000003/blk00000004/sig0000013f ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \blk00000003/blk00000004/blk00000fc8 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00000a0d ), + .O(\blk00000003/blk00000004/sig0000013d ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \blk00000003/blk00000004/blk00000fc7 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig000001a0 ), + .O(\blk00000003/blk00000004/sig00000153 ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \blk00000003/blk00000004/blk00000fc6 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig0000019e ), + .O(\blk00000003/blk00000004/sig00000151 ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \blk00000003/blk00000004/blk00000fc5 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00000154 ), + .O(\blk00000003/blk00000004/sig00000157 ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \blk00000003/blk00000004/blk00000fc4 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00000152 ), + .O(\blk00000003/blk00000004/sig00000155 ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \blk00000003/blk00000004/blk00000fc3 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00000158 ), + .O(\blk00000003/blk00000004/sig0000015b ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \blk00000003/blk00000004/blk00000fc2 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00000156 ), + .O(\blk00000003/blk00000004/sig00000159 ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \blk00000003/blk00000004/blk00000fc1 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00001a42 ), + .O(\blk00000003/blk00000004/sig000000cd ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \blk00000003/blk00000004/blk00000fc0 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig000002cb ), + .O(\blk00000003/blk00000004/sig00000163 ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \blk00000003/blk00000004/blk00000fbf ( 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#( + .INIT ( 4'h4 )) + \blk00000003/blk00000004/blk00000fb9 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig0000015e ), + .O(\blk00000003/blk00000004/sig00000165 ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \blk00000003/blk00000004/blk00000fb8 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig0000016c ), + .O(\blk00000003/blk00000004/sig00000173 ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \blk00000003/blk00000004/blk00000fb7 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig0000016a ), + .O(\blk00000003/blk00000004/sig00000171 ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \blk00000003/blk00000004/blk00000fb6 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00000168 ), + .O(\blk00000003/blk00000004/sig0000016f ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \blk00000003/blk00000004/blk00000fb5 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00000166 ), + .O(\blk00000003/blk00000004/sig0000016d ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \blk00000003/blk00000004/blk00000fb4 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00000174 ), + .O(\blk00000003/blk00000004/sig0000017b ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \blk00000003/blk00000004/blk00000fb3 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00000172 ), + .O(\blk00000003/blk00000004/sig00000179 ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \blk00000003/blk00000004/blk00000fb2 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00000170 ), + .O(\blk00000003/blk00000004/sig00000177 ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \blk00000003/blk00000004/blk00000fb1 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig0000016e ), + .O(\blk00000003/blk00000004/sig00000175 ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \blk00000003/blk00000004/blk00000fb0 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig0000018c ), + .O(\blk00000003/blk00000004/sig0000018f ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \blk00000003/blk00000004/blk00000faf ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig0000018a ), + .O(\blk00000003/blk00000004/sig0000018d ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \blk00000003/blk00000004/blk00000fae ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00000190 ), + .O(\blk00000003/blk00000004/sig00000193 ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \blk00000003/blk00000004/blk00000fad ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig0000018e ), + .O(\blk00000003/blk00000004/sig00000191 ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \blk00000003/blk00000004/blk00000fac ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig000000c6 ), + .O(\blk00000003/blk00000004/sig0000025c ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \blk00000003/blk00000004/blk00000fab ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00000150 ), + .O(\blk00000003/blk00000004/sig00000242 ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \blk00000003/blk00000004/blk00000faa ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig0000013c ), + .O(\blk00000003/blk00000004/sig0000022e ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \blk00000003/blk00000004/blk00000fa9 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig0000013a ), + .O(\blk00000003/blk00000004/sig0000022c ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \blk00000003/blk00000004/blk00000fa8 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00000138 ), + .O(\blk00000003/blk00000004/sig0000022a ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \blk00000003/blk00000004/blk00000fa7 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00000136 ), + .O(\blk00000003/blk00000004/sig00000228 ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \blk00000003/blk00000004/blk00000fa6 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00000134 ), + .O(\blk00000003/blk00000004/sig00000226 ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \blk00000003/blk00000004/blk00000fa5 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00000132 ), + .O(\blk00000003/blk00000004/sig00000224 ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \blk00000003/blk00000004/blk00000fa4 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00000130 ), + .O(\blk00000003/blk00000004/sig00000222 ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \blk00000003/blk00000004/blk00000fa3 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig0000012e ), + .O(\blk00000003/blk00000004/sig00000220 ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \blk00000003/blk00000004/blk00000fa2 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig0000012c ), + .O(\blk00000003/blk00000004/sig0000021e ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \blk00000003/blk00000004/blk00000fa1 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig0000012a ), + .O(\blk00000003/blk00000004/sig0000021c ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \blk00000003/blk00000004/blk00000fa0 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig0000014e ), + .O(\blk00000003/blk00000004/sig00000240 ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \blk00000003/blk00000004/blk00000f9f ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00000128 ), + .O(\blk00000003/blk00000004/sig0000021a ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \blk00000003/blk00000004/blk00000f9e ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00000126 ), + .O(\blk00000003/blk00000004/sig00000218 ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \blk00000003/blk00000004/blk00000f9d ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00000124 ), + .O(\blk00000003/blk00000004/sig00000216 ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \blk00000003/blk00000004/blk00000f9c ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00000122 ), + .O(\blk00000003/blk00000004/sig00000214 ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \blk00000003/blk00000004/blk00000f9b ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00000120 ), + .O(\blk00000003/blk00000004/sig00000212 ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \blk00000003/blk00000004/blk00000f9a ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig0000011e ), + .O(\blk00000003/blk00000004/sig00000210 ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \blk00000003/blk00000004/blk00000f99 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig0000011c ), + .O(\blk00000003/blk00000004/sig0000020e ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \blk00000003/blk00000004/blk00000f98 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig0000011a ), + .O(\blk00000003/blk00000004/sig0000020c ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \blk00000003/blk00000004/blk00000f97 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00000118 ), + .O(\blk00000003/blk00000004/sig0000020a ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \blk00000003/blk00000004/blk00000f96 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00000116 ), + .O(\blk00000003/blk00000004/sig00000208 ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \blk00000003/blk00000004/blk00000f95 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig0000014c ), + .O(\blk00000003/blk00000004/sig0000023e ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \blk00000003/blk00000004/blk00000f94 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00000114 ), + .O(\blk00000003/blk00000004/sig00000206 ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \blk00000003/blk00000004/blk00000f93 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00000112 ), + .O(\blk00000003/blk00000004/sig00000204 ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \blk00000003/blk00000004/blk00000f92 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00000110 ), + .O(\blk00000003/blk00000004/sig00000202 ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \blk00000003/blk00000004/blk00000f91 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig0000010e ), + .O(\blk00000003/blk00000004/sig00000200 ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \blk00000003/blk00000004/blk00000f90 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig0000010c ), + .O(\blk00000003/blk00000004/sig000001fe ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \blk00000003/blk00000004/blk00000f8f ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig0000010a ), + .O(\blk00000003/blk00000004/sig000001fc ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \blk00000003/blk00000004/blk00000f8e ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00000108 ), + .O(\blk00000003/blk00000004/sig000001fa ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \blk00000003/blk00000004/blk00000f8d ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00000106 ), + .O(\blk00000003/blk00000004/sig000001f8 ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \blk00000003/blk00000004/blk00000f8c ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00000104 ), + .O(\blk00000003/blk00000004/sig000001f6 ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \blk00000003/blk00000004/blk00000f8b ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00000102 ), + .O(\blk00000003/blk00000004/sig000001f4 ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \blk00000003/blk00000004/blk00000f8a ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig0000014a ), + .O(\blk00000003/blk00000004/sig0000023c ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \blk00000003/blk00000004/blk00000f89 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00000100 ), + .O(\blk00000003/blk00000004/sig000001f2 ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \blk00000003/blk00000004/blk00000f88 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig000000fe ), + .O(\blk00000003/blk00000004/sig000001f0 ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \blk00000003/blk00000004/blk00000f87 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig000000fc ), + .O(\blk00000003/blk00000004/sig000001ee ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \blk00000003/blk00000004/blk00000f86 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig000000fa ), + .O(\blk00000003/blk00000004/sig000001ec ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \blk00000003/blk00000004/blk00000f85 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig000000f8 ), + .O(\blk00000003/blk00000004/sig000001ea ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \blk00000003/blk00000004/blk00000f84 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig000000f6 ), + .O(\blk00000003/blk00000004/sig000001e8 ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \blk00000003/blk00000004/blk00000f83 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig000000f4 ), + .O(\blk00000003/blk00000004/sig000001e6 ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \blk00000003/blk00000004/blk00000f82 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig000000f2 ), + .O(\blk00000003/blk00000004/sig000001e4 ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \blk00000003/blk00000004/blk00000f81 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig000000f0 ), + .O(\blk00000003/blk00000004/sig000001e2 ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \blk00000003/blk00000004/blk00000f80 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig000000ee ), + .O(\blk00000003/blk00000004/sig000001e0 ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \blk00000003/blk00000004/blk00000f7f ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00000148 ), + .O(\blk00000003/blk00000004/sig0000023a ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \blk00000003/blk00000004/blk00000f7e ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig000000ec ), + .O(\blk00000003/blk00000004/sig000001de ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \blk00000003/blk00000004/blk00000f7d ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig000000ea ), + .O(\blk00000003/blk00000004/sig000001dc ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \blk00000003/blk00000004/blk00000f7c ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig000000e8 ), + .O(\blk00000003/blk00000004/sig000001da ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \blk00000003/blk00000004/blk00000f7b ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig000000e6 ), + .O(\blk00000003/blk00000004/sig000001d8 ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \blk00000003/blk00000004/blk00000f7a ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig000000e4 ), + .O(\blk00000003/blk00000004/sig000001d6 ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \blk00000003/blk00000004/blk00000f79 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig000000e2 ), + .O(\blk00000003/blk00000004/sig000001d4 ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \blk00000003/blk00000004/blk00000f78 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig000000e0 ), + .O(\blk00000003/blk00000004/sig000001d2 ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \blk00000003/blk00000004/blk00000f77 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig000000de ), + .O(\blk00000003/blk00000004/sig000001d0 ) + ); + LUT2 #( + .INIT ( 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.O(\blk00000003/blk00000004/sig000001c6 ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \blk00000003/blk00000004/blk00000f70 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig000000d2 ), + .O(\blk00000003/blk00000004/sig000001c4 ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \blk00000003/blk00000004/blk00000f6f ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00000144 ), + .O(\blk00000003/blk00000004/sig00000236 ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \blk00000003/blk00000004/blk00000f6e ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00000142 ), + .O(\blk00000003/blk00000004/sig00000234 ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \blk00000003/blk00000004/blk00000f6d ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00000140 ), + .O(\blk00000003/blk00000004/sig00000232 ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \blk00000003/blk00000004/blk00000f6c ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig0000013e ), + .O(\blk00000003/blk00000004/sig00000230 ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \blk00000003/blk00000004/blk00000f6b ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig000000d0 ), + .O(\blk00000003/blk00000004/sig000001c2 ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \blk00000003/blk00000004/blk00000f6a ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig000000c8 ), + .O(\blk00000003/blk00000004/sig00000195 ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \blk00000003/blk00000004/blk00000f69 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00000196 ), + .O(\blk00000003/blk00000004/sig00000197 ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \blk00000003/blk00000004/blk00000f68 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00000198 ), + .O(\blk00000003/blk00000004/sig00000199 ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \blk00000003/blk00000004/blk00000f67 ( + .I0(\blk00000003/blk00000004/sig000002dd ), + .I1(\blk00000003/blk00000004/sig000002db ), + .O(\blk00000003/blk00000004/sig000001a1 ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \blk00000003/blk00000004/blk00000f66 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig000002eb ), + .O(\blk00000003/blk00000004/sig0000017f ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \blk00000003/blk00000004/blk00000f65 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig000002ed ), + .O(\blk00000003/blk00000004/sig0000017d ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \blk00000003/blk00000004/blk00000f64 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00000180 ), + .O(\blk00000003/blk00000004/sig00000183 ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \blk00000003/blk00000004/blk00000f63 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig0000017e ), + .O(\blk00000003/blk00000004/sig00000181 ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \blk00000003/blk00000004/blk00000f62 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00000184 ), + .O(\blk00000003/blk00000004/sig00000187 ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \blk00000003/blk00000004/blk00000f61 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00000182 ), + .O(\blk00000003/blk00000004/sig00000185 ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \blk00000003/blk00000004/blk00000f60 ( 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#( + .INIT ( 4'h1 )) + \blk00000003/blk00000004/blk00000f5a ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig000000ca ), + .O(\blk00000003/blk00000004/sig000000c7 ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \blk00000003/blk00000004/blk00000f59 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig000019e3 ), + .O(\blk00000003/blk00000004/sig0000064a ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \blk00000003/blk00000004/blk00000f58 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig000019e5 ), + .O(\blk00000003/blk00000004/sig0000064c ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \blk00000003/blk00000004/blk00000f57 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig000019e7 ), + .O(\blk00000003/blk00000004/sig0000064e ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \blk00000003/blk00000004/blk00000f56 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig000016ff ), + .O(\blk00000003/blk00000004/sig0000060e ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \blk00000003/blk00000004/blk00000f55 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00001701 ), + .O(\blk00000003/blk00000004/sig00000610 ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \blk00000003/blk00000004/blk00000f54 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00001703 ), + .O(\blk00000003/blk00000004/sig00000612 ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \blk00000003/blk00000004/blk00000f53 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig000016b5 ), + .O(\blk00000003/blk00000004/sig00000608 ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \blk00000003/blk00000004/blk00000f52 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig000016b7 ), + .O(\blk00000003/blk00000004/sig0000060a ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \blk00000003/blk00000004/blk00000f51 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig000016b9 ), + .O(\blk00000003/blk00000004/sig0000060c ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \blk00000003/blk00000004/blk00000f50 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig0000166b ), + .O(\blk00000003/blk00000004/sig00000602 ) + ); + LUT2 #( + .INIT ( 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#( + .INIT ( 4'h4 )) + \blk00000003/blk00000004/blk00000f3e ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig000014af ), + .O(\blk00000003/blk00000004/sig000005de ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \blk00000003/blk00000004/blk00000f3d ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig000014b1 ), + .O(\blk00000003/blk00000004/sig000005e0 ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \blk00000003/blk00000004/blk00000f3c ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig000014b3 ), + .O(\blk00000003/blk00000004/sig000005e2 ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \blk00000003/blk00000004/blk00000f3b ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00001465 ), + .O(\blk00000003/blk00000004/sig000005d8 ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \blk00000003/blk00000004/blk00000f3a ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00001467 ), + .O(\blk00000003/blk00000004/sig000005da ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \blk00000003/blk00000004/blk00000f39 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00001469 ), + .O(\blk00000003/blk00000004/sig000005dc ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \blk00000003/blk00000004/blk00000f38 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00001999 ), + .O(\blk00000003/blk00000004/sig00000644 ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \blk00000003/blk00000004/blk00000f37 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig0000199b ), + .O(\blk00000003/blk00000004/sig00000646 ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \blk00000003/blk00000004/blk00000f36 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig0000199d ), + .O(\blk00000003/blk00000004/sig00000648 ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \blk00000003/blk00000004/blk00000f35 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig0000141b ), + .O(\blk00000003/blk00000004/sig000005d2 ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \blk00000003/blk00000004/blk00000f34 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig0000141d ), + .O(\blk00000003/blk00000004/sig000005d4 ) + ); + LUT2 #( + .INIT ( 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.O(\blk00000003/blk00000004/sig000005c8 ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \blk00000003/blk00000004/blk00000f2d ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig0000138b ), + .O(\blk00000003/blk00000004/sig000005ca ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \blk00000003/blk00000004/blk00000f2c ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig0000133d ), + .O(\blk00000003/blk00000004/sig000005c0 ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \blk00000003/blk00000004/blk00000f2b ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig0000133f ), + .O(\blk00000003/blk00000004/sig000005c2 ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \blk00000003/blk00000004/blk00000f2a ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00001341 ), + .O(\blk00000003/blk00000004/sig000005c4 ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \blk00000003/blk00000004/blk00000f29 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig000012f3 ), + .O(\blk00000003/blk00000004/sig000005ba ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \blk00000003/blk00000004/blk00000f28 ( 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#( + .INIT ( 4'h4 )) + \blk00000003/blk00000004/blk00000f22 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00001261 ), + .O(\blk00000003/blk00000004/sig000005b0 ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \blk00000003/blk00000004/blk00000f21 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00001263 ), + .O(\blk00000003/blk00000004/sig000005b2 ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \blk00000003/blk00000004/blk00000f20 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00001215 ), + .O(\blk00000003/blk00000004/sig000005a8 ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \blk00000003/blk00000004/blk00000f1f ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00001217 ), + .O(\blk00000003/blk00000004/sig000005aa ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \blk00000003/blk00000004/blk00000f1e ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00001219 ), + .O(\blk00000003/blk00000004/sig000005ac ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \blk00000003/blk00000004/blk00000f1d ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig000011cb ), + .O(\blk00000003/blk00000004/sig000005a2 ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \blk00000003/blk00000004/blk00000f1c ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig000011cd ), + .O(\blk00000003/blk00000004/sig000005a4 ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \blk00000003/blk00000004/blk00000f1b ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig000011cf ), + .O(\blk00000003/blk00000004/sig000005a6 ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \blk00000003/blk00000004/blk00000f1a ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00001181 ), + .O(\blk00000003/blk00000004/sig0000059c ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \blk00000003/blk00000004/blk00000f19 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00001183 ), + .O(\blk00000003/blk00000004/sig0000059e ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \blk00000003/blk00000004/blk00000f18 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00001185 ), + .O(\blk00000003/blk00000004/sig000005a0 ) + ); + LUT2 #( + .INIT ( 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#( + .INIT ( 4'h4 )) + \blk00000003/blk00000004/blk00000f06 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00001013 ), + .O(\blk00000003/blk00000004/sig00000582 ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \blk00000003/blk00000004/blk00000f05 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00000fc5 ), + .O(\blk00000003/blk00000004/sig00000578 ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \blk00000003/blk00000004/blk00000f04 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00000fc7 ), + .O(\blk00000003/blk00000004/sig0000057a ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \blk00000003/blk00000004/blk00000f03 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00000fc9 ), + .O(\blk00000003/blk00000004/sig0000057c ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \blk00000003/blk00000004/blk00000f02 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00000f7b ), + .O(\blk00000003/blk00000004/sig00000572 ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \blk00000003/blk00000004/blk00000f01 ( + .I0(sclr), + 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.O(\blk00000003/blk00000004/sig00000638 ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \blk00000003/blk00000004/blk00000ef5 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00001907 ), + .O(\blk00000003/blk00000004/sig0000063a ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \blk00000003/blk00000004/blk00000ef4 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00001909 ), + .O(\blk00000003/blk00000004/sig0000063c ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \blk00000003/blk00000004/blk00000ef3 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00000e53 ), + .O(\blk00000003/blk00000004/sig0000055a ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \blk00000003/blk00000004/blk00000ef2 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00000e55 ), + .O(\blk00000003/blk00000004/sig0000055c ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \blk00000003/blk00000004/blk00000ef1 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00000e57 ), + .O(\blk00000003/blk00000004/sig0000055e ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \blk00000003/blk00000004/blk00000ef0 ( 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#( + .INIT ( 4'h4 )) + \blk00000003/blk00000004/blk00000eea ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00000d75 ), + .O(\blk00000003/blk00000004/sig00000548 ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \blk00000003/blk00000004/blk00000ee9 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00000d77 ), + .O(\blk00000003/blk00000004/sig0000054a ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \blk00000003/blk00000004/blk00000ee8 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00000d79 ), + .O(\blk00000003/blk00000004/sig0000054c ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \blk00000003/blk00000004/blk00000ee7 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00000d2b ), + .O(\blk00000003/blk00000004/sig00000542 ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \blk00000003/blk00000004/blk00000ee6 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00000d2d ), + .O(\blk00000003/blk00000004/sig00000544 ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \blk00000003/blk00000004/blk00000ee5 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00000d2f ), + .O(\blk00000003/blk00000004/sig00000546 ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \blk00000003/blk00000004/blk00000ee4 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00000ce1 ), + .O(\blk00000003/blk00000004/sig0000053c ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \blk00000003/blk00000004/blk00000ee3 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00000ce3 ), + .O(\blk00000003/blk00000004/sig0000053e ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \blk00000003/blk00000004/blk00000ee2 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00000ce5 ), + .O(\blk00000003/blk00000004/sig00000540 ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \blk00000003/blk00000004/blk00000ee1 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00000c97 ), + .O(\blk00000003/blk00000004/sig00000536 ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \blk00000003/blk00000004/blk00000ee0 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00000c99 ), + .O(\blk00000003/blk00000004/sig00000538 ) + ); + LUT2 #( + .INIT ( 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.O(\blk00000003/blk00000004/sig0000052c ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \blk00000003/blk00000004/blk00000ed9 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00000c07 ), + .O(\blk00000003/blk00000004/sig0000052e ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \blk00000003/blk00000004/blk00000ed8 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00000bb9 ), + .O(\blk00000003/blk00000004/sig00000524 ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \blk00000003/blk00000004/blk00000ed7 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00000bbb ), + .O(\blk00000003/blk00000004/sig00000526 ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \blk00000003/blk00000004/blk00000ed6 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00000bbd ), + .O(\blk00000003/blk00000004/sig00000528 ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \blk00000003/blk00000004/blk00000ed5 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig000018bb ), + .O(\blk00000003/blk00000004/sig00000632 ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \blk00000003/blk00000004/blk00000ed4 ( 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#( + .INIT ( 4'h4 )) + \blk00000003/blk00000004/blk00000ece ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00000b27 ), + .O(\blk00000003/blk00000004/sig0000051a ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \blk00000003/blk00000004/blk00000ecd ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00000b29 ), + .O(\blk00000003/blk00000004/sig0000051c ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \blk00000003/blk00000004/blk00000ecc ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00000adb ), + .O(\blk00000003/blk00000004/sig00000512 ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \blk00000003/blk00000004/blk00000ecb ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00000add ), + .O(\blk00000003/blk00000004/sig00000514 ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \blk00000003/blk00000004/blk00000eca ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00000adf ), + .O(\blk00000003/blk00000004/sig00000516 ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \blk00000003/blk00000004/blk00000ec9 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00000a91 ), + .O(\blk00000003/blk00000004/sig0000050c ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \blk00000003/blk00000004/blk00000ec8 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00000a93 ), + .O(\blk00000003/blk00000004/sig0000050e ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \blk00000003/blk00000004/blk00000ec7 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00000a95 ), + .O(\blk00000003/blk00000004/sig00000510 ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \blk00000003/blk00000004/blk00000ec6 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00000a47 ), + .O(\blk00000003/blk00000004/sig00000506 ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \blk00000003/blk00000004/blk00000ec5 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00000a49 ), + .O(\blk00000003/blk00000004/sig00000508 ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \blk00000003/blk00000004/blk00000ec4 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00000a4b ), + .O(\blk00000003/blk00000004/sig0000050a ) + ); + LUT2 #( + .INIT ( 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#( + .INIT ( 4'h4 )) + \blk00000003/blk00000004/blk00000eb2 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00001875 ), + .O(\blk00000003/blk00000004/sig00000630 ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \blk00000003/blk00000004/blk00000eb1 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig0000088b ), + .O(\blk00000003/blk00000004/sig000004e2 ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \blk00000003/blk00000004/blk00000eb0 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig0000088d ), + .O(\blk00000003/blk00000004/sig000004e4 ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \blk00000003/blk00000004/blk00000eaf ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig0000088f ), + .O(\blk00000003/blk00000004/sig000004e6 ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \blk00000003/blk00000004/blk00000eae ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig0000083d ), + .O(\blk00000003/blk00000004/sig000004dc ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \blk00000003/blk00000004/blk00000ead ( + .I0(sclr), + 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.O(\blk00000003/blk00000004/sig00000620 ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \blk00000003/blk00000004/blk00000ea1 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig000017df ), + .O(\blk00000003/blk00000004/sig00000622 ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \blk00000003/blk00000004/blk00000ea0 ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig000017e1 ), + .O(\blk00000003/blk00000004/sig00000624 ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \blk00000003/blk00000004/blk00000e9f ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00001793 ), + .O(\blk00000003/blk00000004/sig0000061a ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \blk00000003/blk00000004/blk00000e9e ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00001795 ), + .O(\blk00000003/blk00000004/sig0000061c ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \blk00000003/blk00000004/blk00000e9d ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00001797 ), + .O(\blk00000003/blk00000004/sig0000061e ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \blk00000003/blk00000004/blk00000e9c ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig00001749 ), + .O(\blk00000003/blk00000004/sig00000614 ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \blk00000003/blk00000004/blk00000e9b ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig0000174b ), + .O(\blk00000003/blk00000004/sig00000616 ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \blk00000003/blk00000004/blk00000e9a ( + .I0(sclr), + .I1(\blk00000003/blk00000004/sig0000174d ), + .O(\blk00000003/blk00000004/sig00000618 ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \blk00000003/blk00000004/blk00000e99 ( + .I0(\blk00000003/blk00000004/sig000019f3 ), + .I1(ce), + .O(\blk00000003/blk00000004/sig00001a1f ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \blk00000003/blk00000004/blk00000e98 ( + .I0(sclr), + .I1(erase_2[1]), + .O(\blk00000003/blk00000004/sig000000a2 ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \blk00000003/blk00000004/blk00000e97 ( + .I0(sclr), + .I1(erase_2[0]), + .O(\blk00000003/blk00000004/sig000000a4 ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \blk00000003/blk00000004/blk00000e96 ( + .I0(sclr), + .I1(data_in0_0[2]), + .O(\blk00000003/blk00000004/sig0000009c ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \blk00000003/blk00000004/blk00000e95 ( + .I0(sclr), + .I1(data_in0_0[1]), + .O(\blk00000003/blk00000004/sig0000009e ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \blk00000003/blk00000004/blk00000e94 ( + .I0(sclr), + .I1(data_in0_0[0]), + .O(\blk00000003/blk00000004/sig000000a0 ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \blk00000003/blk00000004/blk00000e93 ( + .I0(sclr), + .I1(data_in1_1[2]), + .O(\blk00000003/blk00000004/sig00000096 ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \blk00000003/blk00000004/blk00000e92 ( + .I0(sclr), + .I1(data_in1_1[1]), + .O(\blk00000003/blk00000004/sig00000098 ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \blk00000003/blk00000004/blk00000e91 ( + .I0(sclr), + .I1(data_in1_1[0]), + .O(\blk00000003/blk00000004/sig0000009a ) + ); + MUXCY \blk00000003/blk00000004/blk00000e90 ( + .CI(\blk00000003/blk00000004/sig00001a40 ), + .DI(\blk00000003/sig00000001 ), + .S(\blk00000003/blk00000004/sig00001a41 ), + .O(\blk00000003/blk00000004/sig00000740 ) + ); + LUT4 #( + .INIT ( 16'h0800 )) + \blk00000003/blk00000004/blk00000e8f ( + .I0(\blk00000003/blk00000004/sig0000194f ), + .I1(\blk00000003/blk00000004/sig00000791 ), + .I2(sclr), + .I3(\blk00000003/blk00000004/sig000007df ), + .O(\blk00000003/blk00000004/sig00001a41 ) + ); + MUXCY \blk00000003/blk00000004/blk00000e8e ( + .CI(\blk00000003/blk00000004/sig00001a3e ), + .DI(\blk00000003/sig00000001 ), + .S(\blk00000003/blk00000004/sig00001a3f ), + .O(\blk00000003/blk00000004/sig00001a40 ) + ); + LUT4 #( + .INIT ( 16'h8000 )) + \blk00000003/blk00000004/blk00000e8d ( + .I0(\blk00000003/blk00000004/sig000008d5 ), + .I1(\blk00000003/blk00000004/sig0000088b ), + .I2(\blk00000003/blk00000004/sig00001999 ), + .I3(\blk00000003/blk00000004/sig0000083d ), + .O(\blk00000003/blk00000004/sig00001a3f ) + ); + MUXCY \blk00000003/blk00000004/blk00000e8c ( + .CI(\blk00000003/blk00000004/sig00001a3c ), + .DI(\blk00000003/sig00000001 ), + .S(\blk00000003/blk00000004/sig00001a3d ), + .O(\blk00000003/blk00000004/sig00001a3e ) + ); + LUT4 #( + .INIT ( 16'h8000 )) + \blk00000003/blk00000004/blk00000e8b ( + .I0(\blk00000003/blk00000004/sig000009b3 ), + .I1(\blk00000003/blk00000004/sig00000969 ), + .I2(\blk00000003/blk00000004/sig00001905 ), + .I3(\blk00000003/blk00000004/sig0000091f ), + .O(\blk00000003/blk00000004/sig00001a3d ) + ); + MUXCY \blk00000003/blk00000004/blk00000e8a ( + .CI(\blk00000003/blk00000004/sig00001a3a ), + .DI(\blk00000003/sig00000001 ), + .S(\blk00000003/blk00000004/sig00001a3b ), + .O(\blk00000003/blk00000004/sig00001a3c ) + ); + LUT4 #( + .INIT ( 16'h8000 )) + \blk00000003/blk00000004/blk00000e89 ( + .I0(\blk00000003/blk00000004/sig00000a91 ), + .I1(\blk00000003/blk00000004/sig00000a47 ), + .I2(\blk00000003/blk00000004/sig000019e3 ), + .I3(\blk00000003/blk00000004/sig000009fd ), + .O(\blk00000003/blk00000004/sig00001a3b ) + ); + MUXCY \blk00000003/blk00000004/blk00000e88 ( + .CI(\blk00000003/blk00000004/sig00001a38 ), + .DI(\blk00000003/sig00000001 ), + .S(\blk00000003/blk00000004/sig00001a39 ), + .O(\blk00000003/blk00000004/sig00001a3a ) + ); + LUT4 #( + .INIT ( 16'h0800 )) + \blk00000003/blk00000004/blk00000e87 ( + .I0(\blk00000003/blk00000004/sig00000b6f ), + .I1(\blk00000003/blk00000004/sig00000b25 ), + .I2(\blk00000003/blk00000004/sig00000741 ), + .I3(\blk00000003/blk00000004/sig00000adb ), + .O(\blk00000003/blk00000004/sig00001a39 ) + ); + MUXCY \blk00000003/blk00000004/blk00000e86 ( + .CI(\blk00000003/blk00000004/sig00001a36 ), + .DI(\blk00000003/sig00000001 ), + .S(\blk00000003/blk00000004/sig00001a37 ), + .O(\blk00000003/blk00000004/sig00001a38 ) + ); + LUT4 #( + .INIT ( 16'h8000 )) + \blk00000003/blk00000004/blk00000e85 ( + .I0(\blk00000003/blk00000004/sig00000c4d ), + .I1(\blk00000003/blk00000004/sig00000c03 ), + .I2(\blk00000003/blk00000004/sig000018bb ), + .I3(\blk00000003/blk00000004/sig00000bb9 ), + .O(\blk00000003/blk00000004/sig00001a37 ) + ); + MUXCY \blk00000003/blk00000004/blk00000e84 ( + .CI(\blk00000003/blk00000004/sig00001a34 ), + .DI(\blk00000003/sig00000001 ), + .S(\blk00000003/blk00000004/sig00001a35 ), + .O(\blk00000003/blk00000004/sig00001a36 ) + ); + LUT4 #( + .INIT ( 16'h8000 )) + \blk00000003/blk00000004/blk00000e83 ( + .I0(\blk00000003/blk00000004/sig00000d2b ), + .I1(\blk00000003/blk00000004/sig00000ce1 ), + .I2(\blk00000003/blk00000004/sig00001871 ), + .I3(\blk00000003/blk00000004/sig00000c97 ), + .O(\blk00000003/blk00000004/sig00001a35 ) + ); + MUXCY \blk00000003/blk00000004/blk00000e82 ( + .CI(\blk00000003/blk00000004/sig00001a32 ), + .DI(\blk00000003/sig00000001 ), + .S(\blk00000003/blk00000004/sig00001a33 ), + .O(\blk00000003/blk00000004/sig00001a34 ) + ); + LUT4 #( + .INIT ( 16'h8000 )) + \blk00000003/blk00000004/blk00000e81 ( + .I0(\blk00000003/blk00000004/sig00000e09 ), + .I1(\blk00000003/blk00000004/sig00000dbf ), + .I2(\blk00000003/blk00000004/sig00001827 ), + .I3(\blk00000003/blk00000004/sig00000d75 ), + .O(\blk00000003/blk00000004/sig00001a33 ) + ); + MUXCY \blk00000003/blk00000004/blk00000e80 ( + .CI(\blk00000003/blk00000004/sig00001a30 ), + .DI(\blk00000003/sig00000001 ), + .S(\blk00000003/blk00000004/sig00001a31 ), + .O(\blk00000003/blk00000004/sig00001a32 ) + ); + LUT4 #( + .INIT ( 16'h8000 )) + \blk00000003/blk00000004/blk00000e7f ( + .I0(\blk00000003/blk00000004/sig00000ee7 ), + .I1(\blk00000003/blk00000004/sig00000e9d ), + .I2(\blk00000003/blk00000004/sig000017dd ), + .I3(\blk00000003/blk00000004/sig00000e53 ), + .O(\blk00000003/blk00000004/sig00001a31 ) + ); + MUXCY \blk00000003/blk00000004/blk00000e7e ( + .CI(\blk00000003/blk00000004/sig00001a2e ), + .DI(\blk00000003/sig00000001 ), + .S(\blk00000003/blk00000004/sig00001a2f ), + .O(\blk00000003/blk00000004/sig00001a30 ) + ); + LUT4 #( + .INIT ( 16'h8000 )) + \blk00000003/blk00000004/blk00000e7d ( + .I0(\blk00000003/blk00000004/sig00000fc5 ), + .I1(\blk00000003/blk00000004/sig00000f7b ), + .I2(\blk00000003/blk00000004/sig00001793 ), + .I3(\blk00000003/blk00000004/sig00000f31 ), + .O(\blk00000003/blk00000004/sig00001a2f ) + ); + MUXCY \blk00000003/blk00000004/blk00000e7c ( + .CI(\blk00000003/blk00000004/sig00001a2c ), + .DI(\blk00000003/sig00000001 ), + .S(\blk00000003/blk00000004/sig00001a2d ), + .O(\blk00000003/blk00000004/sig00001a2e ) + ); + LUT4 #( + .INIT ( 16'h8000 )) + \blk00000003/blk00000004/blk00000e7b ( + .I0(\blk00000003/blk00000004/sig000010ed ), + .I1(\blk00000003/blk00000004/sig000010a3 ), + .I2(\blk00000003/blk00000004/sig00001749 ), + .I3(\blk00000003/blk00000004/sig0000100f ), + .O(\blk00000003/blk00000004/sig00001a2d ) + ); + MUXCY \blk00000003/blk00000004/blk00000e7a ( + .CI(\blk00000003/blk00000004/sig00001a2a ), + .DI(\blk00000003/sig00000001 ), + .S(\blk00000003/blk00000004/sig00001a2b ), + .O(\blk00000003/blk00000004/sig00001a2c ) + ); + LUT4 #( + .INIT ( 16'h8000 )) + \blk00000003/blk00000004/blk00000e79 ( + .I0(\blk00000003/blk00000004/sig00001181 ), + .I1(\blk00000003/blk00000004/sig00001137 ), + .I2(\blk00000003/blk00000004/sig000016ff ), + .I3(\blk00000003/blk00000004/sig00001059 ), + .O(\blk00000003/blk00000004/sig00001a2b ) + ); + MUXCY \blk00000003/blk00000004/blk00000e78 ( + .CI(\blk00000003/blk00000004/sig00001a28 ), + .DI(\blk00000003/sig00000001 ), + .S(\blk00000003/blk00000004/sig00001a29 ), + .O(\blk00000003/blk00000004/sig00001a2a ) + ); + LUT4 #( + .INIT ( 16'h8000 )) + \blk00000003/blk00000004/blk00000e77 ( + .I0(\blk00000003/blk00000004/sig0000125f ), + .I1(\blk00000003/blk00000004/sig00001215 ), + .I2(\blk00000003/blk00000004/sig000016b5 ), + .I3(\blk00000003/blk00000004/sig000011cb ), + .O(\blk00000003/blk00000004/sig00001a29 ) + ); + MUXCY \blk00000003/blk00000004/blk00000e76 ( + .CI(\blk00000003/blk00000004/sig00001a26 ), + .DI(\blk00000003/sig00000001 ), + .S(\blk00000003/blk00000004/sig00001a27 ), + .O(\blk00000003/blk00000004/sig00001a28 ) + ); + LUT4 #( + .INIT ( 16'h8000 )) + \blk00000003/blk00000004/blk00000e75 ( + .I0(\blk00000003/blk00000004/sig0000133d ), + .I1(\blk00000003/blk00000004/sig000012f3 ), + .I2(\blk00000003/blk00000004/sig0000166b ), + .I3(\blk00000003/blk00000004/sig000012a9 ), + .O(\blk00000003/blk00000004/sig00001a27 ) + ); + MUXCY \blk00000003/blk00000004/blk00000e74 ( + .CI(\blk00000003/blk00000004/sig00001a24 ), + .DI(\blk00000003/sig00000001 ), + .S(\blk00000003/blk00000004/sig00001a25 ), + .O(\blk00000003/blk00000004/sig00001a26 ) + ); + LUT4 #( + .INIT ( 16'h8000 )) + \blk00000003/blk00000004/blk00000e73 ( + .I0(\blk00000003/blk00000004/sig0000141b ), + .I1(\blk00000003/blk00000004/sig000013d1 ), + .I2(\blk00000003/blk00000004/sig00001621 ), + .I3(\blk00000003/blk00000004/sig00001387 ), + .O(\blk00000003/blk00000004/sig00001a25 ) + ); + MUXCY \blk00000003/blk00000004/blk00000e72 ( + .CI(\blk00000003/blk00000004/sig00001a22 ), + .DI(\blk00000003/sig00000001 ), + .S(\blk00000003/blk00000004/sig00001a23 ), + .O(\blk00000003/blk00000004/sig00001a24 ) + ); + LUT4 #( + .INIT ( 16'h8000 )) + \blk00000003/blk00000004/blk00000e71 ( + .I0(\blk00000003/blk00000004/sig000014f9 ), + .I1(\blk00000003/blk00000004/sig000014af ), + .I2(\blk00000003/blk00000004/sig000015d7 ), + .I3(\blk00000003/blk00000004/sig00001465 ), + .O(\blk00000003/blk00000004/sig00001a23 ) + ); + MUXCY \blk00000003/blk00000004/blk00000e70 ( + .CI(\blk00000003/blk00000004/sig00000093 ), + .DI(\blk00000003/sig00000001 ), + .S(\blk00000003/blk00000004/sig00001a21 ), + .O(\blk00000003/blk00000004/sig00001a22 ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk00000004/blk00000e6f ( + .I0(\blk00000003/blk00000004/sig0000158d ), + .I1(\blk00000003/blk00000004/sig00001543 ), + .O(\blk00000003/blk00000004/sig00001a21 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk00000e6e ( + .C(clk), + .CE(\blk00000003/blk00000004/sig00001a1f ), + .D(\blk00000003/blk00000004/sig00001a20 ), + .Q(\blk00000003/blk00000004/sig00000094 ) + ); + RAM64X1S #( + .INIT ( 64'h80000001608C9E80 )) + \blk00000003/blk00000004/blk00000e6d ( + .A0(\blk00000003/blk00000004/sig00001a01 ), + .A1(\blk00000003/blk00000004/sig00001a03 ), + .A2(\blk00000003/blk00000004/sig00001a05 ), + .A3(\blk00000003/blk00000004/sig00001a07 ), + .A4(\blk00000003/blk00000004/sig00001a09 ), + .A5(\blk00000003/blk00000004/sig00001a0b ), + .D(\blk00000003/blk00000004/sig000019f9 ), + .WCLK(clk), + .WE(\blk00000003/blk00000004/sig000019f5 ), + .O(\blk00000003/blk00000004/sig00001a0e ) + ); + XORCY \blk00000003/blk00000004/blk00000e6c ( + .CI(\blk00000003/blk00000004/sig00001a1d ), + .LI(\blk00000003/blk00000004/sig00001a1e ), + .O(\blk00000003/blk00000004/sig000019fc ) + ); + MUXCY \blk00000003/blk00000004/blk00000e6b ( + .CI(\blk00000003/blk00000004/sig00001a1d ), + .DI(\blk00000003/sig00000001 ), + .S(\blk00000003/blk00000004/sig00001a1e ), + .O(\blk00000003/blk00000004/sig000019ff ) + ); + XORCY \blk00000003/blk00000004/blk00000e6a ( + .CI(\blk00000003/blk00000004/sig00001a1b ), + .LI(\blk00000003/blk00000004/sig00001a1c ), + .O(\blk00000003/blk00000004/sig00001a0a ) + ); + MUXCY \blk00000003/blk00000004/blk00000e69 ( + .CI(\blk00000003/blk00000004/sig00001a1b ), + .DI(\blk00000003/sig00000001 ), + .S(\blk00000003/blk00000004/sig00001a1c ), + .O(\blk00000003/blk00000004/sig00001a1d ) + ); + XORCY \blk00000003/blk00000004/blk00000e68 ( + .CI(\blk00000003/blk00000004/sig00001a19 ), + .LI(\blk00000003/blk00000004/sig00001a1a ), + .O(\blk00000003/blk00000004/sig00001a08 ) + ); + MUXCY \blk00000003/blk00000004/blk00000e67 ( + .CI(\blk00000003/blk00000004/sig00001a19 ), + .DI(\blk00000003/sig00000001 ), + .S(\blk00000003/blk00000004/sig00001a1a ), + .O(\blk00000003/blk00000004/sig00001a1b ) + ); + XORCY \blk00000003/blk00000004/blk00000e66 ( + .CI(\blk00000003/blk00000004/sig00001a17 ), + .LI(\blk00000003/blk00000004/sig00001a18 ), + .O(\blk00000003/blk00000004/sig00001a06 ) + ); + MUXCY \blk00000003/blk00000004/blk00000e65 ( + .CI(\blk00000003/blk00000004/sig00001a17 ), + .DI(\blk00000003/sig00000001 ), + .S(\blk00000003/blk00000004/sig00001a18 ), + .O(\blk00000003/blk00000004/sig00001a19 ) + ); + XORCY \blk00000003/blk00000004/blk00000e64 ( + .CI(\blk00000003/blk00000004/sig00001a15 ), + .LI(\blk00000003/blk00000004/sig00001a16 ), + .O(\blk00000003/blk00000004/sig00001a04 ) + ); + MUXCY \blk00000003/blk00000004/blk00000e63 ( + .CI(\blk00000003/blk00000004/sig00001a15 ), + .DI(\blk00000003/sig00000001 ), + .S(\blk00000003/blk00000004/sig00001a16 ), + .O(\blk00000003/blk00000004/sig00001a17 ) + ); + XORCY \blk00000003/blk00000004/blk00000e62 ( + .CI(\blk00000003/blk00000004/sig00001a13 ), + .LI(\blk00000003/blk00000004/sig00001a14 ), + .O(\blk00000003/blk00000004/sig00001a02 ) + ); + MUXCY \blk00000003/blk00000004/blk00000e61 ( + .CI(\blk00000003/blk00000004/sig00001a13 ), + .DI(\blk00000003/sig00000001 ), + .S(\blk00000003/blk00000004/sig00001a14 ), + .O(\blk00000003/blk00000004/sig00001a15 ) + ); + XORCY \blk00000003/blk00000004/blk00000e60 ( + .CI(\blk00000003/sig00000001 ), + .LI(\blk00000003/blk00000004/sig00001a12 ), + .O(\blk00000003/blk00000004/sig00001a00 ) + ); + MUXCY \blk00000003/blk00000004/blk00000e5f ( + .CI(\blk00000003/sig00000001 ), + .DI(\blk00000003/blk00000004/sig00000093 ), + .S(\blk00000003/blk00000004/sig00001a12 ), + .O(\blk00000003/blk00000004/sig00001a13 ) + ); + FDSE #( + .INIT ( 1'b1 )) + \blk00000003/blk00000004/blk00000e5e ( + .C(clk), + .CE(\blk00000003/blk00000004/sig000019fb ), + .D(\blk00000003/blk00000004/sig00001a10 ), + .S(\blk00000003/blk00000004/sig000019fd ), + .Q(\blk00000003/blk00000004/sig00001a11 ) + ); + FD #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk00000e5d ( + .C(clk), + .D(\blk00000003/blk00000004/sig00001a0e ), + .Q(\blk00000003/blk00000004/sig00001a0f ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk00000e5c ( + .C(clk), + .CE(\blk00000003/blk00000004/sig000019fb ), + .D(\blk00000003/blk00000004/sig00001a0c ), + .R(\blk00000003/blk00000004/sig000019fd ), + .Q(\blk00000003/blk00000004/sig00001a0d ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk00000e5b ( + .C(clk), + .CE(\blk00000003/blk00000004/sig000019fb ), + .D(\blk00000003/blk00000004/sig00001a0a ), + .R(\blk00000003/blk00000004/sig000019fd ), + .Q(\blk00000003/blk00000004/sig00001a0b ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk00000e5a ( + .C(clk), + .CE(\blk00000003/blk00000004/sig000019fb ), + .D(\blk00000003/blk00000004/sig00001a08 ), + .R(\blk00000003/blk00000004/sig000019fd ), + .Q(\blk00000003/blk00000004/sig00001a09 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk00000e59 ( + .C(clk), + .CE(\blk00000003/blk00000004/sig000019fb ), + .D(\blk00000003/blk00000004/sig00001a06 ), + .R(\blk00000003/blk00000004/sig000019fd ), + .Q(\blk00000003/blk00000004/sig00001a07 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk00000e58 ( + .C(clk), + .CE(\blk00000003/blk00000004/sig000019fb ), + .D(\blk00000003/blk00000004/sig00001a04 ), + .R(\blk00000003/blk00000004/sig000019fd ), + .Q(\blk00000003/blk00000004/sig00001a05 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk00000e57 ( + .C(clk), + .CE(\blk00000003/blk00000004/sig000019fb ), + .D(\blk00000003/blk00000004/sig00001a02 ), + .R(\blk00000003/blk00000004/sig000019fd ), + .Q(\blk00000003/blk00000004/sig00001a03 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk00000e56 ( + .C(clk), + .CE(\blk00000003/blk00000004/sig000019fb ), + .D(\blk00000003/blk00000004/sig00001a00 ), + .R(\blk00000003/blk00000004/sig000019fd ), + .Q(\blk00000003/blk00000004/sig00001a01 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk00000e55 ( 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)) + \blk00000003/blk00000004/blk00000e50 ( + .C(clk), + .D(\blk00000003/blk00000004/sig000019f4 ), + .Q(\blk00000003/blk00000004/sig000019f5 ) + ); + FD #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk00000e4f ( + .C(clk), + .D(\blk00000003/blk00000004/sig000019f2 ), + .Q(\blk00000003/blk00000004/sig000019f3 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk00000e4e ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig000019f0 ), + .Q(\blk00000003/blk00000004/sig000019f1 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk00000e4d ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig000019ee ), + .Q(\blk00000003/blk00000004/sig000019ef ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk00000e4c ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig000019ec ), + .Q(\blk00000003/blk00000004/sig000019ed ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk00000e4b ( + .C(clk), + .CE(ce), + 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\blk00000003/blk00000004/blk0000034e ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig000006e0 ), + .Q(\blk00000003/blk00000004/sig000006e1 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk0000034d ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig000006de ), + .Q(\blk00000003/blk00000004/sig000006df ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk0000034c ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig000006dc ), + .Q(\blk00000003/blk00000004/sig000006dd ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk0000034b ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig000006da ), + .Q(\blk00000003/blk00000004/sig000006db ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk0000034a ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig000006d8 ), + .Q(\blk00000003/blk00000004/sig000006d9 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk00000349 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig000006d6 ), + .Q(\blk00000003/blk00000004/sig000006d7 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk00000348 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig000006d4 ), + .Q(\blk00000003/blk00000004/sig000006d5 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk00000347 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig000006d2 ), + .Q(\blk00000003/blk00000004/sig000006d3 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk00000346 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig000006d0 ), + .Q(\blk00000003/blk00000004/sig000006d1 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk00000345 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig000006ce ), + .Q(\blk00000003/blk00000004/sig000006cf ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk00000344 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig000006cc ), + .Q(\blk00000003/blk00000004/sig000006cd ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk00000343 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig000006ca ), + .Q(\blk00000003/blk00000004/sig000006cb ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk00000342 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig000006c8 ), + .Q(\blk00000003/blk00000004/sig000006c9 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk00000341 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig000006c6 ), + .Q(\blk00000003/blk00000004/sig000006c7 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk00000340 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig000006c4 ), + .Q(\blk00000003/blk00000004/sig000006c5 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk0000033f ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig000006c2 ), + .Q(\blk00000003/blk00000004/sig000006c3 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk0000033e ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig000006c0 ), + .Q(\blk00000003/blk00000004/sig000006c1 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk0000033d ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig000006be ), + .Q(\blk00000003/blk00000004/sig000006bf ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk0000033c ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig000006bc ), + .Q(\blk00000003/blk00000004/sig000006bd ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk0000033b ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig000006ba ), + .Q(\blk00000003/blk00000004/sig000006bb ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk0000033a ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig000006b8 ), + .Q(\blk00000003/blk00000004/sig000006b9 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk00000339 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig000006b6 ), + .Q(\blk00000003/blk00000004/sig000006b7 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk00000338 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig000006b4 ), + .Q(\blk00000003/blk00000004/sig000006b5 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk00000337 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig000006b2 ), + .Q(\blk00000003/blk00000004/sig000006b3 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk00000336 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig000006b0 ), + .Q(\blk00000003/blk00000004/sig000006b1 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk00000335 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig000006ae ), + .Q(\blk00000003/blk00000004/sig000006af ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk00000334 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig000006ac ), + .Q(\blk00000003/blk00000004/sig000006ad ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk00000333 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig000006aa ), + .Q(\blk00000003/blk00000004/sig000006ab ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk00000332 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig000006a8 ), + .Q(\blk00000003/blk00000004/sig000006a9 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk00000331 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig000006a6 ), + .Q(\blk00000003/blk00000004/sig000006a7 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk00000330 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig000006a4 ), + .Q(\blk00000003/blk00000004/sig000006a5 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk0000032f ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig000006a2 ), + .Q(\blk00000003/blk00000004/sig000006a3 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk0000032e ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig000006a0 ), + .Q(\blk00000003/blk00000004/sig000006a1 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk0000032d ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig0000069e ), + .Q(\blk00000003/blk00000004/sig0000069f ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk0000032c ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig0000069c ), + .Q(\blk00000003/blk00000004/sig0000069d ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk0000032b ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig0000069a ), + .Q(\blk00000003/blk00000004/sig0000069b ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk0000032a ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig00000698 ), + .Q(\blk00000003/blk00000004/sig00000699 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk00000329 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig00000696 ), + .Q(\blk00000003/blk00000004/sig00000697 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk00000328 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig00000694 ), + .Q(\blk00000003/blk00000004/sig00000695 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk00000327 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig00000692 ), + .Q(\blk00000003/blk00000004/sig00000693 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk00000326 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig00000690 ), + .Q(\blk00000003/blk00000004/sig00000691 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk00000325 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig0000068e ), + .Q(\blk00000003/blk00000004/sig0000068f ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk00000324 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig0000068c ), + .Q(\blk00000003/blk00000004/sig0000068d ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk00000323 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig0000068a ), + .Q(\blk00000003/blk00000004/sig0000068b ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk00000322 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig00000688 ), + .Q(\blk00000003/blk00000004/sig00000689 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk00000321 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig00000686 ), + .Q(\blk00000003/blk00000004/sig00000687 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk00000320 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig00000684 ), + .Q(\blk00000003/blk00000004/sig00000685 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk0000031f ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig00000682 ), + .Q(\blk00000003/blk00000004/sig00000683 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk0000031e ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig00000680 ), + .Q(\blk00000003/blk00000004/sig00000681 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk0000031d ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig0000067e ), + .Q(\blk00000003/blk00000004/sig0000067f ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk0000031c ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig0000067c ), + .Q(\blk00000003/blk00000004/sig0000067d ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk0000031b ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig0000067a ), + .Q(\blk00000003/blk00000004/sig0000067b ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk0000031a ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig00000678 ), + .Q(\blk00000003/blk00000004/sig00000679 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk00000319 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig00000676 ), + .Q(\blk00000003/blk00000004/sig00000677 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk00000318 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig00000674 ), + .Q(\blk00000003/blk00000004/sig00000675 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk00000317 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig00000672 ), + .Q(\blk00000003/blk00000004/sig00000673 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk00000316 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig00000670 ), + .Q(\blk00000003/blk00000004/sig00000671 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk00000315 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig0000066e ), + .Q(\blk00000003/blk00000004/sig0000066f ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk00000314 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig0000066c ), + .Q(\blk00000003/blk00000004/sig0000066d ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk00000313 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig0000066a ), + .Q(\blk00000003/blk00000004/sig0000066b ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk00000312 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig00000668 ), + .Q(\blk00000003/blk00000004/sig00000669 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk00000311 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig00000666 ), + .Q(\blk00000003/blk00000004/sig00000667 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk00000310 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig00000664 ), + .Q(\blk00000003/blk00000004/sig00000665 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk0000030f ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig00000662 ), + .Q(\blk00000003/blk00000004/sig00000663 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk0000030e ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig00000660 ), + .Q(\blk00000003/blk00000004/sig00000661 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk0000030d ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig0000065e ), + .Q(\blk00000003/blk00000004/sig0000065f ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk0000030c ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig0000065c ), + .Q(\blk00000003/blk00000004/sig0000065d ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk0000030b ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig0000065a ), + .Q(\blk00000003/blk00000004/sig0000065b ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk0000030a ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig00000658 ), + .Q(\blk00000003/blk00000004/sig00000659 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk00000309 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig00000656 ), + .Q(\blk00000003/blk00000004/sig00000657 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk00000308 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig00000654 ), + .Q(\blk00000003/blk00000004/sig00000655 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk00000307 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig00000652 ), + .Q(\blk00000003/blk00000004/sig00000653 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk00000306 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig00000650 ), + .Q(\blk00000003/blk00000004/sig00000651 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk00000305 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig0000064e ), + .Q(\blk00000003/blk00000004/sig0000064f ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk00000304 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig0000064c ), + .Q(\blk00000003/blk00000004/sig0000064d ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk00000303 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig0000064a ), + .Q(\blk00000003/blk00000004/sig0000064b ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk00000302 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig00000648 ), + .Q(\blk00000003/blk00000004/sig00000649 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk00000301 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig00000646 ), + .Q(\blk00000003/blk00000004/sig00000647 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk00000300 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig00000644 ), + .Q(\blk00000003/blk00000004/sig00000645 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk000002ff ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig00000642 ), + .Q(\blk00000003/blk00000004/sig00000643 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk000002fe ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig00000640 ), + .Q(\blk00000003/blk00000004/sig00000641 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk000002fd ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig0000063e ), + .Q(\blk00000003/blk00000004/sig0000063f ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk000002fc ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig0000063c ), + .Q(\blk00000003/blk00000004/sig0000063d ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk000002fb ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig0000063a ), + .Q(\blk00000003/blk00000004/sig0000063b ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk000002fa ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig00000638 ), + .Q(\blk00000003/blk00000004/sig00000639 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk000002f9 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig00000636 ), + .Q(\blk00000003/blk00000004/sig00000637 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk000002f8 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig00000634 ), + .Q(\blk00000003/blk00000004/sig00000635 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk000002f7 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig00000632 ), + .Q(\blk00000003/blk00000004/sig00000633 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk000002f6 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig00000630 ), + .Q(\blk00000003/blk00000004/sig00000631 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk000002f5 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig0000062e ), + .Q(\blk00000003/blk00000004/sig0000062f ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk000002f4 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig0000062c ), + .Q(\blk00000003/blk00000004/sig0000062d ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk000002f3 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig0000062a ), + .Q(\blk00000003/blk00000004/sig0000062b ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk000002f2 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig00000628 ), + .Q(\blk00000003/blk00000004/sig00000629 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk000002f1 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig00000626 ), + .Q(\blk00000003/blk00000004/sig00000627 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk000002f0 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig00000624 ), + .Q(\blk00000003/blk00000004/sig00000625 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk000002ef ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig00000622 ), + .Q(\blk00000003/blk00000004/sig00000623 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk000002ee ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig00000620 ), + .Q(\blk00000003/blk00000004/sig00000621 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk000002ed ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig0000061e ), + .Q(\blk00000003/blk00000004/sig0000061f ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk000002ec ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig0000061c ), + .Q(\blk00000003/blk00000004/sig0000061d ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk000002eb ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig0000061a ), + .Q(\blk00000003/blk00000004/sig0000061b ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk000002ea ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig00000618 ), + .Q(\blk00000003/blk00000004/sig00000619 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk000002e9 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig00000616 ), + .Q(\blk00000003/blk00000004/sig00000617 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk000002e8 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig00000614 ), + .Q(\blk00000003/blk00000004/sig00000615 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk000002e7 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig00000612 ), + .Q(\blk00000003/blk00000004/sig00000613 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk000002e6 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig00000610 ), + .Q(\blk00000003/blk00000004/sig00000611 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk000002e5 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig0000060e ), + .Q(\blk00000003/blk00000004/sig0000060f ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk000002e4 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig0000060c ), + .Q(\blk00000003/blk00000004/sig0000060d ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk000002e3 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig0000060a ), + .Q(\blk00000003/blk00000004/sig0000060b ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk000002e2 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig00000608 ), + .Q(\blk00000003/blk00000004/sig00000609 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk000002e1 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig00000606 ), + .Q(\blk00000003/blk00000004/sig00000607 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk000002e0 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig00000604 ), + .Q(\blk00000003/blk00000004/sig00000605 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk000002df ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig00000602 ), + .Q(\blk00000003/blk00000004/sig00000603 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk000002de ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig00000600 ), + .Q(\blk00000003/blk00000004/sig00000601 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk000002dd ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig000005fe ), + .Q(\blk00000003/blk00000004/sig000005ff ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk000002dc ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig000005fc ), + .Q(\blk00000003/blk00000004/sig000005fd ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk000002db ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig000005fa ), + .Q(\blk00000003/blk00000004/sig000005fb ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk000002da ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig000005f8 ), + .Q(\blk00000003/blk00000004/sig000005f9 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk000002d9 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig000005f6 ), + .Q(\blk00000003/blk00000004/sig000005f7 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk000002d8 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig000005f4 ), + .Q(\blk00000003/blk00000004/sig000005f5 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk000002d7 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig000005f2 ), + .Q(\blk00000003/blk00000004/sig000005f3 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk000002d6 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig000005f0 ), + .Q(\blk00000003/blk00000004/sig000005f1 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk000002d5 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig000005ee ), + .Q(\blk00000003/blk00000004/sig000005ef ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk000002d4 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig000005ec ), + .Q(\blk00000003/blk00000004/sig000005ed ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk000002d3 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig000005ea ), + .Q(\blk00000003/blk00000004/sig000005eb ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk000002d2 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig000005e8 ), + .Q(\blk00000003/blk00000004/sig000005e9 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk000002d1 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig000005e6 ), + .Q(\blk00000003/blk00000004/sig000005e7 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk000002d0 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig000005e4 ), + .Q(\blk00000003/blk00000004/sig000005e5 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk000002cf ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig000005e2 ), + .Q(\blk00000003/blk00000004/sig000005e3 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk000002ce ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig000005e0 ), + .Q(\blk00000003/blk00000004/sig000005e1 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk000002cd ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig000005de ), + .Q(\blk00000003/blk00000004/sig000005df ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk000002cc ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig000005dc ), + .Q(\blk00000003/blk00000004/sig000005dd ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk000002cb ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig000005da ), + .Q(\blk00000003/blk00000004/sig000005db ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk000002ca ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig000005d8 ), + .Q(\blk00000003/blk00000004/sig000005d9 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk000002c9 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig000005d6 ), + .Q(\blk00000003/blk00000004/sig000005d7 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk000002c8 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig000005d4 ), + .Q(\blk00000003/blk00000004/sig000005d5 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk000002c7 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig000005d2 ), + .Q(\blk00000003/blk00000004/sig000005d3 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk000002c6 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig000005d0 ), + .Q(\blk00000003/blk00000004/sig000005d1 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk000002c5 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig000005ce ), + .Q(\blk00000003/blk00000004/sig000005cf ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk000002c4 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig000005cc ), + .Q(\blk00000003/blk00000004/sig000005cd ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk000002c3 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig000005ca ), + .Q(\blk00000003/blk00000004/sig000005cb ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk000002c2 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig000005c8 ), + .Q(\blk00000003/blk00000004/sig000005c9 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk000002c1 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig000005c6 ), + .Q(\blk00000003/blk00000004/sig000005c7 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk000002c0 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig000005c4 ), + .Q(\blk00000003/blk00000004/sig000005c5 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk000002bf ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig000005c2 ), + .Q(\blk00000003/blk00000004/sig000005c3 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk000002be ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig000005c0 ), + .Q(\blk00000003/blk00000004/sig000005c1 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk000002bd ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig000005be ), + .Q(\blk00000003/blk00000004/sig000005bf ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk000002bc ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig000005bc ), + .Q(\blk00000003/blk00000004/sig000005bd ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk000002bb ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig000005ba ), + .Q(\blk00000003/blk00000004/sig000005bb ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk000002ba ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig000005b8 ), + .Q(\blk00000003/blk00000004/sig000005b9 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk000002b9 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig000005b6 ), + .Q(\blk00000003/blk00000004/sig000005b7 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk000002b8 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig000005b4 ), + .Q(\blk00000003/blk00000004/sig000005b5 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk000002b7 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig000005b2 ), + .Q(\blk00000003/blk00000004/sig000005b3 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk000002b6 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig000005b0 ), + .Q(\blk00000003/blk00000004/sig000005b1 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk000002b5 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig000005ae ), + .Q(\blk00000003/blk00000004/sig000005af ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk000002b4 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig000005ac ), + .Q(\blk00000003/blk00000004/sig000005ad ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk000002b3 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig000005aa ), + .Q(\blk00000003/blk00000004/sig000005ab ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk000002b2 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig000005a8 ), + .Q(\blk00000003/blk00000004/sig000005a9 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk000002b1 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig000005a6 ), + .Q(\blk00000003/blk00000004/sig000005a7 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk000002b0 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig000005a4 ), + .Q(\blk00000003/blk00000004/sig000005a5 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk000002af ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig000005a2 ), + .Q(\blk00000003/blk00000004/sig000005a3 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk000002ae ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig000005a0 ), + .Q(\blk00000003/blk00000004/sig000005a1 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk000002ad ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig0000059e ), + .Q(\blk00000003/blk00000004/sig0000059f ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk000002ac ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig0000059c ), + .Q(\blk00000003/blk00000004/sig0000059d ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk000002ab ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig0000059a ), + .Q(\blk00000003/blk00000004/sig0000059b ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk000002aa ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig00000598 ), + .Q(\blk00000003/blk00000004/sig00000599 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk000002a9 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig00000596 ), + .Q(\blk00000003/blk00000004/sig00000597 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk000002a8 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig00000594 ), + .Q(\blk00000003/blk00000004/sig00000595 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk000002a7 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig00000592 ), + .Q(\blk00000003/blk00000004/sig00000593 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk000002a6 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig00000590 ), + .Q(\blk00000003/blk00000004/sig00000591 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk000002a5 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig0000058e ), + .Q(\blk00000003/blk00000004/sig0000058f ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk000002a4 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig0000058c ), + .Q(\blk00000003/blk00000004/sig0000058d ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk000002a3 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig0000058a ), + .Q(\blk00000003/blk00000004/sig0000058b ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk000002a2 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig00000588 ), + .Q(\blk00000003/blk00000004/sig00000589 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk000002a1 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig00000586 ), + .Q(\blk00000003/blk00000004/sig00000587 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk000002a0 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig00000584 ), + .Q(\blk00000003/blk00000004/sig00000585 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk0000029f ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig00000582 ), + .Q(\blk00000003/blk00000004/sig00000583 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk0000029e ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig00000580 ), + .Q(\blk00000003/blk00000004/sig00000581 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk0000029d ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig0000057e ), + .Q(\blk00000003/blk00000004/sig0000057f ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk0000029c ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig0000057c ), + .Q(\blk00000003/blk00000004/sig0000057d ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk0000029b ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig0000057a ), + .Q(\blk00000003/blk00000004/sig0000057b ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk0000029a ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig00000578 ), + .Q(\blk00000003/blk00000004/sig00000579 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk00000299 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig00000576 ), + .Q(\blk00000003/blk00000004/sig00000577 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk00000298 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig00000574 ), + .Q(\blk00000003/blk00000004/sig00000575 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk00000297 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig00000572 ), + .Q(\blk00000003/blk00000004/sig00000573 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk00000296 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig00000570 ), + .Q(\blk00000003/blk00000004/sig00000571 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk00000295 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig0000056e ), + .Q(\blk00000003/blk00000004/sig0000056f ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk00000294 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig0000056c ), + .Q(\blk00000003/blk00000004/sig0000056d ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk00000293 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig0000056a ), + .Q(\blk00000003/blk00000004/sig0000056b ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk00000292 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig00000568 ), + .Q(\blk00000003/blk00000004/sig00000569 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk00000291 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig00000566 ), + .Q(\blk00000003/blk00000004/sig00000567 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk00000290 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig00000564 ), + .Q(\blk00000003/blk00000004/sig00000565 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk0000028f ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig00000562 ), + .Q(\blk00000003/blk00000004/sig00000563 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk0000028e ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig00000560 ), + .Q(\blk00000003/blk00000004/sig00000561 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk0000028d ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig0000055e ), + .Q(\blk00000003/blk00000004/sig0000055f ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk0000028c ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig0000055c ), + .Q(\blk00000003/blk00000004/sig0000055d ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk0000028b ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig0000055a ), + .Q(\blk00000003/blk00000004/sig0000055b ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk0000028a ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig00000558 ), + .Q(\blk00000003/blk00000004/sig00000559 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk00000289 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig00000556 ), + .Q(\blk00000003/blk00000004/sig00000557 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk00000288 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig00000554 ), + .Q(\blk00000003/blk00000004/sig00000555 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk00000287 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig00000552 ), + .Q(\blk00000003/blk00000004/sig00000553 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk00000286 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig00000550 ), + .Q(\blk00000003/blk00000004/sig00000551 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk00000285 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig0000054e ), + .Q(\blk00000003/blk00000004/sig0000054f ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk00000284 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig0000054c ), + .Q(\blk00000003/blk00000004/sig0000054d ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk00000283 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig0000054a ), + .Q(\blk00000003/blk00000004/sig0000054b ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk00000282 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig00000548 ), + .Q(\blk00000003/blk00000004/sig00000549 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk00000281 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig00000546 ), + .Q(\blk00000003/blk00000004/sig00000547 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk00000280 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig00000544 ), + .Q(\blk00000003/blk00000004/sig00000545 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk0000027f ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig00000542 ), + .Q(\blk00000003/blk00000004/sig00000543 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk0000027e ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig00000540 ), + .Q(\blk00000003/blk00000004/sig00000541 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk0000027d ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig0000053e ), + .Q(\blk00000003/blk00000004/sig0000053f ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk0000027c ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig0000053c ), + .Q(\blk00000003/blk00000004/sig0000053d ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk0000027b ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig0000053a ), + .Q(\blk00000003/blk00000004/sig0000053b ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk0000027a ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig00000538 ), + .Q(\blk00000003/blk00000004/sig00000539 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk00000279 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig00000536 ), + .Q(\blk00000003/blk00000004/sig00000537 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk00000278 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig00000534 ), + .Q(\blk00000003/blk00000004/sig00000535 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk00000277 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig00000532 ), + .Q(\blk00000003/blk00000004/sig00000533 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk00000276 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig00000530 ), + .Q(\blk00000003/blk00000004/sig00000531 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk00000275 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig0000052e ), + .Q(\blk00000003/blk00000004/sig0000052f ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk00000274 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig0000052c ), + .Q(\blk00000003/blk00000004/sig0000052d ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk00000273 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig0000052a ), + .Q(\blk00000003/blk00000004/sig0000052b ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk00000272 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig00000528 ), + .Q(\blk00000003/blk00000004/sig00000529 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk00000271 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig00000526 ), + .Q(\blk00000003/blk00000004/sig00000527 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk00000270 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig00000524 ), + .Q(\blk00000003/blk00000004/sig00000525 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk0000026f ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig00000522 ), + .Q(\blk00000003/blk00000004/sig00000523 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk0000026e ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig00000520 ), + .Q(\blk00000003/blk00000004/sig00000521 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk0000026d ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig0000051e ), + .Q(\blk00000003/blk00000004/sig0000051f ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk0000026c ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig0000051c ), + .Q(\blk00000003/blk00000004/sig0000051d ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk0000026b ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig0000051a ), + .Q(\blk00000003/blk00000004/sig0000051b ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk0000026a ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig00000518 ), + .Q(\blk00000003/blk00000004/sig00000519 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk00000269 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig00000516 ), + .Q(\blk00000003/blk00000004/sig00000517 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk00000268 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig00000514 ), + .Q(\blk00000003/blk00000004/sig00000515 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk00000267 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig00000512 ), + .Q(\blk00000003/blk00000004/sig00000513 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk00000266 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig00000510 ), + .Q(\blk00000003/blk00000004/sig00000511 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk00000265 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig0000050e ), + .Q(\blk00000003/blk00000004/sig0000050f ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk00000264 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig0000050c ), + .Q(\blk00000003/blk00000004/sig0000050d ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk00000263 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig0000050a ), + .Q(\blk00000003/blk00000004/sig0000050b ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk00000262 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig00000508 ), + .Q(\blk00000003/blk00000004/sig00000509 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk00000261 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig00000506 ), + .Q(\blk00000003/blk00000004/sig00000507 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk00000260 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig00000504 ), + .Q(\blk00000003/blk00000004/sig00000505 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk0000025f ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig00000502 ), + .Q(\blk00000003/blk00000004/sig00000503 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk0000025e ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig00000500 ), + .Q(\blk00000003/blk00000004/sig00000501 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk0000025d ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig000004fe ), + .Q(\blk00000003/blk00000004/sig000004ff ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk0000025c ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig000004fc ), + .Q(\blk00000003/blk00000004/sig000004fd ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk0000025b ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig000004fa ), + .Q(\blk00000003/blk00000004/sig000004fb ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk0000025a ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig000004f8 ), + .Q(\blk00000003/blk00000004/sig000004f9 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk00000259 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig000004f6 ), + .Q(\blk00000003/blk00000004/sig000004f7 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk00000258 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig000004f4 ), + .Q(\blk00000003/blk00000004/sig000004f5 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk00000257 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig000004f2 ), + .Q(\blk00000003/blk00000004/sig000004f3 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk00000256 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig000004f0 ), + .Q(\blk00000003/blk00000004/sig000004f1 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk00000255 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig000004ee ), + .Q(\blk00000003/blk00000004/sig000004ef ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk00000254 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig000004ec ), + .Q(\blk00000003/blk00000004/sig000004ed ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk00000253 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig000004ea ), + .Q(\blk00000003/blk00000004/sig000004eb ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk00000252 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig000004e8 ), + .Q(\blk00000003/blk00000004/sig000004e9 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk00000251 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig000004e6 ), + .Q(\blk00000003/blk00000004/sig000004e7 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk00000250 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig000004e4 ), + .Q(\blk00000003/blk00000004/sig000004e5 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk0000024f ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig000004e2 ), + .Q(\blk00000003/blk00000004/sig000004e3 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk0000024e ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig000004e0 ), + .Q(\blk00000003/blk00000004/sig000004e1 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk0000024d ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig000004de ), + .Q(\blk00000003/blk00000004/sig000004df ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk0000024c ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig000004dc ), + .Q(\blk00000003/blk00000004/sig000004dd ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk0000024b ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig000004da ), + .Q(\blk00000003/blk00000004/sig000004db ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk0000024a ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig000004d8 ), + .Q(\blk00000003/blk00000004/sig000004d9 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk00000249 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig000004d6 ), + .Q(\blk00000003/blk00000004/sig000004d7 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk00000248 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig000004d4 ), + .Q(\blk00000003/blk00000004/sig000004d5 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk00000247 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig000004d2 ), + .Q(\blk00000003/blk00000004/sig000004d3 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk00000246 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig000004d0 ), + .Q(\blk00000003/blk00000004/sig000004d1 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk00000245 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig000004ce ), + .Q(\blk00000003/blk00000004/sig000004cf ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk00000244 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig000004cc ), + .Q(\blk00000003/blk00000004/sig000004cd ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk00000243 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig000004ca ), + .Q(\blk00000003/blk00000004/sig000004cb ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk00000242 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig000004c8 ), + .Q(\blk00000003/blk00000004/sig000004c9 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk00000241 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig000004c6 ), + .Q(\blk00000003/blk00000004/sig000004c7 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk00000240 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig000004c4 ), + .Q(\blk00000003/blk00000004/sig000004c5 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk0000023f ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig000004c2 ), + .Q(\blk00000003/blk00000004/sig000004c3 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk0000023e ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig000004c0 ), + .Q(\blk00000003/blk00000004/sig000004c1 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk0000023d ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig000004be ), + .Q(\blk00000003/blk00000004/sig000004bf ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk0000023c ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig000004bc ), + .Q(\blk00000003/blk00000004/sig000004bd ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk0000023b ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig000004ba ), + .Q(\blk00000003/blk00000004/sig000004bb ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk0000023a ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig000004b8 ), + .Q(\blk00000003/blk00000004/sig000004b9 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk00000239 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig000004b6 ), + .Q(\blk00000003/blk00000004/sig000004b7 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk00000238 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig000004b4 ), + .Q(\blk00000003/blk00000004/sig000004b5 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk00000237 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig000004b2 ), + .Q(\blk00000003/blk00000004/sig000004b3 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk00000236 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig000004b0 ), + .Q(\blk00000003/blk00000004/sig000004b1 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk00000235 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig000004ae ), + .Q(\blk00000003/blk00000004/sig000004af ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk00000234 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig000004ac ), + .Q(\blk00000003/blk00000004/sig000004ad ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk00000233 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig000004aa ), + .Q(\blk00000003/blk00000004/sig000004ab ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk00000232 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig000004a8 ), + .Q(\blk00000003/blk00000004/sig000004a9 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk00000231 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig000004a6 ), + .Q(\blk00000003/blk00000004/sig000004a7 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk00000230 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig000004a4 ), + .Q(\blk00000003/blk00000004/sig000004a5 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk0000022f ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig000004a2 ), + .Q(\blk00000003/blk00000004/sig000004a3 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk0000022e ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig000004a0 ), + .Q(\blk00000003/blk00000004/sig000004a1 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk0000022d ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig0000049e ), + .Q(\blk00000003/blk00000004/sig0000049f ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk0000022c ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig0000049c ), + .Q(\blk00000003/blk00000004/sig0000049d ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk0000022b ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig0000049a ), + .Q(\blk00000003/blk00000004/sig0000049b ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk0000022a ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig00000498 ), + .Q(\blk00000003/blk00000004/sig00000499 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk00000229 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig00000496 ), + .Q(\blk00000003/blk00000004/sig00000497 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk00000228 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig00000494 ), + .Q(\blk00000003/blk00000004/sig00000495 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk00000227 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig00000492 ), + .Q(\blk00000003/blk00000004/sig00000493 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk00000226 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig00000490 ), + .Q(\blk00000003/blk00000004/sig00000491 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk00000225 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig0000048e ), + .Q(\blk00000003/blk00000004/sig0000048f ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk00000224 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig0000048c ), + .Q(\blk00000003/blk00000004/sig0000048d ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk00000223 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig0000048a ), + .Q(\blk00000003/blk00000004/sig0000048b ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk00000222 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig00000488 ), + .Q(\blk00000003/blk00000004/sig00000489 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk00000221 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig00000486 ), + .Q(\blk00000003/blk00000004/sig00000487 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk00000220 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig00000484 ), + .Q(\blk00000003/blk00000004/sig00000485 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk0000021f ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig00000482 ), + .Q(\blk00000003/blk00000004/sig00000483 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk0000021e ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig00000480 ), + .Q(\blk00000003/blk00000004/sig00000481 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk0000021d ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig0000047e ), + .Q(\blk00000003/blk00000004/sig0000047f ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk0000021c ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig0000047c ), + .Q(\blk00000003/blk00000004/sig0000047d ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk0000021b ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig0000047a ), + .Q(\blk00000003/blk00000004/sig0000047b ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk0000021a ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig00000478 ), + .Q(\blk00000003/blk00000004/sig00000479 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk00000219 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig00000476 ), + .Q(\blk00000003/blk00000004/sig00000477 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk00000218 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig00000474 ), + .Q(\blk00000003/blk00000004/sig00000475 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk00000217 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig00000472 ), + .Q(\blk00000003/blk00000004/sig00000473 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk00000216 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig00000470 ), + .Q(\blk00000003/blk00000004/sig00000471 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk00000215 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig0000046e ), + .Q(\blk00000003/blk00000004/sig0000046f ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk00000214 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig0000046c ), + .Q(\blk00000003/blk00000004/sig0000046d ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk00000213 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig0000046a ), + .Q(\blk00000003/blk00000004/sig0000046b ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk00000212 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig00000468 ), + .Q(\blk00000003/blk00000004/sig00000469 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk00000211 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig00000466 ), + .Q(\blk00000003/blk00000004/sig00000467 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk00000210 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig00000464 ), + .Q(\blk00000003/blk00000004/sig00000465 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk0000020f ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig00000462 ), + .Q(\blk00000003/blk00000004/sig00000463 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk0000020e ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig00000460 ), + .Q(\blk00000003/blk00000004/sig00000461 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk0000020d ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig0000045e ), + .Q(\blk00000003/blk00000004/sig0000045f ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk0000020c ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig0000045c ), + .Q(\blk00000003/blk00000004/sig0000045d ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk0000020b ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig0000045a ), + .Q(\blk00000003/blk00000004/sig0000045b ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk0000020a ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig00000458 ), + .Q(\blk00000003/blk00000004/sig00000459 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk00000209 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig00000456 ), + .Q(\blk00000003/blk00000004/sig00000457 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk00000208 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig00000454 ), + .Q(\blk00000003/blk00000004/sig00000455 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk00000207 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig00000452 ), + .Q(\blk00000003/blk00000004/sig00000453 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk00000206 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig00000450 ), + .Q(\blk00000003/blk00000004/sig00000451 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk00000205 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig0000044e ), + .Q(\blk00000003/blk00000004/sig0000044f ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk00000204 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig0000044c ), + .Q(\blk00000003/blk00000004/sig0000044d ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk00000203 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig0000044a ), + .Q(\blk00000003/blk00000004/sig0000044b ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk00000202 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig00000448 ), + .Q(\blk00000003/blk00000004/sig00000449 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk00000201 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig00000446 ), + .Q(\blk00000003/blk00000004/sig00000447 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk00000200 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig00000444 ), + .Q(\blk00000003/blk00000004/sig00000445 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk000001ff ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig00000442 ), + .Q(\blk00000003/blk00000004/sig00000443 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk000001fe ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig00000440 ), + .Q(\blk00000003/blk00000004/sig00000441 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk000001fd ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig0000043e ), + .Q(\blk00000003/blk00000004/sig0000043f ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk000001fc ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig0000043c ), + .Q(\blk00000003/blk00000004/sig0000043d ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk000001fb ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig0000043a ), + .Q(\blk00000003/blk00000004/sig0000043b ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk000001fa ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig00000438 ), + .Q(\blk00000003/blk00000004/sig00000439 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk000001f9 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig00000436 ), + .Q(\blk00000003/blk00000004/sig00000437 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk000001f8 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig00000434 ), + .Q(\blk00000003/blk00000004/sig00000435 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk000001f7 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig00000432 ), + .Q(\blk00000003/blk00000004/sig00000433 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk000001f6 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig00000430 ), + .Q(\blk00000003/blk00000004/sig00000431 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk000001f5 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig0000042e ), + .Q(\blk00000003/blk00000004/sig0000042f ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk000001f4 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig0000042c ), + .Q(\blk00000003/blk00000004/sig0000042d ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk000001f3 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig0000042a ), + .Q(\blk00000003/blk00000004/sig0000042b ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk000001f2 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig00000428 ), + .Q(\blk00000003/blk00000004/sig00000429 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk000001f1 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig00000426 ), + .Q(\blk00000003/blk00000004/sig00000427 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk000001f0 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig00000424 ), + .Q(\blk00000003/blk00000004/sig00000425 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk000001ef ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig00000422 ), + .Q(\blk00000003/blk00000004/sig00000423 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk000001ee ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig00000420 ), + .Q(\blk00000003/blk00000004/sig00000421 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk000001ed ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig0000041e ), + .Q(\blk00000003/blk00000004/sig0000041f ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk000001ec ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig0000041c ), + .Q(\blk00000003/blk00000004/sig0000041d ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk000001eb ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig0000041a ), + .Q(\blk00000003/blk00000004/sig0000041b ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk000001ea ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig00000418 ), + .Q(\blk00000003/blk00000004/sig00000419 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk000001e9 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig00000416 ), + .Q(\blk00000003/blk00000004/sig00000417 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk000001e8 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig00000414 ), + .Q(\blk00000003/blk00000004/sig00000415 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk000001e7 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig00000412 ), + .Q(\blk00000003/blk00000004/sig00000413 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk000001e6 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig00000410 ), + .Q(\blk00000003/blk00000004/sig00000411 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk000001e5 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig0000040e ), + .Q(\blk00000003/blk00000004/sig0000040f ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk000001e4 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig0000040c ), + .Q(\blk00000003/blk00000004/sig0000040d ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk000001e3 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig0000040a ), + .Q(\blk00000003/blk00000004/sig0000040b ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk000001e2 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig00000408 ), + .Q(\blk00000003/blk00000004/sig00000409 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk000001e1 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig00000406 ), + .Q(\blk00000003/blk00000004/sig00000407 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk000001e0 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig00000404 ), + .Q(\blk00000003/blk00000004/sig00000405 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk000001df ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig00000402 ), + .Q(\blk00000003/blk00000004/sig00000403 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk000001de ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig00000400 ), + .Q(\blk00000003/blk00000004/sig00000401 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk000001dd ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig000003fe ), + .Q(\blk00000003/blk00000004/sig000003ff ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk000001dc ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig000003fc ), + .Q(\blk00000003/blk00000004/sig000003fd ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk000001db ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig000003fa ), + .Q(\blk00000003/blk00000004/sig000003fb ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk000001da ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig000003f8 ), + .Q(\blk00000003/blk00000004/sig000003f9 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk000001d9 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig000003f6 ), + .Q(\blk00000003/blk00000004/sig000003f7 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk000001d8 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig000003f4 ), + .Q(\blk00000003/blk00000004/sig000003f5 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk000001d7 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig000003f2 ), + .Q(\blk00000003/blk00000004/sig000003f3 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk000001d6 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig000003f0 ), + .Q(\blk00000003/blk00000004/sig000003f1 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk000001d5 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig000003ee ), + .Q(\blk00000003/blk00000004/sig000003ef ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk000001d4 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig000003ec ), + .Q(\blk00000003/blk00000004/sig000003ed ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk000001d3 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig000003ea ), + .Q(\blk00000003/blk00000004/sig000003eb ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk000001d2 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig000003e8 ), + .Q(\blk00000003/blk00000004/sig000003e9 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk000001d1 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig000003e6 ), + .Q(\blk00000003/blk00000004/sig000003e7 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk000001d0 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig000003e4 ), + .Q(\blk00000003/blk00000004/sig000003e5 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk000001cf ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig000003e2 ), + .Q(\blk00000003/blk00000004/sig000003e3 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk000001ce ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig000003e0 ), + .Q(\blk00000003/blk00000004/sig000003e1 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk000001cd ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig000003de ), + .Q(\blk00000003/blk00000004/sig000003df ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk000001cc ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig000003dc ), + .Q(\blk00000003/blk00000004/sig000003dd ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk000001cb ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig000003da ), + .Q(\blk00000003/blk00000004/sig000003db ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk000001ca ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig000003d8 ), + .Q(\blk00000003/blk00000004/sig000003d9 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk000001c9 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig000003d6 ), + .Q(\blk00000003/blk00000004/sig000003d7 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk000001c8 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig000003d4 ), + .Q(\blk00000003/blk00000004/sig000003d5 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk000001c7 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig000003d2 ), + .Q(\blk00000003/blk00000004/sig000003d3 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk000001c6 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig000003d0 ), + .Q(\blk00000003/blk00000004/sig000003d1 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk000001c5 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig000003ce ), + .Q(\blk00000003/blk00000004/sig000003cf ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk000001c4 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig000003cc ), + .Q(\blk00000003/blk00000004/sig000003cd ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk000001c3 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig000003ca ), + .Q(\blk00000003/blk00000004/sig000003cb ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk000001c2 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig000003c8 ), + .Q(\blk00000003/blk00000004/sig000003c9 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk000001c1 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig000003c6 ), + .Q(\blk00000003/blk00000004/sig000003c7 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk000001c0 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig000003c4 ), + .Q(\blk00000003/blk00000004/sig000003c5 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk000001bf ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig000003c2 ), + .Q(\blk00000003/blk00000004/sig000003c3 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk000001be ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig000003c0 ), + .Q(\blk00000003/blk00000004/sig000003c1 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk000001bd ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig000003be ), + .Q(\blk00000003/blk00000004/sig000003bf ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk000001bc ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig000003bc ), + .Q(\blk00000003/blk00000004/sig000003bd ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk000001bb ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig000003ba ), + .Q(\blk00000003/blk00000004/sig000003bb ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk000001ba ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig000003b8 ), + .Q(\blk00000003/blk00000004/sig000003b9 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk000001b9 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig000003b6 ), + .Q(\blk00000003/blk00000004/sig000003b7 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk000001b8 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig000003b4 ), + .Q(\blk00000003/blk00000004/sig000003b5 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk000001b7 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig000003b2 ), + .Q(\blk00000003/blk00000004/sig000003b3 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk000001b6 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig000003b0 ), + .Q(\blk00000003/blk00000004/sig000003b1 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk000001b5 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig000003ae ), + .Q(\blk00000003/blk00000004/sig000003af ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk000001b4 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig000003ac ), + .Q(\blk00000003/blk00000004/sig000003ad ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk000001b3 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig000003aa ), + .Q(\blk00000003/blk00000004/sig000003ab ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk000001b2 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig000003a8 ), + .Q(\blk00000003/blk00000004/sig000003a9 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk000001b1 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig000003a6 ), + .Q(\blk00000003/blk00000004/sig000003a7 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk000001b0 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig000003a4 ), + .Q(\blk00000003/blk00000004/sig000003a5 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk000001af ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig000003a2 ), + .Q(\blk00000003/blk00000004/sig000003a3 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk000001ae ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig000003a0 ), + .Q(\blk00000003/blk00000004/sig000003a1 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk000001ad ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig0000039e ), + .Q(\blk00000003/blk00000004/sig0000039f ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk000001ac ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig0000039c ), + .Q(\blk00000003/blk00000004/sig0000039d ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk000001ab ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig0000039a ), + .Q(\blk00000003/blk00000004/sig0000039b ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk000001aa ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig00000398 ), + .Q(\blk00000003/blk00000004/sig00000399 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk000001a9 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig00000396 ), + .Q(\blk00000003/blk00000004/sig00000397 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk000001a8 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig00000394 ), + .Q(\blk00000003/blk00000004/sig00000395 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk000001a7 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig00000392 ), + .Q(\blk00000003/blk00000004/sig00000393 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk000001a6 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig00000390 ), + .Q(\blk00000003/blk00000004/sig00000391 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk000001a5 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig0000038e ), + .Q(\blk00000003/blk00000004/sig0000038f ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk000001a4 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig0000038c ), + .Q(\blk00000003/blk00000004/sig0000038d ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk000001a3 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig0000038a ), + .Q(\blk00000003/blk00000004/sig0000038b ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk000001a2 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig00000388 ), + .Q(\blk00000003/blk00000004/sig00000389 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk000001a1 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig00000386 ), + .Q(\blk00000003/blk00000004/sig00000387 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk000001a0 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig00000384 ), + .Q(\blk00000003/blk00000004/sig00000385 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk0000019f ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig00000382 ), + .Q(\blk00000003/blk00000004/sig00000383 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk0000019e ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig00000380 ), + .Q(\blk00000003/blk00000004/sig00000381 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk0000019d ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig0000037e ), + .Q(\blk00000003/blk00000004/sig0000037f ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk0000019c ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig0000037c ), + .Q(\blk00000003/blk00000004/sig0000037d ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk0000019b ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig0000037a ), + .Q(\blk00000003/blk00000004/sig0000037b ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk0000019a ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig00000378 ), + .Q(\blk00000003/blk00000004/sig00000379 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk00000199 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig00000376 ), + .Q(\blk00000003/blk00000004/sig00000377 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk00000198 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig00000374 ), + .Q(\blk00000003/blk00000004/sig00000375 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk00000197 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig00000372 ), + .Q(\blk00000003/blk00000004/sig00000373 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk00000196 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig00000370 ), + .Q(\blk00000003/blk00000004/sig00000371 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk00000195 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig0000036e ), + .Q(\blk00000003/blk00000004/sig0000036f ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk00000194 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig0000036c ), + .Q(\blk00000003/blk00000004/sig0000036d ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk00000193 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig0000036a ), + .Q(\blk00000003/blk00000004/sig0000036b ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk00000192 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig00000368 ), + .Q(\blk00000003/blk00000004/sig00000369 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk00000191 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig00000366 ), + .Q(\blk00000003/blk00000004/sig00000367 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk00000190 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig00000364 ), + .Q(\blk00000003/blk00000004/sig00000365 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk0000018f ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig00000362 ), + .Q(\blk00000003/blk00000004/sig00000363 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk0000018e ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig00000360 ), + .Q(\blk00000003/blk00000004/sig00000361 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk0000018d ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig0000035e ), + .Q(\blk00000003/blk00000004/sig0000035f ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk0000018c ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig0000035c ), + .Q(\blk00000003/blk00000004/sig0000035d ) + ); + MUXCY \blk00000003/blk00000004/blk0000018b ( + .CI(\blk00000003/sig00000001 ), + .DI(\blk00000003/blk00000004/sig000002f2 ), + .S(\blk00000003/blk00000004/sig0000035b ), + .O(\blk00000003/blk00000004/sig00000359 ) + ); + XORCY \blk00000003/blk00000004/blk0000018a ( + .CI(\blk00000003/sig00000001 ), + .LI(\blk00000003/blk00000004/sig0000035b ), + .O(\blk00000003/blk00000004/sig00000354 ) + ); + XORCY \blk00000003/blk00000004/blk00000189 ( + .CI(\blk00000003/blk00000004/sig00000358 ), + .LI(\blk00000003/sig00000001 ), + .O(\blk00000003/blk00000004/sig0000034e ) + ); + MUXCY \blk00000003/blk00000004/blk00000188 ( + .CI(\blk00000003/blk00000004/sig00000359 ), + .DI(\blk00000003/blk00000004/sig000002f4 ), + .S(\blk00000003/blk00000004/sig0000035a ), + .O(\blk00000003/blk00000004/sig00000356 ) + ); + XORCY \blk00000003/blk00000004/blk00000187 ( + .CI(\blk00000003/blk00000004/sig00000359 ), + .LI(\blk00000003/blk00000004/sig0000035a ), + .O(\blk00000003/blk00000004/sig00000352 ) + ); + MUXCY \blk00000003/blk00000004/blk00000186 ( + .CI(\blk00000003/blk00000004/sig00000356 ), + .DI(\blk00000003/blk00000004/sig000002f6 ), + .S(\blk00000003/blk00000004/sig00000357 ), + .O(\blk00000003/blk00000004/sig00000358 ) + ); + XORCY \blk00000003/blk00000004/blk00000185 ( + .CI(\blk00000003/blk00000004/sig00000356 ), + .LI(\blk00000003/blk00000004/sig00000357 ), + .O(\blk00000003/blk00000004/sig00000350 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk00000184 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig00000354 ), + .R(sclr), + .Q(\blk00000003/blk00000004/sig00000355 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk00000183 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig00000352 ), + .R(sclr), + .Q(\blk00000003/blk00000004/sig00000353 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk00000182 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig00000350 ), + .R(sclr), + .Q(\blk00000003/blk00000004/sig00000351 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk00000181 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig0000034e ), + .R(sclr), + .Q(\blk00000003/blk00000004/sig0000034f ) + ); + MUXCY \blk00000003/blk00000004/blk00000180 ( + .CI(\blk00000003/sig00000001 ), + .DI(\blk00000003/blk00000004/sig000002f8 ), + .S(\blk00000003/blk00000004/sig0000034d ), + .O(\blk00000003/blk00000004/sig0000034b ) + ); + XORCY \blk00000003/blk00000004/blk0000017f ( + .CI(\blk00000003/sig00000001 ), + .LI(\blk00000003/blk00000004/sig0000034d ), + .O(\blk00000003/blk00000004/sig00000346 ) + ); + XORCY \blk00000003/blk00000004/blk0000017e ( + .CI(\blk00000003/blk00000004/sig0000034a ), + .LI(\blk00000003/sig00000001 ), + .O(\blk00000003/blk00000004/sig00000340 ) + ); + MUXCY \blk00000003/blk00000004/blk0000017d ( + .CI(\blk00000003/blk00000004/sig0000034b ), + .DI(\blk00000003/blk00000004/sig000002fa ), + .S(\blk00000003/blk00000004/sig0000034c ), + .O(\blk00000003/blk00000004/sig00000348 ) + ); + XORCY \blk00000003/blk00000004/blk0000017c ( + .CI(\blk00000003/blk00000004/sig0000034b ), + .LI(\blk00000003/blk00000004/sig0000034c ), + .O(\blk00000003/blk00000004/sig00000344 ) + ); + MUXCY \blk00000003/blk00000004/blk0000017b ( + .CI(\blk00000003/blk00000004/sig00000348 ), + .DI(\blk00000003/blk00000004/sig000002fc ), + .S(\blk00000003/blk00000004/sig00000349 ), + .O(\blk00000003/blk00000004/sig0000034a ) + ); + XORCY \blk00000003/blk00000004/blk0000017a ( + .CI(\blk00000003/blk00000004/sig00000348 ), + .LI(\blk00000003/blk00000004/sig00000349 ), + .O(\blk00000003/blk00000004/sig00000342 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk00000179 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig00000346 ), + .R(sclr), + .Q(\blk00000003/blk00000004/sig00000347 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk00000178 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig00000344 ), + .R(sclr), + .Q(\blk00000003/blk00000004/sig00000345 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk00000177 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig00000342 ), + .R(sclr), + .Q(\blk00000003/blk00000004/sig00000343 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk00000176 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig00000340 ), + .R(sclr), + .Q(\blk00000003/blk00000004/sig00000341 ) + ); + MUXCY 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); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk0000016b ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig00000332 ), + .R(sclr), + .Q(\blk00000003/blk00000004/sig00000333 ) + ); + MUXCY \blk00000003/blk00000004/blk0000016a ( + .CI(\blk00000003/sig00000001 ), + .DI(\blk00000003/blk00000004/sig00000331 ), + .S(\blk00000003/blk00000004/sig00000330 ), + .O(\blk00000003/blk00000004/sig0000032d ) + ); + XORCY \blk00000003/blk00000004/blk00000169 ( + .CI(\blk00000003/sig00000001 ), + .LI(\blk00000003/blk00000004/sig00000330 ), + .O(\blk00000003/blk00000004/sig00000327 ) + ); + XORCY \blk00000003/blk00000004/blk00000168 ( + .CI(\blk00000003/blk00000004/sig0000032c ), + .LI(\blk00000003/sig00000001 ), + .O(\blk00000003/blk00000004/sig00000321 ) + ); + MUXCY \blk00000003/blk00000004/blk00000167 ( + .CI(\blk00000003/blk00000004/sig0000032d ), + .DI(\blk00000003/blk00000004/sig0000032f ), + .S(\blk00000003/blk00000004/sig0000032e ), + .O(\blk00000003/blk00000004/sig00000329 ) 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) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk00000161 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig00000323 ), + .R(sclr), + .Q(\blk00000003/blk00000004/sig00000324 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk00000160 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig00000321 ), + .R(sclr), + .Q(\blk00000003/blk00000004/sig00000322 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk0000015f ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig0000031f ), + .Q(\blk00000003/blk00000004/sig00000320 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk0000015e ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig0000031d ), + .Q(\blk00000003/blk00000004/sig0000031e ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk0000015d ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig0000031b ), + .Q(\blk00000003/blk00000004/sig0000031c ) + ); + FDE #( + .INIT ( 1'b0 )) + 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.Q(\blk00000003/blk00000004/sig00000306 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk00000151 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig00000303 ), + .Q(\blk00000003/blk00000004/sig00000304 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk00000150 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig00000301 ), + .Q(\blk00000003/blk00000004/sig00000302 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk0000014f ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig000002ff ), + .Q(\blk00000003/blk00000004/sig00000300 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk0000014e ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig000002fd ), + .Q(\blk00000003/blk00000004/sig000002fe ) + ); + FDE \blk00000003/blk00000004/blk0000014d ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig000002fb ), + .Q(\blk00000003/blk00000004/sig000002fc ) + ); + FDE \blk00000003/blk00000004/blk0000014c ( + .C(clk), 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.O(\blk00000003/blk00000004/sig000002e5 ) + ); + XORCY \blk00000003/blk00000004/blk00000141 ( + .CI(\blk00000003/sig00000001 ), + .LI(\blk00000003/blk00000004/sig000002e8 ), + .O(\blk00000003/blk00000004/sig000002e0 ) + ); + XORCY \blk00000003/blk00000004/blk00000140 ( + .CI(\blk00000003/blk00000004/sig000002e4 ), + .LI(\blk00000003/blk00000004/sig000002e7 ), + .O(\blk00000003/blk00000004/sig000002d9 ) + ); + MUXCY \blk00000003/blk00000004/blk0000013f ( + .CI(\blk00000003/blk00000004/sig000002e5 ), + .DI(\blk00000003/sig00000001 ), + .S(\blk00000003/blk00000004/sig000002e6 ), + .O(\blk00000003/blk00000004/sig000002e2 ) + ); + XORCY \blk00000003/blk00000004/blk0000013e ( + .CI(\blk00000003/blk00000004/sig000002e5 ), + .LI(\blk00000003/blk00000004/sig000002e6 ), + .O(\blk00000003/blk00000004/sig000002de ) + ); + MUXCY \blk00000003/blk00000004/blk0000013d ( + .CI(\blk00000003/blk00000004/sig000002e2 ), + .DI(\blk00000003/sig00000001 ), + .S(\blk00000003/blk00000004/sig000002e3 ), + .O(\blk00000003/blk00000004/sig000002e4 ) + ); + XORCY \blk00000003/blk00000004/blk0000013c ( + .CI(\blk00000003/blk00000004/sig000002e2 ), + .LI(\blk00000003/blk00000004/sig000002e3 ), + .O(\blk00000003/blk00000004/sig000002dc ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk0000013b ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig000002e0 ), + .R(\blk00000003/blk00000004/sig000002da ), + .Q(\blk00000003/blk00000004/sig000002e1 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk0000013a ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig000002de ), + .R(\blk00000003/blk00000004/sig000002da ), + .Q(\blk00000003/blk00000004/sig000002df ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk00000139 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig000002dc ), + .R(\blk00000003/blk00000004/sig000002da ), + .Q(\blk00000003/blk00000004/sig000002dd ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk00000138 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig000002d9 ), + .R(\blk00000003/blk00000004/sig000002da ), + .Q(\blk00000003/blk00000004/sig000002db ) + ); + MUXCY \blk00000003/blk00000004/blk00000137 ( + .CI(\blk00000003/sig00000001 ), + .DI(\blk00000003/blk00000004/sig00000093 ), + .S(\blk00000003/blk00000004/sig000002d8 ), + .O(\blk00000003/blk00000004/sig000002d5 ) + ); + XORCY \blk00000003/blk00000004/blk00000136 ( + .CI(\blk00000003/sig00000001 ), + .LI(\blk00000003/blk00000004/sig000002d8 ), + .O(\blk00000003/blk00000004/sig000002d0 ) + ); + XORCY \blk00000003/blk00000004/blk00000135 ( + .CI(\blk00000003/blk00000004/sig000002d4 ), + .LI(\blk00000003/blk00000004/sig000002d7 ), + .O(\blk00000003/blk00000004/sig000002c9 ) + ); + MUXCY \blk00000003/blk00000004/blk00000134 ( + .CI(\blk00000003/blk00000004/sig000002d5 ), + .DI(\blk00000003/sig00000001 ), + .S(\blk00000003/blk00000004/sig000002d6 ), + .O(\blk00000003/blk00000004/sig000002d2 ) + ); + XORCY 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.LI(\blk00000003/blk00000004/sig000002c7 ), + .O(\blk00000003/blk00000004/sig000002b1 ) + ); + MUXCY \blk00000003/blk00000004/blk00000129 ( + .CI(\blk00000003/blk00000004/sig000002c5 ), + .DI(\blk00000003/sig00000001 ), + .S(\blk00000003/blk00000004/sig000002c6 ), + .O(\blk00000003/blk00000004/sig000002c3 ) + ); + XORCY \blk00000003/blk00000004/blk00000128 ( + .CI(\blk00000003/blk00000004/sig000002c5 ), + .LI(\blk00000003/blk00000004/sig000002c6 ), + .O(\blk00000003/blk00000004/sig000002ba ) + ); + MUXCY \blk00000003/blk00000004/blk00000127 ( + .CI(\blk00000003/blk00000004/sig000002c3 ), + .DI(\blk00000003/sig00000001 ), + .S(\blk00000003/blk00000004/sig000002c4 ), + .O(\blk00000003/blk00000004/sig000002c1 ) + ); + XORCY \blk00000003/blk00000004/blk00000126 ( + .CI(\blk00000003/blk00000004/sig000002c3 ), + .LI(\blk00000003/blk00000004/sig000002c4 ), + .O(\blk00000003/blk00000004/sig000002b8 ) + ); + MUXCY \blk00000003/blk00000004/blk00000125 ( + .CI(\blk00000003/blk00000004/sig000002c1 ), + .DI(\blk00000003/sig00000001 ), + .S(\blk00000003/blk00000004/sig000002c2 ), + .O(\blk00000003/blk00000004/sig000002be ) + ); + XORCY \blk00000003/blk00000004/blk00000124 ( + .CI(\blk00000003/blk00000004/sig000002c1 ), + .LI(\blk00000003/blk00000004/sig000002c2 ), + .O(\blk00000003/blk00000004/sig000002b6 ) + ); + MUXCY \blk00000003/blk00000004/blk00000123 ( + .CI(\blk00000003/blk00000004/sig000002be ), + .DI(\blk00000003/sig00000001 ), + .S(\blk00000003/blk00000004/sig000002bf ), + .O(\blk00000003/blk00000004/sig000002c0 ) + ); + XORCY \blk00000003/blk00000004/blk00000122 ( + .CI(\blk00000003/blk00000004/sig000002be ), + .LI(\blk00000003/blk00000004/sig000002bf ), + .O(\blk00000003/blk00000004/sig000002b4 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk00000121 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig000002bc ), + .R(\blk00000003/blk00000004/sig000002b2 ), + .Q(\blk00000003/blk00000004/sig000002bd ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk00000120 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig000002ba ), + .R(\blk00000003/blk00000004/sig000002b2 ), + .Q(\blk00000003/blk00000004/sig000002bb ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk0000011f ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig000002b8 ), + .R(\blk00000003/blk00000004/sig000002b2 ), + .Q(\blk00000003/blk00000004/sig000002b9 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk0000011e ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig000002b6 ), + .R(\blk00000003/blk00000004/sig000002b2 ), + .Q(\blk00000003/blk00000004/sig000002b7 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk0000011d ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig000002b4 ), + .R(\blk00000003/blk00000004/sig000002b2 ), + .Q(\blk00000003/blk00000004/sig000002b5 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk0000011c ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig000002b1 ), + .R(\blk00000003/blk00000004/sig000002b2 ), + .Q(\blk00000003/blk00000004/sig000002b3 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk0000011b ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig000002af ), + .Q(\blk00000003/blk00000004/sig000002b0 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk0000011a ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig000002ae ), + .Q(\blk00000003/blk00000004/sig000001af ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk00000119 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig000002ad ), + .Q(\blk00000003/blk00000004/sig000001b3 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk00000118 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig000002ac ), + .Q(\blk00000003/blk00000004/sig000001b2 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk00000117 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig000002aa ), + .Q(\blk00000003/blk00000004/sig000002ab ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk00000116 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig000002a8 ), + .Q(\blk00000003/blk00000004/sig000002a9 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk00000115 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig000002a6 ), + .Q(\blk00000003/blk00000004/sig000002a7 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk00000114 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig000002a4 ), + .Q(\blk00000003/blk00000004/sig000002a5 ) + ); + MUXF8 \blk00000003/blk00000004/blk00000113 ( + .I0(\blk00000003/blk00000004/sig000002a2 ), + .I1(\blk00000003/blk00000004/sig0000029f ), + .S(\blk00000003/blk00000004/sig0000029b ), + .O(\blk00000003/blk00000004/sig000002a3 ) + ); + MUXF7 \blk00000003/blk00000004/blk00000112 ( + .I0(\blk00000003/blk00000004/sig000002a0 ), + .I1(\blk00000003/blk00000004/sig000002a1 ), + .S(\blk00000003/blk00000004/sig0000028c ), + .O(\blk00000003/blk00000004/sig000002a2 ) + ); + MUXF7 \blk00000003/blk00000004/blk00000111 ( + .I0(\blk00000003/blk00000004/sig0000029d ), + .I1(\blk00000003/blk00000004/sig0000029e ), + .S(\blk00000003/blk00000004/sig0000028c ), + .O(\blk00000003/blk00000004/sig0000029f ) + ); + MUXF8 \blk00000003/blk00000004/blk00000110 ( + .I0(\blk00000003/blk00000004/sig0000029a ), + .I1(\blk00000003/blk00000004/sig00000297 ), + .S(\blk00000003/blk00000004/sig0000029b ), + .O(\blk00000003/blk00000004/sig0000029c ) + ); + MUXF7 \blk00000003/blk00000004/blk0000010f ( + .I0(\blk00000003/blk00000004/sig00000298 ), + .I1(\blk00000003/blk00000004/sig00000299 ), + .S(\blk00000003/blk00000004/sig0000028c ), + .O(\blk00000003/blk00000004/sig0000029a ) + ); + MUXF7 \blk00000003/blk00000004/blk0000010e ( + .I0(\blk00000003/blk00000004/sig00000295 ), + .I1(\blk00000003/blk00000004/sig00000296 ), + .S(\blk00000003/blk00000004/sig0000028c ), + .O(\blk00000003/blk00000004/sig00000297 ) + ); + MUXF8 \blk00000003/blk00000004/blk0000010d ( + .I0(\blk00000003/blk00000004/sig00000293 ), + .I1(\blk00000003/blk00000004/sig00000290 ), + .S(\blk00000003/blk00000004/sig0000028c ), + .O(\blk00000003/blk00000004/sig00000294 ) + ); + MUXF7 \blk00000003/blk00000004/blk0000010c ( + .I0(\blk00000003/blk00000004/sig00000291 ), + .I1(\blk00000003/blk00000004/sig00000292 ), + .S(\blk00000003/blk00000004/sig0000027d ), + .O(\blk00000003/blk00000004/sig00000293 ) + ); + MUXF7 \blk00000003/blk00000004/blk0000010b ( + .I0(\blk00000003/blk00000004/sig0000028e ), + .I1(\blk00000003/blk00000004/sig0000028f ), + .S(\blk00000003/blk00000004/sig0000027d ), + .O(\blk00000003/blk00000004/sig00000290 ) + ); + MUXF8 \blk00000003/blk00000004/blk0000010a ( + .I0(\blk00000003/blk00000004/sig0000028b ), + .I1(\blk00000003/blk00000004/sig00000288 ), + .S(\blk00000003/blk00000004/sig0000028c ), + .O(\blk00000003/blk00000004/sig0000028d ) + ); + MUXF7 \blk00000003/blk00000004/blk00000109 ( + .I0(\blk00000003/blk00000004/sig00000289 ), + .I1(\blk00000003/blk00000004/sig0000028a ), + .S(\blk00000003/blk00000004/sig0000027d ), + .O(\blk00000003/blk00000004/sig0000028b ) + ); + MUXF7 \blk00000003/blk00000004/blk00000108 ( + .I0(\blk00000003/blk00000004/sig00000286 ), + .I1(\blk00000003/blk00000004/sig00000287 ), + .S(\blk00000003/blk00000004/sig0000027d ), + .O(\blk00000003/blk00000004/sig00000288 ) + ); + MUXF8 \blk00000003/blk00000004/blk00000107 ( + .I0(\blk00000003/blk00000004/sig00000284 ), + .I1(\blk00000003/blk00000004/sig00000281 ), + .S(\blk00000003/blk00000004/sig0000027d ), + .O(\blk00000003/blk00000004/sig00000285 ) + ); + MUXF7 \blk00000003/blk00000004/blk00000106 ( + .I0(\blk00000003/blk00000004/sig00000282 ), + .I1(\blk00000003/blk00000004/sig00000283 ), + .S(\blk00000003/blk00000004/sig00000278 ), + .O(\blk00000003/blk00000004/sig00000284 ) + ); + MUXF7 \blk00000003/blk00000004/blk00000105 ( + .I0(\blk00000003/blk00000004/sig0000027f ), + .I1(\blk00000003/blk00000004/sig00000280 ), + .S(\blk00000003/blk00000004/sig00000278 ), + .O(\blk00000003/blk00000004/sig00000281 ) + ); + MUXF8 \blk00000003/blk00000004/blk00000104 ( + .I0(\blk00000003/blk00000004/sig0000027c ), + .I1(\blk00000003/blk00000004/sig00000279 ), + .S(\blk00000003/blk00000004/sig0000027d ), + .O(\blk00000003/blk00000004/sig0000027e ) + ); + MUXF7 \blk00000003/blk00000004/blk00000103 ( + .I0(\blk00000003/blk00000004/sig0000027a ), + .I1(\blk00000003/blk00000004/sig0000027b ), + .S(\blk00000003/blk00000004/sig00000278 ), + .O(\blk00000003/blk00000004/sig0000027c ) + ); + MUXF7 \blk00000003/blk00000004/blk00000102 ( + .I0(\blk00000003/blk00000004/sig00000276 ), + .I1(\blk00000003/blk00000004/sig00000277 ), + .S(\blk00000003/blk00000004/sig00000278 ), + .O(\blk00000003/blk00000004/sig00000279 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk00000101 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig00000274 ), + .Q(\blk00000003/blk00000004/sig00000275 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk00000100 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig00000272 ), + .Q(\blk00000003/blk00000004/sig00000273 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk000000ff ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig00000270 ), + .Q(\blk00000003/blk00000004/sig00000271 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk000000fe ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig0000026e ), + .Q(\blk00000003/blk00000004/sig0000026f ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk000000fd ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig0000026c ), + .Q(\blk00000003/blk00000004/sig0000026d ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk000000fc ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig0000026a ), + .Q(\blk00000003/blk00000004/sig0000026b ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk000000fb ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig00000268 ), + .Q(\blk00000003/blk00000004/sig00000269 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk000000fa ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig00000266 ), + .Q(\blk00000003/blk00000004/sig00000267 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk000000f9 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig00000264 ), + .Q(\blk00000003/blk00000004/sig00000265 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk000000f8 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig00000262 ), + .Q(\blk00000003/blk00000004/sig00000263 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk000000f7 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig00000260 ), + .Q(\blk00000003/blk00000004/sig00000261 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk000000f6 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig0000025e ), + .Q(\blk00000003/blk00000004/sig0000025f ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk000000f5 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig0000025c ), + .Q(\blk00000003/blk00000004/sig0000025d ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk000000f4 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig0000025a ), + .Q(\blk00000003/blk00000004/sig0000025b ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk000000f3 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig00000258 ), + .Q(\blk00000003/blk00000004/sig00000259 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk000000f2 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig00000256 ), + .Q(\blk00000003/blk00000004/sig00000257 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk000000f1 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig00000254 ), + .Q(\blk00000003/blk00000004/sig00000255 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk000000f0 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig00000252 ), + .Q(\blk00000003/blk00000004/sig00000253 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk000000ef ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig00000250 ), + .Q(\blk00000003/blk00000004/sig00000251 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk000000ee ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig0000024e ), + .Q(\blk00000003/blk00000004/sig0000024f ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk000000ed ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig0000024c ), + .Q(\blk00000003/blk00000004/sig0000024d ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk000000ec ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig0000024a ), + .Q(\blk00000003/blk00000004/sig0000024b ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk000000eb ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig00000248 ), + .Q(\blk00000003/blk00000004/sig00000249 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk000000ea ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig00000246 ), + .Q(\blk00000003/blk00000004/sig00000247 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk000000e9 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig00000244 ), + .Q(\blk00000003/blk00000004/sig00000245 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk000000e8 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig00000242 ), + .Q(\blk00000003/blk00000004/sig00000243 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk000000e7 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig00000240 ), + .Q(\blk00000003/blk00000004/sig00000241 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk000000e6 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig0000023e ), + .Q(\blk00000003/blk00000004/sig0000023f ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk000000e5 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig0000023c ), + .Q(\blk00000003/blk00000004/sig0000023d ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk000000e4 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig0000023a ), + .Q(\blk00000003/blk00000004/sig0000023b ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk000000e3 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig00000238 ), + .Q(\blk00000003/blk00000004/sig00000239 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk000000e2 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig00000236 ), + .Q(\blk00000003/blk00000004/sig00000237 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk000000e1 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig00000234 ), + .Q(\blk00000003/blk00000004/sig00000235 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk000000e0 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig00000232 ), + .Q(\blk00000003/blk00000004/sig00000233 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk000000df ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig00000230 ), + .Q(\blk00000003/blk00000004/sig00000231 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk000000de ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig0000022e ), + .Q(\blk00000003/blk00000004/sig0000022f ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk000000dd ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig0000022c ), + .Q(\blk00000003/blk00000004/sig0000022d ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk000000dc ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig0000022a ), + .Q(\blk00000003/blk00000004/sig0000022b ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk000000db ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig00000228 ), + .Q(\blk00000003/blk00000004/sig00000229 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk000000da ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig00000226 ), + .Q(\blk00000003/blk00000004/sig00000227 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk000000d9 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig00000224 ), + .Q(\blk00000003/blk00000004/sig00000225 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk000000d8 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig00000222 ), + .Q(\blk00000003/blk00000004/sig00000223 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk000000d7 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig00000220 ), + .Q(\blk00000003/blk00000004/sig00000221 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk000000d6 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig0000021e ), + .Q(\blk00000003/blk00000004/sig0000021f ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk000000d5 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig0000021c ), + .Q(\blk00000003/blk00000004/sig0000021d ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk000000d4 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig0000021a ), + .Q(\blk00000003/blk00000004/sig0000021b ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk000000d3 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig00000218 ), + .Q(\blk00000003/blk00000004/sig00000219 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk000000d2 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig00000216 ), + .Q(\blk00000003/blk00000004/sig00000217 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk000000d1 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig00000214 ), + .Q(\blk00000003/blk00000004/sig00000215 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk000000d0 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig00000212 ), + .Q(\blk00000003/blk00000004/sig00000213 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk000000cf ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig00000210 ), + .Q(\blk00000003/blk00000004/sig00000211 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk000000ce ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig0000020e ), + .Q(\blk00000003/blk00000004/sig0000020f ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk000000cd ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig0000020c ), + .Q(\blk00000003/blk00000004/sig0000020d ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk000000cc ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig0000020a ), + .Q(\blk00000003/blk00000004/sig0000020b ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk000000cb ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig00000208 ), + .Q(\blk00000003/blk00000004/sig00000209 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk000000ca ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig00000206 ), + .Q(\blk00000003/blk00000004/sig00000207 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk000000c9 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig00000204 ), + .Q(\blk00000003/blk00000004/sig00000205 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk000000c8 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig00000202 ), + .Q(\blk00000003/blk00000004/sig00000203 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk000000c7 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig00000200 ), + .Q(\blk00000003/blk00000004/sig00000201 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk000000c6 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig000001fe ), + .Q(\blk00000003/blk00000004/sig000001ff ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk000000c5 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig000001fc ), + .Q(\blk00000003/blk00000004/sig000001fd ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk000000c4 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig000001fa ), + .Q(\blk00000003/blk00000004/sig000001fb ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk000000c3 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig000001f8 ), + .Q(\blk00000003/blk00000004/sig000001f9 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk000000c2 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig000001f6 ), + .Q(\blk00000003/blk00000004/sig000001f7 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk000000c1 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig000001f4 ), + .Q(\blk00000003/blk00000004/sig000001f5 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk000000c0 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig000001f2 ), + .Q(\blk00000003/blk00000004/sig000001f3 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk000000bf ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig000001f0 ), + .Q(\blk00000003/blk00000004/sig000001f1 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk000000be ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig000001ee ), + .Q(\blk00000003/blk00000004/sig000001ef ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk000000bd ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig000001ec ), + .Q(\blk00000003/blk00000004/sig000001ed ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk000000bc ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig000001ea ), + .Q(\blk00000003/blk00000004/sig000001eb ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk000000bb ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig000001e8 ), + .Q(\blk00000003/blk00000004/sig000001e9 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk000000ba ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig000001e6 ), + .Q(\blk00000003/blk00000004/sig000001e7 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk000000b9 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig000001e4 ), + .Q(\blk00000003/blk00000004/sig000001e5 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk000000b8 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig000001e2 ), + .Q(\blk00000003/blk00000004/sig000001e3 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk000000b7 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig000001e0 ), + .Q(\blk00000003/blk00000004/sig000001e1 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk000000b6 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig000001de ), + .Q(\blk00000003/blk00000004/sig000001df ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk000000b5 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig000001dc ), + .Q(\blk00000003/blk00000004/sig000001dd ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk000000b4 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig000001da ), + .Q(\blk00000003/blk00000004/sig000001db ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk000000b3 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig000001d8 ), + .Q(\blk00000003/blk00000004/sig000001d9 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk000000b2 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig000001d6 ), + .Q(\blk00000003/blk00000004/sig000001d7 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk000000b1 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig000001d4 ), + .Q(\blk00000003/blk00000004/sig000001d5 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk000000b0 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig000001d2 ), + .Q(\blk00000003/blk00000004/sig000001d3 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk000000af ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig000001d0 ), + .Q(\blk00000003/blk00000004/sig000001d1 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk000000ae ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig000001ce ), + .Q(\blk00000003/blk00000004/sig000001cf ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk000000ad ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig000001cc ), + .Q(\blk00000003/blk00000004/sig000001cd ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk000000ac ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig000001ca ), + .Q(\blk00000003/blk00000004/sig000001cb ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk000000ab ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig000001c8 ), + .Q(\blk00000003/blk00000004/sig000001c9 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk000000aa ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig000001c6 ), + .Q(\blk00000003/blk00000004/sig000001c7 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk000000a9 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig000001c4 ), + .Q(\blk00000003/blk00000004/sig000001c5 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk000000a8 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig000001c2 ), + .Q(\blk00000003/blk00000004/sig000001c3 ) + ); + RAM16X1D #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000004/blk000000a7 ( + .A0(\blk00000003/blk00000004/sig00000176 ), + .A1(\blk00000003/blk00000004/sig00000178 ), + .A2(\blk00000003/blk00000004/sig0000017a ), + .A3(\blk00000003/blk00000004/sig0000017c ), + .D(\blk00000003/blk00000004/sig000001b3 ), + .DPRA0(\blk00000003/blk00000004/sig000001c0 ), + .DPRA1(\blk00000003/blk00000004/sig0000015c ), + .DPRA2(\blk00000003/sig00000001 ), + .DPRA3(\blk00000003/sig00000001 ), + .WCLK(clk), + .WE(\blk00000003/blk00000004/sig000001c1 ), + .SPO(\blk00000003/blk00000004/sig000001bc ), + .DPO(\blk00000003/blk00000004/sig000001b6 ) + ); + RAM16X1D #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000004/blk000000a6 ( + .A0(\blk00000003/blk00000004/sig00000176 ), + .A1(\blk00000003/blk00000004/sig00000178 ), + .A2(\blk00000003/blk00000004/sig0000017a ), + .A3(\blk00000003/blk00000004/sig0000017c ), + .D(\blk00000003/blk00000004/sig000001b2 ), + .DPRA0(\blk00000003/blk00000004/sig000001c0 ), + .DPRA1(\blk00000003/blk00000004/sig0000015c ), + .DPRA2(\blk00000003/sig00000001 ), + .DPRA3(\blk00000003/sig00000001 ), + .WCLK(clk), + .WE(\blk00000003/blk00000004/sig000001c1 ), + .SPO(\blk00000003/blk00000004/sig000001ba ), + .DPO(\blk00000003/blk00000004/sig000001b4 ) + ); + RAM16X1D #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000004/blk000000a5 ( + .A0(\blk00000003/blk00000004/sig00000176 ), + .A1(\blk00000003/blk00000004/sig00000178 ), + .A2(\blk00000003/blk00000004/sig0000017a ), + .A3(\blk00000003/blk00000004/sig0000017c ), + .D(\blk00000003/blk00000004/sig000001af ), + .DPRA0(\blk00000003/blk00000004/sig000001c0 ), + .DPRA1(\blk00000003/blk00000004/sig0000015c ), + .DPRA2(\blk00000003/sig00000001 ), + .DPRA3(\blk00000003/sig00000001 ), + .WCLK(clk), + .WE(\blk00000003/blk00000004/sig000001c1 ), + .SPO(\blk00000003/blk00000004/sig000001be ), + .DPO(\blk00000003/blk00000004/sig000001b8 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk000000a4 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig000001be ), + .Q(\blk00000003/blk00000004/sig000001bf ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk000000a3 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig000001bc ), + .Q(\blk00000003/blk00000004/sig000001bd ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk000000a2 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig000001ba ), + .Q(\blk00000003/blk00000004/sig000001bb ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk000000a1 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig000001b8 ), + .Q(\blk00000003/blk00000004/sig000001b9 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk000000a0 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig000001b6 ), + .Q(\blk00000003/blk00000004/sig000001b7 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk0000009f ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig000001b4 ), + .Q(\blk00000003/blk00000004/sig000001b5 ) + ); + RAM16X1D #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000004/blk0000009e ( + .A0(\blk00000003/blk00000004/sig00000176 ), + .A1(\blk00000003/blk00000004/sig00000178 ), + .A2(\blk00000003/blk00000004/sig0000017a ), + .A3(\blk00000003/blk00000004/sig0000017c ), + .D(\blk00000003/blk00000004/sig000001b3 ), + .DPRA0(\blk00000003/blk00000004/sig000001b0 ), + .DPRA1(\blk00000003/blk00000004/sig0000015c ), + .DPRA2(\blk00000003/sig00000001 ), + .DPRA3(\blk00000003/sig00000001 ), + .WCLK(clk), + .WE(\blk00000003/blk00000004/sig000001b1 ), + .SPO(\blk00000003/blk00000004/sig000001ab ), + .DPO(\blk00000003/blk00000004/sig000001a5 ) + ); + RAM16X1D #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000004/blk0000009d ( + .A0(\blk00000003/blk00000004/sig00000176 ), + .A1(\blk00000003/blk00000004/sig00000178 ), + .A2(\blk00000003/blk00000004/sig0000017a ), + .A3(\blk00000003/blk00000004/sig0000017c ), + .D(\blk00000003/blk00000004/sig000001b2 ), + .DPRA0(\blk00000003/blk00000004/sig000001b0 ), + .DPRA1(\blk00000003/blk00000004/sig0000015c ), + .DPRA2(\blk00000003/sig00000001 ), + .DPRA3(\blk00000003/sig00000001 ), + .WCLK(clk), + .WE(\blk00000003/blk00000004/sig000001b1 ), + .SPO(\blk00000003/blk00000004/sig000001a9 ), + .DPO(\blk00000003/blk00000004/sig000001a3 ) + ); + RAM16X1D #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000004/blk0000009c ( + .A0(\blk00000003/blk00000004/sig00000176 ), + .A1(\blk00000003/blk00000004/sig00000178 ), + .A2(\blk00000003/blk00000004/sig0000017a ), + .A3(\blk00000003/blk00000004/sig0000017c ), + .D(\blk00000003/blk00000004/sig000001af ), + .DPRA0(\blk00000003/blk00000004/sig000001b0 ), + .DPRA1(\blk00000003/blk00000004/sig0000015c ), + .DPRA2(\blk00000003/sig00000001 ), + .DPRA3(\blk00000003/sig00000001 ), + .WCLK(clk), + .WE(\blk00000003/blk00000004/sig000001b1 ), + .SPO(\blk00000003/blk00000004/sig000001ad ), + .DPO(\blk00000003/blk00000004/sig000001a7 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk0000009b ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig000001ad ), + .Q(\blk00000003/blk00000004/sig000001ae ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk0000009a ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig000001ab ), + .Q(\blk00000003/blk00000004/sig000001ac ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk00000099 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig000001a9 ), + .Q(\blk00000003/blk00000004/sig000001aa ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk00000098 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig000001a7 ), + .Q(\blk00000003/blk00000004/sig000001a8 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk00000097 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig000001a5 ), + .Q(\blk00000003/blk00000004/sig000001a6 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk00000096 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig000001a3 ), + .Q(\blk00000003/blk00000004/sig000001a4 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk00000095 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig000001a1 ), + .Q(\blk00000003/blk00000004/sig000001a2 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk00000094 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig0000019f ), + .Q(\blk00000003/blk00000004/sig000001a0 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk00000093 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig0000019d ), + .Q(\blk00000003/blk00000004/sig0000019e ) + ); + LUT3 #( + .INIT ( 8'hE4 )) + \blk00000003/blk00000004/blk00000092 ( + .I0(\blk00000003/blk00000004/sig00000186 ), + .I1(\blk00000003/blk00000004/sig0000019b ), + .I2(\blk00000003/sig00000001 ), + .O(\blk00000003/blk00000004/sig0000019c ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk00000091 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig00000199 ), + .Q(\blk00000003/blk00000004/sig0000019a ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk00000090 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig00000197 ), + .Q(\blk00000003/blk00000004/sig00000198 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk0000008f ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig00000195 ), + .Q(\blk00000003/blk00000004/sig00000196 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk0000008e ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig00000193 ), + .Q(\blk00000003/blk00000004/sig00000194 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk0000008d ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig00000191 ), + .Q(\blk00000003/blk00000004/sig00000192 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk0000008c ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig0000018f ), + .Q(\blk00000003/blk00000004/sig00000190 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk0000008b ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig0000018d ), + .Q(\blk00000003/blk00000004/sig0000018e ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk0000008a ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig0000018b ), + .Q(\blk00000003/blk00000004/sig0000018c ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk00000089 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig00000189 ), + .Q(\blk00000003/blk00000004/sig0000018a ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk00000088 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig00000187 ), + .Q(\blk00000003/blk00000004/sig00000188 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk00000087 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig00000185 ), + .Q(\blk00000003/blk00000004/sig00000186 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk00000086 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig00000183 ), + .Q(\blk00000003/blk00000004/sig00000184 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk00000085 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig00000181 ), + .Q(\blk00000003/blk00000004/sig00000182 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk00000084 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig0000017f ), + .Q(\blk00000003/blk00000004/sig00000180 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk00000083 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig0000017d ), + .Q(\blk00000003/blk00000004/sig0000017e ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk00000082 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig0000017b ), + .Q(\blk00000003/blk00000004/sig0000017c ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk00000081 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig00000179 ), + .Q(\blk00000003/blk00000004/sig0000017a ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk00000080 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig00000177 ), + .Q(\blk00000003/blk00000004/sig00000178 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk0000007f ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig00000175 ), + .Q(\blk00000003/blk00000004/sig00000176 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk0000007e ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig00000173 ), + .Q(\blk00000003/blk00000004/sig00000174 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk0000007d ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig00000171 ), + .Q(\blk00000003/blk00000004/sig00000172 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk0000007c ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig0000016f ), + .Q(\blk00000003/blk00000004/sig00000170 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk0000007b ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig0000016d ), + .Q(\blk00000003/blk00000004/sig0000016e ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk0000007a ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig0000016b ), + .Q(\blk00000003/blk00000004/sig0000016c ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk00000079 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig00000169 ), + .Q(\blk00000003/blk00000004/sig0000016a ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk00000078 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig00000167 ), + .Q(\blk00000003/blk00000004/sig00000168 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk00000077 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig00000165 ), + .Q(\blk00000003/blk00000004/sig00000166 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk00000076 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig00000163 ), + .Q(\blk00000003/blk00000004/sig00000164 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk00000075 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig00000161 ), + .Q(\blk00000003/blk00000004/sig00000162 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk00000074 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig0000015f ), + .Q(\blk00000003/blk00000004/sig00000160 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk00000073 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig0000015d ), + .Q(\blk00000003/blk00000004/sig0000015e ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk00000072 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig0000015b ), + .Q(\blk00000003/blk00000004/sig0000015c ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk00000071 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig00000159 ), + .Q(\blk00000003/blk00000004/sig0000015a ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk00000070 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig00000157 ), + .Q(\blk00000003/blk00000004/sig00000158 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk0000006f ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig00000155 ), + .Q(\blk00000003/blk00000004/sig00000156 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk0000006e ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig00000153 ), + .Q(\blk00000003/blk00000004/sig00000154 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk0000006d ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig00000151 ), + .Q(\blk00000003/blk00000004/sig00000152 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk0000006c ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig0000014f ), + .Q(\blk00000003/blk00000004/sig00000150 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk0000006b ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig0000014d ), + .Q(\blk00000003/blk00000004/sig0000014e ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk0000006a ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig0000014b ), + .Q(\blk00000003/blk00000004/sig0000014c ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk00000069 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig00000149 ), + .Q(\blk00000003/blk00000004/sig0000014a ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk00000068 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig00000147 ), + .Q(\blk00000003/blk00000004/sig00000148 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk00000067 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig00000145 ), + .Q(\blk00000003/blk00000004/sig00000146 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk00000066 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig00000143 ), + .Q(\blk00000003/blk00000004/sig00000144 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk00000065 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig00000141 ), + .Q(\blk00000003/blk00000004/sig00000142 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk00000064 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig0000013f ), + .Q(\blk00000003/blk00000004/sig00000140 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk00000063 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig0000013d ), + .Q(\blk00000003/blk00000004/sig0000013e ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk00000062 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig0000013b ), + .Q(\blk00000003/blk00000004/sig0000013c ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk00000061 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig00000139 ), + .Q(\blk00000003/blk00000004/sig0000013a ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk00000060 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig00000137 ), + .Q(\blk00000003/blk00000004/sig00000138 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk0000005f ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig00000135 ), + .Q(\blk00000003/blk00000004/sig00000136 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk0000005e ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig00000133 ), + .Q(\blk00000003/blk00000004/sig00000134 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk0000005d ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig00000131 ), + .Q(\blk00000003/blk00000004/sig00000132 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk0000005c ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig0000012f ), + .Q(\blk00000003/blk00000004/sig00000130 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk0000005b ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig0000012d ), + .Q(\blk00000003/blk00000004/sig0000012e ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk0000005a ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig0000012b ), + .Q(\blk00000003/blk00000004/sig0000012c ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk00000059 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig00000129 ), + .Q(\blk00000003/blk00000004/sig0000012a ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk00000058 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig00000127 ), + .Q(\blk00000003/blk00000004/sig00000128 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk00000057 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig00000125 ), + .Q(\blk00000003/blk00000004/sig00000126 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk00000056 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig00000123 ), + .Q(\blk00000003/blk00000004/sig00000124 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk00000055 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig00000121 ), + .Q(\blk00000003/blk00000004/sig00000122 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk00000054 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig0000011f ), + .Q(\blk00000003/blk00000004/sig00000120 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk00000053 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig0000011d ), + .Q(\blk00000003/blk00000004/sig0000011e ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk00000052 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig0000011b ), + .Q(\blk00000003/blk00000004/sig0000011c ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk00000051 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig00000119 ), + .Q(\blk00000003/blk00000004/sig0000011a ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk00000050 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig00000117 ), + .Q(\blk00000003/blk00000004/sig00000118 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk0000004f ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig00000115 ), + .Q(\blk00000003/blk00000004/sig00000116 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk0000004e ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig00000113 ), + .Q(\blk00000003/blk00000004/sig00000114 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk0000004d ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig00000111 ), + .Q(\blk00000003/blk00000004/sig00000112 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk0000004c ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig0000010f ), + .Q(\blk00000003/blk00000004/sig00000110 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk0000004b ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig0000010d ), + .Q(\blk00000003/blk00000004/sig0000010e ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk0000004a ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig0000010b ), + .Q(\blk00000003/blk00000004/sig0000010c ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk00000049 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig00000109 ), + .Q(\blk00000003/blk00000004/sig0000010a ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk00000048 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig00000107 ), + .Q(\blk00000003/blk00000004/sig00000108 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk00000047 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig00000105 ), + .Q(\blk00000003/blk00000004/sig00000106 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk00000046 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig00000103 ), + .Q(\blk00000003/blk00000004/sig00000104 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk00000045 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig00000101 ), + .Q(\blk00000003/blk00000004/sig00000102 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk00000044 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig000000ff ), + .Q(\blk00000003/blk00000004/sig00000100 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk00000043 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig000000fd ), + .Q(\blk00000003/blk00000004/sig000000fe ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk00000042 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig000000fb ), + .Q(\blk00000003/blk00000004/sig000000fc ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk00000041 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig000000f9 ), + .Q(\blk00000003/blk00000004/sig000000fa ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk00000040 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig000000f7 ), + .Q(\blk00000003/blk00000004/sig000000f8 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk0000003f ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig000000f5 ), + .Q(\blk00000003/blk00000004/sig000000f6 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk0000003e ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig000000f3 ), + .Q(\blk00000003/blk00000004/sig000000f4 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk0000003d ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig000000f1 ), + .Q(\blk00000003/blk00000004/sig000000f2 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk0000003c ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig000000ef ), + .Q(\blk00000003/blk00000004/sig000000f0 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk0000003b ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig000000ed ), + .Q(\blk00000003/blk00000004/sig000000ee ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk0000003a ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig000000eb ), + .Q(\blk00000003/blk00000004/sig000000ec ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk00000039 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig000000e9 ), + .Q(\blk00000003/blk00000004/sig000000ea ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk00000038 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig000000e7 ), + .Q(\blk00000003/blk00000004/sig000000e8 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk00000037 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig000000e5 ), + .Q(\blk00000003/blk00000004/sig000000e6 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk00000036 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig000000e3 ), + .Q(\blk00000003/blk00000004/sig000000e4 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk00000035 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig000000e1 ), + .Q(\blk00000003/blk00000004/sig000000e2 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk00000034 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig000000df ), + .Q(\blk00000003/blk00000004/sig000000e0 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk00000033 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig000000dd ), + .Q(\blk00000003/blk00000004/sig000000de ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk00000032 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig000000db ), + .Q(\blk00000003/blk00000004/sig000000dc ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk00000031 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig000000d9 ), + .Q(\blk00000003/blk00000004/sig000000da ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk00000030 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig000000d7 ), + .Q(\blk00000003/blk00000004/sig000000d8 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk0000002f ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig000000d5 ), + .Q(\blk00000003/blk00000004/sig000000d6 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk0000002e ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig000000d3 ), + .Q(\blk00000003/blk00000004/sig000000d4 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk0000002d ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig000000d1 ), + .Q(\blk00000003/blk00000004/sig000000d2 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk0000002c ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig000000cf ), + .Q(\blk00000003/blk00000004/sig000000d0 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk0000002b ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig000000cd ), + .Q(\blk00000003/blk00000004/sig000000ce ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk0000002a ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig000000cb ), + .Q(\blk00000003/blk00000004/sig000000cc ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk00000029 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig000000c9 ), + .Q(\blk00000003/blk00000004/sig000000ca ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk00000028 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig000000c7 ), + .Q(\blk00000003/blk00000004/sig000000c8 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk00000027 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig000000c5 ), + .Q(\blk00000003/blk00000004/sig000000c6 ) + ); + MUXCY \blk00000003/blk00000004/blk00000026 ( + .CI(\blk00000003/sig00000001 ), + .DI(\blk00000003/blk00000004/sig00000093 ), + .S(\blk00000003/blk00000004/sig000000c4 ), + .O(\blk00000003/blk00000004/sig000000c1 ) + ); + XORCY \blk00000003/blk00000004/blk00000025 ( + .CI(\blk00000003/sig00000001 ), + .LI(\blk00000003/blk00000004/sig000000c4 ), + .O(\blk00000003/blk00000004/sig000000b6 ) + ); + XORCY \blk00000003/blk00000004/blk00000024 ( + .CI(\blk00000003/blk00000004/sig000000ba ), + .LI(\blk00000003/blk00000004/sig000000c3 ), + .O(\blk00000003/blk00000004/sig000000a9 ) + ); + MUXCY \blk00000003/blk00000004/blk00000023 ( + .CI(\blk00000003/blk00000004/sig000000c1 ), + .DI(\blk00000003/sig00000001 ), + .S(\blk00000003/blk00000004/sig000000c2 ), + .O(\blk00000003/blk00000004/sig000000bf ) + ); + XORCY \blk00000003/blk00000004/blk00000022 ( + .CI(\blk00000003/blk00000004/sig000000c1 ), + .LI(\blk00000003/blk00000004/sig000000c2 ), + .O(\blk00000003/blk00000004/sig000000b4 ) + ); + MUXCY \blk00000003/blk00000004/blk00000021 ( + .CI(\blk00000003/blk00000004/sig000000bf ), + .DI(\blk00000003/sig00000001 ), + .S(\blk00000003/blk00000004/sig000000c0 ), + .O(\blk00000003/blk00000004/sig000000bd ) + ); + XORCY \blk00000003/blk00000004/blk00000020 ( + .CI(\blk00000003/blk00000004/sig000000bf ), + .LI(\blk00000003/blk00000004/sig000000c0 ), + .O(\blk00000003/blk00000004/sig000000b2 ) + ); + MUXCY \blk00000003/blk00000004/blk0000001f ( + .CI(\blk00000003/blk00000004/sig000000bd ), + .DI(\blk00000003/sig00000001 ), + .S(\blk00000003/blk00000004/sig000000be ), + .O(\blk00000003/blk00000004/sig000000bb ) + ); + XORCY \blk00000003/blk00000004/blk0000001e ( + .CI(\blk00000003/blk00000004/sig000000bd ), + .LI(\blk00000003/blk00000004/sig000000be ), + .O(\blk00000003/blk00000004/sig000000b0 ) + ); + MUXCY \blk00000003/blk00000004/blk0000001d ( + .CI(\blk00000003/blk00000004/sig000000bb ), + .DI(\blk00000003/sig00000001 ), + .S(\blk00000003/blk00000004/sig000000bc ), + .O(\blk00000003/blk00000004/sig000000b8 ) + ); + XORCY \blk00000003/blk00000004/blk0000001c ( + .CI(\blk00000003/blk00000004/sig000000bb ), + .LI(\blk00000003/blk00000004/sig000000bc ), + .O(\blk00000003/blk00000004/sig000000ae ) + ); + MUXCY \blk00000003/blk00000004/blk0000001b ( + .CI(\blk00000003/blk00000004/sig000000b8 ), + .DI(\blk00000003/sig00000001 ), + .S(\blk00000003/blk00000004/sig000000b9 ), + .O(\blk00000003/blk00000004/sig000000ba ) + ); + XORCY \blk00000003/blk00000004/blk0000001a ( + .CI(\blk00000003/blk00000004/sig000000b8 ), + .LI(\blk00000003/blk00000004/sig000000b9 ), + .O(\blk00000003/blk00000004/sig000000ac ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk00000019 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig000000b6 ), + .R(\blk00000003/blk00000004/sig000000aa ), + .Q(\blk00000003/blk00000004/sig000000b7 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk00000018 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig000000b4 ), + .R(\blk00000003/blk00000004/sig000000aa ), + .Q(\blk00000003/blk00000004/sig000000b5 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk00000017 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig000000b2 ), + .R(\blk00000003/blk00000004/sig000000aa ), + .Q(\blk00000003/blk00000004/sig000000b3 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk00000016 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig000000b0 ), + .R(\blk00000003/blk00000004/sig000000aa ), + .Q(\blk00000003/blk00000004/sig000000b1 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk00000015 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig000000ae ), + .R(\blk00000003/blk00000004/sig000000aa ), + .Q(\blk00000003/blk00000004/sig000000af ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk00000014 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig000000ac ), + .R(\blk00000003/blk00000004/sig000000aa ), + .Q(\blk00000003/blk00000004/sig000000ad ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk00000013 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig000000a9 ), + .R(\blk00000003/blk00000004/sig000000aa ), + .Q(\blk00000003/blk00000004/sig000000ab ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk00000012 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig000000a8 ), + .Q(\blk00000003/blk00000004/sig00000095 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk00000011 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig000000a6 ), + .Q(\blk00000003/blk00000004/sig000000a7 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk00000010 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig000000a4 ), + .Q(\blk00000003/blk00000004/sig000000a5 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk0000000f ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig000000a2 ), + .Q(\blk00000003/blk00000004/sig000000a3 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk0000000e ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig000000a0 ), + .Q(\blk00000003/blk00000004/sig000000a1 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk0000000d ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig0000009e ), + .Q(\blk00000003/blk00000004/sig0000009f ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk0000000c ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig0000009c ), + .Q(\blk00000003/blk00000004/sig0000009d ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk0000000b ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig0000009a ), + .Q(\blk00000003/blk00000004/sig0000009b ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk0000000a ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig00000098 ), + .Q(\blk00000003/blk00000004/sig00000099 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000004/blk00000009 ( + .C(clk), + .CE(ce), + .D(\blk00000003/blk00000004/sig00000096 ), + .Q(\blk00000003/blk00000004/sig00000097 ) + ); + BUF \blk00000003/blk00000004/blk00000008 ( + .I(\blk00000003/blk00000004/sig00000095 ), + .O(rdy) + ); + BUF \blk00000003/blk00000004/blk00000007 ( + .I(\blk00000003/blk00000004/sig00000094 ), + .O(data_out) + ); + VCC \blk00000003/blk00000004/blk00000006 ( + .P(\blk00000003/blk00000004/sig00000093 ) + ); + GND \blk00000003/blk00000004/blk00000005 ( + .G(\blk00000003/sig00000001 ) + ); + +// synthesis translate_on + +endmodule + +// synthesis translate_off + +`ifndef GLBL +`define GLBL + +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (weak1, weak0) GSR = GSR_int; + assign (weak1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + +endmodule + +`endif + +// synthesis translate_on diff --git a/verilog/coregen/xfft_v7_1.v b/verilog/coregen/xfft_v7_1.v new file mode 100644 index 0000000..934a2da --- /dev/null +++ b/verilog/coregen/xfft_v7_1.v @@ -0,0 +1,49712 @@ +//////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved. +//////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor: Xilinx +// \ \ \/ Version: M.63c +// \ \ Application: netgen +// / / Filename: xfft_v7_1.v +// /___/ /\ Timestamp: Mon Aug 22 19:00:11 2016 +// \ \ / \ +// \___\/\___\ +// +// Command : -intstyle ise -w -sim -ofmt verilog ./tmp/_cg/xfft_v7_1.ngc ./tmp/_cg/xfft_v7_1.v +// Device : 3sd3400afg676-5 +// Input file : ./tmp/_cg/xfft_v7_1.ngc +// Output file : ./tmp/_cg/xfft_v7_1.v +// # of Modules : 1 +// Design Name : xfft_v7_1 +// Xilinx : /opt/Xilinx/12.2/ISE_DS/ISE/ +// +// Purpose: +// This verilog netlist is a verification model and uses simulation +// primitives which may not represent the true implementation of the +// device, however the netlist is functionally correct and should not +// be modified. This file cannot be synthesized and should only be used +// with supported simulation tools. +// +// Reference: +// Command Line Tools User Guide, Chapter 23 and Synthesis and Simulation Design Guide, Chapter 6 +// +//////////////////////////////////////////////////////////////////////////////// + +`timescale 1 ns/1 ps + +module xfft_v7_1 ( + rfd, start, fwd_inv, dv, done, clk, busy, fwd_inv_we, edone, xn_re, xk_im, xn_index, xk_re, xn_im, xk_index +)/* synthesis syn_black_box syn_noprune=1 */; + output rfd; + input start; + input fwd_inv; + output dv; + output done; + input clk; + output busy; + input fwd_inv_we; + output edone; + input [15 : 0] xn_re; + output [22 : 0] xk_im; + output [5 : 0] xn_index; + output [22 : 0] xk_re; + input [15 : 0] xn_im; + output [5 : 0] xk_index; + + // synthesis translate_off + + wire NlwRenamedSig_OI_rfd; + wire NlwRenamedSig_OI_edone; + wire \blk00000003/sig000014f8 ; + wire \blk00000003/sig000014f7 ; + wire \blk00000003/sig000014f6 ; + wire \blk00000003/sig000014f5 ; + wire \blk00000003/sig000014f4 ; + wire \blk00000003/sig000014f3 ; + wire \blk00000003/sig000014f2 ; + wire \blk00000003/sig000014f1 ; + wire \blk00000003/sig000014f0 ; + wire \blk00000003/sig000014ef ; + wire \blk00000003/sig000014ee ; + wire \blk00000003/sig000014ed ; + wire \blk00000003/sig000014ec ; + wire \blk00000003/sig000014eb ; + wire \blk00000003/sig000014ea ; + wire \blk00000003/sig000014e9 ; + wire \blk00000003/sig000014e8 ; + wire \blk00000003/sig000014e7 ; + wire \blk00000003/sig000014e6 ; + wire \blk00000003/sig000014e5 ; + wire \blk00000003/sig000014e4 ; + wire \blk00000003/sig000014e3 ; + wire \blk00000003/sig000014e2 ; + wire \blk00000003/sig000014e1 ; + wire \blk00000003/sig000014e0 ; + wire \blk00000003/sig000014df ; + wire \blk00000003/sig000014de ; + wire \blk00000003/sig000014dd ; + wire \blk00000003/sig000014dc ; + wire \blk00000003/sig000014db ; + wire \blk00000003/sig000014da ; + wire \blk00000003/sig000014d9 ; + wire \blk00000003/sig000014d8 ; + wire \blk00000003/sig000014d7 ; + wire \blk00000003/sig000014d6 ; + wire \blk00000003/sig000014d5 ; + wire \blk00000003/sig000014d4 ; + wire \blk00000003/sig000014d3 ; + wire \blk00000003/sig000014d2 ; + wire \blk00000003/sig000014d1 ; + wire \blk00000003/sig000014d0 ; + wire \blk00000003/sig000014cf ; + wire \blk00000003/sig000014ce ; + wire \blk00000003/sig000014cd ; + wire \blk00000003/sig000014cc ; + wire \blk00000003/sig000014cb ; + wire \blk00000003/sig000014ca ; + wire \blk00000003/sig000014c9 ; + wire \blk00000003/sig000014c8 ; + wire \blk00000003/sig000014c7 ; + wire \blk00000003/sig000014c6 ; + wire \blk00000003/sig000014c5 ; + wire \blk00000003/sig000014c4 ; + wire \blk00000003/sig000014c3 ; + wire \blk00000003/sig000014c2 ; + wire \blk00000003/sig000014c1 ; + wire \blk00000003/sig000014c0 ; + wire \blk00000003/sig000014bf ; + wire \blk00000003/sig000014be ; + wire \blk00000003/sig000014bd ; + wire \blk00000003/sig000014bc ; + wire \blk00000003/sig000014bb ; + wire \blk00000003/sig000014ba ; + wire \blk00000003/sig000014b9 ; + wire \blk00000003/sig000014b8 ; + wire \blk00000003/sig000014b7 ; + wire \blk00000003/sig000014b6 ; + wire \blk00000003/sig000014b5 ; + wire \blk00000003/sig000014b4 ; + wire \blk00000003/sig000014b3 ; + wire \blk00000003/sig000014b2 ; + wire \blk00000003/sig000014b1 ; + wire \blk00000003/sig000014b0 ; + wire \blk00000003/sig000014af ; + wire \blk00000003/sig000014ae ; + wire \blk00000003/sig000014ad ; + wire \blk00000003/sig000014ac ; + wire \blk00000003/sig000014ab ; + wire \blk00000003/sig000014aa ; + wire \blk00000003/sig000014a9 ; + wire \blk00000003/sig000014a8 ; + wire \blk00000003/sig000014a7 ; + wire \blk00000003/sig000014a6 ; + wire \blk00000003/sig000014a5 ; + wire \blk00000003/sig000014a4 ; + wire \blk00000003/sig000014a3 ; + wire \blk00000003/sig000014a2 ; + wire \blk00000003/sig000014a1 ; + wire \blk00000003/sig000014a0 ; + wire \blk00000003/sig0000149f ; + wire \blk00000003/sig0000149e ; + wire \blk00000003/sig0000149d ; + wire \blk00000003/sig0000149c ; + wire \blk00000003/sig0000149b ; + wire \blk00000003/sig0000149a ; + wire \blk00000003/sig00001499 ; + wire \blk00000003/sig00001498 ; + wire \blk00000003/sig00001497 ; + wire \blk00000003/sig00001496 ; + wire \blk00000003/sig00001495 ; + wire \blk00000003/sig00001494 ; + wire \blk00000003/sig00001493 ; + wire \blk00000003/sig00001492 ; + wire \blk00000003/sig00001491 ; + wire \blk00000003/sig00001490 ; + wire \blk00000003/sig0000148f ; + wire \blk00000003/sig0000148e ; + wire \blk00000003/sig0000148d ; + wire \blk00000003/sig0000148c ; + wire \blk00000003/sig0000148b ; + wire \blk00000003/sig0000148a ; + wire \blk00000003/sig00001489 ; + wire \blk00000003/sig00001488 ; + wire \blk00000003/sig00001487 ; + wire \blk00000003/sig00001486 ; + wire \blk00000003/sig00001485 ; + wire \blk00000003/sig00001484 ; + wire \blk00000003/sig00001483 ; + wire \blk00000003/sig00001482 ; + wire \blk00000003/sig00001481 ; + wire \blk00000003/sig00001480 ; + wire \blk00000003/sig0000147f ; + wire \blk00000003/sig0000147e ; + wire \blk00000003/sig0000147d ; + wire \blk00000003/sig0000147c ; + wire \blk00000003/sig0000147b ; + wire \blk00000003/sig0000147a ; + wire \blk00000003/sig00001479 ; + wire \blk00000003/sig00001478 ; + wire \blk00000003/sig00001477 ; + wire \blk00000003/sig00001476 ; + wire \blk00000003/sig00001475 ; + wire \blk00000003/sig00001474 ; + wire \blk00000003/sig00001473 ; + wire \blk00000003/sig00001472 ; + wire \blk00000003/sig00001471 ; + wire \blk00000003/sig00001470 ; + wire \blk00000003/sig0000146f ; + wire \blk00000003/sig0000146e ; + wire \blk00000003/sig0000146d ; + wire \blk00000003/sig0000146c ; + wire \blk00000003/sig0000146b ; + wire \blk00000003/sig0000146a ; + wire \blk00000003/sig00001469 ; + wire \blk00000003/sig00001468 ; + wire \blk00000003/sig00001467 ; + wire \blk00000003/sig00001466 ; + wire \blk00000003/sig00001465 ; + wire \blk00000003/sig00001464 ; + wire \blk00000003/sig00001463 ; + wire \blk00000003/sig00001462 ; + wire \blk00000003/sig00001461 ; + wire \blk00000003/sig00001460 ; + wire \blk00000003/sig0000145f ; + wire \blk00000003/sig0000145e ; + wire \blk00000003/sig0000145d ; + wire \blk00000003/sig0000145c ; + wire \blk00000003/sig0000145b ; + wire \blk00000003/sig0000145a ; + wire \blk00000003/sig00001459 ; + wire \blk00000003/sig00001458 ; + wire \blk00000003/sig00001457 ; + wire \blk00000003/sig00001456 ; + wire \blk00000003/sig00001455 ; + wire \blk00000003/sig00001454 ; + wire \blk00000003/sig00001453 ; + wire \blk00000003/sig00001452 ; + wire \blk00000003/sig00001451 ; + wire \blk00000003/sig00001450 ; + wire \blk00000003/sig0000144f ; + wire \blk00000003/sig0000144e ; + wire \blk00000003/sig0000144d ; + wire \blk00000003/sig0000144c ; + wire \blk00000003/sig0000144b ; + wire \blk00000003/sig0000144a ; + wire \blk00000003/sig00001449 ; + wire \blk00000003/sig00001448 ; + wire \blk00000003/sig00001447 ; + wire \blk00000003/sig00001446 ; + wire \blk00000003/sig00001445 ; + wire \blk00000003/sig00001444 ; + wire \blk00000003/sig00001443 ; + wire \blk00000003/sig00001442 ; + wire \blk00000003/sig00001441 ; + wire \blk00000003/sig00001440 ; + wire \blk00000003/sig0000143f ; + wire \blk00000003/sig0000143e ; + wire \blk00000003/sig0000143d ; + wire \blk00000003/sig0000143c ; + wire \blk00000003/sig0000143b ; + wire \blk00000003/sig0000143a ; + wire \blk00000003/sig00001439 ; + wire \blk00000003/sig00001438 ; + wire \blk00000003/sig00001437 ; + wire \blk00000003/sig00001436 ; + wire \blk00000003/sig00001435 ; + wire \blk00000003/sig00001434 ; + wire \blk00000003/sig00001433 ; + wire \blk00000003/sig00001432 ; + wire \blk00000003/sig00001431 ; + wire \blk00000003/sig00001430 ; + wire \blk00000003/sig0000142f ; + wire \blk00000003/sig0000142e ; + wire \blk00000003/sig0000142d ; + wire \blk00000003/sig0000142c ; + wire \blk00000003/sig0000142b ; + wire \blk00000003/sig0000142a ; + wire \blk00000003/sig00001429 ; + wire \blk00000003/sig00001428 ; + wire \blk00000003/sig00001427 ; + wire \blk00000003/sig00001426 ; + wire \blk00000003/sig00001425 ; + wire \blk00000003/sig00001424 ; + wire \blk00000003/sig00001423 ; + wire \blk00000003/sig00001422 ; + wire \blk00000003/sig00001421 ; + wire \blk00000003/sig00001420 ; + wire \blk00000003/sig0000141f ; + wire \blk00000003/sig0000141e ; + wire \blk00000003/sig0000141d ; + wire \blk00000003/sig0000141c ; + wire \blk00000003/sig0000141b ; + wire \blk00000003/sig0000141a ; + wire \blk00000003/sig00001419 ; + wire \blk00000003/sig00001418 ; + wire \blk00000003/sig00001417 ; + wire \blk00000003/sig00001416 ; + wire \blk00000003/sig00001415 ; + wire \blk00000003/sig00001414 ; + wire \blk00000003/sig00001413 ; + wire \blk00000003/sig00001412 ; + wire \blk00000003/sig00001411 ; + wire \blk00000003/sig00001410 ; + wire \blk00000003/sig0000140f ; + wire \blk00000003/sig0000140e ; + wire \blk00000003/sig0000140d ; + wire \blk00000003/sig0000140c ; + wire \blk00000003/sig0000140b ; + wire \blk00000003/sig0000140a ; + wire \blk00000003/sig00001409 ; + wire \blk00000003/sig00001408 ; + wire \blk00000003/sig00001407 ; + wire \blk00000003/sig00001406 ; + wire \blk00000003/sig00001405 ; + wire \blk00000003/sig00001404 ; + wire \blk00000003/sig00001403 ; + wire \blk00000003/sig00001402 ; + wire \blk00000003/sig00001401 ; + wire \blk00000003/sig00001400 ; + wire \blk00000003/sig000013ff ; + wire \blk00000003/sig000013fe ; + wire \blk00000003/sig000013fd ; + wire \blk00000003/sig000013fc ; + wire \blk00000003/sig000013fb ; + wire \blk00000003/sig000013fa ; + wire \blk00000003/sig000013f9 ; + wire \blk00000003/sig000013f8 ; + wire \blk00000003/sig000013f7 ; + wire \blk00000003/sig000013f6 ; + wire \blk00000003/sig000013f5 ; + wire \blk00000003/sig000013f4 ; + wire \blk00000003/sig000013f3 ; + wire \blk00000003/sig000013f2 ; + wire \blk00000003/sig000013f1 ; + wire \blk00000003/sig000013f0 ; + wire \blk00000003/sig000013ef ; + wire \blk00000003/sig000013ee ; + wire \blk00000003/sig000013ed ; + wire \blk00000003/sig000013ec ; + wire \blk00000003/sig000013eb ; + wire \blk00000003/sig000013ea ; + wire \blk00000003/sig000013e9 ; + wire \blk00000003/sig000013e8 ; + wire \blk00000003/sig000013e7 ; + wire \blk00000003/sig000013e6 ; + wire \blk00000003/sig000013e5 ; + wire \blk00000003/sig000013e4 ; + wire \blk00000003/sig000013e3 ; + wire \blk00000003/sig000013e2 ; + wire \blk00000003/sig000013e1 ; + wire \blk00000003/sig000013e0 ; + wire \blk00000003/sig000013df ; + wire \blk00000003/sig000013de ; + wire \blk00000003/sig000013dd ; + wire \blk00000003/sig000013dc ; + wire \blk00000003/sig000013db ; + wire \blk00000003/sig000013da ; + wire \blk00000003/sig000013d9 ; + wire \blk00000003/sig000013d8 ; + wire \blk00000003/sig000013d7 ; + wire \blk00000003/sig000013d6 ; + wire \blk00000003/sig000013d5 ; + wire \blk00000003/sig000013d4 ; + wire \blk00000003/sig000013d3 ; + wire \blk00000003/sig000013d2 ; + wire \blk00000003/sig000013d1 ; + wire \blk00000003/sig000013d0 ; + wire \blk00000003/sig000013cf ; + wire \blk00000003/sig000013ce ; + wire \blk00000003/sig000013cd ; + wire \blk00000003/sig000013cc ; + wire \blk00000003/sig000013cb ; + wire \blk00000003/sig000013ca ; + wire \blk00000003/sig000013c9 ; + wire \blk00000003/sig000013c8 ; + wire \blk00000003/sig000013c7 ; + wire \blk00000003/sig000013c6 ; + wire \blk00000003/sig000013c5 ; + wire \blk00000003/sig000013c4 ; + wire \blk00000003/sig000013c3 ; + wire \blk00000003/sig000013c2 ; + wire \blk00000003/sig000013c1 ; + wire \blk00000003/sig000013c0 ; + wire \blk00000003/sig000013bf ; + wire \blk00000003/sig000013be ; + wire \blk00000003/sig000013bd ; + wire \blk00000003/sig000013bc ; + wire \blk00000003/sig000013bb ; + wire \blk00000003/sig000013ba ; + wire \blk00000003/sig000013b9 ; + wire \blk00000003/sig000013b8 ; + wire \blk00000003/sig000013b7 ; + wire \blk00000003/sig000013b6 ; + wire \blk00000003/sig000013b5 ; + wire \blk00000003/sig000013b4 ; + wire \blk00000003/sig000013b3 ; + wire \blk00000003/sig000013b2 ; + wire \blk00000003/sig000013b1 ; + wire \blk00000003/sig000013b0 ; + wire \blk00000003/sig000013af ; + wire \blk00000003/sig000013ae ; + wire \blk00000003/sig000013ad ; + wire \blk00000003/sig000013ac ; + wire \blk00000003/sig000013ab ; + wire \blk00000003/sig000013aa ; + wire \blk00000003/sig000013a9 ; + wire \blk00000003/sig000013a8 ; + wire \blk00000003/sig000013a7 ; + wire \blk00000003/sig000013a6 ; + wire \blk00000003/sig000013a5 ; + wire \blk00000003/sig000013a4 ; + wire \blk00000003/sig000013a3 ; + wire \blk00000003/sig000013a2 ; + wire \blk00000003/sig000013a1 ; + wire \blk00000003/sig000013a0 ; + wire \blk00000003/sig0000139f ; + wire \blk00000003/sig0000139e ; + wire \blk00000003/sig0000139d ; + wire \blk00000003/sig0000139c ; + wire \blk00000003/sig0000139b ; + wire \blk00000003/sig0000139a ; + wire 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\NLW_blk00000003/blk00000bfc_BCOUT<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000bfc_BCOUT<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000bfc_BCOUT<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000bfc_BCOUT<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000bfc_BCOUT<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000bfc_BCOUT<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000bfc_BCOUT<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000bfc_BCOUT<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000ae5_CARRYOUT_UNCONNECTED ; + wire \NLW_blk00000003/blk00000ae5_P<47>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000ae5_P<46>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000ae5_P<45>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000ae5_P<44>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000ae5_P<43>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000ae5_P<42>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000ae5_P<41>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000ae5_P<40>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000ae5_P<39>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000ae5_P<38>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000ae5_P<37>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000ae5_P<36>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000ae5_PCOUT<47>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000ae5_PCOUT<46>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000ae5_PCOUT<45>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000ae5_PCOUT<44>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000ae5_PCOUT<43>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000ae5_PCOUT<42>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000ae5_PCOUT<41>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000ae5_PCOUT<40>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000ae5_PCOUT<39>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000ae5_PCOUT<38>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000ae5_PCOUT<37>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000ae5_PCOUT<36>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000ae5_PCOUT<35>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000ae5_PCOUT<34>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000ae5_PCOUT<33>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000ae5_PCOUT<32>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000ae5_PCOUT<31>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000ae5_PCOUT<30>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000ae5_PCOUT<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000ae5_PCOUT<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000ae5_PCOUT<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000ae5_PCOUT<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000ae5_PCOUT<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000ae5_PCOUT<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000ae5_PCOUT<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000ae5_PCOUT<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000ae5_PCOUT<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000ae5_PCOUT<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000ae5_PCOUT<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000ae5_PCOUT<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000ae5_PCOUT<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000ae5_PCOUT<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000ae5_PCOUT<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000ae5_PCOUT<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000ae5_PCOUT<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000ae5_PCOUT<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000ae5_PCOUT<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000ae5_PCOUT<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000ae5_PCOUT<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000ae5_PCOUT<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000ae5_PCOUT<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000ae5_PCOUT<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000ae5_PCOUT<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000ae5_PCOUT<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000ae5_PCOUT<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000ae5_PCOUT<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000ae5_PCOUT<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000ae5_PCOUT<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000ae5_BCOUT<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000ae5_BCOUT<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000ae5_BCOUT<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000ae5_BCOUT<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000ae5_BCOUT<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000ae5_BCOUT<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000ae5_BCOUT<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000ae5_BCOUT<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000ae5_BCOUT<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000ae5_BCOUT<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000ae5_BCOUT<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000ae5_BCOUT<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000ae5_BCOUT<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000ae5_BCOUT<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000ae5_BCOUT<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000ae5_BCOUT<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000ae5_BCOUT<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000ae5_BCOUT<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000ae4_CARRYOUT_UNCONNECTED ; + wire \NLW_blk00000003/blk00000ae3_CARRYOUT_UNCONNECTED ; + wire \NLW_blk00000003/blk00000ae3_P<47>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000ae3_P<46>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000ae3_P<45>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000ae3_P<44>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000ae3_P<43>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000ae3_P<42>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000ae3_P<41>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000ae3_P<40>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000ae3_P<39>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000ae3_P<38>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000ae3_P<37>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000ae3_P<36>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000ae3_PCOUT<47>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000ae3_PCOUT<46>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000ae3_PCOUT<45>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000ae3_PCOUT<44>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000ae3_PCOUT<43>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000ae3_PCOUT<42>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000ae3_PCOUT<41>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000ae3_PCOUT<40>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000ae3_PCOUT<39>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000ae3_PCOUT<38>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000ae3_PCOUT<37>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000ae3_PCOUT<36>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000ae3_PCOUT<35>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000ae3_PCOUT<34>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000ae3_PCOUT<33>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000ae3_PCOUT<32>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000ae3_PCOUT<31>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000ae3_PCOUT<30>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000ae3_PCOUT<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000ae3_PCOUT<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000ae3_PCOUT<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000ae3_PCOUT<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000ae3_PCOUT<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000ae3_PCOUT<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000ae3_PCOUT<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000ae3_PCOUT<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000ae3_PCOUT<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000ae3_PCOUT<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000ae3_PCOUT<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000ae3_PCOUT<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000ae3_PCOUT<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000ae3_PCOUT<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000ae3_PCOUT<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000ae3_PCOUT<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000ae3_PCOUT<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000ae3_PCOUT<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000ae3_PCOUT<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000ae3_PCOUT<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000ae3_PCOUT<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000ae3_PCOUT<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000ae3_PCOUT<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000ae3_PCOUT<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000ae3_PCOUT<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000ae3_PCOUT<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000ae3_PCOUT<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000ae3_PCOUT<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000ae3_PCOUT<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000ae3_PCOUT<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000ae3_BCOUT<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000ae3_BCOUT<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000ae3_BCOUT<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000ae3_BCOUT<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000ae3_BCOUT<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000ae3_BCOUT<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000ae3_BCOUT<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000ae3_BCOUT<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000ae3_BCOUT<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000ae3_BCOUT<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000ae3_BCOUT<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000ae3_BCOUT<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000ae3_BCOUT<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000ae3_BCOUT<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000ae3_BCOUT<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000ae3_BCOUT<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000ae3_BCOUT<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000ae3_BCOUT<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000ae2_CARRYOUT_UNCONNECTED ; + wire \NLW_blk00000003/blk000008b3_O_UNCONNECTED ; + wire \NLW_blk00000003/blk00000888_O_UNCONNECTED ; + wire \NLW_blk00000003/blk000003e8_O_UNCONNECTED ; + wire \NLW_blk00000003/blk000003c3_O_UNCONNECTED ; + wire \NLW_blk00000003/blk00000126_CARRYOUT_UNCONNECTED ; + wire \NLW_blk00000003/blk00000126_P<47>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000126_P<46>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000126_P<45>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000126_P<44>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000126_P<43>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000126_P<42>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000126_P<41>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000126_P<40>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000126_P<39>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000126_P<38>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000126_P<37>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000126_P<36>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000126_P<35>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000126_P<34>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000126_P<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000126_P<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000126_P<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000126_P<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000126_P<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000126_P<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000126_P<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000126_P<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000126_P<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000126_P<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000126_P<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000126_P<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000126_P<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000126_P<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000126_P<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000126_PCOUT<47>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000126_PCOUT<46>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000126_PCOUT<45>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000126_PCOUT<44>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000126_PCOUT<43>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000126_PCOUT<42>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000126_PCOUT<41>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000126_PCOUT<40>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000126_PCOUT<39>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000126_PCOUT<38>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000126_PCOUT<37>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000126_PCOUT<36>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000126_PCOUT<35>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000126_PCOUT<34>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000126_PCOUT<33>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000126_PCOUT<32>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000126_PCOUT<31>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000126_PCOUT<30>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000126_PCOUT<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000126_PCOUT<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000126_PCOUT<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000126_PCOUT<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000126_PCOUT<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000126_PCOUT<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000126_PCOUT<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000126_PCOUT<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000126_PCOUT<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000126_PCOUT<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000126_PCOUT<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000126_PCOUT<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000126_PCOUT<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000126_PCOUT<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000126_PCOUT<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000126_PCOUT<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000126_PCOUT<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000126_PCOUT<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000126_PCOUT<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000126_PCOUT<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000126_PCOUT<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000126_PCOUT<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000126_PCOUT<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000126_PCOUT<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000126_PCOUT<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000126_PCOUT<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000126_PCOUT<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000126_PCOUT<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000126_PCOUT<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000126_PCOUT<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000126_BCOUT<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000126_BCOUT<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000126_BCOUT<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000126_BCOUT<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000126_BCOUT<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000126_BCOUT<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000126_BCOUT<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000126_BCOUT<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000126_BCOUT<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000126_BCOUT<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000126_BCOUT<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000126_BCOUT<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000126_BCOUT<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000126_BCOUT<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000126_BCOUT<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000126_BCOUT<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000126_BCOUT<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000126_BCOUT<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000125_CARRYOUT_UNCONNECTED ; + wire \NLW_blk00000003/blk00000125_P<47>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000125_P<46>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000125_P<45>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000125_P<44>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000125_P<43>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000125_P<42>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000125_P<41>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000125_P<40>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000125_P<39>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000125_P<38>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000125_P<37>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000125_P<36>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000125_P<35>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000125_P<34>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000125_P<33>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000125_P<32>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000125_P<31>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000125_P<30>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000125_P<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000125_P<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000125_P<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000125_P<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000125_P<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000125_P<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000125_P<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000125_P<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000125_P<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000125_P<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000125_P<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000125_P<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000125_P<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000125_P<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000125_P<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000125_P<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000125_P<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000125_P<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000125_P<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000125_P<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000125_P<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000125_P<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000125_P<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000125_P<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000125_P<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000125_P<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000125_P<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000125_P<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000125_P<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000125_P<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000125_BCOUT<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000125_BCOUT<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000125_BCOUT<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000125_BCOUT<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000125_BCOUT<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000125_BCOUT<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000125_BCOUT<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000125_BCOUT<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000125_BCOUT<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000125_BCOUT<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000125_BCOUT<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000125_BCOUT<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000125_BCOUT<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000125_BCOUT<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000125_BCOUT<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000125_BCOUT<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000125_BCOUT<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000125_BCOUT<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000124_CARRYOUT_UNCONNECTED ; + wire \NLW_blk00000003/blk00000124_P<47>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000124_P<46>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000124_P<45>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000124_P<44>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000124_P<43>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000124_P<42>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000124_P<41>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000124_P<40>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000124_P<39>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000124_P<38>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000124_P<37>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000124_P<36>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000124_P<35>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000124_P<34>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000124_P<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000124_P<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000124_P<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000124_P<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000124_P<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000124_P<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000124_P<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000124_P<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000124_P<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000124_P<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000124_P<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000124_P<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000124_P<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000124_P<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000124_P<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000124_PCOUT<47>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000124_PCOUT<46>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000124_PCOUT<45>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000124_PCOUT<44>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000124_PCOUT<43>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000124_PCOUT<42>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000124_PCOUT<41>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000124_PCOUT<40>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000124_PCOUT<39>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000124_PCOUT<38>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000124_PCOUT<37>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000124_PCOUT<36>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000124_PCOUT<35>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000124_PCOUT<34>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000124_PCOUT<33>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000124_PCOUT<32>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000124_PCOUT<31>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000124_PCOUT<30>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000124_PCOUT<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000124_PCOUT<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000124_PCOUT<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000124_PCOUT<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000124_PCOUT<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000124_PCOUT<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000124_PCOUT<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000124_PCOUT<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000124_PCOUT<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000124_PCOUT<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000124_PCOUT<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000124_PCOUT<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000124_PCOUT<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000124_PCOUT<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000124_PCOUT<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000124_PCOUT<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000124_PCOUT<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000124_PCOUT<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000124_PCOUT<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000124_PCOUT<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000124_PCOUT<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000124_PCOUT<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000124_PCOUT<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000124_PCOUT<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000124_PCOUT<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000124_PCOUT<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000124_PCOUT<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000124_PCOUT<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000124_PCOUT<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000124_PCOUT<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000124_BCOUT<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000124_BCOUT<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000124_BCOUT<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000124_BCOUT<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000124_BCOUT<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000124_BCOUT<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000124_BCOUT<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000124_BCOUT<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000124_BCOUT<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000124_BCOUT<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000124_BCOUT<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000124_BCOUT<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000124_BCOUT<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000124_BCOUT<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000124_BCOUT<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000124_BCOUT<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000124_BCOUT<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000124_BCOUT<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000123_CARRYOUT_UNCONNECTED ; + wire \NLW_blk00000003/blk00000123_P<47>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000123_P<46>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000123_P<45>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000123_P<44>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000123_P<43>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000123_P<42>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000123_P<41>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000123_P<40>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000123_P<39>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000123_P<38>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000123_P<37>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000123_P<36>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000123_P<35>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000123_P<34>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000123_P<33>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000123_P<32>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000123_P<31>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000123_P<30>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000123_P<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000123_P<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000123_P<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000123_P<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000123_P<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000123_P<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000123_P<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000123_P<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000123_P<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000123_P<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000123_P<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000123_P<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000123_P<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000123_P<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000123_P<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000123_P<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000123_P<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000123_P<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000123_P<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000123_P<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000123_P<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000123_P<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000123_P<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000123_P<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000123_P<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000123_P<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000123_P<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000123_P<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000123_P<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000123_P<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000123_BCOUT<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000123_BCOUT<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000123_BCOUT<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000123_BCOUT<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000123_BCOUT<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000123_BCOUT<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000123_BCOUT<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000123_BCOUT<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000123_BCOUT<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000123_BCOUT<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000123_BCOUT<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000123_BCOUT<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000123_BCOUT<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000123_BCOUT<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000123_BCOUT<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000123_BCOUT<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000123_BCOUT<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk00000123_BCOUT<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000022b/blk00000291_Q_UNCONNECTED ; + wire \NLW_blk00000003/blk0000022b/blk0000028e_Q_UNCONNECTED ; + wire \NLW_blk00000003/blk0000022b/blk0000028b_Q_UNCONNECTED ; + wire \NLW_blk00000003/blk0000022b/blk00000288_Q_UNCONNECTED ; + wire \NLW_blk00000003/blk0000022b/blk00000285_Q_UNCONNECTED ; + wire \NLW_blk00000003/blk0000022b/blk00000282_Q_UNCONNECTED ; + wire \NLW_blk00000003/blk0000022b/blk0000027f_Q_UNCONNECTED ; + wire \NLW_blk00000003/blk0000022b/blk0000027c_Q_UNCONNECTED ; + wire \NLW_blk00000003/blk0000022b/blk00000279_Q_UNCONNECTED ; + wire \NLW_blk00000003/blk0000022b/blk00000276_Q_UNCONNECTED ; + wire \NLW_blk00000003/blk0000022b/blk00000273_Q_UNCONNECTED ; + wire \NLW_blk00000003/blk0000022b/blk00000270_Q_UNCONNECTED ; + wire \NLW_blk00000003/blk0000022b/blk0000026d_Q_UNCONNECTED ; + wire \NLW_blk00000003/blk0000022b/blk0000026a_Q_UNCONNECTED ; + wire \NLW_blk00000003/blk0000022b/blk00000267_Q_UNCONNECTED ; + wire \NLW_blk00000003/blk0000022b/blk00000264_Q_UNCONNECTED ; + wire \NLW_blk00000003/blk0000022b/blk00000261_Q_UNCONNECTED ; + wire \NLW_blk00000003/blk0000022b/blk0000025e_Q_UNCONNECTED ; + wire \NLW_blk00000003/blk0000022b/blk0000025b_Q_UNCONNECTED ; + wire \NLW_blk00000003/blk0000022b/blk00000258_Q_UNCONNECTED ; + wire \NLW_blk00000003/blk0000022b/blk00000255_Q_UNCONNECTED ; + wire \NLW_blk00000003/blk0000022b/blk00000252_Q_UNCONNECTED ; + wire \NLW_blk00000003/blk0000022b/blk0000024f_Q_UNCONNECTED ; + wire \NLW_blk00000003/blk0000022b/blk0000024c_Q_UNCONNECTED ; + wire \NLW_blk00000003/blk0000022b/blk00000249_Q_UNCONNECTED ; + wire \NLW_blk00000003/blk0000022b/blk00000246_Q_UNCONNECTED ; + wire \NLW_blk00000003/blk0000022b/blk00000243_Q_UNCONNECTED ; + wire \NLW_blk00000003/blk0000022b/blk00000240_Q_UNCONNECTED ; + wire \NLW_blk00000003/blk0000022b/blk0000023d_Q_UNCONNECTED ; + wire \NLW_blk00000003/blk0000022b/blk0000023a_Q_UNCONNECTED ; + wire \NLW_blk00000003/blk0000022b/blk00000237_Q_UNCONNECTED ; + wire \NLW_blk00000003/blk0000022b/blk00000234_Q_UNCONNECTED ; + wire \NLW_blk00000003/blk0000022b/blk00000231_Q_UNCONNECTED ; + wire \NLW_blk00000003/blk0000022b/blk0000022e_Q_UNCONNECTED ; + wire \NLW_blk00000003/blk0000038a/blk0000038d_Q_UNCONNECTED ; + wire \NLW_blk00000003/blk00000390/blk00000393_Q_UNCONNECTED ; + wire \NLW_blk00000003/blk0000039b/blk0000039e_Q_UNCONNECTED ; + wire \NLW_blk00000003/blk00000599/blk000005ab_Q_UNCONNECTED ; + wire \NLW_blk00000003/blk00000599/blk000005a8_Q_UNCONNECTED ; + wire \NLW_blk00000003/blk00000599/blk000005a5_Q_UNCONNECTED ; + wire \NLW_blk00000003/blk00000599/blk000005a2_Q_UNCONNECTED ; + wire \NLW_blk00000003/blk00000599/blk0000059f_Q_UNCONNECTED ; + wire \NLW_blk00000003/blk00000599/blk0000059c_Q_UNCONNECTED ; + wire \NLW_blk00000003/blk000005ae/blk000005b1_Q_UNCONNECTED ; + wire \NLW_blk00000003/blk00000832/blk00000838_Q_UNCONNECTED ; + wire \NLW_blk00000003/blk00000832/blk00000835_Q_UNCONNECTED ; + wire \NLW_blk00000003/blk0000083b/blk0000083e_Q_UNCONNECTED ; + wire \NLW_blk00000003/blk00000846/blk00000849_Q_UNCONNECTED ; + wire \NLW_blk00000003/blk0000100a/blk0000100e_DOA<31>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000100a/blk0000100e_DOA<30>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000100a/blk0000100e_DOA<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000100a/blk0000100e_DOA<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000100a/blk0000100e_DOA<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000100a/blk0000100e_DOA<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000100a/blk0000100e_DOA<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000100a/blk0000100e_DOA<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000100a/blk0000100e_DOA<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000100a/blk0000100e_DOA<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000100a/blk0000100e_DOA<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000100a/blk0000100e_DOA<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000100a/blk0000100e_DOA<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000100a/blk0000100e_DOA<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000100a/blk0000100e_DOA<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000100a/blk0000100e_DOA<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000100a/blk0000100e_DOA<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000100a/blk0000100e_DOA<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000100a/blk0000100e_DOA<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000100a/blk0000100e_DOA<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000100a/blk0000100e_DOA<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000100a/blk0000100e_DOA<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000100a/blk0000100e_DOA<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000100a/blk0000100e_DOA<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000100a/blk0000100e_DOA<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000100a/blk0000100e_DOA<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000100a/blk0000100e_DOA<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000100a/blk0000100e_DOA<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000100a/blk0000100e_DOA<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000100a/blk0000100e_DOA<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000100a/blk0000100e_DOA<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000100a/blk0000100e_DOA<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000100a/blk0000100e_DOB<31>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000100a/blk0000100e_DOB<30>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000100a/blk0000100e_DOB<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000100a/blk0000100e_DOB<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000100a/blk0000100e_DOB<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000100a/blk0000100e_DOB<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000100a/blk0000100e_DOB<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000100a/blk0000100e_DOB<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000100a/blk0000100e_DOB<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000100a/blk0000100e_DOB<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000100a/blk0000100e_DOB<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000100a/blk0000100e_DOB<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000100a/blk0000100e_DOB<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000100a/blk0000100e_DOB<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000100a/blk0000100e_DOB<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000100a/blk0000100e_DOB<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000100a/blk0000100e_DOB<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000100a/blk0000100e_DOB<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000100a/blk0000100e_DOB<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000100a/blk0000100e_DOB<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000100a/blk0000100e_DOB<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000100a/blk0000100e_DOB<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000100a/blk0000100e_DOB<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000100a/blk0000100e_DOPA<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000100a/blk0000100e_DOPA<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000100a/blk0000100e_DOPA<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000100a/blk0000100e_DOPA<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000100a/blk0000100e_DOPB<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000100a/blk0000100e_DOPB<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000100a/blk0000100e_DOPB<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000100a/blk0000100d_DOA<31>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000100a/blk0000100d_DOA<30>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000100a/blk0000100d_DOA<29>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000100a/blk0000100d_DOA<28>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000100a/blk0000100d_DOA<27>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000100a/blk0000100d_DOA<26>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000100a/blk0000100d_DOA<25>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000100a/blk0000100d_DOA<24>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000100a/blk0000100d_DOA<23>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000100a/blk0000100d_DOA<22>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000100a/blk0000100d_DOA<21>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000100a/blk0000100d_DOA<20>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000100a/blk0000100d_DOA<19>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000100a/blk0000100d_DOA<18>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000100a/blk0000100d_DOA<17>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000100a/blk0000100d_DOA<16>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000100a/blk0000100d_DOA<15>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000100a/blk0000100d_DOA<14>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000100a/blk0000100d_DOA<13>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000100a/blk0000100d_DOA<12>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000100a/blk0000100d_DOA<11>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000100a/blk0000100d_DOA<10>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000100a/blk0000100d_DOA<9>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000100a/blk0000100d_DOA<8>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000100a/blk0000100d_DOA<7>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000100a/blk0000100d_DOA<6>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000100a/blk0000100d_DOA<5>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000100a/blk0000100d_DOA<4>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000100a/blk0000100d_DOA<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000100a/blk0000100d_DOA<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000100a/blk0000100d_DOA<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000100a/blk0000100d_DOA<0>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000100a/blk0000100d_DOPA<3>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000100a/blk0000100d_DOPA<2>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000100a/blk0000100d_DOPA<1>_UNCONNECTED ; + wire \NLW_blk00000003/blk0000100a/blk0000100d_DOPA<0>_UNCONNECTED ; + wire [15 : 0] xn_re_0; + wire [15 : 0] xn_im_1; + wire [5 : 0] NlwRenamedSig_OI_xn_index; + wire [5 : 0] xk_index_2; + wire [22 : 0] xk_re_3; + wire [22 : 0] xk_im_4; + assign + xn_re_0[15] = xn_re[15], + xn_re_0[14] = xn_re[14], + xn_re_0[13] = xn_re[13], + xn_re_0[12] = xn_re[12], + xn_re_0[11] = xn_re[11], + xn_re_0[10] = xn_re[10], + xn_re_0[9] = xn_re[9], + xn_re_0[8] = xn_re[8], + xn_re_0[7] = xn_re[7], + xn_re_0[6] = xn_re[6], + xn_re_0[5] = xn_re[5], + xn_re_0[4] = xn_re[4], + xn_re_0[3] = xn_re[3], + xn_re_0[2] = xn_re[2], + xn_re_0[1] = xn_re[1], + xn_re_0[0] = xn_re[0], + rfd = NlwRenamedSig_OI_rfd, + xk_im[22] = xk_im_4[22], + xk_im[21] = xk_im_4[21], + xk_im[20] = xk_im_4[20], + xk_im[19] = xk_im_4[19], + xk_im[18] = xk_im_4[18], + xk_im[17] = xk_im_4[17], + xk_im[16] = xk_im_4[16], + xk_im[15] = xk_im_4[15], + xk_im[14] = xk_im_4[14], + xk_im[13] = xk_im_4[13], + xk_im[12] = xk_im_4[12], + xk_im[11] = xk_im_4[11], + xk_im[10] = xk_im_4[10], + xk_im[9] = xk_im_4[9], + xk_im[8] = xk_im_4[8], + xk_im[7] = xk_im_4[7], + xk_im[6] = xk_im_4[6], + xk_im[5] = xk_im_4[5], + xk_im[4] = xk_im_4[4], + xk_im[3] = xk_im_4[3], + xk_im[2] = xk_im_4[2], + xk_im[1] = xk_im_4[1], + xk_im[0] = xk_im_4[0], + xn_index[5] = NlwRenamedSig_OI_xn_index[5], + xn_index[4] = NlwRenamedSig_OI_xn_index[4], + xn_index[3] = NlwRenamedSig_OI_xn_index[3], + xn_index[2] = NlwRenamedSig_OI_xn_index[2], + xn_index[1] = NlwRenamedSig_OI_xn_index[1], + xn_index[0] = NlwRenamedSig_OI_xn_index[0], + xk_re[22] = xk_re_3[22], + xk_re[21] = xk_re_3[21], + xk_re[20] = xk_re_3[20], + xk_re[19] = xk_re_3[19], + xk_re[18] = xk_re_3[18], + xk_re[17] = xk_re_3[17], + xk_re[16] = xk_re_3[16], + xk_re[15] = xk_re_3[15], + xk_re[14] = xk_re_3[14], + xk_re[13] = xk_re_3[13], + xk_re[12] = xk_re_3[12], + xk_re[11] = xk_re_3[11], + xk_re[10] = xk_re_3[10], + xk_re[9] = xk_re_3[9], + xk_re[8] = xk_re_3[8], + xk_re[7] = xk_re_3[7], + xk_re[6] = xk_re_3[6], + xk_re[5] = xk_re_3[5], + xk_re[4] = xk_re_3[4], + xk_re[3] = xk_re_3[3], + xk_re[2] = xk_re_3[2], + xk_re[1] = xk_re_3[1], + xk_re[0] = xk_re_3[0], + xn_im_1[15] = xn_im[15], + xn_im_1[14] = xn_im[14], + xn_im_1[13] = xn_im[13], + xn_im_1[12] = xn_im[12], + xn_im_1[11] = xn_im[11], + xn_im_1[10] = xn_im[10], + xn_im_1[9] = xn_im[9], + xn_im_1[8] = xn_im[8], + xn_im_1[7] = xn_im[7], + xn_im_1[6] = xn_im[6], + xn_im_1[5] = xn_im[5], + xn_im_1[4] = xn_im[4], + xn_im_1[3] = xn_im[3], + xn_im_1[2] = xn_im[2], + xn_im_1[1] = xn_im[1], + xn_im_1[0] = xn_im[0], + xk_index[5] = xk_index_2[5], + xk_index[4] = xk_index_2[4], + xk_index[3] = xk_index_2[3], + xk_index[2] = xk_index_2[2], + xk_index[1] = xk_index_2[1], + xk_index[0] = xk_index_2[0], + edone = NlwRenamedSig_OI_edone; + VCC blk00000001 ( + .P(NLW_blk00000001_P_UNCONNECTED) + ); + GND blk00000002 ( + .G(NLW_blk00000002_G_UNCONNECTED) + ); + FD #( + .INIT ( 1'b0 )) + \blk00000003/blk00001515 ( + .C(clk), + .D(\blk00000003/sig000014f8 ), + .Q(\blk00000003/sig00001469 ) + ); + SRL16 #( + .INIT ( 16'h0000 )) + \blk00000003/blk00001514 ( + .A0(\blk00000003/sig0000005f ), + .A1(\blk00000003/sig0000005f ), + .A2(\blk00000003/sig0000005f ), + .A3(\blk00000003/sig0000005f ), + .CLK(clk), + .D(\blk00000003/sig000012a0 ), + .Q(\blk00000003/sig000014f8 ) + ); + FD #( + .INIT ( 1'b0 )) + \blk00000003/blk00001513 ( + .C(clk), + .D(\blk00000003/sig000014f7 ), + .Q(\blk00000003/sig00001468 ) + ); + SRL16 #( + .INIT ( 16'h0000 )) + \blk00000003/blk00001512 ( + .A0(\blk00000003/sig0000005f ), + .A1(\blk00000003/sig0000005f ), + .A2(\blk00000003/sig0000005f ), + .A3(\blk00000003/sig0000005f ), + .CLK(clk), + .D(\blk00000003/sig000012a2 ), + .Q(\blk00000003/sig000014f7 ) + ); + FD #( + .INIT ( 1'b0 )) + \blk00000003/blk00001511 ( + .C(clk), + .D(\blk00000003/sig000014f6 ), + .Q(\blk00000003/sig0000146a ) + ); + SRL16 #( + .INIT ( 16'h0000 )) + \blk00000003/blk00001510 ( + .A0(\blk00000003/sig0000005f ), + .A1(\blk00000003/sig0000005f ), + .A2(\blk00000003/sig0000005f ), + .A3(\blk00000003/sig0000005f ), + .CLK(clk), + .D(\blk00000003/sig0000129e ), + .Q(\blk00000003/sig000014f6 ) + ); + FD #( + .INIT ( 1'b0 )) + \blk00000003/blk0000150f ( + .C(clk), + .D(\blk00000003/sig000014f5 ), + .Q(\blk00000003/sig00001467 ) + ); + SRL16 #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000150e ( + .A0(\blk00000003/sig0000005f ), + .A1(\blk00000003/sig0000005f ), + .A2(\blk00000003/sig0000005f ), + .A3(\blk00000003/sig0000005f ), + .CLK(clk), + .D(\blk00000003/sig000012a4 ), + .Q(\blk00000003/sig000014f5 ) + ); + FD #( + .INIT ( 1'b0 )) + \blk00000003/blk0000150d ( + .C(clk), + .D(\blk00000003/sig000014f4 ), + .Q(\blk00000003/sig00001466 ) + ); + SRL16 #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000150c ( + .A0(\blk00000003/sig0000005f ), + .A1(\blk00000003/sig0000005f ), + .A2(\blk00000003/sig0000005f ), + .A3(\blk00000003/sig0000005f ), + .CLK(clk), + .D(\blk00000003/sig000012a6 ), + .Q(\blk00000003/sig000014f4 ) + ); + FD #( + .INIT ( 1'b0 )) + \blk00000003/blk0000150b ( + .C(clk), + .D(\blk00000003/sig000014f3 ), + .Q(\blk00000003/sig00001465 ) + ); + SRL16 #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000150a ( + .A0(\blk00000003/sig0000005f ), + .A1(\blk00000003/sig0000005f ), + .A2(\blk00000003/sig0000005f ), + .A3(\blk00000003/sig0000005f ), + .CLK(clk), + .D(\blk00000003/sig000012a8 ), + .Q(\blk00000003/sig000014f3 ) + ); + FD #( + .INIT ( 1'b0 )) + \blk00000003/blk00001509 ( + .C(clk), + .D(\blk00000003/sig000014f2 ), + .Q(\blk00000003/sig00001464 ) + ); + SRL16 #( + .INIT ( 16'h0000 )) + \blk00000003/blk00001508 ( + .A0(\blk00000003/sig0000005f ), + .A1(\blk00000003/sig0000005f ), + .A2(\blk00000003/sig0000005f ), + .A3(\blk00000003/sig0000005f ), + .CLK(clk), + .D(\blk00000003/sig000012aa ), + .Q(\blk00000003/sig000014f2 ) + ); + FD #( + .INIT ( 1'b0 )) + \blk00000003/blk00001507 ( + .C(clk), + .D(\blk00000003/sig000014f1 ), + .Q(\blk00000003/sig00001463 ) + ); + SRL16 #( + .INIT ( 16'h0000 )) + \blk00000003/blk00001506 ( + .A0(\blk00000003/sig0000005f ), + .A1(\blk00000003/sig0000005f ), + .A2(\blk00000003/sig0000005f ), + .A3(\blk00000003/sig0000005f ), + .CLK(clk), + .D(\blk00000003/sig000012ac ), + .Q(\blk00000003/sig000014f1 ) + ); + FD #( + .INIT ( 1'b0 )) + \blk00000003/blk00001505 ( + .C(clk), + .D(\blk00000003/sig000014f0 ), + .Q(\blk00000003/sig00001462 ) + ); + SRL16 #( + .INIT ( 16'h0000 )) + \blk00000003/blk00001504 ( + .A0(\blk00000003/sig0000005f ), + .A1(\blk00000003/sig0000005f ), + .A2(\blk00000003/sig0000005f ), + .A3(\blk00000003/sig0000005f ), + .CLK(clk), + .D(\blk00000003/sig000012ae ), + .Q(\blk00000003/sig000014f0 ) + ); + FD #( + .INIT ( 1'b0 )) + \blk00000003/blk00001503 ( + .C(clk), + .D(\blk00000003/sig000014ef ), + .Q(\blk00000003/sig00001461 ) + ); + SRL16 #( + .INIT ( 16'h0000 )) + \blk00000003/blk00001502 ( + .A0(\blk00000003/sig0000005f ), + .A1(\blk00000003/sig0000005f ), + .A2(\blk00000003/sig0000005f ), + .A3(\blk00000003/sig0000005f ), + .CLK(clk), + .D(\blk00000003/sig000012b0 ), + .Q(\blk00000003/sig000014ef ) + ); + FD #( + .INIT ( 1'b0 )) + \blk00000003/blk00001501 ( + .C(clk), + .D(\blk00000003/sig000014ee ), + .Q(\blk00000003/sig00001460 ) + ); + SRL16 #( + .INIT ( 16'h0000 )) + \blk00000003/blk00001500 ( + .A0(\blk00000003/sig0000005f ), + .A1(\blk00000003/sig0000005f ), + .A2(\blk00000003/sig0000005f ), + .A3(\blk00000003/sig0000005f ), + .CLK(clk), + .D(\blk00000003/sig000012b2 ), + .Q(\blk00000003/sig000014ee ) + ); + FD #( + .INIT ( 1'b0 )) + \blk00000003/blk000014ff ( + .C(clk), + .D(\blk00000003/sig000014ed ), + .Q(\blk00000003/sig0000145f ) + ); + SRL16 #( + .INIT ( 16'h0000 )) + \blk00000003/blk000014fe ( + .A0(\blk00000003/sig0000005f ), + .A1(\blk00000003/sig0000005f ), + .A2(\blk00000003/sig0000005f ), + .A3(\blk00000003/sig0000005f ), + .CLK(clk), + .D(\blk00000003/sig000012b4 ), + .Q(\blk00000003/sig000014ed ) + ); + FD #( + .INIT ( 1'b0 )) + \blk00000003/blk000014fd ( + .C(clk), + .D(\blk00000003/sig000014ec ), + .Q(\blk00000003/sig0000145e ) + ); + SRL16 #( + .INIT ( 16'h0000 )) + \blk00000003/blk000014fc ( + .A0(\blk00000003/sig0000005f ), + .A1(\blk00000003/sig0000005f ), + .A2(\blk00000003/sig0000005f ), + .A3(\blk00000003/sig0000005f ), + .CLK(clk), + .D(\blk00000003/sig000012b6 ), + .Q(\blk00000003/sig000014ec ) + ); + FD #( + .INIT ( 1'b0 )) + \blk00000003/blk000014fb ( + .C(clk), + .D(\blk00000003/sig000014eb ), + .Q(\blk00000003/sig0000145d ) + ); + SRL16 #( + .INIT ( 16'h0000 )) + \blk00000003/blk000014fa ( + .A0(\blk00000003/sig0000005f ), + .A1(\blk00000003/sig0000005f ), + .A2(\blk00000003/sig0000005f ), + .A3(\blk00000003/sig0000005f ), + .CLK(clk), + .D(\blk00000003/sig000012b8 ), + .Q(\blk00000003/sig000014eb ) + ); + FD #( + .INIT ( 1'b0 )) + \blk00000003/blk000014f9 ( + .C(clk), + .D(\blk00000003/sig000014ea ), + .Q(\blk00000003/sig0000145c ) + ); + SRL16 #( + .INIT ( 16'h0000 )) + \blk00000003/blk000014f8 ( + .A0(\blk00000003/sig0000005f ), + .A1(\blk00000003/sig0000005f ), + .A2(\blk00000003/sig0000005f ), + .A3(\blk00000003/sig0000005f ), + .CLK(clk), + .D(\blk00000003/sig000012ba ), + .Q(\blk00000003/sig000014ea ) + ); + FD #( + .INIT ( 1'b0 )) + \blk00000003/blk000014f7 ( + .C(clk), + .D(\blk00000003/sig000014e9 ), + .Q(\blk00000003/sig0000145b ) + ); + SRL16 #( + .INIT ( 16'h0000 )) + \blk00000003/blk000014f6 ( + .A0(\blk00000003/sig0000005f ), + .A1(\blk00000003/sig0000005f ), + .A2(\blk00000003/sig0000005f ), + .A3(\blk00000003/sig0000005f ), + .CLK(clk), + .D(\blk00000003/sig000012bc ), + .Q(\blk00000003/sig000014e9 ) + ); + FD #( + .INIT ( 1'b0 )) + \blk00000003/blk000014f5 ( + .C(clk), + .D(\blk00000003/sig000014e8 ), + .Q(\blk00000003/sig0000145a ) + ); + SRL16 #( + .INIT ( 16'h0000 )) + \blk00000003/blk000014f4 ( + .A0(\blk00000003/sig0000005f ), + .A1(\blk00000003/sig0000005f ), + .A2(\blk00000003/sig0000005f ), + .A3(\blk00000003/sig0000005f ), + .CLK(clk), + .D(\blk00000003/sig000012be ), + .Q(\blk00000003/sig000014e8 ) + ); + FD #( + .INIT ( 1'b0 )) + \blk00000003/blk000014f3 ( + .C(clk), + .D(\blk00000003/sig000014e7 ), + .Q(\blk00000003/sig00001459 ) + ); + SRL16 #( + .INIT ( 16'h0000 )) + \blk00000003/blk000014f2 ( + .A0(\blk00000003/sig0000005f ), + .A1(\blk00000003/sig0000005f ), + .A2(\blk00000003/sig0000005f ), + .A3(\blk00000003/sig0000005f ), + .CLK(clk), + .D(\blk00000003/sig000012c0 ), + .Q(\blk00000003/sig000014e7 ) + ); + FD #( + .INIT ( 1'b0 )) + \blk00000003/blk000014f1 ( + .C(clk), + .D(\blk00000003/sig000014e6 ), + .Q(\blk00000003/sig00001458 ) + ); + SRL16 #( + .INIT ( 16'h0000 )) + \blk00000003/blk000014f0 ( + .A0(\blk00000003/sig0000005f ), + .A1(\blk00000003/sig0000005f ), + .A2(\blk00000003/sig0000005f ), + .A3(\blk00000003/sig0000005f ), + .CLK(clk), + .D(\blk00000003/sig000012c2 ), + .Q(\blk00000003/sig000014e6 ) + ); + FD #( + .INIT ( 1'b0 )) + \blk00000003/blk000014ef ( + .C(clk), + .D(\blk00000003/sig000014e5 ), + .Q(\blk00000003/sig00001457 ) + ); + SRL16 #( + .INIT ( 16'h0000 )) + \blk00000003/blk000014ee ( + .A0(\blk00000003/sig0000005f ), + .A1(\blk00000003/sig0000005f ), + .A2(\blk00000003/sig0000005f ), + .A3(\blk00000003/sig0000005f ), + .CLK(clk), + .D(\blk00000003/sig000012c4 ), + .Q(\blk00000003/sig000014e5 ) + ); + FD #( + .INIT ( 1'b0 )) + \blk00000003/blk000014ed ( + .C(clk), + .D(\blk00000003/sig000014e4 ), + .Q(\blk00000003/sig00001456 ) + ); + SRL16 #( + .INIT ( 16'h0000 )) + \blk00000003/blk000014ec ( + .A0(\blk00000003/sig0000005f ), + .A1(\blk00000003/sig0000005f ), + .A2(\blk00000003/sig0000005f ), + .A3(\blk00000003/sig0000005f ), + .CLK(clk), + .D(\blk00000003/sig000012c6 ), + .Q(\blk00000003/sig000014e4 ) + ); + FD #( + .INIT ( 1'b0 )) + \blk00000003/blk000014eb ( + .C(clk), + .D(\blk00000003/sig000014e3 ), + .Q(\blk00000003/sig00001455 ) + ); + SRL16 #( + .INIT ( 16'h0000 )) + \blk00000003/blk000014ea ( + .A0(\blk00000003/sig0000005f ), + .A1(\blk00000003/sig0000005f ), + .A2(\blk00000003/sig0000005f ), + .A3(\blk00000003/sig0000005f ), + .CLK(clk), + .D(\blk00000003/sig000012c8 ), + .Q(\blk00000003/sig000014e3 ) + ); + FD #( + .INIT ( 1'b0 )) + \blk00000003/blk000014e9 ( + .C(clk), + .D(\blk00000003/sig000014e2 ), + .Q(\blk00000003/sig00001454 ) + ); + SRL16 #( + .INIT ( 16'h0000 )) + \blk00000003/blk000014e8 ( + .A0(\blk00000003/sig0000005f ), + .A1(\blk00000003/sig0000005f ), + .A2(\blk00000003/sig0000005f ), + .A3(\blk00000003/sig0000005f ), + .CLK(clk), + .D(\blk00000003/sig000012ca ), + .Q(\blk00000003/sig000014e2 ) + ); + FD #( + .INIT ( 1'b0 )) + \blk00000003/blk000014e7 ( + .C(clk), + .D(\blk00000003/sig000014e1 ), + .Q(\blk00000003/sig00001453 ) + ); + SRL16 #( + .INIT ( 16'h0000 )) + \blk00000003/blk000014e6 ( + .A0(\blk00000003/sig0000005f ), + .A1(\blk00000003/sig0000005f ), + .A2(\blk00000003/sig0000005f ), + .A3(\blk00000003/sig0000005f ), + .CLK(clk), + .D(\blk00000003/sig00001341 ), + .Q(\blk00000003/sig000014e1 ) + ); + FD #( + .INIT ( 1'b0 )) + \blk00000003/blk000014e5 ( + .C(clk), + .D(\blk00000003/sig000014e0 ), + .Q(\blk00000003/sig00001452 ) + ); + SRL16 #( + .INIT ( 16'h0000 )) + \blk00000003/blk000014e4 ( + .A0(\blk00000003/sig0000005f ), + .A1(\blk00000003/sig0000005f ), + .A2(\blk00000003/sig0000005f ), + .A3(\blk00000003/sig0000005f ), + .CLK(clk), + .D(\blk00000003/sig00001340 ), + .Q(\blk00000003/sig000014e0 ) + ); + FD #( + .INIT ( 1'b0 )) + \blk00000003/blk000014e3 ( + .C(clk), + .D(\blk00000003/sig000014df ), + .Q(\blk00000003/sig00001451 ) + ); + SRL16 #( + .INIT ( 16'h0000 )) + \blk00000003/blk000014e2 ( + .A0(\blk00000003/sig0000005f ), + .A1(\blk00000003/sig0000005f ), + .A2(\blk00000003/sig0000005f ), + .A3(\blk00000003/sig0000005f ), + .CLK(clk), + .D(\blk00000003/sig0000133f ), + .Q(\blk00000003/sig000014df ) + ); + FD #( + .INIT ( 1'b0 )) + \blk00000003/blk000014e1 ( + .C(clk), + .D(\blk00000003/sig000014de ), + .Q(\blk00000003/sig00001450 ) + ); + SRL16 #( + .INIT ( 16'h0000 )) + \blk00000003/blk000014e0 ( + .A0(\blk00000003/sig0000005f ), + .A1(\blk00000003/sig0000005f ), + .A2(\blk00000003/sig0000005f ), + .A3(\blk00000003/sig0000005f ), + .CLK(clk), + .D(\blk00000003/sig0000133e ), + .Q(\blk00000003/sig000014de ) + ); + FD #( + .INIT ( 1'b0 )) + \blk00000003/blk000014df ( + .C(clk), + .D(\blk00000003/sig000014dd ), + .Q(\blk00000003/sig0000144f ) + ); + SRL16 #( + .INIT ( 16'h0000 )) + \blk00000003/blk000014de ( + .A0(\blk00000003/sig0000005f ), + .A1(\blk00000003/sig0000005f ), + .A2(\blk00000003/sig0000005f ), + .A3(\blk00000003/sig0000005f ), + .CLK(clk), + .D(\blk00000003/sig0000133d ), + .Q(\blk00000003/sig000014dd ) + ); + FD #( + .INIT ( 1'b0 )) + \blk00000003/blk000014dd ( + .C(clk), + .D(\blk00000003/sig000014dc ), + .Q(\blk00000003/sig0000144e ) + ); + SRL16 #( + .INIT ( 16'h0000 )) + \blk00000003/blk000014dc ( + .A0(\blk00000003/sig0000005f ), + .A1(\blk00000003/sig0000005f ), + .A2(\blk00000003/sig0000005f ), + .A3(\blk00000003/sig0000005f ), + .CLK(clk), + .D(\blk00000003/sig0000133c ), + .Q(\blk00000003/sig000014dc ) + ); + FD #( + .INIT ( 1'b0 )) + \blk00000003/blk000014db ( + .C(clk), + .D(\blk00000003/sig000014db ), + .Q(\blk00000003/sig0000144d ) + ); + SRL16 #( + .INIT ( 16'h0000 )) + \blk00000003/blk000014da ( + .A0(\blk00000003/sig0000005f ), + .A1(\blk00000003/sig0000005f ), + .A2(\blk00000003/sig0000005f ), + .A3(\blk00000003/sig0000005f ), + .CLK(clk), + .D(\blk00000003/sig0000133b ), + .Q(\blk00000003/sig000014db ) + ); + FD #( + .INIT ( 1'b0 )) + \blk00000003/blk000014d9 ( + .C(clk), + .D(\blk00000003/sig000014da ), + .Q(\blk00000003/sig0000144c ) + ); + SRL16 #( + .INIT ( 16'h0000 )) + \blk00000003/blk000014d8 ( + .A0(\blk00000003/sig0000005f ), + .A1(\blk00000003/sig0000005f ), + .A2(\blk00000003/sig0000005f ), + .A3(\blk00000003/sig0000005f ), + .CLK(clk), + .D(\blk00000003/sig0000133a ), + .Q(\blk00000003/sig000014da ) + ); + FD #( + .INIT ( 1'b0 )) + \blk00000003/blk000014d7 ( + .C(clk), + .D(\blk00000003/sig000014d9 ), + .Q(\blk00000003/sig0000144a ) + ); + SRL16 #( + .INIT ( 16'h0000 )) + \blk00000003/blk000014d6 ( + .A0(\blk00000003/sig0000005f ), + .A1(\blk00000003/sig0000005f ), + .A2(\blk00000003/sig0000005f ), + .A3(\blk00000003/sig0000005f ), + .CLK(clk), + .D(\blk00000003/sig00001338 ), + .Q(\blk00000003/sig000014d9 ) + ); + FD #( + .INIT ( 1'b0 )) + \blk00000003/blk000014d5 ( + .C(clk), + .D(\blk00000003/sig000014d8 ), + .Q(\blk00000003/sig00001449 ) + ); + SRL16 #( + .INIT ( 16'h0000 )) + \blk00000003/blk000014d4 ( + .A0(\blk00000003/sig0000005f ), + .A1(\blk00000003/sig0000005f ), + .A2(\blk00000003/sig0000005f ), + .A3(\blk00000003/sig0000005f ), + .CLK(clk), + .D(\blk00000003/sig00001337 ), + .Q(\blk00000003/sig000014d8 ) + ); + FD #( + .INIT ( 1'b0 )) + \blk00000003/blk000014d3 ( + .C(clk), + .D(\blk00000003/sig000014d7 ), + .Q(\blk00000003/sig0000144b ) + ); + SRL16 #( + .INIT ( 16'h0000 )) + \blk00000003/blk000014d2 ( + .A0(\blk00000003/sig0000005f ), + .A1(\blk00000003/sig0000005f ), + .A2(\blk00000003/sig0000005f ), + .A3(\blk00000003/sig0000005f ), + .CLK(clk), + .D(\blk00000003/sig00001339 ), + .Q(\blk00000003/sig000014d7 ) + ); + FD #( + .INIT ( 1'b0 )) + \blk00000003/blk000014d1 ( + .C(clk), + .D(\blk00000003/sig000014d6 ), + .Q(\blk00000003/sig00001448 ) + ); + SRL16 #( + .INIT ( 16'h0000 )) + \blk00000003/blk000014d0 ( + .A0(\blk00000003/sig0000005f ), + .A1(\blk00000003/sig0000005f ), + .A2(\blk00000003/sig0000005f ), + .A3(\blk00000003/sig0000005f ), + .CLK(clk), + .D(\blk00000003/sig00001336 ), + .Q(\blk00000003/sig000014d6 ) + ); + FD #( + .INIT ( 1'b0 )) + \blk00000003/blk000014cf ( + .C(clk), + .D(\blk00000003/sig000014d5 ), + .Q(\blk00000003/sig00001447 ) + ); + SRL16 #( + .INIT ( 16'h0000 )) + \blk00000003/blk000014ce ( + .A0(\blk00000003/sig0000005f ), + .A1(\blk00000003/sig0000005f ), + .A2(\blk00000003/sig0000005f ), + .A3(\blk00000003/sig0000005f ), + .CLK(clk), + .D(\blk00000003/sig00001335 ), + .Q(\blk00000003/sig000014d5 ) + ); + FD #( + .INIT ( 1'b0 )) + \blk00000003/blk000014cd ( + .C(clk), + .D(\blk00000003/sig000014d4 ), + .Q(\blk00000003/sig00001446 ) + ); + SRL16 #( + .INIT ( 16'h0000 )) + \blk00000003/blk000014cc ( + .A0(\blk00000003/sig0000005f ), + .A1(\blk00000003/sig0000005f ), + .A2(\blk00000003/sig0000005f ), + .A3(\blk00000003/sig0000005f ), + .CLK(clk), + .D(\blk00000003/sig00001334 ), + .Q(\blk00000003/sig000014d4 ) + ); + FD #( + .INIT ( 1'b0 )) + \blk00000003/blk000014cb ( + .C(clk), + .D(\blk00000003/sig000014d3 ), + .Q(\blk00000003/sig00001445 ) + ); + SRL16 #( + .INIT ( 16'h0000 )) + \blk00000003/blk000014ca ( + .A0(\blk00000003/sig0000005f ), + .A1(\blk00000003/sig0000005f ), + .A2(\blk00000003/sig0000005f ), + .A3(\blk00000003/sig0000005f ), + .CLK(clk), + .D(\blk00000003/sig00001333 ), + .Q(\blk00000003/sig000014d3 ) + ); + FD #( + .INIT ( 1'b0 )) + \blk00000003/blk000014c9 ( + .C(clk), + .D(\blk00000003/sig000014d2 ), + .Q(\blk00000003/sig00001444 ) + ); + SRL16 #( + .INIT ( 16'h0000 )) + \blk00000003/blk000014c8 ( + .A0(\blk00000003/sig0000005f ), + .A1(\blk00000003/sig0000005f ), + .A2(\blk00000003/sig0000005f ), + .A3(\blk00000003/sig0000005f ), + .CLK(clk), + .D(\blk00000003/sig00001332 ), + .Q(\blk00000003/sig000014d2 ) + ); + FD #( + .INIT ( 1'b0 )) + \blk00000003/blk000014c7 ( + .C(clk), + .D(\blk00000003/sig000014d1 ), + .Q(\blk00000003/sig00001443 ) + ); + SRL16 #( + .INIT ( 16'h0000 )) + \blk00000003/blk000014c6 ( + .A0(\blk00000003/sig0000005f ), + .A1(\blk00000003/sig0000005f ), + .A2(\blk00000003/sig0000005f ), + .A3(\blk00000003/sig0000005f ), + .CLK(clk), + .D(\blk00000003/sig00001331 ), + .Q(\blk00000003/sig000014d1 ) + ); + FD #( + .INIT ( 1'b0 )) + \blk00000003/blk000014c5 ( + .C(clk), + .D(\blk00000003/sig000014d0 ), + .Q(\blk00000003/sig00001442 ) + ); + SRL16 #( + .INIT ( 16'h0000 )) + \blk00000003/blk000014c4 ( + .A0(\blk00000003/sig0000005f ), + .A1(\blk00000003/sig0000005f ), + .A2(\blk00000003/sig0000005f ), + .A3(\blk00000003/sig0000005f ), + .CLK(clk), + .D(\blk00000003/sig00001330 ), + .Q(\blk00000003/sig000014d0 ) + ); + FD #( + .INIT ( 1'b0 )) + \blk00000003/blk000014c3 ( + .C(clk), + .D(\blk00000003/sig000014cf ), + .Q(\blk00000003/sig00001441 ) + ); + SRL16 #( + .INIT ( 16'h0000 )) + \blk00000003/blk000014c2 ( + .A0(\blk00000003/sig0000005f ), + .A1(\blk00000003/sig0000005f ), + .A2(\blk00000003/sig0000005f ), + .A3(\blk00000003/sig0000005f ), + .CLK(clk), + .D(\blk00000003/sig0000132f ), + .Q(\blk00000003/sig000014cf ) + ); + FD #( + .INIT ( 1'b0 )) + \blk00000003/blk000014c1 ( + .C(clk), + .D(\blk00000003/sig000014ce ), + .Q(\blk00000003/sig00001440 ) + ); + SRL16 #( + .INIT ( 16'h0000 )) + \blk00000003/blk000014c0 ( + .A0(\blk00000003/sig0000005f ), + .A1(\blk00000003/sig0000005f ), + .A2(\blk00000003/sig0000005f ), + .A3(\blk00000003/sig0000005f ), + .CLK(clk), + .D(\blk00000003/sig0000132e ), + .Q(\blk00000003/sig000014ce ) + ); + FD #( + .INIT ( 1'b0 )) + \blk00000003/blk000014bf ( + .C(clk), + .D(\blk00000003/sig000014cd ), + .Q(\blk00000003/sig0000143f ) + ); + SRL16 #( + .INIT ( 16'h0000 )) + \blk00000003/blk000014be ( + .A0(\blk00000003/sig0000005f ), + .A1(\blk00000003/sig0000005f ), + .A2(\blk00000003/sig0000005f ), + .A3(\blk00000003/sig0000005f ), + .CLK(clk), + .D(\blk00000003/sig0000132d ), + .Q(\blk00000003/sig000014cd ) + ); + FD #( + .INIT ( 1'b0 )) + \blk00000003/blk000014bd ( + .C(clk), + .D(\blk00000003/sig000014cc ), + .Q(\blk00000003/sig0000143e ) + ); + SRL16 #( + .INIT ( 16'h0000 )) + \blk00000003/blk000014bc ( + .A0(\blk00000003/sig0000005f ), + .A1(\blk00000003/sig0000005f ), + .A2(\blk00000003/sig0000005f ), + .A3(\blk00000003/sig0000005f ), + .CLK(clk), + .D(\blk00000003/sig0000132c ), + .Q(\blk00000003/sig000014cc ) + ); + FD #( + .INIT ( 1'b0 )) + \blk00000003/blk000014bb ( + .C(clk), + .D(\blk00000003/sig000014cb ), + .Q(\blk00000003/sig0000143d ) + ); + SRL16 #( + .INIT ( 16'h0000 )) + \blk00000003/blk000014ba ( + .A0(\blk00000003/sig0000005f ), + .A1(\blk00000003/sig0000005f ), + .A2(\blk00000003/sig0000005f ), + .A3(\blk00000003/sig0000005f ), + .CLK(clk), + .D(\blk00000003/sig0000132b ), + .Q(\blk00000003/sig000014cb ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000014b9 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig000014ca ), + .Q(\blk00000003/sig00000f41 ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000014b8 ( + .A0(\blk00000003/sig0000005f ), + .A1(\blk00000003/sig00000065 ), + .A2(\blk00000003/sig0000005f ), + .A3(\blk00000003/sig0000005f ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(\blk00000003/sig00000cb7 ), + .Q(\blk00000003/sig000014ca ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000014b7 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig000014c9 ), + .Q(\blk00000003/sig00000f40 ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000014b6 ( + .A0(\blk00000003/sig0000005f ), + .A1(\blk00000003/sig00000065 ), + .A2(\blk00000003/sig0000005f ), + .A3(\blk00000003/sig0000005f ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(\blk00000003/sig00000cb6 ), + .Q(\blk00000003/sig000014c9 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000014b5 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig000014c8 ), + .Q(\blk00000003/sig00000f3f ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000014b4 ( + .A0(\blk00000003/sig0000005f ), + .A1(\blk00000003/sig00000065 ), + .A2(\blk00000003/sig0000005f ), + .A3(\blk00000003/sig0000005f ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(\blk00000003/sig00000cb5 ), + .Q(\blk00000003/sig000014c8 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000014b3 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig000014c7 ), + .Q(\blk00000003/sig00000f3e ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000014b2 ( + .A0(\blk00000003/sig0000005f ), + .A1(\blk00000003/sig00000065 ), + .A2(\blk00000003/sig0000005f ), + .A3(\blk00000003/sig0000005f ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(\blk00000003/sig00000cb4 ), + .Q(\blk00000003/sig000014c7 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000014b1 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig000014c6 ), + .Q(\blk00000003/sig00000f3d ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000014b0 ( + .A0(\blk00000003/sig0000005f ), + .A1(\blk00000003/sig00000065 ), + .A2(\blk00000003/sig0000005f ), + .A3(\blk00000003/sig0000005f ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(\blk00000003/sig00000cb3 ), + .Q(\blk00000003/sig000014c6 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000014af ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig000014c5 ), + .Q(\blk00000003/sig00000f3c ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000014ae ( + .A0(\blk00000003/sig0000005f ), + .A1(\blk00000003/sig00000065 ), + .A2(\blk00000003/sig0000005f ), + .A3(\blk00000003/sig0000005f ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(\blk00000003/sig00000cb2 ), + .Q(\blk00000003/sig000014c5 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000014ad ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig000014c4 ), + .Q(\blk00000003/sig00000f3b ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000014ac ( + .A0(\blk00000003/sig0000005f ), + .A1(\blk00000003/sig00000065 ), + .A2(\blk00000003/sig0000005f ), + .A3(\blk00000003/sig0000005f ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(\blk00000003/sig00000cb1 ), + .Q(\blk00000003/sig000014c4 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000014ab ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig000014c3 ), + .Q(\blk00000003/sig00000f3a ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000014aa ( + .A0(\blk00000003/sig0000005f ), + .A1(\blk00000003/sig00000065 ), + .A2(\blk00000003/sig0000005f ), + .A3(\blk00000003/sig0000005f ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(\blk00000003/sig00000cb0 ), + .Q(\blk00000003/sig000014c3 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000014a9 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig000014c2 ), + .Q(\blk00000003/sig00000f39 ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000014a8 ( + .A0(\blk00000003/sig0000005f ), + .A1(\blk00000003/sig00000065 ), + .A2(\blk00000003/sig0000005f ), + .A3(\blk00000003/sig0000005f ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(\blk00000003/sig00000caf ), + .Q(\blk00000003/sig000014c2 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000014a7 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig000014c1 ), + .Q(\blk00000003/sig00000f38 ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000014a6 ( + .A0(\blk00000003/sig0000005f ), + .A1(\blk00000003/sig00000065 ), + .A2(\blk00000003/sig0000005f ), + .A3(\blk00000003/sig0000005f ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(\blk00000003/sig00000cae ), + .Q(\blk00000003/sig000014c1 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000014a5 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig000014c0 ), + .Q(\blk00000003/sig00000f37 ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000014a4 ( + .A0(\blk00000003/sig0000005f ), + .A1(\blk00000003/sig00000065 ), + .A2(\blk00000003/sig0000005f ), + .A3(\blk00000003/sig0000005f ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(\blk00000003/sig00000cad ), + .Q(\blk00000003/sig000014c0 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000014a3 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig000014bf ), + .Q(\blk00000003/sig00000f36 ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000014a2 ( + .A0(\blk00000003/sig0000005f ), + .A1(\blk00000003/sig00000065 ), + .A2(\blk00000003/sig0000005f ), + .A3(\blk00000003/sig0000005f ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(\blk00000003/sig00000cac ), + .Q(\blk00000003/sig000014bf ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000014a1 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig000014be ), + .Q(\blk00000003/sig00000f35 ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000014a0 ( + .A0(\blk00000003/sig0000005f ), + .A1(\blk00000003/sig00000065 ), + .A2(\blk00000003/sig0000005f ), + .A3(\blk00000003/sig0000005f ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(\blk00000003/sig00000cab ), + .Q(\blk00000003/sig000014be ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000149f ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig000014bd ), + .Q(\blk00000003/sig00000f34 ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000149e ( + .A0(\blk00000003/sig0000005f ), + .A1(\blk00000003/sig00000065 ), + .A2(\blk00000003/sig0000005f ), + .A3(\blk00000003/sig0000005f ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(\blk00000003/sig00000caa ), + .Q(\blk00000003/sig000014bd ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000149d ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig000014bc ), + .Q(\blk00000003/sig00000f33 ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000149c ( + .A0(\blk00000003/sig0000005f ), + .A1(\blk00000003/sig00000065 ), + .A2(\blk00000003/sig0000005f ), + .A3(\blk00000003/sig0000005f ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(\blk00000003/sig00000ca9 ), + .Q(\blk00000003/sig000014bc ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000149b ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig000014bb ), + .Q(\blk00000003/sig00000f31 ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000149a ( + .A0(\blk00000003/sig0000005f ), + .A1(\blk00000003/sig00000065 ), + .A2(\blk00000003/sig0000005f ), + .A3(\blk00000003/sig0000005f ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(\blk00000003/sig00000ca8 ), + .Q(\blk00000003/sig000014bb ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00001499 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig000014ba ), + .Q(\blk00000003/sig00000bbf ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00001498 ( + .A0(\blk00000003/sig0000005f ), + .A1(\blk00000003/sig00000065 ), + .A2(\blk00000003/sig0000005f ), + .A3(\blk00000003/sig0000005f ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(\blk00000003/sig00000ca5 ), + .Q(\blk00000003/sig000014ba ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00001497 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig000014b9 ), + .Q(\blk00000003/sig00000bbe ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00001496 ( + .A0(\blk00000003/sig0000005f ), + .A1(\blk00000003/sig00000065 ), + .A2(\blk00000003/sig0000005f ), + .A3(\blk00000003/sig0000005f ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(\blk00000003/sig00000ca4 ), + .Q(\blk00000003/sig000014b9 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00001495 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig000014b8 ), + .Q(\blk00000003/sig00000bc0 ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00001494 ( + .A0(\blk00000003/sig0000005f ), + .A1(\blk00000003/sig00000065 ), + .A2(\blk00000003/sig0000005f ), + .A3(\blk00000003/sig0000005f ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(\blk00000003/sig00000ca6 ), + .Q(\blk00000003/sig000014b8 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00001493 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig000014b7 ), + .Q(\blk00000003/sig00000bbd ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00001492 ( + .A0(\blk00000003/sig0000005f ), + .A1(\blk00000003/sig00000065 ), + .A2(\blk00000003/sig0000005f ), + .A3(\blk00000003/sig0000005f ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(\blk00000003/sig00000ca3 ), + .Q(\blk00000003/sig000014b7 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00001491 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig000014b6 ), + .Q(\blk00000003/sig00000bbc ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00001490 ( + .A0(\blk00000003/sig0000005f ), + .A1(\blk00000003/sig00000065 ), + .A2(\blk00000003/sig0000005f ), + .A3(\blk00000003/sig0000005f ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(\blk00000003/sig00000ca2 ), + .Q(\blk00000003/sig000014b6 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000148f ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig000014b5 ), + .Q(\blk00000003/sig00000bbb ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000148e ( + .A0(\blk00000003/sig0000005f ), + .A1(\blk00000003/sig00000065 ), + .A2(\blk00000003/sig0000005f ), + .A3(\blk00000003/sig0000005f ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(\blk00000003/sig00000ca1 ), + .Q(\blk00000003/sig000014b5 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000148d ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig000014b4 ), + .Q(\blk00000003/sig00000bba ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000148c ( + .A0(\blk00000003/sig0000005f ), + .A1(\blk00000003/sig00000065 ), + .A2(\blk00000003/sig0000005f ), + .A3(\blk00000003/sig0000005f ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(\blk00000003/sig00000ca0 ), + .Q(\blk00000003/sig000014b4 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000148b ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig000014b3 ), + .Q(\blk00000003/sig00000bb9 ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000148a ( + .A0(\blk00000003/sig0000005f ), + .A1(\blk00000003/sig00000065 ), + .A2(\blk00000003/sig0000005f ), + .A3(\blk00000003/sig0000005f ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(\blk00000003/sig00000c9f ), + .Q(\blk00000003/sig000014b3 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00001489 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig000014b2 ), + .Q(\blk00000003/sig00000bb8 ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00001488 ( + .A0(\blk00000003/sig0000005f ), + .A1(\blk00000003/sig00000065 ), + .A2(\blk00000003/sig0000005f ), + .A3(\blk00000003/sig0000005f ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(\blk00000003/sig00000c9e ), + .Q(\blk00000003/sig000014b2 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00001487 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig000014b1 ), + .Q(\blk00000003/sig00000bb7 ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00001486 ( + .A0(\blk00000003/sig0000005f ), + .A1(\blk00000003/sig00000065 ), + .A2(\blk00000003/sig0000005f ), + .A3(\blk00000003/sig0000005f ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(\blk00000003/sig00000c9d ), + .Q(\blk00000003/sig000014b1 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00001485 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig000014b0 ), + .Q(\blk00000003/sig00000bb6 ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00001484 ( + .A0(\blk00000003/sig0000005f ), + .A1(\blk00000003/sig00000065 ), + .A2(\blk00000003/sig0000005f ), + .A3(\blk00000003/sig0000005f ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(\blk00000003/sig00000c9c ), + .Q(\blk00000003/sig000014b0 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00001483 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig000014af ), + .Q(\blk00000003/sig00000bb5 ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00001482 ( + .A0(\blk00000003/sig0000005f ), + .A1(\blk00000003/sig00000065 ), + .A2(\blk00000003/sig0000005f ), + .A3(\blk00000003/sig0000005f ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(\blk00000003/sig00000c9b ), + .Q(\blk00000003/sig000014af ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00001481 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig000014ae ), + .Q(\blk00000003/sig00000bb4 ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00001480 ( + .A0(\blk00000003/sig0000005f ), + .A1(\blk00000003/sig00000065 ), + .A2(\blk00000003/sig0000005f ), + .A3(\blk00000003/sig0000005f ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(\blk00000003/sig00000c9a ), + .Q(\blk00000003/sig000014ae ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000147f ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig000014ad ), + .Q(\blk00000003/sig00000bb3 ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000147e ( + .A0(\blk00000003/sig0000005f ), + .A1(\blk00000003/sig00000065 ), + .A2(\blk00000003/sig0000005f ), + .A3(\blk00000003/sig0000005f ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(\blk00000003/sig00000c99 ), + .Q(\blk00000003/sig000014ad ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000147d ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig000014ac ), + .Q(\blk00000003/sig00000bb2 ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000147c ( + .A0(\blk00000003/sig0000005f ), + .A1(\blk00000003/sig00000065 ), + .A2(\blk00000003/sig0000005f ), + .A3(\blk00000003/sig0000005f ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(\blk00000003/sig00000c98 ), + .Q(\blk00000003/sig000014ac ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000147b ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig000014ab ), + .Q(\blk00000003/sig00000bb0 ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000147a ( + .A0(\blk00000003/sig0000005f ), + .A1(\blk00000003/sig00000065 ), + .A2(\blk00000003/sig0000005f ), + .A3(\blk00000003/sig0000005f ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(\blk00000003/sig00000c96 ), + .Q(\blk00000003/sig000014ab ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00001479 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig000014aa ), + .Q(\blk00000003/sig00000f30 ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00001478 ( + .A0(\blk00000003/sig0000005f ), + .A1(\blk00000003/sig00000065 ), + .A2(\blk00000003/sig0000005f ), + .A3(\blk00000003/sig0000005f ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(\blk00000003/sig00000dfd ), + .Q(\blk00000003/sig000014aa ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00001477 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig000014a9 ), + .Q(\blk00000003/sig00000f2f ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00001476 ( + .A0(\blk00000003/sig0000005f ), + .A1(\blk00000003/sig00000065 ), + .A2(\blk00000003/sig0000005f ), + .A3(\blk00000003/sig0000005f ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(\blk00000003/sig00000dfb ), + .Q(\blk00000003/sig000014a9 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00001475 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig000014a8 ), + .Q(\blk00000003/sig00000f2e ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00001474 ( + .A0(\blk00000003/sig0000005f ), + .A1(\blk00000003/sig00000065 ), + .A2(\blk00000003/sig0000005f ), + .A3(\blk00000003/sig0000005f ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(\blk00000003/sig00000df8 ), + .Q(\blk00000003/sig000014a8 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00001473 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig000014a7 ), + .Q(\blk00000003/sig00000f2d ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00001472 ( + .A0(\blk00000003/sig0000005f ), + .A1(\blk00000003/sig00000065 ), + .A2(\blk00000003/sig0000005f ), + .A3(\blk00000003/sig0000005f ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(\blk00000003/sig00000df5 ), + .Q(\blk00000003/sig000014a7 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00001471 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig000014a6 ), + .Q(\blk00000003/sig00000f2c ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00001470 ( + .A0(\blk00000003/sig0000005f ), + .A1(\blk00000003/sig00000065 ), + .A2(\blk00000003/sig0000005f ), + .A3(\blk00000003/sig0000005f ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(\blk00000003/sig00000df2 ), + .Q(\blk00000003/sig000014a6 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000146f ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig000014a5 ), + .Q(\blk00000003/sig00000f2b ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000146e ( + .A0(\blk00000003/sig0000005f ), + .A1(\blk00000003/sig00000065 ), + .A2(\blk00000003/sig0000005f ), + .A3(\blk00000003/sig0000005f ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(\blk00000003/sig00000def ), + .Q(\blk00000003/sig000014a5 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000146d ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig000014a4 ), + .Q(\blk00000003/sig00000f2a ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000146c ( + .A0(\blk00000003/sig0000005f ), + .A1(\blk00000003/sig00000065 ), + .A2(\blk00000003/sig0000005f ), + .A3(\blk00000003/sig0000005f ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(\blk00000003/sig00000dec ), + .Q(\blk00000003/sig000014a4 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000146b ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig000014a3 ), + .Q(\blk00000003/sig00000f29 ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000146a ( + .A0(\blk00000003/sig0000005f ), + .A1(\blk00000003/sig00000065 ), + .A2(\blk00000003/sig0000005f ), + .A3(\blk00000003/sig0000005f ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(\blk00000003/sig00000de9 ), + .Q(\blk00000003/sig000014a3 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00001469 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig000014a2 ), + .Q(\blk00000003/sig00000f28 ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00001468 ( + .A0(\blk00000003/sig0000005f ), + .A1(\blk00000003/sig00000065 ), + .A2(\blk00000003/sig0000005f ), + .A3(\blk00000003/sig0000005f ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(\blk00000003/sig00000de6 ), + .Q(\blk00000003/sig000014a2 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00001467 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig000014a1 ), + .Q(\blk00000003/sig00000f27 ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00001466 ( + .A0(\blk00000003/sig0000005f ), + .A1(\blk00000003/sig00000065 ), + .A2(\blk00000003/sig0000005f ), + .A3(\blk00000003/sig0000005f ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(\blk00000003/sig00000de3 ), + .Q(\blk00000003/sig000014a1 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00001465 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig000014a0 ), + .Q(\blk00000003/sig00000f26 ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00001464 ( + .A0(\blk00000003/sig0000005f ), + .A1(\blk00000003/sig00000065 ), + .A2(\blk00000003/sig0000005f ), + .A3(\blk00000003/sig0000005f ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(\blk00000003/sig00000de0 ), + .Q(\blk00000003/sig000014a0 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00001463 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig0000149f ), + .Q(\blk00000003/sig00000f25 ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00001462 ( + .A0(\blk00000003/sig0000005f ), + .A1(\blk00000003/sig00000065 ), + .A2(\blk00000003/sig0000005f ), + .A3(\blk00000003/sig0000005f ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(\blk00000003/sig00000ddd ), + .Q(\blk00000003/sig0000149f ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00001461 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig0000149e ), + .Q(\blk00000003/sig00000f24 ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00001460 ( + .A0(\blk00000003/sig0000005f ), + .A1(\blk00000003/sig00000065 ), + .A2(\blk00000003/sig0000005f ), + .A3(\blk00000003/sig0000005f ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(\blk00000003/sig00000dda ), + .Q(\blk00000003/sig0000149e ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000145f ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig0000149d ), + .Q(\blk00000003/sig00000f23 ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000145e ( + .A0(\blk00000003/sig0000005f ), + .A1(\blk00000003/sig00000065 ), + .A2(\blk00000003/sig0000005f ), + .A3(\blk00000003/sig0000005f ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(\blk00000003/sig00000dd7 ), + .Q(\blk00000003/sig0000149d ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000145d ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig0000149c ), + .Q(\blk00000003/sig00000f22 ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000145c ( + .A0(\blk00000003/sig0000005f ), + .A1(\blk00000003/sig00000065 ), + .A2(\blk00000003/sig0000005f ), + .A3(\blk00000003/sig0000005f ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(\blk00000003/sig00000dd4 ), + .Q(\blk00000003/sig0000149c ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000145b ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig0000149b ), + .Q(\blk00000003/sig00000f20 ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000145a ( + .A0(\blk00000003/sig00000065 ), + .A1(\blk00000003/sig0000005f ), + .A2(\blk00000003/sig0000005f ), + .A3(\blk00000003/sig0000005f ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(\blk00000003/sig00000e03 ), + .Q(\blk00000003/sig0000149b ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00001459 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig0000149a ), + .Q(\blk00000003/sig00000f9a ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00001458 ( + .A0(\blk00000003/sig00000065 ), + .A1(\blk00000003/sig0000005f ), + .A2(\blk00000003/sig0000005f ), + .A3(\blk00000003/sig0000005f ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(\blk00000003/sig00000e02 ), + .Q(\blk00000003/sig0000149a ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00001457 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig00001499 ), + .Q(\blk00000003/sig00000f21 ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00001456 ( + .A0(\blk00000003/sig0000005f ), + .A1(\blk00000003/sig00000065 ), + .A2(\blk00000003/sig0000005f ), + .A3(\blk00000003/sig0000005f ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(\blk00000003/sig00000dd1 ), + .Q(\blk00000003/sig00001499 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00001455 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig00001498 ), + .Q(\blk00000003/sig00000f99 ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00001454 ( + .A0(\blk00000003/sig00000065 ), + .A1(\blk00000003/sig0000005f ), + .A2(\blk00000003/sig0000005f ), + .A3(\blk00000003/sig0000005f ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(\blk00000003/sig00000e01 ), + .Q(\blk00000003/sig00001498 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00001453 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig00001497 ), + .Q(\blk00000003/sig00000f98 ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00001452 ( + .A0(\blk00000003/sig00000065 ), + .A1(\blk00000003/sig0000005f ), + .A2(\blk00000003/sig0000005f ), + .A3(\blk00000003/sig0000005f ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(\blk00000003/sig00000e00 ), + .Q(\blk00000003/sig00001497 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00001451 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig00001496 ), + .Q(\blk00000003/sig00000f97 ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00001450 ( + .A0(\blk00000003/sig00000065 ), + .A1(\blk00000003/sig0000005f ), + .A2(\blk00000003/sig0000005f ), + .A3(\blk00000003/sig0000005f ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(\blk00000003/sig00000dff ), + .Q(\blk00000003/sig00001496 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000144f ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig00001495 ), + .Q(\blk00000003/sig00000f96 ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000144e ( + .A0(\blk00000003/sig00000065 ), + .A1(\blk00000003/sig0000005f ), + .A2(\blk00000003/sig0000005f ), + .A3(\blk00000003/sig0000005f ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(\blk00000003/sig00000dfe ), + .Q(\blk00000003/sig00001495 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000144d ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig00001494 ), + .Q(\blk00000003/sig00000baf ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000144c ( + .A0(\blk00000003/sig0000005f ), + .A1(\blk00000003/sig00000065 ), + .A2(\blk00000003/sig0000005f ), + .A3(\blk00000003/sig0000005f ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(\blk00000003/sig00000dba ), + .Q(\blk00000003/sig00001494 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000144b ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig00001493 ), + .Q(\blk00000003/sig00000bae ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000144a ( + .A0(\blk00000003/sig0000005f ), + .A1(\blk00000003/sig00000065 ), + .A2(\blk00000003/sig0000005f ), + .A3(\blk00000003/sig0000005f ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(\blk00000003/sig00000db6 ), + .Q(\blk00000003/sig00001493 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00001449 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig00001492 ), + .Q(\blk00000003/sig00000bad ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00001448 ( + .A0(\blk00000003/sig0000005f ), + .A1(\blk00000003/sig00000065 ), + .A2(\blk00000003/sig0000005f ), + .A3(\blk00000003/sig0000005f ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(\blk00000003/sig00000db1 ), + .Q(\blk00000003/sig00001492 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00001447 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig00001491 ), + .Q(\blk00000003/sig00000bac ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00001446 ( + .A0(\blk00000003/sig0000005f ), + .A1(\blk00000003/sig00000065 ), + .A2(\blk00000003/sig0000005f ), + .A3(\blk00000003/sig0000005f ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(\blk00000003/sig00000dac ), + .Q(\blk00000003/sig00001491 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00001445 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig00001490 ), + .Q(\blk00000003/sig00000bab ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00001444 ( + .A0(\blk00000003/sig0000005f ), + .A1(\blk00000003/sig00000065 ), + .A2(\blk00000003/sig0000005f ), + .A3(\blk00000003/sig0000005f ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(\blk00000003/sig00000da7 ), + .Q(\blk00000003/sig00001490 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00001443 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig0000148f ), + .Q(\blk00000003/sig00000baa ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00001442 ( + .A0(\blk00000003/sig0000005f ), + .A1(\blk00000003/sig00000065 ), + .A2(\blk00000003/sig0000005f ), + .A3(\blk00000003/sig0000005f ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(\blk00000003/sig00000da2 ), + .Q(\blk00000003/sig0000148f ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00001441 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig0000148e ), + .Q(\blk00000003/sig00000ba9 ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00001440 ( + .A0(\blk00000003/sig0000005f ), + .A1(\blk00000003/sig00000065 ), + .A2(\blk00000003/sig0000005f ), + .A3(\blk00000003/sig0000005f ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(\blk00000003/sig00000d9d ), + .Q(\blk00000003/sig0000148e ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000143f ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig0000148d ), + .Q(\blk00000003/sig00000ba8 ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000143e ( + .A0(\blk00000003/sig0000005f ), + .A1(\blk00000003/sig00000065 ), + .A2(\blk00000003/sig0000005f ), + .A3(\blk00000003/sig0000005f ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(\blk00000003/sig00000d98 ), + .Q(\blk00000003/sig0000148d ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000143d ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig0000148c ), + .Q(\blk00000003/sig00000ba7 ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000143c ( + .A0(\blk00000003/sig0000005f ), + .A1(\blk00000003/sig00000065 ), + .A2(\blk00000003/sig0000005f ), + .A3(\blk00000003/sig0000005f ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(\blk00000003/sig00000d93 ), + .Q(\blk00000003/sig0000148c ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000143b ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig0000148b ), + .Q(\blk00000003/sig00000ba6 ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000143a ( + .A0(\blk00000003/sig0000005f ), + .A1(\blk00000003/sig00000065 ), + .A2(\blk00000003/sig0000005f ), + .A3(\blk00000003/sig0000005f ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(\blk00000003/sig00000d8e ), + .Q(\blk00000003/sig0000148b ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00001439 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig0000148a ), + .Q(\blk00000003/sig00000ba5 ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00001438 ( + .A0(\blk00000003/sig0000005f ), + .A1(\blk00000003/sig00000065 ), + .A2(\blk00000003/sig0000005f ), + .A3(\blk00000003/sig0000005f ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(\blk00000003/sig00000d89 ), + .Q(\blk00000003/sig0000148a ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00001437 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig00001489 ), + .Q(\blk00000003/sig00000ba4 ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00001436 ( + .A0(\blk00000003/sig0000005f ), + .A1(\blk00000003/sig00000065 ), + .A2(\blk00000003/sig0000005f ), + .A3(\blk00000003/sig0000005f ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(\blk00000003/sig00000d84 ), + .Q(\blk00000003/sig00001489 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00001435 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig00001488 ), + .Q(\blk00000003/sig00000ba3 ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00001434 ( + .A0(\blk00000003/sig0000005f ), + .A1(\blk00000003/sig00000065 ), + .A2(\blk00000003/sig0000005f ), + .A3(\blk00000003/sig0000005f ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(\blk00000003/sig00000d7f ), + .Q(\blk00000003/sig00001488 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00001433 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig00001487 ), + .Q(\blk00000003/sig00000ba2 ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00001432 ( + .A0(\blk00000003/sig0000005f ), + .A1(\blk00000003/sig00000065 ), + .A2(\blk00000003/sig0000005f ), + .A3(\blk00000003/sig0000005f ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(\blk00000003/sig00000d7a ), + .Q(\blk00000003/sig00001487 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00001431 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig00001486 ), + .Q(\blk00000003/sig00000ba1 ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00001430 ( + .A0(\blk00000003/sig0000005f ), + .A1(\blk00000003/sig00000065 ), + .A2(\blk00000003/sig0000005f ), + .A3(\blk00000003/sig0000005f ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(\blk00000003/sig00000d75 ), + .Q(\blk00000003/sig00001486 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000142f ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig00001485 ), + .Q(\blk00000003/sig00000ba0 ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000142e ( + .A0(\blk00000003/sig0000005f ), + .A1(\blk00000003/sig00000065 ), + .A2(\blk00000003/sig0000005f ), + .A3(\blk00000003/sig0000005f ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(\blk00000003/sig00000d70 ), + .Q(\blk00000003/sig00001485 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000142d ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig00001484 ), + .Q(\blk00000003/sig00000b9f ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000142c ( + .A0(\blk00000003/sig00000065 ), + .A1(\blk00000003/sig0000005f ), + .A2(\blk00000003/sig0000005f ), + .A3(\blk00000003/sig0000005f ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(\blk00000003/sig00000e09 ), + .Q(\blk00000003/sig00001484 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000142b ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig00001483 ), + .Q(\blk00000003/sig00000f9f ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000142a ( + .A0(\blk00000003/sig00000065 ), + .A1(\blk00000003/sig0000005f ), + .A2(\blk00000003/sig0000005f ), + .A3(\blk00000003/sig0000005f ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(\blk00000003/sig00000e08 ), + .Q(\blk00000003/sig00001483 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00001429 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig00001482 ), + .Q(\blk00000003/sig00000f9e ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00001428 ( + .A0(\blk00000003/sig00000065 ), + .A1(\blk00000003/sig0000005f ), + .A2(\blk00000003/sig0000005f ), + .A3(\blk00000003/sig0000005f ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(\blk00000003/sig00000e07 ), + .Q(\blk00000003/sig00001482 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00001427 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig00001481 ), + .Q(\blk00000003/sig00000f9d ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00001426 ( + .A0(\blk00000003/sig00000065 ), + .A1(\blk00000003/sig0000005f ), + .A2(\blk00000003/sig0000005f ), + .A3(\blk00000003/sig0000005f ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(\blk00000003/sig00000e06 ), + .Q(\blk00000003/sig00001481 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00001425 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig00001480 ), + .Q(\blk00000003/sig00000f9c ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00001424 ( + .A0(\blk00000003/sig00000065 ), + .A1(\blk00000003/sig0000005f ), + .A2(\blk00000003/sig0000005f ), + .A3(\blk00000003/sig0000005f ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(\blk00000003/sig00000e05 ), + .Q(\blk00000003/sig00001480 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00001423 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig0000147f ), + .Q(\blk00000003/sig00000f9b ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00001422 ( + .A0(\blk00000003/sig00000065 ), + .A1(\blk00000003/sig0000005f ), + .A2(\blk00000003/sig0000005f ), + .A3(\blk00000003/sig0000005f ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(\blk00000003/sig00000e04 ), + .Q(\blk00000003/sig0000147f ) + ); + FD #( + .INIT ( 1'b0 )) + \blk00000003/blk00001421 ( + .C(clk), + .D(\blk00000003/sig0000147e ), + .Q(\blk00000003/sig00000b7f ) + ); + SRL16 #( + .INIT ( 16'h0000 )) + \blk00000003/blk00001420 ( + .A0(\blk00000003/sig0000005f ), + .A1(\blk00000003/sig0000005f ), + .A2(\blk00000003/sig0000005f ), + .A3(\blk00000003/sig0000005f ), + .CLK(clk), + .D(\blk00000003/sig000006e9 ), + .Q(\blk00000003/sig0000147e ) + ); + FD #( + .INIT ( 1'b0 )) + \blk00000003/blk0000141f ( + .C(clk), + .D(\blk00000003/sig0000147d ), + .Q(\blk00000003/sig000006e5 ) + ); + SRL16 #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000141e ( + .A0(\blk00000003/sig0000005f ), + .A1(\blk00000003/sig0000005f ), + .A2(\blk00000003/sig0000005f ), + .A3(\blk00000003/sig0000005f ), + .CLK(clk), + .D(\blk00000003/sig000006af ), + .Q(\blk00000003/sig0000147d ) + ); + INV \blk00000003/blk0000141d ( + .I(\blk00000003/sig00001478 ), + .O(\blk00000003/sig00001477 ) + ); + INV \blk00000003/blk0000141c ( + .I(\blk00000003/sig00000747 ), + .O(\blk00000003/sig00000743 ) + ); + INV \blk00000003/blk0000141b ( + .I(\blk00000003/sig00000704 ), + .O(\blk00000003/sig0000070a ) + ); + INV \blk00000003/blk0000141a ( + .I(\blk00000003/sig00000298 ), + .O(\blk00000003/sig00000294 ) + ); + INV \blk00000003/blk00001419 ( + .I(\blk00000003/sig0000026b ), + .O(\blk00000003/sig00000267 ) + ); + INV \blk00000003/blk00001418 ( + .I(\blk00000003/sig000001f9 ), + .O(\blk00000003/sig0000023d ) + ); + INV \blk00000003/blk00001417 ( + .I(\blk00000003/sig0000012c ), + .O(\blk00000003/sig00000129 ) + ); + INV \blk00000003/blk00001416 ( + .I(\blk00000003/sig000000d9 ), + .O(\blk00000003/sig000000ab ) + ); + INV \blk00000003/blk00001415 ( + .I(\blk00000003/sig000000a1 ), + .O(\blk00000003/sig000000f4 ) + ); + INV \blk00000003/blk00001414 ( + .I(\blk00000003/sig0000007a ), + .O(\blk00000003/sig0000007c ) + ); + INV \blk00000003/blk00001413 ( + .I(\blk00000003/sig00000068 ), + .O(\blk00000003/sig0000006a ) + ); + INV \blk00000003/blk00001412 ( + .I(\blk00000003/sig00000b87 ), + .O(\blk00000003/sig00000e62 ) + ); + INV \blk00000003/blk00001411 ( + .I(\blk00000003/sig00000b85 ), + .O(\blk00000003/sig00000e60 ) + ); + INV \blk00000003/blk00001410 ( + .I(\blk00000003/sig00000b85 ), + .O(\blk00000003/sig00000e5d ) + ); + INV \blk00000003/blk0000140f ( + .I(\blk00000003/sig00000b85 ), + .O(\blk00000003/sig00000e5a ) + ); + INV \blk00000003/blk0000140e ( + .I(\blk00000003/sig00000b85 ), + .O(\blk00000003/sig00000e57 ) + ); + INV \blk00000003/blk0000140d ( + .I(\blk00000003/sig00000b82 ), + .O(\blk00000003/sig00000e54 ) + ); + INV \blk00000003/blk0000140c ( + .I(\blk00000003/sig00000b81 ), + .O(\blk00000003/sig00000e51 ) + ); + INV \blk00000003/blk0000140b ( + .I(\blk00000003/sig00000b87 ), + .O(\blk00000003/sig00000e4c ) + ); + INV \blk00000003/blk0000140a ( + .I(\blk00000003/sig00000b89 ), + .O(\blk00000003/sig00000e49 ) + ); + INV \blk00000003/blk00001409 ( + .I(\blk00000003/sig00000b84 ), + .O(\blk00000003/sig00000e46 ) + ); + INV \blk00000003/blk00001408 ( + .I(\blk00000003/sig00000b83 ), + .O(\blk00000003/sig00000e43 ) + ); + INV \blk00000003/blk00001407 ( + .I(\blk00000003/sig00000b82 ), + .O(\blk00000003/sig00000e40 ) + ); + INV \blk00000003/blk00001406 ( + .I(\blk00000003/sig00000b87 ), + .O(\blk00000003/sig00000e3d ) + ); + INV \blk00000003/blk00001405 ( + .I(\blk00000003/sig00000b8e ), + .O(\blk00000003/sig00000e3a ) + ); + INV \blk00000003/blk00001404 ( + .I(\blk00000003/sig00000b81 ), + .O(\blk00000003/sig00000e35 ) + ); + INV \blk00000003/blk00001403 ( + .I(\blk00000003/sig00000b89 ), + .O(\blk00000003/sig00000e33 ) + ); + INV \blk00000003/blk00001402 ( + .I(\blk00000003/sig00000b89 ), + .O(\blk00000003/sig00000e30 ) + ); + INV \blk00000003/blk00001401 ( + .I(\blk00000003/sig00000b89 ), + .O(\blk00000003/sig00000e2d ) + ); + INV \blk00000003/blk00001400 ( + .I(\blk00000003/sig00000b89 ), + .O(\blk00000003/sig00000e2a ) + ); + INV \blk00000003/blk000013ff ( + .I(\blk00000003/sig00000b82 ), + .O(\blk00000003/sig00000e27 ) + ); + INV \blk00000003/blk000013fe ( + .I(\blk00000003/sig00000b87 ), + .O(\blk00000003/sig00000e24 ) + ); + INV \blk00000003/blk000013fd ( + .I(\blk00000003/sig00000b81 ), + .O(\blk00000003/sig00000e1f ) + ); + INV \blk00000003/blk000013fc ( + .I(\blk00000003/sig00000b85 ), + .O(\blk00000003/sig00000e1c ) + ); + INV \blk00000003/blk000013fb ( + .I(\blk00000003/sig00000b84 ), + .O(\blk00000003/sig00000e19 ) + ); + INV \blk00000003/blk000013fa ( + .I(\blk00000003/sig00000b83 ), + .O(\blk00000003/sig00000e16 ) + ); + INV \blk00000003/blk000013f9 ( + .I(\blk00000003/sig00000b82 ), + .O(\blk00000003/sig00000e13 ) + ); + INV \blk00000003/blk000013f8 ( + .I(\blk00000003/sig00000b81 ), + .O(\blk00000003/sig00000e10 ) + ); + INV \blk00000003/blk000013f7 ( + .I(\blk00000003/sig00000b80 ), + .O(\blk00000003/sig00000e0d ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000013f6 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig000008d7 ), + .Q(\blk00000003/sig0000147b ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000013f5 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig00001183 ), + .Q(\blk00000003/sig0000147c ) + ); + LUT4 #( + .INIT ( 16'hBE82 )) + \blk00000003/blk000013f4 ( + .I0(\blk00000003/sig00000b85 ), + .I1(\blk00000003/sig00000b9d ), + .I2(\blk00000003/sig00000b5d ), + .I3(\blk00000003/sig00000e5b ), + .O(\blk00000003/sig00000e7c ) + ); + LUT4 #( + .INIT ( 16'hBE82 )) + \blk00000003/blk000013f3 ( + .I0(\blk00000003/sig00000b89 ), + .I1(\blk00000003/sig00000b9c ), + .I2(\blk00000003/sig00000b5d ), + .I3(\blk00000003/sig00000e2e ), + .O(\blk00000003/sig00000e90 ) + ); + LUT4 #( + .INIT ( 16'hBE82 )) + \blk00000003/blk000013f2 ( + .I0(\blk00000003/sig00000b85 ), + .I1(\blk00000003/sig00000b9d ), + .I2(\blk00000003/sig00000b5d ), + .I3(\blk00000003/sig00000e58 ), + .O(\blk00000003/sig00000e7a ) + ); + LUT4 #( + .INIT ( 16'hBE82 )) + \blk00000003/blk000013f1 ( + .I0(\blk00000003/sig00000b89 ), + .I1(\blk00000003/sig00000b9c ), + .I2(\blk00000003/sig00000b5d ), + .I3(\blk00000003/sig00000e2b ), + .O(\blk00000003/sig00000e8f ) + ); + LUT4 #( + .INIT ( 16'hBE82 )) + \blk00000003/blk000013f0 ( + .I0(\blk00000003/sig00000b82 ), + .I1(\blk00000003/sig00000b9d ), + .I2(\blk00000003/sig00000b5d ), + .I3(\blk00000003/sig00000e55 ), + .O(\blk00000003/sig00000e78 ) + ); + LUT4 #( + .INIT ( 16'hBE82 )) + \blk00000003/blk000013ef ( + .I0(\blk00000003/sig00000b82 ), + .I1(\blk00000003/sig00000b9c ), + .I2(\blk00000003/sig00000b5d ), + .I3(\blk00000003/sig00000e28 ), + .O(\blk00000003/sig00000e8e ) + ); + LUT4 #( + .INIT ( 16'hBE82 )) + \blk00000003/blk000013ee ( + .I0(\blk00000003/sig00000b81 ), + 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.O(\blk00000003/sig00000e6c ) + ); + LUT4 #( + .INIT ( 16'hBE82 )) + \blk00000003/blk000013e5 ( + .I0(\blk00000003/sig00000b83 ), + .I1(\blk00000003/sig00000b9c ), + .I2(\blk00000003/sig00000b5d ), + .I3(\blk00000003/sig00000e17 ), + .O(\blk00000003/sig00000e88 ) + ); + LUT4 #( + .INIT ( 16'hBE82 )) + \blk00000003/blk000013e4 ( + .I0(\blk00000003/sig00000b82 ), + .I1(\blk00000003/sig00000b9d ), + .I2(\blk00000003/sig00000b5d ), + .I3(\blk00000003/sig00000e41 ), + .O(\blk00000003/sig00000e6a ) + ); + LUT4 #( + .INIT ( 16'hBE82 )) + \blk00000003/blk000013e3 ( + .I0(\blk00000003/sig00000b82 ), + .I1(\blk00000003/sig00000b9c ), + .I2(\blk00000003/sig00000b5d ), + .I3(\blk00000003/sig00000e14 ), + .O(\blk00000003/sig00000e87 ) + ); + LUT4 #( + .INIT ( 16'hBE82 )) + \blk00000003/blk000013e2 ( + .I0(\blk00000003/sig00000b87 ), + .I1(\blk00000003/sig00000b9d ), + .I2(\blk00000003/sig00000b5d ), + .I3(\blk00000003/sig00000e3e ), + .O(\blk00000003/sig00000e68 ) + ); + LUT4 #( + .INIT ( 16'hBE82 )) + \blk00000003/blk000013e1 ( + .I0(\blk00000003/sig00000b81 ), + .I1(\blk00000003/sig00000b9c ), + .I2(\blk00000003/sig00000b5d ), + .I3(\blk00000003/sig00000e11 ), + .O(\blk00000003/sig00000e86 ) + ); + LUT4 #( + .INIT ( 16'hBE82 )) + \blk00000003/blk000013e0 ( + .I0(\blk00000003/sig00000b8e ), + .I1(\blk00000003/sig00000b9d ), + .I2(\blk00000003/sig00000b5d ), + .I3(\blk00000003/sig00000e3b ), + .O(\blk00000003/sig00000e66 ) + ); + LUT4 #( + .INIT ( 16'hBE82 )) + \blk00000003/blk000013df ( + .I0(\blk00000003/sig00000b80 ), + .I1(\blk00000003/sig00000b9c ), + .I2(\blk00000003/sig00000b5d ), + .I3(\blk00000003/sig00000e0e ), + .O(\blk00000003/sig00000e85 ) + ); + LUT3 #( + .INIT ( 8'h60 )) + \blk00000003/blk000013de ( + .I0(\blk00000003/sig00000b5d ), + .I1(\blk00000003/sig00000b9d ), + .I2(\blk00000003/sig00000e4f ), + .O(\blk00000003/sig00000e74 ) + ); + LUT3 #( + .INIT ( 8'h60 )) + \blk00000003/blk000013dd ( + .I0(\blk00000003/sig00000b5d ), + .I1(\blk00000003/sig00000b9c ), + .I2(\blk00000003/sig00000e22 ), + .O(\blk00000003/sig00000e8c ) + ); + LUT3 #( + .INIT ( 8'h60 )) + \blk00000003/blk000013dc ( + .I0(\blk00000003/sig00000b5d ), + .I1(\blk00000003/sig00000b9d ), + .I2(\blk00000003/sig00000e38 ), + .O(\blk00000003/sig00000e64 ) + ); + LUT3 #( + .INIT ( 8'h60 )) + \blk00000003/blk000013db ( + .I0(\blk00000003/sig00000b5d ), + .I1(\blk00000003/sig00000b9c ), + .I2(\blk00000003/sig00000e0b ), + .O(\blk00000003/sig00000e84 ) + ); + LUT4 #( + .INIT ( 16'hF960 )) + \blk00000003/blk000013da ( + .I0(\blk00000003/sig00000b5d ), + .I1(\blk00000003/sig00000b9d ), + .I2(\blk00000003/sig00000e63 ), + .I3(\blk00000003/sig00000b87 ), + .O(\blk00000003/sig00000e82 ) + ); + LUT4 #( + .INIT ( 16'hF960 )) + \blk00000003/blk000013d9 ( + .I0(\blk00000003/sig00000b5d ), + .I1(\blk00000003/sig00000b9c ), + .I2(\blk00000003/sig00000e36 ), + .I3(\blk00000003/sig00000b81 ), + .O(\blk00000003/sig00000e93 ) + ); + LUT4 #( + .INIT ( 16'hF690 )) + \blk00000003/blk000013d8 ( + .I0(\blk00000003/sig00000b9d ), + .I1(\blk00000003/sig00000b5d ), + .I2(\blk00000003/sig00000b85 ), + .I3(\blk00000003/sig00000e61 ), + .O(\blk00000003/sig00000e80 ) + ); + LUT4 #( + .INIT ( 16'hF690 )) + \blk00000003/blk000013d7 ( + .I0(\blk00000003/sig00000b9c ), + .I1(\blk00000003/sig00000b5d ), + .I2(\blk00000003/sig00000b89 ), + .I3(\blk00000003/sig00000e34 ), + .O(\blk00000003/sig00000e92 ) + ); + LUT4 #( + .INIT ( 16'hF690 )) + \blk00000003/blk000013d6 ( + .I0(\blk00000003/sig00000b9d ), + .I1(\blk00000003/sig00000b5d ), + .I2(\blk00000003/sig00000b85 ), + .I3(\blk00000003/sig00000e5e ), + .O(\blk00000003/sig00000e7e ) + ); + LUT4 #( + .INIT ( 16'hF690 )) + \blk00000003/blk000013d5 ( + .I0(\blk00000003/sig00000b9c ), + .I1(\blk00000003/sig00000b5d ), + .I2(\blk00000003/sig00000b89 ), + .I3(\blk00000003/sig00000e31 ), + .O(\blk00000003/sig00000e91 ) + ); + LUT1 #( + .INIT ( 2'h2 )) + \blk00000003/blk000013d4 ( + .I0(\blk00000003/sig00000495 ), + .O(\blk00000003/sig00000333 ) + ); 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.O(\blk00000003/sig00000323 ) + ); + LUT1 #( + .INIT ( 2'h2 )) + \blk00000003/blk000013cb ( + .I0(\blk00000003/sig0000049e ), + .O(\blk00000003/sig00000321 ) + ); + LUT1 #( + .INIT ( 2'h2 )) + \blk00000003/blk000013ca ( + .I0(\blk00000003/sig0000049f ), + .O(\blk00000003/sig0000031f ) + ); + LUT1 #( + .INIT ( 2'h2 )) + \blk00000003/blk000013c9 ( + .I0(\blk00000003/sig000004a0 ), + .O(\blk00000003/sig0000031d ) + ); + LUT1 #( + .INIT ( 2'h2 )) + \blk00000003/blk000013c8 ( + .I0(\blk00000003/sig000004a1 ), + .O(\blk00000003/sig0000031b ) + ); + LUT1 #( + .INIT ( 2'h2 )) + \blk00000003/blk000013c7 ( + .I0(\blk00000003/sig000004a2 ), + .O(\blk00000003/sig00000319 ) + ); + LUT1 #( + .INIT ( 2'h2 )) + \blk00000003/blk000013c6 ( + .I0(\blk00000003/sig000004a3 ), + .O(\blk00000003/sig00000317 ) + ); + LUT1 #( + .INIT ( 2'h2 )) + \blk00000003/blk000013c5 ( + .I0(\blk00000003/sig000004a4 ), + .O(\blk00000003/sig00000315 ) + ); + LUT1 #( + .INIT ( 2'h2 )) + \blk00000003/blk000013c4 ( + .I0(\blk00000003/sig000004a5 ), + .O(\blk00000003/sig00000313 ) + ); + LUT1 #( + .INIT ( 2'h2 )) + \blk00000003/blk000013c3 ( + .I0(\blk00000003/sig00000483 ), + .O(\blk00000003/sig000002ef ) + ); + LUT1 #( + .INIT ( 2'h2 )) + \blk00000003/blk000013c2 ( + .I0(\blk00000003/sig00000484 ), + .O(\blk00000003/sig000002ed ) + ); + LUT1 #( + .INIT ( 2'h2 )) + \blk00000003/blk000013c1 ( + .I0(\blk00000003/sig00000485 ), + .O(\blk00000003/sig000002eb ) + ); + LUT1 #( + .INIT ( 2'h2 )) + \blk00000003/blk000013c0 ( + .I0(\blk00000003/sig00000486 ), + .O(\blk00000003/sig000002e9 ) + ); + LUT1 #( + .INIT ( 2'h2 )) + \blk00000003/blk000013bf ( + .I0(\blk00000003/sig00000487 ), + .O(\blk00000003/sig000002e7 ) + ); + LUT1 #( + .INIT ( 2'h2 )) + \blk00000003/blk000013be ( + .I0(\blk00000003/sig00000488 ), + .O(\blk00000003/sig000002e5 ) + ); + LUT1 #( + .INIT ( 2'h2 )) + \blk00000003/blk000013bd ( + .I0(\blk00000003/sig00000489 ), + .O(\blk00000003/sig000002e3 ) + ); + LUT1 #( + .INIT ( 2'h2 )) + \blk00000003/blk000013bc ( + .I0(\blk00000003/sig0000048a ), + .O(\blk00000003/sig000002e1 ) + ); + LUT1 #( + .INIT ( 2'h2 )) + \blk00000003/blk000013bb ( + .I0(\blk00000003/sig0000048b ), + .O(\blk00000003/sig000002df ) + ); + LUT1 #( + .INIT ( 2'h2 )) + \blk00000003/blk000013ba ( + .I0(\blk00000003/sig0000048c ), + .O(\blk00000003/sig000002dd ) + ); + LUT1 #( + .INIT ( 2'h2 )) + \blk00000003/blk000013b9 ( + .I0(\blk00000003/sig0000048d ), + .O(\blk00000003/sig000002db ) + ); + LUT1 #( + .INIT ( 2'h2 )) + \blk00000003/blk000013b8 ( + .I0(\blk00000003/sig0000048e ), + .O(\blk00000003/sig000002d9 ) + ); + LUT1 #( + .INIT ( 2'h2 )) + \blk00000003/blk000013b7 ( + .I0(\blk00000003/sig0000048f ), + .O(\blk00000003/sig000002d7 ) + ); + LUT1 #( + .INIT ( 2'h2 )) + \blk00000003/blk000013b6 ( + .I0(\blk00000003/sig00000490 ), + .O(\blk00000003/sig000002d5 ) + ); + LUT1 #( + .INIT ( 2'h2 )) + \blk00000003/blk000013b5 ( + .I0(\blk00000003/sig00000491 ), + .O(\blk00000003/sig000002d3 ) + ); + LUT1 #( + .INIT ( 2'h2 )) + \blk00000003/blk000013b4 ( + .I0(\blk00000003/sig00000492 ), + .O(\blk00000003/sig000002d1 ) + ); + LUT1 #( + .INIT ( 2'h2 )) + \blk00000003/blk000013b3 ( + .I0(\blk00000003/sig00000493 ), + .O(\blk00000003/sig000002cf ) + ); + LUT4 #( + .INIT ( 16'hD782 )) + \blk00000003/blk000013b2 ( + .I0(\blk00000003/sig000012fc ), + .I1(\blk00000003/sig00001027 ), + .I2(\blk00000003/sig000012f9 ), + .I3(\blk00000003/sig00001155 ), + .O(\blk00000003/sig0000120d ) + ); + LUT4 #( + .INIT ( 16'h7D28 )) + \blk00000003/blk000013b1 ( + .I0(\blk00000003/sig000012fc ), + .I1(\blk00000003/sig00001155 ), + .I2(\blk00000003/sig000012f9 ), + .I3(\blk00000003/sig00001027 ), + .O(\blk00000003/sig000011c7 ) + ); + LUT2 #( + .INIT ( 4'h6 )) + \blk00000003/blk000013b0 ( + .I0(\blk00000003/sig0000107d ), + .I1(\blk00000003/sig0000107b ), + .O(\blk00000003/sig000010ec ) + ); + LUT2 #( + .INIT ( 4'h9 )) + \blk00000003/blk000013af ( + .I0(\blk00000003/sig0000107d ), + .I1(\blk00000003/sig0000107b ), + .O(\blk00000003/sig000010ab ) + ); + LUT1 #( + .INIT ( 2'h2 )) + \blk00000003/blk000013ae ( + .I0(\blk00000003/sig00000b5b ), + .O(\blk00000003/sig00000b62 ) + ); + LUT1 #( + .INIT ( 2'h2 )) + \blk00000003/blk000013ad ( + .I0(\blk00000003/sig00000b5a ), + .O(\blk00000003/sig00000b67 ) + ); + LUT4 #( + .INIT ( 16'hD782 )) + \blk00000003/blk000013ac ( + .I0(\blk00000003/sig00000a33 ), + .I1(\blk00000003/sig00000799 ), + .I2(\blk00000003/sig00000a31 ), + .I3(\blk00000003/sig000008ad ), + .O(\blk00000003/sig00000959 ) + ); + LUT4 #( + .INIT ( 16'h7D28 )) + \blk00000003/blk000013ab ( + .I0(\blk00000003/sig00000a33 ), + .I1(\blk00000003/sig000008ad ), + .I2(\blk00000003/sig00000a31 ), + .I3(\blk00000003/sig00000799 ), + .O(\blk00000003/sig00000919 ) + ); + LUT2 #( + .INIT ( 4'h6 )) + \blk00000003/blk000013aa ( + .I0(\blk00000003/sig000007e8 ), + .I1(\blk00000003/sig000007e5 ), + .O(\blk00000003/sig0000084e ) + ); + LUT2 #( + .INIT ( 4'h9 )) + \blk00000003/blk000013a9 ( + .I0(\blk00000003/sig000007e8 ), + .I1(\blk00000003/sig000007e5 ), + .O(\blk00000003/sig00000813 ) + ); + LUT1 #( + .INIT ( 2'h2 )) + \blk00000003/blk000013a8 ( + .I0(\blk00000003/sig0000071d ), + .O(\blk00000003/sig00000746 ) + ); + LUT1 #( + .INIT ( 2'h2 )) + \blk00000003/blk000013a7 ( + .I0(\blk00000003/sig000006ea ), + .O(\blk00000003/sig00000707 ) + ); + LUT1 #( + .INIT ( 2'h2 )) + \blk00000003/blk000013a6 ( + .I0(\blk00000003/sig000006ae ), + .O(\blk00000003/sig000006b8 ) + ); + LUT1 #( + .INIT ( 2'h2 )) + \blk00000003/blk000013a5 ( + .I0(\blk00000003/sig000006ab ), + .O(\blk00000003/sig000006bd ) + ); + LUT4 #( + .INIT ( 16'hD782 )) + \blk00000003/blk000013a4 ( + .I0(\blk00000003/sig000005bb ), + .I1(\blk00000003/sig000003e5 ), + .I2(\blk00000003/sig000005b9 ), + .I3(\blk00000003/sig000003d3 ), + .O(\blk00000003/sig00000511 ) + ); + LUT4 #( + .INIT ( 16'h7D28 )) + \blk00000003/blk000013a3 ( + .I0(\blk00000003/sig000005bb ), + .I1(\blk00000003/sig000003d3 ), + .I2(\blk00000003/sig000005b9 ), + .I3(\blk00000003/sig000003e5 ), + .O(\blk00000003/sig000004da ) + ); + LUT3 #( + .INIT ( 8'h6A )) + \blk00000003/blk000013a2 ( + .I0(\blk00000003/sig00000346 ), + .I1(\blk00000003/sig0000029d ), + .I2(\blk00000003/sig0000029c ), + .O(\blk00000003/sig000003a1 ) + ); + LUT3 #( + .INIT ( 8'h6A )) + \blk00000003/blk000013a1 ( + .I0(\blk00000003/sig00000357 ), + .I1(\blk00000003/sig000002ad ), + .I2(\blk00000003/sig0000029c ), + .O(\blk00000003/sig0000036c ) + ); + LUT1 #( + .INIT ( 2'h2 )) + \blk00000003/blk000013a0 ( + .I0(\blk00000003/sig0000026e ), + .O(\blk00000003/sig00000297 ) + ); + LUT1 #( + .INIT ( 2'h2 )) + \blk00000003/blk0000139f ( + .I0(\blk00000003/sig00000247 ), + .O(\blk00000003/sig0000026a ) + ); + LUT4 #( + .INIT ( 16'hFFEF )) + \blk00000003/blk0000139e ( + .I0(\blk00000003/sig00001476 ), + .I1(\blk00000003/sig00001474 ), + .I2(\blk00000003/sig00001478 ), + .I3(\blk00000003/sig00001479 ), + .O(\blk00000003/sig0000147a ) + ); + LUT2 #( + .INIT ( 4'h6 )) + \blk00000003/blk0000139d ( + .I0(NlwRenamedSig_OI_edone), + .I1(\blk00000003/sig00001479 ), + .O(\blk00000003/sig00001472 ) + ); + LUT4 #( + .INIT ( 16'h7E81 )) + \blk00000003/blk0000139c ( + .I0(\blk00000003/sig00001479 ), + .I1(\blk00000003/sig00001478 ), + .I2(\blk00000003/sig00001476 ), + .I3(\blk00000003/sig00001474 ), + .O(\blk00000003/sig00001473 ) + ); + LUT3 #( + .INIT ( 8'h69 )) + \blk00000003/blk0000139b ( + .I0(\blk00000003/sig00001479 ), + .I1(\blk00000003/sig00001478 ), + .I2(\blk00000003/sig00001476 ), + .O(\blk00000003/sig00001475 ) + ); + LUT2 #( + .INIT ( 4'h6 )) + \blk00000003/blk0000139a ( + .I0(\blk00000003/sig00001394 ), + .I1(\blk00000003/sig00001254 ), + .O(\blk00000003/sig0000140a ) + ); + LUT2 #( + .INIT ( 4'h6 )) + \blk00000003/blk00001399 ( + .I0(\blk00000003/sig00001395 ), + .I1(\blk00000003/sig00001252 ), + .O(\blk00000003/sig0000140d ) + ); + LUT2 #( + .INIT ( 4'h6 )) + \blk00000003/blk00001398 ( + .I0(\blk00000003/sig00001396 ), + .I1(\blk00000003/sig00001250 ), + .O(\blk00000003/sig00001410 ) + ); + LUT2 #( + .INIT ( 4'h6 )) + \blk00000003/blk00001397 ( + .I0(\blk00000003/sig00001397 ), + .I1(\blk00000003/sig0000124e ), + .O(\blk00000003/sig00001413 ) + ); + LUT2 #( + .INIT ( 4'h6 )) + \blk00000003/blk00001396 ( + .I0(\blk00000003/sig00001398 ), + .I1(\blk00000003/sig0000124c ), + .O(\blk00000003/sig00001416 ) + ); + LUT2 #( + .INIT ( 4'h6 )) + \blk00000003/blk00001395 ( + .I0(\blk00000003/sig00001399 ), + .I1(\blk00000003/sig0000124a ), + .O(\blk00000003/sig00001419 ) + ); + LUT2 #( + .INIT ( 4'h6 )) + \blk00000003/blk00001394 ( + .I0(\blk00000003/sig0000139a ), + .I1(\blk00000003/sig00001248 ), + .O(\blk00000003/sig0000141c ) + ); + LUT2 #( + .INIT ( 4'h6 )) + \blk00000003/blk00001393 ( + .I0(\blk00000003/sig0000139b ), + .I1(\blk00000003/sig00001246 ), + .O(\blk00000003/sig0000141f ) + ); + LUT2 #( + .INIT ( 4'h6 )) + \blk00000003/blk00001392 ( + .I0(\blk00000003/sig00001387 ), + .I1(\blk00000003/sig0000126e ), + .O(\blk00000003/sig000013e3 ) + ); + LUT2 #( + .INIT ( 4'h6 )) + \blk00000003/blk00001391 ( + .I0(\blk00000003/sig00001388 ), + .I1(\blk00000003/sig0000126c ), + .O(\blk00000003/sig000013e6 ) + ); + LUT2 #( + .INIT ( 4'h6 )) + \blk00000003/blk00001390 ( + .I0(\blk00000003/sig00001389 ), + .I1(\blk00000003/sig0000126a ), + .O(\blk00000003/sig000013e9 ) + ); + LUT2 #( + .INIT ( 4'h6 )) + \blk00000003/blk0000138f ( + .I0(\blk00000003/sig0000139c ), + .I1(\blk00000003/sig00001244 ), + .O(\blk00000003/sig00001422 ) + ); + LUT2 #( + .INIT ( 4'h6 )) + \blk00000003/blk0000138e ( + .I0(\blk00000003/sig0000138a ), + .I1(\blk00000003/sig00001268 ), + .O(\blk00000003/sig000013ec ) + ); + LUT2 #( + .INIT ( 4'h6 )) + \blk00000003/blk0000138d ( + .I0(\blk00000003/sig0000138b ), + .I1(\blk00000003/sig00001266 ), + .O(\blk00000003/sig000013ef ) + ); + LUT2 #( + .INIT ( 4'h6 )) + \blk00000003/blk0000138c ( + .I0(\blk00000003/sig0000138c ), + .I1(\blk00000003/sig00001264 ), + .O(\blk00000003/sig000013f2 ) + ); + LUT2 #( + .INIT ( 4'h6 )) + \blk00000003/blk0000138b ( + .I0(\blk00000003/sig0000138d ), + .I1(\blk00000003/sig00001262 ), + .O(\blk00000003/sig000013f5 ) + ); + LUT2 #( + .INIT ( 4'h6 )) + \blk00000003/blk0000138a ( + .I0(\blk00000003/sig0000138e ), + .I1(\blk00000003/sig00001260 ), + .O(\blk00000003/sig000013f8 ) + ); + LUT2 #( + .INIT ( 4'h6 )) + \blk00000003/blk00001389 ( + .I0(\blk00000003/sig0000138f ), + .I1(\blk00000003/sig0000125e ), + .O(\blk00000003/sig000013fb ) + ); + LUT2 #( + .INIT ( 4'h6 )) + \blk00000003/blk00001388 ( + .I0(\blk00000003/sig00001390 ), + .I1(\blk00000003/sig0000125c ), + .O(\blk00000003/sig000013fe ) + ); + LUT2 #( + .INIT ( 4'h6 )) + \blk00000003/blk00001387 ( + .I0(\blk00000003/sig00001391 ), + .I1(\blk00000003/sig0000125a ), + .O(\blk00000003/sig00001401 ) + ); + LUT2 #( + .INIT ( 4'h6 )) + \blk00000003/blk00001386 ( + .I0(\blk00000003/sig00001392 ), + .I1(\blk00000003/sig00001258 ), + .O(\blk00000003/sig00001404 ) + ); + LUT2 #( + .INIT ( 4'h6 )) + \blk00000003/blk00001385 ( + .I0(\blk00000003/sig00001393 ), + .I1(\blk00000003/sig00001256 ), + .O(\blk00000003/sig00001407 ) + ); + LUT2 #( + .INIT ( 4'h6 )) + \blk00000003/blk00001384 ( + .I0(\blk00000003/sig0000139d ), + .I1(\blk00000003/sig00001242 ), + .O(\blk00000003/sig00001424 ) + ); + LUT2 #( + .INIT ( 4'h9 )) + \blk00000003/blk00001383 ( + .I0(\blk00000003/sig00001394 ), + .I1(\blk00000003/sig00001254 ), + .O(\blk00000003/sig000013c6 ) + ); + LUT2 #( + .INIT ( 4'h9 )) + \blk00000003/blk00001382 ( + .I0(\blk00000003/sig00001395 ), + .I1(\blk00000003/sig00001252 ), + .O(\blk00000003/sig000013c9 ) + ); + LUT2 #( + .INIT ( 4'h9 )) + \blk00000003/blk00001381 ( + .I0(\blk00000003/sig00001396 ), + .I1(\blk00000003/sig00001250 ), + .O(\blk00000003/sig000013cc ) + ); + LUT2 #( + .INIT ( 4'h9 )) + \blk00000003/blk00001380 ( + .I0(\blk00000003/sig00001397 ), + .I1(\blk00000003/sig0000124e ), + .O(\blk00000003/sig000013cf ) + ); + LUT2 #( + .INIT ( 4'h9 )) + \blk00000003/blk0000137f ( + .I0(\blk00000003/sig00001398 ), + .I1(\blk00000003/sig0000124c ), + .O(\blk00000003/sig000013d2 ) + ); + LUT2 #( + .INIT ( 4'h9 )) + \blk00000003/blk0000137e ( + .I0(\blk00000003/sig00001399 ), + .I1(\blk00000003/sig0000124a ), + .O(\blk00000003/sig000013d5 ) + ); + LUT2 #( + .INIT ( 4'h9 )) + \blk00000003/blk0000137d ( + .I0(\blk00000003/sig0000139a ), + .I1(\blk00000003/sig00001248 ), + .O(\blk00000003/sig000013d8 ) + ); + LUT2 #( + .INIT ( 4'h9 )) + \blk00000003/blk0000137c ( + .I0(\blk00000003/sig0000139b ), + .I1(\blk00000003/sig00001246 ), + .O(\blk00000003/sig000013db ) + ); + LUT2 #( + .INIT ( 4'h9 )) + \blk00000003/blk0000137b ( + .I0(\blk00000003/sig00001387 ), + .I1(\blk00000003/sig0000126e ), + .O(\blk00000003/sig0000139f ) + ); + LUT2 #( + .INIT ( 4'h9 )) + \blk00000003/blk0000137a ( + .I0(\blk00000003/sig00001388 ), + .I1(\blk00000003/sig0000126c ), + .O(\blk00000003/sig000013a2 ) + ); + LUT2 #( + .INIT ( 4'h9 )) + \blk00000003/blk00001379 ( + .I0(\blk00000003/sig00001389 ), + .I1(\blk00000003/sig0000126a ), + .O(\blk00000003/sig000013a5 ) + ); + LUT2 #( + .INIT ( 4'h9 )) + \blk00000003/blk00001378 ( + .I0(\blk00000003/sig0000139c ), + .I1(\blk00000003/sig00001244 ), + .O(\blk00000003/sig000013de ) + ); + LUT2 #( + .INIT ( 4'h9 )) + \blk00000003/blk00001377 ( + .I0(\blk00000003/sig0000138a ), + .I1(\blk00000003/sig00001268 ), + .O(\blk00000003/sig000013a8 ) + ); + LUT2 #( + .INIT ( 4'h9 )) + \blk00000003/blk00001376 ( + .I0(\blk00000003/sig0000138b ), + .I1(\blk00000003/sig00001266 ), + .O(\blk00000003/sig000013ab ) + ); + LUT2 #( + .INIT ( 4'h9 )) + \blk00000003/blk00001375 ( + .I0(\blk00000003/sig0000138c ), + .I1(\blk00000003/sig00001264 ), + .O(\blk00000003/sig000013ae ) + ); + LUT2 #( + .INIT ( 4'h9 )) + \blk00000003/blk00001374 ( + .I0(\blk00000003/sig0000138d ), + .I1(\blk00000003/sig00001262 ), + .O(\blk00000003/sig000013b1 ) + ); + LUT2 #( + .INIT ( 4'h9 )) + \blk00000003/blk00001373 ( + .I0(\blk00000003/sig0000138e ), + .I1(\blk00000003/sig00001260 ), + .O(\blk00000003/sig000013b4 ) + ); + LUT2 #( + .INIT ( 4'h9 )) + \blk00000003/blk00001372 ( + .I0(\blk00000003/sig0000138f ), + .I1(\blk00000003/sig0000125e ), + .O(\blk00000003/sig000013b7 ) + ); + LUT2 #( + .INIT ( 4'h9 )) + \blk00000003/blk00001371 ( + .I0(\blk00000003/sig00001390 ), + .I1(\blk00000003/sig0000125c ), + .O(\blk00000003/sig000013ba ) + ); + LUT2 #( + .INIT ( 4'h9 )) + \blk00000003/blk00001370 ( + .I0(\blk00000003/sig00001391 ), + .I1(\blk00000003/sig0000125a ), + .O(\blk00000003/sig000013bd ) + ); + LUT2 #( + .INIT ( 4'h9 )) + \blk00000003/blk0000136f ( + .I0(\blk00000003/sig00001392 ), + .I1(\blk00000003/sig00001258 ), + .O(\blk00000003/sig000013c0 ) + ); + LUT2 #( + .INIT ( 4'h9 )) + \blk00000003/blk0000136e ( + .I0(\blk00000003/sig00001393 ), + .I1(\blk00000003/sig00001256 ), + .O(\blk00000003/sig000013c3 ) + ); + LUT2 #( + .INIT ( 4'h9 )) + \blk00000003/blk0000136d ( + .I0(\blk00000003/sig0000139d ), + .I1(\blk00000003/sig00001242 ), + .O(\blk00000003/sig000013e0 ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk0000136c ( + .I0(\blk00000003/sig00001181 ), + .I1(\blk00000003/sig00001182 ), + .O(\blk00000003/sig000012fb ) + ); + LUT3 #( + .INIT ( 8'hD8 )) + \blk00000003/blk0000136b ( + .I0(\blk00000003/sig00001185 ), + .I1(\blk00000003/sig00001313 ), + .I2(\blk00000003/sig00001386 ), + .O(\blk00000003/sig00001241 ) + ); + LUT3 #( + .INIT ( 8'hD8 )) + \blk00000003/blk0000136a ( + .I0(\blk00000003/sig00001185 ), + .I1(\blk00000003/sig00001312 ), + .I2(\blk00000003/sig00001385 ), + .O(\blk00000003/sig00001243 ) + ); + LUT3 #( + .INIT ( 8'hD8 )) + \blk00000003/blk00001369 ( + .I0(\blk00000003/sig00001185 ), + .I1(\blk00000003/sig00001311 ), + .I2(\blk00000003/sig00001384 ), + .O(\blk00000003/sig00001245 ) + ); + LUT3 #( + .INIT ( 8'hD8 )) + \blk00000003/blk00001368 ( + .I0(\blk00000003/sig00001185 ), + .I1(\blk00000003/sig00001310 ), + .I2(\blk00000003/sig00001383 ), + .O(\blk00000003/sig00001247 ) + ); + LUT3 #( + .INIT ( 8'hD8 )) + \blk00000003/blk00001367 ( + .I0(\blk00000003/sig00001185 ), + .I1(\blk00000003/sig0000130d ), + .I2(\blk00000003/sig00001380 ), + .O(\blk00000003/sig0000124d ) + ); + LUT3 #( + .INIT ( 8'hD8 )) + \blk00000003/blk00001366 ( + .I0(\blk00000003/sig00001185 ), + .I1(\blk00000003/sig0000130f ), + .I2(\blk00000003/sig00001382 ), + .O(\blk00000003/sig00001249 ) + ); + LUT3 #( + .INIT ( 8'hD8 )) + \blk00000003/blk00001365 ( + .I0(\blk00000003/sig00001185 ), + .I1(\blk00000003/sig0000130e ), + .I2(\blk00000003/sig00001381 ), + .O(\blk00000003/sig0000124b ) + ); + LUT3 #( + .INIT ( 8'hD8 )) + \blk00000003/blk00001364 ( + .I0(\blk00000003/sig00001185 ), + .I1(\blk00000003/sig0000130c ), + .I2(\blk00000003/sig0000137f ), + .O(\blk00000003/sig0000124f ) + ); + LUT3 #( + .INIT ( 8'hD8 )) + \blk00000003/blk00001363 ( + .I0(\blk00000003/sig00001185 ), + .I1(\blk00000003/sig0000130b ), + .I2(\blk00000003/sig0000137e ), + .O(\blk00000003/sig00001251 ) + ); + LUT3 #( + .INIT ( 8'hD8 )) + \blk00000003/blk00001362 ( + .I0(\blk00000003/sig00001185 ), + .I1(\blk00000003/sig0000130a ), + .I2(\blk00000003/sig0000137d ), + .O(\blk00000003/sig00001253 ) + ); + LUT3 #( + .INIT ( 8'hD8 )) + \blk00000003/blk00001361 ( + .I0(\blk00000003/sig00001185 ), + .I1(\blk00000003/sig00001309 ), + .I2(\blk00000003/sig0000137c ), + .O(\blk00000003/sig00001255 ) + ); + LUT3 #( + .INIT ( 8'hD8 )) + \blk00000003/blk00001360 ( + .I0(\blk00000003/sig00001185 ), + .I1(\blk00000003/sig00001308 ), + .I2(\blk00000003/sig0000137b ), + .O(\blk00000003/sig00001257 ) + ); + LUT3 #( + .INIT ( 8'hD8 )) + \blk00000003/blk0000135f ( + .I0(\blk00000003/sig00001185 ), + .I1(\blk00000003/sig00001307 ), + .I2(\blk00000003/sig0000137a ), + .O(\blk00000003/sig00001259 ) + ); + LUT3 #( + .INIT ( 8'hD8 )) + \blk00000003/blk0000135e ( + .I0(\blk00000003/sig00001185 ), + .I1(\blk00000003/sig00001304 ), + .I2(\blk00000003/sig00001377 ), + .O(\blk00000003/sig0000125f ) + ); + LUT3 #( + .INIT ( 8'hD8 )) + \blk00000003/blk0000135d ( + .I0(\blk00000003/sig00001185 ), + .I1(\blk00000003/sig00001306 ), + .I2(\blk00000003/sig00001379 ), + .O(\blk00000003/sig0000125b ) + ); + LUT3 #( + .INIT ( 8'hD8 )) + \blk00000003/blk0000135c ( + .I0(\blk00000003/sig00001185 ), + .I1(\blk00000003/sig00001305 ), + .I2(\blk00000003/sig00001378 ), + .O(\blk00000003/sig0000125d ) + ); + LUT3 #( + .INIT ( 8'hD8 )) + \blk00000003/blk0000135b ( + .I0(\blk00000003/sig00001185 ), + .I1(\blk00000003/sig00001303 ), + .I2(\blk00000003/sig00001376 ), + .O(\blk00000003/sig00001261 ) + ); + LUT3 #( + .INIT ( 8'hD8 )) + \blk00000003/blk0000135a ( + .I0(\blk00000003/sig00001185 ), + .I1(\blk00000003/sig00001302 ), + .I2(\blk00000003/sig00001375 ), + .O(\blk00000003/sig00001263 ) + ); + LUT3 #( + .INIT ( 8'hD8 )) + \blk00000003/blk00001359 ( + .I0(\blk00000003/sig00001185 ), + .I1(\blk00000003/sig00001301 ), + .I2(\blk00000003/sig00001374 ), + .O(\blk00000003/sig00001265 ) + ); + LUT3 #( + .INIT ( 8'hD8 )) + \blk00000003/blk00001358 ( + .I0(\blk00000003/sig00001185 ), + .I1(\blk00000003/sig00001300 ), + .I2(\blk00000003/sig00001373 ), + .O(\blk00000003/sig00001267 ) + ); + LUT3 #( + .INIT ( 8'hD8 )) + \blk00000003/blk00001357 ( + .I0(\blk00000003/sig00001185 ), + .I1(\blk00000003/sig000012ff ), + .I2(\blk00000003/sig00001372 ), + .O(\blk00000003/sig00001269 ) + ); + LUT3 #( + .INIT ( 8'hD8 )) + \blk00000003/blk00001356 ( + .I0(\blk00000003/sig00001185 ), + .I1(\blk00000003/sig000012fe ), + .I2(\blk00000003/sig00001371 ), + .O(\blk00000003/sig0000126b ) + ); + LUT3 #( + .INIT ( 8'hD8 )) + \blk00000003/blk00001355 ( + .I0(\blk00000003/sig00001185 ), + .I1(\blk00000003/sig00001385 ), + .I2(\blk00000003/sig00001312 ), + .O(\blk00000003/sig00001215 ) + ); + LUT3 #( + .INIT ( 8'hD8 )) + \blk00000003/blk00001354 ( + .I0(\blk00000003/sig00001185 ), + .I1(\blk00000003/sig000012fd ), + .I2(\blk00000003/sig00001370 ), + .O(\blk00000003/sig0000126d ) + ); + LUT3 #( + .INIT ( 8'hD8 )) + \blk00000003/blk00001353 ( + .I0(\blk00000003/sig00001185 ), + .I1(\blk00000003/sig00001386 ), + .I2(\blk00000003/sig00001313 ), + .O(\blk00000003/sig00001213 ) + ); + LUT3 #( + .INIT ( 8'hD8 )) + \blk00000003/blk00001352 ( + .I0(\blk00000003/sig00001185 ), + .I1(\blk00000003/sig00001384 ), + .I2(\blk00000003/sig00001311 ), + .O(\blk00000003/sig00001217 ) + ); + LUT3 #( + .INIT ( 8'hD8 )) + \blk00000003/blk00001351 ( + .I0(\blk00000003/sig00001185 ), + .I1(\blk00000003/sig00001383 ), + .I2(\blk00000003/sig00001310 ), + .O(\blk00000003/sig00001219 ) + ); + LUT3 #( + .INIT ( 8'hD8 )) + \blk00000003/blk00001350 ( + .I0(\blk00000003/sig00001185 ), + .I1(\blk00000003/sig00001382 ), + .I2(\blk00000003/sig0000130f ), + .O(\blk00000003/sig0000121b ) + ); + LUT3 #( + .INIT ( 8'hD8 )) + \blk00000003/blk0000134f ( + .I0(\blk00000003/sig00001185 ), + .I1(\blk00000003/sig00001381 ), + .I2(\blk00000003/sig0000130e ), + .O(\blk00000003/sig0000121d ) + ); + LUT3 #( + .INIT ( 8'hD8 )) + \blk00000003/blk0000134e ( + .I0(\blk00000003/sig00001185 ), + .I1(\blk00000003/sig00001380 ), + .I2(\blk00000003/sig0000130d ), + .O(\blk00000003/sig0000121f ) + ); + LUT3 #( + .INIT ( 8'hD8 )) + \blk00000003/blk0000134d ( + .I0(\blk00000003/sig00001185 ), + .I1(\blk00000003/sig0000137f ), + .I2(\blk00000003/sig0000130c ), + .O(\blk00000003/sig00001221 ) + ); + LUT3 #( + .INIT ( 8'hD8 )) + \blk00000003/blk0000134c ( + .I0(\blk00000003/sig00001185 ), + .I1(\blk00000003/sig0000137c ), + .I2(\blk00000003/sig00001309 ), + .O(\blk00000003/sig00001227 ) + ); + LUT3 #( + .INIT ( 8'hD8 )) + \blk00000003/blk0000134b ( + .I0(\blk00000003/sig00001185 ), + .I1(\blk00000003/sig0000137e ), + .I2(\blk00000003/sig0000130b ), + .O(\blk00000003/sig00001223 ) + ); + LUT3 #( + .INIT ( 8'hD8 )) + \blk00000003/blk0000134a ( + .I0(\blk00000003/sig00001185 ), + .I1(\blk00000003/sig0000137d ), + .I2(\blk00000003/sig0000130a ), + .O(\blk00000003/sig00001225 ) + ); + LUT3 #( + .INIT ( 8'hD8 )) + \blk00000003/blk00001349 ( + .I0(\blk00000003/sig00001185 ), + .I1(\blk00000003/sig0000137b ), + .I2(\blk00000003/sig00001308 ), + .O(\blk00000003/sig00001229 ) + ); + LUT3 #( + .INIT ( 8'hD8 )) + \blk00000003/blk00001348 ( + .I0(\blk00000003/sig00001185 ), + .I1(\blk00000003/sig0000137a ), + .I2(\blk00000003/sig00001307 ), + .O(\blk00000003/sig0000122b ) + ); + LUT3 #( + .INIT ( 8'hD8 )) + \blk00000003/blk00001347 ( + .I0(\blk00000003/sig00001185 ), + .I1(\blk00000003/sig00001379 ), + .I2(\blk00000003/sig00001306 ), + .O(\blk00000003/sig0000122d ) + ); + LUT3 #( + .INIT ( 8'hD8 )) + \blk00000003/blk00001346 ( + .I0(\blk00000003/sig00001185 ), + .I1(\blk00000003/sig00001378 ), + .I2(\blk00000003/sig00001305 ), + .O(\blk00000003/sig0000122f ) + ); + LUT3 #( + .INIT ( 8'hD8 )) + \blk00000003/blk00001345 ( + .I0(\blk00000003/sig00001185 ), + .I1(\blk00000003/sig00001377 ), + .I2(\blk00000003/sig00001304 ), + .O(\blk00000003/sig00001231 ) + ); + LUT3 #( + .INIT ( 8'hD8 )) + \blk00000003/blk00001344 ( + .I0(\blk00000003/sig00001185 ), + .I1(\blk00000003/sig00001376 ), + .I2(\blk00000003/sig00001303 ), + .O(\blk00000003/sig00001233 ) + ); + LUT3 #( + .INIT ( 8'hD8 )) + \blk00000003/blk00001343 ( + .I0(\blk00000003/sig00001185 ), + .I1(\blk00000003/sig00001375 ), + .I2(\blk00000003/sig00001302 ), + .O(\blk00000003/sig00001235 ) + ); + LUT3 #( + .INIT ( 8'hD8 )) + \blk00000003/blk00001342 ( + .I0(\blk00000003/sig00001185 ), + .I1(\blk00000003/sig00001374 ), + .I2(\blk00000003/sig00001301 ), + .O(\blk00000003/sig00001237 ) + ); + LUT3 #( + .INIT ( 8'hD8 )) + \blk00000003/blk00001341 ( + .I0(\blk00000003/sig00001185 ), + .I1(\blk00000003/sig00001373 ), + .I2(\blk00000003/sig00001300 ), + .O(\blk00000003/sig00001239 ) + ); + LUT3 #( + .INIT ( 8'hD8 )) + \blk00000003/blk00001340 ( + .I0(\blk00000003/sig00001185 ), + .I1(\blk00000003/sig00001372 ), + .I2(\blk00000003/sig000012ff ), + .O(\blk00000003/sig0000123b ) + ); + LUT3 #( + .INIT ( 8'hD8 )) + \blk00000003/blk0000133f ( + .I0(\blk00000003/sig00001185 ), + .I1(\blk00000003/sig00001371 ), + .I2(\blk00000003/sig000012fe ), + .O(\blk00000003/sig0000123d ) + ); + LUT3 #( + .INIT ( 8'hD8 )) + \blk00000003/blk0000133e ( + .I0(\blk00000003/sig00001185 ), + .I1(\blk00000003/sig00001370 ), + .I2(\blk00000003/sig000012fd ), + .O(\blk00000003/sig0000123f ) + ); + LUT3 #( + .INIT ( 8'hD8 )) + \blk00000003/blk0000133d ( + .I0(\blk00000003/sig000012fa ), + .I1(\blk00000003/sig0000143c ), + .I2(\blk00000003/sig0000136f ), + .O(\blk00000003/sig0000129d ) + ); + LUT3 #( + .INIT ( 8'hD8 )) + \blk00000003/blk0000133c ( + .I0(\blk00000003/sig000012fa ), + .I1(\blk00000003/sig0000143b ), + .I2(\blk00000003/sig0000136d ), + .O(\blk00000003/sig0000129f ) + ); + LUT3 #( + .INIT ( 8'hD8 )) + \blk00000003/blk0000133b ( + .I0(\blk00000003/sig000012fa ), + .I1(\blk00000003/sig0000143a ), + .I2(\blk00000003/sig0000136b ), + .O(\blk00000003/sig000012a1 ) + ); + LUT3 #( + .INIT ( 8'hD8 )) + \blk00000003/blk0000133a ( + .I0(\blk00000003/sig000012fa ), + .I1(\blk00000003/sig00001439 ), + .I2(\blk00000003/sig00001369 ), + .O(\blk00000003/sig000012a3 ) + ); + LUT3 #( + .INIT ( 8'hD8 )) + \blk00000003/blk00001339 ( + .I0(\blk00000003/sig000012fa ), + .I1(\blk00000003/sig00001438 ), + .I2(\blk00000003/sig00001367 ), + .O(\blk00000003/sig000012a5 ) + ); + LUT3 #( + .INIT ( 8'hD8 )) + \blk00000003/blk00001338 ( + .I0(\blk00000003/sig000012fa ), + .I1(\blk00000003/sig00001435 ), + .I2(\blk00000003/sig00001361 ), + .O(\blk00000003/sig000012ab ) + ); + LUT3 #( + .INIT ( 8'hD8 )) + \blk00000003/blk00001337 ( + .I0(\blk00000003/sig000012fa ), + .I1(\blk00000003/sig00001437 ), + .I2(\blk00000003/sig00001365 ), + .O(\blk00000003/sig000012a7 ) + ); + LUT3 #( + .INIT ( 8'hD8 )) + \blk00000003/blk00001336 ( + .I0(\blk00000003/sig000012fa ), + .I1(\blk00000003/sig00001436 ), + .I2(\blk00000003/sig00001363 ), + .O(\blk00000003/sig000012a9 ) + ); + LUT3 #( + .INIT ( 8'hD8 )) + \blk00000003/blk00001335 ( + .I0(\blk00000003/sig000012fa ), + .I1(\blk00000003/sig00001434 ), + .I2(\blk00000003/sig0000135f ), + .O(\blk00000003/sig000012ad ) + ); + LUT3 #( + .INIT ( 8'hD8 )) + \blk00000003/blk00001334 ( + .I0(\blk00000003/sig000012fa ), + .I1(\blk00000003/sig00001433 ), + .I2(\blk00000003/sig0000135d ), + .O(\blk00000003/sig000012af ) + ); + LUT3 #( + .INIT ( 8'hD8 )) + \blk00000003/blk00001333 ( + .I0(\blk00000003/sig000012fa ), + .I1(\blk00000003/sig00001432 ), + .I2(\blk00000003/sig0000135b ), + .O(\blk00000003/sig000012b1 ) + ); + LUT3 #( + .INIT ( 8'hD8 )) + \blk00000003/blk00001332 ( + .I0(\blk00000003/sig000012fa ), + .I1(\blk00000003/sig00001431 ), + .I2(\blk00000003/sig00001359 ), + .O(\blk00000003/sig000012b3 ) + ); + LUT3 #( + .INIT ( 8'hD8 )) + \blk00000003/blk00001331 ( + .I0(\blk00000003/sig000012fa ), + .I1(\blk00000003/sig00001430 ), + .I2(\blk00000003/sig00001357 ), + .O(\blk00000003/sig000012b5 ) + ); + LUT3 #( + .INIT ( 8'hD8 )) + \blk00000003/blk00001330 ( + .I0(\blk00000003/sig000012fa ), + .I1(\blk00000003/sig0000142f ), + .I2(\blk00000003/sig00001355 ), + .O(\blk00000003/sig000012b7 ) + ); + LUT3 #( + .INIT ( 8'hD8 )) + \blk00000003/blk0000132f ( + .I0(\blk00000003/sig000012fa ), + .I1(\blk00000003/sig0000142c ), + .I2(\blk00000003/sig0000134f ), + .O(\blk00000003/sig000012bd ) + ); + LUT3 #( + .INIT ( 8'hD8 )) + \blk00000003/blk0000132e ( + .I0(\blk00000003/sig000012fa ), + .I1(\blk00000003/sig0000142e ), + .I2(\blk00000003/sig00001353 ), + .O(\blk00000003/sig000012b9 ) + ); + LUT3 #( + .INIT ( 8'hD8 )) + \blk00000003/blk0000132d ( + .I0(\blk00000003/sig000012fa ), + .I1(\blk00000003/sig0000142d ), + .I2(\blk00000003/sig00001351 ), + .O(\blk00000003/sig000012bb ) + ); + LUT3 #( + .INIT ( 8'hD8 )) + \blk00000003/blk0000132c ( + .I0(\blk00000003/sig000012fa ), + .I1(\blk00000003/sig0000142b ), + .I2(\blk00000003/sig0000134d ), + .O(\blk00000003/sig000012bf ) + ); + LUT3 #( + .INIT ( 8'hD8 )) + \blk00000003/blk0000132b ( + .I0(\blk00000003/sig000012fa ), + .I1(\blk00000003/sig0000142a ), + .I2(\blk00000003/sig0000134b ), + .O(\blk00000003/sig000012c1 ) + ); + LUT3 #( + .INIT ( 8'hD8 )) + \blk00000003/blk0000132a ( + .I0(\blk00000003/sig000012fa ), + .I1(\blk00000003/sig00001429 ), + .I2(\blk00000003/sig00001349 ), + .O(\blk00000003/sig000012c3 ) + ); + LUT3 #( + .INIT ( 8'hD8 )) + \blk00000003/blk00001329 ( + .I0(\blk00000003/sig000012fa ), + .I1(\blk00000003/sig00001428 ), + .I2(\blk00000003/sig00001347 ), + .O(\blk00000003/sig000012c5 ) + ); + LUT3 #( + .INIT ( 8'hD8 )) + \blk00000003/blk00001328 ( + .I0(\blk00000003/sig000012fa ), + .I1(\blk00000003/sig00001427 ), + .I2(\blk00000003/sig00001345 ), + .O(\blk00000003/sig000012c7 ) + ); + LUT3 #( + .INIT ( 8'hD8 )) + \blk00000003/blk00001327 ( + .I0(\blk00000003/sig000012fa ), + .I1(\blk00000003/sig00001426 ), + .I2(\blk00000003/sig00001343 ), + .O(\blk00000003/sig000012c9 ) + ); + LUT3 #( + .INIT ( 8'hD8 )) + \blk00000003/blk00001326 ( + .I0(\blk00000003/sig000012fa ), + .I1(\blk00000003/sig0000136b ), + .I2(\blk00000003/sig0000143a ), + .O(\blk00000003/sig00001273 ) + ); + LUT3 #( + .INIT ( 8'hD8 )) + \blk00000003/blk00001325 ( + .I0(\blk00000003/sig000012fa ), + .I1(\blk00000003/sig0000136f ), + .I2(\blk00000003/sig0000143c ), + .O(\blk00000003/sig0000126f ) + ); + LUT3 #( + .INIT ( 8'hD8 )) + \blk00000003/blk00001324 ( + .I0(\blk00000003/sig000012fa ), + .I1(\blk00000003/sig0000136d ), + .I2(\blk00000003/sig0000143b ), + .O(\blk00000003/sig00001271 ) + ); + LUT3 #( + .INIT ( 8'hD8 )) + \blk00000003/blk00001323 ( + .I0(\blk00000003/sig000012fa ), + .I1(\blk00000003/sig00001369 ), + .I2(\blk00000003/sig00001439 ), + .O(\blk00000003/sig00001275 ) + ); + LUT3 #( + .INIT ( 8'hD8 )) + \blk00000003/blk00001322 ( + .I0(\blk00000003/sig000012fa ), + .I1(\blk00000003/sig00001367 ), + .I2(\blk00000003/sig00001438 ), + .O(\blk00000003/sig00001277 ) + ); + LUT3 #( + .INIT ( 8'hD8 )) + \blk00000003/blk00001321 ( + .I0(\blk00000003/sig000012fa ), + .I1(\blk00000003/sig00001365 ), + .I2(\blk00000003/sig00001437 ), + .O(\blk00000003/sig00001279 ) + ); + LUT3 #( + .INIT ( 8'hD8 )) + \blk00000003/blk00001320 ( + .I0(\blk00000003/sig000012fa ), + .I1(\blk00000003/sig00001363 ), + .I2(\blk00000003/sig00001436 ), + .O(\blk00000003/sig0000127b ) + ); + LUT3 #( + .INIT ( 8'hD8 )) + \blk00000003/blk0000131f ( + .I0(\blk00000003/sig000012fa ), + .I1(\blk00000003/sig00001361 ), + .I2(\blk00000003/sig00001435 ), + .O(\blk00000003/sig0000127d ) + ); + LUT3 #( + .INIT ( 8'hD8 )) + \blk00000003/blk0000131e ( + .I0(\blk00000003/sig000012fa ), + .I1(\blk00000003/sig0000135f ), + .I2(\blk00000003/sig00001434 ), + .O(\blk00000003/sig0000127f ) + ); + LUT3 #( + .INIT ( 8'hD8 )) + \blk00000003/blk0000131d ( + .I0(\blk00000003/sig000012fa ), + .I1(\blk00000003/sig00001359 ), + .I2(\blk00000003/sig00001431 ), + .O(\blk00000003/sig00001285 ) + ); + LUT3 #( + .INIT ( 8'hD8 )) + \blk00000003/blk0000131c ( + .I0(\blk00000003/sig000012fa ), + .I1(\blk00000003/sig0000135d ), + .I2(\blk00000003/sig00001433 ), + .O(\blk00000003/sig00001281 ) + ); + LUT3 #( + .INIT ( 8'hD8 )) + \blk00000003/blk0000131b ( + .I0(\blk00000003/sig000012fa ), + .I1(\blk00000003/sig0000135b ), + .I2(\blk00000003/sig00001432 ), + .O(\blk00000003/sig00001283 ) + ); + LUT3 #( + .INIT ( 8'hD8 )) + \blk00000003/blk0000131a ( + .I0(\blk00000003/sig000012fa ), + .I1(\blk00000003/sig00001357 ), + .I2(\blk00000003/sig00001430 ), + .O(\blk00000003/sig00001287 ) + ); + LUT3 #( + .INIT ( 8'hD8 )) + \blk00000003/blk00001319 ( + .I0(\blk00000003/sig000012fa ), + .I1(\blk00000003/sig00001355 ), + .I2(\blk00000003/sig0000142f ), + .O(\blk00000003/sig00001289 ) + ); + LUT3 #( + .INIT ( 8'hD8 )) + \blk00000003/blk00001318 ( + .I0(\blk00000003/sig000012fa ), + .I1(\blk00000003/sig00001353 ), + .I2(\blk00000003/sig0000142e ), + .O(\blk00000003/sig0000128b ) + ); + LUT3 #( + .INIT ( 8'hD8 )) + \blk00000003/blk00001317 ( + .I0(\blk00000003/sig000012fa ), + .I1(\blk00000003/sig00001351 ), + .I2(\blk00000003/sig0000142d ), + .O(\blk00000003/sig0000128d ) + ); + LUT3 #( + .INIT ( 8'hD8 )) + \blk00000003/blk00001316 ( + .I0(\blk00000003/sig000012fa ), + .I1(\blk00000003/sig0000134f ), + .I2(\blk00000003/sig0000142c ), + .O(\blk00000003/sig0000128f ) + ); + LUT3 #( + .INIT ( 8'hD8 )) + \blk00000003/blk00001315 ( + .I0(\blk00000003/sig000012fa ), + .I1(\blk00000003/sig0000134d ), + .I2(\blk00000003/sig0000142b ), + .O(\blk00000003/sig00001291 ) + ); + LUT3 #( + .INIT ( 8'hD8 )) + \blk00000003/blk00001314 ( + .I0(\blk00000003/sig000012fa ), + .I1(\blk00000003/sig00001347 ), + .I2(\blk00000003/sig00001428 ), + .O(\blk00000003/sig00001297 ) + ); + LUT3 #( + .INIT ( 8'hD8 )) + \blk00000003/blk00001313 ( + .I0(\blk00000003/sig000012fa ), + .I1(\blk00000003/sig0000134b ), + .I2(\blk00000003/sig0000142a ), + .O(\blk00000003/sig00001293 ) + ); + LUT3 #( + .INIT ( 8'hD8 )) + \blk00000003/blk00001312 ( + .I0(\blk00000003/sig000012fa ), + .I1(\blk00000003/sig00001349 ), + .I2(\blk00000003/sig00001429 ), + .O(\blk00000003/sig00001295 ) + ); + LUT3 #( + .INIT ( 8'hD8 )) + \blk00000003/blk00001311 ( + .I0(\blk00000003/sig000012fa ), + .I1(\blk00000003/sig00001345 ), + .I2(\blk00000003/sig00001427 ), + .O(\blk00000003/sig00001299 ) + ); + LUT3 #( + .INIT ( 8'hD8 )) + \blk00000003/blk00001310 ( + .I0(\blk00000003/sig000012fa ), + .I1(\blk00000003/sig00001343 ), + .I2(\blk00000003/sig00001426 ), + .O(\blk00000003/sig0000129b ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk0000130f ( + .I0(\blk00000003/sig0000147c ), + .I1(\blk00000003/sig000012fc ), + .O(\blk00000003/sig000011cc ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \blk00000003/blk0000130e ( + .I0(\blk00000003/sig0000147c ), + .I1(\blk00000003/sig000012fc ), + .O(\blk00000003/sig00001212 ) + ); + LUT4 #( + .INIT ( 16'hD782 )) + \blk00000003/blk0000130d ( + .I0(\blk00000003/sig000012fc ), + .I1(\blk00000003/sig00001023 ), + .I2(\blk00000003/sig000012f9 ), + .I3(\blk00000003/sig00001157 ), + .O(\blk00000003/sig00001207 ) + ); + LUT4 #( + .INIT ( 16'h7D28 )) + \blk00000003/blk0000130c ( + .I0(\blk00000003/sig000012fc ), + .I1(\blk00000003/sig00001157 ), + .I2(\blk00000003/sig000012f9 ), + .I3(\blk00000003/sig00001023 ), + .O(\blk00000003/sig000011c1 ) + ); + LUT4 #( + .INIT ( 16'hD782 )) + \blk00000003/blk0000130b ( + .I0(\blk00000003/sig000012fc ), + .I1(\blk00000003/sig00001027 ), + .I2(\blk00000003/sig000012f9 ), + .I3(\blk00000003/sig00001155 ), + .O(\blk00000003/sig00001210 ) + ); + LUT4 #( + .INIT ( 16'h7D28 )) + \blk00000003/blk0000130a ( + .I0(\blk00000003/sig000012fc ), + .I1(\blk00000003/sig00001155 ), + .I2(\blk00000003/sig000012f9 ), + .I3(\blk00000003/sig00001027 ), + .O(\blk00000003/sig000011ca ) + ); + LUT4 #( + .INIT ( 16'hD782 )) + \blk00000003/blk00001309 ( + .I0(\blk00000003/sig000012fc ), + .I1(\blk00000003/sig00001025 ), + .I2(\blk00000003/sig000012f9 ), + .I3(\blk00000003/sig00001156 ), + .O(\blk00000003/sig0000120a ) + ); + LUT4 #( + .INIT ( 16'h7D28 )) + \blk00000003/blk00001308 ( + .I0(\blk00000003/sig000012fc ), + .I1(\blk00000003/sig00001156 ), + .I2(\blk00000003/sig000012f9 ), + .I3(\blk00000003/sig00001025 ), + .O(\blk00000003/sig000011c4 ) + ); + LUT4 #( + .INIT ( 16'hD782 )) + \blk00000003/blk00001307 ( + .I0(\blk00000003/sig000012fc ), + .I1(\blk00000003/sig00001021 ), + .I2(\blk00000003/sig000012f9 ), + .I3(\blk00000003/sig00001158 ), + .O(\blk00000003/sig00001204 ) + ); + LUT4 #( + .INIT ( 16'h7D28 )) + \blk00000003/blk00001306 ( + .I0(\blk00000003/sig000012fc ), + .I1(\blk00000003/sig00001158 ), + .I2(\blk00000003/sig000012f9 ), + .I3(\blk00000003/sig00001021 ), + .O(\blk00000003/sig000011be ) + ); + LUT4 #( + .INIT ( 16'hD782 )) + \blk00000003/blk00001305 ( + .I0(\blk00000003/sig000012fc ), + .I1(\blk00000003/sig0000101f ), + .I2(\blk00000003/sig000012f9 ), + .I3(\blk00000003/sig00001159 ), + .O(\blk00000003/sig00001201 ) + ); + LUT4 #( + .INIT ( 16'h7D28 )) + \blk00000003/blk00001304 ( + .I0(\blk00000003/sig000012fc ), + .I1(\blk00000003/sig00001159 ), + .I2(\blk00000003/sig000012f9 ), + .I3(\blk00000003/sig0000101f ), + .O(\blk00000003/sig000011bb ) + ); + LUT4 #( + .INIT ( 16'hD782 )) + \blk00000003/blk00001303 ( + .I0(\blk00000003/sig000012fc ), + .I1(\blk00000003/sig0000101d ), + .I2(\blk00000003/sig000012f9 ), + .I3(\blk00000003/sig0000115a ), + .O(\blk00000003/sig000011fe ) + ); + LUT4 #( + .INIT ( 16'h7D28 )) + \blk00000003/blk00001302 ( + .I0(\blk00000003/sig000012fc ), + .I1(\blk00000003/sig0000115a ), + .I2(\blk00000003/sig000012f9 ), + .I3(\blk00000003/sig0000101d ), + .O(\blk00000003/sig000011b8 ) + ); + LUT4 #( + .INIT ( 16'hD782 )) + \blk00000003/blk00001301 ( + .I0(\blk00000003/sig000012fc ), + .I1(\blk00000003/sig0000101b ), + .I2(\blk00000003/sig000012f9 ), + .I3(\blk00000003/sig0000115b ), + .O(\blk00000003/sig000011fb ) + ); + LUT4 #( + .INIT ( 16'h7D28 )) + \blk00000003/blk00001300 ( + .I0(\blk00000003/sig000012fc ), + .I1(\blk00000003/sig0000115b ), + .I2(\blk00000003/sig000012f9 ), + .I3(\blk00000003/sig0000101b ), + .O(\blk00000003/sig000011b5 ) + ); + LUT4 #( + .INIT ( 16'hC3AA )) + \blk00000003/blk000012ff ( + .I0(\blk00000003/sig0000115c ), + .I1(\blk00000003/sig00001019 ), + .I2(\blk00000003/sig000012f9 ), + .I3(\blk00000003/sig000012fc ), + .O(\blk00000003/sig000011f8 ) + ); + LUT4 #( + .INIT ( 16'h3CAA )) + \blk00000003/blk000012fe ( + .I0(\blk00000003/sig00001019 ), + .I1(\blk00000003/sig0000115c ), + .I2(\blk00000003/sig000012f9 ), + .I3(\blk00000003/sig000012fc ), + .O(\blk00000003/sig000011b2 ) + ); + LUT4 #( + .INIT ( 16'hC3AA )) + \blk00000003/blk000012fd ( + .I0(\blk00000003/sig0000115d ), + .I1(\blk00000003/sig00001017 ), + .I2(\blk00000003/sig000012f9 ), + .I3(\blk00000003/sig000012fc ), + .O(\blk00000003/sig000011f5 ) + ); + LUT4 #( + .INIT ( 16'h3CAA )) + \blk00000003/blk000012fc ( + .I0(\blk00000003/sig00001017 ), + .I1(\blk00000003/sig0000115d ), + .I2(\blk00000003/sig000012f9 ), + .I3(\blk00000003/sig000012fc ), + .O(\blk00000003/sig000011af ) + ); + LUT4 #( + .INIT ( 16'hC3AA )) + \blk00000003/blk000012fb ( + .I0(\blk00000003/sig00001160 ), + .I1(\blk00000003/sig00001011 ), + .I2(\blk00000003/sig000012f9 ), + .I3(\blk00000003/sig000012fc ), + .O(\blk00000003/sig000011ec ) + ); + LUT4 #( + .INIT ( 16'h3CAA )) + \blk00000003/blk000012fa ( + .I0(\blk00000003/sig00001011 ), + .I1(\blk00000003/sig00001160 ), + .I2(\blk00000003/sig000012f9 ), + .I3(\blk00000003/sig000012fc ), + .O(\blk00000003/sig000011a6 ) + ); + LUT4 #( + .INIT ( 16'hC3AA )) + \blk00000003/blk000012f9 ( + .I0(\blk00000003/sig0000115e ), + .I1(\blk00000003/sig00001015 ), + .I2(\blk00000003/sig000012f9 ), + .I3(\blk00000003/sig000012fc ), + .O(\blk00000003/sig000011f2 ) + ); + LUT4 #( + .INIT ( 16'h3CAA )) + \blk00000003/blk000012f8 ( + .I0(\blk00000003/sig00001015 ), + .I1(\blk00000003/sig0000115e ), + .I2(\blk00000003/sig000012f9 ), + .I3(\blk00000003/sig000012fc ), + .O(\blk00000003/sig000011ac ) + ); + LUT4 #( + .INIT ( 16'hC3AA )) + \blk00000003/blk000012f7 ( + .I0(\blk00000003/sig0000115f ), + .I1(\blk00000003/sig00001013 ), + .I2(\blk00000003/sig000012f9 ), + .I3(\blk00000003/sig000012fc ), + .O(\blk00000003/sig000011ef ) + ); + LUT4 #( + .INIT ( 16'h3CAA )) + \blk00000003/blk000012f6 ( + .I0(\blk00000003/sig00001013 ), + .I1(\blk00000003/sig0000115f ), + .I2(\blk00000003/sig000012f9 ), + .I3(\blk00000003/sig000012fc ), + .O(\blk00000003/sig000011a9 ) + ); + LUT4 #( + .INIT ( 16'hC3AA )) + \blk00000003/blk000012f5 ( + .I0(\blk00000003/sig00001161 ), + .I1(\blk00000003/sig0000100f ), + .I2(\blk00000003/sig000012f9 ), + .I3(\blk00000003/sig000012fc ), + .O(\blk00000003/sig000011e9 ) + ); + LUT4 #( + .INIT ( 16'h3CAA )) + \blk00000003/blk000012f4 ( + .I0(\blk00000003/sig0000100f ), + .I1(\blk00000003/sig00001161 ), + .I2(\blk00000003/sig000012f9 ), + .I3(\blk00000003/sig000012fc ), + .O(\blk00000003/sig000011a3 ) + ); + LUT4 #( + .INIT ( 16'hC3AA )) + \blk00000003/blk000012f3 ( + .I0(\blk00000003/sig00001162 ), + .I1(\blk00000003/sig0000100d ), + .I2(\blk00000003/sig000012f9 ), + .I3(\blk00000003/sig000012fc ), + .O(\blk00000003/sig000011e6 ) + ); + LUT4 #( + .INIT ( 16'h3CAA )) + \blk00000003/blk000012f2 ( + .I0(\blk00000003/sig0000100d ), + .I1(\blk00000003/sig00001162 ), + .I2(\blk00000003/sig000012f9 ), + .I3(\blk00000003/sig000012fc ), + .O(\blk00000003/sig000011a0 ) + ); + LUT4 #( + .INIT ( 16'hC3AA )) + \blk00000003/blk000012f1 ( + .I0(\blk00000003/sig00001163 ), + .I1(\blk00000003/sig0000100b ), + .I2(\blk00000003/sig000012f9 ), + .I3(\blk00000003/sig000012fc ), + .O(\blk00000003/sig000011e3 ) + ); + LUT4 #( + .INIT ( 16'h3CAA )) + \blk00000003/blk000012f0 ( + .I0(\blk00000003/sig0000100b ), + .I1(\blk00000003/sig00001163 ), + .I2(\blk00000003/sig000012f9 ), + .I3(\blk00000003/sig000012fc ), + .O(\blk00000003/sig0000119d ) + ); + LUT4 #( + .INIT ( 16'hC3AA )) + \blk00000003/blk000012ef ( + .I0(\blk00000003/sig00001164 ), + .I1(\blk00000003/sig00001009 ), + .I2(\blk00000003/sig000012f9 ), + .I3(\blk00000003/sig000012fc ), + .O(\blk00000003/sig000011e0 ) + ); + LUT4 #( + .INIT ( 16'h3CAA )) + \blk00000003/blk000012ee ( + .I0(\blk00000003/sig00001009 ), + .I1(\blk00000003/sig00001164 ), + .I2(\blk00000003/sig000012f9 ), + .I3(\blk00000003/sig000012fc ), + .O(\blk00000003/sig0000119a ) + ); + LUT4 #( + .INIT ( 16'hC3AA )) + \blk00000003/blk000012ed ( + .I0(\blk00000003/sig00001165 ), + .I1(\blk00000003/sig00001007 ), + .I2(\blk00000003/sig000012f9 ), + .I3(\blk00000003/sig000012fc ), + .O(\blk00000003/sig000011dd ) + ); + LUT4 #( + .INIT ( 16'h3CAA )) + \blk00000003/blk000012ec ( + .I0(\blk00000003/sig00001007 ), + .I1(\blk00000003/sig00001165 ), + .I2(\blk00000003/sig000012f9 ), + .I3(\blk00000003/sig000012fc ), + .O(\blk00000003/sig00001197 ) + ); + LUT4 #( + .INIT ( 16'hC3AA )) + \blk00000003/blk000012eb ( + .I0(\blk00000003/sig00001166 ), + .I1(\blk00000003/sig00001005 ), + .I2(\blk00000003/sig000012f9 ), + .I3(\blk00000003/sig000012fc ), + .O(\blk00000003/sig000011da ) + ); + LUT4 #( + .INIT ( 16'h3CAA )) + \blk00000003/blk000012ea ( + .I0(\blk00000003/sig00001005 ), + .I1(\blk00000003/sig00001166 ), + .I2(\blk00000003/sig000012f9 ), + .I3(\blk00000003/sig000012fc ), + .O(\blk00000003/sig00001194 ) + ); + LUT4 #( + .INIT ( 16'hC3AA )) + \blk00000003/blk000012e9 ( + .I0(\blk00000003/sig00001169 ), + .I1(\blk00000003/sig00000fff ), + .I2(\blk00000003/sig0000147c ), + .I3(\blk00000003/sig000012fc ), + .O(\blk00000003/sig000011d1 ) + ); + LUT4 #( + .INIT ( 16'h3CAA )) + \blk00000003/blk000012e8 ( + .I0(\blk00000003/sig00000fff ), + .I1(\blk00000003/sig00001169 ), + .I2(\blk00000003/sig0000147c ), + .I3(\blk00000003/sig000012fc ), + .O(\blk00000003/sig0000118b ) + ); + LUT4 #( + .INIT ( 16'hC3AA )) + \blk00000003/blk000012e7 ( + .I0(\blk00000003/sig00001167 ), + .I1(\blk00000003/sig00001003 ), + .I2(\blk00000003/sig000012f9 ), + .I3(\blk00000003/sig000012fc ), + .O(\blk00000003/sig000011d7 ) + ); + LUT4 #( + .INIT ( 16'h3CAA )) + \blk00000003/blk000012e6 ( + .I0(\blk00000003/sig00001003 ), + .I1(\blk00000003/sig00001167 ), + .I2(\blk00000003/sig000012f9 ), + .I3(\blk00000003/sig000012fc ), + .O(\blk00000003/sig00001191 ) + ); + LUT4 #( + .INIT ( 16'hC3AA )) + \blk00000003/blk000012e5 ( + .I0(\blk00000003/sig00001168 ), + .I1(\blk00000003/sig00001001 ), + .I2(\blk00000003/sig000012f9 ), + .I3(\blk00000003/sig000012fc ), + .O(\blk00000003/sig000011d4 ) + ); + LUT4 #( + .INIT ( 16'h3CAA )) + \blk00000003/blk000012e4 ( + .I0(\blk00000003/sig00001001 ), + .I1(\blk00000003/sig00001168 ), + .I2(\blk00000003/sig000012f9 ), + .I3(\blk00000003/sig000012fc ), + .O(\blk00000003/sig0000118e ) + ); + LUT4 #( + .INIT ( 16'hC3AA )) + \blk00000003/blk000012e3 ( + .I0(\blk00000003/sig0000116a ), + .I1(\blk00000003/sig00000ffd ), + .I2(\blk00000003/sig0000147c ), + .I3(\blk00000003/sig000012fc ), + .O(\blk00000003/sig000011ce ) + ); + LUT4 #( + .INIT ( 16'h3CAA )) + \blk00000003/blk000012e2 ( + .I0(\blk00000003/sig00000ffd ), + .I1(\blk00000003/sig0000116a ), + .I2(\blk00000003/sig0000147c ), + .I3(\blk00000003/sig000012fc ), + .O(\blk00000003/sig00001188 ) + ); + LUT2 #( + .INIT ( 4'h6 )) + \blk00000003/blk000012e1 ( + .I0(\blk00000003/sig00001088 ), + .I1(\blk00000003/sig00001065 ), + .O(\blk00000003/sig0000110d ) + ); + LUT2 #( + .INIT ( 4'h6 )) + \blk00000003/blk000012e0 ( + .I0(\blk00000003/sig00001089 ), + .I1(\blk00000003/sig00001063 ), + .O(\blk00000003/sig00001110 ) + ); + LUT2 #( + .INIT ( 4'h6 )) + \blk00000003/blk000012df ( + .I0(\blk00000003/sig0000108a ), + .I1(\blk00000003/sig00001061 ), + .O(\blk00000003/sig00001113 ) + ); + LUT2 #( + .INIT ( 4'h6 )) + \blk00000003/blk000012de ( + .I0(\blk00000003/sig0000108b ), + .I1(\blk00000003/sig0000105f ), + .O(\blk00000003/sig00001116 ) + ); + LUT2 #( + .INIT ( 4'h6 )) + \blk00000003/blk000012dd ( + .I0(\blk00000003/sig0000108c ), + .I1(\blk00000003/sig0000105d ), + .O(\blk00000003/sig00001119 ) + ); + LUT2 #( + .INIT ( 4'h6 )) + \blk00000003/blk000012dc ( + .I0(\blk00000003/sig0000108d ), + .I1(\blk00000003/sig0000105b ), + .O(\blk00000003/sig0000111c ) + ); + LUT2 #( + .INIT ( 4'h6 )) + \blk00000003/blk000012db ( + .I0(\blk00000003/sig0000108e ), + .I1(\blk00000003/sig00001059 ), + .O(\blk00000003/sig0000111f ) + ); + LUT2 #( + .INIT ( 4'h6 )) + \blk00000003/blk000012da ( + .I0(\blk00000003/sig0000108f ), + .I1(\blk00000003/sig00001057 ), + .O(\blk00000003/sig00001122 ) + ); + LUT2 #( + .INIT ( 4'h6 )) + \blk00000003/blk000012d9 ( + .I0(\blk00000003/sig0000107d ), + .I1(\blk00000003/sig0000107b ), + .O(\blk00000003/sig000010e9 ) + ); + LUT2 #( + .INIT ( 4'h6 )) + \blk00000003/blk000012d8 ( + .I0(\blk00000003/sig00001090 ), + .I1(\blk00000003/sig00001055 ), + .O(\blk00000003/sig00001125 ) + ); + LUT2 #( + .INIT ( 4'h6 )) + \blk00000003/blk000012d7 ( + .I0(\blk00000003/sig0000107e ), + .I1(\blk00000003/sig00001079 ), + .O(\blk00000003/sig000010ef ) + ); + LUT2 #( + .INIT ( 4'h6 )) + \blk00000003/blk000012d6 ( + .I0(\blk00000003/sig0000107f ), + .I1(\blk00000003/sig00001077 ), + .O(\blk00000003/sig000010f2 ) + ); + LUT2 #( + .INIT ( 4'h6 )) + \blk00000003/blk000012d5 ( + .I0(\blk00000003/sig00001080 ), + .I1(\blk00000003/sig00001075 ), + .O(\blk00000003/sig000010f5 ) + ); + LUT2 #( + .INIT ( 4'h6 )) + \blk00000003/blk000012d4 ( + .I0(\blk00000003/sig00001081 ), + .I1(\blk00000003/sig00001073 ), + .O(\blk00000003/sig000010f8 ) + ); + LUT2 #( + .INIT ( 4'h6 )) + \blk00000003/blk000012d3 ( + .I0(\blk00000003/sig00001082 ), + .I1(\blk00000003/sig00001071 ), + .O(\blk00000003/sig000010fb ) + ); + LUT2 #( + .INIT ( 4'h6 )) + \blk00000003/blk000012d2 ( + .I0(\blk00000003/sig00001083 ), + .I1(\blk00000003/sig0000106f ), + .O(\blk00000003/sig000010fe ) + ); + LUT2 #( + .INIT ( 4'h6 )) + \blk00000003/blk000012d1 ( + .I0(\blk00000003/sig00001084 ), + .I1(\blk00000003/sig0000106d ), + .O(\blk00000003/sig00001101 ) + ); + LUT2 #( + .INIT ( 4'h6 )) + \blk00000003/blk000012d0 ( + .I0(\blk00000003/sig00001085 ), + .I1(\blk00000003/sig0000106b ), + .O(\blk00000003/sig00001104 ) + ); + LUT2 #( + .INIT ( 4'h6 )) + \blk00000003/blk000012cf ( + .I0(\blk00000003/sig00001086 ), + .I1(\blk00000003/sig00001069 ), + .O(\blk00000003/sig00001107 ) + ); + LUT2 #( + .INIT ( 4'h6 )) + \blk00000003/blk000012ce ( + .I0(\blk00000003/sig00001087 ), + .I1(\blk00000003/sig00001067 ), + .O(\blk00000003/sig0000110a ) + ); + LUT2 #( + .INIT ( 4'h6 )) + \blk00000003/blk000012cd ( + .I0(\blk00000003/sig00001091 ), + .I1(\blk00000003/sig00001053 ), + .O(\blk00000003/sig00001127 ) + ); + LUT2 #( + .INIT ( 4'h9 )) + \blk00000003/blk000012cc ( + .I0(\blk00000003/sig00001088 ), + .I1(\blk00000003/sig00001065 ), + .O(\blk00000003/sig000010cc ) + ); + LUT2 #( + .INIT ( 4'h9 )) + \blk00000003/blk000012cb ( + .I0(\blk00000003/sig00001089 ), + .I1(\blk00000003/sig00001063 ), + .O(\blk00000003/sig000010cf ) + ); + LUT2 #( + .INIT ( 4'h9 )) + \blk00000003/blk000012ca ( + .I0(\blk00000003/sig0000108a ), + .I1(\blk00000003/sig00001061 ), + .O(\blk00000003/sig000010d2 ) + ); + LUT2 #( + .INIT ( 4'h9 )) + \blk00000003/blk000012c9 ( + .I0(\blk00000003/sig0000108b ), + .I1(\blk00000003/sig0000105f ), + .O(\blk00000003/sig000010d5 ) + ); + LUT2 #( + .INIT ( 4'h9 )) + \blk00000003/blk000012c8 ( + .I0(\blk00000003/sig0000108c ), + .I1(\blk00000003/sig0000105d ), + .O(\blk00000003/sig000010d8 ) + ); + LUT2 #( + .INIT ( 4'h9 )) + \blk00000003/blk000012c7 ( + .I0(\blk00000003/sig0000108d ), + .I1(\blk00000003/sig0000105b ), + .O(\blk00000003/sig000010db ) + ); + LUT2 #( + .INIT ( 4'h9 )) + \blk00000003/blk000012c6 ( + .I0(\blk00000003/sig0000108e ), + .I1(\blk00000003/sig00001059 ), + .O(\blk00000003/sig000010de ) + ); + LUT2 #( + .INIT ( 4'h9 )) + \blk00000003/blk000012c5 ( + .I0(\blk00000003/sig0000108f ), + .I1(\blk00000003/sig00001057 ), + .O(\blk00000003/sig000010e1 ) + ); + LUT2 #( + .INIT ( 4'h9 )) + \blk00000003/blk000012c4 ( + .I0(\blk00000003/sig0000107d ), + .I1(\blk00000003/sig0000107b ), + .O(\blk00000003/sig000010a8 ) + ); + LUT2 #( + .INIT ( 4'h9 )) + \blk00000003/blk000012c3 ( + .I0(\blk00000003/sig00001090 ), + .I1(\blk00000003/sig00001055 ), + .O(\blk00000003/sig000010e4 ) + ); + LUT2 #( + .INIT ( 4'h9 )) + \blk00000003/blk000012c2 ( + .I0(\blk00000003/sig0000107e ), + .I1(\blk00000003/sig00001079 ), + .O(\blk00000003/sig000010ae ) + ); + LUT2 #( + .INIT ( 4'h9 )) + \blk00000003/blk000012c1 ( + .I0(\blk00000003/sig0000107f ), + .I1(\blk00000003/sig00001077 ), + .O(\blk00000003/sig000010b1 ) + ); + LUT2 #( + .INIT ( 4'h9 )) + \blk00000003/blk000012c0 ( + .I0(\blk00000003/sig00001080 ), + .I1(\blk00000003/sig00001075 ), + .O(\blk00000003/sig000010b4 ) + ); + LUT2 #( + .INIT ( 4'h9 )) + \blk00000003/blk000012bf ( + .I0(\blk00000003/sig00001081 ), + .I1(\blk00000003/sig00001073 ), + .O(\blk00000003/sig000010b7 ) + ); + LUT2 #( + .INIT ( 4'h9 )) + \blk00000003/blk000012be ( + .I0(\blk00000003/sig00001082 ), + .I1(\blk00000003/sig00001071 ), + .O(\blk00000003/sig000010ba ) + ); + LUT2 #( + .INIT ( 4'h9 )) + \blk00000003/blk000012bd ( + .I0(\blk00000003/sig00001083 ), + .I1(\blk00000003/sig0000106f ), + .O(\blk00000003/sig000010bd ) + ); + LUT2 #( + .INIT ( 4'h9 )) + \blk00000003/blk000012bc ( + .I0(\blk00000003/sig00001084 ), + .I1(\blk00000003/sig0000106d ), + .O(\blk00000003/sig000010c0 ) + ); + LUT2 #( + .INIT ( 4'h9 )) + \blk00000003/blk000012bb ( + .I0(\blk00000003/sig00001085 ), + .I1(\blk00000003/sig0000106b ), + .O(\blk00000003/sig000010c3 ) + ); + LUT2 #( + .INIT ( 4'h9 )) + \blk00000003/blk000012ba ( + .I0(\blk00000003/sig00001086 ), + .I1(\blk00000003/sig00001069 ), + .O(\blk00000003/sig000010c6 ) + ); + LUT2 #( + .INIT ( 4'h9 )) + \blk00000003/blk000012b9 ( + .I0(\blk00000003/sig00001087 ), + .I1(\blk00000003/sig00001067 ), + .O(\blk00000003/sig000010c9 ) + ); + LUT2 #( + .INIT ( 4'h9 )) + \blk00000003/blk000012b8 ( + .I0(\blk00000003/sig00001091 ), + .I1(\blk00000003/sig00001053 ), + .O(\blk00000003/sig000010e6 ) + ); + LUT3 #( + .INIT ( 8'hD8 )) + \blk00000003/blk000012b7 ( + .I0(\blk00000003/sig000008d5 ), + .I1(\blk00000003/sig00000fa0 ), + .I2(\blk00000003/sig000010a5 ), + .O(\blk00000003/sig00001054 ) + ); + LUT3 #( + .INIT ( 8'hD8 )) + \blk00000003/blk000012b6 ( + .I0(\blk00000003/sig000008d5 ), + .I1(\blk00000003/sig00000fa1 ), + .I2(\blk00000003/sig000010a6 ), + .O(\blk00000003/sig00001052 ) + ); + LUT3 #( + .INIT ( 8'hD8 )) + \blk00000003/blk000012b5 ( + .I0(\blk00000003/sig000008d5 ), + .I1(\blk00000003/sig00000eeb ), + .I2(\blk00000003/sig000010a2 ), + .O(\blk00000003/sig0000105a ) + ); + LUT3 #( + .INIT ( 8'hD8 )) + \blk00000003/blk000012b4 ( + .I0(\blk00000003/sig000008d5 ), + .I1(\blk00000003/sig00000eed ), + .I2(\blk00000003/sig000010a4 ), + .O(\blk00000003/sig00001056 ) + ); + LUT3 #( + .INIT ( 8'hD8 )) + \blk00000003/blk000012b3 ( + .I0(\blk00000003/sig000008d5 ), + .I1(\blk00000003/sig00000eec ), + .I2(\blk00000003/sig000010a3 ), + .O(\blk00000003/sig00001058 ) + ); + LUT3 #( + .INIT ( 8'hD8 )) + \blk00000003/blk000012b2 ( + .I0(\blk00000003/sig000008d5 ), + .I1(\blk00000003/sig00000ee8 ), + .I2(\blk00000003/sig0000109f ), + .O(\blk00000003/sig00001060 ) + ); + LUT3 #( + .INIT ( 8'hD8 )) + \blk00000003/blk000012b1 ( + .I0(\blk00000003/sig000008d5 ), + .I1(\blk00000003/sig00000eea ), + .I2(\blk00000003/sig000010a1 ), + .O(\blk00000003/sig0000105c ) + ); + LUT3 #( + .INIT ( 8'hD8 )) + \blk00000003/blk000012b0 ( + .I0(\blk00000003/sig000008d5 ), + .I1(\blk00000003/sig00000ee9 ), + .I2(\blk00000003/sig000010a0 ), + .O(\blk00000003/sig0000105e ) + ); + LUT3 #( + .INIT ( 8'hD8 )) + \blk00000003/blk000012af ( + .I0(\blk00000003/sig000008d5 ), + .I1(\blk00000003/sig00000ee5 ), + .I2(\blk00000003/sig0000109c ), + .O(\blk00000003/sig00001066 ) + ); + LUT3 #( + .INIT ( 8'hD8 )) + \blk00000003/blk000012ae ( + .I0(\blk00000003/sig000008d5 ), + .I1(\blk00000003/sig00000ee7 ), + .I2(\blk00000003/sig0000109e ), + .O(\blk00000003/sig00001062 ) + ); + LUT3 #( + .INIT ( 8'hD8 )) + \blk00000003/blk000012ad ( + .I0(\blk00000003/sig000008d5 ), + .I1(\blk00000003/sig00000ee6 ), + .I2(\blk00000003/sig0000109d ), + .O(\blk00000003/sig00001064 ) + ); + LUT3 #( + .INIT ( 8'hD8 )) + \blk00000003/blk000012ac ( + .I0(\blk00000003/sig000008d5 ), + .I1(\blk00000003/sig00000ee2 ), + .I2(\blk00000003/sig00001099 ), + .O(\blk00000003/sig0000106c ) + ); + LUT3 #( + .INIT ( 8'hD8 )) + \blk00000003/blk000012ab ( + .I0(\blk00000003/sig000008d5 ), + .I1(\blk00000003/sig00000ee4 ), + .I2(\blk00000003/sig0000109b ), + .O(\blk00000003/sig00001068 ) + ); + LUT3 #( + .INIT ( 8'hD8 )) + \blk00000003/blk000012aa ( + .I0(\blk00000003/sig000008d5 ), + .I1(\blk00000003/sig00000ee3 ), + .I2(\blk00000003/sig0000109a ), + .O(\blk00000003/sig0000106a ) + ); + LUT3 #( + .INIT ( 8'hD8 )) + \blk00000003/blk000012a9 ( + .I0(\blk00000003/sig000008d5 ), + .I1(\blk00000003/sig00000edf ), + .I2(\blk00000003/sig00001096 ), + .O(\blk00000003/sig00001072 ) + ); + LUT3 #( + .INIT ( 8'hD8 )) + \blk00000003/blk000012a8 ( + .I0(\blk00000003/sig000008d5 ), + .I1(\blk00000003/sig00000ee1 ), + .I2(\blk00000003/sig00001098 ), + .O(\blk00000003/sig0000106e ) + ); + LUT3 #( + .INIT ( 8'hD8 )) + \blk00000003/blk000012a7 ( + .I0(\blk00000003/sig000008d5 ), + .I1(\blk00000003/sig00000ee0 ), + .I2(\blk00000003/sig00001097 ), + .O(\blk00000003/sig00001070 ) + ); + LUT3 #( + .INIT ( 8'hD8 )) + \blk00000003/blk000012a6 ( + .I0(\blk00000003/sig000008d5 ), + .I1(\blk00000003/sig00000edc ), + .I2(\blk00000003/sig00001093 ), + .O(\blk00000003/sig00001078 ) + ); + LUT3 #( + .INIT ( 8'hD8 )) + \blk00000003/blk000012a5 ( + .I0(\blk00000003/sig000008d5 ), + .I1(\blk00000003/sig00000ede ), + .I2(\blk00000003/sig00001095 ), + .O(\blk00000003/sig00001074 ) + ); + LUT3 #( + .INIT ( 8'hD8 )) + \blk00000003/blk000012a4 ( + .I0(\blk00000003/sig000008d5 ), + .I1(\blk00000003/sig00000edd ), + .I2(\blk00000003/sig00001094 ), + .O(\blk00000003/sig00001076 ) + ); + LUT3 #( + .INIT ( 8'hD8 )) + \blk00000003/blk000012a3 ( + .I0(\blk00000003/sig000008d5 ), + .I1(\blk00000003/sig000010a5 ), + .I2(\blk00000003/sig00000fa0 ), + .O(\blk00000003/sig0000102a ) + ); + LUT3 #( + .INIT ( 8'hD8 )) + \blk00000003/blk000012a2 ( + .I0(\blk00000003/sig000008d5 ), + .I1(\blk00000003/sig00000edb ), + .I2(\blk00000003/sig00001092 ), + .O(\blk00000003/sig0000107a ) + ); + LUT3 #( + .INIT ( 8'hD8 )) + \blk00000003/blk000012a1 ( + .I0(\blk00000003/sig000008d5 ), + .I1(\blk00000003/sig000010a6 ), + .I2(\blk00000003/sig00000fa1 ), + .O(\blk00000003/sig00001028 ) + ); + LUT3 #( + .INIT ( 8'hD8 )) + \blk00000003/blk000012a0 ( + .I0(\blk00000003/sig000008d5 ), + .I1(\blk00000003/sig000010a2 ), + .I2(\blk00000003/sig00000eeb ), + .O(\blk00000003/sig00001030 ) + ); + LUT3 #( + .INIT ( 8'hD8 )) + \blk00000003/blk0000129f ( + .I0(\blk00000003/sig000008d5 ), + .I1(\blk00000003/sig000010a4 ), + .I2(\blk00000003/sig00000eed ), + .O(\blk00000003/sig0000102c ) + ); + LUT3 #( + .INIT ( 8'hD8 )) + \blk00000003/blk0000129e ( + .I0(\blk00000003/sig000008d5 ), + .I1(\blk00000003/sig000010a3 ), + .I2(\blk00000003/sig00000eec ), + .O(\blk00000003/sig0000102e ) + ); + LUT3 #( + .INIT ( 8'hD8 )) + \blk00000003/blk0000129d ( + .I0(\blk00000003/sig000008d5 ), + .I1(\blk00000003/sig0000109f ), + .I2(\blk00000003/sig00000ee8 ), + .O(\blk00000003/sig00001036 ) + ); + LUT3 #( + .INIT ( 8'hD8 )) + \blk00000003/blk0000129c ( + .I0(\blk00000003/sig000008d5 ), + .I1(\blk00000003/sig000010a1 ), + .I2(\blk00000003/sig00000eea ), + .O(\blk00000003/sig00001032 ) + ); + LUT3 #( + .INIT ( 8'hD8 )) + \blk00000003/blk0000129b ( + .I0(\blk00000003/sig000008d5 ), + .I1(\blk00000003/sig000010a0 ), + .I2(\blk00000003/sig00000ee9 ), + .O(\blk00000003/sig00001034 ) + ); + LUT3 #( + .INIT ( 8'hD8 )) + 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16'hC3AA )) + \blk00000003/blk000011c0 ( + .I0(\blk00000003/sig000008bc ), + .I1(\blk00000003/sig0000077b ), + .I2(\blk00000003/sig00000a31 ), + .I3(\blk00000003/sig00000a33 ), + .O(\blk00000003/sig0000092c ) + ); + LUT4 #( + .INIT ( 16'h3CAA )) + \blk00000003/blk000011bf ( + .I0(\blk00000003/sig0000077b ), + .I1(\blk00000003/sig000008bc ), + .I2(\blk00000003/sig00000a31 ), + .I3(\blk00000003/sig00000a33 ), + .O(\blk00000003/sig000008ec ) + ); + LUT4 #( + .INIT ( 16'hC3AA )) + \blk00000003/blk000011be ( + .I0(\blk00000003/sig000008bd ), + .I1(\blk00000003/sig00000779 ), + .I2(\blk00000003/sig00000a31 ), + .I3(\blk00000003/sig00000a33 ), + .O(\blk00000003/sig00000929 ) + ); + LUT4 #( + .INIT ( 16'h3CAA )) + \blk00000003/blk000011bd ( + .I0(\blk00000003/sig00000779 ), + .I1(\blk00000003/sig000008bd ), + .I2(\blk00000003/sig00000a31 ), + .I3(\blk00000003/sig00000a33 ), + .O(\blk00000003/sig000008e9 ) + ); + LUT4 #( + .INIT ( 16'hC3AA )) + \blk00000003/blk000011bc ( + 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.I1(\blk00000003/sig000007e5 ), + .O(\blk00000003/sig00000810 ) + ); + LUT2 #( + .INIT ( 4'h9 )) + \blk00000003/blk00001199 ( + .I0(\blk00000003/sig000007e9 ), + .I1(\blk00000003/sig000007e3 ), + .O(\blk00000003/sig00000816 ) + ); + LUT2 #( + .INIT ( 4'h9 )) + \blk00000003/blk00001198 ( + .I0(\blk00000003/sig000007ea ), + .I1(\blk00000003/sig000007e1 ), + .O(\blk00000003/sig00000819 ) + ); + LUT2 #( + .INIT ( 4'h9 )) + \blk00000003/blk00001197 ( + .I0(\blk00000003/sig000007eb ), + .I1(\blk00000003/sig000007df ), + .O(\blk00000003/sig0000081c ) + ); + LUT2 #( + .INIT ( 4'h9 )) + \blk00000003/blk00001196 ( + .I0(\blk00000003/sig000007ec ), + .I1(\blk00000003/sig000007dd ), + .O(\blk00000003/sig0000081f ) + ); + LUT2 #( + .INIT ( 4'h9 )) + \blk00000003/blk00001195 ( + .I0(\blk00000003/sig000007ed ), + .I1(\blk00000003/sig000007db ), + .O(\blk00000003/sig00000822 ) + ); + LUT2 #( + .INIT ( 4'h9 )) + \blk00000003/blk00001194 ( + .I0(\blk00000003/sig000007ee ), + .I1(\blk00000003/sig000007d9 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.I0(\blk00000003/sig000002ba ), + .I1(\blk00000003/sig00000365 ), + .I2(\blk00000003/sig0000029c ), + .O(\blk00000003/sig00000421 ) + ); + LUT3 #( + .INIT ( 8'h9A )) + \blk00000003/blk00001085 ( + .I0(\blk00000003/sig000002bb ), + .I1(\blk00000003/sig00000366 ), + .I2(\blk00000003/sig0000029c ), + .O(\blk00000003/sig00000436 ) + ); + LUT3 #( + .INIT ( 8'h9A )) + \blk00000003/blk00001084 ( + .I0(\blk00000003/sig000002ad ), + .I1(\blk00000003/sig00000357 ), + .I2(\blk00000003/sig0000029c ), + .O(\blk00000003/sig00000424 ) + ); + LUT3 #( + .INIT ( 8'h9A )) + \blk00000003/blk00001083 ( + .I0(\blk00000003/sig000002ad ), + .I1(\blk00000003/sig00000357 ), + .I2(\blk00000003/sig0000029c ), + .O(\blk00000003/sig000003f7 ) + ); + LUT3 #( + .INIT ( 8'h9A )) + \blk00000003/blk00001082 ( + .I0(\blk00000003/sig000002ad ), + .I1(\blk00000003/sig00000358 ), + .I2(\blk00000003/sig0000029c ), + .O(\blk00000003/sig000003fa ) + ); + LUT3 #( + .INIT ( 8'h9A )) + \blk00000003/blk00001081 ( + .I0(\blk00000003/sig000002ae ), + .I1(\blk00000003/sig00000359 ), + .I2(\blk00000003/sig0000029c ), + .O(\blk00000003/sig000003fd ) + ); + LUT3 #( + .INIT ( 8'h9A )) + \blk00000003/blk00001080 ( + .I0(\blk00000003/sig000002af ), + .I1(\blk00000003/sig0000035a ), + .I2(\blk00000003/sig0000029c ), + .O(\blk00000003/sig00000400 ) + ); + LUT3 #( + .INIT ( 8'h9A )) + \blk00000003/blk0000107f ( + .I0(\blk00000003/sig000002b0 ), + .I1(\blk00000003/sig0000035b ), + .I2(\blk00000003/sig0000029c ), + .O(\blk00000003/sig00000403 ) + ); + LUT3 #( + .INIT ( 8'h9A )) + \blk00000003/blk0000107e ( + .I0(\blk00000003/sig000002b1 ), + .I1(\blk00000003/sig0000035c ), + .I2(\blk00000003/sig0000029c ), + .O(\blk00000003/sig00000406 ) + ); + LUT3 #( + .INIT ( 8'h9A )) + \blk00000003/blk0000107d ( + .I0(\blk00000003/sig000002b2 ), + .I1(\blk00000003/sig0000035d ), + .I2(\blk00000003/sig0000029c ), + .O(\blk00000003/sig00000409 ) + ); + LUT3 #( + .INIT ( 8'h9A )) + \blk00000003/blk0000107c ( + .I0(\blk00000003/sig000002bc ), + .I1(\blk00000003/sig00000367 ), + .I2(\blk00000003/sig0000029c ), + .O(\blk00000003/sig0000043a ) + ); + LUT3 #( + .INIT ( 8'h6A )) + \blk00000003/blk0000107b ( + .I0(\blk00000003/sig0000034d ), + .I1(\blk00000003/sig000002a3 ), + .I2(\blk00000003/sig0000029c ), + .O(\blk00000003/sig000003b6 ) + ); + LUT3 #( + .INIT ( 8'h6A )) + \blk00000003/blk0000107a ( + .I0(\blk00000003/sig0000034e ), + .I1(\blk00000003/sig000002a4 ), + .I2(\blk00000003/sig0000029c ), + .O(\blk00000003/sig000003b9 ) + ); + LUT3 #( + .INIT ( 8'h6A )) + \blk00000003/blk00001079 ( + .I0(\blk00000003/sig0000034f ), + .I1(\blk00000003/sig000002a5 ), + .I2(\blk00000003/sig0000029c ), + .O(\blk00000003/sig000003bc ) + ); + LUT3 #( + .INIT ( 8'h6A )) + \blk00000003/blk00001078 ( + .I0(\blk00000003/sig00000350 ), + .I1(\blk00000003/sig000002a6 ), + .I2(\blk00000003/sig0000029c ), + .O(\blk00000003/sig000003bf ) + ); + LUT3 #( + .INIT ( 8'h6A )) + \blk00000003/blk00001077 ( + .I0(\blk00000003/sig00000351 ), + .I1(\blk00000003/sig000002a7 ), + .I2(\blk00000003/sig0000029c ), + .O(\blk00000003/sig000003c2 ) + ); + LUT3 #( + .INIT ( 8'h6A )) + \blk00000003/blk00001076 ( + .I0(\blk00000003/sig00000352 ), + .I1(\blk00000003/sig000002a8 ), + .I2(\blk00000003/sig0000029c ), + .O(\blk00000003/sig000003c5 ) + ); + LUT3 #( + .INIT ( 8'h6A )) + \blk00000003/blk00001075 ( + .I0(\blk00000003/sig00000353 ), + .I1(\blk00000003/sig000002a9 ), + .I2(\blk00000003/sig0000029c ), + .O(\blk00000003/sig000003c8 ) + ); + LUT3 #( + .INIT ( 8'h6A )) + \blk00000003/blk00001074 ( + .I0(\blk00000003/sig00000354 ), + .I1(\blk00000003/sig000002aa ), + .I2(\blk00000003/sig0000029c ), + .O(\blk00000003/sig000003cb ) + ); + LUT3 #( + .INIT ( 8'h6A )) + \blk00000003/blk00001073 ( + .I0(\blk00000003/sig00000355 ), + .I1(\blk00000003/sig000002ab ), + .I2(\blk00000003/sig0000029c ), + .O(\blk00000003/sig000003ce ) + ); + LUT3 #( + .INIT ( 8'h6A )) + \blk00000003/blk00001072 ( + .I0(\blk00000003/sig00000346 ), + .I1(\blk00000003/sig0000029d ), + .I2(\blk00000003/sig0000029c ), + .O(\blk00000003/sig0000039e ) + ); + LUT3 #( + .INIT ( 8'h6A )) + \blk00000003/blk00001071 ( + .I0(\blk00000003/sig00000347 ), + .I1(\blk00000003/sig0000029d ), + .I2(\blk00000003/sig0000029c ), + .O(\blk00000003/sig000003a4 ) + ); + LUT3 #( + .INIT ( 8'h6A )) + \blk00000003/blk00001070 ( + .I0(\blk00000003/sig00000348 ), + .I1(\blk00000003/sig0000029e ), + .I2(\blk00000003/sig0000029c ), + .O(\blk00000003/sig000003a7 ) + ); + LUT3 #( + .INIT ( 8'h6A )) + \blk00000003/blk0000106f ( + .I0(\blk00000003/sig00000349 ), + .I1(\blk00000003/sig0000029f ), + .I2(\blk00000003/sig0000029c ), + .O(\blk00000003/sig000003aa ) + ); + LUT3 #( + .INIT ( 8'h6A )) + \blk00000003/blk0000106e ( + .I0(\blk00000003/sig0000034a ), + .I1(\blk00000003/sig000002a0 ), + .I2(\blk00000003/sig0000029c ), + .O(\blk00000003/sig000003ad ) + ); + LUT3 #( + .INIT ( 8'h6A )) + \blk00000003/blk0000106d ( + .I0(\blk00000003/sig0000034b ), + .I1(\blk00000003/sig000002a1 ), + .I2(\blk00000003/sig0000029c ), + .O(\blk00000003/sig000003b0 ) + ); + LUT3 #( + .INIT ( 8'h6A )) + \blk00000003/blk0000106c ( + .I0(\blk00000003/sig0000034c ), + .I1(\blk00000003/sig000002a2 ), + .I2(\blk00000003/sig0000029c ), + .O(\blk00000003/sig000003b3 ) + ); + LUT3 #( + .INIT ( 8'h6A )) + \blk00000003/blk0000106b ( + .I0(\blk00000003/sig00000356 ), + .I1(\blk00000003/sig000002ac ), + .I2(\blk00000003/sig0000029c ), + .O(\blk00000003/sig000003d0 ) + ); + LUT3 #( + .INIT ( 8'h6A )) + \blk00000003/blk0000106a ( + .I0(\blk00000003/sig0000035e ), + .I1(\blk00000003/sig000002b3 ), + .I2(\blk00000003/sig0000029c ), + .O(\blk00000003/sig00000381 ) + ); + LUT3 #( + .INIT ( 8'h6A )) + \blk00000003/blk00001069 ( + .I0(\blk00000003/sig0000035f ), + .I1(\blk00000003/sig000002b4 ), + .I2(\blk00000003/sig0000029c ), + .O(\blk00000003/sig00000384 ) + ); + LUT3 #( + .INIT ( 8'h6A )) + \blk00000003/blk00001068 ( + .I0(\blk00000003/sig00000360 ), + .I1(\blk00000003/sig000002b5 ), + .I2(\blk00000003/sig0000029c ), + .O(\blk00000003/sig00000387 ) + ); + LUT3 #( + .INIT ( 8'h6A )) + \blk00000003/blk00001067 ( + .I0(\blk00000003/sig00000361 ), + .I1(\blk00000003/sig000002b6 ), + .I2(\blk00000003/sig0000029c ), + .O(\blk00000003/sig0000038a ) + ); + LUT3 #( + .INIT ( 8'h6A )) + \blk00000003/blk00001066 ( + .I0(\blk00000003/sig00000362 ), + .I1(\blk00000003/sig000002b7 ), + .I2(\blk00000003/sig0000029c ), + .O(\blk00000003/sig0000038d ) + ); + LUT3 #( + .INIT ( 8'h6A )) + \blk00000003/blk00001065 ( + .I0(\blk00000003/sig00000363 ), + .I1(\blk00000003/sig000002b8 ), + .I2(\blk00000003/sig0000029c ), + .O(\blk00000003/sig00000390 ) + ); + LUT3 #( + .INIT ( 8'h6A )) + \blk00000003/blk00001064 ( + .I0(\blk00000003/sig00000364 ), + .I1(\blk00000003/sig000002b9 ), + .I2(\blk00000003/sig0000029c ), + .O(\blk00000003/sig00000393 ) + ); + LUT3 #( + .INIT ( 8'h6A )) + \blk00000003/blk00001063 ( + .I0(\blk00000003/sig00000365 ), + .I1(\blk00000003/sig000002ba ), + .I2(\blk00000003/sig0000029c ), + .O(\blk00000003/sig00000396 ) + ); + LUT3 #( + .INIT ( 8'h6A )) + \blk00000003/blk00001062 ( + .I0(\blk00000003/sig00000366 ), + .I1(\blk00000003/sig000002bb ), + .I2(\blk00000003/sig0000029c ), + .O(\blk00000003/sig00000399 ) + ); + LUT3 #( + .INIT ( 8'h6A )) + \blk00000003/blk00001061 ( + .I0(\blk00000003/sig00000357 ), + .I1(\blk00000003/sig000002ad ), + .I2(\blk00000003/sig0000029c ), + .O(\blk00000003/sig00000369 ) + ); + LUT3 #( + .INIT ( 8'h6A )) + \blk00000003/blk00001060 ( + .I0(\blk00000003/sig00000358 ), + .I1(\blk00000003/sig000002ad ), + .I2(\blk00000003/sig0000029c ), + .O(\blk00000003/sig0000036f ) + ); + LUT3 #( + .INIT ( 8'h6A )) + \blk00000003/blk0000105f ( + .I0(\blk00000003/sig00000359 ), + .I1(\blk00000003/sig000002ae ), + .I2(\blk00000003/sig0000029c ), + .O(\blk00000003/sig00000372 ) + ); + LUT3 #( + .INIT ( 8'h6A )) + \blk00000003/blk0000105e ( + .I0(\blk00000003/sig0000035a ), + .I1(\blk00000003/sig000002af ), + .I2(\blk00000003/sig0000029c ), + .O(\blk00000003/sig00000375 ) + ); + LUT3 #( + .INIT ( 8'h6A )) + \blk00000003/blk0000105d ( + .I0(\blk00000003/sig0000035b ), + .I1(\blk00000003/sig000002b0 ), + .I2(\blk00000003/sig0000029c ), + .O(\blk00000003/sig00000378 ) + ); + LUT3 #( + .INIT ( 8'h6A )) + \blk00000003/blk0000105c ( + .I0(\blk00000003/sig0000035c ), + .I1(\blk00000003/sig000002b1 ), + .I2(\blk00000003/sig0000029c ), + .O(\blk00000003/sig0000037b ) + ); + LUT3 #( + .INIT ( 8'h6A )) + \blk00000003/blk0000105b ( + .I0(\blk00000003/sig0000035d ), + .I1(\blk00000003/sig000002b2 ), + .I2(\blk00000003/sig0000029c ), + .O(\blk00000003/sig0000037e ) + ); + LUT3 #( + .INIT ( 8'h6A )) + \blk00000003/blk0000105a ( + .I0(\blk00000003/sig00000367 ), + .I1(\blk00000003/sig000002bc ), + .I2(\blk00000003/sig0000029c ), + .O(\blk00000003/sig0000039b ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \blk00000003/blk00001059 ( + .I0(\blk00000003/sig00000298 ), + .I1(\blk00000003/sig00000270 ), + .O(\blk00000003/sig00000286 ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \blk00000003/blk00001058 ( + .I0(\blk00000003/sig00000298 ), + .I1(\blk00000003/sig00000272 ), + .O(\blk00000003/sig00000284 ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \blk00000003/blk00001057 ( + .I0(\blk00000003/sig00000298 ), + .I1(\blk00000003/sig00000274 ), + .O(\blk00000003/sig00000282 ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \blk00000003/blk00001056 ( + .I0(\blk00000003/sig00000298 ), + .I1(\blk00000003/sig00000276 ), + .O(\blk00000003/sig00000280 ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \blk00000003/blk00001055 ( + .I0(\blk00000003/sig00000298 ), + .I1(\blk00000003/sig00000278 ), + .O(\blk00000003/sig0000027e ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \blk00000003/blk00001054 ( + .I0(\blk00000003/sig00000298 ), + .I1(\blk00000003/sig0000027a ), + .O(\blk00000003/sig0000027c ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \blk00000003/blk00001053 ( + .I0(\blk00000003/sig0000026b ), + .I1(\blk00000003/sig00000167 ), + .O(\blk00000003/sig00000259 ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \blk00000003/blk00001052 ( + .I0(\blk00000003/sig0000026b ), + .I1(\blk00000003/sig00000168 ), + .O(\blk00000003/sig00000257 ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \blk00000003/blk00001051 ( + .I0(\blk00000003/sig0000026b ), + .I1(\blk00000003/sig00000169 ), + .O(\blk00000003/sig00000255 ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \blk00000003/blk00001050 ( + .I0(\blk00000003/sig0000026b ), + .I1(\blk00000003/sig0000016a ), + .O(\blk00000003/sig00000253 ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \blk00000003/blk0000104f ( + .I0(\blk00000003/sig0000026b ), + .I1(\blk00000003/sig0000016b ), + .O(\blk00000003/sig00000251 ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \blk00000003/blk0000104e ( + .I0(\blk00000003/sig0000026b ), + .I1(\blk00000003/sig0000016c ), + .O(\blk00000003/sig0000024f ) + ); + LUT3 #( + .INIT ( 8'hD8 )) + \blk00000003/blk0000104d ( + .I0(\blk00000003/sig000000a7 ), + .I1(\blk00000003/sig0000012f ), + .I2(\blk00000003/sig00000244 ), + .O(\blk00000003/sig00000243 ) + ); + LUT3 #( + .INIT ( 8'hF2 )) + \blk00000003/blk0000104c ( + .I0(NlwRenamedSig_OI_rfd), + .I1(\blk00000003/sig0000012c ), + .I2(start), + .O(\blk00000003/sig00000130 ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \blk00000003/blk0000104b ( + .I0(\blk00000003/sig0000012c ), + .I1(NlwRenamedSig_OI_xn_index[5]), + .O(\blk00000003/sig00000134 ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \blk00000003/blk0000104a ( + .I0(\blk00000003/sig0000012c ), + .I1(NlwRenamedSig_OI_xn_index[4]), + .O(\blk00000003/sig00000137 ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \blk00000003/blk00001049 ( + .I0(\blk00000003/sig0000012c ), + .I1(NlwRenamedSig_OI_xn_index[3]), + .O(\blk00000003/sig0000013a ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \blk00000003/blk00001048 ( + .I0(\blk00000003/sig0000012c ), + .I1(NlwRenamedSig_OI_xn_index[2]), + .O(\blk00000003/sig0000013d ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \blk00000003/blk00001047 ( + .I0(\blk00000003/sig0000012c ), + .I1(NlwRenamedSig_OI_xn_index[1]), + .O(\blk00000003/sig00000140 ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \blk00000003/blk00001046 ( + .I0(\blk00000003/sig0000012c ), + .I1(NlwRenamedSig_OI_xn_index[0]), + .O(\blk00000003/sig00000142 ) + ); + LUT3 #( + .INIT ( 8'hA2 )) + \blk00000003/blk00001045 ( + .I0(start), + .I1(NlwRenamedSig_OI_rfd), + .I2(\blk00000003/sig0000012c ), + .O(\blk00000003/sig00000131 ) + ); + LUT3 #( + .INIT ( 8'hD8 )) + \blk00000003/blk00001044 ( + .I0(\blk00000003/sig000000a2 ), + .I1(\blk00000003/sig000000f5 ), + .I2(\blk00000003/sig00000094 ), + .O(\blk00000003/sig000000e6 ) + ); + LUT3 #( + .INIT ( 8'hD8 )) + \blk00000003/blk00001043 ( + .I0(\blk00000003/sig000000a2 ), + .I1(\blk00000003/sig000000f6 ), + .I2(\blk00000003/sig00000093 ), + .O(\blk00000003/sig000000e8 ) + ); + LUT3 #( + .INIT ( 8'hD8 )) + \blk00000003/blk00001042 ( + .I0(\blk00000003/sig000000a2 ), + .I1(\blk00000003/sig000000f7 ), + .I2(\blk00000003/sig00000092 ), + .O(\blk00000003/sig000000ea ) + ); + LUT3 #( + .INIT ( 8'hD8 )) + \blk00000003/blk00001041 ( + .I0(\blk00000003/sig000000a2 ), + .I1(\blk00000003/sig000000f8 ), + .I2(\blk00000003/sig00000091 ), + .O(\blk00000003/sig000000ec ) + ); + LUT3 #( + .INIT ( 8'hD8 )) + \blk00000003/blk00001040 ( + .I0(\blk00000003/sig000000a2 ), + .I1(\blk00000003/sig000000f9 ), + .I2(\blk00000003/sig00000090 ), + .O(\blk00000003/sig000000ee ) + ); + LUT3 #( + .INIT ( 8'hD8 )) + \blk00000003/blk0000103f ( + .I0(\blk00000003/sig000000a2 ), + .I1(\blk00000003/sig000000fa ), + .I2(\blk00000003/sig0000008f ), + .O(\blk00000003/sig000000f0 ) + ); + LUT3 #( + .INIT ( 8'hD8 )) + \blk00000003/blk0000103e ( + .I0(\blk00000003/sig000000a4 ), + .I1(\blk00000003/sig00000095 ), + .I2(\blk00000003/sig000000a0 ), + .O(\blk00000003/sig000000da ) + ); + LUT3 #( + .INIT ( 8'hD8 )) + \blk00000003/blk0000103d ( + .I0(\blk00000003/sig000000a4 ), + .I1(\blk00000003/sig00000096 ), + .I2(\blk00000003/sig0000009f ), + .O(\blk00000003/sig000000dc ) + ); + LUT3 #( + .INIT ( 8'hD8 )) + \blk00000003/blk0000103c ( + .I0(\blk00000003/sig000000a4 ), + .I1(\blk00000003/sig00000097 ), + .I2(\blk00000003/sig0000009e ), + .O(\blk00000003/sig000000de ) + ); + LUT3 #( + .INIT ( 8'hD8 )) + \blk00000003/blk0000103b ( + .I0(\blk00000003/sig000000a4 ), + .I1(\blk00000003/sig00000098 ), + .I2(\blk00000003/sig0000009d ), + .O(\blk00000003/sig000000e0 ) + ); + LUT3 #( + .INIT ( 8'hD8 )) + \blk00000003/blk0000103a ( + .I0(\blk00000003/sig000000a4 ), + .I1(\blk00000003/sig00000099 ), + .I2(\blk00000003/sig0000009c ), + .O(\blk00000003/sig000000e2 ) + ); + LUT3 #( + .INIT ( 8'hD8 )) + \blk00000003/blk00001039 ( + .I0(\blk00000003/sig000000a4 ), + .I1(\blk00000003/sig0000009a ), + .I2(\blk00000003/sig0000009b ), + .O(\blk00000003/sig000000e4 ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \blk00000003/blk00001038 ( + .I0(\blk00000003/sig0000007a ), + .I1(\blk00000003/sig0000008a ), + .O(\blk00000003/sig00000156 ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \blk00000003/blk00001037 ( + .I0(\blk00000003/sig0000007a ), + .I1(\blk00000003/sig00000089 ), + .O(\blk00000003/sig00000159 ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \blk00000003/blk00001036 ( + .I0(\blk00000003/sig0000007a ), + .I1(\blk00000003/sig00000088 ), + .O(\blk00000003/sig0000015c ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \blk00000003/blk00001035 ( + .I0(\blk00000003/sig0000007a ), + .I1(\blk00000003/sig00000087 ), + .O(\blk00000003/sig0000015f ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \blk00000003/blk00001034 ( + .I0(\blk00000003/sig0000007a ), + .I1(\blk00000003/sig00000086 ), + .O(\blk00000003/sig00000162 ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \blk00000003/blk00001033 ( + .I0(\blk00000003/sig0000007a ), + .I1(\blk00000003/sig00000085 ), + .O(\blk00000003/sig00000164 ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \blk00000003/blk00001032 ( + .I0(\blk00000003/sig00000068 ), + .I1(\blk00000003/sig00000078 ), + .O(\blk00000003/sig00000145 ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \blk00000003/blk00001031 ( + .I0(\blk00000003/sig00000068 ), + .I1(\blk00000003/sig00000077 ), + .O(\blk00000003/sig00000148 ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \blk00000003/blk00001030 ( + .I0(\blk00000003/sig00000068 ), + .I1(\blk00000003/sig00000076 ), + .O(\blk00000003/sig0000014b ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \blk00000003/blk0000102f ( + .I0(\blk00000003/sig00000068 ), + .I1(\blk00000003/sig00000075 ), + .O(\blk00000003/sig0000014e ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \blk00000003/blk0000102e ( + .I0(\blk00000003/sig00000068 ), + .I1(\blk00000003/sig00000074 ), + .O(\blk00000003/sig00000151 ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \blk00000003/blk0000102d ( + .I0(\blk00000003/sig00000068 ), + .I1(\blk00000003/sig00000073 ), + .O(\blk00000003/sig00000153 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000102c ( + .C(clk), + .CE(\blk00000003/sig00001472 ), + .D(\blk00000003/sig0000147a ), + .R(\blk00000003/sig0000005f ), + .Q(busy) + ); + FDR #( + .INIT ( 1'b0 )) + \blk00000003/blk0000102b ( + .C(clk), + .D(\blk00000003/sig00001471 ), + .R(\blk00000003/sig0000005f ), + .Q(\blk00000003/sig00001479 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000102a ( + .C(clk), + .CE(\blk00000003/sig00001472 ), + .D(\blk00000003/sig00001477 ), + .R(\blk00000003/sig0000005f ), + .Q(\blk00000003/sig00001478 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00001029 ( + .C(clk), + .CE(\blk00000003/sig00001472 ), + .D(\blk00000003/sig00001475 ), + .R(\blk00000003/sig0000005f ), + .Q(\blk00000003/sig00001476 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00001028 ( + .C(clk), + .CE(\blk00000003/sig00001472 ), + .D(\blk00000003/sig00001473 ), + .R(\blk00000003/sig0000005f ), + .Q(\blk00000003/sig00001474 ) + ); + FDR #( + .INIT ( 1'b0 )) + \blk00000003/blk00001023 ( + .C(clk), + .D(\blk00000003/sig0000146b ), + .R(\blk00000003/sig0000005f ), + .Q(xk_index_2[5]) + ); + FDR #( + .INIT ( 1'b0 )) + \blk00000003/blk00001022 ( + .C(clk), + .D(\blk00000003/sig0000146c ), + .R(\blk00000003/sig0000005f ), + .Q(xk_index_2[4]) + ); + FDR #( + .INIT ( 1'b0 )) + \blk00000003/blk00001021 ( + .C(clk), + .D(\blk00000003/sig0000146d ), + .R(\blk00000003/sig0000005f ), + .Q(xk_index_2[3]) + ); + FDR #( + .INIT ( 1'b0 )) + \blk00000003/blk00001020 ( + .C(clk), + .D(\blk00000003/sig0000146e ), + .R(\blk00000003/sig0000005f ), + .Q(xk_index_2[2]) + ); + FDR #( + .INIT ( 1'b0 )) + \blk00000003/blk0000101f ( + .C(clk), + .D(\blk00000003/sig0000146f ), + .R(\blk00000003/sig0000005f ), + .Q(xk_index_2[1]) + ); + FDR #( + .INIT ( 1'b0 )) + \blk00000003/blk0000101e ( + .C(clk), + .D(\blk00000003/sig00001470 ), + .R(\blk00000003/sig0000005f ), + .Q(xk_index_2[0]) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00001009 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig000013e1 ), + .Q(\blk00000003/sig0000136e ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00001008 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig000013df ), + .Q(\blk00000003/sig0000136c ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00001007 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig000013dc ), + .Q(\blk00000003/sig0000136a ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00001006 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig000013d9 ), + .Q(\blk00000003/sig00001368 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00001005 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig000013d6 ), + .Q(\blk00000003/sig00001366 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00001004 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig000013d3 ), + .Q(\blk00000003/sig00001364 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00001003 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig000013d0 ), + .Q(\blk00000003/sig00001362 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00001002 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig000013cd ), + .Q(\blk00000003/sig00001360 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00001001 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig000013ca ), + .Q(\blk00000003/sig0000135e ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00001000 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig000013c7 ), + .Q(\blk00000003/sig0000135c ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000fff ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig000013c4 ), + .Q(\blk00000003/sig0000135a ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000ffe ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig000013c1 ), + .Q(\blk00000003/sig00001358 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000ffd ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig000013be ), + .Q(\blk00000003/sig00001356 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000ffc ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig000013bb ), + .Q(\blk00000003/sig00001354 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000ffb ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig000013b8 ), + .Q(\blk00000003/sig00001352 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000ffa ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig000013b5 ), + .Q(\blk00000003/sig00001350 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000ff9 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig000013b2 ), + .Q(\blk00000003/sig0000134e ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000ff8 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig000013af ), + .Q(\blk00000003/sig0000134c ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000ff7 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig000013ac ), + .Q(\blk00000003/sig0000134a ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000ff6 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig000013a9 ), + .Q(\blk00000003/sig00001348 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000ff5 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig000013a6 ), + .Q(\blk00000003/sig00001346 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000ff4 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig000013a3 ), + .Q(\blk00000003/sig00001344 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000ff3 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig000013a0 ), + .Q(\blk00000003/sig00001342 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000ff2 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig00001425 ), + .Q(\blk00000003/sig0000143c ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000ff1 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig00001423 ), + .Q(\blk00000003/sig0000143b ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000ff0 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig00001420 ), + .Q(\blk00000003/sig0000143a ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000fef ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig0000141d ), + .Q(\blk00000003/sig00001439 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000fee ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig0000141a ), + .Q(\blk00000003/sig00001438 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000fed ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig00001417 ), + .Q(\blk00000003/sig00001437 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000fec ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig00001414 ), + .Q(\blk00000003/sig00001436 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000feb ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig00001411 ), + .Q(\blk00000003/sig00001435 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000fea ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig0000140e ), + .Q(\blk00000003/sig00001434 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000fe9 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig0000140b ), + .Q(\blk00000003/sig00001433 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000fe8 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig00001408 ), + .Q(\blk00000003/sig00001432 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000fe7 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig00001405 ), + .Q(\blk00000003/sig00001431 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000fe6 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig00001402 ), + .Q(\blk00000003/sig00001430 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000fe5 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig000013ff ), + .Q(\blk00000003/sig0000142f ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000fe4 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig000013fc ), + .Q(\blk00000003/sig0000142e ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000fe3 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig000013f9 ), + .Q(\blk00000003/sig0000142d ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000fe2 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig000013f6 ), + .Q(\blk00000003/sig0000142c ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000fe1 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig000013f3 ), + .Q(\blk00000003/sig0000142b ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000fe0 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig000013f0 ), + .Q(\blk00000003/sig0000142a ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000fdf ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig000013ed ), + .Q(\blk00000003/sig00001429 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000fde ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig000013ea ), + .Q(\blk00000003/sig00001428 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000fdd ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig000013e7 ), + .Q(\blk00000003/sig00001427 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000fdc ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig000013e4 ), + .Q(\blk00000003/sig00001426 ) + ); + MUXCY \blk00000003/blk00000fdb ( + .CI(\blk00000003/sig0000005f ), + .DI(\blk00000003/sig0000139d ), + .S(\blk00000003/sig00001424 ), + .O(\blk00000003/sig00001421 ) + ); + MUXCY \blk00000003/blk00000fda ( + .CI(\blk00000003/sig00001421 ), + .DI(\blk00000003/sig0000139c ), + .S(\blk00000003/sig00001422 ), + .O(\blk00000003/sig0000141e ) + ); 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+ .O(\blk00000003/sig0000140c ) + ); + MUXCY \blk00000003/blk00000fd3 ( + .CI(\blk00000003/sig0000140c ), + .DI(\blk00000003/sig00001395 ), + .S(\blk00000003/sig0000140d ), + .O(\blk00000003/sig00001409 ) + ); + MUXCY \blk00000003/blk00000fd2 ( + .CI(\blk00000003/sig00001409 ), + .DI(\blk00000003/sig00001394 ), + .S(\blk00000003/sig0000140a ), + .O(\blk00000003/sig00001406 ) + ); + MUXCY \blk00000003/blk00000fd1 ( + .CI(\blk00000003/sig00001406 ), + .DI(\blk00000003/sig00001393 ), + .S(\blk00000003/sig00001407 ), + .O(\blk00000003/sig00001403 ) + ); + MUXCY \blk00000003/blk00000fd0 ( + .CI(\blk00000003/sig00001403 ), + .DI(\blk00000003/sig00001392 ), + .S(\blk00000003/sig00001404 ), + .O(\blk00000003/sig00001400 ) + ); + MUXCY \blk00000003/blk00000fcf ( + .CI(\blk00000003/sig00001400 ), + .DI(\blk00000003/sig00001391 ), + .S(\blk00000003/sig00001401 ), + .O(\blk00000003/sig000013fd ) + ); + MUXCY \blk00000003/blk00000fce ( + .CI(\blk00000003/sig000013fd ), + .DI(\blk00000003/sig00001390 ), + .S(\blk00000003/sig000013fe ), + .O(\blk00000003/sig000013fa ) + ); + MUXCY \blk00000003/blk00000fcd ( + .CI(\blk00000003/sig000013fa ), + .DI(\blk00000003/sig0000138f ), + .S(\blk00000003/sig000013fb ), + .O(\blk00000003/sig000013f7 ) + ); + MUXCY \blk00000003/blk00000fcc ( + .CI(\blk00000003/sig000013f7 ), + .DI(\blk00000003/sig0000138e ), + .S(\blk00000003/sig000013f8 ), + .O(\blk00000003/sig000013f4 ) + ); + MUXCY \blk00000003/blk00000fcb ( + .CI(\blk00000003/sig000013f4 ), + .DI(\blk00000003/sig0000138d ), + .S(\blk00000003/sig000013f5 ), + .O(\blk00000003/sig000013f1 ) + ); + MUXCY \blk00000003/blk00000fca ( + .CI(\blk00000003/sig000013f1 ), + .DI(\blk00000003/sig0000138c ), + .S(\blk00000003/sig000013f2 ), + .O(\blk00000003/sig000013ee ) + ); + MUXCY \blk00000003/blk00000fc9 ( + .CI(\blk00000003/sig000013ee ), + .DI(\blk00000003/sig0000138b ), + .S(\blk00000003/sig000013ef ), + .O(\blk00000003/sig000013eb ) + ); + MUXCY \blk00000003/blk00000fc8 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FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000f6f ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig00001238 ), + .Q(\blk00000003/sig0000138b ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000f6e ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig0000123a ), + .Q(\blk00000003/sig0000138a ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000f6d ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig0000123c ), + .Q(\blk00000003/sig00001389 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000f6c ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig0000123e ), + .Q(\blk00000003/sig00001388 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000f6b ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig00001240 ), + .Q(\blk00000003/sig00001387 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000f6a ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig0000132a ), + .Q(\blk00000003/sig00001386 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000f69 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig00001329 ), + .Q(\blk00000003/sig00001385 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000f68 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig00001328 ), + .Q(\blk00000003/sig00001384 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000f67 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig00001327 ), + .Q(\blk00000003/sig00001383 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000f66 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig00001326 ), + .Q(\blk00000003/sig00001382 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000f65 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig00001325 ), + .Q(\blk00000003/sig00001381 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000f64 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig00001324 ), + .Q(\blk00000003/sig00001380 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000f63 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig00001323 ), + .Q(\blk00000003/sig0000137f ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000f62 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig00001322 ), + .Q(\blk00000003/sig0000137e ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000f61 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig00001321 ), + .Q(\blk00000003/sig0000137d ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000f60 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig00001320 ), + .Q(\blk00000003/sig0000137c ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000f5f ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig0000131f ), + .Q(\blk00000003/sig0000137b ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000f5e ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig0000131e ), + .Q(\blk00000003/sig0000137a ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000f5d ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig0000131d ), + .Q(\blk00000003/sig00001379 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000f5c ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig0000131c ), + .Q(\blk00000003/sig00001378 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000f5b ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig0000131b ), + .Q(\blk00000003/sig00001377 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000f5a ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig0000131a ), + .Q(\blk00000003/sig00001376 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000f59 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig00001319 ), + .Q(\blk00000003/sig00001375 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000f58 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig00001318 ), + .Q(\blk00000003/sig00001374 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000f57 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig00001317 ), + .Q(\blk00000003/sig00001373 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000f56 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig00001316 ), + .Q(\blk00000003/sig00001372 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000f55 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig00001315 ), + .Q(\blk00000003/sig00001371 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000f54 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig00001314 ), + .Q(\blk00000003/sig00001370 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000f53 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig0000136e ), + .Q(\blk00000003/sig0000136f ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000f52 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig0000136c ), + .Q(\blk00000003/sig0000136d ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000f51 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig0000136a ), + .Q(\blk00000003/sig0000136b ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000f50 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig00001368 ), + .Q(\blk00000003/sig00001369 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000f4f ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig00001366 ), + .Q(\blk00000003/sig00001367 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000f4e ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig00001364 ), + .Q(\blk00000003/sig00001365 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000f4d ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig00001362 ), + .Q(\blk00000003/sig00001363 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000f4c ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig00001360 ), + .Q(\blk00000003/sig00001361 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000f4b ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig0000135e ), + .Q(\blk00000003/sig0000135f ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000f4a ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig0000135c ), + .Q(\blk00000003/sig0000135d ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000f49 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig0000135a ), + .Q(\blk00000003/sig0000135b ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000f48 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig00001358 ), + .Q(\blk00000003/sig00001359 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000f47 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig00001356 ), + .Q(\blk00000003/sig00001357 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000f46 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig00001354 ), + .Q(\blk00000003/sig00001355 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000f45 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig00001352 ), + .Q(\blk00000003/sig00001353 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000f44 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig00001350 ), + .Q(\blk00000003/sig00001351 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000f43 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig0000134e ), + .Q(\blk00000003/sig0000134f ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000f42 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig0000134c ), + .Q(\blk00000003/sig0000134d ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000f41 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig0000134a ), + .Q(\blk00000003/sig0000134b ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000f40 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig00001348 ), + .Q(\blk00000003/sig00001349 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000f3f ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig00001346 ), + .Q(\blk00000003/sig00001347 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000f3e ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig00001344 ), + .Q(\blk00000003/sig00001345 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000f3d ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig00001342 ), + .Q(\blk00000003/sig00001343 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000f3c ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig00001270 ), + .Q(\blk00000003/sig00001341 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000f3b ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig00001272 ), + .Q(\blk00000003/sig00001340 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000f3a ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig00001274 ), + .Q(\blk00000003/sig0000133f ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000f39 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig00001276 ), + .Q(\blk00000003/sig0000133e ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000f38 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig00001278 ), + .Q(\blk00000003/sig0000133d ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000f37 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig0000127a ), + .Q(\blk00000003/sig0000133c ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000f36 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig0000127c ), + .Q(\blk00000003/sig0000133b ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000f35 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig0000127e ), + .Q(\blk00000003/sig0000133a ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000f34 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig00001280 ), + .Q(\blk00000003/sig00001339 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000f33 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig00001282 ), + .Q(\blk00000003/sig00001338 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000f32 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig00001284 ), + .Q(\blk00000003/sig00001337 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000f31 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig00001286 ), + .Q(\blk00000003/sig00001336 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000f30 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig00001288 ), + .Q(\blk00000003/sig00001335 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000f2f ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig0000128a ), + .Q(\blk00000003/sig00001334 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000f2e ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig0000128c ), + .Q(\blk00000003/sig00001333 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000f2d ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig0000128e ), + .Q(\blk00000003/sig00001332 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000f2c ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig00001290 ), + .Q(\blk00000003/sig00001331 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000f2b ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig00001292 ), + .Q(\blk00000003/sig00001330 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000f2a ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig00001294 ), + .Q(\blk00000003/sig0000132f ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000f29 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig00001296 ), + .Q(\blk00000003/sig0000132e ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000f28 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig00001298 ), + .Q(\blk00000003/sig0000132d ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000f27 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig0000129a ), + .Q(\blk00000003/sig0000132c ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000f26 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig0000129c ), + .Q(\blk00000003/sig0000132b ) + ); + FD #( + .INIT ( 1'b0 )) + \blk00000003/blk00000f25 ( + .C(clk), + .D(\blk00000003/sig000012cb ), + .Q(\blk00000003/sig0000132a ) + ); + FD #( + .INIT ( 1'b0 )) + \blk00000003/blk00000f24 ( + .C(clk), + .D(\blk00000003/sig000012cc ), + .Q(\blk00000003/sig00001329 ) + ); + FD #( + .INIT ( 1'b0 )) + \blk00000003/blk00000f23 ( + .C(clk), + .D(\blk00000003/sig000012cd ), + .Q(\blk00000003/sig00001328 ) + ); + FD #( + .INIT ( 1'b0 )) + \blk00000003/blk00000f22 ( + .C(clk), + .D(\blk00000003/sig000012ce ), + .Q(\blk00000003/sig00001327 ) + ); + FD #( + .INIT ( 1'b0 )) + \blk00000003/blk00000f21 ( + .C(clk), + .D(\blk00000003/sig000012cf ), + .Q(\blk00000003/sig00001326 ) + ); + FD #( + .INIT ( 1'b0 )) + \blk00000003/blk00000f20 ( + .C(clk), + .D(\blk00000003/sig000012d0 ), + .Q(\blk00000003/sig00001325 ) + ); + FD #( + .INIT ( 1'b0 )) + \blk00000003/blk00000f1f ( + .C(clk), + .D(\blk00000003/sig000012d1 ), + .Q(\blk00000003/sig00001324 ) + ); + FD #( + .INIT ( 1'b0 )) + \blk00000003/blk00000f1e ( + .C(clk), + .D(\blk00000003/sig000012d2 ), + .Q(\blk00000003/sig00001323 ) + ); + FD #( + .INIT ( 1'b0 )) + \blk00000003/blk00000f1d ( + .C(clk), + .D(\blk00000003/sig000012d3 ), + .Q(\blk00000003/sig00001322 ) + ); + FD #( + .INIT ( 1'b0 )) + \blk00000003/blk00000f1c ( + .C(clk), + .D(\blk00000003/sig000012d4 ), + .Q(\blk00000003/sig00001321 ) + ); + FD #( + .INIT ( 1'b0 )) + \blk00000003/blk00000f1b ( + .C(clk), + .D(\blk00000003/sig000012d5 ), + .Q(\blk00000003/sig00001320 ) + ); + FD #( + .INIT ( 1'b0 )) + \blk00000003/blk00000f1a ( + .C(clk), + .D(\blk00000003/sig000012d6 ), + .Q(\blk00000003/sig0000131f ) + ); + FD #( + .INIT ( 1'b0 )) + \blk00000003/blk00000f19 ( + .C(clk), + .D(\blk00000003/sig000012d7 ), + .Q(\blk00000003/sig0000131e ) + ); + FD #( + .INIT ( 1'b0 )) + \blk00000003/blk00000f18 ( + .C(clk), + .D(\blk00000003/sig000012d8 ), + .Q(\blk00000003/sig0000131d ) + ); + FD #( + .INIT ( 1'b0 )) + \blk00000003/blk00000f17 ( + .C(clk), + .D(\blk00000003/sig000012d9 ), + .Q(\blk00000003/sig0000131c ) + ); + FD #( + .INIT ( 1'b0 )) + \blk00000003/blk00000f16 ( + .C(clk), + .D(\blk00000003/sig000012da ), + .Q(\blk00000003/sig0000131b ) + ); + FD #( + .INIT ( 1'b0 )) + \blk00000003/blk00000f15 ( + .C(clk), + .D(\blk00000003/sig000012db ), + .Q(\blk00000003/sig0000131a ) + ); + FD #( + .INIT ( 1'b0 )) + \blk00000003/blk00000f14 ( + .C(clk), + .D(\blk00000003/sig000012dc ), + .Q(\blk00000003/sig00001319 ) + ); + FD #( + .INIT ( 1'b0 )) + \blk00000003/blk00000f13 ( + .C(clk), + .D(\blk00000003/sig000012dd ), + .Q(\blk00000003/sig00001318 ) + ); + FD #( + .INIT ( 1'b0 )) + \blk00000003/blk00000f12 ( + .C(clk), + .D(\blk00000003/sig000012de ), + .Q(\blk00000003/sig00001317 ) + ); + FD #( + .INIT ( 1'b0 )) + \blk00000003/blk00000f11 ( + .C(clk), + .D(\blk00000003/sig000012df ), + .Q(\blk00000003/sig00001316 ) + ); + FD #( + .INIT ( 1'b0 )) + \blk00000003/blk00000f10 ( + .C(clk), + .D(\blk00000003/sig000012e0 ), + .Q(\blk00000003/sig00001315 ) + ); + FD #( + .INIT ( 1'b0 )) + \blk00000003/blk00000f0f ( + .C(clk), + .D(\blk00000003/sig000012e1 ), + .Q(\blk00000003/sig00001314 ) + ); + FD #( + .INIT ( 1'b0 )) + \blk00000003/blk00000f0e ( + .C(clk), + .D(\blk00000003/sig000012e2 ), + .Q(\blk00000003/sig00001313 ) + ); + FD #( + .INIT ( 1'b0 )) + \blk00000003/blk00000f0d ( + .C(clk), + .D(\blk00000003/sig000012e3 ), + .Q(\blk00000003/sig00001312 ) + ); + FD #( + .INIT ( 1'b0 )) + \blk00000003/blk00000f0c ( + .C(clk), + .D(\blk00000003/sig000012e4 ), + .Q(\blk00000003/sig00001311 ) + ); + FD #( + .INIT ( 1'b0 )) + \blk00000003/blk00000f0b ( + .C(clk), + .D(\blk00000003/sig000012e5 ), + .Q(\blk00000003/sig00001310 ) + ); + FD #( + .INIT ( 1'b0 )) + \blk00000003/blk00000f0a ( + .C(clk), + .D(\blk00000003/sig000012e6 ), + .Q(\blk00000003/sig0000130f ) + ); + FD #( + .INIT ( 1'b0 )) + \blk00000003/blk00000f09 ( + .C(clk), + .D(\blk00000003/sig000012e7 ), + .Q(\blk00000003/sig0000130e ) + ); + FD #( + .INIT ( 1'b0 )) + \blk00000003/blk00000f08 ( + .C(clk), + .D(\blk00000003/sig000012e8 ), + .Q(\blk00000003/sig0000130d ) + ); + FD #( + .INIT ( 1'b0 )) + \blk00000003/blk00000f07 ( + .C(clk), + .D(\blk00000003/sig000012e9 ), + .Q(\blk00000003/sig0000130c ) + ); + FD #( + .INIT ( 1'b0 )) + \blk00000003/blk00000f06 ( + .C(clk), + .D(\blk00000003/sig000012ea ), + .Q(\blk00000003/sig0000130b ) + ); + FD #( + .INIT ( 1'b0 )) + \blk00000003/blk00000f05 ( + .C(clk), + .D(\blk00000003/sig000012eb ), + .Q(\blk00000003/sig0000130a ) + ); + FD #( + .INIT ( 1'b0 )) + \blk00000003/blk00000f04 ( + .C(clk), + .D(\blk00000003/sig000012ec ), + .Q(\blk00000003/sig00001309 ) + ); + FD #( + .INIT ( 1'b0 )) + \blk00000003/blk00000f03 ( + .C(clk), + .D(\blk00000003/sig000012ed ), + .Q(\blk00000003/sig00001308 ) + ); + FD #( + .INIT ( 1'b0 )) + \blk00000003/blk00000f02 ( + .C(clk), + .D(\blk00000003/sig000012ee ), + .Q(\blk00000003/sig00001307 ) + ); + FD #( + .INIT ( 1'b0 )) + \blk00000003/blk00000f01 ( + .C(clk), + .D(\blk00000003/sig000012ef ), + .Q(\blk00000003/sig00001306 ) + ); + FD #( + .INIT ( 1'b0 )) + \blk00000003/blk00000f00 ( + .C(clk), + .D(\blk00000003/sig000012f0 ), + .Q(\blk00000003/sig00001305 ) + ); + FD #( + .INIT ( 1'b0 )) + \blk00000003/blk00000eff ( + .C(clk), + .D(\blk00000003/sig000012f1 ), + .Q(\blk00000003/sig00001304 ) + ); + FD #( + .INIT ( 1'b0 )) + \blk00000003/blk00000efe ( + .C(clk), + .D(\blk00000003/sig000012f2 ), + .Q(\blk00000003/sig00001303 ) + ); + FD #( + .INIT ( 1'b0 )) + \blk00000003/blk00000efd ( + .C(clk), + .D(\blk00000003/sig000012f3 ), + .Q(\blk00000003/sig00001302 ) + ); + FD #( + .INIT ( 1'b0 )) + \blk00000003/blk00000efc ( + .C(clk), + .D(\blk00000003/sig000012f4 ), + .Q(\blk00000003/sig00001301 ) + ); + FD #( + .INIT ( 1'b0 )) + \blk00000003/blk00000efb ( + .C(clk), + .D(\blk00000003/sig000012f5 ), + .Q(\blk00000003/sig00001300 ) + ); + FD #( + .INIT ( 1'b0 )) + \blk00000003/blk00000efa ( + .C(clk), + .D(\blk00000003/sig000012f6 ), + .Q(\blk00000003/sig000012ff ) + ); + FD #( + .INIT ( 1'b0 )) + \blk00000003/blk00000ef9 ( + .C(clk), + .D(\blk00000003/sig000012f7 ), + .Q(\blk00000003/sig000012fe ) + ); + FD #( + .INIT ( 1'b0 )) + \blk00000003/blk00000ef8 ( + .C(clk), + .D(\blk00000003/sig000012f8 ), + .Q(\blk00000003/sig000012fd ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000ef7 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig00001182 ), + .Q(\blk00000003/sig00001184 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000ef6 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig000012fb ), + .Q(\blk00000003/sig000012fc ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000ef5 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig00001186 ), + .Q(\blk00000003/sig000012fa ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000ef4 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig00001183 ), + .Q(\blk00000003/sig000012f9 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000ef3 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig00001211 ), + .Q(\blk00000003/sig000012f8 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000ef2 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig0000120f ), + .Q(\blk00000003/sig000012f7 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000ef1 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig0000120c ), + .Q(\blk00000003/sig000012f6 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000ef0 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig00001209 ), + .Q(\blk00000003/sig000012f5 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000eef ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig00001206 ), + .Q(\blk00000003/sig000012f4 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000eee ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig00001203 ), + .Q(\blk00000003/sig000012f3 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000eed ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig00001200 ), + .Q(\blk00000003/sig000012f2 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000eec ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig000011fd ), + .Q(\blk00000003/sig000012f1 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000eeb ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig000011fa ), + .Q(\blk00000003/sig000012f0 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000eea ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig000011f7 ), + .Q(\blk00000003/sig000012ef ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000ee9 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig000011f4 ), + .Q(\blk00000003/sig000012ee ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000ee8 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig000011f1 ), + .Q(\blk00000003/sig000012ed ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000ee7 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig000011ee ), + .Q(\blk00000003/sig000012ec ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000ee6 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig000011eb ), + .Q(\blk00000003/sig000012eb ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000ee5 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig000011e8 ), + .Q(\blk00000003/sig000012ea ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000ee4 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig000011e5 ), + .Q(\blk00000003/sig000012e9 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000ee3 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig000011e2 ), + .Q(\blk00000003/sig000012e8 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000ee2 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig000011df ), + .Q(\blk00000003/sig000012e7 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000ee1 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig000011dc ), + .Q(\blk00000003/sig000012e6 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000ee0 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig000011d9 ), + .Q(\blk00000003/sig000012e5 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000edf ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig000011d6 ), + .Q(\blk00000003/sig000012e4 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000ede ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig000011d3 ), + .Q(\blk00000003/sig000012e3 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000edd ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig000011d0 ), + .Q(\blk00000003/sig000012e2 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000edc ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig000011cb ), + .Q(\blk00000003/sig000012e1 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000edb ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig000011c9 ), + .Q(\blk00000003/sig000012e0 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000eda ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig000011c6 ), + .Q(\blk00000003/sig000012df ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000ed9 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig000011c3 ), + .Q(\blk00000003/sig000012de ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000ed8 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig000011c0 ), + .Q(\blk00000003/sig000012dd ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000ed7 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig000011bd ), + .Q(\blk00000003/sig000012dc ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000ed6 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig000011ba ), + .Q(\blk00000003/sig000012db ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000ed5 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig000011b7 ), + .Q(\blk00000003/sig000012da ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000ed4 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig000011b4 ), + .Q(\blk00000003/sig000012d9 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000ed3 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig000011b1 ), + .Q(\blk00000003/sig000012d8 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000ed2 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig000011ae ), + .Q(\blk00000003/sig000012d7 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000ed1 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig000011ab ), + .Q(\blk00000003/sig000012d6 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000ed0 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig000011a8 ), + .Q(\blk00000003/sig000012d5 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000ecf ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig000011a5 ), + .Q(\blk00000003/sig000012d4 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000ece ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig000011a2 ), + .Q(\blk00000003/sig000012d3 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000ecd ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig0000119f ), + .Q(\blk00000003/sig000012d2 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000ecc ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig0000119c ), + .Q(\blk00000003/sig000012d1 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000ecb ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig00001199 ), + .Q(\blk00000003/sig000012d0 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000eca ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig00001196 ), + .Q(\blk00000003/sig000012cf ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000ec9 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig00001193 ), + .Q(\blk00000003/sig000012ce ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000ec8 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig00001190 ), + .Q(\blk00000003/sig000012cd ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000ec7 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig0000118d ), + .Q(\blk00000003/sig000012cc ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000ec6 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig0000118a ), + .Q(\blk00000003/sig000012cb ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000ec5 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig000012c9 ), + .R(\blk00000003/sig0000005f ), + .Q(\blk00000003/sig000012ca ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000ec4 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig000012c7 ), + .R(\blk00000003/sig0000005f ), + .Q(\blk00000003/sig000012c8 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000ec3 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig000012c5 ), + .R(\blk00000003/sig0000005f ), + .Q(\blk00000003/sig000012c6 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000ec2 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig000012c3 ), + .R(\blk00000003/sig0000005f ), + .Q(\blk00000003/sig000012c4 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000ec1 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig000012c1 ), + .R(\blk00000003/sig0000005f ), + .Q(\blk00000003/sig000012c2 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000ec0 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig000012bf ), + .R(\blk00000003/sig0000005f ), + .Q(\blk00000003/sig000012c0 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000ebf ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig000012bd ), + .R(\blk00000003/sig0000005f ), + .Q(\blk00000003/sig000012be ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000ebe ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig000012bb ), + .R(\blk00000003/sig0000005f ), + .Q(\blk00000003/sig000012bc ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000ebd ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig000012b9 ), + .R(\blk00000003/sig0000005f ), + .Q(\blk00000003/sig000012ba ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000ebc ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig000012b7 ), + .R(\blk00000003/sig0000005f ), + .Q(\blk00000003/sig000012b8 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000ebb ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig000012b5 ), + .R(\blk00000003/sig0000005f ), + .Q(\blk00000003/sig000012b6 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000eba ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig000012b3 ), + .R(\blk00000003/sig0000005f ), + .Q(\blk00000003/sig000012b4 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000eb9 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig000012b1 ), + .R(\blk00000003/sig0000005f ), + .Q(\blk00000003/sig000012b2 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000eb8 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig000012af ), + .R(\blk00000003/sig0000005f ), + .Q(\blk00000003/sig000012b0 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000eb7 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig000012ad ), + .R(\blk00000003/sig0000005f ), + .Q(\blk00000003/sig000012ae ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000eb6 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig000012ab ), + .R(\blk00000003/sig0000005f ), + .Q(\blk00000003/sig000012ac ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000eb5 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig000012a9 ), + .R(\blk00000003/sig0000005f ), + .Q(\blk00000003/sig000012aa ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000eb4 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig000012a7 ), + .R(\blk00000003/sig0000005f ), + .Q(\blk00000003/sig000012a8 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000eb3 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig000012a5 ), + .R(\blk00000003/sig0000005f ), + .Q(\blk00000003/sig000012a6 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000eb2 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig000012a3 ), + .R(\blk00000003/sig0000005f ), + .Q(\blk00000003/sig000012a4 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000eb1 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig000012a1 ), + .R(\blk00000003/sig0000005f ), + .Q(\blk00000003/sig000012a2 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000eb0 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig0000129f ), + .R(\blk00000003/sig0000005f ), + .Q(\blk00000003/sig000012a0 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000eaf ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig0000129d ), + .R(\blk00000003/sig0000005f ), + .Q(\blk00000003/sig0000129e ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000eae ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig0000129b ), + .R(\blk00000003/sig0000005f ), + .Q(\blk00000003/sig0000129c ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000ead ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig00001299 ), + .R(\blk00000003/sig0000005f ), + .Q(\blk00000003/sig0000129a ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000eac ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig00001297 ), + .R(\blk00000003/sig0000005f ), + .Q(\blk00000003/sig00001298 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000eab ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig00001295 ), + .R(\blk00000003/sig0000005f ), + .Q(\blk00000003/sig00001296 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000eaa ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig00001293 ), + .R(\blk00000003/sig0000005f ), + .Q(\blk00000003/sig00001294 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000ea9 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig00001291 ), + .R(\blk00000003/sig0000005f ), + .Q(\blk00000003/sig00001292 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000ea8 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig0000128f ), + .R(\blk00000003/sig0000005f ), + .Q(\blk00000003/sig00001290 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000ea7 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig0000128d ), + .R(\blk00000003/sig0000005f ), + .Q(\blk00000003/sig0000128e ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000ea6 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig0000128b ), + .R(\blk00000003/sig0000005f ), + .Q(\blk00000003/sig0000128c ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000ea5 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig00001289 ), + .R(\blk00000003/sig0000005f ), + .Q(\blk00000003/sig0000128a ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000ea4 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig00001287 ), + .R(\blk00000003/sig0000005f ), + .Q(\blk00000003/sig00001288 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000ea3 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig00001285 ), + .R(\blk00000003/sig0000005f ), + .Q(\blk00000003/sig00001286 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000ea2 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig00001283 ), + .R(\blk00000003/sig0000005f ), + .Q(\blk00000003/sig00001284 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000ea1 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig00001281 ), + .R(\blk00000003/sig0000005f ), + .Q(\blk00000003/sig00001282 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000ea0 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig0000127f ), + .R(\blk00000003/sig0000005f ), + .Q(\blk00000003/sig00001280 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000e9f ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig0000127d ), + .R(\blk00000003/sig0000005f ), + .Q(\blk00000003/sig0000127e ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000e9e ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig0000127b ), + .R(\blk00000003/sig0000005f ), + .Q(\blk00000003/sig0000127c ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000e9d ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig00001279 ), + .R(\blk00000003/sig0000005f ), + .Q(\blk00000003/sig0000127a ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000e9c ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig00001277 ), + .R(\blk00000003/sig0000005f ), + .Q(\blk00000003/sig00001278 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000e9b ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig00001275 ), + .R(\blk00000003/sig0000005f ), + .Q(\blk00000003/sig00001276 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000e9a ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig00001273 ), + .R(\blk00000003/sig0000005f ), + .Q(\blk00000003/sig00001274 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000e99 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig00001271 ), + .R(\blk00000003/sig0000005f ), + .Q(\blk00000003/sig00001272 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000e98 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig0000126f ), + .R(\blk00000003/sig0000005f ), + .Q(\blk00000003/sig00001270 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000e97 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig0000126d ), + .R(\blk00000003/sig0000005f ), + .Q(\blk00000003/sig0000126e ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000e96 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig0000126b ), + .R(\blk00000003/sig0000005f ), + .Q(\blk00000003/sig0000126c ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000e95 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig00001269 ), + .R(\blk00000003/sig0000005f ), + .Q(\blk00000003/sig0000126a ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000e94 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig00001267 ), + .R(\blk00000003/sig0000005f ), + .Q(\blk00000003/sig00001268 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000e93 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig00001265 ), + .R(\blk00000003/sig0000005f ), + .Q(\blk00000003/sig00001266 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000e92 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig00001263 ), + .R(\blk00000003/sig0000005f ), + .Q(\blk00000003/sig00001264 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000e91 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig00001261 ), + .R(\blk00000003/sig0000005f ), + .Q(\blk00000003/sig00001262 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000e90 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig0000125f ), + .R(\blk00000003/sig0000005f ), + .Q(\blk00000003/sig00001260 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000e8f ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig0000125d ), + .R(\blk00000003/sig0000005f ), + .Q(\blk00000003/sig0000125e ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000e8e ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig0000125b ), + .R(\blk00000003/sig0000005f ), + .Q(\blk00000003/sig0000125c ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000e8d ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig00001259 ), + .R(\blk00000003/sig0000005f ), + .Q(\blk00000003/sig0000125a ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000e8c ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig00001257 ), + .R(\blk00000003/sig0000005f ), + .Q(\blk00000003/sig00001258 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000e8b ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig00001255 ), + .R(\blk00000003/sig0000005f ), + .Q(\blk00000003/sig00001256 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000e8a ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig00001253 ), + .R(\blk00000003/sig0000005f ), + .Q(\blk00000003/sig00001254 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000e89 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig00001251 ), + .R(\blk00000003/sig0000005f ), + .Q(\blk00000003/sig00001252 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000e88 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig0000124f ), + .R(\blk00000003/sig0000005f ), + .Q(\blk00000003/sig00001250 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000e87 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig0000124d ), + .R(\blk00000003/sig0000005f ), + .Q(\blk00000003/sig0000124e ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000e86 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig0000124b ), + .R(\blk00000003/sig0000005f ), + .Q(\blk00000003/sig0000124c ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000e85 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig00001249 ), + .R(\blk00000003/sig0000005f ), + .Q(\blk00000003/sig0000124a ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000e84 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig00001247 ), + .R(\blk00000003/sig0000005f ), + .Q(\blk00000003/sig00001248 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000e83 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig00001245 ), + .R(\blk00000003/sig0000005f ), + .Q(\blk00000003/sig00001246 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000e82 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig00001243 ), + .R(\blk00000003/sig0000005f ), + .Q(\blk00000003/sig00001244 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000e81 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig00001241 ), + .R(\blk00000003/sig0000005f ), + .Q(\blk00000003/sig00001242 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000e80 ( + .C(clk), + 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), + .LI(\blk00000003/sig000010e1 ), + .O(\blk00000003/sig000010e2 ) + ); + XORCY \blk00000003/blk00000d2c ( + .CI(\blk00000003/sig000010dd ), + .LI(\blk00000003/sig000010de ), + .O(\blk00000003/sig000010df ) + ); + XORCY \blk00000003/blk00000d2b ( + .CI(\blk00000003/sig000010da ), + .LI(\blk00000003/sig000010db ), + .O(\blk00000003/sig000010dc ) + ); + XORCY \blk00000003/blk00000d2a ( + .CI(\blk00000003/sig000010d7 ), + .LI(\blk00000003/sig000010d8 ), + .O(\blk00000003/sig000010d9 ) + ); + XORCY \blk00000003/blk00000d29 ( + .CI(\blk00000003/sig000010d4 ), + .LI(\blk00000003/sig000010d5 ), + .O(\blk00000003/sig000010d6 ) + ); + XORCY \blk00000003/blk00000d28 ( + .CI(\blk00000003/sig000010d1 ), + .LI(\blk00000003/sig000010d2 ), + .O(\blk00000003/sig000010d3 ) + ); + XORCY \blk00000003/blk00000d27 ( + .CI(\blk00000003/sig000010ce ), + .LI(\blk00000003/sig000010cf ), + .O(\blk00000003/sig000010d0 ) + ); + XORCY \blk00000003/blk00000d26 ( + .CI(\blk00000003/sig000010cb ), + .LI(\blk00000003/sig000010cc ), + .O(\blk00000003/sig000010cd ) + ); + XORCY \blk00000003/blk00000d25 ( + .CI(\blk00000003/sig000010c8 ), + .LI(\blk00000003/sig000010c9 ), + .O(\blk00000003/sig000010ca ) + ); + XORCY \blk00000003/blk00000d24 ( + .CI(\blk00000003/sig000010c5 ), + .LI(\blk00000003/sig000010c6 ), + .O(\blk00000003/sig000010c7 ) + ); + XORCY \blk00000003/blk00000d23 ( + .CI(\blk00000003/sig000010c2 ), + .LI(\blk00000003/sig000010c3 ), + .O(\blk00000003/sig000010c4 ) + ); + XORCY \blk00000003/blk00000d22 ( + .CI(\blk00000003/sig000010bf ), + .LI(\blk00000003/sig000010c0 ), + .O(\blk00000003/sig000010c1 ) + ); + XORCY \blk00000003/blk00000d21 ( + .CI(\blk00000003/sig000010bc ), + .LI(\blk00000003/sig000010bd ), + .O(\blk00000003/sig000010be ) + ); + XORCY \blk00000003/blk00000d20 ( + .CI(\blk00000003/sig000010b9 ), + .LI(\blk00000003/sig000010ba ), + .O(\blk00000003/sig000010bb ) + ); + XORCY \blk00000003/blk00000d1f ( + .CI(\blk00000003/sig000010b6 ), + .LI(\blk00000003/sig000010b7 ), + .O(\blk00000003/sig000010b8 ) + ); + XORCY \blk00000003/blk00000d1e ( + .CI(\blk00000003/sig000010b3 ), + .LI(\blk00000003/sig000010b4 ), + .O(\blk00000003/sig000010b5 ) + ); + XORCY \blk00000003/blk00000d1d ( + .CI(\blk00000003/sig000010b0 ), + .LI(\blk00000003/sig000010b1 ), + .O(\blk00000003/sig000010b2 ) + ); + XORCY \blk00000003/blk00000d1c ( + .CI(\blk00000003/sig000010ad ), + .LI(\blk00000003/sig000010ae ), + .O(\blk00000003/sig000010af ) + ); + XORCY \blk00000003/blk00000d1b ( + .CI(\blk00000003/sig000010aa ), + .LI(\blk00000003/sig000010ab ), + .O(\blk00000003/sig000010ac ) + ); + XORCY \blk00000003/blk00000d1a ( + .CI(\blk00000003/sig000010a7 ), + .LI(\blk00000003/sig000010a8 ), + .O(\blk00000003/sig000010a9 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000cc1 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig000008d5 ), + .Q(\blk00000003/sig0000107c ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000cc0 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig0000107c ), + .Q(\blk00000003/sig00000fce ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000cbf ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig0000107a ), + .R(\blk00000003/sig0000005f ), + .Q(\blk00000003/sig0000107b ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000cbe ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig00001078 ), + .R(\blk00000003/sig0000005f ), + .Q(\blk00000003/sig00001079 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000cbd ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig00001076 ), + .R(\blk00000003/sig0000005f ), + .Q(\blk00000003/sig00001077 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000cbc ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig00001074 ), + .R(\blk00000003/sig0000005f ), + .Q(\blk00000003/sig00001075 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000cbb ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig00001072 ), + .R(\blk00000003/sig0000005f ), + .Q(\blk00000003/sig00001073 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000cba ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig00001070 ), + .R(\blk00000003/sig0000005f ), + .Q(\blk00000003/sig00001071 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000cb9 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig0000106e ), + .R(\blk00000003/sig0000005f ), + .Q(\blk00000003/sig0000106f ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000cb8 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig0000106c ), + .R(\blk00000003/sig0000005f ), + .Q(\blk00000003/sig0000106d ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000cb7 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig0000106a ), + .R(\blk00000003/sig0000005f ), + .Q(\blk00000003/sig0000106b ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000cb6 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig00001068 ), + .R(\blk00000003/sig0000005f ), + .Q(\blk00000003/sig00001069 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000cb5 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig00001066 ), + .R(\blk00000003/sig0000005f ), + .Q(\blk00000003/sig00001067 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000cb4 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig00001064 ), + .R(\blk00000003/sig0000005f ), + .Q(\blk00000003/sig00001065 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000cb3 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig00001062 ), + .R(\blk00000003/sig0000005f ), + .Q(\blk00000003/sig00001063 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000cb2 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig00001060 ), + .R(\blk00000003/sig0000005f ), + .Q(\blk00000003/sig00001061 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000cb1 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig0000105e ), + .R(\blk00000003/sig0000005f ), + .Q(\blk00000003/sig0000105f ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000cb0 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig0000105c ), + .R(\blk00000003/sig0000005f ), + .Q(\blk00000003/sig0000105d ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000caf ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig0000105a ), + .R(\blk00000003/sig0000005f ), + .Q(\blk00000003/sig0000105b ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000cae ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig00001058 ), + .R(\blk00000003/sig0000005f ), + .Q(\blk00000003/sig00001059 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000cad ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig00001056 ), + .R(\blk00000003/sig0000005f ), + .Q(\blk00000003/sig00001057 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000cac ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig00001054 ), + .R(\blk00000003/sig0000005f ), + .Q(\blk00000003/sig00001055 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000cab ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig00001052 ), + .R(\blk00000003/sig0000005f ), + .Q(\blk00000003/sig00001053 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000caa ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig00001050 ), + .R(\blk00000003/sig0000005f ), + .Q(\blk00000003/sig00001051 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000ca9 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig0000104e ), + .R(\blk00000003/sig0000005f ), + .Q(\blk00000003/sig0000104f ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000ca8 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig0000104c ), + .R(\blk00000003/sig0000005f ), + .Q(\blk00000003/sig0000104d ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000ca7 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig0000104a ), + .R(\blk00000003/sig0000005f ), + .Q(\blk00000003/sig0000104b ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000ca6 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig00001048 ), + .R(\blk00000003/sig0000005f ), + .Q(\blk00000003/sig00001049 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000ca5 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig00001046 ), + .R(\blk00000003/sig0000005f ), + .Q(\blk00000003/sig00001047 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000ca4 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig00001044 ), + .R(\blk00000003/sig0000005f ), + .Q(\blk00000003/sig00001045 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000ca3 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig00001042 ), + .R(\blk00000003/sig0000005f ), + .Q(\blk00000003/sig00001043 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000ca2 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig00001040 ), + .R(\blk00000003/sig0000005f ), + .Q(\blk00000003/sig00001041 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000ca1 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig0000103e ), + .R(\blk00000003/sig0000005f ), + .Q(\blk00000003/sig0000103f ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000ca0 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig0000103c ), + .R(\blk00000003/sig0000005f ), + .Q(\blk00000003/sig0000103d ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000c9f ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig0000103a ), + .R(\blk00000003/sig0000005f ), + .Q(\blk00000003/sig0000103b ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000c9e ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig00001038 ), + .R(\blk00000003/sig0000005f ), + .Q(\blk00000003/sig00001039 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000c9d ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig00001036 ), + .R(\blk00000003/sig0000005f ), + .Q(\blk00000003/sig00001037 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000c9c ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig00001034 ), + .R(\blk00000003/sig0000005f ), + .Q(\blk00000003/sig00001035 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000c9b ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig00001032 ), + .R(\blk00000003/sig0000005f ), + .Q(\blk00000003/sig00001033 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000c9a ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig00001030 ), + .R(\blk00000003/sig0000005f ), + .Q(\blk00000003/sig00001031 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000c99 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig0000102e ), + .R(\blk00000003/sig0000005f ), + .Q(\blk00000003/sig0000102f ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000c98 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig0000102c ), + .R(\blk00000003/sig0000005f ), + .Q(\blk00000003/sig0000102d ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000c97 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig0000102a ), + .R(\blk00000003/sig0000005f ), + .Q(\blk00000003/sig0000102b ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000c96 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig00001028 ), + .R(\blk00000003/sig0000005f ), + .Q(\blk00000003/sig00001029 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000c95 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig00001026 ), + .R(\blk00000003/sig0000005f ), + .Q(\blk00000003/sig00001027 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000c94 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig00001024 ), + .R(\blk00000003/sig0000005f ), + .Q(\blk00000003/sig00001025 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000c93 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig00001022 ), + .R(\blk00000003/sig0000005f ), + .Q(\blk00000003/sig00001023 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000c92 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig00001020 ), + .R(\blk00000003/sig0000005f ), + .Q(\blk00000003/sig00001021 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000c91 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig0000101e ), + .R(\blk00000003/sig0000005f ), + .Q(\blk00000003/sig0000101f ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000c90 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig0000101c ), + .R(\blk00000003/sig0000005f ), + .Q(\blk00000003/sig0000101d ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000c8f ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig0000101a ), + .R(\blk00000003/sig0000005f ), + .Q(\blk00000003/sig0000101b ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000c8e ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig00001018 ), + .R(\blk00000003/sig0000005f ), + .Q(\blk00000003/sig00001019 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000c8d ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig00001016 ), + .R(\blk00000003/sig0000005f ), + .Q(\blk00000003/sig00001017 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000c8c ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig00001014 ), + .R(\blk00000003/sig0000005f ), + .Q(\blk00000003/sig00001015 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000c8b ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig00001012 ), + .R(\blk00000003/sig0000005f ), + .Q(\blk00000003/sig00001013 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000c8a ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig00001010 ), + .R(\blk00000003/sig0000005f ), + .Q(\blk00000003/sig00001011 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000c89 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig0000100e ), + .R(\blk00000003/sig0000005f ), + .Q(\blk00000003/sig0000100f ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000c88 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig0000100c ), + .R(\blk00000003/sig0000005f ), + .Q(\blk00000003/sig0000100d ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000c87 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig0000100a ), + .R(\blk00000003/sig0000005f ), + .Q(\blk00000003/sig0000100b ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000c86 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig00001008 ), + .R(\blk00000003/sig0000005f ), + .Q(\blk00000003/sig00001009 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000c85 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig00001006 ), + .R(\blk00000003/sig0000005f ), + .Q(\blk00000003/sig00001007 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000c84 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig00001004 ), + .R(\blk00000003/sig0000005f ), + .Q(\blk00000003/sig00001005 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000c83 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig00001002 ), + .R(\blk00000003/sig0000005f ), + .Q(\blk00000003/sig00001003 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000c82 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig00001000 ), + .R(\blk00000003/sig0000005f ), + .Q(\blk00000003/sig00001001 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000c81 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig00000ffe ), + .R(\blk00000003/sig0000005f ), + .Q(\blk00000003/sig00000fff ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000c80 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig00000ffc ), + .R(\blk00000003/sig0000005f ), + .Q(\blk00000003/sig00000ffd ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000c7f ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig00000ffa ), + .R(\blk00000003/sig0000005f ), + .Q(\blk00000003/sig00000ffb ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000c7e ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig00000ff8 ), + .R(\blk00000003/sig0000005f ), + .Q(\blk00000003/sig00000ff9 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000c7d ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig00000ff6 ), + .R(\blk00000003/sig0000005f ), + .Q(\blk00000003/sig00000ff7 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000c7c ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig00000ff4 ), + .R(\blk00000003/sig0000005f ), + .Q(\blk00000003/sig00000ff5 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000c7b ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig00000ff2 ), + .R(\blk00000003/sig0000005f ), + .Q(\blk00000003/sig00000ff3 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000c7a ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig00000ff0 ), + .R(\blk00000003/sig0000005f ), + .Q(\blk00000003/sig00000ff1 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000c79 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig00000fee ), + .R(\blk00000003/sig0000005f ), + .Q(\blk00000003/sig00000fef ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000c78 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig00000fec ), + .R(\blk00000003/sig0000005f ), + .Q(\blk00000003/sig00000fed ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000c77 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig00000fea ), + .R(\blk00000003/sig0000005f ), + .Q(\blk00000003/sig00000feb ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000c76 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig00000fe8 ), + .R(\blk00000003/sig0000005f ), + .Q(\blk00000003/sig00000fe9 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000c75 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig00000fe6 ), + .R(\blk00000003/sig0000005f ), + .Q(\blk00000003/sig00000fe7 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000c74 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig00000fe4 ), + .R(\blk00000003/sig0000005f ), + .Q(\blk00000003/sig00000fe5 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000c73 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig00000fe2 ), + .R(\blk00000003/sig0000005f ), + .Q(\blk00000003/sig00000fe3 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000c72 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig00000fe0 ), + .R(\blk00000003/sig0000005f ), + .Q(\blk00000003/sig00000fe1 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000c71 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig00000fde ), + .R(\blk00000003/sig0000005f ), + .Q(\blk00000003/sig00000fdf ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000c70 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig00000fdc ), + .R(\blk00000003/sig0000005f ), + .Q(\blk00000003/sig00000fdd ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000c6f ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig00000fda ), + .R(\blk00000003/sig0000005f ), + .Q(\blk00000003/sig00000fdb ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000c6e ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig00000fd8 ), + .R(\blk00000003/sig0000005f ), + .Q(\blk00000003/sig00000fd9 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000c6d ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig00000fd6 ), + .R(\blk00000003/sig0000005f ), + .Q(\blk00000003/sig00000fd7 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000c6c ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig00000fd4 ), + .R(\blk00000003/sig0000005f ), + .Q(\blk00000003/sig00000fd5 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000c6b ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig00000fd2 ), + .R(\blk00000003/sig0000005f ), + .Q(\blk00000003/sig00000fd3 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000c6a ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig00000fd0 ), + .R(\blk00000003/sig0000005f ), + .Q(\blk00000003/sig00000fd1 ) + ); + FD #( + .INIT ( 1'b0 )) + \blk00000003/blk00000c65 ( + .C(clk), + .D(\blk00000003/sig00000fcc ), + .Q(\blk00000003/sig00000fcd ) + ); + FDR #( + .INIT ( 1'b0 )) + \blk00000003/blk00000c64 ( + .C(clk), + .D(\blk00000003/sig00000fcb ), + .R(\blk00000003/sig0000005f ), + .Q(\blk00000003/sig00000066 ) + ); + DSP48A #( + .A0REG ( 1 ), + .A1REG ( 1 ), + .B0REG ( 1 ), + .B1REG ( 1 ), + .CARRYINREG ( 0 ), + .CARRYINSEL ( "OPMODE5" ), + .CREG ( 1 ), + .DREG ( 0 ), + .MREG ( 1 ), + .OPMODEREG ( 0 ), + .PREG ( 1 ), + .RSTTYPE ( "SYNC" )) + \blk00000003/blk00000bfd ( + .CARRYIN(\blk00000003/sig0000005f ), + .CARRYOUT(\NLW_blk00000003/blk00000bfd_CARRYOUT_UNCONNECTED ), + .CLK(clk), + .RSTA(\blk00000003/sig0000005f ), + .RSTB(\blk00000003/sig0000005f ), + .RSTM(\blk00000003/sig0000005f ), + .RSTP(\blk00000003/sig0000005f ), + .RSTC(\blk00000003/sig0000005f ), + .RSTD(\blk00000003/sig0000005f ), + .RSTCARRYIN(\blk00000003/sig0000005f ), + .RSTOPMODE(\blk00000003/sig0000005f ), + .CEA(\blk00000003/sig00000065 ), + .CEB(\blk00000003/sig00000065 ), + .CEM(\blk00000003/sig00000065 ), + .CEP(\blk00000003/sig00000065 ), + .CEC(\blk00000003/sig00000065 ), + .CED(\blk00000003/sig0000005f ), + .CECARRYIN(\blk00000003/sig0000005f ), + .CEOPMODE(\blk00000003/sig0000005f ), + .A({\blk00000003/sig0000005f , \blk00000003/sig00000f20 , \blk00000003/sig00000f21 , \blk00000003/sig00000f22 , \blk00000003/sig00000f23 , +\blk00000003/sig00000f24 , \blk00000003/sig00000f25 , \blk00000003/sig00000f26 , \blk00000003/sig00000f27 , \blk00000003/sig00000f28 , +\blk00000003/sig00000f29 , \blk00000003/sig00000f2a , \blk00000003/sig00000f2b , \blk00000003/sig00000f2c , \blk00000003/sig00000f2d , +\blk00000003/sig00000f2e , \blk00000003/sig00000f2f , \blk00000003/sig00000f30 }), + .B({\blk00000003/sig00000f31 , \blk00000003/sig00000f31 , \blk00000003/sig00000f33 , \blk00000003/sig00000f34 , \blk00000003/sig00000f35 , +\blk00000003/sig00000f36 , \blk00000003/sig00000f37 , \blk00000003/sig00000f38 , \blk00000003/sig00000f39 , \blk00000003/sig00000f3a , +\blk00000003/sig00000f3b , \blk00000003/sig00000f3c , \blk00000003/sig00000f3d , \blk00000003/sig00000f3e , \blk00000003/sig00000f3f , +\blk00000003/sig00000f40 , \blk00000003/sig00000f41 , \blk00000003/sig0000005f }), + .D({\blk00000003/sig0000005f , \blk00000003/sig0000005f , \blk00000003/sig0000005f , \blk00000003/sig0000005f , \blk00000003/sig0000005f , +\blk00000003/sig0000005f , \blk00000003/sig0000005f , \blk00000003/sig0000005f , \blk00000003/sig0000005f , \blk00000003/sig0000005f , +\blk00000003/sig0000005f , \blk00000003/sig0000005f , \blk00000003/sig0000005f , \blk00000003/sig0000005f , \blk00000003/sig0000005f , +\blk00000003/sig0000005f , \blk00000003/sig0000005f , \blk00000003/sig0000005f }), + .C({\blk00000003/sig00000bc2 , \blk00000003/sig00000bc2 , \blk00000003/sig00000bc2 , \blk00000003/sig00000bc2 , \blk00000003/sig00000bc2 , +\blk00000003/sig00000bc2 , \blk00000003/sig00000bc2 , \blk00000003/sig00000bc2 , \blk00000003/sig00000bc2 , \blk00000003/sig00000bc2 , +\blk00000003/sig00000bc3 , \blk00000003/sig00000bc4 , \blk00000003/sig00000bc5 , \blk00000003/sig00000bc6 , \blk00000003/sig00000bc7 , +\blk00000003/sig00000bc8 , \blk00000003/sig00000bc9 , \blk00000003/sig00000bca , \blk00000003/sig00000bcb , \blk00000003/sig00000bcc , +\blk00000003/sig00000bcd , \blk00000003/sig00000bce , \blk00000003/sig00000bcf , \blk00000003/sig00000bd0 , \blk00000003/sig00000bd1 , +\blk00000003/sig00000bd2 , \blk00000003/sig00000bd3 , \blk00000003/sig00000bd4 , \blk00000003/sig00000bd5 , \blk00000003/sig00000bd6 , +\blk00000003/sig00000bd7 , \blk00000003/sig00000bd8 , \blk00000003/sig00000bd9 , \blk00000003/sig00000bda , \blk00000003/sig00000bdb , +\blk00000003/sig00000bdc , \blk00000003/sig00000bdd , \blk00000003/sig00000bde , \blk00000003/sig00000bdf , \blk00000003/sig00000be0 , +\blk00000003/sig00000be1 , \blk00000003/sig00000be2 , \blk00000003/sig00000be3 , \blk00000003/sig00000be4 , \blk00000003/sig00000be5 , +\blk00000003/sig00000be6 , \blk00000003/sig00000be7 , \blk00000003/sig00000be8 }), + .P({\blk00000003/sig00000eab , \blk00000003/sig00000eac , \blk00000003/sig00000ead , \blk00000003/sig00000eae , \blk00000003/sig00000eaf , +\blk00000003/sig00000eb0 , \blk00000003/sig00000eb1 , \blk00000003/sig00000eb2 , \blk00000003/sig00000eb3 , \blk00000003/sig00000eb4 , +\blk00000003/sig00000eb5 , \blk00000003/sig00000eb6 , \blk00000003/sig00000eb7 , \blk00000003/sig00000eb8 , \blk00000003/sig00000eb9 , +\blk00000003/sig00000eba , \blk00000003/sig00000ebb , \blk00000003/sig00000ebc , \blk00000003/sig00000ebd , \blk00000003/sig00000ebe , +\blk00000003/sig00000ebf , \blk00000003/sig00000ec0 , \blk00000003/sig00000ec1 , \blk00000003/sig00000ec2 , \blk00000003/sig00000ec3 , +\blk00000003/sig00000ec4 , \blk00000003/sig00000ec5 , \blk00000003/sig00000ec6 , \blk00000003/sig00000ec7 , \blk00000003/sig00000ec8 , +\blk00000003/sig00000ec9 , \blk00000003/sig00000f43 , \blk00000003/sig00000f44 , \blk00000003/sig00000f45 , \blk00000003/sig00000f46 , +\blk00000003/sig00000f47 , \blk00000003/sig00000f48 , \blk00000003/sig00000f49 , \blk00000003/sig00000f4a , \blk00000003/sig00000f4b , +\blk00000003/sig00000f4c , \blk00000003/sig00000f4d , \blk00000003/sig00000f4e , \blk00000003/sig00000f4f , \blk00000003/sig00000f50 , +\blk00000003/sig00000f51 , \blk00000003/sig00000f52 , \blk00000003/sig00000f53 }), + .OPMODE({\blk00000003/sig00000065 , \blk00000003/sig0000005f , \blk00000003/sig0000005f , \blk00000003/sig0000005f , \blk00000003/sig00000065 , +\blk00000003/sig00000065 , \blk00000003/sig0000005f , \blk00000003/sig00000065 }), + .PCIN({\blk00000003/sig0000005f , \blk00000003/sig0000005f , \blk00000003/sig0000005f , \blk00000003/sig0000005f , \blk00000003/sig0000005f , +\blk00000003/sig0000005f , \blk00000003/sig0000005f , \blk00000003/sig0000005f , \blk00000003/sig0000005f , \blk00000003/sig0000005f , +\blk00000003/sig0000005f , \blk00000003/sig0000005f , \blk00000003/sig0000005f , \blk00000003/sig0000005f , \blk00000003/sig0000005f , +\blk00000003/sig0000005f , \blk00000003/sig0000005f , \blk00000003/sig0000005f , \blk00000003/sig0000005f , \blk00000003/sig0000005f , +\blk00000003/sig0000005f , \blk00000003/sig0000005f , \blk00000003/sig0000005f , \blk00000003/sig0000005f , \blk00000003/sig0000005f , +\blk00000003/sig0000005f , \blk00000003/sig0000005f , \blk00000003/sig0000005f , \blk00000003/sig0000005f , \blk00000003/sig0000005f , +\blk00000003/sig0000005f , \blk00000003/sig0000005f , \blk00000003/sig0000005f , \blk00000003/sig0000005f , \blk00000003/sig0000005f , +\blk00000003/sig0000005f , \blk00000003/sig0000005f , \blk00000003/sig0000005f , \blk00000003/sig0000005f , \blk00000003/sig0000005f , +\blk00000003/sig0000005f , \blk00000003/sig0000005f , \blk00000003/sig0000005f , \blk00000003/sig0000005f , \blk00000003/sig0000005f , +\blk00000003/sig0000005f , \blk00000003/sig0000005f , \blk00000003/sig0000005f }), + .PCOUT({\blk00000003/sig00000eef , \blk00000003/sig00000ef0 , \blk00000003/sig00000ef1 , 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\blk00000003/blk00000bfc ( + .CARRYIN(\blk00000003/sig0000005f ), + .CARRYOUT(\NLW_blk00000003/blk00000bfc_CARRYOUT_UNCONNECTED ), + .CLK(clk), + .RSTA(\blk00000003/sig0000005f ), + .RSTB(\blk00000003/sig0000005f ), + .RSTM(\blk00000003/sig0000005f ), + .RSTP(\blk00000003/sig0000005f ), + .RSTC(\blk00000003/sig0000005f ), + .RSTD(\blk00000003/sig0000005f ), + .RSTCARRYIN(\blk00000003/sig0000005f ), + .RSTOPMODE(\blk00000003/sig0000005f ), + .CEA(\blk00000003/sig00000065 ), + .CEB(\blk00000003/sig00000065 ), + .CEM(\blk00000003/sig00000065 ), + .CEP(\blk00000003/sig00000065 ), + .CEC(\blk00000003/sig00000065 ), + .CED(\blk00000003/sig0000005f ), + .CECARRYIN(\blk00000003/sig0000005f ), + .CEOPMODE(\blk00000003/sig0000005f ), + .A({\blk00000003/sig00000e94 , \blk00000003/sig00000e94 , \blk00000003/sig00000e94 , \blk00000003/sig00000e94 , \blk00000003/sig00000e94 , +\blk00000003/sig00000e94 , \blk00000003/sig00000e94 , \blk00000003/sig00000e94 , \blk00000003/sig00000e94 , \blk00000003/sig00000e94 , +\blk00000003/sig00000e94 , \blk00000003/sig00000e94 , \blk00000003/sig00000e94 , \blk00000003/sig00000e94 , \blk00000003/sig00000e95 , +\blk00000003/sig00000e96 , \blk00000003/sig00000e97 , \blk00000003/sig00000e98 }), + .B({\blk00000003/sig00000e99 , \blk00000003/sig00000e9a , \blk00000003/sig00000e9b , \blk00000003/sig00000e9c , \blk00000003/sig00000e9d , +\blk00000003/sig00000e9e , \blk00000003/sig00000e9f , \blk00000003/sig00000ea0 , \blk00000003/sig00000ea1 , \blk00000003/sig00000ea2 , +\blk00000003/sig00000ea3 , \blk00000003/sig00000ea4 , \blk00000003/sig00000ea5 , \blk00000003/sig00000ea6 , \blk00000003/sig00000ea7 , +\blk00000003/sig00000ea8 , \blk00000003/sig00000ea9 , \blk00000003/sig00000eaa }), + .D({\blk00000003/sig0000005f , \blk00000003/sig0000005f , \blk00000003/sig0000005f , \blk00000003/sig0000005f , \blk00000003/sig0000005f , +\blk00000003/sig0000005f , \blk00000003/sig0000005f , \blk00000003/sig0000005f , \blk00000003/sig0000005f , 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\blk00000003/sig00000eb5 , \blk00000003/sig00000eb6 , \blk00000003/sig00000eb7 , +\blk00000003/sig00000eb8 , \blk00000003/sig00000eb9 , \blk00000003/sig00000eba , \blk00000003/sig00000ebb , \blk00000003/sig00000ebc , +\blk00000003/sig00000ebd , \blk00000003/sig00000ebe , \blk00000003/sig00000ebf , \blk00000003/sig00000ec0 , \blk00000003/sig00000ec1 , +\blk00000003/sig00000ec2 , \blk00000003/sig00000ec3 , \blk00000003/sig00000ec4 , \blk00000003/sig00000ec5 , \blk00000003/sig00000ec6 , +\blk00000003/sig00000ec7 , \blk00000003/sig00000ec8 , \blk00000003/sig00000ec9 }), + .P({\NLW_blk00000003/blk00000bfc_P<47>_UNCONNECTED , \NLW_blk00000003/blk00000bfc_P<46>_UNCONNECTED , +\NLW_blk00000003/blk00000bfc_P<45>_UNCONNECTED , \NLW_blk00000003/blk00000bfc_P<44>_UNCONNECTED , \NLW_blk00000003/blk00000bfc_P<43>_UNCONNECTED , +\NLW_blk00000003/blk00000bfc_P<42>_UNCONNECTED , \NLW_blk00000003/blk00000bfc_P<41>_UNCONNECTED , \NLW_blk00000003/blk00000bfc_P<40>_UNCONNECTED , +\NLW_blk00000003/blk00000bfc_P<39>_UNCONNECTED , \NLW_blk00000003/blk00000bfc_P<38>_UNCONNECTED , \NLW_blk00000003/blk00000bfc_P<37>_UNCONNECTED , +\NLW_blk00000003/blk00000bfc_P<36>_UNCONNECTED , \blk00000003/sig00000eca , \blk00000003/sig00000ecb , \blk00000003/sig00000ecc , +\blk00000003/sig00000ecd , \blk00000003/sig00000ece , \blk00000003/sig00000ecf , \blk00000003/sig00000ed0 , \blk00000003/sig00000ed1 , +\blk00000003/sig00000ed2 , \blk00000003/sig00000ed3 , \blk00000003/sig00000ed4 , \blk00000003/sig00000ed5 , \blk00000003/sig00000ed6 , +\blk00000003/sig00000ed7 , \blk00000003/sig00000ed8 , \blk00000003/sig00000ed9 , \blk00000003/sig00000eda , \blk00000003/sig00000edb , +\blk00000003/sig00000edc , \blk00000003/sig00000edd , \blk00000003/sig00000ede , \blk00000003/sig00000edf , \blk00000003/sig00000ee0 , +\blk00000003/sig00000ee1 , \blk00000003/sig00000ee2 , \blk00000003/sig00000ee3 , \blk00000003/sig00000ee4 , \blk00000003/sig00000ee5 , +\blk00000003/sig00000ee6 , \blk00000003/sig00000ee7 , \blk00000003/sig00000ee8 , \blk00000003/sig00000ee9 , \blk00000003/sig00000eea , +\blk00000003/sig00000eeb , \blk00000003/sig00000eec , \blk00000003/sig00000eed }), + .OPMODE({\blk00000003/sig00000065 , \blk00000003/sig0000005f , \blk00000003/sig0000005f , \blk00000003/sig0000005f , \blk00000003/sig00000065 , +\blk00000003/sig00000065 , \blk00000003/sig0000005f , \blk00000003/sig00000065 }), + .PCIN({\blk00000003/sig00000eef , \blk00000003/sig00000ef0 , \blk00000003/sig00000ef1 , \blk00000003/sig00000ef2 , \blk00000003/sig00000ef3 , +\blk00000003/sig00000ef4 , \blk00000003/sig00000ef5 , \blk00000003/sig00000ef6 , \blk00000003/sig00000ef7 , \blk00000003/sig00000ef8 , +\blk00000003/sig00000ef9 , \blk00000003/sig00000efa , \blk00000003/sig00000efb , \blk00000003/sig00000efc , \blk00000003/sig00000efd , +\blk00000003/sig00000efe , \blk00000003/sig00000eff , \blk00000003/sig00000f00 , \blk00000003/sig00000f01 , \blk00000003/sig00000f02 , +\blk00000003/sig00000f03 , \blk00000003/sig00000f04 , \blk00000003/sig00000f05 , \blk00000003/sig00000f06 , \blk00000003/sig00000f07 , +\blk00000003/sig00000f08 , \blk00000003/sig00000f09 , \blk00000003/sig00000f0a , \blk00000003/sig00000f0b , \blk00000003/sig00000f0c , +\blk00000003/sig00000f0d , \blk00000003/sig00000f0e , \blk00000003/sig00000f0f , \blk00000003/sig00000f10 , \blk00000003/sig00000f11 , +\blk00000003/sig00000f12 , \blk00000003/sig00000f13 , \blk00000003/sig00000f14 , \blk00000003/sig00000f15 , \blk00000003/sig00000f16 , +\blk00000003/sig00000f17 , \blk00000003/sig00000f18 , \blk00000003/sig00000f19 , \blk00000003/sig00000f1a , \blk00000003/sig00000f1b , +\blk00000003/sig00000f1c , \blk00000003/sig00000f1d , \blk00000003/sig00000f1e }), + .PCOUT({\NLW_blk00000003/blk00000bfc_PCOUT<47>_UNCONNECTED , \NLW_blk00000003/blk00000bfc_PCOUT<46>_UNCONNECTED , +\NLW_blk00000003/blk00000bfc_PCOUT<45>_UNCONNECTED , \NLW_blk00000003/blk00000bfc_PCOUT<44>_UNCONNECTED , +\NLW_blk00000003/blk00000bfc_PCOUT<43>_UNCONNECTED , \NLW_blk00000003/blk00000bfc_PCOUT<42>_UNCONNECTED , +\NLW_blk00000003/blk00000bfc_PCOUT<41>_UNCONNECTED , \NLW_blk00000003/blk00000bfc_PCOUT<40>_UNCONNECTED , +\NLW_blk00000003/blk00000bfc_PCOUT<39>_UNCONNECTED , \NLW_blk00000003/blk00000bfc_PCOUT<38>_UNCONNECTED , +\NLW_blk00000003/blk00000bfc_PCOUT<37>_UNCONNECTED , \NLW_blk00000003/blk00000bfc_PCOUT<36>_UNCONNECTED , +\NLW_blk00000003/blk00000bfc_PCOUT<35>_UNCONNECTED , \NLW_blk00000003/blk00000bfc_PCOUT<34>_UNCONNECTED , +\NLW_blk00000003/blk00000bfc_PCOUT<33>_UNCONNECTED , \NLW_blk00000003/blk00000bfc_PCOUT<32>_UNCONNECTED , +\NLW_blk00000003/blk00000bfc_PCOUT<31>_UNCONNECTED , \NLW_blk00000003/blk00000bfc_PCOUT<30>_UNCONNECTED , +\NLW_blk00000003/blk00000bfc_PCOUT<29>_UNCONNECTED , \NLW_blk00000003/blk00000bfc_PCOUT<28>_UNCONNECTED , +\NLW_blk00000003/blk00000bfc_PCOUT<27>_UNCONNECTED , \NLW_blk00000003/blk00000bfc_PCOUT<26>_UNCONNECTED , +\NLW_blk00000003/blk00000bfc_PCOUT<25>_UNCONNECTED , \NLW_blk00000003/blk00000bfc_PCOUT<24>_UNCONNECTED , +\NLW_blk00000003/blk00000bfc_PCOUT<23>_UNCONNECTED , \NLW_blk00000003/blk00000bfc_PCOUT<22>_UNCONNECTED , +\NLW_blk00000003/blk00000bfc_PCOUT<21>_UNCONNECTED , \NLW_blk00000003/blk00000bfc_PCOUT<20>_UNCONNECTED , +\NLW_blk00000003/blk00000bfc_PCOUT<19>_UNCONNECTED , \NLW_blk00000003/blk00000bfc_PCOUT<18>_UNCONNECTED , +\NLW_blk00000003/blk00000bfc_PCOUT<17>_UNCONNECTED , \NLW_blk00000003/blk00000bfc_PCOUT<16>_UNCONNECTED , +\NLW_blk00000003/blk00000bfc_PCOUT<15>_UNCONNECTED , \NLW_blk00000003/blk00000bfc_PCOUT<14>_UNCONNECTED , +\NLW_blk00000003/blk00000bfc_PCOUT<13>_UNCONNECTED , \NLW_blk00000003/blk00000bfc_PCOUT<12>_UNCONNECTED , +\NLW_blk00000003/blk00000bfc_PCOUT<11>_UNCONNECTED , \NLW_blk00000003/blk00000bfc_PCOUT<10>_UNCONNECTED , +\NLW_blk00000003/blk00000bfc_PCOUT<9>_UNCONNECTED , \NLW_blk00000003/blk00000bfc_PCOUT<8>_UNCONNECTED , +\NLW_blk00000003/blk00000bfc_PCOUT<7>_UNCONNECTED , \NLW_blk00000003/blk00000bfc_PCOUT<6>_UNCONNECTED , +\NLW_blk00000003/blk00000bfc_PCOUT<5>_UNCONNECTED , \NLW_blk00000003/blk00000bfc_PCOUT<4>_UNCONNECTED , +\NLW_blk00000003/blk00000bfc_PCOUT<3>_UNCONNECTED , \NLW_blk00000003/blk00000bfc_PCOUT<2>_UNCONNECTED , +\NLW_blk00000003/blk00000bfc_PCOUT<1>_UNCONNECTED , \NLW_blk00000003/blk00000bfc_PCOUT<0>_UNCONNECTED }), + .BCOUT({\NLW_blk00000003/blk00000bfc_BCOUT<17>_UNCONNECTED , \NLW_blk00000003/blk00000bfc_BCOUT<16>_UNCONNECTED , +\NLW_blk00000003/blk00000bfc_BCOUT<15>_UNCONNECTED , \NLW_blk00000003/blk00000bfc_BCOUT<14>_UNCONNECTED , +\NLW_blk00000003/blk00000bfc_BCOUT<13>_UNCONNECTED , \NLW_blk00000003/blk00000bfc_BCOUT<12>_UNCONNECTED , +\NLW_blk00000003/blk00000bfc_BCOUT<11>_UNCONNECTED , \NLW_blk00000003/blk00000bfc_BCOUT<10>_UNCONNECTED , +\NLW_blk00000003/blk00000bfc_BCOUT<9>_UNCONNECTED , \NLW_blk00000003/blk00000bfc_BCOUT<8>_UNCONNECTED , +\NLW_blk00000003/blk00000bfc_BCOUT<7>_UNCONNECTED , \NLW_blk00000003/blk00000bfc_BCOUT<6>_UNCONNECTED , +\NLW_blk00000003/blk00000bfc_BCOUT<5>_UNCONNECTED , \NLW_blk00000003/blk00000bfc_BCOUT<4>_UNCONNECTED , +\NLW_blk00000003/blk00000bfc_BCOUT<3>_UNCONNECTED , \NLW_blk00000003/blk00000bfc_BCOUT<2>_UNCONNECTED , +\NLW_blk00000003/blk00000bfc_BCOUT<1>_UNCONNECTED , \NLW_blk00000003/blk00000bfc_BCOUT<0>_UNCONNECTED }) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000bfb ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig00000a72 ), + .Q(\blk00000003/sig00000c95 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000bfa ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig00000a71 ), + .Q(\blk00000003/sig00000c94 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000bf9 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig00000a70 ), + .Q(\blk00000003/sig00000c93 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000bf8 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig00000a6f ), + .Q(\blk00000003/sig00000c92 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000bf7 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig00000a6e ), + .Q(\blk00000003/sig00000c91 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000bf6 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig00000a6d ), + .Q(\blk00000003/sig00000c90 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000bf5 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig00000a6c ), + .Q(\blk00000003/sig00000c8f ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000bf4 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig00000a6b ), + .Q(\blk00000003/sig00000c8e ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000bf3 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig00000a6a ), + .Q(\blk00000003/sig00000c8d ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000bf2 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig00000a69 ), + .Q(\blk00000003/sig00000c8c ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000bf1 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig00000a68 ), + .Q(\blk00000003/sig00000c8b ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000bf0 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig00000a67 ), + .Q(\blk00000003/sig00000c8a ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000bef ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig00000a66 ), + .Q(\blk00000003/sig00000c89 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000bee ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig00000a65 ), + .Q(\blk00000003/sig00000c88 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000bed ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig00000a64 ), + .Q(\blk00000003/sig00000c87 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000bec ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig00000a63 ), + .Q(\blk00000003/sig00000c86 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000beb ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig00000a62 ), + .Q(\blk00000003/sig00000c85 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000bea ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig00000a61 ), + .Q(\blk00000003/sig00000d68 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000be9 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig00000a60 ), + .Q(\blk00000003/sig00000d63 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000be8 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig00000a5f ), + .Q(\blk00000003/sig00000d5e ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000be7 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig00000a5e ), + .Q(\blk00000003/sig00000d56 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000be6 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig000009de ), + .Q(\blk00000003/sig00000dbb ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000be5 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig000009e0 ), + .Q(\blk00000003/sig00000db7 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000be4 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig000009e2 ), + .Q(\blk00000003/sig00000db2 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000be3 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig000009e4 ), + .Q(\blk00000003/sig00000dad ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000be2 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig000009e6 ), + .Q(\blk00000003/sig00000da8 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000be1 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig000009e8 ), + .Q(\blk00000003/sig00000da3 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000be0 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig000009ea ), + .Q(\blk00000003/sig00000d9e ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000bdf ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig000009ec ), + .Q(\blk00000003/sig00000d99 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000bde ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig000009ee ), + .Q(\blk00000003/sig00000d94 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000bdd ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig000009f0 ), + .Q(\blk00000003/sig00000d8f ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000bdc ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig000009f2 ), + .Q(\blk00000003/sig00000d8a ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000bdb ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig000009f4 ), + .Q(\blk00000003/sig00000d85 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000bda ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig000009f6 ), + .Q(\blk00000003/sig00000d80 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000bd9 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig000009f8 ), + .Q(\blk00000003/sig00000d7b ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000bd8 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig000009fa ), + .Q(\blk00000003/sig00000d76 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000bd7 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig000009fc ), + .Q(\blk00000003/sig00000d71 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000bd6 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig000009fe ), + .Q(\blk00000003/sig00000d6c ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000bd5 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig00000a00 ), + .Q(\blk00000003/sig00000d67 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000bd4 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig00000a02 ), + .Q(\blk00000003/sig00000d62 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000bd3 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig00000a04 ), + .Q(\blk00000003/sig00000d5d ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000bd2 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig00000a06 ), + .Q(\blk00000003/sig00000d55 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000bd1 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig00000e93 ), + .Q(\blk00000003/sig00000cb7 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000bd0 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig00000e92 ), + .Q(\blk00000003/sig00000cb6 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000bcf ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig00000e91 ), + .Q(\blk00000003/sig00000cb5 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000bce ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig00000e90 ), + .Q(\blk00000003/sig00000cb4 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000bcd ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig00000e8f ), + .Q(\blk00000003/sig00000cb3 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000bcc ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig00000e8e ), + .Q(\blk00000003/sig00000cb2 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000bcb ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig00000e8d ), + .Q(\blk00000003/sig00000cb1 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000bca ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig00000e8c ), + .Q(\blk00000003/sig00000cb0 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000bc9 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig00000e8b ), + .Q(\blk00000003/sig00000caf ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000bc8 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig00000e8a ), + .Q(\blk00000003/sig00000cae ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000bc7 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig00000e89 ), + .Q(\blk00000003/sig00000cad ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000bc6 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig00000e88 ), + .Q(\blk00000003/sig00000cac ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000bc5 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig00000e87 ), + .Q(\blk00000003/sig00000cab ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000bc4 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig00000e86 ), + .Q(\blk00000003/sig00000caa ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000bc3 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig00000e85 ), + .Q(\blk00000003/sig00000ca9 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000bc2 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig00000e84 ), + .Q(\blk00000003/sig00000ca8 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000bc1 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig00000e82 ), + .Q(\blk00000003/sig00000ca6 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000bc0 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig00000e80 ), + .Q(\blk00000003/sig00000ca5 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000bbf ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig00000e7e ), + .Q(\blk00000003/sig00000ca4 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000bbe ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig00000e7c ), + .Q(\blk00000003/sig00000ca3 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000bbd ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig00000e7a ), + .Q(\blk00000003/sig00000ca2 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000bbc ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig00000e78 ), + .Q(\blk00000003/sig00000ca1 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000bbb ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig00000e76 ), + .Q(\blk00000003/sig00000ca0 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000bba ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig00000e74 ), + .Q(\blk00000003/sig00000c9f ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000bb9 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig00000e72 ), + .Q(\blk00000003/sig00000c9e ) + ); + FDE #( + .INIT ( 1'b0 )) + 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, \blk00000003/sig00000bce , \blk00000003/sig00000bcf , +\blk00000003/sig00000bd0 , \blk00000003/sig00000bd1 , \blk00000003/sig00000bd2 , \blk00000003/sig00000bd3 , \blk00000003/sig00000bd4 , +\blk00000003/sig00000bd5 , \blk00000003/sig00000bd6 , \blk00000003/sig00000bd7 }), + .OPMODE({\blk00000003/sig0000005f , \blk00000003/sig0000005f , \blk00000003/sig0000005f , \blk00000003/sig0000005f , \blk00000003/sig00000065 , +\blk00000003/sig00000065 , \blk00000003/sig0000005f , \blk00000003/sig00000065 }), + .PCIN({\blk00000003/sig00000ce8 , \blk00000003/sig00000ce9 , \blk00000003/sig00000cea , \blk00000003/sig00000ceb , \blk00000003/sig00000cec , +\blk00000003/sig00000ced , \blk00000003/sig00000cee , \blk00000003/sig00000cef , \blk00000003/sig00000cf0 , \blk00000003/sig00000cf1 , +\blk00000003/sig00000cf2 , \blk00000003/sig00000cf3 , \blk00000003/sig00000cf4 , \blk00000003/sig00000cf5 , \blk00000003/sig00000cf6 , +\blk00000003/sig00000cf7 , \blk00000003/sig00000cf8 , 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+\NLW_blk00000003/blk00000ae5_PCOUT<27>_UNCONNECTED , \NLW_blk00000003/blk00000ae5_PCOUT<26>_UNCONNECTED , +\NLW_blk00000003/blk00000ae5_PCOUT<25>_UNCONNECTED , \NLW_blk00000003/blk00000ae5_PCOUT<24>_UNCONNECTED , +\NLW_blk00000003/blk00000ae5_PCOUT<23>_UNCONNECTED , \NLW_blk00000003/blk00000ae5_PCOUT<22>_UNCONNECTED , +\NLW_blk00000003/blk00000ae5_PCOUT<21>_UNCONNECTED , \NLW_blk00000003/blk00000ae5_PCOUT<20>_UNCONNECTED , +\NLW_blk00000003/blk00000ae5_PCOUT<19>_UNCONNECTED , \NLW_blk00000003/blk00000ae5_PCOUT<18>_UNCONNECTED , +\NLW_blk00000003/blk00000ae5_PCOUT<17>_UNCONNECTED , \NLW_blk00000003/blk00000ae5_PCOUT<16>_UNCONNECTED , +\NLW_blk00000003/blk00000ae5_PCOUT<15>_UNCONNECTED , \NLW_blk00000003/blk00000ae5_PCOUT<14>_UNCONNECTED , +\NLW_blk00000003/blk00000ae5_PCOUT<13>_UNCONNECTED , \NLW_blk00000003/blk00000ae5_PCOUT<12>_UNCONNECTED , +\NLW_blk00000003/blk00000ae5_PCOUT<11>_UNCONNECTED , \NLW_blk00000003/blk00000ae5_PCOUT<10>_UNCONNECTED , +\NLW_blk00000003/blk00000ae5_PCOUT<9>_UNCONNECTED , \NLW_blk00000003/blk00000ae5_PCOUT<8>_UNCONNECTED , +\NLW_blk00000003/blk00000ae5_PCOUT<7>_UNCONNECTED , \NLW_blk00000003/blk00000ae5_PCOUT<6>_UNCONNECTED , +\NLW_blk00000003/blk00000ae5_PCOUT<5>_UNCONNECTED , \NLW_blk00000003/blk00000ae5_PCOUT<4>_UNCONNECTED , +\NLW_blk00000003/blk00000ae5_PCOUT<3>_UNCONNECTED , \NLW_blk00000003/blk00000ae5_PCOUT<2>_UNCONNECTED , +\NLW_blk00000003/blk00000ae5_PCOUT<1>_UNCONNECTED , \NLW_blk00000003/blk00000ae5_PCOUT<0>_UNCONNECTED }), + .BCOUT({\NLW_blk00000003/blk00000ae5_BCOUT<17>_UNCONNECTED , \NLW_blk00000003/blk00000ae5_BCOUT<16>_UNCONNECTED , +\NLW_blk00000003/blk00000ae5_BCOUT<15>_UNCONNECTED , \NLW_blk00000003/blk00000ae5_BCOUT<14>_UNCONNECTED , +\NLW_blk00000003/blk00000ae5_BCOUT<13>_UNCONNECTED , \NLW_blk00000003/blk00000ae5_BCOUT<12>_UNCONNECTED , +\NLW_blk00000003/blk00000ae5_BCOUT<11>_UNCONNECTED , \NLW_blk00000003/blk00000ae5_BCOUT<10>_UNCONNECTED , +\NLW_blk00000003/blk00000ae5_BCOUT<9>_UNCONNECTED , \NLW_blk00000003/blk00000ae5_BCOUT<8>_UNCONNECTED , +\NLW_blk00000003/blk00000ae5_BCOUT<7>_UNCONNECTED , \NLW_blk00000003/blk00000ae5_BCOUT<6>_UNCONNECTED , +\NLW_blk00000003/blk00000ae5_BCOUT<5>_UNCONNECTED , \NLW_blk00000003/blk00000ae5_BCOUT<4>_UNCONNECTED , +\NLW_blk00000003/blk00000ae5_BCOUT<3>_UNCONNECTED , \NLW_blk00000003/blk00000ae5_BCOUT<2>_UNCONNECTED , +\NLW_blk00000003/blk00000ae5_BCOUT<1>_UNCONNECTED , \NLW_blk00000003/blk00000ae5_BCOUT<0>_UNCONNECTED }) + ); + DSP48A #( + .A0REG ( 1 ), + .A1REG ( 1 ), + .B0REG ( 1 ), + .B1REG ( 1 ), + .CARRYINREG ( 0 ), + .CARRYINSEL ( "OPMODE5" ), + .CREG ( 0 ), + .DREG ( 1 ), + .MREG ( 1 ), + .OPMODEREG ( 0 ), + .PREG ( 1 ), + .RSTTYPE ( "SYNC" )) + \blk00000003/blk00000ae4 ( + .CARRYIN(\blk00000003/sig0000005f ), + .CARRYOUT(\NLW_blk00000003/blk00000ae4_CARRYOUT_UNCONNECTED ), + .CLK(clk), + .RSTA(\blk00000003/sig0000005f ), + .RSTB(\blk00000003/sig0000005f ), + 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\blk00000003/sig00000c95 }), + .B({\blk00000003/sig00000c96 , \blk00000003/sig00000c96 , \blk00000003/sig00000c98 , \blk00000003/sig00000c99 , \blk00000003/sig00000c9a , +\blk00000003/sig00000c9b , \blk00000003/sig00000c9c , \blk00000003/sig00000c9d , \blk00000003/sig00000c9e , \blk00000003/sig00000c9f , +\blk00000003/sig00000ca0 , \blk00000003/sig00000ca1 , \blk00000003/sig00000ca2 , \blk00000003/sig00000ca3 , \blk00000003/sig00000ca4 , +\blk00000003/sig00000ca5 , \blk00000003/sig00000ca6 , \blk00000003/sig0000005f }), + .D({\blk00000003/sig00000ca8 , \blk00000003/sig00000ca8 , \blk00000003/sig00000ca9 , \blk00000003/sig00000caa , \blk00000003/sig00000cab , +\blk00000003/sig00000cac , \blk00000003/sig00000cad , \blk00000003/sig00000cae , \blk00000003/sig00000caf , \blk00000003/sig00000cb0 , +\blk00000003/sig00000cb1 , \blk00000003/sig00000cb2 , \blk00000003/sig00000cb3 , \blk00000003/sig00000cb4 , \blk00000003/sig00000cb5 , +\blk00000003/sig00000cb6 , \blk00000003/sig00000cb7 , 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, \blk00000003/sig0000005f , \blk00000003/sig0000005f , +\blk00000003/sig0000005f , \blk00000003/sig0000005f , \blk00000003/sig0000005f , \blk00000003/sig0000005f , \blk00000003/sig0000005f , +\blk00000003/sig0000005f , \blk00000003/sig0000005f , \blk00000003/sig0000005f , \blk00000003/sig0000005f , \blk00000003/sig0000005f , +\blk00000003/sig0000005f , \blk00000003/sig0000005f , \blk00000003/sig0000005f , \blk00000003/sig0000005f , \blk00000003/sig0000005f , +\blk00000003/sig0000005f , \blk00000003/sig0000005f , \blk00000003/sig0000005f , \blk00000003/sig0000005f , \blk00000003/sig0000005f , +\blk00000003/sig0000005f , \blk00000003/sig0000005f , \blk00000003/sig0000005f , \blk00000003/sig0000005f , \blk00000003/sig0000005f , +\blk00000003/sig0000005f , \blk00000003/sig0000005f , \blk00000003/sig0000005f , \blk00000003/sig0000005f , \blk00000003/sig0000005f , +\blk00000003/sig0000005f , \blk00000003/sig0000005f , \blk00000003/sig0000005f , \blk00000003/sig0000005f , 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\blk00000003/sig00000d03 , \blk00000003/sig00000d04 , \blk00000003/sig00000d05 , +\blk00000003/sig00000d06 , \blk00000003/sig00000d07 , \blk00000003/sig00000d08 , \blk00000003/sig00000d09 , \blk00000003/sig00000d0a , +\blk00000003/sig00000d0b , \blk00000003/sig00000d0c , \blk00000003/sig00000d0d , \blk00000003/sig00000d0e , \blk00000003/sig00000d0f , +\blk00000003/sig00000d10 , \blk00000003/sig00000d11 , \blk00000003/sig00000d12 , \blk00000003/sig00000d13 , \blk00000003/sig00000d14 , +\blk00000003/sig00000d15 , \blk00000003/sig00000d16 , \blk00000003/sig00000d17 }), + .BCOUT({\blk00000003/sig00000d18 , \blk00000003/sig00000d19 , \blk00000003/sig00000d1a , \blk00000003/sig00000d1b , \blk00000003/sig00000d1c , +\blk00000003/sig00000d1d , \blk00000003/sig00000d1e , \blk00000003/sig00000d1f , \blk00000003/sig00000d20 , \blk00000003/sig00000d21 , +\blk00000003/sig00000d22 , \blk00000003/sig00000d23 , \blk00000003/sig00000d24 , \blk00000003/sig00000d25 , \blk00000003/sig00000d26 , +\blk00000003/sig00000d27 , \blk00000003/sig00000d28 , \blk00000003/sig00000d29 }) + ); + DSP48A #( + .A0REG ( 1 ), + .A1REG ( 1 ), + .B0REG ( 1 ), + .B1REG ( 1 ), + .CARRYINREG ( 0 ), + .CARRYINSEL ( "OPMODE5" ), + .CREG ( 1 ), + .DREG ( 0 ), + .MREG ( 1 ), + .OPMODEREG ( 0 ), + .PREG ( 1 ), + .RSTTYPE ( "SYNC" )) + \blk00000003/blk00000ae3 ( + .CARRYIN(\blk00000003/sig0000005f ), + .CARRYOUT(\NLW_blk00000003/blk00000ae3_CARRYOUT_UNCONNECTED ), + .CLK(clk), + .RSTA(\blk00000003/sig0000005f ), + .RSTB(\blk00000003/sig0000005f ), + .RSTM(\blk00000003/sig0000005f ), + .RSTP(\blk00000003/sig0000005f ), + .RSTC(\blk00000003/sig0000005f ), + .RSTD(\blk00000003/sig0000005f ), + .RSTCARRYIN(\blk00000003/sig0000005f ), + .RSTOPMODE(\blk00000003/sig0000005f ), + .CEA(\blk00000003/sig00000065 ), + .CEB(\blk00000003/sig00000065 ), + .CEM(\blk00000003/sig00000065 ), + .CEP(\blk00000003/sig00000065 ), + .CEC(\blk00000003/sig00000065 ), + .CED(\blk00000003/sig0000005f ), + .CECARRYIN(\blk00000003/sig0000005f ), + .CEOPMODE(\blk00000003/sig0000005f ), + .A({\blk00000003/sig00000c5b , \blk00000003/sig00000c5b , \blk00000003/sig00000c5b , \blk00000003/sig00000c5b , \blk00000003/sig00000c5b , +\blk00000003/sig00000c5b , \blk00000003/sig00000c5b , \blk00000003/sig00000c5b , \blk00000003/sig00000c5b , \blk00000003/sig00000c5b , +\blk00000003/sig00000c5b , \blk00000003/sig00000c5b , \blk00000003/sig00000c5b , \blk00000003/sig00000c5b , \blk00000003/sig00000c5c , +\blk00000003/sig00000c5d , \blk00000003/sig00000c5e , \blk00000003/sig00000c5f }), + .B({\blk00000003/sig00000c49 , \blk00000003/sig00000c4a , \blk00000003/sig00000c4b , \blk00000003/sig00000c4c , \blk00000003/sig00000c4d , +\blk00000003/sig00000c4e , \blk00000003/sig00000c4f , \blk00000003/sig00000c50 , \blk00000003/sig00000c51 , \blk00000003/sig00000c52 , +\blk00000003/sig00000c53 , \blk00000003/sig00000c54 , \blk00000003/sig00000c55 , \blk00000003/sig00000c56 , \blk00000003/sig00000c57 , +\blk00000003/sig00000c58 , \blk00000003/sig00000c59 , \blk00000003/sig00000c5a }), + .D({\blk00000003/sig0000005f , \blk00000003/sig0000005f , \blk00000003/sig0000005f , \blk00000003/sig0000005f , \blk00000003/sig0000005f , +\blk00000003/sig0000005f , \blk00000003/sig0000005f , \blk00000003/sig0000005f , \blk00000003/sig0000005f , \blk00000003/sig0000005f , +\blk00000003/sig0000005f , \blk00000003/sig0000005f , \blk00000003/sig0000005f , \blk00000003/sig0000005f , \blk00000003/sig0000005f , +\blk00000003/sig0000005f , \blk00000003/sig0000005f , \blk00000003/sig0000005f }), + .C({\blk00000003/sig00000be9 , \blk00000003/sig00000be9 , \blk00000003/sig00000be9 , \blk00000003/sig00000be9 , \blk00000003/sig00000be9 , +\blk00000003/sig00000be9 , \blk00000003/sig00000be9 , \blk00000003/sig00000be9 , \blk00000003/sig00000be9 , \blk00000003/sig00000be9 , +\blk00000003/sig00000be9 , \blk00000003/sig00000be9 , \blk00000003/sig00000be9 , \blk00000003/sig00000be9 , \blk00000003/sig00000be9 , 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\NLW_blk00000003/blk00000ae3_P<46>_UNCONNECTED , +\NLW_blk00000003/blk00000ae3_P<45>_UNCONNECTED , \NLW_blk00000003/blk00000ae3_P<44>_UNCONNECTED , \NLW_blk00000003/blk00000ae3_P<43>_UNCONNECTED , +\NLW_blk00000003/blk00000ae3_P<42>_UNCONNECTED , \NLW_blk00000003/blk00000ae3_P<41>_UNCONNECTED , \NLW_blk00000003/blk00000ae3_P<40>_UNCONNECTED , +\NLW_blk00000003/blk00000ae3_P<39>_UNCONNECTED , \NLW_blk00000003/blk00000ae3_P<38>_UNCONNECTED , \NLW_blk00000003/blk00000ae3_P<37>_UNCONNECTED , +\NLW_blk00000003/blk00000ae3_P<36>_UNCONNECTED , \blk00000003/sig00000c60 , \blk00000003/sig00000c61 , \blk00000003/sig00000c62 , +\blk00000003/sig00000c63 , \blk00000003/sig00000c64 , \blk00000003/sig00000c65 , \blk00000003/sig00000c66 , \blk00000003/sig00000c67 , +\blk00000003/sig00000c68 , \blk00000003/sig00000c69 , \blk00000003/sig00000c6a , \blk00000003/sig00000c6b , \blk00000003/sig00000c6c , +\blk00000003/sig00000c6d , \blk00000003/sig00000c6e , \blk00000003/sig00000c6f , \blk00000003/sig00000c70 , \blk00000003/sig00000c71 , +\blk00000003/sig00000c72 , \blk00000003/sig00000c73 , \blk00000003/sig00000c74 , \blk00000003/sig00000c75 , \blk00000003/sig00000c76 , +\blk00000003/sig00000c77 , \blk00000003/sig00000c78 , \blk00000003/sig00000c79 , \blk00000003/sig00000c7a , \blk00000003/sig00000c7b , +\blk00000003/sig00000c7c , \blk00000003/sig00000c7d , \blk00000003/sig00000c7e , \blk00000003/sig00000c7f , \blk00000003/sig00000c80 , +\blk00000003/sig00000c81 , \blk00000003/sig00000c82 , \blk00000003/sig00000c83 }), + .OPMODE({\blk00000003/sig0000005f , \blk00000003/sig0000005f , \blk00000003/sig0000005f , \blk00000003/sig0000005f , \blk00000003/sig00000065 , +\blk00000003/sig00000065 , \blk00000003/sig0000005f , \blk00000003/sig00000065 }), + .PCIN({\blk00000003/sig00000c19 , \blk00000003/sig00000c1a , \blk00000003/sig00000c1b , \blk00000003/sig00000c1c , \blk00000003/sig00000c1d , +\blk00000003/sig00000c1e , \blk00000003/sig00000c1f , \blk00000003/sig00000c20 , \blk00000003/sig00000c21 , \blk00000003/sig00000c22 , +\blk00000003/sig00000c23 , \blk00000003/sig00000c24 , \blk00000003/sig00000c25 , \blk00000003/sig00000c26 , \blk00000003/sig00000c27 , +\blk00000003/sig00000c28 , \blk00000003/sig00000c29 , \blk00000003/sig00000c2a , \blk00000003/sig00000c2b , \blk00000003/sig00000c2c , +\blk00000003/sig00000c2d , \blk00000003/sig00000c2e , \blk00000003/sig00000c2f , \blk00000003/sig00000c30 , \blk00000003/sig00000c31 , +\blk00000003/sig00000c32 , \blk00000003/sig00000c33 , \blk00000003/sig00000c34 , \blk00000003/sig00000c35 , \blk00000003/sig00000c36 , +\blk00000003/sig00000c37 , \blk00000003/sig00000c38 , \blk00000003/sig00000c39 , \blk00000003/sig00000c3a , \blk00000003/sig00000c3b , +\blk00000003/sig00000c3c , \blk00000003/sig00000c3d , \blk00000003/sig00000c3e , \blk00000003/sig00000c3f , \blk00000003/sig00000c40 , +\blk00000003/sig00000c41 , \blk00000003/sig00000c42 , \blk00000003/sig00000c43 , \blk00000003/sig00000c44 , \blk00000003/sig00000c45 , +\blk00000003/sig00000c46 , \blk00000003/sig00000c47 , \blk00000003/sig00000c48 }), + .PCOUT({\NLW_blk00000003/blk00000ae3_PCOUT<47>_UNCONNECTED , \NLW_blk00000003/blk00000ae3_PCOUT<46>_UNCONNECTED , +\NLW_blk00000003/blk00000ae3_PCOUT<45>_UNCONNECTED , \NLW_blk00000003/blk00000ae3_PCOUT<44>_UNCONNECTED , +\NLW_blk00000003/blk00000ae3_PCOUT<43>_UNCONNECTED , \NLW_blk00000003/blk00000ae3_PCOUT<42>_UNCONNECTED , +\NLW_blk00000003/blk00000ae3_PCOUT<41>_UNCONNECTED , \NLW_blk00000003/blk00000ae3_PCOUT<40>_UNCONNECTED , +\NLW_blk00000003/blk00000ae3_PCOUT<39>_UNCONNECTED , \NLW_blk00000003/blk00000ae3_PCOUT<38>_UNCONNECTED , +\NLW_blk00000003/blk00000ae3_PCOUT<37>_UNCONNECTED , \NLW_blk00000003/blk00000ae3_PCOUT<36>_UNCONNECTED , +\NLW_blk00000003/blk00000ae3_PCOUT<35>_UNCONNECTED , \NLW_blk00000003/blk00000ae3_PCOUT<34>_UNCONNECTED , +\NLW_blk00000003/blk00000ae3_PCOUT<33>_UNCONNECTED , \NLW_blk00000003/blk00000ae3_PCOUT<32>_UNCONNECTED , +\NLW_blk00000003/blk00000ae3_PCOUT<31>_UNCONNECTED , \NLW_blk00000003/blk00000ae3_PCOUT<30>_UNCONNECTED , +\NLW_blk00000003/blk00000ae3_PCOUT<29>_UNCONNECTED , \NLW_blk00000003/blk00000ae3_PCOUT<28>_UNCONNECTED , +\NLW_blk00000003/blk00000ae3_PCOUT<27>_UNCONNECTED , \NLW_blk00000003/blk00000ae3_PCOUT<26>_UNCONNECTED , +\NLW_blk00000003/blk00000ae3_PCOUT<25>_UNCONNECTED , \NLW_blk00000003/blk00000ae3_PCOUT<24>_UNCONNECTED , +\NLW_blk00000003/blk00000ae3_PCOUT<23>_UNCONNECTED , \NLW_blk00000003/blk00000ae3_PCOUT<22>_UNCONNECTED , +\NLW_blk00000003/blk00000ae3_PCOUT<21>_UNCONNECTED , \NLW_blk00000003/blk00000ae3_PCOUT<20>_UNCONNECTED , +\NLW_blk00000003/blk00000ae3_PCOUT<19>_UNCONNECTED , \NLW_blk00000003/blk00000ae3_PCOUT<18>_UNCONNECTED , +\NLW_blk00000003/blk00000ae3_PCOUT<17>_UNCONNECTED , \NLW_blk00000003/blk00000ae3_PCOUT<16>_UNCONNECTED , +\NLW_blk00000003/blk00000ae3_PCOUT<15>_UNCONNECTED , \NLW_blk00000003/blk00000ae3_PCOUT<14>_UNCONNECTED , +\NLW_blk00000003/blk00000ae3_PCOUT<13>_UNCONNECTED , \NLW_blk00000003/blk00000ae3_PCOUT<12>_UNCONNECTED , +\NLW_blk00000003/blk00000ae3_PCOUT<11>_UNCONNECTED , \NLW_blk00000003/blk00000ae3_PCOUT<10>_UNCONNECTED , +\NLW_blk00000003/blk00000ae3_PCOUT<9>_UNCONNECTED , \NLW_blk00000003/blk00000ae3_PCOUT<8>_UNCONNECTED , +\NLW_blk00000003/blk00000ae3_PCOUT<7>_UNCONNECTED , \NLW_blk00000003/blk00000ae3_PCOUT<6>_UNCONNECTED , +\NLW_blk00000003/blk00000ae3_PCOUT<5>_UNCONNECTED , \NLW_blk00000003/blk00000ae3_PCOUT<4>_UNCONNECTED , +\NLW_blk00000003/blk00000ae3_PCOUT<3>_UNCONNECTED , \NLW_blk00000003/blk00000ae3_PCOUT<2>_UNCONNECTED , +\NLW_blk00000003/blk00000ae3_PCOUT<1>_UNCONNECTED , \NLW_blk00000003/blk00000ae3_PCOUT<0>_UNCONNECTED }), + .BCOUT({\NLW_blk00000003/blk00000ae3_BCOUT<17>_UNCONNECTED , \NLW_blk00000003/blk00000ae3_BCOUT<16>_UNCONNECTED , +\NLW_blk00000003/blk00000ae3_BCOUT<15>_UNCONNECTED , \NLW_blk00000003/blk00000ae3_BCOUT<14>_UNCONNECTED , +\NLW_blk00000003/blk00000ae3_BCOUT<13>_UNCONNECTED , \NLW_blk00000003/blk00000ae3_BCOUT<12>_UNCONNECTED , +\NLW_blk00000003/blk00000ae3_BCOUT<11>_UNCONNECTED , \NLW_blk00000003/blk00000ae3_BCOUT<10>_UNCONNECTED , +\NLW_blk00000003/blk00000ae3_BCOUT<9>_UNCONNECTED , \NLW_blk00000003/blk00000ae3_BCOUT<8>_UNCONNECTED , +\NLW_blk00000003/blk00000ae3_BCOUT<7>_UNCONNECTED , \NLW_blk00000003/blk00000ae3_BCOUT<6>_UNCONNECTED , +\NLW_blk00000003/blk00000ae3_BCOUT<5>_UNCONNECTED , \NLW_blk00000003/blk00000ae3_BCOUT<4>_UNCONNECTED , +\NLW_blk00000003/blk00000ae3_BCOUT<3>_UNCONNECTED , \NLW_blk00000003/blk00000ae3_BCOUT<2>_UNCONNECTED , +\NLW_blk00000003/blk00000ae3_BCOUT<1>_UNCONNECTED , \NLW_blk00000003/blk00000ae3_BCOUT<0>_UNCONNECTED }) + ); + DSP48A #( + .A0REG ( 1 ), + .A1REG ( 1 ), + .B0REG ( 1 ), + .B1REG ( 1 ), + .CARRYINREG ( 0 ), + .CARRYINSEL ( "OPMODE5" ), + .CREG ( 1 ), + .DREG ( 0 ), + .MREG ( 1 ), + .OPMODEREG ( 0 ), + .PREG ( 1 ), + .RSTTYPE ( "SYNC" )) + \blk00000003/blk00000ae2 ( + .CARRYIN(\blk00000003/sig0000005f ), + .CARRYOUT(\NLW_blk00000003/blk00000ae2_CARRYOUT_UNCONNECTED ), + .CLK(clk), + .RSTA(\blk00000003/sig0000005f ), + .RSTB(\blk00000003/sig0000005f ), + .RSTM(\blk00000003/sig0000005f ), + .RSTP(\blk00000003/sig0000005f ), + .RSTC(\blk00000003/sig0000005f ), + .RSTD(\blk00000003/sig0000005f ), + .RSTCARRYIN(\blk00000003/sig0000005f ), + .RSTOPMODE(\blk00000003/sig0000005f ), + .CEA(\blk00000003/sig00000065 ), + .CEB(\blk00000003/sig00000065 ), + .CEM(\blk00000003/sig00000065 ), + .CEP(\blk00000003/sig00000065 ), + .CEC(\blk00000003/sig00000065 ), + .CED(\blk00000003/sig0000005f ), + .CECARRYIN(\blk00000003/sig0000005f ), + .CEOPMODE(\blk00000003/sig0000005f ), + .A({\blk00000003/sig0000005f , \blk00000003/sig00000b9f , \blk00000003/sig00000ba0 , \blk00000003/sig00000ba1 , \blk00000003/sig00000ba2 , +\blk00000003/sig00000ba3 , \blk00000003/sig00000ba4 , \blk00000003/sig00000ba5 , \blk00000003/sig00000ba6 , \blk00000003/sig00000ba7 , +\blk00000003/sig00000ba8 , \blk00000003/sig00000ba9 , \blk00000003/sig00000baa , \blk00000003/sig00000bab , \blk00000003/sig00000bac , +\blk00000003/sig00000bad , \blk00000003/sig00000bae , \blk00000003/sig00000baf }), + .B({\blk00000003/sig00000bb0 , \blk00000003/sig00000bb0 , \blk00000003/sig00000bb2 , \blk00000003/sig00000bb3 , \blk00000003/sig00000bb4 , +\blk00000003/sig00000bb5 , \blk00000003/sig00000bb6 , \blk00000003/sig00000bb7 , \blk00000003/sig00000bb8 , \blk00000003/sig00000bb9 , +\blk00000003/sig00000bba , \blk00000003/sig00000bbb , \blk00000003/sig00000bbc , \blk00000003/sig00000bbd , \blk00000003/sig00000bbe , +\blk00000003/sig00000bbf , \blk00000003/sig00000bc0 , \blk00000003/sig0000005f }), + .D({\blk00000003/sig0000005f , \blk00000003/sig0000005f , \blk00000003/sig0000005f , \blk00000003/sig0000005f , \blk00000003/sig0000005f , +\blk00000003/sig0000005f , \blk00000003/sig0000005f , \blk00000003/sig0000005f , \blk00000003/sig0000005f , \blk00000003/sig0000005f , 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\blk00000003/sig00000bf9 , \blk00000003/sig00000bfa , \blk00000003/sig00000bfb , \blk00000003/sig00000bfc , +\blk00000003/sig00000bfd , \blk00000003/sig00000bfe , \blk00000003/sig00000bff , \blk00000003/sig00000c00 , \blk00000003/sig00000c01 , +\blk00000003/sig00000c02 , \blk00000003/sig00000c03 , \blk00000003/sig00000c04 , \blk00000003/sig00000c05 , \blk00000003/sig00000c06 , +\blk00000003/sig00000c07 , \blk00000003/sig00000c08 , \blk00000003/sig00000c09 , \blk00000003/sig00000c0a , \blk00000003/sig00000c0b , +\blk00000003/sig00000c0c , \blk00000003/sig00000c0d , \blk00000003/sig00000c0e , \blk00000003/sig00000c0f , \blk00000003/sig00000c10 , +\blk00000003/sig00000c11 , \blk00000003/sig00000c12 , \blk00000003/sig00000c13 , \blk00000003/sig00000c14 , \blk00000003/sig00000c15 , +\blk00000003/sig00000c16 , \blk00000003/sig00000c17 , \blk00000003/sig00000c18 }), + .OPMODE({\blk00000003/sig0000005f , \blk00000003/sig0000005f , \blk00000003/sig0000005f , \blk00000003/sig0000005f , \blk00000003/sig00000065 , +\blk00000003/sig00000065 , \blk00000003/sig0000005f , \blk00000003/sig00000065 }), + .PCIN({\blk00000003/sig0000005f , \blk00000003/sig0000005f , \blk00000003/sig0000005f , \blk00000003/sig0000005f , \blk00000003/sig0000005f , +\blk00000003/sig0000005f , \blk00000003/sig0000005f , \blk00000003/sig0000005f , \blk00000003/sig0000005f , \blk00000003/sig0000005f , +\blk00000003/sig0000005f , \blk00000003/sig0000005f , \blk00000003/sig0000005f , \blk00000003/sig0000005f , \blk00000003/sig0000005f , +\blk00000003/sig0000005f , \blk00000003/sig0000005f , \blk00000003/sig0000005f , \blk00000003/sig0000005f , \blk00000003/sig0000005f , +\blk00000003/sig0000005f , \blk00000003/sig0000005f , \blk00000003/sig0000005f , \blk00000003/sig0000005f , \blk00000003/sig0000005f , +\blk00000003/sig0000005f , \blk00000003/sig0000005f , \blk00000003/sig0000005f , \blk00000003/sig0000005f , \blk00000003/sig0000005f , +\blk00000003/sig0000005f , \blk00000003/sig0000005f , \blk00000003/sig0000005f , \blk00000003/sig0000005f , \blk00000003/sig0000005f , +\blk00000003/sig0000005f , \blk00000003/sig0000005f , \blk00000003/sig0000005f , \blk00000003/sig0000005f , \blk00000003/sig0000005f , +\blk00000003/sig0000005f , \blk00000003/sig0000005f , \blk00000003/sig0000005f , \blk00000003/sig0000005f , \blk00000003/sig0000005f , +\blk00000003/sig0000005f , \blk00000003/sig0000005f , \blk00000003/sig0000005f }), + .PCOUT({\blk00000003/sig00000c19 , \blk00000003/sig00000c1a , \blk00000003/sig00000c1b , \blk00000003/sig00000c1c , \blk00000003/sig00000c1d , +\blk00000003/sig00000c1e , \blk00000003/sig00000c1f , \blk00000003/sig00000c20 , \blk00000003/sig00000c21 , \blk00000003/sig00000c22 , +\blk00000003/sig00000c23 , \blk00000003/sig00000c24 , \blk00000003/sig00000c25 , \blk00000003/sig00000c26 , \blk00000003/sig00000c27 , +\blk00000003/sig00000c28 , \blk00000003/sig00000c29 , \blk00000003/sig00000c2a , \blk00000003/sig00000c2b , \blk00000003/sig00000c2c , +\blk00000003/sig00000c2d , \blk00000003/sig00000c2e , \blk00000003/sig00000c2f , \blk00000003/sig00000c30 , \blk00000003/sig00000c31 , +\blk00000003/sig00000c32 , \blk00000003/sig00000c33 , \blk00000003/sig00000c34 , \blk00000003/sig00000c35 , \blk00000003/sig00000c36 , +\blk00000003/sig00000c37 , \blk00000003/sig00000c38 , \blk00000003/sig00000c39 , \blk00000003/sig00000c3a , \blk00000003/sig00000c3b , +\blk00000003/sig00000c3c , \blk00000003/sig00000c3d , \blk00000003/sig00000c3e , \blk00000003/sig00000c3f , \blk00000003/sig00000c40 , +\blk00000003/sig00000c41 , \blk00000003/sig00000c42 , \blk00000003/sig00000c43 , \blk00000003/sig00000c44 , \blk00000003/sig00000c45 , +\blk00000003/sig00000c46 , \blk00000003/sig00000c47 , \blk00000003/sig00000c48 }), + .BCOUT({\blk00000003/sig00000c49 , \blk00000003/sig00000c4a , \blk00000003/sig00000c4b , \blk00000003/sig00000c4c , \blk00000003/sig00000c4d , +\blk00000003/sig00000c4e , \blk00000003/sig00000c4f , \blk00000003/sig00000c50 , \blk00000003/sig00000c51 , \blk00000003/sig00000c52 , +\blk00000003/sig00000c53 , \blk00000003/sig00000c54 , \blk00000003/sig00000c55 , \blk00000003/sig00000c56 , \blk00000003/sig00000c57 , +\blk00000003/sig00000c58 , \blk00000003/sig00000c59 , \blk00000003/sig00000c5a }) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000abe ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig00000b7b ), + .R(\blk00000003/sig0000005f ), + .Q(\blk00000003/sig00000b5c ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000abd ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig00000b78 ), + .R(\blk00000003/sig0000005f ), + .Q(\blk00000003/sig00000b7e ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000abc ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig00000b75 ), + .R(\blk00000003/sig0000005f ), + .Q(\blk00000003/sig00000b7d ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000abb ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig00000b72 ), + .R(\blk00000003/sig0000005f ), + .Q(\blk00000003/sig00000b7c ) + ); + LUT4 #( + .INIT ( 16'h00CA )) + \blk00000003/blk00000aba ( + .I0(\blk00000003/sig0000005f ), + .I1(\blk00000003/sig0000005f ), + .I2(\blk00000003/sig00000b5f ), + .I3(\blk00000003/sig0000005f ), + .O(\blk00000003/sig00000b79 ) + ); + LUT4 #( + .INIT ( 16'h00CA )) + \blk00000003/blk00000ab9 ( + .I0(\blk00000003/sig0000005f ), + .I1(\blk00000003/sig00000b60 ), + .I2(\blk00000003/sig00000b5f ), + .I3(\blk00000003/sig0000005f ), + .O(\blk00000003/sig00000b76 ) + ); + LUT4 #( + .INIT ( 16'h00CA )) + \blk00000003/blk00000ab8 ( + .I0(\blk00000003/sig0000005f ), + .I1(\blk00000003/sig00000b61 ), + .I2(\blk00000003/sig00000b5f ), + .I3(\blk00000003/sig0000005f ), + .O(\blk00000003/sig00000b73 ) + ); + LUT4 #( + .INIT ( 16'h00CA )) + \blk00000003/blk00000ab7 ( + .I0(\blk00000003/sig0000005f ), + .I1(\blk00000003/sig0000005f ), + .I2(\blk00000003/sig00000b5f ), + .I3(\blk00000003/sig0000005f ), + .O(\blk00000003/sig00000b70 ) + ); + LUT4 #( + .INIT ( 16'h00CA )) + \blk00000003/blk00000ab6 ( + .I0(\blk00000003/sig0000005f ), + .I1(\blk00000003/sig00000b6f ), + .I2(\blk00000003/sig00000b5f ), + .I3(\blk00000003/sig0000005f ), + .O(\blk00000003/sig00000b7a ) + ); + LUT4 #( + .INIT ( 16'h00CA )) + \blk00000003/blk00000ab5 ( + .I0(\blk00000003/sig0000005f ), + .I1(\blk00000003/sig00000b6e ), + .I2(\blk00000003/sig00000b5f ), + .I3(\blk00000003/sig0000005f ), + .O(\blk00000003/sig00000b77 ) + ); + LUT4 #( + .INIT ( 16'h00CA )) + \blk00000003/blk00000ab4 ( + .I0(\blk00000003/sig00000b60 ), + .I1(\blk00000003/sig00000b6d ), + .I2(\blk00000003/sig00000b5f ), + .I3(\blk00000003/sig0000005f ), + .O(\blk00000003/sig00000b74 ) + ); + LUT4 #( + .INIT ( 16'h00CA )) + \blk00000003/blk00000ab3 ( + .I0(\blk00000003/sig00000b61 ), + .I1(\blk00000003/sig00000b6c ), + .I2(\blk00000003/sig00000b5f ), + .I3(\blk00000003/sig0000005f ), + .O(\blk00000003/sig00000b71 ) + ); + MUXF5 \blk00000003/blk00000ab2 ( + .I0(\blk00000003/sig00000b79 ), + .I1(\blk00000003/sig00000b7a ), + .S(\blk00000003/sig00000b5e ), + .O(\blk00000003/sig00000b7b ) + ); + MUXF5 \blk00000003/blk00000ab1 ( + .I0(\blk00000003/sig00000b76 ), + .I1(\blk00000003/sig00000b77 ), + .S(\blk00000003/sig00000b5e ), + .O(\blk00000003/sig00000b78 ) + ); + MUXF5 \blk00000003/blk00000ab0 ( + .I0(\blk00000003/sig00000b73 ), + .I1(\blk00000003/sig00000b74 ), + .S(\blk00000003/sig00000b5e ), + .O(\blk00000003/sig00000b75 ) + ); + MUXF5 \blk00000003/blk00000aaf ( + .I0(\blk00000003/sig00000b70 ), + .I1(\blk00000003/sig00000b71 ), + .S(\blk00000003/sig00000b5e ), + .O(\blk00000003/sig00000b72 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000aae ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig00000b65 ), + .Q(\blk00000003/sig00000b6f ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000aad ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig00000b68 ), + .Q(\blk00000003/sig00000b6e ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000aac ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig00000b6b ), + .Q(\blk00000003/sig00000b6d ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000aab ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig00000b63 ), + .Q(\blk00000003/sig00000b6c ) + ); + MUXCY \blk00000003/blk00000aaa ( + .CI(\blk00000003/sig0000005f ), + .DI(\blk00000003/sig0000005f ), + .S(\blk00000003/sig00000b62 ), + .O(\blk00000003/sig00000b69 ) + ); + MUXCY \blk00000003/blk00000aa9 ( + .CI(\blk00000003/sig00000b69 ), + .DI(\blk00000003/sig00000b5b ), + .S(\blk00000003/sig00000b6a ), + .O(\blk00000003/sig00000b66 ) + ); + MUXCY \blk00000003/blk00000aa8 ( + .CI(\blk00000003/sig00000b66 ), + .DI(\blk00000003/sig0000005f ), + .S(\blk00000003/sig00000b67 ), + .O(\blk00000003/sig00000b64 ) + ); + XORCY \blk00000003/blk00000aa7 ( + .CI(\blk00000003/sig00000b69 ), + .LI(\blk00000003/sig00000b6a ), + .O(\blk00000003/sig00000b6b ) + ); + XORCY \blk00000003/blk00000aa6 ( + .CI(\blk00000003/sig00000b66 ), + .LI(\blk00000003/sig00000b67 ), + .O(\blk00000003/sig00000b68 ) + ); + XORCY \blk00000003/blk00000aa5 ( + .CI(\blk00000003/sig00000b64 ), + .LI(\blk00000003/sig0000005f ), + .O(\blk00000003/sig00000b65 ) + ); + XORCY \blk00000003/blk00000aa4 ( + .CI(\blk00000003/sig0000005f ), + .LI(\blk00000003/sig00000b62 ), + .O(\blk00000003/sig00000b63 ) + ); + FD #( + .INIT ( 1'b0 )) + \blk00000003/blk00000aa3 ( + .C(clk), + .D(\blk00000003/sig00000b5b ), + .Q(\blk00000003/sig00000b61 ) + ); + FD #( + .INIT ( 1'b0 )) + \blk00000003/blk00000aa2 ( + .C(clk), + .D(\blk00000003/sig00000b5a ), + .Q(\blk00000003/sig00000b60 ) + ); + FD #( + .INIT ( 1'b0 )) + \blk00000003/blk00000aa1 ( + .C(clk), + .D(\blk00000003/sig00000b59 ), + .Q(\blk00000003/sig00000b5f ) + ); + FD #( + .INIT ( 1'b0 )) + \blk00000003/blk00000aa0 ( + .C(clk), + .D(\blk00000003/sig00000b58 ), + .Q(\blk00000003/sig00000b5e ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000a90 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig00000b04 ), + .Q(\blk00000003/sig00000a87 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000a8f ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig00000b02 ), + .Q(\blk00000003/sig00000a86 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000a8e ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig00000aff ), + .Q(\blk00000003/sig00000a85 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000a8d ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig00000afc ), + .Q(\blk00000003/sig00000a84 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000a8c ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig00000af9 ), + .Q(\blk00000003/sig00000a83 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000a8b ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig00000af6 ), + .Q(\blk00000003/sig00000a82 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000a8a ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig00000af3 ), + .Q(\blk00000003/sig00000a81 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000a89 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig00000af0 ), + .Q(\blk00000003/sig00000a80 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000a88 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig00000aed ), + .Q(\blk00000003/sig00000a7f ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000a87 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig00000aea ), + .Q(\blk00000003/sig00000a7e ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000a86 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig00000ae7 ), + .Q(\blk00000003/sig00000a7d ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000a85 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig00000ae4 ), + .Q(\blk00000003/sig00000a7c ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000a84 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig00000ae1 ), + .Q(\blk00000003/sig00000a7b ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000a83 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig00000ade ), + .Q(\blk00000003/sig00000a7a ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000a82 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig00000adb ), + .Q(\blk00000003/sig00000a79 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000a81 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig00000ad8 ), + .Q(\blk00000003/sig00000a78 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000a80 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig00000ad5 ), + .Q(\blk00000003/sig00000a77 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000a7f ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig00000ad2 ), + .Q(\blk00000003/sig00000a76 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000a7e ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig00000acf ), + .Q(\blk00000003/sig00000a75 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000a7d ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig00000acc ), + .Q(\blk00000003/sig00000a74 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000a7c ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig00000ac9 ), + .Q(\blk00000003/sig00000a73 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000a7b ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig00000b42 ), + .Q(\blk00000003/sig00000b57 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000a7a ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig00000b40 ), + .Q(\blk00000003/sig00000b56 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000a79 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig00000b3d ), + .Q(\blk00000003/sig00000b55 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000a78 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig00000b3a ), + .Q(\blk00000003/sig00000b54 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000a77 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig00000b37 ), + .Q(\blk00000003/sig00000b53 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000a76 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig00000b34 ), + .Q(\blk00000003/sig00000b52 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000a75 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig00000b31 ), + .Q(\blk00000003/sig00000b51 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000a74 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig00000b2e ), + .Q(\blk00000003/sig00000b50 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000a73 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig00000b2b ), + .Q(\blk00000003/sig00000b4f ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000a72 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig00000b28 ), + .Q(\blk00000003/sig00000b4e ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000a71 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig00000b25 ), + .Q(\blk00000003/sig00000b4d ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000a70 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig00000b22 ), + .Q(\blk00000003/sig00000b4c ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000a6f ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig00000b1f ), + .Q(\blk00000003/sig00000b4b ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000a6e ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig00000b1c ), + .Q(\blk00000003/sig00000b4a ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000a6d ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig00000b19 ), + .Q(\blk00000003/sig00000b49 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000a6c ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig00000b16 ), + .Q(\blk00000003/sig00000b48 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000a6b ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig00000b13 ), + .Q(\blk00000003/sig00000b47 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000a6a ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig00000b10 ), + .Q(\blk00000003/sig00000b46 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000a69 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig00000b0d ), + .Q(\blk00000003/sig00000b45 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000a68 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig00000b0a ), + .Q(\blk00000003/sig00000b44 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000a67 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig00000b07 ), + .Q(\blk00000003/sig00000b43 ) + ); + MUXCY \blk00000003/blk00000a66 ( + .CI(\blk00000003/sig0000005f ), + .DI(\blk00000003/sig00000ac6 ), + .S(\blk00000003/sig00000b41 ), + .O(\blk00000003/sig00000b3e ) + ); + MUXCY \blk00000003/blk00000a65 ( + .CI(\blk00000003/sig00000b3e ), + .DI(\blk00000003/sig00000ac5 ), + .S(\blk00000003/sig00000b3f ), + .O(\blk00000003/sig00000b3b ) + ); + MUXCY \blk00000003/blk00000a64 ( + .CI(\blk00000003/sig00000b3b ), + .DI(\blk00000003/sig00000ac4 ), + .S(\blk00000003/sig00000b3c ), + .O(\blk00000003/sig00000b38 ) + ); + MUXCY \blk00000003/blk00000a63 ( + .CI(\blk00000003/sig00000b38 ), + .DI(\blk00000003/sig00000ac3 ), + .S(\blk00000003/sig00000b39 ), + .O(\blk00000003/sig00000b35 ) + ); + MUXCY \blk00000003/blk00000a62 ( + .CI(\blk00000003/sig00000b35 ), + .DI(\blk00000003/sig00000ac2 ), + .S(\blk00000003/sig00000b36 ), + .O(\blk00000003/sig00000b32 ) + ); + MUXCY \blk00000003/blk00000a61 ( + .CI(\blk00000003/sig00000b32 ), + .DI(\blk00000003/sig00000ac1 ), + .S(\blk00000003/sig00000b33 ), + .O(\blk00000003/sig00000b2f ) + ); + MUXCY \blk00000003/blk00000a60 ( + .CI(\blk00000003/sig00000b2f ), + .DI(\blk00000003/sig00000ac0 ), + .S(\blk00000003/sig00000b30 ), + .O(\blk00000003/sig00000b2c ) + ); + MUXCY \blk00000003/blk00000a5f ( + .CI(\blk00000003/sig00000b2c ), + .DI(\blk00000003/sig00000abf ), + .S(\blk00000003/sig00000b2d ), + .O(\blk00000003/sig00000b29 ) + ); + MUXCY \blk00000003/blk00000a5e ( + .CI(\blk00000003/sig00000b29 ), + .DI(\blk00000003/sig00000abe ), + .S(\blk00000003/sig00000b2a ), + .O(\blk00000003/sig00000b26 ) + ); + MUXCY \blk00000003/blk00000a5d ( + .CI(\blk00000003/sig00000b26 ), + .DI(\blk00000003/sig00000abd ), + .S(\blk00000003/sig00000b27 ), + .O(\blk00000003/sig00000b23 ) + ); + MUXCY \blk00000003/blk00000a5c ( + .CI(\blk00000003/sig00000b23 ), + .DI(\blk00000003/sig00000abc ), + .S(\blk00000003/sig00000b24 ), + .O(\blk00000003/sig00000b20 ) + ); + MUXCY \blk00000003/blk00000a5b ( + .CI(\blk00000003/sig00000b20 ), + .DI(\blk00000003/sig00000abb ), + .S(\blk00000003/sig00000b21 ), + .O(\blk00000003/sig00000b1d ) + ); + MUXCY \blk00000003/blk00000a5a ( + .CI(\blk00000003/sig00000b1d ), + .DI(\blk00000003/sig00000aba ), + .S(\blk00000003/sig00000b1e ), + .O(\blk00000003/sig00000b1a ) + ); + MUXCY \blk00000003/blk00000a59 ( + .CI(\blk00000003/sig00000b1a ), + .DI(\blk00000003/sig00000ab9 ), + .S(\blk00000003/sig00000b1b ), + .O(\blk00000003/sig00000b17 ) + ); + MUXCY \blk00000003/blk00000a58 ( + .CI(\blk00000003/sig00000b17 ), + .DI(\blk00000003/sig00000ab8 ), + .S(\blk00000003/sig00000b18 ), + .O(\blk00000003/sig00000b14 ) + ); + MUXCY \blk00000003/blk00000a57 ( + .CI(\blk00000003/sig00000b14 ), + .DI(\blk00000003/sig00000ab7 ), + .S(\blk00000003/sig00000b15 ), + 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\blk00000003/blk0000092a ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig00000943 ), + .Q(\blk00000003/sig00000a27 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000929 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig00000940 ), + .Q(\blk00000003/sig00000a26 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000928 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig0000093d ), + .Q(\blk00000003/sig00000a25 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000927 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig0000093a ), + .Q(\blk00000003/sig00000a24 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000926 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig00000937 ), + .Q(\blk00000003/sig00000a23 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000925 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig00000934 ), + .Q(\blk00000003/sig00000a22 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000924 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig00000931 ), + .Q(\blk00000003/sig00000a21 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000923 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig0000092e ), + .Q(\blk00000003/sig00000a20 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000922 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig0000092b ), + .Q(\blk00000003/sig00000a1f ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000921 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig00000928 ), + .Q(\blk00000003/sig00000a1e ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000920 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig00000925 ), + .Q(\blk00000003/sig00000a1d ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000091f ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig00000922 ), + .Q(\blk00000003/sig00000a1c ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000091e ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig0000091d ), + .Q(\blk00000003/sig00000a1b ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000091d ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig0000091b ), + .Q(\blk00000003/sig00000a1a ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000091c ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig00000918 ), + .Q(\blk00000003/sig00000a19 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000091b ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig00000915 ), + .Q(\blk00000003/sig00000a18 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000091a ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig00000912 ), + .Q(\blk00000003/sig00000a17 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000919 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig0000090f ), + .Q(\blk00000003/sig00000a16 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000918 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig0000090c ), + .Q(\blk00000003/sig00000a15 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000917 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig00000909 ), + .Q(\blk00000003/sig00000a14 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000916 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig00000906 ), + .Q(\blk00000003/sig00000a13 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000915 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig00000903 ), + .Q(\blk00000003/sig00000a12 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000914 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig00000900 ), + .Q(\blk00000003/sig00000a11 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000913 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig000008fd ), + .Q(\blk00000003/sig00000a10 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000912 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig000008fa ), + .Q(\blk00000003/sig00000a0f ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000911 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig000008f7 ), + .Q(\blk00000003/sig00000a0e ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000910 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig000008f4 ), + .Q(\blk00000003/sig00000a0d ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000090f ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig000008f1 ), + .Q(\blk00000003/sig00000a0c ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000090e ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig000008ee ), + .Q(\blk00000003/sig00000a0b ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000090d ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig000008eb ), + .Q(\blk00000003/sig00000a0a ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000090c ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig000008e8 ), + .Q(\blk00000003/sig00000a09 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000090b ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig000008e5 ), + .Q(\blk00000003/sig00000a08 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000090a ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig000008e2 ), + .Q(\blk00000003/sig00000a07 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000909 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig00000a05 ), + .R(\blk00000003/sig0000005f ), + .Q(\blk00000003/sig00000a06 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000908 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig00000a03 ), + .R(\blk00000003/sig0000005f ), + .Q(\blk00000003/sig00000a04 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000907 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig00000a01 ), + .R(\blk00000003/sig0000005f ), + .Q(\blk00000003/sig00000a02 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000906 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig000009ff ), + .R(\blk00000003/sig0000005f ), + .Q(\blk00000003/sig00000a00 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000905 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig000009fd ), + .R(\blk00000003/sig0000005f ), + .Q(\blk00000003/sig000009fe ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000904 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig000009fb ), + .R(\blk00000003/sig0000005f ), + .Q(\blk00000003/sig000009fc ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000903 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig000009f9 ), + .R(\blk00000003/sig0000005f ), + .Q(\blk00000003/sig000009fa ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000902 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig000009f7 ), + .R(\blk00000003/sig0000005f ), + .Q(\blk00000003/sig000009f8 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000901 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig000009f5 ), + .R(\blk00000003/sig0000005f ), + .Q(\blk00000003/sig000009f6 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000900 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig000009f3 ), + .R(\blk00000003/sig0000005f ), + .Q(\blk00000003/sig000009f4 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000008ff ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig000009f1 ), + .R(\blk00000003/sig0000005f ), + .Q(\blk00000003/sig000009f2 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000008fe ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig000009ef ), + .R(\blk00000003/sig0000005f ), + .Q(\blk00000003/sig000009f0 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000008fd ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig000009ed ), + .R(\blk00000003/sig0000005f ), + .Q(\blk00000003/sig000009ee ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000008fc ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig000009eb ), + .R(\blk00000003/sig0000005f ), + .Q(\blk00000003/sig000009ec ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000008fb ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig000009e9 ), + .R(\blk00000003/sig0000005f ), + .Q(\blk00000003/sig000009ea ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000008fa ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig000009e7 ), + .R(\blk00000003/sig0000005f ), + .Q(\blk00000003/sig000009e8 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000008f9 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig000009e5 ), + .R(\blk00000003/sig0000005f ), + .Q(\blk00000003/sig000009e6 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000008f8 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig000009e3 ), + .R(\blk00000003/sig0000005f ), + .Q(\blk00000003/sig000009e4 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000008f7 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig000009e1 ), + .R(\blk00000003/sig0000005f ), + .Q(\blk00000003/sig000009e2 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000008f6 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig000009df ), + .R(\blk00000003/sig0000005f ), + .Q(\blk00000003/sig000009e0 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000008f5 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig000009dd ), + .R(\blk00000003/sig0000005f ), + .Q(\blk00000003/sig000009de ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000008f4 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig000009db ), + .R(\blk00000003/sig0000005f ), + .Q(\blk00000003/sig000009dc ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000008f3 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig000009d9 ), + .R(\blk00000003/sig0000005f ), + .Q(\blk00000003/sig000009da ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000008f2 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig000009d7 ), + .R(\blk00000003/sig0000005f ), + .Q(\blk00000003/sig000009d8 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000008f1 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig000009d5 ), + .R(\blk00000003/sig0000005f ), + .Q(\blk00000003/sig000009d6 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000008f0 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig000009d3 ), + .R(\blk00000003/sig0000005f ), + .Q(\blk00000003/sig000009d4 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000008ef ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig000009d1 ), + .R(\blk00000003/sig0000005f ), + .Q(\blk00000003/sig000009d2 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000008ee ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig000009cf ), + .R(\blk00000003/sig0000005f ), + .Q(\blk00000003/sig000009d0 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000008ed ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig000009cd ), + .R(\blk00000003/sig0000005f ), + .Q(\blk00000003/sig000009ce ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000008ec ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig000009cb ), + .R(\blk00000003/sig0000005f ), + .Q(\blk00000003/sig000009cc ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000008eb ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig000009c9 ), + .R(\blk00000003/sig0000005f ), + .Q(\blk00000003/sig000009ca ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000008ea ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig000009c7 ), + .R(\blk00000003/sig0000005f ), + .Q(\blk00000003/sig000009c8 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000008e9 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig000009c5 ), + .R(\blk00000003/sig0000005f ), + .Q(\blk00000003/sig000009c6 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000008e8 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig000009c3 ), + .R(\blk00000003/sig0000005f ), + .Q(\blk00000003/sig000009c4 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000008e7 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig000009c1 ), + .R(\blk00000003/sig0000005f ), + .Q(\blk00000003/sig000009c2 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000008e6 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig000009bf ), + .R(\blk00000003/sig0000005f ), + .Q(\blk00000003/sig000009c0 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000008e5 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig000009bd ), + .R(\blk00000003/sig0000005f ), + .Q(\blk00000003/sig000009be ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000008e4 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig000009bb ), + .R(\blk00000003/sig0000005f ), + .Q(\blk00000003/sig000009bc ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000008e3 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig000009b9 ), + .R(\blk00000003/sig0000005f ), + .Q(\blk00000003/sig000009ba ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000008e2 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig000009b7 ), + .R(\blk00000003/sig0000005f ), + .Q(\blk00000003/sig000009b8 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000008e1 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig000009b5 ), + .R(\blk00000003/sig0000005f ), + .Q(\blk00000003/sig000009b6 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000008e0 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig000009b3 ), + .R(\blk00000003/sig0000005f ), + .Q(\blk00000003/sig000009b4 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000008df ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig000009b1 ), + .R(\blk00000003/sig0000005f ), + .Q(\blk00000003/sig000009b2 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000008de ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig000009af ), + .R(\blk00000003/sig0000005f ), + .Q(\blk00000003/sig000009b0 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000008dd ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig000009ad ), + .R(\blk00000003/sig0000005f ), + .Q(\blk00000003/sig000009ae ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000008dc ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig000009ab ), + .R(\blk00000003/sig0000005f ), + .Q(\blk00000003/sig000009ac ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000008db ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig000009a9 ), + .R(\blk00000003/sig0000005f ), + .Q(\blk00000003/sig000009aa ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000008da ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig000009a7 ), + .R(\blk00000003/sig0000005f ), + .Q(\blk00000003/sig000009a8 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000008d9 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig000009a5 ), + .R(\blk00000003/sig0000005f ), + .Q(\blk00000003/sig000009a6 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000008d8 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig000009a3 ), + .R(\blk00000003/sig0000005f ), + .Q(\blk00000003/sig000009a4 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000008d7 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig000009a1 ), + .R(\blk00000003/sig0000005f ), + .Q(\blk00000003/sig000009a2 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000008d6 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig0000099f ), + .R(\blk00000003/sig0000005f ), + .Q(\blk00000003/sig000009a0 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000008d5 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig0000099d ), + .R(\blk00000003/sig0000005f ), + .Q(\blk00000003/sig0000099e ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000008d4 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig0000099b ), + .R(\blk00000003/sig0000005f ), + .Q(\blk00000003/sig0000099c ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000008d3 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig00000999 ), + .R(\blk00000003/sig0000005f ), + .Q(\blk00000003/sig0000099a ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000008d2 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig00000997 ), + .R(\blk00000003/sig0000005f ), + .Q(\blk00000003/sig00000998 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000008d1 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig00000995 ), + .R(\blk00000003/sig0000005f ), + .Q(\blk00000003/sig00000996 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000008d0 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig00000993 ), + .R(\blk00000003/sig0000005f ), + .Q(\blk00000003/sig00000994 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000008cf ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig00000991 ), + .R(\blk00000003/sig0000005f ), + .Q(\blk00000003/sig00000992 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000008ce ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig0000098f ), + .R(\blk00000003/sig0000005f ), + .Q(\blk00000003/sig00000990 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000008cd ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig0000098d ), + .R(\blk00000003/sig0000005f ), + .Q(\blk00000003/sig0000098e ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000008cc ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig0000098b ), + .R(\blk00000003/sig0000005f ), + .Q(\blk00000003/sig0000098c ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000008cb ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig00000989 ), + .R(\blk00000003/sig0000005f ), + .Q(\blk00000003/sig0000098a ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000008ca ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig00000987 ), + .R(\blk00000003/sig0000005f ), + .Q(\blk00000003/sig00000988 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000008c9 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + 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.CI(\blk00000003/sig00000821 ), + .LI(\blk00000003/sig00000822 ), + .O(\blk00000003/sig00000823 ) + ); + XORCY \blk00000003/blk0000076b ( + .CI(\blk00000003/sig0000081e ), + .LI(\blk00000003/sig0000081f ), + .O(\blk00000003/sig00000820 ) + ); + XORCY \blk00000003/blk0000076a ( + .CI(\blk00000003/sig0000081b ), + .LI(\blk00000003/sig0000081c ), + .O(\blk00000003/sig0000081d ) + ); + XORCY \blk00000003/blk00000769 ( + .CI(\blk00000003/sig00000818 ), + .LI(\blk00000003/sig00000819 ), + .O(\blk00000003/sig0000081a ) + ); + XORCY \blk00000003/blk00000768 ( + .CI(\blk00000003/sig00000815 ), + .LI(\blk00000003/sig00000816 ), + .O(\blk00000003/sig00000817 ) + ); + XORCY \blk00000003/blk00000767 ( + .CI(\blk00000003/sig00000812 ), + .LI(\blk00000003/sig00000813 ), + .O(\blk00000003/sig00000814 ) + ); + XORCY \blk00000003/blk00000766 ( + .CI(\blk00000003/sig0000080f ), + .LI(\blk00000003/sig00000810 ), + .O(\blk00000003/sig00000811 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000070e ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig000004a6 ), + .Q(\blk00000003/sig000007e6 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000070d ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig000007e6 ), + .Q(\blk00000003/sig000007e7 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000070c ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig000007e4 ), + .R(\blk00000003/sig0000005f ), + .Q(\blk00000003/sig000007e5 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000070b ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig000007e2 ), + .R(\blk00000003/sig0000005f ), + .Q(\blk00000003/sig000007e3 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000070a ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig000007e0 ), + .R(\blk00000003/sig0000005f ), + .Q(\blk00000003/sig000007e1 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000709 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig000007de ), + .R(\blk00000003/sig0000005f ), + .Q(\blk00000003/sig000007df ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000708 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig000007dc ), + .R(\blk00000003/sig0000005f ), + .Q(\blk00000003/sig000007dd ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000707 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig000007da ), + .R(\blk00000003/sig0000005f ), + .Q(\blk00000003/sig000007db ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000706 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig000007d8 ), + .R(\blk00000003/sig0000005f ), + .Q(\blk00000003/sig000007d9 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000705 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig000007d6 ), + .R(\blk00000003/sig0000005f ), + .Q(\blk00000003/sig000007d7 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000704 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig000007d4 ), + .R(\blk00000003/sig0000005f ), + .Q(\blk00000003/sig000007d5 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000703 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig000007d2 ), + .R(\blk00000003/sig0000005f ), + .Q(\blk00000003/sig000007d3 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000702 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig000007d0 ), + .R(\blk00000003/sig0000005f ), + .Q(\blk00000003/sig000007d1 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000701 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig000007ce ), + .R(\blk00000003/sig0000005f ), + .Q(\blk00000003/sig000007cf ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000700 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig000007cc ), + .R(\blk00000003/sig0000005f ), + .Q(\blk00000003/sig000007cd ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006ff ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig000007ca ), + .R(\blk00000003/sig0000005f ), + .Q(\blk00000003/sig000007cb ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006fe ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig000007c8 ), + .R(\blk00000003/sig0000005f ), + .Q(\blk00000003/sig000007c9 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006fd ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig000007c6 ), + .R(\blk00000003/sig0000005f ), + .Q(\blk00000003/sig000007c7 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006fc ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig000007c4 ), + .R(\blk00000003/sig0000005f ), + .Q(\blk00000003/sig000007c5 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006fb ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig000007c2 ), + .R(\blk00000003/sig0000005f ), + .Q(\blk00000003/sig000007c3 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006fa ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig000007c0 ), + .R(\blk00000003/sig0000005f ), + .Q(\blk00000003/sig000007c1 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006f9 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig000007be ), + .R(\blk00000003/sig0000005f ), + .Q(\blk00000003/sig000007bf ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006f8 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig000007bc ), + .R(\blk00000003/sig0000005f ), + .Q(\blk00000003/sig000007bd ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006f7 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig000007ba ), + .R(\blk00000003/sig0000005f ), + .Q(\blk00000003/sig000007bb ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006f6 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig000007b8 ), + .R(\blk00000003/sig0000005f ), + .Q(\blk00000003/sig000007b9 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006f5 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig000007b6 ), + .R(\blk00000003/sig0000005f ), + .Q(\blk00000003/sig000007b7 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006f4 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig000007b4 ), + .R(\blk00000003/sig0000005f ), + .Q(\blk00000003/sig000007b5 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006f3 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig000007b2 ), + .R(\blk00000003/sig0000005f ), + .Q(\blk00000003/sig000007b3 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006f2 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig000007b0 ), + .R(\blk00000003/sig0000005f ), + .Q(\blk00000003/sig000007b1 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006f1 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig000007ae ), + .R(\blk00000003/sig0000005f ), + .Q(\blk00000003/sig000007af ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006f0 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig000007ac ), + .R(\blk00000003/sig0000005f ), + .Q(\blk00000003/sig000007ad ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006ef ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig000007aa ), + .R(\blk00000003/sig0000005f ), + .Q(\blk00000003/sig000007ab ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006ee ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig000007a8 ), + .R(\blk00000003/sig0000005f ), + .Q(\blk00000003/sig000007a9 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006ed ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig000007a6 ), + .R(\blk00000003/sig0000005f ), + .Q(\blk00000003/sig000007a7 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006ec ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig000007a4 ), + .R(\blk00000003/sig0000005f ), + .Q(\blk00000003/sig000007a5 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006eb ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig000007a2 ), + .R(\blk00000003/sig0000005f ), + .Q(\blk00000003/sig000007a3 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006ea ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig000007a0 ), + .R(\blk00000003/sig0000005f ), + .Q(\blk00000003/sig000007a1 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006e9 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig0000079e ), + .R(\blk00000003/sig0000005f ), + .Q(\blk00000003/sig0000079f ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006e8 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig0000079c ), + .R(\blk00000003/sig0000005f ), + .Q(\blk00000003/sig0000079d ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006e7 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig0000079a ), + .R(\blk00000003/sig0000005f ), + .Q(\blk00000003/sig0000079b ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006e6 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig00000798 ), + .R(\blk00000003/sig0000005f ), + .Q(\blk00000003/sig00000799 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006e5 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig00000796 ), + .R(\blk00000003/sig0000005f ), + .Q(\blk00000003/sig00000797 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006e4 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig00000794 ), + .R(\blk00000003/sig0000005f ), + .Q(\blk00000003/sig00000795 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006e3 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig00000792 ), + .R(\blk00000003/sig0000005f ), + .Q(\blk00000003/sig00000793 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006e2 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig00000790 ), + .R(\blk00000003/sig0000005f ), + .Q(\blk00000003/sig00000791 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006e1 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig0000078e ), + .R(\blk00000003/sig0000005f ), + .Q(\blk00000003/sig0000078f ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006e0 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig0000078c ), + .R(\blk00000003/sig0000005f ), + .Q(\blk00000003/sig0000078d ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006df ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig0000078a ), + .R(\blk00000003/sig0000005f ), + .Q(\blk00000003/sig0000078b ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006de ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig00000788 ), + .R(\blk00000003/sig0000005f ), + .Q(\blk00000003/sig00000789 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006dd ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig00000786 ), + .R(\blk00000003/sig0000005f ), + .Q(\blk00000003/sig00000787 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006dc ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig00000784 ), + .R(\blk00000003/sig0000005f ), + .Q(\blk00000003/sig00000785 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006db ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig00000782 ), + .R(\blk00000003/sig0000005f ), + .Q(\blk00000003/sig00000783 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006da ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig00000780 ), + .R(\blk00000003/sig0000005f ), + .Q(\blk00000003/sig00000781 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006d9 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig0000077e ), + .R(\blk00000003/sig0000005f ), + .Q(\blk00000003/sig0000077f ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006d8 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig0000077c ), + .R(\blk00000003/sig0000005f ), + .Q(\blk00000003/sig0000077d ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006d7 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig0000077a ), + .R(\blk00000003/sig0000005f ), + .Q(\blk00000003/sig0000077b ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006d6 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig00000778 ), + .R(\blk00000003/sig0000005f ), + .Q(\blk00000003/sig00000779 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006d5 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig00000776 ), + .R(\blk00000003/sig0000005f ), + .Q(\blk00000003/sig00000777 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006d4 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig00000774 ), + .R(\blk00000003/sig0000005f ), + .Q(\blk00000003/sig00000775 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006d3 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig00000772 ), + .R(\blk00000003/sig0000005f ), + .Q(\blk00000003/sig00000773 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006d2 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig00000770 ), + .R(\blk00000003/sig0000005f ), + .Q(\blk00000003/sig00000771 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006d1 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig0000076e ), + .R(\blk00000003/sig0000005f ), + .Q(\blk00000003/sig0000076f ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006d0 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig0000076c ), + .R(\blk00000003/sig0000005f ), + .Q(\blk00000003/sig0000076d ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006cf ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig0000076a ), + .R(\blk00000003/sig0000005f ), + .Q(\blk00000003/sig0000076b ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006ce ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig00000768 ), + .R(\blk00000003/sig0000005f ), + .Q(\blk00000003/sig00000769 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006cd ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig00000766 ), + .R(\blk00000003/sig0000005f ), + .Q(\blk00000003/sig00000767 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006cc ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig00000764 ), + .R(\blk00000003/sig0000005f ), + .Q(\blk00000003/sig00000765 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006cb ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig00000762 ), + .R(\blk00000003/sig0000005f ), + .Q(\blk00000003/sig00000763 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006ca ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig00000760 ), + .R(\blk00000003/sig0000005f ), + .Q(\blk00000003/sig00000761 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006c9 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig0000075e ), + .R(\blk00000003/sig0000005f ), + .Q(\blk00000003/sig0000075f ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006c8 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig0000075c ), + .R(\blk00000003/sig0000005f ), + .Q(\blk00000003/sig0000075d ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006c7 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig0000075a ), + .R(\blk00000003/sig0000005f ), + .Q(\blk00000003/sig0000075b ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006c6 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig00000758 ), + .R(\blk00000003/sig0000005f ), + .Q(\blk00000003/sig00000759 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006c5 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig00000756 ), + .R(\blk00000003/sig0000005f ), + .Q(\blk00000003/sig00000757 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006c4 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig00000754 ), + .R(\blk00000003/sig0000005f ), + .Q(\blk00000003/sig00000755 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006c3 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig00000752 ), + .R(\blk00000003/sig0000005f ), + .Q(\blk00000003/sig00000753 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006c2 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig00000750 ), + .R(\blk00000003/sig0000005f ), + .Q(\blk00000003/sig00000751 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006c1 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig0000074e ), + .R(\blk00000003/sig0000005f ), + .Q(\blk00000003/sig0000074f ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006c0 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig0000074c ), + .R(\blk00000003/sig0000005f ), + .Q(\blk00000003/sig0000074d ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006bf ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig0000074a ), + .R(\blk00000003/sig0000005f ), + .Q(\blk00000003/sig0000074b ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006be ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig00000748 ), + .R(\blk00000003/sig0000005f ), + .Q(\blk00000003/sig0000071d ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006bd ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig00000745 ), + .R(\blk00000003/sig0000005f ), + .Q(\blk00000003/sig00000703 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006bc ( + .C(clk), + .CE(\blk00000003/sig0000071d ), + .D(\blk00000003/sig00000742 ), + .R(\blk00000003/sig0000005f ), + .Q(\blk00000003/sig00000749 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000006bb ( + .C(clk), + .CE(\blk00000003/sig0000071d ), + .D(\blk00000003/sig00000749 ), + .R(\blk00000003/sig0000005f ), + .Q(\blk00000003/sig00000747 ) + ); + LUT3 #( + .INIT ( 8'hAE )) + \blk00000003/blk000006ba ( + .I0(\blk00000003/sig00000242 ), + .I1(\blk00000003/sig0000071d ), + .I2(\blk00000003/sig00000747 ), + .O(\blk00000003/sig00000748 ) + ); + MUXCY \blk00000003/blk000006b9 ( + .CI(\blk00000003/sig0000073a ), + .DI(\blk00000003/sig0000005f ), + .S(\blk00000003/sig00000746 ), + .O(\blk00000003/sig00000744 ) + ); + XORCY \blk00000003/blk000006b8 ( + .CI(\blk00000003/sig00000744 ), + .LI(\blk00000003/sig0000005f ), + .O(\blk00000003/sig00000745 ) + ); + MUXCY \blk00000003/blk000006b7 ( + .CI(\blk00000003/sig00000065 ), + .DI(\blk00000003/sig0000005f ), + .S(\blk00000003/sig00000743 ), + .O(\blk00000003/sig0000072a ) + ); + XORCY \blk00000003/blk000006b6 ( + .CI(\blk00000003/sig00000740 ), + .LI(\blk00000003/sig0000005f ), + .O(\blk00000003/sig00000742 ) + ); + MUXCY \blk00000003/blk000006b5 ( + .CI(\blk00000003/sig00000065 ), + .DI(\blk00000003/sig0000005f ), + .S(\blk00000003/sig0000073e ), + .O(\blk00000003/sig00000741 ) + ); + MUXCY \blk00000003/blk000006b4 ( + .CI(\blk00000003/sig00000741 ), + .DI(\blk00000003/sig0000005f ), + .S(\blk00000003/sig0000073d ), + .O(\blk00000003/sig0000073f ) + ); + MUXCY \blk00000003/blk000006b3 ( + .CI(\blk00000003/sig0000073f ), + .DI(\blk00000003/sig0000005f ), + .S(\blk00000003/sig0000073c ), + .O(\blk00000003/sig00000740 ) + ); + LUT4 #( + .INIT ( 16'h9009 )) + \blk00000003/blk000006b2 ( + .I0(\blk00000003/sig00000729 ), + .I1(\blk00000003/sig00000065 ), + .I2(\blk00000003/sig00000727 ), + .I3(\blk00000003/sig0000005f ), + .O(\blk00000003/sig0000073e ) + ); + LUT4 #( + .INIT ( 16'h9009 )) + \blk00000003/blk000006b1 ( + .I0(\blk00000003/sig00000725 ), + .I1(\blk00000003/sig00000065 ), + .I2(\blk00000003/sig00000723 ), + .I3(\blk00000003/sig00000065 ), + .O(\blk00000003/sig0000073d ) + ); + LUT4 #( + .INIT ( 16'h9009 )) + \blk00000003/blk000006b0 ( + .I0(\blk00000003/sig00000721 ), + .I1(\blk00000003/sig00000065 ), + .I2(\blk00000003/sig0000071f ), + .I3(\blk00000003/sig00000065 ), + .O(\blk00000003/sig0000073c ) + ); + MUXCY \blk00000003/blk000006af ( + .CI(\blk00000003/sig00000065 ), + .DI(\blk00000003/sig0000005f ), + .S(\blk00000003/sig00000738 ), + .O(\blk00000003/sig0000073b ) + ); + MUXCY \blk00000003/blk000006ae ( + .CI(\blk00000003/sig0000073b ), + .DI(\blk00000003/sig0000005f ), + .S(\blk00000003/sig00000737 ), + .O(\blk00000003/sig00000739 ) + ); + MUXCY \blk00000003/blk000006ad ( + .CI(\blk00000003/sig00000739 ), + .DI(\blk00000003/sig0000005f ), + .S(\blk00000003/sig00000736 ), + .O(\blk00000003/sig0000073a ) + ); + LUT4 #( + .INIT ( 16'h9009 )) + \blk00000003/blk000006ac ( + .I0(\blk00000003/sig00000729 ), + .I1(\blk00000003/sig0000005f ), + .I2(\blk00000003/sig00000727 ), + .I3(\blk00000003/sig00000065 ), + .O(\blk00000003/sig00000738 ) + ); + LUT4 #( + .INIT ( 16'h9009 )) + \blk00000003/blk000006ab ( + .I0(\blk00000003/sig00000725 ), + .I1(\blk00000003/sig0000005f ), + .I2(\blk00000003/sig00000723 ), + .I3(\blk00000003/sig0000005f ), + .O(\blk00000003/sig00000737 ) + ); + LUT4 #( + .INIT ( 16'h9009 )) + \blk00000003/blk000006aa ( + .I0(\blk00000003/sig00000721 ), + .I1(\blk00000003/sig0000005f ), + .I2(\blk00000003/sig0000071f ), + .I3(\blk00000003/sig0000005f ), + .O(\blk00000003/sig00000736 ) + ); + XORCY \blk00000003/blk000006a9 ( + .CI(\blk00000003/sig00000734 ), + .LI(\blk00000003/sig00000735 ), + .O(\blk00000003/sig0000071e ) + ); + XORCY \blk00000003/blk000006a8 ( + .CI(\blk00000003/sig00000732 ), + .LI(\blk00000003/sig00000733 ), + .O(\blk00000003/sig00000720 ) + ); + XORCY \blk00000003/blk000006a7 ( + .CI(\blk00000003/sig00000730 ), + .LI(\blk00000003/sig00000731 ), + .O(\blk00000003/sig00000722 ) + ); + XORCY \blk00000003/blk000006a6 ( + .CI(\blk00000003/sig0000072e ), + .LI(\blk00000003/sig0000072f ), + .O(\blk00000003/sig00000724 ) + ); + XORCY \blk00000003/blk000006a5 ( + .CI(\blk00000003/sig0000072c ), + .LI(\blk00000003/sig0000072d ), + .O(\blk00000003/sig00000726 ) + ); + MUXCY \blk00000003/blk000006a4 ( + .CI(\blk00000003/sig00000732 ), + .DI(\blk00000003/sig0000005f ), + .S(\blk00000003/sig00000733 ), + .O(\blk00000003/sig00000734 ) + ); + MUXCY \blk00000003/blk000006a3 ( + .CI(\blk00000003/sig00000730 ), + .DI(\blk00000003/sig0000005f ), + .S(\blk00000003/sig00000731 ), + .O(\blk00000003/sig00000732 ) + ); + MUXCY \blk00000003/blk000006a2 ( + .CI(\blk00000003/sig0000072e ), + .DI(\blk00000003/sig0000005f ), + .S(\blk00000003/sig0000072f ), + .O(\blk00000003/sig00000730 ) + ); + MUXCY \blk00000003/blk000006a1 ( + .CI(\blk00000003/sig0000072c ), + .DI(\blk00000003/sig0000005f ), + .S(\blk00000003/sig0000072d ), + .O(\blk00000003/sig0000072e ) + ); + XORCY \blk00000003/blk000006a0 ( + .CI(\blk00000003/sig0000072a ), + .LI(\blk00000003/sig0000072b ), + .O(\blk00000003/sig00000728 ) + ); + MUXCY \blk00000003/blk0000069f ( + .CI(\blk00000003/sig0000072a ), + .DI(\blk00000003/sig0000005f ), + .S(\blk00000003/sig0000072b ), + .O(\blk00000003/sig0000072c ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000069e ( + .C(clk), + .CE(\blk00000003/sig0000071d ), + .D(\blk00000003/sig00000728 ), + .R(\blk00000003/sig0000005f ), + .Q(\blk00000003/sig00000729 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000069d ( + .C(clk), + .CE(\blk00000003/sig0000071d ), + .D(\blk00000003/sig00000726 ), + .R(\blk00000003/sig0000005f ), + .Q(\blk00000003/sig00000727 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000069c ( + .C(clk), + .CE(\blk00000003/sig0000071d ), + .D(\blk00000003/sig00000724 ), + .R(\blk00000003/sig0000005f ), + .Q(\blk00000003/sig00000725 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000069b ( + .C(clk), + .CE(\blk00000003/sig0000071d ), + .D(\blk00000003/sig00000722 ), + .R(\blk00000003/sig0000005f ), + .Q(\blk00000003/sig00000723 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000069a ( + .C(clk), + .CE(\blk00000003/sig0000071d ), + .D(\blk00000003/sig00000720 ), + .R(\blk00000003/sig0000005f ), + .Q(\blk00000003/sig00000721 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000699 ( + .C(clk), + .CE(\blk00000003/sig0000071d ), + .D(\blk00000003/sig0000071e ), + .R(\blk00000003/sig0000005f ), + .Q(\blk00000003/sig0000071f ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000698 ( + .C(clk), + .CE(\blk00000003/sig00000703 ), + .D(\blk00000003/sig0000071c ), + .Q(\blk00000003/sig000006e8 ) + ); + FD #( + .INIT ( 1'b0 )) + \blk00000003/blk00000697 ( + .C(clk), + .D(\blk00000003/sig0000071b ), + .Q(\blk00000003/sig0000071c ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000696 ( + .C(clk), + .CE(\blk00000003/sig000006ea ), + .D(\blk00000003/sig0000071a ), + .R(\blk00000003/sig0000005f ), + .Q(\blk00000003/sig00000704 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000695 ( + .C(clk), + .CE(\blk00000003/sig000006ea ), + .D(\blk00000003/sig0000070c ), + .R(\blk00000003/sig0000005f ), + .Q(\blk00000003/sig0000071a ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000694 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig00000709 ), + .R(\blk00000003/sig0000005f ), + .Q(\blk00000003/sig00000719 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000693 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig00000705 ), + .R(\blk00000003/sig0000005f ), + .Q(\blk00000003/sig000006ea ) + ); + FDR #( + .INIT ( 1'b0 )) + \blk00000003/blk00000692 ( + .C(clk), + .D(\blk00000003/sig00000717 ), + .R(\blk00000003/sig0000005f ), + .Q(\blk00000003/sig00000718 ) + ); + LUT4 #( + .INIT ( 16'h9009 )) + \blk00000003/blk00000691 ( + .I0(\blk00000003/sig000006ee ), + .I1(\blk00000003/sig0000005f ), + .I2(\blk00000003/sig000006ec ), + .I3(\blk00000003/sig0000005f ), + .O(\blk00000003/sig00000716 ) + ); + LUT4 #( + .INIT ( 16'h9009 )) + \blk00000003/blk00000690 ( + .I0(\blk00000003/sig000006f2 ), + .I1(\blk00000003/sig0000005f ), + .I2(\blk00000003/sig000006f0 ), + .I3(\blk00000003/sig0000005f ), + .O(\blk00000003/sig00000714 ) + ); + LUT4 #( + .INIT ( 16'h9009 )) + \blk00000003/blk0000068f ( + .I0(\blk00000003/sig000006f6 ), + .I1(\blk00000003/sig0000005f ), + .I2(\blk00000003/sig000006f4 ), + .I3(\blk00000003/sig0000005f ), + .O(\blk00000003/sig00000712 ) + ); + MUXCY \blk00000003/blk0000068e ( + .CI(\blk00000003/sig00000715 ), + .DI(\blk00000003/sig0000005f ), + .S(\blk00000003/sig00000716 ), + .O(\blk00000003/sig00000706 ) + ); + MUXCY \blk00000003/blk0000068d ( + .CI(\blk00000003/sig00000713 ), + .DI(\blk00000003/sig0000005f ), + .S(\blk00000003/sig00000714 ), + .O(\blk00000003/sig00000715 ) + ); + MUXCY \blk00000003/blk0000068c ( + .CI(\blk00000003/sig00000065 ), + .DI(\blk00000003/sig0000005f ), + .S(\blk00000003/sig00000712 ), + .O(\blk00000003/sig00000713 ) + ); + LUT4 #( + .INIT ( 16'h9009 )) + \blk00000003/blk0000068b ( + .I0(\blk00000003/sig000006ee ), + .I1(\blk00000003/sig00000065 ), + .I2(\blk00000003/sig000006ec ), + .I3(\blk00000003/sig00000065 ), + .O(\blk00000003/sig00000711 ) + ); + LUT4 #( + .INIT ( 16'h9009 )) + \blk00000003/blk0000068a ( + .I0(\blk00000003/sig000006f2 ), + .I1(\blk00000003/sig00000065 ), + .I2(\blk00000003/sig000006f0 ), + .I3(\blk00000003/sig00000065 ), + .O(\blk00000003/sig0000070f ) + ); + LUT4 #( + .INIT ( 16'h9009 )) + \blk00000003/blk00000689 ( + .I0(\blk00000003/sig000006f6 ), + .I1(\blk00000003/sig00000065 ), + .I2(\blk00000003/sig000006f4 ), + .I3(\blk00000003/sig0000005f ), + .O(\blk00000003/sig0000070d ) + ); + MUXCY \blk00000003/blk00000688 ( + .CI(\blk00000003/sig00000710 ), + .DI(\blk00000003/sig0000005f ), + .S(\blk00000003/sig00000711 ), + .O(\blk00000003/sig0000070b ) + ); + MUXCY \blk00000003/blk00000687 ( + .CI(\blk00000003/sig0000070e ), + .DI(\blk00000003/sig0000005f ), + .S(\blk00000003/sig0000070f ), + .O(\blk00000003/sig00000710 ) + ); + MUXCY \blk00000003/blk00000686 ( + .CI(\blk00000003/sig00000065 ), + .DI(\blk00000003/sig0000005f ), + .S(\blk00000003/sig0000070d ), + .O(\blk00000003/sig0000070e ) + ); + XORCY \blk00000003/blk00000685 ( + .CI(\blk00000003/sig0000070b ), + .LI(\blk00000003/sig0000005f ), + .O(\blk00000003/sig0000070c ) + ); + MUXCY \blk00000003/blk00000684 ( + .CI(\blk00000003/sig00000065 ), + .DI(\blk00000003/sig0000005f ), + .S(\blk00000003/sig0000070a ), + .O(\blk00000003/sig000006f7 ) + ); + XORCY \blk00000003/blk00000683 ( + .CI(\blk00000003/sig00000708 ), + .LI(\blk00000003/sig0000005f ), + .O(\blk00000003/sig00000709 ) + ); + MUXCY \blk00000003/blk00000682 ( + .CI(\blk00000003/sig00000706 ), + .DI(\blk00000003/sig0000005f ), + .S(\blk00000003/sig00000707 ), + .O(\blk00000003/sig00000708 ) + ); + LUT3 #( + .INIT ( 8'hAE )) + \blk00000003/blk00000681 ( + .I0(\blk00000003/sig00000703 ), + .I1(\blk00000003/sig000006ea ), + .I2(\blk00000003/sig00000704 ), + .O(\blk00000003/sig00000705 ) + ); + XORCY \blk00000003/blk00000680 ( + .CI(\blk00000003/sig00000701 ), + .LI(\blk00000003/sig00000702 ), + .O(\blk00000003/sig000006eb ) + ); + XORCY \blk00000003/blk0000067f ( + .CI(\blk00000003/sig000006ff ), + .LI(\blk00000003/sig00000700 ), + .O(\blk00000003/sig000006ed ) + ); + XORCY \blk00000003/blk0000067e ( + .CI(\blk00000003/sig000006fd ), + .LI(\blk00000003/sig000006fe ), + .O(\blk00000003/sig000006ef ) + ); + XORCY \blk00000003/blk0000067d ( + .CI(\blk00000003/sig000006fb ), + .LI(\blk00000003/sig000006fc ), + .O(\blk00000003/sig000006f1 ) + ); + XORCY \blk00000003/blk0000067c ( + .CI(\blk00000003/sig000006f9 ), + .LI(\blk00000003/sig000006fa ), + .O(\blk00000003/sig000006f3 ) + ); + MUXCY \blk00000003/blk0000067b ( + .CI(\blk00000003/sig000006ff ), + .DI(\blk00000003/sig0000005f ), + .S(\blk00000003/sig00000700 ), + .O(\blk00000003/sig00000701 ) + ); + MUXCY \blk00000003/blk0000067a ( + .CI(\blk00000003/sig000006fd ), + .DI(\blk00000003/sig0000005f ), + .S(\blk00000003/sig000006fe ), + .O(\blk00000003/sig000006ff ) + ); + MUXCY \blk00000003/blk00000679 ( + .CI(\blk00000003/sig000006fb ), + .DI(\blk00000003/sig0000005f ), + .S(\blk00000003/sig000006fc ), + .O(\blk00000003/sig000006fd ) + ); + MUXCY \blk00000003/blk00000678 ( + .CI(\blk00000003/sig000006f9 ), + .DI(\blk00000003/sig0000005f ), + .S(\blk00000003/sig000006fa ), + .O(\blk00000003/sig000006fb ) + ); + XORCY \blk00000003/blk00000677 ( + .CI(\blk00000003/sig000006f7 ), + .LI(\blk00000003/sig000006f8 ), + .O(\blk00000003/sig000006f5 ) + ); + MUXCY \blk00000003/blk00000676 ( + .CI(\blk00000003/sig000006f7 ), + .DI(\blk00000003/sig0000005f ), + .S(\blk00000003/sig000006f8 ), + .O(\blk00000003/sig000006f9 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000675 ( + .C(clk), + .CE(\blk00000003/sig000006ea ), + .D(\blk00000003/sig000006f5 ), + .R(\blk00000003/sig0000005f ), + .Q(\blk00000003/sig000006f6 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000674 ( + .C(clk), + .CE(\blk00000003/sig000006ea ), + .D(\blk00000003/sig000006f3 ), + .R(\blk00000003/sig0000005f ), + .Q(\blk00000003/sig000006f4 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000673 ( + .C(clk), + .CE(\blk00000003/sig000006ea ), + .D(\blk00000003/sig000006f1 ), + .R(\blk00000003/sig0000005f ), + .Q(\blk00000003/sig000006f2 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000672 ( + .C(clk), + .CE(\blk00000003/sig000006ea ), + .D(\blk00000003/sig000006ef ), + .R(\blk00000003/sig0000005f ), + .Q(\blk00000003/sig000006f0 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000671 ( + .C(clk), + .CE(\blk00000003/sig000006ea ), + .D(\blk00000003/sig000006ed ), + .R(\blk00000003/sig0000005f ), + .Q(\blk00000003/sig000006ee ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000670 ( + .C(clk), + .CE(\blk00000003/sig000006ea ), + .D(\blk00000003/sig000006eb ), + .R(\blk00000003/sig0000005f ), + .Q(\blk00000003/sig000006ec ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000005e6 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig000006df ), + .R(\blk00000003/sig0000005f ), + .Q(\blk00000003/sig000006b0 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000005e5 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig000006dc ), + .R(\blk00000003/sig0000005f ), + .Q(\blk00000003/sig000006e4 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000005e4 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig000006d9 ), + .R(\blk00000003/sig0000005f ), + .Q(\blk00000003/sig000006e3 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000005e3 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig000006d6 ), + .R(\blk00000003/sig0000005f ), + .Q(\blk00000003/sig000006e2 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000005e2 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig000006d3 ), + .R(\blk00000003/sig0000005f ), + .Q(\blk00000003/sig000006e1 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000005e1 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig000006d0 ), + .R(\blk00000003/sig0000005f ), + .Q(\blk00000003/sig000006e0 ) + ); + LUT4 #( + .INIT ( 16'h00CA )) + \blk00000003/blk000005e0 ( + .I0(\blk00000003/sig0000005f ), + .I1(\blk00000003/sig0000005f ), + .I2(\blk00000003/sig000006b3 ), + .I3(\blk00000003/sig0000005f ), + .O(\blk00000003/sig000006dd ) + ); + LUT4 #( + .INIT ( 16'h00CA )) + \blk00000003/blk000005df ( + .I0(\blk00000003/sig0000005f ), + .I1(\blk00000003/sig000006b4 ), + .I2(\blk00000003/sig000006b3 ), + .I3(\blk00000003/sig0000005f ), + .O(\blk00000003/sig000006da ) + ); + LUT4 #( + .INIT ( 16'h00CA )) + \blk00000003/blk000005de ( + .I0(\blk00000003/sig0000005f ), + .I1(\blk00000003/sig000006b5 ), + .I2(\blk00000003/sig000006b3 ), + .I3(\blk00000003/sig0000005f ), + .O(\blk00000003/sig000006d7 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.O(\blk00000003/sig00000638 ) + ); + XORCY \blk00000003/blk00000546 ( + .CI(\blk00000003/sig00000649 ), + .LI(\blk00000003/sig0000064a ), + .O(\blk00000003/sig00000639 ) + ); + XORCY \blk00000003/blk00000545 ( + .CI(\blk00000003/sig00000647 ), + .LI(\blk00000003/sig00000648 ), + .O(\blk00000003/sig0000063a ) + ); + XORCY \blk00000003/blk00000544 ( + .CI(\blk00000003/sig00000645 ), + .LI(\blk00000003/sig00000646 ), + .O(\blk00000003/sig0000063b ) + ); + XORCY \blk00000003/blk00000543 ( + .CI(\blk00000003/sig00000643 ), + .LI(\blk00000003/sig00000644 ), + .O(\blk00000003/sig0000063c ) + ); + XORCY \blk00000003/blk00000542 ( + .CI(\blk00000003/sig00000641 ), + .LI(\blk00000003/sig00000642 ), + .O(\blk00000003/sig0000063d ) + ); + XORCY \blk00000003/blk00000541 ( + .CI(\blk00000003/sig0000063f ), + .LI(\blk00000003/sig00000640 ), + .O(\blk00000003/sig0000063e ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000540 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig0000063e ), + .Q(\blk00000003/sig000005e5 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000053f ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig0000063d ), + .Q(\blk00000003/sig000005e6 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000053e ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig0000063c ), + .Q(\blk00000003/sig000005e7 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000053d ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig0000063b ), + .Q(\blk00000003/sig000005e8 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000053c ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig0000063a ), + .Q(\blk00000003/sig000005e9 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000053b ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig00000639 ), + .Q(\blk00000003/sig000005ea ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000053a ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig00000638 ), + .Q(\blk00000003/sig000005eb ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000539 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig00000637 ), + .Q(\blk00000003/sig000005ec ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000538 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig00000636 ), + .Q(\blk00000003/sig000005ed ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000537 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig00000635 ), + .Q(\blk00000003/sig000005ee ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000536 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig00000634 ), + .Q(\blk00000003/sig000005ef ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000535 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig00000633 ), + .Q(\blk00000003/sig000005f0 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000534 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig00000632 ), + .Q(\blk00000003/sig000005f1 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000533 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig00000631 ), + .Q(\blk00000003/sig000005f2 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000532 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig00000630 ), + .Q(\blk00000003/sig000005f3 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000531 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig0000062f ), + .Q(\blk00000003/sig000005f4 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000530 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig0000062e ), + .Q(\blk00000003/sig000005f5 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000052f ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig0000062d ), + .Q(\blk00000003/sig000005f6 ) + ); + FD #( + .INIT ( 1'b0 )) + \blk00000003/blk0000047d ( + .C(clk), + .D(\blk00000003/sig00000595 ), + .Q(\blk00000003/sig000005e0 ) + ); + FD #( + .INIT ( 1'b0 )) + \blk00000003/blk0000047c ( + .C(clk), + .D(\blk00000003/sig00000596 ), + .Q(\blk00000003/sig000005df ) + ); + FD #( + .INIT ( 1'b0 )) + \blk00000003/blk0000047b ( + .C(clk), + .D(\blk00000003/sig00000597 ), + .Q(\blk00000003/sig000005de ) + ); + FD #( + .INIT ( 1'b0 )) + \blk00000003/blk0000047a ( + .C(clk), + .D(\blk00000003/sig00000598 ), + .Q(\blk00000003/sig000005dd ) + ); + FD #( + .INIT ( 1'b0 )) + \blk00000003/blk00000479 ( + .C(clk), + .D(\blk00000003/sig00000599 ), + .Q(\blk00000003/sig000005dc ) + ); + FD #( + .INIT ( 1'b0 )) + \blk00000003/blk00000478 ( + .C(clk), + .D(\blk00000003/sig0000059a ), + .Q(\blk00000003/sig000005db ) + ); + FD #( + .INIT ( 1'b0 )) + \blk00000003/blk00000477 ( + .C(clk), + .D(\blk00000003/sig0000059b ), + .Q(\blk00000003/sig000005da ) + ); + FD #( + .INIT ( 1'b0 )) + \blk00000003/blk00000476 ( + .C(clk), + .D(\blk00000003/sig0000059c ), + .Q(\blk00000003/sig000005d9 ) + ); + FD #( + .INIT ( 1'b0 )) + \blk00000003/blk00000475 ( + .C(clk), + .D(\blk00000003/sig0000059d ), + .Q(\blk00000003/sig000005d8 ) + ); + FD #( + .INIT ( 1'b0 )) + \blk00000003/blk00000474 ( + .C(clk), + .D(\blk00000003/sig0000059e ), + .Q(\blk00000003/sig000005d7 ) + ); + FD #( + .INIT ( 1'b0 )) + \blk00000003/blk00000473 ( + .C(clk), + .D(\blk00000003/sig0000059f ), + .Q(\blk00000003/sig000005d6 ) + ); + FD #( + .INIT ( 1'b0 )) + \blk00000003/blk00000472 ( + .C(clk), + .D(\blk00000003/sig000005a0 ), + .Q(\blk00000003/sig000005d5 ) + ); + FD #( + .INIT ( 1'b0 )) + \blk00000003/blk00000471 ( + .C(clk), + .D(\blk00000003/sig000005a1 ), + .Q(\blk00000003/sig000005d4 ) + ); + FD #( + .INIT ( 1'b0 )) + \blk00000003/blk00000470 ( + .C(clk), + .D(\blk00000003/sig000005a2 ), + .Q(\blk00000003/sig000005d3 ) + ); + FD #( + .INIT ( 1'b0 )) + \blk00000003/blk0000046f ( + .C(clk), + .D(\blk00000003/sig000005a3 ), + .Q(\blk00000003/sig000005d2 ) + ); + FD #( + .INIT ( 1'b0 )) + \blk00000003/blk0000046e ( + .C(clk), + .D(\blk00000003/sig000005a4 ), + .Q(\blk00000003/sig000005d1 ) + ); + FD #( + .INIT ( 1'b0 )) + \blk00000003/blk0000046d ( + .C(clk), + .D(\blk00000003/sig000005a5 ), + .Q(\blk00000003/sig000005d0 ) + ); + FD #( + .INIT ( 1'b0 )) + \blk00000003/blk0000046c ( + .C(clk), + .D(\blk00000003/sig000005a6 ), + .Q(\blk00000003/sig000005cf ) + ); + FD #( + .INIT ( 1'b0 )) + \blk00000003/blk0000046b ( + .C(clk), + .D(\blk00000003/sig000005a7 ), + .Q(\blk00000003/sig000005ce ) + ); + FD #( + .INIT ( 1'b0 )) + \blk00000003/blk0000046a ( + .C(clk), + .D(\blk00000003/sig000005a8 ), + .Q(\blk00000003/sig000005cd ) + ); + FD #( + .INIT ( 1'b0 )) + \blk00000003/blk00000469 ( + .C(clk), + .D(\blk00000003/sig000005a9 ), + .Q(\blk00000003/sig000005cc ) + ); + FD #( + .INIT ( 1'b0 )) + \blk00000003/blk00000468 ( + .C(clk), + .D(\blk00000003/sig000005aa ), + .Q(\blk00000003/sig000005cb ) + ); + FD #( + .INIT ( 1'b0 )) + \blk00000003/blk00000467 ( + .C(clk), + .D(\blk00000003/sig000005ab ), + .Q(\blk00000003/sig000005ca ) + ); + FD #( + .INIT ( 1'b0 )) + \blk00000003/blk00000466 ( + .C(clk), + .D(\blk00000003/sig000005ac ), + .Q(\blk00000003/sig000005c9 ) + ); + FD #( + .INIT ( 1'b0 )) + \blk00000003/blk00000465 ( + .C(clk), + .D(\blk00000003/sig000005ad ), + .Q(\blk00000003/sig000005c8 ) + ); + FD #( + .INIT ( 1'b0 )) + \blk00000003/blk00000464 ( + .C(clk), + .D(\blk00000003/sig000005ae ), + .Q(\blk00000003/sig000005c7 ) + ); + FD #( + .INIT ( 1'b0 )) + \blk00000003/blk00000463 ( + .C(clk), + .D(\blk00000003/sig000005af ), + .Q(\blk00000003/sig000005c6 ) + ); + FD #( + .INIT ( 1'b0 )) + \blk00000003/blk00000462 ( + .C(clk), + .D(\blk00000003/sig000005b0 ), + .Q(\blk00000003/sig000005c5 ) + ); + FD #( + .INIT ( 1'b0 )) + \blk00000003/blk00000461 ( + .C(clk), + .D(\blk00000003/sig000005b1 ), + .Q(\blk00000003/sig000005c4 ) + ); + FD #( + .INIT ( 1'b0 )) + \blk00000003/blk00000460 ( + .C(clk), + .D(\blk00000003/sig000005b2 ), + .Q(\blk00000003/sig000005c3 ) + ); + FD #( + .INIT ( 1'b0 )) + \blk00000003/blk0000045f ( + .C(clk), + .D(\blk00000003/sig000005b3 ), + .Q(\blk00000003/sig000005c2 ) + ); + FD #( + .INIT ( 1'b0 )) + \blk00000003/blk0000045e ( + .C(clk), + .D(\blk00000003/sig000005b4 ), + .Q(\blk00000003/sig000005c1 ) + ); + FD #( + .INIT ( 1'b0 )) + \blk00000003/blk0000045d ( + .C(clk), + .D(\blk00000003/sig000005b5 ), + .Q(\blk00000003/sig000005c0 ) + ); + FD #( + .INIT ( 1'b0 )) + \blk00000003/blk0000045c ( + .C(clk), + .D(\blk00000003/sig000005b6 ), + .Q(\blk00000003/sig000005bf ) + ); + FD #( + .INIT ( 1'b0 )) + \blk00000003/blk0000045b ( + .C(clk), + .D(\blk00000003/sig000005b7 ), + .Q(\blk00000003/sig000005be ) + ); + FD #( + .INIT ( 1'b0 )) + \blk00000003/blk0000045a ( + .C(clk), + .D(\blk00000003/sig000005b8 ), + .Q(\blk00000003/sig000005bd ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000459 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig0000016e ), + .Q(\blk00000003/sig000005bc ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000458 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig000005ba ), + .Q(\blk00000003/sig000005bb ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000457 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig000004a7 ), + .Q(\blk00000003/sig000005b9 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000456 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig00000515 ), + .Q(\blk00000003/sig000005b8 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000455 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig00000513 ), + .Q(\blk00000003/sig000005b7 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000454 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig00000510 ), + .Q(\blk00000003/sig000005b6 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000453 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig0000050d ), + .Q(\blk00000003/sig000005b5 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000452 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig0000050a ), + .Q(\blk00000003/sig000005b4 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000451 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig00000507 ), + .Q(\blk00000003/sig000005b3 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000450 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig00000504 ), + .Q(\blk00000003/sig000005b2 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000044f ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig00000501 ), + .Q(\blk00000003/sig000005b1 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000044e ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig000004fe ), + .Q(\blk00000003/sig000005b0 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000044d ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig000004fb ), + .Q(\blk00000003/sig000005af ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000044c ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig000004f8 ), + .Q(\blk00000003/sig000005ae ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000044b ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig000004f5 ), + .Q(\blk00000003/sig000005ad ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000044a ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig000004f2 ), + .Q(\blk00000003/sig000005ac ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000449 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig000004ef ), + .Q(\blk00000003/sig000005ab ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000448 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig000004ec ), + .Q(\blk00000003/sig000005aa ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000447 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig000004e9 ), + .Q(\blk00000003/sig000005a9 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000446 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig000004e6 ), + .Q(\blk00000003/sig000005a8 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000445 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig000004e3 ), + .Q(\blk00000003/sig000005a7 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000444 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig000004de ), + .Q(\blk00000003/sig000005a6 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000443 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig000004dc ), + .Q(\blk00000003/sig000005a5 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000442 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig000004d9 ), + .Q(\blk00000003/sig000005a4 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000441 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig000004d6 ), + .Q(\blk00000003/sig000005a3 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000440 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig000004d3 ), + .Q(\blk00000003/sig000005a2 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000043f ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig000004d0 ), + .Q(\blk00000003/sig000005a1 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000043e ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig000004cd ), + .Q(\blk00000003/sig000005a0 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000043d ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig000004ca ), + .Q(\blk00000003/sig0000059f ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000043c ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig000004c7 ), + .Q(\blk00000003/sig0000059e ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000043b ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig000004c4 ), + .Q(\blk00000003/sig0000059d ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000043a ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig000004c1 ), + .Q(\blk00000003/sig0000059c ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000439 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig000004be ), + .Q(\blk00000003/sig0000059b ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000438 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig000004bb ), + .Q(\blk00000003/sig0000059a ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000437 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig000004b8 ), + .Q(\blk00000003/sig00000599 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000436 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig000004b5 ), + .Q(\blk00000003/sig00000598 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000435 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig000004b2 ), + .Q(\blk00000003/sig00000597 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000434 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig000004af ), + .Q(\blk00000003/sig00000596 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000433 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig000004ac ), + .Q(\blk00000003/sig00000595 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000432 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig00000594 ), + .R(\blk00000003/sig0000005f ), + .Q(\blk00000003/sig0000016f ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000431 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig00000593 ), + .R(\blk00000003/sig0000005f ), + .Q(\blk00000003/sig00000170 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000430 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig00000592 ), + .R(\blk00000003/sig0000005f ), + .Q(\blk00000003/sig00000171 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000042f ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig00000591 ), + .R(\blk00000003/sig0000005f ), + .Q(\blk00000003/sig00000172 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000042e ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig00000590 ), + .R(\blk00000003/sig0000005f ), + .Q(\blk00000003/sig00000173 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000042d ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig0000058f ), + .R(\blk00000003/sig0000005f ), + .Q(\blk00000003/sig00000174 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000042c ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig0000058e ), + .R(\blk00000003/sig0000005f ), + .Q(\blk00000003/sig00000175 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000042b ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig0000058d ), + .R(\blk00000003/sig0000005f ), + .Q(\blk00000003/sig00000176 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000042a ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig0000058c ), + .R(\blk00000003/sig0000005f ), + .Q(\blk00000003/sig00000177 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000429 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig0000058b ), + .R(\blk00000003/sig0000005f ), + .Q(\blk00000003/sig00000178 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000428 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig0000058a ), + .R(\blk00000003/sig0000005f ), + .Q(\blk00000003/sig00000179 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000427 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig00000589 ), + .R(\blk00000003/sig0000005f ), + .Q(\blk00000003/sig0000017a ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000426 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig00000588 ), + .R(\blk00000003/sig0000005f ), + .Q(\blk00000003/sig0000017b ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000425 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig00000587 ), + .R(\blk00000003/sig0000005f ), + .Q(\blk00000003/sig0000017c ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000424 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig00000586 ), + .R(\blk00000003/sig0000005f ), + .Q(\blk00000003/sig0000017d ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000423 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig00000585 ), + .R(\blk00000003/sig0000005f ), + .Q(\blk00000003/sig0000017e ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000422 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig00000584 ), + .R(\blk00000003/sig0000005f ), + .Q(\blk00000003/sig0000017f ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000421 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig00000583 ), + .R(\blk00000003/sig0000005f ), + .Q(\blk00000003/sig00000180 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000420 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig00000581 ), + .R(\blk00000003/sig0000005f ), + .Q(\blk00000003/sig00000582 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000041f ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig0000057f ), + .R(\blk00000003/sig0000005f ), + .Q(\blk00000003/sig00000580 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000041e ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig0000057d ), + .R(\blk00000003/sig0000005f ), + .Q(\blk00000003/sig0000057e ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000041d ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig0000057b ), + .R(\blk00000003/sig0000005f ), + .Q(\blk00000003/sig0000057c ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000041c ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig00000579 ), + .R(\blk00000003/sig0000005f ), + .Q(\blk00000003/sig0000057a ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000041b ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig00000577 ), + .R(\blk00000003/sig0000005f ), + .Q(\blk00000003/sig00000578 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000041a ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig00000575 ), + .R(\blk00000003/sig0000005f ), + .Q(\blk00000003/sig00000576 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000419 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig00000573 ), + .R(\blk00000003/sig0000005f ), + .Q(\blk00000003/sig00000574 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000418 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig00000571 ), + .R(\blk00000003/sig0000005f ), + .Q(\blk00000003/sig00000572 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000417 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig0000056f ), + .R(\blk00000003/sig0000005f ), + .Q(\blk00000003/sig00000570 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000416 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig0000056d ), + .R(\blk00000003/sig0000005f ), + .Q(\blk00000003/sig0000056e ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000415 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig0000056b ), + .R(\blk00000003/sig0000005f ), + .Q(\blk00000003/sig0000056c ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000414 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig00000569 ), + .R(\blk00000003/sig0000005f ), + .Q(\blk00000003/sig0000056a ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000413 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig00000567 ), + .R(\blk00000003/sig0000005f ), + .Q(\blk00000003/sig00000568 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000412 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig00000565 ), + .R(\blk00000003/sig0000005f ), + .Q(\blk00000003/sig00000566 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000411 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig00000563 ), + .R(\blk00000003/sig0000005f ), + .Q(\blk00000003/sig00000564 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000410 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig00000561 ), + .R(\blk00000003/sig0000005f ), + .Q(\blk00000003/sig00000562 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000040f ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig0000055f ), + .R(\blk00000003/sig0000005f ), + .Q(\blk00000003/sig00000560 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000040e ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig0000055d ), + .R(\blk00000003/sig0000005f ), + .Q(\blk00000003/sig0000055e ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000040d ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig0000055b ), + .R(\blk00000003/sig0000005f ), + .Q(\blk00000003/sig0000055c ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000040c ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig00000559 ), + .R(\blk00000003/sig0000005f ), + .Q(\blk00000003/sig0000055a ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000040b ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig00000557 ), + .R(\blk00000003/sig0000005f ), + .Q(\blk00000003/sig00000558 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000040a ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig00000555 ), + .R(\blk00000003/sig0000005f ), + .Q(\blk00000003/sig00000556 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000409 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig00000553 ), + .R(\blk00000003/sig0000005f ), + .Q(\blk00000003/sig00000554 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000408 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig00000551 ), + .R(\blk00000003/sig0000005f ), + .Q(\blk00000003/sig00000552 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000407 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig0000054f ), + .R(\blk00000003/sig0000005f ), + .Q(\blk00000003/sig00000550 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000406 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig0000054d ), + .R(\blk00000003/sig0000005f ), + .Q(\blk00000003/sig0000054e ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000405 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig0000054b ), + .R(\blk00000003/sig0000005f ), + .Q(\blk00000003/sig0000054c ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000404 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig00000549 ), + .R(\blk00000003/sig0000005f ), + .Q(\blk00000003/sig0000054a ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000403 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig00000547 ), + .R(\blk00000003/sig0000005f ), + .Q(\blk00000003/sig00000548 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000402 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig00000545 ), + .R(\blk00000003/sig0000005f ), + .Q(\blk00000003/sig00000546 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000401 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig00000543 ), + .R(\blk00000003/sig0000005f ), + .Q(\blk00000003/sig00000544 ) + ); + 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.Q(\blk00000003/sig0000053a ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003fb ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig00000537 ), + .R(\blk00000003/sig0000005f ), + .Q(\blk00000003/sig00000538 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003fa ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig00000535 ), + .R(\blk00000003/sig0000005f ), + .Q(\blk00000003/sig00000536 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003f9 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig00000533 ), + .R(\blk00000003/sig0000005f ), + .Q(\blk00000003/sig00000534 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003f8 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig00000531 ), + .R(\blk00000003/sig0000005f ), + .Q(\blk00000003/sig00000532 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003f7 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig0000052f ), + .R(\blk00000003/sig0000005f ), + .Q(\blk00000003/sig00000530 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003f6 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig0000052d ), + .R(\blk00000003/sig0000005f ), + .Q(\blk00000003/sig0000052e ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003f5 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig0000052b ), + .R(\blk00000003/sig0000005f ), + .Q(\blk00000003/sig0000052c ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003f4 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig00000529 ), + .R(\blk00000003/sig0000005f ), + .Q(\blk00000003/sig0000052a ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003f3 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig00000527 ), + .R(\blk00000003/sig0000005f ), + .Q(\blk00000003/sig00000528 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000003f2 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + 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.O(\NLW_blk00000003/blk000003e8_O_UNCONNECTED ) + ); + XORCY \blk00000003/blk000003e7 ( + .CI(\blk00000003/sig0000050f ), + .LI(\blk00000003/sig00000511 ), + .O(\blk00000003/sig00000513 ) + ); + MUXCY \blk00000003/blk000003e6 ( + .CI(\blk00000003/sig0000050f ), + .DI(\blk00000003/sig0000005f ), + .S(\blk00000003/sig00000511 ), + .O(\blk00000003/sig00000512 ) + ); + XORCY \blk00000003/blk000003e5 ( + .CI(\blk00000003/sig0000050c ), + .LI(\blk00000003/sig0000050e ), + .O(\blk00000003/sig00000510 ) + ); + MUXCY \blk00000003/blk000003e4 ( + .CI(\blk00000003/sig0000050c ), + .DI(\blk00000003/sig0000005f ), + .S(\blk00000003/sig0000050e ), + .O(\blk00000003/sig0000050f ) + ); + XORCY \blk00000003/blk000003e3 ( + .CI(\blk00000003/sig00000509 ), + .LI(\blk00000003/sig0000050b ), + .O(\blk00000003/sig0000050d ) + ); + MUXCY \blk00000003/blk000003e2 ( + .CI(\blk00000003/sig00000509 ), + .DI(\blk00000003/sig0000005f ), + .S(\blk00000003/sig0000050b ), + .O(\blk00000003/sig0000050c ) + ); + XORCY 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.Q(\blk00000003/sig0000049c ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000037f ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig0000040a ), + .Q(\blk00000003/sig0000049b ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000037e ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig00000407 ), + .Q(\blk00000003/sig0000049a ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000037d ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig00000404 ), + .Q(\blk00000003/sig00000499 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000037c ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig00000401 ), + .Q(\blk00000003/sig00000498 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000037b ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig000003fe ), + .Q(\blk00000003/sig00000497 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000037a ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig000003fb ), + .Q(\blk00000003/sig00000496 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000379 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig000003f8 ), + .Q(\blk00000003/sig00000495 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000378 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig00000425 ), + .Q(\blk00000003/sig00000494 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000377 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig00000481 ), + .Q(\blk00000003/sig00000493 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000376 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig0000047d ), + .Q(\blk00000003/sig00000492 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000375 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig00000468 ), + .Q(\blk00000003/sig00000491 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000374 ( + .C(clk), + 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\blk00000003/blk0000036e ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig00000453 ), + .Q(\blk00000003/sig0000048a ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000036d ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig00000450 ), + .Q(\blk00000003/sig00000489 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000036c ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig0000044d ), + .Q(\blk00000003/sig00000488 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000036b ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig0000044a ), + .Q(\blk00000003/sig00000487 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000036a ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig00000447 ), + .Q(\blk00000003/sig00000486 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000369 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig00000444 ), + .Q(\blk00000003/sig00000485 ) + ); + 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); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002fa ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig00000394 ), + .Q(\blk00000003/sig000003f2 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002f9 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig00000391 ), + .Q(\blk00000003/sig000003f1 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002f8 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig0000038e ), + .Q(\blk00000003/sig000003f0 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002f7 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig0000038b ), + .Q(\blk00000003/sig000003ef ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002f6 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig00000388 ), + .Q(\blk00000003/sig000003ee ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002f5 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig00000385 ), + .Q(\blk00000003/sig000003ed ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002f4 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig00000382 ), + .Q(\blk00000003/sig000003ec ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002f3 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig0000037f ), + .Q(\blk00000003/sig000003eb ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002f2 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig0000037c ), + .Q(\blk00000003/sig000003ea ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002f1 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig00000379 ), + .Q(\blk00000003/sig000003e9 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002f0 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig00000376 ), + .Q(\blk00000003/sig000003e8 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002ef ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig00000373 ), + .Q(\blk00000003/sig000003e7 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002ee ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig00000370 ), + .Q(\blk00000003/sig000003e6 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002ed ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig0000036d ), + .Q(\blk00000003/sig000003e5 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002ec ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig0000036a ), + .Q(\blk00000003/sig000003e4 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002eb ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig000003d1 ), + .Q(\blk00000003/sig000003e3 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002ea ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig000003cf ), + .Q(\blk00000003/sig000003e2 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002e9 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig000003cc ), + .Q(\blk00000003/sig000003e1 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002e8 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig000003c9 ), + .Q(\blk00000003/sig000003e0 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002e7 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig000003c6 ), + .Q(\blk00000003/sig000003df ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002e6 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig000003c3 ), + .Q(\blk00000003/sig000003de ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002e5 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig000003c0 ), + .Q(\blk00000003/sig000003dd ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002e4 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig000003bd ), + .Q(\blk00000003/sig000003dc ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002e3 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig000003ba ), + .Q(\blk00000003/sig000003db ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002e2 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig000003b7 ), + .Q(\blk00000003/sig000003da ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002e1 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig000003b4 ), + .Q(\blk00000003/sig000003d9 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002e0 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig000003b1 ), + .Q(\blk00000003/sig000003d8 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002df ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig000003ae ), + .Q(\blk00000003/sig000003d7 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000002de ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig000003ab ), + .Q(\blk00000003/sig000003d6 ) + ); + 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\blk00000003/blk00000223 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig00000326 ), + .Q(\blk00000003/sig0000033e ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000222 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig00000324 ), + .Q(\blk00000003/sig0000033d ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000221 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig00000322 ), + .Q(\blk00000003/sig0000033c ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000220 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig00000320 ), + .Q(\blk00000003/sig0000033b ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000021f ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig0000031e ), + .Q(\blk00000003/sig0000033a ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000021e ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig0000031c ), + .Q(\blk00000003/sig00000339 ) + ); + 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16'h0000 )) + \blk00000003/blk00000207 ( + .A0(\blk00000003/sig00000065 ), + .A1(\blk00000003/sig00000065 ), + .A2(\blk00000003/sig0000005f ), + .A3(\blk00000003/sig0000005f ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(\blk00000003/sig000000fb ), + .Q(\blk00000003/sig00000311 ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000206 ( + .A0(\blk00000003/sig00000065 ), + .A1(\blk00000003/sig00000065 ), + .A2(\blk00000003/sig0000005f ), + .A3(\blk00000003/sig0000005f ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(\blk00000003/sig000000fc ), + .Q(\blk00000003/sig00000310 ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000205 ( + .A0(\blk00000003/sig00000065 ), + .A1(\blk00000003/sig00000065 ), + .A2(\blk00000003/sig0000005f ), + .A3(\blk00000003/sig0000005f ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(\blk00000003/sig000000fd ), + .Q(\blk00000003/sig0000030f ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000204 ( + .A0(\blk00000003/sig00000065 ), + .A1(\blk00000003/sig00000065 ), + .A2(\blk00000003/sig0000005f ), + .A3(\blk00000003/sig0000005f ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(\blk00000003/sig000000fe ), + .Q(\blk00000003/sig0000030e ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000203 ( + .A0(\blk00000003/sig00000065 ), + .A1(\blk00000003/sig00000065 ), + .A2(\blk00000003/sig0000005f ), + .A3(\blk00000003/sig0000005f ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(\blk00000003/sig000000ff ), + .Q(\blk00000003/sig0000030d ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000202 ( + .A0(\blk00000003/sig00000065 ), + .A1(\blk00000003/sig00000065 ), + .A2(\blk00000003/sig0000005f ), + .A3(\blk00000003/sig0000005f ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(\blk00000003/sig00000100 ), + .Q(\blk00000003/sig0000030c ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000201 ( + .A0(\blk00000003/sig00000065 ), + .A1(\blk00000003/sig00000065 ), + .A2(\blk00000003/sig0000005f ), + .A3(\blk00000003/sig0000005f ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(\blk00000003/sig00000101 ), + .Q(\blk00000003/sig0000030b ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000200 ( + .A0(\blk00000003/sig00000065 ), + .A1(\blk00000003/sig00000065 ), + .A2(\blk00000003/sig0000005f ), + .A3(\blk00000003/sig0000005f ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(\blk00000003/sig00000102 ), + .Q(\blk00000003/sig0000030a ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001ff ( + .A0(\blk00000003/sig00000065 ), + .A1(\blk00000003/sig00000065 ), + .A2(\blk00000003/sig0000005f ), + .A3(\blk00000003/sig0000005f ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(\blk00000003/sig00000103 ), + .Q(\blk00000003/sig00000309 ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001fe ( + .A0(\blk00000003/sig00000065 ), + .A1(\blk00000003/sig00000065 ), + .A2(\blk00000003/sig0000005f ), + .A3(\blk00000003/sig0000005f ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(\blk00000003/sig00000104 ), + .Q(\blk00000003/sig00000308 ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001fd ( + .A0(\blk00000003/sig00000065 ), + .A1(\blk00000003/sig00000065 ), + .A2(\blk00000003/sig0000005f ), + .A3(\blk00000003/sig0000005f ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(\blk00000003/sig00000105 ), + .Q(\blk00000003/sig00000307 ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001fc ( + .A0(\blk00000003/sig00000065 ), + .A1(\blk00000003/sig00000065 ), + .A2(\blk00000003/sig0000005f ), + .A3(\blk00000003/sig0000005f ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(\blk00000003/sig00000106 ), + .Q(\blk00000003/sig00000306 ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001fb ( + .A0(\blk00000003/sig00000065 ), + .A1(\blk00000003/sig00000065 ), + .A2(\blk00000003/sig0000005f ), + .A3(\blk00000003/sig0000005f ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(\blk00000003/sig00000107 ), + .Q(\blk00000003/sig00000305 ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001fa ( + .A0(\blk00000003/sig00000065 ), + .A1(\blk00000003/sig00000065 ), + .A2(\blk00000003/sig0000005f ), + .A3(\blk00000003/sig0000005f ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(\blk00000003/sig00000108 ), + .Q(\blk00000003/sig00000304 ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001f9 ( + .A0(\blk00000003/sig00000065 ), + .A1(\blk00000003/sig00000065 ), + .A2(\blk00000003/sig0000005f ), + .A3(\blk00000003/sig0000005f ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(\blk00000003/sig00000109 ), + .Q(\blk00000003/sig00000303 ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001f8 ( + .A0(\blk00000003/sig00000065 ), + .A1(\blk00000003/sig00000065 ), + .A2(\blk00000003/sig0000005f ), + .A3(\blk00000003/sig0000005f ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(\blk00000003/sig0000010a ), + .Q(\blk00000003/sig00000302 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001f7 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig000002f0 ), + .Q(\blk00000003/sig00000301 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001f6 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig000002ee ), + .Q(\blk00000003/sig00000300 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001f5 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig000002ec ), + .Q(\blk00000003/sig000002ff ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001f4 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig000002ea ), + .Q(\blk00000003/sig000002fe ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001f3 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig000002e8 ), + .Q(\blk00000003/sig000002fd ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001f2 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig000002e6 ), + .Q(\blk00000003/sig000002fc ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001f1 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig000002e4 ), + .Q(\blk00000003/sig000002fb ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001f0 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig000002e2 ), + .Q(\blk00000003/sig000002fa ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001ef ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig000002e0 ), + .Q(\blk00000003/sig000002f9 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001ee ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig000002de ), + .Q(\blk00000003/sig000002f8 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001ed ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig000002dc ), + .Q(\blk00000003/sig000002f7 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001ec ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig000002da ), + .Q(\blk00000003/sig000002f6 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001eb ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig000002d8 ), + .Q(\blk00000003/sig000002f5 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001ea ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig000002d6 ), + .Q(\blk00000003/sig000002f4 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001e9 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig000002d4 ), + .Q(\blk00000003/sig000002f3 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001e8 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig000002d2 ), + .Q(\blk00000003/sig000002f2 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001e7 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig000002d0 ), + .Q(\blk00000003/sig000002f1 ) + ); + MUXF5 \blk00000003/blk000001e6 ( + .I0(\blk00000003/sig000002ce ), + .I1(\blk00000003/sig000002ef ), + .S(\blk00000003/sig000002bd ), + .O(\blk00000003/sig000002f0 ) + ); + MUXF5 \blk00000003/blk000001e5 ( + .I0(\blk00000003/sig000002cd ), + .I1(\blk00000003/sig000002ed ), + .S(\blk00000003/sig000002bd ), + .O(\blk00000003/sig000002ee ) + ); + MUXF5 \blk00000003/blk000001e4 ( + .I0(\blk00000003/sig000002cc ), + .I1(\blk00000003/sig000002eb ), + .S(\blk00000003/sig000002bd ), + .O(\blk00000003/sig000002ec ) + ); + MUXF5 \blk00000003/blk000001e3 ( + .I0(\blk00000003/sig000002cb ), + .I1(\blk00000003/sig000002e9 ), + .S(\blk00000003/sig000002bd ), + .O(\blk00000003/sig000002ea ) + ); + MUXF5 \blk00000003/blk000001e2 ( + .I0(\blk00000003/sig000002ca ), + .I1(\blk00000003/sig000002e7 ), + .S(\blk00000003/sig000002bd ), + .O(\blk00000003/sig000002e8 ) + ); + MUXF5 \blk00000003/blk000001e1 ( + .I0(\blk00000003/sig000002c9 ), + .I1(\blk00000003/sig000002e5 ), + .S(\blk00000003/sig000002bd ), + .O(\blk00000003/sig000002e6 ) + ); + MUXF5 \blk00000003/blk000001e0 ( + .I0(\blk00000003/sig000002c8 ), + .I1(\blk00000003/sig000002e3 ), + .S(\blk00000003/sig000002bd ), + .O(\blk00000003/sig000002e4 ) + ); + MUXF5 \blk00000003/blk000001df ( + .I0(\blk00000003/sig000002c7 ), + .I1(\blk00000003/sig000002e1 ), + .S(\blk00000003/sig000002bd ), + .O(\blk00000003/sig000002e2 ) + ); + MUXF5 \blk00000003/blk000001de ( + .I0(\blk00000003/sig000002c6 ), + .I1(\blk00000003/sig000002df ), + .S(\blk00000003/sig000002bd ), + .O(\blk00000003/sig000002e0 ) + ); + MUXF5 \blk00000003/blk000001dd ( + .I0(\blk00000003/sig000002c5 ), + .I1(\blk00000003/sig000002dd ), + .S(\blk00000003/sig000002bd ), + .O(\blk00000003/sig000002de ) + ); + MUXF5 \blk00000003/blk000001dc ( + .I0(\blk00000003/sig000002c4 ), + .I1(\blk00000003/sig000002db ), + .S(\blk00000003/sig000002bd ), + .O(\blk00000003/sig000002dc ) + ); + MUXF5 \blk00000003/blk000001db ( + .I0(\blk00000003/sig000002c3 ), + .I1(\blk00000003/sig000002d9 ), + .S(\blk00000003/sig000002bd ), + .O(\blk00000003/sig000002da ) + ); + MUXF5 \blk00000003/blk000001da ( + .I0(\blk00000003/sig000002c2 ), + .I1(\blk00000003/sig000002d7 ), + .S(\blk00000003/sig000002bd ), + .O(\blk00000003/sig000002d8 ) + ); + MUXF5 \blk00000003/blk000001d9 ( + .I0(\blk00000003/sig000002c1 ), + .I1(\blk00000003/sig000002d5 ), + .S(\blk00000003/sig000002bd ), + .O(\blk00000003/sig000002d6 ) + ); + MUXF5 \blk00000003/blk000001d8 ( + .I0(\blk00000003/sig000002c0 ), + .I1(\blk00000003/sig000002d3 ), + .S(\blk00000003/sig000002bd ), + .O(\blk00000003/sig000002d4 ) + ); + MUXF5 \blk00000003/blk000001d7 ( + .I0(\blk00000003/sig000002bf ), + .I1(\blk00000003/sig000002d1 ), + .S(\blk00000003/sig000002bd ), + .O(\blk00000003/sig000002d2 ) + ); + MUXF5 \blk00000003/blk000001d6 ( + .I0(\blk00000003/sig000002be ), + .I1(\blk00000003/sig000002cf ), + .S(\blk00000003/sig000002bd ), + .O(\blk00000003/sig000002d0 ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001d5 ( + .A0(\blk00000003/sig00000065 ), + .A1(\blk00000003/sig00000065 ), + .A2(\blk00000003/sig0000005f ), + .A3(\blk00000003/sig0000005f ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(\blk00000003/sig0000010b ), + .Q(\blk00000003/sig000002ce ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001d4 ( + .A0(\blk00000003/sig00000065 ), + .A1(\blk00000003/sig00000065 ), + .A2(\blk00000003/sig0000005f ), + .A3(\blk00000003/sig0000005f ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(\blk00000003/sig0000010b ), + .Q(\blk00000003/sig000002cd ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001d3 ( + .A0(\blk00000003/sig00000065 ), + .A1(\blk00000003/sig00000065 ), + .A2(\blk00000003/sig0000005f ), + .A3(\blk00000003/sig0000005f ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(\blk00000003/sig0000010c ), + .Q(\blk00000003/sig000002cc ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001d2 ( + .A0(\blk00000003/sig00000065 ), + .A1(\blk00000003/sig00000065 ), + .A2(\blk00000003/sig0000005f ), + .A3(\blk00000003/sig0000005f ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(\blk00000003/sig0000010d ), + .Q(\blk00000003/sig000002cb ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001d1 ( + .A0(\blk00000003/sig00000065 ), + .A1(\blk00000003/sig00000065 ), + .A2(\blk00000003/sig0000005f ), + .A3(\blk00000003/sig0000005f ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(\blk00000003/sig0000010e ), + .Q(\blk00000003/sig000002ca ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001d0 ( + .A0(\blk00000003/sig00000065 ), + .A1(\blk00000003/sig00000065 ), + .A2(\blk00000003/sig0000005f ), + .A3(\blk00000003/sig0000005f ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(\blk00000003/sig0000010f ), + .Q(\blk00000003/sig000002c9 ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001cf ( + .A0(\blk00000003/sig00000065 ), + .A1(\blk00000003/sig00000065 ), + .A2(\blk00000003/sig0000005f ), + .A3(\blk00000003/sig0000005f ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(\blk00000003/sig00000110 ), + .Q(\blk00000003/sig000002c8 ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001ce ( + .A0(\blk00000003/sig00000065 ), + .A1(\blk00000003/sig00000065 ), + .A2(\blk00000003/sig0000005f ), + .A3(\blk00000003/sig0000005f ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(\blk00000003/sig00000111 ), + .Q(\blk00000003/sig000002c7 ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001cd ( + .A0(\blk00000003/sig00000065 ), + .A1(\blk00000003/sig00000065 ), + .A2(\blk00000003/sig0000005f ), + .A3(\blk00000003/sig0000005f ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(\blk00000003/sig00000112 ), + .Q(\blk00000003/sig000002c6 ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001cc ( + .A0(\blk00000003/sig00000065 ), + .A1(\blk00000003/sig00000065 ), + .A2(\blk00000003/sig0000005f ), + .A3(\blk00000003/sig0000005f ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(\blk00000003/sig00000113 ), + .Q(\blk00000003/sig000002c5 ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001cb ( + .A0(\blk00000003/sig00000065 ), + .A1(\blk00000003/sig00000065 ), + .A2(\blk00000003/sig0000005f ), + .A3(\blk00000003/sig0000005f ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(\blk00000003/sig00000114 ), + .Q(\blk00000003/sig000002c4 ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001ca ( + .A0(\blk00000003/sig00000065 ), + .A1(\blk00000003/sig00000065 ), + .A2(\blk00000003/sig0000005f ), + .A3(\blk00000003/sig0000005f ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(\blk00000003/sig00000115 ), + .Q(\blk00000003/sig000002c3 ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001c9 ( + .A0(\blk00000003/sig00000065 ), + .A1(\blk00000003/sig00000065 ), + .A2(\blk00000003/sig0000005f ), + .A3(\blk00000003/sig0000005f ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(\blk00000003/sig00000116 ), + .Q(\blk00000003/sig000002c2 ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001c8 ( + .A0(\blk00000003/sig00000065 ), + .A1(\blk00000003/sig00000065 ), + .A2(\blk00000003/sig0000005f ), + .A3(\blk00000003/sig0000005f ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(\blk00000003/sig00000117 ), + .Q(\blk00000003/sig000002c1 ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001c7 ( + .A0(\blk00000003/sig00000065 ), + .A1(\blk00000003/sig00000065 ), + .A2(\blk00000003/sig0000005f ), + .A3(\blk00000003/sig0000005f ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(\blk00000003/sig00000118 ), + .Q(\blk00000003/sig000002c0 ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001c6 ( + .A0(\blk00000003/sig00000065 ), + .A1(\blk00000003/sig00000065 ), + .A2(\blk00000003/sig0000005f ), + .A3(\blk00000003/sig0000005f ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(\blk00000003/sig00000119 ), + .Q(\blk00000003/sig000002bf ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001c5 ( + .A0(\blk00000003/sig00000065 ), + .A1(\blk00000003/sig00000065 ), + .A2(\blk00000003/sig0000005f ), + .A3(\blk00000003/sig0000005f ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(\blk00000003/sig0000011a ), + .Q(\blk00000003/sig000002be ) + ); + FD #( + .INIT ( 1'b0 )) + \blk00000003/blk000001c4 ( + .C(clk), + .D(\blk00000003/sig0000029c ), + .Q(\blk00000003/sig000002bd ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000178 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig00000299 ), + .R(\blk00000003/sig0000005f ), + .Q(\blk00000003/sig0000026e ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000177 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig00000296 ), + .R(\blk00000003/sig0000005f ), + .Q(\blk00000003/sig0000029b ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000176 ( + .C(clk), + .CE(\blk00000003/sig0000026e ), + .D(\blk00000003/sig00000293 ), + .R(\blk00000003/sig0000005f ), + .Q(\blk00000003/sig0000029a ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000175 ( + .C(clk), + .CE(\blk00000003/sig0000026e ), + .D(\blk00000003/sig0000029a ), + .R(\blk00000003/sig0000005f ), + .Q(\blk00000003/sig00000298 ) + ); + LUT3 #( + .INIT ( 8'hAE )) + \blk00000003/blk00000174 ( + .I0(\blk00000003/sig00000245 ), + .I1(\blk00000003/sig0000026e ), + .I2(\blk00000003/sig00000298 ), + .O(\blk00000003/sig00000299 ) + ); + MUXCY \blk00000003/blk00000173 ( + .CI(\blk00000003/sig0000028b ), + .DI(\blk00000003/sig0000005f ), + .S(\blk00000003/sig00000297 ), + .O(\blk00000003/sig00000295 ) + ); + XORCY \blk00000003/blk00000172 ( + .CI(\blk00000003/sig00000295 ), + .LI(\blk00000003/sig0000005f ), + .O(\blk00000003/sig00000296 ) + ); + MUXCY \blk00000003/blk00000171 ( + .CI(\blk00000003/sig00000065 ), + .DI(\blk00000003/sig0000005f ), + .S(\blk00000003/sig00000294 ), + .O(\blk00000003/sig0000027b ) + ); + XORCY \blk00000003/blk00000170 ( + .CI(\blk00000003/sig00000291 ), + .LI(\blk00000003/sig0000005f ), + .O(\blk00000003/sig00000293 ) + ); + MUXCY \blk00000003/blk0000016f ( + .CI(\blk00000003/sig00000065 ), + .DI(\blk00000003/sig0000005f ), + .S(\blk00000003/sig0000028f ), + .O(\blk00000003/sig00000292 ) + ); + MUXCY \blk00000003/blk0000016e ( + .CI(\blk00000003/sig00000292 ), + .DI(\blk00000003/sig0000005f ), + .S(\blk00000003/sig0000028e ), + .O(\blk00000003/sig00000290 ) + ); + MUXCY \blk00000003/blk0000016d ( + .CI(\blk00000003/sig00000290 ), + .DI(\blk00000003/sig0000005f ), + .S(\blk00000003/sig0000028d ), + .O(\blk00000003/sig00000291 ) + ); + LUT4 #( + .INIT ( 16'h9009 )) + \blk00000003/blk0000016c ( + .I0(\blk00000003/sig0000027a ), + .I1(\blk00000003/sig00000065 ), + .I2(\blk00000003/sig00000278 ), + .I3(\blk00000003/sig0000005f ), + .O(\blk00000003/sig0000028f ) + ); + LUT4 #( + .INIT ( 16'h9009 )) + \blk00000003/blk0000016b ( + .I0(\blk00000003/sig00000276 ), + .I1(\blk00000003/sig00000065 ), + .I2(\blk00000003/sig00000274 ), + .I3(\blk00000003/sig00000065 ), + .O(\blk00000003/sig0000028e ) + ); + LUT4 #( + .INIT ( 16'h9009 )) + \blk00000003/blk0000016a ( + .I0(\blk00000003/sig00000272 ), + .I1(\blk00000003/sig00000065 ), + .I2(\blk00000003/sig00000270 ), + .I3(\blk00000003/sig00000065 ), + .O(\blk00000003/sig0000028d ) + ); + MUXCY \blk00000003/blk00000169 ( + .CI(\blk00000003/sig00000065 ), + .DI(\blk00000003/sig0000005f ), + .S(\blk00000003/sig00000289 ), + .O(\blk00000003/sig0000028c ) + ); + MUXCY \blk00000003/blk00000168 ( + .CI(\blk00000003/sig0000028c ), + .DI(\blk00000003/sig0000005f ), + .S(\blk00000003/sig00000288 ), + .O(\blk00000003/sig0000028a ) + ); + MUXCY \blk00000003/blk00000167 ( + .CI(\blk00000003/sig0000028a ), + .DI(\blk00000003/sig0000005f ), + .S(\blk00000003/sig00000287 ), + .O(\blk00000003/sig0000028b ) + ); + LUT4 #( + .INIT ( 16'h9009 )) + \blk00000003/blk00000166 ( + .I0(\blk00000003/sig0000027a ), + .I1(\blk00000003/sig0000005f ), + .I2(\blk00000003/sig00000278 ), + .I3(\blk00000003/sig00000065 ), + .O(\blk00000003/sig00000289 ) + ); + LUT4 #( + .INIT ( 16'h9009 )) + \blk00000003/blk00000165 ( + .I0(\blk00000003/sig00000276 ), + .I1(\blk00000003/sig00000065 ), + .I2(\blk00000003/sig00000274 ), + .I3(\blk00000003/sig0000005f ), + .O(\blk00000003/sig00000288 ) + ); + LUT4 #( + .INIT ( 16'h9009 )) + \blk00000003/blk00000164 ( + .I0(\blk00000003/sig00000272 ), + .I1(\blk00000003/sig0000005f ), + .I2(\blk00000003/sig00000270 ), + .I3(\blk00000003/sig0000005f ), + .O(\blk00000003/sig00000287 ) + ); + XORCY \blk00000003/blk00000163 ( + .CI(\blk00000003/sig00000285 ), + .LI(\blk00000003/sig00000286 ), + .O(\blk00000003/sig0000026f ) + ); + XORCY \blk00000003/blk00000162 ( + .CI(\blk00000003/sig00000283 ), + .LI(\blk00000003/sig00000284 ), + .O(\blk00000003/sig00000271 ) + ); + XORCY \blk00000003/blk00000161 ( + .CI(\blk00000003/sig00000281 ), + .LI(\blk00000003/sig00000282 ), + .O(\blk00000003/sig00000273 ) + ); + XORCY \blk00000003/blk00000160 ( + .CI(\blk00000003/sig0000027f ), + .LI(\blk00000003/sig00000280 ), + .O(\blk00000003/sig00000275 ) + ); + XORCY \blk00000003/blk0000015f ( + .CI(\blk00000003/sig0000027d ), + .LI(\blk00000003/sig0000027e ), + .O(\blk00000003/sig00000277 ) + ); + MUXCY \blk00000003/blk0000015e ( + .CI(\blk00000003/sig00000283 ), + .DI(\blk00000003/sig0000005f ), + .S(\blk00000003/sig00000284 ), + .O(\blk00000003/sig00000285 ) + ); + MUXCY \blk00000003/blk0000015d ( + .CI(\blk00000003/sig00000281 ), + .DI(\blk00000003/sig0000005f ), + .S(\blk00000003/sig00000282 ), + .O(\blk00000003/sig00000283 ) + ); + MUXCY \blk00000003/blk0000015c ( + .CI(\blk00000003/sig0000027f ), + .DI(\blk00000003/sig0000005f ), + .S(\blk00000003/sig00000280 ), + .O(\blk00000003/sig00000281 ) + ); + MUXCY \blk00000003/blk0000015b ( + .CI(\blk00000003/sig0000027d ), + .DI(\blk00000003/sig0000005f ), + .S(\blk00000003/sig0000027e ), + .O(\blk00000003/sig0000027f ) + ); + XORCY \blk00000003/blk0000015a ( + .CI(\blk00000003/sig0000027b ), + .LI(\blk00000003/sig0000027c ), + .O(\blk00000003/sig00000279 ) + ); + MUXCY \blk00000003/blk00000159 ( + .CI(\blk00000003/sig0000027b ), + .DI(\blk00000003/sig0000005f ), + .S(\blk00000003/sig0000027c ), + .O(\blk00000003/sig0000027d ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000158 ( + .C(clk), + .CE(\blk00000003/sig0000026e ), + .D(\blk00000003/sig00000279 ), + .R(\blk00000003/sig0000005f ), + .Q(\blk00000003/sig0000027a ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000157 ( + .C(clk), + .CE(\blk00000003/sig0000026e ), + .D(\blk00000003/sig00000277 ), + .R(\blk00000003/sig0000005f ), + .Q(\blk00000003/sig00000278 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000156 ( + .C(clk), + .CE(\blk00000003/sig0000026e ), + .D(\blk00000003/sig00000275 ), + .R(\blk00000003/sig0000005f ), + .Q(\blk00000003/sig00000276 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000155 ( + .C(clk), + .CE(\blk00000003/sig0000026e ), + .D(\blk00000003/sig00000273 ), + .R(\blk00000003/sig0000005f ), + .Q(\blk00000003/sig00000274 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000154 ( + .C(clk), + .CE(\blk00000003/sig0000026e ), + .D(\blk00000003/sig00000271 ), + .R(\blk00000003/sig0000005f ), + .Q(\blk00000003/sig00000272 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000153 ( + .C(clk), + .CE(\blk00000003/sig0000026e ), + .D(\blk00000003/sig0000026f ), + .R(\blk00000003/sig0000005f ), + .Q(\blk00000003/sig00000270 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000152 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig0000026c ), + .R(\blk00000003/sig0000005f ), + .Q(\blk00000003/sig00000247 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000151 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig00000269 ), + .R(\blk00000003/sig0000005f ), + .Q(\blk00000003/sig00000245 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000150 ( + .C(clk), + .CE(\blk00000003/sig00000247 ), + .D(\blk00000003/sig00000266 ), + .R(\blk00000003/sig0000005f ), + .Q(\blk00000003/sig0000026d ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000014f ( + .C(clk), + .CE(\blk00000003/sig00000247 ), + .D(\blk00000003/sig0000026d ), + .R(\blk00000003/sig0000005f ), + .Q(\blk00000003/sig0000026b ) + ); + LUT3 #( + .INIT ( 8'hAE )) + \blk00000003/blk0000014e ( + .I0(\blk00000003/sig000000a7 ), + .I1(\blk00000003/sig00000247 ), + .I2(\blk00000003/sig0000026b ), + .O(\blk00000003/sig0000026c ) + ); + MUXCY \blk00000003/blk0000014d ( + .CI(\blk00000003/sig0000025e ), + .DI(\blk00000003/sig0000005f ), + .S(\blk00000003/sig0000026a ), + .O(\blk00000003/sig00000268 ) + ); + XORCY \blk00000003/blk0000014c ( + .CI(\blk00000003/sig00000268 ), + .LI(\blk00000003/sig0000005f ), + .O(\blk00000003/sig00000269 ) + ); + MUXCY \blk00000003/blk0000014b ( + .CI(\blk00000003/sig00000065 ), + .DI(\blk00000003/sig0000005f ), + .S(\blk00000003/sig00000267 ), + .O(\blk00000003/sig0000024e ) + ); + XORCY \blk00000003/blk0000014a ( + .CI(\blk00000003/sig00000264 ), + .LI(\blk00000003/sig0000005f ), + .O(\blk00000003/sig00000266 ) + ); + MUXCY \blk00000003/blk00000149 ( + .CI(\blk00000003/sig00000065 ), + .DI(\blk00000003/sig0000005f ), + .S(\blk00000003/sig00000262 ), + .O(\blk00000003/sig00000265 ) + ); + MUXCY \blk00000003/blk00000148 ( + .CI(\blk00000003/sig00000265 ), + .DI(\blk00000003/sig0000005f ), + .S(\blk00000003/sig00000261 ), + .O(\blk00000003/sig00000263 ) + ); + MUXCY \blk00000003/blk00000147 ( + .CI(\blk00000003/sig00000263 ), + .DI(\blk00000003/sig0000005f ), + .S(\blk00000003/sig00000260 ), + .O(\blk00000003/sig00000264 ) + ); + LUT4 #( + .INIT ( 16'h9009 )) + \blk00000003/blk00000146 ( + .I0(\blk00000003/sig0000016c ), + .I1(\blk00000003/sig00000065 ), + .I2(\blk00000003/sig0000016b ), + .I3(\blk00000003/sig0000005f ), + .O(\blk00000003/sig00000262 ) + ); + LUT4 #( + .INIT ( 16'h9009 )) + \blk00000003/blk00000145 ( + .I0(\blk00000003/sig0000016a ), + .I1(\blk00000003/sig00000065 ), + .I2(\blk00000003/sig00000169 ), + .I3(\blk00000003/sig00000065 ), + .O(\blk00000003/sig00000261 ) + ); + LUT4 #( + .INIT ( 16'h9009 )) + \blk00000003/blk00000144 ( + .I0(\blk00000003/sig00000168 ), + .I1(\blk00000003/sig00000065 ), + .I2(\blk00000003/sig00000167 ), + .I3(\blk00000003/sig00000065 ), + .O(\blk00000003/sig00000260 ) + ); + MUXCY \blk00000003/blk00000143 ( + .CI(\blk00000003/sig00000065 ), + .DI(\blk00000003/sig0000005f ), + .S(\blk00000003/sig0000025c ), + .O(\blk00000003/sig0000025f ) + ); + MUXCY \blk00000003/blk00000142 ( + .CI(\blk00000003/sig0000025f ), + .DI(\blk00000003/sig0000005f ), + .S(\blk00000003/sig0000025b ), + .O(\blk00000003/sig0000025d ) + ); + MUXCY \blk00000003/blk00000141 ( + .CI(\blk00000003/sig0000025d ), + .DI(\blk00000003/sig0000005f ), + .S(\blk00000003/sig0000025a ), + .O(\blk00000003/sig0000025e ) + ); + LUT4 #( + .INIT ( 16'h9009 )) + \blk00000003/blk00000140 ( + .I0(\blk00000003/sig0000016c ), + .I1(\blk00000003/sig0000005f ), + .I2(\blk00000003/sig0000016b ), + .I3(\blk00000003/sig00000065 ), + .O(\blk00000003/sig0000025c ) + ); + LUT4 #( + .INIT ( 16'h9009 )) + \blk00000003/blk0000013f ( + .I0(\blk00000003/sig0000016a ), + .I1(\blk00000003/sig00000065 ), + .I2(\blk00000003/sig00000169 ), + .I3(\blk00000003/sig00000065 ), + .O(\blk00000003/sig0000025b ) + ); + LUT4 #( + .INIT ( 16'h9009 )) + \blk00000003/blk0000013e ( + .I0(\blk00000003/sig00000168 ), + .I1(\blk00000003/sig0000005f ), + .I2(\blk00000003/sig00000167 ), + .I3(\blk00000003/sig0000005f ), + .O(\blk00000003/sig0000025a ) + ); + XORCY \blk00000003/blk0000013d ( + .CI(\blk00000003/sig00000258 ), + .LI(\blk00000003/sig00000259 ), + .O(\blk00000003/sig00000248 ) + ); + XORCY \blk00000003/blk0000013c ( + .CI(\blk00000003/sig00000256 ), + .LI(\blk00000003/sig00000257 ), + .O(\blk00000003/sig00000249 ) + ); + XORCY \blk00000003/blk0000013b ( + .CI(\blk00000003/sig00000254 ), + .LI(\blk00000003/sig00000255 ), + .O(\blk00000003/sig0000024a ) + ); + XORCY \blk00000003/blk0000013a ( + .CI(\blk00000003/sig00000252 ), + .LI(\blk00000003/sig00000253 ), + .O(\blk00000003/sig0000024b ) + ); + XORCY \blk00000003/blk00000139 ( + .CI(\blk00000003/sig00000250 ), + .LI(\blk00000003/sig00000251 ), + .O(\blk00000003/sig0000024c ) + ); + MUXCY \blk00000003/blk00000138 ( + .CI(\blk00000003/sig00000256 ), + .DI(\blk00000003/sig0000005f ), + .S(\blk00000003/sig00000257 ), + .O(\blk00000003/sig00000258 ) + ); + MUXCY \blk00000003/blk00000137 ( + .CI(\blk00000003/sig00000254 ), + .DI(\blk00000003/sig0000005f ), + .S(\blk00000003/sig00000255 ), + .O(\blk00000003/sig00000256 ) + ); + MUXCY \blk00000003/blk00000136 ( + .CI(\blk00000003/sig00000252 ), + .DI(\blk00000003/sig0000005f ), + .S(\blk00000003/sig00000253 ), + .O(\blk00000003/sig00000254 ) + ); + MUXCY \blk00000003/blk00000135 ( + .CI(\blk00000003/sig00000250 ), + .DI(\blk00000003/sig0000005f ), + .S(\blk00000003/sig00000251 ), + .O(\blk00000003/sig00000252 ) + ); + XORCY \blk00000003/blk00000134 ( + .CI(\blk00000003/sig0000024e ), + .LI(\blk00000003/sig0000024f ), + .O(\blk00000003/sig0000024d ) + ); + MUXCY \blk00000003/blk00000133 ( + .CI(\blk00000003/sig0000024e ), + .DI(\blk00000003/sig0000005f ), + .S(\blk00000003/sig0000024f ), + .O(\blk00000003/sig00000250 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000132 ( + .C(clk), + .CE(\blk00000003/sig00000247 ), + .D(\blk00000003/sig0000024d ), + .R(\blk00000003/sig0000005f ), + .Q(\blk00000003/sig0000016c ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000131 ( + .C(clk), + .CE(\blk00000003/sig00000247 ), + .D(\blk00000003/sig0000024c ), + .R(\blk00000003/sig0000005f ), + .Q(\blk00000003/sig0000016b ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000130 ( + .C(clk), + .CE(\blk00000003/sig00000247 ), + .D(\blk00000003/sig0000024b ), + .R(\blk00000003/sig0000005f ), + .Q(\blk00000003/sig0000016a ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000012f ( + .C(clk), + .CE(\blk00000003/sig00000247 ), + .D(\blk00000003/sig0000024a ), + .R(\blk00000003/sig0000005f ), + .Q(\blk00000003/sig00000169 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000012e ( + .C(clk), + .CE(\blk00000003/sig00000247 ), + .D(\blk00000003/sig00000249 ), + .R(\blk00000003/sig0000005f ), + .Q(\blk00000003/sig00000168 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000012d ( + .C(clk), + .CE(\blk00000003/sig00000247 ), + .D(\blk00000003/sig00000248 ), + .R(\blk00000003/sig0000005f ), + .Q(\blk00000003/sig00000167 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000012c ( + .C(clk), + .CE(\blk00000003/sig00000245 ), + .D(\blk00000003/sig00000244 ), + .Q(\blk00000003/sig00000246 ) + ); + FD #( + .INIT ( 1'b0 )) + \blk00000003/blk0000012b ( + .C(clk), + .D(\blk00000003/sig00000243 ), + .Q(\blk00000003/sig00000244 ) + ); + FDR #( + .INIT ( 1'b0 )) + \blk00000003/blk0000012a ( + .C(clk), + .D(\blk00000003/sig00000241 ), + .R(\blk00000003/sig0000005f ), + .Q(\blk00000003/sig00000242 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000129 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig00000240 ), + .Q(\blk00000003/sig000001f9 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000128 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig0000023f ), + .Q(\blk00000003/sig00000240 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000127 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig0000023e ), + .Q(\blk00000003/sig00000192 ) + ); + DSP48A #( + .A0REG ( 1 ), + .A1REG ( 1 ), + .B0REG ( 1 ), + .B1REG ( 1 ), + .CARRYINREG ( 0 ), + .CARRYINSEL ( "OPMODE5" ), + .CREG ( 0 ), + .DREG ( 0 ), + .MREG ( 1 ), + .OPMODEREG ( 1 ), + .PREG ( 1 ), + .RSTTYPE ( "SYNC" )) + \blk00000003/blk00000126 ( + .CARRYIN(\blk00000003/sig0000005f ), + .CARRYOUT(\NLW_blk00000003/blk00000126_CARRYOUT_UNCONNECTED ), + .CLK(clk), + .RSTA(\blk00000003/sig0000005f ), + .RSTB(\blk00000003/sig0000005f ), + .RSTM(\blk00000003/sig0000005f ), + .RSTP(\blk00000003/sig0000005f ), + .RSTC(\blk00000003/sig0000005f ), + .RSTD(\blk00000003/sig0000005f ), + .RSTCARRYIN(\blk00000003/sig0000005f ), + .RSTOPMODE(\blk00000003/sig0000005f ), + .CEA(\blk00000003/sig00000065 ), + .CEB(\blk00000003/sig00000065 ), + .CEM(\blk00000003/sig00000065 ), + .CEP(\blk00000003/sig00000065 ), + .CEC(\blk00000003/sig0000005f ), + .CED(\blk00000003/sig0000005f ), + .CECARRYIN(\blk00000003/sig0000005f ), + .CEOPMODE(\blk00000003/sig00000065 ), + .A({\blk00000003/sig0000016f , \blk00000003/sig00000170 , \blk00000003/sig00000171 , \blk00000003/sig00000172 , \blk00000003/sig00000173 , +\blk00000003/sig00000174 , \blk00000003/sig00000175 , \blk00000003/sig00000176 , \blk00000003/sig00000177 , \blk00000003/sig00000178 , +\blk00000003/sig00000179 , \blk00000003/sig0000017a , \blk00000003/sig0000017b , \blk00000003/sig0000017c , \blk00000003/sig0000017d , +\blk00000003/sig0000017e , \blk00000003/sig0000017f , \blk00000003/sig00000180 }), + .B({\blk00000003/sig00000181 , \blk00000003/sig00000181 , \blk00000003/sig000001d6 , \blk00000003/sig000001d7 , \blk00000003/sig000001d8 , +\blk00000003/sig000001d9 , \blk00000003/sig000001da , \blk00000003/sig000001db , \blk00000003/sig000001dc , \blk00000003/sig000001dd , +\blk00000003/sig000001de , \blk00000003/sig000001df , \blk00000003/sig000001e0 , \blk00000003/sig000001e1 , \blk00000003/sig000001e2 , +\blk00000003/sig000001e3 , \blk00000003/sig000001e4 , \blk00000003/sig000001e5 }), + .D({\blk00000003/sig0000005f , \blk00000003/sig0000005f , \blk00000003/sig0000005f , \blk00000003/sig0000005f , \blk00000003/sig0000005f , +\blk00000003/sig0000005f , \blk00000003/sig0000005f , \blk00000003/sig0000005f , \blk00000003/sig0000005f , \blk00000003/sig0000005f , +\blk00000003/sig0000005f , \blk00000003/sig0000005f , \blk00000003/sig0000005f , \blk00000003/sig0000005f , \blk00000003/sig0000005f , +\blk00000003/sig0000005f , \blk00000003/sig0000005f , \blk00000003/sig0000005f }), + .C({\blk00000003/sig00000065 , \blk00000003/sig00000065 , \blk00000003/sig00000065 , \blk00000003/sig00000065 , \blk00000003/sig00000065 , +\blk00000003/sig00000065 , \blk00000003/sig00000065 , \blk00000003/sig00000065 , \blk00000003/sig00000065 , \blk00000003/sig00000065 , +\blk00000003/sig00000065 , \blk00000003/sig00000065 , \blk00000003/sig00000065 , \blk00000003/sig00000065 , \blk00000003/sig00000065 , +\blk00000003/sig00000065 , \blk00000003/sig00000065 , \blk00000003/sig00000065 , \blk00000003/sig00000065 , \blk00000003/sig00000065 , +\blk00000003/sig00000065 , \blk00000003/sig00000065 , \blk00000003/sig00000065 , \blk00000003/sig00000065 , \blk00000003/sig00000065 , +\blk00000003/sig00000065 , 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+\NLW_blk00000003/blk00000126_P<39>_UNCONNECTED , \NLW_blk00000003/blk00000126_P<38>_UNCONNECTED , \NLW_blk00000003/blk00000126_P<37>_UNCONNECTED , +\NLW_blk00000003/blk00000126_P<36>_UNCONNECTED , \NLW_blk00000003/blk00000126_P<35>_UNCONNECTED , \NLW_blk00000003/blk00000126_P<34>_UNCONNECTED , +\blk00000003/sig0000022a , \blk00000003/sig0000022b , \blk00000003/sig0000022c , \blk00000003/sig0000022d , \blk00000003/sig0000022e , +\blk00000003/sig0000022f , \blk00000003/sig00000230 , \blk00000003/sig00000231 , \blk00000003/sig00000232 , \blk00000003/sig00000233 , +\blk00000003/sig00000234 , \blk00000003/sig00000235 , \blk00000003/sig00000236 , \blk00000003/sig00000237 , \blk00000003/sig00000238 , +\blk00000003/sig00000239 , \blk00000003/sig0000023a , \blk00000003/sig0000023b , \blk00000003/sig0000023c , +\NLW_blk00000003/blk00000126_P<14>_UNCONNECTED , \NLW_blk00000003/blk00000126_P<13>_UNCONNECTED , \NLW_blk00000003/blk00000126_P<12>_UNCONNECTED , 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\NLW_blk00000003/blk00000124_P<41>_UNCONNECTED , \NLW_blk00000003/blk00000124_P<40>_UNCONNECTED , +\NLW_blk00000003/blk00000124_P<39>_UNCONNECTED , \NLW_blk00000003/blk00000124_P<38>_UNCONNECTED , \NLW_blk00000003/blk00000124_P<37>_UNCONNECTED , +\NLW_blk00000003/blk00000124_P<36>_UNCONNECTED , \NLW_blk00000003/blk00000124_P<35>_UNCONNECTED , \NLW_blk00000003/blk00000124_P<34>_UNCONNECTED , +\blk00000003/sig000001e6 , \blk00000003/sig000001e7 , \blk00000003/sig000001e8 , \blk00000003/sig000001e9 , \blk00000003/sig000001ea , +\blk00000003/sig000001eb , \blk00000003/sig000001ec , \blk00000003/sig000001ed , \blk00000003/sig000001ee , \blk00000003/sig000001ef , +\blk00000003/sig000001f0 , \blk00000003/sig000001f1 , \blk00000003/sig000001f2 , \blk00000003/sig000001f3 , \blk00000003/sig000001f4 , +\blk00000003/sig000001f5 , \blk00000003/sig000001f6 , \blk00000003/sig000001f7 , \blk00000003/sig000001f8 , +\NLW_blk00000003/blk00000124_P<14>_UNCONNECTED , \NLW_blk00000003/blk00000124_P<13>_UNCONNECTED , \NLW_blk00000003/blk00000124_P<12>_UNCONNECTED , +\NLW_blk00000003/blk00000124_P<11>_UNCONNECTED , \NLW_blk00000003/blk00000124_P<10>_UNCONNECTED , \NLW_blk00000003/blk00000124_P<9>_UNCONNECTED , +\NLW_blk00000003/blk00000124_P<8>_UNCONNECTED , \NLW_blk00000003/blk00000124_P<7>_UNCONNECTED , \NLW_blk00000003/blk00000124_P<6>_UNCONNECTED , +\NLW_blk00000003/blk00000124_P<5>_UNCONNECTED , \NLW_blk00000003/blk00000124_P<4>_UNCONNECTED , \NLW_blk00000003/blk00000124_P<3>_UNCONNECTED , +\NLW_blk00000003/blk00000124_P<2>_UNCONNECTED , \NLW_blk00000003/blk00000124_P<1>_UNCONNECTED , \NLW_blk00000003/blk00000124_P<0>_UNCONNECTED }), + .OPMODE({\blk00000003/sig000001f9 , \blk00000003/sig0000005f , \blk00000003/sig0000005f , \blk00000003/sig0000005f , \blk00000003/sig0000005f , +\blk00000003/sig00000065 , \blk00000003/sig0000005f , \blk00000003/sig00000065 }), + .PCIN({\blk00000003/sig00000193 , \blk00000003/sig00000194 , \blk00000003/sig00000195 , \blk00000003/sig00000196 , \blk00000003/sig00000197 , +\blk00000003/sig00000198 , \blk00000003/sig00000199 , \blk00000003/sig0000019a , \blk00000003/sig0000019b , \blk00000003/sig0000019c , +\blk00000003/sig0000019d , \blk00000003/sig0000019e , \blk00000003/sig0000019f , \blk00000003/sig000001a0 , \blk00000003/sig000001a1 , +\blk00000003/sig000001a2 , \blk00000003/sig000001a3 , \blk00000003/sig000001a4 , \blk00000003/sig000001a5 , \blk00000003/sig000001a6 , +\blk00000003/sig000001a7 , \blk00000003/sig000001a8 , \blk00000003/sig000001a9 , \blk00000003/sig000001aa , \blk00000003/sig000001ab , +\blk00000003/sig000001ac , \blk00000003/sig000001ad , \blk00000003/sig000001ae , \blk00000003/sig000001af , \blk00000003/sig000001b0 , +\blk00000003/sig000001b1 , \blk00000003/sig000001b2 , \blk00000003/sig000001b3 , \blk00000003/sig000001b4 , \blk00000003/sig000001b5 , +\blk00000003/sig000001b6 , \blk00000003/sig000001b7 , \blk00000003/sig000001b8 , \blk00000003/sig000001b9 , \blk00000003/sig000001ba , +\blk00000003/sig000001bb , \blk00000003/sig000001bc , \blk00000003/sig000001bd , \blk00000003/sig000001be , \blk00000003/sig000001bf , +\blk00000003/sig000001c0 , \blk00000003/sig000001c1 , \blk00000003/sig000001c2 }), + .PCOUT({\NLW_blk00000003/blk00000124_PCOUT<47>_UNCONNECTED , \NLW_blk00000003/blk00000124_PCOUT<46>_UNCONNECTED , +\NLW_blk00000003/blk00000124_PCOUT<45>_UNCONNECTED , \NLW_blk00000003/blk00000124_PCOUT<44>_UNCONNECTED , +\NLW_blk00000003/blk00000124_PCOUT<43>_UNCONNECTED , \NLW_blk00000003/blk00000124_PCOUT<42>_UNCONNECTED , +\NLW_blk00000003/blk00000124_PCOUT<41>_UNCONNECTED , \NLW_blk00000003/blk00000124_PCOUT<40>_UNCONNECTED , +\NLW_blk00000003/blk00000124_PCOUT<39>_UNCONNECTED , \NLW_blk00000003/blk00000124_PCOUT<38>_UNCONNECTED , +\NLW_blk00000003/blk00000124_PCOUT<37>_UNCONNECTED , \NLW_blk00000003/blk00000124_PCOUT<36>_UNCONNECTED , +\NLW_blk00000003/blk00000124_PCOUT<35>_UNCONNECTED , \NLW_blk00000003/blk00000124_PCOUT<34>_UNCONNECTED , +\NLW_blk00000003/blk00000124_PCOUT<33>_UNCONNECTED , \NLW_blk00000003/blk00000124_PCOUT<32>_UNCONNECTED , +\NLW_blk00000003/blk00000124_PCOUT<31>_UNCONNECTED , \NLW_blk00000003/blk00000124_PCOUT<30>_UNCONNECTED , +\NLW_blk00000003/blk00000124_PCOUT<29>_UNCONNECTED , \NLW_blk00000003/blk00000124_PCOUT<28>_UNCONNECTED , +\NLW_blk00000003/blk00000124_PCOUT<27>_UNCONNECTED , \NLW_blk00000003/blk00000124_PCOUT<26>_UNCONNECTED , +\NLW_blk00000003/blk00000124_PCOUT<25>_UNCONNECTED , \NLW_blk00000003/blk00000124_PCOUT<24>_UNCONNECTED , +\NLW_blk00000003/blk00000124_PCOUT<23>_UNCONNECTED , \NLW_blk00000003/blk00000124_PCOUT<22>_UNCONNECTED , +\NLW_blk00000003/blk00000124_PCOUT<21>_UNCONNECTED , \NLW_blk00000003/blk00000124_PCOUT<20>_UNCONNECTED , +\NLW_blk00000003/blk00000124_PCOUT<19>_UNCONNECTED , \NLW_blk00000003/blk00000124_PCOUT<18>_UNCONNECTED , +\NLW_blk00000003/blk00000124_PCOUT<17>_UNCONNECTED , \NLW_blk00000003/blk00000124_PCOUT<16>_UNCONNECTED , +\NLW_blk00000003/blk00000124_PCOUT<15>_UNCONNECTED , \NLW_blk00000003/blk00000124_PCOUT<14>_UNCONNECTED , +\NLW_blk00000003/blk00000124_PCOUT<13>_UNCONNECTED , \NLW_blk00000003/blk00000124_PCOUT<12>_UNCONNECTED , +\NLW_blk00000003/blk00000124_PCOUT<11>_UNCONNECTED , \NLW_blk00000003/blk00000124_PCOUT<10>_UNCONNECTED , +\NLW_blk00000003/blk00000124_PCOUT<9>_UNCONNECTED , \NLW_blk00000003/blk00000124_PCOUT<8>_UNCONNECTED , +\NLW_blk00000003/blk00000124_PCOUT<7>_UNCONNECTED , \NLW_blk00000003/blk00000124_PCOUT<6>_UNCONNECTED , +\NLW_blk00000003/blk00000124_PCOUT<5>_UNCONNECTED , \NLW_blk00000003/blk00000124_PCOUT<4>_UNCONNECTED , +\NLW_blk00000003/blk00000124_PCOUT<3>_UNCONNECTED , \NLW_blk00000003/blk00000124_PCOUT<2>_UNCONNECTED , +\NLW_blk00000003/blk00000124_PCOUT<1>_UNCONNECTED , \NLW_blk00000003/blk00000124_PCOUT<0>_UNCONNECTED }), + .BCOUT({\NLW_blk00000003/blk00000124_BCOUT<17>_UNCONNECTED , \NLW_blk00000003/blk00000124_BCOUT<16>_UNCONNECTED , +\NLW_blk00000003/blk00000124_BCOUT<15>_UNCONNECTED , \NLW_blk00000003/blk00000124_BCOUT<14>_UNCONNECTED , +\NLW_blk00000003/blk00000124_BCOUT<13>_UNCONNECTED , \NLW_blk00000003/blk00000124_BCOUT<12>_UNCONNECTED , +\NLW_blk00000003/blk00000124_BCOUT<11>_UNCONNECTED , \NLW_blk00000003/blk00000124_BCOUT<10>_UNCONNECTED , +\NLW_blk00000003/blk00000124_BCOUT<9>_UNCONNECTED , \NLW_blk00000003/blk00000124_BCOUT<8>_UNCONNECTED , +\NLW_blk00000003/blk00000124_BCOUT<7>_UNCONNECTED , \NLW_blk00000003/blk00000124_BCOUT<6>_UNCONNECTED , +\NLW_blk00000003/blk00000124_BCOUT<5>_UNCONNECTED , \NLW_blk00000003/blk00000124_BCOUT<4>_UNCONNECTED , +\NLW_blk00000003/blk00000124_BCOUT<3>_UNCONNECTED , \NLW_blk00000003/blk00000124_BCOUT<2>_UNCONNECTED , +\NLW_blk00000003/blk00000124_BCOUT<1>_UNCONNECTED , \NLW_blk00000003/blk00000124_BCOUT<0>_UNCONNECTED }) + ); + DSP48A #( + .A0REG ( 0 ), + .A1REG ( 1 ), + .B0REG ( 0 ), + .B1REG ( 1 ), + .CARRYINREG ( 1 ), + .CARRYINSEL ( "OPMODE5" ), + .CREG ( 0 ), + .DREG ( 0 ), + .MREG ( 1 ), + .OPMODEREG ( 1 ), + .PREG ( 1 ), + .RSTTYPE ( "SYNC" )) + \blk00000003/blk00000123 ( + .CARRYIN(\blk00000003/sig0000005f ), + .CARRYOUT(\NLW_blk00000003/blk00000123_CARRYOUT_UNCONNECTED ), + .CLK(clk), + .RSTA(\blk00000003/sig0000005f ), + .RSTB(\blk00000003/sig0000005f ), + .RSTM(\blk00000003/sig0000005f ), + .RSTP(\blk00000003/sig0000005f ), + .RSTC(\blk00000003/sig0000005f ), + .RSTD(\blk00000003/sig0000005f ), + .RSTCARRYIN(\blk00000003/sig0000005f ), + .RSTOPMODE(\blk00000003/sig0000005f ), + .CEA(\blk00000003/sig00000065 ), + .CEB(\blk00000003/sig00000065 ), + .CEM(\blk00000003/sig00000065 ), + .CEP(\blk00000003/sig00000065 ), + .CEC(\blk00000003/sig0000005f ), + .CED(\blk00000003/sig0000005f ), + .CECARRYIN(\blk00000003/sig0000005f ), + .CEOPMODE(\blk00000003/sig00000065 ), + .A({\blk00000003/sig0000016f , \blk00000003/sig00000170 , \blk00000003/sig00000171 , \blk00000003/sig00000172 , \blk00000003/sig00000173 , +\blk00000003/sig00000174 , \blk00000003/sig00000175 , \blk00000003/sig00000176 , \blk00000003/sig00000177 , \blk00000003/sig00000178 , +\blk00000003/sig00000179 , \blk00000003/sig0000017a , \blk00000003/sig0000017b , \blk00000003/sig0000017c , \blk00000003/sig0000017d , +\blk00000003/sig0000017e , \blk00000003/sig0000017f , \blk00000003/sig00000180 }), + .B({\blk00000003/sig00000181 , \blk00000003/sig00000181 , \blk00000003/sig00000182 , \blk00000003/sig00000183 , \blk00000003/sig00000184 , +\blk00000003/sig00000185 , \blk00000003/sig00000186 , \blk00000003/sig00000187 , \blk00000003/sig00000188 , \blk00000003/sig00000189 , +\blk00000003/sig0000018a , \blk00000003/sig0000018b , \blk00000003/sig0000018c , \blk00000003/sig0000018d , \blk00000003/sig0000018e , +\blk00000003/sig0000018f , \blk00000003/sig00000190 , \blk00000003/sig00000191 }), + .D({\blk00000003/sig0000005f , \blk00000003/sig0000005f , \blk00000003/sig0000005f , \blk00000003/sig0000005f , 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\blk00000003/sig0000005f , \blk00000003/sig0000005f , \blk00000003/sig0000005f , +\blk00000003/sig0000005f , \blk00000003/sig0000005f , \blk00000003/sig0000005f , \blk00000003/sig0000005f , \blk00000003/sig0000005f , +\blk00000003/sig0000005f , \blk00000003/sig0000005f , \blk00000003/sig0000005f , \blk00000003/sig0000005f , \blk00000003/sig0000005f , +\blk00000003/sig0000005f , \blk00000003/sig0000005f , \blk00000003/sig0000005f , \blk00000003/sig0000005f , \blk00000003/sig0000005f , +\blk00000003/sig00000065 , \blk00000003/sig00000065 , \blk00000003/sig00000065 , \blk00000003/sig00000065 , \blk00000003/sig00000065 , +\blk00000003/sig00000065 , \blk00000003/sig00000065 , \blk00000003/sig00000065 }), + .P({\NLW_blk00000003/blk00000123_P<47>_UNCONNECTED , \NLW_blk00000003/blk00000123_P<46>_UNCONNECTED , +\NLW_blk00000003/blk00000123_P<45>_UNCONNECTED , \NLW_blk00000003/blk00000123_P<44>_UNCONNECTED , \NLW_blk00000003/blk00000123_P<43>_UNCONNECTED , +\NLW_blk00000003/blk00000123_P<42>_UNCONNECTED , \NLW_blk00000003/blk00000123_P<41>_UNCONNECTED , \NLW_blk00000003/blk00000123_P<40>_UNCONNECTED , +\NLW_blk00000003/blk00000123_P<39>_UNCONNECTED , \NLW_blk00000003/blk00000123_P<38>_UNCONNECTED , \NLW_blk00000003/blk00000123_P<37>_UNCONNECTED , +\NLW_blk00000003/blk00000123_P<36>_UNCONNECTED , \NLW_blk00000003/blk00000123_P<35>_UNCONNECTED , \NLW_blk00000003/blk00000123_P<34>_UNCONNECTED , +\NLW_blk00000003/blk00000123_P<33>_UNCONNECTED , \NLW_blk00000003/blk00000123_P<32>_UNCONNECTED , \NLW_blk00000003/blk00000123_P<31>_UNCONNECTED , +\NLW_blk00000003/blk00000123_P<30>_UNCONNECTED , \NLW_blk00000003/blk00000123_P<29>_UNCONNECTED , \NLW_blk00000003/blk00000123_P<28>_UNCONNECTED , +\NLW_blk00000003/blk00000123_P<27>_UNCONNECTED , \NLW_blk00000003/blk00000123_P<26>_UNCONNECTED , \NLW_blk00000003/blk00000123_P<25>_UNCONNECTED , +\NLW_blk00000003/blk00000123_P<24>_UNCONNECTED , \NLW_blk00000003/blk00000123_P<23>_UNCONNECTED , \NLW_blk00000003/blk00000123_P<22>_UNCONNECTED , +\NLW_blk00000003/blk00000123_P<21>_UNCONNECTED , \NLW_blk00000003/blk00000123_P<20>_UNCONNECTED , \NLW_blk00000003/blk00000123_P<19>_UNCONNECTED , +\NLW_blk00000003/blk00000123_P<18>_UNCONNECTED , \NLW_blk00000003/blk00000123_P<17>_UNCONNECTED , \NLW_blk00000003/blk00000123_P<16>_UNCONNECTED , +\NLW_blk00000003/blk00000123_P<15>_UNCONNECTED , \NLW_blk00000003/blk00000123_P<14>_UNCONNECTED , \NLW_blk00000003/blk00000123_P<13>_UNCONNECTED , +\NLW_blk00000003/blk00000123_P<12>_UNCONNECTED , \NLW_blk00000003/blk00000123_P<11>_UNCONNECTED , \NLW_blk00000003/blk00000123_P<10>_UNCONNECTED , +\NLW_blk00000003/blk00000123_P<9>_UNCONNECTED , \NLW_blk00000003/blk00000123_P<8>_UNCONNECTED , \NLW_blk00000003/blk00000123_P<7>_UNCONNECTED , +\NLW_blk00000003/blk00000123_P<6>_UNCONNECTED , \NLW_blk00000003/blk00000123_P<5>_UNCONNECTED , \NLW_blk00000003/blk00000123_P<4>_UNCONNECTED , +\NLW_blk00000003/blk00000123_P<3>_UNCONNECTED , \NLW_blk00000003/blk00000123_P<2>_UNCONNECTED , \NLW_blk00000003/blk00000123_P<1>_UNCONNECTED , +\NLW_blk00000003/blk00000123_P<0>_UNCONNECTED }), + .OPMODE({\blk00000003/sig00000192 , \blk00000003/sig0000005f , \blk00000003/sig0000005f , \blk00000003/sig0000005f , \blk00000003/sig00000065 , +\blk00000003/sig00000065 , \blk00000003/sig0000005f , \blk00000003/sig00000065 }), + .PCIN({\blk00000003/sig0000005f , \blk00000003/sig0000005f , \blk00000003/sig0000005f , \blk00000003/sig0000005f , \blk00000003/sig0000005f , +\blk00000003/sig0000005f , \blk00000003/sig0000005f , \blk00000003/sig0000005f , \blk00000003/sig0000005f , \blk00000003/sig0000005f , +\blk00000003/sig0000005f , \blk00000003/sig0000005f , \blk00000003/sig0000005f , \blk00000003/sig0000005f , \blk00000003/sig0000005f , +\blk00000003/sig0000005f , \blk00000003/sig0000005f , \blk00000003/sig0000005f , \blk00000003/sig0000005f , \blk00000003/sig0000005f , +\blk00000003/sig0000005f , \blk00000003/sig0000005f , \blk00000003/sig0000005f , \blk00000003/sig0000005f , \blk00000003/sig0000005f , +\blk00000003/sig0000005f , \blk00000003/sig0000005f , \blk00000003/sig0000005f , \blk00000003/sig0000005f , \blk00000003/sig0000005f , +\blk00000003/sig0000005f , \blk00000003/sig0000005f , \blk00000003/sig0000005f , \blk00000003/sig0000005f , \blk00000003/sig0000005f , +\blk00000003/sig0000005f , \blk00000003/sig0000005f , \blk00000003/sig0000005f , \blk00000003/sig0000005f , \blk00000003/sig0000005f , +\blk00000003/sig0000005f , \blk00000003/sig0000005f , \blk00000003/sig0000005f , \blk00000003/sig0000005f , \blk00000003/sig0000005f , +\blk00000003/sig0000005f , \blk00000003/sig0000005f , \blk00000003/sig0000005f }), + .PCOUT({\blk00000003/sig00000193 , \blk00000003/sig00000194 , \blk00000003/sig00000195 , \blk00000003/sig00000196 , \blk00000003/sig00000197 , +\blk00000003/sig00000198 , \blk00000003/sig00000199 , \blk00000003/sig0000019a , \blk00000003/sig0000019b , \blk00000003/sig0000019c , +\blk00000003/sig0000019d , \blk00000003/sig0000019e , \blk00000003/sig0000019f , \blk00000003/sig000001a0 , \blk00000003/sig000001a1 , +\blk00000003/sig000001a2 , \blk00000003/sig000001a3 , \blk00000003/sig000001a4 , \blk00000003/sig000001a5 , \blk00000003/sig000001a6 , +\blk00000003/sig000001a7 , \blk00000003/sig000001a8 , \blk00000003/sig000001a9 , \blk00000003/sig000001aa , \blk00000003/sig000001ab , +\blk00000003/sig000001ac , \blk00000003/sig000001ad , \blk00000003/sig000001ae , \blk00000003/sig000001af , \blk00000003/sig000001b0 , +\blk00000003/sig000001b1 , \blk00000003/sig000001b2 , \blk00000003/sig000001b3 , \blk00000003/sig000001b4 , \blk00000003/sig000001b5 , +\blk00000003/sig000001b6 , \blk00000003/sig000001b7 , \blk00000003/sig000001b8 , \blk00000003/sig000001b9 , \blk00000003/sig000001ba , +\blk00000003/sig000001bb , \blk00000003/sig000001bc , \blk00000003/sig000001bd , \blk00000003/sig000001be , \blk00000003/sig000001bf , +\blk00000003/sig000001c0 , \blk00000003/sig000001c1 , \blk00000003/sig000001c2 }), + .BCOUT({\NLW_blk00000003/blk00000123_BCOUT<17>_UNCONNECTED , \NLW_blk00000003/blk00000123_BCOUT<16>_UNCONNECTED , +\NLW_blk00000003/blk00000123_BCOUT<15>_UNCONNECTED , \NLW_blk00000003/blk00000123_BCOUT<14>_UNCONNECTED , +\NLW_blk00000003/blk00000123_BCOUT<13>_UNCONNECTED , \NLW_blk00000003/blk00000123_BCOUT<12>_UNCONNECTED , +\NLW_blk00000003/blk00000123_BCOUT<11>_UNCONNECTED , \NLW_blk00000003/blk00000123_BCOUT<10>_UNCONNECTED , +\NLW_blk00000003/blk00000123_BCOUT<9>_UNCONNECTED , \NLW_blk00000003/blk00000123_BCOUT<8>_UNCONNECTED , +\NLW_blk00000003/blk00000123_BCOUT<7>_UNCONNECTED , \NLW_blk00000003/blk00000123_BCOUT<6>_UNCONNECTED , +\NLW_blk00000003/blk00000123_BCOUT<5>_UNCONNECTED , \NLW_blk00000003/blk00000123_BCOUT<4>_UNCONNECTED , +\NLW_blk00000003/blk00000123_BCOUT<3>_UNCONNECTED , \NLW_blk00000003/blk00000123_BCOUT<2>_UNCONNECTED , +\NLW_blk00000003/blk00000123_BCOUT<1>_UNCONNECTED , \NLW_blk00000003/blk00000123_BCOUT<0>_UNCONNECTED }) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000010c ( + .C(clk), + .CE(\blk00000003/sig00000079 ), + .D(\blk00000003/sig00000157 ), + .R(\blk00000003/sig0000005f ), + .Q(\blk00000003/sig0000008a ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000010b ( + .C(clk), + .CE(\blk00000003/sig00000079 ), + .D(\blk00000003/sig0000015a ), + .R(\blk00000003/sig0000005f ), + .Q(\blk00000003/sig00000089 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000010a ( + .C(clk), + .CE(\blk00000003/sig00000079 ), + .D(\blk00000003/sig0000015d ), + .R(\blk00000003/sig0000005f ), + .Q(\blk00000003/sig00000088 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000109 ( + .C(clk), + .CE(\blk00000003/sig00000079 ), + .D(\blk00000003/sig00000160 ), + .R(\blk00000003/sig0000005f ), + .Q(\blk00000003/sig00000087 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000108 ( + .C(clk), + .CE(\blk00000003/sig00000079 ), + .D(\blk00000003/sig00000163 ), + .R(\blk00000003/sig0000005f ), + .Q(\blk00000003/sig00000086 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000107 ( + .C(clk), + .CE(\blk00000003/sig00000079 ), + .D(\blk00000003/sig00000165 ), + .R(\blk00000003/sig0000005f ), + .Q(\blk00000003/sig00000085 ) + ); + MUXCY \blk00000003/blk00000106 ( + .CI(\blk00000003/sig0000007d ), + .DI(\blk00000003/sig0000005f ), + .S(\blk00000003/sig00000164 ), + .O(\blk00000003/sig00000161 ) + ); + XORCY \blk00000003/blk00000105 ( + .CI(\blk00000003/sig0000007d ), + .LI(\blk00000003/sig00000164 ), + .O(\blk00000003/sig00000165 ) + ); + MUXCY \blk00000003/blk00000104 ( + .CI(\blk00000003/sig00000161 ), + .DI(\blk00000003/sig0000005f ), + .S(\blk00000003/sig00000162 ), + .O(\blk00000003/sig0000015e ) + ); + MUXCY \blk00000003/blk00000103 ( + .CI(\blk00000003/sig0000015e ), + .DI(\blk00000003/sig0000005f ), + .S(\blk00000003/sig0000015f ), + .O(\blk00000003/sig0000015b ) + ); + MUXCY \blk00000003/blk00000102 ( + .CI(\blk00000003/sig0000015b ), + .DI(\blk00000003/sig0000005f ), + .S(\blk00000003/sig0000015c ), + .O(\blk00000003/sig00000158 ) + ); + MUXCY \blk00000003/blk00000101 ( + .CI(\blk00000003/sig00000158 ), + .DI(\blk00000003/sig0000005f ), + .S(\blk00000003/sig00000159 ), + .O(\blk00000003/sig00000155 ) + ); + XORCY \blk00000003/blk00000100 ( + .CI(\blk00000003/sig00000161 ), + .LI(\blk00000003/sig00000162 ), + .O(\blk00000003/sig00000163 ) + ); + XORCY \blk00000003/blk000000ff ( + .CI(\blk00000003/sig0000015e ), + .LI(\blk00000003/sig0000015f ), + .O(\blk00000003/sig00000160 ) + ); + XORCY \blk00000003/blk000000fe ( + .CI(\blk00000003/sig0000015b ), + .LI(\blk00000003/sig0000015c ), + .O(\blk00000003/sig0000015d ) + ); + XORCY \blk00000003/blk000000fd ( + .CI(\blk00000003/sig00000158 ), + .LI(\blk00000003/sig00000159 ), + .O(\blk00000003/sig0000015a ) + ); + XORCY \blk00000003/blk000000fc ( + .CI(\blk00000003/sig00000155 ), + .LI(\blk00000003/sig00000156 ), + .O(\blk00000003/sig00000157 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000000fb ( + .C(clk), + .CE(\blk00000003/sig00000067 ), + .D(\blk00000003/sig00000146 ), + .R(\blk00000003/sig0000005f ), + .Q(\blk00000003/sig00000078 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000000fa ( + .C(clk), + .CE(\blk00000003/sig00000067 ), + .D(\blk00000003/sig00000149 ), + .R(\blk00000003/sig0000005f ), + .Q(\blk00000003/sig00000077 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000000f9 ( + .C(clk), + .CE(\blk00000003/sig00000067 ), + .D(\blk00000003/sig0000014c ), + .R(\blk00000003/sig0000005f ), + .Q(\blk00000003/sig00000076 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000000f8 ( + .C(clk), + .CE(\blk00000003/sig00000067 ), + .D(\blk00000003/sig0000014f ), + .R(\blk00000003/sig0000005f ), + .Q(\blk00000003/sig00000075 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000000f7 ( + .C(clk), + .CE(\blk00000003/sig00000067 ), + .D(\blk00000003/sig00000152 ), + .R(\blk00000003/sig0000005f ), + .Q(\blk00000003/sig00000074 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000000f6 ( + .C(clk), + .CE(\blk00000003/sig00000067 ), + .D(\blk00000003/sig00000154 ), + .R(\blk00000003/sig0000005f ), + .Q(\blk00000003/sig00000073 ) + ); + MUXCY \blk00000003/blk000000f5 ( + .CI(\blk00000003/sig0000006b ), + .DI(\blk00000003/sig0000005f ), + .S(\blk00000003/sig00000153 ), + .O(\blk00000003/sig00000150 ) + ); + XORCY \blk00000003/blk000000f4 ( + .CI(\blk00000003/sig0000006b ), + .LI(\blk00000003/sig00000153 ), + .O(\blk00000003/sig00000154 ) + ); + MUXCY \blk00000003/blk000000f3 ( + .CI(\blk00000003/sig00000150 ), + .DI(\blk00000003/sig0000005f ), + .S(\blk00000003/sig00000151 ), + .O(\blk00000003/sig0000014d ) + ); + MUXCY \blk00000003/blk000000f2 ( + .CI(\blk00000003/sig0000014d ), + .DI(\blk00000003/sig0000005f ), + .S(\blk00000003/sig0000014e ), + .O(\blk00000003/sig0000014a ) + ); + MUXCY \blk00000003/blk000000f1 ( + .CI(\blk00000003/sig0000014a ), + .DI(\blk00000003/sig0000005f ), + .S(\blk00000003/sig0000014b ), + .O(\blk00000003/sig00000147 ) + ); + MUXCY \blk00000003/blk000000f0 ( + .CI(\blk00000003/sig00000147 ), + .DI(\blk00000003/sig0000005f ), + .S(\blk00000003/sig00000148 ), + .O(\blk00000003/sig00000144 ) + ); + XORCY \blk00000003/blk000000ef ( + .CI(\blk00000003/sig00000150 ), + .LI(\blk00000003/sig00000151 ), + .O(\blk00000003/sig00000152 ) + ); + XORCY \blk00000003/blk000000ee ( + .CI(\blk00000003/sig0000014d ), + .LI(\blk00000003/sig0000014e ), + .O(\blk00000003/sig0000014f ) + ); + XORCY \blk00000003/blk000000ed ( + .CI(\blk00000003/sig0000014a ), + .LI(\blk00000003/sig0000014b ), + .O(\blk00000003/sig0000014c ) + ); + XORCY \blk00000003/blk000000ec ( + .CI(\blk00000003/sig00000147 ), + .LI(\blk00000003/sig00000148 ), + .O(\blk00000003/sig00000149 ) + ); + XORCY \blk00000003/blk000000eb ( + .CI(\blk00000003/sig00000144 ), + .LI(\blk00000003/sig00000145 ), + .O(\blk00000003/sig00000146 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000000ea ( + .C(clk), + .CE(NlwRenamedSig_OI_rfd), + .D(\blk00000003/sig00000135 ), + .R(\blk00000003/sig0000005f ), + .Q(NlwRenamedSig_OI_xn_index[5]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000000e9 ( + .C(clk), + .CE(NlwRenamedSig_OI_rfd), + .D(\blk00000003/sig00000138 ), + .R(\blk00000003/sig0000005f ), + .Q(NlwRenamedSig_OI_xn_index[4]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000000e8 ( + .C(clk), + .CE(NlwRenamedSig_OI_rfd), + .D(\blk00000003/sig0000013b ), + .R(\blk00000003/sig0000005f ), + .Q(NlwRenamedSig_OI_xn_index[3]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000000e7 ( + .C(clk), + .CE(NlwRenamedSig_OI_rfd), + .D(\blk00000003/sig0000013e ), + .R(\blk00000003/sig0000005f ), + .Q(NlwRenamedSig_OI_xn_index[2]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000000e6 ( + .C(clk), + .CE(NlwRenamedSig_OI_rfd), + .D(\blk00000003/sig00000141 ), + .R(\blk00000003/sig0000005f ), + .Q(NlwRenamedSig_OI_xn_index[1]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000000e5 ( + .C(clk), + .CE(NlwRenamedSig_OI_rfd), + .D(\blk00000003/sig00000143 ), + .R(\blk00000003/sig0000005f ), + .Q(NlwRenamedSig_OI_xn_index[0]) + ); + MUXCY \blk00000003/blk000000e4 ( + .CI(\blk00000003/sig0000012a ), + .DI(\blk00000003/sig0000005f ), + .S(\blk00000003/sig00000142 ), + .O(\blk00000003/sig0000013f ) + ); + XORCY \blk00000003/blk000000e3 ( + .CI(\blk00000003/sig0000012a ), + .LI(\blk00000003/sig00000142 ), + .O(\blk00000003/sig00000143 ) + ); + MUXCY \blk00000003/blk000000e2 ( + .CI(\blk00000003/sig0000013f ), + .DI(\blk00000003/sig0000005f ), + .S(\blk00000003/sig00000140 ), + .O(\blk00000003/sig0000013c ) + ); + MUXCY \blk00000003/blk000000e1 ( + .CI(\blk00000003/sig0000013c ), + .DI(\blk00000003/sig0000005f ), + .S(\blk00000003/sig0000013d ), + .O(\blk00000003/sig00000139 ) + ); + MUXCY \blk00000003/blk000000e0 ( + .CI(\blk00000003/sig00000139 ), + .DI(\blk00000003/sig0000005f ), + .S(\blk00000003/sig0000013a ), + .O(\blk00000003/sig00000136 ) + ); + MUXCY \blk00000003/blk000000df ( + .CI(\blk00000003/sig00000136 ), + .DI(\blk00000003/sig0000005f ), + .S(\blk00000003/sig00000137 ), + .O(\blk00000003/sig00000133 ) + ); + XORCY \blk00000003/blk000000de ( + .CI(\blk00000003/sig0000013f ), + .LI(\blk00000003/sig00000140 ), + .O(\blk00000003/sig00000141 ) + ); + XORCY \blk00000003/blk000000dd ( + .CI(\blk00000003/sig0000013c ), + .LI(\blk00000003/sig0000013d ), + .O(\blk00000003/sig0000013e ) + ); + XORCY \blk00000003/blk000000dc ( + .CI(\blk00000003/sig00000139 ), + .LI(\blk00000003/sig0000013a ), + .O(\blk00000003/sig0000013b ) + ); + XORCY \blk00000003/blk000000db ( + .CI(\blk00000003/sig00000136 ), + .LI(\blk00000003/sig00000137 ), + .O(\blk00000003/sig00000138 ) + ); + XORCY \blk00000003/blk000000da ( + .CI(\blk00000003/sig00000133 ), + .LI(\blk00000003/sig00000134 ), + .O(\blk00000003/sig00000135 ) + ); + FD #( + .INIT ( 1'b0 )) + \blk00000003/blk000000d9 ( + .C(clk), + .D(\blk00000003/sig00000131 ), + .Q(\blk00000003/sig00000132 ) + ); + FDE #( + .INIT ( 1'b1 )) + \blk00000003/blk000000d8 ( + .C(clk), + .CE(fwd_inv_we), + .D(fwd_inv), + .Q(\blk00000003/sig0000012e ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000000d7 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig00000130 ), + .Q(NlwRenamedSig_OI_rfd) + ); + FDE #( + .INIT ( 1'b1 )) + \blk00000003/blk000000d6 ( + .C(clk), + .CE(\blk00000003/sig0000012d ), + .D(\blk00000003/sig0000012e ), + .Q(\blk00000003/sig0000012f ) + ); + FD #( + .INIT ( 1'b0 )) + \blk00000003/blk000000d5 ( + .C(clk), + .D(\blk00000003/sig00000121 ), + .Q(\blk00000003/sig000000a5 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000000d4 ( + .C(clk), + .CE(NlwRenamedSig_OI_rfd), + .D(\blk00000003/sig00000128 ), + .R(\blk00000003/sig0000005f ), + .Q(\blk00000003/sig0000012b ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk000000d3 ( + .C(clk), + .CE(NlwRenamedSig_OI_rfd), + .D(\blk00000003/sig0000012b ), + .R(\blk00000003/sig0000005f ), + .Q(\blk00000003/sig0000012c ) + ); + MUXCY \blk00000003/blk000000d2 ( + .CI(\blk00000003/sig00000065 ), + .DI(\blk00000003/sig0000005f ), + .S(\blk00000003/sig00000129 ), + .O(\blk00000003/sig0000012a ) + ); + XORCY \blk00000003/blk000000d1 ( + .CI(\blk00000003/sig00000126 ), + .LI(\blk00000003/sig0000005f ), + .O(\blk00000003/sig00000128 ) + ); + MUXCY \blk00000003/blk000000d0 ( + .CI(\blk00000003/sig00000065 ), + .DI(\blk00000003/sig0000005f ), + .S(\blk00000003/sig00000124 ), + .O(\blk00000003/sig00000127 ) + ); + MUXCY \blk00000003/blk000000cf ( + .CI(\blk00000003/sig00000127 ), + .DI(\blk00000003/sig0000005f ), + .S(\blk00000003/sig00000123 ), + .O(\blk00000003/sig00000125 ) + ); + MUXCY \blk00000003/blk000000ce ( + .CI(\blk00000003/sig00000125 ), + .DI(\blk00000003/sig0000005f ), + .S(\blk00000003/sig00000122 ), + .O(\blk00000003/sig00000126 ) + ); + LUT4 #( + .INIT ( 16'h9009 )) + \blk00000003/blk000000cd ( + .I0(NlwRenamedSig_OI_xn_index[0]), + .I1(\blk00000003/sig00000065 ), + .I2(NlwRenamedSig_OI_xn_index[1]), + .I3(\blk00000003/sig0000005f ), + .O(\blk00000003/sig00000124 ) + ); + LUT4 #( + .INIT ( 16'h9009 )) + \blk00000003/blk000000cc ( + .I0(NlwRenamedSig_OI_xn_index[2]), + .I1(\blk00000003/sig00000065 ), + .I2(NlwRenamedSig_OI_xn_index[3]), + .I3(\blk00000003/sig00000065 ), + .O(\blk00000003/sig00000123 ) + ); + LUT4 #( + .INIT ( 16'h9009 )) + \blk00000003/blk000000cb ( + .I0(NlwRenamedSig_OI_xn_index[4]), + .I1(\blk00000003/sig00000065 ), + .I2(NlwRenamedSig_OI_xn_index[5]), + .I3(\blk00000003/sig00000065 ), + .O(\blk00000003/sig00000122 ) + ); + XORCY \blk00000003/blk000000ca ( + .CI(\blk00000003/sig0000011f ), + .LI(\blk00000003/sig0000005f ), + .O(\blk00000003/sig00000121 ) + ); + MUXCY \blk00000003/blk000000c9 ( + .CI(\blk00000003/sig00000065 ), + .DI(\blk00000003/sig0000005f ), + .S(\blk00000003/sig0000011d ), + .O(\blk00000003/sig00000120 ) + ); + MUXCY \blk00000003/blk000000c8 ( + .CI(\blk00000003/sig00000120 ), + .DI(\blk00000003/sig0000005f ), + .S(\blk00000003/sig0000011c ), + .O(\blk00000003/sig0000011e ) + ); + MUXCY \blk00000003/blk000000c7 ( + .CI(\blk00000003/sig0000011e ), + .DI(\blk00000003/sig0000005f ), + .S(\blk00000003/sig0000011b ), + .O(\blk00000003/sig0000011f ) + ); + LUT4 #( + .INIT ( 16'h9009 )) + \blk00000003/blk000000c6 ( + .I0(\blk00000003/sig00000065 ), + .I1(NlwRenamedSig_OI_xn_index[0]), + .I2(\blk00000003/sig00000065 ), + .I3(NlwRenamedSig_OI_xn_index[1]), + .O(\blk00000003/sig0000011d ) + ); + LUT4 #( + .INIT ( 16'h9009 )) + \blk00000003/blk000000c5 ( + .I0(\blk00000003/sig00000065 ), + .I1(NlwRenamedSig_OI_xn_index[2]), + .I2(\blk00000003/sig00000065 ), + .I3(NlwRenamedSig_OI_xn_index[3]), + .O(\blk00000003/sig0000011c ) + ); + LUT4 #( + .INIT ( 16'h9009 )) + \blk00000003/blk000000c4 ( + .I0(\blk00000003/sig00000065 ), + .I1(NlwRenamedSig_OI_xn_index[4]), + .I2(\blk00000003/sig0000005f ), + .I3(NlwRenamedSig_OI_xn_index[5]), + .O(\blk00000003/sig0000011b ) + ); + FDR #( + .INIT ( 1'b0 )) + \blk00000003/blk0000007d ( + .C(clk), + .D(\blk00000003/sig00000066 ), + .R(\blk00000003/sig0000005f ), + .Q(\blk00000003/sig000000f3 ) + ); + FDR #( + .INIT ( 1'b0 )) + \blk00000003/blk0000007c ( + .C(clk), + .D(\blk00000003/sig00000078 ), + .R(\blk00000003/sig0000005f ), + .Q(\blk00000003/sig000000fa ) + ); + FDR #( + .INIT ( 1'b0 )) + \blk00000003/blk0000007b ( + .C(clk), + .D(\blk00000003/sig00000077 ), + .R(\blk00000003/sig0000005f ), + .Q(\blk00000003/sig000000f9 ) + ); + FDR #( + .INIT ( 1'b0 )) + \blk00000003/blk0000007a ( + .C(clk), + .D(\blk00000003/sig00000076 ), + .R(\blk00000003/sig0000005f ), + .Q(\blk00000003/sig000000f8 ) + ); + FDR #( + .INIT ( 1'b0 )) + \blk00000003/blk00000079 ( + .C(clk), + .D(\blk00000003/sig00000075 ), + .R(\blk00000003/sig0000005f ), + .Q(\blk00000003/sig000000f7 ) + ); + FDR #( + .INIT ( 1'b0 )) + \blk00000003/blk00000078 ( + .C(clk), + .D(\blk00000003/sig00000074 ), + .R(\blk00000003/sig0000005f ), + .Q(\blk00000003/sig000000f6 ) + ); + FDR #( + .INIT ( 1'b0 )) + \blk00000003/blk00000077 ( + .C(clk), + .D(\blk00000003/sig00000073 ), + .R(\blk00000003/sig0000005f ), + .Q(\blk00000003/sig000000f5 ) + ); + FDR #( + .INIT ( 1'b0 )) + \blk00000003/blk00000076 ( + .C(clk), + .D(\blk00000003/sig00000068 ), + .R(\blk00000003/sig0000005f ), + .Q(\blk00000003/sig000000f2 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000075 ( + .C(clk), + .CE(\blk00000003/sig000000f3 ), + .D(\blk00000003/sig000000f4 ), + .R(\blk00000003/sig0000005f ), + .Q(\blk00000003/sig000000a1 ) + ); + FDR #( + .INIT ( 1'b0 )) + \blk00000003/blk00000074 ( + .C(clk), + .D(\blk00000003/sig0000008e ), + .R(\blk00000003/sig0000005f ), + .Q(NlwRenamedSig_OI_edone) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000073 ( + .C(clk), + .CE(\blk00000003/sig000000f2 ), + .D(\blk00000003/sig000000a1 ), + .R(\blk00000003/sig0000005f ), + .Q(\blk00000003/sig000000a3 ) + ); + FDR #( + .INIT ( 1'b0 )) + \blk00000003/blk00000072 ( + .C(clk), + .D(\blk00000003/sig0000008c ), + .R(\blk00000003/sig0000005f ), + .Q(\blk00000003/sig000000d9 ) + ); + FD #( + .INIT ( 1'b0 )) + \blk00000003/blk00000071 ( + .C(clk), + .D(\blk00000003/sig000000f0 ), + .Q(\blk00000003/sig000000f1 ) + ); + FD #( + .INIT ( 1'b0 )) + \blk00000003/blk00000070 ( + .C(clk), + .D(\blk00000003/sig000000ee ), + .Q(\blk00000003/sig000000ef ) + ); + FD #( + .INIT ( 1'b0 )) + \blk00000003/blk0000006f ( + .C(clk), + .D(\blk00000003/sig000000ec ), + .Q(\blk00000003/sig000000ed ) + ); + FD #( + .INIT ( 1'b0 )) + \blk00000003/blk0000006e ( + .C(clk), + .D(\blk00000003/sig000000ea ), + .Q(\blk00000003/sig000000eb ) + ); + FD #( + .INIT ( 1'b0 )) + \blk00000003/blk0000006d ( + .C(clk), + .D(\blk00000003/sig000000e8 ), + .Q(\blk00000003/sig000000e9 ) + ); + FD #( + .INIT ( 1'b0 )) + \blk00000003/blk0000006c ( + .C(clk), + .D(\blk00000003/sig000000e6 ), + .Q(\blk00000003/sig000000e7 ) + ); + FD #( + .INIT ( 1'b0 )) + \blk00000003/blk0000006b ( + .C(clk), + .D(\blk00000003/sig000000e4 ), + .Q(\blk00000003/sig000000e5 ) + ); + FD #( + .INIT ( 1'b0 )) + \blk00000003/blk0000006a ( + .C(clk), + .D(\blk00000003/sig000000e2 ), + .Q(\blk00000003/sig000000e3 ) + ); + FD #( + .INIT ( 1'b0 )) + \blk00000003/blk00000069 ( + .C(clk), + .D(\blk00000003/sig000000e0 ), + .Q(\blk00000003/sig000000e1 ) + ); + FD #( + .INIT ( 1'b0 )) + \blk00000003/blk00000068 ( + .C(clk), + .D(\blk00000003/sig000000de ), + .Q(\blk00000003/sig000000df ) + ); + FD #( + .INIT ( 1'b0 )) + \blk00000003/blk00000067 ( + .C(clk), + .D(\blk00000003/sig000000dc ), + .Q(\blk00000003/sig000000dd ) + ); + FD #( + .INIT ( 1'b0 )) + \blk00000003/blk00000066 ( + .C(clk), + .D(\blk00000003/sig000000da ), + .Q(\blk00000003/sig000000db ) + ); + FDR #( + .INIT ( 1'b0 )) + \blk00000003/blk00000065 ( + .C(clk), + .D(NlwRenamedSig_OI_edone), + .R(\blk00000003/sig0000005f ), + .Q(done) + ); + FDR #( + .INIT ( 1'b0 )) + \blk00000003/blk00000064 ( + .C(clk), + .D(\blk00000003/sig000000d9 ), + .R(\blk00000003/sig0000005f ), + .Q(dv) + ); + FDR #( + .INIT ( 1'b0 )) + \blk00000003/blk00000063 ( + .C(clk), + .D(\blk00000003/sig000000d8 ), + .R(\blk00000003/sig000000ab ), + .Q(xk_im_4[0]) + ); + FDR #( + .INIT ( 1'b0 )) + \blk00000003/blk00000062 ( + .C(clk), + .D(\blk00000003/sig000000d7 ), + .R(\blk00000003/sig000000ab ), + .Q(xk_im_4[1]) + ); + FDR #( + .INIT ( 1'b0 )) + \blk00000003/blk00000061 ( + .C(clk), + .D(\blk00000003/sig000000d6 ), + .R(\blk00000003/sig000000ab ), + .Q(xk_im_4[2]) + ); + FDR #( + .INIT ( 1'b0 )) + \blk00000003/blk00000060 ( + .C(clk), + .D(\blk00000003/sig000000d5 ), + .R(\blk00000003/sig000000ab ), + .Q(xk_im_4[3]) + ); + FDR #( + .INIT ( 1'b0 )) + \blk00000003/blk0000005f ( + .C(clk), + .D(\blk00000003/sig000000d4 ), + .R(\blk00000003/sig000000ab ), + .Q(xk_im_4[4]) + ); + FDR #( + .INIT ( 1'b0 )) + \blk00000003/blk0000005e ( + .C(clk), + .D(\blk00000003/sig000000d3 ), + .R(\blk00000003/sig000000ab ), + .Q(xk_im_4[5]) + ); + FDR #( + .INIT ( 1'b0 )) + \blk00000003/blk0000005d ( + .C(clk), + .D(\blk00000003/sig000000d2 ), + .R(\blk00000003/sig000000ab ), + .Q(xk_im_4[6]) + ); + FDR #( + .INIT ( 1'b0 )) + \blk00000003/blk0000005c ( + .C(clk), + .D(\blk00000003/sig000000d1 ), + .R(\blk00000003/sig000000ab ), + .Q(xk_im_4[7]) + ); + FDR #( + .INIT ( 1'b0 )) + \blk00000003/blk0000005b ( + .C(clk), + .D(\blk00000003/sig000000d0 ), + .R(\blk00000003/sig000000ab ), + .Q(xk_im_4[8]) + ); + FDR #( + .INIT ( 1'b0 )) + \blk00000003/blk0000005a ( + .C(clk), + .D(\blk00000003/sig000000cf ), + .R(\blk00000003/sig000000ab ), + .Q(xk_im_4[9]) + ); + FDR #( + .INIT ( 1'b0 )) + \blk00000003/blk00000059 ( + .C(clk), + .D(\blk00000003/sig000000ce ), + .R(\blk00000003/sig000000ab ), + .Q(xk_im_4[10]) + ); + FDR #( + .INIT ( 1'b0 )) + \blk00000003/blk00000058 ( + .C(clk), + .D(\blk00000003/sig000000cd ), + .R(\blk00000003/sig000000ab ), + .Q(xk_im_4[11]) + ); + FDR #( + .INIT ( 1'b0 )) + \blk00000003/blk00000057 ( + .C(clk), + .D(\blk00000003/sig000000cc ), + .R(\blk00000003/sig000000ab ), + .Q(xk_im_4[12]) + ); + FDR #( + .INIT ( 1'b0 )) + \blk00000003/blk00000056 ( + .C(clk), + .D(\blk00000003/sig000000cb ), + .R(\blk00000003/sig000000ab ), + .Q(xk_im_4[13]) + ); + FDR #( + .INIT ( 1'b0 )) + \blk00000003/blk00000055 ( + .C(clk), + .D(\blk00000003/sig000000ca ), + .R(\blk00000003/sig000000ab ), + .Q(xk_im_4[14]) + ); + FDR #( + .INIT ( 1'b0 )) + \blk00000003/blk00000054 ( + .C(clk), + .D(\blk00000003/sig000000c9 ), + .R(\blk00000003/sig000000ab ), + .Q(xk_im_4[15]) + ); + FDR #( + .INIT ( 1'b0 )) + \blk00000003/blk00000053 ( + .C(clk), + .D(\blk00000003/sig000000c8 ), + .R(\blk00000003/sig000000ab ), + .Q(xk_im_4[16]) + ); + FDR #( + .INIT ( 1'b0 )) + \blk00000003/blk00000052 ( + .C(clk), + .D(\blk00000003/sig000000c7 ), + .R(\blk00000003/sig000000ab ), + .Q(xk_im_4[17]) + ); + FDR #( + .INIT ( 1'b0 )) + \blk00000003/blk00000051 ( + .C(clk), + .D(\blk00000003/sig000000c6 ), + .R(\blk00000003/sig000000ab ), + .Q(xk_im_4[18]) + ); + FDR #( + .INIT ( 1'b0 )) + \blk00000003/blk00000050 ( + .C(clk), + .D(\blk00000003/sig000000c5 ), + .R(\blk00000003/sig000000ab ), + .Q(xk_im_4[19]) + ); + FDR #( + .INIT ( 1'b0 )) + \blk00000003/blk0000004f ( + .C(clk), + .D(\blk00000003/sig000000c4 ), + .R(\blk00000003/sig000000ab ), + .Q(xk_im_4[20]) + ); + FDR #( + .INIT ( 1'b0 )) + \blk00000003/blk0000004e ( + .C(clk), + .D(\blk00000003/sig000000c3 ), + .R(\blk00000003/sig000000ab ), + .Q(xk_im_4[21]) + ); + FDR #( + .INIT ( 1'b0 )) + \blk00000003/blk0000004d ( + .C(clk), + .D(\blk00000003/sig000000c2 ), + .R(\blk00000003/sig000000ab ), + .Q(xk_im_4[22]) + ); + FDR #( + .INIT ( 1'b0 )) + \blk00000003/blk0000004c ( + .C(clk), + .D(\blk00000003/sig000000c1 ), + .R(\blk00000003/sig000000ab ), + .Q(xk_re_3[0]) + ); + FDR #( + .INIT ( 1'b0 )) + \blk00000003/blk0000004b ( + .C(clk), + .D(\blk00000003/sig000000c0 ), + .R(\blk00000003/sig000000ab ), + .Q(xk_re_3[1]) + ); + FDR #( + .INIT ( 1'b0 )) + \blk00000003/blk0000004a ( + .C(clk), + .D(\blk00000003/sig000000bf ), + .R(\blk00000003/sig000000ab ), + .Q(xk_re_3[2]) + ); + FDR #( + .INIT ( 1'b0 )) + \blk00000003/blk00000049 ( + .C(clk), + .D(\blk00000003/sig000000be ), + .R(\blk00000003/sig000000ab ), + .Q(xk_re_3[3]) + ); + FDR #( + .INIT ( 1'b0 )) + \blk00000003/blk00000048 ( + .C(clk), + .D(\blk00000003/sig000000bd ), + .R(\blk00000003/sig000000ab ), + .Q(xk_re_3[4]) + ); + FDR #( + .INIT ( 1'b0 )) + \blk00000003/blk00000047 ( + .C(clk), + .D(\blk00000003/sig000000bc ), + .R(\blk00000003/sig000000ab ), + .Q(xk_re_3[5]) + ); + FDR #( + .INIT ( 1'b0 )) + \blk00000003/blk00000046 ( + .C(clk), + .D(\blk00000003/sig000000bb ), + .R(\blk00000003/sig000000ab ), + .Q(xk_re_3[6]) + ); + FDR #( + .INIT ( 1'b0 )) + \blk00000003/blk00000045 ( + .C(clk), + .D(\blk00000003/sig000000ba ), + .R(\blk00000003/sig000000ab ), + .Q(xk_re_3[7]) + ); + FDR #( + .INIT ( 1'b0 )) + \blk00000003/blk00000044 ( + .C(clk), + .D(\blk00000003/sig000000b9 ), + .R(\blk00000003/sig000000ab ), + .Q(xk_re_3[8]) + ); + FDR #( + .INIT ( 1'b0 )) + \blk00000003/blk00000043 ( + .C(clk), + .D(\blk00000003/sig000000b8 ), + .R(\blk00000003/sig000000ab ), + .Q(xk_re_3[9]) + ); + FDR #( + .INIT ( 1'b0 )) + \blk00000003/blk00000042 ( + .C(clk), + .D(\blk00000003/sig000000b7 ), + .R(\blk00000003/sig000000ab ), + .Q(xk_re_3[10]) + ); + FDR #( + .INIT ( 1'b0 )) + \blk00000003/blk00000041 ( + .C(clk), + .D(\blk00000003/sig000000b6 ), + .R(\blk00000003/sig000000ab ), + .Q(xk_re_3[11]) + ); + FDR #( + .INIT ( 1'b0 )) + \blk00000003/blk00000040 ( + .C(clk), + .D(\blk00000003/sig000000b5 ), + .R(\blk00000003/sig000000ab ), + .Q(xk_re_3[12]) + ); + FDR #( + .INIT ( 1'b0 )) + \blk00000003/blk0000003f ( + .C(clk), + .D(\blk00000003/sig000000b4 ), + .R(\blk00000003/sig000000ab ), + .Q(xk_re_3[13]) + ); + FDR #( + .INIT ( 1'b0 )) + \blk00000003/blk0000003e ( + .C(clk), + .D(\blk00000003/sig000000b3 ), + .R(\blk00000003/sig000000ab ), + .Q(xk_re_3[14]) + ); + FDR #( + .INIT ( 1'b0 )) + \blk00000003/blk0000003d ( + .C(clk), + .D(\blk00000003/sig000000b2 ), + .R(\blk00000003/sig000000ab ), + .Q(xk_re_3[15]) + ); + FDR #( + .INIT ( 1'b0 )) + \blk00000003/blk0000003c ( + .C(clk), + .D(\blk00000003/sig000000b1 ), + .R(\blk00000003/sig000000ab ), + .Q(xk_re_3[16]) + ); + FDR #( + .INIT ( 1'b0 )) + \blk00000003/blk0000003b ( + .C(clk), + .D(\blk00000003/sig000000b0 ), + .R(\blk00000003/sig000000ab ), + .Q(xk_re_3[17]) + ); + FDR #( + .INIT ( 1'b0 )) + \blk00000003/blk0000003a ( + .C(clk), + .D(\blk00000003/sig000000af ), + .R(\blk00000003/sig000000ab ), + .Q(xk_re_3[18]) + ); + FDR #( + .INIT ( 1'b0 )) + \blk00000003/blk00000039 ( + .C(clk), + .D(\blk00000003/sig000000ae ), + .R(\blk00000003/sig000000ab ), + .Q(xk_re_3[19]) + ); + FDR #( + .INIT ( 1'b0 )) + \blk00000003/blk00000038 ( + .C(clk), + .D(\blk00000003/sig000000ad ), + .R(\blk00000003/sig000000ab ), + .Q(xk_re_3[20]) + ); + FDR #( + .INIT ( 1'b0 )) + \blk00000003/blk00000037 ( + .C(clk), + .D(\blk00000003/sig000000ac ), + .R(\blk00000003/sig000000ab ), + .Q(xk_re_3[21]) + ); + FDR #( + .INIT ( 1'b0 )) + \blk00000003/blk00000036 ( + .C(clk), + .D(\blk00000003/sig000000aa ), + .R(\blk00000003/sig000000ab ), + .Q(xk_re_3[22]) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000035 ( + .C(clk), + .CE(\blk00000003/sig00000079 ), + .D(\blk00000003/sig000000a9 ), + .R(\blk00000003/sig0000005f ), + .Q(\blk00000003/sig0000007a ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000034 ( + .C(clk), + .CE(\blk00000003/sig00000079 ), + .D(\blk00000003/sig0000007f ), + .R(\blk00000003/sig0000005f ), + .Q(\blk00000003/sig000000a9 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000033 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig0000007b ), + .R(\blk00000003/sig0000005f ), + .Q(\blk00000003/sig00000079 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000032 ( + .C(clk), + .CE(\blk00000003/sig00000067 ), + .D(\blk00000003/sig000000a8 ), + .R(\blk00000003/sig0000005f ), + .Q(\blk00000003/sig00000068 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000031 ( + .C(clk), + .CE(\blk00000003/sig00000067 ), + .D(\blk00000003/sig0000006d ), + .R(\blk00000003/sig0000005f ), + .Q(\blk00000003/sig000000a8 ) + ); + FDRE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000030 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig00000069 ), + .R(\blk00000003/sig0000005f ), + .Q(\blk00000003/sig00000067 ) + ); + FDR #( + .INIT ( 1'b0 )) + \blk00000003/blk0000002f ( + .C(clk), + .D(\blk00000003/sig000000a6 ), + .R(\blk00000003/sig0000005f ), + .Q(\blk00000003/sig000000a7 ) + ); + FD #( + .INIT ( 1'b0 )) + \blk00000003/blk0000002e ( + .C(clk), + .D(\blk00000003/sig000000a5 ), + .Q(\blk00000003/sig000000a6 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000002d ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig000000a3 ), + .Q(\blk00000003/sig000000a4 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000002c ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/sig000000a1 ), + .Q(\blk00000003/sig000000a2 ) + ); + FDR #( + .INIT ( 1'b0 )) + \blk00000003/blk0000002b ( + .C(clk), + .D(\blk00000003/sig00000085 ), + .R(\blk00000003/sig0000005f ), + .Q(\blk00000003/sig000000a0 ) + ); + FDR #( + .INIT ( 1'b0 )) + \blk00000003/blk0000002a ( + .C(clk), + .D(\blk00000003/sig00000086 ), + .R(\blk00000003/sig0000005f ), + .Q(\blk00000003/sig0000009f ) + ); + FDR #( + .INIT ( 1'b0 )) + \blk00000003/blk00000029 ( + .C(clk), + .D(\blk00000003/sig00000087 ), + .R(\blk00000003/sig0000005f ), + .Q(\blk00000003/sig0000009e ) + ); + FDR #( + .INIT ( 1'b0 )) + \blk00000003/blk00000028 ( + .C(clk), + .D(\blk00000003/sig00000088 ), + .R(\blk00000003/sig0000005f ), + .Q(\blk00000003/sig0000009d ) + ); + FDR #( + .INIT ( 1'b0 )) + \blk00000003/blk00000027 ( + .C(clk), + .D(\blk00000003/sig00000089 ), + .R(\blk00000003/sig0000005f ), + .Q(\blk00000003/sig0000009c ) + ); + FDR #( + .INIT ( 1'b0 )) + \blk00000003/blk00000026 ( + .C(clk), + .D(\blk00000003/sig0000008a ), + .R(\blk00000003/sig0000005f ), + .Q(\blk00000003/sig0000009b ) + ); + FDR #( + .INIT ( 1'b0 )) + \blk00000003/blk00000025 ( + .C(clk), + .D(\blk00000003/sig00000085 ), + .R(\blk00000003/sig0000005f ), + .Q(\blk00000003/sig0000009a ) + ); + FDR #( + .INIT ( 1'b0 )) + \blk00000003/blk00000024 ( + .C(clk), + .D(\blk00000003/sig00000086 ), + .R(\blk00000003/sig0000005f ), + .Q(\blk00000003/sig00000099 ) + ); + FDR #( + .INIT ( 1'b0 )) + \blk00000003/blk00000023 ( + .C(clk), + .D(\blk00000003/sig00000087 ), + .R(\blk00000003/sig0000005f ), + .Q(\blk00000003/sig00000098 ) + ); + FDR #( + .INIT ( 1'b0 )) + \blk00000003/blk00000022 ( + .C(clk), + .D(\blk00000003/sig00000088 ), + .R(\blk00000003/sig0000005f ), + .Q(\blk00000003/sig00000097 ) + ); + FDR #( + .INIT ( 1'b0 )) + \blk00000003/blk00000021 ( + .C(clk), + .D(\blk00000003/sig00000089 ), + .R(\blk00000003/sig0000005f ), + .Q(\blk00000003/sig00000096 ) + ); + FDR #( + .INIT ( 1'b0 )) + \blk00000003/blk00000020 ( + .C(clk), + .D(\blk00000003/sig0000008a ), + .R(\blk00000003/sig0000005f ), + .Q(\blk00000003/sig00000095 ) + ); + FD #( + .INIT ( 1'b0 )) + \blk00000003/blk0000001f ( + .C(clk), + .D(\blk00000003/sig00000078 ), + .Q(\blk00000003/sig00000094 ) + ); + FD #( + .INIT ( 1'b0 )) + \blk00000003/blk0000001e ( + .C(clk), + .D(\blk00000003/sig00000077 ), + .Q(\blk00000003/sig00000093 ) + ); + FD #( + .INIT ( 1'b0 )) + \blk00000003/blk0000001d ( + .C(clk), + .D(\blk00000003/sig00000076 ), + .Q(\blk00000003/sig00000092 ) + ); + FD #( + .INIT ( 1'b0 )) + \blk00000003/blk0000001c ( + .C(clk), + .D(\blk00000003/sig00000075 ), + .Q(\blk00000003/sig00000091 ) + ); + FD #( + .INIT ( 1'b0 )) + \blk00000003/blk0000001b ( + .C(clk), + .D(\blk00000003/sig00000074 ), + .Q(\blk00000003/sig00000090 ) + ); + FD #( + .INIT ( 1'b0 )) + \blk00000003/blk0000001a ( + .C(clk), + .D(\blk00000003/sig00000073 ), + .Q(\blk00000003/sig0000008f ) + ); + FDR #( + .INIT ( 1'b0 )) + \blk00000003/blk00000019 ( + .C(clk), + .D(\blk00000003/sig0000008d ), + .R(\blk00000003/sig0000005f ), + .Q(\blk00000003/sig0000008e ) + ); + FDR #( + .INIT ( 1'b0 )) + \blk00000003/blk00000018 ( + .C(clk), + .D(\blk00000003/sig0000008b ), + .R(\blk00000003/sig0000005f ), + .Q(\blk00000003/sig0000008c ) + ); + LUT4 #( + .INIT ( 16'h9009 )) + \blk00000003/blk00000017 ( + .I0(\blk00000003/sig00000089 ), + .I1(\blk00000003/sig00000065 ), + .I2(\blk00000003/sig0000008a ), + .I3(\blk00000003/sig00000065 ), + .O(\blk00000003/sig00000084 ) + ); + LUT4 #( + .INIT ( 16'h9009 )) + \blk00000003/blk00000016 ( + .I0(\blk00000003/sig00000087 ), + .I1(\blk00000003/sig00000065 ), + .I2(\blk00000003/sig00000088 ), + .I3(\blk00000003/sig00000065 ), + .O(\blk00000003/sig00000082 ) + ); + LUT4 #( + .INIT ( 16'h9009 )) + \blk00000003/blk00000015 ( + .I0(\blk00000003/sig00000085 ), + .I1(\blk00000003/sig00000065 ), + .I2(\blk00000003/sig00000086 ), + .I3(\blk00000003/sig0000005f ), + .O(\blk00000003/sig00000080 ) + ); + MUXCY \blk00000003/blk00000014 ( + .CI(\blk00000003/sig00000083 ), + .DI(\blk00000003/sig0000005f ), + .S(\blk00000003/sig00000084 ), + .O(\blk00000003/sig0000007e ) + ); + MUXCY \blk00000003/blk00000013 ( + .CI(\blk00000003/sig00000081 ), + .DI(\blk00000003/sig0000005f ), + .S(\blk00000003/sig00000082 ), + .O(\blk00000003/sig00000083 ) + ); + MUXCY \blk00000003/blk00000012 ( + .CI(\blk00000003/sig00000065 ), + .DI(\blk00000003/sig0000005f ), + .S(\blk00000003/sig00000080 ), + .O(\blk00000003/sig00000081 ) + ); + XORCY \blk00000003/blk00000011 ( + .CI(\blk00000003/sig0000007e ), + .LI(\blk00000003/sig0000005f ), + .O(\blk00000003/sig0000007f ) + ); + MUXCY \blk00000003/blk00000010 ( + .CI(\blk00000003/sig00000065 ), + .DI(\blk00000003/sig0000005f ), + .S(\blk00000003/sig0000007c ), + .O(\blk00000003/sig0000007d ) + ); + LUT3 #( + .INIT ( 8'hAE )) + \blk00000003/blk0000000f ( + .I0(\blk00000003/sig00000068 ), + .I1(\blk00000003/sig00000079 ), + .I2(\blk00000003/sig0000007a ), + .O(\blk00000003/sig0000007b ) + ); + LUT4 #( + .INIT ( 16'h9009 )) + \blk00000003/blk0000000e ( + .I0(\blk00000003/sig00000077 ), + .I1(\blk00000003/sig00000065 ), + .I2(\blk00000003/sig00000078 ), + .I3(\blk00000003/sig00000065 ), + .O(\blk00000003/sig00000072 ) + ); + LUT4 #( + .INIT ( 16'h9009 )) + \blk00000003/blk0000000d ( + .I0(\blk00000003/sig00000075 ), + .I1(\blk00000003/sig00000065 ), + .I2(\blk00000003/sig00000076 ), + .I3(\blk00000003/sig00000065 ), + .O(\blk00000003/sig00000070 ) + ); + LUT4 #( + .INIT ( 16'h9009 )) + \blk00000003/blk0000000c ( + .I0(\blk00000003/sig00000073 ), + .I1(\blk00000003/sig00000065 ), + .I2(\blk00000003/sig00000074 ), + .I3(\blk00000003/sig0000005f ), + .O(\blk00000003/sig0000006e ) + ); + MUXCY \blk00000003/blk0000000b ( + .CI(\blk00000003/sig00000071 ), + .DI(\blk00000003/sig0000005f ), + .S(\blk00000003/sig00000072 ), + .O(\blk00000003/sig0000006c ) + ); + MUXCY \blk00000003/blk0000000a ( + .CI(\blk00000003/sig0000006f ), + .DI(\blk00000003/sig0000005f ), + .S(\blk00000003/sig00000070 ), + .O(\blk00000003/sig00000071 ) + ); + MUXCY \blk00000003/blk00000009 ( + .CI(\blk00000003/sig00000065 ), + .DI(\blk00000003/sig0000005f ), + .S(\blk00000003/sig0000006e ), + .O(\blk00000003/sig0000006f ) + ); + XORCY \blk00000003/blk00000008 ( + .CI(\blk00000003/sig0000006c ), + .LI(\blk00000003/sig0000005f ), + .O(\blk00000003/sig0000006d ) + ); + MUXCY \blk00000003/blk00000007 ( + .CI(\blk00000003/sig00000065 ), + .DI(\blk00000003/sig0000005f ), + .S(\blk00000003/sig0000006a ), + .O(\blk00000003/sig0000006b ) + ); + LUT3 #( + .INIT ( 8'hAE )) + \blk00000003/blk00000006 ( + .I0(\blk00000003/sig00000066 ), + .I1(\blk00000003/sig00000067 ), + .I2(\blk00000003/sig00000068 ), + .O(\blk00000003/sig00000069 ) + ); + VCC \blk00000003/blk00000005 ( + .P(\blk00000003/sig00000065 ) + ); + GND \blk00000003/blk00000004 ( + .G(\blk00000003/sig0000005f ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000007e/blk000000a0 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/blk0000007e/sig0000152c ), + .Q(\blk00000003/sig000000fb ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000007e/blk0000009f ( + .A0(\blk00000003/blk0000007e/sig0000151c ), + .A1(\blk00000003/blk0000007e/sig0000151b ), + .A2(\blk00000003/blk0000007e/sig0000151b ), + .A3(\blk00000003/blk0000007e/sig0000151b ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(xn_im_1[15]), + .Q(\blk00000003/blk0000007e/sig0000152c ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000007e/blk0000009e ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/blk0000007e/sig0000152b ), + .Q(\blk00000003/sig000000fc ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000007e/blk0000009d ( + .A0(\blk00000003/blk0000007e/sig0000151c ), + .A1(\blk00000003/blk0000007e/sig0000151b ), + .A2(\blk00000003/blk0000007e/sig0000151b ), + .A3(\blk00000003/blk0000007e/sig0000151b ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(xn_im_1[14]), + .Q(\blk00000003/blk0000007e/sig0000152b ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000007e/blk0000009c ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/blk0000007e/sig0000152a ), + .Q(\blk00000003/sig000000fd ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000007e/blk0000009b ( + .A0(\blk00000003/blk0000007e/sig0000151c ), + .A1(\blk00000003/blk0000007e/sig0000151b ), + .A2(\blk00000003/blk0000007e/sig0000151b ), + .A3(\blk00000003/blk0000007e/sig0000151b ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(xn_im_1[13]), + .Q(\blk00000003/blk0000007e/sig0000152a ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000007e/blk0000009a ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/blk0000007e/sig00001529 ), + .Q(\blk00000003/sig000000fe ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000007e/blk00000099 ( + .A0(\blk00000003/blk0000007e/sig0000151c ), + .A1(\blk00000003/blk0000007e/sig0000151b ), + .A2(\blk00000003/blk0000007e/sig0000151b ), + .A3(\blk00000003/blk0000007e/sig0000151b ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(xn_im_1[12]), + .Q(\blk00000003/blk0000007e/sig00001529 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000007e/blk00000098 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/blk0000007e/sig00001528 ), + .Q(\blk00000003/sig000000ff ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000007e/blk00000097 ( + .A0(\blk00000003/blk0000007e/sig0000151c ), + .A1(\blk00000003/blk0000007e/sig0000151b ), + .A2(\blk00000003/blk0000007e/sig0000151b ), + .A3(\blk00000003/blk0000007e/sig0000151b ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(xn_im_1[11]), + .Q(\blk00000003/blk0000007e/sig00001528 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000007e/blk00000096 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/blk0000007e/sig00001527 ), + .Q(\blk00000003/sig00000100 ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000007e/blk00000095 ( + .A0(\blk00000003/blk0000007e/sig0000151c ), + .A1(\blk00000003/blk0000007e/sig0000151b ), + .A2(\blk00000003/blk0000007e/sig0000151b ), + .A3(\blk00000003/blk0000007e/sig0000151b ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(xn_im_1[10]), + .Q(\blk00000003/blk0000007e/sig00001527 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000007e/blk00000094 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/blk0000007e/sig00001526 ), + .Q(\blk00000003/sig00000101 ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000007e/blk00000093 ( + .A0(\blk00000003/blk0000007e/sig0000151c ), + .A1(\blk00000003/blk0000007e/sig0000151b ), + .A2(\blk00000003/blk0000007e/sig0000151b ), + .A3(\blk00000003/blk0000007e/sig0000151b ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(xn_im_1[9]), + .Q(\blk00000003/blk0000007e/sig00001526 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000007e/blk00000092 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/blk0000007e/sig00001525 ), + .Q(\blk00000003/sig00000102 ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000007e/blk00000091 ( + .A0(\blk00000003/blk0000007e/sig0000151c ), + .A1(\blk00000003/blk0000007e/sig0000151b ), + .A2(\blk00000003/blk0000007e/sig0000151b ), + .A3(\blk00000003/blk0000007e/sig0000151b ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(xn_im_1[8]), + .Q(\blk00000003/blk0000007e/sig00001525 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000007e/blk00000090 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/blk0000007e/sig00001524 ), + .Q(\blk00000003/sig00000103 ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000007e/blk0000008f ( + .A0(\blk00000003/blk0000007e/sig0000151c ), + .A1(\blk00000003/blk0000007e/sig0000151b ), + .A2(\blk00000003/blk0000007e/sig0000151b ), + .A3(\blk00000003/blk0000007e/sig0000151b ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(xn_im_1[7]), + .Q(\blk00000003/blk0000007e/sig00001524 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000007e/blk0000008e ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/blk0000007e/sig00001523 ), + .Q(\blk00000003/sig00000104 ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000007e/blk0000008d ( + .A0(\blk00000003/blk0000007e/sig0000151c ), + .A1(\blk00000003/blk0000007e/sig0000151b ), + .A2(\blk00000003/blk0000007e/sig0000151b ), + .A3(\blk00000003/blk0000007e/sig0000151b ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(xn_im_1[6]), + .Q(\blk00000003/blk0000007e/sig00001523 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000007e/blk0000008c ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/blk0000007e/sig00001522 ), + .Q(\blk00000003/sig00000105 ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000007e/blk0000008b ( + .A0(\blk00000003/blk0000007e/sig0000151c ), + .A1(\blk00000003/blk0000007e/sig0000151b ), + .A2(\blk00000003/blk0000007e/sig0000151b ), + .A3(\blk00000003/blk0000007e/sig0000151b ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(xn_im_1[5]), + .Q(\blk00000003/blk0000007e/sig00001522 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000007e/blk0000008a ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/blk0000007e/sig00001521 ), + .Q(\blk00000003/sig00000106 ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000007e/blk00000089 ( + .A0(\blk00000003/blk0000007e/sig0000151c ), + .A1(\blk00000003/blk0000007e/sig0000151b ), + .A2(\blk00000003/blk0000007e/sig0000151b ), + .A3(\blk00000003/blk0000007e/sig0000151b ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(xn_im_1[4]), + .Q(\blk00000003/blk0000007e/sig00001521 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000007e/blk00000088 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/blk0000007e/sig00001520 ), + .Q(\blk00000003/sig00000107 ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000007e/blk00000087 ( + .A0(\blk00000003/blk0000007e/sig0000151c ), + .A1(\blk00000003/blk0000007e/sig0000151b ), + .A2(\blk00000003/blk0000007e/sig0000151b ), + .A3(\blk00000003/blk0000007e/sig0000151b ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(xn_im_1[3]), + .Q(\blk00000003/blk0000007e/sig00001520 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000007e/blk00000086 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/blk0000007e/sig0000151f ), + .Q(\blk00000003/sig00000108 ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000007e/blk00000085 ( + .A0(\blk00000003/blk0000007e/sig0000151c ), + .A1(\blk00000003/blk0000007e/sig0000151b ), + .A2(\blk00000003/blk0000007e/sig0000151b ), + .A3(\blk00000003/blk0000007e/sig0000151b ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(xn_im_1[2]), + .Q(\blk00000003/blk0000007e/sig0000151f ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000007e/blk00000084 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/blk0000007e/sig0000151e ), + .Q(\blk00000003/sig00000109 ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000007e/blk00000083 ( + .A0(\blk00000003/blk0000007e/sig0000151c ), + .A1(\blk00000003/blk0000007e/sig0000151b ), + .A2(\blk00000003/blk0000007e/sig0000151b ), + .A3(\blk00000003/blk0000007e/sig0000151b ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(xn_im_1[1]), + .Q(\blk00000003/blk0000007e/sig0000151e ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000007e/blk00000082 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/blk0000007e/sig0000151d ), + .Q(\blk00000003/sig0000010a ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000007e/blk00000081 ( + .A0(\blk00000003/blk0000007e/sig0000151c ), + .A1(\blk00000003/blk0000007e/sig0000151b ), + .A2(\blk00000003/blk0000007e/sig0000151b ), + .A3(\blk00000003/blk0000007e/sig0000151b ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(xn_im_1[0]), + .Q(\blk00000003/blk0000007e/sig0000151d ) + ); + VCC \blk00000003/blk0000007e/blk00000080 ( + .P(\blk00000003/blk0000007e/sig0000151c ) + ); + GND \blk00000003/blk0000007e/blk0000007f ( + .G(\blk00000003/blk0000007e/sig0000151b ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000000a1/blk000000c3 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/blk000000a1/sig00001560 ), + .Q(\blk00000003/sig0000010b ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000000a1/blk000000c2 ( + .A0(\blk00000003/blk000000a1/sig00001550 ), + .A1(\blk00000003/blk000000a1/sig0000154f ), + .A2(\blk00000003/blk000000a1/sig0000154f ), + .A3(\blk00000003/blk000000a1/sig0000154f ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(xn_re_0[15]), + .Q(\blk00000003/blk000000a1/sig00001560 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000000a1/blk000000c1 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/blk000000a1/sig0000155f ), + .Q(\blk00000003/sig0000010c ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000000a1/blk000000c0 ( + .A0(\blk00000003/blk000000a1/sig00001550 ), + .A1(\blk00000003/blk000000a1/sig0000154f ), + .A2(\blk00000003/blk000000a1/sig0000154f ), + .A3(\blk00000003/blk000000a1/sig0000154f ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(xn_re_0[14]), + .Q(\blk00000003/blk000000a1/sig0000155f ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000000a1/blk000000bf ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/blk000000a1/sig0000155e ), + .Q(\blk00000003/sig0000010d ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000000a1/blk000000be ( + .A0(\blk00000003/blk000000a1/sig00001550 ), + .A1(\blk00000003/blk000000a1/sig0000154f ), + .A2(\blk00000003/blk000000a1/sig0000154f ), + .A3(\blk00000003/blk000000a1/sig0000154f ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(xn_re_0[13]), + .Q(\blk00000003/blk000000a1/sig0000155e ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000000a1/blk000000bd ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/blk000000a1/sig0000155d ), + .Q(\blk00000003/sig0000010e ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000000a1/blk000000bc ( + .A0(\blk00000003/blk000000a1/sig00001550 ), + .A1(\blk00000003/blk000000a1/sig0000154f ), + .A2(\blk00000003/blk000000a1/sig0000154f ), + .A3(\blk00000003/blk000000a1/sig0000154f ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(xn_re_0[12]), + .Q(\blk00000003/blk000000a1/sig0000155d ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000000a1/blk000000bb ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/blk000000a1/sig0000155c ), + .Q(\blk00000003/sig0000010f ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000000a1/blk000000ba ( + .A0(\blk00000003/blk000000a1/sig00001550 ), + .A1(\blk00000003/blk000000a1/sig0000154f ), + .A2(\blk00000003/blk000000a1/sig0000154f ), + .A3(\blk00000003/blk000000a1/sig0000154f ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(xn_re_0[11]), + .Q(\blk00000003/blk000000a1/sig0000155c ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000000a1/blk000000b9 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/blk000000a1/sig0000155b ), + .Q(\blk00000003/sig00000110 ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000000a1/blk000000b8 ( + .A0(\blk00000003/blk000000a1/sig00001550 ), + .A1(\blk00000003/blk000000a1/sig0000154f ), + .A2(\blk00000003/blk000000a1/sig0000154f ), + .A3(\blk00000003/blk000000a1/sig0000154f ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(xn_re_0[10]), + .Q(\blk00000003/blk000000a1/sig0000155b ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000000a1/blk000000b7 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/blk000000a1/sig0000155a ), + .Q(\blk00000003/sig00000111 ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000000a1/blk000000b6 ( + .A0(\blk00000003/blk000000a1/sig00001550 ), + .A1(\blk00000003/blk000000a1/sig0000154f ), + .A2(\blk00000003/blk000000a1/sig0000154f ), + .A3(\blk00000003/blk000000a1/sig0000154f ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(xn_re_0[9]), + .Q(\blk00000003/blk000000a1/sig0000155a ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000000a1/blk000000b5 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/blk000000a1/sig00001559 ), + .Q(\blk00000003/sig00000112 ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000000a1/blk000000b4 ( + .A0(\blk00000003/blk000000a1/sig00001550 ), + .A1(\blk00000003/blk000000a1/sig0000154f ), + .A2(\blk00000003/blk000000a1/sig0000154f ), + .A3(\blk00000003/blk000000a1/sig0000154f ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(xn_re_0[8]), + .Q(\blk00000003/blk000000a1/sig00001559 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000000a1/blk000000b3 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/blk000000a1/sig00001558 ), + .Q(\blk00000003/sig00000113 ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000000a1/blk000000b2 ( + .A0(\blk00000003/blk000000a1/sig00001550 ), + .A1(\blk00000003/blk000000a1/sig0000154f ), + .A2(\blk00000003/blk000000a1/sig0000154f ), + .A3(\blk00000003/blk000000a1/sig0000154f ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(xn_re_0[7]), + .Q(\blk00000003/blk000000a1/sig00001558 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000000a1/blk000000b1 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/blk000000a1/sig00001557 ), + .Q(\blk00000003/sig00000114 ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000000a1/blk000000b0 ( + .A0(\blk00000003/blk000000a1/sig00001550 ), + .A1(\blk00000003/blk000000a1/sig0000154f ), + .A2(\blk00000003/blk000000a1/sig0000154f ), + .A3(\blk00000003/blk000000a1/sig0000154f ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(xn_re_0[6]), + .Q(\blk00000003/blk000000a1/sig00001557 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000000a1/blk000000af ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/blk000000a1/sig00001556 ), + .Q(\blk00000003/sig00000115 ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000000a1/blk000000ae ( + .A0(\blk00000003/blk000000a1/sig00001550 ), + .A1(\blk00000003/blk000000a1/sig0000154f ), + .A2(\blk00000003/blk000000a1/sig0000154f ), + .A3(\blk00000003/blk000000a1/sig0000154f ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(xn_re_0[5]), + .Q(\blk00000003/blk000000a1/sig00001556 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000000a1/blk000000ad ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/blk000000a1/sig00001555 ), + .Q(\blk00000003/sig00000116 ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000000a1/blk000000ac ( + .A0(\blk00000003/blk000000a1/sig00001550 ), + .A1(\blk00000003/blk000000a1/sig0000154f ), + .A2(\blk00000003/blk000000a1/sig0000154f ), + .A3(\blk00000003/blk000000a1/sig0000154f ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(xn_re_0[4]), + .Q(\blk00000003/blk000000a1/sig00001555 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000000a1/blk000000ab ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/blk000000a1/sig00001554 ), + .Q(\blk00000003/sig00000117 ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000000a1/blk000000aa ( + .A0(\blk00000003/blk000000a1/sig00001550 ), + .A1(\blk00000003/blk000000a1/sig0000154f ), + .A2(\blk00000003/blk000000a1/sig0000154f ), + .A3(\blk00000003/blk000000a1/sig0000154f ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(xn_re_0[3]), + .Q(\blk00000003/blk000000a1/sig00001554 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000000a1/blk000000a9 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/blk000000a1/sig00001553 ), + .Q(\blk00000003/sig00000118 ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000000a1/blk000000a8 ( + .A0(\blk00000003/blk000000a1/sig00001550 ), + .A1(\blk00000003/blk000000a1/sig0000154f ), + .A2(\blk00000003/blk000000a1/sig0000154f ), + .A3(\blk00000003/blk000000a1/sig0000154f ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(xn_re_0[2]), + .Q(\blk00000003/blk000000a1/sig00001553 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000000a1/blk000000a7 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/blk000000a1/sig00001552 ), + .Q(\blk00000003/sig00000119 ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000000a1/blk000000a6 ( + .A0(\blk00000003/blk000000a1/sig00001550 ), + .A1(\blk00000003/blk000000a1/sig0000154f ), + .A2(\blk00000003/blk000000a1/sig0000154f ), + .A3(\blk00000003/blk000000a1/sig0000154f ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(xn_re_0[1]), + .Q(\blk00000003/blk000000a1/sig00001552 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000000a1/blk000000a5 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/blk000000a1/sig00001551 ), + .Q(\blk00000003/sig0000011a ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000000a1/blk000000a4 ( + .A0(\blk00000003/blk000000a1/sig00001550 ), + .A1(\blk00000003/blk000000a1/sig0000154f ), + .A2(\blk00000003/blk000000a1/sig0000154f ), + .A3(\blk00000003/blk000000a1/sig0000154f ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(xn_re_0[0]), + .Q(\blk00000003/blk000000a1/sig00001551 ) + ); + VCC \blk00000003/blk000000a1/blk000000a3 ( + .P(\blk00000003/blk000000a1/sig00001550 ) + ); + GND \blk00000003/blk000000a1/blk000000a2 ( + .G(\blk00000003/blk000000a1/sig0000154f ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000010d/blk00000111 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/blk0000010d/sig00001567 ), + .Q(\blk00000003/sig0000012d ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000010d/blk00000110 ( + .A0(\blk00000003/blk0000010d/sig00001566 ), + .A1(\blk00000003/blk0000010d/sig00001565 ), + .A2(\blk00000003/blk0000010d/sig00001565 ), + .A3(\blk00000003/blk0000010d/sig00001565 ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(\blk00000003/sig00000132 ), + .Q(\blk00000003/blk0000010d/sig00001567 ) + ); + VCC \blk00000003/blk0000010d/blk0000010f ( + .P(\blk00000003/blk0000010d/sig00001566 ) + ); + GND \blk00000003/blk0000010d/blk0000010e ( + .G(\blk00000003/blk0000010d/sig00001565 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000112/blk00000116 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/blk00000112/sig0000156e ), + .Q(\blk00000003/sig0000008d ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000112/blk00000115 ( + .A0(\blk00000003/blk00000112/sig0000156d ), + .A1(\blk00000003/blk00000112/sig0000156c ), + .A2(\blk00000003/blk00000112/sig0000156c ), + .A3(\blk00000003/blk00000112/sig0000156c ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(\blk00000003/sig00000068 ), + .Q(\blk00000003/blk00000112/sig0000156e ) + ); + VCC \blk00000003/blk00000112/blk00000114 ( + .P(\blk00000003/blk00000112/sig0000156d ) + ); + GND \blk00000003/blk00000112/blk00000113 ( + .G(\blk00000003/blk00000112/sig0000156c ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000117/blk0000011b ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/blk00000117/sig00001575 ), + .Q(\blk00000003/sig00000166 ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000117/blk0000011a ( + .A0(\blk00000003/blk00000117/sig00001574 ), + .A1(\blk00000003/blk00000117/sig00001573 ), + .A2(\blk00000003/blk00000117/sig00001573 ), + .A3(\blk00000003/blk00000117/sig00001573 ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(NlwRenamedSig_OI_xn_index[5]), + .Q(\blk00000003/blk00000117/sig00001575 ) + ); + VCC \blk00000003/blk00000117/blk00000119 ( + .P(\blk00000003/blk00000117/sig00001574 ) + ); + GND \blk00000003/blk00000117/blk00000118 ( + .G(\blk00000003/blk00000117/sig00001573 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000011c/blk00000122 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/blk0000011c/sig0000157f ), + .Q(\blk00000003/sig0000016d ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000011c/blk00000121 ( + .A0(\blk00000003/blk0000011c/sig0000157d ), + .A1(\blk00000003/blk0000011c/sig0000157c ), + .A2(\blk00000003/blk0000011c/sig0000157c ), + .A3(\blk00000003/blk0000011c/sig0000157c ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(\blk00000003/sig00000167 ), + .Q(\blk00000003/blk0000011c/sig0000157f ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000011c/blk00000120 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/blk0000011c/sig0000157e ), + .Q(\blk00000003/sig0000016e ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000011c/blk0000011f ( + .A0(\blk00000003/blk0000011c/sig0000157d ), + .A1(\blk00000003/blk0000011c/sig0000157c ), + .A2(\blk00000003/blk0000011c/sig0000157c ), + .A3(\blk00000003/blk0000011c/sig0000157c ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(\blk00000003/sig00000168 ), + .Q(\blk00000003/blk0000011c/sig0000157e ) + ); + VCC \blk00000003/blk0000011c/blk0000011e ( + .P(\blk00000003/blk0000011c/sig0000157d ) + ); + GND \blk00000003/blk0000011c/blk0000011d ( + .G(\blk00000003/blk0000011c/sig0000157c ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000179/blk0000017d ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/blk00000179/sig00001586 ), + .Q(\blk00000003/sig0000029c ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000179/blk0000017c ( + .A0(\blk00000003/blk00000179/sig00001585 ), + .A1(\blk00000003/blk00000179/sig00001584 ), + .A2(\blk00000003/blk00000179/sig00001584 ), + .A3(\blk00000003/blk00000179/sig00001584 ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(\blk00000003/sig00000166 ), + .Q(\blk00000003/blk00000179/sig00001586 ) + ); + VCC \blk00000003/blk00000179/blk0000017b ( + .P(\blk00000003/blk00000179/sig00001585 ) + ); + GND \blk00000003/blk00000179/blk0000017a ( + .G(\blk00000003/blk00000179/sig00001584 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000017e/blk000001a0 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/blk0000017e/sig000015ba ), + .Q(\blk00000003/sig0000029d ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000017e/blk0000019f ( + .A0(\blk00000003/blk0000017e/sig000015aa ), + .A1(\blk00000003/blk0000017e/sig000015a9 ), + .A2(\blk00000003/blk0000017e/sig000015a9 ), + .A3(\blk00000003/blk0000017e/sig000015a9 ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(\blk00000003/sig0000010b ), + .Q(\blk00000003/blk0000017e/sig000015ba ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000017e/blk0000019e ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/blk0000017e/sig000015b9 ), + .Q(\blk00000003/sig0000029e ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000017e/blk0000019d ( + .A0(\blk00000003/blk0000017e/sig000015aa ), + .A1(\blk00000003/blk0000017e/sig000015a9 ), + .A2(\blk00000003/blk0000017e/sig000015a9 ), + .A3(\blk00000003/blk0000017e/sig000015a9 ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(\blk00000003/sig0000010c ), + .Q(\blk00000003/blk0000017e/sig000015b9 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000017e/blk0000019c ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/blk0000017e/sig000015b8 ), + .Q(\blk00000003/sig0000029f ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000017e/blk0000019b ( + .A0(\blk00000003/blk0000017e/sig000015aa ), + .A1(\blk00000003/blk0000017e/sig000015a9 ), + .A2(\blk00000003/blk0000017e/sig000015a9 ), + .A3(\blk00000003/blk0000017e/sig000015a9 ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(\blk00000003/sig0000010d ), + .Q(\blk00000003/blk0000017e/sig000015b8 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000017e/blk0000019a ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/blk0000017e/sig000015b7 ), + .Q(\blk00000003/sig000002a0 ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000017e/blk00000199 ( + .A0(\blk00000003/blk0000017e/sig000015aa ), + .A1(\blk00000003/blk0000017e/sig000015a9 ), + .A2(\blk00000003/blk0000017e/sig000015a9 ), + .A3(\blk00000003/blk0000017e/sig000015a9 ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(\blk00000003/sig0000010e ), + .Q(\blk00000003/blk0000017e/sig000015b7 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000017e/blk00000198 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/blk0000017e/sig000015b6 ), + .Q(\blk00000003/sig000002a1 ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000017e/blk00000197 ( + .A0(\blk00000003/blk0000017e/sig000015aa ), + .A1(\blk00000003/blk0000017e/sig000015a9 ), + .A2(\blk00000003/blk0000017e/sig000015a9 ), + .A3(\blk00000003/blk0000017e/sig000015a9 ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(\blk00000003/sig0000010f ), + .Q(\blk00000003/blk0000017e/sig000015b6 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000017e/blk00000196 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/blk0000017e/sig000015b5 ), + .Q(\blk00000003/sig000002a2 ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000017e/blk00000195 ( + .A0(\blk00000003/blk0000017e/sig000015aa ), + .A1(\blk00000003/blk0000017e/sig000015a9 ), + .A2(\blk00000003/blk0000017e/sig000015a9 ), + .A3(\blk00000003/blk0000017e/sig000015a9 ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(\blk00000003/sig00000110 ), + .Q(\blk00000003/blk0000017e/sig000015b5 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000017e/blk00000194 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/blk0000017e/sig000015b4 ), + .Q(\blk00000003/sig000002a3 ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000017e/blk00000193 ( + .A0(\blk00000003/blk0000017e/sig000015aa ), + .A1(\blk00000003/blk0000017e/sig000015a9 ), + .A2(\blk00000003/blk0000017e/sig000015a9 ), + .A3(\blk00000003/blk0000017e/sig000015a9 ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(\blk00000003/sig00000111 ), + .Q(\blk00000003/blk0000017e/sig000015b4 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000017e/blk00000192 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/blk0000017e/sig000015b3 ), + .Q(\blk00000003/sig000002a4 ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000017e/blk00000191 ( + .A0(\blk00000003/blk0000017e/sig000015aa ), + .A1(\blk00000003/blk0000017e/sig000015a9 ), + .A2(\blk00000003/blk0000017e/sig000015a9 ), + .A3(\blk00000003/blk0000017e/sig000015a9 ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(\blk00000003/sig00000112 ), + .Q(\blk00000003/blk0000017e/sig000015b3 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000017e/blk00000190 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/blk0000017e/sig000015b2 ), + .Q(\blk00000003/sig000002a5 ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000017e/blk0000018f ( + .A0(\blk00000003/blk0000017e/sig000015aa ), + .A1(\blk00000003/blk0000017e/sig000015a9 ), + .A2(\blk00000003/blk0000017e/sig000015a9 ), + .A3(\blk00000003/blk0000017e/sig000015a9 ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(\blk00000003/sig00000113 ), + .Q(\blk00000003/blk0000017e/sig000015b2 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000017e/blk0000018e ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/blk0000017e/sig000015b1 ), + .Q(\blk00000003/sig000002a6 ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000017e/blk0000018d ( + .A0(\blk00000003/blk0000017e/sig000015aa ), + .A1(\blk00000003/blk0000017e/sig000015a9 ), + .A2(\blk00000003/blk0000017e/sig000015a9 ), + .A3(\blk00000003/blk0000017e/sig000015a9 ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(\blk00000003/sig00000114 ), + .Q(\blk00000003/blk0000017e/sig000015b1 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000017e/blk0000018c ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/blk0000017e/sig000015b0 ), + .Q(\blk00000003/sig000002a7 ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000017e/blk0000018b ( + .A0(\blk00000003/blk0000017e/sig000015aa ), + .A1(\blk00000003/blk0000017e/sig000015a9 ), + .A2(\blk00000003/blk0000017e/sig000015a9 ), + .A3(\blk00000003/blk0000017e/sig000015a9 ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(\blk00000003/sig00000115 ), + .Q(\blk00000003/blk0000017e/sig000015b0 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000017e/blk0000018a ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/blk0000017e/sig000015af ), + .Q(\blk00000003/sig000002a8 ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000017e/blk00000189 ( + .A0(\blk00000003/blk0000017e/sig000015aa ), + .A1(\blk00000003/blk0000017e/sig000015a9 ), + .A2(\blk00000003/blk0000017e/sig000015a9 ), + .A3(\blk00000003/blk0000017e/sig000015a9 ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(\blk00000003/sig00000116 ), + .Q(\blk00000003/blk0000017e/sig000015af ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000017e/blk00000188 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/blk0000017e/sig000015ae ), + .Q(\blk00000003/sig000002a9 ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000017e/blk00000187 ( + .A0(\blk00000003/blk0000017e/sig000015aa ), + .A1(\blk00000003/blk0000017e/sig000015a9 ), + .A2(\blk00000003/blk0000017e/sig000015a9 ), + .A3(\blk00000003/blk0000017e/sig000015a9 ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(\blk00000003/sig00000117 ), + .Q(\blk00000003/blk0000017e/sig000015ae ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000017e/blk00000186 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/blk0000017e/sig000015ad ), + .Q(\blk00000003/sig000002aa ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000017e/blk00000185 ( + .A0(\blk00000003/blk0000017e/sig000015aa ), + .A1(\blk00000003/blk0000017e/sig000015a9 ), + .A2(\blk00000003/blk0000017e/sig000015a9 ), + .A3(\blk00000003/blk0000017e/sig000015a9 ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(\blk00000003/sig00000118 ), + .Q(\blk00000003/blk0000017e/sig000015ad ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000017e/blk00000184 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/blk0000017e/sig000015ac ), + .Q(\blk00000003/sig000002ab ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000017e/blk00000183 ( + .A0(\blk00000003/blk0000017e/sig000015aa ), + .A1(\blk00000003/blk0000017e/sig000015a9 ), + .A2(\blk00000003/blk0000017e/sig000015a9 ), + .A3(\blk00000003/blk0000017e/sig000015a9 ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(\blk00000003/sig00000119 ), + .Q(\blk00000003/blk0000017e/sig000015ac ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000017e/blk00000182 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/blk0000017e/sig000015ab ), + .Q(\blk00000003/sig000002ac ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000017e/blk00000181 ( + .A0(\blk00000003/blk0000017e/sig000015aa ), + .A1(\blk00000003/blk0000017e/sig000015a9 ), + .A2(\blk00000003/blk0000017e/sig000015a9 ), + .A3(\blk00000003/blk0000017e/sig000015a9 ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(\blk00000003/sig0000011a ), + .Q(\blk00000003/blk0000017e/sig000015ab ) + ); + VCC \blk00000003/blk0000017e/blk00000180 ( + .P(\blk00000003/blk0000017e/sig000015aa ) + ); + GND \blk00000003/blk0000017e/blk0000017f ( + .G(\blk00000003/blk0000017e/sig000015a9 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001a1/blk000001c3 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/blk000001a1/sig000015ee ), + .Q(\blk00000003/sig000002ad ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001a1/blk000001c2 ( + .A0(\blk00000003/blk000001a1/sig000015de ), + .A1(\blk00000003/blk000001a1/sig000015dd ), + .A2(\blk00000003/blk000001a1/sig000015dd ), + .A3(\blk00000003/blk000001a1/sig000015dd ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(\blk00000003/sig000000fb ), + .Q(\blk00000003/blk000001a1/sig000015ee ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001a1/blk000001c1 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/blk000001a1/sig000015ed ), + .Q(\blk00000003/sig000002ae ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001a1/blk000001c0 ( + .A0(\blk00000003/blk000001a1/sig000015de ), + .A1(\blk00000003/blk000001a1/sig000015dd ), + .A2(\blk00000003/blk000001a1/sig000015dd ), + .A3(\blk00000003/blk000001a1/sig000015dd ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(\blk00000003/sig000000fc ), + .Q(\blk00000003/blk000001a1/sig000015ed ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001a1/blk000001bf ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/blk000001a1/sig000015ec ), + .Q(\blk00000003/sig000002af ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001a1/blk000001be ( + .A0(\blk00000003/blk000001a1/sig000015de ), + .A1(\blk00000003/blk000001a1/sig000015dd ), + .A2(\blk00000003/blk000001a1/sig000015dd ), + .A3(\blk00000003/blk000001a1/sig000015dd ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(\blk00000003/sig000000fd ), + .Q(\blk00000003/blk000001a1/sig000015ec ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001a1/blk000001bd ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/blk000001a1/sig000015eb ), + .Q(\blk00000003/sig000002b0 ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001a1/blk000001bc ( + .A0(\blk00000003/blk000001a1/sig000015de ), + .A1(\blk00000003/blk000001a1/sig000015dd ), + .A2(\blk00000003/blk000001a1/sig000015dd ), + .A3(\blk00000003/blk000001a1/sig000015dd ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(\blk00000003/sig000000fe ), + .Q(\blk00000003/blk000001a1/sig000015eb ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001a1/blk000001bb ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/blk000001a1/sig000015ea ), + .Q(\blk00000003/sig000002b1 ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001a1/blk000001ba ( + .A0(\blk00000003/blk000001a1/sig000015de ), + .A1(\blk00000003/blk000001a1/sig000015dd ), + .A2(\blk00000003/blk000001a1/sig000015dd ), + .A3(\blk00000003/blk000001a1/sig000015dd ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(\blk00000003/sig000000ff ), + .Q(\blk00000003/blk000001a1/sig000015ea ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001a1/blk000001b9 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/blk000001a1/sig000015e9 ), + .Q(\blk00000003/sig000002b2 ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001a1/blk000001b8 ( + .A0(\blk00000003/blk000001a1/sig000015de ), + .A1(\blk00000003/blk000001a1/sig000015dd ), + .A2(\blk00000003/blk000001a1/sig000015dd ), + .A3(\blk00000003/blk000001a1/sig000015dd ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(\blk00000003/sig00000100 ), + .Q(\blk00000003/blk000001a1/sig000015e9 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001a1/blk000001b7 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/blk000001a1/sig000015e8 ), + .Q(\blk00000003/sig000002b3 ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001a1/blk000001b6 ( + .A0(\blk00000003/blk000001a1/sig000015de ), + .A1(\blk00000003/blk000001a1/sig000015dd ), + .A2(\blk00000003/blk000001a1/sig000015dd ), + .A3(\blk00000003/blk000001a1/sig000015dd ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(\blk00000003/sig00000101 ), + .Q(\blk00000003/blk000001a1/sig000015e8 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001a1/blk000001b5 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/blk000001a1/sig000015e7 ), + .Q(\blk00000003/sig000002b4 ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001a1/blk000001b4 ( + .A0(\blk00000003/blk000001a1/sig000015de ), + .A1(\blk00000003/blk000001a1/sig000015dd ), + .A2(\blk00000003/blk000001a1/sig000015dd ), + .A3(\blk00000003/blk000001a1/sig000015dd ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(\blk00000003/sig00000102 ), + .Q(\blk00000003/blk000001a1/sig000015e7 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001a1/blk000001b3 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/blk000001a1/sig000015e6 ), + .Q(\blk00000003/sig000002b5 ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001a1/blk000001b2 ( + .A0(\blk00000003/blk000001a1/sig000015de ), + .A1(\blk00000003/blk000001a1/sig000015dd ), + .A2(\blk00000003/blk000001a1/sig000015dd ), + .A3(\blk00000003/blk000001a1/sig000015dd ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(\blk00000003/sig00000103 ), + .Q(\blk00000003/blk000001a1/sig000015e6 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001a1/blk000001b1 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/blk000001a1/sig000015e5 ), + .Q(\blk00000003/sig000002b6 ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001a1/blk000001b0 ( + .A0(\blk00000003/blk000001a1/sig000015de ), + .A1(\blk00000003/blk000001a1/sig000015dd ), + .A2(\blk00000003/blk000001a1/sig000015dd ), + .A3(\blk00000003/blk000001a1/sig000015dd ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(\blk00000003/sig00000104 ), + .Q(\blk00000003/blk000001a1/sig000015e5 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001a1/blk000001af ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/blk000001a1/sig000015e4 ), + .Q(\blk00000003/sig000002b7 ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001a1/blk000001ae ( + .A0(\blk00000003/blk000001a1/sig000015de ), + .A1(\blk00000003/blk000001a1/sig000015dd ), + .A2(\blk00000003/blk000001a1/sig000015dd ), + .A3(\blk00000003/blk000001a1/sig000015dd ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(\blk00000003/sig00000105 ), + .Q(\blk00000003/blk000001a1/sig000015e4 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001a1/blk000001ad ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/blk000001a1/sig000015e3 ), + .Q(\blk00000003/sig000002b8 ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001a1/blk000001ac ( + .A0(\blk00000003/blk000001a1/sig000015de ), + .A1(\blk00000003/blk000001a1/sig000015dd ), + .A2(\blk00000003/blk000001a1/sig000015dd ), + .A3(\blk00000003/blk000001a1/sig000015dd ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(\blk00000003/sig00000106 ), + .Q(\blk00000003/blk000001a1/sig000015e3 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001a1/blk000001ab ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/blk000001a1/sig000015e2 ), + .Q(\blk00000003/sig000002b9 ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001a1/blk000001aa ( + .A0(\blk00000003/blk000001a1/sig000015de ), + .A1(\blk00000003/blk000001a1/sig000015dd ), + .A2(\blk00000003/blk000001a1/sig000015dd ), + .A3(\blk00000003/blk000001a1/sig000015dd ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(\blk00000003/sig00000107 ), + .Q(\blk00000003/blk000001a1/sig000015e2 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001a1/blk000001a9 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/blk000001a1/sig000015e1 ), + .Q(\blk00000003/sig000002ba ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001a1/blk000001a8 ( + .A0(\blk00000003/blk000001a1/sig000015de ), + .A1(\blk00000003/blk000001a1/sig000015dd ), + .A2(\blk00000003/blk000001a1/sig000015dd ), + .A3(\blk00000003/blk000001a1/sig000015dd ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(\blk00000003/sig00000108 ), + .Q(\blk00000003/blk000001a1/sig000015e1 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001a1/blk000001a7 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/blk000001a1/sig000015e0 ), + .Q(\blk00000003/sig000002bb ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001a1/blk000001a6 ( + .A0(\blk00000003/blk000001a1/sig000015de ), + .A1(\blk00000003/blk000001a1/sig000015dd ), + .A2(\blk00000003/blk000001a1/sig000015dd ), + .A3(\blk00000003/blk000001a1/sig000015dd ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(\blk00000003/sig00000109 ), + .Q(\blk00000003/blk000001a1/sig000015e0 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000001a1/blk000001a5 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/blk000001a1/sig000015df ), + .Q(\blk00000003/sig000002bc ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000001a1/blk000001a4 ( + .A0(\blk00000003/blk000001a1/sig000015de ), + .A1(\blk00000003/blk000001a1/sig000015dd ), + .A2(\blk00000003/blk000001a1/sig000015dd ), + .A3(\blk00000003/blk000001a1/sig000015dd ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(\blk00000003/sig0000010a ), + .Q(\blk00000003/blk000001a1/sig000015df ) + ); + VCC \blk00000003/blk000001a1/blk000001a3 ( + .P(\blk00000003/blk000001a1/sig000015de ) + ); + GND \blk00000003/blk000001a1/blk000001a2 ( + .G(\blk00000003/blk000001a1/sig000015dd ) + ); + FD #( + .INIT ( 1'b0 )) + \blk00000003/blk0000022b/blk00000293 ( + .C(clk), + .D(\blk00000003/blk0000022b/sig00001679 ), + .Q(\blk00000003/sig00000346 ) + ); + SRL16 #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000022b/blk00000292 ( + .A0(\blk00000003/blk0000022b/sig00001634 ), + .A1(\blk00000003/blk0000022b/sig00001634 ), + .A2(\blk00000003/blk0000022b/sig00001635 ), + .A3(\blk00000003/blk0000022b/sig00001635 ), + .CLK(clk), + .D(\blk00000003/blk0000022b/sig00001678 ), + .Q(\blk00000003/blk0000022b/sig00001679 ) + ); + SRLC16 #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000022b/blk00000291 ( + .A0(\blk00000003/blk0000022b/sig00001635 ), + .A1(\blk00000003/blk0000022b/sig00001635 ), + .A2(\blk00000003/blk0000022b/sig00001635 ), + .A3(\blk00000003/blk0000022b/sig00001635 ), + .CLK(clk), + .D(\blk00000003/sig00000301 ), + .Q(\NLW_blk00000003/blk0000022b/blk00000291_Q_UNCONNECTED ), + .Q15(\blk00000003/blk0000022b/sig00001678 ) + ); + FD #( + .INIT ( 1'b0 )) + \blk00000003/blk0000022b/blk00000290 ( + .C(clk), + .D(\blk00000003/blk0000022b/sig00001677 ), + .Q(\blk00000003/sig00000347 ) + ); + SRL16 #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000022b/blk0000028f ( + .A0(\blk00000003/blk0000022b/sig00001634 ), + .A1(\blk00000003/blk0000022b/sig00001634 ), + .A2(\blk00000003/blk0000022b/sig00001635 ), + .A3(\blk00000003/blk0000022b/sig00001635 ), + .CLK(clk), + .D(\blk00000003/blk0000022b/sig00001676 ), + .Q(\blk00000003/blk0000022b/sig00001677 ) + ); + SRLC16 #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000022b/blk0000028e ( + .A0(\blk00000003/blk0000022b/sig00001635 ), + .A1(\blk00000003/blk0000022b/sig00001635 ), + .A2(\blk00000003/blk0000022b/sig00001635 ), + .A3(\blk00000003/blk0000022b/sig00001635 ), + .CLK(clk), + .D(\blk00000003/sig00000300 ), + .Q(\NLW_blk00000003/blk0000022b/blk0000028e_Q_UNCONNECTED ), + .Q15(\blk00000003/blk0000022b/sig00001676 ) + ); + FD #( + .INIT ( 1'b0 )) + \blk00000003/blk0000022b/blk0000028d ( + .C(clk), + .D(\blk00000003/blk0000022b/sig00001675 ), + .Q(\blk00000003/sig00000348 ) + ); + SRL16 #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000022b/blk0000028c ( + .A0(\blk00000003/blk0000022b/sig00001634 ), + .A1(\blk00000003/blk0000022b/sig00001634 ), + .A2(\blk00000003/blk0000022b/sig00001635 ), + .A3(\blk00000003/blk0000022b/sig00001635 ), + .CLK(clk), + .D(\blk00000003/blk0000022b/sig00001674 ), + .Q(\blk00000003/blk0000022b/sig00001675 ) + ); + SRLC16 #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000022b/blk0000028b ( + .A0(\blk00000003/blk0000022b/sig00001635 ), + .A1(\blk00000003/blk0000022b/sig00001635 ), + .A2(\blk00000003/blk0000022b/sig00001635 ), + .A3(\blk00000003/blk0000022b/sig00001635 ), + .CLK(clk), + .D(\blk00000003/sig000002ff ), + .Q(\NLW_blk00000003/blk0000022b/blk0000028b_Q_UNCONNECTED ), + .Q15(\blk00000003/blk0000022b/sig00001674 ) + ); + FD #( + .INIT ( 1'b0 )) + \blk00000003/blk0000022b/blk0000028a ( + .C(clk), + .D(\blk00000003/blk0000022b/sig00001673 ), + .Q(\blk00000003/sig00000349 ) + ); + SRL16 #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000022b/blk00000289 ( + .A0(\blk00000003/blk0000022b/sig00001634 ), + .A1(\blk00000003/blk0000022b/sig00001634 ), + .A2(\blk00000003/blk0000022b/sig00001635 ), + .A3(\blk00000003/blk0000022b/sig00001635 ), + .CLK(clk), + .D(\blk00000003/blk0000022b/sig00001672 ), + .Q(\blk00000003/blk0000022b/sig00001673 ) + ); + SRLC16 #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000022b/blk00000288 ( + .A0(\blk00000003/blk0000022b/sig00001635 ), + .A1(\blk00000003/blk0000022b/sig00001635 ), + .A2(\blk00000003/blk0000022b/sig00001635 ), + .A3(\blk00000003/blk0000022b/sig00001635 ), + .CLK(clk), + .D(\blk00000003/sig000002fe ), + .Q(\NLW_blk00000003/blk0000022b/blk00000288_Q_UNCONNECTED ), + .Q15(\blk00000003/blk0000022b/sig00001672 ) + ); + FD #( + .INIT ( 1'b0 )) + \blk00000003/blk0000022b/blk00000287 ( + .C(clk), + .D(\blk00000003/blk0000022b/sig00001671 ), + .Q(\blk00000003/sig0000034a ) + ); + SRL16 #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000022b/blk00000286 ( + .A0(\blk00000003/blk0000022b/sig00001634 ), + .A1(\blk00000003/blk0000022b/sig00001634 ), + .A2(\blk00000003/blk0000022b/sig00001635 ), + .A3(\blk00000003/blk0000022b/sig00001635 ), + .CLK(clk), + .D(\blk00000003/blk0000022b/sig00001670 ), + .Q(\blk00000003/blk0000022b/sig00001671 ) + ); + SRLC16 #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000022b/blk00000285 ( + .A0(\blk00000003/blk0000022b/sig00001635 ), + .A1(\blk00000003/blk0000022b/sig00001635 ), + .A2(\blk00000003/blk0000022b/sig00001635 ), + .A3(\blk00000003/blk0000022b/sig00001635 ), + .CLK(clk), + .D(\blk00000003/sig000002fd ), + .Q(\NLW_blk00000003/blk0000022b/blk00000285_Q_UNCONNECTED ), + .Q15(\blk00000003/blk0000022b/sig00001670 ) + ); + FD #( + .INIT ( 1'b0 )) + \blk00000003/blk0000022b/blk00000284 ( + .C(clk), + .D(\blk00000003/blk0000022b/sig0000166f ), + .Q(\blk00000003/sig0000034b ) + ); + SRL16 #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000022b/blk00000283 ( + .A0(\blk00000003/blk0000022b/sig00001634 ), + .A1(\blk00000003/blk0000022b/sig00001634 ), + .A2(\blk00000003/blk0000022b/sig00001635 ), + .A3(\blk00000003/blk0000022b/sig00001635 ), + .CLK(clk), + .D(\blk00000003/blk0000022b/sig0000166e ), + .Q(\blk00000003/blk0000022b/sig0000166f ) + ); + SRLC16 #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000022b/blk00000282 ( + .A0(\blk00000003/blk0000022b/sig00001635 ), + .A1(\blk00000003/blk0000022b/sig00001635 ), + .A2(\blk00000003/blk0000022b/sig00001635 ), + .A3(\blk00000003/blk0000022b/sig00001635 ), + .CLK(clk), + .D(\blk00000003/sig000002fc ), + .Q(\NLW_blk00000003/blk0000022b/blk00000282_Q_UNCONNECTED ), + .Q15(\blk00000003/blk0000022b/sig0000166e ) + ); + FD #( + .INIT ( 1'b0 )) + \blk00000003/blk0000022b/blk00000281 ( + .C(clk), + .D(\blk00000003/blk0000022b/sig0000166d ), + .Q(\blk00000003/sig0000034c ) + ); + SRL16 #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000022b/blk00000280 ( + .A0(\blk00000003/blk0000022b/sig00001634 ), + .A1(\blk00000003/blk0000022b/sig00001634 ), + .A2(\blk00000003/blk0000022b/sig00001635 ), + .A3(\blk00000003/blk0000022b/sig00001635 ), + .CLK(clk), + .D(\blk00000003/blk0000022b/sig0000166c ), + .Q(\blk00000003/blk0000022b/sig0000166d ) + ); + SRLC16 #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000022b/blk0000027f ( + .A0(\blk00000003/blk0000022b/sig00001635 ), + .A1(\blk00000003/blk0000022b/sig00001635 ), + .A2(\blk00000003/blk0000022b/sig00001635 ), + .A3(\blk00000003/blk0000022b/sig00001635 ), + .CLK(clk), + .D(\blk00000003/sig000002fb ), + .Q(\NLW_blk00000003/blk0000022b/blk0000027f_Q_UNCONNECTED ), + .Q15(\blk00000003/blk0000022b/sig0000166c ) + ); + FD #( + .INIT ( 1'b0 )) + \blk00000003/blk0000022b/blk0000027e ( + .C(clk), + .D(\blk00000003/blk0000022b/sig0000166b ), + .Q(\blk00000003/sig0000034d ) + ); + SRL16 #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000022b/blk0000027d ( + .A0(\blk00000003/blk0000022b/sig00001634 ), + .A1(\blk00000003/blk0000022b/sig00001634 ), + .A2(\blk00000003/blk0000022b/sig00001635 ), + .A3(\blk00000003/blk0000022b/sig00001635 ), + .CLK(clk), + .D(\blk00000003/blk0000022b/sig0000166a ), + .Q(\blk00000003/blk0000022b/sig0000166b ) + ); + SRLC16 #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000022b/blk0000027c ( + .A0(\blk00000003/blk0000022b/sig00001635 ), + .A1(\blk00000003/blk0000022b/sig00001635 ), + .A2(\blk00000003/blk0000022b/sig00001635 ), + .A3(\blk00000003/blk0000022b/sig00001635 ), + .CLK(clk), + .D(\blk00000003/sig000002fa ), + .Q(\NLW_blk00000003/blk0000022b/blk0000027c_Q_UNCONNECTED ), + .Q15(\blk00000003/blk0000022b/sig0000166a ) + ); + FD #( + .INIT ( 1'b0 )) + \blk00000003/blk0000022b/blk0000027b ( + .C(clk), + .D(\blk00000003/blk0000022b/sig00001669 ), + .Q(\blk00000003/sig0000034e ) + ); + SRL16 #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000022b/blk0000027a ( + .A0(\blk00000003/blk0000022b/sig00001634 ), + .A1(\blk00000003/blk0000022b/sig00001634 ), + .A2(\blk00000003/blk0000022b/sig00001635 ), + .A3(\blk00000003/blk0000022b/sig00001635 ), + .CLK(clk), + .D(\blk00000003/blk0000022b/sig00001668 ), + .Q(\blk00000003/blk0000022b/sig00001669 ) + ); + SRLC16 #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000022b/blk00000279 ( + .A0(\blk00000003/blk0000022b/sig00001635 ), + .A1(\blk00000003/blk0000022b/sig00001635 ), + .A2(\blk00000003/blk0000022b/sig00001635 ), + .A3(\blk00000003/blk0000022b/sig00001635 ), + .CLK(clk), + .D(\blk00000003/sig000002f9 ), + .Q(\NLW_blk00000003/blk0000022b/blk00000279_Q_UNCONNECTED ), + .Q15(\blk00000003/blk0000022b/sig00001668 ) + ); + FD #( + .INIT ( 1'b0 )) + \blk00000003/blk0000022b/blk00000278 ( + .C(clk), + .D(\blk00000003/blk0000022b/sig00001667 ), + .Q(\blk00000003/sig0000034f ) + ); + SRL16 #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000022b/blk00000277 ( + .A0(\blk00000003/blk0000022b/sig00001634 ), + .A1(\blk00000003/blk0000022b/sig00001634 ), + .A2(\blk00000003/blk0000022b/sig00001635 ), + .A3(\blk00000003/blk0000022b/sig00001635 ), + .CLK(clk), + .D(\blk00000003/blk0000022b/sig00001666 ), + .Q(\blk00000003/blk0000022b/sig00001667 ) + ); + SRLC16 #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000022b/blk00000276 ( + .A0(\blk00000003/blk0000022b/sig00001635 ), + .A1(\blk00000003/blk0000022b/sig00001635 ), + .A2(\blk00000003/blk0000022b/sig00001635 ), + .A3(\blk00000003/blk0000022b/sig00001635 ), + .CLK(clk), + .D(\blk00000003/sig000002f8 ), + .Q(\NLW_blk00000003/blk0000022b/blk00000276_Q_UNCONNECTED ), + .Q15(\blk00000003/blk0000022b/sig00001666 ) + ); + FD #( + .INIT ( 1'b0 )) + \blk00000003/blk0000022b/blk00000275 ( + .C(clk), + .D(\blk00000003/blk0000022b/sig00001665 ), + .Q(\blk00000003/sig00000350 ) + ); + SRL16 #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000022b/blk00000274 ( + .A0(\blk00000003/blk0000022b/sig00001634 ), + .A1(\blk00000003/blk0000022b/sig00001634 ), + .A2(\blk00000003/blk0000022b/sig00001635 ), + .A3(\blk00000003/blk0000022b/sig00001635 ), + .CLK(clk), + .D(\blk00000003/blk0000022b/sig00001664 ), + .Q(\blk00000003/blk0000022b/sig00001665 ) + ); + SRLC16 #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000022b/blk00000273 ( + .A0(\blk00000003/blk0000022b/sig00001635 ), + .A1(\blk00000003/blk0000022b/sig00001635 ), + .A2(\blk00000003/blk0000022b/sig00001635 ), + .A3(\blk00000003/blk0000022b/sig00001635 ), + .CLK(clk), + .D(\blk00000003/sig000002f7 ), + .Q(\NLW_blk00000003/blk0000022b/blk00000273_Q_UNCONNECTED ), + .Q15(\blk00000003/blk0000022b/sig00001664 ) + ); + FD #( + .INIT ( 1'b0 )) + \blk00000003/blk0000022b/blk00000272 ( + .C(clk), + .D(\blk00000003/blk0000022b/sig00001663 ), + .Q(\blk00000003/sig00000351 ) + ); + SRL16 #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000022b/blk00000271 ( + .A0(\blk00000003/blk0000022b/sig00001634 ), + .A1(\blk00000003/blk0000022b/sig00001634 ), + .A2(\blk00000003/blk0000022b/sig00001635 ), + .A3(\blk00000003/blk0000022b/sig00001635 ), + .CLK(clk), + .D(\blk00000003/blk0000022b/sig00001662 ), + .Q(\blk00000003/blk0000022b/sig00001663 ) + ); + SRLC16 #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000022b/blk00000270 ( + .A0(\blk00000003/blk0000022b/sig00001635 ), + .A1(\blk00000003/blk0000022b/sig00001635 ), + .A2(\blk00000003/blk0000022b/sig00001635 ), + .A3(\blk00000003/blk0000022b/sig00001635 ), + .CLK(clk), + .D(\blk00000003/sig000002f6 ), + .Q(\NLW_blk00000003/blk0000022b/blk00000270_Q_UNCONNECTED ), + .Q15(\blk00000003/blk0000022b/sig00001662 ) + ); + FD #( + .INIT ( 1'b0 )) + \blk00000003/blk0000022b/blk0000026f ( + .C(clk), + .D(\blk00000003/blk0000022b/sig00001661 ), + .Q(\blk00000003/sig00000352 ) + ); + SRL16 #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000022b/blk0000026e ( + .A0(\blk00000003/blk0000022b/sig00001634 ), + .A1(\blk00000003/blk0000022b/sig00001634 ), + .A2(\blk00000003/blk0000022b/sig00001635 ), + .A3(\blk00000003/blk0000022b/sig00001635 ), + .CLK(clk), + .D(\blk00000003/blk0000022b/sig00001660 ), + .Q(\blk00000003/blk0000022b/sig00001661 ) + ); + SRLC16 #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000022b/blk0000026d ( + .A0(\blk00000003/blk0000022b/sig00001635 ), + .A1(\blk00000003/blk0000022b/sig00001635 ), + .A2(\blk00000003/blk0000022b/sig00001635 ), + .A3(\blk00000003/blk0000022b/sig00001635 ), + .CLK(clk), + .D(\blk00000003/sig000002f5 ), + .Q(\NLW_blk00000003/blk0000022b/blk0000026d_Q_UNCONNECTED ), + .Q15(\blk00000003/blk0000022b/sig00001660 ) + ); + FD #( + .INIT ( 1'b0 )) + \blk00000003/blk0000022b/blk0000026c ( + .C(clk), + .D(\blk00000003/blk0000022b/sig0000165f ), + .Q(\blk00000003/sig00000353 ) + ); + SRL16 #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000022b/blk0000026b ( + .A0(\blk00000003/blk0000022b/sig00001634 ), + .A1(\blk00000003/blk0000022b/sig00001634 ), + .A2(\blk00000003/blk0000022b/sig00001635 ), + .A3(\blk00000003/blk0000022b/sig00001635 ), + .CLK(clk), + .D(\blk00000003/blk0000022b/sig0000165e ), + .Q(\blk00000003/blk0000022b/sig0000165f ) + ); + SRLC16 #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000022b/blk0000026a ( + .A0(\blk00000003/blk0000022b/sig00001635 ), + .A1(\blk00000003/blk0000022b/sig00001635 ), + .A2(\blk00000003/blk0000022b/sig00001635 ), + .A3(\blk00000003/blk0000022b/sig00001635 ), + .CLK(clk), + .D(\blk00000003/sig000002f4 ), + .Q(\NLW_blk00000003/blk0000022b/blk0000026a_Q_UNCONNECTED ), + .Q15(\blk00000003/blk0000022b/sig0000165e ) + ); + FD #( + .INIT ( 1'b0 )) + \blk00000003/blk0000022b/blk00000269 ( + .C(clk), + .D(\blk00000003/blk0000022b/sig0000165d ), + .Q(\blk00000003/sig00000355 ) + ); + SRL16 #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000022b/blk00000268 ( + .A0(\blk00000003/blk0000022b/sig00001634 ), + .A1(\blk00000003/blk0000022b/sig00001634 ), + .A2(\blk00000003/blk0000022b/sig00001635 ), + .A3(\blk00000003/blk0000022b/sig00001635 ), + .CLK(clk), + .D(\blk00000003/blk0000022b/sig0000165c ), + .Q(\blk00000003/blk0000022b/sig0000165d ) + ); + SRLC16 #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000022b/blk00000267 ( + .A0(\blk00000003/blk0000022b/sig00001635 ), + .A1(\blk00000003/blk0000022b/sig00001635 ), + .A2(\blk00000003/blk0000022b/sig00001635 ), + .A3(\blk00000003/blk0000022b/sig00001635 ), + .CLK(clk), + .D(\blk00000003/sig000002f2 ), + .Q(\NLW_blk00000003/blk0000022b/blk00000267_Q_UNCONNECTED ), + .Q15(\blk00000003/blk0000022b/sig0000165c ) + ); + FD #( + .INIT ( 1'b0 )) + \blk00000003/blk0000022b/blk00000266 ( + .C(clk), + .D(\blk00000003/blk0000022b/sig0000165b ), + .Q(\blk00000003/sig00000356 ) + ); + SRL16 #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000022b/blk00000265 ( + .A0(\blk00000003/blk0000022b/sig00001634 ), + .A1(\blk00000003/blk0000022b/sig00001634 ), + .A2(\blk00000003/blk0000022b/sig00001635 ), + .A3(\blk00000003/blk0000022b/sig00001635 ), + .CLK(clk), + .D(\blk00000003/blk0000022b/sig0000165a ), + .Q(\blk00000003/blk0000022b/sig0000165b ) + ); + SRLC16 #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000022b/blk00000264 ( + .A0(\blk00000003/blk0000022b/sig00001635 ), + .A1(\blk00000003/blk0000022b/sig00001635 ), + .A2(\blk00000003/blk0000022b/sig00001635 ), + .A3(\blk00000003/blk0000022b/sig00001635 ), + .CLK(clk), + .D(\blk00000003/sig000002f1 ), + .Q(\NLW_blk00000003/blk0000022b/blk00000264_Q_UNCONNECTED ), + .Q15(\blk00000003/blk0000022b/sig0000165a ) + ); + FD #( + .INIT ( 1'b0 )) + \blk00000003/blk0000022b/blk00000263 ( + .C(clk), + .D(\blk00000003/blk0000022b/sig00001659 ), + .Q(\blk00000003/sig00000354 ) + ); + SRL16 #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000022b/blk00000262 ( + .A0(\blk00000003/blk0000022b/sig00001634 ), + .A1(\blk00000003/blk0000022b/sig00001634 ), + .A2(\blk00000003/blk0000022b/sig00001635 ), + .A3(\blk00000003/blk0000022b/sig00001635 ), + .CLK(clk), + .D(\blk00000003/blk0000022b/sig00001658 ), + .Q(\blk00000003/blk0000022b/sig00001659 ) + ); + SRLC16 #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000022b/blk00000261 ( + .A0(\blk00000003/blk0000022b/sig00001635 ), + .A1(\blk00000003/blk0000022b/sig00001635 ), + .A2(\blk00000003/blk0000022b/sig00001635 ), + .A3(\blk00000003/blk0000022b/sig00001635 ), + .CLK(clk), + .D(\blk00000003/sig000002f3 ), + .Q(\NLW_blk00000003/blk0000022b/blk00000261_Q_UNCONNECTED ), + .Q15(\blk00000003/blk0000022b/sig00001658 ) + ); + FD #( + .INIT ( 1'b0 )) + \blk00000003/blk0000022b/blk00000260 ( + .C(clk), + .D(\blk00000003/blk0000022b/sig00001657 ), + .Q(\blk00000003/sig00000357 ) + ); + SRL16 #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000022b/blk0000025f ( + .A0(\blk00000003/blk0000022b/sig00001634 ), + .A1(\blk00000003/blk0000022b/sig00001634 ), + .A2(\blk00000003/blk0000022b/sig00001635 ), + .A3(\blk00000003/blk0000022b/sig00001635 ), + .CLK(clk), + .D(\blk00000003/blk0000022b/sig00001656 ), + .Q(\blk00000003/blk0000022b/sig00001657 ) + ); + SRLC16 #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000022b/blk0000025e ( + .A0(\blk00000003/blk0000022b/sig00001635 ), + .A1(\blk00000003/blk0000022b/sig00001635 ), + .A2(\blk00000003/blk0000022b/sig00001635 ), + .A3(\blk00000003/blk0000022b/sig00001635 ), + .CLK(clk), + .D(\blk00000003/sig00000345 ), + .Q(\NLW_blk00000003/blk0000022b/blk0000025e_Q_UNCONNECTED ), + .Q15(\blk00000003/blk0000022b/sig00001656 ) + ); + FD #( + .INIT ( 1'b0 )) + \blk00000003/blk0000022b/blk0000025d ( + .C(clk), + .D(\blk00000003/blk0000022b/sig00001655 ), + .Q(\blk00000003/sig00000358 ) + ); + SRL16 #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000022b/blk0000025c ( + .A0(\blk00000003/blk0000022b/sig00001634 ), + .A1(\blk00000003/blk0000022b/sig00001634 ), + .A2(\blk00000003/blk0000022b/sig00001635 ), + .A3(\blk00000003/blk0000022b/sig00001635 ), + .CLK(clk), + .D(\blk00000003/blk0000022b/sig00001654 ), + .Q(\blk00000003/blk0000022b/sig00001655 ) + ); + SRLC16 #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000022b/blk0000025b ( + .A0(\blk00000003/blk0000022b/sig00001635 ), + .A1(\blk00000003/blk0000022b/sig00001635 ), + .A2(\blk00000003/blk0000022b/sig00001635 ), + .A3(\blk00000003/blk0000022b/sig00001635 ), + .CLK(clk), + .D(\blk00000003/sig00000344 ), + .Q(\NLW_blk00000003/blk0000022b/blk0000025b_Q_UNCONNECTED ), + .Q15(\blk00000003/blk0000022b/sig00001654 ) + ); + FD #( + .INIT ( 1'b0 )) + \blk00000003/blk0000022b/blk0000025a ( + .C(clk), + .D(\blk00000003/blk0000022b/sig00001653 ), + .Q(\blk00000003/sig00000359 ) + ); + SRL16 #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000022b/blk00000259 ( + .A0(\blk00000003/blk0000022b/sig00001634 ), + .A1(\blk00000003/blk0000022b/sig00001634 ), + .A2(\blk00000003/blk0000022b/sig00001635 ), + .A3(\blk00000003/blk0000022b/sig00001635 ), + .CLK(clk), + .D(\blk00000003/blk0000022b/sig00001652 ), + .Q(\blk00000003/blk0000022b/sig00001653 ) + ); + SRLC16 #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000022b/blk00000258 ( + .A0(\blk00000003/blk0000022b/sig00001635 ), + .A1(\blk00000003/blk0000022b/sig00001635 ), + .A2(\blk00000003/blk0000022b/sig00001635 ), + .A3(\blk00000003/blk0000022b/sig00001635 ), + .CLK(clk), + .D(\blk00000003/sig00000343 ), + .Q(\NLW_blk00000003/blk0000022b/blk00000258_Q_UNCONNECTED ), + .Q15(\blk00000003/blk0000022b/sig00001652 ) + ); + FD #( + .INIT ( 1'b0 )) + \blk00000003/blk0000022b/blk00000257 ( + .C(clk), + .D(\blk00000003/blk0000022b/sig00001651 ), + .Q(\blk00000003/sig0000035a ) + ); + SRL16 #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000022b/blk00000256 ( + .A0(\blk00000003/blk0000022b/sig00001634 ), + .A1(\blk00000003/blk0000022b/sig00001634 ), + .A2(\blk00000003/blk0000022b/sig00001635 ), + .A3(\blk00000003/blk0000022b/sig00001635 ), + .CLK(clk), + .D(\blk00000003/blk0000022b/sig00001650 ), + .Q(\blk00000003/blk0000022b/sig00001651 ) + ); + SRLC16 #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000022b/blk00000255 ( + .A0(\blk00000003/blk0000022b/sig00001635 ), + .A1(\blk00000003/blk0000022b/sig00001635 ), + .A2(\blk00000003/blk0000022b/sig00001635 ), + .A3(\blk00000003/blk0000022b/sig00001635 ), + .CLK(clk), + .D(\blk00000003/sig00000342 ), + .Q(\NLW_blk00000003/blk0000022b/blk00000255_Q_UNCONNECTED ), + .Q15(\blk00000003/blk0000022b/sig00001650 ) + ); + FD #( + .INIT ( 1'b0 )) + \blk00000003/blk0000022b/blk00000254 ( + .C(clk), + .D(\blk00000003/blk0000022b/sig0000164f ), + .Q(\blk00000003/sig0000035b ) + ); + SRL16 #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000022b/blk00000253 ( + .A0(\blk00000003/blk0000022b/sig00001634 ), + .A1(\blk00000003/blk0000022b/sig00001634 ), + .A2(\blk00000003/blk0000022b/sig00001635 ), + .A3(\blk00000003/blk0000022b/sig00001635 ), + .CLK(clk), + .D(\blk00000003/blk0000022b/sig0000164e ), + .Q(\blk00000003/blk0000022b/sig0000164f ) + ); + SRLC16 #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000022b/blk00000252 ( + .A0(\blk00000003/blk0000022b/sig00001635 ), + .A1(\blk00000003/blk0000022b/sig00001635 ), + .A2(\blk00000003/blk0000022b/sig00001635 ), + .A3(\blk00000003/blk0000022b/sig00001635 ), + .CLK(clk), + .D(\blk00000003/sig00000341 ), + .Q(\NLW_blk00000003/blk0000022b/blk00000252_Q_UNCONNECTED ), + .Q15(\blk00000003/blk0000022b/sig0000164e ) + ); + FD #( + .INIT ( 1'b0 )) + \blk00000003/blk0000022b/blk00000251 ( + .C(clk), + .D(\blk00000003/blk0000022b/sig0000164d ), + .Q(\blk00000003/sig0000035c ) + ); + SRL16 #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000022b/blk00000250 ( + .A0(\blk00000003/blk0000022b/sig00001634 ), + .A1(\blk00000003/blk0000022b/sig00001634 ), + .A2(\blk00000003/blk0000022b/sig00001635 ), + .A3(\blk00000003/blk0000022b/sig00001635 ), + .CLK(clk), + .D(\blk00000003/blk0000022b/sig0000164c ), + .Q(\blk00000003/blk0000022b/sig0000164d ) + ); + SRLC16 #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000022b/blk0000024f ( + .A0(\blk00000003/blk0000022b/sig00001635 ), + .A1(\blk00000003/blk0000022b/sig00001635 ), + .A2(\blk00000003/blk0000022b/sig00001635 ), + .A3(\blk00000003/blk0000022b/sig00001635 ), + .CLK(clk), + .D(\blk00000003/sig00000340 ), + .Q(\NLW_blk00000003/blk0000022b/blk0000024f_Q_UNCONNECTED ), + .Q15(\blk00000003/blk0000022b/sig0000164c ) + ); + FD #( + .INIT ( 1'b0 )) + \blk00000003/blk0000022b/blk0000024e ( + .C(clk), + .D(\blk00000003/blk0000022b/sig0000164b ), + .Q(\blk00000003/sig0000035d ) + ); + SRL16 #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000022b/blk0000024d ( + .A0(\blk00000003/blk0000022b/sig00001634 ), + .A1(\blk00000003/blk0000022b/sig00001634 ), + .A2(\blk00000003/blk0000022b/sig00001635 ), + .A3(\blk00000003/blk0000022b/sig00001635 ), + .CLK(clk), + .D(\blk00000003/blk0000022b/sig0000164a ), + .Q(\blk00000003/blk0000022b/sig0000164b ) + ); + SRLC16 #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000022b/blk0000024c ( + .A0(\blk00000003/blk0000022b/sig00001635 ), + .A1(\blk00000003/blk0000022b/sig00001635 ), + .A2(\blk00000003/blk0000022b/sig00001635 ), + .A3(\blk00000003/blk0000022b/sig00001635 ), + .CLK(clk), + .D(\blk00000003/sig0000033f ), + .Q(\NLW_blk00000003/blk0000022b/blk0000024c_Q_UNCONNECTED ), + .Q15(\blk00000003/blk0000022b/sig0000164a ) + ); + FD #( + .INIT ( 1'b0 )) + \blk00000003/blk0000022b/blk0000024b ( + .C(clk), + .D(\blk00000003/blk0000022b/sig00001649 ), + .Q(\blk00000003/sig0000035e ) + ); + SRL16 #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000022b/blk0000024a ( + .A0(\blk00000003/blk0000022b/sig00001634 ), + .A1(\blk00000003/blk0000022b/sig00001634 ), + .A2(\blk00000003/blk0000022b/sig00001635 ), + .A3(\blk00000003/blk0000022b/sig00001635 ), + .CLK(clk), + .D(\blk00000003/blk0000022b/sig00001648 ), + .Q(\blk00000003/blk0000022b/sig00001649 ) + ); + SRLC16 #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000022b/blk00000249 ( + .A0(\blk00000003/blk0000022b/sig00001635 ), + .A1(\blk00000003/blk0000022b/sig00001635 ), + .A2(\blk00000003/blk0000022b/sig00001635 ), + .A3(\blk00000003/blk0000022b/sig00001635 ), + .CLK(clk), + .D(\blk00000003/sig0000033e ), + .Q(\NLW_blk00000003/blk0000022b/blk00000249_Q_UNCONNECTED ), + .Q15(\blk00000003/blk0000022b/sig00001648 ) + ); + FD #( + .INIT ( 1'b0 )) + \blk00000003/blk0000022b/blk00000248 ( + .C(clk), + .D(\blk00000003/blk0000022b/sig00001647 ), + .Q(\blk00000003/sig0000035f ) + ); + SRL16 #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000022b/blk00000247 ( + .A0(\blk00000003/blk0000022b/sig00001634 ), + .A1(\blk00000003/blk0000022b/sig00001634 ), + .A2(\blk00000003/blk0000022b/sig00001635 ), + .A3(\blk00000003/blk0000022b/sig00001635 ), + .CLK(clk), + .D(\blk00000003/blk0000022b/sig00001646 ), + .Q(\blk00000003/blk0000022b/sig00001647 ) + ); + SRLC16 #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000022b/blk00000246 ( + .A0(\blk00000003/blk0000022b/sig00001635 ), + .A1(\blk00000003/blk0000022b/sig00001635 ), + .A2(\blk00000003/blk0000022b/sig00001635 ), + .A3(\blk00000003/blk0000022b/sig00001635 ), + .CLK(clk), + .D(\blk00000003/sig0000033d ), + .Q(\NLW_blk00000003/blk0000022b/blk00000246_Q_UNCONNECTED ), + .Q15(\blk00000003/blk0000022b/sig00001646 ) + ); + FD #( + .INIT ( 1'b0 )) + \blk00000003/blk0000022b/blk00000245 ( + .C(clk), + .D(\blk00000003/blk0000022b/sig00001645 ), + .Q(\blk00000003/sig00000360 ) + ); + SRL16 #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000022b/blk00000244 ( + .A0(\blk00000003/blk0000022b/sig00001634 ), + .A1(\blk00000003/blk0000022b/sig00001634 ), + .A2(\blk00000003/blk0000022b/sig00001635 ), + .A3(\blk00000003/blk0000022b/sig00001635 ), + .CLK(clk), + .D(\blk00000003/blk0000022b/sig00001644 ), + .Q(\blk00000003/blk0000022b/sig00001645 ) + ); + SRLC16 #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000022b/blk00000243 ( + .A0(\blk00000003/blk0000022b/sig00001635 ), + .A1(\blk00000003/blk0000022b/sig00001635 ), + .A2(\blk00000003/blk0000022b/sig00001635 ), + .A3(\blk00000003/blk0000022b/sig00001635 ), + .CLK(clk), + .D(\blk00000003/sig0000033c ), + .Q(\NLW_blk00000003/blk0000022b/blk00000243_Q_UNCONNECTED ), + .Q15(\blk00000003/blk0000022b/sig00001644 ) + ); + FD #( + .INIT ( 1'b0 )) + \blk00000003/blk0000022b/blk00000242 ( + .C(clk), + .D(\blk00000003/blk0000022b/sig00001643 ), + .Q(\blk00000003/sig00000361 ) + ); + SRL16 #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000022b/blk00000241 ( + .A0(\blk00000003/blk0000022b/sig00001634 ), + .A1(\blk00000003/blk0000022b/sig00001634 ), + .A2(\blk00000003/blk0000022b/sig00001635 ), + .A3(\blk00000003/blk0000022b/sig00001635 ), + .CLK(clk), + .D(\blk00000003/blk0000022b/sig00001642 ), + .Q(\blk00000003/blk0000022b/sig00001643 ) + ); + SRLC16 #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000022b/blk00000240 ( + .A0(\blk00000003/blk0000022b/sig00001635 ), + .A1(\blk00000003/blk0000022b/sig00001635 ), + .A2(\blk00000003/blk0000022b/sig00001635 ), + .A3(\blk00000003/blk0000022b/sig00001635 ), + .CLK(clk), + .D(\blk00000003/sig0000033b ), + .Q(\NLW_blk00000003/blk0000022b/blk00000240_Q_UNCONNECTED ), + .Q15(\blk00000003/blk0000022b/sig00001642 ) + ); + FD #( + .INIT ( 1'b0 )) + \blk00000003/blk0000022b/blk0000023f ( + .C(clk), + .D(\blk00000003/blk0000022b/sig00001641 ), + .Q(\blk00000003/sig00000362 ) + ); + SRL16 #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000022b/blk0000023e ( + .A0(\blk00000003/blk0000022b/sig00001634 ), + .A1(\blk00000003/blk0000022b/sig00001634 ), + .A2(\blk00000003/blk0000022b/sig00001635 ), + .A3(\blk00000003/blk0000022b/sig00001635 ), + .CLK(clk), + .D(\blk00000003/blk0000022b/sig00001640 ), + .Q(\blk00000003/blk0000022b/sig00001641 ) + ); + SRLC16 #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000022b/blk0000023d ( + .A0(\blk00000003/blk0000022b/sig00001635 ), + .A1(\blk00000003/blk0000022b/sig00001635 ), + .A2(\blk00000003/blk0000022b/sig00001635 ), + .A3(\blk00000003/blk0000022b/sig00001635 ), + .CLK(clk), + .D(\blk00000003/sig0000033a ), + .Q(\NLW_blk00000003/blk0000022b/blk0000023d_Q_UNCONNECTED ), + .Q15(\blk00000003/blk0000022b/sig00001640 ) + ); + FD #( + .INIT ( 1'b0 )) + \blk00000003/blk0000022b/blk0000023c ( + .C(clk), + .D(\blk00000003/blk0000022b/sig0000163f ), + .Q(\blk00000003/sig00000363 ) + ); + SRL16 #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000022b/blk0000023b ( + .A0(\blk00000003/blk0000022b/sig00001634 ), + .A1(\blk00000003/blk0000022b/sig00001634 ), + .A2(\blk00000003/blk0000022b/sig00001635 ), + .A3(\blk00000003/blk0000022b/sig00001635 ), + .CLK(clk), + .D(\blk00000003/blk0000022b/sig0000163e ), + .Q(\blk00000003/blk0000022b/sig0000163f ) + ); + SRLC16 #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000022b/blk0000023a ( + .A0(\blk00000003/blk0000022b/sig00001635 ), + .A1(\blk00000003/blk0000022b/sig00001635 ), + .A2(\blk00000003/blk0000022b/sig00001635 ), + .A3(\blk00000003/blk0000022b/sig00001635 ), + .CLK(clk), + .D(\blk00000003/sig00000339 ), + .Q(\NLW_blk00000003/blk0000022b/blk0000023a_Q_UNCONNECTED ), + .Q15(\blk00000003/blk0000022b/sig0000163e ) + ); + FD #( + .INIT ( 1'b0 )) + \blk00000003/blk0000022b/blk00000239 ( + .C(clk), + .D(\blk00000003/blk0000022b/sig0000163d ), + .Q(\blk00000003/sig00000364 ) + ); + SRL16 #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000022b/blk00000238 ( + .A0(\blk00000003/blk0000022b/sig00001634 ), + .A1(\blk00000003/blk0000022b/sig00001634 ), + .A2(\blk00000003/blk0000022b/sig00001635 ), + .A3(\blk00000003/blk0000022b/sig00001635 ), + .CLK(clk), + .D(\blk00000003/blk0000022b/sig0000163c ), + .Q(\blk00000003/blk0000022b/sig0000163d ) + ); + SRLC16 #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000022b/blk00000237 ( + .A0(\blk00000003/blk0000022b/sig00001635 ), + .A1(\blk00000003/blk0000022b/sig00001635 ), + .A2(\blk00000003/blk0000022b/sig00001635 ), + .A3(\blk00000003/blk0000022b/sig00001635 ), + .CLK(clk), + .D(\blk00000003/sig00000338 ), + .Q(\NLW_blk00000003/blk0000022b/blk00000237_Q_UNCONNECTED ), + .Q15(\blk00000003/blk0000022b/sig0000163c ) + ); + FD #( + .INIT ( 1'b0 )) + \blk00000003/blk0000022b/blk00000236 ( + .C(clk), + .D(\blk00000003/blk0000022b/sig0000163b ), + .Q(\blk00000003/sig00000366 ) + ); + SRL16 #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000022b/blk00000235 ( + .A0(\blk00000003/blk0000022b/sig00001634 ), + .A1(\blk00000003/blk0000022b/sig00001634 ), + .A2(\blk00000003/blk0000022b/sig00001635 ), + .A3(\blk00000003/blk0000022b/sig00001635 ), + .CLK(clk), + .D(\blk00000003/blk0000022b/sig0000163a ), + .Q(\blk00000003/blk0000022b/sig0000163b ) + ); + SRLC16 #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000022b/blk00000234 ( + .A0(\blk00000003/blk0000022b/sig00001635 ), + .A1(\blk00000003/blk0000022b/sig00001635 ), + .A2(\blk00000003/blk0000022b/sig00001635 ), + .A3(\blk00000003/blk0000022b/sig00001635 ), + .CLK(clk), + .D(\blk00000003/sig00000336 ), + .Q(\NLW_blk00000003/blk0000022b/blk00000234_Q_UNCONNECTED ), + .Q15(\blk00000003/blk0000022b/sig0000163a ) + ); + FD #( + .INIT ( 1'b0 )) + \blk00000003/blk0000022b/blk00000233 ( + .C(clk), + .D(\blk00000003/blk0000022b/sig00001639 ), + .Q(\blk00000003/sig00000367 ) + ); + SRL16 #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000022b/blk00000232 ( + .A0(\blk00000003/blk0000022b/sig00001634 ), + .A1(\blk00000003/blk0000022b/sig00001634 ), + .A2(\blk00000003/blk0000022b/sig00001635 ), + .A3(\blk00000003/blk0000022b/sig00001635 ), + .CLK(clk), + .D(\blk00000003/blk0000022b/sig00001638 ), + .Q(\blk00000003/blk0000022b/sig00001639 ) + ); + SRLC16 #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000022b/blk00000231 ( + .A0(\blk00000003/blk0000022b/sig00001635 ), + .A1(\blk00000003/blk0000022b/sig00001635 ), + .A2(\blk00000003/blk0000022b/sig00001635 ), + .A3(\blk00000003/blk0000022b/sig00001635 ), + .CLK(clk), + .D(\blk00000003/sig00000335 ), + .Q(\NLW_blk00000003/blk0000022b/blk00000231_Q_UNCONNECTED ), + .Q15(\blk00000003/blk0000022b/sig00001638 ) + ); + FD #( + .INIT ( 1'b0 )) + \blk00000003/blk0000022b/blk00000230 ( + .C(clk), + .D(\blk00000003/blk0000022b/sig00001637 ), + .Q(\blk00000003/sig00000365 ) + ); + SRL16 #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000022b/blk0000022f ( + .A0(\blk00000003/blk0000022b/sig00001634 ), + .A1(\blk00000003/blk0000022b/sig00001634 ), + .A2(\blk00000003/blk0000022b/sig00001635 ), + .A3(\blk00000003/blk0000022b/sig00001635 ), + .CLK(clk), + .D(\blk00000003/blk0000022b/sig00001636 ), + .Q(\blk00000003/blk0000022b/sig00001637 ) + ); + SRLC16 #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000022b/blk0000022e ( + .A0(\blk00000003/blk0000022b/sig00001635 ), + .A1(\blk00000003/blk0000022b/sig00001635 ), + .A2(\blk00000003/blk0000022b/sig00001635 ), + .A3(\blk00000003/blk0000022b/sig00001635 ), + .CLK(clk), + .D(\blk00000003/sig00000337 ), + .Q(\NLW_blk00000003/blk0000022b/blk0000022e_Q_UNCONNECTED ), + .Q15(\blk00000003/blk0000022b/sig00001636 ) + ); + VCC \blk00000003/blk0000022b/blk0000022d ( + .P(\blk00000003/blk0000022b/sig00001635 ) + ); + GND \blk00000003/blk0000022b/blk0000022c ( + .G(\blk00000003/blk0000022b/sig00001634 ) + ); + FD #( + .INIT ( 1'b0 )) + \blk00000003/blk0000038a/blk0000038f ( + .C(clk), + .D(\blk00000003/blk0000038a/sig00001680 ), + .Q(\blk00000003/sig000004a6 ) + ); + SRL16 #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000038a/blk0000038e ( + .A0(\blk00000003/blk0000038a/sig0000167e ), + .A1(\blk00000003/blk0000038a/sig0000167e ), + .A2(\blk00000003/blk0000038a/sig0000167d ), + .A3(\blk00000003/blk0000038a/sig0000167e ), + .CLK(clk), + .D(\blk00000003/blk0000038a/sig0000167f ), + .Q(\blk00000003/blk0000038a/sig00001680 ) + ); + SRLC16 #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000038a/blk0000038d ( + .A0(\blk00000003/blk0000038a/sig0000167e ), + .A1(\blk00000003/blk0000038a/sig0000167e ), + .A2(\blk00000003/blk0000038a/sig0000167e ), + .A3(\blk00000003/blk0000038a/sig0000167e ), + .CLK(clk), + .D(\blk00000003/sig00000274 ), + .Q(\NLW_blk00000003/blk0000038a/blk0000038d_Q_UNCONNECTED ), + .Q15(\blk00000003/blk0000038a/sig0000167f ) + ); + VCC \blk00000003/blk0000038a/blk0000038c ( + .P(\blk00000003/blk0000038a/sig0000167e ) + ); + GND \blk00000003/blk0000038a/blk0000038b ( + .G(\blk00000003/blk0000038a/sig0000167d ) + ); + FD #( + .INIT ( 1'b0 )) + \blk00000003/blk00000390/blk00000395 ( + .C(clk), + .D(\blk00000003/blk00000390/sig00001687 ), + .Q(\blk00000003/sig00000241 ) + ); + SRL16 #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000390/blk00000394 ( + .A0(\blk00000003/blk00000390/sig00001684 ), + .A1(\blk00000003/blk00000390/sig00001685 ), + .A2(\blk00000003/blk00000390/sig00001684 ), + .A3(\blk00000003/blk00000390/sig00001685 ), + .CLK(clk), + .D(\blk00000003/blk00000390/sig00001686 ), + .Q(\blk00000003/blk00000390/sig00001687 ) + ); + SRLC16 #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000390/blk00000393 ( + .A0(\blk00000003/blk00000390/sig00001685 ), + .A1(\blk00000003/blk00000390/sig00001685 ), + .A2(\blk00000003/blk00000390/sig00001685 ), + .A3(\blk00000003/blk00000390/sig00001685 ), + .CLK(clk), + .D(\blk00000003/sig0000029b ), + .Q(\NLW_blk00000003/blk00000390/blk00000393_Q_UNCONNECTED ), + .Q15(\blk00000003/blk00000390/sig00001686 ) + ); + VCC \blk00000003/blk00000390/blk00000392 ( + .P(\blk00000003/blk00000390/sig00001685 ) + ); + GND \blk00000003/blk00000390/blk00000391 ( + .G(\blk00000003/blk00000390/sig00001684 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000396/blk0000039a ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/blk00000396/sig0000168e ), + .Q(\blk00000003/sig000004a7 ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000396/blk00000399 ( + .A0(\blk00000003/blk00000396/sig0000168c ), + .A1(\blk00000003/blk00000396/sig0000168d ), + .A2(\blk00000003/blk00000396/sig0000168c ), + .A3(\blk00000003/blk00000396/sig0000168c ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(\blk00000003/sig00000244 ), + .Q(\blk00000003/blk00000396/sig0000168e ) + ); + VCC \blk00000003/blk00000396/blk00000398 ( + .P(\blk00000003/blk00000396/sig0000168d ) + ); + GND \blk00000003/blk00000396/blk00000397 ( + .G(\blk00000003/blk00000396/sig0000168c ) + ); + FD #( + .INIT ( 1'b0 )) + \blk00000003/blk0000039b/blk000003a0 ( + .C(clk), + .D(\blk00000003/blk0000039b/sig00001695 ), + .Q(\blk00000003/sig000004a8 ) + ); + SRL16 #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000039b/blk0000039f ( + .A0(\blk00000003/blk0000039b/sig00001693 ), + .A1(\blk00000003/blk0000039b/sig00001693 ), + .A2(\blk00000003/blk0000039b/sig00001692 ), + .A3(\blk00000003/blk0000039b/sig00001693 ), + .CLK(clk), + .D(\blk00000003/blk0000039b/sig00001694 ), + .Q(\blk00000003/blk0000039b/sig00001695 ) + ); + SRLC16 #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000039b/blk0000039e ( + .A0(\blk00000003/blk0000039b/sig00001693 ), + .A1(\blk00000003/blk0000039b/sig00001693 ), + .A2(\blk00000003/blk0000039b/sig00001693 ), + .A3(\blk00000003/blk0000039b/sig00001693 ), + .CLK(clk), + .D(\blk00000003/sig00000246 ), + .Q(\NLW_blk00000003/blk0000039b/blk0000039e_Q_UNCONNECTED ), + .Q15(\blk00000003/blk0000039b/sig00001694 ) + ); + VCC \blk00000003/blk0000039b/blk0000039d ( + .P(\blk00000003/blk0000039b/sig00001693 ) + ); + GND \blk00000003/blk0000039b/blk0000039c ( + .G(\blk00000003/blk0000039b/sig00001692 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000047e/blk00000481 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/blk0000047e/sig0000169b ), + .Q(\blk00000003/sig000005e2 ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000047e/blk00000480 ( + .A0(\blk00000003/blk0000047e/sig0000169a ), + .A1(\blk00000003/blk0000047e/sig0000169a ), + .A2(\blk00000003/blk0000047e/sig0000169a ), + .A3(\blk00000003/blk0000047e/sig0000169a ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(\blk00000003/sig000005e1 ), + .Q(\blk00000003/blk0000047e/sig0000169b ) + ); + GND \blk00000003/blk0000047e/blk0000047f ( + .G(\blk00000003/blk0000047e/sig0000169a ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000482/blk00000485 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/blk00000482/sig000016a1 ), + .Q(\blk00000003/sig000005e1 ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000482/blk00000484 ( + .A0(\blk00000003/blk00000482/sig000016a0 ), + .A1(\blk00000003/blk00000482/sig000016a0 ), + .A2(\blk00000003/blk00000482/sig000016a0 ), + .A3(\blk00000003/blk00000482/sig000016a0 ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(\blk00000003/sig000005bc ), + .Q(\blk00000003/blk00000482/sig000016a1 ) + ); + GND \blk00000003/blk00000482/blk00000483 ( + .G(\blk00000003/blk00000482/sig000016a0 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000486/blk00000489 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/blk00000486/sig000016a7 ), + .Q(\blk00000003/sig0000008b ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000486/blk00000488 ( + .A0(\blk00000003/blk00000486/sig000016a6 ), + .A1(\blk00000003/blk00000486/sig000016a6 ), + .A2(\blk00000003/blk00000486/sig000016a6 ), + .A3(\blk00000003/blk00000486/sig000016a6 ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(\blk00000003/sig00000079 ), + .Q(\blk00000003/blk00000486/sig000016a7 ) + ); + GND \blk00000003/blk00000486/blk00000487 ( + .G(\blk00000003/blk00000486/sig000016a6 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000048a/blk0000048d ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/blk0000048a/sig000016ad ), + .Q(\blk00000003/sig000005e3 ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000048a/blk0000048c ( + .A0(\blk00000003/blk0000048a/sig000016ac ), + .A1(\blk00000003/blk0000048a/sig000016ac ), + .A2(\blk00000003/blk0000048a/sig000016ac ), + .A3(\blk00000003/blk0000048a/sig000016ac ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(\blk00000003/sig00000067 ), + .Q(\blk00000003/blk0000048a/sig000016ad ) + ); + GND \blk00000003/blk0000048a/blk0000048b ( + .G(\blk00000003/blk0000048a/sig000016ac ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000048e/blk00000492 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/blk0000048e/sig000016b4 ), + .Q(\blk00000003/sig000005e4 ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000048e/blk00000491 ( + .A0(\blk00000003/blk0000048e/sig000016b2 ), + .A1(\blk00000003/blk0000048e/sig000016b3 ), + .A2(\blk00000003/blk0000048e/sig000016b3 ), + .A3(\blk00000003/blk0000048e/sig000016b3 ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(\blk00000003/sig000005e2 ), + .Q(\blk00000003/blk0000048e/sig000016b4 ) + ); + VCC \blk00000003/blk0000048e/blk00000490 ( + .P(\blk00000003/blk0000048e/sig000016b3 ) + ); + GND \blk00000003/blk0000048e/blk0000048f ( + .G(\blk00000003/blk0000048e/sig000016b2 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000493/blk000004b9 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/blk00000493/sig000016ee ), + .Q(\blk00000003/sig000001c3 ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000493/blk000004b8 ( + .A0(\blk00000003/blk00000493/sig000016db ), + .A1(\blk00000003/blk00000493/sig000016dc ), + .A2(\blk00000003/blk00000493/sig000016dc ), + .A3(\blk00000003/blk00000493/sig000016dc ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(\blk00000003/sig00000582 ), + .Q(\blk00000003/blk00000493/sig000016ee ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000493/blk000004b7 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/blk00000493/sig000016ed ), + .Q(\blk00000003/sig000001c4 ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000493/blk000004b6 ( + .A0(\blk00000003/blk00000493/sig000016db ), + .A1(\blk00000003/blk00000493/sig000016dc ), + .A2(\blk00000003/blk00000493/sig000016dc ), + .A3(\blk00000003/blk00000493/sig000016dc ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(\blk00000003/sig00000580 ), + .Q(\blk00000003/blk00000493/sig000016ed ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000493/blk000004b5 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/blk00000493/sig000016ec ), + .Q(\blk00000003/sig000001c5 ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000493/blk000004b4 ( + .A0(\blk00000003/blk00000493/sig000016db ), + .A1(\blk00000003/blk00000493/sig000016dc ), + .A2(\blk00000003/blk00000493/sig000016dc ), + .A3(\blk00000003/blk00000493/sig000016dc ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(\blk00000003/sig0000057e ), + .Q(\blk00000003/blk00000493/sig000016ec ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000493/blk000004b3 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/blk00000493/sig000016eb ), + .Q(\blk00000003/sig000001c6 ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000493/blk000004b2 ( + .A0(\blk00000003/blk00000493/sig000016db ), + .A1(\blk00000003/blk00000493/sig000016dc ), + .A2(\blk00000003/blk00000493/sig000016dc ), + .A3(\blk00000003/blk00000493/sig000016dc ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(\blk00000003/sig0000057c ), + .Q(\blk00000003/blk00000493/sig000016eb ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000493/blk000004b1 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/blk00000493/sig000016ea ), + .Q(\blk00000003/sig000001c7 ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000493/blk000004b0 ( + .A0(\blk00000003/blk00000493/sig000016db ), + .A1(\blk00000003/blk00000493/sig000016dc ), + .A2(\blk00000003/blk00000493/sig000016dc ), + .A3(\blk00000003/blk00000493/sig000016dc ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(\blk00000003/sig0000057a ), + .Q(\blk00000003/blk00000493/sig000016ea ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000493/blk000004af ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/blk00000493/sig000016e9 ), + .Q(\blk00000003/sig000001c8 ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000493/blk000004ae ( + .A0(\blk00000003/blk00000493/sig000016db ), + .A1(\blk00000003/blk00000493/sig000016dc ), + .A2(\blk00000003/blk00000493/sig000016dc ), + .A3(\blk00000003/blk00000493/sig000016dc ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(\blk00000003/sig00000578 ), + .Q(\blk00000003/blk00000493/sig000016e9 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000493/blk000004ad ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/blk00000493/sig000016e8 ), + .Q(\blk00000003/sig000001ca ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000493/blk000004ac ( + .A0(\blk00000003/blk00000493/sig000016db ), + .A1(\blk00000003/blk00000493/sig000016dc ), + .A2(\blk00000003/blk00000493/sig000016dc ), + .A3(\blk00000003/blk00000493/sig000016dc ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(\blk00000003/sig00000574 ), + .Q(\blk00000003/blk00000493/sig000016e8 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000493/blk000004ab ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/blk00000493/sig000016e7 ), + .Q(\blk00000003/sig000001cb ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000493/blk000004aa ( + .A0(\blk00000003/blk00000493/sig000016db ), + .A1(\blk00000003/blk00000493/sig000016dc ), + .A2(\blk00000003/blk00000493/sig000016dc ), + .A3(\blk00000003/blk00000493/sig000016dc ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(\blk00000003/sig00000572 ), + .Q(\blk00000003/blk00000493/sig000016e7 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000493/blk000004a9 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/blk00000493/sig000016e6 ), + .Q(\blk00000003/sig000001c9 ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000493/blk000004a8 ( + .A0(\blk00000003/blk00000493/sig000016db ), + .A1(\blk00000003/blk00000493/sig000016dc ), + .A2(\blk00000003/blk00000493/sig000016dc ), + .A3(\blk00000003/blk00000493/sig000016dc ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(\blk00000003/sig00000576 ), + .Q(\blk00000003/blk00000493/sig000016e6 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000493/blk000004a7 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/blk00000493/sig000016e5 ), + .Q(\blk00000003/sig000001cc ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000493/blk000004a6 ( + .A0(\blk00000003/blk00000493/sig000016db ), + .A1(\blk00000003/blk00000493/sig000016dc ), + .A2(\blk00000003/blk00000493/sig000016dc ), + .A3(\blk00000003/blk00000493/sig000016dc ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(\blk00000003/sig00000570 ), + .Q(\blk00000003/blk00000493/sig000016e5 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000493/blk000004a5 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/blk00000493/sig000016e4 ), + .Q(\blk00000003/sig000001cd ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000493/blk000004a4 ( + .A0(\blk00000003/blk00000493/sig000016db ), + .A1(\blk00000003/blk00000493/sig000016dc ), + .A2(\blk00000003/blk00000493/sig000016dc ), + .A3(\blk00000003/blk00000493/sig000016dc ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(\blk00000003/sig0000056e ), + .Q(\blk00000003/blk00000493/sig000016e4 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000493/blk000004a3 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/blk00000493/sig000016e3 ), + .Q(\blk00000003/sig000001ce ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000493/blk000004a2 ( + .A0(\blk00000003/blk00000493/sig000016db ), + .A1(\blk00000003/blk00000493/sig000016dc ), + .A2(\blk00000003/blk00000493/sig000016dc ), + .A3(\blk00000003/blk00000493/sig000016dc ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(\blk00000003/sig0000056c ), + .Q(\blk00000003/blk00000493/sig000016e3 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000493/blk000004a1 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/blk00000493/sig000016e2 ), + .Q(\blk00000003/sig000001cf ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000493/blk000004a0 ( + .A0(\blk00000003/blk00000493/sig000016db ), + .A1(\blk00000003/blk00000493/sig000016dc ), + .A2(\blk00000003/blk00000493/sig000016dc ), + .A3(\blk00000003/blk00000493/sig000016dc ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(\blk00000003/sig0000056a ), + .Q(\blk00000003/blk00000493/sig000016e2 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000493/blk0000049f ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/blk00000493/sig000016e1 ), + .Q(\blk00000003/sig000001d0 ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000493/blk0000049e ( + .A0(\blk00000003/blk00000493/sig000016db ), + .A1(\blk00000003/blk00000493/sig000016dc ), + .A2(\blk00000003/blk00000493/sig000016dc ), + .A3(\blk00000003/blk00000493/sig000016dc ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(\blk00000003/sig00000568 ), + .Q(\blk00000003/blk00000493/sig000016e1 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000493/blk0000049d ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/blk00000493/sig000016e0 ), + .Q(\blk00000003/sig000001d1 ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000493/blk0000049c ( + .A0(\blk00000003/blk00000493/sig000016db ), + .A1(\blk00000003/blk00000493/sig000016dc ), + .A2(\blk00000003/blk00000493/sig000016dc ), + .A3(\blk00000003/blk00000493/sig000016dc ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(\blk00000003/sig00000566 ), + .Q(\blk00000003/blk00000493/sig000016e0 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000493/blk0000049b ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/blk00000493/sig000016df ), + .Q(\blk00000003/sig000001d3 ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000493/blk0000049a ( + .A0(\blk00000003/blk00000493/sig000016db ), + .A1(\blk00000003/blk00000493/sig000016dc ), + .A2(\blk00000003/blk00000493/sig000016dc ), + .A3(\blk00000003/blk00000493/sig000016dc ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(\blk00000003/sig00000562 ), + .Q(\blk00000003/blk00000493/sig000016df ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000493/blk00000499 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/blk00000493/sig000016de ), + .Q(\blk00000003/sig000001d4 ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000493/blk00000498 ( + .A0(\blk00000003/blk00000493/sig000016db ), + .A1(\blk00000003/blk00000493/sig000016dc ), + .A2(\blk00000003/blk00000493/sig000016dc ), + .A3(\blk00000003/blk00000493/sig000016dc ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(\blk00000003/sig00000560 ), + .Q(\blk00000003/blk00000493/sig000016de ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000493/blk00000497 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/blk00000493/sig000016dd ), + .Q(\blk00000003/sig000001d2 ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000493/blk00000496 ( + .A0(\blk00000003/blk00000493/sig000016db ), + .A1(\blk00000003/blk00000493/sig000016dc ), + .A2(\blk00000003/blk00000493/sig000016dc ), + .A3(\blk00000003/blk00000493/sig000016dc ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(\blk00000003/sig00000564 ), + .Q(\blk00000003/blk00000493/sig000016dd ) + ); + VCC \blk00000003/blk00000493/blk00000495 ( + .P(\blk00000003/blk00000493/sig000016dc ) + ); + GND \blk00000003/blk00000493/blk00000494 ( + .G(\blk00000003/blk00000493/sig000016db ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004ba/blk000004e0 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/blk000004ba/sig00001728 ), + .Q(\blk00000003/sig000005f7 ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000004ba/blk000004df ( + .A0(\blk00000003/blk000004ba/sig00001715 ), + .A1(\blk00000003/blk000004ba/sig00001716 ), + .A2(\blk00000003/blk000004ba/sig00001716 ), + .A3(\blk00000003/blk000004ba/sig00001716 ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(\blk00000003/sig000005e5 ), + .Q(\blk00000003/blk000004ba/sig00001728 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004ba/blk000004de ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/blk000004ba/sig00001727 ), + .Q(\blk00000003/sig000005f8 ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000004ba/blk000004dd ( + .A0(\blk00000003/blk000004ba/sig00001715 ), + .A1(\blk00000003/blk000004ba/sig00001716 ), + .A2(\blk00000003/blk000004ba/sig00001716 ), + .A3(\blk00000003/blk000004ba/sig00001716 ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(\blk00000003/sig000005e6 ), + .Q(\blk00000003/blk000004ba/sig00001727 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004ba/blk000004dc ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/blk000004ba/sig00001726 ), + .Q(\blk00000003/sig000005f9 ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000004ba/blk000004db ( + .A0(\blk00000003/blk000004ba/sig00001715 ), + .A1(\blk00000003/blk000004ba/sig00001716 ), + .A2(\blk00000003/blk000004ba/sig00001716 ), + .A3(\blk00000003/blk000004ba/sig00001716 ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(\blk00000003/sig000005e7 ), + .Q(\blk00000003/blk000004ba/sig00001726 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004ba/blk000004da ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/blk000004ba/sig00001725 ), + .Q(\blk00000003/sig000005fa ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000004ba/blk000004d9 ( + .A0(\blk00000003/blk000004ba/sig00001715 ), + .A1(\blk00000003/blk000004ba/sig00001716 ), + .A2(\blk00000003/blk000004ba/sig00001716 ), + .A3(\blk00000003/blk000004ba/sig00001716 ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(\blk00000003/sig000005e8 ), + .Q(\blk00000003/blk000004ba/sig00001725 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004ba/blk000004d8 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/blk000004ba/sig00001724 ), + .Q(\blk00000003/sig000005fb ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000004ba/blk000004d7 ( + .A0(\blk00000003/blk000004ba/sig00001715 ), + .A1(\blk00000003/blk000004ba/sig00001716 ), + .A2(\blk00000003/blk000004ba/sig00001716 ), + .A3(\blk00000003/blk000004ba/sig00001716 ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(\blk00000003/sig000005e9 ), + .Q(\blk00000003/blk000004ba/sig00001724 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004ba/blk000004d6 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/blk000004ba/sig00001723 ), + .Q(\blk00000003/sig000005fc ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000004ba/blk000004d5 ( + .A0(\blk00000003/blk000004ba/sig00001715 ), + .A1(\blk00000003/blk000004ba/sig00001716 ), + .A2(\blk00000003/blk000004ba/sig00001716 ), + .A3(\blk00000003/blk000004ba/sig00001716 ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(\blk00000003/sig000005ea ), + .Q(\blk00000003/blk000004ba/sig00001723 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004ba/blk000004d4 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/blk000004ba/sig00001722 ), + .Q(\blk00000003/sig000005fe ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000004ba/blk000004d3 ( + .A0(\blk00000003/blk000004ba/sig00001715 ), + .A1(\blk00000003/blk000004ba/sig00001716 ), + .A2(\blk00000003/blk000004ba/sig00001716 ), + .A3(\blk00000003/blk000004ba/sig00001716 ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(\blk00000003/sig000005ec ), + .Q(\blk00000003/blk000004ba/sig00001722 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004ba/blk000004d2 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/blk000004ba/sig00001721 ), + .Q(\blk00000003/sig000005ff ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000004ba/blk000004d1 ( + .A0(\blk00000003/blk000004ba/sig00001715 ), + .A1(\blk00000003/blk000004ba/sig00001716 ), + .A2(\blk00000003/blk000004ba/sig00001716 ), + .A3(\blk00000003/blk000004ba/sig00001716 ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(\blk00000003/sig000005ed ), + .Q(\blk00000003/blk000004ba/sig00001721 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004ba/blk000004d0 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/blk000004ba/sig00001720 ), + .Q(\blk00000003/sig000005fd ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000004ba/blk000004cf ( + .A0(\blk00000003/blk000004ba/sig00001715 ), + .A1(\blk00000003/blk000004ba/sig00001716 ), + .A2(\blk00000003/blk000004ba/sig00001716 ), + .A3(\blk00000003/blk000004ba/sig00001716 ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(\blk00000003/sig000005eb ), + .Q(\blk00000003/blk000004ba/sig00001720 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004ba/blk000004ce ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/blk000004ba/sig0000171f ), + .Q(\blk00000003/sig00000600 ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000004ba/blk000004cd ( + .A0(\blk00000003/blk000004ba/sig00001715 ), + .A1(\blk00000003/blk000004ba/sig00001716 ), + .A2(\blk00000003/blk000004ba/sig00001716 ), + .A3(\blk00000003/blk000004ba/sig00001716 ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(\blk00000003/sig000005ee ), + .Q(\blk00000003/blk000004ba/sig0000171f ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004ba/blk000004cc ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/blk000004ba/sig0000171e ), + .Q(\blk00000003/sig00000601 ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000004ba/blk000004cb ( + .A0(\blk00000003/blk000004ba/sig00001715 ), + .A1(\blk00000003/blk000004ba/sig00001716 ), + .A2(\blk00000003/blk000004ba/sig00001716 ), + .A3(\blk00000003/blk000004ba/sig00001716 ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(\blk00000003/sig000005ef ), + .Q(\blk00000003/blk000004ba/sig0000171e ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004ba/blk000004ca ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/blk000004ba/sig0000171d ), + .Q(\blk00000003/sig00000602 ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000004ba/blk000004c9 ( + .A0(\blk00000003/blk000004ba/sig00001715 ), + .A1(\blk00000003/blk000004ba/sig00001716 ), + .A2(\blk00000003/blk000004ba/sig00001716 ), + .A3(\blk00000003/blk000004ba/sig00001716 ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(\blk00000003/sig000005f0 ), + .Q(\blk00000003/blk000004ba/sig0000171d ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004ba/blk000004c8 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/blk000004ba/sig0000171c ), + .Q(\blk00000003/sig00000603 ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000004ba/blk000004c7 ( + .A0(\blk00000003/blk000004ba/sig00001715 ), + .A1(\blk00000003/blk000004ba/sig00001716 ), + .A2(\blk00000003/blk000004ba/sig00001716 ), + .A3(\blk00000003/blk000004ba/sig00001716 ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(\blk00000003/sig000005f1 ), + .Q(\blk00000003/blk000004ba/sig0000171c ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004ba/blk000004c6 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/blk000004ba/sig0000171b ), + .Q(\blk00000003/sig00000604 ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000004ba/blk000004c5 ( + .A0(\blk00000003/blk000004ba/sig00001715 ), + .A1(\blk00000003/blk000004ba/sig00001716 ), + .A2(\blk00000003/blk000004ba/sig00001716 ), + .A3(\blk00000003/blk000004ba/sig00001716 ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(\blk00000003/sig000005f2 ), + .Q(\blk00000003/blk000004ba/sig0000171b ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004ba/blk000004c4 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/blk000004ba/sig0000171a ), + .Q(\blk00000003/sig00000605 ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000004ba/blk000004c3 ( + .A0(\blk00000003/blk000004ba/sig00001715 ), + .A1(\blk00000003/blk000004ba/sig00001716 ), + .A2(\blk00000003/blk000004ba/sig00001716 ), + .A3(\blk00000003/blk000004ba/sig00001716 ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(\blk00000003/sig000005f3 ), + .Q(\blk00000003/blk000004ba/sig0000171a ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004ba/blk000004c2 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/blk000004ba/sig00001719 ), + .Q(\blk00000003/sig00000607 ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000004ba/blk000004c1 ( + .A0(\blk00000003/blk000004ba/sig00001715 ), + .A1(\blk00000003/blk000004ba/sig00001716 ), + .A2(\blk00000003/blk000004ba/sig00001716 ), + .A3(\blk00000003/blk000004ba/sig00001716 ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(\blk00000003/sig000005f5 ), + .Q(\blk00000003/blk000004ba/sig00001719 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004ba/blk000004c0 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/blk000004ba/sig00001718 ), + .Q(\blk00000003/sig00000608 ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000004ba/blk000004bf ( + .A0(\blk00000003/blk000004ba/sig00001715 ), + .A1(\blk00000003/blk000004ba/sig00001716 ), + .A2(\blk00000003/blk000004ba/sig00001716 ), + .A3(\blk00000003/blk000004ba/sig00001716 ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(\blk00000003/sig000005f6 ), + .Q(\blk00000003/blk000004ba/sig00001718 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004ba/blk000004be ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/blk000004ba/sig00001717 ), + .Q(\blk00000003/sig00000606 ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000004ba/blk000004bd ( + .A0(\blk00000003/blk000004ba/sig00001715 ), + .A1(\blk00000003/blk000004ba/sig00001716 ), + .A2(\blk00000003/blk000004ba/sig00001716 ), + .A3(\blk00000003/blk000004ba/sig00001716 ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(\blk00000003/sig000005f4 ), + .Q(\blk00000003/blk000004ba/sig00001717 ) + ); + VCC \blk00000003/blk000004ba/blk000004bc ( + .P(\blk00000003/blk000004ba/sig00001716 ) + ); + GND \blk00000003/blk000004ba/blk000004bb ( + .G(\blk00000003/blk000004ba/sig00001715 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004e1/blk00000507 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/blk000004e1/sig00001762 ), + .Q(\blk00000003/sig00000609 ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000004e1/blk00000506 ( + .A0(\blk00000003/blk000004e1/sig0000174f ), + .A1(\blk00000003/blk000004e1/sig00001750 ), + .A2(\blk00000003/blk000004e1/sig00001750 ), + .A3(\blk00000003/blk000004e1/sig00001750 ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(\blk00000003/sig000005cf ), + .Q(\blk00000003/blk000004e1/sig00001762 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004e1/blk00000505 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/blk000004e1/sig00001761 ), + .Q(\blk00000003/sig0000060a ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000004e1/blk00000504 ( + .A0(\blk00000003/blk000004e1/sig0000174f ), + .A1(\blk00000003/blk000004e1/sig00001750 ), + .A2(\blk00000003/blk000004e1/sig00001750 ), + .A3(\blk00000003/blk000004e1/sig00001750 ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(\blk00000003/sig000005d0 ), + .Q(\blk00000003/blk000004e1/sig00001761 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004e1/blk00000503 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/blk000004e1/sig00001760 ), + .Q(\blk00000003/sig0000060b ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000004e1/blk00000502 ( + .A0(\blk00000003/blk000004e1/sig0000174f ), + .A1(\blk00000003/blk000004e1/sig00001750 ), + .A2(\blk00000003/blk000004e1/sig00001750 ), + .A3(\blk00000003/blk000004e1/sig00001750 ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(\blk00000003/sig000005d1 ), + .Q(\blk00000003/blk000004e1/sig00001760 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004e1/blk00000501 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/blk000004e1/sig0000175f ), + .Q(\blk00000003/sig0000060c ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000004e1/blk00000500 ( + .A0(\blk00000003/blk000004e1/sig0000174f ), + .A1(\blk00000003/blk000004e1/sig00001750 ), + .A2(\blk00000003/blk000004e1/sig00001750 ), + .A3(\blk00000003/blk000004e1/sig00001750 ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(\blk00000003/sig000005d2 ), + .Q(\blk00000003/blk000004e1/sig0000175f ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004e1/blk000004ff ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/blk000004e1/sig0000175e ), + .Q(\blk00000003/sig0000060d ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000004e1/blk000004fe ( + .A0(\blk00000003/blk000004e1/sig0000174f ), + .A1(\blk00000003/blk000004e1/sig00001750 ), + .A2(\blk00000003/blk000004e1/sig00001750 ), + .A3(\blk00000003/blk000004e1/sig00001750 ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(\blk00000003/sig000005d3 ), + .Q(\blk00000003/blk000004e1/sig0000175e ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004e1/blk000004fd ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/blk000004e1/sig0000175d ), + .Q(\blk00000003/sig0000060e ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000004e1/blk000004fc ( + .A0(\blk00000003/blk000004e1/sig0000174f ), + .A1(\blk00000003/blk000004e1/sig00001750 ), + .A2(\blk00000003/blk000004e1/sig00001750 ), + .A3(\blk00000003/blk000004e1/sig00001750 ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(\blk00000003/sig000005d4 ), + .Q(\blk00000003/blk000004e1/sig0000175d ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004e1/blk000004fb ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/blk000004e1/sig0000175c ), + .Q(\blk00000003/sig00000610 ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000004e1/blk000004fa ( + .A0(\blk00000003/blk000004e1/sig0000174f ), + .A1(\blk00000003/blk000004e1/sig00001750 ), + .A2(\blk00000003/blk000004e1/sig00001750 ), + .A3(\blk00000003/blk000004e1/sig00001750 ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(\blk00000003/sig000005d6 ), + .Q(\blk00000003/blk000004e1/sig0000175c ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004e1/blk000004f9 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/blk000004e1/sig0000175b ), + .Q(\blk00000003/sig00000611 ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000004e1/blk000004f8 ( + .A0(\blk00000003/blk000004e1/sig0000174f ), + .A1(\blk00000003/blk000004e1/sig00001750 ), + .A2(\blk00000003/blk000004e1/sig00001750 ), + .A3(\blk00000003/blk000004e1/sig00001750 ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(\blk00000003/sig000005d7 ), + .Q(\blk00000003/blk000004e1/sig0000175b ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004e1/blk000004f7 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/blk000004e1/sig0000175a ), + .Q(\blk00000003/sig0000060f ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000004e1/blk000004f6 ( + .A0(\blk00000003/blk000004e1/sig0000174f ), + .A1(\blk00000003/blk000004e1/sig00001750 ), + .A2(\blk00000003/blk000004e1/sig00001750 ), + .A3(\blk00000003/blk000004e1/sig00001750 ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(\blk00000003/sig000005d5 ), + .Q(\blk00000003/blk000004e1/sig0000175a ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004e1/blk000004f5 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/blk000004e1/sig00001759 ), + .Q(\blk00000003/sig00000612 ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000004e1/blk000004f4 ( + .A0(\blk00000003/blk000004e1/sig0000174f ), + .A1(\blk00000003/blk000004e1/sig00001750 ), + .A2(\blk00000003/blk000004e1/sig00001750 ), + .A3(\blk00000003/blk000004e1/sig00001750 ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(\blk00000003/sig000005d8 ), + .Q(\blk00000003/blk000004e1/sig00001759 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004e1/blk000004f3 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/blk000004e1/sig00001758 ), + .Q(\blk00000003/sig00000613 ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000004e1/blk000004f2 ( + .A0(\blk00000003/blk000004e1/sig0000174f ), + .A1(\blk00000003/blk000004e1/sig00001750 ), + .A2(\blk00000003/blk000004e1/sig00001750 ), + .A3(\blk00000003/blk000004e1/sig00001750 ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(\blk00000003/sig000005d9 ), + .Q(\blk00000003/blk000004e1/sig00001758 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004e1/blk000004f1 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/blk000004e1/sig00001757 ), + .Q(\blk00000003/sig00000614 ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000004e1/blk000004f0 ( + .A0(\blk00000003/blk000004e1/sig0000174f ), + .A1(\blk00000003/blk000004e1/sig00001750 ), + .A2(\blk00000003/blk000004e1/sig00001750 ), + .A3(\blk00000003/blk000004e1/sig00001750 ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(\blk00000003/sig000005da ), + .Q(\blk00000003/blk000004e1/sig00001757 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004e1/blk000004ef ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/blk000004e1/sig00001756 ), + .Q(\blk00000003/sig00000615 ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000004e1/blk000004ee ( + .A0(\blk00000003/blk000004e1/sig0000174f ), + .A1(\blk00000003/blk000004e1/sig00001750 ), + .A2(\blk00000003/blk000004e1/sig00001750 ), + .A3(\blk00000003/blk000004e1/sig00001750 ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(\blk00000003/sig000005db ), + .Q(\blk00000003/blk000004e1/sig00001756 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004e1/blk000004ed ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/blk000004e1/sig00001755 ), + .Q(\blk00000003/sig00000616 ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000004e1/blk000004ec ( + .A0(\blk00000003/blk000004e1/sig0000174f ), + .A1(\blk00000003/blk000004e1/sig00001750 ), + .A2(\blk00000003/blk000004e1/sig00001750 ), + .A3(\blk00000003/blk000004e1/sig00001750 ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(\blk00000003/sig000005dc ), + .Q(\blk00000003/blk000004e1/sig00001755 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004e1/blk000004eb ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/blk000004e1/sig00001754 ), + .Q(\blk00000003/sig00000617 ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000004e1/blk000004ea ( + .A0(\blk00000003/blk000004e1/sig0000174f ), + .A1(\blk00000003/blk000004e1/sig00001750 ), + .A2(\blk00000003/blk000004e1/sig00001750 ), + .A3(\blk00000003/blk000004e1/sig00001750 ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(\blk00000003/sig000005dd ), + .Q(\blk00000003/blk000004e1/sig00001754 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004e1/blk000004e9 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/blk000004e1/sig00001753 ), + .Q(\blk00000003/sig00000619 ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000004e1/blk000004e8 ( + .A0(\blk00000003/blk000004e1/sig0000174f ), + .A1(\blk00000003/blk000004e1/sig00001750 ), + .A2(\blk00000003/blk000004e1/sig00001750 ), + .A3(\blk00000003/blk000004e1/sig00001750 ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(\blk00000003/sig000005df ), + .Q(\blk00000003/blk000004e1/sig00001753 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004e1/blk000004e7 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/blk000004e1/sig00001752 ), + .Q(\blk00000003/sig0000061a ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000004e1/blk000004e6 ( + .A0(\blk00000003/blk000004e1/sig0000174f ), + .A1(\blk00000003/blk000004e1/sig00001750 ), + .A2(\blk00000003/blk000004e1/sig00001750 ), + .A3(\blk00000003/blk000004e1/sig00001750 ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(\blk00000003/sig000005e0 ), + .Q(\blk00000003/blk000004e1/sig00001752 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000004e1/blk000004e5 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/blk000004e1/sig00001751 ), + .Q(\blk00000003/sig00000618 ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000004e1/blk000004e4 ( + .A0(\blk00000003/blk000004e1/sig0000174f ), + .A1(\blk00000003/blk000004e1/sig00001750 ), + .A2(\blk00000003/blk000004e1/sig00001750 ), + .A3(\blk00000003/blk000004e1/sig00001750 ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(\blk00000003/sig000005de ), + .Q(\blk00000003/blk000004e1/sig00001751 ) + ); + VCC \blk00000003/blk000004e1/blk000004e3 ( + .P(\blk00000003/blk000004e1/sig00001750 ) + ); + GND \blk00000003/blk000004e1/blk000004e2 ( + .G(\blk00000003/blk000004e1/sig0000174f ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000508/blk0000052e ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/blk00000508/sig0000179c ), + .Q(\blk00000003/sig0000061b ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000508/blk0000052d ( + .A0(\blk00000003/blk00000508/sig00001789 ), + .A1(\blk00000003/blk00000508/sig0000178a ), + .A2(\blk00000003/blk00000508/sig0000178a ), + .A3(\blk00000003/blk00000508/sig0000178a ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(\blk00000003/sig0000053a ), + .Q(\blk00000003/blk00000508/sig0000179c ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000508/blk0000052c ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/blk00000508/sig0000179b ), + .Q(\blk00000003/sig0000061c ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000508/blk0000052b ( + .A0(\blk00000003/blk00000508/sig00001789 ), + .A1(\blk00000003/blk00000508/sig0000178a ), + .A2(\blk00000003/blk00000508/sig0000178a ), + .A3(\blk00000003/blk00000508/sig0000178a ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(\blk00000003/sig00000538 ), + .Q(\blk00000003/blk00000508/sig0000179b ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000508/blk0000052a ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/blk00000508/sig0000179a ), + .Q(\blk00000003/sig0000061d ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000508/blk00000529 ( + .A0(\blk00000003/blk00000508/sig00001789 ), + .A1(\blk00000003/blk00000508/sig0000178a ), + .A2(\blk00000003/blk00000508/sig0000178a ), + .A3(\blk00000003/blk00000508/sig0000178a ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(\blk00000003/sig00000536 ), + .Q(\blk00000003/blk00000508/sig0000179a ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000508/blk00000528 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/blk00000508/sig00001799 ), + .Q(\blk00000003/sig0000061e ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000508/blk00000527 ( + .A0(\blk00000003/blk00000508/sig00001789 ), + .A1(\blk00000003/blk00000508/sig0000178a ), + .A2(\blk00000003/blk00000508/sig0000178a ), + .A3(\blk00000003/blk00000508/sig0000178a ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(\blk00000003/sig00000534 ), + .Q(\blk00000003/blk00000508/sig00001799 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000508/blk00000526 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/blk00000508/sig00001798 ), + .Q(\blk00000003/sig0000061f ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000508/blk00000525 ( + .A0(\blk00000003/blk00000508/sig00001789 ), + .A1(\blk00000003/blk00000508/sig0000178a ), + .A2(\blk00000003/blk00000508/sig0000178a ), + .A3(\blk00000003/blk00000508/sig0000178a ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(\blk00000003/sig00000532 ), + .Q(\blk00000003/blk00000508/sig00001798 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000508/blk00000524 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/blk00000508/sig00001797 ), + .Q(\blk00000003/sig00000620 ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000508/blk00000523 ( + .A0(\blk00000003/blk00000508/sig00001789 ), + .A1(\blk00000003/blk00000508/sig0000178a ), + .A2(\blk00000003/blk00000508/sig0000178a ), + .A3(\blk00000003/blk00000508/sig0000178a ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(\blk00000003/sig00000530 ), + .Q(\blk00000003/blk00000508/sig00001797 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000508/blk00000522 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/blk00000508/sig00001796 ), + .Q(\blk00000003/sig00000622 ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000508/blk00000521 ( + .A0(\blk00000003/blk00000508/sig00001789 ), + .A1(\blk00000003/blk00000508/sig0000178a ), + .A2(\blk00000003/blk00000508/sig0000178a ), + .A3(\blk00000003/blk00000508/sig0000178a ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(\blk00000003/sig0000052c ), + .Q(\blk00000003/blk00000508/sig00001796 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000508/blk00000520 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/blk00000508/sig00001795 ), + .Q(\blk00000003/sig00000623 ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000508/blk0000051f ( + .A0(\blk00000003/blk00000508/sig00001789 ), + .A1(\blk00000003/blk00000508/sig0000178a ), + .A2(\blk00000003/blk00000508/sig0000178a ), + .A3(\blk00000003/blk00000508/sig0000178a ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(\blk00000003/sig0000052a ), + .Q(\blk00000003/blk00000508/sig00001795 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000508/blk0000051e ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/blk00000508/sig00001794 ), + .Q(\blk00000003/sig00000621 ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000508/blk0000051d ( + .A0(\blk00000003/blk00000508/sig00001789 ), + .A1(\blk00000003/blk00000508/sig0000178a ), + .A2(\blk00000003/blk00000508/sig0000178a ), + .A3(\blk00000003/blk00000508/sig0000178a ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(\blk00000003/sig0000052e ), + .Q(\blk00000003/blk00000508/sig00001794 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000508/blk0000051c ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/blk00000508/sig00001793 ), + .Q(\blk00000003/sig00000624 ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000508/blk0000051b ( + .A0(\blk00000003/blk00000508/sig00001789 ), + .A1(\blk00000003/blk00000508/sig0000178a ), + .A2(\blk00000003/blk00000508/sig0000178a ), + .A3(\blk00000003/blk00000508/sig0000178a ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(\blk00000003/sig00000528 ), + .Q(\blk00000003/blk00000508/sig00001793 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000508/blk0000051a ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/blk00000508/sig00001792 ), + .Q(\blk00000003/sig00000625 ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000508/blk00000519 ( + .A0(\blk00000003/blk00000508/sig00001789 ), + .A1(\blk00000003/blk00000508/sig0000178a ), + .A2(\blk00000003/blk00000508/sig0000178a ), + .A3(\blk00000003/blk00000508/sig0000178a ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(\blk00000003/sig00000526 ), + .Q(\blk00000003/blk00000508/sig00001792 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000508/blk00000518 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/blk00000508/sig00001791 ), + .Q(\blk00000003/sig00000626 ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000508/blk00000517 ( + .A0(\blk00000003/blk00000508/sig00001789 ), + .A1(\blk00000003/blk00000508/sig0000178a ), + .A2(\blk00000003/blk00000508/sig0000178a ), + .A3(\blk00000003/blk00000508/sig0000178a ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(\blk00000003/sig00000524 ), + .Q(\blk00000003/blk00000508/sig00001791 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000508/blk00000516 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/blk00000508/sig00001790 ), + .Q(\blk00000003/sig00000627 ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000508/blk00000515 ( + .A0(\blk00000003/blk00000508/sig00001789 ), + .A1(\blk00000003/blk00000508/sig0000178a ), + .A2(\blk00000003/blk00000508/sig0000178a ), + .A3(\blk00000003/blk00000508/sig0000178a ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(\blk00000003/sig00000522 ), + .Q(\blk00000003/blk00000508/sig00001790 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000508/blk00000514 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/blk00000508/sig0000178f ), + .Q(\blk00000003/sig00000628 ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000508/blk00000513 ( + .A0(\blk00000003/blk00000508/sig00001789 ), + .A1(\blk00000003/blk00000508/sig0000178a ), + .A2(\blk00000003/blk00000508/sig0000178a ), + .A3(\blk00000003/blk00000508/sig0000178a ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(\blk00000003/sig00000520 ), + .Q(\blk00000003/blk00000508/sig0000178f ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000508/blk00000512 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/blk00000508/sig0000178e ), + .Q(\blk00000003/sig00000629 ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000508/blk00000511 ( + .A0(\blk00000003/blk00000508/sig00001789 ), + .A1(\blk00000003/blk00000508/sig0000178a ), + .A2(\blk00000003/blk00000508/sig0000178a ), + .A3(\blk00000003/blk00000508/sig0000178a ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(\blk00000003/sig0000051e ), + .Q(\blk00000003/blk00000508/sig0000178e ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000508/blk00000510 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/blk00000508/sig0000178d ), + .Q(\blk00000003/sig0000062b ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000508/blk0000050f ( + .A0(\blk00000003/blk00000508/sig00001789 ), + .A1(\blk00000003/blk00000508/sig0000178a ), + .A2(\blk00000003/blk00000508/sig0000178a ), + .A3(\blk00000003/blk00000508/sig0000178a ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(\blk00000003/sig0000051a ), + .Q(\blk00000003/blk00000508/sig0000178d ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000508/blk0000050e ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/blk00000508/sig0000178c ), + .Q(\blk00000003/sig0000062c ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000508/blk0000050d ( + .A0(\blk00000003/blk00000508/sig00001789 ), + .A1(\blk00000003/blk00000508/sig0000178a ), + .A2(\blk00000003/blk00000508/sig0000178a ), + .A3(\blk00000003/blk00000508/sig0000178a ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(\blk00000003/sig00000518 ), + .Q(\blk00000003/blk00000508/sig0000178c ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000508/blk0000050c ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/blk00000508/sig0000178b ), + .Q(\blk00000003/sig0000062a ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000508/blk0000050b ( + .A0(\blk00000003/blk00000508/sig00001789 ), + .A1(\blk00000003/blk00000508/sig0000178a ), + .A2(\blk00000003/blk00000508/sig0000178a ), + .A3(\blk00000003/blk00000508/sig0000178a ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(\blk00000003/sig0000051c ), + .Q(\blk00000003/blk00000508/sig0000178b ) + ); + VCC \blk00000003/blk00000508/blk0000050a ( + .P(\blk00000003/blk00000508/sig0000178a ) + ); + GND \blk00000003/blk00000508/blk00000509 ( + .G(\blk00000003/blk00000508/sig00001789 ) + ); + FD #( + .INIT ( 1'b0 )) + \blk00000003/blk00000599/blk000005ad ( + .C(clk), + .D(\blk00000003/blk00000599/sig000017b7 ), + .Q(\blk00000003/sig000006aa ) + ); + SRL16 #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000599/blk000005ac ( + .A0(\blk00000003/blk00000599/sig000017ab ), + .A1(\blk00000003/blk00000599/sig000017ab ), + .A2(\blk00000003/blk00000599/sig000017aa ), + .A3(\blk00000003/blk00000599/sig000017aa ), + .CLK(clk), + .D(\blk00000003/blk00000599/sig000017b6 ), + .Q(\blk00000003/blk00000599/sig000017b7 ) + ); + SRLC16 #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000599/blk000005ab ( + .A0(\blk00000003/blk00000599/sig000017ab ), + .A1(\blk00000003/blk00000599/sig000017ab ), + .A2(\blk00000003/blk00000599/sig000017ab ), + .A3(\blk00000003/blk00000599/sig000017ab ), + .CLK(clk), + .D(\blk00000003/sig00000272 ), + .Q(\NLW_blk00000003/blk00000599/blk000005ab_Q_UNCONNECTED ), + .Q15(\blk00000003/blk00000599/sig000017b6 ) + ); + FD #( + .INIT ( 1'b0 )) + \blk00000003/blk00000599/blk000005aa ( + .C(clk), + .D(\blk00000003/blk00000599/sig000017b5 ), + .Q(\blk00000003/sig000006ab ) + ); + SRL16 #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000599/blk000005a9 ( + .A0(\blk00000003/blk00000599/sig000017ab ), + .A1(\blk00000003/blk00000599/sig000017ab ), + .A2(\blk00000003/blk00000599/sig000017aa ), + .A3(\blk00000003/blk00000599/sig000017aa ), + .CLK(clk), + .D(\blk00000003/blk00000599/sig000017b4 ), + .Q(\blk00000003/blk00000599/sig000017b5 ) + ); + SRLC16 #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000599/blk000005a8 ( + .A0(\blk00000003/blk00000599/sig000017ab ), + .A1(\blk00000003/blk00000599/sig000017ab ), + .A2(\blk00000003/blk00000599/sig000017ab ), + .A3(\blk00000003/blk00000599/sig000017ab ), + .CLK(clk), + .D(\blk00000003/sig00000274 ), + .Q(\NLW_blk00000003/blk00000599/blk000005a8_Q_UNCONNECTED ), + .Q15(\blk00000003/blk00000599/sig000017b4 ) + ); + FD #( + .INIT ( 1'b0 )) + \blk00000003/blk00000599/blk000005a7 ( + .C(clk), + .D(\blk00000003/blk00000599/sig000017b3 ), + .Q(\blk00000003/sig000006a9 ) + ); + SRL16 #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000599/blk000005a6 ( + .A0(\blk00000003/blk00000599/sig000017ab ), + .A1(\blk00000003/blk00000599/sig000017ab ), + .A2(\blk00000003/blk00000599/sig000017aa ), + .A3(\blk00000003/blk00000599/sig000017aa ), + .CLK(clk), + .D(\blk00000003/blk00000599/sig000017b2 ), + .Q(\blk00000003/blk00000599/sig000017b3 ) + ); + SRLC16 #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000599/blk000005a5 ( + .A0(\blk00000003/blk00000599/sig000017ab ), + .A1(\blk00000003/blk00000599/sig000017ab ), + .A2(\blk00000003/blk00000599/sig000017ab ), + .A3(\blk00000003/blk00000599/sig000017ab ), + .CLK(clk), + .D(\blk00000003/sig00000270 ), + .Q(\NLW_blk00000003/blk00000599/blk000005a5_Q_UNCONNECTED ), + .Q15(\blk00000003/blk00000599/sig000017b2 ) + ); + FD #( + .INIT ( 1'b0 )) + \blk00000003/blk00000599/blk000005a4 ( + .C(clk), + .D(\blk00000003/blk00000599/sig000017b1 ), + .Q(\blk00000003/sig000006ad ) + ); + SRL16 #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000599/blk000005a3 ( + .A0(\blk00000003/blk00000599/sig000017ab ), + .A1(\blk00000003/blk00000599/sig000017ab ), + .A2(\blk00000003/blk00000599/sig000017aa ), + .A3(\blk00000003/blk00000599/sig000017aa ), + .CLK(clk), + .D(\blk00000003/blk00000599/sig000017b0 ), + .Q(\blk00000003/blk00000599/sig000017b1 ) + ); + SRLC16 #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000599/blk000005a2 ( + .A0(\blk00000003/blk00000599/sig000017ab ), + .A1(\blk00000003/blk00000599/sig000017ab ), + .A2(\blk00000003/blk00000599/sig000017ab ), + .A3(\blk00000003/blk00000599/sig000017ab ), + .CLK(clk), + .D(\blk00000003/sig00000278 ), + .Q(\NLW_blk00000003/blk00000599/blk000005a2_Q_UNCONNECTED ), + .Q15(\blk00000003/blk00000599/sig000017b0 ) + ); + FD #( + .INIT ( 1'b0 )) + \blk00000003/blk00000599/blk000005a1 ( + .C(clk), + .D(\blk00000003/blk00000599/sig000017af ), + .Q(\blk00000003/sig000006ae ) + ); + SRL16 #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000599/blk000005a0 ( + .A0(\blk00000003/blk00000599/sig000017ab ), + .A1(\blk00000003/blk00000599/sig000017ab ), + .A2(\blk00000003/blk00000599/sig000017aa ), + .A3(\blk00000003/blk00000599/sig000017aa ), + .CLK(clk), + .D(\blk00000003/blk00000599/sig000017ae ), + .Q(\blk00000003/blk00000599/sig000017af ) + ); + SRLC16 #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000599/blk0000059f ( + .A0(\blk00000003/blk00000599/sig000017ab ), + .A1(\blk00000003/blk00000599/sig000017ab ), + .A2(\blk00000003/blk00000599/sig000017ab ), + .A3(\blk00000003/blk00000599/sig000017ab ), + .CLK(clk), + .D(\blk00000003/sig0000027a ), + .Q(\NLW_blk00000003/blk00000599/blk0000059f_Q_UNCONNECTED ), + .Q15(\blk00000003/blk00000599/sig000017ae ) + ); + FD #( + .INIT ( 1'b0 )) + \blk00000003/blk00000599/blk0000059e ( + .C(clk), + .D(\blk00000003/blk00000599/sig000017ad ), + .Q(\blk00000003/sig000006ac ) + ); + SRL16 #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000599/blk0000059d ( + .A0(\blk00000003/blk00000599/sig000017ab ), + .A1(\blk00000003/blk00000599/sig000017ab ), + .A2(\blk00000003/blk00000599/sig000017aa ), + .A3(\blk00000003/blk00000599/sig000017aa ), + .CLK(clk), + .D(\blk00000003/blk00000599/sig000017ac ), + .Q(\blk00000003/blk00000599/sig000017ad ) + ); + SRLC16 #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000599/blk0000059c ( + .A0(\blk00000003/blk00000599/sig000017ab ), + .A1(\blk00000003/blk00000599/sig000017ab ), + .A2(\blk00000003/blk00000599/sig000017ab ), + .A3(\blk00000003/blk00000599/sig000017ab ), + .CLK(clk), + .D(\blk00000003/sig00000276 ), + .Q(\NLW_blk00000003/blk00000599/blk0000059c_Q_UNCONNECTED ), + .Q15(\blk00000003/blk00000599/sig000017ac ) + ); + VCC \blk00000003/blk00000599/blk0000059b ( + .P(\blk00000003/blk00000599/sig000017ab ) + ); + GND \blk00000003/blk00000599/blk0000059a ( + .G(\blk00000003/blk00000599/sig000017aa ) + ); + FD #( + .INIT ( 1'b0 )) + \blk00000003/blk000005ae/blk000005b3 ( + .C(clk), + .D(\blk00000003/blk000005ae/sig000017be ), + .Q(\blk00000003/sig000006af ) + ); + SRL16 #( + .INIT ( 16'h0000 )) + \blk00000003/blk000005ae/blk000005b2 ( + .A0(\blk00000003/blk000005ae/sig000017bc ), + .A1(\blk00000003/blk000005ae/sig000017bc ), + .A2(\blk00000003/blk000005ae/sig000017bb ), + .A3(\blk00000003/blk000005ae/sig000017bb ), + .CLK(clk), + .D(\blk00000003/blk000005ae/sig000017bd ), + .Q(\blk00000003/blk000005ae/sig000017be ) + ); + SRLC16 #( + .INIT ( 16'h0000 )) + \blk00000003/blk000005ae/blk000005b1 ( + .A0(\blk00000003/blk000005ae/sig000017bc ), + .A1(\blk00000003/blk000005ae/sig000017bc ), + .A2(\blk00000003/blk000005ae/sig000017bc ), + .A3(\blk00000003/blk000005ae/sig000017bc ), + .CLK(clk), + .D(\blk00000003/sig00000246 ), + .Q(\NLW_blk00000003/blk000005ae/blk000005b1_Q_UNCONNECTED ), + .Q15(\blk00000003/blk000005ae/sig000017bd ) + ); + VCC \blk00000003/blk000005ae/blk000005b0 ( + .P(\blk00000003/blk000005ae/sig000017bc ) + ); + GND \blk00000003/blk000005ae/blk000005af ( + .G(\blk00000003/blk000005ae/sig000017bb ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000005b4/blk000005b7 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/blk000005b4/sig000017c4 ), + .Q(\blk00000003/sig000006b1 ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000005b4/blk000005b6 ( + .A0(\blk00000003/blk000005b4/sig000017c3 ), + .A1(\blk00000003/blk000005b4/sig000017c3 ), + .A2(\blk00000003/blk000005b4/sig000017c3 ), + .A3(\blk00000003/blk000005b4/sig000017c3 ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(\blk00000003/sig000006b0 ), + .Q(\blk00000003/blk000005b4/sig000017c4 ) + ); + GND \blk00000003/blk000005b4/blk000005b5 ( + .G(\blk00000003/blk000005b4/sig000017c3 ) + ); + FD #( + .INIT ( 1'b0 )) + \blk00000003/blk000005e7/blk0000066a ( + .C(clk), + .D(\blk00000003/blk000005e7/sig0000184e ), + .Q(\blk00000003/sig000006e6 ) + ); + SRL16 #( + .INIT ( 16'h0000 )) + \blk00000003/blk000005e7/blk00000669 ( + .A0(\blk00000003/sig00000181 ), + .A1(\blk00000003/sig00000181 ), + .A2(\blk00000003/sig00000181 ), + .A3(\blk00000003/sig00000181 ), + .CLK(clk), + .D(\blk00000003/sig000006e5 ), + .Q(\blk00000003/blk000005e7/sig0000184e ) + ); + LUT4 #( + .INIT ( 16'h77D4 )) + \blk00000003/blk000005e7/blk00000668 ( + .I0(\blk00000003/sig000006e3 ), + .I1(\blk00000003/sig000006e1 ), + .I2(\blk00000003/sig000006e0 ), + .I3(\blk00000003/sig000006e2 ), + .O(\blk00000003/blk000005e7/sig0000180a ) + ); + LUT4 #( + .INIT ( 16'hBBE8 )) + \blk00000003/blk000005e7/blk00000667 ( + .I0(\blk00000003/sig000006e3 ), + .I1(\blk00000003/sig000006e1 ), + .I2(\blk00000003/sig000006e0 ), + .I3(\blk00000003/sig000006e2 ), + .O(\blk00000003/blk000005e7/sig0000182a ) + ); + LUT4 #( + .INIT ( 16'h9AAA )) + \blk00000003/blk000005e7/blk00000666 ( + .I0(\blk00000003/sig000006e3 ), + .I1(\blk00000003/sig000006e1 ), + .I2(\blk00000003/sig000006e0 ), + .I3(\blk00000003/sig000006e2 ), + .O(\blk00000003/blk000005e7/sig00001812 ) + ); + LUT4 #( + .INIT ( 16'h2864 )) + \blk00000003/blk000005e7/blk00000665 ( + .I0(\blk00000003/sig000006e0 ), + .I1(\blk00000003/sig000006e1 ), + .I2(\blk00000003/sig000006e2 ), + .I3(\blk00000003/sig000006e3 ), + .O(\blk00000003/blk000005e7/sig00001810 ) + ); + LUT4 #( + .INIT ( 16'h2066 )) + \blk00000003/blk000005e7/blk00000664 ( + .I0(\blk00000003/sig000006e0 ), + .I1(\blk00000003/sig000006e1 ), + .I2(\blk00000003/sig000006e3 ), + .I3(\blk00000003/sig000006e2 ), + .O(\blk00000003/blk000005e7/sig00001800 ) + ); + LUT4 #( + .INIT ( 16'h5916 )) + \blk00000003/blk000005e7/blk00000663 ( + .I0(\blk00000003/sig000006e2 ), + .I1(\blk00000003/sig000006e1 ), + .I2(\blk00000003/sig000006e0 ), + .I3(\blk00000003/sig000006e3 ), + .O(\blk00000003/blk000005e7/sig0000181e ) + ); + LUT4 #( + .INIT ( 16'hCE9A )) + \blk00000003/blk000005e7/blk00000662 ( + .I0(\blk00000003/sig000006e1 ), + .I1(\blk00000003/sig000006e0 ), + .I2(\blk00000003/sig000006e2 ), + .I3(\blk00000003/sig000006e3 ), + .O(\blk00000003/blk000005e7/sig0000181a ) + ); + LUT4 #( + .INIT ( 16'hA62A )) + \blk00000003/blk000005e7/blk00000661 ( + .I0(\blk00000003/sig000006e3 ), + .I1(\blk00000003/sig000006e1 ), + .I2(\blk00000003/sig000006e0 ), + .I3(\blk00000003/sig000006e2 ), + .O(\blk00000003/blk000005e7/sig00001822 ) + ); + LUT4 #( + .INIT ( 16'h4C28 )) + \blk00000003/blk000005e7/blk00000660 ( + .I0(\blk00000003/sig000006e0 ), + .I1(\blk00000003/sig000006e1 ), + .I2(\blk00000003/sig000006e2 ), + .I3(\blk00000003/sig000006e3 ), + .O(\blk00000003/blk000005e7/sig000017f0 ) + ); + LUT4 #( + .INIT ( 16'hE146 )) + \blk00000003/blk000005e7/blk0000065f ( + .I0(\blk00000003/sig000006e2 ), + .I1(\blk00000003/sig000006e1 ), + .I2(\blk00000003/sig000006e3 ), + .I3(\blk00000003/sig000006e0 ), + .O(\blk00000003/blk000005e7/sig00001804 ) + ); + LUT4 #( + .INIT ( 16'h5596 )) + \blk00000003/blk000005e7/blk0000065e ( + .I0(\blk00000003/sig000006e3 ), + .I1(\blk00000003/sig000006e1 ), + .I2(\blk00000003/sig000006e0 ), + .I3(\blk00000003/sig000006e2 ), + .O(\blk00000003/blk000005e7/sig000017f2 ) + ); + LUT4 #( + .INIT ( 16'h26B2 )) + \blk00000003/blk000005e7/blk0000065d ( + .I0(\blk00000003/sig000006e2 ), + .I1(\blk00000003/sig000006e3 ), + .I2(\blk00000003/sig000006e0 ), + .I3(\blk00000003/sig000006e1 ), + .O(\blk00000003/blk000005e7/sig00001814 ) + ); + LUT4 #( + .INIT ( 16'hF646 )) + \blk00000003/blk000005e7/blk0000065c ( + .I0(\blk00000003/sig000006e1 ), + .I1(\blk00000003/sig000006e2 ), + .I2(\blk00000003/sig000006e0 ), + .I3(\blk00000003/sig000006e3 ), + .O(\blk00000003/blk000005e7/sig0000181c ) + ); + LUT4 #( + .INIT ( 16'h5166 )) + \blk00000003/blk000005e7/blk0000065b ( + .I0(\blk00000003/sig000006e3 ), + .I1(\blk00000003/sig000006e2 ), + .I2(\blk00000003/sig000006e1 ), + .I3(\blk00000003/sig000006e0 ), + .O(\blk00000003/blk000005e7/sig00001802 ) + ); + LUT4 #( + .INIT ( 16'h7A72 )) + \blk00000003/blk000005e7/blk0000065a ( + .I0(\blk00000003/sig000006e0 ), + .I1(\blk00000003/sig000006e3 ), + .I2(\blk00000003/sig000006e2 ), + .I3(\blk00000003/sig000006e1 ), + .O(\blk00000003/blk000005e7/sig000017fc ) + ); + LUT3 #( + .INIT ( 8'hEA )) + \blk00000003/blk000005e7/blk00000659 ( + .I0(\blk00000003/sig000006e3 ), + .I1(\blk00000003/sig000006e1 ), + .I2(\blk00000003/sig000006e2 ), + .O(\blk00000003/blk000005e7/sig0000182c ) + ); + LUT4 #( + .INIT ( 16'h0001 )) + \blk00000003/blk000005e7/blk00000658 ( + .I0(\blk00000003/sig000006e0 ), + .I1(\blk00000003/sig000006e1 ), + .I2(\blk00000003/sig000006e3 ), + .I3(\blk00000003/sig000006e2 ), + .O(\blk00000003/blk000005e7/sig0000180e ) + ); + LUT4 #( + .INIT ( 16'hEB9A )) + \blk00000003/blk000005e7/blk00000657 ( + .I0(\blk00000003/sig000006e2 ), + .I1(\blk00000003/sig000006e0 ), + .I2(\blk00000003/sig000006e1 ), + .I3(\blk00000003/sig000006e3 ), + .O(\blk00000003/blk000005e7/sig00001828 ) + ); + LUT4 #( + .INIT ( 16'hB0C6 )) + \blk00000003/blk000005e7/blk00000656 ( + .I0(\blk00000003/sig000006e1 ), + .I1(\blk00000003/sig000006e3 ), + .I2(\blk00000003/sig000006e2 ), + .I3(\blk00000003/sig000006e0 ), + .O(\blk00000003/blk000005e7/sig000017fe ) + ); + LUT4 #( + .INIT ( 16'hAA08 )) + \blk00000003/blk000005e7/blk00000655 ( + .I0(\blk00000003/sig000006e1 ), + .I1(\blk00000003/sig000006e0 ), + .I2(\blk00000003/sig000006e3 ), + .I3(\blk00000003/sig000006e2 ), + .O(\blk00000003/blk000005e7/sig00001820 ) + ); + LUT4 #( + .INIT ( 16'h57B6 )) + \blk00000003/blk000005e7/blk00000654 ( + .I0(\blk00000003/sig000006e2 ), + .I1(\blk00000003/sig000006e1 ), + .I2(\blk00000003/sig000006e3 ), + .I3(\blk00000003/sig000006e0 ), + .O(\blk00000003/blk000005e7/sig00001808 ) + ); + LUT4 #( + .INIT ( 16'h7A28 )) + \blk00000003/blk000005e7/blk00000653 ( + .I0(\blk00000003/sig000006e3 ), + .I1(\blk00000003/sig000006e2 ), + .I2(\blk00000003/sig000006e0 ), + .I3(\blk00000003/sig000006e1 ), + .O(\blk00000003/blk000005e7/sig000017f8 ) + ); + LUT4 #( + .INIT ( 16'h8A78 )) + \blk00000003/blk000005e7/blk00000652 ( + .I0(\blk00000003/sig000006e2 ), + .I1(\blk00000003/sig000006e1 ), + .I2(\blk00000003/sig000006e0 ), + .I3(\blk00000003/sig000006e3 ), + .O(\blk00000003/blk000005e7/sig00001824 ) + ); + LUT4 #( + .INIT ( 16'h8BD2 )) + \blk00000003/blk000005e7/blk00000651 ( + .I0(\blk00000003/sig000006e3 ), + .I1(\blk00000003/sig000006e2 ), + .I2(\blk00000003/sig000006e0 ), + .I3(\blk00000003/sig000006e1 ), + .O(\blk00000003/blk000005e7/sig00001826 ) + ); + LUT4 #( + .INIT ( 16'h19F2 )) + \blk00000003/blk000005e7/blk00000650 ( + .I0(\blk00000003/sig000006e2 ), + .I1(\blk00000003/sig000006e3 ), + .I2(\blk00000003/sig000006e1 ), + .I3(\blk00000003/sig000006e0 ), + .O(\blk00000003/blk000005e7/sig00001816 ) + ); + LUT4 #( + .INIT ( 16'hB628 )) + \blk00000003/blk000005e7/blk0000064f ( + .I0(\blk00000003/sig000006e3 ), + .I1(\blk00000003/sig000006e2 ), + .I2(\blk00000003/sig000006e0 ), + .I3(\blk00000003/sig000006e1 ), + .O(\blk00000003/blk000005e7/sig000017f4 ) + ); + LUT4 #( + .INIT ( 16'h575E )) + \blk00000003/blk000005e7/blk0000064e ( + .I0(\blk00000003/sig000006e3 ), + .I1(\blk00000003/sig000006e0 ), + .I2(\blk00000003/sig000006e2 ), + .I3(\blk00000003/sig000006e1 ), + .O(\blk00000003/blk000005e7/sig0000180c ) + ); + LUT4 #( + .INIT ( 16'hF22A )) + \blk00000003/blk000005e7/blk0000064d ( + .I0(\blk00000003/sig000006e1 ), + .I1(\blk00000003/sig000006e0 ), + .I2(\blk00000003/sig000006e3 ), + .I3(\blk00000003/sig000006e2 ), + .O(\blk00000003/blk000005e7/sig000017f6 ) + ); + LUT4 #( + .INIT ( 16'hA92E )) + \blk00000003/blk000005e7/blk0000064c ( + .I0(\blk00000003/sig000006e1 ), + .I1(\blk00000003/sig000006e0 ), + .I2(\blk00000003/sig000006e2 ), + .I3(\blk00000003/sig000006e3 ), + .O(\blk00000003/blk000005e7/sig00001806 ) + ); + LUT4 #( + .INIT ( 16'h45E4 )) + \blk00000003/blk000005e7/blk0000064b ( + .I0(\blk00000003/sig000006e3 ), + .I1(\blk00000003/sig000006e2 ), + .I2(\blk00000003/sig000006e0 ), + .I3(\blk00000003/sig000006e1 ), + .O(\blk00000003/blk000005e7/sig00001818 ) + ); + LUT4 #( + .INIT ( 16'h7E70 )) + \blk00000003/blk000005e7/blk0000064a ( + .I0(\blk00000003/sig000006e1 ), + .I1(\blk00000003/sig000006e3 ), + .I2(\blk00000003/sig000006e0 ), + .I3(\blk00000003/sig000006e2 ), + .O(\blk00000003/blk000005e7/sig000017fa ) + ); + LUT3 #( + .INIT ( 8'hD8 )) + \blk00000003/blk000005e7/blk00000649 ( + .I0(\blk00000003/blk000005e7/sig000017ef ), + .I1(\blk00000003/blk000005e7/sig00001811 ), + .I2(\blk00000003/blk000005e7/sig000017f1 ), + .O(\blk00000003/blk000005e7/sig0000183e ) + ); + LUT3 #( + .INIT ( 8'hD8 )) + \blk00000003/blk000005e7/blk00000648 ( + .I0(\blk00000003/blk000005e7/sig000017ef ), + .I1(\blk00000003/blk000005e7/sig00001825 ), + .I2(\blk00000003/blk000005e7/sig00001805 ), + .O(\blk00000003/blk000005e7/sig00001848 ) + ); + LUT3 #( + .INIT ( 8'hD8 )) + \blk00000003/blk000005e7/blk00000647 ( + .I0(\blk00000003/blk000005e7/sig000017ef ), + .I1(\blk00000003/blk000005e7/sig00001827 ), + .I2(\blk00000003/blk000005e7/sig00001807 ), + .O(\blk00000003/blk000005e7/sig00001849 ) + ); + LUT3 #( + .INIT ( 8'hD8 )) + \blk00000003/blk000005e7/blk00000646 ( + .I0(\blk00000003/blk000005e7/sig000017ef ), + .I1(\blk00000003/blk000005e7/sig00001829 ), + .I2(\blk00000003/blk000005e7/sig00001809 ), + .O(\blk00000003/blk000005e7/sig0000184a ) + ); + LUT3 #( + .INIT ( 8'hD8 )) + \blk00000003/blk000005e7/blk00000645 ( + .I0(\blk00000003/blk000005e7/sig000017ef ), + .I1(\blk00000003/blk000005e7/sig0000182b ), + .I2(\blk00000003/blk000005e7/sig0000180b ), + .O(\blk00000003/blk000005e7/sig0000184b ) + ); + LUT3 #( + .INIT ( 8'hD8 )) + \blk00000003/blk000005e7/blk00000644 ( + .I0(\blk00000003/blk000005e7/sig000017ef ), + .I1(\blk00000003/blk000005e7/sig0000182d ), + .I2(\blk00000003/blk000005e7/sig0000180d ), + .O(\blk00000003/blk000005e7/sig0000184c ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \blk00000003/blk000005e7/blk00000643 ( + .I0(\blk00000003/blk000005e7/sig000017ef ), + .I1(\blk00000003/blk000005e7/sig0000180f ), + .O(\blk00000003/blk000005e7/sig0000184d ) + ); + LUT3 #( + .INIT ( 8'hD8 )) + \blk00000003/blk000005e7/blk00000642 ( + .I0(\blk00000003/blk000005e7/sig000017ef ), + .I1(\blk00000003/blk000005e7/sig00001813 ), + .I2(\blk00000003/blk000005e7/sig000017f3 ), + .O(\blk00000003/blk000005e7/sig0000183f ) + ); + LUT3 #( + .INIT ( 8'hD8 )) + \blk00000003/blk000005e7/blk00000641 ( + .I0(\blk00000003/blk000005e7/sig000017ef ), + .I1(\blk00000003/blk000005e7/sig00001815 ), + .I2(\blk00000003/blk000005e7/sig000017f5 ), + .O(\blk00000003/blk000005e7/sig00001840 ) + ); + LUT3 #( + .INIT ( 8'hD8 )) + \blk00000003/blk000005e7/blk00000640 ( + .I0(\blk00000003/blk000005e7/sig000017ef ), + .I1(\blk00000003/blk000005e7/sig00001817 ), + .I2(\blk00000003/blk000005e7/sig000017f7 ), + .O(\blk00000003/blk000005e7/sig00001841 ) + ); + LUT3 #( + .INIT ( 8'hD8 )) + \blk00000003/blk000005e7/blk0000063f ( + .I0(\blk00000003/blk000005e7/sig000017ef ), + .I1(\blk00000003/blk000005e7/sig00001819 ), + .I2(\blk00000003/blk000005e7/sig000017f9 ), + .O(\blk00000003/blk000005e7/sig00001842 ) + ); + LUT3 #( + .INIT ( 8'hD8 )) + \blk00000003/blk000005e7/blk0000063e ( + .I0(\blk00000003/blk000005e7/sig000017ef ), + .I1(\blk00000003/blk000005e7/sig0000181b ), + .I2(\blk00000003/blk000005e7/sig000017fb ), + .O(\blk00000003/blk000005e7/sig00001843 ) + ); + LUT3 #( + .INIT ( 8'hD8 )) + \blk00000003/blk000005e7/blk0000063d ( + .I0(\blk00000003/blk000005e7/sig000017ef ), + .I1(\blk00000003/blk000005e7/sig0000181d ), + .I2(\blk00000003/blk000005e7/sig000017fd ), + .O(\blk00000003/blk000005e7/sig00001844 ) + ); + LUT3 #( + .INIT ( 8'hD8 )) + \blk00000003/blk000005e7/blk0000063c ( + .I0(\blk00000003/blk000005e7/sig000017ef ), + .I1(\blk00000003/blk000005e7/sig0000181f ), + .I2(\blk00000003/blk000005e7/sig000017ff ), + .O(\blk00000003/blk000005e7/sig00001845 ) + ); + LUT3 #( + .INIT ( 8'hD8 )) + \blk00000003/blk000005e7/blk0000063b ( + .I0(\blk00000003/blk000005e7/sig000017ef ), + .I1(\blk00000003/blk000005e7/sig00001821 ), + .I2(\blk00000003/blk000005e7/sig00001801 ), + .O(\blk00000003/blk000005e7/sig00001846 ) + ); + LUT3 #( + .INIT ( 8'hD8 )) + \blk00000003/blk000005e7/blk0000063a ( + .I0(\blk00000003/blk000005e7/sig000017ef ), + .I1(\blk00000003/blk000005e7/sig00001823 ), + .I2(\blk00000003/blk000005e7/sig00001803 ), + .O(\blk00000003/blk000005e7/sig00001847 ) + ); + LUT3 #( + .INIT ( 8'hD8 )) + \blk00000003/blk000005e7/blk00000639 ( + .I0(\blk00000003/blk000005e7/sig000017ef ), + .I1(\blk00000003/blk000005e7/sig000017f1 ), + .I2(\blk00000003/blk000005e7/sig00001811 ), + .O(\blk00000003/blk000005e7/sig0000182e ) + ); + LUT3 #( + .INIT ( 8'hD8 )) + \blk00000003/blk000005e7/blk00000638 ( + .I0(\blk00000003/blk000005e7/sig000017ef ), + .I1(\blk00000003/blk000005e7/sig00001805 ), + .I2(\blk00000003/blk000005e7/sig00001825 ), + .O(\blk00000003/blk000005e7/sig00001838 ) + ); + LUT3 #( + .INIT ( 8'hD8 )) + \blk00000003/blk000005e7/blk00000637 ( + .I0(\blk00000003/blk000005e7/sig000017ef ), + .I1(\blk00000003/blk000005e7/sig00001807 ), + .I2(\blk00000003/blk000005e7/sig00001827 ), + .O(\blk00000003/blk000005e7/sig00001839 ) + ); + LUT3 #( + .INIT ( 8'hD8 )) + \blk00000003/blk000005e7/blk00000636 ( + .I0(\blk00000003/blk000005e7/sig000017ef ), + .I1(\blk00000003/blk000005e7/sig00001809 ), + .I2(\blk00000003/blk000005e7/sig00001829 ), + .O(\blk00000003/blk000005e7/sig0000183a ) + ); + LUT3 #( + .INIT ( 8'hD8 )) + \blk00000003/blk000005e7/blk00000635 ( + .I0(\blk00000003/blk000005e7/sig000017ef ), + .I1(\blk00000003/blk000005e7/sig0000180b ), + .I2(\blk00000003/blk000005e7/sig0000182b ), + .O(\blk00000003/blk000005e7/sig0000183b ) + ); + LUT3 #( + .INIT ( 8'hD8 )) + \blk00000003/blk000005e7/blk00000634 ( + .I0(\blk00000003/blk000005e7/sig000017ef ), + .I1(\blk00000003/blk000005e7/sig0000180d ), + .I2(\blk00000003/blk000005e7/sig0000182d ), + .O(\blk00000003/blk000005e7/sig0000183c ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk000005e7/blk00000633 ( + .I0(\blk00000003/blk000005e7/sig000017ef ), + .I1(\blk00000003/blk000005e7/sig0000180f ), + .O(\blk00000003/blk000005e7/sig0000183d ) + ); + LUT3 #( + .INIT ( 8'hD8 )) + \blk00000003/blk000005e7/blk00000632 ( + .I0(\blk00000003/blk000005e7/sig000017ef ), + .I1(\blk00000003/blk000005e7/sig000017f3 ), + .I2(\blk00000003/blk000005e7/sig00001813 ), + .O(\blk00000003/blk000005e7/sig0000182f ) + ); + LUT3 #( + .INIT ( 8'hD8 )) + \blk00000003/blk000005e7/blk00000631 ( + .I0(\blk00000003/blk000005e7/sig000017ef ), + .I1(\blk00000003/blk000005e7/sig000017f5 ), + .I2(\blk00000003/blk000005e7/sig00001815 ), + .O(\blk00000003/blk000005e7/sig00001830 ) + ); + LUT3 #( + .INIT ( 8'hD8 )) + \blk00000003/blk000005e7/blk00000630 ( + .I0(\blk00000003/blk000005e7/sig000017ef ), + .I1(\blk00000003/blk000005e7/sig000017f7 ), + .I2(\blk00000003/blk000005e7/sig00001817 ), + .O(\blk00000003/blk000005e7/sig00001831 ) + ); + LUT3 #( + .INIT ( 8'hD8 )) + \blk00000003/blk000005e7/blk0000062f ( + .I0(\blk00000003/blk000005e7/sig000017ef ), + .I1(\blk00000003/blk000005e7/sig000017f9 ), + .I2(\blk00000003/blk000005e7/sig00001819 ), + .O(\blk00000003/blk000005e7/sig00001832 ) + ); + LUT3 #( + .INIT ( 8'hD8 )) + \blk00000003/blk000005e7/blk0000062e ( + .I0(\blk00000003/blk000005e7/sig000017ef ), + .I1(\blk00000003/blk000005e7/sig000017fb ), + .I2(\blk00000003/blk000005e7/sig0000181b ), + .O(\blk00000003/blk000005e7/sig00001833 ) + ); + LUT3 #( + .INIT ( 8'hD8 )) + \blk00000003/blk000005e7/blk0000062d ( + .I0(\blk00000003/blk000005e7/sig000017ef ), + .I1(\blk00000003/blk000005e7/sig000017fd ), + .I2(\blk00000003/blk000005e7/sig0000181d ), + .O(\blk00000003/blk000005e7/sig00001834 ) + ); + LUT3 #( + .INIT ( 8'hD8 )) + \blk00000003/blk000005e7/blk0000062c ( + .I0(\blk00000003/blk000005e7/sig000017ef ), + .I1(\blk00000003/blk000005e7/sig000017ff ), + .I2(\blk00000003/blk000005e7/sig0000181f ), + .O(\blk00000003/blk000005e7/sig00001835 ) + ); + LUT3 #( + .INIT ( 8'hD8 )) + \blk00000003/blk000005e7/blk0000062b ( + .I0(\blk00000003/blk000005e7/sig000017ef ), + .I1(\blk00000003/blk000005e7/sig00001801 ), + .I2(\blk00000003/blk000005e7/sig00001821 ), + .O(\blk00000003/blk000005e7/sig00001836 ) + ); + LUT3 #( + .INIT ( 8'hD8 )) + \blk00000003/blk000005e7/blk0000062a ( + .I0(\blk00000003/blk000005e7/sig000017ef ), + .I1(\blk00000003/blk000005e7/sig00001803 ), + .I2(\blk00000003/blk000005e7/sig00001823 ), + .O(\blk00000003/blk000005e7/sig00001837 ) + ); + FD #( + .INIT ( 1'b0 )) + \blk00000003/blk000005e7/blk00000629 ( + .C(clk), + .D(\blk00000003/blk000005e7/sig0000184d ), + .Q(\blk00000003/sig00000182 ) + ); + FD #( + .INIT ( 1'b0 )) + \blk00000003/blk000005e7/blk00000628 ( + .C(clk), + .D(\blk00000003/blk000005e7/sig0000184c ), + .Q(\blk00000003/sig00000183 ) + ); + FD #( + .INIT ( 1'b0 )) + \blk00000003/blk000005e7/blk00000627 ( + .C(clk), + .D(\blk00000003/blk000005e7/sig0000184b ), + .Q(\blk00000003/sig00000184 ) + ); + FD #( + .INIT ( 1'b0 )) + \blk00000003/blk000005e7/blk00000626 ( + .C(clk), + .D(\blk00000003/blk000005e7/sig0000184a ), + .Q(\blk00000003/sig00000185 ) + ); + FD #( + .INIT ( 1'b0 )) + \blk00000003/blk000005e7/blk00000625 ( + .C(clk), + .D(\blk00000003/blk000005e7/sig00001849 ), + .Q(\blk00000003/sig00000186 ) + ); + FD #( + .INIT ( 1'b0 )) + \blk00000003/blk000005e7/blk00000624 ( + .C(clk), + .D(\blk00000003/blk000005e7/sig00001848 ), + .Q(\blk00000003/sig00000187 ) + ); + FD #( + .INIT ( 1'b0 )) + \blk00000003/blk000005e7/blk00000623 ( + .C(clk), + .D(\blk00000003/blk000005e7/sig00001847 ), + .Q(\blk00000003/sig00000188 ) + ); + FD #( + .INIT ( 1'b0 )) + \blk00000003/blk000005e7/blk00000622 ( + .C(clk), + .D(\blk00000003/blk000005e7/sig00001846 ), + .Q(\blk00000003/sig00000189 ) + ); + FD #( + .INIT ( 1'b0 )) + \blk00000003/blk000005e7/blk00000621 ( + .C(clk), + .D(\blk00000003/blk000005e7/sig00001845 ), + .Q(\blk00000003/sig0000018a ) + ); + FD #( + .INIT ( 1'b0 )) + \blk00000003/blk000005e7/blk00000620 ( + .C(clk), + .D(\blk00000003/blk000005e7/sig00001844 ), + .Q(\blk00000003/sig0000018b ) + ); + FD #( + .INIT ( 1'b0 )) + \blk00000003/blk000005e7/blk0000061f ( + .C(clk), + .D(\blk00000003/blk000005e7/sig00001843 ), + .Q(\blk00000003/sig0000018c ) + ); + FD #( + .INIT ( 1'b0 )) + \blk00000003/blk000005e7/blk0000061e ( + .C(clk), + .D(\blk00000003/blk000005e7/sig00001842 ), + .Q(\blk00000003/sig0000018d ) + ); + FD #( + .INIT ( 1'b0 )) + \blk00000003/blk000005e7/blk0000061d ( + .C(clk), + .D(\blk00000003/blk000005e7/sig00001841 ), + .Q(\blk00000003/sig0000018e ) + ); + FD #( + .INIT ( 1'b0 )) + \blk00000003/blk000005e7/blk0000061c ( + .C(clk), + .D(\blk00000003/blk000005e7/sig00001840 ), + .Q(\blk00000003/sig0000018f ) + ); + FD #( + .INIT ( 1'b0 )) + \blk00000003/blk000005e7/blk0000061b ( + .C(clk), + .D(\blk00000003/blk000005e7/sig0000183f ), + .Q(\blk00000003/sig00000190 ) + ); + FD #( + .INIT ( 1'b0 )) + \blk00000003/blk000005e7/blk0000061a ( + .C(clk), + .D(\blk00000003/blk000005e7/sig0000183e ), + .Q(\blk00000003/sig00000191 ) + ); + FD #( + .INIT ( 1'b0 )) + \blk00000003/blk000005e7/blk00000619 ( + .C(clk), + .D(\blk00000003/blk000005e7/sig0000183d ), + .Q(\blk00000003/sig000001d6 ) + ); + FD #( + .INIT ( 1'b0 )) + \blk00000003/blk000005e7/blk00000618 ( + .C(clk), + .D(\blk00000003/blk000005e7/sig0000183c ), + .Q(\blk00000003/sig000001d7 ) + ); + FD #( + .INIT ( 1'b0 )) + \blk00000003/blk000005e7/blk00000617 ( + .C(clk), + .D(\blk00000003/blk000005e7/sig0000183b ), + .Q(\blk00000003/sig000001d8 ) + ); + FD #( + .INIT ( 1'b0 )) + \blk00000003/blk000005e7/blk00000616 ( + .C(clk), + .D(\blk00000003/blk000005e7/sig0000183a ), + .Q(\blk00000003/sig000001d9 ) + ); + FD #( + .INIT ( 1'b0 )) + \blk00000003/blk000005e7/blk00000615 ( + .C(clk), + .D(\blk00000003/blk000005e7/sig00001839 ), + .Q(\blk00000003/sig000001da ) + ); + FD #( + .INIT ( 1'b0 )) + \blk00000003/blk000005e7/blk00000614 ( + .C(clk), + .D(\blk00000003/blk000005e7/sig00001838 ), + .Q(\blk00000003/sig000001db ) + ); + FD #( + .INIT ( 1'b0 )) + \blk00000003/blk000005e7/blk00000613 ( + .C(clk), + .D(\blk00000003/blk000005e7/sig00001837 ), + .Q(\blk00000003/sig000001dc ) + ); + FD #( + .INIT ( 1'b0 )) + \blk00000003/blk000005e7/blk00000612 ( + .C(clk), + .D(\blk00000003/blk000005e7/sig00001836 ), + .Q(\blk00000003/sig000001dd ) + ); + FD #( + .INIT ( 1'b0 )) + \blk00000003/blk000005e7/blk00000611 ( + .C(clk), + .D(\blk00000003/blk000005e7/sig00001835 ), + .Q(\blk00000003/sig000001de ) + ); + FD #( + .INIT ( 1'b0 )) + \blk00000003/blk000005e7/blk00000610 ( + .C(clk), + .D(\blk00000003/blk000005e7/sig00001834 ), + .Q(\blk00000003/sig000001df ) + ); + FD #( + .INIT ( 1'b0 )) + \blk00000003/blk000005e7/blk0000060f ( + .C(clk), + .D(\blk00000003/blk000005e7/sig00001833 ), + .Q(\blk00000003/sig000001e0 ) + ); + FD #( + .INIT ( 1'b0 )) + \blk00000003/blk000005e7/blk0000060e ( + .C(clk), + .D(\blk00000003/blk000005e7/sig00001832 ), + .Q(\blk00000003/sig000001e1 ) + ); + FD #( + .INIT ( 1'b0 )) + \blk00000003/blk000005e7/blk0000060d ( + .C(clk), + .D(\blk00000003/blk000005e7/sig00001831 ), + .Q(\blk00000003/sig000001e2 ) + ); + FD #( + .INIT ( 1'b0 )) + \blk00000003/blk000005e7/blk0000060c ( + .C(clk), + .D(\blk00000003/blk000005e7/sig00001830 ), + .Q(\blk00000003/sig000001e3 ) + ); + FD #( + .INIT ( 1'b0 )) + \blk00000003/blk000005e7/blk0000060b ( + .C(clk), + .D(\blk00000003/blk000005e7/sig0000182f ), + .Q(\blk00000003/sig000001e4 ) + ); + FD #( + .INIT ( 1'b0 )) + \blk00000003/blk000005e7/blk0000060a ( + .C(clk), + .D(\blk00000003/blk000005e7/sig0000182e ), + .Q(\blk00000003/sig000001e5 ) + ); + FD #( + .INIT ( 1'b0 )) + \blk00000003/blk000005e7/blk00000609 ( + .C(clk), + .D(\blk00000003/blk000005e7/sig0000182c ), + .Q(\blk00000003/blk000005e7/sig0000182d ) + ); + FD #( + .INIT ( 1'b0 )) + \blk00000003/blk000005e7/blk00000608 ( + .C(clk), + .D(\blk00000003/blk000005e7/sig0000182a ), + .Q(\blk00000003/blk000005e7/sig0000182b ) + ); + FD #( + .INIT ( 1'b0 )) + \blk00000003/blk000005e7/blk00000607 ( + .C(clk), + .D(\blk00000003/blk000005e7/sig00001828 ), + .Q(\blk00000003/blk000005e7/sig00001829 ) + ); + FD #( + .INIT ( 1'b0 )) + \blk00000003/blk000005e7/blk00000606 ( + .C(clk), + .D(\blk00000003/blk000005e7/sig00001826 ), + .Q(\blk00000003/blk000005e7/sig00001827 ) + ); + FD #( + .INIT ( 1'b0 )) + \blk00000003/blk000005e7/blk00000605 ( + .C(clk), + .D(\blk00000003/blk000005e7/sig00001824 ), + .Q(\blk00000003/blk000005e7/sig00001825 ) + ); + FD #( + .INIT ( 1'b0 )) + \blk00000003/blk000005e7/blk00000604 ( + .C(clk), + .D(\blk00000003/blk000005e7/sig00001822 ), + .Q(\blk00000003/blk000005e7/sig00001823 ) + ); + FD #( + .INIT ( 1'b0 )) + \blk00000003/blk000005e7/blk00000603 ( + .C(clk), + .D(\blk00000003/blk000005e7/sig00001820 ), + .Q(\blk00000003/blk000005e7/sig00001821 ) + ); + FD #( + .INIT ( 1'b0 )) + \blk00000003/blk000005e7/blk00000602 ( + .C(clk), + .D(\blk00000003/blk000005e7/sig0000181e ), + .Q(\blk00000003/blk000005e7/sig0000181f ) + ); + FD #( + .INIT ( 1'b0 )) + \blk00000003/blk000005e7/blk00000601 ( + .C(clk), + .D(\blk00000003/blk000005e7/sig0000181c ), + .Q(\blk00000003/blk000005e7/sig0000181d ) + ); + FD #( + .INIT ( 1'b0 )) + \blk00000003/blk000005e7/blk00000600 ( + .C(clk), + .D(\blk00000003/blk000005e7/sig0000181a ), + .Q(\blk00000003/blk000005e7/sig0000181b ) + ); + FD #( + .INIT ( 1'b0 )) + \blk00000003/blk000005e7/blk000005ff ( + .C(clk), + .D(\blk00000003/blk000005e7/sig00001818 ), + .Q(\blk00000003/blk000005e7/sig00001819 ) + ); + FD #( + .INIT ( 1'b0 )) + \blk00000003/blk000005e7/blk000005fe ( + .C(clk), + .D(\blk00000003/blk000005e7/sig00001816 ), + .Q(\blk00000003/blk000005e7/sig00001817 ) + ); + FD #( + .INIT ( 1'b0 )) + \blk00000003/blk000005e7/blk000005fd ( + .C(clk), + .D(\blk00000003/blk000005e7/sig00001814 ), + .Q(\blk00000003/blk000005e7/sig00001815 ) + ); + FD #( + .INIT ( 1'b0 )) + \blk00000003/blk000005e7/blk000005fc ( + .C(clk), + .D(\blk00000003/blk000005e7/sig00001812 ), + .Q(\blk00000003/blk000005e7/sig00001813 ) + ); + FD #( + .INIT ( 1'b0 )) + \blk00000003/blk000005e7/blk000005fb ( + .C(clk), + .D(\blk00000003/blk000005e7/sig00001810 ), + .Q(\blk00000003/blk000005e7/sig00001811 ) + ); + FD #( + .INIT ( 1'b0 )) + \blk00000003/blk000005e7/blk000005fa ( + .C(clk), + .D(\blk00000003/blk000005e7/sig000017ef ), + .Q(\blk00000003/sig000006e7 ) + ); + FD #( + .INIT ( 1'b0 )) + \blk00000003/blk000005e7/blk000005f9 ( + .C(clk), + .D(\blk00000003/blk000005e7/sig0000180e ), + .Q(\blk00000003/blk000005e7/sig0000180f ) + ); + FD #( + .INIT ( 1'b0 )) + \blk00000003/blk000005e7/blk000005f8 ( + .C(clk), + .D(\blk00000003/blk000005e7/sig0000180c ), + .Q(\blk00000003/blk000005e7/sig0000180d ) + ); + FD #( + .INIT ( 1'b0 )) + \blk00000003/blk000005e7/blk000005f7 ( + .C(clk), + .D(\blk00000003/blk000005e7/sig0000180a ), + .Q(\blk00000003/blk000005e7/sig0000180b ) + ); + FD #( + .INIT ( 1'b0 )) + \blk00000003/blk000005e7/blk000005f6 ( + .C(clk), + .D(\blk00000003/blk000005e7/sig00001808 ), + .Q(\blk00000003/blk000005e7/sig00001809 ) + ); + FD #( + .INIT ( 1'b0 )) + \blk00000003/blk000005e7/blk000005f5 ( + .C(clk), + .D(\blk00000003/blk000005e7/sig00001806 ), + .Q(\blk00000003/blk000005e7/sig00001807 ) + ); + FD #( + .INIT ( 1'b0 )) + \blk00000003/blk000005e7/blk000005f4 ( + .C(clk), + .D(\blk00000003/blk000005e7/sig00001804 ), + .Q(\blk00000003/blk000005e7/sig00001805 ) + ); + FD #( + .INIT ( 1'b0 )) + \blk00000003/blk000005e7/blk000005f3 ( + .C(clk), + .D(\blk00000003/blk000005e7/sig00001802 ), + .Q(\blk00000003/blk000005e7/sig00001803 ) + ); + FD #( + .INIT ( 1'b0 )) + \blk00000003/blk000005e7/blk000005f2 ( + .C(clk), + .D(\blk00000003/blk000005e7/sig00001800 ), + .Q(\blk00000003/blk000005e7/sig00001801 ) + ); + FD #( + .INIT ( 1'b0 )) + \blk00000003/blk000005e7/blk000005f1 ( + .C(clk), + .D(\blk00000003/blk000005e7/sig000017fe ), + .Q(\blk00000003/blk000005e7/sig000017ff ) + ); + FD #( + .INIT ( 1'b0 )) + \blk00000003/blk000005e7/blk000005f0 ( + .C(clk), + .D(\blk00000003/blk000005e7/sig000017fc ), + .Q(\blk00000003/blk000005e7/sig000017fd ) + ); + FD #( + .INIT ( 1'b0 )) + \blk00000003/blk000005e7/blk000005ef ( + .C(clk), + .D(\blk00000003/blk000005e7/sig000017fa ), + .Q(\blk00000003/blk000005e7/sig000017fb ) + ); + FD #( + .INIT ( 1'b0 )) + \blk00000003/blk000005e7/blk000005ee ( + .C(clk), + .D(\blk00000003/blk000005e7/sig000017f8 ), + .Q(\blk00000003/blk000005e7/sig000017f9 ) + ); + FD #( + .INIT ( 1'b0 )) + \blk00000003/blk000005e7/blk000005ed ( + .C(clk), + .D(\blk00000003/blk000005e7/sig000017f6 ), + .Q(\blk00000003/blk000005e7/sig000017f7 ) + ); + FD #( + .INIT ( 1'b0 )) + \blk00000003/blk000005e7/blk000005ec ( + .C(clk), + .D(\blk00000003/blk000005e7/sig000017f4 ), + .Q(\blk00000003/blk000005e7/sig000017f5 ) + ); + FD #( + .INIT ( 1'b0 )) + \blk00000003/blk000005e7/blk000005eb ( + .C(clk), + .D(\blk00000003/blk000005e7/sig000017f2 ), + .Q(\blk00000003/blk000005e7/sig000017f3 ) + ); + FD #( + .INIT ( 1'b0 )) + \blk00000003/blk000005e7/blk000005ea ( + .C(clk), + .D(\blk00000003/blk000005e7/sig000017f0 ), + .Q(\blk00000003/blk000005e7/sig000017f1 ) + ); + FD #( + .INIT ( 1'b0 )) + \blk00000003/blk000005e7/blk000005e9 ( + .C(clk), + .D(\blk00000003/sig000006e4 ), + .Q(\blk00000003/blk000005e7/sig000017ef ) + ); + GND \blk00000003/blk000005e7/blk000005e8 ( + .G(\blk00000003/sig00000181 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000066b/blk0000066f ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/blk0000066b/sig00001855 ), + .Q(\blk00000003/sig000006e9 ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000066b/blk0000066e ( + .A0(\blk00000003/blk0000066b/sig00001853 ), + .A1(\blk00000003/blk0000066b/sig00001854 ), + .A2(\blk00000003/blk0000066b/sig00001854 ), + .A3(\blk00000003/blk0000066b/sig00001854 ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(\blk00000003/sig000006e8 ), + .Q(\blk00000003/blk0000066b/sig00001855 ) + ); + VCC \blk00000003/blk0000066b/blk0000066d ( + .P(\blk00000003/blk0000066b/sig00001854 ) + ); + GND \blk00000003/blk0000066b/blk0000066c ( + .G(\blk00000003/blk0000066b/sig00001853 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000070f/blk00000737 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/blk0000070f/sig00001892 ), + .Q(\blk00000003/sig000007e8 ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000070f/blk00000736 ( + .A0(\blk00000003/blk0000070f/sig0000187e ), + .A1(\blk00000003/blk0000070f/sig0000187f ), + .A2(\blk00000003/blk0000070f/sig0000187f ), + .A3(\blk00000003/blk0000070f/sig0000187e ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(\blk00000003/sig000007bf ), + .Q(\blk00000003/blk0000070f/sig00001892 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000070f/blk00000735 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/blk0000070f/sig00001891 ), + .Q(\blk00000003/sig000007e9 ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000070f/blk00000734 ( + .A0(\blk00000003/blk0000070f/sig0000187e ), + .A1(\blk00000003/blk0000070f/sig0000187f ), + .A2(\blk00000003/blk0000070f/sig0000187f ), + .A3(\blk00000003/blk0000070f/sig0000187e ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(\blk00000003/sig000007bd ), + .Q(\blk00000003/blk0000070f/sig00001891 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000070f/blk00000733 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/blk0000070f/sig00001890 ), + .Q(\blk00000003/sig000007ea ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000070f/blk00000732 ( + .A0(\blk00000003/blk0000070f/sig0000187e ), + .A1(\blk00000003/blk0000070f/sig0000187f ), + .A2(\blk00000003/blk0000070f/sig0000187f ), + .A3(\blk00000003/blk0000070f/sig0000187e ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(\blk00000003/sig000007bb ), + .Q(\blk00000003/blk0000070f/sig00001890 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000070f/blk00000731 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/blk0000070f/sig0000188f ), + .Q(\blk00000003/sig000007eb ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000070f/blk00000730 ( + .A0(\blk00000003/blk0000070f/sig0000187e ), + .A1(\blk00000003/blk0000070f/sig0000187f ), + .A2(\blk00000003/blk0000070f/sig0000187f ), + .A3(\blk00000003/blk0000070f/sig0000187e ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(\blk00000003/sig000007b9 ), + .Q(\blk00000003/blk0000070f/sig0000188f ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000070f/blk0000072f ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/blk0000070f/sig0000188e ), + .Q(\blk00000003/sig000007ec ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000070f/blk0000072e ( + .A0(\blk00000003/blk0000070f/sig0000187e ), + .A1(\blk00000003/blk0000070f/sig0000187f ), + .A2(\blk00000003/blk0000070f/sig0000187f ), + .A3(\blk00000003/blk0000070f/sig0000187e ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(\blk00000003/sig000007b7 ), + .Q(\blk00000003/blk0000070f/sig0000188e ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000070f/blk0000072d ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/blk0000070f/sig0000188d ), + .Q(\blk00000003/sig000007ed ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000070f/blk0000072c ( + .A0(\blk00000003/blk0000070f/sig0000187e ), + .A1(\blk00000003/blk0000070f/sig0000187f ), + .A2(\blk00000003/blk0000070f/sig0000187f ), + .A3(\blk00000003/blk0000070f/sig0000187e ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(\blk00000003/sig000007b5 ), + .Q(\blk00000003/blk0000070f/sig0000188d ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000070f/blk0000072b ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/blk0000070f/sig0000188c ), + .Q(\blk00000003/sig000007ef ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000070f/blk0000072a ( + .A0(\blk00000003/blk0000070f/sig0000187e ), + .A1(\blk00000003/blk0000070f/sig0000187f ), + .A2(\blk00000003/blk0000070f/sig0000187f ), + .A3(\blk00000003/blk0000070f/sig0000187e ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(\blk00000003/sig000007b1 ), + .Q(\blk00000003/blk0000070f/sig0000188c ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000070f/blk00000729 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/blk0000070f/sig0000188b ), + .Q(\blk00000003/sig000007f0 ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000070f/blk00000728 ( + .A0(\blk00000003/blk0000070f/sig0000187e ), + .A1(\blk00000003/blk0000070f/sig0000187f ), + .A2(\blk00000003/blk0000070f/sig0000187f ), + .A3(\blk00000003/blk0000070f/sig0000187e ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(\blk00000003/sig000007af ), + .Q(\blk00000003/blk0000070f/sig0000188b ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000070f/blk00000727 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/blk0000070f/sig0000188a ), + .Q(\blk00000003/sig000007ee ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000070f/blk00000726 ( + .A0(\blk00000003/blk0000070f/sig0000187e ), + .A1(\blk00000003/blk0000070f/sig0000187f ), + .A2(\blk00000003/blk0000070f/sig0000187f ), + .A3(\blk00000003/blk0000070f/sig0000187e ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(\blk00000003/sig000007b3 ), + .Q(\blk00000003/blk0000070f/sig0000188a ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000070f/blk00000725 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/blk0000070f/sig00001889 ), + .Q(\blk00000003/sig000007f1 ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000070f/blk00000724 ( + .A0(\blk00000003/blk0000070f/sig0000187e ), + .A1(\blk00000003/blk0000070f/sig0000187f ), + .A2(\blk00000003/blk0000070f/sig0000187f ), + .A3(\blk00000003/blk0000070f/sig0000187e ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(\blk00000003/sig000007ad ), + .Q(\blk00000003/blk0000070f/sig00001889 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000070f/blk00000723 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/blk0000070f/sig00001888 ), + .Q(\blk00000003/sig000007f2 ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000070f/blk00000722 ( + .A0(\blk00000003/blk0000070f/sig0000187e ), + .A1(\blk00000003/blk0000070f/sig0000187f ), + .A2(\blk00000003/blk0000070f/sig0000187f ), + .A3(\blk00000003/blk0000070f/sig0000187e ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(\blk00000003/sig000007ab ), + .Q(\blk00000003/blk0000070f/sig00001888 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000070f/blk00000721 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/blk0000070f/sig00001887 ), + .Q(\blk00000003/sig000007f4 ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000070f/blk00000720 ( + .A0(\blk00000003/blk0000070f/sig0000187e ), + .A1(\blk00000003/blk0000070f/sig0000187f ), + .A2(\blk00000003/blk0000070f/sig0000187f ), + .A3(\blk00000003/blk0000070f/sig0000187e ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(\blk00000003/sig000007a7 ), + .Q(\blk00000003/blk0000070f/sig00001887 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000070f/blk0000071f ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/blk0000070f/sig00001886 ), + .Q(\blk00000003/sig000007f5 ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000070f/blk0000071e ( + .A0(\blk00000003/blk0000070f/sig0000187e ), + .A1(\blk00000003/blk0000070f/sig0000187f ), + .A2(\blk00000003/blk0000070f/sig0000187f ), + .A3(\blk00000003/blk0000070f/sig0000187e ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(\blk00000003/sig000007a5 ), + .Q(\blk00000003/blk0000070f/sig00001886 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000070f/blk0000071d ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/blk0000070f/sig00001885 ), + .Q(\blk00000003/sig000007f3 ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000070f/blk0000071c ( + .A0(\blk00000003/blk0000070f/sig0000187e ), + .A1(\blk00000003/blk0000070f/sig0000187f ), + .A2(\blk00000003/blk0000070f/sig0000187f ), + .A3(\blk00000003/blk0000070f/sig0000187e ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(\blk00000003/sig000007a9 ), + .Q(\blk00000003/blk0000070f/sig00001885 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000070f/blk0000071b ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/blk0000070f/sig00001884 ), + .Q(\blk00000003/sig000007f6 ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000070f/blk0000071a ( + .A0(\blk00000003/blk0000070f/sig0000187e ), + .A1(\blk00000003/blk0000070f/sig0000187f ), + .A2(\blk00000003/blk0000070f/sig0000187f ), + .A3(\blk00000003/blk0000070f/sig0000187e ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(\blk00000003/sig000007a3 ), + .Q(\blk00000003/blk0000070f/sig00001884 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000070f/blk00000719 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/blk0000070f/sig00001883 ), + .Q(\blk00000003/sig000007f7 ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000070f/blk00000718 ( + .A0(\blk00000003/blk0000070f/sig0000187e ), + .A1(\blk00000003/blk0000070f/sig0000187f ), + .A2(\blk00000003/blk0000070f/sig0000187f ), + .A3(\blk00000003/blk0000070f/sig0000187e ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(\blk00000003/sig000007a1 ), + .Q(\blk00000003/blk0000070f/sig00001883 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000070f/blk00000717 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/blk0000070f/sig00001882 ), + .Q(\blk00000003/sig000007f9 ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000070f/blk00000716 ( + .A0(\blk00000003/blk0000070f/sig0000187e ), + .A1(\blk00000003/blk0000070f/sig0000187f ), + .A2(\blk00000003/blk0000070f/sig0000187f ), + .A3(\blk00000003/blk0000070f/sig0000187e ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(\blk00000003/sig0000079d ), + .Q(\blk00000003/blk0000070f/sig00001882 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000070f/blk00000715 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/blk0000070f/sig00001881 ), + .Q(\blk00000003/sig000007fa ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000070f/blk00000714 ( + .A0(\blk00000003/blk0000070f/sig0000187e ), + .A1(\blk00000003/blk0000070f/sig0000187f ), + .A2(\blk00000003/blk0000070f/sig0000187f ), + .A3(\blk00000003/blk0000070f/sig0000187e ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(\blk00000003/sig0000079b ), + .Q(\blk00000003/blk0000070f/sig00001881 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000070f/blk00000713 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/blk0000070f/sig00001880 ), + .Q(\blk00000003/sig000007f8 ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000070f/blk00000712 ( + .A0(\blk00000003/blk0000070f/sig0000187e ), + .A1(\blk00000003/blk0000070f/sig0000187f ), + .A2(\blk00000003/blk0000070f/sig0000187f ), + .A3(\blk00000003/blk0000070f/sig0000187e ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(\blk00000003/sig0000079f ), + .Q(\blk00000003/blk0000070f/sig00001880 ) + ); + VCC \blk00000003/blk0000070f/blk00000711 ( + .P(\blk00000003/blk0000070f/sig0000187f ) + ); + GND \blk00000003/blk0000070f/blk00000710 ( + .G(\blk00000003/blk0000070f/sig0000187e ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000738/blk00000760 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/blk00000738/sig000018cf ), + .Q(\blk00000003/sig000007fb ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000738/blk0000075f ( + .A0(\blk00000003/blk00000738/sig000018bb ), + .A1(\blk00000003/blk00000738/sig000018bc ), + .A2(\blk00000003/blk00000738/sig000018bc ), + .A3(\blk00000003/blk00000738/sig000018bb ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(\blk00000003/sig000001e6 ), + .Q(\blk00000003/blk00000738/sig000018cf ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000738/blk0000075e ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/blk00000738/sig000018ce ), + .Q(\blk00000003/sig000007fc ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000738/blk0000075d ( + .A0(\blk00000003/blk00000738/sig000018bb ), + .A1(\blk00000003/blk00000738/sig000018bc ), + .A2(\blk00000003/blk00000738/sig000018bc ), + .A3(\blk00000003/blk00000738/sig000018bb ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(\blk00000003/sig000001e7 ), + .Q(\blk00000003/blk00000738/sig000018ce ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000738/blk0000075c ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/blk00000738/sig000018cd ), + .Q(\blk00000003/sig000007fd ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000738/blk0000075b ( + .A0(\blk00000003/blk00000738/sig000018bb ), + .A1(\blk00000003/blk00000738/sig000018bc ), + .A2(\blk00000003/blk00000738/sig000018bc ), + .A3(\blk00000003/blk00000738/sig000018bb ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(\blk00000003/sig000001e8 ), + .Q(\blk00000003/blk00000738/sig000018cd ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000738/blk0000075a ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/blk00000738/sig000018cc ), + .Q(\blk00000003/sig000007fe ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000738/blk00000759 ( + .A0(\blk00000003/blk00000738/sig000018bb ), + .A1(\blk00000003/blk00000738/sig000018bc ), + .A2(\blk00000003/blk00000738/sig000018bc ), + .A3(\blk00000003/blk00000738/sig000018bb ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(\blk00000003/sig000001e9 ), + .Q(\blk00000003/blk00000738/sig000018cc ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000738/blk00000758 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/blk00000738/sig000018cb ), + .Q(\blk00000003/sig000007ff ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000738/blk00000757 ( + .A0(\blk00000003/blk00000738/sig000018bb ), + .A1(\blk00000003/blk00000738/sig000018bc ), + .A2(\blk00000003/blk00000738/sig000018bc ), + .A3(\blk00000003/blk00000738/sig000018bb ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(\blk00000003/sig000001ea ), + .Q(\blk00000003/blk00000738/sig000018cb ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000738/blk00000756 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/blk00000738/sig000018ca ), + .Q(\blk00000003/sig00000800 ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000738/blk00000755 ( + .A0(\blk00000003/blk00000738/sig000018bb ), + .A1(\blk00000003/blk00000738/sig000018bc ), + .A2(\blk00000003/blk00000738/sig000018bc ), + .A3(\blk00000003/blk00000738/sig000018bb ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(\blk00000003/sig000001eb ), + .Q(\blk00000003/blk00000738/sig000018ca ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000738/blk00000754 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/blk00000738/sig000018c9 ), + .Q(\blk00000003/sig00000802 ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000738/blk00000753 ( + .A0(\blk00000003/blk00000738/sig000018bb ), + .A1(\blk00000003/blk00000738/sig000018bc ), + .A2(\blk00000003/blk00000738/sig000018bc ), + .A3(\blk00000003/blk00000738/sig000018bb ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(\blk00000003/sig000001ed ), + .Q(\blk00000003/blk00000738/sig000018c9 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000738/blk00000752 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/blk00000738/sig000018c8 ), + .Q(\blk00000003/sig00000803 ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000738/blk00000751 ( + .A0(\blk00000003/blk00000738/sig000018bb ), + .A1(\blk00000003/blk00000738/sig000018bc ), + .A2(\blk00000003/blk00000738/sig000018bc ), + .A3(\blk00000003/blk00000738/sig000018bb ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(\blk00000003/sig000001ee ), + .Q(\blk00000003/blk00000738/sig000018c8 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000738/blk00000750 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/blk00000738/sig000018c7 ), + .Q(\blk00000003/sig00000801 ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000738/blk0000074f ( + .A0(\blk00000003/blk00000738/sig000018bb ), + .A1(\blk00000003/blk00000738/sig000018bc ), + .A2(\blk00000003/blk00000738/sig000018bc ), + .A3(\blk00000003/blk00000738/sig000018bb ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(\blk00000003/sig000001ec ), + .Q(\blk00000003/blk00000738/sig000018c7 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000738/blk0000074e ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/blk00000738/sig000018c6 ), + .Q(\blk00000003/sig00000804 ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000738/blk0000074d ( + .A0(\blk00000003/blk00000738/sig000018bb ), + .A1(\blk00000003/blk00000738/sig000018bc ), + .A2(\blk00000003/blk00000738/sig000018bc ), + .A3(\blk00000003/blk00000738/sig000018bb ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(\blk00000003/sig000001ef ), + .Q(\blk00000003/blk00000738/sig000018c6 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000738/blk0000074c ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/blk00000738/sig000018c5 ), + .Q(\blk00000003/sig00000805 ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000738/blk0000074b ( + .A0(\blk00000003/blk00000738/sig000018bb ), + .A1(\blk00000003/blk00000738/sig000018bc ), + .A2(\blk00000003/blk00000738/sig000018bc ), + .A3(\blk00000003/blk00000738/sig000018bb ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(\blk00000003/sig000001f0 ), + .Q(\blk00000003/blk00000738/sig000018c5 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000738/blk0000074a ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/blk00000738/sig000018c4 ), + .Q(\blk00000003/sig00000807 ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000738/blk00000749 ( + .A0(\blk00000003/blk00000738/sig000018bb ), + .A1(\blk00000003/blk00000738/sig000018bc ), + .A2(\blk00000003/blk00000738/sig000018bc ), + .A3(\blk00000003/blk00000738/sig000018bb ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(\blk00000003/sig000001f2 ), + .Q(\blk00000003/blk00000738/sig000018c4 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000738/blk00000748 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/blk00000738/sig000018c3 ), + .Q(\blk00000003/sig00000808 ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000738/blk00000747 ( + .A0(\blk00000003/blk00000738/sig000018bb ), + .A1(\blk00000003/blk00000738/sig000018bc ), + .A2(\blk00000003/blk00000738/sig000018bc ), + .A3(\blk00000003/blk00000738/sig000018bb ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(\blk00000003/sig000001f3 ), + .Q(\blk00000003/blk00000738/sig000018c3 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000738/blk00000746 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/blk00000738/sig000018c2 ), + .Q(\blk00000003/sig00000806 ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000738/blk00000745 ( + .A0(\blk00000003/blk00000738/sig000018bb ), + .A1(\blk00000003/blk00000738/sig000018bc ), + .A2(\blk00000003/blk00000738/sig000018bc ), + .A3(\blk00000003/blk00000738/sig000018bb ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(\blk00000003/sig000001f1 ), + .Q(\blk00000003/blk00000738/sig000018c2 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000738/blk00000744 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/blk00000738/sig000018c1 ), + .Q(\blk00000003/sig00000809 ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000738/blk00000743 ( + .A0(\blk00000003/blk00000738/sig000018bb ), + .A1(\blk00000003/blk00000738/sig000018bc ), + .A2(\blk00000003/blk00000738/sig000018bc ), + .A3(\blk00000003/blk00000738/sig000018bb ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(\blk00000003/sig000001f4 ), + .Q(\blk00000003/blk00000738/sig000018c1 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000738/blk00000742 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/blk00000738/sig000018c0 ), + .Q(\blk00000003/sig0000080a ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000738/blk00000741 ( + .A0(\blk00000003/blk00000738/sig000018bb ), + .A1(\blk00000003/blk00000738/sig000018bc ), + .A2(\blk00000003/blk00000738/sig000018bc ), + .A3(\blk00000003/blk00000738/sig000018bb ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(\blk00000003/sig000001f5 ), + .Q(\blk00000003/blk00000738/sig000018c0 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000738/blk00000740 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/blk00000738/sig000018bf ), + .Q(\blk00000003/sig0000080c ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000738/blk0000073f ( + .A0(\blk00000003/blk00000738/sig000018bb ), + .A1(\blk00000003/blk00000738/sig000018bc ), + .A2(\blk00000003/blk00000738/sig000018bc ), + .A3(\blk00000003/blk00000738/sig000018bb ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(\blk00000003/sig000001f7 ), + .Q(\blk00000003/blk00000738/sig000018bf ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000738/blk0000073e ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/blk00000738/sig000018be ), + .Q(\blk00000003/sig0000080d ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000738/blk0000073d ( + .A0(\blk00000003/blk00000738/sig000018bb ), + .A1(\blk00000003/blk00000738/sig000018bc ), + .A2(\blk00000003/blk00000738/sig000018bc ), + .A3(\blk00000003/blk00000738/sig000018bb ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(\blk00000003/sig000001f8 ), + .Q(\blk00000003/blk00000738/sig000018be ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000738/blk0000073c ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/blk00000738/sig000018bd ), + .Q(\blk00000003/sig0000080b ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000738/blk0000073b ( + .A0(\blk00000003/blk00000738/sig000018bb ), + .A1(\blk00000003/blk00000738/sig000018bc ), + .A2(\blk00000003/blk00000738/sig000018bc ), + .A3(\blk00000003/blk00000738/sig000018bb ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(\blk00000003/sig000001f6 ), + .Q(\blk00000003/blk00000738/sig000018bd ) + ); + VCC \blk00000003/blk00000738/blk0000073a ( + .P(\blk00000003/blk00000738/sig000018bc ) + ); + GND \blk00000003/blk00000738/blk00000739 ( + .G(\blk00000003/blk00000738/sig000018bb ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000761/blk00000765 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/blk00000761/sig000018d6 ), + .Q(\blk00000003/sig0000080e ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000761/blk00000764 ( + .A0(\blk00000003/blk00000761/sig000018d4 ), + .A1(\blk00000003/blk00000761/sig000018d5 ), + .A2(\blk00000003/blk00000761/sig000018d5 ), + .A3(\blk00000003/blk00000761/sig000018d4 ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(\blk00000003/sig000007e7 ), + .Q(\blk00000003/blk00000761/sig000018d6 ) + ); + VCC \blk00000003/blk00000761/blk00000763 ( + .P(\blk00000003/blk00000761/sig000018d5 ) + ); + GND \blk00000003/blk00000761/blk00000762 ( + .G(\blk00000003/blk00000761/sig000018d4 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007dc/blk00000806 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/blk000007dc/sig00001916 ), + .Q(\blk00000003/sig000008ad ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000007dc/blk00000805 ( + .A0(\blk00000003/blk000007dc/sig00001901 ), + .A1(\blk00000003/blk000007dc/sig00001902 ), + .A2(\blk00000003/blk000007dc/sig00001902 ), + .A3(\blk00000003/blk000007dc/sig00001901 ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(\blk00000003/sig00000771 ), + .Q(\blk00000003/blk000007dc/sig00001916 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007dc/blk00000804 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/blk000007dc/sig00001915 ), + .Q(\blk00000003/sig000008ae ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000007dc/blk00000803 ( + .A0(\blk00000003/blk000007dc/sig00001901 ), + .A1(\blk00000003/blk000007dc/sig00001902 ), + .A2(\blk00000003/blk000007dc/sig00001902 ), + .A3(\blk00000003/blk000007dc/sig00001901 ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(\blk00000003/sig0000076f ), + .Q(\blk00000003/blk000007dc/sig00001915 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007dc/blk00000802 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/blk000007dc/sig00001914 ), + .Q(\blk00000003/sig000008b0 ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000007dc/blk00000801 ( + .A0(\blk00000003/blk000007dc/sig00001901 ), + .A1(\blk00000003/blk000007dc/sig00001902 ), + .A2(\blk00000003/blk000007dc/sig00001902 ), + .A3(\blk00000003/blk000007dc/sig00001901 ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(\blk00000003/sig0000076b ), + .Q(\blk00000003/blk000007dc/sig00001914 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007dc/blk00000800 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/blk000007dc/sig00001913 ), + .Q(\blk00000003/sig000008b1 ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000007dc/blk000007ff ( + .A0(\blk00000003/blk000007dc/sig00001901 ), + .A1(\blk00000003/blk000007dc/sig00001902 ), + .A2(\blk00000003/blk000007dc/sig00001902 ), + .A3(\blk00000003/blk000007dc/sig00001901 ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(\blk00000003/sig00000769 ), + .Q(\blk00000003/blk000007dc/sig00001913 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007dc/blk000007fe ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/blk000007dc/sig00001912 ), + .Q(\blk00000003/sig000008af ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000007dc/blk000007fd ( + .A0(\blk00000003/blk000007dc/sig00001901 ), + .A1(\blk00000003/blk000007dc/sig00001902 ), + .A2(\blk00000003/blk000007dc/sig00001902 ), + .A3(\blk00000003/blk000007dc/sig00001901 ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(\blk00000003/sig0000076d ), + .Q(\blk00000003/blk000007dc/sig00001912 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007dc/blk000007fc ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/blk000007dc/sig00001911 ), + .Q(\blk00000003/sig000008b2 ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000007dc/blk000007fb ( + .A0(\blk00000003/blk000007dc/sig00001901 ), + .A1(\blk00000003/blk000007dc/sig00001902 ), + .A2(\blk00000003/blk000007dc/sig00001902 ), + .A3(\blk00000003/blk000007dc/sig00001901 ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(\blk00000003/sig00000767 ), + .Q(\blk00000003/blk000007dc/sig00001911 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007dc/blk000007fa ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/blk000007dc/sig00001910 ), + .Q(\blk00000003/sig000008b3 ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000007dc/blk000007f9 ( + .A0(\blk00000003/blk000007dc/sig00001901 ), + .A1(\blk00000003/blk000007dc/sig00001902 ), + .A2(\blk00000003/blk000007dc/sig00001902 ), + .A3(\blk00000003/blk000007dc/sig00001901 ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(\blk00000003/sig00000765 ), + .Q(\blk00000003/blk000007dc/sig00001910 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007dc/blk000007f8 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/blk000007dc/sig0000190f ), + .Q(\blk00000003/sig000008b5 ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000007dc/blk000007f7 ( + .A0(\blk00000003/blk000007dc/sig00001901 ), + .A1(\blk00000003/blk000007dc/sig00001902 ), + .A2(\blk00000003/blk000007dc/sig00001902 ), + .A3(\blk00000003/blk000007dc/sig00001901 ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(\blk00000003/sig00000761 ), + .Q(\blk00000003/blk000007dc/sig0000190f ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007dc/blk000007f6 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/blk000007dc/sig0000190e ), + .Q(\blk00000003/sig000008b6 ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000007dc/blk000007f5 ( + .A0(\blk00000003/blk000007dc/sig00001901 ), + .A1(\blk00000003/blk000007dc/sig00001902 ), + .A2(\blk00000003/blk000007dc/sig00001902 ), + .A3(\blk00000003/blk000007dc/sig00001901 ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(\blk00000003/sig0000075f ), + .Q(\blk00000003/blk000007dc/sig0000190e ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007dc/blk000007f4 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/blk000007dc/sig0000190d ), + .Q(\blk00000003/sig000008b4 ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000007dc/blk000007f3 ( + .A0(\blk00000003/blk000007dc/sig00001901 ), + .A1(\blk00000003/blk000007dc/sig00001902 ), + .A2(\blk00000003/blk000007dc/sig00001902 ), + .A3(\blk00000003/blk000007dc/sig00001901 ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(\blk00000003/sig00000763 ), + .Q(\blk00000003/blk000007dc/sig0000190d ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007dc/blk000007f2 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/blk000007dc/sig0000190c ), + .Q(\blk00000003/sig000008b7 ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000007dc/blk000007f1 ( + .A0(\blk00000003/blk000007dc/sig00001901 ), + .A1(\blk00000003/blk000007dc/sig00001902 ), + .A2(\blk00000003/blk000007dc/sig00001902 ), + .A3(\blk00000003/blk000007dc/sig00001901 ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(\blk00000003/sig0000075d ), + .Q(\blk00000003/blk000007dc/sig0000190c ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007dc/blk000007f0 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/blk000007dc/sig0000190b ), + .Q(\blk00000003/sig000008b8 ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000007dc/blk000007ef ( + .A0(\blk00000003/blk000007dc/sig00001901 ), + .A1(\blk00000003/blk000007dc/sig00001902 ), + .A2(\blk00000003/blk000007dc/sig00001902 ), + .A3(\blk00000003/blk000007dc/sig00001901 ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(\blk00000003/sig0000075b ), + .Q(\blk00000003/blk000007dc/sig0000190b ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007dc/blk000007ee ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/blk000007dc/sig0000190a ), + .Q(\blk00000003/sig000008ba ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000007dc/blk000007ed ( + .A0(\blk00000003/blk000007dc/sig00001901 ), + .A1(\blk00000003/blk000007dc/sig00001902 ), + .A2(\blk00000003/blk000007dc/sig00001902 ), + .A3(\blk00000003/blk000007dc/sig00001901 ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(\blk00000003/sig00000757 ), + .Q(\blk00000003/blk000007dc/sig0000190a ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007dc/blk000007ec ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/blk000007dc/sig00001909 ), + .Q(\blk00000003/sig000008bb ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000007dc/blk000007eb ( + .A0(\blk00000003/blk000007dc/sig00001901 ), + .A1(\blk00000003/blk000007dc/sig00001902 ), + .A2(\blk00000003/blk000007dc/sig00001902 ), + .A3(\blk00000003/blk000007dc/sig00001901 ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(\blk00000003/sig00000755 ), + .Q(\blk00000003/blk000007dc/sig00001909 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007dc/blk000007ea ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/blk000007dc/sig00001908 ), + .Q(\blk00000003/sig000008b9 ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000007dc/blk000007e9 ( + .A0(\blk00000003/blk000007dc/sig00001901 ), + .A1(\blk00000003/blk000007dc/sig00001902 ), + .A2(\blk00000003/blk000007dc/sig00001902 ), + .A3(\blk00000003/blk000007dc/sig00001901 ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(\blk00000003/sig00000759 ), + .Q(\blk00000003/blk000007dc/sig00001908 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007dc/blk000007e8 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/blk000007dc/sig00001907 ), + .Q(\blk00000003/sig000008bc ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000007dc/blk000007e7 ( + .A0(\blk00000003/blk000007dc/sig00001901 ), + .A1(\blk00000003/blk000007dc/sig00001902 ), + .A2(\blk00000003/blk000007dc/sig00001902 ), + .A3(\blk00000003/blk000007dc/sig00001901 ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(\blk00000003/sig00000753 ), + .Q(\blk00000003/blk000007dc/sig00001907 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007dc/blk000007e6 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/blk000007dc/sig00001906 ), + .Q(\blk00000003/sig000008bd ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000007dc/blk000007e5 ( + .A0(\blk00000003/blk000007dc/sig00001901 ), + .A1(\blk00000003/blk000007dc/sig00001902 ), + .A2(\blk00000003/blk000007dc/sig00001902 ), + .A3(\blk00000003/blk000007dc/sig00001901 ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(\blk00000003/sig00000751 ), + .Q(\blk00000003/blk000007dc/sig00001906 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007dc/blk000007e4 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/blk000007dc/sig00001905 ), + .Q(\blk00000003/sig000008bf ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000007dc/blk000007e3 ( + .A0(\blk00000003/blk000007dc/sig00001901 ), + .A1(\blk00000003/blk000007dc/sig00001902 ), + .A2(\blk00000003/blk000007dc/sig00001902 ), + .A3(\blk00000003/blk000007dc/sig00001901 ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(\blk00000003/sig0000074d ), + .Q(\blk00000003/blk000007dc/sig00001905 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007dc/blk000007e2 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/blk000007dc/sig00001904 ), + .Q(\blk00000003/sig000008c0 ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000007dc/blk000007e1 ( + .A0(\blk00000003/blk000007dc/sig00001901 ), + .A1(\blk00000003/blk000007dc/sig00001902 ), + .A2(\blk00000003/blk000007dc/sig00001902 ), + .A3(\blk00000003/blk000007dc/sig00001901 ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(\blk00000003/sig0000074b ), + .Q(\blk00000003/blk000007dc/sig00001904 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000007dc/blk000007e0 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/blk000007dc/sig00001903 ), + .Q(\blk00000003/sig000008be ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000007dc/blk000007df ( + .A0(\blk00000003/blk000007dc/sig00001901 ), + .A1(\blk00000003/blk000007dc/sig00001902 ), + .A2(\blk00000003/blk000007dc/sig00001902 ), + .A3(\blk00000003/blk000007dc/sig00001901 ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(\blk00000003/sig0000074f ), + .Q(\blk00000003/blk000007dc/sig00001903 ) + ); + VCC \blk00000003/blk000007dc/blk000007de ( + .P(\blk00000003/blk000007dc/sig00001902 ) + ); + GND \blk00000003/blk000007dc/blk000007dd ( + .G(\blk00000003/blk000007dc/sig00001901 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000807/blk00000831 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/blk00000807/sig00001956 ), + .Q(\blk00000003/sig000008c1 ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000807/blk00000830 ( + .A0(\blk00000003/blk00000807/sig00001941 ), + .A1(\blk00000003/blk00000807/sig00001942 ), + .A2(\blk00000003/blk00000807/sig00001942 ), + .A3(\blk00000003/blk00000807/sig00001941 ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(\blk00000003/sig00000899 ), + .Q(\blk00000003/blk00000807/sig00001956 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000807/blk0000082f ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/blk00000807/sig00001955 ), + .Q(\blk00000003/sig000008c2 ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000807/blk0000082e ( + .A0(\blk00000003/blk00000807/sig00001941 ), + .A1(\blk00000003/blk00000807/sig00001942 ), + .A2(\blk00000003/blk00000807/sig00001942 ), + .A3(\blk00000003/blk00000807/sig00001941 ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(\blk00000003/sig0000089a ), + .Q(\blk00000003/blk00000807/sig00001955 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000807/blk0000082d ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/blk00000807/sig00001954 ), + .Q(\blk00000003/sig000008c4 ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000807/blk0000082c ( + .A0(\blk00000003/blk00000807/sig00001941 ), + .A1(\blk00000003/blk00000807/sig00001942 ), + .A2(\blk00000003/blk00000807/sig00001942 ), + .A3(\blk00000003/blk00000807/sig00001941 ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(\blk00000003/sig0000089c ), + .Q(\blk00000003/blk00000807/sig00001954 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000807/blk0000082b ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/blk00000807/sig00001953 ), + .Q(\blk00000003/sig000008c5 ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000807/blk0000082a ( + .A0(\blk00000003/blk00000807/sig00001941 ), + .A1(\blk00000003/blk00000807/sig00001942 ), + .A2(\blk00000003/blk00000807/sig00001942 ), + .A3(\blk00000003/blk00000807/sig00001941 ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(\blk00000003/sig0000089d ), + .Q(\blk00000003/blk00000807/sig00001953 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000807/blk00000829 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/blk00000807/sig00001952 ), + .Q(\blk00000003/sig000008c3 ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000807/blk00000828 ( + .A0(\blk00000003/blk00000807/sig00001941 ), + .A1(\blk00000003/blk00000807/sig00001942 ), + .A2(\blk00000003/blk00000807/sig00001942 ), + .A3(\blk00000003/blk00000807/sig00001941 ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(\blk00000003/sig0000089b ), + .Q(\blk00000003/blk00000807/sig00001952 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000807/blk00000827 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/blk00000807/sig00001951 ), + .Q(\blk00000003/sig000008c6 ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000807/blk00000826 ( + .A0(\blk00000003/blk00000807/sig00001941 ), + .A1(\blk00000003/blk00000807/sig00001942 ), + .A2(\blk00000003/blk00000807/sig00001942 ), + .A3(\blk00000003/blk00000807/sig00001941 ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(\blk00000003/sig0000089e ), + .Q(\blk00000003/blk00000807/sig00001951 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000807/blk00000825 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/blk00000807/sig00001950 ), + .Q(\blk00000003/sig000008c7 ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000807/blk00000824 ( + .A0(\blk00000003/blk00000807/sig00001941 ), + .A1(\blk00000003/blk00000807/sig00001942 ), + .A2(\blk00000003/blk00000807/sig00001942 ), + .A3(\blk00000003/blk00000807/sig00001941 ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(\blk00000003/sig0000089f ), + .Q(\blk00000003/blk00000807/sig00001950 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000807/blk00000823 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/blk00000807/sig0000194f ), + .Q(\blk00000003/sig000008c9 ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000807/blk00000822 ( + .A0(\blk00000003/blk00000807/sig00001941 ), + .A1(\blk00000003/blk00000807/sig00001942 ), + .A2(\blk00000003/blk00000807/sig00001942 ), + .A3(\blk00000003/blk00000807/sig00001941 ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(\blk00000003/sig000008a1 ), + .Q(\blk00000003/blk00000807/sig0000194f ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000807/blk00000821 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/blk00000807/sig0000194e ), + .Q(\blk00000003/sig000008ca ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000807/blk00000820 ( + .A0(\blk00000003/blk00000807/sig00001941 ), + .A1(\blk00000003/blk00000807/sig00001942 ), + .A2(\blk00000003/blk00000807/sig00001942 ), + .A3(\blk00000003/blk00000807/sig00001941 ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(\blk00000003/sig000008a2 ), + .Q(\blk00000003/blk00000807/sig0000194e ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000807/blk0000081f ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/blk00000807/sig0000194d ), + .Q(\blk00000003/sig000008c8 ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000807/blk0000081e ( + .A0(\blk00000003/blk00000807/sig00001941 ), + .A1(\blk00000003/blk00000807/sig00001942 ), + .A2(\blk00000003/blk00000807/sig00001942 ), + .A3(\blk00000003/blk00000807/sig00001941 ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(\blk00000003/sig000008a0 ), + .Q(\blk00000003/blk00000807/sig0000194d ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000807/blk0000081d ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/blk00000807/sig0000194c ), + .Q(\blk00000003/sig000008cb ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000807/blk0000081c ( + .A0(\blk00000003/blk00000807/sig00001941 ), + .A1(\blk00000003/blk00000807/sig00001942 ), + .A2(\blk00000003/blk00000807/sig00001942 ), + .A3(\blk00000003/blk00000807/sig00001941 ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(\blk00000003/sig000008a3 ), + .Q(\blk00000003/blk00000807/sig0000194c ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000807/blk0000081b ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/blk00000807/sig0000194b ), + .Q(\blk00000003/sig000008cc ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000807/blk0000081a ( + .A0(\blk00000003/blk00000807/sig00001941 ), + .A1(\blk00000003/blk00000807/sig00001942 ), + .A2(\blk00000003/blk00000807/sig00001942 ), + .A3(\blk00000003/blk00000807/sig00001941 ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(\blk00000003/sig000008a4 ), + .Q(\blk00000003/blk00000807/sig0000194b ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000807/blk00000819 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/blk00000807/sig0000194a ), + .Q(\blk00000003/sig000008ce ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000807/blk00000818 ( + .A0(\blk00000003/blk00000807/sig00001941 ), + .A1(\blk00000003/blk00000807/sig00001942 ), + .A2(\blk00000003/blk00000807/sig00001942 ), + .A3(\blk00000003/blk00000807/sig00001941 ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(\blk00000003/sig000008a6 ), + .Q(\blk00000003/blk00000807/sig0000194a ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000807/blk00000817 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/blk00000807/sig00001949 ), + .Q(\blk00000003/sig000008cf ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000807/blk00000816 ( + .A0(\blk00000003/blk00000807/sig00001941 ), + .A1(\blk00000003/blk00000807/sig00001942 ), + .A2(\blk00000003/blk00000807/sig00001942 ), + .A3(\blk00000003/blk00000807/sig00001941 ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(\blk00000003/sig000008a7 ), + .Q(\blk00000003/blk00000807/sig00001949 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000807/blk00000815 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/blk00000807/sig00001948 ), + .Q(\blk00000003/sig000008cd ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000807/blk00000814 ( + .A0(\blk00000003/blk00000807/sig00001941 ), + .A1(\blk00000003/blk00000807/sig00001942 ), + .A2(\blk00000003/blk00000807/sig00001942 ), + .A3(\blk00000003/blk00000807/sig00001941 ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(\blk00000003/sig000008a5 ), + .Q(\blk00000003/blk00000807/sig00001948 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000807/blk00000813 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/blk00000807/sig00001947 ), + .Q(\blk00000003/sig000008d0 ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000807/blk00000812 ( + .A0(\blk00000003/blk00000807/sig00001941 ), + .A1(\blk00000003/blk00000807/sig00001942 ), + .A2(\blk00000003/blk00000807/sig00001942 ), + .A3(\blk00000003/blk00000807/sig00001941 ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(\blk00000003/sig000008a8 ), + .Q(\blk00000003/blk00000807/sig00001947 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000807/blk00000811 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/blk00000807/sig00001946 ), + .Q(\blk00000003/sig000008d1 ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000807/blk00000810 ( + .A0(\blk00000003/blk00000807/sig00001941 ), + .A1(\blk00000003/blk00000807/sig00001942 ), + .A2(\blk00000003/blk00000807/sig00001942 ), + .A3(\blk00000003/blk00000807/sig00001941 ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(\blk00000003/sig000008a9 ), + .Q(\blk00000003/blk00000807/sig00001946 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000807/blk0000080f ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/blk00000807/sig00001945 ), + .Q(\blk00000003/sig000008d3 ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000807/blk0000080e ( + .A0(\blk00000003/blk00000807/sig00001941 ), + .A1(\blk00000003/blk00000807/sig00001942 ), + .A2(\blk00000003/blk00000807/sig00001942 ), + .A3(\blk00000003/blk00000807/sig00001941 ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(\blk00000003/sig000008ab ), + .Q(\blk00000003/blk00000807/sig00001945 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000807/blk0000080d ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/blk00000807/sig00001944 ), + .Q(\blk00000003/sig000008d4 ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000807/blk0000080c ( + .A0(\blk00000003/blk00000807/sig00001941 ), + .A1(\blk00000003/blk00000807/sig00001942 ), + .A2(\blk00000003/blk00000807/sig00001942 ), + .A3(\blk00000003/blk00000807/sig00001941 ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(\blk00000003/sig000008ac ), + .Q(\blk00000003/blk00000807/sig00001944 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000807/blk0000080b ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/blk00000807/sig00001943 ), + .Q(\blk00000003/sig000008d2 ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000807/blk0000080a ( + .A0(\blk00000003/blk00000807/sig00001941 ), + .A1(\blk00000003/blk00000807/sig00001942 ), + .A2(\blk00000003/blk00000807/sig00001942 ), + .A3(\blk00000003/blk00000807/sig00001941 ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(\blk00000003/sig000008aa ), + .Q(\blk00000003/blk00000807/sig00001943 ) + ); + VCC \blk00000003/blk00000807/blk00000809 ( + .P(\blk00000003/blk00000807/sig00001942 ) + ); + GND \blk00000003/blk00000807/blk00000808 ( + .G(\blk00000003/blk00000807/sig00001941 ) + ); + FD #( + .INIT ( 1'b0 )) + \blk00000003/blk00000832/blk0000083a ( + .C(clk), + .D(\blk00000003/blk00000832/sig00001961 ), + .Q(\blk00000003/sig000008d5 ) + ); + SRL16 #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000832/blk00000839 ( + .A0(\blk00000003/blk00000832/sig0000195d ), + .A1(\blk00000003/blk00000832/sig0000195c ), + .A2(\blk00000003/blk00000832/sig0000195d ), + .A3(\blk00000003/blk00000832/sig0000195d ), + .CLK(clk), + .D(\blk00000003/blk00000832/sig00001960 ), + .Q(\blk00000003/blk00000832/sig00001961 ) + ); + SRLC16 #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000832/blk00000838 ( + .A0(\blk00000003/blk00000832/sig0000195d ), + .A1(\blk00000003/blk00000832/sig0000195d ), + .A2(\blk00000003/blk00000832/sig0000195d ), + .A3(\blk00000003/blk00000832/sig0000195d ), + .CLK(clk), + .D(\blk00000003/sig000006f4 ), + .Q(\NLW_blk00000003/blk00000832/blk00000838_Q_UNCONNECTED ), + .Q15(\blk00000003/blk00000832/sig00001960 ) + ); + FD #( + .INIT ( 1'b0 )) + \blk00000003/blk00000832/blk00000837 ( + .C(clk), + .D(\blk00000003/blk00000832/sig0000195f ), + .Q(\blk00000003/sig000008d6 ) + ); + SRL16 #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000832/blk00000836 ( + .A0(\blk00000003/blk00000832/sig0000195d ), + .A1(\blk00000003/blk00000832/sig0000195c ), + .A2(\blk00000003/blk00000832/sig0000195d ), + .A3(\blk00000003/blk00000832/sig0000195d ), + .CLK(clk), + .D(\blk00000003/blk00000832/sig0000195e ), + .Q(\blk00000003/blk00000832/sig0000195f ) + ); + SRLC16 #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000832/blk00000835 ( + .A0(\blk00000003/blk00000832/sig0000195d ), + .A1(\blk00000003/blk00000832/sig0000195d ), + .A2(\blk00000003/blk00000832/sig0000195d ), + .A3(\blk00000003/blk00000832/sig0000195d ), + .CLK(clk), + .D(\blk00000003/sig000006f6 ), + .Q(\NLW_blk00000003/blk00000832/blk00000835_Q_UNCONNECTED ), + .Q15(\blk00000003/blk00000832/sig0000195e ) + ); + VCC \blk00000003/blk00000832/blk00000834 ( + .P(\blk00000003/blk00000832/sig0000195d ) + ); + GND \blk00000003/blk00000832/blk00000833 ( + .G(\blk00000003/blk00000832/sig0000195c ) + ); + FD #( + .INIT ( 1'b0 )) + \blk00000003/blk0000083b/blk00000840 ( + .C(clk), + .D(\blk00000003/blk0000083b/sig00001968 ), + .Q(\blk00000003/sig00000717 ) + ); + SRL16 #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000083b/blk0000083f ( + .A0(\blk00000003/blk0000083b/sig00001965 ), + .A1(\blk00000003/blk0000083b/sig00001965 ), + .A2(\blk00000003/blk0000083b/sig00001966 ), + .A3(\blk00000003/blk0000083b/sig00001966 ), + .CLK(clk), + .D(\blk00000003/blk0000083b/sig00001967 ), + .Q(\blk00000003/blk0000083b/sig00001968 ) + ); + SRLC16 #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000083b/blk0000083e ( + .A0(\blk00000003/blk0000083b/sig00001966 ), + .A1(\blk00000003/blk0000083b/sig00001966 ), + .A2(\blk00000003/blk0000083b/sig00001966 ), + .A3(\blk00000003/blk0000083b/sig00001966 ), + .CLK(clk), + .D(\blk00000003/sig00000719 ), + .Q(\NLW_blk00000003/blk0000083b/blk0000083e_Q_UNCONNECTED ), + .Q15(\blk00000003/blk0000083b/sig00001967 ) + ); + VCC \blk00000003/blk0000083b/blk0000083d ( + .P(\blk00000003/blk0000083b/sig00001966 ) + ); + GND \blk00000003/blk0000083b/blk0000083c ( + .G(\blk00000003/blk0000083b/sig00001965 ) + ); + FD #( + .INIT ( 1'b0 )) + \blk00000003/blk00000841/blk00000845 ( + .C(clk), + .D(\blk00000003/blk00000841/sig0000196e ), + .Q(\blk00000003/sig000008d7 ) + ); + SRL16 #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000841/blk00000844 ( + .A0(\blk00000003/blk00000841/sig0000196d ), + .A1(\blk00000003/blk00000841/sig0000196c ), + .A2(\blk00000003/blk00000841/sig0000196c ), + .A3(\blk00000003/blk00000841/sig0000196d ), + .CLK(clk), + .D(\blk00000003/sig0000071c ), + .Q(\blk00000003/blk00000841/sig0000196e ) + ); + VCC \blk00000003/blk00000841/blk00000843 ( + .P(\blk00000003/blk00000841/sig0000196d ) + ); + GND \blk00000003/blk00000841/blk00000842 ( + .G(\blk00000003/blk00000841/sig0000196c ) + ); + FD #( + .INIT ( 1'b0 )) + \blk00000003/blk00000846/blk0000084b ( + .C(clk), + .D(\blk00000003/blk00000846/sig00001975 ), + .Q(\blk00000003/sig000008d8 ) + ); + SRL16 #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000846/blk0000084a ( + .A0(\blk00000003/blk00000846/sig00001973 ), + .A1(\blk00000003/blk00000846/sig00001972 ), + .A2(\blk00000003/blk00000846/sig00001973 ), + .A3(\blk00000003/blk00000846/sig00001973 ), + .CLK(clk), + .D(\blk00000003/blk00000846/sig00001974 ), + .Q(\blk00000003/blk00000846/sig00001975 ) + ); + SRLC16 #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000846/blk00000849 ( + .A0(\blk00000003/blk00000846/sig00001973 ), + .A1(\blk00000003/blk00000846/sig00001973 ), + .A2(\blk00000003/blk00000846/sig00001973 ), + .A3(\blk00000003/blk00000846/sig00001973 ), + .CLK(clk), + .D(\blk00000003/sig000006e8 ), + .Q(\NLW_blk00000003/blk00000846/blk00000849_Q_UNCONNECTED ), + .Q15(\blk00000003/blk00000846/sig00001974 ) + ); + VCC \blk00000003/blk00000846/blk00000848 ( + .P(\blk00000003/blk00000846/sig00001973 ) + ); + GND \blk00000003/blk00000846/blk00000847 ( + .G(\blk00000003/blk00000846/sig00001972 ) + ); + FD #( + .INIT ( 1'b0 )) + \blk00000003/blk0000084c/blk00000852 ( + .C(clk), + .D(\blk00000003/blk0000084c/sig0000197e ), + .Q(\blk00000003/sig000008d9 ) + ); + SRL16 #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000084c/blk00000851 ( + .A0(\blk00000003/blk0000084c/sig0000197b ), + .A1(\blk00000003/blk0000084c/sig0000197b ), + .A2(\blk00000003/blk0000084c/sig0000197b ), + .A3(\blk00000003/blk0000084c/sig0000197c ), + .CLK(clk), + .D(\blk00000003/sig00000723 ), + .Q(\blk00000003/blk0000084c/sig0000197e ) + ); + FD #( + .INIT ( 1'b0 )) + \blk00000003/blk0000084c/blk00000850 ( + .C(clk), + .D(\blk00000003/blk0000084c/sig0000197d ), + .Q(\blk00000003/sig000008da ) + ); + SRL16 #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000084c/blk0000084f ( + .A0(\blk00000003/blk0000084c/sig0000197b ), + .A1(\blk00000003/blk0000084c/sig0000197b ), + .A2(\blk00000003/blk0000084c/sig0000197b ), + .A3(\blk00000003/blk0000084c/sig0000197c ), + .CLK(clk), + .D(\blk00000003/sig00000725 ), + .Q(\blk00000003/blk0000084c/sig0000197d ) + ); + VCC \blk00000003/blk0000084c/blk0000084e ( + .P(\blk00000003/blk0000084c/sig0000197c ) + ); + GND \blk00000003/blk0000084c/blk0000084d ( + .G(\blk00000003/blk0000084c/sig0000197b ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000853/blk00000856 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/blk00000853/sig00001984 ), + .Q(\blk00000003/sig000008dc ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000853/blk00000855 ( + .A0(\blk00000003/blk00000853/sig00001983 ), + .A1(\blk00000003/blk00000853/sig00001983 ), + .A2(\blk00000003/blk00000853/sig00001983 ), + .A3(\blk00000003/blk00000853/sig00001983 ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(\blk00000003/sig000008db ), + .Q(\blk00000003/blk00000853/sig00001984 ) + ); + GND \blk00000003/blk00000853/blk00000854 ( + .G(\blk00000003/blk00000853/sig00001983 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000857/blk0000085a ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/blk00000857/sig0000198a ), + .Q(\blk00000003/sig000008dd ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000857/blk00000859 ( + .A0(\blk00000003/blk00000857/sig00001989 ), + .A1(\blk00000003/blk00000857/sig00001989 ), + .A2(\blk00000003/blk00000857/sig00001989 ), + .A3(\blk00000003/blk00000857/sig00001989 ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(\blk00000003/sig000008dc ), + .Q(\blk00000003/blk00000857/sig0000198a ) + ); + GND \blk00000003/blk00000857/blk00000858 ( + .G(\blk00000003/blk00000857/sig00001989 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000085b/blk0000085f ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/blk0000085b/sig00001991 ), + .Q(\blk00000003/sig000008de ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000085b/blk0000085e ( + .A0(\blk00000003/blk0000085b/sig0000198f ), + .A1(\blk00000003/blk0000085b/sig00001990 ), + .A2(\blk00000003/blk0000085b/sig0000198f ), + .A3(\blk00000003/blk0000085b/sig0000198f ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(\blk00000003/sig000008dd ), + .Q(\blk00000003/blk0000085b/sig00001991 ) + ); + VCC \blk00000003/blk0000085b/blk0000085d ( + .P(\blk00000003/blk0000085b/sig00001990 ) + ); + GND \blk00000003/blk0000085b/blk0000085c ( + .G(\blk00000003/blk0000085b/sig0000198f ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000961/blk0000098d ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/blk00000961/sig000019d4 ), + .Q(\blk00000003/sig00000a5e ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000961/blk0000098c ( + .A0(\blk00000003/blk00000961/sig000019be ), + .A1(\blk00000003/blk00000961/sig000019bf ), + .A2(\blk00000003/blk00000961/sig000019be ), + .A3(\blk00000003/blk00000961/sig000019be ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(\blk00000003/sig000009dc ), + .Q(\blk00000003/blk00000961/sig000019d4 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000961/blk0000098b ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/blk00000961/sig000019d3 ), + .Q(\blk00000003/sig00000a5f ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000961/blk0000098a ( + .A0(\blk00000003/blk00000961/sig000019be ), + .A1(\blk00000003/blk00000961/sig000019bf ), + .A2(\blk00000003/blk00000961/sig000019be ), + .A3(\blk00000003/blk00000961/sig000019be ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(\blk00000003/sig000009da ), + .Q(\blk00000003/blk00000961/sig000019d3 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000961/blk00000989 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/blk00000961/sig000019d2 ), + .Q(\blk00000003/sig00000a61 ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000961/blk00000988 ( + .A0(\blk00000003/blk00000961/sig000019be ), + .A1(\blk00000003/blk00000961/sig000019bf ), + .A2(\blk00000003/blk00000961/sig000019be ), + .A3(\blk00000003/blk00000961/sig000019be ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(\blk00000003/sig000009d6 ), + .Q(\blk00000003/blk00000961/sig000019d2 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000961/blk00000987 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/blk00000961/sig000019d1 ), + .Q(\blk00000003/sig00000a62 ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000961/blk00000986 ( + .A0(\blk00000003/blk00000961/sig000019be ), + .A1(\blk00000003/blk00000961/sig000019bf ), + .A2(\blk00000003/blk00000961/sig000019be ), + .A3(\blk00000003/blk00000961/sig000019be ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(\blk00000003/sig000009d4 ), + .Q(\blk00000003/blk00000961/sig000019d1 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000961/blk00000985 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/blk00000961/sig000019d0 ), + .Q(\blk00000003/sig00000a60 ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000961/blk00000984 ( + .A0(\blk00000003/blk00000961/sig000019be ), + .A1(\blk00000003/blk00000961/sig000019bf ), + .A2(\blk00000003/blk00000961/sig000019be ), + .A3(\blk00000003/blk00000961/sig000019be ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(\blk00000003/sig000009d8 ), + .Q(\blk00000003/blk00000961/sig000019d0 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000961/blk00000983 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/blk00000961/sig000019cf ), + .Q(\blk00000003/sig00000a63 ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000961/blk00000982 ( + .A0(\blk00000003/blk00000961/sig000019be ), + .A1(\blk00000003/blk00000961/sig000019bf ), + .A2(\blk00000003/blk00000961/sig000019be ), + .A3(\blk00000003/blk00000961/sig000019be ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(\blk00000003/sig000009d2 ), + .Q(\blk00000003/blk00000961/sig000019cf ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000961/blk00000981 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/blk00000961/sig000019ce ), + .Q(\blk00000003/sig00000a64 ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000961/blk00000980 ( + .A0(\blk00000003/blk00000961/sig000019be ), + .A1(\blk00000003/blk00000961/sig000019bf ), + .A2(\blk00000003/blk00000961/sig000019be ), + .A3(\blk00000003/blk00000961/sig000019be ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(\blk00000003/sig000009d0 ), + .Q(\blk00000003/blk00000961/sig000019ce ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000961/blk0000097f ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/blk00000961/sig000019cd ), + .Q(\blk00000003/sig00000a66 ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000961/blk0000097e ( + .A0(\blk00000003/blk00000961/sig000019be ), + .A1(\blk00000003/blk00000961/sig000019bf ), + .A2(\blk00000003/blk00000961/sig000019be ), + .A3(\blk00000003/blk00000961/sig000019be ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(\blk00000003/sig000009cc ), + .Q(\blk00000003/blk00000961/sig000019cd ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000961/blk0000097d ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/blk00000961/sig000019cc ), + .Q(\blk00000003/sig00000a67 ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000961/blk0000097c ( + .A0(\blk00000003/blk00000961/sig000019be ), + .A1(\blk00000003/blk00000961/sig000019bf ), + .A2(\blk00000003/blk00000961/sig000019be ), + .A3(\blk00000003/blk00000961/sig000019be ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(\blk00000003/sig000009ca ), + .Q(\blk00000003/blk00000961/sig000019cc ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000961/blk0000097b ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/blk00000961/sig000019cb ), + .Q(\blk00000003/sig00000a65 ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000961/blk0000097a ( + .A0(\blk00000003/blk00000961/sig000019be ), + .A1(\blk00000003/blk00000961/sig000019bf ), + .A2(\blk00000003/blk00000961/sig000019be ), + .A3(\blk00000003/blk00000961/sig000019be ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(\blk00000003/sig000009ce ), + .Q(\blk00000003/blk00000961/sig000019cb ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000961/blk00000979 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/blk00000961/sig000019ca ), + .Q(\blk00000003/sig00000a68 ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000961/blk00000978 ( + .A0(\blk00000003/blk00000961/sig000019be ), + .A1(\blk00000003/blk00000961/sig000019bf ), + .A2(\blk00000003/blk00000961/sig000019be ), + .A3(\blk00000003/blk00000961/sig000019be ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(\blk00000003/sig000009c8 ), + .Q(\blk00000003/blk00000961/sig000019ca ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000961/blk00000977 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/blk00000961/sig000019c9 ), + .Q(\blk00000003/sig00000a69 ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000961/blk00000976 ( + .A0(\blk00000003/blk00000961/sig000019be ), + .A1(\blk00000003/blk00000961/sig000019bf ), + .A2(\blk00000003/blk00000961/sig000019be ), + .A3(\blk00000003/blk00000961/sig000019be ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(\blk00000003/sig000009c6 ), + .Q(\blk00000003/blk00000961/sig000019c9 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000961/blk00000975 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/blk00000961/sig000019c8 ), + .Q(\blk00000003/sig00000a6b ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000961/blk00000974 ( + .A0(\blk00000003/blk00000961/sig000019be ), + .A1(\blk00000003/blk00000961/sig000019bf ), + .A2(\blk00000003/blk00000961/sig000019be ), + .A3(\blk00000003/blk00000961/sig000019be ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(\blk00000003/sig000009c2 ), + .Q(\blk00000003/blk00000961/sig000019c8 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000961/blk00000973 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/blk00000961/sig000019c7 ), + .Q(\blk00000003/sig00000a6c ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000961/blk00000972 ( + .A0(\blk00000003/blk00000961/sig000019be ), + .A1(\blk00000003/blk00000961/sig000019bf ), + .A2(\blk00000003/blk00000961/sig000019be ), + .A3(\blk00000003/blk00000961/sig000019be ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(\blk00000003/sig000009c0 ), + .Q(\blk00000003/blk00000961/sig000019c7 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000961/blk00000971 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/blk00000961/sig000019c6 ), + .Q(\blk00000003/sig00000a6a ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000961/blk00000970 ( + .A0(\blk00000003/blk00000961/sig000019be ), + .A1(\blk00000003/blk00000961/sig000019bf ), + .A2(\blk00000003/blk00000961/sig000019be ), + .A3(\blk00000003/blk00000961/sig000019be ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(\blk00000003/sig000009c4 ), + .Q(\blk00000003/blk00000961/sig000019c6 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000961/blk0000096f ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/blk00000961/sig000019c5 ), + .Q(\blk00000003/sig00000a6e ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000961/blk0000096e ( + .A0(\blk00000003/blk00000961/sig000019be ), + .A1(\blk00000003/blk00000961/sig000019bf ), + .A2(\blk00000003/blk00000961/sig000019be ), + .A3(\blk00000003/blk00000961/sig000019be ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(\blk00000003/sig000009bc ), + .Q(\blk00000003/blk00000961/sig000019c5 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000961/blk0000096d ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/blk00000961/sig000019c4 ), + .Q(\blk00000003/sig00000a6f ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000961/blk0000096c ( + .A0(\blk00000003/blk00000961/sig000019be ), + .A1(\blk00000003/blk00000961/sig000019bf ), + .A2(\blk00000003/blk00000961/sig000019be ), + .A3(\blk00000003/blk00000961/sig000019be ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(\blk00000003/sig000009ba ), + .Q(\blk00000003/blk00000961/sig000019c4 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000961/blk0000096b ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/blk00000961/sig000019c3 ), + .Q(\blk00000003/sig00000a6d ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000961/blk0000096a ( + .A0(\blk00000003/blk00000961/sig000019be ), + .A1(\blk00000003/blk00000961/sig000019bf ), + .A2(\blk00000003/blk00000961/sig000019be ), + .A3(\blk00000003/blk00000961/sig000019be ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(\blk00000003/sig000009be ), + .Q(\blk00000003/blk00000961/sig000019c3 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000961/blk00000969 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/blk00000961/sig000019c2 ), + .Q(\blk00000003/sig00000a71 ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000961/blk00000968 ( + .A0(\blk00000003/blk00000961/sig000019be ), + .A1(\blk00000003/blk00000961/sig000019bf ), + .A2(\blk00000003/blk00000961/sig000019be ), + .A3(\blk00000003/blk00000961/sig000019be ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(\blk00000003/sig000009b6 ), + .Q(\blk00000003/blk00000961/sig000019c2 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000961/blk00000967 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/blk00000961/sig000019c1 ), + .Q(\blk00000003/sig00000a72 ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000961/blk00000966 ( + .A0(\blk00000003/blk00000961/sig000019be ), + .A1(\blk00000003/blk00000961/sig000019bf ), + .A2(\blk00000003/blk00000961/sig000019be ), + .A3(\blk00000003/blk00000961/sig000019be ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(\blk00000003/sig000009b4 ), + .Q(\blk00000003/blk00000961/sig000019c1 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000961/blk00000965 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/blk00000961/sig000019c0 ), + .Q(\blk00000003/sig00000a70 ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000961/blk00000964 ( + .A0(\blk00000003/blk00000961/sig000019be ), + .A1(\blk00000003/blk00000961/sig000019bf ), + .A2(\blk00000003/blk00000961/sig000019be ), + .A3(\blk00000003/blk00000961/sig000019be ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(\blk00000003/sig000009b8 ), + .Q(\blk00000003/blk00000961/sig000019c0 ) + ); + VCC \blk00000003/blk00000961/blk00000963 ( + .P(\blk00000003/blk00000961/sig000019bf ) + ); + GND \blk00000003/blk00000961/blk00000962 ( + .G(\blk00000003/blk00000961/sig000019be ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000098e/blk000009ba ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/blk0000098e/sig00001a17 ), + .Q(\blk00000003/sig00000a88 ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000098e/blk000009b9 ( + .A0(\blk00000003/blk0000098e/sig00001a01 ), + .A1(\blk00000003/blk0000098e/sig00001a02 ), + .A2(\blk00000003/blk0000098e/sig00001a01 ), + .A3(\blk00000003/blk0000098e/sig00001a01 ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(\blk00000003/sig00000a73 ), + .Q(\blk00000003/blk0000098e/sig00001a17 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000098e/blk000009b8 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/blk0000098e/sig00001a16 ), + .Q(\blk00000003/sig00000a89 ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000098e/blk000009b7 ( + .A0(\blk00000003/blk0000098e/sig00001a01 ), + .A1(\blk00000003/blk0000098e/sig00001a02 ), + .A2(\blk00000003/blk0000098e/sig00001a01 ), + .A3(\blk00000003/blk0000098e/sig00001a01 ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(\blk00000003/sig00000a74 ), + .Q(\blk00000003/blk0000098e/sig00001a16 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000098e/blk000009b6 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/blk0000098e/sig00001a15 ), + .Q(\blk00000003/sig00000a8b ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000098e/blk000009b5 ( + .A0(\blk00000003/blk0000098e/sig00001a01 ), + .A1(\blk00000003/blk0000098e/sig00001a02 ), + .A2(\blk00000003/blk0000098e/sig00001a01 ), + .A3(\blk00000003/blk0000098e/sig00001a01 ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(\blk00000003/sig00000a76 ), + .Q(\blk00000003/blk0000098e/sig00001a15 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000098e/blk000009b4 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/blk0000098e/sig00001a14 ), + .Q(\blk00000003/sig00000a8c ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000098e/blk000009b3 ( + .A0(\blk00000003/blk0000098e/sig00001a01 ), + .A1(\blk00000003/blk0000098e/sig00001a02 ), + .A2(\blk00000003/blk0000098e/sig00001a01 ), + .A3(\blk00000003/blk0000098e/sig00001a01 ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(\blk00000003/sig00000a77 ), + .Q(\blk00000003/blk0000098e/sig00001a14 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000098e/blk000009b2 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/blk0000098e/sig00001a13 ), + .Q(\blk00000003/sig00000a8a ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000098e/blk000009b1 ( + .A0(\blk00000003/blk0000098e/sig00001a01 ), + .A1(\blk00000003/blk0000098e/sig00001a02 ), + .A2(\blk00000003/blk0000098e/sig00001a01 ), + .A3(\blk00000003/blk0000098e/sig00001a01 ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(\blk00000003/sig00000a75 ), + .Q(\blk00000003/blk0000098e/sig00001a13 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000098e/blk000009b0 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/blk0000098e/sig00001a12 ), + .Q(\blk00000003/sig00000a8d ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000098e/blk000009af ( + .A0(\blk00000003/blk0000098e/sig00001a01 ), + .A1(\blk00000003/blk0000098e/sig00001a02 ), + .A2(\blk00000003/blk0000098e/sig00001a01 ), + .A3(\blk00000003/blk0000098e/sig00001a01 ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(\blk00000003/sig00000a78 ), + .Q(\blk00000003/blk0000098e/sig00001a12 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000098e/blk000009ae ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/blk0000098e/sig00001a11 ), + .Q(\blk00000003/sig00000a8e ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000098e/blk000009ad ( + .A0(\blk00000003/blk0000098e/sig00001a01 ), + .A1(\blk00000003/blk0000098e/sig00001a02 ), + .A2(\blk00000003/blk0000098e/sig00001a01 ), + .A3(\blk00000003/blk0000098e/sig00001a01 ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(\blk00000003/sig00000a79 ), + .Q(\blk00000003/blk0000098e/sig00001a11 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000098e/blk000009ac ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/blk0000098e/sig00001a10 ), + .Q(\blk00000003/sig00000a90 ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000098e/blk000009ab ( + .A0(\blk00000003/blk0000098e/sig00001a01 ), + .A1(\blk00000003/blk0000098e/sig00001a02 ), + .A2(\blk00000003/blk0000098e/sig00001a01 ), + .A3(\blk00000003/blk0000098e/sig00001a01 ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(\blk00000003/sig00000a7b ), + .Q(\blk00000003/blk0000098e/sig00001a10 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000098e/blk000009aa ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/blk0000098e/sig00001a0f ), + .Q(\blk00000003/sig00000a91 ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000098e/blk000009a9 ( + .A0(\blk00000003/blk0000098e/sig00001a01 ), + .A1(\blk00000003/blk0000098e/sig00001a02 ), + .A2(\blk00000003/blk0000098e/sig00001a01 ), + .A3(\blk00000003/blk0000098e/sig00001a01 ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(\blk00000003/sig00000a7c ), + .Q(\blk00000003/blk0000098e/sig00001a0f ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000098e/blk000009a8 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/blk0000098e/sig00001a0e ), + .Q(\blk00000003/sig00000a8f ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000098e/blk000009a7 ( + .A0(\blk00000003/blk0000098e/sig00001a01 ), + .A1(\blk00000003/blk0000098e/sig00001a02 ), + .A2(\blk00000003/blk0000098e/sig00001a01 ), + .A3(\blk00000003/blk0000098e/sig00001a01 ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(\blk00000003/sig00000a7a ), + .Q(\blk00000003/blk0000098e/sig00001a0e ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000098e/blk000009a6 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/blk0000098e/sig00001a0d ), + .Q(\blk00000003/sig00000a92 ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000098e/blk000009a5 ( + .A0(\blk00000003/blk0000098e/sig00001a01 ), + .A1(\blk00000003/blk0000098e/sig00001a02 ), + .A2(\blk00000003/blk0000098e/sig00001a01 ), + .A3(\blk00000003/blk0000098e/sig00001a01 ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(\blk00000003/sig00000a7d ), + .Q(\blk00000003/blk0000098e/sig00001a0d ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000098e/blk000009a4 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/blk0000098e/sig00001a0c ), + .Q(\blk00000003/sig00000a93 ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000098e/blk000009a3 ( + .A0(\blk00000003/blk0000098e/sig00001a01 ), + .A1(\blk00000003/blk0000098e/sig00001a02 ), + .A2(\blk00000003/blk0000098e/sig00001a01 ), + .A3(\blk00000003/blk0000098e/sig00001a01 ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(\blk00000003/sig00000a7e ), + .Q(\blk00000003/blk0000098e/sig00001a0c ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000098e/blk000009a2 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/blk0000098e/sig00001a0b ), + .Q(\blk00000003/sig00000a95 ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000098e/blk000009a1 ( + .A0(\blk00000003/blk0000098e/sig00001a01 ), + .A1(\blk00000003/blk0000098e/sig00001a02 ), + .A2(\blk00000003/blk0000098e/sig00001a01 ), + .A3(\blk00000003/blk0000098e/sig00001a01 ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(\blk00000003/sig00000a80 ), + .Q(\blk00000003/blk0000098e/sig00001a0b ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000098e/blk000009a0 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/blk0000098e/sig00001a0a ), + .Q(\blk00000003/sig00000a96 ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000098e/blk0000099f ( + .A0(\blk00000003/blk0000098e/sig00001a01 ), + .A1(\blk00000003/blk0000098e/sig00001a02 ), + .A2(\blk00000003/blk0000098e/sig00001a01 ), + .A3(\blk00000003/blk0000098e/sig00001a01 ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(\blk00000003/sig00000a81 ), + .Q(\blk00000003/blk0000098e/sig00001a0a ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000098e/blk0000099e ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/blk0000098e/sig00001a09 ), + .Q(\blk00000003/sig00000a94 ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000098e/blk0000099d ( + .A0(\blk00000003/blk0000098e/sig00001a01 ), + .A1(\blk00000003/blk0000098e/sig00001a02 ), + .A2(\blk00000003/blk0000098e/sig00001a01 ), + .A3(\blk00000003/blk0000098e/sig00001a01 ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(\blk00000003/sig00000a7f ), + .Q(\blk00000003/blk0000098e/sig00001a09 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000098e/blk0000099c ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/blk0000098e/sig00001a08 ), + .Q(\blk00000003/sig00000a98 ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000098e/blk0000099b ( + .A0(\blk00000003/blk0000098e/sig00001a01 ), + .A1(\blk00000003/blk0000098e/sig00001a02 ), + .A2(\blk00000003/blk0000098e/sig00001a01 ), + .A3(\blk00000003/blk0000098e/sig00001a01 ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(\blk00000003/sig00000a83 ), + .Q(\blk00000003/blk0000098e/sig00001a08 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000098e/blk0000099a ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/blk0000098e/sig00001a07 ), + .Q(\blk00000003/sig00000a99 ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000098e/blk00000999 ( + .A0(\blk00000003/blk0000098e/sig00001a01 ), + .A1(\blk00000003/blk0000098e/sig00001a02 ), + .A2(\blk00000003/blk0000098e/sig00001a01 ), + .A3(\blk00000003/blk0000098e/sig00001a01 ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(\blk00000003/sig00000a84 ), + .Q(\blk00000003/blk0000098e/sig00001a07 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000098e/blk00000998 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/blk0000098e/sig00001a06 ), + .Q(\blk00000003/sig00000a97 ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000098e/blk00000997 ( + .A0(\blk00000003/blk0000098e/sig00001a01 ), + .A1(\blk00000003/blk0000098e/sig00001a02 ), + .A2(\blk00000003/blk0000098e/sig00001a01 ), + .A3(\blk00000003/blk0000098e/sig00001a01 ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(\blk00000003/sig00000a82 ), + .Q(\blk00000003/blk0000098e/sig00001a06 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000098e/blk00000996 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/blk0000098e/sig00001a05 ), + .Q(\blk00000003/sig00000a9b ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000098e/blk00000995 ( + .A0(\blk00000003/blk0000098e/sig00001a01 ), + .A1(\blk00000003/blk0000098e/sig00001a02 ), + .A2(\blk00000003/blk0000098e/sig00001a01 ), + .A3(\blk00000003/blk0000098e/sig00001a01 ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(\blk00000003/sig00000a86 ), + .Q(\blk00000003/blk0000098e/sig00001a05 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000098e/blk00000994 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/blk0000098e/sig00001a04 ), + .Q(\blk00000003/sig00000a9c ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000098e/blk00000993 ( + .A0(\blk00000003/blk0000098e/sig00001a01 ), + .A1(\blk00000003/blk0000098e/sig00001a02 ), + .A2(\blk00000003/blk0000098e/sig00001a01 ), + .A3(\blk00000003/blk0000098e/sig00001a01 ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(\blk00000003/sig00000a87 ), + .Q(\blk00000003/blk0000098e/sig00001a04 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000098e/blk00000992 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/blk0000098e/sig00001a03 ), + .Q(\blk00000003/sig00000a9a ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000098e/blk00000991 ( + .A0(\blk00000003/blk0000098e/sig00001a01 ), + .A1(\blk00000003/blk0000098e/sig00001a02 ), + .A2(\blk00000003/blk0000098e/sig00001a01 ), + .A3(\blk00000003/blk0000098e/sig00001a01 ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(\blk00000003/sig00000a85 ), + .Q(\blk00000003/blk0000098e/sig00001a03 ) + ); + VCC \blk00000003/blk0000098e/blk00000990 ( + .P(\blk00000003/blk0000098e/sig00001a02 ) + ); + GND \blk00000003/blk0000098e/blk0000098f ( + .G(\blk00000003/blk0000098e/sig00001a01 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000009bb/blk000009e7 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/blk000009bb/sig00001a5a ), + .Q(\blk00000003/sig00000a9d ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000009bb/blk000009e6 ( + .A0(\blk00000003/blk000009bb/sig00001a44 ), + .A1(\blk00000003/blk000009bb/sig00001a45 ), + .A2(\blk00000003/blk000009bb/sig00001a44 ), + .A3(\blk00000003/blk000009bb/sig00001a44 ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(\blk00000003/sig00000a49 ), + .Q(\blk00000003/blk000009bb/sig00001a5a ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000009bb/blk000009e5 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/blk000009bb/sig00001a59 ), + .Q(\blk00000003/sig00000a9e ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000009bb/blk000009e4 ( + .A0(\blk00000003/blk000009bb/sig00001a44 ), + .A1(\blk00000003/blk000009bb/sig00001a45 ), + .A2(\blk00000003/blk000009bb/sig00001a44 ), + .A3(\blk00000003/blk000009bb/sig00001a44 ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(\blk00000003/sig00000a4a ), + .Q(\blk00000003/blk000009bb/sig00001a59 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000009bb/blk000009e3 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/blk000009bb/sig00001a58 ), + .Q(\blk00000003/sig00000aa0 ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000009bb/blk000009e2 ( + .A0(\blk00000003/blk000009bb/sig00001a44 ), + .A1(\blk00000003/blk000009bb/sig00001a45 ), + .A2(\blk00000003/blk000009bb/sig00001a44 ), + .A3(\blk00000003/blk000009bb/sig00001a44 ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(\blk00000003/sig00000a4c ), + .Q(\blk00000003/blk000009bb/sig00001a58 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000009bb/blk000009e1 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/blk000009bb/sig00001a57 ), + .Q(\blk00000003/sig00000aa1 ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000009bb/blk000009e0 ( + .A0(\blk00000003/blk000009bb/sig00001a44 ), + .A1(\blk00000003/blk000009bb/sig00001a45 ), + .A2(\blk00000003/blk000009bb/sig00001a44 ), + .A3(\blk00000003/blk000009bb/sig00001a44 ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(\blk00000003/sig00000a4d ), + .Q(\blk00000003/blk000009bb/sig00001a57 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000009bb/blk000009df ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/blk000009bb/sig00001a56 ), + .Q(\blk00000003/sig00000a9f ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000009bb/blk000009de ( + .A0(\blk00000003/blk000009bb/sig00001a44 ), + .A1(\blk00000003/blk000009bb/sig00001a45 ), + .A2(\blk00000003/blk000009bb/sig00001a44 ), + .A3(\blk00000003/blk000009bb/sig00001a44 ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(\blk00000003/sig00000a4b ), + .Q(\blk00000003/blk000009bb/sig00001a56 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000009bb/blk000009dd ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/blk000009bb/sig00001a55 ), + .Q(\blk00000003/sig00000aa2 ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000009bb/blk000009dc ( + .A0(\blk00000003/blk000009bb/sig00001a44 ), + .A1(\blk00000003/blk000009bb/sig00001a45 ), + .A2(\blk00000003/blk000009bb/sig00001a44 ), + .A3(\blk00000003/blk000009bb/sig00001a44 ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(\blk00000003/sig00000a4e ), + .Q(\blk00000003/blk000009bb/sig00001a55 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000009bb/blk000009db ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/blk000009bb/sig00001a54 ), + .Q(\blk00000003/sig00000aa3 ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000009bb/blk000009da ( + .A0(\blk00000003/blk000009bb/sig00001a44 ), + .A1(\blk00000003/blk000009bb/sig00001a45 ), + .A2(\blk00000003/blk000009bb/sig00001a44 ), + .A3(\blk00000003/blk000009bb/sig00001a44 ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(\blk00000003/sig00000a4f ), + .Q(\blk00000003/blk000009bb/sig00001a54 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000009bb/blk000009d9 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/blk000009bb/sig00001a53 ), + .Q(\blk00000003/sig00000aa5 ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000009bb/blk000009d8 ( + .A0(\blk00000003/blk000009bb/sig00001a44 ), + .A1(\blk00000003/blk000009bb/sig00001a45 ), + .A2(\blk00000003/blk000009bb/sig00001a44 ), + .A3(\blk00000003/blk000009bb/sig00001a44 ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(\blk00000003/sig00000a51 ), + .Q(\blk00000003/blk000009bb/sig00001a53 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000009bb/blk000009d7 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/blk000009bb/sig00001a52 ), + .Q(\blk00000003/sig00000aa6 ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000009bb/blk000009d6 ( + .A0(\blk00000003/blk000009bb/sig00001a44 ), + .A1(\blk00000003/blk000009bb/sig00001a45 ), + .A2(\blk00000003/blk000009bb/sig00001a44 ), + .A3(\blk00000003/blk000009bb/sig00001a44 ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(\blk00000003/sig00000a52 ), + .Q(\blk00000003/blk000009bb/sig00001a52 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000009bb/blk000009d5 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/blk000009bb/sig00001a51 ), + .Q(\blk00000003/sig00000aa4 ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000009bb/blk000009d4 ( + .A0(\blk00000003/blk000009bb/sig00001a44 ), + .A1(\blk00000003/blk000009bb/sig00001a45 ), + .A2(\blk00000003/blk000009bb/sig00001a44 ), + .A3(\blk00000003/blk000009bb/sig00001a44 ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(\blk00000003/sig00000a50 ), + .Q(\blk00000003/blk000009bb/sig00001a51 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000009bb/blk000009d3 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/blk000009bb/sig00001a50 ), + .Q(\blk00000003/sig00000aa7 ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000009bb/blk000009d2 ( + .A0(\blk00000003/blk000009bb/sig00001a44 ), + .A1(\blk00000003/blk000009bb/sig00001a45 ), + .A2(\blk00000003/blk000009bb/sig00001a44 ), + .A3(\blk00000003/blk000009bb/sig00001a44 ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(\blk00000003/sig00000a53 ), + .Q(\blk00000003/blk000009bb/sig00001a50 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000009bb/blk000009d1 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/blk000009bb/sig00001a4f ), + .Q(\blk00000003/sig00000aa8 ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000009bb/blk000009d0 ( + .A0(\blk00000003/blk000009bb/sig00001a44 ), + .A1(\blk00000003/blk000009bb/sig00001a45 ), + .A2(\blk00000003/blk000009bb/sig00001a44 ), + .A3(\blk00000003/blk000009bb/sig00001a44 ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(\blk00000003/sig00000a54 ), + .Q(\blk00000003/blk000009bb/sig00001a4f ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000009bb/blk000009cf ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/blk000009bb/sig00001a4e ), + .Q(\blk00000003/sig00000aaa ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000009bb/blk000009ce ( + .A0(\blk00000003/blk000009bb/sig00001a44 ), + .A1(\blk00000003/blk000009bb/sig00001a45 ), + .A2(\blk00000003/blk000009bb/sig00001a44 ), + .A3(\blk00000003/blk000009bb/sig00001a44 ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(\blk00000003/sig00000a56 ), + .Q(\blk00000003/blk000009bb/sig00001a4e ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000009bb/blk000009cd ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/blk000009bb/sig00001a4d ), + .Q(\blk00000003/sig00000aab ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000009bb/blk000009cc ( + .A0(\blk00000003/blk000009bb/sig00001a44 ), + .A1(\blk00000003/blk000009bb/sig00001a45 ), + .A2(\blk00000003/blk000009bb/sig00001a44 ), + .A3(\blk00000003/blk000009bb/sig00001a44 ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(\blk00000003/sig00000a57 ), + .Q(\blk00000003/blk000009bb/sig00001a4d ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000009bb/blk000009cb ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/blk000009bb/sig00001a4c ), + .Q(\blk00000003/sig00000aa9 ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000009bb/blk000009ca ( + .A0(\blk00000003/blk000009bb/sig00001a44 ), + .A1(\blk00000003/blk000009bb/sig00001a45 ), + .A2(\blk00000003/blk000009bb/sig00001a44 ), + .A3(\blk00000003/blk000009bb/sig00001a44 ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(\blk00000003/sig00000a55 ), + .Q(\blk00000003/blk000009bb/sig00001a4c ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000009bb/blk000009c9 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/blk000009bb/sig00001a4b ), + .Q(\blk00000003/sig00000aad ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000009bb/blk000009c8 ( + .A0(\blk00000003/blk000009bb/sig00001a44 ), + .A1(\blk00000003/blk000009bb/sig00001a45 ), + .A2(\blk00000003/blk000009bb/sig00001a44 ), + .A3(\blk00000003/blk000009bb/sig00001a44 ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(\blk00000003/sig00000a59 ), + .Q(\blk00000003/blk000009bb/sig00001a4b ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000009bb/blk000009c7 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/blk000009bb/sig00001a4a ), + .Q(\blk00000003/sig00000aae ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000009bb/blk000009c6 ( + .A0(\blk00000003/blk000009bb/sig00001a44 ), + .A1(\blk00000003/blk000009bb/sig00001a45 ), + .A2(\blk00000003/blk000009bb/sig00001a44 ), + .A3(\blk00000003/blk000009bb/sig00001a44 ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(\blk00000003/sig00000a5a ), + .Q(\blk00000003/blk000009bb/sig00001a4a ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000009bb/blk000009c5 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/blk000009bb/sig00001a49 ), + .Q(\blk00000003/sig00000aac ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000009bb/blk000009c4 ( + .A0(\blk00000003/blk000009bb/sig00001a44 ), + .A1(\blk00000003/blk000009bb/sig00001a45 ), + .A2(\blk00000003/blk000009bb/sig00001a44 ), + .A3(\blk00000003/blk000009bb/sig00001a44 ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(\blk00000003/sig00000a58 ), + .Q(\blk00000003/blk000009bb/sig00001a49 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000009bb/blk000009c3 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/blk000009bb/sig00001a48 ), + .Q(\blk00000003/sig00000ab0 ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000009bb/blk000009c2 ( + .A0(\blk00000003/blk000009bb/sig00001a44 ), + .A1(\blk00000003/blk000009bb/sig00001a45 ), + .A2(\blk00000003/blk000009bb/sig00001a44 ), + .A3(\blk00000003/blk000009bb/sig00001a44 ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(\blk00000003/sig00000a5c ), + .Q(\blk00000003/blk000009bb/sig00001a48 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000009bb/blk000009c1 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/blk000009bb/sig00001a47 ), + .Q(\blk00000003/sig00000ab1 ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000009bb/blk000009c0 ( + .A0(\blk00000003/blk000009bb/sig00001a44 ), + .A1(\blk00000003/blk000009bb/sig00001a45 ), + .A2(\blk00000003/blk000009bb/sig00001a44 ), + .A3(\blk00000003/blk000009bb/sig00001a44 ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(\blk00000003/sig00000a5d ), + .Q(\blk00000003/blk000009bb/sig00001a47 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000009bb/blk000009bf ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/blk000009bb/sig00001a46 ), + .Q(\blk00000003/sig00000aaf ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000009bb/blk000009be ( + .A0(\blk00000003/blk000009bb/sig00001a44 ), + .A1(\blk00000003/blk000009bb/sig00001a45 ), + .A2(\blk00000003/blk000009bb/sig00001a44 ), + .A3(\blk00000003/blk000009bb/sig00001a44 ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(\blk00000003/sig00000a5b ), + .Q(\blk00000003/blk000009bb/sig00001a46 ) + ); + VCC \blk00000003/blk000009bb/blk000009bd ( + .P(\blk00000003/blk000009bb/sig00001a45 ) + ); + GND \blk00000003/blk000009bb/blk000009bc ( + .G(\blk00000003/blk000009bb/sig00001a44 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000009e8/blk00000a14 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/blk000009e8/sig00001a9d ), + .Q(\blk00000003/sig00000ab2 ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000009e8/blk00000a13 ( + .A0(\blk00000003/blk000009e8/sig00001a87 ), + .A1(\blk00000003/blk000009e8/sig00001a88 ), + .A2(\blk00000003/blk000009e8/sig00001a87 ), + .A3(\blk00000003/blk000009e8/sig00001a87 ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(\blk00000003/sig00000988 ), + .Q(\blk00000003/blk000009e8/sig00001a9d ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000009e8/blk00000a12 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/blk000009e8/sig00001a9c ), + .Q(\blk00000003/sig00000ab3 ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000009e8/blk00000a11 ( + .A0(\blk00000003/blk000009e8/sig00001a87 ), + .A1(\blk00000003/blk000009e8/sig00001a88 ), + .A2(\blk00000003/blk000009e8/sig00001a87 ), + .A3(\blk00000003/blk000009e8/sig00001a87 ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(\blk00000003/sig00000986 ), + .Q(\blk00000003/blk000009e8/sig00001a9c ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000009e8/blk00000a10 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/blk000009e8/sig00001a9b ), + .Q(\blk00000003/sig00000ab5 ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000009e8/blk00000a0f ( + .A0(\blk00000003/blk000009e8/sig00001a87 ), + .A1(\blk00000003/blk000009e8/sig00001a88 ), + .A2(\blk00000003/blk000009e8/sig00001a87 ), + .A3(\blk00000003/blk000009e8/sig00001a87 ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(\blk00000003/sig00000982 ), + .Q(\blk00000003/blk000009e8/sig00001a9b ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000009e8/blk00000a0e ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/blk000009e8/sig00001a9a ), + .Q(\blk00000003/sig00000ab6 ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000009e8/blk00000a0d ( + .A0(\blk00000003/blk000009e8/sig00001a87 ), + .A1(\blk00000003/blk000009e8/sig00001a88 ), + .A2(\blk00000003/blk000009e8/sig00001a87 ), + .A3(\blk00000003/blk000009e8/sig00001a87 ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(\blk00000003/sig00000980 ), + .Q(\blk00000003/blk000009e8/sig00001a9a ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000009e8/blk00000a0c ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/blk000009e8/sig00001a99 ), + .Q(\blk00000003/sig00000ab4 ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000009e8/blk00000a0b ( + .A0(\blk00000003/blk000009e8/sig00001a87 ), + .A1(\blk00000003/blk000009e8/sig00001a88 ), + .A2(\blk00000003/blk000009e8/sig00001a87 ), + .A3(\blk00000003/blk000009e8/sig00001a87 ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(\blk00000003/sig00000984 ), + .Q(\blk00000003/blk000009e8/sig00001a99 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000009e8/blk00000a0a ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/blk000009e8/sig00001a98 ), + .Q(\blk00000003/sig00000ab7 ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000009e8/blk00000a09 ( + .A0(\blk00000003/blk000009e8/sig00001a87 ), + .A1(\blk00000003/blk000009e8/sig00001a88 ), + .A2(\blk00000003/blk000009e8/sig00001a87 ), + .A3(\blk00000003/blk000009e8/sig00001a87 ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(\blk00000003/sig0000097e ), + .Q(\blk00000003/blk000009e8/sig00001a98 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000009e8/blk00000a08 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/blk000009e8/sig00001a97 ), + .Q(\blk00000003/sig00000ab8 ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000009e8/blk00000a07 ( + .A0(\blk00000003/blk000009e8/sig00001a87 ), + .A1(\blk00000003/blk000009e8/sig00001a88 ), + .A2(\blk00000003/blk000009e8/sig00001a87 ), + .A3(\blk00000003/blk000009e8/sig00001a87 ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(\blk00000003/sig0000097c ), + .Q(\blk00000003/blk000009e8/sig00001a97 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000009e8/blk00000a06 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/blk000009e8/sig00001a96 ), + .Q(\blk00000003/sig00000aba ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000009e8/blk00000a05 ( + .A0(\blk00000003/blk000009e8/sig00001a87 ), + .A1(\blk00000003/blk000009e8/sig00001a88 ), + .A2(\blk00000003/blk000009e8/sig00001a87 ), + .A3(\blk00000003/blk000009e8/sig00001a87 ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(\blk00000003/sig00000978 ), + .Q(\blk00000003/blk000009e8/sig00001a96 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000009e8/blk00000a04 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/blk000009e8/sig00001a95 ), + .Q(\blk00000003/sig00000abb ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000009e8/blk00000a03 ( + .A0(\blk00000003/blk000009e8/sig00001a87 ), + .A1(\blk00000003/blk000009e8/sig00001a88 ), + .A2(\blk00000003/blk000009e8/sig00001a87 ), + .A3(\blk00000003/blk000009e8/sig00001a87 ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(\blk00000003/sig00000976 ), + .Q(\blk00000003/blk000009e8/sig00001a95 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000009e8/blk00000a02 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/blk000009e8/sig00001a94 ), + .Q(\blk00000003/sig00000ab9 ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000009e8/blk00000a01 ( + .A0(\blk00000003/blk000009e8/sig00001a87 ), + .A1(\blk00000003/blk000009e8/sig00001a88 ), + .A2(\blk00000003/blk000009e8/sig00001a87 ), + .A3(\blk00000003/blk000009e8/sig00001a87 ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(\blk00000003/sig0000097a ), + .Q(\blk00000003/blk000009e8/sig00001a94 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000009e8/blk00000a00 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/blk000009e8/sig00001a93 ), + .Q(\blk00000003/sig00000abc ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000009e8/blk000009ff ( + .A0(\blk00000003/blk000009e8/sig00001a87 ), + .A1(\blk00000003/blk000009e8/sig00001a88 ), + .A2(\blk00000003/blk000009e8/sig00001a87 ), + .A3(\blk00000003/blk000009e8/sig00001a87 ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(\blk00000003/sig00000974 ), + .Q(\blk00000003/blk000009e8/sig00001a93 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000009e8/blk000009fe ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/blk000009e8/sig00001a92 ), + .Q(\blk00000003/sig00000abd ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000009e8/blk000009fd ( + .A0(\blk00000003/blk000009e8/sig00001a87 ), + .A1(\blk00000003/blk000009e8/sig00001a88 ), + .A2(\blk00000003/blk000009e8/sig00001a87 ), + .A3(\blk00000003/blk000009e8/sig00001a87 ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(\blk00000003/sig00000972 ), + .Q(\blk00000003/blk000009e8/sig00001a92 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000009e8/blk000009fc ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/blk000009e8/sig00001a91 ), + .Q(\blk00000003/sig00000abf ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000009e8/blk000009fb ( + .A0(\blk00000003/blk000009e8/sig00001a87 ), + .A1(\blk00000003/blk000009e8/sig00001a88 ), + .A2(\blk00000003/blk000009e8/sig00001a87 ), + .A3(\blk00000003/blk000009e8/sig00001a87 ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(\blk00000003/sig0000096e ), + .Q(\blk00000003/blk000009e8/sig00001a91 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000009e8/blk000009fa ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/blk000009e8/sig00001a90 ), + .Q(\blk00000003/sig00000ac0 ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000009e8/blk000009f9 ( + .A0(\blk00000003/blk000009e8/sig00001a87 ), + .A1(\blk00000003/blk000009e8/sig00001a88 ), + .A2(\blk00000003/blk000009e8/sig00001a87 ), + .A3(\blk00000003/blk000009e8/sig00001a87 ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(\blk00000003/sig0000096c ), + .Q(\blk00000003/blk000009e8/sig00001a90 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000009e8/blk000009f8 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/blk000009e8/sig00001a8f ), + .Q(\blk00000003/sig00000abe ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000009e8/blk000009f7 ( + .A0(\blk00000003/blk000009e8/sig00001a87 ), + .A1(\blk00000003/blk000009e8/sig00001a88 ), + .A2(\blk00000003/blk000009e8/sig00001a87 ), + .A3(\blk00000003/blk000009e8/sig00001a87 ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(\blk00000003/sig00000970 ), + .Q(\blk00000003/blk000009e8/sig00001a8f ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000009e8/blk000009f6 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/blk000009e8/sig00001a8e ), + .Q(\blk00000003/sig00000ac2 ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000009e8/blk000009f5 ( + .A0(\blk00000003/blk000009e8/sig00001a87 ), + .A1(\blk00000003/blk000009e8/sig00001a88 ), + .A2(\blk00000003/blk000009e8/sig00001a87 ), + .A3(\blk00000003/blk000009e8/sig00001a87 ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(\blk00000003/sig00000968 ), + .Q(\blk00000003/blk000009e8/sig00001a8e ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000009e8/blk000009f4 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/blk000009e8/sig00001a8d ), + .Q(\blk00000003/sig00000ac3 ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000009e8/blk000009f3 ( + .A0(\blk00000003/blk000009e8/sig00001a87 ), + .A1(\blk00000003/blk000009e8/sig00001a88 ), + .A2(\blk00000003/blk000009e8/sig00001a87 ), + .A3(\blk00000003/blk000009e8/sig00001a87 ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(\blk00000003/sig00000966 ), + .Q(\blk00000003/blk000009e8/sig00001a8d ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000009e8/blk000009f2 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/blk000009e8/sig00001a8c ), + .Q(\blk00000003/sig00000ac1 ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000009e8/blk000009f1 ( + .A0(\blk00000003/blk000009e8/sig00001a87 ), + .A1(\blk00000003/blk000009e8/sig00001a88 ), + .A2(\blk00000003/blk000009e8/sig00001a87 ), + .A3(\blk00000003/blk000009e8/sig00001a87 ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(\blk00000003/sig0000096a ), + .Q(\blk00000003/blk000009e8/sig00001a8c ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000009e8/blk000009f0 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/blk000009e8/sig00001a8b ), + .Q(\blk00000003/sig00000ac5 ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000009e8/blk000009ef ( + .A0(\blk00000003/blk000009e8/sig00001a87 ), + .A1(\blk00000003/blk000009e8/sig00001a88 ), + .A2(\blk00000003/blk000009e8/sig00001a87 ), + .A3(\blk00000003/blk000009e8/sig00001a87 ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(\blk00000003/sig00000962 ), + .Q(\blk00000003/blk000009e8/sig00001a8b ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000009e8/blk000009ee ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/blk000009e8/sig00001a8a ), + .Q(\blk00000003/sig00000ac6 ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000009e8/blk000009ed ( + .A0(\blk00000003/blk000009e8/sig00001a87 ), + .A1(\blk00000003/blk000009e8/sig00001a88 ), + .A2(\blk00000003/blk000009e8/sig00001a87 ), + .A3(\blk00000003/blk000009e8/sig00001a87 ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(\blk00000003/sig00000960 ), + .Q(\blk00000003/blk000009e8/sig00001a8a ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk000009e8/blk000009ec ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/blk000009e8/sig00001a89 ), + .Q(\blk00000003/sig00000ac4 ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk000009e8/blk000009eb ( + .A0(\blk00000003/blk000009e8/sig00001a87 ), + .A1(\blk00000003/blk000009e8/sig00001a88 ), + .A2(\blk00000003/blk000009e8/sig00001a87 ), + .A3(\blk00000003/blk000009e8/sig00001a87 ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(\blk00000003/sig00000964 ), + .Q(\blk00000003/blk000009e8/sig00001a89 ) + ); + VCC \blk00000003/blk000009e8/blk000009ea ( + .P(\blk00000003/blk000009e8/sig00001a88 ) + ); + GND \blk00000003/blk000009e8/blk000009e9 ( + .G(\blk00000003/blk000009e8/sig00001a87 ) + ); + FD #( + .INIT ( 1'b0 )) + \blk00000003/blk00000a91/blk00000a9b ( + .C(clk), + .D(\blk00000003/blk00000a91/sig00001aac ), + .Q(\blk00000003/sig00000b58 ) + ); + SRL16 #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000a91/blk00000a9a ( + .A0(\blk00000003/blk00000a91/sig00001aa7 ), + .A1(\blk00000003/blk00000a91/sig00001aa8 ), + .A2(\blk00000003/blk00000a91/sig00001aa8 ), + .A3(\blk00000003/blk00000a91/sig00001aa8 ), + .CLK(clk), + .D(\blk00000003/sig000006f0 ), + .Q(\blk00000003/blk00000a91/sig00001aac ) + ); + FD #( + .INIT ( 1'b0 )) + \blk00000003/blk00000a91/blk00000a99 ( + .C(clk), + .D(\blk00000003/blk00000a91/sig00001aab ), + .Q(\blk00000003/sig00000b59 ) + ); + SRL16 #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000a91/blk00000a98 ( + .A0(\blk00000003/blk00000a91/sig00001aa7 ), + .A1(\blk00000003/blk00000a91/sig00001aa8 ), + .A2(\blk00000003/blk00000a91/sig00001aa8 ), + .A3(\blk00000003/blk00000a91/sig00001aa8 ), + .CLK(clk), + .D(\blk00000003/sig000006f2 ), + .Q(\blk00000003/blk00000a91/sig00001aab ) + ); + FD #( + .INIT ( 1'b0 )) + \blk00000003/blk00000a91/blk00000a97 ( + .C(clk), + .D(\blk00000003/blk00000a91/sig00001aaa ), + .Q(\blk00000003/sig00000b5a ) + ); + SRL16 #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000a91/blk00000a96 ( + .A0(\blk00000003/blk00000a91/sig00001aa7 ), + .A1(\blk00000003/blk00000a91/sig00001aa8 ), + .A2(\blk00000003/blk00000a91/sig00001aa8 ), + .A3(\blk00000003/blk00000a91/sig00001aa8 ), + .CLK(clk), + .D(\blk00000003/sig000006f4 ), + .Q(\blk00000003/blk00000a91/sig00001aaa ) + ); + FD #( + .INIT ( 1'b0 )) + \blk00000003/blk00000a91/blk00000a95 ( + .C(clk), + .D(\blk00000003/blk00000a91/sig00001aa9 ), + .Q(\blk00000003/sig00000b5b ) + ); + SRL16 #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000a91/blk00000a94 ( + .A0(\blk00000003/blk00000a91/sig00001aa7 ), + .A1(\blk00000003/blk00000a91/sig00001aa8 ), + .A2(\blk00000003/blk00000a91/sig00001aa8 ), + .A3(\blk00000003/blk00000a91/sig00001aa8 ), + .CLK(clk), + .D(\blk00000003/sig000006f6 ), + .Q(\blk00000003/blk00000a91/sig00001aa9 ) + ); + VCC \blk00000003/blk00000a91/blk00000a93 ( + .P(\blk00000003/blk00000a91/sig00001aa8 ) + ); + GND \blk00000003/blk00000a91/blk00000a92 ( + .G(\blk00000003/blk00000a91/sig00001aa7 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000a9c/blk00000a9f ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/blk00000a9c/sig00001ab2 ), + .Q(\blk00000003/sig00000b5d ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000a9c/blk00000a9e ( + .A0(\blk00000003/blk00000a9c/sig00001ab1 ), + .A1(\blk00000003/blk00000a9c/sig00001ab1 ), + .A2(\blk00000003/blk00000a9c/sig00001ab1 ), + .A3(\blk00000003/blk00000a9c/sig00001ab1 ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(\blk00000003/sig00000b5c ), + .Q(\blk00000003/blk00000a9c/sig00001ab2 ) + ); + GND \blk00000003/blk00000a9c/blk00000a9d ( + .G(\blk00000003/blk00000a9c/sig00001ab1 ) + ); + FD #( + .INIT ( 1'b0 )) + \blk00000003/blk00000abf/blk00000ae1 ( + .C(clk), + .D(\blk00000003/blk00000abf/sig00001ad9 ), + .Q(\blk00000003/sig00000b82 ) + ); + SRL16 #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000abf/blk00000ae0 ( + .A0(\blk00000003/blk00000abf/sig00001ad7 ), + .A1(\blk00000003/blk00000abf/sig00001ad7 ), + .A2(\blk00000003/blk00000abf/sig00001ad7 ), + .A3(\blk00000003/blk00000abf/sig00001ad7 ), + .CLK(clk), + .D(\blk00000003/sig00000b7c ), + .Q(\blk00000003/blk00000abf/sig00001ad9 ) + ); + FD #( + .INIT ( 1'b0 )) + \blk00000003/blk00000abf/blk00000adf ( + .C(clk), + .D(\blk00000003/blk00000abf/sig00001ad8 ), + .Q(\blk00000003/sig00000b9c ) + ); + SRL16 #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000abf/blk00000ade ( + .A0(\blk00000003/blk00000abf/sig00001ad7 ), + .A1(\blk00000003/blk00000abf/sig00001ad7 ), + .A2(\blk00000003/blk00000abf/sig00001ad7 ), + .A3(\blk00000003/blk00000abf/sig00001ad7 ), + .CLK(clk), + .D(\blk00000003/sig00000b7f ), + .Q(\blk00000003/blk00000abf/sig00001ad8 ) + ); + GND \blk00000003/blk00000abf/blk00000add ( + .G(\blk00000003/blk00000abf/sig00001ad7 ) + ); + LUT3 #( + .INIT ( 8'hD8 )) + \blk00000003/blk00000abf/blk00000adc ( + .I0(\blk00000003/blk00000abf/sig00001ac3 ), + .I1(\blk00000003/blk00000abf/sig00001ac7 ), + .I2(\blk00000003/blk00000abf/sig00001aca ), + .O(\blk00000003/blk00000abf/sig00001ad2 ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \blk00000003/blk00000abf/blk00000adb ( + .I0(\blk00000003/blk00000abf/sig00001ac3 ), + .I1(\blk00000003/blk00000abf/sig00001ad0 ), + .O(\blk00000003/blk00000abf/sig00001ad6 ) + ); + LUT3 #( + .INIT ( 8'hD8 )) + \blk00000003/blk00000abf/blk00000ada ( + .I0(\blk00000003/blk00000abf/sig00001ac3 ), + .I1(\blk00000003/blk00000abf/sig00001aca ), + .I2(\blk00000003/blk00000abf/sig00001ac7 ), + .O(\blk00000003/blk00000abf/sig00001ad4 ) + ); + LUT3 #( + .INIT ( 8'hD8 )) + \blk00000003/blk00000abf/blk00000ad9 ( + .I0(\blk00000003/blk00000abf/sig00001ac3 ), + .I1(\blk00000003/blk00000abf/sig00001ac5 ), + .I2(\blk00000003/blk00000abf/sig00001ac8 ), + .O(\blk00000003/blk00000abf/sig00001ad1 ) + ); + LUT3 #( + .INIT ( 8'hD8 )) + \blk00000003/blk00000abf/blk00000ad8 ( + .I0(\blk00000003/blk00000abf/sig00001ac3 ), + .I1(\blk00000003/blk00000abf/sig00001ac8 ), + .I2(\blk00000003/blk00000abf/sig00001ac5 ), + .O(\blk00000003/blk00000abf/sig00001ad3 ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk00000abf/blk00000ad7 ( + .I0(\blk00000003/blk00000abf/sig00001ac3 ), + .I1(\blk00000003/blk00000abf/sig00001ad0 ), + .O(\blk00000003/blk00000abf/sig00001ad5 ) + ); + LUT2 #( + .INIT ( 4'h1 )) + \blk00000003/blk00000abf/blk00000ad6 ( + .I0(\blk00000003/sig00000b7c ), + .I1(\blk00000003/sig00000b7d ), + .O(\blk00000003/blk00000abf/sig00001acf ) + ); + LUT2 #( + .INIT ( 4'hE )) + \blk00000003/blk00000abf/blk00000ad5 ( + .I0(\blk00000003/sig00000b7d ), + .I1(\blk00000003/sig00000b7c ), + .O(\blk00000003/blk00000abf/sig00001acd ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \blk00000003/blk00000abf/blk00000ad4 ( + .I0(\blk00000003/sig00000b7c ), + .I1(\blk00000003/sig00000b7d ), + .O(\blk00000003/blk00000abf/sig00001acb ) + ); + LUT2 #( + .INIT ( 4'h8 )) + \blk00000003/blk00000abf/blk00000ad3 ( + .I0(\blk00000003/sig00000b7c ), + .I1(\blk00000003/sig00000b7d ), + .O(\blk00000003/blk00000abf/sig00001ac6 ) + ); + LUT2 #( + .INIT ( 4'h6 )) + \blk00000003/blk00000abf/blk00000ad2 ( + .I0(\blk00000003/sig00000b7c ), + .I1(\blk00000003/sig00000b7d ), + .O(\blk00000003/blk00000abf/sig00001ac4 ) + ); + LUT2 #( + .INIT ( 4'h4 )) + \blk00000003/blk00000abf/blk00000ad1 ( + .I0(\blk00000003/sig00000b7d ), + .I1(\blk00000003/sig00000b7c ), + .O(\blk00000003/blk00000abf/sig00001ac9 ) + ); + FD #( + .INIT ( 1'b0 )) + \blk00000003/blk00000abf/blk00000ad0 ( + .C(clk), + .D(\blk00000003/blk00000abf/sig00001ad6 ), + .Q(\blk00000003/sig00000b8e ) + ); + FD #( + .INIT ( 1'b0 )) + \blk00000003/blk00000abf/blk00000acf ( + .C(clk), + .D(\blk00000003/blk00000abf/sig00001ad5 ), + .Q(\blk00000003/sig00000b80 ) + ); + FD #( + .INIT ( 1'b0 )) + \blk00000003/blk00000abf/blk00000ace ( + .C(clk), + .D(\blk00000003/blk00000abf/sig00001ace ), + .Q(\blk00000003/sig00000b83 ) + ); + FD #( + .INIT ( 1'b0 )) + \blk00000003/blk00000abf/blk00000acd ( + .C(clk), + .D(\blk00000003/blk00000abf/sig00001acc ), + .Q(\blk00000003/sig00000b84 ) + ); + FD #( + .INIT ( 1'b0 )) + \blk00000003/blk00000abf/blk00000acc ( + .C(clk), + .D(\blk00000003/blk00000abf/sig00001ad4 ), + .Q(\blk00000003/sig00000b85 ) + ); + FD #( + .INIT ( 1'b0 )) + \blk00000003/blk00000abf/blk00000acb ( + .C(clk), + .D(\blk00000003/blk00000abf/sig00001ad3 ), + .Q(\blk00000003/sig00000b87 ) + ); + FD #( + .INIT ( 1'b0 )) + \blk00000003/blk00000abf/blk00000aca ( + .C(clk), + .D(\blk00000003/blk00000abf/sig00001ad2 ), + .Q(\blk00000003/sig00000b89 ) + ); + FD #( + .INIT ( 1'b0 )) + \blk00000003/blk00000abf/blk00000ac9 ( + .C(clk), + .D(\blk00000003/blk00000abf/sig00001ad1 ), + .Q(\blk00000003/sig00000b81 ) + ); + FD #( + .INIT ( 1'b0 )) + \blk00000003/blk00000abf/blk00000ac8 ( + .C(clk), + .D(\blk00000003/blk00000abf/sig00001ac3 ), + .Q(\blk00000003/sig00000b9d ) + ); + FD #( + .INIT ( 1'b0 )) + \blk00000003/blk00000abf/blk00000ac7 ( + .C(clk), + .D(\blk00000003/blk00000abf/sig00001acf ), + .Q(\blk00000003/blk00000abf/sig00001ad0 ) + ); + FD #( + .INIT ( 1'b0 )) + \blk00000003/blk00000abf/blk00000ac6 ( + .C(clk), + .D(\blk00000003/blk00000abf/sig00001acd ), + .Q(\blk00000003/blk00000abf/sig00001ace ) + ); + FD #( + .INIT ( 1'b0 )) + \blk00000003/blk00000abf/blk00000ac5 ( + .C(clk), + .D(\blk00000003/blk00000abf/sig00001acb ), + .Q(\blk00000003/blk00000abf/sig00001acc ) + ); + FD #( + .INIT ( 1'b0 )) + \blk00000003/blk00000abf/blk00000ac4 ( + .C(clk), + .D(\blk00000003/blk00000abf/sig00001ac9 ), + .Q(\blk00000003/blk00000abf/sig00001aca ) + ); + FD #( + .INIT ( 1'b0 )) + \blk00000003/blk00000abf/blk00000ac3 ( + .C(clk), + .D(\blk00000003/sig00000b7d ), + .Q(\blk00000003/blk00000abf/sig00001ac8 ) + ); + FD #( + .INIT ( 1'b0 )) + \blk00000003/blk00000abf/blk00000ac2 ( + .C(clk), + .D(\blk00000003/blk00000abf/sig00001ac6 ), + .Q(\blk00000003/blk00000abf/sig00001ac7 ) + ); + FD #( + .INIT ( 1'b0 )) + \blk00000003/blk00000abf/blk00000ac1 ( + .C(clk), + .D(\blk00000003/blk00000abf/sig00001ac4 ), + .Q(\blk00000003/blk00000abf/sig00001ac5 ) + ); + FD #( + .INIT ( 1'b0 )) + \blk00000003/blk00000abf/blk00000ac0 ( + .C(clk), + .D(\blk00000003/sig00000b7e ), + .Q(\blk00000003/blk00000abf/sig00001ac3 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000c04/blk00000c0f ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/blk00000c04/sig00001b57 ), + .Q(\blk00000003/sig00000e94 ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000c04/blk00000c0e ( + .A0(\blk00000003/blk00000c04/sig00001b52 ), + .A1(\blk00000003/blk00000c04/sig00001b52 ), + .A2(\blk00000003/blk00000c04/sig00001b52 ), + .A3(\blk00000003/blk00000c04/sig00001b52 ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(\blk00000003/sig00000f96 ), + .Q(\blk00000003/blk00000c04/sig00001b57 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000c04/blk00000c0d ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/blk00000c04/sig00001b56 ), + .Q(\blk00000003/sig00000e95 ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000c04/blk00000c0c ( + .A0(\blk00000003/blk00000c04/sig00001b52 ), + .A1(\blk00000003/blk00000c04/sig00001b52 ), + .A2(\blk00000003/blk00000c04/sig00001b52 ), + .A3(\blk00000003/blk00000c04/sig00001b52 ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(\blk00000003/sig00000f97 ), + .Q(\blk00000003/blk00000c04/sig00001b56 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000c04/blk00000c0b ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/blk00000c04/sig00001b55 ), + .Q(\blk00000003/sig00000e97 ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000c04/blk00000c0a ( + .A0(\blk00000003/blk00000c04/sig00001b52 ), + .A1(\blk00000003/blk00000c04/sig00001b52 ), + .A2(\blk00000003/blk00000c04/sig00001b52 ), + .A3(\blk00000003/blk00000c04/sig00001b52 ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(\blk00000003/sig00000f99 ), + .Q(\blk00000003/blk00000c04/sig00001b55 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000c04/blk00000c09 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/blk00000c04/sig00001b54 ), + .Q(\blk00000003/sig00000e98 ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000c04/blk00000c08 ( + .A0(\blk00000003/blk00000c04/sig00001b52 ), + .A1(\blk00000003/blk00000c04/sig00001b52 ), + .A2(\blk00000003/blk00000c04/sig00001b52 ), + .A3(\blk00000003/blk00000c04/sig00001b52 ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(\blk00000003/sig00000f9a ), + .Q(\blk00000003/blk00000c04/sig00001b54 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000c04/blk00000c07 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/blk00000c04/sig00001b53 ), + .Q(\blk00000003/sig00000e96 ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000c04/blk00000c06 ( + .A0(\blk00000003/blk00000c04/sig00001b52 ), + .A1(\blk00000003/blk00000c04/sig00001b52 ), + .A2(\blk00000003/blk00000c04/sig00001b52 ), + .A3(\blk00000003/blk00000c04/sig00001b52 ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(\blk00000003/sig00000f98 ), + .Q(\blk00000003/blk00000c04/sig00001b53 ) + ); + GND \blk00000003/blk00000c04/blk00000c05 ( + .G(\blk00000003/blk00000c04/sig00001b52 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000c10/blk00000c1b ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/blk00000c10/sig00001b69 ), + .Q(\blk00000003/sig00000c5b ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000c10/blk00000c1a ( + .A0(\blk00000003/blk00000c10/sig00001b64 ), + .A1(\blk00000003/blk00000c10/sig00001b64 ), + .A2(\blk00000003/blk00000c10/sig00001b64 ), + .A3(\blk00000003/blk00000c10/sig00001b64 ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(\blk00000003/sig00000f9b ), + .Q(\blk00000003/blk00000c10/sig00001b69 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000c10/blk00000c19 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/blk00000c10/sig00001b68 ), + .Q(\blk00000003/sig00000c5c ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000c10/blk00000c18 ( + .A0(\blk00000003/blk00000c10/sig00001b64 ), + .A1(\blk00000003/blk00000c10/sig00001b64 ), + .A2(\blk00000003/blk00000c10/sig00001b64 ), + .A3(\blk00000003/blk00000c10/sig00001b64 ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(\blk00000003/sig00000f9c ), + .Q(\blk00000003/blk00000c10/sig00001b68 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000c10/blk00000c17 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/blk00000c10/sig00001b67 ), + .Q(\blk00000003/sig00000c5e ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000c10/blk00000c16 ( + .A0(\blk00000003/blk00000c10/sig00001b64 ), + .A1(\blk00000003/blk00000c10/sig00001b64 ), + .A2(\blk00000003/blk00000c10/sig00001b64 ), + .A3(\blk00000003/blk00000c10/sig00001b64 ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(\blk00000003/sig00000f9e ), + .Q(\blk00000003/blk00000c10/sig00001b67 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000c10/blk00000c15 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/blk00000c10/sig00001b66 ), + .Q(\blk00000003/sig00000c5f ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000c10/blk00000c14 ( + .A0(\blk00000003/blk00000c10/sig00001b64 ), + .A1(\blk00000003/blk00000c10/sig00001b64 ), + .A2(\blk00000003/blk00000c10/sig00001b64 ), + .A3(\blk00000003/blk00000c10/sig00001b64 ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(\blk00000003/sig00000f9f ), + .Q(\blk00000003/blk00000c10/sig00001b66 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000c10/blk00000c13 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/blk00000c10/sig00001b65 ), + .Q(\blk00000003/sig00000c5d ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000c10/blk00000c12 ( + .A0(\blk00000003/blk00000c10/sig00001b64 ), + .A1(\blk00000003/blk00000c10/sig00001b64 ), + .A2(\blk00000003/blk00000c10/sig00001b64 ), + .A3(\blk00000003/blk00000c10/sig00001b64 ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(\blk00000003/sig00000f9d ), + .Q(\blk00000003/blk00000c10/sig00001b65 ) + ); + GND \blk00000003/blk00000c10/blk00000c11 ( + .G(\blk00000003/blk00000c10/sig00001b64 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000c1d/blk00000c22 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/blk00000c1d/sig00001b73 ), + .Q(\blk00000003/sig00000fa0 ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000c1d/blk00000c21 ( + .A0(\blk00000003/blk00000c1d/sig00001b71 ), + .A1(\blk00000003/blk00000c1d/sig00001b71 ), + .A2(\blk00000003/blk00000c1d/sig00001b71 ), + .A3(\blk00000003/blk00000c1d/sig00001b71 ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(\blk00000003/sig00000f43 ), + .Q(\blk00000003/blk00000c1d/sig00001b73 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000c1d/blk00000c20 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/blk00000c1d/sig00001b72 ), + .Q(\blk00000003/sig00000fa1 ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000c1d/blk00000c1f ( + .A0(\blk00000003/blk00000c1d/sig00001b71 ), + .A1(\blk00000003/blk00000c1d/sig00001b71 ), + .A2(\blk00000003/blk00000c1d/sig00001b71 ), + .A3(\blk00000003/blk00000c1d/sig00001b71 ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(\blk00000003/sig00000f44 ), + .Q(\blk00000003/blk00000c1d/sig00001b72 ) + ); + GND \blk00000003/blk00000c1d/blk00000c1e ( + .G(\blk00000003/blk00000c1d/sig00001b71 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000c23/blk00000c28 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/blk00000c23/sig00001b7c ), + .Q(\blk00000003/sig00000fa2 ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000c23/blk00000c27 ( + .A0(\blk00000003/blk00000c23/sig00001b7a ), + .A1(\blk00000003/blk00000c23/sig00001b7a ), + .A2(\blk00000003/blk00000c23/sig00001b7a ), + .A3(\blk00000003/blk00000c23/sig00001b7a ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(\blk00000003/sig00000c08 ), + .Q(\blk00000003/blk00000c23/sig00001b7c ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000c23/blk00000c26 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/blk00000c23/sig00001b7b ), + .Q(\blk00000003/sig00000fa3 ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000c23/blk00000c25 ( + .A0(\blk00000003/blk00000c23/sig00001b7a ), + .A1(\blk00000003/blk00000c23/sig00001b7a ), + .A2(\blk00000003/blk00000c23/sig00001b7a ), + .A3(\blk00000003/blk00000c23/sig00001b7a ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(\blk00000003/sig00000c09 ), + .Q(\blk00000003/blk00000c23/sig00001b7b ) + ); + GND \blk00000003/blk00000c23/blk00000c24 ( + .G(\blk00000003/blk00000c23/sig00001b7a ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000c29/blk00000c4c ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/blk00000c29/sig00001bb2 ), + .Q(\blk00000003/sig00000bd8 ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000c29/blk00000c4b ( + .A0(\blk00000003/blk00000c29/sig00001ba1 ), + .A1(\blk00000003/blk00000c29/sig00001ba1 ), + .A2(\blk00000003/blk00000c29/sig00001ba1 ), + .A3(\blk00000003/blk00000c29/sig00001ba1 ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(\blk00000003/sig00000cd7 ), + .Q(\blk00000003/blk00000c29/sig00001bb2 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000c29/blk00000c4a ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/blk00000c29/sig00001bb1 ), + .Q(\blk00000003/sig00000bd9 ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000c29/blk00000c49 ( + .A0(\blk00000003/blk00000c29/sig00001ba1 ), + .A1(\blk00000003/blk00000c29/sig00001ba1 ), + .A2(\blk00000003/blk00000c29/sig00001ba1 ), + .A3(\blk00000003/blk00000c29/sig00001ba1 ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(\blk00000003/sig00000cd8 ), + .Q(\blk00000003/blk00000c29/sig00001bb1 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000c29/blk00000c48 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/blk00000c29/sig00001bb0 ), + .Q(\blk00000003/sig00000bda ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000c29/blk00000c47 ( + .A0(\blk00000003/blk00000c29/sig00001ba1 ), + .A1(\blk00000003/blk00000c29/sig00001ba1 ), + .A2(\blk00000003/blk00000c29/sig00001ba1 ), + .A3(\blk00000003/blk00000c29/sig00001ba1 ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(\blk00000003/sig00000cd9 ), + .Q(\blk00000003/blk00000c29/sig00001bb0 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000c29/blk00000c46 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/blk00000c29/sig00001baf ), + .Q(\blk00000003/sig00000bdb ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000c29/blk00000c45 ( + .A0(\blk00000003/blk00000c29/sig00001ba1 ), + .A1(\blk00000003/blk00000c29/sig00001ba1 ), + .A2(\blk00000003/blk00000c29/sig00001ba1 ), + .A3(\blk00000003/blk00000c29/sig00001ba1 ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(\blk00000003/sig00000cda ), + .Q(\blk00000003/blk00000c29/sig00001baf ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000c29/blk00000c44 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/blk00000c29/sig00001bae ), + .Q(\blk00000003/sig00000bdc ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000c29/blk00000c43 ( + .A0(\blk00000003/blk00000c29/sig00001ba1 ), + .A1(\blk00000003/blk00000c29/sig00001ba1 ), + .A2(\blk00000003/blk00000c29/sig00001ba1 ), + .A3(\blk00000003/blk00000c29/sig00001ba1 ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(\blk00000003/sig00000cdb ), + .Q(\blk00000003/blk00000c29/sig00001bae ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000c29/blk00000c42 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/blk00000c29/sig00001bad ), + .Q(\blk00000003/sig00000bdd ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000c29/blk00000c41 ( + .A0(\blk00000003/blk00000c29/sig00001ba1 ), + .A1(\blk00000003/blk00000c29/sig00001ba1 ), + .A2(\blk00000003/blk00000c29/sig00001ba1 ), + .A3(\blk00000003/blk00000c29/sig00001ba1 ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(\blk00000003/sig00000cdc ), + .Q(\blk00000003/blk00000c29/sig00001bad ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000c29/blk00000c40 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/blk00000c29/sig00001bac ), + .Q(\blk00000003/sig00000bde ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000c29/blk00000c3f ( + .A0(\blk00000003/blk00000c29/sig00001ba1 ), + .A1(\blk00000003/blk00000c29/sig00001ba1 ), + .A2(\blk00000003/blk00000c29/sig00001ba1 ), + .A3(\blk00000003/blk00000c29/sig00001ba1 ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(\blk00000003/sig00000cdd ), + .Q(\blk00000003/blk00000c29/sig00001bac ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000c29/blk00000c3e ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/blk00000c29/sig00001bab ), + .Q(\blk00000003/sig00000bdf ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000c29/blk00000c3d ( + .A0(\blk00000003/blk00000c29/sig00001ba1 ), + .A1(\blk00000003/blk00000c29/sig00001ba1 ), + .A2(\blk00000003/blk00000c29/sig00001ba1 ), + .A3(\blk00000003/blk00000c29/sig00001ba1 ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(\blk00000003/sig00000cde ), + .Q(\blk00000003/blk00000c29/sig00001bab ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000c29/blk00000c3c ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/blk00000c29/sig00001baa ), + .Q(\blk00000003/sig00000be0 ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000c29/blk00000c3b ( + .A0(\blk00000003/blk00000c29/sig00001ba1 ), + .A1(\blk00000003/blk00000c29/sig00001ba1 ), + .A2(\blk00000003/blk00000c29/sig00001ba1 ), + .A3(\blk00000003/blk00000c29/sig00001ba1 ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(\blk00000003/sig00000cdf ), + .Q(\blk00000003/blk00000c29/sig00001baa ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000c29/blk00000c3a ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/blk00000c29/sig00001ba9 ), + .Q(\blk00000003/sig00000be1 ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000c29/blk00000c39 ( + .A0(\blk00000003/blk00000c29/sig00001ba1 ), + .A1(\blk00000003/blk00000c29/sig00001ba1 ), + .A2(\blk00000003/blk00000c29/sig00001ba1 ), + .A3(\blk00000003/blk00000c29/sig00001ba1 ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(\blk00000003/sig00000ce0 ), + .Q(\blk00000003/blk00000c29/sig00001ba9 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000c29/blk00000c38 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/blk00000c29/sig00001ba8 ), + .Q(\blk00000003/sig00000be2 ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000c29/blk00000c37 ( + .A0(\blk00000003/blk00000c29/sig00001ba1 ), + .A1(\blk00000003/blk00000c29/sig00001ba1 ), + .A2(\blk00000003/blk00000c29/sig00001ba1 ), + .A3(\blk00000003/blk00000c29/sig00001ba1 ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(\blk00000003/sig00000ce1 ), + .Q(\blk00000003/blk00000c29/sig00001ba8 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000c29/blk00000c36 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/blk00000c29/sig00001ba7 ), + .Q(\blk00000003/sig00000be3 ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000c29/blk00000c35 ( + .A0(\blk00000003/blk00000c29/sig00001ba1 ), + .A1(\blk00000003/blk00000c29/sig00001ba1 ), + .A2(\blk00000003/blk00000c29/sig00001ba1 ), + .A3(\blk00000003/blk00000c29/sig00001ba1 ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(\blk00000003/sig00000ce2 ), + .Q(\blk00000003/blk00000c29/sig00001ba7 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000c29/blk00000c34 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/blk00000c29/sig00001ba6 ), + .Q(\blk00000003/sig00000be4 ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000c29/blk00000c33 ( + .A0(\blk00000003/blk00000c29/sig00001ba1 ), + .A1(\blk00000003/blk00000c29/sig00001ba1 ), + .A2(\blk00000003/blk00000c29/sig00001ba1 ), + .A3(\blk00000003/blk00000c29/sig00001ba1 ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(\blk00000003/sig00000ce3 ), + .Q(\blk00000003/blk00000c29/sig00001ba6 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000c29/blk00000c32 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/blk00000c29/sig00001ba5 ), + .Q(\blk00000003/sig00000be5 ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000c29/blk00000c31 ( + .A0(\blk00000003/blk00000c29/sig00001ba1 ), + .A1(\blk00000003/blk00000c29/sig00001ba1 ), + .A2(\blk00000003/blk00000c29/sig00001ba1 ), + .A3(\blk00000003/blk00000c29/sig00001ba1 ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(\blk00000003/sig00000ce4 ), + .Q(\blk00000003/blk00000c29/sig00001ba5 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000c29/blk00000c30 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/blk00000c29/sig00001ba4 ), + .Q(\blk00000003/sig00000be7 ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000c29/blk00000c2f ( + .A0(\blk00000003/blk00000c29/sig00001ba1 ), + .A1(\blk00000003/blk00000c29/sig00001ba1 ), + .A2(\blk00000003/blk00000c29/sig00001ba1 ), + .A3(\blk00000003/blk00000c29/sig00001ba1 ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(\blk00000003/sig00000ce6 ), + .Q(\blk00000003/blk00000c29/sig00001ba4 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000c29/blk00000c2e ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/blk00000c29/sig00001ba3 ), + .Q(\blk00000003/sig00000be8 ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000c29/blk00000c2d ( + .A0(\blk00000003/blk00000c29/sig00001ba1 ), + .A1(\blk00000003/blk00000c29/sig00001ba1 ), + .A2(\blk00000003/blk00000c29/sig00001ba1 ), + .A3(\blk00000003/blk00000c29/sig00001ba1 ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(\blk00000003/sig00000ce7 ), + .Q(\blk00000003/blk00000c29/sig00001ba3 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000c29/blk00000c2c ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/blk00000c29/sig00001ba2 ), + .Q(\blk00000003/sig00000be6 ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000c29/blk00000c2b ( + .A0(\blk00000003/blk00000c29/sig00001ba1 ), + .A1(\blk00000003/blk00000c29/sig00001ba1 ), + .A2(\blk00000003/blk00000c29/sig00001ba1 ), + .A3(\blk00000003/blk00000c29/sig00001ba1 ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(\blk00000003/sig00000ce5 ), + .Q(\blk00000003/blk00000c29/sig00001ba2 ) + ); + GND \blk00000003/blk00000c29/blk00000c2a ( + .G(\blk00000003/blk00000c29/sig00001ba1 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000c50/blk00000c59 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/blk00000c50/sig00001c2d ), + .Q(\blk00000003/sig00000d2a ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000c50/blk00000c58 ( + .A0(\blk00000003/blk00000c50/sig00001c29 ), + .A1(\blk00000003/blk00000c50/sig00001c29 ), + .A2(\blk00000003/blk00000c50/sig00001c29 ), + .A3(\blk00000003/blk00000c50/sig00001c29 ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(\blk00000003/sig00000d56 ), + .Q(\blk00000003/blk00000c50/sig00001c2d ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000c50/blk00000c57 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/blk00000c50/sig00001c2c ), + .Q(\blk00000003/sig00000d2b ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000c50/blk00000c56 ( + .A0(\blk00000003/blk00000c50/sig00001c29 ), + .A1(\blk00000003/blk00000c50/sig00001c29 ), + .A2(\blk00000003/blk00000c50/sig00001c29 ), + .A3(\blk00000003/blk00000c50/sig00001c29 ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(\blk00000003/sig00000d5e ), + .Q(\blk00000003/blk00000c50/sig00001c2c ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000c50/blk00000c55 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/blk00000c50/sig00001c2b ), + .Q(\blk00000003/sig00000d2c ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000c50/blk00000c54 ( + .A0(\blk00000003/blk00000c50/sig00001c29 ), + .A1(\blk00000003/blk00000c50/sig00001c29 ), + .A2(\blk00000003/blk00000c50/sig00001c29 ), + .A3(\blk00000003/blk00000c50/sig00001c29 ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(\blk00000003/sig00000d63 ), + .Q(\blk00000003/blk00000c50/sig00001c2b ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000c50/blk00000c53 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/blk00000c50/sig00001c2a ), + .Q(\blk00000003/sig00000d2d ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000c50/blk00000c52 ( + .A0(\blk00000003/blk00000c50/sig00001c29 ), + .A1(\blk00000003/blk00000c50/sig00001c29 ), + .A2(\blk00000003/blk00000c50/sig00001c29 ), + .A3(\blk00000003/blk00000c50/sig00001c29 ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(\blk00000003/sig00000d68 ), + .Q(\blk00000003/blk00000c50/sig00001c2a ) + ); + GND \blk00000003/blk00000c50/blk00000c51 ( + .G(\blk00000003/blk00000c50/sig00001c29 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000c5a/blk00000c5e ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/blk00000c5a/sig00001c34 ), + .Q(\blk00000003/sig00000fcb ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000c5a/blk00000c5d ( + .A0(\blk00000003/blk00000c5a/sig00001c32 ), + .A1(\blk00000003/blk00000c5a/sig00001c33 ), + .A2(\blk00000003/blk00000c5a/sig00001c33 ), + .A3(\blk00000003/blk00000c5a/sig00001c32 ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(\blk00000003/sig00000fca ), + .Q(\blk00000003/blk00000c5a/sig00001c34 ) + ); + VCC \blk00000003/blk00000c5a/blk00000c5c ( + .P(\blk00000003/blk00000c5a/sig00001c33 ) + ); + GND \blk00000003/blk00000c5a/blk00000c5b ( + .G(\blk00000003/blk00000c5a/sig00001c32 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000c5f/blk00000c63 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/blk00000c5f/sig00001c3b ), + .Q(\blk00000003/sig00000fca ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000c5f/blk00000c62 ( + .A0(\blk00000003/blk00000c5f/sig00001c3a ), + .A1(\blk00000003/blk00000c5f/sig00001c39 ), + .A2(\blk00000003/blk00000c5f/sig00001c39 ), + .A3(\blk00000003/blk00000c5f/sig00001c39 ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(\blk00000003/sig00000718 ), + .Q(\blk00000003/blk00000c5f/sig00001c3b ) + ); + VCC \blk00000003/blk00000c5f/blk00000c61 ( + .P(\blk00000003/blk00000c5f/sig00001c3a ) + ); + GND \blk00000003/blk00000c5f/blk00000c60 ( + .G(\blk00000003/blk00000c5f/sig00001c39 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000c66/blk00000c69 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/blk00000c66/sig00001c41 ), + .Q(\blk00000003/sig00000fcf ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000c66/blk00000c68 ( + .A0(\blk00000003/blk00000c66/sig00001c40 ), + .A1(\blk00000003/blk00000c66/sig00001c40 ), + .A2(\blk00000003/blk00000c66/sig00001c40 ), + .A3(\blk00000003/blk00000c66/sig00001c40 ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(\blk00000003/sig00000fce ), + .Q(\blk00000003/blk00000c66/sig00001c41 ) + ); + GND \blk00000003/blk00000c66/blk00000c67 ( + .G(\blk00000003/blk00000c66/sig00001c40 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000cc2/blk00000ced ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/blk00000cc2/sig00001c83 ), + .Q(\blk00000003/sig0000107d ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000cc2/blk00000cec ( + .A0(\blk00000003/blk00000cc2/sig00001c6e ), + .A1(\blk00000003/blk00000cc2/sig00001c6e ), + .A2(\blk00000003/blk00000cc2/sig00001c6e ), + .A3(\blk00000003/blk00000cc2/sig00001c6e ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(\blk00000003/sig00001051 ), + .Q(\blk00000003/blk00000cc2/sig00001c83 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000cc2/blk00000ceb ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/blk00000cc2/sig00001c82 ), + .Q(\blk00000003/sig0000107e ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000cc2/blk00000cea ( + .A0(\blk00000003/blk00000cc2/sig00001c6e ), + .A1(\blk00000003/blk00000cc2/sig00001c6e ), + .A2(\blk00000003/blk00000cc2/sig00001c6e ), + .A3(\blk00000003/blk00000cc2/sig00001c6e ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(\blk00000003/sig0000104f ), + .Q(\blk00000003/blk00000cc2/sig00001c82 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000cc2/blk00000ce9 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/blk00000cc2/sig00001c81 ), + .Q(\blk00000003/sig00001080 ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000cc2/blk00000ce8 ( + .A0(\blk00000003/blk00000cc2/sig00001c6e ), + .A1(\blk00000003/blk00000cc2/sig00001c6e ), + .A2(\blk00000003/blk00000cc2/sig00001c6e ), + .A3(\blk00000003/blk00000cc2/sig00001c6e ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(\blk00000003/sig0000104b ), + .Q(\blk00000003/blk00000cc2/sig00001c81 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000cc2/blk00000ce7 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/blk00000cc2/sig00001c80 ), + .Q(\blk00000003/sig00001081 ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000cc2/blk00000ce6 ( + .A0(\blk00000003/blk00000cc2/sig00001c6e ), + .A1(\blk00000003/blk00000cc2/sig00001c6e ), + .A2(\blk00000003/blk00000cc2/sig00001c6e ), + .A3(\blk00000003/blk00000cc2/sig00001c6e ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(\blk00000003/sig00001049 ), + .Q(\blk00000003/blk00000cc2/sig00001c80 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000cc2/blk00000ce5 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/blk00000cc2/sig00001c7f ), + .Q(\blk00000003/sig0000107f ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000cc2/blk00000ce4 ( + .A0(\blk00000003/blk00000cc2/sig00001c6e ), + .A1(\blk00000003/blk00000cc2/sig00001c6e ), + .A2(\blk00000003/blk00000cc2/sig00001c6e ), + .A3(\blk00000003/blk00000cc2/sig00001c6e ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(\blk00000003/sig0000104d ), + .Q(\blk00000003/blk00000cc2/sig00001c7f ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000cc2/blk00000ce3 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/blk00000cc2/sig00001c7e ), + .Q(\blk00000003/sig00001082 ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000cc2/blk00000ce2 ( + .A0(\blk00000003/blk00000cc2/sig00001c6e ), + .A1(\blk00000003/blk00000cc2/sig00001c6e ), + .A2(\blk00000003/blk00000cc2/sig00001c6e ), + .A3(\blk00000003/blk00000cc2/sig00001c6e ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(\blk00000003/sig00001047 ), + .Q(\blk00000003/blk00000cc2/sig00001c7e ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000cc2/blk00000ce1 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/blk00000cc2/sig00001c7d ), + .Q(\blk00000003/sig00001083 ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000cc2/blk00000ce0 ( + .A0(\blk00000003/blk00000cc2/sig00001c6e ), + .A1(\blk00000003/blk00000cc2/sig00001c6e ), + .A2(\blk00000003/blk00000cc2/sig00001c6e ), + .A3(\blk00000003/blk00000cc2/sig00001c6e ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(\blk00000003/sig00001045 ), + .Q(\blk00000003/blk00000cc2/sig00001c7d ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000cc2/blk00000cdf ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/blk00000cc2/sig00001c7c ), + .Q(\blk00000003/sig00001085 ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000cc2/blk00000cde ( + .A0(\blk00000003/blk00000cc2/sig00001c6e ), + .A1(\blk00000003/blk00000cc2/sig00001c6e ), + .A2(\blk00000003/blk00000cc2/sig00001c6e ), + .A3(\blk00000003/blk00000cc2/sig00001c6e ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(\blk00000003/sig00001041 ), + .Q(\blk00000003/blk00000cc2/sig00001c7c ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000cc2/blk00000cdd ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/blk00000cc2/sig00001c7b ), + .Q(\blk00000003/sig00001086 ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000cc2/blk00000cdc ( + .A0(\blk00000003/blk00000cc2/sig00001c6e ), + .A1(\blk00000003/blk00000cc2/sig00001c6e ), + .A2(\blk00000003/blk00000cc2/sig00001c6e ), + .A3(\blk00000003/blk00000cc2/sig00001c6e ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(\blk00000003/sig0000103f ), + .Q(\blk00000003/blk00000cc2/sig00001c7b ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000cc2/blk00000cdb ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/blk00000cc2/sig00001c7a ), + .Q(\blk00000003/sig00001084 ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000cc2/blk00000cda ( + .A0(\blk00000003/blk00000cc2/sig00001c6e ), + .A1(\blk00000003/blk00000cc2/sig00001c6e ), + .A2(\blk00000003/blk00000cc2/sig00001c6e ), + .A3(\blk00000003/blk00000cc2/sig00001c6e ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(\blk00000003/sig00001043 ), + .Q(\blk00000003/blk00000cc2/sig00001c7a ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000cc2/blk00000cd9 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/blk00000cc2/sig00001c79 ), + .Q(\blk00000003/sig00001087 ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000cc2/blk00000cd8 ( + .A0(\blk00000003/blk00000cc2/sig00001c6e ), + .A1(\blk00000003/blk00000cc2/sig00001c6e ), + .A2(\blk00000003/blk00000cc2/sig00001c6e ), + .A3(\blk00000003/blk00000cc2/sig00001c6e ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(\blk00000003/sig0000103d ), + .Q(\blk00000003/blk00000cc2/sig00001c79 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000cc2/blk00000cd7 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/blk00000cc2/sig00001c78 ), + .Q(\blk00000003/sig00001088 ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000cc2/blk00000cd6 ( + .A0(\blk00000003/blk00000cc2/sig00001c6e ), + .A1(\blk00000003/blk00000cc2/sig00001c6e ), + .A2(\blk00000003/blk00000cc2/sig00001c6e ), + .A3(\blk00000003/blk00000cc2/sig00001c6e ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(\blk00000003/sig0000103b ), + .Q(\blk00000003/blk00000cc2/sig00001c78 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000cc2/blk00000cd5 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/blk00000cc2/sig00001c77 ), + .Q(\blk00000003/sig0000108a ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000cc2/blk00000cd4 ( + .A0(\blk00000003/blk00000cc2/sig00001c6e ), + .A1(\blk00000003/blk00000cc2/sig00001c6e ), + .A2(\blk00000003/blk00000cc2/sig00001c6e ), + .A3(\blk00000003/blk00000cc2/sig00001c6e ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(\blk00000003/sig00001037 ), + .Q(\blk00000003/blk00000cc2/sig00001c77 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000cc2/blk00000cd3 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/blk00000cc2/sig00001c76 ), + .Q(\blk00000003/sig0000108b ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000cc2/blk00000cd2 ( + .A0(\blk00000003/blk00000cc2/sig00001c6e ), + .A1(\blk00000003/blk00000cc2/sig00001c6e ), + .A2(\blk00000003/blk00000cc2/sig00001c6e ), + .A3(\blk00000003/blk00000cc2/sig00001c6e ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(\blk00000003/sig00001035 ), + .Q(\blk00000003/blk00000cc2/sig00001c76 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000cc2/blk00000cd1 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/blk00000cc2/sig00001c75 ), + .Q(\blk00000003/sig00001089 ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000cc2/blk00000cd0 ( + .A0(\blk00000003/blk00000cc2/sig00001c6e ), + .A1(\blk00000003/blk00000cc2/sig00001c6e ), + .A2(\blk00000003/blk00000cc2/sig00001c6e ), + .A3(\blk00000003/blk00000cc2/sig00001c6e ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(\blk00000003/sig00001039 ), + .Q(\blk00000003/blk00000cc2/sig00001c75 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000cc2/blk00000ccf ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/blk00000cc2/sig00001c74 ), + .Q(\blk00000003/sig0000108d ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000cc2/blk00000cce ( + .A0(\blk00000003/blk00000cc2/sig00001c6e ), + .A1(\blk00000003/blk00000cc2/sig00001c6e ), + .A2(\blk00000003/blk00000cc2/sig00001c6e ), + .A3(\blk00000003/blk00000cc2/sig00001c6e ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(\blk00000003/sig00001031 ), + .Q(\blk00000003/blk00000cc2/sig00001c74 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000cc2/blk00000ccd ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/blk00000cc2/sig00001c73 ), + .Q(\blk00000003/sig0000108e ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000cc2/blk00000ccc ( + .A0(\blk00000003/blk00000cc2/sig00001c6e ), + .A1(\blk00000003/blk00000cc2/sig00001c6e ), + .A2(\blk00000003/blk00000cc2/sig00001c6e ), + .A3(\blk00000003/blk00000cc2/sig00001c6e ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(\blk00000003/sig0000102f ), + .Q(\blk00000003/blk00000cc2/sig00001c73 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000cc2/blk00000ccb ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/blk00000cc2/sig00001c72 ), + .Q(\blk00000003/sig0000108c ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000cc2/blk00000cca ( + .A0(\blk00000003/blk00000cc2/sig00001c6e ), + .A1(\blk00000003/blk00000cc2/sig00001c6e ), + .A2(\blk00000003/blk00000cc2/sig00001c6e ), + .A3(\blk00000003/blk00000cc2/sig00001c6e ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(\blk00000003/sig00001033 ), + .Q(\blk00000003/blk00000cc2/sig00001c72 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000cc2/blk00000cc9 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/blk00000cc2/sig00001c71 ), + .Q(\blk00000003/sig00001090 ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000cc2/blk00000cc8 ( + .A0(\blk00000003/blk00000cc2/sig00001c6e ), + .A1(\blk00000003/blk00000cc2/sig00001c6e ), + .A2(\blk00000003/blk00000cc2/sig00001c6e ), + .A3(\blk00000003/blk00000cc2/sig00001c6e ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(\blk00000003/sig0000102b ), + .Q(\blk00000003/blk00000cc2/sig00001c71 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000cc2/blk00000cc7 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/blk00000cc2/sig00001c70 ), + .Q(\blk00000003/sig00001091 ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000cc2/blk00000cc6 ( + .A0(\blk00000003/blk00000cc2/sig00001c6e ), + .A1(\blk00000003/blk00000cc2/sig00001c6e ), + .A2(\blk00000003/blk00000cc2/sig00001c6e ), + .A3(\blk00000003/blk00000cc2/sig00001c6e ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(\blk00000003/sig00001029 ), + .Q(\blk00000003/blk00000cc2/sig00001c70 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000cc2/blk00000cc5 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/blk00000cc2/sig00001c6f ), + .Q(\blk00000003/sig0000108f ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000cc2/blk00000cc4 ( + .A0(\blk00000003/blk00000cc2/sig00001c6e ), + .A1(\blk00000003/blk00000cc2/sig00001c6e ), + .A2(\blk00000003/blk00000cc2/sig00001c6e ), + .A3(\blk00000003/blk00000cc2/sig00001c6e ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(\blk00000003/sig0000102d ), + .Q(\blk00000003/blk00000cc2/sig00001c6f ) + ); + GND \blk00000003/blk00000cc2/blk00000cc3 ( + .G(\blk00000003/blk00000cc2/sig00001c6e ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000cee/blk00000d19 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/blk00000cee/sig00001cc5 ), + .Q(\blk00000003/sig00001092 ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000cee/blk00000d18 ( + .A0(\blk00000003/blk00000cee/sig00001cb0 ), + .A1(\blk00000003/blk00000cee/sig00001cb0 ), + .A2(\blk00000003/blk00000cee/sig00001cb0 ), + .A3(\blk00000003/blk00000cee/sig00001cb0 ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(\blk00000003/sig00000c71 ), + .Q(\blk00000003/blk00000cee/sig00001cc5 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000cee/blk00000d17 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/blk00000cee/sig00001cc4 ), + .Q(\blk00000003/sig00001093 ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000cee/blk00000d16 ( + .A0(\blk00000003/blk00000cee/sig00001cb0 ), + .A1(\blk00000003/blk00000cee/sig00001cb0 ), + .A2(\blk00000003/blk00000cee/sig00001cb0 ), + .A3(\blk00000003/blk00000cee/sig00001cb0 ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(\blk00000003/sig00000c72 ), + .Q(\blk00000003/blk00000cee/sig00001cc4 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000cee/blk00000d15 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/blk00000cee/sig00001cc3 ), + .Q(\blk00000003/sig00001095 ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000cee/blk00000d14 ( + .A0(\blk00000003/blk00000cee/sig00001cb0 ), + .A1(\blk00000003/blk00000cee/sig00001cb0 ), + .A2(\blk00000003/blk00000cee/sig00001cb0 ), + .A3(\blk00000003/blk00000cee/sig00001cb0 ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(\blk00000003/sig00000c74 ), + .Q(\blk00000003/blk00000cee/sig00001cc3 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000cee/blk00000d13 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/blk00000cee/sig00001cc2 ), + .Q(\blk00000003/sig00001096 ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000cee/blk00000d12 ( + .A0(\blk00000003/blk00000cee/sig00001cb0 ), + .A1(\blk00000003/blk00000cee/sig00001cb0 ), + .A2(\blk00000003/blk00000cee/sig00001cb0 ), + .A3(\blk00000003/blk00000cee/sig00001cb0 ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(\blk00000003/sig00000c75 ), + .Q(\blk00000003/blk00000cee/sig00001cc2 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000cee/blk00000d11 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/blk00000cee/sig00001cc1 ), + .Q(\blk00000003/sig00001094 ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000cee/blk00000d10 ( + .A0(\blk00000003/blk00000cee/sig00001cb0 ), + .A1(\blk00000003/blk00000cee/sig00001cb0 ), + .A2(\blk00000003/blk00000cee/sig00001cb0 ), + .A3(\blk00000003/blk00000cee/sig00001cb0 ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(\blk00000003/sig00000c73 ), + .Q(\blk00000003/blk00000cee/sig00001cc1 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000cee/blk00000d0f ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/blk00000cee/sig00001cc0 ), + .Q(\blk00000003/sig00001097 ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000cee/blk00000d0e ( + .A0(\blk00000003/blk00000cee/sig00001cb0 ), + .A1(\blk00000003/blk00000cee/sig00001cb0 ), + .A2(\blk00000003/blk00000cee/sig00001cb0 ), + .A3(\blk00000003/blk00000cee/sig00001cb0 ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(\blk00000003/sig00000c76 ), + .Q(\blk00000003/blk00000cee/sig00001cc0 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000cee/blk00000d0d ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/blk00000cee/sig00001cbf ), + .Q(\blk00000003/sig00001098 ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000cee/blk00000d0c ( + .A0(\blk00000003/blk00000cee/sig00001cb0 ), + .A1(\blk00000003/blk00000cee/sig00001cb0 ), + .A2(\blk00000003/blk00000cee/sig00001cb0 ), + .A3(\blk00000003/blk00000cee/sig00001cb0 ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(\blk00000003/sig00000c77 ), + .Q(\blk00000003/blk00000cee/sig00001cbf ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000cee/blk00000d0b ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/blk00000cee/sig00001cbe ), + .Q(\blk00000003/sig0000109a ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000cee/blk00000d0a ( + .A0(\blk00000003/blk00000cee/sig00001cb0 ), + .A1(\blk00000003/blk00000cee/sig00001cb0 ), + .A2(\blk00000003/blk00000cee/sig00001cb0 ), + .A3(\blk00000003/blk00000cee/sig00001cb0 ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(\blk00000003/sig00000c79 ), + .Q(\blk00000003/blk00000cee/sig00001cbe ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000cee/blk00000d09 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/blk00000cee/sig00001cbd ), + .Q(\blk00000003/sig0000109b ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000cee/blk00000d08 ( + .A0(\blk00000003/blk00000cee/sig00001cb0 ), + .A1(\blk00000003/blk00000cee/sig00001cb0 ), + .A2(\blk00000003/blk00000cee/sig00001cb0 ), + .A3(\blk00000003/blk00000cee/sig00001cb0 ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(\blk00000003/sig00000c7a ), + .Q(\blk00000003/blk00000cee/sig00001cbd ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000cee/blk00000d07 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/blk00000cee/sig00001cbc ), + .Q(\blk00000003/sig00001099 ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000cee/blk00000d06 ( + .A0(\blk00000003/blk00000cee/sig00001cb0 ), + .A1(\blk00000003/blk00000cee/sig00001cb0 ), + .A2(\blk00000003/blk00000cee/sig00001cb0 ), + .A3(\blk00000003/blk00000cee/sig00001cb0 ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(\blk00000003/sig00000c78 ), + .Q(\blk00000003/blk00000cee/sig00001cbc ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000cee/blk00000d05 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/blk00000cee/sig00001cbb ), + .Q(\blk00000003/sig0000109c ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000cee/blk00000d04 ( + .A0(\blk00000003/blk00000cee/sig00001cb0 ), + .A1(\blk00000003/blk00000cee/sig00001cb0 ), + .A2(\blk00000003/blk00000cee/sig00001cb0 ), + .A3(\blk00000003/blk00000cee/sig00001cb0 ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(\blk00000003/sig00000c7b ), + .Q(\blk00000003/blk00000cee/sig00001cbb ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000cee/blk00000d03 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/blk00000cee/sig00001cba ), + .Q(\blk00000003/sig0000109d ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000cee/blk00000d02 ( + .A0(\blk00000003/blk00000cee/sig00001cb0 ), + .A1(\blk00000003/blk00000cee/sig00001cb0 ), + .A2(\blk00000003/blk00000cee/sig00001cb0 ), + .A3(\blk00000003/blk00000cee/sig00001cb0 ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(\blk00000003/sig00000c7c ), + .Q(\blk00000003/blk00000cee/sig00001cba ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000cee/blk00000d01 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/blk00000cee/sig00001cb9 ), + .Q(\blk00000003/sig0000109f ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000cee/blk00000d00 ( + .A0(\blk00000003/blk00000cee/sig00001cb0 ), + .A1(\blk00000003/blk00000cee/sig00001cb0 ), + .A2(\blk00000003/blk00000cee/sig00001cb0 ), + .A3(\blk00000003/blk00000cee/sig00001cb0 ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(\blk00000003/sig00000c7e ), + .Q(\blk00000003/blk00000cee/sig00001cb9 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000cee/blk00000cff ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/blk00000cee/sig00001cb8 ), + .Q(\blk00000003/sig000010a0 ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000cee/blk00000cfe ( + .A0(\blk00000003/blk00000cee/sig00001cb0 ), + .A1(\blk00000003/blk00000cee/sig00001cb0 ), + .A2(\blk00000003/blk00000cee/sig00001cb0 ), + .A3(\blk00000003/blk00000cee/sig00001cb0 ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(\blk00000003/sig00000c7f ), + .Q(\blk00000003/blk00000cee/sig00001cb8 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000cee/blk00000cfd ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/blk00000cee/sig00001cb7 ), + .Q(\blk00000003/sig0000109e ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000cee/blk00000cfc ( + .A0(\blk00000003/blk00000cee/sig00001cb0 ), + .A1(\blk00000003/blk00000cee/sig00001cb0 ), + .A2(\blk00000003/blk00000cee/sig00001cb0 ), + .A3(\blk00000003/blk00000cee/sig00001cb0 ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(\blk00000003/sig00000c7d ), + .Q(\blk00000003/blk00000cee/sig00001cb7 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000cee/blk00000cfb ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/blk00000cee/sig00001cb6 ), + .Q(\blk00000003/sig000010a2 ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000cee/blk00000cfa ( + .A0(\blk00000003/blk00000cee/sig00001cb0 ), + .A1(\blk00000003/blk00000cee/sig00001cb0 ), + .A2(\blk00000003/blk00000cee/sig00001cb0 ), + .A3(\blk00000003/blk00000cee/sig00001cb0 ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(\blk00000003/sig00000c81 ), + .Q(\blk00000003/blk00000cee/sig00001cb6 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000cee/blk00000cf9 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/blk00000cee/sig00001cb5 ), + .Q(\blk00000003/sig000010a3 ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000cee/blk00000cf8 ( + .A0(\blk00000003/blk00000cee/sig00001cb0 ), + .A1(\blk00000003/blk00000cee/sig00001cb0 ), + .A2(\blk00000003/blk00000cee/sig00001cb0 ), + .A3(\blk00000003/blk00000cee/sig00001cb0 ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(\blk00000003/sig00000c82 ), + .Q(\blk00000003/blk00000cee/sig00001cb5 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000cee/blk00000cf7 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/blk00000cee/sig00001cb4 ), + .Q(\blk00000003/sig000010a1 ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000cee/blk00000cf6 ( + .A0(\blk00000003/blk00000cee/sig00001cb0 ), + .A1(\blk00000003/blk00000cee/sig00001cb0 ), + .A2(\blk00000003/blk00000cee/sig00001cb0 ), + .A3(\blk00000003/blk00000cee/sig00001cb0 ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(\blk00000003/sig00000c80 ), + .Q(\blk00000003/blk00000cee/sig00001cb4 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000cee/blk00000cf5 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/blk00000cee/sig00001cb3 ), + .Q(\blk00000003/sig000010a5 ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000cee/blk00000cf4 ( + .A0(\blk00000003/blk00000cee/sig00001cb0 ), + .A1(\blk00000003/blk00000cee/sig00001cb0 ), + .A2(\blk00000003/blk00000cee/sig00001cb0 ), + .A3(\blk00000003/blk00000cee/sig00001cb0 ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(\blk00000003/sig00000fa2 ), + .Q(\blk00000003/blk00000cee/sig00001cb3 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000cee/blk00000cf3 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/blk00000cee/sig00001cb2 ), + .Q(\blk00000003/sig000010a6 ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000cee/blk00000cf2 ( + .A0(\blk00000003/blk00000cee/sig00001cb0 ), + .A1(\blk00000003/blk00000cee/sig00001cb0 ), + .A2(\blk00000003/blk00000cee/sig00001cb0 ), + .A3(\blk00000003/blk00000cee/sig00001cb0 ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(\blk00000003/sig00000fa3 ), + .Q(\blk00000003/blk00000cee/sig00001cb2 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000cee/blk00000cf1 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/blk00000cee/sig00001cb1 ), + .Q(\blk00000003/sig000010a4 ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000cee/blk00000cf0 ( + .A0(\blk00000003/blk00000cee/sig00001cb0 ), + .A1(\blk00000003/blk00000cee/sig00001cb0 ), + .A2(\blk00000003/blk00000cee/sig00001cb0 ), + .A3(\blk00000003/blk00000cee/sig00001cb0 ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(\blk00000003/sig00000c83 ), + .Q(\blk00000003/blk00000cee/sig00001cb1 ) + ); + GND \blk00000003/blk00000cee/blk00000cef ( + .G(\blk00000003/blk00000cee/sig00001cb0 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000d9c/blk00000dc9 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/blk00000d9c/sig00001d0a ), + .Q(\blk00000003/sig00001155 ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000d9c/blk00000dc8 ( + .A0(\blk00000003/blk00000d9c/sig00001cf4 ), + .A1(\blk00000003/blk00000d9c/sig00001cf4 ), + .A2(\blk00000003/blk00000d9c/sig00001cf4 ), + .A3(\blk00000003/blk00000d9c/sig00001cf4 ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(\blk00000003/sig00000ffb ), + .Q(\blk00000003/blk00000d9c/sig00001d0a ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000d9c/blk00000dc7 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/blk00000d9c/sig00001d09 ), + .Q(\blk00000003/sig00001156 ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000d9c/blk00000dc6 ( + .A0(\blk00000003/blk00000d9c/sig00001cf4 ), + .A1(\blk00000003/blk00000d9c/sig00001cf4 ), + .A2(\blk00000003/blk00000d9c/sig00001cf4 ), + .A3(\blk00000003/blk00000d9c/sig00001cf4 ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(\blk00000003/sig00000ff9 ), + .Q(\blk00000003/blk00000d9c/sig00001d09 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000d9c/blk00000dc5 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/blk00000d9c/sig00001d08 ), + .Q(\blk00000003/sig00001158 ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000d9c/blk00000dc4 ( + .A0(\blk00000003/blk00000d9c/sig00001cf4 ), + .A1(\blk00000003/blk00000d9c/sig00001cf4 ), + .A2(\blk00000003/blk00000d9c/sig00001cf4 ), + .A3(\blk00000003/blk00000d9c/sig00001cf4 ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(\blk00000003/sig00000ff5 ), + .Q(\blk00000003/blk00000d9c/sig00001d08 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000d9c/blk00000dc3 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/blk00000d9c/sig00001d07 ), + .Q(\blk00000003/sig00001159 ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000d9c/blk00000dc2 ( + .A0(\blk00000003/blk00000d9c/sig00001cf4 ), + .A1(\blk00000003/blk00000d9c/sig00001cf4 ), + .A2(\blk00000003/blk00000d9c/sig00001cf4 ), + .A3(\blk00000003/blk00000d9c/sig00001cf4 ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(\blk00000003/sig00000ff3 ), + .Q(\blk00000003/blk00000d9c/sig00001d07 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000d9c/blk00000dc1 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/blk00000d9c/sig00001d06 ), + .Q(\blk00000003/sig00001157 ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000d9c/blk00000dc0 ( + .A0(\blk00000003/blk00000d9c/sig00001cf4 ), + .A1(\blk00000003/blk00000d9c/sig00001cf4 ), + .A2(\blk00000003/blk00000d9c/sig00001cf4 ), + .A3(\blk00000003/blk00000d9c/sig00001cf4 ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(\blk00000003/sig00000ff7 ), + .Q(\blk00000003/blk00000d9c/sig00001d06 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000d9c/blk00000dbf ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/blk00000d9c/sig00001d05 ), + .Q(\blk00000003/sig0000115b ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000d9c/blk00000dbe ( + .A0(\blk00000003/blk00000d9c/sig00001cf4 ), + .A1(\blk00000003/blk00000d9c/sig00001cf4 ), + .A2(\blk00000003/blk00000d9c/sig00001cf4 ), + .A3(\blk00000003/blk00000d9c/sig00001cf4 ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(\blk00000003/sig00000fef ), + .Q(\blk00000003/blk00000d9c/sig00001d05 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000d9c/blk00000dbd ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/blk00000d9c/sig00001d04 ), + .Q(\blk00000003/sig0000115c ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000d9c/blk00000dbc ( + .A0(\blk00000003/blk00000d9c/sig00001cf4 ), + .A1(\blk00000003/blk00000d9c/sig00001cf4 ), + .A2(\blk00000003/blk00000d9c/sig00001cf4 ), + .A3(\blk00000003/blk00000d9c/sig00001cf4 ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(\blk00000003/sig00000fed ), + .Q(\blk00000003/blk00000d9c/sig00001d04 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000d9c/blk00000dbb ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/blk00000d9c/sig00001d03 ), + .Q(\blk00000003/sig0000115a ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000d9c/blk00000dba ( + .A0(\blk00000003/blk00000d9c/sig00001cf4 ), + .A1(\blk00000003/blk00000d9c/sig00001cf4 ), + .A2(\blk00000003/blk00000d9c/sig00001cf4 ), + .A3(\blk00000003/blk00000d9c/sig00001cf4 ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(\blk00000003/sig00000ff1 ), + .Q(\blk00000003/blk00000d9c/sig00001d03 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000d9c/blk00000db9 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/blk00000d9c/sig00001d02 ), + .Q(\blk00000003/sig0000115e ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000d9c/blk00000db8 ( + .A0(\blk00000003/blk00000d9c/sig00001cf4 ), + .A1(\blk00000003/blk00000d9c/sig00001cf4 ), + .A2(\blk00000003/blk00000d9c/sig00001cf4 ), + .A3(\blk00000003/blk00000d9c/sig00001cf4 ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(\blk00000003/sig00000fe9 ), + .Q(\blk00000003/blk00000d9c/sig00001d02 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000d9c/blk00000db7 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/blk00000d9c/sig00001d01 ), + .Q(\blk00000003/sig0000115f ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000d9c/blk00000db6 ( + .A0(\blk00000003/blk00000d9c/sig00001cf4 ), + .A1(\blk00000003/blk00000d9c/sig00001cf4 ), + .A2(\blk00000003/blk00000d9c/sig00001cf4 ), + .A3(\blk00000003/blk00000d9c/sig00001cf4 ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(\blk00000003/sig00000fe7 ), + .Q(\blk00000003/blk00000d9c/sig00001d01 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000d9c/blk00000db5 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/blk00000d9c/sig00001d00 ), + .Q(\blk00000003/sig0000115d ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000d9c/blk00000db4 ( + .A0(\blk00000003/blk00000d9c/sig00001cf4 ), + .A1(\blk00000003/blk00000d9c/sig00001cf4 ), + .A2(\blk00000003/blk00000d9c/sig00001cf4 ), + .A3(\blk00000003/blk00000d9c/sig00001cf4 ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(\blk00000003/sig00000feb ), + .Q(\blk00000003/blk00000d9c/sig00001d00 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000d9c/blk00000db3 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/blk00000d9c/sig00001cff ), + .Q(\blk00000003/sig00001160 ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000d9c/blk00000db2 ( + .A0(\blk00000003/blk00000d9c/sig00001cf4 ), + .A1(\blk00000003/blk00000d9c/sig00001cf4 ), + .A2(\blk00000003/blk00000d9c/sig00001cf4 ), + .A3(\blk00000003/blk00000d9c/sig00001cf4 ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(\blk00000003/sig00000fe5 ), + .Q(\blk00000003/blk00000d9c/sig00001cff ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000d9c/blk00000db1 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/blk00000d9c/sig00001cfe ), + .Q(\blk00000003/sig00001161 ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000d9c/blk00000db0 ( + .A0(\blk00000003/blk00000d9c/sig00001cf4 ), + .A1(\blk00000003/blk00000d9c/sig00001cf4 ), + .A2(\blk00000003/blk00000d9c/sig00001cf4 ), + .A3(\blk00000003/blk00000d9c/sig00001cf4 ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(\blk00000003/sig00000fe3 ), + .Q(\blk00000003/blk00000d9c/sig00001cfe ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000d9c/blk00000daf ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/blk00000d9c/sig00001cfd ), + .Q(\blk00000003/sig00001163 ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000d9c/blk00000dae ( + .A0(\blk00000003/blk00000d9c/sig00001cf4 ), + .A1(\blk00000003/blk00000d9c/sig00001cf4 ), + .A2(\blk00000003/blk00000d9c/sig00001cf4 ), + .A3(\blk00000003/blk00000d9c/sig00001cf4 ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(\blk00000003/sig00000fdf ), + .Q(\blk00000003/blk00000d9c/sig00001cfd ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000d9c/blk00000dad ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/blk00000d9c/sig00001cfc ), + .Q(\blk00000003/sig00001164 ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000d9c/blk00000dac ( + .A0(\blk00000003/blk00000d9c/sig00001cf4 ), + .A1(\blk00000003/blk00000d9c/sig00001cf4 ), + .A2(\blk00000003/blk00000d9c/sig00001cf4 ), + .A3(\blk00000003/blk00000d9c/sig00001cf4 ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(\blk00000003/sig00000fdd ), + .Q(\blk00000003/blk00000d9c/sig00001cfc ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000d9c/blk00000dab ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/blk00000d9c/sig00001cfb ), + .Q(\blk00000003/sig00001162 ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000d9c/blk00000daa ( + .A0(\blk00000003/blk00000d9c/sig00001cf4 ), + .A1(\blk00000003/blk00000d9c/sig00001cf4 ), + .A2(\blk00000003/blk00000d9c/sig00001cf4 ), + .A3(\blk00000003/blk00000d9c/sig00001cf4 ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(\blk00000003/sig00000fe1 ), + .Q(\blk00000003/blk00000d9c/sig00001cfb ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000d9c/blk00000da9 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/blk00000d9c/sig00001cfa ), + .Q(\blk00000003/sig00001166 ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000d9c/blk00000da8 ( + .A0(\blk00000003/blk00000d9c/sig00001cf4 ), + .A1(\blk00000003/blk00000d9c/sig00001cf4 ), + .A2(\blk00000003/blk00000d9c/sig00001cf4 ), + .A3(\blk00000003/blk00000d9c/sig00001cf4 ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(\blk00000003/sig00000fd9 ), + .Q(\blk00000003/blk00000d9c/sig00001cfa ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000d9c/blk00000da7 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/blk00000d9c/sig00001cf9 ), + .Q(\blk00000003/sig00001167 ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000d9c/blk00000da6 ( + .A0(\blk00000003/blk00000d9c/sig00001cf4 ), + .A1(\blk00000003/blk00000d9c/sig00001cf4 ), + .A2(\blk00000003/blk00000d9c/sig00001cf4 ), + .A3(\blk00000003/blk00000d9c/sig00001cf4 ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(\blk00000003/sig00000fd7 ), + .Q(\blk00000003/blk00000d9c/sig00001cf9 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000d9c/blk00000da5 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/blk00000d9c/sig00001cf8 ), + .Q(\blk00000003/sig00001165 ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000d9c/blk00000da4 ( + .A0(\blk00000003/blk00000d9c/sig00001cf4 ), + .A1(\blk00000003/blk00000d9c/sig00001cf4 ), + .A2(\blk00000003/blk00000d9c/sig00001cf4 ), + .A3(\blk00000003/blk00000d9c/sig00001cf4 ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(\blk00000003/sig00000fdb ), + .Q(\blk00000003/blk00000d9c/sig00001cf8 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000d9c/blk00000da3 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/blk00000d9c/sig00001cf7 ), + .Q(\blk00000003/sig00001169 ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000d9c/blk00000da2 ( + .A0(\blk00000003/blk00000d9c/sig00001cf4 ), + .A1(\blk00000003/blk00000d9c/sig00001cf4 ), + .A2(\blk00000003/blk00000d9c/sig00001cf4 ), + .A3(\blk00000003/blk00000d9c/sig00001cf4 ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(\blk00000003/sig00000fd3 ), + .Q(\blk00000003/blk00000d9c/sig00001cf7 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000d9c/blk00000da1 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/blk00000d9c/sig00001cf6 ), + .Q(\blk00000003/sig0000116a ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000d9c/blk00000da0 ( + .A0(\blk00000003/blk00000d9c/sig00001cf4 ), + .A1(\blk00000003/blk00000d9c/sig00001cf4 ), + .A2(\blk00000003/blk00000d9c/sig00001cf4 ), + .A3(\blk00000003/blk00000d9c/sig00001cf4 ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(\blk00000003/sig00000fd1 ), + .Q(\blk00000003/blk00000d9c/sig00001cf6 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000d9c/blk00000d9f ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/blk00000d9c/sig00001cf5 ), + .Q(\blk00000003/sig00001168 ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000d9c/blk00000d9e ( + .A0(\blk00000003/blk00000d9c/sig00001cf4 ), + .A1(\blk00000003/blk00000d9c/sig00001cf4 ), + .A2(\blk00000003/blk00000d9c/sig00001cf4 ), + .A3(\blk00000003/blk00000d9c/sig00001cf4 ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(\blk00000003/sig00000fd5 ), + .Q(\blk00000003/blk00000d9c/sig00001cf5 ) + ); + GND \blk00000003/blk00000d9c/blk00000d9d ( + .G(\blk00000003/blk00000d9c/sig00001cf4 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000dca/blk00000df7 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/blk00000dca/sig00001d4f ), + .Q(\blk00000003/sig0000116b ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000dca/blk00000df6 ( + .A0(\blk00000003/blk00000dca/sig00001d39 ), + .A1(\blk00000003/blk00000dca/sig00001d39 ), + .A2(\blk00000003/blk00000dca/sig00001d39 ), + .A3(\blk00000003/blk00000dca/sig00001d39 ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(\blk00000003/sig0000113f ), + .Q(\blk00000003/blk00000dca/sig00001d4f ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000dca/blk00000df5 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/blk00000dca/sig00001d4e ), + .Q(\blk00000003/sig0000116c ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000dca/blk00000df4 ( + .A0(\blk00000003/blk00000dca/sig00001d39 ), + .A1(\blk00000003/blk00000dca/sig00001d39 ), + .A2(\blk00000003/blk00000dca/sig00001d39 ), + .A3(\blk00000003/blk00000dca/sig00001d39 ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(\blk00000003/sig00001140 ), + .Q(\blk00000003/blk00000dca/sig00001d4e ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000dca/blk00000df3 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/blk00000dca/sig00001d4d ), + .Q(\blk00000003/sig0000116e ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000dca/blk00000df2 ( + .A0(\blk00000003/blk00000dca/sig00001d39 ), + .A1(\blk00000003/blk00000dca/sig00001d39 ), + .A2(\blk00000003/blk00000dca/sig00001d39 ), + .A3(\blk00000003/blk00000dca/sig00001d39 ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(\blk00000003/sig00001142 ), + .Q(\blk00000003/blk00000dca/sig00001d4d ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000dca/blk00000df1 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/blk00000dca/sig00001d4c ), + .Q(\blk00000003/sig0000116f ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000dca/blk00000df0 ( + .A0(\blk00000003/blk00000dca/sig00001d39 ), + .A1(\blk00000003/blk00000dca/sig00001d39 ), + .A2(\blk00000003/blk00000dca/sig00001d39 ), + .A3(\blk00000003/blk00000dca/sig00001d39 ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(\blk00000003/sig00001143 ), + .Q(\blk00000003/blk00000dca/sig00001d4c ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000dca/blk00000def ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/blk00000dca/sig00001d4b ), + .Q(\blk00000003/sig0000116d ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000dca/blk00000dee ( + .A0(\blk00000003/blk00000dca/sig00001d39 ), + .A1(\blk00000003/blk00000dca/sig00001d39 ), + .A2(\blk00000003/blk00000dca/sig00001d39 ), + .A3(\blk00000003/blk00000dca/sig00001d39 ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(\blk00000003/sig00001141 ), + .Q(\blk00000003/blk00000dca/sig00001d4b ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000dca/blk00000ded ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/blk00000dca/sig00001d4a ), + .Q(\blk00000003/sig00001171 ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000dca/blk00000dec ( + .A0(\blk00000003/blk00000dca/sig00001d39 ), + .A1(\blk00000003/blk00000dca/sig00001d39 ), + .A2(\blk00000003/blk00000dca/sig00001d39 ), + .A3(\blk00000003/blk00000dca/sig00001d39 ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(\blk00000003/sig00001145 ), + .Q(\blk00000003/blk00000dca/sig00001d4a ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000dca/blk00000deb ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/blk00000dca/sig00001d49 ), + .Q(\blk00000003/sig00001172 ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000dca/blk00000dea ( + .A0(\blk00000003/blk00000dca/sig00001d39 ), + .A1(\blk00000003/blk00000dca/sig00001d39 ), + .A2(\blk00000003/blk00000dca/sig00001d39 ), + .A3(\blk00000003/blk00000dca/sig00001d39 ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(\blk00000003/sig00001146 ), + .Q(\blk00000003/blk00000dca/sig00001d49 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000dca/blk00000de9 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/blk00000dca/sig00001d48 ), + .Q(\blk00000003/sig00001170 ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000dca/blk00000de8 ( + .A0(\blk00000003/blk00000dca/sig00001d39 ), + .A1(\blk00000003/blk00000dca/sig00001d39 ), + .A2(\blk00000003/blk00000dca/sig00001d39 ), + .A3(\blk00000003/blk00000dca/sig00001d39 ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(\blk00000003/sig00001144 ), + .Q(\blk00000003/blk00000dca/sig00001d48 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000dca/blk00000de7 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/blk00000dca/sig00001d47 ), + .Q(\blk00000003/sig00001174 ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000dca/blk00000de6 ( + .A0(\blk00000003/blk00000dca/sig00001d39 ), + .A1(\blk00000003/blk00000dca/sig00001d39 ), + .A2(\blk00000003/blk00000dca/sig00001d39 ), + .A3(\blk00000003/blk00000dca/sig00001d39 ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(\blk00000003/sig00001148 ), + .Q(\blk00000003/blk00000dca/sig00001d47 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000dca/blk00000de5 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/blk00000dca/sig00001d46 ), + .Q(\blk00000003/sig00001175 ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000dca/blk00000de4 ( + .A0(\blk00000003/blk00000dca/sig00001d39 ), + .A1(\blk00000003/blk00000dca/sig00001d39 ), + .A2(\blk00000003/blk00000dca/sig00001d39 ), + .A3(\blk00000003/blk00000dca/sig00001d39 ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(\blk00000003/sig00001149 ), + .Q(\blk00000003/blk00000dca/sig00001d46 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000dca/blk00000de3 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/blk00000dca/sig00001d45 ), + .Q(\blk00000003/sig00001173 ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000dca/blk00000de2 ( + .A0(\blk00000003/blk00000dca/sig00001d39 ), + .A1(\blk00000003/blk00000dca/sig00001d39 ), + .A2(\blk00000003/blk00000dca/sig00001d39 ), + .A3(\blk00000003/blk00000dca/sig00001d39 ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(\blk00000003/sig00001147 ), + .Q(\blk00000003/blk00000dca/sig00001d45 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000dca/blk00000de1 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/blk00000dca/sig00001d44 ), + .Q(\blk00000003/sig00001176 ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000dca/blk00000de0 ( + .A0(\blk00000003/blk00000dca/sig00001d39 ), + .A1(\blk00000003/blk00000dca/sig00001d39 ), + .A2(\blk00000003/blk00000dca/sig00001d39 ), + .A3(\blk00000003/blk00000dca/sig00001d39 ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(\blk00000003/sig0000114a ), + .Q(\blk00000003/blk00000dca/sig00001d44 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000dca/blk00000ddf ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/blk00000dca/sig00001d43 ), + .Q(\blk00000003/sig00001177 ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000dca/blk00000dde ( + .A0(\blk00000003/blk00000dca/sig00001d39 ), + .A1(\blk00000003/blk00000dca/sig00001d39 ), + .A2(\blk00000003/blk00000dca/sig00001d39 ), + .A3(\blk00000003/blk00000dca/sig00001d39 ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(\blk00000003/sig0000114b ), + .Q(\blk00000003/blk00000dca/sig00001d43 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000dca/blk00000ddd ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/blk00000dca/sig00001d42 ), + .Q(\blk00000003/sig00001179 ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000dca/blk00000ddc ( + .A0(\blk00000003/blk00000dca/sig00001d39 ), + .A1(\blk00000003/blk00000dca/sig00001d39 ), + .A2(\blk00000003/blk00000dca/sig00001d39 ), + .A3(\blk00000003/blk00000dca/sig00001d39 ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(\blk00000003/sig0000114d ), + .Q(\blk00000003/blk00000dca/sig00001d42 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000dca/blk00000ddb ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/blk00000dca/sig00001d41 ), + .Q(\blk00000003/sig0000117a ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000dca/blk00000dda ( + .A0(\blk00000003/blk00000dca/sig00001d39 ), + .A1(\blk00000003/blk00000dca/sig00001d39 ), + .A2(\blk00000003/blk00000dca/sig00001d39 ), + .A3(\blk00000003/blk00000dca/sig00001d39 ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(\blk00000003/sig0000114e ), + .Q(\blk00000003/blk00000dca/sig00001d41 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000dca/blk00000dd9 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/blk00000dca/sig00001d40 ), + .Q(\blk00000003/sig00001178 ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000dca/blk00000dd8 ( + .A0(\blk00000003/blk00000dca/sig00001d39 ), + .A1(\blk00000003/blk00000dca/sig00001d39 ), + .A2(\blk00000003/blk00000dca/sig00001d39 ), + .A3(\blk00000003/blk00000dca/sig00001d39 ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(\blk00000003/sig0000114c ), + .Q(\blk00000003/blk00000dca/sig00001d40 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000dca/blk00000dd7 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/blk00000dca/sig00001d3f ), + .Q(\blk00000003/sig0000117c ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000dca/blk00000dd6 ( + .A0(\blk00000003/blk00000dca/sig00001d39 ), + .A1(\blk00000003/blk00000dca/sig00001d39 ), + .A2(\blk00000003/blk00000dca/sig00001d39 ), + .A3(\blk00000003/blk00000dca/sig00001d39 ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(\blk00000003/sig00001150 ), + .Q(\blk00000003/blk00000dca/sig00001d3f ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000dca/blk00000dd5 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/blk00000dca/sig00001d3e ), + .Q(\blk00000003/sig0000117d ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000dca/blk00000dd4 ( + .A0(\blk00000003/blk00000dca/sig00001d39 ), + .A1(\blk00000003/blk00000dca/sig00001d39 ), + .A2(\blk00000003/blk00000dca/sig00001d39 ), + .A3(\blk00000003/blk00000dca/sig00001d39 ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(\blk00000003/sig00001151 ), + .Q(\blk00000003/blk00000dca/sig00001d3e ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000dca/blk00000dd3 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/blk00000dca/sig00001d3d ), + .Q(\blk00000003/sig0000117b ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000dca/blk00000dd2 ( + .A0(\blk00000003/blk00000dca/sig00001d39 ), + .A1(\blk00000003/blk00000dca/sig00001d39 ), + .A2(\blk00000003/blk00000dca/sig00001d39 ), + .A3(\blk00000003/blk00000dca/sig00001d39 ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(\blk00000003/sig0000114f ), + .Q(\blk00000003/blk00000dca/sig00001d3d ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000dca/blk00000dd1 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/blk00000dca/sig00001d3c ), + .Q(\blk00000003/sig0000117f ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000dca/blk00000dd0 ( + .A0(\blk00000003/blk00000dca/sig00001d39 ), + .A1(\blk00000003/blk00000dca/sig00001d39 ), + .A2(\blk00000003/blk00000dca/sig00001d39 ), + .A3(\blk00000003/blk00000dca/sig00001d39 ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(\blk00000003/sig00001153 ), + .Q(\blk00000003/blk00000dca/sig00001d3c ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000dca/blk00000dcf ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/blk00000dca/sig00001d3b ), + .Q(\blk00000003/sig00001180 ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000dca/blk00000dce ( + .A0(\blk00000003/blk00000dca/sig00001d39 ), + .A1(\blk00000003/blk00000dca/sig00001d39 ), + .A2(\blk00000003/blk00000dca/sig00001d39 ), + .A3(\blk00000003/blk00000dca/sig00001d39 ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(\blk00000003/sig00001154 ), + .Q(\blk00000003/blk00000dca/sig00001d3b ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000dca/blk00000dcd ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/blk00000dca/sig00001d3a ), + .Q(\blk00000003/sig0000117e ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000dca/blk00000dcc ( + .A0(\blk00000003/blk00000dca/sig00001d39 ), + .A1(\blk00000003/blk00000dca/sig00001d39 ), + .A2(\blk00000003/blk00000dca/sig00001d39 ), + .A3(\blk00000003/blk00000dca/sig00001d39 ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(\blk00000003/sig00001152 ), + .Q(\blk00000003/blk00000dca/sig00001d3a ) + ); + GND \blk00000003/blk00000dca/blk00000dcb ( + .G(\blk00000003/blk00000dca/sig00001d39 ) + ); + FD #( + .INIT ( 1'b0 )) + \blk00000003/blk00000df8/blk00000dfe ( + .C(clk), + .D(\blk00000003/blk00000df8/sig00001d58 ), + .Q(\blk00000003/sig00001181 ) + ); + SRL16 #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000df8/blk00000dfd ( + .A0(\blk00000003/blk00000df8/sig00001d55 ), + .A1(\blk00000003/blk00000df8/sig00001d55 ), + .A2(\blk00000003/blk00000df8/sig00001d56 ), + .A3(\blk00000003/blk00000df8/sig00001d55 ), + .CLK(clk), + .D(\blk00000003/sig000008d5 ), + .Q(\blk00000003/blk00000df8/sig00001d58 ) + ); + FD #( + .INIT ( 1'b0 )) + \blk00000003/blk00000df8/blk00000dfc ( + .C(clk), + .D(\blk00000003/blk00000df8/sig00001d57 ), + .Q(\blk00000003/sig00001182 ) + ); + SRL16 #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000df8/blk00000dfb ( + .A0(\blk00000003/blk00000df8/sig00001d55 ), + .A1(\blk00000003/blk00000df8/sig00001d55 ), + .A2(\blk00000003/blk00000df8/sig00001d56 ), + .A3(\blk00000003/blk00000df8/sig00001d55 ), + .CLK(clk), + .D(\blk00000003/sig000008d6 ), + .Q(\blk00000003/blk00000df8/sig00001d57 ) + ); + VCC \blk00000003/blk00000df8/blk00000dfa ( + .P(\blk00000003/blk00000df8/sig00001d56 ) + ); + GND \blk00000003/blk00000df8/blk00000df9 ( + .G(\blk00000003/blk00000df8/sig00001d55 ) + ); + FD #( + .INIT ( 1'b0 )) + \blk00000003/blk00000dff/blk00000e03 ( + .C(clk), + .D(\blk00000003/blk00000dff/sig00001d5e ), + .Q(\blk00000003/sig00001183 ) + ); + SRL16 #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000dff/blk00000e02 ( + .A0(\blk00000003/blk00000dff/sig00001d5d ), + .A1(\blk00000003/blk00000dff/sig00001d5d ), + .A2(\blk00000003/blk00000dff/sig00001d5c ), + .A3(\blk00000003/blk00000dff/sig00001d5c ), + .CLK(clk), + .D(\blk00000003/sig00000fcd ), + .Q(\blk00000003/blk00000dff/sig00001d5e ) + ); + VCC \blk00000003/blk00000dff/blk00000e01 ( + .P(\blk00000003/blk00000dff/sig00001d5d ) + ); + GND \blk00000003/blk00000dff/blk00000e00 ( + .G(\blk00000003/blk00000dff/sig00001d5c ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000e04/blk00000e07 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/blk00000e04/sig00001d64 ), + .Q(\blk00000003/sig00001185 ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000e04/blk00000e06 ( + .A0(\blk00000003/blk00000e04/sig00001d63 ), + .A1(\blk00000003/blk00000e04/sig00001d63 ), + .A2(\blk00000003/blk00000e04/sig00001d63 ), + .A3(\blk00000003/blk00000e04/sig00001d63 ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(\blk00000003/sig00001184 ), + .Q(\blk00000003/blk00000e04/sig00001d64 ) + ); + GND \blk00000003/blk00000e04/blk00000e05 ( + .G(\blk00000003/blk00000e04/sig00001d63 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00000e08/blk00000e0b ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/blk00000e08/sig00001d6a ), + .Q(\blk00000003/sig00001186 ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00000e08/blk00000e0a ( + .A0(\blk00000003/blk00000e08/sig00001d69 ), + .A1(\blk00000003/blk00000e08/sig00001d69 ), + .A2(\blk00000003/blk00000e08/sig00001d69 ), + .A3(\blk00000003/blk00000e08/sig00001d69 ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(\blk00000003/sig00001185 ), + .Q(\blk00000003/blk00000e08/sig00001d6a ) + ); + GND \blk00000003/blk00000e08/blk00000e09 ( + .G(\blk00000003/blk00000e08/sig00001d69 ) + ); + RAMB16BWER #( + .DATA_WIDTH_A ( 36 ), + .DATA_WIDTH_B ( 36 ), + .DOA_REG ( 0 ), + .DOB_REG ( 1 ), + .EN_RSTRAM_A ( "TRUE" ), + .EN_RSTRAM_B ( "TRUE" ), + .INIT_A ( 36'h000000000 ), + .INIT_B ( 36'h000000000 ), + .INITP_00 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INITP_01 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INITP_02 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INITP_03 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INITP_04 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INITP_05 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .SRVAL_A ( 36'h000000000 ), + .INIT_00 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_01 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_02 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_03 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_04 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_05 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_06 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_07 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_08 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_09 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_0A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_0B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_0C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_0D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_0E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_0F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_10 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_11 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_12 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_13 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_14 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_15 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_16 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_17 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_18 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_19 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_1A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_1B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_1C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_1D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_1E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_1F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_20 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_21 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_22 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_23 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_24 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_25 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_26 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_27 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_28 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_29 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_2A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_2B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_2C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_2D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_2E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_2F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_30 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_31 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_32 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_33 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_34 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_35 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_36 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_37 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_38 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_39 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_3A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_3B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_3C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_3D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_3E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_3F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_FILE ( "NONE" ), + .RSTTYPE ( "SYNC" ), + .RST_PRIORITY_A ( "CE" ), + .RST_PRIORITY_B ( "CE" ), + .SIM_COLLISION_CHECK ( "GENERATE_X_ONLY" ), + .SIM_DEVICE ( "SPARTAN3ADSP" ), + .INITP_06 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INITP_07 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .WRITE_MODE_A ( "READ_FIRST" ), + .WRITE_MODE_B ( "READ_FIRST" ), + .SRVAL_B ( 36'h000000000 )) + \blk00000003/blk0000100a/blk0000100e ( + .CLKA(clk), + .CLKB(clk), + .ENA(\blk00000003/blk0000100a/sig00001dd5 ), + .ENB(\blk00000003/blk0000100a/sig00001dd5 ), + .RSTA(\blk00000003/blk0000100a/sig00001dd6 ), + .RSTB(\blk00000003/blk0000100a/sig00001dd6 ), + .REGCEA(\blk00000003/blk0000100a/sig00001dd6 ), + .REGCEB(\blk00000003/blk0000100a/sig00001dd5 ), + .ADDRA({\blk00000003/sig000000e7 , \blk00000003/sig000000e9 , \blk00000003/sig000000eb , \blk00000003/sig000000ed , \blk00000003/sig000000ef , +\blk00000003/sig000000f1 , \blk00000003/blk0000100a/sig00001dd6 , \blk00000003/blk0000100a/sig00001dd6 , \blk00000003/blk0000100a/sig00001dd6 , +\blk00000003/blk0000100a/sig00001dd6 , \blk00000003/blk0000100a/sig00001dd6 , \blk00000003/blk0000100a/sig00001dd6 , +\blk00000003/blk0000100a/sig00001dd6 , \blk00000003/blk0000100a/sig00001dd6 }), + .ADDRB({\blk00000003/sig000000db , \blk00000003/sig000000dd , \blk00000003/sig000000df , \blk00000003/sig000000e1 , \blk00000003/sig000000e3 , +\blk00000003/sig000000e5 , \blk00000003/blk0000100a/sig00001dd6 , \blk00000003/blk0000100a/sig00001dd6 , \blk00000003/blk0000100a/sig00001dd6 , +\blk00000003/blk0000100a/sig00001dd6 , \blk00000003/blk0000100a/sig00001dd6 , \blk00000003/blk0000100a/sig00001dd6 , +\blk00000003/blk0000100a/sig00001dd6 , \blk00000003/blk0000100a/sig00001dd6 }), + .DIA({\blk00000003/blk0000100a/sig00001dd6 , \blk00000003/blk0000100a/sig00001dd6 , \blk00000003/blk0000100a/sig00001dd6 , +\blk00000003/blk0000100a/sig00001dd6 , \blk00000003/blk0000100a/sig00001dd6 , \blk00000003/blk0000100a/sig00001dd6 , +\blk00000003/blk0000100a/sig00001dd6 , \blk00000003/blk0000100a/sig00001dd6 , \blk00000003/blk0000100a/sig00001dd6 , +\blk00000003/blk0000100a/sig00001dd6 , \blk00000003/blk0000100a/sig00001dd6 , \blk00000003/blk0000100a/sig00001dd6 , +\blk00000003/blk0000100a/sig00001dd6 , \blk00000003/blk0000100a/sig00001dd6 , \blk00000003/blk0000100a/sig00001dd6 , +\blk00000003/blk0000100a/sig00001dd6 , \blk00000003/blk0000100a/sig00001dd6 , \blk00000003/blk0000100a/sig00001dd6 , +\blk00000003/blk0000100a/sig00001dd6 , \blk00000003/blk0000100a/sig00001dd6 , \blk00000003/blk0000100a/sig00001dd6 , +\blk00000003/blk0000100a/sig00001dd6 , \blk00000003/blk0000100a/sig00001dd6 , \blk00000003/sig0000143d , \blk00000003/sig0000143f , +\blk00000003/sig00001440 , \blk00000003/sig00001441 , \blk00000003/sig00001442 , \blk00000003/sig00001443 , \blk00000003/sig00001444 , +\blk00000003/sig00001445 , \blk00000003/sig00001446 }), + .DIB({\blk00000003/blk0000100a/sig00001dd6 , \blk00000003/blk0000100a/sig00001dd6 , \blk00000003/blk0000100a/sig00001dd6 , +\blk00000003/blk0000100a/sig00001dd6 , \blk00000003/blk0000100a/sig00001dd6 , \blk00000003/blk0000100a/sig00001dd6 , +\blk00000003/blk0000100a/sig00001dd6 , \blk00000003/blk0000100a/sig00001dd6 , \blk00000003/blk0000100a/sig00001dd6 , +\blk00000003/blk0000100a/sig00001dd6 , \blk00000003/blk0000100a/sig00001dd6 , \blk00000003/blk0000100a/sig00001dd6 , +\blk00000003/blk0000100a/sig00001dd6 , \blk00000003/blk0000100a/sig00001dd6 , \blk00000003/blk0000100a/sig00001dd6 , +\blk00000003/blk0000100a/sig00001dd6 , \blk00000003/blk0000100a/sig00001dd6 , \blk00000003/blk0000100a/sig00001dd6 , +\blk00000003/blk0000100a/sig00001dd6 , \blk00000003/blk0000100a/sig00001dd6 , \blk00000003/blk0000100a/sig00001dd6 , +\blk00000003/blk0000100a/sig00001dd6 , \blk00000003/blk0000100a/sig00001dd6 , \blk00000003/blk0000100a/sig00001dd6 , +\blk00000003/blk0000100a/sig00001dd6 , \blk00000003/blk0000100a/sig00001dd6 , \blk00000003/blk0000100a/sig00001dd6 , +\blk00000003/blk0000100a/sig00001dd6 , \blk00000003/blk0000100a/sig00001dd6 , \blk00000003/blk0000100a/sig00001dd6 , +\blk00000003/blk0000100a/sig00001dd6 , \blk00000003/blk0000100a/sig00001dd6 }), + .DIPA({\blk00000003/blk0000100a/sig00001dd6 , \blk00000003/blk0000100a/sig00001dd6 , \blk00000003/blk0000100a/sig00001dd6 , +\blk00000003/sig0000143e }), + .DIPB({\blk00000003/blk0000100a/sig00001dd6 , \blk00000003/blk0000100a/sig00001dd6 , \blk00000003/blk0000100a/sig00001dd6 , +\blk00000003/blk0000100a/sig00001dd6 }), + .WEA({\blk00000003/sig000005e3 , \blk00000003/sig000005e3 , \blk00000003/sig000005e3 , \blk00000003/sig000005e3 }), + .WEB({\blk00000003/blk0000100a/sig00001dd6 , \blk00000003/blk0000100a/sig00001dd6 , \blk00000003/blk0000100a/sig00001dd6 , +\blk00000003/blk0000100a/sig00001dd6 }), + .DOA({\NLW_blk00000003/blk0000100a/blk0000100e_DOA<31>_UNCONNECTED , \NLW_blk00000003/blk0000100a/blk0000100e_DOA<30>_UNCONNECTED , +\NLW_blk00000003/blk0000100a/blk0000100e_DOA<29>_UNCONNECTED , \NLW_blk00000003/blk0000100a/blk0000100e_DOA<28>_UNCONNECTED , +\NLW_blk00000003/blk0000100a/blk0000100e_DOA<27>_UNCONNECTED , \NLW_blk00000003/blk0000100a/blk0000100e_DOA<26>_UNCONNECTED , +\NLW_blk00000003/blk0000100a/blk0000100e_DOA<25>_UNCONNECTED , \NLW_blk00000003/blk0000100a/blk0000100e_DOA<24>_UNCONNECTED , +\NLW_blk00000003/blk0000100a/blk0000100e_DOA<23>_UNCONNECTED , \NLW_blk00000003/blk0000100a/blk0000100e_DOA<22>_UNCONNECTED , +\NLW_blk00000003/blk0000100a/blk0000100e_DOA<21>_UNCONNECTED , \NLW_blk00000003/blk0000100a/blk0000100e_DOA<20>_UNCONNECTED , +\NLW_blk00000003/blk0000100a/blk0000100e_DOA<19>_UNCONNECTED , \NLW_blk00000003/blk0000100a/blk0000100e_DOA<18>_UNCONNECTED , +\NLW_blk00000003/blk0000100a/blk0000100e_DOA<17>_UNCONNECTED , \NLW_blk00000003/blk0000100a/blk0000100e_DOA<16>_UNCONNECTED , +\NLW_blk00000003/blk0000100a/blk0000100e_DOA<15>_UNCONNECTED , \NLW_blk00000003/blk0000100a/blk0000100e_DOA<14>_UNCONNECTED , +\NLW_blk00000003/blk0000100a/blk0000100e_DOA<13>_UNCONNECTED , \NLW_blk00000003/blk0000100a/blk0000100e_DOA<12>_UNCONNECTED , +\NLW_blk00000003/blk0000100a/blk0000100e_DOA<11>_UNCONNECTED , \NLW_blk00000003/blk0000100a/blk0000100e_DOA<10>_UNCONNECTED , +\NLW_blk00000003/blk0000100a/blk0000100e_DOA<9>_UNCONNECTED , \NLW_blk00000003/blk0000100a/blk0000100e_DOA<8>_UNCONNECTED , +\NLW_blk00000003/blk0000100a/blk0000100e_DOA<7>_UNCONNECTED , \NLW_blk00000003/blk0000100a/blk0000100e_DOA<6>_UNCONNECTED , +\NLW_blk00000003/blk0000100a/blk0000100e_DOA<5>_UNCONNECTED , \NLW_blk00000003/blk0000100a/blk0000100e_DOA<4>_UNCONNECTED , +\NLW_blk00000003/blk0000100a/blk0000100e_DOA<3>_UNCONNECTED , \NLW_blk00000003/blk0000100a/blk0000100e_DOA<2>_UNCONNECTED , +\NLW_blk00000003/blk0000100a/blk0000100e_DOA<1>_UNCONNECTED , \NLW_blk00000003/blk0000100a/blk0000100e_DOA<0>_UNCONNECTED }), + .DOB({\NLW_blk00000003/blk0000100a/blk0000100e_DOB<31>_UNCONNECTED , \NLW_blk00000003/blk0000100a/blk0000100e_DOB<30>_UNCONNECTED , +\NLW_blk00000003/blk0000100a/blk0000100e_DOB<29>_UNCONNECTED , \NLW_blk00000003/blk0000100a/blk0000100e_DOB<28>_UNCONNECTED , +\NLW_blk00000003/blk0000100a/blk0000100e_DOB<27>_UNCONNECTED , \NLW_blk00000003/blk0000100a/blk0000100e_DOB<26>_UNCONNECTED , +\NLW_blk00000003/blk0000100a/blk0000100e_DOB<25>_UNCONNECTED , \NLW_blk00000003/blk0000100a/blk0000100e_DOB<24>_UNCONNECTED , +\NLW_blk00000003/blk0000100a/blk0000100e_DOB<23>_UNCONNECTED , \NLW_blk00000003/blk0000100a/blk0000100e_DOB<22>_UNCONNECTED , +\NLW_blk00000003/blk0000100a/blk0000100e_DOB<21>_UNCONNECTED , \NLW_blk00000003/blk0000100a/blk0000100e_DOB<20>_UNCONNECTED , +\NLW_blk00000003/blk0000100a/blk0000100e_DOB<19>_UNCONNECTED , \NLW_blk00000003/blk0000100a/blk0000100e_DOB<18>_UNCONNECTED , +\NLW_blk00000003/blk0000100a/blk0000100e_DOB<17>_UNCONNECTED , \NLW_blk00000003/blk0000100a/blk0000100e_DOB<16>_UNCONNECTED , +\NLW_blk00000003/blk0000100a/blk0000100e_DOB<15>_UNCONNECTED , \NLW_blk00000003/blk0000100a/blk0000100e_DOB<14>_UNCONNECTED , +\NLW_blk00000003/blk0000100a/blk0000100e_DOB<13>_UNCONNECTED , \NLW_blk00000003/blk0000100a/blk0000100e_DOB<12>_UNCONNECTED , +\NLW_blk00000003/blk0000100a/blk0000100e_DOB<11>_UNCONNECTED , \NLW_blk00000003/blk0000100a/blk0000100e_DOB<10>_UNCONNECTED , +\NLW_blk00000003/blk0000100a/blk0000100e_DOB<9>_UNCONNECTED , \blk00000003/sig000000aa , \blk00000003/sig000000ad , \blk00000003/sig000000ae , +\blk00000003/sig000000af , \blk00000003/sig000000b0 , \blk00000003/sig000000b1 , \blk00000003/sig000000b2 , \blk00000003/sig000000b3 , +\blk00000003/sig000000b4 }), + .DOPA({\NLW_blk00000003/blk0000100a/blk0000100e_DOPA<3>_UNCONNECTED , \NLW_blk00000003/blk0000100a/blk0000100e_DOPA<2>_UNCONNECTED , +\NLW_blk00000003/blk0000100a/blk0000100e_DOPA<1>_UNCONNECTED , \NLW_blk00000003/blk0000100a/blk0000100e_DOPA<0>_UNCONNECTED }), + .DOPB({\NLW_blk00000003/blk0000100a/blk0000100e_DOPB<3>_UNCONNECTED , \NLW_blk00000003/blk0000100a/blk0000100e_DOPB<2>_UNCONNECTED , +\NLW_blk00000003/blk0000100a/blk0000100e_DOPB<1>_UNCONNECTED , \blk00000003/sig000000ac }) + ); + RAMB16BWER #( + .DATA_WIDTH_A ( 36 ), + .DATA_WIDTH_B ( 36 ), + .DOA_REG ( 0 ), + .DOB_REG ( 1 ), + .EN_RSTRAM_A ( "TRUE" ), + .EN_RSTRAM_B ( "TRUE" ), + .INIT_A ( 36'h000000000 ), + .INIT_B ( 36'h000000000 ), + .INITP_00 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INITP_01 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INITP_02 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INITP_03 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INITP_04 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INITP_05 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .SRVAL_A ( 36'h000000000 ), + .INIT_00 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_01 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_02 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_03 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_04 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_05 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_06 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_07 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_08 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_09 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_0A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_0B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_0C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_0D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_0E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_0F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_10 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_11 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_12 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_13 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_14 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_15 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_16 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_17 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_18 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_19 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_1A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_1B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_1C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_1D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_1E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_1F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_20 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_21 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_22 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_23 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_24 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_25 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_26 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_27 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_28 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_29 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_2A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_2B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_2C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_2D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_2E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_2F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_30 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_31 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_32 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_33 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_34 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_35 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_36 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_37 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_38 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_39 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_3A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_3B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_3C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_3D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_3E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_3F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INIT_FILE ( "NONE" ), + .RSTTYPE ( "SYNC" ), + .RST_PRIORITY_A ( "CE" ), + .RST_PRIORITY_B ( "CE" ), + .SIM_COLLISION_CHECK ( "GENERATE_X_ONLY" ), + .SIM_DEVICE ( "SPARTAN3ADSP" ), + .INITP_06 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .INITP_07 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ), + .WRITE_MODE_A ( "READ_FIRST" ), + .WRITE_MODE_B ( "READ_FIRST" ), + .SRVAL_B ( 36'h000000000 )) + \blk00000003/blk0000100a/blk0000100d ( + .CLKA(clk), + .CLKB(clk), + .ENA(\blk00000003/blk0000100a/sig00001dd5 ), + .ENB(\blk00000003/blk0000100a/sig00001dd5 ), + .RSTA(\blk00000003/blk0000100a/sig00001dd6 ), + .RSTB(\blk00000003/blk0000100a/sig00001dd6 ), + .REGCEA(\blk00000003/blk0000100a/sig00001dd6 ), + .REGCEB(\blk00000003/blk0000100a/sig00001dd5 ), + .ADDRA({\blk00000003/sig000000e7 , \blk00000003/sig000000e9 , \blk00000003/sig000000eb , \blk00000003/sig000000ed , \blk00000003/sig000000ef , +\blk00000003/sig000000f1 , \blk00000003/blk0000100a/sig00001dd6 , \blk00000003/blk0000100a/sig00001dd6 , \blk00000003/blk0000100a/sig00001dd6 , +\blk00000003/blk0000100a/sig00001dd6 , \blk00000003/blk0000100a/sig00001dd6 , \blk00000003/blk0000100a/sig00001dd6 , +\blk00000003/blk0000100a/sig00001dd6 , \blk00000003/blk0000100a/sig00001dd6 }), + .ADDRB({\blk00000003/sig000000db , \blk00000003/sig000000dd , \blk00000003/sig000000df , \blk00000003/sig000000e1 , \blk00000003/sig000000e3 , +\blk00000003/sig000000e5 , \blk00000003/blk0000100a/sig00001dd6 , \blk00000003/blk0000100a/sig00001dd6 , \blk00000003/blk0000100a/sig00001dd6 , +\blk00000003/blk0000100a/sig00001dd6 , \blk00000003/blk0000100a/sig00001dd6 , \blk00000003/blk0000100a/sig00001dd6 , +\blk00000003/blk0000100a/sig00001dd6 , \blk00000003/blk0000100a/sig00001dd6 }), + .DIA({\blk00000003/sig00001448 , \blk00000003/sig00001449 , \blk00000003/sig0000144a , \blk00000003/sig0000144b , \blk00000003/sig0000144c , +\blk00000003/sig0000144d , \blk00000003/sig0000144e , \blk00000003/sig0000144f , \blk00000003/sig00001451 , \blk00000003/sig00001452 , +\blk00000003/sig00001453 , \blk00000003/sig00001454 , \blk00000003/sig00001455 , \blk00000003/sig00001456 , \blk00000003/sig00001457 , +\blk00000003/sig00001458 , \blk00000003/sig0000145a , \blk00000003/sig0000145b , \blk00000003/sig0000145c , \blk00000003/sig0000145d , +\blk00000003/sig0000145e , \blk00000003/sig0000145f , \blk00000003/sig00001460 , \blk00000003/sig00001461 , \blk00000003/sig00001463 , +\blk00000003/sig00001464 , \blk00000003/sig00001465 , \blk00000003/sig00001466 , \blk00000003/sig00001467 , \blk00000003/sig00001468 , +\blk00000003/sig00001469 , \blk00000003/sig0000146a }), + .DIB({\blk00000003/blk0000100a/sig00001dd6 , \blk00000003/blk0000100a/sig00001dd6 , \blk00000003/blk0000100a/sig00001dd6 , +\blk00000003/blk0000100a/sig00001dd6 , \blk00000003/blk0000100a/sig00001dd6 , \blk00000003/blk0000100a/sig00001dd6 , +\blk00000003/blk0000100a/sig00001dd6 , \blk00000003/blk0000100a/sig00001dd6 , \blk00000003/blk0000100a/sig00001dd6 , +\blk00000003/blk0000100a/sig00001dd6 , \blk00000003/blk0000100a/sig00001dd6 , \blk00000003/blk0000100a/sig00001dd6 , +\blk00000003/blk0000100a/sig00001dd6 , \blk00000003/blk0000100a/sig00001dd6 , \blk00000003/blk0000100a/sig00001dd6 , +\blk00000003/blk0000100a/sig00001dd6 , \blk00000003/blk0000100a/sig00001dd6 , \blk00000003/blk0000100a/sig00001dd6 , +\blk00000003/blk0000100a/sig00001dd6 , \blk00000003/blk0000100a/sig00001dd6 , \blk00000003/blk0000100a/sig00001dd6 , +\blk00000003/blk0000100a/sig00001dd6 , \blk00000003/blk0000100a/sig00001dd6 , \blk00000003/blk0000100a/sig00001dd6 , +\blk00000003/blk0000100a/sig00001dd6 , \blk00000003/blk0000100a/sig00001dd6 , \blk00000003/blk0000100a/sig00001dd6 , +\blk00000003/blk0000100a/sig00001dd6 , \blk00000003/blk0000100a/sig00001dd6 , \blk00000003/blk0000100a/sig00001dd6 , +\blk00000003/blk0000100a/sig00001dd6 , \blk00000003/blk0000100a/sig00001dd6 }), + .DIPA({\blk00000003/sig00001447 , \blk00000003/sig00001450 , \blk00000003/sig00001459 , \blk00000003/sig00001462 }), + .DIPB({\blk00000003/blk0000100a/sig00001dd6 , \blk00000003/blk0000100a/sig00001dd6 , \blk00000003/blk0000100a/sig00001dd6 , +\blk00000003/blk0000100a/sig00001dd6 }), + .WEA({\blk00000003/sig000005e3 , \blk00000003/sig000005e3 , \blk00000003/sig000005e3 , \blk00000003/sig000005e3 }), + .WEB({\blk00000003/blk0000100a/sig00001dd6 , \blk00000003/blk0000100a/sig00001dd6 , \blk00000003/blk0000100a/sig00001dd6 , +\blk00000003/blk0000100a/sig00001dd6 }), + .DOA({\NLW_blk00000003/blk0000100a/blk0000100d_DOA<31>_UNCONNECTED , \NLW_blk00000003/blk0000100a/blk0000100d_DOA<30>_UNCONNECTED , +\NLW_blk00000003/blk0000100a/blk0000100d_DOA<29>_UNCONNECTED , \NLW_blk00000003/blk0000100a/blk0000100d_DOA<28>_UNCONNECTED , +\NLW_blk00000003/blk0000100a/blk0000100d_DOA<27>_UNCONNECTED , \NLW_blk00000003/blk0000100a/blk0000100d_DOA<26>_UNCONNECTED , +\NLW_blk00000003/blk0000100a/blk0000100d_DOA<25>_UNCONNECTED , \NLW_blk00000003/blk0000100a/blk0000100d_DOA<24>_UNCONNECTED , +\NLW_blk00000003/blk0000100a/blk0000100d_DOA<23>_UNCONNECTED , \NLW_blk00000003/blk0000100a/blk0000100d_DOA<22>_UNCONNECTED , +\NLW_blk00000003/blk0000100a/blk0000100d_DOA<21>_UNCONNECTED , \NLW_blk00000003/blk0000100a/blk0000100d_DOA<20>_UNCONNECTED , +\NLW_blk00000003/blk0000100a/blk0000100d_DOA<19>_UNCONNECTED , \NLW_blk00000003/blk0000100a/blk0000100d_DOA<18>_UNCONNECTED , +\NLW_blk00000003/blk0000100a/blk0000100d_DOA<17>_UNCONNECTED , \NLW_blk00000003/blk0000100a/blk0000100d_DOA<16>_UNCONNECTED , +\NLW_blk00000003/blk0000100a/blk0000100d_DOA<15>_UNCONNECTED , \NLW_blk00000003/blk0000100a/blk0000100d_DOA<14>_UNCONNECTED , +\NLW_blk00000003/blk0000100a/blk0000100d_DOA<13>_UNCONNECTED , \NLW_blk00000003/blk0000100a/blk0000100d_DOA<12>_UNCONNECTED , +\NLW_blk00000003/blk0000100a/blk0000100d_DOA<11>_UNCONNECTED , \NLW_blk00000003/blk0000100a/blk0000100d_DOA<10>_UNCONNECTED , +\NLW_blk00000003/blk0000100a/blk0000100d_DOA<9>_UNCONNECTED , \NLW_blk00000003/blk0000100a/blk0000100d_DOA<8>_UNCONNECTED , +\NLW_blk00000003/blk0000100a/blk0000100d_DOA<7>_UNCONNECTED , \NLW_blk00000003/blk0000100a/blk0000100d_DOA<6>_UNCONNECTED , +\NLW_blk00000003/blk0000100a/blk0000100d_DOA<5>_UNCONNECTED , \NLW_blk00000003/blk0000100a/blk0000100d_DOA<4>_UNCONNECTED , +\NLW_blk00000003/blk0000100a/blk0000100d_DOA<3>_UNCONNECTED , \NLW_blk00000003/blk0000100a/blk0000100d_DOA<2>_UNCONNECTED , +\NLW_blk00000003/blk0000100a/blk0000100d_DOA<1>_UNCONNECTED , \NLW_blk00000003/blk0000100a/blk0000100d_DOA<0>_UNCONNECTED }), + .DOB({\blk00000003/sig000000b6 , \blk00000003/sig000000b7 , \blk00000003/sig000000b8 , \blk00000003/sig000000b9 , \blk00000003/sig000000ba , +\blk00000003/sig000000bb , \blk00000003/sig000000bc , \blk00000003/sig000000bd , \blk00000003/sig000000bf , \blk00000003/sig000000c0 , +\blk00000003/sig000000c1 , \blk00000003/sig000000c2 , \blk00000003/sig000000c3 , \blk00000003/sig000000c4 , \blk00000003/sig000000c5 , +\blk00000003/sig000000c6 , \blk00000003/sig000000c8 , \blk00000003/sig000000c9 , \blk00000003/sig000000ca , \blk00000003/sig000000cb , +\blk00000003/sig000000cc , \blk00000003/sig000000cd , \blk00000003/sig000000ce , \blk00000003/sig000000cf , \blk00000003/sig000000d1 , +\blk00000003/sig000000d2 , \blk00000003/sig000000d3 , \blk00000003/sig000000d4 , \blk00000003/sig000000d5 , \blk00000003/sig000000d6 , +\blk00000003/sig000000d7 , \blk00000003/sig000000d8 }), + .DOPA({\NLW_blk00000003/blk0000100a/blk0000100d_DOPA<3>_UNCONNECTED , \NLW_blk00000003/blk0000100a/blk0000100d_DOPA<2>_UNCONNECTED , +\NLW_blk00000003/blk0000100a/blk0000100d_DOPA<1>_UNCONNECTED , \NLW_blk00000003/blk0000100a/blk0000100d_DOPA<0>_UNCONNECTED }), + .DOPB({\blk00000003/sig000000b5 , \blk00000003/sig000000be , \blk00000003/sig000000c7 , \blk00000003/sig000000d0 }) + ); + GND \blk00000003/blk0000100a/blk0000100c ( + .G(\blk00000003/blk0000100a/sig00001dd6 ) + ); + VCC \blk00000003/blk0000100a/blk0000100b ( + .P(\blk00000003/blk0000100a/sig00001dd5 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000100f/blk0000101d ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/blk0000100f/sig00001dec ), + .Q(\blk00000003/sig0000146c ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000100f/blk0000101c ( + .A0(\blk00000003/blk0000100f/sig00001de6 ), + .A1(\blk00000003/blk0000100f/sig00001de5 ), + .A2(\blk00000003/blk0000100f/sig00001de5 ), + .A3(\blk00000003/blk0000100f/sig00001de5 ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(\blk00000003/sig00000096 ), + .Q(\blk00000003/blk0000100f/sig00001dec ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000100f/blk0000101b ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/blk0000100f/sig00001deb ), + .Q(\blk00000003/sig0000146d ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000100f/blk0000101a ( + .A0(\blk00000003/blk0000100f/sig00001de6 ), + .A1(\blk00000003/blk0000100f/sig00001de5 ), + .A2(\blk00000003/blk0000100f/sig00001de5 ), + .A3(\blk00000003/blk0000100f/sig00001de5 ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(\blk00000003/sig00000097 ), + .Q(\blk00000003/blk0000100f/sig00001deb ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000100f/blk00001019 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/blk0000100f/sig00001dea ), + .Q(\blk00000003/sig0000146b ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000100f/blk00001018 ( + .A0(\blk00000003/blk0000100f/sig00001de6 ), + .A1(\blk00000003/blk0000100f/sig00001de5 ), + .A2(\blk00000003/blk0000100f/sig00001de5 ), + .A3(\blk00000003/blk0000100f/sig00001de5 ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(\blk00000003/sig00000095 ), + .Q(\blk00000003/blk0000100f/sig00001dea ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000100f/blk00001017 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/blk0000100f/sig00001de9 ), + .Q(\blk00000003/sig0000146f ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000100f/blk00001016 ( + .A0(\blk00000003/blk0000100f/sig00001de6 ), + .A1(\blk00000003/blk0000100f/sig00001de5 ), + .A2(\blk00000003/blk0000100f/sig00001de5 ), + .A3(\blk00000003/blk0000100f/sig00001de5 ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(\blk00000003/sig00000099 ), + .Q(\blk00000003/blk0000100f/sig00001de9 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000100f/blk00001015 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/blk0000100f/sig00001de8 ), + .Q(\blk00000003/sig00001470 ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000100f/blk00001014 ( + .A0(\blk00000003/blk0000100f/sig00001de6 ), + .A1(\blk00000003/blk0000100f/sig00001de5 ), + .A2(\blk00000003/blk0000100f/sig00001de5 ), + .A3(\blk00000003/blk0000100f/sig00001de5 ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(\blk00000003/sig0000009a ), + .Q(\blk00000003/blk0000100f/sig00001de8 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk0000100f/blk00001013 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/blk0000100f/sig00001de7 ), + .Q(\blk00000003/sig0000146e ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk0000100f/blk00001012 ( + .A0(\blk00000003/blk0000100f/sig00001de6 ), + .A1(\blk00000003/blk0000100f/sig00001de5 ), + .A2(\blk00000003/blk0000100f/sig00001de5 ), + .A3(\blk00000003/blk0000100f/sig00001de5 ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(\blk00000003/sig00000098 ), + .Q(\blk00000003/blk0000100f/sig00001de7 ) + ); + VCC \blk00000003/blk0000100f/blk00001011 ( + .P(\blk00000003/blk0000100f/sig00001de6 ) + ); + GND \blk00000003/blk0000100f/blk00001010 ( + .G(\blk00000003/blk0000100f/sig00001de5 ) + ); + FDE #( + .INIT ( 1'b0 )) + \blk00000003/blk00001024/blk00001027 ( + .C(clk), + .CE(\blk00000003/sig00000065 ), + .D(\blk00000003/blk00001024/sig00001df2 ), + .Q(\blk00000003/sig00001471 ) + ); + SRL16E #( + .INIT ( 16'h0000 )) + \blk00000003/blk00001024/blk00001026 ( + .A0(\blk00000003/blk00001024/sig00001df1 ), + .A1(\blk00000003/blk00001024/sig00001df1 ), + .A2(\blk00000003/blk00001024/sig00001df1 ), + .A3(\blk00000003/blk00001024/sig00001df1 ), + .CE(\blk00000003/sig00000065 ), + .CLK(clk), + .D(\blk00000003/sig000000a5 ), + .Q(\blk00000003/blk00001024/sig00001df2 ) + ); + GND \blk00000003/blk00001024/blk00001025 ( + .G(\blk00000003/blk00001024/sig00001df1 ) + ); + +// synthesis translate_on + +endmodule + +// synthesis translate_off + +`ifndef GLBL +`define GLBL + +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (weak1, weak0) GSR = GSR_int; + assign (weak1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + +endmodule + +`endif + +// synthesis translate_on diff --git a/verilog/crc32.v b/verilog/crc32.v new file mode 100644 index 0000000..b78e2c5 --- /dev/null +++ b/verilog/crc32.v @@ -0,0 +1,69 @@ +//----------------------------------------------------------------------------- +// Copyright (C) 2009 OutputLogic.com +// This source file may be used and distributed without restriction +// provided that this copyright statement is not removed from the file +// and that any derivative work contains the original copyright notice +// and the associated disclaimer. +// +// THIS SOURCE FILE IS PROVIDED "AS IS" AND WITHOUT ANY EXPRESS +// OR IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED +// WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE. +//----------------------------------------------------------------------------- +// CRC module for data[7:0] , crc[31:0]=1+x^1+x^2+x^4+x^5+x^7+x^8+x^10+x^11+x^12+x^16+x^22+x^23+x^26+x^32; +//----------------------------------------------------------------------------- +module crc32( + input [7:0] data_in, + input crc_en, + output [31:0] crc_out, + input rst, + input clk); + +reg [31:0] lfsr_q,lfsr_c; + +assign crc_out = lfsr_q; + +always @(*) begin + lfsr_c[0] = lfsr_q[24] ^ lfsr_q[30] ^ data_in[0] ^ data_in[6]; + lfsr_c[1] = lfsr_q[24] ^ lfsr_q[25] ^ lfsr_q[30] ^ lfsr_q[31] ^ data_in[0] ^ data_in[1] ^ data_in[6] ^ data_in[7]; + lfsr_c[2] = lfsr_q[24] ^ lfsr_q[25] ^ lfsr_q[26] ^ lfsr_q[30] ^ lfsr_q[31] ^ data_in[0] ^ data_in[1] ^ data_in[2] ^ data_in[6] ^ data_in[7]; + lfsr_c[3] = lfsr_q[25] ^ lfsr_q[26] ^ lfsr_q[27] ^ lfsr_q[31] ^ data_in[1] ^ data_in[2] ^ data_in[3] ^ data_in[7]; + lfsr_c[4] = lfsr_q[24] ^ lfsr_q[26] ^ lfsr_q[27] ^ lfsr_q[28] ^ lfsr_q[30] ^ data_in[0] ^ data_in[2] ^ data_in[3] ^ data_in[4] ^ data_in[6]; + lfsr_c[5] = lfsr_q[24] ^ lfsr_q[25] ^ lfsr_q[27] ^ lfsr_q[28] ^ lfsr_q[29] ^ lfsr_q[30] ^ lfsr_q[31] ^ data_in[0] ^ data_in[1] ^ data_in[3] ^ data_in[4] ^ data_in[5] ^ data_in[6] ^ data_in[7]; + lfsr_c[6] = lfsr_q[25] ^ lfsr_q[26] ^ lfsr_q[28] ^ lfsr_q[29] ^ lfsr_q[30] ^ lfsr_q[31] ^ data_in[1] ^ data_in[2] ^ data_in[4] ^ data_in[5] ^ data_in[6] ^ data_in[7]; + lfsr_c[7] = lfsr_q[24] ^ lfsr_q[26] ^ lfsr_q[27] ^ lfsr_q[29] ^ lfsr_q[31] ^ data_in[0] ^ data_in[2] ^ data_in[3] ^ data_in[5] ^ data_in[7]; + lfsr_c[8] = lfsr_q[0] ^ lfsr_q[24] ^ lfsr_q[25] ^ lfsr_q[27] ^ lfsr_q[28] ^ data_in[0] ^ data_in[1] ^ data_in[3] ^ data_in[4]; + lfsr_c[9] = lfsr_q[1] ^ lfsr_q[25] ^ lfsr_q[26] ^ lfsr_q[28] ^ lfsr_q[29] ^ data_in[1] ^ data_in[2] ^ data_in[4] ^ data_in[5]; + lfsr_c[10] = lfsr_q[2] ^ lfsr_q[24] ^ lfsr_q[26] ^ lfsr_q[27] ^ lfsr_q[29] ^ data_in[0] ^ data_in[2] ^ data_in[3] ^ data_in[5]; + lfsr_c[11] = lfsr_q[3] ^ lfsr_q[24] ^ lfsr_q[25] ^ lfsr_q[27] ^ lfsr_q[28] ^ data_in[0] ^ data_in[1] ^ data_in[3] ^ data_in[4]; + lfsr_c[12] = lfsr_q[4] ^ lfsr_q[24] ^ lfsr_q[25] ^ lfsr_q[26] ^ lfsr_q[28] ^ lfsr_q[29] ^ lfsr_q[30] ^ data_in[0] ^ data_in[1] ^ data_in[2] ^ data_in[4] ^ data_in[5] ^ data_in[6]; + lfsr_c[13] = lfsr_q[5] ^ lfsr_q[25] ^ lfsr_q[26] ^ lfsr_q[27] ^ lfsr_q[29] ^ lfsr_q[30] ^ lfsr_q[31] ^ data_in[1] ^ data_in[2] ^ data_in[3] ^ data_in[5] ^ data_in[6] ^ data_in[7]; + lfsr_c[14] = lfsr_q[6] ^ lfsr_q[26] ^ lfsr_q[27] ^ lfsr_q[28] ^ lfsr_q[30] ^ lfsr_q[31] ^ data_in[2] ^ data_in[3] ^ data_in[4] ^ data_in[6] ^ data_in[7]; + lfsr_c[15] = lfsr_q[7] ^ lfsr_q[27] ^ lfsr_q[28] ^ lfsr_q[29] ^ lfsr_q[31] ^ data_in[3] ^ data_in[4] ^ data_in[5] ^ data_in[7]; + lfsr_c[16] = lfsr_q[8] ^ lfsr_q[24] ^ lfsr_q[28] ^ lfsr_q[29] ^ data_in[0] ^ data_in[4] ^ data_in[5]; + lfsr_c[17] = lfsr_q[9] ^ lfsr_q[25] ^ lfsr_q[29] ^ lfsr_q[30] ^ data_in[1] ^ data_in[5] ^ data_in[6]; + lfsr_c[18] = lfsr_q[10] ^ lfsr_q[26] ^ lfsr_q[30] ^ lfsr_q[31] ^ data_in[2] ^ data_in[6] ^ data_in[7]; + lfsr_c[19] = lfsr_q[11] ^ lfsr_q[27] ^ lfsr_q[31] ^ data_in[3] ^ data_in[7]; + lfsr_c[20] = lfsr_q[12] ^ lfsr_q[28] ^ data_in[4]; + lfsr_c[21] = lfsr_q[13] ^ lfsr_q[29] ^ data_in[5]; + lfsr_c[22] = lfsr_q[14] ^ lfsr_q[24] ^ data_in[0]; + lfsr_c[23] = lfsr_q[15] ^ lfsr_q[24] ^ lfsr_q[25] ^ lfsr_q[30] ^ data_in[0] ^ data_in[1] ^ data_in[6]; + lfsr_c[24] = lfsr_q[16] ^ lfsr_q[25] ^ lfsr_q[26] ^ lfsr_q[31] ^ data_in[1] ^ data_in[2] ^ data_in[7]; + lfsr_c[25] = lfsr_q[17] ^ lfsr_q[26] ^ lfsr_q[27] ^ data_in[2] ^ data_in[3]; + lfsr_c[26] = lfsr_q[18] ^ lfsr_q[24] ^ lfsr_q[27] ^ lfsr_q[28] ^ lfsr_q[30] ^ data_in[0] ^ data_in[3] ^ data_in[4] ^ data_in[6]; + lfsr_c[27] = lfsr_q[19] ^ lfsr_q[25] ^ lfsr_q[28] ^ lfsr_q[29] ^ lfsr_q[31] ^ data_in[1] ^ data_in[4] ^ data_in[5] ^ data_in[7]; + lfsr_c[28] = lfsr_q[20] ^ lfsr_q[26] ^ lfsr_q[29] ^ lfsr_q[30] ^ data_in[2] ^ data_in[5] ^ data_in[6]; + lfsr_c[29] = lfsr_q[21] ^ lfsr_q[27] ^ lfsr_q[30] ^ lfsr_q[31] ^ data_in[3] ^ data_in[6] ^ data_in[7]; + lfsr_c[30] = lfsr_q[22] ^ lfsr_q[28] ^ lfsr_q[31] ^ data_in[4] ^ data_in[7]; + lfsr_c[31] = lfsr_q[23] ^ lfsr_q[29] ^ data_in[5]; + +end // always + +always @(posedge clk, posedge rst) begin + if(rst) begin + lfsr_q <= {32{1'b1}}; + end + else begin + lfsr_q <= crc_en ? lfsr_c : lfsr_q; + end +end // always +endmodule // crc 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+0000000000000000000000 +0000000000000000000000 +0000000000000000000000 +0000000000000000000000 +0000000000000000000000 +0000000000000000000000 +0000000000000000000000 +0000000000000000000000 +0000000000000000000000 +0000000000000000000000 +0000000000000000000000 +0000000000000000000000 +0000000000000000000000 +0000000000000000000000 +0000000000000000000000 +0000000000000000000000 +0000000000000000000000 +0000000000000000000000 +0000000000000000000000 +0000000000000000000000 +0000000000000000000000 +0000000000000000000000 +0000000000000000000000 +0000000000000000000000 +0000000000000000000000 diff --git a/verilog/deinter_lut.v b/verilog/deinter_lut.v new file mode 100644 index 0000000..7810a36 --- /dev/null +++ b/verilog/deinter_lut.v @@ -0,0 +1,24 @@ +module deinter_lut +#( + parameter DWIDTH = 22, + parameter AWIDTH = 11 +) +( + input clka, + input [AWIDTH-1:0] addra, + output reg [DWIDTH-1:0] douta +); + +reg [DWIDTH-1:0] ram [0:(1<>1; + addrb <= 0; + + lut_key <= 0; + lut_valid <= 0; + ht_delayed <= 0; + + ram_delay <= 0; + state <= S_INPUT; + end else if (enable) begin + ht_delayed <= ht; + if (ht != ht_delayed) begin + addra <= num_data_carrier>>1; + end + + case(state) + S_INPUT: begin + if (input_strobe) begin + if (addra == half_data_carrier-1) begin + lut_key <= {6'b0, ht, rate[3:0]}; + ram_delay <= 0; + lut_valid <= 0; + state <= S_GET_BASE; + end else begin + if (addra == num_data_carrier-1) begin + addra <= 0; + end else begin + addra <= addra + 1; + end + end + end + end + + S_GET_BASE: begin + if (ram_delay) begin + lut_key <= lut_out; + ram_delay <= 0; + state <= S_OUTPUT; + end else begin + ram_delay <= 1; + end + end + + S_OUTPUT: begin + if (ram_delay) begin + addra <= lut_addra; + addrb <= lut_addrb; + if (lut_done) begin + lut_key <= 0; + lut_valid <= 0; + state <= S_INPUT; + end else begin + lut_valid <= 1; + lut_key <= lut_key + 1; + end + end else begin + ram_delay <= 1; + lut_valid <= 1; + lut_key <= lut_key + 1; + end + end + default: begin + end + endcase + end +end + +endmodule diff --git a/verilog/delayT.v b/verilog/delayT.v new file mode 100644 index 0000000..a21fb01 --- /dev/null +++ b/verilog/delayT.v @@ -0,0 +1,32 @@ +module delayT +#( + parameter DATA_WIDTH = 32, + parameter DELAY = 1 +) +( + input clock, + input reset, + + input [DATA_WIDTH-1:0] data_in, + output [DATA_WIDTH-1:0] data_out +); + +reg [DATA_WIDTH-1:0] ram[DELAY-1:0]; +integer i; + +assign data_out = ram[DELAY-1]; + +always @(posedge clock) begin + if (reset) begin + for (i = 0; i < DELAY; i = i+1) begin + ram[i] <= 0; + end + end else begin + ram[0] <= data_in; + for (i = 1; i < DELAY; i= i+1) begin + ram[i] <= ram[i-1]; + end + end +end + +endmodule diff --git a/verilog/delay_sample.v b/verilog/delay_sample.v new file mode 100644 index 0000000..6bea872 --- /dev/null +++ b/verilog/delay_sample.v @@ -0,0 +1,61 @@ +/* +* Delay using RAM +* Only support 2^n delay +*/ +module delay_sample +#( + parameter DATA_WIDTH = 16, + parameter DELAY_SHIFT = 4 +) +( + input clock, + input enable, + input reset, + + input [(DATA_WIDTH-1):0] data_in, + input input_strobe, + + output [(DATA_WIDTH-1):0] data_out, + output reg output_strobe +); + +localparam DELAY_SIZE = 1< QAM_64_DIV_0 && + abs_cons_i < QAM_64_DIV_2? 1: 0; + bits[3] <= ~cons_q_delayed[15]; + bits[4] <= abs_cons_q < QAM_64_DIV_1? 1: 0; + bits[5] <= abs_cons_q > QAM_64_DIV_0 && + abs_cons_q < QAM_64_DIV_2? 1: 0; + end + endcase + end +end + +endmodule diff --git a/verilog/descramble.v b/verilog/descramble.v new file mode 100644 index 0000000..b6be804 --- /dev/null +++ b/verilog/descramble.v @@ -0,0 +1,49 @@ +module descramble +( + input clock, + input enable, + input reset, + + input in_bit, + input input_strobe, + + output reg out_bit, + output reg output_strobe +); + +reg [6:0] state; +reg [4:0] bit_count; + +reg [5:0] init_bits; +reg inited; + +wire feedback = state[6] ^ state[3]; + +always @(posedge clock) begin + if (reset) begin + bit_count <= 0; + state <= 0; + init_bits <= 0; + inited <= 0; + out_bit <= 0; + output_strobe <= 0; + end else if (enable & input_strobe) begin + if (!inited) begin + state[6-bit_count] <= in_bit; + if (bit_count == 6) begin + bit_count <= 0; + inited <= 1; + end else begin + bit_count <= bit_count + 1; + end + end else begin + out_bit <= feedback ^ in_bit; + output_strobe <= 1; + state <= {state[5:0], feedback}; + end + end else begin + output_strobe <= 0; + end +end + +endmodule diff --git a/verilog/divider.v b/verilog/divider.v new file mode 100644 index 0000000..29d6151 --- /dev/null +++ b/verilog/divider.v @@ -0,0 +1,31 @@ +/* +* DELAY: 36 cycles +*/ +module divider ( + input clock, + input reset, + input enable, + + input signed [31:0] dividend, + input signed [23:0] divisor, + input input_strobe, + + output signed [31:0] quotient, + output output_strobe +); + +div_gen_v3_0 div_inst ( + .clk(clock), + .dividend(dividend), + .divisor(divisor), + .quotient(quotient) +); + +delayT #(.DATA_WIDTH(1), .DELAY(36)) out_inst ( + .clock(clock), + .reset(reset), + .data_in(input_strobe), + .data_out(output_strobe) +); + +endmodule diff --git a/verilog/dot11.v b/verilog/dot11.v new file mode 100644 index 0000000..4ff1599 --- /dev/null +++ b/verilog/dot11.v @@ -0,0 +1,819 @@ +`include "common_defs.v" + +module dot11 ( + input clock, + input enable, + input reset, + + input set_stb, + input [7:0] set_addr, + input [31:0] set_data, + + // INPUT: I/Q sample + input [31:0] sample_in, + input sample_in_strobe, + + // OUTPUT: bytes and FCS status + output [7:0] byte_out, + output byte_out_strobe, + + output reg fcs_out_strobe, + output reg fcs_ok, + + ///////////////////////////////////////////////////////// + // DEBUG PORTS + ///////////////////////////////////////////////////////// + + // decode status + output reg [3:0] state, + output reg [3:0] status_code, + output state_changed, + + // power trigger + output power_trigger, + + // sync short + output short_preamble_detected, + output [31:0] phase_offset, + + // sync long + output [31:0] sync_long_metric, + output sync_long_metric_stb, + output long_preamble_detected, + output [31:0] sync_long_out, + output sync_long_out_strobe, + output [2:0] sync_long_state, + + // equalizer + output [31:0] equalizer_out, + output equalizer_out_strobe, + output [2:0] equalizer_state, + + // signal info + output reg signal_out_strobe, + output [3:0] data_rate, + output signal_reserved, + output [11:0] length, + output parity, + output parity_ok, + output [5:0] signal_tail, + + // ht signal info + output reg ht_sig_strobe, + output [6:0] mcs, + output cbw, + output [15:0] ht_len, + output smoothing, + output not_sounding, + output aggregation, + output [1:0] stbc, + output fec_coding, + output ht_sgi, + output [1:0] num_ext_spatial, + output reg ht_sig_crc_ok, + + // OFDM stuff + output [5:0] demod_out, + output demod_out_strobe, + + output [1:0] deinterleave_out, + output deinterleave_out_strobe, + + output conv_decoder_out, + output conv_decoder_out_stb, + + output descramble_out, + output descramble_out_strobe +); + +`include "common_params.v" + + +//////////////////////////////////////////////////////////////////////////////// +// Shared rotation LUT for sync_long and equalizer +//////////////////////////////////////////////////////////////////////////////// +wire [`ROTATE_LUT_LEN_SHIFT-1:0] sync_long_rot_addr; +wire [31:0] sync_long_rot_data; + +wire [`ROTATE_LUT_LEN_SHIFT-1:0] eq_rot_addr; +wire [31:0] eq_rot_data; + +rot_lut rot_lut_inst ( + .clka(clock), + .addra(sync_long_rot_addr), + .douta(sync_long_rot_data), + + .clkb(clock), + .addrb(eq_rot_addr), + .doutb(eq_rot_data) +); +//////////////////////////////////////////////////////////////////////////////// + + + +//////////////////////////////////////////////////////////////////////////////// +// Shared phase module for sync_short and equalizer +//////////////////////////////////////////////////////////////////////////////// +wire [31:0] sync_short_phase_in_i; +wire [31:0] sync_short_phase_in_q; +wire sync_short_phase_in_stb; +wire [31:0] sync_short_phase_out; +wire sync_short_phase_out_stb; + +wire [31:0] eq_phase_in_i; +wire [31:0] eq_phase_in_q; +wire eq_phase_in_stb; +wire [31:0] eq_phase_out; +wire eq_phase_out_stb; + +wire[31:0] phase_in_i = state == S_SYNC_SHORT? + sync_short_phase_in_i: eq_phase_in_i; +wire[31:0] phase_in_q = state == S_SYNC_SHORT? + sync_short_phase_in_q: eq_phase_in_q; +wire phase_in_stb = state == S_SYNC_SHORT? + sync_short_phase_in_stb: eq_phase_in_stb; + +wire [31:0] phase_out; +wire phase_out_stb; + +assign sync_short_phase_out = phase_out; +assign sync_short_phase_out_stb = phase_out_stb; +assign eq_phase_out = phase_out; +assign eq_phase_out_stb = phase_out_stb; + +phase phase_inst ( + .clock(clock), + .reset(reset), + .enable(enable), + + .in_i(phase_in_i), + .in_q(phase_in_q), + .input_strobe(phase_in_stb), + + .phase(phase_out), + .output_strobe(phase_out_stb) +); +//////////////////////////////////////////////////////////////////////////////// + + +reg sync_short_reset; +reg sync_long_reset; +wire sync_short_enable = state == S_SYNC_SHORT; +reg sync_long_enable; + +reg equalizer_reset; +reg equalizer_enable; + +reg ht_next; + +wire eq_out_stb_delayed; +wire [15:0] eq_out_i = equalizer_out[31:16]; +wire [15:0] eq_out_q = equalizer_out[15:0]; +wire [15:0] eq_out_i_delayed; +wire [15:0] eq_out_q_delayed; +reg [15:0] abs_eq_i; +reg [15:0] abs_eq_q; +reg [3:0] rot_eq_count; +reg [3:0] normal_eq_count; + +// OFDM control +reg ofdm_reset; +reg ofdm_enable; +reg ofdm_in_stb; +reg [15:0] ofdm_in_i; +reg [15:0] ofdm_in_q; + +reg do_descramble; +reg [7:0] rate; +reg [31:0] num_bits_to_decode; +reg short_gi; + +reg [3:0] old_state; +assign state_changed = state != old_state; + +// SIGNAL information +reg [23:0] signal_bits; +reg [31:0] byte_count; + +assign data_rate = signal_bits[3:0]; +assign signal_reserved = signal_bits[4]; +assign length = signal_bits[16:5]; +assign parity = signal_bits[17]; +assign signal_tail = signal_bits[23:18]; +assign parity_ok = ~^signal_bits[17:0]; + + +// HT-SIG information +reg [23:0] ht_sig1; +reg [23:0] ht_sig2; + +assign mcs = ht_sig1[6:0]; +assign cbw = ht_sig1[7]; +assign ht_len = ht_sig1[23:8]; + +assign smoothing = ht_sig2[0]; +assign not_sounding = ht_sig2[1]; +assign aggregation = ht_sig2[3]; +assign stbc = ht_sig2[5:4]; +assign fec_coding = ht_sig2[6]; +assign ht_sgi = ht_sig2[7]; +assign num_ext_spatial = ht_sig2[9:8]; + + +wire ht_rsvd = ht_sig2[2]; +wire [7:0] crc = ht_sig2[17:10]; +wire [5:0] ht_sig_tail = ht_sig2[23:18]; + + +reg crc_in_stb; +reg crc_in; +reg [7:0] crc_count; +reg crc_reset; +wire [7:0] crc_out; + +reg [31:0] pkt_length; + +reg [31:0] sample_count; + +wire fcs_enable = state == S_DECODE_DATA && byte_out_strobe; +wire fcs_reset = state_changed && state == S_DECODE_DATA; +wire [7:0] byte_reversed; +wire [31:0] pkt_fcs; + +assign byte_reversed[0] = byte_out[7]; +assign byte_reversed[1] = byte_out[6]; +assign byte_reversed[2] = byte_out[5]; +assign byte_reversed[3] = byte_out[4]; +assign byte_reversed[4] = byte_out[3]; +assign byte_reversed[5] = byte_out[2]; +assign byte_reversed[6] = byte_out[1]; +assign byte_reversed[7] = byte_out[0]; + +reg [15:0] sync_long_out_count; + +integer i; + +power_trigger power_trigger_inst ( + .clock(clock), + .enable(enable), + .reset(reset), + + .sample_in(sample_in), + .sample_in_strobe(sample_in_strobe), + + .set_stb(set_stb), + .set_addr(set_addr), + .set_data(set_data), + + .trigger(power_trigger) +); + +sync_short sync_short_inst ( + .clock(clock), + .reset(reset | sync_short_reset), + .enable(enable & sync_short_enable), + + .set_stb(set_stb), + .set_addr(set_addr), + .set_data(set_data), + + .sample_in(sample_in), + .sample_in_strobe(sample_in_strobe), + + .phase_in_i(sync_short_phase_in_i), + .phase_in_q(sync_short_phase_in_q), + .phase_in_stb(sync_short_phase_in_stb), + + .phase_out(sync_short_phase_out), + .phase_out_stb(sync_short_phase_out_stb), + + .short_preamble_detected(short_preamble_detected), + .phase_offset(phase_offset) +); + +sync_long sync_long_inst ( + .clock(clock), + .reset(reset | sync_long_reset), + .enable(enable & sync_long_enable), + + .set_stb(set_stb), + .set_addr(set_addr), + .set_data(set_data), + + .sample_in(sample_in), + .sample_in_strobe(sample_in_strobe), + .phase_offset(phase_offset), + .short_gi(short_gi), + + .rot_addr(sync_long_rot_addr), + .rot_data(sync_long_rot_data), + + .metric(sync_long_metric), + .metric_stb(sync_long_metric_stb), + .long_preamble_detected(long_preamble_detected), + .state(sync_long_state), + + .sample_out(sync_long_out), + .sample_out_strobe(sync_long_out_strobe) +); + +equalizer equalizer_inst ( + .clock(clock), + .reset(reset | equalizer_reset), + .enable(enable & equalizer_enable), + + .sample_in(sync_long_out), + .sample_in_strobe(sync_long_out_strobe), + .ht_next(ht_next), + + .phase_in_i(eq_phase_in_i), + .phase_in_q(eq_phase_in_q), + .phase_in_stb(eq_phase_in_stb), + + .phase_out(eq_phase_out), + .phase_out_stb(eq_phase_out_stb), + + .rot_addr(eq_rot_addr), + .rot_data(eq_rot_data), + + .sample_out(equalizer_out), + .sample_out_strobe(equalizer_out_strobe), + + .state(equalizer_state) +); + + +delayT #(.DATA_WIDTH(33), .DELAY(6)) eq_delay_inst ( + .clock(clock), + .reset(reset), + + .data_in({equalizer_out_strobe, equalizer_out}), + .data_out({eq_out_stb_delayed, eq_out_i_delayed, eq_out_q_delayed}) +); + + +ofdm_decoder ofdm_decoder_inst ( + .clock(clock), + .reset(reset|ofdm_reset), + .enable(enable & ofdm_enable), + + .sample_in({ofdm_in_i, ofdm_in_q}), + .sample_in_strobe(ofdm_in_stb), + + .do_descramble(do_descramble), + .num_bits_to_decode(num_bits_to_decode), + .rate(rate), + + .byte_out(byte_out), + .byte_out_strobe(byte_out_strobe), + + .demod_out(demod_out), + .demod_out_strobe(demod_out_strobe), + + .deinterleave_out(deinterleave_out), + .deinterleave_out_strobe(deinterleave_out_strobe), + + .conv_decoder_out(conv_decoder_out), + .conv_decoder_out_stb(conv_decoder_out_stb), + + .descramble_out(descramble_out), + .descramble_out_strobe(descramble_out_strobe) +); + +ht_sig_crc crc_inst ( + .clock(clock), + .enable(enable), + .reset(reset | crc_reset), + + .bit(crc_in), + .input_strobe(crc_in_stb), + .crc(crc_out) +); + +crc32 fcs_inst ( + .clk(clock), + .crc_en(enable & fcs_enable), + .rst(reset | fcs_reset), + .data_in(byte_reversed), + .crc_out(pkt_fcs) +); + + +always @(posedge clock) begin + if (reset) begin + status_code <= E_OK; + state <= S_WAIT_POWER_TRIGGER; + old_state <= 0; + + sync_short_reset <= 0; + + sync_long_reset <= 0; + sync_long_enable <= 0; + + byte_count <= 0; + + + rot_eq_count <= 0; + normal_eq_count <= 0; + abs_eq_i <= 0; + abs_eq_q <= 0; + + do_descramble <= 0; + num_bits_to_decode <= 0; + short_gi <= 0; + rate <= 0; + + equalizer_reset <= 0; + equalizer_enable <= 0; + ht_next <= 0; + + pkt_length <= 0; + + ofdm_reset <= 0; + ofdm_enable <= 0; + ofdm_in_stb <= 0; + ofdm_in_i <= 0; + ofdm_in_q <= 0; + + sample_count <= 0; + + sync_long_out_count <= 0; + + signal_bits <= 0; + signal_out_strobe <= 0; + + ht_sig1 <= 0; + ht_sig2 <= 0; + crc_in_stb <= 0; + crc_in <= 0; + crc_count <= 0; + crc_reset <= 0; + ht_sig_crc_ok <= 0; + ht_sig_strobe <= 0; + + fcs_out_strobe <= 0; + fcs_ok <= 0; + end else if (enable) begin + old_state <= state; + + case(state) + S_WAIT_POWER_TRIGGER: begin + sync_long_enable <= 0; + equalizer_enable <= 0; + ofdm_enable <= 0; + + if (power_trigger) begin + `ifdef DEBUG_PRINT + $display("Power triggered."); + `endif + sync_short_reset <= 1; + state <= S_SYNC_SHORT; + end + end + + S_SYNC_SHORT: begin + if (sync_short_reset) begin + sync_short_reset <= 0; + end + + if (~power_trigger) begin + // power level drops before finding STS + state <= S_WAIT_POWER_TRIGGER; + end + + if (short_preamble_detected) begin + `ifdef DEBUG_PRINT + $display("Short preamble detected"); + `endif + sync_long_reset <= 1; + sync_long_enable <= 1; + sample_count <= 0; + state <= S_SYNC_LONG; + end + + end + + S_SYNC_LONG: begin + if (sync_long_reset) begin + sync_long_reset <= 0; + end + + if (sample_in_strobe) begin + sample_count <= sample_count + 1; + end + if (sample_count > 320) begin + state <= S_WAIT_POWER_TRIGGER; + end + + if (~power_trigger) begin + state <= S_WAIT_POWER_TRIGGER; + end + + if (long_preamble_detected) begin + rate <= {1'b0, 3'b0, 4'b1011}; + do_descramble <= 0; + num_bits_to_decode <= 48; + + ofdm_reset <= 1; + ofdm_enable <= 1; + + equalizer_enable <= 1; + equalizer_reset <= 1; + + byte_count <= 0; + state <= S_DECODE_SIGNAL; + end + end + + S_DECODE_SIGNAL: begin + if (ofdm_reset) begin + ofdm_reset <= 0; + end + + if (equalizer_reset) begin + equalizer_reset <= 0; + end + + ofdm_in_stb <= equalizer_out_strobe; + ofdm_in_i <= eq_out_i; + ofdm_in_q <= eq_out_q; + + if (byte_out_strobe) begin + signal_bits <= {byte_out, signal_bits[23:8]}; + byte_count <= byte_count + 1; + end + + if (byte_count == 3) begin + byte_count <= 0; + `ifdef DEBUG_PRINT + $display("[SIGNAL] rate = %04b, ", data_rate, + "length = %012b (%d), ", length, length, + "parity = %b, ", parity, + "tail = %6b", signal_tail); + `endif + ofdm_reset <= 1; + state <= S_CHECK_SIGNAL; + end + end + + S_CHECK_SIGNAL: begin + if (ofdm_reset) begin + ofdm_reset <= 0; + end + + if (~parity_ok) begin + status_code <= E_PARITY_FAIL; + state <= S_SIGNAL_ERROR; + end else if (signal_reserved) begin + status_code <= E_WRONG_RSVD; + state <= S_SIGNAL_ERROR; + end else if (|signal_tail) begin + status_code <= E_WRONG_TAIL; + state <= S_SIGNAL_ERROR; + end else begin + signal_out_strobe <= 1; + status_code <= E_OK; + if (data_rate == 4'b1011) begin + abs_eq_i <= 0; + abs_eq_q <= 0; + rot_eq_count <= 0; + normal_eq_count <= 0; + state <= S_DETECT_HT; + end else begin + rate <= {1'b0, 3'b0, data_rate}; + num_bits_to_decode <= (length+3)<<4; + do_descramble <= 1; + ofdm_reset <= 1; + byte_count <= 0; + pkt_length <= length; + byte_count <= 0; + state <= S_DECODE_DATA; + end + end + end + + S_SIGNAL_ERROR: begin + state <= S_WAIT_POWER_TRIGGER; + end + + S_DETECT_HT: begin + signal_out_strobe <= 0; + + if (equalizer_out_strobe) begin + abs_eq_i <= eq_out_i[15]? ~eq_out_i+1: eq_out_i; + abs_eq_q <= eq_out_q[15]? ~eq_out_q+1: eq_out_q; + if (abs_eq_q > abs_eq_i) begin + rot_eq_count <= rot_eq_count + 1; + end else begin + normal_eq_count <= normal_eq_count + 1; + end + end + + if (rot_eq_count >= 4) begin + // HT-SIG detected + byte_count <= 0; + rate <= {1'b0, 3'b0, 4'b1011}; + num_bits_to_decode <= 96; + do_descramble <= 0; + ofdm_reset <= 1; + state <= S_HT_SIGNAL; + end else if (normal_eq_count > 4) begin + pkt_length <= length; + num_bits_to_decode <= (length+3)<<4; + do_descramble <= 1; + ofdm_reset <= 1; + byte_count <= 0; + state <= S_DECODE_DATA; + end + end + + S_HT_SIGNAL: begin + if (ofdm_reset) begin + ofdm_reset <= 0; + end + + ofdm_in_stb <= eq_out_stb_delayed; + // rotate clockwise by 90 degree + ofdm_in_i <= eq_out_q_delayed; + ofdm_in_q <= ~eq_out_i_delayed+1; + + if (byte_out_strobe) begin + if (byte_count < 3) begin + ht_sig1 <= {byte_out, ht_sig1[23:8]}; + end else begin + ht_sig2 <= {byte_out, ht_sig2[23:8]}; + end + byte_count <= byte_count + 1; + end + + if (byte_count == 6) begin + byte_count <= 0; + `ifdef DEBUG_PRINT + $display("[HT SIGNAL] mcs = %07b (%d), ", mcs, mcs, + "CBW: %d, ", cbw? 40: 20, + "length = %012b (%d), ", ht_len, ht_len, + "rsvd = %d, ", ht_rsvd, + "aggr = %d, ", aggregation, + "stbd = %02b, ", stbc, + "fec = %d, ", fec_coding, + "sgi = %d, ", ht_sgi, + "num_ext = %d, ", num_ext_spatial, + "crc = %08b, ", crc, + "tail = %06b", ht_sig_tail); + `endif + crc_count <= 0; + crc_reset <= 1; + crc_in_stb <= 0; + ht_sig_crc_ok <= 0; + state <= S_CHECK_HT_SIG_CRC; + end + end + + S_CHECK_HT_SIG_CRC: begin + crc_reset <= 0; + crc_count <= crc_count + 1; + + if (crc_count < 24) begin + crc_in_stb <= 1; + crc_in <= ht_sig1[crc_count]; + end else if (crc_count < 34) begin + crc_in_stb <= 1; + crc_in <= ht_sig2[crc_count-24]; + end else if (crc_count == 34) begin + crc_in_stb <= 0; + end else if (crc_count == 35) begin + if (crc_out ^ crc) begin + status_code <= E_WRONG_CRC; + ht_sig_strobe <= 1; + state <= S_HT_SIG_ERROR; + end else begin + `ifdef DEBUG_PRINT + $display("[HT SIGNAL] CRC OK"); + `endif + ht_sig_crc_ok <= 1; + ht_sig_strobe <= 1; + ofdm_reset <= 1; + state <= S_CHECK_HT_SIG; + end + end + end + + S_CHECK_HT_SIG: begin + ofdm_reset <= 0; + ht_sig_strobe <= 0; + if (mcs > 7) begin + status_code <= E_UNSUPPORTED_MCS; + state <= S_HT_SIG_ERROR; + end else if (cbw) begin + status_code <= E_UNSUPPORTED_CBW; + state <= S_HT_SIG_ERROR; + end else if (ht_rsvd == 0) begin + status_code <= E_HT_WRONG_RSVD; + state <= S_HT_SIG_ERROR; + end else if (stbc != 0) begin + status_code <= E_UNSUPPORTED_STBC; + state <= S_HT_SIG_ERROR; + end else if (fec_coding) begin + status_code <= E_UNSUPPORTED_FEC; + state <= S_HT_SIG_ERROR; + end else if (short_gi) begin + status_code <= E_UNSUPPORTED_SGI; + state <= S_HT_SIG_ERROR; + end else if (num_ext_spatial != 0) begin + status_code <= E_UNSUPPORTED_SPATIAL; + state <= S_HT_SIG_ERROR; + end else if (ht_sig_tail != 0) begin + status_code <= E_HT_WRONG_TAIL; + state <= S_HT_SIG_ERROR; + end else begin + sync_long_out_count <= 0; + state <= S_HT_STS; + end + end + + S_HT_SIG_ERROR: begin + ht_sig_strobe <= 0; + state <= S_WAIT_POWER_TRIGGER; + end + + S_HT_STS: begin + if (sync_long_out_strobe) begin + sync_long_out_count <= sync_long_out_count + 1; + end + if (sync_long_out_count == 64) begin + sync_long_out_count <= 0; + ht_next <= 1; + state <= S_HT_LTS; + end + end + + S_HT_LTS: begin + short_gi <= ht_sgi; + if (sync_long_out_strobe) begin + sync_long_out_count <= sync_long_out_count + 1; + end + if (sync_long_out_count == 64) begin + ht_next <= 0; + num_bits_to_decode <= (ht_len+3)<<4; + rate <= {1'b1, mcs}; + do_descramble <= 1; + ofdm_reset <= 1; + byte_count <= 0; + pkt_length <= ht_len; + state <= S_DECODE_DATA; + end + end + + S_DECODE_DATA: begin + signal_out_strobe <= 0; + + if (ofdm_reset) begin + ofdm_reset <= 0; + end + + ofdm_in_stb <= eq_out_stb_delayed; + ofdm_in_i <= eq_out_i_delayed; + ofdm_in_q <= eq_out_q_delayed; + + if (byte_out_strobe) begin + `ifdef DEBUG_PRINT + $display("[BYTE] [%4d/%4d] %02x", byte_count, pkt_length, + byte_out); + `endif + byte_count <= byte_count + 1; + end + + if (byte_count >= pkt_length) begin + fcs_out_strobe <= 1; + if (pkt_fcs == EXPECTED_FCS) begin + fcs_ok <= 1; + status_code <= E_OK; + end else begin + fcs_ok <= 0; + status_code <= E_WRONG_FCS; + end + state <= S_DECODE_DONE; + end + end + + S_DECODE_DONE: begin + `ifdef DEBUG_PRINT + $display("===== PACKET DECODE DONE ====="); + if (status_code == E_OK) begin + $display("FCS CORRECT"); + end else begin + $display("FCS WRONG"); + end + `endif + fcs_out_strobe <= 0; + state <= S_WAIT_POWER_TRIGGER; + end + + default: begin + state <= S_WAIT_POWER_TRIGGER; + end + endcase + end +end + +endmodule diff --git a/verilog/dot11_modules.list b/verilog/dot11_modules.list new file mode 100644 index 0000000..9af3aa9 --- /dev/null +++ b/verilog/dot11_modules.list @@ -0,0 +1,44 @@ +-y ./Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/ +-y ./Xilinx/12.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/ + +dot11.v + +sync_short.v +power_trigger.v +moving_avg.v +delay_sample.v +complex_to_mag.v +divider.v +complex_to_mag_sq.v + +sync_long.v +stage_mult.v + +ofdm_decoder.v +phase.v +rotate.v +equalizer.v +complex_mult.v +calc_mean.v +deinterleave.v +demodulate.v +descramble.v +bits_to_bytes.v + +delayT.v +ht_sig_crc.v +rate_to_idx.v +crc32.v + +./usrp2/setting_reg.v +./usrp2/ram_2port.v + +./coregen/xfft_v7_1.v +./coregen/complex_multiplier.v +./coregen/viterbi_v7_0.v +./coregen/div_gen_v3_0.v +./coregen/deinter_lut.v +./coregen/atan_lut.v +./coregen/rot_lut.v + +./Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/MULT18X18S.v diff --git a/verilog/dot11_tb.v b/verilog/dot11_tb.v new file mode 100644 index 0000000..f2add43 --- /dev/null +++ b/verilog/dot11_tb.v @@ -0,0 +1,288 @@ +`timescale 1ns/1ps + +module dot11_tb; +`include "common_params.v" + +reg clock; +reg reset; +reg enable; + +reg[31:0] sample_in; +reg sample_in_strobe; +reg [15:0] clk_count; + +wire [31:0] sync_short_metric; +wire short_preamble_detected; +wire power_trigger; + +wire [31:0] sync_long_out; +wire sync_long_out_strobe; +wire [31:0] sync_long_metric; +wire sync_long_metric_stb; +wire long_preamble_detected; + + +wire [31:0] equalizer_out; +wire equalizer_out_strobe; + +wire [5:0] demod_out; +wire demod_out_strobe; + +wire [1:0] deinterleave_out; +wire deinterleave_out_strobe; + +wire conv_decoder_out; +wire conv_decoder_out_stb; + +wire descramble_out; +wire descramble_out_strobe; + +wire [3:0] data_rate; +wire signal_reserved; +wire [11:0] length; +wire parity; +wire [5:0] signal_tail; +wire signal_out_strobe; +reg signal_done; + +wire [3:0] dot11_state; + +wire [7:0] byte_out; +wire byte_out_strobe; + + +reg set_stb; +reg [7:0] set_addr; +reg [31:0] set_data; + +localparam RAM_SIZE = 1<<25; + +reg [31:0] ram [0:RAM_SIZE-1]; +reg [31:0] addr; + +integer bb_sample_fd; +integer power_trigger_fd; +integer short_preamble_detected_fd; + +integer long_preamble_detected_fd; +integer sync_long_metric_fd; +integer sync_long_out_fd; + +integer equalizer_out_fd; + +integer demod_out_fd; +integer deinterleave_out_fd; +integer conv_out_fd; +integer descramble_out_fd; + +integer signal_fd; + +integer byte_out_fd; + +`ifndef SAMPLE_FILE +`define SAMPLE_FILE "../testing_inputs/conducted/dot11a_6mbps_qos_data_e4_90_7e_15_2a_16_e8_de_27_90_6e_42.txt" +`endif + +`ifndef NUM_SAMPLE +`define NUM_SAMPLE 1000 +`endif + +initial begin + $dumpfile("dot11_decoder.vcd"); + $dumpvars; + + $display("Reading memory from..."); + $display(`SAMPLE_FILE); + $readmemh(`SAMPLE_FILE, ram); + $display("Done."); + + clock = 0; + reset = 1; + enable = 0; + signal_done <= 0; + + # 20 reset = 0; + enable = 1; + + set_stb = 1; + + # 20 + // do not skip sample + set_addr = SR_SKIP_SAMPLE; + set_data = 0; + + # 20 + // jam filter len + set_addr = SR_HEADER_LEN; + set_data = 32; + + # 20 set_stb = 0; + + bb_sample_fd = $fopen("./sim_out/sample_in.txt", "w"); + power_trigger_fd = $fopen("./sim_out/power_trigger.txt", "w"); + short_preamble_detected_fd = $fopen("./sim_out/short_preamble_detected.txt", "w"); + + sync_long_metric_fd = $fopen("./sim_out/sync_long_metric.txt", "w"); + long_preamble_detected_fd = $fopen("./sim_out/sync_long_frame_detected.txt", "w"); + sync_long_out_fd = $fopen("./sim_out/sync_long_out.txt", "w"); + + equalizer_out_fd = $fopen("./sim_out/equalizer_out.txt", "w"); + + demod_out_fd = $fopen("./sim_out/demod_out.txt", "w"); + deinterleave_out_fd = $fopen("./sim_out/deinterleave_out.txt", "w"); + conv_out_fd = $fopen("./sim_out/conv_out.txt", "w"); + descramble_out_fd = $fopen("./sim_out/descramble_out.txt", "w"); + + signal_fd = $fopen("./sim_out/signal_out.txt", "w"); + + byte_out_fd = $fopen("./sim_out/byte_out.txt", "w"); +end + + +always begin + #5 clock = !clock; +end + +always @(posedge clock) begin + if (reset) begin + sample_in <= 0; + clk_count <= 0; + sample_in_strobe <= 0; + addr <= 0; + end else if (enable) begin + if (clk_count == 4) begin + sample_in_strobe <= 1; + sample_in <= ram[addr]; + addr <= addr + 1; + clk_count <= 0; + end else begin + sample_in_strobe <= 0; + clk_count <= clk_count + 1; + end + + if (signal_out_strobe) begin + end + + if (sample_in_strobe && power_trigger) begin + $fwrite(bb_sample_fd, "%d %d %d\n", $time/2, $signed(sample_in[31:16]), $signed(sample_in[15:0])); + $fwrite(power_trigger_fd, "%d %d\n", $time/2, power_trigger); + $fwrite(short_preamble_detected_fd, "%d %d\n", $time/2, short_preamble_detected); + + $fwrite(long_preamble_detected_fd, "%d %d\n", $time/2, long_preamble_detected); + + $fflush(bb_sample_fd); + $fflush(power_trigger_fd); + $fflush(short_preamble_detected_fd); + + $fflush(sync_long_metric_fd); + $fflush(long_preamble_detected_fd); + + + if ((addr % 100) == 0) begin + $display("%d / %d", addr, RAM_SIZE); + end + + if (addr == `NUM_SAMPLE) begin + $finish; + end + end + + if (sync_long_metric_stb) begin + $fwrite(sync_long_metric_fd, "%d %d\n", $time/2, sync_long_metric); + end + + if (sync_long_out_strobe) begin + $fwrite(sync_long_out_fd, "%d %d\n", $signed(sync_long_out[31:16]), $signed(sync_long_out[15:0])); + $fflush(sync_long_out_fd); + end + + if (equalizer_out_strobe) begin + $fwrite(equalizer_out_fd, "%d %d\n", $signed(equalizer_out[31:16]), $signed(equalizer_out[15:0])); + $fflush(equalizer_out_fd); + end + + if (signal_out_strobe) begin + signal_done <= 1; + $fwrite(signal_fd, "%04b %b %012b %b %06b", data_rate, signal_reserved, length, parity, signal_tail); + $fflush(signal_fd); + end + + if (dot11_state == S_DECODE_DATA && demod_out_strobe) begin + $fwrite(demod_out_fd, "%06b\n", demod_out); + $fflush(demod_out_fd); + end + + if (dot11_state == S_DECODE_DATA && deinterleave_out_strobe) begin + $fwrite(deinterleave_out_fd, "%b%b\n", deinterleave_out[0], deinterleave_out[1]); + $fflush(deinterleave_out_fd); + end + + if (dot11_state == S_DECODE_DATA && conv_decoder_out_stb) begin + $fwrite(conv_out_fd, "%b\n", conv_decoder_out); + $fflush(conv_out_fd); + end + + if (dot11_state == S_DECODE_DATA && descramble_out_strobe) begin + $fwrite(descramble_out_fd, "%b\n", descramble_out); + $fflush(descramble_out_fd); + end + + if (dot11_state == S_DECODE_DATA && byte_out_strobe) begin + $fwrite(byte_out_fd, "%02x\n", byte_out); + $fflush(byte_out_fd); + end + + end +end + +dot11 dot11_inst ( + .clock(clock), + .reset(reset), + .enable(enable), + + .set_addr(set_addr), + .set_stb(set_stb), + .set_data(set_data), + + .sample_in(sample_in), + .sample_in_strobe(sample_in_strobe), + + .state(dot11_state), + + .power_trigger(power_trigger), + .short_preamble_detected(short_preamble_detected), + + .sync_long_metric(sync_long_metric), + .sync_long_metric_stb(sync_long_metric_stb), + .long_preamble_detected(long_preamble_detected), + + .sync_long_out(sync_long_out), + .sync_long_out_strobe(sync_long_out_strobe), + + .equalizer_out(equalizer_out), + .equalizer_out_strobe(equalizer_out_strobe), + + .demod_out(demod_out), + .demod_out_strobe(demod_out_strobe), + + .deinterleave_out(deinterleave_out), + .deinterleave_out_strobe(deinterleave_out_strobe), + + .conv_decoder_out(conv_decoder_out), + .conv_decoder_out_stb(conv_decoder_out_stb), + + .descramble_out(descramble_out), + .descramble_out_strobe(descramble_out_strobe), + + .byte_out(byte_out), + .byte_out_strobe(byte_out_strobe), + + .data_rate(data_rate), + .signal_reserved(signal_reserved), + .length(length), + .parity(parity), + .signal_tail(signal_tail), + .signal_out_strobe(signal_out_strobe) +); + +endmodule diff --git a/verilog/equalizer.v b/verilog/equalizer.v new file mode 100644 index 0000000..2197f29 --- /dev/null +++ b/verilog/equalizer.v @@ -0,0 +1,540 @@ +`include "common_defs.v" + +module equalizer +( + input clock, + input enable, + input reset, + + input [31:0] sample_in, + input sample_in_strobe, + input ht_next, + + output [31:0] phase_in_i, + output [31:0] phase_in_q, + output reg phase_in_stb, + input [31:0] phase_out, + input phase_out_stb, + + output [`ROTATE_LUT_LEN_SHIFT-1:0] rot_addr, + input [31:0] rot_data, + + output reg [31:0] sample_out, + output reg sample_out_strobe, + + output reg [2:0] state +); + + +// mask[0] is DC, mask[1:26] -> 1,..., 26 +// mask[38:63] -> -26,..., -1 +localparam SUBCARRIER_MASK = + 64'b1111111111111111111111111100000000000111111111111111111111111110; + +localparam HT_SUBCARRIER_MASK = + 64'b1111111111111111111111111111000000011111111111111111111111111110; + +// -7, -21, 21, 7 +localparam PILOT_MASK = + 64'b0000001000000000000010000000000000000000001000000000000010000000; + +localparam DATA_SUBCARRIER_MASK = + SUBCARRIER_MASK ^ PILOT_MASK; + +localparam HT_DATA_SUBCARRIER_MASK = + HT_SUBCARRIER_MASK ^ PILOT_MASK; + + +// -1,..,-26, 26,..,1 +localparam LTS_REF = + 64'b0000101001100000010100110000000000000000010101100111110101001100; + +localparam HT_LTS_REF = + 64'b0000101001100000010100110000000000011000010101100111110101001100; + + +localparam POLARITY = + 128'b1111111000111011000101001011111010101000010110111100111001010110011000001101101011101000110010001000000100100110100111101110000; + +// 21, 7, -7, -21 +localparam HT_POLARITY = 4'b1000; + + +localparam IN_BUF_LEN_SHIFT = 6; + +reg ht; +reg [5:0] num_data_carrier; + + +// bit masks +reg [63:0] lts_ref; +reg [63:0] ht_lts_ref; +reg [63:0] subcarrier_mask; +reg [63:0] data_subcarrier_mask; +reg [63:0] pilot_mask; + +reg [127:0] polarity; +reg [3:0] ht_polarity; +reg [3:0] current_polarity; +reg [3:0] pilot_count; + +reg signed [15:0] input_i; +reg signed [15:0] input_q; + +reg current_sign; + +wire signed [15:0] new_lts_i; +wire signed [15:0] new_lts_q; +wire new_lts_stb; + +reg calc_mean_strobe; + +reg [5:0] lts_waddr; +reg [6:0] lts_raddr; // one bit wider to detect overflow +reg [15:0] lts_i_in; +reg [15:0] lts_q_in; +reg lts_in_stb; +wire signed [15:0] lts_i_out; +wire signed [15:0] lts_q_out; +wire signed [15:0] lts_q_out_neg = ~lts_q_out + 1; + +reg [5:0] in_waddr; +reg [6:0] in_raddr; +wire [15:0] buf_i_out; +wire [15:0] buf_q_out; + +reg pilot_in_stb; +wire signed [31:0] pilot_i; +wire signed [31:0] pilot_q; + +reg signed [31:0] pilot_sum_i; +reg signed [31:0] pilot_sum_q; + +assign phase_in_i = pilot_sum_i; +assign phase_in_q = pilot_sum_q; + +reg signed [31:0] pilot_phase; + +reg rot_in_stb; +wire signed [15:0] rot_i; +wire signed [15:0] rot_q; + +wire [31:0] mag_sq; +wire [31:0] prod_i; +wire [31:0] prod_q; +wire [31:0] prod_i_scaled = prod_i<<`CONS_SCALE_SHIFT; +wire [31:0] prod_q_scaled = prod_q<<`CONS_SCALE_SHIFT; +wire prod_stb; + +reg [15:0] num_output; +wire [31:0] norm_i; +wire [31:0] norm_q; + +wire norm_out_stb; + +reg prod_in_strobe; +wire prod_out_strobe; + +ram_2port #(.DWIDTH(32), .AWIDTH(6)) lts_inst ( + .clka(clock), + .ena(1), + .wea(lts_in_stb), + .addra(lts_waddr), + .dia({lts_i_in, lts_q_in}), + .doa(), + .clkb(clock), + .enb(1), + .web(1'b0), + .addrb(lts_raddr[5:0]), + .dib(32'hFFFF), + .dob({lts_i_out, lts_q_out}) +); + +calc_mean lts_i_inst ( + .clock(clock), + .enable(enable), + .reset(reset), + + .a(lts_i_out), + .b(input_i), + .sign(current_sign), + .input_strobe(calc_mean_strobe), + + .c(new_lts_i), + .output_strobe(new_lts_stb) +); + +calc_mean lts_q_inst ( + .clock(clock), + .enable(enable), + .reset(reset), + + .a(lts_q_out), + .b(input_q), + .sign(current_sign), + .input_strobe(calc_mean_strobe), + + .c(new_lts_q) +); + +ram_2port #(.DWIDTH(32), .AWIDTH(6)) in_buf_inst ( + .clka(clock), + .ena(1), + .wea(sample_in_strobe), + .addra(in_waddr), + .dia(sample_in), + .doa(), + .clkb(clock), + .enb(1), + .web(1'b0), + .addrb(in_raddr[5:0]), + .dib(32'hFFFF), + .dob({buf_i_out, buf_q_out}) +); + +complex_mult pilot_inst ( + .clock(clock), + .enable(enable), + .reset(reset), + .a_i(input_i), + .a_q(input_q), + .b_i(lts_i_out), + .b_q(lts_q_out), + .input_strobe(pilot_in_stb), + .p_i(pilot_i), + .p_q(pilot_q), + .output_strobe(pilot_out_stb) +); + +rotate rotate_inst ( + .clock(clock), + .enable(enable), + .reset(reset), + + .in_i(buf_i_out), + .in_q(buf_q_out), + .phase(pilot_phase), + .input_strobe(rot_in_stb), + + .rot_addr(rot_addr), + .rot_data(rot_data), + + .out_i(rot_i), + .out_q(rot_q), + .output_strobe(rot_out_stb) +); + +complex_mult input_lts_prod_inst ( + .clock(clock), + .enable(enable), + .reset(reset), + .a_i(rot_i), + .a_q(rot_q), + .b_i(lts_i_out), + .b_q(lts_q_out_neg), + .input_strobe(rot_out_stb), + .p_i(prod_i), + .p_q(prod_q), + .output_strobe(prod_out_strobe) +); + +complex_mult lts_lts_prod_inst ( + .clock(clock), + .enable(enable), + .reset(reset), + .a_i(lts_i_out), + .a_q(lts_q_out), + .b_i(lts_i_out), + .b_q(lts_q_out_neg), + .input_strobe(rot_out_stb), + .p_i(mag_sq) +); + +divider norm_i_inst ( + .clock(clock), + .enable(enable), + .reset(reset), + + .dividend(prod_i_scaled), + .divisor(mag_sq[23:0]), + .input_strobe(prod_out_strobe), + + .quotient(norm_i), + .output_strobe(norm_out_stb) +); + +divider norm_q_inst ( + .clock(clock), + .enable(enable), + .reset(reset), + + .dividend(prod_q_scaled), + .divisor(mag_sq[23:0]), + .input_strobe(prod_out_strobe), + + .quotient(norm_q) +); + +localparam S_FIRST_LTS = 0; +localparam S_SECOND_LTS = 1; +localparam S_GET_POLARITY = 2; +localparam S_CALC_FREQ_OFFSET = 3; +localparam S_ADJUST_FREQ_OFFSET = 4; +localparam S_HT_LTS = 5; + +always @(posedge clock) begin + if (reset) begin + sample_out_strobe <= 0; + lts_raddr <= 0; + lts_waddr <= 0; + sample_out <= 0; + + lts_in_stb <= 0; + lts_i_in <= 0; + lts_q_in <= 0; + + ht <= 0; + num_data_carrier <= 48; + + subcarrier_mask <= SUBCARRIER_MASK; + data_subcarrier_mask <= DATA_SUBCARRIER_MASK; + pilot_mask <= PILOT_MASK; + lts_ref <= LTS_REF; + ht_lts_ref <= HT_LTS_REF; + polarity <= POLARITY; + + ht_polarity <= HT_POLARITY; + + current_polarity <= 0; + pilot_count <= 0; + + in_waddr <= 0; + in_raddr <= 0; + + phase_in_stb <= 0; + pilot_sum_i <= 0; + pilot_sum_q <= 0; + pilot_phase <= 0; + pilot_in_stb <= 0; + + prod_in_strobe <= 0; + + rot_in_stb <= 0; + + current_sign <= 0; + input_i <= 0; + input_q <= 0; + calc_mean_strobe <= 0; + + num_output <= 0; + + state <= S_FIRST_LTS; + end else if (enable) begin + case(state) + S_FIRST_LTS: begin + // store first LTS as is + lts_in_stb <= sample_in_strobe; + {lts_i_in, lts_q_in} <= sample_in; + + if (lts_in_stb) begin + if (lts_waddr == 63) begin + lts_waddr <= 0; + lts_raddr <= 0; + state <= S_SECOND_LTS; + end else begin + lts_waddr <= lts_waddr + 1; + end + end + end + + S_SECOND_LTS: begin + // calculate and store the mean of the two LTS + if (sample_in_strobe) begin + calc_mean_strobe <= sample_in_strobe; + {input_i, input_q} <= sample_in; + current_sign <= lts_ref[0]; + lts_ref <= {lts_ref[0], lts_ref[63:1]}; + lts_raddr <= lts_raddr + 1; + end else begin + calc_mean_strobe <= 0; + end + + lts_in_stb <= new_lts_stb; + {lts_i_in, lts_q_in} <= {new_lts_i, new_lts_q}; + + if (lts_in_stb) begin + if (lts_waddr == 63) begin + lts_waddr <= 0; + state <= S_GET_POLARITY; + end else begin + lts_waddr <= lts_waddr + 1; + end + end + end + + S_GET_POLARITY: begin + // obtain the polarity of pilot sub-carriers for next OFDM symbol + if (ht) begin + current_polarity <= { + ht_polarity[1]^polarity[0], // -7 + ht_polarity[0]^polarity[0], // -21 + ht_polarity[3]^polarity[0], // 21 + ht_polarity[2]^polarity[0] // 7 + }; + ht_polarity <= {ht_polarity[0], ht_polarity[3:1]}; + end else begin + current_polarity <= { + polarity[0], // -7 + polarity[0], // -21 + ~polarity[0], // 21 + polarity[0] // 7 + }; + end + polarity <= {polarity[0], polarity[127:1]}; + + pilot_sum_i <= 0; + pilot_sum_q <= 0; + pilot_count <= 0; + in_waddr <= 0; + in_raddr <= 0; + input_i <= 0; + input_q <= 0; + lts_raddr <= 0; + state <= S_CALC_FREQ_OFFSET; + end + + S_CALC_FREQ_OFFSET: begin + if (~ht & ht_next) begin + ht <= 1; + num_data_carrier <= 52; + lts_waddr <= 0; + lts_ref <= HT_LTS_REF; + subcarrier_mask <= HT_SUBCARRIER_MASK; + data_subcarrier_mask <= HT_DATA_SUBCARRIER_MASK; + pilot_mask <= PILOT_MASK; + // reverse this extra shift + polarity <= {polarity[126:0], polarity[127]}; + state <= S_HT_LTS; + end + + // calculate residue freq offset using pilot sub carriers + if (sample_in_strobe) begin + in_waddr <= in_waddr + 1; + lts_raddr <= lts_raddr + 1; + + pilot_mask <= {pilot_mask[0], pilot_mask[63:1]}; + if (pilot_mask[0]) begin + pilot_count <= pilot_count + 1; + current_polarity <= {current_polarity[0], + current_polarity[3:1]}; + // obtain the conjugate of current pilot sub carrier + if (current_polarity[0] == 0) begin + input_i <= sample_in[31:16]; + input_q <= ~sample_in[15:0] + 1; + end else begin + input_i <= ~sample_in[31:16] + 1; + input_q <= sample_in[15:0]; + end + pilot_in_stb <= 1; + end else begin + pilot_in_stb <= 0; + end + end else begin + pilot_in_stb <= 0; + end + + if (pilot_out_stb) begin + pilot_sum_i <= pilot_sum_i + pilot_i; + pilot_sum_q <= pilot_sum_q + pilot_q; + if (pilot_count == 4) begin + phase_in_stb <= 1; + end else begin + phase_in_stb <= 0; + end + end else begin + phase_in_stb <= 0; + end + + if (phase_out_stb) begin + `ifdef DEBUG_PRINT + $display("[PILOT OFFSET] %d", phase_out); + `endif + pilot_phase <= phase_out; + in_raddr <= 0; + // compensate for RAM read delay + lts_raddr <= 1; + rot_in_stb <= 0; + num_output <= 0; + state <= S_ADJUST_FREQ_OFFSET; + end + end + + S_ADJUST_FREQ_OFFSET: begin + // first rotate, then normalize by avg LTS + if (in_raddr < 64) begin + in_raddr <= in_raddr + 1; + rot_in_stb <= 1; + end else begin + rot_in_stb <= 0; + end + + if (rot_out_stb) begin + lts_raddr <= lts_raddr + 1; + end + + if (norm_out_stb) begin + data_subcarrier_mask <= {data_subcarrier_mask[0], + data_subcarrier_mask[63:1]}; + if (data_subcarrier_mask[0]) begin + sample_out_strobe <= 1; + sample_out <= {norm_i[31], norm_i[14:0], + norm_q[31], norm_q[14:0]}; + num_output <= num_output + 1; + end else begin + sample_out_strobe <= 0; + end + end else begin + sample_out_strobe <= 0; + end + + if (num_output == num_data_carrier) begin + state <= S_GET_POLARITY; + end + end + + S_HT_LTS: begin + if (sample_in_strobe) begin + lts_in_stb <= 1; + ht_lts_ref <= {ht_lts_ref[0], ht_lts_ref[63:1]}; + if (ht_lts_ref[0] == 0) begin + {lts_i_in, lts_q_in} <= sample_in; + end else begin + lts_i_in <= ~sample_in[31:16]+1; + lts_q_in <= ~sample_in[15:0]+1; + end + end else begin + lts_in_stb <= 0; + end + + if (lts_in_stb) begin + if (lts_waddr == 63) begin + lts_waddr <= 0; + lts_raddr <= 0; + state <= S_GET_POLARITY; + end else begin + lts_waddr <= lts_waddr + 1; + end + end + + end + + default: begin + state <= S_FIRST_LTS; + end + endcase + end else begin + sample_out_strobe <= 0; + end +end + +endmodule diff --git a/verilog/ht_sig_crc.v b/verilog/ht_sig_crc.v new file mode 100644 index 0000000..7f75b2d --- /dev/null +++ b/verilog/ht_sig_crc.v @@ -0,0 +1,36 @@ +module ht_sig_crc +( + input clock, + input enable, + input reset, + + input bit, + input input_strobe, + + output [7:0] crc +); + +reg [7:0] C; +genvar i; + +generate +for (i = 0; i < 8; i=i+1) begin: reverse + assign crc[i] = ~C[7-i]; +end +endgenerate + + +always @(posedge clock) begin + if (reset) begin + C <= 8'hff; + end else if (enable) begin + if (input_strobe) begin + C[0] <= bit ^ C[7]; + C[1] <= bit ^ C[7] ^ C[0]; + C[2] <= bit ^ C[7] ^ C[1]; + C[7:3] <= C[6:2]; + end + end +end + +endmodule diff --git a/verilog/moving_avg.v b/verilog/moving_avg.v new file mode 100644 index 0000000..4b611b0 --- /dev/null +++ b/verilog/moving_avg.v @@ -0,0 +1,79 @@ +module moving_avg +#( + parameter DATA_WIDTH = 32, + parameter WINDOW_SHIFT = 4, + parameter SIGNED = 0 +) +( + input clock, + input enable, + input reset, + + input signed [DATA_WIDTH-1:0] data_in, + input input_strobe, + + output reg signed [DATA_WIDTH-1:0] data_out, + output reg output_strobe +); + +localparam WINDOW_SIZE = 1<= num_bits_to_decode) begin + flush <= 1; + end + end + if (!flush) begin + conv_in_stb <= deinterleave_out_strobe; + conv_in0 <= deinterleave_out[0]? 3'b111: 3'b011; + conv_in1 <= deinterleave_out[1]? 3'b111: 3'b011; + conv_erase <= erase; + end else begin + conv_in_stb <= 1; + conv_in0 <= 3'b011; + conv_in1 <= 3'b011; + conv_erase <= 0; + end + + if (deinter_out_count > 0) begin + if (~do_descramble) begin + bit_in <= conv_decoder_out; + bit_in_stb <= conv_decoder_out_stb; + end else begin + bit_in <= descramble_out; + if (descramble_out_strobe) begin + if (skip_bit > 0 ) begin + skip_bit <= skip_bit - 1; + bit_in_stb <= 0; + end else begin + bit_in_stb <= 1; + end + end else begin + bit_in_stb <= 0; + end + end + end + end +end + +endmodule diff --git a/verilog/phase.v b/verilog/phase.v new file mode 100644 index 0000000..701718f --- /dev/null +++ b/verilog/phase.v @@ -0,0 +1,131 @@ +`include "common_defs.v" + +module phase +#( + parameter DATA_WIDTH = 32 +) +( + input clock, + input reset, + input enable, + + input signed [DATA_WIDTH-1:0] in_i, + input signed [DATA_WIDTH-1:0] in_q, + input input_strobe, + + // [-pi, pi) scaled up by 2048 + output reg signed [31:0] phase, + output output_strobe +); +`include "common_params.v" + +reg [DATA_WIDTH-1:0] in_i_delay; +reg [DATA_WIDTH-1:0] in_q_delay; +reg [DATA_WIDTH-1:0] abs_i; +reg [DATA_WIDTH-1:0] abs_q; +reg [DATA_WIDTH-1:0] max; +reg [DATA_WIDTH-1:0] min; + +wire div_in_stb; + +wire [31:0] quotient; +wire div_out_stb; + +wire [`ATAN_LUT_LEN_SHIFT-1:0] atan_addr; +wire [`ATAN_LUT_SCALE_SHIFT-1:0] atan_data; + +assign atan_addr = quotient[`ATAN_LUT_LEN_SHIFT-1:0]; +wire signed [`ATAN_LUT_SCALE_SHIFT:0] _phase = {1'b0, atan_data}; + +reg [2:0] quadrant; +wire [2:0] quadrant_delayed; + +// 1 cycle for abs +// 1 cycle for quadrant +delayT #(.DATA_WIDTH(1), .DELAY(2)) div_in_inst ( + .clock(clock), + .reset(reset), + + .data_in(input_strobe), + .data_out(div_in_stb) +); + +// 1 cycle for atan_lut +// 1 cycle for quadrant_delayed +delayT #(.DATA_WIDTH(1), .DELAY(2)) output_inst ( + .clock(clock), + .reset(reset), + + .data_in(div_out_stb), + .data_out(output_strobe) +); + + +divider div_inst ( + .clock(clock), + .enable(enable), + .reset(reset), + + .dividend(min), + .divisor({{(`ATAN_LUT_LEN_SHIFT-8){1'b0}}, max[31:`ATAN_LUT_LEN_SHIFT]}), + .input_strobe(div_in_stb), + + .quotient(quotient), + .output_strobe(div_out_stb) +); + +delayT #(.DATA_WIDTH(3), .DELAY(36)) quadrant_inst ( + .clock(clock), + .reset(reset), + + .data_in(quadrant), + .data_out(quadrant_delayed) +); + +atan_lut lut_inst ( + .clka(clock), + .addra(atan_addr), + .douta(atan_data) +); + + +always @(posedge clock) begin + if (reset) begin + max <= 0; + min <= 0; + abs_i <= 0; + abs_q <= 0; + in_i_delay <= 0; + in_q_delay <= 0; + end else if (enable) begin + // 1st cycle + abs_i <= in_i[DATA_WIDTH-1]? ~in_i+1: in_i; + abs_q <= in_q[DATA_WIDTH-1]? ~in_q+1: in_q; + in_i_delay <= in_i; + in_q_delay <= in_q; + + // 2nd cycle + if (abs_i >= abs_q) begin + quadrant <= {in_i_delay[DATA_WIDTH-1], in_q_delay[DATA_WIDTH-1], 1'b0}; + max <= abs_i; + min <= abs_q; + end else begin + quadrant <= {in_i_delay[DATA_WIDTH-1], in_q_delay[DATA_WIDTH-1], 1'b1}; + max <= abs_q; + min <= abs_i; + end + + case(quadrant_delayed) + 3'b000: phase <= _phase; // [0, PI/4] + 3'b001: phase <= PI_2 - _phase; // [PI/4, PI/2] + 3'b010: phase <= -_phase; // [-PI/4, 0] + 3'b011: phase <= _phase - PI_2; // [-PI/2, -Pi/4] + 3'b100: phase <= PI - _phase; // [3/4PI, PI] + 3'b101: phase <= PI_2 + _phase; // [PI/2, 3/4PI] + 3'b110: phase <= _phase - PI; // [-3/4PI, -PI] + 3'b111: phase <= -PI_2 - _phase; // [-PI/2, -3/4PI] + endcase + end +end + +endmodule diff --git a/verilog/power_trigger.v b/verilog/power_trigger.v new file mode 100644 index 0000000..8dc5ceb --- /dev/null +++ b/verilog/power_trigger.v @@ -0,0 +1,98 @@ +module power_trigger +( + input clock, + input enable, + input reset, + + input [31:0] sample_in, + input sample_in_strobe, + + input set_stb, + input [7:0] set_addr, + input [31:0] set_data, + + output reg trigger +); +`include "common_params.v" + +localparam S_SKIP = 0; +localparam S_IDLE = 1; +localparam S_PACKET = 2; +reg [1:0] state; + +wire [15:0] power_thres; +wire [15:0] window_size; +wire [31:0] num_sample_to_skip; +wire num_sample_changed; + + +reg [31:0] sample_count; + +wire [15:0] input_i = sample_in[31:16]; +reg [15:0] abs_i; + +// threshold to claim a power trigger. +setting_reg #(.my_addr(SR_POWER_THRES), .width(16), .at_reset(100)) sr_0 ( + .clk(clock), .rst(reset), .strobe(set_stb), .addr(set_addr), .in(set_data), + .out(power_thres), .changed()); + +// power trigger window +setting_reg #(.my_addr(SR_POWER_WINDOW), .width(16), .at_reset(80)) sr_1 ( + .clk(clock), .rst(reset), .strobe(set_stb), .addr(set_addr), .in(set_data), + .out(window_size), .changed()); + +// num samples to skip initially +setting_reg #(.my_addr(SR_SKIP_SAMPLE), .width(32), .at_reset(5000000)) sr_2 ( + .clk(clock), .rst(reset), .strobe(set_stb), .addr(set_addr), .in(set_data), + .out(num_sample_to_skip), .changed(num_sample_changed)); + + +always @(posedge clock) begin + if (reset) begin + sample_count <= 0; + trigger <= 0; + abs_i <= 0; + state <= S_SKIP; + end else if (enable & sample_in_strobe) begin + abs_i <= input_i[15]? ~input_i+1: input_i; + case(state) + S_SKIP: begin + if(sample_count > num_sample_to_skip) begin + state <= S_IDLE; + end else begin + sample_count <= sample_count + 1; + end + end + + S_IDLE: begin + if (num_sample_changed) begin + sample_count <= 0; + state <= S_SKIP; + end else if (abs_i > power_thres) begin + // trigger on any significant signal + trigger <= 1; + sample_count <= 0; + state <= S_PACKET; + end + end + + S_PACKET: begin + if (num_sample_changed) begin + sample_count <= 0; + state <= S_SKIP; + end else if (abs_i < power_thres) begin + // go back to idle for N consecutive low signals + if (sample_count > window_size) begin + trigger <= 0; + state <= S_IDLE; + end else begin + sample_count <= sample_count + 1; + end + end else begin + sample_count <= 0; + end + end + endcase + end +end +endmodule diff --git a/verilog/rand_gen.v b/verilog/rand_gen.v new file mode 100644 index 0000000..ee69e19 --- /dev/null +++ b/verilog/rand_gen.v @@ -0,0 +1,28 @@ +module rand_gen +( + input clock, + input enable, + input reset, + + output reg [7:0] rnd +); + +localparam LFSR_LEN = 128; + +reg [LFSR_LEN-1:0] random; +wire feedback = random[127] ^ random[125] ^ random[100] ^ random[98]; +reg [2:0] bit_idx; + +always @(posedge clock) begin + if (reset) begin + random <= {LFSR_LEN{4'b0101}}; + bit_idx <= 0; + rnd <= 0; + end else if (enable) begin + random <= {random[LFSR_LEN-2:0], feedback}; + rnd[bit_idx] <= feedback; + bit_idx <= bit_idx + 1; + end +end + +endmodule diff --git a/verilog/rand_gen_tb.v b/verilog/rand_gen_tb.v new file mode 100644 index 0000000..073abb6 --- /dev/null +++ b/verilog/rand_gen_tb.v @@ -0,0 +1,44 @@ +module rand_gen_tb; + +reg clock; +reg reset; +reg enable; + +wire [7:0] rnd; + +integer fd; + +rand_gen inst ( + .clock(clock), + .enable(enable), + .reset(reset), + + .rnd(rnd) +); + + +initial begin + clock = 0; + reset = 1; + enable = 0; + + fd = $fopen("./sim_out/rand_gen.txt", "w"); + + # 10 reset = 0; + enable = 1; + + # 10000000 $finish; +end + + +always begin + #1 clock <= ~clock; +end + +always @(posedge clock) begin + if (enable) begin + $fwrite(fd, "%d\n", rnd); + end +end + +endmodule diff --git a/verilog/rate_to_idx.v b/verilog/rate_to_idx.v new file mode 100644 index 0000000..7e3bb08 --- /dev/null +++ b/verilog/rate_to_idx.v @@ -0,0 +1,67 @@ +// translate rate to idx +// rate format +// MSB = 0 --> 802.11a rates, rate[3:0] is the rate bits +// MSB = 1 --> 802.11n MCS, rate[6:0] is the MCS +module rate_to_idx +( + input clock, + input enable, + input reset, + + input [7:0] rate, + input input_strobe, + + output reg [7:0] idx, + output reg output_strobe +); + +always @(posedge clock) begin + if (reset) begin + idx <= 0; + output_strobe <= 0; + end else if (enable & input_strobe) begin + case ({rate[7], rate[2:0]}) + 4'b0011: begin + // 6 mbps + idx <= 0; + end + 4'b0111: begin + // 9 mbps + idx <= 1; + end + 4'b0010: begin + // 12 mbps + idx <= 2; + end + 4'b0110: begin + // 18 mbps + idx <= 3; + end + 4'b0001: begin + // 24 mbps + idx <= 4; + end + 4'b0101: begin + // 36 mbps + idx <= 5; + end + 4'b0000: begin + // 48 mbps + idx <= 6; + end + 4'b0100: begin + // 54 mbps + idx <= 7; + end + default: begin + // mcs + idx <= {5'b0, rate[2:0]}; + end + endcase + output_strobe <= 1; + end else begin + output_strobe <= 0; + end +end + +endmodule diff --git a/verilog/rot_lut.coe b/verilog/rot_lut.coe new file mode 100644 index 0000000..ac1288e --- /dev/null +++ b/verilog/rot_lut.coe @@ -0,0 +1,514 @@ +memory_initialization_radix=2; +memory_initialization_vector= +00001000000000000000000000000000, +00001000000000000000000000000100, +00001000000000000000000000001000, +00001000000000000000000000001100, +00001000000000000000000000010000, +00001000000000000000000000010100, +00001000000000000000000000011000, +00001000000000000000000000011100, +00001000000000000000000000100000, +00001000000000000000000000100100, +00001000000000000000000000101000, +00001000000000000000000000101100, +00000111111111110000000000110000, +00000111111111110000000000110100, +00000111111111110000000000111000, +00000111111111110000000000111100, +00000111111111110000000001000000, +00000111111111110000000001000100, +00000111111111110000000001001000, +00000111111111110000000001001100, +00000111111111100000000001010000, +00000111111111100000000001010100, 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input clock, + input enable, + input reset, + + input [15:0] in_i, + input [15:0] in_q, + // [-PI, PI] + // scaled up by ATAN_LUT_SCALE_SHIFT + input signed [31:0] phase, + input input_strobe, + + output [`ROTATE_LUT_LEN_SHIFT-1:0] rot_addr, + input [31:0] rot_data, + + output signed [15:0] out_i, + output signed [15:0] out_q, + output output_strobe +); +`include "common_params.v" + +reg [31:0] phase_abs; + +reg [2:0] quadrant; +reg [2:0] quadrant_delayed; +wire [15:0] in_i_delayed; +wire [15:0] in_q_delayed; + +reg [31:0] actual_phase; + +wire [15:0] raw_rot_i; +wire [15:0] raw_rot_q; +reg [15:0] rot_i; +reg [15:0] rot_q; + +wire mult_in_stb; + +wire [31:0] p_i; +wire [31:0] p_q; + +assign out_i = p_i[`ROTATE_LUT_SCALE_SHIFT+15:`ROTATE_LUT_SCALE_SHIFT]; +assign out_q = p_q[`ROTATE_LUT_SCALE_SHIFT+15:`ROTATE_LUT_SCALE_SHIFT]; + +assign rot_addr = actual_phase[`ROTATE_LUT_LEN_SHIFT-1:0]; +assign raw_rot_i = rot_data[31:16]; +assign raw_rot_q = rot_data[15:0]; + + +delayT #(.DATA_WIDTH(32), .DELAY(4)) in_delay_inst ( + .clock(clock), + .reset(reset), + + .data_in({in_i, in_q}), + .data_out({in_i_delayed, in_q_delayed}) +); + +delayT #(.DATA_WIDTH(1), .DELAY(4)) mult_delay_inst ( + .clock(clock), + .reset(reset), + + .data_in(input_strobe), + .data_out(mult_in_stb) +); + + +complex_mult mult_inst ( + .clock(clock), + .enable(enable), + .reset(reset), + .a_i(in_i_delayed), + .a_q(in_q_delayed), + .b_i(rot_i), + .b_q(rot_q), + .input_strobe(mult_in_stb), + .p_i(p_i), + .p_q(p_q), + .output_strobe(output_strobe) +); + + +integer i; +always @(posedge clock) begin + if (reset) begin + actual_phase <= 0; + + rot_i <= 0; + rot_q <= 0; + phase_abs <= 0; + + end else if (enable) begin + `ifdef DEBUG_PRINT + if (phase > PI || phase < -PI) begin + $display("[WARN] phase overflow: %d\n", phase); + end + `endif + + // cycle 1 + phase_abs <= phase[31]? ~phase+1: phase; + + // cycle 2 + if (phase_abs <= PI_4) begin + quadrant <= {phase[31], 2'b00}; + actual_phase <= phase_abs; + end else if (phase_abs <= PI_2) begin + quadrant <= {phase[31], 2'b01}; + actual_phase <= PI_2 - phase_abs; + end else if (phase_abs <= PI_3_4) begin + quadrant <= {phase[31], 2'b10}; + actual_phase <= phase_abs - PI_2; + end else begin + quadrant <= {phase[31], 2'b11}; + actual_phase <= PI - phase_abs; + end + + // cycle 3 + // wait for raw_rot_i + quadrant_delayed <= quadrant; + + // cycle 4 + case(quadrant_delayed) + 3'b000: begin + rot_i <= raw_rot_i; + rot_q <= raw_rot_q; + end + 3'b001: begin + rot_i <= raw_rot_q; + rot_q <= raw_rot_i; + end + 3'b010: begin + rot_i <= ~raw_rot_q+1; + rot_q <= raw_rot_i; + end + 3'b011: begin + rot_i <= ~raw_rot_i+1; + rot_q <= raw_rot_q; + end + 3'b100: begin + rot_i <= raw_rot_i; + rot_q <= ~raw_rot_q+1; + end + 3'b101: begin + rot_i <= raw_rot_q; + rot_q <= ~raw_rot_i+1; + end + 3'b110: begin + rot_i <= ~raw_rot_q+1; + rot_q <= ~raw_rot_i+1; + end + 3'b111: begin + rot_i <= ~raw_rot_i+1; + rot_q <= ~raw_rot_q+1; + end + endcase + end +end + +endmodule diff --git a/verilog/stage_mult.v b/verilog/stage_mult.v new file mode 100644 index 0000000..f2cf626 --- /dev/null +++ b/verilog/stage_mult.v @@ -0,0 +1,112 @@ +module stage_mult +( + input clock, + input enable, + input reset, + + input signed [15:0] X0, + input signed [15:0] X1, + input signed [15:0] X2, + input signed [15:0] X3, + input signed [15:0] X4, + input signed [15:0] X5, + input signed [15:0] X6, + input signed [15:0] X7, + + + input signed [15:0] Y0, + input signed [15:0] Y1, + input signed [15:0] Y2, + input signed [15:0] Y3, + input signed [15:0] Y4, + input signed [15:0] Y5, + input signed [15:0] Y6, + input signed [15:0] Y7, + + input input_strobe, + + output reg [63:0] sum, + output output_strobe +); + +wire signed [31:0] prod_0_i; +wire signed [31:0] prod_0_q; +wire signed [31:0] prod_1_i; +wire signed [31:0] prod_1_q; +wire signed [31:0] prod_2_i; +wire signed [31:0] prod_2_q; +wire signed [31:0] prod_3_i; +wire signed [31:0] prod_3_q; + +complex_multiplier mult_inst1 ( + .clk(clock), + .ar(X0), + .ai(X1), + .br(Y0), + .bi(Y1), + .pr(prod_0_i), + .pi(prod_0_q) +); + +complex_multiplier mult_inst2 ( + .clk(clock), + .ar(X2), + .ai(X3), + .br(Y2), + .bi(Y3), + .pr(prod_1_i), + .pi(prod_1_q) +); + +complex_multiplier mult_inst3 ( + .clk(clock), + .ar(X4), + .ai(X5), + .br(Y4), + .bi(Y5), + .pr(prod_2_i), + .pi(prod_2_q) +); + +complex_multiplier mult_inst4 ( + .clk(clock), + .ar(X6), + .ai(X7), + .br(Y6), + .bi(Y7), + .pr(prod_3_i), + .pi(prod_3_q) +); + +reg signed [31:0] sum_i1; +reg signed [31:0] sum_i2; +reg signed [31:0] sum_q1; +reg signed [31:0] sum_q2; + +delayT #(.DATA_WIDTH(1), .DELAY(5)) sum_delay_inst ( + .clock(clock), + .reset(reset), + + .data_in(input_strobe), + .data_out(output_strobe) +); + +always @(posedge clock) begin + if (reset) begin + sum <= 0; + sum_i1 <= 0; + sum_i2 <= 0; + sum_q1 <= 0; + sum_q2 <= 0; + end else if (enable) begin + sum_i1 <= prod_0_i + prod_1_i; + sum_i2 <= prod_2_i + prod_3_i; + sum_q1 <= prod_0_q + prod_1_q; + sum_q2 <= prod_2_q + prod_3_q; + + sum[63:32] <= sum_i1 + sum_i2; + sum[31:0] <= sum_q1 + sum_q2; + end +end + +endmodule diff --git a/verilog/sync_long.v b/verilog/sync_long.v new file mode 100644 index 0000000..93c5f7f --- /dev/null +++ b/verilog/sync_long.v @@ -0,0 +1,511 @@ +module sync_long ( + input clock, + input reset, + input enable, + + input set_stb, + input [7:0] set_addr, + input [31:0] set_data, + + input [31:0] sample_in, + input sample_in_strobe, + input signed [31:0] phase_offset, + input short_gi, + + output [`ROTATE_LUT_LEN_SHIFT-1:0] rot_addr, + input [31:0] rot_data, + + output [31:0] metric, + output metric_stb, + output reg long_preamble_detected, + + output reg [31:0] sample_out, + output reg sample_out_strobe, + + output reg [2:0] state +); +`include "common_params.v" + +localparam IN_BUF_LEN_SHIFT = 8; + +localparam NUM_STS_TAIL = 32; + +reg [15:0] in_offset; +reg [IN_BUF_LEN_SHIFT-1:0] in_waddr; +reg [IN_BUF_LEN_SHIFT-1:0] in_raddr; +wire [IN_BUF_LEN_SHIFT-1:0] gi_skip = short_gi? 9: 17; +reg signed [31:0] num_input_produced; +reg signed [31:0] num_input_consumed; +reg signed [31:0] num_input_avail; + +reg [2:0] mult_stage; +reg [1:0] sum_stage; +reg mult_strobe; + +wire signed [31:0] stage_sum_i; +wire signed [31:0] stage_sum_q; + +wire stage_sum_stb; + +reg signed [31:0] sum_i; +reg signed [31:0] sum_q; +reg sum_stb; + +reg signed [31:0] phase_correction; +reg signed [31:0] next_phase_correction; + + +complex_to_mag #(.DATA_WIDTH(32)) sum_mag_inst ( + .clock(clock), + .enable(enable), + .reset(reset), + + .i(sum_i), + .q(sum_q), + .input_strobe(sum_stb), + + .mag(metric), + .mag_stb(metric_stb) +); + +reg [31:0] metric_max1; +reg [(IN_BUF_LEN_SHIFT-1):0] addr1; +reg [31:0] metric_max2; +reg [(IN_BUF_LEN_SHIFT-1):0] addr2; +reg [15:0] gap; + +reg [31:0] match_filter_buf[0:15]; + +reg [31:0] stage_X0; +reg [31:0] stage_X1; +reg [31:0] stage_X2; +reg [31:0] stage_X3; + +reg [31:0] stage_Y0; +reg [31:0] stage_Y1; +reg [31:0] stage_Y2; +reg [31:0] stage_Y3; + +stage_mult stage_mult_inst ( + .clock(clock), + .enable(enable), + .reset(reset), + + .X0(stage_X0[31:16]), + .X1(stage_X0[15:0]), + .X2(stage_X1[31:16]), + .X3(stage_X1[15:0]), + .X4(stage_X2[31:16]), + .X5(stage_X2[15:0]), + .X6(stage_X3[31:16]), + .X7(stage_X3[15:0]), + + .Y0(stage_Y0[31:16]), + .Y1(stage_Y0[15:0]), + .Y2(stage_Y1[31:16]), + .Y3(stage_Y1[15:0]), + .Y4(stage_Y2[31:16]), + .Y5(stage_Y2[15:0]), + .Y6(stage_Y3[31:16]), + .Y7(stage_Y3[15:0]), + + .input_strobe(mult_strobe), + + .sum({stage_sum_i, stage_sum_q}), + .output_strobe(stage_sum_stb) +); + +localparam S_SKIPPING = 0; +localparam S_WAIT_FOR_FIRST_PEAK = 1; +localparam S_WAIT_FOR_SECOND_PEAK = 2; +localparam S_IDLE = 3; +localparam S_FFT = 4; + +reg fft_start; +wire fft_start_delayed; +wire fft_in_stb; +reg fft_loading; +wire signed [15:0] fft_in_re; +wire signed [15:0] fft_in_im; +wire [22:0] fft_out_re; +wire [22:0] fft_out_im; +wire fft_ready; +wire fft_done; +wire fft_busy; +wire fft_valid; + +wire [31:0] fft_out = {fft_out_re[22:7], fft_out_im[22:7]}; + +wire signed [15:0] raw_i; +wire signed [15:0] raw_q; +reg raw_stb; + +ram_2port #(.DWIDTH(32), .AWIDTH(IN_BUF_LEN_SHIFT)) in_buf ( + .clka(clock), + .ena(1), + .wea(sample_in_strobe), + .addra(in_waddr), + .dia(sample_in), + .doa(), + .clkb(clock), + .enb(fft_start | fft_loading), + .web(1'b0), + .addrb(in_raddr), + .dib(32'hFFFF), + .dob({raw_i, raw_q}) +); + +rotate rotate_inst ( + .clock(clock), + .enable(enable), + .reset(reset), + + .in_i(raw_i), + .in_q(raw_q), + .phase(phase_correction), + .input_strobe(raw_stb), + + .rot_addr(rot_addr), + .rot_data(rot_data), + + .out_i(fft_in_re), + .out_q(fft_in_im), + .output_strobe(fft_in_stb) +); + +delayT #(.DATA_WIDTH(1), .DELAY(9)) fft_delay_inst ( + .clock(clock), + .reset(reset), + + .data_in(fft_start), + .data_out(fft_start_delayed) +); + + +xfft_v7_1 dft_inst ( + .clk(clock), + .fwd_inv(1), + .start(fft_start_delayed), + .fwd_inv_we(1), + + .xn_re(fft_in_re), + .xn_im(fft_in_im), + .xk_re(fft_out_re), + .xk_im(fft_out_im), + .rfd(fft_ready), + .done(fft_done), + .busy(fft_busy), + .dv(fft_valid) +); + +reg [15:0] num_sample; +reg [15:0] num_ofdm_symbol; + +integer i; +integer j; +always @(posedge clock) begin + if (reset) begin + for (j = 0; j < 16; j= j+1) begin + match_filter_buf[j] <= 0; + end + do_clear(); + state <= S_SKIPPING; + end else if (enable) begin + if (sample_in_strobe && state != S_SKIPPING) begin + in_waddr <= in_waddr + 1; + num_input_produced <= num_input_produced + 1; + end + num_input_avail <= num_input_produced - num_input_consumed; + + case(state) + S_SKIPPING: begin + // skip the tail of short preamble + if (num_sample >= NUM_STS_TAIL) begin + num_sample <= 0; + state <= S_WAIT_FOR_FIRST_PEAK; + end else if (sample_in_strobe) begin + num_sample <= num_sample + 1; + end + end + + S_WAIT_FOR_FIRST_PEAK: begin + do_mult(); + + if (metric_stb && (metric > metric_max1)) begin + metric_max1 <= metric; + addr1 <= in_raddr - 1; + end + + if (num_sample >= 64) begin + num_sample <= 0; + addr2 <= 0; + state <= S_WAIT_FOR_SECOND_PEAK; + end else if (metric_stb) begin + num_sample <= num_sample + 1; + end + + end + + S_WAIT_FOR_SECOND_PEAK: begin + do_mult(); + + if (metric_stb && (metric > metric_max2)) begin + metric_max2 <= metric; + addr2 <= in_raddr - 1; + end + gap <= addr2 - addr1; + + if (num_sample >= 64) begin + `ifdef DEBUG_PRINT + $display("PEAK GAP: %d (%d - %d)", gap, addr2, addr1); + $display("PHASE OFFSET: %d", phase_offset); + `endif + if (gap > 62 && gap < 66) begin + long_preamble_detected <= 1; + num_sample <= 0; + mult_strobe <= 0; + sum_stb <= 0; + in_raddr <= addr1 - 15; + num_input_consumed <= addr1 - 15; + in_offset <= 0; + num_ofdm_symbol <= 0; + phase_correction <= 0; + next_phase_correction <= phase_offset; + state <= S_FFT; + end else begin + state <= S_IDLE; + end + end else if (metric_stb) begin + num_sample <= num_sample + 1; + end + + end + + S_FFT: begin + if (long_preamble_detected) begin + `ifdef DEBUG_PRINT + $display("Long preamble detected"); + `endif + long_preamble_detected <= 0; + end + + if (~fft_loading && num_input_avail > 64) begin + fft_start <= 1; + in_offset <= 0; + end + + if (fft_start) begin + fft_start <= 0; + fft_loading <= 1; + end + + raw_stb <= fft_start | fft_loading; + if (raw_stb) begin + if (phase_offset > 0) begin + if (next_phase_correction > PI) begin + phase_correction <= next_phase_correction - DOUBLE_PI; + next_phase_correction <= next_phase_correction + phase_offset - DOUBLE_PI; + end else begin + phase_correction <= next_phase_correction; + next_phase_correction <= next_phase_correction + phase_offset; + end + end else begin + if (next_phase_correction < -PI) begin + phase_correction <= next_phase_correction + DOUBLE_PI; + phase_correction <= next_phase_correction + DOUBLE_PI + phase_offset; + end else begin + phase_correction <= next_phase_correction; + phase_correction <= next_phase_correction + phase_offset; + end + end + end + + if (fft_start | fft_loading) begin + in_offset <= in_offset + 1; + + if (in_offset == 63) begin + fft_loading <= 0; + num_ofdm_symbol <= num_ofdm_symbol + 1; + if (num_ofdm_symbol > 0) begin + // skip the Guard Interval for data symbols + in_raddr <= in_raddr + gi_skip; + num_input_consumed <= num_input_consumed + gi_skip; + end else begin + in_raddr <= in_raddr + 1; + num_input_consumed <= num_input_consumed + 1; + end + end else begin + in_raddr <= in_raddr + 1; + num_input_consumed <= num_input_consumed + 1; + end + end + + sample_out_strobe <= fft_valid; + sample_out <= fft_out; + end + + S_IDLE: begin + end + + default: begin + state <= S_WAIT_FOR_FIRST_PEAK; + end + endcase + end else begin + sample_out_strobe <= 0; + end +end + +integer do_mult_i; +task do_mult; begin + // cross correlation of the first 16 samples of LTS + if (sample_in_strobe) begin + match_filter_buf[15] <= sample_in; + for (do_mult_i = 0; do_mult_i < 15; do_mult_i = do_mult_i+1) begin + match_filter_buf[do_mult_i] <= match_filter_buf[do_mult_i+1]; + end + + sum_stage <= 0; + sum_i <= 0; + sum_q <= 0; + sum_stb <= 0; + + stage_X0 <= match_filter_buf[1]; + stage_X1 <= match_filter_buf[2]; + stage_X2 <= match_filter_buf[3]; + stage_X3 <= match_filter_buf[4]; + + stage_Y0[31:16] <= 156; + stage_Y0[15:0] <= 0; + stage_Y1[31:16] <= -5; + stage_Y1[15:0] <= 120; + stage_Y2[31:16] <= 40; + stage_Y2[15:0] <= 111; + stage_Y3[31:16] <= 97; + stage_Y3[15:0] <= -83; + + mult_strobe <= 1; + mult_stage <= 1; + end + + if (mult_stage == 1) begin + stage_X0 <= match_filter_buf[4]; + stage_X1 <= match_filter_buf[5]; + stage_X2 <= match_filter_buf[6]; + stage_X3 <= match_filter_buf[7]; + + stage_Y0[31:16] <= 21; + stage_Y0[15:0] <= -28; + stage_Y1[31:16] <= 60; + stage_Y1[15:0] <= 88; + stage_Y2[31:16] <= -115; + stage_Y2[15:0] <= 55; + stage_Y3[31:16] <= -38; + stage_Y3[15:0] <= 106; + + mult_stage <= 2; + end else if (mult_stage == 2) begin + stage_X0 <= match_filter_buf[8]; + stage_X1 <= match_filter_buf[9]; + stage_X2 <= match_filter_buf[10]; + stage_X3 <= match_filter_buf[11]; + + stage_Y0[31:16] <= 98; + stage_Y0[15:0] <= 26; + stage_Y1[31:16] <= 53; + stage_Y1[15:0] <= -4; + stage_Y2[31:16] <= 1; + stage_Y2[15:0] <= 115; + stage_Y3[31:16] <= -137; + stage_Y3[15:0] <= 47; + + mult_stage <= 3; + end else if (mult_stage == 3) begin + stage_X0 <= match_filter_buf[12]; + stage_X1 <= match_filter_buf[13]; + stage_X2 <= match_filter_buf[14]; + stage_X3 <= match_filter_buf[15]; + + stage_Y0[31:16] <= 24; + stage_Y0[15:0] <= 59; + stage_Y1[31:16] <= 59; + stage_Y1[15:0] <= 15; + stage_Y2[31:16] <= -22; + stage_Y2[15:0] <= -161; + stage_Y3[31:16] <= 119; + stage_Y3[15:0] <= 4; + + mult_stage <= 4; + end else if (mult_stage == 4) begin + mult_stage <= 0; + mult_strobe <= 0; + in_raddr <= in_raddr + 1; + num_input_consumed <= num_input_consumed + 1; + end + + if (stage_sum_stb) begin + sum_stage <= sum_stage + 1; + sum_i <= sum_i + stage_sum_i; + sum_q <= sum_q + stage_sum_q; + if (sum_stage == 3) begin + sum_stb <= 1; + end + end else begin + sum_stb <= 0; + sum_i <= 0; + sum_q <= 0; + end +end +endtask + +task do_clear; begin + gap <= 0; + + in_waddr <= 0; + in_raddr <= 0; + in_offset <= 0; + num_input_produced <= 0; + num_input_consumed <= 0; + num_input_avail <= 0; + + phase_correction <= 0; + next_phase_correction <= 0; + + raw_stb <= 0; + + sum_i <= 0; + sum_q <= 0; + sum_stb <= 0; + sum_stage <= 0; + mult_strobe <= 0; + + metric_max1 <= 0; + addr1 <= 0; + metric_max2 <= 0; + addr2 <= 0; + + mult_stage <= 0; + + long_preamble_detected <= 0; + num_sample <= 0; + num_ofdm_symbol <= 0; + + fft_start <= 0; + fft_loading <= 0; + + sample_out_strobe <= 0; + sample_out <= 0; + + stage_X0 <= 0; + stage_X1 <= 0; + stage_X2 <= 0; + stage_X3 <= 0; + + stage_Y0 <= 0; + stage_Y1 <= 0; + stage_Y2 <= 0; + stage_Y3 <= 0; +end +endtask + +endmodule diff --git a/verilog/sync_short.v b/verilog/sync_short.v new file mode 100644 index 0000000..3cdbd5f --- /dev/null +++ b/verilog/sync_short.v @@ -0,0 +1,251 @@ +`include "common_defs.v" + +module sync_short ( + input clock, + input reset, + input enable, + + input set_stb, + input [7:0] set_addr, + input [31:0] set_data, + + output [31:0] phase_in_i, + output [31:0] phase_in_q, + output phase_in_stb, + input [31:0] phase_out, + input phase_out_stb, + + input [31:0] sample_in, + input sample_in_strobe, + + output reg short_preamble_detected, + output reg signed [31:0] phase_offset +); +`include "common_params.v" + +localparam WINDOW_SHIFT = 4; +localparam DELAY_SHIFT = 4; + +wire [31:0] mag_sq; +wire mag_sq_stb; + +wire [31:0] mag_sq_avg; +wire mag_sq_avg_stb; +reg [31:0] prod_thres; + +wire [31:0] sample_delayed; +wire sample_delayed_stb; + +reg [31:0] sample_delayed_conj; +reg sample_delayed_conj_stb; + +wire [63:0] delay_prod; +wire delay_prod_stb; + +reg [15:0] delay_i; +reg [15:0] delay_q_neg; + +wire [63:0] delay_prod_avg; +wire delay_prod_avg_stb; + +wire [31:0] freq_offset_i; +wire [31:0] freq_offset_q; +wire freq_offset_stb; + +reg [31:0] phase_out_neg; + +wire [31:0] delay_prod_avg_mag; +wire delay_prod_avg_mag_stb; + +reg [31:0] plateau_count; + +// this is to ensure that the short preambles contains both positive and +// negative in-phase, to avoid raise false positives when there is a constant +// power +reg [31:0] pos_count; +reg [31:0] min_pos; +reg has_pos; +reg [31:0] neg_count; +reg [31:0] min_neg; +reg has_neg; + +wire [31:0] min_plateau; + +// minimal number of samples that has to exceed plateau threshold to claim +// a short preamble +setting_reg #(.my_addr(SR_MIN_PLATEAU), .width(32), .at_reset(100)) sr_0 ( + .clk(clock), .rst(reset), .strobe(set_stb), .addr(set_addr), .in(set_data), + .out(min_plateau), .changed()); + + +complex_to_mag_sq mag_sq_inst ( + .clock(clock), + .enable(enable), + .reset(reset), + + .i(sample_in[31:16]), + .q(sample_in[15:0]), + .input_strobe(sample_in_strobe), + + .mag_sq(mag_sq), + .mag_sq_strobe(mag_sq_stb) +); + +moving_avg #(.DATA_WIDTH(32), .WINDOW_SHIFT(WINDOW_SHIFT)) mag_sq_avg_inst ( + .clock(clock), + .enable(enable), + .reset(reset), + + .data_in(mag_sq), + .input_strobe(mag_sq_stb), + .data_out(mag_sq_avg), + .output_strobe(mag_sq_avg_stb) +); + +delay_sample #(.DATA_WIDTH(32), .DELAY_SHIFT(DELAY_SHIFT)) sample_delayed_inst ( + .clock(clock), + .enable(enable), + .reset(reset), + + .data_in(sample_in), + .input_strobe(sample_in_strobe), + .data_out(sample_delayed), + .output_strobe(sample_delayed_stb) +); + +complex_mult delay_prod_inst ( + .clock(clock), + .enable(enable), + .reset(reset), + + .a_i(sample_in[31:16]), + .a_q(sample_in[15:0]), + .b_i(sample_delayed_conj[31:16]), + .b_q(sample_delayed_conj[15:0]), + .input_strobe(sample_delayed_conj_stb), + + .p_i(delay_prod[63:32]), + .p_q(delay_prod[31:0]), + .output_strobe(delay_prod_stb) +); + +moving_avg #(.DATA_WIDTH(32), .WINDOW_SHIFT(WINDOW_SHIFT)) +delay_prod_avg_i_inst ( + .clock(clock), + .enable(enable), + .reset(reset), + .data_in(delay_prod[63:32]), + .input_strobe(delay_prod_stb), + .data_out(delay_prod_avg[63:32]), + .output_strobe(delay_prod_avg_stb) +); + +moving_avg #(.DATA_WIDTH(32), .WINDOW_SHIFT(WINDOW_SHIFT)) +delay_prod_avg_q_inst ( + .clock(clock), + .enable(enable), + .reset(reset), + .data_in(delay_prod[31:0]), + .input_strobe(delay_prod_stb), + .data_out(delay_prod_avg[31:0]) +); + + +// for fixing freq offset +moving_avg #(.DATA_WIDTH(32), .WINDOW_SHIFT(6)) +freq_offset_i_inst ( + .clock(clock), + .enable(enable), + .reset(reset), + .data_in(delay_prod[63:32]), + .input_strobe(delay_prod_stb), + .data_out(phase_in_i), + .output_strobe(phase_in_stb) +); + +moving_avg #(.DATA_WIDTH(32), .WINDOW_SHIFT(6)) +freq_offset_q_inst ( + .clock(clock), + .enable(enable), + .reset(reset), + .data_in(delay_prod[31:0]), + .input_strobe(delay_prod_stb), + .data_out(phase_in_q) +); + +complex_to_mag #(.DATA_WIDTH(32)) delay_prod_avg_mag_inst ( + .clock(clock), + .reset(reset), + .enable(enable), + + .i(delay_prod_avg[63:32]), + .q(delay_prod_avg[31:0]), + .input_strobe(delay_prod_avg_stb), + .mag(delay_prod_avg_mag), + .mag_stb(delay_prod_avg_mag_stb) +); + +always @(posedge clock) begin + if (reset) begin + sample_delayed_conj <= 0; + sample_delayed_conj_stb <= 0; + + pos_count <= 0; + min_pos <= 0; + has_pos <= 0; + + neg_count <= 0; + min_neg <= 0; + has_neg <= 0; + + prod_thres <= 0; + + plateau_count <= 0; + short_preamble_detected <= 0; + phase_offset <= 0; + end else if (enable) begin + sample_delayed_conj_stb <= sample_delayed_stb; + sample_delayed_conj[31:16] <= sample_delayed[31:16]; + sample_delayed_conj[15:0] <= ~sample_delayed[15:0]+1; + + min_pos <= min_plateau>>2; + min_neg <= min_plateau>>2; + has_pos <= pos_count > min_pos; + has_neg <= neg_count > min_neg; + + phase_out_neg <= ~phase_out + 1; + + prod_thres <= {1'b0, mag_sq_avg[31:1]} + {2'b0, mag_sq_avg[31:2]}; + + if (delay_prod_avg_mag_stb) begin + if (delay_prod_avg_mag > prod_thres) begin + if (sample_in[31]) begin + neg_count <= neg_count + 1; + end else begin + pos_count <= pos_count + 1; + end + if (plateau_count > min_plateau) begin + plateau_count <= 0; + pos_count <= 0; + neg_count <= 0; + short_preamble_detected <= has_pos & has_neg; + phase_offset <= {{4{phase_out_neg[31]}}, phase_out_neg[31:4]}; + end else begin + plateau_count <= plateau_count + 1; + short_preamble_detected <= 0; + end + end else begin + plateau_count <= 0; + pos_count <= 0; + neg_count <= 0; + short_preamble_detected <= 0; + end + end else begin + short_preamble_detected <= 0; + end + end else begin + short_preamble_detected <= 0; + end +end + +endmodule diff --git a/verilog/usrp2/ram_2port.v b/verilog/usrp2/ram_2port.v new file mode 100644 index 0000000..734365b --- /dev/null +++ b/verilog/usrp2/ram_2port.v @@ -0,0 +1,66 @@ +// +// Copyright 2011 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . +// + + + +module ram_2port +#( + parameter DWIDTH=32, + parameter AWIDTH=9 +) +( + input clka, + input ena, + input wea, + input [AWIDTH-1:0] addra, + input [DWIDTH-1:0] dia, + output reg [DWIDTH-1:0] doa, + + input clkb, + input enb, + input web, + input [AWIDTH-1:0] addrb, + input [DWIDTH-1:0] dib, + output reg [DWIDTH-1:0] dob +); + +reg [DWIDTH-1:0] ram [(1<. +// + + + +module setting_reg + #(parameter my_addr = 0, + parameter width = 32, + parameter at_reset=32'd0) + (input clk, input rst, input strobe, input wire [7:0] addr, + input wire [31:0] in, output reg [width-1:0] out, output reg changed); + + always @(posedge clk) + if(rst) + begin + out <= at_reset; + changed <= 1'b0; + end + else + if(strobe & (my_addr==addr)) + begin + out <= in; + changed <= 1'b1; + end + else + changed <= 1'b0; + +endmodule // setting_reg diff --git a/verilog/viterbi.v b/verilog/viterbi.v new file mode 100644 index 0000000..12b7579 --- /dev/null +++ b/verilog/viterbi.v @@ -0,0 +1,31 @@ +/* +* A wrapper of Xilinx Viterbi IP core +* Added strobe signal. +*/ +module viterbi +( + input clock, + input enable, + input reset, + + input [2:0] sym0, + input [2:0] sym1, + input [1:0] erase, + input input_strobe, + + output out_bit, + output output_strobe +); + +viterbi_v7_0 viterbi_inst ( + .clk(clock), + .ce(reset | (enable & input_strobe)), + .sclr(reset), + .data_in0(sym0), + .data_in1(sym1), + .erase(erase), + .rdy(output_strobe), + .data_out(out_bit) +); + +endmodule diff --git a/verilog/xilinx_viterbi_tb.v b/verilog/xilinx_viterbi_tb.v new file mode 100644 index 0000000..deb4a4b --- /dev/null +++ b/verilog/xilinx_viterbi_tb.v @@ -0,0 +1,125 @@ +module viterbi_tb; + +reg clock; +reg reset; +reg enable; + +localparam RAM_SIZE = 1<<25; +reg encoded_data [0:RAM_SIZE-1]; +reg [31:0] encoded_data_addr; + +reg decoded_data [0:RAM_SIZE-1]; +reg [31:0] decoded_data_addr; + +wire expected = decoded_data[decoded_data_addr]; + +reg [31:0] input_count; + + +localparam ENCODED_DATA_FILE = "./test_in/conv_encoded_data.txt"; +localparam DECODED_DATA_FILE = "./test_in/conv_decoded_data.txt"; + +reg clr; +reg sym0; +reg sym1; + +reg [31:0] error_count; + +wire [15:0] ber; +wire ber_done; +wire data_out; +wire rdy; + +viterbi_v7_0 viterbi_inst ( + .clk(clock), + .ce(1), + .sclr(clr), + .data_in0(sym0), + .data_in1(sym1), + .rdy(rdy), + .data_out(data_out) +); + +initial begin + $dumpfile("xilinx_viterbi_tb.vcd"); + $dumpvars; + + $display("Reading memory from %s ...", ENCODED_DATA_FILE); + $readmemb(ENCODED_DATA_FILE, encoded_data); + $readmemb(DECODED_DATA_FILE, decoded_data); + $display("Done."); + + clock = 0; + reset = 1; + enable = 0; + clr = 1; + + # 100 reset = 0; + # 100 enable = 1; + + # 20000 $finish; +end + + +always begin + #1 clock = !clock; +end + +localparam S_INPUT = 0; +localparam S_FLUSH = 1; + +reg [3:0] state; + +localparam BITS_TO_DECODE = 48*6+48; + + +always @(posedge clock) begin + if (reset) begin + sym0 <= 0; + sym1 <= 0; + input_count <= 0; + + error_count <= 0; + + encoded_data_addr <= 0; + decoded_data_addr <= 0; + state <= S_INPUT; + end else if (enable) begin + clr <= 0; + case(state) + S_INPUT: begin + if (input_count < BITS_TO_DECODE) begin + sym0 <= encoded_data[encoded_data_addr]; + sym1 <= encoded_data[encoded_data_addr+1]; + encoded_data_addr <= encoded_data_addr + 2; + input_count <= input_count + 2; + end else begin + sym0 <= 0; + sym1 <= 0; + state <= S_FLUSH; + end + end + + S_FLUSH: begin + end + endcase + + if (rdy) begin + $display("%d\t%d\t%d\t%d", decoded_data_addr, expected, data_out, error_count); + if (data_out != expected) begin + error_count <= error_count + 1; + if (error_count > 500) begin + $display("too many errors."); + $finish; + end + end + if (decoded_data_addr >= BITS_TO_DECODE/2) begin + $finish; + end else begin + decoded_data_addr <= decoded_data_addr + 1; + end + end + end +end + +endmodule